Patent Description:
Deeply etched micro-optical benches are typically formed using a Deep Reactive Ion Etching (DRIE) process on Silicon On Insulator (SOI) wafers in order to produce microoptical and Micro-Electro-Mechanical Systems (MEMS) components that are able to process free-space optical beams propagating parallel to the SOI substrate. Conventionally, a one-level shadow mask is used to provide step coverage and selective metallization or thin film coating of optical surfaces within deeply etched micro-optical benches. Example of in-plane surfaces coating is described in documents <CIT> and <CIT>.

However, protection of nearby optical surfaces from thin film coating requires separating the coated and non-coated surfaces by a sufficient distance to avoid inadvertent coating of non-coated surfaces. Therefore, the optical propagation distance within microoptical bench devices is limited to the design rules of the shadow mask.

<FIG> illustrates an exemplary prior art one-level shadow mask <NUM> for use in metallizing etched surfaces of a substrate <NUM>, such as a Silicon On Insulator (SOI) wafer/substrate. The substrate <NUM> includes a device layer <NUM>, an etch stop or sacrificial (e.g., buried oxide (BOX)) layer <NUM> and a handle layer <NUM>. Various micro-fabricated structures (e.g., structures <NUM> and <NUM>) of a micro-optical bench device <NUM> are etched into the device layer <NUM> using, for example, a DRIE Bosch process, to expose micro-optical surfaces <NUM> and <NUM>. To sputter a coating material <NUM> (e.g., metal layer) on one of the surfaces (e.g., surface <NUM>), an opening in the shadow mask of width Lm is required, assuming a metallization angle, θm. From geometry, the metallization opening width is given by: <MAT> where M, h and D<NUM> are the misalignment margin, the SOI device layer height and the shadow mask thickness, respectively.

To protect an opposite micro-optical surface (e.g., surface <NUM>) from being metallized, a protection distance Lp from the metallization opening is required. The protection distance is directly proportional to the metallization opening width and device layer height, and is given by: <MAT> Where D<NUM> is the thickness of the shadow mask excluding recessed part above the SOI wafer. Thus, the total distance between a metallized surface <NUM> and a protected surface <NUM> is given by: <MAT>.

From the above equations, it can be deduced that increasing the device layer height, which may be required for better optical coupling efficiency, directly affects the minimum optical propagation distance that can be achieved using a one-level shadow mask for metallization or thin film coating of vertical micro-optical surfaces. On the other hand, increasing the thickness of the one-level shadow mask increases the required metallization opening, while at the same time reduces the protection distance.

Documents <CIT>, <CIT> and <CIT> disclose coating methods that remain unsatisfactory.

Therefore, what is needed is a shadow mask designed to provide selective step coverage of micro-fabricated structures within a micro-optical bench device with minimal protection distance between optical surfaces.

Various aspects of the present disclosure provide a shadow mask for use in selectively coating micro-fabricated structures within a micro-optical bench device. The shadow mask includes a first opening within a top surface of the shadow mask and a second opening within a bottom surface of the shadow mask. The second opening is aligned with the first opening and has a second width less than a first width of the first opening. An overlap between the first opening and the second opening forms a hole within the shadow mask through which selective coating of micro-fabricated structures within the micro-optical bench device may occur.

The present invention is directed to a method and a shadow mask for selective coating of out-of-plane surfaces of micro-fabricated structures within a device, the main and subsidiaries aspects of which are defined by the appended claims. Embodiments and examples in the following description which are not covered by the appended claims are considered as being not part of the present invention, and are merely provided for the purpose of understanding.

A more complete understanding of the present invention may be obtained by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:.

In accordance with aspects of the present disclosure, selective metallization or thin film coating of optical surfaces of micro-fabricated structures within micro-optical bench devices is performed using two or more levels of openings in a shadow mask, placed above the micro-optical bench device. The multi-level shadow mask enables forming optical mirrors in Silicon-On-Insulator SOI wafers with smaller bench foot print (i.e., reduced optical propagation distance) and controlled thin firm coating of the micro-optical components inside the micro-optical bench device. The size and shape of the top level shadow mask openings are used to control the profile and thickness of the deposited thin film. The second level shadow mask openings are used to control the spread of the deposition and to protect the surfaces that are not to be coated. The multi-level shadow mask may further improve the uniformity of coating from one optical surface to another inside a single micro-optical bench device and across a wafer containing multiple micro-optical bench devices before singulation of the wafer.

<FIG> illustrates an exemplary multi-level shadow mask <NUM> for use in providing selective step coverage for micro-fabricated structures within a micro-optical bench device <NUM>, in accordance with aspects of the present disclosure. The micro-optical bench device <NUM> is fabricated within a substrate <NUM>, such as a Silicon On Insulator (SOI) wafer/substrate. The substrate <NUM> includes a device layer <NUM>, an etch stop or sacrificial (e.g., buried oxide (BOX)) layer <NUM> and a handle layer <NUM>. Various micro-fabricated structures (e.g., structures <NUM> and <NUM>) of the micro-optical bench device <NUM> are etched into the device layer <NUM> using, for example, a DRIE Bosch process, to expose optical surfaces <NUM> and <NUM> thereof. As shown in <FIG>, the etched optical surfaces <NUM> and <NUM> are out-of-plane with respect to the substrate <NUM> and may be vertical or at an inclination angle with respect to the plane of the substrate <NUM>.

The shadow mask <NUM> may be, for example, formed of a silicon (Si) substrate or other type of substrate (e.g., plastic, glass, etc.) that has a top surface <NUM> and a bottom surface <NUM>. The multiple levels of the shadow mask <NUM> are formed using two or more openings therein. For example, as shown in <FIG>, the shadow mask <NUM> includes a first opening <NUM> within the top surface <NUM> of the shadow mask <NUM> and a second opening <NUM> within the bottom surface <NUM> of the shadow mask <NUM>. The second opening <NUM> is aligned with the first opening <NUM> and has a width Lmb that is less than the width Lm of the first opening <NUM>. The overlap between the widths of the first and second openings <NUM> and <NUM> forms a hole <NUM> within the shadow mask <NUM> that extends through the top and bottom surfaces <NUM> and <NUM> thereof. Although not shown, it should be understood that additional openings between the first and second openings <NUM> and <NUM> may also be included within the shadow mask.

A recessed portion <NUM> of the shadow mask <NUM> provides a gap between the shadow mask <NUM> and the moving/fragile micro-fabricated structures <NUM> and <NUM> within the micro-optical bench device <NUM>. By having different widths for the first and second opening <NUM> and <NUM>, a protection lip <NUM> may be formed within the shadow mask <NUM>, in which the width of the protection lip <NUM> corresponds to a difference between the first width Lm of the first opening <NUM> and the second width Lmb of the second opening <NUM>. The protection lip <NUM> enables protection of a surface <NUM> during deposition of the coating material (i.e., metal layer) on an opposing surface <NUM>.

As can be seen in <FIG>, there are three different shadow mask levels, denoted by D<NUM>, D<NUM> and D<NUM>. The first level D<NUM> of the shadow mask <NUM> includes the thickness of the shadow mask <NUM> less the recessed portion <NUM> and corresponds to the depth of the hole <NUM>. The second level D<NUM> of the shadow mask <NUM> includes the total thickness of the shadow mask <NUM> including the recessed portion <NUM>. The third level D<NUM> of the shadow mask <NUM> includes the thickness of the shadow mask <NUM> corresponding to the depth of the second opening <NUM>, in which D<NUM> is much smaller than D<NUM>. Thus, the third level D<NUM> of the shadow mask <NUM> extends from the recessed bottom surface <NUM> of the shadow mask <NUM> through the depth of the second opening <NUM>. In addition, the first opening <NUM> extends from the top surface <NUM> of the shadow mask <NUM> through a thickness corresponding to a difference between D<NUM> and D<NUM>. Furthermore, the protection lip <NUM> is formed within the third level D<NUM> of the shadow mask <NUM>.

The different levels are designed to expose some optical surfaces (e.g., surface <NUM>), while at the same time protect other optical surfaces (e. g, surface <NUM>) within the micro-optical bench device <NUM>. Thus, these levels represent the control parameters for selective metallization or thin film coating of the micro-optical bench device <NUM>. By optimizing these levels, smaller micro-fabricated structures <NUM> and <NUM> with shorter optical propagation distances therebetween can be achieved. In addition, optimization of the levels may further control the optical quality of the micro-mirrors and optical interfaces within the micro-optical bench device <NUM>. Consequently, the multi-level shadow mask <NUM> enhances the optical efficiency of the micro-optical bench device <NUM>.

In an aspect of the disclosure, the distance between a surface to be metallized/coated (e.g., surface <NUM>) and a surface to be protected from metallization/thin film coating (e.g., surface <NUM>) may be minimized by controlling the shadow mask levels. For example, the width of the top level opening <NUM> may be the same as that shown in <FIG>, and thus, given by Equation <NUM>. However, by having a shadow mask with large thickness D<NUM>, while still offering the same metallization properties through the second level of thickness D<NUM>, the protection distance Lp, may be reduced as indicated in the following equation: <MAT> In addition, the total distance Lt between the metallized surface <NUM> and the protected surface <NUM> may be given by: <MAT>.

Using a shadow mask thickness twice as large as the conventional shadow mask thickness D<NUM>, such that D<NUM>=<NUM>D<NUM>, and using D<NUM>=D<NUM>/<NUM>, the total optical propagation distance (Lt) may be reduced to half of the value when using the conventional shadow mask. Further reduction may also be achieved by further increases in D<NUM> and/or decreases in D<NUM>.

The thickness and profile of the coating material <NUM> (i.e., metal layer) deposited on the optical surface <NUM> may be controlled by the sputtering time and the top opening width Lm, while the spread of the metal on the substrate (≈Lt) may be controlled by the bottom opening width Lmb, which is given by: <MAT>.

Thus, the sputtered metal thickness profile and maximum thickness value may be controlled by the shadow mask opening shape and profile, respectively, as shown in <FIG>. The shape of the shadow mask top opening g(x,y) controls the profile shape of the sputtered thin film t(x,y). By changing the opening size from Lm1 to Lm2. to Lm4, the maximum achievable thickness is controlled from t<NUM> to t<NUM>. to t<NUM>, as shown in <FIG>. If the opening size is smaller than a given threshold value Lm-th, the sputtering thickness will be negligible. This threshold value is controlled by the process conditions, including the distance between the target and the wafer in the reactor, biasing power and the sputtering gas. In addition, the threshold value depends on the overall thickness of the shadow mask used. An example experimental dependence of the thin firm thickness on the opening size is shown in <FIG>. For large opening size, the thickness saturates a certain value. This value is controlled by the process time and process conditions.

Referring now to <FIG>, the shadow mask <NUM> may have different opening sizes simultaneously leading to different metallization or thin film thickness. This may enable, for example, the formation of fully reflective mirrors 282b and partially reflective/transmitting mirrors 280a with controlled transmission. In the example shown in <FIG>, there are two different top level openings 205a and 205b in the shadow mask <NUM>, each with a different width Lm1 and Lm2. The different top level opening sizes lead to two different thin film thicknesses t<NUM> and t<NUM> on the coated optical surfaces 280a and 280b of micro-fabricated structures 282a and 282b. If the thin film <NUM> is metal, the coated surfaces 280a and 280b may have different reflectivity and transmission characteristics, depending on the metal thickness with respect to the optical skin depth at the given wavelength of the light propagating in the micro-optical bench <NUM>. If one or both of the metallized surfaces 280a and 280b coating thickness is much larger than the skin depth, then the surface (e.g., surface 280b) will act as a fully reflecting surface with the respect to the incident light.

The widths of the bottom level openings 210a and 210b may be the same or different. For example, the widths of the bottom level openings 210a and 210b may be selected to provide protection to other surfaces 290a and 290b within the micro-optical bench device <NUM> during deposition of the coating material <NUM> on coated surfaces 280a and 280b.

Referring now to <FIG>, both uniform and non-uniform step coverage may be achieved using the multi-level shadow mask <NUM>. For example, the shadow mask top level and bottom level opening sizes <NUM> and <NUM>, respectively, along with the process conditions, may be optimized to produce either uniform coating across the height of the optical surface <NUM>, as shown in <FIG>, or non-uniform coating, as shown in <FIG>. The non-uniform coating can lead to, for example, a wedge shape of the coating material <NUM>, as can be seen in <FIG>.

Referring now to <FIG>, to simultaneously control the thin film thickness on multiple optical surfaces 280a and 280b of the micro-optical bench device <NUM>, the shadow mask <NUM> may include a single large top level opening <NUM> overlapping two or more bottom level openings 210a and 210b. In one example, the top level opening <NUM> may provide the same thin film thickness on both optical surfaces 280a and 280b of the micro-optical bench device <NUM>. The bottom level openings 210a and 210b may be used to control the spread of the thin film material <NUM> and to protect other non-coated surfaces 290a and 290b.

<FIG> illustrates an exemplary shadow mask <NUM> including spacers <NUM> between the shadow mask <NUM> and the substrate <NUM>, in accordance with aspects of the present disclosure. The spacers <NUM> may control the thin film thickness across the wafer and prevent stress on the shadow mask <NUM>, thus preventing bending of the shadow mask <NUM>. The spacers <NUM> may be distributed between the shadow mask <NUM> and the substrate/wafer <NUM> before singulation. In one example, the spacers <NUM> may be distributed in the bottom level (i.e., recessed portion) of the shadow mask <NUM> and may be etched in the shadow mask using a photolithographic mask on the bottom surface of the shadow mask <NUM>. The spacers <NUM> may be positioned in the bottom level so as to not overlap with the moving/fragile micro-fabricated structures <NUM> in the micro-optical bench device <NUM>. The stoppers <NUM> may maintain a nearly constant gap between the recessed bottom surface of the shadow mask <NUM> and the top surface of the substrate <NUM>, and thus, may improve uniformity of metallization across the substrate/wafer <NUM>.

<FIG> is a top view of a layout of an exemplary multi-level shadow mask <NUM>, in accordance with aspects of the present disclosure. In the example shown in <FIG>, the bottom level opening <NUM> can be seen through the top level opening <NUM> in the shadow mask <NUM>. The bottom level opening <NUM> includes several sub-openings 210a-210d aligned in different directions to produce the desired thin film coating on the micro-optical bench device <NUM> (shown as a dotted line). The micro-optical bench device <NUM> shown in <FIG> forms at least a part of an optical interferometer including a micro-mirror to be metallized and an interface (e.g., a beam splitter) to be protected from metallization.

For example, one sub-opening (e.g., sub-opening 210a) may be designed to minimize the opening size in the direction connecting the micro-mirror surface <NUM> to be metallized and the interface surface <NUM> to be protected. Another sub-opening (e.g., sub-opening 210b) may be designed to maximize the opening in a tilted direction with respect to the line connecting the micro-mirror surface <NUM> and the interface surface <NUM>. Thus, as can be seen in <FIG>, the bottom level opening <NUM> may include a union of at least one rectangular shape and at least one parallelogram shape, where the parallelogram shape forms an opening that is tilted with respect to the rectangular shape.

An example of a spectrometer including an interferometer that may be fabricated as a micro-optical bench device is shown in <FIG>. In the example shown in <FIG>, the spectrometer <NUM> includes a Michelson interferometer <NUM>. However, in other examples, other types of interferometers, such as Fabry-Perot and Mach-Zehnder interferometers, may be utilized. In <FIG>, collimated light I<NUM> from a broadband source <NUM> is split into two beams I<NUM> and I<NUM> by a beam splitter <NUM>. One beam I<NUM> is reflected off a fixed mirror <NUM> and the other beam I<NUM> is reflected off a moving mirror <NUM> coupled to an actuator <NUM>, such as a MEMS actuator. It should be noted that the (light) coupling efficiency of the interferometer <NUM> may be maximized by optimizing the step coverage uniformity of the metal layer along the height of the fixed and moveable mirrors <NUM> and <NUM> using a multi-level shadow mask <NUM>, as discussed above.

In one example, the MEMS actuator <NUM> is formed of a comb drive and spring. By applying a voltage to the comb drive, a potential difference results across the actuator <NUM>, which induces a capacitance therein, causing a driving force to be generated as well as a restoring force from the spring, thereby causing a displacement of moveable mirror <NUM> to the desired position for reflection of the beam L<NUM>. An optical path length difference (OPD) is then created between the reflected beams that is substantially equal to twice the mirror <NUM> displacement.

The reflected beams interfere at the beam splitter <NUM>, allowing the temporal coherence of the light to be measured at each different Optical Path Difference (OPD) offered by the moving mirror. The signal, called the interferogram, is measured by a detector <NUM> at many discrete positions of the moving mirror. The spectrum may then be retrieved, for example, using a Fourier transform carried out by a processor <NUM>.

The processor <NUM> may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processor <NUM> may have an associated memory and/or memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of the processor. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information.

<FIG> is a flowchart illustrating an exemplary method <NUM> for selective coating of micro-fabricated structures within a micro-optical bench device using a multi-level shadow mask, in accordance with aspects of the present disclosure. The method <NUM> begins at block <NUM> by providing a substrate including micro-fabricated structures forming a micro-optical bench device. At block <NUM>, a multi-level shadow mask is provided that includes a first opening within a top surface of the shadow mask and a second opening within a bottom surface of the shadow mask. The second opening is aligned with the first opening and has a width less than the width of the first opening, such that an overlap between the first opening and the second opening form a hole within the shadow mask.

At block <NUM>, the shadow mask is placed on the substrate in a position to enable a surface of a micro-fabricated structure to be coated through the hole. In particular, the bottom surface of the shadow mask is placed adjacent to a top surface of the substrate and the micro-fabricated structure surface to be coated is aligned with the hole. At block <NUM>, a coating material, such as a metal layer, is deposited on the surface of the micro-fabricated structure through the hole.

<FIG> illustrate an exemplary process for fabricating a multi-level shadow mask <NUM>, in accordance with aspects of the present disclosure. As shown in <FIG>, a substrate <NUM> for the shadow mask is provided and a recess pattern <NUM> is formed on a bottom surface <NUM> of the substrate <NUM> through a lithography step. The recess pattern <NUM> may be formed, for example, by depositing a layer of aluminum on the bottom surface <NUM> of the substrate <NUM> and patterning the layer of aluminum to form the recess pattern <NUM>. Then, as shown in <FIG>, a layer of photo-resist <NUM> is deposited on the bottom surface <NUM> of the substrate <NUM> and patterned to form a bottom opening pattern. In <FIG>, the bottom opening <NUM> is etched in the substrate <NUM> through the bottom opening pattern for a predefined depth.

In <FIG>, another layer of photo-resist <NUM> is deposited on the top surface <NUM> of the substrate <NUM> and patterned to form a top opening pattern. In <FIG>, the top opening <NUM> is etched in the substrate <NUM> through the top opening pattern until the top opening <NUM> meets the bottom opening <NUM>, and a hole <NUM> forms in the substrate <NUM>. Finally, as shown in <FIG>, the shadow mask recess portion <NUM> is etched using the recess pattern <NUM> to ensure the shadow mask <NUM> does not come into contact with any movable/fragile micro-fabricated structures while using the shadow mask for step coverage.

Claim 1:
A method for selective coating of out-of-plane surfaces of micro-fabricated structures within a device, comprising:
providing a substrate (<NUM>) including the micro-fabricated structures;
providing a shadow mask (<NUM>) including a first opening (<NUM>) within a top surface (<NUM>) of the shadow mask (<NUM>) and a second opening (<NUM>) within a bottom surface (<NUM>) of the shadow mask (<NUM>), wherein the second opening (<NUM>) is aligned with the first opening (<NUM>) and has a second width (Lmb) less than a first width (Lm) of the first opening (<NUM>), a first overlap between the first opening (<NUM>) and the second opening (<NUM>) forming a first hole (<NUM>) within the shadow mask (<NUM>);
placing the shadow mask (<NUM>) on the substrate (<NUM>) such that the bottom surface (<NUM>) of the shadow mask (<NUM>) faces the substrate (<NUM>); and
depositing a coating material (<NUM>) on a first surface (<NUM>) of a first micro-fabricated structure (<NUM>) through the first hole (<NUM>), the first surface (<NUM>) being out-of-plane with respect to the substrate (<NUM>);
wherein the shadow mask (<NUM>) is a multi-level shadow mask comprising a first thickness (D1) corresponding to a first depth of the first hole (<NUM>), a second thickness (D2) greater than the first thickness (D1) and corresponding to a total thickness of the shadow mask (<NUM>), and a third thickness (D3) less than the first thickness (D1) and corresponding to a second depth of the second opening (<NUM>);
wherein the third thickness (D3) extends from the bottom surface (<NUM>) of the shadow mask (<NUM>); and
wherein the first opening (<NUM>) extends from the top surface (<NUM>) through a fourth thickness corresponding to a difference between the first thickness (D1) and the third thickness (D3);
characterized in that the step of providing the shadow mask further comprises forming a protection lip (<NUM>) along the bottom surface (<NUM>) of the shadow mask (<NUM>), the protection lip (<NUM>) having a third width corresponding to a difference between the first width (Lm) of the first opening (<NUM>) and the second width (Lmb) of the second opening (<NUM>);
wherein a sidewall of the hole extends through the first thickness (D1) by alignment of the first opening (<NUM>) and the second opening (<NUM>) on one side of the hole; and
wherein the third thickness (D3) forms a protection lip (<NUM>) on only the other side of the hole opposite the sidewall.