Patent Description:
This disclosure relates generally to the field of reference voltage generation, and, in particular, to a precision bandgap reference with trim adjustment.

A reference voltage in electronic circuits is a signal at a fixed voltage value which may be used for calibration purposes. That is, other signals may be compared with the reference voltage, or other signals may be generated from the reference voltage. The reference voltage should have high stability (i.e., robustness against environmental change) and good accuracy (i.e., small difference relative to a desired voltage value). A bandgap reference voltage source generates a reference voltage that is substantially constant over a defined voltage supply and temperature range. Integrated circuit (IC) applications often rely on the accuracy of this reference to allow the highest possible system performance. However, bandgap reference voltage references are subject to tolerance error due to an imperfect silicon fabrication process which can alter the individual device parameters of the transistors and resistors which comprise the bandgap reference. Hence, a trimming procedure is required to mitigate these inaccuracies and restore the accuracy of the bandgap reference.

Attention is drawn to document <CIT> which relates to a trimmable bandgap voltage reference circuit which includes variable current sources to drive variable currents through parallel combination circuits. The parallel combination circuits include variable resistors and diodes of differing sizes. Voltages developed across the parallel combination circuits are input to a differential amplifier that is used as a feedback amplifier to bias the variable current sources. The variable current sources and variable resistors can all be digitally controlled. A processor can query the operating point of the bandgap voltage reference circuit, and can also set the current and resistance values through a control circuit.

Further attention is drawn to document <CIT> which relates to a collector and a base of a first, a second transistors which are each short circuited. The second transistor has a current density larger than that of the first transistor. A first resistor is connected between the emitter of the first transistor and a ground potential node. One end of a second resistor is connected to the first transistor. One end of a third resistor is connected to the second transistor. The other end of the third resistor is connected commonly to the other end of the second resistor. An operational amplifier circuit has an inverting input terminal connected to the one end of the second resistor and a non-inverting input terminal connected to the one end of the third resistor. A reference voltage regulating output circuit is inserted between the output terminal of the operational amplifier circuit and the other ends of the second, the third resistors.

The invention is defined by the appended independent claim <NUM>. Further embodiments of the invention are defined by the appended dependent claims.

These and other aspects of the disclosure will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and implementations of the present disclosure will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary implementations of the present invention in conjunction with the accompanying figures. While features of the present invention may be discussed relative to certain implementations and figures below, all implementations of the present invention can include one or more of the advantageous features discussed herein. In other words, while one or more implementations may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various implementations of the invention discussed herein. In similar fashion, while exemplary implementations may be discussed below as device, system, or method implementations it should be understood that such exemplary implementations can be implemented in various devices, systems, and methods.

While for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.

The present disclosure discloses a bandgap reference voltage circuit for producing a reference voltage which minimizes tolerance error due to device mistracking. It is also desirable that the reference voltage be stable against environmental conditions and over time. Also, it is desirable that the reference voltage be accurate; that is, its voltage value should be close to a desired voltage value. Integrated circuits (IC) such as a system on a chip (SOC) may require a reference voltage with high stability and good accuracy for internal circuit usage. In one aspect, obtaining such a reference voltage may be achieved by using a bandgap reference voltage. In one aspect, the bandgap reference voltage relies on semiconductor physics, specifically on the <NUM> eV bandgap voltage of silicon at zero degrees Kelvin (<NUM>), to provide a well-defined reference voltage for electronic circuits. In one example, the bandgap reference voltage may be generated by combining (e.g., summing) a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage-.

<FIG> illustrates a first example of a voltage circuit <NUM> with trimming. The voltage circuit <NUM> includes an op amp <NUM>, a transistor <NUM>, a cascaded resistor network <NUM> and a plurality of switches <NUM>. In one example, the op amp <NUM> has a reference voltage VREF supplied to an inverting (minus) terminal <NUM> and a feedback voltage supplied to a non-inverting (plus) terminal <NUM>. An output <NUM> of the op amp <NUM> is supplied to a gate terminal <NUM> of a transistor <NUM>. A bias voltage VDD <NUM> is supplied to a source terminal <NUM> of the transistor <NUM> and a drain terminal <NUM> of the transistor <NUM> is connected to a cascaded resistor network <NUM>.

In one example, the cascaded resistor network <NUM> is includes a plurality of resistors connected in series: R<NUM>n <NUM>, R<NUM>n-<NUM> <NUM>,. , R<NUM> <NUM>, R<NUM> <NUM>. Although in the example of <FIG>, four resistors are explicitly shown in the cascaded resistor network <NUM>, one skilled in the art would understand that the quantity of the resistors is not limiting and the more or less quantity of resistors in the cascaded resistor network <NUM> is within the scope and spirit of the present disclosure.

In addition, each resistor includes one terminal connected to a switch, wherein the switch is part of a plurality of switches <NUM> denoted as SW<NUM>n <NUM>, SW<NUM>n-<NUM> <NUM>,. SW<NUM> <NUM>, SW<NUM><NUM>. In one example, each of the plurality of switches <NUM> may be used to engage or disengage each resistor of the cascaded resistor network <NUM> for contributing to the feedback voltage. In one example, the plurality of switches <NUM> is used to provide trimming of the reference voltage.

<FIG> illustrates a second example of a voltage circuit <NUM> with trimming. In one example, the voltage circuit <NUM> includes a trim circuit <NUM>. In one example, the trim circuit <NUM> uses a first current source <NUM> as an input to a resistor R2 <NUM> and a second current source <NUM> as an output from resistor R2 <NUM>.

<FIG> illustrates an example of a bandgap voltage reference circuit <NUM> which incorporates negative feedback loop circuit for generating a reference voltage. In one example, the bandgap voltage reference circuit includes a differential error amplifier <NUM>, a transconductance (e.g., voltage input, current output) gain stage <NUM>, a first resistor branch <NUM>, a second resistor branch <NUM>, and a diode array (DARRAY) <NUM>. In one example, the first resistor branch <NUM> and the second resistor branch <NUM> form a two-parallel resistor branches.

In one example, the differential error amplifier <NUM> (e.g., operational amplifier) provides a voltage Vout <NUM> which is proportional to a difference voltage between a first amplifier input fbp <NUM> and a second amplifier input fbn <NUM>. In one example, the differential error amplifier <NUM> has an open loop gain G from the difference voltage to the amplifier output Vout <NUM>. For example, the amplifier output may be expressed as Vout = G(fbp - fbn).

In one example, the differential error amplifier <NUM> is part of the bandgap voltage reference circuit <NUM> which incorporates negative feedback, where the differential error amplifier <NUM> accepts two inputs, the first amplifier input fbp <NUM> from a first resistor branch and the second amplifier input fbn <NUM> from a second resistor branch. The output <NUM> of the differential error amplifier <NUM> provides a voltage to the input of a transconductance gain stage <NUM>, which in turn provides bias current equally to the two resistors branches, the first resistor branch <NUM> and the second resistor branch <NUM>, using current outputs <NUM> and <NUM>. The transconductance gain corresponding to current output <NUM> of transconductance gain stage <NUM> is adjustable (e.g., trimmable), determined by the state set by a trim<<NUM>:<NUM>> vector input. The transconductance gain corresponding to current output <NUM> of transconductance gain stage <NUM> is not adjusted by the input trim<<NUM>:<NUM>> vector input. Further, both current outputs <NUM> and <NUM> are proportional to the output voltage of the differential error amplifier <NUM>, in which only the proportional gain of output <NUM> set by the trim<<NUM>:<NUM>> vector input.

In one example, the transconductance gain stage <NUM> uses an n-bit binary command "trim<n-<NUM>:<NUM>>" <NUM> to control the selection or deselection of a plurality of n parallel finger elements, shown in detail in <FIG> for the specific case of n =<NUM>. One skilled in the art would understand that having n=<NUM> is an example, and that other quantities for n are also within the scope and spirit of the present disclosure. In one example, the n-bit binary command may be set at the time of manufacture to adjust voltages such that a bandgap voltage Vbgap <NUM> reaches a desired target voltage.

In one example, the bandgap voltage Vbgap <NUM>, is set by combining (e.g., summing) a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage. The CTAT voltage is derived from the base-emitter junction voltage Vbe of a bipolar junction transistor which has a negative temperature coefficient. The PTAT voltage is derived from the ΔVbe voltage impressed between the anodes of the equally biased diode branches (<NUM> and N) in the diode array <NUM>, according to the classical equation: <MAT>.

In one example, the first resistor branch <NUM> is comprised by two resistors <NUM>, <NUM> connected in series, which further connects to the single (<NUM>) diode branch in diode array <NUM> through node <NUM>. The second resistor branch voltage <NUM> includes three resistors <NUM>, <NUM>, and <NUM> connected in series, which further connects to the N diode branch in diode array <NUM>.

In one example, the differential error amplifier <NUM> is part of the bandgap voltage reference circuit <NUM> which incorporates negative feedback, where the differential error amplifier <NUM> accepts two inputs, the first amplifier input fbp <NUM> from a first resistor branch <NUM> and the second amplifier input fbn <NUM> from a second resistor branch <NUM>. Specifically, differential error amplifier <NUM> input fbp <NUM> connects to node <NUM> in first resistor branch <NUM>, whereas input fbn <NUM> connects to node <NUM> in second resistor branch <NUM>. These connections comprise a negative feedback path which drives the input fbp311 and fbn <NUM> of differential error amplifier <NUM> to the same voltage, assuming the open loop gain of the negative feedback path is sufficiently high. As a result, one skilled in the art will recognize that the same ΔVbe voltage impressed between the anodes of the equally biased diode branches (<NUM> and N) in the diode array <NUM> now also is impressed across resistor <NUM> in second resistor branch <NUM>. Because resistor <NUM> voltage drop is controlled by feedback to be the ΔVbe voltage (PTAT voltage), the currents flowing in first resistor branch <NUM> and second resistor branch <NUM> are thus also PTAT. Further, if resistors <NUM>, <NUM>, <NUM>, and <NUM> are of equal resistance, the currents flowing in first resistor branch <NUM> and second resistor branch <NUM> are of equal magnitude. Summing the PTAT voltage drops across each resistor in either resistor branch with the corresponding CTAT Vbe of that branch yields a Vbgap voltage <NUM> which can be tuned to be largely independent of temperature (with proper nulling of CTAT with PTAT). In one example, the bandgap voltage may be expressed by the following equation: <MAT> where:.

The current flowing in each resistor branch is determined by the ratio of ΔVBE to the resistance of resistor <NUM>, according to the following equation: <MAT> where:.

In one example, the transconductance gain stage <NUM> uses binary weighted switched parallel transistor segments controlled by input trim<<NUM>:<NUM>> to set the transconductance gain corresponding to current output <NUM>. The transconductance gain corresponding to current output <NUM> is fixed and not controlled by the input trim<<NUM>:<NUM>>. Further, both current outputs <NUM> and <NUM> are proportional to the output voltage of the differential error amplifier <NUM>, and track precisely over temperature, supply voltage, and manufacturing process. The output of differential error amplifier <NUM>, controlled by the feedback loop, determines the proper input voltage to transconductance gain stage <NUM> which will source the correct amount of IPTAT from both current outputs <NUM> and <NUM> required to drive the input fbp311 and fbn <NUM> of differential error amplifier <NUM> to the same voltage.

<FIG> illustrates an example <NUM> of one possible embodiment of the transconductance gain stage <NUM>. The output of differential error amplifier <NUM> impresses a voltage signal on input <NUM>, which is then distributed to a plurality of gate connections to PFET current source elements. Element <NUM> is a fixed geometry PFET current source which provides an output current to output <NUM>, as determined by the input <NUM> signal. In one aspect, the example <NUM> includes selectable parallel elements which may be binary weighted or non-binary weighted. In one example, the selectable parallel elements are parallel connected current source elements <NUM>, <NUM>, <NUM> as shown in <FIG>.

In one example, the parallel connected current source elements <NUM>, <NUM>, and <NUM> form a digitally trimmable network comprised of switchable PFET current source segments which provide output currents to output <NUM>, as determined by the input <NUM> signal. The PFET geometries current source elements <NUM>, <NUM>, and <NUM> are binary weighted, i.e., the parallel current source elements are combined with individual geometric scale factors which are integral powers of <NUM>. In one example, the digitally trimmable network uses a n-bit binary encoded vector 'trim<<NUM>:<NUM>>' <NUM> to control the selection or deselection of the plurality of n binary weighted current source elements.

In one example, <FIG> illustrates a specific case of n = <NUM> binary weighted parallel current source elements. For example, trim<<NUM>> <NUM> may control a first current source element <NUM> with a relative weighting of <NUM>°, i.e., unity; trim<<NUM>> <NUM> may control a second current source element <NUM> with a relative weighting of <NUM><NUM>, i.e., two; trim<<NUM>> <NUM> may control a third current source element <NUM> with a relative weighting of <NUM><NUM>, i.e., four. For example, the n-bit binary command "trim<n-<NUM>:<NUM>> <NUM> may be used to implement a binary weighted superposition S of selected current source elements, with <MAT>.

<FIG> illustrates an example of a top-level block diagram of a reference voltage generation system <NUM>. A differential error amplifier <NUM> accepts a first input fbp <NUM> and a second input fbn <NUM> to produce an amplifier output Vout <NUM>. In one example, the amplifier output Vout <NUM> is related to the first and second amplifier inputs <NUM>, <NUM> via a differential error amplifier equation: <MAT> where G = open loop amplifier gain. In one example, G >> <NUM> and the differential error amplifier <NUM> is operated in a feedback configuration.

In one example, the feedback configuration is a negative feedback configuration. In one example, the negative feedback configuration drives the first amplifier input fbp <NUM> and the second amplifier input fbn <NUM> towards equality (i.e., fbp = fbn).

The amplifier output Vout <NUM> is split into two paths, a primary signal path with a primary transconductance amplifier <NUM> and a secondary signal path with a secondary transconductance amplifier <NUM>. In one example, the primary signal path and the secondary signal path track each other proportionally over temperature. In one example, the primary signal path and the secondary signal path are connected to both a first current branch <NUM> and a second current branch <NUM> of negative feedback path <NUM>. In one example, the negative feedback path <NUM> is a PTAT circuit.

In one example, a primary output <NUM> from the primary transconductance amplifier <NUM> is connected to a first node <NUM> of the first current branch <NUM> and the second current branch <NUM> of the negative feedback path <NUM>. In one example, a secondary output <NUM> from the secondary transconductance amplifier <NUM> is connected to a first trim node <NUM> of the first current branch <NUM> and the second current branch <NUM>.

The secondary signal path of the secondary transconductance amplifier <NUM> is a source of trim current for the negative feedback path <NUM>. The trim current is selected using selectable parallel elements. In one example, the selectable parallel elements are binary weighted. For example, the binary weighted selectable parallel elements may be selected using an n-bit binary encoded vector. In one example, the selectable parallel elements are selected during manufacturing test, and prior to operational use.

The diode array <NUM> employs a plurality of transistors (not shown). One diode-connected transistor is connected between the input <NUM> of DARRAY <NUM> and ground reference, whereas N parallel connected diode-connected transistors are connected between the input <NUM> of DARRAY <NUM> and ground reference. Given equal current magnitudes for each current entering the inputs <NUM> and <NUM> of DARRAY <NUM>, a voltage offset ΔVbe is impressed between inputs <NUM> and <NUM> which is PTAT in nature. In one example, the DARRAY <NUM> has a forward voltage drop which is a complementary to absolute temperature (CTAT) voltage.

In one example, the negative feedback path <NUM>, with equally biased current magnitudes in first and second current branches <NUM> and <NUM>, includes a differential voltage ΔVbe which is proportional to absolute temperature T in degrees Kelvin and is dependent on the diode-connected transistor ratio N. For example, <MAT> where:.

A first feedback node <NUM> of the first current branch <NUM> is connected to the first amplifier input fbp <NUM>. A second feedback node <NUM> of the second current branch <NUM> is connected to the second amplifier input fbn <NUM>.

In one example, a first bottom node <NUM> of the first current branch <NUM> is connected to a first input <NUM> of a diode array (e.g., DRRAY <NUM>). A second bottom node <NUM> of the second current branch <NUM> is connected to a second input <NUM> of the diode array (e.g., DRRAY <NUM>).

The various nodes of the first current branch <NUM> are interconnected using resistors. The various nodes of the second current branch <NUM> are interconnected using resistors. In one example, all resistances in current branches <NUM> and <NUM> are comprised of common matched unit cell (same physical geometries) structures to provide optimal ratio matching over temperature.

In one example, the sum of the currents flowing from the output <NUM> of the primary transconductance amplifier <NUM> and from the output <NUM> of the secondary transconductance amplifier <NUM> must equal the sum of current flowing into inputs <NUM> and <NUM> of DARRAY <NUM>. Further, if no current flows from the output <NUM> of the secondary transconductance amplifier <NUM>, the output <NUM> of the primary transconductance amplifier <NUM> must supply all the current flowing into inputs <NUM> and <NUM> of DARRAY <NUM>. Further, the current flow into inputs <NUM> and <NUM> of DARRAY <NUM> are constant, being set by the operation of the negative feedback path <NUM> by setting the ΔVbe across resistor <NUM> to be constant. In one example, the difference between input <NUM> and input <NUM> is a proportional to absolute temperature (PTAT) voltage. In one example, the input <NUM> is a complementary to absolute temperature (CTAT) voltage relative to ground and the input <NUM> is a CTAT voltage relative to ground.

In one example, the sum of current flow through resistor <NUM> is equal to the current flowing from output <NUM> of the transconductance amplifier <NUM> minus the current flowing from output <NUM> of transconductance amplifier <NUM>. This difference current impresses a voltage I*R drop across resistor <NUM>, according to the equation: <MAT> where:.

In one example, the voltage I*R drop impressed across resistor <NUM> is adjustable (trimmable) and is controlled by the binary-encoded input vector trim<(n-<NUM>):<NUM>>. The input vector trim<(n-<NUM>):<NUM>> controls the current flowing from output <NUM> of transconductance amplifier <NUM> by controlling the number binary-encoded parallel current source elements, which combined, source current to the output <NUM>. In one example, the bandgap output reference voltage can be adjusted, according to the following equation: <MAT> where:.

In one example, the combination of a PTAT voltage and a CTAT voltage of the diode array DARRAY <NUM> provides a bandgap voltage Vbgap <NUM> which is stable over temperature and has a reduced voltage offset. The bandgap voltage Vbgap <NUM> is a reference voltage.

<FIG> illustrates an example of flow diagram <NUM> for generating a precision bandgap reference with trim adjustment. In block <NUM>, generate a first voltage with a negative temperature coefficient. In one example, the first voltage may be generated by a bipolar junction transistor (BJT). In one example, the first voltage is a complementary to absolute temperature (CTAT) voltage.

In block <NUM>, generate a second voltage with a positive temperature coefficient using a common amplifier. In one example, the second voltage may be generated by a pair of transistors with a N:<NUM> emitter area ratio. In one example, the plurality of transistors with a N:<NUM> emitter area ratio is part of a diode array, for example, the diode array (e.g., DARRAY <NUM>). In one example, the second voltage is a proportional to absolute temperature (PTAT) voltage.

In block <NUM>, scale the second voltage to generate a first scaled voltage, wherein the first scaled voltage includes a voltage offset. In one example, the voltage offset is a constant voltage offset. In one example, the first scaled voltage is generated using a differential error amplifier (e.g., differential error amplifier <NUM> shown in <FIG>). In one example, the first scaled voltage is generated using a diode array.

In block <NUM>, generate a trim current using at least one of a plurality of selectable parallel elements. In one example, the plurality of selectable parallel elements is binary weighted. In one example, the at least one of the plurality of selectable parallel elements is selected for usage using an n-bit binary word. In one example, the at least one of the plurality of selectable parallel elements is selected for usage prior to operational use. In one example, the trim current tracks the first scaled voltage over temperature.

In block <NUM>, input the trim current to parallel resistor branches to generate a second scaled voltage. In one example, the second scaled voltage is the first scaled voltage with the voltage offset reduced. In one example, the trim current may be inputted to multiple parallel resistor branches to generate the second scaled voltage.

In block <NUM>, combine the first voltage and the second scaled voltage to generate a reference voltage. In one example, the reference voltage is a bandgap voltage. In one example, the reference voltage is stable over temperature variation.

<FIG> illustrates example reference voltage curves vs. temperature <NUM> which assumes a nominal semiconductor carrier mobility. In the example of <FIG>, the horizontal axis denotes temperature in degrees Celsius and the vertical axis denotes voltage in volts. For example, the reference voltage curves vs. temperature demonstrates good stability over a temperature range of -<NUM> deg C to <NUM> deg C.

<FIG> illustrates example reference voltage curves vs. temperature <NUM> which assumes a fast semiconductor carrier mobility. In the example of <FIG>, the horizontal axis denotes temperature in degrees Celsius and the vertical axis denotes voltage in volts. For example, the reference voltage curves vs. temperature demonstrates good stability over a temperature range of -<NUM> deg C to <NUM> deg C.

<FIG> illustrates example reference voltage curves vs. temperature <NUM> which assumes a slow semiconductor carrier mobility. In the example of <FIG>, the horizontal axis denotes temperature in degrees Celsius and the vertical axis denotes voltage in volts. For example, the reference voltage curves vs. temperature demonstrates good stability over a temperature range of -<NUM> deg C to <NUM> deg C.

In one aspect, one or more of the steps for generating a precision bandgap reference with trim adjustment in <FIG> may be executed by one or more processors which may include hardware, software, firmware, etc. In one aspect, one or more of the steps in <FIG> may be executed by one or more processors which may include hardware, software, firmware, etc. The one or more processors, for example, may be used to execute software or firmware needed to perform the steps in the flow diagram of <FIG>.

The software may reside on a computer-readable medium. The computer-readable medium may be a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The computer-readable medium may reside in the processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer-readable medium may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. The computer-readable medium may include software or firmware for generating a precision bandgap reference with trim adjustment. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

Any circuitry included in the processor(s) is merely provided as an example, and other means for carrying out the described functions may be included within various aspects of the present disclosure, including but not limited to the instructions stored in the computer-readable medium, or any other suitable apparatus or means described herein, and utilizing, for example, the processes and/or algorithms described herein in relation to the example flow diagram.

For instance, a first die may be coupled to a second die in a package even though the first die is never directly physically in contact with the second die.

One or more of the components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein.

Claim 1:
A circuit for generating a reference voltage with trim adjustment, the circuit comprising:
a differential error amplifier (<NUM>) having a first input (<NUM>), a second input (<NUM>) and an amplifier output (<NUM>);
a transconductance gain stage comprising a primary transconductance amplifier (<NUM>) and a secondary transconductance amplifier (<NUM>) both connected to the amplifier output (<NUM>), the secondary transconductance amplifier (<NUM>) configured for generating a trim current using at least one of a plurality of selectable parallel elements within the secondary transconductance amplifier (<NUM>), wherein the secondary transconductance amplifier (<NUM>) is configured to receive a trim vector input for adjusting the gain of the secondary transconductance amplifier (<NUM>);
a first current branch (<NUM>) including two resistors connected in series, wherein the first current branch has an input, a trim node between the two resistors, and an output;
a second current branch (<NUM>) including three resistors connected in series, wherein the second current branch has an input, a trim node between a first and a second resistor of the three resistors corresponding to the first branch (<NUM>), and an output;
wherein the input of the first and second current branch (<NUM>, <NUM>) is connected to an output of the primary transconductance amplifier (<NUM>),
wherein the trim node of the first and second current branch (<NUM>, <NUM>) is connected to an output of the secondary transconductance amplifier (<NUM>), and
wherein the output of the first current branch (<NUM>) is connected the first input (<NUM>) of the differential error amplifier (<NUM>), and wherein a feedback node between the second resistor and a third resistor of the three resistors of the second current branch (<NUM>) is connected to the second input (<NUM>) of the differential error amplifier (<NUM>);
a diode array (<NUM>) including a plurality of diode-connected transistors, wherein one of the plurality of diode-connected transistors is connected between the output of the first current branch (<NUM>) and ground, and wherein the remaining ones of the diode-connected transistors are connected in parallel between the output of the second current branch (<NUM>) and ground;
wherein the reference voltage is generated at the output of the primary transconductance amplifier (<NUM>).