Patent Description:
Modern optical and electronic devices of almost all types, from computers to powertrains, comprise power switching circuitry for generating timing pulses, data packets, and/or delivering power. For delivering power to electric powertrains, such as powertrains used to deliver power to electric vehicles, power switches are required that can rapidly be turned ON and OFF to couple and decouple a high voltage electric power source to a load. Group III-V high electron mobility transistors (HEMTs), for example GaN (gallium nitride) transistors, are particularly advantageous for such applications. Group III-V HEMTs are wide band gap transistors characterized by high breakdown voltage, high current density, and low ON-state resistance. However, Group III-V HEMTs are generally normally ON, depletion mode transistors. As a result, in power switching circuitry that use these transistors as switching elements, a controller is required to be in constant control of the ON/OFF states of the transistors and maintain them OFF as long as they are coupled to a power source and not required to be ON to switch power from the power source to a load. In the absence of such control, for example if the switching circuitry is connected to the power source before being connected to the controller or the controller malfunctions during operation, large current transients may be generated that damage the power switch, the load, and/or the power source.

An aspect of an embodiment of the disclosure relates to providing a fast switching power switch that comprises a normally ON optionally a depletion mode transistor. The power switch is configured to electrically connect and disconnect a load to and from a load power source and prevent generation of large current transients that might damage the power switch, load, and/or power source.

In an embodiment the power switch comprises a cascode in which the normally ON transistor is connected in series with a normally OFF, optionally enhancement mode, transistor at a node of the cascode. A diode, optionally referred to as a safety diode, is connected between the gate of the normally ON transistor and a first ground common to the cascode and the diode. A controller powered by a controller power supply controls the gates of the depletion and enhancement mode transistors. An output of the controller power supply that provides a controller voltage relative to a second ground is connected to the cascode node. The second ground, which may be referred as a floating ground or ground floating relative to the first ground, is not directly connected to the first ground, and has a voltage that is offset relative to the first ground responsive to voltage of the cascode node minus the controller voltage. The controller power supply voltage has an absolute value greater than an absolute value of a threshold voltage of the normally ON transistor.

The controller dynamically controls the ON/OFF states of the transistors to turn ON and turn OFF the power switch, and to prevent large transient currents is configured to maintain the normally ON transistor OFF as long as the enhancement mode transistor is OFF. The controller controls the gates to make the cascode conducting and turn ON the power switch by first turning ON the enhancement mode transistor and then the normally ON transistor. When the power switch is turned ON, the cascode provides a conducting path through which current may flow from a load power supply connected to the power switch to provide power to a load connected to the power switch. The controller controls the gates to render the cascode nonconducting and turn OFF the power switch to prevent current from the load power supply to flow through the cascode and provide power to the load by turning OFF the normally ON transistor while the enhancement mode transistor ON.

For a situation, also referred to as an aberrant situation, in which the power switch is connected to a load power supply and the controller does not operate to maintain the normally ON transistor OFF when the enhancement mode transistor is OFF, the safety diode operates to turn OFF the normally ON transistor and protect the power switch, the load and/or the load power source from damage resulting from large transient currents.

Whereas in accordance with an embodiment of the disclosure the depletion and enhancement transistors may be n-channel or p-channel transistors, for convenience of presentation and reference to voltage polarities it is assumed by way of example in the following discussion that the depletion and enhancement mode transistors are n-channel transistors. The source of the enhancement mode transistor is assumed to be connected to the first ground and the anode of the safety diode connected to the gate of the normally ON transistor. The first ground voltage is assumed to be a zero reference voltage and the load power supply to provide a positive voltage relative to the first ground.

For aberrant situations in which the power switch is connected to a load power supply and the controller does not operate to maintain the normally ON transistor OFF when the enhancement mode transistor is OFF voltage of the drain and source of the normally ON transistor become relative to the first ground substantially equal to a positive voltage provided by the load power supply. The safety diode limits voltage at the normally ON transistor gate relative to the first ground to a positive forward voltage of the safety diode that is less than the positive voltage of the power supply by at least the absolute value of the threshold voltage of the normally ON transistor. The forward voltage of the safety diode generates thereby a gate to source voltage for the normally ON transistor that is less than the threshold voltage and turns OFF the normally ON transistor to prevent transient current flow from damaging the power switch, the load, and/or the power supply.

When the controller subsequently turns ON the enhancement mode transistor, the cascode node, the source of the normally ON transistor, the drain of the enhancement mode transistor and thereby the controller power supply output are electrically connected to the first ground. The voltage of the second ground therefore assumes a voltage, optionally referred to as a controller operating reference voltage, that is less than the first ground by about the controller power supply voltage. As a result, the controller sets the voltage of the gate of the normally ON transistor to the controller operating reference voltage and maintains the normally ON transistor OFF and the power switch turned OFF. The controller operates to turn ON the normally ON transistor and turn ON the power switch by applying to the normally ON transistor gate a "turn-on" positive voltage relative to the controller operating reference voltage. The turn-on voltage has a magnitude that raises the voltage of the normally ON transistor gate to greater than the voltage of the first ground minus the absolute value of the normally ON transistor threshold voltage but less than the voltage of the first ground plus the forward voltage of safety diode. The turn-on voltage therefor is not shunted to ground by the safety diode but generates a gate to source voltage for the normally ON transistor that turns ON the normally ON transistor and turns ON the power switch.

<CIT> and <CIT> are considered to be relevant prior art which disclose a power switching circuit for high voltage switching comprising a normally ON transistor in series with normally OFF transistor, a diode connected between the gate of the normally ON transistor and a source of the normally OFF transistor, driver circuitry for the normally ON transistor and a controller power supply for said driver circuitry of the normally ON transistor.

Non-limiting examples of embodiments of the invention are described below with reference to figures attached hereto that are listed following this paragraph. Identical structures, elements or parts that appear in more than one figure are generally labeled with a same numeral in all the figures in which they appear. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.

Wherever a general term in the disclosure is illustrated by reference to an example instance or a list of example instances, the instance or instances referred to, are by way of non-limiting example instances of the general term, and the general term is not intended to be limited to the specific example instance or instances referred to. The phrase "in an embodiment", whether or not associated with a permissive, such as "may", "optionally", or "by way of example", is used to introduce for consideration an example, but not necessarily a required configuration of possible embodiments of the disclosure. Unless otherwise indicated, the word "or" in the description and claims is considered to be the inclusive "or" rather than the exclusive or, and indicates at least one of, or any combination of more than one of items it conjoins.

<FIG> schematically shows a power switch <NUM> in accordance with an embodiment of the disclosure. Power switch <NUM> comprises a cascode <NUM> having a normally ON optionally depletion mode, transistor <NUM> connected in series with a normally OFF transistor <NUM>, a controller <NUM> that controls the transistors, and a safety diode <NUM> that operates to turn OFF the normally ON transistor in the absence of appropriate control by the controller.

Cascode <NUM> is connected between terminals <NUM> and <NUM> to which loads and load power supplies for which the power switch controls transmission of power from the power supplies to the loads are connected. Optionally, terminal <NUM> is connected to a ground G<NUM>, which for convenance of presentation is assumed to have voltage equal to zero. A drain D31 of normally ON transistor <NUM> is connected to terminal <NUM> and a source S32 of enhancement mode transistor <NUM> is connected to terminal <NUM> and thereby to ground G<NUM>. A drain D32 of enhancement transistor <NUM> is connected to a source S31 of normally ON transistor <NUM> at a cascode node N33. Optionally, as indicated in <FIG> transistors <NUM> and <NUM> are n-channel transistors, have threshold voltages V31th and V32th respectively, and normally OFF transistor <NUM> is an enhancement mode transistor. Safety diode <NUM> is connected between a gate G31 of normally ON transistor <NUM> and ground G<NUM> and has the anode of the safety diode connected to the gate. By way of example, in <FIG> a load, schematically represented by a resistor <NUM>, and a load power supply, LPS, that provides a positive voltage VLPS relative to ground G<NUM> for powering the load are connected in series to power switch terminals <NUM> and <NUM>.

Voltage signals generated by controller <NUM> are referenced to a ground G<NUM> that is floating relative to ground G<NUM>. The controller comprises a controller power supply CPS that generates a positive voltage VCPS at an output <NUM> of the power supply relative to G<NUM> that is greater than the larger of the absolute value of the threshold voltage V31th and optionally the threshold voltage V32th. Output <NUM> is electrically connected to cascode node N33 and to a DC isolator or isolated gate driver <NUM>, optionally referred to generically as a DC isolator. DC isolator <NUM> connects controller power supply CPS to a gate G32 of enhancement transistor <NUM>. When controller power supply CPS provides DC isolator <NUM> with voltage VCPS the DC isolator generates, or is controllable to generate, a DC voltage at gate G32 relative to ground G<NUM>. The DC voltage provided by the DC isolator at gate G32 generates a gate to source voltage V32GS for enhancement mode transistor <NUM> that is greater than the threshold voltage V32th of the enhancement mode transistor and turns ON the enhancement mode transistor to connect cascode node N33 to ground G<NUM>.

In accordance with an embodiment of the disclosure controller <NUM> comprises an isolated power amplifier operating as a gate driver <NUM> that receives power from controller power supply CPS and controls the ON/OFF state of normally ON transistor <NUM>. The gate driver has an output <NUM> connected to gate G31 of the normally ON transistor <NUM> and an input <NUM> through which the gate driver receives switch control signals from a gate driver controller (not shown). When powered by voltage VCPS from controller power supply CPS the switch control signals control an output voltage V<NUM> that the gate driver generates at output <NUM> relative to ground G<NUM>. Voltage V<NUM> controls voltage of gate G31 and a gate to source voltage, V31GS, for normally ON transistor <NUM> that controls the ON/OFF state of the normally ON transistor <NUM>. As discussed below, as long as controller power supply CPS provides power to DC isolator <NUM> to maintain enhancement mode transistor <NUM> turned ON, V<NUM> at output <NUM> and thereby voltage V31GS, controls whether normally ON transistor <NUM> is turned OFF or turned ON and thereby whether power switch <NUM> is respectively turned OFF or turned ON.

Since output <NUM> of controller power supply CPS is connected to cascode node N33 and ground G<NUM> is floating relative to ground G<NUM>, voltage V<NUM> generates a gate to source voltage V31GS = (V<NUM>-VCPS) for normally ON transistor <NUM>. In the absence of switch control signals from the gate driver, controller voltage V<NUM> is zero relative to G<NUM> and gate to source voltage V31GS is equal to -VCPS. As a result, because VCPS is greater than the absolute value |V31th| of the threshold voltage of normally ON transistor <NUM>, V31GS is less than V31th and operates to turn OFF and maintain the normally ON transistor OFF.

On the other hand, in accordance with an embodiment of the disclosure, when triggered by appropriate switch control signals at input <NUM>, gate driver <NUM> increases voltage V<NUM> relative to G<NUM> to generate a gate to source voltage V31GS = (V<NUM>-VCPS) that is greater than V31th, The gate to source voltage V31GS therefore turns ON normally ON transistor <NUM> to render cascode <NUM> conducting and turn ON power switch <NUM>.

By way of example, <FIG> schematically shows gate driver <NUM> receiving switch control signals that are a sequence of voltage pulses <NUM>, which cause gate driver <NUM> to generate a corresponding sequence of output, also referred to as "turn-on", pulses <NUM>. The voltage pulses have a positive magnitude V<NUM> relative to G<NUM> and generate a gate to source voltage pulses V31GS = (V<NUM>-VCPS). In accordance with an embodiment the magnitude of V<NUM> is such that (V<NUM>-VCPS) ≥ V31th, and each pulse <NUM> turns ON normally ON transistor <NUM> for a period substantially equal to a duration of the pulse for which V<NUM> ≥ (V31th + VCPS). Since enhancement mode transistor <NUM> is ON, switch control pulses <NUM> operate to turn ON and turn OFF power switch <NUM> and provide power to load <NUM> from load power supply LPS at a repetition frequency and duty cycle determined by the frequency and pulse widths of the switch control signal pulses.

It is noted that for power switch <NUM> voltage pulses V<NUM> are referenced to ground G<NUM> and have a maximum magnitude equal to VCPS relative to G<NUM>. Relative to ground G<NUM>, ground G<NUM> establishes an operating reference voltage for controller <NUM> that is equal to (VN33-VCPS) where VN33 is a voltage at cascode node N33. Because enhancement transistor <NUM> is turned ON, cascode node N33 is electrically connected to ground G<NUM> via turned ON enhancement transistor <NUM>. Voltage at VN33 is therefore about equal to voltage of G<NUM> plus a voltage drop V32ds across enhancement transistor <NUM> and the operating reference voltage of ground G<NUM> is equal to about voltage (G<NUM> + V32ds) - VCPS. In an embodiment, safety diode <NUM> is configured to have a forward voltage Vf that is greater than an expected voltage drop V32ds when power switch <NUM> is turned ON. Relative to ground G<NUM> to which safety diode <NUM> is directly connected, voltage pulses <NUM> therefore do not exceed the forward voltage Vf of safety diode <NUM>. As a result, the voltage pulses are not shunted to ground G<NUM> by the safety diode and prevented from generating a voltage V31GS that turns ON transistor <NUM> and switches ON power switch <NUM>.

<FIG> shows a graph <NUM> that schematically shows temporal development and relative timing of voltages relevant to operation of power switch <NUM> along timelines <NUM>, <NUM>, <NUM>, and <NUM>, in accordance with an embodiment of the disclosure. Voltage VCPS generated by controller power supply CPS at output <NUM> of the controller relative to ground G<NUM> is shown along timeline <NUM>. Timeline <NUM> schematically shows gate voltage V32GS that DC isolator <NUM> (<FIG>) applies to gate G32 to turn ON and maintain ON enhancement mode transistor <NUM> when controller power supply <NUM> provides voltage VCPS to the DC isolator. Timeline <NUM> schematically shows switch control pulses <NUM> that control gate driver <NUM> to generate gate driver output pulses <NUM> (<FIG>) which turn ON normally ON transistor <NUM> and switches ON power switch <NUM> when controller power supply provides voltage VCPS. Timeline <NUM> schematically shows voltage of output pulses <NUM> and threshold voltage V31th of normally ON transistor <NUM> relative to ground G<NUM> and ground G<NUM>. As described above, when controller power supply CPS is turned on and provides voltage VCPS to power controller <NUM>, voltage of ground G<NUM> is less by voltage VCPS than voltage of ground G<NUM> to which source S31 is electrically connected by turned ON enhancement mode transistor <NUM>. When voltage of a gate driver pulse <NUM> rises above G<NUM> to a voltage (assuming that V31th is negative) that is greater than (G<NUM>- |V31th|), normally ON transistor <NUM> is turned ON and power switch <NUM> turned ON. Voltage at which a gate driver pulses <NUM> rise above (G<NUM>- |V31th|) and turns ON power switch <NUM> is indicated by regions of the pulses that lack hatching.

Whereas as long as controller <NUM> is connected to cascode <NUM> and properly controls transistors <NUM> and <NUM> to maintain normally ON transistor <NUM> OFF and enhancement transistor <NUM> ON when power switch <NUM> is intended to be turned OFF, controller <NUM> operates as described above and prevents occurrence of potentially large and damaging transient currents. However, large damaging transient currents may develop if load power supply LPS is connected to power switch <NUM> normally ON transistor <NUM> is turned ON and enhancement mode transistor turned OFF, for example as a result of controller <NUM> malfunctioning or not being properly connected to cascode <NUM>. In the event of such an aberrant situation, voltage of drain D31, gate G31, and source S31 of normally ON transistor <NUM> rise toward voltage VLPS of the load power supply and operate to turn ON the normally ON transistor and enable generation of damaging transient currents. In accordance with an embodiment of the disclosure safety diode <NUM> operates to prevent the normally ON transistor from turning ON. As voltage at gate G31 rises to exceed the forward voltage threshold Vf of safety diode <NUM>, the diode turns ON, limits voltage of gate G31 relative to ground G<NUM> to the forward diode voltage threshold and generates a negative gate to source voltage V31GS that turns OFF the normally ON transistor <NUM>, and limits generation and/or persistence of large transients that might damage power switch <NUM> and circuits connected to the power switch.

<FIG> schematically shows a power switch <NUM> in accordance with an embodiment of the disclosure. Power switch <NUM> is similar to power switch <NUM> but comprises a controller <NUM> having an additional safety diode <NUM> that operates to block parasitic current path from cascode node <NUM> from flowing to the controller.

<FIG> schematically shows a power switch <NUM>, in accordance with an embodiment of the disclosure. Power switch <NUM> is similar to power switch <NUM> but comprises a controller <NUM> having a comparator <NUM>, optionally a Schmidt trigger, having an input <NUM> connected to output <NUM> of controller power supply CPS and an output <NUM> connected to DC isolator <NUM> and gate driver <NUM>. In accordance with an embodiment, comparator <NUM> disables operation of DC isolator <NUM> and gate driver <NUM> if controller power supply CPS does not provide a voltage VCPS that is greater than the absolute value |V31th| of the threshold voltage of normally ON transistor <NUM>, or otherwise sufficient voltage to enable proper operation of the controller. If power supply CPS does provide sufficient voltage, comparator <NUM> generates an enable signal at output <NUM> that enables operation of DC isolator <NUM> and gate driver <NUM>. Preventing operation of DC isolator <NUM> and gate driver <NUM> engages safety diode <NUM> as discussed above to turn OFF normally ON transistor <NUM> and turn OFF power switch <NUM>.

Whereas in the above description power switches are described as comprising a safety diode <NUM> that operates to turn OFF the normally ON transistor and protect the power switches from damage resulting from large transient currents, practice of embodiments of the disclosure is not limited to safety diodes. For example, a normally ON switch which is turned OFF when normally OFF transistor <NUM> is turned ON may be used to protect the power switch from damaging transients. <FIG> schematically shows a power switch <NUM> in accordance with an embodiment that is similar to power switch <NUM> shown in <FIG> but having a normally ON switch <NUM> in place of diode <NUM> (<FIG>). Normally ON switch <NUM> is optionally turned OFF by an enable signal provided by comparator <NUM> at output <NUM> or by a voltage generated by gate driver <NUM>, such as V32GS.

<FIG> schematically shows details of a circuit configuration <NUM>-<NUM> for DC isolator <NUM> that connects controller power supply CPS to enhancement mode transistor <NUM> to generate a DC gate to source voltage V32GS that turns ON the enhancement mode transistor, in accordance with an embodiment of the disclosure.

Circuit configuration <NUM>-<NUM> optionally comprises an inverting operational amplifier <NUM> coupled to a resistor R<NUM> and a capacitor C<NUM> connected in series to ground G1. Rails <NUM> and <NUM> of amplifier <NUM> are connected to output <NUM> of controller power supply CPS and ground G<NUM> respectively. Resistor R<NUM> is connected between an output <NUM> and an input <NUM> of inverting amplifier <NUM>. As a result, responsive to the DC voltage VCPS provided by controller power supply CPS, inverting amplifier <NUM> generates an oscillating voltage and current. The oscillating current is rectified by resistor R<NUM>, capacitors C<NUM> and C<NUM>, and diodes D<NUM> and D<NUM>, to provide the gate to source DC voltage V32GS that turns ON enhancement mode transistor <NUM>. Capacitors C<NUM> and C<NUM> DC isolate controller power supply CPS from enhancement transistor <NUM>. Resistor R<NUM> is a bleeder resistor.

<FIG> schematically shows details of another circuit configuration <NUM>-<NUM> for DC isolator <NUM> that connects controller power supply CPS to enhancement mode transistor <NUM> to generate a DC gate to source voltage V32GS that turns ON the enhancement mode transistor, in accordance with an embodiment of the disclosure.

Circuit configuration <NUM>-<NUM> is similar to circuit configuration <NUM>-<NUM> but instead of generating an oscillating current by coupling output <NUM> of inverting operational amplifier <NUM> to input <NUM> of the amplifier, in configuration <NUM>-<NUM> the input is configured to receive a sequence of input pulses <NUM> at input <NUM> from an external driver (not shown), in accordance with an embodiment of the disclosure. In response to input pulses <NUM> amplifier <NUM> generates a sequence of output pulses <NUM> that are rectified to provide gate to source DC voltage V32GS that turns ON enhancement mode transistor <NUM>.

In the description and claims of the present application, each of the verbs, "comprise" "include" and "have", and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb.

Claim 1:
A power switch comprising:
a cascode (<NUM>) having a normally ON transistor (<NUM>) connected in series with a normally OFF transistor (<NUM>) at a cascode node (<NUM>);
a first diode (<NUM>) connected between a gate (G31) of the normally ON transistor and a first ground (G1) common to the cascode and the diode; and
a controller comprising:
a gate driver (<NUM>) having a gate driver output (<NUM>) connected to the gate of the normally ON transistor;
a controller power supply (CPS) having positive and negative outputs that provide positive and negative rail voltages respectively to the gate driver and wherein the positive output of the controller power supply is connected to the cascode node and the negative output the controller power supply to a second ground (G2) that is floating relative to the first ground; and
a DC isolator having positive and negative isolator inputs connected respectively to the positive and negative outputs of the power supply and a first isolator output connected to the gate of the normally OFF transistor and a second isolator output connected to the first ground, and wherein when the controller power supply is turned ON, the DC isolator generates a DC voltage at the first voltage output that turns and maintains ON the normally OFF transistor.