Patent Description:
A flat panel display, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display, and the like, includes a pair of electric field-generating electrodes and an electrical active layer interposed therebetween. The liquid crystal display (LCD) includes a liquid crystal layer as an electric active layer, and the organic light emitting diode (OLED) display includes an organic emission layer as an electrical active layer.

One of the pairs of the electric field-generating electrodes is commonly connected to a switching device and receives an electrical signal, and the electrical active layer transforms the electrical signal into an optical signal and thus displays an image.

The flat panel display includes a three-terminal element of a thin film transistor (TFT) as a switch, and also includes a gate line and a data line. The gate line may be used for transferring a scan signal and for controlling the thin film transistor. The data line may be used for transferring a data signal to be applied to a pixel electrode.

<CIT> discloses a nanoporous thin film device including a nanoporous insulating layer.

<NPL>et al. discloses a device having insulated gated channels through the insulating layer.

An embodiment provides a thin film transistor capable of realizing improved performance.

Another embodiment provides a method of manufacturing the thin film transistor.

Yet another embodiment provides a thin film transistor array display panel including the thin film transistor.

Still another embodiment provides an electronic device including the thin film transistor or the thin film transistor array display panel.

According to an embodiment, a thin film transistor is provided according to claim <NUM>.

According to the invention, the semiconductor layer is on the gate insulating layer, and the plurality of recess portions of the gate insulating layer and the plurality of holes of the semiconductor layer are overlapped with each other.

According to the invention, the plurality of holes of the semiconductor layer are repetitively arranged according to a column or a row.

In some example embodiments, the depth of the recess portions may range from about <NUM> to about <NUM>.

In some example embodiments, the width of the recess portions may range from about <NUM> to about <NUM>.

In some example embodiments, an interval between the neighboring recess portions, among the plurality of recess portions, may range from about <NUM> to about <NUM>.

In some example embodiments, the plurality of recess portions may have substantially the same width according to a depth.

In some example embodiments, the plurality of recess portions may have a different width according to a depth.

In some example embodiments, a width of the plurality of recess portions may become wider as a depth from the surface of the gate insulating layer facing the semiconductor layer increases.

In some example embodiments, the thin film transistor may further include a surface-modification layer between the gate insulating layer and the semiconductor layer.

In some example embodiments, the semiconductor layer may be a continuous thin film.

In some example embodiments, the semiconductor layer may include an organic semiconductor.

In some example embodiments, the organic semiconductor may include at least one of a fused polycyclic aromatic compound or a fused polycyclic heteroaromatic compound.

In some example embodiments, a thin film transistor array panel may include a substrate, a gate line and a date line on the substrate, and the thin film transistor connected to the gate line and the date line and disposed in one of a plurality of pixels. The gate line and the date line may cross each other to define a plurality of pixels.

According to another embodiment, a method of manufacturing a thin film transistor is provided according to claim <NUM>.

In some example embodiments, the forming the gate insulating layer may include forming the plurality of recess portions at the surface of the gate insulating layer using at least one of a photolithography process or an electron beam lithography.

In some example embodiments, the forming the semiconductor layer may include depositing or coating a semiconductor material on the surface of the gate insulating layer having the recess portions and the semiconductor material may be selectively deposited or coated on the surface of the gate insulating layer except for the recess portions.

In some example embodiments, a part of the semiconductor material may flow into the recess portions and the part of semiconductor material that flows into the plurality of recess portions may not be connected to the semiconductor material on the surface of the gate insulating layer.

In some example embodiments, the manufacturing method may further include modifying the gate insulating layer before forming the semiconductor layer.

According to another embodiment, an electronic device includes the thin film transistor.

In some example embodiments, an electronic device may include the thin film transistor, a gate line connected to the gate electrode, a data line connected to the source electrode.

According to inventive concepts, a thin film transistor having a high performance may be realized.

Example embodiments will hereinafter be described in detail, and may be easily performed by those who have common knowledge in the related art. However, this disclosure may be embodied in many different forms and is not to be construed as limited to the embodiments set forth herein.

When a definition is not otherwise provided, "substituted" refers to replacement of hydrogen of a compound by a substituent selected from a halogen atom (F, Br, Cl, or I), a hydroxy group, an alkoxy group, a nitro group, a cyano group, an amino group, an azido group, an amidino group, a hydrazino group, a hydrazono group, a carbonyl group, a carbamyl group, a thiol group, an ester group, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid or a salt thereof, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C2 to C20 alkynyl group, a C6 to C30 aryl group, a C3 to C30 heteroaryl group, a C7 to C30 arylalkyl group, a C1 to C30 alkoxy group, a C1 to C20 heteroalkyl group, a C3 to C20 heteroarylalkyl group, a C3 to C30 cycloalkyl group, a C3 to C15 cycloalkenyl group, a C6 to C15 cycloalkynyl group, a C3 to C30 heterocycloalkyl group, and a combination thereof.

As used herein, when specific definition is not otherwise provided, "hetero" refers to one including <NUM> to <NUM> heteroatoms selected from N, O, S, Se, and P.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

Hereinafter, a thin film transistor according to an embodiment is described.

<FIG> is a schematic top plan view of a thin film transistor according to an embodiment and <FIG> is a cross-sectional view taken along the II-II line of <FIG>.

<FIG> is a schematic view showing a surface of a gate insulating layer <NUM> according to an embodiment, <FIG> is a schematic view showing a cross-section of a gate insulating layer according to an embodiment, and <FIG> and <FIG> are schematic views showing various arrangements of recess portions 141p of gate insulating layers <NUM>, wherein <FIG> is not according to the present invention and <FIG> is according to an embodiment of the present invention.

<FIG> is a schematic view showing a surface of a semiconductor layer <NUM> according to an embodiment.

<FIG> and <FIG> are schematic views showing arrangements of holes <NUM> of semiconductor layers <NUM>, wherein <FIG> is not according to the present invention and <FIG> is according to an embodiment of the present invention,.

A thin film transistor <NUM> according to an embodiment includes a gate electrode <NUM>, a gate insulating layer <NUM>, a semiconductor layer <NUM>, a source electrode <NUM>, and a drain electrode <NUM>.

The substrate <NUM> may support the thin film transistor <NUM> and may be for example an insulation substrate such as transparent glass or a polymer, or a silicon wafer. The polymer may include for example polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyacrylate, polyimide, or a combination thereof, but is not limited thereto.

The gate electrode <NUM> is connected to a gate line <NUM> transferring a gate signal. The gate electrode <NUM> may be for example made of gold (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), an alloy thereof, or a combination thereof, but is not limited thereto. However, when the substrate <NUM> is a silicon wafer, the gate electrode <NUM> may be a doping region of the silicon wafer. The gate electrode <NUM> may include one layer or two or more layers.

The gate insulating layer <NUM> is formed on the gate electrode <NUM>. The gate insulating layer <NUM> is formed on the whole surface of the substrate <NUM> and may include a first region in the thin film transistor <NUM> and a second region in the region except the thin film transistor <NUM>. For example, the first region may be a region overlapped with the semiconductor layer <NUM> and the second region may be a region except the first region. For example, the first region may be a region in which a channel of the thin film transistor <NUM> is formed and the second region may be a region except the first region.

A plurality of recess portions 141p are formed at the surface of the gate insulating layer <NUM>. The recess portions 141p may have a lower surface than a main surface of the gate insulating layer <NUM>, and may be, for example, a pattern having a desired (and/or alternatively predetermined) width and depth. For example, the gate insulating layer <NUM> may have a surface portion having a first thickness D1 corresponding to a thickness of the gate insulating layer <NUM> and the recess portions 141p having a thinner second thickness D2 than the first thickness D1.

The plurality of recess portions 141p are regularly arranged with a desired (and/or alternatively predetermined) interval at the surface of the gate insulating layer <NUM>. The plurality of recess portions 141p are disposed in a region where the thin film transistor <NUM> is disposed, that is, in a first region of the gate insulating layer <NUM>.

Referring to <FIG> and <FIG>, the plurality of recess portions 141p having a desired (and/or alternatively predetermined) width (a) and depth (b) may be formed with a desired (and/or alternatively predetermined) interval (c) at the surface of the gate insulating layer <NUM>.

For example, the width (a) of the recess portions 141p may be in a sub-micrometer range, for example, in a range of about <NUM> to about <NUM>, and/or about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, or about <NUM> to about <NUM>. The recess portions 141p may have substantially the same width (a) depending on a depth. The width (a) of the plurality of recess portions 141p may be the same or different.

According to the invention, the depth (b) of the recess portions 141p is less than or equal to about <NUM> % of the first thickness D1, a thickness of the gate insulating layer <NUM>. Within the range, the depth (b) of the recess portions 141p may be less than or equal to about <NUM> %, less than or equal to about <NUM> %, less than or equal to about <NUM>%, or less than or equal to about <NUM> % of the thickness D1 of the gate insulating layer <NUM>. For example, the depth (b) of the recess portions 141p may be within a sub-micrometer range, for example, in a range of about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, or about <NUM> to about <NUM>. The depth (b) of the plurality of recess portions 141p may be the same or different.

For example, the interval (c) among the neighboring recess portions 141p may be for example in a range of about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, for example about <NUM> to about <NUM>, and about <NUM> to about <NUM>. The interval (c) among the recess portions 141p may be the same or different.

In a comparative example not forming part of the present invention, referring to <FIG>, the plurality of recess portions 141p may be randomly arranged at the surface of the gate insulating layer <NUM>.

According to the invention, referring to <FIG>, the plurality of recess portions 141p may be repetitively arranged according to a row and/or a column at the surface of the gate insulating layer <NUM>. For example, the plurality of recess portions 141p may be arranged as a lattice structure.

The gate insulating layer <NUM> may be made of an organic material, an inorganic material, or an organic/inorganic material. Examples of the organic material may include a compound such as one of a polyvinyl alcohol-based compound, a polyvinyl phenol-based compound, a polyimide-based compound, a polyacryl-based compound, a polystyrene-based compound, a benzocyclobutane (BCB), or a combination thereof. Examples of the inorganic material may include a silicon nitride (SiNx), a silicon oxide (SiO<NUM>), aluminum oxide (Al<NUM>O<NUM>), hafnium oxide (HfO<NUM>), or a combination thereof, and examples of the organic/inorganic material may be polysiloxane but are not limited thereto. The gate insulating layer <NUM> may include for example one layer or two or more layers.

The gate insulating layer <NUM> may have a thickness of about <NUM> to about <NUM>, but is not limited thereto.

The semiconductor layer <NUM> is formed on the gate insulating layer <NUM>. The semiconductor layer <NUM> overlaps with the gate electrode and the gate insulating layer <NUM> interposed therebetween. The semiconductor layer <NUM> may have for example an island shape, but is not limited thereto.

The semiconductor layer <NUM> may be a continuous thin film having a plurality of holes <NUM>. The holes <NUM> may be fine holes penetrated in a thickness direction from one surface of the semiconductor layer <NUM> to the other surface of the semiconductor layer <NUM>. The continuous thin film may be a thin film connected without a breakage from a first side of the semiconductor layer <NUM> to a second surface of the semiconductor layer <NUM> facing the first side of the semiconductor layer <NUM>.

The semiconductor layer <NUM> may have substantially the same morphology as a morphology of the surface of the gate insulating layer <NUM>. Accordingly, the plurality of holes <NUM> of the semiconductor layer <NUM> are disposed corresponding to the plurality of recess portions 141p of the gate insulating layer <NUM>. For example, the recess portions 141p of the gate insulating layer <NUM> and the holes <NUM> of the semiconductor layer <NUM> may be overlapped along a vertical direction of the substrate <NUM>.

For example, referring to <FIG>, the semiconductor layer <NUM> has the plurality of holes <NUM> exposing the gate insulating layer <NUM>, and the recess portions 141p of the gate insulating layer <NUM> may be exposed through the plurality of holes <NUM>.

In a comparative example not forming part of the present invention, referring to <FIG>, the holes <NUM> of the semiconductor layer <NUM> may be randomly arranged. The plurality of recess portions 141p of the gate insulating layer <NUM> may be randomly arranged at the surface of the gate insulating layer <NUM>, as shown in <FIG>.

According to the invention, referring to <FIG>, the holes <NUM> of the semiconductor layer <NUM> are repetitively arranged along a row and/or a column. For example, the holes <NUM> of the semiconductor layer <NUM> may be arranged as a lattice structure. The plurality of recess portions 141p of the gate insulating layer <NUM> may be arranged as a lattice structure, as shown in <FIG>.

For example, referring to <FIG>, the holes <NUM> of the semiconductor layer <NUM> may be rectangular. The plurality of recess portions 141p of the gate insulating layer <NUM> may be rectangular.

In a comparative example not forming part of the present invention, referring to <FIG>, the semiconductor layer <NUM> may have first holes <NUM> and second holes <NUM>' of different sizes and/or shapes. The plurality of recess portions 141p of the gate insulating layer <NUM> may have first recess portions and second recess portions of different sizes and/or shapes.

The semiconductor layer <NUM> may be formed as a continuous thin film having the plurality of holes <NUM> due to the recess portions 141p at the surface of the gate insulating layer <NUM>. Accordingly, the semiconductor layer <NUM> may include a semiconductor having a larger grain size and a less grain boundary than a semiconductor of a semiconductor layer having no hole but a flat surface. Therefore, carrier mobility of the thin film transistor <NUM> may be improved.

The semiconductor layer <NUM> may include a semiconductor material, for example, an inorganic semiconductor material or an organic semiconductor material. For example, the semiconductor layer <NUM> may include an organic semiconductor material.

The organic semiconductor material may be for example a low molecular organic semiconductor material wherein the low molecular organic semiconductor material may be an organic semiconductor material having an average molecular weight of less than or equal to about <NUM>. For example, the organic semiconductor material may be an aromatic compound and/or a heteroaromatic compound. For example, the organic semiconductor material may be a fused polycyclic aromatic compound and/or a fused polycyclic heteroaromatic compound, for example a fused polycyclic aromatic compound such as pentacene and/or a fused polycyclic heteroaromatic compound including at least one O, S, Se, Te, N, or a combination thereof, for example a fused polycyclic heteroaromatic compound including at least one S, Se, Te, or a combination thereof. For example, the organic semiconductor material may be a fused polycyclic aromatic compound and/or a fused polycyclic heteroaromatic compound having a compact planar structure wherein three or more rings are fused with each other, for example a fused polycyclic aromatic compound and/or a fused polycyclic heteroaromatic compound wherein <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> rings are condensed.

For example, the organic semiconductor material may be represented by Chemical Formula 1A or 1B. <CHM>
In Chemical Formulae 1A and 1B,.

The organic semiconductor material represented by Chemical Formula 1A may be for example represented by Chemical Formula 1A-<NUM> and the organic semiconductor material represented by Chemical Formula 1B may be for example represented by Chemical Formula 1B-<NUM>.

In Chemical Formulae 1A-<NUM> and 1B-<NUM>, R<NUM> to R<NUM> are the same as described above.

The organic semiconductor material represented by Chemical Formula 1A or 1B may be for example any one of the following compounds, but is not limited thereto. <CHM>
<CHM>
<CHM>
<CHM>.

In the compounds, Hex, Hep, and Oct are independently a hexyl group, a heptyl group, and an octyl group.

For example, the organic semiconductor material may be represented by Chemical Formula 2A or 2B. <CHM>
<CHM>
In Chemical Formulae 2A and 2B,.

For example, R<NUM> and R<NUM> may be substituted, and may be for example one of a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C7 to C30 arylalkyl group, a substituted or unsubstituted C2 to C30 heteroarylalkyl group, a substituted or unsubstituted C2 to C30 alkylheteroaryl group, a substituted or unsubstituted C5 to C30 cycloalkyl group, or a substituted or unsubstituted C2 to C30 heterocycloalkyl group.

For example, R<NUM> and R<NUM> may be a fluoro-substituted C1 to C30 alkyl group.

For example, Ra may be one of a substituted or unsubstituted C10 to C30 alkyl group, a substituted or unsubstituted C10 to C30 alkoxy group, a substituted or unsubstituted C10 to C30 alkenyl group, or a substituted or unsubstituted C10 to C30 alkynyl group, for another example, a fluoro-substituted C1 to C30 alkyl group, desirably a C1 to C30 perfluoro alkyl group (CnF2n+<NUM>, wherein n is an integer of greater than or equal to <NUM>), or a fluoro-substituted C10 to C30 alkyl group, desirably a C10 to C30 perfluoro alkyl group (CnF2n+<NUM>, wherein n is an integer of <NUM> to <NUM>). in Chemical Formulae 2A and 2B, when n1 is <NUM>, n2 and n3 may be an integer of <NUM>, <NUM>, or <NUM> and when n1 is <NUM>, n1+n2+n3≥<NUM>, for example when n1 is <NUM>, both n2 and n3 may not be <NUM>.

The organic semiconductor material represented by Chemical Formula 2A or 2B may be for example the following compounds, but is not limited thereto. <CHM>
<CHM>
<CHM>
<CHM>
<CHM>
<CHM>.

In the compounds, hydrogen of each phenylene ring, thiophene ring, a selenophene ring, and/or a pyrrole ring may be substituted with one of a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C1 to C30 alkoxy group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C2 to C30 alkynyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C7 to C30 arylalkyl group, a substituted or unsubstituted C2 to C30 heteroarylalkyl group, a substituted or unsubstituted C2 to C30 alkylheteroaryl group, a substituted or unsubstituted C5 to C30 cycloalkyl group, or a substituted or unsubstituted C2 to C30 heterocycloalkyl group.

A surface-modification layer (not shown) may be further formed between the gate insulating layer <NUM> and the semiconductor layer <NUM>. The surface-modification layer may be for example a layer configured to modify the surface characteristics of the gate insulating layer <NUM> to be hydrophobic or hydrophilic and may be for example a self-assembled thin film (a self-assembled monolayer, SAM) including octadecyltrichlorosilane, but is not limited thereto.

The source electrode <NUM> and the drain electrode <NUM> are formed on the semiconductor layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> face each other with the semiconductor layer <NUM> therebetween and may be electrically connected to the semiconductor layer <NUM>. The source electrode <NUM> is electrically connected to the data line (not shown) transferring the data signal. The source electrode <NUM> and the drain electrode <NUM> may be for example made of gold (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), an alloy thereof or a combination thereof.

Hereinafter, a thin film transistor according to another embodiment is described.

<FIG> is a cross-sectional view of a thin film transistor according to another embodiment.

<FIG> is a schematic view showing a cross-section of a gate insulating layer <NUM> in a thin film transistor according to another embodiment.

The thin film transistor <NUM> according to the present embodiment includes a gate electrode <NUM>, a gate insulating layer <NUM>, a semiconductor layer <NUM>, a source electrode <NUM>, and a drain electrode <NUM> like the above embodiment.

However, the thin film transistor <NUM> according to the present embodiment includes different widths of recess portions 141p of the gate insulating layer <NUM> depending on a depth, unlike the above embodiment.

Referring to <FIG>, the recess portions 141p of the gate insulating layer <NUM> may have a different width depending on a depth, for example, the deeper from the surface of the gate insulating layer <NUM>, the wider. For example, the recess portions 141p of the gate insulating layer <NUM> may have each first width a1, a second width a2, and a third width a3 at a surface point, a middle point, and a bottom point, and herein, the second width a2 may be wider than the first width a1, and the third width a3 may be wider than the second width a2.

For example, the first width a1, second width a2, and third width a3 of the recess portions 141p may be independently within a sub-micrometer range, for example, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, respectively in a range of about <NUM> to about <NUM>, or respectively in a range of about <NUM> to about <NUM>.

Hereinafter, a method of manufacturing the thin film transistor according to an embodiment is described.

<FIG> are cross-sectional views showing a manufacturing method of the thin film transistor of <FIG>.

Referring to <FIG>, a conductive layer (not shown) for a gate electrode is deposited on a substrate <NUM> and treated through photolithography to form a gate electrode <NUM>.

Referring to <FIG>, a thin film <NUM> for a gate insulating layer is formed on the whole surface of the substrate <NUM> including the gate electrode <NUM>. The thin film <NUM> for the gate insulating layer may be for example formed by depositing or coating silicon oxide (SiO<NUM>), silicon nitride (SiNx), aluminum oxide (Al<NUM>O<NUM>), or an organic insulator. The depositing may be for example a chemical vapor deposition (CVD), a vacuum deposition, thermal evaporation, a laser deposition, or a solution process. The solution process may be one of a spin coating, a screen printing, a printing, an imprinting, a spin casting, a dipping, a roll coating, a drop casting, a spray coating, a roll printing, a slit coating, or inkjet printing, but are not limited thereto.

Subsequently, recess portions 141p are formed at the surface of the thin film <NUM> for the gate insulating layer to form a gate insulating layer <NUM>.

For example, the gate insulating layer <NUM> may be formed by photolithography or a different patterning process. Photolithography may be used to pattern the thin film <NUM> into the gate insulating layer <NUM>.

Referring to <FIG>, a photoresist is coated on the thin film <NUM> for the gate insulating layer to form a photoresist thin film <NUM>.

Subsequently, a mask <NUM> is disposed on the photoresist thin film <NUM> and then, the photoresist film <NUM> is exposed. The mask <NUM> has a transmission portion 60a transmitting light and a non-transmission portion 60b not transmitting light. The transmission portion 60a may be disposed to correspond to a place where the recess portions 141p of the gate insulating layer <NUM> are formed.

Referring to <FIG>, the mask <NUM> is removed and then the photoresist thin film <NUM> in exposed region is developed and removed to form a photoresist pattern 50a.

Referring to <FIG>, the thin film <NUM> for the gate insulating layer is patterned using the photoresist pattern 50a as a mask to form the gate insulating layer <NUM> having the plurality of recess portions 141p.

For another example, the gate insulating layer <NUM> having the plurality of recess portions 141p may be formed by an electron beam (e-beam) lithography.

For another example, the gate insulating layer <NUM> having the plurality of recess portions 141p may be formed by an imprinting process.

Subsequently, the gate insulating layer <NUM> optionally may be surface-modified, for example, by arranging a hydrophilic or hydrophobic self-assembled thin film (not shown) to further form a surface-modification layer (not shown) on the surface of the gate insulating layer <NUM>.

Referring to <FIG>, the semiconductor layer <NUM> is formed on the gate insulating layer <NUM>.

For example, the semiconductor layer <NUM> may be for example formed by depositing or coating a semiconductor material. The depositing may be for example a chemical vapor deposition (CVD), a vacuum deposition, thermal evaporation, or a laser deposition and the coating may be for example a spin coating, a screen printing, printing, an imprinting, a spin casting, dipping, a roll coating, a drop casting, a spray coating, a roll printing, a slit coating, or an inkjet printing, but are not limited thereto.

When the semiconductor material is deposited or coated, the semiconductor material is formed exclusively on the surface of the gate insulating layer <NUM>, and thus the semiconductor layer <NUM> may be formed to have substantially the same morphology as morphology of the surface of the gate insulating layer <NUM>. Accordingly, the semiconductor layer <NUM> may be formed exclusively on the surface of gate insulating layer <NUM> except for the recess portions, and accordingly, empty spaces, the holes <NUM>, may be formed at a place corresponding to the recess portions 141p of the gate insulating layer <NUM>. Otherwise, when the semiconductor material is deposited or coated, a part of the semiconductor material may flow unintentionally into the recess portions 141p, wherein the semiconductor material that flowed into the recess portions 141p (see <FIG> illustrating a part of the semiconductor material <NUM> that flowed into the recess portions 141B) is not connected to the semiconductor material <NUM> on the surface of the gate insulating layer <NUM> due to a step between the surface of the gate insulating layer <NUM> and the bottom surface of the recess portions 141p and thus may have no influence on a function of the semiconductor layer <NUM>.

Referring to <FIG>, a conductive layer for source and drain electrodes is disposed on the semiconductor layer <NUM> and photo-etched to form the source electrode <NUM> and the drain electrode <NUM>. Otherwise, the source electrode <NUM> and the drain electrode <NUM> are deposited on the semiconductor layer <NUM> by using a metal mask.

Although a thin film transistor having a bottom gate structure is discussed as an example, inventive concepts are not limited thereto and may be applied to all thin film transistors.

The thin film transistor <NUM> may be included in each pixel defined by a gate line <NUM> and a data line <NUM>, and each pixel may include one or at least two thin film transistors <NUM>.

A thin film transistor array display panel, in which a plurality of thin film transistor <NUM> may be arranged along a row and/or a column, may include the substrate <NUM>, the gate line <NUM> and the data line <NUM> formed on the substrate <NUM>, crossing each other, and defining a plurality of pixels, and the above thin film transistor <NUM> connected to the gate line <NUM> and the data line <NUM> and disposed in each pixel.

The thin film transistor <NUM> may be applied to a switching or driving device of various electronic devices, and the electronic device may be, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display device, an organic sensor, or a wearable device.

<FIG> is schematic views showing arrangements of recess portions of the gate insulating layer in an electronic device according to an embodiment, and <FIG> is schematic views showing arrangements of holes of the semiconductor layer in an electronic device according to an embodiment.

Referring to <FIG> and <FIG>, an electronic device may include a first region I and a second region II. The density of recess portions 141p of the gate insulating layer <NUM> and holes <NUM> of the semiconductor layer <NUM> may be different in the first region I and the second region II of the substrate in order to form thin film transistors having different charge mobility.

However, these examples are non-limiting, and inventive concepts are not limited thereto.

A <NUM>-thick gate insulating layer is formed on a silicon wafer substrate by thermally evaporating SiO<NUM>. Subsequently, a plurality of recess portions is formed at the surface of the gate insulating layer by using electron beam lithography (JBX-<NUM>, JEOL Inc. The plurality of recess portions is arranged as a lattice structure, and herein, each recess portion has a width of about <NUM>, a depth of about <NUM>, and an interval of about <NUM> among the neighboring recess portions. Subsequently, the surface of the gate insulating layer is modified by dipping the substrate in a solution for a self-assembled thin film prepared by diluting octadecyltrichlorosilane (ODTS) in a concentration of <NUM> in hexane and then, allowing the substrate to stand for one hour. Then, a <NUM> A-thick semiconductor layer is formed by vacuum-depositing an organic semiconductor represented by Chemical Formula A on the gate insulating layer. On the semiconductor layer, a <NUM> A-thick source electrode and a <NUM>Å-thick drain electrode is formed by depositing gold (Au) using a metal mask to manufacture a thin film transistor. The thin film transistor has a channel width of about <NUM> and a channel length of about <NUM>.

A thin film transistor is manufactured according to the same method as Example <NUM> except for changing the interval among the neighboring recess portions of the gate insulating layer into about <NUM>. The thin film transistor has a channel width of about <NUM> and a channel length of about <NUM>.

A thin film transistor is manufactured according to the same method as Example <NUM> except for not forming the recess portions at the surface of the gate insulating layer. The thin film transistor has a channel width of about <NUM> and a channel length of about <NUM>.

The surfaces of the gate insulating layer and the semiconductor layer in the thin film transistors according to Examples <NUM> and <NUM> are examined.

The surfaces of the gate insulating layer and the semiconductor layer are examined by using Atomic Force Microscopy (Dimension Icon, Bruker).

<FIG> shows an atomic force microscope (AFM) analysis image of the gate insulating layer in the thin film transistor according to Example <NUM>, <FIG> shows an AFM analysis image of the semiconductor layer in the thin film transistor according to Example <NUM>, <FIG> shows an AFM analysis image of the gate insulating layer in the thin film transistor according to Example <NUM>, and <FIG> shows an AFM analysis image of the semiconductor layer in the thin film transistor according to Example <NUM>.

Referring to <FIG> and <FIG>, the recess portions of the gate insulating layer in the thin film transistor according to Example <NUM> are formed as a lattice structure, and in addition, holes of the semiconductor layer are formed.

Referring to <FIG> and <FIG>, the recess portions of the gate insulating layer in the thin film transistor according to Example <NUM> are formed as a more compact lattice structure than the recess portions of the gate insulating layer in the thin film transistor according to Example <NUM>, and in addition, holes of the semiconductor layer are formed to be much closer.

Charge mobility of the thin film transistors according to Examples <NUM> and <NUM> and Comparative Example <NUM> are evaluated.

The charge mobility is obtained from a slope of a graph having variables of (ISD)<NUM>/<NUM> and VG, which is obtained from a saturation region current formula. <MAT> <MAT> <MAT> <MAT>.

In the equations, ISD is a source-drain current, µ or µFET is the charge mobility, C<NUM> is capacitance of a gate insulating layer, W is a channel width, L is a channel length, VG is a gate voltage, and VT is a threshold voltage.

Claim 1:
A thin film transistor (<NUM>), comprising
a gate electrode (<NUM>),
a semiconductor layer (<NUM>) overlapped with the gate electrode, the semiconductor layer including a plurality of holes (<NUM>),
a gate insulating layer (<NUM>) between the gate electrode and the semiconductor layer, the gate insulating layer including a plurality of recess portions (141p) at a surface of the gate insulating layer facing the semiconductor layer, and
a source electrode (<NUM>) and a drain electrode (<NUM>) electrically connected to the semiconductor layer,
wherein
the plurality of holes of the semiconductor layer correspond to the plurality of recess portions of the gate insulating layer,
a depth of the recess portions is <NUM> % or less of a thickness of the gate insulating layer, and
the plurality of recess portions of the gate insulating layer are repetitively arranged according to a column or a row at the surface of the gate insulating layer facing the semiconductor layer.