Patent Description:
<NPL> discloses a multiphase delay locked loop with duty cycle corrector.

<NPL> discloses a clock skew compensation and duty-cycle correction circuit for clock signals.

<CIT> of Application <CIT>, entitled "Quadrature and Duty Cycle Correction in Matrix Phase Lock Loop", hereinafter referred to as [Tajalli I].

The present invention relates to communications systems circuits generally, and more particularly to obtaining stable, correctly phased receiver clock signals from a high-speed multi-wire interface used for chip-to-chip communication.

In modem digital systems, digital information has to be processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information.

In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards ("PCBs") boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used.

Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as "encoding". The encoded codeword is communicated as a group of signals from the transmitter to one or more receivers. At a receiver, the received signals corresponding to the codeword are transformed back into the original digital information representation space. Herein, this process is referred to as "decoding".

Regardless of the encoding method used, the received signals presented to the receiving device must be sampled (or their signal value otherwise recorded) at intervals best representing the original transmitted values, regardless of transmission channel delays, interference, and noise. This Clock and Data Recovery (CDR) not only must determine the appropriate sample timing, but must continue to do so continuously, providing dynamic compensation for varying signal propagation conditions.

Many known CDR systems utilize a Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) to synthesize a local receive clock having an appropriate frequency and phase for accurate receive data sampling. In advanced embodiments, multiple local clocks with particular phase relationships may be generated, as one example to permit overlapping or parallel processing of received information by multiple instances of the receiver embodiment.

Data receivers require accurately adjusted local clocks to enable accurate signal detection, and advanced receiver designs may require generation of multiple clock phases, collectively having particular relationships with the received data signals, and fixed phase relationships among each other.

A common receiver clock subsystem utilizes a phase-locked loop (PLL) to produce a local clock having the desired frequency and phase relationship with a reference signal, generally obtained with or derived from the received data. Within the PLL, a voltage-controlled oscillator based on a ring-connected sequence of active elements conveniently produces multiple clock phases in a fixed relationship. However, variations among the ring's active elements can also induce periodic clock variations and thus result in undesirable duty cycle variations as well as skew between output clock phases.

A configurable clock buffer chain is described, allowing adjustment of clock duty cycle and overall delay by internally modifying the rise and fall time of signals propagating between buffer stages. These buffers are combined with a measurement subsystem capable of directly measuring clock duty cycle and inter-phase skew, to provide clean, accurately timed multiphase clock signals to the data receiver.

To reliably detect the data values transmitted over a communications system, a receiver must accurately measure the received signal value amplitudes at carefully selected times. Various methods are known to facilitate such receive measurements, including reception of one or more dedicated clock signals associated with the transmitted data stream, extraction of clock signals embedded within the transmitted data stream, and synthesis of a local receive clock from known attributes of the communicated data stream. In general, the receiver embodiments of such timing methods are described as Clock-Data Recovery (CDR) or alternatively as performing Clock-Data Alignment (CDA). These timing methods are often based on Phase-Lock Loop (PLL) or Delay-Locked Loop (DLL) synthesis of a local receive clock having the desired frequency and phase characteristics.

In both PLL and DLL embodiments, a Phase Detector compares the relative phase (and in some variations, the relative frequency) of a received reference signal and a local clock signal to produce an error signal, which is subsequently used to correct the phase and/or frequency of the local clock source and thus minimize the error. As this feedback loop behavior will lead to a given PLL embodiment producing a fixed phase relationship (as examples, <NUM> degrees or <NUM> degrees of phase offset) between the reference signal and the local clock, an additional fixed or variable phase adjustment is often introduced to permit the phase offset to be set to a different desired value (as one example, <NUM> degrees of phase offset) to facilitate receiver data detection.

Advanced receiver embodiments may require the generation of two or more local clocks having particular phase relationships. As one example, a so-called "four phase" embodiment incorporates four instances of detection apparatus configured to operate on consecutive unit intervals of the received signal, with the resulting parallelism providing extended detection time. In such a system, four phases of local clock signals may be required having a fixed frequency and phase relationship to the reference signal, and also having fixed relationships to each other.

Phase Locked Loops are well represented in the literature. A typical PLL is composed of a phase detector that compares an external reference signal to an internal clock signal, a low pass filter that smooths the resulting error value to produce a clock control signal, and a variable frequency clock source (typically, a Voltage Controlled Oscillator or VCO) controlled by the smoothed error value, producing the internal clock signal presented to the phase detector.

In an alternative embodiment, the variable frequency clock source is replaced by a variable delay element, its (optionally multiple tapped) outputs thus representing one or more successive time-delayed versions of the original input signal rather than successive cycles of an oscillator to be phase compared to the reference input signal. For the purposes of this document, such Delay Locked Loops (DLL) are considered functionally equivalent to a PLL in such an application, and the tapped variable delay element of a DLL functionally equivalent to the ring of delay elements in a PLL ring-oscillator VCO.

In one embodiment, a ring oscillator composed of a sequence of identical gates in a closed loop is used as the internal Voltage Controlled Oscillator (VCO) timing source for the PLL. The VCO frequency is varied by analog adjustment of at least one of gate propagation delay, inter-gate rise and fall time, and gate switching threshold within the ring oscillator. As examples, the supply voltage or current provided to the ring oscillator elements may be adjusted to modify internal node switching time and thus the resulting oscillation frequency. Outputs taken at equal intervals (i.e. separated by equal numbers of ring oscillator gates) along the sequence of gates comprising the ring oscillator can provide multi-phase clocks having a fixed phase relationship. Such ring oscillators are well represented in the art, typically comprised of three to eight or more elements typically embodied as digital inverters, with both single-ended and differential signal variations described in the literature.

The example embodiment illustrated in <FIG> incorporates ring oscillator <NUM> to generate clock signals VCO Phase <NUM> and VCO Phase <NUM>. In this example, <NUM> utilizes three differential delay elements (shown here as differential inverters) connected in a ring, with the two VCO clock outputs having a fixed <NUM> degree phase relationship with each other.

It is known that periodic variations in edge timing of a receiver's local clock signals can lead to degraded signal detection quality, thus it is extremely desirable to minimize these effects. In the example of <FIG>, Clock Phase <NUM> and Clock Phase <NUM> are ideally perfect square waves of constant frequency, with exact <NUM>% duty cycles and zero differential phase error or "skew. " In practice, however, it is recognized that unavoidable variations among the ring oscillator elements can result in asymmetric output waveforms and periodic timing variations.

[Tajalli <NUM>] describes a ring oscillator embodiment in which multiple ring oscillator output phases are compared against each other using a matrix phase detector. The resulting differential phase error information is used to incrementally adjust the delay of each ring oscillator element, above and beyond the overall frequency and phase error correction applied to the ring oscillator as a whole by the primary PLL phase detector.

One embodiment of the system shown in <FIG> includes a ring oscillator operating at frequencies near the practical limits of the integrated circuit process used. Thus, a minimal three-stage ring was designed, with an extremely tight physical layout to minimize parasitic node capacitance. In this design, the extra metallization lines needed to bring in individual delay controls for each stage, and the additional loading introduced by bringing out individual ring phases for matrix comparison, introduced unacceptable constraints on the desired maximum VCO operating frequency.

Instead of directly manipulating ring oscillator elements, the system of <FIG> processes selected clock outputs Clk<NUM> and Clk<NUM> selected via clock selection circuit <NUM> using configurable buffer chains <NUM> and <NUM>, allowing each output clock Clock Phase <NUM> and Clock Phase <NUM> to be brought to the desired <NUM>% duty cycle and zero differential phase before use by the receiver system. In some embodiments, the sources used to generate Clk<NUM> and Clk<NUM> may be selected via the clock selection circuit <NUM>, shown in <FIG> as a differential multiplexer. Such a clock selection circuit may have inputs from the VCO <NUM> and inputs provided via a phase interpolator (PI) <NUM> that may be operating e.g., on outputs of the VCO. Thus, the duty cycle and delay correction circuit may be shared between the "main" clocks and the "PI" clocks. For descriptive simplicity, Clk<NUM> and Clk<NUM> are assumed to be full-swing CMOS clock signals with a <NUM>-degree phase offset with no limitation implied.

Measurement subsystem <NUM> observes the resulting outputs Clock Phase <NUM> and Clock Phase <NUM>, measuring individual clock duty cycles Clk1_duty and Clk2_duty respectively, and the differential clock offset between Clk<NUM> and Clk<NUM>, denoted Clk_skew. In some embodiments, the delay correction Clk_skew may include a rising-edge to rising-edge (RE-to-RE) component and a falling-edge to falling-edge (FE-to-FE) component. The control logic <NUM> provides multi-bit control signals for adjusting stages <NUM>, <NUM>, and <NUM> in configurable clock buffer chains <NUM> and <NUM> to maintain the desired result at their outputs. <FIG> is a block diagram of an exemplary control logic <NUM>, in accordance with some embodiments.

As shown, control logic <NUM> includes a selection circuit <NUM>, shown in <FIG> as a multiplexer. The multiplexer may be a differential multiplexer configured to receive differential inputs corresponding to (i) the duty cycle corrections for the first and second clock signals Clk1_duty and Clk2_duty, respectively, and delay corrections generated from the inter-phase comparison of the edge-triggered half-rate clocks, shown as FE-to-FE_delay and RE-to_RE_delay. The selection circuit <NUM> may be configured to incrementally select the inputs, and to provide the selected input to a shared low-pass filter. The filtered result may be provided to control signal generator <NUM>, which generates the multi-bit control signals EnP<<NUM>:<NUM>>, EnN<<NUM>:<NUM>>, EnPb<<NUM>:<NUM>> and EnNb<<NUM>:<NUM>>. The control signal generator <NUM> may be configured to synchronize the multi-bit control signals according to a digital flag syn_dig and a two UI clock Clk_2ui. <FIG> is a block diagram of an exemplary control signal generator <NUM>, in accordance with some embodiments. <FIG> illustrates waveforms of an incremental update process, in accordance with some embodiments.

<FIG> shows additional details of measurement system <NUM>. If inputs Clk<NUM> and Clk<NUM> are full-swing <NUM>% duty cycle CMOS signals, their time-averaged DC/common mode level will be Vdd/<NUM>, or one-half of the total signal excursion. For the first clock signal Clk<NUM>, Low-pass filter <NUM> performs such a time-averaging operation, with analog result <NUM> representing the average DC level of the first clock signal. Comparator <NUM> compares <NUM> to a fixed DC reference of Vdd/<NUM>, with the duty cycle correction Clk1_duty indicating whether the duty cycle of the first clock signals Clk<NUM> is greater than, or less than the desired <NUM>% value. Similarly, Low-pass Filter <NUM> generates the analog result <NUM> representing the average DC level of the second clock signal and Comparator <NUM> compares <NUM> to the reference voltage Vdd/<NUM> to produce duty cycle correction Clk2_duty. A <NUM>% duty cycle approach should not be considered limiting, and another appropriate fixed DC reference may be set for inputs having a different desired duty cycle or different voltage swing.

Digital divide-by-<NUM> flip-flops <NUM> and <NUM> produce rising-edge (RE) and/or falling-edge (FE) triggered half-rate square wave signals <NUM> and <NUM> from rising/falling edges respectively of Clk<NUM> and Clk<NUM> which are then compared by phase detector <NUM>, shown here as a simple XOR gate. In some embodiments, both RE and FE triggered half-rate clocks are generated, while alternative embodiments may utilize a single edge-triggered half-rate clock to reduce convergence time for duty cycle and clock skew. <FIG> illustrates various waveforms generated for duty cycle corrections between rising edges of Clk<NUM> and Clk<NUM>, in accordance with some embodiments. As shown, Clk<NUM> and Clk<NUM> have a rising-edge to rising-edge delay that is greater and a single unit interval (UI). Edge-triggered half-rate clocks are generated for each of Clk<NUM> and Clk<NUM>, shown as Clk<NUM>/<NUM> and Clk<NUM>/<NUM>, respectively. An inter-phase comparison is formed by taking a logical XOR of the edge-triggered half-rate clocks. As shown in <FIG>, the inter-phase comparison has a duty cycle > <NUM>%, indicative of the ><NUM> UI delay between the rising edges in Clks <NUM> and <NUM>. Such a delay correction may then be applied to elements controlling the rising edges of Clks <NUM> and <NUM>, described in more detail below. As Clk<NUM> and Clk<NUM> in this example have a <NUM>-degree phase differential, clocking the divide-by-<NUM> flops with the same edge (e.g. rising clock edge) of both clocks will result in edge-triggered half-rate clock signals having a <NUM>-degree phase differential, absent any skew in the original clock signals. Thus, delay correction <NUM> will ideally be a perfect square wave of <NUM>% duty cycle with any skew between the input clocks presented as a duty cycle error in the delay correction which may be measured as previously described, using low-pass filter <NUM> and comparator <NUM> to produce delay correction Clk_skew. To ensure a valid result, dividers <NUM> and <NUM> may be initialized to a known state at startup (as one example, such that that first positive-going transition of <NUM> will precede the first positive-going transition of <NUM>) to ensure the desired phase relationship between their outputs can be observed. <FIG> includes the resulting interphase comparison of Clki'/<NUM> XOR'd with Clk<NUM>/<NUM> that may occur absent any start up initialization. As shown, the duty cycle of the resulting erroneous waveform is <<NUM>%. Again, no limitation is implied, as a different desired clock phase relationship may be targeted by appropriate initialization of the divider initial state, transitioning edge, and/or DC comparison value for the resulting low-pass-filtered result.

One embodiment of <NUM> minimizes measurement errors by implementing all signals and signal processing elements differentially, with identical loading on both signal paths in each differential pair. Thus, as examples, differential signal Clk1 passes through a differential R-C low pass filter <NUM> to differential comparator <NUM>. <FIG> is a block diagram of one particular implementation of divider <NUM> operating on clock signal Clk1, in accordance with some embodiments. As shown, divider <NUM> includes a true single-phase clock (TSPC) divider <NUM> configured to generate singled-ended half-rate clock Clk<NUM>/<NUM> from single-ended clock signal Clk1. Divider <NUM> further includes an inverter <NUM> configured to generate an inverted version Clk<NUM>/<NUM> of the single-ended half-rate clock signal Clk<NUM>/<NUM>. The two single-ended half-rate clocks Clk<NUM>/<NUM> and Clk<NUM>/<NUM>' may then be retimed using a retiming circuit <NUM> according to the input clock signal Clk<NUM>. Divider <NUM> operating on Clk2 may include similar elements. The differential edge-triggered half-rate clocks <NUM> and <NUM> are inter-phase compared by differential phase comparator <NUM> before being low-pass filtered <NUM> and compared <NUM>. In at least one embodiment, the corner frequency of each low pass filter is set approximately <NUM> times lower than the clock frequency to provide a desired amount of DC averaging. In a further embodiment, two-stage low pass filters are used, a first filter having a corner frequency <NUM> to <NUM> times lower than the clock frequency, with its result directed to a second filter providing the remainder of the desired amount of DC averaging. In some embodiments, the second filter and measurement comparator are shared among multiple first filters and measurement points using an analog multiplexor, eliminating the need for multiple instances of the substantial second filter capacitance.

<FIG> details the internals of a configurable buffer chain, in accordance with some embodiments. In this embodiment, a series of digital inverters <NUM>, <NUM>, <NUM> amplify and buffer an input signal, resulting in an output suitable for driving a greater load and/or longer signal lines within an integrated circuit device. In some embodiments, the size of the transistors composing the inverter stages are scaled proportionately larger across the buffer chain, balancing increased drive capability with increased capacitive loading on the previous output stage. As one non-limiting example, the transistors within <NUM> may be twice the size and current-drive capability of those in <NUM>, and those of <NUM> twice those of <NUM>.

As illustrated in <FIG>, the second stage of the buffer chain is composed of inverter <NUM>, paralleled by seven instances of configurable augmentation inverter <NUM>. As shown, each instance of <NUM> contains a pull-up transistor <NUM> and pull-down transistor <NUM> controlled by the same input signal as <NUM>, and capable of driving the same output signal as <NUM>. Enabling element <NUM>, shown here as a switch, may be configured by control signal EnP to place pull-up transistor <NUM> into the active signal path, or to keep it isolated. In one representative embodiment, <NUM> and <NUM> are series MOS transistors. Similarly, control signal EnN controls enabling element <NUM>, which may be configured to place pull-down transistor <NUM> into the active signal path, or keep it isolated. Enabling pull-up transistors <NUM> and pull-down transistors <NUM> may adjust the rising and falling edges of the eventual output signal Out of final output buffer stage <NUM>. It should be noted that as there is a signal inversion at each stage of the illustrated buffer chain <NUM>, <NUM>, <NUM>, the absolute clock edge associated with a "rising" and "falling" local signal edge will similarly reverse at each stage. For example, pull-up transistors <NUM> in stage <NUM> and pull-down transistors <NUM> in stage <NUM> may control the rising edge of the output signal Out (via enable signals EnP<<NUM>:<NUM>> and EnPb<<NUM>:<NUM>>, respectively) while pull-down transistors <NUM> in stage <NUM> and pull-up transistors <NUM> in stage <NUM> may control the falling edge of the output signal Out (via enable signals EnN<<NUM>:<NUM>> and EnNb<<NUM>:<NUM>>, respectively), or vice versa depending on the total number of buffer stages. Furthermore, pull-up transistors <NUM> and pull-down transistors <NUM> in stage <NUM> may include multiple transistors connected in parallel, increasing the effective size with respect to the transistors in stage <NUM>.

<FIG> and <FIG> illustrate exemplary behavior of instances <NUM>, in accordance with some embodiments. As transistors <NUM> are enabled via EnP and transistors <NUM> are disabled via EnN, the duty cycle of the output signal Out increases due to the decrease in rise time of the rising edge and the increase in fall time of the signal on node <NUM>, as shown in <FIG>. Similarly, disabling transistors <NUM> and enabling transistors <NUM> may decrease the duty cycle of the output signal Out. <FIG> illustrates a mechanism for correcting rising-edge to rising-edge delay between Clks <NUM> and <NUM>. As shown, disabling transistors <NUM> in the buffer generating Clk1 and enabling transistors <NUM> in the buffer generating Clk2 increases the rise time for Clk1 and decreases the rise time for Clk2, respectively. Such adjustments may create a one-unit interval alignment between the rising edges of clock signals Clk1 and Clk2.

When both EnP and EnN are enabled in a given parallel stage <NUM>, stage <NUM> acts in parallel with <NUM> to provide an increased output drive current for both rising and falling edges of signal transitions on node <NUM>, thus incrementally reducing the effective overall propagation delay of <NUM>. Enabling only EnP provides increased drive (and thus, a faster transition time,) only for rising transitions, and enabling only EnN provides increased drive (and thus, faster transition time,) only for falling transitions. Other characteristics remaining constant, a faster rising transition time will incrementally increase the duration of active high levels of signal <NUM>, and a faster falling transition time will incrementally increase the duration of active low levels of signal <NUM>.

Seven parallel instances of <NUM> are shown, thus if control signals EnP<<NUM>:<NUM>> and EnN<<NUM>:<NUM>> are thermometer-coded, seven distinct amounts of augmentation may be configured for each of the rising and falling edge rates seen at node <NUM>. Similarly, the seven instances of <NUM> can be configured to augment <NUM>, using control signals EnP<<NUM>:<NUM>> and EnN<<NUM>:<NUM>>.

In one embodiment, transistors <NUM> and <NUM> within <NUM> are twice the size and current drive capability of the comparable transistors <NUM> and <NUM> in stage <NUM>. As the transistors in <NUM> are themselves scaled to be twice the size of those in <NUM>, one may observe that each step of augmentation provided by <NUM> may be 4x (assuming a 2x increase per stage) that provide by <NUM>, thus EnP<<NUM>:<NUM>> and EnN<<NUM>:<NUM>> may be considered as "coarse" adjustment controls, and EnPb<<NUM>:<NUM>> and EnNb<<NUM>:<NUM>> as "fine" adjustment controls over the rising and falling edge characteristics of the signals being buffered by their respective stages.

As the "fine" and "coarse" control signals are thermometer-encoded where they are applied to each augmentation group, incremental control signal changes within each group are glitch-free. One particular embodiment insures that concurrent changes to both fine and coarse control signals are synchronized, by latching all control signals using a common clock. A further embodiment changes the amount of augmentation for a given edge transition only when the drivers for that edge are inactive. <FIG> illustrates such a mechanism for ensuring glitch-free incremental changes utilizing a digital flag syn_dig to latch the outputs of most significant bits gray _msb<<NUM>:<NUM>> and least significant bits gray _lsb<<NUM>:<NUM>> prior to being converted to corresponding thermometer coded bits th<<NUM>:<NUM>>.

In one embodiment, a finite state machine within the measurement subsystem initiates duty cycle and skew measurements, interprets the results, and adjusts the configurable clock buffer chains to minimize duty cycle and skew errors. To reduce power utilization, the measurement subsystem may operate periodically, rather than continuously. The finite state machine may perform duty cycle corrections for clock <NUM>, duty cycle corrections for clock <NUM> duty cycle, and delay corrections for rising-edge to rising-edge and/or falling-edge to falling-edge delay corrections sequentially. <FIG> illustrates various steps of such a sequential operation. As shown, control signals '<NUM>', '<NUM>', '<NUM>', and '<NUM>' may correspond to a two-bit input to a selection circuit, e.g., a multiplexor in control logic <NUM>. In the embodiment of <FIG>, a selection input of '<NUM>' corresponds to falling-edge to falling-edge (FE-to-FE) delay corrections between clocks Clk1 and Clk2, a selection input of '<NUM>' corresponds to duty cycle correction of Clk1, a selection input of '<NUM>' corresponds to a duty cycle correction of Clk2, and a selection input of '<NUM>' corresponds to rising-edge to rising-edge (RE-to-RE) delay corrections between clocks Clk1 and Clk2. As shown, the system corrects duty cycle and delays between Clk1 and Clk2 in approximately <NUM> microsecond. In some embodiments, the finite state machine may perform a single set of delay corrections. For example, one particular embodiment may perform duty cycle corrections for Clk1 and Clk2, and perform only FE-to-FE delay corrections between clocks Clk1 and Clk2, and thus it may be assumed that the RE-to-RE delays are inherently corrected by the FE-to-FE delay corrections. Conversely, another embodiment may perform RE-to-RE delay corrections, and thus it is assumed that the FE-to-FE delays are inherently corrected. In such embodiments, either FE-to-FE or RE-to-RE delay corrections may be chosen based on what edge type a particular critical path of a circuit is operating on.

In the receiver embodiment illustrated in <FIG>, one level of speculative DFE is generated, thus two data detection samplers (e.g. <NUM>, <NUM>) are provided within each processing slice <NUM> and <NUM>, each adjusted to a different speculative DFE correction threshold, including a positive DFE correction threshold +vh1 used to generate data when the previous data decision was a '<NUM>', and a negative DFE correction threshold -vh1 used to generate data when the previous data decision was a '<NUM>'. The embodiment of <FIG> also incorporates two essentially parallel receive processing slices <NUM>, <NUM>, each processing the received signal <NUM> on alternating receive unit intervals using e.g., sampling clock phases ph000 and ph180 which may correspond to Clk1 and Clk2 above, respectively. As the samplers <NUM>, <NUM>, <NUM>, and <NUM> may represent critical paths in the receive signal processing path, the duty cycle correction circuit may prioritize corrections made on the edge type for which the samplers are sampling data on. Specifically, if samplers <NUM>/<NUM> and <NUM>/<NUM> are operating on the falling edges of ph000 and ph180, respectively, then the finite state machine described above my perform FE-to-FE delay corrections. Conversely, if samplers <NUM>/<NUM> and <NUM>/<NUM> are operating on the rising edges of ph000 and ph180, respectively, then the finite state machine described above my perform RE-to-RE delay corrections.

The set of speculative DFE compensation values representing the constellation of potential detected data results over the previous transmit unit interval or intervals represent a set of measurement levels spanning some portion of the receive signal amplitude range. As an example, previous transmission of consecutive "zero" or "low" signals might lead to a predicted lower threshold level -vh1 for a subsequent receiver data measurement incorporating speculative DFE compensation, while previous transmission of consecutive "one" or "high" signals might lead to a predicted higher threshold level +vh1 for the same data measurement. Thus, for any data measurement used to detect an actual data value, the described multiple-sampler receiver will potentially perform measurement operations using thresholds either too high or too low for the actual signal during that interval. In some embodiments, these measurement operations from the samplers or comparators performing such speculative operations not directly associated with the actual data detection, although not used for determining the received data value, may nonetheless be used to obtain new information relating to clock recovery, thus mitigating the additional receiver power and complexity those devices add to the receiver.

Consider the processing of a receive signal in the present unit interval by processing slice <NUM>. Under control of clock Ph180, samplers <NUM> and <NUM> capture the state of the received signal <NUM> relative to speculative DFE thresholds +vh1 and - vh1. When the correct data decision for the previous unit interval has been resolved by processing slice <NUM>, the data decision may be provided to digital multiplexer <NUM> as a selection input to select one of the speculative sampler results <NUM> or <NUM>. Similarly, the selected data decision at the output of digital multiplexer <NUM> may be provided as a selection input to digital multiplexer <NUM>.

In a first startup mode, the duty cycle of each clock is rapidly optimized by simultaneously modifying both the rise time and the fall time configuration of its respective buffer chain after each measurement cycle. The skew between the two clocks is adjusted by modifying both the first and second clock rise times after each measurement cycle.

In a second operational mode, the duty cycle of each clock is adjusted non-intrusively, by incrementally modifying only the falling edge characteristics of the clock buffers after each measurement cycle. If required, the skew between the two clocks is adjusted by incrementally modifying the rise time for one clock or the other.

To minimize the number of control signals needing to be routed, the measurement subsystem outputs binary control values. A gray code is used to minimize glitching when incrementally increasing or decreasing a control value. The more-significant and less-significant portions of the control value are locally converted using Boolean logic from gray code to thermometer code to control enabling of driver elements in <NUM> and <NUM>, respectively. Clocked latches synchronize changes between more-significant and less-significant portions of the control value to minimize glitching.

Claim 1:
A method comprising:
generating edge-triggered half-rate clocks, each edge-triggered half-rate clock (<NUM>, <NUM>) generated from a divider (<NUM>, <NUM>) operating responsive to rising or falling edges of a corresponding first (Clk<NUM>) or second (Clk<NUM>) clock signal;
generating a set of multi-bit control signals, each multi-bit control signal having coarse and fine components for adjusting a rising edge and a falling edge of a respective clock signal of the first and second clock signals, each multi-bit control signal incrementally updated responsive to a selection of:
a duty cycle correction of the respective clock signal generated responsive to a comparison (<NUM>, <NUM>) of a common mode signal (<NUM>, <NUM>) associated with the respective clock signal to a reference voltage; and
delay corrections between the first and second clock signals, the delay corrections generated responsive to inter-phase comparisons between the edge-triggered half-rate clocks; and
adjusting respective coarse and fine inverter stages of a set of clock buffers generating the first and second clock signals according to the coarse and fine components of the set of multi-bit control signals, respectively.