Patent Description:
Modern computing systems comprise numerous electronic components such as Graphics Processing Units (GPUs), Central Processing Units (CPUs), Random-Access Memory (RAM), etc. As a computing system becomes more complex to support demand from users for computing and other applications, multiple GPUs and/or CPUs are often required within the same computing system.

Traditionally, computing systems are designed with a fixed Peripheral Component Interconnect Express (PCIe) topology to support multiple GPUs and CPUs. A user of a computing system cannot change the PCIe topology of the computing system. However, a specific PCIe topology that is ideal for a particular application may be inefficient for some other applications (e.g., other GPU applications).

<CIT> describes a method of operating a data processing system, which includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric.

<CIT> describes a host computer, which comprises a PCI-express expansion part connected to the said host computer and provides a computer system with a reduced slot without depending on the number of host computers.

Systems and methods, in accordance with various examples of the present disclosure, provide a solution to the above-mentioned problems by enabling a flexible PCIe topology in a computing system. The flexible PCIe topology can allow a user or a management controller of the computing system to adjust PCIe connections between CPUs and components of the computing system based upon a specific application. In some implementations, the computing system comprises a plurality of CPUs, a plurality of GPUs or Field-Programmable Gate Arrays (FPGAs), a plurality of PCIe switches, and a plurality of network interface controllers (NICs). In some implementations, the computing system comprises a switch circuit to connect the plurality of CPUs, the plurality of PCIe switches, and the plurality of NICs. The switch circuit comprises a plurality of inputs and a plurality of outputs to connect the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs. Connection routes within the switch circuit can be adjusted to set a specific PCIe topology of the computing system. The specific PCIe topology includes a full configuration mode, a balance mode, a common mode, and a cascade mode.

In some implementations, the switch circuit is connected to a Dual-Inline-Package (DIP) switch. The DIP switch is configured to set connection routes among the plurality of inputs and the plurality of outputs of the switch.

In some implementations, the switch circuit comprises a plurality of multiplexers (MUXs) to connect the plurality of inputs and the plurality of outputs. The DIP switch can set the connection status of each of the plurality of MUXs, and hence set connection routes among the plurality of inputs and the plurality of outputs.

In some implementations, at least one connection route among the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs includes multiple mini SAS connectors, and at least one physical PCIe cable. A specific PCIe topology of the computing system can be set by adjusting connection routes among the multiple mini SAS connectors and/or a golden finger repeater board installed on one of the plurality of NICs, via the at least one physical PCIe cable.

In accordance with one aspect of the present disclosure, a computer-implemented method for setting a peripheral component interconnect express (PCIe) topology in a computing system, comprises: receiving a request for a specific PCIe topology of the computing system; determining current connection routes among a plurality of CPUs, a plurality of PCIe switches, a plurality of NICs, and a plurality of FPGAs and/or GPUs in the computing system; determining whether the current connection routes are consistent with the specific PCIe topology; and in an event that the connection routes among the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs are inconsistent with the specific PCIe topology, adjusting at least one connection route among the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs.

In accordance with another aspect of the present disclosure, a non-transitory computer-readable storage medium storing instructions is provided. The instructions, when executed by a processor of a computing system, cause the processor to perform operations including: receiving a request for a specific PCIe topology of the computing system; determining current connection routes among a plurality of CPUs, a plurality of PCIe switches, a plurality of NICs, and a plurality of FPGAs and/or GPUs in the computing system; determining whether the current connection routes are consistent with the specific PCIe topology; and in an event that the connection routes among the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs are inconsistent with the specific PCIe topology, adjusting at least one connection route among the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs.

Additional features and advantages of the disclosure will be set forth in the description that follows, and will in part be obvious from the description; or can be learned by the practice of the principles set forth herein.

The disclosure, and its advantages and drawings, will be better understood from the following description of exemplary embodiments together with reference to the accompanying drawings.

The present disclosure can be embodied in many different forms. Representative embodiments are shown in the drawings, and will herein be described in detail.

Various examples of the present disclosure provide systems and methods for enabling a flexible PCIe topology in a computing system. The flexible PCIe topology can allow a user or a management controller of the computing system to adjust PCIe connections between CPUs and components of the computing system based upon a specific application. In some implementations, the computing system comprises a plurality of CPUs, a plurality of GPUs or Field-Programmable Gate Arrays (FPGAs), a plurality of PCIe switches, and a plurality of network interface controllers (NICs). In some implementations, the computing system comprises a switch circuit to connect the plurality of CPUs, the plurality of PCIe switches, and the plurality of NICs. The switch circuit comprises a plurality of inputs and a plurality of outputs to connect the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs. Connection routes within the switch circuit can be adjusted to set a specific PCIe topology of the computing system.

<FIG> is a schematic block diagram illustrating an exemplary system <NUM> having a plurality of processors <NUM>, a plurality of PCIe switch <NUM>, and a plurality of GPUs or FPGAs <NUM> with a flexible configuration, in accordance with an implementation of the present disclosure. In this example, the computing system <NUM> includes GPUs <NUM>, processors <NUM>, PCIe switches <NUM>, one or more cooling modules <NUM>, a main memory (MEM) <NUM>, and at least one power supply unit (PSU) <NUM> that receives an AC power from an AC power supply <NUM>. The PSU <NUM> provides power to various components of the computing system <NUM>, such as the processors <NUM>, north bridge (NB) logic <NUM>, PCIe slots <NUM>, south bridge (SB) logic <NUM>, storage device <NUM>, ISA slots <NUM>, PCI slots <NUM>, and a management controller <NUM>.

In this example, the GPUs or FPGAs <NUM> are connected to the processors <NUM> via the PCIe switches <NUM>. The PCIe switches <NUM> enables high-speed serial point-to-point connections among multiple I/O devices, GPUs or FPGAs <NUM>, and processors <NUM> for optimized aggregation, fan-out, or peer-to-peer communication of end-point traffic to a host. The computing system <NUM> further comprises NICs (not shown) that connect to the PCIe switches <NUM>. The NICs connect the computing system <NUM> to a computer network.

The processors <NUM> can be central processing units (CPUs) configured to execute program instructions for specific functions. For example, during a booting process, the processors <NUM> can access firmware data stored in the management device <NUM> or the flash storage device, and execute the BIOS <NUM> to initialize the computing system <NUM>. After the booting process, the processors <NUM> can execute an operating system (OS) in order to perform and manage specific tasks for the computing system <NUM>.

In some configurations, each of the processors <NUM> is coupled together through a CPU bus (not shown) connected to the NB logic <NUM>. In some configurations, the NB logic <NUM> can be integrated into the processors <NUM>. The NB logic <NUM> can also be connected to a plurality of peripheral component interconnect express (PCIe) slots <NUM> and an SB logic <NUM> (optional). The plurality of PCIe slots <NUM> can be used for connections and buses such as PCI Express x1, USB <NUM>, SMBus, SIM card, future extension for another PCIe lane, <NUM> V and <NUM> V power, and wires to diagnostics LEDs on the computing system <NUM>'s chassis.

In computing system <NUM>, the NB logic <NUM> and the SB logic <NUM> are connected by a peripheral component interconnect (PCI) Bus <NUM>. The SB logic <NUM> can couple the PCI Bus <NUM> to a plurality of expansion cards or ISA slots <NUM> (e.g., an ISA slot <NUM>) via an expansion bus. The SB logic <NUM> is further coupled to the management device <NUM> that is connected to the at least one PSU <NUM>. In some implementations, the management device <NUM> can be a specialized microcontroller embedded on the motherboard of the server system 100A. The management device <NUM> can be a baseboard management controller (BMC) or a rack management controller (RMC).

In some implementations, the processors <NUM> are connected to the PCIe switches <NUM> via a switch circuit (not shown). The switch circuit comprises a plurality of inputs and a plurality of outputs to connect the plurality of processors <NUM>, the plurality of PCIe switches <NUM>, and the plurality of NICs (not shown). Connection routes within the switch circuit can be adjusted to set a specific PCIe topology of the computing system <NUM>. The specific PCIe topology includes a full configuration mode, a balance mode, a common mode, and a cascade mode.

In some implementations, at least one connection route among the plurality of processors <NUM>, the plurality of PCIe switches <NUM>, and the plurality of NICs includes multiple mini SAS connectors (not shown), and at least one physical PCIe cable (not shown). A specific PCIe topology of the computing system <NUM> can be set by adjusting connection routes among the multiple mini SAS connectors and/or a golden finger repeater board installed on one of the plurality of NICs, via the at least one physical PCIe cable.

Implementations of the PCIe configuration in <FIG> is further illustrated in <FIG>. In <FIG>, multiple mini Serial Attached SCSI (SAS) connectors and at least one physical PCIe cable are used to set a flexible PCIe topology in a computing system. The specific PCIe topology includes a full configuration mode, a balance mode, a common mode, and a cascade mode.

<FIG> illustrates a general PCIe topology of a computing system 200A. The computing system 200A comprises CPUs <NUM>-<NUM> and <NUM>-<NUM>, FPGAs <NUM>-<NUM> thru <NUM>-<NUM>, NICs <NUM>-<NUM> thru <NUM>-<NUM>, PCIe switches <NUM>-<NUM> thru <NUM>-<NUM>, and SAS connectors <NUM>-<NUM> thru <NUM>-<NUM>. In this example, the CPU <NUM>-<NUM> is connected to the CPU <NUM>-<NUM> via a UltraPath Interconnect (UPI). The CPU <NUM>-<NUM> is connected to the PCIe switch <NUM>-<NUM> via a PCIe connection, and connected to the PCIe switch <NUM>-<NUM> via two SAS connectors <NUM>-<NUM>, <NUM>-<NUM> and a PCIe cable <NUM>-<NUM>. The CPU <NUM>-<NUM> is connected to the PCIe switch <NUM>-<NUM> via two SAS connectors <NUM>-<NUM>, <NUM>-<NUM> and a PCIe cable <NUM>-<NUM>, and connected to the PCIe switch <NUM>-<NUM> via two SAS connectors <NUM>-<NUM>, <NUM>-<NUM> and a PCIe cable <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>.

The PCIe topology in the computing system 200A can be adjusted to a full configuration mode, a balance mode, a common mode, and a cascade mode, which are illustrated in <FIG>, respectively.

In <FIG>, the PCIe topology of the computing system 200B is a full configuration mode. The computing system 200B comprises CPUs <NUM>-<NUM> and <NUM>-<NUM>, FPGAs or GPUs <NUM>-<NUM> thru <NUM>-<NUM>, NICs <NUM>-<NUM> thru <NUM>-<NUM>, PCIe switches <NUM>-<NUM> thru <NUM>-<NUM>, and SAS connectors <NUM>-<NUM> thru <NUM>-<NUM>. Connected routes between the above components of the computing system 200B are the same as those illustrated in <FIG>. In the full configuration mode, the computing system 200B supports all downstream of PCIe switches <NUM>-<NUM> thru <NUM>-<NUM> to the endpoint devices. In this example, the computing system 200B has <NUM> PCIe switches and have to support up to <NUM> PCIex16 end-point devices.

In <FIG>, the PCIe topology of the computing system 200C is a balance mode. The computing system 200C comprises CPUs <NUM>-<NUM> and <NUM>-<NUM>, FPGAs or GPUs (i.e., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>), NICs <NUM>-<NUM> and <NUM>-<NUM>, PCIe switches <NUM>-<NUM> and <NUM>-<NUM>, and SAS connectors <NUM>-<NUM> thru <NUM>-<NUM>. Comparing the full configuration mode in <FIG> and the balance mode in <FIG>, the PCIe switches <NUM>-<NUM> and <NUM>-<NUM> are not needed or not mounted in the computing system 200C. A PCIe cable <NUM>-<NUM> is used to connect SAS connectors <NUM>-<NUM> and <NUM>-<NUM>. The SAS connectors <NUM>-<NUM> and <NUM>-<NUM> are connected to the CPU <NUM>-<NUM> and the PCIe switch <NUM>-<NUM>, respectively. In the balance mode, each CPU of the computing system 200C connects to one PCIe switch and to all downstream of the corresponding PCIe switch. In this mode, each of CPUs <NUM>-<NUM> and <NUM>-<NUM> connects to a PCIe switch, and thus each CPU PCIe root port can connect up to <NUM> PCIe x <NUM> endpoint device via its corresponding PCIe switches <NUM>-<NUM> and <NUM>-<NUM>, respectively.

In <FIG>, the PCIe topology of the computing system 200D is a common mode. Similar to the computing system 200C in <FIG>, PCIe switches <NUM>-<NUM> and <NUM>-<NUM> are not needed or not mounted in the computing system 200D. However, in the computing system 200D, the PCIe cable <NUM>-<NUM> is used to connect SAS connectors <NUM>-<NUM> and <NUM>-<NUM>. The SAS connectors <NUM>-<NUM> and <NUM>-<NUM> are connected to the CPU <NUM>-<NUM> and the PCIe switch <NUM>-<NUM>, respectively. The remaining connection routes of the PCIe topology of the computing system 200D is the same as those of the PCIe topology of the computing system 200C. By adjusting the PCIe cable <NUM>-<NUM> connecting SAS connectors <NUM>-<NUM>, <NUM>-<NUM> and/or <NUM>-<NUM>, the PCIe topology can be switched between the common mode and the balance mode. In the common mode, a CPU of the computing system 200D connects to two PCIe switches and to all downstream of two PCIe switches. In this mode, CPU <NUM>-<NUM> connects to active PCIe switches <NUM>-<NUM> and <NUM>-<NUM>, and end point devices <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. Data from these end point devices are transferred directly to CPU <NUM>-<NUM>, instead of requiring some data being transferred from CPU204-<NUM> via UPI.

In <FIG>, the PCIe topology of the computing system 200E is a cascade mode. Similar to the computing systems 200C and 200D in <FIG> and <FIG>, respectively, PCIe switches <NUM>-<NUM> and <NUM>-<NUM> are not needed or not mounted in the computing system 200E. However, in the computing system 200E, the PCIe cable <NUM>-<NUM> is used to connect SAS connector <NUM>-<NUM> and a golden finger repeater board <NUM>-<NUM> installed on NIC <NUM>-<NUM>. The SAS connector <NUM>-<NUM> is connected to the PCIe switch <NUM>-<NUM>. The golden finger repeater board <NUM>-<NUM> is configured to pass PCIe signal from the NIC <NUM>-<NUM> to a SAS communication channel (e.g., the PCIe cable <NUM>-<NUM>) and the PCIe switch <NUM>-<NUM>. In the cascade mode, a CPU of the computing system 200D connects to two PCIe switches and to all downstream of two PCIe switches. In this mode, CPU <NUM>-<NUM> connects to active PCIe switches <NUM>-<NUM> and <NUM>-<NUM>, and end point devices <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. Data from these end point devices are transferred directly to CPU <NUM>-<NUM>, instead of requiring some data being transferred from CPU204-<NUM> via UPI. In the cascade mode, a CPU of the computing system 200E connects to a first PCIe switch, while a second PCIe switch cascades under the first PCIe switch. Thus, the CPU can connect to all active endpoint devices, and transfer data between the first and second PCIe switches without being limited by throughput of CPUs of the computing system 200E. In this mode, CPU <NUM>-<NUM> connects to the first PCIe switch <NUM>-<NUM>, while the second PCIe switch <NUM>-<NUM> connects to the first PCIe switch <NUM>-<NUM> via NIC <NUM>-<NUM>.

As illustrated above in <FIG>, multiple mini Serial Attached SCSI (SAS) connectors and at least one physical PCIe cable can be used to set a flexible PCIe topology in computing systems 200A thru 200E. However, the present disclosure contemplates that a switching circuit can be used to switch the PCIe topology between the different modes. This is illustrated in <FIG>.

<FIG> are schematic block diagrams illustrating exemplary systems 300A-300F comprising a switch circuit <NUM> to set a specific PCIe topology of the exemplary systems, in accordance with an implementation of the present disclosure. The switch circuit <NUM> is configured to set the specific PCIe topology based upon a request of a management controller or a user of the exemplary systems.

In <FIG>, the computing system 300A comprises CPUs <NUM>-<NUM> and <NUM>-<NUM>, FPGAs <NUM>-<NUM> thru <NUM>-<NUM>, NICs <NUM>-<NUM> thru <NUM>-<NUM>, PCIe switches <NUM>-<NUM> thru <NUM>-<NUM>, and a switching circuit <NUM> that connects the CPUs (i.e., <NUM>-<NUM> and <NUM>-<NUM>), the PCIe switches (i.e., <NUM>-<NUM> thru <NUM>-<NUM>), and the NICs (i.e., <NUM>-<NUM> and <NUM>-<NUM>). In this example, the CPU <NUM>-<NUM> is connected to the CPU <NUM>-<NUM> via a UltraPath Interconnect (UPI). The CPU <NUM>-<NUM> is also connected to the PCIe switch <NUM>-<NUM> while the CPU <NUM>-<NUM> is also connected to the PCIe switch <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>. The PCIe switch <NUM>-<NUM> is connected to the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, and the NIC <NUM>-<NUM>.

In this example, the switch circuit <NUM> has four inputs (i.e., from the CPUs <NUM>-<NUM> and <NUM>-<NUM>, and from the PCIe switches <NUM>-<NUM> and <NUM>-<NUM>), and four outputs (i.e., to the PCIe switches <NUM>-<NUM> and <NUM>-<NUM>, and to the NICs <NUM>-<NUM> and <NUM>-<NUM>). In this example, a DIP switch <NUM> is used to set connection routes within the switch circuit.

In some implementations, the switch circuit <NUM> comprises a plurality of MUXs (i.e., <NUM>-<NUM> thru <NUM>-<NUM>) to connect the CPUs (i.e., <NUM>-<NUM> and <NUM>-<NUM>), the PCIe switches (i.e., <NUM>-<NUM> thru <NUM>-<NUM>), and the NICs (i.e., <NUM>-<NUM> and <NUM>-<NUM>), which is illustrated in <FIG>. The DIP switch <NUM> can set connection status of each of the plurality of MUXs (i.e., <NUM>-<NUM> thru <NUM>-<NUM>), and hence set connection routes among four inputs and four output of the switch circuit <NUM>.

In <FIG>, the PCIe topology of the computing system 300C is a full configuration mode. The computing system 300C comprises CPUs <NUM>-<NUM> and <NUM>-<NUM>, FPGAs or GPUs <NUM>-<NUM> thru <NUM>-<NUM>, NICs <NUM>-<NUM> thru <NUM>-<NUM>, PCIe switches <NUM>-<NUM> thru <NUM>-<NUM>, and SAS connectors <NUM>-<NUM> thru <NUM>-<NUM>. In this example, the DIP switch <NUM> sets input of the switch circuit <NUM> from the CPU <NUM>-<NUM> to the MUX <NUM>-<NUM>, then to the MUX <NUM>-<NUM>, and to the PCIe switch <NUM>-<NUM>. Also, the DIP switch <NUM> sets input of the switch circuit <NUM> from the CPU <NUM>-<NUM> to the MUX <NUM>-<NUM>, then to the MUX <NUM>-<NUM>, and to the PCIe switch <NUM>-<NUM>. The DIP switch <NUM> further sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIC <NUM>-<NUM>. Also, the DIP switch <NUM> sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIX <NUM>-<NUM>. All other connection routes within the switching circuit <NUM> are disenabled by the DIP switch <NUM> in the computing system 300C.

In <FIG>, the PCIe topology of the computing system 300D is a balance mode. In this example, the DIP switch <NUM> sets input of the switch circuit <NUM> from the CPU <NUM>-<NUM> to the MUX <NUM>-<NUM>, then to the MUX <NUM>-<NUM>, and to the PCIe switch <NUM>-<NUM>. The DIP switch <NUM> further sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIC <NUM>-<NUM>. Also, the DIP switch <NUM> sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIX <NUM>-<NUM>. All other connection routes within the switching circuit <NUM> are disenabled by the DIP switch <NUM> in the computing system 300D.

In <FIG>, the PCIe topology of the computing system 300E is a common mode. In this example, the DIP switch <NUM> sets input of the switch circuit <NUM> from the CPU <NUM>-<NUM> to the MUX <NUM>-<NUM>, then to the MUX <NUM>-<NUM>, and to the PCIe switch <NUM>-<NUM>. The DIP switch <NUM> further sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIC <NUM>-<NUM>. Also, the DIP switch <NUM> sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, and then to the NIX <NUM>-<NUM>. All other connection routes within the switching circuit <NUM> are disenabled by the DIP switch <NUM> in the computing system 300E.

In <FIG>, the PCIe topology of the computing system 300F is a cascade mode. In this example, the DIP switch <NUM> sets input of the switch circuit <NUM> from the PCIe switch <NUM>-<NUM> to the MUX <NUM>-<NUM>, then to the MUX <NUM>-<NUM>, and then to the PCIe switch <NUM>-<NUM>. All other connection routes within the switching circuit <NUM> are disenabled by the DIP switch <NUM> in the computing system 300F.

As illustrated above in <FIG>, the switch circuit <NUM> can be used to set a flexible PCIe topology in computing systems 300A thru 300F. The PCIe topology set by the switch circuit <NUM> includes a full configuration mode, a balance mode, a common mode, and a cascade mode.

<FIG> is an exemplary method <NUM> for setting a PCIe topology in a computing system, in accordance with an implementation of the present disclosure. It should be understood that the exemplary method <NUM> is presented solely for illustrative purposes, and that other methods in accordance with the present disclosure can include additional, fewer, or alternative steps performed in similar or alternative orders, or in parallel. The exemplary method <NUM> starts at step <NUM> by receiving a request for a specific PCIe topology for the computing system. In some implementations, the request can be from a management controller (e.g., BMC) or a user of the computing system. The specific PCIe topology includes a full configuration mode, a balance mode, a common mode, and a cascade mode.

At step <NUM>, the management controller can determine current connection routes among a plurality of CPUs, a plurality of PCIe switches, a plurality of NICs, and a plurality of FPGAs and/or GPUs in the computing system. In some implementations, the computing system comprises a switch circuit that comprises a plurality of inputs and a plurality of outputs. The inputs and outputs of the switch circuit connect the plurality of CPUs, the plurality of PCIe switches, the plurality of NICs, and the plurality of FPGAs and/or GPUs. In some implementations, the switch circuit comprises a plurality of MUXs. A DIP switch connected to the switch can set connection status of each of the plurality of MUXs), and hence set connection routes among the plurality of inputs and the plurality of outputs of the switch circuit.

At step <NUM>, the management controller can determine current connection routes can determine whether the current connection routes among the CPUs, the PCIe switches, the NICs, and the FPGAs and/or GPUs are consistent with the specific PCIe topology. In an event that the current connection routes among the CPUs, the PCIe switches, the NICs, and the FPGAs and/or GPUs are consistent with the specific PCIe topology, the process <NUM> ends at step <NUM>. In an event that the current connection routes among the CPUs, the PCIe switches, the NICs, and the FPGAs and/or GPUs are inconsistent with the specific PCIe topology, the management controller can cause the connection routes among the plurality of inputs and the plurality of outputs of the switch circuit to be adjusted such that the connection routes are consistent with the specific PCIe topology, at step <NUM>. In some implementations, the management controller can adjust the settings of the DIP switch to set connection status of each of the plurality of MUXs in the switch circuit.

Claim 1:
A computing system (<NUM>), comprising:
a plurality of Central Processing Units, CPUs (<NUM>);
a plurality of Peripheral Component Interconnect Express, PCIe, switches (<NUM>);
a plurality of network interface controllers, NICs (<NUM>); and
a connection mechanism that enables at least one connection route among the plurality of CPUs (<NUM>), the plurality of PCIe switches (<NUM>), and the plurality of NICs (<NUM>) to be adjusted to set a specific PCIe topology of the computing system (<NUM>); wherein
the specific PCIe topology includes a full configuration mode, a balance mode, a common mode, and a cascade mode;
the connection mechanism comprises multiple mini Serial Attached SCSI, SAS, connectors (<NUM>) and at least one physical PCIe cable (<NUM>);
the connection mechanism further comprises a golden finger repeater board (<NUM>) installed on one of the plurality of NICs (<NUM>);
in the full configuration mode, a first CPU (CPU0) is connected to a first switch (PLX0) and to a second switch (PLX1), and a second CPU (CPU1) is connected to a third switch (PLX2) and to a fourth switch (PLX3) supporting all downstream ports;
in the balance mode, the first CPU (CPU0) is connected to the first switch (PLX0) while the connection to the second switch (PLX1) is interrupted, and the second CPU (CPU1) is connected to the third switch (PLX2) while the connection to the fourth switch (PLX3) is interrupted;
in the common mode, the first CPU (CPU0) is connected to the first switch (PLX0) and to the third switch (PLX2) while the interconnections of the second CPU (CPU1) to the switches are interrupted; and
in the cascade mode, the first CPU (CPU0) is connected to the first switch (PLX0), wherein the first switch (PLX0) is connected via the golden finger repeater board (<NUM>) to the upstream port of the third switch (PLX2), while the interconnections of the second CPU (CPU1) to the switches are interrupted.