Patent Description:
Modern circuit fabrication includes processes of forming electrical interconnection structures for interconnecting semiconductor devices in a functioning circuit, e.g. in the back-end-of-line (BEOL). An interconnection structure may include one or more interconnection levels or tiers, which are formed above the substrate supporting the active device regions. An interconnection level includes horizontal conductive paths or lines arranged in an insulating material layer. Conductive lines of different interconnection levels may be interconnected by conductive vias extending vertically through the insulating layers.

A conventional approach for forming an interconnection level is the "dual damascene process". According to this approach, horizontally extending trenches are etched in the insulating layer. Further, vertically extending via holes are formed in the insulating layer. Thereafter the trenches and via holes are simultaneously filled with a conductive material to form conductive lines in the trenches and conductive vias in the via holes. The process may be repeated to form a stack of interconnection levels.

Another approach for forming an interconnection level is to directly etch metal lines in a metal layer using e.g. single- or multi-patterning techniques such as lithography and etching, self-aligned double patterning (SADP) or quadruple patterning (SAQP). Vias may be formed using subtractive etching of the patterned metal lines, wherein vias may be defined by non-recessed portions of the metal lines. Compared to the dual damascene process, a direct metal etch approach may facilitate interconnection level fabrication at more aggressive line pitches by avoiding challenges related to reliably filling narrow trenches with metal, among others.

<CIT> and <CIT> disclose prior art patterning methods for interconnects.

In some cases it would be desirable to combine metal lines of different heights in a same interconnection level. However, current direct metal etch approaches are lacking in terms of ability to efficiently and reliably form an interconnection level with hybrid-height metal lines.

In light of the above, it is an objective to provide a method for forming an interconnection structure allowing forming of an interconnection level comprising metal lines of differing heights. Further and alternative objectives may be understood from the following.

According to an aspect there is provided a method for forming an interconnection structure, comprising:.

The method according to the present aspect enables forming of an interconnection structure comprising hybrid-height metal features, i.e. metal features of different heights. In some embodiments, the metal features may be metal lines, wherein hybrid-height metal lines, i.e. metal lines of different heights may be formed. The method is however not so limited but may also be used to form metal features in the form of pillars or metal features with arbitrary 2D layouts, exclusively or in combination with metal lines.

More specifically, the method allows forming of two consecutive interconnection levels, a lower and an upper interconnection level, wherein the set of lower metal features are arranged in the lower interconnection level, the set of upper metal features are arranged in the upper interconnection level, and the stacked metal features are arranged to span the lower and upper interconnection levels. It is hereby to understood that the first portion of the second metal layer pattern overlies and is formed in electrical contact with the second portion of the first metal layer pattern.

The hybrid-height metal feature interconnection structure is enabled by the stacking of the first and second metal layer patterns which subsequently are etched using the mask pattern of the mask material. This contrasts a conventional direct metal patterning approach wherein metal features (e.g. metal lines) are patterned in a single blanket-deposited metal layer.

An additional advantage of the present method is that metal features of the first height, metal features of the second height and metal features of the third height may be interleaved with each other. For instance, a subset of the stacked metal features (e.g. lines) may be formed between a subset of the lower metal features (e.g. lines) and a subset of the upper metal features (e.g. lines). As further may be appreciated, the metal features may be formed in a staggered fashion in the sense that the lower metal features and the upper metal features may be arranged at different vertical levels over the substrate.

The term "covering the first/second dielectric layer pattern with metal" as used herein means that a first/second metal layer is formed to cover and surround the first/second dielectric layer pattern. The first/second metal layer is subsequently planarized to form the first/second metal layer pattern. The metal may be deposited on top of (e.g. in direct contact with) the first/second dielectric layer pattern (and in the case of the second metal layer pattern in direct contact with the first metal layer pattern). The (first/second) metal layer may each be formed of a single metal layer or a stack of metal (sub-)layers of different metals, for instance a stack of a metal liner (sub-)layer and a metal fill (sub-)layer.

Relative spatial terms such as "upper", "lower", "top", "bottom", "stacked on top of", are herein to be understood as denoting locations or orientations within a frame of reference relative the substrate. In particular, the terms may be understood as locations relative a normal direction to a main surface or main plane of extension of the substrate (equivalently a vertical direction). Conversely, terms such as "lateral" and "horizontal" are to be understood as locations or orientations parallel to the substrate, i.e. parallel to the main surface / main plane of extension of the substrate.

The term "height" as used herein accordingly denotes a dimension as seen along the vertical direction. Also the term "thickness" is to be understood in this sense unless stated otherwise.

The term "planarizing" (e.g. as in "planarizing the metal") as used herein denotes subjecting an initial surface (e.g. an upper surface of deposited metal or layer) to a planarization process to produce a planar surface (wherein the surface initially may have a varying topography). For example, the act of "planarizing" may comprise chemical mechanical polishing (CMP).

The term "using a feature as an etch mask" (where the "feature" refers to a feature such as a layer or a line) as used herein means that one or more underlying layers are etched while the feature counteracts etching of portions of the underlaying layer(s) masked by the feature (i.e. portions overlapped or covered by the feature).

In some embodiments, the first sub-pattern may further be transferred into said portion of the second dielectric layer pattern to form a set of dielectric features, wherein the lower set of metal features are capped by the set of dielectric features. This may facilitate connecting the lower metal features with vias by enabling forming of via holes self-aligned to the lower metal features (by selective etching of the dielectric features). Various embodiments for via formation are further set out in the following.

In some embodiments, forming one of the first and the second dielectric layer pattern may comprise forming a dielectric layer and patterning a set of openings in the dielectric layer, and wherein forming the other one of the first and second dielectric layer pattern may comprise forming a dielectric layer and patterning a set of dielectric blocks in the dielectric layer. Hence, a set of openings may be patterned in the first dielectric layer (e.g. using a lithography and etching process) and a set of dielectrics blocks may be patterned in the second dielectric layer (e.g. using a lithography and etching process), or vice versa.

The term "openings" is hereby used to refer to cavities etched through the first or second dielectric layer. The first/second metal layer pattern may accordingly fill the set of openings in the first/second dielectric layer. The first/second metal layer pattern may accordingly be defined by a set of first/second metal layer pattern parts, each pattern part formed in a respective opening in the first/second dielectric layer pattern.

The dielectric blocking pattern defines regions in which no stacked metal features are to be formed. The first/second metal layer pattern may surround the dielectric blocks of the first/second dielectric layer pattern.

The mask material of the mask pattern may be a hard mask material, e.g. a dielectric hard mask material.

Forming the mask pattern may comprise forming a mask layer of the mask material over the second dielectric layer pattern and the second metal layer pattern and patterning the mask layer to form the mask pattern.

In some embodiments, the method may further comprise depositing an interlayer dielectric to embed and cover the sets of metal lines and the mask line pattern of the mask material, and planarizing the interlayer dielectric to expose an upper surface of mask line pattern.

The upper surface of the mask line pattern may be used for end point detection for the planarizing (i.e. planarization process e.g. CMP) of the interlayer dielectric. In other words, the planarizing of the interlayer dielectric may be stopped in response to detecting the upper surface of the mask line pattern.

The mask pattern may comprise a pattern of mask lines of the mask material. This enables forming of metal features in the form of metal lines (e.g. lower, upper and stacked metal lines).

The mask line pattern may comprise a grating of lines of the mask material. This enables a relatively large area of mask material (e.g. hard mask material) for end point detection for the planarization process applied to the interlayer dielectric.

In some embodiments, the method may further comprise method steps for forming metal vias on top of the lower, upper and/or stacked metal features (e.g. metal lines).

The method may comprise patterning a first via hole exposing an upper surface of a first lower metal feature, the first via hole extending through a first mask feature of the mask pattern overlying the first lower metal feature (and a first dielectric feature overlying / capping the first lower metal feature); and forming a first metal via in the first via hole.

The method may additionally or alternatively comprise patterning a second via hole exposing an upper surface of a first stacked metal feature and extending through a second mask feature of the mask pattern overlying the first stacked metal feature; and forming a second metal via in the second via hole.

The method may additionally or alternatively comprise patterning a third via hole exposing an upper surface of a first upper metal feature and extending through a third mask feature of the mask pattern overlying the first upper metal feature; and forming a third metal via in the third via hole.

In each of these cases, via formation (e.g. first, second or third) may be achieved without any metal etch back but by forming respective via holes (in which metal vias are subsequently formed). The mask feature of the mask pattern (as they overlie / overlap the underlying metal lines) facilitates aligning the via holes with the respective metal features.

Since the upper surfaces of the upper and stacked metal feature may be located at a same level above the substrate, the second and third via holes and metal vias may be of relatively low aspect ratio (LAR). Only the first via hole and metal via needs to be of a relatively high aspect ratio (HAR) as it needs to extend through the upper level to reach the upper surface of the lower metal feature.

Advantageously, each one of the first, second and third via holes may be patterned simultaneously, e.g. using a same via mask layer as etch mask.

Forming the first, second and/or third via hole may comprise etching the mask material selectively to the interlayer dielectric. This enables the via holes to be formed to in a self-aligned manner to the metal lines.

Forming the first via hole may further comprise etching a dielectric material of the first dielectric feature capping the first lower metal feature selectively to the interlayer dielectric. Hence also a lower portion of the first via hole may be formed in a self-aligned manner.

In some embodiments, the method may further comprise forming a metal liner (which may be denoted "upper metal liner") after forming the second dielectric layer pattern and the second metal layer pattern and subsequently forming the mask pattern on the metal liner. The (upper) metal liner may serve as a metal adhesion layer, facilitating adhesion of the mask material of the mask pattern, in particular of the portion(s) of the mask pattern overlying the second metal layer pattern. This may further increase the flexibility of the method with respect to material choices for the mask material and the second metal layer pattern.

The (upper) metal liner / adhesion layer may be deposited selectively on an upper surface of the second metal layer pattern. The metal liner may hence be formed selectively on the surfaces where improved adhesion may provide the most benefit. Additionally, by a selective deposition, sandwiching of metal liner portions between the second dielectric layer pattern and the mask pattern, which could create line to line shorts if not removed, may thus be avoided.

In embodiments comprising forming the (upper) metal liner, each upper metal feature and each stacked metal feature may comprise a respective thickness portion of the metal liner. Accordingly, each upper metal feature may comprises a thickness portion of the second metal layer pattern and a thickness portion of the metal liner, and each stacked metal feature may comprise a thickness portion of the first metal layer pattern, a thickness portion of the metal liner, and a thickness portion of the second metal layer pattern.

In some embodiments, the method may further comprise forming a metal liner (which may be denoted "lower metal liner") after forming the first dielectric layer pattern and the first metal layer pattern and subsequently forming the second dielectric layer pattern on the metal liner. The (lower) metal liner may serve as a metal adhesion layer, facilitating adhesion of the second dielectric layer pattern, in particular of the portion(s) of the second dielectric layer pattern overlying the first metal layer pattern. This may further increase the flexibility of the method in respect of material choices for the second dielectric layer and the first metal layer pattern.

The above, as well as additional objects, features and advantages, may be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings.

Methods for forming an interconnection structure, suitable for instance for a semiconductor device, will now be described with reference to the figures. The methods will be described in connection with forming interconnection levels exemplified in the figures as a bottom interconnection level. It is however noted that the methods herein have a more general applicability and may be used for forming any interconnection level of a stack of interconnection levels of an interconnection structure. The methods herein allows forming of an interconnection structure comprising two consecutive levels, a lower and an upper level, wherein the interconnection structure comprises a set of lower metal lines in the lower level, a set of upper metal lines in the upper level and a set of stacked metal lines spanning the lower and upper levels. Using a conventional notation for interconnection levels, the lower level may be denoted MX and the upper level may be denoted MX+<NUM>. While the illustrated examples refer to metal features in the shape of metal lines, it is to be noted that the method has a more general applicability and may be used to form hybrid-height metal features with arbitrary 2D layout, or hybrid-height metal pillars.

<FIG> schematically illustrate method steps for forming an interconnection structure. Each one of <FIG> shows in cross-section a device structure <NUM> at different stages of the method, except for <FIG>, <FIG>, <FIG> and <FIG> which depict a top-down view of the device structure <NUM>. In the figures, the X- and Y-axes indicate first and second horizontal directions, respectively, parallel to a main plane of a substrate <NUM> of the device structure <NUM>, and the Z-axis indicate a normal or vertical direction with respect to the substrate <NUM>.

<FIG> shows an initial or starting device structure <NUM> for the method. The device structure <NUM> comprises as shown a substrate <NUM>, for instance a semiconductor substrate such as a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a SiGe substrate, or any other conventional type of substrate suitable for CMOS fabrication. Active device regions (not shown) including semiconductor devices such as transistors may be fabricated on a main surface of the substrate <NUM> during front-end-of-line (FEOL) processing. The substrate <NUM>, including the active device regions, may be covered by an insulating layer structure comprising e.g. an interlayer dielectric layer <NUM> (e.g. of SiO<NUM> or another low-k oxide-based or other insulating material) and optionally a dielectric capping layer <NUM> (e.g. of SiN, AIN or another dielectric hard mask material such as AlOx or SiOC). The capping layer <NUM> may be used as an etch stop layer (ESL) during subsequent etching steps and may accordingly be referred to as ESL <NUM>. The interlayer dielectric layer <NUM> may embed a set of conductive structures. In case the interconnection level to be formed is a bottom interconnection level (e.g. M1) the conductive structures may be contact structures for the active device regions (e.g. in M0A). However, in case the interconnection level is a second or higher level interconnection level the conductive structures may be metal lines and/or metal vias of a lower interconnection level.

A first dielectric layer <NUM> is formed over the substrate <NUM>, more specifically on top of the insulating layer structure (e.g. layers <NUM> and <NUM>). The first dielectric layer <NUM> may like the interlayer dielectric <NUM> be formed of SiO<NUM> or of another low-k insulating material (e.g. an oxide) suitable as interlayer dielectric in an interconnection structure. The interlayer dielectric layer <NUM> may be formed using conventional deposition techniques such as chemical vapor deposition (CVD), flowable-CVD or physical vapor deposition (PVD).

In <FIG> a mask layer <NUM> has been formed on top of the first dielectric layer <NUM>. While schematically shown as a single layer structure, the mask layer <NUM> may in practice be a lithographic layer stack. As one example, a lithographic layer stack may comprise a spin-on-carbon/spin-on-glass (SOC/SOG) stack and a resist layer. A pattern of a set of openings <NUM> (of which <FIG> depicts a single opening but further openings may be formed outside the shown partial view of the device structure <NUM>) has been patterned in the mask layer <NUM>, e.g. using a lithography and etching process.

In <FIG> the set of openings <NUM> have been transferred into the first dielectric layer <NUM> by etching the first dielectric layer <NUM> while using the mask layer <NUM> as an etch mask. A first dielectric layer pattern <NUM> defining a pattern of a set of openings or cavities <NUM> conforming or corresponding to the set of openings <NUM> in the mask layer <NUM> has thus been formed. Each opening <NUM> may as shown be formed to extend completely through the first dielectric layer <NUM>. The pattern transfer may comprise anisotropic or isotropic etching, wet or dry. The mask layer <NUM> may subsequently be removed.

In <FIG> metal has been deposited to form a first metal layer <NUM> covering the first dielectric layer pattern <NUM> and filling the set of openings <NUM>. Portions of the metal deposited outside the set of openings <NUM> defines a metal overburden. The first metal layer <NUM> may as shown comprise a stack of a (first) metal liner layer <NUM> (e.g. of TiN or TiO<NUM>) and a metal fill or bulk layer <NUM> (e.g. of Ru, Mo, W, Al or Co, or combinations of sub-layers of one or more of the aforementioned metals). The metal liner layer <NUM> may be a conformal layer. By a conformal layer is hereby meant a layer with a uniform thickness and following a contour of the surface on which it is deposited. The metal fill layer <NUM> may be deposited to completely fill a (remaining) space of each opening <NUM>. The metal fill layer <NUM> may be a non-conformal layer, i.e. with a non-uniform thickness. The metal liner layer <NUM> and the metal fill layer <NUM> may each be deposited using conventional deposition techniques, such as atomic layer deposition (ALD), CVD, PVD or plating. While the metal liner layer <NUM> may facilitate adhesion of the metal fill layer <NUM>, the metal liner layer <NUM> may however be omitted in case the metal fill layer <NUM> already presents sufficient adhesion to the device structure <NUM>, e.g. the first dielectric layer pattern <NUM> and the insulating layer structure (e.g. layer <NUM> or <NUM>). In this case, the metal fill layer <NUM> may on its own form the first metal layer <NUM> and completely fill the set of openings <NUM>.

While not shown in the figures, it is to be understood that prior to forming the first dielectric layer <NUM>, a pattern of metal vias may be formed in the insulating layer structure, on top of conductive structures (e.g. contact structures or metal lines) embedded therein, to enable an electrical connection to the metal lines that are to be formed in the lower level (e.g. MX). The metal vias may e.g. be formed by patterning via holes in the insulating layer structure (e.g. through layers <NUM> and <NUM>) and filling the same with metal. A top surface of the metal vias may then be exposed in set of openings <NUM> patterned in the first dielectric layer <NUM> such that the first metal layer <NUM> may be formed in electrical contact with the metal vias. It is also possible to pattern via holes in the insulating layer structure after patterning the first dielectric layer <NUM>, e.g. by etching via holes through layers <NUM> and <NUM> from the set openings <NUM> patterned in the first dielectric layer <NUM>. The via holes may then be filled by the first metal layer <NUM>.

In <FIG> the deposited metal / the first metal layer <NUM> (e.g. comprising layers <NUM> and <NUM>) has been subjected to a planarization process (e.g. CMP) to reduce a thickness thereof and expose an upper surface of the first dielectric layer pattern <NUM>. The metal overburden is thus removed from the upper surface of the first dielectric layer pattern <NUM> such that a first metal layer pattern <NUM> is formed of the deposited metal / first metal layer <NUM> remaining in each opening <NUM>. The planarization process may be stopped on the upper surface of the first dielectric layer pattern <NUM>. An upper surface of the first metal layer pattern <NUM> may be flush with the upper surface of the first dielectric layer pattern <NUM> such that the first dielectric layer pattern <NUM> and the first metal layer pattern <NUM> together define a planarized upper surface of the device structure <NUM>.

In <FIG> a second dielectric layer <NUM> has been formed over the first dielectric layer pattern <NUM> and the first metal layer pattern <NUM>. The second dielectric layer <NUM> may be formed of a dielectric material different from a material of the first dielectric layer <NUM> (and first dielectric layer pattern <NUM>). The second dielectric layer <NUM> may for example be formed of a dielectric hard mask material, such as any of the materials mentioned in connection with capping layer / ESL <NUM>. The second dielectric layer <NUM> and the ESL <NUM> may be formed of a same or a different material. As shown in <FIG>, a (second) metal liner layer <NUM> may optionally be formed on top of the first dielectric layer pattern <NUM> and the first metal layer pattern <NUM> wherein the second dielectric layer <NUM> may be formed on top of the metal liner layer <NUM>. The metal liner layer <NUM> may be a conformal layer. The metal liner layer <NUM> may for example be formed of a same material as the metal liner <NUM>. Analogous to the discussion of the metal liner <NUM>, the metal liner layer <NUM> may facilitate adhesion of a second metal layer <NUM> to be subsequently formed. The metal liner layer <NUM> may however be omitted in case the second metal layer <NUM> already presents sufficient adhesion to the device structure <NUM>.

A mask layer <NUM> has further been formed on top of the second dielectric layer <NUM> and patterned to define a set of mask blocks (of which <FIG> depicts a single block but further blocks may be formed outside the shown partial view of the device structure <NUM>). While schematically shown as a single layer structure, the mask layer <NUM> may like the mask layer <NUM> be a lithographic layer stack (e.g. a SOC/SOG/resist layer stack), and be patterned using a lithography and etching process.

In <FIG> the pattern of mask blocks defined by the mask layer <NUM> has been transferred into the second dielectric layer <NUM> by etching while using the set of mask blocks <NUM> as an etch mask. A second dielectric layer pattern <NUM> defined by a set of dielectric blocks conforming or corresponding to the pattern of mask blocks of the mask layer <NUM> has thus been formed. The dielectric blocks of the second dielectric layer pattern <NUM> may be formed using anisotropic or isotropic etching, wet or dry. The etching may be stopped on an upper surface of the metal liner layer <NUM>, if present, or otherwise on the planarized upper surface of the first dielectric layer pattern <NUM> and the first metal layer pattern <NUM>. The mask layer <NUM> may subsequently be removed.

In <FIG> metal has been deposited to form a second metal layer <NUM> covering the second dielectric layer pattern <NUM>. The set of dielectric blocks may as shown be fully encased or embedded in the deposited metal / second metal layer <NUM>. The second metal layer <NUM> may as shown comprise a stack of a (third) metal liner layer <NUM> and a metal fill or bulk layer <NUM>. The metal liner layer <NUM> may be a conformal layer. The metal fill layer <NUM> may be a non-conformal layer, i.e. with a non-uniform thickness. The metal liner layer <NUM> and the metal fill layer <NUM> may respectively be formed using any of the deposition techniques, and of any of the materials, mentioned in connection with the metal liner layer <NUM> and metal fill layer <NUM>, for instance of the same respective materials as indicated by the fill patterns in <FIG>. Analogous to the discussion of the metal liner <NUM>, the metal liner layer <NUM> may facilitate adhesion of the metal fill layer <NUM>. The metal liner layer <NUM> may however be omitted in case the metal fill layer <NUM> already presents sufficient adhesion to the device structure <NUM>, e.g. the second dielectric layer pattern <NUM> and the metal liner layer <NUM>, or the first dielectric layer pattern <NUM> if the metal liner layer <NUM> is omitted.

In <FIG> the deposited metal / the second metal layer <NUM> (e.g. comprising layers <NUM> and <NUM>) has been subjected to a planarization process (e.g. CMP) to reduce a thickness thereof and expose an upper surface of the second dielectric layer pattern <NUM>. Metal overburden is thus removed from the upper surface of the second dielectric layer pattern <NUM> such that a second metal layer pattern <NUM> is formed of the deposited metal / second metal layer <NUM> remaining to surround the set of blocks of the second dielectric layer pattern <NUM>. The planarization process may be stopped on (e.g. in response to detecting) the upper surface of the second dielectric layer pattern <NUM>. An upper surface of the second metal layer pattern <NUM> may be flush with the upper surface of the second dielectric layer pattern <NUM> such that the second dielectric layer pattern <NUM> and the second metal layer pattern <NUM> together define a planarized upper surface of the device structure <NUM>.

Accordingly, at the stage of the method depicted in <FIG> an intermediate layer stack for an interconnection structure has been formed over the device structure <NUM>, the intermediate layer stack comprises a first level (e.g. MX) and a second level on top of the first level (e.g. MX+<NUM>). The first level (MX) comprises the first metal layer pattern <NUM> and the first dielectric layer pattern <NUM>. The second level (MX+<NUM>) comprises the second metal layer pattern <NUM> and the second dielectric layer pattern <NUM>. The first metal layer pattern <NUM> is arranged within the first dielectric layer pattern <NUM> (e.g. in each opening <NUM> in the first dielectric layer pattern <NUM>). The second dielectric layer pattern <NUM> is arranged within the second metal layer pattern <NUM> (e.g. the second metal layer pattern <NUM> surrounds the set of blocks of the second dielectric layer pattern <NUM>).

As may be seen in <FIG>, the second dielectric layer pattern <NUM> comprises a first portion 130a overlying a first portion 122a of the first metal layer pattern <NUM>. The second metal layer pattern <NUM> comprises a first portion 136a overlying a second portion 122b (indicated by absence of a bounding box) of the first metal layer pattern <NUM>. The second metal layer pattern <NUM> further comprises a second portion 136b (indicated by absence of a bounding box) overlying a first portion 114a of the first dielectric layer pattern <NUM>. The overlap between the first portion 130a of the second dielectric layer pattern <NUM> and the first portion 122a of the first metal layer pattern <NUM> is the result of the illustrated block of the mask layer <NUM> (see <FIG>) overlying or overlapping the first portion 122a of the first metal layer pattern <NUM> and a portion 126a of the second dielectric layer <NUM> (wherein portion 126a after patterning of the second dielectric layer <NUM> forms the first portion 130a of the second dielectric layer pattern <NUM>).

The illustrated example shows a single discrete metal pattern part of the first metal layer pattern <NUM> within a single opening <NUM> in the first dielectric layer pattern <NUM>. However, it is to be understood that the first metal layer pattern <NUM> may comprise a set of plural discrete metal pattern parts, each metal pattern part formed in a respective one of a set of plural openings <NUM> in the first dielectric layer pattern <NUM>. Each metal pattern part of the first metal layer pattern <NUM> may be formed with a first horizontal dimension (e.g. along the X direction) such that at least one lower metal line may be patterned therein, and/or such that at least a lower portion of a stacked metal line may be patterned therein. For example, the first horizontal dimension of a metal pattern part of the first metal layer pattern <NUM> may be at least N * p, where N ≥ <NUM> and p is the (minimum) pitch of the pattern of metal lines that is to be formed in the first metal layer pattern <NUM>. A second horizontal dimension (e.g. along the Y direction) of each metal pattern part of the first metal layer pattern <NUM> may define a maximum length of a lower or a stacked metal line which may be patterned therein.

Correspondingly, the illustrated example shows a single discrete dielectric block of the second dielectric layer pattern <NUM>. However, it is to be understood that the second dielectric layer pattern <NUM> may comprise a set of multiple discrete dielectric blocks. Each dielectric block of the second dielectric layer pattern <NUM> may define a region in which no upper metal lines are to be formed.

In <FIG>, a mask material layer <NUM> has been formed over the over the intermediate layer stack of the device structure <NUM>. The mask material of the mask line pattern may be a hard mask material, e.g. any of the dielectric hard mask materials mentioned in connection with the ESL <NUM>. Prior to forming the mask material layer <NUM> a (fourth) metal liner layer <NUM> may be formed on top of the second dielectric layer pattern <NUM> and the second metal layer pattern <NUM>. Similar to the discussion of the metal liner <NUM>, the metal liner layer <NUM> may facilitate adhesion of the mask material layer <NUM> to the device structure <NUM>. The metal liner layer <NUM> may however be omitted in case the mask material layer <NUM> already presents sufficient adhesion to the device structure <NUM>.

An etch mask <NUM> defining a pattern of lines has been formed over the mask material layer <NUM>. The pattern of lines of the etch mask <NUM> may be formed using single- or multi-patterning techniques, such as lithography (e.g. Extreme Ultraviolet Lithography) and etching, or pitch splitting techniques such as SADP or SAQP. In the illustrated example, the etch mask <NUM> is formed to define a grating of regularly spaced apart lines. The method is however not so limited but it is also possible to form lines with different spacing and/or of different lengths. Further, the method is not limited to lines parallel along their entire lengths (i.e. unidirectional lines). For example, the lines of the pattern (or subsets thereof) may comprise portions extending along the X-direction and portions extending along the Y-direction. Variations in the line pattern may for example be introduced by forming cuts in the pattern of lines of the etch mask <NUM> prior to being transferred into the mask material layer <NUM>.

While in the depicted example, the second metal liner layer <NUM> (see <FIG>) and the fourth metal liner layer <NUM> (see <FIG>) are blanket-deposited, one or both may instead be deposited in an area-selective fashion using a metal-on-metal deposition process. For example, the metal liner layer <NUM> may be deposited selectively on an upper surface of the first metal layer pattern <NUM>. Additionally or alternatively, the metal liner layer <NUM> may be deposited selectively on an upper surface of the second metal layer pattern <NUM>. Sandwiching of redundant metal liner portions between dielectric layers of the interconnection structure may thus be avoided.

In <FIG>, the etch mask <NUM> has been used to pattern the mask material layer <NUM> to define a mask line pattern <NUM> of the mask material, wherein the mask line pattern <NUM> corresponds to or conforms to the pattern of lines of the etch mask <NUM>. The mask line pattern <NUM> accordingly comprises:.

As further shown in <FIG>, <FIG> and <FIG> the mask line pattern <NUM> has subsequently been transferred successively into the layer stack underneath. In <FIG> the first sub-pattern is transferred into the metal liner layer <NUM> and the second dielectric layer pattern <NUM>. In <FIG> the second and third sub-pattern is transferred into the second metal layer pattern <NUM>. In <FIG>, the first and second sub-pattern is transferred into the first metal layer pattern <NUM>, e.g. into the first portion 122a and the second portion 122b, respectively, thereby completing formation of a set of lower metal lines <NUM> of interconnection level MX, a set of upper metal lines <NUM> for interconnection level MX+<NUM>, and a set of stacked metal lines <NUM> spanning MX and MX+<NUM>.

More specifically, and with reference to <FIG>, the set of lower metal lines <NUM> are formed in the first portion 122a of the first metal layer pattern <NUM>. Each lower metal line <NUM> is capped by a respective dielectric line <NUM> formed in the portion 130a of the second dielectric layer pattern <NUM>. The set of upper metal lines <NUM> are formed in the second portion 136b of the second metal layer pattern <NUM>. Each upper metal line <NUM> is formed on top of the portion 114a of the first dielectric layer pattern <NUM>. Each stacked metal lines <NUM> comprises a lower line portion <NUM> (formed in the second portion 122b of the first metal layer pattern <NUM>) and, on top, an upper line portion <NUM> (formed in the first portion 136a of the second metal layer pattern <NUM>).

In the top-down view of <FIG>, all elements except for the metal lines <NUM>, <NUM>, <NUM> have been omitted to more clearly illustrate their respective layouts: the lower metal lines <NUM> are indicated by a dash-dotted outline, the upper metal lines <NUM> are indicated by a solid outline, and the stacked metal lines <NUM> are indicated by a dashed outline.

In the illustrated example, both lower metal lines <NUM> and lower line portions <NUM> are formed (in part) in a same discrete part of the first metal layer pattern <NUM>. This is however merely an example and it is also possible to form e.g. only lower metal lines <NUM> in a first discrete part of the first metal layer pattern <NUM> and only lower line portions <NUM> in another discrete part of the first metal layer pattern <NUM>. Correspondingly, it is possible to form only upper metal lines <NUM> in a first discrete part of the second metal layer pattern <NUM> and only upper line portions <NUM> in another discrete part of the second metal layer pattern <NUM>. It is further to be noted that the number of lines <NUM>, <NUM>, <NUM>, <NUM> shown in <FIG> is merely an example and that the method is not limited thereto.

As per the illustrated example, the metal liner <NUM> may be used as an etch stop layer for the transfer of the first sub-pattern into the second dielectric layer pattern <NUM> and also for the transfer of the second and third sub-patterns into the second metal layer pattern <NUM>. Furthermore, the ESL <NUM> may be used as an etch stop layer for the transfer of the first, second and third sub-pattern into the first metal layer pattern <NUM>. As a non-limiting example for a layer stack comprising an ESL <NUM> of SiN, a first metal layer pattern <NUM> and a second metal layer pattern <NUM> comprising a Ru fill metal, a second dielectric layer pattern <NUM> of SiN, a mask line pattern of SiN, and liner layers <NUM>, <NUM>, <NUM>, <NUM> of TiN, the etching process may after patterning the mask layer <NUM> to form the mask line pattern proceed as follows:.

As may be appreciated by the skilled person, the etching process used for the pattern transfer may comprise a number of successive etch steps comprising different chemistries selected in accordance with the specific material that is to be etched.

In the illustrated example, a set of openings <NUM> is patterned in the first dielectric layer <NUM> and a set of dielectrics blocks <NUM> is patterned in the second dielectric layer <NUM>. However, it is also possible to pattern a set of dielectric blocks (corresponding to blocks <NUM>) in the first dielectric layer <NUM> and a set of openings (corresponding to openings <NUM>) in the second dielectric layer <NUM>. The combination of openings in one of the dielectric layers and blocks in the other dielectric layer may be a convenient choice specifically for metal line patterning; the blocks may be used to define sub-regions in which no stacked metal lines are to be formed, within a densely populated region/pattern of upper metal lines (in case the blocks are patterned in the second dielectric layer <NUM>) or lower metal lines (in case the blocks are patterned in the first dielectric layer <NUM>), and the openings may be used to define sub-regions in which lower metal line portions (in case the openings are patterned in the first dielectric layer <NUM>) or upper metal line portions of stacked metal lines are to be formed. As may be appreciated, the relative populations of upper metal lines, stacked metal lines and lower metal lines may be controlled via the relative footprints and the overlap of the openings and the blocks (more generally via the relative footprints and the overlap of the first dielectric layer pattern and the second dielectric layer pattern).

In <FIG>, an interlayer dielectric <NUM> has been deposited to embed and cover the sets of metal lines <NUM>, <NUM>, <NUM> and the mask line pattern <NUM>, and then planarized (e.g. by CMP) to expose an upper surface of mask line pattern <NUM>. The interlayer dielectric <NUM> may be formed of a same material as the interlayer dielectric <NUM>. The mask line pattern <NUM> may provide a relatively large area of mask material (e.g. a dielectric hard mask material such as SiN) surrounded by the interlayer dielectric <NUM> (e.g. an oxide such as SiO<NUM>). This may facilitate end point detection for the planarization.

<FIG> is a schematic perspective view of a section of an interconnection structure comprising hybrid-height metal lines (e.g. lower metal lines <NUM>, stacked metal lines <NUM> and upper metal lines <NUM>) which may be formed using the method illustrated in <FIG>, wherein like reference signs refer to like elements.

<FIG> depict supplementary method steps for forming metal vias, may be may be performed in case the metal lines of the MX and MX+<NUM> levels are to be connected to metal lines of higher interconnection levels (e.g. MX+<NUM>).

In <FIG> a mask layer <NUM> (which may be denoted "via mask layer") has been formed over the upper interconnection level, e.g. on top of the interlayer dielectric <NUM> and the mask line pattern <NUM>. The mask layer <NUM> may be formed of a hard mask material, e.g. any of the dielectric hard mask materials, however of a different material than the mask line pattern <NUM> with an etch contrast thereto, such that the mask layer <NUM> may be used as an etch mask during the subsequent etching of via holes.

In <FIG> a set of via openings <NUM>, <NUM>, <NUM> has been patterned in the mask layer <NUM>, e.g. using a lithography and etching process. The set of via openings <NUM>, <NUM>, <NUM> has been transferred into the upper interconnection level by etching while using the (patterned) mask layer <NUM> as an etch mask, thereby forming a set of via holes <NUM>, <NUM>, <NUM> for metal vias over the lower, stacked and upper metal lines <NUM>, <NUM>, <NUM>.

More specifically, as shown, a first via hole <NUM> exposing an upper surface of a first lower metal line 150a is patterned by etching from the first via opening <NUM>. The first via hole <NUM> extends through a first mask line of the mask line pattern <NUM> overlying the first lower metal line 150a, and a first dielectric line of the set of dielectric lines <NUM> capping the first lower metal line 150a (and the metal liners <NUM> and/or <NUM> if present).

A second via hole <NUM> exposing an upper surface of a first stacked metal line <NUM> is patterned by etching from the second via opening <NUM>. The second via hole <NUM> extends through a second mask line of the mask line pattern <NUM> overlying the first stacked metal line <NUM> (and the metal liner <NUM> if present).

A third via hole <NUM> exposing an upper surface of a first upper metal line 156a is patterned by etching from the third via opening <NUM>. The third via hole <NUM> extends through a third mask line of the mask line pattern <NUM> overlying the first upper metal feature 156a (and the metal liner <NUM> if present).

The etching process used for the via hole patterning may comprise a number of successive etch steps comprising different chemistries selected in accordance with the specific material that is to be etched.

The mask material of the first, second and third dielectric lines of the set of dielectric lines <NUM> may be etched selectively to the inter layer dielectric <NUM>, wherein the via holes <NUM>, <NUM>, <NUM> may be self-aligned with the respective metal lines 150a, <NUM>, 156a underneath. Forming the first via hole may further comprise etching the dielectric material of the first dielectric line capping the first lower metal line 150a selectively to the interlayer dielectric <NUM>. Hence also a lower portion of the first via hole <NUM> may be formed in a self-aligned manner with respect to the lower metal line 150a. Etching processes and chemistries for etching e.g. conventional dielectrics and dielectric hard mask materials (e.g. SiN, AIN, AlOx or SiOC) selectively to interlayer dielectrics (e.g. SiO<NUM>) are per se known in the art.

The etching process (e.g. each of the etch steps thereof) may further be adapted to not appreciably etch the fill metal of the metal lines <NUM>, <NUM>, <NUM>. In other words, the metal lines <NUM>, <NUM>, <NUM> may be used as an etch stop layer for the etching process. Depending on presence of the metal liners <NUM> and/or <NUM>, the etching process may comprise an etch step for opening the metal liner <NUM> (to form each of the via holes <NUM>, <NUM>, <NUM>) and/or an etch step for opening the metal liner <NUM> (to form the via hole <NUM>). These etch steps may advantageously be selective to the metal liner <NUM>/<NUM> to not appreciably etch the surrounding dielectric and the mask layer <NUM>.

While in the illustrated example, the first, second and third via holes <NUM>, <NUM>, <NUM> are patterned simultaneously using a same mask layer <NUM> as etch mask, it is also possible to pattern the first, second and third via holes <NUM>, <NUM>, <NUM> sequentially using different etch masks. For instance, the first via hole <NUM> may be patterned using a first lithography and etching process and the second and third via holes <NUM>, <NUM> may be patterned sequentially using a second and a third lithography and etching process, respectively, or simultaneously using a (common) second lithography and etching process.

After forming the via holes <NUM>, <NUM>, <NUM>, the mask layer <NUM> may be removed and the via formation may be completed by filling the via holes <NUM>, <NUM>, <NUM> with metal. Overburden metal may be removed by planarization. The metal via formed in the first via hole <NUM> may form a HAR via, while the metal vias in the second and third via holes <NUM>, <NUM> may form LAR vias.

The method may then proceed with forming metal lines of a further interconnection level (e.g. MX+<NUM>), for instance by repeating the method steps described above, or using a conventional damascene-style process.

<FIG> is a schematic perspective view corresponding to <FIG>, wherein additionally via holes <NUM> of HAR and via holes <NUM>, <NUM> of LAR have been formed to accommodate metal vias on top of lower metal lines <NUM>, stacked metal lines <NUM> and upper metal lines <NUM>.

Claim 1:
A method for forming an interconnection structure, comprising:
forming a first dielectric layer pattern (<NUM>) over a substrate covering the first dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the first dielectric layer pattern and form a first metal layer pattern (<NUM>);
forming a second dielectric layer pattern (<NUM>) over the first dielectric layer pattern and the first metal layer pattern;
covering the second dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the second dielectric layer pattern and form a second metal layer pattern (<NUM>),
wherein the second dielectric layer pattern comprises a portion overlying a first portion of the first metal layer pattern, and the second metal layer pattern comprises a first portion (136a) overlying a second portion of the first metal layer pattern, and a second portion (136b) overlying a portion of the first dielectric layer pattern;
forming a mask pattern (<NUM>) of a mask material over the second dielectric layer pattern and the second metal layer pattern, wherein the mask pattern comprises a first sub-pattern of mask features overlying said first portion of the first metal layer pattern, a second sub-pattern of mask features overlying said first portion of the second metal layer pattern, and a third sub-pattern of mask features overlying said second portion of the second metal layer pattern; and
in an etching process comprising using the mask pattern as an etch mask, transferring: the first sub-pattern into said first portion of the first metal layer pattern to form a set of lower metal features (<NUM>),
the second sub-pattern into said first portion of the second metal layer pattern and said second portion of the first metal layer pattern to form a set of stacked metal features (<NUM>), and the third sub-pattern into said second portion of the second metal layer pattern to form a set of upper metal features (<NUM>).