Patent Description:
<CIT> discloses semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die.

<CIT> discloses a semiconductor device that has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semi-conductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die.

<CIT> discloses stairstep interposers with integrated conductive shields, and related assemblies and techniques. An interposer includes an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate.

<CIT> recites a method and an apparatus for power delivery to a die stack via a heat spreader.

The invention is defined by the independent claim.

One aspect of the disclosure provides an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias (TMVs) or through dielectric vias (TDVs).

In some instances, the integrated voltage regulator die is connected to the silicone layer by a power distribution network (PDN). In some examples, the PDN includes one or more through silicon vias (TSVs) within the silicon layer. In some examples, the PDN further includes a redistribution layer configured to provide power from the integrated voltage regulator die to the TSVs. In some examples, the TSVs and redistribution layer form an inductor.

In some instances, each of the one or more TMVs are connected to the packaging substrate on a first end by a flip chip bump and to the integrated voltage regulator die at a second opposite end.

In some instances, the silicon layer is connected to the packaging substrate via one or more flip chip bumps.

In some instances, the packaging substrate is configured to connect to a land grid array (LGA) socket or ball grid array (BGA) socket. In some examples, power is delivered to the integrated voltage regulator die via the LGA socket or the BGA socket. In some examples, the packaging substrate includes a redistribution layer configured to route the power from the LGA socket or the BGA socket to the one or more TMVs.

In some instances, the IC die may be an application specific integrated circuit (ASIC) die.

Another aspect of the technology is directed to an integrated circuit (IC) package including a packaging substrate, an application specific integrated circuit (ASIC) die, and an integrated voltage regulator die. The ASIC die may include a metal layer and a silicon layer, the metal layer being connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias (TMVs) or through dielectric vias (TDVs), the integrated voltage regulator die configured to provide power to the ASIC die.

In some instances, the integrated voltage regulator die is connected to the silicone layer by a power distribution network (PDN). In some examples, the PDN includes one or more through silicon vias (TSVs) within the silicon layer, and the integrated voltage regulator die is configured to provide power to the ASIC die via the TSVs. In some examples, the PDN further includes a redistribution layer configured to provide power from the integrated voltage regulator die to the TSVs. In some examples, the TSVs and redistribution layer form an inductor.

In some instances, the IC package further includes deep trench capacitors embedded into the silicon layer or stacked on the silicon layer for use by the integrated voltage regulator die.

The technology relates generally to integrating a voltage regulator die onto the backside of an application specific integrated circuit (ASIC) package. For example, and as shown in <FIG>, the ASIC package <NUM> includes an ASIC die <NUM> including a silicon substrate <NUM> and one or more metal layers <NUM>. The ASIC die <NUM> may be positioned such that the metal layer is adjacent to a packaging substrate <NUM>. An integrated voltage regulator die <NUM> may be mounted to the backside of the ASIC die <NUM>, adjacent to the silicon substrate <NUM>. Power may be delivered to the ASIC die <NUM> by the integrated voltage regulator die <NUM> using a backside power distribution network PDN <NUM> including through-silicon vias (TSVs) <NUM> and a redistribution layer <NUM>. The ASIC package <NUM> may include a housing, such as housing <NUM> in which at least some of the components of the ASIC package <NUM> may be positioned.

As previously described, increases in processing speed of an ASIC die may increase the amount of power required to operate the ASIC die. An increase in power drawn by an ASIC die within a typical ASIC package may result in an increase of heat within the ASIC package due to copper losses generated by the wires and/or other such connections which carry the power through the ASIC package. Copper losses, also known as "I<NUM>R losses", where 'I' is the current flowing through the copper wiring and 'R' is the resistance of the wiring, is the amount of heat dissipated as current passes through wiring. The increase in temperature generated by the increased power draw of the ASIC die may result in solder electromigration and potential failure of solder joints. The increase of temperature may also affect the thermal performance of the ASIC die and other components within the ASIC package, potentially leading to failure of the ASIC die, failure of other components of the ASIC package, or reduced processing performance.

To reduce or remediate the amount of copper losses generated by wires, planes, such as copper planes, redistribution layers, and/or other such connections which carry the power through the ASIC package to the ASIC die, a voltage regulator may be integrated into the ASIC package.

The packaging substrate <NUM> may be configured to connect the ASIC package <NUM> to a circuit board or other such chip carrier. In this regard, the packaging substrate <NUM> may have arrays of connectors on its top side and bottom side, as shown in <FIG>, respectively. In some instances, connectors may be included on the sides of the packaging substrate <NUM>. Referring to <FIG>, although the packaging substrate <NUM> is shown as being outside of housing <NUM>, the packaging substrate <NUM> may be positioned fully or partially within the housing <NUM>.

Referring to <FIG>, a top side <NUM> of the packaging substrate <NUM> shows a plurality of connectors, including connectors <NUM>-<NUM>. For clarity, only a portion of the connectors on the top side <NUM> of the packaging substrate <NUM> are labeled. The connectors, including connectors <NUM>-<NUM>, may be connector pads onto which other components of the ASIC package <NUM> may be connected, as described herein. The connector pads may be gold, nickel, tin, copper, solder, or other such conductive materials.

The top side <NUM> of the packaging substrate <NUM> may include any number of connector pads arranged in any layout. In this regard, the arrangement and number of connectors, including connector pads <NUM>-<NUM>, shown in <FIG> is merely for illustration. For instance, the number and arrangement of connector pads on the top side of the packaging substrate may be based on the design and arrangement of the ASIC die <NUM>, integrated voltage regulator die <NUM>, and/or other components within the ASIC package <NUM> to allow for the ASIC package to attach to the top side of the packaging substrate <NUM>.

<FIG> shows a bottom side <NUM> of the packaging substrate including a plurality of connectors, including connectors <NUM>-<NUM>. For clarity, only a portion of the connectors on the bottom side <NUM> are labeled. The connectors, including connectors <NUM>-<NUM>, may be configured to connect or otherwise mount the ASIC package <NUM> to a printed circuit board (PCB), socket, or other such chip carrier. The connectors may be solder balls, pins, sockets, etc. The connectors <NUM>-<NUM> may be gold, nickel, tin, copper, solder, or other such conductive material.

The bottom side <NUM> of the packaging substrate may include any number of connectors in any arrangement. In this regard, the arrangement and number of connectors, including connectors <NUM>-<NUM>, shown in <FIG> is merely for illustration. For instance, the connectors on the bottom side <NUM> of the packaging substrate may be solder balls arranged in a ball grid array (BGA). Other such arrangements and connectors may include contacts arranged in a land grid array (LGA), connector pins arranged in a pin grid array (PGA), etc..

The integrated voltage regulator die <NUM> may be connected to one or more connector pads on the top side <NUM> packaging substrate <NUM>. For instance, the connection between the voltage regulator die <NUM> and the packaging substrate <NUM> may be made via one or more through mold vias (TMVs), such as TMV <NUM>, as shown in <FIG>. For clarity, only a portion of the TMVs shown in <FIG> are labeled.

Each TMV may connect the integrated voltage regulator die <NUM> to the packaging substrate <NUM> via a connector pad or other such connector. For instance, the first end <NUM> of TMV <NUM> may be attached to a connector pad <NUM> and the opposite end <NUM> of the TMV <NUM> may be attached to the integrated voltage regulator die <NUM>.

The connection between the TMVs and the connector pads may be made via a soldered flip chip bump. For example, <FIG> shows an exploded side-view of a portion <NUM> of the ASIC package <NUM>, including the connection between TMV <NUM> and connector pad <NUM>. The first end <NUM> of the TMV <NUM> is connected to connector pad <NUM> on the top side <NUM> of the packaging substrate <NUM> via a soldered flip chip bump <NUM>. Although the TMVs are shown as being connected via soldered flip chip bumps in <FIG>, other connectors and connections may be used.

The metal layer <NUM> of the ASIC die <NUM> may also be connected to the packaging substrate <NUM>. The connection of the metal layer <NUM> to the packaging substrate <NUM> may be made via flip chip bumps and connector pads, or other such connectors. For example, and as further shown in <FIG>, flip chip bump <NUM> connects the metal layer <NUM> to connector pad <NUM>, on the top side <NUM> of the packaging substrate. Although the flip chip bumps are shown in <FIG> as being soldered onto connector pads, such as flip chip bump <NUM> being soldered onto connector pad <NUM>, other connections may be used.

Power may be supplied to the ASIC package <NUM> by an external power source. In this regard, the external power source may provide power to the ASIC package <NUM> through the chip carrier to which the ASIC package <NUM> is mounted. For example, and as illustrated in <FIG>, power, shown as arrow <NUM>, may be supplied from an external power source (not shown) to the PCB <NUM>. PCB <NUM> may supply the power to a connector on the packaging substrate.

The packaging substrate may include a redistribution layer etched onto, or otherwise embedded within, that routes power between the connectors on the bottom side <NUM> of the packaging substrate and connector pads <NUM> on the top side of the packaging substrate <NUM>. For instance, power <NUM> delivered by the PCB, or other such chip mount, at connector <NUM> on the bottom side <NUM> of the packaging substrate <NUM> may be routed by the redistribution layer to connector pad <NUM> on the top side <NUM> of the packaging substrate. Although <FIG> illustrates the power <NUM> being supplied to connector <NUM> and routed to connector pad <NUM>, power may be supplied to any of the connectors on the bottom side of the packaging substrate <NUM>, and in some instances, to more than one connectors. The power may be routed by the redistribution layer from the one or more connectors to one or more of the connector pads. For instance, power may be routed from one or more of the connectors on the bottom side <NUM> of the packaging substrate <NUM> to one, two, three, or more connector pads on the top side <NUM> of the packaging substrate <NUM>.

Power may be carried from the packaging substrate <NUM> to the integrated voltage regulator die <NUM> by one or more TMVs. For example, <FIG> shows power <NUM> being routed by TMV <NUM> from connector pad <NUM> to the integrated voltage regulator die <NUM>. For clarity, power is shown being routed through only TMV <NUM>. In some instances, power may be routed to the integrated voltage regulator die <NUM> by more than one TMV.

Power received by the integrated voltage regulator die may be considered the input power supply. The input power supply may be delivered to the integrated voltage regulator die <NUM> at a higher voltage level and lower current level than the input power supply delivered directly to the ASIC die. The integrated voltage regulator die <NUM> may provide power to the ASIC die <NUM> with a different supply voltage level. For example, the integrated voltage regulator die <NUM> may operate as a switching voltage regulator and adjust the amount of voltage supplied to the ASIC die based on the needs of the ASIC die or other components within the ASIC package <NUM>.

The integrated voltage regulator die <NUM> may deliver power to the ASIC die <NUM> via backside TSVs. For example, and as shown in <FIG>, power, illustrated by arrow <NUM> may be provided from the integrated voltage regulator die <NUM> to a backside redistribution layer <NUM>. The redistribution layer <NUM> may direct power to one or more TSV <NUM>, including TSV <NUM>, embedded within the silicon layer <NUM> of the ASIC die <NUM>. Although <FIG> illustrates power being delivered to all of the TSVs <NUM>, power may be delivered to any number of TSVs.

Referring to <FIG>, the backside redistribution layer <NUM> may be etched into and/or positioned above the silicon layer <NUM>. The backside redistribution layer <NUM> together with the TSVs may be used to create inductors for use by the integrated voltage regulator die <NUM>. Deep trench capacitors (DTCs) may also be embedded into the silicon layer <NUM> of the ASIC die <NUM> for use by the integrated voltage regulator die <NUM>. In this regard, switching voltage regulators typically require many inductors and capacitors to operate. In instances where the integrated voltage regulator die <NUM> is a switching voltage regulator, the backside redistribution layer <NUM>, the TSVs <NUM>, as well as the DTC's embedded silicon (not shown) may provide at least some the functionality of inductors and capacitors. In some instances, the inductors and DTCs may be stacked onto the ASIC die.

As discussed herein, increases in processing speed of an ASIC die may increase the amount of power required to operate the ASIC die. An increase in power drawn by an ASIC die within an ASIC package without an integrated voltage regulator die may result in an increase of heat within the ASIC package due to copper losses generated by the wires and/or other such connections which carry the power through the ASIC package. By integrating the integrated voltage regulator die in the ASIC package, such as integrated voltage regulator die <NUM> in ASIC package <NUM>, the power drawn by the ASIC package from an external power source may be limited, controlled, or otherwise regulated. For example, the integrated voltage regulator die <NUM> may cap the amount of power drawn by the components within ASIC package <NUM>, such as ASIC die <NUM>. In some examples, the integrated voltage regulator die <NUM> may include a closed loop feedback system to provide a steady voltage output.

In another example, the integrated voltage regulator die <NUM> may throttle the amount of power drawn, such as when the temperature of the ASIC die <NUM> is above a particular value or the ASIC die <NUM> does not require full power to operate. The integrated voltage regulator die <NUM> may also accept higher input voltages, thereby reducing the current supplied to the ASIC package <NUM> by an external power supply. Accordingly, the amount of current carried by the wires, traces, and/or other such connections on or within the ASIC package may be reduced, resulting in a decrease in the amount of copper losses and minimizing electromigration failure risk in the ASIC package. Moreover, the integrated voltage regulator die <NUM> may reduce overall power consumption and increase power efficiency of the ASIC package <NUM>.

The voltage regulator may maintain a consistent power draw from the external power source, thereby preventing or reducing the number of increases in power carried by the wires, traces, and/or other such connections on or within the ASIC package <NUM>. In some instances, the integrated voltage regulator die <NUM> can include a closed loop feedback system to minimize voltage fluctuations output. In this regard, a feedback sense line may monitor the voltage output by the integrated voltage regulator die <NUM> and feed monitored voltage level back to the integrated voltage regulator die <NUM>. The feedback sense line may have high bandwidth, so the integrated voltage regulator die <NUM> may be able to compensate for voltage fluctuations quickly. By doing such, inductive noise caused by voltage fluctuations may be reduced.

A typical ASIC die will receive power from connectors on a packaging substrate which are closer to the ASIC die to reduce the amount of heat generated by power delivery. Consequently, data signals may be required to traverse longer paths from the ASIC die to connectors positioned on the exterior of the packaging substrate, thereby slowing the processing speed of the ASIC package. <FIG> illustrates an interior and exterior collection of connectors, <NUM> and <NUM>, respectively, on the top side <NUM> of a packaging substrate <NUM>. In a typical ASIC package, power may be delivered by the connectors within the interior <NUM> of the packaging substrate <NUM> and data may be delivered by the connections within the exterior <NUM> of the packaging substrate <NUM>.

Referring to <FIG>, by positioning the integrated voltage regulator die <NUM> above the ASIC die <NUM> and connecting the integrated voltage regulator die <NUM> to the packaging substrate through TMVs <NUM> positioned around the exterior of the ASIC die <NUM>, the data connections between the ASIC die <NUM> and the packaging substrate <NUM> may be moved to the interior collection of connectors <NUM>. Accordingly, the distance data needs to travel from the ASIC die <NUM> to the packaging substrate <NUM> may be reduced, as illustrated by arrows <NUM>, resulting in improved communication speeds and reduced signal loss. The data connections may be routed by the redistribution layer in the packaging substrate and may include SERDES connections, parallel connections, serial connections, etc..

Although the example ASIC packages <NUM> and <NUM> described herein are described with reference to a single ASIC die <NUM>, <NUM>, respectively, each ASIC package may include any number of ASIC dies. Moreover, each ASIC package may include any number of voltage regulators or other components. Additionally, although the packages described herein are described as ASIC packages having ASIC dies, any type of die may be used, such as a memory die or integrated circuit die.

Claim 1:
An integrated circuit, IC, package comprising:
a packaging substrate (<NUM>);
an IC die including a metal layer (<NUM>) and a silicon layer (<NUM>), the metal layer (<NUM>) being connected to the packaging substrate (<NUM>); and
an integrated voltage regulator die (<NUM>) positioned adjacent to the silicon layer (<NUM>) and connected to the packaging substrate (<NUM>) via one or more through mold vias, TMVs, (<NUM>) or through dielectric vias, TDVs,
wherein the integrated voltage regulator die (<NUM>) is configured to regulate power provided to the IC die.