Patent Description:
In many cases the energy consumption of an electronic device, such as a digital processor circuit, is a critical issue. For example, technologies such as the Internet-of-Things "IoT", the Industrial Internet "II", and the Internet-of-Everything "IoE" are on the threshold of a massive breakthrough, and the major drivers behind the breakthrough are ubiquitous wireless processing nodes. However, the energy consumption of transmitting a bit across a given distance does not scale with Moore's law as advantageously as the digital processing within a wireless node. Therefore the energy cost of wireless transmission will proportionally grow when compared to digital processing. Increasing the energy efficiency thus requires increasing the amount of intra-node processing in order to minimize the wireless transmission of data. Therefore, the processor and the digital signal processing "DSP" will become one of the, if not the, most important parts to be optimized. This will be compounded by the increasing functionalities of the wireless node, such as e.g. Machine Learning, Video, etc..

For example, in conventional digital Complementary Metal Oxide Semiconductor "CMOS" designs, the operating voltage i.e. the power supply voltage VDD is typically <NUM> Volt or greater. The energy consumption indicated by the power consumption is substantially quadratically dependent on the operating voltage VDD, i.e. the power consumption is substantially proportional to VDD<NUM>. Therefore, there is a strong motivation to reduce the operating voltage VDD for a wide range of applications from energy-constrained systems, e.g. the Internet-of-Things "IoT", to thermal-constrained systems, e.g. servers. There is a lower bound on the operating voltage VDD due to: a) functional limitations of the technology such as e.g. the CMOS technology and b) performance limitations such as e.g. limitations on the operating speed. By operating slightly above the lower bound of the operating voltage VDD, or near the threshold voltage, "NTV", the digital design is robust, has low energy consumption, and has a good performance. Thus, there is an increasingly large amount of researchers and companies building digital NTV designs. In some cases and especially in conjunction with central processing units "CPU", the operating voltage is often called core voltage.

A potential market of the NTV is in near-future electronics for applications such as the above-mentioned IoT and wireless wellbeing and healthcare. Growth in the healthcare industry is expected to be one of the major drivers and is expected to have a positive impact on embedded system demand. This can be attributed to the substantial number of embedded systems used in medical devices such as blood glucose monitors.

Ideally, an electronic system would be able to scale its operation from the nominal operating voltage down to the NTV. However, reducing the operating voltage below the threshold voltage results in a dramatic loss in performance and in practice may lead to functional failure. Therefore, in order to operate at the NTV, there needs to be a method to identify where the threshold voltage is located. The method is advantageously dynamic since the threshold voltage in for example CMOS devices changes with both local and global variations, e.g. temperature. In addition, a body bias is used in modern CMOS to intentionally move the threshold voltage. In a known technical solution for reducing the energy consumption, the operating voltage VDD is determined with the aid of a look-up table which gives the value of the operating voltage as a function of operating parameters such as for example throughput requirements and/or temperature. However, the look-up table is finalized at the design phase of the electronic system and therefore the look-up table has to include a safety margin to overcome dynamic changes and post-design variables. This safety margin leads to energy loss at run time.

Technical solutions usable in conjunction with and/or related to optimizing energy consumption are described for example in the following publications: <CIT>, <CIT>, and <CIT>.

Prior art further includes <CIT> which discloses a performance scaling device, a processor having the same, and a performance scaling method thereof.

Prior art further includes <NPL>) which discloses a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors.

Prior art further includes <CIT> which discloses a memory system that includes an error detection circuit having an error counter.

The following summary merely presents some concepts in a simplified form as a prelude to a more detailed description of exemplifying embodiments of the invention.

In accordance with the invention, there is provided a new control system for controlling operating voltage VDD supplied to an electronic device such as e.g. a digital processor circuit. The electronic device is provided with a timing event detector responsive to timing events related to the operation of the electronic device. The timing events can be for example responsive to errors related to the operation of the electronic device, and/or to signals about the dynamic operation of the device, such as time-borrowing signals, and/or to any other signals or events directly or indirectly indicative of quality, performance, or some other appropriate property or properties of the operation of the electronic device.

A control system according to the invention is defined in claim <NUM>.

In this document, the term "increasing function" means a function whose derivative is positive, e.g. dFclk/dVDD > <NUM>, i.e. the clock frequency decreases when the operating voltage decreases and increases when the operating voltage increases. The above mentioned rate of the time-borrowing events can be, for example but not necessarily, the rate of errors related to the operation of the electronic device.

As the above-mentioned clock frequency Fclk is varied together with the operating voltage VDD when searching for the above-mentioned threshold voltage, it is possible to find a voltage-frequency operating point where the energy consumption of the electronic device is minimized so that the detected time-borrowing event rate is however kept at an acceptable level and thus the performance does not crash. The control system is advantageously configured to operate during the operation of the electronic device so as to dynamically adapt the operating voltage VDD and the clock frequency Fclk with respect to changes in operating conditions, e.g. temperature.

In accordance with the invention, there is provided also a new electronic system that comprises:.

The electronic device may further comprise error-repair and/or error prevention logic responsive to errors related to the operation of the electronic device so as to repair the errors related to the operation of the electronic device.

In accordance with the invention, there is provided also a new method for controlling operating voltage supplied to an electronic device as defined in claim.

In the method according to the invention, the clock frequency that represents the pulse rate of the clock signal operating the electronic device is according to an increasing function of the operating voltage such that the rate of the time-borrowing events is substantially at the target level when the operating voltage is above the threshold voltage, and the rate of the time-borrowing events exceeds the target level when the operating voltage is below the threshold voltage.

In accordance with the invention, there is provided also a new computer program product comprising a non-transitory computer readable medium as defined in claim <NUM>.

The computer program product comprises a non-volatile computer readable medium, e.g. a compact disc "CD", encoded with a computer program according to the invention.

In accordance with the invention, there is provided also a new signal that carries information defining a computer program according to an embodiment of invention. The signal can be received for example from a communication network, e.g. from a cloud service.

A number of exemplifying and non-limiting embodiments of the invention are described in accompanied dependent claims.

Various exemplifying and non-limiting embodiments of the invention both as to constructions and to methods of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific exemplifying embodiments when read in connection with the accompanying drawings.

The features recited in the accompanied dependent claims are mutually freely combinable unless otherwise explicitly stated.

Exemplifying and non-limiting embodiments of the invention and their advantages are explained in greater detail below with reference to the accompanying drawings, in which:.

The specific examples provided in the description below should not be construed as limiting the scope and/or the applicability of the accompanied claims. Lists and groups of examples provided in the description below are not exhaustive unless otherwise explicitly stated.

<FIG> shows a functional block diagram of an electronic system according to an exemplifying and non-limiting embodiment of the invention. The electrical system comprises an electronic device <NUM> that can be for example a digital processor circuit. The electronic device <NUM> is provided with a timing event detector responsive to timing events, e.g. errors, related to operation of the electronic device. The electronic device <NUM> produces a timing event signal <NUM> that comprises pulses corresponding to timing events related to the operation of the electronic device. For example, each pulse in the timing event signal <NUM> may correspond to, for example but not necessarily, one error in the operation of the electronic device <NUM>. In addition to the timing event detector, the electronic device <NUM> may further comprise error-repair and/or error prevention logic responsive to errors so as to repair the errors. An exemplifying electronic device which is provided with a timing event detector and error-repair and/or error prevention logic of the kind mentioned above can be found e.g. from the publication <CIT>.

The electronic system comprises a control system <NUM> for controlling operating voltage VDD supplied to the electronic device <NUM>. The control system <NUM> is configured to produce a voltage control signal <NUM> for controlling a voltage regulator <NUM>. The voltage regulator <NUM> is configured to convert voltage of an energy source <NUM> into direct "DC" voltage whose value depends on the voltage control signal <NUM>. The voltage regulator <NUM> can be for example a switched mode DC-DC converter or an AC-DC converter. The energy source <NUM> can be for example a battery, a fuel cell, a power grid supplying alternative voltage, or an energy harvested source.

The control system <NUM> comprises a controllable clock signal generator <NUM> for producing a clock signal <NUM> for operating the electronic device <NUM>. The control system <NUM> further comprises a controller <NUM> for determining the rate of timing events, e.g. errors, related to the operation of the electronic device <NUM>. The rate of timing events can be determined for example with the aid of two counters so that one of the counters counts pulses of the clock signal <NUM> and the other one of the counters counts pulses of the timing event signal <NUM>. The rate of timing events can be defined for example as a ratio of the number of the pulses of the timing event signal <NUM> and the number of the pulses of the clock signal <NUM> counted during a suitable sample period. The controller <NUM> is configured to decrease the operating voltage VDD as long as the rate of timing events is below a predetermined target level, and to increase the operating voltage VDD when the rate of the timing events exceeds the target level so as to search for a threshold voltage Vth that is the smallest value of the operating voltage at which the rate of the timing events is substantially at the target level. The target level can be for example <NUM> %, i.e. the pulse rate of the timing event signal <NUM> is <NUM> times smaller than the pulse rate of the clock signal <NUM>.

The controllable clock signal generator <NUM> is configured produce the clock signal <NUM> so that the clock frequency Fclk that represents the pulse rate of the clock signal <NUM> is according to an increasing function of the operating voltage VDD such that the rate of timing events is substantially at the target level when the operating voltage is above the threshold voltage Vth and the rate of timing events exceeds the target level when the operating voltage is below the threshold voltage.

<FIG> illustrates an exemplifying case where the timing events being detected are errors related to the operation of the electronic device <NUM>. Thus, in <FIG>, the rate of the detected timing events is the rate of errors. In <FIG>, the rate of errors as a function of the operating voltage VDD is depicted with a curve <NUM> and the clock frequency Fclk as the above-mentioned increasing function of the operating voltage VDD is depicted with a curve <NUM>. On the curve <NUM>, the clock frequency Fclk can be substantially according to the following equation (<NUM>) when the operating voltage VDD is sufficiently greater than the threshold voltage Vth:
<MAT>
where K is a delay-fitting parameter, Cg is the output capacitance of the characteristic inverter related to the transistor technology of the electronic device, and αv is the velocity saturation index that is between <NUM> and <NUM>. The curve <NUM> can be approximated for example with a suitable polynomial function of the VDD.

As can be seen from <FIG>, the rate of errors depicted with the curve <NUM> is substantially at the target level when the operating voltage VDD is above the threshold voltage Vth and the clock frequency Fclk is according to the curve <NUM>. The rate of errors increases rapidly when the operating voltage VDD is decreased below the threshold voltage Vth and the clock frequency Fclk is according to the curve <NUM>. In <FIG>, a curve <NUM> illustrates how the clock frequency Fclk should be decreased when the operating voltage VDD decreases below the threshold voltage Vth in order to keep the rate of errors at the target level. On the curve <NUM>, the clock frequency Fclk can be substantially according to the following equation (<NUM>) when the operating voltage VDD is less than or equal to the threshold voltage Vth:
<MAT>
where IO is the ON current of the characteristic inverter related to the transistor technology of the electronic device, n is the sub-threshold swing coefficient, and UT is the thermodynamic voltage. More detailed information about the above-presented equations can be found from e.g.: <NPL>.

As can be seen from <FIG>, the curves <NUM> and <NUM> coincide when the operating voltage VDD is above the threshold voltage Vth, and the curves <NUM> and <NUM> deviate from each other when the operating voltage VDD is below the threshold voltage Vth. A curve <NUM> shown in <FIG> illustrates the average energy consumption per operation of the electronic device <NUM>. The operation can be for example an arithmetic-logical operation, writing to a register, or reading from a register. As illustrated by the curve <NUM>, the energy per operation is high when the operating voltage VDD is high or when the operating voltage VDD is low. A high operating voltage causes high energy consumption per operation because electrical currents for charging and discharging internal capacitances of the electronic device <NUM> grow along with the operating voltage, whereas a low operating voltage causes high energy consumption per operation because of leakage currents through semiconductor switches of the electronic device <NUM>.

As can be seen from <FIG>, the minimum of the energy per operation is located in the vicinity of the threshold voltage Vth. It has been noticed that in conjunction with many types of electronic devices, e.g. CMOS circuits, the minimum of the energy per operation is located in the vicinity of a threshold voltage at which the rate of errors starts to rapidly grow when the operating voltage decreases below the threshold voltage and the clock frequency is according to a downwards convex increasing function of the operating voltage. The term "downwards convex function" means that the graph of the function is at each point under consideration above the tangent of the graph. Thus, the energy consumption of the electronic device <NUM> can be optimized by controlling the operating voltage VDD to be the threshold voltage Vth or slightly above, e.g. <NUM>-<NUM>%, the threshold voltage Vth.

In a control system according to an exemplifying and non-limiting embodiment of the invention, the controllable clock signal generator <NUM> is constructed with electrical components which have been selected to produce the clock signal <NUM> so that the clock frequency Fclk behaves in a desired way when the operating voltage VDD changes, i.e. the clock frequency Fclk is according to the desired increasing function of the operating voltage VDD. The controllable clock signal generator <NUM> may comprise for example a voltage-controlled-oscillator "VCO" that is responsive to the operating voltage VDD in accordance with to the desired increasing function of the operating voltage VDD.

In some cases, there can be however a need to tune the controllable clock signal generator <NUM> to produce the clock signal <NUM> so that the clock frequency Fclk behaves in a desired way when the operating voltage VDD changes. In a control system according to an exemplifying and non-limiting embodiment of the invention, the controller <NUM> is configured to set, prior to searching for the threshold voltage Vth, the operating voltage VDD to have an initial value V_ini greater than the threshold voltage Vth and to control the controllable clock signal generator <NUM> to increase the clock frequency Fclk when the rate of timing events, e.g. errors, is below the target level and to decrease the clock frequency Fclk when the rate of timing events exceeds the target level so as to search for an initial value F_ini of the clock frequency Fclk corresponding to the initial value V_ini of the operating voltage VDD. The controller <NUM> is configured to tune, on the basis of the initial values V_ini and F_ini, the controllable clock signal generator <NUM> to operate in the desired way, i.e. in accordance with the increasing function illustrated with the curve <NUM>. In <FIG>, the tuning of the controllable clock signal generator <NUM> is depicted with a dashed line arrow <NUM>. The tuning can be for example setting an input bias voltage of a VCO so that Fclk = F_ini when VDD = V_ini.

<FIG> shows a functional block diagram of an electronic system according to an exemplifying and non-limiting embodiment of the invention. The electrical system comprises an electronic device <NUM> that is provided with a timing event detector responsive to timing events, e.g. errors, related to operation of the electronic device. The electronic device <NUM> produces a timing event signal <NUM> that comprises pulses corresponding to timing events related to the operation of the electronic device. In addition to the timing event detector, the electronic device <NUM> may further comprise error-repair and/or error prevention logic responsive to the errors so as to repair the errors related to the operation of the electronic device. The electronic system comprises a control system <NUM> for controlling operating voltage VDD supplied to the electronic device <NUM>. The control system <NUM> is configured to produce a voltage control signal <NUM> for controlling a voltage regulator <NUM>.

The control system <NUM> comprises a controllable clock signal generator <NUM> for producing a clock signal <NUM> so as to operate the electronic device <NUM>. The control system <NUM> further comprises a controller <NUM> for determining the rate of timing events, e.g. errors, related to the operation of the electronic device <NUM>. The controller <NUM> is configured to decrease the operating voltage VDD as long as the rate of timing events is below a target level, and to increase the operating voltage VDD when the rate of timing events exceeds the target level so as to search for a threshold voltage Vth that is the smallest value of the operating voltage VDD at which the rate of timing events is substantially at the target level.

The controller <NUM> is configured to produce a frequency control <NUM> signal for controlling the clock signal generator <NUM>. The clock signal generator <NUM> is controlled to produce the clock signal <NUM> so that the clock frequency Fclk is according to an increasing function of the operating voltage VDD such that the rate of timing events is substantially at the target level when the operating voltage is above the threshold voltage Vth and the rate of timing events exceeds the target level when the operating voltage is below the threshold voltage.

<FIG> illustrates an exemplifying case where the timing events being detected are errors related to the operation of the electronic device <NUM>. Thus, in <FIG>, the rate of the detected timing events is the rate of errors. In <FIG>, the rate of errors as a function of the operating voltage VDD is depicted with a curve <NUM> and the clock frequency Fclk is depicted with a curve <NUM>. On the curve <NUM>, the clock frequency Fclk can be substantially according to the above-presented equation (<NUM>) when the operating voltage VDD is sufficiently greater than the threshold voltage Vth. The curve <NUM> can be approximated for example with a suitable polynomial function of VDD.

As can be seen from <FIG>, the rate of errors depicted with the curve <NUM> is substantially at the target level when the operating voltage VDD is above the threshold voltage Vth and the clock frequency Fclk is according to the curve <NUM>. The rate of errors increases rapidly when the operating voltage VDD is decreased below the threshold voltage Vth and the clock frequency Fclk is according to the curve <NUM>. In <FIG>, a curve <NUM> illustrates how the clock frequency Fclk should be decreased when the operating voltage VDD decreases below the threshold voltage Vth in order to keep the rate of errors at the target level. On the curve <NUM>, the clock frequency Fclk can be substantially according to the above-presented equation (<NUM>) when the operating voltage VDD is not greater than the threshold voltage Vth. A curve <NUM> shown in <FIG> illustrates the average energy consumption per operation of the electronic device <NUM>. As illustrated in <FIG>, the energy consumption of the electronic device <NUM> can be optimized by controlling the operating voltage VDD to be the threshold voltage Vth or slightly above, e.g. <NUM>-<NUM>%, the threshold voltage Vth.

In the exemplifying control system <NUM> illustrated in <FIG>, the controller <NUM> is configured to set, prior to searching for the threshold voltage Vth, the operating voltage VDD to have successively each of fitting voltage values V_ft1, V_ft2, and V_ft3 which are greater than the threshold voltage Vth. The controller <NUM> is configured to control, when the operating voltage has each of the fitting voltage values, the clock signal generator <NUM> to increase the clock frequency when the rate of errors is below the target level and to decrease the clock frequency when the rate of errors exceeds the target level so as to search for fitting frequency values F_ft1, F_ft2, and F_ft3 corresponding to the fitting voltage values V_ft1, V_ft2, and V_ft3 as illustrated in <FIG>. The controller <NUM> is configured to determine, on the basis of the fitting voltage and fitting frequency values, one or more setting parameters related to the control of the clock frequency so as to set the clock frequency to be according to the increasing function of the operating voltage VDD such that the rate of errors is according to the curve <NUM>. The controller <NUM> may comprise for example a digital signal processor "DSP" which is configured, with the aid of the above-mentioned setting parameters, to control the clock signal generator <NUM> so that the clock frequency is changed in the desired way when the operating voltage VDD is changed.

<FIG> shows a flowchart of a method according to an exemplifying and non-limiting embodiment of the invention for controlling operating voltage VDD supplied to an electronic device provided with a timing event detector responsive to timing events related to operation of the electronic device. The method comprises:.

In the method illustrated in <FIG>, the clock frequency Fclk that represents the pulse rate of a clock signal operating the electronic device is according to an increasing function F(VDD) of the operating voltage such that the rate of timing events is substantially at the target level when the operating voltage is above the threshold voltage and the rate of timing events exceeds the target level when the operating voltage is below the threshold voltage.

In a method according to an exemplifying and non-limiting embodiment of the invention, the clock signal is produced with a controllable clock signal generator comprising a voltage-controlled-oscillator responsive to the operating voltage in accordance with the increasing function of the operating voltage.

A method according to an exemplifying and non-limiting embodiment of the invention comprises producing a voltage control signal for controlling a voltage regulator to produce the operating voltage and a frequency control signal for controlling a controllable clock signal generator to produce the clock frequency in accordance with the increasing function of the operating voltage.

A method according to an exemplifying and non-limiting embodiment of the invention comprises:.

In a method according to an exemplifying and non-limiting embodiment of the invention, the increasing function of the operating voltage is a downwards convex increasing function of the operating voltage. For example, the increasing function of the operating voltage can be substantially according to the following equation when the operating voltage VDD is sufficiently greater than the threshold voltage Vth:
<MAT>
where Fclk is the clock frequency, K is a delay-fitting parameter, Cg is the output capacitance of the characteristic inverter related to the transistor technology of the electronic device, Vth is the threshold voltage, and αv is the velocity saturation index that is between <NUM> and <NUM>.

In a method according to an exemplifying and non-limiting embodiment of the invention, the determination of the rate of timing events comprises:.

A computer program according to an exemplifying and non-limiting embodiment of the invention comprises computer executable instructions for controlling a programmable processing system to carry out actions related to a method according to any of the above-described exemplifying embodiments of the invention.

A computer program according to an exemplifying and non-limiting embodiment of the invention comprises software modules for controlling operating voltage supplied to an electronic device provided with a timing event detector responsive to timing events related to operation of the electronic device. The software modules comprise computer executable instructions for controlling a programmable processing system to:.

The above-mentioned software modules can be e.g. subroutines or functions implemented with a suitable programming language and with a compiler suitable for the programming language and the programmable processing system under consideration. It is worth noting that also a source code corresponding to a suitable programming language represents the computer executable software modules because the source code contains the information needed for controlling the programmable processing system to carry out the above-presented actions and compiling changes only the format of the information. Furthermore, it is also possible that the programmable processing system is provided with an interpreter so that a source code implemented with a suitable programming language does not need to be compiled prior to running.

A computer program product according to an exemplifying and non-limiting embodiment of the invention comprises a computer readable medium, e.g. a compact disc "CD", encoded with a computer program according to an embodiment of invention.

A signal according to an exemplifying and non-limiting embodiment of the invention is encoded to carry information defining a computer program according to an embodiment of invention.

The above-described method for controlling the operating voltage was confirmed with a test system that is similar to the electronic system shown in <FIG>. In the test system, the electronic device <NUM> is a <NUM>-bit microprocessor based on the CMOS technology and provided with a timing event detector. The implementation of the controller <NUM> of the test system is shown in <FIG> where "clk sgn" is the clock signal <NUM> and "err sgn" is the timing event signal <NUM>. The operating voltage VDD and correspondingly the clock frequency Fclk were reduced so that the clock frequency was reduced substantially quadractically as a function of the operating voltage until an increase in the rate of timing events, such as e.g. errors, was observed. The point at which the rate of timing events increases is approximately the threshold voltage Vth slightly above which the energy consumption is optimized.

Two tests were carried out. In these tests, the timing events being detected are errors related to the operation of the electronic device. In the first test, the body bias "BB" voltage was lower than in the second test. The measured results of the first test are shown in Table <NUM> below.

In the first test, the threshold voltage Vth is approximately <NUM> V.

The measured results of the second test are shown in Table <NUM> below.

In the second test, the threshold voltage Vth is approximately <NUM> V.

Claim 1:
A control system (<NUM>, <NUM>) for controlling operating voltage supplied to an electronic device provided with a timing event detector responsive to timing events related to operation of the electronic device, the control system comprising:
- a controller (<NUM>, <NUM>) for determining a rate of the timing events as a ratio of a number of pulses of a timing event signal and a number of pulses of a clock signal during a sample period, for decreasing the operating voltage as long as the rate of the timing events is below a target level, and for increasing the operating voltage when the rate of the timing events exceeds the target level so as to search for a threshold voltage being a smallest value of the operating voltage at which the rate of the timing events is substantially at the target level, and
- a controllable clock signal generator (<NUM>, <NUM>) for producing the clock signal for operating the electronic device,
wherein the clock frequency representing a pulse rate of the clock signal is according to an increasing function of the operating voltage such that the rate of the timing events is substantially at the target level when the operating voltage is above the threshold voltage and the clock frequency is according to the increasing function of the operating voltage, and the rate of the timing events exceeds the target level when the operating voltage is below the threshold voltage and the clock frequency is according to the increasing function of the operating voltage.