Patent Description:
Leadless semiconductor die packages have several advantages over packages having leads extending beyond a perimeter of the package. Such semiconductor die packages may have a low profile as compared to other types of semiconductor die packages. Such semiconductor die packages may take up less space and thereby have a smaller "footprint" on a printed circuit board than conventional packages having leads extending beyond the perimeter of the semiconductor die packages. Such leadless semiconductor die packages may also have better thermal performance as compared to packages having leads extending beyond the perimeter of the package.

An issue within the relevant industry as it concerns QFN and DFN packages relates to the inspection of the solder connections to the leads of the packages. In order to ensure proper solder connections to QFN and DFN packages, it is necessary to inspect the connections. These inspections can be performed by x-ray, for example, or by automated optical inspection (AOI). Automated optical inspection (AOI) systems are used to inspect, for example, semiconductor devices and printed circuit boards (PCBs), for defects. QFN and DFN packages can allow for AOI, which is less costly than x-ray inspections, if the leads are oriented in such a manner that the portions of the sides or "flanks" of the leads are wettable by solder, such as by having solder wick up the sides or sidewalls of the exposed leads.

A method of making Flat No-Lead Packages with plated lead surfaces is described in <CIT>. In this method, the packages are mounted on a dicing tape and singulated, after which a conductive plate is applied and cut surface portions of the leads are plated in an electroplating bath.

Conventional lead wettable devices may be formed by a step cutting process which requires multiple surfaces to be plated at the same time with the same platable material. Plating multiple surfaces at the same time may be complicated and may not allow targeted plating for specific surfaces.

There is therefore the need for an efficient method of manufacturing a semiconductor die packages having wettable flanks.

The method for fabricating a semiconductor die package from a package assembly includes a lead frame including at least a first lead and a second lead, the first and second leads each having a top surface and a bottom surface, a first integrated circuit die provided on the top surface of the first lead, a second integrated circuit die provided on the top surface of the second lead, and a mold encapsulation surrounding at least portions of the lead frame and at least portions of the first integrated circuit die and the second integrated circuit die, the mold encapsulation having a top major surface and a bottom major surface. A bottom surface of the first lead and a bottom surface of the second lead are plated with a first electrical plating. A conductive film is applied to connect the bottom surface of the first lead and the bottom surface of the second lead. A cut is made to create a channel through the mold encapsulation, the second lead, and the first electrical plating on the bottom surface of the second lead, the channel exposing a first lead sidewall and a second lead sidewall of the second lead. The first lead sidewall and the second lead sidewall are platted, through the channel, with a second electrical plating and the conductive film is removed.

Certain terminology is used in the following description for convenience only and is not limiting. The words "right," "left," "top," and "bottom" designate directions in the drawings to which reference is made. However, it will be understood that such orientation-based terms are for reference only and that the embodiments may be implemented in different directions such that such terms may be applied as adjusted based on such respective different directions. The words "a" and "one," as used in the claims and in the corresponding portions of the specification, are defined as including one or more of the referenced item unless specifically stated otherwise. This terminology includes the words above specifically mentioned, derivatives thereof, and words of similar import. The phrase "at least one" followed by a list of two or more items, such as "A, B, or C," means any individual one of A, B or C as well as any combination thereof.

The description provided herein is to enable those skilled in the art to make and use the described embodiments set forth.

Techniques are disclosed herein for forming bottom and sidewall wettable flanks on semiconductor die packages, and, preferably, DFN and/or QFN semiconductor die packages. The techniques include a package assembly having multiple non-singulated packages. The package assembly includes a lead frame having dies and other internal package components (e.g., wire bonds) coupled thereto. The dies and other components form different regions of non-singulated packages, as further disclosed herein. The dies and other components are encapsulated within a mold encapsulation (also referred to as a "molding," "mold," "encapsulation," "encapsulation material," "mold encapsulation material", or other similar term herein). The mold encapsulation may be non-conductive and may cover all or most of the package components but may leave exposed certain electrical contact pads (referred to herein as "leads," including a "first lead" and a "second lead") and, possibly, thermal contact pads (referred to herein as "die paddles") as well as other components as disclosed herein. The mold encapsulation may include a top major surface that is opposite to the bottom surface of the plurality of leads and a bottom major surface that is adjacent and substantially parallel to the bottom surface of the plurality of the leads. The lead frame provides a continuous electrical connection between one end of the package assembly and the other, and between the various exposed leads and die paddles of the semiconductor die packages. Elements such as wire bonds or tie bars may assist with forming the electrical connection. This electrical connection may be used for current flow during electroplating (e.g., a first electrical plating), which may be a step that occurs in the process for forming bottom and sidewall wettable flanks on DFN and/or QFN packages.

<FIG> shows a flow diagram of a process <NUM> for forming a semiconductor die packages from a package assembly, according to an aspect of the present invention. The process <NUM> of <FIG> is discussed in conjunction with <FIG>, which illustrate stages of a package assembly <NUM> as the process <NUM> proceeds. A lead frame <NUM>, as referenced herein, may be cut from a lead frame material such as a sheet of copper. A lead frame assembly, as referenced herein, may be the lead frame <NUM> having a plurality of leads <NUM>. As shown in <FIG>, the leads <NUM> may be etched into portions of the lead frame <NUM>.

The package assembly <NUM> is shown with a top surface <NUM> and a bottom surface <NUM>, as indicated in <FIG>. At step <NUM> of the process <NUM>, a plurality of die <NUM> are deposited on and bonded to a corresponding plurality of leads <NUM> of a lead frame <NUM> that are part of the lead frame assembly. The lead frame assembly may include multiple leads <NUM> integrated into a single part or unit. The lead frame assembly may include any metal alloy. A plurality of semiconductor die packages may be formed in an array of die packages in the package assembly <NUM>, which are then cut (e.g., singulated) into individual semiconductor die packages. Each semiconductor die package may include a second portion (e.g., 24b as described in <FIG>) of a lead <NUM> (e.g., 23a) that is attached to a die <NUM>, a first portion (e.g., 25a as described in <FIG>) of a lead <NUM> (e.g., 23b) that is electrically connected to the die <NUM> (e.g., by wire <NUM> or a tie-bar (not shown)), and mold encapsulation <NUM>. A singulated semiconductor die package may be a semiconductor die package that is separated from one or more other semiconductor die packages in the package assembly, as further described herein.

At step <NUM>, one or more of the integrated circuit dies, which are referred to herein as "dies," for simplicity, may be deposited on the leads <NUM> of the lead frame <NUM>. At step <NUM>, other components, such as wires <NUM>, conductive clips (elements within the semiconductor die package that couple the die(s) to one or more leads), or other elements are deposited to form a plurality of semiconductor die packages.

At step <NUM>, a portion of the lead frame <NUM> is taped, and a mold encapsulation <NUM> is deposited around the lead frame <NUM> and other components of the semiconductor die packages. Notably, a bottom portion of the lead frame that faces away from the wire bonds formed by wires <NUM> deposited at step <NUM> may be taped to prevent the mold encapsulation deposited at step <NUM> to extend past the base of the lead frame <NUM> such as through gaps between two or more leads <NUM> in the lead frame <NUM>. The mold encapsulation <NUM> may provide a physical and electrical barrier for the components of the package. The mold encapsulation <NUM> may be a silica-filled resin, a ceramic, a halide-free material, or other protective encapsulation material, or a combination thereof. The mold encapsulation <NUM> may be formed by molding thermosetting materials in a process where a plastic is softened by heat and pressure in a transfer chamber, then forced at high pressure through suitable sprues, runners, and gates into a closed mold for final curing. The mold encapsulant may also be formed by using a liquid which may be heated to form a solid by curing in a UV or ambient atmosphere, or by using a solid that is heated to form a liquid and then cooled to form a solid mold. At step <NUM>, the lead frame <NUM> may be de-taped, after step <NUM>, and one or more markings (not shown) may be applied to the lead frame assembly. The markings may include one or more fiducial marks which are marks detectable by a machine that allow the machine to align itself for cutting. After step <NUM>, a package assembly <NUM> is provided that includes multiple non-singulated semiconductor die packages with package components (e.g., dies, the lead frame, and the components that couple the dies to the lead frame) encapsulated within a molding material <NUM>.

<FIG> shows a top view of a package assembly <NUM> with a top major surface <NUM> of the mold encapsulation <NUM> after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, a plurality of leads <NUM> are provided as part of a lead frame <NUM>. A die <NUM> is deposited on each of the leads <NUM> on a die surface 27a of the leads (e.g., top surface, as shown in <FIG>). As shown in <FIG>, a given die 20a is deposited on a given first lead 23a of the plurality of leads <NUM> and may be electrically connected to an adjacent lead (e.g., second lead 23b), of the plurality of leads. The electrical connections may be implemented using wires <NUM>, such as a given wire 21a, bonded to the given die 20a deposited on a die surface <NUM> of the first lead 23a, the given wire 21a connecting to a die surface 27a of a second lead 23b. Similarly, the plurality of dies <NUM> are deposited on respective leads <NUM> and are electrically connected to adjacent leads <NUM> using wire bonds. Portions of mold encapsulation <NUM> are shown in <FIG>, though it will be understood that the mold encapsulation <NUM> covers the lead frame and associated components, as seen from the cross-sectional view shown in <FIG>. In an embodiment, the mold encapsulation <NUM> may be partially or fully opaque and may be of a given color (e.g., black, grey, etc) such that the lead frame and associated components may not be visible from a top view. However, it will be understood that in the top view, as shown in <FIG>, the mold encapsulation <NUM> is shown as transparent for illustrative purposes, such that the lead frame and associated components are visible in <FIG> Leads 23a and 23b, die 20a, and wire 20a are referenced herein for exemplary purposes; however, one of ordinary skill in the art would understand that the same description generally applies for each of the plurality of leads <NUM>, dies <NUM>, and wires <NUM>.

<FIG> shows a cross-sectional view of the package assembly <NUM> of <FIG>, after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, the plurality of leads <NUM> (e.g., first lead 23a and second lead 23b) are provided as part of a lead frame <NUM>. The plurality of dies <NUM> are deposited onto the leads <NUM> (e.g., 23a and 23b) and a given die 20a is deposited on a first lead (e.g., 23a), of the plurality of leads <NUM>, may be electrically connected to a second lead (e.g., 23b), of the plurality of leads using electrical connections using wires (e.g., wire <NUM>), as disclosed herein. Similarly, a plurality of dies <NUM> (e.g., die 20a) are deposited on respective leads <NUM> (e.g., 23a) and are electrically connected to adjacent leads (e.g., 23b) using wires <NUM>. As shown, mold encapsulation <NUM>, encapsulates the dies <NUM>, plurality of leads <NUM> and may be provided between the space between adjacent leads (e.g., between lead 23a and lead 23b). Further, the mold encapsulation <NUM> also encapsulates other components such as wires <NUM> (e.g., wire 21a).

<FIG> shows a bottom view of the package assembly <NUM> of <FIG>, after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, a plurality of leads <NUM> (e.g., leads 23a and 23b) may be arranged in an array configuration. <FIG> shows the plating surface 27b (e.g., bottom surface) of leads 23a and 23b which may be adjacent to each other in an X direction. As further noted herein, leads <NUM> that are adjacent to each other in a Y direction (e.g., top and bottom in <FIG>) may be independent from each other during the semiconductor package fabrication, as disclosed herein.

At step <NUM> of the process <NUM> of <FIG>, a bottom surface of the plurality of leads <NUM> of the lead frame may be plated with a first electrical plating <NUM>. The plating surface 27b of the plurality of leads <NUM> may be the surface of the plurality of leads <NUM> that is opposite from the surface of the plurality of leads <NUM> that is bonded to the wires <NUM> deposited at step <NUM>. Notably, the plating surface 27b of the plurality of leads <NUM> is the surface of the leads that is not covered by the molding material.

A first electrical plating <NUM> may be applied by an electroplating process, at step <NUM> of the process <NUM> of <FIG>, as shown in <FIG>. The first electrical plating <NUM> may include one or more layers of a metal, such as tin or a tin alloy, plated on the plating surface 27b of the leads <NUM> and may protect the plating surface 27b of the leads <NUM> from oxidation and may also provide a wettable surface for soldering. The electroplating process may include depositing a conductive plating material that covers the plating surface (e.g., bottom surface) of the plurality of leads <NUM> of the lead frame <NUM> and allows for solder to adhere to the leads <NUM>. A first electrical plating <NUM> material may be deposited on the exposed plating surfaces 27b (e.g., exposed bottom surfaces) of the leads <NUM>. During the electroplating process of step <NUM>, the lead frame <NUM> may be dipped in a bath and the lead frame <NUM> may be electrically coupled to the cathode of an electrolytic plating device (not shown). The anode of the electrolytic plating device may be coupled to the plating material, which is also dipped in the bath. An electrical current may be applied to the lead frame which causes the plating material to be deposited on the plating surface 27b (e.g., bottom surface) of the plurality of leads <NUM> so that, for example, the plating surface 27b of leads 23a and 23b are plated with the plating material. At step <NUM>, because only the plating surfaces 27b of the leads 23a and 23b are exposed, only these surfaces are plated by the first electrical plating <NUM>. Notably, sidewalls <NUM> and <NUM>, as further disclosed herein, of the leads 23a and 23b, which are not exposed, are not electrolytically plated. The first electrical plating <NUM> material may be any of a variety of plating materials, such as tin, gold, palladium, or silver.

After step <NUM> of the process <NUM> of <FIG>, one of two processes may be taken, as shown in <FIG>. A first process - not an embodiment of the invention - is described at steps <NUM>, <NUM>, <NUM>, and <NUM> of <FIG> and illustrated in <FIG>, and a second process - in accordance with the invention - is described at steps <NUM>, <NUM>, and <NUM> of <FIG> and illustrated at <FIG>.

Referring to the first process (not an embodiment of the invention), at step <NUM>, top taping and saw singulation are performed as further described herein.

According to an embodiment, step <NUM>, top taping and saw singulation, of the process <NUM> of <FIG> may be taken after applying the first electrical plating <NUM> to the bottom exposed surfaces of the leads <NUM> (e.g., leads 23a and 23b of <FIG>) at step <NUM> of the process <NUM>. At step <NUM>, as shown in <FIG>, a first connecting film <NUM> may be applied to the top major surface 22a of the mold encapsulation <NUM>. As shown, the connecting film <NUM> may be applied over a plurality of the leads <NUM> (e.g., leads 23a and 23b). The connecting film <NUM> may be any applicable film that attaches to the top major surface 22a of the mold encapsulation <NUM>. The connecting film <NUM> may attach to the top major surface of the mold encapsulation <NUM> using any applicable adhesive material.

Step <NUM> of the process <NUM> of <FIG> includes a singulation process. The singulation process at step <NUM> may be implemented using an applicable cutting device and/or technique such as, without limitation, a saw having a saw blade, or a laser cutter, a plasma cutter, or a water jet cutter, or any other acceptable cutting device and/or technique as known to those of skill in the art. The singulation process at step <NUM> may include making one or more cuts through the first electrical plating <NUM> on the plating surface 27b (e.g., bottom surface) of the plurality of leads <NUM> through the top major surface 22a of the mold encapsulation <NUM> to create one or more channels <NUM>. The channels <NUM> may each expose lead sidewalls <NUM> and <NUM> on each side of each of the channels. As shown in <FIG>, the lead frame <NUM> may be singulated into individual semiconductor die packages <NUM>. The singulation process may include making a first series of parallel cuts 51a along a first direction (e.g., an X direction) cutting through the bottom major surface 22b (e.g., opposed major surface) of the mold encapsulation <NUM> opposite of the connecting film <NUM> to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM>. The first series of parallel cuts 51a may also cut through a portion of the lead frame <NUM> that is between adjacent leads <NUM> in the vertical direction (e.g., through lead connectors <NUM>). As applied herein, lead connectors <NUM> may connect two adjacent leads and may be part of a lead frame (e.g., lead frame <NUM>) itself or may be formed from one or more other materials. Notably, this first series of parallel cuts 51a only cut through the area between adjacent leads <NUM> (e.g., leads arranged above or below each other in the Y direction if viewing the package assembly <NUM> from a top view), and do not cut through the leads <NUM>. The singulation process may further include making a second series of parallel cuts 51b along a second direction (e.g., a Y-direction), the second direction substantially perpendicular to the first direction, the second series of parallel cuts cutting through the plating surface 27b (e.g., bottom surface) of each of the plurality of leads <NUM>, and the electrical plating <NUM> of each of the plurality of leads <NUM>, and the mold encapsulation <NUM> to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM> to create a channel <NUM> exposing a first lead sidewall <NUM> and a second lead sidewall <NUM> of each of the plurality of leads <NUM>.

The first and/or second, series of parallel step cuts 51a and 51b, between the semiconductor die packages <NUM> create sidewalls <NUM> and <NUM> where wettable flanks will be formed. The first and second series of parallel cuts 51a and 51b may be made at a depth not fully through the connecting film <NUM> shown in <FIG> and <FIG>, to allow the packages to remain as a single assembly for additional handling in subsequent steps.

<FIG> shows a top view of a package assembly <NUM> at step <NUM> of process <NUM> of <FIG>. As shown in <FIG>, a plurality of cuts <NUM> (e.g., 51a and 51b) may be made during a singulation process. The top view shown in <FIG> is a top view from below connecting film <NUM> (not shown in <FIG>). The plurality of cuts may include a series of parallel cuts 51a in the X direction (e.g., from a left side to a right side of the package assembly <NUM> shown in <FIG>), as well a series of parallel cuts 51b in the Y direction, as indicated by the axis provided in <FIG>. The series of parallel cuts in the X direction 51a may cut through the bottom major surface 22b (e.g., opposed major surface) of the mold encapsulation <NUM> opposite of the connecting film <NUM> (shown in corresponding <FIG>) to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM>. Notably, according to the example shown in <FIG>, the leads <NUM> in the package assembly <NUM> are configured such that adjacent leads (e.g., 23a and 23b) in the X direction are connected by wires <NUM>, and adjacent leads <NUM> in the Y direction may be connected by lead connectors <NUM> or may be independent of each other during fabrication of semiconductor die packages, as disclosed herein. It will be noted that the cuts 51a and 51b are shown in the top view of <FIG> are from below the connecting film <NUM> (not shown in <FIG>) as the cuts <NUM> do not extend through the connecting film <NUM> that is above the mold encapsulation <NUM> shown in <FIG>. The cuts 51b in the Y direction create channels <NUM> (as shown in <FIG>) that cut through each of the plurality of leads <NUM> (e.g., leads 23a and 23b) whereas the cuts 51a in the X direction may not cut through the plurality of leads <NUM> but rather separate adjacent leads in the Y direction from each other by cutting through the mold encapsulation <NUM> and/or lead connectors <NUM>.

<FIG> shows a cross-section view of the package assembly <NUM> of <FIG>, during step <NUM> of the process <NUM> of <FIG>. <FIG> shows a series of parallel cuts 51b made in the Y direction to create a plurality of channels <NUM>. Notably, the series of parallel cuts 51b in the Y direction cut through the first electrical plating <NUM> on the plating surface 27b (e.g., bottom surface) of the plurality of leads <NUM> (e.g., leads 23a and 23b), through the plurality of leads <NUM>, and through the mold encapsulation <NUM>. <FIG> shows the channels <NUM> extending partially into the connecting film <NUM>, though it will be understood that, according to an embodiment, the channels <NUM> may be formed up to, but not through a portion of the connecting film <NUM>. As shown in <FIG>, at least a portion of the connecting film <NUM> is contiguous over the major top surface 22a of the mold encapsulation <NUM> across multiple leads <NUM>. Notably, the connecting film <NUM> may have properties (e.g., strength, rigidity, elasticity, etc.) that enable the connecting film <NUM> to maintain the plurality of semiconductor die packages <NUM> of the package assembly <NUM> that are separated by the channels <NUM>, to remain as part of a single unit connected by the connecting film <NUM>. For example, the connecting film <NUM> may enable the plurality of semiconductor die packages <NUM> of the package assembly <NUM> plus the plurality of channels <NUM> to have a width, in an X direction, that is substantially equal to the width of the package assembly <NUM> before the plurality of cuts at step <NUM> of process <NUM> (e.g., the width of the package assembly <NUM> prior to step <NUM>, as shown in <FIG>).

As shown in <FIG>, the channels <NUM> expose lead sidewalls <NUM> and <NUM> of each of the plurality of leads <NUM> (e.g., leads 23a and 23b). The lead sidewalls <NUM> and <NUM> are created during the formation of the channels <NUM> such that the formation of the channels <NUM> cuts through each of the plurality of leads <NUM> (e.g., leads 23a and 23b) to expose two lead sidewalls <NUM> and <NUM> of each of the plurality of leads <NUM>. The lead sidewalls <NUM> and <NUM> correspond to the portions of the leads that face the respective channels <NUM>. Notably, the channels <NUM> are created between a first portion 24a and second portion 24b of each of the plurality of leads <NUM>. The first portion 24a preferably includes a wire <NUM> (e.g., wire 21a) bonded to the die surface 27a of the first portion 24a of the plurality of leads <NUM> and the second portion 24b preferably includes a die <NUM> (e.g., die 20a). As shown in <FIG>, for example, after the plurality of cuts 51a and 51b, each semiconductor die package <NUM> of the package assembly <NUM> includes a second portion 24b of a first lead 23a, including die 20a, and a first portion 24a of a second lead 23b, including wire 21a bonded to a die surface 27a of the first portion 24a of the second lead 23b.

<FIG> shows a bottom view of the package assembly <NUM> of <FIG>, at step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, the plurality of cuts <NUM> include a series of parallel cuts 51a in the X direction (e.g., from a left side to a right side of the package assembly <NUM> shown in <FIG>), as well a series of parallel cuts 51b in the Y direction (e.g., from a top to a bottom of the package assembly <NUM> shown in <FIG>). The series of parallel cuts in the X direction cut through the bottom major surface 22b (e.g., opposed major surface) of the mold encapsulation <NUM> opposite of the connecting film <NUM> (shown in corresponding <FIG>) to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM>. The cuts 51b in the Y direction create channels <NUM> (as shown in <FIG>) that cut through each of the plurality of leads <NUM> (e.g., leads 23a and 23b) whereas the cuts 51a in the X direction do not cut through the plurality of leads <NUM> but rather separate adjacent leads <NUM> in the Y direction from each other by cutting through the mold encapsulation <NUM> and/or lead connectors <NUM>. As disclosed herein, the first series of parallel cuts 51a may also cut through a portion of the lead frame <NUM> that is between adjacent leads <NUM> in the vertical direction (e.g., if the lead connectors <NUM> are part of the lead frame <NUM>).

At step <NUM> of the process <NUM> of <FIG>, as shown in <FIG>, a conductive film <NUM> is applied to the bottom of the semiconductor die packages <NUM> of the package assembly <NUM> that are separated by channels <NUM>. The conductive film <NUM> may be applied while the connecting film <NUM> of <FIG> and <FIG> is attached to the top major surface 22a of the mold encapsulation <NUM> such that the semiconductor die packages <NUM> of the package assembly <NUM> maintain their position and/or structure while the conductive film <NUM> is applied. The connecting film <NUM> of <FIG> and <FIG> may be removed at step <NUM> of process <NUM> such that the semiconductor die packages <NUM> of the package assembly <NUM> may be connected to each other by the conductive film <NUM>. Notably, the conductive film <NUM> may have properties (e.g., strength, rigidity, elasticity, etc.) that enable the conductive film <NUM> to maintain the plurality semiconductor die packages <NUM> of the package assembly <NUM> that are separated by the channels <NUM>, to remain as part of a single unit connected by the conductive film <NUM>. For example, the conductive film <NUM> may enable the plurality of semiconductor die packages <NUM> of the package assembly <NUM> plus the plurality of channels <NUM> to have a width, in an X direction, that is substantially equal to the width of the package assembly <NUM> before the removal of the connecting film <NUM> at step <NUM> of process <NUM> (e.g., the width of the package assembly <NUM> prior to step <NUM>, as shown in <FIG>). The conductive film <NUM> may be made from any applicable material that conducts electricity such that an electrical path is maintained between segments of the package assembly <NUM> separate by channels <NUM>. For example, the conductive film <NUM> may be made from or may include metal or metal alloys. It will be noted that although conductive film <NUM> is described herein, the conductive film <NUM> may also be a connecting film.

The conductive film <NUM> is preferably applied to a bottom of the semiconductor die packages <NUM> of the package assembly <NUM>, as shown in <FIG>. The conductive film <NUM> is more preferably applied to one or more of the bottom major surface 22b of the mold encapsulation <NUM> and/or the first electrical plating <NUM> on the plating surface 27b (e.g., bottom surface) of the plurality of leads <NUM>.

After applying the conductive film <NUM> to the bottom of the semiconductor die packages <NUM> of the package assembly <NUM> and removing the connecting film <NUM> from the top of the semiconductor die packages <NUM> of the package assembly <NUM> at step <NUM>, the lead sidewalls <NUM> and <NUM> of the plurality of leads <NUM> may be plated at step <NUM> of the process <NUM> of <FIG>. As shown in <FIG> a second electrical plating <NUM> may be applied by an electroplating process, at step <NUM> of the process <NUM> of <FIG>. The second electrical plating <NUM> may be one or more layers of a metal such as tin or a tin alloy that plated on the lead sidewalls and may protect the lead sidewalls from oxidation and may also provide a wettable surface for soldering. The electroplating process at step <NUM> may include depositing a conductive plating material to cover the exposed surface of lead sidewalls <NUM> and <NUM> e.g., through the channels <NUM>). During the electroplating process of step <NUM>, the semiconductor die packages <NUM> of the package assembly <NUM>, connected by the conductive film <NUM>, may be dipped in a bath and may be electrically coupled to the cathode of an electrolytic plating device. The anode of the electrolytic plating device may be coupled to the plating material, which is also dipped in the bath. An electrical current may be applied to the semiconductor die packages <NUM> of the package assembly <NUM>, connected by the conductive film <NUM>, which causes the plating material to be deposited on the exposed surface of the lead sidewalls <NUM> and <NUM> of the plurality of leads so that, for example, the exposed surface of the lead sidewalls of leads 23a and 23b are plated with the plating material (electrical plating <NUM>). At step <NUM>, because only the sidewalls <NUM> and <NUM> of the leads 23a and 23b are exposed, only these surfaces are plated by the second electrical plating <NUM>. Notably, after applying the second electrical plating <NUM> at step <NUM>, at least two surfaces of each portion 24a and 24b of a lead (e.g., a first portion and second portion 24a and 24b of lead 23b) are covered by electrical plating (e.g., first electrical plating <NUM> on a plating surface and second electrical plating on a sidewall surface).

At step <NUM> of the process <NUM> of <FIG>, the conductive film <NUM> is removed, as shown in <FIG>. After removal of the conductive film <NUM> at step <NUM>, a plurality of semiconductor die packages <NUM> corresponding to each of the plurality of package assembly <NUM> segments of <FIG> remain. Each of the plurality of semiconductor die packages <NUM> include a first portion 24a of a lead <NUM> (e.g., lead 23b), a die <NUM> (e.g., die 20a) deposited over a second portion 24b of a lead <NUM> (e.g., lead 23a), a wire <NUM> (e.g., wire 21a) electrically connecting the die <NUM> (e.g., die 20a) to a first portion 24a of the lead <NUM> (e.g., a first portion 24a of lead 23b). Additionally, each of the portions 24a and 24b of leads <NUM> for each of the plurality of semiconductor die packages <NUM> include electrical plating material on the plating surfaces 27b (e.g., bottom surfaces) of the portions of the leads as well as the sidewall surfaces <NUM> and <NUM> of each of the leads <NUM>.

Referring to the second process in accordance with the invention, at step <NUM> bottom taping and saw singulation are performed as an alternative to steps <NUM> and <NUM> of process <NUM> of <FIG>. <FIG> shows an example of step <NUM> which includes applying a conductive film <NUM> to the bottom surface <NUM> of the package assembly <NUM> after step <NUM> of the process <NUM> of <FIG>. To clarify, as shown in <FIG>, step <NUM> follows step <NUM> of the process <NUM> of <FIG> such that step <NUM> is performed after the first electrical plating <NUM> is applied to the plating surface 27b (e.g., bottom surface) of the leads <NUM>. The conductive film <NUM> applied at step <NUM> is attached to both of the bottom major surface 22b of the mold encapsulation <NUM> and the first electrical plating <NUM> on the plating surface 27b (e.g., bottom surface) of the plurality of leads <NUM>.

As shown in <FIG>, step <NUM> includes a singulation process, such as a saw singulation process described in relation to step <NUM> of process <NUM> of <FIG>. <FIG> shows a cross-section view of the package assembly <NUM> and <FIG> shows a top view of the package assembly <NUM> at step <NUM>. The singulation process at step <NUM> may be implemented using an applicable cutting device and/or technique such as a saw having a saw blade, or a laser cutter, a plasma cutter, or a water jet cutter, or any other acceptable cutting device and/or technique as known to those of skill in the art. As further described herein, the singulation process at step <NUM> may include making one or more cuts <NUM> (e.g., 52a and/or 52b) through the top major surface 22a of the mold encapsulation <NUM> through the plurality of leads <NUM> (e.g., leads 23a an 23b) to create one or more channels <NUM>. The channels <NUM> may each include exposed lead sidewalls <NUM> and <NUM> on each side of each of the channels. The package assembly <NUM> may be singulated into individual semiconductor die packages <NUM> connected only by the conductive film <NUM>. The singulation process at step <NUM> may include making a first series of parallel cuts 52a along a first direction (e.g., an X direction) cutting through the top major surface 22a of the mold encapsulation <NUM> opposite of the conductive film <NUM> to a depth down to the conductive film <NUM> or a portion of the conductive film <NUM>. Notably, this first series of parallel cuts 52a only cut through lead connectors <NUM>, as shown in <FIG>, and the area between adjacent electrically unconnected leads (e.g., leads arranged above or below each other if viewing the package assembly <NUM> from a top view, as shown in <FIG>), and do not cut through the leads <NUM>. The first series of parallel cuts 52a may also cut through a portion of the lead frame <NUM>, such as the lead connectors <NUM>, that is between adjacent leads <NUM> in the vertical direction. The singulation process may further include making a second series of parallel cuts 52b along a second direction (e.g., a Y direction), the second direction substantially perpendicular to the first direction, the second series of parallel cuts 52b cutting through the top major surface 22a of the mold encapsulation <NUM> surface, down through plurality of leads <NUM>, and through the first electrical plating <NUM> of each of the plurality of leads to a depth up to the conductive film <NUM> or a portion of the conductive film <NUM> to create channels <NUM> exposing a first lead sidewall <NUM> and a second lead sidewall <NUM> of each of the plurality of leads <NUM>. It will be noted that although conductive film <NUM> is described herein, the conductive film <NUM> may also be a connecting film.

The first and/or second series of parallel step cuts 52a and/or 52b between the semiconductor die packages <NUM> that form the channels <NUM> result in exposed sidewalls that will form wettable flanks. The first and second series of parallel cuts 52a and 52b may be made at a depth that does not extend fully through the conductive film <NUM>, to allow the semiconductor die packages <NUM> to remain as a single assembly for additional handling in subsequent steps. Notably, the conductive film <NUM> may have properties (e.g., strength, rigidity, elasticity, etc.) that enable the conductive film <NUM> to maintain the plurality of semiconductor die packages <NUM> of the package assembly <NUM>, that are separated by the channels <NUM>, to remain as part of a single unit connected by the conductive film <NUM>. For example, the conductive film <NUM> may enable the semiconductor die packages <NUM> of the package assembly <NUM> plus the plurality of channels <NUM> to have a width, in an X direction, that is substantially equal to the width of the package assembly <NUM> before the singulation at step <NUM> (e.g., the width of the package assembly <NUM> prior to step <NUM>, as shown in <FIG>). The conductive film <NUM> may be made from any applicable material that conducts electricity such that an electrical path is maintained between segments of the package assembly <NUM> separated by channels <NUM>. For example, the conductive film <NUM> may be made from or may include metal or metal alloys.

As described herein, steps <NUM> and <NUM> may be performed after the application of conductive film <NUM> and the plurality of cuts 52a and/or 52b to create channels <NUM> of step <NUM>. Notably the lead sidewalls <NUM> and <NUM> of the plurality of leads <NUM> (e.g., the surfaces facing channels <NUM>) may be plated at step <NUM> of the process <NUM> of <FIG>. As shown in <FIG> a second electrical plating <NUM> may be applied by an electroplating process, at step <NUM> of the process <NUM> of <FIG>. The second electrical plating <NUM> may be one or more layers of a metal such as tin or a tin alloy that is plated on the lead sidewalls <NUM> and <NUM> and may protect the lead sidewalls <NUM> and <NUM> from oxidation and may also provide a wettable surface for soldering. The electroplating process at step <NUM> may include depositing a conductive plating material (not shown) to cover the exposed surface of lead sidewalls (e.g., through the channels <NUM>). During the electroplating process of step <NUM>, the semiconductor die package <NUM> of the package assembly <NUM>, connected by the conductive film <NUM>, may be dipped in a bath and may be electrically coupled to the cathode of an electrolytic plating device (not shown). The anode of the electrolytic plating device may be coupled to the plating material, which is also dipped in the bath. An electrical current may be applied to the lead frame <NUM> of the package assembly <NUM>, connected by the conductive film <NUM>, which causes the plating material to be deposited on the exposed surfaces of the lead sidewalls <NUM> and <NUM> of the plurality of leads so that, for example, the exposed surface of the lead sidewalls <NUM> and <NUM> leads <NUM> are plated with the plating material (i.e., resulting in electrical plating <NUM>). At step <NUM>, because only the surfaces of the lead sidewalls <NUM> and <NUM> are exposed, only these surfaces are plated by the second electrical plating <NUM>. Notably, after applying the second electrical plating <NUM> at step <NUM>, at least two surfaces of each portion 24a and 24b of a lead <NUM> (e.g., a first portion 24a and second portion 24b of lead 23b) are covered by electrical plating (e.g., first electrical plating <NUM> on a plating surface 27b (e.g., bottom surface) and second electrical plating <NUM> on a lead sidewalls <NUM>, <NUM>).

At step <NUM> of the process <NUM> of <FIG>, the conductive film <NUM> is removed, as shown in <FIG>. As shown, after removal of the conductive film <NUM> at step <NUM>, only the plurality of semiconductor die packages <NUM>, of package assembly <NUM> of <FIG>, remain. Each of the plurality of semiconductor die packages <NUM> include a first portion 24a of a lead <NUM> (e.g., a second portion of lead 23b shown in the middle semiconductor die package <NUM> of <FIG>), a die <NUM> (e.g., die 20a) bonded to a second portion 24b of the lead 23a, a wire <NUM> (e.g., wire 21a) electrically connecting the die <NUM> (e.g., die 20a) to the first portion 24a of a lead <NUM> (e.g., a first portion 24a of lead 23b). Additionally, each of the portions of leads <NUM> for each of the plurality of semiconductor die packages <NUM> include electrical plating material on the plating surfaces 27b (e.g., electrical plating material <NUM>) of the portions of the leads <NUM> as well as the lead sidewalls <NUM> and <NUM> (e.g., electrical plating material <NUM>) of each of the leads <NUM>. The electrical plating material (e.g., <NUM> and/or <NUM>) may serve to mount a given semiconductor die package to a printed circuit board (PCB).

Although a specific number and configuration of leads (e.g., leads 23a and 23b) is shown and/or described herein, the techniques of the present disclosure are applicable to assembly packages having any configuration of leads and/or dies. Additionally, it is understood by one in the art that the same or similar techniques may be applied to provide QFN packages with wettable flanks as DFN packages with wettable flanks.

<FIG> show a DFN package with wettable flanks <NUM> with a first electrical plating material <NUM> on the bottom of two corresponding leads (not shown) as well as a second electrical plating <NUM> on the lead sidewalls (not shown) of the DFN package <NUM>. The first plating material <NUM> and the second plating material <NUM> may be plated in accordance with the process <NUM> of <FIG>, as disclosed herein. Additionally, as shown in <FIG> a tie bar area <NUM> may also be plated (e.g., with second electrical plating <NUM>). The tie bar area <NUM> may assist with, as disclosed herein, forming an electrical connection for current flow during electroplating (e.g., during the first electrical plating <NUM> and/or second electrical plating <NUM> such as, for example, in the absence of a conductive film <NUM>).

<FIG> show a QFN package <NUM> with a first electrical plating material <NUM> on the bottom of corresponding leads (not shown) as well as a second electrical plating <NUM> on the lead sidewalls (not shown) of the QFN package <NUM>. The first plating material <NUM> and the second plating material <NUM> may be plated in accordance with the process <NUM> of <FIG>, as disclosed herein.

Claim 1:
A method for fabricating a semiconductor package (<NUM>) from a package assembly (<NUM>) comprising:
providing a lead frame (<NUM>) comprising at least a first lead (23a) and a second lead (23b), the first and second leads (23a, 23b) each having a top surface (27a) and a bottom surface (27b), a first integrated circuit die (<NUM>) on the top surface (27a) of the first lead (23a), and a second integrated circuit die (<NUM>) on the top surface (27a) of the second lead (23b);
encapsulating at least portions of the lead frame (<NUM>) and at least portions of the first integrated circuit die (<NUM>) and the second integrated circuit die (<NUM>) in a mold encapsulation (<NUM>), the mold encapsulation having a top major surface (22a) and a bottom major surface (22b);
plating the bottom surface (27b) of the first lead (23a) and the bottom surface (27b) of the second lead (23b) with a first electrical plating (<NUM>);
applying a conductive film (<NUM>) to connect the bottom surface (27b) of the first lead (23a) and the bottom surface (27b) of the second lead (23b);
cutting through the mold encapsulation (<NUM>), the second lead (23b), and the first electrical plating (<NUM>) on the bottom surface (27b) of the second lead (23b) to create a channel (<NUM>), the channel (<NUM>) exposing a first lead sidewall (<NUM>) and a second lead sidewall (<NUM>) of the second lead (23b);
plating, through the channel (<NUM>), the first lead sidewall (<NUM>) and the second lead sidewall (<NUM>) with a second electrical plating (<NUM>); and
removing the conductive film (<NUM>),
characterized in that
the cutting is carried out while the conductive film (<NUM>) is connected to the bottom surface (27b) of the first and second leads (23a, 23b).