Patent Description:
Universal Serial Bus (USB) devices that communicate with a host over USB include USB printers, scanners, digital cameras, storage devices, card readers, and the like. USB based systems may require that a USB host controller be present in the host system , and that the operating system (OS) of the host system support USB and USB Mass Storage Class Devices. USB2 devices may communicate over the USB bus at low speed (LS), full speed (FS), or high speed (HS). A connection between a USB device and a host may be established via a four wire interface that includes a power line, a ground line, and a pair of data line, differential voltage plus (D+) and differential voltage minus (D-), or for the case of USB On-The-Go (OTG), a fifth line named ID (identification pin) may be added. When a USB device connects to the host, the USB device may first pull a D+ line high (or the D-line if the device is a low speed device) using a pull up resistor on the D+ line when connecting as FS (Full Speed) mode. The host may respond by resetting the USB device. If the USB device is a high-speed USB device, the USB device may "chirp" by driving the D- line high during the reset. The host may respond to the "chirp" by alternately driving the D+ and D- lines high. The USB device may then electronically remove the pull up resistor and continue communicating at high speed if both communicating devices are HS capable. Disconnection at high-speed happens when a cable is removed and HS RX terminal on USB device is removed. It results in doubling HS amplitude on the USB host transmitter. The USB2 specification defines a mechanism to detect differential line voltage using differential difference receiver detectors.

The success of USB2. <NUM> technology has enjoyed wide adoption in almost every computing device, with tremendous ecosystem support not only in terms of device choice to support various platform features, but also in terms of technology development with well-established hardware IP portfolios and standardized software infrastructure. It is foreseeable that the great asset of USB2. <NUM> technology will continue to benefit the ecosystem for years to come. As power efficiency becomes increasingly critical in today's computing devices, there is a need for IO technology to be optimized for both active and idle power. <NUM> technology, originally optimized for external device interconnect, is primed to be enhanced for inter-chip interconnect such that the link power can be further optimized. Meantime, silicon technology continues to scale. Device dimensions are getting smaller and therefore more devices can be packed onto a single integrated chip. However, the device reliability challenge arising from the densely packed transistors has become more profound.

At system level, eUSB2 to USB2. <NUM> bridge (eUSB2 repeater) is required to support host communication to external USB2. <NUM> compliant devices via USB connectors. eUSB2 typically works at <NUM>. However, typically, a system on chip (SoC) includes <NUM>. 8V and <NUM>. 3V power sources. A DC-to-DC converter may be used to convert <NUM>. 8V to <NUM>. However, this converter is not power and/or area efficient, takes more space on the chip and generates noise. Other solutions using low dropout (LDO) regulators are available but these solutions do not provide the regulated output voltage variations within a predefined range and are not fast enough to track the output load quickly and making it fast has power penalty. A large capacitor at output node of the LDO will help for the fast changing load, but it brings silicon area penalty or need a dedicated pin and an external capacitor which makes it an expensive solution. <CIT> describes a voltage regulator for suppressing overshoot and undershoot and devices including the same. <CIT> describes a low dropout regulating device and operating method thereof.

In a first aspect, there is defined a circuit for converting a first voltage to a second voltage in a system according to claim <NUM>.

In some examples, the constant reference voltage is generated by a bandgap reference voltage generator and the value of the constant reference voltage is equal to the second voltage. The first one shot pulse and the second one shot pulse have configurable widths that may be the same or different from each other. The first one shot pulse may be generated by a one shot pulse generator by inputting the input signal to the one shot pulse generator and the second one shot pulse may be generated by a one shot pulse generator by inputting an inverse of the input signal to the one shot pulse generator. In some examples, the circuit may be included in a low dropout regulator included in a USB circuit such as a USB driver, USB repeater or other USB circuit. In some examples, the USB circuit may be included in a system on chip ( SoC).

In another aspect , a method for converting a first voltage to a second voltage in a system is disclosed according to claim <NUM>.

It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended Figs. could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the Figs. , is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

The described embodiments are to be considered in all respects only as illustrative and not restrictive.

Traditional low dropout (LDO) regulators are simple to design and provide good regulated output, but are area consuming and usually need off-chip capacitors which increase the overall component count and need a dedicated pin. Capless LDO regulators are attractive due to their small area footprints and they don't require an off-chip capacitor. The embodiments described herein provide a capless LDO regulator which is suitable for a variable load of IMAX/IMIN (e.g., 10mA/0mA). The capless LDO regulator uses simple one-shot circuit with pull-up/pull-down switches to partially adjust output voltage variation during IMAX/IMIN transition. Typical LDO regulator generally use a feedback loop to sense the output voltage and are configured to adjust the output voltage through the feedback loop. However, the embodiments of a capless LDO regulator described herein do not use a feedback loop to adjust the output voltage. The capless LDO regulator uses a one-shot circuit for (that uses positive and negative edges of to be transmitted input signal ) a quick adjustment of the output voltage when load changes by switching a pass transistor. It should be noted that even though the capless LDO regulator is described herein in the context of a eUSB2/USB2 repeater, the introduced capless LDO regulator may be used in other applications that requires a voltage conversion from a first voltage to a second voltage with a fast tracking of load changes.

<FIG> shows a block diagram of a bidirectional eUSB2/USB2 repeater <NUM> including a low dropout (LDO) regulator <NUM>. The eUSB2/USB2 repeater <NUM> may be housed in a system on chip (SOC). In one example, the SoC provides two voltage sources VDD1 and VDD2. VDD1 may be <NUM>. 8V and VDD2 may be <NUM>. USB2 typically works on <NUM>. 3V and eUSB2 operates on <NUM>. If the SoC does not provide a <NUM>. 2V source, <NUM>. 2V needs to be generated for eUSB2. For efficiency reasons, <NUM>. 2V is generated from <NUM>. 8V source than <NUM>.

The eUSB2/USB2 repeater <NUM> includes a eUSB2 port that outputs eD+/eD- signals and a USB2 port that outputs D+/D- signals. A logic block is coupled between the eUSB2 port and the USB2 port. The operations of these two ports and the switch are known to a person skilled in the art. A capless LDO <NUM> is included to convert VDD1 to a voltage different from VDD1. In this example, the capless LDO <NUM> may convert <NUM>. 8V to <NUM>. However, the capless LDO may also be used for converting other voltage values if needed. The capless LDO <NUM> provides advantages over a typical solution because the capless LDO does not require an additional external capacitor or large internal capacitor and the capless LDO provides a fast tracking of load changes so that the output signal's rise and fall time improves. The capless LDO <NUM> also removes a need for a <NUM>. 2V input port or pin.

<FIG> illustrates the internal circuit of the LDO regulator <NUM>. The LDO regulator <NUM> includes an error amplifier <NUM> that receives a reference voltage Vref. Vref may be generated using a bandgap voltage reference circuit (not shown). A bandgap voltage reference is an on-chip reference with minimum variation. It produces a fixed (constant) voltage regardless of power supply variations, temperature changes, or circuit loading from a device ( with some acceptable variation depending on the system requirement and design). Vref should be the same or substantially same to the required output voltage. For example, if the capless LDO regulator <NUM> is configured to convert <NUM>. 8V to <NUM>. 2V, Vref should be <NUM>. The capless LDO regulator <NUM> is configured to keep the output voltage equal to Vref. The load <NUM> may be a component external to the capless LDO regulator <NUM>. The load has an impedance ZL that may include CL and RL. In the example of <FIG>, the load <NUM> may be the eUSB2 port.

The capless LDO regulator <NUM> includes a pass transistor M that allows the current IL from a power source VDD to pass through it when it is conducting. The capless LDO regulator <NUM> converts VDD to VLDO. A (fairly small) capacitor CLDO coupled with the first terminal of the pass transistor M is included. The second terminal of the pass transistor M is coupled with the voltage source VDD. The other end of the capacitor CLDO is coupled with ground. VLDO represents the voltage at the first terminal of the pass transistor M. The rising and falling edges of VLDO should be rise and fall fast as close to the ideal square wave signal as possible. When SWL is enabled, the rising edge of the signal SL, the load ZLDO (e.g., the impedance of the capacitor CLDO in parallel with ZL= CL || RL) sinks current from pass transistor of the LDO, but since ZL is small at the beginning (due to CL) , VLDO drops and VG drops too. It takes some time for the OTA to adjust VG since it doesn't have enough juice to charge the effective cap at the gate of the pass transistor M.

The capless LDO regulator <NUM> includes a switch Swu coupled with a resistor Ru at the output of the error amplifier <NUM>. The switch Swu is controlled by a signal Su. The signal Su may be generated using a one shot circuit <NUM> shown in <FIG>. The one shot signal is generated from the input signal SL (the signal being transmitted) at the rising edge of the input signal. A one shot circuit is well known in the art, hence a detailed discussion is being omitted. A switch SWD is included and is coupled with a resistor RD. The switch SWD is driven by a signal SD. The signal SD is a one shot signal that is generated at the falling edge of the input signal, that is the inverse of the input signal may be inputted to the one shot circuit <NUM> to generate the signal SD. The resistor RD is coupled with the output of the error amplifier <NUM>. The output of the error amplifier <NUM> provides the voltage VG to drive the gate of the pass transistor M. A switch SWL is included at the output of the capless LDO <NUM>. The switch SWL is driven by the input signal SL. In one example, the switch Swu may be of type N or NMOS and the switch SWD may be of type P or PMOS. The switch Swu needs to be of different type (e.g., NMOS or PMOS) than the switch SWD.

The one shot signals Su and SD turns on the switches Swu and SWD at rising and falling edges respectively to lift VG that would otherwise fall during the rising and falling edges. This boost in VG at the rising and falling edges results in faster rising and falling edges of the output voltage Vo. The switches Swu and SWD turns on only for the duration of the one shot pulse (which may be adjusted to adjust rising and falling edges slopes), the current path including the switches Swu and SWD remains disconnected during the input signal pulse width other than for a period equal to the width of the one shot pulse at the rising and falling edges. Hence, the introduction of the current path including the switches Swu and SWD does not cause any significantly additional consumption of power.

The value of the resistor Ru can be as close to <NUM> as possible to prevent the resistor RU from limiting the current flow significantly to prevent connecting VG to VDD. The value of Ru may be calculated based on specific application requirement to achieve a desired output voltage characteristics (e.g., optimized rising and falling edges). In some examples, the value of Ru may be programmable or trimmable so that the value of Ru may be set or changed at run time. Similarly, to enable the error amplifier <NUM> to provide fast tracking of the input signal, the width of the one shot pulse may be programmable to allow an optimization of the output voltage characteristics at run time. At the falling edge of signal SL, the switch SWL will be shut down, then already flowing IL will see an impedance increase (CLDO || ZL < CLDO, ZL is the impedance of the load <NUM>) that causes VG and VLDO to spike for a short period of time. Practically, the error amplifier <NUM> is not fast enough to adjust VG. The SD signal that is generated by negative edge of the input signal SL, by the one-shot circuit <NUM> enables the switch SWD for the duration of the one shot pulse and pulls VG down to cause VLDO to drop until the error amplifier <NUM> reacts to the falling edge of the input signal SL. The resistor RD may be high enough to prevent connecting VG to ground during the falling edge. The use of one shot pulse to boost and pulldown VG during rising and falling edges respectively provides a significantly stable Vo between load changes.

<FIG> shows the voltage-time waveforms <NUM> and output characteristics of the capless LDO regulator <NUM>. As shown, at the rising edge of the input signal SL, a one shot pulse signal Su is generated using a one shot circuit which may be the one shot circuit <NUM> or any other type of known one shot pulse circuit. The one shot pulse has a configurable or programmable duration Twup. The switch Swu remains on during the duration Twup and that causes a boost in VG during the duration Twup. The boost in VG pulls up VLDO faster than it could rise without the one shot pulse. The faster pull up of VLDO causes the output voltage Vo also rises faster (e.g., the curve <NUM>) than it would have been without the signal Su (e.g., the curve <NUM>). At the falling edge, the one shot pulse (e.g., the signal SD) is generated at the falling edge of the input signal SL. The falling edge one shot pulse has the configurable or programmable width Twdn. As explained above, the falling edge one shot pulse causes a faster pull down of the capacitor CLDO and as shown, thus causing the spike in VLDO to be smaller compared to the spike without the falling edge one shot pulse.

<FIG> illustrates an example implementation of the internal circuit of the capless LDO regulator <NUM>. The capless LDO regulator <NUM> includes an error amplifier <NUM> and coupled with a load <NUM>. The capless LDO regulator <NUM> functions the same manner as the capless LDO regulator <NUM>. In one example, the switch Swu may be implemented using a PMOS transistor MP and the switch SWD may be implemented using a NMOS switch MN. And the switch SWL may be implemented using a transmitter driver <NUM> including at least two transistors of different types (e.g., NMOS and PMOS). The gates of the transistors of the transistor pairs are driven by the input signal SL (or an inverse of the input signal SL depending on the configuration of the differential transistor pair or the TX driver <NUM>).

A circuit for converting a first voltage to a second voltage in a system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

Claim 1:
A circuit (<NUM>) for converting a first voltage to a second voltage in a system, the circuit comprising:
a pass transistor (M) including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage (VDD) ;
an error amplifier (<NUM>) including a first input that is coupled with a constant reference voltage (Vref) and a second input that is coupled with a first switch (SWL) that is coupled with an output port (Vo) ;
a second switch (Swu) coupled between the first voltage and an output of the error amplifier (<NUM>), wherein the output of the error amplifier is coupled with the gate of the pass transistor (M);
a third switch (SWD)coupled between ground and the output of the error amplifier (<NUM>);
wherein the second switch (Swu) is configured to be driven by a first one shot pulse (Su) generated from an input signal (S) of the system and the third switch (SWD) is configured to be driven by a second one shot pulse (Su) generated from the input signal; and
the first one shot pulse is generated at a rising edge of the input signal (S), the second one shot pulse is generated at a falling edge of the input signal (S), and the first switch (SWL) is driven by the input signal (S) and is configured to connect or disconnect a load from the output port.