Patent Description:
The present disclosure relates generally to high-speed data communication interfaces, and more particularly, to clock generation in a receiver coupled to a multi-wire, multi-phase data communication link.

Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while an imaging device or camera may be obtained from a second manufacturer, and a display may be obtained from a third manufacturer. The application processor, the imaging device, the display controller, or other types of device may be interconnected using a standards-based or proprietary physical interface. In one example, an imaging device may be connected using the Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, a display may include an interface that conforms to the Display Serial Interface (DSI) standard specified by the Mobile Industry Processor Interface (MIPI) Alliance.

The C-PHY interface is a multiphase three-wire interface defined by the MIPI Alliance that uses a trio of conductors to transmit information between devices. Each wire in the trio may be in one of three signaling states during transmission of a symbol. Clock information is encoded in the sequence of transmitted symbols and a receiver generates a clock signal from transitions between consecutive symbols. The ability of a clock and data recovery (CDR) circuit to recover clock information may be limited by the maximum time variation related to transitions of signals transmitted on the different wires of the communication link. The CDR circuit in a C-PHY receiver may employ a feedback loop to control circuits that generate pulses in a receive clock signal. The feedback loop may be used to ensure that pulse generating circuits do not generate additional pulses triggered by transients that can occur before the conductors in the trio have assumed a stable signaling state before providing a sampling edge. Maximum symbol transmission rate may be limited by the feedback loop, and there is an ongoing need for optimized clock generation circuits that can function reliably at ever-higher signaling frequencies.

<CIT> discloses methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a <NUM>-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.

Embodiments disclosed herein provide systems, methods and apparatus that enable improved communication on a multi-wire and/or multiphase communication link. The communication link may be deployed in apparatus such as a mobile terminal having multiple Integrated Circuit (IC) devices.

In various aspects of the disclosure, a clock recovery apparatus has a plurality of pulse generating circuits, a first logic circuit and a delay flipflop. Each pulse generating circuit is configured to generate a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus. The first logic circuit is configured to provide a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses received from the plurality of pulse generating circuits. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

In certain aspects, each pulse generating circuit includes a delay circuit configured to provide a delayed difference signal by delaying one of three difference signals, and a second logic circuit configured to provide the transition pulse by performing an exclusive OR function on the one of three difference signals and the delayed difference signal. The delay circuit may be configured to provide a delay that exceeds a duration of a skew between two of the three difference signals. The delay circuit may be configurable to provide a delay that accommodates variations in manufacturing process, circuit supply voltage, and die temperature conditions. The transition pulse may have a configurable duration. The delay flipflop may receive an inverse of the clock signal as its input. A rising edge in the clock signal may be used to capture a first symbol from the three-wire bus and a rising edge in the inverse of the clock signal is used to capture a second symbol from the three-wire bus. A falling edge in the clock signal may be used to capture a first symbol from the three-wire bus and a falling edge in the inverse of the clock signal is used to capture a second symbol from the three-wire bus. A rising edge in the clock signal may be used to capture a first symbol from the three-wire bus and a falling edge in the clock signal is used to capture a second symbol from the three-wire bus.

In various aspects of the disclosure, a clock recovery method includes generating a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus, providing a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses generated at the each boundary between the pairs of sequentially-transmitted symbols, and clocking a delay flipflop with the combination signal such that signaling state of a clock signal is changed in response to each pulse in the combination signal. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus.

In various aspects of the disclosure, a processor-readable storage medium has one or more instructions which, when executed by at least one processor of a processing circuit in a receiver, cause the at least one processor to generate a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus, provide a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses generated at the each boundary between the pairs of sequentially-transmitted symbols, and clock a delay flipflop with the combination signal such that signaling state of a clock signal is changed in response to each pulse in the combination signal. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus.

In various aspects of the disclosure, a clock recovery apparatus includes means for generating a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus, means for providing a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses received from the means for generating the transition pulse, and means for providing a clock signal that is output by the clock recovery apparatus. The means for providing a clock signal includes a delay flipflop configured to respond to each pulse in the combination signal by changing signaling state of the clock signal. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus.

As used in this application, the terms "component," "module," "system" and the like are intended to include a computer-related entity, such as, but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal.

Certain aspects of the invention may be applicable to a C-PHY interface specified by the MIPI Alliance, which may be deployed to connect electronic devices that are subcomponents of a mobile apparatus such as a telephone, a mobile computing device, an appliance, automobile electronics, avionics systems, etc. Examples of a mobile apparatus include a mobile computing device, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, avionics systems, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similarly functioning device.

The C-PHY interface is a high-speed serial interface that can provide high throughput over bandwidth-limited channels. The C-PHY interface may be deployed to connect application processors to peripherals, including displays and cameras. The C-PHY interface encodes data into symbols that are transmitted over a set of three wires, which may be referred to as a trio, or trio of wires. For each symbol transmission interval, a three-phase signal is transmitted in different phases on the wires of the trio, where the phase of the three-phase signal on each wire is defined by a symbol transmitted in the symbol transmission interval. Each trio provides a lane on a communication link. A symbol transmission interval may be defined as the interval of time in which a single symbol controls the signaling state of a trio. In each symbol transmission interval, one wire of the trio is undriven, while the remaining two wires are differentially driven such that one of the two differentially driven wires assumes a first voltage level and the other differentially driven wire assumes to a second voltage level different from the first voltage level. The undriven wire may float, be driven, and/or be terminated such that it assumes a third voltage level that is at or near the mid-level voltage between the first and second voltage levels. In one example, the driven voltage levels may be +V and -V with the undriven voltage being <NUM> V. In another example, the driven voltage levels may be +V and <NUM> V with the undriven voltage being + ½V. Different symbols are transmitted in each consecutively transmitted pair of symbols, and different pairs of wires may be differentially driven in different symbol intervals.

Certain aspects disclosed herein provide a clock recovery circuit in a C-PHY receiver circuit using an open-loop half-rate clock recovery circuit to enable symbol capture and decoding at next-generation C-PHY clock rates. In one example, a clock recovery method includes generating a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus, providing a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses generated at the each boundary between the pairs of sequentially-transmitted symbols, and clocking a delay flipflop with the combination signal such that signaling state of a clock signal is changed in response to each pulse in the combination signal. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus.

<FIG> depicts an example of apparatus <NUM> that may be adapted in accordance with certain aspects disclosed herein. The apparatus <NUM> may employ C-PHY <NUM>-phase protocols to implement one or more communication links. The apparatus <NUM> may include a processing circuit <NUM> having multiple circuits or devices <NUM>, <NUM> and/or <NUM>, which may be implemented in one or more ASICs or in an SoC. In one example, the apparatus <NUM> may be a communication device and the processing circuit <NUM> may include a processor <NUM> provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits or functions. The processing circuit <NUM> may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or other processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM>, the processor-readable storage <NUM> may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> and/or an integrated or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may provide one or more buses 118a, 118b, <NUM> that enable certain devices <NUM>, <NUM>, and/or <NUM> to communicate. In one example, the ASIC <NUM> may include a bus interface circuit <NUM> that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes a plurality of IC devices <NUM> and <NUM>, which can exchange data and control information through a communication link <NUM>. The communication link <NUM> may be used to connect a pair of IC devices <NUM> and <NUM> that are located in close proximity to one another, or that are physically located in different parts of the apparatus <NUM>. In one example, the communication link <NUM> may be provided on a chip carrier, substrate or circuit board that carries the IC devices <NUM> and <NUM>. In another example, a first IC device <NUM> may be located in a keypad section of a flip-phone while a second IC device <NUM> may be located in a display section of the flip-phone. In another example, a portion of the communication link <NUM> may include a cable or optical connection.

The communication link <NUM> may include multiple channels <NUM>, <NUM> and <NUM>. One or more channel <NUM> may be bidirectional, and may operate in half-duplex and/or full-duplex modes. One or more channel <NUM> and <NUM> may be unidirectional. The communication link <NUM> may be asymmetrical, providing higher bandwidth in one direction. In one example described herein, a first channel <NUM> may be referred to as a forward channel <NUM> while a second channel <NUM> may be referred to as a reverse channel <NUM>. The first IC device <NUM> may be designated as a host system or transmitter, while the second IC device <NUM> may be designated as a client system or receiver, even if both IC devices <NUM> and <NUM> are configured to transmit and receive on the channel <NUM>. In one example, the forward channel <NUM> may operate at a higher data rate when communicating data from a first IC device <NUM> to a second IC device <NUM>, while the reverse channel <NUM> may operate at a lower data rate when communicating data from the second IC device <NUM> to the first IC device <NUM>.

The IC devices <NUM> and <NUM> may each include a processor <NUM>, <NUM>, controller or other processing and/or computing circuit or device. In one example, the first IC device <NUM> may perform core functions of the apparatus <NUM>, including establishing and maintaining wireless communication through a wireless transceiver <NUM> and an antenna <NUM>, while the second IC device <NUM> may support a user interface that manages or operates a display controller <NUM>, and may control operations of a camera or video input device using a camera controller <NUM>. Other features supported by one or more of the IC devices <NUM> and <NUM> may include a keyboard, a voice-recognition component, and other input or output devices. The display controller <NUM> may include circuits and software drivers that support displays such as a liquid crystal display (LCD) panel, touch-screen display, indicators and so on. The storage media <NUM> and <NUM> may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by respective processors <NUM> and <NUM>, and/or other components of the IC devices <NUM> and <NUM>. Communication between each processor <NUM>, <NUM> and its corresponding storage media <NUM> and <NUM> and other modules and circuits may be facilitated by one or more internal buses <NUM> and <NUM> and/or a channel <NUM>, <NUM> and/or <NUM> of the communication link <NUM>.

The reverse channel <NUM> may be operated in the same manner as the forward channel <NUM>, and the forward channel <NUM>, and the reverse channel <NUM> may be capable of transmitting at comparable speeds or at different speeds, where speed may be expressed as data transfer rate, symbol transmission rate and/or clocking rates. The forward and reverse data rates may be substantially the same or may differ by orders of magnitude, depending on the application. In some applications, a single bidirectional channel <NUM> may support communication between the first IC device <NUM> and the second IC device <NUM>. The forward channel <NUM> and/or the reverse channel <NUM> may be configurable to operate in a bidirectional mode when, for example, the forward and reverse channels <NUM> and <NUM> share the same physical connections and operate in a half-duplex manner. In one example, the communication link <NUM> may be operated to communicate control, command and other information between the first IC device <NUM> and the second IC device <NUM> in accordance with an industry or other standard.

The communication link <NUM> of <FIG> may be implemented according to MIPI Alliance specifications for C-PHY and may provide a wired bus that includes a plurality of signal wires (denoted as M wires). The M wires may be configured to carry N-phase encoded data in a high-speed digital interface, such as a mobile display digital interface (MDDI). The M wires may facilitate N-phase polarity encoding on one or more of the channels <NUM>, <NUM> and <NUM>. The physical layer drivers <NUM> and <NUM> may be configured or adapted to generate N-phase polarity encoded data for transmission on the communication link <NUM>. The use of N-phase polarity encoding provides high speed data transfer and may consume half or less of the power of other interfaces because fewer drivers are active in N-phase polarity encoded data links.

The physical layer drivers <NUM> and <NUM> can typically encode multiple bits per transition on the communication link <NUM> when configured for N-phase polarity encoding. In one example, a combination of <NUM>-phase encoding and polarity encoding may be used to support a wide video graphics array (WVGA) <NUM> frames per second LCD driver IC without a frame buffer, delivering pixel data at <NUM> Mbps for display refresh.

<FIG> is a diagram <NUM> illustrating a <NUM>-wire, <NUM>-phase polarity encoder that may be used to implement certain aspects of the communication link <NUM> depicted in <FIG>. The example of <NUM>-wire, <NUM>-phase encoding is selected solely for the purpose of simplifying descriptions of certain aspects of the invention. The principles and techniques disclosed for <NUM>-wire, <NUM>-phase encoders can be applied in other configurations of M-wire, N-phase polarity encoders.

Signaling states defined for each of the <NUM> wires in a <NUM>-wire, <NUM>-phase polarity encoding scheme may include an undriven state, a positively driven state and a negatively driven state. The positively driven state and the negatively driven state may be obtained by providing a voltage differential between two of the signal wires 318a, 318b and/or 318c, and/or by driving a current through two of the signal wires 318a, 318b and/or 318c connected in series such that the current flows in different directions in the two signal wires 318a, 318b and/or 318c. The undriven state may be realized by placing an output of a driver of a signal wire 318a, 318b or 318c in a high-impedance mode. Alternatively, or additionally, an undriven state may be obtained on a signal wire 318a, 318b or 318c by passively or actively causing an "undriven" signal wire 318a, 318b or 318c to attain a voltage level that lies substantially halfway between positive and negative voltage levels provided on driven signal wires 318a, 318b and/or 318c. Typically, there is no significant current flow through an undriven signal wire 318a, 318b or 318c. Signaling states defined for a <NUM>-wire, <NUM>-phase polarity encoding scheme may be denoted using the three voltage or current states (+<NUM>, -<NUM>, and <NUM>).

A <NUM>-wire, <NUM>-phase polarity encoder may employ line drivers <NUM> to control the signaling state of signal wires 318a, 318b and 318c. The line drivers <NUM> may be implemented as unit-level current-mode or voltage-mode drivers. In some implementations, each line driver <NUM> may receive sets of signals 316a, 316b and 316c that determine the output state of corresponding signal wires 318a, 318b and 318c. In one example, each of the sets of signals 316a, 316b and 316c may include two or more signals, including a pull-up signal (PU signal) and a pull-down signal (PD signal) that, when high, activate pull-up and pull down circuits that drive the signal wires 318a, 318b and 318c toward a higher level or lower level voltage, respectively. In this example, when both the PU signal and the PD signal are low, the signal wires 318a, 318b and 318c may be terminated to a mid-level voltage.

For each transmitted symbol interval in an M-wire, N-phase polarity encoding scheme, at least one signal wire 318a, 318b or 318c is in the midlevel/undriven (<NUM>) voltage or current state, while the number of positively driven (+<NUM> voltage or current state) signal wires 318a, 318b or 318c is equal to the number of negatively driven (-<NUM> voltage or current state) signal wires 318a, 318b or 318c, such that the sum of current flowing to the receiver is always zero. For each symbol, the signaling state of at least one signal wire 318a, 318b or 318c is changed from the wire state transmitted in the preceding transmission interval.

In operation, a mapper <NUM> may receive and map <NUM>-bit data <NUM> to <NUM> symbols <NUM>. In the <NUM>-wire example, each of the <NUM> symbols defines the states of the signal wires 318a, 318b and 318c for one symbol interval. The <NUM> symbols <NUM> may be serialized using parallel-to-serial converters <NUM> that provide a timed sequence of symbols <NUM> for each signal wire 318a, 318b and 318c. The sequence of symbols <NUM> is typically timed using a transmission clock. A <NUM>-wire, <NUM>-phase encoder <NUM> receives the sequence of <NUM> symbols <NUM> produced by the mapper one symbol at a time and computes the state of each signal wire 318a, 318b and 318c for each symbol interval. The <NUM>-wire, <NUM>-phase encoder <NUM> selects the states of the signal wires 318a, 318b and 318c based on the current input symbol <NUM> and the previous states of signal wires 318a, 318b and 318c.

The use of M-wire, N-phase encoding permits a number of bits to be encoded in a plurality of symbols where the bits per symbol is not an integer. In the example of a <NUM>-wire communication link, there are <NUM> available combinations of <NUM> wires, which may be driven simultaneously, and <NUM> possible combinations of polarity on the pair of wires that is driven, yielding <NUM> possible states. Since each transition occurs from a current state, <NUM> of the <NUM> states are available at every transition. The state of at least one wire is required to change at each transition. With <NUM> states, log<NUM>(<NUM>) ≅ <NUM> bits may be encoded per symbol. Accordingly, a mapper may accept a <NUM>-bit word and convert it to <NUM> symbols because <NUM> symbols carrying <NUM> bits per symbol can encode <NUM> bits. In other words, a combination of seven symbols that encode five states has <NUM><NUM> (<NUM>,<NUM>) permutations. Accordingly, the <NUM> symbols may be used to encode the <NUM><NUM> (<NUM>,<NUM>) permutations of <NUM> bits.

<FIG> includes an example of a timing chart <NUM> for signals encoded using a three-phase modulation data-encoding scheme, which is based on the circular state diagram <NUM>. Information may be encoded in a sequence of signaling states where, for example, a wire or connector is in one of three phase states S<NUM>, S<NUM> and S<NUM> defined by the circular state diagram <NUM>. Each state may be separated from the other states by a <NUM>° phase shift. In one example, data may be encoded in the direction of rotation of phase states on the wire or connector. The phase states in a signal may rotate in clockwise direction <NUM> and <NUM>' or counterclockwise direction <NUM> and <NUM>'. In the clockwise direction <NUM> and <NUM>' for example, the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. In the counterclockwise direction <NUM> and <NUM>', the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. The three signal wires 318a, 318b and 318c carry different versions of the same signal, where the versions may be phase shifted by <NUM>° with respect to one another. Each signaling state may be represented as a different voltage level on a wire or connector and/or a direction of current flow through the wire or connector. During each of the sequence of signaling states in a <NUM>-wire system, each signal wire 318a, 318b and 318c is in a different signaling states than the other wires. When more than <NUM> signal wires 318a, 318b and 318c are used in a <NUM>-phase encoding system, two or more signal wires 318a, 318b and/or 318c can be in the same signaling state at each signaling interval, although each state is present on at least one signal wire 318a, 318b and/or 318c in every signaling interval.

Information may be encoded in the direction of rotation at each phase transition <NUM>, and the <NUM>-phase signal may change direction for each signaling state. Direction of rotation may be determined by considering which signal wires 318a, 318b and/or 318c are in the '<NUM>' state before and after a phase transition, because the undriven signal wire 318a, 318b and/or 318c changes at every signaling state in a rotating three-phase signal, regardless of the direction of rotation.

The encoding scheme may also encode information in the polarity <NUM> of the two signal wires 318a, 318b and/or 318c that are actively driven. At any time in a <NUM>-wire implementation, exactly two of the signal wires 318a, 318b, 318c are driven with currents in opposite directions and/or with a voltage differential. In one implementation, data may be encoded using two bit values <NUM>, where one bit is encoded in the direction of phase transitions <NUM> and the second bit is encoded in the polarity <NUM> for the current state.

The timing chart <NUM> illustrates data encoding using both phase rotation direction and polarity. The curves <NUM>, <NUM> and <NUM> relate to signals carried on three signal wires 318a, 318b and 318c, respectively for multiple phase states. Initially, the phase transitions <NUM> are in a clockwise direction and the most significant bit is set to binary '<NUM>,' until the rotation of phase transitions <NUM> switches at a time <NUM> to a counterclockwise direction, as represented by a binary '<NUM>' of the most significant bit. The least significant bit reflects the polarity <NUM> of the signal in each state.

According to certain aspects disclosed herein, one bit of data may be encoded in the rotation, or phase change in a <NUM>-wire, <NUM>-phase encoding system, and an additional bit may be encoded in the polarity of the two driven wires. Additional information may be encoded in each transition of a <NUM>-wire, <NUM>-phase encoding system by allowing transition to any of the possible states from a current state. Given <NUM> rotational phases and two polarities for each phase, <NUM> states are available in a <NUM>-wire, <NUM>-phase encoding system. Accordingly, <NUM> states are available from any current state, and there may be log<NUM>(<NUM>) ≅ <NUM> bits encoded per symbol (transition), which allows the mapper <NUM> to accept a <NUM>-bit word and encode it in <NUM> symbols.

<FIG> is a diagram illustrating certain aspects of a <NUM>-wire, <NUM>-phase decoder <NUM>. Differential receivers 502a, 502b, 502c and a wire state decoder <NUM> are configured to provide a digital representation <NUM> of the state of the three transmission lines (e.g., the signal wires 318a, 318b and 318c illustrated in <FIG>), with respect to one another, and to detect changes in the state of the three transmission lines compared to the state transmitted in the previous symbol period. Seven consecutive states are assembled by the serial-to-parallel convertors <NUM> to obtain a set of <NUM> symbols <NUM> to be processed by the demapper <NUM>. The demapper <NUM> produces <NUM> bits of data <NUM> that may be buffered in a first-in-first-out (FIFO) register <NUM> to provide output data <NUM>.

The wire state decoder <NUM> may extract a sequence of symbols <NUM> from phase encoded signals received on the signal wires 318a, 318b and 318c. The symbols <NUM> are encoded as a combination of phase rotation and polarity as disclosed herein. The wire state decoder may include a CDR circuit <NUM> that extracts a clock <NUM> that can be used to reliably capture wire states from the signal wires 318a, 318b and 318c. A transition occurs on least one of the signal wires 318a, 318b and 318c at each symbol boundary and the CDR circuit <NUM> may be configured to generate the clock <NUM> based on the occurrence of a transition or multiple transitions. An edge of the clock may be delayed to allow time for all signal wires 318a, 318b and 318c to have stabilized and to thereby ensure that the current wire state is captured for decoding purposes.

<FIG> is state diagram <NUM> illustrating the possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the three wires, with the possible transitions illustrated from each state. In the example of a <NUM>-wire, <NUM>-phase communication link, <NUM> states and <NUM> state transitions are available. The possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> include and expand on the states shown in the circular state diagram <NUM> of <FIG>. As shown in the exemplar of a state element <NUM>, each signaling state <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> defines voltage signaling state of the signal wires 318a, 318b, 318c, which are labeled A, B and C respectively. For example, in signaling state <NUM> (+x) wire A= +<NUM>, wire B = -<NUM> and wire C= <NUM>, yielding output of differential receiver 502a (A-B) = +<NUM>, differential receiver 502b (B-C) = -<NUM> and differential receiver 502c (C-A) = -<NUM>. Transition decisions taken by phase change detect circuits in a receiver are based on <NUM> possible levels produced by the differential receivers 502a, 502b, 502c, which include -<NUM>, -<NUM>, <NUM>, +<NUM> and +<NUM> voltage states.

The transitions in the state diagram <NUM> can be represented by a Flip, Rotate, Polarity symbol (e.g., the FRP symbol <NUM>) that has one of the three-bit binary values in the set: {<NUM>, <NUM>, <NUM>, <NUM>, <NUM>}. The Rotation bit <NUM> of the FRP symbol <NUM> indicates the direction of phase rotation associated with a transition to a next state. The Polarity bit <NUM> of the FRP symbol <NUM> is set to binary <NUM> when a transition to a next state involves a change in polarity. When the Flip bit <NUM> of the FRP symbol <NUM> is set to binary <NUM>, the Rotate and Polarity values may be ignored and/or zeroed. A flip represents a state transition that involves only a change in polarity. Accordingly, the phase of a <NUM>-phase signal is not considered to be rotating when a flip occurs and the polarity bit is redundant when a flip occurs. The FRP symbol <NUM> corresponds to wire state changes for each transition. The state diagram <NUM> may be separated into an inner circle <NUM> that includes the positive polarity signaling states <NUM>, <NUM>, <NUM> and an outer circle <NUM> that encompasses the negative polarity signaling states <NUM>, <NUM>, <NUM>.

A <NUM>-phase transmitter includes drivers that provide high, low and middle-level voltages onto the transmit channel. This results in some variable transitions between consecutive symbol intervals. Low-to-high and high-to-low voltage transitions may be referred to as full-swing transitions, while low-to-middle and high-to-middle voltage transitions may be referred to as half-swing transitions. Different types of transitions may have different rise or fall times, and may result in different zero crossings at the receiver. These differences can result in "encoding jitter," which may impact link signal integrity performance.

<FIG> is a timing diagram <NUM> that illustrates certain aspects of transition variability at the output of a C-PHY <NUM>-phase transmitter. Variability in signal transition times may be attributed to the existence of the different voltage and/or current levels used in <NUM>-phase signaling. The timing diagram <NUM> illustrates transition times in a signal received from a single signal wire 318a, 318b or 318c. A first symbol Symn <NUM> is transmitted in a first symbol interval that ends at a time <NUM> when a second symbol Symn+<NUM> <NUM> is transmitted in a second symbol interval. The second symbol interval may end at time <NUM> when a third symbol Symn+<NUM> <NUM> is transmitted in the third symbol interval, which ends when a fourth symbol Symn+<NUM> <NUM> is transmitted in a fourth symbol interval. The transition from a state determined by the first symbol <NUM> to the state corresponding to the second symbol <NUM> may be detectable after a delay <NUM> attributable to the time taken for voltage in the signal wire 318a, 318b or 318c to reach a threshold voltage <NUM> and/or <NUM>. The threshold voltages may be used to determine the state of the signal wire 318a, 318b or 318c. The transition from a state determined by the second symbol <NUM> to the state for the third symbol <NUM> may be detectable after a delay <NUM> attributable to the time taken for voltage in the signal wire 318a, 318b or 318c to reach one of the threshold voltages <NUM> and/or <NUM>. The transition from a state determined by the third symbol <NUM> to the state for the fourth symbol <NUM> may be detectable after a delay <NUM> attributable to the time taken for voltage in the signal wire 318a, 318b or 318c to reach a threshold voltage <NUM> and/or <NUM>. The delays <NUM>, <NUM> and <NUM> may have different durations, which may be attributable in part to variations in device manufacturing processes and operational conditions, which may produce unequal effects on transitions between different voltage or current levels associated with the <NUM> states and/or different transition magnitudes. These differences may contribute to jitter and other issues in C-PHY <NUM>-phase receiver.

<FIG> illustrates certain aspects of CDR circuits that may be provided in a receiver in a C-PHY interface <NUM>. Differential receivers 802a, 802b and 802c are configured to generate a set of difference signals 810a, 810b, 810c by comparing signaling state of each different pair of signal wires 318a, 318b and 318c in a trio. In the illustrated example, a first differential receiver 802a provides an AB difference signal 810a representative of the difference in signaling state of A and B signal wires 318a and 318b, a second differential receiver 802b provides a BC difference signal 810b representative of the difference in signaling state of B and C signal wires 318b and 318c and a third differential receiver 802c provides a CA difference signal 810c representative of the difference in signaling state of C and A signal wires 318c and 318a. Accordingly, a transition detection circuit <NUM> can be configured to detect occurrence of a phase change because the output of at least one of the differential receivers 802a, 802b and 802c changes at the end of each symbol interval.

Transitions between some consecutively transmitted pairs of symbols are detectable by a single differential receiver 802a, 802b or 802c, while other transitions may be detected by two or more of the differential receivers 802a, 802b and 802c. In one example the states, or relative states of two wires may be unchanged after a transition and the output of a corresponding differential receiver 802a, 802b or 802c may also be unchanged after the phase transition. Accordingly, a clock generation circuit <NUM> may include a transition detection circuit <NUM> and/or other logic to monitor the outputs of all differential receivers 802a, 802b and 802c in order to determine when a phase transition has occurred. The clock generation circuit generates a receive clock signal <NUM> based on detected phase transitions.

Changes in signaling states of the <NUM> wires in a trio may be detected at different times, which can result in the difference signals 810a, 810b, 810c assuming stable states at different times. The state of the difference signals 810a, 810b, 810c may switch before stability has been reached after the signaling state of each signal wire 318a, 318b and/or 318c has transitioned to its defined state for a symbol transmission interval. The result of such variability is illustrated in the timing diagram <NUM> of <FIG>.

The timing of signaling state change detection may vary according to the type of signaling state change that has occurred. Markers <NUM>, <NUM> and <NUM> represent occurrences of transitions in the difference signals 810a, 810b, 810c provided to the transition detection circuit <NUM>. The markers <NUM>, <NUM> and <NUM> are assigned different heights in the timing diagram <NUM> for clarity of illustration only, and the relative heights of the markers <NUM>, <NUM> and <NUM> are not intended to show a specific relationship to voltage or current levels, polarity or weighting values used for clock generation or data decoding. The timing diagram <NUM> illustrates the effect of timing of transitions associated with symbols transmitted in phase and polarity on the three signal wires 318a, 318b and 318c. In the timing diagram <NUM>, transitions between some symbols may result in variable capture windows 830a, 830b, 830c, 830d, 830e, 830f and/or <NUM> (collectively symbol capture windows <NUM>) during which symbols may be reliably captured. The number of state changes detected and their relative timing can result in jitter on the clock signal <NUM>.

The throughput of a C-PHY communication link may be affected by duration and variability in signal transition times. For example, variability in detection circuits may be caused by manufacturing process tolerances, variations and stability of voltage and current sources and operating temperature, as well as by the electrical characteristics of the signal wires 318a, 318b and 318c. The variability in detection circuits may limit channel bandwidth.

<FIG> includes timing diagrams <NUM> and <NUM> representative of certain examples of transitions from a first signaling state to a second signaling state between certain consecutive symbols. The signaling state transitions illustrated in the timing diagrams <NUM> and <NUM> are selected for illustrative purposes, and other transitions and combinations of transitions can occur in a MIPI Alliance C-PHY interface. The timing diagrams <NUM> and <NUM> relate to an example of a <NUM>-wire, <NUM>-phase communication link, in which multiple receiver output transitions may occur at each symbol interval boundary due to differences in rise and fall time between the signal levels on the trio of wires. With reference also to <FIG>, the first timing diagrams <NUM> illustrate the signaling states of the trio of signal wires 318a, 318b and 318c (A, B, and C) before and after a transition and second timing diagrams <NUM> illustrate the outputs of the differential receivers 802a, 802b and 802c, which provides difference signals 810a, 810b, 810c representative of the differences between signal wires 318a, 318b and 318c. In many instances, a set of differential receivers 802a, 802b and 802c may be configured to capture transitions by comparing different combinations for two signal wires 318a, 318b and 318c. In one example, these differential receivers 802a, 802b and 802c may be configured to produce outputs by determining the difference (e.g. by subtraction) of their respective input voltages.

In each of the examples shown in the timing diagrams <NUM> and <NUM>, the initial a symbol representing the -z state <NUM> (see <FIG>) transitions to a different symbol. As shown in the timing diagrams <NUM>, <NUM> and <NUM> signal A is initially in a +<NUM> state, signal B is in a <NUM> state and signal C is in the -<NUM> state. Accordingly, the differential receivers 802a, 802b initially measure a +<NUM> difference <NUM> and the differential receiver 802c measures a -<NUM> difference <NUM>, as shown in the timing diagrams <NUM>, <NUM>, <NUM> for the differential receiver outputs.

In a first example corresponding to the timing diagrams <NUM>, <NUM>, a transition occurs from a symbol representing the -z state <NUM> to a symbol representing the -x signaling state <NUM> (see <FIG>) in which signal A transitions to a -<NUM> state, signal B transitions to a +<NUM> state and signal C transitions to a <NUM> state, with the differential receiver 802a transitioning from +<NUM> difference <NUM> to a -<NUM> difference <NUM>, differential receiver 802b remaining at a +<NUM> difference <NUM>, <NUM> and differential receiver 802c transitioning from -<NUM> difference <NUM> to a +<NUM> difference <NUM>.

In a second example corresponding to the timing diagrams <NUM>, <NUM>, a transition occurs from a symbol representing the -z signaling state <NUM> to a symbol representing the +z signaling state <NUM> in which signal A transitions to a -<NUM> state, signal B remains at the <NUM> state and signal C transitions to a +<NUM> state, with two differential receivers 802a and 802b transitioning from +<NUM> difference <NUM> to a -<NUM> difference <NUM>, and differential receiver 802c transitioning from -<NUM> difference <NUM> to a +<NUM> difference <NUM>.

In a third example corresponding to the timing diagrams <NUM>, <NUM>, a transition occurs from a symbol representing the -z signaling state <NUM> to a symbol representing the +x signaling state <NUM> in which signal A remains at the +<NUM> state, signal B transitions to the - <NUM> state and signal C transitions to a <NUM> state, with the differential receiver 802a transitioning from a +<NUM> difference <NUM> to a +<NUM> difference <NUM>, the differential receiver 802b transitioning from a +<NUM> difference <NUM> to a -<NUM> difference <NUM>, and the differential receiver 802c transitioning from -<NUM> difference <NUM> to a -<NUM> difference <NUM>.

These examples illustrate transitions in difference values spanning <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> levels. Pre-emphasis techniques used for typical differential or single-ended serial transmitters were developed for two level transitions and may introduce certain adverse effects if used on a MIPI Alliance C-PHY <NUM>-phase signal. In particular, a pre-emphasis circuit that overdrives a signal during transitions may cause overshoot during transitions spanning <NUM> or <NUM> levels and may cause false triggers to occur in edge sensitive circuits.

<FIG> illustrates a binary eye pattern <NUM> generated as an overlay of multiple symbol intervals, including a single symbol interval <NUM>. A signal transition region <NUM> represents a time period of uncertainty at the boundary between two symbols where variable signal rise times prevent reliable decoding. State information may be determined reliably in a region defined by an eye mask <NUM> within an "eye opening" that represents the time period in which the symbol is stable and can be reliably received and decoded. The eye mask <NUM> masks off a region in which zero crossings do not occur, and the eye mask is used by the decoder to prevent multiple clocking due to the effect of subsequent zero crossings at the symbol interval boundary that follow the first signal zero crossing.

The concept of periodic sampling and display of the signal is useful during design, adaptation and configuration of systems which use a clock-data recovery circuit that recreates the received data-timing signal using frequent transitions appearing in the received data. A communication system based on Serializer/Deserializer (SERDES) technology is an example of a system where a binary eye pattern <NUM> can be utilized as a basis for judging the ability to reliably recover data based on the eye opening of the binary eye pattern <NUM>.

An M-wire N-Phase encoding system, such as a <NUM>-wire, <NUM>-phase encoder may encode a signal that has at least one transition at every symbol boundary and the receiver may recover a clock using those guaranteed transitions. The receiver may require reliable data immediately prior to the first signal transition at a symbol boundary, and must also be able to reliably mask any occurrences of multiple transitions that are correlated to the same symbol boundary. Multiple receiver transitions may occur due to slight differences in rise and fall time between the signals carried on the M-wires (e.g. a trio of wires) and due to slight differences in signal propagation times between the combinations of signal pairs received (e.g. A-B, B-C, and C-A outputs of differential receivers 802a, 802b and 802c of <FIG>).

<FIG> illustrates an example of a multi-level eye-pattern <NUM> generated for a C-PHY <NUM>-phase signal. The multi-level eye-pattern <NUM> may be generated from an overlay of multiple symbol intervals <NUM>. The multi-level eye-pattern <NUM> may be produced using a fixed and/or symbol-independent trigger <NUM>. The multi-level eye-pattern <NUM> includes an increased number of voltage levels <NUM>, <NUM>, <NUM>, <NUM>, <NUM> that may be attributed to the multiple voltage levels measured by the differential receivers 802a, 802b, 802c an N-phase receiver circuit (see <FIG>). In the example, the multi-level eye-pattern <NUM> may correspond to possible transitions in <NUM>-wire, <NUM>-phase encoded signals provided to the differential receivers 802a, 802b, and 802c. The three voltage levels may cause the differential receivers 802a, 802b, and 802c to generate strong voltage levels <NUM>, <NUM> and weak voltage levels <NUM>, <NUM> for both positive and negative polarities. Typically, only one signal wire 318a, 318b and 318c is undriven in any symbol and the differential receivers 802a, 802b, and 802c do not produce a <NUM> state (here, <NUM> Volts) output. The voltages associated with strong and weak levels need not be evenly spaced with respect to a <NUM> Volts level. For example, the weak voltage levels <NUM>, <NUM> represent a comparison of voltages that may include the voltage level reached by an undriven signal wire 318a, 318b and 318c. The multi-level eye-pattern <NUM> may overlap the waveforms produced by the differential receivers 802a, 802b, and 802c because all three pairs of signals are considered simultaneously when data is captured at the receiving device. The waveforms produced by the differential receivers 802a, 802b, and 802c are representative of difference signals 810a, 810b, 810c representing comparisons of three pairs of signals (A-B, B-C, and C-A).

Drivers, receivers and other devices used in a C-PHY <NUM>-Phase decoder may exhibit different switching characteristics that can introduce relative delays between signals received from the three wires. Multiple receiver output transitions may be observed at each symbol interval boundary <NUM> and/or <NUM> due to slight differences in the rise and fall time between the three signals of the trio of signal wires 318a, 318b, 318c and due to slight differences in signal propagation times between the combinations of pairs of signals received from the signal wires 318a, 318b, 318c. The multi-level eye-pattern <NUM> may capture variances in rise and fall times as a relative delay in transitions near each symbol interval boundary <NUM> and <NUM>. The variances in rise and fall times may be due to the different characteristics of the <NUM>-Phase drivers. Differences in rise and fall times may also result in an effective shortening or lengthening of the duration of the symbol interval <NUM> for any given symbol.

A signal transition region <NUM> represents a time, or period of uncertainty, where variable signal rise times prevent reliable decoding. State information may be reliably determined in an "eye opening" <NUM> representing the time period in which the symbol is stable and can be reliably received and decoded. In one example, the eye opening <NUM> may be determined to begin at the end <NUM> of the signal transition region <NUM>, and end at the symbol interval boundary <NUM> of the symbol interval <NUM>. In the example depicted in <FIG>, the eye opening <NUM> may be determined to begin at the end <NUM> of the signal transition region <NUM>, and end at a time <NUM> when the signaling state of the signal wires 318a, 318b, 318c and/or the outputs of the three differential receivers 802a, 802b and 802c have begun to change to reflect the next symbol.

The maximum speed of a communication link <NUM> configured for N-Phase encoding may be limited by the duration of the signal transition region <NUM> compared to the eye opening <NUM> corresponding to the received signal. The minimum period for the symbol interval <NUM> may be constrained by tightened design margins associated with the CDR circuit <NUM> in the decoder <NUM> illustrated in <FIG>, for example. Different signaling state transitions may be associated with different variations in signal transition times corresponding to two or more signal wires 318a, 318b and/or 318c, thereby causing the outputs of the differential receivers 802a, 802b and 802c in the receiving device to change at different times and/or rates with respect to the symbol interval boundary <NUM>, where the inputs of the differential receivers 802a, 802b and 802c begin to change. The differences between signal transition times may result in timing skews between signaling transitions in two or more difference signals 810a, 810b, 810c. CDR circuits may include delay circuits and other circuits to accommodate timing skews between the difference signals 810a, 810b, 810c.

<FIG> provides an example of a CDR circuit <NUM> for a <NUM>-wire, <NUM>-phase interface. The illustrated CDR circuit <NUM> includes certain features and functional elements that are common to many different types of clock recovery circuits. The CDR circuit <NUM> receives difference signals <NUM>, <NUM>, <NUM>, which may be derived from the difference signals 810a, 810b, 810c produced by the differential receivers 802a, 802b and 802c of <FIG> for example. In the CDR circuit <NUM>, each difference signal <NUM>, <NUM>, <NUM> clocks a pair of D flipflops 1210a, 1210b, 1210c to produce output signals 1230a-1230f. The output signals 1230a-1230f carry a pulse when a transition is detected on the corresponding difference signal <NUM>, <NUM>, <NUM>. A rising edge provided to a clock input on a D flipflop clocks a logic one through the D flipflop. Inverters 1208a, 1208b, 1208c may be used to provide inverted versions of the difference signals <NUM>, <NUM>, <NUM> to one of the D flipflops in each corresponding pair of D flipflops 1210a, 1210b, 1210c. Accordingly, each pair of D flipflops 1210a, 1210b, 1210c produces pulses responsive to rising edge and falling edges detected in the corresponding difference signal <NUM>, <NUM>, <NUM>.

For example, the AB difference signal <NUM> is provided to a first D flipflop <NUM> of a first pair of D flipflops 1210a, and the inverter 1208a provides an inverted version of the AB difference signal <NUM> to a second D flipflop <NUM> of the first pair of D flipflops 1210a. The D flipflops are initially in a reset state. A rising edge on the AB difference signal <NUM> clocks a logic one through the first D flipflop <NUM> causing the output of the first flipflop (r_AB) 1230a to transition to a logic one state. A falling edge on the AB difference signal <NUM> clocks a logic one through the second D flipflop <NUM> causing the output of the second flipflop (f_AB) 1230b to transition to a logic one state.

The output signals 1230a-1230f are provided to logic, such as the OR gate <NUM>, which produces an output signal that may serve as the receiver clock (RxCLK) signal <NUM>. The RxCLK signal <NUM> transitions to a logic one state when a transition occurs in signaling state of any of the difference signals <NUM>, <NUM>, <NUM>. The RxCLK signal <NUM> is provided to a programmable delay circuit <NUM>, which drives a reset signal (rb signal <NUM>) that resets the D flipflops in the pairs of D flipflops 1210a, 1210b, 1210c. In the illustrated example, an inverter <NUM> may be included when the D flipflops are reset by a low signal. When the D flipflops are reset, the output of the OR gate <NUM> returns to the logic <NUM> state and the pulse on the RxCLK signal <NUM> is terminated. When this logic <NUM> state propagates through the programmable delay circuit <NUM> and the inverter <NUM>, the reset condition on the D flipflops is released. While the D flipflops are in the reset condition, transitions on the difference signals <NUM>, <NUM>, <NUM> are ignored.

The programmable delay circuit <NUM> is typically configured to produce a delay that has a duration that exceeds the difference in the timing skew between the occurrence of first and last transitions on the difference signals <NUM>, <NUM>, <NUM>. The programmable delay circuit <NUM> configures the duration of pulses (i.e., the pulse width) on the RxCLK signal <NUM>. The programmable delay circuit <NUM> may be configured when a Set signal <NUM> is asserted by a processor or other control and/or configuration logic.

The RxCLK signal <NUM> may also be provided to a set of three flipflops <NUM> that capture the signaling state of the difference signals <NUM>, <NUM>, <NUM>, providing a stable output symbol <NUM> for each pulse that occurs on the RxCLK signal <NUM>. Delay or alignment logic <NUM> may adjust the timing of the set of difference signals <NUM>, <NUM>, <NUM>. For example, the delay or alignment logic <NUM> may be used to adjust the timing of the difference signals <NUM>, <NUM>, <NUM> with respect to the pulses on the RxCLK signal <NUM> to ensure that the flipflops <NUM> capture the signaling state of the difference signals <NUM>, <NUM>, <NUM> when the difference signals <NUM>, <NUM>, <NUM> are stable. The delay or alignment logic <NUM> may delay edges in the difference signals <NUM>, <NUM>, <NUM> based on the delay configured for the programmable delay circuit <NUM>.

The programmable delay circuit <NUM> may be configured in the CDR circuit <NUM> to accommodate possible large variations in transition times in the difference signals <NUM>, <NUM>, <NUM>. In one example, the programmable delay circuit <NUM> is typically configured to provide a minimum delay period that exceeds the duration of the timing skew between the occurrence of the first and last transitions on the difference signals <NUM>, <NUM>, <NUM>. The delay time provided by the programmable delay circuit <NUM> is calculated to account for the number of logic gates in the delay loop of the CDR circuit <NUM> and is constrained to a minimum delay time that accounts for expected or observed PVT variances that can affect the logic gates and/or the programmable delay circuit <NUM>. For reliable operation of the CDR circuit <NUM>, the maximum delay time provided by the programmable delay circuit <NUM> may not be greater than the symbol interval. At faster data rates, timing skew and the delay time provided by the delay loop of the CDR circuit <NUM> increase as a proportion of the symbol interval <NUM>. The eye opening <NUM> can become small in comparison to the symbol interval <NUM> and the eye opening <NUM> can close at higher frequencies. The maximum symbol transmission rate may be limited when the delay time provided by the programmable delay circuit <NUM> reduces the percentage of the symbol interval <NUM> occupied by the eye opening <NUM> below a threshold size that can support reliable capture of symbols.

<FIG> is a timing diagram <NUM> that illustrates certain aspects of the operation of the CDR circuit <NUM>. The diagram relates to operations after the programmable delay circuit <NUM> has been configured, and the Set signal <NUM> is inactive. The CDR circuit <NUM> operates as an edge detector. C-PHY <NUM>-phase encoding provides a single signaling state transition per unit interval (UI) <NUM>. Differences in the state of each wire of the trio, and/or transmission characteristics of the trio may cause a transition to appear at different times on two or more wires. The maximum difference in time of occurrence of transitions in the difference signals <NUM>, <NUM>, <NUM> may be referred to as the skew time (tskew) <NUM>. Other delays associated with the CDR circuit <NUM> include the propagation delay (tck2q) <NUM> through the pairs of D flipflops 1210a, 1210b, 1210c, the propagation delay (tPR_0) <NUM> associated with a rising edge passed through the OR gate <NUM>, the propagation delay (tOR_1) <NUM> associated with a falling edge passed through the OR gate <NUM>, the programmable delay (tpgm) <NUM> combining the delay introduced by the programmable delay circuit <NUM> and a driver and/or inverter <NUM>, and the reset delay (trst) <NUM> corresponding to the delay between time of receipt of the rb signal <NUM> by the pairs of D flipflops 1210a, 1210b, 1210c and time at which the flipflop outputs are cleared.

A loop delay (tloop <NUM>) may be defined as: <MAT>.

The relationship between tloop <NUM> and the UI <NUM> may determine the reliability of operation of the CDR circuit <NUM>. This relationship is affected by clock frequency used for transmission, which has a direct effect on the UI <NUM>, and variability in the operation of the programmable delay circuit <NUM>.

In some devices, the operation of the programmable delay circuit <NUM> can be afflicted by variations in operating conditions, including variations in manufacturing process, circuit supply voltage, and die temperature (PVT) conditions. The delay time provided by the programmable delay circuit <NUM> for a configured value may vary significantly from device to device, and/or from circuit to circuit within a device. In conventional systems, the nominal operating condition of the CDR circuit <NUM> is generally set by design to generate a clock edge somewhere in the middle of the eye opening <NUM> under all PVT conditions, in order to ensure that a clock edge occurs after the end <NUM> of the signal transition region <NUM> and prior to the commencement of the transition region to the next symbol, even under worst case PVT effects. Difficulty can arise in designing a CDR circuit <NUM> that guarantees a clock edge within the eye opening <NUM> when the transmission frequency increases and timing skew of the difference signals <NUM>, <NUM>, <NUM> is large compared to the UI <NUM>. For example, a typical delay circuit may produce a delay value that changes by a factor of <NUM> over all PVT conditions.

<FIG> is a timing diagram <NUM> that illustrates the effect of a programmable delay circuit <NUM> that provides an insufficient delay. In this example, tloop <NUM> is too short for the observed tskew <NUM>, and multiple clock pulses <NUM>, <NUM> are generated in one UI <NUM>. That is, the loop delay tloop <NUM> is not big enough relative to tskew <NUM>, and later occurring transitions on the difference signals <NUM>, <NUM>, <NUM> are not masked. In the depicted example, a second transition <NUM> in one of the difference signals <NUM> may be detected after a pulse <NUM> has been generated in response to a first occurring transition <NUM> in another of the difference signals <NUM>. In this example, the recovered clock frequency may be twice the clock frequency used to transmit symbols on the <NUM>-phase interface.

<FIG> is a timing diagram <NUM> that illustrates the effect of a programmable delay circuit <NUM> that provides a delay that is too long. In this example, there is an observed skew of duration tskew <NUM> and tloop <NUM> is greater than the UI <NUM>. The CDR circuit <NUM> may generate a clock pulse <NUM> in response to a first-occurring transition <NUM> in a first UI <NUM>, but the rb signal <NUM> may be active when transitions <NUM>, <NUM> occur in a second UI <NUM>, In the example depicted, the transitions <NUM>, <NUM> in the second UI <NUM> are masked, and the expected pulse <NUM> corresponding to the second UI <NUM> is suppressed. In this example, the recovered clock frequency may be half the clock frequency used to transmit symbols on the <NUM>-phase interface.

As illustrated by the examples of <FIG> and <FIG>, the CDR circuit <NUM> may be subject to the constraint: <MAT>.

Empirical evidence suggests that tloop <NUM>, <NUM>, <NUM> is very sensitive to PVT. tloop <NUM> for the CDR circuit <NUM> may be restated as: <MAT>.

The loop time is susceptible to reliability at higher symbol rates due to the large number of delays that are sensitive to PVT variations, the double tpgm delay and the large delay associated with the <NUM>-input OR gate <NUM> can limit the maximum frequency of a clock signal recoverable by the CDR circuit <NUM>. Increasing the delay provided by the programmable delay circuit <NUM> to accommodate the range of potential variations of PVT serves to further limit the maximum frequency of the clock signal recoverable by the CDR circuit <NUM>.

More recent implementations and proposed specifications for C-PHY, including the C-PHY <NUM> specifications and C-PHY <NUM> specifications, define frequencies of symbol transmission clock signals that can exceed the capabilities of conventional CDR circuits to recover a clock signal at the receiver. The symbol transmission clock signal is used to control the rate of symbol transmission and determines the duration of the UI <NUM>. The duration of the UI <NUM> is reduced when the frequency of the symbol transmission clock signal is increased. Constraints introduced by the loop delay in the CDR circuit <NUM> limit the minimum duration of the UI <NUM> that can be supported by the CDR circuit <NUM>, which limits the maximum frequency of the symbol transmission clock signal that can be supported by the CDR circuit <NUM>. Even using advanced device technology, the loop delay in the CDR circuit <NUM> can exceed <NUM> picoseconds under certain PVT conditions, which can limit conventional C-PHY applications to a maximum symbol transmission rate of <NUM> Gigasymbols per second. In some implementations, the constraint on the duration of the UI <NUM> introduced by the loop delay in the CDR circuit <NUM> can render the conventional CDR circuit <NUM> ineffective for use in C-PHY interfaces that are to conform to later generations of C-PHY specifications.

The ability to increase the frequency of the symbol transmission clock may be limited by the capabilities of circuits in C-PHY transmitters and receivers. In many implementations, switching times defined for logic gates may limit the maximum frequency of the symbol transmission clock, and/or may limit the number of levels of gates in circuits used to transmit or receive symbols at higher clock frequencies. In one example, propagation time through logic circuits of a receiver circuit can constrain the minimum UI that can be supported by the receiver, and/or the window of time during which a symbol can be reliably sampled. In another example, the generation and distribution of a high-speed symbol transmission clock signal may be difficult to accomplish and/or may complicate integrated circuit design.

In accordance with certain aspects of this disclosure, increased and/or maximized symbol transmission rates may be accomplished using half-rate symbol transmission clocks. A conventional C-PHY data path operates using a full-rate symbol transmission clock, whereby data is transmitted and sampled on a single type of edge of the transmitter's symbol clock signal or receiver's symbol clock signal respectively. The type of edge used for timing in a symbol clock signal may be the rising edge or the falling edge, based on the circuit design employed in an implementation. Data throughput is determined by the symbol rate of the C-PHY interface, where symbol rate may be expressed as the number of symbols transmitted per second over the C-PHY bus. According to conventional C-PHY specifications: <MAT>.

Data throughput may be measured as the number of bits per second transmitted over the C-PHY bus. In one example, approximately <NUM> bits can be encoded in the transitions between consecutively-transmitted symbols, such that: <MAT>.

A C-PHY interface implemented in accordance with certain aspects of this disclosure can increase data throughput of a C-PHY interface by using half-rate symbol clock signal to control timing in a C-PHY data path. In one example, a transmitter can transmit symbols on rising edges and falling edges of the symbol transmission clock signal. In another example, a receiver can generate a half-rate symbol clock signal that is half the frequency of the symbol transmission clock signal, and can use rising edges and falling edges of the generated clock signal to capture symbols transmitted through the C-PHY interface. The use of a half-rate symbol clock signal in accordance with certain aspects of this disclosure provides that: <MAT>.

Data throughput is measured as the number of bits per second transmitted over the C-PHY bus. When <NUM> bits are encoded in the transitions between consecutively-transmitted symbols: <MAT>.

In one example, the data throughput obtained using a <NUM> full-rate symbol clock signal in a conventional C-PHY interface can be obtained using a <NUM> half-rate symbol clock signal in a C-PHY interface implemented in accordance with certain aspects of this disclosure.

<FIG> illustrates a clock recovery circuit <NUM> that is configured to provide a half-rate symbol clock signal <NUM> from signaling transmitted through a C-PHY interface. Multiple delay circuits <NUM>, <NUM>, <NUM>, <NUM> are used to mask variations in transition times in the difference signals <NUM>, <NUM>, <NUM>. The delay circuits <NUM>, <NUM>, <NUM> are provided in a pulse merge circuit <NUM> that generates, and merges transition pulses representative of transitions detected in the difference signals <NUM>, <NUM>, <NUM>. <FIG> is a timing diagram <NUM> that illustrates timing associated with the pulse merge circuit <NUM> and clock recovery circuit <NUM>.

The pulse merge circuit <NUM> receives difference signals <NUM>, <NUM>, <NUM> that represent differences in signaling state of pairs of wires the trio of wires A, B and C. The difference signals <NUM>, <NUM>, <NUM> are received from differential receivers or comparators such as differential receivers 802a, 802b and 802c that produce the difference signals 810a, 810b, 810c illustrated in <FIG>. The pulse merge circuit <NUM> uses three exclusive-OR gates <NUM>, <NUM>, <NUM> and corresponding delay circuits <NUM>, <NUM> and <NUM> to generate transition pulses <NUM>, <NUM>, <NUM> in response to transitions occurring in the difference signals <NUM>, <NUM>, <NUM>. In the example of the illustrated timing diagram <NUM>, a transition in the AB difference signal <NUM>, the BC difference signal <NUM> and the CA difference signal <NUM> occurs at the each of the illustrated symbol boundaries 1710a, 1710b, 1710c, 1710d. The transitions in the difference signals <NUM>, <NUM>, <NUM> can occur at different times, such that a skew <NUM> can be observed between the first-occurring transition and the last-occurring transition. In the illustrated example, the first-occurring transition is observed at the first illustrated symbol boundary 1710a on the AB difference signal <NUM> and the last-occurring transition at the first illustrated symbol boundary 1710a is observed on the CA difference signal <NUM>. The relationship between transitions can be different at each symbol boundary 1710a, 1710b, 1710c, 1710d. In operation, a transition may not occur on one of the difference signals <NUM>, <NUM>, <NUM> at one or more symbol boundaries 1710a, 1710b, 1710c, 1710d.

A first exclusive-OR gate <NUM> receives the AB difference signal <NUM> and a delayed version of the AB difference signal <NUM> provided by the AB-delay circuit <NUM>, and provides an AB_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the AB-delay circuit <NUM>. A second exclusive-OR gate <NUM> receives the BC difference signal <NUM> and a delayed version of the BC difference signal <NUM> provided by the BC-delay circuit <NUM>, and provides a BC_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the BC-delay circuit <NUM>. A third exclusive-OR gate <NUM> receives the CA difference signal <NUM> and a delayed version of the CA difference signal <NUM> provided by the CA-delay circuit <NUM>, and provides a CA_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the CA-delay circuit <NUM>. The AB_p signal <NUM>, the BC_p signal <NUM> and the CA_p signal <NUM> are provided to an OR-gate <NUM> that provides an eg_pulse signal <NUM> that includes combined pulses <NUM> corresponding to the pulses <NUM>, <NUM>, <NUM> in the AB_p signal <NUM>, the BC_p signal <NUM> and the CA_p signal <NUM>. In some instances, two or more of the pulses <NUM>, <NUM>, <NUM> may overlap in time and are merged in the combined pulses <NUM>.

The eg_pulse signal <NUM> clocks a delay flipflop (DFF <NUM>) in the clock recovery circuit <NUM>. Each rising edge in the eg_pulse signal <NUM> clocks an inverted, delayed half-rate symbol clock signal <NUM> from the D input through to the output (Q) of the DFF <NUM>. The output of the DFF <NUM> provides the half-rate symbol clock signal <NUM> (rclk). The delay circuits <NUM>, <NUM> and <NUM> may be configured to provide pulses <NUM>, <NUM>, <NUM> that have a duration sufficient to clock the DFF <NUM> under expected or observed PVT conditions. For example, the duration of the pulses <NUM>, <NUM>, <NUM> may be configured based on a minimum duration for a clock pulse.

The clock recovery circuit <NUM> is configured to provide a half-rate symbol clock signal <NUM> that changes state at each symbol boundary 1710a, 1710b, 1710c, 1710d. For example, the inverted, delayed half-rate symbol clock signal <NUM> is in a logic <NUM> state at the first symbol boundary 1710a, while the half-rate symbol clock signal <NUM> is at logic <NUM>. The first rising edge in the combined pulses <NUM>, which corresponds to the first difference pulse <NUM>, clocks the logic <NUM> level through to the Q output of the DFF <NUM>, causing the half-rate symbol clock signal <NUM> to transition to the logic <NUM> state. A combination of a delay circuit <NUM> and an inverter <NUM> delay the transition in the half-rate symbol clock signal <NUM> and cause the inverted, delayed half-rate symbol clock signal <NUM> to transition to the logic <NUM> state after a rise delay <NUM>. The duration of the rise delay <NUM> is configured to mask additional edges in the eg_pulse signal <NUM> such that difference pulses <NUM>, <NUM> corresponding to the first symbol boundary 1710a have no effect on the state of the half-rate symbol clock signal <NUM>.

The first rising edge in the combined pulses corresponding to the second symbol boundary 1710b clocks the logic <NUM> level of the inverted, delayed half-rate symbol clock signal <NUM> through to the Q output of the DFF <NUM>, causing the half-rate symbol clock signal <NUM> to transition to the logic <NUM> state. The duration of a fall delay <NUM> is configured to mask additional edges in the eg_pulse signal <NUM> such that difference pulses corresponding to the second symbol boundary 1710b have no effect on the state of the half-rate symbol clock signal <NUM>. The delay circuit <NUM> is configured to provide matching durations of the rise delay <NUM> and the fall delay <NUM>. Configuration of the delay circuit <NUM> is constrained by the need to match the durations of the rise delay <NUM> and the fall delay <NUM> and to mask additional pulses at symbol boundaries 1710a, 1710b, 1710c, 1710d.

The maximum frequency of operation of the Clock recovery circuit <NUM> and the corresponding minimum UI may be determined by the timing constraints associated with the clock recovery circuit <NUM> and the pulse merge circuit <NUM>. The timing constraints may be stated as: <MAT> <MAT> <MAT> <MAT> <MAT>.

In many implementations, the matching rise_dly and fall_dly duration constraint requires duplicate delay cells and the intrinsic delay of the two delay cells can be quite large. In some instances, the delay cells in the delay circuit <NUM> are associated with delay durations that cause the total delay to be large and unsuitable for newer C-PHY implementations.

<FIG> illustrates a CDR circuit <NUM> that is configured to provide a high-frequency half-rate symbol clock signal <NUM> from signaling transmitted through a C-PHY interface. Delay circuits <NUM>, <NUM>, <NUM> are provided in a pulse merge circuit <NUM> that generates, and merges transition pulses representative of transitions detected in the difference signals <NUM>, <NUM>, <NUM>. <FIG> is a timing diagram <NUM> that illustrates timing associated with the pulse merge circuit <NUM> and the CDR circuit <NUM>.

The pulse merge circuit <NUM> receives difference signals <NUM>, <NUM>, <NUM> that represent differences in signaling state of pairs of wires the trio of wires A, B and C. The difference signals <NUM>, <NUM>, <NUM> are received from differential receivers or comparators such as differential receivers 802a, 802b and 802c that produce the difference signals 810a, 810b, 810c illustrated in <FIG>. The pulse merge circuit <NUM> uses three exclusive-OR gates <NUM>, <NUM>, <NUM> and corresponding delay circuits <NUM>, <NUM> and <NUM> to generate transition pulses <NUM>, <NUM>, <NUM> in response to transitions occurring in the difference signals <NUM>, <NUM>, <NUM>. In the example of the illustrated timing diagram <NUM>, a transition in the AB difference signal <NUM>, the BC difference signal <NUM> and the CA difference signal <NUM> occurs at the each of the illustrated symbol boundaries 1910a, 1910b, 1910c, 1910d.

The transitions in the difference signals <NUM>, <NUM>, <NUM> can occur at different times, such that a timing skew <NUM> can be observed between the first-occurring transition and the last-occurring transition. In the illustrated example, the first-occurring transition is observed at the first illustrated symbol boundary 1910a on the AB difference signal <NUM> and the last-occurring transition at the first illustrated symbol boundary 1910a is observed on the CA difference signal <NUM>. The relationship between transitions can be different at each symbol boundary 1910a, 1910b, 1910c, 1910d. In operation, a transition may not occur on one of the difference signals <NUM>, <NUM>, <NUM> at one or more symbol boundaries 1910a, 1910b, 1910c, 1910d.

A first exclusive-OR gate <NUM> receives the AB difference signal <NUM> and a delayed version of the AB difference signal <NUM> provided by the AB-delay circuit <NUM>, and provides an AB_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the AB-delay circuit <NUM>. A second exclusive-OR gate <NUM> receives the BC difference signal <NUM> and a delayed version of the BC difference signal <NUM> provided by the BC-delay circuit <NUM>, and provides a BC_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the BC-delay circuit <NUM>. A third exclusive-OR gate <NUM> receives the CA difference signal <NUM> and a delayed version of the CA difference signal <NUM> provided by the CA-delay circuit <NUM>, and provides a CA_p signal <NUM> that includes a pulse <NUM> that has a duration controlled by the duration of delay introduced by the CA-delay circuit <NUM>. The AB_p signal <NUM>, the BC_p signal <NUM> and the CA_p signal <NUM> are provided to an OR-gate <NUM> that provides an eg_pulse signal <NUM>.

Each of the delay circuits <NUM>, <NUM>, <NUM> may be configured and/or calibrated to provide a delay that exceeds the duration of the timing skew <NUM> measured with respect to a corresponding difference signal <NUM>, <NUM>, <NUM>. For example, the duration of the delay provided by the AB-delay circuit <NUM> may be configured or adjusted to exceed the duration of the timing skew <NUM> between transitions in the AB difference signal <NUM> and transitions in the BC difference signal <NUM> and/or the CA difference signal <NUM>. The resultant pulses <NUM>, <NUM> and/or <NUM> overlap such that the OR-gate <NUM> provides a combined pulse <NUM> in the eg_pulse signal <NUM> for each symbol boundary 1910a, 1910b, 1910c, 1910d. The delay circuits <NUM>, <NUM>, <NUM> may be reconfigured and/or recalibrated to accommodate timing and other variations associated with variances in PVT conditions.

The eg_pulse signal <NUM> clocks a delay flipflop (DFF <NUM>) in the CDR circuit <NUM>. Each rising edge in the eg_pulse signal <NUM> clocks an inverted version (rclk_inv signal <NUM>) of the half-rate symbol clock signal <NUM> (rclk) from the D input through to the output (Q) of the DFF <NUM>. The output of the DFF <NUM> provides the half-rate symbol clock signal <NUM>. The delay circuits <NUM>, <NUM> and <NUM> may be configured to provide pulses <NUM>, <NUM>, <NUM> that have a minimum duration that is sufficient to exceed the duration of the skew <NUM> for expected or measured PVT conditions.

The CDR circuit <NUM> is configured to provide a half-rate symbol clock signal <NUM> that changes state at each symbol boundary 1910a, 1910b, 1910c, 1910d. For example, the rclk_inv signal <NUM> is in the logic <NUM> state at the first symbol boundary 1910a, while the half-rate symbol clock signal <NUM> is at the logic <NUM> state. The rising edge of the combined pulse <NUM> in the eg_pulse signal <NUM> clocks the logic <NUM> level through to the Q output of the DFF <NUM>, causing the half-rate symbol clock signal <NUM> to transition to the logic <NUM> state. The inverter <NUM> generates the rclk_inv signal <NUM> from the half-rate symbol clock signal <NUM> with minimal delay.

The delay mask used to accommodate skew between difference signals <NUM>, <NUM>, <NUM> is provided in the pulse merge circuit <NUM>, and is external to the CDR circuit <NUM>. Accordingly, the CDR circuit <NUM> is effectively an open-loop circuit that can switch very quickly in response to an edge in a signal provided to its clock signal. The maximum frequency of operation of the CDR circuit <NUM> and the corresponding minimum UI may be determined by the timing constraints: <MAT> and <MAT> where dly represents the duration of the maximum delay provided by the delay circuits <NUM>, <NUM> and <NUM>.

The CDR circuit <NUM> may include or be coupled to one or more circuits used to decode data encoded in the signals transmitted over a three wire bus in accordance with C-PHY protocols. For example, the half-rate symbol clock signal <NUM> may be used to control the capture of symbols representative of the three difference signals <NUM>, <NUM>, <NUM> at each symbol boundary 1910a, 1910b, 1910c, 1910d. In one example, raw symbols that define the state of the three difference signals <NUM>, <NUM>, <NUM> may be captured. In another example, FRP symbols may be generated and captured based on the state of the three difference signals <NUM>, <NUM>, <NUM>.

In the illustrated example, the CDR circuit <NUM> includes timing circuits that may be used to delay or otherwise align the difference signals <NUM>, <NUM>, <NUM> to enable capture at an edge of the half-rate symbol clock signal <NUM> or a derivative of the half-rate symbol clock signal <NUM>. Aligned difference signals may be used to generate a symbol stream <NUM> of three-bit raw symbols to a set of registers <NUM> that are configured to capture the raw symbols from the symbol stream <NUM> on both the rising edge and falling edge of the half-rate symbol clock signal <NUM>. In one example, the set of registers <NUM> may include first registers that capture symbols from the symbol stream <NUM> based on timing derived from rising edges in the half-rate symbol clock signal <NUM> and second registers that capture symbols from the symbol stream <NUM> based on timing derived from rising edges in the rclk_inv signal <NUM>. The set of registers <NUM> may include one or more <NUM>-bit shift registers and/or may be organized as a first-in, first-out (FIFO) buffer that provides a sequence of symbols <NUM> that have been assembled from different registers in the set of registers <NUM>.

<FIG> illustrates an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM> that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit <NUM>. The processing circuit <NUM> may include certain devices, circuits, and/or logic that support clock recovery techniques disclosed herein.

The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. In one example, the bus <NUM> links together various circuits including the one or more processors <NUM> and a processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers <NUM>. A transceiver <NUM> may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver <NUM>. Each transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus <NUM>, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

A processor <NUM> may be responsible for managing the bus <NUM> and for general processing that may include the execution of software stored in a computer-readable medium, which may include the processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may be used for storing data that is manipulated by the processor <NUM> when executing software, and the software may be configured to implement any one of the methods disclosed herein.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the processor-readable storage medium <NUM> or in another external processor-readable medium. The processor-readable storage medium <NUM> may include a non-transitory computer-readable medium. A non-transitory processor-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), a random access memory (RAM), a ROM, a PROM, an erasable PROM (EPROM), an EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The processor-readable storage medium <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The processor-readable storage medium <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The processor-readable storage medium <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The processor-readable storage medium <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM>, and may manage access to external devices such as the transceiver <NUM>, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to the transceiver <NUM>, the user interface <NUM>, and so on.

<FIG> is a flowchart <NUM> of a clock recovery method that may be implemented at a receiving device coupled to a <NUM>-wire C-PHY interface. At block <NUM>, the receiving device generates a combination signal that includes one or more transition pulses. Each transition pulse is generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. At block <NUM>, the receiving device may provide the combination signal to a delay flipflop that is configured to provide a clock signal as its output. The pulses in the combination signal cause the clock signal to be driven to a first state. At block <NUM>, the receiving device may provide a reset signal to the delay flipflop. The reset signal is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state when the reset signal transitions to the first state.

The receiving device may generate a transition pulse for a first difference signal by performing an exclusive OR-gate function on the first difference signal and a delayed version of the first difference signal. The receiving device may configure at least one pulse generating circuit to provide corresponding transition pulses with a duration based on a minimum clock pulse duration defined for the delay flipflop. The receiving device may calibrate at least one pulse generating circuit based on operating conditions of the three-wire bus. The receiving device may configure an asymmetric delay to provide a desired duration of delay applied to transitions to the first state. In one example, the asymmetric delay circuit is implemented as a rising-edge delay circuit configured to delay transitions from a low logic state to a high logic state. The rising-edge delay circuit may be further configured to pass transitions from the high logic state to the low logic state without added delay.

In various implementations, the clock signal may be provided to a wire state decoder configured to decode symbols from transitions in signaling state of the three-wire bus based on timing information provided in the clock signal.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. The processing circuit <NUM> typically has at least one processor <NUM> that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware modules, represented by the processor <NUM>, the modules or circuits <NUM>, <NUM> and <NUM>, difference receiver circuits <NUM> that generate difference signals <NUM> representative of differences in signaling state between different pairs of the connectors or wires <NUM> and the processor-readable storage medium <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processor <NUM> is responsible for general processing, including the execution of software stored on the processor-readable storage medium <NUM>. The software, when executed by the processor <NUM>, causes the processing circuit <NUM> to perform the various functions described supra for any particular apparatus. The processor-readable storage medium <NUM> may also be used for storing data that is manipulated by the processor <NUM> when executing software, including data decoded from symbols transmitted over the connectors or wires <NUM>, which may be configured as a C-PHY bus. The processing circuit <NUM> further includes at least one of the modules <NUM>, <NUM> and <NUM>. The modules <NUM>, <NUM> and <NUM> may be software modules running in the processor <NUM>, resident/stored in the processor-readable storage medium <NUM>, one or more hardware modules coupled to the processor <NUM>, or some combination thereof. The modules <NUM>, <NUM> and/or <NUM> may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus <NUM> may be configured for data communication in accordance with a C-PHY interface protocol. The apparatus <NUM> may include modules and/or circuits <NUM> configured to generate transition pulses responsive to transitions in signaling state of the difference signals <NUM>, modules and/or circuits <NUM> that are configured to generate a clock signal useable to decode symbols from transitions in signaling state of the three-wire bus, and configuration modules and/or circuits <NUM> for configuring delay durations used in generating the transition pulses and/or the receive clock.

In one example, the apparatus <NUM> has a plurality of pulse generating circuits, a first logic circuit and a delay flipflop. Each of the pulse generating circuits is configured to generate a transition pulse in response to a transition in a difference signal <NUM> that is representative of a difference in signaling state of a pair of wires in a three-wire bus. The first logic circuit is configured to provide a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses received from the plurality of pulse generating circuits. The delay flipflop responds to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

Each pulse generating circuit may have a delay circuit configured to provide a delayed difference signal by delaying one of three difference signals, and a second logic circuit configured to provide the transition pulse by performing an exclusive OR function on the one of three difference signals and the delayed difference signal. The delay circuit may be configured to provide a delay that exceeds a duration of a skew between two of the three difference signals. The delay circuit may be configurable to provide a delay that accommodates variations in PVT conditions. The transition pulse may have a configurable duration. The delay flipflop may receive an inverse of the clock signal as its input. In one example, a rising edge in the clock signal can be used to capture a first symbol from the three-wire bus and a rising edge in the inverse of the clock signal can be used to capture a second symbol from the three-wire bus. In another example, a falling edge in the clock signal can be used to capture a first symbol from the three-wire bus and a falling edge in the inverse of the clock signal can be used to capture a second symbol from the three-wire bus. In another example, a rising edge in the clock signal can be used to capture a first symbol from the three-wire bus and a falling edge in the clock signal can be used to capture a second symbol from the three-wire bus.

The processor-readable storage medium <NUM> may be a non-transitory storage medium and may store instructions and/or code that, when executed a processor <NUM>, cause the processing circuit <NUM> to generate a transition pulse in response to a transition in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus, provide a single pulse in a combination signal at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses generated at the each boundary between the pairs of sequentially-transmitted symbols, and clock a delay flipflop with the combination signal such that signaling state of a clock signal is changed in response to each pulse in the combination signal. Transitions in one or more difference signals can occur at boundaries between symbols that are sequentially transmitted over the three-wire bus.

In certain implementations, the instructions may cause the processing circuit <NUM> to provide a delayed difference signal by delaying one of three difference signals, and perform an exclusive OR function on the one of three difference signals and the delayed difference signal to obtain the transition pulse. The instructions may cause the processing circuit <NUM> to delay the one of three difference signals by a duration that exceeds a duration of a skew between two of the three difference signals. The instructions may cause the processing circuit <NUM> to delay the one of three difference signals by a duration that accommodates variations in PVT conditions. The transition pulse can have a configurable duration. The instructions may cause the processing circuit <NUM> to provide an inverse of the clock signal as an input to the delay flipflop, use a rising edge in the clock signal to capture a first symbol from the three-wire bus, and use a falling edge in the clock signal to capture a second symbol from the three-wire bus.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches.

Claim 1:
A clock recovery apparatus (<NUM>, <NUM>, <NUM>, <NUM>) comprising:
three pulse generating circuits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), each pulse generating circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) being configured to generate a transition pulse (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) in response to a transition in one of three difference signals (810a, <NUM>, <NUM>, <NUM>, <NUM>) representative of a difference in signaling state (<NUM>) of a pair of wires in a three-wire bus (<NUM>, <NUM>), wherein transitions (<NUM>) in one or more difference signals (810a, <NUM>, <NUM>, <NUM>, <NUM>) occur at boundaries between symbols (<NUM>) that are sequentially transmitted over the three-wire bus (<NUM>, <NUM>);
a first logic circuit (<NUM>, <NUM>) configured to provide a single pulse (<NUM>, <NUM>) in a combination signal (<NUM>, <NUM>) at each boundary between pairs of sequentially-transmitted symbols (<NUM>) by combining one or more transition pulses (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) received from the three pulse generating circuits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>); and
a delay flipflop (<NUM>, <NUM>) configured to respond to each single pulse (<NUM>, <NUM>) in the combination signal by changing signaling state of a clock signal (<NUM>, <NUM>) that is output by the clock recovery apparatus (<NUM>, <NUM>, <NUM>, <NUM>), wherein to respond to a first single pulse (<NUM>, <NUM>), the delay flipflop (<NUM>, <NUM>) is configured to change the signaling state from a logic <NUM> state to a logic <NUM> state, and in response to a second single pulse (<NUM>, <NUM>) consecutive to the first single pulse (<NUM>, <NUM>), the delay flipflop (<NUM>, <NUM>) is configured to change the signaling state from a logic <NUM> state to a logic <NUM> state.