Patent Description:
The present invention relates to the field of memory, in particular to a semiconductor device.

Dynamic Random Access Memory (DRAM) is a semiconductor storage device commonly used in computers, and its storage array region consists of many repeating storage cells. Each of the storage cells typically includes a capacitor and a transistor, wherein the gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source electrode is connected to the capacitor. The voltage signal over the word line can control ON/OFF of the transistor, and then data information stored in the capacitor is read through the bit line, or data information is written through the bit line to the capacitor for storage. The <CIT> discloses a method for determining the temperature of a semiconductor chip and semiconductor chip with temperature measuring configuration. The US patent document <CIT> discloses an energy adjusted write pulses in phase-change memory cells. The US <CIT> discloses a thermal event sensor.

Temperature has a great effect on memory write. In low temperature environments, in the case of writing to memory, there are problems of long writing time and low writing stability.

The technical problem to be solved by the present invention is to provide a semiconductor device that enables the activation of a temperature detection unit to be free from whether a storage chip is activated such that the detection of the temperature of the storage chip is not affected by whether a storage chip is activated.

In order to solve the above problem, the present invention provides a semiconductor device according to claim <NUM>. The dependent claims set out particular embodiments of the invention.

The present invention has the following advantages. The storage chip and the temperature detection unit use different power supplies, and thus, the activations of both of them can be controlled separately, i.e., the activation of the temperature detection unit is free from whether a storage chip is activated, so that the detection of the temperature of the storage chip is free from whether a storage chip is activated, thereby providing a reference for the activation and operation of the storage chip, and in turn avoiding the activation or operation of the storage chip under low temperatures and improving the stability of the storage chip.

Embodiments of the semiconductor device according to the present invention are detailed below in combination with drawings.

As described in the background of the invention, temperature has a great effect on memory write, and in low temperature environments, in the case of writing to memory, there are problems of long writing time and low writing stability.

Studies find out that, when existing memory operates in low temperature environments, the stability of memory write is affected since a temperature drop may cause increased resistances of the word line, bit line, metal connecting line (metal contacting portion), or the like in the memory, and the increased resistances may cause varied or extended time when data is written into memory.

Therefore, the present invention provides a semiconductor device with a temperature detection unit to detect the temperature of the storage chip so as to provide a reference for the activation and operation of the storage chip, thereby avoiding the activation and operation of the storage chip under low temperatures, shortening write time, and improving the stability of the storage chip write.

<FIG> is a schematic structural diagram of the first embodiment of the semiconductor device according to the present invention. Referring to <FIG>, the semiconductor device according to the present invention includes a storage chip <NUM> and a temperature detection unit <NUM>.

The storage chip <NUM> is an existing memory capable of performing data write, data read, and/or data deletion. The storage chip <NUM> is formed by the semiconductor integration fabricating process. Specifically, the storage chip <NUM> can include a storage array and peripheral circuits connected to the storage array. The storage array includes a plurality of storage cells and bit lines, word lines, and metal connecting lines (metal contacting portions) that are connected to the storage cells. The storage cells are configured to store data, and the peripheral circuits are related circuits when operations are performed on the storage arrays. In the present embodiment, the storage chip <NUM> is a DRAM storage chip, which includes a plurality of storage cells. The storage cell includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source electrode is connected to the capacitor. In other embodiments, as the storage chip <NUM>, other types of storage chips may be used.

The temperature detection unit <NUM> is configured to detect the temperature of the storage chip <NUM>. The temperature detection unit <NUM> includes a temperature sensor for sensing a temperature and converting the sensed temperature to an electric signal. The temperature sensor may be a PN junction diode temperature sensor or a capacitive temperature sensor.

The semiconductor device includes one or more storage chips <NUM> and one or more temperature detection units <NUM>. The temperature detection unit <NUM> may be configured to detect the temperature(s) of one or more storage chips <NUM>. The temperature detection unit <NUM> may be in one-to-one relationship or one-to-many relationship with the storage chip <NUM>.

When the number of the storage chip <NUM> is one, and the number of the temperature detection unit <NUM> is also one, the temperature detection unit <NUM> is in one-to-one relationship with the storage chip <NUM> and configured to merely detect the temperature of this storage chip <NUM>.

When the number of the storage chip <NUM> is more than one, and the number of the temperature detection unit <NUM> is one, the temperature detection unit <NUM> is in one-to-many relationship with the storage chip <NUM> and configured to detect the temperatures of the more than one storage chips <NUM>.

When the number of the storage chip <NUM> is more than one, and the number of the temperature detection unit <NUM> is also more than one, but the number of the temperature detection unit <NUM> is less than the number of the storage chip <NUM>, the temperature detection unit <NUM> and the storage chip <NUM> may have one-to-one relationship and one-to-many relationship simultaneously, or have one-to-many relationship only. That is, there may be the situation where one of the temperature detection units <NUM> detects one storage chip <NUM> only and one temperature detection unit <NUM> detects more than one of the storage chips <NUM>, or only the situation where one temperature detection unit <NUM> detects more than one of the storage chips <NUM>.

When the number of the storage chip <NUM> is more than one, the number of the temperature detection unit <NUM> is also more than one, and the number of the temperature detection unit <NUM> equals to the number of the storage chip <NUM>, the temperature detection unit <NUM> is in one-to-one relationship with the storage chip <NUM>, and one temperature detection unit <NUM> is configured to detect the temperature of one of the storage chips <NUM>.

In the present embodiment, the semiconductor device includes a plurality of storage chips <NUM> disposed as a stack and a plurality of temperature detection unit <NUM> one-to-one corresponding to the storage chips <NUM>. Four storage chips <NUM> and four temperature detection units <NUM> are schematically depicted in <FIG>.

The temperature detection units <NUM> and the storage chips <NUM> are powered by different power supplies. <FIG> is a schematic diagram of the circuit connections of the first embodiment of the semiconductor device according to the present invention. Referring to <FIG>, the temperature detection unit <NUM> is powered by a power supply Vtemp, and the storage chip <NUM> is powered by VDD. Since the temperature detection unit <NUM> and the storage chip <NUM> are powered by different power supplies, the power supplied to the temperature detection unit <NUM> and the power supplied to the storage chip <NUM> can be controlled independently, thereby enabling the temperature detection unit <NUM> to be activated at a different time from the storage chip <NUM>.

As described above, temperature has a great influence on the performance of the storage chip <NUM>, especially when the storage chip <NUM> is activated. If the storage chip <NUM> is activated under low temperatures, the time of writing data into the storage chip <NUM> may vary or extend, affecting the stability of the storage chip <NUM>. Therefore, the temperature of the storage chip is required to be measured before the activation of the storage chip <NUM> such that the storage chip <NUM> can be activated within a suitable temperature.

Therefore, in the present invention, the power supplied to the temperature detection unit <NUM> is earlier than the power supplied to the storage chip <NUM>, i.e., before the storage chip <NUM> is activated, the temperature detection unit <NUM> has been activated, and thus, the temperature prior to the activation of the storage chip <NUM> can be acquired so as to provide a reference for the activation of the storage chip <NUM>. <FIG> is a timing diagram of supplying power to the temperature detection unit <NUM> and the storage chip <NUM>. Referring to <FIG>, after power is supplied to the temperature detection unit <NUM> for time T, power is supplied to the storage chip <NUM>. The time may be a preset time, or the time taken by the temperature of the storage chip <NUM> to reach a set threshold temperature.

Further, referring to <FIG>, the temperature detection unit <NUM> and the storage chip <NUM> share the same grounding terminal VSS. The advantage thereof is as follows. On one hand, the leakage current of the non-activated phase of the storage chip <NUM> will not increase, and on the other hand, the number of the pins will reduce, thereby saving space.

In the present embodiment, the semiconductor device further includes a control chip <NUM>. The storage chip <NUM> and the temperature detection unit <NUM> are electrically connected to the control chip <NUM>. The control chip <NUM> is configured to control the activation and operation of the storage chip <NUM> and the temperature detection unit <NUM>. The grounding terminal VSS, the power supply VDD and the power supply Vtemp are provided by the control chip <NUM>. The activation of the storage chip <NUM> includes power up and self-check, and the operation of the storage chip <NUM> includes writing data to the storage chip <NUM>, reading data from the storage chip <NUM>, and deleting the accessed data in the storage chip <NUM>, or the like. A plurality of storage chips <NUM> are stacked on the control chip <NUM>, which bonds with the storage chip <NUM> at the bottommost layer of the stack structure. However, in another embodiment of the present invention, when only one storage chip <NUM> is provided, this storage chip <NUM> is disposed on and bonds with the control chip <NUM>.

The storage chip <NUM> has a through-silicon-via interconnecting structure <NUM> formed therein. With the through-silicon-via interconnecting structure <NUM>, the storage chip <NUM> is electrically connected to the control chip <NUM>, and the temperature detection unit <NUM> is electrically connected to the control chip <NUM>. That is, with the through-silicon-via interconnecting structure <NUM>, the storage chip <NUM> is electrically connected to the grounding terminal VSS and the power supply VDD, and the temperature detection unit <NUM> is electrically connected to the power supply Vtemp and the grounding terminal VSS. Specifically, in the present embodiment, when the plurality of the storage chips <NUM> are stacked, each of the storage chips <NUM> may be connected to the control chip <NUM> through different through-silicon-via interconnecting structures; when a plurality of the temperature detection units <NUM> is provided, there may be the situation where each of the temperature detection units <NUM> is connected to the control chip <NUM> through through-silicon-via interconnecting structures, and also the situation where the plurality of the temperature detection units <NUM> share the through-silicon-via interconnecting structure so as to connect to the control chip <NUM>. It can be understood that the storage chip <NUM> and the temperature detection units <NUM> are connected to the control chip <NUM> through different through-silicon-via interconnecting structures such that the temperature detection units <NUM> and the storage chip <NUM> can be powered by different power supplies. Further, the power supplying of the plurality of the temperature detection units <NUM> may also share the technology of through-silicon-via interconnecting structure.

In other embodiments, the storage chip <NUM> and the temperature detection unit may also electrically connect to the control chip <NUM> by metal leads (formed by the lead bonding process).

Further, the temperature detection unit <NUM> may be formed in the storage chip <NUM> by the semiconductor integration fabricating process. In the case of merely detecting the temperature of one storage chip <NUM>, the temperature detection unit <NUM> may be formed in this storage chip <NUM>. For example, in the present embodiment, as shown in <FIG>, the temperature detection units <NUM> are one-to-one corresponding to the storage chips <NUM>, and each storage chip <NUM> is provided with one temperature detection unit <NUM> therein. In the case of detecting the temperatures of a plurality of the storage chips <NUM>, the temperature detection unit <NUM> may be formed in any one of the plurality of the storage chips <NUM> or in the storage chip <NUM> at the centered or bottommost layer. For example, in the second embodiment of the present invention, referring to <FIG> which is a schematic structural diagram of the second embodiment of the semiconductor device according to the present invention, the temperature detection unit <NUM> is disposed in the storage chip <NUM> at the bottommost layer and capable of measuring the temperatures of four storage chips <NUM>.

In another embodiment of the present invention, the temperature detection unit <NUM> is disposed in the control chip <NUM> rather than a storage chip <NUM>. Specifically, referring to <FIG> which is a schematic structural diagram of the third embodiment of the semiconductor device according to the present invention, the temperature detection unit <NUM> is disposed in the control chip <NUM> and capable of measuring the temperatures of four storage chips <NUM> stacked on the control chip <NUM>.

In another embodiment of the present invention, referring to <FIG> which is a schematic structural diagram of the fourth embodiment of the semiconductor device according to the present invention, the semiconductor device further includes a wiring substrate <NUM> having connection lines (not depicted in the drawing) provided therein, wherein both of the storage chip <NUM> and the control chip <NUM> are located on the wiring substrate <NUM>, and the storage chip <NUM> and the control chip <NUM> are electrically connected through the connection lines in the wiring substrate <NUM>. In this embodiment, the temperature detection unit <NUM> is also disposed on the wiring substrate <NUM> and configured to measure the ambient temperature. This ambient temperature is close to the temperature of the storage chip <NUM> and may be approximately as the temperature of the storage chip <NUM>. The wiring substrate <NUM> includes, but not limited to, a PCB circuit board. It can be understood that, in other embodiments of the present invention, the temperature detection unit <NUM> may not be disposed on the wiring substrate <NUM>, and is disposed in the storage chip <NUM> or the control chip <NUM>, as shown in <FIG>, <FIG> and <FIG>.

In the semiconductor device according to the present invention, the storage chip and the temperature detection unit use different power supplies, and thus, the activations of both of them can be controlled separately, i.e., the activation of the temperature detection unit is free from whether a storage chip is activated, so that the detection of the temperature of the storage chip is free from whether a storage chip is activated, thereby providing a reference for the activation and operation of the storage chip, and in turn avoiding the activation or operation of the storage chip under low temperatures and improving the stability of the storage chip.

When the storage chip <NUM> is in a low temperature environment, if the storage chip <NUM> is heated, then the temperature thereof increases quickly, thereby expediting the activation of the storage chip <NUM>. Therefore, the control chip <NUM> according to the present invention can further be activated prior to the activation of the storage chip <NUM>, and the control chip <NUM> heats the storage chip <NUM> by heat generated itself after activation so as to raise the temperature of the storage chip <NUM> quickly.

After being activated, the control chip <NUM> controls the activation of the temperature detection unit <NUM> so as to detect the temperature of the storage chip <NUM>. The temperature detection unit <NUM> can further transmit the detected temperature to the control chip <NUM> as the data of the control chip <NUM>.

The control chip <NUM> can judge whether a temperature detected by the temperature detection unit <NUM> reaches a set threshold, and control the activation of the storage chip <NUM> if the set threshold is reached. The control chip can control the activation of the storage chip by supplying power to the storage chip.

If only one temperature detection unit <NUM> and one storage chip <NUM> are provided, and the one temperature detection unit <NUM> is configured to merely detect the temperature of one storage chip <NUM>, when the control chip <NUM> judges that the temperature detected by this temperature detection unit <NUM> reaches a set threshold, then the control chip <NUM> controls the activation of this storage chip <NUM>.

If one temperature detection unit <NUM> and a plurality of storage chips <NUM> are provided, and the one temperature detection unit <NUM> is configured to detect the temperatures of the plurality of storage chips <NUM>, when the control chip <NUM> judges that the temperature detected by this temperature detection unit <NUM> reaches a set threshold, then the control chip <NUM> first controls the activation of the storage chip <NUM> closest to the control chip <NUM>, and then controls the subsequent activations of other storage chips <NUM> above.

If a plurality of temperature detection units <NUM> and a plurality of storage chips <NUM> are provided, there may be the situation where one of the temperature detection units <NUM> merely detects one storage chip <NUM> and one temperature detection unit <NUM> detects a plurality of the storage chips <NUM>, or only the situation where one temperature detection unit <NUM> detects a plurality of the storage chips <NUM>. When the control chip <NUM> judges that the temperature detected by a certain temperature detection unit <NUM> reaches a set threshold, the control chip <NUM> controls the activation of the storage chip <NUM> corresponding to this temperature detection unit <NUM>, and if this temperature detection unit <NUM> detects the temperatures of a plurality of the storage chips <NUM>, then the control chip <NUM> first controls the activation of the storage chip <NUM> closest to the control chip <NUM>, and then controls the subsequent activations of other storage chips <NUM> above.

If a plurality of temperature detection units <NUM> and a plurality of storage chips <NUM> are provided, and the plurality of temperature detection units <NUM> are one-to-one corresponding to the plurality of storage chips <NUM>, when the control chip <NUM> judges that the temperature detected by a certain temperature detection unit <NUM> reaches a set threshold, the control chip <NUM> controls the activation of the storage chip <NUM> corresponding to this temperature detection unit <NUM>. Specifically, there are four storage chips <NUM> in the stack structure as shown in <FIG>, each of the storage chips <NUM> has one temperature detection unit <NUM> correspondingly, and thus, each of the temperature detection units <NUM> detects the temperature of the corresponding storage chip <NUM>, obtaining four detection values of temperature. The control chip <NUM> sequentially judges whether the temperatures detected by the four of the temperature detection units <NUM> reach a set threshold, and if a temperature detected by a certain temperature detection unit <NUM> reaches the set threshold, then the control chip <NUM> controls the activation of the storage chip corresponding to this temperature detection unit <NUM>. For example, if the temperature detected by the temperature detection unit <NUM> in the storage chip <NUM> at the bottommost layer of the stack structure first reaches the set threshold, then the control chip <NUM> first controls the activation of the storage chip <NUM> at the bottommost layer of the stack structure; next, if the temperature detected by the corresponding temperature detection unit <NUM> in the storage chip <NUM> at the last but one layer of the stack structure also reaches the set threshold, the control chip <NUM> then controls the activation of the storage chip <NUM> at the last but one layer of the stack structure; the activation of the storage chips <NUM> at the two layers above are performed similarly.

For the semiconductor device having a plurality of storage chips <NUM>, such aforementioned control structure and control manner further improve the precision of the activation timing of each storage chip <NUM>, further shorten the write time when data is written to each storage chip <NUM> in a low temperature environment, and further improves the stability of writing to each storage chip <NUM>.

When the semiconductor device according to the present invention operates in a low temperature environment, the temperature of the storage chip <NUM> can be raised to the set threshold by the control chip <NUM>, preventing the increased resistances of the word line, bit line and metal connecting line (metal contacting portion) in the storage chip <NUM> due to the excessive low ambient temperature, thereby shortening the write time when data is written into the storage chip in a low temperature environment and improving the stability of writing to the storage chip. The set threshold may be set in the control chip <NUM>, and the specific magnitude of the set threshold may be set as needed or based on experience.

Claim 1:
A semiconductor device, comprising a storage chip (<NUM>), a temperature detection unit, a control chip (<NUM>), a first power supply (Vtemp), and a second power supply (VDD),
wherein the temperature detection unit (<NUM>) is configured to detect the temperature of the storage chip (<NUM>), and the control chip (<NUM>) is configured to heat the storage chip prior to the activation of the storage chip; wherein the temperature detection unit (<NUM>) being powered by the first power supply (Vtemp), and the storage chip (<NUM>) being powered by the second power supply (VDD); and
wherein the semiconductor device is configured to supply power to the temperature detection unit before supplying power to the storage chip (<NUM>).