Patent Description:
Semiconductor devices in chip size package (CSP) include a through silicon via (TSV) that connects a wiring layer in a package and a connecting terminal on a mounting board (for example, refer to Patent Literature <NUM>).

When a TSV is formed, generally, a through hole that reaches a wiring layer inside a package is formed from a rear surface of a board first, and then the through hole is covered with a seed metal film. Thereafter, on a surface of the seed metal film, a Re distribution layer (RDL) film, such as copper film, is grown, for example, by electroplating or the like to form the TSV.

Further semiconductor devices are known from <CIT>, <CIT>, <CIT>, <CIT>, <CIT>, and <CIT>.

However, in the conventional technique described above, a step disconnection can occur in a seed metal film, and the RDL film cannot grow normally at a step disconnection portion of the seed metal film, to cause a faulty connection in TSV. This can reduce yields of semiconductor devices.

In view of the above problems, the present disclosure proposes a semiconductor device that can suppress reduction of yields.

The above objects are solved by the claimed matter according to the independent claims.

A semiconductor device according to the present disclosure includes a board and a via. In the board, a wiring layer is embedded. The via extends in a depth direction from a main surface of the board to pierce through the wiring layer, and is connected to the wiring layer on a side peripheral surface. According to the present invention, the via comprises a vertical portion and a bottom portion in a tapered shape smoothly continuing from the vertical portion. Embodiments described herein that do not have this feature, notably the embodiments in <FIG>, <FIG>, <FIG>, <FIG> and corresponding text in the description, are not part of the claimed invention and are provided merely as additional information.

Hereinafter, an embodiment of the present disclosure will be explained in detail with reference to the drawings. In the following embodiment, like reference signs are assigned to like parts, and duplicated explanation will be thereby omitted.

First, a structure of a semiconductor device <NUM> according to the present disclosure will be explained, referring to <FIG> is an explanatory diagram illustrating a cross-section of the semiconductor device <NUM> according to an embodiment of the present disclosure. It will be explained herein with a case in which the semiconductor device <NUM> according to the embodiment is a chip size package (CSP) stacked image sensor as an example, but the semiconductor device according to the embodiment may be any semiconductor device having a through silicon via (TSV).

As illustrated in <FIG>, the semiconductor device <NUM> is used mounted on a mounting board <NUM>. The semiconductor device <NUM> includes, for example, a logic board <NUM>, and a sensor board <NUM> that is laminated on the logic board <NUM>.

The logic board <NUM> includes Si (silicon) substrate <NUM> and an insulation layer <NUM> that is formed with SiO (silicon monoxide) laminated on the Si substrate <NUM> or the like. Inside the insulation layer <NUM>, a multi-layered wiring layer <NUM> is embedded. Although illustration is omitted, inside the insulation layer <NUM>, a signal processing circuit, a memory, or the like are arranged other than the multi-layered wiring layer <NUM>.

The sensor board <NUM> includes an Si substrate <NUM>, a glass cover <NUM> that is arranged on the Si substrate <NUM>, and a supporting member <NUM> that supports a periphery portion of the glass cover <NUM>. Inside the Si substrate <NUM>, for example, a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor <NUM> is arranged. Moreover, on a light receiving surface of each of a plurality of light receiving devices included in the CMOS image sensor <NUM>, a micro lens <NUM> is arranged.

Furthermore, the CSP semiconductor device <NUM> includes a TSV <NUM> to connect the multi-layered wiring layer <NUM> arranged inside the logic board <NUM> and a connecting terminal <NUM> arranged on the mounting board <NUM>.

The TSV <NUM> is a kind of a through electrode that is formed by making a redistribution layer (RDL) film <NUM> of, for example, a copper film, or the like so as to extend from an inner peripheral surface of a through hole formed from a bottom surface of the logic board <NUM> to reach the multi-layered wiring layer <NUM>, to a part of the bottom surface of the logic board <NUM>.

The semiconductor device <NUM> is mounted on the mounting board <NUM> as a portion of the RDL film <NUM> extending to the bottom surface of the logic board <NUM> is connected to the connecting terminal <NUM> through a solder bump <NUM>.

As described, in the CSP semiconductor device <NUM>, the RDL film <NUM> of the TSV <NUM> is directly connected with the connecting terminal <NUM> of the mounting board <NUM> through the solder bump <NUM> without using a bonding wire and, therefore, a mounting area can be suppressed to be minimum.

In the present embodiment, by contriving the shape of the TSV <NUM>, occurrence of faulty connection in the TSV <NUM> is suppressed, and the yields of the semiconductor device <NUM> is thereby improved. Next, a specific structure of the TSV <NUM> will be explained, referring to <FIG>.

<FIG> is an explanatory diagram illustrating a cross-section of the TSV <NUM> according to the embodiment of the present disclosure. <FIG> selectively illustrates a portion near the TSV <NUM> in the logic board <NUM> out of components of the semiconductor device <NUM>, and illustration of the sensor board <NUM> is omitted.

Moreover, in <FIG>, the logic board <NUM> in a state in which the logic board <NUM> in <FIG> is reversed vertically is illustrated. Therefore, in the following, it is explained referring a bottom surface side of the logic board <NUM> in <FIG> as upward, and a top surface side of the logic board <NUM> as downward.

As illustrated in <FIG>, the TSV <NUM> extends in a depth direction from the top surface of the logic board <NUM>, and pierces through a first wiring layer M1 that is the upper most layer among the first wiring layer M1, a second wiring layer M2, and a third wiring layer M3 in the multi-layered wiring layer <NUM>, and is connected to the first wiring layer M1 on a side peripheral surface.

The TSV <NUM> is formed by forming a seed metal film <NUM> and an RDL film sequentially on a surface of a through hole <NUM> that reaches such a depth that pierces through the first wiring layer M1 from a top surface of the Si substrate <NUM>.

Between the Si substrate <NUM> and the seed metal film <NUM>, an SiO film <NUM> is arranged in advance for insulation purposes. A specific formation process of the TSV <NUM> will be described later with reference to <FIG>.

Before forming the seed metal film <NUM> and the RDL film <NUM>, it is necessary to etch the insulation layer <NUM> and the first wiring layer M1 in a process of forming the through hole <NUM> that reaches the depth to pierce through the first wiring layer M1 from the top surface of the logic board <NUM>.

Therefore, the process of forming the through hole <NUM>, the through hole <NUM> is formed by reactive ion etching (RIE) using an etching gas in which an etching gas suitable for etching of the insulation layer <NUM> and an etching gas suitable for etching of the first wiring layer M1 are mixed.

In the RIE, the etching proceeds toward the direction of depth of the logic board <NUM>, but does not proceed toward a surface direction of the insulation layer <NUM>. Therefore, a diameter of the through hole <NUM> in the insulation layer <NUM> is not to be larger than a diameter of the through hole <NUM> in the Si substrate <NUM>.

Thus, occurrence of a step disconnection in the seed metal film <NUM> formed after the through hole <NUM> is formed is suppressed, and thereby enabling to form the RDL film <NUM> on the entire surface of the seed metal film <NUM> without a step disconnection.

On the other hand, general TSVs have a depth only reaching the top surface of the first wiring layer M1 from the top surface of the Si substrate <NUM>, and is connected to the top surface of the first wiring layer M1 at the bottom surface. When forming such a general TSV, the first wiring layer M1 is used as an etching stopper, and a through hole having a depth reaching the top surface of the first wiring layer M1 from the top surface of the Si substrate <NUM> is formed by RIE.

In this RIE, an etching gas suitable for the insulation layer <NUM> is used, but an etching gas suitable for the first wiring layer M1 is not used. Therefore, when over-etching to completely expose the top surface of the first wiring layer M1 is performed, while etching in the depth direction stops at the top surface of the first wiring layer M1, etching in a surface direction in the insulation layer <NUM> continues to proceed.

As a result, the diameter of the through hole <NUM> in the insulation layer <NUM> becomes larger than the diameter of the through hole <NUM> in the Si substrate <NUM>, and a notch (slit or cutout) is formed at a bottom portion of the through hole <NUM>. When the seed metal film <NUM> is formed on a surface of this through hole <NUM>, a step disconnection is generated in the seed metal film <NUM> at the notch portion at the bottom portion of the through hole <NUM>, and the RDL film <NUM> that entirely covers the through hole <NUM> cannot be formed, resulting in causing a faulty connection in the TSV, to reduce the yields of semiconductor devices.

On the other hand, in the TSV <NUM> according to the embodiment, because the RDL film <NUM> is formed on the entire surface of the seed metal film <NUM> without step disconnection as described above, occurrence of a faulty connection in the TSV <NUM> can be suppressed, and the yields of the semiconductor device <NUM> can be improved.

Moreover, as illustrated in <FIG>, in the TSV <NUM> according to the embodiment, a bottom portion has a tapered shape smoothly continuing from a vertical hole portion of the through hole <NUM>, specifically, a bowl shape. Thus, according to the present embodiment, the step disconnection of the seed metal film <NUM> can be prevented more certainly and, therefore, occurrence of a faulty connection in the TSV <NUM> can be suppressed, to improve the yields of the semiconductor device <NUM>.

Furthermore, because the TSV <NUM> according to the embodiment has the bottom portion in a bowl shape, a joint surface with the first wiring layer M1 is to be an inclined plane. Thus, the TSV <NUM> can provide a larger junction area with respect to the first wiring layer M1, compared to such a shape that the bottom portion is horizontal and completely pierce through the first wiring layer M1 to make the joint surface with respect to the first wiring layer M1 perpendicular thereto and, therefore, a junction resistance can be reduced.

Next, a formation process of the TSV <NUM> according to the embodiment will be explained with reference to <FIG>. When the TSV <NUM> is formed, first, a resist <NUM> is applied to the top surface of the Si substrate <NUM>, and then patterning is performed on the resist <NUM> by photolithography to selectively remove the resist <NUM> at a portion at which the TSV <NUM> is formed as illustrated in <FIG>.

At this time, for example, a hole in a substantially circular shape in planar view having a diameter of about <NUM> is formed in the resist <NUM>. Subsequently, as illustrated in <FIG>, using the resist <NUM> as a mask, the through hole <NUM> is formed in the Si substrate <NUM> by performing dry etching, for example, RIE or the like.

In this etching, a chlorine-based or fluorine based etching gas that is suitable for Si (silicon) etching is used. Thus, a portion that is not masked by the resist <NUM> in the Si substrate <NUM> is etched in a depth direction by about <NUM>, to expose a top surface of the insulation layer <NUM>.

Thereafter, as illustrated in <FIG>, the resist <NUM> is removed from the top surface of the Si substrate <NUM>. Subsequently, as illustrated in <FIG>, to insulate between the Si substrate <NUM> and the RDL film <NUM> to be formed later, the SiO film <NUM> is formed, for example, by chemical vapor deposition (CVD) on the top surface of the Si substrate <NUM>, and the bottom surface and the side peripheral surface of the through hole <NUM>.

At this time, on the top surface of the Si substrate <NUM>, the SiO film <NUM> having a thickness of about <NUM> is formed, and on the bottom surface and the side peripheral surface of the through hole <NUM>, the SiO film <NUM> having a thickness of about <NUM> is formed. Thereafter, dry etching, for example, RIE or the like is performed on the entire surface of the SiO film <NUM>.

In this etching, a fluorine-based etching gas that is suitable for etching of an insulation film and a chlorine-based etching gas that is suitable for metallic system etching are used. Furthermore, in this process, a fluorine carbide-based or hydro carbon-based gas that functions as a depot gas to suppress progress of etching in a horizontal direction is mixed to the etching gas to perform etching.

Thus, as illustrated in <FIG>, the SiO film <NUM> formed on the bottom portion of the through hole <NUM>, the insulation layer <NUM>, and the first wiring layer M1 are sequentially etched, and the through hole <NUM> reaches the depth to pierce through the first wiring layer M1.

In the final phase of the etching, an amount of the etching gas is gradually decreased, while the depot gas is increased. This enables to avoid the etching from proceeding in the horizontal directions indicated by outlined arrows in <FIG>, and to make the bottom portion of the through hole <NUM> into a bowl shape. As described, the through hole <NUM> according to the present embodiment is formed such that the shape of the bottom portion becomes a bowl shape smoothly continuing from the vertical hole portion, without a notch formed in the bottom portion.

Thereafter, a depot film deposited on the surface of the through hole <NUM> is removed by an organic solution. Subsequently, a thin film of Ti (titanium), Cu (copper), or Ti (titanium) and Cu (copper) having a film thickness of <NUM> to <NUM> is formed by spattering on the bottom surface of the through hole <NUM>, a side surface of the through hole <NUM>, and the entire top surface of the SiO film <NUM>, to form the seed metal film <NUM>.

Finally, on the surface of the seed metal film <NUM>, the RDL film <NUM> is formed by growing a Cu (copper) film having a film thickness of about <NUM> by electroplating, to thereby form the TSV <NUM> illustrated in <FIG>. In the process of forming the RDL film <NUM>, a portion other than a portion at which the RDL film <NUM> is formed is masked with a resist before performing the electroplating.

After formation of the RDL film <NUM>, the resist is removed. At this time, if a notch is present at the bottom portion of the through hole <NUM>, a residue of the resist remains in the notch, to be a cause of a crack in the RDL film <NUM>. However, as described above, a notch is not formed in the bottom portion of the through hole <NUM> in the present embodiment. Thus, the TSV <NUM> according to the embodiment can suppress occurrence of a crack in the RDL film <NUM> and, therefore, can prevent the occurrence of a faulty connection.

Note that the shape of the TSV <NUM> illustrated in <FIG> is one example of the TSV according to the embodiment. The TSV according to the embodiment allows various modifications other than the shape illustrated in <FIG>. In the following, the shape of the TSV according to modifications of the embodiment will be explained with reference to <FIG>.

<FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a first modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a second modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a third modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a fourth modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a fifth modification of the embodiment.

Moreover, <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a sixth modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a seventh modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to an eighth modification of the embodiment. <FIG> is an explanatory diagram illustrating a cross-section of a TSV according to a ninth modification of the embodiment.

As illustrated in <FIG>, the TSV according to the first modification differs from the TSV <NUM> illustrated in <FIG> in only the shape of the bottom portion, and the bottom portion has a conical shape that becomes thinner as it goes deeper. The conical-shaped bottom portion can be formed by performing ratio adjustment in amount of the etching gas to an amount of the depot gas in the final phase of the etching to form the through hole <NUM>.

The TSV according to the first modification reaches the depth to pierce through the first wiring layer M1 similarly to the TSV <NUM> illustrated in <FIG>, and is connected to the first wiring layer M1 on the side peripheral surface. The TSV is formed without using the first wiring layer M1 as an etching stopper.

Therefore, because a notch is not formed at the bottom portion in the TSV according to the first modification, occurrence of a faulty connection in the RDL film <NUM> is suppressed, and the yields of semiconductor devices can be thereby improved.

Moreover, in the TSV according to the first modification, because the joint surface with the first wiring layer M1 is an inclined plane, a large junction area with the first wiring layer M1 can be provided similarly to the TSV <NUM> illustrated in <FIG>, and a junction resistance can be reduced.

Moreover, as illustrated in <FIG>, the TSV according to the second modification differs from the TSV <NUM> illustrated in <FIG> in only the shape of the bottom portion, and the bottom portion has a shape of horizontal plane. The bottom portion in a horizontal planer shape can be formed by completing etching without changing an amount of the etching gas and an amount of the depot gas in the final phase of the etching to form the through hole <NUM>.

The TSV according to the second modification reaches the depth to pierce through the first wiring layer M1 similarly to the TSV <NUM> illustrated in <FIG>, and is connected to the first wiring layer M1 on the side peripheral surface. The TSV is formed without using the first wiring layer M1 as an etching stopper.

Therefore, because a notch is not formed at the bottom portion in the TSV according to the second modification, occurrence of a faulty connection in the RDL film <NUM> is suppressed, and the yields of semiconductor devices can be improved.

Moreover, as illustrated in <FIG>, the TSV according to the third modification differs from the TSV <NUM> illustrated in <FIG> only in a point that the depth in the logic board <NUM> is deeper than the TSV <NUM> illustrated in <FIG>, and reaches a depth to pierce through the third wiring layer M3.

Furthermore, as illustrated in <FIG>, the TSV according to the fourth modification differs from the TSV according to the first modification illustrated in <FIG> only in a point that the depth in the logic board <NUM> is deeper than the TSV of the first modification illustrated in <FIG>, and reaches a depth to pierce through the third wiring layer M3.

Moreover, as illustrated in <FIG>, the TSV according to the fifth modification differs from the TSV according to the second modification illustrated in <FIG> only in a point that the depth in the logic board <NUM> is deeper than the TSV of the second modification illustrated in <FIG>, and reaches a depth to pierce through the third wiring layer M3.

According to the TSV of these third to fifth modifications, the first to the third wiring layers M1, M2, M3 can be connected at once, and similarly to the TSV <NUM> illustrated in <FIG>, occurrence of a faulty connection in the RDL film <NUM> is suppressed, and can thereby improve the yields of the semiconductor devices.

The TSVs of the third to the fifth modifications may have a depth to pierce through the second wiring layer M2. That is, as long as the TSV according to the embodiment has the depth to pierce through a wiring layer, the number of wiring layers to be pierced through is not limited.

Furthermore, as long as the TSV according to the embodiment has a tapered shape at the bottom portion, it is not necessarily required to pierce through a wiring layer. For example, as illustrated in <FIG>, the TSV according to the sixth modification is connected to the top surface of the first wiring layer M1 at the bottom surface, without piercing through the first wiring layer M1. The shape of the bottom surface of the sixth modification is a bowl shape similar to that of the TSV <NUM> illustrated in <FIG>.

When forming such a TSV, the through hole <NUM> is formed using the first wiring layer M1 as an etching stopper. However, in the final phase of the etching to form the through hole <NUM>, a ratio adjustment of an amount of the etching gas to an amount of the depot gas is performed, to make the bottom portion of the through hole <NUM> into a bowl shape. This enables to prevent formation of a notch in the bottom portion of the through hole <NUM>.

Therefore, the TSV of the sixth modification suppresses occurrence of a faulty connection in the RDL film <NUM> similarly to the TSV <NUM> illustrated in <FIG>, and can thereby improve the yields of the semiconductor devices.

Moreover, as illustrated in <FIG>, the TSV according to the seventh modification is connected to the top surface of the first wiring layer M1 at a distal end portion in a bottom portion in a conical shape, without piercing through the first wiring layer M1. With this TSV also, similarly to the TSV illustrated in <FIG>, occurrence of a faulty connection in the RDL film <NUM> is suppressed, and can thereby improve the yields of the semiconductor devices.

Furthermore, the TSV according to the embodiment can be applied, for example, at a shallower position than the first wiring layer M1 in the insulation layer <NUM> of the logic board <NUM>, for example, to a semiconductor device in which a wiring layer formed with a metallic material, such as tungsten, is provided.

For example, as illustrated in <FIG>, the TSV according to the eight modification pierces through a metallic wiring layer M0, such as a local inter connect (LIC) formed with a metal of tungsten or the like provided on the shallowest layer in the insulation layer <NUM>, and is connected to the metallic wiring layer M0 on the side peripheral surface. The bottom portion of the TSV of the eighth modification is in a bowl shape.

Claim 1:
A semiconductor device (<NUM>) comprising:
a board (<NUM>) in which a wiring layer (<NUM>) is embedded; and
a via (<NUM>) that extends in a depth direction from a main surface of the board (<NUM>) to pierce through the wiring layer (<NUM>), and that is connected to the wiring layer (<NUM>) on a side peripheral surface, characterized in that
the via (<NUM>) comprises a vertical portion and a bottom portion in a tapered shape smoothly continuing from the vertical portion.