Patent Description:
A display device is a device displaying an image for providing visual information to a user. The display device may include pixels, and each of the pixels may include a light emitting element generating light and a pixel circuit providing a driving current to the light emitting element. The pixel circuit may include stacked conductive layers.

In the process of forming the conductive layers to form the pixel circuit, the conductive layers may be misaligned due to misalignment of a mask. In this case, capacitances between the conductive layers of pixel rows may not be uniform, therefore, kickback voltages of the pixel rows may not be uniform. Accordingly, stains may be recognized in the display device, and display quality of the display device may be reduced.

It is to be understood that this background of the technology section is, in part, intended to provide useful background for understanding the technology. However, this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein.

<CIT> discloses an organic light emitting diode display that includes a substrate, a plurality of pixels disposed on the substrate, and a plurality of transmitting windows configured to transmit light therethrough. The plurality of transmitting windows is spaced apart from the plurality of pixels. Each of the plurality of pixels includes a transistor and a capacitor. The transistor includes a light-blocking electrode disposed on the substrate and a plurality of electrode members disposed at different layers on the light-blocking electrode. The capacitor includes a first capacitor electrode disposed on a same layer as the light-blocking electrode, and a second capacitor electrode disposed on a same layer as a first one of the plurality of electrode members to overlap the first capacitor electrode.

<CIT> discloses a display device including: a substrate; a light emitting element on the substrate; a pixel circuit between the substrate and the light emitting element, wherein the pixel circuit is electrically connected to the light emitting element, and includes a plurality of transistors; and a conductive pattern including an electrode portion and a wiring portion for supplying a voltage to the electrode portion, wherein the electrode portion overlaps an active pattern of at least one transistor among the plurality of transistors, wherein the conductive pattern is disposed between the substrate and the active pattern, and wherein a thickness of the wiring portion is greater than a thickness of the electrode portion.

Embodiments provide a display device having improved display quality.

According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>. According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

In the display device according to the embodiments, an entirety of the upper gate signal line overlaps a part of the lower gate signal line, or an entirety of the lower gate signal line overlaps a part of the upper gate signal line in the overlapping area in which the lower gate signal line or the upper gate signal line overlap the first connection pattern, so that a capacitance between the lower gate signal line and the first connection pattern and a capacitance between the upper gate signal line and the first connection pattern may be constantly maintained. Accordingly, a kickback voltage of the first connection pattern due to a gate signal applied to the lower gate signal line and the upper gate signal line may be constant. Further, stains may not occur in the display device, therefore, display quality of the display device may be improved.

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Hereinafter, display devices in accordance with embodiments will be explained in detail with reference to the accompanying drawings.

Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the disclosure and like reference numerals refer to like elements throughout the specification.

The terms "and" and "or" may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to "and/or. " In the specification and the claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of" for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B.

It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

It will be further understood that the terms "comprises" and/or "comprising" "includes" and/or "including", "have" and/or "having" are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof.

When a layer, film, region, substrate, or area, or element is referred to as being "on" another layer, film, region, substrate, or area, or element, it may be directly on the other film, region, substrate, or area, or element, or intervening films, regions, substrates, or areas, or elements may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being "directly on" another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, or element, is referred to as being "below" another layer, film, region, substrate, or area, or element, it may be directly below the other layer, film, region, substrate, or area, or element, or intervening layers, films, regions, substrates, or areas, or elements, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, or element, is referred to as being "directly below" another layer, film, region, substrate, or area, or element, intervening layers, films, regions, substrates, or areas, or elements may be absent therebetween. Further, "over" or "on" may include positioning on or below an object and does not necessarily imply a direction based upon gravity.

The spatially relative terms "below", "beneath", "lower", "above", "upper", or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned "below" or "beneath" another device may be placed "above" another device. Accordingly, the illustrative term "below" may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations.

Sizes of components in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

Additionally, the terms "overlap" or "overlapped" mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term "overlap" may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The terms "face" and "facing" mean that a first element may directly or indirectly oppose a second element. In a case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other. When an element is described as 'not overlapping' or 'to not overlap' another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

In the specification, an expression such as "A and/or B" indicates A, B, or A and B. Also, an expression such as "at least one of A and B" indicates A, B, or A and B.

In embodiments below, when a component is referred to as being "on a plane," it is understood that a component is viewed from the top, and when a component is referred to as being "on a schematic cross section," it is understood that the component is vertically cut and viewed from the side.

It will be understood that when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, it may be "directly connected" or "directly coupled" to the other layer, region, or component and/or may be "indirectly connected" or "indirectly coupled" to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be "directly electrically connected" or "directly electrically coupled" to the other layer, region, or component and may be "indirectly electrically connected" or "indirectly electrically coupled" to the other layer, region, or component with other layers, regions, or components interposed therebetween.

Also, when an element is referred to as being "in contact" or "contacted" or the like to another element, the element may be in "electrical contact" or in "physical contact" with another element; or in "indirect contact" or in "direct contact" with another element.

In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that may not be perpendicular to one another.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments pertain. In addition, it will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

<FIG> is a plan view illustrating a display device according to an embodiment.

Referring to <FIG>, a display device according to an embodiment may include pixels PX. Each pixel PX may refer to a single area defined by dividing a display area in a plan view for displaying a color, and one pixel PX may display one predetermined basic color. In other words, one pixel PX may be a minimum unit that may display an independent color from another pixel PX. The pixels PX may be arranged or disposed along a first direction DR1 and a second direction DR2 crossing or intersecting the first direction DR1.

<FIG> is an equivalent circuit diagram illustrating a pixel according to an embodiment.

Referring to <FIG>, a pixel PX according to an embodiment may include a pixel circuit PC and a light emitting element EL. The pixel circuit PC may provide a driving current to the light emitting element EL. The light emitting element EL may emit light based on the driving current provided from the pixel circuit PC. The pixel circuit PC may include at least one transistor and at least one capacitor to generate the driving current.

In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor CAP. However, embodiments of the disclosure are not limited thereto, and in an embodiment, the pixel circuit PC may include two to six or eight or more transistors and/or two or more capacitors.

The first transistor T1 may be electrically connected between a first node N1 and a second node N2. A gate electrode of the first transistor T1 may be electrically connected to a third node N3. The first transistor T1 may generate the driving current based on a voltage between the first node N1 and the third node N3.

The second transistor T2 may be electrically connected between a data line <NUM> and the first node N1. A gate electrode of the second transistor T2 may receive a first gate signal GS1. The second transistor T2 may transmit a data voltage DV to the first node N1 based on the first gate signal GS1.

The third transistor T3 may be electrically connected between the second node N2 and the third node N3. A gate electrode of the third transistor T3 may receive a second gate signal GS2. The third transistor T3 may electrically connect the second node N2 and the third node N3 based on the second gate signal GS2 to compensate a threshold voltage of the first transistor T1.

The fourth transistor T4 may be electrically connected between a first initialization voltage line <NUM> and the third node N3. A gate electrode of the fourth transistor T4 may receive a third gate signal GS3. In an embodiment, the third gate signal GS3 may be a first gate signal applied to an (N-<NUM>)-th pixel row in a case that the pixel PX is included in an N-th pixel row. The fourth transistor T4 may receive a first initialization voltage IV1 from the first initialization voltage line <NUM>, and may transmit the first initialization voltage IV1 to the third node N3 based on the third gate signal GS3 to initialize the gate electrode of the first transistor T1.

The fifth transistor T5 may be electrically connected between a power voltage line <NUM> and the first node N1. A gate electrode of the fifth transistor T5 may receive an emission control signal EM. The power voltage line <NUM> may transmit a first power voltage VDD from a first power source.

The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. A gate electrode of the sixth transistor T6 may receive the emission control signal EM. The fifth transistor T5 and the sixth transistor T6 may transmit the driving current generated from the first transistor T1 to the light emitting element EL based on the emission control signal EM.

The seventh transistor T7 may be electrically connected between a second initialization voltage line <NUM> and the fourth node N4. A gate electrode of the seventh transistor T7 may receive a fourth gate signal GS4. In an embodiment, the fourth gate signal GS4 may be a first gate signal applied to an (N+<NUM>)-th pixel row in a case that the pixel PX is included in an N-th pixel row. The seventh transistor T7 may receive a second initialization voltage IV2 from the second initialization voltage line <NUM>, and may transmit the second initialization voltage IV2 to the fourth node N4 based on the fourth gate signal GS4 to initialize the light emitting element EL.

In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a single gate structure, and each of the third transistor T3 and the fourth transistor T4 may be a transistor having a double gate structure. However, embodiments of the disclosure are not limited thereto. In such an embodiment, the gate electrode of each of the third transistor T3 and the fourth transistor T4 may include a lower gate electrode and an upper gate electrode, and the lower gate electrode and the upper gate electrode may be electrically connected to each other.

In an embodiment, an active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed of polycrystalline silicon, and an active layer of each of the third transistor T3 and the fourth transistor T4 may be formed of an oxide semiconductor. In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS, and each of the third transistor T3 and the fourth transistor T4 may be an NMOS. However, embodiments of the disclosure are not limited thereto.

The capacitor CAP may be electrically connected between the power voltage line <NUM> and the third node N3. The capacitor CAP may maintain the voltage between the first node N1 and the third node N3 in a case that the second transistor T2 is turned off, so that the light emitting element EL may emit light.

The light emitting element EL may be electrically connected between the fourth node N4 and a second power source. The second power source may provide a second power voltage VSS. In an embodiment, the second power voltage VSS may be less than the first power voltage VDD. The light emitting element EL may emit light based on the driving current transmitted from the pixel circuit PC.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are layout diagrams illustrating an example of the pixel PX in <FIG>. <FIG> is a schematic cross-sectional view taken along a line I-I' in <FIG>.

Referring to <FIG>, the pixel PX may include a first active layer <NUM>, a first conductive layer <NUM>, a second conductive layer <NUM>, a second active layer <NUM>, a third conductive layer <NUM>, a fourth conductive layer <NUM>, a fifth conductive layer <NUM>, a first electrode <NUM>, an emission layer <NUM>, and a second electrode <NUM> which may be disposed on a substrate <NUM>.

The substrate <NUM> may be an insulating substrate including glass, quartz, plastic, or the like within the scope of the disclosure. In an embodiment, the substrate <NUM> may include a first flexible layer, a first barrier layer disposed on the first flexible layer, a second flexible layer disposed on the first barrier layer, and a second barrier layer disposed on the second flexible layer. The first flexible layer and the second flexible layer may include an organic insulation material such as polyimide (PI) or the like within the scope of the disclosure. The first barrier layer and the second barrier layer may include an inorganic insulation material such as silicon oxide, silicon nitride, amorphous silicon, or the like within the scope of the disclosure.

The first active layer <NUM> may be disposed on the substrate <NUM>. In an embodiment, the first active layer <NUM> may include polycrystalline silicon. However, embodiments of the disclosure are not limited thereto, and in an embodiment, the first active layer <NUM> may include amorphous silicon, an oxide semiconductor, or the like within the scope of the disclosure.

A buffer layer may be disposed between the substrate <NUM> and the first active layer <NUM>. The buffer layer may block impurities from being permeated toward above the substrate <NUM> through the substrate <NUM>. The buffer layer may provide a planarized upper surface above the substrate <NUM>. The buffer layer may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like within the scope of the disclosure. The buffer layer may be omitted.

The first conductive layer <NUM> may be disposed on the first active layer <NUM>. The first conductive layer <NUM> may include a conductive material such as molybdenum (Mo), copper (Cu), or the like within the scope of the disclosure.

A first insulation layer <NUM> may be disposed between the first active layer <NUM> and the first conductive layer <NUM>. The first insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like within the scope of the disclosure.

The first conductive layer <NUM> may include a first gate signal line <NUM>, an emission control signal line <NUM>, and a conductive pattern <NUM>. The first gate signal line <NUM> may extend in the first direction DR1. The emission control signal line <NUM> may be spaced apart from the first gate signal line <NUM>, and may extend in the first direction DR1. The conductive pattern <NUM> may be positioned or disposed between the first gate signal line <NUM> and the emission control signal line <NUM>.

A first portion of the first gate signal line <NUM> overlapping the first active layer <NUM> may form the gate electrode of the second transistor T2, and a second portion of the first gate signal line <NUM> overlapping the first active layer <NUM> may form the gate electrode of the seventh transistor T7. A portion of the first active layer <NUM> overlapping the gate electrode of the second transistor T2 may be a channel region of the second transistor T2, and a portion of the first active layer <NUM> overlapping the gate electrode of the seventh transistor T7 may be a channel region of the seventh transistor T7. Accordingly, the first active layer <NUM> and the first portion of the first gate signal line <NUM> may form the second transistor T2, and the first active layer <NUM> and the second portion of the first gate signal line <NUM> may form the seventh transistor T7.

A first portion of the emission control signal line <NUM> overlapping the first active layer <NUM> may form the gate electrode of the fifth transistor T5, and a second portion of the emission control signal line <NUM> overlapping the first active layer <NUM> may form the gate electrode of the sixth transistor T6. A portion of the first active layer <NUM> overlapping the gate electrode of the fifth transistor T5 may be a channel region of the fifth transistor T5, and a portion of the first active layer <NUM> overlapping the gate electrode of the sixth transistor T6 may be a channel region of the sixth transistor T6. Accordingly, the first active layer <NUM> and the first portion of the emission control signal line <NUM> may form the fifth transistor T5, and the first active layer <NUM> and the second portion of the emission control signal line <NUM> may form the sixth transistor T6.

A portion of the conductive pattern <NUM> overlapping the first active layer <NUM> may form the gate electrode of the first transistor T1. A portion of the first active layer <NUM> overlapping the gate electrode of the first transistor T1 may be a channel region of the first transistor T1. Accordingly, the first active layer <NUM> and the portion of the conductive pattern <NUM> may form the first transistor T1.

The second conductive layer <NUM> may be disposed on the first conductive layer <NUM>. The second conductive layer <NUM> may include a conductive material such as molybdenum (Mo), copper (Cu), or the like within the scope of the disclosure.

A second insulation layer <NUM> may be disposed between the first conductive layer <NUM> and the second conductive layer <NUM>. The second insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like within the scope of the disclosure.

The second conductive layer <NUM> may include a first lower gate signal line <NUM>, a second lower gate signal line <NUM>, the first initialization voltage line <NUM>, and a conductive line <NUM>. The first lower gate signal line <NUM> may extend in the first direction DR1. The second lower gate signal line <NUM> may be spaced apart from the first lower gate signal line <NUM>, and may extend in the first direction DR1. The first initialization voltage line <NUM> may be spaced apart from the second lower gate signal line <NUM>, and may extend in the first direction DR1. The conductive line <NUM> may be spaced apart from the first lower gate signal line <NUM>, and may extend in the first direction DR1.

The conductive line <NUM> may overlap the conductive pattern <NUM>. The conductive pattern <NUM> and the conductive line <NUM> may form the capacitor CAP.

The second active layer <NUM> may be disposed on the second conductive layer <NUM>. The second active layer <NUM> may not overlap the first active layer <NUM>. In an embodiment, the second active layer <NUM> may include an oxide semiconductor. However, embodiments of the disclosure are not limited thereto, and in an embodiment, the second active layer <NUM> may include amorphous silicon, polycrystalline silicon, or the like within the scope of the disclosure.

A third insulation layer <NUM> may be disposed between the second conductive layer <NUM> and the second active layer <NUM>. The third insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like within the scope of the disclosure.

The third conductive layer <NUM> may be disposed on the second active layer <NUM>. The third conductive layer <NUM> may include a conductive material such as molybdenum (Mo), copper (Cu), or the like within the scope of the disclosure.

A fourth insulation layer <NUM> may be disposed between the second active layer <NUM> and the third conductive layer <NUM>. The fourth insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like within the scope of the disclosure.

The third conductive layer <NUM> may include a first upper gate signal line <NUM> and a second upper gate signal line <NUM>. The first upper gate signal line <NUM> may extend in the first direction DR1. The second upper gate signal line <NUM> may be spaced apart from the first upper gate signal line <NUM>, and may extend in the first direction DR1.

A portion of the first lower gate signal line <NUM> overlapping the second active layer <NUM> may form the lower gate electrode of the third transistor T3, and a portion of the first upper gate signal line <NUM> overlapping the second active layer <NUM> may form the upper gate electrode of the third transistor T3. A portion of the second active layer <NUM> overlapping the lower gate electrode and the upper gate electrode of the third transistor T3 may be a channel region of the third transistor T3. Accordingly, the portion of the first lower gate signal line <NUM>, the second active layer <NUM>, and the portion of the first upper gate signal line <NUM> may form the third transistor T3. The third transistor T3 may be a transistor having a double gate structure.

A portion of the second lower gate signal line <NUM> overlapping the second active layer <NUM> may form the lower gate electrode of the fourth transistor T4, and a portion of the second upper gate signal line <NUM> overlapping the second active layer <NUM> may form the upper gate electrode of the fourth transistor T4. A portion of the second active layer <NUM> overlapping the lower gate electrode and the upper gate electrode of the fourth transistor T4 may be a channel region of the fourth transistor T4. Accordingly, the portion of the second lower gate signal line <NUM>, the second active layer <NUM>, and the portion of the second upper gate signal line <NUM> may form the fourth transistor T4. The fourth transistor T4 may be a transistor having a double gate structure.

The fourth conductive layer <NUM> may be disposed on the third conductive layer <NUM>. The fourth conductive layer <NUM> may include a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), or the like within the scope of the disclosure. In an embodiment, the fourth conductive layer <NUM> may have a multilayer structure including a Ti layer, an Al layer, and a Ti layer which may be stacked.

A fifth insulation layer <NUM> may be disposed between the third conductive layer <NUM> and the fourth conductive layer <NUM>. The fifth insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like and/or an organic insulation material such as polyimide (PI) or the like within the scope of the disclosure.

The fourth conductive layer <NUM> may include the second initialization voltage line <NUM>, a first connection pattern <NUM>, a second connection pattern <NUM>, a third connection pattern <NUM>, a first contact pattern <NUM>, a second contact pattern <NUM>, and a third contact pattern <NUM>. The second initialization voltage line <NUM> may extend in the first direction DR1. The second initialization voltage line <NUM> may be electrically connected to the first active layer <NUM> through a first contact hole CH1. Accordingly, the second initialization voltage line <NUM> may be electrically connected to the seventh transistor T7.

The first connection pattern <NUM> may be spaced apart from the second initialization voltage line <NUM>. The first connection pattern <NUM> may be electrically connected to the conductive pattern <NUM> through a second contact hole CH2, and may be electrically connected to the second active layer <NUM> through a third contact hole CH3. Accordingly, the first connection pattern <NUM> may electrically connect the gate electrode of the first transistor T1 and a second end portion of the third transistor T3. For example, the first connection pattern <NUM> may electrically connect the gate electrode of the first transistor T1 and a second end portion <NUM> of the second active layer <NUM>.

The second connection pattern <NUM> may be spaced apart from the first connection pattern <NUM>. The second connection pattern <NUM> may be electrically connected to the first active layer <NUM> through a fourth contact hole CH4, and may be electrically connected to the second active layer <NUM> through a fifth contact hole CH5. Accordingly, the second connection pattern <NUM> may electrically connect an end portion of the first transistor T1 and a first end portion of the third transistor T3. As an example, the second connection pattern <NUM> may electrically connect an end portion <NUM> of the first active layer <NUM> and a first end portion <NUM> of the second active layer <NUM>.

The third connection pattern <NUM> may be spaced apart from the second connection pattern <NUM>. The third connection pattern <NUM> may be electrically connected to the first initialization voltage line <NUM> through a sixth contact hole CH6, and may be electrically connected to the second active layer <NUM> through a seventh contact hole CH7. Accordingly, the third connection pattern <NUM> may electrically connect the first initialization voltage line <NUM> and the second active layer <NUM>. The first initialization voltage line <NUM> may be electrically connected to the fourth transistor T4 through the third connection pattern <NUM>.

The first contact pattern <NUM> may be spaced apart from the third connection pattern <NUM>. The first contact pattern <NUM> may be electrically connected to the first active layer <NUM> through an eighth contact hole CH8. Accordingly, the first contact pattern <NUM> may be electrically connected to the second transistor T2.

The second contact pattern <NUM> may be spaced apart from the first contact pattern <NUM>. The second contact pattern <NUM> may be electrically connected to the first active layer <NUM> through a ninth contact hole CH9, and may be electrically connected to the conductive line <NUM> through a tenth contact hole CH10. Accordingly, the second contact pattern <NUM> may be electrically connected to the fifth transistor T5 and the capacitor CAP.

The third contact pattern <NUM> may be spaced apart from the second contact pattern <NUM>. The third contact pattern <NUM> may be electrically connected to the first active layer <NUM> through an eleventh contact hole CH11. Accordingly, the third contact pattern <NUM> may be electrically connected to the sixth transistor T6.

The fifth conductive layer <NUM> may be disposed on the fourth conductive layer <NUM>. The fifth conductive layer <NUM> may include a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), or the like within the scope of the disclosure. In an embodiment, the fifth conductive layer <NUM> may have a multilayer structure including a Ti layer, an Al layer, and a Ti layer which may be stacked.

A sixth insulation layer <NUM> may be disposed between the fourth conductive layer <NUM> and the fifth conductive layer <NUM>. The sixth insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like and/or an organic insulation material such as polyimide (PI) or the like within the scope of the disclosure.

The fifth conductive layer <NUM> may include the data line <NUM>, the power voltage line <NUM>, and a fourth contact pattern <NUM>. The data line <NUM> may extend in the second direction DR2. The date line <NUM> may be electrically connected to the first contact pattern <NUM> through a twelfth contact hole CH12. Accordingly, the date line <NUM> may be electrically connected to the second transistor T2 through the first contact pattern <NUM>.

The power voltage line <NUM> may be spaced apart from the date line <NUM>, and may extend in the second direction DR2. The power voltage line <NUM> may be electrically connected to the second contact pattern <NUM> through a thirteenth contact hole CH13. Accordingly, the power voltage line <NUM> may be electrically connected to the fifth transistor T5 and the capacitor CAP through the second contact pattern <NUM>.

The fourth contact pattern <NUM> may be spaced apart from the power voltage line <NUM>. The fourth contact pattern <NUM> may be electrically connected to the third contact pattern <NUM> through a fourteenth contact hole CH14.

The first electrode <NUM> may be disposed on the fifth conductive layer <NUM>. The first electrode <NUM> may include a conductive material such as a metal, an alloy, a transparent conductive oxide, or the like within the scope of the disclosure. For example, the first electrode <NUM> may include silver (Ag), indium tin oxide (ITO), or the like within the scope of the disclosure. In an embodiment, the first electrode <NUM> may have a multilayer structure including an ITO layer, an Ag layer, and an ITO layer which may be stacked.

A seventh insulation layer <NUM> may be disposed between the fifth conductive layer <NUM> and the first electrode <NUM>. The seventh insulation layer <NUM> may include an inorganic insulation material such as silicon oxide, silicon nitride, silicon oxynitride, or the like and/or an organic insulation material such as polyimide (PI) or the like within the of the disclosure.

The first electrode <NUM> may be electrically connected to the fourth contact pattern <NUM> through a contact hole. Accordingly, the first electrode <NUM> may be electrically connected to the sixth transistor T6 through the third contact pattern <NUM> and the fourth contact pattern <NUM>.

An eighth insulation layer <NUM> may be disposed on the first electrode <NUM>. The eighth insulation layer <NUM> may cover or overlap the first electrode <NUM>, and may be disposed on the seventh insulation layer <NUM>. The eighth insulation layer <NUM> may have a pixel opening exposing at least a portion of the first electrode <NUM>. In an embodiment, the pixel opening may expose a central portion of the first electrode <NUM>, and the eighth insulation layer <NUM> may cover or overlap a peripheral portion of the first electrode <NUM>. The eighth insulation layer <NUM> may include an organic insulation material such as polyimide (PI) or the like within the scope of the disclosure.

The emission layer <NUM> may be disposed on the first electrode <NUM>. The emission layer <NUM> may be disposed on the first electrode <NUM> exposed by the pixel opening. The emission layer <NUM> may include at least one of an organic light emitting material and a quantum dot.

In an embodiment, the organic light emitting material may include a low molecular organic compound or a high molecular organic compound. For example, the low molecular organic compound may include copper phthalocyanine, diphenylbenzidine (N, N'-diphenylbenzidine), trihydroxyquinoline aluminum (tris-(<NUM>-hydroxyquinoline)aluminum), and the like within the scope of the disclosure. The high molecular organic compound may include poly ethylenedioxythiophene (poly(<NUM>,<NUM>-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, and the like within the scope of the disclosure.

In an embodiment, the quantum dot may include a core including a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and a combination thereof. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may prevent chemical denaturation of the core, thereby serving as a protective layer for maintaining semiconductor characteristics and a charging layer for imparting electrophoretic characteristics to the quantum dot.

The second electrode <NUM> may be disposed on the emission layer <NUM>. In an embodiment, the second electrode <NUM> may also be disposed on the eighth insulation layer <NUM>. The second electrode <NUM> may include a conductive material such as a metal, an alloy, a transparent conductive oxide, or the like within the scope of the disclosure. For example, the second electrode <NUM> may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), or the like within the scope of the disclosure. The first electrode <NUM>, the emission layer <NUM>, and the second electrode <NUM> may form the light emitting element EL.

<FIG> is a layout diagram illustrating an example of an area A in <FIG>. <FIG> is a schematic cross-sectional view taken along a line II-II' in <FIG>.

Referring to <FIG>, the first upper gate signal line <NUM> is disposed on the first lower gate signal line <NUM>, and the first connection pattern <NUM> is disposed on the first upper gate signal line <NUM>. The first connection pattern <NUM> crosses or intersects the first lower gate signal line <NUM> and the first upper gate signal line <NUM> which may extend in the first direction DR1. An area in which the first lower gate signal line <NUM> or the first upper gate signal line <NUM> overlap the first connection pattern <NUM> is defined as an overlapping area OA. The first connection pattern <NUM> may extend in the second direction DR2 in the overlapping area OA.

A width 151W of the first upper gate signal line <NUM> in the second direction DR2 may be less than a width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA. An entirety of the first upper gate signal line <NUM> overlaps a part of the first lower gate signal line <NUM> in the overlapping area OA. In other words, a portion of the first lower gate signal line <NUM> may overlap the first upper gate signal line <NUM> in the overlapping area OA, and another portion of the first lower gate signal line <NUM> may not overlap the first upper gate signal line <NUM> in the overlapping area OA. For example, a central portion of the first lower gate signal line <NUM> in the second direction DR2 may overlap the first upper gate signal line <NUM> in the overlapping area OA, and side portions of the first lower gate signal line <NUM> in the second direction DR2 may not overlap the first upper gate signal line <NUM> in the overlapping area OA.

In a comparative example, in a case that a first lower gate signal line and a first upper gate signal line partially overlap each other in an overlapping area, due to tolerance in the process of forming the first upper gate signal line on the first lower gate signal line, a capacitance between the first lower gate signal line and the first upper gate signal line may be changed. However, in an embodiment, the width 151W of the first upper gate signal line <NUM> in the second direction DR2 may be less than the width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA, and an entirety of the first upper gate signal line <NUM> may overlap a part of the first lower gate signal line <NUM> in the overlapping area OA. Therefore, although tolerance in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM> is considered, a capacitance between the first lower gate signal line <NUM> and the first connection pattern <NUM> and a capacitance between the first upper gate signal line <NUM> and the first connection pattern <NUM> may be constantly maintained.

In an embodiment, a value subtracting the width 151W of the first upper gate signal line <NUM> in the second direction DR2 from the width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA may be greater than about <NUM>. In other words, the difference between the width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA and the width 151W of the first upper gate signal line <NUM> in the second direction DR2 may be greater than about <NUM>. A tolerance less than about <NUM> in the second direction DR2 may occur in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM>. Since the value subtracting the width 151W of the first upper gate signal line <NUM> in the second direction DR2 from the width 131W of the first lower gate signal line <NUM> in the second direction DR2 may be greater than about <NUM> in the overlapping area OA, although the tolerance less than about <NUM> in the second direction DR2 may occur in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM>, an entirety of the first upper gate signal line <NUM> may overlap a part of the first lower gate signal line <NUM> in the overlapping area OA.

In an embodiment, each of a width of the first lower gate signal line <NUM> in the second direction DR2 and a width of the first upper gate signal line <NUM> in the second direction DR2 may be constant. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to the width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to the width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA.

<FIG> is a layout diagram illustrating an example of the area A in <FIG>. <FIG> is a layout diagram illustrating an example of the area A in <FIG>.

Referring to <FIG>, in an embodiment, the first lower gate signal line <NUM> may protrude in the second direction DR2 in a plan view in the overlapping area OA. In such an embodiment, a portion of the first upper gate signal line <NUM> outside the overlapping area OA may not overlap the first lower gate signal line <NUM>, and the first lower gate signal line <NUM> may have a protruding portion 131P protruding in the second direction DR2 in the overlapping area OA. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be less than a width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to a width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA.

Referring to <FIG>, in an embodiment, the first upper gate signal line <NUM> may be recessed in the second direction DR2 in a plan view in the overlapping area OA. In such an embodiment, a portion of the first upper gate signal line <NUM> outside the overlapping area OA may not overlap the first lower gate signal line <NUM>, and the first upper gate signal line <NUM> may have a recessed portion 151R recessed in the second direction DR2 in the overlapping area OA. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to a width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be greater than a width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA.

<FIG> is a diagram illustrating a kickback voltage of the third node N3 based on the second gate signal GS2.

Referring to <FIG>, <FIG>, and <FIG>, in a case that the second gate signal GS2 applied to the gate electrode of the third transistor T3 is changed from a low level to a high level, the second node N2 and the third node N3 may be electrically connected to each other such that the first transistor T1 may be diode-connected. Then, in a case that the second transistor T2 is turned-on based on the first gate signal GS1, the data voltage DV may be applied to the first node N1, therefore, a voltage V_N3 in which a threshold voltage of the first transistor T1 may be compensated from the data voltage DV may be applied to the third node N3. Then, in a case that the second gate signal GS2 is changed from the high level to the low level, the voltage V_N3 of the third node N3 may be increase or decrease as much as a kickback voltage V_KB.

Because capacitances may be formed between the first lower gate signal line <NUM> and the first connection pattern <NUM> and between the first upper gate signal line <NUM> and the first connection pattern <NUM> in the overlapping area OA, the first lower gate signal line <NUM> and the first upper gate signal line <NUM> may electrically affect the first connection pattern <NUM>. In a case that the second gate signal GS2 which the first lower gate signal line <NUM> and the first upper gate signal line <NUM> transmit is changed from the high level to the lower level, the voltage V_N3 of the first connection pattern <NUM> that may be the third node N3 may increase or decrease as much as the kickback voltage V_KB.

In a comparative example, in a case that kickback voltages V_KB occurred in pixel rows may be different from each other, stains may occur in the display device. However, in an embodiment, because the capacitance between the first lower gate signal line <NUM> and the first connection pattern <NUM> and the capacitance between the first upper gate signal line <NUM> and the first connection pattern <NUM> may be constantly maintained, kickback voltages V_KB that occurred in pixel rows may be substantially equal to each other, therefore, stains may not occur in the display device, and display quality of the display device may be improved.

Hereinafter, descriptions of elements of a display device described with reference to <FIG>, which may be substantially the same as or similar to those of the display device described with reference to <FIG>, will not be repeated.

<FIG> is a layout diagram illustrating an example of the area A in <FIG>. <FIG> is a schematic cross-sectional view taken along a line III-III' in <FIG>.

Referring to <FIG> and <FIG>, a width 151W of the first upper gate signal line <NUM> in the second direction DR2 may be greater than a width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA. An entirety of the first lower gate signal line <NUM> overlaps a part of the first upper gate signal line <NUM> in the overlapping area OA. In other words, a portion of the first upper gate signal line <NUM> may overlap the first lower gate signal line <NUM> in the overlapping area OA, and another portion of the first upper gate signal line <NUM> may not overlap the first lower gate signal line <NUM> in the overlapping area OA. For example, a central portion of the first upper gate signal line <NUM> in the second direction DR2 may overlap the first lower gate signal line <NUM> in the overlapping area OA, and side portions of the first upper gate signal line <NUM> in the second direction DR2 may not overlap the first lower gate signal line <NUM> in the overlapping area OA.

In an embodiment, the width 151W of the first upper gate signal line <NUM> in the second direction DR2 may be greater than the width 131W of the first lower gate signal line <NUM> in the second direction DR2 in the overlapping area OA, and an entirety of the first lower gate signal line <NUM> may overlap a part of the first upper gate signal line <NUM> in the overlapping area OA. Therefore, although tolerance in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM> is considered, the first upper gate signal line <NUM> may shield the first lower gate signal line <NUM> from the first connection pattern <NUM>. Accordingly, a capacitance between the first lower gate signal line <NUM> and the first connection pattern <NUM> and a capacitance between the first upper gate signal line <NUM> and the first connection pattern <NUM> may be constantly maintained.

In an embodiment, a value subtracting the width 131W of the first lower gate signal line <NUM> in the second direction DR2 from the width 151W of the first upper gate signal line <NUM> in the second direction DR2 in the overlapping area OA may be greater than about <NUM>. In other words, the difference between the width 151W of the first upper gate signal line <NUM> in the second direction DR2 in the overlapping area OA and the width 131W of the first lower gate signal line <NUM> in the second direction DR2 may be greater than about <NUM>. A tolerance less than about <NUM> in the second direction DR2 may occur in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM>. Since the value subtracting the width 131W of the first lower gate signal line <NUM> in the second direction DR2 from the width 151W of the first upper gate signal line <NUM> in the second direction DR2 is greater than about <NUM> in the overlapping area OA, although the tolerance less than about <NUM> in the second direction DR2 may occur in the process of forming the first upper gate signal line <NUM> on the first lower gate signal line <NUM>, an entirety of the first lower gate signal line <NUM> may overlap a part of the first upper gate signal line <NUM> in the overlapping area OA.

In an embodiment, each of a width of the first lower gate signal line <NUM> in the second direction DR2 and a width of the first upper gate signal line <NUM> in the second direction DR2 may be constant. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to the width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to the width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA. In other words, the widths of the first lower gate signal line <NUM> both inside and outside of the overlapping area OA in the second direction DR2 may be substantially equal. Similarly, the widths of the first upper gate signal line <NUM> both inside and outside of the overlapping area OA in the second direction DR2 may be substantially equal.

Referring to <FIG>, in an embodiment, the first lower gate signal line <NUM> may be recessed in the second direction DR2 in a plan view in the overlapping area OA. In such an embodiment, a portion of the first lower gate signal line <NUM> outside the overlapping area OA may not overlap the first upper gate signal line <NUM>, and the first lower gate signal line <NUM> may have a recessed portion 131R recessed in the second direction DR2 in the overlapping area OA. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be greater than a width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to a width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA.

Referring to <FIG>, in an embodiment, the first upper gate signal line <NUM> may protrude in the second direction DR2 in a plan view in the overlapping area OA. In such an embodiment, a portion of the first lower gate signal line <NUM> outside the overlapping area OA may not overlap the first upper gate signal line <NUM>, and the first upper gate signal line <NUM> may have a protruding portion 151P protruding in the second direction DR2 in the overlapping area OA. For example, a width of the first lower gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be substantially equal to a width 131W of the first lower gate signal line <NUM> in the second direction DR2 inside the overlapping area OA, and a width of the first upper gate signal line <NUM> in the second direction DR2 outside the overlapping area OA may be less than a width 151W of the first upper gate signal line <NUM> in the second direction DR2 inside the overlapping area OA.

<FIG> is a layout diagram illustrating an example of the pixel PX in <FIG>. A pixel described with reference to <FIG> may be substantially the same as or similar to the pixel described with <FIG> except for the structure of the first connection pattern <NUM> and the position of the third contact hole CH3. Accordingly, descriptions on repeated elements will be omitted.

Referring to <FIG>, in an embodiment, the third contact hole CH3 electrically connecting the second active layer <NUM> and the first connection pattern <NUM> may not overlap the first gate signal line <NUM>. In other words, the third contact hole CH3 and the first gate signal line <NUM> may be spaced apart from each other in a plan view. Accordingly, a path for compensating the threshold voltage of the first transistor T1 through the second active layer <NUM>, the third contact hole CH3, and the first connection pattern <NUM> may not overlap the first gate signal line <NUM> transmitting the first gate signal.

In a case that the third contact hole CH3 may overlap the first gate signal line <NUM>, (in other words, in a case that the path for compensating the threshold voltage of the first transistor T1 may overlap the first gate signal line <NUM>), a resistance of the second active layer <NUM> may increase due to the first gate signal which the first gate signal line <NUM> transmits, therefore, on-current of the third transistor T3 may decrease. However, in an embodiment, the third contact hole CH3 electrically connecting the second active layer <NUM> and the first connection pattern <NUM> may not overlap the first gate signal line <NUM>, so that the first gate signal which the first gate signal line <NUM> transmits may not substantially affect the path for compensating the threshold voltage of the first transistor T1. Accordingly, the decrease of the on-current of the third transistor T3 due to the increase of the resistance of the second active layer <NUM> may be prevented.

The display device according to embodiments may be applied to a display device included in a computer, a notebook, a mobile phone, a smartphone, a smart pad, a PMP, a PDA, an MP3 player, or the like within the scope of the disclosure.

Claim 1:
A display device, comprising:
a first transistor (T1) including:
a first active layer (<NUM>) disposed over a substrate (<NUM>); and
a gate electrode disposed over the first active layer (<NUM>);
a second transistor (T3) including:
a lower gate electrode disposed over the substrate (<NUM>);
a second active layer (<NUM>) disposed over the lower gate electrode, a first end portion of the second active layer (<NUM>) being electrically connected to an end portion of the first active layer (<NUM>); and
an upper gate electrode disposed over the second active layer (<NUM>);
a lower gate signal line (<NUM>) extending in a first direction (DR1), a portion of the lower gate signal line (<NUM>) forming the lower gate electrode;
an upper gate signal line (<NUM>) disposed over the lower gate signal line (<NUM>) and extending in the first direction, a portion of the upper gate signal line (<NUM>) forming the upper gate electrode; and
a first connection pattern (<NUM>) disposed over the upper gate signal line (<NUM>), electrically connecting the gate electrode and a second end portion of the second active layer (<NUM>), and intersecting the lower gate signal line (<NUM>) and the upper gate signal line (<NUM>), characterized in that
an entire part of the upper gate signal line (<NUM>) overlaps a part of the lower gate signal line (<NUM>) in an overlapping area (OA) in which the lower gate signal line (<NUM>) or the upper gate signal line (<NUM>) overlaps the first connection pattern (<NUM>),
a channel of the second active layer (<NUM>) is disposed in the first direction (DR1) from the overlapping area (OA) in a plan view, and
the lower gate electrode and the upper gate electrode overlap the channel of the second active layer (<NUM>).