Patent Description:
This application is generally related to electronic design automation and, more specifically, to path-based layer stack connectivity check for plasma induced damage avoidance.

In a design flow for fabricating integrated circuits, a physical design of an integrated circuit can describe specific geometric elements, often referred to as a layout design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the integrated circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.

Descriptions for physical designs of integrated circuits can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each structure including layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway, EDDM, and Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define the geometrical information in layout designs that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.

There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

During manufacture of the integrated circuits, transistors can have gate dielectrics thin enough, for example, only a few molecules thick, to become damaged when a transistor gate receives a higher than expected voltage. For example, an aggressor transistor can be designed to provide a voltage to a gate of a victim transistor. To avoid having the gate dielectric of the victim transistor damaged during manufacturing, the foundry will typically manufacture the transistors by manufacturing a connection between the wells of the aggressor transistor and the victim transistor and then manufacturing the connection from the aggressor transistor to the gate of the victim transistor.

Many foundries generate connectivity rules, which can be used to ensure layout designs having pairs of aggressor and victim transistors will manufacture the connection between the wells of the aggressor transistor and the victim transistor before manufacturing the connection from the aggressor transistor to the gate of the victim transistor. Traditional verification tools apply these connectivity rules in a step-by-step fashion, by analyzing the layers of the layout design from the substrate up to the metal layers. Oftentimes, however, victim and aggressor transistor wells are not directly connected in the layout designs, but instead include intervening circuitry, such as a current pump, an intermediate well, or the like. This lack of direct connectivity between the victim and aggressor transistor wells can stifle traditional verification tools and render that portion of the layout design unchecked against the connectivity rules.

<NPL>, studies the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology.

<NPL>, addresses the problem of crosstalk computation and reduction using circuit and layout techniques. It provides easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines.

<NPL>, discloses a new test structure based on cross bridge Kelvin resistor, in order to evaluate low contact resistivity precisely. In this structure, the misalignment margin can be as small as possible. Furthermore, the theoretical expressions to ensure the validity of the newly developed method are successively derived.

This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistive network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor. The invention is defined by the attached set of claims. Embodiments of will be described below in greater detail.

Various examples may be implemented through the execution of software instructions by a computing device <NUM>, such as a programmable computer. Accordingly, <FIG> shows an illustrative example of a computing device <NUM>. As seen in this figure, the computing device <NUM> includes a computing unit <NUM> with a processing unit <NUM> and a system memory <NUM>. The processing unit <NUM> may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory <NUM> may include both a read-only memory (ROM) <NUM> and a random access memory (RAM) <NUM>. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) <NUM> and the random access memory (RAM) <NUM> may store software instructions for execution by the processing unit <NUM>.

The processing unit <NUM> and the system memory <NUM> are connected, either directly or indirectly, through a bus <NUM> or alternate communication structure, to one or more peripheral devices <NUM>-<NUM>. For example, the processing unit <NUM> or the system memory <NUM> may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive <NUM>, which can be magnetic and/or removable, a removable optical disk drive <NUM>, and/or a flash memory card. The processing unit <NUM> and the system memory <NUM> also may be directly or indirectly connected to one or more input devices <NUM> and one or more output devices <NUM>. The input devices <NUM> may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices <NUM> may include, for example, a monitor display, a printer and speakers. With various examples of the computing device <NUM>, one or more of the peripheral devices <NUM>-<NUM> may be internally housed with the computing unit <NUM>. Alternately, one or more of the peripheral devices <NUM>-<NUM> may be external to the housing for the computing unit <NUM> and connected to the bus <NUM> through, for example, a Universal Serial Bus (USB) connection.

With some implementations, the computing unit <NUM> may be directly or indirectly connected to a network interface <NUM> for communicating with other devices making up a network. The network interface <NUM> can translate data and control signals from the computing unit <NUM> into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface <NUM> may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

It should be appreciated that the computing device <NUM> is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device <NUM> illustrated in <FIG>, which include only a subset of the components illustrated in <FIG>, or which include an alternate combination of components, including components that are not shown in <FIG>. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

With some implementations, the processor unit <NUM> can have more than one processor core. Accordingly, <FIG> illustrates an example of a multi-core processor unit <NUM> that may be employed with various embodiments. As seen in this figure, the processor unit <NUM> includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and/or instructions for execution.

Each processor core 201A and 201B is connected to an interconnect <NUM>. The particular construction of the interconnect <NUM> may vary depending upon the architecture of the processor unit <NUM>. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect <NUM> may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect <NUM> may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect <NUM> with an input/output interface <NUM> and a memory controller <NUM>. The input/output interface <NUM> provides a communication interface to the bus <NUM>. Similarly, the memory controller <NUM> controls the exchange of information to the system memory <NUM>. With some implementations, the processor unit <NUM> may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in <FIG> and <FIG> is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.

<FIG> illustrates an example of a physical verification system <NUM> including a reliability verification system <NUM> to perform a path-based layer stack connectivity check for plasma induced damage avoidance according to various embodiments. <FIG> illustrates a flowchart showing example path-based layer stack connectivity check for plasma induced damage avoidance according to various examples. Referring to <FIG> and <FIG>, the physical verification system <NUM> can receive a layout design <NUM> of an electronic system. The layout design <NUM> can define geometrical information capable of being utilized to manufacture an integrated circuit, such as the electronic system, which can be specified in a Graphic Data System II (GDSII) format, an Open Access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, or the like. The physical verification system <NUM> also can receive connectivity rules <NUM>, for example, from a foundry or integrated circuit manufacturer, to identify valid types of connectivity in the layout design <NUM> and a manufacturing order for circuit device connectivity.

The physical verification system <NUM>, in some embodiments, can include a design rule check system <NUM> to analyze the layout design <NUM> to determine whether the circuitry within the layout design <NUM> conforms to design rules from a foundry capable of manufacturing an integrated circuit described by the layout design <NUM>. The design rule check system <NUM>, when determining whether the layout design <NUM> conforms to the connectivity rules <NUM>, can perform a sequential, layer-by-layer check for electrical connectivity of the integrated circuit. The design rule check system <NUM> can identify connectivity on different layers of the integrated circuit in the order that they are to be manufactured, e.g., starting at the substrate layer before moving to the diffusion layer, and then to each of the stacked metal layers.

The design rule check system <NUM> can utilize the identified connectivity on the different layers to perform the connectivity checks based on the connectivity rules <NUM>. In some embodiments, when the design rule check system <NUM> identifies a pair of transistors do not conform to the connectivity rules <NUM>, for example, due to no connectivity between the wells of the transistors prior to connecting a gate region of at least one of the transistors, the design rule check system <NUM> can generate one or more connectivity errors <NUM>. In some instances, the connectivity errors <NUM> generated by the design rule check system <NUM> can be false, for example, as the pair of transistors can connect their wells to a common voltage potential through shared intervening circuitry, such as a current pump circuit or an intermediate well.

The physical verification system <NUM> can include a reliability verification system <NUM> to determine whether the layout design <NUM> conforms to the connectivity rules <NUM>. In some embodiments, the reliability verification system <NUM> can receive the connectivity errors <NUM> from the design rule check system <NUM>. The reliability verification system <NUM> can analyze the portions of the layout design <NUM>, which may be associated with the connectivity errors <NUM>, to ascertain whether the pair of transistors can connect their wells to a common voltage potential, either directly or through shared intervening circuitry, such as a current pump circuit or an intermediate well, and also whether the connection allows the pair of transistors to conform to the connectivity rules <NUM>. In some embodiments, the reliability verification system <NUM> can determine whether the layout design <NUM> conforms to the connectivity rules <NUM> independently of any connectivity errors <NUM> generated by the design rule check system <NUM> and/or without the design rule check system <NUM> performing a check of the layout design <NUM> against the connectivity rules <NUM>.

The reliability verification system <NUM> can include a connectivity system <NUM> to identify the circuit devices and their connectivity described in the layout design <NUM>. For example, the connectivity system <NUM> can analyze the geometric information in the layout design <NUM> to identify circuit device and their connectivity. In some embodiments, the connectivity system <NUM>, in a block <NUM>, can identify a portion of a layout design describing an integrated circuit includes a victim transistor and an aggressor transistor have wells. In some embodiments, the wells of the victim transistor and the aggressor transistor can be coupled to shared intervening circuitry. Embodiments of an aggressor transistor, victim transistor, and intervening circuitry in a layout design will be described below in greater detail with reference to <FIG>.

<FIG> illustrates an example layout design having an aggressor transistor, victim transistor, and intervening circuitry according to various embodiments. Referring to <FIG>, a portion of an integrated circuit <NUM> can include transistors <NUM>-<NUM>. The transistors <NUM> and <NUM> can be P-Channel Metal-Oxide-Semiconductor (PMOS) transistors, while the transistors <NUM> and <NUM> can be N-Channel Metal-Oxide-Semiconductor (NMOS) transistors. The transistors <NUM> and <NUM> can form to a switch having their drain regions coupled to the gate regions of the transistors <NUM> and <NUM>. The source regions of transistors <NUM> and <NUM> can be connected via intervening circuitry <NUM>, which can include at least one current pump, intermediate well, other circuitry coupled between the wells of the transistors <NUM> and <NUM>, or a combination thereof. During manufacture, the connection of the source regions of transistors <NUM> and <NUM> via the intervening circuitry <NUM> should be manufactured prior to the manufacturing of the connection between the drain regions of the transistors <NUM> and <NUM> and the gate regions of the transistors <NUM> and <NUM> in order to avoid any plasma induced damage to a dielectric for the gate regions of the transistors <NUM> and <NUM>.

Referring back to <FIG> and <FIG>, the reliability verification system <NUM> can include a parasitic extraction system <NUM> to determine resistive electrical characteristics for circuitry identified by the connectivity system <NUM> in the layout design <NUM>, for example, by converting polygons on layers of the layout design <NUM> into an equivalent resistive representation. The parasitic extraction system <NUM> can aggregate the resistive electrical characteristics into a resistive network, which can be the equivalent resistive representation of the circuitry identified by the connectivity system <NUM>. In some embodiments, the parasitic extraction system <NUM>, in a block <NUM>, can extract a resistive network for connections between the victim transistor, the aggressor transistor, and any shared intervening circuitry coupled between the wells of the victim and aggressor transistors. Embodiments of resistive network for connections between the victim transistor, the aggressor transistor, and the shared intervening circuitry will be described below in greater detail with reference to <FIG>.

<FIG> illustrates an example path-based layer stack connectivity check for plasma induced damage avoidance for the layout design described in <FIG>. Referring to <FIG>, a resistive network <NUM> can be a resistive electrical representation of a portion of the integrated circuit <NUM> in <FIG>. The resistive network <NUM> can include a pair of transistors <NUM> and <NUM>, which can correspond to transistors <NUM> and <NUM> in <FIG>. The transistors <NUM> and <NUM> can be connected to a resistive intervening circuit <NUM>, which can correspond to the intervening circuitry <NUM> in <FIG>. The resistive representation also can include resistors R representing the various connections between the transistors <NUM> and <NUM> and the resistive intervening circuitry <NUM> along with their locations within the different metal layers of the integrated circuit.

Referring back to <FIG> and <FIG>, the reliability verification system <NUM> can include a layer condition system <NUM> to set the various conditions of the integrated circuit described in the layout design <NUM> at different stages of manufacturing based, at least in part, on the connectivity rules <NUM>. For example, a condition when a top metal layer has not yet been manufactured, but other layers below the top metal layer have been manufactured, the condition can indicate the top metal layer to be an open circuit and thus blocks current flow through a portion of the resistive network corresponding to the top metal layer. In some embodiments, the layer condition system <NUM> can set those layers as open circuit by setting the resistance values for those layers as having resistance values of infinite or some other very high resistance value which would block the flow of current through the resistive network. In some embodiments, the layer condition system <NUM>, in a block <NUM>, can set resistor values of a connection between a gate of the victim transistor and the aggressor transistor to block current to flow through the connection.

The reliability verification system <NUM> can include a simulator <NUM> to simulate the conditions of the resistive network that were set by the layer condition system <NUM>. In some embodiments, the simulator <NUM> can inject current into a node of an aggressor transistor and then use a numerical simulation, for example, with Kirchhoff's current law, to determine whether the injected current reaches the victim transistor. In some embodiments, the simulator <NUM>, in a block <NUM>, can simulate the resistive network with the set resistor values for the connection to determine connectivity between the wells of the victim transistor and the aggressor transistor. Embodiments of simulating the resistive network with blocked current flow through the connection between a gate of the victim transistor and the aggressor transistor will be described below in greater detail with reference to <FIG>.

<FIG> illustrates an example path-based layer stack connectivity check for plasma induced damage avoidance for the layout design described in <FIG>. Referring to <FIG>, the resistive network <NUM> can be set to block the current flow through the metal <NUM> layer, which would include the connection between the drain region of the transistor <NUM> and the gate region of the transistor <NUM>. This condition can correspond to a situation where the substrate, diffusion, metal <NUM>, and metal <NUM> layers have all been manufactured, but the metal <NUM> layer has yet to be manufactured. A simulator can apply an injected current <NUM> at the source region of the transistor <NUM> and detect whether the source region of the transistor <NUM> received the current <NUM>. The presence of received current <NUM> on the source region of the transistor <NUM> indicates the source regions of the two transistors <NUM> and <NUM> connect with each other via the resistive intervening circuitry <NUM>, and that the connection has been made prior to manufacture of the connection between the drain region of the transistor <NUM> and the gate region of the transistor <NUM>.

Referring back to <FIG> and <FIG>, in some embodiments, the layer condition system <NUM>, in a block <NUM>, can set resistor values of the connection between the gate of the victim transistor and the aggressor transistor to unblock current to flow through the connection. This condition set by the layer condition system <NUM> can correspond to when the connection between the gate of the victim transistor and the aggressor transistor has been manufactured. In some embodiments, the connectivity system <NUM>, in a block <NUM>, can simulate the resistive network with the set resistor values for the connection to determine electrical connectivity of the connection between the gate of the victim transistor and the aggressor transistor. Although the simulation of the layer conditions has been shown as being performed serially, in some embodiments, the layer condition system <NUM> can generate a matrix with the different conditions and their corresponding resistor values in each layer, and the simulator <NUM> can simulate the resistive network across the different conditions in parallel. The matrix and the different conditions can correspond to different connection paths through the different layers and polygons in the layout design <NUM>, which can be associated with the connectivity rules <NUM>. In some embodiments, the matrix can be populated with the different conditions determined by the connectivity system <NUM> or that were received by the reliability verification system <NUM> via user input. The ability to allow user-based control over whether an entire layer or specific polygons within a layer form a path between victim and aggressor transistors can add flexibility for analysis of layout designs <NUM> having differing construction requirement, such as in multi-chip module for three-dimensional integrated circuits (3DIC). Embodiments of simulating the resistive network with unblocked current flow through the connection between a gate of the victim transistor and the aggressor transistor will be described below in greater detail with reference to <FIG>.

<FIG> illustrates an example path-based layer stack connectivity check for plasma induced damage avoidance for the layout design described in <FIG>. Referring to <FIG>, the resistive network <NUM> can be set to unblock the current flow through the metal <NUM> layer, which would include the connection between the drain region of the transistor <NUM> and the gate region of the transistor <NUM>. This condition can correspond to a situation where all of the layers-substrate through metal <NUM>-have been manufactured. A simulator can apply an injected current <NUM> at the drain region of the transistor <NUM> and detect whether the gate region of the transistor <NUM> received the current <NUM>. The presence of received current <NUM> on the gate region of the transistor <NUM> indicates the connection to the gate region of the transistor <NUM> has been manufactured.

Referring back to <FIG> and <FIG>, the reliability verification system <NUM> can include a report system <NUM> to, in a block <NUM>, apply one or more of the connectivity rules to the connectivity determined during the simulation(s) to ascertain whether the portion of the layout design can be manufactured to avoid plasma induced damage to a gate dielectric of a victim transistor. The report system <NUM> can analyze the intervening circuitry in the portion of the layout design <NUM> to determine whether the connection has been made through an intermediate well, often called a soft connect between aggressor and victim transistors. The report system <NUM> can generate a connectivity report <NUM> based on the results determined from the application of the connectivity rules <NUM> to the connectivity determined during the simulation(s). The connectivity report <NUM> can identify which portions of the layout design <NUM> conforms or do not conform with the connectivity rules <NUM> and/or whether any connections were made through a soft connection via an intermediate well.

The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and/or methods described herein may be performed by an apparatus, a device, and/or a system substantially similar to those as described herein and with reference to the illustrated figures.

The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I/O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. "Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and/or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.

While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

Claim 1:
A method comprising:
Identifying (<NUM>), by a computing system, a portion of a layout design (<NUM>) describing an integrated circuit (<NUM>) includes a victim transistor (<NUM>, <NUM>) having a gate connected to an aggressor transistor (<NUM>, <NUM>), wherein the victim transistor (<NUM>, <NUM>) and the aggressor transistor (<NUM>, <NUM>) have wells;
Extracting (<NUM>), by the computing system, a resistive network (<NUM>) for connections between the victim transistor (<NUM>, <NUM>) and the aggressor transistor (<NUM>, <NUM>); and
Simulating (<NUM>), by the computing system, the resistive network (<NUM>) to determine connectivity between the wells of the victim transistor (<NUM>, <NUM>) and the aggressor transistor (<NUM>, <NUM>) occurs prior to the victim transistor (<NUM>, <NUM>) having the gate connected to the aggressor transistor (<NUM>, <NUM>) to ascertain whether manufacture of the portion of the layout avoids plasma induced damages.