Patent Description:
<CIT> discloses a system for in-situ launch and capture clock generation. The in-situ capture and launch clocks are to be used for testing path delay faults and transition faults.

In accordance with at least one example of the disclosure, an integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

In accordance with at least one example of the disclosure, a method implemented by an integrated circuit comprises receiving, by a synchronizing circuit, a scan enable signal; providing, by the synchronizing circuit, a synchronizing signal based on the scan enable signal; receiving, by a clock leaker circuit, a first clock signal based on the synchronizing signal; providing, by the clock leaker circuit, a second clock signal that includes a set of pulses; receiving, by a multiplexer (MUX), a shift clock at a first input of the MUX and a second clock signal at a second input of the MUX; and providing, by the MUX, an output clock signal that includes a second set of pulses at an output of the MUX.

In DSM processes, defects like high impedance metal, high impedance shorts, and cross talk may not be detectable by traditional stuck-at fault tests, and may only show-up as timing failures via at-speed tests during testing. At-speed tests include transition fault testing and path delay fault testing. During a transition fault test, a mode of operation (e.g., an initialization cycle, a launch cycle, and/or a capture cycle, etc.) may be based on a state (e.g., a state '<NUM>' or a state '<NUM>') of a scan enable signal. The at-speed scan enable signal controls the mode of operation (e.g., the initialization/shift cycle/phase, the launch phase, and/or the capture phase, etc.). Both of the above at-speed tests input test patterns by scanning them into shift register(s) of a digital logic circuit at a slow speed during the shift phase at a clock frequency that is slower than the functional clock frequency applied during the launch and capture phase. After the test pattern is scanned in during the shift phase, clock pulses are applied at full speed during the launch and capture phases. One clock pulse launches a transition timing operation and a second clock pulse clocks a capture of the output transition for a respective path. The captured result can be scanned out during another shift phase, usually at slow speed and compared with an expected response or programmed value.

Generally, clock shaper circuits (such as clock leaker circuits) are logic circuits that provide a clock pulse or a set of clock pulses (e.g., in a test operation). These clock pulses are useful for transition fault testing or stuck-at fault testing of an integrated circuit-under-test (e.g., a cluster of flip-flops in a SoC) during the test operation. In some examples, clock shaper circuits are useful to provide a single clock pulse during stuck-at fault testing or a set of clock pulses during transition fault testing. In an example, for at-speed transition fault testing, the logic circuits provide the clock pulses to the integrated circuit-under-test (CUT)having a functional clock frequency of the integrated CUT. In an example, the logic circuits may be implemented together with the integrated CUT in a SoC. Further, in a shift phase, the clock shaper circuit receives a logic high scan enable signal that is also provided to the integrated CUT. In the launch and capture phase, the scan enable signal transitions to a logic low to cause the clock shaper circuit to provide a set of clock pulses to the integrated CUT in order to perform transition fault testing on the integrated CUT.

In an at-speed transition fault test of the integrated CUT, automatic test equipment (ATE) (e.g., a tester) loads a test pattern that includes programmed data vectors/scan vectors (e.g., data stream of '<NUM>' and '<NUM>' bits) into the integrated CUT in the shift phase. The ATE may load each data bit into the integrated CUT at a slow speed responsive to providing a shift clock frequency to the integrated CUT. As used herein, a 'slow speed' indicates clock signals that operate at a lower frequency than a functional clock frequency of clock signals (e.g., from a phase-locked loop (PLL) clock) provided to the integrated CUT and that corresponds to the operating frequency of the integrated CUT. In the shift phase, the ATE also applies a logic high (e.g., logic <NUM>) scan enable signal to a clock shaper circuit and to the integrated CUT. Once the test pattern is loaded into the integrated CUT, the scan enable signal transitions to a logic low signal and begins the launch and capture phase. In an example, the clock shaper circuit provides the set of clock pulses to the integrated CUT for transition fault testing by the ATE in the launch and capture phase.

In at-speed transition fault testing of the integrated CUT, the logic circuits of the clock shaper circuit operate at the functional clock frequency of the integrated CUT while providing the clock pulses to the integrated CUT such as, for example, clock pulses at the clock frequency of a PLL clock. Further, responsive to the ATE providing the scan enable signal to the integrated CUT, the clock shaper circuit provides, during the launch and capture phase, the clock pulses to the integrated CUT. Therefore, to provide the clock pulses at-speed (e.g., at the functional clock frequency of the integrated CUT) after the scan enable signal is applied to the integrated CU, minimum wait cycles are inserted into the clock shaper circuit that cause the scan enable signal to be applied to the integrated CUT before the clock pulses are applied to the integrated CUT. If the scan enable signal is provided to the integrated CUT before or about the same time the clock pulses are provided to the integrated CUT, the ATE may not be able to perform transition fault testing of the integrated CUT.

Generally, minimum wait cycles in a timing path provide a delay between the time the scan enable signal reaches the integrated CUT and the time the clock pulses are applied to the integrated CUT. A minimum wait cycle for at-speed transition delay fault testing may be implemented by logic circuits that operate at the clock frequency of the integrated CUT. In an example, minimum wait cycles are implemented by pulse generators (e.g., a finite state machine (FSM) or clock cycles from a PLL) in a clock shaper circuit. These FSM or PLL circuits insert timing delays in a timing path of the clock shaper circuit for providing the clock pulses (e.g., clock pulse timing path) after the scan enable signal reaches the integrated CUT. The timing delays delay a time at which the clock shaper circuit initiates generation of the clock pulses based on a trigger signal to later than the time the scan enable is applied to the integrated CUT. In an example, the trigger signal may be a scan enable signal from the ATE. As used herein, the clock pulse timing path is the path between an input and an output with the maximum delay to cause the clock shaper circuit to provide the clock pulses to the integrated CUT and that does not require more time to provide the clock pulses than the available clock cycle. However, clock shaper circuits with FSM or PLL circuits add additional logic depth in the clock pulse timing path. As used herein, logic depth is the sum of the logic gates in the clock pulse timing path which receive the scan enable signal from the ATE as a trigger signal that causes the clock shaper circuit to provide the clock pulses to the integrated CUT. In integrated CUTs with <NUM> nanometer (nm) CMOS technology (e.g., DSM CMOS technology), the operating frequency is generally in the range of about <NUM> gigahertz (GHz) to about <NUM>. clock shaper circuits with FSMs or PLLs are generally able to provide the clock pulses for at-speed testing of an integrated CUT that operates up to about <NUM>. However, to perform at-speed testing of integrated CUT in the frequency range of about <NUM> to about <NUM>, logic gates may be useful that operate at these higher frequencies. In an example, in the clock pulse timing path, each logic gate may have a programmed delay to the propagating signal of about <NUM> picoseconds (ps). However, the clock shaper circuits may have to provide the clock pulses in the launch and capture phase with a programmed delay that does not exceed about <NUM> ps (e.g., for an integrated CUT operating at about <NUM>). At least some clock shaper circuits based on FSMs or PLLs for at-speed testing at these higher frequencies add additional wait cycles in the clock pulse timing path, causing the logic depth in the clock pulse timing path to exceed <NUM> (and thereby causing the programmed delay to exceed <NUM> ps). Further, the logic depth of clock of shaper circuits with FSMs or PLLs at the higher frequencies of about <NUM> to about <NUM> may not be able to synchronize the scan enable signal with the clock pulses, which can impede at-speed transition fault testing of an integrated CUT in the frequency range of about <NUM> to about <NUM>.

Disclosed herein are examples of a clock shaper circuit that provides clock pulses for at-speed transition fault testing of an integrated CUT. In an example, a clock shaper circuit may provide two clock pulses or multiple clock pulses for transition delay fault testing or a single clock pulse for other fault testing of an integrated CUT. The clock shaper circuit includes logic circuits that operate at a functional clock frequency in the range of about <NUM> to about <NUM>, such as the functional clock frequency of an integrated CUT. In an example, the clock shaper circuit receives a logic high scan enable signal from an ATE in the shift phase that is useful to load (scan in) test vectors into an integrated CUT, to load clock configuration vectors into the clock shaper circuit, and to provide a synchronized scan enable signal to the integrated CUT. Once the test vectors are loaded, the scan enable signal transitions to a logic low that begins a launch and capture phase of transition fault testing. In an example, the scan enable signal may transition its output to a logic low signal that is useful in the launch and capture phase to trigger the clock shaper circuit to provide a set of clock pulses to the integrated CUT at the functional clock frequency of the integrated CUT. In an example, the synchronizing circuit includes logic circuits that have a logic depth in a clock pulse timing path that may not exceed <NUM>. In an example, the clock shaper circuit provides a number of wait cycles during the launch and capture phase such that the synchronized scan enable signal is provided to the integrated CUT in the shift phase before the set of clock pulses are provided to the integrated CUT in the launch and capture phase.

<FIG> is a block diagram of a clock shaper circuit <NUM> (e.g., a logic circuit) for providing clock pulses, in accordance with various examples. In an example, the clock shaper circuit <NUM> may provide two clock pulses in a test operation that are applied to an integrated CUT. The clock pulses may correspond to a functional clock frequency of the integrated CUT. While the clock shaper circuit <NUM> described herein is useful for generating two clock pulses that are applied to an integrated CUT, in various examples any number of clock pulses may be provided by the clock shaper circuit <NUM> for performing testing of the integrated CUT. In various examples, the clock shaper circuit <NUM> is implemented as a standalone device (e.g., implemented on its own substrate, enclosed within its own chip package, etc.) or is implemented with the integrated CUT and other electrical devices in a SoC. In an example, the clock shaper circuit <NUM> provides a two-clock pulse for at-speed transition fault testing of an integrated CUT that operates in a frequency range of about <NUM> to about <NUM> from signals that are applied to the clock shaper circuit <NUM> from an external tester <NUM> (e.g., ATE).

As shown in <FIG>, the clock shaper circuit <NUM> includes a synchronizing circuit <NUM>, an integrated clock gating (ICG) circuit <NUM>, a clock leaker circuit <NUM>, an AND gate <NUM>, a shaping ICG circuit <NUM>, a multiplexer (MUX) <NUM>, an AND gate <NUM>, a MUX <NUM>, and inverters <NUM>, <NUM>, <NUM>, and <NUM>. In some examples, the synchronizing circuit <NUM>, an ICG circuit <NUM>, clock leaker circuit <NUM>, AND gate <NUM>, shaping ICG circuit <NUM>, MUX <NUM>, AND gate <NUM>, MUX <NUM>, and inverters <NUM>-<NUM> and <NUM> are electrically coupled together by way of wires, metal traces on a printed circuit board, metal routing on a silicon substrate, or any other suitable form of conductive coupling. In an example, the clock shaper circuit <NUM> may receive signals from the external tester <NUM> (e.g., ATE), which may be coupled to the clock shaper circuit <NUM> for providing the two clock pulses that are applied to an integrated CUT, such as integrated CUT <NUM>. In some examples, the signals from the external tester <NUM> may include a shift clock signal (SHIFT_CLK) having a shift frequency, clock signal (PLL_CLK) having a functional clock frequency that is greater than the shift frequency and that corresponds to an operating frequency of the integrated CUT, clock pulse configuration vectors (CONF_VECTORS), a scan enable signal (SCAN_EN), and transition fault test enable signal (TFT_EN) that may be received by the clock shaper circuit <NUM> via independent couplings from the external tester <NUM> to the clock shaper circuit <NUM>.

As shown in <FIG>, the synchronizing circuit <NUM> may be coupled to the inverters <NUM>, <NUM>, and <NUM>, and the MUX <NUM>. In an example, the synchronizing circuit <NUM> includes shift registers <NUM>, <NUM>, <NUM>, and <NUM> (which may be referred to herein as shift registers <NUM>-M) that are arranged as a cascade of flip-flops. In an example, while the synchronizing circuit <NUM> is shown with shift registers <NUM>-M, additional shift registers may be implemented. In an example, the shift registers <NUM>, <NUM>, <NUM>, and <NUM> may be D flip-flops. However, other types of flip-flops may be suitable, such as S-R or J-K type flip-flops. In an example, each output node (e.g., the Q node) of a respective shift register of the shift registers <NUM>-<NUM> is coupled to an input node (e.g., the D node) of an immediately adjacent downstream shift register of the shift registers <NUM>-<NUM>. In an example, the output node of shift register <NUM> is coupled to the input node of shift register <NUM>, the output node of shift register <NUM> is coupled to the input node of shift register <NUM>, and the output node of shift register <NUM> is coupled to the input node of shift register <NUM>. While synchronizing circuit <NUM> is shown with shift registers <NUM>-<NUM>, in some examples, additional shift registers similar to the shift registers <NUM>-<NUM> may be included. As explained further below, the shift registers <NUM>-<NUM> are coupled so that an output of the last shift register in the synchronizing circuit <NUM> (e.g., shift register <NUM>) provides a signal SCAN_EN_SYNC[M] that is based on the SCAN_EN provided by the tester <NUM> and delayed by a number of cycles of the PLL_CLK equal to the number of shift registers <NUM>-<NUM>. This signal SCAN_EN_SYNC[M] is useful to control a clock (LKR_SHIFT_CLK) applied to the clock leaker circuit <NUM>.

The output of the first shift register <NUM> in the chain of shift registers <NUM>-<NUM> is also coupled to an input of the MUX <NUM> to provide a signal SCAN_EN_SYNC[<NUM>] that is based on SCAN_EN being provided by the tester <NUM> and delayed by a cycle of the PLL_CLK. In an example, the MUX <NUM> may be implemented as a <NUM>-to-<NUM> multiplexer with a high-side input node (e.g., input '<NUM>'), a low-side input node (e.g., input '<NUM>'), a select input node, and an output node. In an example, the logic value at low-side input node will be reflected at the output node in response to the select input node being held to a logic low (e.g., logic <NUM>). In an example, the logic value at high-side input node will be reflected at the output node in response to the select input node being held at a logic high (e.g., logic <NUM>). In an example, the output node of shift register <NUM> is coupled to the inverters <NUM> and <NUM>, and to the high-side input node of the MUX <NUM>. The output node of the shift register <NUM> is coupled to the input node of the inverter <NUM>. In an example, each of the shift registers <NUM>-<NUM> receives PLL_CLK from a PLL or another clock circuit (not shown) coupled to the external tester <NUM>. In an example, PLL_CLK has a same frequency as the functional clock frequency of the integrated CUT. In an example, the PLL_CLK is configured to drive the shift registers <NUM>-<NUM> in the synchronizing circuit <NUM>. In an example, SCAN_EN is applied to the shift register <NUM> via a scan enable signal line, to the low-side input node of the MUX <NUM>, and to the AND gate <NUM> via the inverter <NUM>.

In an example, each shift register <NUM>-<NUM> inserts a programmed delay into the clock pulse timing path such that an output signal that is provided from a respective shift register <NUM>-<NUM> meets the timing requirements for generating the two clock pulses in the launch and capture phase. In an example, based on the timing requirements, SCAN_EN is applied to the clock shaper circuit <NUM> in the shift phase to initiate providing of the two clock pulses during the launch and capture phase. Further, in an example, a synchronized scan enable signal HS_SCAN_EN is provided by the clock shaper circuit <NUM> to the integrated CUT <NUM> before the two clock pulses are provided to the integrated CUT <NUM>. In an example, the clock pulse timing path from the synchronizing circuit <NUM> to the clock leaker circuit <NUM> includes the programmed delays in logic gates including the shift register <NUM> and the inverter <NUM>, or the programmed delays in other logic gates including the shift register <NUM> and the inverter <NUM>.

In an example, the shift register <NUM> adds a programmed delay to an output signal from the shift register <NUM> in response to SCAN_EN that is applied at an input node of the shift register <NUM>. In an example, the logic high SCAN_EN initiates loading/shifting the CONF VECTORS into the clock shaper circuit <NUM> during the shift phase. In another example, the shift registers <NUM>-<NUM> add additional programmed delays to the output signals that are provided from a respective shift register to an adjacent and downstream shift register <NUM>-<NUM>. In an example, each of the shift registers <NUM>-<NUM> provides a programmed delay in lieu of other solutions that include FSMs or PLLs to provide the timing requirements during the launch and capture phases, increasing the logic depth of the clock pulse timing path.

In an example, the clock leaker circuit <NUM> includes shift registers <NUM>, <NUM>, <NUM>, and <NUM> (which may be referred to herein as shift registers <NUM>-N) that are arranged as a cascade of parallel-input, serial-output shift registers. In an example, while the clock leaker circuit <NUM> is shown with shift registers <NUM>-N, additional shift registers may be included. In an example, shift registers <NUM>, <NUM>, <NUM>, and <NUM> may be implemented as D flip-flops. However, other types of flip-flops such as S-R flip-flops, J-K flip-flops, or a combination of D, S-R, and J-K flip-flops may be included. In an example, each input node (e.g., the D node) of the shift registers <NUM>-<NUM> is coupled to an output node of a respective MUX of the MUXs <NUM>-<NUM> and each output node (e.g., the Q node) of the shift registers <NUM>-<NUM> is coupled to an input node of an adjacent MUX of a downstream shift register. In some examples, the input node of the shift register <NUM> is coupled to the output node of the MUX <NUM>, and the output node of the shift register <NUM> is coupled to the low-side input node of the MUX <NUM>, the input node of the shift register <NUM> is coupled to output node of the MUX <NUM>, and output node of the shift register <NUM> is coupled to low-side input node of the MUX <NUM>, and the input node of the shift register <NUM> is coupled to output node of the MUX <NUM>, and the output node of the shift register <NUM> is coupled to low-side input node of the MUX <NUM>. In an example, an input node of shift register <NUM> is coupled to the output node of the MUX <NUM>, and the output node of shift register <NUM> is coupled to the AND gate <NUM>. In an example, the MUXs <NUM>-<NUM> may be implemented as <NUM>-to-<NUM> multiplexers substantially similar to the MUX <NUM> with a high-side input node (e.g., input 'D1'), a low-side input node (e.g., input 'D0'), a select input node (e.g., select 'S0'), and an output node.

In an example, the high-side input nodes of the MUXs <NUM>-<NUM> are coupled to a data line to receive CONF_VECTORS as '<NUM>' or '<NUM>' data bits. In an example, CONF_VECTORS include a programmed sequence of data bits having '<NUM>' and '<NUM>' in which two consecutive '<NUM>' bits (e.g., two consecutive logic high bits sequence with leading and trailing zeros may be `<NUM>') may provide the two clock pulses responsive to the CONF _VECTORS that are shifted out of the clock leaker circuit <NUM> into the shaping ICG circuit <NUM>. In an example, the leading zeros of CONF_VECTORS provide a programmed delay to the shifting out the consecutive '<NUM>' bits by clock leaker circuit <NUM> during the launch and capture phase. The trailing zero may indicate an end to the operation for providing the clock pulses. In an example, other clock pulses may be provided (e.g., a one clock pulse, three clock pulses, or any number of clock pulses) based on a number of the programmed consecutive '<NUM>' bits that are to be loaded into the shift registers <NUM>-<NUM> according to CONF_VECTORS. In an example in which three-clock pulses are provided by the clock shaper circuit <NUM>, data vectors that include three consecutive '<NUM>' data bits after a set of leading zeros in the CONF _VECTORS may be loaded into the clock leaker circuit <NUM>. In an example, the CONF _VECTORS may provide the two clock pulses responsive to being loaded into the MUXs <NUM>-<NUM> and shifted out based on a clock signal that is applied to the MUXs <NUM>-<NUM>.

In an example, the MUXs <NUM>-<NUM> may provide CONF _VECTORS into each of the shift registers <NUM>-<NUM> based on output clock pulses (LKR_SHIFT_CLK), as received at the clock inputs of the MUXs <NUM>-<NUM>. In an example, each of the shift registers <NUM>-<NUM> is coupled to an output node of the ICG circuit <NUM> and receives LKR_SHIFT_CLK from the ICG circuit <NUM>. LKR_SHIFT_CLK drives the shift registers in the clock leaker circuit <NUM> to load the CONF_VECTORS into the clock leaker circuit <NUM> and provide the two pulses (e.g., LKR_CLK_OUT) from the clock shaper circuit <NUM> based on the programmed sequence of data bits.

In an example, the ICG circuit <NUM> receives PLL_CLK at an input node and receives an enable signal at an enable node from an output of the inverter <NUM>. In an example, the PLL_CLK is configured to drive the shift registers <NUM>-<NUM> in the clock leaker circuit <NUM> such that clock pulses from the PLL_CLK serially shift the CONF VECTORS through the shift registers <NUM>-<NUM> in response to a clock gating signal that is deasserted at the clock leaker circuit <NUM>. In an example, the ICG circuit <NUM> is clock gated (e.g., clock gating signal is asserted) with a logic low enable signal (e.g., ICG circuit <NUM> is turned OFF with a logic low signal) such that LKR_SHIFT_CLK is not provided at the output node of the ICG circuit <NUM> (e.g., ICG circuit <NUM> is clock gated). Clock gating the ICG circuit <NUM> prevents the LKR_SHIFT_CLK from being applied to the clock nodes of the shift registers <NUM>-<NUM> and prevents serially shifting the data bits through the shift registers <NUM>-<NUM>. In an example, the ICG circuit <NUM> may be ungated with a logic high enable signal to initiate generation of the two clock pulses. In an example, applying a logic high enable signal to the enable node of ICG circuit <NUM> ungates the ICG circuit <NUM> (e.g., ICG circuit <NUM> is turned ON with a logic high signal) and causes LKR_SHIFT_CLK to propagate to the output node of the ICG circuit <NUM>.

In an example, a first input of the AND gate <NUM> is coupled to the output node of the shift register <NUM> via the inverter <NUM>, a second input of the AND gate <NUM> is coupled to the output node of the shift register <NUM>, and a third input of the AND gate <NUM> is coupled to a transition fault testing signal line to receive a transition fault test enable signal (TFT_EN). In an example, a first input of the AND gate <NUM> is coupled to the scan enable signal line via the inverter <NUM> and receives an inverted output of SCAN_EN. In an example, a second input of the AND gate <NUM> is coupled to the transition fault testing signal line to receive TFT_EN. In an example, TFT_EN is held high during the shift phase and during the launch and capture phase, and does not change its state during at-speed transition fault testing of the integrated CUT <NUM>. In an example, TFT_EN is held low for another test mode such as stuck-at fault testing. In an example, the shaping ICG circuit <NUM> is coupled at a first input node to the output of the AND gate <NUM> for receiving an enable signal (LKR_SHAPE_EN) and at a second input node to a clock circuit for receiving the PLL_CLK. The output of the shaping ICG circuit <NUM> is coupled to a high-side input node of the MUX <NUM>. The low-side input node of the MUX <NUM> is coupled to a signal line for receiving a SHIFT_CLK, and the output node of the MUX <NUM> is coupled to the integrated CUT <NUM>. In an example, the MUX <NUM> may be implemented as a <NUM>-to-<NUM> multiplexer that is substantially similar to the MUX <NUM> with a high-side input node (e.g., input 'D1'), a low-side input node (e.g., input 'D0'), a select input node (e.g., select 'S0'), and an output node. In an example, SHIFT _CLK is a "slow" clock (e.g., having a clock frequency that is lower than a frequency of PLL_CLK). In an example, SHIFT _CLK is configured to shift the CONF _VECTORS into the clock leaker circuit <NUM> during the shift phase. In an example, the high-side input node of the MUX <NUM> is coupled to the output node of the shift register <NUM> of the synchronizing circuit <NUM>, the low-side input node of the MUX <NUM> is coupled to the scan enable signal line to receive SCAN_EN, and the output of the MUX <NUM> is coupled to the integrated CUT <NUM>.

In an example operation, the clock shaper circuit <NUM> may receive the SCAN_EN. During a shift phase where the SCAN_EN is high, the MUX <NUM> provides the SHIFT_CLK to the integrated CUT <NUM> as LKR_CLK_OUT for use in loading (scanning in) a test pattern into latches of the integrated CUT <NUM>. Once the test pattern is loaded into the integrated CUT <NUM>, the SCAN_EN signal transitions and begins a launch and capture phase of, for example, transition fault testing. In an example, the SCAN_EN may transition its output state from a high state (e.g., logic high) to a low state (e.g., logic low) to trigger the clock leaker circuit <NUM> to provide the set of functional frequency clock pulses as LKR_CLK_OUT. The clock shaper circuit <NUM> provides the clock pulses in a launch and capture phase after a synchronized scan enable signal (HS_SCAN_EN) is provided to the integrated CUT <NUM> in the shift phase. In an example, the clock pulses are useful for an external tester to perform transition fault testing of the integrated CUT. In an example, during a transition fault testing mode, a logic high TFT_EN is applied to the AND gate <NUM> during the shift phase and maintained at logic high during the transition fault testing. In an example, other inputs to the AND gate <NUM> are at a logic high in the launch and capture phase. The logic high inputs to the AND gate <NUM> causes the AND gate <NUM> to provide a logic high signal to the shaping ICG circuit <NUM>, which triggers the shaping ICG circuit <NUM> to provide LKR_CLK_OUT with the two clock pulses responsive to the PLL_CLK during the duration of the logic high enable signal LKR_SHAPE_EN at the shaping ICG circuit <NUM>. In an example, for stuck-at fault testing of an integrated CUT <NUM> based on two clock pulses not being useful for testing the integrated CUT <NUM>, the TFT_EN is held at logic low and the SCAN_EN is held at logic high, which is inverted by the inverter <NUM> to provide a logic low signal to an input of the AND gate <NUM>. The output node of the AND gate <NUM> is coupled to the MUX <NUM>. In an example, in response to the SCAN_EN being held at logic high, the AND gate <NUM> provides a logic low signal to the MUX <NUM>. In an example, the logic low signal to MUX <NUM> causes the PLL_CLK to be bypassed while the SHIFT _CLK is propagated to the integrated CUT <NUM>. The clock shaper circuit <NUM> disclosed herein is configured to provide a minimum number of wait cycles in a synchronizing circuit based on a scan enable signal that is received such that two clock pulses are provided to an integrated CUT before a synchronized scan enable signal is provided to the integrated CUT <NUM>. In an example, the clock shaper circuit <NUM> disclosed herein includes logic gates in a clock pulse timing path that does not exceed a logic depth of <NUM> and provides the two clock pulses that is useful for at-speed transition fault testing of the integrated CUT <NUM> in the frequency range of about <NUM> to about <NUM>.

<FIG> is a waveform diagram <NUM> that shows a test operation of the clock shaper circuit <NUM> of <FIG>, in accordance with various examples. In an example, the test operation includes a shift phase <NUM> in which a set of test vectors are shifted into shift registers of an integrated CUT <NUM> according to a scan clock LKR_SHIFT_CLK and provided by a clock shaper circuit <NUM> to the integrated CUT <NUM> as a set of clock pulses LKR_CLK_OUT. In an example, the test operation may include loading clock configuration vectors CONF_VECTORS into a clock leaker circuit <NUM> of the clock shaper circuit <NUM>. The test operation further includes a launch and capture phase <NUM> in which a set of clock pulses <NUM> specified by CONF_VECTORS are provided by the clock shaper circuit <NUM> via LKR_CLK_OUT and based on a transition of SCAN_EN. In an example, an external ATE (e.g., tester <NUM> in <FIG>) may provide signals to the clock shaper circuit <NUM> for implementing the test operation of the clock shaper circuit <NUM> described herein.

With continued reference to <FIG>, in the shift phase <NUM>, SCAN_EN is held at a logic high and applied to the clock leaker circuit <NUM> to shift a set of test vectors into the integrated CUT <NUM> and to load CONF _VECTORS into the clock leaker circuit <NUM>. In an example, CONF _VECTORS are applied to the clock leaker circuit <NUM> and the PLL_CLK is applied to the ICG circuit <NUM>. Low frequency pulses from SHIFT_CLK are applied to low-side input node of the MUX <NUM> during the shift phase <NUM>. In an example, a logic high SCAN_EN is inverted by the inverter <NUM>, which causes the MUX <NUM> to provide the SHIFT_CLK based on a logic low signal at the select input node of the MUX <NUM>. In an example, CONF_VECTORS are shifted into the MUXs <NUM>-<NUM> of the clock leaker circuit <NUM> responsive to the SCAN_EN being applied to the synchronizing circuit <NUM>. In an example, the SCAN_EN is a logic high signal and the TFT_EN is a logic high signal. In an example, the logic high SCAN_EN is applied to an input node of the shift register <NUM> and to the low-side input node of the MUX <NUM>. Further, PLL_CLK is applied to the shift registers <NUM>-<NUM> and to the ICG circuit <NUM>. In an example, PLL_CLK is applied to the clock input of the shift registers <NUM>-<NUM> and to the input node of the ICG circuit <NUM>.

In an example, applying a logic high SCAN_EN to the shift register <NUM> produces an output signal (SCAN_EN_SYNC[<NUM>]), which is a logic high signal at the output node of the shift register <NUM> responsive to PLL_CLK being applied to the clock input of the shift register <NUM>. In the shift phase <NUM>, the SCAN_EN_SYNC[<NUM>] is applied to the input of the inverters <NUM> and <NUM>, and to the high-side input node of the MUX <NUM>, and TFT_EN is held high. In an example, TFT_EN is applied to the select input node of the MUX <NUM>. A logic high TFT_EN causes SCAN_EN_SYNC[<NUM>] at the high-side input node of the MUX <NUM> to be provided from the output node of the MUX <NUM> as synchronized scan enable signal HS_SCAN_EN. In an example, based on programmed delays that are configured into the synchronizing circuit <NUM> and the clock leaker circuit <NUM>, HS_SCAN_EN is provided to the integrated CUT <NUM> in the shift phase <NUM> before SCAN_EN that is applied to the clock shaper circuit <NUM> in the launch and capture phase <NUM> provides the two clock pulses LKR_CLK_ OUT <NUM> that is provided from the MUX <NUM>.

In an example, in the shift phase <NUM>, the inverters <NUM> and <NUM> invert the logic high SCAN_EN_SYNC[<NUM>] to a logic low signal. The logic low signals are applied to the select input node of MUXs <NUM>-<NUM> and to the AND gate <NUM>. Applying the logic low signals from inverter <NUM> to the MUXs <NUM>-<NUM> cause CONF _VECTORS to be loaded into the shift registers <NUM>-<NUM>. The data bits in the shift registers <NUM>-<NUM> is not shifted into the shift registers <NUM>-<NUM> until LKR_SHIFT_CLK is applied to each clock input of the shift registers <NUM>-<NUM>. As a logic low signal is applied to the enable node of the ICG circuit <NUM>, the ICG circuit <NUM> is gated OFF and LKR_SHIFT_CLK is not applied as clock signals to the shift registers <NUM>-<NUM> which prevents CONF_VECTORS at the input nodes of the shift registers <NUM>-<NUM> from being serially shifted from the shift register <NUM> to the shift register <NUM> and then to the AND gate <NUM>.

In an example, SCAN_EN_SYNC[<NUM>] is an output signal at the output node of the first shift register <NUM> that propagates through shift registers <NUM>-<NUM> during each clock pulse of PLL_CLK. SCAN_EN being logic high causes each shift register <NUM>-<NUM> to output a logic high signal at their respective output nodes with shift register <NUM> providing a logic high signal SCAN_EN_SYNC[M] at the output node of shift register <NUM> (e.g., Mth shift register). In an example, SCAN_EN_SYNC[M] is a trigger signal that starts the two clock pulse generation by the clock leaker circuit <NUM>.

In an example, the logic high signal at the input node of shift register <NUM> propagates through the shift registers <NUM>-<NUM> based on receiving clock cycles from PLL_CLK. Each input logic high signal that is provided by the shift registers <NUM>-<NUM> is delayed by a programmed delay by a respective shift register of the shift registers <NUM>-<NUM> in the synchronizing circuit <NUM>. The shift register <NUM> inserts one programmed delay to the logic high SCAN_EN_SYNC[<NUM>] at the output node of the shift register <NUM>, which is applied to the MUX <NUM>. Further, the shift registers <NUM>-<NUM> may add three additional programmed delays to the logic high SCAN_EN_SYNC[M] that is provided at the output node of the shift register <NUM>. The logic high SCAN_EN_SYNC[M] is inverted by the inverter <NUM>, which causes the ICG circuit <NUM> to be gated OFF and prevents the ICG circuit <NUM> from providing LKR_SHIFT_CLK.

In an example, during the launch and capture phase <NUM>, SCAN_EN is transitioned from a high state (e.g., logic high) to a low state (e.g., logic low). In an example, a logic low signal is applied at the input node of the shift register <NUM> that causes SCAN_EN_SYNC[<NUM>] at the output node of shift register <NUM> to transition from a logic high to a logic low during the rising edge of PLL_CLK. After the first cycle (e.g., rising edge) of PLL_CLK, the shift register <NUM> outputs a logic low SCAN_EN_SYNC[<NUM>], which is applied to the input of inverter <NUM>. The inverters <NUM> and <NUM> invert the logic low SCAN_EN_SYNC[<NUM>] to a logic high signal. The logic high signal from the inverter <NUM> is applied to the select input nodes of the MUXs <NUM>-<NUM> as an enable signal to shift out the data bits from the shift registers <NUM>-<NUM>. The logic high signal from the inverter <NUM> is applied to the AND gate <NUM>. The logic low SCAN_EN_SYNC[<NUM>] at the output node of the shift register <NUM> propagates through the shift registers <NUM>-<NUM> based on each rising edge of the PLL_CLK. In an example, after the fourth cycle of PLL_CLK, the output node of the shift register <NUM> provides a logic low SCAN_EN_SYNC[M]. Each logic low signal that is provided by a respective shift register <NUM>-<NUM> is delayed by a programmed delay in the synchronizing circuit <NUM>. The logic low SCAN_EN_SYNC[<NUM>] is inverted to a logic high enable signal by the inverter <NUM>, and is applied to the enable node of the ICG circuit <NUM> as an ungating signal. In an example, the ungating signal at the ICG circuit <NUM> triggers the clock leaker circuit <NUM> to shift the CONF _VECTORS to the next shift register in the clock leaker circuit <NUM> to provide the two clock pulses for transition fault testing in response to a LKR_SHIFT_CLK that is provided to the shift registers <NUM>-<NUM>.

In an example, applying ungating signals (e.g., logic high signal) to the enable node of the ICG circuit <NUM> causes the ICG circuit <NUM> to provide LKR_SHIFT_CLK. LKR_SHIFT_CLK are clock pulses from PLL_CLK. In an example, the timing requirement for applying ungating signal to the enable node of the ICG circuit <NUM> may include programmed delays to the signals that propagate through the shift registers <NUM>-<NUM>. In an example, the inverter <NUM> and the ICG circuit <NUM> may add further propagation delays to the ungating signal applied to the ICG circuit <NUM>. In an example, LKR_SHIFT_CLK that is applied to the clock leaker circuit <NUM> to provide LKR_CLK_OUT <NUM> is delayed by a programmed delay based on each delay of the shift registers <NUM>-<NUM>.

In an example, LKR_SHIFT_CLK is applied to the clock nodes of shift registers <NUM>-<NUM>. Each rising edge of LKR_SHIFT_CLK causes CONF_VECTORS (e.g., data bits '<NUM>' or '<NUM>') at the input nodes of the shift registers <NUM>-<NUM> to be serially shifted from the shift register <NUM> to the adjacent shift registers downstream of the shift register and out of the shift register <NUM>. The CONF _VECTORS may be shifted out of the clock leaker circuit <NUM> into a first input node of the AND gate <NUM>. In an example, the other input nodes of the AND gate <NUM> receive a logic high signal from the output of inverter <NUM> and a logic high TFT_EN. In an example, based on consecutive logic high CONF _VECTORS that are provided by clock leaker circuit <NUM> and while other inputs to the AND gate <NUM> are logic high, a logic high enable signal LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit <NUM>, which ungates the shaping ICG circuit <NUM> and causes PLL_CLK to propagate to the high-side input node of the MUX <NUM> for the duration of the logic high LKR_SHAPE_EN. In an example, two consecutive logic high data bits in CONF_VECTORS cause the LKR_SHAPE_EN to be logic high for two clock cycles of PLL _CLK and provide two logic high signals to the high-side input node of the MUX <NUM>.

In an example, the inputs of the AND gate <NUM> receive an inverted output of SCAN_EN and receives TFT_EN. In the launch and capture phase, SCAN_EN is held low while TFT_EN is held high, which causes a logic high signal to be provided from the AND gate <NUM> to the select input node of the MUX <NUM>. In an example, PLL_CLK at the high-side input node of MUX <NUM> is reflected on the output node of MUX <NUM> for the duration of logic high LKR_SHAPE_EN at high side input node of the MUX <NUM> in response to the select input node of the MUX <NUM> being at logic high. In an example, in response to consecutive logic '<NUM>' CONF_VECTORS being shifted out of the clock leaker circuit <NUM>, a logic high LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit <NUM> and causes the MUX <NUM> to provide two clock pulses of PLL_CLK from the high-side input node of the MUX <NUM> in response to the select input node of the MUX <NUM> being at logic high. In an example, the LKR_SHAPE_EN is logic high for two clock cycles of PLL_CLK, which causes the MUX <NUM> to provide LKR_CLK_OUT as the two clock pulses <NUM>. In an example, the launch and capture phase <NUM> is followed by another shift phase <NUM> whereby additional CONF _VECTORS are loaded into the clock shaper circuit <NUM> and additional two clock pulses are provided based on another launch and capture phase substantially similar to launch and capture phase <NUM>. The clock shaper circuit <NUM> disclosed herein is configured to provide a minimum number of wait cycles in the launch and capture phase <NUM> in response to the SCAN_EN that is received such that two clock pulses LKR_CLK_OUT are provided to an integrated CUT <NUM> before a synchronized scan enable signal HS_SCAN_EN is provided to the integrated CUT <NUM>. In an example, the clock shaper circuit <NUM> disclosed herein includes logic gates in a clock pulse timing path that does not exceed a logic depth of <NUM> and provides the two clock pulses that is useful for at-speed transition fault testing of the integrated CUT <NUM> in the frequency range of about <NUM> to about <NUM>.

<FIG> is a flow diagram of a method <NUM> implemented on an integrated circuit, in accordance with various examples. In an example, the method <NUM> implements a clock leaker operation for generating a set of clock pulses in an integrated circuit. In an example, the integrated circuit is clock shaper circuit <NUM> that was shown and described in <FIG>.

With continued reference to <FIG> and <FIG>, in step <NUM>, data vectors are provided to the clock shaper circuit <NUM>. In an example, an external tester <NUM> (e.g., automatic test equipment) may provide the clock configuration vectors (e.g., CONF _VECTORS in <FIG>) to the MUXs <NUM>-<NUM> of a clock leaker circuit <NUM> in the clock shaper circuit <NUM> during a shift phase.

In step <NUM>, a logic high scan enable signal is applied to the clock shaper circuit <NUM>. In an example, the logic high scan enable signal SCAN_EN is applied to a shift register <NUM> of a synchronizing circuit <NUM> and clock pulses PLL_CLK are applied to the clock nodes of the shift registers <NUM>-<NUM> in a shift phase. The logic high SCAN_EN causes the shift register <NUM> to provide a logic high output signal at the output node of the shift register <NUM> on a clock pulse PLL_CLK. The logic high output signal provided at the output node of the shift register <NUM> is inverted by the inverter <NUM> to a logic low output signal and provided to select input nodes of the MUXs <NUM>-<NUM>. The logic low output signal loads CONF VECTORS into the shift registers <NUM>-<NUM> of the clock leaker circuit <NUM>. In an example, the logic high output signal from the shift register <NUM> is provided to the high-side input node of the MUX <NUM>. In an example, a logic high TFT_EN in the shift phase causes a logic high output signal at the high-side input node of the MUX <NUM> to be provided from the output node of MUX <NUM> as HS_SCAN_EN. In an example, HS_SCAN_EN is applied to the integrated CUT <NUM> before LKR_CLK_ OUT provides the set of clock pulses <NUM> in the launch and capture phase <NUM>.

In step <NUM>, a logic low scan enable signal is provided at the input to the clock shaper circuit <NUM> to shift the data bits in the clock leaker circuit <NUM>. In an example, the logic low scan enable signal SCAN_EN is applied to the shift register <NUM> of the synchronizing circuit <NUM> and PLL_CLK is applied to the clock nodes of the shift registers <NUM>-<NUM>. After the first cycle (e.g., rising edge) of PLL_CLK, the shift register <NUM> provides a logic low output signal, which is inverted by the inverter <NUM> to a logic high signal and provided to the select input node of the MUXs <NUM>-<NUM>. The logic high signal from the inverter <NUM> is provided to the select input nodes of the MUXs <NUM>-<NUM> as a gating signal for the MUXs <NUM>-<NUM>. A logic low output signal is provided by the shift register <NUM> based on the fourth cycle of PLL_CLK as a logic low SCAN_EN_SYNC[M] and is inverted to a logic high SCAN_EN_SYNC[M] by the inverter <NUM>. The logic high SCAN_EN_SYNC[M] is provided to the enable node of the ICG circuit <NUM> as an ungating signal. In an example, LKR_SHIFT_CLK is applied to the clock nodes of the shift registers <NUM>-<NUM> in response to the logic high SCAN_EN_SYNC[M] from the inverter <NUM> being provided to the enable node of the ICG circuit <NUM>. Each rising edge of LKR_SHIFT_CLK causes CONF _VECTORS (e.g., data bits '<NUM>' or '<NUM>') at the input nodes of the shift registers <NUM>-<NUM> to be serially shifted from the shift register <NUM> to the adjacent shift registers downstream of the shift register <NUM> and out of the shift register <NUM>.

In step <NUM>, LKR_SHAPE_EN is provided to an integrated clock generator (e.g., ICG circuit <NUM>) to cause the clock shaper circuit <NUM> to provide the two clock pulses. In an example, in response to the CONF _VECTORS being provided to the AND gate <NUM> as consecutive logic high inputs, a logic high enable signal LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit <NUM>, which ungates the shaping ICG circuit <NUM> for two clock cycles of PLL_CLK. In an example, two consecutive logic high data bits in CONF _VECTORS causes the LKR_SHAPE_EN to be logic high for two clock cycles of PLL_CLK and provide two logic high signals to the high-side input node of the MUX <NUM>. In an example, the inputs of the AND gate <NUM> receive logic high signals. In an example, an input to the AND gate <NUM> is a logic high signal based on inverting the logic low SCAN_EN by the inverter <NUM> and another input to the AND gate <NUM> is a logic high TFT_EN, which causes a logic high signal to be provided from the AND gate <NUM> to the select input node of the MUX <NUM>. In an example, in response to the select input node of the MUX <NUM> being kept at logic high, the PLL_CLK at the high-side input node is provided on the output node of the MUX <NUM> for the duration of the logic high LKR_SHAPE_EN. In an example, the LKR_SHAPE_EN is a logic high for two clock cycles of PLL_CLK, which causes the MUX <NUM> to provide LKR_CLK_OUT as the set of clock pulses <NUM>.

<FIG> is a block diagram of an electronic system <NUM> in accordance with various examples. For example, the electronic system <NUM> is, or is incorporated into, or is coupled to, a system such as an automobile, or any type of electronic system operable to process information. In some examples, the electronic system <NUM> includes a computing device <NUM> that includes a clock shaper circuit <NUM>, a central processing unit (CPU) <NUM>, a power supply <NUM>, an input-output (I/O) port <NUM>, a display <NUM>, a user interface (UI) <NUM>, a storage <NUM> (e.g., a random-access memory (RAM)), and a networked devices <NUM>.

In some examples, the clock shaper circuit <NUM> is clock shaper circuit <NUM> that was described in <FIG> and may be configured to receive clock signals and scan enable signals to provide a set of clock pulses for performing transition fault testing of an integrated CUT.

In some examples, the CPU <NUM> is a CISC-type (complex instruction set computer) CPU, RISC-type (reduced instruction set computer) CPU, MCU-type (microcontroller unit) CPU, or a digital signal processor (DSP). The CPU <NUM> includes one or more processor cores. The one or more processor cores are arranged to execute code for transforming the one or more processors into a special-purpose machine or improving the functions of other components in the electronic system <NUM> to provide a programmed output without performing similar operations on the one or more other processor cores. The CPU <NUM> includes memory and logic that store information frequently accessed from storage <NUM>.

The CPU <NUM> and the power supply <NUM> are coupled to the I/O port <NUM>. In an example, the I/O port <NUM> provides an interface that is configured to receive input from (and/or provide output to) the networked devices <NUM>.

In an example, a user controls the computing device <NUM> via the user interface (UI) <NUM>. In an example, during execution of software application <NUM>, a user provides inputs to the computing device <NUM> via the UI <NUM>, and receives outputs from the computing device <NUM>. In some examples, the outputs are provided via the display <NUM>, indicator lights, a speaker, vibrations and the like. The input is received as audio and/or video inputs (e.g., via voice or image recognition), and electrical and/or mechanical devices such as keypads, switches, proximity detectors, gyros, accelerometers, and the like.

In some examples, the storage <NUM> is memory such as on-processor cache, off-processor cache, RAM, flash memory, or disk storage for storing one or more software applications <NUM> (e.g., embedded application), that performs functions associated with the computing device <NUM> that are described herein in response to executing the one or more software applications <NUM> by the CPU <NUM>.

The networked device <NUM> can include any device (including test equipment) capable of point-to-point and/or networked communications with the computing device <NUM>. The computing device <NUM> is often coupled to peripherals and/or computing devices, including tangible, non-transitory media (such as flash memory) and/or cabled or wireless media. These and other input and output devices are selectively coupled to the computing device <NUM> by external devices via wireless or cabled connections. The storage <NUM> is accessible by the networked devices <NUM>. The CPU <NUM>, the storage <NUM>, and the power supply <NUM> are also optionally coupled to an external power supply (not shown), which is configured to receive power from a power source (such as a battery, solar cell, "live" power cord, inductive field, fuel cell, capacitor, and the like). While not shown in <FIG>, the power supply <NUM> includes power generating components. Power generating components include one or more power switches. Each of the power switches is independently controlled for generating power to supply power at various input voltages to various components of the computing device <NUM>. The computing device <NUM> operates in various power-saving modes wherein individual voltages are supplied (and/or turned off) by the power switches in accordance with a selected power-saving mode and the various components arranged within a specific power domain.

The term "couple" is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

A device that is "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third-party.

Claim 1:
An integrated circuit for transition fault testing, comprising:
a synchronizing circuit (<NUM>) including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal;
a clock leaker circuit (<NUM>) coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and
a multiplexer MUX (<NUM>) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.