Patent Description:
Electronic semiconductor devices are known, for example diodes or MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), in particular for electronic power applications, made starting from a silicon carbide substrate.

The above devices prove advantageous thanks to the favourable chemico-physical properties of silicon carbide. For instance, silicon carbide generally has a wider bandgap than silicon, which is commonly used in electronic power devices. Consequently, also with relatively small thicknesses, silicon carbide has a breakdown voltage higher than that of silicon and may therefore be advantageously used in high-voltage, high-power, and high-temperature applications.

Manufacturing of a silicon carbide semiconductor device is, however, affected by some problems.

For instance, problems of crystallographic quality of silicon carbide may represent an obstacle to achieving high production yields, which in general prove lower than similar devices obtained starting from silicon, consequently causing an increase in the production costs.

In particular, epitaxial processes generally used for device manufacturing tend to propagate crystallographic defects buried in the starting substrate towards the surface of the grown epitaxial layers.

In detail, propagation of TSDs (Threading-Screw Dislocations) from the substrate towards the epitaxial layer may generate, on the surface of the same epitaxial layer, pits or nano-pits (i.e., pits having nanometric dimensions, with a diameter of few nanometres, for example less than <NUM>).

It has been shown that the presence of such defects entails a reduction of the device electrical performance and in particular a drop in reliability, with a consequent reduction of the yield after electrical testing, with possible generation of high leakage currents in conditions of reverse biasing.

The aforesaid problems are particularly important for certain applications, in particular in the automotive field, where extremely low percentages of failure are allowed (for example, less than <NUM>) during effective use of the devices (in the example, on board a motor vehicle).

<FIG> shows schematically a wafer <NUM> of semiconductor material, in particular silicon carbide (SiC), comprising a substrate <NUM>, on which an epitaxial layer <NUM>, having a top surface 3a, is grown, in particular with a homo-epitaxial process. A defect, in particular a TSD, designated by <NUM>, propagates starting from the substrate <NUM> (as indicated by the arrow) towards the overlying epitaxial layer <NUM>, generating, on its top surface 3a, a surface pit <NUM>.

The presence of the surface pit <NUM>, in particular if in the active area of a corresponding power device, for example a diode or MOSFET, formed in the epitaxial layer <NUM>, may lead to a drop in the performance and reliability of the power device; for example, the surface pit <NUM> may jeopardise proper growth of subsequent layers on the top surface 3a of the epitaxial layer <NUM>, for example a dielectric layer grown via surface oxidation and/or a conductive layer designed for formation of electrodes of the power device, thus jeopardising reliability of the power device.

Studies and experimental test - see, for example, <NPL>) - have confirmed that the presence of the aforesaid surface pits (nano-pits), originating from propagation of dislocations from the substrate, effectively jeopardises device performance.

In this regard, <FIG> and <FIG> show plots of the leakage current Ileak as the reverse-biasing voltage Vr increases for a power device (in this case, a Schottky diode) made starting from a silicon carbide substrate, in the case where nano-pits are present in the active area as a result of the propagation of dislocations from the substrate (<FIG>), and in the case where there are dislocations, but these dislocations do not entail the presence of surface pits (<FIG>). From an examination of <FIG> and <FIG> it is evident that the leakage current is sensibly higher in the presence of surface pits in the active area, as compared to the case where, even in the presence of dislocations through the substrate, surface pits are not present.

Solutions that have so far been proposed to overcome the problem highlighted (see, for example, <NPL>), and in particular for reducing the effect of defects on the surface of the epitaxial layer, envisage appropriate steps aimed at improving the epitaxial growth performed starting from the silicon carbide substrate. However, since TSDs are defects of a crystallographic nature, it is not possible to prevent propagation thereof towards the epitaxial layer.

Other known solutions (see, for example,<NPL>) envisage introduction of buffer layers, interposed between the substrate and the epitaxial layer; however, also these solutions enable at most a limited reduction of the density of dislocations, but do not arrest propagation of the same dislocations towards the surface of the epitaxial layer.

<CIT> discloses a method for manufacturing a silicon carbide semiconductor device, which includes: forming a silicon carbide epitaxial film on a silicon carbide substrate; flattening a surface of the epitaxial film by using chemical mechanical polishing such that the surface of the epitaxial film has an arithmetic mean roughness Ra of <NUM> or less; thermally oxidizing the surface of the epitaxial film to form a sacrificial oxide; removing the sacrificial oxide; and cleaning, by using deionized water, a surface of the epitaxial film exposed by the removing of the sacrificial oxide.

<CIT> discloses a polishing liquid and method for producing a polished article. This polishing liquid contains permanganate ions, a weak acid and a soluble salt of the weak acid.

<NPL>, discloses the influences of wafer-related defect and gate oxide fabrication process on characteristics of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of dry oxidation temperature and the applying of N2O and H2 POAs. In addition, the document shows that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is disclosed as an effective technique for the improvement of SiC MOS reliability.

The need is therefore certainly felt to provide a solution that will enable reduction of the disadvantages linked to propagation of the crystallographic defects, in particular TSDs, towards the surface of the epitaxial layer grown on the silicon carbide substrate.

The aim of the present solution is to provide a process for manufacturing a silicon carbide semiconductor device, which will enable the disadvantages highlighted previously to be overcome.

According to the present invention, a manufacturing process is consequently provided, as defined in the appended claims.

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:.

As will be discussed in detail in what follows, an aspect of the present solution, instead of following the approach of known solutions acting on stopping or reducing propagation of defects (in particular, TSDs), envisages intervening on reducing the morphological damage generated on the surface by propagation of the same defects, in particular on reducing the pits (nano-pits) generated on the epitaxial layer surface.

The solution proposed allows to improve subsequent processing operations envisaged by the manufacturing process on the epitaxial layer, for example an oxidation step for the growth of a dielectric layer on the epitaxial layer, preventing effects of electrical-field crowding and ensuring a uniform oxidation.

According to the present solution, an additional CMP step is introduced into the manufacturing process, i.e., a step of chemical-mechanical polishing of the surface of the epitaxial layer formed on the silicon carbide substrate. According to the present invention, said CMP process step uses a polishing compound free of particles and having a pH lower than <NUM>.

This process step, with the associated surface machining (which is a combination of chemical etching and mechanical planarization) enables removal of a thin superficial layer of material (of the order of hundreds of nanometres starting from the surface of the epitaxial layer), consequently making the surface of the epitaxial layer substantially free of pits. The pits due to propagation of the TSDs are substantially removed entirely with removal of the aforesaid superficial layer of material.

With reference to <FIG>, a process for manufacturing a generic silicon carbide semiconductor device, for example a power device (such as a diode or a MOSFET) is now described.

As indicated at step <NUM>, the process first envisages providing a wafer <NUM> of silicon carbide (in particular <NUM>-SiC), comprising a substrate <NUM> (which is illustrated schematically in <FIG>). Next (step <NUM>), an epitaxial growth is carried out, for example with Chemical Vapour Deposition (CVD), for the formation, on the substrate <NUM>, of an epitaxial layer (once again of <NUM>-SiC) <NUM>, having a top surface 23a.

As discussed previously, a defect, in particular a TSD, designated as a whole by <NUM> in <FIG>, during epitaxial growth may propagate starting from the substrate <NUM> towards the overlying epitaxial layer <NUM>, generating, on its top surface 23a, a surface pit <NUM>, which may, for example, have a diameter of some nanometres (for example, less than <NUM>).

According to the present solution, the manufacturing process comprises, following upon the aforesaid step of epitaxial growth (in particular, immediately after), an additional step, designated by <NUM> in <FIG>, of Chemical Mechanical Polishing (CMP) using a polishing compound free of particles and having a pH less than <NUM>, so-called "soft", of the top surface 23a of the epitaxial layer <NUM> formed on the substrate <NUM>.

As indicated again in <FIG>, the CMP process is preceded by a step, designated by <NUM>, of cleaning of the wafer surface, in particular of the top surface 23a of the aforesaid epitaxial layer <NUM>; cleaning is, for example, obtained via a jet of water at a high pressure and drying of the surface via rotation of the sample, or, alternatively via the use of chemical agents, such as HF, NH<NUM>OH, H<NUM>O<NUM>, HCl.

As illustrated schematically in <FIG>, the CMP process, via combination of chemical and mechanical effects, causes removal of a thin surface layer of the epitaxial layer <NUM>, starting from its top surface 23a, so as to remove the surface pits <NUM> originated by propagation of the TSDs <NUM>, consequently making the resulting top surface of the epitaxial layer <NUM>, designated by 23a', substantially planar and free of defects.

In detail, the thickness of the surface layer removed (considered in a direction orthogonal to the aforesaid top surface 23a) may be comprised between <NUM> and <NUM>, for example <NUM>, it being in any case sufficient to remove, as mentioned previously, the surface pits <NUM>, possibly entirely.

As it will be clear, the actual thickness of the removed surface layer will result from a compromise between the desire to remove as little material as possible (so as to optimize times and costs of the manufacturing process) and, at the same time, assure a complete removal of the surface defectiveness. The present Applicant has found that removal of a layer of a thickness of <NUM> may in general be sufficient to make the top surface 23a' resulting from the CMP process uniform. However, it may be convenient to remove a greater thickness, for example of <NUM>, in order to have a higher certainty that the desired results are obtained.

In any case, the CMP process has the further advantage of reducing the surface roughness of the aforesaid resulting top surface 23a' of the epitaxial layer <NUM>.

In this regard, it is known that the typical roughness (generally denoted as parameter Rq) measured on the top surface of an epitaxial layer is variable between <NUM> and <NUM>; moreover, there frequently arises a phenomenon known as "step bunching", i.e., of formation of surface steps, basically due to CVD epitaxial growth on "off-axis" substrates.

The present Applicant has found that the aforesaid CMP process enables a marked reduction of the roughness value of the resulting top surface 23a', with values of the Rq parameter of even less than <NUM> (i.e., values comparable with the noise of the instrumentation used for detecting the same thickness), and moreover enables complete elimination of the step-bunching phenomenon.

Basically, the resulting top surface 23a', after the CMP process, is optimized and prepared for the subsequent chemical and/or mechanical processing steps, which may be envisaged for manufacturing of an electronic device (for example, a power device, such as a diode or a MOSFET).

In this regard, with reference again to <FIG>, the manufacturing process envisages, following the aforesaid CMP process, a step, designated by <NUM>, of cleaning of the resulting top surface 23a' of the epitaxial layer, in particular via C<NUM>H<NUM>O<NUM> and H<NUM>O<NUM>, and subsequently a standard process of oxidation of the same resulting top surface 23a', for formation of an oxide layer on the epitaxial layer <NUM>.

Advantageously, the physical/chemical properties of the formed oxide layer are optimized thanks to the absence of defects and to the low roughness of the starting surface (the aforesaid resulting top surface 23a').

As indicated generically at step <NUM>, the manufacturing process may then proceed with processing operations (known and not described in detail herein) required for formation of the desired power device, for example steps of formation and definition of conductive layers for providing electrodes, formation of passivation layers, etc..

It will thus be noted that the proposed solution differ from pre-existing solutions substantially for the fact of envisaging the additional CMP process step (with standard preliminary cleaning and subsequent dedicated cleaning), therefore not involving a substantial increase in terms of costs or times of the manufacturing process.

The present Applicant has moreover found that it is possible to configure appropriately the CMP process (in particular, in terms of the process parameters and in terms of the used consumables), so that the same CMP process will not cause defects, such as scratches or the like, on the resulting top surface 23a' of the epitaxial layer <NUM>.

In this regard, <FIG> shows a system <NUM> for implementation of the CMP process on the silicon carbide wafer, again designated by <NUM>, which has already undergone the step of epitaxial growth for formation of the epitaxial layer <NUM> on the corresponding substrate <NUM>.

In particular, the system <NUM> comprises a polishing pad <NUM> carried by a rotating support <NUM>, which causes rotation thereof at a certain speed; the wafer <NUM> is set in contact with the polishing pad <NUM> by a supporting head <NUM> (to which it is attached by a fixing layer <NUM>); the supporting head <NUM>, in addition to rotating about its axis of rotation, exerts a force to press the wafer <NUM> on the polishing pad <NUM>.

A polishing compound (so-called "slurry") <NUM> is made to flow over the surface of the polishing pad <NUM> so as to come into contact, thanks to rotation of the same polishing pad <NUM>, with the wafer <NUM> in order to abrade its surface and cause chemical etching thereof.

Moreover, a conditioner pad <NUM> supported in cantilever fashion above the surface of the polishing pad <NUM>, implements cleaning of the polishing pad <NUM> to clean it from residues possibly trapped on its surface and consequently to prevent any scratching of the wafer <NUM>.

The present Applicant has found experimentally that it is possible to achieve better electrical and physical characteristics after the CMP process, using a particle-free polishing compound <NUM> having a pH < <NUM>.

In addition, a pressure P exerted by the supporting head <NUM> on the polishing pad <NUM> comprised between <NUM> and <NUM> psi has been found to be optimal, as likewise a temperature T of the CMP process lower than <NUM>, <NUM> psi being approximately <NUM> kPa.

The present Applicant has moreover found that using one or more of the following further parameters of the CMP process is advantageous: rate of rotation of the polishing pad <NUM> less than <NUM> rpm; rate of rotation of the supporting head <NUM> less than <NUM> rpm; force of thrust of the conditioner pad <NUM> on the polishing pad approximately <NUM> lbf (i.e., around <NUM> kgf, 1kgf being approximately <NUM> N); flow of the polishing compound <NUM> less than <NUM>/min.

The advantages of the proposed solution emerge clearly from the foregoing description.

In any case, it is underlined that the process described enables, by introduction of the CMP process step subsequent to epitaxial growth, removal of the surface defects and therefore optimal preparation of the resulting top surface of the wafer for the subsequent processing operations for manufacturing of the semiconductor device (for example, enabling an increase in the robustness of oxide layers subsequently grown on the epitaxial layer).

In particular, the aforesaid CMP process enables elimination of surface pits due to propagation of the dislocations coming from the substrate generated during the step of epitaxial growth. Furthermore, the CMP process has the further advantage of reducing the surface roughness and in particular the so-called step-bunching phenomenon. As mentioned previously, the surface roughness of the resulting top surface 23a' following upon CMP has low values, in particular with values of the Rq parameter of less than <NUM>, preferably less than <NUM>, and even more preferably less than <NUM>.

Moreover, advantageously, the aforesaid CMP process may be configured so as not to cause scratches or surface defects, as discussed previously and as demonstrated by the experimental tests conducted by the present Applicant.

Consequently, the present solution enables an increase in the electrical yield associated to the manufacturing process, a saving in manufacturing costs, and moreover a saving of area.

Claim 1:
A process for manufacturing a silicon carbide semiconductor device, comprising:
providing a silicon carbide wafer (<NUM>), having a substrate (<NUM>); and
carrying out an epitaxial growth for formation on the substrate (<NUM>) of an epitaxial layer (<NUM>), having a top surface (23a), propagation of dislocations (<NUM>) from the substrate (<NUM>) towards the top surface (23a) occurring during said epitaxial growth with consequent formation of surface damages,
further comprising, subsequent to the step of carrying out an epitaxial growth: removing a surface portion of the epitaxial layer (<NUM>) starting from said top surface (23a), so as to remove the surface damages at said top surface (23a) and define a resulting top surface (23a') substantially free of defects;
wherein said surface damages are pits (<NUM>) due to propagation of the dislocations (<NUM>) starting from said substrate (<NUM>) towards said top surface (23a) during said epitaxial growth;
and wherein the step of removing comprises carrying out a step of Chemical Mechanical Polishing - CMP - of the top surface (23a) of the epitaxial layer (<NUM>);
characterized in that said CMP step is carried out using a polishing compound (<NUM>) free of particles and having a pH lower than <NUM>.