Patent Description:
In computing, a "cache" memory is used to store data for faster access by a processor instead of having to access a main memory. Multiple levels of cache may be used, with a lower level cache (e.g., level <NUM>) being closer to the processor than a higher level cache (such as level <NUM>). The lower level cache is generally more expensive and smaller in size than a higher level cache.

Generally, to improve performance, the size of cache can be increased to allow for faster access to data, but the increase in size comes with an increased cost due to the additional footprint and/or an increased power consumption. Hence, any increase to cache sizes would have to be weighed carefully against the costs.

<CIT> shows a processor which includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level.

<CIT> shows a processor includes multiple processor cores and a load-store queue. Each processor core is configured to execute an instruction block including load and store instructions. The instruction block can be identified by a block identifier, and each of the load and store instructions is identified with a load-store identifier.

The subject-matter provided by the present invention is defined in independent claims, while preferred embodiments of the present invention are defined in dependent claims.

The detailed description is provided with reference to the accompanying figures.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. Further, various aspects of embodiments may be performed using various means, such as integrated semiconductor circuits ("hardware"), computer-readable instructions organized into one or more programs ("software"), or some combination of hardware and software. For the purposes of this disclosure reference to "logic" shall mean either hardware (such as logic circuitry or more generally circuitry or circuit), software, firmware, or some combination thereof.

As mentioned above, any increase to cache sizes would have to be weighed carefully against the costs. Through detailed experiments across a suite of important workloads, it can be observed that a significant fraction of code lines fetched in a processor's on-chip caches are speculative. These speculative code lines belong to unused or rarely used code segments in programs - they are fetched into processor's caches, but their constituent instructions almost never execute. Hence, storing such unneeded code lines at the expense of other frequently used cache lines leads to a performance loss. The problem is exaggerated with the trend towards significantly larger code footprints, due to deep software stacks, interpreted or Just In Time (JIT) code, multiple code instances due to containers and Virtual Machines (VMs) and platform independent code. With such large code footprint workloads, it can be observed that speculative code footprints sometimes range up to three times larger than non-speculative code footprints and occupy nearly <NUM>% to <NUM>% of processor caches such as the Level <NUM> (L1) code cache and the Level <NUM> (L2) cache (which is shared between code and data in some implementations).

To this end, some embodiments provide one or more techniques for de-prioritizing speculative code lines in on-chip caches. An embodiment identifies and deprioritizes such speculative code lines in the L2 cache. By de-prioritizing speculative code lines, some embodiments effectively prioritize storage of non-speculative code lines and data lines in the L2 cache. Through better caching of such L2 frequently accessed lines, a speedup in workload execution can be achieved. This technique can be extended to other on-chip caches storing code lines such as the L1 code cache, shared Last Level Cache (LLC), etc. As discussed herein, a "code line" generally refers to a cache line (e.g., in L2 cache) that stores an instruction or a micro-operation.

Further, it has been observed that in case of workloads with large code footprints, the speculative code footprint can even be much larger than the size of the L2 cache. Hence, even with larger L2 caches, speculative code lines still occupy non-trivial L2 cache capacity. Hence, one or more embodiments can improve performance by allotting L2 cache space of rarely-used speculative code lines to store frequently used code and data lines.

<FIG> illustrate flow diagrams of methods <NUM> and <NUM> to de-prioritize speculative code lines in on-chip caches, according to some embodiments. One or more of the operations of methods <NUM> and <NUM> may be performed by one or more components of <FIG>, such as a processor, processor core, or other logic circuitry discussed herein.

Referring to <FIG> and <FIG>, an operation <NUM> determines whether an instruction has reached pre-allocation or an Instruction Dispatch Queue (IDQ) <NUM>. Once an instruction reaches IDQ at operation <NUM>, operation <NUM> stores an indicia in a Bloom filter <NUM> (e.g., indicating that the instruction is likely to retire). As discussed herein, a "Bloom filter" generally refers to a data/storage structure or storage unit (such as those discussed herein with reference to <FIG>) used for holding state (in an embodiment, each bit in the Bloom filter denotes a block of 128B (Bytes) which reached the IDQ <NUM>). Bloom filters are generally used to store approximate state. Because a Bloom filter stores approximate state, the size of a Bloom filter is relatively smaller - and hence Bloom filters are attractive to use in hardware solutions. In an embodiment, the Bloom filter is <NUM> kB (kilo Bytes), e.g., including four tables of <NUM> kB each, capable of tracking 128B code regions. The use of four tables is part of a Bloom filter design; namely, each table may be accessed with a different hash function. The use of multiple hashes reduces the number of false positives in a Bloom filter. Method <NUM> performs no action at operation <NUM> if an instruction does not reach the IDQ <NUM> (e.g., indicating that the instruction is unlikely to retire).

In an embodiment, the Bloom filter hardware may be contained in one hardware cluster, called the front end in some processor implementations. The instruction(s) or micro-operations ("uops") indicia stored in the Bloom filter <NUM> may include the virtual address of (e.g., all) instruction(s)/uop(s) being allocated in the IDQ <NUM>. In an embodiment, the IDQ <NUM> is a queue where instructions/uops are stored prior to their allocation in the pre-execution stage of the processor pipeline.

Operation <NUM> may be performed by logic provided in the front end <NUM> or execution engine <NUM>, or logic coupled between the front end <NUM> and the execution engine <NUM> to identify a simple metric to predict whether a code line (stored in an L2 cache (such as L2 caches discussed herein, e.g., L2 cache <NUM> of <FIG>) is speculative. For example, code lines whose instructions do not reach pre-allocation stage or the IDQ <NUM> are identified at operation <NUM>, which are likely to be speculative. Generally, the IDQ <NUM> allows the code processing to run ahead.

In an embodiment, the pre-allocation stage occurs after the decode stage (e.g., decode state <NUM> of <FIG>, so the branch and target information are known at this point, or after decoding by the decode circuitry <NUM> in the front end <NUM> of <FIG>), but prior to pre-scheduling/pre-allocation into a scheduler, e.g., prior to reaching the allocate stage <NUM> of <FIG> or rename/allocator circuitry <NUM> and scheduler(s) <NUM> in the execution engine <NUM> of <FIG>. Doing so before allocation is in part because the identified code line/micro-operation is considered likely to retire (e.g., by the retirement unit <NUM> of <FIG>). Hence, the information stored in the Bloom filter <NUM> can be used to predict whether a code line is speculative (e.g., by assuming that code lines represented in the Bloom filter are likely to retire).

Subsequently, at an operation <NUM>, a code miss in code L1 cache triggers operation <NUM> to determine whether a code line corresponding to the code miss in the L1 cache is present in the Bloom filter <NUM>. In an embodiment, operation <NUM> checks the Bloom filter <NUM> for the corresponding virtual address of the code miss. If the Bloom filter does not contain an indicia corresponding to the code miss (or otherwise a corresponding reference is absent from the Bloom filter), the code line is deemed as speculative and such speculative lines are assigned lower priority in the L2 cache at operation <NUM>, e.g., both at the time of allocation and demand access. According to the invention, the code miss request is forwarded to the L2 cache with an indication to de-prioritize that code line in the L2 cache (e.g., with a hit in the L2 cache, the age of the code line is set to <NUM> (or a lowest priority value for earliest eviction from the L2 cache), and with a miss in L2 cache, an entry is inserted into the L2 cache for the code line with age <NUM> (or a lowest priority value for earliest eviction from the L2 cache)). Otherwise if the code line is not seen in the Bloom filter at operation <NUM>, method <NUM> performs no action at operation <NUM>.

Moreover, in an embodiment, at operation <NUM>, a miss in the Bloom filter <NUM> (which means that the 128B block has not been seen in IDQ <NUM>) is a true miss - not a false negative. But, a hit in the Bloom filter <NUM> means that the 128B block may or may not have reached the IDQ <NUM> - false positives are possible. A false positive would, however, not hurt/reduce performance relative to current implementations, and would merely potentially reduce the performance upside of embodiments since code lines that could have been de-prioritized are not being de-prioritized. Further, some embodiments use an 8KB Bloom filter that tracks code bytes at 128B granularity, as this is found to potentially reduce false positives.

Referring to <FIG> and <FIG>, upon a code miss in code L1 cache at operation <NUM>, operation <NUM> pushes the code line fetched from the L2 cache in a queue called Recent Multi-Level Cache (MLC) Return Queue (RMRQ) <NUM>. In an embodiment, RMRQ <NUM> is a <NUM>-entry queue First In First Out (FIFO) queue. Each RMRQ entry contains four fields:.

A new entry is pushed into RMRQ <NUM> at operation <NUM> when a code line is fetched from L2 cache, e.g., into an Instruction Stream Buffer (ISB, which may function in a manner similar to a code cache's MSHR (Miss Status Handling Register)). Moreover, the MSHR holds the request that missed in code L1 cache and is responsible for filling back into the code L1 cache once MSHR receives data from the L2 cache. For the oldest entry popped/evicted from RMRQ <NUM> at an operation <NUM>, there are the following possibilities:.

When an instruction is pushed into the IDQ <NUM>, the IDQWrite field is set to TRUE for the RMRQ entry whose VirtAddr matches the instruction's program counter.

Furthermore, with respect to the de-prioritization signal (sent at operation <NUM>), arbitration logic of a L2 cache controller's determines which request will arbitrate the L2 cache in a particular cycle. The L2 cache controller (not shown but may be coupled to and/or located on the same integrated circuit device as the L2 cache) may be modified to assign the highest priority to L2 de-prioritization requests received from the RMRQ <NUM>. Hence, in cycles where a valid L2 de-prioritization request is received, L2 controller arbitrates the L2 cache, and for the code line whose address matches the requested address, the priority value is set to <NUM> (lowest priority value for earliest eviction from the L2 cache).

Moreover, the RMRQ mechanism requires minimal hardware (e.g., <NUM> bytes) but its implementation may require communication between two hardware clusters - the front end <NUM> and the L2 cache <NUM>.

Hence, method <NUM> tracks code lines (in a queue of about <NUM> Bytes) returned from the L2 cache 476and whether they reach the IDQ <NUM>. For code lines that do not reach the IDQ, a (e.g., data-less) request is issued to the L2 cache to de-prioritize the identified code line in the L2 cache. The data-less request may include the code line address with another flag (e.g., <NUM> bits) to cause the age of that code line to be set to <NUM> (or lowest priority value for earliest eviction from the L2 cache).

Referring to <FIG>, one or more embodiments are able to:.

<FIG> illustrates a sample average code footprint observed across stages in a processor pipeline for large code footprint workloads, according to an embodiment. A code line is considered non-speculative if the instructions of the code line are executed by the processor. By reference to <FIG>, it can be observed that most instructions that are eventually executed by the processor reach the pre-execution stage. This can be observed by tracking unique code footprints observed at different stages in the pipeline. As shown in <FIG>, the unique code footprint observed at the pre-execution stage (i.e., IDQ write) is almost the same as retired/executed stage.

Referring to <FIG>, this information augments one or more embodiments in the following ways: (<NUM>) instructions may reach the pre-execution stage approximately <NUM>+ cycles earlier than the retired stage; hence, tracking pre-execution stage results in an early indication about whether a line is speculative or not; and (<NUM>) the hardware cluster for the pre-execution stage (IDQ write) is located next to the front end, where the decision about deprioritizing code lines is made; hence, resulting in tracking pre-execution stage results in a smaller and less complicated communication channel.

<FIG> illustrates the impact of proposed techniques on a suite of large code footprint workloads, according to an embodiment. The baseline system mimics a sample server processor. Over a suite of <NUM> workloads, the proposed Bloom filter <NUM> and RMRQ <NUM> approaches improve a workload's performance (geometric mean) by about <NUM> percent and <NUM> percent, respectively. Also, for the top <NUM> workloads (in terms of code footprint), the proposed Bloom filter and RMRQ techniques improve workload performance by about <NUM>% and <NUM>%, respectively.

Accordingly, at least one embodiment deprioritizes speculative code lines in the L2 cache by: (<NUM>) identifying a simple metric to predict if a code line is speculative or not (for example, code lines whose instructions do not reach the pre-allocation stage/IDQ are identified, which are very likely to be speculative); and (<NUM>) using the above-mentioned metric with one of two techniques to de-prioritize speculative code lines in the L2 cache. Both techniques under (<NUM>) may make minimal changes to existing hardware. Also, the above heuristic (<NUM>) enables low-hardware-cost solutions to optimize for speculative lines in at least one embodiment.

Even with limited hardware requirements, these features can enable performance gains of about <NUM>% for a suite of large code footprint workloads (such games, databases, and web workloads). For the top <NUM> workloads (in terms of code footprint), the performance gains can be between approximately <NUM>% and <NUM>%. Since the proposed feature only selectively targets speculative code lines that are not critical for performance, it is not envisioned to degrade performance in other conditions.

Additionally, some embodiments may be applied in computing systems that include one or more processors (e.g., where the one or more processors may include one or more processor cores), such as those discussed with reference to <FIG> et seq. , including for example a desktop computer, a workstation, a computer server, a server blade, or a mobile computing device. The mobile computing device may include a smartphone, tablet, UMPC (Ultra-Mobile Personal Computer), laptop computer, Ultrabook™ computing device, wearable devices (such as a smart watch, smart ring, smart bracelet, or smart glasses), etc..

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU (Central Processing Unit) including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point" status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a writemask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

<FIG> illustrates a block diagram of an SOC package in accordance with an embodiment. As illustrated in <FIG>, SOC <NUM> includes one or more Central Processing Unit (CPU) cores <NUM>, one or more Graphics Processor Unit (GPU) cores <NUM>, an Input/Output (I/O) interface <NUM>, and a memory controller <NUM>. Various components of the SOC package <NUM> may be coupled to an interconnect or bus such as discussed herein with reference to the other figures. Also, the SOC package <NUM> may include more or less components, such as those discussed herein with reference to the other figures. Further, each component of the SOC package <NUM> may include one or more other components, e.g., as discussed with reference to the other figures herein. In one embodiment, SOC package <NUM> (and its components) is provided on one or more Integrated Circuit (IC) die, e.g., which are packaged into a single semiconductor device.

As illustrated in <FIG>, SOC package <NUM> is coupled to a memory <NUM> via the memory controller <NUM>. In an embodiment, the memory <NUM> (or a portion of it) can be integrated on the SOC package <NUM>.

The I/O interface <NUM> may be coupled to one or more I/O devices <NUM>, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s) <NUM> may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch screen, a speaker, or the like.

<FIG> is a block diagram of a processing system <NUM>, according to an embodiment. In various embodiments the system <NUM> includes one or more processors <NUM> and one or more graphics processors <NUM>, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors <NUM> or processor cores <NUM>. In on embodiment, the system <NUM> is a processing platform incorporated within a system-on-a-chip (SoC or SOC) integrated circuit for use in mobile, handheld, or embedded devices.

An embodiment of system <NUM> can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system <NUM> is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system <NUM> can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system <NUM> is a television or set top box device having one or more processors <NUM> and a graphical interface generated by one or more graphics processors <NUM>.

In some embodiments, the processor <NUM> also uses an external cache (e.g., a Level <NUM> (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores <NUM> using known cache coherency techniques.

In some embodiments, processor <NUM> is coupled to a processor bus <NUM> to transmit communication signals such as address, data, or control signals between processor <NUM> and other components in system <NUM>. In one embodiment the system <NUM> uses an exemplary 'hub' system architecture, including a memory controller hub <NUM> and an Input Output (I/O) controller hub <NUM>. A memory controller hub <NUM> facilitates communication between a memory device and other components of system <NUM>, while an I/O Controller Hub (ICH) <NUM> provides connections to I/O devices via a local I/O bus. In one embodiment, the logic of the memory controller hub <NUM> is integrated within the processor.

Memory device <NUM> can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device <NUM> can operate as system memory for the system <NUM>, to store data <NUM> and instructions <NUM> for use when the one or more processors <NUM> executes an application or process. Memory controller hub <NUM> also couples with an optional external graphics processor <NUM>, which may communicate with the one or more graphics processors <NUM> in processors <NUM> to perform graphics and media operations.

In some embodiments, ICH <NUM> enables peripherals to connect to memory device <NUM> and processor <NUM> via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller <NUM>, a firmware interface <NUM>, a wireless transceiver <NUM> (e.g., Wi-Fi, Bluetooth), a data storage device <NUM> (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller <NUM> for coupling legacy (e.g., Personal System <NUM> (PS/<NUM>)) devices to the system. One or more Universal Serial Bus (USB) controllers <NUM> connect input devices, such as keyboard and mouse <NUM> combinations. A network controller <NUM> may also couple to ICH <NUM>. In some embodiments, a high-performance network controller (not shown) couples to processor bus <NUM>. It will be appreciated that the system <NUM> shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, the I/O controller hub <NUM> may be integrated within the one or more processor <NUM>, or the memory controller hub <NUM> and I/O controller hub <NUM> may be integrated into a discreet external graphics processor, such as the external graphics processor <NUM>.

<FIG> is a block diagram of an embodiment of a processor <NUM> having one or more processor cores 702A to 702N, an integrated memory controller <NUM>, and an integrated graphics processor <NUM>. Those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor <NUM> can include additional cores up to and including additional core 702N represented by the dashed lined boxes. Each of processor cores 702A to 702N includes one or more internal cache units 704A to 704N. In some embodiments each processor core also has access to one or more shared cached units <NUM>.

The internal cache units 704A to 704N and shared cache units <NUM> represent a cache memory hierarchy within the processor <NUM>. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level <NUM> (L2), Level <NUM> (L3), Level <NUM> (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units <NUM> and 704A to 704N.

In some embodiments, processor <NUM> may also include a set of one or more bus controller units <NUM> and a system agent core <NUM>. The one or more bus controller units <NUM> manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). System agent core <NUM> provides management functionality for the various processor components. In some embodiments, system agent core <NUM> includes one or more integrated memory controllers <NUM> to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 702A to 702N include support for simultaneous multi-threading. In such embodiment, the system agent core <NUM> includes components for coordinating and operating cores 702A to 702N during multi-threaded processing. System agent core <NUM> may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 702A to 702N and graphics processor <NUM>.

In some embodiments, processor <NUM> additionally includes graphics processor <NUM> to execute graphics processing operations. In some embodiments, the graphics processor <NUM> couples with the set of shared cache units <NUM>, and the system agent core <NUM>, including the one or more integrated memory controllers <NUM>. In some embodiments, a display controller <NUM> is coupled with the graphics processor <NUM> to drive graphics processor output to one or more coupled displays. In some embodiments, display controller <NUM> may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor <NUM> or system agent core <NUM>.

In some embodiments, a ring based interconnect unit <NUM> is used to couple the internal components of the processor <NUM>. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor <NUM> couples with the ring interconnect <NUM> via an I/O link <NUM>.

The exemplary I/O link <NUM> represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module <NUM>, such as an eDRAM (or embedded DRAM) module. In some embodiments, each of the processor cores <NUM> to 702N and graphics processor <NUM> use embedded memory modules <NUM> as a shared Last Level Cache.

In some embodiments, processor cores 702A to 702N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 702A to 702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 702A to 702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores 702A to 702N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor <NUM> can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

<FIG> is a block diagram of a graphics processor <NUM>, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor <NUM> includes a memory interface <NUM> to access memory. Memory interface <NUM> can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor <NUM> also includes a display controller <NUM> to drive display output data to a display device <NUM>. Display controller <NUM> includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In some embodiments, graphics processor <NUM> includes a video codec engine <NUM> to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-<NUM>, Advanced Video Coding (AVC) formats such as H. <NUM>/MPEG-<NUM> AVC, as well as the <NPL>, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor <NUM> includes a block image transfer (BLIT) engine <NUM> to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 3D graphics operations are performed using one or more components of graphics processing engine (GPE) <NUM>. In some embodiments, graphics processing engine <NUM> is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE <NUM> includes a 3D pipeline <NUM> for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline <NUM> includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system <NUM>. While 3D pipeline <NUM> can be used to perform media operations, an embodiment of GPE <NUM> also includes a media pipeline <NUM> that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline <NUM> includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine <NUM>. In some embodiments, media pipeline <NUM> additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system <NUM>. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system <NUM>.

In some embodiments, 3D/Media subsystem <NUM> includes logic for executing threads spawned by 3D pipeline <NUM> and media pipeline <NUM>. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem <NUM>, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem <NUM> includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.

In various embodiments, one or more operations discussed with reference to <FIG> et seq. may be performed by one or more components (interchangeably referred to herein as "logic") discussed with reference to any of the figures.

In various embodiments, the operations discussed herein, e.g., with reference to <FIG> et seq. , may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including one or more tangible (e.g., non-transitory) machine-readable or computer-readable media having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. The machine-readable medium may include a storage device such as those discussed with respect to the figures.

Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals provided in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, and/or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase "in one embodiment" in various places in the specification may or may not be all referring to the same embodiment.

Also, in the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

Claim 1:
An apparatus comprising:
logic circuitry to determine whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache (<NUM>); and
the logic circuitry to cause de-prioritization of a speculative code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure,
wherein the code miss request is directed at the shared cache.
wherein the storage structure comprises a Bloom filter (<NUM>);
wherein the logic circuitry is to forward the code miss request to the shared cache with an indication to de-prioritize the code line in the shared cache in response to the absence of the reference in the storage structure,
wherein the shared cache is a Level <NUM> ;L2; cache (<NUM>), or wherein the code miss request is directed at the shared cache after a miss in a code Level <NUM> ;L1; cache; and
wherein the storage structure is to store an indicia of one or more instructions or one or more micro-operations that have been allocated in an Instruction Dispatch Queue ;IDQ; (<NUM>), or wherein the IDQ (<NUM>) is to store an instruction or micro-operation prior to allocation in a pre-execution stage of a processor pipeline (<NUM>).