Patent Description:
Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR Flash memory and NAND Flash memory. Various operations can be performed by Flash memory, such as read, program (write), and erase, to change the threshold voltage of each memory cell to a desired level. For NAND Flash memory, an erase operation can be performed at the block level, and a program operation or a read operation can be performed at the page level. For example, <CIT> discloses a wave pipeline including a fist stage to receive a data and clock signal, a plurality of second stages to process data received from the first stage in response to a clock cycle and a third stage to process data received from the second stage.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

Aspects of the present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosure can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure. The scope of the invention is set out in the appended set of claims.

Some memory devices, such as NAND Flash memory devices, can perform read operations at the page level, i.e., reading all the memory cells in the same selected page at the same time. Page buffers are used by NAND Flash memory devices for buffering the read-out data between the memory cell array and the data bus in read operations. A page buffer of a certain memory plane is divided into multiple portions, such as four quarters, each of which has its own clock path and data patch that will finally merge together to output from the NAND Flash memory device.

Since NAND Flash memory devices work at very high frequencies, to track the read-out data, the clock signal that sent the column address to the memory plane will return along with the read-out data as a clock return signal according to a clock signal return scheme (a. , wave pipeline structure). As the page buffer quarters need to switch when the data reading from the current select quarter is finished, the return clock signals also need to switch from quarter to quarter. However, due to the process and operating condition variations (e.g., process, voltage, temperature, etc.) among different quarters, the duration of transmitting each clock return signal also varies. Thus, it is challenging to merge the clock return signals from the four page buffer quarters.

According to some known clock signal return schemes, when merging the clock return signals of different quarters, in order not to gate other quarters' clock return signals, the level of each clock return signal has to return to low at the end. That is, each clock return signal includes short pulses according to those known schemes. The issue of using the short pulse for the clock return signal is that the short pulse needs to pass along a long routing line of the clock path, which becomes difficult to control considering the process and operating condition variations among different quarters.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which the short pulse is avoided for clock return signals while still not gating other clock return signals from other portions of the page buffer during the switch between different portions of the page buffer. Depending on the type of logic gate used in the clock path for merging different clock return signals, for example, an OR gate or a NAND gate, the clock return signal returned from the current select portion can be ensured to finish at a particular level (e.g., low for OR gate and high for NAND gate) that will not gate another clock return signal next to it. As a result, a frequency divider can be used at the beginning of the clock path to increase the period of the clock return signal to avoid using short pulses for clock return signals. In the embodiments of the invention, to ensure the desired end level of the clock return signal from the current select portion of the page buffer, the parity of the number of cycles in the clock return signal is determined and used to set the start level of the clock return signal. In the embodiments of the invention, since the clock cycles correspond to the read-out data cycles to be transferred in the current select portion, the parity of the number of clock cycles can be determined based on the address of the read-out data from the current select portion of the page buffer as indicated in the read instruction. As a result, the clock return signals can be more easily controlled even over a long routing and with the process and operating condition variations among different portions of the page buffer, thereby achieving a seamless switch between different portions. Moreover, the tracking between data and clock signals over data path and clock path become more easily as well by using the clock signal return scheme disclosed herein, compared with the known clock signal return schemes.

<FIG> illustrates a block diagram of an exemplary system <NUM> having a memory device, according to some aspects of the present disclosure. System <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in <FIG>, system <NUM> can include a host <NUM> and a memory system <NUM> having one or more memory devices <NUM> and a memory controller <NUM>. Host <NUM> can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host <NUM> can be coupled to memory controller <NUM> and configured to send or receive data to or from memory devices <NUM> through memory controller <NUM>. For example, host <NUM> may send the program data in a program operation or receive the read data in a read operation.

Memory device <NUM> can be any memory device disclosed in the present disclosure, such as a NAND Flash memory device, which includes a page buffer having multiple portions, for example, four quarters. Consistent with the scope of the present disclosure, depending on the type of logic gate used in the clock path for merging different clock return signals, for example, an OR gate or a NAND gate, the clock return signal returned from the current select portion can be ensured to finish at a particular level (e.g., low for OR gate and high for NAND gate) that will not gate another clock return signal next to it. As a result, a frequency divider can be used at the beginning of the clock path to increase the period of the clock return signal to avoid using short pulses for clock return signals.

Memory controller <NUM> is coupled to memory device <NUM> and host <NUM> and is configured to control memory device <NUM>, according to some implementations. Memory controller <NUM> can manage the data stored in memory device <NUM> and communicate with host <NUM>. In some implementations, memory controller <NUM> is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller <NUM> is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller <NUM> can be configured to control operations of memory device <NUM>, such as read, erase, and program operations, by providing instructions, such as read instructions, to memory device <NUM>. For example, memory controller <NUM> may be configured to provide a read instruction to the peripheral circuit of memory device <NUM> to control the read operation. Memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in memory device <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device <NUM>. Any other suitable functions may be performed by memory controller <NUM> as well, for example, formatting memory device <NUM>.

Memory controller <NUM> can communicate with an external device (e.g., host <NUM>) according to a particular communication protocol. For example, memory controller <NUM> may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc..

Memory controller <NUM> and one or more memory devices <NUM> can be integrated into various types of storage devices, for example, being included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single memory device <NUM> may be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., host <NUM> in <FIG>). In another example as shown in <FIG>, memory controller <NUM> and multiple memory devices <NUM> may be integrated into an SSD <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., host <NUM> in <FIG>). In some implementations, the storage capacity and/or the operation speed of SSD <NUM> is greater than those of memory card <NUM>.

<FIG> illustrates a schematic circuit diagram of an exemplary memory device <NUM> including peripheral circuits, according to some aspects of the present disclosure. Memory device <NUM> can be an example of memory device <NUM> in <FIG>. Memory device <NUM> can include a memory cell array <NUM> and peripheral circuits <NUM> coupled to memory cell array <NUM>. Memory cell array <NUM> can be a NAND Flash memory cell array in which memory cells <NUM> are provided in the form of an array of NAND memory strings <NUM> each extending vertically above a substrate (not shown). In some implementations, each NAND memory string <NUM> includes a plurality of memory cells <NUM> coupled in series and stacked vertically. Each memory cell <NUM> can hold a continuous, analog value, such as an electrical voltage or charge, which depends on the number of electrons trapped within a region of memory cell <NUM>. Each memory cell <NUM> can be either a floating gate type of memory cell including a floating-gate transistor or a charge trap type of memory cell including a charge-trap transistor.

In some implementations, each memory cell <NUM> is a single-level cell (SLC) that has two possible memory states and thus, can store one bit of data. For example, the first memory state "<NUM>" can correspond to a first range of voltages, and the second memory state "<NUM>" can correspond to a second range of voltages. In some implementations, each memory cell <NUM> is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC can store two bits per cell, three bits per cell (also known as triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

As shown in <FIG>, each NAND memory string <NUM> can include a source select gate (SSG) transistor <NUM> at its source end and a drain select gate (DSG) transistor <NUM> at its drain end. SSG transistor <NUM> and DSG transistor <NUM> can be configured to activate selected NAND memory strings <NUM> (columns of the array) during read and program operations. In some implementations, the sources of NAND memory strings <NUM> in the same block <NUM> are coupled through a same source line (SL) <NUM>, e.g., a common SL. In other words, all NAND memory strings <NUM> in the same block <NUM> have an array common source (ACS), according to some implementations. The drain of DSG transistor <NUM> of each NAND memory string <NUM> is coupled to a respective bit line <NUM> from which data can be read or written via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string <NUM> is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of DSG transistor <NUM>) or a deselect voltage (e.g., <NUM> V) to the gate of respective DSG transistor <NUM> through one or more DSG lines <NUM> and/or by applying a select voltage (e.g., above the threshold voltage of SSG transistor <NUM>) or a deselect voltage (e.g., <NUM> V) to the gate of respective SSG transistor <NUM> through one or more SSG lines <NUM>.

As shown in <FIG>, NAND memory strings <NUM> can be organized into multiple blocks <NUM>, each of which can have a common source line <NUM>, e.g., coupled to the ACS. In some implementations, each block <NUM> is the basic data unit for erase operations, i.e., all memory cells <NUM> on the same block <NUM> are erased at the same time. To erase memory cells <NUM> in a selected block <NUM>, source lines <NUM> coupled to selected block <NUM> as well as unselected blocks <NUM> in the same plane as selected block <NUM> can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., <NUM> V or more). Memory cells <NUM> of adjacent NAND memory strings <NUM> can be coupled through word lines <NUM> that select which row of memory cells <NUM> is affected by the read and program operations. In some implementations, each word line <NUM> is coupled to a page <NUM> of memory cells <NUM>, which is the basic data unit for the program and read operations. The size of one page <NUM> in bits can relate to the number of NAND memory strings <NUM> coupled by word line <NUM> in one block <NUM>. Each word line <NUM> can include a plurality of control gates (gate electrodes) at each memory cell <NUM> in respective page <NUM> and a gate line coupling the control gates.

<FIG> illustrates a side view of a cross-section of an exemplary memory cell array <NUM> including NAND memory strings <NUM>, according to some aspects of the present disclosure. As shown in <FIG>, NAND memory string <NUM> can extend vertically through a memory stack <NUM> above a substrate <NUM>. Substrate <NUM> can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials.

Memory stack <NUM> can include interleaved gate conductive layers <NUM> and gate-to-gate dielectric layers <NUM>. The number of the pairs of gate conductive layers <NUM> and gate-to-gate dielectric layers <NUM> in memory stack <NUM> can determine the number of memory cells <NUM> in memory cell array <NUM>. Gate conductive layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each gate conductive layer <NUM> includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer <NUM> includes a doped polysilicon layer. Each gate conductive layer <NUM> can include control gates surrounding memory cells <NUM>, the gates of DSG transistors <NUM>, or the gates of SSG transistors <NUM>, and can extend laterally as DSG line <NUM> at the top of memory stack <NUM>, SSG line <NUM> at the bottom of memory stack <NUM>, or word line <NUM> between DSG line <NUM> and SSG line <NUM>.

As shown in <FIG>, NAND memory string <NUM> includes a channel structure <NUM> extending vertically through memory stack <NUM>. In some implementations, channel structure <NUM> includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel <NUM>) and dielectric material(s) (e.g., as a memory film <NUM>). In some implementations, semiconductor channel <NUM> includes silicon, such as polysilicon. In some implementations, memory film <NUM> is a composite dielectric layer including a tunneling layer <NUM>, a storage layer <NUM> (also known as a "charge trap/storage layer"), and a blocking layer <NUM>. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). Semiconductor channel <NUM>, tunneling layer <NUM>, storage layer <NUM>, blocking layer <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Tunneling layer <NUM> can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer <NUM> can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer <NUM> can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film <NUM> may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

As shown in <FIG>, a well <NUM> (e.g., a P-well and/or an N-well) is formed in substrate <NUM>, and the source end of NAND memory string <NUM> is in contact with well <NUM>, according to some implementations. For example, source line <NUM> may be coupled to well <NUM> to apply an erase voltage to well <NUM>, i.e., the source of NAND memory string <NUM>, during erase operations. In some implementations, NAND memory string <NUM> further includes a channel plug <NUM> at the drain end of NAND memory string <NUM>.

Referring back to <FIG>, peripheral circuits <NUM> can be coupled to memory cell array <NUM> through bit lines <NUM>, word lines <NUM>, source lines <NUM>, SSG lines <NUM>, and DSG lines <NUM>. Peripheral circuits <NUM> can include any suitable analog, digital, and mixed-signal circuits for facilitating the operations of memory cell array <NUM> by applying and sensing voltage signals and/or current signals to and from each target memory cell <NUM> through bit lines <NUM>, word lines <NUM>, source lines <NUM>, SSG lines <NUM>, and DSG lines <NUM>. Peripheral circuits <NUM> can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technologies. For example, <FIG> illustrates some exemplary peripheral circuits including a page buffer/sense amplifier <NUM>, a column decoder/bit line driver <NUM>, a row decoder/word line driver <NUM>, a voltage generator <NUM>, control logic <NUM>, registers <NUM>, an interface <NUM>, and a data bus <NUM>. It is understood that in some examples, additional peripheral circuits not shown in <FIG> may be included as well.

Page buffer/sense amplifier <NUM> can be configured to read and program (write) data from and to memory cell array <NUM> according to the control signals from control logic <NUM>. In one example, page buffer/sense amplifier <NUM> may store one page of program data (write data) to be programmed into one page <NUM> of memory cell array <NUM>. In another example, page buffer/sense amplifier <NUM> may perform program verify operations to ensure that the data has been properly programmed into memory cells <NUM> coupled to selected word lines <NUM>. In still another example, page buffer/sense amplifier <NUM> may also sense the low power signals from bit line <NUM> that represents a data bit stored in memory cell <NUM> and amplifies the small voltage swing to recognizable logic levels in a read operation. As described below in detail, page buffer/sense amplifier <NUM> can include a plurality of physically separated portions (e.g., four quarters) that can be sequentially accessed through its own clock path and data path in read operations.

Column decoder/bit line driver <NUM> can be configured to be controlled by control logic <NUM> according to the control signals from control logic <NUM> and select one or more NAND memory strings <NUM> by applying bit line voltages generated from voltage generator <NUM>. As described below in detail, in read operations, the control signals can include read commands that include addresses (e.g.. , column addresses) each identifying read-out data starting from one of the portions of page buffer/sense amplifier <NUM>.

Row decoder/word line driver <NUM> can be configured to be controlled by control logic <NUM> according to the control signals from control logic <NUM> and select/deselect blocks <NUM> of memory cell array <NUM> and select/deselect word lines <NUM> of block <NUM>. Row decoder/word line driver <NUM> can be further configured to drive word lines <NUM> using word line voltages generated from voltage generator <NUM>. In some implementations, row decoder/word line driver <NUM> can also select/deselect and drive SSG lines <NUM> and DSG lines <NUM> as well. Voltage generator <NUM> can be configured to be controlled by control logic <NUM> according to the control signals from control logic <NUM> and generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array <NUM>.

Control logic <NUM> can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit by generating and sending various control signals, such as read commands for read operations. Control logic <NUM> can also send clock signals at desired frequencies, periods, and duty cycles to other peripheral circuits <NUM> to orchestrate the operations of each peripheral circuit <NUM>, for example, for synchronization. Registers <NUM> can be coupled to control logic <NUM> and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit <NUM>.

Interface <NUM> can be coupled to control logic <NUM> and act as an instruction fetcher/buffer as well as an instruction decoder to decode instructions received from a memory controller (e.g., <NUM> in <FIG>) and relay the decoded instructions to control logic <NUM>. Interface <NUM> can also buffer and relay status information received from control logic <NUM> to the memory controller (e.g., <NUM> in <FIG>). Interface <NUM> can be coupled to page buffer/sense amplifier <NUM> via data bus <NUM> and further act as a data input/output (I/O) interface and a data buffer to buffer and relay the data to and from memory cell array <NUM>.

As described below in detail, peripheral circuits <NUM> can further include a clock path <NUM> coupled to and from each portion of page buffer/sense amplifier <NUM> and configured to transfer and merge multiple clock return signals from multiple portions of page buffer/sense amplifier <NUM> in a read operation according to the clock signal return schemes disclosed herein. Clock path <NUM> can be coupled to interface <NUM> as well to transfer the merged clock return signals to interface <NUM> in order to synchronize the output of the read-out data from data bus <NUM> in read operations. In some implementations, the merged clock return signal on clock path <NUM> is aligned with the read-out data on data bus <NUM> in a read operation.

<FIG> illustrates a block diagram of exemplary memory device <NUM> including multiple memory planes, according to some aspects of the present disclosure. In some implementations, memory device <NUM> includes a plurality of memory planes <NUM> (e.g., four memory planes in <FIG>). Memory plane <NUM> can be mutually independent in performing a read operation, a program operation, or an erase operation. For example, each memory plane <NUM> may be configured to perform a read operation independently in response to receiving a read control signal from control logic <NUM>. In some implementations, each memory plane <NUM> covers local buffering for the read and program data and can process operations in parallel, thereby increasing the operation speed. To enable its independent operation, each memory plane <NUM> can include a set of blocks <NUM> of memory cell array <NUM> and a set of peripheral circuits, such as page buffer/sense amplifier <NUM>, column decoder/bit line driver <NUM>, and row decoder/word line driver <NUM>.

<FIG> illustrates an exemplary layout of memory plane <NUM> including page buffer/sense amplifier <NUM> having multiple portions and clock path <NUM> coupled to the multiple portions of page buffer/sense amplifier <NUM>, according to some aspects of the present disclosure. Memory plane <NUM> can include page buffer/sense amplifier <NUM> divided into a plurality of portions. As shown in <FIG>, page buffer/sense amplifier <NUM> includes four physically separated quarters 504a, 504b, 504c, and 504d, according to some implementations. For ease of descriptions, the multiple portions of a page buffer may be described herein as four quarters. It is understood that the number of portions is not limited to four and may be any integer greater than <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), for example, two halves. Page buffer/sense amplifier <NUM> can include a plurality of storage units (e.g., latches, caches, or registers) for temporarily storing (buffering) one or more pages of data to be read from or written to the memory cells in memory plane <NUM>. In some implementations, each quarter 504a, 504b, 504c, or 504d has the same size, i.e., one quarter of page buffer/sense amplifier <NUM>. For example, page buffer/sense amplifier <NUM> may store <NUM> bytes of data, and each quarter 504a, 504b, 504c, or 504d may store <NUM> bytes of data.

In some implementations, clock path <NUM> is coupled to each quarter 504a, 504b, 504c, or 504d of page buffer/sense amplifier <NUM>. As shown in <FIG>, clock path <NUM> can diverge at each junction <NUM>, 704a, or 704b to form branches thereof. For example, clock path <NUM> may diverge into two plane half branches at junction <NUM>, and each plane half branch of clock path may respectively diverge into two quarter branches at a respective junction 704a or 704b, such that each of four quarter branches of clock path <NUM> may be coupled to a respective quarter 504a, 504b, 504c, or 504d of page buffer/sense amplifier <NUM>. Clock path <NUM> can be bidirectional to transfer clock signals from, for example, control logic <NUM>, to each quarter 504a, 504b, 504c, or 504d, and transfer clock return signals from each quarter 504a, 504b, 504c, or 504d to, for example, interface <NUM>. In some implementations, clock path <NUM> is configured to split a clock signal into four clock signals and transfer the four clock signals to four quarters 504a, 504b, 504c, and 504d of page buffer/sense amplifier <NUM>, respectively, via the quarter branches thereof. As described below in detail, clock path <NUM> is also configured to transfer four clock return signals from four quarters 504a, 504b, 504c, and 504d of page buffer/sense amplifier <NUM>, respectively, via the quarter branches thereof, and merge the four clock return signals into a merged clock return signal.

<FIG> illustrates a circuit diagram of a clock path <NUM> coupled to multiple portions of a page buffer <NUM> for merging clock return signals. <FIG> illustrates a timing diagram of a clock signal return scheme implemented by clock path <NUM> in <FIG>. Each of quarters <NUM>, <NUM>, <NUM>, and <NUM> of page buffer <NUM> is sequentially selected following this order: <NUM>, <NUM>, <NUM>, and <NUM> in a read operation. Thus, taking quarters <NUM> and <NUM> as an example, as shown in <FIG>, the clock signal (clk_dp) transferred on clock path <NUM> to page buffer <NUM> is split into two sequential clock signals (clk_dp_q0 and clk_dp_q1). That is, each of quarters <NUM> and <NUM> sequentially receives a respective clock signal (clk_dp_q0 or clk_dp_q1). As shown in <FIG>, in each quarter <NUM>,<NUM>, <NUM>, or <NUM>, a respective clock signal <NUM> passes through a respective delay circuit (DLY) <NUM> to become a respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk_rtn_q2, or clk _rtn_q3) in a respective branch of clock path <NUM>. As shown in <FIG>, for example, when quarter <NUM> is selected, delay circuit <NUM> for quarter <NUM> acts as a frequency multiplier to reduce the period of the first clock return signal (clk _rtn_q0) from that of the first clock signal (clk_dp_q0). Similarly, when quarter <NUM> is selected, delay circuit <NUM> for quarter <NUM> acts as a frequency multiplier to reduce the period of the second clock return signal (clk_rtn_q1) from that of the second clock signal (clk_dp_q1). As a result, clock return signals are transferred on clock path <NUM> in the forms of short pulses to ensure that the end level of each clock return signal when switching is low (e.g., <NUM> V, Vss) to avoid gating each other when merging at quarter branches of clock path <NUM> by OR gates <NUM>. It is understood that although for ease of illustration, only delay circuit <NUM> is shown in page buffer <NUM> of <FIG>, any other suitable components, for example, as described above, may be included in each quarter of page buffer <NUM>.

As shown in <FIG>, in each quarter branch of clock path <NUM>, every two clock return signals from two quarters next to each other (e.g., quarters <NUM> and <NUM>, or quarters <NUM> and <NUM>) are merged by a respective OR gate <NUM>. Each of the two merged clock return signals on a respective quarter branch of clock path <NUM> also passes a respective frequency divider <NUM> that increases its period to generate a respective merged clock return signal (clk_rtn_q01 or clk_rtn_q23). As shown in <FIG>, OR gate <NUM> in conjunction with frequency divider <NUM> toggle the level of the merged clock return signal (clk_rtn_q01) at each rising edge of either clock return signal (clk_rtn_q0 or clk_rtn_q1). In other words, the short pulse of each clock return signal is enlarged after merging at each quarter branch.

As shown in <FIG>, since the two merged clock return signals (clk_rtn_q01 or clk_rtn_q23) need to merge again in the plane half branch, clock path <NUM> also includes an edge detector/pulse generator <NUM> on each quarter branch that respectively generates a short pulse at each rising edge or falling edge of a respective merged clock return signal (clk_rtn_q01 or clk_rtn_q23). The two outputted signals are merged again by an OR gate <NUM> to generate a merged clock return signal (clk_rtn_pul). As shown in <FIG>, short pulses are regenerated in the merged clock return signal (clk_rtn_pul) in response to the rising edges or falling edges of the merged clock return signal (clk_trn_q01). Referring back to <FIG>, the merged clock return signal (clk_rtn_pul) needs to pass through a frequency divider <NUM> again on clock path <NUM> to increase the period, i.e., enlarging the short pulses, of the merged clock return signal (clk_rtn).

The clock signal return scheme described above with respect to <FIG> and <FIG> requires short pulses in the various clock return signals (e.g., clk _rtn_q0, clk_rtn_q1, clk_rtn_q2, clk_rtn_q3, and clk_rtn_pul) to avoid gating at OR gates <NUM> and <NUM>. Considering the process and operating condition variations (e.g., process, voltage, temperature, etc.) among different quarters, it becomes difficult to well control the short pulses that pass along a long routing line of clock path <NUM>. Moreover, the frequent change of the signal periods and frequencies over clock path <NUM>, for example, by frequency dividers, frequency multipliers, and/or edge detector/pulse generators, is also undesirable as it can increase the risk of mismatch between clock return signals and the corresponding data signals.

To overcome one or more of the above problems of the known clock signal return scheme, an improved clock signal return scheme according to the invention is disclosed herein with respect to <FIG> and <FIG> below. Depending on the type of logic gate used in the clock path for merging different clock return signals, for example, an OR gate or a NAND gate, the clock return signal returned from the current select portion can be ensured to finish at a particular level (e.g., low for OR gate and high for NAND gate) that will not gate another clock return signal next to it. As a result, a frequency divider can be used at the beginning of the clock path to increase the period of the clock return signal to avoid using short pulses for clock return signals. For example, <FIG> illustrates a circuit diagram of an exemplary clock level set module <NUM> and an exemplary clock path <NUM> each coupled to multiple portions of a page buffer <NUM> for merging clock return signals, according to some aspects of the present disclosure, and <FIG> illustrates a timing diagram of an exemplary clock signal return scheme implemented by clock path <NUM> in <FIG>, according to some aspects of the present disclosure. Clock path <NUM> and clock level set module <NUM> can be parts of peripheral circuits <NUM> of memory device <NUM>. Clock path <NUM> may be one example of clock path <NUM> in <FIG>. It is understood that although for ease of illustration, clock level set module <NUM> is illustrated and described herein as a separate component coupled to page buffer <NUM>, clock level set module <NUM> may be a standalone circuit or part of another peripheral circuit <NUM>, such as part of page buffer <NUM>. For example, clock level set module <NUM> may be part of page buffer/sense amplifier <NUM> or part of control logic <NUM> in <FIG>.

Page buffer <NUM> described with respect to <FIG> and <FIG> may be, for example, page buffer/sense amplifier <NUM> in <FIG> that includes a plurality of portions, such as four quarters 504a, 504b, 504c, and 504d in <FIG>. Each quarter 504a, 504b, 504c, or 504d can be configured to sequentially receive a clock signal. For example, a clock signal (clk_dp) may be transferred from control logic <NUM> to page buffer/sense amplifier <NUM> and split into four clock signals (clk_dp_q0, clk_dp_q1, clk_dp_q2, and clk _dp_q3) by junctions <NUM>, 704a, and 704b of clock path <NUM>, which are respectively transferred to quarters 504a, 504b, 504c, and 504d through four quarter branches. Taking quarters <NUM> and <NUM> as an example, as shown in <FIG>, quarter <NUM> may be first selected and receives a first clock signal (clk_dp_q0) of the clock signal (clk_dp) in a read operation. At the end of the first clock signal (clk_dp_q0), the current selected quarter may change from quarter <NUM> to quarter <NUM>, which receives a second clock signal (clk_dp_q1) of the clock signal (clk_dp). It is understood that the clock signal timing may be similarly applied to quarters <NUM> and <NUM> when they are selected. It is also understood that the sequence of selecting each quarter, i.e., the sequence of receiving clock signals by the four quarters, may be preset, for example, in the order of quarters <NUM>, <NUM>, <NUM>, and <NUM>. It is further understood that depending on the specific read instruction, in a read operation, not all four quarters may always be selected. For example, depending on the starting address of the read data in page buffer/sense amplifier <NUM>, the first selected quarter may be any one of quarters <NUM>, <NUM>, <NUM>, and <NUM>. Similarly, depending on the length of the read data as well, the last selected quarter may be any one of quarters <NUM>, <NUM>, <NUM>, and <NUM>.

Each quarter 504a, 504b, 504c, or 504d can also be configured to sequentially return a clock return signal in response to receiving the corresponding clock signal. That is, in some implementations, each quarter 504a, 504b, 504c, or 504d returns a clock return signal once the corresponding clock signal is received, i.e., following the wave pipeline structure as described above. The sequence of returning the clock return signals by the four quarters can thus be the same as the sequence of receiving the clock signals by the four quarters, as well as the sequence of selecting each quarter. It is understood that the sequence of returning the clock return signals by the four quarters may be thus preset as well, for example, in the order of quarters <NUM>, <NUM>, <NUM>, and <NUM>.

In the embodiments of the invention, clock path <NUM> is coupled to the plurality of portions of page buffer <NUM> and configured to merge the plurality of clock return signals. For example, clock path <NUM> may be coupled to the four quarters of page buffer <NUM> and configured to merge the four clock return signals sequentially returned from the four quarters. It is understood that in some examples, not all four quarters may be selected in a read operation depending on the read instructions and thus, clock path <NUM> may merge only some of the four clock return signals accordingly in those examples. Nevertheless, clock path <NUM> can be capable of merging all four clock return signals sequentially returned from the four quarters when the four quarters are all selected in read operations.

In some implementations, clock level set module <NUM> is coupled to each quarter of page buffer <NUM> and configured to set the start level of a first clock return signal of the plurality of clock return signals based on the number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal can correspond to the first clock signal. The first clock signal is sent to the current selected portion of page buffer <NUM> in a read operation based on the read instruction, and the first clock return signal is returned by the current selected portion of page buffer <NUM> in response to receiving the first clock signal, according to some implementations. As a result, the end level of the first clock return signal can be set at a level that would not gate the second clock return signal next to the first clock return signal when the first and second clock return signals are merged by clock path <NUM>, as described below in detail.

In some implementations, each quarter of page buffer <NUM> includes a frequency divider <NUM> coupled to clock level set module <NUM>. Each frequency divider <NUM> is configured to receive a respective clock signal <NUM> (e.g., clk_dp_q0 or clk_dp_q1 in <FIG>) and generate the respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk_rtn_q2, or clk _rtn_q3) based on clock signal <NUM>. As shown in <FIG>, according to the invention, frequency divider <NUM> includes a flip-flop <NUM> coupled to clock level set module <NUM>. According to the invention, flip-flop <NUM> is a D flip-flop (DFF) with set/reset (SR). The DFF with SR may include a clock input, an SR input, a D input, a Q output and a Q output. The Q output of the DFF may be coupled to the D input via an inverter, and the Q output of the DFF may output the respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk_rtn_q2, or clk_rtn_q3). The clock input of the DFF may receive the respective clock signal (clk_dp_q0, clk_dp_q1, clk_dp_q2, or clk _dp_q3), and the SR input of the DFF may receive an SR signal from clock level set module <NUM>. Also referring to <FIG>, taking quarters <NUM> and <NUM>, for example, when quarter <NUM> is selected, frequency divider <NUM> coupled to quarter <NUM> can double the period of the first clock return signal (clk _rtrn_q0) from the period of the first clock signal (clk_dp_q0) to avoid transferring short pulses on clock path <NUM>. For example, the duty cycle of the first clock return signal (clk _rtrn_q0) may be <NUM>%. Similarly, when the current select quarter switches from quarter <NUM> to quarter <NUM>, frequency divider <NUM> coupled to quarter <NUM> can double the period of the second clock return signal (clk_rtrn_q1) from the period of the second clock signal (clk_dp_q1) as well. It is understood although only frequency divider <NUM> coupled to one of the quarters of page buffer <NUM> is shown in <FIG> for ease of illustration, frequency divider <NUM> may be similarly coupled to each of the four quarters of page buffer <NUM>.

Instead of using short pulses in clock return signals to avoid gating the clock return signals next to each other when merging the clock return signals (when switching the current select quarters), clock level set module <NUM> in conjunction with frequency dividers <NUM> can ensure that the end level of the clock return signal is at a level (either at a high level, e.g., Vdd, or at a low level, e.g., <NUM> V or Vss) that would not gate the subsequent clock return signal by setting the suitable start level of the clock return signal. According to the invention, to set the start level of the first clock return signal, clock level set module <NUM> is configured to determine the parity of the number of cycles in the first clock signal based on an address of the page buffer associated with the first clock signal, and set the start level of the first clock return signal based on the parity. The address is in a read instruction. Since the level of the clock return signal is toggled at each rising edge of the respective clock signal by frequency divider <NUM>, the parity (odd or even) of the number of cycles in the clock signal, as well as the start level (high or low) of the clock return signal determine the end level (high or low) of the clock return signal, according to some implementations. For example, the start and end levels of the clock return signal may be the same if the parity of the number of cycles in the clock signal is even, while the start and end levels of the clock return signal may be different if the parity of the number of cycles in the clock signal is odd.

As shown in <FIG>, according to the invention, clock level set module <NUM> includes an address unit <NUM> configured to receive a read instruction or a read command including the starting address of the data to be read from page buffer/sense amplifier <NUM>, and determine the parity of the number of cycles in the clock signal. As described above, clock level set module <NUM> can be part of page buffer/sense amplifier <NUM>, for example, as a dedicated integrated circuit (IC), such as an application-specific integrated circuit (ASIC), or can be part of control logic <NUM>, for example, as a dedicated IC or firmware/software code running on a microcontroller unit (MCU). Thus, address unit <NUM> can either receive the read instruction from a memory controller (e.g., <NUM> in <FIG>) when clock level set module <NUM> is part of control logic <NUM>, or receive a read command (control signals) from control logic <NUM> based on the read instruction from the memory controller when clock level set module <NUM> is part of page buffer/sense amplifier <NUM>. Nevertheless, address unit <NUM> is capable of identifying the starting address of the data to be read in the read operation in one of the four quarters of page buffer/sense amplifier <NUM>. According to the invention, the number of cycles in the first clock signal corresponds to the number of data units transferred in the corresponding portion of page buffer <NUM> with the first clock signal. That is, the clock signals can be synchronized with the data signals. Thus, based on the starting address in a read instruction, address unit <NUM> can determine the number of cycles in the clock signal sent to the current selected quarter. In some implementations, address unit <NUM> determines the parity based on the lowest bit of the address of the read data in a read instruction.

For example, as shown in <FIG>, for each of read instructions <NUM>, <NUM>, and <NUM>, the starting address may be in quarter <NUM>, which becomes the first select quarter. In read instruction <NUM>, clock level set module <NUM> may determine that there is an odd number (<NUM>) of cycle in the clock signal sent to quarter <NUM>, which will make the start and end levels of the clock return signal from quarter <NUM> to be different. In read instruction <NUM> or <NUM>, clock level set module <NUM> may determine that there is an even number (<NUM> or <NUM>) of cycles in the clock signal coupled to quarter <NUM>, which will make the start and end levels of the clock return signal from quarter <NUM> to be the same. It is understood that the starting address may not always be in quarter <NUM>. For example, for instruction <NUM>, the starting address may be in quarter <NUM>, and clock level set module <NUM> may determine that there is an even number (<NUM>) of cycles in the clock signal coupled to quarter <NUM>, which will make the start and end levels of the clock return signal from quarter <NUM> to be the same.

Referring back to <FIG>, according to the invention, clock level set module <NUM> includes an SR unit <NUM> configured to generate the SR signal to the SR input of flip-flop <NUM> based on the parity of the number of cycles in the clock signal. By setting or resetting flip-flop <NUM> (e.g., the DFF with SR) with the appropriate SR signal (high or low), the start level of the output, i.e., the first clock return signal, can be set to either high or low. Another factor taken into consideration when determining the appropriate SR signal for setting the start level of the first clock return signal is the way how the clock return signals are merged by clock path <NUM>. Clock path <NUM> includes either an OR gate or a NAND gate configured to merge two clock return signals. Thus, clock level set module <NUM> isfurther configured to set the start level of the first clock return signal based on the parity and whether the clock return signals are merged by the OR gate or the NAND gate. Gating may occur at an OR gate when the end level of first clock return signal is high, or at a NAND gate when the end level of the first clock return signal is low. In some implementations, the end level of the first clock return signal is low in response to clock path <NUM> including an OR gate to avoid gating at the OR gate. In some implementations, the end level of the first clock return signal is high in response to clock path <NUM> including a NAND gate to avoid gating at the NAND gate.

As shown in <FIG>, clock path <NUM> includes two OR gates <NUM> each configured to merge two clock return signals (clk_rtn_q0 and clk_rtn_q1, or clk_rtn_q2 and clk _rtn_q3) and generate a merged clock return signal (clk_rtn_q01 or clk_rtn_q23). As shown in <FIG>, for current select quarter <NUM>, since the parity of the number (<NUM>) of cycles in the first clock signal (clk_dp_q0) is even, and the first and second clock return signals (clk _rtn_q0 and clk_rtn_q1) is merged by OR gate <NUM>, the start level of the first clock return signal (clk _rtn_q0) may be set to low, such that the end level of the first clock return signal (clk _rtn_q0) may remain low to avoid gating the second clock return signal (clk_rtn_q0) next to the first clock return signal (clk_rtn_q0). As a result, the merged clock return signal (clk_rtn_q01) may be generated without the concern of gating even when short pulses are not used in the first or second clock return signal (clk_rtn_q0 or clk_rtn_q1).

In some implementations, clock level set module <NUM> is further configured to set the start level of a second clock return signal next to the first clock return signal to low in response to clock path <NUM> including an OR gate, and set the start level of the second clock return signal to high in response to clock path <NUM> including a NAND gate. That is, for the subsequent quarter next to the current select quarter, assuming the parity of the number of data units (the number of cycles of the corresponding clock signal) to be transferred in the entire quarter is preset to be even (e.g., <NUM> bytes), since the start and end levels of the corresponding clock return signal would be the same, clock level set module <NUM> can determine the start level of the corresponding clock return signal based on whether the first and second clock return signals are merged by an OR gate or AND gate alone. In case the data transferred in the subsequent quarter may not occupy the entire quarter, i.e., no further quarter and clock return signals may be needed in the read operation, the gating would not be an issue for the second clock return signal then since no more merging is needed.

For example, as shown in <FIG>, for read instruction <NUM> or <NUM>, since the data to be read covers the entirety of each of quarter <NUM>, <NUM>, and <NUM> (selected after the current select quarter <NUM>), assuming OR gates are used for merging clock return signals, clock level set module <NUM> may set the start level of each clock return signal from quarter <NUM>, <NUM>, or <NUM> to low. For read instruction <NUM>, since the data to be read covers the entirety of quarter <NUM> (selected after the current select quarter <NUM>), clock level set module <NUM> may set the start level of the clock return signal from quarter <NUM> to low. As to read instruction <NUM>, since the data to be read covers the entirety of each of quarters <NUM> and <NUM> (selected after the current select quarter <NUM>), but a part of quarter <NUM>, clock level set module <NUM> may set the start level of the clock return signal from quarter <NUM> to low and set the start level of the clock return signal from quarter <NUM> to any level as there is no more clock return signal next to it.

Referring back to <FIG>, clock path <NUM> can further include an OR gate <NUM> configured to further merge the two merged clock return signals (clk_rtn_q01 and clk_rtn_q23) to generate a merged clock return signal (clk_rtn) that merges the four clock return signals (clk _rtn_q0, clk_rtn_q1, clk_rtn_q2, and clk_rtn_q3) from the four quarters. In some implementations, clock path <NUM> further includes one or more delay circuits, for example, a delay circuit <NUM> after each frequency divider <NUM>, and a delay circuit <NUM> after OR gate <NUM>, to synchronize the clock return signals with corresponding data signals in case a misalignment occurs during the transfer of the clock return signals by clock path <NUM>. For example, the merged clock return signal (clk_rtn) may become a synchronized merged clock return signal (clk_rtn_sryne) after passing delay circuit <NUM> to be used for reading the aligned data signals.

<FIG> illustrates a flowchart of a method <NUM> for operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device <NUM>. Method <NUM> may be implemented by clock level set module <NUM>. It is understood that the operations shown in method <NUM> may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a read instruction is received. For example, control logic <NUM> of memory device <NUM> may receive a read instruction from memory controller <NUM> in a read operation. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an address of the page buffer is obtained in the read instruction. For example, clock level set module <NUM> of memory device <NUM> may obtain the starting address of data to be read from page buffer/sense amplifier <NUM> in the read instruction. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a parity of a number of cycles in a first clock signal is determined based on the address. The first clock signal is received by a first portion of the page buffer. The number of cycles in the first clock signal can correspond to a number of data units transferred in the first portion of the page buffer with the first clock signal. For example, clock level set module <NUM> of memory device <NUM> may determine the parity of the number of cycles in the clock signal sent to the current select quarter based on the starting address.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a start level of a first clock return signal is set based on the parity. The first clock return signal is returned by the first portion of the page buffer in response to receiving the first clock signal. The duty cycle of the first clock return signal can be <NUM>%. For example, clock level set module <NUM> and frequency divider <NUM> of memory device <NUM> may set the start level of the clock return signal from the current select quarter based on the parity. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a start level of a second clock return signal is set to be a same level as an end level of the first clock return signal. The second clock return signal is returned next to the first clock return signal by a second portion of the page buffer. For example, clock level set module <NUM> and another frequency divider <NUM> of memory device <NUM> may set the start level of the subsequent clock return signal from the next select quarter to be the same level as the end level of the clock return signal.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

Claim 1:
A circuit, comprising:
a page buffer (<NUM>, <NUM>) comprising a plurality of portions, each of the portions being configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal;
a clock path (<NUM>) coupled to the plurality of portions of the page buffer (<NUM>, <NUM>) and configured to merge the plurality of clock return signals; characterized by
a clock level set module (<NUM>) coupled to the page buffer (<NUM>, <NUM>) and configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals, the first clock return signal corresponding to the first clock signal,
wherein the clock path (<NUM>) includes either an OR gate or a NAND gate configured to merge two clock return signals,
wherein the clock level set module (<NUM>) is further configured to set the start level of the first clock return signal based on the parity and whether the clock return signals are merged by the OR gate or the NAND gate,
the circuit further characterized by a frequency divider (<NUM>) comprising a D flip-flop (<NUM>) with set/reset (SR) coupled to the clock level set module (<NUM>) and configured to receive a respective clock signal (<NUM>, clk_dp_q0 or clk _dp_q1) and generate the respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk _rtn_q2, or clk _rtn_q3) based on the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1),
wherein the clock level set module (<NUM>) comprises an address unit (<NUM>) configured to receive a read instruction or a read command (RD INSTR/CMD) including the starting address of the data to be read from page buffer (<NUM>, <NUM>) and determine the parity of the number of cycles in the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1) based on an address of the page buffer associated with the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1) and an SR unit (<NUM>) coupled to the address unit (<NUM>) and configured to generate an SR signal to an SR input of D flip-flop (<NUM>) based on the parity of the number of cycles in the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1), wherein the number of cycles in the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1) corresponds to the number of data units transferred in the corresponding portion of page buffer (<NUM>) with the respective clock signal (<NUM>, clk_dp_q0 or clk_dp_q1).