Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. <CIT> discloses a monolithic three-dimensional memory device, which comprises: a first tier structure located over a top surface of a substrate and comprising a first alternating stack of first insulating layers and first electrically conductive layers; an insulating cap layer overlying the first tier structure; a second tier structure located over the insulating cap layer and comprising a second alternating stack of second insulating layers and second electrically conductive layers; and a memory stack structure comprising a first memory film located within the first tier structure, a second memory film located within the second tier structure, and a semiconductor channel that extends through the second tier structure, the insulating cap layer, and the first tier structure, wherein the semiconductor channel contacts the insulating cap layer.

<CIT> discloses a memory array which includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

The invention provides a three-dimensional memory device as defined in claim <NUM> and a method of making a three-dimensional memory device as defined in claim <NUM>.

Although specific configurations and arrangements are discussed, this should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

As used herein, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A "step" or "staircase" refers to a vertical shift in the height of a set of adjoined surfaces. In the present disclosure, the term "staircase" and the term "step" refer to one level of a staircase structure and are used interchangeably. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with the top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.

In the following description, the use of "may" prior to a feature included in one of the independent claims does not render the feature an optional feature.

NAND flash memory devices, widely used in various electronic products, are non-volatile, light-weighted memory of low power consumption and good performance. Currently, planar NAND flash memory devices have reached its storage limit. To further increase the storage capacity and reduce the storage cost per bit, 3D NAND memory devices have been proposed. The process to form an existing 3D NAND memory device often includes the following operations. First, a stack structure of a plurality of interleaved sacrificial layers and insulating layers are formed over a substrate. A channel hole is formed extending in the stack structure. The bottom of the channel hole is etched to form a recess in the substrate. An epitaxial portion is formed at the bottom of the channel hole by selective epitaxial growth. A semiconductor channel, conductively connected to the epitaxial portion, is formed in the channel hole. The sacrificial layers can be removed and replaced with conductor layers. The conductor layers function as word lines in the 3D NAND memory device.

An existing 3D NAND memory device often includes a plurality of memory blocks. Adj acent memory blocks are often separated by a GLS, in which an array common source (ACS) is formed. In the fabrication method to form the existing 3D NAND memory device, the feature size of the GLS is susceptible to fluctuation, potentially affecting the performance of the 3D NAND memory device.

The present disclosure provides 3D memory devices (e.g., 3D NAND memory devices) formed by using a support structure in the fabrication of a slit structure (e.g., GLS) and a source structure, and methods for forming the 3D memory devices. During the fabrication of a 3D memory device, a support structure is formed over a stack structure. The support structure has a plurality of first openings that divide the stack structure into a plurality of block portions (e.g., regions in the stack structure in which memory blocks are formed). The support structure also includes a plurality of connection portions that are in contact with (i.e., connecting) portions of the support structure on both sides of the first openings. The support structure can be used as an etch mask for the formation of the slit structure. During the etching of the stack structure to form the slit structure, the support structure can provide support to the block portions of the stack structure, so as to reduce deformation of the slit structure. The support structure can be removed before or after the formation of a source structure (e.g., ACS) formed in the slit structure. The timing to remove the support structure has little or no impact on the formation of the source structure. In some embodiments, the support structure is removed after the formation of the source structure to provide support to the 3D memory device during the formation of the source structure. To further reduce the susceptibility of the slit structure to deformation, in some embodiments, the conductor layers, e.g., in the block portions and exposed by the slit structure, undergo a recess etch to form a plurality of recessed portions on the conductor layers and a plurality of protruding portions on the insulating layers. The offset between a conductor layer and adjacent insulating layers in the slit structure can improve the bonding/adhesion between the source structure (or the insulating structure of the source structure) and the slit structure (or the sidewall of the slit structure), improving the structural stability of the slit structure and the source structure). The 3D memory device is then less susceptible to deformation or damages during the fabrication process. By applying the structures and methods of the present disclosure, adjacent block portions can be connected through the support structures during the formation of slit structures and source contacts; the 3D memory device is thus less likely to deform during the fabrication process. The feature size of the slit structure is less susceptible to fluctuation.

<FIG> illustrates an exemplary 3D memory device <NUM>, according to some embodiments. <FIG> illustrates a cross-sectional view of the 3D memory device <NUM> shown in <FIG> along the A-B direction. <FIG> illustrates a cross-sectional view of the 3D memory device <NUM> shown in <FIG> along the C-D direction.

As shown in <FIG>, <FIG> memory device <NUM> may include a substrate <NUM> and a stack structure <NUM> over substrate <NUM>. 3D memory device <NUM> may also include one or more source structures <NUM> aligned along the y-direction, dividing a memory region (e.g., a region in 3D memory device <NUM> where memory cells are formed) of 3D memory device <NUM> into a plurality of block portions <NUM> arranged in parallel along the y-direction. Memory cells may be formed in each block portion <NUM>, forming a memory block. In each block portion <NUM>, stack structure <NUM> may include a plurality of conductor layers and a plurality of insulating layers <NUM> interleaved over a buffer oxide layer <NUM> on substrate <NUM>. In some embodiments, the plurality of conductor layers may include a top conductor layer <NUM> having a plurality of top select conductor layers, a bottom conductor layer <NUM> having a plurality of bottom select conductor layers, and control conductor layers <NUM> between top conductor layer <NUM> and bottom conductor layer <NUM>. Top conductor layer <NUM> may function as top select gate electrodes, and bottom conductor layer <NUM> may function as bottom select gate electrodes. 3D memory device <NUM> may include a buffer oxide layer <NUM> between substrate <NUM> and bottom conductor layer <NUM>.

3D memory device <NUM> may also include a dielectric cap layer <NUM> covering the stack structure <NUM>. In each block portion <NUM>, 3D memory device <NUM> may include a plurality of channel structures <NUM> extending from a top surface of dielectric cap layer <NUM> into substrate <NUM> along the vertical direction (e.g., the z-direction). Each channel structure <NUM> may include an epitaxial portion <NUM> at a bottom portion, a drain structure <NUM> at a top portion, and a semiconductor channel <NUM> between epitaxial portion <NUM> and drain structure <NUM>. Semiconductor channel <NUM> may include a memory film <NUM>, a semiconductor layer <NUM>, and a dielectric core <NUM>. Epitaxial portion <NUM> may contact and be conductively connected to substrate <NUM>, and semiconductor channel <NUM> may contact and be conductively connected to drain structure <NUM> and epitaxial portion <NUM>. A plurality of memory cells may be formed by semiconductor channels <NUM> and control conductor layers <NUM>. Stack structure <NUM> may also be referred to as a memory stack.

3D memory device <NUM> may include at least one source structure <NUM> extending vertically along the z-direction and laterally along the x-direction between block portions. Each source structure <NUM> may be formed in a respective slit structure and may extend from a top surface of 3D memory device <NUM> (e.g., a top surface of dielectric layer cap <NUM>) through stack structure <NUM> and form contact with substrate <NUM>. Source structure <NUM> may include an insulating structure <NUM> and a source contact <NUM> in insulating structure <NUM>. Source contact <NUM> may be in contact with substrate <NUM> and may be insulated from conductor layers (e.g., <NUM>, <NUM>, and <NUM>) in adjacent block portions <NUM> by respective insulating structure <NUM>. In some embodiments, conductor layers (e.g., <NUM>, <NUM>, and <NUM>) on a sidewall of the slit structure may each form a recessed portion, e.g., form an offset with adjacent insulating layers <NUM>. Accordingly, insulating layers <NUM> may each form a protruding portion on the sidewall of the slit structure. In some embodiments, at one or more locations along the x-direction, a diameter D of the slit structure increases from a top surface of the slit structure towards a lower position (e.g., a middle position) of the slit structure, and a diameter d of source contact <NUM> increases from a top surface of source structure <NUM> towards a lower portion (e.g., a middle portion) of source structure <NUM>/source contact <NUM>. Details of each structure in 3D memory device <NUM> are described as follows.

Substrate <NUM> can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some embodiments, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, substrate <NUM> includes silicon.

Channel structures <NUM> may form an array in each block portion <NUM> and may each extend vertically above substrate <NUM>. Channel structure <NUM> may extend through a plurality of pairs each including a conductor layer (e.g., <NUM>, <NUM>, or <NUM>) and an insulating layer <NUM> (referred to herein as "conductor/insulating layer pairs"). At least on one side along a horizontal direction (e.g., x-direction and/or y-direction), stack structure <NUM> can include a staircase structure. The number of the conductor/insulating layer pairs in stack structure <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) determines the number of memory cells in 3D memory device <NUM>. In some embodiments, conductor layers (e.g., <NUM>, <NUM>, and <NUM>) and insulating layers <NUM> in stack structure <NUM> are alternatingly arranged along the vertical direction in block portions <NUM>. Conductor layers (e.g., <NUM>, <NUM>, and <NUM>) can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Insulating layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, buffer oxide layer <NUM> and dielectric cap layer <NUM> each includes a dielectric material such as silicon oxide. In some embodiments, top conductor layer <NUM> includes a plurality of top select conductor layers, which function as the top select gate electrodes. Control conductor layers <NUM> may function as select gate electrodes and form memory cells with intersecting channel structures <NUM>. In some embodiments, bottom conductor layer <NUM> includes a plurality of bottom select conductor layers, which function as the bottom select gate electrodes. Top select gate electrodes and bottom select gate electrodes can respectively be applied with desired voltages to select a desired memory block/finger/page.

As shown in <FIG>, channel structure <NUM> can include a semiconductor channel <NUM> extending vertically through stack structure <NUM>. Semiconductor channel <NUM> can include a channel hole filled with a channel-forming structure, e.g., semiconductor materials (e.g., as a semiconductor layer <NUM>) and dielectric materials (e.g., as a memory film <NUM>). In some embodiments, semiconductor layer <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a memory layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole of semiconductor channel <NUM> can be partially or fully filled with a dielectric core <NUM> including dielectric materials, such as silicon oxide. Semiconductor channel <NUM> can have a cylinder shape (e.g., a pillar shape). Dielectric core <NUM>, semiconductor layer <NUM>, the tunneling layer, the memory layer, and the blocking layer are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the memory layer can include a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

In some embodiments, channel structure <NUM> further includes an epitaxial portion <NUM> (e.g., a semiconductor plug) in the lower portion (e.g., at the lower end of bottom) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the vertical direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the vertical direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Epitaxial portion <NUM> can include a semiconductor material, such as silicon, which is epitaxially grown from substrate <NUM> in any suitable directions. It is understood that in some embodiments, epitaxial portion <NUM> includes single crystalline silicon, the same material as substrate <NUM>. In other words, epitaxial portion <NUM> can include an epitaxially-grown semiconductor layer grown from substrate <NUM>. Epitaxial portion <NUM> can also include a different material than substrate <NUM>. In some embodiments, epitaxial portion <NUM> includes at least one of silicon, germanium, and silicon germanium. In some embodiments, part of epitaxial portion <NUM> is above the top surface of substrate <NUM> and in contact with semiconductor channel <NUM>. Epitaxial portion <NUM> may be conductively connected to semiconductor channel <NUM>. In some embodiments, a top surface of epitaxial portion <NUM> is located between a top surface and a bottom surface of a bottom insulating layer <NUM> (e.g., the insulating layer at the bottom of stack structure <NUM>).

In some embodiments, channel structure <NUM> further includes drain structure <NUM> (e.g., channel plug) in the upper portion (e.g., at the upper end) of channel structure <NUM>. Drain structure <NUM> can be in contact with the upper end of semiconductor channel <NUM> and may be conductively connected to semiconductor channel <NUM>. Drain structure <NUM> can include semiconductor materials (e.g., polysilicon) or conductive materials (e.g., metals). In some embodiments, drain structure includes an opening filled with Ti/TiN or Ta/TaN as an adhesion layer and tungsten as a conductor material. By covering the upper end of semiconductor channel <NUM> during the fabrication of 3D memory device <NUM>, drain structure <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in semiconductor channel <NUM>, such as silicon oxide and silicon nitride.

In some embodiments, source structure <NUM> includes a source contact <NUM> in an insulating structure <NUM>, extending laterally along the x-direction. Source contact <NUM> may be in contact with and form a conductive connection with substrate <NUM> for applying a source voltage on memory cells. In some embodiments, source contact <NUM> includes one or more of polysilicon, silicides, germanium, silicon germanium, copper, aluminum, cobalt, and tungsten. In some embodiments, insulating structure <NUM> includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

Each source structure <NUM> may be formed in the respective slit structure that extends along the same vertical and lateral directions along which source structure <NUM> extends. In some embodiments, a sidewall of the slit structure may include a plurality of protruding portions and a plurality of recessed portions. Each protruding portion may be sandwiched by two adjacent recessed portions, and vice versa. The protruding portions are formed on insulating layers <NUM>. The recessed portions are formed on conductor layers (e.g., <NUM>, <NUM>, and <NUM>). An offset is formed between a protruding portion (or insulating layer <NUM>) and an adjacent recessed portion (or conductor layer (<NUM>, <NUM>, or <NUM>) on the sidewall of the slit structure. Insulating structure <NUM> may be in contact with the protruding portions and/or the recessed portions. In some embodiments, insulating structure <NUM> is in contact with both the protruding portions and the recessed portions.

Along the lateral direction in which it extends, e.g., the x-direction, a width of the slit structure and/or source structure <NUM> may vary. <FIG> illustrates a cross-sectional view of source structure <NUM> and surrounding structures along the A-B direction. <FIG> illustrates a cross-sectional view of source structure <NUM> and surrounding structures along the C-D direction. The A-B direction may be at a first location and <FIG> illustrates a cross-sectional view of gate structure <NUM> at the first location along the x-direction. The C-D direction may be at a second location and <FIG> illustrates a cross-sectional view of source structure <NUM> at the second location along the x-direction. At the first location, a width D of source structure <NUM> (or the slit structure) along the y-direction may increase from the top portion of source structure (or the slit structure) towards a lower portion of source structure <NUM> (or the slit structure). In some embodiments, a width d of source contact <NUM> along the y-direction may increase from the top portion of source contact <NUM> towards a lower portion of source contact <NUM>. At the second location, a width of source structure <NUM> (or the slit structure) along the y-direction may decrease from the top portion of source structure (or the slit structure) towards a lower portion of source structure <NUM> (or the slit structure). In some embodiments, width D of source structure <NUM> along the y-direction may decrease from the top portion of source structure <NUM> towards a lower portion of source structure <NUM>, and width d of source contact <NUM> may decrease from the top portion of source contact <NUM> towards a lower portion of source contact <NUM>. The variation of widths of the slit structure, source structure <NUM>, and/or source contact <NUM> may be caused by the use of support structure during the fabrication of the slit structure and source structure <NUM>. In some embodiments, portions of dielectric cap layer <NUM> covered by the support structure during the fabrication process may not be completely removed along the y-direction for the formation of the slit structure. Accordingly, the removal of portions of stack structure <NUM> under dielectric cap layer <NUM> may increase (e.g., be removed more completely) from the top portion of the slit structure towards a lower portion of the slit structure, forming the slit structure with increasing width along the z-direction towards substrate <NUM>.

Along the x-direction, a distance range of the slit structure formed under the coverage of the support structure may be referred to as a first distance range R1, and a distance range of the slit structure formed without the coverage of the support structure may be referred to as a second distance range R2. In some embodiments, one slit structure extends along at least one first distance range R1 and at least one second distance range R2 along the x-direction. In some embodiments, in first distance range R1, the width of the slit structure along the y-direction increases from the top surface of the slit structure to at least a middle portion of the slit structure and width d of source contact 141cincreases from the top surface of source contact <NUM> to at least the middle portion of source contact <NUM>. In some embodiments, in second distance range R2, the width of slit structure along the y-direction decreases from the top surface of the slit structure to the middle portion of the slit structure and width d of source contact <NUM> decreases from the top surface of source contact <NUM> to the middle portion of source contact <NUM>. As shown in <FIG>, the boundaries of the slit structure may have an arch shape, e.g., extending inwardly along the x-y plane in first distance range R1, while extend in parallel in second distance range R2. In some embodiments, first distance ranges R1 in different slit structures may be aligned along the y-direction, and second distance ranges R2 in different slit structures may be aligned along the y-direction.

In some embodiments, width d of source contact and width D of source structure <NUM> or the slit structure may each be nominally uniform along the z-direction. That is, the use of the support structure during the fabrication of 3D memory device <NUM> may have little or no impact on the dimensions of the slit structure and/or source contact <NUM>. Whether there is noticeable variation in the widths of source structure <NUM>, slit structure, and source contact <NUM> should not be limited by the embodiments of the present disclosure.

3D memory device <NUM> can be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., NAND channel structures) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, 3D memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate <NUM>) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It is understood that in some embodiments, the memory array device substrate (e.g., substrate <NUM>) is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate (e.g., substrate <NUM>) can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the backside of the thinned memory array device substrate.

<FIG> illustrate a fabrication process to form 3D memory device <NUM>, and <FIG> illustrates a flowchart <NUM> of the fabrication process, according to some embodiments.

At the beginning of the process, a support structure is formed over a stack structure (Operation <NUM>). The stack structure includes interleaved a plurality of initial insulating layers and a plurality of initial sacrificial layers). The support structure includes a plurality of support openings aligned along a lateral direction and exposing the stack structure. The support structure also includes at least one connection portion each between and in contact with adjacent support openings. <FIG> illustrate corresponding structures <NUM> and <NUM>.

As shown in <FIG> and <FIG>, a stack structure <NUM> having a dielectric stack of interleaved initial insulating layers 104i and initial sacrificial layers 103i is formed over a substrate <NUM>. Initial sacrificial layers 103i may be used for subsequent formation of conductor layers <NUM>, <NUM>, and <NUM>. Initial insulating layers 104i may be used for subsequent formation of insulating layers <NUM>. In some embodiments, stack structure <NUM> includes a dielectric cap layer <NUM> over initial sacrificial layers 103i and initial insulating layers 104i.

Stack structure <NUM> may have a staircase structure along the x-direction and/or the y-direction (not shown in the figures). The staircase structure can be formed by repetitively etching a material stack that includes a plurality of interleaved sacrificial material layers and insulating material layers using an etch mask, e.g., a patterned PR layer over the material stack. The interleaved sacrificial material layers and the insulating material layers can be formed by alternatingly depositing layers of sacrificial material and layers of insulating material over buffer oxide layer <NUM> until a desired number of layers is reached. In some embodiments, a sacrificial material layer is deposited over buffer oxide layer <NUM>, and an insulating material layer is deposited over the sacrificial material layer, so on and so forth. The sacrificial material layers and insulating material layers can have the same or different thicknesses. In some embodiments, a sacrificial material layer and the underlying insulating material layer are referred to as a dielectric pair. In some embodiments, one or more dielectric pairs can form one level/staircase. During the formation of the staircase structure, the PR layer is trimmed (e.g., etched incrementally and inwardly from the boundary of the material stack, often from all directions) and used as the etch mask for etching the exposed portion of the material stack. The amount of trimmed PR can be directly related (e.g., determinant) to the dimensions of the staircases. The trimming of the PR layer can be obtained using a suitable etch, e.g., an isotropic dry etch such as a wet etch. One or more PR layers can be formed and trimmed consecutively for the formation of the staircase structure. Each dielectric pair can be etched, after the trimming of the PR layer, using suitable etchants to remove a portion of both the sacrificial material layer and the underlying insulating material layer. The etched sacrificial material layers and insulating material layers may form initial sacrificial layers 103i and initial insulating layers 104i. The PR layer can then be removed.

The insulating material layers and sacrificial material layers may have different etching selectivities during the subsequent gate-replacement process. In some embodiments, the insulating material layers and the sacrificial material layers include different materials. In some embodiments, the insulating material layers include silicon oxide, and the deposition of insulating material layers include one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering. In some embodiments, the sacrificial material layers include silicon nitride, and the deposition of insulating material layers include one or more of CVD, PVD, ALD, and sputtering. In some embodiments, the etching of the sacrificial material layers and the insulating material layers include one or more suitable anisotropic etching process, e.g., dry etch.

A plurality of channel structures <NUM> may be formed in stack structure <NUM>. A plurality of channel holes may be formed extending vertically through stack structure <NUM>. In some embodiments, a plurality of channel holes are formed through the interleaved initial sacrificial layers 103i and initial insulating layers 104i. The plurality of channel holes may be formed by performing an anisotropic etching process, using an etch mask such as a patterned PR layer, to remove portions of stack structure <NUM> and expose substrate <NUM>. In some embodiments, a plurality of channel holes are formed in each block portion <NUM>. A recess region may be formed at the bottom of each channel hole to expose a top portion of substrate <NUM> by the same etching process that forms the channel hole above substrate <NUM> and/or by a separate recess etching process. In some embodiments, a semiconductor plug is formed at the bottom of each channel hole, e.g., over the recess region. The semiconductor plug may be formed by an epitaxial growth process and/or a deposition process. In some embodiments, the semiconductor plug is formed by epitaxial growth and is referred to as epitaxial portion <NUM>. Optionally, a recess etch process (e.g., dry etch and/or wet etch) may be performed to remove excess semiconductor material on the sidewall of the channel hole and/or control the top surface of epitaxial portion <NUM> at a desired position. In some embodiments, the top surface of epitaxial portion <NUM> is located between the top and bottom surfaces of the bottom initial insulating layer 104i.

In some embodiments, the channel holes are formed by performing a suitable etching process, e.g., an anisotropic etching process (e.g., dry etch) and/or an isotropic etching process (wet etch). In some embodiments, epitaxial portion <NUM> includes single crystalline silicon and is formed by epitaxially grown from substrate <NUM>. In some embodiments, epitaxial portion <NUM> includes polysilicon formed by a deposition process. The formation of epitaxially-grown epitaxial portion <NUM> can include, but not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof. The formation of epitaxial portion <NUM> may include, but not limited by, CVD, PVD, and/or ALD.

In some embodiments, a semiconductor channel <NUM> is formed over and contacting epitaxial portion <NUM> in the channel hole. Semiconductor channel can include a channel-forming structure that has a memory film <NUM> (e.g., including a blocking layer, a memory layer, and a tunneling layer), a semiconductor layer <NUM> formed above and connecting epitaxial portion <NUM>, and a dielectric core <NUM> filling up the rest of the channel hole. In some embodiments, memory film <NUM> is first deposited to cover the sidewall of the channel hole and the top surface of epitaxial portion <NUM>, and semiconductor layer <NUM> is then deposited over memory film <NUM> and above epitaxial portion <NUM>. The blocking layer, memory layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor layer <NUM> can then be deposited on the tunneling layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, dielectric core <NUM> is filled in the remaining space of the channel hole by depositing dielectric materials after the deposition of semiconductor layer <NUM>, such as silicon oxide.

In some embodiments, drain structure <NUM> is formed in the upper portion of each channel hole. In some embodiments, parts of memory film <NUM>, semiconductor layer <NUM>, and dielectric core <NUM> on the top surface of stack structure <NUM> and in the upper portion of each channel hole can be removed by CMP, grinding, wet etching, and/or dry etching to form a recess in the upper portion of the channel hole so that a top surface of semiconductor channel may be between the top surface and the bottom surface of dielectric cap layer <NUM>. Drain structure <NUM> then can be formed by depositing conductive materials, such as metals, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. A channel structure <NUM> is thereby formed. A plurality of memory cells may subsequently be formed by the intersection of semiconductor channels <NUM> and control conductor layers <NUM>. Optionally, a planarization process, e.g., dry/wet etch and/or CMP, is performed to remove any excess material on the top surface of stack structure <NUM>.

As shown in <FIG> and <FIG>, a support layer 116i can be formed over stack structure <NUM>. Support layer 116i may include a material different from initial sacrificial layers 103i and initial insulating layers 104i. In some embodiments, support layer 116i includes one or more of polysilicon, silicon germanium, and silicon carbide. Support layer 116i may be formed by CVD, PVD, ALD, and/or sputtering. In some embodiments, support layer 116i includes polysilicon and is formed by CVD. In some embodiments, support layer 116i includes the same material as initial insulating layers 104i. Support layer 116i may include a single-layer structure or a multi-layer structure. For example, support layer 116i can include more than one material in a multi-layer structure. A plurality of pits (e.g., recessed areas) are formed on the top surface of stack structure <NUM> (e.g., top surface of dielectric cap layer <NUM>. The formation of support layer 116i fills the pits with the material of support layer 116i, increasing the bonding between support layer 116i and stack structure <NUM>. In the subsequent formation of slit structures, the support structure (e.g., formed based on support layer 116i) more effectively supports the 3D memory device, improving the structural stability of the 3D memory device. The pits may be formed by any suitable method such as wet etch.

A patterned mask layer <NUM> may be formed over support layer 116i. Patterned mask layer <NUM> may include a patterned photoresist layer, formed by spinning on a layer of photoresist layer on support layer 116i and patterning it with a photolithography process. Patterned mask layer <NUM> may include a plurality of mask openings <NUM> aligned along the x-direction and at least one mask portion <NUM> in contact with (e.g., connecting) adjacent mask openings <NUM>. Mask openings <NUM> may expose support layer 116i and mask portions <NUM> may cover portions of support layer 116i. The area and locations of mask openings <NUM> may correspond to the area and locations of support openings subsequently formed in the fabrication process, and the area and locations of mask portions <NUM> may correspond to the area and locations of connection portions subsequently formed in the fabrication process. Mask openings <NUM> and mask portions <NUM> aligned along the x-direction may form a mask pattern <NUM>, which corresponds to the area and location of a slit structure subsequently formed in the fabrication process. In some embodiments, a plurality of mask patterns <NUM> may be formed, extending along the x-direction and being arranged parallel along the y-direction.

As shown in <FIG>, patterned mask layer <NUM> may be used as an etch mask to remove portions of support layer 116i and expose stack structure <NUM>. A support structure <NUM>, having a plurality of support openings <NUM> and at least one connection portion <NUM>, may be formed. Each connection portion <NUM> may cover a portion of stack structure <NUM> (e.g., cover a portion of the top surface of dielectric cap layer <NUM>). One or more support openings <NUM> may be aligned along the x-direction, and at least one connection portion <NUM> may each be in contact with (e.g., connecting) adjacent support openings <NUM>. The support openings <NUM> and connection portions <NUM> aligned along the x-direction may form a support pattern <NUM>, which corresponds to the location and area of the subsequently-formed slit structure. Optionally, patterned mask layer <NUM> is removed after the formation of support openings <NUM> and connection portions <NUM>. A suitable etching process, e.g., dry and/or wet etch, can be performed to form support pattern <NUM>. In some embodiments, each support pattern <NUM> includes at least two support openings <NUM> and at least one connection portion <NUM>. In some embodiments, structure <NUM> includes at least two support patterns <NUM> arranged in parallel along the y-direction. The number of support openings <NUM> and connection portions <NUM> in each support pattern <NUM> should be determined based on the design and fabrication process (e.g., the area of the memory region and/or the length of the slit structure) and should not be limited by the embodiments of the present disclosure. In some embodiments, a support portion <NUM>, of support structure <NUM>, between adjacent support patterns <NUM> may correspond to the location and area of subsequently formed block portion <NUM>. In some embodiments, connection portions <NUM> of different support patterns <NUM> may be aligned along the y-direction. Referring back to <FIG>, connection portions <NUM> may be formed in (or may cover) first distance ranges R1, and support openings <NUM> may be formed in (or may cover) second distance ranges R2.

Referring back to <FIG>, after the formation of the support structure, the support structure is used as an etch mask to remove portions of the stack structure and form a plurality of first openings in the stack structure and at least one stack portion under the connection portion (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>.

As shown in <FIG>, support structure <NUM> may be used as an etch mask to remove portions of stack structure <NUM> exposed by support openings <NUM> to expose substrate <NUM>, forming a plurality of first openings <NUM> in stack structure <NUM>. A stack portion <NUM>-<NUM> may also be formed under each connection portion <NUM>. At least two first openings <NUM> may be aligned along the x-direction and extend vertically and laterally in stack structure <NUM>. Connection portion <NUM> may be in contact with (e.g., connecting) adjacent first openings <NUM>. In some embodiments, dielectric cap layer <NUM> and buffer oxide layer <NUM> may also be patterned to form a dielectric cap portion <NUM>-<NUM> and a buffer oxide portion <NUM>-<NUM> in stack portion <NUM>-<NUM>. Referring back to <FIG>, stack portions <NUM>-<NUM> may be formed in (or may cover) first distance ranges R1, and first openings <NUM> may be formed in (or may cover) second distance ranges R2.

A stack portion <NUM>-<NUM> may include interleaved a plurality of sacrificial portions <NUM>-<NUM> and a plurality of insulating portions <NUM>-<NUM>, stacking between substrate <NUM> (or buffer oxide portion <NUM>-<NUM>) and connection portion <NUM> (or dielectric cap portion <NUM>-<NUM>). Sacrificial portions <NUM>-<NUM> and insulating portions <NUM>-<NUM> may be formed by removing portions of initial sacrificial layers 103i and initial insulating layers 104i exposed by support openings <NUM>. The remaining portions of initial sacrificial layers 103i and initial insulating layers 104i separated by first openings <NUM> may respectively form sacrificial layers <NUM> and insulating layers <NUM>. In some embodiments, each sacrificial portion <NUM>-<NUM> may be in contact with adjacent sacrificial layers <NUM> and each insulating portion <NUM>-<NUM> may be in contact with adjacent insulating layer <NUM>. In some embodiments, an anisotropic etching process, e.g., dry etch, is performed to form first openings <NUM>. The etchant of the anisotropic etching process may selectively etch initial sacrificial layers 103i, initial insulating layers 104i, dielectric cap layer <NUM>, and buffer oxide layer <NUM> over support structure <NUM>. For example, the dry etch may include a plasma etching process, and the etchant may include fluorine-containing gases.

Referring back to <FIG>, after the formation of first openings and stack portions, the stack portions are removed to form at least one second opening in contact with adjacent first openings and form at least one initial slit structure and a plurality of block portions (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures <NUM> and <NUM>.

As shown in <FIG> and <FIG>, sacrificial portions <NUM>-<NUM> and insulating portions <NUM>-<NUM> in stack portion <NUM>-<NUM> may be respectively removed. In some embodiments, dielectric cap portion <NUM>-<NUM> and buffer oxide portion <NUM>-<NUM> are also removed, e.g., together with insulating portions <NUM>-<NUM>. A second opening <NUM> (e.g., illustrated in <FIG>) can be formed under each connection portion <NUM>. Second opening <NUM> may be in contact with (e.g., connecting) adjacent first openings <NUM> to form an initial slit structure <NUM>. In some embodiments, initial slit structure <NUM> extend laterally along the x-direction and vertically through stack structure <NUM>. The portion of stack structure <NUM> between adjacent initial slit structures <NUM> form a block portion <NUM>. In some embodiments, more than one initial slit structures <NUM> and a plurality of block portions <NUM> are formed. The plurality of block portions <NUM> may be disconnected from one another by the more than one initial slit structures <NUM>. Each block portion <NUM> may include interleaved a plurality of sacrificial layers <NUM> and a plurality of insulating layers <NUM>.

The order to remove sacrificial portions <NUM>-<NUM> and insulating portions <NUM>-<NUM> in stack portion <NUM>-<NUM> may be dependent on the fabrication process, e.g., the order and type of etchant used in the etching operation, and should not be limited by the embodiments of the present disclosure. <FIG> and <FIG> illustrate an example in which sacrificial portions <NUM>-<NUM> are removed before the removal of insulating portions <NUM>-<NUM>. In some embodiments, insulating portions <NUM>-<NUM> are removed before the removal of sacrificial portions <NUM>-<NUM>. In some embodiments, insulating portions <NUM>-<NUM> and sacrificial portions <NUM>-<NUM> are removed together, e.g., using the same etching process.

As shown in <FIG>, sacrificial portions <NUM>-<NUM> are first removed. In some embodiments, a suitable isotropic etching process is performed to remove sacrificial portions <NUM>-<NUM>. The etchant may selectively etch sacrificial portions <NUM>-<NUM> over insulating portions <NUM>-<NUM>. In some embodiments, sacrificial portions <NUM>-<NUM> includes silicon nitride, and the isotropic etching process includes a wet etch which employs phosphoric acid as the etchant.

As shown in <FIG>, after sacrificial portions <NUM>-<NUM> are removed, another isotropic etching process can be performed to remove insulating portions <NUM>-<NUM>. Stack portion <NUM>-<NUM> may be removed to form second openings <NUM>. First openings <NUM> and second openings <NUM> aligned along the x-direction can be connected to one another to form initial slit structure <NUM>. The etchant of the other isotropic etching process may selectively etch insulating portions <NUM>-<NUM> over sacrificial portions <NUM>-<NUM>. In some embodiments, insulating portions <NUM>-<NUM> include silicon oxide, and the other isotropic etching process includes a wet etch process, which employs hydrofluoric acid as the etchant.

As shown in <FIG> and <FIG>, along the C-D direction (e.g., at the second location along the x-direction), the removal of sacrificial portions <NUM>-<NUM> and insulating portions <NUM>-<NUM> may respectively remove portions of sacrificial layers <NUM> and insulating layers <NUM> of block portions <NUM> in contact with first openings <NUM>. For example, as shown in <FIG>, the removal of sacrificial portions <NUM>-<NUM> may cause sacrificial layers <NUM> in contact with first openings <NUM> to undergo a recess etch, forming a recessed portion on sacrificial layers <NUM>. As shown in <FIG>, the removal of insulating portions <NUM>-<NUM> may cause insulating layers <NUM> in contact with first openings <NUM> to undergo a recess etch, forming a recessed portion on insulating layers <NUM>. The etched sacrificial layers <NUM> and insulating layers <NUM> (e.g., also etched dielectric cap layer <NUM> and etched buffer oxide layer <NUM>) may cause a width of first opening <NUM> (or initial slit structure <NUM>) to widen. In some embodiments, the portions of sacrificial layers <NUM> and insulating layers <NUM> removed by etching of sacrificial portions <NUM>-<NUM> and insulating portions <NUM>-<NUM> can be negligible.

As shown in <FIG> and <FIG>, along the A-B direction (e.g., at the first location along the x-direction), because of the coverage of connection portion <NUM>, the removal of dielectric cap portion <NUM>-<NUM>, sacrificial portions <NUM>-<NUM>, and insulating portions <NUM>-<NUM> may not be as complete at the top portion of initial slit structure <NUM> as a lower portion (e.g., a middle portion) of initial slit structure <NUM>. The incomplete removal of dielectric cap portion <NUM>-<NUM>, sacrificial portions <NUM>-<NUM>, and insulating portions <NUM>-<NUM> may cause a width D0 of initial slit structure <NUM> to be less than width D0 when no support structure <NUM> is used. For example, width D0 may gradually increase from the top portion to a lower portion of initial slit structure <NUM>. For example, width D0 may be the smallest at the top surface of initial slit structure <NUM>, and may increase to a lower portion to initial slit structure. The lower portion can be any position of initial slit structure <NUM> that is between the top surface of initial slit structure <NUM> and substrate <NUM>. In some embodiments, the middle portion of initial slit structure <NUM> is approximately the middle position of initial slit structure <NUM> along the z-direction. In some embodiments, the variation of D0 along the z-direction at the second location is negligible.

Referring back to <FIG>, after the formation of initial slit structures, the sacrificial layers are removed with a conductor material to form a plurality of conductor layers in each block portion (Operation <NUM>). A recessed portion is formed on each conductor layer along a sidewall of each initial slit structure, form at least one slit structure (Operation <NUM>). A source structure is formed in each slit structure (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures <NUM> and <NUM>.

As shown in <FIG>, sacrificial layers <NUM> in each block portion <NUM> can be removed through initial slit structure <NUM> to form a plurality of lateral recesses, each between a pair of adjacent insulating layers <NUM>. A suitable conductor material may be deposited to fill up the lateral recesses, forming a plurality of conductor layers (e.g., <NUM>, <NUM>, and <NUM>) in each block portions <NUM>. Control conductor layers <NUM> may intersect with semiconductor channels <NUM> and form a plurality of memory cells in each block portion <NUM>, which forms a memory block. In some embodiments, the lateral recess formed by the removal of the top sacrificial layer <NUM> in block portion <NUM> may be filled with the conductor material form a top conductor layer <NUM>, and the lateral recess formed by the removal of the bottom sacrificial layer <NUM> in block portion <NUM> may be filled with the conductor material to form a bottom conductor layer <NUM>. In some embodiments, lateral recesses formed by the removal of sacrificial layers <NUM> between the top and bottom sacrificial layers <NUM> may be filled with the conductor material to form a plurality of control conductor layers <NUM>.

A suitable isotropic etching process, e.g., wet etch, can be performed to remove sacrificial layers <NUM>, and form the plurality of lateral recesses. The conductor material may include one or more of tungsten, aluminum, copper, cobalt, silicides, and polysilicon. A suitable deposition process, such as CVD, PVD, ALD, and/or sputtering can be performed to deposit the conductor material into the lateral recesses to form conductor layers (e.g., <NUM>, <NUM>, and <NUM>).

As shown in <FIG>, a recess etch may be performed to selectively remove a portion of each conductor layer (e.g., <NUM>, <NUM>, and <NUM>) exposed by the sidewall of initial slit structure <NUM> to form a recessed portion on each conductor layer (e.g., <NUM>, <NUM>, and <NUM>). Accordingly, an offset can be formed between each conductor layer (e.g., <NUM>, <NUM>, and <NUM>) and adjacent insulating layers <NUM> along the z-direction. That is, a protruding portion may be formed on each insulating layer <NUM>. In some embodiments, a plurality of protruding portions (e.g., formed on insulating layers <NUM>) and a plurality of recessed portions (e.g., formed on conductor layers (e.g., <NUM>, <NUM>, and <NUM>)) can be formed interleaved with one another along the sidewall of initial slit structure <NUM>. A slit structure, exposing substrate <NUM>, can be formed. In some embodiments, the recessed portions may be formed on insulating layers <NUM>, and the protruding portions may be formed on conductor layers (e.g., <NUM>, <NUM>, and <NUM>). For example, a recess etch may be performed to selectively remove a portion of each insulating layer <NUM> exposed by the sidewall of initial slit structure <NUM> to form a recessed portion on each insulating layer <NUM>. The width of the slit structure along the x-direction can be determined based on with D0 of initial slit structure <NUM> and the amount of conductor layers (e.g., <NUM>, <NUM>, and <NUM>) and/or insulating layers <NUM> removed by the recess etching process. In some embodiments, the width of the slit structure may be equal to or greater than width D0 of initial slit structure <NUM>, and may be similar to or the same as width D0 of the subsequently formed source structure <NUM>. A suitable isotropic etching process, e.g., wet etch, may be performed to form the recessed portions and protruding portions.

An insulating structure <NUM> may be formed in slit structure and a source contact <NUM> may be formed in the respective insulating structure <NUM>, forming source structure <NUM>. In some embodiments, insulating structure <NUM> includes silicon oxide, and is deposited by one or more of CVD, PVD, ALD, and sputtering. A recess etch may be performed on insulating structure <NUM> to remove any excess material at the bottom of the slit structure to expose substrate <NUM>. In some embodiments, source contact <NUM> includes one or more of tungsten, aluminum, copper, cobalt, silicides, and polysilicon, and is formed by a suitable deposition process, e.g., one or more of CVD, PVD, ALD, and sputtering. Source contact <NUM> may be in contact and form a conductive connection with substrate <NUM>. Cross-sectional views of source structure <NUM> along the A-B direction (e.g., at the first location along the x-direction) and along the C-D direction (e.g., at the second location along the x-direction) may be referred to the description of <FIG>, and are not repeated herein.

Support structure <NUM> may be removed at a suitable stage of the fabrication process. In some embodiments, support structure <NUM> is performed after the formation of conductor layers (e.g., <NUM>, <NUM>, and <NUM>) and before the formation of source contact <NUM>. In some embodiments, support structure <NUM> is removed after the formation of source contacts <NUM>. The existence of support structure <NUM> may have little or no impact on the deposition of insulating structure <NUM> and source contact <NUM>. In some embodiments, support structure <NUM> is removed after the formation of source contacts <NUM> and provides support to the slit structure during the formation of initial slit structures <NUM> and source contacts <NUM>.

Claim 1:
A three-dimensional (3D) memory device (<NUM>), comprising:
a memory stack (<NUM>) over a substrate (<NUM>), the memory stack (<NUM>) comprising a plurality of interleaved conductor layers (<NUM>, <NUM>, <NUM>) and a plurality of insulating layers (<NUM>) extending laterally in the memory stack (<NUM>);
a plurality of channel structures (<NUM>) extending vertically through the memory stack (<NUM>) into the substrate (<NUM>), the plurality of channel structures (<NUM>) and the plurality of conductor layers (<NUM>, <NUM>, <NUM>) intersecting with one another and forming a plurality of memory cells;
a support structure (<NUM>) over the stack structure (<NUM>), having a plurality of support openings (<NUM>) and at least one connection portion (<NUM>), each between and in contact with adjacent support openings (<NUM>);
a slit structure extending vertically and laterally in the memory stack (<NUM>) below the support openings (<NUM>) and the at least one connection portion (<NUM>) and dividing the plurality of memory cells into at least one memory block, the slit structure comprising a plurality of protruding portions and a plurality of recessed portions arranged vertically along a sidewall of the slit structure, whereas the protruding portions are formed on insulating layers (<NUM>) and the recessed portions are formed on conductor layers (<NUM>, <NUM>, <NUM>); and
a source structure (<NUM>) in the slit structure, the source structure (<NUM>) comprising an insulating structure (<NUM>) in contact with the slit structure and a source contact (<NUM>) in the insulating structure (<NUM>) and in contact with the substrate (<NUM>),
wherein the top surface of the stack structure (<NUM>) includes a plurality of pits, wherein the support structure (<NUM>) fills the pits with the material of support structure (<NUM>), increasing the bonding between support structure (<NUM>) and stack structure (<NUM>) and improving the structural stability of the 3D memory device (<NUM>) during processing.