Patent Description:
Wireless communication devices and technologies are becoming ever more prevalent, as are communication devices that operate at millimeter-wave (mmW) frequencies. Wireless communication devices generally transmit and/or receive communication signals.

A communication signal is typically processed by a variety of different components and circuits. In some modern communication systems, a communication beam may be formed and steered in one or more directions. One type of beam steering system uses what is referred to as phased array, or phased array antenna system. A phased array may use a number of different elements and antennas where each element may process a transmit and/or receive signal that is offset in phase by some amount, leading to different elements of a phased array system processing slightly phase-shifted versions of a transmit and/or a receive signal. A phased array system may produce narrow, steerable, high power communication beams. A phased array antenna system may also form part of a massive multiple-input, multiple-output (MIMO) system. A transmitter in a phased array communication system may have a number of transmit paths and may have a number of amplifiers, including a number of power amplifiers. A variety of factors influence the operation of a power amplifier, including, for example, input signal strength, input impedance, output impedance, load impedance, and other factors. These factors may influence the longevity and reliability of a power amplifier. It is desirable to have a way to ensure that each power amplifier operates within an acceptable operating range to maximize longevity and reliability.

Attention is drawn to <CIT> Al describing an apparatus comprising an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.

Further embodiments of the invention are described in the dependent claims.

Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein.

One aspect of the disclosure provides a system for power amplifier control including a processor, a memory in communication with the processor, wherein the processor and the memory are configured to simultaneously provide input signal strength of each of a plurality of power amplifiers in a millimeter wave (mmW) phased array system, determine an average input signal strength of the plurality of power amplifiers based on the provided input signal strengths using an analog-to-digital converter (ADC), determine a voltage headroom for the plurality of power amplifiers based on the determined average input signal strength, estimate a power backoff value based on the voltage headroom, and determine a gain control value based on the estimated power backoff value.

Another aspect of the disclosure provides a method for power control including simultaneously providing input signal strength of each of a plurality of power amplifiers in a millimeter wave (mmW) phased array system, determining an average input signal strength of the plurality of power amplifiers based on the provided input signal strengths, determining a voltage headroom based on the determined average input signal strength, estimating a power backoff value based on the determined voltage headroom, and determining a gain control value to achieve the estimated power backoff value.

Another aspect of the disclosure provides a device including means for simultaneously providing input signal strength of each of a plurality of power amplifiers in a millimeter wave (mmW) phased array system, means for determining an average input signal strength of the plurality of power amplifiers based on the provided input signal strengths, means for determining a voltage headroom based on the determined average input signal strength, means for estimating a power backoff value based on the determined voltage headroom, and means for determining a gain control value to achieve the estimated power backoff value.

Another aspect of the disclosure provides a power control system for a millimeter wave (mmW) communication system including a plurality of transmission paths, each transmission path having a power amplifier, and an input power detector, an analog-to-digital converter (ADC) coupled to each input power detector, the ADC configured to generate a single digital value for a plurality of input voltage signals corresponding to an input voltage of each power amplifier within a symbol, a variable gain amplifier (VGA) coupled to the plurality of transmission paths, and a processor configured to cause a control signal to be applied to the variable gain amplifier (VGA) responsive to the single digital value.

In the figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as "102a" or "102b", the letter character designations may differentiate two like parts or elements present in the same figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.

In a communication system that uses a phased array antenna system having phased array elements, each phased array element typically includes a power amplifier. Factors that may influence the operation of each power amplifier include, for example, input signal strength, input impedance, output impedance, load impedance, and other factors. It is desirable to have a way to ensure that each power amplifier operates within an acceptable operating range to maximize longevity and reliability.

Each power amplifier may include an input power detector and an output power detector. An input power detector may be referred to as an RDET (reliability input power detector), and an output power detector may be referred to as a PDET (power detector, or output power detector).

An RDET may be part of an input protection circuit to prevent over-driving the power amplifier, which can degrade performance and long term reliability. An RDET detects the voltage swing, or voltage level, at the input of the power amplifier. Information about individual power amplifier input voltage swings in a phased array antenna system is important to determine if a certain power amplifier has crossed an input level threshold. The input level of each power amplifier in a phased array system may differ due to the use of a technique referred to as mismatch calibration, which aligns power amplifier output, but can lead to differences in the input level provided to each power amplifier. Differences in power amplifier input power could also result from the use of digital pre-distortion (DPD) calibration based on different antenna loading per phased array element.

Architectures for power estimation that rely on simultaneous summing of signals from multiple elements help in improving error accuracy, especially for narrow resource block (RB) signals, and also reduce the overall time of measurement, both of which are very important in mission mode. However, known methods do not provide any information for individual power amplifiers or power amplifier elements in real time. For example, a prior method for determining power amplifier input power in a phased array system having eight (<NUM>) elements reads the output of one RDET at a time for a total of eight (<NUM>) RDET outputs in each symbol period. However, given the short duration of a communication symbol, there is little time to accurately obtain input power measurements for eight (<NUM>) power amplifiers, leading to as much as a 2dB variation in input power for narrow RB waveforms using this prior technique.

Therefore, it would be desirable to have a way of measuring power amplifier input power in a phased array antenna system that accurately captures values for multiple power amplifiers in a short period of time.

In an exemplary embodiment, a system and method for power amplifier input control includes a calibration system and method that captures an average input power across multiple power amplifiers in a millimeter wave (mmW) phased array system.

In an exemplary embodiment, a system and method for power amplifier input control includes a real time power control system that uses the average input power across multiple power amplifiers to develop a power control system for the power amplifiers in the phased array system.

<FIG> is a diagram showing a wireless device <NUM> communicating with a wireless communication system <NUM>. The wireless communication system <NUM> may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, a <NUM> NR (new radio) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, <FIG> shows wireless communication system <NUM> including two base stations <NUM> and <NUM> and one system controller <NUM>. In general, a wireless communication system may include any number of base stations and any set of network entities.

The wireless device <NUM> may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device <NUM> may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, an automobile, a device configured to connect to one or more other devices (for example through the internet of things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device <NUM> may communicate with wireless communication system <NUM>. Wireless device <NUM> may also receive signals from broadcast stations (e.g., a broadcast station <NUM>) and/or signals from satellites (e.g., a satellite <NUM> in one or more global navigation satellite systems (GNSS)), etc). Wireless device <NUM> may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, <NUM>, <NUM>, etc..

Wireless device <NUM> may support carrier aggregation, for example as described in one or more LTE or <NUM> standards. In some embodiments, a single stream of data is transmitted over multiple carriers using carrier aggregation, for example as opposed to separate carriers being used for respective data streams. Wireless device <NUM> may be able to operate in a variety of communication bands including, for example, those communication bands used by LTE, WiFi, <NUM> or other communication bands, over a wide range of frequencies. Wireless device <NUM> may also be capable of communicating directly with other wireless devices without communicating through a network.

In general, carrier aggregation (CA) may be categorized into two types - intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.

<FIG> is a block diagram showing a wireless device <NUM> in which exemplary techniques of the present disclosure may be implemented. The wireless device <NUM> may, for example, be an embodiment of the wireless device <NUM> illustrated in <FIG>.

<FIG> shows an example of a transceiver <NUM> having a transmitter <NUM> and a receiver <NUM>. In general, the conditioning of the signals in the transmitter <NUM> and the receiver <NUM> may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. These circuit blocks may be arranged differently from the configuration shown in <FIG>. Furthermore, other circuit blocks not shown in <FIG> may also be used to condition the signals in the transmitter <NUM> and receiver <NUM>. Unless otherwise noted, any signal in <FIG>, or any other figure in the drawings, may be either single-ended or differential. Some circuit blocks in <FIG> may also be omitted.

In the example shown in <FIG>, wireless device <NUM> generally comprises the transceiver <NUM> and a data processor <NUM>. The data processor <NUM> may include a processor <NUM> operatively coupled to a memory <NUM>. The memory <NUM> may be configured to store data and program codes shown generally using reference numeral <NUM>, and may generally comprise analog and/or digital processing components. The processor <NUM> and the memory <NUM> may cooperate to control, configure, program, or otherwise fully or partially control some or all of the operation of the embodiments of the system and method for power amplifier input control described herein.

The transceiver <NUM> includes a transmitter <NUM> and a receiver <NUM> that support bidirectional communication. In general, wireless device <NUM> may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver <NUM> may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc..

A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown in <FIG>, transmitter <NUM> and receiver <NUM> are implemented with the direct-conversion architecture.

In the transmit path, the data processor <NUM> processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter <NUM>. In an exemplary embodiment, the data processor <NUM> includes digital-to-analog-converters (DAC's) 214a and 214b for converting digital signals generated by the data processor <NUM> into the I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs 214a and 214b are included in the transceiver <NUM> and the data processor <NUM> provides data (e.g., for I and Q) to the transceiver <NUM> digitally.

Within the transmitter <NUM>, baseband (e.g., lowpass) filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from baseband filters 232a and 232b, respectively, and provide I and Q baseband signals. An upconverter <NUM> having upconversion mixers 241a and 241b upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator <NUM> and provides an upconverted signal. A filter <NUM> filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) <NUM> amplifies the signal from filter <NUM> to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal may be routed through a duplexer or switch <NUM> and transmitted via an antenna <NUM>. While examples discussed herein utilize I and Q signals, those of skill in the art will understand that components of the transceiver may be configured to utilize polar modulation.

In the receive path, antenna <NUM> receives communication signals and provides a received RF signal, which may be routed through duplexer or switch <NUM> and provided to a low noise amplifier (LNA) <NUM>. The duplexer <NUM> is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA <NUM> and filtered by a filter <NUM> to obtain a desired RF input signal. Downconversion mixers 261a and 261b in a downconverter <NUM> mix the output of filter <NUM> with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator <NUM> to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by baseband (e.g., lowpass) filters 264a and 264b to obtain I and Q analog input signals, which are provided to data processor <NUM>. In the exemplary embodiment shown, the data processor <NUM> includes analog-to-digital-converters (ADC's) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor <NUM>. In some embodiments, the ADCs 216a and 216b are included in the transceiver <NUM> and provide data to the data processor <NUM> digitally.

In <FIG>, TX LO signal generator <NUM> generates the I and Q TX LO signals used for frequency upconversion, while RX LO signal generator <NUM> generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase locked loop (PLL) <NUM> receives timing information from data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator <NUM>. Similarly, a PLL <NUM> receives timing information from data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator <NUM>.

Wireless device <NUM> may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. Those of skill in the art will understand, however, that aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.

Certain components of the transceiver <NUM> are functionally illustrated in <FIG>, and the configuration illustrated therein may or may not be representative of a physical device configuration in certain implementations. For example, as described above, transceiver <NUM> may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver <NUM> is implemented on a substrate or board such as a printed circuit board (PCB) having various modules, chips, and/or components. For example, the power amplifier <NUM>, the filter <NUM>, and the duplexer <NUM> may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver <NUM> may be implemented in a single transceiver chip.

The power amplifier <NUM> may comprise one or more stages comprising, for example, driver stages, power amplifier stages, or other components, that can be configured to amplify a communication signal on one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier <NUM> can be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and can be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

In an exemplary embodiment in a super-heterodyne architecture, the PA <NUM> and LNA <NUM> (and filter <NUM> and filter <NUM> in some examples) may be implemented separately from other components in the transmitter <NUM> and receiver <NUM>, for example on a millimeter wave integrated circuit. An example super-heterodyne architecture is illustrated in <FIG>.

<FIG> is a block diagram showing a wireless device in which exemplary techniques of the present disclosure may be implemented. Certain components, for example which may be indicated by identical reference numerals, of the wireless device 200a in <FIG> may be configured similarly to those in the wireless device <NUM> shown in <FIG> and the description of identically numbered items in <FIG> will not be repeated.

The wireless device 200a is an example of a heterodyne (or superheterodyne) architecture in which the upconverter <NUM> and the downconverter <NUM> are configured to process a communication signal between baseband and an intermediate frequency (IF). For example, the upconverter <NUM> may be configured to provide an IF signal to an upconverter <NUM>. In an exemplary embodiment, the upconverter <NUM> may comprise summing function <NUM> and upconversion mixer <NUM>. The summing function <NUM> combines the I and the Q outputs of the upconverter <NUM> and provides a non-quadrature signal to the mixer <NUM>. The non-quadrature signal may be single ended or differential. The mixer <NUM> is configured to receive the IF signal from the upconverter <NUM> and TX RF LO signals from a TX RF LO signal generator <NUM>, and provide an upconverted RF signal to phase shift circuitry <NUM>. While PLL <NUM> is illustrated in <FIG> as being shared by the signal generators <NUM>, <NUM>, a respective PLL for each signal generator may be implemented.

In an exemplary embodiment, components in the phase shift circuitry <NUM> may comprise one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor <NUM> over connection <NUM> and operate the adjustable or variable phased array elements based on the received control signals.

In an exemplary embodiment, the phase shift circuitry <NUM> comprises phase shifters <NUM> and phased array elements <NUM>. Although three phase shifters <NUM> and three phased array elements <NUM> are shown for ease of illustration, the phase shift circuitry <NUM> may comprise more or fewer phase shifters <NUM> and phased array elements <NUM>.

Each phase shifter <NUM> may be configured to receive the RF transmit signal from the upconverter <NUM>, alter the phase by an amount, and provide the RF signal to a respective phased array element <NUM>. Each phased array element <NUM> may comprise transmit and receive circuitry including one or more filters, amplifiers, driver amplifiers, and/or power amplifiers. In some embodiments, the phase shifters <NUM> may be incorporated within respective phased array elements <NUM>.

The output of the phase shift circuitry <NUM> is provided to an antenna array <NUM>. In an exemplary embodiment, the antenna array <NUM> comprises a number of antennas that typically correspond to the number of phase shifters <NUM> and phased array elements <NUM>, for example such that each antenna element is coupled to a respective phased array element <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> and the antenna array <NUM> may be referred to as a phased array.

In a receive direction, an output of the phase shift circuitry <NUM> is provided to a downconverter <NUM>. In an exemplary embodiment, the downconverter <NUM> may comprise an I/Q generation function <NUM> and a downconversion mixer <NUM>. In an exemplary embodiment, the mixer <NUM> downconverts the receive RF signal provided by the phase shift circuitry <NUM> to an IF signal according to RX RF LO signals provided by an RX RF LO signal generator <NUM>. The I/Q generation function <NUM> receives the IF signal from the mixer <NUM> and generates I and Q signals for the downconverter <NUM>, which downconverts the IF signals to baseband, as described above. While PLL <NUM> is illustrated in <FIG> as being shared by the signal generators <NUM>, <NUM>, a respective PLL for each signal generator may be implemented.

In some embodiments, the upconverter <NUM>, downconverter <NUM>, and the phase shift circuitry <NUM> are implemented on a common IC. In some embodiments, the summing function <NUM> and the I/Q generation function <NUM> are implemented separate from the mixers <NUM> and <NUM> such that the mixers <NUM>, <NUM> and the phase shift circuitry <NUM> are implemented on the common IC, but the summing function <NUM> and I/Q generation function <NUM> are not (e.g., the summing function <NUM> and I/Q generation function <NUM> are implemented in another IC coupled to the IC having the mixers <NUM>, <NUM>). In some embodiments, the LO signal generators <NUM>, <NUM> are included in the common IC. In some embodiments in which phase shift circuitry is implemented on a common IC with <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>, the common IC and the antenna array <NUM> are included in a module, which may be coupled to other components of the transceiver <NUM> via a connector. In some embodiments, the phase shift circuitry <NUM>, for example, a chip on which the phase shift circuitry <NUM> is implemented, is coupled to the antenna array <NUM> by an interconnect. For example, components of the antenna array <NUM> may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuitry <NUM> via a flexible printed circuit.

In some embodiments, both the architecture illustrated in <FIG> and the architecture illustrated in <FIG> are implemented in the same device. For example, a wireless device <NUM> or <NUM> may be configured to communicate with signals having a frequency below about <NUM> using the architecture illustrated in <FIG> and to communicate with signals having a frequency above about <NUM> using the architecture illustrated in <FIG>. In devices in which both architectures are implemented, one or more components of <FIG> and <FIG> that are identically numbered may be shared between the two architectures. For example, both signals that have been downconverted directly to baseband from RF and signals that have been downconverted from RF to baseband via an IF stage may be filtered by the same baseband filter <NUM>. In other embodiments, a first version of the filter <NUM> is included in the portion of the device which implements the architecture of <FIG> and a second version of the filter <NUM> is included in the portion of the device which implements the architecture of <FIG>. While certain example frequencies are described herein, other implementations are possible. For example, signals having a frequency above about <NUM> (e.g., having a mmW frequency) may be transmitted and/or received using a direct conversion architecture. In such embodiments, for example, a phased array may be implemented in the direct conversion architecture.

<FIG> is a block diagram <NUM> showing in greater detail an embodiment of some of the components of <FIG>. In an exemplary embodiment, the upconversion mixer <NUM> provides an RF transmit signal to the phase shift circuitry <NUM> and the downconversion mixer <NUM> receives an RF receive signal from the phase shift circuitry <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> comprises an RF variable gain amplifier (VGA) <NUM>, a splitter <NUM>, a combiner <NUM>, the phase shifters <NUM> and the phased array elements <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> may be implemented on a millimeter-wave integrated circuit (mmWIC). In some such embodiments, the upconverter <NUM> and/or the downconverter <NUM> (or just the mixers <NUM>, <NUM>) are also implemented on the mmWIC. In an exemplary embodiment, the RF VGA <NUM> may comprise a TX VGA <NUM> and an RX VGA <NUM>. In some embodiments, the TX VGA <NUM> and the RX VGA <NUM> may be implemented independently. In other embodiments, the RF VGA <NUM> is bidirectional. In an exemplary embodiment, the splitter <NUM> and the combiner <NUM> may be an example of, or may comprise a power distribution network and a power combining network. In some embodiments, the splitter <NUM> and the combiner <NUM> may be implemented as a single component or as a separate signal splitter and signal combiner as shown. The phase shifters <NUM> may be implemented as separate transmit (TX) and receive (RX) phase shifters, or may be implemented as TX/RX bidirectional phase shifters. The phase shifters <NUM> may be coupled to respective phased array elements <NUM>. In an exemplary embodiment, each phased array element may comprise a power amplifier (PA) <NUM> and a low noise amplifier (LNA) <NUM>. Each PA <NUM> may comprise one or more amplifiers or amplifier stages including, for example, one or more driver amplifiers and one or more power amplifiers. Each LNA <NUM> may comprise one or more amplifiers or amplifier stages. In an exemplary embodiment, a phase shifter <NUM> may be coupled to a PA <NUM> and to an LNA <NUM>. Each respective phased array element <NUM> having a PA <NUM> and an LNA <NUM> is coupled to a respective antenna element in the antenna array <NUM>. In an exemplary embodiment, phase shifters <NUM> and the phased array elements <NUM> receive control signals from the data processor <NUM> over connection <NUM>. The exemplary embodiment shown in <FIG> comprises a 1x4 array having four TX phase shifters <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>; and four RX phase shifters <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n; four phased array elements <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n, and four antennas <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n. However, a 1x4 phased array is shown for example only, and other configurations, such as 1x2, 1x6, 1x8, 2x3, 2x4, or other configurations are possible. Further, each PA <NUM> and LNA <NUM> of a phased array element <NUM> may share a common signal pin to reduce circuit area. However, in other embodiments, each PA <NUM> and LNA <NUM> of a phased array element <NUM> can have an independent pin and rely on module routing or the respective antenna element to couple Tx and Rx together.

Examples illustrated with respect to <FIG> and <FIG> implement phase shifting (e.g., using phase shifters <NUM>) in a signal path of the wireless device 200a. In other examples, the phase shifters <NUM> are omitted, and a phase of a signal may be adjusted by varying a phase at the mixers <NUM>, <NUM>. In some examples, the LO signal generators <NUM>, <NUM> are configured to provide oscillating signals having varied phase in order to produce TX and/or RX signals having different phases. In some such examples, more than one mixer is implemented for the TX path and/or the RX path in the circuitry <NUM>.

<FIG> is a block diagram of a portion of a phased array circuit <NUM> in accordance with an exemplary embodiment of the disclosure. In an exemplary embodiment, the phased array circuit <NUM> is an example of a phased array transmit system having four (<NUM>) transmit paths <NUM>, <NUM>, <NUM> and <NUM>. The phased array circuit <NUM> may also be referred to as a phased array. Four transmit paths are shown for example only, as more or fewer transmit paths may be implemented in a phased array system. In an exemplary embodiment, the transmit paths <NUM>, <NUM>, <NUM> and <NUM> may be configured to receive respective outputs of the phase shifters <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of <FIG>, or configured to receive signals that have varied phases produced using other means.

In an exemplary embodiment, the transmit path <NUM> may comprise one or more driver amplifiers, shown as a single driver amplifier <NUM> in this example, a power amplifier <NUM> and an antenna <NUM>. The transmit path <NUM> may also comprise an input power detector (referred to as a reliability input power detector RDET) <NUM> and an output power detector, PDET <NUM>. The output power detector, PDET <NUM>, may be coupled to the connection <NUM> between the power amplifier <NUM> and the antenna <NUM> using a (power) coupler <NUM>. The input power detector, RDET <NUM>, may be coupled to the connection <NUM> between the driver amplifier <NUM> and the power amplifier <NUM> using a (power) coupler <NUM>. In an exemplary embodiment, the power amplifier <NUM> may be an example of one of the power amplifiers <NUM> in <FIG>. In an exemplary embodiment, the input power detectors, RDETs <NUM>, <NUM>, <NUM> and <NUM>, may be configured to measure an input voltage swing at the input to respective power amplifiers <NUM>, <NUM>, <NUM> and <NUM>. As used herein, the term "input power" may also be referred to as "input voltage swing" or "voltage swing.

In an exemplary embodiment, the transmit path <NUM> may comprise one or more driver amplifiers, shown as a single driver amplifier <NUM> in this example, a power amplifier <NUM> and an antenna <NUM>. The transmit path <NUM> may also comprise an input power detector, RDET <NUM> and an output power detector, PDET <NUM>. The output power detector, PDET <NUM>, may be coupled to the connection <NUM> between the power amplifier <NUM> and the antenna <NUM> using a (power) coupler <NUM>. The input power detector, RDET <NUM>, may be coupled to the connection <NUM> between the driver amplifier <NUM> and the power amplifier <NUM> using a (power) coupler <NUM>. In an exemplary embodiment, the power amplifier <NUM> may be an example of one of the power amplifiers <NUM> in <FIG>.

In an exemplary embodiment, each driver amplifier <NUM>, <NUM>, <NUM> and <NUM> may be coupled over connection <NUM> to the data processor <NUM> (<FIG>), from which respective control signals may be applied to the driver amplifiers <NUM>, <NUM>, <NUM> and <NUM>. In an exemplary embodiment, each RDET <NUM>, <NUM>, <NUM> and <NUM> and each PDET <NUM>, <NUM>, <NUM> and <NUM> may be coupled over a connection <NUM> to an analog-to-digital converter (ADC) <NUM>. The ADC <NUM> may be coupled over connection <NUM> to the data processor <NUM> (<FIG>). In an exemplary embodiment, the ADC <NUM> may be located on the same circuit, chip or die as the driver amplifiers, power amplifiers, input power detectors and/or output power detectors. Alternatively, the ADC <NUM> may be located on circuitry other than the circuitry on which the driver amplifiers, power amplifiers, input power detectors and/or output power detectors are located. Further, separate ADCs may be implemented for one or more of the transmit paths and/or for one or more of the RDET(s) and PDET(s) instead of having one ADC coupled to all of the RDETs and PDETs. In an exemplary embodiment, the ADC <NUM> may receive power measurements from the input power detectors, RDETs <NUM>, <NUM>, <NUM> and <NUM>, and may receive power measurements from the output power detectors, PDETs <NUM>, <NUM>, <NUM> and <NUM> over connection <NUM>. In an exemplary embodiment, the connection <NUM> may comprise a communication bus configured to transport multiple signals simultaneously. In an exemplary embodiment, the measurements from the input power detectors and output power detectors may be provided to the ADC <NUM>. In an exemplary embodiment, the ADC <NUM> may develop one or more signals representative of the power detected by the input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM>, and may develop one or more signals representative of the power detected by the output power detectors, PDETs, <NUM>, <NUM>, <NUM> and <NUM>. The ADC <NUM> may be in communication with the data processor <NUM> (<FIG>) and the data processor <NUM> may be configured to perform calculations on the power measurement signals developed by the ADC <NUM>. Similarly, the data processor <NUM> may control the operation of each of the driver amplifiers and indirectly, the power amplifiers, in some embodiments, responsive to the power detected by the input power detectors and the output power detectors. In other examples, the data processor <NUM> may directly control operation of one or more of the power amplifiers.

In an exemplary embodiment, the data processor <NUM> may develop control signals for the driver amplifiers <NUM>, <NUM>, <NUM> and <NUM> to provide power control. In an exemplary embodiment, there are two controls: one control is a coarse control referred to as automatic gain control, (AGC), and the other control is a fine control. The fine control may be used to perform power amplifier power output mismatch calibration as described herein and in an exemplary embodiment, can be done in the driver amplifiers <NUM>, <NUM>, <NUM> and <NUM> to indirectly control the power provided by the power amplifiers <NUM>, <NUM>, <NUM> and <NUM>. The coarse power control (AGC) may be done in a VGA, such as in the RF VGA <NUM> of <FIG> because in this example the RF VGA <NUM> is common to all transmit paths <NUM>, <NUM>, <NUM> and <NUM>. The coarse control (AGC) may also be used for power backoff as will be described below.

In an exemplary embodiment, each antenna <NUM>, <NUM>, <NUM> and <NUM> may be associated with a communication port. For example, antenna <NUM> may be associated with a first communication port (port <NUM>), antenna <NUM> may be associated with a second communication port (port <NUM>), antenna <NUM> may be associated with a third communication port (port <NUM>), and antenna <NUM> may be associated with a fourth communication port (port <NUM>).

<FIG> is a flow chart <NUM> describing an example of the operation of a method for input power detection and power amplifier output calibration. The blocks in the method <NUM> can be performed in or out of the order shown, and in some embodiments, can be performed at least in part in parallel. The description of the method <NUM> will also refer to an exemplary calibration chart <NUM> shown in <FIG>. The operations described with respect to chart <NUM> may be performed during a factory calibration of a device (e.g., the device 200a), or during a calibration after the device is deployed to a user. In some examples, portions of the operations described with respect to flow chart <NUM> are performed in a factory and portions are performed after the device is deployed to the user. The operations may be performed once (e.g., at the factory), or multiple times (e.g., periodically so as to account for changing behavior over time and/or varying conditions).

In block <NUM>, the output power of each power amplifier in a phased array system is set to a nominal value, for example using an AGC value, and the power output of each power amplifier is measured and stored. For example, an output power of each power amplifier <NUM>, <NUM>, <NUM> and <NUM> may be set using a nominal AGC index value of <NUM> as shown in the exemplary calibration chart <NUM> in the column titled "AGC Index" and the power output measured by respective output power detectors PDETs, <NUM>, <NUM>, <NUM> and <NUM>, as shown in the exemplary calibration chart <NUM> in the column titled "PDET". The AGC index value is a value that corresponds to an approximate desired power output. The power measurement value for each power amplifier <NUM>, <NUM>, <NUM> and <NUM> may be stored in a memory <NUM> associated with the data processor <NUM> (<FIG>). In some examples, output power of each power amplifier <NUM>, <NUM>, <NUM>, and <NUM> is measured individually, for example one after another.

In block <NUM>, a gain mismatch value associated with the power amplifiers in the phased array is determined. For example, with reference to the rows <NUM> in the column labeled "PDET" in the calibration chart <NUM> in <FIG>, the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>) is 14dBm, the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>) is <NUM>. 5dBm, the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>) is 12dBm, and the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>) is 13dBm. In this example, the gain mismatch from the lowest power output to the highest power output is 2dB.

In block <NUM>, fine gain correction is applied among the power amplifiers to align the output power of each power amplifier to a particular value, for example the lowest measured value. For example, referring to the column labeled "PDET" in the calibration chart <NUM> in <FIG>, it is determined that the lowest measured output power value was obtained from communication port <NUM> (power amplifier <NUM>) at 12dBm. Therefore, the example fine gain correction applied to the driver amplifiers <NUM>, <NUM>, <NUM> and <NUM> in the phased array aligns the output of each power amplifier to an output of approximately 12dBm, which is the measured power output of the power amplifier <NUM> (communication port <NUM>). For example, referring to the column labeled "Gain Adjustment" in the calibration chart <NUM> in <FIG>, the driver amplifier <NUM> driving the power amplifier <NUM> associated with communication port <NUM> has its power reduced by 2dB (-2dB), so that the output of the power amplifier <NUM> is 12dBm. Similarly, the driver amplifier <NUM> driving the power amplifier <NUM> associated with communication port <NUM> has its power reduced by <NUM>. 5dB (-<NUM>. 5dB), so that the output of the power amplifier <NUM> is 12dBm, and the driver amplifier <NUM> driving the power amplifier <NUM> associated with communication port <NUM> has its power reduced by 1dB (-1dB), so that the output of the power amplifier <NUM> is 12dBm. In this manner, the power amplifiers associated with communication ports <NUM>, <NUM>, <NUM> and <NUM> are each controlled to have a nominal power output of 12dBm.

In block <NUM>, the power amplifiers are controlled so as to provide the nominal (desired) output power, for example using the AGC value. In this example, the desired nominal output power is 14dBm. For example, referring to the column labeled "AGC Index" in the calibration chart <NUM> in <FIG>, it is shown that the AGC index value provided to each driver amplifier <NUM>, <NUM>, <NUM> and <NUM> is set to <NUM>, such that the power output of each power amplifier <NUM>, <NUM>, <NUM> and <NUM> is approximately a nominal 14dBm. This is shown in the rows <NUM> and in the column labeled "PDET" in the calibration chart <NUM> in <FIG>, whereby the power output of each power amplifier <NUM>, <NUM>, <NUM> and <NUM> when the AGC Index is <NUM> is the nominal output power of 14dBm. The AGC index value may be adjusted while the gain adjustment values determined in block <NUM> are applied, as shown in rows <NUM>. In this way, the output power of all power amplifiers may be set to be approximately equal (and to be approximately a desired output power).

In block <NUM>, the input power of each power amplifier is measured. For example, respective input power detectors, RDET <NUM>, <NUM>, <NUM> and <NUM> serially or simultaneously measure the input power of the input signal provided to each power amplifier <NUM>, <NUM>, <NUM> and <NUM>. For example, referring to the rows <NUM> and the column labeled "RDET" in the calibration chart <NUM> in <FIG>, the input power at communication port <NUM> (power amplifier <NUM>) is 190mV, the input power at communication port <NUM> (power amplifier <NUM>) is 193mV, the input power at communication port <NUM> (power amplifier <NUM>) is 198mV, and the input power at communication port <NUM> (power amplifier <NUM>) is 195mV. From these input power measurements, it can be determined that the average input power (RDET_avg_cal) is 194mV, and the highest measured input power (RDET_max_cal) is 198mV.

In block <NUM>, the input power measurements and/or values derived therefrom are stored. For example, the average input power, RDET_avg_cal (of 194mV in this example), and the highest measured input power, RDET_max_cal (of 198mV in this example) may be stored in (a non-volatile (NV) portion of) the memory <NUM> (<FIG>).

In block <NUM>, the input power variation, RDET_variation, is determined. In an exemplary embodiment, the input power variation, RDET_variation may be determined according to:
RDET_variation = RDET_max_cal - RDET_avg_cal.

In an exemplary embodiment, using the RDET values from the rows <NUM> and the column labeled "RDET" the value for RDET_variation may be determined to be RDET_max_cal, (198mV) minus RDET_avg_cal (194mV), resulting in an RDET_variation (ΔRDET_cal) of 4mV.

In block <NUM>, the value of RDET_variation (ΔRDET_cal=4mV in this example) may be stored in (a non-volatile (NV) portion of) the memory <NUM> (<FIG>).

<FIG> is a flow chart describing an example of the operation of a method <NUM> for input power detection and power amplifier output control. The blocks in the method <NUM> can be performed in or out of the order shown, and in some embodiments, can be performed at least in part in parallel. The description of the method <NUM> will also refer to the exemplary calibration chart <NUM> shown in <FIG>; to a graph <NUM> shown in <FIG> that shows input power (vertical axis in mV) measured at each communication port (horizontal axis) (power amplifier); to an operation chart <NUM> shown in <FIG>; and to a chart <NUM> shown in <FIG> that shows power amplifier backoff at different temperatures. In some examples, the operations described with respect to the method <NUM> are performed during operation (e.g., mission mode) of a device (e.g., the device 200a). For example, power measurement and averaging operations described with respect to at least blocks <NUM> and <NUM> may be performed within a single symbol period during transmission of a wireless communication. In some examples, all of the operations described with respect to the method <NUM> are performed during a single symbol period.

In block <NUM>, input powers (e.g., for all power amplifiers being adjusted, for example for all power amplifiers in the phased array which are transmitting or scheduled to transmit) are simultaneously provided to the ADC <NUM>. To facilitate such measurement, an input power detection event, also referred to as an RDET event, may be scheduled. For example, the input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM> may be configured to periodically determine input power for the respective power amplifiers <NUM>, <NUM>, <NUM> and <NUM> according to a pre-determined schedule. For example, the input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM> may be configured to provide the input power for the respective power amplifiers <NUM>, <NUM>, <NUM> and <NUM> to the ADC <NUM> every <NUM>, or another interval. In some examples, readback may be scheduled in a subsequent slot. In an exemplary embodiment, each RDET <NUM>, <NUM>, <NUM> and <NUM> may generate an analog voltage (for example, in mV) that represents respective input power of each power amplifier <NUM>, <NUM>, <NUM> and <NUM>. This may occur two times (2X) for each power amplifier: one for each antenna polarization (e.g., vertical polarization, Vpol, and horizontal polarization, Hpol, or slant polarizations). The analog input voltages may be simultaneously provided to the analog-to-digital converter (ADC) <NUM> of <FIG> and may be averaged by the ADC <NUM>. Simultaneously may refer to concurrent operation. For example, all of the RDETs, <NUM>, <NUM>, <NUM> and <NUM> may be operating approximately concurrently and may be providing a signal to the ADC <NUM> in overlapping times. Simultaneously may also refer to operation that is within a time required for the ADC <NUM> to compute an average. For example, even if several signals are not received at the ADC <NUM> at exactly the same time, if they are all available to the ADC <NUM> while the ADC is computing an average the signals may be considered to have been provided simultaneously. In some examples, simultaneously may refer to operation during a symbol or a shorter amount of time within the symbol.

In block <NUM>, the analog input voltages provided to the ADC <NUM> are averaged. In an exemplary embodiment, the ADC <NUM> may develop a digital word that represents the average of the analog input voltages for the power amplifiers for each antenna polarization. In an exemplary embodiment, the ADC <NUM> generates two digital words representing the average power for the four exemplary power amplifiers <NUM>, <NUM>, <NUM> and <NUM> in this example, and for each of two antenna polarizations. In this example, the averaged RDET input power measurements taken from each of the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> during operation (mission mode) will be referred to as RDET_avg_op to differentiate these mission mode measurements from the calibration mode averaged RDET measurements RDET_avg_cal. In an exemplary embodiment, input voltages measured and averaged during operation (blocks <NUM> and <NUM> of <FIG>) may be the same or different than the input voltages measured during calibration (block <NUM> of <FIG>). Therefore, the average of the input voltages generated in block <NUM> (RDET_avg_op) may be the same or different than the average of the input voltages described in block <NUM> (RDET_avg_cal). For example, during the calibration mode described in <FIG>, the RDET measurements may be taken from individual power amplifiers and averaged by software in the data processor <NUM> (<FIG>) resulting in the average RDET_avg_cal. During the mission mode described in <FIG>, the RDET measurement, RDET_avg_op, is an average of the input voltages from all the power amplifiers that happen to be active during operating conditions, which may include differences due to, for example, temperature variation. The average power amplifier input power may be referred to as RDET_avg_op in block <NUM> and may be determined by the ADC <NUM> (<FIG>) in hardware, and may differ from RDET_avg_cal (block <NUM>). In block <NUM>, only the average, RDET_avg_op, input power of the active power amplifiers may be available, for example when input powers for multiple power amplifiers are provided at the same time. However, RDET_avg_cal and RDET_avg_op may be the same (or substantially the same) when measured under the same conditions (temperature, etc.).

In block <NUM>, a variable referred to as "DISTANCE" is computed by the data processor <NUM> (<FIG>). In an exemplary embodiment, the variable DISTANCE represents a voltage level comprising the amount of voltage headroom between a power amplifier threshold voltage, THRESHOLD, and the sum of RDET_variation and RDET_avg_op, as shown in the below formula. Thus, the THRESHOLD may be compared to the sum of RDET_variation and RDET_avg_op (and in some examples, a headroom may not explicitly be calculated or determined; in some such examples, it may only be determined whether the sum of RDET_variation and RDET_avg_op is greater than the THRESHOLD).

In the example shown in <FIG>, referring to the rows <NUM> and the columns labeled "AGC Index" and "PDET (dBm)", of the operation chart <NUM>, the AGC index is raised to <NUM> and the output power is nominally increased to 15dBm over the calibration example shown in <FIG>. Accordingly, the column labeled "RDET (mV)" in the operation chart <NUM> is blank indicating that individual input power measurements are not typically available in mission mode, but the average input power, RDET_avg_op, is available and in this example is shown as <NUM> mV. From the simultaneous input power values provided to the ADC <NUM> (<FIG>), the ADC <NUM> can determine that the average input power (RDET_avg_op) is 204mV in this example. In this operation example, because there are no individual input power measurements available, the highest measured input power (RDET_max) is unavailable. In this example, the value for DISTANCE may be determined by subtracting the value for RDET_variation (4mV) and the value for RDET_avg_op (204mV) from the THRESHOLD (238mV) resulting in a minimum distance of 30mV in this example.

In <FIG>, the power amplifier threshold voltage, THRESHOLD, is shown in the graph <NUM> using reference numeral <NUM> (<NUM> mV in this example), the value of RDET_variation (ΔRDET_cal) is shown using reference numeral <NUM> (<NUM> mV in this example), and the value of RDET_avg_op is shown using reference numeral <NUM> (<NUM> mV in this example). In this exemplary embodiment, RDET_avg_op (<NUM> mV) is different than RDET_avg_cal (<NUM> mV). However, as mentioned above, the values of RDET_avg_op and RDET_avg_cal may be the same if the conditions under which they are measured are the same or sufficiently similar.

In an exemplary embodiment, the threshold voltage, THRESHOLD, may be determined during characterization of the integrated circuit (IC) on which the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> are located. In an exemplary embodiment, the threshold voltage, THRESHOLD, refers to the maximum allowable voltage swing at the input to each power amplifier <NUM>, <NUM>, <NUM> and <NUM> at a given temperature, before damage to the power amplifier occurs, resulting in a permanent drop in gain, output power, and/or linearity. The threshold voltage may vary over temperature. In an exemplary embodiment, at a nominal temperature of <NUM> degrees Centigrade (C), the threshold voltage, THRESHOLD, may be determined for each power amplifier. As shown in the exemplary calibration chart <NUM> in <FIG> and operation chart <NUM> in <FIG>, the rows <NUM> and <NUM> and the column labeled "RDET Threshold (25C)" indicate that the threshold voltage, THRESHOLD, is <NUM> mV at this temperature. Using the value for THRESHOLD, the minimum value for the variable DISTANCE may be determined. In this example, because the measured mission mode average power, RDET_avg_op, is <NUM> mV, in the column labeled "@<NUM> C", the exemplary operation chart <NUM> also shows that for an average operating input power, RDET_avg_op, of 204mV, the minimum value for the variable DISTANCE is 30mV. Individual values in the column titled "@25C" are not entered because in this operation example, individual RDET input power measurements are not available.

In block <NUM>, based on the value of DISTANCE of 30mV, a power backoff can be estimated. For example, power backoff values can be determined based on temperature, as shown by the exemplary chart <NUM> of <FIG>. For example, at a temperature of <NUM> degrees C and a DISTANCE value of 30mV, the power backoff provided to the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> will be 0dB. Similarly, at a temperature of <NUM> degrees C and a DISTANCE value of 9mV, the power backoff provided to the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> will also be 0dB. In these instances, no power backoff is called for. However, at a temperature of <NUM> degrees C and a DISTANCE value of -11mV, the power backoff provided to the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> (e.g., via adjusting the AGC value, see below) will be -<NUM>. 18dB; and at a temperature of <NUM> degrees C and a DISTANCE value of -32mV, the power backoff provided to the power amplifiers <NUM>, <NUM>, <NUM> and <NUM> (e.g., via adjusting the AGC value, see below) will be -<NUM>. In this example, a negative value for DISTANCE indicates that the input power to that power amplifier has exceeded the voltage headroom (THRESHOLD) and should be reduced to prevent damage to the power amplifier. In some examples, if DISTANCE is less than a value other than zero (e.g., <NUM> (mV)), power is backed off.

In block <NUM>, the value for DISTANCE is used to determine gain control for one or more of the amplifiers. For example, the AGC value may be adjusted such that input power provided to the power amplifiers is adjusted. In an exemplary embodiment, the backoff in dB can be determined based on: <MAT>.

The above formula determines the amount of power backoff, and can be correlated to the value of the AGC control signal.

<FIG> is a call flow diagram <NUM> showing an example of the operation of a method for input power detection and power amplifier output calibration. The call flow diagram <NUM> shows an exemplary power amplifier <NUM>, and exemplary input power detector, RDET, <NUM>, an exemplary ADC <NUM> and an exemplary data processor <NUM>. Although a single power amplifier <NUM> and a single input power detector, RDET, <NUM> is shown in <FIG>, it is assumed that the number of power amplifiers and RDETs will vary, as shown in <FIG>, where four (<NUM>) power amplifiers and four (<NUM>) input power detectors, RDETs, are shown. In an exemplary embodiment, the ADC <NUM> may be the ADC <NUM> of <FIG>, and the data processor <NUM> may be the data process or <NUM> of <FIG>.

In call <NUM>, each input power detector, RDET, <NUM> receives a voltage signal representing the input power provided to a power amplifier <NUM>. In the example shown in <FIG>, four signals representing the input power of four power amplifiers are shown for each polarization. For example, a total of two instances of four voltage values, one for each polarization (e.g., one vertical polarization (Vpol) and one for horizontal polarization (Hpol), or one for two slant polarizations, etc.), may be included in call <NUM>.

In call <NUM>, each input power detector, RDET, <NUM> generates a voltage signal representing the input power provided to a power amplifier <NUM>. In the example shown in <FIG>, four signals representing the input power of four power amplifiers are shown for each polarization. For example, a total of two instances of four voltage values, one for each polarization may be included in call <NUM>.

In block <NUM>, the ADC <NUM> averages each of the (two instances of) four voltage values from the input power detector, RDET <NUM>, and generates a single digital signal (word) representing the average power for each set of four voltage values. In an exemplary embodiment, the two digital signals (words) represent the average power for the four voltage values for each polarization.

In call <NUM>, the digital signal(s) (words) are provided to the data processor <NUM> from the ADC <NUM>. In this example, two words are provided to the data processor <NUM>.

In block <NUM>, the data processor <NUM> processes the two digital signals and develops a gain control signal (e.g., AGC signal, in the form of an AGC index value), that may be based on a backoff value to adjust the power amplifier(s), via respective VGA and/or driver amplifiers, based on the threshold voltage, THRESHOLD, the value for DISTANCE, the average input power, RDET_avg_op, and the input power variation, RDET_variation.

In call <NUM>, the AGC signal used to provide the desired power is provided to an amplifier associated with each power amplifier <NUM> to control the power output of the power amplifier <NUM>.

In an exemplary embodiment, the calibration process described in <FIG> can be done during device calibration where sufficient time is available, and the adjustment process of <FIG> can be done quickly (e.g., within a symbol period where inputs might quickly vary depending on the signals being transmitted) during device operation to ensure that the input power provided to each power amplifier does not exceed a level at which damage to the power amplifier(s) might occur.

<FIG> is a functional block diagram of an apparatus for input power detection and power amplifier output calibration. The apparatus <NUM> comprises means <NUM> for measuring and storing the output power of each power amplifier in a phased array system. In certain embodiments, the means <NUM> for measuring and storing the output power of each power amplifier in a phased array system can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for measuring and storing the output power of each power amplifier in a phased array system may comprise output power detectors PDETs, <NUM>, <NUM>, <NUM> and <NUM>. The power measurement value for each power amplifier <NUM>, <NUM>, <NUM> and <NUM> may be stored in a memory <NUM> associated with the data processor <NUM> (<FIG>). The data processor <NUM> and/or VGA <NUM> may also be included in these means.

The apparatus <NUM> may also comprise means <NUM> for determining a gain mismatch value associated with the power amplifiers in the phased array system. In certain embodiments, the means <NUM> for determining a gain mismatch value associated with the power amplifiers in the phased array system can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for determining a gain mismatch value associated with the power amplifiers in the phased array system may comprise the data processor <NUM>. For example, in the operation described with respect to calibration chart <NUM> the data processor <NUM> may determine a gain mismatch among the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>), which is 14dBm, the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>), which is <NUM>. 5dBm, the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>), which is 12dBm, and the output power detected at communication port <NUM> (power amplifier <NUM> of <FIG>), which is 13dBm. In this example, the maximum gain difference is <NUM> dB.

The apparatus <NUM> may also comprise means <NUM> for applying fine gain correction among the power amplifiers to align the output power of each power amplifier to the lowest measured value. In certain embodiments, the means <NUM> for applying fine gain correction among the power amplifiers to align the output power of each power amplifier to the lowest measured value can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for applying fine gain correction among the power amplifiers to align the output power of each power amplifier to the lowest measured value may comprise the data processor <NUM> and/or one or more of the driver amplifiers <NUM>, <NUM>, <NUM>, <NUM>. For example, the data processor <NUM> may be configured to reduce a gain of the driver amplifiers <NUM>, <NUM>, <NUM>, <NUM> such that the outputs of the power amplifiers associated with communication ports <NUM>, <NUM>, <NUM> and <NUM> each have a nominal power output of 12dBm.

The apparatus <NUM> may also comprise means <NUM> for controlling the power amplifiers to provide the nominal (desired) output power. In certain embodiments, the means <NUM> for controlling the power amplifiers to provide the nominal (desired) output power can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for controlling the power amplifiers to provide the nominal (desired) output power may comprise the data processor <NUM> and/or VGA <NUM>.

The apparatus <NUM> may also comprise means <NUM> for measuring the input power of each power amplifier. In certain embodiments, the means <NUM> for measuring the input power of each power amplifier can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for measuring the input power of each power amplifier may comprise a respective input power detector, RDET <NUM>, <NUM>, <NUM> and <NUM>, which may, for example, serially or simultaneously measure the input power of the input signal provided to each power amplifier <NUM>, <NUM>, <NUM> and <NUM>.

The apparatus <NUM> may also comprise means <NUM> for storing the average input power, RDET_avg_cal, and the highest measured input power, RDET_max_cal. In certain embodiments, the means <NUM> for storing the average input power, RDET_avg_cal, and the highest measured input power, RDET_max_cal can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for storing the average input power, RDET_avg_cal, and the highest measured input power, RDET_max_cal, may comprise (a non-volatile (NV) portion of) the memory <NUM> (<FIG>) and/or the data processor <NUM>.

The apparatus <NUM> may also comprise means <NUM> for determining input power variation. In certain embodiments, the means <NUM> for determining input power variation can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for determining input power variation may comprise the data processor <NUM>. For example, the data processor <NUM> may be configured to determine the input power variation, RDET_variation, according to:
<MAT>.

The apparatus <NUM> may also comprise means <NUM> for storing the input power variation. In certain embodiments, the means <NUM> for storing the input power variation can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for storing the input power variation may comprise (a non-volatile (NV) portion of) the memory <NUM> (<FIG>) and/or the data processor <NUM>.

<FIG> is a functional block diagram of an apparatus for input power detection and power amplifier output calibration. The apparatus <NUM> comprises means <NUM> for providing input powers. In certain embodiments, the means <NUM> for providing input powers can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for providing input powers may comprise the input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM>. The input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM> may be configured to periodically provide input power for the respective power amplifiers <NUM>, <NUM>, <NUM> and <NUM> to the ADC <NUM> according to a pre-determined schedule. For example, the input power detectors, RDETs, <NUM>, <NUM>, <NUM> and <NUM> may be configured to provide input power for the respective power amplifiers <NUM>, <NUM>, <NUM> and <NUM> to the ADC <NUM> every <NUM>. In an exemplary embodiment, each RDET <NUM>, <NUM>, <NUM> and <NUM> may generate an analog voltage (for example, in mV) that represents respective input power of each power amplifier <NUM>, <NUM>, <NUM> and <NUM>. This may occur two times (2X) for each power amplifier, one time for each of two antenna polarizations for each power amplifier. The analog input voltages may be provided to an analog-to-digital converter (e.g., ADC <NUM>).

The apparatus <NUM> may also comprise means <NUM> for determining an average of all input powers. In certain embodiments, the means <NUM> for determining an average of all input powers can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for determining an average of all input powers may comprise the ADC <NUM>. For example, the ADC <NUM> may develop a digital word that represents the average of the analog input voltages for each power amplifier for each antenna polarization. In an exemplary embodiment, the ADC <NUM> generates two digital words representing the average power for the four exemplary power amplifiers <NUM>, <NUM>, <NUM> and <NUM> in this example, and for each of two antenna polarizations.

The apparatus <NUM> may also comprise means <NUM> for determining a voltage headroom. In certain embodiments, the means <NUM> for determining a voltage headroom can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for determining a voltage headroom may comprise the data processor <NUM>. For example, the data processor <NUM> may be configured to determine a variable referred to as "DISTANCE". In an exemplary embodiment, the variable DISTANCE represents a voltage level comprising the amount of voltage headroom between a power amplifier threshold voltage, THRESHOLD, and the sum of RDET_variation and RDET_avg_op, as shown in the below formula.

The apparatus <NUM> may also comprise means <NUM> for estimating power backoff. In certain embodiments, the means <NUM> for estimating power backoff can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for estimating power backoff may comprise the data processor <NUM>. For example, the data processor <NUM> may be configured to estimate backoff voltage based on a value of DISTANCE of 30mV in the example of <FIG>.

The apparatus <NUM> may also comprise means <NUM> for determining gain control. In certain embodiments, the means <NUM> for determining gain control can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for determining gain control may comprise the data processor <NUM> and/or the VGA <NUM>. For example, the data processor <NUM> may be configured to use the value for DISTANCE to determine the gain control that can be used to control an input power to one or more of the power amplifiers, for example by controlling a VGA index value. In an exemplary embodiment, the backoff in dB can be determined based on: <MAT>.

The above formula determines the amount of power backoff, and corresponds to the value of the gain control signal provided to a power amplifier.

The circuit architecture described herein described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc..

An apparatus implementing the circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc..

Claim 1:
A method (<NUM>) for power control, comprising:
simultaneously providing (<NUM>) input signal strength of each of a plurality of power amplifiers in a millimeter wave, mmW, phased array system;
determining (<NUM>) an average input signal strength of the plurality of power amplifiers based on the provided input signal strengths;
determining (<NUM>) a voltage headroom for the plurality of amplifies based on the determined average input signal strength;
estimating (<NUM>) a power backoff value based on the determined voltage headroom; and
determining (<NUM>) a gain control value for one or more amplifiers to achieve the estimated power backoff value.