Patent Description:
<FIG>, <FIG>, <FIG> and <FIG> show embodiments forming part of the claimed invention, <FIG>, <FIG>, <FIG> and <FIG> show embodiments not forming part of the claimed invention. <FIG> shows an embodiment being useful to understand the present invention.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

According to various embodiments of the present disclosure, stacked transistor architectures according to claim <NUM> having vertically aligned fins with diverse fin geometry are provided. In some embodiments, multiple fin widths are employed for different levels of fins. In some embodiments, multiple fin heights are employed for different levels of fins. For instance, different width fins at different vertical portions of stacked transistor architectures can provide improved characteristics such as improved electrical (e.g., propagation modes), thermal, yield, and mechanical characteristics. By way of example, different width fins for n-type metal oxide semiconductor (NMOS) devices versus p-type MOS (PMOS) devices can provide improved characteristics for complementary (CMOS) integrations in stacked device architectures (e.g., one fin width for NMOS devices for one level of the stack, and a different fin width for PMOS devices for another level of the stacked CMOS architecture). Electrical propagation modes can be improved in some CMOS configurations by using wider NMOS fins than CMOS fins. In some embodiments, there are more than two device layers in the stacked architecture. In some embodiments, the device layers include fin field-effect transistor (FinFET) devices and non-FinFET devices. In some embodiments, the device layers include integration of a nanoribbon or nanowire device layer with a FinFET device layer.

As noted above, there are a number of non-trivial performance issues associated with semiconductor fin architectures or semiconductor fin field-effect transistor (FinFET) architectures. Stacking FinFET devices can increase the density (or area density) of such devices on an integrated circuit. Further, different device layers can benefit from different width fins in stacked device architectures. However, an example approach to monolithic stacking would use the same width on top and bottom device layers, to use the same front-end lithography and isolation processes.

Accordingly, in various embodiments of the present disclosure, different fin geometries, i.e. different fin widths, are employed at different layers of a stacked transistor architecture. The fins are vertically aligned (such as originally formed from the same tall semiconductor fins) between device layers. In some embodiments not forming part of the claimed invention, the fins are consistently offset (e.g., at the same pitch, or at pitches that are integer multiples or integer divisors of one another) between device layers. In some embodiments, aspect ratio trapping (ART), which epitaxially seeds one semiconductor layer off an existing seed layer and forms new semiconductor within a mold, is used to form a top fin that is narrower or wider than a bottom fin in a vertically stacked process. In some embodiments, a single lithographic operation is used to fabricate fins having different widths, for example, stacked transistor architectures such as nanowires on FinFETs. Here, the nanowires (or nanoribbons) fit in the width of a semiconductor fin (or replacement semiconductor fin) structure and can be treated as a form of semiconductor fin within this disclosure.

In some embodiments, a CMOS integration of a stacked transistor architecture is provided, with NMOS transistors in one device layer and PMOS transistors in another device layer. The NMOS transistors use one fin width while the PMOS transistors use a different fin width. For instance, in some embodiments, it is useful to have a slightly wider (e.g., <NUM> % wider or more) fin for Group III-V (e.g., gallium arsenide) semiconductor materials than for Group IV (e.g., silicon, silicon germanium, and the like) semiconductor materials. In some of these embodiments, NMOS transistors use a wider Group III-V semiconductor fin layer than corresponding PMOS transistors in another device layer and implemented with a Group IV semiconductor. In some embodiments, a much wider second fin structure is utilized (e.g., <NUM>% wider, <NUM>% wider, or more), such as for nanowire or nanoribbon implementations (e.g., for NMOS fin structures). In some embodiments, a stacked CMOS transistor architecture is employed with a nanowire NMOS device layer and a FinFET PMOS device layer. Here, the NMOS nanowire width is significantly wider (e.g., twice as wide or more) as the PMOS FinFET fin width.

In an example embodiment of the present disclosure, an integrated circuit (IC) structure according to claim <NUM> is provided.

In another example embodiment of the present disclosure not forming part of the claimed invention, a stacked transistor structure is provided. The stacked transistor structure includes a top set of two or more transistors having corresponding semiconductor fin structures extending in a length direction, and a bottom set of two or more transistors having corresponding semiconductor fin structures extending in the length direction. The top set includes a top transistor having a top semiconductor fin structure, and a source region and a drain region separated by and physically connected to a portion of the top semiconductor fin structure. The semiconductor fin structures in the bottom set are under and consistently offset in a width direction with the semiconductor fin structures of the top set. The bottom set includes a bottom transistor having a bottom semiconductor fin structure, and a source region and a drain region separated by and physically connected to a portion of the bottom semiconductor fin structure. A height, a width, or both the height and width of the portion of the top semiconductor fin structure is different from the height, width, or both the height and width of the bottom semiconductor fin structure.

<FIG> are cross-sectional views of an example stacked transistor architecture <NUM> including upper and lower transistors, according to an embodiment of the present disclosure. In the stacked transistor architecture <NUM>, <FIG> is a Y-Z view and <FIG> is an X-Z view, where X, Y, and Z represent the length, width, and height dimensions of the underlying semiconductor fins making up the stacked transistors. In more detail, <FIG> is a cross-sectional view through gate electrodes <NUM> and <NUM> of the upper and lower transistors, respectively, while <FIG> is a cross-sectional view through upper and lower fins <NUM> and <NUM> of the upper and lower transistors, respectively. The lower fin <NUM> is wider than the upper fin <NUM>. For example, the lower fin <NUM> is <NUM> % or more wider (e.g., <NUM> %, <NUM> %, or <NUM> %) than the upper fin <NUM>.

Here, width can be defined to be a suitable width based on factors such as the shape of the fin. For example, the width can be an average width, or a width at a consistent location (such as halfway up the fin in a vertical or height direction), or a transition width (e.g., width of the top portion of a lower fin and the bottom portion of an upper fin), or the like. Measurements like height (when comparing fin geometries) can be defined similarly. Dimensions like height and width can also be defined relative to the devices or device features being compared. For example, fin height can be the gate height, such as the vertical component corresponding to the overlap of the gate structure (e.g., gate electrode and gate dielectric) and the fin.

It should be noted that while most of the description herein is directed to stacked transistor architectures having two device layers (e.g., an upper device layer and a lower device layer), some other embodiments of the present disclosure are directed to stacked transistor architectures of three or more device layers. For example, in some embodiments, there are three or more device layers in a stacked transistor architecture, where the fin widths of the corresponding devices of two or more of the device layers are different. It should further be noted that while most of the description is directed to rectangular shape fins, other embodiments are not so limited. For instance, in other embodiments, the fins can be different shapes, such as trapezoidal or rounded shape, and the techniques disclosed herein still apply.

Referring to <FIG>, semiconductor <NUM>, such as silicon (Si), silicon germanium (SiGe), or a Group III-V semiconductor such as gallium arsenide (GaAs) is formed into vertical fins, such as lower fin <NUM> and upper fin <NUM>. In some embodiments, the lower fin <NUM> and upper fin <NUM> are at one time part of the same vertical fin extending from semiconductor <NUM>. At some point in the fabrication, one or both of these fin structures may be replaced with a different fin structure using the original fin shape as a guide or template for forming the replacement fin or fins. For example, in some embodiments, the upper fin <NUM> includes replacement semiconductor fin material different than the semiconductor fin material of the lower fin <NUM>. The lower fin <NUM> is covered with a lower gate dielectric <NUM>, such as a high-κ dielectric like hafnium dioxide (HfO<NUM>). In a similar fashion, the upper fin <NUM> is covered with an upper gate dielectric <NUM> such as HfO<NUM> (for example, the same gate dielectric material as the lower gate dielectric <NUM>). The lower gate dielectric <NUM> is covered with a lower gate electrode <NUM>, such as one or more of a metal, conductive oxide, heavily doped semiconductor, and the like. Likewise, the upper gate dielectric <NUM> is covered with an upper gate electrode <NUM>, such as one or more of a metal, conductive oxide, heavily doped semiconductor, and the like.

The lower and upper gate electrodes <NUM> and <NUM> control the lower and upper transistors, respectively, by applying gate voltages to semiconductive channel regions <NUM> and <NUM> of the lower and upper transistors. The lower and upper gate electrodes <NUM> and <NUM> can be the same composition or different (e.g., different metal, different dopant type, or the like). The channel regions <NUM> and <NUM> electrically connect source and drain regions <NUM> and <NUM> (of the lower transistor) and source and drain regions <NUM> and <NUM> (of the upper transistor) in response to the applied gate electrode voltage. The source and drain regions <NUM> and <NUM> (and <NUM> and <NUM>) can be, for example, heavily doped regions of the lower fin <NUM> and upper fin <NUM>. For instance, n-type source and drain regions can be semiconductor material heavily doped with n-type dopant, while p-type source and drain regions can be semiconductor material heavily doped with p-type dopant. In some embodiments, the source and drain regions <NUM> and <NUM> (and <NUM> and <NUM>) are replacement semiconductor material, such as epitaxially formed source and drain regions with in situ doping.

The upper transistors of the stacked transistor architecture <NUM> are usually electrically isolated (or not in direct contact) from the lower transistors. By way of example, an insulating dielectric <NUM> such as silicon dioxide (SiO<NUM>) covers the lower gate electrode <NUM> to electrically separate the lower gate electrode <NUM> from the upper gate electrode <NUM>. In addition, lower isolation layer <NUM> and upper isolation layer <NUM> also electrically separate the lower and upper transistors (such as the source and drain regions <NUM> and <NUM> of the lower transistor from the source and drain regions <NUM> and <NUM> of the upper transistor). The lower isolation layer <NUM> covers the lower source and drain regions <NUM> and <NUM> of the lower fin <NUM> while the upper isolation layer <NUM> is below the upper fin <NUM> and above the lower isolation layer <NUM> and the insulating dielectric <NUM> covering the lower gate electrode <NUM>. The lower and upper isolation layers <NUM> and <NUM> correspond to the semiconductor fin (e.g., formed originally from the same tall semiconductor fin), such as between and vertically aligned with the lower fin <NUM> and upper fin <NUM>.

For example, the lower and upper isolation layers <NUM> and <NUM> can be doped semiconductor. For instance, if the upper transistor is an NMOS device, then the upper isolation layer <NUM> can be p-doped semiconductor, and if the upper transistor is a PMOS device, then the upper isolation layer <NUM> can be n-doped semiconductor. Likewise, if the lower transistor is an NMOS device, then the lower isolation layer <NUM> can be p-doped semiconductor, and if the lower transistor is a PMOS device, then the lower isolation layer <NUM> can be n-doped semiconductor. In some embodiments, the lower and upper isolation layers <NUM> and <NUM> are formed through oxidation or removal of a portion of the fin between the lower and upper fins <NUM> and <NUM>. In some embodiments, the lower and upper isolations layers <NUM> and <NUM> are formed through fixed charge layers adjacent to the fin (such as fixed charge layers adjacent to the lower and upper isolation layers <NUM> and <NUM>). Remaining spaces can be filled with further insulating dielectric <NUM> such as SiO<NUM>.

<FIG> are cross-sectional views of an example stacked transistor architecture <NUM>, according to another embodiment of the present disclosure. The stacked transistor architecture <NUM> of <FIG> is similar to the stacked transistor architecture <NUM> of <FIG>, with corresponding elements between <FIG> and <FIG> being numbered the same and their corresponding descriptions not necessarily being repeated.

In the stacked transistor architecture <NUM>, the lower gate structure (e.g., lower gate <NUM> and lower gate dielectric <NUM>) does not extend down to the semiconductor <NUM>. Rather, the semiconductor <NUM> (and possibly the lower gate dielectric <NUM>) are polished (or selectively or anisotropically etched) to extend the lower fin <NUM> (exposing lower fin extension <NUM>). The trench areas corresponding to the lower fin extension <NUM> are filled with a lower dielectric <NUM> (such as a shallow trench fill or shallow trench isolation), which can be, for example, an insulating oxide such as SiO<NUM> (or a nitride, oxynitride, or other insulating material). The lower gate electrode <NUM> is formed on the lower dielectric <NUM> and remaining lower gate dielectric <NUM>. It should be noted that the dielectric <NUM> in <FIG> is renamed as upper dielectric <NUM> in <FIG>.

Features of the above embodiments may be combined or selectively appear in other embodiments. For example, features such as the fin extension, the covering of non-fin areas with the gate dielectric (or removal of the gate dielectric from the non-fin areas), the forming of the shallow trench fill (or other dielectric corresponding to the fin extension), to name a few, can appear in different combinations in different embodiments. For instance, the embodiments in <FIG> described below can be modified to incorporate or remove features (and produce other embodiments) in this manner.

By way of example, in some embodiments, the lower gate dielectric <NUM> can be polished or etched away to expose the lower semiconductor <NUM> (e.g., the backside of the semiconductor <NUM>), and the lower gate electrode <NUM> formed on the backside of the semiconductor <NUM> (e.g., contacting the semiconductor <NUM>). See, for instance, <FIG> for one such embodiment. By way of another example, in some embodiments, the shallow trench fill or lower dielectric <NUM> can be formed between lower fins <NUM>, and the gate structures formed on the lower dielectric <NUM>. This effectively forms a lower fin extension <NUM> without further etching or polishing of the semiconductor <NUM> as discussed above. It should be noted that, in different embodiments, the dielectric materials for the lower dielectric <NUM>, (upper) dielectric <NUM>, and upper isolation <NUM> may be the same or different.

<FIG> are cross-sectional views of an example method of fabricating the stacked transistor architecture <NUM> of <FIG>, according to an embodiment of the present disclosure. The method of <FIG> highlights the formation of the different width fins (such as lower and upper fins <NUM> and <NUM>) in the stacked transistor architecture <NUM> of <FIG>. For instance, in <FIG>, semiconductor <NUM> has tall, narrow fins <NUM> formed on top of it (e.g., through photolithography, epitaxial growth, or similar technique), with corresponding trenches between (and defined by) adjacent fins <NUM>. The fins <NUM>, for example, can be made of the same semiconductor material as semiconductor <NUM>, and be of a uniform or consistent width or shape. It is desired to use the fins <NUM> to form a stacked transistor architecture, with the upper portions of the fins <NUM> having a smaller width than the lower portions of the fins <NUM>.

In <FIG>, dielectric material <NUM> (such as SiO<NUM>, silicon oxynitride, silicon nitride, or the like) is used to fill the trenches and cover the fins <NUM>. In <FIG>, the excess dielectric material <NUM> is planarized (e.g., through chemical-mechanical planarization or similar technique) or otherwise removed to produce planarized fins <NUM> and dielectric material <NUM>. In some embodiments, this operation is omitted. In <FIG>, the planarized dielectric material <NUM> is recessed (e.g., through a timed etch) to produce recessed dielectric material <NUM> corresponding to the desired height of the lower fins and leaving the upper portions of the planarized fins <NUM> exposed. In <FIG>, the upper (exposed) portions of the planarized fins <NUM> are selectively etched while leaving the lower (covered) portions of the planarized fins <NUM> alone, producing etched (narrowed) upper fins <NUM> and leaving (normal width) lower fins <NUM>. For example, the selective etching can be a digital etch, such as a (shallow) plasma oxidation of the exposed upper portion of the planarized fins <NUM> followed by a selective oxide removal of the oxidized surface material. In other embodiments, the selective etching can be a wet etch or similar process to remove only a (controlled) portion of the upper (exposed) part of the planarized fins <NUM>. In <FIG>, the remaining recessed dielectric material <NUM> is removed to reveal the upper fins <NUM> having smaller widths than the lower fins <NUM>.

<FIG> are cross-sectional views of an example method of fabricating the stacked transistor architecture <NUM> of <FIG>, according to another embodiment of the present disclosure. In <FIG>, similar operations leading to the embodiment of <FIG> are performed, only this time followed by a selective etch to recess the planarized fin (instead of to recess the planarized dielectric as in <FIG>) to produce recessed fins <NUM> and leaving the planarized dielectric <NUM> in place. For example, the planarized fin can be recessed to the intended height of the lower fins. In <FIG>, a spacer <NUM> is formed on top of the planarized dielectric <NUM> and recessed fins <NUM>. For example, an isotropic deposition such as atomic layer deposition (ALD) or the like can be used to deposit a very thin (e.g., a few nanometers (nm) thick, such as <NUM> or <NUM>) layer of spacer material (e.g., a nitride or other material chemically different than the dielectric or fin material). In <FIG>, the horizonal portions of the spacer <NUM> are removed by, for example, an anisotropic etch such as dry etching or plasma etching to form etched spacers <NUM> within (e.g., lining the walls of) the evacuated fins. The lined evacuated fins are also referred to as molds (for epitaxial growth).

In <FIG>, epitaxial semiconductor <NUM> is grown (e.g., templated growth) within the molds (and extending slightly past the top of the molds), using the semiconductor material <NUM> present at the top of the recessed fins <NUM> to serve as seed crystals (e.g., the template). From these seed crystals, a second (different) semiconductor can be grown epitaxially, such as by using aspect ratio trapping (ART) within the molds. ART traps defects between the two semiconductor crystal structures using high aspect ratio features such as these molds, allowing the second semiconductor to grow without defects throughout most of the mold.

For example, the base semiconductor <NUM> can be silicon (Si) and the epitaxial semiconductor <NUM> can be germanium (Ge) or a III-V semiconductor such as GaAs. The ART technique allows the crystal mismatch between the two different semiconductors to be corrected within the mold (or other high aspect ratio feature) at locations near the interface of the two semiconductors (such as within <NUM> % of the vertical height of the feature or mold). Such crystal defects at the interface will be apparent under high magnification (such as with electron microscopy) when using techniques such as ART. In <FIG>, the top surface of the molds is planarized to produce further planarized dielectric material <NUM>, planarized spacers <NUM>, and planarized semiconductor <NUM>.

In <FIG>, the further planarized dielectric material <NUM> and the planarized spacers <NUM> are removed (e.g., through selecting etching) to reveal upper fins <NUM> and lower fins <NUM>, with the lower fins <NUM> being wider than the upper fins <NUM>. Here, the upper fins <NUM> can be a different semiconductor than the lower fins <NUM>. When using techniques such as ART, different semiconductors will form crystal defects <NUM> at the boundaries between the lower fins <NUM> and the upper fins <NUM>. While the density of defects <NUM> will be greatest at the boundary, they can still be found at distances (such as <NUM> % of the feature height) away from the boundary, such as in a defect region <NUM>. For example, if the upper fins <NUM> extend <NUM> in height, the defects <NUM> may be contained in the bottom <NUM> of the upper fins <NUM>, while if the lower fins <NUM> are <NUM> tall, the defects <NUM> may be contained in the top <NUM> of the lower fins <NUM> (accordingly, the defect region <NUM> may be <NUM> tall). The defects <NUM> are due to crystal mismatches between the two semiconductors, but gradually correct themselves as the ART process extends up the feature (trapping such defects near the semiconductor boundaries and eventually producing the proper crystal structure for most of the feature height).

The technique of <FIG> can also be performed using the same semiconductor for the lower and upper fins <NUM> and <NUM>. In this case, there will not be crystal mismatches or defects at the interface since it is the same material, but the upper fins <NUM> will still be smaller in width than the lower fins <NUM>.

<FIG> are cross-sectional views of an example method of fabricating a stacked transistor architecture, according to an embodiment of the present disclosure. Contrary to the techniques illustrated in <FIG> and <FIG>, in the method of <FIG>, the goal is produce upper semiconductor fins that are wider than their corresponding lower semiconductor fins. The method has a similar initial process to that shown above for <FIG>, such as the operations leading up to <FIG> with planarized dielectric material and recessed fins <NUM> on base semiconductor <NUM>. In <FIG>, the two techniques start to diverge. Instead of forming spacers, in <FIG>, a timed selective etch (e.g., wet etch) of the dielectric material is performed to remove a portion of the dielectric material (such as to blow out the ART mold) and widen the evacuated region formed by the recessed fins <NUM>. This produces etched dielectric <NUM>. In <FIG>, epitaxial semiconductor <NUM> is grown in the molds similar to the process illustrated in <FIG>, only in this case the mold is wider than the recessed fins <NUM>. For instance, ART can be used to epitaxially grow a different semiconductor <NUM> in the evacuated (and blown out) dielectric areas between the etched dielectric <NUM>. In another embodiment, the same semiconductor could be deposited (e.g., when a material change is not needed between the lower and upper fins, but a width change is needed).

In <FIG> (as in <FIG>), the epitaxially grown semiconductor <NUM> and the etched dielectric <NUM> is planarized to form planarized semiconductor <NUM> and planarized dielectric <NUM>. In <FIG>, the planarized dielectric <NUM> is removed (e.g., through selective etching) to reveal the upper fins <NUM> and the lower fins <NUM>, which can be different semiconductor materials. In addition, if a technique such as ART is used to form the upper fins <NUM> of a different semiconductor material than the lower fins <NUM>, there will be a region <NUM> of semiconductor crystal defects <NUM> (similar to that in <FIG>) at boundaries between the lower fins <NUM> and the upper fins <NUM>, with the defect region <NUM> containing all or most of the defects <NUM>.

<FIG> are cross-sectional views (similar to <FIG>) of example bonding and layer transfer implementations of stacked transistor architectures <NUM> and <NUM>, according to embodiments of the present disclosure. The semiconductor fin layers in the stacked transistor architectures <NUM> and <NUM> are formed as two separate base lithographies. For instance, in the stacked transistor architecture <NUM>, lower fins <NUM> are formed using one (base) lithography, while upper fins <NUM> are formed using a different (base) lithography. This contrasts with the examples shown above, where the base semiconductor fins can be formed in one lithography.

In further detail, in the stacked transistor architecture <NUM> in <FIG>, upper and lower device layers make up the transistor architecture <NUM>. The lower device layer includes base semiconductor <NUM> and corresponding lower fins <NUM>. Lower dielectric <NUM> (e.g., SiO<NUM>) covers the bottoms of the lower fins <NUM> (e.g., to better electrically isolate the lower fins <NUM> from one another). Lower gate dielectric <NUM> (e.g., high-κ material such as HfO<NUM>) covers lower fins <NUM> to electrically insulate the lower fins <NUM> from lower gate electrode <NUM> (e.g., metal, conductive oxide, doped semiconductor, or the like). The lower device layer is topped with a layer of etch stop material <NUM> (such as silicon nitride) and (optionally) planarized.

The upper device layer is formed from a separate substrate, such as upper dielectric <NUM> (e.g., an insulating dielectric/bonding layer such as SiO<NUM>). The upper device layer has a layer of semiconductor material (can be the same or different semiconductor than semiconductor <NUM>) on the upper dielectric <NUM> prior to bonding with the lower device layer. After bonding the unformed upper device layer to the formed bottom device layer (e.g., through layer transfer or other bonding technique), the upper fins <NUM> are formed from the upper semiconductor layer. The upper fins <NUM> can be formed at the same pitch and in vertical alignment with the lower fins <NUM>. An upper gate dielectric <NUM> and upper gate electrode <NUM>, e.g., similar construction and materials to their lower device layer counterparts (such as lower gate dielectric <NUM> and lower gate electrode <NUM>), is formed on the upper fins <NUM> to form the upper transistors.

In some embodiments, the upper fins are formed at the same pitch as the bottom fins, and in the same length direction, but offset (e.g., staggered) vertically in the width direction. In some embodiments, the upper fins are more numerous than the lower fins (e.g., twice as many, or three times as many, or more), and their corresponding pitches are an integer divisor of the bottom fin pitches (e.g., half the pitch, one-third the pitch, or less), with the upper fins being consistently offset with respect to the bottom fins. In some embodiments, the lower fins are more numerous (and with corresponding integer divisors for pitches) than the upper fins, but are consistently offset in the width direction with respect to the upper fins.

The stacked transistor architecture <NUM> in <FIG> is similar to the stacked transistor architecture <NUM> in <FIG>, only the stacked transistor architecture <NUM> lacks the etch stop layer <NUM>. For example, the upper device layer in the stacked transistor architecture <NUM> can be layer transferred directly on the lower gate electrode <NUM> (and other device features, such as source and drain electrodes, and space possibly filled with dielectric), with the lower gate electrode <NUM> (and other top structures) being (optionally) planarized prior to the layer transfer.

<FIG> is a cross-sectional view of an example nanowire stacked transistor architecture <NUM>, according to an embodiment of the present disclosure. In the nanowire stacked transistor architecture <NUM>, the upper device layer includes a set of vertically aligned semiconductor nanowires <NUM> (the same or different semiconductor material as semiconductor <NUM>), with upper gate dielectric <NUM> (e.g., high-κ material such as HfO<NUM>) surrounding each nanowire <NUM>, and upper gate electrode <NUM> (e.g., metal, conductive oxide, doped semiconductor, or the like), surrounding the gate-dielectric wrapped nanowires <NUM>. By way of example, the nanowire stacked transistor architecture <NUM> in <FIG> can be formed similarly to the stacked transistor architecture <NUM> of <FIG> (e.g., semiconductor <NUM>, lower fin <NUM>, lower gate dielectric <NUM>, lower gate electrode <NUM>, dielectric layer <NUM>, and upper isolation layer <NUM>), but with wider fin molds (e.g., blown out ART molds) for the upper fins compared to the lower fins <NUM>.

However, the lower gate dielectric <NUM> is formed only on the lower fin <NUM> such that the lower gate electrode <NUM> is formed directly on the semiconductor <NUM>. Further, instead of forming continuous upper fins (as in <FIG>), in <FIG>, individual nanowires <NUM> are formed (e.g., epitaxially grown) vertically in the fin mold, with other material (e.g., replaceable dielectric material) separating the nanowires <NUM> and that can be removed prior to forming the upper gate dielectric <NUM>.

The nanowires <NUM> increase the surface area contact between the upper gate structure (e.g., upper gate dielectric <NUM> and upper gate electrode <NUM>) and the semiconductive channel portion of the upper transistors, which provides for more efficient gate operation. The nanowire device layer integrates well with a FinFET device layer for the stacked device architecture. For instance, a CMOS integration can use Group III-V semiconductor nanowires in the upper device layer for the NMOS transistors and Group IV semiconductor FinFET devices in the lower device layer for the PMOS transistors (having much smaller fin width than the nanowire width). For example, the nanowires can be <NUM> %, <NUM> %, or more wider than the comparable FinFET channel regions in the same integration. In some embodiments, the stacked nanowires are formed from different semiconductors (e.g., epitaxially grown into a superlattice of different materials for the different nanowires making up a device layer).

<FIG> are cross-sectional views of an example single-gate stacked transistor architecture <NUM>, according to an embodiment of the present disclosure. In the single-gate stacked transistor architecture <NUM> of <FIG>, there is an upper device layer (including an upper transistor) and a lower device layer (including a lower transistor). The stacked transistor architecture <NUM> is similar to that of the stacked transistor architecture <NUM> of <FIG>, e.g., semiconductor <NUM>, lower fin <NUM> (including lower source region <NUM>, drain region <NUM>, and channel region <NUM>), lower gate electrode <NUM>, lower isolation later <NUM>, upper isolation layer <NUM>, upper fin <NUM> (including upper source region <NUM>, drain region <NUM>, and channel region <NUM>), and upper gate dielectric <NUM>, which are similar to their counterparts in the stacked transistor architecture <NUM>. However, the stacked transistor architecture <NUM> includes a single gate electrode <NUM> (with modifications to the insulating dielectric region <NUM>) to control both the upper and lower transistors. The lower fin <NUM> is wider than the upper fin <NUM>. In other embodiments, the lower fin <NUM> and upper fin <NUM> share a common gate dielectric layer or common gate dielectric material in place of, or in addition to, a common gate electrode.

<FIG> is a cross-sectional view of an example stacked transistor architecture <NUM>, according to another embodiment of the present disclosure. The stacked transistor architecture <NUM> of <FIG> includes similar components to that of the stacked transistor architecture <NUM> of <FIG>, e.g., semiconductor <NUM>, lower fin <NUM>, lower gate dielectric <NUM>, lower gate electrode <NUM>, insulating dielectric <NUM>, upper isolation layer <NUM>, upper fin <NUM>, upper gate dielectric <NUM>, and upper gate electrode <NUM>, which are similar to their counterparts in the stacked transistor architecture <NUM> of <FIG>. However, in the stacked transistor architecture <NUM> of <FIG>, the lower fin <NUM> and upper fin <NUM> have the same width, but different heights. The upper fin <NUM> is taller than the lower fin <NUM>. In some embodiments, the height of the lower fin is greater than the height of the upper fin.

<FIG> are flow diagrams of example methods <NUM>-<NUM> of fabricating integrated circuit structures, according to embodiments of the present disclosure. These and other methods disclosed herein may be carried out using integrated circuit fabrication techniques such as photolithography as would be apparent in light of the present disclosure. The corresponding transistors and other devices may be part of other (logic) devices on the same substrate, such as application specific integrated circuits (ASICs), microprocessors, central processing units, processing cores, and the like. Unless otherwise described herein, verbs such as "coupled" or "couple" refer to an electrical coupling (such as capable of transmitting an electrical signal), either directly or indirectly (such as through one or more conductive layers in between).

Referring to the method <NUM> of <FIG> (with specific example references to the structures or operations of <FIG>), processing begins with forming <NUM> semiconductor fins (such as fins <NUM> in <FIG>) extending in a same length direction. Each of the fins includes a lower portion (such as lower fin <NUM>) and an upper portion (such as upper fin <NUM>). The fins define corresponding trenches (such as the empty portion between the two fins <NUM>) between the fins extending in the length direction.

The method <NUM> further includes filling <NUM> the trenches with dielectric material (such as dielectric material <NUM> in <FIG>), planarizing <NUM> the dielectric material to expose top surfaces of upper portions of the fins (see <FIG>), removing <NUM> the upper portions of the fins to expose top surfaces of the lower portions of the fins while leaving cavities (such as the empty portions between adjacent planarized dielectric regions <NUM> in <FIG>) in the dielectric material whose shapes correspond to those of the removed upper portions of the fins, modifying <NUM> walls of the cavities (such as etched spacers <NUM> in <FIG>) to alter widths of the cavities (e.g., make them wider or narrower) compared to widths of the removed upper portions of the fins, and filling <NUM> the modified cavities with replacement semiconductor fin material (such as epitaxial semiconductor <NUM> in <FIG>) to form new upper portions of the fins having different widths than the widths of the removed upper portions of the fins.

Referring to the method <NUM> of <FIG>, processing begins with forming <NUM> semiconductor fins extending in a same length direction. Each of the fins includes a lower portion and an upper portion. The fins define corresponding trenches between the fins extending in the length direction. The method <NUM> further includes filling <NUM> the trenches with dielectric material, planarizing <NUM> the dielectric material to expose top surfaces of the upper portions of the fins, removing <NUM> upper portions of the dielectric material to expose the upper portions of the fins while leaving the lower portions of the fins covered by the dielectric material (see <FIG>), and removing <NUM> surface portions of the exposed upper portions of the fins to decrease widths of the exposed upper portions of the fins compared to widths of the covered lower portions of the fins (see <FIG>).

Referring to the method <NUM> of <FIG>, processing begins with forming <NUM> a bottom fin layer having semiconductor bottom fins (such as lower fins <NUM>) extending in a length direction, forming <NUM> a bottom transistor including a semiconductor portion of one of the bottom fins, source and drain portions on different sides of and adjacent to the semiconductor portion, a gate dielectric on the semiconductor portion, and a gate electrode on the gate dielectric (see <FIG>), filling <NUM> spaces in the bottom fin layer with dielectric material and planarizing the bottom fin layer, bonding <NUM> a semiconductor layer to the planarized bottom fin layer with a dielectric bonding layer (such as upper dielectric layer <NUM>), and forming <NUM> a top fin layer by forming semiconductor top fins (such as upper fins <NUM>) from the semiconductor layer. The top fins extend in the length direction and are vertically aligned (see <FIG>) or are consistently offset in a width direction with the bottom fins. The width of the semiconductor portion is different than the width of the top fins.

While the above example methods appear as a series of operations or stages, it is to be understood that there is no required order to the operations or stages unless specifically indicated.

<FIG> illustrates a computing system <NUM> implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure. As can be seen, the computing system <NUM> houses a motherboard <NUM>. The motherboard <NUM> may include a number of components, including, but not limited to, a processor <NUM> (including stacked transistor structures as described herein) and at least one communication chip <NUM>, each of which can be physically and electrically coupled to the motherboard <NUM>, or otherwise integrated therein. As will be appreciated, the motherboard <NUM> may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system <NUM>, to name a few examples.

Depending on its applications, computing system <NUM> may include one or more other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM), resistive random-access memory (RRAM), and the like), a graphics processor, a digital signal processor, a crypto (or cryptographic) processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system <NUM> may include one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip <NUM> can be part of or otherwise integrated into the processor <NUM>).

The communication chip <NUM> enables wireless communications for the transfer of data to and from the computing system <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, and the like. , that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The computing system <NUM> may include a plurality of communication chips <NUM>.

The processor <NUM> of the computing system <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., stacked transistor structures) formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also may include an integrated circuit die packaged within the communication chip <NUM>. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., stacked transistor architectures) formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor <NUM> (e.g., where functionality of any chips <NUM> is integrated into processor <NUM>, rather than having separate communication chips). Further note that processor <NUM> may be a chip set having such wireless capability. In short, any number of processor <NUM> and/or communication chips <NUM> can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., stacked transistor architectures) formed using the disclosed techniques, as variously described herein.

Claim 1:
An integrated circuit (IC) structure comprising:
a top fin (<NUM>) consisting of semiconductor material and extending in a length direction;
a bottom fin (<NUM>) consisting of semiconductor material and extending in the length direction, the bottom fin (<NUM>) being under and vertically aligned with the top fin (<NUM>);
a top gate structure (<NUM>) in contact with a portion of the top fin (<NUM>);
a top source region (<NUM>) and a top drain region (<NUM>) each adjacent to the portion of the top fin (<NUM>), such that the portion of the top fin (<NUM>) is between the top source region (<NUM>) and the top drain region (<NUM>);
a bottom gate structure (<NUM>) in contact with a portion of the bottom fin; and
a bottom source region (<NUM>) and a bottom drain region (<NUM>) each adjacent to the portion of the bottom fin (<NUM>), such that the portion of the bottom fin (<NUM>) is between the bottom source region (<NUM>) and the bottom drain region (<NUM>);
wherein widths of the portions of the top and bottom fins are different; and
characterized in that
the top fin (<NUM>) is separated from the bottom fin (<NUM>) by an upper isolation (<NUM>) and a dielectric (<NUM>), and wherein the top source region (<NUM>) and top drain region (<NUM>) are separated from the bottom source region (<NUM>) and bottom drain region (<NUM>) by the upper isolation (<NUM>) and a lower isolation (<NUM>), and wherein the upper gate (<NUM>) is separated from the lower gate (<NUM>) by the dielectric (<NUM>).