Patent Description:
In many applications, receivers receive interference along with the data-bearing portion of the signal. While later stages may filter the interference, stages before the filter stages may be subject to the interference components of the signal. When amplifying the signal, both the interference and the data-bearing portion may contribute to the saturation of the amplified signal. <CIT> discloses packet-based radio receiver with automatic gain control. <CIT> discloses apparatus and methods for detection of interface in radio-frequency devices. <CIT> discloses dynamic range on demand receiver and method of varying same.

The invention is defined by the independent claims <NUM> and <NUM>. In some examples, an integrated circuit is provided that includes a receiver chain for a wireless receiver. The receiver chain includes amplifier stages, mixer stages, filter stages, and/or other suitable stages. Properties of these stages, including gain, may be controlled by an automatic gain control (AGC) circuit that receives feedback of the signal strength from the various stages and adjusts the properties of the stages accordingly. Various stages in the receiver stages may filter interference and preserve the data-bearing portion of the signal, and so the feedback from these stages may not measure the interference components. Because the interference may contribute to signal saturation, particularly in stages of the receiver chain before the filter stages, the receiver chain may include a separate control path running in parallel that preserves the interference for use in AGC determinations.

In some examples, an integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response to the input signal and the control signal. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path is coupled to the amplifier stage that receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component of the input signal. A gain control circuit is coupled to the main path and the control path that receives the first feedback signal and the second feedback signal and provides the control signal in response to the first feedback signal and the second feedback signal.

In some examples, an integrated circuit includes an amplifier with a first input, a control input, and an output. A first path is coupled to the amplifier that includes an output and a first mixer stage coupled to the output of the amplifier. A second path is coupled to the amplifier that includes an output and a second mixer stage coupled to the output of the amplifier. The integrated circuit also includes a control circuit with a first input coupled to the output of the first mixer stage, a second input coupled to the output of the second mixer stage, and an output coupled to the control input of the amplifier.

In some examples, a method includes receiving an input signal, and amplifying the input signal according to a gain control signal to produce an amplified signal. A first baseband conversion is performed on the amplified signal to produce a first intermediate frequency signal, and a first feedback signal is determined based on the first intermediate frequency signal that corresponds to a signal strength of a data-bearing portion of the input signal. A second baseband conversion is performed on the amplified signal to produce a second intermediate frequency signal, and a second feedback signal is determined based on the second intermediate frequency signal that corresponds to a signal strength of the data-bearing portion and an interference component of the input signal. The gain control signal is modified based on the first feedback signal and the second feedback signal.

Features of the present invention may be understood from the following detailed description and the accompanying drawings.

Specific examples are described below in detail with reference to the accompanying figures. These examples are not limiting, and unless otherwise noted, no feature is required for any particular example. Moreover, a first device that is coupled (electrically, physically, or otherwise) to a second device may be coupled directly without any intervening device or indirectly through one or more intervening devices.

An example receiver includes a receiver chain with a number of analog and digital stages that process a received signal to extract data from the signal. These stages may include one or more amplifier stages that amplify the received signal. The maximum combined gain of the receiver chain may be relatively high (e.g., about <NUM> dB in some examples) so that data can be extracted from weaker signals. However, applying the maximum gain to a stronger signal may saturate the amplified signal, which may cause clipping and other types of distortion. Accordingly, the example receiver includes an automatic gain control (AGC) circuit that adjusts the operation of one or more stages in the receiver chain to decrease gain when the signal is relatively strong and increase gain when the signal is relatively weak.

In some examples, the AGC circuit receives a first feedback signal that corresponds to signal strength from an analog-to-digital converter (ADC) of the receiver chain. Because the receiver chain may have filtered out interference from the signal before it reached the ADC, the first feedback signal may correspond primarily to the strength of the data-bearing portion of the signal. However, both the data-bearing portion and interference in the signal may contribute to signal saturation. Accordingly, the example AGC also receives a second feedback signal that corresponds to signal strength of both the data-bearing portion and the interference. This second feedback signal may be provided by a parallel control path in the receiver chain that includes stages such as a baseband down-conversion mixer, a peak detector, and/or an ADC. The stages of the control path may be specifically configured to preserve and even amplify the interference.

By considering the interference as well as the data-bearing portion of the signal, the AGC may more aggressively increase gain in low- and moderate-interference situations. In some such examples, the receiver is able use the increased amplification to detect received signals having <NUM> dB less power than comparable designs.

In some examples, the control path includes a baseband down-conversion mixer with wide bandwidth to preserve interference that also amplifies the signal being down-converted to increase sensitivity to the interference components of the signal. In some such examples, the baseband down-conversion mixer provides this amplification without inductors, which tend to have a large layout footprint. The baseband down-conversion mixer allows peak detection of the signal to be performed in the intermediate frequency domain (e.g., baseband domain) rather than the radio frequency domain, which may allow for simpler peak detector circuitry because the frequencies are lower and the range of frequencies of interest is smaller in the intermediate frequency domain. In these examples and others, the receiver demonstrates greater signal sensitivity using the same or reduced power and area despite the addition of the control path stages.

Of course, these advantages are merely examples, and no advantage is required for any particular embodiment.

Examples of an integrated circuit device with a receiver chain are described with reference to the figures below. In that regard, <FIG> is a circuit diagram of a receiver chain <NUM> of a receiver according to some aspects of this description.

The receiver chain <NUM> may be part of a wireless transceiver and may receive an input signal 102A via an antenna <NUM>. In further embodiments, the receiver chain <NUM> is part of a wired transceiver (e.g., optical transceiver, Ethernet transceiver) and receives the input signal 102A via a receiver element such as a photodiode or via a direct electrical connection with a transmitter.

The input signal 102A may be a differential or single-ended signal and may include a data-bearing portion occurring at one or more specified frequencies or frequency ranges. The input signal 102A may also include interference components at other frequencies. These interference components may include data-bearing emissions intended for other receivers and/or general background noise. Interference components near in frequency to the data-bearing portion may be referred to as interferers or blockers.

The receiver chain <NUM> may include two parallel signal paths of the receiver chain, a main receiver path <NUM> and a control path <NUM>. The main receiver path <NUM> may process the received signal to extract data from the data-bearing portion. This may include filtering by one or more stages to remove interference and extract the data-bearing portion. In contrast, the control path <NUM> may preserve at least some portion of the interference for use in setting the gain and/or other operating parameters of the stages of the main receiver path <NUM>.

The main receiver path <NUM> is described first, and includes an amplifier stage <NUM> coupled to the antenna <NUM>. The input signal 102A, including the data-bearing portion and any interference, is received by an input of the amplifier stage <NUM>. The amplifier stage <NUM> may include any suitable amplifier circuits, and in some examples, the amplifier stage <NUM> includes a low-noise amplifier (LNA) or similar amplifier. The amplifier stage <NUM> amplifies the input signal 102A according to a set of operating parameters (e.g., a gain value, a frequency response curve, and/or other operating parameters) provided by an AGC circuit <NUM> via a set of AGC control signals <NUM> at control inputs of the amplifier stage <NUM>. The amplifier stage <NUM> provides the amplified input signal 102A as amplified signal 102B. The amplifier stage <NUM> may be configured to remove some of the interference from the input signal 102A through filtering or control of the amplifier's frequency response curve. However, significant interference, particularly in frequencies around the frequency of the data-bearing portion of the signal, may be present in the amplified signal 102B.

The amplifier stage <NUM> may provide the amplified signal 102B to the rest of the main receiver path <NUM> as well as the control path <NUM>. In the main receiver path <NUM>, a first mixer stage <NUM> coupled to the amplifier stage <NUM> receives the radio-frequency amplified signal 102B and converts it into a first intermediate frequency signal 102C. The first mixer stage <NUM> may include a baseband down-conversion mixer that mixes the radio-frequency amplified signal 102B with a fixed-amplitude signal (e.g., a square wave signal, a sinusoidal signal, etc.) at a carrier frequency produced by a local oscillator (LO) <NUM>. The first mixer stage <NUM> may also include baseband filters (e.g., low-pass filters) coupled to the down-conversion mixer that remove aliases from the output signal of the down-conversion mixer to produce the first intermediate frequency signal 102C. Operating parameters of the first mixer stage <NUM>, such as the gain, the frequency response curve(s), and/or other parameters, may be controlled by the AGC control signals <NUM> of the AGC circuit <NUM>, which are received at control inputs of the mixer stage <NUM>.

The down-mixing and the filtering of the first mixer stage <NUM> may remove some of the interference from the first intermediate frequency signal 102C, and to the extent that any interference remains, the main receiver path <NUM> may include one or more filter stages <NUM> coupled to the first mixer stage <NUM> that receive the first intermediate frequency signal 102C from the first mixer stage <NUM> and produce filtered signal 102D. Operating parameters of the filter stages <NUM> including the frequency response curve(s) may be controlled by the AGC control signals <NUM> of the AGC circuit <NUM>, which are received at control inputs of the filter stages <NUM>.

The main receiver path <NUM> includes a first analog-to-digital converter (ADC) stage <NUM> coupled to the filter stages <NUM> to receive the filtered signal 102D from the filter stages <NUM>. The first ADC stage <NUM> may convert voltages of the filtered signal 102D into a digital representation of the filtered signal 102D to produce a digital output signal 102E. The digital output signal 102E may be provided to a remainder of the receiver for further signal processing including extracting data encoded in the digital output signal 102E.

The ADC stage <NUM> may also provide a first feedback signal <NUM> to an input of the AGC circuit <NUM>. The first feedback signal <NUM> corresponds to the signal strength of the filtered signal 102D and/or digital output signal 102E, and thus corresponds to the signal strength of the data-bearing portion of the received input signal 102A. In some examples, the first feedback signal <NUM> corresponds to a peak value of the data-bearing portion of the input signal 102A within an interval of time. In some examples, the first feedback signal <NUM> corresponds to an average of the data-bearing portion of the input signal 102A over an interval of time. In further examples, the first feedback signal <NUM> includes other representations of signal strength.

The AGC circuit <NUM> uses the first feedback signal <NUM> to provide operating parameters to stages of the main receiver path <NUM>, such as the amplifier stage <NUM>, the first mixer stage <NUM>, the filter stage <NUM>, etc., via the AGC control signals <NUM>. For example, the AGC circuit <NUM> may increase the gain of these stages when the first feedback signal <NUM> indicates that the signal strength is low, and decrease the gain of these stages when the first feedback signal <NUM> indicates that the signal strength is high.

Elements of the main receiver path <NUM>, such as the filter stage <NUM>, may remove most or all of the interference from the filtered signal 102D before reaching the first ADC stage <NUM>. Accordingly, the first feedback signal <NUM>, which is based on the filtered signal 102D, may represent primarily the data-bearing portion of the input signal 102A without the interference. So that the AGC circuit <NUM> may also consider the interference component, the control path <NUM> may be configured to process the received signal (e.g., amplified signal 102B) in a manner that preserves at least a portion of the interference.

In some examples, the control path <NUM> includes a second mixer stage <NUM> coupled to the amplifier stage <NUM> in parallel with the first mixer stage <NUM>. Similar to the first mixer stage <NUM>, the second mixer stage <NUM> receives the amplified signal 102B and may include a baseband down-conversion mixer that mixes the radio-frequency amplified signal 102B with a signal at the carrier frequency produced by an LO <NUM>. The second mixer stage <NUM> may also include baseband filters (e.g., low-pass filters) coupled to the down-conversion mixer that filter the output signal of the down-conversion mixer to produce a second intermediate frequency signal 102F.

In contrast to the first mixer stage <NUM>, the filters and/or down-conversion mixer of the second mixer stage <NUM> may be configured to have a wider bandwidth so that interference components that are absent or reduced in signal 102C are present in the second intermediate frequency signal 102F. In some examples, the second mixer stage <NUM> has a bandwidth of about <NUM>. The second mixer stage <NUM> may also have greater amplification than the first mixer stage <NUM> to increase the sensitivity to the interference components. In some such examples, the second mixer stage <NUM> has a gain of about <NUM> dB, although any suitable gain may be used. In some examples, such as those described in subsequent figures, the second mixer stage <NUM> achieves this gain without the use of inductors, which may otherwise consume a significant amount of circuit area.

The control path <NUM> further includes a peak detector <NUM> coupled to the second mixer stage <NUM> to receive the second intermediate frequency signal 102F. The peak detector <NUM> may produce a peak signal <NUM> with a voltage representing a peak voltage of the second intermediate frequency signal 102F over a window of time. In an example, the peak detector <NUM> includes a diode <NUM> with an input coupled to receive signal 102F and an output coupled to produce signal <NUM> and a capacitor <NUM> coupled between the output of the diode <NUM> and ground. Further examples of the peak detector <NUM> are described in more detail below.

Arranging the peak detector <NUM> after the second mixer stage <NUM> may simplify the structure of the peak detector <NUM> because of the baseband conversion. In some examples, because the relevant frequencies are lower in the intermediate frequency domain, the highfrequency response of the peak detector <NUM> becomes less relevant, and in turn, the complexity and sensitivity of peak detector <NUM> may be reduced. Similarly, in some examples, because the range of relevant frequencies is smaller in the intermediate frequency domain, the complexity and sensitivity of peak detector <NUM> may be further reduced. The peak detector <NUM> may also benefit from the amplification provided by the second mixer stage <NUM> and/or the amplifier stage <NUM>, which may amplify the interference and allow detection even if sensitivity of the peak detector <NUM> is reduced.

A second ADC stage <NUM> is coupled to the peak detector <NUM> and receives the peak signal <NUM>. The second ADC stage <NUM> produces a second feedback signal <NUM> with a digital value representing voltage of the peak signal <NUM> relative to a threshold voltage VThres. In this way, the second feedback signal <NUM> has a voltage proportional to the strength of the data-bearing portion and the interference components of the input signal 102A. As with the first feedback signal <NUM>, the second feedback signal <NUM> may correspond to a peak measurement, an average measurement, and/or any other suitable measurement of signal strength.

The AGC circuit <NUM> is coupled to the second ADC stage <NUM> and receives the second feedback signal <NUM> from the second ADC stage <NUM>. Accordingly, the AGC circuit <NUM> considers both the first feedback signal <NUM> and the second feedback signal <NUM> when determining the operating parameters (e.g., gain settings, frequency responses, and/or other operating parameters) of the stages of the main receiver path <NUM> (e.g., the amplifier stage <NUM>, the first mixer stage <NUM>, the filter stage <NUM>, etc.) provided via the AGC control signals <NUM>.

In an example, the AGC circuit <NUM> increases the gain of the stages of the main receiver path <NUM> when the first feedback signal <NUM> indicates the signal strength of the data-bearing portion of the input signal 102A is low, and decreases the gain when the first feedback signal <NUM> indicates that the signal strength of the data-bearing portion is high. The example AGC circuit <NUM> limits the maximum gain of the stages of the main receiver path <NUM> based on the second feedback signal <NUM> so that the signal strength of the combined interference and data-bearing portion represented by the second feedback signal <NUM> will not cause signal saturation. In particular, the AGC circuit <NUM> may apply a greater gain to low- or medium-noise signals than otherwise possible because the amount of interference is determined and considered instead of using a conservative interference guardband. In turn, this greater amplification may allow the receiver chain <NUM> to successfully extract data from weaker signals.

Further examples of a receiver chain <NUM> are described with reference to <FIG>, which is a circuit diagram of a receiver chain <NUM> of a receiver according to some aspects of this description. In many aspects, the receiver chain <NUM> is substantially similar to receiver chain <NUM>. For example, the receiver chain <NUM> includes a main receiver path <NUM> that includes an amplifier stage <NUM>, a first mixer stage <NUM>, filter stages <NUM>, and a first ADC stage <NUM> similar to those of <FIG>. The receiver chain <NUM> also includes an AGC circuit <NUM> substantially similar to that of <FIG>.

In contrast, the control path <NUM> of the receiver chain <NUM> receives the input signal 102A from the antenna <NUM> directly rather than receiving the amplified signal 102B. Otherwise, operation of the control path <NUM> is similar. The control path <NUM> includes a second mixer stage <NUM> that is coupled to the antenna <NUM> and receives the input signal 102A. Similar to second mixer stage <NUM>, second mixer stage <NUM> may include a baseband down-conversion mixer that mixes the radio-frequency input signal 102A with a signal at the carrier frequency produced by an LO <NUM>. The second mixer stage <NUM> may also include baseband filters (e.g., low-pass filters) coupled to the down-conversion mixer that filter the output signal of the down-conversion mixer to produce a second intermediate frequency signal 102F.

The filters and/or downmixer of the second mixer stage <NUM> may be configured to have a wider bandwidth than the first mixer stage <NUM>, so that interference components that are absent or reduced in signal 102C are present in the second intermediate frequency signal 102F.

The control path <NUM> further includes a peak detector <NUM> (including a diode <NUM> and a capacitor <NUM>) and a second ADC stage <NUM> that produces a second feedback signal <NUM> substantially as described above.

Examples of a mixer stage suitable for use in the second mixer stage <NUM> and/or <NUM> of the control path <NUM> are described with reference to <FIG>. In that regard, <FIG> is a circuit diagram of a mixer stage <NUM> according to some aspects of this description.

The mixer stage <NUM> is configured to receive an input signal (e.g., amplified signal 102B) as a differential pair of signals VinP <NUM> and VinM <NUM>. Signal VinP <NUM> is coupled to a gate of a first transistor <NUM>, and signal VinM <NUM> is coupled to a gate of a second transistor <NUM>.

The mixer stage <NUM> is also configured to receive a signal (e.g., a square wave signal, a sinusoidal signal, etc.) at a carrier frequency from an LO <NUM> as a differential pair of signals LO <NUM> and LO <NUM>. Signal LO <NUM> is coupled to a gate of a third transistor <NUM>. Signal LO <NUM> is coupled to a gate of a fourth transistor <NUM> and a gate of a fifth transistor <NUM>. Signal LO <NUM> is also coupled to a gate of a sixth transistor <NUM>.

The source of the first transistor <NUM> is coupled to a ground node, and the drain of the first transistor <NUM> is coupled to sources of the third transistor <NUM> and the fourth transistor <NUM>. Similarly, the source of the second transistor <NUM> is coupled to the ground node, and the drain of the second transistor <NUM> is coupled to sources of the fifth transistor <NUM> and the sixth transistor <NUM>.

The mixer stage <NUM> is configured to produce an intermediate frequency signal (e.g., second intermediate frequency signal 102F) as a differential pair of signals VoutP <NUM> and VoutM <NUM>. The VoutM node <NUM> is coupled to drains of the third transistor <NUM> and the fifth transistor <NUM>, and a first resistor <NUM> is coupled between a voltage source and the VoutM node <NUM>. The VoutP node <NUM> is coupled to drains of the fourth transistor <NUM> and the sixth transistor <NUM>, and a second resistor <NUM> is coupled between the voltage source and the VoutP node <NUM>.

In some examples, the mixer stage <NUM> includes current helper transistors <NUM> and <NUM> coupled in parallel with the first resistor <NUM> and the second resistor <NUM>, respectively. In some such examples, sources of the first current helper transistor <NUM> and the second current helper transistor <NUM> are coupled to the voltage source, and gates of the first current helper transistor <NUM> and the second current helper transistor <NUM> are coupled to a bias voltage VBias <NUM>. A drain of the first current helper transistor <NUM> is coupled to the VoutM node <NUM>, and a drain of the second current helper transistor <NUM> is coupled to the VoutP node <NUM>.

Mixer stage <NUM> is merely one example of a suitable circuit for the second mixer stages <NUM> and <NUM>, and other suitable circuits are contemplated and provided for.

Examples of a peak detector <NUM> suitable for use in the peak detector <NUM> of the control path <NUM> are described with reference to <FIG>. In that regard, <FIG> is a circuit diagram of a peak detector <NUM> according to some aspects of this description.

In some examples, the peak detector <NUM> is configured to operate on a differential signal pair and includes a main peak detector subunit <NUM> to produce a first signal of the differential signal pair (VoP <NUM>) and a replica peak detector subunit <NUM> to produce a second signal of the differential signal pair (VoM <NUM>).

The main peak detector subunit <NUM> may receive an input signal (e.g., second intermediate frequency signal 102F) as a differential pair of signals VoutP <NUM> and VoutM <NUM>. Signal VoutP <NUM> is coupled to a gate of a first transistor <NUM>, and signal VoutM <NUM> is coupled to a gate of a second transistor <NUM>. The drains of the first transistor <NUM> and the second transistor <NUM> are coupled to a voltage source, and the sources of the first transistor <NUM> and the second transistor <NUM> are coupled to a first node <NUM>.

The main peak detector subunit <NUM> includes a first current source <NUM> and a first capacitor <NUM> coupled in parallel between the first node <NUM> and a ground node. A first resistor <NUM> is coupled between the first node <NUM> and a node associated with the first output signal, VoP <NUM>. A second capacitor <NUM> is coupled between the VoP node <NUM> and the ground node.

The replica peak detector subunit <NUM> is similar to the main peak detector subunit <NUM> and may be used to correct a DC offset. The main peak detector subunit <NUM> is configured to receive a common mode voltage VBias <NUM> that is provided to a gate of a third transistor <NUM> and a gate of a fourth transistor <NUM>. The drains of the third transistor <NUM> and the fourth transistor <NUM> are coupled to the voltage source, and the sources of the third transistor <NUM> and the fourth transistor <NUM> are coupled to a second node <NUM>.

The replica peak detector subunit <NUM> includes a second current source <NUM> and a third capacitor <NUM> coupled in parallel between the second node <NUM> and the ground node. A second resistor <NUM> is coupled between the second node <NUM> and a node associated with the second output signal, VoM <NUM>. A fourth capacitor <NUM> is coupled between the node associated with VoM <NUM> and the ground node.

Peak detector <NUM> is merely one example of a suitable circuit for the peak detector <NUM>, and other suitable circuits are contemplated and provided for.

Operation of the receiver is further described with reference to <FIG> and <FIG> is a flow diagram of a method <NUM> of performing gain control in a receiver chain according to some aspects of this description. The method <NUM> is suitable for performing by the receiver chain <NUM> of <FIG> or other suitable integrated circuit. Processes of the method <NUM> may be performed in orders other than described, and processes may be performed concurrently in parallel. Furthermore, processes of the method <NUM> may be omitted or substituted in some examples of this description.

Referring to block <NUM>, the receiver chain <NUM> receives an input signal 102A. The input signal 102A may be received via an antenna <NUM>, a photodiode, another receiver element, direct electrical connection, and/or any other suitable receiving mechanism.

Referring to block <NUM>, an amplifier stage <NUM> of the receiver chain <NUM> receives the input signal 102A, amplifies the input signal 102A according to a set of operating parameters, and provides it as an amplified signal 102B.

Referring to block <NUM>, a first mixer stage <NUM> of the receiver chain <NUM> receives the amplified signal 102B and performs a baseband conversion to convert the amplified signal 102B into a first intermediate frequency signal 102C. Parameters of the baseband conversion such as the gain and/or frequency response may be determined by the set of operating parameters.

Referring to block <NUM>, a filter stage <NUM> of the receiver chain <NUM> filters the first intermediate frequency signal 102C to remove interference while preserving a data-bearing portion of the signal, which is provided as a filtered signal 102D. The frequency response and/or other operating parameters of the filter stage <NUM> may be determined by the set of operating parameters.

Referring to block <NUM>, a first ADC stage <NUM> of the receiver chain <NUM> receives the filtered signal 102D and digitizes the signal to produce a digital output signal 102E. Referring to block <NUM>, the first ADC stage <NUM> also provides a first feedback signal <NUM> to an AGC circuit <NUM>. The first feedback signal <NUM> corresponds to a signal strength of a data-bearing portion of the received input signal 102A.

Referring to block <NUM>, a second mixer stage <NUM> of the receiver chain <NUM> also receives the amplified signal 102B and performs a baseband conversion to convert the amplified signal 102B into a second intermediate frequency signal 102F. Additionally or in the alternative, the second mixer stage receives the input signal 102A directly and performs a baseband conversion to convert the input signal 102A into the second intermediate frequency signal 102F. In either example, in contrast to the conversion of block <NUM> and/or the filtering of block <NUM>, the conversion of block <NUM> may be configured to preserve interference in the second intermediate frequency signal 102F. Accordingly, the second intermediate frequency signal 102F may include interference components that are removed by the conversion of block <NUM> or the filtering of block <NUM>. For example, the baseband conversion of block <NUM> may be performed using a mixer stage with greater bandwidth than that used in block <NUM>. In some examples, the baseband conversion of block <NUM> includes applying a gain to the amplified signal 102B to increase the strength of the interference in the second intermediate frequency signal 102F.

Referring to block <NUM>, a peak detector <NUM> receives the second intermediate frequency signal 102F and provides a peak signal <NUM> with a voltage corresponding to a peak of the second intermediate frequency signal 102F.

Referring to block <NUM>, a second ADC stage <NUM> of the receiver chain <NUM> receives the peak signal <NUM> and digitizes the signal to produce a second feedback signal <NUM>. The second feedback signal <NUM> corresponds to a signal strength of both the data-bearing portion of the received input signal 102A and one or more interference components of the received input signal 102A.

Referring to block <NUM>, an AGC circuit <NUM> modifies the set of operating parameters of the receiver chain <NUM> based on the first feedback signal <NUM> and the second feedback signal <NUM>. In some examples, this includes the AGC circuit <NUM> increasing gain of the receiver chain <NUM> when the first feedback signal <NUM> indicates that the signal strength of a data-bearing portion of the received input signal 102A up to a maximum gain determined based on the second feedback signal <NUM> to avoid signal saturation.

The receiver chain <NUM> or other integrated circuit device may perform the processes of the method <NUM> using any combination of dedicated hardware and instructions stored in a non-transitory medium. Accordingly, elements of the receiver chain <NUM>, such as the AGC circuit <NUM>, may include a processing resource coupled to a non-transitory computer-readable medium. The processing resource may include one or more microcontrollers, ASICs, CPUs, GPUs, and/or other processing resources configured to execute instructions stored on the medium. Examples of suitable non-transitory computer-readable media include one or more flash memory devices, battery-backed RAM, SSDs, HDDs, optical media, and/or other memory devices suitable for storing the instructions for the processing resource.

Claim 1:
An integrated circuit device comprising:
an amplifier stage (<NUM>) configured to receive an input signal (102A) and a control signal (<NUM>) and to provide an amplified signal (102B) in response to the input signal and the control signal;
a main path coupled to the amplifier stage that is configured to receive the amplified signal and to provide a first feedback signal (<NUM>) corresponding to a signal strength of a data-bearing portion of the input signal;
a control path (<NUM>) coupled to the amplifier stage that is configured to receive the amplified signal and to provide a second feedback signal (<NUM>) corresponding to a signal strength of the data-bearing portion and an interference component of the input signal; and
a gain control circuit (<NUM>) coupled to the main path and the control path that is configured to receive the first feedback signal and the second feedback signal and to provide the control signal in response to the first feedback signal and the second feedback signal, wherein
the main path includes a first mixer stage (<NUM>) coupled to the amplifier stage that is configured to receive the amplified signal and to provide a first intermediate frequency signal (102C) in response to the amplified signal; and
the first feedback signal is in response to the first intermediate frequency signal,
wherein
the control path includes a second mixer stage (<NUM>) coupled to the amplifier stage that is configured to receive the amplified signal and to provide a second intermediate frequency signal (102F) in response to the amplified signal;
wherein the second mixer stage is configured to preserve the interference component of the input signal, and
wherein:
the control path further includes a peak detector (<NUM>) coupled to the second mixer stage that is configured to receive the second intermediate frequency signal and to provide a peak signal (<NUM>) in response to the second intermediate frequency signal; and
the second feedback signal is in response to the peak signal.