Patent Description:
A multiphase power converter commonly includes interleaved PFC boost subconverters and a control circuit for controlling power switches in the subconverters. In some examples, the control circuit may control duty cycles of the power switches to balance rail currents in the subconverters. In such examples, the rail currents may be balanced by employing a split boost inductor, multiple current sensors, and/or multiple current compensators for balancing rail currents. In other examples, the power converter's input voltage and current may be sampled multiple times per cycle, and the control circuit's current compensator may be executed multiple times per cycle to adjust the duty cycles to balance the rail currents. <CIT> as well as <CIT> discloses a control device for a switching converter.

The dependent claims recite advantageous embodiments.

Further aspects and areas of applicability will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the invention which is defined by the independent claims.

Corresponding reference numerals indicate corresponding (but not necessarily identical) parts and/or features throughout the several views of the drawings.

These terms may be only used to distinguish one element, component, region, layer or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the example embodiments.

An interleaved multiphase switching power converter according to one example embodiment of the present disclosure is illustrated in <FIG> and indicated generally by reference number <NUM>. As shown in <FIG>, the interleaved multiphase switching power converter <NUM> includes phase-shifted subconverters <NUM>, <NUM> having power switches <NUM>, <NUM>, and a control circuit <NUM> coupled to the subconverters <NUM>, <NUM> for controlling the power switches <NUM>, <NUM> to balance currents in the subconverters <NUM>, <NUM> over multiple periods. The control circuit <NUM> includes a current compensator <NUM> configured to determine a duty cycle D1 multiple times over the multiple periods based on a reference signal Iref and a sensed current Isense in the switching power converter <NUM>, generate a PWM control signal <NUM> having a present value of the duty cycle D1 for controlling the power switch <NUM> of the subconverter <NUM> during a period of the multiple periods, determine another duty cycle D2 based on the present value of the duty cycle D1 and a previous value of the duty cycle D1, and generate a PWM control signal <NUM> having the duty cycle D2 for controlling the power switch <NUM> of the subconverter <NUM> during the period.

The control circuit <NUM> employs an interpolation-based control for balancing rail currents in the subconverters <NUM>, <NUM> when the subconverters are operated with average current mode control. For example, the control circuit <NUM> determines the duty cycle D2 for controlling the subconverter <NUM> based on known values of the duty cycle D1. In such examples, the interpolation-based control mitigates current imbalances between the subconverter <NUM> (e.g., a master subconverter) and the subconverter <NUM> (e.g., a slave subconverter) caused by, for example, control signal delays, control peripheral delays, differing inductance values in the subconverters <NUM>, <NUM>, mismatched PCB traces in the subconverters <NUM>, <NUM>, etc. As such, rail currents in the subconverters <NUM>, <NUM> may be phase synchronized, and have a similar wave shape and amplitude. By balancing rail currents in the subconverters <NUM>, <NUM>, heat may be spread and dissipated evenly in the power switches <NUM>, <NUM> while effectively reducing ripple current by a factor inversely proportional to number of subconverters.

Conventionally, duty cycles of control signals for controlling different subconverters are updated based on the same current and voltage values. For example, in average current mode, the duty cycles of the control signals are computed based on an error between a current reference (e.g., Iref(t)) and a sensed current (e.g., an input current Iint(t)), both changing over time. The current reference Iref(t) is greatly influenced by the input voltage V(t). For example, <FIG> illustrates a graph <NUM> showing duty cycles <NUM>, <NUM> for two subconverters employing conventional control techniques and the input voltage V over multiple periodic cycles. In this example, PWM modules for generating PWM control signals operate with a <NUM>-degree phase shift φ. As shown in <FIG>, an increasing input voltage V(t) (e.g., during the upward AC slope of the input voltage) results in decreasing duty cycle values (u). The duty cycle values continue to decrease until the input voltage V(t) reaches a peak voltage value. During the downward AC slope of the input voltage (not shown in <FIG>), the duty cycle values increase until the input voltage V(t) reaches a minimum voltage value.

A compensator updates the duty cycle values (u) for the subconverters based on the same input voltage V(t) one time per cycle T. As such, when the compensator updates the duty cycle values (u), the duty cycle value <NUM> for one subconverter is shifted and overcompensated relative to the duty cycle value <NUM> for the other subconverter. For example, and as shown in <FIG>, the duty cycle values <NUM>, <NUM> take different paths because the input voltage V changes while the updated duty cycle values (u) remain the same through each cycle T. As a result, one subconverter may store more energy than the other subconverter thereby causing an imbalance between rail currents (e.g., inductor currents) in the subconverters.

For example, <FIG>, <FIG>, and <FIG> illustrate graphs <NUM>, <NUM>, 500A, 500B, 500C of duty cycle values <NUM>, <NUM> and rail currents <NUM>, <NUM> in two subconverters of a power converter employing conventional control techniques. Specifically, the graph <NUM> illustrates the duty cycle values <NUM>, <NUM> over time when an input voltage of the power converter is in its upward slope of one AC cycle, and the graph <NUM> illustrates the rail currents <NUM>, <NUM> over two AC cycles. The graphs 500A, 500B, 500C show enlarged portions of the rail currents <NUM>, <NUM> of <FIG> during a start of a positive cycle (see <FIG>), at positive peak values (see <FIG>), and at negative peak values (see <FIG>). In this example, the power converter may be a two-phase interleaved totem pole PFC operating at <NUM>.

As shown in <FIG>, the duty cycle value <NUM> for one of the subconverters is shifted and overcompensated relative to the duty cycle value <NUM> for the other subconverter. This causes an imbalance between the rail currents <NUM>, <NUM> (e.g., inductor currents) in the subconverters as shown in <FIG> and <FIG>.

However, and as further explained below, if the interpolation-based control methods are employed as disclosed herein, one of the duty cycles may be corrected to ensure the duty cycles track along the same path. As a result, balanced rail currents in the subconverters may be achieved.

The control circuit <NUM> of <FIG> may include various components for generating duty cycles to achieve balanced rail currents in the subconverters <NUM>, <NUM>. For example, <FIG> illustrates a current compensator <NUM> employable in the control circuit <NUM> for determining values of the duty cycles D1, D2 to balance rail currents in the subconverters <NUM>, <NUM> over multiple periods (e.g., cycles). As shown in <FIG>, the current compensator <NUM> includes comparators <NUM>, <NUM>, a controller <NUM>, limiters <NUM>, <NUM>, a delay device <NUM>, a multiplier <NUM>, an adder <NUM>, and PWM modules DPWM1, DPWM2.

In the example of <FIG>, the current compensator <NUM> receives a current reference signal Iref and a sensed current Isense (e.g., an input current of the switching power converter <NUM> of <FIG>). The current reference signal Iref may change from one periodic cycle to the next periodic cycle due to, for example, an input voltage of the switching power converter changing over time. The comparator <NUM> compares the current reference signal Iref and the sensed current Isense during one periodic cycle, and generates a current error signal err_i based on the comparison (e.g., difference) between the current reference signal Iref and the sensed current Isense.

The controller <NUM> then generates a signal u(t) representing the duty cycle D1 for the periodic cycle based on the current error signal err_i. The signal u(t) is passed through the limiter <NUM> to limit the value of the signal u(t). In such examples, when the signal u(t) is less than a defined value, the signal u(t) may be forced to that defined value. If, however, the signal u(t) is greater than another defined value, the signal u(t) may be forced to the other defined value. The PWM module DPWM1 then generates a control signal PWM1 having a present value u(t) of the duty cycle D1 for controlling one or more power switches in a subconverter (e.g., the subconverter <NUM> of <FIG>) during the periodic cycle.

The controller <NUM> of <FIG> is shown as including a proportional- integral (Pl) controller. In such examples, the controller <NUM> may include one or more amplifiers for multiplying the current error signal err_i with a proportional gain coefficient and an integrator coefficient. In other examples, the controller <NUM> may include another suitable type of controller such as a proportional- integral-derivative (PID) controller.

As shown in <FIG>, the comparator <NUM> compares the present value u(t) and a previous value u(t-<NUM>) of the duty cycle D1, and generates an error signal err based on the comparison (e.g., the difference) between the values. For example, and as shown in <FIG>, the present value u(t) of the duty cycle D1 is passed through the delay device <NUM> to obtain the previous value u(t- <NUM>) of the duty cycle D1 from the previous periodic cycle.

The multiplier <NUM> receives the error signal err and a reference signal C1, and generates a signal based on the product of the error signal err and the reference signal C1. For example, the reference signal C1 may be a defined constant value based on a phase delay between the subconverters (e.g., the subconverters <NUM>, <NUM>) and the periodic cycle. For instance, if the switching power converters include two interleaved subconverters, the phase delay between one subconverter and the other subconverter is <NUM> degrees, and the periodic cycle is <NUM> degrees. In such examples, the reference signal C1 may be obtained by dividing the phase delay (e.g., <NUM> degrees) by the cycle (e.g., <NUM> degrees).

The adder <NUM> then adds the signal provided by the multiplier <NUM> and the present value u(t) of the duty cycle D1 to determine the duty cycle D2. For example, a signal u(t)' representing a present value of the duty cycle D2 is provided by the adder <NUM> and passed through the limiter <NUM>, which functions in a similar manner as the limiter <NUM>. The signal u(t)' representing the present value of the duty cycle D2 is then passed to the PWM module DPWM2. The PWM module DPWM2 generates a control signal PWM2 having the present value u(t)' of the duty cycle D2 for controlling one or more power switches in another subconverter (e.g., the subconverter <NUM> of <FIG>) during the periodic cycle. The computations for determining the value of the signal u(t)' are shown in equation (<NUM>) below.

The values of the signal u(t), u(t)' are time referenced. As such, the values of the signals u(t), u(t)' may be valid within one PWM period (e.g., one cycle). The signal values may be determined again in a similar manner as explained above for previous and/or subsequent PWM periods.

When the value of the signal u(t)' for the duty cycle D2 is determined as explained above, the duty cycles D1, D2 may track along the same path thereby forcing rail currents in the subconverters to balance. For example, <FIG> illustrates a graph <NUM> showing duty cycle values D1, D2 for two subconverters when using the current compensator <NUM> of <FIG>. As shown in <FIG>, the duty cycle values D1, D2 track along a similar path as the input voltage V changes.

In the particular example of <FIG>, the duty cycle D2 is corrected by half the error of the present value u(t) and the previous value u(t-<NUM>) of the duty cycle D1. As a result, the duty cycle D2 is computed to match the midpoint of the present value u(t) and a future value u(t+<NUM>) of the duty cycle D1. For example, if the input voltage is <NUM> volts at the previous cycle (e.g., V(t-<NUM>)), <NUM> volts at the present cycle (e.g., V(t)), and <NUM> volts at the future cycle (e.g., V(t+<NUM>)), the input voltage is <NUM> volts (e.g., V(t+<NUM>)) when the duty cycle D2 is computed to match the midpoint (e.g., u(t+<NUM>)) of the present value u(t) and the future value u(t+<NUM>) of the duty cycle D1.

As a result of the duty cycles D1, D2 tracking along a similar path, power switches may be controlled to achieve balanced current in the subconverters. For example, <FIG>, <FIG> and <FIG> illustrate graphs <NUM>, <NUM>, 1000A, 1000B, 1000C showing duty cycle values <NUM>, <NUM> and rail currents 1a, 1b in two subconverters of a power converter employing the interpolation-based control methods disclosed herein. Specifically, the graph <NUM> illustrates the duty cycle values <NUM>, <NUM> over time when an input voltage of the power converter is in its upward slope of one AC cycle, and the graph <NUM> illustrates the rail currents 1a, 1b (e.g., inductor currents) over two AC cycles. The graphs 1000a, 1000b, 1000c show enlarged portions of the rail currents 1a, 1b of <FIG> during a start of a positive cycle (see <FIG>), at positive peak values (see <FIG>), and at negative peak values (see <FIG>). In this example, the power converter may be a two-phase interleaved totem pole PFC operating at <NUM>.

As shown in <FIG>, the duty cycle values <NUM>, <NUM> track along a similar path. As a result, the rail current 1a flowing through one of the subconverters (e.g., the subconverter <NUM> of <FIG>) and the rail current 1b flowing through the other subconverter (e.g., the subconverter <NUM> of <FIG>) are balanced, as shown in <FIG> and <FIG>. Specifically, the rail currents 1a, 1b are phase synchronized, and have a similar wave shape and amplitude.

Although <FIG> and <FIG> relate to interpolation-based control methods for controlling two interleaved subconverters in a power converter, it should be apparent that the methods may be used to control more than two interleaved subconverters. For example, <FIG> illustrates a current compensator <NUM> employable for determining duty cycles D1, D2, D3 for balancing rail currents in the three subconverters. The current compensator <NUM> of <FIG> is substantially similar to the current compensator <NUM> of <FIG>, but includes another control loop for generating the duty cycle D3 for the third subconverter. For example, the current compensator <NUM> of <FIG> includes the comparators <NUM>, <NUM>, the controller <NUM>, the limiters <NUM>, <NUM>, the delay device <NUM>, the multiplier <NUM>, the adder <NUM>, and the PWM modules DPWM1, DPWM2 of <FIG>, and a multiplier <NUM>, an adder <NUM>, a limiter <NUM> and a PWM module DPWM3.

The duty cycles D1, D2 are determined in the same manner as described above relative to <FIG>. For example, during one periodic cycle, the duty cycle D1 (e.g., the signal u(t) representing the present value of the duty cycle D1) is determined based on current values of the reference signal Iref and the sensed current Isense, and the duty cycle D2 (e.g., the signal u(t)' representing the present value of the duty cycle D2) is determined based on the present value u(t) and the previous value u(t-<NUM>) of the duty cycle D1 as explained above.

In the example of <FIG>, the multiplier <NUM> receives the error signal err from the comparator <NUM> and a reference signal C1, and generates a signal based on the product of the error signal err and the reference signal C1 as explained above. In the particular example of <FIG>, the reference signal C1 is altered as compared to the reference signal C1 of <FIG>. Specifically, the reference signal C1 of <FIG> is determined by dividing a phase delay between the first subconverter (e.g., a master subconverter) and the second subconverter (e.g., a slave subconverter) and the cycle (e.g., <NUM> degrees). In such examples, the phase delay between the first subconverter and the second subconverter is <NUM> degrees. Thus, in the particular example of <FIG>, the reference signal C1 is <NUM> (e.g., <NUM> I <NUM>).

Similar to the duty cycle D2, the duty cycle D3 for the third subconverter is determined based on the present value u(t) and the previous value u(t-<NUM>) of the duty cycle D1. For example, and as shown in <FIG>, the multiplier <NUM> receives the error signal err from the comparator <NUM> and a reference signal C2, and generates a signal based on the product of the error signal err and the reference signal C2.

The reference signal C2 may be a defined constant value determined in a similar manner as the reference signal C1. For example, the reference signal C2 may be determined based on a phase delay between the first subconverter (e.g., the master subconverter) and the third subconverter (e.g., a slave subconverter) and the cycle. In such examples, the phase delay between the first subconverter and the third subconverter is <NUM> degrees. As such, the reference signal C2 may be obtained by dividing the phase delay (e.g., <NUM> degrees) by the cycle (e.g., <NUM> degrees). Thus, in the particular example of <FIG>, the reference signal C2 is <NUM> (e.g., <NUM> degrees / <NUM> degrees).

The adder <NUM> then adds the signal provided by the multiplier <NUM> and the present value u(t) of the duty cycle D1 to determine a present value (e.g., a signal u(t)") of the duty cycle D3. The signal u(t)" representing the present value of the duty cycle D3 is passed through the limiter <NUM>, which functions in a similar manner as the limiter <NUM> explained above. The signal u(t)" is then passed to the PWM module DPWM3. The PWM module DPWM3 generates a control signal PWM3 having the present value u(t)" of the duty cycle D3 for controlling one or more power switches in the third subconverter during the periodic cycle. The computations for determining the value of the signal u(t)" are shown in equation (<NUM>) below.

In the particular example of <FIG>, the duty cycle D2 is corrected by one third of the error of the present value u(t) and the previous value u(t-<NUM>) of the duty cycle D1 due to the reference signal C1. As a result, the duty cycle D2 is computed to match a point one third of the way between the present value u(t) and a future value u(t+<NUM>) of the duty cycle D1. Additionally, the duty cycle D3 is corrected by two thirds of the error of the present value u(t) and the previous value u(t-<NUM>) of the duty cycle D1 due to the reference signal C2. As such, the duty cycle D3 is computed to match a point two thirds of the way between the present value u(t) and a future value u(t+<NUM>) of the duty cycle D1.

The reference signals Iref disclosed herein may be generated based on an output of a voltage compensator. For example, <FIG> illustrates a control circuit <NUM> for controlling power switches in two subconverters of a switching power converter (e.g., the switching power converter <NUM> of <FIG>) to balance currents over multiple periods. As shown, the control circuit <NUM> includes the current compensator <NUM> of <FIG> and a circuit <NUM> for generating the current reference signal Iref for the current compensator <NUM>.

In the example of <FIG>, the current reference signal Iref is generated based on an input voltage Vin of the switching power converter, an output voltage Vo of the switching power converter, and a reference voltage Vref. For example, and as shown in <FIG>, the circuit <NUM> includes a comparator <NUM>, a multiplier <NUM>, and a power limit function <NUM>. The comparator <NUM> compares the reference voltage Vref and the output voltage Vo, and provides an output to the multiplier <NUM>. The output voltage Vo may pass through an optional zero-order hold (ZOH) device such as a sample and hold (S&H) circuit that samples the output voltage Vo (e.g., an analog signal) and holds its value at a constant level for a period of time (e.g., a sample interval) to generate a digital signal.

In some examples, the comparator <NUM> may represent a voltage compensator. As such, the output of the comparator <NUM> may be an output of the voltage compensator. In such examples, a controller (e.g., similar to the PI controller <NUM> of <FIG>) may be coupled to the comparator <NUM>.

The power limit function <NUM> receives the input voltage Vin of the power converter (e.g., a rectified input voltage), and provides an output to the multiplier <NUM>. For example, the power limit function <NUM> may output a signal representing the inverse of the square of the average input voltage (e.g., <NUM> / (average (Vin)) A <NUM>, <NUM> / Vacrms A <NUM>, etc.). Alternatively, the power limit function <NUM> may output another signal if desired. Similar to the output voltage Vo, the input voltage Vin may pass through an optional ZOH device if desired.

The multiplier <NUM> generates the current reference signal Iref based on the product of the output of the comparator <NUM> (e.g., the output of the voltage compensator), the output of the power limit function <NUM>, and the input voltage Vin of the power converter. The current reference signal Iref is then passed to the comparator <NUM> of the current compensator <NUM>, as explained above.

In the example of <FIG>, the duty cycles of the PWM control signals PWM1, PWM2 may be determined using minimal sensors. For example, the duty cycles may be determined using a single current sensor, a single input voltage sensor, and a single output voltage sensor.

In some examples, the subconverters disclosed herein may include one or more inductors and/or PCB traces. In such examples, differing inductor values and/or PCB traces (e.g., mismatched resistances) may attribute to at least some of the current imbalance between the subconverters. However, if the interpolation-based control methods disclosed herein are employed, rail currents in the subconverters may be substantially balanced in amplitude and phase even with inductor values differing by ±<NUM>% and/or resistance values differing by ±<NUM> milliohms.

For example, <FIG> illustrate graphs 1300A, 1300B 1400A, 1400B, 1500A, 1500B, 1600A, 1600B showing rail currents <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in inductors L1, L2. The inductor L1 may be coupled in a rail of one subconverter (e.g., a master subconverter such as the subconverter <NUM> of <FIG>), and the inductor L2 may be coupled in a rail of another subconverter (e.g., a slave subconverter such as the subconverter <NUM> of <FIG>). The graphs 1300B, 1400B, 1500B, 1600B of <FIG>, <FIG>, <FIG>, <FIG> show enlarged portions of the rail currents <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of <FIG>, <FIG>, <FIG>, <FIG> at their positive peak values. In the examples of <FIG>, the inductors L1, L2 have values differing by <NUM>%. For example, the inductor L2 value is <NUM>% of the inductor L1 value (e.g., L2 = <NUM> * L1) in <FIG> and <FIG>, and the inductor L2 value is <NUM>% of the inductor L1 value (e.g., L2 = <NUM> * L1) in <FIG> and <FIG>.

As shown in <FIG> and <FIG>, the <NUM>% difference in inductance results in an imbalance between the currents <NUM>, <NUM> in the inductor L1 and the currents <NUM>, <NUM> in the inductor L2 when the interpolation control methods are not employed. However, and as shown in <FIG> and <FIG>, if the interpolation control methods are employed, the <NUM>% difference in inductance results in minimal imbalance between the currents <NUM>, <NUM> in the inductor L1 and the currents <NUM>, <NUM> in the inductor L2.

Additionally, <FIG> illustrate graphs 1700A, 1700B, 1800A, 1800B, 1900A, 1900B, 2000A, 2000B showing rail currents <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> flowing through subconverters including resistors R1, R2. In some examples, the rail currents <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may represent inductor currents in the subconverters. The resistor R1 may represent a PCB trace in one subconverter (e.g., a master subconverter such as the subconverter <NUM> of <FIG>), and the resistor R2 may represent a PCB trace in another subconverter (e.g., a slave subconverter such as the subconverter <NUM> of <FIG>). The graphs 1700B, 1800B, 1900B, 2000B of <FIG>, <FIG>, <FIG>, <FIG> show enlarged portions of the rail currents <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of <FIG>, <FIG>, <FIG>, <FIG> at their positive peak values. In the examples of <FIG>, the resistors R1, R2 have values differing by <NUM> milliohms. For example, the resistor R2 value is <NUM> milliohms larger than the resistor R1 value (e.g., R2 = R1 + <NUM> milliohms) in <FIG> and 19A-B, and the resistor R1 value is <NUM> milliohms larger than the resistor R2 value (e.g., R1 = R2 + <NUM> milliohms) in <FIG> and <FIG>.

As shown in <FIG> and <FIG>, the <NUM>-milliohm difference between the resistors R1, R2 results in an imbalance between the currents <NUM>, <NUM> flowing through the master subconverter and the currents <NUM>, <NUM> flowing through the slave subconverter when the interpolation control methods are not employed. Specifically, the currents <NUM>, <NUM> in the slave subconverter are larger than and leading the currents <NUM>, <NUM> in the master subconverter. However, and as shown in <FIG> and <FIG>, if the interpolation-based control methods are employed, the <NUM> milliohm resistive difference results in minimal imbalance between the currents <NUM>, <NUM> flowing through the master subconverter and the currents <NUM>, <NUM> flowing through the slave subconverter.

The interleaved multiphase switching power converters disclosed herein may include any suitable topology such as a buck, boost, buck-boost, totem-pole, etc. topology for providing AC/DC, DC/AC and/or DC/DC power conversion. In some preferred embodiments, the subconverters may be front- end stages in the switching power converters, and include, for example, AC/DC boost PFC power circuits, totem pole PFC power circuits, etc. operated at defined phase shifts and with average current mode control. In such examples, the power converters may have a power rating of <NUM> W, more or less than <NUM> W, etc..

For example, <FIG> illustrates an interleaved multiphase switching power converter <NUM> including three interleaved subconverters <NUM>, <NUM>, <NUM>, and a control circuit <NUM>. The subconverters <NUM>, <NUM>, <NUM> are coupled in parallel, and include inductors L1, L2, L3, diodes D1, D2, D3, and power switches S1, S2, S3, respectively. The inductors, the diodes, and the power switches of the subconverters <NUM>, <NUM>, <NUM> are arranged in PFC boost topologies. In some examples, the subconverter <NUM> may be a master subconverter, and the subconverters <NUM>, <NUM> may be slave subconverters.

The control circuit <NUM> is coupled to the subconverters <NUM>, <NUM>, <NUM> for controlling the power switches S1, S2, S3 to operate the subconverters <NUM>, <NUM>, <NUM> at a <NUM>-degree phase shift therebetween. The control circuit <NUM> may include, for example, the current compensator <NUM> of <FIG>, the circuit <NUM> of <FIG>, or another suitable current compensator and/or voltage compensator for balancing rail currents in the subconverters <NUM>, <NUM>, <NUM>. In scenarios where the interleaved multiphase switching power converter <NUM> includes only two subconverters (e.g., the subconverters <NUM>, <NUM>), the control circuit <NUM> may include, for example, the current compensator <NUM> of <FIG> or another suitable current compensator for balancing rail currents.

As shown in <FIG>, the switching power converter <NUM> further includes a rectifier (e.g., a diode bridge rectifier, etc.) for rectifying an AC input voltage V_ac, a capacitor C3 coupled between the subconverters <NUM>, <NUM>, <NUM> and the rectifier, and a capacitor C4 coupled between the subconverters <NUM>, <NUM>, <NUM> and the converter's output. Additionally, the switching power converter <NUM> includes an optional diode D4 (e.g., a bypass diode) coupled across the subconverters <NUM>, <NUM>, <NUM> for rerouting current flow from the input to the output when the input voltage is greater than the output voltage. During this condition, energy in the inductors cannot transfer to the output. When the input voltage is less than the output voltage, the diode D4 is in its inactive state.

The control circuit <NUM> may employ any one of the interpolation-based control methods disclosed herein to ensure rail currents passing through the inductors L1, L2, L3 are balanced. For example, the control circuit <NUM> may determine a duty cycle D1 for the power switch S1 (e.g., of the master subconverter <NUM>) based on a sensed current Isense and a reference signal. The reference signal may be determined based on a sensed input voltage Vin and a sensed output voltage Vo, as explained above. The control circuit <NUM> may also determine duty cycles D2, D3 for the power switches S2, S3 (e.g., of the slave subconverters <NUM>, <NUM>) based on present and previous values of the duty cycle D1 and constant reference signals (e.g., reference signals C1, C2 of <FIG>), as explained above. The control circuit <NUM> may then generate PWM control signals PWM1, PWM2, PWM3 having the duty cycle D1, D2, D3 for controlling the power switches S1, S2, S3, respectively.

In the example of <FIG>, the signal Isense represents the combined current flowing through the subconverters <NUM>, <NUM>, <NUM>, and is generated by a single current sensor R1. Alternatively, a current sensor may be associated with each subconverter <NUM>, <NUM>, <NUM> if desired. However, employing multiple current sensors increases components, and as a result, increases cost and complexity of the power converter <NUM>.

The control circuits disclosed herein may include an analog control circuit, a digital control circuit, or a hybrid control circuit (e.g., a digital control unit and an analog circuit). If, for example, the control circuit is a digital control circuit, the control circuit may be implemented with one or more hardware components and/or software. For example, instructions for performing any one or more of the features of the interpolation-based control methods disclosed herein may be stored in and/or transferred from a non-transitory computer readable medium, etc. to one or more existing digital control circuits, new digital control circuits, etc. In such examples, one or more of the instructions may be stored in volatile memory, nonvolatile memory, ROM, RAM, one or more hard disks, magnetic disk drives, optical disk drives, removable memory, non- removable memory, magnetic tape cassettes, flash memory cards, CD-ROM, DVDs, cloud storage, etc..

The digital control circuits may be implemented with one or more types of digital control circuitry. For example, the digital control circuits each may include a digital signal controller (DSC), a digital signal processor (DSP), a microcontroller unit (MCU), a field-programmable gate array (FPGA), an application-specific IC (ASIC), etc..

The power switches disclosed herein may include transistors and/or another suitable switching device. For example, the power switches may include metal-oxide-semiconductor field-effect transistors (MOSFETs) as shown in <FIG>.

The interpolation-based control methods disclosed herein may be used to balance rail currents in two or more subconverters of an interleaved multiphase switching power converter. In some examples, it may be preferred to employ the interpolation-based control methods in switching power converters having two interleaved subconverters or three interleaved subconverters to minimize noise levels in the generated control signals. The control methods may be implemented at any suitable load and/or input range condition while maintaining balanced currents (e.g., phase synchronized, similar wave shapes, similar amplitudes, etc.) at all times.

Claim 1:
An interleaved multiphase switching power converter (<NUM>) comprising:
a plurality of subconverters including: a first subconverter (<NUM>) having a power switch (<NUM>); and a second subconverter (<NUM>) having a power switch (<NUM>), the second subconverter phase shifted relative to the first subconverter; and
a control circuit (<NUM>) coupled to the first subconverter and the second subconverter for controlling the power switch of the first subconverter and the power switch of the second subconverter to balance currents in the first subconverter and the second subconverter over multiple periods, the control circuit (<NUM>) including:
a current compensator (<NUM>, <NUM>) configured to:
determine a first duty cycle (D1) multiple times over the multiple periods based on a first reference signal (Iref) and a sensed current (Isense) in the switching power converter;
generate a first PWM control signal (<NUM>) having a present value (u(t)) of the first duty cycle for controlling the power switch of the first subconverter during one period of the multiple periods;
determine a second duty cycle (D2) based on the present value (u(t)) of the first duty cycle and a previous value (u(t-<NUM>)) of the first duty cycle; and
generate a second PWM control signal (<NUM>) having a present value (u(t)') of the second duty cycle for controlling the power switch of the second subconverter during the one period;
wherein the control circuit (<NUM>) is configured to generate an error signal (err) based on a comparison between the present value of the first duty cycle and the previous value of the first duty cycle for determining the second duty cycle; and
characterized in that the control circuit (<NUM>) is configured to determine the present value (u(t)') of the second duty cycle (D2) based on the equation: <MAT>
wherein u(t) - u(t-<NUM>) represents the error signal (err);
wherein C1 represents a second reference signal; and
wherein u(t)' represents the present value of the second duty cycle (D2).