Patent Description:
"<NPL>, notes that "high-speed electronic digital-to-analog converters (DACs) are of key importance in modem optical transmission systems" and "in multilevel optical transmitters, the analog bandwidth of the DACs is one of the factors limiting the transmitter's bandwidth". Yamazaki et al. describes a digital-preprocessed analog-multiplexed DAC (DP-AM-DAC) that uses a digital pre-processor, two sub-DACs, and an analog multiplexer (AMUX). "With sub-DACs with a bandwidth of ~½fB, we can generate signals with a bandwidth of ~fB as the output from the AMUX. " The AMUX is a heterojunction bipolar transistor (HBT) analog multiplexer (mux). <FIG> of Yamazaki et al. shows an interleaving method (type I) and a preprocessed spectrum method (type II) that reduces the switching frequency of the analog mux by a factor of two. However, type II is very sensitive to imperfections of the matching of the analog characteristics of the two inputs of the analog mux, as very large signal components need to be almost-perfectly cancelled.

"<NPL>), discloses a distributed structure to interleave together the outputs from two DACs. Huang et al. uses two interleaved NRZ (non-return-to-zero) DACs sampled at <NUM> degrees out of phase with respect to each other and summed up at the output stage. The interleaving is structured to invert one of the image spectra so that they are cancelled when summed. Again, there are very strong interference terms that are suppressed only with precise matching of the two halves of the analog circuit.

<CIT> discloses the combining of two half-band signals from two DACs into a full-band signal, by shifting up the frequency of one of the half-band signals with a bipolar mixer. It is desirable to have the circuit implemented using lower energy technologies such as complementary metal-oxide-semiconductor (CMOS).

European Patent Application <CIT> discloses an analog multiplexer in combination with digital-to-analog converters for generating a high-speed analog output signal.

Packet and burst switches are known, where typically <NUM> bytes received from one tributary are sent in sequence out of one optical or electrical output. <NPL> proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. This article illustrates in <FIG> a circuit model of a single-stage MUX having N inputs. Simulation results for N = <NUM>, <NUM>, <NUM> are disclosed. However, there is no disclosure or suggestion that, in the case of N≥<NUM>, a data transition occurs between two adjacent analog samples while one of the inputs is connected to the single input. <FIG> and <FIG> of <CIT> demonstrate conventional interleaving of samples from two streams using a <NUM>:<NUM> MUX. <FIG> illustrates a <NUM>:<NUM> MUX that also performs interleaving and "operates in a similar way [to the <NUM>-way interleaved DAC in <FIG>]".

The invention is defined by the appended independent claim and the preferred embodiments are set out in the appended dependent claims.

<FIG> illustrates a mechanism for creating a high-bandwidth analog signal.

A controlled switch <NUM> has N inputs and a single output, where the number N is equal to three. N sub-streams of analog samples are provided as input to the controlled switch <NUM>, each sub-stream to a respective one of the inputs. A first sub-stream <NUM>, a second sub-stream <NUM> and an N-th sub-stream <NUM> are illustrated in <FIG>.

The controlled switch <NUM> is operative to produce a high-bandwidth analog signal at a sample rate of FS. The high-bandwidth analog signal comprises an output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } that contains one analog sample in each time period of duration ~TS. The symbol "~" is shorthand for the word "approximately". The index i of each analog sample Ai represents an order of the analog samples in the output stream <NUM>. A pair of samples is deemed "adjacent" if the index of the second sample in the pair is one greater than the index of the first sample in the pair.

The controlled switch <NUM> has N different states. In the first state, the first sub-stream <NUM> is connected to the output of the controlled switch <NUM> and thus contributes to the output stream <NUM>. In the second state, the second sub-stream <NUM> is connected to the output of the controlled switch <NUM> and thus contributes to the output stream <NUM>. In the N-th state, the N-th sub-stream <NUM> is connected to the output of the controlled switch <NUM> and thus contributes to the output stream <NUM>.

A control signal <NUM> having a period of ~ <NUM>N TS controls the controlled switch <NUM> to switch between the N different states. For example, the control signal <NUM> is a clock signal operating at a frequency of <MAT>, and the controlled switch <NUM> is controlled by rising edges and falling edges of the <MAT> clock signal <NUM>.

The first sub-stream <NUM> is intentionally composed of pairs of adjacent analog samples such as {A<NUM>, A<NUM>}, {AN, AN+<NUM>}, and {A2N, A2N+<NUM>}. The timing of the control signal <NUM> is intentionally arranged so that a data transition occurs between two adjacent analog samples in the first sub-stream <NUM> while the controlled switch <NUM> is in the first state. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> while the controlled switch <NUM> is in the first state.

The second sub-stream <NUM> is intentionally composed of pairs of adjacent analog samples such as {A<NUM>, A<NUM>}, {AN+<NUM>, AN+<NUM>}, and {A2N+<NUM>, A2N+<NUM>}. The timing of the control signal <NUM> is intentionally arranged so that a data transition occurs between two adjacent analog samples in the second sub-stream <NUM> while the controlled switch <NUM> is in the second state. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> while the controlled switch <NUM> is in the second state.

The N-th sub-stream <NUM> is intentionally composed of pairs of adjacent analog samples such as {AN-<NUM>, AN-<NUM>}, {A2N-<NUM>, A2N-<NUM>}, and {A3N-<NUM>, A3N-<NUM>}. The timing of the control signal <NUM> is intentionally arranged so that a data transition occurs between two adjacent analog samples in the N-th sub-stream <NUM> while the controlled switch <NUM> is in the N-th state. For example, the analog samples AN-<NUM> and AN-<NUM> contribute one after the other to the output stream <NUM> while the controlled switch <NUM> is in the N-th state.

Two adjacent analog samples in the output stream <NUM> are substantially determined by a corresponding two adjacent analog samples in one of the sub-streams. For example, the output stream <NUM> has the analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. }, and the samples {A<NUM>, A<NUM>} in the output stream <NUM> are substantially determined by the corresponding samples {A<NUM>, A<NUM>} in the first sub-stream <NUM>, and the samples {A<NUM>, A<NUM>} in the output stream <NUM> are substantially determined by the corresponding samples {A<NUM>, A<NUM>} in the second sub-stream <NUM>. The term "substantially determined" is used to express the fact that the samples in the output stream <NUM> may not be identical to the samples in the sub-streams. Imperfect circuits may contribute distortion and/or noise. Analog filtering, peaking, hysteresis, reconstruction filtering, and parasitic circuit elements can cause inter-symbol interference (ISI) so that one output sample is a function of more than one input sample, while still being substantially determined by one input sample.

The "capture" of a data transition between two adjacent analog samples in a sub-stream, with both of the adjacent analog samples contributing, one after the other, to the output stream <NUM>, results in an effective sampling rate of twice the number of sub-streams. Stated differently, the mechanism described with respect to <FIG> achieves twice the throughput as expected for the number of sub-streams.

It is unconventional, unexpected, and unintuitive to intentionally "capture" a data transition from one analog sample to an adjacent analog sample, because samples are unstable during the data transition, for example, due to the inter-symbol interference (ISI). Usual design practice is to resample the data in the center of the data interval, to avoid the effects of timing jitter, timing offset, and the complicated and potentially asymmetric dynamics of the data transition.

It is a challenge to generate a high-speed clock and to bring the high-speed clock to an analog multiplexer component. Furthermore, an analog multiplexer component controlled by a high-speed clock consumes power that is directly proportional to the clock speed.

One potential benefit of the mechanism described with respect to <FIG> is that for a desired sample rate of FS, it is sufficient to generate and bring to the controlled switch <NUM> a control signal <NUM> having a period of ~ <NUM>N TS. For example, if there are precisely two sub-streams, then a clock signal <NUM> operating at ~¼FS is sufficient to achieve the desired sample rate of FS. In another example, if there are precisely four sub-streams, then a clock signal <NUM> operating at ~⅛FS is sufficient to achieve the desired sample rate of FS. It is much easier for the controlled switch <NUM> to switch when controlled by a slower clock signal than when controlled by a fast clock signal, and the controlled switch <NUM> will consume less heat when controlled by the slower clock signal than when controlled by the fast clock signal.

The source of the first sub-stream <NUM> of analog samples provided as input to the controlled switch <NUM> is shown conceptually in <FIG> as an arbitrary source <NUM>. The source of the second sub-stream <NUM> of analog samples provided as input to the controlled switch <NUM> is shown conceptually in <FIG> as an arbitrary source <NUM>. The source of the N-th sub-stream <NUM> of analog samples provided as input to the controlled switch <NUM> is shown conceptually in <FIG> as an arbitrary source <NUM>.

Another potential benefit of the mechanism described with respect to <FIG> is that it involves a single control signal <NUM> to drive the arbitrary sources <NUM>, <NUM>, <NUM> and to drive the controlled switch <NUM>. No other control signals or clock signals are required.

Each one of the N sub-streams of analog samples provided as input to the controlled switch <NUM> may be converted from a respective sub-stream of digital samples (not shown). Various example digital-to-analog converters that employ the mechanism described with respect to <FIG> are illustrated in <FIG>, <FIG>, <FIG>, and <FIG> and are described hereinbelow. In those example digital-to-analog converters, the arbitrary sources <NUM>, <NUM>, <NUM> of the N sub-streams of analog samples are sub-DACs controlled by a clock signal operating at a frequency of <MAT>.

Linear digital filtering of the sub-streams of digital samples may adapt the signals in each sub-stream to obtain a cleaner output from the controlled switch <NUM>. This may become more important when the controlled switch <NUM> is physically further away from the sources of the sub-streams. The linear digital filtering may be calibrated in the factory. Alternatively, local or remote feedback may be used to dynamically control the linear digital filtering.

Nonlinear compensation may be included in the generation of the sub-streams, for example, as described in <CIT>, without memory, or with memory (time delays) in the response. This nonlinear compensation may compensate for nonlinearity in the component DACs, the controlled switch, or downstream elements.

The arrangement of the timing of the control signal <NUM> relative to the occurrence of data transitions between two adjacent analog samples in the sub-streams may result from delays introduced in the sub-streams. This is the case, for example, in the DACs illustrated in <FIG> and <FIG>.

The arrangement of the timing of the control signal <NUM> relative to the occurrence of data transitions between two adjacent analog samples in the sub-streams may result from a phase offset between the control signal <NUM> and clocks used to generate the sub-streams. This is the case, for example, in the DACs illustrated in <FIG> and <FIG>. Phase shifting may be used to obtain precision control of the clock phases. This may be calibrated in the factory. Alternatively, local or remote feedback may be used to dynamically control the phase.

Depending on the implementation, it may be simpler to produce clock signals having zero relative phase offset (as used in the DACs illustrated in <FIG> and <FIG>) than to produce clock signals having a non-zero relative phase offset (as used in the DACs illustrated in <FIG> and <FIG>).

Depending on the implementation, it may be simpler to produce clock signals having non-zero relative phase offset (as used in the DACs illustrated in <FIG> and <FIG>) than to delay analog signals (as used in the DACs illustrated in <FIG> and <FIG>).

<FIG> illustrates an example digital-to-analog converter (DAC) <NUM>, not forming part of the claimed invention, that is operative to convert an input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at a sampling rate of FS.

<FIG> is a timing diagram of clock signals and data signals in the DAC <NUM>.

The DAC <NUM> comprises a "positive" sub-DAC component <NUM>, a "negative" sub-DAC component <NUM>, and a controlled switch <NUM>. The controlled switch <NUM> has two inputs (coupled to the outputs of the sub-DAC components <NUM>, <NUM>) and a single output (the output stream <NUM>). (The controlled switch <NUM> is a specific example of the controlled switch <NUM> described with respect to <FIG>, where the number of sub-streams is precisely two (N=<NUM>).

The positive sub-DAC component <NUM> receives as input a first sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. }, and the negative sub-DAC component <NUM> receives as input a second sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. The first sub-stream <NUM> is composed of pairs of adjacent digital samples such as {D<NUM>, D<NUM>}, {D<NUM>, D<NUM>}, and {D<NUM>, D<NUM>}, and the second sub-stream <NUM> is composed of pairs of adjacent digital samples such as {D<NUM>, D<NUM>}, {D<NUM>, D<NUM>}, and {D<NUM>, D<NUM>}. A partitioning module <NUM> comprised in the DAC <NUM> is operative to partition the input stream <NUM> of digital samples into the first sub-stream <NUM> and the second sub-stream <NUM>, using any suitable technique. For example, the partitioning module <NUM> could reorder every four consecutive samples in the input stream <NUM> as {D<NUM>, D<NUM>, D<NUM>, D<NUM>, D<NUM>, D<NUM>, D<NUM>, D<NUM>,. To obtain the first sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. }, the partitioning module <NUM> could apply a decimate-by-two function to the reordered samples. To obtain the second sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. }, the partitioning module <NUM> could delay a copy of the reordered samples by a delay of duration ~TS, and then apply a decimate-by-two function.

A clock signal <NUM> operating at ~¼FS (and therefore having a period of ~4TS) is provided to the sub-DAC components <NUM>, <NUM>. The positive sub-DAC component <NUM> samples the first sub-stream <NUM> at rising edges and falling edges of the ~¼FS clock signal <NUM>, thus converting the first sub-stream <NUM> into a first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. The negative sub-DAC component <NUM> samples the second sub-stream <NUM> at rising edges and falling edges of the ~¼FS clock signal <NUM>, thus converting the second sub-stream <NUM> into a second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. An analog delay line <NUM> is operative to delay the first sub-stream <NUM> by a delay of duration ~TS, yielding a first sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. An analog delay line <NUM> is operative to delay the second sub-stream <NUM> by a delay of duration ~3TS, yielding a second sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. (The first sub-stream <NUM> is a specific example of the first sub-stream <NUM> described with respect to <FIG>, and the second sub-stream <NUM> is a specific example of the second sub-stream <NUM> described with respect to <FIG>.

The ~¼FS clock signal <NUM> is provided, with zero phase offset, to the controlled switch <NUM>. The controlled switch <NUM> is controlled by rising edges and falling edges of the ~¼FS clock signal <NUM>, switching between a "positive" state in which the first sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM> and a "negative" state in which the second sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>. The resulting output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~TS.

As mentioned, the analog delay line <NUM> and the analog delay line <NUM> are operative to introduce delays in the sub-streams of analog samples. These delays result in the arrangement of the timing of the "positive" states and "negative" states of the controlled switch <NUM> relative to the occurrence of data transitions between two adjacent analog samples in the first sub-stream <NUM> and in the second sub-stream <NUM>.

While the controlled switch <NUM> is in the "positive" state, the data transition in the first sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "negative" state, the data transition in the second sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a single half-period of duration ~2TS of the ~¼FS clock signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single half-period of duration ~2TS of the ~¼FS clock signal <NUM>.

The following time-table is helpful for understanding the operation of the DAC <NUM> and the timing diagram illustrated in <FIG>.

By employing the mechanism described above with respect to <FIG>, the DAC <NUM> produces the output stream <NUM> at the rate of ~FS using clock signals operating solely at ~¼FS.

<FIG> illustrates an example digital-to-analog converter (DAC) <NUM>, not forming part of the claimed invention, that is operative to convert the input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at the sampling rate of FS.

The DAC <NUM> is a variant of the DAC <NUM> illustrated in <FIG>. In contrast to the DAC <NUM>, there are no analog delay lines in the DAC <NUM>. (The first sub-stream <NUM> is a specific example of the first sub-stream <NUM> described with respect to <FIG>, and the second sub-stream <NUM> is a specific example of the second sub-stream <NUM> described with respect to <FIG>.

In the DAC <NUM>, the ~¼FS clock signal <NUM> provided to the controlled switch <NUM> has a <NUM>° phase offset relative to the ~¼FS clock signal <NUM> that is provided to the sub-DAC components <NUM>, <NUM>. The controlled switch <NUM> is controlled by rising edges and falling edges of the <NUM>° phase offset ~¼FS clock signal <NUM>, switching between a "positive" state in which the first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM> and a "negative" state in which the second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>. The resulting output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~TS.

As illustrated, in the DAC <NUM>, the ~¼FS clock signal <NUM> provided to the controlled switch <NUM> has a <NUM>° phase offset relative to the ~¼FS clock signal <NUM> that is provided to the sub-DAC components <NUM>, <NUM>. This <NUM>° phase offset results in the arrangement of the timing of the "positive" states and "negative" states of the controlled switch <NUM> relative to the occurrence of data transitions between two adjacent analog samples in the first sub-stream <NUM> and in the second sub-stream <NUM>.

While the controlled switch <NUM> is in the "positive" state, the data transition in the first sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "negative" state, the data transition in the second sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a single half-period of duration ~2TS of the <NUM>° phase offset ~¼FS clock signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single half-period of duration ~2TS of the <NUM>° phase offset ~¼FS clock signal <NUM>.

<FIG> illustrates an example digital-to-analog converter (DAC) <NUM> that is operative to convert the input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at the sampling rate of FS.

The DAC <NUM> comprises a "positive" sub-DAC component <NUM>, a "zero" sub-DAC component <NUM>, a "negative" sub-DAC component <NUM>, and a controlled switch <NUM>. The controlled switch <NUM> has three inputs (coupled to the outputs of the sub-DAC components <NUM>, <NUM>, <NUM>) and a single output (the output stream <NUM>). (The controlled switch <NUM> is a specific example of the controlled switch <NUM> described with respect to <FIG>, where the number of sub-streams is precisely three (N=<NUM>).

The positive sub-DAC component <NUM> receives as input a first sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. }, the zero sub-DAC component <NUM> receives as input a second sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. }, and the negative sub-DAC component <NUM> receives as input a third sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. The first sub-stream <NUM> is composed of pairs of adjacent samples such as {D<NUM>, D<NUM>}, {D<NUM>, D<NUM>}, and {D<NUM>, D<NUM>}, the second sub-stream <NUM> is composed of pairs of adjacent samples such as {D<NUM>, D<NUM>}, {D<NUM>, D<NUM>}, and {D<NUM>, D<NUM>}, and the third sub-stream <NUM> is composed of pairs of adjacent samples such as {D<NUM>, D<NUM>}, {D<NUM>, D<NUM>}, and {D<NUM>, D<NUM>}. A partitioning module <NUM> comprised in the DAC <NUM> is operative to partition the input stream <NUM> of digital samples into the first sub-stream <NUM>, the second sub-stream <NUM>, and the third sub-stream <NUM>, using any suitable technique.

A clock signal <NUM> operating at <MAT> (and therefore having a period of ~6TS) is provided to the sub-DAC components <NUM>, <NUM>, <NUM>. The positive sub-DAC component <NUM> samples the first sub-stream <NUM> at rising edges and falling edges of the <MAT> clock signal <NUM>, thus converting the first sub-stream <NUM> into a first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. The zero sub-DAC component <NUM> samples the second sub-stream <NUM> at rising edges and falling edges of the <MAT> clock signal <NUM>, thus converting the second sub-stream <NUM> into a second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. The negative sub-DAC component <NUM> samples the third sub-stream <NUM> at rising edges and falling edges of the <MAT> clock signal <NUM>, thus converting the third sub-stream <NUM> into a third sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,.

An analog delay line <NUM> is operative to delay the first sub-stream <NUM> by a delay of duration ~TS, yielding a first sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. An analog delay line <NUM> is operative to delay the second sub-stream <NUM> by a delay of duration ~3TS, yielding a second sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. An analog delay line <NUM> is operative to delay the third sub-stream <NUM> by a delay of duration ~5TS, yielding a third sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,.

A three-state control signal <NUM> having a period of ~6TS is provided to the controlled switch <NUM>. The controlled switch <NUM> is controlled by transitions of the three-state control signal <NUM>, switching between a "positive" state in which the first sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>, a "zero" state in which the second sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>, and a "negative" state in which the third sub-stream <NUM> of delayed analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>. The resulting output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~TS.

As illustrated, the three-state control signal <NUM> has a zero-phase offset relative to the <MAT> clock signal <NUM> provided to the sub-DAC components <NUM>, <NUM>, <NUM>. The delays introduced by the analog delay lines <NUM>, <NUM>, and <NUM> result in the arrangement of the timing of the "positive", "zero" and "negative" states of the controlled switch <NUM>, respectively, relative to the occurrence of data transitions between two adjacent analog samples in the first sub-stream <NUM>, the second sub-stream <NUM> and the third sub-stream <NUM>.

While the controlled switch <NUM> is in the "positive" state, the data transition in the first sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "zero" state, the data transition in the second sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "negative" state, the data transition in the third sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a single third-period of duration ~2TS of the control signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single third-period of duration ~2TS of the control signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single third-period of duration ~2TS of the control signal <NUM>.

By employing the mechanism described above with respect to <FIG>, the DAC <NUM> produces the output stream at the rate of ~FS using clock signals operating solely at <MAT>.

<FIG> illustrates an example digital-to-analog converter (DAC) <NUM> that is operative to convert the input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at the sampling rate of FS.

The DAC <NUM> is a variant of the DAC <NUM> illustrated in <FIG>. In contrast to the DAC <NUM>, there are no analog delay lines in the DAC <NUM>.

In the DAC <NUM>, a three-state control signal <NUM> having a period of ~6TS is provided to the controlled switch <NUM>. The controlled switch <NUM> is controlled by transitions of the three-state control signal <NUM>, switching between a "positive" state in which the first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>, a "zero" state in which the second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>, and a "negative" state in which the third sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contributes to the output stream <NUM>. The resulting output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~TS.

As illustrated, the three-state control signal <NUM> has a <NUM>° phase offset relative to the <MAT> clock signal <NUM>. This <NUM>° phase offset results in the arrangement of the timing of the "positive", "zero" and "negative" states of the controlled switch <NUM> relative to the occurrence of data transitions between two adjacent analog samples in the first sub-stream <NUM>, the second sub-stream <NUM> and the third sub-stream <NUM>.

While the controlled switch <NUM> is in the "positive" state, the data transition in the first sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "zero" state, the data transition in the second sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. While the controlled switch <NUM> is in the "negative" state, the data transition in the third sub-stream <NUM> from one analog sample to an adjacent analog sample is captured. For example, the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a single third-period of duration ~2TS of the three-state control signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single third-period of duration ~2TS of the three-state control signal <NUM>, and then the analog samples A<NUM> and A<NUM> contribute one after the other to the output stream <NUM> during a next single third-period of duration ~2TS of the three-state control signal <NUM>.

By employing the mechanism described above with respect to <FIG>, the DAC <NUM> produces the output stream <NUM> at the rate of ~FS using clock signals operating solely at <MAT>.

<FIG> illustrates an example sub-DAC <NUM>, not forming part of the claimed invention, that is operative to convert digital samples into analog samples. The sub-DAC <NUM> may optionally be used as the "positive" sub-DAC <NUM> in DAC <NUM> or DAC <NUM> to convert the first sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at a sampling rate of ½FS.

<FIG> is a timing diagram of clock signals and data signals in the sub-DAC <NUM>.

The sub-DAC <NUM> comprises an "even" sub-sub-DAC component <NUM>, an "odd" sub-DAC component <NUM>, and an analog multiplexer (AMUX) component <NUM>. The AMUX component <NUM> has two inputs (coupled to the outputs of the sub-sub-DAC components <NUM>, <NUM>) and a single output (the first sub-stream <NUM>).

The even sub-sub-DAC component <NUM> receives as input a first sub-sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>,. }, and the odd sub-sub-DAC component <NUM> receives as input a second sub-sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>,. A partitioning module <NUM> is operative to partition the first sub-stream <NUM> of digital samples into the first sub-sub-stream <NUM> and the second sub-sub-stream <NUM>, using any suitable technique. For example, the first sub-stream <NUM> could be duplicated, a delay buffer (not shown) could delay one copy of the first sub-stream <NUM> by a duration of ~TS, and decimator elements (not shown) could remove every other sample from the copies of the first sub-stream <NUM>.

A clock signal <NUM> operating at ~⅛FS (and therefore having a period of ~8TS) is provided to the sub-sub-DAC components <NUM>, <NUM>. The ~⅛FS clock signal <NUM> provided to the odd sub-sub-DAC component <NUM> has a <NUM>° phase offset relative to the ~⅛FS clock signal <NUM> provided to the even sub-sub-DAC component <NUM>. The even sub-sub-DAC component <NUM> samples the first sub-sub-stream <NUM> at rising edges and falling edges of the ~⅛FS clock signal <NUM>, thus converting the first sub-sub-stream <NUM> into a first sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. The odd sub-DAC component <NUM> samples the second sub-sub-stream <NUM> at rising edges and falling edges of the <NUM>° phase offset ~⅛FS clock signal <NUM>, thus converting the second sub-sub-stream <NUM> into a second sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,.

The ~¼FS clock signal <NUM> is provided to the AMUX component <NUM>. The AMUX component <NUM> is controlled by rising edges and falling edges of the ~¼FS clock signal <NUM>, switching between an "even" state in which the first sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. } contributes a single analog sample to the first sub-stream <NUM> and an "odd" state in which the second sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. } contributes a single analog sample to the first sub-stream <NUM>. The resulting first sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~2TS.

The ~¼FS clock signal <NUM> is offset by approximately <NUM>° phase from double the ~⅛FS clock signal <NUM>. The ~¼FS clock signal <NUM> is intentionally timed so that no data transition occurs between analog samples in the first sub-sub-stream <NUM> while the AMUX component <NUM> is in the "even" state, and no data transition occurs between analog samples in the second sub-sub-stream <NUM> while the AMUX component <NUM> is in the "odd" state. Stated differently, all samples in the first sub-stream <NUM> are captured from stable portions of the sub-sub-streams <NUM> and <NUM>.

<FIG> illustrates an example sub-DAC <NUM>, not forming part of the claimed invention, that is operative to convert digital samples into analog samples. The sub-DAC <NUM> may optionally be used as the "negative" sub-DAC <NUM> in DAC <NUM> or DAC <NUM> to convert the second sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } into the second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } at a sampling rate of ½FS.

The sub-DAC <NUM> comprises an "even" sub-sub-DAC component <NUM>, an "odd" sub-DAC component <NUM>, and an analog multiplexer (AMUX) component <NUM>. The AMUX component <NUM> has two inputs (coupled to the outputs of the sub-sub-DAC components <NUM>, <NUM>) and a single output (the second sub-stream <NUM>).

The even sub-sub-DAC component <NUM> receives as input a first sub-sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>,. }, and the odd sub-sub-DAC component <NUM> receives as input a second sub-sub-stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>,. A partitioning module <NUM> is operative to partition the second sub-stream <NUM> of digital samples into the first sub-sub-stream <NUM> and the second sub-sub-stream <NUM>, using any suitable technique. For example, the second sub-stream <NUM> could be duplicated, a delay buffer (not shown) could delay one copy of the second sub-stream <NUM> by a duration of ~TS, and decimator elements (not shown) could remove every other sample from the copies of the second sub-stream <NUM>.

The ~⅛FS clock signal <NUM> is provided to the sub-sub-DAC components <NUM>, <NUM>. The ~⅛FS clock signal <NUM> provided to the odd sub-sub-DAC component <NUM> has a <NUM>° phase offset relative to the ~⅛FS clock signal <NUM> provided to the even sub-sub-DAC component <NUM>. The even sub-sub-DAC component <NUM> samples the first sub-sub-stream <NUM> at rising edges and falling edges of the <NUM>° phase offset ~⅛FS clock signal <NUM>, thus converting the first sub-sub-stream <NUM> into a first sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. The odd sub-DAC component <NUM> samples the second sub-sub-stream <NUM> at rising edges and falling edges of the ~⅛FS clock signal <NUM>, thus converting the second sub-sub-stream <NUM> into a second sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,.

The ~¼FS clock signal <NUM> is provided to the AMUX component <NUM>. The AMUX component <NUM> is controlled by rising edges and falling edges of the ~¼FS clock signal <NUM>, switching between an "even" state in which the first sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. } contributes a single analog sample to the second sub-stream <NUM> and an "odd" state in which the second sub-sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>,. } contributes a single analog sample to the second sub-stream <NUM>. The resulting second sub-stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>, A<NUM>,. } contains one analog sample in each time period of duration ~2TS.

The ~¼FS clock signal <NUM> is offset by approximately <NUM>° phase from double the ~⅛FS clock signal <NUM>. The ~¼FS clock signal <NUM> is intentionally timed so that no data transition occurs between analog samples in the first sub-sub-stream <NUM> while the AMUX component <NUM> is in the "even" state, and no data transition occurs between analog samples in the second sub-sub-stream <NUM> while the AMUX component <NUM> is in the "odd" state. Stated differently, all samples in the second sub-stream <NUM> are captured from stable portions of the sub-sub-streams <NUM> and <NUM>.

Use of the sub-DACs <NUM> and <NUM> in the DAC <NUM> or in the DAC <NUM> will increase resilience to distortions as well as to time mismatches between sub-DACs, at a cost of increased complexity. The increased complexity involves providing a clock signal at approximately one quarter of the sampling rate (~¼FS), and the increased complexity may be deemed acceptable.

The following time-table is helpful for understanding use of the sub-DACs <NUM> and <NUM> in the operation of the DAC <NUM>.

Sub-DACs similar to the sub-DACs <NUM> and <NUM> could be used as the "positive" sub-DAC, "zero" sub-DAC, and "negative" sub-DAC in the DAC <NUM> or in the DAC <NUM>.

<FIG> is a block diagram illustration of an example transmitter <NUM> that employs polarization-division multiplexing (PDM). A laser <NUM> is operative to generate a continuous wave (CW) optical carrier <NUM>. A polarizing beam splitter <NUM> is operative to split the CW optical carrier <NUM> into orthogonally-polarized components <NUM>, <NUM> (nominally referred to as the "X-polarization" component and the "Y-polarization" component) that are modulated by respective electrical-to-optical modulators <NUM>, <NUM> to produce modulated polarized optical signals <NUM>, <NUM> that are combined by a beam combiner <NUM>, thus yielding an optical signal <NUM>.

A symbol source <NUM> is operative to generate a stream of symbols representing data to be transmitted in the optical signal <NUM>. A digital signal processor (DSP) <NUM> is operative to process the symbols output from the symbol source <NUM>, for example, performing one or more of pulse shaping, subcarrier multiplexing, chromatic dispersion pre-compensation, and distortion pre-compensation on the symbols. The DSP <NUM> is operative to generate I and Q digital drive signals <NUM> for the X-polarization to be converted by a DAC <NUM> into I and Q analog drive signals <NUM> for the X-polarization that, after amplification by amplifiers <NUM>, are used to drive the electrical-to-optical modulator <NUM>. The DSP <NUM> is operative to generate I and Q digital drive signals <NUM> for the Y-polarization to be converted by a DAC <NUM> into I and Q analog drive signals <NUM> for the Y-polarization that, after amplification by amplifiers <NUM>, are used to drive the electrical-to-optical modulator <NUM>.

The DACs described in this document could be used as the DAC <NUM> and the DAC <NUM>. For example, the I and Q digital drive signals <NUM> for the X-polarization may be the input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } and the I and Q analog drive signals <NUM> for the X-polarization may be the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,. For example, the I and Q digital drive signals <NUM> for the Y-polarization may be the input stream <NUM> of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>,. } and the I and Q analog drive signals <NUM> for the Y-polarization may be the output stream <NUM> of analog samples {A<NUM>, A<NUM>, A<NUM>, A<NUM>,.

Stated differently, each of the DAC <NUM>, <NUM> may comprise two or more sub-DACs, and the streams of analog samples that are output from the two or more sub-DACs may be provided as inputs to a controlled switch that is a specific example of the controlled switch <NUM> described with respect to <FIG>. In some implementations, a sub-DAC may employ the architecture described with respect to <FIG> or <FIG>.

In some implementations, the DSP <NUM> and the DACs <NUM>, <NUM> are comprised in a CMOS module, and the amplifiers <NUM>, <NUM> are comprised in a BiCMOS module.

In other implementations, when the interconnect between blocks does not support the full bandwidth, the controlled switches of the DACs <NUM>, <NUM> may be separate from the CMOS module that comprises the DSP <NUM> and the other components (including the sub-DACs) of the DACs <NUM>, <NUM>. For example, the controlled switches may be comprised in another CMOS module, or a BiCMOS module, or HBT. For example, the controlled switches may be co-packaged with the electrical-to-optical modulator <NUM>, <NUM> or the driver.

For simplicity of explanation, perfect analog switches were used in the examples, with a square clock. At high frequencies, the clock will generally consist of a fundamental along with one or two harmonics. The controlled switch may be implemented with nonlinear electrical, electro-optic, or optical elements, such as CMOS field effect transistors (FETs) or diodes, bipolar transistors or diodes, heterojunction bipolar transistors (HBTs), electro-absorption (EA) modulators, phase modulators, or semiconductor optical amplifier (SOA) structures. The switching function may be substantially a multiplication by the clock voltage or may include strong nonlinear functional terms.

The techniques described in this document may be used to convert integer sub-streams into a voltage stream, in CMOS. However, other instantiations may be used. For example, current sub-streams may be converted to an optical E-Field stream, as was described in <CIT> An integer sub-stream may be combined with a voltage sub-stream to produce a voltage stream. The analog characteristic of the stream that is being created may be an optical or electrical phase, or other modulation of an input analog signal.

A series of integer values that represent a time-series signal may be instantiated in parallel circuits or any other pre-determined pattern.

Claim 1:
A method comprising:
partitioning an input stream (<NUM>) of digital samples {D<NUM>, D<NUM>, D<NUM>, D<NUM>, ...} into N sub-streams (<NUM>,<NUM>,<NUM>,<NUM>,<NUM>), wherein N is three, such that the first sub-stream includes a first pair of adjacent digital samples {D<NUM>, D<NUM>} from the input stream and each subsequent Nth pair of adjacent digital samples {D2N, D2N+<NUM>} from the input stream, and the second sub-stream includes a second pair of adjacent digital samples {D<NUM>, D<NUM>} from the input stream and each subsequent Nth pair of adjacent digital samples {D2N+<NUM>, D2N+<NUM>} from the input stream;
for each of the N sub-streams
converting the sub-stream of digital samples into a respective sub-stream (<NUM>,<NUM>,<NUM>,<NUM>,<NUM>) of analog samples such that each analog sample in the sub-stream of analog samples is captured from a stable portion of a corresponding digital sample in the sub-stream of digital samples, and where the sub-stream of analog samples contains one analog sample in each time period of duration ~2Ts; and
providing the sub-stream of analog samples to a respective one of N inputs of a controlled switch (<NUM>,<NUM>), the controlled switch having a single output; and
controlling with a control signal the controlled switch to switch between N different states, the control signal having a period of ~<NUM>N Ts, where in each state a respective one of the N inputs is connected to the single output,
wherein while the controlled switch is in any one of the N different states, a data transition occurs between two adjacent analog samples in the sub-stream that is provided to the one of the N inputs that is connected to the single output,
wherein the single output yields a high-bandwidth analog signal (<NUM>) that contains one analog sample {A<NUM>, A<NUM>, A<NUM>, A<NUM>, ... } in each time period of duration approximately Ts, and any pair of adjacent analog samples in any one of the N sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth signal;
wherein converting each sub-stream of digital samples into its respective sub-stream of analog samples is performed in a respective sub-DAC driven by a clock (<NUM>,<NUM>) at a rate identical to a rate of the control signal; and
wherein an order of the digital samples in the input stream is identical to an order of the analog samples in the high-bandwidth analog signal.