Patent Description:
The present invention relates to the field of electrical coupling apparatuses, and in particular, to a differential signal amplification circuit, a digital isolator, and a digital receiver.

A digital isolation circuit is used to provide an intermediate circuit between a digital signal transmitting circuit and a digital signal receiving circuit. The isolation circuit enables communications between different electrical devices, such as communications between a weak-current circuit and a strong-current circuit, while preventing mutual interference between different circuits.

<FIG> shows an implementation of a traditional digital isolator, which adopts an OOK modem technology and consists of a transmitting circuit TX and a receiving circuit RX. High and low levels in a digital signal are transmitted by sending and not sending a high-frequency clock signal.

Circuit elements of the transmitting circuit TX and the receiving circuit RX are connected as shown in <FIG>. The transmitting circuit TX includes a digital signal input terminal TX_DATA, an oscillator OSC, and isolation capacitors Ciso1 and Ciso2. The receiving circuit RX includes isolation capacitors Ciso3 and Ciso4, two-stage amplification circuits AMP1 and AMP2, capacitors C3 and C4, a comparator CMP, and grounded resistors R1 and R2.

The isolation capacitors Ciso1 and Cios3 as well as Cios2 and Cios4 are connected by wirings Wire1 and Wire2 respectively.

When a common-mode transient interference signal occurs between TX and RX, there may be common-mode currents I1 and I2 flowing through the isolation capacitors Ciso1-Ciso4 respectively to form direct-current voltages Vi1 and Vi2 on the resistors R1 and R2. When the common-mode transient interference signals occur, Vi1 and Vi2 may generate comparatively large direct-current offset voltages. After amplified by AMP1, the direct-current offset voltages Vo1 and Vo2 become larger relative to Vi1 and Vi2, resulting in reduced AMP2 gain and output swing and abnormal signal transmission functions.

<NPL>, involves a design of a CMOS operational amplifier with constant-gm input stages, having almost constant transconductance through the use of rail-to-rail input stages and parallel differential pairs.

<NPL>, involves a low-voltage analog IC design using CMOS technology.

<CIT> involves a differential amplifier circuit utilizing a quadritail configuration.

The object of the present invention is to solve the problem that an input voltage of the amplification circuit described above further results in abnormal signal transmission functions due to the direct-current offset voltages caused by common-mode interference.

To achieve the above inventive object, in an embodiment of the present invention, a differential signal amplification circuit is is provided in accordance with appended independent apparatus claim <NUM>.

As a further improvement of an embodiment of the present invention, the common-mode transient adaptive biasing circuit comprises a common-mode detection circuit and an adaptive biasing circuit, wherein the common-mode detection circuit is connected to the positive input terminal and the negative input terminal of the primary differential amplifier respectively; and when the common-mode detection circuit detects the positive or negative common-mode transient interference signals at the positive input terminal and the negative input terminal, the adaptive biasing circuit is turned on to form a biasing current loop by the adaptive biasing circuit and the multi-stage differential amplifier.

As a further improvement of an embodiment of the present invention, the common-mode detection circuit is configured to detect the positive common-mode transient interference signals, and comprises a first NMOS transistor MC1 and a second NMOS transistor MC2 that are connected in parallel, wherein gate electrodes of the first NMOS transistor MC1 and the NMOS transistor second MC2 are respectively connected to the positive input terminal and the negative input terminal of the primary differential amplifier; drain electrodes of the first NMOS transistor MC1 and the second NMOS transistor MC2 are connected to a biasing current output terminal of the multi-stage differential amplifier; and source electrodes of the first NMOS transistor MC1 and the second NMOS transistor MC2 are connected to a current input terminal of the adaptive biasing circuit.

As a further improvement of an embodiment of the present invention, the adaptive biasing circuit comprises a third NMOS transistor MC3 and a fourth NMOS transistor MC4 having their source electrode and the drain electrode connected, wherein the drain electrode and the gate electrode of the third NMOS transistor MC3 are connected to an output terminal of the common-mode detection circuit; and the source electrode of the fourth NMOS transistor MC4 is connected to ground.

As a further improvement of an embodiment of the present invention, the common-mode detection circuit is configured to detect the negative common-mode transient interference signals, and comprises:.

As a further improvement of an embodiment of the present invention, the adaptive biasing circuit is a current mirror in structure, and a mirroring current output terminal of the current mirror is connected to a biasing current output terminal of the multi-stage differential amplifier.

As a further improvement of an embodiment of the present invention, the adaptive biasing circuit comprises a sixth NMOS transistor MD5 and a seventh NMOS transistor MD6 having their gate electrodes connected, wherein source electrodes of the sixth NMOS transistor MD5 and the seventh NMOS transistor MD6 are connected to ground; a drain electrode and a gate electrode of the sixth NMOS transistor MD5 are connected to a signal output terminal of the adaptive biasing circuit; and a drain electrode of the seventh NMOS transistor MD6 is connected to the biasing current output terminal of the multi-stage differential amplifier.

As a further improvement of an embodiment of the present invention, the differential amplifier is a mirroring circuit, wherein the mirroring circuit comprises a third PMOS transistor MA3 and an eighth NMOS transistor MA1 whose drain electrodes are connected on one side,.

As a further improvement of an embodiment of the present invention, the differential amplifiers above the second stage comprises at least one stage of differential amplifier in which the source electrodes of the eighth NMOS transistor MA1 and the nineth NMOS transistor MA2 are connected to the biasing current output terminal.

As a further improvement of an embodiment of the present invention, the positive input terminal and the negative input terminal of the primary differential amplifier are respectively connected with a third resistor R3 and a fourth resistor R4 to a level.

As a further improvement of an embodiment of the present invention, the positive input terminal and the negative input terminal of the primary differential amplifier are connected to an isolation capacitor Ciso3 and an isolation capacitor Ciso4.

To achieve the above inventive object, in an embodiment of the present invention, a receiver for a digital isolator is provided. Based on the same technical improvements, the present invention provides the receiver for the digital isolator including the differential signal amplification circuit, wherein the positive input terminal and the negative input terminal of the primary differential amplifier are connected to a positive input terminal and a negative input terminal of the digital isolator; the output terminal of the multi-stage differential amplifier is connected to an input terminal of a comparison circuit; and an output terminal of the comparison circuit is connected to an output terminal of the receiver for the digital isolator.

To achieve the above inventive object, in an embodiment of the present invention, a digital isolator is provided. The digital isolator includes a transmitter and a receiver,.

The differential signal amplification circuit includes a multi-stage differential amplifier and a common-mode transient adaptive biasing circuit,.

Compared with the prior art, with the technical solutions of the present invention, abnormal signal transmission caused by the common-mode interference signals can be suppressed.

Preferred embodiments of the technical solutions of the present invention are described below in detail in conjunction with the accompanying drawings to help understanding of the technical solutions of the present invention by those skilled in the art.

<FIG> shows an architecture diagram of a differential signal amplification circuit, including a multi-stage differential amplifier <NUM> and a common-mode transient adaptive biasing circuit (CMTI) <NUM> for providing a biasing current of the multi-stage differential amplifier <NUM>.

The multi-stage differential amplifier <NUM> includes at least a two-stage differential amplifier. An input terminal of the common-mode transient adaptive biasing circuit <NUM> is connected to a positive input terminal INP and a negative input terminal INN of the multi-stage differential amplifier. A positive or negative common-mode interference signal generated on the input terminals is input into the common-mode transient adaptive biasing circuit <NUM>. The common-mode transient adaptive biasing circuit <NUM> detects the positive or negative common-mode transient interference signals at the positive input terminal INP and the negative input terminal INN, determines that an effective positive or negative common-mode transient interference signal is detected after the common-mode transient interference signal reaches a starting voltage of the common-mode transient adaptive biasing circuit <NUM>, and provides a biasing current of a differential amplifier of at least one stage above a second stage when the positive or negative common-mode transient interference signals are detected.

When common-mode transient interference occurs, the multi-stage amplification circuit inputs a direct-current offset voltage, and the offset voltage further becomes larger after amplified by a primary amplifier, resulting in the offset voltage being transferred along the multi-stage amplification circuit and eventually leading to abnormal signal transmission. In this solution, the common-mode transient adaptive biasing circuit <NUM> is capable of compensating for amplifier output loss caused by the occurrence of the positive or negative common-mode transient interference signals. When a primary offset voltage occurs, a positive or negative input voltage and a reverse input voltage of a primary amplification circuit are increased. When the voltages change to exceed a starting voltage of the common-mode transient adaptive biasing circuit, the common-mode transient adaptive biasing circuit <NUM> provides a current in a differential amplifier above the second stage by providing the biasing currents. The differential currents compensate for reduced output swing and gain loss of the differential amplifiers caused by voltage imbalance, and avoid continuous transfer of the direct-current input voltage mismatch caused by the common-mode signals between second-stage differential amplifiers or the differential amplifiers above the second stage. Therefore, the interference caused by the common-mode signals to signal transmission is suppressed. With this method, the common-mode transient adaptive biasing circuit <NUM> compensates for the differential amplifiers of each stage or unspecified number of stages above a second-stage amplification circuit.

With reference to <FIG>, the multi-stage amplification circuit <NUM> includes a plurality of differential amplifiers AMP1 to AMPN having inputs and outputs connected in series. The positive input terminal INP and the negative input terminal INN of the primary differential amplifier AMP1 serve as input terminals of the multi-stage amplification circuit. Optionally, a biasing current output terminal of any number of amplifiers in AMP2 to AMPN is connected to the common-mode transient adaptive biasing circuit <NUM>. The common-mode transient adaptive biasing circuit adjusts the biasing currents of a plurality of differential amplifiers simultaneously. With regard to the order of connection, the differential amplifiers may be connected to the common-mode transient adaptive biasing circuit in the order of AMP2, AMP3, AMP4, AMPS. Alternatively, the differential amplifiers may be connected to the common-mode transient adaptive biasing circuit every other stage in the order of AMP2, AMP4, AMP6, AMPS. AMP2n or by any other electrical connection method known by those skilled in the art. The number of the common-mode transient adaptive biasing circuits <NUM> is not limited to one as shown in <FIG>, but may be multiple. In this case, a connection relationship between the common-mode transient adaptive biasing circuits <NUM> and the multi-stage differential amplifiers AMP1 to AMPN is one-to-one connection or one-to-many connection or many-to-one connection or many-to-many connection. With such a connection solution, the common-mode transient adaptive biasing circuits may provide compensation for the biasing currents of a one-stage or multi-stage differential amplifier simultaneously.

<FIG> is a schematic structural diagram of the primary differential amplifier AMP1 in the multi-stage amplification circuit. A biasing current output terminal IBCMTI is added in <FIG> in addition to those shown in <FIG>. Among the differential amplifiers AMP1 to AMPN, at least one stage of the differential amplifiers is provided with the biasing current output terminal IBCMTI shown in <FIG>.

With reference to <FIG>, a differential amplification circuit is composed of a plurality of basic elements connected in a mirrored manner. The mirroring circuit includes a PMOS transistor MA3 and an NMOS transistor MA <NUM> with their drain electrodes connected in series on the left side. The source electrode of the PMOS transistor MA3 is connected to a power supply VCC, a capacitor CA1 is connected between the gate electrode and the source electrode of the PMOS transistor MA3, and a biasing resistor RA1 is connected between the gate electrode and the drain electrode of the PMOS transistor. The drain electrode of the NMOS transistor MA1 is connected to a negative output terminal OUTN of the differential amplifier, and the gate electrode of the NMOS transistor MA1 is connected to the positive input terminal INP of the differential amplifier. The mirroring structure includes a PMOS transistor MA4 and an NMOS transistor MA2 with their drain electrodes connected in series on the right side. The source electrode of the PMOS transistor MA4 is connected to the power supply VCC, a capacitor CA2 is connected between the gate electrode and the source electrode of the PMOS transistor MA4, and a biasing resistor RA2 is connected between the gate electrode and the drain electrode of the PMOS transistor MA4. The drain electrode of the NMOS transistor MA2 is connected to a positive output terminal OUTP of the differential amplifier, and the gate electrode of the NMOS transistor MA2 is connected to the negative input terminal INN of the differential amplifier.

The source electrodes of the PMOS transistor MA3 and the PMOS transistor MA4 on both sides of the mirroring circuit are connected in parallel, the source electrodes of the NMOS transistor MA1 and the NMOS transistor MA2 on both sides of the mirroring circuit are connected in parallel, and the source electrodes of the NMOS transistor MA1 and the NMOS transistor MA2 are connected to the drain electrode of a grounded NMOS transistor MA5. The gate electrode of the grounded NMOS transistor MA5 is connected to a reference level VBN to provide a biasing current required by the amplifier during normal operation.

The source electrode of the NMOS transistor MA1/MA2 is connected to the biasing current output terminal IBCMTI. When the biasing currents are output, mirroring currents on both sides of the differential circuit are increased, and the difference in output potentials between the positive output terminal OUTP and the negative output terminal OUTN of the differential amplification circuit becomes larger. That is, the corresponding output signal waveform swing becomes larger. Among the multi-stage differential amplifiers AMP2 to AMPN, the amplifiers having at least one stage are provided with the biasing current output terminals IBCMTI. The biasing current output terminals IBCMTI at different stages are connected to the common-mode transient adaptive biasing circuit <NUM> to form multi-stage output gain and swing compensation.

<FIG> and <FIG> show two embodiments of the common-mode transient adaptive biasing circuit. The common-mode transient adaptive biasing circuit shown in <FIG> is configured to detect and suppress the positive common-mode transient interference signals. The common-mode transient adaptive biasing circuit shown in <FIG> is configured to detect and suppress the negative common-mode transient interference signals. For positive and negative common-mode transient adaptive biasing circuits, one of them may be used separately to be connected to the multi-stage differential amplifier <NUM>, or both of them are connected in parallel and connected to the multi-stage differential amplifier <NUM> simultaneously for use.

With reference to the common-mode transient adaptive biasing circuit <NUM> shown in <FIG>, it is connected to the input terminals of the primary amplifier. The positive input terminal INP and the negative input terminal INN of the primary amplifier AMP1 are connected to a positive input terminal RXINP and a negative input terminal RXINN of the receiver described below by isolation capacitors Ciso3 and Ciso4. The positive input terminal and the negative input terminal of the primary amplifier are connected to a level VCM by resistors R3 and R4. When the common-mode signals occur, direct-current voltages Vi1 and Vi2 are formed on the resistors R3 and R4. The adaptive biasing circuit detects the direct-current voltages Vi1 and Vi2, and determines whether common-mode interference occurs based on values of the direct-current voltages Vi1 and Vi2.

The common-mode transient adaptive biasing circuit <NUM> includes a common-mode detection circuit <NUM> and an adaptive biasing circuit <NUM>. The common-mode detection circuit <NUM> includes an NMOS transistor MC1 and an NMOS transistor MC2 that are connected in parallel. The gate electrodes of the two NMOS transistors, as the input terminals of the common-mode transient adaptive biasing circuit, are respectively connected to the positive input terminal INP and the negative input terminal INN of the primary differential amplifier. The drain electrode of the NMOS transistor MC1/MC2 is connected to the biasing current output terminal IBCMTI of the differential amplification circuit, and the source electrodes of the NMOS transistor MC1 and the NMOS transistor MC2 are connected to a current input terminal BiasIN of the adaptive biasing circuit.

The adaptive biasing circuit <NUM> includes an NMOS transistor MC3 and an NMOS transistor MC4 having their source electrode and the drain electrode connected in series. The drain electrode and the gate electrode of the NMOS transistor MC3 are connected to an output terminal CMTIOUT of the common-mode detection circuit <NUM>, and the source electrode of the NMOS transistor MC4 is connected to the ground. The gate electrode of the grounded NMOS transistor MC4 is connected to the reference level VBN for generating the biasing currents for compensating.

Since the gate electrode of the NMOS transistor MC3 is connected to the output terminal CMTIOUT of the common-mode detection circuit <NUM>, the starting voltage of the common-mode transient adaptive biasing circuit is the sum of threshold voltages of the NMOS transistor MC1 or MC2 and the NMOS transistor MC3.

When the common-mode direct-current voltage Vi1 or Vi2 formed by the common-mode interference signals on the grounded resistor R3 or R4 is greater than the starting voltage, the NMOS transistors of the common-mode detection circuit <NUM> are turned on, so that the adaptive biasing circuit <NUM> is communicated with the biasing current output terminal IBCMTI. The common-mode detection circuit <NUM> causes the adaptive biasing circuit <NUM> to form a biasing current loop with at least one of the differential amplifiers AMP2. A biasing current is formed in the adaptive biasing current loop. The currents at the biasing current output terminal IBCMTI flow through the adaptive biasing circuit <NUM> to the ground. The biasing currents increase the currents of the mirroring circuit in the differential amplifier, so that the gain and output swing of the corresponding differential amplifier are increased, thereby compensating for output direct-current imbalance of the primary differential amplifier. The increase in output swing of the differential signal amplification circuit eliminates the influence of common-mode signal interference.

With reference to the negative common-mode transient adaptive biasing circuit shown in <FIG>, it is connected to the input terminals of the primary amplification circuit, and it is connected to the positive common-mode transient adaptive biasing circuit <NUM> shown in <FIG> in parallel. Moreover, it is connected to the positive input terminal INP or the negative input terminal INN of the primary differential amplifier AMP1 as well as the resistor R1 or R2 in the same manner as that in which it is connected to the positive common-mode transient adaptive biasing circuit shown in <FIG>.

The common-mode transient adaptive biasing circuit shown <FIG> includes a common-mode detection circuit <NUM> and an adaptive biasing circuit <NUM>. The common mode detection circuit <NUM> includes a PMOS transistor MD4 and an NMOS transistor MD3 whose drain electrodes are connected in series are provided. The source electrode of the PMOS transistor MD4 is connected to the power supply VCC, and the gate electrodes of the PMOS transistor MD4 and the NMOS transistor MD3 are respectively connected to a level VBP and a level VSET. The common mode detection circuit <NUM> includes a PMOS transistor MD1 and a PMOS transistor MD2 connected in parallel having their source electrodes connected to the source electrode of the NMOS transistor MD3, the gate electrodes of the PMOS transistor MD1 and the PMOS transistor MD2 are respectively connected to the positive input terminal INP and the negative input terminal INN of the primary differential amplifier AMP1, and the drain electrodes of the PMOS transistor MD1 and the PMOS transistor MD2 are connected to a signal input terminal BiasIN' of the adaptive biasing circuit <NUM>.

The common-mode detection circuit <NUM> may detect the negative common-mode transient interference signals and adaptively adjust the biasing currents. The PMOS transistor MD4 generates a biasing current according to the level VBP, the PMOS transistor MD1 and the PMOS transistor MD2 detect a common-mode voltage, and when VCM is less than VSET minus a threshold voltage of MD3 and a threshold voltage of MD1 or MD2 (i.e., VCM < VSET - |Vth_MD3| - Vth_MDl, or VCM < VSET - |Vth_MD3| - Vth_MD2), an adaptive biasing current is switched on. A current signal output is generated at an output terminal CMTIOUT' of the common-mode detection circuit.

With continuing reference to <FIG>, the adaptive biasing circuit <NUM> is a current mirror in structure. A mirroring current output terminal of the current mirror is connected to the biasing current output terminal IBCMTI of the multi-stage differential amplifier <NUM>. The adaptive biasing circuit includes an NMOS transistor MD5 and an NMOS transistor MD6 having their gate electrodes connected, and source electrodes of the NMOS transistor MD5 and the NMOS transistor MD6 are connected to the ground. The drain electrode and the gate electrode of the NMOS transistor MD5 are connected to the signal output terminal CMTIOUT' of the adaptive biasing circuit <NUM>. The drain electrode of the NMOS transistor MD6 is connected to the biasing current output terminal IBCMTI of the multi-stage differential amplifier <NUM>.

After the common-mode detection circuit <NUM> is turned on, a current signal passes through the gate electrodes of the NMOS transistor MD5 and NMOS transistor MD6 and forms a mirroring current at the drain electrode of the NMOS transistor MD6. The mirroring currents increase the currents of the mirroring circuit in the multi-stage differential amplifier <NUM>, so that the gain and output swing of the corresponding differential amplifier are increased, eliminating the influence of common-mode signal interference.

<FIG> shows a digital isolator including a transmitter TX and a receiver RX isolated by capacitors. The digital isolator includes isolation capacitors Ciso1 and Ciso2 connecting a positive output terminal TXOUTP and a negative output terminal TXOUTN of the transmitter, and isolation capacitors Ciso3 and Ciso4 connecting a positive input terminal RXINP and a negative input terminal RXINN of the receiver. The positive output terminal TXOUTP of the transmitter TX and the positive input terminal RXINP of the receiver as well as the negative output terminal TXOUTN of the transmitter and the negative input terminal RXINN of the receiver are connected by wiring. It would be readily occurred to those skilled in the art that means of isolating may also include optical isolation, resistive isolation, and inductive isolation.

The transmitter TX includes an oscillator OSC and a transmission driving circuit TXDriver. The transmission driving circuit modulates and transmits an OOK modulation signal. An oscillating signal input terminal of the transmission driving circuit TXDriver is connected to the oscillator OSC, a digital input terminal of the transmission driving circuit is connected to a digital signal input terminal TXIN of the transmitter, and an output terminal TXDRVP/TXDRVN of the transmission driving circuit is connected to the output terminal TXOUTP/TXOUTN of the transmitter. The oscillator OSC generates a carrier signal. A switching device within the transmission driving circuit TXDriver is driven by a digital signal TXDATA input from the digital signal input terminal TXIN. When the digital signal is in a high level, the transmission driving circuit TXDriver output, at the positive and negative output terminals, a high-frequency signal generated by the oscillator. When the digital signal is in a low level, the transmission driving circuit does not output a signal. Thus, a binary signal is enabled to be loaded onto a high-frequency carrier.

The receiver RX includes a multi-stage differential signal amplification circuit and a comparison circuit CMP and is configured to receive demodulated OOK modulation signal. Positive and negative input terminals of the differential signal amplification circuit are connected to the input terminal RXINP of the receiver. An output terminal of the multi-stage amplification circuit is connected to an input terminal of the comparison circuit CMP. Positive and negative input terminals of the comparison circuit CMP as well as the positive and negative output terminals of the differential signal amplification circuit are connected by coupling capacitors C3 and C4. When there are high-frequency signals at the two input terminals of the comparison circuit, the comparison circuit outputs a high level. When there is no signal at the two input terminals, the comparison circuit outputs a low level. In this way, outputting of the digital signal RXDATA is completed. An output terminal of the comparison circuit is connected to a digital output terminal RXOUT of the receiver.

The multi-stage amplification circuit includes a multi-stage differential amplifier AMP and a common-mode transient adaptive biasing circuit <NUM>. The multi-stage differential amplifier AMP has a structure as shown in <FIG> and includes AMP1-AMPN. The differential amplifiers of each stage include the mirroring structure as shown in <FIG>. The amplification circuit above the second-stage differential amplifier AMP2 includes the biasing current output terminal as shown in <FIG>. The positive input terminal and the negative input terminal of a primary differential amplifier AMP1 are connected to the input terminals of the common-mode transient adaptive biasing circuit <NUM>.

The common-mode transient adaptive biasing circuit <NUM> includes the positive common-mode transient adaptive biasing circuit of <FIG> or the negative common-mode transient adaptive biasing circuit shown in <FIG>. The positive common-mode transient adaptive biasing circuit includes the positive common-mode detection circuit <NUM> and the adaptive biasing circuit <NUM>. The negative common-mode transient adaptive biasing circuit includes the negative common-mode detection circuit <NUM> and the adaptive biasing circuit <NUM>. The common-mode transient adaptive biasing circuit <NUM> is optionally connected to the differential amplifiers above the second stage, AMP2. AMPN, in a one-to-many, many-to-one, or many-to-many manner.

Claim 1:
A differential signal amplification circuit, comprising a multi-stage differential amplifier (<NUM>),
a common-mode transient adaptive biasing circuit (<NUM>),
wherein a positive input terminal (INP) and a negative input terminal (INN) of a primary differential amplifier (AMP1) of the multi-stage differential amplifier (<NUM>), which corresponds to a first stage of the multi-stage differential amplifier, are connected to respective input terminals of the common-mode transient adaptive biasing circuit (<NUM>); and
the common-mode transient adaptive biasing circuit (<NUM>) is configured to detect a positive or negative common-mode transient interference signal at the positive input terminal (INP) and the negative input terminal (INN), and characterized in that the common-mode transient adaptive biasing circuit (<NUM>) is configured to provide a biasing current to a differential amplifier of at least one stage above a second stage of the multi-stage differential amplifier when the positive or negative common-mode transient interference signals are detected.