Patent Description:
A technology of performing high-speed serial communication between a SerDes for a Master and a SerDes for a Slave has been proposed (see PTL <NUM>). PTL <NUM> describes a wireless protocol may be implemented in a smart transceiver device that contains the physical (PHY) and media access control (MAC) layers of the wireless protocol stack.

In a case where serial communication is performed between two SerDeses, an FDD (Frequency Division Duplexing) method or a TDD (Time Division Duplex) method is used, for example. In a case where the amount of data transmitted from one SerDes to the other SerDes is significantly different from the amount of data transmitted from the other SerDes to the one SerDes, the TDD method may be adopted to make the uplink data transmission capacity different from the downlink data transmission capacity. The TDD method is a half-duplex communication method in which communication can be performed in only one direction because uplink communication and downlink communication cannot be simultaneously performed.

One of the serial communication standards is called SPI (Serial Peripheral Interface). SPI is a full-duplex communication method in which uplink communication and downlink communication can be simultaneously performed. In a certain case, while the abovementioned two SerDeses are respectively performing SPI communication with the other communication devices, SPI data is transmitted via each of the abovementioned two SerDeses to a communication device connected to the counterpart-side SerDes which is connected to the SerDes itself. In a case where these SerDeses communicate with each other by the TDD method, the SPI data for a full-duplex communication method cannot be transmitted by the TDD method which is a half-duplex communication method.

Thus, the present disclosure is to provide a communication device, a communication system, and a communication method by which high-speed serial communication can be performed by a combination of different communication methods.

According to a first aspect, the present invention provides a communication device according to independent claim <NUM>. According to a second aspect, the present invention provides a communication device according to independent claim <NUM>. According to a third aspect, the present invention provides a communication system communication system according to independent claim <NUM>. According to a fourth aspect, the present invention provides a communication method according to independent claim <NUM>. Further aspects of the present invention are set forth in the dependent claims, the drawings and the following description.

In order to solve the abovementioned problems, the present disclosure provides a communication device including a communication section that transmits, by a batch of data blocks, an SPI (Serial Peripheral Interface)-compliant serial signal group transmitted from a Master in synchronization with a clock, to a communication partner device within one frame period of a predetermined communication protocol or transmits the serial signal group by multiple data blocks divided according to multiple frame periods, to the communication partner device.

The communication device further includes a memory that saves an SPI-compliant first serial signal group transmitted from the Master in synchronization with the clock and saves an SPI-compliant second serial signal group transmitted from a Slave in synchronization with the clock, a packet encoder that converts the first serial signal group saved in the memory into a first packet of the predetermined communication protocol, and a packet decoder that converts a second packet of the predetermined communication protocol received from the communication partner device into the second serial signal group.

The first packet includes frequency information regarding the clock and may further include polarity information regarding the clock, and phase information regarding the clock with respect to a data signal of the SPI-compliant first serial signal group.

The first packet may include information indicating that the batch of data blocks is included in the one frame period or information indicating that the multiple data blocks divided according to the multiple frame periods are included.

In a case where the first packet includes the multiple data blocks, the first packet may include the total number of the data blocks and information regarding division positions of the data blocks.

The first packet may include information regarding a size of the data block.

The first packet may include information indicating whether the data block is valid or invalid.

The first packet may include information indicating a reset of the Slave.

The second packet may include at least one of information indicating an operation state of the Slave and interrupt information from the Slave.

In a case where the interrupt information is included in the second packet and in a case where the second packet itself arrives at the memory from the communication partner device, the memory may determine that the Slave has requested to read out a state of the Slave and transmit an interrupt signal to the Master.

The first packet may include information regarding a Slave select signal which is included in the SPI-compliant first serial signal group and by which the communication partner device or the Slave is selected.

The packet encoder may transmit the first packet to, as a destination, the communication partner device or the Slave selected by the Slave select signal.

The communication device may further include a shift register that sequentially saves each of serial signals included in the first serial signal group, in the memory in synchronization with the clock and sequentially transmits each of serial signals included in the second serial signal group, to the Master in synchronization with the clock.

The communication section may transmit the first packet at a first timing that is determined by the predetermined communication protocol and receive the second packet at a second timing that is determined by the predetermined communication protocol.

When a Slave select signal transmitted from the Master is changed from a first logic to a second logic, the packet encoder may determine that transmission of the first serial signal group from the Master is completed.

The communication section may transmit and receive the first packet and the second packet to and from the communication partner device by the communication protocol according to TDD (Time Division Duplex).

The present disclosure provides a communication device including a communication section that, in synchronization with a clock generated on the basis of clock frequency information included in a packet supplied from a communication partner device, transmits an SPI-compliant serial signal group transmitted from a Slave, to a communication partner device by a batch of data blocks within one frame period of a predetermined communication protocol, or transmits the serial signal group by multiple data blocks divided according to multiple frame periods, to the communication partner device.

The communication device further includes a packet decoder that converts a first packet of the predetermined communication protocol received from the communication partner device into an SPI-compliant first serial signal group, a clock generator that generates the clock based on the clock frequency information included in the first serial signal group, a memory that saves the first serial signal group in synchronization with the clock and saves an SPI-compliant second serial signal group transmitted from a Slave in synchronization with the clock, and a packet encoder that converts the second serial signal group saved in the memory into a second packet of the predetermined communication protocol.

The second packet may include information indicating that a batch of data blocks to be transmitted within one frame period of the second serial signal group is included or information indicating that multiple data blocks to be dividedly transmitted according to multiple frame periods are included.

The second packet may include information indicating whether or not the Slave is in a busy state of being unable to receive the first serial signal group and information indicating whether or not an error is included in the first serial signal group received by the Slave.

The second packet may include interrupt information that is a request to cause a Master to read out a state of the Slave.

The communication device may further include a shift register that saves, in the memory, each of serial signals included in the second serial signal group and transmits each of serial signals included in the first serial signal group to the Slave.

The communication section may transmit the second packet at a first timing that is determined by the predetermined communication protocol and receive the first packet at a second timing that is determined by the predetermined communication protocol.

The present disclosure provides a communication system including a first communication device and a second communication device that transmit and receive a packet by a predetermined communication protocol, in which the first communication device includes a first communication section that transmits, by a batch of data blocks, an SPI (Serial Peripheral Interface)-compliant first serial signal group transmitted from a Master in synchronization with a clock, to the second communication device within one frame period of a predetermined communication protocol or transmits the serial signal group by multiple data blocks divided according to multiple frame periods, to the second communication device, and the second communication device transmits, in synchronization with a clock generated on the basis of clock frequency information included in a packet supplied from the first communication device, an SPI-compliant second serial signal group transmitted from a Slave, by a batch of data blocks, to the first communication device within one frame period of a predetermined communication protocol, or transmits the serial signal group by multiple data blocks divided according to multiple frame periods, to the first communication device.

The first communication device may include a first memory that saves the first serial signal group transmitted from the Master in synchronization with a first clock and saves the second serial signal group transmitted from a Slave in synchronization with the first clock, a first packet encoder that converts the first serial signal group saved in the first memory into a first packet of the predetermined communication protocol, a first packet decoder that converts a second packet of the predetermined communication protocol received from the second communication device into the second serial signal group, and the first communication section that transmits the first packet at a timing determined by the predetermined communication protocol and receives the second packet at a timing determined by the predetermined communication protocol, and the second communication device may include a second packet decoder that converts the received first packet into the first serial signal group, a clock generator that generates a second clock based on the clock frequency information included in the first serial signal group, a second memory that saves the first serial signal group in synchronization with the second clock and saves the second serial signal group transmitted from the Slave in synchronization with the second clock, a packet encoder that converts the second serial signal group saved in the second memory into the second packet, and a second communication section that transmits the second packet at a timing determined by the predetermined communication protocol and receives the first packet at a timing determined by the predetermined communication protocol.

The present disclosure provides a communication method including a communication section that transmits, by a batch of data blocks, an SPI-compliant serial signal group transmitted from a Master in synchronization with a clock, to a communication partner device within one frame period of a predetermined communication protocol or transmits the serial signal group by multiple data blocks divided according to multiple frame periods, to the communication partner device.

Hereinafter, embodiments of a communication device, a communication system, and a communication method will be explained with reference to the drawings. An explanation of important constituent parts of the communication device, the communication system, and the communication method will be mainly given below but the communication device, the communication system, and the communication method can include any other constituent parts or functions that are not depicted or explained. The following explanation is not intended to exclude any other constituent parts or functions that are not depicted or explained.

<FIG> is a block diagram depicting a schematic configuration of a communication system <NUM> including communication devices 1a and 1b according to the first embodiment. The communication system <NUM> in <FIG> includes an SPI/Master <NUM>, a Master SerDes (M_SerDes) <NUM>, an SPI/Slave <NUM>, and a Slave SerDes (S_SerDes) <NUM>. The M_SerDes <NUM> corresponds to the communication device 1a while the S_SerDes <NUM> corresponds to the communication device 1b.

The SPI/Master <NUM> and the M_SerDes <NUM> perform SPI-compliant serial communication (hereinafter, referred to as SPI communication in some cases). Similarly, the SPI/Slave <NUM> and the S_SerDes <NUM> perform SPI-compliant serial communication (SPI communication). The M_SerDes <NUM> and the S_SerDes <NUM> perform high-speed serial communication by a TDD method. In <FIG>, a path of signal transmission from the M_SerDes <NUM> to the S_SerDes <NUM> and a path of signal transmission from the S_SerDes <NUM> to the M_SerDes <NUM> are referred to as an UP Link and a Down Link, respectively. In the SPI communication, serial communication is performed by a protocol (hereinafter, referred to as an SPI protocol) conforming to the SPI standard. In addition, in the present description, serial data that is transmitted and received by SPI communication may be referred to as SPI data.

As explained later, the M_SerDes <NUM> includes a communication section (DLL <NUM>-<NUM>) that transmits an SPI (Serial Peripheral Interface)-compliant serial signal group transmitted from a Master (SPI_Master <NUM>) in synchronization with a clock, to a communication partner device (S_SerDes <NUM>) by a batch of data blocks within one frame period of a predetermined communication protocol or transmits the SPI-compliant serial signal group to the communication partner device (S_SerDes <NUM>) by multiple data blocks divided according to multiple frame periods. Also, the S_SerDes <NUM> includes a communication section (DLL <NUM>-<NUM>) that, in synchronization with a clock generated on the basis of clock frequency information included in a packet supplied by a communication partner device (M_SerDes <NUM>), transmits an SPI-compliant serial signal group transmitted from a Slave (SPI_Slave <NUM>) to a communication partner device (M_SerDes <NUM>) by a batch of data blocks within one frame period of a predetermined communication protocol or transmits the SPI-compliant serial signal group to the communication partner device (M_SerDes <NUM>) by multiple data blocks divided according to multiple frame periods.

<FIG> is a block diagram of a part that is related to SPI communication between the SPI/Master <NUM> and the SPI/Slave <NUM>. It is to be noted that <FIG> depicts an example in which SPI-compliant serial communication is performed directly between the SPI/Master <NUM> and the SPI/Slave <NUM>, for simplification of the explanation.

As depicted in <FIG>, the SPI/Master <NUM> includes a shift register <NUM>-<NUM> and a buffer/memory <NUM>-<NUM>. Similarly, the SPI/Slave <NUM> includes a shift register <NUM>-<NUM> and a buffer/memory <NUM>-<NUM>.

The shift register <NUM>-<NUM> of the SPI/Slave <NUM> operates in synchronization with a clock SCK which is supplied from the SPI/Master <NUM>. The shift register <NUM>-<NUM> of the SPI/Master <NUM> sequentially outputs serial data through an MSB (Most Significant Bit) side in synchronization with the SCK. The outputted serial data is inputted to an LSB (Least Significant Bit) side of the shift register <NUM>-<NUM> of the SPI/Slave <NUM> through a MOSI pin. Serial data outputted from an MSB side of the shift register <NUM>-<NUM> of the SPI/Slave <NUM> is inputted to an LSB side of the shift register <NUM>-<NUM> of the SPI/Master <NUM> through a MISO pin. Data held in the shift register <NUM>-<NUM> of the SPI/Master <NUM> can be saved in the buffer/memory <NUM>-<NUM>. Further, the shift register <NUM>-<NUM> can hold data saved in the buffer/memory <NUM>-<NUM>. Similarly, data held in the shift register <NUM>-<NUM> of the SPI/Slave <NUM> can be saved in the buffer/memory <NUM>-<NUM>. Further, the shift register <NUM>-<NUM> can hold data saved in the buffer/memory <NUM>-<NUM>.

<FIG> depicts basic signal waveform diagrams of an SPI protocol. In the SPI protocol, there are four combinations of the polarity of the SCK when a Slave selector signal (CS signal) outputted from the SPI/Master <NUM> is idle (high level in <FIG>) and an edge (a rising edge or a falling edge) of the clock (SCK) where data is latched when the CS signal enters an active state (low level in <FIG>). These four combinations are called SPI modes. The SPI/Master <NUM> can optionally select one from among the four SPI modes. The SPI/Master <NUM> has known an SPI mode that can be supported by the SPI/Salve, and thus needs to select a mode corresponding to the supportable mode.

<FIG> are signal waveform diagrams of the four SPI modes. In SPI mode=<NUM> depicted in <FIG>, the SCK is Low when the CS signal is idle, and data is held when the SCK rises. In SPI mode=<NUM> depicted in <FIG>, the SCK is Low when the CS signal is idle, and data is held when the SCK falls. In SPI mode=<NUM> depicted in <FIG>, the SCK is High when the CS signal is idle, and data is held when the SCK rises. In SPI mode=<NUM> depicted in <FIG>, the SCK is High when the CS signal is idle, data is held when the SCK rises.

The frequency of the SCK is not defined by the SPI protocol and varies for respective devices that perform SPI communication. The SPI/Master <NUM> selects the frequency of the SCK for each of the devices to perform the SPI communication. For this reason, the SPI/Master <NUM> needs to previously know an SCK frequency that can be supported by each of the devices to perform SPI communication.

Hereinafter, a communication method using the SPI protocol will be explained. In the example of <FIG>, communication using the SPI protocol is performed between the SPI/Master <NUM> and the SPI/Slave <NUM>. The number of the SPI/Slaves <NUM> which are connected to the SPI/Master <NUM> may be one or more. In a case where two or more SPI/Slaves <NUM> are connected to the SPI/Master <NUM>, the SPI/Master <NUM> has multiple CS signals corresponding to the respective SPI/Slaves <NUM>, and uses a corresponding CS signal to select a Slave to communicate with, so that communication with the Slave can be performed. A CS signal with which the SPI/Master <NUM> selects an SPI/Slave <NUM> to communicate is included in SPI control information, as explained later. The SPI/Master <NUM> transmits SPI data including the SPI control information to the M_SerDes <NUM>.

In a case of performing SPI communication, the SPI/Master <NUM> activates a CS signal (Low in <FIG>) connected to the SPI/Slave <NUM> to communicate with. In the present description, asserting refers to bringing any signal into an active state, and deasserting refers to bringing any signal into an idle state, in some cases.

The SPI/Master <NUM> and the SPI/Slave <NUM> transfer data to be transferred, from the buffer/memories <NUM>-<NUM> and <NUM>-<NUM> to the shift registers <NUM>-<NUM> and <NUM>-<NUM>, respectively. The SPI/Master <NUM> generates an SCK and supplies the SCK not only to the shift register <NUM>-<NUM> but also to the shift register <NUM>-<NUM> of the SPI/Slave <NUM>. The shift registers <NUM>-<NUM> and <NUM>-<NUM> each shift the held data by <NUM> bit with a toggle of the SCK. As a result of the SCK toggling by the number of stages of the shift registers <NUM>-<NUM> and <NUM>-<NUM>, the data in the shift registers <NUM>-<NUM> and <NUM>-<NUM> is replaced. Subsequently, the SPI/Master <NUM> brings the CS signal into an idle state (High in <FIG>). By transferring the current data in the shift registers <NUM>-<NUM> and <NUM>-<NUM> to the buffer/memories <NUM>-<NUM> and <NUM>-<NUM>, the SPI/Master <NUM> and the SPI/Slave <NUM> can obtain the data from the buffer/memories <NUM>-<NUM> and <NUM>-<NUM>. Then, the SPI communication is finished.

While <FIG> depicts an example in which SPI communication is performed directly between the SPI/Master <NUM> and the SPI/Slave <NUM>, <FIG> depicts that the M_SerDes <NUM> and the S_SerDes <NUM> are disposed between the SPI/Master <NUM> and the M_SerDes <NUM>. In <FIG>, the SPI/Master <NUM> performs SPI communication with the M_SerDes <NUM>, the M_SerDes <NUM> and the S_SerDes <NUM> perform serial communication with each other by a TDD method, and the SPI/Slave <NUM> and the S_SerDes <NUM> perform SPI communication with each other.

<FIG> is a diagram for explaining a TDD method that is performed between the M_SerDes <NUM> and the S_SerDes <NUM> in <FIG>. In <FIG>, a simplified internal configuration of the SPI/Master <NUM> and the SPI/Slave <NUM> depicted in <FIG> is depicted. In addition, <FIG> depicts an example in which peripheral devices <NUM> and <NUM> are connected to the M_SerDes <NUM> and the S_SerDes <NUM>, respectively.

The M_SerDes <NUM> and the S_SerDes <NUM> are connected to each other via a cable <NUM> having a length of several meters to over ten meters, for example. Via the cable <NUM>, high-speed serial communication is performed between the M_SerDes <NUM> and the S_SerDes <NUM>. It is to be noted that two or more devices may perform serial communication with the M_SerDes <NUM>. In this case, each of these devices has a configuration similar to that of the S_SerDes <NUM> in <FIG>. Also, multiple pairs of devices that have configurations similar to those of the M_SerDes <NUM> and the S_SerDes <NUM> in <FIG> may be provided so that each of the pairs perform high-serial communication. The M_SerDes <NUM> and the S_SerDes <NUM> in <FIG> are applicable to a wide variety of uses such as on-vehicle camera modules for transmitting and receiving a large amount of data, for example.

The M_SerDes <NUM> and the S_SerDes <NUM> perform high-speed serial communication by the TDD method. A timing and a frequency band in the TDD method are depicted in the lower right of <FIG>. In the TDD method, an uplink signal transmission period and a downlink signal transmission period are provided so as not to temporally overlap each other within one TDD cycle, as depicted on the right side of <FIG>. The TDD timing chart in <FIG> illustrates an example in which a signal transmission period of an uplink signal (referred to as an UP Link) from the M_SerDes <NUM> to the S_SerDes <NUM> is excessively shorter than a signal transmission period of a downlink signal (referred to as a Down Link) from the S_SerDes <NUM> to the M_SerDes <NUM>, that is, an example in which the signal ratio of the UP Link is excessively smaller than the signal ratio of the Downlink. For example, in a case where a video signal taken by a sensor in the S_SerDes <NUM> is transmitted to the M_SerDes <NUM>, the signal ratio becomes a ratio such as that illustrated in the TDD timing chart in <FIG>.

A frequency band that is used for UP Link signal transmission and a frequency band that is used for Down Link signal transmission in the TDD method are depicted on the right side of <FIG>. As depicted in <FIG>, the frequency bands of the UP Link signal transmission and the Down Link signal transmission mostly overlap each other in the TDD method. For example, in a case where a video signal taken by a sensor in the S_SerDes <NUM> is transmitted to the M_SerDes <NUM>, the Down Link signal transmission is carried out by a wider frequency band including a frequency band that is used for the UP Link signal transmission because the Down Link signal transmission whose signal amount is large needs a frequency band wider than that of the UP Link signal transmission. Since the Down Link signal transmission period does not overlap with the UP Link signal transmission period in the TDD method, an echo cancellation circuit for separating these signals is unnecessary.

To carry out signal transmission by the TDD method is a prerequisite for the M_SerDes <NUM> and the S_SerDes <NUM> according to the present embodiment. However, the M_SerDes <NUM> and the S_SerDes <NUM> may carry out signal transmission by an FDD method in some cases. A timing and a frequency band in the FDD method are depicted in the lower left of <FIG>. In the FDD method, a frequency band that is used for signal transmission from the M_SerDes <NUM> to the S_SerDes <NUM> differs from a frequency band that is used for signal transmission from the S_SerDes <NUM> to the M_SerDes <NUM>. For this reason, the signal transmission from the M_SerDes <NUM> to the S_SerDes <NUM> and the signal transmission from the S_SerDes <NUM> to the M_SerDes <NUM> can be carried out at the same timing, and the uplink signal transmission and the downlink signal transmission can be carried out by using the entirety of one FDD cycle.

Further, in the FDD method, uplink signal transmission whose signal amount is large is carried out by using a wide frequency band on the high frequency side. Downlink signal transmission whose signal amount is small is carried out by using a narrow frequency band on the low frequency side. In the lower left example in <FIG>, a frequency band that is used for the uplink signal transmission and a frequency band that is used for the downlink signal transmission partially overlap each other in order to increase the efficiency of using frequencies. Due to this overlapping part, an echo cancellation circuit is required. The echo cancellation circuit is configured to separate an uplink signal and a downlink signal with high accuracy.

An example, in which high-speed serial communication is performed between the M_SerDes <NUM> and the S_SerDes <NUM> by the TDD method, the M_SerDes <NUM> performs SPI-compliant serial communication with the SPI/Master <NUM>, and the S_SerDes <NUM> performs SPI-compliant serial communication with the SPI/Slave <NUM>, will be given below.

Since serial communication not by SPI but by the TDD method is performed between the M_SerDes <NUM> and the S_SerDes <NUM>, it is necessary to perform protocol conversion in the M_SerDes <NUM> and the S_SerDes <NUM>. Further, serial communication by the TDD method is a half-duplex communication method, whereas serial communication by SPI is a full-duplex communication method. Therefore, data supplied from the SPI/Master <NUM> or an SPI_Slave cannot be transmitted and received at an unchanged timing in the TDD method.

A detailed explanation of the configuration of the communication system <NUM> in <FIG> will be given below. The SPI/Master <NUM> in <FIG> includes a controller <NUM>-<NUM> and an SCK generator <NUM>-<NUM>, in addition to the shift register <NUM>-<NUM> and the buffer/memory <NUM>-<NUM>, as depicted in <FIG>.

The controller <NUM>-<NUM> supplies a Slave select signal (CS signal) for activating SPI communication to the M_SerDes <NUM> through an M_CSn pin. The CS signals are provided by the number of devices to perform SPI communication with the SPI/Master <NUM>. For example, in <FIG>, different M_CSn pins are allocated to the M_SerDes <NUM>, the S_SerDes <NUM>, and the SPI/Slave <NUM>. In the present description, a pin that outputs a CS signal outputted from the SPI/Master <NUM> is expressed as M_CSn(x) in some cases. For example, M_CSn(<NUM>) is allocated to the M_SerDes <NUM> while M_CSn(<NUM>) is allocated to the SPI/Slave <NUM>.

The controller <NUM>-<NUM> controls operation of the SCK generator <NUM>-<NUM>. The SCK generator <NUM>-<NUM> outputs the SCK when any of the CS signals is in an active state. The shift register <NUM>-<NUM> performs a shift operation in synchronization with the SCK.

The controller <NUM>-<NUM> detects, from an interrupt signal M_INT supplied from the M_SerDes <NUM>, that the SPI/Slave <NUM> has outputted an interrupt signal S_INT. The interrupt signal M_INT is a trigger for causing the controller <NUM>-<NUM> to start SPI communication for the next frame. Alternatively, also in a case where SPI data is to be transmitted from the controller <NUM>-<NUM>, SPI communication is similarly started (time t5 of M_CSn(<NUM>) in <FIG> to be explained later).

The M_SerDes <NUM> is connected to the SPI/Master <NUM>. The M_SerDes <NUM> includes an SPI block <NUM>-<NUM> for performing data communication with the SPI/Master <NUM> in accordance with the SPI protocol. The SPI block <NUM>-<NUM> includes a shift register <NUM>-<NUM>-<NUM> and a buffer/memory <NUM>-<NUM>-<NUM>. When the controller <NUM>-<NUM> of the SPI/Master <NUM> activates a CS signal for the M_SerDes <NUM> and the SCK generator <NUM>-<NUM>-<NUM> outputs an SCK, the shift register <NUM>-<NUM>-<NUM> outputs SPI data in synchronization with the SCK, and the SPI data is supplied to the SPI/Master <NUM> through the MISO pin. Further, in synchronization with the SCK, the shift register <NUM>-<NUM>-<NUM> fetches the SPI data outputted from the SPI/Master <NUM> through the MOSI pin.

When the CS signal enters an idle state, the controller <NUM>-<NUM> causes the SCK generator <NUM>-<NUM> to stop outputting the SCK. As a result, the state of the shift register <NUM>-<NUM>-<NUM> immediately before the stop of the SCK is held.

When the CS signal enters an idle state, the SPI block <NUM>-<NUM> of the M_SerDes <NUM> transfers all the data pieces in the shift register <NUM>-<NUM>-<NUM> to the buffer/memory <NUM>-<NUM>-<NUM>. As a result, data transfer process from the SPI/Master <NUM> to the M_SerDes <NUM> according to the SPI protocol is finished.

It is to be noted that data transfer from the shift register <NUM>-<NUM>-<NUM> to the buffer/memory <NUM>-<NUM>-<NUM> in the M_SerDes <NUM> depends on an amount of data that the SPI/Master <NUM> desires to transfer and the data capacity of the shift register <NUM>-<NUM>-<NUM>. Therefore, in a case where there is a possibility that the data in the shift register <NUM>-<NUM>-<NUM> overflows during the active state of the CS signal, the data in the shift register <NUM>-<NUM>-<NUM> is transferred to the buffer/memory <NUM>-<NUM>-<NUM> before overflowing. Accordingly, data omission can be prevented.

Besides, the M_SerDes <NUM> includes a packet encoder (ECP) <NUM>-<NUM>, a packet decoder (DCP) <NUM>-<NUM>, the DLL <NUM>-<NUM>, and a PHY layer block (PHY) <NUM>-<NUM>. The ECP <NUM>-<NUM> of the M_SerDes <NUM> converts SPI data saved in the buffer/memory <NUM>-<NUM>-<NUM>, into a packet (SPI packet) that conforms to the TDD method. The DLL <NUM>-<NUM> generates an UP Link packet by combining the SPI packet generated by the ECP <NUM>-<NUM> with the other transmission packets other than the SPI packet. The PHY <NUM>-<NUM> transmits the UP Link packet to the S_SerDes <NUM> through an UP Link.

The S_SerDes <NUM> in <FIG> is connected to the SPI/Slave <NUM>. The S_SerDes <NUM> includes an SPI block <NUM>-<NUM> for transmitting and receiving data with the SPI/Slave <NUM> in accordance with an SPI protocol. The SPI block <NUM>-<NUM> includes a controller (CNTR) <NUM>-<NUM>-<NUM>, an SCK generator <NUM>-<NUM>-<NUM>, a shift register <NUM>-<NUM>-<NUM>, and a buffer/memory <NUM>-<NUM>-<NUM>. The controller <NUM>-<NUM>-<NUM> controls a timing and a frequency of an SCK to be outputted from the SCK generator <NUM>-<NUM>-<NUM> on the basis of SPI control information supplied from the SPI/Master <NUM>. The controller <NUM>-<NUM>-<NUM> activates a CS signal corresponding to the SPI/Slave <NUM>, and when the SCK generator <NUM>-<NUM>-<NUM> outputs the SCK, the shift register <NUM>-<NUM>-<NUM> outputs SPI data in synchronization with the SCK, and the SPI data is supplied to the SPI/Slave <NUM> through the S_MOSI pin. Further, the SPI data outputted from the SPI/Slave <NUM> via the S_MISO pin is inputted to the shift register <NUM>-<NUM>-<NUM> in synchronization with the SCK. Besides, the S_SerDes <NUM> includes a packet encoder (ECP) <NUM>-<NUM>, a packet decoder (DCP) <NUM>-<NUM>, the DLL <NUM>-<NUM>, and a PHY layer block (PHY) <NUM>-<NUM>. The ECP <NUM>-<NUM> of the S_SerDes <NUM> converts SPI data saved in the buffer/memory <NUM>-<NUM>-<NUM>, into a packet (SPI packet) that conforms to the TDD method. The DLL <NUM>-<NUM> generates an UP Link packet by combining the SPI packet generated by the ECP <NUM>-<NUM> with the other transmission packets other than the SPI packet. The PHY <NUM>-<NUM> transmits the UP Link packet to the S_SerDes <NUM> through an UP Link.

<FIG> is a diagram for explaining information that is included in transmission packets generated by the ECPs <NUM>-<NUM> and <NUM>-<NUM>. For each of information units in the transmission packet in <FIG>, an identification symbol, an information name, a function in a transmission packet for data transmission from the SPI/Master <NUM> to the SPI/Slave <NUM>, a function in a transmission packet for data transmission from the SPI/Slave <NUM> to the SPI/Master <NUM>, and a description are associated with one another.

C-<NUM> is a transmission mode which is issued as a command by the SPI/Master <NUM>. The transmission mode included in a packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor a state. When C-<NUM> is <NUM>, a batch of data blocks is transmitted within one frame period of TDD. When C-<NUM> is <NUM>, multiple data blocks divided according to multiple frame periods are transmitted.

C-<NUM> is a Slave selector signal (CSn signal) which is issued as a command by the SPI/Master <NUM>. The CSn signal included in the packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor the state. With the CSn signal, the SPI/Master <NUM> selects the SPI/Slave <NUM> to communicate with. With the CSn signal, not only each of the SPI/Slaves <NUM> can be selected, but also a SerDes (M_SerDes <NUM> or S_SerDes <NUM>) can be selected.

C-<NUM> is an SCK frequency which is issued as a command by the SPI/Master <NUM>. The SCK frequency included in a packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor the state. C-<NUM> is provided for the SPI/Master <NUM> to designate an SCK frequency of the SPI/Slave <NUM> side.

C-<NUM> is an SPI mode which is issued as a command by the SPI/Master <NUM>. The SPI mode included in a packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor the state. For example, when C-<NUM> is <NUM>, mode=<NUM> which is illustrated in <FIG> is selected. When C-<NUM> is <NUM>, mode=<NUM> which is illustrated in <FIG> is selected. When C-<NUM> is <NUM>, mode=<NUM> which is illustrated in <FIG> is selected. When C-<NUM> is <NUM>, mode=<NUM> which is illustrated in <FIG> is selected.

C-<NUM> is the total number of data blocks DB, which is information provided by the SPI/Master <NUM>. The total number of DBs included in a packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor the state. When C-<NUM> is <NUM> (when divided DBs are transmitted), C-<NUM> is <NUM>. The SPI/Slave <NUM> returns the number of DBs received after start of SPI communication.

C-<NUM> is the position of the current data block DB, which is information provided by the SPI/Master <NUM>. C-<NUM> is not included in a packet supplied from the SPI/Slave <NUM>. C-<NUM> that is <NUM> indicates invalid information. In a case where C-<NUM> is <NUM>, C-<NUM> is <NUM>. C-<NUM> that is <NUM> indicates the head divided data piece. C-<NUM> that is <NUM> indicates a divided data piece other than the head and last divided data pieces. C-<NUM> that is <NUM> indicates the last divided data piece.

C-<NUM> is the state of the current data block DB, which is information provided by the SPI/Master <NUM> and the SPI/Slave <NUM>. C-<NUM> that is <NUM> indicates dummy data. C-<NUM> that is <NUM> indicates valid data.

C-<NUM> is the size of a data block DB, which is information provided by the SPI/Master <NUM>. The data transmission size included in a packet supplied from the SPI/Slave <NUM> is used by the SPI/Master <NUM> to monitor the state. C-<NUM> indicates the data transmission size in unit of bytes. The maximum size is <NUM> bytes.

C-<NUM> is interrupt information of the SPI/Slave <NUM>, which is not included in a packet that is transmitted by the SPI/Master <NUM>, but is an interrupt flag included in a packet that is transmitted by the SPI/Slave <NUM>. C-<NUM> that is <NUM> indicates that there is no interrupt. C-<NUM> that is <NUM> indicates that there is an interrupt.

C-<NUM> is an operation state of the SPI/Slave <NUM> side, which is not included in a packet that is transmitted by the SPI/Master <NUM> but is included in a packet supplied from the SPI/Slave <NUM>. C-<NUM> that is <NUM> indicates a normal state. C-<NUM> that is <NUM> indicates a busy state (the DCP <NUM>-<NUM> is not empty. C-<NUM> that is <NUM> indicates that an error has occurred (SPI data has been broken).

C-<NUM> is a reset of the SPI block <NUM>-<NUM> and is issued as a command by the SPI/Master <NUM>. C-<NUM> is not included in a packet supplied from the SPI/Slave <NUM>. When C-<NUM> is <NUM>, the reset is not performed. When C-<NUM> is <NUM>, the SPI block <NUM>-<NUM> of the S_SerDes <NUM> is reset.

D-<NUM> is SPI data that is transmitted together with C-<NUM> to C-<NUM> described above. SPI data that is transmitted by the SPI/Master <NUM> is outputted through the M_MOSI pin. SPI data that is transmitted by the SPI/Slave <NUM> is outputted through the S_MISO pin.

E-<NUM> is CRC that is transmitted together with C-<NUM> to C-<NUM> and D-<NUM>. E-<NUM> is included in the SPI data to be transmitted by the SPI/Master <NUM> and in the SPI data to be transmitted by the SPI/Slave <NUM>. The CRC is used to detect an error in the control data C-<NUM> to C-<NUM> and the SPI data.

<FIG> is a timing chart of communication of the SPI/Master <NUM> with the SPI/Slave <NUM>. <FIG> and <FIG> are flowcharts each illustrating a processing procedure in which the SPI/Master <NUM> performs communication with the SPI/Slave <NUM>. <FIG> is a diagram schematically depicting a packet that is transmitted and received by an UP Link and a Down Link. <FIG> each depict a processing procedure of transmitting and receiving a batch of data blocks within one frame period of TDD.

First, the SPI/Master <NUM> generates SPI control information which is used by the ECP <NUM>-<NUM> and the DCP <NUM>-<NUM> of the M_SerDes <NUM>, and transmits the SPI control information to the M_SerDes <NUM> (steps S1 to S4, time t1 to t4). The SPI control information includes an SPI transmission mode, SCK frequency information, an SPI mode, and the size and number of data blocks DB during SPI communication, for example. The SPI/Master <NUM> preliminarily saves the SPI control information in the buffer/memory <NUM>-<NUM>.

In order to perform SPI communication with the M_SerDes <NUM>, the controller <NUM>-<NUM> of the SPI/Master <NUM> brings M_CSn(<NUM>) into an active state (Low) (asserting) (step S1, time t1).

The controller <NUM>-<NUM> of the SPI/Master <NUM> controls the SCK generator <NUM>-<NUM> to output a clock M_SCK (step S2, time t2). In synchronization with the clock M_SCK, SPI control information saved in the buffer/memory <NUM>-<NUM> is sequentially read out and transferred to the shift register <NUM>-<NUM>. A transmission mode, SCK frequency information, an SPI mode, a transmission data size, the number of data blocks, etc. are transmitted as the SPI control information. In synchronization with the clock M_SCK, the shift register <NUM>-<NUM> sequentially outputs the SPI control information (steps S2 to S3, time t2 to t3). The SPI control information is inputted to the M_SerDes <NUM> through the M_MOSI pin. In synchronization with M_SCK, the shift register <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> fetches the SPI control information supplied from the SPI/Master <NUM>.

In parallel with fetching the SPI control information supplied from the SPI/Master <NUM>, the shift register <NUM>-<NUM>-<NUM> transmits data held in the shift register <NUM>-<NUM>-<NUM>, to the SPI/Master <NUM> through the M_MISO pin in synchronization with the M_SCK. This data is invalid and is indicated by a broken line in time t2 to t3 in <FIG>. The SPI/Master <NUM> receives this data and then discards this data.

After completion of the data transfer from the SPI/Master <NUM>, the controller <NUM>-<NUM> of the SPI/Master <NUM> causes the SCK generator <NUM>-<NUM> to stop generating the M_SCK and deasserts M_CSn(<NUM>) to be an idle state (step S4, time t4). When the M_SCK is stopped, the shift register <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> transfers the held SPI control information supplied from the SPI/Master <NUM>, to the buffer/memory <NUM>-<NUM>-<NUM>.

The buffer/memory <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> transfers the SPI control information supplied from the SPI/Master <NUM> to the ECP <NUM>-<NUM>. The ECP <NUM>-<NUM> converts the SPI control information into an SPI packet.

Subsequently, for the purpose of carrying out data transmission to the SPI/Slave <NUM>, the SPI/Master <NUM> transmits the SPI data to the M_SerDes <NUM>. Specifically, the controller <NUM>-<NUM> of the SPI/Master <NUM> brings M_CSn(<NUM>) corresponding to the SPI/Slave <NUM> to an active state from the idle state (deasserting) (step S5, time t5).

Further, the controller <NUM>-<NUM> causes the SCK generator <NUM>-<NUM> to output the M_SCK (step S6, time t6). The buffer/memory <NUM>-<NUM> reads out a transmission data size of data to be transmitted to the SPI/Slave <NUM> and inputs the read data to the shift register <NUM>-<NUM>. In synchronization with the M_SCK, the shift register <NUM>-<NUM> sequentially outputs the data for the SPI/Slave <NUM> through the M_MOSI pin (step S7, time t7).

The shift register <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> sequentially fetches the data outputted from the SPI/Master <NUM>, into the shift register <NUM>-<NUM>-<NUM> in synchronization with the SCK. After the transfer of the data of the transmission data size is completed, the controller <NUM>-<NUM> of the SPI/Master <NUM> causes the SCK generator <NUM>-<NUM> to stop outputting the M_SCK (step S8, time t8). Then, the controller <NUM>-<NUM> of the SPI/Master <NUM> brings the M_CSn(<NUM>) into an idle state (deasserting), and the SPI communication is finished (step S9, time t9).

When the M_SCK is stopped, the M_SerDes <NUM> transfers the data held in the shift register <NUM>-<NUM>-<NUM> to the buffer/memory <NUM>-<NUM>-<NUM>. The buffer/memory <NUM>-<NUM>-<NUM> transfers the data transferred from the shift register <NUM>-<NUM>-<NUM>, to the ECP <NUM>-<NUM>. The ECP <NUM>-<NUM> generates data that includes the SPI control information received as a result of the communication performed in time t1 to t3, a CS signal (M_CSn(<NUM>)) for the SPI/Slave <NUM>, and the data for the SPI/Slave <NUM>. The ECP <NUM>-<NUM> generates a transmission packet by adding a flag indicating that the packet is valid, to the generated data.

The ECP <NUM>-<NUM> transmits, as an SPI packet <NUM> which is depicted in <FIG>, the generated transmission packet to the DLL <NUM>-<NUM>. The DLL <NUM>-<NUM> generates an UP Link packet <NUM> by combining the SPI packet <NUM> transmitted from the ECP <NUM>-<NUM> and another transmission packet, and outputs the UP Link packet <NUM> to the PHY layer block <NUM>-<NUM>. The PHY layer block <NUM>-<NUM> outputs the received UP Link packet <NUM> to the cable <NUM> in accordance with an UP Link output timing according to TDD (step S10, time t10).

The S_SerDes <NUM> communicates with the M_SerDes <NUM> by the TDD method and also performs SPI communication with the SPI/Slave <NUM>. The PHY layer block <NUM>-<NUM> of the S_SerDes <NUM> receives the UP Link Packet transmitted from the M_SerDes <NUM> via the cable <NUM> and outputs the UP Link Packet to the Link layer block (DLL) <NUM>-<NUM>.

The Link layer block <NUM>-<NUM> of the S_SerDes <NUM> extracts, from the UP Link Packet, the SPI packet including the SPI data and outputs the SPI packet to the packet decoder (DCP) <NUM>-<NUM>. On the basis of the CSn information (C-<NUM>) included in the received SPI packet, the DCP <NUM>-<NUM> detects that the SPI/Slave <NUM> is an SPI communication target. Then, in order to start SPI communication with the SPI/Slave <NUM>, the controller <NUM>-<NUM>-<NUM> detects that the SPI data has been fully transmitted on the basis of the transmission mode information (C-<NUM>) included in the SPI packet, obtains the number of SCK cycles required to perform SPI communication once on the basis of the number of the SPI data pieces (C-<NUM>) and the SPI data size (C-<NUM>), and then brings the Slave select signal S_CS into an active state (asserting) (step S11, time t11).

Next, the controller <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> obtains the SCK frequency information (C-<NUM>) included in the SPI packet and causes the SCK generator <NUM>-<NUM>-<NUM> to output S_SCK by the obtained frequency (step S12, time t12). Here, the phase relation between S_CS and SCK follows the SPI mode (C-<NUM>) in the SPI packet. Accordingly, the S_SerDes <NUM> is allowed to transfer SPI data to the SPI/Slave <NUM>. Data to be transferred to the SPI/Slave <NUM> is the SPI packet (D-<NUM>) and is saved in the buffer/memory <NUM>-<NUM>-<NUM>.

The shift register <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> sequentially outputs, through the S_MOSI pin, the SPI data transferred from the buffer/memory <NUM>-<NUM>-<NUM> in accordance with SCK supplied by the SCK generator <NUM>-<NUM>-<NUM> (step S13, time t13). In parallel with this, SPI data to be outputted from the SPI/Slave <NUM> to the S_MISO pin is saved in the shift register <NUM>-<NUM>-<NUM>, and then is transferred to the buffer/memory41-<NUM>-<NUM> at an appropriate timing.

The SPI/Slave <NUM> sequentially fetches the SPI data from the S_MOSI pin of the S_SerDes <NUM>, into the shift register <NUM>-<NUM> in synchronization with the S_SCK, and further, sequentially outputs the data held in the shift register <NUM>-<NUM> through the S_MISO pin (step S14, time t14).

After driving the S_SCK for the defined SPI data size (C-<NUM>), the controller (<NUM>-<NUM>-<NUM>) stops the SCK and brings the S_CS back into an idle state (deasserting) in order to finish the SPI communication (step S15, time t15). In parallel with this, the SPI/Slave <NUM> transfers the SPI data transmitted from the S_MOSI pin of the S_SerDes <NUM> to the buffer/memory <NUM>-<NUM> at an appropriate timing while receiving the SPI data from the S_MOSI pin so that data reception from the SPI/Master <NUM> is finally completed.

The buffer/memory <NUM>-<NUM>-<NUM> transfers the SPI data received from the SPI/Slave <NUM> to the packet encoder (ECP) <NUM>-<NUM> in order to transmit the SPI data to the SPI/Master <NUM>. The ECP <NUM>-<NUM> adds, to the SPI packet <NUM>, the received SPI data and SPI control information that is obtained from the SPI packet by the ECP <NUM>-<NUM>. In addition, the ECP <NUM>-<NUM> adds, to the SPI packet, the information (C-<NUM>) indicating an operation state of the SPI/Slave <NUM> and the CRC (E-<NUM>), which are illustrated in <FIG>.

Moreover, in a case where the SPI/Slave <NUM> outputs an interrupt signal (C-<NUM>), the ECP <NUM>-<NUM> further adds information regarding the interrupt signal to the SPI packet <NUM>. In this case, SPI data supplied from the SPI/Slave <NUM> is not transmitted by the SPI packet <NUM>. The reason for providing the interrupt signal is that the CS signal and the SCK are controlled by the SPI/Master <NUM> alone in the SPI protocol, and thus, the SPI/Slave <NUM> cannot actively output any data. Accordingly, the SPI/Slave <NUM> outputs the interrupt signal to wait for a command from the SPI/Master <NUM>.

The Link layer block (DLL) <NUM>-<NUM> generates a Down Link packet <NUM> by combining the SPI packet <NUM> received from the ECP <NUM>-<NUM> with another transmission packet and outputs the Down Link packet <NUM> to the PHY layer block <NUM>-<NUM>. The PHY layer block <NUM>-<NUM> outputs the received Down Link packet <NUM> to the cable <NUM> in accordance with a Down Link output timing (step S16, time t16).

The PHY layer block <NUM>-<NUM> of the M_SerDes <NUM> receives the Down Link packet including the SPI packet <NUM> supplied from the SPI/Slave <NUM> and outputted from the S_SerDes <NUM> and outputs the Down Link packet to the DLL <NUM>-<NUM>. The DLL <NUM>-<NUM> extracts the SPI packet <NUM> from the received Down Link packet <NUM> and outputs the SPI packet <NUM> to the packet decoder (DCP) <NUM>-<NUM>.

When receiving SPI data O_DB#<NUM> from the Master <NUM>, the DCP <NUM>-<NUM> of the M_SerDes <NUM> simultaneously receives a packet including I_DB#<NUM> to be transmitted to the Master <NUM> and stores the packet in the buffer/memory <NUM>-<NUM>-<NUM>. In order to indicate that the valid SPI data I_DB#<NUM> has been returned from the SPI/Slave <NUM>, the buffer/memory <NUM>-<NUM>-<NUM> asserts the interrupt signal M_INT (step S17, time t17). After receiving the interrupt signal M_INT, the controller <NUM>-<NUM> of the SPI/Master <NUM> starts SPI communication to read out, from the M_SerDes <NUM>, the SPI data supplied from the SPI/Slave <NUM> and activates M_CSn(<NUM>) (asserting) (step S18, time t18).

The controller <NUM>-<NUM> of the SPI/Master <NUM> controls the SCK generator <NUM>-<NUM> to output M_SCK (<NUM>-<NUM>-<NUM>) (step S19, time t19). In synchronization with the SCK, the shift register <NUM>-<NUM> sequentially fetches the data by the transfer data size (c-<NUM>) which is defined in Frame#<NUM>, from the M_MISO pin. Here, the buffer/memory <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> transfers the data supplied form the SPI/Slave <NUM> to the shift register <NUM>-<NUM>-<NUM> at an appropriate timing, and the shift register <NUM>-<NUM>-<NUM> sequentially outputs the data in synchronization with the SCK generator <NUM>-<NUM>, as previously explained. The outputted data is fetched through the M_MISO pin (step S20, time t20). In parallel with this, the SPI/Master <NUM> reads out, from the buffer/memory <NUM>-<NUM>, SPI data to be next transferred to the SPI/Slave <NUM>, saves the SPI data in the shift register <NUM>-<NUM>, and sequentially outputs the SPI data through the M_MOSI pin from the shift register <NUM>-<NUM> (step S21, time t21). After necessary data is read out, the buffer/memory <NUM>-<NUM>-<NUM> recovers the interrupt signal M_INT into an idle state (deasserting) (step S22, time t22).

As a result of the operations explained so far, transfer of SPI data between the SPI/Master <NUM> and the SPI/Slave <NUM> is completed. The above series of operations is repeated as many times as the number of times of necessary SPI data transfers (step S23, time t23).

When reading out the last SPI data piece from the SPI/Slave <NUM>, the SPI/Master <NUM> asserts M_CSn(<NUM>) in order to output dummy data (step S24, time t24). The dummy data is invalid data transfer of which to an SPI Slave is not required. Therefore, the dummy data is discarded instead of being transferred from the shift register <NUM>-<NUM>-<NUM> to the buffer/memory <NUM>-<NUM>-<NUM> in the M_SerDes <NUM> (step S25, time t25). The last data piece supplied from the SPI/Slave <NUM> is outputted from the shift register <NUM>-<NUM>-<NUM> of the M_SerDes <NUM> through the M_MISO pin and is fetched into the shift register <NUM>-<NUM> of the SPI/Master <NUM> (step S26, time t26).

In the first embodiment, within one frame period of the TDD method, a batch of data transmitted, by SPI communication, from the SPI/Master <NUM> to the M_SerDes <NUM> can be transmitted to the S_SerDes <NUM> through an UP Link, and a batch of data transmitted, by SPI communication, from the SPI/Slave <NUM> to the S_SerDes <NUM> can be transmitted to the M_SerDes <NUM> through a Down Link, in the abovementioned manner. Accordingly, SPI communication which is full-duplex communication and TDD communication which is half-duplex communication are combined together, and serial communication between the SPI/Master <NUM> and the SPI/Slave <NUM> can be performed via the M_SerDes <NUM> and the S_SerDes <NUM>.

In the second embodiment, data to be transmitted and received through SPI communication is divided according to multiple frame periods in a TDD method.

The communication system <NUM> according to the second embodiment has a configuration similar to that in <FIG>. However, there is a difference therebetween in SPI control information to be transmitted from the SPI/Master <NUM> to the M_SerDes <NUM>.

<FIG> is a timing chart of a case where a process of transmitting divided data pieces within each frame period is repeated for multiple frames. <FIG>, <FIG>, and <FIG> are flowcharts each illustrating a processing procedure of the communication system <NUM> that operates in accordance with a timing illustrated in <FIG>.

At steps S31 to S38 (time t31 to t38) in <FIG> which are similar to steps S1 to S8 (time t1 to t8) in <FIG>, the SPI/Master <NUM> generates SPI control information and sets the SPI control information in the ECP <NUM>-<NUM> and the DCP <NUM>-<NUM> of the M_SerDes <NUM>. In the processing operation in step S39 and later which is basically similar to that in <FIG> and <FIG>, data to be transmitted within one SPI frame is divided into multiple pieces in <FIG>, <FIG>, <FIG>, and <FIG>, so that each of the divided data pieces is transmitted within one frame period of TDD. A signal that is transmitted within one frame period of TDD is referred to as a TDD burst signal.

Until transfer of all the divided data pieces in the SPI frame is completed, the active state of the Slave Select signal M_CSn(<NUM>) between the SPI/Master <NUM> and the M_SerDes <NUM> and the active state of the Slave Select signal S_CS between the S_SerDes <NUM> and the SPI/Slave <NUM> are kept.

The SPI/Master <NUM> asserts the CS signal (M_CSn(<NUM>)) to start transfer of the SPI data (step S35, time t35). The SPI/Master <NUM> causes the SCK generator <NUM>-<NUM> to output the M_SCK for the purpose of transmitting one divided data piece (data block DB) (step S36, time t36).

Subsequently, the SPI/Master <NUM> sequentially outputs SPI data from the shift register <NUM>-<NUM> and outputs the SPI data through the M_MOSI pin in synchronization with the SCK (step S37, time t37). Further, the SPI/Master <NUM> outputs, to the M_SerDes <NUM>, a CS signal corresponding to the SPI/Slave <NUM> that is a communication target (step S38, time t38). Subsequently, the ECP <NUM>-<NUM> of the M_SerDes <NUM> generates a packet including the SPI data and the CS signal (step S39, time t39). The PHY layer block <NUM>-<NUM> combines this packet with another transmission packet so that an UP Link packet is generated. The UP Link packet is transmitted to the S_SerDes <NUM> through UP Link.

The SPI/Master <NUM> continues asserting the CS signal until all the divided data pieces are transmitted (step S40, time t40). The SPI/Master <NUM> stops the output of the M_SCK from the SCK generator <NUM>-<NUM> until the next divided data piece is transmitted (step S41, time t41).

The S_SerDes <NUM> obtains, from the received packet, the CS signal and the SPI data and asserts S_CS (step S42, time t42). The controller <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> causes the SCK generator <NUM>-<NUM>-<NUM> to output S_SCK (step S43, time t43). The S_SerDes <NUM> temporarily saves the SPI data in the received packet into the buffer/memory <NUM>-<NUM>-<NUM>, and then transfers the SPI data to the shift register <NUM>-<NUM>-<NUM>. The shift register <NUM>-<NUM>-<NUM> sequentially outputs the data in synchronization with the S_SCK. The outputted data is inputted to the SPI/Slave <NUM> through the S_MOSI pin (step S44, time t44). Further, the data outputted from the shift register <NUM>-<NUM> of the SPI/Slave <NUM> in synchronization with the S_SCK is inputted to the S_SerDes <NUM> through the S_MISO pin (step S45, time t45).

The DLL <NUM>-<NUM> of the S_SerDes <NUM> generates a transmission packet including the data supplied from the S_MISO pin. The PHY layer block <NUM>-<NUM> transmits the transmission packet to a Down Link at a timing determined by the TDD method (step S46, time t46).

The DLL <NUM>-<NUM> of the M_SerDes <NUM> transmits the SPI packet included in the transmission packet transmitted from the S_SerDes <NUM>, to the DCP <NUM>-<NUM>. The DCP <NUM>-<NUM> receives a packet including I_DB#<NUM> which is transmitted to the Master <NUM> at the same time as when SPI data 0_DB#<NUM> is received from the Master <NUM>, and saves the packet in the buffer/memory <NUM>-<NUM>-<NUM>. In order to indicate that the valid SPI data I_DB#<NUM> is returned from the SPI/Slave <NUM>, the buffer/memory <NUM>-<NUM>-<NUM> asserts the interrupt signal M_INT (step S47, time t47).

Upon detecting that the M_INT has been asserted, the SPI/Master <NUM> causes the SCK generator <NUM>-<NUM> to output the M_SCK (step S48, time t48). The buffer/memory <NUM>-<NUM> transfers data to be next transmitted, to the shift register <NUM>-<NUM>, and the shift register <NUM>-<NUM> outputs the SPI data through the M_MOSI pin in synchronization with the M_SCK (step S49, time t49). In parallel with this, the data outputted from the M_SerDes <NUM> through the M_MISO pin is fetched into the shift register <NUM>-<NUM> (step S50, time t50).

After reading out all the data pieces supplied from the M_SerDes <NUM>, the SPI/Master <NUM> recovers the M_INT to an idle state (deasserting) (step S51, time t51).

The S_SerDes <NUM> maintains the active state of the S_CS (asserting) until all the divided data pieces are transmitted (step S52, time t52). Further, output of the S_SCK from the SCK generator <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> is stopped until the next SPI data is transmitted from the M_SerDes <NUM> (step S53, time t53).

Thereafter, the processing operations in steps S40 to S53 are repeated (step S54, time t54). When the M_SerDes <NUM> transmits the last divided packet piece by an UP Link (step S55, time t55), the S_SerDes <NUM> outputs the S_SCK (step S56, time t56). Then, the S_SerDes <NUM> outputs the SPI data through the S_MOSI pin (step S57, time t57), and further, receives the last SPI data piece from the SPI/Slave <NUM> through the S_MISO pin (step S58, time t58).

After receiving the last SPI data piece, the S_SerDes <NUM> brings the S_CS into an idle state (deasserting) (step S59, time t59). Also, the S_SerDes <NUM> transmits a transmission packet including the last SPI data piece to the M_SerDes <NUM> by a Down Link (step S60, time t60).

The M_SerDes <NUM> brings the M_INT into an active state (step S61, time t61), which is similar to step S47. Further, the M_SerDes <NUM> causes the SCK generator <NUM>-<NUM> of the SPI/Master <NUM> to output the M_SCK (step S62, time <NUM>). In synchronization with the M_SCK, the data outputted from the shift register <NUM>-<NUM>-<NUM> through the M_MISO pin is fetched into the shift register <NUM>-<NUM> of the SPI/Master <NUM> (steps S63 to S64, time t63 to t64). After all the data pieces are fetched, the SPI/Master <NUM> brings the CS signal into an idle state (step S65, time t65). The data outputted from the shift register <NUM>-<NUM> at step S63 is discarded (step S66, time t66) because this data is dummy data.

In the second embodiment, therefore, divided data pieces which are obtained by dividing a batch of data transmitted from the SPI/Master <NUM> to the M_SerDes <NUM> by SPI communication into multiple pieces can be transmitted to the S_SerDes <NUM> by an UP Link in multiple frame periods of the TDD method, and divided data pieces which are obtained by dividing a batch of data transmitted from the SPI/Slave <NUM> to the S_SerDes <NUM> by SPI communication can be transmitted to the M_SerDes <NUM> by a Down Link in multiple frame periods of the TDD method.

In the third embodiment, the SPI/Master <NUM> performs serial communication with the multiple SPI/Slaves <NUM>.

<FIG> is a block diagram of a main part of the communication system <NUM> including a communication device according to the third embodiment. <FIG> depicts the S_SerDes <NUM> and the multiple SPI/Slaves <NUM>. The internal configurations of each SPI/Slave <NUM> and the M_SerDes <NUM> are similar to those in <FIG>, and thus are omitted in <FIG>. In addition, constituent parts in <FIG> common to those in <FIG> are denoted by the same reference signs.

The SPI/Master <NUM> designates a CSn signal for the SPI/Slave <NUM> to communicate with, by using SPI control information that is transmitted to the M_SerDes <NUM>. The controller <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> activates the CSn signal designated by the SPI/Master <NUM>. <FIG> depicts an example in which two SPI/Slaves 12_1 and 12_2 are connected to the S_SerDes <NUM>.

In a case where data communication with the SPI/Slave 12_1 is desired, the SPI/Master <NUM> sets the CSn signal to CS1 in the SPI control signal. Accordingly, the controller <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> brings a S_CS1 pin for outputting the CS1 signal, into an active state. The CS1 signal transmitted from the S_CS1 pin is inputted to the SPI/Slave 12_1. Therefore, the SPI/Slave 12_1 receives SPI data in synchronization with an S_SCK supplied from the S_SerDes <NUM>, and transmits SPI data to the S_SerDes <NUM> in synchronization with the S_SCK.

Further, in a case where data communication with the SPI/Slave 12_2 is desired, the SPI/Master <NUM> sets a CSn signal to CS2 in the SPI control signal. Accordingly, the controller <NUM>-<NUM>-<NUM> of the S_SerDes <NUM> brings an S_CS2 pin for outputting the CS2 signal, into an active state. The CS2 signal transmitted from the S_CS2 pin is inputted to the SPI/Slave 12_2. Therefore, the SPI/Slave 12_2 receives SPI data in synchronization with an S_SCK supplied from the S_SerDes <NUM>, and transmits SPI data to the S_SerDes <NUM> in synchronization with the S_SCK.

The communication system <NUM> in <FIG> depicts an example in which the SPI/Master <NUM> designates the SPI/Slave <NUM> to communicate with, by using a CSn signal included in an SPI control signal. However, the multiple SPI/Slaves <NUM> may be connected in a daisy chain, as depicted in <FIG>.

<FIG> is a block diagram of a main part of the communication system <NUM> including a communication device according to one modification of <FIG>. Two SPI/Slaves <NUM> that can simultaneously perform serial communication with the SPI/Master <NUM> are depicted in <FIG>. However, three or more SPI/Slaves <NUM> may be configured so as to simultaneously perform serial communication with the SPI/Master <NUM>.

The respective shift registers <NUM>-<NUM> of the two SPI/Slaves 12_1 and 12_2 in <FIG> are daisy-chained with each other. Data outputted from an MSB of the shift register <NUM>-<NUM> of the SPI/Slave 12_2 in synchronization with an SCK, is inputted to an LSB of the shift register <NUM>-<NUM> of the SPI/Slave 12_1, and further, the data outputted from the MSB is transmitted to the S_SerDes <NUM> by SPI communication.

The communication device in <FIG> needs to repeat steps S24 to S26 in <FIG> as many times as the number of the SPI/Slaves <NUM>.

In the third embodiment, therefore, the SPI/Master <NUM> designates the SPI/Slaves <NUM> by using respective CSn signals included in the SPI control information, whereby bidirectional serial communication with the multiple SPI/Slaves <NUM> can be performed. Further, if the multiple SPI/Slaves <NUM> are daisy-chained, the SPI/Master <NUM> can perform serial communication with the multiple SPI/Slaves <NUM> simultaneously.

Claim 1:
A communication device (1a) comprising:
a communication section (<NUM>-<NUM>) that configured to transmit , as a batch of data blocks (DB), an SPI (Serial Peripheral Interface)-compliant serial signal group transmitted from a Master (<NUM>) to the communication section (<NUM>-<NUM>) in synchronization with a clock (SCK), to a communication partner device (1b) within one frame period of a predetermined communication protocol or to transmit the serial signal group as multiple data blocks (DB) divided according to multiple frame periods of the predetermined communication protocol, to the communication partner device (1b)
a memory (<NUM>-<NUM>-<NUM>) that is configured to save an SPI-compliant first serial signal group transmitted from the Master (<NUM>) in synchronization with the clock (SCK) and to save an SPI-compliant second serial signal group transmitted from a Slave (<NUM>) in synchronization with the clock (SCK);
a packet encoder (<NUM>-<NUM>) that is configured to convert the first serial signal group saved in the memory (<NUM>-<NUM>-<NUM>) into a first packet of the predetermined communication protocol, wherein the first packet includes frequency information regarding the clock; and
a packet decoder (<NUM>-<NUM>) that is configured to convert a second packet of the predetermined communication protocol received from the communication partner device (1b) into the second serial signal group; wherein
the communication section (<NUM>-<NUM>) is configured to transmit the first packet to and to receive the second packet from the communication partner device (1b) by the predetermined communication protocol according to TDD (Time Division Duplex) or according to FDD (Frequency Division Duplex).