Patent Description:
Temporal alignment of signals is crucial to many aspects of wireless communication systems. For example, time alignment of input signals and feedback signals reduces cross-channel interference in the power amplifiers implemented in base stations and user equipment to amplify signals for transmission over the air interface. The power amplifiers are typically operated in a non-linear mode to achieve higher efficiency and reduce power consumption. However, the non-linear response of the power amplifier increases the frequency bandwidth of the output signal (relative to the frequency bandwidth of the input signal), which increases interference between different radio frequency carriers.

Digital predistortion can compensate for the effects of the non-linear power amplifier on the output signal by applying an inverse distortion to the input signal. The inverse distortion is determined by comparing the input signal to time-aligned feedback from the output of the power amplifier. Time alignment is conventionally performed using polynomial based interpolators such as a Farrow structure. Errors or inaccuracies in the time alignment of the input and feedback signals reduce the effectiveness of predistortion. The precision of the time alignment can be increased by increasing the degree or the number of taps implemented by the interpolator, e.g., the Farrow structure. However, polynomial interpolation is computationally intensive and improving the accuracy of the interpolators requires increasing the computation time and power consumption, which is not feasible for many current and future products.

<NPL> discloses digital predistortion for OFDM systems.

<NPL> discloses a predistorter based on frequency domain estimation for OFDM systems.

<CIT> (<CIT>) discloses an RF Transmitter with Nonlinear Predistortion.

The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Various embodiments of the disclosure are set out by the independent claims. The exemplary embodiments and features, if any, described in this specification, that do not fall under the scope of the independent claims, are to be interpreted as examples useful for understanding various exemplary embodiments of the disclosure.

In some embodiments, a method according to claim <NUM> is provided for aligning vector signals using vector transforms.

In some embodiments, an apparatus according to claim <NUM> is provided to align vector signals using vector transforms.

In some embodiments, a non-transitory computer readable medium according to claim <NUM> is provided that embodies a set of executable instructions for aligning vector signals using vector transforms. The set of executable instructions manipulate a processor to receive a first vector signal and a second vector signal from a circuit in response to the circuit receiving the first vector signal. The set of executable instructions also manipulate the processor to transform the second vector signal from a time domain to a transform domain and rotate the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal. comprising instructions which, when executed by a computer, cause the computer to carry out the steps of claim <NUM>.

Feedback vector signals can be accurately time-aligned with corresponding input vector signals by transforming the feedback vector signals from a time domain to a transform domain, rotating the transformed feedback vector signals in the transform domain based on a measured time delay between the feedback vector signals and the corresponding input vector signals, and then transforming the transformed feedback vector signals back into the time domain. Examples of transform kernels that may be used to transform the feedback vector signals between the time domain and the transform domain include Fourier transforms, wavelet transforms, Hartley transforms, and the like. In some embodiments, a DC offset is calculated for the feedback vector signal and removed from the feedback vector signal prior to transforming to the transform domain. The feedback vector signal may also be scaled by a gain factor determined by a ratio of power in the feedback signal (after the DC offset correction) to power in the input signal prior to transforming to the transform domain. The aligned feedback vector signal may also be scaled (after transformation back into the time domain) by a scaling factor determined based on the input signal and the aligned feedback vector signal. Aligning the feedback vector signal to the input vector signal in the transform domain may result in a minimal residue between the aligned feedback vector signal and the input vector signal.

<FIG> is a block diagram of a wireless communication system <NUM> according to some embodiments. The communication system <NUM> includes a base station <NUM> that provides wireless connectivity according to one or more radio access technologies. For example, the base station <NUM> may be an integrated device that implements LTE communication and a Wi-Fi access point. The base station <NUM> includes a transceiver <NUM> for transmitting and receiving signals using one or more antennas <NUM>. Some embodiments of the transceiver <NUM> include one or more power amplifiers for amplifying signals that are then provided to the one or more antennas <NUM> for transmission over an air interface <NUM>.

The base station <NUM> also includes a processor <NUM> and a memory <NUM>. The processor <NUM> may be used to execute instructions stored in the memory <NUM> and to store information in the memory <NUM> such as the results of the executed instructions. Some embodiments of the processor <NUM> operate or information representative of vector signals such as digital vector signals. For example, the digital vector signals may be complex signals with in-phase (I) and quadrature (Q) components. The length of the digital vector signals may be determined by the number of samples of the signal in a predetermined time interval, such as a frame.

Some embodiments of the processor <NUM> implement a predistortion module (PD) <NUM> that is used to pre-distort input signals before providing the input signals to the transceiver <NUM>. The predistortion module <NUM> may therefore receive feedback signals from the transceiver <NUM> that correspond to the amplified output signals provided to the antenna <NUM>. The predistortion module <NUM> compares the input signal to the feedback signal to determine the predistortion that is applied to the input signal. Predistortion of the input signals compensates for nonlinearities in power amplifiers in the transceiver <NUM> so that amplifying the pre-distorted signal produces an amplified signal that is substantially equal to (e.g., within a predetermined tolerance) a linear amplification of the original input signal. Techniques for implementing predistortion are known in the art.

Signal delays in the processor <NUM> or the transceiver <NUM> can generate a temporal misalignment between the input signal and the amplified output signal, which can reduce the efficacy of predistortion in the predistortion module <NUM>. For example, if the delay between the input and output waveforms is not accurately cancelled, the residual delay causes additional dispersion in the amplitude modulation/amplitude modulation (AM/AM) and amplitude modulation/phase modulation (AM/PM) characteristics of look up tables (LUTs) that are used to define the predistortion coefficients applied to the input signal.

The processor <NUM> implements a vector alignment processor (VA) <NUM> to time-align a feedback signal from the power amplifier to the corresponding input signal. Some embodiments of the processor <NUM> receive the input vector signal and the feedback vector signal and transform the feedback vector signal from a time domain to a transform domain. For example, the vector alignment processor <NUM> may transform the feedback vector signal from the time domain to a transform domain using a Fourier transform, a wavelet transform, a Hartley transform, or other transform. The vector alignment processor <NUM> then rotates the transformed feedback vector signal by a phase that is proportional to a time delay between the input and feedback vector signals to phase-align the feedback vector signal to the input vector signal. Thus, the feedback vector signal is time-aligned to the input vector signal when the feedback vector signal is transformed back into the time domain. The time-aligned feedback vector signal may then be provided to the predistortion module <NUM>, which uses the time-aligned feedback vector to generate the predistortion that is applied to the input signal, e.g., by defining the appropriate LUTs.

The wireless communication system also includes one or more user equipment <NUM>. The user equipment <NUM> includes a transceiver <NUM> for transmitting and receiving signals over the air interface <NUM> via antenna <NUM>. The user equipment <NUM> also includes a processor <NUM> and a memory <NUM>. The processor <NUM> may be used to execute instructions stored in the memory <NUM> and to store information in the memory <NUM> such as the results of the executed instructions. Some embodiments of the processor <NUM> include a predistortion module <NUM> and a vector alignment processor <NUM>. The predistortion module <NUM> may pre-distort input signals based on time-aligned signals provided by the vector alignment processor <NUM> to compensate for nonlinearities in power amplifiers implemented in the transceiver <NUM>, as discussed herein.

<FIG> is a block diagram of a circuit <NUM> for converting one or more digital signals into amplified analog signals suitable for transmission over an air interface by an antenna according to some non-claimed embodiments. The circuit <NUM> may be implemented in some embodiments of the base station <NUM> or the user equipment <NUM> shown in <FIG>. The circuit <NUM> receives input signals at corresponding input nodes <NUM>, <NUM>. In some embodiments, the input signals received at the input nodes <NUM>, <NUM> are digital vector signals that are generated by a processor such as the processors <NUM>, <NUM> shown in <FIG>. Although the circuit <NUM> includes two input nodes <NUM>, <NUM> for receiving input vector signals, some embodiments of the circuit <NUM> may be configured with more or fewer input nodes to receive more or fewer input vector signals.

The circuit <NUM> includes digital-to-analog (DAC) converters <NUM>, <NUM> that are used to convert the input vector signals received at the input nodes <NUM>, <NUM> from the digital domain to the analog domain. The analog signals are then provided to corresponding low pass filters (LPF) <NUM>, <NUM>, which may be used to filter out extraneous high frequency components and provide the filtered analog signals to an up-converter <NUM>. A local oscillator (LO) <NUM> provides a signal corresponding to a transmission frequency to the up-converter <NUM> so that the up-converter <NUM> can combine the filtered analog signals and up convert the combined signals from the baseband frequency to the transmission frequency used for transmissions over the air interface. The up-converted signal is provided to a bandpass filter (BPF) <NUM> to filter out portions of the signal outside of the transmission bandwidth and provide the filtered, up-converted signal to a driver <NUM> and a power amplifier <NUM>. The amplified signal may then be provided to one or more antennas such as the antennas <NUM>, <NUM> shown in <FIG> for transmission over the air interface.

A coupler <NUM> is used to couple a portion of the analog vector output signal generated by the power amplifier <NUM> into a feedback path <NUM>. The signal portion (referred to herein as the feedback vector signal) is provided to a down-converter <NUM> that uses a baseband frequency signal provided by a local oscillator <NUM> to down-convert the feedback vector signal from the transmission frequency to the baseband frequency. The down-converter <NUM> may also de-multiplex the feedback vector signal into multiple feedback vector signals that correspond to the input vector signals received at the input nodes <NUM>, <NUM>. The feedback vector signals are then provided to LPFs <NUM>, <NUM> to filter out high frequency components and the filtered feedback vector signals are provided to analog-to-digital converters (ADCs) <NUM>, <NUM> to convert the filtered feedback vector signals from the analog domain to the digital domain to form digital feedback vector signals.

The circuit <NUM> is coupled to a vector signal processor <NUM> that receives the input vector signals received at the input nodes <NUM>, <NUM> and the feedback vector signals corresponding to the amplified input signals generated by the power amplifier <NUM>. Portions of the circuit <NUM> between the input nodes <NUM>, <NUM> and the outputs of the ADCs <NUM>, <NUM> introduce a time delay (Tdelay) between the input vector signals and the feedback vector signals received at the vector signal processor <NUM>. As discussed herein, timing delays between the input and feedback vector signals can degrade the quality of the predistortion coefficients used to pre-distort the input vector signals to compensate for nonlinearities in the power amplifier <NUM>. The vector signal processor <NUM> may therefore use vector transforms to time align the feedback vector signals with the corresponding input vector signals. Some embodiments of the vector signal processor <NUM> use a vector forward transform to transform the feedback vector signals from a time domain to a transform domain. The vector signal processor <NUM> may then rotate the transformed feedback vector signal by a phase that is proportional to the time delay (Tdelay) between the input vector signals and the feedback vector signals received at the vector signal processor <NUM>. A vector inverse transform is applied to the rotated feedback vector signal to transform it from the transform domain back into the time domain, where it is now time aligned with the input vector signal. The input vector signal and the time-aligned feedback vector signal may be provided to the predistortion module such as the predistortion modules <NUM>, <NUM> shown in <FIG>.

<FIG> is a block diagram of a vector signal processor <NUM> according to some embodiments of the present invention. The vector signal processor <NUM> may be used to implement some embodiments of the vector signal processor <NUM> shown in <FIG>. The vector signal processor <NUM> receives one or more feedback vector signals at the feedback node <NUM> and one or more input vector signals at the input node <NUM>.

The feedback vector signals and the input vector signals are provided to a preprocessing module <NUM> that is used to perform operations such as DC offset compensation on the feedback vector signal to remove DC offsets produced by sampling, gain control, and the like in a circuit such as the circuit <NUM> shown in <FIG>. The preprocessing module <NUM> is also used to scale the feedback vector signal by an amount determined by the relative powers of the input vector signal and the feedback vector signal.

The preprocessed feedback vector signal and the input vector signal are provided to a delay estimation module <NUM>, which estimates the timing delay between the preprocessed feedback vector signal and the input vector signal. In some embodiments, the delay estimation module <NUM> estimates a timing delay Tdelay= Tint + Tfrac, wherein Tint is the integer delay and Tfrac is the fractional delay of the sampling period. The delay estimation module <NUM> provides the estimated timing delay to a signal alignment module <NUM>. The preprocessed feedback signal (from the preprocessing module <NUM>) is also provided to the signal alignment module <NUM>. Thus, the signal alignment module <NUM> time aligns the input vector signal with the preprocessed feedback vector signal using the estimated timing delay. A post-processing module <NUM> receives the time-aligned feedback vector signal and the input vector signal. Some embodiments of the post-processing module <NUM> perform operations such as calculating a scaling factor based on a ratio of a product of the input vector signal and the time-aligned feedback vector signal to a magnitude of the time-aligned feedback vector signal. The post-processing module <NUM> may then scale the time-aligned feedback vector signal using the scaling factor.

<FIG> is a flow diagram of a method <NUM> for time aligning a feedback vector signal with an input vector signal according to some embodiments. The method <NUM> may be implemented in some embodiments of processor such as the vector signal processor <NUM> shown in <FIG>, the vector signal processor <NUM> shown in <FIG>, or the processors <NUM>, <NUM> shown in <FIG>.

At block <NUM>, the processor shifts the feedback vector signal to compensate for a DC offset. For example, the processor may calculate the mean value, x , of the feedback vector signal, SigB: <MAT> where N is the length of the feedback vector signal SigB. For example, N may indicate the number of samples of the signal in a frame. The processor subtracts then the mean value to shift the feedback vector signal to an offset-corrected feedback vector signal, MSigB: <MAT>.

At block <NUM>, the processor calculates a gain factor using an input vector signal and the offset-corrected feedback vector signal. For example, the processor calculates a vector power PF for the input vector signal, SigF: <MAT> where SigF* , is the complex conjugate of the input vector signal SigF. The processor also calculates a vector power PB for the offset-corrected feedback vector signal: <MAT> where MSigB* is the complex conjugate of the offset-corrected feedback vector signal MSigB. The gain factor is then computed based on a ratio of the vector powers for the input vector signal and the offset-corrected feedback vector signal: <MAT>.

At block <NUM>, the processor scales the offset-corrected feedback vector signal by the gain factor: <MAT>.

At block <NUM>, the processor transforms the scaled feedback vector signal from a time domain to a transform domain. For example, the processor may compute the vector forward transform (VFT) of the scaled feedback vector signal SigBP to obtain XB. <MAT> where the vector forward transform (VFT) can be carried out by equation (<NUM>) or equation (<NUM>): <MAT> where U is the transform kernel, x is the vector signal, and X(k) is the VTF. Examples of transform kernels that may be used to transform the scaled feedback vector signals between the time domain and the transform domain include Fourier transforms, wavelet transforms, Hartley transforms, and the like.

At block <NUM>, the processor rotates the transformed feedback vector signal based on a delay, such as a timing delay between the input vector signal and the feedback vector signal. For example, the processor may rotate the vector signal XB by a phase that is proportional to the delay Tdalay estimated by the delay estimation module <NUM> shown in <FIG> to obtain the rotated signal vector XBR.

Some embodiments of the processor may also multiply the signal vector XB by the rotated vector signal XBR to obtain the variance of the vector signal, XBS : <MAT>.

At block <NUM>, the processor transforms the phase-aligned feedback vector signal from the transform domain to the time domain. For example, the processor may compute the inverse of the signal vector XBS by the vector inverse transform (VIT) to obtain the shifted signal vector SSigB: <MAT> where the vector inverse transform (VIT) can be carried out by equation (<NUM>) or equation (<NUM>): <MAT> <MAT> where U is the transform kernel and X is the signal vector. Transforming the phase-aligned feedback vector signal from the transform domain to the time domain generates the time-aligned feedback vector signal.

At block <NUM>, the processor scales the time-aligned feedback vector signal by a scaling factor. For example, the processor can compute Cnum: <MAT>.

The processor may then use these quantities to compute the scaling factor: <MAT>.

The processor shifts the time-aligned feedback vector signal by multiplying with the scaling factor: <MAT>.

The vector signal SSigBF is the vector signal aligned with the feed-forward signal with minimal residue.

The timing delays, gains, scaling factors, and other quantities used to time align the input vector signal and the feedback vector signal may change between different time intervals. For example, some or all these quantities may change from frame-to-frame during transmissions over an air interface between a base station and one or more user equipment. Some embodiments of the method <NUM> may therefore be iterated at a predetermined time interval or in response to other events such as detecting changes in one or quantities used to time align the input vector signal and the feedback vector signal.

The software can include the instructions and certain data that, when executed by the one or more processors, cause the one or more processors to perform the steps of method claim <NUM>.

Such storage media can include, but is not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc , magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media.

Moreover, the particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein.

Claim 1:
A method comprising:
receiving, at a processor (<NUM>), a second vector signal from a circuit in response to the circuit receiving a first vector signal;
transforming, at the processor (<NUM>), the second vector signal from a time domain to a transform domain; and
rotating, at the processor (<NUM>), the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal, wherein the time delay is introduced between the first and second vector signals by the circuit, wherein transforming the second vector signal from the time domain to the transform domain comprises calculating an offset based on a sum of components of the second vector signal and subtracting the offset from the components of the second vector signal prior to transforming the offset-corrected second vector signal from the time domain to the transform domain,
wherein transforming the offset-corrected second vector signal from the time domain to the transform domain comprises calculating a first vector power based on the first vector signal and a second vector power based on the offset-corrected second vector signal, calculating a gain based on a ratio of the first vector power to the second vector power, and scaling the offset-corrected second vector signal based on the gain prior to transforming the scaled second vector signal from the time domain to the transform domain.