Patent Description:
Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and speed in comparison to alternative types of memory.

Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T -1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modem memory architectures. As another DRAM cell, a 2T-1C memory cell configuration is schematically illustrated in <FIG> according to the prior art, which includes two transistors and one capacitor.

<NPL> discloses a 2T/1C ferroelectric memory cell. <CIT> discloses a dynamic memory cell which can be selected by means of a selection signal and the content of which can be read out by means of a bit line pair with a first and a second bit line.

<FIG> are examples not forming part of the invention.

Some embodiments include 2T-1C configurations in which two or more components are vertically stacked relative to one another in order to increase integration. Specific example embodiments of stacking arrangements are described below with reference to <FIG>.

Referring again to <FIG>, an example prior art 2T-1C memory cell configuration <NUM> includes two transistors and one capacitor. The two transistors are labeled as T1 and T2, and the capacitor is labeled as CAP.

A source/drain region of T1 connects with a first node of the capacitor (CAP), and the other source/drain region of T1 connects with a first comparative bitline (BL-<NUM>). A gate of T1 connects with a wordline (WL). A source/drain region of T2 connects with a second node of the capacitor (CAP), and the other source/drain region of T2 connects with a second comparative bitline BL-<NUM>. A gate of T2 connects with the wordline (WL).

The comparative bitlines BL-<NUM> and BL-<NUM> extend to circuitry <NUM> which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell <NUM>. An advantage of the 2T-1C memory cell is that a memory state may be ascertained by comparing the electrical properties of the two comparative bitlines BL-<NUM> an BL-<NUM> to one another, and accordingly a reference bitline associated with prior art memory (for instance, 1T-1C memory) may be omitted.

The 2T-1C configuration of <FIG> may be utilized in DRAM (dynamic random access memory) and/or other types of memory.

<FIG> shows a region of a memory array <NUM> comprising example 2T-1C memory cells. Specifically, a pair of adjacent memory cells <NUM> and 12a are illustrated. A dashed line <NUM> demarcates an approximate boundary of the memory cell <NUM>. The memory cells <NUM> and 12a are substantially identical to one another, with the term "substantially identical" meaning that the memory cells are identical to within reasonable tolerances of fabrication and measurement.

The illustrated portion of memory array <NUM> is supported by a base <NUM>. The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. The base <NUM> is shown to be spaced from components of array <NUM> to indicate that other circuitry or components may be between array <NUM> and the base <NUM>. An interlayer insulating film <NUM> may intervene between the base <NUM> and the array <NUM>. Although the film <NUM> is only shown in <FIG>, it is to be understood that it may be present in the embodiments shown in other figures as well. The film <NUM> may comprise any suitable electrically insulative material or combination of insulative materials, including, for example, silicon dioxide, silicon nitride, etc..

In the illustrated embodiment, the insulating film <NUM> has a substantially planar upper surface, and the comparative bitlines (BL-<NUM>, BL-<NUM>, BL-1a and BL-2a) are disposed on such upper surface, and in parallel with one another. The term "substantially planar" means planar to within reasonable tolerances of fabrication and measurement.

The memory cell <NUM> comprises a pair of comparative bitlines BL-<NUM> and BL-<NUM>, and comprises transistors T1 and T2 over the bitlines BL-<NUM> and BL-<NUM>, respectively. Similarly the memory cell 12a comprises a pair of comparative bitlines BL-1a and BL-2a, and comprises transistors T1a and T2a. The comparative bitlines BL-<NUM> and BL-<NUM> are electrically coupled with circuitry <NUM> of the type described above with reference to <FIG> for comparing electrical properties of the comparative bitlines one another, and similarly the comparative bitlines BL-1a and BL-2a are electrically coupled with circuitry 4a for comparing electrical properties of the comparative bitlines one another. Circuitry <NUM> and 4a, each serving as a sense amplifier, may be in any suitable location relative to array <NUM>, and may, for example, be between array <NUM> and base <NUM>, laterally offset from array <NUM>, etc. Circuitry <NUM> and 4a may be further incorporated into the base <NUM> as a sense amplifier together with other electrical circuits that may be used to access to the array <NUM> to read or write data from or into the array <NUM>. In applications in which an interlayer insulating film intervenes between the array <NUM> and the base <NUM>, a plurality of vias may be formed in the interlayer insulating film to electrically connect wordlines WL and bitlines BL of the array <NUM> to the circuits, such as the sense amplifiers <NUM> and 4a, that may be formed in the base <NUM>.

In the illustrated example the comparative bitlines BL-<NUM> and BL-<NUM> of memory cell <NUM> are laterally displaced relative to one another, and similarly the transistors T1 and T2 are laterally displaced relative to one another. The transistors T1 and T2 are shown to be in a common horizontal plane as one another (i.e., are horizontally aligned with one another), but in other embodiments may be vertically offset relative to one another.

The transistors T1 and T2 comprise gates <NUM> and <NUM>; and similarly the transistors T1a and T2a comprise gates 14a and 16a. The memory cells <NUM> and 12a are in a common row as one another within the memory array, and accordingly a wordline (WL) extends across all of the transistors T1, T1a, T2 and T2a, and comprises the gates of such transistors. The wordline and the bitlines may comprise any suitable electrically conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc. The wordline and bitlines may comprise the same composition as one another, or may comprise different compositions relative to one another.

Semiconductor pillars <NUM> and <NUM> extend upwardly from the comparative bitlines BL-<NUM> and BL-<NUM>. Such semiconductor pillars may comprise any suitable semiconductor materials including, for example, one or both of silicon and germanium. Similar semiconductor pillars18a and 20a extend upwardly from the comparative bitlines BL-1a and BL-2a.

The transistor gate <NUM> is spaced from the semiconductor pillar <NUM> by gate dielectric material <NUM>, and the transistor gate <NUM> is spaced from the semiconductor pillar <NUM> by gate dielectric material <NUM>. The gate dielectric materials <NUM> and <NUM> may comprise any suitable compositions or combinations of compositions; including, for example, silicon dioxide, silicon nitride, high-K dielectric material, ferroelectric material, etc. Analogous gate dielectric materials 22a and 24a are within the transistors T1a and T2a.

The transistor T1 comprises a channel region <NUM> within semiconductor material of pillar <NUM>, and comprises source/drain regions <NUM> and <NUM> on opposing sides of the channel region. The source/drain regions and channel region may be doped with any suitable dopants. In some embodiments the source/drain regions may be n-type majority doped, and in other embodiments may be p-type majority doped.

The transistor T2 comprises a channel region <NUM> within semiconductor material of pillar <NUM>, and comprises source/drain regions <NUM> and <NUM> on opposing sides of the channel region. In some embodiments the source/drain regions <NUM> and <NUM> may be referred to as first and second source/drain regions, respectively; and the source/drain regions <NUM> and <NUM> may be referred to as third and fourth source/drain regions, respectively.

The transistors T1a and T2a comprise source/drain regions (28a/30a/34a/36a) and channel regions (26a/32a) analogous those described with reference to transistors T1 and T2.

Memory cell <NUM> comprises a capacitor <NUM> which is vertically displaced relative to transistors T1 and T2, and in the illustrated embodiment is over the transistors T1 and T2. The capacitor comprises an outer node (or first node) <NUM>, an inner node (or second node) <NUM>, and capacitor dielectric material <NUM> between the inner and outer nodes. In the shown embodiment the outer node <NUM> is container-shaped, and the inner node <NUM> and capacitor dielectric material <NUM> extend into the container-shaped outer node. In other embodiments the outer node may have a different configuration (e.g., a planar configuration).

The inner and outer nodes <NUM> and <NUM> may comprise any suitable electrically conductive compositions or combinations of electrically conductive compositions; including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing materials (for instance, metal nitride, metal silicide, metal carbide, etc.), conductively-doped semiconductor materials (for instance, conductively-doped silicon, conductively-doped germanium, etc.), etc. The inner and outer nodes <NUM> and <NUM> may comprise the same composition as one another in some embodiments, and in other embodiments may comprise different compositions relative to one another.

The capacitor dielectric material <NUM> may comprise any suitable composition or combination of compositions. In some embodiments, the capacitor dielectric material may comprise non-ferroelectric material and may, for example, consist of one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. In some embodiments the capacitor dielectric material may comprise ferroelectric material. For instance, the capacitor dielectric material may comprise, consist essentially of, or consist of one or more materials selected from the group consisting of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and having dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, niobium, strontium, and a rare earth element.

In the shown example the outer electrode <NUM> is electrically coupled with the first source/drain region <NUM> of transistor T1, and the inner electrode <NUM> is electrically coupled with the third source/drain region <NUM> of transistor T2. The second source/drain region <NUM> of transistor T1 is electrically coupled with comparative bitline BL-<NUM> and the fourth source/drain region <NUM> of transistor T2 is electrically coupled with comparative bitline BL-<NUM>. The capacitor <NUM>, together with transistors T1 and T2, and comparative bitlines BL-<NUM> and BL-<NUM>, forms a 2T-1C memory cell of the type described above with reference to <FIG>.

The inner electrode <NUM> is shown having a single homogenous composition that extends from inside of the container-shaped outer electrode <NUM> to outside of the container-shaped outer electrode and into electrical contact with source/drain region <NUM>. In other embodiments at least some of the illustrated portion of the inner electrode <NUM> outside of the container-shaped outer electrode <NUM> may be replaced with an electrically conductive interconnect which may or may not have a same composition as the inner electrode <NUM>.

The memory cell 12a comprises a capacitor 38a analogous to the capacitor <NUM> of memory cell <NUM> (with capacitor 38a comprising a first node 40a, a second node 42a and capacitor dielectric material 44a), and also comprises a 2T-1C memory cell of the type described above with reference to <FIG>.

Insulative material <NUM> is shown to surround the various components of memory cells <NUM> and 12a. Such insulative material may comprise any suitable composition or combination of compositions; including, for example, one or more of silicon dioxide, silicon nitride, borophosphosilicate glass, spin-on dielectric, etc. Although insulative material <NUM> is shown as a single homogeneous material, in other embodiments the insulative material may include two or more discrete insulative compositions.

<FIG> is a top view of a region of memory array <NUM> showing an example embodiment relationship between a series of wordlines (WL) and comparative bitlines (BL-<NUM>, BL-<NUM>, BL-1a and BL-2a). The cross-section of <FIG> is along the line <NUM>-<NUM> of <FIG>.

In some example configurations analogous to that of <FIG> and <FIG> may be incorporated into stacked memory array tiers. In such examples a second tier may be over a first tier and inverted such that comparative bitlines may be shared between the tiers. <FIG> shows a region of an example arrangement <NUM> of stacked memory array tiers, with a second tier <NUM> being over a first tier <NUM>.

The first tier <NUM> comprises memory cells <NUM> and 12a of the type described in <FIG> and <FIG>. The second tier <NUM> comprises similar memory cells 12b and 12c, except that the second memory cells are inverted relative to the first memory cells. The memory cell 12b comprises first and second transistors T1b and T2b, and the memory cell 12c comprises first and second transistors T1c and T2c. The memory cells 12b and 12c comprise capacitors 38b and 38c, respectively. The wordline extending across the memory cells <NUM> and 12a is labeled as a first wordline (WL1), and the wordline across the memory cells 12b and 12c is labeled as a second wordline (WL2).

In some examples an axis <NUM> through the comparative bitlines BL-<NUM>, BL-<NUM>, BL-1a and BL-2a may be considered to define a mirror plane and the memory cells 12b and 12c may be considered to be substantially mirror images of the memory cells <NUM> and 12a, respectively, across the mirror plane. The term "substantially mirror images" is utilized to indicate that the indicated cells may be mirror images of one another to within reasonable tolerances of fabrication and measurement.

In some examples the configuration of <FIG> and <FIG> may be considered to comprise memory cells within 4F<NUM> architecture, and the configuration of <FIG> may be considered to comprise memory cells within 8F<NUM> architecture.

The example of <FIG> shows comparative bitlines BL-<NUM> and BL-<NUM> within a common horizontal plane as one another (i.e., are horizontally aligned with one another). In other embodiments, the comparative bitlines BL-<NUM> and BL-<NUM> may be vertically displaced relative to one another, as described with reference to <FIG>.

Referring to <FIG>, a memory array <NUM> comprises adjacent memory cells <NUM> and 12a. The memory cells <NUM> and 12a of memory array <NUM> are similar to the memory cells <NUM> and 12a of the memory array <NUM> discussed above with reference to <FIG>, except that the second comparative bitlines BL-<NUM>/BL-2a are vertically displaced relative to the first comparative bitlines BL-<NUM>/BL-1a in the configuration of <FIG>. In contrast, the first and second comparative bitlines are not vertically displaced relative to one another in the configuration of <FIG>.

The configuration of <FIG> may be formed with any suitable method. In some examples the configuration of <FIG> may be formed by including insulative subcomponents of material <NUM> having first surfaces <NUM> and second surfaces <NUM>, with first surfaces <NUM> being above second surfaces <NUM>. Such subcomponents of material <NUM> may correspond to one or more insulative films in some embodiments.

In the illustrated example of <FIG>, the second comparative bitlines BL-<NUM>/BL-2a are deeper than the first comparative bitlines BL-<NUM>/BL-1a, and accordingly pedestals <NUM>/20a are longer than pedestals <NUM>/18a within memory cells <NUM>/12a. In such embodiment, the distance between second comparative bitlines BL-<NUM>/BL-2a and the channel regions <NUM>/32a of transistors T2/T2a is lengthened relative to the embodiment of <FIG>, resulting in the lengthening of the source/drain regions <NUM>/36a of transistors T2/T2a. In some examples electrically conductive interconnects (not shown) may be provided along upper surfaces of BL-<NUM>/BL-2a to reduce the length of the source/drain regions <NUM>/36a.

The first comparative bitlines BL-<NUM>/BL-1a are entirely laterally displaced relative to the second comparative bitlines BL-<NUM>/BL-2a for each of the memory cells <NUM>/12a in the embodiment of <FIG>. <FIG> shows an alternative example in which the comparative bitlines BL-<NUM> and BL-<NUM> laterally overlap one another. In the illustrated example of <FIG>, the pedestal <NUM> is laterally offset from a center of comparative bitline BL-<NUM>. In other examples the pedestal <NUM> may extend to the central region of BL-<NUM> even though the comparative bitlines BL-<NUM> and BL-<NUM> laterally overlap. In yet other examples the pedestal <NUM> may be laterally offset from a center of comparative bitline BL-<NUM> in addition to, or alternatively to, the pedestal <NUM> being offset from the center of comparative bitline BL-<NUM>. The lateral overlap of the comparative bitlines BL-<NUM> and BL-<NUM> in the example of <FIG> may provide larger landing pads for the pedestals <NUM> and <NUM> which may better compensate for mask misalignment as compared to examples having smaller dimensions of the comparative bitlines. Example surfaces <NUM> and <NUM> are diagrammatically illustrated in <FIG> to illustrate an example method of forming the construction of <FIG> through utilization of subcomponents of insulative material <NUM> having upper surfaces <NUM> and <NUM>.

<FIG> shows a region of an example memory array <NUM> with stacked memory cells. Specifically, the array <NUM> comprises memory cells <NUM> and 12a-g; with memory cells 12b, <NUM>, 12f and 12d (i.e., cell-<NUM>, cell-<NUM>, cell-<NUM> and cell-<NUM>) being in a first vertical stack, and memory cells 12c, 12a, <NUM> and 12e (i.e., cell-<NUM>, cell-<NUM>, cell-<NUM> and cell-<NUM>) being in a second vertical stack. The memory cells of the first vertical stack are electrically coupled with a first set of comparative bitlines (i.e.. , comparative bitlines BL-<NUM>, BL-<NUM>, BL-1b and BL-2b); and the memory cells of the second vertical stack are electrically coupled with a second set of comparative bitlines (i.e., comparative bitlines BL-1a, BL-2a, BL-1c and BL-2c). First sensing amplifier circuitry <NUM> is electrically coupled with the first set of comparative bitlines, and second sensing amplifier circuitry 4a is electrically coupled with the second set of comparative bitlines.

Wordlines WL-<NUM>, WL-<NUM>, WL-<NUM> and WL-<NUM> extend along rows of the memory array <NUM>.

The examples of <FIG> have the transistors (e.g., T1 and T2) laterally offset from one another, and the capacitor (e.g., <NUM> of <FIG>) provided above (or below) both of such transistors. According to the invention, , the two transistors of a 2T-1C memory cell are vertically offset relative to one another, and the capacitor is provided vertically between such transistors. <FIG> shows a portion of a memory array <NUM> illustrating an example embodiment in which the capacitors of 2T-1C memory cells are provided between vertically displaced transistors.

The illustrated region of memory array <NUM> comprises comparative bitlines BL-<NUM> and BL-<NUM>, with such comparative bitlines being vertically offset relative to another and connected to circuitry <NUM>. A pair of adjacent memory cells <NUM> and 12a are shown, with such adjacent memory cells being in a common column as one another within the memory array (i.e., being along a common bitline, with such bitline being comprised by the comparative bitlines BL-<NUM> and BL-<NUM> in combination). Such is in contrast to the embodiments of <FIG>, <FIG> and <FIG> in which the adjacent memory cells <NUM> and 12a are in a common row as one another (i.e., are along a common wordline). In some embodiments the memory cells <NUM> and 12a may be referred to as substantially identical memory cells along a column of a memory array, with the term "substantially identical" meaning that the memory cells are identical to one another within reasonable tolerances of fabrication and measurement.

The lower comparative bitline (BL-<NUM>) is shown to be over and supported by a base <NUM>. Such base may be a semiconductor substrate of the type described above with reference to <FIG>.

The memory cell <NUM> comprises transistors T1 and T2, with such transistors being along a first wordline WL1. The adjacent memory cell 12a comprises transistors T1a and T2a, with such transistors being along a second wordline WL2.

A capacitor <NUM> is vertically between the transistors T1 and T2 of memory cell <NUM>, and a similar capacitor 38a is vertically between the transistors T1a and T2a of memory cell 12a.

The capacitors comprise first nodes <NUM>/40a, second nodes <NUM>/42a and capacitor dielectric material <NUM>/44a. Although the first nodes <NUM>/40a are shown to be container-shaped and the second nodes <NUM>/42a are shown to extend within such container shapes, in other embodiments the first and second nodes may have other configurations. For instance, the first and second nodes may have planar configurations. In the illustrated configuration the first nodes <NUM>/40a may be referred to as outer nodes and the second nodes <NUM>/42a may be referred to as inner nodes.

The pillars <NUM>/18a extend from comparative bitline BL-<NUM> to the outer nodes <NUM>/40a of capacitors <NUM>/38a, and the pillars <NUM>/20a extend from the comparative bitline BL-<NUM> to the inner nodes <NUM>/42a of capacitors <NUM>/38a.

The transistors T1/T1a have first source/drain regions <NUM>/28a extending to the outer nodes <NUM>/40a of capacitors <NUM>/38a, and have second source/drain regions <NUM>/30a extending to the comparative bitline BL-<NUM>. The transistors T1/T1a also have channel regions <NUM>/26a between the first and second source/drain regions. Gates <NUM>/14a are along the channel regions and offset from the channel regions by gate dielectric materials <NUM>/22a.

The transistors T2/T2a have third source/drain regions <NUM>/34a extending to the inner nodes <NUM>/42a of capacitors <NUM>/38a, and have fourth source/drain regions <NUM>/36a extending to the comparative bitline BL-<NUM>. The transistors T2/T2a also have channel regions <NUM>/32a between the third and fourth source/drain regions. Gates <NUM>/16a are along the channel regions and offset from the channel regions by gate dielectric materials <NUM>/24a.

The embodiment of <FIG> advantageously enables the transistors and capacitor of a 2T-1C memory cell to all be vertically stacked, which may enable the memory cells to be packed to high levels of integration.

Although the illustrated embodiment of <FIG> comprises a configuration with BL-<NUM> over a supporting substrate <NUM> and BL-<NUM> over BL-<NUM>, in other embodiments the relative orientations of BL-<NUM> and BL-<NUM> could be reversed so that BL-<NUM> is over the supporting substrate and BL-<NUM> is over BL-<NUM>. In such other embodiments the illustrated capacitors <NUM>/38a would be inverted relative to the shown configuration and accordingly container-shaped outer nodes <NUM> would open upwardly instead of downwardly.

An advantage of various examples of memory arrays described above with reference to <FIG> and embodiment of <FIG> is that such examples of <FIG> and embodiment of <FIG> may have symmetric layouts relative to the comparative bitlines (e.g., BL-<NUM> and BL-<NUM>) extending throughout the memory arrays, and such may reduce resistance/signal mismatches between the comparative bitlines as compared to less symmetric layouts.

The illustrated capacitors in the above-described examples of <FIG> and embodiment of <FIG> may be replaced with other capacitive units in other embodiments. For instance, any of the capacitors may be replaced with a capacitive unit having two or more capacitors in combination.

The transistors T1 and T2 of the above-described examples of <FIG> and embodiment of <FIG> may comprise any suitable configurations. For instance, in the illustrated examples of <FIG> and embodiment of <FIG> the transistors are field effect transistors, but in other examples of <FIG> and embodiment of <FIG> other suitable transistors may be substituted for one or more of the transistors T1 and T2; with bipolar junction transistors being an example of a transistor configuration which may be used alternatively to field effect transistors. The field effect transistors described herein may utilize gate dielectric material comprising non-ferroelectric material and/or ferroelectric material depending on the application. The gates of the transistors may have any of numerous configurations, with some example configurations being described with reference to <FIG>. The figures specifically pertain to the T1 transistor gates, but in other embodiments analogous configurations may be utilized for the T2 transistor gates.

Referring to <FIG>, the T1 transistor gate <NUM> is shown in a configuration of the type utilized in the examples of <FIG> and <FIG> and embodiment of <FIG>. Specifically, the transistor gate is a block of uniform width, with such width being approximately equal to a length "L" of the channel region <NUM>. In contrast, each of the embodiments of <FIG> has the gate narrower than the length of the channel region, and has at least one extension region <NUM> that extends from the gate and along the channel region. Further, each of the embodiments of <FIG> has at least one bent region <NUM> where the gate <NUM> joins to an extension region. The embodiment of <FIG> shows the gate <NUM> and extension regions <NUM> forming a substantially T-shaped configuration, the embodiment of <FIG> shows the extension region <NUM> and gate <NUM> together forming a substantially U-shaped configuration, and the embodiments of <FIG> show the gate <NUM> and extension regions <NUM> forming substantially shelf-shaped configurations (with <FIG> showing the gate <NUM> as a top shelf over extension regions <NUM> and <FIG> showing the gate <NUM> as a bottom shelf beneath regions <NUM>).

Advantages of the embodiments of <FIG> relative to that of <FIG> may include reduced gate resistance and associated reduced current requirements for desired access drive parameters.

The structures and architectures described above may be incorporated into memory (e.g., DRAM, SRAM, etc.) and/or otherwise may be utilized in electronic systems. Such electronic systems may be any of a broad range of systems, such as, for example, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

Both of the terms "dielectric" and "electrically insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "electrically insulative" in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

Claim 1:
A memory cell (<NUM>) comprising:
a first transistor (T1) and a second transistor (T2) vertically displaced relative to one another; and
a capacitor (<NUM>) disposed to be vertically between the first transistor (T1) and the second transistor (T2), the capacitor (<NUM>) having a first node (<NUM>) electrically coupled with a first source/drain region (<NUM>) of the first transistor (T1), having a second node (<NUM>) electrically coupled with a third source/drain region (<NUM>) of the second transistor (T2), and having capacitor dielectric material (<NUM>) between the first and second nodes (<NUM>, <NUM>); characterised by one of the first node (<NUM>) and the second node (<NUM>) being container-shaped and the other of the first node (<NUM>) and the second node (<NUM>) extending into the container shape; and wherein;
the first transistor (T1) has the first source/drain region (<NUM>) and a second source/drain region (<NUM>), the first node (<NUM>) of the capacitor (<NUM>) being electrically coupled with the first source/drain region (<NUM>);
the second transistor (T2) has the third source/drain region (<NUM>) and a fourth source/drain region (<NUM>), the second node (<NUM>) of the capacitor (<NUM>) being electrically coupled with the third source/drain region (<NUM>); and
the second and fourth source/drain regions (<NUM>, <NUM>) being electrically coupled with a first and a second comparative bitline (BL-<NUM>, BL-<NUM>) respectively.