Patent Description:
The present disclosure relates generally to methods and apparatuses having power supply circuits with reduced leakage current and more particularly, methods and apparatuses having power supply circuits that power down delay circuits to reduce leakage current.

A computing device (e.g., a laptop, a mobile phone, etc.) may include a processor on one or more semiconductor dies to perform various functions, such as telephony, internet access, camera/video function, etc. The processor may include various circuit blocks to perform those functions. These and other circuit blocks draw power while in operation. The circuit blocks may be powered by power sources, such as batteries and wall plug-ins, via power/voltage regulating circuits. For example, the power sources may generate supply voltages, and power supply circuits may be configured to provide the supply voltages to the circuit blocks.

Attention is drawn to document <CIT> which relates to an integrated circuit which may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled.

Further attention is drawn to document <CIT> which relates to a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Attention is also drawn to document <CIT> which relates to a single-stage level shifting circuit which is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

Further embodiments of the invention are defined by the appended dependent claims. This summary identifies features of some example aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Additional features and aspects are described and will become apparent to persons skilled in the art upon reading the following detailed description and viewing the drawings that form a part thereof.

An apparatus in accordance with at least one embodiment includes a switch circuit configured to power a circuit block, a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block.

Aspects of a method to reduce leakage current, in accordance with at least one embodiment, are presented. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block. Bypassing the delay circuit to disable the switch circuit powering the circuit block permits the delay circuit to be powered down. In this way, contribution of delay circuits to leakage current in the standby mode or the power-down mode can be reduced.

Various aspects of apparatus and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:.

The detailed description includes specific details for providing a thorough understanding of various concepts. In some instances, well known structures and components are shown in block diagram form to avoid obscuring such concepts.

As used herein, the term "coupled to" in the various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term "coupled to" may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" indicate having an electric current flowing between the elements A and B. In some examples, the term "electrically connected" may indicate having an electric current flowing between the elements A and B. The term "node" may mean electrical connection, conductor, or wiring.

The terms "first," "second," "third," etc. are employed for ease of reference and may not carry substantive meanings. Examples may include a "first" control signal.

As the computing device grows in functions and shrinks in physical dimension, reducing power consumption is becoming of greater concern. For example, the computing device may enter into a standby mode, in which the computing device may power down certain circuit blocks and/or be unresponsive to certain control signals. In the standby mode, the computing device would continue to draw leakage current. For example, in the standby mode, the power circuits providing supply voltages to circuit blocks may continue to discharge leakage current, even without operations.

Moreover, the supply voltages may be powered down (e.g., to ground) in a power-down mode the reduce power consumption. The power supply circuits likewise may draw leakage current in the power-down mode. Further, powering up supply voltage networks to exit the power-down mode may cause a large inrush current to flow over the power supply circuits. Thus, the power supply circuits may include multiple parts operating in a staggered fashion. For example, the power supply circuits may include a power supply circuit and a next stage power supply circuit, each may include a delay circuit. In power up a supply voltage, the power supply circuit may start powering a circuit block first, then followed by the next stage power supply circuit powering a second circuit block, after a delay by the delay circuit. Staggering the power supply circuits in powering up of the supply voltage would reduce a peak of the inrush current, but the delay circuits may draw even more leakage current in the standby mode or the power-down mode.

Methods and apparatuses to reduce leakage in the power supply circuits (e.g., in the standby mode) are presented. For example, the delay circuits may be powered down to reduce leakage current in the standby mode or the power-down mode. In some examples, the power supply circuits may be configured to receive multiple control signals, e.g., a first control signal and a second control signal. In certain operations, the delay circuits may be powered down by either the first control signal or the second control signal.

<FIG> illustrates an apparatus <NUM> having power supply circuits with reduced leakage current, in accordance with certain aspects of the disclosure. The apparatus <NUM> may, for example, be one of computing system (e.g., servers, datacenters, desktop computers), mobile computing device (e.g., laptops, cell phones, vehicles, etc.), Internet of Things device, and/or virtual reality or augmented reality system. The apparatus <NUM> includes a power supply circuit <NUM> and a next stage power supply circuit <NUM>, control circuit <NUM>, and circuit blocks <NUM> and <NUM>. The power supply circuit <NUM> is coupled to a supply voltage VDD2 and configured to provide power to the circuit block <NUM> from the supply voltage VDD2. The next stage power supply circuit <NUM> is coupled to a supply voltage VDD2 and configured to provide power to a second circuit block <NUM> from the supply voltage VDD2. The circuit blocks <NUM> and <NUM> may perform various function and may include, for example, processing units or memories.

The control circuit <NUM> may be configured to control functions (presented below) of the power supply circuit <NUM> and the next stage power supply circuit <NUM> via signaling S113 (e.g., via one or more electrical connections). Certain portions of the control circuit <NUM> may be coupled to and/or powered by the supply voltage VDD1, and other portions may be coupled to and/or powered by the supply voltage VDD2. The supply voltages VDD1 and VDD2 may be different. The certain portions of the control circuit <NUM> may thus operate based on the supply voltage VDD1 and may be in a first voltage domain. The power supply circuit <NUM> and the next stage power supply circuit <NUM>, the circuit blocks <NUM> and <NUM>, and the other portions of the control circuit <NUM>, being powered by and/or operate based on the supply voltage VDD2, may be in a second voltage domain.

In some example, the power supply circuit <NUM> and the next stage power supply circuit <NUM> may power (e.g., restart to power) the circuit blocks <NUM> and <NUM> in a staggered fashion to, for example, exit the standby mode or the power-down mode. For example, the power supply circuit <NUM> may be configured to power the circuit block <NUM> first, then provide signaling S103 (e.g., via one or more electrical connections) to the next stage power supply circuit <NUM>. In response to the signaling S103, the next stage power supply circuit <NUM> may be configured to power the circuit block <NUM> after a delay. In such fashion, a peak of an inrush current to exit the standby mode or the power-down mode may be reduced.

<FIG> illustrates example circuits of the apparatus of <FIG>, in accordance with certain aspects of the disclosure. <FIG> includes the power supply circuit <NUM>, the control circuit <NUM>, and the circuit block <NUM> of <FIG>. As illustrated, the power supply circuit <NUM> may include a delay circuit <NUM>, a bypass circuit <NUM>, and/or a switch circuit <NUM>. The control circuit <NUM> may include a power-down circuit <NUM>, a control logic-<NUM><NUM>, a voltage shifter circuit <NUM>, and a control logic-<NUM><NUM>.

The switch circuit <NUM> may be configured to power the circuit block <NUM>. As illustrated, the switch circuit <NUM> may include a p-type transistor <NUM>. The p-type transistor <NUM> may be configured to have a source coupled to a node N23 and a drain coupled to a node N22. The drain may be further coupled to the circuit block <NUM> via the node N22. The p-type transistor <NUM> may be configured to receive power via the node N23 and to power the circuit block <NUM> via the node N22. The p-type transistor <NUM> may further be configured to have a gate coupled to a node N21. The p-type transistor <NUM> (thus switch circuit <NUM>) may be configured to turned ON (or OFF) to power (or to not power) the circuit block <NUM> based on signaling on the node N21.

The node N23 may provide a supply voltage VDD2, and the switch circuit <NUM> may be configured to provide the supply voltage VDD2 to the circuit block <NUM>. Accordingly, switch circuit <NUM> may be configured to power the circuit block <NUM> in the second voltage domain. For example, the switch circuit <NUM> may be configured to provide power to the circuit block <NUM> based on the supply voltage VDD2 in the second voltage domain. In such fashion, the switch circuit <NUM> may be configured to operate based on the supply voltage VDD2.

The bypass circuit <NUM> may be configured to drive the switch circuit <NUM> to enable and to disable the switch circuit <NUM> powering the circuit block <NUM>. The bypass circuit <NUM> may be further configured to drive the switch circuit <NUM> based on a first control signal and a second control signal (e.g., respectively a control signal SLP and a control signal CLAMP; see <FIG> and <FIG>). As illustrated, the bypass circuit <NUM> includes a NOR gate <NUM> and an inverter <NUM> arranged in series, via a node N20. The NOR gate <NUM> may be configured to receive inputs via nodes N19 and N16 (e.g., respectively first input and second input) and output via the node N20. The inverter <NUM> may be configured to receive input from the node N20 and output to the switch circuit <NUM> via the node N21. For example, the bypass circuit <NUM> may be configured to, via the inverter <NUM>, drive the gate of the p-type transistor <NUM> of the switch circuit <NUM> to turn ON and OFF the p-type transistor <NUM>, thereby to enable and to disable the switch circuit <NUM> powering the circuit block <NUM>. Moreover, signaling on the node N21 (e.g., signaling S103 in <FIG>) may be provided to the next stage power supply circuit <NUM> (see <FIG> and <FIG>).

In some examples, the bypass circuit <NUM> may be in the second power domain. For example, the bypass circuit <NUM> (e.g., the NOR gate <NUM> and/or the inverter <NUM>) may be configured to couple to and be powered via the node N23, the node N23 being configured to provide the supply voltage VDD2. Thus, the bypass circuit <NUM> (e.g., the NOR gate <NUM> and/or the inverter <NUM>) may be configured to be powered by and/or to operate based on the supply voltage VDD2 in the second voltage domain.

The delay circuit <NUM> may be configured to delay signaling to the bypass circuit <NUM>. In some examples, the delay circuit <NUM> delaying signaling for an intended period. In some examples, a sole or substantial purpose of the delay circuit <NUM> is to delay signaling. In some examples, the delayed signaling may be based on the control signal SLP. In some examples, the delay circuit <NUM> may be configured to delay enabling the switch circuit <NUM> powering the circuit block <NUM> and to be powered down (e.g., as instructed by the control circuit <NUM>).

As illustrated, the delay circuit <NUM> may include N stages of inverters 253_1 to 253_N arranged in series. For example, an output of the inverter 253_1 may be provided as an input to the inverter 253_2, and so forth. The inverters 253_1 to 253_N may be configured to be powered via a node N18. The delay circuit <NUM> may be configured to receive signaling via a node N17, delay the received signaling, and output the delayed signaling to the bypass circuit <NUM> via the node N19. As presented with <FIG>, the signaling on the node N17 may be based on the control signal SLP.

In some examples, the delay circuit <NUM> may be in the second power domain. For example, the delay circuit <NUM> (e.g., the N stages of inverters 253_1 to 253_N) may be configured to couple to and be powered via the node N23, the node N23 being configured to provide the supply voltage VDD2 (see presentation below with the control circuit <NUM>). Thus, the delay circuit <NUM> (e.g., the N stages of inverters 253_1 to 253_N) may be configured to be powered by and to operate based on the supply voltage VDD2 in the second voltage domain. See presentation relating to the control circuit <NUM> below.

As presented above, the bypass circuit <NUM> may be configured to bypass the delay circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>. The bypass circuit may include a first input (e.g., the node N19) and a second input (e.g., the node N16). The delay circuit <NUM> may be configured to delay enabling the switch circuit <NUM> powering the circuit block <NUM> via the first input (e.g., the node N19). The bypass circuit <NUM> may be further configured to, based on signaling received via the second input (e.g., the node N16), bypass the delay circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>. In some examples, the bypass circuit <NUM> may include a gate, such as the NOR gate <NUM>, coupled to the first input (e.g., the node N19) and the second input (e.g., the node N16).

The control circuit <NUM> may be configured to, based on the control signal SLP (e.g., the first control signal) and via the delay circuit <NUM> and the bypass circuit <NUM>, enable and disable the power supply circuit <NUM> powering the circuit block <NUM>. The control signal SLP may be in a voltage domain of the supply voltage VDD1 (e.g., the first voltage domain) and may be in a state of logic one or a state of logic zero. The control circuit <NUM> may be further configured to, based on the control signal CLAMP (e.g., the second control signal), cause the bypass circuit <NUM> to drive the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>, bypassing the delay circuit <NUM>. The second control signal CLAMP may be in a voltage domain of the supply voltage VDD2 (e.g., the second voltage domain) and may be in a state of logic one or a state of logic zero.

The power-down circuit <NUM> may be coupled to and powered via a node N11 and configured to receive an input via a node N02. The node N11 may be configured to provide the supply voltage VDD1. The power-down circuit <NUM> may be configured to provide power to the control logic-<NUM><NUM> via a node N15 and be further configured to power down the control logic-<NUM><NUM>, based on the control signal CLAMP received via the node N02. For example, the power-down circuit <NUM> may be configured to provide power from the node N11 to the control logic-<NUM><NUM>, via the node N15, in response to the CLAMP signal being in a first state (e.g., logic one). The power-down circuit <NUM> may be further configured to stop powering (e.g., to power down) the control logic-<NUM><NUM>, via the node N15, in response to the CLAMP signal being in a second state (e.g., logic zero). In some example, the power-down circuit <NUM> may include a p-type transistor (not shown) having a source coupled to the node N11, a drain coupled to the node N15, and a gate coupled to the node N02.

The control logic-<NUM><NUM> may be configured to receive the control signal SLP via a node N04 and to output a state of the SLP signal to the voltage shifter circuit <NUM> via a node N14. The control logic-<NUM><NUM> may be configured to be powered via the node N15 to implement various functions (such as those present below) to control the power supply circuit <NUM>. For example, the control logic-<NUM><NUM> may be configured to a state of the SLP signal to the voltage shifter circuit <NUM> via the node N14. For example, the control logic-<NUM><NUM> may be configured output a logic zero to the voltage shifter circuit <NUM> via the node N14, in response to SLP signal being in a logic zero state.

In some examples, the node N11 may be configured to provide a supply voltage VDD1, different from the supply voltage VDD2. Since the power-down circuit <NUM> and the control logic-<NUM><NUM> operate based on and/or being powered by the supply voltage VDD1, the power-down circuit <NUM> and the control logic-<NUM><NUM> may be in a first voltage domain. In some examples, the SLP signal may be in the first voltage domain. Circuits and signals operate based on and/or being powered by the supply voltage VDD2 may be in a second voltage domain. The CLAMP signal may be in the second voltage domain.

The voltage shifter circuit <NUM> may be configured to convert signaling in the first voltage domain (e.g., received from the node N14) into signaling in the second voltage domain (outputted to nodes N12 and N13). In some examples, signaling at the node N12 or the node N13 may be an inverted state of an input at the node N14. The voltage shifter circuit <NUM> may be further configured to output the signaling in the second voltage domain to the control logic-<NUM><NUM> via the nodes N12 and N13. The control logic-<NUM><NUM> may be configured to receive input on nodes N12, N13 and the CLAMP signal on a node N06. The control logic-<NUM><NUM> may be further configured to output various signals on nodes N16, N17, and N18 to cause the power supply circuit <NUM> to operate. In such fashion, the control circuit <NUM> may be configured to provide signaling to the second input (e.g., the node N16) via the voltage shifter circuit <NUM>. In some examples, the control logic-<NUM><NUM> may be configured to receive and to be powered by the supply voltage VDD2 via the node N23. The control logic-<NUM><NUM>, being powered by and/or operate based on the supply voltage VDD2, may thus be in the second voltage domain.

The control circuit <NUM> may be configured to, based on the control signal SLP (may be referred to as first control signal) and via the delay circuit <NUM> and the bypass circuit <NUM>, enable and disable the switch circuit <NUM> powering the circuit block <NUM>. The control circuit <NUM> may be further configured to power down the delay circuit <NUM> and to cause the bypass circuit <NUM> to drive the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>, in response to a state of the control signal CLAMP (may be referred to as second control signal) and independent of the control signal SLP. The control circuit <NUM> may be further configured to allow the bypass circuit <NUM> to drive the switch circuit <NUM> to enable and to disable the switch circuit <NUM> powering the circuit block <NUM>, based on the control signal SLP and via the delay circuit <NUM>, in response to a second state of the control signal CLAMP. These and other functions and operations of the control circuit <NUM> are presented with <FIG>.

<FIG> illustrates example operations of the apparatus <NUM> of <FIG>, in accordance with certain aspects of the disclosure. In <FIG>, the node N17 is labeled with "delay circuit input;" the node N19 is labeled with "delay circuit output;" the node N18 is labeled with "delay circuit power;" the node N16 is labeled with "bypass circuit control;" and the node N21 is labeled with "switch circuit control" for reference.

In <FIG>, the supply voltages VDD1 and VDD2 are both ON and at their respective supply voltage levels. The control signal SLP (may be referred to as a first control signal and may be in the first voltage domain) and the control signal CLAMP (may be referred to as a second control signal and may be in the second voltage domain) toggle and trigger operations to reduce current leakage in the power supply circuit <NUM> (<FIG>). At T0, the control signal CLAMP is at logic zero (e.g., ground), a state that does not turn off the delay circuit <NUM> and the bypass circuit <NUM> (<FIG>). Further, at T0, the control signal SLP is at logic one (e.g., at VDD1), a state that does not turn off the delay circuit <NUM> and the bypass circuit <NUM>. Accordingly, the input to the switch circuit <NUM> (<FIG>) is at logic zero, and the switch circuit <NUM> is ON and powers the circuit block <NUM>.

At T1, the control signal SLP transitions to logic zero (e.g., ground). As presented below, the control circuit <NUM>, based on the control signal SLP transitioning to logic zero and via the delay circuit <NUM> and the bypass circuit <NUM>, disables the switch circuit <NUM> powering the circuit block <NUM>. At <NUM>, an input to the delay circuit <NUM> at node N17 transitions to logic one, in response to the control signal SLP transitioning to logic zero. Referring to <FIG>, the control logic-<NUM><NUM> outputs at N14 logic zero, in response to the control signal SLP transitioning to logic zero. The voltage shifter circuit <NUM>, based on the signaling at N14, outputs logic one at the node N12. The control logic-<NUM><NUM> outputs logic one at N17 via a NOR gate <NUM> and an inverter <NUM>, in response to the node N13 transitioning to logic one.

At <NUM>, the delay circuit <NUM> outputs at the node N19 logic one following the input to the delay circuit <NUM> at node N17 transitions to logic one, after a delay through the delay circuit <NUM>. At <NUM>, in response to the control signal SLP transitioning to logic zero (the node N14 becomes logic zero and the node N13 becomes logic one), the control logic-<NUM><NUM> outputs logic zero at a node N18 via a NOR gate <NUM> to power down the delay circuit <NUM>. For example, power (e.g., supply voltage VDD2 via the NOR gate <NUM> of the control logic-<NUM><NUM>) provided to one or more stages (e.g., among inverters 253_1 to 253_N) in the delay circuit <NUM> is disabled by setting the node N18 to logic zero. In such fashion, reduce leakage current of the delay circuit <NUM> in a standby state is reduced. In such fashion, the control circuit <NUM> powers down the delay circuit <NUM> in response to the control signal SLP being logic zero.

At <NUM>, in response to the control signal SLP transitioning to logic zero (the node N14 becomes logic zero and the node N12 becomes logic one), the control logic-<NUM><NUM> outputs logic one (e.g., at supply voltage VDD2) at a node N16 via NOR gates <NUM> and <NUM>. At <NUM>, in response to the node N16 becomes logic one, the bypass circuit <NUM> outputs logic one at the node N21 to the switch circuit <NUM>, turning off the p-type transistor <NUM> powering the circuit block <NUM>. In such fashion, the control circuit <NUM>, based on the control signal SLP (may be referred to as first control signal) and the control signal CLAMP being de-asserted, may be configured to provide signaling on the node N16 to bypass the delay circuit <NUM> and to disable the switch circuit <NUM> powering the circuit block <NUM>. Further, the control circuit <NUM>, based on the control signal SLP and the control signal CLAMP being de-asserted, may be configured to power down the delay circuit <NUM>.

As presented above, the control circuit <NUM> may be configured to, based on a first control signal (e.g., the control signal SLP), provide the signaling to the second input (e.g., the node N16) to bypass the delay circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>. For example, the control circuit <NUM> providing logic one on the node N16 would disable the switch circuit <NUM> powering the circuit block <NUM>, independent of actions of the delay circuit <NUM>. Further, the control circuit <NUM> may be further configured to, via the voltage shifter circuit <NUM>, power down the delay circuit <NUM> based on the control signal SLP.

At T2, the control signal CLAMP is asserted to effect functions presented herein (transitions to logic one). In response, the VDD1 power-down circuit <NUM> of the control circuit <NUM> powers down the control logic-<NUM> circuit <NUM>. For example, the VDD1 power-down circuit <NUM> may turn off the supply voltage VDD1 provided to the control logic-<NUM><NUM> via the node N15. As a result, a leakage current of the control circuit <NUM> may be further reduced in a standby mode (e.g., a mode that the control circuit <NUM> is not in operation and/or not responsive to certain control signal transitions). This and other functions of the control signal CLAMP are presented further with <FIG>. At T3, the control signal CLAMP transitions to logic zero (de-asserted), and in response, the VDD1 power-down circuit <NUM> powers up the control logic-<NUM><NUM>. For example, the VDD1 power-down circuit <NUM> provides the supply voltage VDD1 via the node N15, allowing the control logic-<NUM><NUM> to operate and/or to respond to the control signal SLP.

At T4, the control signal SLP transitions to logic one (e.g., supply voltage VDD1). As presented below, the control circuit <NUM>, based on the control signal SLP transitioning to logic one (e.g., the supply voltage VDD1) and via the delay circuit <NUM> and the bypass circuit <NUM>, enables the switch circuit <NUM> powering the circuit block <NUM>. At <NUM>, the node N18, via which power (e.g., supply voltage VDD2) is provided to the delay circuit <NUM>, transitions to logic one to power up the delay circuit <NUM>. For example, in response to the control signal SLP transitioning to logic one, the control logic-<NUM><NUM> output logic one onto the node N14, and the voltage shifter circuit <NUM> outputs logic zero on the node N12. The control logic-<NUM><NUM> outputs logic one via the NOR gate <NUM>.

At <NUM>, the node N16, a control of the bypass circuit <NUM>, transitions to logic zero to enable the bypass circuit <NUM> (e.g., the bypass circuit <NUM> would operate based on the node N19 with the node N16 at logic zero). For example, the control logic-<NUM><NUM> outputs logic zero at the node N16 via the NOR gates <NUM> and <NUM>. In some examples, the control circuit <NUM>, via the voltage shifter circuit <NUM> and the control logic-<NUM><NUM>, may delay output N16 to logic zero, after the node N18 is powered up to ensure that the node N19 follows the node N17. In such fashion, a possibility of a false state on the node N19 is removed.

At <NUM>, the node N17, input to the delay circuit <NUM>, transitions to logic zero. For example, the control logic-<NUM><NUM> outputs logic one at the node N14 and the voltage shifter circuit <NUM> outputs logic zero at the node N13, in response to the control signal SLP transitioning to logic one. The control logic-<NUM><NUM> outputs logic zero at the node N17 via the NOR gate <NUM> and the inverter <NUM>. At 48a, the delay circuit <NUM> is powered up via the node N18. At <NUM>, the node N19, output of the delay circuit <NUM>, transitions to logic zero following a delay via the delay circuit <NUM>. At <NUM>, the node N21 transitions to logic zero in response to the node N19 transitioning to logic zero. For example, the bypass circuit <NUM> outputs logic zero on the node N21 via the NOR gate <NUM> and the inverter <NUM>, based on the node N19, to turn on the switch circuit <NUM> powering the circuit block <NUM>. In such fashion, the switch circuit <NUM> is enabled to power the circuit block <NUM>, by control circuit <NUM> via the delay circuit <NUM> and the bypass circuit <NUM>, based on the control signal SLP (e.g., when the control signal CLAMP is not asserted). Moreover, the logic zero at the node N21 may be provided to the next stage power supply circuit <NUM> (e.g., <FIG> and <FIG>) as signaling S103.

<FIG> illustrates example operations of the apparatus <NUM> of <FIG> during powering up of supply voltages, in accordance with certain aspects of the disclosure. In <FIG>, the node N18 is labeled with "delay circuit power" and the node N16 is labeled with "bypass circuit control" for ease of reference. In some examples, the apparatus <NUM> powers down the delay circuit <NUM> to reduce leakage current during powering up of supply voltages VDD1 and VDD2. At P0, the supply voltages VDD1 and VDD2 are at ground. At P1, the supply voltage VDD2 powers up, while the supply voltage VDD1 remains at ground. At P2, the control signal CLAMP follows the supply voltage VDD2 and rises to the supply voltage VDD2.

As an example, the control signal CLAMP is asserted in response to powering up the supply voltage VDD2 to effect at least some of functions presented below. For example, the control signal CLAMP may be asserted to power down the delay circuit <NUM> and/or to disable the switch circuit <NUM> powering the circuit block <NUM>. At <NUM>, in response to the control signal CLAMP being asserted (e.g., transitions to logic one), the node N18 goes to logic zero (e.g., ground). For example, in response to the control signal CLAMP being logic one, the control logic-<NUM> outputs logic zero on the node N18 via the NOR gate <NUM>, independent of the control signal SLP. <FIG> illustrates that control signal SLP being in an undetermined state, having no bearing on the control circuit <NUM> powering down the node N18 (and therefor, powering down the delay circuit <NUM>). In such fashion, the control circuit <NUM> powers down the delay circuit <NUM>, in response the logic one state of the control signal CLAMP independent of the control signal SLP.

At <NUM>, in response to the control signal CLAMP being asserted (e.g., transitions to logic one), the node N16 goes to logic one to cause the bypass circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>. For example, referring to <FIG>, the control logic-<NUM> outputs logic one on the node N16 via the gates <NUM> and <NUM>, in response to the control signal CLAMP being asserted. In such fashion, the control circuit <NUM> may be configured to provide the signaling to the node N16 to bypass the delay circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>, in response to the control signal CLAMP being asserted and independent of the control signal SLP. At P3, the supply voltage VDD1 is powered up. At <NUM>, the control signal SLP is ready to be powered up after the supply voltage VDD1 is powered up.

<FIG> illustrates example circuits of the next stage power supply circuit <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. Referring to <FIG>, the next stage power supply circuit <NUM> may be configured to power the second circuit block <NUM>, conditioned by signaling S103 from the power supply circuit <NUM>. In some examples, the power supply circuit <NUM> powering the circuit block <NUM> and the next stage power supply circuit <NUM> powering the second circuit block <NUM> may be configured to be staggered, in accordance with signaling from the control circuit <NUM>. For example, the power supply circuit <NUM> may be configured to power up the circuit block <NUM> first, followed by the next stage power supply circuit <NUM> powering up the second circuit block <NUM>. In some examples, the control circuit <NUM> may be configured to turn off the power supply circuit <NUM> powering the circuit block <NUM> and the next stage power supply circuit <NUM> powering the second circuit block <NUM> in parallel.

<FIG> illustrates the next stage power supply circuit <NUM>, the second circuit block <NUM>, and the control circuit <NUM>. In some examples, the next stage power supply circuit <NUM> may be an instance of the power supply circuit <NUM>, and description related to the power supply circuit <NUM> may be applicable to the next stage power supply circuit <NUM>. The second circuit block <NUM> may be an instance of the circuit block <NUM>, and description related to the circuit block <NUM> may be applicable to the second circuit block <NUM>. <FIG> illustrates that the next stage power supply circuit <NUM> may include a second delay circuit <NUM>, a second bypass circuit <NUM>, and/or a second switch circuit <NUM>.

The second switch circuit <NUM> may be configured to power the second circuit block <NUM>. As illustrated, the second switch circuit <NUM> may include a p-type transistor <NUM>. The p-type transistor <NUM> may be configured to have a source coupled to a node N23 and a drain coupled to a node N52 and via the node N52, to the second circuit block <NUM>. The p-type transistor <NUM> may be configured to receive power via the node N23 and to power the second circuit block <NUM> via the node N52. The p-type transistor <NUM> may further be configured to have a gate coupled to a node N51. The p-type transistor <NUM> (thus second switch circuit <NUM>) may be configured to turned ON (or OFF) to power (or to not power) the second circuit block <NUM> based on signaling on the node N51.

The second bypass circuit <NUM> may be configured to drive the second switch circuit <NUM> to enable and to disable the second switch circuit <NUM> to power the second circuit block <NUM>. As illustrated, the second bypass circuit <NUM> includes a NOR gate <NUM> and an inverter <NUM> arranged in series, via a node N50. The NOR gate <NUM> may be configured to receive inputs via nodes N59 and N56 and output via the node N50. The inverter <NUM> may be configured to receive input from the node N50 and output to the second switch circuit <NUM> via the node N51. For example, the second bypass circuit <NUM> may be configured to, via the inverter <NUM>, drive the gate of the p-type transistor <NUM> of the second switch circuit <NUM> to turn the p-type transistor <NUM> ON and OFF, thereby to enable and to disable the second switch circuit <NUM> powering the second circuit block <NUM>.

The second delay circuit <NUM> may be configured to delay the second bypass circuit <NUM> driving the second switch circuit <NUM>. As illustrated, the second delay circuit <NUM> includes N stages of inverters 553_1 to 553_N arranged in series. For example, an output of the inverter 553_1 may be provided as an input to the inverter 553_2, and so forth. The inverters 553_1 to 553_N may be configured to be powered via a node N58. The second delay circuit <NUM> may be configured to receive signaling via a node N21 (see <FIG>, the signaling may include S103 of <FIG>), delay the received signaling, and output the delayed signaling to the second bypass circuit <NUM> via the node N59.

As presented with the power supply circuit <NUM> of <FIG>, the second switch circuit <NUM> may be configured to power the second circuit block <NUM>. The second bypass circuit <NUM> may be configured to drive the second switch circuit <NUM> to enable and to disable the second switch circuit <NUM> powering the second circuit block <NUM>, based on the control signal SLP and the control signal CLAMP. For example, the control circuit <NUM> may be configured to, based on the control signal CLAMP, cause the second bypass circuit <NUM> to drive the second switch circuit <NUM> to disable the second switch circuit <NUM> powering the second circuit block <NUM>, bypassing the second delay circuit <NUM>. For example, the control circuit <NUM> may be configured to output logic zero (e.g., ground) on the node N58 and logic one (e.g., supply voltage VDD2) on the node N56, in response to the control signal CLAMP being at logic one (e.g., supply voltage VDD2). The node N58 being at logic zero powers down the second delay circuit <NUM>, reducing leakage current while the next stage power supply circuit <NUM> is in a standby mode (e.g., inactive or unresponsive to certain control signals). The node N56 being at logic one causes the second bypass circuit <NUM> to output logic one on the node N51 and disables the second switch circuit <NUM> powering the second circuit block <NUM>.

Moreover, the second delay circuit <NUM> may be configured to delay signaling to the second bypass circuit <NUM>, the signaling being based on the control signal SLP. For example, the second delay circuit <NUM> may be configured to receive signaling on the node N21 from the power supply circuit <NUM> (see <FIG>), and to delay the received signaling via the N stages of inverters 553_1 to 553_N. As presented with the power supply circuit <NUM> of <FIG>, the signaling on the node N21 being based on (e.g., controlled by) the control signal SLP. The second delay circuit <NUM> may be further configured to output the delayed signaling to the second bypass circuit <NUM> (via the node N59) and the second switch circuit <NUM> (via the node N51). In such fashion, the control circuit <NUM> may be further configured to, based on the control signal SLP and via the second delay circuit <NUM> and the second bypass circuit <NUM>, enable and disable the second switch circuit <NUM> powering the second circuit block <NUM>.

Moreover, the second bypass circuit <NUM> may be further configured to drive the second switch circuit <NUM> to enable the second switch circuit <NUM> powering the second circuit block <NUM>, conditioned by the bypass circuit <NUM> driving the switch circuit <NUM> to enable the switch circuit <NUM> powering the circuit block <NUM>. For example, referring to <FIG>, the bypass circuit <NUM> may be configured to output logic zero onto the node N21 to enable the switch circuit <NUM> powering the circuit block <NUM>. The second delay circuit <NUM> may be configured to receive logic zero on the node N21, delay the signaling, and provide logic zero on the node N59 to the second bypass circuit <NUM>. In response, the second bypass circuit <NUM> may be configured to output logic zero to the second switch circuit <NUM>, via the node N51, enabling the second switch circuit <NUM> to power the second switch circuit <NUM>.

As presented above, the second delay circuit <NUM> may be configured to delay enabling the second switch circuit <NUM> powering the second circuit block <NUM> conditioned on the switch circuit <NUM> powering the circuit block <NUM>. For example, second delay circuit <NUM> may be configured to receive signaling on N21 (from <FIG>) and based upon which delay outputting onto the node N59. The second bypass circuit <NUM> may be configured to enabling the second switch circuit <NUM> powering the second circuit block <NUM> in response to signaling received on the node N59. The second delay circuit <NUM> may be further configured to be powered down, e.g., via the node N58. For example, the second delay circuit <NUM> may be configured to be powered, and therefore powered down, via the node N58. The second bypass circuit <NUM> may be further configured to bypass the second delay circuit <NUM> to disable the second switch circuit <NUM> powering the second circuit block <NUM>. For example, the second bypass circuit <NUM> may be configured disable the second switch circuit <NUM> powering the second circuit block <NUM> independent of signaling on the node N59 (and therefore the second delay circuit <NUM>), in response to logic one on the node N56.

<FIG> illustrate portions of a method to reduce leakage current in powering a circuit block (e.g., the circuit block <NUM> or the second circuit block <NUM>), in accordance with certain aspects of the disclosure. The operations of <FIG> may be implemented by, for example, the apparatus <NUM> presented with <FIG>. The arrows indicate certain relationships among the operations, but not necessarily sequential relationships. At <NUM>, a circuit block is powered by a switch circuit. For example, referring to <FIG>, the switch circuit <NUM> includes the p-type transistor <NUM>. The bypass circuit <NUM> turns on the p-type transistor <NUM>, via the node N21, to provide the supply voltage VDD2 on the node N23 to the switch circuit <NUM>.

At <NUM>, the switch circuit is driven by a bypass circuit to enable and to disable the switch circuit powering the circuit block, based on a first control signal and a second control signal. For example, referring to <FIG>, the bypass circuit <NUM> drives the switch circuit <NUM> via the node N21 to turn the p-type transistor <NUM> on and off. The bypass circuit <NUM> includes the NOR gate <NUM> receiving inputs from nodes N16 and N19, the inputs on N16 and N19 being based on the control signal SLP and the control signal CLAMP. For example, the control circuit <NUM>, based on the control signal SLP and the control signal CLAMP outputs to the NOR gate <NUM> via the node N16 and via the node N19 (via the delay circuit <NUM>).

At <NUM>, signaling to the bypass circuit is delayed by a delay circuit, the signaling being based on the first control signal. For example, the delay circuit <NUM> delays signaling on the node N17 and provide the delayed signaling to the bypass circuit <NUM> via the node N19. At <NUM>, the switch circuit powering the circuit block is enabled and disabled by the control circuit, based on the first control signal. For example, while the control signal CLAMP is at logic zero, the control circuit <NUM> outputs onto the node N17 based on the control signal SLP (see <FIG>). For example, in response to the control signal SLP at logic zero (and the control signal CLAMP at logic zero), the control circuit <NUM> outputs logic one onto node N17. In response to the control signal SLP at logic one (and the control signal CLAMP at logic zero), the control circuit <NUM> outputs logic zero onto node N17. The bypass circuit <NUM> drives the switch circuit <NUM> to enable the switch circuit <NUM> powering the circuit block <NUM>, in response to the node N17 at logic zero. The bypass circuit <NUM> drives the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>, in response to the node N17 at logic one.

At <NUM>, the bypass circuit is caused by the control circuit to drive the switch circuit to disable the switch circuit powering the circuit block, bypassing the delay circuit. At <NUM>, the delay circuit is powered down by the control circuit and the bypass circuit is caused by the control circuit to drive the switch circuit to disable the switch circuit powering the circuit block, in response to a first state of the second control signal and independent of the first control signal. For example, in response to the control signal CLAMP at logic one, the control circuit <NUM> outputs logic one onto the node N16, forcing the bypass circuit <NUM> to output logic one onto the node N21 (see <FIG>). In response, the switch circuit <NUM> powering the circuit block <NUM> is disabled independent of signaling on the node N19, bypassing the delay circuit <NUM>. Further, in response to the control signal CLAMP at logic one, the control circuit <NUM> outputs logic zero onto the node N18 to power down the delay circuit <NUM>.

At <NUM>, the bypass circuit is caused by the control circuit to drive the switch circuit to enable the switch circuit powering the circuit block based on the first control signal and via the delay circuit, in response to a second state of the second control signal. For example, in response to the control signal CLAMP at logic zero, the control circuit <NUM> outputs at the node N16 logic zero to enable the bypass circuit <NUM> to operate based on signaling on the node N19 (see <FIG>). With the control signal SLP at logic one, the control circuit <NUM> outputs logic one on the node N18 to power on the delay circuit <NUM>, and control circuit <NUM> outputs logic zero on the node N17. The delay circuit <NUM> delays signaling on the node N17 and outputs logic zero on the node N19 to the bypass circuit <NUM>. In response, the bypass circuit <NUM> drives the switch circuit <NUM>, via the node N21, to enable the switch circuit <NUM> powering the circuit block <NUM>. By powering on the delay circuit, and enabling the switch circuit <NUM> powering the circuit block via the delay circuit, the delay circuit and the switch circuit are powered on in a staggered fashion, thereby reducing a peak of an inrush current.

At <NUM>, the bypass circuit is caused by the control circuit to drive the switch circuit to disable the switch circuit powering the circuit block and the delay circuit is caused by the control circuit to power down, based on the first control signal and in response to the second state of the second control signal. For example, in response to the control signal CLAMP at logic zero and based on the control signal SLP at logic zero, the control circuit <NUM> outputs at the node N16 logic one to cause the bypass circuit <NUM> to output logic one on the node N21 (see <FIG>). The node N21 at logic one turns OFF the switch circuit <NUM> and therefore, the bypass circuit <NUM> drives the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM>. Moreover, with the control signal CLAMP at logic zero and the control signal SLP at logic zero, the control circuit <NUM> outputs logic zero on the node N18, powering down the delay circuit <NUM>. In sum, responsive to the control signal CLAMP at logic zero, the bypass circuit <NUM> driving the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block <NUM> and the delay circuit powering down are based on the control signal SLP at logic zero.

At <NUM>, a first portion of the control circuit is powered down in response to the state of the second control signal and independent of the first control signal. For example, referring to <FIG>, the control circuit <NUM> includes the control logic-<NUM><NUM> (e.g., the first portion). The power-down circuit <NUM> provides power of VDD1 from the node N16 to the control logic-<NUM><NUM>, via the node N15. In response to the control signal CLAMP at logic one, the power-down circuit <NUM> turns off power to the control logic-<NUM><NUM>, powering down the control logic-<NUM><NUM>. For example, the power-down circuit <NUM> may include a p-type transistor controlled by the control signal CLAMP.

At <NUM>, signaling from the delay circuit and the control circuit is received, directly or indirectly by a gate of the bypass circuit. At <NUM>, signaling from the delay circuit instructing the bypass circuit to drive the switch circuit to enable and to disable the switch circuit powering the circuit block based on the first control signal and signaling from the control circuit causing the bypass circuit to drive the switch circuit to disable the switch circuit powering the circuit block, in response to the first state of the second control signal and independent of the first control signal are received directly by the gate of the bypass circuit. For example, see <FIG>, the bypass circuit <NUM> includes the NOR gate <NUM> receiving signaling from the delay circuit <NUM> on the node N19 and receiving signaling from the control circuit <NUM> on the node N16. In other examples, examples, the NOR gate <NUM> may receive signaling on the nodes N16 and N19 via intervening circuits (not shown). As presented with <NUM>, signaling on the node N19, from the delay circuit <NUM>, instructs the bypass circuit <NUM> to drive the switch circuit <NUM> to enable and to disable the switch circuit <NUM> powering the circuit block <NUM> based on the control signal SLP. As presented with <NUM>, signaling on the node N16 from the control circuit <NUM> causing the bypass circuit <NUM> to drive the switch circuit <NUM> to disable the switch circuit <NUM> powering the circuit block, in response to logic one of the control signal CLAMP and independent of the control signal SLP.

At <NUM> (e.g., following operation <NUM>), a second circuit block is powered by a second switch circuit. For example, referring to <FIG>, the second switch circuit <NUM> powers the second circuit block <NUM>. At <NUM>, the second switch circuit is driven by a second bypass circuit to enable and to disable the second switch circuit powering the second circuit block, based on the first control signal and the second control signal. For example, referring to <FIG>, the second bypass circuit <NUM> drives the second switch circuit <NUM> via the node N51 to turn the p-type transistor <NUM> on and off. The second bypass circuit <NUM> includes the NOR gate <NUM> receiving inputs from nodes N56 and N59 (e.g., respectively the first input and the second input of the second bypass circuit <NUM>), the inputs on N56 and N59 being based on the control signal SLP and the control signal CLAMP. For example, the control circuit <NUM>, based on the control signal SLP and the control signal CLAMP outputs to the NOR gate <NUM> via the node N56 and via the node N59 (via the second delay circuit <NUM>).

At <NUM>, signaling is delayed by a second delay circuit to the second bypass circuit, the signaling being based on the output of the bypass circuit. For example, the second delay circuit <NUM> delays signaling on the node N21 and provide the delayed signaling to the second bypass circuit <NUM> via the node N59. At <NUM>, the second switch circuit powering the second circuit block is enabled and disabled the control circuit, based on the first control signal. For example, while the control signal CLAMP is at logic zero, the control circuit <NUM> outputs onto the node N21 based on the control signal SLP (see <FIG>). For example, in response to the control signal SLP at logic zero (and the control signal CLAMP at logic zero), the control circuit <NUM> outputs logic one onto the node N21. In response to the control signal SLP at logic one (and the control signal CLAMP at logic zero), the control circuit <NUM> outputs logic zero onto node N21. The second bypass circuit <NUM> drives the second switch circuit <NUM> to enable the second switch circuit <NUM> powering the second circuit block <NUM>, in response to the node N21 at logic zero. The second bypass circuit <NUM> drives the second switch circuit <NUM> to disable the second switch circuit <NUM> powering the second circuit block <NUM>, in response to the node N21 at logic one.

At <NUM>, the second bypass circuit is caused by the control circuit to drive the second switch circuit to disable the second switch circuit powering the second circuit block, bypassing the second delay circuit. For example, in response to the control signal CLAMP at logic one, the control circuit <NUM> outputs logic one onto the node N56, forcing the second bypass circuit <NUM> to output logic one onto the node N51 (see <FIG>). In response, the second switch circuit <NUM> powering the second circuit block <NUM> is disabled independent of signaling on the node N59, bypassing the second delay circuit <NUM>. Further, in response to the control signal CLAMP at logic one, the control circuit <NUM> outputs logic zero onto the node N58 to power down the second delay circuit <NUM>.

At <NUM>, the second switch circuit is driven, by the second bypass circuit, to enable the second switch circuit powering the second circuit block, conditioned by the bypass circuit driving the switch circuit to enable the switch circuit powering the circuit block. For example, the bypass circuit <NUM> driving the switch circuit <NUM> to enable the switch circuit <NUM> powering the circuit block <NUM> by outputting logic zero on the node N21 (see <FIG>). In <FIG>, the second delay circuit <NUM> receive signaling on N21 (from <FIG>) and based upon which delay outputting onto the node N59. In response to the node N59 (and the node N21) being at logic zero, the second delay circuit <NUM> drives the second switch circuit <NUM> to enable the second switch circuit <NUM> powering the second circuit block powering the second circuit block <NUM>.

<FIG> illustrate portions of another method to reduce leakage current in powering a circuit block (e.g., the circuit block <NUM> or the second circuit block <NUM>), in accordance with certain aspects of the disclosure. The operations of <FIG> may be implemented by, for example, the apparatus <NUM> presented with <FIG>. The arrows indicate certain relationships among the operations, but not necessarily sequential relationships. At <NUM>, a circuit block is powered by a switch circuit. For example, referring to <FIG>, the switch circuit <NUM> includes the p-type transistor <NUM>. The bypass circuit <NUM> turns on the p-type transistor <NUM>, via the node N21, to provide the supply voltage VDD2 on the node N23 to the switch circuit <NUM>.

At <NUM>, a delay circuit is powered down. At <NUM>, the delay circuit is powered down by the control circuit, based on the first control signal and the second control signal. At <NUM>, the delay circuit is powered down by the control circuit via a voltage shifter circuit. For example, referring to <FIG>, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic zero onto the node N18, via the NOR gate <NUM>, to power down the delay circuit <NUM>. Further, while the control signal CLAMP is not asserted, the control circuit <NUM> may power down the delay circuit <NUM> based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP at logic zero causes the control circuit <NUM> to output logic zero onto the node N18, via the voltage shifter circuit <NUM> and the NOR gate <NUM>, to power down the delay circuit <NUM>.

At <NUM>, the delay circuit is bypassed by a bypass circuit to disable the switch circuit powering the circuit block. At <NUM>, the delay circuit is bypassed by the bypass circuit to disable the switch circuit powering the circuit block based on signaling received via a second input of the bypass circuit. At <NUM>, the signaling on the second input is provided by a control circuit to bypass the delay circuit to disable the switch circuit powering the circuit block, based on a first control signal and a second control signal. At <NUM>, the signaling on the second input is provided via the voltage shifter circuit of the control circuit. For example, referring to <FIG>, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic one onto the node N16 (e.g., the second input of the bypass circuit <NUM>), via the gates <NUM> and <NUM>. In response to logic one on the node N16, the bypass circuit <NUM> bypasses (e.g., to operate regardless or independent of) the delay circuit <NUM> and to disable the switch circuit <NUM> powering the circuit block <NUM> by outputting logic one onto the node N21. Further, while the control signal CLAMP is not asserted, the control circuit <NUM> may output logic one onto the node N16 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP at logic zero causes the control circuit <NUM> to output logic one onto the node N16, via the voltage shifter circuit <NUM> and gates <NUM> and <NUM>, to bypass the delay circuit <NUM> while disabling the switch circuit <NUM> powering the circuit block <NUM>.

At <NUM>, enabling the switch circuit powering the circuit block is delayed by the delay circuit via a first input of the bypass circuit. For example, while the control signal CLAMP is de-asserted (e.g., as logic zero), the control circuit <NUM> delays the switch circuit <NUM> powering the circuit block <NUM> via the delay circuit <NUM> and the node N19 (e.g., the first input of the bypass circuit <NUM>). For example, the control signal SLP at logic one causes the control circuit <NUM> to output logic zero at the node N17, via the voltage shifter circuit <NUM> and the gates <NUM> and <NUM>. The delay circuit <NUM> delays from the node N17 and then outputs logic zero onto the node N19 (the first input). The switch circuit <NUM> is thus enabled to power the circuit block <NUM>.

At <NUM> (e.g., following <NUM> of <FIG>), signaling on the second input to bypass the delay circuit to disable the switch circuit powering the circuit block is provided by the control circuit, in response to the second control signal being asserted and independent of the first control signal. At <NUM>, the delay circuit is powered down by the control circuit in response to the second control signal being asserted and independent of the first control signal. For example, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic one onto the node N16 (e.g., the second input of the bypass circuit <NUM>), via the gates <NUM> and <NUM>. In response to logic one on the node N16, the bypass circuit <NUM> bypasses (e.g., to operate regardless or independent of) the delay circuit <NUM> and to disable the switch circuit <NUM> powering the circuit block <NUM> by outputting logic one onto the node N21. Further, referring to <FIG>, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic zero onto the node N18, via the NOR gate <NUM>, to power down the delay circuit <NUM> independent of the control signal SLP.

At <NUM>, the switch circuit powering the circuit block via the delay circuit is enabled by the control circuit in response to the second signal being not asserted and based on the first control signal. For example, referring to <FIG>, the control signal CLAMP being not asserted allows the control circuit to respond to the control signal SLP to, for example, enable the switch circuit <NUM> powering the circuit block <NUM> via the delay circuit <NUM>. For example, while the control signal CLAMP is not asserted, the control circuit <NUM> may output logic one onto the node N16 based on the control signal SLP (e.g., the first control signal). While the control signal CLAMP is de-asserted (e.g., as logic zero), the control circuit <NUM> delays the switch circuit <NUM> powering the circuit block <NUM> via the delay circuit <NUM> and the node N19 (e.g., the first input of the bypass circuit <NUM>). For example, the control signal SLP at logic one causes the control circuit <NUM> to output logic zero at the node N17, via the voltage shifter circuit <NUM> and the gates <NUM> and <NUM>. The delay circuit <NUM> delays from the node N17 and then outputs logic zero onto the node N19 (the first input). The switch circuit <NUM> is thus enabled to power the circuit block <NUM>.

At <NUM>, the signaling on the second input to the bypass circuit to bypass the delay circuit to disable the switch circuit powering the circuit block is provided by the control circuit in response to the second control signal being not asserted and based on the first control signal. For example, while the control signal CLAMP is not asserted, the control circuit <NUM> may output logic one onto the node N16 based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP at logic zero causes the control circuit <NUM> to output logic one onto the node N16, via the voltage shifter circuit <NUM> and gates <NUM> and <NUM>, to bypass the delay circuit <NUM> while disabling the switch circuit <NUM> powering the circuit block <NUM>.

At <NUM>, the second delay circuit is powered down by the control circuit in response to the second control signal being not asserted and based on the first control signal. For example, while the control signal CLAMP is not asserted, the control circuit <NUM> may power down the delay circuit <NUM> based on the control signal SLP (e.g., the first control signal). For example, the control signal SLP at logic zero causes the control circuit <NUM> to output logic zero onto the node N18, via the voltage shifter circuit <NUM> and the NOR gate <NUM>, to power down the delay circuit <NUM>.

At <NUM> (e.g., following <NUM> of <FIG>), a second circuit block is powered by a second switch circuit. For example, referring to <FIG>, the second switch circuit <NUM> includes the p-type transistor <NUM>. The second bypass circuit <NUM> turns on the p-type transistor <NUM>, via the node N51, to provide the supply voltage VDD2 on the node N23 to the second switch circuit <NUM>. At <NUM>, enabling the second switch circuit powering the second circuit block is delayed by a second delay circuit conditioned on the switch circuit powering the circuit block. For example, referring to <FIG>, the second delay circuit <NUM> delays enabling the second switch circuit <NUM> powering the second circuit block <NUM> conditioned on the switch circuit <NUM> powering the circuit block <NUM>. For example, second delay circuit <NUM> receives signaling on N21 (from <FIG>) and based upon which delay outputting onto the node N59. The second bypass circuit <NUM> enables the second switch circuit <NUM> powering the second circuit block <NUM> in response to signaling received on the node N59.

At <NUM>, a second delay circuit is powered down. For example, referring to <FIG>, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic zero onto the node N58, via the NOR gate <NUM>, to power down the second delay circuit <NUM>. At <NUM>, the second delay circuit is bypassed by a second bypass circuit to disable the second switch circuit powering the second circuit block. For example, referring to <FIG>, the control signal CLAMP (e.g., the second control signal) being asserted (e.g., to logic one) causes the control circuit <NUM> to output logic one onto the node N56 (e.g., the second input of the second bypass circuit <NUM>), via the NOR gate <NUM>. In response to logic one on the node N56, the second bypass circuit <NUM> bypasses (e.g., to operate regardless or independent of) the second delay circuit <NUM> and to disable the second switch circuit <NUM> powering the second circuit block <NUM> by outputting logic one onto the node N51.

Claim 1:
An apparatus, comprising:
a switch circuit (<NUM>) configured to power a circuit block (<NUM>);
a delay circuit (<NUM>) configured
to delay enabling the switch circuit (<NUM>) powering the circuit block (<NUM>) and
to be powered down;
a bypass circuit (<NUM>) configured to bypass the delay circuit (<NUM>) to disable the switch circuit (<NUM>) powering the circuit block (<NUM>), the bypass circuit (<NUM>) comprising a first input and a second input,
the delay circuit (<NUM>) being configured to delay enabling the switch circuit powering the circuit block via the first input, and
the bypass circuit (<NUM>) being further configured to, based on signaling received via the second input, bypass the delay circuit (<NUM>) to disable the switch circuit (<NUM>) powering the circuit block (<NUM>), the apparatus further comprising a control circuit (<NUM>) configured to, based on a first control signal and a second control signal, provide the signaling to the second input to bypass the delay circuit (<NUM>) to disable the switch circuit (<NUM>) powering the circuit block (<NUM>), the control circuit (<NUM>) being further configured to power down the delay circuit (<NUM>) based on the first control signal and the second control signal.