Patent Description:
Programmable integrated circuits (ICs) are generally user configurable and capable of implementing logic operations. There are several types of programmable ICs, including Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs), for example. CPLDs include function blocks based on programmable logic array (PLA) architecture and programmable interconnect lines to route and transmit signals between the function blocks. FPGAs include configurable logic blocks (CLBs), input output blocks (IOBs), and programmable interconnect lines that route and transmit signals. The function blocks of CPLDs, CLBs of FPGAs, and interconnect lines are configured by data stored in a configuration memory of the respective devices. The programmable interconnects and programmable logic are typically programmed by loading configuration data into internal configuration memory cells that define how the programmable elements are configured.

<CIT>) describes systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.

The invention as defined in independent claim <NUM> relates to an integrated circuit, IC, comprising: a programmable logic region ; a controller; a programmable network connected between the controller and the programmable logic region, wherein the controller is programmed to configure the programmable logic region via the programmable network; and a configuration frame driver connected between the programmable network and the programmable logic region, wherein the controller is programmed to configure the programmable logic region via the programmable network and the configuration frame driver.

The invention as defined in independent method claim <NUM> relates to a method for operating one or more integrated circuits, the method comprising: configuring at least a portion of a programmable logic region comprising transmitting first configuration data from a controller via a programmable network and a configuration frame segment driver associated with the portion of the programmable logic region; and communicating application data with the configured portion of the programmable logic region via the programmable network, and wherein configuring at least the portion of the programmable logic region further comprises: routing the first configuration data through switches of the programmable network; receiving the first configuration data from the programmable network at a slave unit; transmitting the first configuration data from the slave unit to the configuration frame segment driver; and writing to configuration memory by the configuration frame segment driver in response to the first configuration data.

These and other aspects may be understood with reference to the following detailed description.

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

Examples described herein provide for an integrated circuit (IC) that includes one or more programmable logic regions and methods for operating such an IC. In some examples, the IC includes a communication network (e.g., a programmable network of a Network-on-Chip (NoC)) that can implement communications between, e.g., a logic function, an application, a kernel, and/or the like instantiated on a programmable logic region of the IC and another component or circuit. The communication network can be a high bandwidth, high speed network, for example. Further, configuration data for configuring the one or more programmable logic regions can be communicated through the communication network. Communicating configuration data for programmable logic regions through such a communication network can permit high speed transmission and parallel processing of such data. This can permit programmable logic regions to be configured faster.

In further examples, a multi-chip structure is provided where chips can include a respective IC that includes one or more programmable logic regions. The ICs in the multi-chip structure can include a communication network that can implement communications between, e.g., a logic function, etc. instantiated on a programmable logic region of any of the ICs and another component or circuit in any of the ICs. Further, configuration data for configuring one or more programmable logic regions can be communicated through the communication network. For example, a master IC can communicate configuration data through the communication network from the master IC to a slave IC. Such examples can permit simpler circuits (e.g., processing systems) on slave ICs.

In Field Gate Programmable Array (FPGA) architectures, a dedicated configuration frame driver has been implemented for communicating configuration data to programmable logic regions (e.g., the fabric) of the FPGA. The dedicated configuration frame driver has been a low bandwidth serial connection to the programmable logic regions that does not permit parallel processing of configuration data. Additionally, the dedicated configuration frame driver does not permit out-of-order configuration. Accordingly, configuring the programmable logic regions of such FPGAs could be a relatively slow process.

System-on-Chips (SoCs) are being developed that include programmable logic regions of an FPGA architecture. These SoCs can be capable of providing an integrated solution for a number of applications. Some of such SoCs are being developed to include a high bandwidth, high speed NoC. In some examples, a SoC includes a number of segments of a configuration frame driver that correspond to respective sub-regions of programmable logic regions. Configuration data can be delivered to the configuration frame segment drivers via the network of the NoC, which permits a high speed delivery of the configuration data. Further, segmenting the configuration frame driver permits more localized and parallel processing of configuration data to configure the programmable logic regions. It is envisioned that in some examples an increase in bandwidth is <NUM> times more than a dedicated configuration frame driver.

Further, it is envisioned that some examples described herein may be implemented in virtualized computing, such as in cloud data centers. In a data center, a client may lease portions of programmable logic regions in which to implement the client's design (e.g., a logic function, etc.). The virtualized nature of such a data center can cause the programmable logic regions to be configured and reconfigured (e.g., by partial reconfiguration) a number of times to maximize the economic benefit of leasing such programmable logic regions. To further maximize the economic benefit, configuring or reconfiguring the programmable logic regions should be as fast as possible to reduce down time where the client may not be able to implement its design. Some examples provided herein can increase the speed of configuring programmable logic regions (e.g., fully configuring and/or partially reconfiguring), which can increase the economic benefit associated with a data center, for example. Additionally, in further examples, clients may further pay more or less for weights or priority in virtual channels implemented in a network of a NoC for configuration data. The weights or priority can increase or decrease the speed with which the configuration data is routed through the network of the NoC.

Aspects of these and other examples are described below. Additional or other benefits may be achieved by various examples, as a person having ordinary skill in the art will readily understand upon reading this disclosure.

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described. Further, methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders (e.g., including different serial or parallel performance of various operations) with more or fewer operations. Even further, various directions or orientations are described as, e.g., a column and a row. These designations are for ease of description of generally perpendicular directions or orientations, and other directions or orientations may be implemented.

<FIG> is a block diagram depicting a SoC <NUM> according to some examples. The SoC <NUM> is an IC that is a programmable logic device, such as a FPGA. The SoC <NUM> comprises a processing system <NUM>, a NoC <NUM>, configuration frame segment drivers <NUM>, and one or more programmable logic regions <NUM>. The SoC <NUM> may further include other circuits, such as a memory controller, multi-gigabit transceivers (MGTs), input/output blocks (IOs), and other IP circuits. The SoC <NUM> is communicatively coupled to external memory, e.g., non-volatile memory (NVM) <NUM>.

In general, the processing system <NUM> is connected to the programmable logic region(s) <NUM> through the NoC <NUM> and configuration frame segment drivers <NUM>. The processing system <NUM> and programmable logic region(s) <NUM> are further connected to the NoC <NUM> separate from the configuration frame segment drivers <NUM>, and hence, may be communicatively coupled to each other via the NoC <NUM>.

The processing system <NUM> can include one or more processor cores. For example, the processing system <NUM> can include a number of ARM-based embedded processor cores. The programmable logic region(s) <NUM> can include any number of configurable logic blocks, look-up tables, digital signal processing blocks, random access memory (RAM) blocks, UltraRAM blocks, and programmable interconnect elements. The programmable logic region(s) <NUM> may be programmed or configured using the processing system <NUM> through the NoC <NUM> and respective configuration frame segment drivers <NUM>. For example, the NoC <NUM> and configuration frame segment drivers <NUM> can enable, for example, frame-based programming of the fabric of the programmable logic region(s) <NUM> by a controller (e.g., a processor core) of the processing system <NUM> (such as a platform management controller (PMC)). The controller (e.g., PMC) can be programmed to perform various functionality as described herein, such as programming or configuring the programmable logic region(s) <NUM> and the NoC <NUM>.

The NoC <NUM> includes end-to-end Quality-of-Service (QoS) features for controlling data-flows therein. In examples, the NoC <NUM> first separates data-flows into designated traffic classes. Data-flows in the same traffic class can either share or have independent virtual or physical transmission paths. The QoS scheme applies multiple levels of priority across traffic classes. Within and across traffic classes, the NoC <NUM> applies a weighted arbitration scheme to shape the traffic flows and provide bandwidth and latency that meets the user requirements. Examples of the NoC <NUM> are discussed further below.

<FIG> is a block diagram depicting the NoC <NUM> of a SoC according to some examples. The NoC <NUM> includes NoC master units (NMUs) <NUM>, NoC slave units (NSUs) <NUM>, a network <NUM>, NoC peripheral interconnect (NPI) <NUM>, and register blocks <NUM>. Each NMU <NUM> is an ingress circuit that connects a master circuit to the NoC <NUM>. Each NSU <NUM> is an egress circuit that connects the NoC <NUM> to a slave endpoint circuit. The NMUs <NUM> are connected to the NSUs <NUM> through the network <NUM>. In some examples, the network <NUM> includes NoC packet switches <NUM> and routing <NUM> between the NoC packet switches <NUM>. Each NoC packet switch <NUM> performs switching of NoC packets. The NoC packet switches <NUM> are connected to each other and to the NMUs <NUM> and NSUs <NUM> through the routing <NUM> to implement a plurality of physical channels. The NoC packet switches <NUM> also support multiple virtual channels per physical channel. The NPI <NUM> includes circuitry to write to register blocks <NUM> that determine the functionality of the NMUs <NUM>, NSUs <NUM>, and NoC packet switches <NUM>. The NPI <NUM> includes a peripheral interconnect coupled to the register blocks <NUM> for programming thereof to set functionality. The register blocks <NUM> in the NoC <NUM> support interrupts, QoS, error handling and reporting, transaction control, power management, and address mapping control. Some configuration data for the NoC <NUM> can be stored in the NVM <NUM>, for example, and provided to the NPI <NUM> for programming the NoC <NUM> and/or other slave endpoint circuits.

<FIG> is a block diagram depicting connections between endpoint circuits in a SoC through the NoC <NUM> according to some examples. In the example, endpoint circuits <NUM> are connected to endpoint circuits <NUM> through the NoC <NUM>. The endpoint circuits <NUM> are master circuits, which are coupled to NMUs <NUM> of the NoC <NUM>. The endpoint circuits <NUM> are slave circuits coupled to the NSUs <NUM> of the NoC <NUM>. Each endpoint circuit <NUM> and <NUM> can be a circuit in the processing system <NUM>, a circuit in a programmable logic region <NUM>, or a circuit in another subsystem. Each endpoint circuit in the programmable logic region <NUM> can be a dedicated circuit (e.g., a hardened circuit) or a circuit configured in programmable logic.

The network <NUM> includes a plurality of physical channels <NUM>. The physical channels <NUM> are implemented by programming the NoC <NUM>. Each physical channel <NUM> includes one or more NoC packet switches <NUM> and associated routing <NUM>. An NMU <NUM> connects with an NSU <NUM> through at least one physical channel <NUM>. A physical channel <NUM> can also have one or more virtual channels <NUM>. The virtual channels <NUM> can implement weights to prioritize various communications along any physical channel <NUM>. Configuration data communicated through the network <NUM>, as described in more detail below, can be assigned any weight or priority. For example, configuration data can be assigned a weight or priority based on a customer's targeted speed of implementing a design.

<FIG> is a block diagram depicting connections to a register block <NUM> of, e.g., an NMU <NUM>, NoC packet switch <NUM>, or NSU <NUM> through the NPI <NUM> in a SoC <NUM> according to some examples. To connect to a register block <NUM>, the NPI <NUM> includes an NPI root node <NUM>, interconnected NPI switches <NUM>, and a protocol block <NUM>. The NPI root node <NUM> resides on a platform management controller (PMC) <NUM>, which resides in the processing system <NUM> of the SoC <NUM>.

Generally, the NPI root node <NUM> can packetize a transaction request, such as a write or read request, into a format implemented by the NPI <NUM> and can transmit a memory-mapped transaction request to interconnected NPI switches <NUM>. The transaction request can be routed through the interconnected NPI switches <NUM> to a protocol block <NUM> connected to the register block <NUM> to which the transaction request is directed. The protocol block <NUM> can then translate the memory-mapped transaction request into a format implemented by the register block <NUM> and transmit the translated request to the register block <NUM> for processing. The register block <NUM> can further transmit a response to the transaction request through the protocol block <NUM> and the interconnected NPI switches <NUM> to the NPI root node <NUM>, which then responds to the master circuit that issued the transaction request.

The NPI root node <NUM> can translate a transaction request between a protocol used by the one or more master circuits, such as the PMC <NUM>, and a protocol used by the NPI <NUM>. For example, the master circuits can implement the Advanced eXtensible Interface fourth generation (AXI4) protocol, and the NPI <NUM> can implement an NPI Protocol. The protocol blocks <NUM> can also translate the transaction request from the protocol implemented on the NPI <NUM> to a protocol implemented by the register blocks <NUM> of the NoC packet switches <NUM>. In some examples, the protocol blocks <NUM> can translate between NPI Protocol and the Advanced Microcontroller Bus Architecture (AMBA) <NUM> Advanced Peripheral Bus (APB3) protocol or a proprietary protocol like a configuration frame driver.

The PMC <NUM> further includes a configuration frame driver (CF) root node <NUM>. The configuration frame driver root node <NUM> is an endpoint circuit <NUM> to the network <NUM> of the NoC <NUM>. The configuration frame driver root node <NUM> is configured to program the fabric of the programmable logic regions <NUM> by transmitting NoC protocol packets via an NMU <NUM> and network <NUM> to respective NSUs <NUM> that can translate the NoC protocol packets to configuration frames that are implemented by respective configuration frame segment drivers <NUM>. The configuration frame segment drivers <NUM> are delivery mechanisms for programming programmable units of the programmable logic regions <NUM> on the SoC <NUM>.

<FIG> is a diagram depicting additional details of the SoC <NUM> according to some examples. Various NMUs <NUM> (each labeled with an "M") and NSUs <NUM> (each labeled with an "S") are interconnected via NoC packet switches <NUM> (each labeled with an "X") and routing <NUM>. <FIG> illustrates connections of the processing system <NUM> (including the PMC <NUM> with NPI root node <NUM> and configuration frame driver root node <NUM>), configuration frame segment drivers <NUM>, and programmable logic regions <NUM> to the NoC <NUM>.

Each programmable logic region <NUM> is separated into multiple sub-regions for configuration, and each sub-region of a programmable logic region <NUM> has a corresponding configuration frame segment driver <NUM>. The sub-regions of the programmable logic region <NUM> can correspond to a size or period of the corresponding configuration frame segment drivers <NUM>. <FIG> illustrates multiple NSUs <NUM> at each configuration frame segment driver <NUM>. One or more of the NSUs <NUM> is configured to communicate configuration data with the corresponding configuration frame segment driver <NUM> for configuring the corresponding sub-region of the programmable logic region <NUM>. If applicable, for example, one or more of the NSUs <NUM> is configured to communicate with corresponding configuration frame segment driver <NUM> for preloading and sampling data from block memory in the corresponding sub-region of the programmable logic region <NUM>. One or more of the NSUs <NUM> is configured to communicate application data with the corresponding sub-region of the programmable logic region <NUM>, e.g., with logic functions, applications, and/or kernels instantiated on the sub-region of the programmable logic region <NUM>.

<FIG> illustrates NSUs 204a, 204b, 204c at a configuration frame segment driver <NUM> according to some examples. The NSU 204a is communicatively coupled to the configuration frame segment driver <NUM> to transfer configuration data of the sub-region of the programmable logic region <NUM> to the configuration frame segment driver <NUM> from the NoC <NUM>. The configuration frame segment driver <NUM> configures the sub-region of the programmable logic region <NUM> using the configuration data. The NSU 204b is communicatively coupled to an interconnect network connected to the logic elements, e.g., columns of configurable logic blocks (CLBs) <NUM>, of the sub-region of the programmable logic region <NUM> for communicating, via the NoC <NUM>, application data with logic functions, etc. instantiated in the sub-region of the programmable logic region <NUM>. The NSU 204c is communicatively coupled to columns of block memory <NUM>, such as block RAMs (BRAMs), UltraRAMs (URAMs), look-up-table RAMs (LUTRAMs), and/or the like, for preloading and sampling data from the block memory <NUM>.

<FIG> illustrates additional details of <FIG> according to some examples. The configuration frame segment driver <NUM> of <FIG> includes a serial-deserializer circuit (SerDes) <NUM>, a read/write control circuit (R/W Control) <NUM>, and an address decoder and clock circuit (ADDR/CLK) <NUM>. A portion of a sub-region of the programmable logic region <NUM> includes a number of columns and rows of configuration memory cells <NUM> (one specifically identified) for configuring, e.g., CLBs <NUM>. The portion of the sub-region of the programmable logic region <NUM> also includes flip-flops <NUM>, <NUM> for preloading data into block memory <NUM> and flip-flops <NUM>, <NUM> for sampling data from the block memory <NUM>.

The NSUs 204a, 204c receive packets from the network <NUM> (e.g., routing <NUM> and NoC packet switches <NUM>) of the NoC <NUM>. The configuration memory cells <NUM>, bits for block memory <NUM>, and register(s) storing sub-region control signals <NUM> are mapped to an address space of the NoC <NUM>. Accordingly, packets addressed to the configuration memory cells <NUM> and register(s) for storing sub-region control signals <NUM> of the sub-region of the programmable logic region <NUM> are routed by the network <NUM> to the NSU 204a, and packets addressed to bits for block memory <NUM> of the sub-region of the programmable logic region <NUM> are routed by the network <NUM> to the NSU 204c. The NSUs 204a, 204c are configured to translate the packets to a format that is usable by the configuration frame segment driver <NUM>.

The NSUs 204a, 204c are electrically connected to the serial-deserializer circuit <NUM>. The NSUs 204a, 204c output data corresponding to the received packets to the serial-deserializer circuit <NUM>. The serial-deserializer circuit <NUM> deserializes the data output from the NSUs 204a, 204c and converts the data into frame words implemented by the read/write control circuit <NUM>. The serial-deserializer circuit <NUM> is electrically connected to the read/write control circuit <NUM> and is configured to communicate converted frame words to the read/write control circuit <NUM>. Additionally, the NSU 204a is electrically connected to the read/write control circuit <NUM> to write sub-region control signals <NUM> to register(s) in the read/write control circuit <NUM>.

In addition to register(s) for storing the sub-region control signals <NUM>, the read/write control circuit <NUM> includes a logic circuit configured to read and write to configuration memory cells <NUM> and to block memory <NUM>. The logic circuit can, for example, be enabled by one or more sub-region control signals <NUM>. The sub-region control signals <NUM> can indicate a mode, such as a configure mode, functional (e.g., mission) mode, test mode, diagnostic mode, power up/down mode, or the like, that the logic circuit enters and implements.

The read/write control circuit <NUM> is further electrically connected to the address decoder and clock circuit <NUM>. The read/write control circuit <NUM> can communicate data from a frame word to the address decoder and clock circuit <NUM>. The address decoder and clock circuit <NUM> includes a logic circuit to decode the data to identify a word line of a column in which a configuration memory cell <NUM> or block memory <NUM> that is to be written or read is disposed. The address decoder and clock circuit <NUM> further includes a circuit configured to generate or otherwise provide one or more clock signals.

The sub-region of the programmable logic region <NUM> includes a number of columns of configuration memory cells <NUM> (three columns illustrated), a number of columns of block memory <NUM> (one column illustrated), and possibly, a number of columns of other configurable logic (e.g., digital signal processing (DSP) blocks, programmable interconnect (INT) elements, etc.). The sub-region illustrated in <FIG> is a simplified illustration, as a person having ordinary skill in the art will readily understand. As illustrated, each column of configuration memory cells <NUM> has a word line WL that extends from the address decoder and clock circuit <NUM> along the respective column, and each column of block memory <NUM> has two word lines WL and two clock lines CLK that extend from the address decoder and clock circuit <NUM> along the respective column. A number of rows (two illustrated) extend across the various configurable logic elements in the sub-region of the programmable logic region <NUM>. Each row has a first bit line BL1 and a second bit line BL2 that extend from the read/write control circuit <NUM> along the respective row.

In the illustrated example, each configuration memory cell <NUM> is a static random access memory (SRAM) cell, although other memory cells may be implemented as the configuration memory cells <NUM>. Although not specifically labeled, each configuration memory cell <NUM> includes cross-coupled inverters that are coupled via transmission gates between the first bit line BL1 and the second bit line BL2 of the row in which the configuration memory cell <NUM> is disposed. The transistors of the transmission gates of the configuration memory cell <NUM> have respective gates that are coupled to the word line WL (or inverted or complementary word line) of the column in which the configuration memory cell <NUM> is disposed. In other examples, pass-gate transistors may be implemented instead of or in addition to the transmission gates.

The block memory <NUM> has a preload stage and a sample stage. The preload stage includes flip-flops <NUM>, <NUM>. The flip-flops <NUM>, <NUM> are disposed in a same column. The flip-flop <NUM> has a data input node (D) that is electrically coupled, via a transmission gate, to the first bit line BL1 of the row in which the flip-flop <NUM> is disposed. The flip-flop <NUM> has a data input node (D) that is electrically coupled, via another transmission gate, to the second bit line BL2 of the row in which the flip-flop <NUM> is disposed. The flip-flops <NUM>, <NUM> each have a data output node (Q) connected to the block memory <NUM>. The flip-flops <NUM>, <NUM> further each have a clock input node connected to the clock line CLK of the column in which the flip-flops <NUM>, <NUM> are disposed. The respective transmission gates coupling the data input node (D) of the flip-flop <NUM> to the first bit line BL1 and the data input node (D) of the flip-flop <NUM> to the second bit line BL2 have gates that are coupled to the word line WL of the column in which the flip-flops <NUM>, <NUM> are disposed.

The sample stage includes flip-flops <NUM>, <NUM>. The flip-flops <NUM>, <NUM> are disposed in a same column. The flip-flops <NUM>, <NUM> each have a data input node (D) connected to the block memory <NUM>. The flip-flop <NUM> has a data output node (Q) that is electrically coupled, via a transmission gate, to the first bit line BL1 of the row in which the flip-flop <NUM> is disposed. The flip-flop <NUM> has a data output node (Q) that is electrically coupled, via another transmission gate, to the second bit line BL2 of the row in which the flip-flop <NUM> is disposed. The flip-flops <NUM>, <NUM> further each have a clock input node connected to the clock line CLK of the column in which the flip-flops <NUM>, <NUM> are disposed. The respective transmission gates coupling the data output node (Q) of the flip-flop <NUM> to the first bit line BL1 and the data output node (Q) of the flip-flop <NUM> to the second bit line BL2 have gates that are coupled to the word line WL of the column in which the flip-flops <NUM>, <NUM> are disposed.

The configuration frame segment driver <NUM> is configured to read or write a configuration memory cell <NUM> based on a frame word, for example. The frame word can identify the configuration memory cell <NUM> to be read or written, whether the configuration memory cell <NUM> is to be read or written, and, if written, the data to be stored in the configuration memory cell <NUM>. The address decoder and clock circuit <NUM> determines in which column the configuration memory cell <NUM> is disposed and asserts a signal on the word line WL of that column to enable to the transmission gates of the configuration memory cell <NUM>. The read/write control circuit <NUM> determines in which row the configuration memory cell <NUM> is disposed and whether the configuration memory cell <NUM> is to be read or written. If a read is determined, the read/write control circuit <NUM> enables, e.g., a differential driver to sense the differential signal between the first bit line BL1 and the second bit line BL2 of the row in which the configuration memory cell <NUM> is disposed. If a write is determined, the read/write control circuit <NUM> drives the first bit line BL1 and the second bit line BL2 of the row in which the configuration memory cell <NUM> is disposed to complementary values to write an appropriate value to the configuration memory cell <NUM>. During the reading of or writing to a configuration memory cell <NUM>, the corresponding first bit line BL1 and second bit line BL2 are operated as complementary bit lines (e.g., as a bit line BL and a complementary bit line BLB) as a person having ordinary skill in the art will readily understand. Writing to a configuration memory cell <NUM> can configure a logic element in the sub-region of the programmable logic region <NUM>. Reading a configuration memory cell <NUM> can be performed to test the fidelity of the configuration of a logic element in the sub-region of the programmable logic region <NUM>.

The configuration frame segment driver <NUM> is further configured to sample (read) or preload (write) a block memory <NUM> based on a frame word, for example. The frame word can identify the block memory <NUM> to be sampled or preloaded, whether the block memory <NUM> is to be sampled or preloaded, and, if preloaded, the data to be stored in the block memory <NUM>. The address decoder and clock circuit <NUM> determines in which column the flip-flops <NUM>-<NUM> to be preloaded or sampled is disposed and asserts a signal on the word line WL of that column to enable to the transmission gates of the flip-flops <NUM>-<NUM>. The read/write control circuit <NUM> determines in which row the flip-flops <NUM>-<NUM> to be preloaded or sampled are disposed and whether the flip-flops <NUM>-<NUM> are to be preloaded or sampled. If a sample is determined, the read/write control circuit <NUM> enables drivers to sense respective signal on the first bit line BL1 and the second bit line BL2 of the row in which the flip-flops <NUM>, <NUM> are disposed. If a write is determined, the read/write control circuit <NUM> drives the first bit line BL1 and the second bit line BL2 of the row in which the flip-flops <NUM>, <NUM> are disposed to signals to write respective values to the flip-flops <NUM>, <NUM>.

During the sampling or preloading to flip-flops <NUM>-<NUM>, the corresponding first bit line BL1 and second bit line BL2 can be operated independently of each other. Operating the first bit line BL1 and second bit line BL2 independently can permit two bits to be preloaded into flip-flops <NUM>, <NUM> (e.g., one to each flip-flop <NUM>, <NUM>) and to be sampled from flip-flops <NUM>, <NUM> (e.g., one to each flip-flop <NUM>, <NUM>) for a single operation. The independent operation of the first bit line BL1 and second bit line BL2 during preloading and sampling can enable a two times greater bandwidth than, e.g., reading and writing the configuration memory cells <NUM> (e.g., preloading/sampling of the flip-flops <NUM>-<NUM> can be at twice a rate of reading/writing of the configuration memory cells <NUM>).

The example illustrated in <FIG> can have shortened lines (e.g., bit lines and/or word lines) relative to other programmable devices. The separating and segmenting of the programmable logic regions <NUM> and configuration frame segment drivers <NUM> permits these lines to be shortened. By shortening lines, bandwidth for reading/writing and/or sampling/preloading can be increased.

Additionally, since sub-regions of programmable logic region(s) <NUM> have separate configuration frame segment drivers <NUM>, configuration data for writing to configuration memory cells <NUM> can be communicated via the network <NUM> of the NoC <NUM> to different configuration frame segment drivers <NUM> for processing the configuration data and configuring the respective sub-regions of the programmable logic region(s) <NUM> in parallel. This parallel processing and parallel configuring can further increase a speed in configuring one or more programmable logic regions <NUM>.

<FIG> is a flow chart of a method <NUM> of operating an IC according to some examples. The IC includes a programmable logic region and NoC, such as described above.

At block <NUM>, NoC packet switches, NMUs, and NSUs of a NoC are configured via a NPI. In the examples described above, for example, the processing system <NUM> (e.g., the PMC <NUM>) obtains configuration data of the NoC <NUM>. The processing system <NUM> (e.g., the PMC <NUM>) transfers the configuration data to the NPI root node <NUM>, which packetizes the configuration data in to memory mapped transaction requests. The NPI root node <NUM> transmits the memory mapped transaction requests to the NPI switches <NUM>, which route the transaction requests to appropriate protocol blocks <NUM>. The protocol blocks <NUM> then translate the memory-mapped transaction requests into formats implemented by the respective register block <NUM> and transmit the translated requests to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> for processing. The appropriate data corresponding to the configuration data for the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> is written to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> to configure those NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM>.

The configuration of the NoC packet switches, NMUs, and NSUs to configure the NoC can be any configuration. The configuration can be, e.g., a minimal configuration to enable communicating configuration data for a programmable logic region through the NoC, a full system level configuration to enable communication across the NoC for any component, or any configuration therebetween.

At block <NUM>, one or more sub-regions of one or more programmable logic regions are configured via the network of the NoC and respective configuration frame segment drivers. In the examples described above, for example, the processing system <NUM> (e.g., the PMC <NUM>) obtains configuration data of the sub-region of the programmable logic region <NUM>. The processing system <NUM> (e.g., the PMC <NUM>) transfers the configuration data to the configuration frame driver root node <NUM>, which packetizes the configuration data in to NoC protocol packets. The configuration frame driver root node <NUM> transmits the NoC protocol packets to one or more NMUs <NUM>, which transmits the NoC protocol packets to the network <NUM> of the NoC <NUM>. The NoC protocol packets are then routed through various NoC packet switches <NUM> and routing <NUM> in the network <NUM> of the NoC <NUM> to the appropriate NSU 204a. The NSU 204a translates the NoC packets to a format usable by the configuration frame segment driver <NUM> and transmits the corresponding data to the configuration frame segment driver <NUM>. The serial-deserializer circuit <NUM> of the configuration frame segment driver <NUM> deserializes the data output from the NSU 204a and converts the data into frame words implemented by the read/write control circuit <NUM> of the configuration frame segment driver <NUM>. The frame word is transmitted to the read/write control circuit <NUM>, and the read/write control circuit <NUM> and address decoder and clock circuit <NUM>, based on the frame work, assert signals on the corresponding word line WL, first bit line BL1, and second bit line BL2 to write to configuration memory cells <NUM> in the sub-region of the programmable logic region <NUM>. Writing to configuration memory cells <NUM> can configure configurable elements to implement various logic functions, applications, and/or kernels.

At block <NUM>, various components or circuits in the IC communicate with the configured sub-regions of programmable logic regions via the network of the NoC. Referring again to the examples described above, any component or circuit, e.g., the processing system <NUM>, another programmable logic region <NUM>, a memory controller, a MGT, an IO, etc., can communicate, e.g., application data through the network <NUM> of the NoC <NUM> to a configured sub-region of the programmable logic region <NUM>.

In some examples, the communication is not through a configuration frame segment driver <NUM>. The component or circuit can transmit a NoC protocol packet containing application data via an NMU <NUM> and the network <NUM> (e.g., various NoC packet switches <NUM> and routing <NUM>) to an NSU 204b. The NSU 204b translates the NoC protocol packets to a format usable by the logic function, etc., of the configured sub-region of the programmable logic region <NUM> and transmits the corresponding data to the interconnect network of the programmable logic region <NUM>, which routes the data as appropriate. The logic function, etc., can respond to such communications using the same or similar path (e.g., in reverse), and/or can initiate a communication using a same or similar path (e.g., from interconnect network of the programmable logic region <NUM> to NMU <NUM>, to network <NUM>, to NSU <NUM>, and to a component or circuit).

In some examples, the communication can be also through a configuration frame segment driver <NUM>. The component or circuit can transmit a NoC protocol packet via an NMU and network <NUM> to an NSU 204c. The NSU 204c translates the NoC protocol packets to a format usable by the configuration frame segment driver <NUM> and transmits the corresponding data to the configuration frame segment driver <NUM>. The serial-deserializer circuit <NUM> of the configuration frame segment driver <NUM> deserializes the data output from the NSU 204c and converts the data into frame words implemented by the read/write control circuit <NUM> of the configuration frame segment driver <NUM>. The frame word is transmitted to the read/write control circuit <NUM>, and the read/write control circuit <NUM> and address decoder and clock circuit <NUM>, based on the frame work, assert a signal on the corresponding word line WL, and assert or sense signals on the corresponding first bit line BL1 and second bit line BL2 to preload data in flip-flops <NUM>, <NUM> or sample data from flip-flops <NUM>, <NUM> in block memory <NUM> of the programmable logic region <NUM>.

<FIG> is a block diagram of a multi-chip structure, such as a two-and-a-half-dimensional integrated circuit (<NUM>. 5DIC) structure, according to some examples. 5DIC structure includes a first chip <NUM>, a second chip <NUM>, a third chip <NUM>, and a memory chip <NUM> attached to an interposer <NUM> or another substrate. In other examples, the <NUM>. 5DIC structure may have fewer or more chips, and the memory chip <NUM> may be outside of, but communicatively coupled to, the <NUM>. 5DIC structure. Each of the first chip <NUM>, second chip <NUM>, and third chip <NUM> can be or include an integrated circuit (IC), such as a system-on-chip (SoC) as described below. The memory chip <NUM> can comprise any form of memory for storing data, such as configuration data. The first chip <NUM>, second chip <NUM>, third chip <NUM>, and memory chip <NUM> are attached to the interposer <NUM> by electrical connectors <NUM>, such as microbumps, metal pillars (e.g., copper pillars), or the like. Electrical connectors <NUM> are on a side of the interposer <NUM> opposite from the chips <NUM>, <NUM>, <NUM>, <NUM> for attaching the <NUM>. 5DIC structure to another substrate, such as a package substrate, for example. The electrical connectors <NUM> may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or the like.

The interposer <NUM> includes electrical interconnects that electrically connect various ones of the chips <NUM>, <NUM>, <NUM>, <NUM>. The electrical interconnects can include one or more metallization layers or redistribution layers on the side of the interposer <NUM> on which the chips <NUM>, <NUM>, <NUM>, <NUM> are attached, one or more through substrate vias (TSVs) through the bulk substrate (e.g., silicon substrate) of the interposer <NUM>, and/or one or more metallization layers or redistribution layers on the side of the interposer <NUM> opposing the side on which the chips <NUM>, <NUM>, <NUM>, <NUM> are attached. Hence, various signals, packets, etc. can be communicated between various ones of the chips <NUM>, <NUM>, <NUM>, <NUM>.

In other examples, more or fewer chips may be included, and the chips may be in other configurations. For example, more or fewer chips that include a SoC may be implemented, such as two, four, or more chips, and more or fewer memory chips may be included. In some examples, the multi-chip structure can include various stacked chips, such as in a three-dimensional IC (3DIC) structure. For example, two or more memory chips may be stacked on each other with the bottom memory chip being attached to the interposer <NUM>. Other multi-chip structures may be implemented in other examples, such as without an interposer. Various modifications may be made that would be readily apparent to a person having ordinary skill in the art.

<FIG> is a block diagram depicting a multi-chip structure with multiple chips each having a SoC according to some examples. The multi-chip structure includes a SoC <NUM> (e.g., on the first chip <NUM> of <FIG>), a SoC <NUM> (e.g., on the second chip <NUM>), and a SoC <NUM> (e.g., on the third chip <NUM>). Each SoC <NUM>, <NUM>, <NUM> is an IC comprising a processing system <NUM>, a NoC <NUM>, configuration frame segment drivers <NUM>, and one or more programmable logic regions <NUM>, as described above with respect to the SoC <NUM> of <FIG>. Each SoC <NUM>, <NUM>, <NUM> can be coupled to external circuits, and as illustrated, the SoC <NUM> is coupled to NVM <NUM> (e.g., on the memory chip <NUM> in <FIG>). The NVM <NUM> can store data that can be loaded to the SoCs <NUM>, <NUM>, <NUM> for configuring the SoCs <NUM>, <NUM>, <NUM>, such as configuring the NoC <NUM> and the programmable logic region(s) <NUM>. As illustrated in <FIG> and <FIG>, the NVM <NUM> is on the memory chip <NUM> attached to the interposer <NUM>; however, in other examples, memory, such as flash memory, can be external to the multi-chip structure and communicatively coupled to the SoC <NUM>, such as via an serial peripheral interface (SPI). For example, the memory may be attached to a same package substrate to which the multi-chip structure is attached, and may communicate with the SoC <NUM> via the package substrate.

In general, the processing system <NUM> of each SoC <NUM>, <NUM>, <NUM> is connected to the programmable logic region(s) <NUM> through the NoC <NUM> alone and through the NoC <NUM> with the configuration frame segment drivers <NUM>. Additionally, the NoC <NUM> of each SoC <NUM>, <NUM>, <NUM> is connected to the NoC <NUM> of each neighboring SoC <NUM>, <NUM>, <NUM>. For example, the NoCs <NUM> of the SoCs <NUM>, <NUM> are connected, and the NoCs <NUM> of the SoCs <NUM>, <NUM> are connected. The NoCs <NUM> being connected permits communication between the SoCs <NUM>, <NUM>, <NUM> via the NoCs <NUM>.

<FIG> is a block diagram depicting a multi-chip structure with interconnected NoCs <NUM> according to some examples. <FIG> illustrates some aspects of the multi-chip structure of <FIG> in more detail while omitting other aspects so as not to obscure aspects described here. The multi-chip structure includes SoCs <NUM>, <NUM>, <NUM>, each of which generally have the structure of the SoC <NUM> of <FIG>. Description of corresponding structure between the SoC <NUM> and the SoCs <NUM>, <NUM>, <NUM> is omitted here for brevity.

Routing <NUM> of each NoC <NUM> is connected to interposer drivers <NUM> (each labeled with an "I"), which are in turn connected to external connectors <NUM> (each labeled with a "C") to interconnect the NoCs <NUM> of the SoCs <NUM>, <NUM>, <NUM>. The external connectors <NUM> can be or include, for example, bumps attaching the respective chips to an interposer and/or metallization layers or redistribution layers on the interposer, such as described with respect to <FIG>. Routing <NUM> of the NoC <NUM> of SoC <NUM> is connected to respective interposer drivers <NUM> of the SoC <NUM>, which are connected via external connectors <NUM> to respective interposer drivers <NUM> of the SoC <NUM>. The interposer drivers <NUM> of the SoC <NUM> are connected to routing <NUM> of the NoC <NUM> of SoC <NUM>. Routing <NUM> of the NoC <NUM> of SoC <NUM> is connected to respective other interposer drivers <NUM> of the SoC <NUM>, which are connected via external connectors <NUM> to respective interposer drivers <NUM> of the SoC <NUM>. The interposer drivers <NUM> of the SoC <NUM> are connected to routing <NUM> of the NoC <NUM> of SoC <NUM>.

In some examples, the SoCs <NUM>, <NUM> do not include a PMC <NUM> and configuration frame driver root node <NUM> in the respective processing system <NUM>. The SoCs <NUM>, <NUM> may include a processor <NUM> (e.g., a microprocessor), including an NPI root node <NUM>, that has reduced functionality compared to a PMC <NUM>. In some examples, the processor <NUM> may implement some basic redundancy repair and feature enablement and may implement a minimal configuration on the respective SoC <NUM>, <NUM>, and PMC <NUM> of the SoC <NUM> acts as a master to the SoCs <NUM>, <NUM> to implement a system-level configuration and to configure programmable logic regions <NUM> in the SoCs <NUM>, <NUM>, <NUM>. In other examples, each SoC <NUM>, <NUM>, <NUM> can include a PMC <NUM> and configuration frame driver root node <NUM> for configuring the various components of the respective SoC <NUM>, <NUM>, <NUM>.

<FIG> is a flowchart of a method <NUM> for operating a multi-chip structure according to some examples. The method <NUM> is described in the context of the SoC <NUM> acting as a master and the SoCs <NUM>, <NUM> acting as slaves. The slave SoCs <NUM>, <NUM> include a simplified processor <NUM> as described above. Accordingly, in the method <NUM>, some configurations in the slave SoCs <NUM>, <NUM> can be initiated by the PMC <NUM> of the master SoC <NUM> and communicated through networks <NUM> of the NoCs <NUM> of the SoCs <NUM>, <NUM>, <NUM>. In other examples, each SoC <NUM>, <NUM>, <NUM> may be configured locally independent of other SoCs <NUM>, <NUM>, <NUM>.

At block <NUM>, locally at each SoC, memory that is not in a programmable logic region is repaired via the NPI of the respective SoC. In some examples, each SoC <NUM>, <NUM>, <NUM> has electric fuses (eFuses) that are programmed at manufacturing with values to permit repair of faulty memory by enabling redundant memory. The PMC <NUM> or processor <NUM> of the respective SoC <NUM>, <NUM>, <NUM> is capable of reading the values of the eFuses and responsively transmitting memory mapped transactions from the NPI root node <NUM> via the NPI <NUM> to various register blocks <NUM> to repair memory by redundancy built into the respective SoC <NUM>, <NUM>, <NUM>. The register blocks <NUM> can be in respective NMUs <NUM>, NSUs <NUM>, NoC packet switches <NUM>, interposer drivers <NUM>, or any other memory within the address space of the NPI <NUM> of the respective SoC <NUM>, <NUM>, <NUM>.

At block <NUM>, locally at each SoC, NoC packet switches, NMUs, and NSUs of the NoC of the respective SoC are configured with a NoC minimal configuration via the NPI. The NoC minimal configuration establishes a communication channel between the PMC <NUM> or processor <NUM> of the respective SoC <NUM>, <NUM>, <NUM> to configuration frame segment drivers <NUM> of that SoC <NUM>, <NUM>, <NUM>. Additionally, the NoC minimal configuration communicatively connects (e.g., as a bridge) the network <NUM> of the NoC <NUM> of each slave SoC <NUM>, <NUM> to the network <NUM> of a NoC <NUM> of a neighboring SoC proximate to the master SoC <NUM> so communication between the master SoC <NUM> and the slave SoC <NUM>, <NUM> may be established.

Each SoC <NUM>, <NUM>, <NUM> can have memory, such as read only memory (ROM), on-chip or off-chip that is electrically connected to the SoC that stores the NoC minimal configuration data. The PMC <NUM> or processor <NUM> of the respective SoC <NUM>, <NUM>, <NUM> reads the NoC minimal configuration data from the memory and transfers the NoC minimal configuration data to the NPI root node <NUM>. The NPI root node <NUM> packetizes the NoC minimal configuration data as memory mapped transactions and transmits the memory mapped transactions via the interconnected NPI switches <NUM> of the NPI <NUM> to protocol blocks <NUM> of appropriate NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> of the NoC <NUM> of the respective SoC <NUM>, <NUM>, <NUM>. The protocol blocks <NUM> then translate the memory-mapped transaction requests into formats implemented by the respective register block <NUM> and transmit the translated requests to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> for processing. The appropriate data corresponding to the NoC minimal configuration data for the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> is written to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> to configure those NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM>.

After the NoCs <NUM> are configured with the NoC minimal configuration, the NoC <NUM> of the master SoC <NUM> is configured to permit communications between the PMC <NUM> (e.g., the configuration frame driver root node <NUM>) and the configuration frame segment drivers <NUM> of the SoC <NUM>. The NoC <NUM> of the slave SoC <NUM> is configured to permit communications between the processor <NUM> and the configuration frame segment drivers <NUM> of the SoC <NUM> and to permit communications received from at least some of the external connectors <NUM> electrically connected between the SoCs <NUM>, <NUM>. The NoC <NUM> of the slave SoC <NUM> is configured to permit communications between the processor <NUM> and the configuration frame segment drivers <NUM> of the SoC <NUM> and to permit communications received from at least some of the external connectors <NUM> electrically connected between the SoCs <NUM>, <NUM>.

At block <NUM>, locally at each SoC, memory of a programmable logic region is repaired via the network of the NoC and configuration frame segment drivers of the respective SoC. As above, in some examples, each SoC <NUM>, <NUM>, <NUM> has eFuses that are programmed at manufacturing with values to permit repair of faulty memory by enabling redundant memory. The PMC <NUM> or processor <NUM> of the respective SoC <NUM>, <NUM>, <NUM> is capable of reading the values of the eFuses and responsively transmitting NoC protocol packets from the PMC <NUM> or processor <NUM> via the network <NUM> of the NoC <NUM> to respective configuration frame segment drivers <NUM>. The configuration frame segment drivers <NUM> are configured to process the repair data and to repair memory in a corresponding sub-region of a programmable logic region <NUM> by redundancy built into the respective SoC <NUM>, <NUM>, <NUM>.

At block <NUM>, locally at the master SoC, NoC packet switches, NMUs, and NSUs of the network of the NoC are configured with a NoC system-level configuration for the master SoC via the NPI of the master SoC. The PMC <NUM> of the SoC <NUM> can read the NoC system-level configuration data from memory on-chip or off-chip and transfers the NoC system-level configuration data to the NPI root node <NUM>. The NPI root node <NUM> packetizes the NoC system-level configuration data as memory mapped transactions and transmits the memory mapped transactions via the interconnected NPI switches <NUM> of the NPI <NUM> to protocol blocks <NUM> of appropriate NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> of the NoC <NUM> of the SoC <NUM>. The protocol blocks <NUM> then translate the memory-mapped transaction requests into formats implemented by the respective register block <NUM> and transmit the translated requests to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> for processing. The appropriate data corresponding to the NoC system-level configuration data for the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> is written to the register blocks <NUM> of the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> to configure those NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM>.

With the network <NUM> of the NoC <NUM> of the master SoC <NUM> being configured with the NoC system-level configuration data, and with the network <NUM> of the NoC <NUM> of the slave SoC <NUM> being configured with the NoC minimal configuration data (e.g., to configure a bridge), the PMC <NUM> of the master SoC <NUM> may communicate with the processor <NUM> of the slave SoC <NUM> via the networks <NUM> of the NoCs <NUM> of the SoCs <NUM>, <NUM>.

At block <NUM>, locally at the master SoC, one or more sub-regions of one or more programmable logic regions of the master SoC are configured via a network of the NoC and respective configuration frame segment drivers of the master SoC. In the examples described above, for example, the processing system <NUM> (e.g., the PMC <NUM>) of the master SoC <NUM> obtains configuration data of the sub-region of the programmable logic region <NUM> of the master SoC <NUM>. The configuration data is then handled and processed to configure one or more sub-regions of one or more programmable logic regions <NUM> of the master SoC <NUM> as described above with respect to block <NUM> of method <NUM> of <FIG>. Various sub-regions of the programmable logic region(s) <NUM> can be configured in parallel.

At block <NUM>, the master SoC communicates NoC system-level configuration data to a slave SoC via the networks of the NoCs of the SoCs. As described above, the networks <NUM> of the NoCs <NUM> of the SoCs <NUM>, <NUM> are configured to permit communication between the PMC <NUM> of the master SoC <NUM> and the processor <NUM> of the slave SoC <NUM>. The PMC <NUM> of the SoC <NUM> can read the NoC system-level configuration data from memory on-chip or off-chip and transfers the NoC system-level configuration data to an NMU <NUM> that packetizes the data into NoC protocol packets. The NoC protocol packets are transmitted from the NMU <NUM> to the network <NUM> of the NoC <NUM> of the SoC <NUM>, through one or more interposer drivers <NUM> on the SoC <NUM>, through one or more external connectors <NUM>, through one or more interposer drivers <NUM> on the SoC <NUM>, through the network <NUM> of the NoC <NUM> of the SoC <NUM>, to an NSU <NUM> of the SoC <NUM>. The NSU <NUM> reformats the data and transfers the NoC system-level configuration data for the SoC <NUM> to the processor <NUM> of the SoC <NUM>.

At block <NUM>, locally at the slave SoC, NoC packet switches, NMUs, and NSUs of the network of the NoC are configured with the NoC system-level configuration for the slave SoC via the NPI of the slave SoC. After having received the NoC system-level configuration data from the master SoC <NUM>, the slave SoC <NUM> configures the NoC packet switches <NUM>, NMUs <NUM>, and NSUs <NUM> of the network <NUM> of the NoC <NUM> of the SoC <NUM> via the NPI root node <NUM> and NPI <NUM> of the SoC <NUM> like described above at block <NUM> with respect to the master SoC <NUM>. With the network <NUM> of the NoC <NUM> of the SoCs <NUM>, <NUM> being configured with the NoC system-level configuration data, and with the network <NUM> of the NoC <NUM> of the slave SoC <NUM> being configured with the NoC minimal configuration data (e.g., to configure a bridge), the PMC <NUM> of the master SoC <NUM> may communicate with the processor <NUM> of the slave SoC <NUM> via the networks <NUM> of the NoCs <NUM> of the SoCs <NUM>, <NUM>, <NUM>.

At block <NUM>, initiated by the master SoC, one or more sub-regions of one or more programmable logic regions of the slave SoC are configured via the networks of the NoCs of the master and slave SoCs and respective configuration frame segment drivers of the slave SoC. In the examples described above, for example, the processing system <NUM> (e.g., the PMC <NUM>) of the master SoC <NUM> obtains configuration data of the sub-region of the programmable logic region <NUM> of the slave SoC <NUM>. The processing system <NUM> (e.g., the PMC <NUM>) of the master SoC <NUM> transfers the configuration data to the configuration frame driver root node <NUM>, which packetizes the configuration data in to NoC protocol packets. The configuration frame driver root node <NUM> transmits the NoC protocol packets to one or more NMUs <NUM>, which transmits the NoC protocol packets to the network <NUM> of the NoC <NUM> of the SoC <NUM>. The NoC protocol packets are then routed through the network <NUM> of the NoC <NUM> of the SoC <NUM>, through one or more interposer drivers <NUM> on the SoC <NUM>, through one or more external connectors <NUM>, through one or more interposer drivers <NUM> on the SoC <NUM>, through the network <NUM> of the NoC <NUM> of the SoC <NUM>, to the appropriate NSU 204a of the SoC <NUM>. The configuration data is then handled and processed to configure one or more sub-regions of one or more programmable logic regions <NUM> of the slave SoC <NUM> as described above with respect to block <NUM> of method <NUM> of <FIG>. Various sub-regions of the programmable logic region(s) <NUM> can be configured in parallel.

Blocks <NUM>, <NUM>, <NUM> can be repeated for any additional slave SoC, such as slave SoC <NUM>. The performance of blocks <NUM>, <NUM>, <NUM> can be performed as described, except communications may additionally traverse any network <NUM> of a NoC <NUM> of a SoC, any additional interposer drivers, and any external connectors that intervene between the master SoC and the slave SoC. For example, communicating from the master SoC <NUM> to the slave SoC <NUM> includes routing communications through the network <NUM> of the NoC <NUM> of the SoC <NUM>.

At block <NUM>, various components or circuits in the multi-chip structure communicate, e.g., application data with the configured sub-region(s) of programmable logic region(s) of any SoC via the network(s) of the NoCs. The networks <NUM> of the NoCs <NUM> of the SoCs <NUM>, <NUM>, <NUM> permit any component in any SoC <NUM>, <NUM>, <NUM> to communicate with any sub-region of the programmable logic regions <NUM> in any SoC <NUM>, <NUM>, <NUM>. The communication can be as described above with respect to block <NUM> of the method <NUM> of <FIG> except may additionally be through the networks <NUM> of NoCs <NUM> of the multiple SoCs <NUM>, <NUM>, <NUM>.

Any master circuit within the multi-chip structure that is communicatively connected to the networks <NUM> of NoCs <NUM> of the multiple SoCs <NUM>, <NUM>, <NUM> can be capable of configuring any sub-region of any programmable logic region <NUM> in the SoCs <NUM>, <NUM>, <NUM> via the networks <NUM> of NoCs <NUM>. For example, a master circuit on the SoC <NUM> can transmit configuration data to a configuration frame segment driver(s) <NUM> on at least one of SoCs <NUM>, <NUM> via the networks <NUM> of the NoCs <NUM> of the SoC <NUM>, <NUM>, and possibly, SoC <NUM>. Similarly, a master circuit on the SoC <NUM> can transmit configuration data to a configuration frame segment driver(s) <NUM> on at least one of SoCs <NUM>, <NUM> via the networks <NUM> of the NoCs <NUM> of the SoC <NUM>, <NUM>, or SoCs <NUM>, <NUM>. Further, a master circuit on the SoC <NUM> can transmit configuration data to a configuration frame segment driver(s) <NUM> on at least one of SoCs <NUM>, <NUM> via the networks <NUM> of the NoCs <NUM> of the SoC <NUM>, <NUM>, and possibly, <NUM>. Multiple kernels may be instantiated in any programmable logic region(s) <NUM> that can use independent network paths to asynchronously program different independent programmable logic regions <NUM>. Configuring these programmable logic regions <NUM> may be out-of-order.

<FIG> illustrate portions <NUM>, <NUM> of respective layouts of SoCs according to some examples. The portion <NUM> of <FIG> includes a PMC <NUM> in the processing system <NUM> and can be the SoC <NUM> of <FIG> or the master SoC <NUM> of <FIG>, for example. Random access memory (RAM) <NUM>, read only memory (ROM) <NUM>, eFuses (eF) <NUM>, and other support circuits <NUM> are included in the processing system <NUM> of the portion <NUM> of the layout of <FIG>. The portion <NUM> of the layout further illustrates portions of programmable logic regions <NUM>, a portion of the NoC <NUM>, an NMU <NUM>, an NSU <NUM>, and a MGT <NUM> in a layout arrangement with the processing system <NUM>.

The portion <NUM> of <FIG> includes a processor <NUM> in the processing system <NUM> and can be the slave SoC <NUM>, <NUM> of <FIG>, for example. The processing system <NUM> (and processor <NUM>), RAM <NUM>, ROM <NUM>, eFuses (eF) <NUM>, other support circuits <NUM>, NMU <NUM>, and NSU <NUM> are in the area of the portion of the NoC <NUM>. Replacing the PMC <NUM> with the processor <NUM> (e.g., simplified and/or reduced functionality processor) frees space in the layout for other components, in the illustrated example. For example, as illustrated in the portion <NUM>, additional MGTs <NUM> are included, a larger portion of a programmable logic region <NUM> is included, and a high density input/output region (HDIO) <NUM> is included. The HDIO <NUM> may be implemented to facility testing of the SoC due to, e.g., a simplified and/or reduced functionality processor being implemented.

Claim 1:
An integrated circuit, IC, (<NUM>) comprising:
a programmable logic region (<NUM>);
a controller (<NUM>);
a programmable network (<NUM>) connected between the controller and the programmable logic region, wherein the controller is programmed to configure the programmable logic region via the programmable network; characterized by
a configuration frame driver connected between the programmable network and the programmable logic region, wherein the controller is programmed to configure the programmable logic region via the programmable network and the configuration frame driver.