Patent Description:
The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations.

Non-volatile memory devices are well known in the art. See for example <CIT>, which discloses a four-gate memory cell configuration. Specifically, <FIG> of the present application illustrates a split gate memory cell <NUM> with spaced apart source and drain regions <NUM>/<NUM> formed in a silicon semiconductor substrate <NUM>. The source region <NUM> can be referred to as a source line SL (because it commonly is connected to other source regions for other memory cells in the same row or column), and the drain region <NUM> is commonly connected to a bit line by a bit line contact <NUM>. A channel region <NUM> of the substrate is defined between the source/drain regions <NUM>/<NUM>. A floating gate <NUM> is disposed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM> (and partially vertically over and insulated from the source region <NUM>). A control gate <NUM> is disposed vertically over and insulated from the floating gate <NUM>. A select gate <NUM> is disposed vertically over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>. An erase gate <NUM> is disposed vertically over and insulated from the source region <NUM> and is laterally adjacent to the floating gate <NUM>. A plurality of such memory cells can be arranged in rows and columns to form a memory cell array.

Various combinations of voltages are applied to the control gate <NUM>, select gate <NUM>, erase gate <NUM> and/or source and drain regions <NUM>/<NUM>, to program the split gate memory cell <NUM> (i.e., inject electrons onto the floating gate), to erase the split gate memory cell <NUM> (i.e., remove electrons from the floating gate), and to read the split gate memory cell <NUM> (i.e., measure or detect the conductivity of the channel region <NUM> to determine the programming state of the floating gate <NUM>).

Split gate memory cell <NUM> can be operated in a digital manner, where the split gate memory cell <NUM> is set to one of only two possible states: a programmed state and an erased state. The split gate memory cell <NUM> is erased by placing a high positive voltage on the erase gate <NUM>, and optionally a negative voltage on the control gate <NUM>, to induce tunneling of electrons from the floating gate <NUM> to the erase gate <NUM> (leaving the floating gate <NUM> in a more positively charged state - the erased state). Split gate memory cell <NUM> can be programmed by placing positive voltages on the control gate <NUM>, erase gate <NUM>, select gate <NUM> and source region <NUM>, and a current on drain region <NUM>. Electrons will then flow along the channel region <NUM> from the drain region <NUM> toward the source region <NUM>, with electrons becoming accelerated and heated whereby some of them are injected onto the floating gate <NUM> by hotelectron injection (leaving the floating gate <NUM> in a more negatively charged state - the programmed state). Split gate memory cell <NUM> can be read by placing positive voltages on the select gate <NUM> (turning on the portion of channel region <NUM> under the select gate <NUM>) and drain region <NUM> (and optionally on the erase gate <NUM> and/or the control gate <NUM>), and sensing current flow through the channel region <NUM>. If the floating gate <NUM> is positively charged (i.e. split gate memory cell <NUM> is erased), the split gate memory cell <NUM> will turn on, and electrical current will flow from drain region <NUM> to source region <NUM> (i.e. the split gate memory cell <NUM> is sensed to be in its erased "<NUM>" state based on sensed current flow). If the floating gate <NUM> is negatively charged (i.e. split gate memory cell <NUM> is programmed), the portion of channel region <NUM> under the floating gate is turned off, thereby preventing appreciable current flow (i.e., the split gate memory cell <NUM> is sensed to be in its programmed "<NUM>" state based on no, or minimal, current flow).

Table <NUM> provides non-limiting examples of erase, program and read voltages, where Vcc is power supply voltage or another positive voltage such as <NUM> V.

Split gate memory cell <NUM> can alternately be operated in an analog manner where the memory state (i.e. the amount of charge, such as the number of electrons, on the floating gate <NUM>) of the split gate memory cell <NUM> can be continuously changed anywhere from a fully erased state (minimum number of electrons on the floating gate <NUM>) to a fully programmed state (maximum number of electrons on the floating gate <NUM>), or just a portion of this range. This means the split gate memory cell <NUM> storage is analog, which allows for very precise and individual tuning of each split gate memory cell <NUM> in an array of split gate memory cells <NUM>. Alternatively, the split gate memory cell <NUM> could be operated as an MLC (multilevel cell) where it is configured to be programmed to one of many discrete values (such as <NUM> or <NUM> different values). In the case of analog or MLC programming, the programming voltages are applied for a limited time, or as a series of pulses, until the desired programming state is achieved. In the case of multiple programming pulses, intervening read operations between programming pulses can be used to determine if the desired programming state has been achieved (in which case programming ceases) or has not been achieved (in which case programming continues).

Split gate memory cell <NUM> operated in an analog manner or as an MLC may be more sensitive to noise and read current instabilities which can adversely affect the accuracy of the split gate memory cell <NUM>. One source of read current instability in analog non-volatile memory devices is the capture and emission of electrons by oxide traps located at the interface and near-interface between the gate oxide and memory cell channel region. The gate oxide is the insulation layer that separates the floating gate <NUM> from the channel region <NUM> of substrate <NUM>. When an electron is captured on an interface trap, it reduces the channel conductivity during a read operation, and thus increases the threshold voltage Vt of the split gate memory cell <NUM> (i.e., the minimum voltage on the control gate <NUM> needed to turn on the channel region <NUM> of the split gate memory cell <NUM> to produce a predetermined target current, <NUM>µA being an example). When the control gate voltage is at or above the threshold voltage Vt, a conducting path is created between the source region <NUM> and the drain region <NUM>, and a current of at least the predetermined target current flows. When the control gate voltage is below the threshold voltage Vt, a conducting path is not created, and any current between the source region <NUM> and the drain region <NUM> is considered sub-threshold or leakage current. An electron captured on an interface trap can be emitted from the interface trap, which decreases threshold voltage Vt of the memory cell, and thus increases the channel conductivity during a read operation. These single-electron events of electron capture and emission by interface traps appear as read current noise and are referred to as random telegraph noise (RTN). In general, RTN produced by a single interface trap is characterized by two states: a lower Vt state (and higher read current state) when an electron is emitted from the interface trap and a higher Vt state (and lower read current state) when an electron is captured by the interface trap. As described above, the instability of the split gate memory cell <NUM> during read can be characterized either by the threshold voltage Vt, i.e. the control gate voltage corresponding to the predetermined target current or by memory cell current under given read voltage conditions. The present examples are particularly described in relation to memory cell read instability as threshold voltage Vt, however the use of memory cell current under given read voltages are specifically contemplated.

Document <CIT> discloses a memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

Document <CIT> discloses memory cells which having read noise being identified during a programming pass and an amount of programming being increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. In one approach, during the programming pass, a cell enters a temporary lockout state when it passes a first verify test and is subject to one or more additional verify tests. Data is stored to identify the cell as a noisy cell or a non-noisy cell based on the one or more additional verify tests. Or, the cells are subject to the one or more additional verify tests at the end of the programming pass. In a subsequent programming pass, the noisy cell is programmed using a stricter verify condition. Or, the noisy cell is kept in an erased state.

RTN that occurs during programming can be addressed as part of the program operation. However, one issue with RTN is that electron emission that undesirably decreases the threshold voltage Vt of the memory cell (and therefore undesirably increases channel conductivity during a read operation) can occur after programming of the memory cell is completed. Therefore, there is a need to address RTN in analog and MLC non-volatile memory devices, such as split gate memory cell <NUM>, without limitation, to compensate for post-program RTN.

The aforementioned problems and needs are addressed by a memory device that comprises a plurality of non-volatile memory cells each comprising a first gate, and a control circuitry. The control circuitry is configured to:.

A method of programming a selected non-volatile memory cell of a plurality of non-volatile memory cells, wherein each of the plurality of non-volatile memory cells includes a first gate, the method comprising:.

Other objects and features will become apparent by a review of the specification, claims and appended figures.

The present examples illustrate a technique for compensating RTN after programming of non-volatile memory cells, such as the split gate memory cell <NUM> of <FIG> is completed, by performing post-program tuning to improve read operation accuracy.

The memory cell programming and post-program tuning techniques are implemented as part of the configuration of the control circuitry <NUM>, which controls the various device elements for the memory array, which can be better understood from the architecture of an example memory device as illustrated in <FIG>. The memory device includes an array <NUM> of the split gate memory cells <NUM>, which can be segregated into two separate planes (Plane A 52a and Plane B 52b). The split gate memory cells <NUM> can be of the type shown in <FIG>, arranged in a plurality of rows and columns in the semiconductor substrate <NUM>, and thus formed on a single chip. Adjacent to the array of array <NUM> of split gate memory cells <NUM> are an address decoder (e.g. XDEC <NUM>), source line drivers (e.g. SLDRV <NUM>), a column decoder (e.g. YMUX <NUM>), a high voltage row decoder (e.g. HVDEC <NUM>) and a bit line controller (e.g. BLINHCTL <NUM>), which are used to decode addresses and supply the various voltages to the various gates and regions of the split gate memory cells <NUM> during read, program, and erase operations for selected split gate memory cells <NUM> of the array <NUM>. Column decoder <NUM> includes a sense amplifier containing circuitry for measuring the currents on the bit lines during a read operation. Control circuitry <NUM> is configured to control the various device elements to implement each operation (program, erase, read) on selected split gate memory cells <NUM> of the array <NUM> as described herein. Charge pump CHRGPMP <NUM> provides the various voltages used to read, program and erase the selected split gate memory cells <NUM> of the array <NUM> under the control of the control circuitry <NUM>. Control circuitry <NUM> is configured to operate the memory device to program, erase and read the selected split gate memory cells <NUM> of the array <NUM>. As part of these operations, the control circuitry <NUM> can be provided with access to incoming data which is data to be programmed to the selected split gate memory cells <NUM> of the array <NUM>, along with program, erase and read commands provided on the same or different lines. Data read from the array <NUM>, i.e. from selected split gate memory cells <NUM> of the array <NUM>. is provided as outgoing data. The control circuitry <NUM> includes, or is provided access to, a separate memory such as random access memory (RAM) <NUM> for storing voltage values as described further below.

The post-program tuning technique involves the control circuitry <NUM> implementing memory cell initial programming, followed by post-program tuning for memory cells that exhibit an intolerable level of read current instability after initial programming. Memory cell programming is described first, followed by post-program tuning. Thus, control circuitry <NUM> may be loaded with software, i.e. non-transitory electronically readable instructions, or firmware, to perform the methods described below in relation to <FIG>, thereby being configured. Control circuity <NUM> may be implemented by a microcontroller, dedicated circuitry, a processor, or a combination thereof.

Memory cell programming involves programming a selected memory cell to an initial programming state using programming voltage pulses, with intervening read operations to measure a threshold voltage parameter (i.e., a minimum voltage applied to the split gate memory cell <NUM> to achieve a predetermined level of source/drain current, referred to as a target current Itarget) for the memory cell. The threshold voltage parameter is a control gate threshold voltage Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate <NUM> (also referred to herein as the first gate). Specifically, the control gate threshold voltage Vtcg is the voltage placed on the control gate <NUM> that results in the channel region <NUM> being a conducting path, and therefore results in a read current through the channel of the predetermined level of source/drain current, also known as the target current (Itarget) (e.g., <NUM>µA) to consider the memory cell turned on when the read potentials of a read operation are applied to the select gate <NUM> and drain region <NUM>. The control gate threshold voltage Vtcg varies as a function of programming state of the split gate memory cell <NUM>, but it is desired that once the split gate memory cell <NUM> is programmed to a particular programming state, any variation of control gate threshold voltage Vtcg over time be below a predetermined amount.

Initial memory cell programming is illustrated as Steps <NUM>-<NUM> in <FIG>, which is implemented to program a selected split gate memory cell <NUM> to a specific, desired, initial programming state so that it has a target control gate threshold voltage Vtcgtarget that is associated with that specific, desired, initial programming state. The technique begins in Step <NUM> with control circuitry <NUM> programming a selected split gate memory cell <NUM> of array <NUM>. As described above, this programming step involves applying programming voltages to the selected split gate memory cell <NUM> for a limited time (i.e., in at least one pulse), which results in injecting electrons onto the floating gate <NUM>. In the programming of Step <NUM>, the voltage Vcg applied to the control gate <NUM> has a control gate program voltage Vcgprogram value. In Step <NUM>, a read operation is performed which involves applying read voltages from for example SLDRV <NUM> to the selected split gate memory cell <NUM> and measuring, with column decoder <NUM> and bit line controller <NUM>, the current flowing through the channel region <NUM> of the selected split gate memory cell <NUM>, Iread. In this read operation, the voltage Vcg applied to the control gate <NUM> is the target control gate threshold voltage Vtcgtarget. In Step <NUM>, it is determined from the read operation of Step <NUM> whether or not the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcgtarget (i.e., whether the read current Iread measured by column decoder <NUM> and bit line controller <NUM> is less than or equal to the target current Itarget, where Iread equal to the target current Itarget is indicative of the control gate threshold voltage Vtcg of the memory cell reaching the target control gate threshold voltage Vtcgtarget). Read current Iread for Step <NUM> is also referred to herein as the second read current. If the determination is no (i.e., that the control gate threshold voltage Vtcg is not greater than or equal to the target control gate threshold voltage Vtcgtarget), then in Step <NUM> the control gate program voltage Vcgprogram used for programming is increased relative to that used in the previous Step <NUM> programming of the memory cell, and then Step <NUM> is repeated using the increased control gate program voltage Vcgprogram. Steps <NUM>-<NUM> are repeated, in order, by control circuitry <NUM>, until it is determined in Step <NUM> that the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcgtarget (i.e., that the read current Iread is less than or equal to the target current Itarget). At that point, the memory cell is considered programmed to its desired, initial programming state (i.e. to its target control gate threshold voltage Vtcgtarget). It is at this point where conventional programming usually ends.

However, if the programmed memory cell exhibits RTN after programming is completed, then electron(s) captured in interface trap(s) contribute to the measured control gate threshold voltage Vtcg of the memory cell as part of programming. If/when the electron(s) are emitted from the interface trap(s) after programming has ended, then the control gate threshold voltage Vtcg could drop by more than ΔVtcgmax below the target control gate threshold voltage Vtcgtarget, where ΔVtcgmax is the maximum tolerable read error in terms of control gate threshold voltage Vtcg variation. A control gate threshold voltage drop by more than ΔVtcgmax is considered to be an intolerable error during subsequent read operations. Therefore, post-program tuning begins with Step <NUM> in <FIG>, where the maximum control gate program voltage Vcgprogram value (also referred to herein as the first value) that was used in programming the memory cell (also referred to herein as the program voltage) is stored in memory (i.e., the last control gate program voltage Vcgprogram value used in programming the particular split gate memory cell, i.e., the last iteration of Step <NUM>, unless the initial control gate program voltage Vcgprogram of Step <NUM> resulted in the control gate threshold voltage Vtcg of the memory cell reaching or exceeding the target control gate threshold voltage Vtcgtarget (i.e., that the read current Iread is less than or equal to the target current Itarget), in which case the initial control gate program voltage Vcgprogram of Step <NUM> is the maximum control gate program voltage Vcgprogram value). In one example, the memory used to store the maximum Vcgprogram value is RAM <NUM> if post-program tuning is performed just after analog programming. However, if a user intends to perform post-program tuning sometime after analog programming, the maximum control gate program voltage Vcgprogram values can instead be stored in a file (e.g., in a non-volatile storage, accessible by control circuitry <NUM>) to save the data for a longer period of time. Storing the maximum control gate program voltage Vcgprogram value is performed by control circuitry <NUM> after the split gate memory cell <NUM> is found to be programmed to its desired initial program state, as described above in relation to Step <NUM>.

In Step <NUM>, the split gate memory cell <NUM> is read (also referred to herein as a first read operation) using a control gate voltage Vcg that is less than the target control gate threshold voltage Vtcgtarget used in Step <NUM>. Specifically, the control gate voltage Vcg used for this read operation is Vtcgtarget - ΔVtcg, where ΔVtcg can be, but need not be, the maximum tolerable deviation of control gate threshold voltage (ΔVtcgmax). As a non-limiting example, ΔVtcg can be, for example, <NUM> mV. In Step <NUM>, it is determined from the read operation of Step <NUM> whether or not the read current Iread is greater than the target read current Itarget. Read current Iread for Step <NUM> is also referred to herein as the first read current. If the memory cell does not exhibit post-program intolerable RTN, then the small decrease in control gate voltage Vcg by ΔVtcg during the read operation of Step <NUM> should lower the read current Iread below, or further below, Itarget, and the determination of Step <NUM> should be no, i.e. negative. In that case, the memory cell can be considered properly programmed and no post-program tuning is needed. However, as indicated in optional Step <NUM>, Steps <NUM> and <NUM> can be repeated one or more times (where the repeated read operation is also referred to herein as a second read operation), whereby the memory cell will be subjected to another round of programming, as will be described below, if there is a positive determination in Step <NUM> no matter how many previous negative determinations occurred. Repeating Steps <NUM>-<NUM> even if the result in Step <NUM> is initially negative is advantageous because an electron may not necessarily be emitted from the trap before the first read, but could be emitted from the trap after the first read, and a yes, or positive, determination in Step <NUM> can occur in subsequent read operations if there is an electron emission after the first read operation.

If the memory cell does exhibit intolerable RTN, and if before or during this read operation there is interface trap electron emission, then the control gate threshold voltage Vtcg of the memory cell will drop, resulting in a rise in read current Iread. If that rise in current exceeds Itarget, then the determination of Step <NUM> will be yes, i.e. positive, and the selected split gate memory cell <NUM> is subjected to another round of programming starting at Step <NUM>, where the maximum control gate program voltage Vcgprogram value stored in Step <NUM>, i.e. in RAM <NUM> (or other memory) is retrieved. The retrieved control gate program voltage Vcgprogram value is increased in preparation for use in programming (see Step <NUM>) (e.g., by determining a control gate program voltage Vcgprogram of increased value, also referred to herein as the second value), and the determined increased control gate program voltage Vcgprogram value is stored in RAM <NUM> (or other memory) (see Step <NUM>). The memory cell is then programmed in Step <NUM> (similar to Step <NUM> described above) using the increased control gate program voltage Vcgprogram value. The process then reverts back to Step <NUM>, where the memory cell is once again read as described above with respect to Step <NUM>, followed by the determination of Step <NUM> as described above. If the subsequent determination in Step <NUM> is yes, i.e. positive, Steps <NUM>-<NUM> are performed again, followed by another read in Step <NUM> and determination in Step <NUM>. If the subsequent determination in Step <NUM> is no, i.e. negative, post program tuning can end, or, steps <NUM>-<NUM> can be repeated one or more times as indicated in optional Step <NUM>, even though Steps <NUM>-<NUM> may have been performed one or more times. There is no limitation on the number of read and determination operations (Steps <NUM>-<NUM>) and on the number of rounds of programming (Steps <NUM>-<NUM>). The number of times that Steps <NUM>-<NUM> and <NUM>-<NUM> are repeated can be user defined by taking into account desired programming time. The post-programing tuning process can also be repeated at a time after a previous instance of post-programming tuning, in which case the increased control gate program voltage Vcgprogram value can be stored in a more permanent memory such as a hard drive or other non-volatile storage, accessible by control circuitry <NUM>, for longer term storage.

The advantage of the above described technique is that if the memory cell exhibits intolerable RTN after programming is initially completed, then it will still end up being more deeply programmed (i.e. exhibit a higher control gate threshold voltage Vtcg) than would otherwise be the case, so that the control gate threshold voltage Vtcg will not vary from the target control gate threshold voltage Vtegtarget by an undesired amount. By utilizing the above described technique, even if electron emission occurs, it is less likely that the control gate threshold voltage Vtcg of the split gate memory cell <NUM> will drop below the target control gate threshold voltage Vtcgtarget by an amount exceeding the tolerance level of ΔVtcg. This is because the split gate memory cell <NUM> is more deeply programmed above Vtcgtarget and future read operations will more accurately reflect the desired programming state of the memory cell within the tolerance level of ΔVtcg variations.

<FIG> illustrates a first alternate example, which is the same method as that described above and depicted in <FIG>, and will not be described again, except Step 6A is added before Step <NUM>, and after Step <NUM> the process reverts to Step 6A instead of to Step <NUM>. Specifically, before the memory cell is read in Step <NUM>, a negative voltage is applied to the memory cell sourced from for example SLDRV <NUM> under the control of control circuitry <NUM> (e.g. to any non-floating gate of the memory cell, such as the control gate <NUM>, erase gate <NUM>, and/or select gate <NUM>), with the negative voltage defined in relation to the potential of substrate <NUM>. This negative voltage applied to the split gate memory cell <NUM> induces electric field stress on the gate oxide of the split gate memory cell <NUM> to stimulate detrapping (emission) of electrons from the interface and near-interface oxide traps. In one example, the negative voltage is applied to the control gate <NUM>, but it can additionally or alternatively be applied to any gate or terminal that is capacitively coupled to the floating gate <NUM>. Therefore, for a split gate memory cell <NUM> that has an oxide trap which produces RTN, the negative voltage will help stimulate detrapping of electron, setting the control gate threshold voltage Vtcg to a lower threshold voltage Vt state, and increasing the chances that the determination of Step <NUM> will be positive (and therefore the memory cell will be subjected to additional programming). Since RTN has an erratic behavior, a defective memory cell may stay in one control gate threshold voltage Vtcg state even during the read operation of Step <NUM>, and it will therefore not be properly identified for additional programming of steps <NUM> - <NUM>. Therefore, application of a negative voltage (e.g., -<NUM> V to -<NUM> V) before the read operation of Step <NUM> may stimulate a memory cell with RTN to exhibit a lower control gate threshold voltage Vtcg state and, thereby, be identified in Step <NUM> for additional programming, enhancing programming efficiency and accuracy. There is some characteristic time during which memory cells maintain their control gate threshold voltage Vtcg state acquired under the applied voltage stress after its removal. Therefore, the delay between the negative voltage application of Step 6A and the read operation of Step <NUM> is in one example not longer than typical electron capture and emission time (<NUM> at room temperature, as an example), otherwise, application of the negative voltage of step 6A prior to the read operation of step <NUM> may be less efficient.

Claim 1:
A memory device, comprising:
a plurality of non-volatile memory cells each comprising a first gate; and
a control circuitry configured to:
program a selected non-volatile memory cell of the plurality of non-volatile memory cells to an initial program state that corresponds to a threshold voltage for the first gate of the selected non-volatile memory cell meeting or exceeding a target threshold voltage for the first gate of the selected non-volatile memory cell, wherein the target threshold voltage for the first gate corresponds to a target read current, wherein the programing of the selected non-volatile memory cell includes apply a program voltage having a first value to the first gate,
store the first value in a memory,
read the selected non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the selected non-volatile memory cell that is less than the target threshold voltage for the first gate to generate a first read current, and
subject the selected non-volatile memory cell to additional programming in response to a determination that the first read current is greater than the target read current, wherein the additional programming comprises:
retrieve the first value from the memory,
determine a second value greater than the first value, and
program the selected non-volatile memory cell that includes applying a program voltage having the second value to the first gate.