Patent Description:
A phased array antenna device generally has a phase shifter mounted thereon that can change the phase of a signal. The phase shifter is connected to an antenna element included in the phased array antenna device.

The following Non-Patent Literature <NUM> discloses a phase shifter in which a phase difference between a pass phase of a first path and a pass phase of a second path is the amount of phase shift. A circuit in which a plurality of first all-pass filters are connected in series is inserted in the first path, and a circuit in which a plurality of second all-pass filters are connected in series is inserted in the second path. The first all-pass filters each include two inductors and two capacitors as lumped-parameter elements. In addition, the second all-pass filters each include two inductors and two capacitors as lumped-parameter elements.

Non-Patent Literature <NUM> describes an ultra-broadband phase shifter to address the multiband requirements of <NUM> millimeter-wave systems, wherein the phase shifter construction is based on all-pass networks.

Non-Patent Literature <NUM> discloses an alternative design of a digital phase shifter with bandwidths from <NUM>:<NUM> up to <NUM>:<NUM> using common mode all-pass networks.

Lastly, <CIT> describes an analog phase shifter using a cascaded voltage tunable capacitor, wherein a circuit topology is configured to flatten out a phase- and amplitude-response over a specified range of frequencies.

Non-Patent Literature <NUM>: <NPL>. Non-Patent Literature <NUM>: <NPL>. Non-Patent Literature <NUM>: <NPL>.

In the phase shifter disclosed in Non-Patent Literature <NUM>, a combination of lumped-parameter elements that achieves an amount of phase shift and a matching condition is uniquely determined, and a frequency characteristic of the amount of phase shift is also uniquely determined. Hence, there is a problem that in a desired frequency band, a phase-shift error is uniquely determined and a desired amount of phase shift may not be able to be obtained.

The present disclosure is made to solve a problem such as that described above, and an object of the present disclosure is to obtain a phase shifter that can achieve a frequency characteristic of a desired amount of phase shift in a desired frequency band.

According to the present disclosure, a frequency characteristic of the desired amount of phase shift can be achieved in a desired frequency band.

To describe the present disclosure in more detail, embodiments for carrying out the present disclosure will be described below with reference to the accompanying drawings.

<FIG> is a configuration diagram showing a phase shifter <NUM> according to a first embodiment.

The phase shifter <NUM> includes a first all-pass filter <NUM>, a second all-pass filter <NUM>, a first switching switch <NUM>, and a second switching switch <NUM>.

The first all-pass filter <NUM> includes two inductors and three capacitors as a plurality of elements.

Namely, the first all-pass filter <NUM> includes a first inductor <NUM>, a second inductor <NUM>, a first capacitor <NUM>, a second capacitor <NUM>, and a third capacitor <NUM> as a plurality of elements.

A pass phase Φ<NUM> of the first all-pass filter <NUM> is determined by an element value of each of the first inductor <NUM>, the second inductor <NUM>, the first capacitor <NUM>, the second capacitor <NUM>, and the third capacitor <NUM>.

The second all-pass filter <NUM> includes two inductors and three capacitors as a plurality of elements.

Namely, the second all-pass filter <NUM> includes a third inductor <NUM>, a fourth inductor <NUM>, a fourth capacitor <NUM>, a fifth capacitor <NUM>, and a sixth capacitor <NUM> as a plurality of elements.

A pass phase Φ<NUM> of the second all-pass filter <NUM> is determined by an element value of each of the third inductor <NUM>, the fourth inductor <NUM>, the fourth capacitor <NUM>, the fifth capacitor <NUM>, and the sixth capacitor <NUM>.

A connection terminal 13a of the first switching switch <NUM> is connected to either one of one end 20a of a first path <NUM> and one end 30a of a second path <NUM>.

The first switching switch <NUM> provides a signal to either one of the first all-pass filter <NUM> and the second all-pass filter <NUM>.

Namely, when the connection terminal 13a is connected to the one end 20a of the first path <NUM>, the first switching switch <NUM> provides a signal to the first all-pass filter <NUM>.

When the connection terminal 13a is connected to the one end 30a of the second path <NUM>, the first switching switch <NUM> provides a signal to the second all-pass filter <NUM>.

A connection terminal 14a of the second switching switch <NUM> is connected to either one of the other end 20b of the first path <NUM> and the other end 30b of the second path <NUM>.

The second switching switch <NUM> selects a signal having passed through the first all-pass filter <NUM> or a signal having passed through the second all-pass filter <NUM>.

Namely, when the connection terminal 13a of the first switching switch <NUM> is connected to the one end 20a of the first path <NUM> and the connection terminal 14a is connected to the other end 20b of the first path <NUM>, the second switching switch <NUM> selects a signal having passed through the first all-pass filter <NUM>.

When the connection terminal 13a of the first switching switch <NUM> is connected to the one end 30a of the second path <NUM> and the connection terminal 14a is connected to the other end 30b of the second path <NUM>, the second switching switch <NUM> selects a signal having passed through the second all-pass filter <NUM>.

The first path <NUM> is a path that connects the first switching switch <NUM> to the second switching switch <NUM>. The first inductor <NUM> is inserted in the first path <NUM>.

The second path <NUM> is a path that connects the first switching switch <NUM> to the second switching switch <NUM>. The third inductor <NUM> is inserted in the second path <NUM>.

The one end 20a of the first path <NUM> or the one end 30a of the second path <NUM> is connected to the connection terminal 13a of the first switching switch <NUM>.

The other end 20b of the first path <NUM> or the other end 30b of the second path <NUM> is connected to the connection terminal 14a of the second switching switch <NUM>.

The first inductor <NUM> is inserted in the first path <NUM>.

The element value of the first inductor <NUM> is L1r.

One end of the first capacitor <NUM> is connected to one end of the first inductor <NUM>.

The other end of the first capacitor <NUM> is connected to each of the other end of the second capacitor <NUM> and one end of the second inductor <NUM>.

The element value of the first capacitor <NUM> is C1r.

One end of the second capacitor <NUM> is connected to the other end of the first inductor <NUM>.

The other end of the second capacitor <NUM> is connected to each of the other end of the first capacitor <NUM> and the one end of the second inductor <NUM>.

The element value of the second capacitor <NUM> is C1r.

The one end of the second inductor <NUM> is connected to the other end of each of the first capacitor <NUM> and the second capacitor <NUM>.

The other end of the second inductor <NUM> is connected to one end of the third capacitor <NUM>.

The element value of the second inductor <NUM> is L2r.

The one end of the third capacitor <NUM> is connected to the other end of the second inductor <NUM>.

The other end of the third capacitor <NUM> is grounded.

The element value of the third capacitor <NUM> is C2r.

The third inductor <NUM> is inserted in the second path <NUM>.

The element value of the third inductor <NUM> is L1p.

One end of the fourth capacitor <NUM> is connected to one end of the third inductor <NUM>.

The other end of the fourth capacitor <NUM> is connected to each of the other end of the fifth capacitor <NUM> and one end of the fourth inductor <NUM>.

The element value of the fourth capacitor <NUM> is C1p.

One end of the fifth capacitor <NUM> is connected to the other end of the third inductor <NUM>.

The other end of the fifth capacitor <NUM> is connected to each of the other end of the fourth capacitor <NUM> and the one end of the fourth inductor <NUM>.

The element value of the fifth capacitor <NUM> is C1p.

The one end of the fourth inductor <NUM> is connected to the other end of each of the fourth capacitor <NUM> and the fifth capacitor <NUM>.

The other end of the fourth inductor <NUM> is connected to one end of the sixth capacitor <NUM>.

The element value of the fourth inductor <NUM> is L2p.

The one end of the sixth capacitor <NUM> is connected to the other end of the fourth inductor <NUM>.

The other end of the sixth capacitor <NUM> is grounded.

The element value of the sixth capacitor <NUM> is C2p.

Next, operations of the phase shifter <NUM> shown in <FIG> will be described.

The first all-pass filter <NUM> forms a phase reference circuit and the second all-pass filter <NUM> forms a phase-delay circuit.

The amount of phase shift Φ of the phase shifter <NUM> shown in <FIG> is determined by a phase difference between a pass phase Φ<NUM> of the first all-pass filter <NUM> and a pass phase Φ<NUM> of the second all-pass filter <NUM>.

When the connection terminal 13a of the first switching switch <NUM> is connected to the one end 20a of the first path <NUM>, a signal is provided to the first all-pass filter <NUM> from, for example, a transmitter which is not shown through the first switching switch <NUM>.

When the connection terminal 14a of the second switching switch <NUM> is connected to the other end 20b of the first path <NUM>, the signal having passed through the first all-pass filter <NUM> is outputted to, for example, an antenna element which is not shown through the second switching switch <NUM>.

When the connection terminal 13a of the first switching switch <NUM> is connected to the one end 30a of the second path <NUM>, a signal is provided to the second all-pass filter <NUM> from, for example, the transmitter which is not shown through the first switching switch <NUM>.

When the connection terminal 14a of the second switching switch <NUM> is connected to the other end 30b of the second path <NUM>, the signal having passed through the second all-pass filter <NUM> is outputted to, for example, the antenna element which is not shown through the second switching switch <NUM>.

It is assumed that the impedance of each of the antenna element and the transmitter is Z<NUM>, and the phase shifter <NUM> achieves both of impedance matching with the antenna element and impedance matching with the transmitter.

When the element values of the plurality of elements included in the first all-pass filter <NUM> and the element values of the plurality of elements included in the second all-pass filter <NUM> satisfy the following equation (<NUM>), the phase shifter <NUM> can achieve impedance matching at all frequencies.

In equation (<NUM>), ω<NUM> is the center angular frequency of a frequency band of each of the first all-pass filter <NUM> and the second all-pass filter <NUM>, and ωt and G are common variables for each element value.

The amount of phase shift Φ of the phase shifter <NUM> shown in <FIG> is determined by a phase difference between the pass phase Φ<NUM> of the first all-pass filter <NUM> and the pass phase Φ<NUM> of the second all-pass filter <NUM>, and the amount of phase shift Φ<NUM> at the center angular frequency ω<NUM> is represented by the following equation (<NUM>): <MAT>.

As shown in equation (<NUM>), each of ωt and G is a free variable for changing the amount of phase shift Φ<NUM> at the center angular frequency ω<NUM>.

Thus, by changing ωt or G, the amount of phase shift Φ<NUM> at the center angular frequency ω<NUM> can be changed while matching at impedance Z<NUM> is achieved.

Note that when, as in the phase shifter described in Non-Patent Literature <NUM>, each of the first all-pass filters and the second all-pass filters includes two inductors and two capacitors as a plurality of elements, the amount of phase shift Φ<NUM> at the center angular frequency ω<NUM> is represented as shown in the following equation (<NUM>): <MAT>.

The phase shifter described in Non-Patent Literature <NUM> has one free variable ωt for changing the amount of phase shift Φ<NUM> at the center angular frequency ω<NUM>. By determining ωt, a combination of elements is uniquely determined and the amounts of phase shift other than that at the center angular frequency ω<NUM> are also uniquely determined, and thus, a frequency characteristic of the amount of phase shift is uniquely determined. Thus, there is little flexibility in design for widening frequency band. Hence, in a desired frequency band, a phase-shift error is uniquely determined, and thus, a desired amount of phase shift may not be able to be obtained.

The phase shifter <NUM> shown in <FIG> has two free variables ωt and G for changing the amount of phase shift Φ, and there is more flexibility in design for widening frequency band than in the phase shifter described in Non-Patent Literature <NUM>.

<FIG> is an explanatory diagram showing simulation results of the amount of phase shift Φ of the phase shifter <NUM> shown in <FIG>.

Simulations of <FIG> are shown for the phase shifter <NUM> that is designed with a center frequency f<NUM> of <NUM> [GHz] and an amount of phase shift Φ<NUM> at the center frequency f<NUM> of <NUM> [degrees]. Here, a relationship between the center frequency f<NUM> and the center angular frequency ω<NUM> is represented by ω<NUM> = 2πf<NUM>. As a free variable for changing a frequency characteristic of the amount of phase shift Φ of the phase shifter <NUM>, the variable G is changed. Namely, the amount of phase shift Φ for G = <NUM>, G = <NUM>, G = <NUM>, G = <NUM>, G = <NUM>, and G = <NUM> is simulated.

As shown in <FIG>, it can be seen that by changing the variable G, the frequency characteristic of the amount of phase shift Φ changes.

In the above-described first embodiment, the phase shifter <NUM> is configured in such a manner that the phase shifter <NUM> includes the first all-pass filter <NUM> including a plurality of elements; the second all-pass filter <NUM> including a plurality of elements; the first switching switch <NUM> that provides a signal to either one of the first all-pass filter <NUM> and the second all-pass filter <NUM>; and the second switching switch <NUM> that selects the signal having passed through the first all-pass filter <NUM> or the signal having passed through the second all-pass filter <NUM>, and the first all-pass filter <NUM> includes two inductors and three capacitors as the plurality of elements, and the second all-pass filter <NUM> includes two inductors and three capacitors as the plurality of elements, and element values of the plurality of elements included in the first all-pass filter <NUM> and element values of the plurality of elements included in the second all-pass filter <NUM> are determined by impedance at which impedance matching is achieved, the frequency of the signal, and a variable. Thus, the phase shifter <NUM> can achieve a frequency characteristic of the desired amount of phase shift in a desired frequency band.

In a second embodiment not covered by the claims, a phase shifter <NUM> will be described in which a first all-pass filter <NUM> includes three inductors and two capacitors as a plurality of elements and a second all-pass filter <NUM> includes three inductors and two capacitors as a plurality of elements.

<FIG> is a configuration diagram showing the phase shifter <NUM> according to the second embodiment. In <FIG>, the same reference signs as those of <FIG> indicate the same or corresponding portions and thus description thereof is omitted.

The phase shifter <NUM> includes the first all-pass filter <NUM>, the second all-pass filter <NUM>, a first switching switch <NUM>, and a second switching switch <NUM>.

The first all-pass filter <NUM> includes three inductors and two capacitors as a plurality of elements.

Namely, the first all-pass filter <NUM> includes a first inductor <NUM>, a second inductor <NUM>, a third inductor <NUM>, a first capacitor <NUM>, and a second capacitor <NUM> as a plurality of elements.

A pass phase Φ<NUM> of the first all-pass filter <NUM> is determined by an element value of each of the first inductor <NUM>, the second inductor <NUM>, the third inductor <NUM>, the first capacitor <NUM>, and the second capacitor <NUM>.

The second all-pass filter <NUM> includes three inductors and two capacitors as a plurality of elements.

Namely, the second all-pass filter <NUM> includes a fourth inductor <NUM>, a fifth inductor <NUM>, a sixth inductor <NUM>, a third capacitor <NUM>, and a fourth capacitor <NUM> as a plurality of elements.

A pass phase Φ<NUM> of the second all-pass filter <NUM> is determined by an element value of each of the fourth inductor <NUM>, the fifth inductor <NUM>, the sixth inductor <NUM>, the third capacitor <NUM>, and the fourth capacitor <NUM>.

The first capacitor <NUM> is inserted in a first path <NUM>.

The element value of the first capacitor <NUM> is C1r'.

One end of the first inductor <NUM> is connected to one end of the first capacitor <NUM>.

The other end of the first inductor <NUM> is connected to each of the other end of the second inductor <NUM> and one end of the second capacitor <NUM>.

The element value of the first inductor <NUM> is L1r'.

One end of the second inductor <NUM> is connected to the other end of the first capacitor <NUM>.

The other end of the second inductor <NUM> is connected to each of the other end of the first inductor <NUM> and the one end of the second capacitor <NUM>.

The element value of the second inductor <NUM> is L1r'.

The one end of the second capacitor <NUM> is connected to the other end of each of the first inductor <NUM> and the second inductor <NUM>.

The other end of the second capacitor <NUM> is connected to one end of the third inductor <NUM>.

The element value of the second capacitor <NUM> is C2r'.

The one end of the third inductor <NUM> is connected to the other end of the second capacitor <NUM>.

The other end of the third inductor <NUM> is grounded.

The element value of the third inductor <NUM> is L1r'.

The third capacitor <NUM> is inserted in a second path <NUM>.

The element value of the third capacitor <NUM> is C1p'.

One end of the fourth inductor <NUM> is connected to one end of the third capacitor <NUM>.

The other end of the fourth inductor <NUM> is connected to each of the other end of the fifth inductor <NUM> and one end of the fourth capacitor <NUM>.

The element value of the fourth inductor <NUM> is L1p'.

One end of the fifth inductor <NUM> is connected to the other end of the third capacitor <NUM>.

The other end of the fifth inductor <NUM> is connected to each of the other end of the fourth inductor <NUM> and the one end of the fourth capacitor <NUM>.

The element value of the fifth inductor <NUM> is L1p'.

The one end of the fourth capacitor <NUM> is connected to the other end of each of the fourth inductor <NUM> and the fifth inductor <NUM>.

The other end of the fourth capacitor <NUM> is connected to one end of the sixth inductor <NUM>.

The element value of the fourth capacitor <NUM> is C2p'.

The one end of the sixth inductor <NUM> is connected to the other end of the fourth capacitor <NUM>.

The other end of the sixth inductor <NUM> is grounded.

The element value of the sixth inductor <NUM> is L2p'.

The amount of phase shift Φ of the phase shifter <NUM> shown in <FIG> is determined by a phase difference between the pass phase Φ<NUM> of the first all-pass filter <NUM> and the pass phase Φ<NUM> of the second all-pass filter <NUM>.

When a connection terminal 13a of the first switching switch <NUM> is connected to one end 20a of the first path <NUM>, a signal is provided to the first all-pass filter <NUM> from, for example, a transmitter which is not shown through the first switching switch <NUM>.

When a connection terminal 14a of the second switching switch <NUM> is connected to the other end 20b of the first path <NUM>, the signal having passed through the first all-pass filter <NUM> is outputted to, for example, an antenna element which is not shown through the second switching switch <NUM>.

When the connection terminal 13a of the first switching switch <NUM> is connected to one end 30a of the second path <NUM>, a signal is provided to the second all-pass filter <NUM> from, for example, the transmitter which is not shown through the first switching switch <NUM>.

In the above-described second embodiment, the phase shifter <NUM> is configured in such a manner that the phase shifter <NUM> includes the first all-pass filter <NUM> including a plurality of elements; the second all-pass filter <NUM> including a plurality of elements; the first switching switch <NUM> that provides a signal to either one of the first all-pass filter <NUM> and the second all-pass filter <NUM>; and the second switching switch <NUM> that selects the signal having passed through the first all-pass filter <NUM> or the signal having passed through the second all-pass filter <NUM>, and the first all-pass filter <NUM> includes three inductors and two capacitors as the plurality of elements, and the second all-pass filter <NUM> includes three inductors and two capacitors as the plurality of elements, and element values of the plurality of elements included in the first all-pass filter <NUM> and element values of the plurality of elements included in the second all-pass filter <NUM> are determined by impedance at which impedance matching is achieved, the frequency of the signal, and a variable. Thus, the phase shifter <NUM> can achieve a frequency characteristic of the desired amount of phase shift in a desired frequency band.

In a third embodiment, a phase shifter <NUM> will be described in which a plurality of first all-pass filters <NUM> inserted in a first path <NUM> are connected in series and a plurality of second all-pass filters <NUM> inserted in a second path <NUM> are connected in series.

<FIG> is a configuration diagram showing the phase shifter <NUM> according to the third embodiment. In <FIG>, the same reference signs as those of <FIG> and <FIG> indicate the same or corresponding portions and thus description thereof is omitted.

A phase reference circuit <NUM> is provided between a first switching switch <NUM> and a second switching switch <NUM>, and includes a plurality of first all-pass filters <NUM> shown in <FIG>. The plurality of first all-pass filters <NUM> are connected in series with each other.

In the phase shifter <NUM> shown in <FIG>, the phase reference circuit <NUM> includes the plurality of first all-pass filters <NUM>. In an embodiment not covered by the claims, the phase reference circuit <NUM> may include a plurality of first all-pass filters <NUM> shown in <FIG>, instead of the first all-pass filters <NUM> shown in <FIG>.

A phase-delay circuit <NUM> is provided between the first switching switch <NUM> and the second switching switch <NUM>, and includes a plurality of second all-pass filters <NUM> shown in <FIG>. The plurality of second all-pass filters <NUM> are connected in series with each other.

In the phase shifter <NUM> shown in <FIG>, the phase-delay circuit <NUM> includes the plurality of second all-pass filters <NUM>. In an embodiment not covered by the claims, the phase-delay circuit <NUM> may include a plurality of second all-pass filters <NUM> shown in <FIG>, instead of the second all-pass filters <NUM> shown in <FIG>.

A pass phase of the phase reference circuit <NUM> is a total sum of pass phases Φ<NUM> of the plurality of first all-pass filters <NUM>, and a pass phase of the phase-delay circuit <NUM> is a total sum of pass phases Φ<NUM> of the plurality of second all-pass filters <NUM>.

The amount of phase shift Φ of the phase shifter <NUM> shown in <FIG> is determined by a phase difference between the pass phase of the phase reference circuit <NUM> and the pass phase of the phase-delay circuit <NUM>.

<FIG> and <FIG> are explanatory diagrams showing simulation results of the amount of phase shift Φ obtained when the phase reference circuit <NUM> includes only one first all-pass filter <NUM> (hereinafter, referred to as "first all-pass filter <NUM> at the first stage") and the phase-delay circuit <NUM> includes only one second all-pass filter <NUM> (hereinafter, referred to as "second all-pass filter <NUM> at the first stage").

In a simulation of the amount of phase shift Φ shown in <FIG>, each element value is designed in such a manner that when the center frequency f<NUM> is <NUM> [GHz], the amount of phase shift Φ<NUM> at the center frequency f<NUM> is <NUM> degrees, and the amount of phase shift Φ of the phase shifter <NUM> has a maximal value at the center frequency f<NUM>.

In simulations of the amount of phase shift Φ shown in <FIG>, each element value is designed in such a manner that when the center frequency f<NUM> is <NUM> [GHz], the amount of phase shift Φ<NUM> at the center frequency f<NUM> is <NUM> degrees, and the amount of phase shift Φ of the phase shifter <NUM> has a minimal value at the center frequency f<NUM>.

It is assumed that the phase reference circuit <NUM> includes two first all-pass filters <NUM>, and the phase-delay circuit <NUM> includes two second all-pass filters <NUM>.

In this case, a first all-pass filter <NUM> that is the first one from the first switching switch <NUM> is a first all-pass filter <NUM> at the first stage, and a first all-pass filter <NUM> that is the second one from the first switching switch <NUM> is a first all-pass filter <NUM> at the second stage.

In addition, a second all-pass filter <NUM> that is the first one from the first switching switch <NUM> is a second all-pass filter <NUM> at the first stage, and a second all-pass filter <NUM> that is the second one from the first switching switch <NUM> is a second all-pass filter <NUM> at the second stage.

It is assumed that each element value is designed in such a manner that for the amount of phase shift Φ produced by the first all-pass filter <NUM> at the first stage and the second all-pass filter <NUM> at the first stage, as shown in <FIG>, the amount of phase shift Φ<NUM> at the center frequency f<NUM> is <NUM> degrees, and the amount of phase shift Φ of the phase shifter <NUM> has a maximal value at the center frequency f<NUM>.

On the other hand, it is assumed that each element value is designed in such a manner that for the amount of phase shift Φ produced by the first all-pass filter <NUM> at the second stage and the second all-pass filter <NUM> at the second stage, as shown in <FIG>, the amount of phase shift Φ<NUM> at the center frequency f<NUM> is <NUM> degrees, and the amount of phase shift Φ of the phase shifter <NUM> has a minimal value at the center frequency f<NUM>.

In a case of the above-described design, as shown in <FIG>, frequency dependence of the amount of phase shift Φ produced by the first all-pass filter <NUM> at the first stage and the second all-pass filter <NUM> at the first stage and frequency dependence of the amount of phase shift Φ produced by the first all-pass filter <NUM> at the second stage and the second all-pass filter <NUM> at the second stage compensate for each other. By compensation for the frequency dependence, a phase-shift error of the phase shifter <NUM> is reduced.

In simulations of the amount of phase shift Φ, the center frequency f<NUM> is <NUM> [GHz] and a variable G for element values of elements included in the first all-pass filter <NUM> at the second stage and the second all-pass filter <NUM> at the second stage is changed. Namely, the amount of phase shift Φ for G = <NUM>, G = <NUM>, G = <NUM>, G = <NUM>, G = <NUM>, and G = <NUM> is simulated.

As shown in <FIG>, by changing the variable G for element values of elements included in the first all-pass filter <NUM> at the second stage and the second all-pass filter <NUM> at the second stage, it can be seen that the compensation for frequency dependence of the amount of phase shift produced by each of the first all-pass filter <NUM> at the first stage and the second all-pass filter <NUM> at the first stage is performed, and a phase-shift error of the phase shifter <NUM> is reduced.

Here, it is assumed that the phase reference circuit <NUM> includes two first all-pass filters <NUM> and the phase-delay circuit <NUM> includes two second all-pass filters <NUM>, and the amounts of phase shift for the first stage and the second stage both achieve the amount of phase shift Φ<NUM> at the center frequency f<NUM>.

In general, the phase reference circuit <NUM> may include N first all-pass filters <NUM> and the phase-delay circuit <NUM> may include N second all-pass filters <NUM>, and the center frequency f<NUM> and the amount of phase shift Φ<NUM> at the center frequency f<NUM> for each stage may vary between stages. In addition, each circuit may include only all-pass filters whose frequency characteristic of the amount of phase shift Φ at each stage has a maximal value, or may include only all-pass filters whose frequency characteristic of the amount of phase shift Φ at each stage has a minimal value. In addition, each circuit may include a combination of all-pass filters whose frequency characteristic of the amount of phase shift Φ at each stage has a maximal value and all-pass filters whose frequency characteristic of the amount of phase shift Φ at each stage has a minimal value. The order of cascade connection of the N first all-pass filters <NUM> may be any and the order of cascade connection of the N second all-pass filters <NUM> may be any.

In a fourth embodiment, a phase shifter <NUM> will be described in which a phase reference circuit <NUM> includes a third all-pass filter <NUM> in addition to a first all-pass filter <NUM>, and a phase-delay circuit <NUM> includes a fourth all-pass filter <NUM> in addition to a second all-pass filter <NUM>.

<FIG> is a configuration diagram showing the phase shifter <NUM> according to the fourth embodiment. In <FIG>, the same reference signs as those of <FIG>, <FIG> indicate the same or corresponding portions and thus description thereof is omitted.

The third all-pass filter <NUM> is connected in series with the first all-pass filter <NUM>.

The third all-pass filter <NUM> includes two inductors and two capacitors as a plurality of elements.

Namely, the third all-pass filter <NUM> includes inductors <NUM> and <NUM> and capacitors <NUM> and <NUM> as a plurality of elements.

The capacitor <NUM> is inserted in a first path <NUM>.

One end of the inductor <NUM> is connected to one end of the capacitor <NUM>.

The other end of the inductor <NUM> is connected to each of the other end of the inductor <NUM> and one end of the capacitor <NUM>.

One end of the inductor <NUM> is connected to the other end of the capacitor <NUM>.

The other end of the inductor <NUM> is connected to each of the other end of the inductor <NUM> and the one end of the capacitor <NUM>.

The one end of the capacitor <NUM> is connected to each of the other end of the inductor <NUM> and the other end of the inductor <NUM>.

The other end of the capacitor <NUM> is grounded.

The fourth all-pass filter <NUM> is connected in series with the second all-pass filter <NUM>.

The fourth all-pass filter <NUM> includes two inductors and two capacitors as a plurality of elements.

Namely, the fourth all-pass filter <NUM> includes inductors <NUM> and <NUM> and capacitors <NUM> and <NUM> as a plurality of elements.

The capacitor <NUM> is inserted in a second path <NUM>.

One end of the inductor <NUM> is connected to the other end of the capacitor <NUM>. The other end of the inductor <NUM> is connected to each of the other end of the inductor <NUM> and the one end of the capacitor <NUM>.

In the phase shifter <NUM> shown in <FIG>, the phase reference circuit <NUM> includes the third all-pass filter <NUM> in addition to the first all-pass filter <NUM>, and the phase-delay circuit <NUM> includes the fourth all-pass filter <NUM> in addition to the second all-pass filter <NUM>.

In an embodiment not covered by the claims, the phase reference circuit <NUM> may include the third all-pass filter <NUM> in addition to a first all-pass filter <NUM>, and the phase-delay circuit <NUM> may include the fourth all-pass filter <NUM> in addition to a second all-pass filter <NUM>.

In another embodiment not covered by the claims, the phase reference circuit <NUM> may include the third all-pass filter <NUM> in addition to the first all-pass filter <NUM> and a first all-pass filter <NUM>, and the phase-delay circuit <NUM> may include the fourth all-pass filter <NUM> in addition to the second all-pass filter <NUM> and a second all-pass filter <NUM>.

The third all-pass filter <NUM> corresponds to the first all-pass filter described in Non-Patent Literature <NUM>.

In addition, the fourth all-pass filter <NUM> corresponds to the second all-pass filter described in Non-Patent Literature <NUM>.

Thus, a phase shifter that includes only the third all-pass filter <NUM> included in the phase reference circuit <NUM> and the fourth all-pass filter <NUM> included in the phase-delay circuit <NUM> cannot change a frequency characteristic of the amount of phase shift while impedance matching is achieved.

However, in the phase shifter <NUM> shown in <FIG>, the phase reference circuit <NUM> includes the first all-pass filter <NUM> and the phase-delay circuit <NUM> includes the second all-pass filter <NUM>, and thus, the amount of phase shift can be changed while impedance matching is achieved.

The elements included in the third all-pass filter <NUM> are two inductors <NUM> and <NUM> and two capacitors <NUM> and <NUM>, and the number of the elements included in the third all-pass filter <NUM> is smaller than the number of elements included in the first all-pass filter <NUM>.

In addition, the elements included in the fourth all-pass filter <NUM> are two inductors <NUM> and <NUM> and two capacitors <NUM> and <NUM>, and the number of the elements included in the fourth all-pass filter <NUM> is smaller than the number of elements included in the second all-pass filter <NUM>.

Thus, the phase shifter <NUM> shown in <FIG> can achieve a further size reduction than in the phase shifter <NUM> shown in <FIG> under conditions that the number of stages of all-pass filters included in the phase reference circuit <NUM> is the same and the number of stages of all-pass filters included in the phase-delay circuit <NUM> is the same.

In the phase shifter <NUM> shown in <FIG>, as long as the third all-pass filter <NUM> includes two inductors <NUM> and <NUM> and two capacitors <NUM> and <NUM>, disposition of each of the two inductors <NUM> and <NUM> and the two capacitors <NUM> and <NUM> is not limited to that shown in <FIG>.

In <FIG>, for example, the inductor <NUM> may be disposed at a location where the capacitor <NUM> is disposed, the inductor <NUM> may be disposed at a location where the capacitor <NUM> is disposed, the capacitor <NUM> may be disposed at a location where the inductor <NUM> is disposed, and the capacitor <NUM> may be disposed at a location where the inductor <NUM> is disposed.

In the phase shifter <NUM> shown in <FIG>, as long as the fourth all-pass filter <NUM> includes two inductors <NUM> and <NUM> and two capacitors <NUM> and <NUM>, disposition of each of the two inductors <NUM> and <NUM> and the two capacitors <NUM> and <NUM> is not limited to that shown in <FIG>.

A phased array antenna device including a phase shifter <NUM> according to any one of the first to fourth embodiments will be described.

<FIG> is a configuration diagram showing a phased array antenna device according to a fifth embodiment.

In <FIG>, a transmitter <NUM>-m (m = <NUM>,. , M) outputs a transmission signal to a phase shifter <NUM>-m. M is an integer greater than or equal to <NUM>.

The phase shifter <NUM>-m is the phase shifter <NUM> according to any one of the first to fourth embodiments.

The phase shifter <NUM>-m shifts the phase of the transmission signal outputted from the transmitter <NUM>-m, and outputs the phase-shifted transmission signal to an antenna element <NUM>-m.

The antenna element <NUM>-m radiates a radio wave based on the transmission signal whose phase has been shifted by the phase shifter <NUM>-m into space.

The phased array antenna device shown in <FIG> radiates radio waves based on transmission signals into space. However, this is merely an example, and the phased array antenna device may receive radio waves. When the antenna element <NUM>-m of the phased array antenna device receives a radio wave, the antenna element <NUM>-m outputs a reception signal of the radio wave to the phase shifter <NUM>-m.

The phase shifter <NUM>-m shifts the phase of the reception signal outputted from the antenna element <NUM>-m, and outputs the phase-shifted reception signal to a receiver which is not shown.

The present disclosure is suitable for a phase shifter.

The present disclosure is suitable for a phased array antenna device including a phase shifter.

Claim 1:
A phase shifter (<NUM>) comprising:
a first all-pass filter (<NUM>) including a plurality of elements;
a second all-pass filter (<NUM>) including a plurality of elements;
a first switching switch (<NUM>) to provide a signal to either one of the first all-pass filter and the second all-pass filter; and
a second switching switch (<NUM>) to select the signal having passed through the first all-pass filter or the signal having passed through the second all-pass filter, wherein
the first all-pass filter (<NUM>) includes a first inductor (<NUM>), a second inductor (<NUM>), a first capacitor (<NUM>), a second capacitor (<NUM>), and a third capacitor (<NUM>) as the plurality of elements,
the second all-pass filter (<NUM>) includes a third inductor (<NUM>), a fourth inductor (<NUM>), a fourth capacitor (<NUM>), a fifth capacitor (<NUM>), and a sixth capacitor (<NUM>) as the plurality of elements,
the first inductor is inserted in a first path (<NUM>) that connects the first switching switch to the second switching switch,
a first end of the first capacitor is connected to a first end of the first inductor,
a first end of the second capacitor is connected to a second end of the first inductor,
a first end of the second inductor is connected to a second end of each of the first capacitor and the second capacitor,
a first end of the third capacitor is connected to a second end of the second inductor, and a second end of the third capacitor is grounded,
the third inductor is inserted in a second path (<NUM>) that connects the first switching switch to the second switching switch,
a first end of the fourth capacitor is connected to a first end of the third inductor,
a first end of the fifth capacitor is connected to a second end of the third inductor,
a first end of the fourth inductor is connected to a second end of each of the fourth capacitor and the fifth capacitor,
a first end of the sixth capacitor is connected to a second end of the fourth inductor, and a second end of the sixth capacitor is grounded and
values of the plurality of capacitors and inductors included in the first and second all-pass filters are determined such that impedance matching is achieved in a desired frequency band.