Patent Description:
In many servers and mobile devices, a NAND storage system is widely used as the primary non-volatile storage device due to its high storage density and relatively low access latency. However, performance of a high density storage system, for example, a three-dimensional (3D) NAND storage system, is often restricted by the maximum amount of power (or peak current) that it can use. Currently, operations consuming high power (i.e., peak power operations) that are carried out by various memory dies of the NAND storage system can be staggered by a system controller. Only a limited number of peak power operations can be performed simultaneously. This approach can also result in increased system loading with unnecessary over-management. Communications between different memory dies can be established to coordinate the peak power operations. Currently, coordination between two memory dies can be arranged and peak power operations can be staggered between these two memory dies. However, only one peak power operation can be performed at one time. In addition, two or more contact pads are used on each memory die for communications between different memory dies on the same memory chip. Therefore, it is necessary to optimize the peak power management circuits and scheme to coordinate between multiple memory dies such that multiple peak power operations can be performed on a memory chip simultaneously. As such, the storage system's power or current budget can be fully utilized.

<CIT> discloses a non-volatile memory with multiple memory dies managing simultaneous operations to not exceed a system power capacity.

An aspect of the present disclosure is to provide effective peak power management for a memory chip according to claim <NUM>.

In some embodiments, the PPM system further includes a comparator with a first input terminal electrically connected to the PPM contact pads of the multiple memory dies and a second input terminal electrically connected to a reference voltage. In some embodiments, an output terminal of the comparator is connected to an inverter. In some embodiments, an RC filter is electrically connected to the PPM contact pads of the multiple memory dies and the first input terminal of the comparator. In some embodiments, the reference voltage is based on a maximum total current allowed on the memory chip.

In some embodiments, the pull-up driver includes a p-channel metal oxide semiconductor field effect transistor (MOSFET).

In some embodiments, the pull-down driver includes an n-channel metal oxide semiconductor field effect transistor (MOSFET).

In some embodiments, the PPM contact pad, the PPM resistor and the pull-down driver are electrically connected.

In some embodiments, the PPM contact pad, the PPM resistor and the pull-up driver are electrically connected.

In some embodiments, the PPM contact pads are electrically connected through die-to-die connections, each die-to-die connection including a metal interconnect.

In some embodiments, the PPM contact pads are electrically connected through flip-chip bonding, die-to-die bonding, or wire-bonding.

Another aspect of the present disclosure provides a method of peak power management (PPM) for a memory chip according to claim <NUM>.

In some embodiments, the method also includes, after switching on the pull-down driver, setting the pull-down current flowing through the pull-down driver on the selected memory die at a high current level, wherein the high current level correspond to a peak current of the peak power operation on the selected memory die.

In some embodiments, the method further includes, after performing the peak power operation, setting the pull-down current flowing through the pull-down driver on the selected memory die to a low current level, wherein the low current level correspond to a base current on the selected memory die.

In some embodiments, the method further includes switching off the pull-down driver on the selected memory die if the PPM enablement signal indicates that the total current of the memory chip is more than the maximum total current allowed for the memory chip.

In some embodiments, the method also includes, after switching off the pull-down driver, waiting for a delay time period.

In some embodiments, the method further includes, prior to verifying the PPM enablement signal, generating the PPM enablement signal by comparing a reference voltage with an electric potential of the PPM contact pads. The reference voltage is selected according to the maximum total current allowed for the memory chip.

In some embodiments, the method also includes regulating the electric potential of the PPM contact pads through the pull-down current of the pull-down driver, wherein the total current of the memory chip corresponds to a sum of the pull-down current flowing through each pull-down driver on the memory chip.

In some embodiments, the PPM enablement signal is set to <NUM> if the electric potential of the PPM contact pads is higher than the reference voltage; and the PPM enablement signal is set to <NUM> if the electric potential of the PPM contact pads is lower than the reference voltage.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

As used herein, the term "nominal/nominally" refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value.

<FIG> illustrates a storage system <NUM>, according to some embodiments of the present disclosure. The storage system <NUM> (also referred to as a NAND storage system or a solid state drive) can include a host controller <NUM> and one or more memory chips <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. Each semiconductor memory chip <NUM> (hereafter just "memory chip") can be a NAND chip (i.e., "flash," "NAND flash" or "NAND"). The solid state drive (SSD) <NUM> can communicate with a host computer <NUM> through the host controller <NUM>, where the host controller <NUM> can be connected to the one or more memory chips <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n, via one or more memory channels <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. In some embodiments, each memory chip <NUM> can be managed by the host controller <NUM> via a memory channel <NUM>.

The host computer <NUM> sends data to be stored at the NAND storage system or SSD <NUM> or retrieves data by reading the SSD <NUM>. The host controller <NUM> can handle I/O requests received from the host computer <NUM>, ensure data integrity and efficient storage, and manage the memory chip <NUM>. The memory channels <NUM> can provide data and control communication between the host controller <NUM> and each memory chip <NUM> via a data bus. The host controller <NUM> can select one of the memory chip <NUM> according to a chip enable signal.

<FIG> illustrates a top-down view of a NAND flash memory <NUM>, according to some embodiments of the present disclosure. The NAND flash memory <NUM> can be a memory die (or a die) or any portion of a memory die. In some embodiments, each memory chip <NUM> in <FIG> can include one or more memory dies, e.g., one or more NAND flash memories <NUM>. In some embodiments, each NAND flash memory <NUM> can include one or more memory planes <NUM>, each of which can include a plurality of memory blocks <NUM>. Identical and concurrent operations can take place at each memory plane <NUM>. The memory block <NUM>, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Shown in <FIG>, the exemplary NAND flash memory <NUM> includes four memory planes <NUM> and each memory plane <NUM> includes six memory blocks <NUM>. Each memory block <NUM> can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. The direction of bit lines and word lines are labeled as "BL" and "WL" in <FIG>. In this disclosure, the memory block <NUM> is also referred to as the "memory array" or "array. " The memory array is the core area on a memory die, performing storage functions.

The NAND flash memory <NUM> also includes a periphery region <NUM>, an area surrounding memory planes <NUM>. The periphery region <NUM> contains many digital, analog, and/or mixed-signal circuits to support functions of the memory array, for example, page buffers <NUM>, row decoders <NUM>, column decoders <NUM>, peripheral circuits <NUM> and sense amplifiers <NUM>. Peripheral circuits <NUM> include active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art.

It is noted that the layout of the electronic components in the SSD <NUM> and the NAND flash memory <NUM> in <FIG> are shown as examples. The SSD <NUM> and the NAND flash memory <NUM> can have other layout and can include additional components. For example, the NAND flash memory <NUM> can also have high-voltage charge pumps, I/O circuits, etc. The SSD <NUM> can also include firmware, data scrambler, etc..

<FIG> illustrates a peak power management system <NUM> of the memory chip <NUM>, according to some embodiments of the present disclosure. The peak power management (PPM) system <NUM> can be implemented in each memory chip <NUM> of the NAND storage system <NUM> in <FIG>, where each memory chip <NUM> can include a plurality of memory dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n, and each memory die can be similar to the NAND flash memory <NUM> discussed previously in reference with <FIG>. In some embodiments, each NAND flash memory <NUM> can include a peak power management (PPM) circuit <NUM> where each PPM circuit <NUM> can include a PPM contact pad <NUM> (also referred to as PPM pin). The PPM circuits <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n on different NAND flash memories <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n of the memory chip <NUM> can communicate with each other through the PPM pins <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. In some embodiments, the PPM pins between different NAND flash memories <NUM> can be electrically connected with each other through a plurality of die-to-die connections <NUM>. For example, the PPM pin <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be electrically connected with the PPM pin <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> through the die-to-die connection <NUM>-<NUM> and can be electrically connected with the PPM pin <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> through the die-to-die connection <NUM>-<NUM>. In some embodiments, the die-to-die connections <NUM> can be a metal wire formed through wire-bonding. In some embodiments, the die-to-die connections <NUM> can be metal wires or any suitable metal or conductive material formed through flip-chip bonding or any suitable die-to-die bonding. In some embodiments, the die-to-die connections <NUM> can be formed by through-silicon VIAs (e. g, through-array structures).

By using the die-to-die connections described above, communications between different memory dies (i.e., NAND flash memories <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n) can be established in the memory chip <NUM>. As such, the NAND storage system <NUM> can send operation commands to any number of memory dies at any time while the PPM circuits <NUM> can control the system's power consumption by selecting one or more memory dies.

<FIG> illustrates an exemplary PPM circuit <NUM> on the NAND flash memory <NUM>, according to some embodiments of the present disclosure. The PPM circuit <NUM> can include a pull-up driver <NUM>, where one terminal of the pull-up driver <NUM> is connected to a power source <NUM> with a voltage Vdd. In some embodiments, the pull-up driver <NUM> can be a metal-oxide-semiconductor-field-effect-transistor (MOSFET). In some embodiments, the pull-up driver <NUM> can be a p-channel MOSFET (i.e., pFET), where a source terminal of the pFET <NUM> can be connected to the power source <NUM> and a drain terminal of the pFET <NUM> can be connected to a PPM resistor <NUM> with a resistance Rppm.

In some embodiments, the PPM circuit <NUM> also includes a pull-down driver <NUM>. In some embodiments, the pull-down driver <NUM> can be a MOSFET. In some embodiments, the pull-down driver <NUM> can be an n-channel MOSFET (i.e., nFET). A source terminal of the nFET <NUM> can be grounded, and a drain terminal of the nFET <NUM> can be connected to the PPM resistor <NUM>.

In some embodiments, the PPM resistor <NUM> and the drain terminal of the nFET <NUM> are also electrically connected to the PPM contact pad <NUM> at a node <NUM>. Some or all the PPM contact pads (e.g., the PPM pins <NUM>) can be electrically connected through the die-to-die connections <NUM> (see <FIG>). Thus, the PPM contact pads <NUM> of the memory chip <NUM> can be held to an electrical potential Vppm at the node <NUM>.

In some embodiments, the PPM circuit <NUM> can also include a comparator <NUM>, with a first input terminal <NUM> at a reference voltage Vref and a second input terminal <NUM> connected to the node <NUM>. The comparator <NUM> can be an operational amplifier used for comparing an input voltage Vin at the second input terminal <NUM> with the reference voltage Vref at the first input terminal <NUM>, where an output voltage Vout at an output terminal <NUM> can indicate whether the input voltage Vin is above or below the reference voltage Vref. For example, the output voltage Vout can be a positive voltage when the input voltage Vin is larger than the reference voltage Vref. On the other hand, the output voltage Vout can be a negative voltage when the input voltage Vin is smaller than the reference voltage Vref.

In some embodiments, the PPM circuit <NUM> can further include an inverter <NUM> with an input terminal connected to the output terminal <NUM> of the comparator <NUM>. The inverter <NUM> can invert an input signal. For example, when the output voltage Vout of the comparator <NUM> is a positive voltage, a PPM enablement signal enPPM generated by the inverter <NUM> at an output terminal <NUM> can be zero, i.e., the PPM enablement signal enPPM=<NUM>. On the other hand, when the output voltage Vout of the comparator <NUM> is a negative voltage, the PPM enablement signal enPPM = <NUM>. In the other words, when the electrical potential Vppm at the node <NUM> is larger (or higher) than the reference voltage Vref (i.e., Vppm > Vref), the PPM enablement signal enPPM=<NUM>. When the electrical potential Vppm at the node <NUM> is smaller (or lower) than the reference voltage Vref (i.e., Vppm < Vref), the PPM enablement signal enPPM=<NUM>.

In some embodiments, there can be an optional RC filter <NUM> connected between the node <NUM> and the second input terminal <NUM> of the comparator <NUM>. The RC filter <NUM> can be used to filter out unwanted signals within a certain frequency range.

As discussed previously, the PPM pins on the same memory chip are electrically connected, i.e., all the PPM pins of the same PPM group have the same electrical potential Vppm. Therefore, each memory chip only needs one comparator <NUM> electrically connected at the node <NUM> to the PPM contact pads <NUM>. And the PPM enablement signal enPPM indicates the electrical potential Vppm for multiple the memory dies on the memory chip.

Referring to <FIG>, during operation, a first control signal <NUM> can be sent to a gate terminal <NUM> of the pFET <NUM> to switch the pFET <NUM> on or off. For example, if the first control signal <NUM> has a voltage less than a threshold voltage of the pFET <NUM>, the pFET <NUM> can be switched on, and a conductive path can be formed from the power source <NUM> to the PPM resistor <NUM>. The current flowing through the pull-up driver <NUM> and the PPM resistor <NUM> is also referred to as a pull-up current Ipull_up. If the first control signal <NUM> has a voltage higher than the threshold voltage of the pFET <NUM>, the pFET <NUM> can be switched off.

When a second control signal <NUM> is sent to a gate terminal <NUM> of the nFET <NUM>, the nFET <NUM> can be switched on or off. For example, if the second control signal <NUM> has a voltage higher than a threshold voltage of the nFET <NUM>, the nFET <NUM> can be switched on, and a conductive path can be formed from the node <NUM> to the ground. If the second control signal <NUM> has a voltage less than the threshold voltage of the nFET <NUM>, the nFET <NUM> can be switched off.

In some embodiments, the pull-down driver <NUM> can be operated as a current controller. In this example, when the pull-down driver <NUM> is switched on, the magnitude of the current flowing through the pull-down driver <NUM> from the node <NUM> to the ground (also referred to as pull-down current Ipull_dn) depends on the second control signal <NUM>. When the pull-down driver <NUM> is an nFET, as shown in <FIG>, the pull-down current Ipull_dn can be determined by the voltage level of the second control signal <NUM> and the trans-conductance of the nFET <NUM>. According to some embodiments of the present disclosure, a current profile Icc of a memory die (e.g., the NAND flash memory <NUM>-<NUM>) can correspond to the voltage level of the second control signal <NUM>, and thereby correspond to the pull-down current Ipull_dn. Therefore, the pull-down current Ipull_dn can function as a current mirror of the current profile Icc of the memory die.

In some embodiments, the pull-down current Ipull_dn can be proportional to a current level of the current profile Icc. The pull-down current Ipull_dn can be scaled down proportionally from the current profile Icc. For example, if the memory die is operating with <NUM> mA of current, the pull-down current Ipull_dn of the PPM circuit <NUM> can be <NUM>µA. Therefore, memory operations and corresponding current can be regulated for each memory die through the pull-down current Ipull_dn. Furthermore, through the die-to-die connections at the PPM contact pads, peak power operations throughout the entire memory chip can be coordinated between different memory dies.

<FIG> shows an exemplary current profile Icc of a memory die (e.g., the NAND flash memory <NUM> in <FIG>), according to some embodiments of the present disclosure. The current profile Icc can include two defined current levels, a peak current Icp and a base current Icb. The peak current Icp corresponds to a current level when the memory die is performing a peak power operation. The base current Icb corresponds to an average current level when the memory die is performing regular operations. When the current profile Icc of a memory die rises to the base current Icb, the memory die arrives at a break point <NUM>. Due to an increasing trend of current, a PPM scheme can be implemented to control total current consumed by the memory chip among the multiple memory dies.

Referring back to <FIG>, in some embodiments, the pull-down current Ipull_dn can also be defined using two current levels, i.e., a high current level IH (or a first current level) and a low current level IL (or a second current level). The high current level IH of the pull-down current Ipull_dn corresponds to the peak current Icp of a specific memory die. The low current level IL of the pull-down current Ipull_dn corresponds to the base current Icb of the specific memory die.

During operation, according to some embodiments of the present disclosure, only one pull-up driver <NUM> is switched on (i.e., enabled) in a memory chip and the other pull-up drivers <NUM> on different memory dies of the same memory chip can be switched off. As such, current only flows from the power source <NUM> through one PPM resistor <NUM> on each memory chip. Namely, the PPM circuits <NUM> on the same memory chip share a shared pull-up driver <NUM> and a shared PPM resistor <NUM>.

During operation, the pull-down driver <NUM> can be switched on or off depending on the status of the memory die, and can be independently controlled according to the PPM management scheme discussed below. For example, the NAND flash memory <NUM>-<NUM> (in <FIG>) can perform a peak power operation using the peak current Icp when the pull-down driver <NUM> of the PPM circuit <NUM>-<NUM> is switched on, where a conductive path can be formed through the pull-down driver <NUM> to the ground with the pull-down current Ipull_dn at the high current level IH. The NAND flash memories <NUM>-<NUM> is prohibited from performing any peak power operation when the pull-down driver <NUM> of the PPM circuit <NUM>-<NUM> is switched off, where no current can flow through the pull-down driver <NUM> on the NAND flash memory <NUM>-<NUM>.

The electric potential Vppm of the node <NUM> (or the PPM pins <NUM>) depends on the number of pull-down drivers <NUM> that are switched on and depends on current levels of the pull-down current Ipull_dn going through the pull-down drivers <NUM>. A peak power operation can be performed on a memory die when the pull-down driver <NUM> is switched on and the pull-down current Ipull_dn is at the high current level IH. By monitoring the electric potential Vppm, a total current Itotal used by the memory chip can be controlled and the number of peak power operations performed in a memory chip having multiple memory dies can thereby be regulated.

<FIG> shows an equivalent PPM circuit <NUM> on a memory chip of multiple memory dies, according to some embodiments of the present disclosure. The equivalent PPM circuit <NUM> represents the PPM circuits <NUM> across different memory dies, as shown in <FIG> and <FIG>. Since only the pull-up driver <NUM> and the pull-down drivers <NUM> that are switched on can form conductive paths, <FIG> omits those pull-up drivers <NUM> and pull-down drivers <NUM> that are switched off. As discussed previously, the node <NUM> is electrically connected to the PPM pin <NUM> on the memory die (see <FIG>), and all the PPM pins <NUM> in the same memory chip are electrically connected between different memory dies (see <FIG>). Therefore, the node <NUM> can be held at the same electrical potential Vppm between different memory dies on the same memory chip, and is illustrated as one intersection point to the PPM resistor <NUM> in <FIG>.

In some embodiments, only one pull-up driver <NUM> can be switched on for peak power management across multiple memory dies on the same memory chip. In some embodiments, the pull-down driver <NUM> can be switched on in the PPM circuit corresponding to the memory die performing the peak power operation, i.e., using the peak current Icp.

In one example, there can be m number of pull-down drivers <NUM> that are switched on in a memory chip, where m can be any whole number. The pull-down drivers <NUM> are from the PPM circuits <NUM> of the memory dies, e.g., NAND flash memory <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-m in <FIG>. The pull-down drivers <NUM> are connected in parallel with each other. In this configuration, the pull-up current Ipull_up flowing through the pull-up driver <NUM> that is switched on, is the sum of the pull-down current Ipull-dn, and can be expressed as: <MAT> where Ipull_dn-<NUM>, Ipull_dn-<NUM>,. , Ipull_dn-m are the pull-down current flowing through each of the pull-down drivers <NUM> that are switched on. The pull-down current Ipull_dn can be set at either the high level current IH or the low level current IL, depending on the operations performed on the specific memory die.

Since the pull-up driver <NUM> in <FIG> is a shared pull-up driver of the PPM circuits on the memory chip, the pull-up current Ipull_up can be a total current of the PPM circuits on the same memory chip. In some embodiments, the pull-up current Ipull_up can correspond to a total current Itotal of the memory chip. The pull-up current Ipull_up (in Equation <NUM>) and the total current Itotal of the memory chip can follow the same scaling ratio as the pull-down current Ipull_dn (e.g., the high and low current level IH and IL) of the PPM circuit <NUM> and the current profile Icc (e.g., the peak and base current Icp and Icb) of the memory chip. For example, if the total current Itotal of a memory chip is <NUM> mA, the pull-up current Ipull_up of the PPM circuits <NUM> can be <NUM>µA.

The electric potential Vppm of the node <NUM> can be expressed as: <MAT> wherein Rppm is the resistance of the PPM resistor <NUM>, and Vdd is the voltage of the power source <NUM>.

As discussed previously, the reference voltage Vref for the comparator <NUM> (in <FIG>) can be selected such that the PPM enablement signal enPPM can be set at enPPM = <NUM> when the electric potential Vppm is higher than the reference voltage Vref. In this example, the reference voltage Vref can be defined as: <MAT> where Ipull_up_max is a maximum pull-up current flowing through the pull-up driver <NUM> in the PPM circuit <NUM>, corresponding to a maximum total current Itotal_max allowed on a memory chip. In some embodiments, the maximum pull-up current Ipull_up_max of the PPM circuit <NUM> (in <FIG>) and the maximum total current Itotal_max of the memory chip <NUM> follows the same scaling ratio as the pull-down current Ipull_dn (e.g., the high and low current level IH and IL) of the PPM circuit <NUM> and the current profile Icc (e.g., the peak and base current Icp and Icb) of the memory chip. For example, if the maximum total current Itotal_max allowed on a memory chip is <NUM> mA, the maximum pull-up current Ipull_up_max of the PPM circuit <NUM> can be <NUM>µA.

In this example, when the pull-up current Ipull_up is less than the maximum pull-up current Ipull_up_max, based on the Equations (<NUM>) and (<NUM>), the electric potential Vppm is higher than the reference voltage Vref. The PPM enablement signal enPPM can thereby be set at enPPM = <NUM>. On the other hand, when the pull-up current Ipull_up is more than the maximum pull-up current Ipull_up_max, the electric potential Vppm is lower than the reference voltage Vref. And the PPM enablement signal enPPM can be set at enPPM = <NUM>. As such, by regulating the pull-down driver <NUM> of the PPM circuit <NUM>, the pull-down current Ipull_dn on each memory die can be adjusted. The pull-up current Ipull_up can be regulated accordingly. By comparing the pull-up current Ipull_up that corresponds to the total current Itotal of the memory chip, with the maximum pull-up current Ipull_up_max that is predetermined according to the maximum total current Itotal_max allowed on the memory chip, the PPM enablement signal enPPM can be set at <NUM> or <NUM>. In the other words, the reference voltage Vref can be programmed to correspond to the maximum total current Itotal_max allowed on the memory chip. And the PPM enablement signal enPPM can be used to indicate whether there are still current or power budget to run additional peak power operations. For example, if the PPM enablement signal enPPM =<NUM>, the maximum pull-up current Ipull_up_max of the PPM circuit <NUM> has not been reached, indicating that the maximum total current Itotal_max of the memory chip <NUM> has not been reached. The memory chip <NUM> can provide the peak current Icp to at least one of the memory dies, i.e., having enough power (or current) to provide at least one additional memory die to perform peak power operation. On the contrary, when the PPM enablement signal enPPM = <NUM>, the maximum pull-up current Ipull_up_max of the PPM circuit <NUM> has been reached, indicating that the maximum total current Itotal_max of the memory chip <NUM> has been reached. The memory chip <NUM> has reached its power (or current) limit and cannot provide additional peak current Icp to any of the memory dies to perform any additional peak power operation.

<FIG> illustrates a peak power check routine <NUM> associated with the peak power management system <NUM> in <FIG> and the PPM circuit <NUM> in <FIG>, according to some embodiments of the present disclosure. The PPM scheme described with reference with <FIG> is used to determine the reference voltage Vref and generate the PPM enablement signal enPPM to indicate whether the NAND storage system <NUM> is operating at a current level below the maximum total current Itotal_max allowed on the memory chip <NUM>. It should be understood that the peak power check (PPC) routine <NUM> are not exhaustive and that other operation steps can be performed as well before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of the PPC routine <NUM> can be omitted or other operation steps can be included, which are not described here for simplicity. In some embodiments, operation steps of the PPC routine <NUM> can be performed in a different order and/or vary.

The PPC routine <NUM> provides an exemplary method of managing peak power usage for a memory chip with one or more memory dies, where each memory die includes at least one PPM circuit. The example below is shown for a memory chip, e.g., the memory chip <NUM> in <FIG>, where each memory die includes the PPM circuit <NUM> for checking and regulating peak power operations performed by the memory dies. However, the method can be extended to a memory chip where each memory die includes two or more PPM circuits.

The PPC routine <NUM> can be implemented before a memory die starts to perform a peak power operation such that the total power (or current) consumed by a memory chip can be regulated and controlled to below a predetermined value, e.g., the maximum total current Itotal_max.

The PPC routine <NUM> starts at operation step S605, when a NAND storage system (e.g., the NAND storage system <NUM> in <FIG>) determines that one of the memory dies (e.g., the NAND flash memory <NUM>-<NUM>) on the memory chip <NUM> arrives at a break point (e.g., the break point <NUM> shown in <FIG>). Compared with the current level prior to the break point <NUM>, the increased current consumption on the memory die indicates that the memory die may perform a peak power operation subsequently.

Prior to the break point <NUM>, the PPM circuit <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be at a reset state. At the reset state, the pull-down driver <NUM>-<NUM> is switched off. At the operation step S605, one of the pull-up drivers <NUM> of the PPM circuits <NUM> can be switched on as a shared pull-up driver among the multiple memory dies on the memory chip.

At operation step S610, the pull-down driver <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be switched on.

At operation step S615, the pull-down current Ipull_dn_1 flowing through the pull-down driver <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be set to the high current level IH, which corresponds to the peak current Icp needed to perform the peak power operation on the NAND flash memory <NUM>-<NUM>.

At operation step S620, the PPM enablement signal enPPM is verified. If the PPM enablement signal enPPM=<NUM>, the pull-up current Ipull_up flowing through the shared pull-up driver is less than the maximum pull-up current Ipull_up_max, indicating that the NAND flash memory <NUM>-<NUM> can perform the peak power operation with the peak current Icp without causing a total current Itotal of the memory chip exceeding the maximum total current Itotal_max.

At operation step S625, the NAND flash memory <NUM>-<NUM> performs the peak power operation running at the peak current Icp. In some embodiments, the NAND flash memory <NUM>-<NUM> can also perform any operation running at a current level less than the peak current Icp.

If, at operation step S620, the PPM enablement signal enPPM is not zero (e.g., enPPM=<NUM>), the PPC routine <NUM> continues to operation step S630, where the pull-down driver <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be switched off. At operation step S635, the PPC routine <NUM> is paused and waits for a delay time period tdl. In some embodiment, the delay time period tdl is random. In some embodiments, the delay time period tdl can be any suitable time period in a range between <NUM> to <NUM>. In some embodiments, the delay time period tdl can be different for each memory die. After the delay time period tdl, the PPC routine <NUM> returns to operation step S620 via loop L1 and the PPM enablement signal enPPM is checked again.

The delay time period tdl is introduced in event that multiple memory dies enter the PPC routine <NUM> at the same time and multiple pull-down drivers are switched on and set at the high current level IH at the same time. If there is no current/power budget available to run the peak power operations for these memory dies at the same time, the PPM enablement signal enPPM indicates to the multiple memory dies at operation step S620. Then the corresponding pull-down drivers can be switched off on the multiple memory dies simultaneously at operations step S630. By introducing the delay time period tdl, the multiple memory dies can return to operation step S620 one at a time, i.e., the requests for peak power operations from multiple memory dies can be de-synchronized. As such, the multiple memory dies can perform the peak power operation sequentially without exceeding the maximum total current Itotal_max allowed on the memory chip.

At operation step S640, after completing the peak power operation, the pull-down current Ipull_dn_1 flowing through the pull-down driver <NUM>-<NUM> can be set to the low current level IL. As such, the NAND flash memory <NUM>-<NUM> can continue operations with current less than the peak current Icp.

In some embodiments, the PPC routine <NUM> can return back via loop L2 to operation step S605, for example, when another break point is detected after the completion of the present peak power operation.

At operation step S645, the pull-down driver <NUM>-<NUM> of the PPM circuit <NUM>-<NUM> on the NAND flash memory <NUM>-<NUM> can be disabled (i.e., switched off), for example, when the current level of the NAND flash memory <NUM>-<NUM> falls below the base current Icb. The PPC routine <NUM> is finished and can be restarted again if the NAND storage system <NUM> determines that one of the memory dies on the memory chip enters one of the break points.

When the pull-down current Ipull_dn of a specific memory die is set to the high current level IH, the current/power budget can be temporary reserved for this specific memory die. Any other memory die on the same memory chip that runs the PPC routine <NUM> can be queued in the loop of operation steps S620, S630 and S635 unless the total current Itotal is less than the maximum total current Itotal_max or until the current/power budget is available on the memory chip, which can be verified at the operation step S620.

Through defining two current levels (e.g., the peak current Icp and the base current Icb) on the current profile Icc of a memory die, and through adjusting the pull-down current Ipull_dn of the pull-down driver <NUM> in the PPM circuit <NUM> on the memory die accordingly (e.g., switching on/off, setting to the high current level IH and the low current level IL), the electric potential Vppm of the PPM contact pads <NUM> across multiple memory dies on the memory chip can be regulated because the PPM contact pads <NUM> on different memory dies can be electrically connected through the die-to-die connections <NUM> and can be held at the same electric potential Vppm. By comparing the electric potential Vppm with the reference voltage Vref predetermined according to the maximum total current Itotal_max allowed on the memory chip, peak power operations performed by each memory die on the memory chip can be managed using the PPC routine <NUM>. As a result, the total current Itotal of the memory chip with multiple memory dies can be controlled.

However, the PPM circuit and PPM scheme are not limited to the examples shown in <FIG>. Variations of the PPM circuit <NUM> and the PPC routine <NUM> can provide similar peak power manage for a memory chip with multiple memory dies.

<FIG> illustrates another exemplary PPM circuit <NUM>' on the NAND flash memory <NUM>, according to some embodiments of the present disclosure. The PPM circuit <NUM>' is similar to the PPM circuit <NUM>. The main difference is that the PPM resistor <NUM> can be connected between the node <NUM> and the pull-down driver <NUM>. In this example, during operation, only one pull-down driver <NUM> is switched on among the multiple memory dies on the same memory chip, while the pull-up driver <NUM> can be regulated according to the current profile Icc on the memory die. Here, the pull-up current Ipull_up of the PPM circuit <NUM>' can be defined with two current levels, e.g., the high current level IH and the low current level IL, corresponding the peak current Icp and the base current Icb of the memory die. In this example, during operation, when there can be m number of pull-up drivers <NUM> that are switched on in a memory chip, the pull-down current Ipull_dn flowing through the pull-down driver <NUM> that is switched on, is the sum of the pull-up current Ipull-up, and can be expressed as: <MAT> The electric potential Vppm of the node <NUM> can be expressed as: <MAT> and the reference voltage Vref can be defined as: <MAT> where Ipull_dn_max is a maximum pull-down current flowing through the pull-down driver <NUM>, corresponding to the maximum total current Itotal_max allowed on a memory chip. Thus, when the pull-down current Ipull_dn is larger than the maximum pull-down current Ipull_dn_max, the electric potential Vppm is higher than the reference voltage Vref, and the output voltage Vout at the comparator <NUM> can be positive. In the PPM circuit <NUM>', the output voltage Vout can be directly sent to the PPM enablement signal enPPM without an inverter. According, the PPM enablement signal enPPM=<NUM> when Ipull_dn > Ipull_dn_max. Conversely, enPPM=<NUM> if Ipull_dn < Ipull_dn_max. In this example, PPC routing <NUM> can be modified by switching the pull-down driver / pull-down current to pull-up driver / pull-up current.

The devices and configurations used for the exemplary PPM circuit <NUM> in <FIG> and the PPM circuit <NUM>' in <FIG> are only for illustration purpose and for simplicity to demonstrate the functionality of the PPM circuit and PPM scheme. In some embodiments, the pull-down driver <NUM> in <FIG> can be replaced by a suitable current source to set the current levels of the pull-down current Ipull_dn.

Dynamic peak power management of a memory chip discussed above can also be implemented to closely follow the current profile Icc of a memory die. For example, based on the current profile Icc in <FIG>, the PPM scheme can be separated into multiple phases, where each phase P; can include a peak current Ii (i=<NUM>, <NUM>,. In this example, when the pull-down driver <NUM> is switched on, the pull-down current Ipull_dn can be adjusted to be proportional to the peak current Ii of each phase P;. The break point <NUM> can be inserted at the beginning of phase P<NUM> and each phase P; if the peak current Ii is larger than the peak current Ii-<NUM> of the previous phase Pi-<NUM>. For example, break points <NUM> can be inserted at the beginning of phase P<NUM>, P<NUM> and P<NUM> in <FIG>.

Using similar PPC routine <NUM> in <FIG>, when a memory die arrives at a break point <NUM>, for example, at the beginning of phase P<NUM>, operation step S605 can be started. The pull-down driver <NUM> on the memory die can be enabled at operation step S610, and the pull-down current Ipull_dn flowing through the pull-down driver <NUM> can be set at a current level reflecting the peak current I<NUM> in phase P<NUM>. At operation step S620, the PPM enablement signal enPPM is checked. If the PPM enablement signal enPPM=<NUM>, the peak power operation corresponding to the peak current I<NUM> can be executed by the memory die. Otherwise, the pull-down driver <NUM> on the memory die can be switched off and the memory die can wait for a delay time period at operation step S635 before checking the PPM enablement signal enPPM again at operation step S620.

If the peak current Ii is smaller than the peak current Ii-<NUM> of the previous phase Pi-<NUM>, no break point is needed at the beginning of the phase Pi. For example, no break point is inserted in the current profile Icc at the beginning of phase P<NUM>, P<NUM> and P<NUM> in the example shown in <FIG>.

When the peak power operation is completed at operation step S640, the pull-down current Ipull_dn can be adjusted to a lower level to be proportional to the next peak current of the memory die. For example, when the peak power operation is completed for phase P<NUM>, the pull-down current Ipull_dn of the memory die can be adjusted to be proportional to the peak current I<NUM> and continues to execute the operations in phase P<NUM>.

At the beginning of phase P<NUM>, another break point <NUM> is detected. The PPC routine <NUM> returns back to operation step S605 and the PPM enablement signal enPPM is checked again at operation step S620.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance.

The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

Claim 1:
A peak power management (PPM) system (<NUM>) for a memory chip (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n) with multiple memory dies (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n), comprising:
a PPM circuit (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n, <NUM>', <NUM>) on each of the multiple memory dies (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n), each PPM circuit (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n, <NUM>', <NUM>) comprising:
a pull-up driver (<NUM>) electrically connected to a power source (<NUM>) and a first end of a PPM resistor (<NUM>);
a pull-down driver (<NUM>, <NUM>-<NUM>) electrically connected to a second end of the PPM resistor (<NUM>); and
a PPM contact pad (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n) connected to the second end of the PPM resistor (<NUM>),
wherein PPM contact pads (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n) of the multiple memory dies (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n) are electrically connected with each other; and
wherein the PPM system is configured to manage a peak power operation based on an electric potential of the PPM contact pads (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n), wherein the electric potential of the PPM contact pads (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n) is adjusted by a pull-down current flowing through the pull-down driver (<NUM>, <NUM>-<NUM>) in the PPM circuit (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, ..., <NUM>-n, <NUM>', <NUM>), wherein the pull-down current comprises a high current level, the high current level corresponding to a peak current of the peak power operation.