Patent Description:
The present invention is set out in the appended claims <NUM>-<NUM>.

In some examples not forming part of the claimed invention, the marking plate is formed of at least one of a ceramic material, a metal material, a metal alloy material In an embodiment, the marking plate is formed of a semiconductor material.

In an embodiment, the IC package includes a plurality of bond wires that are configured to interconnect the one or more IC chips to the package substrate. The plastic structure is configured to encapsulate the plurality of bond wires.

It is noted that in an embodiment, the IC package is one of a ball grid array (BGA) package, a quad-flat package (QFP), a quad flat non-lead (QFN) package, a land grid array (LGA) package, and a pin grid array (PGA).

In some embodiments, neighboring IC chips are staggered and multiple IC chips in the IC package are stacked in a zig-zag pattern.

According to an aspect of the disclosure, the marking plate has a better anti-laser penetration property than the plastic structure. In some embodiments, the marking plate has a higher rigidity than the plastic structure. According to another aspect of the disclosure, the marking plate has a better thermal conductivity than the plastic structure. Thus, the marking plate can transfer heat generated by the IC chips during operation to the outer surface of the IC package.

It is noted that, in accordance with the standard practice in the industry, various features are not drawn to dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Aspects of the disclosure provide an integrated circuit(IC) package with a marking plate embedded in a plastic structure. The marking plate has a higher rigidity than the molding material of the plastic structure, and has a better anti-laser penetration property than the molding material. Because of the higher rigidity, the IC package distortion due to high temperature processing, such as a soldering process, can be reduced. Further, because of the better anti-laser penetration property, a relatively thinner marking plate is allowed. Thus, the IC package can have a relatively small thickness or can encapsulate more IC chips without increasing the package thickness.

<FIG> shows a cross-sectional view of an integrated circuit (IC) package <NUM> in accordance with some embodiments. The IC package <NUM> includes a package substrate <NUM>, a plurality of IC chips <NUM> (e.g., including IC chips 120A-<NUM> in <FIG>) and a marking plate <NUM>. The IC chips <NUM> are stacked on the package substrate <NUM> and are encapsulated in a plastic structure <NUM>. The marking plate <NUM> is stacked on the IC chips <NUM> and is embedded in the plastic structure <NUM>. A surface <NUM> of the marking plate <NUM> is a portion of the outer surface of the IC package <NUM> and the surface <NUM> can be laser-marked for identification and traceability.

The package substrate <NUM> is made, for example, of suitable insulating material (also referred to as dielectric material), such as an epoxy based laminate substrate, a resin-based Bismaleimide-Triazine (BT) substrate, and the like. The package substrate <NUM> is relatively rigid to provide mechanical support to the IC chips <NUM>. The package substrate <NUM> has a first surface <NUM> and a second surface <NUM>. The IC chips <NUM> are disposed on a surface, such as the second surface <NUM> of the package substrate <NUM>.

The package substrate <NUM> also provides electrical support for the IC chips <NUM>. In some examples, the package substrate <NUM> includes multiple layers of metal traces, such as copper wires, and the like with the insulating material in between. The metal traces on the different layers can be connected by vias. Further, contact structures are formed on both the first surface <NUM> and the second surface <NUM> to electrically interface the IC chips <NUM> in the IC package <NUM> to components out of the IC package <NUM>.

The IC chips <NUM> can be any suitable chips. The IC chips <NUM> include various circuits for providing storage, computing and/or processing functionalities.

The package substrate <NUM> provides interconnects from the inputs/outputs of the IC chips <NUM> to the contact structures that are formed on the first surface <NUM> and the second surface <NUM> of the IC package <NUM>. In an example, the IC chips <NUM> includes input/output (I/O) pads (not shown) that are electrically connected to internal circuits that are formed on the IC chips <NUM>. Bond wires <NUM> (e.g. aluminum wires, copper wires, silver wires, gold wires and the like) are bonded to connect the I/O pads on the IC chips <NUM> and the contact structures on the second surface <NUM> of the package substrate <NUM> to form electrical connections between the IC chips <NUM> and the package substrate <NUM>. In <FIG>, neighboring IC chips in the IC chips <NUM> are staggered to provide bonding space to allow the bond wires <NUM> to be bonded on the I/O pads, and avoid shorting circuit. Further, the IC chips <NUM> are stacked in a zig-zag pattern to provide space for bond wires <NUM>.

The package substrate <NUM> also includes suitable contact structures <NUM> on the first surface <NUM>. In <FIG>, the IC package <NUM> is a ball grid array (BGA) package, and each of the contact structures <NUM> includes a solder pad and a solder ball that is deposited on the solder pad. It is noted that, in some examples, the solder balls are not formed on the package substrate <NUM>. In an embodiment, the IC package is a quad-flat package (QFP). In another embodiment, the IC package <NUM> is a quad flat non-lead (QFN) package. In another embodiment, the IC package <NUM> is a land grid array (LGA) package, and each of the contact structures includes a solder pad. In another embodiment, the IC package <NUM> is a pin grid array (PGA) package, and each of the contact structures <NUM> includes a pin.

In <FIG>, the package substrate <NUM>, the plastic structure <NUM> and the marking plate <NUM> form the outer portion of the IC package <NUM> that encapsulates the IC chips <NUM> inside. Specifically, the marking plate <NUM> is stacked on the IC chips <NUM>. Then, the second surface <NUM> of the package substrate <NUM>, the IC chips <NUM> and the bond wires <NUM> are encapsulated by the plastic structure <NUM>. The marking plate <NUM> is embedded in the plastic structure <NUM> with the surface <NUM> exposed for laser-marking.

The plastic structure <NUM> is formed of any suitable material, such as silica fillers, resin, and the like. In an example, the plastic structure <NUM> includes epoxy molding compound (EMC). The plastic structure <NUM> and IC chips <NUM> have different coefficient thermal expansions (CTE) (also referred to as CTE mismatch), and have different thermal conductivity.

According to an aspect of the disclosure, the marking plate <NUM> is formed of a material that has a higher rigidity than the plastic structure <NUM>. In <FIG>, the IC package <NUM> includes the marking plate <NUM>, the IC chips <NUM> and the package substrate <NUM> from the upper surface (e.g., the surface <NUM> of the marking plate <NUM>) to the bottom surface (e.g., the first surface <NUM> of the package substrate <NUM>). The marking plate <NUM>, the IC chips and the package substrate <NUM> have relatively high rigidity than the plastic structure <NUM>. In a conventional example, the upper portion of a related IC package is also made of EMC, and is used for laser-marking. Compared to the conventional example, the IC package <NUM> has lower volume percentage of EMC, and thus has higher package rigidity than the conventional example.

The marking plate <NUM> has about the same CTE (e.g., matching CTE) as the IC chips <NUM>. Thus, the IC package <NUM> has a reduced warpage during thermal processing. For example, CTE mismatch can cause package warpage during thermal processing after molding. For example, the IC packages can be mounted on a printed circuit board (PCB) using a surface mount process. The surface mount process includes a solder reflow step that raises a processing temperature, for example, above <NUM>. When the processing temperature returns to for example room temperature, the IC package <NUM> has reduced warpage compared to the conventional example due to the matching CTE from the upper surface to the bottom surface.

The marking plate <NUM> has a better anti-laser penetration property than the plastic structure <NUM> to prevent laser penetration. A laser penetration depth in the marking plate <NUM> is shorter than a laser penetration depth in the plastic structure <NUM>. Thus, the IC package <NUM> has a reduced thickness or can include more IC chips <NUM>. For example, in the conventional example, because the laser-marking is marked on the EMC, to prevent laser damages to the circuits on the IC chips <NUM> and to the bond wires <NUM>, the top portion of the plastic package above the IC chips needs to be relatively thick, such as about <NUM>. The marking plate <NUM> has a better anti-laser penetration property than the plastic structure <NUM>, and a thickness of <NUM> is enough to prevent laser damage to the circuits on the IC chips <NUM> and the bond wires <NUM>.

According to another aspect of the disclosure, the marking plate <NUM> has a better thermal conductivity than the plastic structure <NUM>. For example, the marking plate <NUM> can transfer heat generated by the IC chips during operation to the outer surface of the IC package <NUM> faster than the plastic structure <NUM>. The fast heat transfer can provide proper thermal environment for the IC chips <NUM>, reduce chip temperature during operation, and allow the IC chips <NUM> to perform properly during operation.

In an embodiment, the marking plate <NUM> is formed of silicon, such as pure silicon, and is then referred to as a mirror die (due to shining surface <NUM>) in an example. Thus, the marking plate <NUM> has about the same CTE (e.g., matching CTE) as the IC chips <NUM>, and has a higher rigidity and better anti-laser penetration property than the plastic structure <NUM>.

It is noted that in examples not forming part of the claimed invention, other suitable material, such as ceramic, metal, metal alloy can be used to form the marking plate <NUM>. In an example, the marking plate <NUM> is formed of ceramic material. In another example, the marking plate <NUM> is formed of metal alloy. The marking plate <NUM> is suitably processed such that the bottom surface of the marking plate <NUM> that faces the IC chips <NUM> is electrically non-conductive to avoid shorting to the bond wires <NUM>.

The marking plate <NUM> is configured to have a stair shape at the cross-sectional view. Thus, the surface <NUM> of the marking plate <NUM> that faces the IC chip <NUM> is smaller than the surface <NUM> of the marking plate <NUM>. The smaller surface <NUM> provides more space for wire-bonding on the IC chip <NUM>. The larger surface <NUM> allows more area for laser markings.

It is noted that while the IC chips <NUM> are shown with the same chip size in <FIG>, the IC chips <NUM> can have different chip sizes in other examples.

It is also noted that when stacking IC chips <NUM> and the marking plate <NUM>, intermediate layers <NUM>, such as adhesive films, polymer films, spacer films, and the like can be used between the IC chips <NUM> and the marking plate <NUM>.

<FIG> shows a cross-sectional view of another IC package <NUM> in accordance with some examples, not being part of the invention. Similar to the IC package <NUM>, the IC package <NUM> includes a package substrate <NUM>, a plurality of IC chips <NUM> and a marking plate <NUM>. The IC chips <NUM> are stacked on the package substrate <NUM> and are encapsulated in a plastic structure <NUM>. The marking plate <NUM> is stacked on the IC chips <NUM> and is embedded in the plastic structure <NUM>. A surface <NUM> of the marking plate <NUM> is a portion of the outer surface of the IC package <NUM> and the surface <NUM> can be laser-marked for identification and traceability.

The IC package <NUM> utilizes certain components that are identical, equivalent or similar to those used in the IC package <NUM>. For example, the IC chips <NUM> are equivalent or similar to the IC chips <NUM>. The bond wires <NUM> are equivalent or similar to the bond wires <NUM>. The plastic structure <NUM> is equivalent or similar to the plastic structure <NUM>. The package substrate <NUM> is equivalent or similar to the package substrate <NUM>. The description of these components has been provided above and will be omitted here for clarity purposes.

In the <FIG> example, the marking plate <NUM> is configured to have a rectangular cuboid shape, and have a rectangular shape in the cross-sectional view, thus the surface <NUM> that faces the IC chip <NUM> is of the same surface area as the surface <NUM> that is a portion of the outer surface of the IC package <NUM>.

Further, in the <FIG> example, the IC package <NUM> can be a LGA package without soldering balls. The package substrate <NUM> includes flat contact structures on the first surface <NUM>.

<FIG> shows a flow chart outlining a process <NUM> for fabrication according some embodiments of the disclosure. In an embodiment, the process <NUM> is used to fabricate the IC package <NUM>.

<FIG> show various cross sectional views of the IC package <NUM> at intermediate stages during the process <NUM> in accordance with some embodiments. It is noted that suitable modifications can be made on the <FIG> for other IC package, such as the IC package <NUM>.

Referring to <FIG> and <FIG>, the process starts at S301, and proceeds to S310.

At S310, IC chips are stacked on a package substrate. As shown in <FIG>, the plurality of IC chips <NUM> are stacked on the package substrate <NUM>. The IC chips <NUM> are stacked in a staggered manner to provide more space for wire bonding. In an embodiment, neighboring IC chips in the IC chips <NUM> area staggered to provide space for wire bonding. The IC chips <NUM> can be stacked in a zig-zag pattern. Then bond wires <NUM> are bonded to interconnect the IC chips <NUM> to the package substrate <NUM>. <FIG>, adhesive films <NUM> are used between the neighboring IC chips <NUM>.

At S320, an initial marking plate is stacked on the IC chips. As shown in <FIG>, an initial marking plate <NUM> is stacked on the IC chips <NUM>. It is noted that the initial marking plate <NUM> is thicker than the marking plate <NUM> in the IC package <NUM>. In <FIG>, an adhesive film <NUM> is used between the initial marking plate <NUM> and the top of IC chips <NUM>.

At S330, the initial marking plate and the IC chips are encapsulated in an initial plastic structure. As shown in <FIG>, plastic material, such as EMC and the like is molded to form the initial plastic structure <NUM> that encapsulates the IC chips <NUM> and the initial marking plate <NUM>.

At S340, the initial plastic structure is grinded. As shown in <FIG>, the initial plastic structure <NUM> is grinded to expose the initial marking plate <NUM>, and further grinded to form the plastic structure <NUM> and the marking plate <NUM>. <FIG> shows the IC package after the grinding process.

At S350, the IC package is laser marked on the marking plate. For example, laser marking can be performed on the marking plate <NUM> for identification and traceability.

At S360, further process(es) can be performed on the IC package. In an example, solder balls, such as the solder balls <NUM> are attached to the package substrate <NUM>. In an example, the IC packaging is performed in the form of a matrix array of packages. The matrix array of packages can be diced to form individual IC packages. The individual IC packages can then be tested and sorted. Then, the process proceeds to S399 and terminates.

Claim 1:
An integrated circuit, IC, (<NUM>) package, comprising:
a package substrate (<NUM>);
one or more IC chips (<NUM>) that are interconnected with the package substrate (<NUM>);
a marking plate (<NUM>), suitable for being laser marked or being laser marked, having a first major surface and a second major surface, the marking plate (<NUM>) being stacked on the one or more IC chips (<NUM>) with the first major surface facing the one or more IC chips and the marking plate (<NUM>) has a stair structure;
a plastic structure (<NUM>) configured to encapsulate the one or more IC chips (<NUM>) and the marking plate (<NUM>) with the second major surface of the marking plate (<NUM>) being a portion of an outer surface of the IC package (<NUM>), wherein
a laser penetration depth in the marking plate is shorter than a laser penetration depth in the plastic structure (<NUM>), and wherein
the first major surface of the marking plate is smaller than the second major surface, characterized by the marking plate (<NUM>) having an equal coefficient of thermal expansion, CTE, as the one or more IC chips (<NUM>).