Patent Description:
Chip scale package (CSPs) semiconductor devices are becoming increasingly important for applications which require a small footprint. CSPs are commonly used, for instance, in mobile communications devices such as mobile telephones and portable electronic devices. When a CSP incorporates a power semiconductor device, such as a transistor or diode, they require high performance thermal capacity and heat dissipation because they are required to drain large currents to ground or other rails, to protect devices connected thereto from being damaged. On the other hand, the power devices face challenges to increase structural compactness, which requires on the one hand, to have a very small footprint and package height, and, on the other hand to be protected by a package material. The package material is necessary to protect the device from environmental factors such as moisture. In addition the package material prevents solder pastes used to mount the device to a printed circuit board from contacting and potentially short circuiting the body of the semiconductor die. Such arrangements typically have mould material on six sides of the device and are known as six-sided protected CSP devices.

<FIG> is a cross-sectional view of a conventional six sided protected CSP device <NUM>. The semiconductor device <NUM> has a top major surface <NUM> and an opposing bottom major surface <NUM>. On the bottom major surface <NUM>, the CSP semiconductor device <NUM> includes multiple contacts <NUM>, <NUM>. The contacts <NUM>, <NUM> electrically connect to a bottom surface of a semiconductor die <NUM> to external circuit components, such as a printed circuit board (PCB) (not illustrated). The contacts <NUM>, <NUM> are formed on a surface of the semiconductor die <NUM>.

The semiconductor device <NUM> is packaged in a mould material <NUM> using any appropriate mould compound such as an epoxy based material. The mould material <NUM> is arranged to cover all six sides of the semiconductor die <NUM>, with the exception of the contacts <NUM>, <NUM>.

<CIT> relates to bumped integrated circuits for optical applications. <CIT> relates to a semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump. <CIT> relates to a semiconductor device and method of forming a thick encapsulant for stiffness with recesses for stress relief in fan-out WLCSP. <CIT>, <CIT> and <CIT> relate to semiconductor devices within similar technical field as the present invention.

Furthermore, <CIT> discloses:
A chip scale package semiconductor device, comprising;a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface;a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a moulding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through moulding material, wherein the opposing second major surface of the carrier is arranged as a recess in the carrier,wherein the recess is arranged to mountably receive the semiconductor die, and wherein the recess is arranged to receive an adhesive layer for mounting the semiconductor die to the carrier.

Compared to conventional CSP semiconductor devices without mould compound, conventional six sided protected CSP device suffer from the problem of how to dissipate heat generated in the semiconductor die during operation. This is of particular concern when the semiconductor die is a power device.

According to an embodiment of the present invention there is provided a chip scale package semiconductor device according to claim <NUM>, comprising; a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a moulding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through the moulding material, and the at least two terminals are exposed through the moulding material on a second side of the device. The chip scale semiconductor package device according to claim <NUM> is such that the opposing second major surface of the carrier is arranged as a recess in the carrier, such that the recess is arranged to mountably receive the semiconductor die and such that an adhesive layer is arranged in the recess for mounting the semiconductor die to the carrier.

The carrier may extend and be exposed through the moulding material on opposing side walls of the device.

The first major surface of the carrier may be co-planar with the moulding material on a top major surface of the device.

A top major surface of the package may comprise the carrier and a second opposing major surface of the package may comprise the terminals and the moulding material.

According to another embodiment of the present invention there is provided a method of manufacturing a chip scale package semiconductor device, according to claim <NUM>, the method comprising: providing a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; providing a carrier comprising a first major surface and an opposing second major surface; mounting the first major surface of the semiconductor die to the opposing second major surface of the carrier; partially encapsulating the semiconductor die and the carrier in a moulding material, wherein the first major surface of the carrier extends and is exposed through the moulding material, and the at least two terminals are exposed through the moulding material on a second side of the device. The method of manufacturing a chip scale semiconductor package device according to claim <NUM> is such that the opposing second major surface of the carrier is arranged as a recess in the carrier, such that the recess is arranged to mountably receive the semiconductor die and such that the recess receives an adhesive layer for mounting the semiconductor die to the carrier.

The semiconductor die and the carrier may be encapsulated such that the first major surface of the carrier is co-planar with the moulding material on a top major surface of the device.

The CSP semiconductor device according to the embodiments provides for improved heat dissipation and structural integrity, without increasing the height of the overall package. The CSP device according to embodiments is therefore suited to high power transistor devices.

<FIG> is cross-sectional view of a six-sided Protected Chip Scale Package (CSP) semiconductor device <NUM>.

The CSP semiconductor device <NUM> has a top major surface <NUM> and an opposing bottom major surface <NUM>. On the bottom major surface <NUM>, the CSP semiconductor device <NUM> includes multiple terminals or contacts <NUM>, <NUM>. The terminals <NUM>, <NUM> electrically connect to a bottom surface of a semiconductor die <NUM> of the CSP semiconductor device <NUM> to external circuit components, such as a printed circuit board (PCB), not illustrated. The contacts <NUM>, <NUM> are formed on a surface of the semiconductor die <NUM>.

The top major surface <NUM> of the CSP semiconductor device <NUM> includes a metal (or plastic) carrier <NUM> to support the semiconductor die <NUM>. The carrier <NUM> is fixedly mounted to a top surface of the semiconductor die <NUM> by any appropriate means, such as an epoxy based adhesive <NUM>.

Whilst <FIG>, illustrates two contacts <NUM>, <NUM> formed on the bottom surface of the semiconductor die <NUM>, the skilled person will recognise that the any number of contacts may be provided dependent on the type and functionality of the semiconductor die <NUM>. For example, where the semiconductor die is a field effect transistor, the number of contacts may be three, with respective contacts connected to corresponding source, gate and drain terminals of the semiconductor die <NUM>. The semiconductor die <NUM> may alternatively be a bipolar junction transistor, thyristor or a two terminal diode. In addition a passivation layer <NUM> may be included on the surface of the semiconductor die <NUM> having the contacts <NUM>, <NUM>.

The CSP semiconductor device <NUM> is packaged in a mould material <NUM> using any appropriate mould compound such as an epoxy based material. The mould material may substantially cover the four minor sides of the CSP semiconductor device <NUM>. With the exception of the contacts <NUM>, <NUM>, the mould material <NUM> may also be formed to cover the bottom major surface of the device <NUM>. The mould material <NUM> may be arranged on the top major surface <NUM> of the device <NUM> so that a top surface of the carrier <NUM> is exposed.

The carrier <NUM> may also include one or more metal tabs <NUM> that extend from each side of the carrier <NUM> to protrude through the mould material <NUM> so as to be exposed at opposing sides of the CSP semiconductor device <NUM>. The tabs <NUM> are an artefact of the singulation process of the CSP semiconductor device <NUM>, which will be discussed in more detail below.

A side view of CSP semiconductor device <NUM> is illustrated in <FIG>, which shows the tabs <NUM>, protruding through the mould material <NUM> on the side of the device <NUM>. <FIG> illustrates one side of the device <NUM> and the skilled person will appreciate that the corresponding opposing side will have the same arrangement of tabs <NUM>, <NUM> protruding through the mould material <NUM>, due to the matrix arrangement of the carrier as discussed below.

<FIG> illustrates a bottom view of the CSP semiconductor device <NUM> and shows the contacts <NUM>, <NUM> and the mould material <NUM> arranged on the bottom surface <NUM> of the device <NUM>. <FIG> illustrates a top view of the CSP semiconductor device <NUM> and shows the carrier <NUM> protrude through the mould material <NUM> such that the carrier is exposed on the top surface <NUM> of the device <NUM>. An optional chamfer <NUM> may be arranged on the carrier <NUM>, which may be used to indicate contact polarity and assist in device orientation when placing on PCB.

The arrangement of the carrier <NUM> to protrude through the top surface <NUM> of the device <NUM> and also through the opposing side walls provides improved thermal characteristics of the device <NUM>. The carrier, which acts as a heat sink is exposed, rather than covered by the mould material, and thus any heat generated in the die during operation of the device may be efficiently dissipated away from the semiconductor die <NUM>. This may be particularly advantageous where the device is a high power device.

Furthermore, and as discussed in more detail below with respect to the method of fabrication, the arrangement of the carrier <NUM> in the device <NUM>, when compared to conventional devices, is provided without increasing the overall package height of the device <NUM>.

Furthermore, the carrier <NUM> also provides mechanical strength to the device <NUM> by supporting the semiconductor die <NUM>. This is particularly advantageous where the device <NUM> is used in harsh environmental conditions such as in automotive applications.

<FIG> illustrates a multi-die CSP semiconductor device <NUM>, whereby multiple semiconductor dies 310a, 310b are arranged in the CSP semiconductor device <NUM>. As with the previous CSP semiconductor device <NUM>, the dies will be fixed to a carrier <NUM> using, for example, an epoxy based adhesive. The mould material <NUM> is arranged to separate the multiple dies 310a, 310b. This arrangement may be advantageous, where the semiconductor dies 310a, 310b are arranged in, for example a cascode, or half-bridge configurations.

<FIG> illustrate an embodiment according to the claimed invention, whereby the carrier <NUM> includes a recessed portion for accommodating the adhesive <NUM> and an upper portion of the semiconductor die <NUM>. In the embodiment of <FIG> the recessed portion of the carrier <NUM> is sized to receive the semiconductor die <NUM> and the adhesive <NUM> arranged thereon. Alternatively, the recessed portion <NUM> of the carrier <NUM> may be sized to receive the adhesive <NUM> arranged on the semiconductor die <NUM>. The arrangement of <FIG> may be advantageous in reducing the overall package height of the device <NUM>. In addition adhesive bleeds may be prevented by containing the adhesive <NUM> within the recess <NUM> of the carrier <NUM>. The skilled person will also understand that the embodiment of <FIG> is also amenable to multi-die arrangements such as the arrangement of <FIG>.

An example process flow for manufacturing the semiconductor device according to the above figures will now be described with reference to <FIG> which illustrates example process steps.

With reference to <FIG>, a metallic frame <NUM> is arranged on a carrier tape <NUM>. The carrier tape <NUM> prevents mould material from covering the carrier during the moulding process and ensures that, as discussed above with reference to <FIG> and <FIG> that the carrier <NUM> is exposed and protrudes through the top surface <NUM> of the device <NUM>. The metallic frame comprises a repeating matrix of carriers <NUM> whereby neighbouring carriers are interconnected by connecting members <NUM> or tie bars. The matrix of carriers interconnected by the connecting members <NUM> may be a linear matrix. Alternatively, and as illustrated in the plan view of <FIG>, the matrix of carriers may be n x m matrix, where n is the number of rows in the matrix and m is the number of columns in the matrix, and where n and m are both positive integers, with adjacent carriers <NUM> connected by connecting members <NUM>. The example of <FIG> illustrates one connecting member <NUM> connecting adjacent carriers in any row or column. However, consistent with the example of <FIG>, the skilled person will appreciate the number of connecting members <NUM> may be greater than one on any one side of the device.

As illustrated in <FIG>, semiconductor dies <NUM> are then attached to respective carriers <NUM> using a die attach material <NUM>, such as an epoxy based adhesive as mentioned above, or any appropriate solder or glue. In certain applications the die attach material may be conductive to enable electrical connection from the carrier <NUM> to the semiconductor die <NUM>. It should be noted that the semiconductor dies <NUM> are attached top down to the carrier <NUM>. In other words the top major surface of the semiconductor die <NUM>, that is, the major surface opposing the surface having the contacts <NUM>, <NUM> is affixed to a respective carrier using the adhesive <NUM>. The adhesive may then be set or solidified by heat curing.

Following the semiconductor die <NUM> attach process discussed above, the arrangement of semiconductor dies attached to the carriers is then packaged. <FIG> illustrates a packaging process known as film assisted moulding (FAM), whereby a protective film <NUM> is applied over the matrix of attached or fixed dies. The matrix is then loaded into a moulding machine whereby the liquefied moulding material is forced into closed mould cavities formed by the protective film <NUM> and the carrier tape <NUM>. The moulding material is then solidified by curing.

When the moulded matrix is removed from the moulding machine the protective film <NUM> is also removed. Following the moulding process, the matrix may also undergo a process known as post mould curing to further cure and solidify the liquefied moulding material.

Following moulding and curing, the carrier tape is removed, by a process known as de-taping, from the moulded matrix as illustrated in <FIG>. When de-taping is completed, any excess mould material present on the contacts or on the exposed side of the carrier is removed, as illustrated in <FIG> by a process known as deflashing. Once deflashing is completed the exposed side of the carrier may be marked with device details such as for example a product type, using for example a laser, as illustrated in <FIG>.

As an alternative to the FAM process mentioned above, the moulding may be achieved using an over-moulding process as illustrated in <FIG>. In the over-moulding process, the mould material <NUM> is arranged to completely cover the semiconductor dies <NUM>, including the contacts arranged thereon. Following curing of the mould material <NUM>, the mould material is removed until the contacts are exposed using a grinding process.

Following marking, individual CSP semiconductor devices <NUM> are separated by singulation from the matrix arrangement. Singulation is carried out along the sidewall walls of the semiconductor devices <NUM>. The singulation process may be any appropriate cutting process, such as laser cutting, plasma cutting, saw cutting or any combination thereof, in order to separate the devices <NUM>. The step of singulation severs the connecting members <NUM> and the mould material <NUM> of adjacent devices <NUM>. This results in the tabs <NUM> as discussed above with respect to <FIG> extending through mould material <NUM> at the side walls of the device <NUM>.

Following singulation, the devices may be electrically tested to ensure that they have not been damaged during the packaging process. Following testing the devices may be placed on a carrier tape and loaded on reel in preparation for shipping.

Claim 1:
A chip scale package semiconductor device (<NUM>), comprising;
a semiconductor die (<NUM>) having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface;
a carrier (<NUM>) comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier (<NUM>); and
a moulding material (<NUM>) partially encapsulating the semiconductor die and the carrier (<NUM>), wherein the first major surface of the carrier extends and is exposed through the moulding material, and the at least two terminals are exposed through the moulding material on a second side of the device,
wherein the opposing second major surface of the carrier is arranged as a recess (<NUM>) in the carrier (<NUM>),
wherein the recess (<NUM>) is arranged to mountably receive the semiconductor die, and
wherein an adhesive layer (<NUM>) is arranged in the recess (<NUM>) for mounting the semiconductor die to the carrier (<NUM>).