Patent Description:
Single slope analog to digital converters (ADCs) have been used for analog to digital (AD) conversion in solid-state image sensors or the like because of its simple structures. This single slope ADC is generally configured by a comparator and a counter that performs counting on the basis of a comparison result of the comparator. For example, a solid-state image sensor has been proposed, which has a p-channel metal-oxide-semiconductor (pMOS) transistor and an inverter arranged in the comparator, the pMOS transistor having a pixel signal input to a source and a reference signal input to a gate (for example, see PTL <NUM>). This pMOS transistor outputs a drain voltage thereof to the counter via the inverter as a comparison result of the pixel signal and the reference signal. Document <CIT> relates to a sensor that includes an image sensing unit including pixel blocks, and a readout unit for reading out a signal from the image sensing unit. The pixel block includes a photoelectric converter, first and second transistors, and a current source. First main electrodes of the first and second transistors are connected to a common node, and the current source is provided between the common node and a predetermined voltage. A signal readout operation includes an operation in which a voltage corresponding to charges in the photoelectric converter is supplied to a control electrode of the first transistor, and a temporally changing reference voltage is supplied to a control electrode of the second transistor. The readout unit reads out a signal from the image sensing unit via a second main electrode of the first transistor. In the photoelectric conversion apparatus of document <CIT>, a pixel transistor and a differential transistor form a differential pair. A clamp circuit clamps a gate voltage of the differential transistor. An output circuit performs a first operation in which a voltage based on the voltage at the gate of a pixel transistor is output to the gate of the differential transistor. The output circuit also performs a second operation in which in response to receiving a current from the differential transistor, a signal based on a result of a comparison between the gate voltage of the pixel transistor and the gate voltage of the differential transistor is output to the output node. In the second operation, a control unit in the output circuit controls a change in the drain voltage of the differential transistor to be smaller than a change in the voltage at the output node. According to document <CIT> a plurality of pixels includes a photoelectric conversion unit and the first transistor. A signal line is connected to the plurality of pixels. A second transistor includes a source or a drain electrically connected to the first transistor and includes a gate supplied with a signal corresponding to a reference signal of which a potential changes at a predetermined gradient with time. A first current source is configured to supply a current to the first and second transistors. A control unit is configured to control a voltage between a gate and a source of a third transistor to be a voltage corresponding to a voltage between the gate and the source of the second transistor. A comparator circuit is configured to compare a first current flowing through the third transistor with a reference current.

In the above-described solid-state image sensor, the comparator shares a power supply of a pixel circuit, thereby reducing power consumption, as compared with a configuration having a power supply in the comparator separately from the pixel circuit. However, in a connection configuration of the above-described solid-state image sensor, the drain voltage of the pMOS transistor varies according to a level of the pixel signal when the pixel signal substantially coincides with the reference signal. For this reason, timing when the comparison result is inverted may be shifted from ideal timing when the pixel signal substantially coincides with the reference signal. There is a problem that an error or non-linearity occurs in a digital signal obtained by AD conversion of the pixel signal due to this inversion timing error, and image quality of image data is degraded.

The present technology has been made in view of the foregoing, and it is desirable to suppress an error in inversion timing of a comparison result in a solid-state image sensor that compares a reference signal and a pixel signal.

The invention is defined by the appended independent claim <NUM> and preferred embodiments are defined by the appended dependent claims.

According to the modification of an embodiment of the present technology, the input-side clamp transistor suppresses the decrease in the drain voltage, thereby preventing the stop of the supply of the current.

Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. Description will be given according to the following order.

<FIG> is a block diagram illustrating a configuration example of an imaging device <NUM> according to a first embodiment of the present technology. The imaging device <NUM> is a device for imaging image data, and includes an optical unit <NUM>, a solid-state image sensor <NUM>, and a digital signal processing (DSP) circuit <NUM>. Moreover, the imaging device <NUM> includes a display unit <NUM>, an operation unit <NUM>, a bus <NUM>, a frame memory <NUM>, a storage unit <NUM>, and a power supply unit <NUM>. As the imaging device <NUM>, a camera mounted on a smartphone, an in-vehicle camera, or the like is assumed.

The optical unit <NUM> condenses light from an object and guides the light to the solid-state image sensor <NUM>. The solid-state image sensor <NUM> generates image data by photoelectric conversion. The solid-state image sensor <NUM> supplies the generated image data to the DSP circuit <NUM> via a signal line <NUM>.

The DSP circuit <NUM> executes predetermined signal processing for the image data. The DSP circuit <NUM> outputs the processed image data to the frame memory <NUM> or the like via the bus <NUM>.

The display unit <NUM> displays the image data. As the display unit <NUM>, for example, a liquid crystal panel or an organic electro luminescence (EL) panel is assumed. The operation unit <NUM> generates an operation signal according to a user operation.

The bus <NUM> is a common path for the optical unit <NUM>, the solid-state image sensor <NUM>, the DSP circuit <NUM>, the display unit <NUM>, the operation unit <NUM>, the frame memory <NUM>, the storage unit <NUM>, and the power supply unit <NUM> to exchange data with one another.

The frame memory <NUM> holds image data. The storage unit <NUM> stores various data such as image data. The power supply unit <NUM> supplies power to the solid-state image sensor <NUM>, the DSP circuit <NUM>, the display unit <NUM>, and the like.

<FIG> and <FIG> are block diagrams illustrating a configuration example of the solid-state image sensor <NUM> according to the first embodiment of the present technology. The solid-state image sensor <NUM> includes a vertical scanning circuit <NUM>, a timing control unit <NUM>, a digital to analog converter (DAC) <NUM>, a pixel array unit <NUM>, a column signal processing unit <NUM>, and a horizontal scanning circuit <NUM>. The solid-state image sensor <NUM> may be integrated into a single chip, or may be implemented as a stacked structure. In the stacked structure, the various illustrated components may be respectively formed in multiple substrates which are then stacked together, bonded or laminated, and connected to one another by a connection portion.

In the example illustrated in <FIG>, a first substrate <NUM> includes the pixel array unit <NUM> and a second substrate <NUM> includes the vertical scanning circuit <NUM>; the timing control unit <NUM>; the DAC <NUM>; a pair of counter areas <NUM>, a pair of latch areas <NUM>, and a pair of comparator areas <NUM> (which may be components of the column signal processing unit <NUM>); the horizontal scanning circuit <NUM>; and an interface (I/F) <NUM>. In this example, the first substrate <NUM> and the second substrate <NUM> both include a plurality of pads <NUM> and a plurality of connection portions <NUM>. The connection portions <NUM> may be Cu-Cu connection (CCC), a through-silicon via (TSV), a continuous wire, and the like. As illustrated in <FIG>, the comparator <NUM> is disposed adjacent the connection portions <NUM>.

In another example, the pixel array unit <NUM> and a control circuit including the vertical scanning circuit <NUM> and the timing control unit <NUM> may be disposed in a first substrate; and a signal processing circuit including the DAC <NUM>, the column signal processing unit <NUM>, and the horizontal scanning circuit <NUM> may be disposed in a second substrate. In another example, the pixel array unit <NUM> may be disposed in a first substrate; the control circuit including the vertical scanning circuit <NUM> and the timing control unit <NUM> may be disposed in a second substrate; and the signal processing circuit including the DAC <NUM>, the column signal processing unit <NUM>, and the horizontal scanning circuit <NUM> may be disposed in a third substrate.

In the pixel array unit <NUM>, a plurality of pixel circuits <NUM> is arrayed in a two-dimensional lattice pattern. Hereinafter, a set of the pixel circuits <NUM> arrayed in a predetermined horizontal direction is referred to as a "row", and a set of the pixel circuits <NUM> arrayed in a vertical direction with respect to the row is referred to as a "column".

The vertical scanning circuit <NUM> sequentially drives the rows to cause the pixel circuits <NUM> to output signals.

The timing control unit <NUM> controls operation timing of each of the vertical scanning circuit <NUM>, the DAC <NUM>, the column signal processing unit <NUM>, and the horizontal scanning circuit <NUM> in synchronization with a vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal having a predetermined frequency (such as <NUM> hertz) indicating imaging timing.

The DAC <NUM> generates a predetermined reference signal by digital to analog (DA) conversion. As the reference signal, for example, a sawtooth ramp signal is used. The DAC <NUM> supplies the reference signal to the column signal processing unit <NUM>. Note that the DAC <NUM> is an example of a reference signal supply unit described in the claims.

The pixel circuit <NUM> generates an analog pixel signal by photoelectric conversion and supplies the analog pixel signal to the column signal processing unit <NUM>.

The column signal processing unit <NUM> performs signal processing such as AD conversion processing and correlated double sampling (CDS) processing for the pixel signal for each column. The column signal processing unit <NUM> supplies image data including a processed digital signal to the DSP circuit <NUM> via the signal line <NUM>.

The horizontal scanning circuit <NUM> controls the column signal processing unit <NUM> to sequentially output the digital signals.

<FIG> is a circuit diagram illustrating a configuration example of the pixel circuit <NUM> according to the first embodiment of the present technology. The pixel circuit <NUM> includes a photoelectric conversion element <NUM>, a transfer transistor <NUM>, a reset transistor <NUM>, a floating diffusion layer <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM>. Furthermore, in the pixel array unit <NUM>, the vertical signal line VSL is wired for each column along the vertical direction.

The photoelectric conversion element <NUM> photoelectrically converts incident light to generate charges. The transfer transistor <NUM> transfers the charges from the photoelectric conversion element <NUM> to the floating diffusion layer <NUM> according to a drive signal TRG from the vertical scanning circuit <NUM>.

The reset transistor <NUM> extracts and initializes the charges from the floating diffusion layer <NUM> according to a drive signal RST from the vertical scanning circuit <NUM>.

The floating diffusion layer <NUM> accumulates the charges and generates a voltage corresponding to a charge amount. The amplification transistor <NUM> amplifies the voltage of the floating diffusion layer <NUM>.

The selection transistor <NUM> outputs an amplified voltage signal as a pixel signal to the column signal processing unit <NUM> via the vertical signal line VSL according to a drive signal SEL from the vertical scanning circuit <NUM>.

Note that the pixel circuit <NUM> is not limited to the circuit illustrated in <FIG> as long as the pixel circuit <NUM> can generate the pixel signal by photoelectric conversion.

<FIG> is a block diagram illustrating a configuration example of the column signal processing unit <NUM> according to the first embodiment of the present technology. In the column signal processing unit <NUM>, a comparator <NUM>, a counter <NUM>, and a latch <NUM> are arranged for each column. In a case where the number of columns is N (N is an integer), N comparators <NUM>, N counters <NUM>, and N latches <NUM> are arranged.

The comparator <NUM> compares the reference signal from the DAC <NUM> with the pixel signal from a corresponding column. Hereinafter, the voltage of the reference signal is referred to as a reference voltage VRMP, and the voltage of the pixel signal input via the vertical signal line VSL is referred to as an input voltage VVSL. The comparator <NUM> supplies a comparison result COMP between the reference voltage VRMP and the input voltage VVSL to the counter <NUM> of the corresponding column.

Furthermore, the input voltage VVSL of when the pixel circuit <NUM> is initialized is hereinafter referred to as a "reset level", and the input voltage VVSL of when the charge is transferred to the floating diffusion layer <NUM> is hereinafter referred to as a "signal level".

The counter <NUM> counts a count value over a period until the comparison result COMP is inverted. For example, the counter <NUM> down-counts over a period until the comparison result COMP with the reset level is inverted, and up-counts over a period until the comparison result COMP with the signal level is inverted. By the counting, the CDS processing for obtaining a difference between the reset level and the signal level is implemented.

Then, the counter <NUM> causes the latch <NUM> to hold a digital signal indicating the count value. The AD conversion processing for converting the analog pixel signal into the digital signal is implemented by the comparator <NUM> and the counter <NUM>. That is, the comparator <NUM> and the counter <NUM> function as an ADC. An ADC using a comparator and a counter in this manner is generally called single slope ADC.

Note that the CDS processing is implemented by up-counting and down-counting. However, the CDS processing is not limited to this configuration. A configuration in which the counter <NUM> performs only the up-counting or the down-counting, and CDS processing for obtaining a difference is executed by a subsequent-stage circuit may be adopted.

The latch <NUM> holds the digital signal. The latch <NUM> outputs the held digital signal to the DSP circuit <NUM> under the control of the horizontal scanning circuit <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the first embodiment of the present technology. The comparator <NUM> includes capacitors <NUM> and <NUM>, an input transistor <NUM>, an auto-zero switch <NUM>, an output transistor <NUM>, an input-side current source <NUM>, and an output-side current source <NUM>.

The capacitor <NUM> is inserted between the DAC <NUM> and a gate of the input transistor <NUM>.

A source of the input transistor <NUM> is connected to the vertical signal line VSL, and the input voltage VVSL is input to the source. Furthermore, the reference voltage VRMP is input to the gate of the input transistor <NUM> via the capacitor <NUM>. At a point of time when the input voltage VVSL input to the source substantially coincides with the reference voltage VRMP input to the gate, the input transistor <NUM> becomes a voltage state that is the same as a voltage state at an auto-zero time and outputs a drain voltage Vd according to the input voltage VVSL and the reference voltage VRMP from a drain. Here, "substantially coincide" means that changes from voltage values in respective auto-zero periods are completely coincident or the difference falls within a predetermined allowable value. For example, a pMOS transistor is used as the input transistor <NUM>.

Furthermore, a back gate and the source of the input transistor <NUM> are desirably short-circuited in order to suppress a back gate effect.

The auto-zero switch <NUM> is for short-circuiting the gate and the drain of the input transistor <NUM> according to a control signal AZSW1 from the timing control unit <NUM>.

The input-side current source <NUM> is inserted between the drain of the input transistor <NUM> and a predetermined reference terminal (such as a ground terminal). The input-side current source <NUM> supplies a fixed current Id1. The input-side current source <NUM> is implemented by an n-channel MOS (nMOS) transistor and the like. The circuit configuration of the input-side current source <NUM> will be described below.

The capacitor <NUM> is inserted between the source and the drain of the input transistor <NUM>.

A source of the output transistor <NUM> is connected to the vertical signal line VSL, and the input voltage VVSL is input to the source. Furthermore, a gate of the output transistor <NUM> is connected to the drain of the input transistor <NUM>, and the drain voltage Vd is input to the gate of the output transistor <NUM>. For example, as the output transistor <NUM>, a pMOS transistor is used. Furthermore, a back gate and the source of the output transistor <NUM> are desirably short-circuited.

The output transistor <NUM> outputs a signal indicating whether or not a difference between the input voltage VVSL input to the source and the drain voltage Vd input to the gate exceeds a predetermined threshold voltage from a drain as a comparison result COMP. The comparison result COMP is supplied to the counter <NUM>.

The output-side current source <NUM> is inserted between the drain of the output transistor <NUM> and a predetermined reference terminal (such as a ground terminal) and supplies a fixed current Id2. The output-side current source <NUM> is implemented by an nMOS transistor and the like. The circuit configuration of the output-side current source <NUM> will be described below.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the first embodiment of the present technology.

At timing T0 immediately before the start of AD conversion, the control signal AZSW1 is input over a predetermined auto-zero period. As a result, the gate and the drain of the input transistor <NUM> are short-circuited, and auto-zeroing of the comparator <NUM> is performed.

Next, the DAC <NUM> gradually lowers the reference voltage VRMP over a fixed period from timing T2. Meanwhile, the pixel circuit <NUM> is initialized, and the input voltage VVSL (that is, the reset level) at this time is set to VVSLp.

Then, at timing T3, the reference voltage VRMP is assumed to substantially coincide with the reset level VVSLp.

The drain voltage Vd of the input transistor <NUM> at this timing T3 is set to Vdp. When a level lower than Vdp is set to a low level and a level equal to or higher than Vdp is set to a high level, the drain voltage Vd of the input transistor <NUM> is inverted from the low level to the high level at the timing T3.

Next, the DAC <NUM> initializes the reference voltage and gradually lowers the reference voltage VRMP over a fixed period from timing T5. Meanwhile, charges are transferred to the floating diffusion layer <NUM>, and the input voltage VVSL (that is, the signal level) at this time is set to VVSLd. This signal level VVSLd is assumed to be lower than the reset level VVSLp by ΔV.

Then, at timing T6, the reference voltage VRMP is assumed to substantially coincide with the signal level VVSLd. The drain voltage Vd of the input transistor <NUM> at this timing T6 is set to Vdd. The drain voltage Vdd is a value lower than the drain voltage Vdp by ΔV. That is, the drain voltage Vdd at the timing T6 becomes lower as the input voltage (signal level VVSLd) at that time is lower.

Since the drain voltage Vdd of the input transistor <NUM> is lowered by ΔV from the drain voltage Vdp at the reset level conversion time, the timing when this drain voltage Vd is determined to be inverted is timing T7 after the timing T6 in an existing technology. Therefore, if this drain voltage Vd is used as the comparison result COMP, the inversion timing T7 of the comparison result COMP is shifted from the ideal timing T6 at which the reference voltage VRMP substantially coincides with the signal level VVSLd. As a result, an linearity error and an offset occur in the ADC, and the image quality of the image data may be deteriorated due to these errors.

However, as described above, the output transistor <NUM> is provided at a subsequent stage of the input transistor <NUM>, and the source and the drain of the input transistor <NUM> are connected to the source and the gate of the output transistor <NUM>. With this connection, a drain-source voltage Vds of the input transistor <NUM> is input as a gate-source voltage of the output transistor <NUM>.

As illustrated in <FIG>, a voltage drop amount ΔV of the input voltage VVSL is the same as a voltage drop amount of the drain voltage Vd at the timings T3 and T6 when the reference voltage VRMP substantially coincides with the input voltage VVSL. Therefore, at these timings, the drain-source voltages Vds have the same value. At this time (that is, at the timings T3 and T6), the value of the drain-source voltage Vds is the same as the value at the auto-zero time. Since the drain-source voltage Vds is the gate-source voltage of the output transistor <NUM>, the drain voltage of the output transistor <NUM> is inverted at the timings T3 and T6.

Since the inversion timing of the comparison result COMP is the ideal timing at which the reference voltage VRMP substantially coincides with the signal level VVSLd, an error in the inversion timing is suppressed. As a result, the linearity error and the offset can be made small and the image quality of the image data can be improved, as compared with a case of using the drain voltage Vd as the comparison result COMP.

Next, the reason why the voltage drop amount ΔV of the drain voltage Vd of the input transistor <NUM> becomes the same as the voltage drop amount of the input voltage VVSL input to the source at the timings T3 and T6 will be described.

<FIG> is a graph illustrating an example of a characteristic of a pMOS transistor according to the first embodiment of the present technology. In <FIG>, the vertical axis represents a drain current, and the horizontal axis represents the drain-source voltage. Furthermore, the one-dot chain line illustrates a boundary between a linear region and a saturation region.

As a general rule, an operating point of the pMOS transistor is determined so as to operate in the saturation region at the auto-zero time. A drain current Id in this saturation region is expressed by the following expression.

In the above expression, µ represents electron mobility and the unit is, for example, square meter per volt second (m2/V • s). COX represents a capacitance per unit area of a MOS capacitor and the unit is, for example, farad per meter (F/m). W represents a gate width and the unit is, for example, meter (m). L represents a gate length and the unit is, for example, meter (m). Vth represents the threshold voltage and the unit is, for example, volt (V). λ represents a predetermined coefficient. Furthermore, the unit of the drain-source voltage Vds is, for example, volt (V), and the unit of the drain current Id is, for example, ampere (A).

Since the input transistor <NUM> is a pMOS transistor, the expression <NUM> is established in the saturation region. At this time, the drain current Id is a fixed value (that is, Id1) supplied from the input-side current source <NUM>. Furthermore, the electron mobility µ, the unit capacity COX, the gate width W, the gate length L, the threshold voltage Vth, and the coefficient λ are fixed values.

Furthermore, when the reference voltage VRMP and the input voltage VVSL input to the gate and the source of the input transistor <NUM> substantially coincide with each other, the gate-source voltage VGS is a fixed value determined at the auto-zero time.

Therefore, when the reference voltage VRMP and the input voltage VVSL input to the gate and the source of the input transistor <NUM> substantially coincide with each other, the drain-source voltage Vds is also a fixed value according to the expression <NUM>. When the fixed drain-source voltage is Vds1, the following expressions are established at the above-described timings T3 and T6. <MAT> <MAT>.

When the drain-source voltage Vds1 is deleted from the expressions <NUM> and <NUM>, the following expression is obtained.

Note that, in a case where the operating point of the pMOS transistor is determined so as to operate in the linear region at the auto-zero time, the expression <NUM> takes a different form but the expression <NUM> is similarly established.

According to the expression <NUM>, the voltage drop amount ΔV of the drain voltage Vd of the input transistor <NUM> becomes the same as the voltage drop amount of the input voltage VVSL input to the source. Therefore, the timing chart illustrated in <FIG> is obtained.

Next, a first comparative example of not providing the output transistor <NUM> will be considered.

<FIG> is a circuit diagram illustrating a configuration example of a comparator according to the first comparative example. In the first comparative example, an inverter is provided at a subsequent stage of an input transistor, instead of the output transistor <NUM>. The inverter inverts the drain voltage of the input transistor and outputs the drain voltage as the comparison result COMP. Substantially, the drain voltage of the input transistor is used as the comparison result COMP.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator according to the first comparative example. Variation in the input voltage VVSL, the reference voltage VRMP, and the drain voltage Vd in the first comparative example are similar to those in the first embodiment illustrated in <FIG>.

As described above, according to the expression <NUM>, the voltage drop amount of the drain voltage Vd of the input transistor becomes the same as the voltage drop amount of the input voltage VVSL input to a source of the input transistor. For this reason, the timing T7 at which the drain voltage Vd is inverted is shifted from the ideal timing T6 at which the reference voltage substantially coincides with the signal level. Since the inverter of the first comparative example inverts the drain voltage Vd as it is, the inversion timing of the comparison result COMP is similarly shifted from the ideal timing T6. Due to this timing error, the image quality of the image data is degraded.

Next, a second comparative example using a differential amplifier circuit will be considered.

<FIG> is a circuit diagram illustrating a configuration example of a comparator according to the second comparative example. A differential amplifier circuit is arranged in the second comparative example. Furthermore, in a load MOS circuit, a current source is further connected to the vertical signal line VSL.

Since a differential amplifier circuit is used in the second comparative example, the comparison result COMP is inverted at ideal timing at which the reference voltage substantially coincides with the signal level, unlike the first comparative example. Meanwhile, as illustrated in <FIG>, a current source is necessary in a load MOS circuit and a power supply is necessary in the comparator. Therefore, the power consumption becomes large.

In summary, since the output transistor <NUM> is not provided in the first comparative example, the image quality of the image data is degraded as compared with the first embodiment. The differential amplification-type second comparative example can solve the problem of the image quality degradation of the image data, but the second comparative example is not favorable due to larger power consumption than the first embodiment.

<FIG> is a flowchart illustrating an example of an operation of the solid-state image sensor according to the first embodiment of the present technology. This operation is started when, for example, a predetermined application for capturing image data is executed.

In the solid-state image sensor <NUM>, the vertical scanning circuit <NUM> sequentially selects and drives the rows (step S901). The column signal processing unit <NUM> performs AD conversion for the reset level for each column (step S902) and performs AD conversion for the signal level (step S903).

The solid-state image sensor <NUM> determines whether or not readout of all the rows has been completed (step S904). In a case where the readout of all the rows has not been completed (step S904: No), the solid-state image sensor <NUM> repeatedly executes the processing of step S901 and the subsequent steps. On the other hand, in a case where readout of all the rows has been completed (step S904: Yes), the solid-state image sensor <NUM> terminates the operation for imaging the image data. In a case where a plurality of image data is sequentially imaged, steps S901 to S904 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.

As described above, according to the first embodiment of the present technology, the input transistor <NUM> supplies the drain-source voltage between the gate and the source of the output transistor <NUM>, thereby inverting the comparison result at the timing when the input voltage coincides with the reference voltage. As a result, the noise caused by the error of the inversion timing can be reduced and the image quality of the image data can be improved.

In the above-described first embodiment, the input-side current source <NUM> has been connected to the drain of the input transistor <NUM>. However, in this configuration, the input voltage VVSL is significantly decreased, the drain voltage Vd is lowered, and the state of the transistor constituting the input-side current source <NUM> becomes a non-conducting state, and the supply of the drain current Id1 may be stopped. A comparator <NUM> according to a modification of the first embodiment is different from the comparator <NUM> according to the first embodiment in preventing the stop of the supply of the current Id1 by adding an input-side clamp transistor.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the modification of the first embodiment of the present technology. The comparator <NUM> of the modification of the first embodiment is different from the first embodiment in further including an input-side clamp transistor <NUM>.

The input-side clamp transistor <NUM> is inserted between the vertical signal line VSL (that is, the source of the input transistor <NUM>) and the power supply terminal. An nMOS transistor is used as the input-side clamp transistor <NUM>, and a fixed bias voltage Vclamp is applied to a gate of the input-side clamp transistor <NUM>. The input-side clamp transistor <NUM> can limit the drain voltage Vd to a predetermined lower-limit voltage or larger. With the configuration, the transistor constituting the input-side current source <NUM> can be maintained in a conductive state, and the stop of the supply of the current Id1 can be prevented.

As described above, according to the modification of the first embodiment of the present technology, the input-side clamp transistor <NUM> suppresses the decrease in the drain voltage Vd, thereby preventing the stop of the supply of the current Id1.

In the above-described modification of the first embodiment, the input-side clamp transistor <NUM> has been inserted between the power supply terminal and the vertical signal line VSL to suppress the decrease in the drain voltage Vd. However, in this configuration, when the current flows through the input-side clamp transistor <NUM>, the current to flow through the vertical signal line VSL decreases by the amount of the current flowing through the input-side clamp transistor <NUM>, and there is a possibility that a settling time of the vertical signal line VSL becomes long. A comparator <NUM> according to a second embodiment is different from the modification of the first embodiment in that an input-side clamp transistor is inserted between a source and a drain of an input transistor <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the second embodiment of the present technology. The comparator <NUM> receives a pixel signal VVSL from the pixel circuit <NUM> via a connection portion <NUM>. The connection portion <NUM> may be Cu-Cu connection (CCC), a through-silicon via (TSV), a continuous wire, and the like. The comparator <NUM> according to the second embodiment is different from the modification of the first embodiment in including an input-side clamp transistor <NUM> instead of the input-side clamp transistor <NUM>. Furthermore, an initialization switch <NUM> may be further included.

The input-side clamp transistor <NUM> is inserted between a source and a drain of an input transistor <NUM>. A pMOS transistor is used as the input-side clamp transistor <NUM>, and a gate of the input-side clamp transistor <NUM> is short-circuited with a drain of the input-side clamp transistor <NUM>. Furthermore, a back gate and the source of the input-side clamp transistor <NUM> are desirably short-circuited. The input-side clamp transistor <NUM> can suppress a decrease in a drain voltage Vd of when the input transistor <NUM> is in a non-conducting state. Furthermore, since the input-side clamp transistor is not connected to a power supply terminal, a current of a vertical signal line VSL is not reduced, and a settling time can be made shorter than the modification of the first embodiment.

Furthermore, the initialization switch <NUM> opens and closes a path between a gate and a drain of an output transistor <NUM> according to a control signal GDSW from a timing control unit <NUM>.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the second embodiment of the present technology.

The timing control unit <NUM> supplies the control signal GDSW to close the output transistor <NUM> over a pulse period from timing T4 between an AD conversion period at a reset level and an AD conversion period at a signal level. By this control, sticking of the drain voltage Vd to a lower-limit voltage can be suppressed by the vertical signal line VSL and the input-side clamp transistor <NUM> immediately before AD conversion of the signal level. As a result, the drain voltage Vd is stabilized, an error in the AD conversion of the signal level can be reduced, and an offset and a linearity error can be reduced.

As described above, according to the second embodiment of the present technology, the input-side clamp transistor <NUM> is inserted between the source and the drain of the input transistor <NUM>, and thus a decrease in the current of the vertical signal line VSL can be suppressed.

In the above-described second embodiment, only the output of the output-side current source <NUM> has been connected to the drain of the output transistor <NUM>. However, in this configuration, the voltage of a comparison result COMP may not be stabilized due to variation in characteristics of elements constituting a circuit. A comparator <NUM> according to a third embodiment is different from the second embodiment in setting a gate voltage of an output transistor <NUM> on the basis of an input-side current Id1 during an auto-zero period.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the third embodiment of the present technology. The comparator <NUM> according to the third embodiment is different from the second embodiment in arranging an auto-zero switch <NUM>, a capacitor <NUM>, and a current source transistor <NUM> in an output-side current source <NUM>. Furthermore, a current source transistor <NUM> and a capacitor <NUM> are arranged in an input-side current source <NUM> of the second embodiment. As the current source transistors <NUM> and <NUM>, nMOS transistors are used, for example.

The current source transistor <NUM> is inserted between a drain of an input transistor <NUM> and a reference terminal (such as a ground terminal). Furthermore, a predetermined bias voltage Vbias1 is applied to a gate of the current source transistor <NUM>. The capacitor <NUM> is inserted between the gate of the current source transistor <NUM> and the reference terminal. Note that the bias voltage Vbias1 may be sampled and held in the capacitor <NUM> by a switch (not illustrated) in an initial state.

Furthermore, the current source transistor <NUM> is inserted between a drain of an output transistor <NUM> and the reference terminal. The capacitor <NUM> is inserted between a gate of the current source transistor <NUM> and the reference terminal. The auto-zero switch <NUM> opens and closes a path between the gate and a drain of the current source transistor <NUM> according to a control signal AZSW2 from a timing control unit <NUM>. Note that the auto-zero switch <NUM> is an example of a first auto-zero switch described in the claims.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the third embodiment of the present technology. The timing control unit <NUM> further supplies a control signal AZSW2 in addition to the control signal AZSW1 over an auto-zero period from timing T0. The auto-zero switch <NUM> is controlled to be in a closed state by the control signal AZSW2.

Under the control of the auto-zero switch <NUM>, the gate voltage of the current source transistor <NUM> is self-set on the basis of an input-side current Id1. As a result, a voltage of a comparison result COMP is stabilized regardless of variation in elements.

As described above, according to the third embodiment of the present technology, the auto-zero switch <NUM> short-circuits the gate and the drain of the current source transistor <NUM>, and thus the gate voltage of the current source transistor <NUM> absorbs an error due to the variation and can stabilize the voltage of the comparison result COMP.

In the above-described third embodiment, the gate voltage of the output-side current source transistor <NUM> has been self-set during the auto-zero period. However, in this configuration, when the drain voltages of the input transistor <NUM> and the output transistor <NUM> are not uniform, there is a possibility that a current ratio of the input-side current Id1 to an output-side current Id2 deviates from an assumed value. A comparator <NUM> according to a fourth embodiment is different from the third embodiment in making deviation in the current ratio small by cascode-connecting transistors.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the fourth embodiment of the present technology. The comparator <NUM> according to the fourth embodiment is different from the third embodiment in further including an input-side cascode connection transistor <NUM>, an output-side cascode connection transistor <NUM>, and cascode control switches <NUM> and <NUM>. As the input-side cascode connection transistor <NUM> and the output-side cascode connection transistor <NUM>, pMOS transistors are used, for example.

The input-side cascode connection transistor <NUM> is cascode-connected to an input transistor <NUM>. The input-side cascode connection transistor <NUM> is inserted between a drain of the input transistor <NUM> and an input-side current source <NUM>. Furthermore, a gate of the input-side cascode connection transistor <NUM> is connected to a gate of the output-side cascode connection transistor <NUM>.

The output-side cascode connection transistor <NUM> is cascode-connected to an output transistor <NUM>. The output-side cascode connection transistor <NUM> is inserted between a drain of the output transistor <NUM> and an output-side current source <NUM>.

The cascode control switch <NUM> opens and closes a path between the gate and a drain of the input-side cascode connection transistor <NUM> according to a control signal CASEN from a timing control unit <NUM>.

The cascode control switch <NUM> opens and closes a path between the gates of the input-side cascode connection transistor <NUM> and the output-side cascode connection transistor <NUM> and a reference terminal according to XCASEN that is an inverted control signal CASEN.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the third embodiment of the present technology. The timing control unit <NUM> supplies the control signals CASEN and XCASEN over a fixed period from timing T0. By these control signals CASEN and XCASEN, the cascode control switch <NUM> is controlled to be in a closed state, and the cascode control switch <NUM> is controlled to be in an open state. As a result, a drain voltage of the input transistor <NUM> and a drain voltage of the output transistor <NUM> are easily uniform, and the deviation of the current ratio of the current Id1 to the current Id2 from the assumed value can be made small.

However, if the cascode is kept connected, a dynamic range may decrease. Therefore, at timing T1 after the auto-zero period has elapsed, the cascode control switch <NUM> is controlled to be in the open state and the cascode control switch <NUM> is controlled to be in the closed state by the control signals CASEN and XCASEN. As a result, the cascode connection is released and the decrease in the dynamic range can be prevented.

As described above, according to the fourth embodiment of the present technology, the transistors are cascode-connected to the input transistor <NUM> and the output transistor <NUM>, and thus the drain voltages of the transistors can be made uniform. As a result, the deviation of the current ratio of the current Id1 to the current Id2 from the assumed value can be made small.

In the above-described second embodiment, the input-side current source <NUM> and the output-side current source <NUM> have been provided. However, in a case where these current sources individually generate currents Id1 and Id2 by a bias voltage, values of the currents may vary. A solid-state image sensor <NUM> according to a fifth embodiment is different from the second embodiment in suppressing the variation in the currents by adding an auto-zero switch on an output side.

<FIG> is a circuit diagram illustrating a configuration example of a comparator <NUM> according to the fifth embodiment of the present technology. The comparator <NUM> according to the fifth embodiment is different from the second embodiment in further including a capacitor <NUM> and an auto-zero switch <NUM>. Furthermore, a sample-and-hold switch <NUM>, a capacitor <NUM>, and a current source transistor <NUM> are arranged in an output-side current source <NUM> according to the fifth embodiment. Furthermore, a current source transistor <NUM> and a capacitor <NUM> are arranged in an input-side current source <NUM> according to the fifth embodiment. As the current source transistors <NUM> and <NUM>, nMOS transistors are used, for example.

The current source transistor <NUM> is inserted between a drain of an input transistor <NUM> and a reference terminal. Furthermore, a predetermined bias voltage Vbias1 is applied to a gate of the current source transistor <NUM>. The capacitor <NUM> is inserted between a gate of the current source transistor <NUM> and the reference terminal.

Furthermore, the current source transistor <NUM> is inserted between a drain of an output transistor <NUM> and the reference terminal. The capacitor <NUM> is inserted between a gate of the current source transistor <NUM> and the reference terminal. The sample-and-hold switch <NUM> applies a predetermined bias voltage Vbias2 to the capacitor <NUM> and the gate of the current source transistor <NUM> according to a control signal ISBH from a timing control unit <NUM>.

Furthermore, the capacitor <NUM> is inserted between the drain of the input transistor <NUM> and a gate of the output transistor <NUM>. The auto-zero switch <NUM> short-circuits the gate and the drain of the output transistor <NUM> according to a control signal AZSW2 from the timing control unit <NUM>. Note that the auto-zero switch <NUM> is an example of a second auto-zero switch described in the claims.

Furthermore, an initialization switch <NUM> of the fifth embodiment opens and closes a path between the drain of the input transistor <NUM> and the drain of the output transistor <NUM> according to a control signal GDSW.

As described above, in each of the input-side current source <NUM> and the output-side current source <NUM>, currents Id1 and Id2 are individually generated by the bias voltage.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the fifth embodiment of the present technology. The timing control unit <NUM> further supplies a control signal ISBH in addition to the control signals AZSW1 and AZSW2 over an auto-zero period from timing T0. The output-side auto-zero switch <NUM> is controlled to be in a closed state by the control signal AZSW2. Furthermore, the sample-and-hold switch <NUM> in the output-side current source <NUM> is controlled to be in a closed state by the control signal ISBH.

An influence of the variation in the currents Id1 and Id2 of when the output-side offset is decreased by the output-side auto-zero switch <NUM> and the currents Id1 and Id2 are individually generated by the bias voltage can be suppressed.

As described above, according to the fifth embodiment of the present technology, the auto-zero switch <NUM> is added to the output side, and thus the influence of the variation in the currents Id1 and Id2 of when the currents Id1 and Id2 are individually generated by the bias voltage can be suppressed.

In the above-described second embodiment, the drain voltage of the output transistor <NUM> has been output as it is as the comparison result COMP. However, a logic gate such as an inverter can be further added at a subsequent stage of the output transistor <NUM>. A comparator <NUM> according to a sixth embodiment is different from the second embodiment in adding a logic gate.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the sixth embodiment of the present technology. The comparator <NUM> according to the sixth embodiment is different from the second embodiment in further including a NOR gate <NUM> and an inverter <NUM>.

The NOR gate <NUM> outputs a negative OR of a drain of an output transistor <NUM> and a control signal XEN to the inverter <NUM>. The inverter <NUM> inverts an output of the NOR gate <NUM> and outputs the inverted output to a counter <NUM> as a comparison result COMP. Note that the NOR gate <NUM> and the inverter <NUM> are examples of logic gates described in the claims.

With the above-described configuration, a voltage of a signal path (comparison result COMP) can be set to a power supply voltage level of a logic circuit. Furthermore, the logic of the output of the NOR gate <NUM> is fixed during an auto-zero period or between an AD conversion period at a reset level and an AD conversion period at a signal level. As a result, even when a drain voltage of the output transistor <NUM> is an intermediate voltage, a through current can be prevented from flowing through the third-stage NOR gate <NUM>.

Note that the sixth embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the sixth embodiment of the present technology, the NOR gate <NUM> and the inverter <NUM> are added to the subsequent stage of the output transistor <NUM>, and thus the logic of the output can be fixed during the auto-zero period and the like.

In the above-described second embodiment, only one stage of input-side clamp transistor has been arranged. However, in this configuration, an output amplitude of the input transistor <NUM> may be insufficient. A comparator <NUM> according to a seventh embodiment is different from the second embodiment in that input-side clamp transistors are arranged at two stages.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the seventh embodiment of the present technology. The comparator <NUM> according to the seventh embodiment is different from the second embodiment in further including an input-side clamp transistor <NUM>.

A pMOS transistor is used as the input-side clamp transistor <NUM>. Input-side clamp transistors <NUM> and <NUM> are connected in series between a drain and a source of an input transistor <NUM>.

By adding the input-side clamp transistor <NUM>, the output amplitude of the input transistor <NUM> becomes larger than the case of only the input-side clamp transistor <NUM>. With the configuration, a delay time until inversion of a comparison result COMP becomes long and noise can be reduced.

Note that the seventh embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the seventh embodiment of the present technology, the input-side clamp transistors <NUM> and <NUM> are connected in series between the drain and the source of the input transistor <NUM>, and thus the output amplitude of the input transistor <NUM> can be made large.

In the above-described second embodiment, the currents Id1 and Id2 have been supplied from the input-side current source <NUM> and the output-side current source <NUM>. However, in this configuration, these current amounts may become excessive. A comparator <NUM> according to an eighth embodiment is different from the second embodiment in adding a current source to suppress current amounts of currents Id1 and Id2.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the eighth embodiment of the present technology. The comparator <NUM> according to the eighth embodiment is different from the second embodiment in further including a pixel-side current source <NUM>.

The pixel-side current source <NUM> is connected between the vertical signal line VSL and the reference terminal. The current amounts of the currents Id1 and Id2 can be decreased by the amount of a current supplied by the pixel-side current source <NUM>.

Note that the eighth embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the eighth embodiment of the present technology, the pixel-side current source <NUM> is connected to a vertical signal line VSL, and thus the current amounts of the currents Id1 and Id2 can be suppressed.

In the above-described second embodiment, the pMOS transistor has been used as the input-side clamp transistor. However, an nMOS transistor can also be used. A comparator <NUM> according to the ninth embodiment is different from the second embodiment in using an nMOS transistor as an input-side clamp transistor.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the ninth embodiment of the present technology. The comparator <NUM> of the ninth embodiment is different from the second embodiment in including an input-side clamp transistor <NUM> instead of the input-side clamp transistor <NUM>. As the input-side clamp transistor <NUM>, an nMOS transistor is used. A gate and a drain of the input-side clamp transistor <NUM> are short-circuited.

Note that the ninth embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the ninth embodiment of the present technology, the input-side clamp transistor <NUM> is an nMOS transistor, and thus a lower limit of a drain voltage Vd can be limited by the nMOS transistor.

In the above-described ninth embodiment, the gate and the drain of the input-side clamp transistor <NUM> have been short-circuited. However, in this configuration, the lower-limit voltage limited by the input-side clamp transistor <NUM> is determined on the basis of a voltage of a vertical signal line VSL. For this reason, a margin of the lower-limit voltage for suppressing stop of supply of the current Id1 needs to be increased, and a dynamic range may be decreased by the margin. Furthermore, since an output amplitude of an input transistor <NUM> is small, noise easily becomes large. A comparator <NUM> according to a modification of the ninth embodiment is different from the ninth embodiment in limiting a lower limit of a drain voltage Vd by a bias voltage.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the modification of the ninth embodiment of the present technology. The comparator <NUM> according to the modification of the ninth embodiment is different from the ninth embodiment in that a bias voltage Vbias3 is applied to a gate of the input-side clamp transistor <NUM>.

By the application of the bias voltage Vbias3, the lower limit of the drain voltage Vd is limited regardless of the voltage of the vertical signal line VSL, and the stop of the supply of the current Id1 of the drain can be directly prevented.

Note that, in a case where the problems of the dynamic range and noise do not occur, a configuration without using a bias voltage can be adopted, as illustrated in <FIG>. In the configuration in <FIG>, the lower-limit voltage to be limited is linked with the voltage of the vertical signal line VSL, and thus dependence of a maximum amplitude of a gate-source voltage of the output transistor <NUM> on a signal level is suppressed, and a linearity error and a gain error can be decreased, as compared with the configuration in <FIG>.

As described above, according to the modification of the ninth embodiment, the lower limit of the drain voltage Vd is limited by the bias voltage, and thus the decrease in the dynamic range and deterioration of the noise can be suppressed.

In the above-described second embodiment, the input transistor <NUM> in the comparator <NUM> has been connected with the DAC <NUM> via the capacitor <NUM>. However, in this configuration, a kickback from the comparator <NUM> in a certain column to the DAC <NUM> may interfere with a column adjacent to the column via a signal line for transmitting the reference signal. A comparator <NUM> according to a tenth embodiment is different from the second embodiment in adding a buffer between a capacitor <NUM> and an DAC <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the tenth embodiment of the present technology. The comparator <NUM> according to the tenth embodiment is different from the second embodiment in further including a buffer <NUM>.

The buffer <NUM> is inserted between the DAC <NUM> and the capacitor <NUM>. Note that the buffer <NUM> is arranged for each column, but the arrangement is not limited to this configuration. For example, the buffer <NUM> can be arranged for each of a plurality of columns.

The buffer <NUM> can make a load of the comparator <NUM> invisible to the DAC <NUM>. Furthermore, a kickback from the comparator <NUM> in a certain column can be prevented from interfering with a column adjacent to the column via a signal line for transmitting a reference signal.

Note that the tenth embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the tenth embodiment of the present technology, the buffer <NUM> is inserted between the DAC <NUM> and the capacitor <NUM>, and thus the kickback of a certain column can be prevented from interfering with an adjacent column.

In the above-described second embodiment, the lower limit of the drain voltage Vd of the input transistor <NUM> has been limited by the input-side clamp transistor <NUM>. However, the state of the transistor constituting the output-side current source <NUM> becomes a non-conducting state due to the decrease in the drain voltage of the output transistor <NUM>, and the supply of the current Id2 may be stopped. A comparator <NUM> according to an eleventh embodiment is different from the second embodiment in adding an output-side clamp transistor to limit a lower limit of a drain voltage of an output transistor <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the eleventh embodiment of the present technology. The comparator <NUM> according to the eleventh embodiment is different from the second embodiment in further including an output-side clamp transistor <NUM>.

The output-side clamp transistor <NUM> is inserted between a source and a drain of an output transistor <NUM>. A pMOS transistor is used as the output-side clamp transistor <NUM>, and a gate of the output-side clamp transistor <NUM> is short-circuited with a drain of the output-side clamp transistor <NUM>. Furthermore, a back gate and the source of the output-side clamp transistor <NUM> are desirably short-circuited. By adding the output-side clamp transistor <NUM>, the decrease in the drain voltage of the output transistor <NUM> is suppressed, and stop of supply of a drain current Id2 can be prevented.

Note that the eleventh embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, the output-side clamp transistor <NUM> suppresses the decrease in the drain voltage of the output transistor <NUM>, and thus the stop of the supply of the drain current Id2 can be prevented.

In the above-described eleventh embodiment, the pMOS transistor has been used as the output-side clamp transistor. However, an nMOS transistor can also be used. A comparator <NUM> according to a modification of the eleventh embodiment is different from the eleventh embodiment in using an nMOS transistor as an output-side clamp transistor.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the modification of the eleventh embodiment of the present technology. The comparator <NUM> according to the modification of the eleventh embodiment is different from the eleventh embodiment in including an output-side clamp transistor <NUM> instead of the output-side clamp transistor <NUM>.

As the output-side clamp transistor <NUM>, an nMOS transistor is used. Furthermore, a predetermined bias voltage Vbias4 is applied to a gate of the output-side clamp transistor <NUM>.

Note that the gate and a drain of the output-side clamp transistor <NUM> in <FIG> can be short-circuited like the input-side clamp transistor <NUM> illustrated in <FIG>.

As described above, since the output-side clamp transistor <NUM> is an nMOS transistor in the modification of the eleventh embodiment of the present technology, the lower limit of the drain voltage of the output transistor <NUM> can be limited by the nMOS transistor.

In the above-described first embodiment, the input-side current source <NUM> has been connected to the drain of the input transistor <NUM>. However, in this configuration, when the input transistor <NUM> is in the non-conducting state, the drain voltage Vd is lowered, and the state of the transistor constituting the input-side current source <NUM> becomes a non-conducting state, and the supply of the drain current Id1 may be stopped. A comparator <NUM> according to a twelfth embodiment is different from the comparator <NUM> according to the first embodiment in preventing the stop of the supply of the drain current Id1 by adding a clamp switch.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the twelfth embodiment of the present technology. The comparator <NUM> according to the twelfth embodiment is different from the first embodiment in further including a clamp switch <NUM>.

The clamp switch <NUM> supplies a predetermined lower-limit voltage Vref to a connection node of a DAC <NUM> and a capacitor <NUM> according to a control signal clampSW from a timing control unit <NUM>.

<FIG> is a timing chart illustrating an example of variation in input and output signals of the comparator <NUM> according to the twelfth embodiment of the present technology. The timing control unit <NUM> supplies the control signal clampSW over a pulse period from timing T4. The clamp switch <NUM> is controlled to be in a closed state by the control signal clampSW. As a result, the lower-limit voltage Vref is supplied, the input transistor <NUM> is turned on regardless of an input voltage VVSL, and a decrease in a drain voltage Vd can be suppressed.

As described above, according to the twelfth embodiment of the present technology, the clamp switch <NUM> suppresses the decrease in the drain voltage Vd, thereby preventing stop of supply of a drain current Id1.

In the above-described second embodiment, the input-side clamp transistor <NUM> has been inserted between the source and the drain of the input transistor <NUM> to limit the lower limit of the drain voltage Vd. However, adjustment of the lower-limit voltage may be difficult only with the input-side clamp transistor <NUM>. A comparator <NUM> according to a thirteenth embodiment is different from the second embodiment in adjusting a lower-limit voltage with a resistive element.

<FIG> is a circuit diagram illustrating a configuration example of the comparator <NUM> according to the thirteenth embodiment of the present technology. The comparator <NUM> according to the thirteenth embodiment is different from the second embodiment in further including a resistive element <NUM>.

An input-side clamp transistor <NUM> and the resistive element <NUM> are connected in series between a source and a drain of an input transistor <NUM>. This resistive element <NUM> may be a variable resistive element. In the case of being adopted as the variable resistive element, a resistance value of the variable resistive element is held in a register or the like. By adjusting the resistance value of the resistive element <NUM>, a lower-limit voltage to be limited can be set to an optimum value. Furthermore, the resistive element <NUM> may be mounted by using an active element as the resistive element.

Note that the thirteenth embodiment can be applied to the respective embodiments other than the second embodiment and modifications of the embodiments.

As described above, according to the thirteenth embodiment of the present technology, the resistive element <NUM> is added, and thus the lower-limit voltage can be set to the optimum value by adjusting the resistance value of the resistive element <NUM>.

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving bodies including an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

<FIG> is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applicable.

A vehicle control system <NUM> includes a plurality of electronic control units connected through a communication network <NUM>. In the example illustrated in <FIG>, the vehicle control system <NUM> includes a drive system control unit <NUM>, a body system control unit <NUM>, a vehicle exterior information detection unit <NUM>, a vehicle interior information detection unit <NUM>, and an integrated control unit <NUM>. Furthermore, as functional configurations of the integrated control unit <NUM>, a microcomputer <NUM>, a sound image output unit <NUM>, and an in-vehicle network interface (I/F) <NUM> are illustrated.

The drive system control unit <NUM> controls operations of devices regarding a drive system of a vehicle according to various programs. For example, the drive system control unit <NUM> functions as a control device of a drive force generation device for generating drive force of a vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to wheels, a steering mechanism that adjusts a steering angle of a vehicle, a braking device that generates braking force of a vehicle, and the like.

The body system control unit <NUM> controls operations of various devices equipped in a vehicle body according to various programs. For example, the body system control unit <NUM> functions as a control device of a keyless entry system, a smart key system, an automatic window device, and various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a mobile device substituted for a key or signals of various switches can be input to the body system control unit <NUM>. The body system control unit <NUM> receives an input of the radio waves or the signals, and controls a door lock device, the automatic window device, the lamps, and the like of the vehicle.

The vehicle exterior information detection unit <NUM> detects information outside the vehicle that mounts the vehicle control system <NUM>. For example, an imaging unit <NUM> is connected to the vehicle exterior information detection unit <NUM>. The vehicle exterior information detection unit <NUM> causes the imaging unit <NUM> to image an image outside the vehicle, and receives the imaged image. The vehicle exterior information detection unit <NUM> may perform object detection processing or distance detection processing of persons, vehicles, obstacles, signs, letters on a road surface, or the like on the basis of the received image.

The imaging unit <NUM> is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit <NUM> can output the electrical signal as an image and can output the electrical signal as information of distance measurement. Furthermore, the light received by the imaging unit <NUM> may be visible light or may be non-visible light such as infrared light.

The vehicle interior information detection unit <NUM> detects information inside the vehicle. A driver state detection unit <NUM> that detects a state of a driver is connected to the vehicle interior information detection unit <NUM>, for example. The driver state detection unit <NUM> includes a camera that captures the driver, for example, and the vehicle interior information detection unit <NUM> may calculate the degree of fatigue or the degree of concentration of the driver, or may determine whether or not the driver falls asleep on the basis of the detection information input from the driver state detection unit <NUM>.

The microcomputer <NUM> calculates a control target value of the drive power generation device, the steering mechanism, or the braking device on the basis of the information outside and inside the vehicle acquired in the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM>, and can output a control command to the drive system control unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control for the purpose of realization of an advanced driver assistance system (ADAS) function including collision avoidance or shock mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintaining travel, collision warning of the vehicle, lane out warning of the vehicle, and the like.

Furthermore, the microcomputer <NUM> controls the drive force generation device, the steering mechanism, the braking device, or the like on the basis of the information of a vicinity of the vehicle acquired in the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM> to perform cooperative control for the purpose of automatic drive of autonomous travel without depending on an operation of the driver or the like.

Furthermore, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information outside the vehicle acquired in the vehicle exterior information detection unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control for the purpose of achievement of non-glare such as by controlling the head lamps according to the position of a leading vehicle or an oncoming vehicle detected in the vehicle exterior information detection unit <NUM>, and switching high beam light to low beam light.

The sound image output unit <NUM> transmits an output signal of at least one of a sound or an image to an output device that can visually and aurally notify a passenger of the vehicle or an outside of the vehicle of information. In the example in <FIG>, as the output device, an audio speaker <NUM>, a display unit <NUM>, and an instrument panel <NUM> are exemplarily illustrated. The display unit <NUM> may include, for example, at least one of an on-board display or a head-up display.

<FIG> is a diagram illustrating an example of an installation position of the imaging unit <NUM>.

In <FIG>, imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are included as the imaging unit <NUM>.

The imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are provided at positions such as a front nose, side mirrors, a rear bumper or a back door, and an upper portion of a windshield in an interior of the vehicle <NUM>, for example. The imaging unit <NUM> provided at the front nose and the imaging unit <NUM> provided at an upper portion of the windshield in an interior of the vehicle mainly acquire front images of the vehicle <NUM>. The imaging units <NUM> and <NUM> provided at the side mirrors mainly acquire side images of the vehicle <NUM>. The imaging unit <NUM> provided at the rear bumper or the back door mainly acquires a rear image of the vehicle <NUM>. The imaging unit <NUM> provided at the upper portion of the windshield in the interior of the vehicle is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that <FIG> illustrates an example of capture ranges of the imaging units <NUM> to <NUM>. An imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided at the front nose, imaging ranges <NUM> and <NUM> respectively indicate the imaging ranges of the imaging units <NUM> and <NUM> provided at the side mirrors, and an imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided at the rear bumper or the back door. For example, a bird's-eye view image of the vehicle <NUM> as viewed from above can be obtained by superimposing image data captured by the imaging units <NUM> to <NUM>.

At least one of the imaging units <NUM> to <NUM> may have a function to acquire distance information. For example, at least one of the imaging units <NUM> to <NUM> may be a stereo camera including a plurality of imaging elements or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> obtains distances to three-dimensional objects in the imaging ranges <NUM> to <NUM> and temporal change of the distances (relative speeds to the vehicle <NUM>) on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, thereby to extract particularly a three-dimensional object closest to the vehicle <NUM> on a traveling road and traveling at a predetermined speed (for example, <NUM>/h or more) in substantially the same direction as the vehicle <NUM> as a leading vehicle. Moreover, the microcomputer <NUM> can set an inter-vehicle distance to be secured from the leading vehicle in advance and perform automatic braking control (including following stop control) and automatic acceleration control (including following start control), and the like. In this way, the cooperative control for the purpose of automatic drive of autonomous travel without depending on an operation of the driver or the like can be performed.

For example, the microcomputer <NUM> classifies three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, and other three-dimensional objects such as electric poles to be extracted, on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, and can use the data for automatic avoidance of obstacles. For example, the microcomputer <NUM> discriminates obstacles around the vehicle <NUM> into obstacles visually recognizable by the driver of the vehicle <NUM> and obstacles visually unrecognizable by the driver. Then, the microcomputer <NUM> determines a collision risk indicating a risk of collision with each of the obstacles, and can perform drive assist for collision avoidance by outputting warning to the driver through the audio speaker <NUM> or the display unit <NUM>, and performing forced deceleration or avoidance steering through the drive system control unit <NUM>, in a case where the collision risk is a set value or more and there is a collision possibility.

At least one of the imaging units <NUM> to <NUM> may be an infrared camera that detects infrared light. For example, the microcomputer <NUM> determines whether or not a pedestrian exists in the imaged images of the imaging units <NUM> to <NUM>, thereby to recognize the pedestrian. Such recognition of a pedestrian is performed by a process of extracting characteristic points in the imaged images of the imaging units <NUM> to <NUM>, as the infrared camera, for example, and by a process of performing pattern matching processing for the series of characteristic points indicating a contour of an object and discriminating whether or not the object is a pedestrian. When the microcomputer <NUM> determines that a pedestrian exists in the imaged images of the imaging units <NUM> to <NUM> and recognizes the pedestrian, the sound image output unit <NUM> causes the display unit <NUM> to superimpose and display a square contour line for emphasis on the recognized pedestrian. Furthermore, the sound image output unit <NUM> may cause the display unit <NUM> to display an icon or the like representing the pedestrian at a desired position.

Claim 1:
A comparator (<NUM>) comprising:
a first input configured to receive a pixel signal (VVSL) ;
a second input configured to receive a reference signal (VRPM);
a first transistor (<NUM>), wherein a gate of the first transistor is coupled to the second input and a source of the first transistor (<NUM>) is connected to the first input;
a second transistor (<NUM>), wherein a gate of the second transistor (<NUM>) is coupled to a drain of the first transistor (<NUM>) and a source of the second transistor (<NUM>) is connected to the first input;
a current source (<NUM>) is inserted between a reference/supply terminal and the drain of the first transistor (<NUM>);
a current source (<NUM>) is inserted between a reference/supply terminal and the drain of the second transistor (<NUM>); and
a channel conductivity type of the first transistor (<NUM>) corresponds to the channel conductivity type of the second transistor (<NUM>).