Patent Description:
The through silicon via (TSV) technology is a high-density packaging technology, and a fourth packaging technology as a promising replacement for mature wire bonding. The TSV technology implements the vertical electrical interconnection by filling conductive materials such as copper, tungsten and polycrystalline silicon. It can transmit a signal from one side of the chip to the other side of the chip and implement three-dimensional (3D) integration for multiple layers of chips in combination with chip stacking. The TSV technology is an important development trend of the semiconductors in the future. Through the vertical interconnection, it can effectively shorten the interconnecting line between chips and reduce the signal delay to achieve the better signal transmission performance, higher working frequency, wider broadband and higher device integration of the electronic system.

A TSV process mainly includes deep silicon etching for forming micro holes, deposition of an insulating layer/a barrier layer/a seed layer, deep hole filling, chemical-mechanical polishing (CMP), thinning, pad manufacturing, re-distribution line manufacturing, etc. The conventional TSV process is implemented by forming a TSV in a front side of the chip, establishing metal interconnection at the front side of the chip to form electrical connection, thinning the semiconductor chip, and leading out an electrode from a back side of the chip.

However, for the conventional TSV process in which the TSV is only formed in one chip, when two or more chips are bonded together, adjacent chips are connected electrically by an additional conductive structure (such as a solder ball or a conductive bump) to make the structure and manufacturing process more complicated. Background may be found in <CIT> and <CIT>.

In view of the problems in the background art, there is a need to provide a semiconductor structure and a manufacturing method thereof to implement metal interconnection without an additional solder ball.

By forming the TSV penetrating through the second chip and a part of the first chip, and forming the conductive layer in the TSV, the manufacturing method of a semiconductor structure in the present application can implement electrical connection between the metal layers in the first chip and the second chip without an additional conductive structure, and thus can simplify the semiconductor structure and the process steps. With the inclined sidewall of the second part, the manufacturing method only forms the insulating layer on the sidewall of the first part to simplify the process steps and reduce the cost.

With the TSV penetrating through the second chip and a part of the first chip, and the conductive layer in the TSV, the semiconductor structure in the present application can implement electrical connection between the metal layers in the first chip and the second chip without an additional conductive structure, and thus the semiconductor structure and the process steps are simplified. With the inclined sidewall of the second part, the semiconductor structure only forms the insulating layer on the sidewall of the first part to simplify the process steps and reduce the cost.

To describe the technical solutions in the embodiments of the present application or in the conventional art more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the conventional art.

Reference numerals:
<NUM>. first chip, <NUM>. substrate, <NUM>. dielectric layer, <NUM>. metal layer, <NUM>. pad, <NUM>. second chip, <NUM>. first part, <NUM>. second part, <NUM>. insulating layer, <NUM>. conductive layer, <NUM>. bonding layer, <NUM>. solder ball, and <NUM>. insulating material layer.

To facilitate the understanding of the present application, the present application will be described more completely below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the accompanying drawings.

The embodiments are provided to make the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present application.

It should be understood that when an element or a layer is described as "being on", "being adjacent to", "being connected to" or "being coupled to" another element or layer, it can be on, adjacent to, connected to, or coupled to the another element or layer directly, or intervening elements or layers may be present. On the contrary, when an element is described as "being directly on", "being directly adjacent to", "being directly connected to" or "being directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first and second may be used to describe various elements, components, regions, layers, doped types and/or sections, these elements, components, regions, layers, doped types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doped type or section from another element, component, region, layer, doped type or section. Thus, a first element, component, region, layer, doped type or section discussed below may be termed a second element, component, region, layer or section without departing from the teachings of the present application. For example, the first chip may become the second chip; and similarly, the second chip may become the first chip. The first chip and the second chip are different chips.

Spatial relationship terms such as "under", "beneath", "lower", "below", "above", and "upper" can be used herein to describe the relationship shown in the figure between one element or feature and another element or feature. It should be understood that in addition to the orientations shown in the figure, the spatial relationship terms further include different orientations of used and operated devices. For example, if a device in the accompanying drawings is turned over and described as being "beneath another element", "below it", or "under it", the device or feature is oriented "on" the another element or feature. Therefore, the exemplary terms "beneath" and "under" may include two orientations of above and below. In addition, the device may further include other orientations (for example, a rotation by <NUM> degrees or other orientations), and the spatial description used herein is interpreted accordingly.

In this specification, the singular forms of "a", "an" and "the" may also include plural forms, unless clearly indicated otherwise. It should also be understood that terms "include" and/or "comprise", when used in this specification, may determine the presence of features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups. In this case, in this specification, the term "and/or" includes any and all combinations of related listed items.

Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic diagrams of idealized embodiments (and intermediate structures) of the present application, such that variations shown in the shapes can be contemplated due to, for example, manufacturing techniques and/or tolerances. Therefore, the embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing technologies. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and limit the scope of the present application.

<FIG> shows a conventional semiconductor structure. The conventional semiconductor structure includes a stacked structure, a TSV <NUM>', an insulating layer <NUM>' and a conductive layer <NUM>'. The stacked structure includes a first chip <NUM>' and a second chip <NUM>'. The second chip <NUM>' is bonded onto the first chip <NUM>' in an F2F manner through a bonding layer <NUM>'. The first chip <NUM>' and the second chip <NUM>' each include a substrate <NUM>', a dielectric layer <NUM>' on the substrate <NUM>' and a metal layer <NUM>' in the dielectric layer <NUM>'. The TSV <NUM>' penetrates through the substrate <NUM>' of the second chip <NUM>' and the dielectric layer <NUM>' of the second chip <NUM>'. The insulating layer <NUM>' is located on a sidewall of a first part <NUM>'. The conductive layer <NUM>' is located in the TSV <NUM>' and fills up the TSV <NUM>'. The conductive layer <NUM>' is electrically connected to the penetrated metal layer <NUM>' in each of the first chip <NUM>' and the second chip <NUM>'. However, as the TSV <NUM>' is only located in the second chip <NUM>' in the conventional semiconductor structure shown in <FIG>, there is a need for an additional solder ball <NUM>' to establish the metal interconnection, and thus the manufacturing process is complicated.

Referring to <FIG>, the present application provides a manufacturing method of a semiconductor structure, including the following steps:.

By forming the TSV penetrating through the second chip and a part of the first chip, and forming the conductive layer in the TSV, the manufacturing method of a semiconductor structure in the present application can implement electrical connection between the metal layers in the first chip and the second chip without an additional conductive structure, and thus can simplify the semiconductor structure and the process steps. With the inclined sidewall of the second part, the manufacturing method only forms the insulating layer on the sidewall of the first part to simplify the process steps and reduce the cost. In addition, by bonding the second chip onto the first chip in the F2F manner, the structure obtained further has the advantages of the high precision, small size of the stacked structure, high input/output (I/O) density, short interconnecting line, small parasitic parameter of the lead, etc..

Preferably, the bonding between the first chip and the second chip may be implemented with wafer level packaging (WLP) such as wafer on wafer (WOW) or chip on wafer (COW), and may also be implemented with chip scale package (CSP).

Preferably, in a manufacturing method provided by some embodiments, the sidewall of the second part may have an inclination angle of <NUM>-<NUM>° with respect to a surface of the substrate, such as <NUM>°, <NUM>°, <NUM>°, <NUM>° or <NUM>°. In a manufacturing method provided by some embodiments, the TSV may have a depth of <NUM>-<NUM>, such as <NUM>, <NUM>, <NUM> or <NUM>. In a manufacturing method provided by some embodiments, the TSV may have a width of <NUM>-<NUM>, such as <NUM>, <NUM>, <NUM>, <NUM> or <NUM>. In the manufacturing method of a semiconductor structure provided by the present application, there are no limits made on the specific inclination angle of the sidewall of the second part with respect to the surface of the substrate, the specific depth of the TSV and the specific width of the TSV.

In Step S1, referring to S1 in <FIG> and <FIG>, a stacked structure is provided. The stacked structure includes a first chip <NUM> and a second chip <NUM>. The second chip <NUM> is bonded onto the first chip <NUM> in an F2F manner. The first chip <NUM> and the second chip <NUM> each include a substrate <NUM>, a dielectric layer <NUM> on the substrate <NUM> and a metal layer <NUM> in the dielectric layer <NUM>.

Referring also to <FIG>, in an embodiment, Step S1 may include the following steps:.

In an embodiment, the substrate <NUM> may include, but is not limited to, a silicon substrate, a silicon nitride substrate or a silicon oxynitride substrate. The dielectric layer <NUM> may include, but is not limited to, a silicon dioxide layer or a silicon nitride layer. There are no limits made on the material of the substrate <NUM> and the dielectric layer <NUM> in the present application.

Specifically, the dielectric layer <NUM> may be located at a front side of the substrate <NUM>. The so-called term "F2F" means that after the second chip <NUM> is bonded onto the first chip <NUM>, the dielectric layer <NUM> of the second chip <NUM> and the dielectric layer <NUM> of the first chip <NUM> are bonded together, as shown in <FIG>. It can be considered that the front side of the first chip <NUM> is upward, and the second chip <NUM> with the downward front side is bonded onto the first chip <NUM>.

Referring also to <FIG>, in an embodiment, the first chip <NUM> and the second chip <NUM> each may further include a pad <NUM>. The pad <NUM> is located at a side of the metal layer <NUM> away from the substrate <NUM>. In the above embodiment, the TSV <NUM> further penetrates through the pad <NUM> in the first chip <NUM> and the pad <NUM> in the second chip <NUM>.

In an embodiment, a through via (not shown) may be reserved in the metal layer <NUM> and the pad <NUM> separately. The through via corresponds to the subsequent TSV <NUM> and becomes a part of the TSV <NUM> upon formation of the TSV <NUM>.

According to the manufacturing method of a semiconductor structure provided by the above embodiment, the through via is reserved in the metal layer <NUM> and the pad <NUM> separately. The reserved through via is filled with the dielectric layer <NUM> when the dielectric layer <NUM> covering the metal layer <NUM> and the pad <NUM> is formed. Consequently, during the subsequent formation of the TSV <NUM>, the etching step upon the etching of the substrate <NUM> is to etch the dielectric layer <NUM>, rather than to alternately etch the dielectric layer <NUM> and the metal layer <NUM> or the pad <NUM>, thus simplifying the process steps and improving the production efficiency.

Preferably, the pad <NUM> may include, but is not limited to, a copper pad. There are no limits made on the material of the pad <NUM> in the present application.

In Step S2, referring to S2 in <FIG> and <FIG>, a TSV <NUM> is formed in the stacked structure. The TSV <NUM> includes a first part <NUM> and a second part <NUM> communicating with the first part <NUM>. The first part <NUM> penetrates through the substrate <NUM> of the second chip <NUM>. A sidewall of the first part <NUM> is a vertical sidewall. The second part <NUM> penetrates through the metal layer <NUM> of the second chip <NUM> and at least a part of the metal layer <NUM> in the first chip <NUM>. A sidewall of the second part <NUM> is an inclined sidewall. A bottom of the second part <NUM> is narrower than a top of the second part <NUM>.

Referring also to <FIG>, in an embodiment, Step S2 may include the following step:
Etch the first chip <NUM> and the second chip <NUM> to form the TSV <NUM>.

Referring to <FIG>, in an embodiment, the second chip <NUM> may be bonded onto the first chip <NUM> through a bonding layer <NUM>. In the above embodiment, the TSV <NUM> may further penetrate through the bonding layer <NUM>.

In an embodiment, the bonding layer <NUM> may include, but is not limited to, an aluminum/copper composite layer. There are no limits made on the material and structure of the bonding layer <NUM> in the present application.

Due to a high-temperature working environment, the stable performance of the system is restricted by the conventional aluminum wire. The copper metal has the advantages of better thermal conductivity, better electrical conductivity and lower thermal expansion coefficient than the aluminum metal, but copper wire bonding is hardly applied to the semiconductors. The manufacturing method of a semiconductor structure provided by the above embodiment takes the aluminum/copper composite layer as the bonding layer <NUM>, in which the aluminum metal can provide the desirable bonding, while the copper metal can provide the desirable electrical, mechanical and thermal properties.

In an embodiment, in the step of etching the first chip <NUM> and the second chip <NUM> to form the TSV <NUM>, dry etching may be used to etch the first chip <NUM> and the second chip <NUM> to form the TSV <NUM>.

In an embodiment, after the dry etching is used to etch the first chip <NUM> and the second chip <NUM> to form the TSV <NUM>, the stacked structure may further be etched with wet etching to widen the TSV <NUM>, thus fully exposing the pad <NUM> in each of the first chip <NUM> and the second chip <NUM>.

In Step S3, referring to S3 in <FIG> and <FIG>, an insulating layer <NUM> is formed on the sidewall of the first part <NUM>.

As shown in <FIG>, in an embodiment, Step S3 may include the following steps:.

According to the manufacturing method of a semiconductor structure provided by the above embodiment, with the inclined sidewall of the second part, the insulating material layer on the sidewall and the bottom of the second part can be removed directly, and the insulating layer is only formed on the sidewall of the first part. Therefore, the structure obtained can directly form electrical connection between the metal layers in the first chip and the second chip through the conductive layer in the TSV without an additional solder ball or distribution line, thus simplifying the process steps and reducing the cost.

In an embodiment, the insulating material layer <NUM> may include, but is not limited to, an oxide layer. There are no limits made on the material and structure of the insulating material layer <NUM> in the present application.

In Step S302, referring to S302 in <FIG> and <FIG>, the insulating material layer <NUM> on the sidewall and the bottom of the second part <NUM> is removed, the remaining insulating material layer <NUM> on the sidewall of the first part <NUM> being the insulating layer <NUM>.

In an embodiment, the insulating material layer <NUM> on the sidewall and the bottom of the second part <NUM> may be removed with, but not limited to, the dry etching.

In an embodiment, after Step S302, the stacked structure may further be etched with the wet etching to widen the TSV <NUM>, thus fully exposing the pad <NUM> in each of the first chip <NUM> and the second chip <NUM>.

In Step S4, referring to S4 in <FIG> and <FIG>, a conductive layer <NUM> is formed in the TSV <NUM>. The conductive layer <NUM> is electrically connected to the penetrated metal layer <NUM> in each of the first chip <NUM> and the second chip <NUM>.

As shown in <FIG>, in an embodiment, Step S4 may further include the following steps:.

It should be understood that although the steps in the flowcharts of <FIG>, <FIG> and <FIG> are shown in sequence according to the arrows, these steps are unnecessarily executed in the sequence indicated by the arrows. The execution order of these steps is not strictly limited, and these steps may be executed in other orders, unless clearly described otherwise. Moreover, at least one of the steps in <FIG>, <FIG> and <FIG> may include a plurality of steps or stages. The steps or stages are unnecessarily executed at the same time, but may be executed at different times. The execution order of the steps or stages is unnecessarily carried out sequentially, but may be executed alternately with other steps or at least one of the steps or stages of other steps.

Referring also to <FIG>, the present application further provides a semiconductor structure, including a stacked structure, a TSV <NUM>, an insulating layer <NUM> and a conductive layer <NUM>. The stacked structure includes a first chip <NUM> and a second chip <NUM>. The second chip <NUM> is bonded onto the first chip <NUM> in an F2F manner. The first chip <NUM> and the second chip <NUM> each include a substrate <NUM>, a dielectric layer <NUM> on the substrate <NUM> and a metal layer <NUM> in the dielectric layer <NUM>. The TSV <NUM> includes a first part <NUM> and a second part <NUM> communicating with the first part <NUM>. The first part <NUM> penetrates through the substrate <NUM> of the second chip <NUM>. A sidewall of the first part <NUM> is a vertical sidewall. The second part <NUM> penetrates through the metal layer <NUM> of the second chip <NUM> and at least a part of the metal layer <NUM> in the first chip <NUM>. A sidewall of the second part <NUM> is an inclined sidewall. A bottom of the second part <NUM> is narrower than a top of the second part <NUM>. The insulating layer <NUM> is located on the sidewall of the first part <NUM>. The conductive layer <NUM> is located in the TSV <NUM> and fills up the TSV <NUM>. The conductive layer <NUM> is electrically connected to the penetrated metal layer <NUM> in each of the first chip <NUM> and the second chip <NUM>.

With the TSV penetrating through the second chip and a part of the first chip, and the conductive layer in the TSV, the semiconductor structure in the present application can implement electrical connection between the metal layers in the first chip and the second chip without an additional conductive structure, and thus the semiconductor structure and the process steps can be simplified. With the inclined sidewall of the second part, the semiconductor only forms the insulating layer on the sidewall of the first part to simplify the process steps and reduce the cost.

In an embodiment, the substrate <NUM> may include, but is not limited to, a silicon substrate, a sapphire substrate, a silicon nitride substrate or a silicon oxynitride substrate. The dielectric layer <NUM> may include, but is not limited to, a silicon dioxide layer or a silicon nitride layer. There are no limits made on the material of the substrate <NUM> and the dielectric layer <NUM> in the present application.

Referring also to <FIG>, in an embodiment, the first chip <NUM> and the second chip <NUM> each may further include a pad <NUM>. Specifically, the pad <NUM> may be located at a side of the metal layer <NUM> away from the substrate <NUM>. The pad <NUM> may include, but is not limited to, a copper pad. There are no limits made on the material of the pad <NUM> in the present application.

On the basis of the above embodiment, the TSV <NUM> further penetrates through the pad <NUM> in the first chip <NUM> and the pad <NUM> in the second chip <NUM>.

Preferably, in a semiconductor structure provided by some embodiments, the sidewall of the second part may have an inclination angle of <NUM>-<NUM>° with respect to a surface of the substrate, such as <NUM>°, <NUM>, <NUM>°, <NUM>° or <NUM>°. In a semiconductor structure provided by some embodiments, the TSV may have a depth of <NUM>-<NUM>, such as <NUM>, <NUM>, <NUM> or <NUM>. In a semiconductor structure provided by some embodiments, the TSV may have a width of <NUM>-<NUM>, such as <NUM>, <NUM>, <NUM>, <NUM> or <NUM>. In the semiconductor structure provided by the present application, there are no limits made on the specific inclination angle of the sidewall of the second part with respect to the surface of the substrate, the specific depth of the TSV and the specific width of the TSV.

Referring also to <FIG>, in an embodiment, the semiconductor structure may further include a bonding layer <NUM>. Specifically, the bonding layer <NUM> is located between the first chip <NUM> and the second chip <NUM>, and contacts the dielectric layer <NUM> of the first chip <NUM> and the dielectric layer <NUM> of the second chip <NUM>. The bonding layer <NUM> may include, but is not limited to, an aluminum/copper composite layer. There are no limits made on the material and structure of the bonding layer <NUM> in the present application.

In an embodiment, the conductive layer <NUM> may include a metal barrier layer and a filling conductive layer. The metal barrier layer is located on a surface of the insulating layer and on the sidewall and the bottom of the second part. The filling conductive layer is located on a surface of the metal barrier layer and fills up the TSV <NUM>.

In an embodiment, the metal barrier layer may include, but is not limited to, a tantalum layer, and a metal barrier layer made of other materials or a stacked structure thereof. There are no limits made on the material and form of the metal barrier layer.

In an embodiment, the insulating layer <NUM> may include, but is not limited to, a pad oxide layer.

Claim 1:
A manufacturing method of a semiconductor structure, comprising:
providing a stacked structure, wherein the stacked structure comprises a first chip (<NUM>) and a second chip (<NUM>), the second chip (<NUM>) is bonded onto the first chip (<NUM>)in a face-to-face (F2F) manner, and the first chip (<NUM>) and the second chip (<NUM>)each comprise a substrate (<NUM>), a dielectric layer (<NUM>)on the substrate (<NUM>) and a metal layer (<NUM>) in the dielectric layer (<NUM>) (S1);
forming a through silicon via (TSV) (<NUM>) in the stacked structure, wherein the TSV (<NUM>) comprises a first part (<NUM>) and a second part (<NUM>) communicating with the first part (<NUM>); the first part (<NUM>) penetrates through the substrate (<NUM>) of the second chip (<NUM>); a sidewall of the first part (<NUM>) is a vertical sidewall; the second part (<NUM>) penetrates through the metal layer (<NUM>) of the second chip (<NUM>) and at least a part of the metal layer (<NUM>) in the first chip (<NUM>); a sidewall of the second part (<NUM>) is an inclined sidewall; and a bottom of the second part (<NUM>) is narrower than a top of the second part (<NUM>) (S2);
forming an insulating layer (<NUM>) on the sidewall of the first part (<NUM>) (S3); and
forming a conductive layer (<NUM>) in the TSV(<NUM>), the conductive layer (<NUM>) being electrically connected to the penetrated metal layer (<NUM>) in each of the first chip (<NUM>) and the second chip (<NUM>) (S4);
characterized in that,
forming an insulating layer (<NUM>) on the sidewall of the first part (<NUM>) (S3) comprises:
forming an insulating material layer (<NUM>) on a sidewall and a bottom of the TSV (<NUM>); and
removing the insulating material layer (<NUM>) on the sidewall and the bottom of the second part (<NUM>) with dry etching, the remaining insulating material layer (<NUM>) on the sidewall of the first part (<NUM>) being the insulating layer (<NUM>).