Patent Description:
In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages, and operation, etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice embodiments of the present disclosure. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of a computer system haven't been described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure.

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™ and may also be used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a 'green technology' future balanced with performance considerations.

As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the present disclosure.

Referring to <FIG>, an embodiment of a fabric composed of point-to-point Links that interconnect a set of components is illustrated. System <NUM> includes processor <NUM>, controller hub <NUM>, and system memory <NUM> coupled to controller hub <NUM>. Processor <NUM> includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor <NUM> is coupled to controller hub <NUM> through front-side buses (FSB) <NUM>, respectively. It should be appreciated that, in some embodiments, the computing system <NUM> may include more or fewer processors. In computing systems <NUM> with more processors, each pair of processors may be connected by a link <NUM>. In one embodiment, FSB <NUM> is a serial point-to-point interconnect as described below. In another embodiment, link <NUM> includes a serial, differential interconnect architecture that is compliant with different interconnect standard, such as a Quick Path Interconnect (QPI) or an Ultra Path Interconnect (UPI). In some implementations, the system may include logic to implement multiple protocol stacks and further logic to negotiation alternate protocols to be run on top of a common physical layer, among other example features.

System memory <NUM> includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system <NUM>. In the illustrative embodiment, the system memory <NUM> is coupled to the controller hub <NUM>. Additionally or alternatively, in some embodiments, the system memory <NUM> is coupled to processor <NUM> though a memory interface. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub <NUM> is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub <NUM> include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processors <NUM>, while controller <NUM> is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex <NUM>.

The controller hub <NUM> also includes an input/output memory management unit (IOMMU) <NUM>. In some embodiments, the IOMMU <NUM> may be referred to as a translation agent. In the illustrative embodiment, the IOMMU <NUM> forms part of the controller hub <NUM>. Additionally or alternatively, in some embodiments, some or all of the IOMMU <NUM> may be a separate component from the controller hub <NUM>. The IOMMU <NUM> can include hardware circuitry, software, or a combination of hardware and software. The IOMMU <NUM> can be used to provide address translation services (ATS) for address spaces in the memory <NUM> to allow one or more of the offload devices <NUM> to perform memory transactions to satisfy job requests issued by the host system.

Here, controller hub <NUM> is coupled to switch/bridge <NUM> through serial link <NUM>. Input/output modules <NUM> and <NUM>, which may also be referred to as interfaces/ports <NUM> and <NUM>, include/implement a layered protocol stack to provide communication between controller hub <NUM> and switch <NUM>. In one embodiment, multiple devices are capable of being coupled to switch <NUM>. In some embodiments, the port <NUM> may be referred to as a root port <NUM>.

Switch/bridge <NUM> routes packets/messages from offload device <NUM> upstream, i.e., up a hierarchy towards a root complex, to controller hub <NUM> and downstream, i.e., down a hierarchy away from a root controller, from processor <NUM> or system memory <NUM> to offload device <NUM>. Switch <NUM>, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Offload device <NUM> includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, an accelerator device, a field programmable gate array (FPGA), an application specific integrated circuit, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, offload device <NUM> may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

Graphics accelerator <NUM> is also coupled to controller hub <NUM> through serial link <NUM>. In one embodiment, graphics accelerator <NUM> is coupled to an MCH, which is coupled to an ICH. Switch <NUM>, and accordingly offload device <NUM>, is then coupled to the ICH. I/O modules <NUM> and <NUM> are also to implement a layered protocol stack to communicate between graphics accelerator <NUM> and controller hub <NUM>. Similar to the MCH discussion above, a graphics controller or the graphics accelerator <NUM> itself may be integrated in processor <NUM>. Further, one or more links (e.g., <NUM>) of the system can include one or more extension devices (e.g., <NUM>), such as retimers, repeaters, etc..

In use, in some embodiments, the offload device <NUM> (or any other device connected to the processor <NUM>, such as the graphics accelerator <NUM>) may support different domains. For example, the offload device <NUM> may support multiple virtualized functions, each of which corresponds to a different domain. In one example, the offload devices <NUM> may support different tenants of a single root I/O virtualization (SR-IOV) offload device. The different domains may share physical memory (e.g., on the offload device <NUM> or on the system memory <NUM>). The offload device <NUM> can send and receive various messages across the link <NUM> and, after going through the switch <NUM>, the link <NUM> such as memory transactions, cache coherency messages, etc. In order to enforce isolation between the tenants, messages such as memory requests may include a domain identifier that identifies, e.g., a particular virtual function associated with the message.

Messages on the link <NUM> may include untranslated addresses, such as a guest virtual address (GVA), guest physical address (GPA) or IO virtual address (IOVA) or may include a translated address, such as a host physical address (HPA). For untranslated addresses, an IOMMU <NUM> performs address translation from GPA, GPA or IOVA to HPA to allow the offload device access to system memory <NUM>.

For example, in one embodiment, an Address Translation Service (ATS) on the IOMMU <NUM> may allow the offload device <NUM> to cache a translated address (i.e., an HPA) in a device translation lookaside buffer to improve performance, such as by avoiding or reducing use of the inline use of the IOMMU translation capabilities. ATS allows devices to support shared virtual memory, and support protocols such as coherent caches that operate in the physical address domain (such as Compute Express Link (CXL) cache, or CXL. A Secure ATS service on the IOMMU <NUM> can enforce isolation of the physical addresses that a device can access using a physical-indexed table that contains permissions for each page. The table can be set up on a per-domain basis (e.g., for each virtual machine in a virtual environment or for each process in a non-virtual environment). Services such as a secure ATS can benefit from having access to a domain identifier for each message being processed. For example, a message trying to access a physical memory address included in the message may be permitted or not permitted based on the domain associated with the message and the physical memory address.

As such, an indicator of a domain may be included in messages sent on the link <NUM>. One approach would be to include all the data needed to identify the domain in a header of each message of a link protocol. However, if the message size is small, increasing the header size with a domain identifier will reduce the efficiency of the link <NUM> significantly. The link efficiency is defined as the ratio between the size of the data being sent in the message and the size of the entire message. For example, if the domain identifier information is, e.g., <NUM> bits, and the size of previously used message is <NUM> bits, then the additional <NUM> bits in the header will increase the size of the entire message to <NUM> bits, leading to reduction in link efficiency of <NUM>%, not including the impact of other control fields in the header such as physical address. If the size of the domain identifier in the header could be reduced the efficiency of the link could be improved up to <NUM> percentage points. In general, the payload may be any suitable length, such as <NUM> to <NUM> bits. The domain identifier information may be any suitable length, such as <NUM>-<NUM> bits.

When the additional header bits to be transmitted are mapped to a relatively small number of domains, e.g. not all possible combinations are likely to appear on the link <NUM>, increasing link efficiency may be storing a mapping of the domains that are in use to a smaller number of header bits in a table (such as device handle table <NUM>) on both ends of the link. In addition (or instead of) to storing a mapping of domains, a mapping of other header bits (such as device or domain capability) may be mapped to a smaller number of header bits.

In order to increase the efficiency of the link <NUM>, in the illustrative embodiment, a device handle table <NUM> (see <FIG>) is defined that includes several entries for different device handle identifiers (DHIs). Each entry in the device handle table <NUM> includes a DHI and one or more elements of a domain identifier, such as a bus/device/function (BDF) identifier (or source identifier) and/or a processor address space identifier (PASID). In the illustrative embodiment, the BDF identifier is <NUM> bits and the PASID is <NUM> bits, giving a domain identifier that is <NUM>-<NUM> bits. More generally, the domain identifier is any identifier that identifies a virtual function, a virtual machine, a process, and/or any other suitable domain. In some embodiments, the domain identifier may be any identifier that identifies different memory domains, and the domain identifier can be used by the IOMMU <NUM>, memory <NUM>, controller hub <NUM>, etc., to enforce boundaries between different memory domains. The domain identifier may be any suitable number of bits, such as <NUM>-<NUM> bits. The device handle table <NUM> may include additional fields that can be uniquely associated with a domain. For example, in some embodiments the device handle table <NUM> may include a Trusted bit for each DHI to identify if the DHI is for a trusted domain.

Rather than including the BDF identifier and/or the PASID in a message header, which would be <NUM>-<NUM> bits per message, messages across the link <NUM> include a reference to an entry in the device handle table in the message header, which can be indexed using a smaller number of bits. For example, the device handle table can be indexed with, e.g., <NUM>-<NUM> bits, which would correspond to <NUM>-<NUM>,<NUM> entries in the device handle table. As more domains may exist than entries available in the device handle table <NUM>, entries in the device handle table <NUM> can be allocated and deallocated as necessary. In the illustrative embodiment, the increased efficiency in the link <NUM> due to a smaller number of bits used to identify the domain makes up for any resources necessary to populate and maintain the device handle table <NUM>.

The approach described herein allows a link (such as a PCIe or CXL link) to support any usages that require tagging of transactions with a sparse set of header fields more efficiently. In one embodiment, it allows fine-grained memory isolation (such as per virtual machine or per process) as defined by software (e.g., by a virtual machine manager (VMM), hypervisor, or an operating system). By splitting the tagging of the domain into a separate device identifier allocation message, a regular message can use a smaller tag to identify the relevant domain. Additionally, the techniques disclosed herein can be used to expand the device context information associated with a device handle identifier (DHI). For example, the device context information can include a trusted bit, which may be used for, e.g., Intel® trusted domain extensions for input/output (TDX.

Turning to <FIG> an embodiment of a layered protocol stack is illustrated. Layered protocol stack <NUM> includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, an Ultra Path Interconnect (UPI) stack, a PCIe stack, a Compute Express Link (CXL), a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below in reference to <FIG> are in relation to a UPI stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack <NUM> is a UPI protocol stack including protocol layer <NUM>, routing layer <NUM>, link layer <NUM>, and physical layer <NUM>. An interface or link, such as link <NUM> in <FIG>, may be represented as communication protocol stack <NUM>. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

UPI uses packets to communicate information between components. Packets are formed in the Protocol Layer <NUM> to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer <NUM> representation to the Data Link Layer <NUM> representation and finally to the form that can be processed by the Protocol Layer <NUM> of the receiving device.

In one embodiment, protocol layer <NUM> is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer <NUM> and physical layer <NUM>. In this regard, a primary responsibility of the protocol layer <NUM> is the assembly and disassembly of packets. The packets may be categorized into different classes, such as home, snoop, data response, non-data response, non-coherent standard, and non-coherent bypass.

The routing layer <NUM> may be used to determine the course that a packet will traverse across the available system interconnects. Routing tables may be defined by firmware and describe the possible paths that a packet can follow. In small configurations, such as a two-socket platform, the routing options are limited and the routing tables quite simple. For larger systems, the routing table options may be more complex, giving the flexibility of routing and rerouting traffic.

Link layer <NUM>, also referred to as data link layer <NUM>, acts as an intermediate stage between protocol layer <NUM> and the physical layer <NUM>. In one embodiment, a responsibility of the data link layer <NUM> is providing a reliable mechanism for exchanging packets between two components. One side of the data link layer <NUM> accepts packets assembled by the protocol layer <NUM>, applies an error detection code, i.e., CRC, and submits the modified packets to the physical layer <NUM> for transmission across a physical to an external device. In receiving packets, the data link layer <NUM> checks the CRC and, if an error is detected, instructs the transmitting device to resend. In the illustrative embodiment, CRC are performed at the flow control unit (flit) level rather than the packet level. In the illustrative embodiment, each flit is <NUM> bits. In other embodiments, each flit may be any suitable length, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> bits.

In one embodiment, physical layer <NUM> includes logical sub block <NUM> and electrical sub-block <NUM> to physically transmit a packet to an external device. Here, logical sub-block <NUM> is responsible for the "digital" functions of Physical Layer <NUM>. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block <NUM>, and a receiver section to identify and prepare received information before passing it to the Link Layer <NUM>.

Physical block <NUM> includes a transmitter and a receiver. The transmitter is supplied by logical sub-block <NUM> with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block <NUM>. In the illustrative embodiment, the physical layer <NUM> sends and receives bits in groups of <NUM> bits, called a physical unit or phit. In some embodiments, a line coding, such as an 8b/10b transmission code or a 64b/66b transmission code, is employed. In some embodiments, special symbols are used to frame a packet with frames <NUM>. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although protocol layer <NUM>, routing layer <NUM>, link layer <NUM>, and physical layer <NUM> are discussed in reference to a specific embodiment of a QPI protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, a port/interface that is represented as a layered protocol includes: (<NUM>) a first layer to assemble packets, i.e. a protocol layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

Referring next to <FIG>, an embodiment of a UPI serial point-to-point link is illustrated. Although an embodiment of a UPI serial point-to-point link is illustrated, a serial point-to-point link is not so limited, as it includes any transmission path for transmitting serial data. In the embodiment shown, a basic UPI serial point-to-point link includes two, low-voltage, differentially driven signal pairs: a transmit pair <NUM>/<NUM> and a receive pair <NUM>/<NUM>. Accordingly, device <NUM> includes transmission logic <NUM> to transmit data to device <NUM> and receiving logic <NUM> to receive data from device <NUM>. In other words, two transmitting paths, i.e. paths <NUM> and <NUM>, and two receiving paths, i.e. paths <NUM> and <NUM>, are included in a UPI link.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device <NUM> and device <NUM>, is referred to as a link, such as link <NUM>. A link may support one lane - each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or wider. In some implementations, each symmetric lane contains one transmit differential pair and one receive differential pair. Asymmetric lanes can contain unequal ratios of transmit and receive pairs. Some technologies can utilize symmetric lanes (e.g., UPI), while others (e.g., Displayport) may not and may even including only transmit or only receive pairs, among other examples. A link may refer to a one-way link (such as the link established by transmission logic <NUM> and receive logic <NUM>) or may refer to a bi-directional link (such as the links established by transmission logic <NUM> and <NUM> and receive logic <NUM> and <NUM>).

A differential pair refers to two transmission paths, such as lines <NUM> and <NUM>, to transmit differential signals. As an example, when line <NUM> toggles from a low voltage level to a high voltage level, i.e. a rising edge, line <NUM> drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.

Referring now to <FIG>, in an illustrative embodiment, the computing system <NUM> establishes an environment <NUM> during operation. The illustrative environment <NUM> includes a host device handle table manager <NUM> and a host message processor <NUM>. The various modules of the environment <NUM> may be embodied as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of the environment <NUM> may form a portion of, or otherwise be established by, the controller hub <NUM> (which may be a root complex) the port <NUM> (which may be a root port), or other hardware components of the computing system <NUM>. As such, in some embodiments, one or more of the modules of the environment <NUM> may be embodied as circuitry or collection of electrical devices (e.g., host device handle table manager circuitry <NUM>, host message processor circuitry <NUM>, etc.). It should be appreciated that, in such embodiments, one or more of the circuits (e.g., the host device handle table manager circuitry <NUM>, the host message processor circuitry <NUM>, etc.) may form a portion of one or more of the controller hub <NUM>, the port <NUM>, and/or other components of the computing system <NUM>. Additionally, in some embodiments, one or more of the illustrative modules may form a portion of another module and/or one or more of the illustrative modules may be independent of one another. Further, in some embodiments, one or more of the modules of the environment <NUM> may be embodied as virtualized hardware components or emulated architecture. It should be appreciated that some of the functionality of one or more of the modules of the environment <NUM> may require a hardware implementation, in which case embodiments of modules which implement such functionality will be embodied at least partially as hardware.

The host device handle table manager <NUM>, which may be implemented as hardware, firmware, software, and/or any suitable combination thereof, is configured to manage the host device handle table, such as the table <NUM> shown in <FIG>. The host device table manager <NUM> can add, remove, invalidate, etc., entries in the table <NUM>. In the illustrative embodiment, each entry in the table <NUM> has a device handle identifier (DHI), one or more domain identifiers (such as a PASID or BDF identifier), and, in some embodiments, additional context information such as a trusted bit or whether a particular feature or set of features is supported by a particular device <NUM> or device context. For example, in some embodiments, a device <NUM> may not support PASID. In such embodiments, the PASID in the table <NUM> may be zero, or a separate bit in the host device handle table entry may indicate that PASID is not supported. In the illustrative embodiment, the DHI is an N-bit number, such as a <NUM>-<NUM> bit number, and the DHI may be any value from <NUM> to <NUM>N-<NUM>. Each entry in the table may have any suitable number of bits. For example, in the illustrative embodiment, each PASID is <NUM> bits, each BDF identifier is <NUM> bits, and the trusted bit is a single bit. More generally, each column in each entry in the table may have any suitable number of bits, such as <NUM>-<NUM> bits.

In some embodiments, the host device table manager <NUM> may store some or all of the table <NUM> on SRAM or may store some or all of the table <NUM> in private DRAM and use a cache to keep its most recently used entries. In the illustrative embodiment, the host device handle table manager <NUM> manages separate table <NUM> for each connected device <NUM>. In some embodiments, the host device handle table manager <NUM> may manage a single table <NUM> for more than one or all of the connected devices <NUM>. In such embodiments, the table <NUM> may be partitioned and each partition assigned to a unique connected device.

In some embodiments, the host device handle table manager <NUM> may receive an instruction to clear or reset a table. For example, in some embodiments, upon a hot swap or hot plug of a device <NUM>, a table <NUM> associated with the device <NUM> may be reset or completely deallocated.

The host message processor <NUM>, which may be implemented as hardware, firmware, software, and/or any suitable combination thereof, is configured to manage the host device handle table, is configured to manage messages sent to and from the controller hub <NUM>. The host message processor <NUM> includes an allocation manager <NUM>, a deallocation manager <NUM>, and a transaction manager <NUM>.

The allocation manager <NUM> is configured to process special-purpose device handle identifier (DHI) allocation messages. The device allocation message may indicate, e.g., a DHI to allocate (e.g., an n-bit number), a bus/device/function (BDF) identifier, a processor address space identifier (PASID), and a trusted bit value. Upon receipt of a device allocation message, the allocation manager <NUM> allocates the device handle identifier by adding or editing an entry in a device handle identifier table <NUM>. The allocation manager <NUM> stores the context information included in the message (such as the BDF identifier, the PASID, the trusted bit, etc.). It should be appreciated that additional context may be provided other than the specific context described herein, such as context associated with protocols not explicitly referenced herein. In some embodiments, the allocation manager <NUM> may validate that the BDF is within the secondary and subordinate bus number of the controller hub <NUM>. The allocation manager <NUM> may also validate that the DHI is within the DHI range associated with the BDF if the host device handle table <NUM> has been partitioned among connected devices.

The deallocation manager <NUM> is configured to process special-purpose DHI deallocation messages. A deallocation message indicates a DHI that should be deallocated. Upon receipt of a deallocation message, the deallocation manager <NUM> deallocates the DHI included in the DHI deallocation message. The deallocation manager <NUM> may, e.g., delete an entry from the device handle table <NUM> or mark an entry associated with the DHI as invalid. In some embodiments, the device deallocation message may indicate that all of the device handles should be deallocated. Such a message may, e.g., be initiated by software after a hot plug event. In response to such a message, the deallocation manager <NUM> may deallocate all device handles associated with one or more devices <NUM>. In the illustrative embodiment, allocation and deallocation messages are sent from the device <NUM> on links <NUM> such as PCIe or CXL when the device is responsible for autonomously managing the DHI assigned to it. In some embodiments, software may use deallocation and/or allocation messages using MMIO register writes to manage the device handle table. The interface used to initiate those messages may be implementation specific. In one implementation, the controller hub <NUM> may use the Intel® Virtualization Technology for Directed I/O (Intel® VT-d) architecture to send these deallocation requests to the device <NUM> using a similar or the mechanisms used to send device translation lookaside buffer (DevTLB) address translation invalidation messages.

The transaction manager <NUM> is configured to process ordinary transaction messages on the link <NUM> connecting a device <NUM> and the controlled hub <NUM>. In the illustrative embodiment, transaction messages received from the device <NUM> include a DHI, and messages to be sent to the device <NUM> include a DHI. Upon receipt of a message, the transaction manager <NUM> accesses the entry in the device handle table corresponding to the DHI or domain identifier in the message. If the entry is not valid or not in the table, processing of the message is aborted and an error may be returned.

For messages received from the device <NUM>, the transaction manager <NUM> processes the transaction message with use of the domain identifier fields retrieved from a valid entry the host device handle table corresponding to the DHI in the message. In one embodiment, the transaction manager <NUM> may send the transaction message to a destination, such as the IOMMU <NUM>, the memory <NUM>, the processor <NUM>, etc. Additionally or alternatively, the transaction manager <NUM> may use the domain identifier to determine how to process the message. For example, in one embodiment, security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted. For messages to be sent to the device <NUM>, the transaction manager <NUM> may send the message to the device <NUM> with the DHI from the device handle table. The device <NUM> can then use the DHI to identify the domain and process the message accordingly. In some embodiments, an entry in the device handle table <NUM> may indicate whether a particular function or feature is supported. For example, for Secure ATS, if the PASID field was not valid, the transaction manager <NUM> may use a Requester ID PASID (RID_PASID), which may be defined by Intel® VT-d, in place of the PASID to perform a Secure ATS check. As another example, the trusted field may be used to treat the message as a trusted transaction as defined by Intel® VT-d, and if the trusted field is not valid for a domain, all requests associated with the domain would be treated as untrusted.

Referring now to <FIG>, in an illustrative embodiment, the offload device <NUM> establishes an environment <NUM> during operation. The illustrative environment <NUM> includes a device handle table manager <NUM> and a device message processor <NUM>. The various modules of the environment <NUM> may be embodied as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of the environment <NUM> may form a portion of, or otherwise be established by, the device <NUM> or other hardware components of the computing system <NUM>. As such, in some embodiments, one or more of the modules of the environment <NUM> may be embodied as circuitry or collection of electrical devices (e.g., device handle table manager circuitry <NUM>, device message processor circuitry <NUM>, etc.). It should be appreciated that, in such embodiments, one or more of the circuits (e.g., the device handle table manager circuitry <NUM>, the device message processor circuitry <NUM>, etc.) may form a portion of the device <NUM> and/or other components of the computing system <NUM>. Additionally, in some embodiments, one or more of the illustrative modules may form a portion of another module and/or one or more of the illustrative modules may be independent of one another. Further, in some embodiments, one or more of the modules of the environment <NUM> may be embodied as virtualized hardware components or emulated architecture. It should be appreciated that some of the functionality of one or more of the modules of the environment <NUM> may require a hardware implementation, in which case embodiments of modules which implement such functionality will be embodied at least partially as hardware.

The device handle table manager <NUM>, which may be implemented as hardware, firmware, software, and/or any suitable combination thereof, is configured to manage the device handle table <NUM> on the device <NUM>, such as the table <NUM> shown in <FIG>. The device table manager <NUM> can add, remove, invalidate, etc., entries in the table <NUM>. In some embodiments, the device table manager <NUM> may store some or all of the table <NUM> on SRAM or may store some or all of the table <NUM> in private DRAM and use a cache to keep its most recently used entries. In some embodiments, the device handle table manager <NUM> may receive an instruction to clear or reset a table. For example, in some embodiments, upon a hot swap or hot plug of a device <NUM>, a table <NUM> associated with the device <NUM> may be reset or completely deallocated.

The device message processor <NUM>, which may be implemented as hardware, firmware, software, and/or any suitable combination thereof, is configured to control device handle table allocations and deallocations on the device <NUM> and to use the device handle table information when sending ordinary transactions on the link <NUM>. The device message processor <NUM> includes an allocation manager <NUM>, a deallocation manager <NUM>, and a transaction manager <NUM>.

The allocation manager <NUM> manages device handle allocations on the device <NUM>. When a DHI needs to be allocated, the allocation manager communicates with the device handle manager <NUM> to allocate an entry in the device handle table <NUM>. In one embodiment, allocation of DHI may be performed by software by writing to MMIO registers on the device. In such case, software would also be responsible for sending a DHI allocation message to the host allocation manager <NUM>. In another embodiment, the device <NUM> selects a DHI to be allocated autonomously among those DHI assigned to the device, using a device-specific selection method using any suitable algorithm to select the DHI, such as a first-in-first-out algorithm, a least recently used algorithm, a least frequently used algorithm, etc. In such case, the allocation manager <NUM> is responsible for sending a DHI allocation message to the computing system <NUM> on the link <NUM>, only after the update to the local device handle table <NUM> is completed. If no DHI is free, software or the device is expected to first deallocate an existing DHI using the deallocation manager <NUM>. In one embodiment, DHI allocation occurs when a new device context is created by software. When software creates a device context, it is required to provide the necessary information to identify the device context domain, such as the BDF and/or PASID information, using a device-specific mechanism.

The deallocation manager <NUM> manages device handle deallocation on the device <NUM>. When a DHI needs to be deallocated, the deallocation manager communicates with the device handle manager <NUM> to deallocate an entry in the device handle table <NUM>. In one embodiment, deallocation of DHI may be performed by software by writing to MMIO registers on the device. In such case, software would also be responsible for sending a DHI deallocation message to the host deallocation manager <NUM>. In another embodiment, the device <NUM> selects a DHI to be deallocated autonomously, using a device-specific selection method. In such case, the deallocation manager <NUM> is responsible for sending a DHI deallocation message to the computing system <NUM> on the link <NUM>, only after the update to the local device handle table <NUM> is completed. In one embodiment, DHI deallocation occurs when a device context is terminated by software.

In the illustrative embodiment, the deallocation manager <NUM> must ensure that all previous requests using a particular DHI have been completed before deallocating the DHI. If necessary, the deallocation manager <NUM> may wait until all previous requests associated with a DHI have been completed before deallocating a DHI. In some embodiments, the deallocation manager <NUM> may select a DHI to deallocate based on the DHI not having any outstanding requests.

In some embodiments, a device handle allocation message automatically deallocates the DHI from the previous domain and reallocates it to the new domain on the device <NUM> and/or the controller hub <NUM>. In such embodiments, an explicit device handle deallocation message may not be necessary. In some embodiments, the deallocation manager <NUM> may receive a message to deallocate one or more or all of the device handles, such as from software operating on another component of the computing system <NUM>. In such cases, the deallocation manager <NUM> may update the device handle table accordingly.

The transaction manager <NUM> is configured to process ordinary transaction on the device <NUM>. For messages sent from the device <NUM>, the transaction manager <NUM> accesses the device handle table to identify the device handle identifier (DHI) for the domain associated with the message. The transaction manager <NUM> then sends the message with the DHI. It should be appreciated that the transaction manager <NUM> does not need to include the domain identifier, which would be longer (i.e., more bits) than the DHI.

For messages received at the device <NUM> from the controller hub <NUM> with a DHI, the transaction manager <NUM> accesses an entry in the device handle table based on the DHI. In the illustrative embodiment, the transaction manager <NUM> searches the device handle table for an entry that matches the DHI. The transaction manager <NUM> accesses the domain identifier corresponding to the DHI. The transaction manager <NUM> then processes the message based on the domain identifier. For example, the transaction manager <NUM> may send the message to a particular virtual function, a queue pair, a dedicated work queue, a shared work queue, a work command, etc. In the illustrative embodiment, the domain identifier may be a BDF identifier and/or a PASID. In some embodiments, if the transaction manager <NUM> does not find an entry in the device handle table based on the DHI, the transaction manager <NUM> may send an error message.

Referring now to <FIG>, in one embodiment, a device handle table <NUM> includes several entries for different device handle identifiers (DHIs). Each illustrative entry includes a DHI, a PASID, a BDF identifier, and a trusted bit. A valid bit on each entry indicates if a valid DHI has been allocated in the entry. Additionally or alternatively, a column in the table <NUM> may indicate whether a particular feature is supported.

It should be appreciated that the device handle table <NUM> may be organized differently on the controller hub <NUM> from the device <NUM>. For example, the table <NUM> on the controller hub <NUM> may be indexed differently from the device <NUM>. In another example, the device <NUM> may include an indication of a queue pair, a dedicated work queue, a shared work queue, a work command, etc., associated with a DHI. The device handle table <NUM> may be of different size on the controller hub <NUM> and the device <NUM>. For example, if the device handle table <NUM> on the controlled hub <NUM> is partitioned among the connected devices, each connected device <NUM> only needs to store the subset of DHI assigned to it. In one embodiment, software partitions the DHI by assigning a contiguous range of DHI to each device <NUM>.

Referring now to <FIG>, in use, the computing system <NUM> may execute a method <NUM> for transferring data using device handle identifiers (DHIs), which may be performed by hardware, software, firmware, or any combination thereof. In the illustrative embodiment, some or all of the method <NUM> may be performed by the controller hub <NUM>. In some embodiments, the controller hub <NUM> may be a root complex, and some or all of the method <NUM> may be performed by a root port <NUM>. The method <NUM> begins in block <NUM>, in which the controller hub <NUM> negotiates link capabilities with one or more connected devices <NUM>. In the illustrative embodiment, the controller hub <NUM> negotiates link capabilities when the link is first established. For example, the controller hub <NUM> may send and/or receive a message with an enabling bit at a particular location indicating that the controller hub <NUM> and/or the connected device <NUM> supports using DHIs. In the illustrative embodiment, the controller hub <NUM> informs the device <NUM> of the allowed range of DHI values in block <NUM>. For example, if the DHIs are stored in the controller hub as N bits, then the DHI values can be from <NUM> to <NUM>N-<NUM>. If the device handle table <NUM> is being partitioned among multiple devices, the controlled hub informs the device <NUM> of the range of DHIs assigned to it by providing the lower and upper bound value in the range from <NUM> to <NUM>N-<NUM>.

In block <NUM>, the controller hub <NUM> receives a message from the device <NUM>. The message may be part of a coherent protocol such as CXL. cache or a non-coherent protocol such as CXL input/output (CXL. In some embodiments, the message may be referred to as a flit. The controller hub <NUM> may receive a device handle allocation (DHI_ALLOC) message in block <NUM>. The controller hub <NUM> may receive a device handle deallocation (DHI_DEALLOC) message in block <NUM>. In block <NUM>, the controller hub <NUM> may receive a transaction message (e.g., a memory read or write, a cache coherency message, etc.) with a DHI. The message may be, e.g., a message associated with a queue pair, a dedicated work queue, a shared work queue, a work command, etc. In the illustrative embodiment, some or all of the messages in block <NUM> may be received from a device <NUM>. It should be appreciated that, in some embodiments, devices <NUM> do not perform allocation and deallocation of DHIs, and, instead, the controller hub <NUM> receives the device handle allocation and device handle deallocation messages from software, such as, for example, through writes to memory mapped I/O (MMIO) registers. In that case, the controller hub <NUM> processes these messages in the same manner as if they came from the device.

In block <NUM>, if the message is a device allocation message, the method <NUM> jumps to block <NUM> in <FIG>. In block <NUM>, the controller hub <NUM> allocates a DHI to the device <NUM> based on the device allocation message. The device allocation message may indicate, e.g., a DHI to allocate (e.g., an n-bit number), a bus/device/function (BDF) identifier, a processor address space identifier (PASID), and a trusted bit value. In some embodiments, the controller hub <NUM> may validate that the BDF is within the secondary and subordinate number of the controller hub <NUM>. The controller hub <NUM> may also validate that the DHI is within the DHI range associated with the BDF. The controller hub <NUM> updates the device handle table (such as device handle table <NUM>) to add an entry (or mark the entry for the DHI as valid) in block <NUM>. The controller hub <NUM> stores the context information provided by the device <NUM> (such as the BDF identifier, the PASID, the trusted bit, etc.) in block <NUM>. It should be appreciated that additional context may be provided other than the specific context described herein, such as context associated with protocols not explicitly referenced herein. After the controller hub <NUM> stores the context information, the method <NUM> loops back to block <NUM> in <FIG> to wait for another message.

Referring back to block <NUM>, if the received message is not a device handle allocation message, the method <NUM> proceeds to block <NUM>. In block <NUM>, if the message is a device deallocation message, the method <NUM> jumps to block <NUM> in <FIG>. In block <NUM>, the controller hub <NUM> deallocates the DHI in the device deallocation message. The controller hub <NUM> may, e.g., delete an entry from the device handle table <NUM> or mark an entry associated with the DHI as invalid. In some embodiments, the device deallocation message may indicate that all of the device handles should be deallocated. Such a message may, e.g., be initiated by software after a hot plug event. In response to such a message, the controller hub <NUM> may deallocate all device handles in block <NUM>. More generally, software may send a message to deallocate, one, some, or all device handles. The method <NUM> then loops back to block <NUM> in <FIG> to wait for another message.

Referring back to block <NUM>, if the received message is not a device handle deallocation message, the method <NUM> proceeds to block <NUM>. In block <NUM>, the controller hub <NUM> accesses the entry in the device handle table for the device <NUM> corresponding to the DHI in the message. As part of accessing the entry, the controller hub <NUM> accesses one or more domain identifiers corresponding to the DHI in block <NUM>. The domain identifier may identify a virtual function, a virtual machine, a process, etc. In the illustrative embodiment, the domain identifier is embodied as a BDF identifier and/or PASID.

In block <NUM>, if the entry for the DHI is not valid or not in the table, the method <NUM> proceeds to block <NUM>, in which processing of the message is aborted and an error may be returned to the device <NUM>. If the entry for the DHI is valid, the method <NUM> proceeds to block <NUM>, in which the controller hub <NUM> processes the transaction message with use of the domain identifier. In one embodiment, the controller hub <NUM> may send the transaction message to a destination, such as the IOMMU <NUM>, the memory <NUM>, the processor <NUM>, etc., in block <NUM>. Additionally or alternatively, the controller hub <NUM> may use the domain identifier to determine how to process the message. For example, in one embodiment, security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted.

Referring now to <FIG>, in use, the computing system <NUM> may execute a method <NUM> for transferring data using device handle identifiers (DHIs), which may be performed by hardware, software, firmware, or any combination thereof. In the illustrative embodiment, some or all of the method <NUM> may be performed by the controller hub <NUM>. The controller hub <NUM> is a root complex, and some or all of the method <NUM> may be performed by a root port <NUM>. The method <NUM> begins in block <NUM>, in which the controller hub <NUM> receives a message for a device <NUM> with a domain identifier. In the illustrative embodiment, the domain identifier is a BDF identifier and/or a PASID. Additionally or alternatively, in some embodiments, the domain identifier may be any identifier that identifies a virtual function, a virtual machine, a process, etc. The message may be part of a coherent protocol such as CXL. cache or a non-coherent protocol such as CXL input/output (CXL. In some embodiments, the message may be referred to as a flit. The message may be, e.g., a memory read or write, a cache coherency message, etc. In some embodiments, the controller hub <NUM> may create a message to be sent to a device <NUM> and identify a domain identifier associated with the message.

In block <NUM>, the controller hub <NUM> accesses an entry in the device handle table based on the domain identifier. In the illustrative embodiment, the controller hub <NUM> searches the device handle table for an entry that matches the domain identifier, such as an entry that matches the BDF and/or PASID. In block <NUM>, the controller hub <NUM> accesses the DHI corresponding to the domain. In some embodiments, if the controller hub <NUM> does not find an entry in the device handle table based on the domain identifier, the controller hub <NUM> may send an error message and/or send a message to the device <NUM> using the domain identifier directly.

In block <NUM>, the controller hub <NUM> sends the message to the device <NUM> with the DHI from the device handle table. The device <NUM> can then use the DHI to identify the domain and process the message accordingly.

Referring now to <FIG>, in use, the computing system <NUM> may execute a method <NUM> for transferring data using DHIs, which may be performed by hardware, software, firmware, or any combination thereof. In the illustrative embodiment, some or all of the method <NUM> may be performed by a device <NUM>. The method <NUM> begins in block <NUM>, in which the device <NUM> negotiates link capabilities with the controller hub <NUM>. In the illustrative embodiment, the device <NUM> negotiates link capabilities when the link is first established. For example, the device <NUM> may send and/or receive a message with an enabling bit at a particular location indicating that the controller hub <NUM> and/or the connected device <NUM> supports using DHIs. In the illustrative embodiment, the controller hub <NUM> informs the device <NUM> of the allowed range of DHI values. For example, if the DHIs are stored in the controller hub as N bits, then the DHI range assigned to the device <NUM> can be from <NUM> to <NUM>N-<NUM>. In some embodiments, the device <NUM> implements a new capability to support use of DHIs using, for example, a Designated Vendor-Specific Extended Capability (DVSEC).

In block <NUM>, the device <NUM> determines a message to send. In one embodiment, a virtual function or other function on the device <NUM> creates a message to be sent and transmits it to a supervisor. As part of determining the message to send, the device <NUM> determines a domain associated with the message. For example, the device <NUM> may determine a domain identifier, such as a BDF identifier (or source ID) and/or a PASID associated with the message based on the device context that originated the message. In some embodiments, the device <NUM> may determine a device context as part of the domain identifier, such as a queue pair, a dedicated work queue, a shared work queue, a work command, etc. The message may be part of a coherent protocol such as CXL. cache or a non-coherent protocol such as CXL input/output (CXL. In some embodiments, the message may be referred to as a flit. The message may be, e.g., a memory read or write, a cache coherency message, etc..

In block <NUM>, the device <NUM> determines whether a DHI is allocated for the domain associated with the message. The device <NUM> may access a device handle table (such as by searching the device handle table for the domain identifier) and, if there is an entry associated with the domain, access the DHI.

In block <NUM>, if a DHI is allocated for the domain, the method <NUM> jumps to block <NUM>, in which the device <NUM> sends a message with the DHI in a header of the message. The device <NUM> may send the message to the controller hub <NUM>, possibly through one or more switches <NUM>.

In block <NUM>, if a DHI is not allocated for the domain, the method <NUM> proceeds to block <NUM>, in which the device <NUM> determines whether there are unallocated entries in the domain handle table. If there are, the method <NUM> jumps to block <NUM> to send a DHI allocation message. If there are not, the method <NUM> proceeds to block <NUM> to determine a DHI to deallocate.

In block <NUM>, the device <NUM> determines a DHI to deallocate. The device <NUM> may use any suitable approach to determining a DHI to deallocate. In some embodiments, a device context associated with a DHI has been terminated, but the associated DHI has not yet been deallocated, as the device <NUM> can deallocate DHIs lazily because there will be no new requests with the DHI until it gets reallocated. In such embodiments, the device <NUM> may deallocate a DHI for which the associated device context has been terminated. More generally, the device <NUM> may use any suitable algorithm to select the DHI, such as a first-in-first-out algorithm, a least recently used algorithm, a least frequently used algorithm, etc..

In the illustrative embodiment, the device <NUM> must ensure that all previous requests using a particular DHI have been completed before deallocating the DHI. If necessary, the device <NUM> may wait until all previous requests associated with a DHI have been completed before deallocating a DHI. In some embodiments, the device <NUM> may select a DHI to deallocate based on the DHI not having any outstanding requests.

In block <NUM>, the device <NUM> sends a DHI deallocation message to the controller hub <NUM> identifying the DHI to be deallocated. The device <NUM> will also update the local device handle table with an indication that the DHI has been deallocated. In some embodiments, a device handle allocation message automatically deallocates the DHI from the previous domain and reallocates it to the new domain on the device <NUM> and/or the controller hub <NUM>. In such embodiments, an explicit device handle deallocation message may not be necessary.

In block <NUM>, the device <NUM> sends a device handle allocation message to the controller hub <NUM>. The device handle allocation message may include a domain identifier and the DHI to be allocated. The domain identifier in the message includes the context information (such as the BDF identifier, the PASID, the trusted bit, etc.). The device <NUM> also updates the local device handle allocation table upon sending the DHI allocation message.

In block <NUM>, the device <NUM> sends the message with the DHI. It should be appreciated that the device <NUM> does not need to include the domain identifier, which would be longer (i.e., more bits) than the DHI.

Referring now to <FIG>, in use, the computing system <NUM> may execute a method <NUM> for transferring data using DHIs, which may be performed by hardware, software, firmware, or any combination thereof. In the illustrative embodiment, some or all of the method <NUM> may be performed by the device <NUM>. The method <NUM> begins in block <NUM>, in which the device <NUM> receives a message from the host controller hub <NUM> with a DHI. The message may be part of a coherent protocol such as CXL. cache or a non-coherent protocol such as CXL input/output (CXL. In some embodiments, the message may be referred to as a flit. The message may be, e.g., a memory read or write, a cache coherency message, etc..

In block <NUM>, the device <NUM> accesses an entry in the device handle table based on the DHI. In the illustrative embodiment, the device <NUM> searches the device handle table for an entry that matches the DHI. In block <NUM>, the device <NUM> accesses the domain identifier corresponding to the DHI. In the illustrative embodiment, the domain identifier may be a BDF identifier and/or a PASID. In some embodiments, if the device <NUM> does not find an entry in the device handle table based on the domain identifier, the device <NUM> may send an error message.

In block <NUM>, the device <NUM> processes the message based on the domain identifier. For example, the device <NUM> may send the message to a particular virtual function, a queue pair, a dedicated work queue, a shared work queue, a work command, etc..

Referring to <FIG>, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor <NUM> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor <NUM>, in one embodiment, includes at least two cores-core <NUM> and <NUM>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <NUM> may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor <NUM>, as illustrated in <FIG>, includes two cores-core <NUM> and <NUM>. Here, core <NUM> and <NUM> are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core <NUM> includes an out-of-order processor core, while core <NUM> includes an in-order processor core. However, cores <NUM> and <NUM> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core <NUM> are described in further detail below, as the units in core <NUM> operate in a similar manner in the depicted embodiment.

As depicted, core <NUM> includes two hardware threads 1301a and 1301b, which may also be referred to as hardware thread slots 1301a and 1301b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <NUM> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1301a, a second thread is associated with architecture state registers 1301b, a third thread may be associated with architecture state registers 1302a, and a fourth thread may be associated with architecture state registers 1302b. Here, each of the architecture state registers (1301a, 1301b, 1302a, and 1302b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1301a are replicated in architecture state registers 1301b, so individual architecture states/contexts are capable of being stored for logical processor 1301a and logical processor 1301b. In core <NUM>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <NUM> may also be replicated for threads 1301a and 1301b. Some resources, such as re-order buffers in reorder/retirement unit <NUM>, ILTB <NUM>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <NUM>, execution unit(s) <NUM>, and portions of out-of-order unit <NUM> are potentially fully shared.

Processor <NUM> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <FIG>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <NUM> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <NUM> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <NUM> to store address translation entries for instructions.

Core <NUM> further includes decode module <NUM> coupled to fetch unit <NUM> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1301a, 1301b, respectively. Usually core <NUM> is associated with a first ISA, which defines/specifies instructions executable on processor <NUM>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <NUM> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders <NUM>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <NUM>, the architecture or core <NUM> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders <NUM>, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders <NUM> recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block <NUM> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1301a and 1301b are potentially capable of out-of-order execution, where allocator and renamer block <NUM> also reserves other resources, such as reorder buffers to track instruction results. Unit <NUM> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <NUM>. Reorder/retirement unit <NUM> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block <NUM>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) <NUM> are coupled to execution unit(s) <NUM>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores <NUM> and <NUM> share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface <NUM>. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache-last cache in the memory hierarchy on processor <NUM>-such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache-a type of instruction cache-instead may be coupled after decoder <NUM> to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor <NUM> also includes on-chip interface module <NUM>. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor <NUM>. In this scenario, on-chip interface <NUM> is to communicate with devices external to processor <NUM>, such as system memory <NUM>, a chipset (often including a memory controller hub to connect to memory <NUM> and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus <NUM> may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory <NUM> may be dedicated to processor <NUM> or shared with other devices in a system. Common examples of types of memory <NUM> include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device <NUM> may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor <NUM>. For example in one embodiment, a memory controller hub is on the same package and/or die with processor <NUM>. Here, a portion of the core (an on-core portion) <NUM> includes one or more controller(s) for interfacing with other devices such as memory <NUM> or a graphics device <NUM>. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface <NUM> includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link <NUM> for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory <NUM>, graphics processor <NUM>, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor <NUM> is capable of executing a compiler, optimization, and/or translator code <NUM> to compile, translate, and/or optimize application code <NUM> to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (<NUM>) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (<NUM>) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (<NUM>) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (<NUM>) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (<NUM>) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (<NUM>) a combination thereof.

Referring now to <FIG>, shown is a block diagram of another system <NUM> in accordance with an embodiment of the present disclosure. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of a processor. In one embodiment, <NUM> and <NUM> are part of a serial, point-to-point coherent interconnect fabric, such as a high-performance architecture. As a result, aspects of the present disclosure may be implemented within the QPI architecture.

While shown with only two processors <NUM>, <NUM>, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors <NUM> and <NUM> are shown including integrated memory controller units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> also exchanges information with a high-performance graphics circuit <NUM> via an interface circuit <NUM> along a high-performance graphics interconnect <NUM>.

A shared cache (not shown) may be included in either processor or outside of both processors; yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

In one embodiment, first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in <FIG>, various I/O devices <NUM> are coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, second bus <NUM> includes a low pin count (LPC) bus. Various devices are coupled to second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which often includes instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> is shown coupled to second bus <NUM>. Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a <NUM> or a <NUM> during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a <NUM> or <NUM>. Instead, the logic gate is one coupled in some manner that during operation the <NUM> or <NUM> output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases 'to,' 'capable of/to,' and or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as <NUM>'s and <NUM>'s, which simply represents binary logic states. For example, a <NUM> refers to a high logic level and <NUM> refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of <NUM> and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

Claim 1:
A controller hub (<NUM>) comprising:
host message processor circuitry to:
receive a message from a device connected to the controller hub by a link, wherein the message comprises a device handle identifier;
access an entry in a device handle table based on the device handle identifier of the message, wherein the entry in the device handle table comprises a domain identifier corresponding to a domain of the message; and
process the message based on the domain identifier corresponding to the device handle identifier of the message,
wherein the domain identifier comprises a bus/device/function, BDF, identifier, a processor address space identifier, PASID, or both, and
wherein the controller hub (<NUM>) is a root complex of a Peripheral Component Interconnect Express, PCIE, interconnect, or
wherein the controller hub (<NUM>) is a root complex of a Compute Express Link, CXL, interconnect.