Patent Description:
Integrated electronic devices are known, for example diodes or MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) for power-electronic applications, made starting from a silicon carbide substrate.

Such devices are advantageous thanks, at least in part, to the favourable chemico-physical properties of silicon carbide. For instance, silicon carbide generally has a bandgap wider than that of silicon, that is the material commonly used in electronic power devices. Consequently, even with relatively small thicknesses, silicon carbide has a breakdown voltage higher than silicon and can therefore be advantageously used in high-voltage, high-power, and high-temperature applications.

Manufacturing of advanced silicon carbide power devices is, however, affected by some problems due to the dielectric properties of passivation layers used with insulating functions.

On account of the high operating temperature and dielectric rigidity, a polyimide layer (i.e., a polymer of imide monomers) is typically used as passivation and insulation material in current silicon carbide power devices, being for example formed via deposition using spin-coating techniques. Problems of adhesion of this passivation layer to the underlying silicon carbide substrate (or to some other layer of material), in particular after thermal cycles (both during operations of electrical testing and during the effective operating life) currently limit reliability of such power devices.

In particular, due to possible delamination of the passivation layer, caused by thermomechanical stresses after the aforesaid thermal cycles, so-called electrical arching phenomena may occur in reverse biasing, between metal-material regions of the power device, with consequent damage or breakdown of the same power device.

<CIT> and <CIT> disclose respective semiconductor devices including a SiC layer substrate and a passivation layer overlying a dielectric region at an edge area of the substrate; the passivation layer has portions extending throughout the thickness of the dielectric region and reaching the substrate, at the edge area.

The aim of the present invention is to provide an improved solution for a silicon carbide power device, allowing to overcome the disadvantages highlighted previously associated to known solutions and in particular providing a higher robustness in regard to thermomechanical stresses due to thermal cycles.

According to the present invention, a silicon carbide power device and a corresponding manufacturing process are therefore provided, as defined in the appended claims.

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

With initial reference to <FIG>, a first embodiment of a process for manufacturing a silicon carbide power device is now disclosed.

The above manufacturing process envisages providing a wafer <NUM> comprising a silicon carbide substrate <NUM>, having a front surface 2a and a rear surface 2b, which extend in a horizontal plane xy and are separated from and opposite to one another along a vertical axis z, transverse to the horizontal plane xy.

In the embodiment illustrated, where the power device is, by way of example, a power diode, a rear cathode contact is formed on the rear surface 2b of the substrate, constituted by a layer of conductive material <NUM>, for example metal material.

Moreover, a plurality of anode wells <NUM>, constituted by appropriately doped regions, are formed at the front surface 2a of the substrate <NUM>, in an active area A' of the power device. In a known manner, each of the aforesaid anode wells <NUM>, which can have a strip-like conformation (in top view, in the horizontal plane xy), represents a cell of the power device.

At the front surface 2a of the substrate <NUM>, in an edge area A" of the power device (distinct and separate from the active area A'), an edge anode region <NUM> is moreover formed, which is also constituted by an appropriately doped region, having a side extension greater than that of the aforesaid anode wells <NUM> (in <FIG>, along a first axis x of the aforesaid horizontal plane xy).

In a known manner, the edge area A" terminates at a scribe line SL, represented by a dashed line, along which dicing of the wafer <NUM> will be carried out, for the formation of dies of the power device, once the manufacturing process is completed.

The edge anode region <NUM> is arranged externally with respect to the active area A' and to the anode wells <NUM>, for example being shaped like a ring around the active area A'. In a way not shown, the aforesaid edge anode region <NUM> may be connected to a ring-shaped implanted region, which is also formed at the front surface 2a of the substrate <NUM>, at the edge area A" (having, in a known manner, functions of termination of the electrical field).

As shown in the aforesaid <FIG>, a thick dielectric layer <NUM>, in particular of TEOS (TetraEthyl OrthoSilicate), is formed by deposition on the substrate <NUM>, coating the entire front surface 2a of the substrate <NUM>; the thick dielectric layer <NUM> has a thickness comprised, for example, between <NUM> and <NUM>.

As illustrated in <FIG>, an overlying layer <NUM> is formed by deposition on the thick dielectric layer <NUM>, for example made of polysilicon or of a different material (for example, silicon nitride), which provides a chemical-etching selectivity relative to the material of the thick dielectric layer <NUM>, in the example TEOS; the overlying layer <NUM> has a thickness comprised, for example, between <NUM> and <NUM>.

As illustrated in <FIG>, the overlying layer <NUM> is defined via photolithographic process, i.e., via formation of a photoresist mask (not illustrated here) and subsequent etching of the material, in the example polysilicon (selectively with respect to the underlying thick dielectric layer <NUM>).

In particular, definition of the overlying layer <NUM> leads to formation of a first overlying region 10a and a second overlying region 10b, at the edge area A", which are spaced apart laterally (in the horizontal plane xy, in <FIG> along the axis x) and define between them an access window <NUM>. As will be illustrated hereinafter, these overlying regions 10a, 10b can have a ring shape in top view and are arranged around and externally to the active area A' of the power device.

For instance, the first and second overlying regions 10a, 10b may have a same width in the horizontal plane xy (in <FIG> along the axis x), for example a width of <NUM>, and the access window <NUM> may have a width (in <FIG> along the axis x; in general, in a direction transverse to a direction of longitudinal extension) comprised between <NUM> and <NUM>.

In particular, the first overlying region 10a is located laterally at a distance (in the horizontal plane xy, in <FIG> along the axis x) with respect to the boundary of the active area A' of the power device, therefore being arranged, in use, in an electrically non-active area of the power device (in other words, an area external to the area involved by the electrical field lines due to operation of the power device).

As illustrated in <FIG>, the thick dielectric layer <NUM> is then defined, once again by photolithographic process so as to remove it (therefore leaving the front surface 2a of the substrate <NUM> exposed) in the active area A' (therefore exposing the anode wells <NUM> and, at least in part, the edge anode region <NUM>) and moreover along the scribe line SL, leaving a remaining dielectric region 8a above the edge area A".

In a known way, here not shown, anode electrical-contact regions may then be formed, by surface implants in the aforesaid anode wells <NUM> and edge anode region <NUM>, in order to improve the corresponding electrical contact properties.

As shown in <FIG>, a front conductive layer <NUM>, for example a metal layer, is then formed above the front surface 2a of the substrate <NUM>, in a conformable manner (for example, by a sputtering process).

The front conductive layer <NUM> is then defined, as illustrated in <FIG>, via photolithographic process, so as to remove it in the edge area A" and leave a remaining portion thereof, designated by 14a, above the active area A', in particular in direct contact with the front surface 2a of the substrate <NUM>, the anode wells <NUM>, and the edge anode region <NUM>, therefore forming an anode electrical contact of the power device.

As illustrated in the aforesaid <FIG>, this remaining portion 14a extends in part also above the dielectric region 8a, at the boundary between the active area A' and the edge area A".

The outer end of the aforesaid remaining portion 14a is in any case sufficiently far from the first overlying region 10a, so that the first overlying region 10a is located, as discussed previously, in a non-active area of the power device (for example, in the case where the electrical field lines terminate at a distance of approximately <NUM> from the outer end of the remaining portion 14a, the first overlying region 10a is arranged at a distance sufficiently higher than <NUM> from the same outer end of the remaining portion 14a).

With reference to <FIG>, the manufacturing process proceeds with a chemical etching, for example with hydrofluoric acid (HF), of the dielectric region 8a, through the access window <NUM> defined between the first and second overlying regions 10a, 10b.

In particular, this etching operation is carried out via photolithographic process, with an etching mask <NUM>, represented schematically by a dashed line in the aforesaid <FIG>, which coats the entire surface of the wafer <NUM> and in particular a major part of the same overlying regions 10a, 10b, except for the area at the aforesaid access window <NUM>. In other words, the etching mask <NUM> has an opening 15a vertically corresponding to the access window <NUM>, having slightly larger dimensions, in the horizontal plane xy (in <FIG> along the axis x), than those of the access window <NUM>.

During etching, the chemical-etching agent (in the example, HF) therefore penetrates through the access window <NUM> through the dielectric region 8a, removing the underlying material (etching stops on the front surface 2a of the substrate <NUM>), without, however, involving the overlying regions 10a, 10b given the characteristics of selectivity of the etching process in regard to the material of the same overlying regions 10a, 10b.

In particular, given that wet etching is totally isotropic, an anchorage opening <NUM> is formed in the dielectric region 8a, extending vertically (along the vertical axis z) throughout the thickness of the dielectric region 8a, and which horizontally (in the horizontal plane xy, in <FIG> along the axis x, in general in a direction transverse to a direction of longitudinal extension) has a width, designated by W<NUM>, that is greater than the corresponding width, designated by W<NUM>, of the access window <NUM> (for example, satisfying the relation: W<NUM> > W<NUM> + <NUM>; in other words, there is, for example, a difference of at least <NUM> with respect to the overlying opening, i.e. the access window <NUM>, on either side along the axis x).

In detail, in the embodiment illustrated, the anchorage opening <NUM> is trapezium-shaped in cross-section, and the aforesaid dimension W<NUM> has a larger extension, at the major base of the trapezium, facing the access window <NUM>, comprised, for example, between <NUM> and <NUM> (in any case depending upon the thickness of the dielectric, the aforesaid wet etching being isotropic).

Basically, following upon etching, a respective end portion of the first and second overlying regions 10a, 10b, designated by 18a and 18b, respectively, facing the access window <NUM>, is arranged suspended and protruding over the underlying anchorage opening <NUM>.

As illustrated in <FIG>, a passivation layer <NUM>, in particular, of polyimide (other materials, for example photoresist or the like, which in any case have dielectric characteristics, may be used) is then formed above the entire surface of the wafer <NUM> (except for the area of the scribe line SL). For instance, the passivation layer is formed using fluid or viscous spin-coating techniques and is subsequently subjected to a curing step.

Following upon its formation, the passivation layer <NUM> has a an anchorage region <NUM>, which extends in the anchorage opening <NUM>, occupying it entirely, and has: a first portion 22a, within the aforesaid anchorage opening <NUM>, which assumes a corresponding conformation (in the example, with trapezoidal cross-section); and a second portion 22b, within the access window <NUM>, having a width smaller than that of the first portion (in <FIG>, along the axis x).

The aforesaid first portion 22a of the anchorage region <NUM> is located directly underneath, and in direct contact with, the end portions 18a, 18b of the first and second overlying regions 10a, 10b, and the aforesaid second portion 22b is arranged between the same end portions 18a, 18b.

The wafer <NUM> is then subjected to dicing along the scribe line SL, for formation of a die integrating the power device, here designated by <NUM> (in the example, a power diode).

The aforesaid power device <NUM> therefore has the passivation layer <NUM>, arranged at least over the dielectric region <NUM> (of thick dielectric) in the edge area A", that is appropriately anchored thanks to the presence of the corresponding anchorage region <NUM> and the associated mechanical anchorage within the anchorage opening <NUM>.

Advantageously, this anchorage region <NUM> allows the passivation layer <NUM> to remain mechanically anchored, even after thermal cycles (during electrical testing or during effective operation of the power device <NUM>), eliminating or in any case markedly reducing the possibility of delamination of the passivation layer <NUM> from the underlying material and of consequent electrical-arching phenomena.

<FIG> is a simplified top view, with parts removed for clarity, of the resulting power device <NUM> and of the corresponding die, designated by <NUM>' (having a substantially square conformation in top view).

In the embodiment illustrated, the active area A' of the power device <NUM> has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the overlying anode electrical contact (constituted by the remaining portion 14a of the front conductive layer <NUM>). The first and second overlying regions 10a, 10b have in this case the conformation of a square ring in the horizontal plane xy and entirely surround the active area A'. The passivation layer <NUM> extends above the front surface of the die <NUM>' and has the anchorage region <NUM>, which also has the shape of a square ring (in top view), being in fact arranged at the access window <NUM> defined between the aforesaid first and second overlying regions 10a, 10b.

In the variant embodiment illustrated in <FIG>, the first and second overlying regions 10a, 10b do not form a complete ring around the active area A' of the power device <NUM>, but are arranged in a distributed manner, only at the corners of the active area A', externally thereto. Consequently, also the anchorage region <NUM> is in this case present in a distributed manner, only at the aforesaid corners, being on the other hand made in a way altogether similar to what has been discussed previously.

<FIG> shows, once again in cross-sectional view, a further variant of the power device <NUM>, where the second overlying region 10b has a width in the horizontal plane xy (in <FIG> along the axis x, in general in a direction transverse to the direction of longitudinal extension) greater than the corresponding width of the first overlying region 10a.

In particular, the aforesaid second overlying region 10b has a further end 18b', opposite to the end 18b facing the access window <NUM>, which protrudes from the underlying dielectric region 8a. Consequently, the passivation layer <NUM>, once formed, has a further anchorage area, designated by <NUM>', arranged directly underneath the aforesaid further end 18b', which therefore contributes to anchoring the passivation layer <NUM> with respect to the underlying substrate <NUM> and to preventing delamination phenomena due to the thermomechanical stresses.

In an evident manner, also for this embodiment the configurations discussed previously with reference to <FIG> and <FIG> may be envisaged.

A further embodiment of the manufacturing process of the power device is now discussed.

In this case, as shown in <FIG>, a first dielectric layer <NUM>, in particular of TEOS, is first deposited above the front surface 2a of the substrate <NUM> (at which the anode wells <NUM> and the edge anode region <NUM> have previously been formed).

As illustrated in <FIG>, this first dielectric layer <NUM> is then subjected to a dopant implantation (for example, As, Ar, or some other P type dopant) through an appropriate implant mask <NUM>, in a way limited and confined to an external region, at the edge area A" and in the proximity of the scribe line SL, for formation of a doped portion <NUM>' (the width of which in the horizontal plane xy, along the axis x in <FIG>, substantially corresponds to the aforesaid width W<NUM>, as will be highlighted hereinafter).

The aforesaid doped portion <NUM>' is arranged at what constitutes, during operation, an electrically non-active area of the power device (in other words, it is arranged in an area external to the area involved by the electrical field lines due to operation of the power device).

Next, as shown in <FIG>, a second dielectric layer <NUM>, in particular once again of TEOS, is deposited above the first dielectric layer <NUM> (and the corresponding doped portion <NUM>'), the assembly constituted by the first and second dielectric layers <NUM>, <NUM> forming a thick dielectric layer, once again designated by <NUM>, within which, as has been discussed previously, the aforesaid doped portion <NUM>' is to be incorporated.

In particular, following upon the aforesaid implantation, the doped portion <NUM>' has an etch rate higher than that of the material constituting the second dielectric layer <NUM>; for example, the ratio between the etch rate of the doped portion <NUM>' and that of the second dielectric layer <NUM> is higher than or equal to two.

As illustrated in <FIG>, the thick dielectric layer <NUM> is then defined, via photolithographic process, so as to remove it (therefore leaving the front surface 2a of the substrate <NUM> exposed) in the active area A' (thus exposing the anode wells <NUM> and, at least in part, the edge anode region <NUM>) and moreover along the scribe line SL, leaving a remaining dielectric region 8a above the edge area A" (wherein the aforesaid doped portion <NUM>' is incorporated).

As illustrated in <FIG>, the front conductive layer, once again designated by <NUM>, for example a metal layer, is then formed, in a conformable manner on the front surface 2a of the substrate <NUM> (for example, by a sputtering process).

The above front conductive layer <NUM> is then defined, as illustrated in <FIG>, via photolithographic process, so as to remove it in the edge area A" and leave a remaining portion thereof, designated once again by 14a, in the active area A', in particular in direct contact with the front surface 2a of the substrate <NUM>, the anode wells <NUM>, and the edge anode region <NUM>, thus forming the anode electrical contact of the power device.

As illustrated in the aforesaid <FIG>, the remaining portion 14a extends in part also on the dielectric region 8a, at the boundary between the active area A' and the edge area A".

As shown in <FIG>, dry etching, for example plasma etching, of the dielectric region 8a is then carried out, in an area vertically corresponding to the corresponding doped portion <NUM>'.

In particular, etching is carried out through an appropriate etching mask <NUM> (represented schematically with dashed lines) so as to dig a vertical trench <NUM> throughout the thickness of the dielectric region 8a, centrally with respect to the corresponding doped portion <NUM>' (it is noted that the dry etch involves indistinctly the material of the dielectric region 8a, irrespective of doping, therefore without distinction as regards the corresponding doped portion <NUM>').

As shown in <FIG>, through the same etching mask <NUM>, which has therefore not yet been removed, a second etch is carried out, in particular a wet etch, for example with hydrofluoric acid HF.

On account of the different etch rate, the etch penetrates, in the horizontal plane xy, more into the doped portion <NUM>' than it does into the overlying material of the dielectric region 8a, thus causing removal (in the example, complete removal) of the same doped portion <NUM>', for formation of what is once again defined as the anchorage opening <NUM> and of the access window <NUM>, overlying, and in fluidic communication with, the same anchorage opening <NUM>, which is in this case also formed in the same dielectric region 8a. The anchorage opening <NUM> therefore has again, in the horizontal plane xy (in <FIG> along the axis x), a width W<NUM> greater than the corresponding width W<NUM> of the access window <NUM>.

It is noted that, in this embodiment, the end portions, once again designated by 18a, 18b, facing the access window <NUM> and suspended and protruding above the underlying anchorage opening <NUM> are the result of etching of the surface portion of the dielectric region 8a and are therefore constituted by the material of the same dielectric region 8a.

As illustrated in <FIG>, the passivation layer <NUM>, for example, of polyimide, is then formed above the entire surface of the wafer <NUM> (except for the area of the scribe line SL), using spin-coating techniques.

After its formation, the passivation layer <NUM> has the anchorage region <NUM>, which extends in the anchorage opening <NUM>, occupying it entirely, and once again has: the first portion 22a, within the same anchorage opening <NUM>, having a corresponding conformation; and the second portion 22b, within the access window <NUM>, having a dimension smaller than that of the first portion 22a in the horizontal plane xy (in <FIG>, along the axis x).

In particular, the aforesaid first portion 22a of the anchorage region <NUM> is located directly underneath, and in direct contact with, the end portions 18a, 18b of the dielectric region 8a, and the aforesaid second portion 22b is arranged between the same end portions 18a, 18b of the dielectric region 8a.

The wafer <NUM> is then subjected to dicing along the scribe line SL, for formation of the die containing the power device, once again designated by <NUM>.

Also in this case, advantageously, the anchorage region <NUM> enables the passivation layer <NUM> to remain anchored and fixed, even following upon thermal cycles and the resulting electromechanical stresses.

<FIG> is a top view, simplified and with parts removed for clarity, of the resulting power device <NUM> and of the corresponding die <NUM>' (having a substantially square conformation in top view).

In the embodiment illustrated, the active area A' of the power device <NUM> has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the remaining overlying portion 14a of the front conductive layer <NUM> (which constitutes the anode electrical contact).

The anchorage opening <NUM> and the corresponding anchorage region <NUM> of the passivation layer <NUM> have the conformation of a square ring in the horizontal plane xy itself, entirely surrounding the active area A'.

In the embodiment illustrated in <FIG>, the aforesaid anchorage opening <NUM> and the aforesaid anchorage region <NUM> do not form a complete ring around the active area A' of the power device <NUM>, but are arranged in a distributed manner only at the corners of the active area A', externally thereto.

A further embodiment of the process for manufacturing the power device is now discussed.

In this case, as illustrated in <FIG>, a sacrificial region <NUM> is first formed above the front surface 2a of the substrate <NUM>, by deposition via photolithographic process; the sacrificial region <NUM> is made of polysilicon or other appropriate material (for example, silicon nitride), which provides a chemical-etching selectivity relative to the dielectric material, for example TEOS, of which the thick dielectric layer <NUM> will then be formed.

The sacrificial region <NUM> is formed in a manner limited and confined to an external region of the power device, in the edge area A" and in the proximity of the scribe line SL, therefore being arranged in what constitutes, during operation, an electrically non-active area of the power device (in other words, being arranged in an area external to the area involved by the electrical field lines due to operation of the power device).

The sacrificial region <NUM> has, for example, a width of approximately <NUM> (in particular, the width of the sacrificial region <NUM> in the horizontal plane xy, along the axis x in Figure 6A, corresponds substantially to the aforesaid width W<NUM>, as will on the other hand be highlighted hereinafter).

Then (<FIG>), the thick dielectric layer <NUM>, for example, once again of TEOS, is deposited above the front surface 2a of the substrate <NUM> and in particular on the sacrificial region <NUM>, which is therefore incorporated within the same thick dielectric layer <NUM>.

As shown in <FIG>, the thick dielectric layer <NUM> is then defined, via photolithographic process, in a way substantially similar to what has been discussed previously, therefore so as to remove it in the active area A' and moreover along the scribe line SL, leaving a remaining dielectric region 8a above the edge area A" (wherein the aforesaid sacrificial region <NUM> is incorporated).

As illustrated in <FIG>, the manufacturing process proceeds in this case with dry etching, for example plasma etching, of the dielectric region 8a, in an area vertically corresponding to the sacrificial region <NUM>.

In particular, etching is carried out using an appropriate etching mask <NUM> (represented schematically with a dashed line), so as to dig a vertical trench <NUM> throughout the thickness of the dielectric region 8a, centrally with respect to the aforesaid sacrificial region <NUM>.

As illustrated in <FIG>, after removal of the etching mask <NUM>, a second etch is carried out, in particular a wet etch for selective removal of the remaining sacrificial region <NUM>. In particular, the etching agent penetrates into the vertical trench <NUM> and moves laterally to remove the aforesaid sacrificial region <NUM> so as to form what is once again defined as anchorage opening <NUM> in the dielectric region 8a and the access window <NUM>, overlying, and in fluidic communication with, the same anchorage opening <NUM>, which in this case is also formed in the same dielectric region 8a (the anchorage opening <NUM> once again has in the horizontal plane xy, in <FIG> along the axis x, a width W<NUM> greater than the corresponding width W<NUM> of the access window <NUM>).

The anchorage opening <NUM> has in this case a substantially rectangular shape in cross-section, and the access window has a substantially trapezoidal section (with the minor base facing the aforesaid anchorage opening <NUM>).

It is noted that, also in this embodiment, the end portions 18a, 18b, facing the access window <NUM> and suspended and protruding above the underlying anchorage opening <NUM>, are the result of etching of the surface portion of the dielectric region 8a and are integral with the same dielectric region 8a.

As illustrated in <FIG>, the front conductive layer, once again designated by <NUM>, for example of metal material, is then formed, in a conformable manner on the front surface 2a of the substrate <NUM> (for example, by a sputtering process) ; it is noted that in this case, the front conductive layer <NUM> also penetrates into the anchorage opening <NUM> and the access window <NUM>, in the example filling them.

The front conductive layer <NUM> is then defined, as illustrated in <FIG>, via photolithographic process, so as to remove it in the edge area A" and leave a remaining portion thereof, designated once again by 14a, above the active area A', in particular in direct contact with the front surface 2a of the substrate <NUM>, the anode wells <NUM>, and the edge anode region <NUM>, therefore forming the anode electrical contact of the power device. As illustrated in the aforesaid <FIG>, this remaining portion 14a extends in part also on the dielectric region 8a, at the boundary between the active area A' and the edge area A". It is noted that this etching envisages complete removal of the material within the anchorage opening <NUM> and the access window <NUM>.

As illustrated in <FIG>, the passivation layer <NUM>, for example of polyimide is then formed above the entire surface of the wafer <NUM> (except for the area of the scribe line SL), using spin-coating techniques.

Following upon its formation, the passivation layer <NUM> has in particular the anchorage region <NUM>, which extends in the anchorage opening <NUM>, occupying it entirely, and once again has: the first portion 22a, within the same anchorage opening <NUM>, having a corresponding conformation (also in this case being rectangular in section); and the second portion 22b, within the access window <NUM>, having a size smaller than that of the first portion 22a in the horizontal plane xy (in <FIG>, along the axis x).

The aforesaid first portion 22a of the anchorage region <NUM> is located also in this case directly underneath, and in direct contact with, the end portions 18a, 18b of the dielectric region 8a, and the aforesaid second portion 22b is arranged between the same end portions 18a, 18b of the dielectric region 8a.

The wafer <NUM> is then subjected to dicing along the scribe line SL, for formation of the die integrating the power device, once again designated by <NUM>.

Also in this case, advantageously, the anchorage region <NUM> enables the passivation layer <NUM> to remain anchored in a fixed manner within the anchorage opening <NUM>, even following upon thermal cycles and resulting electromechanical stresses.

<FIG> is a simplified top view, with parts removed for clarity, of the resulting power device <NUM> and of the corresponding die <NUM>' (having a substantially square conformation in top view). In the embodiment illustrated, the active area A' of the power device <NUM> has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the remaining overlying portion 14a of the front conductive layer <NUM> (which defines the anode electrical contact).

The anchorage opening <NUM> and the corresponding anchorage region <NUM> of the passivation layer <NUM> have the conformation of a square ring in the horizontal plane xy, surrounding the active area A' entirely.

In the embodiment illustrated in <FIG>, the aforesaid anchorage opening <NUM> and the aforesaid anchorage region <NUM> do not form a complete ring around the active area A' of the power device <NUM>, but are arranged in a distributed way only at the corners of the active area A', externally thereto.

The advantages of the present solution are clear from the foregoing description.

In particular, it is once again underlined that, thanks to the presence of the anchorage region <NUM>, the passivation layer <NUM> is anchored and fixed in a reliable manner, thus preventing possible delamination thereof, i.e., its partial detachment from the underlying material, on account of thermomechanical stresses due to thermal cycles.

Consequently, the present solution enables maximisation of the reliability and robustness of a resulting power device <NUM>, in particular with respect to the corresponding edge termination (from which, in use, the aforesaid delamination phenomena start), which is obtained starting from the silicon carbide substrate <NUM>.

The manufacturing process, in the embodiments described, is convenient and economically advantageous to implement, including processing steps that are in themselves standard in the semiconductor industry.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

In particular, it is underlined that the present solution can find advantageous application in any electronic device, in particular for power applications, in which anchorage of a passivation layer to an underlying material is advantageous to prevent phenomena of delamination due, for example, to thermomechanical stresses.

Moreover, it is underlined that the present solution may envisage a desired number of anchorage regions <NUM>, obtained in a way altogether corresponding to what has been discussed previously, in particular in the edge area A" of the power device <NUM>.

Provision of a plurality of anchorage regions <NUM> may in fact enable a further increase in the anchoring of the passivation layer <NUM> and therefore a further increase in the reliability of the resulting power device <NUM>.

These anchorage regions <NUM> may have any desired arrangement; for example, they may be arranged according to a grid arrangement in the aforesaid edge area A".

Claim 1:
An electronic power device (<NUM>), comprising:
a substrate (<NUM>) of silicon carbide (SiC), having a front surface (2a) and a rear surface (2b), which lie in respective planes parallel to a horizontal plane (xy) and are opposite to one another along a vertical axis (z) transverse to said horizontal plane (xy), the substrate (<NUM>) including an active area (A'), arranged in which are, at said front surface (2a), a number of doped regions (<NUM>), and an edge area (A"), being not active, distinct from and surrounding said active area (A');
a dielectric region (8a), arranged above said front surface (2a), at least in said edge area (A");
a passivation layer (<NUM>) arranged above the front surface (2a) of said substrate (<NUM>), in contact with said dielectric region (8a) in said edge area (A"),
wherein said passivation layer (<NUM>) comprises at least one anchorage region (<NUM>) that extends above the front surface (2a) of said substrate (<NUM>), throughout the thickness of said dielectric region (8a) at said edge area (A") and up to said front surface (2a), and is configured to define a mechanical anchorage for said passivation layer (<NUM>),
said anchorage region (<NUM>) comprises: a first portion (22a), arranged within said dielectric region (8a) and having a first width (W<NUM>) along an axis of said horizontal plane (xy); and a second portion (22b), overlying said first portion (22a), centrally thereto, and having a second width (W<NUM>); said first portion (22a) being arranged in direct contact, at the top, with a first and a second abutment element (18a, 18b), which are arranged laterally and on opposite side of said second portion (22b)
characterized in that
said second width (w<NUM>) is smaller than said first width (w<NUM>) along said axis of the horizontal plane (xy).