Patent Description:
Poly-resistors are characterized by their sheet resistance values. In order to reduce the chip size, the poly-resistors with high sheet resistance values are often used and fabricated in a small area, and they are extensively used in a variety of integrated circuits.

However, the depletion effect is a phenomenon in which there is unwanted variation in the threshold voltage of devices using poly-silicon as a gate material, leading to unpredictable behavior on the part of electronic circuits. It results in serious non-linearity of the poly-resistors. Accordingly, there is a need for a novel solution for suppressing the non-ideal depletion effect in poly-resistors.

<CIT> discloses a variable impedance circuit comprising a resistive layer-insulator layer field effect transistor having a source region, a drain region, and a channel therebetween, the lengths of said channel and said resistive layer lying in the same direction, electrodes on said source region and said drain region for connection to a main signal source, a capacitor connected between one end of said resistive layer and one of said regions, and a gate electrode on the other end of said resistive layer for connection to a control signal source, whereby variation of the control signal causes variation of the impedance of said channel through which said main signal flows.

<CIT> relates to a differential amplifier having polysilicon resistors, the resistances of which are controlled by digital-to-analog converters (DAC).

<CIT> discloses a differential amplifier circuit.

In accordance with the present invention there is provided a differential amplifier circuit as defined in claim <NUM>. Embodiments of the invention are presented in the depending claims.

In some embodiments, the poly-resistor includes a poly-silicon layer, a channel layer, and an insulation layer. The poly-silicon layer has a first end and a second end. The first end of the poly-silicon layer is coupled to the first terminal of the poly-resistor, and the second end of the poly-silicon layer is coupled to the second terminal of the poly-resistor. The channel layer has a first end and a second end. The first end of the channel layer is arranged for receiving the first control voltage, and the second end of the channel layer is arranged for receiving the second control voltage. The insulation layer is disposed between the poly-silicon layer and the channel layer.

In some embodiments, the first end of the channel layer is close to the first end of the poly-silicon layer, and the second end of the channel layer is close to the second end of the poly-silicon layer.

In some embodiments, the channel layer is a conductive layer, a semiconductor layer, or another poly-silicon layer.

In some embodiments, the channel layer is an n-well, and the first end and the second end of the channel layer are n+ doped regions.

In some embodiments, the channel layer is a p-well, and the first end and the second end of the channel layer are p+ doped regions.

In some embodiments, the insulation layer is made of different materials, such as a silicon dioxide layer, a field oxide (FOX) layer, or shallow trench isolation (STI) layer.

In some embodiments, the first control voltage and the second control voltage are dynamic.

In some embodiments, each of the first control voltage and the second control voltage is a linear function of the first voltage and the second voltage.

In some embodiments, the first control voltage is substantially equal to the first voltage, and the second control voltage is substantially equal to the second voltage.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings (note that <FIG> show examples that do not fall within the scope of the claims), wherein:.

In order to illustrate the purposes, features and advantages of the invention, the embodiments and figures of the invention will be described in detail as follows.

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" means the value is within an acceptable error range. One skilled in the art can solve the technical problem within a predetermined error range and achieve the proposed technical performance. Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

<FIG> is a diagram of an impedance circuit <NUM>. The impedance circuit <NUM> includes a poly-resistor <NUM> and a controller <NUM>. The poly-resistor <NUM> has a first terminal <NUM> and a second terminal <NUM>. If a second voltage V2 at the second terminal <NUM> is higher than a first voltage V1 at the first terminal <NUM> (i.e., a driving voltage difference (V2-V1) is applied to the poly-resistor <NUM>), a current through the poly-resistor <NUM> will flow from the second terminal <NUM> to the first terminal <NUM>. The controller <NUM> may be a voltage generator, a voltage divider, or a weighted summer circuit. The controller <NUM> is configured to generate a first control voltage VC1 and a second control voltage VC2 for controlling the poly-resistor <NUM>. The resistance between the first terminal <NUM> and the second terminal <NUM> of the poly-resistor <NUM> is determined according to the first control voltage VC1 and the second control voltage VC2. In one embodiment, the second control voltage VC2 is different from the first control voltage VC1.

Such a design can improve the linearity of the poly-resistor <NUM>. Please refer to the following embodiments and figures. It should be noted that these embodiments and figures are exemplary, rather than restricted limitations of the invention.

<FIG> is a diagram of a poly-resistor <NUM>. <FIG> illustrates the detailed physical structure of the poly-resistor <NUM> of <FIG>. In <FIG>, the poly-resistor <NUM> with a first terminal <NUM> and a second terminal <NUM> includes a poly-silicon layer <NUM>, a channel layer <NUM> and an insulation layer <NUM>. The poly-silicon layer <NUM> has a first end <NUM> and a second end <NUM>, which are located apart from each other. The first end <NUM> of the poly-silicon layer <NUM> is coupled to the first terminal <NUM> of the poly-resistor <NUM>, and the second end <NUM> of the poly-silicon layer <NUM> is coupled to the second terminal <NUM> of the poly-resistor <NUM>. If a second voltage V2 at the second terminal <NUM> is higher than a first voltage V1 at the first terminal <NUM> (i.e., a driving voltage difference (V2-V1) is applied to the poly-resistor <NUM>), a current through the poly-resistor <NUM> will flow from the second terminal <NUM> to the first terminal <NUM>. That is, the current may flow through the poly-silicon layer <NUM>, from the second end <NUM> to the first end <NUM>. The channel layer <NUM> may be a conductive layer, a semiconductor layer, or another poly-silicon layer which is different from the poly-silicon layer <NUM>. The channel layer <NUM> has a first end <NUM> and a second end <NUM>, which are located apart from each other. The first end <NUM> of the channel layer <NUM> is arranged for receiving the first control voltage VC1, and the second end <NUM> of the channel layer <NUM> is arranged for receiving the second control voltage VC2. In some embodiments, the first end <NUM> of the channel layer <NUM> is closer to the first end <NUM> of the poly-silicon layer <NUM> than to the second end <NUM> of the channel layer <NUM>, and the second end <NUM> of the channel layer <NUM> is closer to the second end <NUM> of the poly-silicon layer <NUM> than to the first end <NUM> of the channel layer <NUM>. As a result, the first control voltage VC1 controls the operation characteristic (e.g., the resistance) of the first end <NUM> of the poly-silicon layer <NUM>, and the second control voltage VC2 controls the operation characteristic (e.g., the resistance) of the second end <NUM> of the poly-silicon layer <NUM>. The insulation layer <NUM> may be made of any nonconductive material. The insulation layer <NUM> is disposed between the poly-silicon layer <NUM> and the channel layer <NUM>, and is configured to isolate the poly-silicon layer <NUM> from the channel layer <NUM>.

Please refer to <FIG> further in view of <FIG> and understand the operation theory of the invention. To suppress the depletion effect of the poly-resistor <NUM>, the first control voltage VC1 and the second control voltage VC2 may be dynamic, instead of being constant values. For example, the first control voltage VC1 and the second control voltage VC2 may be determined according to the first voltage V1 at the first terminal <NUM> of the poly-resistor <NUM>, and the second voltage V2 at the second terminal <NUM> of the poly-resistor <NUM>. That is, each of the first control voltage VC1 and the second control voltage VC2 may be a function of the first voltage V1 and the second voltage V2. The aforementioned functions may be linear and expressed as the following equations (<NUM>) to (<NUM>):
<MAT>
<MAT>
<MAT> where "VC1" represents the first control voltage VC1, "VC2" represents the second control voltage VC2, "V1" represents the first voltage V1, "V2" represents the second voltage V2, and each of "A", "B", "C", and "D" represents a respective value.

The above values A, B, C, and D are adjustable in response to different requirements. Specifically, when the controller <NUM> dynamically adjusts the first control voltage VC1 and the second control voltage VC2 in response to the first voltage V1 and the second voltage V2, the depletion effect of the poly-resistor <NUM> can be suppressed. The proposed impedance circuit is more linear and more concentrated than the conventional poly-resistor in which only one control voltage is applied to the poly-resistor, or the control voltage applied to the poly-resistor is fixed.

In some embodiments, the first control voltage VC1 is substantially equal to the first voltage V1, and the second control voltage VC2 is substantially equal to the second voltage V2. That is, according to the equations (<NUM>) to (<NUM>), the values A and D are both set to <NUM>, and the values B and C are both set to <NUM>. Please refer to the physical structure of <FIG>. If the first control voltage VC1 is equal to the first voltage V1 and the second control voltage VC2 is equal to the second voltage V2, the control voltage difference (e.g., VC2-VC1) between the second control voltage VC2 and the first control voltage VC1 will be the same as the driving voltage difference (e.g.,V2-V1) between the second terminal <NUM> and the first terminal <NUM> of the poly-resistor <NUM>. The control voltage difference (e.g., VC2-VC1) is uniformly distributed over the channel layer <NUM>, and it is consistent with the driving voltage difference (e.g.,V2-V1) which is uniformly distributed over the poly-silicon layer <NUM>. With such a design, the channel layer <NUM> has almost the same voltage level distribution as that of the poly-silicon layer <NUM>, and no effective voltage difference exists between the channel layer <NUM> and the poly-silicon layer <NUM>. Therefore, compared with the conventional method applying only one control voltage, the depletion effect of the poly-resistor <NUM> can be eliminated, and the poly-resistor <NUM> can provide resistance to accomplish better and more concentrated linearity.

<FIG> is a diagram of a poly-resistor <NUM>. <FIG> is similar to <FIG>. In the embodiment of <FIG>, a channel layer <NUM> of the poly-resistor <NUM> is an N-type doped layer, which may be configured in a P-type doped layer <NUM>, and a first end <NUM> and a second end <NUM> of the channel layer <NUM> are n+ doped regions. An insulation layer <NUM> of the poly-resistor <NUM> can be of different materials, such as a silicon dioxide layer, a field oxide (FOX) layer, or a Shallow Trench Isolation (STI) layer, but is not limited thereto. Other features of the poly-resistor <NUM> of <FIG> are similar to those of the poly-resistor <NUM> of <FIG>. <FIG> is a diagram of a poly-resistor <NUM>. <FIG> is similar to <FIG>. In the embodiment of <FIG>, a channel layer <NUM> of the poly-resistor <NUM> is a P-type doped layer, which may be configured in an N-type doped layer <NUM>, and a first end <NUM> and a second end <NUM> of the channel layer <NUM> are p+ doped regions. An insulation layer <NUM> can be of different materials, such as a silicon dioxide layer, a field oxide (FOX) layer, or a STI layer, but is not limited thereto. Other features of the poly-resistor <NUM> of <FIG> are similar to those of the poly-resistor <NUM> of <FIG>.

<FIG> is a diagram of an impedance circuit 500A. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the impedance circuit 500A includes a first poly-resistor <NUM>, a second poly-resistor <NUM>, and a controller <NUM>. The first poly-resistor <NUM> has a first terminal <NUM> and a second terminal <NUM>. The second poly-resistor <NUM> has a first terminal <NUM> and a second terminal <NUM>. The first terminal <NUM> of the second poly-resistor <NUM> is coupled to the second terminal <NUM> of the first poly-resistor <NUM>. The controller <NUM> is configured to generate a first control voltage VC1, a second control voltage VC2, a third control voltage VC3, and a fourth control voltage VC4 for controlling the first poly-resistor <NUM> and the second poly-resistor <NUM>. The resistance between the first terminal <NUM> and the second terminal <NUM> of the first poly-resistor <NUM> is determined according to the first control voltage VC1 and the second control voltage VC2. In one embodiment, the second control voltage VC2 is different from the first control voltage VC1. The resistance between the first terminal <NUM> and the second terminal <NUM> of the second poly-resistor <NUM> is determined according to the third control voltage VC3 and the fourth control voltage VC4. In one embodiment, the fourth control voltage VC4 is different from the third control voltage VC3.

In the impedance circuit 500A, a first poly-resistor <NUM> and a second poly-resistor <NUM> are coupled in series. The first control voltage VC1, the second control voltage VC2, the third control voltage VC3 and the fourth control voltage VC4 may be dynamic. The first control voltage VC1 and the second control voltage VC2 may be determined according to a first voltage V1 at the first terminal <NUM> of the first poly-resistor <NUM>, and a second voltage V2 at the second terminal <NUM> of the first poly-resistor <NUM>. Each of the first control voltage VC1 and the second control voltage VC2 may be a function of the first voltage V1 and the second voltage V2. The aforementioned function may be linear. For example, the first control voltage VC1 may be substantially equal to the first voltage V1, and the second control voltage VC2 may be substantially equal to the second voltage V2, but they are not limited thereto. The third control voltage VC3 and the fourth control voltage VC4 may be determined according to the second voltage V2 at the first terminal <NUM> of the second poly-resistor <NUM>, and a third voltage V3 at the second terminal <NUM> of the second poly-resistor <NUM>. Each of the third control voltage VC3 and the fourth control voltage VC4 may be a function of the second voltage V2 and the third voltage V3. The aforementioned function may be linear. For example, the third control voltage VC3 may be substantially equal to the second voltage V2, and the fourth control voltage VC4 may be substantially equal to the third voltage V3, but they are not limited thereto. Other features of the impedance circuit 500A of <FIG> are similar to those of the impedance circuit <NUM> of <FIG>. Accordingly, the two embodiments can achieve similar levels of performance. It should be noted that the impedance circuit 500A may include three or more poly-resistors which are coupled in series and controlled by the controller in a similar way although there are only two poly-resistors displayed in <FIG>.

<FIG> is a diagram of an impedance circuit 500B. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the impedance circuit 500B further includes a first controller <NUM> and a second controller <NUM>. Such a design can also suppress the non-linear depletion effect. The first controller <NUM> is configured to generate the first control voltage VC1 and the second control voltage VC2 for controlling the first poly-resistor <NUM>. The second controller <NUM> is configured to generate the third control voltage VC3 and the fourth control voltage VC4 for controlling the second poly-resistor <NUM>. Similarly, the first control voltage VC1, the second control voltage VC2, the third control voltage VC3, and the fourth control voltage VC4 may be dynamic. In the impedance circuit 500B, the second poly-resistor <NUM> is separate from the first poly-resistor <NUM>. The first control voltage VC1 and the second control voltage VC2 may be determined according to a first voltage V1 at the first terminal <NUM> of the first poly-resistor <NUM>, and a second voltage V2 at the second terminal <NUM> of the first poly-resistor <NUM>. Each of the first control voltage VC1 and the second control voltage VC2 may be a function of the first voltage V1 and the second voltage V2. The aforementioned function may be linear. For example, the first control voltage VC1 may be substantially equal to the first voltage V1, and the second control voltage VC2 may be substantially equal to the second voltage V2, but they are not limited thereto. The third control voltage VC3 and the fourth control voltage VC4 may be determined according to a third voltage V3 at the first terminal <NUM> of the second poly-resistor <NUM>, and a fourth voltage V4 at the second terminal <NUM> of the second poly-resistor <NUM>. Each of the third control voltage VC3 and the fourth control voltage VC4 may be a function of the third voltage V3 and the fourth voltage V4. The aforementioned function may be linear. For example, the third control voltage VC3 may be substantially equal to the third voltage V3, and the fourth control voltage VC4 may be substantially equal to the fourth voltage V4, but they are not limited thereto. Other features of the impedance circuit 500B of <FIG> are similar to those of the impedance circuit 500A of <FIG>. It should be noted that the impedance circuit 500B may include three or even more poly-resistors which are respectively controlled by three or more controllers in a similar way.

The proposed impedance circuit and the poly-resistor therein can be applied to a variety of circuits. Please refer to the following embodiments in <FIG>.

<FIG> is a diagram of a differential or pseudo-differential amplifier 600A according to an embodiment of the invention. In the embodiment of <FIG>, the differential or pseudo-differential amplifier 600A generates a positive output voltage VOP and a negative output voltage VON according to a positive input voltage VIP and a negative input voltage VIN. Specifically, the differential or pseudo-differential amplifier 600A includes a main operational amplifier <NUM>, an auxiliary operational amplifier <NUM>, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a controller <NUM>, a first poly-resistor <NUM>, and a second poly-resistor <NUM>. The first resistor R1 is coupled between the negative input voltage VIN and a negative input terminal of the main operational amplifier <NUM>. The second resistor R2 is coupled between the positive input voltage VIP and a positive input terminal of the main operational amplifier <NUM>. The third resistor R3 is coupled between the negative input terminal and a positive output terminal (i.e., the positive output voltage VOP) of the main operational amplifier <NUM>. The fourth resistor R4 is coupled between the positive input terminal and a negative output terminal (i.e., the negative output voltage VON) of the main operational amplifier <NUM>. An inner voltage VAV is between the first poly-resistor <NUM> and the second resistor <NUM>, and it may be close to a common voltage VCM. The first poly-resistor <NUM> is coupled between the positive output terminal (i.e., the positive output voltage VOP) of the main operational amplifier <NUM> and the inner voltage VAV. The second poly-resistor <NUM> is coupled between the inner voltage VAV and the negative output terminal (i.e., the negative output voltage VON) of the main operational amplifier <NUM>. The auxiliary operational amplifier <NUM> compares the inner voltage VAV with the common voltage VCM, so as to adjust a DC (Direct Current) offset of the main operational amplifier <NUM> with a negative feedback mechanism. The common voltage VCM may be set to a ground voltage VSS (e.g., 0V). The controller <NUM> is configured to generate a first control voltage VC1 and a second control voltage VC2 for controlling the first poly-resistor <NUM>, and further generate a third control voltage VC3 and a fourth control voltage VC4 for controlling the second poly-resistor <NUM>. In some embodiments, the first control voltage VC1, the second control voltage VC2, the third control voltage VC3, and the fourth control voltage VC4 are determined according to the positive output voltage VOP, the negative output voltage VON, and the inner voltage VAV. Specifically, each of the first control signal VC1 and the second control signal VC2 may be dynamic and be a function of the positive output voltage VOP and the inner voltage VAV; and each of the third control signal VC3 and the fourth control signal VC4 may be dynamic and be a function of the inner voltage VAV and the negative output voltage VON. For example, the first control voltage VC1 may be substantially equal to the positive output voltage VOP, the second control voltage VC2 and the third control voltage VC3 may be both substantially equal to the inner voltage VAV, and the fourth control voltage VC4 may be substantially equal to the negative output voltage VON, but they are not limited thereto. In the embodiment of <FIG>, each of the first poly-resistor <NUM> and the second poly-resistor <NUM> is a common-mode feedback resistor used in the differential or pseudo-differential amplifier 600A.

<FIG> is a diagram of a differential or pseudo-differential amplifier 600B according to an embodiment of the invention. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the controller <NUM> controls the first poly-resistor <NUM> and the second resistor <NUM> according to the positive input voltage VIP and the negative input voltage VIN, which are related to the positive output voltage VOP and the negative output voltage VON. <FIG> is a diagram of a differential or pseudo-differential amplifier 600C according to an embodiment of the invention. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the differential or pseudo-differential amplifier 600C generates the positive output voltage VOP and the negative output voltage VON according to a positive input current IIP and a negative input current IIN. <FIG> is a diagram of a differential or pseudo-differential amplifier 600D according to an embodiment of the invention. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the controller <NUM> controls the first poly-resistor <NUM> and the second resistor <NUM> according to the positive input current IIP and the negative input current IIN, which are related to the positive output voltage VOP and the negative output voltage VON. Other features of the differential or pseudo-differential amplifiers 600B, 600C, and 600D of <FIG>, <FIG> are similar to those of the differential or pseudo-differential amplifier 600A of <FIG>. Accordingly, these embodiments can achieve similar levels of performance.

<FIG> is a diagram of a differential-to-single-ended amplifier 700A according to an example not falling within the scope of the claimed invention. In the example of <FIG>, the differential-to-single-ended amplifier 700A generates a positive output voltage VOP according to a positive input voltage VIP and a negative input voltage VIN. Specifically, the differential-to-single-ended amplifier 700A includes a main operational amplifier <NUM>, a first resistor R1, a second resistor R2, a first poly-resistor <NUM>, a second poly-resistor <NUM>, a first controller <NUM>, and a second controller <NUM>. The first resistor R1 is coupled between the negative input voltage VIN and a negative input terminal of the main operational amplifier <NUM>. The second resistor R2 is coupled between the positive input voltage VIP and a positive input terminal of the main operational amplifier <NUM>. A positive inner voltage VIPX is at the positive input terminal of the main operational amplifier <NUM>. The first poly-resistor <NUM> is coupled between the negative input terminal and a positive output terminal (i.e., the positive output voltage VOP) of the main operational amplifier <NUM>. The second poly-resistor <NUM> is coupled between the positive input terminal of the main operational amplifier <NUM> and a ground voltage VSS. The first controller <NUM> is configured to generate a first control voltage VC1 and a second control voltage VC2 for controlling the first poly-resistor <NUM>. The second controller <NUM> is configured to generate a third control voltage VC3 and a fourth control voltage VC4 for controlling the second poly-resistor <NUM>. In some examples, the first control voltage VC1, the second control voltage VC2, the third control voltage VC3, and the fourth control voltage VC4 are determined according to the positive output voltage VOP, the positive inner voltage VIPX, and the ground voltage VSS. Specifically, each of the first control signal VC1 and the second control signal VC2 may be dynamic and be a function of the positive inner voltage VIPX and the positive output voltage VOP; and each of the third control signal VC3 and the fourth control signal VC4 may be dynamic and be a function of the positive inner voltage VIPX and the ground voltage VSS. For example, the first control voltage VC1 and the third control voltage VC3 may be substantially equal to the positive inner voltage VIPX, the second control voltage VC2 may be substantially equal to the positive output voltage VOP, and the fourth control voltage VC4 may be substantially equal to the ground voltage VSS, but they are not limited thereto. In the embodiment of <FIG>, each of the first poly-resistor <NUM> and the second poly-resistor <NUM> is a feedback resistor used in the differential-to-single-ended amplifier 700A.

<FIG> is a diagram of a differential-to-single-ended amplifier 700B according to an example not falling within the scope of the claimed invention. <FIG> is similar to <FIG>. In the example of <FIG>, the first controller <NUM> controls the first poly-resistor <NUM> according to the positive input voltage VIP, which is related to the positive output voltage VOP. <FIG> is a diagram of a differential-to-single-ended amplifier 700C according to an example not falling within the scope of the claimed invention. <FIG> is similar to <FIG>. In the example of <FIG>, the differential-to-single-ended amplifier 700C generates the positive output voltage VOP according to a positive input current IIP and a negative input current IIN <FIG> is a diagram of a differential-to-single-ended amplifier 700D according to an example not falling within the scope of the claimed invention. <FIG> is similar to <FIG>. In the example of <FIG>, the first controller <NUM> controls the first poly-resistor <NUM> according to the positive input current IIP, which is related to the positive output voltage VOP. Other features of the differential-to-single-ended amplifiers 700B, 700C, and 700D of <FIG>, <FIG> are similar to those of the differential-to-single-ended amplifier 700A of <FIG>. Accordingly, these examples can achieve similar levels of performance.

<FIG> is a diagram of an inverting amplifier 800A according to an example not falling within the scope of the claimed invention. In the example of <FIG>, the inverting amplifier 800A generates a positive output voltage VOP according to a negative input voltage VIN. Specifically, the inverting amplifier 800A includes a main operational amplifier <NUM>, a first resistor R1, a controller <NUM>, and a poly-resistor <NUM>. The first resistor R1 is coupled between the negative input voltage VIN and a negative input terminal of the main operational amplifier <NUM>. A common voltage VCM is at a positive input terminal of the main operational amplifier <NUM>. The common voltage VCM may be set to a ground voltage VSS (e.g., 0V). The poly-resistor <NUM> is coupled between the negative input terminal and a positive output terminal (i.e., the positive output voltage VOP) of the main operational amplifier <NUM>. The controller <NUM> is configured to generate a first control voltage VC1 and a second control voltage VC2 for controlling the poly-resistor <NUM>. In some embodiments, the first control voltage VC1 and the second control voltage VC2 are determined according to the positive output voltage VOP and the common voltage VCM. Specifically, each of the first control signal VC1 and the second control signal VC2 may be dynamic and be a function of the positive output voltage VOP and the common voltage VCM. For example, the first control voltage VC1 may be substantially equal to the common voltage VCM, and the second control voltage VC2 may be substantially equal to the positive output voltage VOP, but they are not limited thereto. In the example of <FIG>, the poly-resistor <NUM> is a feedback resistor used in the inverting amplifier 800A.

<FIG> is a diagram of an inverting amplifier 800B according to an example not falling within the scope of the claimed invention. <FIG> is similar to <FIG>. In the embodiment of <FIG>, the inverting amplifier 800B generates the positive output voltage VOP according to a negative input current IIN. <FIG> is a diagram of an inverting amplifier 800C according to an example not falling within the scope of the claimed invention. <FIG> is similar to <FIG>. In the example of <FIG>, the controller <NUM> controls the poly-resistor <NUM> according to the positive input current IIN, which is related to the positive output voltage VOP. Other features of the inverting amplifiers 800B and 800C of <FIG> and <FIG> are similar to those of the inverting amplifier 800A of <FIG>. Accordingly, these examples can achieve similar levels of performance.

The invention proposes a novel differential amplifier circuit including a poly-resistor and a controller. The proposed controller can compensate for non-linearity of the poly-resistor. Alternatively, the poly-resistor may be further divided into a plurality of sub-poly-resistors coupled in series, without affecting the performance of the proposed impedance circuit. To be brief, the proposed impedance circuit can eliminate the depletion effect of the poly-resistor, and make the poly-resistor be more linear and subject to Ohm's law.

Note that the above voltages, currents, resistances, inductances, capacitances and other element parameters are not limitations of the invention. A designer can adjust these parameters according to different requirements. The impedance circuit and poly-resistor of the invention are not limited to the configurations of <FIG>. The invention may merely include any one or more features of any one or more configurations of <FIG>. In other words, not all of the features displayed in the figures should be implemented in the impedance circuit and poly-resistor of the invention.

Use of ordinal terms such as "first", "second", "third", etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.

Claim 1:
A differential amplifier circuit (600A, 600B, 600C, 600D) comprising:
a main operational amplifier (<NUM>), the main operational amplifier (<NUM>) having a positive output (VOP) and a negative output (VON), and having a positive input and a negative input;
a resistor (R3) connecting the positive output (VOP) to the negative input, and a resistor (R4) connecting the negative output (VON) to the positive input;
wherein the differential amplifier circuit further comprises:
a first poly-resistor (<NUM>) and a second poly-resistor (<NUM>), one end of the first poly-resistor (<NUM>) being connected to the positive output (VOP), another end of the first poly-resistor (<NUM>) being connected to an inner voltage node (VAV), one end of the second poly-resistor (<NUM>) being connected to the negative output (VON), another end of the second poly-resistor (<NUM>) being connected to the inner voltage node (VAV);
a controller (<NUM>), the controller (<NUM>) being configured to generate a first control voltage (VC1) and a second control voltage (VC2) for controlling the first poly-resistor (<NUM>), and to generate a third control voltage (VC3) and a fourth control voltage (VC4) for controlling the second poly-resistor (<NUM>);
wherein the second control voltage (VC2) is configured to be different from the first control voltage (VC1), and the fourth control voltage (VC4) is configured to be different from the third control voltage (VC3);
an auxiliary operational amplifier (<NUM>), wherein the auxiliary operational amplifier (<NUM>) is operable to compare an inner voltage (VAV) at the inner node (VAV) with a common voltage (VCM) so as to adjust a DC offset of the main operational amplifier (<NUM>) with a negative feedback mechanism.