Patent Description:
This application is a continuation claiming the benefit under <NUM> U. § <NUM> of <CIT>, under Attorney Docket No. G0766.70254US01, and entitled "BI-DIRECTIONAL DATA ISOLATOR WITH DYNAMIC COMMUNICATION".

<CIT> is a continuation claiming the benefit under <NUM> U. § <NUM> of <CIT>, under Attorney Docket No. G0766.70254US00, and entitled "BI-DIRECTIONAL DATA ISOLATOR WITH DYNAMIC COMMUNICATION".

The present disclosure relates to bi-directional data isolator configurations that enable dynamic communication.

Data isolators may be, for example, electronic devices that are configured to receive data at an input port and provide the data at an output port that is isolated from the input port. Thus, the data isolator may prevent certain disturbances from propagating from the input port to the output port or vice-versa. Data isolators may employ isolation barriers to isolate the input port from the output port. Typically, a data isolator includes a transmitter disposed on one side of an isolation barrier and a receiver disposed on an opposite side of the isolation barrier. The transmitter typically transmits a data signal representative of the information received at the input port across an isolation barrier to the receiver. In turn, the receiver processes the received data signal to recover the information provided to the input port. The actions of the transmitter and the receiver may be coordinated by a clock signal that oscillates between two states at a fixed frequency. <CIT> discloses a bidirectional communication circuit having a first circuit transmitting data across an isolator to a second circuit, where the size of the packet or an evaluation time for a receive condition to be satisfied can be adjusted during operation of the communication circuit.

Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

According to at least one aspect, a bi-directional data isolator is provided according to claim <NUM>.

According to at least one aspect, a method of operating a bi-directional data isolator is provided according to claim <NUM>.

Various aspects and embodiments of the application will be described with reference to the following figures. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.

According to some aspects, data isolators that enable dynamic communication are provided. A conventional data isolator generally transmits information in a static fashion. For example, a frequency of the clock signal that coordinates the transmitter and receiver may be fixed. Additionally, the number of bits transmitted per clock cycle may also be fixed. The inventors have appreciated that such a conventional approach fails to provide flexibility for handling transmission of data packets of various sizes. For example, a sensor may periodically transmit small pieces of data (e.g., containing less than <NUM> bits) indicative of a parameter sensed by the sensor through the data isolator and occasionally need to transmit significantly larger pieces of data (e.g., containing more than <NUM> bits) to send operating status information (e.g., fault codes) through the data isolator. As a result, conventional data isolators may divide the larger pieces of data into multiple smaller packets that can be individually transmitted. Dividing up the data packets in such a manner reduces the speed at which the entire piece of data is transmitted across the isolation barrier and increases the amount of communication overhead required to send the piece of data. Accordingly, aspects of the present disclosure provide data isolators with dynamic communication schemes that enable data packets of different sizes to be transmitted across the isolation barrier.

In some embodiments, the data isolator may transmit data in a first direction across an isolation barrier (e.g., a capacitive isolation barrier, an optical isolation barrier, and/or an inductive isolation barrier) while a clock signal is in a first state and transmits data in a second, opposite direction across the isolation barrier while the clock signal is in a second state. In these embodiments, the clock signal may have a variable frequency that enables a variable number of bits to be transmitted in each direction across the isolation in a given cycle of the clock signal. For example, the clock frequency may be reduced to increase the amount of time the clock signal spends in each of the first and second states during a given cycle. Thus, the number of bits that may be transmitted while the clock signal is in a given state is increased. Increasing the number of bits in a given clock cycle may advantageously permit larger pieces of data to be transmitted in a fewer number of packets and, as a result, reduce the total amount of time required to transmit the piece of data across the isolation barrier. Conversely, the clock frequency can be increased to reduce the amount of time the clock signal is in a given state and, as a result, reduce the number of bits that may be transmitted while the clock signal in the given state. Reducing the number of bits in a given clock cycle may advantageously permit smaller pieces of data to be transmitted faster across the isolation barrier because the duration of each clock cycle is reduced. Thus, the clock frequency and/or the number of bits transmitted in a given clock cycle may be adjusted to best suit the information to be transmitted across the isolation barrier.

The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.

<FIG> shows an example data isolator <NUM>, according to some embodiments. The data isolator <NUM> may provide data isolation between a first port <NUM> and a second port <NUM>. The first port <NUM> may be in a first voltage domain <NUM> while the second port <NUM> may be in a second voltage domain <NUM>. The first voltage domain <NUM> may be a different voltage domain from the second voltage domain <NUM>. For example, the voltage domain at the first port <NUM> may be a lower (or higher) voltage domain than the second voltage domain <NUM>. Alternatively, the first voltage domain <NUM> may be the same as the second voltage domain <NUM>.

As shown in <FIG>, the data isolator <NUM> comprises a first circuit <NUM> that communicates with a second circuit <NUM> over an isolation barrier <NUM> shown as an inductive isolation barrier that comprises transformer <NUM>. The first circuit <NUM> is coupled between the first port <NUM> and a first coil <NUM> of the transformer <NUM>. The second circuit <NUM> is coupled between the second port <NUM> and a second coil <NUM> of the transformer <NUM>. The first circuit <NUM> may comprise a transmit circuit <NUM> that enables transmission of data across the isolation barrier <NUM> in a first direction to the second circuit <NUM> and a receive circuit <NUM> that enables receipt of data transmitted by the second circuit <NUM> across the isolation barrier <NUM> in a second, opposite direction. The second circuit <NUM> may comprise a transmit circuit <NUM> that enables transmission of data across the isolation barrier <NUM> in the second direction to the first circuit <NUM> and a receive circuit <NUM> that enables receipt of data transmitted by the first circuit <NUM> across the isolation barrier <NUM> in the first direction. Thus, the first and second circuits <NUM> and <NUM>, respectively, may operate in concert to enable bi-directional communication between the first port <NUM> and the second port <NUM>.

The isolation barrier <NUM> may be configured to isolate the first port <NUM> from the second port <NUM>. The isolation barrier <NUM> may comprise one or more isolators such as transformers, optical isolators, and capacitive isolators. For example, the isolation barrier <NUM> may comprise a single isolator across which the data and the clock signal are transmitted. Alternatively, the isolation barrier may comprise two or more isolators. For example, a first isolator may be employed for transmission of data and a second isolator may be employed for transmission of a clock signal. In another example, a first isolator may be employed for transmission of data and the clock signal in a first direction across the isolation barrier and a second isolator may be employed for transmission of data in a second, opposite direction across the isolation barrier.

The isolation barrier <NUM> may be implemented, for example, as a capacitive isolation barrier using one or more capacitors, an optical isolation barrier using one or more optical components, and/or as an inductive isolation barrier <NUM> using one or more transformers. In the particular implementation shown in <FIG>, the isolation barrier <NUM> is implemented as an inductive isolation barrier that employs the transformer <NUM> to provide the isolation. The transformer <NUM> may be, for example, configured to transfer energy via electromagnetic induction. The transformer <NUM> may have any of a variety of constructions. For example, the transformer <NUM> may be constructed as a core type transformer where the windings surround the core, a shell type transformer where the windings are at least partially surrounded by the core, and/or a planar transformer where each of the coils are disposed within a respective <NUM>-dimensional plane. Additionally, the transformer <NUM> may be a micro-transformer that is implemented within a semiconductor die.

The transmit circuits <NUM> and <NUM> may be configured to transmit data across the isolation barrier <NUM>. For example, the transmit circuit <NUM> may be configured to transmit data across the isolation barrier <NUM> in a first direction to the receive circuit <NUM> and the transmit circuit <NUM> may be configured to transmit data across the isolation barrier <NUM> in a second direction to receive circuit <NUM>. The data transmitted by each of the transmit circuit <NUM> and the transmit circuit <NUM> may be received, for example, via the first port <NUM> and the second port <NUM>, respectively. One (or both) of the transmit circuits <NUM> and <NUM> may transmit a clock signal across the isolation barrier <NUM> along with the data to coordinate operation of the first and second circuits <NUM> and <NUM>, respectively. For example, the clock signal may oscillate between a first state where only the transmit circuit <NUM> is permitted to transmit data across the isolation barrier <NUM> and a second state where only the transmitter <NUM> is permitted to transmit data across the isolation barrier <NUM>. Thus, collisions caused by both transmitters <NUM> and <NUM> attempting to transmit data simultaneously may be avoided.

The receive circuits <NUM> and <NUM> may be configured to receive data transmitted across the isolation barrier <NUM>. For example, the receive circuit <NUM> may be configured to receive data transmitted across the isolation barrier <NUM> by transmit circuit <NUM> and the receive circuit <NUM> may be configured to receive the data transmitted across the isolation barrier <NUM> by the transmit circuit <NUM>. The data received by each of receive circuit <NUM> and receive circuit <NUM> may be provided to, for example, the first port <NUM> and the second port <NUM>, respectively. The receive circuits <NUM> and/or <NUM> may employ the clock signal transmitted along with the data signal to, for example, identify the source of the data being received. For example, the transmitter <NUM> may be the source of the received data when the clock signal is in a first state and the transmitter <NUM> may be the source of the received data when the clock signal is in a second state. Additionally (or alternatively), one or both of the receive circuits <NUM> and <NUM> may output the clock signal along with the received data. Thus, the clock signal may be employed by external device(s) coupled to the first port <NUM> and/or the second port <NUM>.

In some embodiments, the transmit circuits <NUM> and <NUM> may be configured to transmit data in a dynamic fashion to enable data packets of different sizes to be transmitted across the isolation barrier <NUM>. Such a transmission scheme may be accomplished by, for example, varying a frequency of the clock signal. Thus, the amount of time the clock signal spends in a given state is variable and the number of data bits that may be transmitted in a clock cycle are variable. For example, the clock frequency may nominally be approximately <NUM> megahertz and eight bits may be transmitted per clock cycle. In this example, the clock frequency may be reduced (e.g., to <NUM> kilohertz) to enable up to sixteen bits to be transmitted per clock cycle. Conversely, the clock frequency may be increased (e.g., to <NUM> megahertz) to enable up to <NUM> bits to be transmitted per clock cycle. It should be appreciated that the particular range of clock frequencies and the associated range of bits that may be transmitted per clock cycle may vary based on the particular implementation. In some embodiments, the minimum clock frequency may be no more than <NUM> kilohertz (e.g., <NUM> kilohertz, <NUM> kilohertz, <NUM> kilohertz, <NUM> kilohertz, <NUM> kilohertz, <NUM> kilohertz, etc.) and the maximum clock frequency may be at least <NUM> megahertz (e.g., <NUM> megahertz, <NUM> megahertz, <NUM> megahertz, <NUM> megahertz etc.). Particular non-limiting example ranges for the clock frequency include: (<NUM>) <NUM> kilohertz to <NUM> Megahertz; (<NUM>) <NUM> kilohertz to <NUM> Megahertz; (<NUM>) <NUM> kilohertz to <NUM> Megahertz; and (<NUM>) <NUM> kilohertz to <NUM> Megahertz. In some embodiments, the number of bits transmitted per clock cycle may vary within a range with a minimum number of bits that is no more than <NUM> (e.g., <NUM> bit, <NUM> bits, etc.) and a maximum number of bits that is at least <NUM> (e.g., <NUM> bits, <NUM>, bits, <NUM> bits, <NUM> bits, etc.). Particular non-liming example ranges for the number of bits to be transmitted per clock cycle include: (<NUM>) <NUM> bits to <NUM> bits; (<NUM>) <NUM> bits to <NUM> bits; and (<NUM>) <NUM> bits to <NUM> bits. As a result of the variable clock frequency and the variable number of bits transmitter per clock cycle, the ratio of the data rate to the clock frequency may also vary within a range. In some embodiments, the ratio of the data rate to the clock frequency may have a minimum ratio of no more than <NUM>:<NUM> (e.g., the data rate in bits per second equals the clock frequency in hertz) and a maximum ratio of at least <NUM>:<NUM> (e.g., the data rate in bits per second is four times larger than the clock frequency in hertz). Particular non-liming example ranges for the ratio include: (<NUM>) <NUM>:<NUM> to <NUM>:<NUM>; (<NUM>) <NUM>:<NUM> to <NUM>:<NUM>; and (<NUM>) <NUM>:<NUM> to <NUM>:<NUM>.

Referring to <FIG>, an example communication sequence <NUM> is depicted that may be employed to achieve dynamic data transmission. As shown, the communication sequence <NUM> includes a first circuit transmit sequence <NUM> that may be transmitted by transmit circuit <NUM>, a second transmit sequence <NUM> that may be transmitted by transmit circuit <NUM>, and a clock signal <NUM> that varies between a first state <NUM> and a second state <NUM>. The first transmit sequence <NUM> comprises a first clock marker <NUM>, a first packet <NUM>, a second clock marker <NUM>, and a no transmission period <NUM>. The second transmit sequence <NUM> comprises a no transmission period <NUM> and a second packet <NUM>. The communication sequence <NUM> starts at a communication start <NUM> and is divided into four periods shown as first, second, third, and fourth periods <NUM>, <NUM>, <NUM>, and <NUM>, respectively.

During the first period <NUM>, the transmit circuit <NUM> transmits the first clock marker <NUM> while the transmit circuit <NUM> is in no transmission period <NUM> (e.g., transmit circuit <NUM> is idle). The first clock marker <NUM> may be a signal that is representative of a transition in the clock signal <NUM> between the first state <NUM> and the second state <NUM>. For example, the first clock marker <NUM> may be a unique sequence of one or more pulses, such as a sequence of three pulses having a sequence of polarities that is positive-negative-positive.

During the second period <NUM>, the transmit circuit <NUM> transmits a first packet <NUM> while the transmit circuit <NUM> is in the no transmission period <NUM>. The first packet <NUM> may include data that is being transmitted between the first and second ports <NUM> and <NUM>, respectively. The first packet <NUM> may comprise, for example, a sequence of pulses each representative of a state of a bit being transmitted. The size of the first packet <NUM> may vary based on the duration of the second period <NUM>. As the duration of the second period <NUM> increases, more bits may be transmitted in the first packet <NUM>. Conversely, the size of the first packet <NUM> may be reduced as the duration of the second period <NUM> is decreased.

During the third period <NUM>, the transmit circuit <NUM> transmits a second clock marker <NUM> while the transmit circuit <NUM> is in the no transmission period <NUM>. The second clock marker <NUM> may be a signal that is representative of a transition in the clock signal <NUM> between the second state <NUM> back to the first state <NUM>. For example, the second clock marker <NUM> may be a unique sequence of one or more pulses, such as a sequence of three pulses having a sequence of polarities that is negative-positive-negative.

During the fourth period <NUM>, the transmit circuit <NUM> transmits the second packet <NUM> while the transmit circuit <NUM> is in no transmission period <NUM> (e.g., transmit circuit <NUM> is idle). The second packet <NUM> may include data that is being transmitted between the first and second ports <NUM> and <NUM>, respectively. The second packet <NUM> may comprise, for example, a sequence of pulses each representative of a state of a bit being transmitted. The size of the second packet <NUM> may vary based on the duration of the fourth period <NUM>. As the duration of the fourth period <NUM> increases, more bits may be transmitted in the second packet <NUM>. Conversely, the size of the second packet <NUM> may be reduced as the duration of the fourth period <NUM> is decreased.

Once the fourth period <NUM> has ended, the communication sequence <NUM> may repeat until the communication is complete. For example, the transmitters <NUM> and <NUM> may repeat the first transmit sequence <NUM> and the second transmit sequence <NUM>, respectively. The communication sequence <NUM> may be repeated any number of times depending on the amount of data to be transmitted over the isolation barrier.

Returning to <FIG>, it should be appreciated that the data isolator <NUM> may be implemented using any number of semiconductor dies integrated into any number of circuit packages. For example, the data isolator <NUM> may be implemented in a single semiconductor die that may be integrated into a circuit package. In another example, the components of the data isolator <NUM> may be distributed into a plurality of semiconductor dies that may be electrically connected. The plurality of dies may be integrated into a single circuit package or multiple circuit packages. In addition, other circuits configured to perform additional operations may be integrated into the data isolator <NUM> without departing from the scope of the present disclosure. For example, a power isolator may be integrated with the data isolator <NUM> to provide a combined power and data isolator. Such a combined power and data isolator may be integrated into a single circuit package or divided into multiple separate packages.

<FIG> shows an example transmit circuit <NUM> that may be employed as, for example, transmit circuits <NUM> and/or <NUM> in data isolator <NUM>. The transmit circuit <NUM> includes a controller <NUM> that generates pulse information <NUM> based on the information that is to be transmitted across the isolation barrier. The pulse information <NUM> may include the information regarding how a transmission should be performed, such as the number and/or polarity of the pulses in the transmission. The pulse information <NUM> may be received by a pulse generator <NUM> that employs the pulse information to generate output pulses that may be converted into analog signals by a front-end circuit <NUM> before being transmitted across the isolation barrier. The timing of the transmission of the pulses by the pulse generate <NUM> may be controlled by a transmit timing circuit <NUM>. For example, the transmit timing circuit <NUM> may identify the appropriate time for the pulse generator <NUM> to transmit pulses, monitor a number of pulses that have been transmitted, and/or determine the duration of the pulses.

The controller <NUM> may be configured to generate the pulse information <NUM> based on the information that is to be transmitted across the isolation barrier (e.g., information received from a device external to the data isolator). The controller <NUM> may generate a series of data packets that are to be transmitted across the isolation barrier based on the received information. The particular techniques employed by the controller <NUM> to packetize the data may vary based on the particular data to be transmitted and/or the particular packetization scheme employed by the data isolator. Once the data packets have been generated, the controller <NUM> may identify a sequence of pulses that correspond to the data packet and/or a clock signal that may accompany the data packet. For example, the controller <NUM> may identify the number of pulses to be transmitted in the sequence and the polarity of each pulse in the sequence. The identified number of pulses and the sequence of pulses may, in turn, be provided as pulse information <NUM> to the pulse generator <NUM>.

The transmit timing circuit <NUM> may be configured to generate timing information for the pulse generator <NUM>. The transmit timing circuit <NUM> may start when a transmit start signal <NUM> is a logic high. The transmit start signal <NUM> may be received from, for example, a receive circuit (e.g., receive circuit <NUM> in <FIG>) that is located on the same side of the isolation barrier. The logic high on the transmit start signal <NUM> triggers a D flip flop <NUM> to output a logic high at the output Q because the D-input to the D flip flop <NUM> also receives a logic high (e.g., is coupled to a supply voltage). In turn, the output of the D flip flop <NUM> is provided to an analog delay line <NUM> that provides an output that is a delayed version of the input. The analog delay line <NUM> may be implemented using analog components to advantageously provide a more precise delay than digital components. The output of the analog delay line <NUM> may be provided to an edge detector <NUM> that identifies rising and falling edges in the output of the analog delay line <NUM>. When the edge detector <NUM> detects a rising edge, a logic high is provided to the reset input of the D-flip flop <NUM> that triggers the output Q of the D-flip flop <NUM> to go to a logic low. Conversely, when the edge detector <NUM> detects a falling edge, a logic high is provided to the set input of the D-flip flop <NUM> that triggers the output Q of the D-flip flop <NUM> to return to a logic high. As a result, the D-flip flop <NUM> in combination with analog delay line <NUM> and edge detector <NUM> form a self-generated clock that has a frequency equal to the inverse of double the delay time of the analog delay line <NUM>. The rising and falling edges detected by the edge detector <NUM> are provided to an OR-gate <NUM>. In turn, the output of the OR-gate <NUM> is provided to the pulse generator <NUM> via a digital delay <NUM> to trigger the transmission of pulses. In addition, a pulse counter <NUM> counts the number of logic highs in the output of the OR-gate <NUM> that is indicative of the number of pulses output by the pulse generator <NUM>. Once the transmission is complete, the transmission start signal <NUM> becomes a logic low and triggers the pulse counter <NUM> to reset the pulse count and a generate a transmit done signal <NUM> that is a logic high. Additionally, the self-generated clock formed by the D-flip flop <NUM>, the analog delay line <NUM>, and the edge detector <NUM> may also be stopped.

The pulse generator <NUM> may be configured to output pulses to the front-end circuit <NUM> based on the pulse information <NUM> received from the controller and the timing information received from the transmit timing circuit <NUM>. For example, the timing information may include a trigger signal to send a pulse and a total number of pulses transmitted and the pulse information may include the total number of pulses to be transmitted and the polarity of each pulse. In this example, the pulse generator may transmit a pulse with a polarity as specified by the pulse information each time a trigger signal is received until the total number of pulses transmitted equals the total number of pulses to be transmitted. Once the total number of pulses transmitted equals the total number of pulses to be transmitted the pulse generator <NUM> may stop sending pulses.

The front-end circuit <NUM> may be configured to convert the pulses received from the pulse generator <NUM> into analog signals that may be transmitted across the isolation barrier. The front-end circuit <NUM> may include any of a variety of components including, for example, digital-to-analog converts (DACs), filters, and/or amplifiers.

<FIG> shows an example receive circuit <NUM> that may be employed as, for example, receive circuits <NUM> and/or <NUM> in data isolator <NUM>. The receive circuit <NUM> includes a front-end circuit <NUM> to digitize signals from the isolation barrier and output first and second received pulse signals <NUM> and <NUM>, respectively. A receive timing circuit <NUM> may monitor a receive state indicative of whether the receive circuit <NUM> should process the first and second pulse signals <NUM> and <NUM>, respectively. A pair of flip flops <NUM> and <NUM> may be coupled between the front-end circuit <NUM> and the data processing circuit <NUM>. The flip flops <NUM> and <NUM> may sample and maintain a state of the pulses output by the front-end circuit <NUM>. For example, the pulses output by the front-end circuit <NUM> may have a short duration and the flip flops <NUM> and <NUM> may provide output pulses to the data processing circuit <NUM> that have a longer duration than the short pulses output by the front-end circuit <NUM>. The data processing circuit <NUM> may analyze the received pulses to generate recovered data <NUM> that may be provided to a controller <NUM>. The controller <NUM> may, in turn, provide the recovered data <NUM> to a port of the data isolator.

The front-end circuit <NUM> may be configured to convert the analog signals received from the isolation barrier into digital signals shown as first and second pulse signals <NUM> and <NUM>, respectively. The first pulse signal <NUM> may be a logic high when a first signal is received across the isolation barrier (e.g., associated with a <NUM> being transmitted) and the second pulse signal <NUM> may be a logic high when a second, different signal is received across the isolation barrier (e.g., associated with a <NUM> being transmitted). The front-end circuit <NUM> may include any of a variety of components including, for example, analog-to-digital converters (ADCs), filters, and/or amplifiers.

The receive timing circuit <NUM> may be configured to monitor a receive state indicative of whether the receive circuit <NUM> is in a receive state where the received information from the front-end circuit <NUM> should be processed or a transmit state where the received information from the front-end circuit <NUM> should be ignored. In the receive timing circuit <NUM>, the state machine circuit <NUM> receives a transmit done signal <NUM> from a transmit circuit (e.g., transmit circuit <NUM>) on the same side of the isolation barrier indicating that the last transmission is complete. In turn, the state machine circuit <NUM> outputs a logic high signal at the receive state ports that trigger the data processing circuit <NUM> to process the logic states output by the flip flops <NUM> and <NUM>. Further, the transmit state port of the state machine circuit <NUM> outputs a logic low signal that, via inverter <NUM>, provides a logic high to a first port of AND gates <NUM> and <NUM>. The second input of each of the AND gates <NUM> and <NUM> receives the first pulse signal <NUM> and the second pulse signal <NUM>, respectively. Thus, the output of the AND gates <NUM> and <NUM> may track the first pulse signal <NUM> and the second pulse signal <NUM>, respectively. The output of the AND gates <NUM> and <NUM> is provided to an OR gate <NUM> that outputs an indication of whether a pulse has been received. The output of the OR gate <NUM> is provided to OR gate <NUM> that is, in turn, provided to an analog one-shot circuit <NUM>. The analog one-shot circuit <NUM> may be configured to monitor an amount of time that has passed since a pulse signal was last received. If the amount of time between received pulses exceeds a threshold, the analog one-shot circuit <NUM> times-out and provides a logic high signal. The analog one-shot circuit <NUM> may be implemented using analog components to advantageously provide a more precise time threshold before timing-out relative to employing digital components. The logic high signal output by the analog one-shot <NUM> may trigger the receive timing circuit <NUM> to transition from a receive state to a transmit state. As a result, the number of pulses that may be received and processed is arbitrary because the receive circuit <NUM> does not transition from a receive state to a transmit state until a threshold amount of time has passed since a pulse has been transmitted.

In some embodiments, the state machine circuit <NUM> may output an rxidle signal indicative of whether pulses are expected to be received or not expected to be received. The rxidle signal may be output to an edge detector <NUM> that detects edges in the rxidle signal and provides an output, indicative of whether an edge was detected, to the OR gate <NUM>. The state of the rxidle signal may be controlled so as to block spurious pulses from being detected to increase the robustness of the receive circuit <NUM>. For example, the rxidle signal may be triggered to mask the output of the OR gate <NUM> when no received signals are expected so as to stop spurious pulses from being processed by the receive circuit <NUM>.

The timing circuit <NUM> may monitor the output of the analog one-shot using an edge detector <NUM> that outputs a logic high in response to detecting a rising edge in the signal output by the analog one-shot <NUM>. The logic high output by the edge detector <NUM> triggers a flip-flop <NUM> to transition from providing a logic low at the output Q to providing a logic high. The logic high output by the flip-flop <NUM> is provided to the state machine circuit <NUM> that may trigger the state machine circuit <NUM> to output a logic high at the transmit state port to stop the first and second pulse signals <NUM> and <NUM> from being propagated to the analog one-shot <NUM>. Further, the state machine circuit <NUM> may output a logic low at the receive state port to stop the data processing circuit <NUM> from processing the outputs of the flip-flops <NUM> and <NUM>. The output (Q) of the flip-flop <NUM> may also be provided to a digital delay <NUM> before being provided to an AND gate <NUM>. The output of the AND gate <NUM> may be the transmit start signal <NUM> that may be provided to the transmitter (e.g., the transmitter <NUM> shown in <FIG>) on the same side of the isolation barrier. Thus, the digital delay <NUM> may add a time delay between when the transmission over the isolation barrier in a first direction is complete and when the transmission over the isolation barrier in a second, opposite direction starts.

In some embodiments, the state machine circuit <NUM> may comprise a clock recovery circuit <NUM> that is configured to recover the clock signal from the first and second pulse signals <NUM> and <NUM>, respectively. In these embodiments, the state machine circuit <NUM> may be coupled to the output of one or more of the flip-flops <NUM> and/or <NUM> and monitor the outputs of the flip-flops <NUM> and/or <NUM> to locate the transmitted clock markers that denote transitions in the clock signal. The recovered clock signal may be output to the controller <NUM> that may be, for example, output by the data isolator to an external electronic device to facilitate control of one or more components within the external electronic device.

The data processing circuit <NUM> may be configured to recover the transmitted data packet (e.g., recover the total number of bits in the data packet and the value of each bit) based on the output of the flip-flops <NUM> and <NUM> when the receive circuit <NUM> is in a receive state (as opposed to a transmit state). For example, the data processing circuit <NUM> may monitor the output of the flip-flops <NUM> and <NUM> to determine the state of a given bit in the data packet. In this example, data processing circuit <NUM> may identify a sequence of low-to-high-to-low transitions in the output of the flip flop <NUM> as a <NUM> in the data packet and identify a sequence of low-to-high-to-low transitions in the output of the flip flop <NUM> as a <NUM> in the data packet. The data processing circuit <NUM> may provide the recovered data packet to a controller <NUM> that may, in turn, provide the recovered data packet to an output of the data isolator (e.g., alone or in combination with other information such as additional recovered data packets).

The controller <NUM> may provide information to an output of the data isolator based on the recovered data <NUM> and/or the recovered clock signal. For example, the controller <NUM> may stich together data from multiple data packets into a single piece of data before providing the data to the output. The particular way in which information from multiple data packets is combined may depend on the particular packetization scheme employed by the data isolator. Additionally, the controller <NUM> may output the recovered clock signal to a port of the data isolator such that the clock signal may be employed by an external device (e.g., to control one or more components within the external device).

As discussed above, a data isolator is disclosed herein that may be configured to enable bi-directional communication in a dynamic fashion. These data isolators may perform various processes to, for example, enable the bi-directional communication. An example of such a process to operate the data isolator to enable bi-directional communication is shown in <FIG> by process <NUM>. The process <NUM> includes an act <NUM> of identifying a clock frequency, act <NUM> of generating a clock signal, an act <NUM> of transmitting the clock signal, an act <NUM> of transmitting first data in a first direction across an isolation barrier, an act <NUM> of receiving the first data and the clock signal, an act <NUM> of transmitting second data in a second direction across the isolation barrier, and an act <NUM> of determining whether communication is complete.

In act <NUM>, the data isolator may identify a clock frequency to employ for the data transmission (or any portion thereof). The clock frequency may be variable within a range of frequencies to change a number of bits that are transmitted while the clock signal is in a given state. For example, the clock frequency may be reduced to enable a greater number of bits to be transmitted while the clock signal is in a given state. Conversely, the clock frequency may be increased to reduce the number of bits that may be transmitted while the clock signal is in a given state. Accordingly, the data isolator may increase the clock frequency to transmit data packets that are smaller in size (e.g., sensor values) at a low latency or reduce the clock frequency to transmit larger data packets (e.g., error messages). As a result, the data isolator may select the clock frequency based on the data being transmitted.

In act <NUM>, the data isolator may generate a clock signal at the identified clock frequency. The clock signal may be employed by the data isolator to coordinate operation of multiple components (e.g., transmitter circuits and/or receiver circuits). For example, the data isolator may transmit data in a first direction across the isolation barrier while the clock signal is in a first state and transmit data in a second, opposite direction across the isolation barrier when the clock signal is in a second state.

In act <NUM>, the data isolator may transmit the clock signal in a first direction across the isolation barrier. The data isolator may transmit the clock signal by transmitting clock markers that indicate when transitions occur in the clock signal. The clock markers may be, for example, a unique sequence of pulses representative of either a rising edge in the clock signal or a falling edge in the clock signal.

In act <NUM>, the data isolator may transmit first data in the first direction across the isolation barrier. The first data may, for example, originate from a device coupled the data isolator. The data isolator may transmit the first data in response to the clock signal being in a particular state. For example, the clock signal may oscillate between two states and the data isolator may transmit the first data response to the clock signal being in the first state. Otherwise, the data isolator may wait to transmit the first data until the state of the clock signal changes. The data isolator may transmit the first data as a sequence of pulses. Each of the pulses may be, for example, representative of a state of at least one bit in the first data. It should be appreciated that other signal shapes separate and apart from pulses may be employed to transmit the data.

In act <NUM>, the data isolator may receive the clock signal and the first data. The data isolator may receive the clock signal by, for example, identifying the clock markers transmitted across the isolation barrier and recovering the clock signal based on the identified clock markers. Similarly, the data isolator may receive the first data by, for example, identifying the pulses transmitted over the isolator barrier and reconstructing the first data based on the identified pulses.

In act <NUM>, the data isolator may transmit second data in a second direction across isolation barrier that is opposite the first direction. The second data may, for example, originate from a device coupled the data isolator. The data isolator may transmit the second data in response to the clock signal being in a particular state. For example, the clock signal may oscillate between two states and the data isolator may transmit the first data response to the clock signal being in a second state. Otherwise, the data isolator may wait to transmit the second data until the state of the clock signal changes. The data isolator may transmit the second data as a sequence of pulses. Each of the pulses may be, for example, representative of a state of at least one bit in the second data. It should be appreciated that other signal shapes separate and apart from pulses may be employed to transmit the data.

In act <NUM>, the data isolator may determine whether the communication is complete. The data isolator may determine that communication is complete when there is no more data to transfer across the isolation barrier (e.g., in either direction). If the data isolator determines that communication is not complete, the data isolator may return to act <NUM> to identify a new clock frequency for the next transmission. Otherwise, process <NUM> may end.

<FIG> is a block diagram illustrating an example of a system <NUM> comprising the data isolator <NUM> described above. As shown, the system <NUM> includes a first device <NUM> coupled the first port <NUM> of the data isolator <NUM> and a second device <NUM> coupled to the second port <NUM> of the data isolator <NUM>. The data isolator <NUM> may provide, for example, data isolation between the first device <NUM> and the second device <NUM>. The first device <NUM> and the second device <NUM> may be in the same voltage domain or different voltage domains.

The first device <NUM> may be configured to provide data to (and/or receive data from) the first port <NUM>. The first device <NUM> may be configured to output (and/or receive) the data at a first voltage level. The voltage output (and/or received) by the first device <NUM> is shown as a data voltage D1+ and reference potential D1- and the first voltage level may be the potential difference between D1+ and D1-.

The second device <NUM> may be configured to receive data from (and/or provide data to) the second port <NUM>. The second device <NUM> may be configured to receive (and/or output) the data at a second voltage level. The voltage received (and/or output) by the first device <NUM> is shown as a data voltage D2+ and reference potential D2- and the second voltage level may be the potential difference between D2+ and D2-.

In some embodiments, the first device <NUM> may be in a different voltage domain than the second device <NUM>. In these embodiments, the second voltage level may be different from the first voltage level (e.g., smaller or larger than the first voltage level). For example, the potential difference between D2+ and D2- may not be the same as the difference between D1+ and D1-. Additionally (or alternatively), the first voltage level may be offset relative to the second voltage level. For example, the potential at D1- may not match the potential at D2- (irrespective of whether the potential difference between D1+ and D1- matches the potential difference between D2+ and D2-). The data isolator <NUM> may be configured to support a substantial offset between the first and second voltage levels including, for example, a potential difference between D1- and D2- of at least <NUM> Volts, <NUM> Volts, <NUM> Volts, and/or <NUM> Volts.

In some embodiments, the first device <NUM> may be in the same voltage domain as the second device <NUM>. In these embodiments, the first voltage level may be the same as the second voltage level. For example, the potential difference between D2+ and D2- may be the same as the difference between D1+ and D1-. Additionally, there may be no offset between the first and second voltage levels. For example, the potential at D1- may match the potential at D2-.

Having described bi-directional isolators with dynamic data transmission, it should be appreciated that the information transmitted across the isolation barrier may be arranged in any of a variety of packet structures. In some embodiments, the communication scheme uses an asymmetric packet structure where the structure of the data packet being transmitted in a first direction across the isolation barrier is different from the structure of the data packet being transmitted in a second, opposite direction across the isolation barrier. An example of such an asymmetric packet structure that may be employed to transmit data across the isolation barrier is shown below in Tables <NUM> and <NUM>. Table <NUM> shows the data fields for the bits in each data pack in the sequence of <NUM> data packets transmitted in a first direction across the isolation barrier. Similarly, Table <NUM> shows the data fields for the bits in each data packet in the sequence of <NUM> data packets transmitted in a second direction across the isolation barrier. One data packet from each of Tables <NUM> and <NUM> may be transmitted per clock cycle. For example, data packet <NUM> from Table <NUM> may be transmitted in the first direction over the isolation barrier during the first half of a clock cycle and data packet <NUM> from Table <NUM> may be transmitted in the second direction over the isolation barrier. As a result, the sequence of <NUM> data packets in each of Tables <NUM> and <NUM> may be transmitted over <NUM> clock cycles.

As shown in Table <NUM>, each of the <NUM> data packets includes two bits. The data bits being transmitted across the isolation barrier in a first direction are shown as db[<NUM>]-db[<NUM>] in Table <NUM>. The data bits may, for example, include information to control a digital-to-analog converter (DAC) on a second side of the isolation barrier (e.g., a DAC integrated into the second circuit <NUM>). Additionally, the data packet structure shown in Table <NUM> may include one or more spare bits (shown as sp[<NUM>] and sp[<NUM>]). The spare bits may have predetermined states that may be employed as a synchronization sequence by the receiver. Alternatively, the one or more spare bits may be removed altogether and replaced with additional data bits. Error detection and/or error correction codes may also be integrated into the data packets to improve noise immunity. The error detection and/or correction codes may be, for example, cyclic redundancy check (CRC) codes (shown as crc[<NUM>] through crc[<NUM>] in Table <NUM>) and/or error correction codes (ECC) codes.

As shown in Table <NUM>, each of the <NUM> data packets includes five bits. The data bits being transmitted across the isolation barrier in a second direction are shown as db[<NUM>]-db[<NUM>] in Table <NUM>. The data bits may, for example, include information to control an analog-to-digital converter (ADC) on a first side of the isolation barrier (e.g., an ADC integrated into the first circuit <NUM>). Information regarding the state of the circuitry on the first side of the isolation barrier may be transmitted across the isolation barrier in the second direction as status bits stat[<NUM>]-stat[<NUM>]. Additionally, the data packet structure shown in Table <NUM> may include one or more spare bits (shown as sp[<NUM>] and sp[<NUM>]). The spare bits may have predetermined states that may be employed as a synchronization sequence by the receiver. Alternatively, the one or more spare bits may be removed altogether and replaced with additional data bits. Error detection and/or error correction codes may also be integrated into the data packets to improve noise immunity. The error detection and/or correction codes may be, for example, cyclic redundancy check (CRC) codes (shown as crc[<NUM>] through crc[<NUM>]) and/or error correction codes (ECC) codes (shown as ecc[<NUM>]-ecc[<NUM>]).

In some embodiments, the data isolator may be paired with a power isolator that is configured to transmit power across an isolation barrier. In these embodiments, the data packets may include additional bits to control operation of the power isolator. In Table <NUM>, the bits to control operation of the power isolator are shown as pwr[<NUM>]-pwr[<NUM>].

It should be appreciated that additional bits may be added to the data packets shown in Tables <NUM> and <NUM> to incorporate additional functionality. An example of such an asymmetric packet structure with additional functionality relative to the structure of Tables <NUM> and <NUM> is shown below in Tables <NUM> and <NUM>. The particular packet structure shown in Tables <NUM> and <NUM> may be employed to transmit write commands over the isolation barrier. Table <NUM> shows the data fields for the bits in each data pack in the sequence of <NUM> data packets transmitted in a first direction across the isolation barrier. Similarly, Table <NUM> shows the data fields for the bits in each data packet in the sequence of <NUM> data packets transmitted in a second direction across the isolation barrier. One data packet from each of Tables <NUM> and <NUM> may be transmitted per clock cycle. As a result, the sequence of <NUM> data packets in each of Tables <NUM> and <NUM> may be transmitted over <NUM> clock cycles.

As shown in Table <NUM>, each of the <NUM> data packets includes between seven and eight bits. The first two bits of each packet (shown as txbit0 and txbit1) may be, for example, bits from the data packets shown in Table <NUM> above. The packet structure in Table <NUM> adds a series of command bits shown as cm[<NUM>] - cm[<NUM>] that issue a write command to the receiver. The target addresses for the write commands are shown as add[<NUM>] - add[<NUM>]. The data to be written may be included in dt[<NUM>] - dt[<NUM>]. Parity bits are also integrated into the data packets to enable the receiver to check the integrity of the data packets. The parity bit associated with the command bits is shown as cmpty, the parity bit associated with the address bits is shown as addpty, and the parity bits associated with the data to be written is shown as dtpty.

As shown in Table <NUM>, each of the <NUM> data packets includes six bits. The first five bits of each packet (shown as txbit0 - txbit4) may be, for example, bits from the data packets shown in Table <NUM> above. The packet structure in Table <NUM> adds a series of parity bits. In particular, the parity bits cmpty, addpty, and dtpty shown in Table <NUM> that were transmitted in a first direction across the isolation barrier, may be transmitted back across the isolation barrier in a second direction if a self-generated parity bit matches the received parity bit (e.g., because the transmission was not corrupted). If the self-generated parity bit does not match the received parity bit (e.g., because the transmission contained an error), the transmission may be stopped.

Another example of such an asymmetric packet structure with additional functionality relative to the structure of Tables <NUM> and <NUM> is shown below in Tables <NUM> and <NUM>. The particular packet structure shown in Tables <NUM> and <NUM> may be employed to transmit read commands over the isolation barrier. Table <NUM> shows the data fields for the bits in each data pack in the sequence of <NUM> data packets transmitted in a first direction across the isolation barrier. Similarly, Table <NUM> shows the data fields for the bits in each data packet in the sequence of <NUM> data packets transmitted in a second direction across the isolation barrier. One data packet from each of Tables <NUM> and <NUM> may be transmitted per clock cycle. As a result, the sequence of <NUM> data packets in each of Tables <NUM> and <NUM> may be transmitted over <NUM> clock cycles.

As shown in Table <NUM>, each of the <NUM> data packets include between two and eight bits. The first two bits of each packet (shown as txbit0 and txbit1) may be, for example, bits from the data packets shown in Table <NUM> above. The packet structure in Table <NUM> adds a series of command bits shown as cm[<NUM>] - cm[<NUM>] that issue a command to the receiver (e.g., to read data). The target addresses for the commands are shown as add[<NUM>] - add[<NUM>]. Parity bits are also integrated into the data packets to enable the receiver to check the data packets. The parity bit associated with the command bits is shown as cmpty and the parity bit associated with the address bits is shown as addpty.

As shown in Table <NUM>, each of the <NUM> data packets includes between six and eight bits. The first five bits of each packet (shown as txbit0 - txbit4) may be, for example, bits from the data packets shown in Table <NUM> above. The packet structure in Table <NUM> adds a series of data fields dt[<NUM>] - dt[<NUM>] that include the data that is located at the addresses specified in Table <NUM>. Parity bits are also integrated into the data packets to enable the receiver to check the data packets. The parity bit associated with the command bits is shown as cmpty, the parity bit associated with the address bits is shown as addpty, and the parity bits associated with the data to be written is shown as dtpty.

Having described various techniques for dynamic communication across an isolation barrier in bi-directional isolators, it should be appreciated that the techniques described herein may also be applied to unidirectional data isolators. For example, the receive circuit <NUM> and the transmit circuit <NUM> may be removed from the data isolator <NUM>. Similarly, the receive circuit <NUM> and the transmit circuit <NUM> may be removed from the data isolator <NUM>. As a result, the techniques described herein are not limited to bi-directional data isolators.

Claim 1:
A bi-directional data isolator (<NUM>), comprising:
an isolation barrier (<NUM>);
a first circuit (<NUM>) configured to transmit first data and a clock signal across the isolation barrier (<NUM>), the clock signal being configured to periodically vary between a plurality of states at a clock frequency; and
a second circuit (<NUM>) configured to receive the first data and the clock signal and transmit second data across the isolation barrier (<NUM>);
wherein the first circuit (<NUM>) is configured to transmit the first data at a data rate that is variable relative to the clock frequency within a range including a first ratio of the data rate to the clock frequency and a second ratio of the data rate to the clock frequency, wherein the first circuit (<NUM>) is configured to transmit the first data across the isolation barrier (<NUM>) while the clock signal is in a first state of the plurality of states and the second circuit (<NUM>) is configured to transmit the second data across the isolation barrier (<NUM>) while the clock signal is in a second state of the plurality of states and wherein the first circuit (<NUM>) is configured to change the data rate relative to the clock frequency within the range at least in part by changing the clock frequency by adjusting a duration of the first state to adjust a size of the first data.