Patent Description:
Embodiments of the invention relate to dynamic voltage scaling software and hardware in a computing system.

Modern processors use dynamic techniques, such as dynamic voltage and frequency scaling (DVFS), to balance performance and power consumption to meet workload demands. When a processor is under a heavy workload, the operating voltage and frequency can be increased to achieve a higher performance. Conversely, when the workload is light, the operating voltage and frequency can be decreased to save power and reduce heat generation. When the operating frequency increases, a processor requires a higher operating voltage to perform its operations and maintain the stability. However, increasing the operating voltage can cause a significant increase in power consumption and heat generation, which not only can adversely degrade the system performance but can also damage the processor hardware.

<CIT> discloses an apparatus and a method that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume. <CIT> discloses an all-digital closed-loop fine-grained control of voltage and frequency for running conditions of a compute machine such as graphic processor unit (GPU), central processing unit (CPU), or any other processing unit. The scheme optimizes the voltage margin and frequency on the fly according to desired programmable performance metrics. A mitigation response to droops is naturally built into the system and is equal to the cause rather than being excessive. The scheme is scalable and can be instantiated in different clusters for best results.

Manufacturers often design processors to operate within specific voltage and frequency ranges to maintain a balance between performance, power consumption, and reliability. The relationship between an operating frequency and its corresponding voltage can be described by a voltage-frequency curve used by the DVFS. Manufacturers typically build in a large voltage margin in the curve to ensure proper operations of the processors at the expense of energy efficiency. Additionally, physical parameters and characteristics of processor chips can vary widely due to variations in the fabrication process, and can change over time due to aging and changes in operating conditions (e.g., temperature, current, etc.). Conventional DVFS techniques do not sufficiently address these changes. Thus, there is a need for improving the voltage scaling techniques in a processor system.

A method and a system according to the invention are defined in the independent claims. The dependent claims define preferred embodiments thereof.

Other aspects and features will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures.

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to "an" or "one" embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

In the following description, numerous specific details are set forth. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure the understanding of this description. It will be appreciated, however, by one skilled in the art, that the invention may be practiced without such specific details. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

This disclosure describes an adaptive voltage and code scaling (DVCS) mechanism that enables a computing system to maintain a required computing power and achieve optimal energy efficiency. The DVCS mechanism tracks the computing power required by a computing system in real time and optimizes the power output in real time. The DVCS mechanism can respond to a wide range of physical transients that occur inside a processor chip.

The computing power required by a computing system depends on system workload, and can be distorted by changes in physical parameters and characteristics of the chip on which the system resides. These changes often have no feedback mechanism to the system. According to embodiments of the invention, a frequency-locked loop (FLL) controller monitors changes in physical parameters and/or operating conditions and immediately feeds back to a DVCS controller to perform voltage correction. The FLL feedback and the DVCS operations enable a computing system to save power and achieve an optimal power output.

In one embodiment, a computing system may utilize both DVFS and DVCS for adaptive voltage control. The computing system may include both a DVFS controller and a DVCS controller. The DVFS controller determines whether to change the operating frequency and the corresponding operating voltage to satisfy the system performance under a given workload. The DVCS controller determines whether to apply fine adjustments to the operating voltage for a given target frequency.

<FIG> is a block diagram illustrating an adaptive voltage scaling system <NUM> according to one embodiment. In this embodiment, system <NUM> includes an FLL <NUM>, a DVCS controller <NUM>, a power management unit (PMU) <NUM> (e.g., a power management integrated circuit (PMIC)), and a first memory that stores a minimum code table <NUM>, and a second memory that stores a DVFS table <NUM>. System <NUM> further includes a phase locked loop (PLL) <NUM> coupled to FLL <NUM>. PLL <NUM> provides a target frequency (Ftarget) to FLL <NUM>. FLL <NUM> includes an oscillator <NUM>, such as a ring oscillator, which generates a clock signal at a clock frequency (Fclk). FLL <NUM> further includes an FLL controller <NUM>, which outputs a code to oscillator <NUM> to control the clock frequency of oscillator <NUM>. The code can be dynamically adjusted such that the clock frequency can closely track or match the target frequency. FLL controller <NUM> also generates a voltage adjustment hint indicating whether to increase, decrease, or maintain the present operating voltage to satisfy the system workload requirement at the target frequency. The voltage adjustment hint may be generated periodically (e.g., every one millisecond) to provide real time feedback on the voltage required to match the target frequency.

Preferably, the clock signal is provided to a processor such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU), a digital processing unit (DSP), an AI processor, other general-purpose and/or special-purpose processing circuitry. The operating voltage is also provided to the processor that receives the clock signal. Preferably, system <NUM> and the processor receiving the clock signal may be part of a system-on-a-chip (SoC).

Preferably, DVCS controller <NUM> receives the voltage adjustment hint from FLL <NUM> and generates a voltage adjustment signal to indicate an adjustment to the present operating voltage. The adjustment may be to increase the present operating voltage by a step size (u) or to decrease the present operating voltage by the step size (u). DVCS controller <NUM> sends the voltage adjustment signal to PMU <NUM>, and PMU <NUM> in response adjusts the operating voltage of FLL <NUM> accordingly.

Furthermore, based on the voltage adjustment hint from FLL <NUM>, DVCS controller <NUM> determines an adjusted operating voltage (adjusted Vop) and identifies a Mincode set from minimum code table <NUM>. When the adjusted operating voltage is not provided in minimum code table <NUM>, the MinCode set (also referred to as a minimum code set) may be obtained by interpolating the given code values in minimum code table <NUM>, where the given code values correspond to the adjusted Vop and the operating temperature sensed by a temperature sensor <NUM>. DVCS controller <NUM> sends the MinCode set to FLL <NUM>, such that FLL controller <NUM> can determine a code to configure oscillator <NUM> in real time. With the adjusted operating voltage and the code, oscillator <NUM> is configured to generate a clock signal that locks the target frequency (i.e., frequency and phase aligned to the target frequency). If the clock signal cannot lock the target frequency due to low operating voltage, FLL controller <NUM> can generate a hint to DVCS controller <NUM> to request a voltage increase. DVCS controller <NUM> in response requests PMU <NUM> for a voltage increase and updates the MinCode set corresponding to the increased voltage for FLL <NUM>. Preferably, the update to the MinCode set can occur at a predetermined time interval; e.g., every one millisecond.

Additionally, when the operating voltage is adjusted, DVCS controller <NUM> can further update DFVS table <NUM> to indicate that the adjusted operating voltage corresponds to the present clock frequency. This update provides a real time view into the relationship between the clock frequency and the required voltage. DVFS table <NUM> may be used by a DVFS controller <NUM> to look up a corresponding voltage when there is a need to change the target frequency (e.g., for system performance). Preferably, the update to DFVS table <NUM> can occur at a predetermined time interval; e.g., every one millisecond.

<FIG> is a block diagram illustrating an example of an FLL (e.g., FLL <NUM> in <FIG>) according to one embodiment. In this embodiment, FLL <NUM> includes oscillator <NUM> coupled to FLL controller <NUM>. FLL <NUM> is coupled to PMU <NUM>, which supplies an operating voltage to FLL <NUM>. FLL <NUM> is further coupled to PLL <NUM>, which provides a target frequency to FLL <NUM>. FLL controller <NUM> provides a code C to oscillator <NUM>, where code C is a set of parameters that can be used to configure oscillator <NUM> to generate a clock signal at a clock frequency (Fclk). FLL controller <NUM> may select or determine the value of code C and/or may request an adjustment to the operating voltage such that the clock frequency (Fclk) can match the target frequency (Ftarget). Preferably, FLL controller <NUM> includes a clock sensing circuit <NUM>, a frequency comparator <NUM>, a voltage adjustment hint generator <NUM>, and a code selector <NUM>. FLL controller <NUM> further includes a memory to store a set of MinCodes <NUM>.

Preferably, clock sensing circuit <NUM> senses a time window for frequency comparison, and frequency comparator <NUM> compares the clock frequency (Fclk) with the target frequency (Ftarget). Depending on the difference between Fclk and Ftarget, FLL controller <NUM> may determine to request an adjustment to the operating voltage, and send the request for voltage adjustment to DVCS controller <NUM>. Alternatively, FLL controller <NUM> may select a different code C from the set of MinCodes <NUM>.

<FIG> illustrates an example of a minimum code table <NUM> used by DVCS controller <NUM> (<FIG>) according to one embodiment. Minimum code table <NUM> is an example of minimum code table <NUM> in <FIG>. The values in minimum code table <NUM> may be determined during the chip testing stage. DVCS controller <NUM> may use minimum code table <NUM> to determine a MinCode set corresponding to the current operating voltage, and provide the MinCode set to FLL <NUM>. After DVCS controller <NUM> provides the MinCode set to FLL <NUM>, code selector <NUM> in FLL <NUM> can select a code C = (CC, FC) to set the operating parameters of oscillator <NUM> to thereby adjust the clock frequency of oscillator <NUM>.

Preferably, a MinCode includes a pair of a coarse code (CC) and a fine code (FC). Each MinCode set for a given voltage includes multiple FCs for the corresponding CCs. For example, according to table <NUM>, the MinCode set for <NUM> mV includes (CC, FC) = (<NUM>, <NUM>), (<NUM>, <NUM>), (<NUM>, <NUM>), (<NUM>, <NUM>). Alternatively, the MinCode set for <NUM> mV may be represented by fine codes only; e.g., (<NUM>, <NUM>, <NUM>, <NUM>), where each fine code corresponds to a respective coarse code. This MinCode set corresponds to a frequency range at <NUM> mV; a processor cannot safely operate at a clock frequency higher than this frequency range at <NUM> mV. The four coarse codes, which have fixed values of <NUM>, <NUM>, <NUM>, <NUM>, correspond to four frequency segments in the frequency range. The smaller the coarse code, the higher the frequency. The fine code can be used to fine tune the clock frequency in each frequency segment. FLL controller <NUM> may select a code that corresponds to the target frequency.

When a given operating voltage is not provided in minimum code table <NUM>, DVCS controller <NUM> may interpolate the fine codes between two adjacent voltages in minimum code table <NUM>. For example, if the operating voltage is <NUM> mV, DVCS controller <NUM> may interpolate the fine codes at <NUM> mV and <NUM> mV to obtain the fine codes at <NUM> mV. These fine codes and the corresponding coarse codes form the MinCode set at <NUM> mV.

Preferably, when the operating temperature is outside a predetermined temperature range, a code margin can be added to each fine code. The code margin may be determined during the chip testing process. The code margin can be adjusted according to the operating temperature measured by temperature sensor <NUM> (<FIG>) and the operating voltage. The code margin provides temperature compensation to each fine code.

In an alternative embodiment, a minimum code table may be a three-dimensional table including a coarse code dimension, a voltage dimension, and a temperature dimension. The code values provided in the table are the fine codes. Thus, a fine code can be determined with a given coarse code, an operating voltage, and an operating temperature.

<FIG> is a diagram illustrating a DVCS process <NUM> according to one embodiment. Process <NUM> starts with step <NUM> when a bootloader at system boot time initializes hardware and loads system data and software from on-chip memory, such as an eFuse. The loaded data contains voltage and code data to be used for adaptive voltage scaling. Alternatively, the voltage and code data may be read from embedded software stored in a location different from the eFuse.

Referring also to <FIG>, at step <NUM>, a parser parses the loaded data to format the data for DVCS controller <NUM> to read and populate a minimum code table, such as MinCode table <NUM> and/or MinCode table <NUM> in <FIG>. At step <NUM>, DVCS controller <NUM> obtains (e.g., by interpolation) fine codes for the present operating voltage. At step <NUM>, DVCS controller <NUM> receives a voltage adjustment hint from FLL <NUM>. The voltage adjustment hint may indicate whether to increase, decrease, or maintain the present operating voltage. At step <NUM>, DVCS controller <NUM> generates a voltage adjustment signal according to the voltage adjustment hint. Preferably, the voltage adjustment may be a voltage increase by a step size u (where u is a positive real number), a voltage decrease by u, or an unchanged voltage. The voltage adjustment applied to the present operating voltage is the adjusted operating voltage (adjusted Vop).

Concurrent with the voltage adjustment determination, DVCS controller <NUM> further determines a MinCode adjustment for FLL <NUM>. The MinCode adjustment may be based on the adjusted Vop and a temperature measurement that DVCS controller <NUM> receives from a temperature sensor at step <NUM>. At step <NUM>, DVCS controller <NUM> calculates or determines a code margin based on the temperature measurement. At step <NUM>, DVCS controller <NUM> determines an updated MinCode set based on the adjusted Vop and the temperature measurement. DVCS controller <NUM> may interpolate the data in the MinCode table in the voltage dimension and/or the temperature dimension to obtain the updated MinCode set corresponding to the adjusted operating voltage.

At step <NUM>, DVCS controller <NUM> sends a voltage adjustment signal to PMU <NUM>. Upon receiving the voltage adjustment signal, PMU <NUM> supplies the adjusted Vop to FLL <NUM>. DVCS controller <NUM> at step <NUM> updates a DVFS table to indicate that the adjusted operating voltage corresponds to the clock frequency. DVCS controller <NUM> at step <NUM> sends the updated MinCode set to FLL <NUM>. FLL controller <NUM> may select a code C = (CC, FC) from the updated MinCode set to fine tune the clock frequency of oscillator <NUM>. FLL controller <NUM> at step <NUM> logs the last DVCS information, such as the adjusted Vop, the clock frequency, and the updated MinCode set.

Preferably, DVCS operations <NUM> including steps <NUM>-<NUM> may repeat every N millisecond; e.g., every one millisecond. Thus, the operating voltage and the operating frequency can closely track any changes in the physical characteristics of the hardware and system workload.

Referring to <FIG>, in some scenarios, DVFS controller <NUM> may determine to change the operating frequency to satisfy system performance requirements. DVFS controller <NUM> may use DVFS table <NUM> to determine an operating voltage corresponding to the changed operating frequency. DVFS controller <NUM> then sets PLL <NUM> to the changed operating frequency and requests PMU <NUM> to supply the corresponding operating voltage to the hardware including FLL <NUM> and the processor receiving the clock signal.

<FIG> is an example of a DVFS table according to one embodiment. In this example, the voltage-frequency data in the DVFS table is represented by a DVFS curve <NUM>. <FIG> also shows a full-yield curve <NUM> for comparison purposes. Each voltage point on full-yield curve <NUM> is padded with margins that incorporate the effects of all of the factors that demand power. Furthermore, full-yield curve <NUM> is not dynamically updated. Thus, for any given frequency, full-yield curve <NUM> requires an operating voltage that is much higher than the voltage needed to sustain a normal system workload in a normal operating condition. A conventional DVFS controller may use full-yield curve <NUM> in determining voltage scaling. By contrast, for each given frequency, DVFS curve <NUM> indicates a lower voltage value than full-yield curve <NUM>, and, therefore, voltage scaling according to DVFS curve <NUM> can achieve power saving. DVCS operations, as described with reference to <FIG> and <FIG>, suppress the voltage required by full-yield curve <NUM> to achieve power saving. The voltage points on DVFS curve <NUM> are dynamically updated in response to the voltage adjustment signal from DVCS controller <NUM>. The vertical line segment on each voltage point of DVFS curve indicates a dynamic voltage range for a corresponding frequency.

<FIG> is a flow diagram illustrating a method <NUM> for adaptive voltage scaling according to one embodiment. Preferably, method <NUM> may be performed by a circuit implementing DVCS controller <NUM> in <FIG>. Preferably, the circuit may execute software to perform the operations of DVCS controller <NUM>.

Method <NUM> starts with step <NUM> in which a DVCS controller generates a voltage adjustment signal based on a hint from a FLL (e.g., FLL <NUM> in <FIG>). The FLL includes an oscillator that generates a clock signal at a clock frequency. At step <NUM>, the DVCS controller sends the voltage adjustment signal to a PMU to cause the PMU to supply an adjusted operating voltage to the FLL. At step <NUM>, the DVCS controller updates a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.

Preferably, the voltage adjustment signal indicates an increase by a step size or a decrease by the step size in a present operating voltage of the FLL. The voltage adjustment signal may be generated at a predetermined time interval for the PMU to periodically adjust voltage supplied to the FLL.

Preferably, method <NUM> further includes the step of updating a dynamic voltage-frequency table to indicate that the adjusted operating voltage corresponds to the clock frequency. The dynamic voltage-frequency table may be updated at a predetermined time interval during operation of the FLL.

Preferably, the minimum code set is updated at a predetermined time interval during operation of the FLL. Preferably, updating the minimum code set further comprises identifying, from a minimum code table, first fine codes at a first voltage level above the adjusted operating voltage and second fine codes at a second voltage level below the adjusted operating voltage, and obtaining fine codes in the minimum code set at the adjusted operating voltage by interpolating between the first fine codes and the second fine codes.

Preferably, the minimum code set includes multiple fine codes and corresponding coarse codes. Method <NUM> further includes the step of determining a fine code in the minimum code set based on the adjusted operating voltage, an operating temperature, and a corresponding coarse code.

Preferably, the minimum code set includes multiple fine codes. Method <NUM> further includes the step of calculating a code margin based on an operating temperature, and adding the code margin to the fine codes that correspond to the adjusted operating voltage. The code provided to the oscillator may be dynamically adjusted to control the clock frequency at the adjusted operating voltage.

The operations of the flow diagrams of <FIG> and <FIG> have been described with reference to the exemplary embodiment of <FIG>. However, it should be understood that the operations of the flow diagrams of <FIG> and <FIG> can be performed by embodiments of the invention other than the embodiment of <FIG>, and the embodiment of <FIG> can perform operations different than those discussed with reference to the flow diagrams. While the flow diagrams of <FIG> and <FIG> show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.).

Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, the functional blocks will preferably be implemented through circuits (either dedicated circuits or general-purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein.

Claim 1:
A method for adaptive voltage scaling, comprising:
generating (<NUM>) a voltage adjustment signal based on a hint from a frequency-locked loop, FLL, wherein the FLL includes an oscillator that generates a clock signal at a clock frequency (<NUM>);
sending (<NUM>) the voltage adjustment signal to a power management unit, PMU, to cause the PMU to supply an adjusted operating voltage to the FLL (<NUM>);
calculating (<NUM>) a code margin based on an operating temperature;
determining (<NUM>) a minimum code set according to the adjusted operating voltage and the operating temperature; and
updating (<NUM>) a dynamic voltage-frequency table to indicate that the adjusted operating voltage corresponds to the clock frequency,
wherein the clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set (<NUM>).