Patent Description:
As is known in the art, Field Effect Transistors (FETs) having a linear array of a plurality of FET cells are used in many applications. Each one of the FET cells has a source, a drain and a gate between the source and the drain to control a flow of carriers along a channel between the source and drain. It should also be understood the source and drain may be reversed in any electrical circuit application; with, in either circuit application, the gate controlling the flow of carriers between a source and a drain.

As is also known in the art, in some FETs, the gates are finger-like gates interconnected to a common gate contact on the top surface of a substrate. Likewise, the individual drains connected to a common drain contact electrode and the sources are connected to a common source contact using air bridges over the gate fingers and over either the drains, or over the sources, and with air bridges connected to a common drain, or source, contact on the bottom surface of the substrate. A FET with the air bridges over the drains is shown in <FIG>. Generally, many of these are FET cells are stacked together in a linear array in the output stage of a power amp Monolithic Microwave Integrated Circuit (MMIC), as shown in <FIG>. The linear stacking of these FET cells determines the linear dimension size of the MMIC.

German patent application publication <CIT> discloses a multi-component transistor which has at least three mutually interconnected regions. Conducting traces run from a central contact on a chip spoke-like outwards, and form contacts for subzones of a zone. Subzones of the other two zones are arranged in a ring around the central contact, and provided with connections projecting outwards. Zones are separated by the spoke-like conducting traces. The source and drawn sections form segments of the same circular ring and have the necessary contacts to connect with the conducting traces.

<CIT> discloses a high-frequency semiconductor device having microwave transmission line being formed by a gate electrode source electrode and a dielectric layer in between. A drain electrode and a source electrode are provided for an intrinsic device section on a GaAs substrate with a gate electrode placed therebetween. Almost all or substantial parts of the GaAs substrate is covered by an extending source electrode extending from the source electrode. A belt-shaped extending drain electrode is provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an output-side microstripline is formed. A belt-shaped extending gate electrode is also provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an input-side microstripline is formed.

<CIT> relates to a semiconductor device structure in a super high frequency region, and more particularly to a structure of a gate via hole type semiconductor device suitable for high power output of a device.

<CIT>does not disclose that one of a source contact or drain contact is connected to a corresponding one of a source pad or drain pad of each one of one or more FET cells through a corresponding one of a plurality of electrically conductive vias passing through a substrate.

<CIT> relates to a semiconductor integrated circuit capable of reducing the loss of a transmission line. The semiconductor integrated circuit includes: a sapphire substrate provided with a via hole penetrating it from its front surface to its back surface.

In accordance with the present disclosure, a Field Effect Transistor (FET) is provided according to claim <NUM>.

In one embodiment, the gate projects outwardly from the gate pad.

In one embodiment, the gate pad is disposed at the center of the circle.

In one embodiment, a strip conductor is disposed on the bottom of the substrate, the feed line having one end connected to the gate contact, the feed line being spaced from the conductor disposed on the bottom surface of the substrate and connected to the gate contact through a gate via passing through the substrate.

In one embodiment, the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line.

In one embodiment, the gate via and the plurality of source vias provide a quasi-coaxial transmission line.

In one embodiment, the loop configuration is a circle.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below.

Referring now to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>, a Field Effect Transistor (FET) <NUM> is shown here formed using photo-lithographic chemical etching processing. More particularly, the FET <NUM> includes a plurality of, here eight, FET cells <NUM><NUM>-<NUM><NUM>, (<FIG>) interconnected by eight air bridges <NUM><NUM>-<NUM><NUM> and controlled by a corresponding one of eight gates G<NUM>-G<NUM>, respectively (<FIG> and <FIG>; <FIG> showing the FET <NUM> with the air bridges <NUM><NUM>-<NUM><NUM> removed to more clearly show the cells <NUM><NUM>-<NUM><NUM>). Each one of the FET cells <NUM><NUM>-<NUM><NUM> has, on an upper, planar surface <NUM> of a semiconductor substrate <NUM>, here for example a substrate having gallium nitride (GaN), a corresponding one of eight gates G<NUM>-G<NUM>, respectively, in Schottky contact with the surface <NUM> of the semiconductor substrate <NUM>, as shown in <FIG>; each one of the eight gates G<NUM>-G<NUM> being disposed between a source (S) and a drain (D) in a manner to be described in more detail hereinafter to control a flow of carriers along a channel between the source pad (S) and drain pad (D) of each one of the eight, FET cells <NUM><NUM>-<NUM><NUM>. Suffice it to say here; however that each one of the gates G<NUM>-G<NUM> is here an elongated, finger-like gate and extends radially outward from a central, circular shaped gate pad <NUM>, as shown. The gate pad <NUM> is electrically connected to a gate contact <NUM>, shown more clearly in <FIG>) disposed on a bottom surface <NUM> (FIG. 2B) of the semiconductor substrate <NUM> through an electrically conductive gate via <NUM> disposed at the center of the gate pad <NUM> and passing vertically through the substrate <NUM> between the gate pad <NUM> and the gate contact <NUM> (<FIG> and <FIG>). The elongated, finger-like gates G<NUM>-G<NUM> are regularly spaced about the outer periphery of the common gate pad <NUM>. More particularly, the finger-like gate electrodes G<NUM>-G<NUM> are electrically interconnected to successive, evenly spaced points, P, (<FIG>) along an outer edge of the common, circular shaped, gate pad <NUM>. Thus, the here eight elongated, finger-like gates G<NUM>-G<NUM> are separated one from the other by here forty-five degrees.

The FET <NUM> also includes a drain contact <NUM> disposed on the upper surface <NUM> of the substrate <NUM> and terminating in a circular ring-like structure <NUM> (<FIG>) having a plurality of, here four, radially inwardly extending projections <NUM><NUM>-<NUM><NUM> regularly spaced about an outer, circumferential rim of the circular structure <NUM>; each one of the projections <NUM><NUM>-<NUM><NUM> is a drain pad in ohmic contacted with the surface <NUM> of the semiconductor substrate <NUM>. Each one of the projections <NUM><NUM>-<NUM><NUM> provides a drain (D) (<FIG>, <FIG>, <FIG>) for a pair of adjacent FET cells <NUM><NUM>-<NUM><NUM>, in a manner to be described in more detail hereinafter. The central axis of the circular structure <NUM> and the center of the circular, common pad <NUM> are co-axial and are disposed along a common vertical Z axis, such Z axis being perpendicular to the X-Y planar surface <NUM> (<FIG>). Thus, here the surface <NUM> is in the X-Y plane and the common vertical axis is along the Z-axis. Thus, here the projections <NUM><NUM>-<NUM><NUM> are spaced one from another by ninety degrees. It is noted that the projections <NUM><NUM>-<NUM><NUM> terminate a predetermined distance from the outer periphery of the common gate pad <NUM> (<FIG>). It is also noted that each one of the projections <NUM><NUM>-<NUM><NUM> is disposed between every other adjacent pair of the finger-like gates G<NUM>-G<NUM>; as shown most clearly in <FIG>. Thus, each one of the projections <NUM><NUM> - <NUM><NUM> provides two drains (D) for the FET <NUM>, one radial positioned side region of the projection <NUM><NUM> - <NUM><NUM> providing a drain for one of the eight FET cells <NUM><NUM>-<NUM><NUM> and the opposite radially positioned side region providing a drain for the adjacent one of the eight FET cells <NUM><NUM>-<NUM><NUM>. Thus, here, projection <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; projection <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; projection <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; and projection <NUM><NUM> is disposed between gates G<NUM> and G<NUM>. More particularly, looking vertically downward on the FET <NUM> and progressing clockwise; one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; and one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>.

An annular structure <NUM> (<FIG>) having a center coaxial with both the gate pad <NUM> and the circular ring-like structure <NUM> (along the Z-axis) has four source pads <NUM><NUM> - <NUM><NUM> (<FIG>, <FIG> and <FIG>) regularly spaced circumferentially about the annular structure <NUM>; that is the source pads <NUM><NUM> - <NUM><NUM> are spaced one from the other by ninety degrees and are disposed on the upper surface <NUM> (<FIG>, <FIG> and <FIG>). Each one of the source pads <NUM><NUM>-<NUM><NUM> is in ohmic contacted with the surface <NUM> of the semiconductor substrate <NUM>. The source pads <NUM><NUM> - <NUM><NUM> (<FIG>) are electrically interconnected by the air bridges <NUM><NUM>-<NUM><NUM> (<FIG>, <FIG> and <FIG>; the air bridges <NUM><NUM>-<NUM><NUM> not being shown in <FIG> as mentioned above). Thus, the each one of the air bridges <NUM><NUM>-<NUM><NUM> is elevated from the surface <NUM> and, more particularly, each one of the air bridges <NUM><NUM>-<NUM><NUM> is elevated from a corresponding one of the projections <NUM><NUM>-<NUM><NUM> and over a pair of adjacent G<NUM>-G<NUM> on each side of the such corresponding one of the projections; one gate finger on either side of the projection <NUM><NUM>-<NUM><NUM>. Thus, air bridge <NUM><NUM> is over projection <NUM><NUM> and over gate fingers G<NUM> and G<NUM>; air bridge <NUM><NUM> is over projection <NUM><NUM> and over gate fingers G<NUM> and G<NUM>; air bridge <NUM><NUM> is over projection <NUM><NUM> and over gate fingers G<NUM> and G<NUM>; and air bridge <NUM><NUM> is over projection <NUM><NUM> and over gate fingers G<NUM> and G<NUM>; as indicated in <FIG> and <FIG>. Thus, it is noted that each one of the four source pads <NUM><NUM> - <NUM><NUM> is disposed between an adjacent pair of the finger-like gates G<NUM>-G<NUM>. Thus, source pad <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; source pad <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; source pad <NUM><NUM> is disposed between gates G<NUM> and G<NUM>; and source pad <NUM><NUM> is disposed between gates G<NUM> and G<NUM> as shown in <FIG>. Thus, each one of the source pads <NUM><NUM> - <NUM><NUM> provides two sources (S) for the FET <NUM>, one radial positioned side region of the source pad <NUM><NUM> - <NUM><NUM> providing a source (S) for one of the eight FET cells <NUM><NUM>-<NUM><NUM> and the opposite radially positioned side region providing a source (S) for the adjacent one of the eight FET cells <NUM><NUM>-<NUM><NUM>. Thus, each one of the gate fingers G<NUM>-G<NUM> is disposed between a source (S) and drain (D), with each one of the fingers G<NUM>-G<NUM> being adjacent one side of one of the source (S) and one side of the drain (D) while an adjacent one of the gate fingers G<NUM>-G<NUM> is adjacent the other side of the same drain (D) and one of the source (S). It follows then that each gate finger (G) shares a drain (D) provided by one of the projections or drain pads <NUM><NUM>-<NUM><NUM> and a source (S) provided by an adjacent one of the source pads22<NUM> - <NUM><NUM>.

Referring again to <FIG>, a source contact <NUM>, here provided by an electrical conductor <NUM> on the bottom surface <NUM> of the substrate <NUM> is electrically connected to the sources pads <NUM><NUM>-<NUM><NUM> of the FET cells <NUM><NUM>-<NUM><NUM> through, here four vias <NUM> (<FIG>, <FIG> and <FIG>) passing vertically through the substrate <NUM> between the conductor <NUM> and the four source pads <NUM><NUM>-<NUM><NUM>. Also formed on the bottom surface <NUM> of the substrate <NUM> is a conductive feed <NUM> (<FIG>) for the gate pad <NUM>. The feed <NUM> is a strip conductor <NUM> terminating in the gate contact <NUM>. The gate contact <NUM> is connected to the gate pad <NUM> with a gate via <NUM>. It is noted that the gate via <NUM> is disposed within a circular array of the vias <NUM> thus forming a vertical quasi coaxial transmission line. It is also noted that the electrical conductor <NUM> (<FIG>) and feed <NUM> are electrically insulated from each other by the portion of the substrate <NUM> in the space between the feed <NUM> and the electrical conductor <NUM>, as indicated. Thus, the conductor <NUM> on the bottom of the substrate <NUM> is spaced a predetermined distance from the feed line <NUM>, as indicated, to provide a coplanar waveguide (CPW) transmission line feed for the <NUM>. Thus, an RF input signal is fed to the FET <NUM> through the backside in a quasi-coax approach.

Thus, the FET cells <NUM><NUM>-<NUM><NUM> are disposed in an X-Y plane in a closed loop configuration, here for example, a circular configuration in the X-Y plane (<FIG> and <FIG>) on the upper surface <NUM> of the substrate <NUM>. The FET <NUM> is suitable for flip chip mounting to a printed circuit board.

Referring now to <FIG>, here the FET <NUM>' has the air bridges <NUM><NUM>-<NUM><NUM> eliminated since each one of the source pads <NUM><NUM>-<NUM><NUM> is connected to ground conductor <NUM> of the bottom of the substrate <NUM> with the vias <NUM>. More particularly, it was recognized that because the gates G1-G8 extend radially out from the pad <NUM>, the source pads <NUM><NUM>-<NUM><NUM> are triangular shaped and thus flare out from the center of the pad <NUM>, there is now sufficient space towards the base of the triangle for placement of a via <NUM> thus eliminating the need for air bridges. To put it another way, the gate to gate spacing spreads out as one moves away from the center of the FET which allows for vias <NUM> for each source pad without growing the size of the FET.

Thus, here the FET <NUM>' again includes the plurality of, here eight, FET cells <NUM><NUM>-<NUM><NUM>, (<FIG>); here, however they are interconnected by the electrical conductor <NUM> through the vias <NUM>. More particularly, as described above and shown more clearly in <FIG>, one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>; and one side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM> while the opposite side region of projection <NUM><NUM> provides the drain for FET cell <NUM><NUM>.

The drain / RF output can be bonded to from the topside of this circular FET as shown in <FIG>. Thus, referring to <FIG> the FET <NUM>' mounted to a printed circuit board <NUM> having an input impedance matching network (IMN) and an output impedance matching network (OMN) coupled to the FET <NUM>'. More particularly, the IMN is coupled to the gate contact <NUM> through a microstrip transmission line having a strip conductor <NUM> separated from a ground plane conductor <NUM>. More particularly, the strip conductor <NUM> is connected to the strip conductor <NUM> (<FIG>). The OMN is coupled to the drain contact <NUM> through a conductor <NUM> connecting the strip conductor <NUM> of a microstrip transmission line separated from an underlying portion of the ground plane conductor <NUM>.

A number of embodiments have been described. Nevertheless, it will be understood that other loop configurations may be used such as, for example, an oval or square or rectangular or triangular or other polygon shaped configuration. Further, the source and drain may be reversed in any electrical circuit application; with, in either circuit application, the gate controlling the flow of carriers between a source and a drain.

It should now be appreciated a Field Effect Transistor (FET) according to an embodiment of the invention includes: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate, each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads, a gate contact connected to the gate electrode of each one of the FET cells, a drain contact connected to the drain pad of each one of the FET cells and a source contact connected to source pad of each one of the FET cells; wherein the cells are disposed in a loop configuration. The FET further includes: a gate pad disposed on an upper surface of the substrate connected to the plurality of gate electrodes wherein the gate contact is disposed on an bottom surface of the substrate; wherein an electrically conductive gate via passes through the substrate to electrically connect the gate contact to the gate pad; wherein the gate pad is disposed in an inner region of the loop; and wherein one of the source contact or the drain contact is disposed on the bottom surface of the substrate; wherein one of the source contact or the drain contact is a conductor disposed on the bottom surface of the substrate and is connected to the corresponding one of the source pad or drain pad of each one of the FET cells though a corresponding one of a plurality of electrically conductive vias passing through the substrate. The FET may include one or more of the following features, independently or in combination with another feature, to include: wherein the gate electrodes projects outwardly from the gate pad; wherein the gate pad is disposed at the center of the circle; a strip conductor disposed on the bottom of the substrate, the feed line having one end connected to the gate contact, the feed line being spaced from the conductor disposed on the bottom surface of the substrate; wherein the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line; and wherein the gate via and the plurality of source vias provide a quasi-coaxial transmission line.

Claim 1:
A Field Effect Transistor, FET, comprising:
a plurality of FET cells (<NUM>) having a plurality of source pads (<NUM>), a plurality of drain pads (<NUM>), and a plurality of gate electrodes (G) disposed on an upper surface of a substrate (<NUM>); each one of the FET cells (<NUM>) having a corresponding one of the gate electrodes (G) disposed between one of the source pads (<NUM>) and one of the drain pads (<NUM>);
a gate contact (<NUM>) connected to the gate electrode (G) of each one of the FET cells (<NUM>); a drain contact (<NUM>) connected to the drain pad (<NUM>) of each one of the FET cells (<NUM>); a source contact (<NUM>) connected to the source pad (<NUM>) of each one of the FET cells (<NUM>); wherein the cells (<NUM>) are disposed in a loop configuration;
a gate pad (<NUM>) disposed on the upper surface of the substrate (<NUM>) connected to the plurality of gate electrodes (G) wherein the gate contact (<NUM>) is disposed on a bottom surface of the substrate (<NUM>) and wherein an electrically conductive gate via (<NUM>) passes through the substrate (<NUM>) to electrically connect the gate contact (<NUM>) to the gate pad (<NUM>);
wherein the gate pad (<NUM>) is disposed in an inner region of the loop configuration; and
wherein one of the source contact (<NUM>) or drain contact (<NUM>) is a conductor disposed on the bottom surface of the substrate (<NUM>) and is connected to the corresponding one of the source pad or drain pad of each one of the FET cells (<NUM>) through a corresponding one of a plurality of electrically conductive vias (<NUM>) passing through the substrate (<NUM>).