Patent Description:
High power, radio frequency (RF) transistor devices are commonly used in RF communication infrastructure amplifiers. These RF transistor devices typically include one or more input leads, one or more output leads, one or more transistors, one or more bias leads, and various bondwires coupling the leads to the transistor(s). In some cases, input and output circuits also may be contained within the same package that contains the device's transistor(s). More specifically, an in-package input circuit (e.g., including an input impedance matching circuit) may be coupled between a device's input lead and a control terminal (e.g., the gate) of a transistor, and an in-package output circuit (e.g., including an output impedance matching circuit) may be coupled between a current conducting terminal (e.g., the drain) of a transistor and a device's output lead.

Instantaneous signal bandwidth (ISBW) is becoming a major requirement for RF communication infrastructure amplifiers, and thus for the high-power RF transistor devices included in such amplifiers. Along with an impedance matching circuit, an RF device's output circuit also may include a baseband decoupling circuit configured to provide an RF ground down to envelope frequencies. Generally, the ISBW of the device is limited by the low frequency resonance (LFR) caused by interaction between the device's bias feeds and components of such a baseband decoupling circuit. In recent years, RF transistor devices have been developed with limited LFRs in the range of about <NUM> megahertz (MHz) or less, which supports ISBWs in the range of about <NUM> or less. Although these devices are sufficient for some applications, the desire for wider RF bandwidth amplifiers continues to increase.

United States patent application publication number <CIT> discloses an integrated passive device assembly for RF amplifiers including two RF capacitors and a MIM capacitor integrally formed within a substrate, and methods of making the same. The device assembly may include a cap.

United States patent application publication number <CIT> discloses a semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding. United States patent application publication number <CIT> discloses an RF device with an electromagnetic interference shielding.

Various optional features are elaborated in the dependent claims.

A conventional RF amplifier device includes an active device (e.g., a transistor), an input impedance matching circuit coupled between an input to the RF amplifier device and an input to the active device, and an output circuit (including an output impedance matching circuit) coupled between an output of the active device and an output of the RF amplifier device. Examples of RF amplifier devices discussed herein may also include a baseband decoupling circuit in the output circuit, which is configured to provide an RF ground down to envelope frequencies. These RF amplifier device embodiments can include output circuit components that may support wider RF bandwidth amplifiers than are achievable using conventional components, while meeting various performance requirements and other criteria. For example, assuming a <NUM>:<NUM> ratio of low frequency resonance (LFR) to instantaneous signal bandwidth (ISBW), embodiments may enable transmission of signals with a <NUM> megahertz (MHz) or above ISBW, which corresponds to low LFRs of approximately <NUM> or greater. In other cases, the LFR to ISBW ratio could be from <NUM>:<NUM> to <NUM>:<NUM>, depending on the system used for linearization (e.g., the digital pre-distortion (DPD) system).

In various embodiments, a baseband decoupling circuit with a relatively large capacitance value, referred to herein as an envelope capacitance or "Cenv", is used to achieve an increased LFR (and thus increased ISBW). Use of low temperature co-fired ceramic (LTCC) structure to integrate baseband decoupling can improve ISBW and help to achieve target LFRs of <NUM> gigahertz (GHz) and higher. However, in certain applications, the LTCC material used for low frequency decoupling can have losses in carrier frequencies and reduce performance. RF shielding in LTCC devices can help enhance performance by reducing eddy currents and controlling the current return path of the RF signals in the packaged transistor, but LTCC shielding may face cost and manufacturing issues in certain devices. As such, RF shielding approaches may be desired for shielding integrated passive devices (IPDs) fabricated using semiconductor-based structures.

In a conventional high-power RF transistor device, the transistor and components of the output circuit are mounted on a conductive substrate or flange, and forward current between the transistor and the output lead is carried through bondwires between the transistor and the output lead. Reverse current, on the other hand, is carried in an opposite direction across the surface of the conductive substrate. In this configuration, eddy currents develop during operation in the space between the forward-current-carrying bondwires and the reverse-current-carrying substrate surface. In devices in which these eddy currents pass though low-Q material (e.g., material with high loss tangent) positioned between the forward and reverse current paths, the devices may experience significant power loss through the low-Q material at the carrier frequencies.

To overcome this issue, embodiments of the inventive subject matter include a current path structure that circumscribes the low-Q material (e.g., dielectric materials included in Cenv), thus substantially reducing or eliminating power losses through that low-Q material. In other words, the current path structure substantially eliminates the presence of relatively lossy low-Q material between the device's forward and return current paths. More specifically, in one embodiment, a "reverse current path structure" is configured to carry reverse current, and it is physically positioned between Cenv and the forward current path.

<FIG> is a schematic diagram of an RF amplifier device <NUM>. Device <NUM> includes an input lead <NUM>, an input impedance matching circuit <NUM>, a transistor <NUM>, an output impedance matching circuit <NUM>, an envelope frequency termination circuit <NUM>, and an output lead <NUM>, in an embodiment. The output impedance matching circuit <NUM> and the envelope frequency termination circuit <NUM> may be referred to collectively as an "output circuit. " Although transistor <NUM> and various elements of the input and output impedance matching circuits <NUM>, <NUM> and the envelope frequency termination circuit <NUM> are shown as singular components, the depiction is for the purpose of ease of explanation only. Those of skill in the art would understand, based on the description herein, that transistor <NUM> and/or certain elements of the input and output impedance matching circuits <NUM>, <NUM> and the envelope frequency termination circuit <NUM> each may be implemented as multiple components (e.g., connected in parallel or in series with each other), and examples of such embodiments are illustrated in the other Figures and described later. For example, embodiments may include single-path devices (e.g., including a single input lead, output lead, transistor, etc.), dual-path devices (e.g., including two input leads, output leads, transistors, etc.), and/or multi-path devices (e.g., including two or more input leads, output leads, transistors, etc.). Further, the number of input/output leads may not be the same as the number of transistors (e.g., there may be multiple transistors operating in parallel for a given set of input/output leads). The description of transistor <NUM> and various elements of the input and output impedance matching circuits <NUM>, <NUM> and the envelope frequency termination circuit <NUM>, below, thus are not intended to limit the scope of the inventive subject matter only to the illustrated embodiments.

Input lead <NUM> and output lead <NUM> each include a conductor, which is configured to enable the device <NUM> to be electrically coupled with external circuitry (not shown). More specifically, input and output leads <NUM>, <NUM> are physically located between the exterior and the interior of the device's package. Input impedance matching circuit <NUM> is electrically coupled between the input lead <NUM> and a first terminal of transistor <NUM>, which is also located within the device's interior, and output impedance matching circuit <NUM> and envelope frequency termination circuit <NUM> are electrically coupled between a second terminal of transistor <NUM> and the output lead <NUM>.

According to an embodiment, transistor <NUM> is the primary active component of device <NUM>. Transistor <NUM> includes a control terminal and two current conducting terminals, where the current conducting terminals are spatially and electrically separated by a variable-conductivity channel. For example, transistor <NUM> may be a field effect transistor (FET) (such as a metal oxide semiconductor FET (MOSFET)) or a high electron mobility transistor (HEMT), each of which includes a gate (control terminal), a drain (a first current conducting terminal), and a source (a second current conducting terminal). Alternatively, transistor <NUM> may be a bipolar junction transistor (BJT). Accordingly, references herein to a "gate," "drain," and "source," are not intended to be limiting, as each of these designations has analogous features for a BJT implementation (e.g., a base, collector, and emitter, respectively). According to an embodiment, and using nomenclature typically applied to MOSFETs in a non-limiting manner, the gate of transistor <NUM> is coupled to the input impedance matching circuit <NUM>, the drain of transistor <NUM> is coupled to the output impedance matching circuit <NUM> and the envelope frequency termination circuit <NUM>, and the source of transistor <NUM> is coupled to ground (or another voltage reference). Through the variation of control signals provided to the gate of transistor <NUM>, the current between the current conducting terminals of transistor <NUM> may be modulated.

Input impedance matching circuit <NUM> is configured to raise the impedance of device <NUM> to a higher (e.g., intermediate or higher) impedance level (e.g., in a range from about <NUM> to about <NUM> Ohms or higher). This can be advantageous in that it allows the printed circuit board level (PCB-level) matching interface from a driver stage to have an impedance that can be achieved in high-volume manufacturing with minimal loss and variation (e.g., a "user friendly" matching interface). Input impedance matching circuit <NUM> is coupled between the input lead <NUM> and the control terminal (e.g., gate) of the transistor <NUM>. According to an embodiment, input impedance matching circuit <NUM> is a low pass circuit, which includes two inductive elements <NUM>, <NUM> (e.g., two sets of bondwires) and a shunt capacitor <NUM>. A first inductive element <NUM> (e.g., a first set of bondwires) is coupled between input lead <NUM> and a first terminal of capacitor <NUM>, and a second inductive element <NUM> (e.g., a second set of bondwires) is coupled between the first terminal of capacitor <NUM> and the control terminal of transistor <NUM>. The second terminal of capacitor <NUM> is coupled to ground (or another voltage reference). The combination of inductive elements <NUM>, <NUM> and shunt capacitor <NUM> functions as a low-pass filter. According to an embodiment, the series combination of inductive elements <NUM>, <NUM> may have a value in a range between about <NUM> picohenries (pH) to about <NUM> nanohenries (nH), and shunt capacitor <NUM> may have a value in a range between about <NUM> picofarads (pF) to about <NUM> pF.

Output impedance matching circuit <NUM> is configured to match the output impedance of device <NUM> with the input impedance of an external circuit or component (not shown) that may be coupled to output lead <NUM>. Output impedance matching circuit <NUM> is coupled between the first current conducting terminal (e.g., drain) of transistor <NUM> and the output lead <NUM>. According to an embodiment, output impedance matching circuit <NUM> includes three inductive elements <NUM>, <NUM>, <NUM> (e.g., three sets of bondwires) and two capacitors <NUM>, <NUM>. Output impedance matching circuit <NUM> includes a high-pass matching circuit <NUM> (including inductive element <NUM> and capacitor <NUM>) and a low-pass matching circuit <NUM> (including inductive elements <NUM>, <NUM> and capacitor <NUM>), in an embodiment.

In the low-pass matching circuit <NUM>, inductive elements <NUM>, <NUM> (e.g., third and fourth sets of bondwires), also referred to herein as "LLP1" and "LLP2", are coupled in series between the first current conducting terminal (e.g., drain) of transistor <NUM> and the output lead <NUM>, with node <NUM> between inductive elements <NUM>, <NUM>. Capacitor <NUM>, also referred to herein as "CLP", has a first terminal coupled to node <NUM>, and a second terminal coupled to a ground node <NUM>, which in turn may be coupled to ground (or to another voltage reference). The combination of inductive elements <NUM>, <NUM> and capacitor <NUM> functions as a first (low-pass) matching stage. According to an embodiment, the series combination of inductive elements <NUM>, <NUM> may have a value in a range between about <NUM> pH to about <NUM> nH, and capacitor <NUM> may have a value in a range between about <NUM> pF to about <NUM> pF, although these components may have values outside of these ranges, as well.

In the high-pass matching circuit <NUM>, inductive element <NUM> (e.g., a fifth set of bondwires), also referred to as "Lshunt", is coupled between the first current conducting terminal of transistor <NUM> and a first terminal of capacitor <NUM>, also referred to as "Cshunt". A second terminal of capacitor <NUM> is coupled to a ground node <NUM>. The combination of inductive element <NUM> and capacitor <NUM> functions as a second (high-pass) matching stage. According to an embodiment inductive element <NUM> may have a value in a range between about <NUM> pH to about <NUM> nH, and capacitor <NUM> may have a value in a range between about <NUM> pF to about <NUM> pF, although these components may have values outside of these ranges, as well.

An RF "cold point" is present at the node <NUM> between inductive element <NUM> and capacitor <NUM>, where the RF cold point represents a high impedance point in the circuit to signals having RF frequencies. Envelope frequency termination circuit <NUM> is coupled between the RF cold point (at node <NUM>) and ground node <NUM>, in an embodiment. Envelope frequency termination circuit <NUM> functions to improve the low frequency resonance of device <NUM> caused by the interaction between the output impedance matching circuit <NUM> and the bias feeds by presenting a high impedance at RF frequencies. Envelope frequency termination circuit <NUM> essentially is "invisible" from a matching standpoint, as it only effects the output impedance at envelope frequencies (i.e., envelope frequency termination circuit <NUM> provides terminations for the envelope frequencies of device <NUM>).

According to an embodiment, envelope frequency termination circuit <NUM> includes a resistor <NUM>, an inductance <NUM>, and a capacitor <NUM> coupled in series. A first terminal of resistor <NUM>, referred to herein as an "envelope resistor" or "Renv," is coupled to node <NUM> (i.e., the RF cold point). At node <NUM>, a second terminal of envelope resistor <NUM> is coupled to a first terminal of inductance <NUM>, referred to herein as an "envelope inductor" or "Lenv. " At node <NUM>, a second terminal of inductance <NUM> is coupled to capacitor <NUM>, referred to herein as an "envelope capacitor" or "Cenv. " A second terminal of the envelope capacitor <NUM> is coupled to the ground node <NUM>, in an embodiment. Envelope resistor <NUM> may have a value in a range between about <NUM> Ohm to about <NUM> Ohm, envelope inductance <NUM> may have a value that is less than about <NUM>-<NUM> pH, and envelope capacitor <NUM> may have a value in a range between about <NUM> nanofarads (nF) to about <NUM> microfarad (µF), although these components may have values outside of these ranges, as well. Although envelope inductance <NUM> is shown to include a single lumped element in <FIG>, envelope inductance <NUM> actually may be made up of one or more distinct inductors (e.g., inductor <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>) and additional small inductances associated with other conductive features (e.g., conductive vias and portions of conductive traces) present in the conductive path between RF cold point node <NUM> and ground node <NUM>.

<FIG> is a top view of an example of a packaged RF amplifier device <NUM> that embodies the circuit of <FIG>, in accordance with an example embodiment. More particularly, the interconnected electrical components and elements of device <NUM> may be modeled by the schematic diagram of <FIG>. For enhanced understanding, <FIG> should be viewed in parallel with <FIG>, which is a cross-sectional, side view of the RF amplifier device <NUM> of <FIG> along line <NUM>-<NUM>.

Device <NUM> includes an input lead <NUM> (e.g., input lead <NUM>, <FIG>), an output lead <NUM> (e.g., output lead <NUM>, <FIG>), bias leads <NUM>, a flange <NUM>, an isolation structure <NUM>, and three parallel amplification paths (i.e., three parallel instantiations of circuit <NUM>, <FIG>) electrically coupled between the input and output leads <NUM>, <NUM>. Each amplification path includes an input impedance matching circuit <NUM> (e.g., input impedance matching circuit <NUM>, <FIG>), a transistor <NUM> (e.g., transistor <NUM>, <FIG>), an output impedance matching circuit <NUM> (e.g., output impedance matching circuit <NUM>, <FIG>), and an envelope frequency termination circuit <NUM> (e.g., envelope frequency termination circuit <NUM>, <FIG>).

Flange <NUM> includes a rigid electrically-conductive substrate, which has a thickness that is sufficient to provide structural support for other components and elements of device <NUM>. In addition, flange <NUM> may function as a heat sink for transistors <NUM> and other devices mounted on flange <NUM>. Flange <NUM> has a top and bottom surface and a substantially-rectangular perimeter that corresponds to the perimeter of the device <NUM>. In <FIG>, only a central portion of the top surface of flange <NUM> is visible through an opening in isolation structure <NUM>. At least the surface of flange <NUM> is formed from a layer of conductive material, and possibly all of flange <NUM> is formed from bulk conductive material. Alternatively, flange <NUM> may have one or more layers of non-conductive material below its top surface. Either way, flange <NUM> has a conductive top surface. When device <NUM> is incorporated into a larger electrical system, flange <NUM> may be used to provide a ground reference for the device <NUM>.

Isolation structure <NUM> has a frame shape, in an embodiment, which includes a substantially enclosed, four-sided structure with a central opening. Isolation structure <NUM> may have a substantially rectangular shape, as shown in <FIG>, or isolation structure <NUM> may have another shape (e.g., annular ring, oval, and so on). Isolation structure <NUM> may be formed as a single, integral structure, or isolation structure <NUM> may be formed as a combination of multiple members. For example, in an alternate embodiment, isolation structure <NUM> may include multiple portions that contact each other or that are spatially separated from each other (e.g., isolation structure <NUM> may have one portion isolating input lead <NUM> from flange <NUM>, and another portion isolating output lead <NUM> from flange <NUM>). In addition, isolation structure <NUM> may be formed from a homogenous material, or isolation structure <NUM> may be formed from multiple layers.

The input and output leads <NUM>, <NUM> and the bias leads <NUM> are mounted on a top surface of the isolation structure <NUM> on opposed sides of the central opening, and thus the input and output leads <NUM>, <NUM> and the bias leads <NUM> are elevated above the top surface of the flange <NUM>, and are electrically isolated from the flange <NUM>. For example, the leads <NUM>, <NUM>, <NUM> may be soldered or otherwise attached to metallization (not shown) on a top surface of isolation structure <NUM> (e.g., a metallurgic connection). Generally, the leads <NUM>, <NUM>, <NUM> are oriented to allow for attachment of bondwires (e.g., bondwires <NUM>, <NUM>) between the leads <NUM>, <NUM>, <NUM> and components and elements within the central opening of isolation structure <NUM>.

According to an embodiment, bias leads <NUM> are electrically coupled together with a bar-shaped conductor <NUM>, which also is coupled to the top surface of isolation structure <NUM>. According to a particular embodiment, conductor <NUM> includes metallization on a top surface of isolation structure <NUM>. Proximal ends of bias leads <NUM> are coupled to opposite ends of conductor <NUM>, in an embodiment. Bondwires (not shown) are electrically coupled between conductor <NUM> and a bias point (e.g., cold point node <NUM>, <NUM>, <FIG>, <FIG>).

Bias leads <NUM> extend from the device <NUM>, once packaged, so that their distal ends are exposed and may be coupled to a printed circuit board (PCB) of a larger system to receive a bias voltage. Accordingly, inclusion of bias leads <NUM> eliminates the need for bias leads on the PCB itself. According to an embodiment, each bias lead <NUM> has a length corresponding to lambda/<NUM>, although each bias lead <NUM> may have a different length, as well. An advantage of including bias leads <NUM> as part of device <NUM> is that the bias leads <NUM> remove the need for quarter wave bias feeds, as additional large value de-coupling capacitors may be connected between the bias leads <NUM> and ground as the bias leads <NUM> exit the device package.

Another embodiment may include a four-lead device with an input lead, an output lead, and two bias leads coupled to the input impedance matching circuit. Yet another embodiment includes a six-lead device with an input lead, an output lead, two bias leads coupled to the output impedance matching circuit and two bias leads coupled to the input impedance matching circuit. In still other embodiments, only a single bias lead may be coupled to the input and/or output impedance matching circuits (e.g., particularly for embodiments in which there are more than two RF leads, such as in dual-path and multi-path devices).

Transistors <NUM> and various elements <NUM>, <NUM> of the input and output impedance matching circuits <NUM>, <NUM> and the envelope frequency termination circuit <NUM> are mounted on a generally central portion of the top surface of a flange <NUM> that is exposed through the opening in isolation structure <NUM>. For example, the transistors <NUM> and elements <NUM>, <NUM> of the input and output impedance matching circuits <NUM>, <NUM> and the envelope frequency termination circuit <NUM> may be coupled to flange <NUM> using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds. As used herein, an "active device area" corresponds to a portion of a device on which one or more active devices (e.g., transistor <NUM>) are mounted (e.g., the portion of the conductive surface of flange <NUM> that exposed through the opening in isolation structure <NUM>).

Each of transistors <NUM> has a control terminal (e.g., a gate) and two current conducting terminals (e.g., a drain and a source). The control terminal of each transistor <NUM> is coupled to the input lead <NUM> through an input impedance matching circuit <NUM> (e.g., input impedance matching circuit <NUM>, <FIG>). In addition, one current conducting terminal (e.g., the drain) of each transistor <NUM> is coupled to the output lead <NUM> through an output impedance matching circuit <NUM> (e.g., output impedance matching circuit <NUM>, <FIG>), and the other current conducting terminal (e.g., the source) is coupled to the flange <NUM> (e.g., to a ground reference node for the device <NUM>).

In the device <NUM> of <FIG>, each input impedance matching circuit <NUM> includes two inductive elements <NUM>, <NUM> (e.g., inductive elements <NUM>, <NUM>, <FIG>) and a capacitor <NUM> (e.g., capacitor <NUM>, <FIG>). Each inductive element <NUM>, <NUM> is formed from a plurality of parallel, closely-spaced sets of bondwires. For example, a first inductive element <NUM> (e.g., inductive element <NUM>, <FIG>) includes a plurality of bondwires coupled between input lead <NUM> and a first terminal of capacitor <NUM> (e.g., capacitor <NUM>, <FIG>), and a second inductive element <NUM> (e.g., inductive element <NUM>, <FIG>) includes a plurality of bondwires coupled between the first terminal of capacitor <NUM> and the control terminal of transistor <NUM>. The second terminal of capacitor <NUM> is coupled to the flange <NUM> (e.g., to ground). Capacitor <NUM> may be, for example, a discrete silicon capacitor (e.g., comprised of a silicon substrate with a top surface corresponding to a first terminal, and a bottom surface corresponding to a second terminal). Bondwires <NUM>, <NUM> are attached to a conductive top plate at the top surface of capacitor <NUM>.

In the device <NUM> of <FIG>, each output impedance matching circuit <NUM> includes three inductive elements <NUM>, <NUM>, <NUM> (e.g., Lshunt <NUM>, LLP1 <NUM>, and LLP2 <NUM>, <FIG>) and two capacitors (e.g., Cshunt <NUM> and CLP <NUM>, <FIG>), where the capacitors form portions of device <NUM> (e.g., device <NUM>, <FIG>), in an embodiment. Again, each inductive element <NUM>, <NUM>, <NUM> is formed from a plurality of parallel, closely-spaced sets of bondwires. For example, shunt inductive element <NUM> (e.g., Lshunt <NUM>, <FIG>) includes a plurality of bondwires coupled between the first current conducting terminal (e.g., the drain) of transistor <NUM> and a first bond pad <NUM> (e.g., corresponding to RF cold point node <NUM>, <FIG>) on a top surface of device <NUM>. The first bond pad <NUM> is electrically coupled to a shunt capacitor (e.g., Cshunt <NUM>, <FIG>) within the device <NUM>. A first series inductive element <NUM> (e.g., LLP1 <NUM>, <FIG>) includes a plurality of bondwires coupled between the first current conducting terminal of transistor <NUM> and a second bond pad <NUM> (e.g., corresponding to node <NUM>, <FIG>) on the top surface of the device <NUM>. The second bond pad <NUM> is electrically coupled to a low pass matching capacitor (e.g., CLP <NUM>, <FIG>) within the device <NUM>. Finally, a second series inductive element <NUM> (e.g., LLP2 <NUM>, <FIG>) is coupled between the second bond pad <NUM> and the output lead <NUM>. Second terminals of the shunt and LP-match capacitors within the device <NUM> are coupled to the flange <NUM> (e.g., to ground).

According to an embodiment, device <NUM> is incorporated in an air cavity package, in which transistors <NUM> and various impedance matching and envelope frequency termination elements are located within an enclosed air cavity <NUM>. Basically, the air cavity is bounded by flange <NUM>, isolation structure <NUM>, and a cap <NUM> overlying and in contact with the isolation structure <NUM> and leads <NUM>, <NUM>. In other embodiments, a device may be incorporated into an overmolded package (i.e., a package in which the electrical components within the active device area are encapsulated with a non-conductive molding compound, and in which portions of the leads <NUM>, <NUM> also may be encompassed by the molding compound).

In the embodiments discussed in conjunction with <FIG>, the output impedance matching circuit <NUM>, <NUM> includes a high-pass shunt circuit <NUM> and a low-pass, LP-match circuit <NUM> (e.g., including inductive elements <NUM>, <NUM> or bondwires <NUM>, <NUM> and capacitor <NUM>). In an alternate embodiment, the low-pass matching circuit <NUM> may be replaced with a differently-configured matching circuit. For example, <FIG> is a schematic diagram of an RF amplifier <NUM> with a second matching circuit <NUM> (e.g., a low-pass matching circuit with a very high frequency resonance) forming a portion of its output impedance matching circuit <NUM>, in accordance with another example embodiment. Except for the replacement of low-pass matching circuit <NUM> with matching circuit <NUM>, and the inclusion of inductive element <NUM>, RF amplifier <NUM> may be substantially similar to the amplifier <NUM> of <FIG>, and like reference numbers are used in both drawings to indicate elements that may be substantially the same between the two embodiments.

In device <NUM>, inductive element <NUM>, or "Lseries", is coupled directly between the first current conducting terminal (e.g., drain) of transistor <NUM> and the output lead <NUM>. In addition, the high-pass matching circuit <NUM>, which includes a "bond back" or "BB" inductive element <NUM> coupled in series with a BB capacitor <NUM>, is coupled between the output lead <NUM> and the ground node <NUM>. More specifically, LBB <NUM> is coupled between the output lead <NUM> and a node <NUM>, and CBB <NUM> is coupled between node <NUM> and the ground node <NUM>. According to an embodiment, Lseries <NUM> may have a value in a range between about <NUM> pH to about <NUM> nH, LBB <NUM> may have a value in a range between about <NUM> pH to about <NUM> pH, and CBB <NUM> may have a value in a range between about <NUM> pF to about <NUM> pF, although these components may have values outside of these ranges, as well.

<FIG> is a top view of an example of a packaged RF amplifier device <NUM> that embodies the circuit of <FIG>, in accordance with an example embodiment. More particularly, the interconnected electrical components and elements of device <NUM> may be modeled by the schematic diagram of <FIG>. For enhanced understanding, <FIG> should be viewed in parallel with <FIG>, which is a cross-sectional, side view of the RF amplifier device <NUM> of <FIG> along line <NUM>-<NUM>. Except for the replacement of low-pass matching circuit <NUM> with low-pass matching circuit <NUM>, and the inclusion of inductive element <NUM> (e.g., inductive element <NUM>, <FIG>), packaged RF amplifier device <NUM> may be substantially similar to the device <NUM> of <FIG> and <FIG>, and like reference numbers are used in both drawings to indicate elements that may be substantially the same between the two embodiments.

In the device <NUM> of <FIG>, each output impedance matching circuit <NUM> includes three inductive elements <NUM>, <NUM>, <NUM> (e.g., Lshunt <NUM>, Lseries <NUM>, and LBB <NUM>, <FIG>) and two capacitors (e.g., Cshunt <NUM> and CBB <NUM>, <FIG>), where the capacitors form portions of device <NUM> (e.g., device <NUM>, <FIG>), in an embodiment. Again, each inductive element <NUM>, <NUM>, <NUM> is formed from a plurality of parallel, closely-spaced sets of bondwires. For example, shunt inductive element <NUM> (e.g., Lshunt <NUM>, <FIG>) includes a plurality of bondwires coupled between the first current conducting terminal (e.g., the drain) of transistor <NUM> and a first bond pad <NUM> (e.g., corresponding to RF cold point node <NUM>, <FIG>) on a top surface of the device <NUM>. The first bond pad <NUM> is electrically coupled to a shunt capacitor (e.g., Cshunt <NUM>, <FIG>) within the device <NUM>. A series inductive element <NUM> (e.g., Lseries <NUM>, <FIG>) includes a plurality of bondwires coupled between the first current conducting terminal of transistor <NUM> and the output lead <NUM>. A bond back inductive element <NUM> (e.g., LBB <NUM>, <FIG>) is coupled between the output lead <NUM> and a second bond pad <NUM> (e.g., corresponding to node <NUM>, <FIG>) on the top surface of the device <NUM>. The second bond pad <NUM> is electrically coupled to a bond back capacitor (e.g., CBB <NUM>, <FIG>) within the device <NUM>. Second terminals of the shunt and bond back capacitors within the device <NUM> are coupled to the flange <NUM> (e.g., to ground).

As will now be further discussed, the RF shielding structures help enhance drain efficiency in packaged transistors by reducing eddy currents, controlling the current return path of RF signals, and decreasing losses from bond pads. Referring initially to the side-view representation of a portion of an unshielded RF amplifier packaged device <NUM> in <FIG>, that does not form part of the present invention but is useful for understanding it, a semiconductor (e.g., silicon) integrated passive device (IPD) <NUM> includes a semiconductor substrate <NUM> (e.g., a silicon or other semiconductor substrate), a high-density capacitor <NUM>, a first RF (shunt) capacitor <NUM>, and a second RF capacitor <NUM>. In the equivalent circuit shown in <FIG>, the high-density capacitor <NUM> corresponds with envelope capacitor <NUM>, first and second RF capacitors <NUM> and <NUM> correspond with capacitors <NUM> and <NUM>, active die <NUM> corresponds with transistor <NUM>, bondwires <NUM>, <NUM>, and <NUM> correspond with inductive elements <NUM>, <NUM>, and <NUM>, respectively, and flange <NUM> corresponds with ground node <NUM> or flange <NUM>.

In one background example, the IPD <NUM> may comprise a portion of a wafer formed from a bulk semiconductor material, e.g., silicon or another suitable semiconductor material with overlying conductive and dielectric layers. The IPD may be formed using a variety of semiconductor processes, including layering dielectric and conductive materials, and patterning the dielectric and conductive material layers, among other processes. In the material layering process, dielectric and conductive materials can be grown or deposited on the wafer substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures.

Generally, the IPD <NUM> may be fabricated from a number of layers of different materials, including insulators, and conductors that are each patterned to form particular structures within the IPD <NUM>. Such structures may include capacitors, inductors, resistors, transmission lines, and conductive vias that electrically connected different material layers within the IPD <NUM>.

After the IPD <NUM> is formed, the wafer may be singulated to separate the IPD <NUM> from other devices that may be formed in the wafer. The IPD <NUM> can then be connected to other components within an amplifier system.

The IPD <NUM> is situated on a flange <NUM> (e.g., flange <NUM>, <FIG>, <FIG>), and on opposing sides of IPD <NUM> are the active die <NUM> (e.g., die <NUM>, <FIG>, <FIG>) and portions of the transistor package, such as a portion of the insulator frame <NUM> (e.g., insulator frame <NUM>, <FIG>, <FIG>) and an output terminal <NUM> (e.g., terminal <NUM> or lead <NUM>, <FIG>). A terminal of the active die <NUM> (e.g., a current conducting terminal, such a drain terminal) is connected to a first terminal <NUM> of the first RF capacitor <NUM> via a first plurality of bondwires <NUM>, and to a first terminal <NUM> of the second RF capacitor <NUM> via a second plurality of bondwires <NUM>. The first terminal <NUM> of the first RF capacitor <NUM> also is connected, through resistor <NUM> (e.g., resistor <NUM>, <FIG>) and inductor <NUM> (e.g., inductor <NUM>, <FIG>) to a first terminal <NUM> of capacitor <NUM>. Second terminals <NUM>, <NUM>, and <NUM> of the first RF capacitor <NUM>, the second RF capacitor <NUM>, and the high-density capacitor <NUM> are connected to the flange <NUM> (e.g., corresponding to node <NUM>, <FIG>, and flange <NUM>, <FIG>, <FIG>). The first terminal <NUM> of the second RF capacitor <NUM> is connected to the output terminal <NUM> (e.g., terminal <NUM> or lead <NUM>, <FIG>) via a third plurality of bondwires <NUM>. It is noted that bondwires <NUM>, <NUM>, and <NUM> correspond with the three inductive elements <NUM>, <NUM>, <NUM> of <FIG>, respectively, and with bondwires <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, respectively.

An electric field in the device <NUM> is represented by electric field lines <NUM> extending from the flange <NUM> to the bondwires <NUM> and <NUM>. A "forward" current Ifwd <NUM> travels from active die <NUM> along bondwires <NUM> and <NUM> and to the output terminal <NUM>. A reverse current Irev <NUM> travels from the output side of the transistor package (e.g., from the portion of insulator frame <NUM> under output terminal <NUM>) to active die <NUM> primarily along the flange <NUM>. During operation, the reverse current <NUM> travels along the surface of the substrate to which IPD <NUM> is attached (e.g., flange <NUM>, <FIG>). The eddy currents develop between the reverse current path <NUM> and the forward current path <NUM>, and those eddy currents can sometimes impinge upon the material from which high-density capacitor <NUM> is formed. The material from which high-density capacitor <NUM> may be a relatively-lossy material, and thus those eddy currents may induce significant losses through the material. In other words, during operation, significant loss may occur through the lossy material of high-density capacitor <NUM>, which is positioned between reverse current path <NUM> and the forward current path <NUM>.

There are at least two types of loss that may be reduced through implementation of the various embodiments. The first type of loss occurs through the lossy material positioned between the forward current <NUM> and reverse current <NUM> paths, as discussed above. The second type of loss occurs through additional, relatively lossy material that is positioned very close to the bond pads <NUM> (e.g., positioned such that the distance ("b") between the lossy material and the bond pad is less than five times the width of bond pad "a"). When current flows along the surface of the bond pad <NUM> (e.g., between ends of bondwires <NUM> and <NUM> that are coupled to the bond pad), the bond pad <NUM> may behave like a microstrip transmission line. If the lossy material (e.g., a high density capacitor <NUM>) is positioned very physically close to the bond pad <NUM>, the lossy material near the bond pad can decrease the quality factor of the bond pad, potentially leading to significant losses through the lossy material.

It is noted that, according to the inventive IPD, a shielding structure is placed between the material from which the IPD's high-density capacitor is formed and the bond pads of the IPD's RF capacitors, which may allow the high-density capacitor to be positioned closer to bond pads, without incurring the losses that may otherwise be experienced without the shielding structure.

It is also noted that, to achieve a relatively high quality factor for the bond pads of the IPD's second RF capacitor (which may behave as a microstrip transmission line), the dielectric layer of the IPD's second RF capacitor may preferably have a low loss tangent. This can improve the quality factor of the bond pads and may further reduce losses.

It is moreover noted that, in certain devices, both types of losses are caused by eddy currents in the high density capacitor. However, the first type of loss generally results when the lossy material of the high density capacitor is positioned between reverse current path <NUM> and the forward current path <NUM>, while the second type of loss generally results when the lossy material of the high density capacitor is positioned very close to bond pad <NUM>, which can behave like a microstrip transmission line.

As discussed above, for conventional devices, RF performance may degrade when using integrated structures like high-density capacitor <NUM> with semiconductor-based technology because of potential eddy currents being generate within the material of high density capacitor <NUM>. Further, losses from bond pads could reduce drain efficiency in packaged transistors.

According to various embodiments, a modified path for the return current, which may function as a shielding structure, addresses the performance degradation mentioned above. Referring to the side-view representation of the inventive shielded device <NUM> in <FIG>, a shielded semiconductor (e.g., silicon) IPD <NUM> includes a high-density capacitor <NUM>, a first RF (shunt) capacitor <NUM>, and a second RF capacitor <NUM>. In the circuit shown in <FIG>, the high-density capacitor <NUM> corresponds with envelope capacitor <NUM>, and first and second RF capacitors <NUM> and <NUM> correspond with capacitors <NUM> and <NUM>.

The IPD <NUM> is situated on a flange <NUM> (e.g., corresponding to flange <NUM>, <FIG>, <FIG>), and on opposing sides of IPD <NUM> are the active die <NUM> (e.g., die <NUM>, <FIG>, <FIG>) and portions of the transistor package, such as a portion of the insulator frame <NUM> (e.g., insulator frame <NUM>, <FIG>, <FIG>) and an output terminal <NUM> (e.g., terminal <NUM> or lead <NUM>, <FIG>). A terminal of the active die <NUM> (e.g., a current conducting terminal, such as a drain terminal) is connected to a first terminal <NUM> of the first RF capacitor <NUM> via a first plurality of bondwires <NUM>, and to a first terminal <NUM> of the second RF capacitor <NUM> via a second plurality of bondwires <NUM>. The first terminal <NUM> of the first RF capacitor <NUM> also is connected, through resistor <NUM> (e.g., resistor <NUM>, <FIG>) and inductor <NUM> (e.g., inductor <NUM>, <FIG>) to a first terminal <NUM> of capacitor <NUM>. Second terminals (not numbered or shown in <FIG>) of the first RF capacitor <NUM> and the second RF capacitor <NUM> are connected to the flange <NUM> (e.g., corresponding to node <NUM>, <FIG>, and flange <NUM>, <FIG>, <FIG>). Similarly, the second terminal <NUM> of the high-density capacitor <NUM> is connected to the flange <NUM>. The first terminal <NUM> of the second RF capacitor <NUM> is connected to the output terminal <NUM> (e.g., terminal <NUM> or lead <NUM>, <FIG>) via a third plurality of bondwires <NUM>. It is noted that bondwires <NUM>, <NUM>, and <NUM> correspond with the three inductive elements <NUM>, <NUM>, <NUM> of <FIG>, respectively, and with bondwires <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, respectively.

The shielding structure <NUM> includes a continuous conductive path, which includes a first vertical portion <NUM>, an elevated horizontal portion <NUM>, and a second vertical portion <NUM>. Ends of the first and second vertical portions <NUM>, <NUM> of the shielding structure <NUM> that are proximate to the bottom surface of the IPD <NUM> are electrically coupled to the flange <NUM>, in an embodiment. The elevated horizontal portion <NUM> is located above the high-density capacitor <NUM>, according to the present invention.

Note that in <FIG>, the view depicted shows elevated horizontal portion <NUM> as two different segments (allowing for the vertical interconnect extending from inductor <NUM> to high density capacitor <NUM>), but both segments <NUM> are electrically connected to one another forming a single conductor structure <NUM> that extends at least from first vertical portion <NUM> to second vertical portion <NUM>. Accordingly, the materials from which the high-density capacitor <NUM> is formed are located between the top surface of the flange <NUM> and the horizontal portion <NUM> of the shielding structure <NUM>. An electric field is represented by electric field lines <NUM> extending from a first portion of the flange <NUM> (between active die <NUM> and the left vertical portion <NUM> of shielding <NUM>), from the horizontal portion <NUM> of the shielding structure <NUM>, and from a second portion of the flange (between the right vertical portion <NUM> of shielding <NUM> and the insulator frame <NUM>) to the bondwires <NUM> and <NUM>.

During operation, a "forward" current Ifwd <NUM> travels from the output terminal (e.g., drain terminal) of active die <NUM> along bondwires <NUM> and <NUM> and to the output terminal <NUM>. A "return" current Irev <NUM> travels across the flange <NUM> from the insulator frame <NUM>, and when it reaches the portion of the flange <NUM> that is electrically connected to the reverse conductive path structure <NUM> of the IPD <NUM> (or more specifically to vertical portion <NUM>), significant portions of the reverse current <NUM> travel from the flange <NUM> at the right side of the IPD <NUM> into and through the reverse conductive path structure <NUM> to the flange <NUM> at the left side of the IPD <NUM>, rather than traveling along the portion of the surface of the flange <NUM> to which IPD <NUM> is attached (e.g., the portion of flange <NUM> underlying the reverse conductive path structure <NUM> and between the vertical portions <NUM>, <NUM> of the reverse conductive path structure <NUM>). Although eddy currents still may develop between the reverse current path <NUM> and the forward current path <NUM>, those eddy currents are above the material from which the high-density capacitor <NUM> is formed, and thus the eddy currents would not significantly impinge upon the relatively lossy material of the high-density capacitor <NUM>. Accordingly, those eddy currents may not induce significant losses through the high-density capacitor <NUM>. In other words, the reverse current path structure <NUM> substantially reduces or eliminates the presence of relatively lossy material for the high-density capacitor <NUM> between the device's forward path <NUM> and the portion of the return current path <NUM> that is carried by the reverse current path structure <NUM>.

An implementation of shielded device <NUM> in accordance with the present invention is depicted by device <NUM> in <FIG> and <FIG>. <FIG> and <FIG> of device <NUM> are each cross-sectional views of device <NUM> taken through different portions of device <NUM>. Device <NUM> includes a conductive layer <NUM> (e.g., which may be coupled to a flange <NUM>) deposited on a surface of a semiconductor substrate <NUM> (e.g., a silicon or other semiconductor substrate), and a plurality of conductive and dielectric layers formed on or over the top surface of the semiconductor substrate <NUM>. A first conductive layer <NUM> at relative Z-height <NUM>, a second conductive layer <NUM> at Z-height <NUM> relative to conductive layer <NUM>, and a third conductive layer <NUM> at Z-height <NUM> relative to conductive layer <NUM>. Z-heights can vary greatly depending on the application, but example Z-heights, for certain implementations, may be, for example, <NUM> microns (µm) for Z-height <NUM>, <NUM> for Z-height <NUM>, and <NUM> for Z-height <NUM>. It is also noted that "disposed" is intended to identify relative position, and does not signify "placement" of the layer during a manufacturing process, or require direct contact between the layers disposed on top of each other (i.e., there could be additional layers or structures in between one layer disposed on another layer). In one or more embodiments, the conductive layers may be deposited and patterned to have different structures and shapes by etching. It is noted that device <NUM> includes other layers not illustrated in <FIG> and <FIG>, and that the representations in <FIG> and <FIG> are not to scale.

Device <NUM> includes first and second RF capacitors <NUM>, <NUM>, and high-density capacitor <NUM>. In certain embodiments, the high-density capacitor <NUM> may include terminals <NUM>, <NUM> (or electrodes) patterned into the first and third conductive layers <NUM>, <NUM>, and the terminals may be separated by a portion of a dielectric layer <NUM>, although capacitor <NUM> may be implemented in other ways (e.g., using other conductive layers). Capacitor <NUM> is a MIM (metal-insulator-metal) capacitor that is integrally formed as a portion of the device <NUM>. The capacitor <NUM> may be formed entirely above the semiconductor substrate <NUM>, or may have portions that extend into the semiconductor substrate <NUM> or are otherwise coupled to, or in contact with, semiconductor substrate <NUM>. According to the present invention, the capacitor <NUM> is formed from a first electrode <NUM>, a second electrode <NUM>, and a dielectric material <NUM> between the first and third electrodes. The dielectric material <NUM> of capacitor <NUM> may include one or more layers of polysilicon, various oxides, a nitride, or other suitable materials.

In various embodiments, the first and second electrodes <NUM>, <NUM> may include horizontal portions of conductive layers (e.g., portions that are parallel to portion <NUM>) and/or vertical portions (e.g., portions that are orthogonal to portion <NUM>) of conductive layers that are interconnected. Further, the first and second electrodes <NUM>, <NUM> may be formed from metal layers and/or from conductive semiconductor materials (e.g., polysilicon). Although particular two-plate capacitor structures are shown in <FIG>, a variety of other capacitor structures that do not form part of the present invention alternatively may be utilized, as would be understood by one of skill in the art based on the description herein.

The third metal layer <NUM> includes a first portion <NUM>, which may form a first terminal (or electrode) of RF capacitor <NUM>, and a second portion <NUM>, which may form a first terminal (or electrode) of RF capacitor <NUM>. In other embodiments, the first terminals of capacitors <NUM>, <NUM> may be formed from different conductive layers. A portion <NUM> of a conductive layer ( the third conductive layer <NUM>) is disposed over high-density capacitor <NUM> to elevate the return current path over the high-density capacitor <NUM>. Although the first, second, and third conductive features <NUM>, <NUM>, and <NUM> are depicted as being formed from portions of the third conductive layer <NUM>, and thus are depicted at the same height (i.e., height <NUM>), they are not continuous, but rather separate segments of the third conductive layer <NUM>. In other embodiments, conductive features <NUM>, <NUM>, but not <NUM> may be formed from portions of different conductive layers.

As best seen in the cross-section of <FIG>, one or more through-silicon vias (TSVs) <NUM>, <NUM>, extend from the bottom surface of IPD <NUM> (and thus from flange <NUM>) to the horizontal shielding portion <NUM> of the third conductive layer <NUM>. The reverse current Irev <NUM> is provided with a conductive current path <NUM> (see arrows <NUM> in <FIG>) over the high-density capacitor <NUM> via the TSVs <NUM>, <NUM> and shielding portion <NUM>. Referring also to <FIG>, TSVs <NUM> correspond to the first vertical portion <NUM>, a patterned portion of layer <NUM> corresponds to an elevated horizontal portion <NUM>, and the second vertical portion <NUM> corresponds to TSVs <NUM>.

<FIG> depicts a top view of a shielded IPD <NUM> according to the present invention that can be used to implement the approach represented in <FIG> and <FIG>. The shielded IPD <NUM> includes first RF capacitor <NUM> (e.g., capacitor <NUM>, <NUM>, <FIG>, <FIG>), a plurality of parallel-coupled second RF capacitors <NUM> (e.g., capacitor <NUM>, <NUM>, <FIG>, <FIG>), a resistor <NUM> (e.g., resistor <NUM>, <NUM>, <FIG>, <FIG>), parallel inductors <NUM> (e.g., inductor <NUM>, <NUM>, <FIG>, <FIG>), and a buried high-density capacitor (e.g., capacitor <NUM>, <NUM>, <FIG>, <FIG>), which is not visible in the top view of <FIG>. The various components are interconnected as previously described.

Near the center is shielding structure <NUM>, which is formed at least in part by the shielding portion <NUM> of third conductive layer <NUM>. It is noted that the horizontal portion of the shielding structure <NUM> needs not be limited to only the third conductive layer <NUM>, and may alternatively or additionally include portions of other layers, such as the second conductive layer <NUM>, or other conductive layers, examples that do not form part of the present invention but are useful for understanding it. Further, an embodiment not forming part of the present invention but useful for understanding it of a device may include more than three conductive layers, and the horizontal portion of the shielding structure <NUM> may be formed from various portions of those layers.

The high-density capacitor within the IPD <NUM> is not viewable from the top (in the top view of <FIG>) because it is positioned underneath the horizontal portion of shielding structure <NUM>. On opposing sides of the shielding structure <NUM> are RF capacitor <NUM> (corresponding with capacitor <NUM> in <FIG> or <NUM> in <FIG>), and RF capacitor <NUM> (corresponding with capacitor <NUM> in <FIG> or <NUM> in <FIG>). An inductive element <NUM> (corresponding with inductance <NUM> in <FIG> or <NUM> in <FIG>), and a resistor <NUM> (corresponding with resistor <NUM> in <FIG> or <NUM> in <FIG>), are also depicted in this top-view perspective. In actuality, some or all of these components may be buried under overlying layers.

The shielding structure <NUM> may include a plurality of slots (voids) <NUM> that may help to prevent die crack and decrease warpage. The slot size may be, for example, about <NUM>-<NUM> microns (µm) wide (e.g., <NUM>) by about <NUM>-<NUM> long (e.g., <NUM>) for IPD arrangements in example implementations. As a rule of thumb in certain implementations, to reduce or prevent coupling, the length and width dimensions of slot <NUM> may be, for example, no larger than about one tenth of the wavelength of the low end of operating frequency.

The wavelength of the low end of operating frequency may be represented by: <MAT> where v is the phase speed of the wave and f is the low end of operating frequency.

A plurality of conductive vias <NUM>, <NUM>, which are depicted as small rectangles in <FIG>, may make up the vertical portions of the shielding structure (e.g., vertical portions <NUM>, <NUM>, <FIG>, or TSVs <NUM>, <NUM>, <FIG>). As shown, the vertical portions of the shielding structure may include a row of aligned vias <NUM>, <NUM>, in some embodiments. For example, as shown in the enlarged portion of the device, each via may have a length <NUM> in a range of about <NUM> to about <NUM>, and a width <NUM> in a range of about <NUM> to about <NUM>. In other embodiments, the vias <NUM>, <NUM> may be circular, oval, or may have some other cross-sectional shape.

It is noted that although particular configurations of vias are shown in <FIG>, <FIG>, and <FIG>, the vias may be arranged in different manners, in other embodiments. Having multiple vias in parallel can reduce the impedance of the vias to enable the device to operate more efficiently. It is noted that some of the vias may be interconnected while others may be isolated. Also, vias may extend up to different layers (e.g., the second conductive layer <NUM> or the third conductive layer <NUM>, depicted in <FIG> and <FIG>). The number and configuration of vias may be driven at least in part by the internal circuitry in a package, and other interconnections and configurations may be utilized to suit different applications in other embodiments.

Low-frequency probe testing for baseband (without DC bias on the gate and drain) has shown that the LFR is over <NUM> using a high-density capacitor, as compared with LFRs of about <NUM> in designs without a baseband termination circuit. The shielding structure is not expected to deteriorate baseband performance. The embodiments discussed above are well-suited for many RF power products, including but not limited to those that require ISBWs greater than <NUM> with reduced power dissipation (that may result from electromagnetic coupling) and high RF efficiency. The disclosed approach helps enable multiband transistors in discrete, integrated circuit (IC), or module format. Products can be, for example, in air cavity or overmolded packages, and may be single-stage or multi-stage products. Example implementations can be directly incorporated into, for example, transistor products based on silicon (Si), gallium arsenide (GaAs), and/or gallium nitride (GaN).

The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. The subject-matter disclosed in the present application is only limited by the appended claims.

Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).

Claim 1:
An integrated passive device, IPD, (<NUM>, <NUM>, <NUM>) comprising:
a semiconductor substrate (<NUM>);
a first conductive layer (<NUM>) on a top surface of the semiconductor substrate, and a plurality of conductive and dielectric layers formed on or over the top surface of the semiconductor substrate (<NUM>) and including a second conductive layer (<NUM>), a third conductive layer (<NUM>) thereabove, and a fourth conductive layer (<NUM>) thereabove;
a metal-insulator-metal, MIM,
capacitor (<NUM>) coupled to the semiconductor substrate (<NUM>) integrally formed as a portion of the device and implemented using at least one of the second, third and fourth conductive layers, the MIM capacitor (<NUM>) including:
a first electrode (<NUM>),
a second electrode (<NUM>), and
a dielectric (<NUM>) between the first electrode (<NUM>) and the second electrode (<NUM>;
a first radio frequency, RF, capacitor (<NUM>, <NUM>) over the semiconductor substrate (<NUM>), and having at least one first terminal thereof (<NUM>) formed from a portion of a one of the conductive layers;
a second RF capacitor (<NUM>, <NUM>) over the semiconductor substrate (<NUM>), and having at least one second terminal thereof (<NUM>) formed from a portion of one of the conductive layers; and
a shielding structure (<NUM>) placed between the MIM capacitor and the first and second terminal of the RF capacitors and forming a continuous conductive path, comprising a first vertical portion including a first one or more vias (<NUM>) through the semiconductor substrate (<NUM>), an elevated horizontal metal shielding portion (<NUM>, <NUM>, <NUM>) located above the MIM capacitor, and a second vertical portion including a second one or more vias (<NUM>) through the semiconductor substrate (<NUM>), wherein the first and second one or more vias (<NUM>, <NUM>) extend from a bottom surface of the semiconductor substrate and are electrically coupled to the elevated horizontal metal shielding structure (<NUM>),
wherein the fourth conductive layer includes the elevated horizontal metal shielding portion.