Patent Description:
Light emitting diodes (LEDs) have been widely adopted in various illumination contexts, for backlighting of liquid crystal display (LCD) systems (e.g., as a substitute for cold cathode fluorescent lamps), and for sequentially illuminated LED displays. Applications utilizing LED arrays include automotive headlamps, roadway illumination, light fixtures, and various indoor, outdoor, and specialty contexts. Desirable characteristics of LED devices according to various end uses include high luminous efficacy, long lifetime, and wide color gamut.

Conventional color LCD display systems require color filters (e.g., red, green, and blue) that inherently reduce light utilization efficiency. Sequential illuminated LED displays, which utilize self-emitting LEDs and dispense with the need for backlights and color filters, provide enhanced light utilization efficiency.

Large format multi-color sequentially illuminated LED displays (including full color LED video screens) typically include numerous individual LED panels, packages, and/or components providing image resolution determined by the distance between adjacent pixels or "pixel pitch. " Sequentially illuminated LED displays may include "RGB" three-color displays with arrayed red, green and blue LEDs, or "RG" two-color displays with arrayed red and green LEDs. Other colors and combinations of colors may be used. Large format displays (e.g., electronic billboards and stadium displays) intended for viewing from great distances typically have relatively large pixel pitches and usually include discrete LED arrays with multi-color (e.g., red, green, and blue) LEDs that may be independently operated to form what appears to a viewer to be a full color pixel. Medium-sized displays with relatively shorter viewing distances require shorter pixel pitches (e.g., <NUM> or less), and may include panels with arrayed red, green, and blue LED components mounted on a single electronic device attached to a driver printed circuit board (PCB) that controls the LEDs.

Various LED array applications, including (but not limited to) automotive headlamps, high resolution displays suitable for short viewing distances, and other lighting devices, may benefit from smaller pixel pitches; however, practical considerations have limited their implementation. Conventional pick-and-place techniques useful for mounting LED components and packages to PCBs may be difficult to implement in a reliable manner in high-density arrays with small pixel pitches. Additionally, due to the omnidirectional character of LED and phosphor emissions, it may be difficult to prevent emissions of one LED (e.g., a first pixel) from significantly overlapping emissions of another LED (e.g., a second pixel) of an array, which would impair the effective resolution of an LED array device. It may also be difficult to avoid non-illuminated or "dark" zones between adjacent LEDs (e.g., pixels) to improve homogeneity, particularly while simultaneously reducing crosstalk or light spilling between emissions of the adjacent LEDs. Moreover, addition of various light segregation or light steering structures within a beam path of one or more LEDs may result in reduced light utilization efficiency. The art continues to seek improved LED array devices with small pixel pitches while overcoming limitations associated with conventional devices and production methods.

<CIT> discloses a method for fabricating a flip-chip light emitting diode device in which the thickness of a growth substrate is reduced.

<CIT> discloses processes of forming a plurality of known good die (KGD) light emitting diode (LED) components into larger size optically coherent LED chips or devices, wherein gaps and spaces in between the mounted KGD - LED components and a mounting substrate are filled with under-filling materials.

The present invention is defined by claim <NUM>. In certain embodiments, various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. Other technical benefits may additionally or alternatively be achieved. Certain enhancements may also promote efficient manufacturability. Exemplary enhancements providing one or more technical benefits described herein include, but are not limited to: providing underfill materials with improved surface coverage between adjacent pixels; providing underfill materials with improved surface coverage between pixels and submounts on which the pixels are mounted; providing wetting layers to improve wicking or flow of underfill materials within pixelated light emitting diodes (LEDs); providing underfill materials before or after individual pixels have been formed; and providing different pixels with protruding features or textured features.

In certain embodiments, the electrical contacts of each pixel may comprise an anode and a cathode, and the wetting layer is further arranged between the anode and the cathode of each pixel of the plurality of pixels. In certain embodiments, the wetting layer is compositionally different than the passivation layer. The wetting layer may comprise silicon dioxide (SiO<NUM>) and the passivation layer comprises silicon nitride (SiN). In accordance with the invention, the wetting layer comprises a contact angle with the underfill material of less than about <NUM> degrees. In certain embodiments, each of the plurality of pixels further comprises a substrate supporting the semiconductor layers, and wherein the wetting layer is arranged entirely between the underfill material and the substrate of each pixel. In other embodiments, each of the plurality of pixels further comprises a substrate supporting the semiconductor layers, and wherein the wetting layer is arranged partially between the underfill material and the substrate of each pixel.

Those skilled in the art will appreciate the scope of the present invention is defined by the appended claims.

<FIG> show examples not forming part of the invention as claimed, and are shown to illustrate certain aspects of the invention. <FIG> and <FIG> show processes resulting in embodiments of the invention.

Solid state light emitting devices disclosed herein include a plurality of active layer portions that form a plurality of pixels. In certain embodiments, various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel homogeneity, without unduly restricting light utilization efficiency. Efficient manufacturability of a lighting device may also be provided. Additional and/or alternative beneficial effects are contemplated. Exemplary enhancements to provide one or more technical benefits described herein include, but are not limited to: providing underfill materials with improved surface coverage between adjacent pixels; providing underfill materials with improved surface coverage between pixels and submounts on which the pixels are mounted; providing wetting layers to improve wicking or flow of the underfill material within pixelated-light emitting diodes (LEDs); providing underfill materials before or after individual pixels have been formed; and providing different pixels with protruding features or textured features.

Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the present invention and will recognize applications of these concepts not particularly addressed herein.

As used herein, a "pixelated-LED chip" refers to an inorganic light emitting device or precursor thereof, in which a body or film comprising at least one layer or region made of a semiconductor material and being configured into sub-regions or pixels to emit visible light, infrared and/or ultraviolet light when a current is applied. The pixelated-LED chip may include an active layer that is segregated into a plurality of active layer portions such that each pixel comprises a different active layer portion. The pixelated-LED chip may also include a substrate that supports the active layer. The substrate may be segregated, either partially or entirely through a thickness of the substrate, into a plurality of substrate portions that support a different active layer portion in each pixel. Depending on the embodiment, the pixelated-LED chip may include lumiphoric materials, including phosphors or other conversion materials, and other physical optical structures that are integral with the pixelated-LED chip.

As used herein, an "active layer" or an "active region" of a solid state light emitting device refers to the layer or region in which majority and minority electronic carriers (e.g., holes and electrons) recombine to produce light. In general, an active layer or region according to embodiments disclosed herein can include a double heterostructure or a well structure, such as a quantum well structure. An active layer or region can include multiple layers or regions, such as a multiple quantum well structure.

As used herein, a "wetting layer" refers to a layer of material intended to reduce surface tension and promote wicking of an underfill material when the underfill material an uncured, flowable state. In certain embodiments, the underfill material may comprise a silicone binder containing titanium dioxide particles.

Solid state light emitting devices disclosed herein may include at least one solid state light source (e.g., an LED or a pixelated-LED chip) and one or more lumiphoric materials (also referred to herein as lumiphors) arranged to receive emissions of the at least one solid state light source. A lumiphoric material may include one or more of a phosphor, a scintillator, a lumiphoric ink, a quantum dot material, a day glow tape, or the like. In certain embodiments, a lumiphoric material may be in the form of one or more phosphors and/or quantum dots arranged in a binder such as silicone or glass, arranged in the form of a single crystalline plate or layer, a polycrystalline plate or layer, and/or a sintered plate. In certain embodiments, a lumiphoric material such as a phosphor may be spin coated or sprayed on a surface of an LED array or a pixelated-LED chip. In certain embodiments, a lumiphoric material may be located on a growth substrate, on epitaxial layers, and/or on a carrier substrate of an LED array or a pixelated-LED chip. If desired, multiple pixels including one or more lumiphoric materials may be manufactured in a single plate. In general, a solid state light source may generate light having a first peak wavelength. At least one lumiphor receiving at least a portion of the light generated by the solid state light source may re-emit light having a second peak wavelength that is different from the first peak wavelength. A solid state light source and one or more lumiphoric materials may be selected such that their combined output results in light with one or more desired characteristics such as color, color point, intensity, etc. In certain embodiments, aggregate emissions of one or more flip chip LEDs or pixels of a pixelated-LED chip, optionally in combination with one or more lumiphoric materials, may be arranged to provide cool white, neutral white, or warm white light, such as within a color temperature range of from <NUM> to <NUM>,<NUM>. In certain embodiments, lumiphoric materials having cyan, green, amber, yellow, orange, and/or red peak wavelengths may be used. In certain embodiments, lumiphoric materials may be added to one or more emitting surfaces (e.g., a top surface and one or more edge surfaces) by methods such as spray coating, dipping, liquid dispensation, powder coating, inkjet printing, or the like. In certain embodiments, lumiphoric material may be dispersed in an encapsulant, adhesive, or other binding medium.

In certain embodiments, photolithographic patterning or other stencil-type patterning may be used to permit different lumiphoric materials to be applied on or over different pixels associated with a substrate to provide lumiphoric materials and/or scattering materials that differs in (a) composition, (b) concentration, (c) particle size, or (d) distribution with respect to different pixels.

In certain embodiments, a scattering material may be added over or incorporated into a lumiphoric material. The scattering material may include scattering particles arranged in a binder, such as silicone. The scattering particles affect total internal reflection (TIR) of light to promote scattering and mixing of light that interacts with the scattering material. The scattering particles may include fused silica, fumed silica, or particles of titanium dioxide (TiO<NUM>), among others. In some embodiments, the scattering material includes a layer of scattering particles suspended in a binder that is applied on the lumiphoric material. In other embodiments, the scattering particles may be included within the lumiphoric material such that the lumiphoric material comprises lumiphoric particles and scattering particles suspended in the same binder.

As used herein, a layer or region of a light emitting device may be considered to be "transparent" when at least <NUM>% of emitted radiation that impinges on the layer or region emerges through the layer or region. For example, in the context of LEDs configured to emit visible light, suitably pure crystalline substrate materials of silicon carbide (SiC) or sapphire may be considered transparent. Moreover, as used herein, a layer or region of an LED is considered to be "reflective" or embody a "reflector" when at least <NUM>% of the angle averaged emitted radiation that impinges on the layer or region is reflected. In some embodiments, an LED is considered to be "reflective" or embody a "reflector" when at least <NUM>% of the angle averaged emitted radiation that impinges on the layer or region is reflected. For example, in the context of gallium nitride (GaN)-based blue and/or green LEDs, silver (Ag) (for example, at least <NUM>% reflective, or at least <NUM>% reflective) may be considered a reflective or reflecting material. In the case of ultraviolet (UV) LEDs, appropriate materials may be selected to provide a desired, and in some embodiments high, reflectivity and/or a desired, and in some embodiments low, absorption. In certain embodiments, a "light-transmissive" material may be configured to transmit at least <NUM>% of emitted radiation of a desired wavelength.

Certain embodiments disclosed herein relate to the use of flip chip LED devices or flip chip pixelated-LED chips in which a light-transmissive substrate represents the exposed light emitting surface. In certain embodiments, the light-transmissive substrate embodies or includes an LED growth substrate, wherein multiple LEDs are grown on the same substrate that forms a light emitting surface or region. In certain embodiments, a pixelated-LED chip includes multiple active layer portions formed from an active layer grown on a growth substrate. In certain embodiments, the pixels may share functional layers of the pixelated-LED chip. In certain embodiments, one or more portions (or the entirety) of a growth substrate and/or portions of epitaxial layers may be thinned or removed. In certain embodiments, a second substrate (such as a carrier substrate or a temporary substrate to perform chip processing) may be added to the pixelated-LED chip or precursor thereof, whether or not a growth substrate has been partially or fully removed. In certain embodiments, a light-transmissive substrate includes SiC, sapphire, or glass. Multiple LEDs (e.g., flip chip LEDs or flip chip pixels) may be grown on a substrate and incorporated into a light emitting device. In certain embodiments, a substrate (e.g., silicon (Si)) may include vias arranged to make contact with LED chips mounted or grown thereon. In certain embodiments, as an alternative to using flip chips, individual LEDs or LED packages may be individually placed and mounted on or over a substrate to form an array. For example, multiple wafer level packaged LEDs may be used to form LED arrays or subarrays.

When LEDs embodying a flip chip configuration are used, desirable flip chip LEDs incorporate multi-layer reflectors and incorporate light-transmissive (preferably transparent) substrates that are optionally patterned along an internal surface adjacent to semiconductor layers. A flip chip LED, or a flip chip pixel in some embodiments, includes anode and cathode contacts that are spaced apart and extend along the same face, with such face opposing a face defined by the light-transmissive (preferably transparent) substrate. A flip chip LED may be termed a horizontal structure, as opposed to a vertical structure having contacts on opposing faces of an LED chip. The transparent substrate is textured to provide a varying surface which may increase the probability of refraction over internal reflection, so as to enhance light extraction. A substrate may be patterned or roughened by any of various methods known in the art, including (but not limited to) formation of nano-scale features by etching (e.g., photolithographic etching) using any suitable etchants, optionally in combination with one or more masks.

Patterning or texturing of a substrate may depend on the substrate material as well as implications on light extraction efficiency and/or pixel separation. If a SiC substrate bearing multiple LEDs (e.g., flip chip LEDs or flip chip pixels) is used, then the index of refraction of the SiC is well-matched to a GaN-based active region of an LED, so light emissions of the active region tend to enter the substrate easily. If a sapphire substrate bearing multiple LEDs (e.g., flip chip LEDs or flip chip pixels) is used, then it may be desirable to provide a patterned, roughened, or textured interface between the active region and the substrate to promote passage of LED emissions into the substrate. With respect to the light extraction surface of a substrate, the surface is textured to promote extraction of light from the substrate. In embodiments where a growth substrate is removed, a GaN epitaxial light emitting surface can be roughened, patterned and/or textured.

In certain embodiments, LEDs or pixels may be grown on a first substrate of a first material (e.g., Si, SiC, or sapphire), the first (growth) substrate may be partially removed (e.g., thinned) or fully removed, and the LEDs or pixels may be bonded to, mounted to, or otherwise supported by a second substrate of a second material (e.g., glass, sapphire, etc.) through which LED emissions are transmitted, wherein the second material is preferably more transmissive of LED emissions than the first material. Removal of the first (growth) substrate may be done by any appropriate method, such as by use of an internal parting region or parting layer that is weakened and/or separated by: application of energy (e.g., laser rastering, sonic waves, heat, etc.), fracturing, one or more heating and cooling cycles, chemical removal, and/or mechanical removal (e.g., including one or more grinding, lapping, and/or polishing steps), or by any appropriate combination of techniques. In certain embodiments, one or more substrates may be bonded or otherwise joined to a carrier. Bonding of one or more LEDs or pixels to a substrate, or bonding of substrates to a carrier, may be performed by any suitable methods. Any suitable wafer bonding technique known in the art may be used such as van der Waals bonds, hydrogen bonds, covalent bonds, and/or mechanical interlocking. In certain embodiments, direct bonding may be used. In certain embodiments, bonding may include one or more surface activation steps (e.g., plasma treatment, chemical treatment, and/or other treatment methods) followed by application of heat and/or pressure, optionally followed by one or more annealing steps. In certain embodiments, one or more adhesion promoting materials may additionally or alternatively be used.

In certain embodiments, an LED array includes multiple flip chip LEDs or flip chip pixels grown on a single first (or growth) substrate, with the first substrate removed from the LEDs, and a second substrate (or carrier) added to the LEDs, with the second substrate including one or more reflective layers, vias, and a phosphor layer (e.g., spin-coated phosphor layer). In certain embodiments, an LED array includes multiple flip chip LEDs or flip chip pixels grown on a single growth substrate, wherein grooves, recesses, or other features are defined in the growth substrate and/or a carrier, and are used to form light-affecting elements, optionally being filled with one or more materials such as to form a grid between individual LEDs or pixels.

In certain embodiments utilizing flip chip LEDs or flip chip pixels, a light-transmissive substrate, a plurality of semiconductor layers, a multi-layer reflector, and a passivation layer may be provided. The light-transmissive substrate is preferably transparent with a patterned surface including a plurality of recessed features and/or a plurality of raised features. The plurality of semiconductor layers is adjacent to the patterned surface, and includes a first semiconductor layer comprising doping of a first type and a second semiconductor layer comprising doping of a second type, wherein a light emitting active region is arranged between the first semiconductor layer and the second semiconductor layer. The multi-layer reflector is arranged proximate to the plurality of semiconductor layers and includes a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and the plurality of semiconductor layers. The passivation layer is arranged between the metal reflector layer and first and second electrical contacts, wherein the first electrical contact is arranged in conductive electrical communication with the first semiconductor layer, and the second electrical contact is arranged in conductive electrical communication with the second semiconductor layer. In certain embodiments, a first array of conductive microcontacts extends through the passivation layer and provides electrical communication between the first electrical contact and the first semiconductor layer, and a second array of conductive microcontacts extends through the passivation layer. In certain embodiments, a substrate useable for forming and supporting an array of flip chip LEDs or flip chip pixels may include sapphire; alternatively, the substrate may include Si, SiC, a Group III-nitride material (e.g., GaN), or any combination of the foregoing materials (e.g., Si on sapphire, etc.). Further details regarding fabrication of flip chip LEDs are disclosed in <CIT>.

<FIG> illustrates a single flip chip LED <NUM> including a light-transmissive substrate <NUM>, first and second electrical contacts <NUM>, <NUM>, and a functional stack <NUM> (incorporating at least one light emitting active region <NUM>) arranged therebetween. The flip chip LED <NUM> includes an internal light-transmissive surface <NUM> that is patterned (with multiple recessed and/or raised features <NUM>) proximate to multiple semiconductor layers <NUM>, <NUM> of the LED <NUM>, including a multi-layer reflector proximate to the semiconductor layers <NUM>, <NUM> according to one embodiment. The light-transmissive (preferably transparent) substrate <NUM> has an outer major surface <NUM>, side edges <NUM>, and the patterned surface <NUM>. The multiple semiconductor layers <NUM>, <NUM> sandwiching the light emitting active region <NUM> are adjacent to the patterned surface <NUM>, and may be deposited via vapor phase epitaxy or any other suitable deposition process. In one implementation, a first semiconductor layer <NUM> proximate to the substrate <NUM> embodies an n-doped material (e.g., n-GaN), and a second semiconductor layer <NUM> embodies a p-doped material (e.g., p-GaN). A central portion of the multiple semiconductor layers <NUM>, <NUM> including the active region <NUM> extends in a direction away from the substrate <NUM> to form a mesa <NUM> that is laterally bounded by at least one recess <NUM> containing a passivation material (e.g., silicon nitride (SiN) as part of a passivation layer <NUM>), and that is vertically bounded by surface extensions 21A of the first semiconductor layer <NUM>.

The multi-layer reflector is arranged proximate to (e.g., on) the second semiconductor layer <NUM>, with the multi-layer reflector consisting of a dielectric reflector layer <NUM> and a metal reflector layer <NUM>. The dielectric reflector layer <NUM> is arranged between the metal reflector layer <NUM> and the second semiconductor layer <NUM>. In certain implementations, the dielectric reflector layer <NUM> comprises silicon dioxide (SiO<NUM>), and the metal reflector layer <NUM> comprises Ag. Numerous conductive vias <NUM>-<NUM>, <NUM>-<NUM> are defined in the dielectric reflector layer <NUM> and are preferably arranged in contact between the second semiconductor layer <NUM> and the metal reflector layer <NUM>. In certain implementations, the conductive vias <NUM>-<NUM>, <NUM>-<NUM> comprise substantially the same material(s) as the metal reflector layer <NUM>. In certain implementations, at least one (preferably both) of the dielectric reflector layer <NUM> and the metal reflector layer <NUM> is arranged over substantially the entirety of a major surface of the mesa <NUM> terminated by the second semiconductor layer <NUM> (e.g., at least about <NUM>%, at least about <NUM>%, or at least about <NUM>% of the major (e.g., lower) surface of the mesa <NUM> of the second semiconductor layer <NUM>).

A barrier layer <NUM> (including first and second portions <NUM>-<NUM>, <NUM>-<NUM>) is preferably provided between the metal reflector layer <NUM> and the passivation layer <NUM>. In certain implementations, the barrier layer <NUM> comprises sputtered titanium (Ti)/platinum (Pt) followed by evaporated gold (Au), or comprises sputtered Ti/nickel (Ni) followed by evaporated Ti/Au. In certain implementations, the barrier layer <NUM> may function to prevent migration of metal from the metal reflector layer <NUM>. The passivation layer <NUM> is arranged between the barrier layer <NUM> and (i) the first externally accessible electrical contact (e.g., electrode, or cathode) <NUM> and (ii) the second externally accessible electrical contact (e.g., electrode, or anode) <NUM>, which are both arranged along a lower surface <NUM> of the flip chip LED <NUM> separated by a gap <NUM>. In certain implementations, the passivation layer <NUM> comprises SiN. The passivation layer <NUM> includes a metal-containing interlayer <NUM> arranged therein, wherein the interlayer <NUM> may include (or consist essentially of) aluminum (Al) or another suitable metal.

The LED <NUM> includes first and second arrays of microcontacts <NUM>, <NUM> extending through the passivation layer <NUM>, with the first array of microcontacts <NUM> providing conductive electrical communication between the first electrical contact <NUM> and the first (e.g., n-doped) semiconductor layer <NUM>, and with the second array of microcontacts <NUM> providing conductive electrical communication between the second electrical contact <NUM> and the second (e.g., p-doped) semiconductor layer <NUM>. The first array of microcontacts <NUM> extends from the first electrical contact <NUM> (e.g., n-contact) through the passivation layer <NUM>, through openings defined in the interlayer <NUM>, through openings <NUM> defined in the first portion <NUM>-<NUM> of the barrier layer <NUM>, through openings defined in a first portion <NUM>-<NUM> of the metal reflector layer <NUM>, through openings defined in a first portion <NUM>-<NUM> of the dielectric reflector layer <NUM>, through the second semiconductor layer <NUM>, and through the active region <NUM> to terminate in the first semiconductor layer <NUM>. Within the openings defined in the interlayer <NUM>, the first portion <NUM>-<NUM> of the barrier layer <NUM>, the first portion <NUM>-<NUM> of the metal reflector layer <NUM>, and the first portion <NUM>-<NUM> of the dielectric reflector layer <NUM>, dielectric material of the dielectric reflector layer <NUM> laterally encapsulates the first array of microcontacts <NUM> to prevent electrical contact between the first array of microcontacts <NUM> and the respective layers <NUM>, <NUM>, <NUM>, <NUM>. The conductive vias <NUM>-<NUM> defined in the first portion <NUM>-<NUM> of the dielectric reflector layer <NUM> contact the first portion <NUM>-<NUM> of the dielectric reflector layer <NUM> and the second semiconductor layer <NUM>, which may be beneficial to promote current spreading in the active region <NUM>. The second array of microcontacts <NUM> extends from the second electrical contact <NUM> through the passivation layer <NUM> and through the openings defined in the interlayer <NUM> to at least one of (i) the second portion <NUM>-<NUM> of the barrier layer <NUM>, and (ii) a second portion <NUM>-<NUM> of the metal reflector layer <NUM>, wherein electrical communication is established between the metal reflector layer <NUM> and the second semiconductor layer <NUM> through the conductive vias <NUM>-<NUM> defined in a second portion <NUM>-<NUM> of the dielectric reflector layer <NUM>. Although the second array of microcontacts <NUM> is preferred in certain implementations, in other implementations, a single second microcontact may be substituted for the second array of microcontacts <NUM>. Similarly, although it is preferred in certain implementations to define multiple vias <NUM>-<NUM> in the second portion <NUM>-<NUM> of the dielectric reflector layer <NUM>, in other implementations, a single via or other single conductive path may be substituted for the conductive vias <NUM>-<NUM>.

Following formation of the passivation layer <NUM>, one or more side portions <NUM> extending between the outer major surface <NUM> of the substrate <NUM> and the surface extensions 21A of the first semiconductor layer <NUM> are not covered with passivation material. Such side portions <NUM> embody a non-passivated side surface.

In operation of the flip chip LED <NUM>, current may flow from the first electrical contact (e.g., n-contact or cathode) <NUM>, the first array of microcontacts <NUM>, and the first (n-doped) semiconductor layer <NUM> into the active region <NUM> to generate light emissions. From the active region <NUM>, current flows through the second (p-doped) semiconductor layer <NUM>, the conductive vias <NUM>-<NUM>, the second metal reflector layer portion <NUM>-<NUM>, the second barrier layer portion <NUM>-<NUM>, and the second array of microcontacts <NUM> to reach the second electrical contact (e.g., p-contact or anode) <NUM>. Emissions generated by the active region <NUM> are initially propagated in all directions, with the reflector layers <NUM>, <NUM> serving to reflect emissions in a direction generally toward the substrate <NUM>. As emissions reach the patterned surface <NUM> arranged between the substrate <NUM> and the first semiconductor layer <NUM>, the recessed and/or raised features <NUM> arranged in or on the patterned surface <NUM> promote refraction rather than reflection at the patterned surface <NUM>, thereby increasing the opportunity for photons to pass from the first semiconductor layer <NUM> into the substrate <NUM> and thereafter exit the LED <NUM> through the outer major surface <NUM> and non-passivated side portions <NUM>. In certain implementations, one or more surfaces of the LED <NUM> may be covered with one or more lumiphoric materials (not shown), to cause at least a portion of emissions emanating from the LED <NUM> to be up-converted or down-converted in wavelength.

<FIG> are plan view photographs of a single flip chip LED <NUM> similar in structure and operation to the flip chip LED <NUM> of <FIG>. Referring to <FIG>, the flip chip LED <NUM> includes an outer major surface <NUM> arranged for extraction of LED emissions, and includes an active region having a length L and a width W. In certain embodiments, the active region includes a length L of about <NUM> microns (µm), and a width W of about <NUM>, and a substrate <NUM> extends beyond the active region. Referring to <FIG>, the flip chip LED <NUM> includes a cathode (e.g., first electrical contact) <NUM> and an anode (e.g., second electrical contact) <NUM> arranged along a lower surface <NUM>. In certain embodiments, the cathode <NUM> includes length and width dimensions of about <NUM> by <NUM>, and the anode <NUM> includes length and width dimensions of about <NUM> by <NUM>.

<FIG> are plan view photographs of a pixelated-LED chip including an array of four flip chip LEDs <NUM> formed on a single transparent substrate <NUM>, with each flip chip LED <NUM> being substantially similar in structure and operation to the flip chip LED <NUM> of <FIG>. Each flip chip LED <NUM> includes an active layer portion of an active layer. The active layer portion of each flip chip LED <NUM> is spaced apart from the active area of each adjacent flip chip LED <NUM> by a gap (e.g., <NUM> in a length direction and <NUM> in a width direction). A central portion of each gap embodies a street <NUM> (e.g., having a width of about <NUM>) consisting solely of the substrate <NUM>, whereas peripheral portions of each gap (between each street <NUM> and active areas of LEDs <NUM>) includes the substrate <NUM> as well as passivation material (e.g., the passivation layer <NUM> shown in <FIG>). Each street <NUM> thus represents a boundary between adjacent flip chip LEDs <NUM>. Each flip chip LED <NUM> includes a cathode <NUM> and an anode <NUM> arranged along a lower surface <NUM>, and each flip chip LED <NUM> is arranged to emit light through an outer major surface <NUM> of the substrate <NUM>. The exposed cathodes <NUM> and anodes <NUM> permit separate electrical connections to be made to each flip chip LED <NUM>, such that each flip chip LED <NUM> may be individually addressable and independently electrically accessed. Additionally, this allows groups or subgroups of the flip chip LEDs <NUM> to be accessed together, separately from other flip chip LEDs <NUM>. If it were desired to separate the flip chip LEDs <NUM> from one another, then a conventional method to do so would be to utilize a mechanical saw to cut through the streets <NUM> to yield individual flip chip LEDs <NUM>.

<FIG> and <FIG> are plan view photographs of a pixelated-LED chip including an array of one hundred flip chip LEDs <NUM> on a single transparent substrate <NUM>, with each flip chip LED <NUM> being substantially similar in structure and operation to the flip chip LED <NUM> illustrated in <FIG>. The flip chip LEDs <NUM> are separated from one another by gaps including streets <NUM>. Each flip chip LED <NUM> includes an outer major surface <NUM> arranged for extraction of LED emissions, and includes a cathode <NUM> and an anode <NUM> arranged along a lower surface <NUM>. The exposed cathodes <NUM> and anodes <NUM> permit separate electrical connections to be made to each flip chip LED <NUM>, such that each flip chip LED <NUM> may be individually addressable and independently electrically accessed.

In certain embodiments, each flip chip LED of an array of LEDs supported by a single substrate (e.g., a pixelated-LED chip) includes a greatest lateral dimension of no greater than about <NUM>, about <NUM>, or about <NUM>. In certain embodiments, each flip chip LED pixel of an array of LEDs supported by a single substrate includes inter-pixel spacing of no greater than about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>. Such dimensional ranges provide a desirably small pixel pitch.

In certain embodiments, a pixelated-LED chip includes LEDs serving as pixels each having a substantially square shape. In certain embodiments, a pixelated-LED chip includes LEDs serving as pixels each having a rectangular (but non-square) shape. In other embodiments, LEDs may be provided as pixels having hexagonal shapes, triangular shapes, round shapes, or other shapes.

In certain embodiments, a pixelated-LED chip may include LEDs provided in a two-dimensional array as pixels of about <NUM> long x <NUM> wide, each including an active region of about <NUM> long x <NUM> wide, thereby providing a ratio of emitting area to total area of <NUM><NUM>/<NUM><NUM> =. <NUM> (or <NUM>%). In certain embodiments, an array of at least <NUM> LEDs (as shown in <FIG>) may be provided in an area of no greater than <NUM> long x <NUM> wide, with spacing between LEDs (pixel pitch) of no greater than <NUM> in the length direction and no greater than <NUM> in the width direction. In certain embodiments, each LED may include an emissive area of <NUM> long x <NUM> wide (totaling an area of <NUM><NUM>). Considering a total top area of <NUM> long x <NUM> wide (totaling an area of <NUM><NUM>) for each LED, a ratio of emissive area to total area (i.e., including emissive area in combination with non-emissive area) along a major (e.g., top) surface is <NUM>%. In certain embodiments, a light emitting device as disclosed herein includes a ratio of emissive area to non-emissive (or dark) area along a major (e.g., top) surface of at least about <NUM>%, at least about <NUM>%, at least about <NUM>% (i.e., about <NUM>:<NUM> ratio of emitting area to non-emitting (dark) area), at least about <NUM>%, at least about <NUM>%, at least about <NUM>%, at least about <NUM>%, at least about <NUM>%, or at least about <NUM>%. In certain embodiments, one or more of the foregoing values may optionally constitute a range bounded by an upper value of no greater than <NUM>%, <NUM>%, <NUM>%, <NUM>%, or <NUM>%. In certain embodiments, an array of at least <NUM> LEDs may be provided.

Although <FIG>, <FIG>, <FIG>, and <FIG> show each LED <NUM> as including two n-contact vias (embodying vertically offset circles registered with the n-contact or cathode <NUM>), in certain embodiments, n-contacts and any associated n-contact vias may be shifted laterally and provided in a dark area outside the emitting area of each LED <NUM>.

As noted previously, the omnidirectional character of LED and phosphor emissions may render it difficult to prevent emissions of one LED (e.g., a first pixel) from significantly overlapping emissions of another LED (e.g., a second pixel) of an array of flip chip LEDs arranged on a single light-transmissive substrate. A single transparent substrate supporting multiple flip chip LEDs would permit light beams to travel in numerous directions, leading to light scattering and loss of pixel-like resolution of emissions transmitted through the substrate. Problems of light scattering and loss of pixel-like resolution would be further exacerbated by presence of one or more lumiphoric materials overlying the light extraction surface of a substrate, owing to the omnidirectional character of lumiphor emissions. Various embodiments disclosed herein address this issue by providing light segregation elements configured to reduce interaction between emissions of different LEDs and/or lumiphoric material regions, thereby reducing scattering and/or optical crosstalk and preserving pixel-like resolution of the resulting emissions. In this manner, light segregation elements as described herein may additionally provide strong contrast and/or sharpness between lit and unlit regions of LED arrays. In certain embodiments, exemplary light segregation elements may extend from a light injection surface into a substrate, may extend from a light extraction surface into a substrate, may extend outward from a light extraction surface, or any combination of the foregoing. In certain embodiments, multiple light segregation elements may be defined by different methods in the same substrate and/or light emitting device. In certain embodiments, light segregation elements of different sizes and/or shapes may be provided in the same substrate and/or light emitting device. For example, in certain embodiments, a first group of light segregation elements having a first size, shape, and/or fabrication technique may extend from a light injection surface into an interior of a substrate, and a second group of light segregation elements having a second size, shape, and/or fabrication technique may extend from the light injection surface into the interior of the substrate, wherein the second size, shape, and/or fabrication technique differs from the first size, shape, and/or fabrication technique. In certain embodiments, light segregation elements may include recesses (whether filled or unfilled) defined in a substrate supporting multiple LEDs, with such recesses embodying boundaries between pixels.

In certain embodiments, an underfill material is arranged between pixels of a pixelated-LED chip to form light segregation elements. In some embodiments, the underfill material comprises TiO<NUM> particles suspended in a silicone binder. In certain embodiments, a weight ratio of TiO<NUM> to silicone is in a range of <NUM>% to <NUM>%. In some embodiments, the weight ratio of TiO<NUM> to silicone is about <NUM>%, or about <NUM>:<NUM>. Additionally, a solvent may be added to alter the viscosity of the underfill material to improve flow and filling between pixels. The underfill material may comprise metallic particles suspended in an insulating binder. In certain embodiments, the underfill material comprises a dielectric material. In other embodiments, the underfill material comprises air. In certain embodiments, the underfill material comprises a material with a high durometer on a Shore hardness scale (e.g., a high durometer silicone material). A material with a high durometer value, or hardness, in the underfill material provides mechanical stability or anchoring of pixels of the pixelated-LED chip. For example, the underfill material may comprise a material, such as silicone, with a Shore D hardness scale durometer value of at least <NUM>. In further embodiments, the underfill material may comprise a material with a Shore D hardness scale durometer value in a range of from about <NUM> to about <NUM> or in a range from about <NUM> to about <NUM>.

<FIG> is an upper perspective view photograph of a portion of a pixelated-LED light emitting device <NUM> with an underfill material <NUM> according to some embodiments, showing a plurality of pixels A1, A2, B1, and B2. Alphanumeric column labels A and B appear at top between vertical dashed lines, and Arabic numerals <NUM> and <NUM> appear at left between horizontal dashed lines to provide column and row references for individual pixels. The vertical and horizontal dashed lines correspond to street-aligned cut lines or regions <NUM>-<NUM> to <NUM>-<NUM> that define lateral borders and inter-pixel spaces between the pixels A1, A2, B1, and B2. Dashed lines extending outward beyond the image represent extensions of boundaries between pixels. The vertical and horizontal solid lines correspond to cut lines or regions <NUM>-<NUM> to <NUM>-<NUM> that are not aligned with streets between pixels. In certain embodiments, the cut lines or regions <NUM>-<NUM> to <NUM>-<NUM> are provided to form a patterned surface to promote extraction of light from each pixel. The underfill material <NUM> is configured along the lateral borders of each pixel A1, A2, B1, B2 for improved contrast. The width of the street-aligned cut lines <NUM>-<NUM> to <NUM>-<NUM> forms at least a portion of the spacing between pixels. In certain embodiments, each pixel A1, A2, B1, B2 of the pixelated-LED light emitting device <NUM> is spaced from adjacent pixels by a distance no greater than about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or in a range of from about <NUM> to about <NUM>, or in a range of from about <NUM> to about <NUM>. Such dimensional ranges provide a desirably small pixel pitch. The spacing between pixels also relates to the width of the underfill material <NUM> that is configured between adjacent pixels. For example, in some embodiments, a <NUM> spacing between pixels allows more of the underfill material <NUM> (about <NUM> width) to be configured between adjacent pixels than a pixel spacing of <NUM>. Accordingly, more light may be reflected and redirected out of each pixel without leaking into an adjacent pixel by the underfill material <NUM> with <NUM> spacing compared to the underfill material <NUM> with <NUM> spacing, thereby providing improved contrast and pixel brightness. Notably, for a constant spacing between the street-aligned cut lines <NUM>-<NUM> to <NUM>-<NUM>, a pixel spacing of <NUM> reduces the area of each pixel; however, the increase in the underfill material <NUM> may still provide brighter pixels with improved contrast.

The cut lines <NUM>-<NUM> to <NUM>-<NUM> form a plurality of light extraction surface recesses <NUM> that intersect and segregate a plurality of protruding features <NUM>. For example, in the pixel A1, the vertical cut lines <NUM>-<NUM> and <NUM>-<NUM> and the horizontal cut lines <NUM>-<NUM> and <NUM>-<NUM> form two vertical and two horizontal light extraction surface recesses <NUM> that intersect and define nine protruding features <NUM>. The shape of a cutting tool as well as the number and direction of cut lines defines the shape of the protruding features <NUM>. In <FIG>, the cut lines <NUM>-<NUM> to <NUM>-<NUM> are evenly spaced vertical lines that intersect with evenly spaced and orthogonal horizontal cut lines <NUM>-<NUM> to <NUM>-<NUM>, and are formed with a beveled cutting tool. Accordingly, the protruding features <NUM> comprise square-base pyramidal shapes. In some embodiments, the pyramidal shapes comprise truncated pyramidal shapes, wherein such truncation may be vertical, lateral, or both vertical and lateral in character. Other shapes are possible, including triangle-shaped features, extruded triangle-shaped features and cuboid-shaped features. In other embodiments, the cut lines <NUM>-<NUM> to <NUM>-<NUM> may comprise intersecting diagonal lines to form other shapes, such as diamond-shaped features or other polyhedral features.

In certain embodiments, inter-pixel spaces are provided between adjacent pixels in a pixelated-LED chip. Inter-pixel spaces are formed when individual pixels are defined within a pixelated-LED chip and may include spaces between various elements of adjacent pixels, including active layer portions, substrate portions, and electrical contacts, among others. In certain embodiments, an underfill material is arranged in the inter-pixel spaces to cover all lateral surfaces between adjacent pixels. Additionally, the underfill material may substantially fill entire inter-pixel spaces between adjacent pixels. In certain embodiments, the electrical contacts for each pixel include an anode and a cathode and the underfill material is additionally arranged between the anode and cathode of each pixel.

<FIG> are schematic cross-sectional views of various states of fabrication of a pixelated-LED chip that includes an underfill material arranged in inter-pixel spaces between adjacent pixels. In <FIG>, an LED structure <NUM> including an active layer <NUM> has been deposited on a substrate <NUM>. The LED structure <NUM> may include a plurality of epitaxial layers deposited by metal organic chemical vapor deposition (MOCVD). In addition to the active layer <NUM>, the LED structure <NUM> may further include one or more n-type semiconductor layers and one or more p-type semiconductor layers. In some embodiments, the LED structure <NUM> includes Group III-V nitrides including but not limited to GaN, aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), and indium gallium nitride (InGaN). An exemplary n-type dopant is Si and an exemplary p-type dopant is magnesium (Mg). The active layer <NUM> may be configured between at least one n-type layer and one p-type layer. The active layer <NUM> may include a single quantum well (SQW) structure that includes a layer of InGaN or a multiple quantum well (MQW) structure such as a plurality of layers that include alternating layers of InGaN and GaN. Other semiconductor materials are possible, including gallium arsenide (GaAs), gallium phosphide (GaP), and alloys thereof. The substrate <NUM> may include a light-transmissive material such as SiC or sapphire, although other substrate materials are possible.

In <FIG>, a plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> have been formed from the LED structure <NUM>. A plurality of recesses or streets <NUM> are configured to segregate the active layer portions <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. The plurality of recesses <NUM> may be formed by selectively etching portions of the LED structure <NUM>. In some embodiments, the plurality of recesses <NUM> extends entirely through the active layer <NUM> and less than an entire thickness of an n-type layer that is between the active layer <NUM> and the substrate <NUM>. In certain embodiments, an etching step is applied to the LED structure <NUM> to form the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM>. In <FIG>, electrical contacts that include an anode <NUM> and a cathode <NUM> are deposited over each of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> to form a plurality of anode-cathode pairs <NUM>, <NUM>.

In <FIG>, the substrate <NUM> is flip-chip mounted over a mounting surface <NUM>. In some embodiments, the mounting surface <NUM> is a surface of a submount <NUM> that includes a plurality of electrode pairs <NUM>, <NUM>. The submount <NUM> may comprise an active interface element such as an ASIC chip, a passive interface element that serves as an intermediate element that may be later-attached to an active interface element, or a temporary interface element that provides temporary support for subsequent manufacturing steps. For embodiments where the submount <NUM> comprises a temporary interface element, the plurality of electrode pairs <NUM>, <NUM> may be omitted. The flip-chip mounting comprises establishing electrically conductive paths between the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM>. In some embodiments, the plurality of anode-cathode pairs <NUM>, <NUM> are planarized before flip-chip mounting to correct any variations in thicknesses from the anode-cathode deposition. Such planarization helps ensure that reliable electrical contacts may be made across the electrode pairs <NUM>, <NUM> distributed across the entire interface between the submount <NUM> and the substrate <NUM>, and avoids variation in interfacial height that would otherwise promote cracking of the substrate <NUM> when the substrate <NUM> is mechanically processed (e.g., thinned and shaped) in subsequent steps. The submount <NUM> may include a plurality of separate electrical paths, including one electrical path for each electrode pair of the plurality of electrode pairs <NUM>, <NUM>. In this regard, each of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> may be independently electrically accessible. Additionally, this allows a group or subgroup of the active layer portions (e.g., <NUM>-<NUM> and <NUM>-<NUM>) to be accessed together, independently of other active layer portions (e.g., <NUM>-<NUM>). Any suitable material and/or technique (e.g., solder attachment, preform attachment, flux or no-flux eutectic attachment, silicone epoxy attachment, metal epoxy attachment, thermal compression attachment, bump bonding, and/or combinations thereof) can electrically connect the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM>. In some embodiments, residue from the mounting step may be left in undesired areas between the substrate <NUM> and the submount <NUM> (such as in the recesses or streets <NUM>), and a cleaning step (such as an ultrasonic clean), may be used to remove the residue.

In <FIG>, the substrate <NUM> may be subjected to one or more thinning processes such as etching, grinding, lapping, mechanical polishing, chemical polishing, chemical-mechanical polishing, and the like. In some embodiments, the substrate <NUM> may initially comprise a thickness of greater than <NUM>. After mounting the substrate <NUM> to the submount <NUM>, the substrate <NUM> may be thinned to a thickness of no more than <NUM>. In some embodiments, the substrate <NUM> may be thinned to about <NUM> by one or more thinning steps. In certain embodiments, multiple thinning steps may be performed in increments of <NUM>-<NUM> per thinning step.

As illustrated in <FIG>, the substrate (<NUM> of <FIG>) is separated along various cut lines or regions <NUM>. In certain embodiments, the separation is performed with a rotary saw along the various cut lines or regions <NUM> at a high rotation speed but a slow linear travel speed to prevent cracking of crystalline substrate material. The cut lines or regions <NUM> are aligned with the plurality of recesses or streets <NUM> that segregate the active layer portions <NUM>-<NUM> to <NUM>-<NUM>, thereby providing a "street-aligned" configuration. Notably, the cut lines or regions <NUM> intersect with the plurality of recesses or streets <NUM>, such that portions of the substrate <NUM> that are registered with the plurality of recesses or streets <NUM> are removed through an entire thickness of the substrate <NUM>. The substrate <NUM> is thereby segregated into a plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM> that are registered with corresponding active layer portions <NUM>-<NUM> to <NUM>-<NUM> to form a pixelated-LED chip <NUM> comprising a plurality of pixels 104a, 104b, and 104c. As illustrated, inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> are provided or formed between adjacent ones of the plurality of pixels 104a, 104b, and 104c. For example, the inter-pixel space <NUM>-<NUM> is provided between the pixels 104a and 104b. In this regard, the inter-pixel space <NUM>-<NUM> is formed between lateral surfaces of adjacent substrate portions <NUM>-<NUM>, <NUM>-<NUM>, between lateral surfaces of adjacent active layer portions <NUM>-<NUM>, <NUM>-<NUM>, between lateral surfaces of the cathode <NUM> of the pixel 104a and the anode <NUM> of the pixel 104b, and between lateral surfaces of the electrode <NUM> that is registered with the pixel 104a and the electrode <NUM> that is registered with the pixel 104b.

In <FIG>, an underfill material <NUM> has been applied between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> of the pixelated-LED chip <NUM>. The underfill material <NUM> fills the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> as well as filling open spaces between the plurality of anode-cathode pairs <NUM>, <NUM> that are bonded to the plurality of electrode pairs <NUM>, <NUM>. In this manner, the underfill material <NUM> may be arranged to cover various lateral surfaces between the pixels 104a to 104c, including lateral surfaces of adjacent substrate portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces of adjacent active layer portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces between the anode-cathode pairs <NUM>, <NUM> of adjacent pixels 104a to 104c, and lateral surfaces between the electrode pairs <NUM>, <NUM> that are registered with the adjacent pixels 104a to 104c. In certain embodiments, the underfill material <NUM> is arranged in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> to cover all lateral surfaces between the adjacent pixels 104a to 104c. In certain embodiments, the substrate portions <NUM>-<NUM> to <NUM>-<NUM> are spaced from each other by a distance no greater than about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or about <NUM>, or in a range of from about <NUM> to about <NUM>, or in a range of from about <NUM> to about <NUM>. Accordingly, a width of the underfill material <NUM> between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> would have the same dimensions. By segregating the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM> before application of the underfill material <NUM>, the underfill material <NUM> may be directly applied or dispensed to the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> from the top of the pixelated-LED chip <NUM> as indicated by arrows <NUM> in <FIG>. In this manner, the underfill material <NUM> may more evenly cover the various lateral surfaces in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. Additionally, the underfill material <NUM> will have less distance to flow to reach and fill the areas between the anode-cathode pairs <NUM>, <NUM> and the electrode pairs <NUM>, <NUM> of each pixel 104a - 104c. In further embodiments, the underfill material <NUM> may additionally be applied to the sides or lateral edges of the pixelated-LED chip <NUM> between the pixels 104a to 104c and the submount <NUM> as indicated by the arrows <NUM>'. In certain embodiments, residue from thinning and sawing processes may be left in undesired areas between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> and in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. Before applying the underfill material <NUM>, a cleaning step (such as an ultrasonic clean), may be used to remove the residue. In certain embodiments, the underfill material <NUM> may be applied under a vacuum to assist filling of certain areas, such as the areas between the anode-cathode pairs <NUM>, <NUM> and the electrode pairs <NUM>, <NUM> of each pixel 104a to 104c.

In certain embodiments, the underfill material <NUM> comprises an insulating material. The underfill material <NUM> may comprise a light-altering material, such as light-altering particles suspended in an insulating binder or a matrix. The light-altering material may include a material or particles that are configured to reflect, refract, or otherwise redirect light, or even absorb light generated from the active layer portions <NUM>-<NUM> to <NUM>-<NUM>. In certain embodiments, the light-altering material may include combinations of different light-altering materials, such as light reflective or refractive particles suspended in the same binder as light-absorbing particles. The underfill material <NUM> may comprise TiO<NUM> particles suspended in a silicone binder. In certain embodiments, a weight ratio of TiO<NUM> to silicone is in a range of <NUM>% to <NUM>%. In certain embodiments, the weight ratio of TiO<NUM> to silicone is about <NUM>%, or about <NUM>:<NUM>. Additionally, a solvent may be added to alter a viscosity of the underfill material <NUM> to promote improved flow when filling the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> and the open spaces between the plurality of anode-cathode pairs <NUM>, <NUM>. In other embodiments, the underfill material <NUM> may comprise metallic particles suspended in an insulating binder. In some embodiments, the underfill material <NUM> comprises a dielectric material. In other embodiments, the underfill material <NUM> comprises air. In this manner, the underfill material <NUM> is arranged in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> to form light segregation elements, or pixel segregation elements, between each of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. Accordingly, light emissions of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> may be segregated from each other, thereby having improved contrast.

In certain embodiments, the underfill material <NUM> may be configured with a reduced coefficient of thermal expansion (CTE). The submount <NUM> may comprise a material, such as Si, that has a low CTE. For example, some Si submounts may be configured with single digit CTE values in parts per million per degrees Celsius (ppm/°C). If the underfill material <NUM> is configured with a CTE that has too large of a mismatch with the CTE of the submount <NUM>, then the underfill material may detach from the submount <NUM> during subsequent curing steps. In certain embodiments, the underfill material <NUM> is configured with a CTE in a range from about <NUM> ppm/°C to about <NUM> ppm/°C. In further embodiments, the underfill material <NUM> is configured with a CTE in a range from about <NUM> ppm/°C to about <NUM> ppm/°C, or in a range from about <NUM> ppm/°C to about <NUM> ppm/°C. Additionally, the underfill material <NUM> may comprise additional particles as previously described, such as TiO<NUM>, which can significantly lower the CTE even further. In certain embodiments, a methyl group may be added to the underfill material <NUM> that may improve the ability of the underfill material <NUM> to withstand high light flux with reduced degradation, and serve to increase blocking of contaminates that may otherwise reach the active layer portions <NUM>-<NUM> to <NUM>-<NUM>. In certain embodiments, the underfill material <NUM> comprises an index of refraction that is either closely matched or substantially matched with at least one of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> or the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In this manner, light from the active layer portions <NUM>-<NUM> to <NUM>-<NUM> that impinges the underfill <NUM> may more easily pass from the active layer portions <NUM>-<NUM> to <NUM>-<NUM> or the substrate portions <NUM>-<NUM> to <NUM>-<NUM> into the underfill material <NUM> before being redirected out of the pixelated LED chip <NUM>.

In certain embodiments, the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM> are formed before the underfill material <NUM> is applied to the pixelated-LED chip <NUM>. Accordingly, the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> provide direct access between the pixels 104a to 104c. The underfill material <NUM> may be applied directly to the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>, rather than relying on a wicking action to spread the underfill material <NUM> from lateral edges of the pixelated-LED chip <NUM>. The underfill material <NUM> may still wick around and between the anode-cathode pairs <NUM>, <NUM> and the electrode pairs <NUM>, <NUM>. In addition to improving the contrast between the active layer portions <NUM>-<NUM> to <NUM>-<NUM>, the underfill material <NUM> may additionally protect the integrity of the electrical connections between the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM>. The underfill material <NUM> may further strengthen a mechanical interface between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> and between the adjacent pixels 104a to 104c during subsequent processing steps. In certain embodiments, the underfill material <NUM> comprises a material with a high durometer on a Shore hardness scale (e.g., a high durometer silicone material). A material with a high durometer, or hardness, in the underfill material <NUM> provides mechanical stability or anchoring to help prevent the plurality of anode-cathode pairs <NUM>, <NUM> from detaching from the plurality of electrode pairs <NUM>, <NUM> in subsequent processing steps or during operation. For example, the underfill material <NUM> may comprise a material, such as silicone, with a Shore D hardness scale durometer value of at least <NUM>. In further embodiments, the underfill material <NUM> may comprise a material with a Shore D hardness scale durometer value in a range of from about <NUM> to about <NUM> or in a range from about <NUM> to about <NUM>.

In <FIG>, the pixelated-LED chip <NUM> includes at least one lumiphoric material <NUM> (also referred to herein as a lumiphor). In particular, the lumiphoric material <NUM> is arranged on a light extraction surface <NUM> of each of the plurality of pixels 104a to 104c. As previously described, the lumiphoric material <NUM> may include one or more of a phosphor, a scintillator, a lumiphoric ink, a quantum dot material, a day glow tape, or the like. In certain embodiments, the lumiphoric material <NUM> may be in the form of one or more phosphors and/or quantum dots arranged in a binder such as silicone or glass, arranged in the form of a single crystalline plate or layer, a polycrystalline plate or layer, and/or a sintered plate. In certain embodiments, the lumiphoric material <NUM> may be spin coated or sprayed on a surface of the plurality of pixels 104a to 104c. In certain embodiments, the lumiphoric material <NUM> may be located on each of the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In some embodiments, the lumiphoric material <NUM> is continuous on the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In some embodiments, the lumiphoric material <NUM> is over-applied, and a removal process such as grinding is used to tune each pixel 104a to 104c to desired color points. In general, the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> may generate light having a first peak wavelength. At least one lumiphor receiving at least a portion of the light generated by the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> may re-emit light having a second peak wavelength that is different from the first peak wavelength. A solid state light source and one or more lumiphoric materials may be selected such that their combined output results in light with one or more desired characteristics such as color, color point, intensity, etc. In certain embodiments, aggregate emissions may be arranged to provide cool white, neutral white, or warm white light, such as within a color temperature range of from <NUM> to <NUM>,<NUM>. In certain embodiments, a lumiphoric material comprises one or more materials including cyan, green, amber, yellow, orange, and/or red peak emission wavelengths. In certain embodiments, a scattering material may be included in the lumiphoric material <NUM>. By way of example, the lumiphoric material <NUM> may include phosphor particles and scattering particles such as fused silica, fumed silica, or TiO<NUM> particles in the same silicone binder. In other embodiments, the scattering material may comprise a layer of fused silica, fumed silica, or TiO<NUM> particles in a silicone binder deposited sequentially on the lumiphoric material <NUM>.

The lumiphoric material <NUM> may comprise a material with a lower durometer value on a Shore hardness scale than the underfill material <NUM>. In some embodiments, the lumiphoric material <NUM> and the underfill material <NUM> comprise silicone, and the silicone of the lumiphoric material <NUM> has a lower durometer value on a Shore hardness scale than the silicone of the underfill material <NUM>. As previously described, the underfill material <NUM> may comprise a silicone with a Shore D hardness durometer value of at least <NUM>. In further embodiments, the underfill material <NUM> may comprise silicone with a Shore D hardness durometer value in a range from about <NUM> to about <NUM> or in a range from about <NUM> to about <NUM>. In that regard, the lumiphoric material <NUM> comprises silicone with a Shore D hardness durometer value of less than <NUM> in some embodiments. In some embodiments, the underfill material <NUM> between each pixel of the plurality of pixels 104a to 104c may be omitted. Accordingly, an open space or an unfilled void of air may be provided between each pixel of the plurality of pixels 104a to 104c to form a light segregation element, or a pixel segregation element.

In <FIG>, the underfill material <NUM> has been applied to fill areas between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> of the pixelated-LED chip <NUM> in a manner similar to <FIG>. In this manner, the underfill material <NUM> may be arranged to cover various lateral surfaces between the pixels (104a to 104c of <FIG>). In certain embodiments, the underfill material <NUM> is arranged to only partially cover the lateral surfaces of the substrate portions <NUM>-<NUM> to <NUM>-<NUM> in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. In other embodiments, the underfill material <NUM> is arranged to cover the lateral surfaces of the active layer portions <NUM>-<NUM> to <NUM>-<NUM>, but not the lateral surfaces of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>, as indicated by the alternate underfill material level <NUM>' in <FIG>.

In some embodiments, the submount <NUM> of <FIG> may comprise a temporary carrier. Accordingly, the plurality of pixels 104a to 104c, the underfill material <NUM>, and the lumiphoric material <NUM> may be separated or removed from the submount <NUM>.

The pixelated-LED chip may includes a plurality of discontinuous substrate portions that form light extraction surfaces of the pixelated-LED chip. Depending on the substrate material, the light extraction surfaces include a textured surface to promote extraction of light. In certain embodiments related to manufacturing a pixelated-LED chip, it may be desirable to thin the substrate before mounting the substrate on a submount. In this manner, subsequent sawing steps have less substrate material to cut through to form the discontinuous substrate portions. After mounting a thinned substrate, a sawing step may also be used to form protruding features and light extraction surface recesses on the light extraction surfaces. The thinned substrate is micro-textured. In other embodiments, the thinned substrate may be micro-textured with a chemical or mechanical process prior to mounting on a submount.

<FIG> are schematic cross-sectional views of various states of fabrication of a pixelated-LED chip that includes substrate portions with protruding features and light extraction surface recesses as well as an underfill material arranged in inter-pixel spaces. In <FIG>, the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> are segregated on the substrate <NUM> by the recesses or streets <NUM>, and the anode-cathode pairs <NUM>, <NUM> are provided on the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> as previously described. As illustrated, the substrate <NUM> is thinned before subsequent processing steps. In <FIG>, the substrate <NUM> that has been pre-thinned is then flip-chip mounted over the mounting surfaced <NUM> of the submount <NUM>. In certain embodiments, the flip-chip mounting comprises establishing electrically conductive paths between the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM> as previously described.

In <FIG>, the substrate (<NUM> of <FIG>) is separated along various cut lines or regions <NUM> to form the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM>, the pixels 104a to 104c, and the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> of a pixelated-LED chip <NUM>. Each of the substrate portions <NUM>-<NUM> to <NUM>-<NUM> includes a light injection surface <NUM> adjacent corresponding active layer portions <NUM>-<NUM> to <NUM>-<NUM> and the light extraction surface <NUM> that generally opposes the light injection surface <NUM>. The light injection surface <NUM> is arranged between the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and the light extraction surface <NUM> of each pixel 104a to 104c. Additional cut lines or regions <NUM> form a plurality of light extraction surface recesses <NUM> that intersect and serve to define and segregate a plurality of protruding features <NUM> for each pixel 104a to 104c. More particularly, bevel cutting may be performed to yield a plurality of inclined lateral faces defined between the light extraction recesses <NUM> and the protruding features <NUM>. In certain embodiments, each inclined lateral face comprises an angle of inclination from vertical in a range of from about <NUM> degrees to about <NUM> degrees, or in a subrange of from about <NUM> degrees to about <NUM> degrees, or in a subrange of from about <NUM> degrees to about <NUM> degrees, or in an amount of about <NUM> degrees. When an angle of inclination from vertical of about <NUM> degrees is used, and opposing faces of the protruding features <NUM> are formed by two bevel cuts of the same magnitude, the protruding feature <NUM> may include an angle of about <NUM> degrees between the opposing faces. With further reference to <FIG>, a lower boundary of each light extraction surface recess <NUM> may be radiused, reflecting the fact that a rotary saw blade useable to form each light extraction surface recess <NUM> has a non-zero thickness. In certain embodiments, the cut lines or regions <NUM> are formed first, followed by the cut lines or regions <NUM>. In other embodiments, the order may be reversed such that the cut lines or regions <NUM> are formed before the cut lines or regions <NUM>. In still further embodiments, the cut lines or regions <NUM> and <NUM> are formed sequentially across the pixelated-LED chip <NUM>.

In <FIG>, the underfill material <NUM> as previously described has been applied between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> of the pixelated-LED chip <NUM>. The underfill material <NUM> fills the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> as well as filling open spaces between the plurality of anode-cathode pairs <NUM>, <NUM> that are bonded to the plurality of electrode pairs <NUM>, <NUM>. In this manner, the underfill material <NUM> may be arranged to cover various lateral surfaces between the pixels 104a to 104c, including lateral surfaces of the adjacent substrate portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces of the adjacent active layer portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces between the anode-cathode pairs <NUM>, <NUM> of the adjacent pixels 104a to 104c, and lateral surfaces between the electrode pairs <NUM>,<NUM> that are registered with the adjacent pixels 104a to 104c. In certain embodiments, the underfill material <NUM> is arranged in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> to cover all lateral surfaces between the adjacent pixels 104a to 104c. In certain embodiments, a lumiphoric material may be applied as previously described. Additionally, the lumiphoric material could be formed with a shape that conforms to surfaces of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>, including the light extraction surface recesses (<NUM> in <FIG>) and the protruding features (<NUM> in <FIG>). The lumiphoric material may be conformally applied to the substrate portions <NUM>-<NUM> to <NUM>-<NUM> by conformal deposition or a molding process, or the lumiphoric material may be subjected to a removal process to form the desired shape.

<FIG> are schematic cross-sectional views of various states of fabrication of a pixelated-LED chip that includes substrate portions with textured surfaces as well as an underfill material arranged in inter-pixel spaces. In <FIG>, the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> are segregated on the substrate <NUM> by the recesses or streets <NUM>, and the anode-cathode pairs <NUM>, <NUM> are provided on the plurality of active layer portions <NUM>-<NUM> to <NUM>-<NUM> as previously described. As illustrated, the substrate <NUM> is thinned before subsequent processing steps. In <FIG>, the substrate <NUM> has been subject to a texturing or micro-texturing process to form a textured surface <NUM>. In certain embodiments, the textured surface <NUM> may be formed by one or more etching steps, such as reactive ion etching and may include randomly textured features, patterned features, or combinations of randomly textured features and patterned features. The textured surface <NUM> may be formed by first polishing the substrate <NUM> with a diamond slurry, followed by reactive ion etching, or by reactive ion etching over a patterned photoresist material to form various patterns on the textured surface, or by reactive ion etching over a material that has undergone Ostwald ripening.

In certain embodiments, the textured surface <NUM> may comprise a plurality of microscale textural features. In certain embodiments, each microscale textural feature may have a maximum dimension (e.g., length, width, or height) of up to about <NUM>, or up to about <NUM>, or up to about <NUM>, or up to about <NUM>, or up to about <NUM>, or up to about <NUM>. In certain embodiments, microscale textural features may be defined by a subtractive material removal process, such as dry etching and/or wet etching. Examples of dry etching processes that might be used in certain embodiments include inductively coupled plasma etching and reactive ion etching.

In certain embodiments, microscale textural features may be randomly distributed (e.g., with large variation in spacing, optionally in combination with large variation in size, shape, and/or texture). In certain embodiments, microscale textural features may be regularly spaced and/or regularly sized. Such features may be formed through use of at least one mask with regularly spaced openings or pores, which may be defined by photolithographic patterning or other conventional mask formation methods.

In certain embodiments, a substrate (e.g., SiC) may be blanket coated with a thin coating (e.g., <NUM>-<NUM> Angstroms) of Al. A consumable water soluble template pre-coated with resist may be bonded to a coated wafer surface with low temperature and pressure. The template may be removed with warm water, leaving resist dots. The Al layer may be patterned with a short chlorine etch followed by a short (e.g., <NUM>-<NUM> second) inductively coupled plasma (ICP) etch to transfer the pattern into the SiC. A tetramethyl ammonium hydroxide (TMAH) wet etch may be used to remove any residual Al.

In certain embodiments, a pixelated LED chip may include combinations of microscale textural features illustrated in <FIG> and the protruding features as described for <FIG>.

In <FIG>, the substrate <NUM> that has been pre-thinned and includes the textured surface <NUM> has been flip-chip mounted over the mounting surfaced <NUM> of the submount <NUM> as previously described. In <FIG>, the substrate (<NUM> of <FIG>) is separated to form the plurality of discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM>, the pixels 104a to 104c, and the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> of a pixelated-LED chip <NUM>. In <FIG>, the underfill material <NUM> as previously described has been applied between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> as well as in the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> of the pixelated-LED chip <NUM>. In certain embodiments, a lumiphoric material may be applied as previously described.

In accordance with the invention, LED chips are configured with surfaces to promote improved wetting or wicking of underfill material. For pixelated-LED chips, this allows the underfill material to more easily cover all lateral surfaces of inter-pixel spaces. In certain embodiments, LED chips or individual pixels of a pixelated-LED chip include coatings or layers that are configured to comprise a contact angle with the underfill material that promotes improved wetting or wicking. In this regard, a pixelated-LED chip may include: an active layer comprising a plurality of active layer portions that form a plurality of pixels, wherein each pixel of the plurality of pixels includes electrical contacts, and inter-pixel spaces are provided between adjacent pixels of the plurality of pixels; an underfill material arranged in the inter-pixel spaces between adjacent pixels; and, in accordance with the invention, a wetting layer between the underfill material and the plurality of active layer portions, wherein the wetting layer comprises a contact angle with the underfill material of less than about <NUM> degrees.

<FIG> is a comparison plot illustrating contact angles between various wetting layer materials and an underfill material as previously described. In particular, a droplet of common underfill material that includes TiO<NUM> suspended in a silicone binder was placed on a variety of surface materials and the contact angle or wetting angle of each droplet was measured. The surface materials included aluminum oxide (Al<NUM>O<NUM>), GaN, a first SiO<NUM> material, a second SiO<NUM> material, SiC, SiN, Ti, and titanium oxynitride (TiON). The contact angles are measured in degrees from the surface material and, accordingly, lower contact angles indicate better wetting of the underfill material than higher contact angles. Notably, SiN, which is typically used as a passivation layer (e.g., <NUM> of <FIG>) that is on a portion of an exterior sidewall of an LED, has a higher contact angle. This may reduce wetting of the underfill material, thereby providing uneven regions or voids in the underfill material between pixels in a pixelated-LED chip. As indicated, the first SiO<NUM> material (SiO<NUM>-<NUM>), the second SiO<NUM> material (SiO<NUM>-<NUM>), and the SiC demonstrated the lowest contact angles, or improved wetting or wicking of underfill material. In particular, the SiO<NUM>-<NUM> material demonstrated the lowest contact angle with values under about <NUM> degrees, or in a range including about <NUM> degrees to about <NUM> degrees. The SiO<NUM>-<NUM> material was deposited with a higher density or fewer voids than the SiO<NUM>-<NUM> material by adjusting the deposition conditions according to common manufacturing techniques for SiO<NUM>. In certain embodiments, a wetting layer may be arranged on exterior surfaces of an LED chip or a pixel of a pixelated-LED chip with a contact angle with the underfill material in a range of about <NUM> degrees to about <NUM> degrees, or in a range of from about <NUM> degrees to about <NUM> degrees.

<FIG> illustrates a representative LED chip <NUM> that includes a wetting layer <NUM> configured to promote improved wetting or wicking of an underfill material. The LED chip <NUM> is illustrated as a flip-chip LED that is similar to the flip chip LED chip <NUM> of <FIG>. In particular, the LED chip <NUM> includes the substrate <NUM>, the internal light-transmissive surface <NUM>, the first semiconductor layer <NUM>, the second semiconductor layer <NUM>, the active region <NUM>, the mesa <NUM> that is laterally bounded by the at least one recess <NUM> containing part of the passivation layer <NUM> as previously described. The LED chip <NUM> additionally includes the multi-layer reflector arranged proximate to (e.g., on) the second semiconductor layer <NUM>, with the multi-layer reflector consisting of the dielectric reflector layer <NUM> and the metal reflector layer <NUM> as previously described. In certain embodiments, the multi-layer reflector "wraps around" peripheral portions of the semiconductor layers <NUM>, <NUM> (including the active region <NUM>). In one embodiment, the first semiconductor layer <NUM> proximate to the substrate <NUM> embodies an n-doped material (e.g., n-GaN), and the second semiconductor layer <NUM> embodies a p-doped material (e.g., p-GaN). The at least one recess <NUM>, which is vertically bounded by the surface extensions 21A of the first semiconductor layer <NUM>, further may include peripheral "wrap-around" portions <NUM>' of the dielectric layer <NUM>. In this regard, the "wrap-around" portions <NUM>' of the dielectric layer <NUM> are configured to reflect or redirect light from the active region <NUM> that may otherwise escape laterally from the LED chip <NUM> in an undesired emission direction. Within the at least one recess <NUM>, the "wrap-around" portions <NUM>' are peripherally bounded by passivation material of the passivation layer <NUM>. As previously described, the passivation layer <NUM> may include moisture resistant SiN to prevent moisture to be drawn into contact with portions of the metal reflector layer <NUM> or the interlayer <NUM>, which would be expected to lead to detrimental chemical interaction. The LED chip <NUM> further includes the wetting layer <NUM> on the passivation layer <NUM>. As illustrated, the wetting layer <NUM> is arranged to peripherally bound the passivation layer <NUM> in the at least one recess <NUM>. In this manner, the passivation layer <NUM> is configured as a moisture barrier while the wetting layer <NUM> provides a surface to promote wetting or wicking of underfill materials. Accordingly, the at least one recess <NUM> may include portion of the "wrap-around" portion <NUM>' of the dielectric reflector <NUM>, the passivation layer <NUM> and the wetting layer <NUM> that are sequentially configured to laterally or peripherally bound the mesa <NUM>. In accordance with the invention, the wetting layer <NUM> is configured to comprise a contact angle with the underfill material of less than about <NUM> degrees, or in a range of about <NUM> degrees to about <NUM> degrees, or in a range of about <NUM> degrees to about <NUM> degrees as previously described. In certain embodiments, the wetting layer <NUM> is compositionally different from the passivation layer <NUM>. In certain embodiments, the wetting layer <NUM> comprises a dielectric material, such as SiO<NUM>. The wetting layer <NUM> may also comprise a layer or coating of SiC, or TiON, among others. In certain embodiments, the wetting layer <NUM> may be arranged between the passivation layer <NUM> and the first and second externally accessible electrical contacts <NUM>, <NUM>.

Following formation of the passivation layer <NUM> and the wetting layer <NUM>, the one or more side portions <NUM> extending between the outer major surface <NUM> of the substrate <NUM> and the surface extensions 21A of the first semiconductor layer <NUM> may not be covered with the passivation layer <NUM> and the wetting layer <NUM>. Such side portions <NUM> embody non-passivated side surfaces. In certain embodiments, the side portions <NUM> and the wetting layer <NUM> are configured to both comprise a contact angle with an underfill material of less than about <NUM> degrees, or in a range of about <NUM> degrees to about <NUM> degrees, or in a range of about <NUM> degrees to about <NUM> degrees as previously described. In certain embodiments, the wetting layer <NUM> may also be configured to extend on and peripherally bound the one or more side portions <NUM> of the substrate <NUM>.

<FIG> are schematic cross-sectional views of various states of fabrication of a pixelated-LED chip according to the invention that includes a wetting layer and an underfill material arranged in inter-pixel spaces between adjacent pixels. In <FIG>, a pixelated-LED chip <NUM> includes the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and the substrate portions <NUM>-<NUM> to <NUM>-<NUM> that form the pixels 104a to 104c as previously described. Additionally, the pixels 104a to 104c are arranged in a flip-chip configuration with electrically conductive paths between the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM> of the submount <NUM>. As illustrated, the wetting layer <NUM> is configured to at least peripherally bound the active layer portions <NUM>-<NUM> to <NUM>-<NUM>. In this manner, the wetting layer <NUM> is configured to cover lateral surfaces of the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and the mesa (<NUM> of <FIG>) of each pixel 104a to 104c that are adjacent the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. As previously described, the passivation layer (<NUM> of <FIG>) may be arranged to laterally bound the mesa (<NUM> of <FIG>) of each pixel 104a to 104c. In this manner, the wetting layer <NUM> may be arranged to laterally bound the passivation layer (<NUM> of <FIG>) along the mesa (<NUM> of <FIG>) of each pixel 104a to 104c. In <FIG>, the underfill material <NUM> has been applied between the substrate portions <NUM>-<NUM> to <NUM>-<NUM> and the submount <NUM> of the pixelated-LED chip <NUM>. The underfill material <NUM> fills the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> as well as filling open spaces between the plurality of anode-cathode pairs <NUM>, <NUM> that are bonded to the plurality of electrode pairs <NUM>, <NUM>. In this manner, the underfill material <NUM> may be arranged to cover various lateral surfaces between the pixels 104a to 104c, including lateral surfaces of the adjacent substrate portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces of the adjacent active layer portions <NUM>-<NUM> to <NUM>-<NUM>, lateral surfaces between the anode-cathode pairs <NUM>, <NUM> of the adjacent pixels 104a to 104c, and lateral surfaces between the electrode pairs <NUM>, <NUM> that are registered with the adjacent pixels 104a to 104c. In certain embodiments, the underfill material <NUM> is arranged in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> to cover all lateral surfaces between the adjacent pixels 104a to 104c. In particular, the underfill material <NUM> is arranged to cover the wetting layer <NUM> that peripherally bounds the active layer portions <NUM>-<NUM> to <NUM>-<NUM> as well as the portions of the wetting layer <NUM> that are between the anode-cathode pairs <NUM>, <NUM> of each pixel 104a to 104c. In this manner, the underfill material <NUM> may flow more easily to fill the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> and the surfaces between the anode-cathode pairs <NUM>, <NUM> of the adjacent pixels 104a to 104c with reduced voids in the underfill material <NUM>.

<FIG> is a schematic cross-sectional view of a pixelated-LED chip <NUM> with alternative configurations of the wetting layer <NUM> of <FIG>. As illustrated, the wetting layer <NUM> may be configured to at least peripherally bound the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and at least a portion of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In particular, the wetting layer <NUM> may be configured to laterally bound substantially all of each lateral edge of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. Accordingly, the wetting layer <NUM> is arranged entirely between the underfill material <NUM> and each of the substrate portions <NUM>-<NUM> to <NUM>-<NUM> in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. In other embodiments, the wetting layer <NUM> may be configured to laterally bound the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and only portions of each lateral edge of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>, as indicated by an alternative wetting layer level <NUM>' in <FIG>. In this manner, the wetting layer <NUM> is arranged partially between the underfill material <NUM> and each pixel (104a to 104c of <FIG>) in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM>. When the wetting layer <NUM> is arranged to partially bound lateral edges of each of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>, the remainder of each of the lateral edges may be filled with the underfill material <NUM>. In certain embodiments, a lumiphoric material may be applied as previously described.

<FIG> are schematic cross-sectional views of various states of fabrication of a pixelated-LED chip according to the invention that includes a wetting layer and an underfill material that has been arranged in inter-pixel spaces before discontinuous substrate portion are formed. In <FIG>, the active layer portions <NUM>-<NUM> to <NUM>-<NUM> of a pixelated-LED chip <NUM> have been formed on the substrate <NUM>, and the substrate <NUM> has been flip-chip mounted on the submount <NUM> to form electrically conductive paths between the plurality of anode-cathode pairs <NUM>, <NUM> and the plurality of electrode pairs <NUM>, <NUM>. As illustrated, the wetting layer <NUM> is configured to at least peripherally bound the active layer portions <NUM>-<NUM> to <NUM>-<NUM> as previously described. The active layer portions <NUM>-<NUM> to <NUM>-<NUM> form the plurality of pixels 104a to 104c on a continuous portion of the substrate <NUM>. In <FIG>, the underfill material <NUM> has been applied between the substrate <NUM> and the submount <NUM> of the pixelated-LED chip <NUM>. The underfill material <NUM> fills the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> as well as filling open spaces between the plurality of anode-cathode pairs <NUM>, <NUM> that are bonded to the plurality of electrode pairs <NUM>, <NUM>. In <FIG>, the substrate <NUM> is continuous over the active layer portions <NUM>-<NUM> to <NUM>-<NUM> and, accordingly, the underfill material <NUM> is applied along a perimeter of the pixelated-LED chip <NUM> between the substrate <NUM> and the submount <NUM>. A wicking action and a capillary action allows the underfill material <NUM> to fill the inter-pixel spaces <NUM>-<NUM>,<NUM>-<NUM> and the spaces between the plurality of anode-cathode pairs <NUM>, <NUM>. The wetting layer <NUM> provides improved flow and wicking by reducing surface energy with the underfill material <NUM> to provide the underfill material <NUM> in these spaces with reduced voids or bubbles. In certain embodiments, a pressure or a vacuum is applied to the pixelated-LED chip <NUM> to assist the wicking and capillary action of the underfill material <NUM>. In <FIG>, the discontinuous substrate portions <NUM>-<NUM> to <NUM>-<NUM> have been formed in the pixelated-LED chip <NUM> after the underfill material <NUM> has been formed. In this manner, the underfill material <NUM> may only partially cover lateral surfaces of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In certain embodiments, an additional material that may be the same material or different than the underfill material <NUM> may be applied in the inter-pixel spaces <NUM>-<NUM>, <NUM>-<NUM> to substantially cover the remaining lateral surfaces of the substrate portions <NUM>-<NUM> to <NUM>-<NUM>. In certain embodiments, a lumiphoric material may be applied as previously described.

Claim 1:
A pixelated light emitting diode (LED) chip (<NUM>) comprising:
a plurality of pixels (104a-104c), wherein each pixel (104a-104c) of the plurality of pixels (104a-104c) includes semiconductor layers (<NUM>, <NUM>) that form a mesa (<NUM>), a passivation layer (<NUM>) on the semiconductor layers (<NUM>, <NUM>) and laterally bounding the mesa (<NUM>), and electrical contacts (<NUM>, <NUM>), and wherein inter-pixel spaces (<NUM>-<NUM>, <NUM>-<NUM>) are provided between adjacent pixels (104a-104c) of the plurality of pixels (104a-104c); and
an underfill material (<NUM>) arranged in the inter-pixel spaces (<NUM>-<NUM>, <NUM>-<NUM>) between the adjacent pixels (104a-104c); and
characterized in that
a wetting layer (<NUM>) is arranged between the underfill material (<NUM>) and the passivation layer (<NUM>) of each pixel (104a-104c), wherein the wetting layer (<NUM>) is arranged to laterally bound the passivation layer (<NUM>) along the mesa (<NUM>) of each pixel (104a-104c),
wherein the wetting layer (<NUM>) comprises a contact angle with the underfill material (<NUM>) of less than about <NUM> degrees.