Patent Description:
In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are desired to be small in size, to support multi-pin connection, to support high speeds, and to support high functionality. The demand for increasing Input-Output (I/O) pin counts and high-performance ICs has led to the development of flip chip packages.

Flip-chip technology uses bumps on a chip to interconnect to a package substrate. The flip-chip is bonded face down to the package substrate through the shortest path. The technology used can be applied not only to a single-chip package, but also to higher or integrated levels of packaging in which the packages are larger and packaged with more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, can achieve a high density interconnection with devices and a very low inductance interconnection with packaging. However, this requires printed circuit board (PCB) fabricators to minimize line widths and space or to develop direct chip attach (DCA) semiconductors. Accordingly, the increased amount of input/output connections of a multifunctional flip-chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products.

<CIT> discloses a semiconductor device in which a chip is mounted on a wiring board. The chip is mounted on pads formed in a wiring layer of the wiring board by means of solder bumps.

<CIT> describes a semiconductor chip mounted on a support plate through an insulating layer by means of solder bumps made of solder and connected to underlying electrode pads having a layer structure including a gold layer and a layer and via conductive patterns formed in the insulating layer.

A semiconductor chip mounted on a built-up structure by means of solder bumps and metal bumps is know from <CIT>.

In <CIT>, electrode pads are used for mounting a semiconductor device on a base. In <CIT>, contact pads are employed on a carrier substrate for mounting a die on a PCB via solder bumps.

<CIT> describes a plurality of package traces embedded in an insulating layer. This document discloses a trace layer with a bottom surface and sidewalls connected to an insulating layer and with top surface that is aligned with a surface of the insulating layer in which the solder is embedded. This same document also discloses a trace embedded in an insulating layer having a top surface below a surface of the insulating layer but without having a bottom surface fully connected to the insulating layer.

<CIT> describes a trace line having a top surface aligned with a surface of a surrounding substrate in which the trace line is embedded and trace lines that are not embedded in an underlying substrate.

<CIT> likewise discloses a trace line having a top surface aligned with a surface of a surrounding substrate in which the trace line is embedded and trace lines that are not embedded in an underlying substrate.

None of <CIT>, <CIT> and <CIT> discloses a conductive trace having a top surface above a surface of a base while being embedded in said base.

<CIT> teaches using out-of-plane traces protruding from a base as screening elements for shielding adjacent in-plane traces embedded in the base.

<CIT> discloses a semiconductor package and manufacturing method, in which the semiconductor package lead frame can be isolated and transported during the manufacturing process.

<CIT> discloses a circuit board with a buried conductive trace formed thereon. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding.

<CIT> discloses a wiring substrate including a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film.

In <NPL>, coper pillar bump technology is described in general.

<CIT> describes that bumps including a fusible material that are deformable onto mating surfaces of traces, such that deformation of the bumps breaks oxide film on the contact surfaces of the bumps and the mating surfaces of the traces, establishing a good electrical and mechanical connection.

Thus, a novel high-density flip chip package and a printed circuit board for a high-density flip chip package are desirable.

A semiconductor package as defined in claim <NUM> is provided.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:.

The following description is a mode for carrying out the invention. The scope of the invention is determined by the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention.

<FIG> and <FIG> show an embodiment of a semiconductor package of the invention. In this embodiment, the semiconductor package can be a flip chip package using conductive structures, for example, copper pillar bumps, connecting a semiconductor device to a base. Alternatively, the semiconductor package can be a package using wire bonding technology to connect a semiconductor device to a base. <FIG> shows a partial cross section of one exemplary embodiment of a semiconductor package 500a of the invention. Please refer to <FIG>, wherein the semiconductor package 500a comprises a base <NUM> having a device attach surface <NUM>. In one embodiment, the base <NUM>, for example, a print circuit board (PCB), may be formed of polypropylene (PP). It should be also noted that the base <NUM> can be a single layer or a multilayer structure. A plurality of conductive traces 202a is embedded in the base <NUM>. In one embodiment, the conductive traces 202a may comprise signal trace segments or ground trace segments, which are used for input/output (I/O) connections of a semiconductor device <NUM> mounted directly onto the base <NUM>. Therefore, each of the conductive traces 202a has a portion serving as a pad region of the base <NUM>. In this embodiment, the conductive traces 202a are designed to have a width which is larger than <NUM>. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than <NUM> if required.

A semiconductor device <NUM> is mounted on the device attach surface <NUM> of the base <NUM> with an active surface of the semiconductor device <NUM> facing the base <NUM> by a bonding process. In one embodiment, the semiconductor device <NUM> may comprise a die, a passive component, a package or a wafer level package. In this embodiment, the semiconductor device <NUM> is a flip chip package. A circuitry of the semiconductor device <NUM> is disposed on the active surface, and metal pads <NUM> are disposed on a top of the circuitry. The circuitry of the semiconductor device <NUM> is interconnected to the circuitry of the base <NUM> via a plurality of conductive structures <NUM> disposed on the active surface of the semiconductor device <NUM>. However, it should be noted that the conductive structures <NUM> shown in <FIG> is only an example and is not a limitation to the present invention.

As shown in <FIG>, the semiconductor device <NUM> may include a body <NUM>, metal pads <NUM> overlying the semiconductor body <NUM>, and an insulation layer <NUM> covering the metal pads <NUM>. In this embodiment, the semiconductor body <NUM> may include but is not limited to a semiconductor substrate, circuit elements fabricated on the main surface of the semiconductor substrate, inter-layer dielectric (ILD) layers and an interconnection structure. In one embodiment, the interconnection structure may comprise a plurality of metal layers, a plurality of dielectric layers alternatively laminated with the metal layers and a plurality of vias formed through the dielectric layers on the semiconductor substrate. The metal pads <NUM> comprise the topmost metal layer of the metal layers of the interconnection structure. In one embodiment, the insulation layer <NUM> may be a single layer structure or a multilayer structure, and the insulation layer <NUM> may comprise but is not limited to silicon nitride, silicon oxide, silicon oxynitride, polyimide or any combination thereof. Also, the insulation layer <NUM> may have functions of stress buffering and insulation. In one embodiment, the metal pad <NUM> may comprise but is not limited to aluminum, copper or alloys thereof. A plurality of openings can be formed in the insulation layer <NUM>. Each of the openings exposes at least a portion of one of the metal pads <NUM>.

As shown in <FIG>, the conductive structure <NUM> may comprise a conductive bump structure such as a copper bump or a solder bump structure, a conductive wire structure, or a conductive paste structure. In this embodiment, the conductive structure <NUM> may be a copper bump structure composed of a metal stack comprising a UBM (under bump metallurgy) layer <NUM>, a copper layer <NUM> such as a plated copper layer, a conductive buffer layer <NUM>, and a solder cap <NUM>. In one embodiment, the UBM layer <NUM> can be formed on the exposed metal pads <NUM> within the openings by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. The UBM layer <NUM> may also extend onto a top surface of the insulation layer <NUM>. In this embodiment, the UBM layer <NUM> may comprise titanium, copper or a combination thereof. A copper layer <NUM> such as an electroplated copper layer can be formed on the UBM layer <NUM>. The opening can be filled with the copper layer <NUM> and the UBM layer <NUM>, and the copper layer <NUM> and the UBM layer <NUM> within the opening may form an integral plug of the conductive structure <NUM>. A formation position of the copper layer <NUM> is defined by a dry film photoresist or liquid photoresist patterns (not shown).

A solder cap <NUM> can be formed on the copper layer <NUM> by electroplating a solder with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process. A conductive buffer layer <NUM> formed of Ni may be formed between the copper layer <NUM> and the solder cap <NUM> by an electroplating method. The conductive buffer layer <NUM> may serve as a seed layer, adhesion layer and barrier layer for the solder cap <NUM> formed thereon. In this embodiment, the conductive structure <NUM>, such as a conductive pillar structure, is used as a solder joint for the metal pad <NUM>, which transmits input/output (I/O), ground or power signals of the semiconductor device <NUM> formed thereon. Therefore, the copper layer <NUM> of the conductive structure <NUM> may help to increase the mechanical strength of the bump structure. In one embodiment, an underfill material or the underfill <NUM> can be introduced into the gap between the semiconductor device <NUM> and the base <NUM>. In one embodiment, the underfill <NUM> may comprises a capillary underfill (CUF), molded underfill (MUF) or a combination thereof.

According to the present invention, and as shown in <FIG>, the conductive traces 202a have top surfaces 212a disposed below a device attach surface <NUM> of the base <NUM>. That is to say, a bottom surface 206a and at least a portion of a sidewall 204a of the conductive trace 202a are designed to be connected to the base <NUM>. In this embodiment, the solder cap <NUM> of the conductive structure <NUM> is disposed to contact with a portion of the base <NUM> and to connect to a top surface 212a of the conductive trace 202a only. Due to the top surfaces of the conductive traces being recessed from the device attach surface <NUM> of the base <NUM>, the bump-to-trace space is increased and the problem of bump-to-trace bridging can be effectively avoided.

<FIG> shows a partial cross section of a semiconductor package 500b which is not part of the invention. Elements that are the same or similar as those previously described with reference to <FIG>, are hereinafter not repeated for brevity. In this device, conductive traces 202b of the semiconductor package 500b embedded in the base <NUM> may have a top surface 212b designed to be aligned to a device attach surface <NUM> of the base <NUM> to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface 206b and a sidewall 204b of the conductive trace 202b are designed to be fully connected to the base <NUM>. Therefore, the solder cap <NUM> of the conductive structure <NUM> is disposed on the device attach surface <NUM> of the base <NUM>, contacting the top surface 212b of the conductive trace 202b only.

<FIG> shows a partial cross section of yet another semiconductor package 500c not part of the invention. Elements that are the same or similar as those previously described with reference to <FIG> and <FIG>, are hereinafter not repeated for brevity. In this device, conductive traces 202c of the semiconductor package 500c embedded in the base <NUM> may have a top surface 212c designed above a device attach surface <NUM> of the base <NUM> to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface 206c and only a portion of a sidewall 204c of the conductive trace 202c are designed to be connected to the base <NUM>. Therefore, the solder cap <NUM> of the conductive structure <NUM> is disposed on the device attach surface <NUM> of the base <NUM>, wrapping a top surface 212c and only a portion of the sidewall 204c of the conductive trace 202c.

<FIG> shows a partial cross section of another exemplary embodiment of a semiconductor package 500d of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to <FIG>, are hereinafter not repeated for brevity. The base may comprise a single layer structure as shown in <FIG>. Alternatively, the base may comprise a multilayer structure. In this embodiment, conductive traces 202d of the semiconductor package 500d embedded in the base portion 200a may have a top surface 212d designed to be aligned to a surface <NUM> of the base portion 200a to improve routing ability for high-density semiconductor packages. That is to say, a bottom surface 206d and a sidewall 204d of the conductive trace 202d are designed to be connected to the base portion 200a. Also, an insulation layer <NUM> having openings <NUM> is disposed on the base portion 200a. The insulation layer <NUM> is disposed above the device attach surface <NUM> of the conductive trace 202d. In this embodiment, the base portion 200a and the insulation layer <NUM> collectively serve as a multilayer base. As shown in <FIG>, the conductive traces 202d are exposed within the openings <NUM>. Therefore, the solder cap <NUM> of the conductive structure <NUM> is formed through a portion of the insulation layer <NUM>, contacting a top surface 212d of the conductive trace 202d only. It should be noted that it is not necessary for the insulation layer <NUM> to align with the sidewall 204d of the conductive traces 202d. Instead, it can be designed to be distanced outward or inward from the sidewall 204d of the conductive traces 202d as shown in <FIG>.

<FIG> are cross sections showing a method for fabricating two bases 200c and 200d for a semiconductor package not part of the invention. This method for fabricating bases for a semiconductor package is also called a double-sided base fabricating process. Elements that are the same or similar as those previously described with reference to <FIG>, are hereinafter not repeated for brevity. As shown in <FIG>, a carrier <NUM> with conductive seed layers 402a and 402b on a top surface <NUM> and a bottom surface <NUM> is provided. The carrier <NUM> may comprise FR4 glass epoxy or stainless steel. Also, the conductive seed layers 402a and 402b are used as seed layers for subsequently formed interconnection conductive traces of bases on the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>. The conductive seed layers 402a and 402b may comprise copper.

Next, as shown in <FIG>, first conductive traces 404a and 404b are respectively formed on the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>. Bottom portions of the first conductive traces 404a and 404b connect to top portions of the conductive seed layers 402a and 402b. The first conductive traces 404a and 404b may be formed by a plating process and an anisotropic etching process. The plating process and the anisotropic etching process are simultaneously performed on the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>. The plating process may comprise an electrical plating process. The first conductive traces 404a and 404b may comprise copper. The first conductive traces 404a and 404b are designed to have a width which is larger than <NUM>. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than <NUM> if required. The anisotropic etching process may precisely control the width of the first conductive traces 404a and 404b.

Next, as shown in <FIG>, a laminating process is performed to respectively dispose a first base material layer 406a and a second base material layer 406b on the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>, wherein the first base material layer 406a and a second base material layer 406b respectively cover the first conductive traces 404a and 404b.

The laminating process of the first base material layer 406a and the second base material layer 406b is simultaneously performed on the on the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>. The first base material layer 406a and the second base material layer 406b may comprise polypropylene (PP).

Next, please refer to <FIG> again, wherein a drilling process is performed to form openings (not shown) through the first base material layer 406a and the second base material layer 406b to define the formation positions of subsequently formed vias 408a and 408b. The drilling process may comprise a laser drilling process, an etching drilling process or a mechanical drilling process. Next, a plating process is performed to fill a conductive material into the openings to form vias 408a and 408b for interconnecting the first conductive traces 404a and 404b to subsequent second conductive traces 410a and 410b.

The drilling process and the plating process are simultaneously performed on the first base material layer 406a and the second base material layer 406b, respectively.

Next, please refer to <FIG> again, wherein a plurality of second conductive traces 410a and 410b are respectively formed on a first surface <NUM> of the first base material layer 406a and a first surface <NUM> of the second base material layer 406b. As shown in <FIG>, the first surface <NUM> of the first base material layer 406a and the first surface <NUM> of the second base material layer 406b are respectively away from the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM>. The second conductive traces 410a and 410b are formed by a plating process and an anisotropic etching process. The plating process and the anisotropic etching process are simultaneously performed on the first surface <NUM> of the first base material layer 406a and the first surface <NUM> of the second base material layer 406b. The plating process may comprise an electrical plating process. The second conductive traces 410a and 410b may comprise copper. The second conductive traces 410a and 410b are designed to have a width which is larger than <NUM>. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than <NUM> if required. The anisotropic etching process may precisely control the width of the second conductive traces 410a and 410b.

Next, as shown in <FIG>, the first base material layer 406a with the first and second conductive traces 404a and 410a thereon and the second base material layer 406b with the first and second conductive traces 404b and 410b thereon are respectively separated from the top surface <NUM> and the bottom surface <NUM> of the carrier <NUM> to form a first base 200c and a second base 200d which are separated from each other. Next, as shown in <FIG> again, the conductive seed layers 402a and 402b are removed from the first base 200c and the second base 200d, respectively.

As shown in <FIG>, the first conductive traces 404a and 404b are aligned to second surfaces <NUM> and <NUM> of the of the first and second bases 200c and 200d, which are respectively opposite to the first surfaces <NUM> and <NUM>. The first base 200c and the second base 200d are simultaneously fabricated on opposite surfaces (the top surface <NUM> and the bottom surface <NUM>) by the double-sided base fabricating process.

Alternatively, two passivation or insulation layers (not shown) having openings may be optionally formed respectively on a second surface <NUM> of the first base 200c and the second surface <NUM> of the second base 200d after the separation of the first base 200c and the second base 200d as shown in <FIG>. In this alternative, the first conductive traces 404a and 404b of the first and second bases 200c and 200d are exposed within the opening. Positions of the insulation layer with openings and the first conductive traces 404a/404b as shown in <FIG> can be similar to the insulation layer <NUM> with openings <NUM> and the conductive traces 202d as shown in <FIG>. Also, in this alternative, the first base 200a/second base 200b and the insulation layer thereon collectively serve as a multilayer base.

<FIG> are cross sections showing an exemplary embodiment of a method for making a semiconductor package of the invention. Also, <FIG> shows a cross section of another exemplary embodiment of a semiconductor package 500e of the invention. Elements of the embodiments that are the same or similar as those previously described with reference to <FIG> and <FIG>, are hereinafter not repeated for brevity. Alternatively, the base may have a multilayer structure. As shown in <FIG>, a base <NUM> with a top surface <NUM> is provided. Next, as shown in <FIG>, at least one conductive trace <NUM> is formed on the top surface <NUM> of the base <NUM>. In one embodiment, the conductive trace <NUM> may be formed by a plating process and an anisotropic etching process. In one embodiment, the plating process may comprise an electrical plating process. In one embodiment, the conductive trace <NUM> may comprise copper. In one embodiment, the conductive trace <NUM> is designed to have a width which is larger than <NUM>. However, it should be noted that there is no limitation on the width of the conductive traces. For different designs, the width of the conductive traces can be smaller than <NUM> if required. In this embodiment, the anisotropic etching process may precisely control the width of the conductive trace <NUM>.

Next, as shown in <FIG>, a laminating process is performed to respectively dispose an additional insulation material <NUM> on the top surface <NUM> of the base <NUM>. Also, the additional insulation material <NUM> covers a top surface <NUM> and sidewalls <NUM> of the conductive trace <NUM>.

Next, please refer to <FIG>, wherein a drilling process is performed to form at least one opening <NUM> through the additional insulation material <NUM> to define formation of a position of a subsequently formed conductive structure, for example, a copper bump structure or a solder bump structure. In one embodiment, the drilling process may comprise a laser drilling process, an etching drilling process or a mechanical drilling process. In this embodiment, the top surface <NUM> of the conductive trace <NUM> is exposed within the opening <NUM> of the additional insulation material <NUM>.

Next, as shown in <FIG>, a bonding process is performed to mount a semiconductor device <NUM> on the base <NUM> through the conductive structure <NUM>. Elements of the semiconductor device <NUM> and the conductive structure <NUM> that are the same or similar as those previously described with reference to <FIG>, are hereinafter not repeated for brevity.

After the bonding process, the conductive structures <NUM> are disposed through the opening <NUM> of the additional insulation material <NUM>, contacting to the top surface <NUM> of the conductive trace <NUM> only. Next, an underfill material or the underfill <NUM> can be introduced into the gap between the semiconductor device <NUM> and the additional insulation material <NUM>. In one embodiment, the underfill <NUM> may comprises a capillary underfill (CUF), molded underfill (MUF) or a combination thereof. Finally, the base <NUM>, the additional insulation material <NUM>, the semiconductor device <NUM>, the conductive trace <NUM>, and the conductive structure <NUM> collectively form a semiconductor package 500e.

Exemplary embodiments provide a semiconductor package. The semiconductor package is designed to comprise conductive trace embedded in a base, for example, a print circuit board (PCB). The conductive traces have a top surface disposed below a surface of the base to improve routing ability for high-density semiconductor packages. Also, the conductive traces are designed to have a width which is larger than <NUM>. Further, the base may comprise a single layer structure or a multilayer structure. Exemplary embodiments also provide a method for fabricating a base for a semiconductor package. In one embodiment, the method can fabricate two bases on two sides of a carrier simultaneously. Also, the conductive traces are embedded in the base. Further, the conductive trace may be formed by a plating process and an anisotropic etching process, and the anisotropic etching process may precisely control the width of the conductive trace. Alternatively, the method can fabricate a base comprising a single layer structure or a multilayer structure to improve design capability.

Claim 1:
A semiconductor package comprising:
a conductive trace (202a; 202d; <NUM>) embedded in a base (<NUM>; 200a; <NUM>; <NUM>; <NUM>) having a device attach surface (<NUM>); and
a semiconductor device (<NUM>) mounted on the conductive trace (202a; 202d; <NUM>) via a conductive structure (<NUM>); wherein
the conductive trace (202a; 202d; <NUM>) has a top surface (212a; 212d; <NUM>) below the device attach surface (<NUM>) of the base (<NUM>; 200a; <NUM>; <NUM>; <NUM>); and
the conductive structure (<NUM>) contacts a top surface (212a; 212d; <NUM>) of the conductive trace (202a; 202d; <NUM>) and is disposed on the device attach surface of the base (<NUM>; 200a; <NUM>; <NUM>; <NUM>).