Patent Description:
<CIT> discloses an inkjet print head including data signal lines configured to supply inkjet control voltages and non-volatile memory cell random access addresses.

<CIT> discloses a circuit for use with a memory element and a nozzle for outputting fluid, the circuit including a data line, a fire line, and a selector responsive to the data line to select the memory element or the nozzle.

<CIT> discloses an integrated circuit comprising an elongate substrate having a length, a thickness, and a width, the length being at least twenty times the width, wherein on the elongate substrate there is provided a plurality of nozzles arranged in a column along the length of the elongate substrate.

Fluid ejection dies, such as thermal inkjet (TIJ) dies may be narrow and long pieces of silicon. The silicon area used by a die is related to the cost of the die so that any functionality that can be removed from the die should be removed or modified to have multiple purposes if possible. Non-volatile memory (NVM) may be used on the die to transfer information from the die to a printer, such as thermal behavior, offsets, region information, a color map, the number of nozzles, etc. In addition, NVM may also be used to transfer information from the printer to the die, such as an ink usage gauge, nozzle health information, etc. Memories may be composed of storage elements, read/write multiplexers, and enable/address circuitry. For small memories, the non-storage circuitry may be a large percentage of the overall area used by the memory, making small memories very area inefficient.

Accordingly, disclosed herein are integrated circuits (e.g., fluid ejection dies) including memory cells corresponding to fluid actuation devices. The same circuit logic is used to activate either selected fluid actuation devices or access selected corresponding memory cells based on received addresses and nozzle data. The data stored in each memory cell may be read out of the integrated circuit through a single contact pad. The memory cells may be distributed along the length of the integrated circuit adjacent to the corresponding fluid actuation devices.

As used herein a "logic high" signal is a logic "<NUM>" or "on" signal or a signal having a voltage about equal to the logic power supplied to an integrated circuit (e.g., between about <NUM> V and <NUM> V, such as <NUM> V). As used herein a "logic low" signal is a logic "<NUM>" or "off" signal or a signal having a voltage about equal to a logic power ground return for the logic power supplied to the integrated circuit (e.g., about <NUM> V).

<FIG> is a block diagram illustrating one example of an integrated circuit <NUM> to drive a plurality of fluid actuation devices. Integrated circuit <NUM> includes a plurality of fluid actuation devices <NUM><NUM> to <NUM>N, where "N" is any suitable number of fluid actuation devices. Integrated circuit <NUM> also includes a plurality of memory cells <NUM><NUM> to <NUM>N, a select circuit <NUM>, control logic <NUM>, and configuration logic <NUM>. Each fluid actuation device <NUM><NUM> to <NUM>N is electrically coupled to control logic <NUM> through a signal path <NUM><NUM> to <NUM>N, respectively. Each memory cell <NUM><NUM> to <NUM>N is electrically coupled to control logic <NUM> through a signal path <NUM><NUM> to <NUM>N, respectively. Control logic <NUM> is electrically coupled to select circuit <NUM> through a signal path <NUM> and to configuration logic <NUM> through a signal path <NUM>.

In one example, each fluid actuation device <NUM><NUM> to <NUM>N includes a nozzle or a fluidic pump to eject fluid drops. Each memory cell <NUM><NUM> to <NUM>N corresponds to a fluid actuation device <NUM><NUM> to <NUM>N, respectively. In one example, each memory cell <NUM><NUM> to <NUM>N includes a non-volatile memory cell (e.g., a floating gate transistor, a programmable fuse, etc.). The select circuit <NUM> selects fluid actuation devices <NUM><NUM> to <NUM>N and memory cells <NUM><NUM> to <NUM>N corresponding to the selected fluid actuation devices <NUM><NUM> to <NUM>N. Select circuit <NUM> may include an address decoder, activation logic, and/or other suitable logic circuitry for selecting fluid actuation devices <NUM><NUM> to <NUM>N and corresponding memory cells <NUM><NUM> to <NUM>N in response to an address signal and a nozzle data signal. Configuration logic <NUM> enables or disables access to the plurality of memory cells <NUM><NUM> to <NUM>N. Configuration logic <NUM> may include a memory device or other suitable logic circuitry for enabling or disabling access to the plurality of memory cells <NUM><NUM> to <NUM>N.

Control logic <NUM> either activates the selected fluid actuation devices <NUM><NUM> to <NUM>N or accesses the memory cells <NUM><NUM> to <NUM>N corresponding to the selected fluid actuation devices based on a state of the configuration logic <NUM>. Control logic <NUM> may include a microprocessor, an application-specific integrated circuit (ASIC), or other suitable logic circuitry for controlling the operation of integrated circuit <NUM>. While select circuit <NUM>, control logic <NUM>, and configuration logic <NUM> are illustrated in separates blocks in <FIG>, in other examples, select circuit <NUM>, control logic <NUM>, and/or configuration logic <NUM> may be combined into a single block or a different number of blocks.

<FIG> is a block diagram illustrating another example of an integrated circuit <NUM> to drive a plurality of fluid actuation devices. Integrated circuit <NUM> includes a plurality of fluid actuation devices <NUM><NUM> to <NUM>N, a plurality of memory cells <NUM><NUM> to <NUM>N, a select circuit <NUM>, and control logic <NUM>. In addition, integrated circuit <NUM> includes a write circuit <NUM>, a sensor <NUM>, and a configuration register <NUM>. In one example, configuration logic <NUM> of integrated circuit <NUM> of <FIG> includes configuration register <NUM>.

In this example, select circuit <NUM> includes an address decoder <NUM> and activation logic <NUM>. Address decoder <NUM> receive addresses and data through a data interface <NUM>. Address decoder <NUM> is electrically coupled to activation logic <NUM>. Activation logic <NUM> receives a fire signal through a fire interface <NUM>. Each memory cell <NUM><NUM> to <NUM>N is electrically coupled to write circuit <NUM> through a sense interface <NUM>. Sensor <NUM> is electrically coupled to control logic <NUM> through a signal path <NUM> and to sense interface <NUM>.

Address decoder <NUM> selects fluid actuation devices <NUM><NUM> to <NUM>N and memory cells <NUM><NUM> to <NUM>N corresponding to the selected fluid actuation devices <NUM><NUM> to <NUM>N in response to an address. The address may be received through data interface <NUM>. The activation logic <NUM> activates selected fluid actuation devices <NUM><NUM> to <NUM>N and memory cells <NUM><NUM> to <NUM>N corresponding to the selected fluid actuation devices <NUM><NUM> to <NUM>N based on a data signal and a fire signal. The data signal may include nozzle data indicating which fluid actuation device(s) for the provided address are to be selected. The data signal may be received through the data interface <NUM>. The fire signal indicates when the selected fluid actuation devices are to be activated (i.e., fired) or when the corresponding memory cells are to be accessed. The fire signal may be received through the fire interface <NUM>. Each of the data interface <NUM>, fire interface <NUM>, and sense interface <NUM> may be a contact pad, a pin, a bump, a wire, or another suitable electrical interface for transmitting signals to and/or from integrated circuit <NUM>. Each of the interfaces <NUM>, <NUM>, and <NUM> may be electrically coupled to a fluid ejection system (e.g., a host print apparatus such as fluid ejection system <NUM>, which will be described below with reference to <FIG>).

The configuration register <NUM> stores data to enable or disable access to the plurality of memory cells <NUM><NUM> to <NUM>N. The control logic <NUM> either activates the selected fluid actuation devices <NUM><NUM> to <NUM>N or accesses the memory cells <NUM><NUM> to <NUM>N corresponding to the selected fluid actuation devices <NUM><NUM> to <NUM>N based on the data stored in the configuration register <NUM>. In one example, the configuration register <NUM> also stores data to enable write access or read access to the plurality of memory cells <NUM><NUM> to <NUM>N. In another example, the configuration register <NUM> also stores data to enable or disable the sensor <NUM>.

Configuration register <NUM> may be a memory device (e.g., non-volatile memory, shift register, etc.) and may include any suitable number of bits (e.g., <NUM> bits to <NUM> bits, such as <NUM> bits). In certain examples, configuration register <NUM> may also store configuration data for testing integrated circuit <NUM>, detecting cracks within a substrate of integrated circuit <NUM>, enabling timers of integrated circuit <NUM>, setting analog delays of integrated circuit <NUM>, validating operations of integrated circuit <NUM>, or for configuring other functions of integrated circuit <NUM>.

Data stored in memory cells <NUM><NUM> to <NUM>N may be read through sense interface <NUM> when the selected memory cells <NUM><NUM> to <NUM>N have been accessed by control logic <NUM>. In addition, write circuit <NUM> may write data to selected memory cells when the selected memory cells <NUM><NUM> to <NUM>N have been accessed by control logic <NUM>. Sensor <NUM> may be a junction device (e.g., thermal diode), a resistive device (e.g., crack detector), or another suitable device for sensing a state of integrated circuit <NUM>. Sensor <NUM> may be read through sense interface <NUM>.

<FIG> is a schematic diagram illustrating one example of a circuit <NUM> to drive a plurality of fluid actuation devices or access corresponding memory cells. In one example, circuit <NUM> is part of integrated circuit <NUM> of <FIG> or integrated circuit <NUM> of <FIG>. Circuit <NUM> illustrates one group of <NUM> fluid actuation devices and a corresponding group of <NUM> memory cells. An integrated circuit, such as integrated circuit <NUM> of <FIG> or integrated circuit <NUM> of <FIG> may include any suitable number of groups of fluid actuation devices and corresponding memory cells. While a group of <NUM> actuation devices and corresponding memory cells is illustrated in <FIG>, in other examples the number of fluid actuation devices and corresponding memory cells within each group may vary.

Circuit <NUM> includes a plurality of fluid actuation devices <NUM><NUM> to <NUM><NUM>, a plurality of memory cells <NUM><NUM> to <NUM><NUM>, an address decoder including logic gates <NUM><NUM> to <NUM><NUM>, activation logic including logic gates <NUM> and <NUM><NUM> to <NUM><NUM>, a write circuit including a memory write voltage regulator <NUM>, transistors <NUM> and <NUM>, and a contact (i.e., sense) pad <NUM>. A first input of logic gate <NUM> receives nozzle data through a nozzle data signal path <NUM>. A second input of logic gate <NUM> receives a fire signal through a fire signal path <NUM>. The output of logic gate <NUM> is electrically coupled to a first input of each logic gate <NUM><NUM> to <NUM><NUM> through a signal path <NUM>. The input of each logic gate <NUM><NUM> to <NUM><NUM> receives an address signal through an address signal path <NUM>. The output of each logic gate <NUM><NUM> to <NUM><NUM> is electrically coupled to a second input of each logic gate <NUM><NUM> to <NUM><NUM> through a signal path <NUM><NUM> to <NUM><NUM>, respectively. The output of each logic gate <NUM><NUM> to <NUM><NUM> is electrically coupled to a fluid actuation device <NUM><NUM> to <NUM><NUM> and to a memory cell <NUM><NUM> to <NUM><NUM> through a signal path <NUM><NUM> to <NUM><NUM>, respectively.

Each fluid actuation device <NUM><NUM> to <NUM><NUM> includes a logic gate <NUM>, a transistor <NUM>, and a firing resistor <NUM>. While fluid actuation device <NUM><NUM> is illustrated and described herein, the other fluid actuation devices <NUM><NUM> to <NUM><NUM> include a similar circuit. A first input of the logic gate <NUM> is electrically coupled to signal path <NUM><NUM>. A second input (inverting) of the logic gate <NUM> receives a memory enable signal through a memory enable signal path <NUM>. The output of logic gate <NUM> is electrically coupled to the gate of transistor <NUM> through a signal path <NUM>. One side of the source-drain path of transistor <NUM> is electrically coupled to a common or ground node <NUM>. The other side of the source-drain path of transistor <NUM> is electrically coupled to one side of firing resistor <NUM> through a signal path <NUM>. The other side of firing resistor <NUM> is electrically coupled to a supply voltage node (e.g., VPP) <NUM>.

Each memory cell <NUM><NUM> to <NUM><NUM> includes transistors <NUM> and <NUM> and a floating gate transistor <NUM>. While memory cell <NUM><NUM> is illustrated and described herein, the other memory cells <NUM><NUM> to <NUM><NUM> include a similar circuit. The gate of transistor <NUM> is electrically coupled to signal path <NUM><NUM>. One side of the source-drain path of transistor <NUM> is electrically coupled to a common or ground node <NUM>. The other side of the source-drain path of transistor <NUM> is electrically coupled to one side of the source-drain path of transistor <NUM> through a signal path <NUM>. The gate of transistor <NUM> receives a memory enable signal through a memory enable signal path <NUM>. The other side of the source-drain path of transistor <NUM> is electrically coupled to one side of the source-drain path of floating gate transistor <NUM> through a signal path <NUM>. The other side of the source-drain path of floating gate transistor <NUM> is electrically coupled to memory write voltage regulator <NUM> and one side of the source-drain path of transistor <NUM> through a signal path <NUM>.

Memory write voltage regulator <NUM> receives a memory write signal through a memory write signal path <NUM>. The gate of transistor <NUM> and the gate of transistor <NUM> receive a memory read signal through a memory read signal path <NUM>. The other side of the source-drain path of transistor <NUM> is electrically coupled to one side of the source-drain path of transistor <NUM> through a signal path <NUM>. The other side of the source-drain path of transistor <NUM> is electrically coupled to sense pad <NUM>.

The nozzle data signal on nozzle data signal path <NUM>, the fire signal on fire signal path <NUM>, and the address signal on address signal path <NUM> are used to activate a fluid actuation device <NUM><NUM> to <NUM><NUM> or a corresponding memory cell <NUM><NUM> to <NUM><NUM>. The memory enable signal on memory enable signal path <NUM> determines whether a fluid actuation device <NUM><NUM> to <NUM><NUM> is activated or whether a corresponding memory cell <NUM><NUM> to <NUM><NUM> is accessed. In response to a logic high memory enable signal, transistor <NUM> is turned on to enable access to memory cells <NUM><NUM> to <NUM><NUM>. In addition, in response to a logic high memory enable signal, logic gate <NUM> outputs a logic low signal to turn off transistor <NUM> to prevent any fluid actuation devices <NUM><NUM> to <NUM><NUM> from firing in response to a fire signal passed to signal paths <NUM><NUM> to <NUM><NUM>. In response to a logic low memory enable signal, transistor <NUM> turns off to disable access to memory cells <NUM><NUM> to <NUM><NUM>. In addition, in response to a logic low memory enable signal, logic gate <NUM> allows fire signals passed to signal paths <NUM><NUM> to <NUM><NUM> to fire fluid actuation devices <NUM><NUM> to <NUM><NUM>. In one example, the memory enable signal is based on a data bit stored in a configuration register, such as configuration register <NUM> of <FIG>. In another example, the memory enable signal is based on a data bit received by circuit <NUM> along with the address and nozzle data, which is used by configuration logic, such as configuration logic <NUM> of <FIG>, to enable or disable the memory cells <NUM><NUM> to <NUM><NUM>.

The nozzle data signal indicates whether fluid actuation devices <NUM><NUM> to <NUM><NUM> or corresponding memory cells <NUM><NUM> to <NUM><NUM> will be selected. In one example, the nozzle data signal includes a logic high signal to select fluid actuation devices <NUM><NUM> to <NUM><NUM> or corresponding memory cells <NUM><NUM> to <NUM><NUM> and a logic low signal to deselect fluid actuation devices <NUM><NUM> to <NUM><NUM> or corresponding memory cells <NUM><NUM> to <NUM><NUM>. In response to a logic high nozzle data signal, logic gate <NUM> passes a logic high signal to signal path <NUM> in response to a logic high fire signal. In response to a logic low nozzle data signal or a logic low fire signal, logic gate <NUM> passes a logic low signal to signal path <NUM>.

The address signal selects one of the fluid actuation devices <NUM><NUM> to <NUM><NUM> or corresponding memory cells <NUM><NUM> to <NUM><NUM>. In response to the address signal, one of the logic gates <NUM><NUM> to <NUM><NUM> passes a logic high signal to a corresponding signal path <NUM><NUM> to <NUM><NUM>. The other logic gates <NUM><NUM> to <NUM><NUM> pass a logic low signal to the corresponding signal paths <NUM><NUM> to <NUM><NUM>.

Each logic gate <NUM><NUM> to <NUM><NUM> passes a logic high signal to the corresponding signal path <NUM><NUM> to <NUM><NUM> in response to a logic high signal on signal path <NUM> and a logic high signal on the corresponding signal path <NUM><NUM> to <NUM><NUM>. Each logic gate <NUM><NUM> to <NUM><NUM> passes a logic low signal to the corresponding signal path <NUM><NUM> to <NUM><NUM> in response to a logic low signal on signal path <NUM> or a logic low signal on the corresponding signal path <NUM><NUM> to <NUM><NUM>. Accordingly, in response to a logic low memory enable signal and a logic high signal on a signal path <NUM><NUM> to <NUM><NUM>, the corresponding fluid actuation device <NUM><NUM> to <NUM><NUM> fires by activating the corresponding firing resistor <NUM>. In response to a logic high memory enable signal and a logic high signal on a signal path <NUM><NUM> to <NUM><NUM>, the corresponding memory cell <NUM><NUM> to <NUM><NUM> is selected for access.

With a memory cell <NUM><NUM> to <NUM><NUM> selected for access, memory write voltage regulator <NUM> may be enabled by a memory write signal on memory write signal path <NUM> to apply a voltage to signal path <NUM> to write a data bit to floating gate transistor <NUM>. In addition, with a memory cell <NUM><NUM> to <NUM><NUM> selected for access, transistors <NUM> and <NUM> may be turned on in response to a memory read signal on memory read signal path <NUM>. With transistors <NUM> and <NUM> turned on, the data bit stored in floating gate transistor <NUM> may be read through sense pad <NUM> (e.g., by a host print apparatus coupled to sense pad <NUM>). In one example, the memory write signal and the memory read signal are based on data stored in a configuration register, such as configuration register <NUM> of <FIG>. In another example, the memory write signal and the memory read signal are based on data received by circuit <NUM> along with the address and nozzle data, which is used by configuration logic, such as configuration logic <NUM> of <FIG>, to activate the read signal or the write signal.

<FIG> is a block diagram illustrating one example of an integrated circuit <NUM> to access a memory associated with a fluid ejection device. In this example, the fluid actuation devices may be located on an integrated circuit separate from the memory. Integrated circuit <NUM> includes a plurality of memory cells <NUM><NUM> to <NUM>N, an address decoder <NUM>, activation logic <NUM>, and configuration logic <NUM>. Each memory cell <NUM><NUM> to <NUM>N is electrically coupled to activation logic <NUM> through a signal path <NUM><NUM> to <NUM>N, respectively. Activation logic <NUM> is electrically coupled to address decoder <NUM>, to configuration logic <NUM> through a signal path <NUM>, and receives a fire signal through a fire interface <NUM>. Address decoder <NUM> receives a data signal through a data interface <NUM>. Each of the data interface <NUM> and the fire interface <NUM> may be a contact pad, a pin, a bump, a wire, or another suitable electrical interface for transmitting signals to and/or from integrated circuit <NUM>. Each of the interfaces <NUM> and <NUM> may be electrically coupled to a fluid ejection system (e.g., a host print apparatus).

In one example, each memory cell <NUM><NUM> to <NUM>N includes a non-volatile memory cell (e.g., a floating gate transistor, a programmable fuse, etc.). Address decoder <NUM> selects memory cells <NUM><NUM> to <NUM>N in response to an address, which may be received through data interface <NUM>. Activation logic <NUM> activates selected memory cells <NUM><NUM> to <NUM>N based on a data signal on data interface <NUM> and a fire signal on fire interface <NUM>. Configuration logic <NUM> enables or disables access to the plurality of memory cells <NUM><NUM> to <NUM>N.

<FIG> is a block diagram illustrating another example of an integrated circuit <NUM> to access a memory associated with a fluid ejection device. Integrated circuit <NUM> includes a plurality of memory cells <NUM><NUM> to <NUM>N, an address decoder <NUM>, and activation logic <NUM>. In addition, integrated circuit <NUM> includes a write circuit <NUM> and a configuration register <NUM>. In one example, configuration logic <NUM> of integrated circuit <NUM> of <FIG> includes configuration register <NUM>. Each memory cell <NUM><NUM> to <NUM>N is electrically coupled to write circuit <NUM> through a sense interface <NUM>.

Configuration register <NUM> may store data to enable or disable access to the plurality of memory cells <NUM><NUM> to <NUM>N. In addition, configuration register <NUM> may store data to enable write access or read access to the plurality of memory cells <NUM><NUM> to <NUM>N. Sense interface <NUM> provides a single interface coupled to each of the plurality of memory cells <NUM><NUM> to <NUM>N to connect to a single contact of a host print apparatus. In one example, sense interface <NUM> includes a single contact pad.

Data stored in memory cells <NUM><NUM> to <NUM>N may be read through sense interface <NUM> when the selected memory cells <NUM><NUM> to <NUM>N have been accessed by address decoder <NUM> and activation logic <NUM>. In addition, write circuit <NUM> may write data to selected memory cells <NUM><NUM> to <NUM>N when the selected memory cells <NUM><NUM> to <NUM>N have been accessed by address decoder <NUM> and activation logic <NUM>.

<FIG> illustrates one example of a fluid ejection die <NUM> and <FIG> illustrates an enlarged view of the ends of fluid ejection die <NUM>. In one example, fluid ejection die <NUM> includes integrated circuit <NUM> of <FIG>, integrated circuit <NUM> of <FIG>, or circuit <NUM> of <FIG>. Die <NUM> includes a first column <NUM> of contact pads, a second column <NUM> of contact pads, and a column <NUM> of fluid actuation devices <NUM>. The second column <NUM> of contact pads is aligned with the first column <NUM> of contact pads and at a distance (i.e., along the Y axis) from the first column <NUM> of contact pads. The column <NUM> of fluid actuation devices <NUM> is disposed longitudinally to the first column <NUM> of contact pads and the second column <NUM> of contact pads. The column <NUM> of fluid actuation devices <NUM> is also arranged between the first column <NUM> of contact pads and the second column <NUM> of contact pads. In one example, fluid actuation devices <NUM> are nozzles or fluidic pumps to eject fluid drops.

In one example, the first column <NUM> of contact pads includes six contact pads. The first column <NUM> of contact pads may include the following contact pads in order: a data contact pad <NUM>, a clock contact pad <NUM>, a logic power ground return contact pad <NUM>, a multipurpose input/output (i.e., sense) contact pad <NUM>, a first high voltage power supply contact pad <NUM>, and a first high voltage power ground return contact pad <NUM>. Therefore, the first column <NUM> of contact pads includes the data contact pad <NUM> at the top of the first column <NUM>, the first high voltage power ground return contact pad <NUM> at the bottom of the first column <NUM>, and the first high voltage power supply contact pad <NUM> directly above the first high voltage power ground return contact pad <NUM>. While contact pads <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are illustrated in a particular order, in other examples the contact pads may be arranged in a different order.

In one example, the second column <NUM> of contact pads includes six contact pads. The second column <NUM> of contact pads may include the following contact pads in order: a second high voltage power ground return contact pad <NUM>, a second high voltage power supply contact pad <NUM>, a logic reset contact pad <NUM>, a logic power supply contact pad <NUM>, a mode contact pad <NUM>, and a fire contact pad <NUM>. Therefore, the second column <NUM> of contact pads includes the second high voltage power ground return contact pad <NUM> at the top of the second column <NUM>, the second high voltage power supply contact pad <NUM> directly below the second high voltage power ground return contact pad <NUM>, and the fire contact pad <NUM> at the bottom of the second column <NUM>. While contact pads <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are illustrated in a particular order, in other examples the contact pads may be arranged in a different order.

Data contact pad <NUM> (e.g. data interface <NUM> of <FIG>) may be used to input serial data to die <NUM> for selecting fluid actuation devices (e.g., via select circuit <NUM> of <FIG>), memory bits (e.g., via select circuit <NUM> of <FIG>), thermal sensors, configuration modes (e.g. via configuration register <NUM> of <FIG>), etc. Data contact pad <NUM> may also be used to output serial data from die <NUM> for reading memory bits, configuration modes, status information, etc. Clock contact pad <NUM> may be used to input a clock signal to die <NUM> to shift serial data on data contact pad <NUM> into the die or to shift serial data out of the die to data contact pad <NUM>. Logic power ground return contact pad <NUM> provides a ground return path for logic power (e.g., about <NUM> V) supplied to die <NUM>. In one example, logic power ground return contact pad <NUM> is electrically coupled to the semiconductor (e.g., silicon) substrate <NUM> of die <NUM>. Multipurpose input/output contact pad <NUM> (e.g., sense interface <NUM> of <FIG> or sense pad <NUM> of <FIG>) may be used for analog sensing and/or digital test modes of die <NUM>. In one example, multipurpose input/output contact pad <NUM> may be electrically coupled to each memory cell <NUM><NUM> to <NUM>N, write circuit <NUM>, and sensor <NUM> of <FIG>.

First high voltage power supply contact pad <NUM> and second high voltage power supply contact pad <NUM> may be used to supply high voltage (e.g., about <NUM> V) to die <NUM>. First high voltage power ground return contact pad <NUM> and second high voltage power ground return contact pad <NUM> may be used to provide a power ground return (e.g., about <NUM> V) for the high voltage power supply. The high voltage power ground return contact pads <NUM> and <NUM> are not directly electrically connected to the semiconductor substrate <NUM> of die <NUM>. The specific contact pad order with the high voltage power supply contact pads <NUM> and <NUM> and the high voltage power ground return contact pads <NUM> and <NUM> as the innermost contact pads may improve power delivery to die <NUM>. Having the high voltage power ground return contact pads <NUM> and <NUM> at the bottom of the first column <NUM> and at the top of the second column <NUM>, respectively, may improve reliability for manufacturing and may improve ink shorts protection.

Logic reset contact pad <NUM> may be used as a logic reset input to control the operating state of die <NUM>. Logic power supply contact pad <NUM> may be used to supply logic power (e.g., between about <NUM> V and <NUM> V, such as <NUM> V) to die <NUM>. Mode contact pad <NUM> may be used as a logic input to control access to enable/disable configuration modes (i.e., functional modes) of die <NUM>. Fire contact pad <NUM> (e.g., fire interface <NUM> of <FIG>) may be used as a logic input to latch loaded data from data contact pad <NUM> and to enable fluid actuation devices or memory elements of die <NUM>.

Die <NUM> includes an elongate substrate <NUM> having a length <NUM> (along the Y axis), a thickness <NUM> (along the Z axis), and a width <NUM> (along the X axis). In one example, the length <NUM> is at least twenty times the width <NUM>. The width <NUM> may be <NUM> or less and the thickness <NUM> may be less than <NUM> microns. The fluid actuation devices <NUM> (e.g., fluid actuation logic) and contact pads <NUM>-<NUM> are provided on the elongate substrate <NUM> and are arranged along the length <NUM> of the elongate substrate. Fluid actuation devices <NUM> have a swath length <NUM> less than the length <NUM> of the elongate substrate <NUM>. In one example, the swath length <NUM> is at least <NUM>. The contact pads <NUM>-<NUM> may be electrically coupled to the fluid actuation logic. The first column <NUM> of contact pads may be arranged near a first longitudinal end <NUM> of the elongate substrate <NUM>. The second column <NUM> of contact pads may be arranged near a second longitudinal end <NUM> of the elongate substrate <NUM> opposite to the first longitudinal end <NUM>.

<FIG> illustrates an enlarged view of a central portion of a fluid ejection die 400a, as a further example of the fluid ejection die <NUM> of <FIG>. As previously described with reference to <FIG>, fluid ejection die 400a includes a plurality of nozzles <NUM> arranged in a column along the length of the elongate substrate <NUM>. In addition, fluid ejection die <NUM> includes a plurality of memory cells arranged in groups <NUM> adjacent to the plurality of nozzles <NUM>. As illustrated in <FIG>, each group <NUM> of memory cells may include a first memory cell <NUM><NUM> and a second memory cell <NUM><NUM>. Each memory cell <NUM> corresponds to a nozzle <NUM>. As previously described, fluid actuation logic of fluid ejection die <NUM> either ejects fluid from selected nozzles <NUM> or accesses memory cells <NUM> corresponding to the selected nozzles <NUM>.

In one example, each nozzle <NUM> of the plurality of nozzles has a corresponding memory cell <NUM>. In another example, every other nozzle <NUM> of the plurality of nozzles has a corresponding memory cell <NUM>. In another example, the plurality of memory cells may include a single memory cell <NUM> corresponding to each nozzle <NUM>. In another example, the plurality of memory cells includes at least two memory cells <NUM> corresponding to each nozzle <NUM>. The plurality of memory cells <NUM> may be arranged in a plurality of groups <NUM>, where each group <NUM> includes at least two memory cells <NUM>. The plurality of groups <NUM> are spaced apart from each other along the length of the elongate substrate <NUM>.

<FIG> illustrates an enlarged view of a central portion of a fluid ejection die 400b, as a further example of the fluid ejection die <NUM> of <FIG>. Fluid ejection die 400b includes a plurality of nozzles 408a arranged in a first column along the length of the elongate substrate <NUM> and a plurality of nozzles 408b arranged in a second column along the length of the elongate substrate <NUM>. The first column is adjacent to the second column. The nozzles 408a in the first column may be offset with respect to the nozzles 408b in the second column. In addition, fluid ejection die 400b includes a plurality of memory cells arranged in groups <NUM> adjacent to the plurality of nozzles 408a and 408b. The groups <NUM> are spaced apart from each other along the length of the elongate substrate <NUM>.

As illustrated in <FIG>, each group <NUM> may include six memory cells arranged in three banks <NUM><NUM> to <NUM><NUM>. The first bank <NUM><NUM> includes a first memory cell <NUM><NUM>-<NUM> and a second memory cell <NUM><NUM>-<NUM>. The second bank <NUM><NUM> includes a first memory cell <NUM><NUM>-<NUM> and a second memory cell <NUM><NUM>-<NUM>. The third bank <NUM><NUM> includes a first memory cell <NUM><NUM>-<NUM> and a second memory cell <NUM><NUM>-<NUM>. Each bank <NUM><NUM> to <NUM><NUM> may be selected in response to a bank enable signal on a bank enable signal path <NUM><NUM> to <NUM><NUM>, respectively.

In one example, the plurality of memory cells includes three memory cells <NUM> corresponding to each nozzle 408a and/or 408b. A first memory cell (e.g., memory cell <NUM><NUM>-<NUM>) corresponding to each nozzle is arranged in a first bank (e.g., bank <NUM><NUM>) of memory cells, a second memory cell (e.g., memory cell <NUM><NUM>-<NUM>) corresponding to each nozzle is arranged in a second bank (e.g., bank <NUM><NUM>) of memory cells, and a third memory cell (e.g., memory cell <NUM><NUM>-<NUM>) corresponding to each nozzle is arranged in a third bank (e.g., bank <NUM><NUM>) of memory cells. The fluid actuation logic either ejects fluid from the selected nozzles 408a and/or 408b or accesses memory cells <NUM> corresponding to the selected nozzles and a selected bank of memory cells.

In one example, the bank one, bank two, and bank three enable signals are based on data stored in a configuration register, such as configuration register <NUM> of <FIG>. In another example, the bank one, bank two, and bank three enable signals are based on data received by fluid ejection die 400b along with the address and nozzle data, which is used by configuration logic, such as configuration logic <NUM> of <FIG>, to enable a selected bank <NUM><NUM> to <NUM><NUM>.

<FIG> is a block diagram illustrating one example of a fluid ejection system <NUM>. Fluid ejection system <NUM> includes a fluid ejection assembly, such as printhead assembly <NUM>, and a fluid supply assembly, such as ink supply assembly <NUM>. In the illustrated example, fluid ejection system <NUM> also includes a service station assembly <NUM>, a carriage assembly <NUM>, a print media transport assembly <NUM>, and an electronic controller <NUM>. While the following description provides examples of systems and assemblies for fluid handling with regard to ink, the disclosed systems and assemblies are also applicable to the handling of fluids other than ink.

Printhead assembly <NUM> includes at least one printhead or fluid ejection die <NUM> previously described and illustrated with reference to <FIG>, which ejects drops of ink or fluid through a plurality of orifices or nozzles <NUM>. In one example, the drops are directed toward a medium, such as print media <NUM>, so as to print onto print media <NUM>. In one example, print media <NUM> includes any type of suitable sheet material, such as paper, card stock, transparencies, Mylar, fabric, and the like. In another example, print media <NUM> includes media for three-dimensional (3D) printing, such as a powder bed, or media for bioprinting and/or drug discovery testing, such as a reservoir or container. In one example, nozzles <NUM> are arranged in at least one column or array such that properly sequenced ejection of ink from nozzles <NUM> causes characters, symbols, and/or other graphics or images to be printed upon print media <NUM> as printhead assembly <NUM> and print media <NUM> are moved relative to each other.

Ink supply assembly <NUM> supplies ink to printhead assembly <NUM> and includes a reservoir <NUM> for storing ink. As such, in one example, ink flows from reservoir <NUM> to printhead assembly <NUM>. In one example, printhead assembly <NUM> and ink supply assembly <NUM> are housed together in an inkjet or fluid-jet print cartridge or pen. In another example, ink supply assembly <NUM> is separate from printhead assembly <NUM> and supplies ink to printhead assembly <NUM> through an interface connection <NUM>, such as a supply tube and/or valve.

Carriage assembly <NUM> positions printhead assembly <NUM> relative to print media transport assembly <NUM>, and print media transport assembly <NUM> positions print media <NUM> relative to printhead assembly <NUM>. Thus, a print zone <NUM> is defined adjacent to nozzles <NUM> in an area between printhead assembly <NUM> and print media <NUM>. In one example, printhead assembly <NUM> is a scanning type printhead assembly such that carriage assembly <NUM> moves printhead assembly <NUM> relative to print media transport assembly <NUM>. In another example, printhead assembly <NUM> is a non-scanning type printhead assembly such that carriage assembly <NUM> fixes printhead assembly <NUM> at a prescribed position relative to print media transport assembly <NUM>.

Service station assembly <NUM> provides for spitting, wiping, capping, and/or priming of printhead assembly <NUM> to maintain the functionality of printhead assembly <NUM> and, more specifically, nozzles <NUM>. For example, service station assembly <NUM> may include a rubber blade or wiper which is periodically passed over printhead assembly <NUM> to wipe and clean nozzles <NUM> of excess ink. In addition, service station assembly <NUM> may include a cap that covers printhead assembly <NUM> to protect nozzles <NUM> from drying out during periods of non-use. In addition, service station assembly <NUM> may include a spittoon into which printhead assembly <NUM> ejects ink during spits to ensure that reservoir <NUM> maintains an appropriate level of pressure and fluidity, and to ensure that nozzles <NUM> do not clog or weep. Functions of service station assembly <NUM> may include relative motion between service station assembly <NUM> and printhead assembly <NUM>.

Electronic controller <NUM> communicates with printhead assembly <NUM> through a communication path <NUM>, service station assembly <NUM> through a communication path <NUM>, carriage assembly <NUM> through a communication path <NUM>, and print media transport assembly <NUM> through a communication path <NUM>. In one example, when printhead assembly <NUM> is mounted in carriage assembly <NUM>, electronic controller <NUM> and printhead assembly <NUM> may communicate via carriage assembly <NUM> through a communication path <NUM>. Electronic controller <NUM> may also communicate with ink supply assembly <NUM> such that, in one implementation, a new (or used) ink supply may be detected.

Electronic controller <NUM> receives data <NUM> from a host system, such as a computer, and may include memory for temporarily storing data <NUM>. Data <NUM> may be sent to fluid ejection system <NUM> along an electronic, infrared, optical or other information transfer path. Data <NUM> represent, for example, a document and/or file to be printed. As such, data <NUM> form a print job for fluid ejection system <NUM> and includes at least one print job command and/or command parameter.

In one example, electronic controller <NUM> provides control of printhead assembly <NUM> including timing control for ejection of ink drops from nozzles <NUM>. As such, electronic controller <NUM> defines a pattern of ejected ink drops which form characters, symbols, and/or other graphics or images on print media <NUM>. Timing control and, therefore, the pattern of ejected ink drops, is determined by the print job commands and/or command parameters. In one example, logic and drive circuitry forming a portion of electronic controller <NUM> is located on printhead assembly <NUM>. In another example, logic and drive circuitry forming a portion of electronic controller <NUM> is located off printhead assembly <NUM>.

Claim 1:
An integrated circuit comprising:
an elongate substrate (<NUM>) having a length, a thickness, and a width, the length being at least twenty times the width, wherein on the elongate substrate there is provided:
a plurality of nozzles (<NUM>) arranged in a column along the length of the elongate substrate,
a plurality of memory cells (<NUM>) arranged adjacent to the plurality of nozzles, each memory cell corresponding to a nozzle, and
fluid actuation logic (<NUM>) to either eject fluid from selected nozzles or access memory cells corresponding to the selected nozzles.