Patent Description:
Various device testing may be performed by loading test data onto a chip from external testing equipment. The data may be stored into test registers. After tests have been performed the test results may be stored in test registers and output to the external testing equipment for comparing the actual test results with expected results. Moving this comparison onto the chip can save time in the testing process. As chips become more and more complex the need to perform these tests quickly also becomes more and more desirable. Document <CIT> features an integrated circuit that includes a first input port configured to receive a test pattern, a second input port configured to receive a signature pattern, a set of interconnected circuit elements, and a comparison circuit. The signature pattern is indicative of an expected test output pattern in response to the test pattern. The set of interconnected circuit elements is configured to generate a test output pattern in response to the test pattern being passed through the set of interconnected circuit elements. The comparison circuit is configured to compare the test output pattern to the signature pattern, generate a test result based on a comparison result of the test output pattern to the signature pattern, and output the test result to the test apparatus. Further prior art can be found in <CIT> and <CIT>.

The present invention solves the above mentioned problem by a method according to claim <NUM>, a corresponding device in claim <NUM> and a system to test a chip according to claim <NUM>. Additional non-claimed embodiments, aspects or examples are also presented in the description for the better understanding of the invention.

In accordance with embodiments, a method for testing a chip with an on-chip comparator comprises receiving, by the chip, N scan-in chains of test data from an off-chip test equipment, N being an integer; using the N scan-in chains of test data to perform tests on the chip that produce test results; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being an integer less than <NUM>*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results; for each decoded output signal comprising an expected test result, using the on-chip comparator to compare the decoded output signal with the respective chain of test results for that decoded output signal; and for each decoded output signal comprising a masking condition, masking from comparison the respective test chain of test results for that decoded output signal.

In accordance with embodiments, a chip with an on-chip comparator comprises N input pins configured to receive N scan-in chains that comprise test data, N being an integer; a plurality of scan-chain test registers configured to store test data from the N scan-in chains for on-chip tests and to store results from on-chip tests; decoding logic configured to receive a merged test-result and masking-instruction signal from X input pins and output N decoded output signals decoded from the merged test-result and masking-instruction signal wherein X is an integer less than <NUM>*N; and wherein the on-chip comparator is coupled with the plurality of scan-chain test registers to receive test results from the plurality of scan-chain test registers and wherein the on-chip comparator is coupled with the decoding logic to receive the N decoded output signals, the on-chip comparator being configured to compare each of the N decoded output signals comprising an expected test result with a respective test result chain and configured to mask from comparison each of the N decoded output signals comprising a mask instruction.

In accordance with embodiments, a system to test a chip comprises an off-chip test equipment; N input pins coupled with the off-chip test equipment to receive N scan-in chains that comprise test data, N being an integer; a plurality of scan-chain test registers configured to store test data from the N scan-in chains for on-chip tests and to store results from on-chip tests; decoding logic configured to receive a merged test-result and masking-instruction signal from X input pins and output N decoded output signals decoded from the merged test-result and masking-instruction signal wherein X is an integer less than <NUM>*N, the X input pins being coupled with the off-chip testing equipment; and an on-chip comparator is coupled with the plurality of scan-chain test registers to receive test results from the plurality of scan-chain test registers and wherein the on-chip comparator is coupled with the decoding logic to receive the N decoded output signals, the on-chip comparator being configured to compare each of the N decoded output signals comprising an expected test result with a respective test result chain and configured to mask from comparison each of the N decoded output signals comprising a mask instruction.

Inputs are used to load data onto a chip to perform on chip testing. The data may be provided by off chip testing equipment such as Automatic Testing Equipment (briefly, ATE). The data, or test patterns, is/are loaded serially onto the chip using input pins for the chip. The data is stored on test registers where it can be provided to on-chip components for testing purposes. Data may be input into a device under test as a scan chain and stored on a corresponding test register or corresponding test registers. After tests are performed, the results are stored in test registers. Known systems and devices output the data via output pins to the external test equipment (such as an ATE) where the test results may be compared with expected results to determine whether the chip is functioning as desired.

<FIG> shows a chip comprising a known scan-in and scan-out architecture for performing on-chip tests.

The chip <NUM> includes a number of inputs to receive a compressed data signal that is decompressed and loaded into scan chains for the chip. The chip <NUM> may include a first input <NUM>, a second input <NUM>, and an Nth input <NUM>. Data (scan-in chains) received at the inputs may be provided to decompressor logic <NUM> where the compressed signal is expanded. Each pin may receive a scan-in chain. The expanded data may then be provided to a number of test registers. A first test register <NUM> may receive a first section of data, a second register may receive a second section of data and so forth. An Nth test register <NUM> may receive an Nth section of data. The registers may be loaded in parallel in a serial manner meaning each register may receive one bit per cycle.

Once the test registers are loaded, the data may be supplied to other components on the chip <NUM> for testing. The results of the test may then be stored in the test registers. The first test register <NUM> may store a first section of test results, a second test register (not shown in <FIG>) may store a second section of test results and so forth. The Nth test register <NUM> may store an Nth section of test results.

The results of the tests may be provided to compressor logic <NUM>. The data may be compressed into scan-out chains. The number of scan-out chains may correspond to the number of scan in chains. The scan-out chains are then be provided to output pins for transmission to off-chip testing equipment such as automatic testing equipment. The chip <NUM> includes a first output <NUM>, a second output <NUM>, and so on up to an Nth output <NUM> to output the scan-out chains.

Once the compressed output data is received by the off-chip testing equipment the test results may be evaluated. This can be accomplished by comparing the results with expected results. When the test results do not match the expected results it can be determined that the chip is not performing as expected.

Achieving higher scan compression and test efficiency is an ever increasing goal. Faster testing can allow faster production, decrease cost and increase revenue. Further, new fault models for higher quality, such as small-delay defect testing, cell aware testing and others, inflate the scan-volume significantly. And, the impact made by growing test times is multiplicative because test time is a recurring cost for each device shipped. Faster solutions are thus desirable to allow faster testing. The time used to perform a test on a chip may be described by Equation <NUM>.

In equation one, the chain length is the number of bits of a test pattern. The shift frequency is the rate that bits of data can be input and output from a device under test. And, as indicated by the name, the number of patterns is the number of patterns loaded onto a chip for testing.

As will be appreciated, the cost of a test is a function of the test time. Thus, reducing the test time can reduce the test cost. Further, reducing test time can hasten the device-production time allowing more chips to be prepared thereby driving up revenue and relieving shortages.

The variables from Equation <NUM> that drive the test cost may depend on different factors. The chain length and the number of patterns may be related to the number of pins available for loading data. With more pins available, the length of the chains may be reduced. More pins also reduces the number of patterns needed. As will be appreciated, greater pin availability allows decompression and compression logic to perform better thus reducing the number of patterns used to perform tests. The shift frequency is limited by the speed of the scan out from the chip to the off-chip testing equipment. The scan outs have a load on the external tester, which drives the external logic (on an ATE, for example). The external load also has a capacitance that slows how fast the scan outs can travel. This contrasts with scan in because scan in supports logic sitting internally on the chip so it is easier to shift data in for the local load. As a result, the scan in is faster than scan out, and scan out bottlenecks the process. In some cases, scan in may be two or three times as fast as scan-out.

Embodiments of the present disclosure leverage the relative speed advantage provided by scan in and increase the number of pins available for scanning. This provides improved reductions in test time by addressing the variables driving test time and thus test cost.

<FIG> depicts an on-chip comparison system with smart masking in accordance with embodiments of the present invention.

The on-chip comparison system <NUM> may comprise a chip <NUM> or other electronic device. As will be appreciated, it may be advantageous to perform various functionality, performance, quality, or stress tests for the chip <NUM> (or other electronic device under test). Testing may be performed in conjunction with off-chip testing equipment <NUM> (or off device) such as an ATE. An ATE may provide test data to the chip <NUM> using input pins. A first input pin <NUM> may receive a first scan-in chain. As will be appreciated, various embodiments may comprise more input pins. Additional input pins may receive additional scan-in chains from off-chip testing equipment <NUM>. The more pins utilized for inputting data, more scan-in chains may be provided, the length of the scan-in chains may be reduced and the faster data may be input. The chip <NUM> may further comprise a clock input <NUM> to receive a clock signal. The clock signal may be received from the off-chip test equipment <NUM>.

Scan-in chains received at the inputs maybe in a compressed form. Decompression logic may expand data signals received from the input pins. As will be appreciated the number of internal data streams available to be extracted from a data signal received from off-chip testing equipment may depend on the number of pins accessible to transfer the data. For simplicity, decompressor logic is not depicted in <FIG>.

Data received through the input pins may be provided to test registers on the chip <NUM>. For example, a first test register <NUM> may receive a section of scan-in data. Various embodiments may comprise different number of test registers for receiving different numbers of scan-in chains. As will be appreciated, multiple test registers may be used for each scan-in chain because each scan-in chain may be expanded by the decompression logic. As already referenced, the number of scan-in chains available may depend on the number of pins accessible for receiving data from off-chip test equipment (such as an ATE).

The first test register <NUM> may comprise a number of flip flop for storing data received. Different numbers of flip flops may be used in different embodiments. The number of flip flops for the test registers may depend on the length of the scan-in chain.

As will be appreciated, data may be loaded serially into the test registers. On each cycle of a clock signal (for example, clock signal received at clock input <NUM>), one bit of data may be loaded into each test register. In embodiments, with multiple test registers, each register may be serially loaded in parallel. For example, in an embodiment with <NUM> test registers each of the <NUM> test registers may be loaded with one bit of data on a first cycle. Additional bits may be loaded and shifted in accordance with scan-shift operations. Using the first test register as an example, on a first cycle data may be loaded into a first flip 208A of the first test register <NUM>. On a second cycle, data may be shifted to a second flip flop. Data may continue to be shifted until an Nth flip flop 208B of the first test register is filled. Additional test registers may also be loaded simultaneously in the same way.

Once test data is loaded into the test registers, the data stored in the test registers may be used for performing different tests for the chip. For example, the data may be used to test for stuck-at faults for the chip's internal logic circuitry. Data from the test registers may be carried to other parts of the chip <NUM> using internal logic <NUM>. This may be performed using scan load, unload and capture operations.

As will be appreciated, the test registers may comprise input and output shift modes for shifting data and out serially. The test registers may also comprise parallel in and parallel out modes for loading data in and out of all the flip flops of a test register in parallel. Once loaded with data from the off-chip testing equipment (such as an ATE), the data from the test registers may output data from the flip flops in parallel to perform testing operations. When tests are complete, the results may be loaded into the test registers. Test-result data may be loaded into the test registers in parallel.

In various embodiments, the chip <NUM> may comprise a comparator <NUM>. The comparator <NUM> may be used to compare expected test results for the test operations with the actual test results. The comparator may be in communication with the test registers, such as the first test register and any additional test registers, to receive the test-result data from the test registers after test-result data has been loaded into the test register. In various embodiments, compressor logic may compress the data from the test registers before it is provided to the comparator <NUM>. The comparator may thus receive scan-out chains. The test registers may operate in a shift mode to output the test results serially to the compression logic and then to the comparator <NUM>. Compression logic is not depicted in <FIG> for simplicity.

The comparator <NUM> may receive the expected test results from off-chip test equipment. As will be appreciated, there may be situations where a comparison of one or more bits of data may not be desired. It may be desirable to mask a comparison when there is some uncertainty about data captured for the relevant cycle or the data may not be valid for any number of possible reasons. Timing exceptions provide one possible example where this may be the case.

Data input from the off-chip testing equipment (such as an ATE) for comparison with the test results may comprise one of three states: high state, low state, or a masked state. As will be readily appreciated, more than one binary pin is needed to carry three-states of information for each scan chain.

Using a three scan-chain embodiment as an example, each of the three scan chains may comprise a high state or low state depending on the expected result or a masked state. The state may be determined by a signal received from the off-chip testing equipment. A signal for three three-state scan chains cannot be carried in one cycle on three pins. And, using two pins for each scan chain (a total of six pins) consumes pin resources that could otherwise be used to load scan-in data and expedite test time. The number of pins used to carry these three states can be reduced by encoding expected result data with the masking data on shared pins. For example, three scan chains with three possible states yields <NUM> possible combinations for the three scan chains. Using a merged expected test-result and masking-instruction signal this data may be transmitted using only five pins (rather than six). Decoding logic can then be used to extract the appropriate data or masking signal. And, the extra pin may be used for another purpose. The more scan chains the more advantageous this approach becomes because more pins may be saved for other uses.

The chip <NUM> may comprise an (e.g., first) input pin <NUM> and an (e.g., second) input pin <NUM>. Expected test results may be loaded on the chip <NUM> from the (e.g., first) data input pin <NUM>. As will be appreciated, various embodiments may comprise additional input pins and additional masking pins for inputting a merged expected test-result and masking-instruction signal. For example, for the example described in the previous paragraph, five pins may be utilized to receive a merged expected test-result and masking-instruction signal The merged expected test-result and masking-instruction signal may be provided to decoding logic <NUM>. The decoded expected results may be provided to the comparator <NUM> for comparison with the actual test results when the expected test results are not masked. As will be appreciated, masking may be accomplished by translating received data in constant value using AND/OR gating.

Results of the comparisons may be output at an output port <NUM>. Using a comparator <NUM> on the chip <NUM> to perform comparisons of the expected results with the actual test results may reduce the number of output pins needed output data. This is accomplished by using input pins to transmit the expected test-result data onto the chip <NUM> rather than using output pins to transmit the actual results to off-chip testing equipment (such as an ATE). For example, results from <NUM> (twenty or more) scan chains may be output by a single output port rather than <NUM> (twenty or more) output ports. This trade leverages the speed advantage that the input pins have over output pins so overall test-time speed is increased. And, using a merged expected test-result and masking-instruction signal to transmit data on shared pins frees up additional pins rather than having dedicated pins for masking and expected test results.

As previously referenced, the chip <NUM> may comprise additional registers and inputs. <FIG> depicts a chip <NUM> comprising three test registers. This is but one example, and a chip <NUM> may have any number of test registers in various embodiments. As will be appreciated, the number of test registers in a chain may depend on the number of inputs reserved for scan-in chain and the expansion capabilities of any decompression logic.

As depicted in <FIG>, the chip <NUM> may comprise a second test register <NUM>, and a third test register <NUM>. The second test register <NUM> may be loaded with test data for a second scan in chain. The third test register <NUM> may be loaded with data from a third scan-in chain. It should be appreciated that in various embodiments multiple test registers may be used to store data from a single scan-in chain (or input) due to decompression logic (not depicted in <FIG>). For example, additional test registers may also store data from the first scan chain, second scan chain, and third scan chain.

Once loaded into test registers, the data may be used to perform tests on the chip <NUM>. Results from second scan chain may be stored on the second test register <NUM>. Results from the scan chain may be stored on the third test register <NUM>. The second test register <NUM> and the third test register <NUM> may be loaded serially and test results may be output serially to the comparator <NUM>. For performing tests on the chip <NUM>, the second test register <NUM> and the third test register <NUM> may be output in parallel and loaded with test results. The second test register <NUM> and third test register <NUM> may each also comprise any number of flip flops for storing data. The chip <NUM> may comprise any number of additional test registers, as will be appreciated.

The chip <NUM> may comprise a second input <NUM> and a third input <NUM>. As will be appreciated, the chip <NUM> may comprise additional inputs in various embodiments. The second input <NUM> may receive a second scan-in chain and provide test data from off-chip test equipment (such as an ATE) to the second test register <NUM>. The third input <NUM> may receive a third scan-in chain and provide test data from off-chip test equipment (such as an ATE) to the third test register <NUM>. It should also be appreciated that the chip <NUM> may comprise decompression logic and compression logic (not depicted in <FIG>) to expand scan-in chains before test is provided to the test registers and to compress test-result data before it is provided to a comparator <NUM>. Accordingly, the number of test registers loaded with test data may be greater the number of inputs used to receive the data from off-chip test equipment (such as an ATE). <FIG> omits depicting a clock signal for simplicity. However, it should be appreciated that the chip <NUM> may comprise an input to receive a clock signal, or clock signals, that are carried to on chip components (such as the test registers).

Test results stored in the first test register <NUM>, second test register <NUM>, and third test register <NUM> may be provided to the comparator <NUM>. The results may be compressed in scan-out chains using compression logic (not depicted in <FIG>) before they are provided to the comparator. Expected results for the scan out chains received by the comparator may be loaded from off-chip test equipment (such as an ATE). Data for masking comparisons may also be loaded from off chip test equipment (such as an ATE).

In various embodiments a merged signal comprising the expected results and masking indicators for the test chains may be received from off-chip test equipment <NUM> using the same input pins. As will be appreciated, the number of pins used to transmit a merged signal comprising expected results and masking indications may depend on the number of scan-out chains for which comparison is desired.

As depicted in <FIG>, data from five input pins may be provided the decoding logic <NUM> to provide expected results and masking indicators to allow on-chip comparisons for three scan-out chains of test results. Decoding logic <NUM> may be coupled with comparator <NUM> and provide an output to the comparator <NUM> that depends on the merged signal received by the decoding logic <NUM>. A first decoded output <NUM> of the decoding logic <NUM> may be provided to the comparator <NUM>. A second decoded output <NUM> of the decoding logic <NUM> may be provided to the comparator <NUM>. A third decoded output <NUM> of the decoding logic <NUM> may be provided to the comparator <NUM>.

The decoding logic <NUM> may receive inputs from five input pins. For example, (e.g., first) data input pin <NUM>, (e.g., second) data input pin <NUM>, (e.g., third) data input pin <NUM>, (e.g., fourth) data input pin <NUM>, and (e.g., fifth) data input pin <NUM>. In various embodiments, any number of input pins may be used to receive merged expected test-result and masking-instruction signal and provide it to decoding logic <NUM>.

Each of the first decoded output <NUM>, the second decoded output <NUM>, and the third decoded output <NUM> may comprise one of three states. The three states may include a "high" state, a "low" state, and a "mask" state. The state may depend on the merged expected test-result and masking-instruction signal received by the decoding logic <NUM>.

As will be appreciated, there may be additional three-state decoded outputs in various embodiments. The decoder logic <NUM> may comprise a three-state decoded output for each scan-out chain so that each scan-out chain is masked or compared with an expected test result for the corresponding scan-out chain (either "high" or "low). The merged expected test-result and masking-instruction signal may be received by the chip <NUM> by less than <NUM>*N inputs, where N is the number of scan-out chains of test results received by comparator <NUM>.

Using a merged expected test-result and masking-instruction signal carried on shared pins allows more efficient use of the data pins to encode the three-state of outputs used to transmit expected results and masking indications to the comparator <NUM>. As referenced earlier in this disclosure, a signal for three three-state outputs may be carried on five binary input pins (for example, data input pin <NUM>, data input pin <NUM>, data input pin <NUM>, data input pin <NUM> and data input pin <NUM>). The <NUM> possible states for the data signals having one of three states may be described with five binary inputs.

<FIG> depicts an example table mapping five binary input states to data having one of three states. The scan-out values of Table <NUM> may correspond the decoded outputs of <FIG>. For example, SO_0 of Table <NUM> may correspond to the first decoded output <NUM>, SO_1 of Table <NUM> may correspond to the second decoded output <NUM>, and SO_2 of Table <NUM> may correspond to the third decoded output <NUM>. For the purposes of Table <NUM>, a "<NUM>" may correspond to a low state for an expected test result, a "<NUM>" may correspond to a high state, and an "M" may correspond to a mask state. The cells for scan pins from Table <NUM> relate to encoded data loaded through scan-pins as inputs. The cells for scan pins from Table <NUM> may correspond to input pins of <FIG>. For example, RSI0 may correspond to data input pin <NUM>, RS1 may correspond to data input pin <NUM>, RS2 may correspond to data input pin <NUM>, RS3 may correspond to data input pin <NUM>, and RS4 may correspond to data input pin <NUM>.

As will be appreciated, and as demonstrated by Table <NUM>, all <NUM> (twenty-seven) possible states of the decoded outputs may be corresponded one of the thirty-two possible states allowed by five input pins. Various embodiments may use more input pins for providing expected results and masking instructions for more test chains. The number of pins for encoding a merged expected test-result and masking-instruction signal may be describe by Equation <NUM>, below.

In Equation <NUM>, input pins refer to the number of pins for receiving the merged expected test-result and masking-instruction signal. ScanOuts refers to the number of three-state outputs from the decoding logic <NUM>, which as will be appreciated may be equal to the number of scan-out chains of test results received by comparator <NUM>. It should also be appreciated that more than one output pin may be used for carrying decoded output data that may comprise one of three states. And, the function ceiling[*] maps the value * to the least integer greater than or equal to *. For example where * = <NUM>, ceiling[*] is equal to <NUM>. The number of input pins, thus, may depend on the number three-state outputs desired. Using Equation <NUM>, <NUM> input pins may be used for receiving a merged expected test-result and masking-instruction signal for <NUM> scan chains.

It will be appreciated, that the decoding logic <NUM> may be implemented in differently in various embodiments. For example, the decoding logic <NUM> may be implemented with a circuit of logic gates.

The outputs from the decoding logic <NUM> may be compared with actual test results from the test registers using the comparator <NUM>. For example, if the first decoded output <NUM>, second decoded output <NUM>, and third decoded output <NUM> comprises expected test results (high or low) they may be compared with actual test results received by the comparator. The expected result from the first decoded output <NUM> may be compared with the actual result from a first scan-out chain <NUM>. The expected result from the second decoded output <NUM> may be compared with the actual result from a second scan-out chain <NUM>. The expected result from the third decoded output <NUM> may be compared with the actual result from a third scan out chain <NUM>. In various embodiments additional decoded outputs comprising expected test results may be compared with actual test results from scan-out chains. As will be appreciated, the output from test registers (such as the first test register <NUM>, second test register <NUM>, third test register <NUM>, and additional test registers) may be compressed into scan-out chains that are transmitted to the comparator <NUM>. When a decoded output comprises a mask state, the comparison may be masked.

The chip <NUM> may comprise an output port <NUM>. The output port <NUM> may comprise a single bit. The output port <NUM> may output the results of the comparison done by the comparator <NUM>. For example, a signal provided to the output port <NUM> from the comparator <NUM> may be asserted when expected test results (communicated via decoder logic <NUM>) match the actual test results (received from test registers). It will be appreciated that a signal may be de-asserted when expected test results do not match actual test results. In various embodiments, results from a comparison may be output every cycle a comparison is made.

In various embodiments, the comparator <NUM> may comprise a memory 210A. The memory may store the results of comparisons made by the comparator <NUM>. For example, the memory 210A may comprise a shift register. The memory 210A may comprise flip flops to store comparison results. Results of each comparison maybe accumulated in the memory 210A. As will be appreciated, test results may be output in different ways or at different times in various embodiments. For example, comparisons from each chain may be output each cycle, once per pattern, or after all tests have been completed. In various embodiments, results from all chains may be aggregated and output once per cycle, once per pattern, or after all tests have been performed. In various embodiments, results may be output after a specified number of comparisons have been performed. In various embodiments, comparison results may be stored on a per-pattern basis. For example, a single bit of memory may indicate if the expected results for a full pattern match the actual results for the full pattern. In various embodiments, the comparator may store results for each individual scan-out chain or store the results of multiple comparisons for each scan out chain. In various embodiments, the comparator may only store a single result for the combined comparison of all the scan chains.

A count of the number of cycles, patterns or other means to track the progression of the tests may be reset after the results are output. Comparison results may then be automatically output each time the count reaches a desired threshold (patterns, cycles, or any other means to track progression of tests) and reset again. In other embodiments, comparison results stored in memory 210A may be output in response to an output directly received from off-chip equipment (such as an ATE) or an on-chip component.

It will be appreciated that the comparator <NUM> may comprise numerous different forms. For example, in various embodiments, the comparator may comprise individual comparators for each scan chain that are configured to receive a scan-out chain and a decoded output from the decoder logic <NUM>. In various embodiments, the comparator may comprise a single comparator that receives all the scan-out chains and all the decoded outputs from the decoder logic <NUM>. <FIG> depicts an on-chip comparison system with smart masking in accordance with embodiments of the present invention.

In various embodiments, the chip <NUM> may comprise a first merged input <NUM>, a second merged input <NUM>, and an Nth merged input <NUM>. The merged inputs may receive the merged expected test-result and masking-instruction signal from off-chip test equipment <NUM>.

As will be appreciated, a plurality of devices may be tested simultaneously with one off-chip test equipment.

<FIG> depicts a system for testing a plurality of chips.

The system <NUM> may comprise off-chip test equipment <NUM> coupled with a plurality of devices under test, each of which may comprise a chip <NUM>. The off-chip test equipment <NUM> may send data to each of the devices under test to perform test operations. The off-chip test equipment <NUM> may also provide expected result data and masking indications to the devices under test, each of which may comprise a chip <NUM>. Test results may be compared with expected results on the devices under test. And, each device under test, each of which may comprise a chip, may output the results to the off-chip test equipment. Output for each device under test may comprise a single bit while the inputs may comprise multiple channels of data. As will be appreciated, input data may be broadcast to multiple chains using the same input data for each chip being tested. Access to more inputs due to single-bit outputs thus allows more devices to be tested using a single ATE.

<FIG> depicts a method for testing a chip with an on-chip comparator in accordance with embodiments.

In various embodiments, the method <NUM> comprises at a step <NUM>, receiving, by the chip, N scan-in chains of test data from an off-chip test equipment, N being an integer; at a step <NUM>, using the N scan-in chains of test data to perform tests on the chip that produce test results; at a step <NUM>, receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being an integer less than <NUM>*N; and at a step <NUM>, decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

In various embodiments, the method <NUM> may further comprise, for each decoded output signal comprising an expected test result, using the on-chip comparator to compare the decoded output signal with the respective chain of test results for that decoded output signal.

In various embodiments, the method <NUM> may further comprise for each decoded output signal comprising a masking condition, masking from comparison the respective test chain of test results for that decoded output signal.

In various embodiments, the method <NUM> may further comprise decompressing the N scan-in chains and serially loading a plurality of test registers with test data extracted from the N scan-in chain.

In various embodiments, the method <NUM> may further comprise storing results from test results in the plurality of test registers.

In various embodiments, the method <NUM> may further comprise compressing test results output from the test registers into N chains of test results.

In various embodiments, the method <NUM> may further comprise setting the integer X to a least integer greater than or equal to log<NUM>(<NUM>^(N)).

In various embodiments, the method <NUM> may further comprise using a single bit output comparison results.

In various embodiments, the method <NUM> may further comprise storing comparison results on the chip.

In various embodiments, the method <NUM> may further comprise outputting comparison results after a set number of comparisons have been made.

In various embodiments, the method <NUM> may further comprise, wherein each of the N decoded output signals comprises data having one of three states In various embodiments, the method <NUM> may further comprise, wherein the merged expected test-result and masking-instruction signal is received from the off-chip testing equipment.

In various embodiments, the method <NUM> may further comprise outputting comparison results to the off-chip test equipment.

<FIG> depicts a comparator consistent with embodiments.

In various embodiments, the comparator <NUM> may comprise an input <NUM> to receive test-data results. This may be received directly from test registers. In various embodiments test data results may be received from compression logic, such as compressor logic <NUM>. For simplicity, <FIG> only depicts a single input for receiving test results, but the comparator may receive any number of results. The number of inputs of the comparator <NUM> for receiving test data results may correspond to the number of scan chains being compared.

The comparator <NUM> may comprise an input <NUM> to receive decoded expected test results. This may originate from decoding logic <NUM>. For example, the first decoded output <NUM>. Again, as appreciated, the comparator <NUM> may also comprise additional inputs to receive decoded expected results and masking indications for additional comparisons (scan chains).

The test results received at input <NUM> and the expected result received at input <NUM> may be provided to an XOR gate <NUM>. The masking indicator received at input <NUM> may be provided to an AND gate <NUM> along with an output of the XOR gate <NUM>. As will be appreciated the comparator may also comprise additional XOR gates for receiving expected test results and actual test results from additional scan chains and additional AND gates for receiving additional masking inputs. Results may be aggregated, in various embodiments, for example with an OR gate <NUM>. An input <NUM> may carry comparison results from a first scan chain. An input <NUM>, may carry comparison results from an Nth scan chain. This may allow the output of the OR gate <NUM> to be asserted if expected results from any scan chain deviate from actual test results. Output from the OR gate <NUM> may be provided to a memory 210A, which may comprise a flip flop. ** Output of the flip flop may also be fed back to the OR gate <NUM> so that once a deviation is detected the output may be maintained until the flip flop is reset. This allows all results to be tracked by a single flip flop. As will be appreciated, <FIG> depicts but one example of comparator <NUM> and other architectures may be used in various embodiments. A comparator output <NUM> may provide results of comparisons. For example, the comparator output <NUM> may be coupled with output port <NUM>.

<FIG> depicts a flow chart for a method for a design for testability flow in accordance with embodiments.

At a step <NUM>, the method comprises planning for the number of channels for a chip (such as chip <NUM>). For instance, at the step <NUM> the method comprises to plan total scan channels. At a step <NUM>, the method <NUM> comprises implementing pin-muxing with N inputs and R merged inputs. The N inputs may correspond to the inputs for carrying the scan chain test data. For example, input pin <NUM>. The R merged inputs may correspond to inputs that carry a merged expected test-result and masking-instruction signal. For example, input pin <NUM>, input <NUM>, etc..

The method <NUM>, may comprise at a step <NUM> implement a second pin-muxing with N inputs (briefly, ins) and M outputs. Here, M may correspond to the number of scan out chains that may be used for on-chip comparisons. At a step <NUM>, the method may comprise inserting modules into a chip design such as a comparator <NUM> and decoding logic <NUM>. For instance, at the step <NUM> the method comprises to insert module in design. The method may comprise at a step <NUM>, generating an NxM codec. For instance, the method at step <NUM> comprises to generate NxM codec using R=log<NUM>(<NUM>^M). As will be appreciated, the number of inputs for carrying the merged expected test-result and masking-instruction signal may be selected in accordance with Equation <NUM>. At a step <NUM>, the method may comprise integrating the codec generated at step <NUM> and inserting scan chains. Device registers may be stitched into multiple shift registers (scan chains) and connected between a codec decompressor and compressor.

Claim 1:
A method (<NUM>) for testing a chip (<NUM>, <NUM>) with an on-chip comparator (<NUM>), the method (<NUM>) comprising:
receiving (<NUM>), by the chip (<NUM>, <NUM>), N scan-in chains of test data from an off-chip test equipment (<NUM>), wherein N is a first integer value;
using (<NUM>) the N scan-in chains of test data to perform tests on the chip (<NUM>, <NUM>) that produce test results;
receiving (<NUM>) a merged expected test-result and masking-instruction signal on X pins of the chip (<NUM>, <NUM>) from the off-chip test equipment (<NUM>), wherein X is a second integer value less than twice the first integer number N;
decoding (<NUM>) the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results;
for each decoded output signal comprising an expected test result, using the on-chip comparator (<NUM>) to compare the decoded output signal with the respective chain of test results for that decoded output signal; and
for each decoded output signal comprising a masking condition, masking from comparison the respective test chain of test results for that decoded output signal.