Patent Description:
Embedded processing systems can include control system software that is critical to the physical performance of a control system. For example, a vehicle control system relies on a combination of carefully crafted control processes using a combination of instructions, constant data, and dynamically adjusted data to operate one or more electromechanical systems. If configuration items, such as software and/or data are modified, whether intentionally or unintentionally, the control system may be at risk of exhibiting undesirable behavior and/or degraded performance.

<CIT> discloses a fixed function hardware module which, in conjunction with a TPM, performs integrity checks at memory addresses specified by a memory address list. The memory addresses may correspond to system software or data. The integrity checks may take place at boot time or at run time.

<CIT> discloses a secure storage element that independently verifies the integrity of various software components of a system, according to a set of address ranges provided. The integrity verification can take place at runtime.

<CIT> teaches verifying the integrity of software components of an automotive ECU based in part on a memory map and the corresponding expected contents.

According to one embodiment, an embedded processing system includes processing circuitry configured to execute a plurality of computer executable instructions. The embedded processing system also includes a memory system configured to store a plurality of configuration items, where at least one of the configuration items includes a sequence of the computer executable instructions. The embedded processing system also includes an authentication control configured to authenticate an immutable anchor associated with the embedded processing system, authenticate integrity of a reconfigurable entity map associated with the memory system, authenticate the configuration items based on the reconfigurable entity map, and perform an accommodation measure based on an authentication failure of at least one of the configuration items.

The immutable anchor may be hardware or software that establishes a root and chain of trust in authentication.

The reconfigurable entity map may define a list of address ranges for authenticating the configuration items in the memory system.

The list of address ranges may include two or more address ranges for one of the configuration items.

Two or more different accommodation measures may be defined for the list of address ranges.

The reconfigurable entity map may identify at least one of the address ranges to skip authentication.

The accommodation measure may include one or more of: resetting the embedded processing system, switching the embedded processing system to a fail-safe mode of operation, and transmitting an authentication failure message on a communication interface.

The authentication may include one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure.

One or more of the configuration items may be decrypted prior to authentication within the embedded processing system.

The embedded processing system may be a controller of a gas turbine engine, and at least one of the configuration items may include an application configured to control operation of the gas turbine engine.

According to another embodiment, an authentication control of an embedded processing system authenticates an immutable anchor associated with the embedded processing system and may establish a root of trust. The authentication control authenticates integrity of a reconfigurable entity map associated with a memory system of the embedded processing system. The authentication control authenticates a plurality of configuration items in the memory system based on the reconfigurable entity map. An accommodation measure is performed based on an authentication failure of at least one of the configuration items.

A technical effect of the apparatus, systems and methods is achieved by multi-stage authentication for an embedded processing system as described herein.

Referring now to the drawings, <FIG> illustrates a system <NUM> that includes an embedded processing system <NUM> and a controlled system <NUM>. The controlled system <NUM> can be any type of physical system that includes one or more effectors <NUM> controlled by one or more effector commands <NUM> generated by the embedded processing system <NUM>. Examples of effectors <NUM> can include one or more motors, solenoids, valves, relays, pumps, heaters, and/or other such actuation control components. A plurality of sensors <NUM> can capture state data associated with the controlled system <NUM> and provide sensed values <NUM> as feedback to the embedded processing system <NUM> to enable closed-loop control of the controlled system <NUM> according to one or more control laws. Examples of the sensors <NUM> can include one or more temperature sensors, pressure sensors, strain gauges, level sensors, accelerometers, rate sensors, and the like. The controlled system <NUM> can be an engine, a vehicle, a heating, ventilating, and air conditioning (HVAC) system, an elevator system, industrial machinery, or the like. For purposes of explanation, embodiments are primarily described with respect to an engine system of an aircraft as the controlled system <NUM>, such as a gas turbine engine, where the embedded processing system <NUM> may provide one or more control channels and/or monitoring systems of a controller (e.g., a full authority digital engine control) of one or more gas turbine engines.

In the example of <FIG>, the embedded processing system <NUM> includes processing circuitry <NUM> and a memory system <NUM> configured to store a plurality of configuration items, where at least one of the configuration items includes a sequence of the computer executable instructions for execution by the processing circuitry <NUM>. The executable instructions may be stored or organized in any manner and at any level of abstraction, such as in connection with controlling and/or monitoring operation of the controlled system <NUM>. The processing circuitry <NUM> can be any type or combination of central processing unit (CPU), including one or more of: a microprocessor, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Also, in embodiments, the memory system <NUM> may include volatile memory <NUM>, such as random access memory (RAM), and non-volatile memory <NUM>, such as Flash memory, read only memory (ROM), and/or other electronic, optical, magnetic, or any other computer readable medium onto which is stored data and algorithms in a non-transitory form.

The embedded processing system <NUM> can also include one or more of an input/output interface <NUM>, a communication interface <NUM>, an authentication control <NUM>, and/or other elements (not depicted). The input/output interface <NUM> can include support circuitry for interfacing with the effectors <NUM> and sensors <NUM>, such as filters, amplifiers, digital-to-analog converters, analog-to-digital converters, and other such circuits to support digital and/or analog interfaces. Further, the input/output interface <NUM> can receive or output signals to/from other sources. As one example, discrete inputs <NUM> can be input to the input/output interface <NUM> to establish an operating mode of the embedded processing system <NUM> or to trigger actions by the embedded processing system <NUM>. A reset signal <NUM> may also be received as a signal by the input/output interface <NUM> or may interface with other circuitry of the embedded processing system <NUM>, such as power conditioning circuitry (not depicted). The communication interface <NUM> can be communicatively coupled to a communication system <NUM>, which can include one or more direct or networked communication links to systems, such as a loader system <NUM>, a data repository <NUM>, or another system (not depicted). The loader system <NUM> can be any type of computer system operable to load new/updated configuration items to the embedded processing system <NUM> for storage in the memory system <NUM>. The loader system <NUM> can interface to the communication system <NUM> through a wired, wireless, optical, or magnetic coupling. The data repository <NUM> can serve as a data source for updating the memory system <NUM>, for instance, with control system data, or as a data sink to offload and clear data from the memory system <NUM>, such as fault data, history data, and the like.

In embodiments, the authentication control <NUM> can be implemented in dedicated circuitry, such as an application specific integrated circuit, programmable logic device, field programmable gate array, or the like. Alternatively, the authentication control <NUM> can be implemented in software, such as boot software. In some embodiments, a processing core of the processing circuitry <NUM> can be dedicated for use by the authentication control <NUM>. The authentication control <NUM> can be configured to implement embodiments as further described herein.

Referring now to <FIG>, an example of a plurality of configuration items <NUM> for authentication is depicted. The configuration items <NUM> of <FIG> can include one or more of a boot control <NUM>, a reconfigurable entity map <NUM>, an operating system <NUM>, an application <NUM>, constant data <NUM>, and/or configurable data <NUM>. Further, there can be multiple instances of the configuration items <NUM>, such as multiple instances of the application <NUM>, constant data <NUM>, configurable data <NUM>, and/or other items. The configuration items <NUM> can have different levels of criticality and authentication required. The boot control <NUM> can manage the loading and/or initialization of other configuration items <NUM>. The reconfigurable entity map <NUM> can define address ranges and authentication requirements of the configuration items <NUM>. The operating system <NUM> can provide scheduling and support for one or more applications <NUM> to interface with various hardware elements of the embedded control system <NUM> of <FIG>. One or more applications <NUM> that use constant data <NUM> and/or configurable data <NUM> can be invoked by the operating system <NUM>. The application <NUM> can be, for example, configured to control operation of the controlled system <NUM> of <FIG>.

<FIG> depicts an example of an authentication process <NUM> that can be performed by the authentication control <NUM> of <FIG>. Upon receiving a reset signal <NUM>, a root authentication <NUM> authenticates an immutable anchor <NUM>. The immutable anchor <NUM> is hardware or software that establishes a root and chain of trust in authentication. As one example, the immutable anchor <NUM> can be encoded in a read-only register that is accessible by the authentication control <NUM>. Authentication of the immutable anchor <NUM> can include use of key pairs, certificates, signatures, and/or other known authentication techniques. Upon successful authentication <NUM> of the immutable anchor <NUM> during root authentication <NUM>, the authentication control <NUM> can perform entity map authentication <NUM> of the reconfigurable entity map <NUM>. Authentication can include one or more asymmetric cryptographic methods using unique key pairs that result in an authentication failure based on an incorrect key, a missing key, or software that is tampered with resulting in the authentication failure. For instance, if an incorrect key was used to sign the software, the corresponding key pair does not exist in the embedded processing system <NUM>, or the software was tampered with, an authentication result may be a failure of a signature to authenticate. As a further example, an authentication failure can be detected for a memory range defined in the reconfigurable entity map <NUM> due to tampering of the memory content in the address range when the correct key exists.

Upon successful authentication <NUM> of the reconfigurable entity map <NUM> during entity map authentication <NUM>, the contents of the reconfigurable entity map <NUM> can be used to locate a plurality of configuration items <NUM>, which may be embodiments of the plurality of configuration items <NUM> of <FIG>, including a first configuration item 312A up to configuration item 312N, where N represents any number of configuration items <NUM>. In embodiments, the entity map authentication <NUM> defines a list of address ranges for authenticating the configuration items <NUM> in the memory system <NUM> of <FIG>. Reconfigurable address ranges provide flexibility in authentication boundaries. Each of the configuration items <NUM> can be a sequence of executable instructions (e.g., executable by the processing circuitry <NUM>) or data values, such as values that support execution of instructions (e.g., constant or trim values). Address ranges in the entity map authentication <NUM> may have a one-to-one correspondence with one or more of the configuration items <NUM>, or the list of address ranges can include two or more address ranges for at least one of the configuration items <NUM>. For example, an address range can identify a location and size of the first configuration item 312A in the memory system <NUM> as a single item for authentication <NUM>. Further, multiple address ranges 316A, 316B, 316C, 316N can be associated with a single configuration item, such as configuration item 312N. Thus, rather than performing a single authentication for configuration item 312N, each of the address ranges 316A, 316B, 316C, 316N can have a corresponding authentication 318A, 318B, 318C, 318N.

The authentications <NUM>, 318A-318N may also have different accommodation measures to handle authentication failure conditions. For example, different levels of criticality may be assigned to each of the configuration items <NUM> and/or address ranges 316A-316N. A high level of criticality may be assigned to instructions or control parameters for the controlled system <NUM>, where degraded/faulty performance or non-performance of control operations could occur if non-authenticated instructions or control parameters are used. If the configuration items <NUM> are partitioned to include instruction sequences that are not critical to operation of the controlled system <NUM>, such as diagnostic code, a lower level of criticality can be assigned that may not impede normal operation of controlling the controlled system <NUM>. Further, the reconfigurable entity map can identify at least one of the address ranges 316A-31N to skip authentication, for instance, when a range of memory has to be authenticated during a software load, i.e., reprogramming of the embedded processing system <NUM>, but not when the embedded processing system <NUM> powers up to control the controlled system <NUM>.

Referring now to <FIG> with continued reference to <FIG>, <FIG> is a flow chart illustrating a method <NUM> for multi-step authentication, in accordance with an embodiment. The method <NUM> may be performed, for example, by the authentication control <NUM> of <FIG>.

At block <NUM>, the authentication control <NUM> can authenticate an immutable anchor <NUM> associated with the embedded processing system <NUM> as part of root authentication <NUM>. At block <NUM>, the authentication control <NUM> can authenticate integrity of a reconfigurable entity map <NUM> associated with the memory system <NUM> of the embedded processing system <NUM> as part of entity map authentication <NUM>. At block <NUM>, the authentication control <NUM> can authenticate the configuration items <NUM>, <NUM> based on the reconfigurable entity map <NUM>. The embedded processing system <NUM> can perform an accommodation measure based on an authentication failure of at least one of the configuration items <NUM>, <NUM>. The accommodation measure can include one or more of: resetting the embedded processing system <NUM>, switching the embedded processing system <NUM> to a fail-safe mode of operation, and/or transmitting an authentication failure message on a communication interface <NUM> to the communication system <NUM>. The accommodation measure may be selected based on a level of criticality associated with the item being authenticated, where the level of criticality may be fixed or assigned based on one or more values of the reconfigurable entity map <NUM>. For example, two or more different accommodation measures can be defined for a list of address ranges in the reconfigurable entity map <NUM>. Failure accommodation for authentication failures may not be deferred after all entities are authenticated. Accommodation may happen immediately following a failure depending on the criticality of the function performed by the configuration item. For example, authentication failure of the immutable anchor can be immediate, but failure accommodation for a configuration item that does some diagnostic functionality may be simply to log a fault, and disable execution of the function.

In embodiments, one or more of the configuration items <NUM>, <NUM>, can be decrypted prior to authentication within the embedded processing system <NUM>. For example, when one or more of the configuration items <NUM>, <NUM> are provide from the loader system <NUM>, data repository <NUM>, and/or other source, the configuration items <NUM>, <NUM> can be in an encrypted format and written temporarily into the volatile memory <NUM> for authentication prior to updating intended storage addresses within the non-volatile memory <NUM>. The one or more of the configuration items <NUM>, <NUM> can be signed and encrypted at a point of generation and encrypted and signed again for transfer to the loader system <NUM>. The loader system <NUM> can decrypt the one or more of the configuration items <NUM>, <NUM> and verify one or more associated signatures before transfer to the embedded processing system <NUM>. Within the embedded processing system <NUM>, the one or more of the configuration items <NUM>, <NUM> can be decrypted and one or more associated signatures verified, for instance, during transfer into non-volatile memory <NUM> in the embedded processing system <NUM>. The authentication control <NUM> may work in conjunction with the boot control <NUM> to manage the loading, authentication, and storage of the configuration items <NUM>, <NUM> in the memory system <NUM>. The boot control <NUM> can send a response indicating a success or failure of signature verification and/or authentication to the loader system <NUM>. Upon successful authentication, a decrypted version of the one or more of the configuration items <NUM>, <NUM> can be written to the non-volatile memory <NUM>. As an alternative, one or more of the configuration items <NUM>, <NUM> can be stored in the non-volatile memory <NUM> in an encrypted format and be decrypted and transferred to the volatile memory <NUM> upon authentication during a start-up process. If updates are made to the one or more of the configuration items <NUM>, <NUM> in the volatile memory <NUM>, periodic backup copies may be written to the non-volatile memory <NUM> (in an encrypted or decrypted format) to support recovery operations due to a loss of power or assertion of the reset signal <NUM>.

While the present disclosure has been described with reference to an exemplary embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof.

In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure.

Claim 1:
An embedded processing system (<NUM>), which is a controller for a gas turbine engine, the embedded processing system (<NUM>) comprising:
processing circuitry (<NUM>) configured to execute a plurality of computer executable instructions;
a memory system (<NUM>) configured to store a plurality of configuration items (<NUM>), wherein at least one of the configuration items comprises an application (<NUM>) configured to control operation of the gas turbine engine, and wherein at least one of the configuration items comprises a reconfigurable entity map (<NUM>) that defines a list of address ranges of the configuration items; and
an authentication control (<NUM>) configured to:
authenticate an immutable anchor (<NUM>) associated with the embedded processing system, wherein authentication of the immutable anchor is performed upon receiving a reset signal at the embedded processing system, and wherein the immutable anchor is encoded in a read-only storage;
authenticate integrity of the reconfigurable entity map upon successful authentication of the immutable anchor;
locate one or more of the configuration items in the memory system based on the list of address ranges in the reconfigurable entity map upon successful authentication of the reconfigurable entity map;
authenticate the one or more of the configuration items based on the reconfigurable entity map; and
perform an accommodation measure based on an authentication failure of at least one of the configuration items.