Patent Description:
The present invention provides a method in accordance with claim <NUM> and a processor in accordance with claim <NUM>.

<FIG> illustrate techniques for applying offset values to read and write pointers to a FIFO for data being transferred between clock domains of a processor based on a frequency ratio between the clock domains, allowing data to be written to or read from the FIFO at a faster rate than that governed by meta-stability circuitry associated with the read and write pointers. The processor employs one or more controllers that set and apply pointer offsets in each of the clock domains to reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. Further, the controller resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains. By employing the one or more controllers to set and apply pointer offset values, the processor continues to accurately transfer data in response to clock frequency changes, while reducing latency and maximizing bandwidth. The processor enhances processing efficiency while supporting accurate data transfer between the clock domains.

To illustrate, the processor includes a first-in first out queue (FIFO) having multiple entries to store data transferred between two different clock domains. Each clock domain includes a controller to manage a set of pointers to access the FIFO. Conventionally, the read and write pointers are transferred across the clock domains via a meta-stability circuit to ensure that data is not written to or read from a FIFO entry until a read or write of the entry has been completed. However, the timing and configuration of the meta-stability circuit is based on an assumed "worst-case" relationship between the clock signals of the different clock domains. Furthermore, because the frequencies of the different clock signals vary over time based on changing operating requirements of the processor, the assumed worst-case relationship is too conservative in many cases, negatively impacting processing efficiency. Using the techniques described herein, the FIFO controller applies a non-zero offset value to one or more of the read and write pointers based on the frequencies of the clock signals of the different clock domains, thereby allowing the FIFO to be read or written more quickly. The controller thereby ensures that a lower latency is established for data written to the FIFO before that data is read. For example, for some embodiments in which the frequencies of the clock domains are equal, the controller sets a positive write pointer offset value and a positive read pointer offset value that reduce the latency of the FIFO by several clock cycles. In some embodiments, the frequency of the write clock is higher than the frequency of the read clock, and the controller sets a negative offset value for the write pointer to reduce the time entries sit in the FIFO and a positive offset value for the read pointer to prevent the read side from stalling as it waits for the pointers to synchronize, resulting in reduced latency and increased bandwidth. Both clock domains of the FIFO move their read and write pointers at constant rates, even if there is no data to transfer, based on the known frequency (or period) ratio. The constancy of the transfer rate allows the application of appropriate offsets that would otherwise be unsafe if the frequencies were unknown or fluctuating beyond margined limits. To determine the offset values, the controller compares the frequencies of the clock domains in view of the FIFO depth, synchronizer depth, delays due to signals indicating readiness of a write module to write to and a read module to read from the FIFO (ready and heads up depths), and required margining. As described further herein, by employing a controller to offset the write and read pointer positions, the processor reduces the latency of the flow of data across the clock domains.

<FIG> illustrates a processor <NUM> that applies offset values to read and write pointers to a FIFO for data being transferred between clock domains of a processor based on a frequency ratio between the clock domains, and resets the offset values in response to a frequency change in a clock signal for at least one of the clock domains in accordance with some embodiments. The processor <NUM> is implemented by any of a variety of compute-enabled electronic devices, such as a server, a desktop computer, a notebook computer, a tablet computer, a compute-enabled portable cellular phone (e.g., a "smart phone"), a compute-enabled watch or other wearable item, a personal digital assistant (PDA), a gaming console, and the like. In the depicted example, the processor <NUM> includes two clock domains, designated write clock domain <NUM> and read clock domain <NUM>. The write clock domain <NUM> includes a write module <NUM> associated with operations of a processor core (not shown). The read clock domain <NUM> includes a read module <NUM> associated with operations of a processor core (not shown). In some embodiments, the processor <NUM> includes additional clock domains (not shown) similar to write clock domain <NUM> and read clock domain <NUM> to support different processor cores and corresponding caches, with each clock domain having its own memory hierarchy including its own caches.

To maintain processing efficiency, the processor <NUM> provides different clock signals to the write clock domain <NUM> and the read clock domain <NUM> to synchronize their respective operations. In the depicted example, the clock signal provided to the write clock domain <NUM> is designated "WRITE CLOCK" and the clock signal provided to the read clock domain <NUM> is designated "READ CLOCK". As described further herein, the WRITE CLOCK and READ CLOCK signals are asynchronous, and therefore may have different frequencies and phases.

In particular, to generate the WRITE CLOCK and READ CLOCK signals, the processor <NUM> employs a clock generator <NUM>. The clock generator <NUM> is a module configured to generate the WRITE CLOCK and READ CLOCK signals based on a timing signal (not shown) that is phase locked to a stable oscillating signal provided by a clock source (not shown), such as a reference crystal. In some embodiments, the clock generator <NUM> generates the WRITE CLOCK and READ CLOCK signals by selectively combining multiple clock signals based on control signaling that independently establishes the clock frequency for each clock signal. In the depicted example, the control signaling is provided by a controller <NUM>.

The clock generator <NUM> identifies the frequencies for each of the WRITE CLOCK and READ CLOCK signals based on the control signaling from the controller <NUM>. The clock generator <NUM> generates the WRITE CLOCK and READ CLOCK signals at their respective determined frequencies. In some embodiments, the clock generator <NUM> generates each of the WRITE CLOCK and READ CLOCK signals by independently combining phase-shifted versions of the timing signal to generate each clock signal at its respective frequency. The clock generator <NUM> sets and changes the frequency for each of the clock signals WRITE CLOCK and READ CLOCK independently of the other, such that the WRITE CLOCK and READ CLOCK signals are asynchronous.

Because of the asynchronicity of the clock signals WRITE CLOCK and READ CLOCK, the write clock domain <NUM> and read clock domain <NUM> cannot reliably communicate data synchronously, based on only one of their corresponding clock signals. Accordingly, to facilitate communication of data between the write clock domain <NUM> and the read clock domain <NUM>, the processor <NUM> includes a FIFO <NUM> having a plurality of entries, wherein each entry is a separately addressable storage location that is accessed by both the write clock domain <NUM> and the read clock domain <NUM>. For example, in some embodiments the FIFO <NUM> includes eight entries (i.e., it has a depth of <NUM>). As used herein, the depth of the FIFO <NUM> refers to the number of entries of the FIFO <NUM>. Thus, in some embodiments, the FIFO <NUM> has a depth of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. For ease of description, it is assumed that the FIFO <NUM> is employed to transfer data from the write clock domain <NUM> to the read clock domain <NUM> according to the techniques described herein.

To access the FIFO <NUM>, the write clock domain <NUM> includes a write module <NUM> and the read clock domain <NUM> includes a read module <NUM>. Each of the read/write modules <NUM> and <NUM> independently manages a set of pointers to access the FIFO <NUM>. In particular, the write module <NUM> employs a write pointer <NUM> to indicate the next entry of the FIFO <NUM> to be written. In response to detecting an available slot in the FIFO <NUM> for transfer data to the read clock domain <NUM>, the write module <NUM> asserts ready signal <NUM> for one clock cycle to indicate to external logic in communication with components of the processor <NUM> that an open FIFO entry will be available in the configured number of clocks in the write clock domain <NUM>. After the configured number of clocks in the write clock domain <NUM> the write module <NUM> writes the data to the entry of the FIFO <NUM>, then adjusts the write pointer <NUM> to point to the next entry of the FIFO <NUM>. The write module <NUM> performs a write into the FIFO <NUM> whether or not there is valid data in order to maintain the required cadence. If the written entry is the last entry of the FIFO <NUM>, the write module <NUM> adjusts the write pointer <NUM> to point to the first entry of the FIFO <NUM>. Thus, assuming the FIFO <NUM> has eight entries, the write pointer <NUM> first points to entry zero, then to entry one, then to entry two, then to entry three, then to entry four, then to entry five, then to entry six, then to entry seven, and then returns to entry zero.

The read module <NUM> employs a read pointer <NUM> to indicate the next entry of the FIFO <NUM> to be read. In response to the read module <NUM> detecting that an entry can be read from FIFO <NUM>, it asserts the heads up signal <NUM> for one clock cycle to external logic that a read from the FIFO <NUM> will occur in a configured number of read clock domain <NUM> cycles. After the configured number of read clock domain <NUM> cycles, the read module <NUM> reads the entry indicated by the read pointer <NUM>, then adjusts the read pointer <NUM> to point to the next entry of the FIFO <NUM>. The read module <NUM> performs a transfer whether or not there is valid data to transfer in order to maintain the proper cadence. As with the write pointer <NUM> described above, if the read entry is the last entry of the FIFO <NUM>, the read module <NUM> adjusts the read pointer <NUM> to point to the first entry of the FIFO <NUM>.

During a reset, both the write pointer <NUM> and the read pointer <NUM> are set to an initial value corresponding to an initial entry of the FIFO <NUM>. The FIFO <NUM> is empty when the write pointer <NUM> and the read pointer <NUM> are equal. The FIFO <NUM> is full when the most significant bit (MSB) of the write pointer <NUM> and the read pointer <NUM> are different, but the remaining bits are equal. In some embodiments, the write pointer <NUM> and the read pointer <NUM> are encoded using a Gray code. The code distance between any two adjacent Gray code words is <NUM>; thus, only one bit changes from one Gray count to the next. By using a Gray code to encode the write pointer <NUM> and the read pointer <NUM>, it is not necessary to synchronize multiple changing bits on a clock edge.

Each of the write module <NUM> and read module <NUM> is synchronized by the clock signal corresponding to their clock domain (that is, clock signals WRITE CLOCK and READ CLOCK, respectively). To synchronize the read pointer <NUM> with the write clock domain <NUM>, and to prevent meta-stability errors, the position of the write pointer <NUM> with respect to the entries of the FIFO <NUM> is transmitted to the read pointer <NUM> via a write pointer sync <NUM>. Similarly, to synchronize the write pointer <NUM> with the read clock domain, and to prevent meta-stability errors, the position of the read pointer <NUM> with respect to the entries of the FIFO <NUM> is transmitted to the write pointer <NUM> via a read pointer sync <NUM>. Each of the write pointer sync <NUM> and the read pointer sync <NUM> includes a number of flip flops (not shown) (the number of flip flops being referred to as the "sync depth") and maintains a delay for data written to or read from an entry of the FIFO <NUM>.

In some embodiments, the write module <NUM> asserts a ready signal <NUM> indicating that the write module <NUM> is ready to output data to the FIFO <NUM>. In some embodiments, the write module <NUM> asserts the ready signal <NUM> a predetermined number of write clock cycles before the write module <NUM> outputs data to the FIFO <NUM>. In some embodiments, the predetermined number of write clock cycles is programmable. In some embodiments, the read module <NUM> asserts a heads up signal <NUM> a predetermined number of read clock cycles before the read module <NUM> is ready to read data from the FIFO <NUM>. In some embodiments, the predetermined number of read clock cycles is programmable. The heads up signal <NUM> and the ready signal <NUM> allow interface logic on each side of the FIFO <NUM> to deliver and receive data efficiently, reduce latency, and ease critical timing paths. However, the accumulated delays from the read pointer sync <NUM>, the write pointer sync <NUM>, the heads up signal <NUM>, and the ready signal <NUM> result in increased latency at the FIFO <NUM>. In some embodiments, the write module <NUM> contains a pipeline of state elements (not shown) to delay the ready signal <NUM> and heads up signal <NUM>.

In some embodiments, the write module <NUM> employs a commit write pointer <NUM> and the read module <NUM> employs a commit read pointer <NUM> to track additional write and read pointer states, respectively, that reflect the number of cycles with ready signal <NUM> and heads up signal <NUM> assertions that are outstanding to external logic but not yet committed to the FIFO <NUM> (referred to as the ready signal <NUM> delay and the heads up signal <NUM> delay, respectively). The independently configurable ready signal <NUM> delay of the commit write pointer <NUM> and the heads up signal <NUM> delay of the commit read pointer <NUM> allow external logic time to align data to be transferred with the cadence of available transfer slots in the FIFO <NUM>, as controlled by the ratio of the write clock domain <NUM> to the read clock domain <NUM>. In asynchronous mode, the ready signal <NUM> and heads up signal <NUM> delays add directly to the latency of data transfers. However, with properly calculated write offset <NUM> and read offset <NUM> values, the ready signal <NUM> and heads up signal <NUM> can be absorbed within the operations of the processor <NUM>, resulting in reduced overall system clock domain transfer latency. In some embodiments, the commit write pointer <NUM> and the commit read pointer <NUM> use a chain of flip flops to create the delay needed between the clock cycle asserting the ready signal <NUM> and the heads up signal <NUM> to the time the write module <NUM> and the read module <NUM>, respectively, perform the write or read operation.

To facilitate decreased latency and higher bandwidth, the controller <NUM> applies a write offset <NUM> to the write pointer <NUM> based on the ratio of the frequencies (or periods) of the write clock to the read clock. The controller <NUM> also applies a read offset <NUM> to the read pointer <NUM> based on the ratio of the frequencies (or periods) of the write clock to the read clock. In some embodiments, both the write offset <NUM> and the read offset <NUM> are positive integers. In some embodiments, one or both of the write offset <NUM> and the read offset <NUM> is a negative integer. The write offset <NUM> and the read offset <NUM> either advance (in the case of a positive offset) or retard (in the case of a negative offset) the limits of the write pointer <NUM> and read pointer <NUM>, respectively, allowing the FIFO <NUM> to maintain full bandwidth by not stalling as the FIFO <NUM> waits for the write pointer <NUM> and the read pointer <NUM> to be synchronized across the write clock domain <NUM> and the read clock domain <NUM>.

In some embodiments, the controller <NUM> calculates the write offset <NUM> and the read offset <NUM> based on the variables set forth below in Table <NUM>.

In some embodiments, the controller calculates the read offset <NUM> as:<MAT>.

In some embodiments, the controller <NUM> performs all calculations with integers except for the final divide, in which the remainder is used to round to the nearest integer.

In some embodiments, if the WritePeriod is less than or equal to the ReadPeriod, the controller calculates the write offset <NUM> as: <MAT>.

In some embodiments, if the WritePeriod is greater than the ReadPeriod, the controller calculates the write offset <NUM> as: <MAT>.

In some embodiments, these equations are only employed for ratios of the WRITE CLOCK frequency to the READ CLOCK frequency of <NUM>-to-<NUM> and <NUM>-to-<NUM>. In some embodiments, the controller <NUM> calculates the write offset <NUM> and the read offset <NUM> twice, once for each direction through the FIFO <NUM>.

According to the invention, in response to a change in the frequency of either the WRITE CLOCK or READ CLOCK, the controller <NUM> resets the values of the write offset <NUM> and the read offset <NUM> in a controlled manner. In some embodiments, in response to receiving a request to change a frequency, the controller <NUM> sets both the write offset <NUM> and the read offset <NUM> to zero to place the FIFO <NUM> in a simple asynchronous mode. The controller <NUM> then adjusts the WRITE CLOCK and/or the READ CLOCK to match the requested frequency, and determines an adjusted write offset <NUM> and read offset <NUM> based on the ratio of the adjusted frequencies of the WRITE CLOCK and the READ CLOCK.

<FIG> illustrates an example of the controller <NUM> of <FIG> applying a write offset <NUM> of zero to the write pointer <NUM> and a read offset <NUM> of zero to the read pointer <NUM> for writes to and reads from the FIFO <NUM> in accordance with some embodiments. In particular, <FIG> illustrates waveforms <NUM> and <NUM>, corresponding to examples of the WRITE CLOCK and READ CLOCK signals, respectively. For the example of <FIG>, the WRITE CLOCK and READ CLOCK signals have the same frequency. The waveforms <NUM> and <NUM> are each divided into cycles: cycles <NUM>-<NUM> of the WRITE CLOCK (waveform <NUM>) and cycles <NUM>-<NUM> of the READ CLOCK (waveform <NUM>). In addition, for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the write pointer <NUM> for data to be written by the write module <NUM>, and for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the read pointer <NUM> for data to be read by the read module <NUM>.

In the example of <FIG>, the FIFO <NUM> has a depth of <NUM> entries, the read pointer sync <NUM> and write pointer sync <NUM> each have a depth of <NUM> flip flops, the heads up signal <NUM> specifies a <NUM> cycle delay, and the ready signal <NUM> specifies a <NUM> cycle delay. The FIFO <NUM> is empty when the write pointer <NUM> and the read pointer <NUM> are equal. The FIFO <NUM> is full when the most significant bit (MSB) of the write pointer <NUM> and the read pointer <NUM> (illustrated in <FIG> as having a value of either A or B) are different, but the remaining bits are equal. Thus, in the depicted example, the write module <NUM> writes to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO <NUM> during cycle <NUM>, and so on through cycle <NUM>, when the write module <NUM> writes to location <NUM> of the FIFO <NUM>, after which the write module <NUM> stalls at location <NUM> as the read of location <NUM> has yet to be communicated to the write module <NUM>. In the depicted example, the read module <NUM> reads the data from location <NUM> of the FIFO <NUM> during cycle <NUM> of the READ CLOCK, which is <NUM> cycles after the data was written to location <NUM> of the FIFO <NUM>.

Similar to the example of <FIG>, in the example of <FIG> the WRITE CLOCK and READ CLOCK signals have the same frequency. <FIG> illustrates an example of the controller <NUM> of <FIG> applying a write offset <NUM> of <NUM> to the write pointer <NUM> and a read offset <NUM> of <NUM> to the read pointer <NUM> for writes to and reads from the FIFO <NUM> in accordance with some embodiments. Similar to <FIG> illustrates waveforms <NUM> and <NUM>, corresponding to examples of the WRITE CLOCK and READ CLOCK signals, respectively. The waveforms <NUM> and <NUM> are each divided into cycles: cycles <NUM>-<NUM> of the WRITE CLOCK (waveform <NUM>) and cycles <NUM>-<NUM> of the READ CLOCK (waveform <NUM>). In addition, for each cycle <NUM>-<NUM> <FIG> illustrates the location of the FIFO <NUM> that is indicated by the write pointer <NUM> for data to be written by the write module <NUM>, and for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the read pointer <NUM> for data to be read by the read module <NUM>.

As with the example of <FIG>, in the example of <FIG>, the FIFO <NUM> has a depth of <NUM> entries, the read pointer sync <NUM> and write pointer sync <NUM> each have a depth of <NUM> flip flops, the heads up signal <NUM> specifies a <NUM> cycle delay, and the ready signal <NUM> specifies a <NUM> cycle delay. The most significant bits (MSB) of the write pointer <NUM> and the read pointer <NUM> are illustrated in <FIG> as having a value of either A or B. In the depicted example, applying the write offset <NUM> of <NUM> to the write pointer <NUM> and the read offset <NUM> of <NUM> to the read pointer <NUM>, the write module <NUM> writes to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO <NUM> during cycle <NUM>, and so on through cycle <NUM>, when the write module <NUM> writes to location <NUM> of the FIFO <NUM>, after which the write module <NUM> writes to location <NUM>. In the depicted example, the read module <NUM> reads the data from location <NUM> of the FIFO <NUM> during cycle <NUM> of the READ CLOCK, which is <NUM> cycles after the data was written to location <NUM> of the FIFO <NUM>. Thus, by applying the write offset <NUM> of <NUM> to the write pointer <NUM> and the read offset <NUM> of <NUM> to the read pointer <NUM>, the controller <NUM> shortens the latency of the FIFO <NUM> from <NUM> cycles, as depicted in <FIG> cycles, as depicted in <FIG>.

<FIG> illustrates an example of the controller <NUM> of <FIG> applying a write offset <NUM> of zero to the write pointer <NUM> and a read offset <NUM> of zero to the read pointer <NUM> for writes to and reads from the FIFO <NUM> in accordance with some embodiments. <FIG> illustrates waveforms <NUM> and <NUM>, corresponding to examples of the WRITE CLOCK and READ CLOCK signals, respectively. For the example of <FIG>, the READ CLOCK signal is <NUM>% slower than the WRITE CLOCK signal. The waveforms <NUM> and <NUM> are each divided into cycles: cycles <NUM>-<NUM> of the WRITE CLOCK (waveform <NUM>) and cycles <NUM>-<NUM> of the READ CLOCK (waveform <NUM>). In addition, for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the write pointer <NUM> for data to be written by the write module <NUM>, and for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the read pointer <NUM> for data to be read by the read module <NUM>.

As with the examples of <FIG>, in the example of <FIG>, the FIFO <NUM> has a depth of <NUM> entries, the read pointer sync <NUM> and write pointer sync <NUM> each have a depth of <NUM> flip flops, the heads up signal <NUM> specifies a <NUM> cycle delay, and the ready signal <NUM> specifies a <NUM> cycle delay. The most significant bits (MSB) of the write pointer <NUM> and the read pointer <NUM> are illustrated in <FIG> as having a value of either A or B. Thus, in the depicted example, the write module <NUM> writes to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO <NUM> during cycle <NUM>, and so on through cycle <NUM>, when the write module <NUM> writes to location <NUM> of the FIFO <NUM>, after which the write module <NUM> writes to location <NUM>. In the depicted example, the read module <NUM> reads the data from location <NUM> of the FIFO <NUM> during cycle <NUM> of the READ CLOCK, which is <NUM> cycles of the WRITE CLOCK and <NUM> cycles of the READ CLOCK after the first data value A was written to location <NUM> of the FIFO <NUM>.

Similar to the example of <FIG>, in the example of <FIG> the READ CLOCK signal is <NUM>% slower than the WRITE CLOCK signal. <FIG> illustrates an example of the controller <NUM> of <FIG> applying a write offset <NUM> of -<NUM> to the write pointer <NUM> and a read offset <NUM> of <NUM> to the read pointer <NUM> for writes to and reads from the FIFO <NUM> in accordance with some embodiments. Similar to <FIG> illustrates waveforms <NUM> and <NUM>, corresponding to examples of the WRITE CLOCK and READ CLOCK signals, respectively. The waveforms <NUM> and <NUM> are each divided into cycles: cycles <NUM>-<NUM> of the WRITE CLOCK (waveform <NUM>) and cycles <NUM>-<NUM> of the READ CLOCK (waveform <NUM>). In addition, for each cycle <NUM>-<NUM> <FIG> illustrates the location of the FIFO <NUM> that is indicated by the write pointer <NUM> for data to be written by the write module <NUM>, and for each cycle <NUM>-<NUM>, <FIG> illustrates the location of the FIFO <NUM> that is indicated by the read pointer <NUM> for data to be read by the read module <NUM>.

As with the example of <FIG>, in the example of <FIG>, the FIFO <NUM> has a depth of <NUM> entries, the read pointer sync <NUM> and write pointer sync <NUM> each have a depth of <NUM> flip flops, the heads up signal <NUM> specifies a <NUM> cycle delay, and the ready signal <NUM> specifies a <NUM> cycle delay. The most significant bits (MSB) of the write pointer <NUM> and the read pointer <NUM> are illustrated in <FIG> as having a value of either A or B. In the depicted example, applying the write offset <NUM> of -<NUM> to the write pointer <NUM> and the read offset <NUM> of <NUM> to the read pointer <NUM>, the write module <NUM> writes to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO <NUM> during cycle <NUM>, to location <NUM> of the FIFO during cycle <NUM>, to location <NUM> during cycle <NUM>, and so on through cycle <NUM>, when the write module <NUM> writes to location <NUM> of the FIFO <NUM>, after which the write module <NUM> writes to location <NUM> in cycle <NUM>. In the depicted example, the read module <NUM> reads the data from location <NUM> of the FIFO <NUM> during cycle <NUM> of the READ CLOCK, which is <NUM> cycles of the WRITE CLOCK and <NUM> cycles of the READ CLOCK after the data was written to location <NUM> of the FIFO <NUM>. Thus, by applying the write offset <NUM> of -<NUM> to the write pointer <NUM> and the read offset <NUM> of <NUM> to the read pointer <NUM>, the controller <NUM> shortens the latency of the FIFO <NUM> from <NUM> cycles of the WRITE CLOCK and <NUM> cycles of the READ CLOCK, as depicted in <FIG> cycles of the WRITE CLOCK and <NUM> cycles of the READ CLOCK, as depicted in <FIG>.

<FIG> illustrates a block diagram of the controller <NUM> of <FIG> in accordance with some embodiments. In the depicted example, and as described further below, the controller <NUM> calculates and applies the write offset <NUM> and the read offset <NUM> to the commit write pointer <NUM> and commit read pointer <NUM>, respectively. In turn, the commit write pointer <NUM> and the commit read pointer <NUM> directly control the write pointer <NUM> and the read pointer <NUM>, respectively, through a pipeline of flip flops. In some embodiments, the depth of the pipeline of flip flops depends on the delays of the read and heads up signals (not shown). For example, if the ready depth is zero and the heads up depth is zero, then the commit write pointer <NUM> and the commit read pointer <NUM> are effectively removed.

By taking into account the relative frequencies of the WRITE CLOCK and READ CLOCK, as well as other parameters such as the depth of the FIFO <NUM>, the depth of the read pointer sync <NUM> and the write pointer sync <NUM>, and the number of cycles of the heads up signal <NUM> and ready signal <NUM>, the controller <NUM> is able to anticipate the number of transfers into or out of each side of the FIFO <NUM> that will have taken place during the delay between the time at which a location of the FIFO <NUM> is written to by the write module <NUM> and the time that location of the FIFO <NUM> is read from by the read module <NUM>. The controller <NUM> applies offset values for the write offset <NUM> and the read offset <NUM> that allow the commit write pointer <NUM> and the commit read pointer <NUM> to move beyond the raw values they would otherwise have indicated while maintaining a margin sufficient to ensure that the read module <NUM> reads to correct value from the location of the FIFO <NUM> indicated by the commit read pointer <NUM> and that the write module <NUM> does not overwrite a value at a location of the FIFO <NUM> that has not yet been read by the read module <NUM>.

In the example of <FIG>, the processor <NUM> includes the clock generator <NUM>, the controller <NUM>, the read offset <NUM>, the commit read pointer <NUM>, the read pointer module <NUM>, the write offset <NUM>, the commit write pointer <NUM>, the write pointer module <NUM>, and the FIFO <NUM>. The read pointer module <NUM> is configured to store the read pointer for the read module (not shown). In response to assertion of a signal designated "RD", the commit read pointer <NUM> adjusts the read pointer module <NUM> to point to the next location of the FIFO <NUM>, and the read pointer module <NUM> in turn provides the read pointer to the FIFO <NUM>. In response, the FIFO <NUM> reads the location indicated by the read pointer and provides the read data to the read module.

The write pointer module <NUM> is configured similarly to the read pointer module <NUM> to write data to the FIFO <NUM>. In particular, the write pointer module <NUM> stores the write pointer for the write module (not shown). In response to assertion of a signal designated "WRT", the commit write pointer <NUM> adjusts the write pointer module <NUM> to point to the next location of the FIFO <NUM>, and the write pointer module <NUM> in turn provides the write pointer to the FIFO <NUM>, along with the data provided by the write module (not shown). In response, the FIFO <NUM> writes the data location indicated by the write pointer.

The controller <NUM> is configured to generate the RD and WRT signals to read and write data from and to the FIFO <NUM> to calculate and apply the write offset <NUM> and the read offset <NUM> as described above with respect to <FIG>, <FIG>, and <FIG>. In particular, in the example of <FIG>, the controller <NUM> receives a frequency change request <NUM> from the clock generator <NUM>. The frequency change request <NUM> indicates that the clock generator <NUM> will change the frequency of one or both of the WRITE CLK and the READ CLK. The controller <NUM> calculates the new write offset <NUM> and read offset <NUM> based on the adjusted frequencies of the WRITE CLK and READ CLK. The controller <NUM> then waits for the write pointer <NUM> and the read pointer <NUM> to pass a first common entry of the FIFO <NUM> and then temporarily halts transfers of data from components of the processor <NUM> and empties the entries of the FIFO <NUM> that include data that has not been accessed by the read module. The controller <NUM> stops the write pointer <NUM> and the read pointer <NUM> at a second common entry of the FIFO <NUM> and applies the new write offset <NUM> and the new read offset <NUM>. The controller <NUM> then restarts the write pointer <NUM> and the read pointer <NUM> and re-enables transfers of data from components of the processor <NUM>.

<FIG> is a flow diagram of a method <NUM> of setting a write offset <NUM> and a read offset <NUM> for transferring data between clock domains at a FIFO in response to a frequency change of a clock signal for one or both of the clock domains in accordance with some embodiments. The method <NUM> is implemented in some embodiments of the processor <NUM> shown in <FIG>. Controller <NUM> performs method <NUM> whenever new a new write offset <NUM> or a new read offset <NUM> are needed before and after one or both of WRITE CLK and READ CLK change frequency. Method <NUM> ensures no data is lost or duplicated when the write offset <NUM> and read offset <NUM> change by stopping transfers through the FIFO <NUM>, flushing all pending entries from the FIFO <NUM>, stopping the write pointer <NUM> and read pointer <NUM> at a fixed location, applying the new write offset <NUM> and read offset <NUM> values, restarting the write pointer <NUM> and the read pointer <NUM> in a controlled fashion, and finally resuming data transfers though the FIFO <NUM>.

In some embodiments, the controller <NUM> operates two parallel instances of method <NUM>, one for the write clock domain <NUM> and another for the read clock domain <NUM>. At several points in method <NUM> the write pointer <NUM> and the read pointer <NUM> are required to operate in a coordinated fashion such that parallel versions in read clock domain <NUM> and write clock domain <NUM> of method <NUM> are in the same block <NUM> through <NUM> at the same time or nearly the same time as required for proper operation.

At block <NUM>, the controller <NUM> determines if a frequency change is in progress and if a new write offset <NUM> and a read offset <NUM> are required. If not, the method flow returns to block <NUM>. If a new write offset <NUM> and a read offset <NUM> are required, at block <NUM>, the controller <NUM> calculates the new write offset <NUM> and read offset <NUM>. At block <NUM>, the controller <NUM> waits for the read pointer <NUM> and write pointer <NUM> to pass a first common reference point. The common reference point is a defined position in the FIFO <NUM> that the instances of method <NUM> in the write clock domain <NUM> and the read clock domain <NUM> agree upon. In some embodiments, the common reference point is the FIFO <NUM> entry 0A. In some embodiments, the common reference point is a FIFO <NUM> entry as tracked by the commit write pointer <NUM> and the commit read pointer <NUM>. Use of the commit write pointer <NUM> and the commit read pointer <NUM> ensures that every pulse of ready signal <NUM> has a corresponding heads up signal <NUM> and that entries still in the FIFO <NUM> at the entry of block <NUM> will still be read by the read module <NUM> and have a corresponding pulse of heads up signal <NUM>.

At block <NUM>, after the write pointer <NUM> and the read pointer <NUM> have passed the first common reference point, the controller <NUM> forces the ready signal <NUM> and heads up signal <NUM> values low to inform components connected to processor <NUM> that no transfers are available. However, while components outside processor <NUM> are stalled, write pointer <NUM> and read pointer <NUM> continue to operate within processor <NUM> to perform method <NUM>. At block <NUM>, controller <NUM> drains any data in the FIFO <NUM> that is waiting to be read by the read module <NUM>. In some embodiments, the forcing of ready signal <NUM> and heads up signal <NUM> low through the commit write pointer <NUM> and commit read pointer <NUM> ensures that any transfers through the FIFO <NUM> when method <NUM> reaches block <NUM> will still have a proper heads up signal <NUM> as the flip flop pipeline used inside the commit write pointer <NUM> and the commit read pointer <NUM> will contain the proper values to operate the write pointer <NUM> and read pointer <NUM>, respectively, to prevent lost data.

At block <NUM>, first the commit write pointer <NUM> and then write pointer <NUM> stop at a second common reference point. The commit read pointer <NUM> and the read pointer <NUM> then stop at the second common reference point. In some embodiments, the second common reference point is the FIFO <NUM> entry 0B. When the write pointer <NUM> and the read pointer <NUM> stop, the controller <NUM>, at block <NUM>, applies the new read write offset <NUM> and new read offset <NUM>. At block <NUM>, the controller <NUM> restarts the write pointer <NUM> upon detecting that the read pointer sync <NUM> has reached the second common reference point. At block <NUM>, the read pointer <NUM> detects that the write pointer sync <NUM> moves past the second common reference point. The commit read pointer <NUM> bypasses the internal flip flop pipeline and begins moving the read pointer <NUM> and the commit read pointer <NUM> at the same time, advancing the commit read pointer <NUM> by the number of flip flops in the pipeline between the commit read pointer <NUM> and the read pointer <NUM>. In embodiments with a commit read pointer <NUM>, block <NUM> ensures the time differential between the write pointer <NUM> and the read pointer <NUM> is not skewed based on the commit read pointer <NUM> pipeline depth.

At block <NUM>, the controller <NUM> waits for the write pointer <NUM> and the read pointer <NUM> to return to the first common reference point, giving time for the write pointer <NUM> and the read pointer <NUM> to settle to the proper time differential. At block <NUM>, the controller <NUM> enables normal traffic by restoring the ready signal <NUM> and heads up signal <NUM> to their proper values for the new processor <NUM> configuration. At block <NUM>, the controller <NUM> sends a signal to the clock generator <NUM> to indicate that method <NUM> is complete.

In some embodiments, a method includes: at a first clock domain of a processor, incrementing a position of a write pointer with respect to a plurality of entries of a buffer based on a depth of the buffer and a first offset value; accessing, at a write module of the processor, a first entry of the plurality of entries of the buffer in response to the write pointer indicating the first entry; at a second clock domain of the processor, incrementing a position of a read pointer with respect to the plurality of entries of the buffer based on the position of the write pointer and a second offset value, the second offset value based on a ratio of a first frequency of a first clock signal of the first clock domain to a second frequency of a second clock signal of the second clock domain, the second clock signal asynchronous with the first clock signal; and accessing, at a read module of the processor, the first entry of the plurality of entries of the buffer in response to the read pointer indicating the first entry. In one aspect, the first offset value is based on the ratio of the first frequency to the second frequency. In another aspect, the first offset value is based on a depth of a synchronizer between the first clock domain and the second clock domain.

In one aspect, the method includes asserting a signal indicating that the write module will access the buffer, and wherein the first offset value is further based on a number of clock cycles of the first clock signal between assertion of the signal and the write module accessing of the buffer. In another aspect the second offset value is further based on a depth of a synchronizer between the first clock domain and the second clock domain. In still another aspect, the method includes resetting the first offset value and the second offset value in response to a request to adjust the first frequency to a first adjusted frequency or the second frequency to a second adjusted frequency. In one aspect resetting the first offset value and the second offset value includes: determining a first adjusted offset value for the write pointer based on the ratio of the first adjusted frequency to the second adjusted frequency in response to the first adjusted frequency being higher than the second adjusted frequency; determining a second adjusted offset value for the read pointer based on the ratio of the first adjusted frequency to the second adjusted frequency; emptying the entries of the buffer that include data that has not been accessed by the read module; stopping the write pointer and the read pointer at a common entry of the buffer; incrementing the position of the write pointer based on the first adjusted offset value; and incrementing the position of the read pointer based on the second adjusted offset value.

In some embodiments, a method includes at a first clock domain of a processor, offsetting a position of a write pointer with respect to a first-in first-out buffer (FIFO) having a depth, based on a first offset value; at a second clock domain of the processor, offsetting a position of a read pointer with respect to the FIFO based on a second offset value, wherein the second offset value is based on a ratio of a first period of a first clock signal of the first clock domain to a second period of a second clock signal of the second clock domain; accessing, at a write module of the processor, a first entry of the FIFO based on the position of the write pointer; incrementing the write pointer with respect to the FIFO in response to accessing the first entry; reading, at a read module of the processor, from the first entry of the FIFO based on the position of the read pointer with respect to the FIFO; and incrementing the read pointer with respect to the FIFO in response to reading from the first entry. In one aspect the first offset value is based on the ratio of the first period to the second period. In another aspect the first offset value is based on a depth of a synchronizer between the first clock domain and the second clock domain.

In still another aspect, the method includes asserting a signal indicating that the write module will access the buffer, and wherein the first offset value is further based on a number of clock cycles of the first clock signal between assertion of the signal and the write module accessing of the buffer. In yet another aspect, the method includes resetting the first offset value and the second offset value in response to a request to adjust the first period to a first adjusted period or the second period to a second adjusted period. In another aspect resetting the first offset value and the second offset value includes: determining a first adjusted offset value for the write pointer based on the ratio of the first adjusted frequency to the second adjusted frequency in response to the first adjusted frequency being higher than the second adjusted frequency; determining a second adjusted offset value for the read pointer based on the ratio of the first adjusted frequency to the second adjusted frequency; emptying the entries of the buffer that include data that has not been accessed by the read module; stopping the write pointer and the read pointer at a common entry of the buffer; incrementing the position of the write pointer based on the first adjusted offset value; and incrementing the position of the read pointer based on the second adjusted offset value.

In some embodiments, a processor includes: a first-in first-out buffer (FIFO); a first clock domain including: a write pointer; a first synchronizer; and a write module configured to access a first entry of the FIFO in response to a position of the write pointer with respect to the FIFO, wherein the position of the write pointer is based on a depth of the FIFO and a first offset value; a second clock domain including: a read pointer; a second synchronizer; and a read module configured to access the first entry of the FIFO in response to a position of the read pointer with respect to the FIFO, wherein the position of the read pointer is based on the position of the write pointer and a second offset value; and a controller configured to determine the first offset value and the second offset value. In one aspect the controller is configured to determine the first offset value based on a ratio of a first frequency of a first clock signal of the first clock domain to a second frequency of a second clock signal of the second clock domain, the second clock signal asynchronous with the first clock signal.

In another aspect the controller is configured to determine the first offset value based on a depth of the first synchronizer. In still another aspect, the write module is further configured to assert a signal indicating that the write module will access the buffer, and wherein controller is further configured to determine the first offset value based on a number of clock cycles of the first clock signal between assertion of the signal and the write module accessing of the buffer. In yet another aspect the controller is configured to determine the second offset value based on a ratio of a first frequency of a first clock signal of the first clock domain to a second frequency of a second clock signal of the second clock domain, the second clock signal asynchronous with the first clock signal. In another aspect the controller is configured to reset the first offset value and the second offset value in response to a request to adjust the first frequency to a first adjusted frequency or the second frequency to a second adjusted frequency. In yet another aspect the controller is further configured to: determine a first adjusted offset value for the write pointer based on the ratio of the first adjusted frequency to the second adjusted frequency in response to the first adjusted frequency being higher than the second adjusted frequency; determine a second adjusted offset value for the read pointer based on the ratio of the first adjusted frequency to the second adjusted frequency; empty the entries of the FIFO that include data that has not been accessed by the read module; stop the write pointer and the read pointer at a common entry of the FIFO; increment the position of the write pointer based on the depth of the FIFO and the first adjusted offset value; and increment the position of the read pointer based on the position of the write pointer and the second adjusted offset value.

In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the multimedia system described above with reference to <FIG>. Electronic design automation (EDA) and computer aided design (CAD) software tools are used in the design and fabrication of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices to perform at least a portion of a process to design or adapt a manufacturing system to fabricate the circuitry. This code includes instructions, data, or a combination of instructions and data. The software instructions representing a design tool or fabrication tool typically are stored in a computer readable storage medium accessible to the computing system. Likewise, the code representative of one or more phases of the design or fabrication of an IC device may be stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

A computer readable storage medium includes any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and/or data to the computer system. Such storage media include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc, magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media. The computer readable storage medium, in one embodiment, is embedded in the computing system (e.g., system RAM or ROM), fixedly attached to the computing system e.g., a magnetic hard drive), removably attached to the computing system (e.g., an optical disc or Universal Serial Bus (USB)-based Flash memory), or coupled to the computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium. The software includes the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer readable storage medium includes, for example, a magnetic or optical disk storage device, solid state storage devices such as Flash memory, a cache, random access memory (RAM) or other non-volatile memory device or devices, and the like. The executable instructions stored on the non-transitory computer readable storage medium are implemented, for example, in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

Claim 1:
A method comprising:
at a first clock domain (<NUM>) of a processor (<NUM>), incrementing a position of a write pointer (<NUM>) with respect to a plurality of entries of a buffer based on a depth of the buffer and a first offset value;
accessing, at a write module (<NUM>) of the processor, a first entry of the plurality of entries of the buffer in response to the write pointer indicating a location of the first entry;
at a second clock domain (<NUM>) of the processor, incrementing a position of a read pointer (<NUM>) with respect to the plurality of entries of the buffer based on the position of the write pointer and a second offset value;
accessing, at a read module (<NUM>) of the processor, the first entry of the plurality of entries of the buffer in response to the read pointer indicating the location of the first entry; and characterized by
resetting the first offset value and the second offset value in response to a request to adjust a first frequency of a first clock signal of the first clock domain to a first adjusted frequency or a second frequency of a second clock signal of the second clock domain to a second adjusted frequency.