Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate ofsemiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process.

Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features.

<CIT> discloses a semiconductor device having a gate electrode. First contact portions are on both sides of the gate electrode. An etch stopping layer is formed over the gate electrode and over the first contact portions on both sides of the gate electrode.

<CIT> discloses a gate with first contact vias on both sides of the gate. A gate etch stop layer is formed over the gate and over the first contact vias on both sides of the gate.

<CIT> discloses a substrate with source and drain regions. A contact metal is aligned above the source and drain regions, and is covered by an oxide cap. On both sides of the contact metal, a respective work function metal layer is aligned, and is covered by a hardmask material layer. Between the work function metal layers and the contact metals, a vertical dielectric liner and vertical dielectric material layer are disposed.

The present invention concerns a device as defined in claim <NUM> and a method as defined in claim <NUM>. Preferred embodiments are defined in dependent claims.

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

One or more embodiments of the present invention are directed to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed over active portions of gate electrodes of the semiconductor structures or devices. One or more embodiments of the present invention are directed to methods of fabricating
semiconductor structures or devices having one or more gate contact structures formed over active portions of gate electrodes of the semiconductor structures or devices. Approaches described herein may be used to reduce a standard cell area by enabling gate contact formation over active gate regions. In one or more embodiments, the gate contact structures fabricated to contact the gate electrodes are self-aligned via structures.

In technologies where space and layout constraints are somewhat relaxed compared with current generation space and layout constraints, a contact to gate structure may be fabricated by making contact to a portion of the gate electrode disposed over an isolation region. As an example, <FIG> illustrates a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

Referring to <FIG>, a semiconductor structure or device <NUM> A includes a diffusion or active region <NUM> disposed in a substrate <NUM>, and within an isolation region <NUM>, in an example not covered by the appended claims. One or more gate lines (also known as poly lines), such as gate lines <NUM> A, 108B and 108C are disposed over the diffusion or active region <NUM> as well as over a portion of the isolation region <NUM>. Source or drain contacts (also known as trench contacts), such as contacts 110A and HOB, are disposed over source and drain regions of the semiconductor structure or device 100A. Trench contact vias 112A and 112B provide contact to trench contacts 110A and HOB, respectively. A separate
gate contact <NUM>, and overlying gate contact via <NUM>, provides contact to gate line 108B. In contrast to the source or drain trench contacts 110A or 110B, the gate contact <NUM> is disposed, from a plan view perspective, over isolation region <NUM>, but not over diffusion or active region <NUM>. Furthermore, neither the gate contact <NUM> nor gate contact via <NUM> is disposed between the source or drain trench contacts 110A an 110B.

<FIG> illustrates a cross-sectional view of a planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode, an example not covered by the appended claims. Referring to Figure IB, a semiconductor structure or device 100B, e.g. a planar version of device 100A of <FIG>, includes a planar diffusion or active region 104B disposed in substrate <NUM>, and within isolation region <NUM>. Gate line 108B is disposed over the planar diffusion or active region 104B as well as over a portion of the isolation region <NUM>. As shown, gate line 108B includes a gate electrode <NUM> and gate dielectric layer <NUM>. As well, a dielectric cap layer <NUM> may be disposed on the gate electrode, e.g., a dielectric cap layer for protecting a metal gate electrode. Gate contact <NUM>, and overlying gate contact via <NUM> are also seen from this perspective, along with an overlying metal interconnect <NUM>, all of which are disposed in inter-layer dielectric stacks or layers <NUM>. Also seen from the perspective of Figure IB, the gate contact <NUM> and gate contact via <NUM> are disposed over isolation region <NUM>, but not over planar diffusion or active region 104B.

<FIG> illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode, an example not covered by the appended claims. Referring to <FIG>, a semiconductor structure or device looC, e.g. a non-planar version of device 100A of <FIG>, includes a non-planar diffusion or active region 104C (e.g., a fin structure) formed from substrate <NUM>, and within isolation region <NUM>. Gate line 108B is disposed over the non-planar diffusion or active region 104C as well as over a portion of the isolation region <NUM>. As shown, gate line 108B includes a gate electrode <NUM> and gate dielectric layer <NUM>, along with a dielectric cap layer <NUM>. Gate contact <NUM>, and overlying gate contact via <NUM> are also seen from this perspective, along with an overlying metal interconnect <NUM>, all of which are disposed in inter-layer dielectric stacks or layers <NUM>. Also seen from the perspective of <FIG>, the gate contact <NUM> is disposed over isolation region <NUM>, but not over non-planar diffusion or active region 104C.

Referring again to <FIG>, the arrangement of semiconductor structure or device looA-looC, respectively, places the gate contact over isolation regions. Such an arrangement wastes layout space. However, placing the gate contact over active regions would require either an extremely tight registration budget or gate dimensions would have to increase to provide enough space to land the gate contact. Furthermore, historically, contact to gate over diffusion regions has been avoided for risk of drilling through conventional gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address.

the above issues by providing feasible approaches, and the resulting structures, to fabricating contact structures that contact portions of a gate electrode formed over a diffusion or active region.

As an example, <FIG> illustrates a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an example not covered by the appended claims. Referring to <FIG>, a semiconductor structure or device 200A includes a diffusion or active region <NUM> disposed in a substrate <NUM>, and within an isolation region <NUM>. One or more gate lines, such as gate lines 208A, 208B and 208C are disposed over the diffusion or active region <NUM> as well as over a portion of the isolation region <NUM>. Source or drain trench contacts, such as trench contacts 210A and 210B, are disposed over source and drain regions of the semiconductor structure or device 200A. Trench contact vias 212A and 212B provide contact to trench contacts 210A and 210B, respectively. A gate contact via <NUM>, with no intervening separate gate contact layer, provides contact to gate line 208B. In contrast to <FIG>, the gate contact <NUM> is disposed, from a plan view perspective, over the diffusion or active region <NUM> and between the source or drain contacts <NUM> OA and 210B.

<FIG> illustrates a cross-sectional view of a planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an example not covered by the appended claims. Referring to <FIG>, a semiconductor structure or device 200B, e.g. a planar version of device 200A of <FIG>, includes a planar diffusion or active region 204B disposed in substrate <NUM>, and within isolation region <NUM>. Gate line 208B is disposed over the planar diffusion or active region 204B as well as over a portion of the isolation region <NUM>. As shown, gate line 208B includes a gate electrode <NUM> and gate dielectric layer <NUM>. As well, a dielectric cap layer <NUM> may be disposed on the gate electrode, e.g., a dielectric cap layer for protecting a metal gate electrode. Gate contact via <NUM> is also seen from this perspective, along with an overlying metal interconnect <NUM>, both of which are disposed in inter-layer dielectric stacks or layers <NUM>. Also seen from the perspective of <FIG>, the gate contact via <NUM> is disposed over planar diffusion or active region 204B.

<FIG> illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an example not covered by the appended claims. Referring to <FIG>, a semiconductor structure or device 200C, e.g. a non-planar version of device 200A of <FIG>, includes a non-planar diffusion or active region 204C (e.g., a fin structure) formed from substrate <NUM>, and within isolation region <NUM>. Gate line 208B is disposed over the non-planar diffusion or active region 204C as well as over a portion of the isolation region <NUM>. As shown, gate line 208B includes a gate electrode <NUM> and gate dielectric layer <NUM>, along with a dielectric cap layer <NUM>. The gate
contact via <NUM> is also seen from this perspective, along with an overlying metal interconnect <NUM>, both of which are disposed in inter-layer dielectric stacks or layers <NUM>. Also seen from the perspective of <FIG>, the gate contact via <NUM> is disposed over non-planar diffusion or active region 204C.

Thus, referring again to <FIG>, trench contact vias 212A, 212B and gate contact via <NUM> are formed in a same layer and are essentially co-planar. In comparison to <FIG>, the contact to the gate line would otherwise include and additional gate contact layer, e.g., which could be run perpendicular to the corresponding gate line. In the structure(s) described in association with <FIG>, however, the fabrication of structures 200A-200C, respectively, enables the landing of a contact directly from a metal interconnect layer on an active gate portion without shorting to adjacent source drain regions. Such an arrangement provides a large area reduction in circuit layout by eliminating the need to extend transistor gates on isolation to form a reliable contact. As used throughout, in an embodiment, reference to an active portion of a gate refers to that portion of a gate line or structure disposed over (from a plan view perspective) an active or diffusion region of an underlying substrate. In an embodiment, reference to an inactive portion of a gate refers to that portion of a gate line or structure disposed over (from a plan view perspective) an isolation region of an underlying substrate.

The semiconductor structure or device <NUM> is a planar device, such as shown in <FIG>. In another example, the semiconductor structure or device <NUM> is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an example, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such example, the gate electrode stacks of gate lines 208A-208C surround at least a top surface and a pair of sidewalls of the three-dimensional body. In another example, at least the channel region is made to be a discrete three-dimensional body, such as in a gate-all-around device. In one such example, the gate electrode stacks of gate lines 208A-208C each completely surrounds the channel region.

Substrate <NUM> may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an example, substrate <NUM> is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form diffusion or active region <NUM>. In one example, the concentration of silicon atoms in bulk substrate <NUM> is greater than <NUM>%. In another example, bulk substrate <NUM> is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate <NUM> may
alternatively be composed of a group III-V material. In an example, bulk substrate <NUM> is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one example, bulk substrate <NUM> is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In an alternative example, substrate <NUM> is a silicon- or semiconductor-on insulator (SOI) substrate.

Isolation region <NUM> may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region <NUM> is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate lines 208A, 208B and 208C maybe composed of gate electrode stacks which each include a gate dielectric layer and a gate electrode layer (not shown as separate layers herein). In an example, the gate electrode of gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate <NUM>. In an example, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one example, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

In one example, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific example the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer.

Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, example
the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Any or all of contacts 210A and 210B and vias 212A, 212B and <NUM> maybe composed of a conductive material. In an example, contacts any or all of these contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

More generally, one or more embodiments are directed to approaches for, and structures formed from, landing a gate contact via directly on an active transistor gate. Such approaches may eliminate the need for extension of a gate line on isolation for contact purposes. Such approaches may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from a gate line or structure. In an embodiment, eliminating the above features is achieved by recessing contact metals in a trench contact (TCN) and introducing an additional dielectric material in the process flow (e.g., TILA). The additional dielectric material is included as a trench contact dielectric cap layer with etch characteristics different from the gate dielectric material cap layer already used for trench contact alignment in a gate aligned contact process (GAP ) processing scheme (e.g., GILA).

As an exemplary fabrication scheme not covered by the claims, <FIG> illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate.

Referring to <FIG>, a semiconductor structure <NUM> is provided following trench contact (TCN) formation. It is to be understood that the specific arrangement of structure <NUM> is used for illustration purposes only. The semiconductor structure <NUM> includes one or more gate stack structures, such as gate stack structures 308A-308E disposed above a substrate <NUM>. The gate stack structures may include a gate dielectric layer and a gate electrode, as described above in association with <FIG>. Trench contacts, e.g., contacts to diffusion regions of substrate <NUM>, such as trench contacts 310A-310C are also included in structure <NUM> and are spaced apart from gate stack structures 308A-308E by dielectric spacers <NUM>. An insulating cap layer <NUM> may be disposed on the gate stack structures 308A-308E (e.g., GILA), as is also depicted in <FIG>. As is also depicted in <FIG>, contact blocking regions or "contact plugs," such as region <NUM> fabricated from an inter-layer dielectric material, may be included in regions where contact formation is to be blocked.

A process used to provide structure <NUM> may be one described in International Patent.

Application No. <CIT>,. For example, a trench contact etch engineered selective to the insulating cap layer <NUM> may be used to form self-aligned contacts 310A-310C.

Providing structure <NUM> involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such example, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such example, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an example, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such example, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, the gate stack structures 308A-308E maybe fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such example, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an example, dummy gates are removed by a dry etch or wet etch process. In one example, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process comprising SF6. In another example, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process comprising aqueous NH4OH or tetramethylammonium hydroxide. In one example, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an example, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure <NUM>. In one such example, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately <NUM> degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

Referring to <FIG>, the trench contacts 310A-310C of the structure <NUM> are recessed
within spacers <NUM> to provide recessed trench contacts 311A-311C that have a height below the top surface of spacers <NUM> and insulating cap layer <NUM>. An insulating cap layer <NUM> is then formed on recessed trench contacts 311A-311C (e.g., TILA). In accordance with an example, the insulating cap layer <NUM> on recessed trench contacts 311A-311C is composed of a material having a different etch characteristic than insulating cap layer <NUM> on gate stack structures 308A-308E. As will be seen in subsequent processing operations, such a difference may be exploited to etch one of <NUM>/<NUM> selectively from the other of <NUM>/<NUM>.

The trench contacts 310A-310C maybe recessed by a process selective to the materials of spacers <NUM> and insulating cap layer <NUM>. For example, the trench contacts 310A-310C are recessed by an etch process such as a wet etch process or dry etch process. Insulating cap layer <NUM> may be formed by a process suitable to provide a conformal and sealing layer above the exposed portions of trench contacts 310A-310C. For example, in one embodiment, insulating cap layer <NUM> is formed by a chemical vapor deposition (CVD) process as a conformal layer above the entire structure. The conformal layer is then planarized, e.g., by chemical mechanical polishing (CMP), to provide insulating cap layer <NUM> material only above trench contacts 310A-310C, and re-exposing spacers <NUM> and insulating cap layer <NUM>.

Regarding suitable material combinations for insulating cap layers <NUM>/<NUM>, in one example, one of the pair of <NUM>/<NUM> is composed of silicon oxide while the other is composed of silicon nitride. In another example, one of the pair of <NUM>/<NUM> is composed of silicon oxide while the other is composed of carbon doped silicon nitride.

In another example, one of the pair of <NUM>/<NUM> is composed of silicon oxide while the other is composed of silicon carbide. In another example, one of the pair of <NUM>/<NUM> is composed of silicon nitride while the other is composed of carbon doped silicon nitride. In another example, one of the pair of <NUM>/<NUM> is composed of silicon nitride while the other is composed of silicon carbide. In another example, one of the pair of <NUM>/<NUM> is composed of carbon doped silicon nitride while the other is composed of silicon carbide.

Referring to <FIG>, an inter-layer dielectric (ILD) <NUM> and hardmask <NUM> stack is formed and patterned to provide, e.g., a metal (<NUM>) trench <NUM> patterned above the structure of <FIG>.

The inter-layer dielectric (ILD) <NUM> may be composed of a material suitable to electrically isolate metal features ultimately formed therein while maintaining a robust structure between front end and back end processing. Furthermore, in an, the composition of the ILD <NUM> is selected to be consistent with via etch selectivity for trench contact dielectric cap layer and gate dielectric cap layer patterning, as described in greater detail below in association with <FIG> and <FIG>. In one, the ILD <NUM> is composed of a single or several layers of
silicon oxide or a single or several layers of a carbon doped oxide (CDO) material. However, in other examples, the ILD <NUM> has a bi-layer composition with a top portion composed of a different material than an underlying bottom portion of the ILD <NUM>, as described in greater detail below in association with <FIG>. The hardmask layer <NUM> may be composed of a material suitable to act as a subsequent sacrificial layer. For example, the hardmask layer <NUM> is composed substantially of carbon, e.g., as a layer of cross-linked organic polymer. In other examples, a silicon nitride or carbon-doped silicon nitride layer is used as a hardmask <NUM>. The inter-layer dielectric (ILD) <NUM> and hardmask <NUM> stack may be patterned by a lithography and etch process.

Referring to <FIG>, via openings <NUM> (e.g., VCT) are formed in inter-layer dielectric (ILD) <NUM>, extending from metal (<NUM>) trench <NUM> to one or more of the recessed trench contacts 311A-311C. For example, in <FIG>, via openings are formed to expose recessed trench contacts 311A and 311C. The formation of via openings <NUM> includes etching of both inter-layer dielectric (ILD) <NUM> and respective portions of corresponding insulating cap layer <NUM>. In one such example, a portion of insulating cap layer <NUM> is exposed during patterning of inter-layer dielectric (ILD) <NUM> (e.g., a portion of insulating cap layer <NUM> over gate stack structures 308B and 308E is exposed). In that example, insulating cap layer <NUM> is etched to form via openings <NUM> selective to (i.e., without significantly etching or impacting) insulating cap layer <NUM>.

The via openings <NUM> may be formed by first depositing a hardmask layer, an anti-reflective coating (ARC) layer and a layer of photoresist. In an example, the hardmask layer is composed substantially of carbon, e.g., as a layer of cross-linked organic polymer. In an example, the ARC layer is suitable to suppress reflective interference during lithographic patterning of the photo-resist layer. In one such example, the ARC layer is a silicon ARC layer. The photo-resist layer may be composed of a material suitable for use in a lithographic process. In one embodiment, the photo-resist layer is formed by first masking a blanket layer of photo-resist material and then exposing it to a light source. A patterned photo-resist layer may then be formed by developing the blanket photo-resist layer. In an example, the portions of the photo-resist layer exposed to the light source are removed upon developing the photo-resist layer. Thus, patterned photo-resist layer is composed of a positive photo-resist material. In a specific example, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a <NUM> resist, a <NUM> resist, a <NUM> resist, an extreme ultra violet (EUV) resist, an e-beam imprint layer, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another example, the portions of the photo-resist layer exposed to the light source are retained upon developing the photo-resist layer. Thus, the photo-resist layer is
composed of a negative photo-resist material. In a specific example, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, consisting of poly-cis-isoprene or poly-vinyl-cinnamate.

In accordance with an example, the pattern of the photo-resist layer (e.g., the pattern of via openings <NUM>) is transferred to the hardmask layer by using a plasma etch process. The pattern is ultimately transferred to the inter-layer dielectric (ILD) <NUM>, e.g., by another or the same dry etch process. In one example, the pattern is then finally transferred to the insulating cap layer <NUM> (i.e., the trench contact insulating cap layers) by an etch process without etching the insulating cap layer <NUM> (i.e., the gate insulating cap layers). The insulating cap layer <NUM> (TILA) may be composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, various metal oxides and silicates including zirconium oxide, hafnium oxide, lanthanum oxide or a combination thereof. The layer may be deposited using any of the following techniques including CVD, ALD, PECVD, PVD, HDP assisted CVD, low temp CVD. A corresponding plasma dry etch is developed as a combination of chemical and physical sputtering mechanisms. Coincident polymer deposition may be used to control material removal rate, etch profiles and film selectivity. The dry etch is typically generated with a mix of gases that include NF3, CHF3, C4Fg, HBr and <NUM> with typically pressures in the range of <NUM>-<NUM> mTorr and a plasma bias of <NUM>-<NUM> Watts. The dry etch may be engineered to achieve significant etch selectivity between cap layer <NUM> (TILA) and <NUM> (GILA) layers to minimize the loss of <NUM> (GILA) during dry etch of <NUM> (TILA) to form contacts to the source drain regions of the transistor.

Referring to <FIG>, one or more additional via openings <NUM> (e.g., VCG) are formed in inter-layer dielectric (ILD) <NUM>, extending from metal (<NUM>) trench <NUM> to one or more of the gate stack structures 308A-308E. For example, in <FIG>, via openings are formed to expose gate stack structures 308C and 308D. The formation of via openings <NUM> includes etching of both inter-layer dielectric (ILD) <NUM> and respective portions of corresponding insulating cap layer <NUM>. In one such example, a portion of insulating cap layer <NUM> is exposed during patterning of inter-layer dielectric (ILD) <NUM> (e.g., a portion of insulating cap layer <NUM> over recessed trench contact <NUM> IB is exposed). In that example, insulating cap layer <NUM> is etched to form via openings <NUM> selective to (i.e., without significantly etching or impacting) insulating cap layer <NUM>.

Similar to forming the via openings <NUM>, the via openings <NUM> may be formed by first depositing a hardmask layer, an anti-reflective coating (ARC) layer and a layer of photoresist. In accordance with an, the pattern of the photo-resist layer
(e.g., the pattern of via openings <NUM>) is transferred to the hardmask layer by using a plasma etch process. The pattern is ultimately transferred inter-layer dielectric (ILD) <NUM>, e.g., by another or the same dry etch process. In one example, the pattern is then finally transferred to the insulating cap layer <NUM> (i.e., the gate insulating cap layers) by an etch process without etching the insulating cap layer <NUM> (i.e., the trench contact insulating cap layers). The insulating cap layer <NUM> (GILA) may be composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, various metal oxides and silicates including zirconium oxide, hafnium oxide, lanthanum oxide or a combination thereof. The layer may be deposited using any of the following techniques including CVD, ALD, PECVD, PVD, HDP assisted CVD, low temp CVD. The insulating cap layer <NUM> (GILA) is, in an example, composed of a different material relative to cap layer <NUM> (TILA) to ensure significant etch rate differential between the two capping layers. A corresponding plasma dry etch may be developed as a combination of chemical and physical sputtering mechanisms to achieve acceptable etch rate differential between GILA and TILA films. Coincident polymer deposition may be used to control material removal rate, etch profiles and film selectivity. The dry etch is typically generated with a mix of gases that include NF3, CHF , C4F8, HBr and <NUM> with typically pressures in the range of <NUM>-<NUM> mTorr and a plasma bias of <NUM>-<NUM> Watts. The dry etch may be engineered to achieve significant etch selectivity between cap layer <NUM> (GILA) and <NUM> (TILA) layers to minimize the loss of <NUM> (TILA) during dry etch of <NUM> (GILA) to form the gate contact on active regions of the transistor.

Referring to <FIG>, a metal contact structure <NUM> is formed in the metal (<NUM>) trench <NUM> and via openings <NUM> and <NUM> of the structure described in association with <FIG>. The metal contact structure <NUM> includes a metal (<NUM>) portion <NUM> along with trench contact vias (e.g., trench contact vias 341A and 341B to trench contacts 311A and 311C, respectively) and gate contact vias (e.g., gate contact vias 342A and 342B to gate stack structures 308C and 308D, respectively).

In an embodiment, the metal contact structure is formed by a metal deposition and subsequent chemical mechanical polishing operation. The metal deposition may involve first deposition of an adhesion layer followed by deposition of a fill metal layer. Thus, the metal structure <NUM> may be composed of a conductive material. In an example, the metal structure <NUM> is composed of a metal species. The metal species may be a pure metal, such as copper, tungsten, nickel or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

As mentioned briefly above in association with <FIG>, ILD <NUM> may instead be a bi-layer structure. As an example, <FIG> illustrates a cross-sectional view of another non-planar
semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with another example not covered by the claims. Referring to <FIG>, a semiconductor structure or device <NUM>, e.g. a non-planar device, includes a non-planar diffusion or active region <NUM> (e.g., a fin structure) formed from substrate <NUM>, and within isolation region <NUM>. A gate electrode stack <NUM> is disposed over the non-planar diffusion or active region <NUM> as well as over a portion of the isolation region <NUM>. As shown, gate electrode stack <NUM> includes a gate electrode <NUM> and gate dielectric layer <NUM>, along with a dielectric cap layer <NUM>. The gate electrode stack <NUM> is disposed in an inter-layer dielectric layer <NUM>, such as a layer of silicon oxide. A gate contact via <NUM> and an overlying metal interconnect <NUM> are both disposed in inter-layer dielectric (ILD) stacks or layers <NUM>. In an example, structure <NUM> is a bi-layer interlayer dielectric stack including a bottom layer <NUM> and a top layer <NUM>, as depicted in <FIG>.

In an example, the top layer <NUM> of ILD structure <NUM> is composed of a material optimized for low-K performance, e.g., for reducing capacitive coupling between metal lines formed therein. In one such example, the top layer <NUM> of ILD structure <NUM> is composed of a material such as, but not limited to, a carbon-doped oxide (CDO) or porous oxide film. In an example, the bottom layer <NUM> of ILD structure <NUM> is composed of a material optimized for via etch selectivity, e.g., for compatibility with an integration scheme leveraging the etch selectivities between a trench contact cap layer and a gate cap layer. In one such example, the bottom layer <NUM> of ILD structure <NUM> is composed of a material such as, but not limited to, silicon dioxide (Si02) or a CDO film. In a specific example, the top layer <NUM> of ILD structure <NUM> is composed of a CDO material and the bottom layer <NUM> of ILD structure <NUM> is composed of Si02.

In the process flow, described in association with <FIG>, the tops of the spacers <NUM> are exposed during via opening formation in cap layers <NUM> and <NUM>. In the case that the material of spacers <NUM> is different from that of the cap layers <NUM> and <NUM>, and additional etch selectivity consideration may have to be accounted for in order to hinder unwanted degradation of the spacers during via opening formation. In an embodiment, the spacers may be recessed to be essentially planar with the gate structures. In such an embodiment, the gate cap layer may be formed to cover the spacers, hindering exposure of the spacers during via opening formation. As an example, <FIG> illustrate cross-sectional views representing various operations in a method of fabricating another semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present invention.

Referring to <FIG>, a semiconductor structure <NUM> is provided following trench contact (TCN) formation. It is to be understood that the specific arrangement of structure <NUM> is used for illustration purposes only, and that a variety of possible layouts may benefit from embodiments of the invention described herein. The semiconductor structure <NUM> includes one or more gate stack structures, such as gate stack structures 308A-308E disposed above a substrate <NUM>. The gate stack structures include a gate dielectric layer and a gate electrode, as described above in association with <FIG>. Trench contacts, e.g., contacts to diffusion regions of substrate <NUM>, such as trench contacts 310A-310C are also included in structure <NUM> and are spaced apart from gate stack structures 308A-308E by dielectric spacers <NUM>. An insulating cap layer <NUM> is disposed on the gate stack structures 308A-308E (e.g., GILA), as is also depicted in <FIG>. However, in contrast to the structure <NUM> described in association with <FIG>, the spacers <NUM> have been recessed to approximately the same height as the gate stack structures 308A-308E. As such, the corresponding insulating cap layers <NUM> cover the spacers <NUM> associated with each gate stack, as well as covering the gate stack.

Referring to <FIG>, a metal contact structure <NUM> is formed in a metal (<NUM>) trench and via openings formed in a dielectric layer <NUM>. The metal contact structure <NUM> includes a metal (<NUM>) portion <NUM> along with trench contact vias (e.g., trench contact vias 341A and 341B to trench contacts 311A and 311C, respectively). The metal contact structure <NUM> also includes gate contact vias (e.g., gate contact vias 542A and 542B to gate stack structures 308C and 308D, respectively). In comparison to the structure described in association with <FIG>, the resulting structure of <FIG> is slightly different since the spacers <NUM> are not exposed, yet coverage of the insulating cap layers <NUM> is extended, during etch formation of the via openings leading to gate contact vias 542A and 542B.

Referring again to <FIG>, in an embodiment, the trench contacts (including trench contacts labeled 311A and 311C in <FIG>) are recessed lower relative to the gate stack structures (including gate stack structures labeled 308C and 308D in <FIG>). The trench contacts are recessed lower relative to the gate stack structures in order to prevent a possibility of shorting between gate contact vias 542A and 542B and trench contacts 311A and 311C, respectively, e.g., at the corners where gate contact vias 542A and 542B and trench contacts 311A and 311C, respectively, would otherwise meet if the trench contacts were co-planar with the gate stack structures.

Furthermore, in an example not covered by the claims, (not shown), spacers are recessed to approximately the same height as the trench contacts. The corresponding trench insulating cap layers (TILA) cover the spacers associated with each trench contact, as well as covering the trench contact. In one such example, the gate stack structures are recessed lower relative to the trench contacts in order to prevent a possibility of shorting between trench contact vias and adjacent or nearby.

The approaches and structures described herein may enable formation of other structures or devices that were not possible or difficult to fabricate using conventional methodologies. In a first example, <FIG> illustrates a plan view of another semiconductor device having a gate contact via disposed over an active portion of a gate, in accordance with another example not covered by the claims. Referring to <FIG>, a semiconductor structure or device <NUM> includes a plurality of gate structures 608A-608C interdigitated with a plurality of trench contacts <NUM> OA and 610B (these features are disposed above an active region of a substrate, not shown). A gate contact via <NUM> is formed on an active portion the gate structure 608B. The gate contact via <NUM> is further disposed on the active portion of the gate structure 608C, coupling gate structures 608B and 608C. It is to be understood that the intervening trench contact 610B may be isolated from the contact <NUM> by using a trench contact isolation cap layer (e.g., TILA). The contact configuration of <FIG> may provide an easier approach to strapping adjacent gate lines in a layout, without the need to route the strap through upper layers of metallization, hence enabling smaller cell areas and/or less intricate wiring schemes.

In a second example, <FIG> illustrates a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts, in accordance with another example not covered by the claims. Referring to <FIG>, a semiconductor structure or device <NUM> includes a plurality of gate structures 708A-708C interdigitated with a plurality of trench contacts <NUM> OA and 710B (these features are disposed above an active region of a substrate, not shown). A trench contact via <NUM> is formed on the trench contact 710A. The trench contact via <NUM> is further disposed on the trench contact 710B, coupling trench contacts 710A and 710B. It is to be understood that the intervening gate structure 708B may be isolated from the trench contact via <NUM> by using a gate isolation cap layer (e.g., by a GILA process). The contact configuration of <FIG> may provide an easier approach to strapping adjacent trench contacts in a layout, without the need to route the strap through upper layers of metallization, hence enabling smaller cell areas and/or less intricate wiring schemes.

It is to be understood that not all aspects of the processes described above need be practiced to fall within the scope of embodiments of the present invention. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein maybe used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors.

Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a <NUM> or smaller technology node.

In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present invention include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the invention. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The term "wireless" and its derivatives maybe used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The communication chip <NUM> may implement
any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE
<NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond.

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Claim 1:
A semiconductor structure (<NUM>), comprising:
a substrate (<NUM>) comprising an active region and an isolation region;
a plurality of gate structures (308A-308E), each having a portion disposed above the active region and a portion disposed above the isolation region of the substrate (<NUM>), wherein one or more of the plurality of gate structures (308A-308E) comprises a gate cap dielectric layer (<NUM>) on a top surface of the gate structure, the gate cap dielectric layer (<NUM>) having a top surface, and wherein the gate cap dielectric layer (<NUM>) comprises a first material;
a plurality of source or drain regions disposed in the active region of the substrate (<NUM>), between the portions of the gate structures (308A-308E) disposed above the active region;
a plurality of source or drain contacts (311A-311C), a source or drain contact disposed on each of the source or drain regions, one or more of the plurality of source or drain contacts (311A-311C) comprising a trench cap dielectric layer (<NUM>) on a top surface of the source or drain contact, the source or drain contacts (311A-311C) having a top surface below the top surface of the gate structures (308A-308E), and the trench cap dielectric layer (<NUM>) having a top surface co-planar with the top surface of the gate cap dielectric layer (<NUM>), wherein the trench cap dielectric layer (<NUM>) comprises a second material with a different etch characteristic than the first material;
a gate contact via (<NUM>) disposed on one of the gate structures (308A-308E) only partially covered by the gate cap dielectric layer (<NUM>), on the portion of the gate structure disposed above the active region of the substrate (<NUM>); and
a source or drain contact via (<NUM>) disposed on one of the source or drain contacts (311A-311C) only partially covered by the trench cap dielectric layer (<NUM>);
wherein each of the gate structures (308A-308E) further comprises a pair of sidewall spacers, wherein the source or drain contacts (311A-311C) are disposed directly adjacent to the sidewall spacers of a corresponding gate structure, and wherein the sidewall spacers have a same height as the gate structures (308A-308E) and are covered by the gate cap dielectric layer (<NUM>).