Patent Description:
Memories (e.g., memory devices) are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.

In programming memory, memory cells might be programmed as what are often termed single-level cells (SLC). SLC may use a single memory cell to represent one digit (e.g., one bit) of data. For example, in SLC, a Vt of <NUM>. 5V or higher might indicate a programmed memory cell (e.g., representing a logical <NUM>) while a Vt of -<NUM>. 5V or lower might indicate an erased memory cell (e.g., representing a logical <NUM>). Such memory might achieve higher levels of storage capacity by including multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., or combinations thereof in which the memory cell has multiple levels that enable more digits of data to be stored in each memory cell. For example, MLC might be configured to store two digits of data per memory cell represented by four Vt ranges, TLC might be configured to store three digits of data per memory cell represented by eight Vt ranges, QLC might be configured to store four digits of data per memory cell represented by sixteen Vt ranges, and so on.

Sensing (e.g., reading or verifying) a data state of a memory cell often involves detecting whether the memory cell is activated in response to a particular voltage applied to its control gate, such as by detecting whether a data line connected to the memory cell experiences a change in voltage level caused by current flow through the memory cell. As memory operation advances to represent additional data states per memory cell, the margins between adjacent Vt ranges can become smaller. This can lead to an inaccurate determination of the data state of a sensed memory cell if the Vt of the sensed memory cell shifts over time.

Threshold voltages of memory cells may shift due to such phenomena as quick charge loss (QCL). QCL is a de-trapping of electrons near a gate dielectric interface out to the channel region of the memory cell, and can cause a Vt shift shortly after a programming pulse. When a memory cell passes the verify operation, the programmed threshold voltage may appear to be higher due to the trapped charge in the gate dielectric. When the memory cell is read after the program operation has been completed, the memory cell may have a Vt that is lower than the Vt obtained during the program verify operation due to the charge in the gate dielectric leaking out to the channel region.

Threshold voltages of memory cells may further shift due to cumulative charge loss over the age of their programmed data, e.g., a period of time between programming the data and reading the data, referred to herein as data age. Such charge loss can become more pronounced as the data storage structures become smaller.

Furthermore, threshold voltages of memory cells may shift due to read disturb. In read disturb, the threshold voltage of a memory cell may shift in response to the voltage applied to the memory cell to facilitate access to the target memory cell selected for reading, e.g., increasing the threshold voltage of the memory cell.

<CIT> describes sense circuits that vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

The invention is defined by the features of independent claim.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments might be utilized and structural, logical and electrical changes might be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term "semiconductor" used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term "conductive" as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term "connecting" as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

It is recognized herein that even where values might be intended to be equal, variabilities and accuracies of industrial processing and operation might lead to differences from their intended values. These variabilities and accuracies will generally be dependent upon the technology utilized in fabrication and operation of the integrated circuit device. As such, if values are intended to be equal, those values are deemed to be equal regardless of their resulting values.

<FIG> is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device) <NUM>, in communication with a second apparatus, in the form of a processor <NUM>, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor <NUM>, e.g., a controller external to the memory device <NUM>, might be a memory controller or other external host device.

Memory device <NUM> includes an array of memory cells <NUM> that might be logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in <FIG>) of at least a portion of array of memory cells <NUM> are capable of being programmed to one of at least two target data states.

A row decode circuitry <NUM> and a column decode circuitry <NUM> are provided to decode address signals. Address signals are received and decoded to access the array of memory cells <NUM>. Memory device <NUM> also includes input/output (I/O) control circuitry <NUM> to manage input of commands, addresses and data to the memory device <NUM> as well as output of data and status information from the memory device <NUM>. An address register <NUM> is in communication with I/O control circuitry <NUM> and row decode circuitry <NUM> and column decode circuitry <NUM> to latch the address signals prior to decoding. A command register <NUM> is in communication with I/O control circuitry <NUM> and control logic <NUM> to latch incoming commands.

A controller (e.g., the control logic <NUM> internal to the memory device <NUM>) controls access to the array of memory cells <NUM> in response to the commands and may generate status information for the external processor <NUM>, i.e., control logic <NUM> is configured to perform access operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells <NUM>. The control logic <NUM> is in communication with row decode circuitry <NUM> and column decode circuitry <NUM> to control the row decode circuitry <NUM> and column decode circuitry <NUM> in response to the addresses. The control logic <NUM> might include instruction registers <NUM> which might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction registers <NUM> might represent firmware. Alternatively, the instruction registers <NUM> might represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells <NUM>.

Control logic <NUM> might also be in communication with a cache register <NUM>. Cache register <NUM> latches data, either incoming or outgoing, as directed by control logic <NUM> to temporarily store data while the array of memory cells <NUM> is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache register <NUM> to the data register <NUM> for transfer to the array of memory cells <NUM>; then new data might be latched in the cache register <NUM> from the I/O control circuitry <NUM>. During a read operation, data might be passed from the cache register <NUM> to the I/O control circuitry <NUM> for output to the external processor <NUM>; then new data might be passed from the data register <NUM> to the cache register <NUM>. The cache register <NUM> and/or the data register <NUM> might form (e.g., might form a portion of) a page buffer of the memory device <NUM>. A page buffer might further include sensing devices (not shown in <FIG>) to sense a data state of a memory cell of the array of memory cells <NUM>, e.g., by sensing a state of a data line connected to that memory cell. A status register <NUM> might be in communication with I/O control circuitry <NUM> and control logic <NUM> to latch the status information for output to the processor <NUM>.

Memory device <NUM> receives control signals at control logic <NUM> from processor <NUM> over a control link <NUM>. The control signals might include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP#. Additional or alternative control signals (not shown) might be further received over control link <NUM> depending upon the nature of the memory device <NUM>. Memory device <NUM> receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor <NUM> over a multiplexed input/output (I/O) bus <NUM> and outputs data to processor <NUM> over I/O bus <NUM>.

For example, the commands might be received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and might then be written into command register <NUM>. The addresses might be received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and might then be written into address register <NUM>. The data might be received over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device at I/O control circuitry <NUM> and then might be written into cache register <NUM>. The data might be subsequently written into data register <NUM> for programming the array of memory cells <NUM>. For another embodiment, cache register <NUM> might be omitted, and the data might be written directly into data register <NUM>. Data might also be output over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device. Although reference might be made to I/O pins, they might include any conductive nodes providing for electrical connection to the memory device <NUM> by an external device (e.g., processor <NUM>), such as conductive pads or conductive bumps as are commonly used.

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device <NUM> of <FIG> has been simplified. It should be recognized that the functionality of the various block components described with reference to <FIG> might not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of <FIG>. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of <FIG>.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.

<FIG> is a schematic of a portion of an array of memory cells 200A, such as a NAND memory array, as could be used in a memory of the type described with reference to <FIG>, e.g., as a portion of array of memory cells <NUM>. Memory array 200A includes access lines (e.g., word lines) <NUM><NUM> to <NUM>N, and data lines (e.g., bit lines) <NUM><NUM> to <NUM>M. The access lines <NUM> might be connected to global access lines (e.g., global word lines), not shown in <FIG>, in a many-to-one relationship. For some embodiments, memory array 200A might be formed over a semiconductor that, for example, might be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array 200A might be arranged in rows (each corresponding to an access line <NUM>) and columns (each corresponding to a data line <NUM>). Each column might include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings <NUM><NUM> to <NUM>M. Each NAND string <NUM> might be connected (e.g., selectively connected) to a common source (SRC) <NUM> and might include memory cells <NUM><NUM> to <NUM>N. The memory cells <NUM> might represent non-volatile memory cells for storage of data. The memory cells <NUM><NUM> to <NUM>N might include memory cells intended for storage of data, and might further include other memory cells not intended for storage of data, e.g., dummy memory cells. Dummy memory cells are typically not accessible to a user of the memory, and are instead typically incorporated into the string of series-connected memory cells for operational advantages that are well understood.

The memory cells <NUM> of each NAND string <NUM> might be connected in series between a select gate <NUM> (e.g., a field-effect transistor), such as one of the select gates <NUM><NUM> to <NUM>M (e.g., that might be source select transistors, commonly referred to as select gate source), and a select gate <NUM> (e.g., a field-effect transistor), such as one of the select gates <NUM><NUM> to <NUM>M (e.g., that might be drain select transistors, commonly referred to as select gate drain). Select gates <NUM><NUM> to <NUM>M might be commonly connected to a select line <NUM>, such as a source select line (SGS), and select gates <NUM><NUM> to <NUM>M might be commonly connected to a select line <NUM>, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates <NUM> and <NUM> might utilize a structure similar to (e.g., the same as) the memory cells <NUM>. The select gates <NUM> and <NUM> might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

A source of each select gate <NUM> might be connected to common source <NUM>. The drain of each select gate <NUM> might be connected to a memory cell <NUM><NUM> of the corresponding NAND string <NUM>. For example, the drain of select gate <NUM><NUM> might be connected to memory cell <NUM><NUM> of the corresponding NAND string <NUM><NUM>. Therefore, each select gate <NUM> might be configured to selectively connect a corresponding NAND string <NUM> to common source <NUM>. A control gate of each select gate <NUM> might be connected to select line <NUM>.

The drain of each select gate <NUM> might be connected to the data line <NUM> for the corresponding NAND string <NUM>. For example, the drain of select gate <NUM><NUM> might be connected to the data line <NUM><NUM> for the corresponding NAND string <NUM><NUM>. The source of each select gate <NUM> might be connected to a memory cell <NUM>N of the corresponding NAND string <NUM>. For example, the source of select gate <NUM><NUM> might be connected to memory cell <NUM>N of the corresponding NAND string <NUM><NUM>. Therefore, each select gate <NUM> might be configured to selectively connect a corresponding NAND string <NUM> to the corresponding data line <NUM>. A control gate of each select gate <NUM> might be connected to select line <NUM>.

The memory array in <FIG> might be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source <NUM>, NAND strings <NUM> and data lines <NUM> extend in substantially parallel planes. Alternatively, the memory array in <FIG> might be a three-dimensional memory array, e.g., where NAND strings <NUM> might extend substantially perpendicular to a plane containing the common source <NUM> and to a plane containing the data lines <NUM> that might be substantially parallel to the plane containing the common source <NUM>.

Typical construction of memory cells <NUM> includes a data-storage structure <NUM> (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate <NUM>, as shown in <FIG>. The data-storage structure <NUM> might include both conductive and dielectric structures while the control gate <NUM> is generally formed of one or more conductive materials. In some cases, memory cells <NUM> might further have a defined source/drain (e.g., source) <NUM> and a defined source/drain (e.g., drain) <NUM>. Memory cells <NUM> have their control gates <NUM> connected to (and in some cases form) an access line <NUM>.

A column of the memory cells <NUM> might be a NAND string <NUM> or a plurality of NAND strings <NUM> selectively connected to a given data line <NUM>. A row of the memory cells <NUM> might be memory cells <NUM> commonly connected to a given access line <NUM>. A row of memory cells <NUM> can, but need not, include all memory cells <NUM> commonly connected to a given access line <NUM>. Rows of memory cells <NUM> might often be divided into one or more groups of physical pages of memory cells <NUM>, and physical pages of memory cells <NUM> often include every other memory cell <NUM> commonly connected to a given access line <NUM>. For example, memory cells <NUM> commonly connected to access line <NUM>N and selectively connected to even data lines <NUM> (e.g., data lines <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc.) might be one physical page of memory cells <NUM> (e.g., even memory cells) while memory cells <NUM> commonly connected to access line <NUM>N and selectively connected to odd data lines <NUM> (e.g., data lines <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc.) might be another physical page of memory cells <NUM> (e.g., odd memory cells). Although data lines <NUM><NUM>-<NUM><NUM> are not explicitly depicted in <FIG>, it is apparent from the figure that the data lines <NUM> of the array of memory cells 200A might be numbered consecutively from data line <NUM><NUM> to data line <NUM>M. Other groupings of memory cells <NUM> commonly connected to a given access line <NUM> might also define a physical page of memory cells <NUM>. For certain memory devices, all memory cells commonly connected to a given access line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells might include those memory cells that are configured to be erased together, such as all memory cells connected to access lines <NUM><NUM>-<NUM>N (e.g., all NAND strings <NUM> sharing common access lines <NUM>). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

Although the example of <FIG> is discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS or other data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

<FIG> is another schematic of a portion of an array of memory cells 200B as could be used in a memory of the type described with reference to <FIG>, e.g., as a portion of array of memory cells <NUM>. Like numbered elements in <FIG> correspond to the description as provided with respect to <FIG>. <FIG> provides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B might incorporate vertical structures which might include semiconductor pillars where a portion of a pillar might act as a channel region of the memory cells of NAND strings <NUM>. The NAND strings <NUM> might be each selectively connected to a data line <NUM><NUM>-<NUM>M by a select transistor <NUM> (e.g., that might be drain select transistors, commonly referred to as select gate drain) and to a common source <NUM> by a select transistor <NUM> (e.g., that might be source select transistors, commonly referred to as select gate source). Multiple NAND strings <NUM> might be selectively connected to the same data line <NUM>. Subsets of NAND strings <NUM> can be connected to their respective data lines <NUM> by biasing the select lines <NUM><NUM>-<NUM>K to selectively activate particular select transistors <NUM> each between a NAND string <NUM> and a data line <NUM>. The select transistors <NUM> can be activated by biasing the select line <NUM>. Each access line <NUM> might be connected to multiple rows of memory cells of the memory array 200B. Rows of memory cells that are commonly connected to each other by a particular access line <NUM> might collectively be referred to as tiers.

The three-dimensional NAND memory array 200B might be formed over peripheral circuitry <NUM>. The peripheral circuitry <NUM> might represent a variety of circuitry for accessing the memory array 200B. The peripheral circuitry <NUM> might include complementary circuit elements. For example, the peripheral circuitry <NUM> might include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience.

<FIG> is a further schematic of a portion of an array of memory cells 200C as could be used in a memory of the type described with reference to <FIG>, e.g., as a portion of array of memory cells <NUM>. Like numbered elements in <FIG> correspond to the description as provided with respect to <FIG>. Array of memory cells 200C may include strings of series-connected memory cells (e.g., NAND strings) <NUM>, access (e.g., word) lines <NUM>, data (e.g., bit) lines <NUM>, select lines <NUM> (e.g., source select lines), select lines <NUM> (e.g., drain select lines) and source <NUM> as depicted in <FIG>. A portion of the array of memory cells 200A may be a portion of the array of memory cells 200C, for example. <FIG> depicts groupings of NAND strings <NUM> into blocks of memory cells <NUM>, e.g., blocks of memory cells <NUM><NUM>-<NUM>L. Blocks of memory cells <NUM> may be groupings of memory cells <NUM> that may be erased together in a single erase operation, sometimes referred to as erase blocks. Each block of memory cells <NUM> might include those NAND strings <NUM> commonly associated with a single select line <NUM>, e.g., select line <NUM><NUM>. The source <NUM> for the block of memory cells <NUM><NUM> might be a same source as the source <NUM> for the block of memory cells <NUM>L. For example, each block of memory cells <NUM><NUM>-<NUM>L might be commonly selectively connected to the source <NUM>. Access lines <NUM> and select lines <NUM> and <NUM> of one block of memory cells <NUM> may have no direct connection to access lines <NUM> and select lines <NUM> and <NUM>, respectively, of any other block of memory cells of the blocks of memory cells <NUM><NUM>-<NUM>L.

The data lines <NUM><NUM>-<NUM>M may be connected (e.g., selectively connected) to a buffer portion <NUM>, which might be a portion of a data buffer of the memory. The buffer portion <NUM> might correspond to a memory plane (e.g., the set of blocks of memory cells <NUM><NUM>-<NUM>L). The buffer portion <NUM> might include sense circuits (not shown in <FIG>) for sensing data values indicated on respective data lines <NUM>.

While the blocks of memory cells <NUM> of <FIG> depict only one select line <NUM> per block of memory cells <NUM>, the blocks of memory cells <NUM> might include those NAND strings <NUM> commonly associated with more than one select line <NUM>. For example, select line <NUM><NUM> of block of memory cells <NUM><NUM> might correspond to the select line <NUM><NUM> of the memory array 200B of <FIG>, and the block of memory cells of the memory array 200C of <FIG> might further include those NAND strings <NUM> associated with select lines <NUM><NUM>-<NUM>K of <FIG>. In such blocks of memory cells <NUM> having NAND strings <NUM> associated with multiple select lines <NUM>, those NAND strings <NUM> commonly associated with a single select line <NUM> might be referred to as a sub-block of memory cells. Each such sub-block of memory cells might be selectively connected to the buffer portion <NUM> responsive to its respective select line <NUM>.

<FIG> is a conceptual depiction of threshold voltage ranges of a plurality of memory cells. <FIG> illustrates an example of threshold voltage ranges and their distributions for a population of a sixteen-level memory cells, often referred to as QLC memory cells. For example, such a memory cell might be programmed to a threshold voltage (Vt) that falls within one of sixteen different threshold voltage ranges <NUM><NUM>-<NUM><NUM>, each being used to represent a data state corresponding to a bit pattern of four bits. The threshold voltage range <NUM><NUM> typically has a greater width than the remaining threshold voltage ranges <NUM><NUM>-<NUM><NUM> as memory cells are generally all placed in the data state corresponding to the threshold voltage range <NUM><NUM>, then subsets of those memory cells are subsequently programmed to have threshold voltages in one of the threshold voltage ranges <NUM><NUM>-<NUM><NUM>. As programming operations are generally more incrementally controlled than erase operations, these threshold voltage ranges <NUM><NUM>-<NUM><NUM> may tend to have tighter distributions.

The threshold voltage ranges <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> might each represent a respective data state, e.g., L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14 and L15, respectively. As an example, if the threshold voltage of a memory cell is within the first of the sixteen threshold voltage ranges <NUM><NUM>, the memory cell in this case may be storing a data state L0 having a data value of logical '<NUM>' and is typically referred to as the erased state of the memory cell. If the threshold voltage is within the second of the sixteen threshold voltage ranges <NUM><NUM>, the memory cell in this case may be storing a data state L1 having a data value of logical '<NUM>'. If the threshold voltage is within the third of the sixteen threshold voltage ranges <NUM><NUM>, the memory cell in this case may be storing a data state L2 having a data value of logical '<NUM>', and so on. Table <NUM> provides one possible correspondence between the data states and their corresponding logical data values. Other assignments of data states to logical data values are known. Memory cells remaining in the lowest data state (e.g., the erased state or L0 data state), as used herein, will be deemed to be programmed to the lowest data state. The information of Table <NUM> might be contained within the trim register <NUM>, for example.

As memory cells are reduced in size, their associated data storage structures generally become smaller. In addition, as more levels of data states are stored to memory cells, differentiation between data states may become more difficult.

<FIG> are conceptual depictions of threshold voltage distributions. Threshold voltages of memory cells may shift due to read disturb and/or other phenomena, such as quick charge loss (QCL) and cumulative charge loss. In read disturb, the threshold voltage of a memory cell may shift in response to the voltage applied to the memory cell to facilitate access to the target memory cell selected for sensing, e.g., increasing the threshold voltage of the memory cell. QCL is a de-trapping of electrons near a gate dielectric interface out to the channel region of the memory cell, and can cause an immediate Vt shift after a programming pulse. When a memory cell passes the verify operation, the programmed threshold voltage may appear to be higher due to the trapped charge in the gate dielectric. When the memory cell is subsequently sensed, the memory cell may have a Vt that is lower than the Vt obtained during the program verify operation due to the charge in the gate dielectric leaking out to the channel region. Cumulative charge loss might occur over the age of the programmed data, e.g., a period of time between programming the data and sensing the data. Such charge loss can become more pronounced as the data storage structures become smaller. These phenomena can make accurate determination of data states more difficult as the threshold voltage of a memory cell may shift enough to place it in the threshold voltage distribution of a data state that is different than its original target data state.

<FIG> is a conceptual depiction of threshold voltage distributions following programming, e.g., without a net charge loss or net charge gain. The threshold voltage distributions 330x and <NUM>X+<NUM> might represent any two adjacent threshold voltage distributions representing the data states to which the memory cells might be assigned, i.e., X could have any integer value <NUM>-<NUM> for the example of <FIG>. Threshold voltage distributions generally experience spread following programming, which can lead to overlap of the threshold voltage distributions of memory cells programmed to the corresponding data states as depicted for the threshold voltage distributions 330x and <NUM>X+<NUM>. Arrow <NUM> might represent a sense voltage used to distinguish between these two data states, e.g., a memory cell being deemed to first activate in response to the voltage level corresponding to the arrow <NUM> might be deemed to be within the threshold voltage distribution 330x. Ideally, a sense voltage at a local minima between two threshold voltage distributions, such as depicted in <FIG>, might be expected to most accurately assign memory cells of the two adjacent threshold voltage distributions to the correct data states.

<FIG> is a conceptual depiction of the threshold voltage distributions 330x and <NUM>X+<NUM> shifting due to charge loss, e.g., that might occur due to QCL and/or cumulative charge loss. In response to charge loss, the threshold voltage distributions 330x and <NUM>X+<NUM> might generally shift lower relative to the sense voltage. With the sense voltage higher than the local minima, additional memory cells of the threshold voltage distribution 330x might be accurately assigned, but more memory cells of the threshold voltage distribution <NUM>X+<NUM> might be incorrectly assigned. <FIG> is a conceptual depiction of the threshold voltage distributions 330x and <NUM>X+<NUM> shifting due to charge gain, e.g., that might result from read disturb. In response to charge gain, the threshold voltage distributions <NUM>X and <NUM>X+<NUM> might generally shift higher relative to the sense voltage. With the sense voltage lower than the local minima, additional memory cells of the threshold voltage distribution <NUM>X+<NUM> might be accurately assigned, but more memory cells of the threshold voltage distribution <NUM>X might be incorrectly assigned. Such competing phenomena, some raising threshold voltages and some lowering threshold voltages, may complicate the reliable sensing of data states over the life of the memory device. Various embodiments seek to determine data states of memory cells despite these variations in threshold voltage distributions.

Sense circuits are typically utilized in memory devices to facilitate performing a sense (e.g., read and/or verify) operation on each of one or more selected (e.g., target) memory cells in the memory device. A sense operation might be a read operation, e.g., for providing data output from the array of memory cells, or a verify operation, e.g., for verifying whether a programming pulse successfully changed a threshold voltage of a target memory cell to indicate its desired data state. <FIG> illustrates a sense circuit <NUM> of a type that might be used with various embodiments. Sense circuit <NUM> is shown connected to a particular NAND string <NUM> by a particular data line <NUM>, such as shown in more detail in <FIG>, for example. Note that select transistors <NUM> and <NUM> selectively connecting the NAND string <NUM> to the source <NUM> and data line <NUM>, respectively, are not shown in <FIG>. While the discussion is directed to use of the sense circuit <NUM> with a NAND string <NUM>, other memory structures and architectures are suitable for use with sense circuit <NUM> where a current path can be selectively created between the data line <NUM> and the source <NUM> dependent upon a data state of a memory cell selected for sensing.

As part of a sense operation, e.g., a precharge portion of the sense operation, the sense circuit <NUM> may precharge the sense node <NUM>, tc node <NUM> and the data line <NUM> by activating a precharge transistor (e.g., p-type field effect transistor, or pFET) <NUM> by biasing (e.g., driving) the signal line <NUM> to a particular voltage level (e.g., a voltage level of control signal pbiasp) sufficient to activate the transistor <NUM>, by activating a first clamp transistor (e.g., n-type field effect transistor, or nFET) <NUM> by biasing the signal line <NUM> to a particular voltage level (e.g., a voltage level of control signal blclamp) sufficient to activate the transistor <NUM>, by activating a second clamp transistor (e.g., nFET) <NUM> by biasing the signal line <NUM> to a particular voltage level (e.g., a voltage level of control signal blclamp2) sufficient to activate the transistor <NUM>, and by activating an isolation transistor (e.g., nFET) <NUM> by biasing the signal line <NUM> to a particular voltage level (e.g., a voltage level of control signal tc_iso) sufficient to activate the transistor <NUM>. Control signals of the sense circuit <NUM> may be provided by the internal controller (e.g., control logic <NUM>) of the memory device <NUM>. Such control signals (e.g., both voltage levels and timing) may be defined by the sense operation and are distinguished from signals generated in response to performing the sense operation (e.g., the voltage level generated at the output <NUM> of the sense circuit <NUM> (e.g., the output signal sa_out), a voltage level generated on the sense node <NUM>, or a voltage level generated on the tc node <NUM>). The output <NUM> might have an initial logic high level during the precharge portion of the sense operation, and might be connected to the input of an inverter <NUM>, such that a transistor <NUM> (e.g., pFET), having its control gate connected to the output of the inverter <NUM>, might be activated. This might connect the sense node <NUM>, the tc node <NUM>. and the data line <NUM> to the voltage node <NUM> configured to receive a voltage level Vreg2.

The tc node <NUM> might be connected to one electrode of a capacitance (e.g., capacitor) <NUM>, to the control gate of a transistor (e.g., nFET) <NUM>, and to a source/drain of a transistor (e.g., nFET) <NUM> having its control gate connected to signal line <NUM> configured to receive the control signal blc1. The transistor <NUM> might remain deactivated during the sense operation. The capacitance <NUM> might have its second electrode connected to the output of a variable voltage node (e.g., voltage regulator) <NUM>. The variable voltage node <NUM> might further be connected to one or more additional capacitances <NUM> of other sense circuits <NUM>. Although the capacitance <NUM> is depicted in <FIG> as a capacitor, it should be recognized that, in other examples, capacitance <NUM> can refer to a portion (which may include one or more active/passive elements) of a circuit (e.g., sense circuit) having a capacitance (e.g., a predefined capacitance) and configured to influence (e.g., capacitively influence) a voltage level of the tc node <NUM> in response to an applied voltage from the voltage node <NUM>.

A sense enable transistor (e.g., nFET) <NUM> might be connected between a source/drain of the transistor <NUM> and the output <NUM> of the sense circuit <NUM>, and might have its control gate connected to the signal line <NUM> configured to receive the control signal senb. The transistor <NUM> might have its other source/drain connected to a voltage node (e.g., reference potential node) <NUM>. The voltage node <NUM> might be configured to receive a reference potential, such as a ground, 0V or the supply voltage Vss.

Following the precharging of the tc node <NUM> and the data line <NUM>, additional portions of the sense operation might be performed to detect whether or not the precharged data line <NUM> and tc node <NUM> is discharged during the sense operation, thereby determining the data state of the memory cell selected for sensing. In general, following the precharging of the tc node <NUM> and the data line <NUM>, the data line <NUM> can then be selectively connected to the source <NUM> depending upon whether the memory cell selected for sensing is activated or deactivated in response to a sense voltage applied to its control gate. The data line <NUM> and tc node <NUM> might then be given an opportunity to discharge, if current is flowing through the NAND string <NUM>. If a voltage level of the data line <NUM> is lower than the precharge voltage level due to current flow through the NAND string <NUM>, the voltage level of the tc node <NUM> will likewise experience a drop. If the voltage level of the data line <NUM> remains at the precharge voltage level, such as when the memory cell selected for sensing remains deactivated, the voltage level of the tc node <NUM> may remain at its precharge (or boosted) voltage level. The tc note <NUM> might then be isolated from the data line <NUM>, e.g., by deactivating the transistor <NUM> and/or the transistor <NUM>.

While the transistor <NUM> activated, and the voltage level of the tc node <NUM> applied to the control gate of the transistor <NUM>, the voltage node <NUM> may be selectively connected to the output <NUM> depending upon a voltage level of the tc node <NUM>. The output <NUM> may have a particular logic level (e.g., logic high) prior to sensing. If the voltage level of the voltage node <NUM> is applied to the output <NUM> upon activation of the transistor <NUM>, its logic level may change, e.g., from a logic high level to a logic low level, and if the voltage node <NUM> remains isolated from the output <NUM> upon activation of the transistor <NUM>, its logic level may remain at the particular logic level.

Various embodiments may utilize boosting and deboosting of the tc node <NUM> during the sense operation. Boosting (e.g., capacitively coupling a first boost voltage level to) and deboosting (e.g., capacitively coupling a second, lower, deboost voltage level to) the tc node <NUM> might be used, for example, to facilitate a higher develop overhead. By boosting the tc node <NUM> prior to the sense node develop time, the voltage level of the tc node <NUM> can be allowed to develop longer without prematurely indicating current flow of the data line <NUM>. Subsequent deboosting of the tc node <NUM> after isolation from the NAND string <NUM> from the data line <NUM> may permit the voltage level of the tc node <NUM> to drop below the trip point (e.g., threshold voltage) of the transistor <NUM> to indicate that current flow (e.g., a threshold level of current flow) was detected.

The trip point of the sense circuit <NUM> may generally be dependent upon the threshold voltage of the transistor <NUM>. The sense circuit <NUM> is typically configured to have a trip point (e.g., sense threshold level) close to the precharge voltage level that may be established on the tc node <NUM> prior to sensing the selected memory cell. The trip point might be a particular voltage level on the tc node <NUM> wherein the sense circuit <NUM> outputs a first logic level indicative of a first state of the tc node <NUM>, e.g., when the voltage level of the tc node <NUM> is equal to or above the trip point. The sense circuit <NUM> might output a second logic level indicative of a second state of the tc node <NUM>, e.g., when the voltage level of the tc node <NUM> is below the trip point, for example. The state of the tc node <NUM> can be used to provide an indication of the data state of the sensed memory cell.

It is noted that data lines corresponding to activated memory cells having threshold voltages nearer the sense voltage applied to their control gates might be expected to experience lower levels of discharge and higher resulting voltage levels of the tc node <NUM> than data lines corresponding to activated memory cells having threshold voltages farther from the sense voltage applied to their control gates. This phenomena might be expected to alter current demand from the capacitance <NUM> in response to varying voltage levels of the tc node <NUM>.

Various embodiments utilize an indication of current demand of a capacitance <NUM> during a sensing operation to estimate the conditions that might indicate activation of those memory cells having threshold voltages below the local minima of two adjacent threshold voltage distributions, and might indicate deactivation of those memory cells having threshold voltages above that local minima. By gaining information about a magnitude and direction of the shift of the threshold voltage distributions, decisions about deboosting conditions might be informed.

<FIG> is a conceptual depiction of current flow through a memory cell as a function of threshold voltage in response to an applied control gate voltage in accordance with an embodiment. The current level of the memory cell might be represented by the line <NUM>. Vt_target might represent a target threshold voltage, and might correspond to the voltage level applied to a selected access line for a sensing operation of one or more memory cells connected to that access line. It might be desired to deem a memory cell having a current flow of less than Atarget as being deactivated in response to applying the sense voltage to its control gate. It is noted, however, that there might be an expectation that memory cells having threshold voltages above Vt_target might experience some current flow, albeit less than the target current flow Atarget. Similarly, there might be an expectation that memory cells having threshold voltages below Vt_target might experience current flows higher that the target current level Atarget.

With reference to the sense circuit <NUM>, current flows higher than the current level A0 might initially be supplied from the capacitance <NUM>, but might be subsequently supplied by the voltage node <NUM>. The current level A0 might be dependent upon a voltage level applied to the capacitance <NUM> by the variable voltage node <NUM>. Current flows lower than the current level A0, occurring at the threshold voltage level Vt0, might be supplied from the capacitance <NUM> in response to the voltage level applied by the variable voltage node <NUM>. The line <NUM> might represent a steady-state current demand on the variable voltage node <NUM> as a function of the threshold voltage level of the memory cell. As depicted, the steady-state current demand on the variable voltage node <NUM> might equal the current level A0 at the threshold voltage level Vt0, and might follow the current level of the memory cell for threshold voltage levels above the threshold voltage level Vt0.

<FIG> are conceptual depictions of adjacent threshold voltage distributions such as depicted in <FIG> in accordance with embodiments. The threshold voltage distributions 330x and <NUM>X+<NUM> might represent any two adjacent threshold voltage distributions representing the data states to which the memory cells might be assigned, i.e., X could have any integer value <NUM>-<NUM> for the example of <FIG>. The arrow <NUM> might represent the target threshold voltage level Vt_target and the arrow <NUM> might represent the threshold voltage level Vt0.

In <FIG>, the shaded area 739a might represent a magnitude of current flow supplied by the variable voltage nodes <NUM> of the memory cells of the threshold voltage distributions <NUM>X and <NUM>X+<NUM> having threshold voltages between Vt0 and Vt_target if there is no net charge gain or charge loss experienced by those memory cells. In <FIG>, the shaded area 739b might represent a magnitude of current flow supplied by the variable voltage nodes <NUM> of the memory cells of the threshold voltage distributions <NUM>X and <NUM>X+<NUM> having threshold voltages between Vt0 and Vt_target if there is charge loss experienced by those memory cells. And in <FIG>, the shaded area 739c might represent a magnitude of current flow supplied by the variable voltage nodes <NUM> of the memory cells of the threshold voltage distributions <NUM>X and <NUM>X+<NUM> having threshold voltages between Vt0 and Vt_target if there is charge gain experienced by those memory cells. As depicted in Figured 7A-7C, memory cells experiencing charge loss might be expected to experience a lower current demand from their variable voltage nodes <NUM> relative to memory cells not experiencing a net charge loss or charge gain. Conversely, memory cells experiencing charge gain might be expected to experience a higher current demand from their variable voltage nodes <NUM> relative to memory cells not experiencing a net charge loss or charge gain.

Provided the magnitude of the charge loss or charge gain is not excessive, e.g., to the point where the foregoing relationships begin to reverse, the relative magnitudes of the current demand can be used to indicate a direction and magnitude of the threshold voltage shift. In response to determining an expected direction and magnitude of the threshold voltage shift, a deboost voltage level might be determined that might be expected to compensate for the detected threshold voltage shift. This might result in memory cells having threshold voltages higher than the local minima between the two adjacent threshold voltage distributions being deemed to be deactivated, and memory cells having threshold voltages lower than the local minima being deemed to be activated. Alternatively, or in addition, the relationship between a desired deboost voltage level and the current demand might be expressed as a function or stored in a look-up table in, or otherwise accessible to, the memory. In general, lower deboost voltage levels might be applied in response to charge gain, while higher deboost voltage levels might be applied in response to charge loss.

Table <NUM> might be an example of a look-up table for deboost voltage level as a function of measured current demand. In Table <NUM>, Vdefault might represent a default deboost voltage level, e.g., that might be used if little or no threshold voltage shift were detected. The relationship between the various voltage levels of the deboost voltage level might be V1 > V2 > Vdefault > V3 > V4. While five rows of a look-up table are depicted in Table <NUM>, fewer or more rows might be used.

<FIG> is a timing diagram generally depicting voltage levels of various nodes of a sense circuit such as the sense circuit <NUM> depicted in <FIG> at various stages of a sense operation in accordance with an embodiment. With reference to <FIG> and <FIG>, the trace <NUM> might represent the voltage level of the output of the variable voltage node <NUM>, the trace <NUM> might represent the voltage level of the control signal tc_iso applied to the signal line <NUM> connected to the control gate of the transistor <NUM>, and the trace <NUM> might represent the voltage level of the control signal blclamp2 applied to the signal line <NUM> connected to the control gate of the transistor <NUM>.

During a precharge and boost phase of the sense operation, the voltage level of the control signal tc_iso (trace <NUM>) might be sufficient to initially activate the transistor <NUM>, and the voltage level of the control signal blclamp2 (trace <NUM>) might be sufficient to initially activate the transistor <NUM>. The voltage level of the output of the variable voltage node <NUM> (trace <NUM>) might then be increased from an initial voltage level <NUM> to a boost voltage level <NUM>. The initial voltage level <NUM> might be a reference potential, such as ground, Vss or 0V. At or around time t1, the voltage level of the control signal blclamp2 might be reduced.

At time t1, the tc node <NUM> is allowed to develop, e.g., selectively discharging depending upon whether the NAND string <NUM> connected to the data line <NUM> is conducting current, e.g., whether the selected memory cell is conducting current. This might be referred to as the tc node development phase of the sense operation. If the current level of the selected memory cell is above A0 (<FIG>), the transistor <NUM> might be activated, and the memory cell current might be supplied by the voltage node <NUM>. If the current level of the selected memory cell is below A0, the transistor <NUM> might be deactivated, and the memory cell current might be supplied by the voltage node <NUM>. At time t2, the control signal tc_iso might be decreased to deactivate the transistor <NUM> and isolate the tc node <NUM> from the data line <NUM> during subsequent deboosting. After time t2, the voltage level of the output of the variable voltage node <NUM> might be decreased, e.g., deboosted, to a deboost voltage level <NUM>, and the data value might be sensed and latched in manners well understood in the art.

For various embodiments, the current demand of the capacitances <NUM> for a set of sense circuits, e.g., corresponding to a grouping of memory cells selected for sensing, might be measured during the period of time <NUM>. This might include measuring current demand of one or more voltage nodes <NUM> connected to the capacitances <NUM> for the set of sense circuits. A set of sense circuits might include each sense circuit configured to sense a data state of a memory cell selected for sensing during a sense operation, or each sense circuit configured to sense a data state of some subset of memory cells selected for sensing during the sense operation. For example, a logical page of memory cells selected for sensing during a sense operation might include <NUM> memory cells connected to a selected access line whose NAND strings are connected to <NUM> sense circuits, respectively. The measurement of current demand could be based on each voltage node connected to a capacitance of each of the <NUM> sense circuits. Note that a single voltage node might be connected to capacitances of more than one sense circuit.

Threshold voltage shift might be variable among the logical page of memory cells due to such factors as differing fabrication conditions along the access line, differing ambient conditional along the access line, different programming conditions along the access line, etc. As such, it may be beneficial to perform the measurement of current demand for subsets of the memory cells selected for the sense operation that might be expected to experience similar, or more similar, levels of threshold voltage shift. For example, the <NUM> memory cells of the logical page of the foregoing example might be divided into four subsets of <NUM> memory cells each. Each subset of memory cells might represent a contiguous grouping of memory cells along the selected access line. A variable voltage node should generally corresponding to only one subset of memory cells.

As noted previously, the threshold voltage level Vt0 might be dependent upon the boost voltage level <NUM>. For embodiments determining current demand corresponding to multiple subsets of memory cells of a sense operation, different boost voltage levels could be used in order to obtain additional information about the magnitude of any threshold voltage shift. For example, with reference to <FIG>, moving Vt0 might change the cell current level that can be supplied by the capacitance, and thus the variable voltage node. By comparing current demand for sensing of one subset of memory cells using a first boost voltage level to the current demand for sensing of different subset of memory cells using a second boost voltage level, different than the first boost voltage level, information indicating the number of memory cells having threshold voltages between the Vt0 for the first boost voltage level and the Vt0 for the second boost voltage level might be determined. This information might better inform the magnitude of the adjustment of the deboost voltage level.

The period of time <NUM> might represent a period of time extending from time t2, e.g., when the tc node <NUM> is isolated from the data line <NUM>, to some time before time t2. The period of time <NUM> might represent the last <NUM>% of the tc node development phase of the sense operation. Alternatively, the period of time <NUM> might represent some period of time less than the last <NUM>% of the tc node development phase of the sense operation.

The deboost voltage level <NUM> might be selected in response to the measurement of current demand. If the current demand is determined to be within a predefined range, which might include being equal to some target current level, the deboost voltage level <NUM> might be selected to be some default value selected in response to desired operation of the sense circuit under the presumption that the memory cells have not experienced a net charge gain or charge loss. For current demand determined to be outside the predefined range, the deboost voltage level <NUM> might be selected to be higher or lower than the default value to compensate for detected threshold voltage shift. Selecting the deboost voltage level <NUM> in response to a level of current demand might include selecting a voltage difference <NUM> in response to the level of current demand and adding the voltage difference <NUM> (e.g., absolute value of the voltage difference <NUM>) to the initial voltage level <NUM>. In general, lower deboost voltage levels (e.g., closer to the initial voltage level <NUM> than the default value) might be applied in response to charge gain, while higher deboost voltage levels (e.g., farther from the initial voltage level <NUM> than the default value) might be applied in response to charge loss.

<FIG> depicts a flowchart of a method of operating a memory according to an embodiment, e.g., during a sense operation in accordance with an embodiment. The method might be in the form of computer-readable instructions, e.g., stored to the instruction registers <NUM>. Such computer-readable instructions might be executed by a controller, e.g., the control logic <NUM>, to cause the memory (e.g., relevant components of the memory) to perform the method.

At <NUM>, a boost voltage level might be applied to each capacitance of a plurality of capacitances, each connected to a respective node of a plurality of nodes. For example, the boost voltage level might be applied to a capacitance <NUM> by a variable voltage node <NUM> during, and as part of, the sense operation for a plurality of memory cells selected for the sense operation. The plurality of memory cells might include each memory cell selected for the sense operation, or some subset of all of the memory cells selected for the sense operation. Each capacitance <NUM> might be connected to a corresponding tc node <NUM>. At <NUM>, each node of the plurality of nodes might be selectively discharged through its respective memory cell of the plurality of memory cells selected for the sense operation and connected to its respective node of the plurality of nodes. For example, each tc node <NUM> might be selectively discharged through a respective memory cell of a respective NAND string <NUM> to the source <NUM> depending upon whether that memory cell is activated in response to a sense voltage applied to its control gate, e.g., depending upon its data state. As is common, all remaining memory cells of each NAND string <NUM> might receive a pass voltage sufficient to activate those memory cells regardless of their data states.

At <NUM>, the current demand of the plurality of capacitances might be measured while each node is connected to its respective memory cell. Measuring the current demand of the capacitances might include measuring a current demand of voltage node (e.g., variable voltage node) connected to one electrode of each of the capacitances, or it might include measuring a current demand of a plurality of voltage nodes (e.g., variable voltage nodes), each connected to one or more capacitances of the plurality of capacitances, and summing those measured current demands. At <NUM>, each node of the plurality of nodes might be isolated from its respective memory cell. For example, each tc node <NUM> might be isolated from its respective NAND string <NUM> by deactivating a respective transistor <NUM>.

At <NUM>, a deboost voltage level might be determined in response to the measured current demand. As discussed with reference to <FIG> and <FIG>, the current demand of the capacitances <NUM> might generally be dependent upon threshold voltage levels of the memory cells connected to them relative to the voltage level of the sense voltage applied to their control gates. At <NUM>, the deboost voltage level might be applied to each capacitance of the plurality of capacitances. At <NUM>, a data state might be determined for each memory cell of the plurality of memory cells while the deboost voltage level is applied to each capacitance of the plurality of capacitances. For example, if the voltage level of a tc node <NUM> is below a trip point (e.g., below the threshold voltage) of the transistor <NUM>, the transistor <NUM> might be deactivated. Upon activating the transistor <NUM>, the output <NUM> of the sense circuit might remain isolated from the voltage node <NUM>, and thus remain in a logic high state indicating that the memory cell is deemed to be activated in response to the sense voltage. Conversely, if the voltage level of a tc node <NUM> is above the trip point (e.g., above the threshold voltage) of the transistor <NUM>, the transistor <NUM> might be activated. Upon activating the transistor <NUM>, the output <NUM> of the sense circuit might be connected to the voltage node <NUM>, and thus transition to a logic low state indicating that the memory cell is deemed to be deactivated in response to the sense voltage. It is noted that various embodiments might facilitate more accurate determinations of intended data states over methods using a default deboost voltage level, and may facilitate such increased accuracy without a penalty in read time.

Claim 1:
A memory (<NUM>), comprising:
an array of memory cells (<NUM>);
a plurality of sense circuits (<NUM>), each sense circuit (<NUM>) of the plurality of sense circuits (<NUM>) comprising a respective capacitor (<NUM>) of a plurality of capacitors (<NUM>), wherein each capacitor (<NUM>) of the plurality of capacitors (<NUM>) is connected to a respective node (<NUM>) of a plurality of nodes (<NUM>), and wherein each node (<NUM>) of the plurality of nodes (<NUM>) is selectively connected to memory cells (<NUM>) of the array of memory cells (<NUM>); and
a controller (<NUM>) for access of the array of memory cells (<NUM>), wherein the controller (<NUM>) is configured to cause the memory (<NUM>) to:
apply a boost voltage level to each capacitor (<NUM>) of the plurality of capacitors (<NUM>);
selectively discharge each node (<NUM>) of the plurality of nodes (<NUM>) through a respective memory cell (<NUM>) of a plurality of memory cells (<NUM>) of the array of memory cells (<NUM>) selected for a sense operation, with each memory cell (<NUM>) of the plurality of memory cells (<NUM>) connected to its respective node (<NUM>) of the plurality of nodes (<NUM>);
measure a current demand of the plurality of capacitors (<NUM>) while each node (<NUM>) of the plurality of nodes (<NUM>) is connected to its respective memory cell (<NUM>) of the plurality of memory cells (<NUM>);
isolate each node (<NUM>) of the plurality of nodes (<NUM>) from its respective memory cell (<NUM>) of the plurality of memory cells (<NUM>);
determine a deboost voltage level in response to the measured current demand;
apply the deboost voltage level to each capacitor (<NUM>) of the plurality of capacitors (<NUM>); and
determine a respective data state of each memory cell (<NUM>) of the plurality of memory cells (<NUM>) while the deboost voltage level is applied to each capacitor (<NUM>) of the plurality of capacitors (<NUM>).