Patent Description:
High-density memory arrays, e.g. Magnetic Random Access Memory (MRAM) arrays can suffer from the so-called sneak path problem. This problem arises from cross-talk interference between adjacent memory cells caused by a sneak path current, e.g. between a read-out cell and a neighboring cell. This can result in misinterpretation of the read-out signal of the read-out cell.

Selector devices can be used to protect the read-out signals. The selector devices provide a threshold (diode behavior) for device selection based on word-line and bit-line (source line) voltage. That is, the sneak path problem can be mitigated by inserting selector devices next to the memory cells of the memory array.

In particular, in one approach of a magnetic memory device shown in <FIG>, a selector device <NUM> is inserted on top of each Magnetic Tunnel Junction (MTJ) element <NUM> in the Back End of Line (BEOL). However, the limitation of this approach is that the inserted selector devices <NUM> obstruct the BEOL, and therefore reduce the interconnect density that can be achieved towards a computing platform (e.g., for a logic-memory interconnect). In other words, it is difficult to achieve a high interconnect density with, e.g., a logic chip, because the BEOL area is fully occupied by the memory elements <NUM> and selector device <NUM>.

In addition, the BEOL-fabricated selector devices <NUM> are not very efficient, in particular, they suffer from high leakage and low mobility, due to defects in amorphous and poly-crystalline materials used in the BEOL.

<CIT> discloses a resistive memory cell control unit, integrated circuit, and method, wherein the resistive memory cell control unit includes a switching transistor and a resistive memory cell.

<CIT> discloses a method for manufacturing a semiconductor device, including: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween.

In view of the above, embodiments of the present invention aim to provide an improved solution to the sneak path problem. An objective is to provide a memory device, and a method for fabricating the memory device, wherein the memory device is more efficient and has a higher interconnect density, for instance, to connect a memory array and a logic chip. In particular, the memory device should have improved selector devices, and an improved arrangement of selector devices and memory elements. Further, it should be possible to dispose the selector devices with the same pitch as the memory elements of the memory array.

The objective is achieved by the embodiments of the invention provided in the enclosed independent claims. Advantageous implementations of these embodiments are defined in the dependent claims.

In particular, the embodiments of the invention solve the above problems by, firstly, fabricating selector devices in the substrate front-side, which leads to better efficiency and enables the same pitch as for the memory elements, and, secondly, by putting the memory elements on the substrate back-side, in order to enable higher bandwidth interconnections.

A first aspect of the invention provides a method for fabricating a memory device, wherein the method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure, wherein each selector device comprises an NPN bipolar transistor with a floating base, or a PNP bipolar transistor with a floating base, or an NP diode, or a PN diode.

Using the method of the first aspect, the selector devices can be fabricated in a front-side of the first substrate, in particular they can be manufactured in the FEOL. This allows processing the selector devices in a high quality semiconductor layer. Thus, the selector devices show less leakage and a higher mobility, due to less defects in the semiconductor layer than, e.g., in amorphous or poly-crystalline semiconductor layers. The selector devices are therefore more efficient.

The interconnect layer, which includes the interconnect structure, can be manufactured in the BEOL. Accordingly, the interconnect structure may be a BEOL connection. The interconnect structure may be any structure that allows electrically connecting to the selector devices from the outside of the first substrate. The interconnect layer may be any kind of layer including such an interconnect structure.

Furthermore, the memory elements can be processed in the back-side of the first substrate, particularly they can be manufactured after the BEOL. Thus, the memory elements do not obstruct the BEOL, in particular not the interconnect structure, and therefore a higher interconnect density and bandwidth is possible. In addition, a lower thermal budget and a lower aspect ratio are possible, compared to selector devices and memory elements that are processed in the BEOL. The lower aspect ratio is possible, because the memory elements and the selector devices are not stacked together, so that it is not necessary to etch high aspect ratio pillars each comprising a memory element and a selector device. Another advantage is that the selector devices can be disposed with the same pitch as the memory elements.

Overall an improved memory device, is created, and also an improved solution to the sneak path problem is provided.

The memory device fabricated by the method of the first aspect may be a magnetic memory device including magnetic memory elements, e.g., MRAM elements like MTJs. The memory device may also be a resistive memory device including resistive memory elements, e.g., may be a Resistive Random Access Memory (RRAM). The memory device fabricated by the method is of the "1S1M" architecture, i.e., there is one selector device for each memory element. In particular, the memory device is preferably not of the "1T1M" architecture, with one transistor for each memory element. The selector devices may be bipolar selector elements. In particular, the selector devices may be bipolar transistors operated with a floating base. The one or more vias may be one or more Through-Silicon Vias (TSV) connecting the interconnect structure with rows of memory elements.

"Front side" and "back side" of the first substrate refer to opposite sides of the semiconductor layer. The "front-side" may be the side that is processed first, e.g. in the FEOL, and the "back-side" may be the side that is processed last, e.g. after the BEOL. Further, in this document, a layer being "provided on" or "arranged on" another layer may either mean that the layer is arranged "below" or "above" the other layer. Thereby, the terms "below"/"above" or "bottom"/"top" relate to layers of the material stack, in particular to the fabrication/growth direction of these layers. In any case, "provided on" or "arranged on" means that the layer is in contact with the other layer.

In an implementation, the method further comprises, after processing the interconnect layer and before processing the memory elements: bonding the first substrate to a second substrate including a logic chip, wherein the first substrate is bonded with the interconnect layer to the second substrate such that the interconnect structure is electrically connected to the logic chip.

The method of the first aspect thus allows creating a high bandwidth connection of the memory elements and the logic chip, in particular, by means of the one or more vias connecting the memory elements to the interconnect structure and the interconnect structure further connecting to the logic chip. The logic chip may comprise a high-performance computing platform, for example, based on Fin Field Effect Transistor (FinFET) technology. However, the logic chip can also be planar or based on nanowires, for example. The bonding may be hybrid bonding.

In an implementation form, the interconnect layer further comprises a periphery of the plurality of memory elements.

That means, the interconnect layer may comprise the interconnect structure and the periphery (or a part of the periphery) of the memory elements. The interconnect layer may thus comprise a mix of BEOL connection and periphery (elements). The periphery is, in particular, not a part of the interconnect structure. The periphery of the memory elements, i.e., of the memory array, may include one or more CMOS circuits, e.g., sense-amplifiers, and/or level shifters, and/or other memory circuit elements. The interconnect layer may thus be a periphery layer. Additionally or alternatively, it is possible to form periphery of the memory elements in the FEOL, e.g., together with the selector devices in the semiconductor layer. Further, it is also possible to provide the periphery of the memory array on the second substrate, e.g., to fabricate the periphery together with the logic chip on the second substrate.

In an implementation, the semiconductor layer is a crystalline semiconductor layer.

Thus, the selector devices processed in this semiconductor layer can have a particularly high efficiency, e.g., in terms of leakage and mobility.

The fabricated memory device is of the "1S1M" architecture, i.e., each selector device is a selector in the sense of "1S1M". Each selector device may be a <NUM>-terminal device. In case of a bipolar transistor, this is still a <NUM>-terminal device because it has the floating base.

In an implementation, the selector devices are processed by forming blanket implants or are processed by epitaxy, and the selector devices are isolated from each other by shallow trench isolation.

This enables a selector device pitch that is in the same order, or even the same, as a pitch of the memory elements. For instance, this pitch may be around <NUM>.

In an implementation, the blanket implants are formed with different N/P/N or P/N/P implant energies to respectively form NPN or PNP bipolar transistors with a floating base; and/or the blanket implants are formed with different N/P or P/N implant energies to respectively form NP or PN diodes.

Forming the blanket implants with different N/P/N implant energies achieves floating-base bipolar transistors.

In an implementation, the selector devices are formed over the entire thickness of the semiconductor layer.

The thickness of the semiconductor layer can, in particular, be selected such that an etching thereof will expose the deepest doping layer of the selector device(s).

In an implementation, the selector devices are processed in a front-side of the first substrate.

For instance, they are processed in the FEOL. A higher quality semiconductor layer, for instance a crystalline semiconductor layer, can be used, leading to a higher efficiency of the selector devices. Further, the selector devices do not obstruct the BEOL.

In an implementation, the memory elements are processed after a back end of line.

Thus, a lower thermal budget and lower aspect ratio is possible, since BEOL and bonding may already be processed before processing the memory elements.

In an implementation, the selector devices and the memory elements are, respectively, arranged regularly with the same pitch, in particular each with a pitch in a range of <NUM>-<NUM>.

In an implementation, the first substrate is a semiconductor-on-insulator substrate comprising a semiconductor substrate layer, the oxide layer arranged on the semiconductor substrate layer, and the semiconductor layer arranged on the oxide layer.

In an implementation, the method further comprises, before processing the memory elements in the oxide layer of the first substrate, thinning the first substrate to remove the semiconductor substrate layer and to expose the oxide layer.

A second aspect of the invention provides a memory device, comprising: a plurality of selector devices formed in a semiconductor layer of a first substrate, an interconnect layer arranged on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, a plurality of memory elements formed in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and one or more vias through the semiconductor layer electrically connecting the memory elements to the interconnect structure, wherein each selector device comprises an NPN bipolar transistor with a floating base, or a PNP bipolar transistor with a floating base, or an NP diode, or a PN diode.

In an implementation, the memory device further comprises: a second substrate including a logic chip, wherein the first substrate is bonded with the interconnect layer to the second substrate such that the interconnect structure is electrically connected to the logic chip.

The memory device of the second aspect may be a magnetic memory device, and enjoys the advantages mentioned above with respect to the fabrication method of the first aspect.

The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:.

<FIG> shows a method <NUM> for fabricating a memory device <NUM>, wherein the method <NUM> comprises several processing steps, which are schematically illustrated in <FIG>.

In particular, the method <NUM> comprises a step <NUM> of processing a plurality of selector devices <NUM> in a semiconductor layer <NUM> of a first substrate <NUM> (or wafer). The semiconductor layer <NUM> may, in particular, be a crystalline semiconductor layer, e.g. crystalline silicon layer. The selector devices <NUM> may be processed in a front-side of the first substrate <NUM>, particularly in the FEOL.

The method <NUM> further comprises a step <NUM> of processing an interconnect layer <NUM> on a front-side of the semiconductor layer <NUM>, wherein the interconnect layer <NUM> comprises an interconnect structure <NUM>, which is electrically connected to the plurality of selector devices <NUM>. The interconnect structure <NUM> may be used to connect memory elements <NUM> processed on the first substrate <NUM> electrically to another chip, e.g., to a logic chip, e.g. processed on another substrate. The interconnect structure <NUM> may be formed in the interconnect layer <NUM> together with periphery of the memory elements <NUM>.

The method <NUM> further comprises a step <NUM> of processing a plurality of memory elements <NUM> in an oxide layer <NUM> of the first substrate <NUM>, which oxide layer <NUM> is arranged on a back-side of the semiconductor layer <NUM>. Each memory element <NUM> is electrically connected to one of the selector devices <NUM>, i.e. the memory device may be of the "1S1M" architecture. The memory elements <NUM> may be processed after a BEOL. Each memory element <NUM> may be a magnetic memory element, e.g., for an MRAM device, for instance, including a MTJ stack.

Finally, the method <NUM> comprises a step <NUM> of processing one or more vias <NUM> through the semiconductor layer <NUM>, in order to electrically connect the memory elements <NUM> to the interconnect structure <NUM>. For instance, shown in <FIG> as an example, at least one via <NUM> may be connected on its one side to the interconnect structure <NUM>, may pass from the interconnect layer <NUM> through the semiconductor layer to the oxide layer <NUM>, and may be connected on its other side to, e.g., a metal line <NUM> connecting it with one or more of the memory elements <NUM>.

As will be shown further below, the steps <NUM>-<NUM> of the method <NUM> are not necessarily steps, which directly following one another. The method <NUM> may comprise further steps, either after the steps <NUM>-<NUM> or in between these steps <NUM>-<NUM>.

After step <NUM> of the method <NUM> shown in <FIG>, a memory device <NUM> may be obtained. This memory device <NUM> comprises, as shown in <FIG>: the plurality of selector devices <NUM>, which are formed in the semiconductor layer <NUM> of the first substrate <NUM>; the interconnect layer <NUM>, which is arranged on a front-side of the semiconductor layer <NUM>, wherein the interconnect layer <NUM> comprises the interconnect structure <NUM> that is electrically connected to the plurality of selector devices <NUM>; the plurality of memory elements <NUM>, which are formed in the oxide layer <NUM> of the first substrate <NUM>, which oxide <NUM> layer is arranged on the back-side of the semiconductor layer <NUM>, each memory element <NUM> being electrically connected to one of the selector devices <NUM>; and the one or more vias <NUM> through the semiconductor layer <NUM>, electrically connecting the memory elements <NUM> to the interconnect structure <NUM>. The one or more vias <NUM> are inserted to connect, for instance, a top electrode of a MTJ memory element <NUM> to the front-side of the first substrate <NUM>.

Of course, the memory device <NUM> may include further features, as will be described below, in particular, if the method <NUM> for fabricating the memory device <NUM> includes further steps.

By fabricating the memory device <NUM> with the method <NUM>, a space in the BEOL, which is required to enable a high interconnect density of the interconnect structure <NUM>, is made available by putting the selector devices <NUM> as through-substrate devices, and further by putting the memory elements <NUM> as back-side devices directly connected to the selector devices <NUM>. An extra advantage of the method <NUM> and the memory device <NUM>, respectively, is that the rest of the space in the first substrate <NUM> can be used to insert a periphery of the memory elements <NUM>, e.g., including a sense-amplifier, and/or level shifters, and/or other memory circuit elements, which are more difficult to realize in FinFET devices, due to their process constraints and low operating voltages. That is, the interconnect layer <NUM> may further comprise a periphery of the memory array, particularly for reading out or writing into the memory elements <NUM>. The interconnect layer <NUM> then includes the interconnect structure <NUM> and periphery of the memory elements. Periphery may also or alternatively be provided in the semiconductor layer <NUM> beneath the interconnect layer <NUM>.

For fabricating a specific memory device <NUM> according to an embodiment of the invention, a thinned cheap CMOS wafer may be used as the first substrate <NUM>. This first substrate <NUM> may be bonded, in particular may be hybrid-bonded, to a second substrate <NUM> including a high performance computing platform (e.g. a FinFET). This will be illustrated in the following with respect to <FIG>.

In particular, <FIG> illustrate a method <NUM> according to an embodiment of the invention, which builds on the embodiment illustrated in <FIG>. The method <NUM> of <FIG> includes further, optional, method steps. The method <NUM> specifically includes steps <NUM>-<NUM>, which include the general steps <NUM>-<NUM> shown in <FIG>.

<FIG> shows step <NUM> and step <NUM> of the method <NUM> according to an embodiment of the invention.

Step <NUM> relates to the steps <NUM> and <NUM> of the general method <NUM> shown in <FIG>. In step <NUM>, a semiconductor-on-insulator (SOI) substrate or wafer is used as the first substrate <NUM>, and comprises a semiconductor substrate layer <NUM> (e.g., a silicon layer), the oxide layer <NUM> (e.g. a silicon oxide layer), which is arranged on the semiconductor substrate layer <NUM>, and the semiconductor layer <NUM> (e.g. a crystalline silicon layer), which is arranged on the oxide layer <NUM>. A planar relaxed and cheap CMOS technology can be used to process the interconnect structure <NUM> in the interconnect layer <NUM>, e.g. as a memory read-out circuitry. The interconnect layer <NUM> may comprise a silicon oxide layer embedding the interconnect structure <NUM>.

According to the invention, the selector devices <NUM> may be processed as N/P/N, or P/N/P structures, or alternatively as N/P or P/N structures. In particular, each selector device <NUM> may comprise an NPN bipolar transistor with a floating base, or may comprise a PNP bipolar transistor with a floating base, or may comprise an NP diode, or may comprise a PN diode. The selector devices <NUM> may thereby be formed over the entire thickness of the semiconductor layer <NUM>. This allows exposing the deepest doping layer, e.g. by etching.

Step <NUM> is performed after the step <NUM>, and before step <NUM>, of the general method <NUM> of <FIG>. Step <NUM> comprises a step of bonding <NUM> the first substrate <NUM> (or first wafer) to a second substrate <NUM> (or second wafer), the second substrate <NUM> including a logic chip <NUM>, e.g. FinFET CMOS technology for logic computing. In particular, the first substrate <NUM> may be bonded <NUM> with the interconnect layer <NUM> to the second substrate <NUM>, such that the interconnect structure <NUM> is electrically connected to the logic chip <NUM>. In this way, it may provide a high interconnect bandwidth between the logic chip <NUM> and the memory elements <NUM>. The bonding may be hybrid bonding and/or wafer-to-wafer bonding.

In step <NUM>, the semiconductor substrate layer is removed, e.g. by thinning. The thickness of the oxide layer <NUM> can be directly used as back-side BEOL oxide.

Step <NUM> relates to step <NUM> of the general method <NUM> of <FIG>. In particular, the plurality of memory elements <NUM> may be processed in the BEOL oxide (oxide layer <NUM>). For example, as illustrated, MTJ memory elements may be processed as the memory elements <NUM>.

Step <NUM> shows how the complete MTJ memory elements <NUM> can be processed, each memory element <NUM> including a MTJ bottom electrode 16a connected to a selector device <NUM>, further including the MTJ 16b, and further including a MTJ top electrode 16c.

Step <NUM> relates to step <NUM> of the general method <NUM> of <FIG>. The one or more vias <NUM> are processed through the semiconductor layer <NUM>, in order to electrically connect the memory elements <NUM> to the interconnect structure <NUM>. A via <NUM> may thereby connect, on the one side, to the MTJ top electrode 16c, e.g. over a metal line <NUM>, and, on the other side, to a metal contact of the interconnect structure <NUM>. A pitch of multiple vias <NUM> processed is not a problem, because there can be one via <NUM> per row of memory elements <NUM>, not one via <NUM> per memory element <NUM>. After step <NUM>, the full structure of the memory device <NUM> is obtained, i.e., <FIG>, step <NUM>, shows a memory device <NUM> according to an embodiment of the invention.

<FIG> shows a high-density implementation of selector devices <NUM> for a memory device <NUM> according to an embodiment of the invention.

In order to fabricate the high-density selector devices <NUM>, i.e. multiple selector devices <NUM> arranged with a very small pitch, blanket implants <NUM> may be combined with Shallow Trench Isolation (STI) <NUM>. In particular, each selector device <NUM> (each "real" selector device) may be obtained by one of multiple blanket implants <NUM> (or one of multiple regions of a blanket implant <NUM>) isolated by STIs <NUM>. That is, a STI <NUM> is arranged between each two neighboring blanket implants <NUM> or regions. This implementation with blanket implants <NUM> enables the pitch of the selector devices <NUM> to reach same pitch as of the memory elements <NUM> (e.g. MRAM target, e.g. <NUM>). In particular, the selector device pitch is determined by the STI pitch. Another option is to fabricate the selector devices <NUM> by epitaxy, and to separate them likewise with STI <NUM>, in order to achieve a high pitch.

The blanket implants <NUM> may be formed with different N/P/N or P/N/P implant energies, in order to respectively form an NPN or PNP bipolar transistor with a floating base for each selector device <NUM>. The blanket implants <NUM> may also be formed with different N/P or P/N implant energies, in order to respectively form an NP or PN diode for each selector device <NUM>.

<FIG> still shows a high-density implementation of selector devices <NUM> for a memory device <NUM> according to an embodiment of the invention (right side of <FIG>). Also, <FIG> shows a low-density implementation (left side of <FIG>) with a high planar NPN selector pitch. Such a planar NPN selector device <NUM> requires a collector and emitter contact from the front-side, which limits the pitch.

By using extreme thinning technology (with a SOI substrate <NUM>), processing of vias <NUM> (e.g., TSVs through the semiconductor layer <NUM>), bonding of the first substrate <NUM> and the second substrate <NUM>, and back-side processing of the memory elements <NUM>, an embedded high-density memory array can be obtained with NPN selector devices <NUM>. Other implementations (e.g. a memory array periphery bonded wafer) would not enable this high pitch density for the selector devices <NUM>. Further, the memory elements <NUM> advantageously see a lower thermal budget (since BEOL and bonding may already be processed).

<FIG> shows simulations of a selector device <NUM> for a memory device <NUM> according to an embodiment of the invention. Conventional diode selectors are unidirectional, but a bidirectional selector device <NUM> is needed, for instance, for read and write operations in an MRAM device. As an example, an NPN type selector device <NUM> is used (however, this could also be replaced by PNP). The NPN can be made a strong bidirectional selector device <NUM> thanks to Impact Ionization (II) and Band-To-Band Tunneling (BTBT), and by providing abrupt doping profiles and high doping densities. This triggers the open-base bipolar behavior of the selector device <NUM>. The NPN stack for the selector device <NUM> can be built either using poly or SOI wafers (crystalline). Crystalline material is assumed in the TCAD simulations shown in <FIG>.

II and BTBT enable abrupt switching of the selector device <NUM>, due to open base bipolar amplification. Notably, transient simulations are required to simulate this selector device <NUM> (cannot be done with quasi-stationary). The simulation results can be observed in the graph shown in <FIG>. It is shown that good bidirectional selection behavior is achieved.

Claim 1:
Method (<NUM>) for fabricating a memory device (<NUM>), wherein the method (<NUM>) comprises:
processing (<NUM>) a plurality of selector devices (<NUM>) in a semiconductor layer (<NUM>) of a first substrate (<NUM>),
processing (<NUM>) an interconnect layer (<NUM>) on a front-side of the semiconductor layer (<NUM>), the interconnect layer (<NUM>) comprising an interconnect structure (<NUM>) electrically connected to the plurality of selector devices (<NUM>),
processing (<NUM>) a plurality of memory elements (<NUM>) in an oxide layer (<NUM>) of the first substrate (<NUM>) arranged on a back-side of the semiconductor layer (<NUM>), each memory element (<NUM>) being electrically connected to one of the selector devices (<NUM>), and
processing (<NUM>) one or more vias (<NUM>) through the semiconductor layer (<NUM>) to electrically connect the memory elements (<NUM>) to the interconnect structure (<NUM>),
characterised in that
each selector device (<NUM>) comprises an NPN bipolar transistor with a floating base, or a PNP bipolar transistor with a floating base, or an NP diode, or a PN diode.