Patent Description:
A magnetic random access memory (MRAM) stores digital information utilizing the resistance variation related to polarity change of a magnetic substance. In some instances, sensitivity to external magnetic field can negatively impact MRAM performance, which can lead to unrecoverable failure.

Costly and complex shielding solutions have been proposed to allow for MRAM products to operate in presence of an external field. Other solutions have been proposed to shut down the chip operation if the presence of an external magnetic field that would alter the data or memory operation is detected. For example, designs have been proposed that include magnetic field sensors. Additionally, watch cells may be incorporated with the MRAMs, in which the watch cells are Magnetic Tunnel Junction elements with a lower switching field than the MRAM bits. In these designs, the system periodically reads the state of the watch cells to determine the presence of an external fields, and adjusts the performance of the MRAMs accordingly. Such solutions might not be acceptable for high performance applications.

European Patent Application Number <CIT>) discloses an array of magnetoresistive memory elements. The array comprises: means for applying a current or voltage for generating a programming magnetic field at a selected magnetoresistive memory element, a magnetic field sensor unit for measuring an external magnetic field in the vicinity of the selected magnetoresistive memory element, and means for tuning the current or voltage for compensating locally for the measured external magnetic field during a programming operation.

United States Patent Application Number <CIT>) discloses a semiconductor memory device including a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.

United States Patent Application Number <CIT>) discloses A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array including a plurality of sensing cells and a controller. Each of the sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to access the first MRAM cells to detect the external magnetic field strength of the MRAM. The controller determines whether to stop the write operation of a plurality of memory cells of the MRAM according to the external magnetic field strength of the MRAM, and each of the memory cells includes a second MTJ device. The first MTJ device is smaller than the second MTJ device.

The present invention is defined by a method for compensating for external magnetic fields according to independent claim <NUM> and by a memory device according to independent claim <NUM>.

Advantageous features are set out in the dependent claims.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

The following description will provide details of preferred embodiments with reference to the following figures wherein:.

It has been determined that magnetic random access memory (MRAM) memory can be sensitive to external magnetic fields that can negatively impact MRAM performance, and in some instances can lead to unrecoverable failure.

<FIG> is a plot illustrating the dependence of bit error rate (BER) of an MRAM device in the presence of an external magnetic field. The y-axis represents the bit error rate (BER), while the x-axis illustrates the strength of an external magnetic field. The plot line identified by reference number <NUM> illustrates that as the strength of the external magnetic field is increased, the bit error rate (BER) also increases. The data provided in <FIG> is produced from a high speed version of MRAM architecture that includes a cell with an access transistor and a MTJ (1T1MTJ) in the array. A MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In a MRAM device, the MTJ element is formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line. A MTJ stack of layers that is subsequently patterned to form a MTJ element may be formed in a so-called "bottom pinned" configuration by sequentially depositing a seed layer, a ferromagnetic reference (or "pinned") layer, a thin tunnel barrier layer, a ferromagnetic "free" layer, and a capping layer.

One type of MRAM is spin - transfer torque ( STT ) MRAM. STT MRAM has the advantages of lower power consumption and better scalability over conventional MRAM which uses magnetic fields to flip the active elements. In STT MRAM , spin - transfer torque is used to flip ( switch ) the orientation of the magnetic free layer. STT MRAM uses a two - terminal device with a magnetic tunnel junction ( MTJ ) pillar composed of a magnetic reference layer , a tunnel barrier layer , and a magnetic free layer. The magnetization of the magnetic reference layer is fixed in one direction and a current passed up through the MTJ pillar makes the magnetic free layer anti-parallel to the magnetic reference layer, while a current passed down through the MTJ pillar makes the magnetic free layer anti-parallel to the magnetic reference layer. Up and down are relative to the direction of the pinned layer. A smaller current ( of either polarity ) is used to read the resistance of the device, which depends on the relative orientations of the magnetic reference layer and the magnetic free layer.

The application of the external magnetic field can affect the magnetic tunnel junction energy barrier and modulates the switching voltage. As illustrated in <FIG>, raising the magnetic tunnel junction (MTJ) switching voltage will result in an increased bit error rate (BER) at the array level. In some embodiments, when the number of bit errors, i.e., the bit error rate (BER), increases beyond the Error Correction Code (ECC) capability, the MRAM element of the cell will begin to generate potentially uncorrectable errors, which can lead to system failure.

The structures and methods of the present disclosure overcome the aforementioned sensitivity of MRAM memory arrays to external magnetic fields by coupling a magnetic field detection circuit to the write driver of the memory array including the MRAM elements. Using the field detection circuit <NUM>, the write voltage to the driver circuit, i.e., write driver <NUM>, is adjusted based upon measurements of external magnetic field recorded by the field detection circuit <NUM>, as depicted in <FIG> is a schematic illustrating one embodiment of a magnetic field detection circuit <NUM> coupled to a write driver <NUM>. The write driver <NUM> effectuates writing data to a memory cell <NUM>, e.g., magnetic tunnel junction (memory element <NUM>) and access transistor <NUM>. The write driver <NUM> controls how the write current is provided through the MTJ and how the magnetic state of the MTJ is written, which stores data. The write driver <NUM> may include its own hardware processor and memory for commands that are configured for controlling the read and write functions of the memory device, as well as the application of write current to provide for magnetic field compensation.

<FIG> and <FIG> illustrate examples of how field compensation is achieved by adjusting the write voltage based upon the measurement of an external magnetic field. <FIG> is a plot illustrating how the field compensation can mitigate the bit error rate (BER) of an MRAM device in the presence of an external magnetic field. The y-axis of the plot depicted in <FIG> represents the bit error rate (BER), while the x-axis illustrates the strength of an external magnetic field. The plot line identified by reference number <NUM> in <FIG> illustrates that as the strength of the external magnetic field is increased, the bit error rate (BER) also increases. The plot point identified by reference number <NUM> illustrates a high bit error rate (BER) when a high external magnetic field is applied to the memory cell. This represents normal operation of the memory cell when an external magnetic field is applied to the memory cell, and field compensation is not actuated. As noted above, the methods and structures that are described herein, adjust the write voltage to compensate for external magnetic fields that increase the bit error rate (BER) of the memory cell. The plot point identified by reference number <NUM> illustrates a reduction in the bit error rate (BER) in scenarios in which the write voltage has been increased to compensate for the external magnetic field. As illustrated by the plot point having reference number <NUM>, by increasing the write voltage through the write driver, the bit error rate (BER) of the memory cell when in the presence of an external magnetic field can be restored (reduced) to a level of normal operation, i.e., substantially equal to the bit error rate (BER), in the absence of an external magnetic field (as illustrated by plot point <NUM>). Referring to <FIG>, reference point <NUM> indicates that the bit error rate (BER) for a memory cell has been reduced from a high number of bit errors to a substantially low number of bit errors.

<FIG> is a plot illustrating write voltage shmoo with no external field and with a small applied field, in accordance with one embodiment of the present disclosure. Referring to <FIG>, the reference number <NUM> represents data points for the array write characteristics when no magnetic field is applied and reference number <NUM> represents data points for the array write characteristics when a magnetic field substantially aligned with the direction of the storage layer is applied. The presence of magnetic field stabilizes the storage layer and increases its programming current, shifting the write characteristics to the right and increasing the memory error rate under fixed bias conditions.

Referring to <FIG>, external magnetic fields are detected by the field detection circuit <NUM>. <FIG> is a block diagram illustrating one embodiment of a field detection circuit <NUM>. The field detection circuit <NUM> can be provided by magnetic field sensors <NUM>. In other embodiments, the field detection circuit <NUM> may include magnetic position and distance sensors, magnetic proximity switches, magnetic force and torque sensors, magnetic flowmeters and current sensors. The magnetic field sensor <NUM> is positioned proximate to the memory cell array. The reader <NUM>, watch cells <NUM>, and the sensor <NUM> depicted in the field detection circuit <NUM> are interconnected by a system bus <NUM>. The system bus <NUM> can provide for interconnectivity with the processing system <NUM> depicted in <FIG>.

The field detection circuit <NUM> is provided by watch cells <NUM>. A "watch cell" is a magnetic tunnel junction device used for detection of external magnetic fields. The watch cell <NUM> is positioned proximate to the memory cell (also referred to a bit cells). The watch cell is designed to register a change in electrical programing in response to external magnetic fields. By detecting the change in electrical programming of the watch cell <NUM>, the presence of an external magnetic field is detected.

In some embodiments, the watch-cells <NUM> have a lower switching field than the memory cells, e.g., MRAM bits. In other embodiments, to provide watch-cells with lower switching field than the memory cells, e.g., MRAM bits, the watch cells may have a different magnetic anisotropy field (Hk) characteristics than the memory cells.

In other embodiments, to provide that watch cells <NUM> for detecting external magnetic fields in the vicinity of memory cells <NUM>, the watch cells <NUM> may be configured to have a larger diameter than the memory cells <NUM>. The watch cells <NUM> may have a larger diameter biased under nominal voltage conditions. In this example, in the absence of magnetic field, the current applied to the watch cells <NUM> having the larger diameter geometry when compared to the memory cells <NUM> is not large enough to program the watch cells <NUM>, however that same level of current would program the memory cells. Further, when subjected to the presence of an external magnetic field, at least some of the watch cells <NUM> will be programmed at that same current that previously was insufficient to program the watch cells <NUM>. In this example, to determine the presence of an external magnetic field, the fraction of programmed cells is monitored. If the fraction of programmed cells for the watch cells <NUM> reaches a threshold when subjected to the current that is known not to be sufficient to program the watch cells <NUM> due to their greater diameter dimensions, the conditions warrant field compensation by adjusting the write bias in the array.

The watch cells <NUM> in the field detection circuit <NUM> employ watch-cells <NUM> biased at lower voltage than normal, e.g., a write error rate (WER) of 1x10-<NUM>. In this example, to determine the presence of an external magnetic field, the error rate would be monitored over time, and the write bias is adjusted to keep the write error rate (WER) constant. In some embodiments, in which the write error rate (WER) is monitored to determine the presence of an external magnetic field, additional array of bits for dedicated watch cells <NUM> are not required. By biasing the watch cells at a higher bit error rate (BER) point, it is possible to detect the presence of a magnetic field in fewer writes and improve the response time of the field detection circuit.

In each of the aforementioned examples, the sensing elements, e.g., watch cells <NUM>, magnetic field sensors <NUM>, or elements for measuring write error rates (WER), or a combination of the aforementioned sensing elements are periodically monitored. The periodic monitoring of the sensing elements of the field detection circuit <NUM> may be effectuated using a reader <NUM>, which may include a clock that schedules a monitor cycle. The reader <NUM> may also include at least one hardware processor and memory, the memory storing instructions to be executed by the hardware processor of the reader <NUM> for monitoring the watch cells <NUM> in determining the presence of external magnetic fields. In some embodiments, a field detection circuit <NUM> can periodically read the state of the watch-cells and look for disruptions indicative of external magnetic fields.

<FIG> depicts an array of memory cells including a field detection circuit for measuring external magnetic fields that includes watch cells having a different diameter than the memory cells, and write driver controller for controlling the write voltage to provide field compensation. Memory arrays are built as an array of bit cells, each of which stores <NUM> bit of data. The memory cells of the arrays depicted in <FIG> may be magnetic random access memory cells. In some embodiments, the memory cells includes an MRAM architecture that includes a cell with an access transistor and a MTJ (1T1MTJ) in the array. In the array, each bit cell is connected to a wordline and a bitline. For each combination of address bits, the memory asserts a single wordline that activates the bit cells in that row.

Referring to <FIG>, a plurality of memory banks 40a, 40b, 40c are depicted, wherein in each memory bank 40a, 40b, 40c there are many bit cell (BC) arrays <NUM>'. In the embodiment that is depicted in <FIG>, each array <NUM>' may have a supplemental column <NUM>' with magnetic tunnel junctions (MTJs) having a larger diameter or different magnetic anisotropy field (Hk) characteristics than the bit cells that provide the memory cell <NUM>. The supplemental column <NUM>' provides the watch cells <NUM> for the field detection circuit <NUM>. In the embodiment that is depicted in <FIG>, the watch cells <NUM> may be biased with the same conditions as the bit cell (BC) array <NUM>'. In some examples, due to the larger diameter of the MTJ for the watch cells <NUM> in the supplemental column <NUM>' relative to the MTJs for the bit cell (BC) arrays, the watch cells <NUM> in the supplemental column <NUM>' need the presence of an external magnetic field to switch, e.g., be programmed. In further examples, due to the different magnetic anisotropy field (Hk) characteristics for the watch cells <NUM> in the supplemental column <NUM>' relative to the MTJs for the bit cell (BC) arrays, the watch cells <NUM> in the supplemental column <NUM>' need the presence of an external magnetic field to switch, e.g., be programmed.

It is noted that the in the embodiment depicted in <FIG> there are three bit cell (BC) array blocks <NUM>'. It is noted that this example is provided for illustrative purposes only, and it is not intended that the present disclosure be limited to only this example. For example, any number of bit cell (BC) array blocks <NUM>' may be employed with the methods and the structures that provide for external magnetic field compensation.

Referring to <FIG>, in some embodiments, for further accuracy of determining whether the watch cells <NUM> in the supplemental column <NUM>' are switching, i.e., programmed, in response to an external magnetic field, there is a majority voter circuit <NUM>. that will detect the fraction of the switched cells. A majority voter circuit <NUM>,contains a set of combinatory logic gates with 'n' inputs coming from the watch cells read data of each block (40a, 40b, 40c). It has one output which returns true '<NUM>' if and only if more than <NUM>% of its inputs are true. The use of majority voter increases the accuracy of the external magnetic field detection by taking into account the process variation form array to array (<NUM>'). Based on the output of different majority voter circuits <NUM>, a write driver controller <NUM>', shmoos the voltage of the write driver, as shown in <FIG>. The write driver controller <NUM>' consists of a voltage divider which outputs a voltage value specific to its inputs (the digital data fed from the majority voter circuits).

To determine the presence of an external magnetic field the watch cells in the supplemental columns <NUM>' may be monitored. The watch cell diameters/Hk may be different from block to block. In the embodiment that is depicted in <FIG>, each of the bit cell (BC) arrays includes a supplemental column <NUM>' including watch cells <NUM> having a diameter with a different degree of deviation from the diameter of the memory cells <NUM> in the bit cell (BC) arrays. For example, the memory cells <NUM> in the bit cell arrays <NUM>' may include magnetic tunnel junction structures (MJTs) having a same diameter, which can be referred to a nominal diameter ("nom Dia"). In the embodiment depicted in <FIG>, the watch cells <NUM> in the supplemental column <NUM>' of the first block (block <NUM>) has magnetic tunnel junctions (MTJ) with a diameter that is larger than the nominal diameter of the memory cells <NUM> in the bit cell array <NUM>' by a differential value (Δ). In the adjacent block of bit cell (BC) arrays 40b, the watch cells <NUM> in the supplemental column <NUM>' have a diameter that is larger than the nominal diameter of the memory cells in the bit cell array <NUM>' by the differential value (Δ) by <NUM>, i.e., the watch cells <NUM> have a diameter of the nominal diameter plus two times the differential value (nom Dia + 2Δ). In the next block of bit cell (BC) arrays 40c, the watch cells <NUM> in the supplemental column <NUM>' have a diameter that is larger than the nominal diameter of the memory cells in the bit cell array <NUM>' by the differential value (Δ) by <NUM>, i.e., the watch cells <NUM> have a diameter of the nominal diameter plus three times the differential value (nom Dia + 3Δ). In this example, every block watch cell will detect a higher value of the external magnetic field. The larger the different in the diameter the greater the external magnetic field needed to program the watch cell <NUM>.

Referring to <FIG>, a write driver control circuit <NUM>' will tune the write current by dynamically trimming the write driver <NUM> based on the inputs from the majority voter circuits <NUM> from each block 40a, 40b, 40c. As illustrated in <FIG>, when a field is applied opposite to the direction of the write state, e.g., when trying to write a "<NUM>", but the field stabilizes the "<NUM>" state, the write current needs to be increased. In this case, the majority voter detects bits switching to the "<NUM>" state.

<FIG> illustrate some embodiments of the MRAM array, e.g., memory cells <NUM> in the blocks 40a, 40b, 40c, and biasing in connection with the write driver controller. <FIG> is a circuit diagram of one embodiment of an MRAM array as employed in the blocks depicted in <FIG>. The memory cells <NUM> include a magnetic tunnel junction (MJT) <NUM> and one or more access transistor <NUM>. Each memory cell <NUM> is associated with a bit line. The MRAM array and an on pitch bit line (BL)/source line (SL) switch correspond to a single bit line (BL) and sense line (SL) combination. A word line (WL) is in communication with access transistors to the magnetic tunnel junctions. In the embodiment depicted in <FIG>, the supplemental column <NUM>' includes watch cells having the nominal diameter plus the differential, as described above with the description of block 40a.

Still referring to <FIG>, the MRAM array further includes circuits for bit line multiplexing (BL MUXING) <NUM> and sense line multiplexing (SL MUXING) <NUM>. Multiplexing describes the operation of sending one or more signals over a common transmission line at different times or speeds and as such, in which the device to do just that is called a Multiplexer. The multiplexer, shortened to "MUX", is a combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control signal. In the embodiment depicted the MUX includes MOSFET's or relays to switch the voltage or current inputs through to a single output.

The circuits for bit line multiplexing (BL MUXING) <NUM> and sense line multiplexing (SL MUXING) <NUM> are in electrical communication with the write driver controller <NUM>. The write driver controller <NUM> receives input from the majority voter <NUM> for each of the blocks of arrays 40a, 40b, 40c. The write driver controller <NUM> tunes the write current by dynamically trimming the write driver <NUM> based on the inputs from the majority voter circuits <NUM> from each block 40a, 40b, 40c.

<FIG> illustrate how the array depicted in <FIG> is biased to provide write and read memory functions, and to provide that the supplemental column <NUM>' includes watch cells <NUM> is monitoring for external magnetic currents.

<FIG> is a circuit diagram of an MRAM array illustrating biasing to provide a write function to provide a "<NUM>" bit data storage value. In <FIG>, a single write line (WL) is selected, and the voltage is set to be equal to the WL activation voltage. The circuit for bit line multiplexing (BL MUXING) <NUM> is bias with a thick OX field effect transistor (WR0BIAS), and the select line multiplexing (SL MUXING) is set to force low. The unselected portions of the array are identified by regions 70a, 70b. The write driver controller <NUM> sets the above noted conditions for writing "<NUM>". As noted, the write driver control circuit <NUM>' will tune the write current by dynamically trimming the write driver <NUM> based on the inputs from the majority voter circuits <NUM> from each block 40a, 40b, 40c in order to compensate for the presence of an external magnetic field.

<FIG> is a circuit diagram of an MRAM array illustrating biasing to provide a write function to provide a "<NUM>" bit data storage value. In <FIG>, a single write line (WL) is selected, and the voltage is set to be equal to the WL activation voltage. The circuit for bit line multiplexing (BL MUXING) <NUM> is set to force low, and the select line multiplexing (SL MUXING) is bias with a thick OX field effect transistor (WR1BIAS). The unselected portions of the array are identified by regions 70c, 70d. The write driver controller <NUM> sets the above noted conditions for writing "<NUM>". As noted, the write driver control circuit <NUM>' will tune the write current by dynamically trimming the write driver <NUM> based on the inputs from the majority voter circuits <NUM> from each block 40a, 40b, 40c in order to compensate for the presence of an external magnetic field.

<FIG> is a circuit diagram of an MRAM array illustrating biasing for a read function, in accordance with one embodiment of the present disclosure. In <FIG>, a single write line (WL) is selected, and the voltage is set to be equal to the WL activation voltage The circuit for bit line multiplexing (BL MUXING) <NUM> is set to force low, and the select line multiplexing (SL MUXING) is connected to the sense amplifier. The unselected portions of the array are identified by regions 70e, 70d. The write driver controller <NUM> sets the above noted conditions for reading.

<FIG> depicts the present disclosure in which an external magnetic field is sensed in the presence of memory cells, and the write voltage is adjusted to compensate for the external magnetic field. is a schematic diagram of an array of memory cells in which external magnetic fields are detected by monitoring changes in write error rates. Similar to the embodiment depicted in <FIG>, the memory banks depicted in <FIG> contains many BC arrays. Every array has a supplementary column <NUM>' with MTJs on nominal size and electrically connected to a separate write path. In this embodiment, the watch cells are biased at sub nominal conditions compared to the bit cells in the blocks of arrays 40a, 40b, 40c. In some embodiments, a counter <NUM> is used to monitor the WER error rate of the watch cells and is periodically reset. For example, the counter <NUM> may monitor the WER error rate every <NUM>-<NUM> write cycles. In the embodiment depicted in <FIG>, when the WER error rate indicates the presence of an external magnetic field, the write driver control circuit will tune the write current by dynamically trimming the write driver based on the output of the counter.

In yet another embodiment, an alternative embodiment would be to shrink the access transistor to the watch cells. By shrinking the access transistor, the channel length is decreased and the write bias provided to the MTJs is reduced. Therefore using the same bias conditions for the BC arrays and watch cell arrays will result in a higher BER for the watch cell arrays. The mode of operation of this embodiment is similar to the previous embodiment but it provides additional simplicity since there is no need to specifically trim the bias conditions for the watch cells. In response to sensing the programming of the magnetic tunnel junctions of the watch cells <NUM>, the write driver control circuit can tune the write current by dynamically trimming the write driver <NUM> to compensate for the external magnetic field.

The methods and systems of the present disclosure advantageously allows for continuous operation of the chip even when a magnetic field is detected. A circuit design including a field detection device coupled to the write driver will adjust the programming voltage to offset the impact of the external magnetic field on the chip error rate.

Additionally, the field detection circuit <NUM> and write driver <NUM> (collectively identified with reference number <NUM>) that is depicted in <FIG> and <FIG> may be integrated into the processing system <NUM> depicted in <FIG>. The processing system <NUM> includes at least one processor (CPU) <NUM> operatively coupled to other components via a system bus <NUM>. A cache <NUM>, a Read Only Memory (ROM) <NUM>, a Random Access Memory (RAM) <NUM>, an input/output (I/O) adapter <NUM>, a sound adapter <NUM>, a network adapter <NUM>, a user interface adapter <NUM>, and a display adapter <NUM>, are operatively coupled to the system bus <NUM>. The bus <NUM> interconnects a plurality of components has will be described herein.

The processing system <NUM> depicted in <FIG>, may further include a first storage device <NUM> and a second storage device <NUM> are operatively coupled to system bus <NUM> by the I/O adapter <NUM>. The storage devices <NUM> and <NUM> can be any of a disk storage device (e.g., a magnetic or optical disk storage device), a solid state magnetic device, and so forth. The storage devices <NUM> and <NUM> can be the same type of storage device or different types of storage devices.

A speaker <NUM> is operatively coupled to system bus <NUM> by the sound adapter <NUM>. A transceiver <NUM> is operatively coupled to system bus <NUM> by network adapter <NUM>. A display device <NUM> is operatively coupled to system bus <NUM> by display adapter <NUM>.

A first user input device <NUM>, a second user input device <NUM>, and a third user input device <NUM> are operatively coupled to system bus <NUM> by user interface adapter <NUM>. The user input devices <NUM>, <NUM>, and <NUM> can be any of a keyboard, a mouse, a keypad, an image capture device, a motion sensing device, a microphone, a device incorporating the functionality of at least two of the preceding devices, and so forth. Of course, other types of input devices can also be used, while maintaining the scope of the present invention. The user input devices <NUM>, <NUM>, and <NUM> can be the same type of user input device or different types of user input devices. The user input devices <NUM>, <NUM>, and <NUM> are used to input and output information to and from system <NUM>.

Of course, the processing system <NUM> may also include other elements (not shown), as readily contemplated by one of skill in the art, as well as omit certain elements. For example, various other input devices and/or output devices can be included in processing system <NUM>, depending upon the particular implementation of the same, as readily understood by one of ordinary skill in the art. For example, various types of wireless and/or wired input and/or output devices can be used. Moreover, additional processors, controllers, memories, and so forth, in various configurations can also be utilized as readily appreciated by one of ordinary skill in the art. These and other variations of the processing system <NUM> are readily contemplated by one of ordinary skill in the art given the teachings of the present invention provided herein.

As employed herein, the term "hardware processor subsystem" or "hardware processor" can refer to a processor, memory, software or combinations thereof that cooperate to perform one or more specific tasks. In useful embodiments, the hardware processor subsystem can include one or more data processing elements (e.g., logic circuits, processing circuits, instruction execution devices, etc.). The one or more data processing elements can be included in a central processing unit, a graphics processing unit, and/or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The hardware processor subsystem can include one or more onboard memories (e.g., caches, dedicated memory arrays, read only memory, etc.). In some embodiments, the hardware processor subsystem can include one or more memories that can be on or off board or that can be dedicated for use by the hardware processor subsystem (e.g., ROM, RAM, basic input/output system (BIOS), etc.).

In some embodiments, the hardware processor subsystem can include and execute one or more software elements. The one or more software elements can include an operating system and/or one or more applications and/or specific code to achieve a specified result.

In other embodiments, the hardware processor subsystem can include dedicated, specialized circuitry that performs one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more application-specific integrated circuits (ASICs), FPGAs, and/or PLAs.

These and other variations of a hardware processor subsystem are also contemplated in accordance with embodiments of the present invention.

Reference in the specification to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment", as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following "/", "and/or", and "at least one of", for example, in the cases of "A/B", "A and/or B" and "at least one of A and B", is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of "A, B, and/or C" and "at least one of A, B, and C", such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

Claim 1:
A method for compensating for external magnetic fields in memory devices comprising:
positioning at least one external magnetic field sensing element (<NUM>) adjacent to at least one array of memory cells (<NUM>), wherein the array of memory cells comprises bit cells having a bit cell magnetic tunnel junction, MTJ (<NUM>), wherein a write driver (<NUM>) is in electrical communication with said at least one external magnetic field sensing element and said at least one array of memory cells, wherein the at least one external magnetic field sensing element is a watch cell, the watch cell comprising a watch cell access transistor to a watch cell magnetic tunnel junction that has different bias conditions than a bit cell access transistor (<NUM>) to a bit cell MTJ;
monitoring the at least one external magnetic field sensing element for signals indicative of the present of an external magnetic field; and
adjusting a write current to the at least one array of memory cells by trimming the write driver.