Patent Description:
Driver circuitry may operate, or drive, one or more light sources, such as light emitting diodes (LEDs). The driver circuitry may control a light intensity output by a light source by varying an average amount of electrical current flowing through the light source. For example, the driver circuitry may increase a duty cycle of an electrical current delivered to a light source to increase a light intensity generated by the light source. Similarly, the driver circuit may decrease the duty cycle of the electrical current delivered to a light source to decrease the light intensity generated by the light source. At high switching frequencies, a human eye may perceive a change in the duty cycle of the electrical current as a change in the brightness or intensity of the light generated by the light source.

<CIT> discloses a device for driving several light sources arranged in a matrix structure. The device comprises a diagnosis functionality which, when activated, makes it possible to determine whether each pixel cell to be diagnosed works or suffers from open-load or a short-circuit to ground issues.

<CIT> discloses another device for driving several light sources.

<CIT> discloses a method for compensating unwanted signals from pixel measurements in emissive displays.

<CIT> discloses a method for on-chip bias measurement of analog signals on an integrated circuit with a switchable analog-to-digital converter capable of performing testing and other types of processing.

One embodiment of the invention relates to a device according to claim <NUM>. Another embodiment relates to a method according to claim <NUM>.

A device includes at least two light sources and driver circuitry configured to selectively drive each light source of the at least two light sources. The driver circuitry is configured to drive the light sources based on the bit values in each frame of a bit stream received by the device. The device includes monitor circuitry configured to determine the voltage drop across each of the light sources. The monitor circuitry is configured to determine the voltage drop across a current source in the driver circuitry. The monitor circuitry may also be configured to determine whether there is a short circuit or open circuit across the specific light source. In some examples, the voltage drop across a specific light source may indicate whether the specific light source is functioning properly, whether there is a short circuit or open circuit across the specific light source, and/or whether the temperature of the specific light source is higher than a desirable operating temperature.

To determine the voltage drop across the specific light source, the device includes snooping circuitry configured to read a specific bit in a first frame of the bit stream as buffer circuitry of the device receives the first frame. The specific bit in the first frame that is received by the buffer circuitry indicates whether the driver circuitry will drive the specific light source during a second frame. In some examples, the second frame may immediately follow the first frame. By reading the specific bit as the buffer circuitry receives the first frame, the snooping circuitry causes the monitor circuitry to determine a voltage drop across a specific light source during the second frame.

Thus, the snooping circuitry reads the specific bit before the driver circuitry uses the specific bit to drive the specific light source. The snooping circuitry is configured to determine whether to cause the monitor circuitry to determine the voltage drop across the specific light source. In some examples, the snooping circuitry may be configured to determine whether the specific light source will be on or off during the next frame and to cause the monitor circuitry to determine the voltage drop based on the determination whether the specific light source will be on or off during the next frame. In other examples, the snooping circuitry may receive a request signal indicating a requested state for the specific light source, and the snooping circuitry may be configured to cause the monitor circuitry to determine the voltage drop based on comparing the requested state to the value of the specific bit.

<FIG> is a conceptual block diagram of a device <NUM> including at least two light sources <NUM>, in accordance with some examples of this disclosure. Device <NUM> may include light sources <NUM>, buffer circuitry <NUM>, driver circuitry <NUM>, monitor circuitry <NUM>, snooping circuitry <NUM>, and optional controller circuitry <NUM>. In some examples, device <NUM> may be a lighting device for a vehicle, a building, and/or any other system that includes a lighting device.

Light sources <NUM> may include two or more light sources such as light-emitting diodes (LEDs) or any other suitable light sources. Light sources <NUM> are arrayed in a matrix or grid formation, and each light source is a pixel. In some examples, light sources <NUM> may include one thousand and twenty-four light sources that are arrayed in a grid of thirty-two light sources by thirty-two light sources. Each of light sources <NUM> may be numbered in sequential order (see <FIG>). For a first frame of bit stream <NUM>, some of light sources <NUM> may be on, and some of light sources <NUM> may be off. From the first frame to a second frame of bit stream <NUM>, some of light sources <NUM> that were on in the first frame may remain on for the second frame, and some of light sources <NUM> that were on in the first frame may switch off for the second frame.

Buffer circuitry <NUM> is configured to receive bit stream <NUM>, which includes a series of bits. Each bit of bit stream <NUM> corresponds to a light source of light sources <NUM>. In some examples, buffer circuitry <NUM> may include a shift register with a number of bits that may be equal or approximately equal to the number of light sources in light source <NUM>. As a shift register, buffer circuitry <NUM> may include a cascade of flip flops sharing the same clock input. When buffer circuitry <NUM> has finished receiving a first frame of bit stream <NUM>, buffer circuitry <NUM> may deliver bit stream <NUM> to driver circuitry <NUM> and begin receiving a second frame of bit stream <NUM>. Each frame of bit stream <NUM> may include a number of bits that is equal to or approximately equal to the number of light sources in light sources <NUM>.

In some examples, buffer circuitry <NUM> may be configured to deliver a first frame of bit stream <NUM> to driver circuitry <NUM> in response to receiving an update signal. In some examples, the update signal may include a pulse or high digital value to indicate the end of each frame of bit stream <NUM>. As used herein, the terms "receiving an update signal" and "delivering an update signal" may mean receiving or delivering the high pulse of the update signal. The high pulse of the update signal may indicate that buffer circuitry <NUM> has received bit stream <NUM>. Device <NUM> may also include error-checking circuitry configured to determine whether each frame includes errors. If the error-checking circuitry determines that the first frame includes an error, device <NUM> may not deliver an update signal to cause buffer circuitry <NUM> to deliver the first frame of bit stream <NUM> to driver circuitry <NUM>. If the error-checking circuitry does not determine that a frame includes an error, device <NUM> may be configured to generate and deliver the update signal to the circuits of <FIG>. In response to receiving a high pulse of the update signal, buffer circuitry <NUM> may be configured to deliver a frame of bit stream <NUM> to driver circuitry <NUM>.

Bit stream <NUM> includes one or more frames, where each frame of bit stream <NUM> includes one or more bits such as specific bit <NUM>. Bit stream <NUM> includes a series of frames, where each frame includes a series of digital bits. Each bit of bit stream <NUM> may be a command signal to driver circuitry <NUM> for a light source of light sources <NUM>. Driver circuitry <NUM> may be configured to transmit each bit to a current source for the respective light source of light sources <NUM>. Each bit may command the respective current source to deliver electrical current to the respective light source of light sources <NUM>.

Driver circuitry <NUM> is configured to receive bit stream <NUM> from buffer circuitry <NUM>. Driver circuitry <NUM> is also configured to drive light sources <NUM> based on the bits in bit stream <NUM>. For example, driver circuitry <NUM> may be configured to drive a first light source based on a first bit and to drive a second light source based on a second bit. In some examples, a high bit such as a "<NUM>" in a frame may cause driver circuitry <NUM> to drive the corresponding light source during the frame, and a low bit such as a "<NUM>" may cause driver circuitry <NUM> to refrain from driving the corresponding light source.

If the frame rate for device <NUM> is one frame per five microseconds (i.e., two hundred kilohertz), each frame of bit stream <NUM> may cause driver circuitry <NUM> to drive, or refrain from driving, light sources <NUM> for five microseconds. To brighten or dim a light source of light sources <NUM>, processing circuitry may increase or decrease the percentage of high bits in the frames of bit stream <NUM>. At one frame per five microseconds, driver circuitry <NUM> may drive a specific light source based on two hundred thousand frames of a specific bit during a one-second time period. The apparent brightness of the specific light source to a human eye may be based on the percentage of frames in which the specific bit that corresponds to the specific light source has a high value.

Monitor circuitry <NUM> is configured to determine voltage drop <NUM> across a specific light source of light sources <NUM>. Monitor circuitry <NUM> may be configured to determine the voltage drop across each light source of light sources <NUM> by using one or more multiplexers. The multiplexers may allow monitor circuitry <NUM> to measure the voltage drop across one or more of the light sources during each frame of bit stream <NUM>. In some examples, monitor circuitry <NUM> may include one or more levels of multiplexers. The first level of multiplexers may include a number of inputs that is equal to the number of light sources <NUM>. Monitor circuitry <NUM> may include an analog-to-digital converter (ADC) configured to receive an analog output signal of the last level of multiplexers, which may indicate the voltage drop across a light source. The ADC may be configured to convert the analog output signal to a digital signal. The digital signal may indicate the approximate amplitude of the voltage drop across a light source of light sources <NUM>.

In some examples, monitor circuitry <NUM> may be configured to determine the voltage drop across a first light source during a first frame, determine the voltage drop across a second light source during a second frame, and so on. Whether monitor circuitry <NUM> continues monitoring the first light source during successive frames depends on whether a user selects a different light source, a different current source, or a different bit. The user may be a control device that includes processing circuitry configured to, from time to time, requests light source(s), current source(s), and/or bit(s) to be monitored. In some examples, monitor circuitry <NUM> may be capable of determining the voltage drop across only one light source during each frame. In other examples, monitor circuitry <NUM> may be capable of determining the voltage drop across more than one light source during each frame.

In accordance with the techniques of this disclosure, snooping circuitry <NUM> is configured to read specific bit <NUM> as buffer circuitry <NUM> receives bit stream <NUM>. Snooping circuitry <NUM> is further configured to cause monitor circuitry <NUM> to determine voltage drop <NUM> across a specific light source based on the value of specific bit <NUM>. For example, if the value of specific bit <NUM> is a "<NUM>", snooping circuitry may be configured to cause monitor circuitry <NUM> to determine voltage drop <NUM> across the specific light source. If the value of specific bit <NUM> is a "<NUM>", snooping circuitry may be configured to refrain from causing monitor circuitry <NUM> to determine voltage drop <NUM> across the specific light source. In some examples, snooping circuitry <NUM> may cause monitor circuitry <NUM> to determine voltage drops across light sources that are on. In other examples, snooping circuitry <NUM> may cause monitor circuitry <NUM> to determine a voltage drop across a specific light source during a frame, regardless of whether the specific light source is on or off during the frame.

After reading specific bit <NUM>, snooping circuitry <NUM> may be configured to cause monitor circuitry <NUM> in response to receiving an update signal, such as in response to receiving a high pulse of the update signal. Snooping circuitry <NUM> may be configured to read specific bit <NUM> before receiving the pulse of the update signal. After snooping circuitry <NUM> receives the update signal indicating the end of the first frame, snooping circuitry <NUM> may be configured to read a bit from the next frame. In some examples, the position of the bit in the next frame may be based on whether device <NUM> receives user input selecting a light source that is different than the specific light source. If a user selects a different light source or a different bit, snooping circuitry <NUM> may be configured to read the different bit during the next frame.

If the user does not select a different light source or a different bit, snooping circuitry <NUM> may be configured to read specific bit <NUM> as buffer circuitry <NUM> receives the next frame. Snooping circuitry <NUM> may be further configured to cause monitor circuitry <NUM> to determine, as buffer circuitry <NUM> receives a third frame, a second voltage drop across the specific light source based on a value of specific bit <NUM>. In some examples, the third frame may immediately follow the second frame (i.e., the third frame). Snooping circuitry <NUM> may be configured to cause monitor circuitry <NUM> to continue monitoring the specific light source until a user selects a different light source or until specific bit <NUM> has an inactive value (e.g., a "<NUM>") in a later frame.

Snooping circuitry <NUM> is configured to determine a position of specific bit <NUM> in bit stream <NUM> based on a position of the specific light source. The specific light source is positioned in a matrix (i.e., grid) of light sources <NUM>. Snooping circuitry <NUM> is configured to determine the position of specific bit <NUM> in bit stream <NUM> by at least accessing a lookup table associating positions of bits in bit stream <NUM> and position of light sources <NUM> in the matrix.

In some examples, snooping circuitry <NUM> may include counter circuitry that is configured to count the position of specific bit <NUM> as buffer circuitry <NUM> receives bit stream <NUM>. For example, snooping circuitry <NUM> may determine that specific bit <NUM> is located in a specific positon with bit stream <NUM>, such as a sixth position. As buffer circuitry <NUM> receives a frame of bit stream <NUM>, the counter circuitry may count to the specific position. In some examples, the counter circuitry may be configured to increment a count until the count is equal to the number of the specific position. The counter circuitry may then be configured to read specific bit <NUM> in response to counting the position of specific bit <NUM>.

Snooping circuitry <NUM> and/or monitor circuitry <NUM> may be configured to determine whether the specific light source is on or will be on before monitor circuitry <NUM> determines the voltage drop across the specific light source. In some examples, monitor circuitry <NUM> may be configured to determine the voltage drop across the specific light source if and only if the specific light source is or will be on during the voltage measurement. In other examples, monitor circuitry <NUM> may be configured to determine the voltage drop across the specific light source regardless of whether the specific light source is or will be on during the voltage measurement. The capability of snooping circuitry <NUM> to read specific bit <NUM> in a frame of bit stream <NUM> as the frame is received by buffer circuitry <NUM> may allow device <NUM> to synchronize the determination of a voltage drop across a specific light source. The determination may be synchronized by selecting a light source that will be on during the measurement, by selecting a light source that will be off during the measurement, and/or by selecting a light source based on the value of specific bit <NUM>.

Controller circuitry <NUM> may be configured to determine whether voltage drop <NUM> is within an acceptable voltage window. The acceptable voltage window may include an upper threshold that is less than an open-circuit voltage and a lower threshold that is more than a short-circuit voltage. The thresholds of the acceptable voltage window may be established based on acceptable operating temperatures, such that determining voltage drop <NUM> outside of the acceptable voltage window may indicate an unacceptable temperature. Controller circuitry <NUM> may be configured to cause driver circuitry <NUM> to increase or decrease voltage drop <NUM> across the specific light source in response to determining that voltage drop <NUM> across the light source is not within the acceptable voltage window.

In accordance with the techniques of this disclosure, snooping circuitry <NUM> is configured to read specific bit <NUM> as buffer circuitry <NUM> receives a first frame of bit stream <NUM>. Snooping circuitry <NUM> is configured to determine the value of specific bit <NUM> and cause monitor circuitry <NUM> to determine voltage drop <NUM> based on the value of specific bit <NUM>. Snooping circuitry <NUM> is configured to read specific bit <NUM> as buffer circuitry <NUM> receives the first frame of bit stream <NUM>, so that monitor circuitry can determine voltage drop <NUM> as driver circuitry <NUM> is driving light sources <NUM> based on the first frame of bit stream <NUM>.

For example, snooping circuitry <NUM> reads specific bit <NUM> of a first frame of bit stream <NUM>. When buffer circuitry <NUM> receives an update signal, buffer circuitry <NUM> may deliver the first frame to driver circuitry <NUM> and begin receiving a second frame of bit stream <NUM>. Driver circuitry <NUM> is configured to drive light sources <NUM> based on the first frame of bit stream <NUM>. While driver circuitry <NUM> is driving light sources <NUM> based on the first frame, snooping circuitry <NUM> is configured to cause monitor circuitry <NUM> to determine voltage drop <NUM> across the specific light source. By reading specific bit <NUM> as buffer circuitry <NUM> receives the first frame, snooping circuitry <NUM> may prepare monitor circuitry to determine voltage drop <NUM> as driver circuitry <NUM> drives light sources <NUM> based on the first frame. In some examples, snooping circuitry <NUM> may be configured to compare the value of specific bit <NUM> to a requested state and cause monitor circuitry <NUM> to determine the voltage drop based on the comparison of the value of specific bit <NUM> to the requested state.

<FIG> shows an exemplary arrangement comprising a light source array <NUM> which is placed on top of a semiconductor device <NUM>, in accordance with some examples of this disclosure. Device <NUM> may include light source array <NUM>, semiconductor device <NUM>, printed circuit board (PCB) <NUM>, and wire bond(s) <NUM>. Light source array <NUM> and semiconductor device <NUM> may be a chip-on-chip assembly. Light source array <NUM> may include at least two light sources. Semiconductor device <NUM> may be arranged on PCB <NUM>. Semiconductor device <NUM> may be electronically connected to PCB <NUM> via bond wires <NUM>.

Semiconductor device <NUM> may comprise at least one of the following: current sources for individual light sources arranged on light source array <NUM>, in particular at least one current source for each light source; a communication interface for driving the light sources and for management purposes; generation of at least one reference current; and diagnosis and protection functionality. For such purposes, semiconductor device <NUM> may comprise an array of silicon cells, wherein each silicon cell (also referred to as pixel cell) may comprise a current source, which may be directly connected to a light source of light source array <NUM>. In addition, semiconductor device <NUM> may comprise current source regulation circuitry or any other circuitry as discussed throughout.

In some examples, the at least one current source of semiconductor device <NUM> may be a part of driver circuitry configured to drive light source array <NUM> based on a bit stream. The communication interface of semiconductor device <NUM> may be a part of buffer circuitry configured to receive the bit stream and deliver the bit stream to the driver circuitry. Semiconductor device <NUM> may be configured to receive a bit stream through bond wire(s) <NUM> and an electrical connection in PCB <NUM>. In some examples, semiconductor device may include <NUM>,<NUM> current sources, each directly connected to a LED of light source array <NUM>. Semiconductor device <NUM> may independently control the current sources in order to generate the correct light pattern either in beam shape and intensity.

In some examples, device <NUM> may be a high-pixel LED driver, where light source array <NUM> may be an LED array of <NUM>,<NUM> pixels that is mounted on top of a silicon substrate array (i.e., semiconductor device <NUM>) in a chip-on-chip assembly solution. In some examples, semiconductor device <NUM> may be an intelligent, smart silicon-substrate chip. The smart silicon substrate may include an array of pixel cells called an LED driver matrix and may be placed and directly connected to each respective LED of light source array <NUM>. Each pixel cell of light source array <NUM> may include an area of <NUM> by <NUM>. The smart silicon substrate may also include common circuitry outside the LED matrix area, where the common circuitry may include, for example, the communication interfaces or diagnosis and protection circuitry. The common circuitry may add to the total volume of device <NUM>, and it may be desirable to have a smaller volume for device <NUM>.

<FIG> shows an exemplary block diagram of a matrix <NUM> of light sources <NUM> and a semiconductor device <NUM> comprising driver circuitry <NUM>, in accordance with some examples of this disclosure. Each pixel of matrix <NUM> may be represented by at least one light source <NUM>. Driver circuitry <NUM> may be a portion of semiconductor device <NUM> that is associated with each one pixel of light source array <NUM>). Semiconductor device <NUM> may also include circuitry <NUM>. Semiconductor device <NUM> may be connected to a serial interface <NUM>. Respective light sources <NUM> of matrix <NUM> may be controlled via serial interface <NUM>. Matrix <NUM> may be arranged on top of driver circuitry <NUM>. Driver circuitry <NUM> may be part of the semiconductor device <NUM> as shown in <FIG> and may comprise a pixel cell area (also referred to as "pixel cell") for each light source <NUM> of matrix <NUM>. It is an option that driver circuitry <NUM> has (e.g., substantially) the same area size as matrix <NUM>. In particular, the pixel cell area of driver circuitry <NUM> may have the same surface area as an individual one light source <NUM>. Light sources <NUM> of matrix <NUM> may be directly connected to the pixel cells of driver circuitry <NUM>. Matrix <NUM> may in particular be arranged on top of driver circuitry <NUM>.

Circuitry <NUM> may comprise a serial interface for accessing light sources <NUM> of matrix <NUM>, e.g., one register <NUM> for configuration purposes, reference current generator <NUM>, reference voltage generator <NUM> and temperature sensor <NUM>, and may be arranged in an area adjacent or distant to driver circuitry <NUM>. In some examples, circuitry <NUM> may also include buffer circuitry configured to receive a bit stream and to deliver the bit stream to driver circuitry <NUM>. Matrix <NUM> may comprise an arbitrary number of light sources (e.g., pixels) arranged in columns and rows. For example, matrix <NUM> may comprise <NUM> light sources, <NUM> light sources, <NUM>,<NUM> light sources, etc. In the example shown in <FIG>, matrix <NUM> comprises sixteen rows and sixteen columns of light sources <NUM>, amounting to two hundred and fifty-six light sources. An LED may be one example of a light source. It may be an option to use any kind of light source, in particular semiconductor light source. It is another option that each light source may be a component comprising at least two semiconductor light sources.

In an exemplary application, each pixel of matrix <NUM> may occupy a surface area of, for example, less than <NUM> by <NUM> although surface area occupation may be implementation-specific. Any area suitable for a predetermined resolution of light source array <NUM> may be selected. The semiconductor light source may be arranged in the middle of each pixel cell. Adjacent pixel cells may have a gap between light sources amounting to less than <NUM>. Each light source may have one contact connected to driver circuitry <NUM> and one contact connected to a common contact, e.g., GND. This is an exemplary scenario; other dimensions, distances and connections may apply accordingly.

With each light source being mounted directly on top of the semiconductor device, each current source is placed in an area defined by the surface area of the pixel cell. In the example provided above, the area amounts to <NUM> · <NUM> = <NUM><NUM>. For increasing the resolution in x- and y-dimensions (e.g., <NUM>°) of the light at long distance and for avoiding extra mechanical components for beam leveling adjustment, a short pitch between the pixel cells is beneficial. In the example provided above, the pitch between pixel cells may be less than <NUM>.

Due to the compact arrangement, a high amount of heat sources may generate different temperatures, which may influence temperature gradients and hence lead to a mismatch between pixels. In addition, the output of each current source per pixel cell may not be directly accessible as the driver circuitry is directly connected to the light sources. Hence, a solution is required that provides at least one of the following: a current source that provides current to the individual light source, which allows switching the light source on or off with high accuracy, optionally providing over-current protection; a diagnostic functionality capable of detecting an open-load and a short to ground of the output channel; a low mismatch between different pixels, i.e., between different current sources; current source regulation circuitry as discussed throughout; etc..

An external device may independently control the state of the pixels of matrix <NUM> by transmitting a bit stream via serial interface <NUM>. Circuitry <NUM> may be configured to store the incoming bit stream data in a memory buffer in order to check its integrity. Circuitry <NUM> may be configured to deliver the bit stream to driver circuitry <NUM> only if the integrity check is successful. Device <NUM> may be configured to run a diagnosis of matrix <NUM>, in particular how to monitor the forward voltages of each light source and the variation over time caused for example by a temperature change, for example. Current source outputs may not accessible because they are covered by the light source array. To cope with this limitation, the output net may be observable to the common circuitry part via a group of analog multiplexers that are configured by the system. Circuitry <NUM> and/or <NUM> may then convert this voltage by an analog to digital data converter for further processing.

Successive frames of the bit stream may form a pulse-width modulated (PWM) signal to modulate the light sources. Additionally or alternatively, the bit stream may also form a pulse-density modulated (PDM) signal and/or a pulse-frequency modulated (PFM) signal. In some examples, circuitry <NUM> may indicate a desired state such that the conversion should be executed when the LED is in the desired state. For example, when the desired state is on, the state of the specific light source should stay stable during the conversion. If the PWM generator is not integrated in device <NUM> but is calculated externally by a microcontroller or by a field-programmable gate array (FPGA) and then transferred to the light source array, it may be difficult to synchronize the diagnostic, for example of an ADC, to a configurable state of the specific light source. The complication may arise from determining the state of the specific light source in a short period of time and consideration of also possible communication errors.

<FIG> shows exemplary driver circuitry including high-side current sources <NUM>, <NUM>, and <NUM>, in accordance with some examples of this disclosure. Each of current sources <NUM>, <NUM>, and <NUM>, each of which being arranged on driver circuitry <NUM> on top of which light sources <NUM>, <NUM>, and <NUM> are mounted. In this scenario, light source <NUM> is arranged on top of current source <NUM>, light source <NUM> is arranged on top of current source <NUM> and light source <NUM> is arranged on top of current source <NUM>.

Each current source <NUM>, <NUM>, and <NUM> may be an NMOS power stage with the drain connected to supply voltage VCC, and with the source connected with the respective light sources <NUM>, <NUM>, and <NUM>. The gate of each NMOS power stage may be controlled via a corresponding error amplifier <NUM>, <NUM>, and <NUM>, and each error amplifier <NUM>, <NUM>, and <NUM> may be used to control the output current using an internal reference current. Each error amplifier <NUM>, <NUM>, and <NUM> may be enabled by a digital or by an analog signal.

In light of the foregoing, driver circuitry <NUM> may thus comprise a relatively large number of current sources and/or switches on the area available for a pixel cell (in case the driver circuitry is physically below the light source array). Examples presented herein in particular show how an efficient solution for the light source array and the underlying driver circuitry may be realized even if the driver circuitry is arranged on a silicon semiconductor device (e.g., single chip). Examples provided in particular cope with a high number of heat sources as well as heat gradients between current sources of the pixel cells.

Other examples presented herein allow providing driver circuitry comprising in particular at least one of the following: a communication interface for controlling the drivers for each pixel cell; an output current regulation with self-protection against over-current; an open-load and short to ground diagnostic functionality; and a low temperature sensitivity. In some examples, the communication interface may be part of buffer circuitry. This may in particular be achieved by distributing a control logic between a circuitry and the driver circuitry, both integrated on a semiconductor device. The circuitry may be arranged adjacent to the driver circuitry and the driver circuitry may take the same surface area than the light source array, which can be arranged on top of the driver circuitry as explained above. As an option, the circuitry may be arranged in an area adjacent or distant to the driver circuitry.

A challenge is how to efficiently drive the current sources, wherein one current source is placed (or associated with) a pixel cell. As shown in the example described above, the distance between two pixel cells (e.g., less than <NUM>) may set forth limiting restrictions, which makes it difficult to electrically connect all current sources that are arranged below their associated light sources such that they can be driven by the circuitry of the semiconductor device.

<FIG> shows an exemplary driver circuitry <NUM> for light source <NUM>, in accordance with some examples of this disclosure. <FIG> may also show buffer circuitry configured to receive and deliver a bit stream to driver circuitry <NUM>. The buffer circuitry may include flip-flops <NUM> and <NUM>. Flip-flop <NUM> may be configured to receive a bit of a bit stream at the node labeled "D" and from the node labeled Data_i. When flip-flop <NUM> receives an active clock signal from the node labeled clk, flip-flop <NUM> may be configured to output the bit at the node labeled "Q". When flip-flop <NUM> receives an active clock signal from the node labeled Clk _update, flip-flop <NUM> may be configured to output the bit at the node labeled "Q". In some examples, the bit may enable error amplifier <NUM> to drive current source <NUM> and reference switch <NUM>.

Reference switch <NUM> may be configured to conduct a lower-amplitude electrical current than the electrical current conducted by current source <NUM>. The KILIS factor between reference switch <NUM> and current source <NUM> may be one to fifty. Driver circuitry <NUM> may be configured to output the reference current conducted by reference switch <NUM> at the node labeled "Iref". Current source <NUM> may conduct an electrical current from a power supply labeled VDDP, and driver circuitry <NUM> may output the electrical current at the node labeled OUT2.

A device of this disclosure may include monitor circuitry configured to determine a voltage drop across light source <NUM>. To determine the voltage drop across light source <NUM>, the monitor circuitry may deliver a control signal through the node labeled Pixel_selection to the control terminal of switch <NUM>. The control signal may cause switch <NUM> to transmit a voltage signal to a multiplexer (see <FIG>), where the voltage signal may indicate the voltage drop. The voltage drop across light source <NUM> may be referred to as the forward voltage of light source <NUM>. In some examples, the voltage drop across light source <NUM> may indicate the temperature of light source <NUM>, whether there is a short circuit across light source <NUM>, and/or whether there is an open circuit across light source <NUM>.

<FIG> shows an exemplary circuitry that may be arranged on a semiconductor device for two pixel cells N and N+<NUM>. In this example, circuitry <NUM> may supply an update signal UPD, a data signal DATA_I and a clock signal CLK. Pixel cell N may deliver a data signal DATA_I+<NUM> to the pixel cell N+<NUM>, and pixel cell N+<NUM> may deliver a data signal DATA_I+<NUM> to a subsequent pixel cell (not shown).

In practice, data signal DATA_I may be a bit stream, i.e., a sequence of binary signals (e.g., "<NUM>" and "<NUM>") that are conveyed to a shift register. Each cell of the shift register may include a D-flip-flop, e.g., D-flip-flop <NUM> for pixel N and D-flip-flop <NUM> for pixel N+<NUM>. In this example, data signal DATA_I may be connected to the D-input of D-flip-flop <NUM>, the Q-output of D-flip-flop <NUM> may be connected to the D-input of D-flip-flop <NUM>. Both D-flip-flops <NUM> and <NUM> are driven by clock signal CLK. Hence, a sequence of "<NUM>" and "<NUM>" values may be conveyed to D-flip-flops <NUM> and <NUM>, wherein with each clock cycle (rising edge) of clock signal CLK, the actual value stored in D-flip-flop <NUM> is shifted to subsequent D-flip-flop <NUM> and the subsequent value provided by data signal DATA_I is stored in D-flip-flop <NUM>. According to the example shown, a bit sequence of first <NUM>, then <NUM> is - after two clock cycles - stored in D-flip-flops <NUM> and <NUM> such that D-flip-flop <NUM> has a value "<NUM>" and D-flip-flop <NUM> has the value "<NUM>". D-flip-flops <NUM> and <NUM> may be a part of buffer circuitry <NUM>.

A light source, e.g., light source, for pixel N may be driven via a terminal <NUM> of a register, e.g., D-flip-flop <NUM>. Similarly, a light source for pixel N+<NUM> may be driven via a terminal <NUM> of a register, e.g., D-flip-flop <NUM>. The D-input of D-flip-flop <NUM> may be connected to the Q-output of D-flip-flop <NUM> and the D-input of D-flip-flop <NUM> may be connected to the Q-output of D-flip-flop <NUM>. The enable (or clock) inputs of both D-flip-flops <NUM> and <NUM> may be connected to update signal UPD. When update signal UPD becomes "<NUM>" the value stored in D-flip-flop <NUM> may become visible at the Q-output of D-flip-flop <NUM> and hence may be used to drive the light source for this pixel N. Accordingly, the value stored in D-flip-flop <NUM> may become visible at the Q-output of D-flip-flop <NUM> and hence may be used to drive the light source of pixel N+<NUM>. Hence, the shift register exemplarily shown in <FIG> comprises two cells, wherein the cell for pixel N may include D-flip-flop <NUM> and register <NUM> and the cell for pixel N+<NUM> may include D-flip-flop <NUM> and register <NUM>.

<FIG> shows only an exemplary excerpt of a sequence of two pixel cells. This approach, however, may be applied to a sequence of more than two pixel cells, e.g., a column or a row of a matrix of pixels. In addition, several rows or columns may be connected and represented by an even longer shift register. Insofar, the shift register may be used for providing a data signal to all pixels of a column or line or even matrix and to update the column, line or matrix at once.

The frequency of clock signal CLK may advantageously be high enough to fill the shift registers for such sequence of pixels before the update signal UPD is activated and before the values stored at that time in the respective shift register are used to control the pixels of this sequence, e.g., column or row of the matrix of pixels. Hence, a high refresh rate for each pixel may result in a high resolution of a PWM/PDM/PFM dimming. Therefore, a high clock frequency may be advantageous to store the information in the flip-flop of the shift-register before triggering the update signal. In some examples, buffer circuitry may receive a frame of a bit stream in approximately five microseconds. At the end of a frame of the bit stream, the buffer circuitry may receive an active update signal, causing flip-flops <NUM> and <NUM> to deliver the respective bits to respective terminals <NUM> and <NUM>. Thus, the device may update the status of the light sources for every frame, which may last five microseconds in some examples.

Advantageously, by providing registers (e.g., D-flip-flops according to <FIG>) in daisy-chain fashion (one pixel driving the next one) and arranging those registers together with the respective pixel cells, a single line may suffice to convey data signal DATA_I to a sequence of pixels, whereas otherwise each pixel would require a separate connection to convey the data signal for controlling this pixel. It is noted that any sort of register or memory may be used to achieve the result described above. The register may be a flip-flop, a latch, register or any other element with a memorizing functionality.

<FIG> illustrates a graph of an update signal for two frames of a bit stream, in accordance with some examples of this disclosure. The update signal is described with respect to device <NUM> in <FIG>, although other devices and circuits in other FIGS. may also generate or receive update signals. Device <NUM> may include a communication serial interface consisting of a clock-, data-, and update-line based on a synchronous clock forward scheme. The clock signal, which may have the same frequency as the bit rate of bit stream <NUM>, where it is provided the clock to be used as reference to sample the data and update signals. A frame may include a new state of all of light sources <NUM>, and the update signal may mark the end of the frame, as well as any error-correction bits or error-checking bits. Device <NUM> may check incoming data for consistency, for example to determine if the frame length is correct. Device <NUM> may not store the incoming data, instead forwarding the new data to driver circuitry <NUM> when the frame ends. When the frame is complete and marked as valid, the new data may be applied to driver circuitry <NUM> and the states of the pixels are updated.

At the end of each frame of bit stream <NUM>, device <NUM> may generate an update signal. The high pulse of the update signal may indicate the end of a frame and/or that the frame is free of transmission errors. In some examples, device <NUM> may deliver the update signal to buffer circuitry <NUM> and snooping circuitry <NUM>. Device <NUM> may be configured to generate an update signal based on determining that a frame of bit stream <NUM> is complete and further based on not detecting any errors in the frame. Device <NUM> may be configured to check bit stream <NUM> for consistency, for example if frame length is correct.

During the time period that the update signal has low amplitude <NUM>, buffer circuitry <NUM> may be receiving Frame(n) of bit stream <NUM> and driver circuitry <NUM> may be driving light sources <NUM> based on Frame(n-<NUM>) of bit stream <NUM>. During the time period that the update signal has low amplitude <NUM>, buffer circuitry <NUM> may be receiving Frame(n+<NUM>) of bit stream <NUM> and driver circuitry <NUM> may be driving light sources <NUM> based on Frame(n) of bit stream <NUM>.

Buffer circuitry <NUM> may be configured to deliver the frame of bit stream <NUM> to driver circuitry <NUM> in response to receiving the update signal. "Receiving the update signal," as used herein, means receiving a high pulse of the update signal, such as one of pulses <NUM>, <NUM>, and <NUM>. Snooping circuitry <NUM> may be configured to cause monitor circuitry <NUM> to determine voltage drop <NUM> in response to receiving the update signal, i.e., receiving one of high pulses <NUM>, <NUM>, and <NUM>.

<FIG> is a conceptual block diagram of device <NUM>, in accordance with some examples of this disclosure. Buffer circuitry <NUM> ("frame buffer") is configured to receive a first frame of bit stream <NUM>. As buffer circuitry <NUM> receives the first frame, snooping circuitry <NUM> is configured to read specific bit <NUM>. Buffer circuitry <NUM> may be configured to hold and/or shift the first frame until buffer circuitry <NUM> receives an update signal. When buffer circuitry <NUM> receives the update signal, buffer circuitry <NUM> may be configured to deliver the first frame to driver circuitry <NUM> ("frame actual").

When driver circuitry <NUM> receives the first frame of bit stream <NUM>, driver circuitry <NUM> may be configured to drive light sources <NUM> based on the first frame. As driver circuitry <NUM> is driving light sources <NUM> based on the first frame, buffer circuitry <NUM> may be receiving a second frame of bit stream <NUM>. Driver circuitry <NUM> may be configured to store the first frame until buffer circuitry <NUM> and/or driver circuitry <NUM> receives an update signal. Driver circuitry <NUM> may be configured to update the states of light sources <NUM> based on each frame that driver circuitry <NUM> receives.

Buffer circuitry <NUM> may be implemented with a shift register acting as a frame buffer. In some examples, buffer circuitry <NUM> and/or driver circuitry <NUM> may include a shadow register holding the actual state of the pixels (see <FIG>). The data is shifted into a shift register and as soon as the phase shift is completed, the data is written into the shadow register during the high-phase or high pulse of the update signal. The output of the shadow register may be connected to the respective pixel cell: if all the shift registers and shadow registers are placed in the common part of the silicon the consequence may be an increase of area. The increase in area may result in usage of all of the available metal connection and therefore routing congestion issues.

The shift register and shadow registers may be distributed across the pixel matrix with a slice in each pixel cell: in this way each pixel driver may drive the next one in a sort of daisy-chain. <FIG> shows an example of a serial interface slice including a flip flop (shift) and a latch (store element) placed in each cell. As a consequence, there may be no information in the common circuitry about the status of the pixels in order to not have a bigger area overhead (overhead may be equal to die area outside matrix area that in theory is useless).

<FIG> illustrates monitor circuitry <NUM> for determining a voltage drop across at least two light sources <NUM>, in accordance with some examples of this disclosure. At a system level, it may be important to have the option to monitor the forward voltage of light sources <NUM> to determine, for example, an indication of the temperature of each of light sources <NUM>. The output voltages of the current sources may not be directly accessible because the pixels may be covered by the light source array chip. The pixel under monitor may be selectable by the user via a dedicated register. Analog multiplexers may be implemented in monitor circuitry <NUM> in order to have the selected output node accessible. The ADC may convert the selected voltage for further processing by a digital signal processor or a microcontroller. The ADC may be integrated in driver circuitry <NUM> or monitor circuitry <NUM> together with control logic such as central logic circuitry <NUM>.

The system selects the pixel and the desired state for the conversion, and then the system requests an ADC conversion. The task of central logic circuitry <NUM> is to synchronize the start of the ADC conversion to the actual state of the light sources. The state of the light source may not be known outside the pixel cell, and the central logic circuitry <NUM> may have to reconstruct such information. To avoid an overly burdensome reconstruction, snooping circuitry may look at or "snoop into" the incoming serial stream going to the shift register spread over the pixel matrix. The snooping circuitry may extract the bit corresponding to the pixel to be monitored. Additionally, the coherence with the matrix may be more likely because an invalid frame may not update the shadow register or the light source status flag. Central logic circuitry <NUM> may use the light source status flag to handle the ADC conversion, starting it in the right moment and eventually aborting it if the light source toggles during the conversion.

Central logic circuitry <NUM> may be configured to select a row and a column for a specific light source of light sources <NUM>. Central logic circuitry <NUM> may be configured to deliver control signals to multiplexers <NUM> and <NUM>. Multiplexer <NUM> may be configured to deliver an output signal to ADC <NUM> for conversion of the analog signal to a digital signal.

Multiplexers <NUM> may be configured to configured to receive, as inputs, voltage drop connections for each light source of light sources <NUM>. Each of light sources <NUM> may include an electrical connection to one of multiplexers <NUM>. As depicted in <FIG>, light sources <NUM> may include five rows and five columns. In the example of <FIG>, all of the light sources of a column may be electrically connected as inputs to one of multiplexers <NUM>. Central logic circuitry <NUM> may be configured to connect one of light sources <NUM> to ADC <NUM> through multiplexers <NUM> and <NUM>.

Central logic circuitry <NUM> may be configured to generate and/or receive inputs for row select and column select. For example, central logic circuitry <NUM> may select a specific light source at row one and column one. Central logic circuitry <NUM> may be configured to select the row and column based on the mapping of each of light sources <NUM>. In some examples, central logic circuitry <NUM> may be configured to determine the row and column of the specific light source and to transmit the row and column coordinates to mapping circuitry. The mapping circuitry may be configured to convert the row and column coordinates to a position of a specific bit in a frame of a bit stream. Snooping circuitry may be configured to read the value of the specific bit based on the position determined by the mapping circuitry.

The system may be simplified by letting the driver circuitry autonomously manage the light source forward voltage diagnostic. The master chip may request a conversion to a dedicated pixel in a defined, or requested, state and then either read back the converted digital value or an error message if feature implemented. If multiple driver circuits are present the synchronization may be relatively simple, as compared to other devices that lack snooping circuitry. The snooping circuitry may synchronize an embedded ADC to the light source status for an intelligent silicon substrate designed to drive a matrix including light sources. By reading the specific bit as the buffer circuitry receives the bit stream, the snooping circuitry may be configured to determine the status of the LED under diagnosis and send the status to the ADC controller. In some examples, a transmission error may cause the snooping circuitry to not send the status to the ADC controller.

In some examples, a device of this disclosure may be part of an adaptive driving beam front light system for a vehicle. The device may also be used for lighting, automotive, aviation, and/or any other suitable applications. The snooping circuitry of this disclosure helps the system to manage the monitoring of the forward voltage drop of each of light sources. The system may use voltage-drop information as a temperature monitor and to improve the thermal management of the system, reducing either the worst case margins or the thermal dissipation structures.

<FIG> illustrates snooping circuitry <NUM> configured to read bit <NUM> from bit stream <NUM>, in accordance with some examples of this disclosure. <FIG> depicts bit stream <NUM> as including two hundred and fifty-six bits in a frame and eight cyclic redundancy check (CRC) bits after the end of the frame of bit stream <NUM>. In some examples, bit stream <NUM> may be received by serial interface (SI) <NUM> of <FIG>. <FIG> also depicts a clock signal with a frequency equal to the bit rate of bit stream <NUM>. <FIG> also depicts an update signal (UPD) with a high pulse at the end of the CRC bits.

In an example implementation, a user may write the pixel coordinates register (X-Y coordinates, for example) and snooping circuitry <NUM> may calculate, from these coordinates, the corresponding position of specific bit <NUM> in bit stream <NUM>. Snooping circuitry <NUM> may use the shift position to extract the light source state (i.e., specific bit <NUM>) out of bit stream <NUM>. The light source state signal going to the ADC control logic may be updated only at the end of the frame, i.e. when update signal is high, in order to have a temporal coherence with the state stored in the pixel. Additionally, in case of any transmission errors the LED state may not be updated because the state in pixel is not going to be updated.

SI <NUM> may be configured to receive the bits of bit stream <NUM> in descending order. Bit stream <NUM> may be fed into buffer circuitry <NUM> backwards so that the bit for light source <NUM> travels through the D flip-flops for all other light sources before reaching the D flip-flop for light source <NUM>. Snooping circuitry <NUM> may be configured to read specific bit <NUM>, which may correspond to a specific light source of light sources <NUM>. Snooping circuitry <NUM> may be configured to determine the position of specific bit <NUM> by receiving the LED pointer X-Y coordinates from a register. The coordinates may indicate the location of the specific light source in an array, grid, and/or matrix of light sources <NUM>. Snooping circuitry <NUM> may be configured to determine the position of specific bit <NUM> by using a map register to determine the stream position based on the row and column of the X-Y coordinates.

Snooping circuitry <NUM> may be configured to determine whether the specific light source will be on or off during the next frame based on the value of specific bit <NUM>. When snooping circuitry <NUM> receives the high pulse of the update signal, snooping circuitry <NUM> may cause the ADC control logic, such as central logic circuitry <NUM>, to determine the voltage drop across the specific light source.

<FIG> is a block diagram of snooping circuitry <NUM> and counter circuitry <NUM>, in accordance with some examples of this disclosure. The signal clk _matrix may be the serial interface clock used for the shift register, while the signal clk_update_matrix may be the clock used to load the shadow register. Device <NUM> may generate the update signal only if the frame integrity checks pass successfully. D flip-flop <NUM> may be configured to store the value of the specific bit and may be updated by the clk_update_matrix in order to keep D flip-flop <NUM> coherent with the shadow flip-flop (not shown in <FIG>) in the pixel cell.

Counter circuitry <NUM> may be configured to count a position of the specific bit as buffer circuitry receives the bit stream. Counter circuitry <NUM> may be configured to cause multiplexer <NUM> to read the specific bit in response to counting the position of the specific bit. When counter circuitry <NUM> has counted to the position of the specific bit, shift register <NUM> may deliver a high bit to multiplexer <NUM>, causing multiplexer <NUM> to deliver the specific bit to D flip-flop <NUM>. For all bits other than the specific bit, shift register <NUM> may deliver a low bit to multiplexer <NUM>, causing multiplexer <NUM> to deliver the output of D flip-flop <NUM> to the inputs of D flip-flop <NUM>. When D flip-flop <NUM> receives a pulse of the update signal (i.e., "Clk update matrix"), D flip-flop <NUM> may be configured to deliver the value of the specific bit to the ADC control logic circuitry.

<FIG> is a diagram of an algorithm implemented by counter circuitry, in accordance with some examples of this disclosure. Table <NUM> illustrates that two hundred and fifty-six light sources may be arrayed in a grid or matrix format. The number associated with each light source may count up and down the rows of table <NUM> from the leftmost column to the rightmost column. The D flip-flops of the buffer circuitry may have a similar arrangement to the arrangement of table <NUM> to allow the buffer circuitry to receive the bit stream serially.

<FIG> is a block and circuit diagram of example snooping circuitry <NUM>, in accordance with some examples of this disclosure. Snooping circuitry <NUM> may receive the value of a specific bit when counter circuitry <NUM> has counted to the position of the specific bit. XNOR gate <NUM> may receive the value of the specific bit and a requested state (i.e., Requested_led_state) as inputs. When the value of the specific bit and the requested state have the same value, XNOR gate <NUM> may output a high binary signal.

Request generation circuitry <NUM> may be configured to generate a request signal (i.e., request) that may be delivered to AND gate <NUM> as request_s. Based on the request_s and the output signal of XNOR gate <NUM>, AND gate <NUM> may be configured to output a signal to AND gate <NUM>. AND gate <NUM> may be configured to output a signal indicating a state of a specific light source.

Division <NUM> may separate the circuitry that receives clk_sys on the left side of <FIG> from the circuitry that receives clk_update, permanent clk_sci, and Clk matrix on the right side of <FIG>. Flip flops in <FIG> that are labeled clk _update may be configured to operate based on an update signal, i.e., a high pulse of an update signal. The pixel coordinates and the serial interface may run in two different clock domains. Synchronization between the clock domains may be accomplished via a request-acknowledge handshake mechanism.

Additionally, it is depicted how to handle the problem to have a selectable light source state search via the signal Requested_LED_state signal. In the previous diagram, it is depicted also how a change of pixel coordinates is handled. The signal labeled LED_state may be equal to ` <NUM>' if the light source state is correct. The circuitry may immediately set this signal to '<NUM>' when a coordinate change is done and only after a complete new correct frame is transmitted. Therefore, the circuitry of <FIG> may receive the state of the new pixel under monitor, and then the circuitry may set the light source state to '<NUM>'.

<FIG> is a timing diagram of an update signal <NUM> and other signals if a first light source is on or off, in accordance with some examples of this disclosure. A user may request a conversion on the pixel that is already selected. There are <NUM> cases: (i) the light source is already in the desired state, and the conversion starts immediately, and (ii) the light source is not in the desired state, and the monitor circuitry waits until the light source toggles and then the conversion starts. As shown in <FIG>, a high value of conversion request signal <NUM> may cause monitor circuitry to determine a voltage drop across the first light source in response to a high pulse of update signal <NUM>. The high pulse of update signal <NUM> may cause the light source state signal <NUM> to change.

Conversion request signal <NUM> may cause a high pulse in start-of-conversion signal <NUM> when light source state signal <NUM> has a high value, indicating that the first light source is on. The high pulse in start-of-conversion signal <NUM> may cause an ADC to begin converting an analog signal to converted signal <NUM>, where the analog signal indicates the voltage drop across the first light source. End-of-conversion signal <NUM> may include a high pulse at the end of the conversion by the ADC. Converted signal <NUM> may be a digital representation of the voltage drop across the first light source.

Conversion request signal <NUM> may not cause a high pulse in start-of-conversion signal <NUM> until light source state signal <NUM> has a high value, indicating that the first light source is on. The high pulse of start-of-conversion signal <NUM> may coincide with the next high pulse of update signal <NUM> after light source state signal <NUM> has a high value. End-of-conversion signal <NUM> may include a high pulse at the end of the conversion by the ADC. Converted signal <NUM> may be a digital representation of the voltage drop across the first light source.

<FIG> is a timing diagram of an update signal <NUM> and other signals if a second light source is on or off, in accordance with some examples of this disclosure. A user may request a conversion and, at the same time, select a different pixel than the pixel that is already selected. The snooping circuitry may wait for the next complete frame to update the stored light source state to the new pixel. In other words, the conversion process may begin after the second high pulse of the update signal after the user requests a conversion. There are <NUM> cases: (i) the light source is already in the desired state, and the conversion starts immediately after the second high pulse of the update signal, and (ii) the light source is not in the desired state, and the monitor circuitry waits until the light source toggles and then the conversion starts.

Pixel coordinates signal <NUM> may change if the system transmits a request for a pixel that is different than a previous pixel. The different pixel may include the second light source. The change in pixel coordinates signal <NUM> may cause conversion request signal <NUM> to change from a low value to a high value. The change in pixel coordinates signal <NUM> may also cause light source state signal <NUM> to change from a high value to a low value (i.e., an invalid state). Light source state signal <NUM> may change back from a low value to a high value after two high pulses in update signal <NUM>.

If the second light source is on, light source state signal <NUM> may cause a high pulse in start-of-conversion signal <NUM> after the settling time for an ADC, which may include a frontend operational amplifier. In some examples, the ADC may have a settling time to allow for accurate sampling of the voltage drop by the ADC. End-of-conversion signal <NUM> may include a high pulse at the end of the conversion by the ADC. Converted signal <NUM> may be a digital representation of the voltage drop across the first light source.

If the second light source is off, conversion request signal <NUM> may not cause a high pulse in start-of-conversion signal <NUM> until light source state signal <NUM> has a high value, indicating that the second light source is on. A high pulse in update signal <NUM> and a high value of light source state signal <NUM> may cause a high pulse in start-of-conversion signal <NUM> after the settling time for a frontend operational amplifier. End-of-conversion signal <NUM> may include a high pulse at the end of the conversion by the ADC. Converted signal <NUM> may be a digital representation of the voltage drop across the first light source.

<FIG> and <FIG> are flowcharts illustrating example techniques for determining a voltage drop across a light source, in accordance with some examples of this disclosure. The techniques of <FIG> and <FIG> are described with reference to device <NUM> in <FIG>, although other components, such as semiconductor device <NUM> in <FIG> and snooping circuitry <NUM> in <FIG>, may exemplify similar techniques.

The techniques of <FIG> include buffer circuitry <NUM> receiving bit stream <NUM> (<NUM>). Buffer circuitry <NUM> may include a shift register configured to receive a frame of bit stream <NUM>. Each flip flop of the shift register may be configured to receive each bit of the frame of bit stream <NUM>. When buffer circuitry <NUM> has received the frame of bit stream <NUM>, buffer circuitry <NUM> may be configured to receive an update signal indicating the end of the frame. The update signal may also indicate that the frame does not include any errors. In response to receiving the update signal, buffer circuitry <NUM> may be configured to deliver the frame of bit stream <NUM> to driver circuitry <NUM>.

The techniques of <FIG> further include snooping circuitry <NUM> reading, while buffer circuitry <NUM> receives bit stream <NUM>, specific bit <NUM> of bit stream <NUM> (<NUM>). Snooping circuitry <NUM> may include counter circuitry configured to count the position of specific bit <NUM> in a frame of bit stream <NUM> as buffer circuitry <NUM> receives the frame. The counter circuitry may be configured to cause snooping circuitry <NUM> to read the value of specific bit <NUM> in response to counting the position of specific bit <NUM>. In some examples, snooping circuitry <NUM> may be configured to read specific bit <NUM> as buffer circuitry <NUM> receives specific bit <NUM>.

The techniques of <FIG> further include driver circuitry <NUM> driving light sources <NUM> based on bit stream <NUM> (<NUM>). Driver circuitry <NUM> may be configured to receive the frame of bit stream <NUM> in response to buffer circuitry <NUM> receiving the update signal. In some examples, driver circuitry <NUM> may be configured to deliver an electrical current to a light source based on a high value of a corresponding bit in bit stream <NUM>. Driver circuitry <NUM> may be configured to refrain from delivering an electrical current to a light source based on a low value of a corresponding bit in bit stream <NUM>.

The techniques of <FIG> further include monitor circuitry <NUM> determining a voltage drop across a specific light source of light sources <NUM> based on a value of specific bit <NUM> (<NUM>). Snooping circuitry <NUM> may be configured to compare the value of specific bit <NUM> to a requested state and cause monitor circuitry <NUM> to determine the voltage drop if the value of specific bit <NUM> and the requested state are equal. Snooping circuitry may include logic gates configured to compare the value of specific bit <NUM> and the requested state (e.g., snooping circuitry <NUM> in <FIG>). Monitor circuitry <NUM> may be configured to receive a voltage signal from driver circuitry <NUM>, where the voltage signal indicates the voltage drop across the specific light source (e.g., light source <NUM> and switch <NUM> in <FIG>). Monitor circuitry <NUM> may include multiplexers that are configured to deliver the voltage signal from driver circuitry <NUM> to an ADC (e.g., multiplexers <NUM> and <NUM> in <FIG>).

By reading the value of specific bit <NUM> as buffer circuitry <NUM> receives a frame of bit stream <NUM>, snooping circuitry <NUM> may be configured to synchronize monitor circuitry <NUM> to determine the voltage drop. Snooping circuitry <NUM> may be configured to cause monitor circuitry <NUM> to determine the voltage drop in response to receiving an update signal, rather than waiting until after the update signal to determine the value of specific bit <NUM> or to determine whether the specific light source is on or off.

Other devices may include an external ADC, where the monitoring of the forward voltage (i.e., the voltage drop) may be implemented by multiplexing the output current source voltage of the driver circuitry to a pad in order to be sampled by an external ADC. Synchronization of the external ADC with the desired light source state may require that the external PWM/PDM/PFM generator be configured to trigger the state of conversion that must include the latency of the transmission and light source state update. An antialiasing filter (e.g., a low-pass filter) may be present at the external ADC inputs. A possible drawback is that the minimum on-state that can be monitored may be limited. Such a scheme may become more difficult to support when several voltages must be monitored. For example, there are four voltages per device and there may be three or four devices per system, meaning that as many as sixteen voltages are being sampled. Additionally, it may be difficult to account for transmission errors that cause the transmitted data to be rejected causing a mismatch of the light source state in the PWM/PDM/PFM generator and real one in the device.

Additionally or alternatively, another device may include an internal ADC. If the light source state information is stored locally in the pixel area and not available in the common circuitry where the ADC control logic is placed, a wire may run from each pixel down to the common circuitry, which may cause routing congestion issues in the already limited routing channel. The congestion may increase as the size of each light source decreases. It may consume area to have state information stored locally in the pixel area and a replica stored in the common area because a doubling of the memory elements is needed, resulting in a bigger area overhead. As the number of light sources in a device increases, the footprint of such a device may also increase. To have state information stored in the common area and then pixel cell driven by dedicated wire may result in routing congestion issue and bigger area overhead. It may also be difficult to provide a start of conversion signal for such a device.

A device of this disclosure may synchronize an internal ADC to the on-the-fly changing light source status. The device may monitor the incoming data stream and extract a specific bit corresponding to the specific light source under diagnosis. This way the ADC control logic has continuously the correct information about the actual light source status and it can trigger an ADC conversion in the right moment. In the event of a transmission error for the bit stream, the light source state may be not updated. If the specific light source changes state during the conversion the ADC controller may abort the conversion and either execute a retry or issue an error to the system possibly indicating that the duty cycle is too small. The device may include a small number of logic gates, which may be an advantage in the terms of area compared to other devices. Additionally, the device may not include wires in the matrix area of the light sources without much impact on matrix route-ability.

The techniques of <FIG> include controller circuitry <NUM>, monitor circuitry <NUM>, and/or snooping circuitry <NUM> selecting a specific light source of light sources <NUM> (<NUM>). In some examples, device <NUM> may be configured to select the next light source based on the positions of the light sources. For example, device <NUM> may select light source n, followed by light source n+<NUM>, followed by light source n+<NUM>, etc. The techniques of <FIG> further include controller circuitry <NUM>, monitor circuitry <NUM>, and/or snooping circuitry <NUM> determining a position of specific bit <NUM> based on a position of the specific light source (<NUM>). Device <NUM> may include mapping circuitry configured to convert the position of the specific light source to the position of specific bit <NUM>, or vice versa. The mapping circuitry may include a lookup table matching the X-Y coordinates of light sources <NUM> and positions of bits in bit stream <NUM>.

The techniques of <FIG> further include buffer circuitry <NUM> beginning to receive bit stream <NUM> that includes specific bit <NUM> (<NUM>). The techniques of <FIG> further include snooping circuitry <NUM> and/or counter circuitry counting through bit stream <NUM> to the position of specific bit <NUM> (<NUM>). The counter circuitry may be configured to clear the count in response to receiving an update signal and to being counting at the start of each frame. When the counter circuitry reaches the position of specific bit <NUM>, the techniques of <FIG> further include snooping circuitry <NUM> reading and storing specific bit <NUM> (<NUM>). Snooping circuitry <NUM> may include a multiplexer configured to receive bit stream <NUM> as an input and to output only the value of specific bit <NUM>. In some examples, snooping circuitry <NUM> may be configured to store the value of specific bit <NUM> in a flip flop.

The techniques of <FIG> further include buffer circuitry <NUM> and/or snooping circuitry <NUM> receiving an update signal, such as an active period and/or high pulse of the update signal (<NUM>). When buffer circuitry <NUM> receives the update signal, buffer circuitry <NUM> may be configured to deliver a frame of bit stream <NUM> to driver circuitry <NUM>. When snooping circuitry <NUM> receives the update signal, snooping circuitry <NUM> may be configured to cause monitor circuitry <NUM> to determine the voltage drop across the specific light source. The techniques of <FIG> further include driver circuitry <NUM> driving light sources <NUM> based on bit stream <NUM> (<NUM>). The techniques of <FIG> further include monitor circuitry <NUM> determining the voltage drop across the specific light source (<NUM>). After monitor circuitry <NUM> determines the voltage drop, controller circuitry <NUM>, monitor circuitry <NUM>, and/or snooping circuitry <NUM> may select another light source of light sources <NUM> for measuring the voltage drop (<NUM>).

The techniques of this disclosure may be implemented in a device or article of manufacture comprising a computer-readable storage medium. The term "processing circuitry," as used herein may refer to any of the foregoing structure or any other structure suitable for processing program code and/or data or otherwise implementing the techniques described herein. Elements of device <NUM>, buffer circuitry <NUM>, driver circuitry <NUM>, monitor circuitry <NUM>, snooping circuitry <NUM>, and/or controller circuitry <NUM> may be implemented in any of a variety of types of solid state circuit elements, such as CPUs, CPU cores, GPUs, digital signal processors (DSPs), application-specific integrated circuits (ASICs), a mixed-signal integrated circuits, field programmable gate arrays (FPGAs), microcontrollers, programmable logic controllers (PLCs), programmable logic device (PLDs), complex PLDs (CPLDs), a system on a chip (SoC), any subsection of any of the above, an interconnected or distributed combination of any of the above, or any other integrated or discrete logic circuitry, or any other type of component or one or more components capable of being configured in accordance with any of the examples disclosed herein. Processing circuitry may also include analog components arranged in a mixed-signal IC.

Device <NUM>, buffer circuitry <NUM>, driver circuitry <NUM>, monitor circuitry <NUM>, snooping circuitry <NUM>, and/or controller circuitry <NUM> may include memory. One or more memory devices of the memory may include any volatile or non-volatile media, such as a RAM, ROM, non-volatile RAM (NVRAM), electrically erasable programmable ROM (EEPROM), flash memory, and the like. One or more memory devices of the memory may store computer readable instructions that, when executed by the processing circuitry, cause the processing circuitry to implement the techniques attributed herein to the processing circuitry.

Elements of device <NUM>, buffer circuitry <NUM>, driver circuitry <NUM>, monitor circuitry <NUM>, snooping circuitry <NUM>, and/or controller circuitry <NUM> may be programmed with various forms of software. The processing circuitry may be implemented at least in part as, or include, one or more executable applications, application modules, libraries, classes, methods, objects, routines, subroutines, firmware, and/or embedded code, for example. The processing circuitry may be configured to receive voltage signals, determine switching frequencies, and deliver control signals.

Claim 1:
A device (<NUM>) comprising:
light sources (<NUM>), arrayed in a matrix of light sources, wherein each light source is a respective pixel;
a buffer circuitry (<NUM>) configured to receive a bit stream (<NUM>), wherein the bit stream (<NUM>) has at least a first frame and a next frame that follows the first frame;
a driver circuitry (<NUM>) configured to:
receive the first frame of the bit stream (<NUM>) from the buffer circuitry (<NUM>), while the buffer circuitry (<NUM>) receives the next frame; and
drive each of the light sources (<NUM>) based on a bit value of a respective bit of a respective frame of the at least first frame and the next frame of the bit stream (<NUM>);
a monitor circuitry (<NUM>) configured to determine a voltage drop (<NUM>) across each light source of the light sources (<NUM>);
characterized by
a snooping circuitry (<NUM>) configured to:
receive pixel coordinates from a register indicating a location of a specific light source in the matrix;
determine, by using a map register, a position of a specific bit in the first frame of the bit stream based on the received pixel coordinates, wherein the specific bit corresponds to the specific light source in the matrix;
read, as the buffer circuitry (<NUM>) receives the first frame of the bit stream (<NUM>), the specific bit (<NUM>) of the first frame of the bit stream (<NUM>) based on the determined position of the specific bit,
wherein the bit value of the specific bit (<NUM>) of the first frame indicates whether the driver circuitry (<NUM>) will drive the specific light source of the light sources (<NUM>) as the buffer circuitry (<NUM>) is receiving the next frame; and
cause the monitor circuitry (<NUM>) to determine a voltage drop (<NUM>) across the specific light source based on the read value of the specific bit (<NUM>) while the driver circuitry (<NUM>) is driving the specific light source based on the specific bit of the first frame.