Patent Description:
In digitally controlled DC to DC converters it may be desirable to provide a variable current limitation, sometimes known in the art as CC (constant current) mode, in order to limit the input or output current, and thereby protect the converter and/or load from over-currents.

However, there is a difficulty in providing a simple, low cost solution for implementing a steady state current limitation mechanism.

<CIT> relates to over-shoot recovery including overshoot suppression.

According to one aspect, there is provided a method of limiting an input or output current of a DC to DC converter as defined by the appended claims.

According to a further aspect, there is provided a current limiting circuit as defined by the appended claims.

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the particular circuit implementation of a buck, boost or buck-boost DC-DC converter has not been described, such circuits being well known to those skilled in the art.

Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements linked or coupled together, this signifies that these two elements can be connected or they can be linked or coupled via one or more other elements.

Unless specified otherwise, the expressions "around", "approximately", "substantially" and "in the order of" signify within <NUM> %, and preferably within <NUM> %.

<FIG> schematically illustrates an example of a circuit <NUM> comprising a DC-DC voltage converter (DC-DC CONVERTER) <NUM>. The DC-DC converter <NUM> receives an input voltage Vin and generates an output voltage Vout supplying a load (LOAD) <NUM> coupled to ground. The DC-DC converter <NUM> includes an over-current detector (OVER-CURRENT DETECTOR) <NUM> for detecting an over-current of the input current Iin and/or of the output current Iout of the converter <NUM>.

<FIG> schematically illustrates the over-current detector <NUM> of <FIG> in more detail according to one example.

In the example of <FIG>, the over-current detector <NUM> comprises an input receiving a current signal I indicating the current level at the input or output of the converter <NUM>. This current signal I is for example filtered by a low pass filter (LPF) <NUM> to generate a filtered signal Ifi, which is in turn for example provided to the positive input of a comparator (CMP) <NUM>. The negative input of the comparator <NUM> receives a current threshold Ith. When this current threshold Ith is exceeded by the filtered signal Ifi, the comparator <NUM> asserts an output signal LIMIT.

The current Iin at the input or Iout at the output of the converter <NUM> varies during charge and discharge phases of each cycle of the DC-DC converter, depending on the conversion mode, such as whether in buck, boost or buck-boost mode. However, the aim of the over-current detector <NUM> is not to avoid these high frequency fluctuations, but to limit the average current. Therefore, the low pass filter <NUM> permits such an average current level to be extracted. However, such an arrangement can lead to undesirable oscillation of the output voltage Vout of the converter <NUM>, as will now be described in more detail with reference to <FIG>.

<FIG> is a timing diagram illustrating an example of the signals I, Ifi and LIMIT in the over-current detector <NUM> of <FIG>, and the voltage Vout of the converter <NUM> of <FIG>. It is assumed that the current I is initially rising.

When the filtered current signal Ifi exceeds the current threshold Ith, the signal LIMIT goes high. In order to reduce the input or output current Iin, Iout of the converter <NUM>, the output voltage Vout is reduced in a linear manner. The current I therefore starts to fall. However, because of the low pass filter <NUM>, the signal Ifi only starts to fall after a delay td introduced by this filter <NUM>. Once the signal Ifi returns below the threshold Ith, the signal LIMIT falls low, and the voltage Vout is increased again, but due to the delay td, the voltage Vout falls lower than necessary.

Similarly, when the filtered current signal Ifi next exceeds the current threshold Ith, a similar situation occurs in which the output voltage Vout rises higher than necessary in view of the delay td of the low pass filter.

These oscillations of the output voltage Vout continue and are undesirable.

One solution to the problem highlighted in <FIG> would be to introduce a slow variation of the output voltage Vout, and in particular a response time that is slower than the delay td of the low pass filter. However, such a slow response time is unacceptable in some applications as it can risk the current exceeding desired limits before the appropriate correction is applied.

Another solution to the problem highlighted in <FIG> would be to introduce a PID (proportional, integral, differential) control to the output voltage, but such a solution would be complex, most likely including an analog to digital converter, and would require precise tuning of the PID parameter.

<FIG> is a timing diagram illustrating a further example of signals in the circuit of <FIG>. <FIG> shows the same signals as those shown in <FIG>. Furthermore, <FIG> represents voltage limits Vmax and Vmin associated with the peaks and troughs of the output voltage Vout during the undesired oscillation. Indeed, the present inventor has noted that generally, in view of the fixed time delay td of the low pass filter, the output voltage Vout will reach a maximum voltage level Vmax when the signal LIMIT at the output of the comparator toggles high, and will reach a minimum voltage level Vmin when the signal LIMIT toggles low, these levels being respectively above and below an optimum intermediate level of the output voltage Vout. As will now be described with reference to <FIG>, a current limitation mechanism of the present disclosure is based on the value of Vmax or of a signal representative of the level of Vmax, and/or based on the value of Vmin or of a signal representative of the level of Vmin.

<FIG> schematically illustrates a DC-DC converter <NUM> with a steady state current limitation mechanism according to an example embodiment of the present disclosure.

The DC-DC converter <NUM> comprises a converting circuit (CONVERTER) <NUM>, which is for example a buck, boost or buck-boost converter. This circuit <NUM> receives an input voltage Vin on an input line and generates an output voltage Vout on an output line. The converting circuit <NUM> receives a control signal CTRL' for controlling the level of the output voltage Vout. For example, this control signal CTRL' is in the form of a digital control signal that controls the duration of a charge and/or discharge phase of the converter <NUM>.

A feedback control circuit (FEEDBACK CONTROL) <NUM> for example receives the output voltage Vout and a reference voltage Vref and generates a digital control signal CTRL suitable for bringing the output voltage Vout towards a target level indicated by the voltage reference Vref. A controller (CONTROLLER) <NUM> for example receives the control signal CTRL and generates the control signal CTRL' to the converter <NUM>. The controller <NUM> also for example receives the signal LIMIT from an over-current detector, which in the example of <FIG> is implemented by the circuit <NUM> of <FIG> and will not be described again in detail. The current signal I at the input of the over-current detector <NUM> for example represents the input current Iin of the converter <NUM> and/or the output current Iout of the converter <NUM>. For example, the current signal I is a voltage measured across a resistor placed in the input or output path of the converter <NUM>, although other implementations would be possible. In some embodiments, the over-current detector <NUM> is duplicated, one of the detectors <NUM> receiving a current signal I representing the current Iin at the input of the converter <NUM>, and the other detector <NUM> receiving a current signal I representing the current Iout at the output of the converter <NUM>. In such an embodiment the output signals LIMIT from the two detectors <NUM> can be combined by an OR gate in order to detect an over-current occurring at either or both of the input and output of the converter <NUM>.

Operation of the circuit of <FIG> will now be described in more detail with reference to <FIG>.

<FIG> is a flow diagram illustrating operations in a method of limiting the current at the input and/or output of a DC-DC converter according to an example embodiment of the present disclosure. The method of <FIG> is for example implemented by the controller <NUM> of <FIG>, and for example by a state machine implemented within the controller <NUM>.

In an operation <NUM>, parameters VMAX and VMIN are for example set to a value representing the current level of the output voltage Vout, for example by setting these parameters to a current level of the control signal CTRL'.

In an operation <NUM>, it is determined whether an over-current has been detected at the input or output of the DC to DC converter. For example, the over-current detector <NUM> or a similar circuit is used to generate a signal, such as the signal LIMIT of <FIG>, indicating when the input and/or output current exceeds the threshold Ith.

If in operation <NUM> no over-current was detected, the next operation is an operation <NUM>, in which it is determined whether the output voltage Vout of the converter is equal to the target voltage Vref, for example based on whether the control signal CTRL generated by the feedback control circuit <NUM> is equal to the current level of the control signal CTRL'. If so, the method for example returns to operation <NUM>. If, however, the output voltage Vout is not equal to the target voltage Vref, in an operation <NUM>, the control signal CTRL' is for example modified by the controller <NUM> to step up the output voltage Vout of the converter. Then, in an operation <NUM>, it is again determined whether an over-current is detected, and if not, the operations <NUM> and <NUM> are repeated. When, in operation <NUM>, the over-current is detected, the next operation is an operation <NUM>, in which the parameter VMAX is set by the controller <NUM> to a value representing the voltage Vout. For example, the parameter VMAX is set to the current value of the control signal CTRL', as will now be described with reference to <FIG>.

<FIG> is a timing diagram illustrating an example of signals I, Ifi, LIMIT and Vout in the circuit of <FIG>. When the signal LIMIT is asserted following a period in which the output voltage Vout is increasing, the output voltage Vout has reached a level Vmax, and a value representative of this level is stored as the parameter VMAX.

Referring again to <FIG>, if an over-current is detected in operation <NUM>, the controller <NUM> for example modifies the control signal CTRL', in an operation <NUM>, in order to step down the output voltage Vout of the converter. Then, in an operation <NUM>, it is again determined whether an over-current is detected, and if so, the operations <NUM> and <NUM> are repeated. When, in operation <NUM>, the over-current is no longer detected, the parameter VMIN is set by the controller <NUM>, in an operation <NUM>, to a value representing the voltage Vout. For example, the parameter VMIN is set to the current value of the control signal CTRL', as will now be described with reference again to <FIG>.

As shown in <FIG>, when the signal LIMIT falls low following a period in which the output voltage Vout is decreasing, the output voltage Vout has reached a level Vmin, and a value representative of this level is stored as the parameter VMIN.

After operations <NUM> and <NUM>, in an operation <NUM>, the control signal CTRL' is set to a value so that Vout will be between the minimum and maximum voltages Vmin and Vmax. In some embodiments, the control signal CTRL' is set to a midpoint between the values of the parameters VMAX and VMIN.

For example, with reference to <FIG>, when the current Ifi falls below the threshold Ith and the signal LIMIT falls low, the output voltage is at the level Vmin, and the control signal CTRL' is modified in order to bring the voltage Vout to an intermediate value Vint equal to (Vmax+Vmin)/<NUM>, or to another intermediate voltage between Vmin and Vmax. For example, this is achieved by applying a new control signal CTRL' equal to an intermediate value between the values of the parameters VMIN and VMAX.

With reference again to <FIG>, after operation <NUM>, an operation <NUM> is for example performed in which the method waits for a time delay equal, for example, to at least the propagation delay of the low pass filter <NUM> of the over-current detector <NUM>, and then the method returns to operation <NUM>.

In some embodiments, an iterative process can be applied by the controller <NUM> to determine a higher level of the output voltage Vout that can be obtained without causing an over-current, as will now be described with reference to <FIG>.

<FIG> is a timing diagram illustrating a further example of the same signals as those of <FIG>. However, in the example of <FIG>, the intermediate voltage Vint is maintained for a fixed time duration DELAY, which is for example longer than the time delay td introduced by the low pass filter. The control signal CTRL' is then for example modified in order to increase again the output voltage Vout, which again causes the current threshold Ith to be exceeded. However, in view of the time delay DELAY, the new maximum voltage level reached by the output voltage Vout is a level Vmax_new, which is lower than Vmax. The control signal CTRL' is then for example modified to a level to bring the output voltage to a level Vmin_new corresponding to a mid-point between the voltages Vmin and Vmax_new. Then, when signal LIMIT toggles again to a low level, the control signal CTRL' is for example modified to bring the output voltage Vout to a new intermediate level Vint', corresponding for example to a mid-point between the levels Vmax_new and Vmin_new.

An advantage of the embodiments described herein is that a steady state current limiting mechanism is implemented with relatively low complexity, and for example without the use of any analog to digital conversion.

Claim 1:
A method of limiting an input or output current (Iin, Iout) of a DC to DC converter controlled by a control signal (CTRL'), the control signal controlling the level of an output voltage of the DC to DC converter, the method comprising:
- setting first and second values (VMAX, VMIN) to a value representing a current level of the output voltage;
- in response to the input or output current (Iin, Iout) exceeding a first threshold (Ith), modifying the control signal (CTRL') in order to step down the output voltage of the converter until the input or output current (Iin, Iout) no longer exceeds the first threshold (Ith), and storing as the first value the value of the control signal (CTRL') when the input or output current (Iin, Iout) exceeded the first threshold (Ith), the first value being representative of the level of the output voltage (Vout) of the DC to DC converter, and in response to the input or output current (Iin, Iout) falling below the first threshold (Ith) or a further threshold, modifying the control signal (CTRL') in order to step up the output voltage of the converter until the input or output current (Iin, Iout) exceeds the first threshold (Ith) or further threshold, and storing as the second value the value of the control signal (CTRL') when the input or output current (Iin, Iout) fell below the first or further threshold, the second value being representative of the level of the output voltage (Vout); and
- modifying the control signal (CTRL') to a value between the first and second values (VMAX, VMIN) to bring the output voltage (Vout) to an intermediate voltage level (Vint) between the level of the output voltage (Vout) represented by the first value and the level of the output voltage (Vout) represented by the second value.