Patent Description:
Semiconductor packages are being developed to efficiently fabricate semiconductor chips having more diverse functions and high reliability. In addition, in order to mount more semiconductor chips in the same area, a stacked semiconductor package in which a plurality of semiconductor chips are stacked has been proposed. For example, a package-in-package (PIP) type semiconductor package or a package-on-package (POP) type semiconductor package may be used.

On the other hand, when many semiconductor chips are mounted in one semiconductor package in this way, defects such as void traps may occur during a molding process of the semiconductor package.

Accordingly, research into a technology capable of preventing unfilled molding members and occurrence of void trap defects during a molding process for the semiconductor package in which many semiconductor chips are mounted is being conducted.

<CIT> discloses an apparatus relating generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.

<CIT> discloses a microelectronic assembly including a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

The invention is defined in the appended independent claims. Further developments of the invention are specified in the dependent claims.

Some example embodiments of the present disclosure provide semiconductor packages with improved product reliability.

Some example embodiments of the present disclosure also provide methods of fabricating a semiconductor package with improved product reliability.

However, example embodiments of the present disclosure are not restricted to those set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an example embodiment of the present disclosure, a semiconductor package includes a first package substrate including a first area, a first semiconductor chip on the first area, a second package substrate on an upper surface of the first semiconductor chip, the second package substrate including a second area and a first hole penetrating through the second area, a second semiconductor chip on the second area, a connection member electrically connecting the first package substrate and the second package substrate, a connection member being between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.

According to an example embodiment of the present disclosure, a semiconductor package includes a first package substrate, an upper pad exposed from an upper surface of the first package substrate, a first semiconductor chip on the upper surface of the first package substrate, a second package substrate on an upper surface of the first semiconductor chip and spaced apart from the upper surface of the first semiconductor chip, a lower pad exposed from a lower surface of the second package substrate, a second semiconductor chip on an upper surface of the second package substrate, a connection member electrically connecting the first package substrate and the second package substrate, the connection member being in direct contact with the upper pad and the lower pad, and a mold film covering the first semiconductor chip and the connection member on the first package substrate and covering the second semiconductor chip on the second package substrate, wherein the first package substrate includes a first hole penetrating through the first package substrate in a first direction, the second package substrate includes a second hole penetrating through the second package substrate in the first direction, the first hole overlaps the first semiconductor chip in plan view, and the second hole overlaps the second semiconductor chip in plan view.

According to an example embodiment of the present disclosure, a method of fabricating a semiconductor package includes forming a first hole penetrating through a first package substrate in a first direction, mounting a first semiconductor chip on an upper surface of the first package substrate so as to overlap the first hole in plan view, forming a connection member on the upper surface of the first package substrate, forming a second hole penetrating through a second package substrate in the first direction, disposing the second package substrate on an upper surface of the first semiconductor chip so that an upper end of the connection member is in direct contact with a lower pad exposed from a lower surface of the second package substrate, mounting a second semiconductor chip on an upper surface of the second package substrate so as to overlap the second hole in plan view, and forming a mold film covering the first semiconductor chip and the connection member on the first package substrate and covering the second semiconductor chip on the second package substrate.

It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description.

The above and other aspects and features of the present disclosure will become more apparent by describing in detail some example embodiments thereof with reference to the attached drawings, in which:.

Hereinafter, semiconductor packages and/or methods of fabricating the same according to some example embodiments will be described with reference to the accompanying drawings.

Thus, for example, both "at least one of A, B, or C" and "at least one of A, B, and C" mean either A, B, C or any combination thereof. Likewise, A and/or B means A, B, or A and B.

<FIG> is an illustrative plan view for describing a semiconductor package according to an example embodiment. <FIG> is an illustrative cross-sectional view for describing a semiconductor package according to an example embodiment. <FIG> is an enlarged view for describing area B of <FIG>. Hereinafter, a semiconductor package according to some example embodiments will be described with reference to <FIG>.

First, referring to <FIG> and <FIG> together, a semiconductor package according to some example embodiments may include a first package substrate <NUM>, a first semiconductor chip <NUM>, a second package substrate <NUM>, a second semiconductor chip <NUM>, a connection member 300A, and a mold film <NUM>.

The first package substrate <NUM> may be a substrate for a package. For example, the first package substrate <NUM> may be a printed circuit board (PCB) or a ceramic substrate. In some example embodiments, the first package substrate <NUM> may also be a substrate for a wafer level package (WLP) manufactured at a wafer level. The first package substrate <NUM> may have a single layer or multiple layers. The first package substrate <NUM> may include a lower surface and an upper surface that are opposite to each other in a first direction Z. In the following description, lower and upper surfaces of components (e.g., the first package substrate <NUM> and the first semiconductor chip <NUM>) included in the semiconductor package may be based on the first direction Z.

The first package substrate <NUM> may include a first lower pad <NUM>, an upper pad <NUM>, a first chip pad <NUM>, and a first wiring pattern <NUM>. The first lower pad <NUM> may be exposed from the lower surface of the first package substrate <NUM>. Each of the upper pad <NUM> and the first chip pad <NUM> may be exposed from the upper surface of the first package substrate <NUM>. Each of the first lower pad <NUM>, the upper pad <NUM>, and the first chip pad <NUM> may include, at least one of, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), gold (Au), and a combination thereof, but is not limited thereto.

Each of the first lower pad <NUM>, the upper pad <NUM>, and the first chip pad <NUM> may be connected to the first wiring pattern <NUM>, which is an electrical circuit formed in the first package substrate <NUM>. That is, each of the first lower pad <NUM>, the upper pad <NUM>, and the first chip pad <NUM> is a portion (pattern or pad) to which the first wiring pattern <NUM> of the first package substrate <NUM> is connected to the outside.

In some example embodiments, a connection terminal <NUM> may be formed on the lower surface of the first package substrate <NUM>. The connection terminal <NUM> may be used to electrically connect the first package substrate <NUM> and an external device. For example, the connection terminal <NUM> may be in contact with the first lower pad <NUM> of the first package substrate <NUM>. Accordingly, the connection terminal <NUM> may provide an electrical signal from the external device to the first package substrate <NUM> or may provide an electrical signal from the first package substrate <NUM> to an external device.

The connection terminal <NUM> may be, for example, a spherical, hemispherical, or elliptical bump, a solder ball, or under bump metallurgy (UBM), but is not limited thereto. The connection terminal <NUM> may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or a combination thereof, but is not limited thereto.

The first semiconductor chip <NUM> may be mounted on the first package substrate <NUM>. As an example, the first semiconductor chip <NUM> may be mounted on the upper surface of the first package substrate <NUM>. It is illustrated in <FIG> that only two first semiconductor chips <NUM> are mounted on the upper surface of the first package substrate <NUM> and horizontally arranged on the upper surface of the first package substrate <NUM> in a second direction X, but the exemplary embodiments are not limited thereto. For example, in some example embodiments, only one first semiconductor chip <NUM> may be mounted on the upper surface of the first package substrate <NUM>. In some other example embodiments, three or more first semiconductor chips <NUM> may be disposed on the first package substrate <NUM> and/or horizontally arranged in the second direction X and/or the third direction Y. In addition, in some example embodiments, two or more first semiconductor chips <NUM> may also be sequentially stacked on the first package substrate <NUM>.

The first semiconductor chip <NUM> may be an integrated circuit (IC) in which hundreds to millions of semiconductor elements are integrated into a single chip. For example, the first semiconductor chip <NUM> may be memory chips such as volatile memory (e.g., DRAM) or non-volatile memory (e.g., ROM or flash memory), application Processor (AP) chips such as Central Processing Unit (CPU), Graphic Processing Unit (GPU), Field-Programmable Gate Array (FPGA), digital signal processor, encryption processor, microprocessor, or microcontroller, and logic chips such as analog-digital converters (ADCs) or application-specific ICs (ASICs), but is not limited thereto. In addition, the first semiconductor chip <NUM> may also be configured by combining the above-mentioned elements.

In some example embodiments, a first chip bump group <NUM> may be formed between the first package substrate <NUM> and the first semiconductor chip <NUM>. For example, the first chip bump group <NUM> may be formed between the upper surface of the first package substrate <NUM> and the lower surface of the first semiconductor chip <NUM>. The first chip bump group <NUM> may include a plurality of bumps. The first chip bump group <NUM> may electrically connect the first package substrate <NUM> and the first semiconductor chip <NUM>. For example, the first semiconductor chip <NUM> may be mounted on the first package substrate <NUM> by a flip chip bonding method.

For example, each of the plurality of bumps included in the first chip bump group <NUM> may include a first pillar layer <NUM> and a first solder layer <NUM>. The first pillar layer <NUM> may be a post-shaped structure protruding from the lower surface of the first semiconductor chip <NUM>. In addition, the first pillar layer <NUM> may be electrically connected to the first semiconductor chip <NUM>. The first pillar layer <NUM> may include, for example, copper (Cu), a copper alloy, nickel (Ni), a nickel alloy, palladium (Pd), platinum (Pt), gold (Au), cobalt (Co), or a combination thereof, but is not limited thereto.

The first solder layer <NUM> may electrically connect the first pillar layer <NUM> and the first package substrate <NUM> to each other. For example, the first solder layer <NUM> may be in contact with the first chip pad <NUM> of the first package substrate <NUM>. The first solder layer <NUM> may have, for example, a spherical, hemispherical, or ellipsoidal structure. The first solder layer <NUM> may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or a combination thereof, but is not limited thereto.

The second package substrate <NUM> may be disposed on the upper surface of the first semiconductor chip <NUM>. The second package substrate <NUM> may include a lower surface and an upper surface that are opposite to each other in a first direction Z. The upper surface of the first semiconductor chip <NUM> and the lower surface of the second package substrate <NUM> may be spaced apart from each other in the first direction Z perpendicular to the upper surface of the first semiconductor chip <NUM>. The second package substrate <NUM> may be a substrate for a package. For example, the second package substrate <NUM> may be a printed circuit board (PCB) or a ceramic substrate. In some example embodiments, the second package substrate <NUM> may be a substrate for a wafer level package (WLP) manufactured at a wafer level. The second package substrate <NUM> may have a single layer or multiple layers. In some other example embodiments, the second package substrate <NUM> may be an interposer.

The second package substrate <NUM> may include a second lower pad <NUM>, a second chip pad <NUM>, and a second wiring pattern <NUM>. The second lower pad <NUM> may be exposed from the lower surface of the second package substrate <NUM>. The second chip pad <NUM> may be exposed from the upper surface of the second package substrate <NUM>. Each of the second lower pad <NUM> and the second chip pad <NUM> may include, at least one of, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), gold (Au), or a combination thereof, but is not limited thereto.

Each of the second lower pad <NUM> and the second chip pad <NUM> may be connected to the second wiring pattern <NUM>, which is an electrical circuit formed in the second package substrate <NUM>. That is, each of the second lower pad <NUM> and the second chip pad <NUM> is a portion (pattern or pad) to which the second wiring pattern <NUM> of the second package substrate <NUM> is connected to the outside.

The second semiconductor chip <NUM> may be mounted on the second package substrate <NUM>. As an example, the second semiconductor chip <NUM> may be mounted on the upper surface of the second package substrate <NUM>. For example, the second semiconductor chip <NUM> may be mounted on a second area A2 of the upper surface of the second package substrate <NUM>. The second area A2 may be an area of the upper surface of the second package substrate <NUM> overlapping the second semiconductor chip <NUM> in a vertical view (e.g., in the first direction Z perpendicular to the upper surface of the second package substrate <NUM>).

It is illustrated in <FIG> and <FIG> that only two second semiconductor chips <NUM> are mounted on the upper surface of the second package substrate <NUM> and horizontally arranged in the second direction X, but example embodiments are not limited thereto. For example, in some example embodiments, only one second semiconductor chip <NUM> may be mounted on the upper surface of the second package substrate <NUM>. In some other example embodiments, three or more second semiconductor chips <NUM> may be disposed on the second package substrate <NUM> and horizontally arranged in the second direction X and/or the third direction Y. In addition, in some example embodiments, two or more second semiconductor chips <NUM> may be sequentially stacked on the second package substrate <NUM>.

The second semiconductor chip <NUM> may be an integrated circuit (IC) in which hundreds to millions of semiconductor elements are integrated into a single chip. For example, the second semiconductor chip <NUM> may be memory chips such as volatile memory (e.g., DRAM) or non-volatile memory (e.g., ROM or flash memory), application Processor (AP) chips such as Central Processing Unit (CPU), Graphic Processing Unit (GPU), Field-Programmable Gate Array (FPGA), digital signal processor, encryption processor, microprocessor, or microcontroller, and logic chips such as analog-digital converters (ADCs) or application-specific ICs (ASICs), but is not limited thereto. In addition, the second semiconductor chip <NUM> may also be configured by combining the above-mentioned elements. In some example embodiments, both the first semiconductor chip <NUM> and the second semiconductor chip <NUM> may be volatile memories (e.g., DRAM).

In some example embodiments, as illustrated in <FIG> and <FIG>, a second hole <NUM> penetrating through the second package substrate <NUM> in the first direction Z may be formed in the second package substrate <NUM>. For example, referring to <FIG>, a length (e.g., depth) D3 of the second hole <NUM> in the first direction Z may be the same as a length (e.g., depth) of the second package substrate <NUM> in the first direction Z. The second hole <NUM> may be formed to penetrate through the second area A2 on the second package substrate <NUM>. For example, the second hole <NUM> may be formed to penetrate through a portion of an area A2 on the upper surface of the second package substrate overlapping the second semiconductor chip <NUM> in the vertical view. For example, the second hole <NUM> may be provided at a center or central part of an area A2 on the upper surface of the second package substrate overlapping the second semiconductor chip <NUM> in the vertical view. The second hole <NUM> may have a rectangular shape in plan view as illustrated in <FIG>, but example embodiment is not limited thereto. The second hole <NUM> may have a shape extending to be long (e.g., elongating) along the third direction Y and being parallel to the lower surface of the second semiconductor chip <NUM>.

Referring to <FIG> and <FIG> together, a length D1 of the second hole <NUM> in the second direction X may be shorter than a length T1 of the second semiconductor chip <NUM> in the second direction X. In addition, a length D2 of the second hole <NUM> in the third direction Y may be shorter than a length T2 of the second semiconductor chip <NUM> in the third direction Y.

In some example embodiments, a second chip bump group <NUM> may be formed between the second package substrate <NUM> and the second semiconductor chip <NUM>. For example, the second chip bump group <NUM> may be formed between the upper surface of the second package substrate <NUM> and the lower surface of the second semiconductor chip <NUM>. The second chip bump group <NUM> may include a plurality of bumps. The second chip bump group <NUM> may electrically connect the second package substrate <NUM> and the second semiconductor chip <NUM>. For example, the second semiconductor chip <NUM> may be mounted on the second package substrate <NUM> by a flip chip bonding method.

For example, each of the plurality of bumps included in the second chip bump group <NUM> may include a second pillar layer <NUM> and a second solder layer <NUM>. The second pillar layer <NUM> may be a post-shaped structure protruding from the lower surface of the second semiconductor chip <NUM>. In addition, the second pillar layer <NUM> may be electrically connected to the second semiconductor chip <NUM>. The second pillar layer <NUM> may include, for example, copper (Cu), a copper alloy, nickel (Ni), a nickel alloy, palladium (Pd), platinum (Pt), gold (Au), cobalt (Co), or a combination thereof, but is not limited thereto.

The second solder layer <NUM> may electrically connect the second pillar layer <NUM> and the second package substrate <NUM> to each other. For example, the second solder layer <NUM> may be in contact with the second chip pad <NUM> of the second package substrate <NUM>. The second solder layer <NUM> may have, for example, a spherical, hemispherical, or ellipsoidal structure. The second solder layer <NUM> may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or a combination thereof, but is not limited thereto.

Referring back to <FIG>, the second chip bump group <NUM> may include third chip bumps CB3 disposed on one side S3 of the second hole <NUM> and fourth chip bumps CB4 disposed on another side S4 of the second hole <NUM>. The number of third chip bumps CB3 and fourth chip bumps CB4 is plural, respectively, and the plurality of third chip bumps CB3 and the plurality of fourth chip bumps CB4 may be disposed along the third direction Y with the second hole <NUM> interposed therebetween. As such, the second hole <NUM> may be disposed between the third chip bumps CB3 and the fourth chip bumps CB4 in the second area A2.

A connection member 300A may be formed between the first package substrate <NUM> and the second package substrate <NUM>. The connection member 300A may electrically connect the first package substrate <NUM> and the second package substrate <NUM> to each other. For example, a lower end of the connection member 300A may be in direct contact with the upper pad <NUM> of the first package substrate <NUM>, and an upper end of the connection member 300A may be in direct contact with the second lower pad <NUM> of the second package substrate <NUM>. As described above, the semiconductor package according to some example embodiments may have a structure in which the second package substrate <NUM> is directly stacked on the first package substrate <NUM> through the connection member 300A.

The connection member 300A may have, for example, a cylindrical post shape, but is not limited thereto. The connection member 300A may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or a combination thereof, but is not limited thereto. The connection member 300A may be disposed at a side of the first semiconductor chip <NUM>. For example, a plurality of connection members 300A may be disposed to surround the first semiconductor chip <NUM> in plan view.

A mold film <NUM> may be disposed on the upper surface of the first package substrate <NUM> and the upper surface of the second package substrate <NUM>. The mold film <NUM> may cover the first package substrate <NUM>, the first semiconductor chip <NUM>, and the connection member 300A, and may cover the second package substrate <NUM> and the second semiconductor chip <NUM>. For example, the connection member 300A may penetrate through the mold film <NUM> and connect the first package substrate <NUM> and the second package substrate <NUM> to each other. The mold film <NUM> may fill a space between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM> and may cover the first chip bump group <NUM>. The mold film <NUM> may fill a space between the lower surface of the second semiconductor chip <NUM> and the upper surface of the second package substrate <NUM> and may cover the second chip bump group <NUM>. In addition, the mold film <NUM> may be formed to fill the second hole <NUM>.

As described above, in the semiconductor package in which the first semiconductor chip <NUM> on the first package substrate <NUM> and the second semiconductor chip <NUM> on the second package substrate <NUM> are vertically stacked as illustrated in <FIG>, the mold film <NUM> formed on the first package substrate <NUM> and the mold film <NUM> formed on the second package substrate <NUM> may be integrally formed. In addition, the integrally formed mold film <NUM> may fill the second hole penetrating through the second package substrate <NUM>. As described above, the mold film <NUM> formed on the upper surface of the first package substrate <NUM> and the mold film <NUM> formed on the upper surface of the second package substrate <NUM> may be integrally formed through hole <NUM> penetrating through the second package substrate <NUM>.

The mold film <NUM> may include, for example, an insulating polymer material such as an epoxy molding compound (EMC), but is not limited thereto. The mold film <NUM> may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin having a reinforcing material such as filler included in the thermosetting resin and the thermoplastic resin, for example, Ajinomoto Build-up Film (ABF), FR-<NUM>, Bismaleimide Triazine (BT) resin, etc..

As the filler, one or more materials selected from the group consisting of silica (SiO<NUM>), alumina (Al<NUM>O<NUM>), silicon carbide (SiC), barium sulfate (BaSO<NUM>), talc, clay, mica powders, aluminum hydroxide (Al(OH)<NUM>), magnesium hydroxide (Mg(OH)<NUM>), calcium carbonate (CaCO<NUM>), magnesium carbonate (MgCO<NUM>), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO<NUM>), barium titanate (BaTiO<NUM>), and calcium zirconate (CaZrO<NUM>) may be used. However, the material of the filler is not limited thereto, and may also include a metal material and/or an organic material.

In the semiconductor package illustrated in <FIG>, it is illustrated that only the first semiconductor chip <NUM> on the first package substrate <NUM> and the second semiconductor chip <NUM> on the second package substrate <NUM> are vertically stacked, but the example embodiment is not limited thereto. For example, in some example embodiments, another package substrate and semiconductor chip may be stacked on the upper surface of the second semiconductor chip <NUM>. That is, assuming that one package substrate and a semiconductor chip on the one package substrate are a single-stage semiconductor package, the semiconductor package according to some example embodiments may be implemented in a structure in which three or more stages of semiconductor packages are stacked.

<FIG> is an illustrative plan view for describing a semiconductor package according to an example embodiment. <FIG> is an illustrative cross-sectional view for describing a semiconductor package according to an example embodiment. Hereinafter, overlapping descriptions with the foregoing will be omitted and differences will be mainly described.

Referring to <FIG> and <FIG> together, in a semiconductor package according to some example embodiments, a first hole <NUM> penetrating through the first package substrate <NUM> in the first direction Z may be further formed, unlike that illustrated in <FIG>. For example, a length of the first hole <NUM> in the first direction Z may be the same as a length of the first package substrate <NUM> in the first direction Z. The first hole <NUM> may be formed to penetrate through a first area A1 on the first package substrate <NUM>. For example, the first hole <NUM> may be formed to penetrate through a portion of the first area A1, which is an area on the upper surface of the first package substrate <NUM> that overlaps the first semiconductor chip <NUM> in the vertical view. The first hole <NUM> may have a quadrangular shape extending to be long (e.g., elongating) along the third direction Y and being parallel to the lower surface of the first semiconductor chip <NUM> as illustrated in <FIG>, but is not limited thereto.

A length of the first hole <NUM> in the second direction X may be shorter than a length of the first semiconductor chip <NUM> in the second direction X. In addition, a length of the first hole <NUM> in the third direction Y may be shorter than a length of the first semiconductor chip <NUM> in the third direction Y.

The first chip bump group <NUM> may include first chip bumps CB1 disposed on one side S1 of the first hole <NUM> and second chip bumps CB2 disposed on another side S2 of the first hole <NUM>. The number of first chip bumps CB1 and second chip bumps CB2 is plural, respectively, and the plurality of first chip bumps CB1 and the plurality of second chip bumps CB2 may be disposed along the third direction Y with the first hole <NUM> interposed therebetween. As such, the first hole <NUM> may be disposed between the first chip bumps CB1 and the second chip bumps CB2 in the first area A1.

<FIG> is an illustrative view for describing an effect of the semiconductor package according to an example embodiment.

Referring to <FIG>, the semiconductor package according to an example embodiment may mitigate or prevent voids from being trapped inside the mold films <NUM> formed between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM> and between the lower surface of the second semiconductor chip <NUM> and the upper surface of the second package substrate <NUM> when the mold films <NUM> are formed, by providing the first hole <NUM> and the second hole <NUM> in the first package substrate <NUM> and the second package substrate <NUM>, respectively. For example, in an encapsulation process in which the mold film <NUM> is formed, voids formed between the lower surface of the second semiconductor chip <NUM> and the upper surface of the second package substrate <NUM> may be easily discharged through the second hole <NUM>. In addition, in the first semiconductor chip <NUM> and the first package substrate <NUM> disposed on a lower side of the second package substrate <NUM>, voids formed between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM> may be easily discharged through the first hole <NUM>. Through this, a semiconductor package with improved product reliability may be provided.

In addition, by making a molding material constituting the mold film <NUM> flow on the upper surfaces of the first semiconductor chip <NUM> and the first package substrate <NUM> through the second hole <NUM> formed in the second package substrate <NUM>, the encapsulation process of forming the mold film <NUM> in a semiconductor package in which a plurality of package substrates and a plurality of semiconductor chips are vertically stacked may be performed at once (in one step).

In addition, by directly connecting the package substrates <NUM> and <NUM> through the connection member 300A in the semiconductor package in which the plurality of package substrates and the plurality of semiconductor chips are vertically stacked, heat dissipation characteristics and electrical characteristics (e.g., power consumption characteristics or electrical connection speed characteristics) of the semiconductor package may be improved.

<FIG> are various illustrative views for describing a semiconductor package according to some example embodiments.

Referring to <FIG>, in a semiconductor package according to an example embodiment, a first hole 100Ha may be formed in a center or a central part of the first area A1 on the first package substrate <NUM>. For example, as illustrated in <FIG>, when the first hole 100Ha and the first area A1 each have a rectangular shape, a distance L1 from a first side d1 of the first area A1 to a first side e1 of the first hole 100Ha may be the same as a distance L1 from a second side d2 of the first area A1 to a second side e2 of the first hole 100Ha. In addition, a distance L2 from a third side d3 of the first area A1 to a third side e3 of the first hole 100Ha may be the same as a distance L2 from the fourth side d4 of the first area A1 to the fourth side e4 of the first hole 100Ha. Through this, during the encapsulation process, voids that occur most frequently in an area corresponding to a central area on the lower surface of the first semiconductor chip <NUM> may be more easily discharged in an area where the mold film is formed between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM>.

Referring to <FIG>, in a semiconductor package according to an example embodiment, a length of the first hole 100Hb in the third direction Y may be formed to be longer than a length of the first semiconductor chip <NUM> in the third direction Y. For example, as illustrated in <FIG>, each length of the first hole 100Hb on both sides in the third direction Y may be formed to be longer by 'a' than that of the first area A1 where the first semiconductor chip <NUM> is mounted on the first package substrate <NUM> by. Through this, during the encapsulation process, the voids inside the mold film formed between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM> may be more easily discharged.

Referring to <FIG>, in a semiconductor package according to an example embodiment, a first hole 100Hc may be formed in an elliptical shape extending to be long (e.g., elongating) in the third direction Y.

Various example embodiments of the first holes 100Ha, 100Hb, and 100Hc described with reference to <FIG> may be equally applied to the second hole <NUM> formed in the second package substrate <NUM>.

Next, referring to <FIG> and <FIG>, in a semiconductor package according to an example embodiment, a second hole 200Ha may be formed on the second package substrate <NUM> so that only a portion thereof overlaps the second area A2 in plan view, unlike that illustrated in <FIG>.

Next, referring to <FIG> and <FIG>, in a semiconductor package according to an example embodiment, a first hole 100Hd may be formed on the first package substrate <NUM> so that only a portion thereof overlaps the first area A1 in plan view, unlike that illustrated in <FIG>.

Next, referring to <FIG> and <FIG>, in a semiconductor package according to an example embodiment, a first hole 100He may be formed on the first package substrate <NUM> so as not to overlap the first area A1 in plan view, unlike those illustrated in <FIG> and <FIG> and <FIG>.

Referring to <FIG>, in an example embodiment, a circuit element <NUM> may be disposed on the first package substrate <NUM>. Although the circuit element <NUM> is illustrated as being disposed on the lower surface of the first package substrate <NUM>, this is merely an example. The circuit element <NUM> may include, for example, various active elements such as transistors or various passive elements such as capacitors, resistors, and inductors. As an example, circuit element <NUM> may be a capacitor.

Referring to <FIG>, in a semiconductor package according to an example embodiment, the circuit element <NUM> may be disposed in the first package substrate <NUM>.

For example, the circuit element <NUM> may be disposed in an area between the first lower pad <NUM> and the upper pad <NUM> and/or in an area between the first lower pad <NUM> and the first chip pad <NUM>.

Next, referring to <FIG>, in a semiconductor package according to an example embodiment, a connection member 300B may be implemented in a solder ball shape, unlike that illustrated in <FIG>. In this case, when the connection members 300A (illustrated in <FIG>) are implemented in a cylindrical post shape, lengths W1a, W2a, and W3a of areas where the connection members 300B are disposed in the second direction X may be longer than lengths W1, W2, and W3 (illustrated in <FIG>) of the areas where the respective corresponding connection members 300A (illustrated in <FIG>) are disposed in the second direction X, respectively. Therefore, in the semiconductor package, when a fine pitch is desired, the connection members 300A may be implemented in a cylindrical post shape as illustrated in <FIG>.

Next, referring to <FIG>, in a semiconductor package according to an example embodiment, connection members 300C and 300D may be implemented in a form in which a solder ball-shaped connection member 300D and a solder ball-shaped connection member 300C are stacked and connected. In this case, when the connection member 300B (illustrated in <FIG>) is implemented in the form of one solder ball, lengths W1b, W2b, and W3b of areas where the connection members 300C and 300D are disposed in the second direction X may be longer than lengths W1a, W2a, and W3a (illustrated in <FIG>) of the areas where the respective corresponding connection members 300B (illustrated in <FIG>) are disposed in the second direction X, respectively.

<FIG> is an illustrative flowchart illustrating a method of fabricating a semiconductor package according to an example embodiment. <FIG> are intermediate step drawings for describing the method of fabricating the semiconductor package according to an example embodiment. Hereinafter, a method of fabricating a semiconductor package according to an example embodiment will be described with reference to <FIG>.

First, referring to <FIG> and <FIG>, a first hole <NUM> is formed on a first package substrate <NUM> (S100). The first hole <NUM> may be formed to penetrate through the first package substrate <NUM> in the first direction Z. In addition, the first hole <NUM> may be formed in a first area A1 (illustrated in <FIG>), which is an area on which a first semiconductor chip <NUM> is mounted in the next process, on an upper surface of the first package substrate <NUM>.

Next, referring to <FIG> and <FIG>, the first semiconductor chip <NUM> is mounted on the upper surface of the first package substrate <NUM> (S110). The first semiconductor chip <NUM> may be mounted on the first package substrate <NUM> so that a first solder layer <NUM> of a first chip bump group <NUM> formed on a lower surface of the first semiconductor chip <NUM> is in contact with a first chip pad <NUM> exposed from the upper surface of the first package substrate <NUM>. The first semiconductor chip <NUM> may be mounted on the upper surface of the first package substrate <NUM> to overlap the first hole <NUM> in plan view.

Next, referring to <FIG> and <FIG>, connection members 300A are formed on the upper surface of the first package substrate <NUM> (S120). In some example embodiments, the connection member 300A may be disposed so that a lower end thereof is in direct contact with the upper pad <NUM> exposed from the upper surface of the first package substrate <NUM>.

Next, referring to <FIG> and <FIG>, a second hole <NUM> is formed in a second package substrate <NUM> (S130), and the second package substrate <NUM> is disposed on the upper surface of the first semiconductor chip <NUM> (S140). In this case, the second package substrate <NUM> may be disposed on the upper surface of the first semiconductor chip <NUM> so that an upper end of the connection member 300A is in direct contact with a second lower pad <NUM> exposed from a lower surface of the second package substrate <NUM>. Thus, the connection member 300A may directly and electrically connect the first package substrate <NUM> and the second package substrate <NUM> to each other.

Next, referring to <FIG> and <FIG>, a second semiconductor chip <NUM> is mounted on an upper surface of the second package substrate <NUM> (S150). The second semiconductor chip <NUM> may be mounted on the second package substrate <NUM> so that a second solder layer <NUM> of a second chip bump group <NUM> formed on a lower surface of the second semiconductor chip <NUM> is in contact with a second chip pad <NUM> exposed from the upper surface of the second package substrate <NUM>. The second semiconductor chip <NUM> may be mounted on the upper surface of the second package substrate <NUM> to overlap the second hole <NUM> in plan view.

Next, referring to <FIG> and <FIG>, a mold film <NUM> is formed on the upper surfaces of the first package substrate <NUM> and the second package substrate <NUM> (S160). It is only illustrated in <FIG> that an encapsulation process is performed by a transfer molding method among molding methods, but example embodiments are not limited thereto. For example, in some example embodiments, the encapsulation process may be performed by a compression molding method. Hereinafter, a case in which the mold film <NUM> is formed by the transfer molding method will be described as an example. In addition, it is only illustrated in <FIG> that a molding material is introduced into the semiconductor package from one side in the second direction X, but example embodiments are not limited thereto. For example, the molding material may be introduced into the semiconductor package from an arbitrary direction on an X-Y plane.

The molding material introduced into the semiconductor package may pass through the second hole <NUM> and flow to the upper surfaces of the first semiconductor chip <NUM> and the first package substrate <NUM>. Accordingly, the integrally formed mold film <NUM> may cover the first package substrate <NUM>, the first semiconductor chip <NUM>, and the connection member 300A, and may cover the second package substrate <NUM> and the second semiconductor chip <NUM> at the same time. In addition, the mold film <NUM> may fill a space between the lower surface of the first semiconductor chip <NUM> and the upper surface of the first package substrate <NUM>, cover the first chip bump group <NUM>, fill a space between the lower surface of the second semiconductor chip <NUM> and the upper surface of the second package substrate <NUM>, and cover the second chip bump group <NUM>. In addition, the mold film <NUM> may be formed to fill both first hole <NUM> and the second hole <NUM>.

As described above, because voids formed in the mold film <NUM> are easily discharged through the first hole <NUM> formed in the first package substrate <NUM> and the second hole <NUM> formed in the second package substrate <NUM>, product reliability of the semiconductor package may be improved.

Next, referring to <FIG>, a connection terminal <NUM> is attached to the first lower pad <NUM> of the first package substrate <NUM>.

Claim 1:
A semiconductor package comprising:
a first package substrate (<NUM>) including a first area;
a first semiconductor chip (<NUM>) on the first area;
a second package substrate (<NUM>) on an upper surface of the first semiconductor chip (<NUM>), the second package substrate (<NUM>) including a second area and a first hole (<NUM>) penetrating through the second area;
a second semiconductor chip (<NUM>) on the second area;
a connection member (300A) electrically connecting the first package substrate (<NUM>) and the second package substrate (<NUM>), the connection member (300A) being between the first package substrate (<NUM>) and the second package substrate (<NUM>);
a mold film (<NUM>) covering the second semiconductor chip (<NUM>) on the second package substrate (<NUM>), filling the first hole (<NUM>), and covering the first semiconductor chip (<NUM>) and the connection member (300A) on the first package substrate (<NUM>), and
a second hole (<NUM>) penetrating through the first package substrate (<NUM>), and
a first chip bump group (<NUM>) formed between the first semiconductor chip (<NUM>) and the first package substrate (<NUM>) and connecting the first semiconductor chip (<NUM>) and the first package substrate (<NUM>).