Patent Description:
Liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays are widely used as display apparatuses. In recent years, a technology for manufacturing a high-resolution display apparatus using a micro light-emitting diode (LED) is receiving attention at least in part because the micro LEDs have low power consumption and are eco-friendly.

<CIT> discloses a direct view multicolor light emitting device includes blue, green and red light emitting diodes (LEDs) in each pixel. The different light emitting diodes are formed by depositing different types of active region layers in a stack such that deposition area of each subsequent active region is less than the deposition area of any preceding active region, and by patterning the active region layers into different types of stacks. The active region layers may be formed as planar layers, or may be formed on semiconductor nanowires. The active region layers can emit light at the respective target wavelength range.

<CIT> discloses a semiconductor device including a light emitting structure including a first conductive type semiconductor layer, a plurality of active layers disposed to be spaced apart on the first conductive type semiconductor layer, and a plurality of second conductive type semiconductor layers disposed on the plurality of active layers, respectively, a first electrode electrically connected to the first conductive type semiconductor layer, and a plurality of second electrodes electrically connected to the plurality of second conductive type semiconductor layers, respectively, wherein the plurality of active layers include a first active layer, a second active layer, and a third active layer, the light emitting structure includes a first light emitter including the first active layer, a second light emitter including the second active layer, and a third light emitter including the third active layer, the first active layer emits light in a blue wavelength band, the second active layer emits light in a green wavelength band, and a height of the second active layer differs from a height of the first active layer.

Provided are micro light-emitting display apparatuses.

Provided are methods of manufacturing micro light-emitting display apparatuses.

According to an aspect of the disclosure, there is provided a micro light-emitting display apparatus as defined in the claims.

The rod semiconductor layer may comprise: a first portion having a width that is constant along a height direction and a second portion having a width that changes along the height direction, wherein the second portion includes a first inclined surface, a second inclined surface facing the first inclined surface, and an upper surface between the first inclined surface and the second inclined surface.

An angle between a surface extending from the first inclined surface and the upper surface may range from about <NUM> degrees to about <NUM> degrees.

The rod semiconductor layer may include a same material as the first semiconductor layer.

A width D1 of the upper surface satisfies the following equation: D1 = D-<NUM>×(h1/tanβ), where h1 is a height of the second portion, β is an angle between the surface extending from the first inclined surface and the upper surface and D is a width of the first portion.

An aspect ratio (H/D) of the first portion satisfies <NUM><H/D<<NUM>, where H is a height of the first portion and D is a width of the first portion.

The height H of the first portion satisfies <NUM><H<<NUM>.

The width D of the first portion satisfies <NUM><D<<NUM>.

The height h1 of the second portion is about <NUM> or less.

The micro light-emitting display apparatus may further comprise a third light-emitting unit configured to emit red light.

The third light-emitting unit may include a plurality of nanorod semiconductor layers arranged apart from each other on the first semiconductor layer, a plurality of third active layers each of which is provided on a respective one of the plurality of nanorod semiconductor layers, and a plurality of fourth semiconductor layers each of which is provided on a respective one of the plurality of third active layers.

Each of the nanorod semiconductor layers and each of the third active layers have a width in a range of about <NUM> to about <NUM>.

A pitch between the nanorod semiconductor layers is in a range of about <NUM> to about <NUM>.

Each of the nanorod semiconductor layers include an inclined surface and a flat surface.

The micro light-emitting display apparatus may further comprise fourth light-emitting unit configured to emit blue light, and a color conversion layer configured to convert the blue light emitted from the fourth light-emitting unit into red light.

The isolation structure comprises an ion implantation area.

According to another aspect of the disclosure, there is provided a method of manufacturing a micro light-emitting display apparatusas defined in the claims.

In the planarizing of the semiconductor layer, an etching solution including potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH) is used.

The rod semiconductor layer may include a first portion having a width that is constant along a height direction and a second portion having a width that changes along the height direction, wherein the second portion may include a first inclined surface, a second inclined surface facing the first inclined surface, and an upper surface between the first inclined surface and the second inclined surface.

An angle between a surface extending from the first inclined surface and the upper surface ranges from about <NUM> degrees to about <NUM> degrees.

The micro light-emitting display apparatus further includes a third light-emitting unit configured to emit red light.

The third light-emitting unit includes a plurality of nanorod semiconductor layers arranged apart from each other on the first semiconductor layer, a plurality of third active layers each of which is provided on a respective one of the plurality of nanorod semiconductor layers, and a plurality of fourth semiconductor layers each of which is provided on a respective one of the third active layers.

According to another aspect of the disclosure, there is provided a method of manufacturing a micro light-emitting display apparatus, the method comprising: forming a first active layer on a first semiconductor layer; forming a second semiconductor layer on the first active layer; forming an isolation structure in the first active layer and the second semiconductor layer; etching an upper surface of the isolation structure to form an opening; forming a rod semiconductor layer in the opening; forming a second active layer on the rod semiconductor layer; and forming a third semiconductor layer on the second active layer.

According to another aspect of the disclosure, there is provided a micro light-emitting display apparatus comprising: a first semiconductor layer; an isolation structure provided on the first semiconductor layer; a first light-emitting unit provided on an upper surface of the first semiconductor layer to form a first sub-pixel, the first light-emitting unit including a first active layer and a second semiconductor layer provided on the first active layer; a second light-emitting unit provided in a first area of the isolation structure to form a second sub-pixel, the second light-emitting unit including a rod semiconductor layer, a second active layer provided on the rod semiconductor layer, and a third semiconductor layer provided on the second active layer, wherein the first active layer is configured to emit first light and the second active layer is configured to emit second light.

The micro light-emitting display apparatus may further comprise: a third light-emitting unit provided in a second area of the isolation structure to form a third sub-pixel, the third light-emitting unit including a plurality of nanorod semiconductor layers, a plurality of third active layers each of which is provided on a respective one of the plurality of nanorod semiconductor layers, and a plurality of fourth semiconductor layers each of which is provided on a respective one of the plurality of third active layers, wherein the third active layer is configured to emit third light.

The above and other aspects, features, and advantages of certain example embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:.

Hereinafter, a micro light-emitting display apparatus and a method of manufacturing the same according to various example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout. In the drawings, the sizes of constituent elements may be exaggerated for clarity.

In addition, it will be understood that when a unit is referred to as "comprising" another element, it does not preclude the possibility that one or more other elements may exist or may be added. In addition, thicknesses or sizes of elements in the drawings are exaggerated for convenience and clarity of description. Furthermore, when an element is referred to as being "on" or "above" another element, it may be directly on the other element, or intervening elements may also be present. Moreover, the materials constituting each layer in the following example embodiments are merely examples, and other materials may be used.

In addition, the terms "-er", "-or", and "module" described in the specification mean units for performing at least one function and/or operation and can be implemented by hardware components or software components and combinations thereof.

The particular implementations shown and described herein are illustrative examples of the inventive concept and are not intended to otherwise limit the scope of the invention which is defined by the appended claims.

For the sake of brevity, conventional electronics, control systems, software development and other functional aspects of the systems may not be described in detail. Furthermore, the connecting lines, or connectors shown in the various figures presented are intended to represent exemplary functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.

The use of the terms "a," "an," and "the" and similar referents is to be construed to cover both the singular and the plural.

Operations constituting a method may be performed in any suitable order unless explicitly stated that they should be performed in the order described. Further, the use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the inventive concept and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.

<FIG> is a schematic cross-sectional view of a micro light-emitting display apparatus according to an example embodiment.

A micro light-emitting display apparatus <NUM> includes a plurality of sub-pixels, and is configured to emit light using each of the plurality of sub-pixels. The micro light-emitting display apparatus <NUM> may include, for example, a first sub-pixel SP1 and a second sub-pixel SP2.

The micro light-emitting display apparatus <NUM> includes a first semiconductor layer <NUM>, an isolation structure <NUM> provided on the first semiconductor layer <NUM> to define the plurality of sub-pixels, a first light-emitting unit <NUM> including a first active layer <NUM> configured to emit blue light in the first sub-pixel SP1 defined by the isolation structure <NUM>, and a second light-emitting unit <NUM> including a rod semiconductor layer <NUM> provided in the second sub-pixel SP2 defined by the isolation structure <NUM> and a second active layer <NUM> provided on the rod semiconductor layer <NUM>. The isolation structure <NUM> is provided on an upper surface of the first semiconductor layer <NUM>.

The second light-emitting unit <NUM> is configured to emit, for example, green light. The rod semiconductor layer <NUM> is provided between isolation structures <NUM>, and the second active layer <NUM> may be above the isolation structures <NUM>.

The first semiconductor layer <NUM> may include a first type semiconductor. For example, the first semiconductor layer <NUM> may include an n-type semiconductor. Alternatively, the first semiconductor layer <NUM> may include a p-type semiconductor. The first semiconductor layer <NUM> may include a III-V group n-type semiconductor, for example, n-GaN. Alternatively, the first semiconductor layer <NUM> may include an AlN layer or an AlxGa(<NUM>-x)N (<NUM>≦x≦<NUM>) layer. The first semiconductor layer <NUM> may have a single layer structure or a multilayer structure.

The first active layer <NUM> is provided on the upper surface of the first semiconductor layer <NUM>. The first active layer <NUM> may generate light while electrons and holes are combined. The first active layer <NUM> may have a multi-quantum well (MQW) structure or a single-quantum well (SQW) structure. The first active layer <NUM> may include a III-V group semiconductor, for example, GaN. The first active layer <NUM> may have, for example, a multi-quantum well structure in which InGaN layers and GaN layers are alternately stacked.

The first light-emitting unit <NUM> further includes a second semiconductor layer <NUM>. The second semiconductor layer <NUM> may include a second type semiconductor layer. For example, the second semiconductor layer <NUM> may include a p-type semiconductor layer. When the first semiconductor layer <NUM> is n-type, the second semiconductor layer <NUM> may be p-type. The second semiconductor layer <NUM> may include, for example, a GaN layer, an AlN layer, or an AlxGa(<NUM>-x)N (<NUM>≦x≦<NUM>) layer. For example, as a p-type dopant, for example, magnesium (Mg), calcium (Ca), zinc (Zn), cadmium (Cd), mercury (Hg), or the like may be used.

The second light-emitting unit <NUM> includes the rod semiconductor layer <NUM>, the second active layer <NUM>, and a third semiconductor layer <NUM>. A first electrode <NUM> may be provided on the second semiconductor layer <NUM> and the third semiconductor layer <NUM>, respectively. The first electrode <NUM> may be, for example, a pixel electrode capable of applying a voltage in sub-pixel units. A current blocking layer <NUM> may be further provided at both ends of the first electrode <NUM>. The current blocking layer <NUM> may be similar to the current blocking layer <NUM> to be described below in detail with reference to <FIG>.

An electron blocking layer <NUM> may be further provided between the first active layer <NUM> and the second semiconductor layer <NUM>. In addition, an electron blocking layer <NUM> may be further provided between the second active layer <NUM> and the third semiconductor layer <NUM>. However, according to another example embodiment, the electron blocking layers <NUM> and <NUM> may be omitted.

Meanwhile, the isolation structure <NUM> includes an ion implantation area. Here, ions may include, for example, nitrogen (N) ions, boron (B) ions, argon (Ar) ions, or phosphorus (P) ions. Because no current is injected in the ion implantation area, light is not emitted, and when the isolation structure <NUM> is configured with the ion implantation area, a light-emitting unit may be formed without a mesa structure. That is, because the light-emitting unit is provided by the isolation structure <NUM>, a micro light-emitting device array structure may be implemented without an etching process. In a case of using the etching process, there is a limit to reducing the size of sub-pixels. However, because the isolation structure <NUM> does not require the use of the etching process, it is possible to manufacture a small-sized sub-pixel, thereby manufacturing a high-resolution micro light-emitting device array.

<FIG> is a conceptual diagram illustrating an enlarged second light-emitting unit <NUM>.

The first semiconductor layer <NUM> may be a doped material layer or an updoped material layer. In an example, the first semiconductor layer <NUM> may be a doped GaN layer or an undoped GaN layer. The rod semiconductor layer <NUM> may include a first portion 130A having a constant width and a second portion 130B having a variable width, wherein the second portion 130B may include a first inclined surface S11, a second inclined surface S12 facing the first inclined surface S11, and an upper surface <NUM> between the first inclined surface S11 and the second inclined surface S12. For example, the upper surface <NUM> may be flat. For example, the upper surface <NUM> may be a plane parallel to the upper surface of the first semiconductor layer <NUM>. The rod semiconductor layer <NUM> may include, for example, a GaN layer, an AlN layer, or an AlxGa(<NUM>-x)N (<NUM>≦x≦<NUM>) layer. The rod semiconductor layer <NUM> may include the same material as that of the first semiconductor layer <NUM>.

The second active layer <NUM> may be provided on the rod semiconductor layer <NUM>.

The second portion 130B may have a narrower width as it goes upward. For convenience of explanation, the rod semiconductor layer <NUM> is divided into the first portion 130A and the second portion 130B, but the first portion and the second portion may be a single body of the same material and composition without having a physical boundary. The first portion 130A may have a given height H and a given width (e.g., diameter) D. An aspect ratio of the first portion 130A, that is, a ratio (H/D) of the height H and the width D may be in a range of, for example, <NUM><H/D<<NUM>. The first portion 130A may have a width D that satisfies this aspect ratio. For example, the width D of the first portion 130A may be in a range of <NUM><D<<NUM>. In addition, the first portion 130A may have a height H that satisfies the aspect ratio. For example, the height H of the first portion 130A may be in a range of <NUM><H<<NUM>. The second portion 130B may be a portion regrown from the first portion 130A. The second portion 130B may include a first inclined surface S11 and a second inclined surface S12. The first and second inclined surfaces S11 and S12 may be symmetrical to each other with respect to the upper surface <NUM>. However, the disclosure is not limited thereto. In an example, a geometric shape of the second portion 130B viewed in plan may be a hexagonal shape. The first inclined surface S11 may have a given inclination angle β. The inclination angle β is an angle between a surface extending from the first inclined surface S11 and the upper surface <NUM>. The inclination angle β may be in a range of, for example, about <NUM> degrees to about <NUM> degrees. Because the second portion 130B has a narrower width as it goes upward, the width D1 of the upper surface <NUM> may be narrower than the width D of the first portion 130A. The width D1 of the upper surface <NUM> may satisfy the following equation.

Here, D is the width of the first portion 130A, h1 is the height of the second portion 130B, and β is the inclination angle. The height h1 of the second portion 130B may be about <NUM> or less. The second active layer <NUM> may be provided on the second portion 130B. The second active layer <NUM> may cover the upper surface <NUM> and the first and second inclined surfaces S11 and S12. The upper surface <NUM> may be flat. When the second active layer <NUM> is grown on the flat upper surface <NUM>, the thickness and composition of the second active layer <NUM> may be uniform. The second active layer <NUM> may include an InGaN/GaN layer, but the disclosure is not limited thereto. When the second active layer <NUM> is grown on the flat upper surface <NUM>, indium (In) distribution uniformity of the second active layer <NUM> may be relatively higher than when the second active layer <NUM> is grown on a non-flat surface. When composition distribution and thickness uniformity of the second active layer <NUM> is high, high-efficiency green light having a narrow full width at half maximum (FWHM) may be emitted.

<FIG> is a view of a micro light-emitting display apparatus according to another example embodiment.

A micro light-emitting display apparatus <NUM> includes a first semiconductor layer <NUM>, and an isolation structure <NUM> provided on the first semiconductor layer <NUM>. The isolation structure <NUM> is configured to define the first sub-pixel SP1, the second sub-pixel SP2, and a third sub-pixel SP3. According to an example embodiment, the isolation structure <NUM> is provided on an upper surface of the first semiconductor layer <NUM>. The micro light-emitting display apparatus <NUM> further includes a first light-emitting unit <NUM> configured to emit blue light in the first sub-pixel SP1, a second light-emitting unit <NUM> configured to emit green light in the second sub-pixel SP2, and a third light-emitting unit <NUM> configured to emit blue light in the third sub-pixel SP3.

The first light-emitting unit <NUM> includes the first semiconductor layer <NUM>, a first active layer <NUM>, and a second semiconductor layer <NUM>. An electron blocking layer <NUM> may be further provided between the first active layer <NUM> and the second semiconductor layer <NUM>. The first light-emitting unit <NUM> has substantially the same configuration and operation as those of the first light-emitting unit <NUM> described with reference to <FIG>, and thus a detailed description thereof will not be given herein. The second light-emitting unit <NUM> includes a rod semiconductor layer <NUM>, a second active layer <NUM>, and a third semiconductor layer <NUM>. An electron blocking layer <NUM> may be further provided between the second active layer <NUM> and the third semiconductor layer <NUM>. The second light-emitting unit <NUM> has substantially the same configuration and operation as those of the second light-emitting unit <NUM> described with reference to <FIG>.

The third light-emitting unit <NUM> may include the first semiconductor layer <NUM>, a third active layer <NUM>, and a fourth semiconductor layer <NUM>. The third light-emitting unit <NUM> may be configured to emit blue light. The third light-emitting unit <NUM> may be configured substantially the same as the first light-emitting unit <NUM>. An electron blocking layer <NUM> may be further provided between the third active layer <NUM> and the fourth semiconductor layer <NUM>.

A first electrode <NUM> may include a reflective material to reflect light emitted from the first active layer <NUM>, the second active layer <NUM>, and the third active layer <NUM>. The first electrode <NUM> may include, for example, Ag, Au, Al, Cr, or Ni, or an alloy thereof. The first electrode <NUM> is a pixel electrode and may independently drive a sub-pixel. The first electrodes <NUM> may be arranged apart from each other, and may be arranged to face the first active layer <NUM>, the second active layer <NUM>, and the third active layer <NUM>, respectively. A current blocking layer <NUM> may be further provided at both ends of the first electrode <NUM>. The current blocking layer <NUM> may prevent leakage of current to other adjacent sub-pixel areas. The current blocking layer <NUM> may include, for example, silicon oxide or silicon nitride. The current blocking layer <NUM> may be provided to overlap at least partially between one surface of the isolation structure <NUM> and the first electrode <NUM>. The current blocking layer <NUM> may be arranged to correspond to the isolation structure <NUM>.

According to an example embodiment, the first sub-pixel SP1 emits blue light, the second sub-pixel SP2 emits green light, and the third sub-pixel SP3 emits blue light. A full-color image may be displayed by converting the blue light emitted from the third sub-pixel SP3 into red light. This will be described later below.

A micro light-emitting display apparatus <NUM> includes the first semiconductor layer <NUM>, the isolation structure <NUM> configured to define the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 that are provided apart from each other on the first semiconductor layer <NUM>, the first light-emitting unit <NUM> configured to emit blue light in the first sub-pixel SP1, the second light-emitting unit <NUM> configured to emit green light in the second sub-pixel SP2, and a third light-emitting unit <NUM> configured to emit red light in the third sub-pixel SP3.

Components using the same reference numerals as those used in <FIG> in the example embodiment are substantially the same as those described with reference to <FIG>, and thus detailed descriptions thereof will not be given herein.

The third light-emitting unit <NUM> may include a plurality of nanorod semiconductor layers <NUM> arranged to be apart from each other on the first semiconductor layer <NUM>, a third active layer <NUM> provided on the plurality of nanorod semiconductor layers <NUM>, and a fourth semiconductor layer <NUM> provided on the third active layer <NUM>. An electron blocking layer <NUM> may be further provided between the third active layer <NUM> and the fourth semiconductor layer <NUM>. According to an example embodiment, the plurality of nanorod semiconductor layers <NUM> may be arranged to be apart from each other on an upper surface of the first semiconductor layer <NUM>.

<FIG> is an enlarged view of the third light-emitting unit <NUM>. According to an example embodiment illustrated in <FIG>, the electron blocking layer <NUM> is omitted.

The first semiconductor layer <NUM> may include, for example, an n-type semiconductor. However, the disclosure is not necessarily limited thereto, and according to another example embodiment, the first semiconductor layer <NUM> may include a p-type semiconductor. The first semiconductor layer <NUM> may include a III-V group n-type semiconductor, for example, n-GaN. The first semiconductor layer <NUM> may have a single layer structure or a multilayer structure. For example, the first semiconductor layer <NUM> may include any one of InAlGaN, GaN, AlGaN, InGaN, AIN, and InN, and may include a semiconductor layer doped with a conductive dopant such as silicon (Si), germanium (Ge), and tin (Sn).

The nanorod semiconductor layers <NUM> may be arranged apart from each other on the first semiconductor layer <NUM>. A nanorod semiconductor layer <NUM> may include the same material as that of the first semiconductor layer <NUM>. The nanorod semiconductor layer <NUM> may include an inclined surface and a flat surface thereon. Accordingly, the third active layer <NUM> may also include an inclined surface and a flat surface thereon. According to an example embodiment, the inclined surface may be provided on a side portion of the nanorod semiconductor layers <NUM> and the flat surface may be provided in a middle portion of the nanorod semiconductor layers <NUM>.

The third active layer <NUM> may be provided on the nanorod semiconductor layer <NUM>. The third active layer <NUM> may generate light while electrons and holes are combined, and may have an MQW structure or an SQW structure. The third active layer <NUM> may include a III-V group semiconductor, for example, InGaN, GaN, AlGaN, AlInGaN, or the like.

The fourth semiconductor layer <NUM> is provided on the third active layer <NUM> and may include a semiconductor layer of a different type from the nanorod semiconductor layer <NUM>. For example, the fourth semiconductor layer <NUM> may include a p-type semiconductor layer. The fourth semiconductor layer <NUM> may include, for example, InAlGaN, GaN, AlGaN and/or InGaN, and may be a semiconductor layer doped with a conductive dopant such as Mg.

Hereinafter, a light-emitting operation of the third light-emitting unit <NUM> will be described. Light is emitted by the recombination of electrons and holes in an active layer. A wavelength of the emitted light may vary depending on the content of a material in the active layer. For example, the greater the In content, the greater the wavelength of the emitted light. For example, when the In content of the active layer is about <NUM> %, the active layer may emit blue light of about <NUM>, and when the In content of the active layer is about <NUM> %, the active layer may emit green light of about <NUM>. In addition, when the In content of the active layer is about <NUM> %, the active layer may emit red light of about <NUM>.

On the other hand, in general, as the In content of the active layer increases and the wavelength of emitted light increases, the efficiency of a light-emitting diode decreases.

<FIG> is a graph showing luminous efficiency according to a wavelength of a general active layer. As shown in <FIG>, when the active layer is formed of a material emitting blue light of about <NUM>, the maximum value of external quantum efficiency is about <NUM>. However, when the active layer is formed of a material emitting red light of about <NUM>, the maximum value of the external quantum efficiency becomes less than <NUM>. This is because as the In content increases, a lattice mismatch between materials in the active layer, for example, InGaN and GaN, occurs. Such a lattice mismatch may cause strain or defects in the material in the active layer, and the strain may lead to phase separation of the active layer.

<FIG> is a graph showing a phase separation state according to the material content of InxGa(<NUM>-x)N in a relaxed state, and <FIG> is a graph showing a phase separation state according to the material content of InxGa(<NUM>-x)N in a strain state.

As shown in <FIG>, when InxGa(<NUM>-x)N in a relaxed state includes the In content of <NUM> or less, depending on the temperature, InxGa(<NUM>-x)N may be in a spinodal state or a binodal state. In particular, when the In content is about <NUM> to about <NUM>, InxGa(<NUM>-x)N is in a spinodal state in most of the temperature range. In the spinodal state, an active layer may become unstable, and a light-emitting diode including such an active layer may cause problems in a manufacturing process.

According to <FIG>, when InxGa(<NUM>-x)N in a strain state includes the In content of <NUM> or less, for example, <NUM> to <NUM>, the active layer is in a binodal state over all temperature ranges. Therefore, when the In content is less than <NUM> and in a strain state, it means that InxGa(<NUM>-x)N may maintain a stable state regardless of temperature. This strain state occurs when the active layer has a lattice mismatch.

When the thickness or width of the active layer increases, the strain caused by the lattice mismatch may disappear as defects such as dislocation occur. Therefore, it is necessary to form an active layer in which defects do not occur while maintaining a strain state.

The width and thickness of the active layer in which phase separation does not occur while maintaining the strain state may be determined by lattice constants of materials in the active layer. <FIG> is a view illustrating a relationship between a width and a thickness capable of maintaining a strain for each material of an active layer of a micro light-emitting display apparatus according to an embodiment. As illustrated in <FIG>, according to the material, the width and thickness of the active layer capable of maintaining a strain may vary. Also, even with the same material, the greater the width, the smaller the thickness that may maintain the strain. For example, when In<NUM>Ga<NUM>N having a width of about <NUM> or more is to be stacked on a GaN layer, In<NUM>Ga<NUM>N needs to be stacked to a thickness of about <NUM> or less to maintain the strain. However, stacking layers to a thickness of <NUM> or less may cause process difficulties.

In order to overcome such process difficulties, the strain may be maintained by reducing the width of the active layer. For example, in a case of stacking In<NUM>Ga<NUM>N with a thickness of <NUM> or more, by forming a width of <NUM> or less, defect generation and phase separation may be reduced and the strain may be maintained. In particular, when materials having a large lattice mismatch are stacked, limiting a width may effectively reduce the occurrence of defects.

Referring back to <FIG>, the nanorod semiconductor layer <NUM> and the third active layer <NUM> of the third light-emitting unit <NUM> according to an example embodiment may have a nano-sized width W. For example, the width W of the nanorod semiconductor layer <NUM> and the third active layer <NUM> may be in a range of about <NUM> or more and about <NUM> or less. In addition, a pitch P between the nanorod semiconductor layers <NUM> may be in a range of about <NUM> or less, for example, about <NUM> or more and about <NUM> or less. The thickness of the third active layer <NUM> may be in a range of <NUM> or more and <NUM> or less. In this way, by reducing the width W of the third active layer <NUM>, even if a lattice mismatch in the third active layer <NUM> or a lattice mismatch between the nanorod semiconductor layer <NUM> and the third active layer <NUM> is large, the occurrence of defects may be reduced.

When the width and thickness of the third active layer <NUM> are adjusted, defects may be prevented even when the In content is high, so that light having high light efficiency may be emitted. For example, the third active layer <NUM> may include InxGa<NUM>-xN (<NUM>≦5x≦<NUM>), and the In content may be about <NUM> % or more capable of emitting red light.

Meanwhile, the third light-emitting unit <NUM> may have a width W<NUM> of about <NUM> or less, for example, about <NUM> or less.

Because the nanorod semiconductor layer <NUM> serves as a seed layer when the third active layer <NUM> grows, and has a narrow width, even if there is a lattice mismatch between the nanorod semiconductor layer <NUM> and the third active layer <NUM>, a defect may not occur. Accordingly, the third active layer <NUM> may efficiently emit red light.

<FIG> shows a micro light-emitting display apparatus according to an example embodiment.

A micro light-emitting display apparatus <NUM> includes the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit different color lights, respectively. The micro light-emitting display apparatus <NUM> may include a support substrate <NUM>, a driving layer <NUM> provided on the support substrate <NUM>, and a light-emitting layer <NUM> provided on the driving layer <NUM>.

The support substrate <NUM> may not be a substrate for growth but may be a substrate for supporting the driving layer <NUM> thereon. For example, a silicon substrate, a glass substrate, a sapphire substrate, or a silicon substrate coated with SiO<NUM> may be used as the support substrate <NUM>. However, this is merely exemplary, and various other materials may be used as the support substrate <NUM>.

The driving layer <NUM> may include a driving device <NUM> for electrically driving the light-emitting layer <NUM> for each sub-pixel. The driving device <NUM> may include, for example, a transistor, a thin-film transistor (TFT), or a high electron mobility transistor (HEMT). For example, the driving device <NUM> may include a gate electrode G, a source electrode S, and a drain electrode D. The driving layer <NUM> may further include at least one insulating layer. For example, at least one insulating layer may include a first insulating layer <NUM> and a second insulating layer <NUM>. The second insulating layer <NUM> may be, for example, a gate oxide. A third insulating layer <NUM> may be further provided between the driving layer <NUM> and the light-emitting layer <NUM>.

A bonding layer <NUM> may be provided between the support substrate <NUM> and the driving layer <NUM>. The bonding layer <NUM> is for bonding the driving layer <NUM> to the support substrate <NUM>, and may include, for example, an adhesive layer or a direct bonding layer. The adhesive layer may include, for example, epoxy, spin on glass (SOG), or benzocyclobutene (BCB). The direct bonding layer may be formed by, for example, plasma or ion beam treatment. The bonding layer <NUM> is for physically bonding the driving layer <NUM> to the support substrate <NUM>, and the driving layer <NUM> may be bonded to the support substrate <NUM> by a bonding method that does not require electrical connection. The bonding layer <NUM> may cover, for example, the source electrode S and the drain electrode D during a bonding process.

Meanwhile, the support substrate <NUM> may be a substrate used for a complementary metal-oxide semiconductor (CMOS) backplane. In this case, the support substrate <NUM> and the driving layer <NUM> may constitute a CMOS backplane. When the support substrate <NUM> and the driving layer <NUM> constitute the CMOS backplane, the bonding layer <NUM> may not be provided.

The light-emitting layer <NUM> includes a micro light-emitting device array, for example, a micro LED array. The light-emitting layer <NUM> includes the first light-emitting unit <NUM> that emits light of a first wavelength, for example, blue light, the second light-emitting unit <NUM> that emits light of a second wavelength, for example, green light, and the third light-emitting unit <NUM> that emits light of a third wavelength, for example, blue light. The first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM> are the same as those described with reference to <FIG>, so detailed descriptions thereof will not be given herein, and reference numerals of the light-emitting units follow <FIG>. In <FIG>, reference numerals of the elements in the light-emitting units are omitted for convenience. In <FIG>, the light-emitting layer <NUM> is arranged in the reverse direction of the structure shown in <FIG>.

The light-emitting layer <NUM> has the isolation structure <NUM> such that light from each of the active layers of the first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM> is emitted in sub-pixel units. In other words, the light-emitting layer <NUM> may have the isolation structure <NUM> between neighboring sub-pixels.

The first electrode <NUM> electrically connected to each of the second semiconductor layer <NUM>, the third semiconductor layer <NUM>, and the fourth semiconductor layer <NUM> is provided, and a second electrode <NUM> electrically connected to the first semiconductor layer <NUM> may be provided. The first electrode <NUM> may be a pixel electrode, and the second electrode <NUM> may be a common electrode. When the second, third, and fourth semiconductor layers <NUM>, <NUM>, and <NUM> include a p-type semiconductor, the first electrode <NUM> is a p-type electrode, and when the first semiconductor layer <NUM> includes an n-type semiconductor, the second electrode <NUM> may be an n-type electrode.

The driving device <NUM> is electrically connected to the first electrode <NUM>, and power of the first electrode <NUM> may be turned on and off by the driving device <NUM>. Therefore, the driving device <NUM> may selectively drive at least one desired sub-pixel from among the first, second, and third sub-pixels SP1, SP2, and SP3.

The third insulating layer <NUM> may be further provided between the driving layer <NUM> and the light-emitting layer <NUM>. A via <NUM> may be further provided on the third insulating layer <NUM> so that the driving device <NUM> and the first electrode <NUM> are electrically connected to each other.

The second electrode <NUM> may be formed as a transparent electrode or an opaque electrode. The transparent electrode may include, for example, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or In-Ga-Zn-O (IGZO). When the second electrode <NUM> is an opaque electrode, the second electrode <NUM> may further include a window area <NUM> such that light emitted from each active layer may be transmitted. The window area <NUM> may be provided at a position corresponding to each active layer. When the second electrode <NUM> is formed as a transparent electrode, the second electrode <NUM> may be arranged to cover the entire first semiconductor layer <NUM> without a window area.

According to an example embodiment, from among lights emitted from the first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM>, light directed downward may be reflected by the first electrode <NUM> and directed upward, and light emitted in a lateral direction from the first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM> may not be absorbed or scattered because there is no mesa structure in the isolation structure <NUM> and the light may go upward. Thus, the luminous efficiency may be improved. In addition, because the size of sub-pixels may be reduced by the isolation structure <NUM>, the resolution may be increased. In addition, the present embodiment may have a vertical electrode structure in which the first electrode <NUM> and the second electrode <NUM> are arranged vertically with respect to each active layer (e.g., arranged in a direction perpendicular to the active layer). Because the second electrode <NUM> is arranged on the first semiconductor layer <NUM> and may be manufactured without a via hole process, an electrode may be formed without a mesa structure.

On the first semiconductor layer <NUM>, a plurality of color conversion layers <NUM>, <NUM>, and <NUM> emitting different color lights by lights emitted from the first, second and third light-emitting units <NUM>, <NUM>, and <NUM> may be provided. The first light-emitting unit <NUM> and the third light-emitting unit <NUM> may emit, for example, blue light. The second light-emitting unit <NUM> may emit, for example, green light. The color conversion layers <NUM>, <NUM>, and <NUM> may be provided corresponding to the sub-pixels SP1, SP2, and SP3, respectively. The plurality of color conversion layers <NUM>, <NUM>, and <NUM> may include, for example, a blue conversion layer, a green conversion layer, and a red conversion layer. The blue conversion layer <NUM> may correspond to a blue sub-pixel, the green conversion layer <NUM> may correspond to a green sub-pixel, and the red conversion layer <NUM> may correspond to a red sub-pixel.

The blue conversion layer <NUM> may include, for example, a material that emits blue light, or may be a transmission layer through which blue light emitted from the first light-emitting unit <NUM> passes.

The blue conversion layer <NUM> may transmit blue light emitted from the first light-emitting unit <NUM> to be emitted to the outside. The blue conversion layer <NUM> may further include a photoresist or a light scattering agent having good transmission characteristics.

The green conversion layer <NUM> may include a material that emits green light emitted from the second light-emitting unit <NUM> or may be a transmission layer through which green light emitted from the second light-emitting unit <NUM> passes.

The red conversion layer <NUM> may convert blue light emitted from the third light-emitting unit <NUM> into red light. The red conversion layer <NUM> may include quantum dots (QD) of a certain size that are excited by blue light to emit red light. A quantum dot may have a core-shell structure having a core portion and a shell portion, and may also have a particle structure without a shell. The core-shell structure may have a single-shell or a multi-shell. The multi-shell may be, for example, a double-shell.

The quantum dot may include, for example, at least one of a group II-VI series semiconductor, a group III-V series semiconductor, a group IV-VI series semiconductor, a group IV series semiconductor, and a graphene quantum dot. As a specific example, the quantum dot may include at least one of Cd, selenium (Se), Zn, sulfur (S), and indium phosphide (InP), but is not limited thereto. Each quantum dot may have a diameter of tens of nm or less, for example, a diameter of about <NUM> or less. Further, the red conversion layer <NUM> may include a phosphor that is excited by blue light to emit red light. Meanwhile, the red conversion layer <NUM> may further include a photoresist having good transmission characteristics or a light scattering agent that uniformly emits green light.

The blue conversion layer <NUM>, the green conversion layer <NUM>, and the red conversion layer <NUM> may have a cross-sectional shape in which the width increases toward the top. A partition <NUM> may be between the adjacent color conversion layers <NUM>, <NUM>, and <NUM>. A reflective layer <NUM> is further provided on a side surface of the partition <NUM> to increase extraction efficiency of light converted from each color conversion layer. Alternatively, the partition <NUM> may be formed of a black matrix for absorbing light. The black matrix may improve contrast by preventing crosstalk between the blue conversion layer <NUM>, the green conversion layer <NUM>, and the red conversion layer <NUM>.

Because blue light, green light, and red light are emitted from the first, second, and third sub-pixels SP1, SP2, and SP3, respectively, and the amount of light is controlled by the amount of current injected into the first electrode <NUM> and the second electrode <NUM>, a color image may be displayed. Even if the size of sub-pixels is reduced, light leakage to neighboring sub-pixels is reduced or prevented by an isolation structure, thereby increasing the resolution of a display apparatus. In addition, in the present embodiment, because a color conversion layer for converting to red light is provided among color conversion layers, and blue light and green light may be transmitted as it is, light efficiency may be improved and a manufacturing process of the color conversion layer may be reduced.

<FIG> is a view of a micro light-emitting display apparatus according to another embodiment.

A micro light-emitting display apparatus <NUM> includes the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 emit different color lights, respectively. The micro light-emitting display apparatus <NUM> may include a support substrate <NUM>, a driving layer <NUM> provided on the support substrate <NUM>, and a light-emitting layer <NUM> provided on the driving layer <NUM>.

The support substrate <NUM> may not be a substrate for growth but may be a substrate for supporting the driving layer <NUM> thereon. For example, a silicon substrate, a glass substrate, a sapphire substrate, or a silicon substrate coated with SiO<NUM> may be used as the support substrate <NUM>. The driving layer <NUM> may include a driving device <NUM> for electrically driving the light-emitting layer <NUM> for each sub-pixel. The driving device <NUM> may include, for example, a transistor, a TFT or an HEMT. For example, the driving device <NUM> may include a gate electrode G, a source electrode S, and a drain electrode D. The driving layer <NUM> may further include at least one insulating layer. For example, at least one insulating layer may include a first insulating layer <NUM> and a second insulating layer <NUM>. The second insulating layer <NUM> may be, for example, a gate oxide. A third insulating layer <NUM> may be further provided between the driving layer <NUM> and the light-emitting layer <NUM>.

A bonding layer <NUM> may be provided between the support substrate <NUM> and the driving layer <NUM>. The bonding layer <NUM> is for bonding the driving layer <NUM> to the support substrate <NUM>, and may include, for example, an adhesive layer or a direct bonding layer.

The light-emitting layer <NUM> includes a micro light-emitting device array, for example, a micro LED array. The light-emitting layer <NUM> includes the first light-emitting unit <NUM> that emits light of a first wavelength, for example, blue light, the second light-emitting unit <NUM> that emits light of a second wavelength, for example, green light, and the third light-emitting unit <NUM> that emits light of a third wavelength, for example, red light. The first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM> are the same as those described with reference to <FIG>, so detailed descriptions thereof will not be given herein, and reference numerals of the light-emitting units follow <FIG>. In <FIG>, reference numerals of the elements in the light-emitting units are omitted. In <FIG>, the light-emitting layer <NUM> is arranged in the reverse direction of the structure shown in <FIG>.

The light-emitting layer <NUM> may have an isolation structure <NUM> such that light from each of the active layers of the first light-emitting unit <NUM>, the second light-emitting unit <NUM>, and the third light-emitting unit <NUM> is emitted in sub-pixel units. That is, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be defined by the isolation structure <NUM>.

The first electrode <NUM> electrically connected to each of the second semiconductor layer <NUM>, a third semiconductor layer <NUM>, and a fourth semiconductor layer <NUM> is provided, and a second electrode <NUM> electrically connected to a first semiconductor layer <NUM> may be provided. The first electrode <NUM> may be a pixel electrode, and the second electrode <NUM> may be a common electrode. When the second, third, and fourth semiconductor layers <NUM>, <NUM>, and <NUM> include a p-type semiconductor, the first electrode <NUM> is a p-type electrode, and when the first semiconductor layer <NUM> includes an n-type semiconductor, the second electrode <NUM> may be an n-type electrode.

The second electrode <NUM> may be formed as a transparent electrode or an opaque electrode. The transparent electrode may include, for example, ITO, ZnO, IZO, or IGZO. When the second electrode <NUM> is an opaque electrode, the second electrode <NUM> may further include a window area <NUM> such that light emitted from each active layer may be transmitted. The window area <NUM> may be provided at a position corresponding to each active layer. When the second electrode <NUM> is formed as a transparent electrode, the second electrode <NUM> may be arranged to cover the entire first semiconductor layer <NUM> without a window area.

Because blue light, green light, and red light are emitted from the first, second, and third sub-pixels SP1, SP2, and SP3, respectively, and the amount of light is controlled by the amount of current injected into the first electrode <NUM> and the second electrode <NUM> in the present disclosure, a color image may be displayed. In the present embodiment, because a color image may be displayed without a color conversion layer or a color filter layer, it is possible to increase light efficiency and increase the efficiency of a manufacturing process.

<FIG> are views for explaining a method of manufacturing a micro light-emitting display apparatus according to an example embodiment.

Referring to <FIG>, a first layer <NUM> is formed on a first semiconductor layer <NUM>. The first semiconductor layer <NUM> may include an n-type semiconductor layer. However, in some cases, the first semiconductor layer <NUM> may include a p-type semiconductor layer. For example, the first semiconductor layer <NUM> may include n-type GaN. The first layer <NUM> is a layer for forming an active layer, and may include, for example, GaN. A second semiconductor layer <NUM> is formed on the first layer <NUM>. The second semiconductor layer <NUM> may include, for example, a p-type semiconductor layer. The second semiconductor layer <NUM> may include, for example, p-type GaN.

According to an example embodiment, an electron blocking layer <NUM> may be further formed between the first layer <NUM> and the second semiconductor layer <NUM>. The electron blocking layer <NUM> may include, for example, AlGaN. According to an example embodiment, the second semiconductor layer <NUM> is formed on the electron blocking layer <NUM>.

Referring to <FIG>, an isolation structure <NUM> is formed in the first layer <NUM>, the electron blocking layer <NUM>, and the second semiconductor layer <NUM> by using a mask. The mask is an ion implantation mask. The isolation structure <NUM> is formed by implanting ions into certain areas of the first layer <NUM> and the second semiconductor layer <NUM>. According to an example embodiment, the isolation structure <NUM> is formed by implanting ions into certain areas of the first layer <NUM>, the electron blocking layer <NUM>, and the second semiconductor layer <NUM>. Ions may include, for example, N ions, B ions, Ar ions, or P ions. However, ions are not limited thereto. A thickness of the isolation structure <NUM> may vary. The isolation structure <NUM> includes a first isolation structure 425a having a first width A1 and a second isolation structure 425b having a second width A2. The second width A2 is greater than the first width A1.

A plurality of first active layers 415A that are spaced apart from each other by the isolation structure <NUM>, are formed. Further, a plurality of second semiconductor layers 420a that are spaced apart from each other by the isolation structure <NUM> are formed. Each of the plurality of first active layers 415A and each of the plurality of second semiconductor layers 420a provided apart from each other may define a sub-pixel area. Each of the plurality of first active layers 415A may include a multi-quantum well structure in which InGaN layers and GaN layers are alternately stacked. The isolation structure <NUM> may form a micro light-emitting structure array, for example, a micro LED array.

Referring to <FIG>, a second layer <NUM> is deposited on the second semiconductor layers 420a and the isolation structure <NUM>. The second layer <NUM> may be formed through a photoresist and etching process. The second layer <NUM> may include, for example, an insulating material. The second layer <NUM> may function as a current blocking layer. The second layer <NUM> is patterned so that a first area <NUM> of the second isolation structure 425b is exposed.

Referring to <FIG>, a regrowth area <NUM> may be formed by etching the exposed first area <NUM> of the second isolation structure 425b. The regrowth area <NUM> may be formed to a depth penetrating the second isolation structure 425b.

Referring to <FIG>, a semiconductor layer <NUM> is regrown in the regrowth area <NUM>. The semiconductor layer <NUM> may include, for example, the same material as the material of the first semiconductor layer <NUM>. The semiconductor layer <NUM> may include, for example, n-type GaN. A thickness of a central portion of the semiconductor layer <NUM> may be greater than that of a peripheral portion according to a difference in growth rate. The semiconductor layer <NUM> may have a sharp central portion.

Referring to <FIG>, the semiconductor layer <NUM> is planarized or flattened to form a rod semiconductor layer 450A. The semiconductor layer <NUM> may be planarized by etching, for example, with an etching solution of KOH or TMAH. In addition, the planarized semiconductor layer may be regrown to form the rod semiconductor layer 450A. By regrowing the planarized semiconductor layer, a plane may be formed on an upper surface of the rod semiconductor layer 450A. The rod semiconductor layer 450A may have, for example, a truncated pyramid shape. However, the shape of the rod semiconductor layer 450A is not limited thereto, and as such, according to another example embodiment, the rod semiconductor layer 450A may have a different shape. Because the rod semiconductor layer 450A is substantially the same as the configuration described with reference to <FIG>, a detailed description thereof will not be given herein.

Referring to <FIG>, a second active layer <NUM> is formed on the rod semiconductor layer 450A, and a third semiconductor layer <NUM> is formed on the second active layer <NUM>. The second active layer <NUM> may have an MQW structure or an SQW structure. The second active layer <NUM> may include a III-V group semiconductor, for example, GaN. The second active layer <NUM> may have a GaN/InGaN multiple quantum well structure. For example, the second active layer <NUM> may include a multi-quantum well structure in which InGaN layers and GaN layers are alternately stacked. The second active layer <NUM> may be configured to emit green light by adjusting, for example, the uniformity of the composition and thickness of In. In the second active layer <NUM>, the uniformity of the composition and thickness of In is increased through a planarization process and a regrowth process, thereby reducing an FWHM of a wavelength of green light and emitting green light with high purity.

The third semiconductor layer <NUM> may include a p-type semiconductor. The third semiconductor layer <NUM> may include a III-V group p-type semiconductor, for example, p-GaN. The third semiconductor layer <NUM> may have a single layer structure or a multilayer structure.

After the third semiconductor layer <NUM> is formed, the second layer <NUM> may be patterned to expose plurality of second areas <NUM> in which the plurality of first active layers 415A is formed.

Referring to <FIG>, a conductive material may be deposited on the structure illustrated in <FIG> and then, through etching, a plurality of first electrodes <NUM> spaced apart from each other in sub-pixel units may be formed. A first electrode <NUM> may be a pixel electrode that operates in sub-pixel units. The first electrode <NUM> may include a reflective conductive material. The first electrode <NUM> may include, for example, silver (Ag), gold (Au), aluminum (Al), chromium (Cr), or nickel (Ni), or an alloy thereof. The first electrode <NUM> may be an opaque electrode.

In this way, the plurality of first electrodes <NUM> apart from each other may be formed in areas corresponding to the first active layer 415A and the second active layer <NUM>. Accordingly, a light-emitting unit in sub-pixel units may be formed.

When sub-pixels are electrically separated by the isolation structure <NUM> by ion implantation, by deactivating an edge portion of an active layer where defects may exist through ion implantation, light emission may be induced only inside the active layer. In addition, local contrast deterioration may be prevented by electrically separating pixels (sub-pixels) by an ion implantation area. The local contrast deterioration may be caused by light being emitted to unintended adjacent pixels (sub-pixels) at a pixel (sub-pixel) interface of a horizontal mesa-free structure in which no structural separation between pixels (sub-pixels) is performed. However, according to an example embodiment, current spreading to adjacent pixels (sub-pixels) may be prevented by a mesa-free isolation structure, thereby improving contrast.

Referring to <FIG>, a first insulating layer <NUM> may be formed to cover the plurality of first electrodes <NUM>. The first insulating layer <NUM> may include, for example, silicon oxide (SiO<NUM>), silicon nitride (SiN), aluminum oxide (Al<NUM>O<NUM>), or titanium oxide (TiO<NUM>), but is not limited thereto.

Referring to <FIG>, the first insulating layer <NUM> may be etched and deposited with a conductive material to form a via <NUM> and an electrode pad <NUM>. The via <NUM> may contact the first electrode <NUM>.

Referring to <FIG>, a second insulating layer <NUM> may be formed on the first insulating layer <NUM> and a gate electrode <NUM> may be formed on the second insulating layer <NUM>. In addition, a third insulating layer <NUM> may be formed on the second insulating layer <NUM> and the gate electrode <NUM>. A source electrode <NUM> and a drain electrode <NUM> may be formed by etching the second insulating layer <NUM> and the third insulating layer <NUM>. The gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> may constitute a driving device. A method of forming a TFT as an example of the driving device has been described. The source electrode <NUM> may be connected to the electrode pad <NUM>, and the drain electrode <NUM> may be connected to the via <NUM>. Accordingly, a driving layer <NUM> may be formed.

Referring to <FIG>, the structure shown in <FIG> may be turned over so that the first semiconductor layer <NUM> is facing upward, and the structure may be arranged on a substrate <NUM> so that the third insulating layer <NUM> faces the substrate <NUM>. The substrate <NUM> is to support the structure shown in <FIG>, and, for example, a silicon substrate, a glass substrate, a sapphire substrate, or a silicon substrate coated with SiO<NUM> may be used. However, this is merely exemplary, and various materials that are easy to combine with a third insulating layer <NUM> may be used. Referring to <FIG>, the substrate <NUM> and the third insulating layer <NUM> may be combined by a bonding layer <NUM>. The bonding layer <NUM> may include, for example, an adhesive layer or a direct bonding layer. The substrate <NUM> does not require electrical connection and is for supporting a structure, and the substrate <NUM> and the structure may be physically bonded to each other by simple bonding. The bonding layer <NUM> may have a thickness, for example, in a range of about <NUM> to about <NUM>.

Referring to <FIG>, a second electrode <NUM> may be formed on the first semiconductor layer <NUM> by an etching process. The second electrode <NUM> may be a common electrode. The second electrode <NUM> may be formed, for example, as an opaque electrode. In the case of an opaque electrode, a window area <NUM> may be formed by etching the second electrode <NUM> to allow light to exit. Alternatively, the second electrode <NUM> may be formed as a transparent electrode. When the second electrode <NUM> is a transparent electrode, it is not necessary to form a window area. Meanwhile, before forming the second electrode <NUM>, a process of planarizing the first semiconductor layer <NUM> by a polishing process may be further added.

Referring to <FIG>, a color conversion layer <NUM> may be formed on the second electrode <NUM>.

A layer is applied to the second electrode <NUM> and etched to form a plurality of partitions <NUM>, and a first color conversion layer <NUM>, a second color conversion layer <NUM>, and a third color conversion layer <NUM> may be formed respectively in the areas partitioned by the plurality of partitions <NUM>.

The first, second, and third color conversion layers <NUM>, <NUM>, and <NUM> may be provided corresponding to the first, second, and third sub-pixels SP1, SP2, and SP3, respectively. The first, second, and third color conversion layers <NUM>, <NUM>, and <NUM> may include, for example, a blue conversion layer, a green conversion layer, and a red conversion layer, respectively.

As described above, a display apparatus according to an example embodiment may be manufactured. According to a method of manufacturing a display apparatus according to an example embodiment, a driving layer and a light-emitting layer may be formed in a monolithic manner. Further, according to the method of manufacturing a display apparatus according to an example embodiment, a vertical electrode structure without a mesa structure may be formed through a flip manufacturing process. The manufacturing process may be simplified by reducing a via hole etching process for forming an electrode, and because there is no mesa structure, a decrease in internal quantum efficiency due to a mesa structure may be prevented.

Meanwhile, in the present embodiment, the method of monolithically forming the light-emitting layer and the Thin Film Transistor (TFT) driving layer has been described, but it is also possible to manufacture a display apparatus by forming a light-emitting layer and bonding the light-emitting layer to a complementary metal-oxide semiconductor (CMOS) backplane.

<FIG> are views for explaining a method of manufacturing a micro light-emitting display apparatus according to another embodiment.

An electron blocking layer <NUM> may be further formed between the first layer <NUM> and the second semiconductor layer <NUM>. The electron blocking layer <NUM> may include, for example, AlGaN.

Referring to <FIG>, an isolation structure <NUM> is formed in the first layer <NUM>, the electron blocking layer <NUM>, and the second semiconductor layer <NUM> by using a mask. The mask is an ion implantation mask. The isolation structure <NUM> is formed by implanting ions into certain areas of the first layer <NUM> and the second semiconductor layer <NUM>. The isolation structure <NUM> includes a first isolation structure 525a having a first width B1 and a second isolation structure 525b having a second width B2. The second width B2 is greater than the first width B1.

A plurality of first active layers 515A, spaced apart from each other by the isolation structure <NUM>, are formed. Further, a plurality of second semiconductor layers 520a spaced apart from each other are formed by the isolation structure <NUM>. Each of the plurality of first active layers 515A and each of the plurality of second semiconductor layers layer 520a provided apart from each other may define a sub-pixel area. Each of the plurality of first active layers 515A may include a multi-quantum well structure in which InGaN layers and GaN layers are alternately stacked. The isolation structure <NUM> may form a micro light-emitting structure array, for example, a micro LED array.

Referring to <FIG>, a second layer <NUM> is deposited on the second semiconductor layers 520a and the isolation structure <NUM>. The second layer <NUM> may be formed through a photoresist and etching process. The second layer <NUM> may include, for example, an insulating material. The second layer <NUM> may function as a current blocking layer. The second layer <NUM> is patterned so that a first area <NUM> and a second area <NUM> of the second isolation structure 525b are exposed. The first area <NUM> may be an area where a rod semiconductor layer is to be formed, and the second area <NUM> may be an area where a nano rod semiconductor layer is to be formed. The second area <NUM> may have a plurality of groove structures 536a formed in the second layer <NUM>. The second area <NUM> may have a width of, for example, a nanometer size.

Referring to <FIG>, a first regrowth area <NUM> is formed by etching the exposed first area <NUM> of the second isolation structure 525b. The first regrowth area <NUM> may be formed to a depth penetrating the second isolation structure 525b. Furthermore, a second regrowth area <NUM> may be formed by etching the second area <NUM> of the second isolation structure 525b. The second regrowth area <NUM> may include a plurality of areas spaced apart from each other by the isolation structure <NUM>.

Referring to <FIG>, a semiconductor layer <NUM> is regrown in the first regrowth area <NUM>. In addition, a semiconductor layer <NUM> may be regrown in a second regrowth area <NUM>. The semiconductor layers <NUM> and <NUM> may include, for example, the same material as the material of the first semiconductor layer <NUM>. The semiconductor layers <NUM> and <NUM> may include, for example, n-type GaN. A thickness of a central portion of the semiconductor layers <NUM> and <NUM> may be greater than that of a peripheral portion according to a difference in growth rate.

Referring to <FIG>, the semiconductor layer <NUM> may be planarized to form a rod semiconductor layer 550A. In addition, the semiconductor layer <NUM> may be planarized to form a nanorod semiconductor layer 552A. The semiconductor layers <NUM> and <NUM> may be planarized by etching with, for example, an etching solution of KOH or TMAH. Because the rod semiconductor layer 550A and the nano rod semiconductor layer 552A are substantially the same as those described with reference to <FIG> and <FIG>, respectively, a detailed description thereof will not be given herein.

Referring to <FIG>, a second active layer <NUM> may be formed on the rod semiconductor layer 550A, and a third semiconductor layer <NUM> may be formed on the second active layer <NUM>. The second active layer <NUM> may have an MQW structure or an SQW structure. For example, the second active layer <NUM> may include a multi-quantum well structure in which InGaN layers and GaN layers are alternately stacked. The second active layer <NUM> may be configured to emit green light by adjusting, for example, the uniformity of composition and thickness of In.

A third active layer <NUM> may be formed on the nanorod semiconductor layer 552A, and a fourth semiconductor layer <NUM> may be formed on the third active layer <NUM>.

The third semiconductor layer <NUM> and the fourth semiconductor layer <NUM> may include a p-type semiconductor. The third semiconductor layer <NUM> and the fourth semiconductor layer <NUM> may include a III-V group p-type semiconductor, for example, p-GaN.

After the third semiconductor layer <NUM> and the fourth semiconductor layer <NUM> are formed, the second layer <NUM> may be patterned to expose a plurality of third areas <NUM> in which the first active layers 515A are formed.

Referring to <FIG>, a conductive material may be deposited on the structure illustrated in <FIG> and then, through etching, first electrodes <NUM> spaced apart from each other in sub-pixel units may be formed. A first electrode <NUM> may be a pixel electrode that operates in sub-pixel units. The first electrode <NUM> may include a reflective conductive material. The first electrode <NUM> may include, for example, Ag, Au, Al, Cr, or Ni, or an alloy thereof. The first electrode <NUM> may be an opaque electrode.

In this way, the first electrodes <NUM> apart from each other may be formed in areas corresponding to the first active layer 515A, the second active layer <NUM>, and the third active layer <NUM>. Accordingly, a light-emitting unit in sub-pixel units may be formed.

Referring to <FIG>, a driving layer for driving a light emitting unit may be combined to the structure shown in <FIG>. In <FIG>, the process of forming the driving layer <NUM> on the structure shown in <FIG> is substantially the same as those described with reference to <FIG>, and thus a detailed description thereof will not be given herein. In <FIG>, components using the same reference numerals as in <FIG> may have substantially the same configuration and function as those described with reference to <FIG>. The structure shown in <FIG> may be turned over so that the first semiconductor layer <NUM> is upward, and the structure may be arranged on the substrate <NUM> so that the third insulating layer <NUM> faces the substrate <NUM>.

In addition, a second electrode <NUM> may be formed on the first semiconductor layer <NUM> by an etching process. The second electrode <NUM> may be a common electrode. The second electrode <NUM> may be formed, for example, as an opaque electrode. In the case of an opaque electrode, a window area <NUM> may be formed by etching the second electrode <NUM> to allow light to exit. Alternatively, the second electrode <NUM> may be formed as a transparent electrode. When the second electrode <NUM> is a transparent electrode, it is not necessary to form a window area.

In the present embodiment, blue light may be emitted from the first active layer 515A, green light may be emitted from the second active layer <NUM>, and red light may be emitted from the third active layer <NUM>. Accordingly, a color image may be displayed using each of the color lights emitted from the first active layer 515A, the second active layer <NUM>, and the third active layer <NUM>. In the present embodiment, it is not necessary to separately provide a color conversion layer. Therefore, it is possible to simplify a method of manufacturing a micro light-emitting display apparatus.

Meanwhile, a method of manufacturing a display apparatus according to an example embodiment may provide a method of manufacturing a mesa-free flip.

The micro light-emitting display apparatus according to the above-described embodiments may be applied to display apparatuses of various sizes and uses without limitation. For example, <FIG> show example applications of various display apparatuses. As shown in <FIG>, a micro light-emitting display apparatus according to various embodiments may be applied to a head mounted display (HMD) <NUM>. As shown in <FIG>, the micro light-emitting display apparatus according to various embodiments may be applied to a small display panel used in a glasses-type display or a goggle-type display <NUM>. As shown in <FIG>, the micro light-emitting display apparatus may be applied to a display panel of a television, a smart television, or a computer <NUM>. As shown in <FIG>, the micro light-emitting display apparatus according to various embodiments may be applied to a display panel of a mobile phone or a smart phone <NUM>. As shown in <FIG>, the micro light-emitting display apparatus according to various embodiments may be applied to a display panel of a tablet or a smart tablet <NUM>.

In addition, the micro light-emitting display apparatus according to various embodiments may be applied to a display panel of a laptop computer <NUM> as shown in <FIG>, and may also be applied to a large display panel used in signage <NUM>, a large electronic signboard, a theater screen, and the like as shown in <FIG>.

Although the micro light-emitting display apparatus according to various embodiments and the method of manufacturing the same has been described with reference to the embodiments shown in the drawings, they are only examples. The scope of rights is indicated in the claims rather than the above description, and all differences within the scope of the claims should be construed as being included in the scope of rights.

An example embodiment may implement a display that displays a high-resolution color image using a micro light-emitting device. A display apparatus according to an example embodiment may simplify the display apparatus by using a micro light-emitting structure that directly displays a green color without converting blue light into green light.

In a method of manufacturing a micro light-emitting device according to an example embodiment, a light-emitting structure that is separated by sub-pixel units through an isolation structure and emits green light or red light through regrowth of a semiconductor layer may be manufactured.

Claim 1:
A micro light-emitting display apparatus comprising:
a first semiconductor layer (<NUM>);
an isolation structure (<NUM>) comprising an ion implantation area, provided on the first semiconductor layer and configured to define a plurality of sub-pixels (SP1, SP2) each configured to emit light;
a first light-emitting unit (<NUM>) including a first active layer (<NUM>) provided on the upper surface of the first semiconductor layer in a first sub-pixel among the plurality of sub-pixels, and a second semiconductor layer (<NUM>) provided on the first active layer; and
a second light-emitting unit (<NUM>) including a rod semiconductor layer (<NUM>) formed by regrowth from the first semiconductor layer in a regrowth area etched from the isolation structure (<NUM>) and provided in a second sub-pixel among the plurality of sub-pixels, a second active layer (<NUM>) provided on the rod semiconductor layer, and a third semiconductor layer (<NUM>) provided on the second active layer,
wherein the first active layer is configured to emit blue light and the second active layer is configured to emit green light.