Patent Description:
Finding the local minimum of a transistor circuit which has a transfer characteristic with a local minimum may be achieved by sweeping the gate source voltage and measuring the source drain current through the transistor circuit. This allows to find the specific gate source voltage where the current is minimum. It would be advantageous if the time for finding this specific voltage could be reduced.

An example of such a transistor circuit is a graphene FET which has a local minimum at the Dirac voltage. <CIT> discloses a device and method wherein a semiconductor device is used for generating a test voltage. A graphene transistor is configured to receive a gate-source voltage based on the test voltage, and a detector is configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor. The detector therefore detects whether the graphene transistor is turned off or not based on the drain source voltage and/or the drain source current. Also in this case if would be advantageous if the time for finding the specific voltage (in this case the Dirac voltage) could be reduced.

There is therefore a need for an alternative system for determining the local minimum of a transistor circuit which has a transfer characteristic with a local minimum.

<CIT> discloses a semiconductor device including a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

It is an object of embodiments of the present invention to provide a system for determining the local minimum of a transistor circuit which has a transfer characteristic with a local minimum.

The above objective is accomplished by a system according to the present invention as defined in claim <NUM>.

Embodiments of the present invention relate to a system for characterizing a transistor circuit.

The transistor circuit comprises a gate, a source, and a drain, and is configured such that a drain source current versus gate source voltage transfer function has a local minimum for a specific voltage.

The system is configured for measuring this specific voltage, and comprises:.

A first integrator, of the one or more integrators, is configured for integrating the electrical signal from the multiplier, and if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators.

The system, moreover, comprises a summator configured for summing the toggling signal and an integration signal, or a processed version thereof, wherein the integration signal is obtained by linearly combining outputs of the one or more integrators and configured for outputting the sum to the gate of the transistor circuit.

In embodiments of the present invention the transistor circuit comprises:.

The first slope and the second slope have opposite signs.

If the first voltage converter is configured for converting the voltage at the source of the first transistor then the transistor circuit, furthermore, may comprise a third voltage converter. This third voltage converter is configured for applying a voltage at the drain of the first transistor such that a stable drain-source voltage is obtained for the first transistor.

If the second voltage converter is configured for converting the voltage at the source of the second transistor then the transistor circuit, furthermore, may comprise a fourth voltage converter. The fourth voltage converter is configured for applying a voltage at the drain of the second transistor such that a stable drain-source voltage is obtained for the second transistor.

In embodiments of the present invention the first transistor or the second transistor is exposable to and sensitive for a chemical component.

In embodiments of the present invention the first transistor and the second transistor are metal-oxide-semiconductor FET or bipolar transistors.

In embodiments of the present invention the transistor circuit is a graphene FET.

In embodiments of the present invention the system comprises a sample and hold circuit for sampling and holding the integration signal for obtaining the processed version of the integration signal.

In embodiments of the present invention the system comprises exactly one integrator.

In embodiments of the present invention the system comprises exactly two integrators wherein an input signal of the second integrator is the sum of an output signal of the first integrator and an output signal of the second integrator multiplied with a predefined constant a<NUM>.

In embodiments of the present invention the predefined bias voltage is such that the sum obtained by the summator is inside a quadratic region of the transistor circuit characteristic.

In embodiments of the present invention the predefined bias voltage is such that the sum obtained by the summator is in a linear region of the transistor circuit characteristic.

In embodiments of the present invention, in a first stage the predefined bias voltage may be such that the sum obtained by the summator is in a linear region of the transistor circuit characteristic and in a second stage the predefined bias voltage may be such that the sum obtained by the summator is inside a quadratic region of the transistor circuit characteristic.

In embodiments of the present invention the system comprises a quantizer configured for quantizing the integrator signal at a predefined sampling frequency, and a digital to analog converter for converting the quantized signal into an analog signal for summing with the toggling signal at the summator.

In embodiments of the present invention the digital to analog converter is toggling between a first predefined reference voltage for a digital zero input and a second predefined reference voltage for a digital one input wherein the first and second reference voltages and the predefined bias voltage are selected such that toggling with the predefined bias voltage results in a voltage in the left linear region and a voltage in the right linear region of said transistor circuit.

In embodiments of the present invention the digital to analog converter is toggling between a first predefined reference voltage for a digital zero input and a second predefined reference voltage for a digital one input. The first reference voltage and the predefined bias voltage are selected such that toggling with the predefined bias voltage results in a voltage in the left part of a quadratic region and a voltage in the same left part of said quadratic region. The second reference voltage and the predefined bias voltage are selected such that toggling with the predefined bias voltage results in a voltage in the right part of said quadratic region and a voltage in the same right part of said quadratic region of said transistor circuit.

In embodiments of the present invention the quantizer is a multi-bit quantizer with a predefined number of Nq bits, wherein the digital to analog converter has Nq bits.

Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as set out in the claims.

Where in embodiments of the present invention reference is made to the quadratic region of a transistor circuit, reference is made to the region wherein the current vs. gate characteristic can be approximated by a second order curve.

Where in embodiments of the present invention reference is made to the linear region of a transistor circuit, reference is made to the region wherein the current vs. gate characteristic can be approximated by two linear functions.

Embodiments of the present invention relate to a system <NUM> for characterizing a transistor circuit which comprises a gate, a source, and a drain. The transistor circuit is configured such that a drain source current in function of a gate source voltage transfer function has a local minimum for a specific voltage. The system <NUM> is configured for measuring the specific voltage.

Exemplary embodiments of such systems <NUM> are shown in <FIG>, <FIG>, <FIG>, and <FIG>.

A system in accordance with embodiments of the present invention comprises:.

In embodiments of the present invention the gate voltage or the source voltage may be toggled in order to get a toggling of the gate source voltage corresponding with said toggling signal. When toggling the source voltage, the drain voltage might be toggled simultaneously such that the drain source voltage remains stable. Toggling the source voltage may be advantageous for a common gate operation. In such a configuration the common gates of one or more transistor circuits may be kept at a fixed potential and the feedback voltage (i.e. the sum of the toggling signal and the integration signal or a processed version thereof) may be applied to the source. A version of said feedback voltage should then also be applied to the drain simultaneously such that a stable drain source voltage is obtained. Also this is of advantage for a common gate operation. When toggling the source voltage without toggling the drain voltage, instability in the drain source voltage may be compensated for by post processing in order to remove errors due to instability in the drain source voltage.

It is an advantage of embodiments of the present invention that from the integration signal or from the processed version of the integration signal the specific voltage related to the local minimum of the transfer function of the transistor circuit can be obtained.

A system <NUM> according to embodiments of the present invention may comprise different types of transistor systems. The inventors have found a particular transistor circuit, in accordance with embodiments of the present invention, which may be used for detecting and/or quantifying a chemical component such as for example bio-molecules or ions. The transistor circuit may be sensitive to chemical components of different kinds (e.g. different types of bio molecules or different kinds of ions).

In the field of sensing a field effect transistor (FET) may be used with a gate electrode that is sensitive to one or more chemical components. When exposing the gate electrode to a liquid or a gas, that contains the one or more chemical components, these one or more chemical components interact with the gate electrode in a certain way, so that the FET changes its electrical characteristics as for example the drain source current Ids which is a function f of the gate source voltage VGS and the drain source voltage VDS: IDS = f (VDS, VGS).

The usual approach is, that an initial function of IDS = f1 (VDS, VGS) is either known or either measured before the transistor is exposed to the media.

After the exposure to the media and the interaction of the molecules to be detected with the gate, the relationship between VDS, VGS and IDS is modified into IDS = f2 (VDS, VGS). It was observed by the inventors that in most cases f2 is shifted compared to f1.

In the classic approach the shift between f2 compared to f1 is measured and analyzed. This is time consuming and requires some complex hardware / software efforts. The left drawing of <FIG> shows a classic n-channel field effect transistor with gate G, source S, and drain D terminals. The right graph shows the drain source current Ids in function of the gate source voltage VGS (IDS= f(VGS)) characteristic. At a given bias point Vb, a drain source current in function of the bias voltage can be derived IDS = f(Vb).

The inventors have found that by combining the transistors in a transistor circuit the drain source current of this transistor circuit in function of the gate source voltage has a local minimum.

An example thereof is illustrated in <FIG>. The transistor circuit <NUM> comprises a first transistor <NUM> and a second transistor <NUM> with shared sources forming the source of the transistor circuit <NUM> and with shared drains forming the drain of the transistor circuit <NUM>. A first voltage converter <NUM> converts a voltage at the gate of the transistor circuit <NUM>, according to a transfer function with a first slope, into a voltage at the gate of the first transistor <NUM>, and a second voltage converter <NUM> converts a voltage at the gate of the transistor circuit <NUM>, according to a transfer function with a second slope, into a voltage at the gate of the second transistor <NUM>. The first slope and the second slope have opposite signs.

Alternatively the first voltage converter <NUM> and the second voltage converter <NUM> may respectively be connected to the source of the first transistor <NUM> and the source of the second transistor <NUM> for creating the gate source voltage. An example thereof is illustrated in <FIG>. In that case, additionally, the transistor circuit may comprise a third voltage converter <NUM>' and a fourth voltage converter <NUM>' respectively connected with the drain of the first transistor <NUM> and the drain of the second transistor <NUM> for driving the drains with a version of the signals on the source of the first and second transistor in order to achieve a constant drain source voltage of the first transistor and a constant drain source voltage of the second transistor, so that a stable drain source current can be obtained. Also this is of advantage for a constant gate operation under consideration of the two-transistor-circuit.

Keeping the drain source voltage constant is not strictly necessary. A system in accordance with embodiments of the present invention may also work accepting some modulation of the drain source voltage. This would cause a shift in the detected minimum conduction point but in different applications this is acceptable. Users may for example be interested in the drift before and after exposure to a target chemical and the measured drift accepting drain source voltage modulation may be the same as the actual voltage drift of the specific voltage (e.g. Dirac voltage). In embodiments of the present invention the system may be configured for post processing of the found minimum to compensate for the changes in the drain source voltage.

The transistor circuit <NUM> of <FIG> may be sensitive to any type of exposure. The two transistors may be transistors of the same kind. They may for example be two n-channel transistors (as it is shown in the schematic drawing), they may for example also be two p-channel transistors, two depletion transistors, or two zero threshold voltage transistors.

The transistors may for example be characterized by a threshold voltage Vth, that can be positive, negative, or even zero.

In embodiments of the present invention the transistors have a nonlinear current versus control voltage characteristic with a quadratic term in the polynomial expansion of their I=f(V) characteristics in the neighborhood of the operating point Vb. Any transistors may be used. They could also be bipolar transistors or MOSFET transistors, which can also be used in their subthreshold (<Vth) ranges.

The first voltage converter <NUM> converts a voltage VGS at the gate of the transistor circuit into a voltage at the gate of the first transistor <NUM> using the following formula: <MAT>.

This function defines the operating point of the first transistor at the minimum conduction point (gate voltage Vb) occurring at the control voltage VGS=Vd. The voltage VGS1 applied between the gate and the source of the first transistor is increasing with the control voltage VGS according to a given slope (G).

The second voltage converter <NUM> converts a voltage VGS at the gate of the transistor circuit into a voltage at the gate of the second transistor <NUM> using the following formula: <MAT>.

The voltage VGS2 applied between the gate and the source of the second transistor is decreasing with the control voltage VGS according to the opposite slope or gain factor (-G).

The drain source current of the first transistor is shown in <FIG> and is a function of the gate source voltage and is expressed as Ids = f(T1). Because of the first voltage converter it has a positive slope. The drain source current of the second transistor is shown in <FIG> and is a function of the gate source voltage and is expressed as Ids = f(T2). Because of the second voltage converter it has a negative slope. The traces are mirrored in the vertical direction for the nonexposed transistors as they are in their initial state.

The drain source current for both transistors together is the sum of the drain source currents of each transistor and is expressed as Ids=f(T1, T2). This final trace of the transistor circuit is characterized in that the current has a local minimum and the current is of a quadratic nature around that minimum.

This local minimum will be shifted to other positions than Vd if the voltage current characteristic of one of the transistors is shifted. This may for example occur when the first transistor or the second transistor is exposable to and sensitive for a chemical component. When exposing the sensitive transistor to the chemical component (e.g. a biomolecule, or an ion) this will result in a shift of the transfer function and therefore also in a shift of the local minimum. It is an advantage that the specific voltage of this minimum can be measured using a system in accordance with embodiments of the present invention.

One of the transistors in <FIG> may be exposable to and sensitive for a chemical component while the other transistor is not exposed to the chemical component. The chemical component may be present in a given medium such as a liquid, a gel, or a gas.

In the transistor circuit illustrated in <FIG> the transistors may for example also be graphene transistors wherein both transistors are exposed to the medium, but only one transistor is for example functionalized to be more sensitive for a given kind of chemical components (e.g. biomolecules) and the other one is not.

In embodiments of the present invention also a single graphene field effect transistor (GFET) can be used as transistor circuit <NUM> (see inset in <FIG>). The reason therefore being that a single GFET has a local minimum in its current voltage characteristic. In that case the specific gate source voltage at which the drain source current is at a local minimum is the Dirac voltage of the GFET. Using a system, in accordance with embodiments of the present invention, the GFET is integrated inside a closed loop-system acting as a low-pass filter which delivers an output voltage equal to the Dirac voltage of the GFET. The loop can be a sigma-delta modulator delivering a digital value of the Dirac voltage. In embodiments of the present invention the Dirac voltage is shifted during exposure of the GFET to a chemical component to which it is sensitive.

If in the transistor circuit illustrated in <FIG> two graphene transistors are used, one exposed and the other one not, or one functionalized and the other one not, this will result in an overlay of two non linear functions which both have a Dirac point and of which the combination has a common Dirac point. This common Dirac point will be shifted during exposure when the exposure changes the electrical characteristic of the exposed graphene transistor. This is not illustrated in the right graph of <FIG> which instead shows the current voltage characteristics of normal MOS transistors. In embodiments of the present invention with a transistor circuit as illustrated in <FIG>, both transistors might generate a transfer function which in case of a MOS transistor can for example be approximated by a <NUM>nd order in the neighborhood of the minimum conduction point: <MAT> <MAT>.

The minimum conduction point is shifted if an electrical characteristic of one of the transistors is modified. This could be I<NUM>, a<NUM>, and/or b<NUM> if the transistor T<NUM> is exposed.

These equations and the equations below are valid when the transistors are MOS transistors. Similar equations can be derived if two GFETs are used.

In the particular case of MOS transistors biased in strong inversion, with Vth1 and Vth2 the threshold voltages of the transistors, the following Ids=f(VGS) characteristics can be derived: <MAT> <MAT>.

In embodiments of the present invention the transistor circuit may be configured such that the minimum conduction point of the system before exposure with identical matched transistors is set at gate voltage VGS=Vd=<NUM>. Then the following equation can be derived: <MAT>.

The minimum conduction point is shifted if the gain a<NUM> or the threshold Vth2 is modified, if the transistor T<NUM> would for instance be exposed to a chemical component.

The specific voltage at the minimum conduction point VGSmc can be obtained by calculating the first derivative of Ids in the equation above and equating this derivative to zero resulting in: <MAT>.

A transistor circuit as shown in <FIG> will have a local minimum (minimum conduction point) at a specific voltage. When one of the transistors is sensitive and exposed to the chemical component the specific voltage changes.

It is an advantage that this specific voltage can be obtained using a system <NUM> in accordance with embodiments of the present invention which comprises this transistor circuit.

In embodiments of the present invention the transistors of the transistor circuit may be chemical sensitive transistors (CHEMFETs), or ion sensitive transistors (ISFETS), but also graphene transistors (GFETs) in a differential approach. New application fields might be supported as well, for what graphene transistors are for instance not sensitive enough, e.g. measurements at very high temperature or harsh media.

In embodiments of the present invention the first transistor or the second transistor is exposable to and sensitive for a chemical component. In embodiments of the present invention only one of the transistors is exposable and this one is sensitive to the chemical component.

In embodiments of the present invention the first transistor and the second transistor are exposable to a chemical component and only one is sensitive for the chemical component. For example in the case of two (graphene) transistors, only one may be functionalized and the other one not, while both are exposed.

In embodiments of the present invention only one of the first transistor or the second transistor is exposable to a chemical component and the first transistor and the second transistor are sensitive for the chemical component. For example both transistors may be identical (e.g. two identical chemFETs) and only one is exposed to the chemical component.

<FIG> shows the MIT model <NUM> of a GFET. The model was presented in "Mackin, C. (<NUM>) Graphene chemical and biological sensors: Modeling, systems, and applications. PhD thesis at the Massachusetts Institute of Technology". <FIG> shows a fitting <NUM> by a simple linear and quadratic approximation.

Around the Dirac point (Vd), the current vs. gate voltage characteristic can be approximated by a <NUM>nd order curve: <MAT>.

Moving away from the Dirac point, the characteristic becomes more linear and can be approximated by <NUM> lines: <MAT> <MAT>.

The junctions between the <NUM> parts are made at gate voltages Vd - V<NUM> and Vd + V<NUM>. At those points, IDS = IDS<NUM> = IDS<NUM> + α (V<NUM>)<NUM> and the slope (transconductance) is <NUM> a V<NUM>.

In a system according to embodiments of the present invention wherein the transistor circuit <NUM> is a GFET, an analog low-pass filter loop automatically adjusts the gate voltage to the Dirac point. The advantage of this approach is that a low-noise, high-resolution measurement of the Dirac point can be obtained in approximately the same time as the cited prior art systems would take for each single step of their gate voltage ramp. In embodiments of the present invention a simple analog circuit / digital circuit can be used what results in a low energy consumption.

A system <NUM> for measuring a specific voltage (e.g. Dirac voltage) of transistor circuit <NUM> (e.g. a graphene field effect transistor or a transistor circuit as in <FIG>) according to embodiments of the present invention comprises the transistor circuit <NUM>, and a bias voltage generator <NUM> configured for generating a toggling signal, toggling between plus and minus a predefined bias voltage vG around a given bias point. The bias point is thus the average level of the toggling signal generated by the bias voltage generator. The given bias point may for example be zero volt. The invention is, however, not limited thereto. The given bias point may also be different from zero.

The system <NUM>, moreover, comprises a multiplier <NUM> configured for generating an electrical signal by multiplying an electrical signal which is a function of the drain source current of the transistor circuit (e.g. a channel current IDS of e.g. a graphene field effect transistor <NUM>, or the sum of the currents IDS through the transistors T1 and T2 in the circuit of <FIG>), with a waveform alternating between two predefined values +A and -A which alternates synchronously with the toggling signal. Depending on the frequency of the toggling gate voltage and the characteristic of the transistor circuit (frequency response), the alternating waveform applied to the multiplier could thereby be delayed (phase shifted) with respect to the gate voltage toggling signal. The predefined value A may for example be equal to <NUM>. The invention is, however, not limited thereto. Also other values of A are possible. The factor A is a multiplication factor for the signal to be integrated. This signal can be the drain current of the transistor circuit (e.g. the GFET drain current), a multiplication of the drain current, the output of a trans-impedance amplifier and is referred to as the transistor circuit signal. This signal is integrated by an integrator which also has a gain factor. In embodiments of the present invention A is selected such that the product of all multiplication factors applied to the transistor circuit signal do not lead to saturation of the first integrator at any time. This total gain factor impacts the loop bandwidth and stability. The feedback or feedforward factors are preferably chosen to achieve the desired bandwidth and stability taking into account the transistor circuit characteristic and all multiplicative factors involved in the integration of the transistor circuit signal. In an exemplary embodiment of the present invention A may for example be in a range between <NUM> and <NUM>.

The system <NUM>, moreover, comprises one or more integrators <NUM> wherein a first integrator <NUM>, of the one or more integrators <NUM>, is configured for integrating the electrical signal from the multiplier <NUM>, and wherein if more integrators <NUM> are present, linear combinations of output signals of the integrators are provided to the further integrators <NUM>.

The system <NUM>, moreover, comprises a summator <NUM> configured for summing the toggling signal of the bias voltage generator <NUM> and an integration signal, or a processed version thereof, wherein the integration signal is obtained by linearly combining outputs of the one or more integrators <NUM>.

In embodiments of the present invention the integration signal may be sampled before the toggling from -A to +A (or from +A to -A) of the toggling signal applied to the multiplier and held for one full period of the toggling signal applied to the multiplier (same frequency as the toggling voltage applied to the gate but possible delay) so until the next toggling from -A to +A (or from +A to -A). The invention is, however, not limited thereto. A sample and hold circuit is not strictly required and if a sample and hold circuit is present, the sample moment may be selected different as specified above.

In embodiments of the present invention the last integrator in the loop may be implemented with a switched-capacitor circuit for providing the sample and hold functionality.

In such a system, according to embodiments of the present invention, a loop is formed. In order for the loop to converge to a stable gate voltage at the specific voltage at the local minimum, the low-pass filter loop has to integrate a quantity that is <NUM> when the gate voltage is at the specific voltage and which has a linear dependency on the gate voltage in the neighborhood of the specific voltage.

In the vicinity of the specific voltage, the current vs. gate voltage characteristic is a <NUM>nd-order curve so its derivative is a linear function of the gate voltage which is null at the local minimum of the current.

The loop could therefore process the quantity ΔIDS(VG) = IDS(VG + vG) - IDS(VG - vG) where vG is the predefined bias voltage so that the current difference can be expressed using the derivative of the current at VG: <MAT>.

The system therefore has to process the difference between <NUM> current measurements performed at slightly different gate voltages. Those current measurements have to be performed in sequence. The gate voltage (VGS also referred to as VGate) applied to the transistor circuit can be periodically toggled between VG + vG and VG - vG and the difference can be computed inside the integrator by inverting the integrated current when VG - vG is applied to the gate: <MAT> <MAT> <MAT> <MAT> <MAT> M(t) is a square wave oscillating between A=+<NUM> and -A=-<NUM> with period T and <NUM>% duty-cycle.

This integration of the drain source current of the transistor circuit is illustrated in <FIG>. A basic first order measurement loop of a system for measuring the specific voltage at the local minimum (e.g. the Dirac voltage in case the transistor circuit is a GFET), in accordance with embodiments of the present invention is illustrated in <FIG>. It shows the transistor circuit <NUM> (represented by its characteristic graph with local minimum in the current voltage characteristic), the bias voltage generator <NUM>, the first integrator <NUM>, the multiplier <NUM>, and the summator <NUM>. In this example the bias point of the bias voltage generator is <NUM> and as a result thereof the integration signal will in this example be the specific voltage corresponding with the local minimum. If the bias point is different from zero, the integration signal will be the specific voltage minus the bias point.

The integrator integrates the difference between <NUM> transistor circuit currents corresponding to <NUM> different gate voltages in order to integrate the slope of the current vs. gate voltage characteristic rather than the current itself.

The basic loop illustrated in <FIG> forms a <NUM>st order linear system of which the block diagram is shown in <FIG>.

The loop can be extended up to any order. In embodiments of the present invention the system comprises exactly two integrators wherein an input signal of the second integrator is the sum of an output signal of the first integrator and an output signal of the second integrator multiplied with a predefined constant a<NUM>. An example thereof is illustrated in <FIG>. It shows the transistor circuit <NUM> (this may for example be a GFET or a transistor circuit as illustrated in <FIG>), the bias voltage generator <NUM>, the first integrator 130a, the second integrator 130b, the multiplier <NUM>, the summator <NUM>, a multiplier <NUM> for multiplying an output signal of the second integrator 130b with a predefined constant a<NUM>, and a summator <NUM> for summing the output signal of the first integrator 130a and the output signal of the second integrator 130b.

The corresponding block diagram of the second order system is illustrated in <FIG>. In this block diagram K1 holds the product multiplication factors like a possible trans-impedance factor, the amplitude of the multiplication waveform (A) and the capacitor used in the implementation of the of the continuous time integrator. K2 holds the time-constant of the second continuous time integrator.

In embodiments of the present invention the system has a predefined bias voltage modulation which is small enough such that the modulation is inside the quadratic region of the transistor circuit characteristic (e.g. GFET characteristic).

The linear system description is valid when the predefined bias voltage vG > <NUM> V<NUM> and the gate voltages involved in the difference IDS(VG + vG) - IDS(VG - vG) are located in both linear regions of the transistor circuit characteristic: VG - vG ≤ Vd - V<NUM> and VG + vG ≥ Vd + V<NUM>.

The difference with respect to the previous case is that the gain is <NUM> a V<NUM> instead of <NUM> α vG.

Using a large gate voltage modulation allows to search for the specific voltage over a large gate voltage range.

In embodiments of the present invention the loop can be implemented with continuous time integrator or discrete-time integrators.

The following Matlab simulation results show the behavior of the described <NUM>nd-order system for which the transistor circuit is a GFET. The MIT model <NUM> used for the GFET has a Dirac point at Vd = <NUM> V. The approximation <NUM> described in the document has the following parameters: α = <NUM> A/V<NUM>, V<NUM> = <NUM> V, IDS<NUM> = <NUM> µA. These parameters are the parameters for the model in <FIG>.

A first loop was constructed with <NUM> bandwidth approximately. The predefined bias voltage was +/- <NUM>. 2V (i.e. large gate voltage modulation) at <NUM>. The loop parameters were calculated considering the gain value <NUM> α V<NUM>. The simulation results in <FIG> and <FIG> show that the output of the filter reaches the Dirac voltage in less than <NUM> (see <FIG>). There is +/- 1mV residual oscillation at <NUM> (see <FIG> which is a zoomed-in version of <FIG> between <NUM> and <NUM> V). <FIG> shows the frequency response of the second order system.

The following simulation results show a second loop design with the same bandwidth of <NUM> but using a predefined bias voltage vG of <NUM>. 01V (i.e. small gate voltage modulation) instead of <NUM>. The loop parameters were calculated considering the gain value <NUM> α vG. The integrator time constants are therefore different from the ones used with the larger bias voltage. The plot in <FIG> shows the settling at the output of the second order system with a small gate voltage modulation. The correct value is reached within <NUM> starting from discharged integrators. The loop first operates outside the quadratic GFET current region where the current difference ΔIDS(VG) = -<NUM> α V<NUM> is constant instead of being proportional to VG. The loop only starts working when VG enters the quadratic region. This is further explained in the paragraph below.

The residual oscillation of the second order system with <NUM> bandwidth and small gate voltage modulation at <NUM> has 2mV amplitude. This is illustrated in <FIG> which shows a zoomed-in version of <FIG> between <NUM> and <NUM> V.

The oscillations can be reduced with a smaller filter bandwidth. <FIG> and <FIG> show the results for a loop with less than <NUM> bandwidth and large gate signal modulation. The filter settles within <NUM> with <NUM> µV residual oscillation. <FIG> shows the frequency response of the <NUM>nd-order system with <NUM> bandwidth and large gate voltage modulation. <FIG> shows a Matlab simulation result illustrating the settling of the <NUM>-bandwidth, <NUM>nd-order system with large gate voltage modulation. <FIG> shows a Matlab simulation result illustrating the residual oscillation at the output of the <NUM>-bandwidth, <NUM>nd-order system with large gate voltage modulation. The residual oscillation can be reduced by introducing the sample and hold circuit. It is, however, not strictly required.

In embodiments of the present invention the system <NUM> comprises a quantizer <NUM> which is configured for quantizing the integrator signal at a predefined sampling frequency. The system <NUM>, moreover, comprises a digital to analog converter <NUM> for converting the quantized signal into an analog signal for summing with the toggling signal at the summator <NUM>.

Thus, the low-pass filter loop is converted into sigma-delta modulator. This is possible because of the linear relationship between the current difference, ΔIDS, and the gate voltage.

<FIG> shows a schematic diagram of an exemplary system for measuring the specific voltage corresponding with the local minimum of the current of a transistor circuit (this may for example be a GFET), comprising a <NUM>nd-order sigma-delta ADC, in accordance with embodiments of the present invention.

The system <NUM> of <FIG> comprises the transistor circuit <NUM>, a bias voltage generator <NUM>, a digital to analog converter <NUM>, a summator <NUM> for summing the signal from the bias voltage generator <NUM> and the signal from the digital to analog converter <NUM>. The output of the summator <NUM> is connected to the gate of the transistor circuit <NUM>. The system <NUM> furthermore comprises a waveform generator <NUM> configured for generating a waveform alternating between +A and -A, and a multiplier <NUM> configured for multiplying the waveform of the waveform generator with an electrical signal which is a function of a channel current of e.g. the GFET or the resulting sum of the two channel currents of the both transistors of the transistor circuit <NUM>. The system, furthermore, comprises a first integrator 130a for integrating the signal from the multiplier <NUM> and a second integrator 130b for integrating the sum, obtained using a summator <NUM>, of the signal from the first integrator 130a and the quantized output of the second integrator multiplied with a predefined factor a1 using a multiplier <NUM>. The system, furthermore, comprises a <NUM>-bit quantizer for quantizing the output signal of the second integrator 130b. The system, furthermore, comprises a decimation filter <NUM> at the output of the quantizer.

In the exemplary embodiment illustrated in <FIG>, instead of smoothly adjusting the gate voltage to the specific voltage (e.g. Dirac point in case of e.g. a GFET), the sigma-delta loop toggles the gate voltage VG between <NUM> fixed voltages, Vref<NUM> and Vref<NUM>, within the region of validity of the linear relationship between the current difference and the gate voltage. The output of the <NUM>-bit quantizer is, therefore, connected to a switch of the digital to analog converter <NUM> which switches between Vref<NUM> and Vref<NUM> and connects them alternatingly to the summator <NUM>.

The transistor circuit <NUM> is then operated at <NUM> possible different voltages only: Vref<NUM> ± vG and Vref<NUM> ± vG, wherein vG is the predefined voltage of the bias voltage generator <NUM>. Those will generate only <NUM> different values for the current difference: <MAT> <MAT>.

In order for a linear relationship to be valid, the gate voltages must be chosen as follows. If one uses a small gate voltage modulation (i.e. within the quadratic region of the transistor circuit), vG, all <NUM> gate voltages have to be in the central quadratic part of the transistor circuit characteristic. In embodiments of the present invention small vG signal modulation is used in the quadratic region so that at the first predefined voltage, the gate voltage is toggling between <NUM> levels both at the left side of the specific voltage (the gate voltage is smaller than the specific voltage Vd) and at the second predefined voltage, both levels will be at the right side of the specific voltage (the gate voltage is larger than the specific voltage Vd).

In order for a linear relationship to be valid, if one uses a large gate voltage modulation (i.e. within the linear region of the transistor circuit), vG, all <NUM> gate voltages have to be outside the central quadratic part of the transistor circuit characteristic:.

In embodiments of the present invention the sigma-delta loop is sampling at the gate voltage modulation frequency ( <MAT>). This is illustrated by the sampling trigger signal <NUM> in <FIG>. The sigma-delta loop delivers a bit stream alternating between <NUM> and <NUM>. Let D be the ratio between the number of <NUM> and the total number of bits in the bit stream.

The sigma delta loop will adjust D such that the average of ΔIDS is <NUM>. ΔIDS thereby is proportional to the slope of the transistor circuit IDS vs. VGS characteristic and becomes <NUM> at the specific voltage. The sigma-delta modulator generates its feedback signal such that the quantity that is integrated by the integrator is <NUM> in average.

Supposing large gate voltage modulation: <MAT> IDS = <NUM>, therefore: <MAT> <MAT> <MAT>.

The invention is not limited to sigma-delta modulators of the second order. Also sigma delta modulators of different orders may be used.

In embodiments of the present invention the integrators can be continuous-time or discrete-time integrators.

A Matlab simulation of an exemplary system, in accordance with embodiments of the present invention and illustrated in <FIG>, applied to the GFET described by the MIT model has been executed. The Dirac point is at <NUM>. 61V and the limit of the quadratic region is V<NUM> = <NUM> V.

If the converter is able to make accurate conversions over the full reference voltage range, from Vref<NUM> to Vref<NUM>, the system is able to measure a Dirac voltage for a GFET or the voltage for a minimum IDS of the both Ts in a transistor circuit <NUM> (i.e. the specific voltage of the transistor circuit) in the range from Vref<NUM> to Vref<NUM>.

If the system is operated with a large gate modulation, the following conditions have to be fulfilled:.

Therefore, in this exemplary embodiment of the present invention, the predefined bias voltage, also referred to as the modulation voltage, vG must meet the following condition: <MAT>.

For the simulation, the following values have been used: Vref<NUM> = <NUM> V, Vref<NUM> = <NUM> V and vG = <NUM>. The sample frequency Fs = <NUM> kHz. In embodiments of the present invention the system comprises a decimation filter. The decimation filter may for example be a sinc3 filter with an over-sampling rate of <NUM>.

In view of the values given above, the GFET is operated at the following gate voltages: <MAT> <MAT> <MAT> <MAT>.

It can be seen on the plot of <FIG> that those values are at the limit of the linear approximation. In the plot the drain current is shown in function of the drain current for the accurate model <NUM> and the approximation <NUM>. The output of the decimation filter gives a Dirac point measurement at <NUM>.

<FIG> shows the output of the decimation filter converted to voltage. The output of the filter settles within <NUM>*<NUM> samples corresponding to a settling time of <NUM>.

<FIG> shows a plot zoomed to the settled output of the decimation filter.

In an alternative embodiment of the present invention the reference voltages may be selected closer to the actual Dirac voltage. The following values may for example be selected: Vref<NUM> = <NUM> V, Vref<NUM> = <NUM> V and vG = <NUM>. In this example the GFET is operated at <NUM> gates voltages where the linear approximation holds better which yields a better estimation of the Dirac point. This is illustrated in <FIG> which shows a plot zoomed to the settled output of the decimation filter for the values cited above.

In embodiments of the present invention the quantizer <NUM> is a multi-bit quantizer with a predefined number of Nq bits, wherein the digital to analog converter <NUM> has Nq bits. An exemplary embodiment of such a system is shown in <FIG>. The schematic diagram is similar to the schematic in <FIG> except for the fact that the quantizer is a Nq bits quantizer and the digital to analog converter <NUM> has Nq bits.

The multi-bit approach allows to search for the specific voltage in a wide range. In embodiments of the present invention the initial settling of the loop will take care of the initial guess of the specific voltage and eventually, the DAC will toggle between <NUM> or <NUM> levels only.

In embodiments of the present invention the multi-bit quantizer inside the sigma-delta loop is a low-resolution ADC. In embodiments of the present invention it is not just converting the output of the current integrator but a linear combination of the outputs of several integrators. In the example the output voltage of the second integrator is converted.

In embodiments of the present invention the output of the low-resolution multi-bit quantizer is directly connected to the low-resolution DAC without any processing by a control circuit configured to determine a voltage value applied to a control electrode of the control circuit.

As explained earlier the linear relationship between the current differences ΔIDS and the <NUM> reference voltages Vref<NUM>, Vref<NUM> must be valid in order for the single-bit sigma-delta to deliver the correct value for the Dirac voltage.

The reference voltages can be extended beyond the regions of validity of the linear relationship if a multi-bit quantizer is used in the sigma-delta loop.

Instead of feeding back only <NUM> different gate voltages at the extremes of the [Vref<NUM>; Vref<NUM>] range, the loop will feedback <NUM>Nq different possible DAC voltages which are uniformly spread over the range [Vref<NUM>; Vref<NUM>], Nq being the number of bits of the quantizer used inside the loop. After some settling time, the loop will automatically converge to a situation where the feedback gate voltage will toggle between a few of those possible feedback voltages only, all being located in the neighborhood of the specific voltage. In embodiments of the present invention the number of bits of the quantizer is chosen such that the several consecutive DAC voltages are inside the region of validity of the linear relationship between the current difference and the gate voltage.

In the following simulation the transistor circuit is a GFET. The following simulation illustrates the operation of a multi-bit sigma-delta with small gate voltage modulation (vG = 5mV) able to give a digital code for the Dirac voltage in the range from 0V to 1V using a <NUM>-bit quantizer and a <NUM>-level DAC. The GFET model is the same as before. For small gate modulation, the current difference is linear vs. the gate voltage in the gate voltage range [Vd - <NUM> ; Vd + <NUM>]. The DAC step is 1V/<NUM> = <NUM> mV so that <NUM> or <NUM> DAC levels are inside that gate voltage range.

<FIG> shows a plot of the decimation filter output in function of the sample number. <FIG> shows a zoom to the output of the decimation filter. <FIG> shows the <NUM>-bit quantizer output in function of the sample number.

With a small vG modulation signal, preferably there are several consecutive DAC voltages inside the quadratic region of the GFET IDS vs. VG characteristic so that the slope (the quantity that is integrated) is proportional to the applied gate voltage. That is the condition to form a linear feedback system and have an accurate measurement of the Dirac voltage as the successive DAC voltages. Indeed several DAC voltage outputs Vdac+/-vG are preferably in the quadratic region.

Note that the system will likely start in the linear region where the slope is constant. At that moment, there will be no actual feedback but the integrators will make the DAC voltage go to the direction of the Dirac voltage. It is only when the DAC voltage enters the curved part of the characteristic that there will be an actual feedback signal and that the loop will settle. The closer to a <NUM>nd order characteristic, the more accurate the measurement of the Dirac point.

Claim 1:
A system (<NUM>) for characterizing a transistor circuit (<NUM>) which comprises a gate, a source, and a drain, wherein the transistor circuit is configured such that a drain source current versus gate source voltage transfer function has a local minimum for a specific voltage, wherein the system is configured for measuring the specific voltage, the system comprising:
- the transistor circuit (<NUM>),
- a bias voltage generator (<NUM>) configured for generating a toggling signal, toggling between plus and minus a predefined bias voltage vG around a given bias point,
- one or more integrators (<NUM>),
- a multiplier (<NUM>) configured for generating an electrical signal by multiplying an electrical signal which is a function of the drain source current of the transistor circuit (<NUM>), with a waveform alternating between two predefined values plus and minus A which alternates synchronously with the toggling signal,
- wherein a first integrator (<NUM>), of the one or more integrators (<NUM>), is configured for integrating the electrical signal from the multiplier (<NUM>), and wherein if more integrators (<NUM>) are present, linear combinations of output signals of the integrators are provided to the further integrators (<NUM>),
- a summator (<NUM>) configured for summing the toggling signal and an integration signal, or a processed version thereof, wherein the integration signal is obtained by linearly combining outputs of the one or more integrators (<NUM>) and configured for outputting the sum as gate source voltage of the transistor circuit.