Patent Description:
Ray tracing is a technique in which a light transport is simulated through physically-based rendering. Widely used in cinematic rendering, it was considered too resource-intensive for real-time performance until just a few years ago. One of the key operations in ray tracing is processing a visibility query for ray-scene intersections known as "ray traversal" which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH).

The publication by <NPL> introduces a deep learning approach for denoising Monte Carlo-rendered images that produces high-quality results suitable for production. The approach consists in training a convolutional neural network to learn the complex relationship between noisy and reference data across a large set of frames with varying distributed effects from a film. The trained network can then be applied to denoise new images from other films with significantly different style and content with production-quality results.

In the publication by <NPL>, a generative adversarial network (GAN) for image superresolution (SR) is disclosed wherein a complex mapping between low-resolution (LR) and high-resolution (HR) image information is used for training to relate example-pairs on LR training patches for which the corresponding HR counterparts are known.

Advantageous embodiments are described by the dependent claims.

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings. The embodiments and examples in <FIG> are not according to the claimed invention and are present for illustration purposes only.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention can be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

<FIG> is a block diagram of a processing system <NUM>, according to an embodiment. In various embodiments the system <NUM> includes one or more processors <NUM> and one or more graphics processors <NUM>, and is a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors <NUM> or processor cores <NUM>. In one embodiment, the system <NUM> is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

The system <NUM> can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. The system <NUM> is a mobile phone, smart phone, tablet computing device or mobile Internet device. The processing system <NUM> can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. The processing system <NUM> is a television or set top box device having one or more processors <NUM> and a graphical interface generated by one or more graphics processors <NUM>.

Instruction set <NUM> may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW).

The processor <NUM> includes cache memory <NUM>. The cache memory is shared among various components of the processor <NUM>. The processor <NUM> also uses an external cache (e.g., a Level-<NUM> (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores <NUM> using known cache coherency techniques.

In some embodiments, one or more processor(s) <NUM> are coupled with one or more interface bus(es) <NUM> to transmit communication signals such as address, data, or control signals between processor <NUM> and other components in the system <NUM>. The interface bus <NUM> can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. The processor(s) <NUM> include an integrated memory controller <NUM> and a platform controller hub <NUM>. The memory controller <NUM> facilitates communication between a memory device and other components of the system <NUM>, while the platform controller hub (PCH) <NUM> provides connections to I/O devices via a local I/O bus.

The memory device <NUM> can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. The memory device <NUM> can operate as system memory for the system <NUM>, to store data <NUM> and instructions <NUM> for use when the one or more processors <NUM> executes an application or process. Memory controller <NUM> also couples with an optional external graphics processor <NUM>, which may communicate with the one or more graphics processors <NUM> in processors <NUM> to perform graphics and media operations. A display device <NUM> can connect to the processor(s) <NUM>. The display device <NUM> can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). The display device <NUM> can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

The platform controller hub <NUM> enables peripherals to connect to memory device <NUM> and processor <NUM> via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller <NUM>, a network controller <NUM>, a firmware interface <NUM>, a wireless transceiver <NUM>, touch sensors <NUM>, a data storage device <NUM> (e.g., hard disk drive, flash memory, etc.). The data storage device <NUM> can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The touch sensors <NUM> can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver <NUM> can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a <NUM>, <NUM>, or Long Term Evolution (LTE) transceiver. The firmware interface <NUM> enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller <NUM> can enable a network connection to a wired network. A high-performance network controller (not shown) couples with the interface bus <NUM>. The audio controller <NUM> is a multi-channel high definition audio controller. The system <NUM> includes an optional legacy I/O controller <NUM> for coupling legacy (e.g., Personal System <NUM> (PS/<NUM>)) devices to the system. The platform controller hub <NUM> can also connect to one or more Universal Serial Bus (USB) controllers <NUM> connect input devices, such as keyboard and mouse <NUM> combinations, a camera <NUM>, or other USB input devices.

It will be appreciated that the system <NUM> shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller <NUM> and platform controller hub <NUM> may be integrated into a discreet external graphics processor, such as the external graphics processor <NUM>. The platform controller hub <NUM> and/or memory controller <NUM> may be external to the one or more processor(s) <NUM>. For example, the system <NUM> can include an external memory controller <NUM> and platform controller hub <NUM>, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s) <NUM>.

<FIG> is a block diagram of an embodiment of a processor <NUM> having one or more processor cores 202A-202N, an integrated memory controller <NUM>, and an integrated graphics processor <NUM>. Those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor <NUM> can include additional cores up to and including additional core 202N represented by the dashed lined boxes. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. Each processor core also has access to one or more shared cached units <NUM>.

The internal cache units 204A-204N and shared cache units <NUM> represent a cache memory hierarchy within the processor <NUM>. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level <NUM> (L2), Level <NUM> (L3), Level <NUM> (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. Cache coherency logic maintains coherency between the various cache units <NUM> and 204A-204N.

Processor <NUM> may also include a set of one or more bus controller units <NUM> and a system agent core <NUM>. The one or more bus controller units <NUM> manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core <NUM> provides management functionality for the various processor components. System agent core <NUM> includes one or more integrated memory controllers <NUM> to manage access to various external memory devices (not shown).

One or more of the processor cores 202A-202N include support for simultaneous multi-threading. The system agent core <NUM> includes components for coordinating and operating cores 202A-202N during multi-threaded processing. System agent core <NUM> may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 202A-202N and graphics processor <NUM>.

In some embodiments, processor <NUM> additionally includes graphics processor <NUM> to execute graphics processing operations. The graphics processor <NUM> couples with the set of shared cache units <NUM>, and the system agent core <NUM>, including the one or more integrated memory controllers <NUM>. The system agent core <NUM> also includes a display controller <NUM> to drive graphics processor output to one or more coupled displays. Display controller <NUM> may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor <NUM>.

A ring based interconnect unit <NUM> is used to couple the internal components of the processor <NUM>. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. Graphics processor <NUM> couples with the ring interconnect <NUM> via an I/O link <NUM>.

The exemplary I/O link <NUM> represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module <NUM>, such as an eDRAM module. Each of the processor cores 202A-202N and graphics processor <NUM> use embedded memory modules <NUM> as a shared Last Level Cache.

Processor cores 202A-202N are homogenous cores executing the same instruction set architecture. Processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. Processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor <NUM> can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

<FIG> is a block diagram of a graphics processor <NUM>, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. The graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. Graphics processor <NUM> includes a memory interface <NUM> to access memory. Memory interface <NUM> can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

Graphics processor <NUM> also includes a display controller <NUM> to drive display output data to a display device <NUM>. Display controller <NUM> includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device <NUM> can be an internal or external display device. The display device <NUM> is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. Graphics processor <NUM> includes a video codec engine <NUM> to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-<NUM>, Advanced Video Coding (AVC) formats such as H. <NUM>/MPEG-<NUM> AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) <NUM>/VC-<NUM>, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

Graphics processor <NUM> includes a block image transfer (BLIT) engine <NUM> to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) <NUM>. GPE <NUM> is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

GPE <NUM> includes a 3D pipeline <NUM> for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline <NUM> includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system <NUM>. While 3D pipeline <NUM> can be used to perform media operations, an example of GPE <NUM> also includes a media pipeline <NUM> that is specifically used to perform media operations, such as video post-processing and image enhancement.

Media pipeline <NUM> includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine <NUM>. Media pipeline <NUM> additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system <NUM>. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system <NUM>.

3D/Media subsystem <NUM> includes logic for executing threads spawned by 3D pipeline <NUM> and media pipeline <NUM>. The pipelines send thread execution requests to 3D/Media subsystem <NUM>, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. 3D/Media subsystem <NUM> includes one or more internal caches for thread instructions and data. The subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

<FIG> is a block diagram of a graphics processing engine <NUM> of a graphics processor in accordance with some embodiments. The graphics processing engine (GPE) <NUM> is a version of the GPE <NUM> shown in <FIG>. Elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline <NUM> and media pipeline <NUM> of <FIG> are illustrated. The media pipeline <NUM> is optional in some examples of the GPE <NUM> and may not be explicitly included within the GPE <NUM>. For example, a separate media and/or image processor is coupled to the GPE <NUM>.

GPE <NUM> couples with or includes a command streamer <NUM>, which provides a command stream to the 3D pipeline <NUM> and/or media pipelines <NUM>. Command streamer <NUM> is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. Command streamer <NUM> receives commands from the memory and sends the commands to 3D pipeline <NUM> and/or media pipeline <NUM>. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline <NUM> and media pipeline <NUM>. The ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline <NUM> can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline <NUM> and/or image data and memory objects for the media pipeline <NUM>. The 3D pipeline <NUM> and media pipeline <NUM> process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array <NUM>. The graphics core array <NUM> include one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

The 3D pipeline <NUM> includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array <NUM>. The graphics core array <NUM> provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s) 415A-414B of the graphic core array <NUM> includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

The graphics core array <NUM> also includes execution logic to perform media functions, such as video and/or image processing. The execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) <NUM> of <FIG> or core 202A-202N as in <FIG>.

Output data generated by threads executing on the graphics core array <NUM> can output data to memory in a unified return buffer (URB) <NUM>. The URB <NUM> can store data for multiple threads. The URB <NUM> may be used to send data between different threads executing on the graphics core array <NUM>. The URB <NUM> may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic <NUM>.

Graphics core array <NUM> is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE <NUM>. The execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

The graphics core array <NUM> couples with shared function logic <NUM> that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic <NUM> are hardware logic units that provide specialized supplemental functionality to the graphics core array <NUM>. Shared function logic <NUM> includes but is not limited to sampler <NUM>, math <NUM>, and inter-thread communication (ITC) <NUM> logic. Additionally, some examples implement one or more cache(s) <NUM> within the shared function logic <NUM>.

A shared function is implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array <NUM>. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic <NUM> and shared among the execution resources within the graphics core array <NUM>. The precise set of functions that are shared between the graphics core array <NUM> and included within the graphics core array <NUM> varies. Specific shared functions within the shared function logic <NUM> that are used extensively by the graphics core array <NUM> may be included within shared function logic <NUM> within the graphics core array <NUM>. The shared function logic <NUM> within the graphics core array <NUM> can include some or all logic within the shared function logic <NUM>. All logic elements within the shared function logic <NUM> may be duplicated within the shared function logic <NUM> of the graphics core array <NUM>. The shared function logic <NUM> is excluded in favor of the shared function logic <NUM> within the graphics core array <NUM>.

<FIG> is a block diagram of hardware logic of a graphics processor core <NUM>, according to some embodiments described herein. Elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The illustrated graphics processor core <NUM> is included within the graphics core array <NUM> of <FIG>. The graphics processor core <NUM>, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor core <NUM> is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core <NUM> can include a fixed function block <NUM> coupled with multiple sub-cores 501A-501F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

The fixed function block <NUM> includes a geometry/fixed function pipeline <NUM> that can be shared by all sub-cores in the graphics processor core <NUM>, for example, in lower performance and/or lower power graphics processor implementations. The geometry/fixed function pipeline <NUM> includes a 3D fixed function pipeline (e.g., 3D pipeline <NUM> as in <FIG> and <FIG>) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers, such as the unified return buffer <NUM> of <FIG>.

The fixed function block <NUM> also includes a graphics SoC interface <NUM>, a graphics microcontroller <NUM>, and a media pipeline <NUM>. The graphics SoC interface <NUM> provides an interface between the graphics processor core <NUM> and other processor cores within a system on a chip integrated circuit. The graphics microcontroller <NUM> is a programmable sub-processor that is configurable to manage various functions of the graphics processor core <NUM>, including thread dispatch, scheduling, and pre-emption. The media pipeline <NUM> (e.g., media pipeline <NUM> of <FIG> and <FIG>) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline <NUM> implement media operations via requests to compute or sampling logic within the sub-cores <NUM>-501F.

The SoC interface <NUM> enables the graphics processor core <NUM> to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface <NUM> can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics processor core <NUM> and CPUs within the SoC. The SoC interface <NUM> can also implement power management controls for the graphics processor core <NUM> and enable an interface between a clock domain of the graphic core <NUM> and other clock domains within the SoC. The SoC interface <NUM> enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline <NUM>, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline <NUM>, geometry and fixed function pipeline <NUM>) when graphics processing operations are to be performed.

The graphics microcontroller <NUM> can be configured to perform various scheduling and management tasks for the graphics processor core <NUM>. The graphics microcontroller <NUM> can perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arrays 502A-502F, 504A-504F within the sub-cores 501A-501F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics processor core <NUM> can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. The graphics microcontroller <NUM> can also facilitate low-power or idle states for the graphics processor core <NUM>, providing the graphics processor core <NUM> with the ability to save and restore registers within the graphics processor core <NUM> across low-power state transitions independently from the operating system and/or graphics driver software on the system.

The graphics processor core <NUM> may have greater than or fewer than the illustrated sub-cores 501A-501F, up to N modular sub-cores. For each set of N sub-cores, the graphics processor core <NUM> can also include shared function logic <NUM>, shared and/or cache memory <NUM>, a geometry/fixed function pipeline <NUM>, as well as additional fixed function logic <NUM> to accelerate various graphics and compute processing operations. The shared function logic <NUM> can include logic units associated with the shared function logic <NUM> of <FIG> (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics processor core <NUM>. The shared and/or cache memory <NUM> can be a last-level cache for the set of N sub-cores 501A-501F within the graphics processor core <NUM>, and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline <NUM> can be included instead of the geometry/fixed function pipeline <NUM> within the fixed function block <NUM> and can include the same or similar logic units.

The graphics processor core <NUM> includes additional fixed function logic <NUM> that can include various fixed function acceleration logic for use by the graphics processor core <NUM>. The additional fixed function logic <NUM> includes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline <NUM>, <NUM>, and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic <NUM>. The cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example the cull pipeline logic within the additional fixed function logic <NUM> can execute position shaders in parallel with the main application and generally generates critical results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated critical results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase.

The additional fixed function logic <NUM> can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

Within each graphics sub-core 501A-501F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-cores 501A-501F include multiple EU arrays 502A-502F, 504A-504F, thread dispatch and inter-thread communication (TD/IC) logic 503A-503F, a 3D (e.g., texture) sampler 505A-505F, a media sampler 506A-506F, a shader processor 507A-507F, and shared local memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logic 503A-503F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D sampler 505A-505F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media sampler 506A-506F can perform similar read operations based on the type and format associated with media data. Each graphics sub-core 501A-501F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-cores 501A-501F can make use of shared local memory 508A-508F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

<FIG> illustrate thread execution logic <NUM> including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. <FIG> illustrates an overview of thread execution logic <NUM>, which can include a variant of the hardware logic illustrated with each sub-core 501A-501F of <FIG>. <FIG> illustrates exemplary internal details of an execution unit.

As illustrated in <FIG>, thread execution logic <NUM> includes a shader processor <NUM>, a thread dispatcher <NUM>, instruction cache <NUM>, a scalable execution unit array including a plurality of execution units 608A-608N, a sampler <NUM>, a data cache <NUM>, and a data port <NUM>. The scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit 608A, 608B, 608C, 608D, through 608N-<NUM> and 608N) based on the computational requirements of a workload. The included components are interconnected via an interconnect fabric that links to each of the components. Thread execution logic <NUM> includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache <NUM>, data port <NUM>, sampler <NUM>, and execution units 608A-608N. Each execution unit (e.g. 608A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. The array of execution units 608A-608N is scalable to include any number individual execution units.

The execution units 608A-608N are primarily used to execute shader programs. A shader processor <NUM> can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher <NUM>. The thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units 608A-608N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. Thread dispatcher <NUM> can also process runtime thread spawning requests from the executing shader programs.

The execution units 608A-608N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units 608A-608N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 608A-608N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays of data elements. The number of data elements is the "execution size," or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. Execution units 608A-608N support integer and floating-point data types.

The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a <NUM>-bit wide vector, the <NUM> bits of the vector are stored in a register and the execution unit operates on the vector as four separate <NUM>-bit packed data elements (Quad-Word (QW) size data elements), eight separate <NUM>-bit packed data elements (Double Word (DW) size data elements), sixteen separate <NUM>-bit packed data elements (Word (W) size data elements), or thirty-two separate <NUM>-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

One or more execution units can be combined into a fused execution unit 609A-609N having thread control logic (607A-607N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 609A-609N includes at least two execution units. For example, fused execution unit 609A includes a first EU 608A, second EU 608B, and thread control logic 607A that is common to the first EU 608A and the second EU 608B. The thread control logic 607A controls threads executed on the fused graphics execution unit 609A, allowing each EU within the fused execution units 609A-609N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., <NUM>) are included in the thread execution logic <NUM> to cache thread instructions for the execution units. One or more data caches (e.g., <NUM>) are included to cache thread data during thread execution. A sampler <NUM> is included to provide texture sampling for 3D operations and media sampling for media operations. Sampler <NUM> includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send thread initiation requests to thread execution logic <NUM> via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor <NUM> is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). A pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. Pixel processor logic within the shader processor <NUM> then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor <NUM> dispatches threads to an execution unit (e.g., 608A) via thread dispatcher <NUM>. Shader processor <NUM> uses texture sampling logic in the sampler <NUM> to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

The data port <NUM> provides a memory access mechanism for the thread execution logic <NUM> to output processed data to memory for further processing on a graphics processor output pipeline. The data port <NUM> includes or couples to one or more cache memories (e.g., data cache <NUM>) to cache data for memory access via the data port.

As illustrated in <FIG>, a graphics execution unit <NUM> can include an instruction fetch unit <NUM>, a general register file array (GRF) <NUM>, an architectural register file array (ARF) <NUM>, a thread arbiter <NUM>, a send unit <NUM>, a branch unit <NUM>, a set of SIMD floating point units (FPUs) <NUM>, and a set of dedicated integer SIMD ALUs <NUM>. The GRF <NUM> and ARF <NUM> includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit <NUM>. Per thread architectural state is maintained in the ARF <NUM>, while data used during thread execution is stored in the GRF <NUM>. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF <NUM>.

The graphics execution unit <NUM> has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads.

The graphics execution unit <NUM> can co-issue multiple instructions, which may each be different instructions. The thread arbiter <NUM> of the graphics execution unit thread <NUM> can dispatch the instructions to one of the send unit <NUM>, branch unit <NUM>, or SIMD FPU(s) <NUM> for execution. Each execution thread can access <NUM> general-purpose registers within the GRF <NUM>, where each register can store <NUM> bytes, accessible as a SIMD <NUM>-element vector of <NUM>-bit data elements. Each execution unit thread has access to <NUM> Kbytes within the GRF <NUM>, and greater or fewer register resources may be provided. Up to seven threads can execute simultaneously, although the number of threads per execution unit can also vary. In an example in which seven threads may access <NUM> Kbytes, the GRF <NUM> can store a total of <NUM> Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

Memory operations, sampler operations, and other longer-latency system communications are dispatched via "send" instructions that are executed by the message passing send unit <NUM>. Branch instructions are dispatched to a dedicated branch unit <NUM> to facilitate SIMD divergence and eventual convergence.

The graphics execution unit <NUM> includes one or more SIMD floating point units (FPU(s)) <NUM> to perform floating-point operations. The FPU(s) <NUM> also support integer computation. The FPU(s) <NUM> can SIMD execute up to M number of <NUM>-bit floating-point (or integer) operations, or SIMD execute up to <NUM> <NUM>-bit integer or <NUM>-bit floating-point operations. At least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision <NUM>-bit floating-point. A set of <NUM>-bit integer SIMD ALUs <NUM> are also present, and may be specifically optimized to perform operations associated with machine learning computations.

Arrays of multiple instances of the graphics execution unit <NUM> can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can chose the exact number of execution units per sub-core grouping. The execution unit <NUM> can execute instructions across a plurality of execution channels. In a further example, each thread executed on the graphics execution unit <NUM> is executed on a different channel.

<FIG> is a block diagram illustrating a graphics processor instruction formats <NUM> according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. Instruction format <NUM> described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

The graphics processor execution units natively support instructions in a <NUM>-bit instruction format <NUM>. A <NUM>-bit compacted instruction format <NUM> is available for some instructions based on the selected instruction, instruction options, and number of operands. The native <NUM>-bit instruction format <NUM> provides access to all instruction options, while some options and operations are restricted in the <NUM>-bit format <NUM>. The native instructions available in the <NUM>-bit format <NUM> vary. The instruction is compacted in part using a set of index values in an index field <NUM>. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the <NUM>-bit instruction format <NUM>.

For each format, instruction opcode <NUM> defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. Instruction control field <NUM> enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the <NUM>-bit instruction format <NUM> an exec-size field <NUM> limits the number of data channels that will be executed in parallel. Exec-size field <NUM> is not available for use in the <NUM>-bit compact instruction format <NUM>.

Some execution unit instructions have up to three operands including two source operands, src0 <NUM>, src1 <NUM>, and one destination <NUM>. The execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 <NUM>), where the instruction opcode <NUM> determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

The <NUM>-bit instruction format <NUM> includes an access/address mode field <NUM> specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

The <NUM>-bit instruction format <NUM> includes an access/address mode field <NUM>, which specifies an address mode and/or an access mode for the instruction. The access mode is used to define a data access alignment for the instruction. Some examples support access modes including a <NUM>-byte aligned access mode and a <NUM>-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use <NUM>-byte-aligned addressing for all source and destination operands.

The address mode portion of the access/address mode field <NUM> determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

Instructions are grouped based on opcode <NUM> bit-fields to simplify Opcode decode <NUM>. For an <NUM>-bit opcode, bits <NUM>, <NUM>, and <NUM> allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. A move and logic opcode group <NUM> includes data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic group <NUM> shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group <NUM> (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group <NUM> includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group <NUM> includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group <NUM> performs the arithmetic operations in parallel across data channels. The vector math group <NUM> includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

<FIG> is a block diagram of another example of a graphics processor <NUM>. Elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

Graphics processor <NUM> includes a geometry pipeline <NUM>, a media pipeline <NUM>, a display engine <NUM>, thread execution logic <NUM>, and a render output pipeline <NUM>. Graphics processor <NUM> is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor <NUM> via a ring interconnect <NUM>. Ring interconnect <NUM> couples graphics processor <NUM> to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect <NUM> are interpreted by a command streamer <NUM>, which supplies instructions to individual components of the geometry pipeline <NUM> or the media pipeline <NUM>.

Command streamer <NUM> directs the operation of a vertex fetcher <NUM> that reads vertex data from memory and executes vertex-processing commands provided by command streamer <NUM>. Vertex fetcher <NUM> provides vertex data to a vertex shader <NUM>, which performs coordinate space transformation and lighting operations to each vertex. Vertex fetcher <NUM> and vertex shader <NUM> execute vertex-processing instructions by dispatching execution threads to execution units 852A-852B via a thread dispatcher <NUM>.

Execution units 852A-852B are an array of vector processors having an instruction set for performing graphics and media operations. Execution units 852A-852B have an attached L1 cache <NUM> that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

Geometry pipeline <NUM> includes tessellation components to perform hardware-accelerated tessellation of 3D objects. A programmable hull shader <NUM> configures the tessellation operations. A programmable domain shader <NUM> provides back-end evaluation of tessellation output. A tessellator <NUM> operates at the direction of hull shader <NUM> and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline <NUM>. If tessellation is not used, tessellation components (e.g., hull shader <NUM>, tessellator <NUM>, and domain shader <NUM>) can be bypassed.

Complete geometric objects can be processed by a geometry shader <NUM> via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper <NUM>. The geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader <NUM> receives input from the vertex shader <NUM>. Geometry shader <NUM> is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper <NUM> processes vertex data. The clipper <NUM> may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. A rasterizer and depth test component <NUM> in the render output pipeline <NUM> dispatches pixel shaders to convert the geometric objects into per pixel representations. Pixel shader logic is included in thread execution logic <NUM>. An application can bypass the rasterizer and depth test component <NUM> and access un-rasterized vertex data via a stream out unit <NUM>.

The graphics processor <NUM> has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. Execution units 852A-852B and associated logic units (e.g., L1 cache <NUM>, sampler <NUM>, texture cache <NUM>, etc.) interconnect via a data port <NUM> to perform memory access and communicate with render output pipeline components of the processor. Sampler <NUM>, caches <NUM>, <NUM> and execution units 852A-852B each have separate memory access paths. The texture cache <NUM> can also be configured as a sampler cache.

Render output pipeline <NUM> contains a rasterizer and depth test component <NUM> that converts vertex-based objects into an associated pixel-based representation. The rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache <NUM> and depth cache <NUM> are also available. A pixel operations component <NUM> performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine <NUM>, or substituted at display time by the display controller <NUM> using overlay display planes. A shared L3 cache <NUM> is available to all graphics components, allowing the sharing of data without the use of main system memory.

Graphics processor media pipeline <NUM> includes a media engine <NUM> and a video front-end <NUM>. Video front-end <NUM> receives pipeline commands from the command streamer <NUM>. Media pipeline <NUM> includes a separate command streamer. Video front-end <NUM> processes media commands before sending the command to the media engine <NUM>. Media engine <NUM> includes thread spawning functionality to spawn threads for dispatch to thread execution logic <NUM> via thread dispatcher <NUM>.

Graphics processor <NUM> includes a display engine <NUM>. Display engine <NUM> is external to processor <NUM> and couples with the graphics processor via the ring interconnect <NUM>, or some other interconnect bus or fabric. Display engine <NUM> includes a 2D engine <NUM> and a display controller <NUM>. Display engine <NUM> contains special purpose logic capable of operating independently of the 3D pipeline. Display controller <NUM> couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

The geometry pipeline <NUM> and media pipeline <NUM> are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). Driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. Support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. Support may also be provided for the Direct3D library from the Microsoft Corporation. A combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

<FIG> is a block diagram illustrating a graphics processor command format <NUM> according to some examples. <FIG> is a block diagram illustrating a graphics processor command sequence <NUM> according to an example. The solid lined boxes in <FIG> illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format <NUM> of <FIG> includes data fields to identify a client <NUM>, a command operation code (opcode) <NUM>, and data <NUM> for the command. A sub-opcode <NUM> and a command size <NUM> are also included in some commands.

Client <NUM> specifies the client unit of the graphics device that processes the command data. A graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. The graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode <NUM> and, if present, sub-opcode <NUM> to determine the operation to perform. The client unit performs the command using information in data field <NUM>. For some commands an explicit command size <NUM> is expected to specify the size of the command. The command parser automatically determines the size of at least some of the commands based on the command opcode. Commands are aligned via multiples of a double word.

The flow diagram in <FIG> illustrates an exemplary graphics processor command sequence <NUM>. Software or firmware of a data processing system that features an example of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

The graphics processor command sequence <NUM> may begin with a pipeline flush command <NUM> to cause any active graphics pipeline to complete the currently pending commands for the pipeline. The 3D pipeline <NUM> and the media pipeline <NUM> do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked 'dirty' can be flushed to memory. Pipeline flush command <NUM> can be used for pipeline synchronization or before placing the graphics processor into a low power state.

A pipeline select command <NUM> is used when a command sequence requires the graphics processor to explicitly switch between pipelines. A pipeline select command <NUM> is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. A pipeline flush command <NUM> is required immediately before a pipeline switch via the pipeline select command <NUM>.

A pipeline control command <NUM> configures a graphics pipeline for operation and is used to program the 3D pipeline <NUM> and the media pipeline <NUM>. Pipeline control command <NUM> configures the pipeline state for the active pipeline. The pipeline control command <NUM> is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

Return buffer state commands <NUM> are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. The graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. The return buffer state <NUM> includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination <NUM>, the command sequence is tailored to the 3D pipeline <NUM> beginning with the 3D pipeline state <NUM> or the media pipeline <NUM> beginning at the media pipeline state <NUM>.

The commands to configure the 3D pipeline state <NUM> include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. 3D pipeline state <NUM> commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

3D primitive <NUM> command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive <NUM> command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive <NUM> command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. 3D primitive <NUM> command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline <NUM> dispatches shader execution threads to graphics processor execution units.

3D pipeline <NUM> is triggered via an execute <NUM> command or event. A register write triggers command execution. Execution is triggered via a 'go' or 'kick' command in the command sequence. Command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

The graphics processor command sequence <NUM> follows the media pipeline <NUM> path when performing media operations. In general, the specific use and manner of programming for the media pipeline <NUM> depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. The media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. The media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

Media pipeline <NUM> is configured in a similar manner as the 3D pipeline <NUM>. A set of commands to configure the media pipeline state <NUM> are dispatched or placed into a command queue before the media object commands <NUM>. Commands for the media pipeline state <NUM> include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. Commands for the media pipeline state <NUM> also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

Media object commands <NUM> supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. All media pipeline states must be valid before issuing a media object command <NUM>. Once the pipeline state is configured and media object commands <NUM> are queued, the media pipeline <NUM> is triggered via an execute command <NUM> or an equivalent execute event (e.g., register write). Output from media pipeline <NUM> may then be post processed by operations provided by the 3D pipeline <NUM> or the media pipeline <NUM>. GPGPU operations are configured and executed in a similar manner as media operations.

<FIG> illustrates exemplary graphics software architecture for a data processing system <NUM> according to some examples. Software architecture includes a 3D graphics application <NUM>, an operating system <NUM>, and at least one processor <NUM>. Processor <NUM> includes a graphics processor <NUM> and one or more general-purpose processor core(s) <NUM>. The graphics application <NUM> and operating system <NUM> each execute in the system memory <NUM> of the data processing system.

3D graphics application <NUM> contains one or more shader programs including shader instructions <NUM>. The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions <NUM> in a machine language suitable for execution by the general-purpose processor core <NUM>. The application also includes graphics objects <NUM> defined by vertex data.

Operating system <NUM> is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system <NUM> can support a graphics API <NUM> such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system <NUM> uses a front-end shader compiler <NUM> to compile any shader instructions <NUM> in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. High-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application <NUM>. The shader instructions <NUM> are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

User mode graphics driver <NUM> contains a back-end shader compiler <NUM> to convert the shader instructions <NUM> into a hardware specific representation. When the OpenGL API is in use, shader instructions <NUM> in the GLSL high-level language are passed to a user mode graphics driver <NUM> for compilation. User mode graphics driver <NUM> uses operating system kernel mode functions <NUM> to communicate with a kernel mode graphics driver <NUM>. Kernel mode graphics driver <NUM> communicates with graphics processor <NUM> to dispatch commands and instructions.

One or more aspects of at least one example may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit is fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

<FIG> is a block diagram illustrating an IP core development system <NUM> that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system <NUM> may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit. A design facility <NUM> can generate a software simulation <NUM> of an IP core design in a high-level programming language (e.g., C/C++). The software simulation <NUM> can be used to design, test, and verify the behavior of the IP core using a simulation model <NUM>. The simulation model <NUM> may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design <NUM> can then be created or synthesized from the simulation model <NUM>. The RTL design <NUM> is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design <NUM>, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design <NUM> or equivalent may be further synthesized by the design facility into a hardware model <NUM>, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3rd party fabrication facility <NUM> using non-volatile memory <NUM> (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection <NUM> or wireless connection <NUM>. The fabrication facility <NUM> may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit is configured to perform operations in accordance with at least one embodiment described herein.

<FIG> illustrates a cross-section side view of an integrated circuit package assembly <NUM>, according to some embodiments described herein. The integrated circuit package assembly <NUM> illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly <NUM> includes multiple units of hardware logic <NUM>, <NUM> connected to a substrate <NUM>. The logic <NUM>, <NUM> may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic <NUM>, <NUM> can be implemented within a semiconductor die and coupled with the substrate <NUM> via an interconnect structure <NUM>. The interconnect structure <NUM> may be configured to route electrical signals between the logic <NUM>, <NUM> and the substrate <NUM>, and can include interconnects such as, but not limited to bumps or pillars. The interconnect structure <NUM> may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic <NUM>, <NUM>. The substrate <NUM> is an epoxy-based laminate substrate. The package substrate <NUM> may include other suitable types of substrates in other examples. The package assembly <NUM> can be connected to other electrical devices via a package interconnect <NUM>. The package interconnect <NUM> may be coupled to a surface of the substrate <NUM> to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

The units of logic <NUM>, <NUM> are electrically coupled with a bridge <NUM> that is configured to route electrical signals between the logic <NUM>, <NUM>. The bridge <NUM> may be a dense interconnect structure that provides a route for electrical signals. The bridge <NUM> may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic <NUM>, <NUM>.

Although two units of logic <NUM>, <NUM> and a bridge <NUM> are illustrated, examples described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge <NUM> may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

<FIG> illustrated exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various examples described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

<FIG> is a block diagram illustrating an exemplary system on a chip integrated circuit <NUM> that may be fabricated using one or more IP cores, according to an example. Exemplary integrated circuit <NUM> includes one or more application processor(s) <NUM> (e.g., CPUs), at least one graphics processor <NUM>, and may additionally include an image processor <NUM> and/or a video processor <NUM>, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit <NUM> includes peripheral or bus logic including a USB controller <NUM>, UART controller <NUM>, an SPI/SDIO controller <NUM>, and an I2S/I2C controller <NUM>. Additionally, the integrated circuit can include a display device <NUM> coupled to one or more of a high-definition multimedia interface (HDMI) controller <NUM> and a mobile industry processor interface (MIPI) display interface <NUM>. Storage may be provided by a flash memory subsystem <NUM> including flash memory and a flash memory controller. Memory interface may be provided via a memory controller <NUM> for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine <NUM>.

<FIG> are block diagrams illustrating exemplary graphics processors for use within an SoC, according to examples described herein. <FIG> illustrates an exemplary graphics processor <NUM> of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an example. <FIG> illustrates an additional exemplary graphics processor <NUM> of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an example. Graphics processor <NUM> of <FIG> is an example of a low power graphics processor core. Graphics processor <NUM> of <FIG> is an example of a higher performance graphics processor core. Each of the graphics processors <NUM>, <NUM> can be variants of the graphics processor <NUM> of <FIG>.

As shown in <FIG>, graphics processor <NUM> includes a vertex processor <NUM> and one or more fragment processor(s) 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-<NUM>, and 1315N). Graphics processor <NUM> can execute different shader programs via separate logic, such that the vertex processor <NUM> is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s) 1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor <NUM> performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor <NUM> to produce a framebuffer that is displayed on a display device. The fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

Graphics processor <NUM> additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B provide for virtual to physical address mapping for the graphics processor <NUM>, including for the vertex processor <NUM> and/or fragment processor(s) 1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s) 1325A-1325B. The one or more MMU(s) 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s) <NUM>, image processor <NUM>, and/or video processor <NUM> of <FIG>, such that each processor <NUM>-<NUM> can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s) 1330A-1330B enable graphics processor <NUM> to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

As shown <FIG>, graphics processor <NUM> includes the one or more MMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor <NUM> of <FIG>. Graphics processor <NUM> includes one or more shader core(s) 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-<NUM>, and 1355N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among implementations. Additionally, graphics processor <NUM> includes an inter-core task manager <NUM>, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling unit <NUM> to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

<FIG> illustrate additional exemplary graphics processor logic according to examples described herein. <FIG> illustrates a graphics core <NUM> that may be included within the graphics processor <NUM> of <FIG>, and may be a unified shader core 1355A-1355N as in <FIG>. <FIG> illustrates an additional highly-parallel general-purpose graphics processing unit <NUM>, which is a highly-parallel general-purpose graphics processing suitableunit suitable for deployment on a multi-chip module.

As shown in <FIG>, the graphics core <NUM> includes a shared instruction cache <NUM>, a texture unit <NUM>, and a cache/shared memory <NUM> that are common to the execution resources within the graphics core <NUM>. The graphics core <NUM> can include multiple slices 1401A-1401N or partition for each core, and a graphics processor can include multiple instances of the graphics core <NUM>. The slices 1401A-1401N can include support logic including a local instruction cache 1404A-1404N, a thread scheduler 1406A-1406N, a thread dispatcher 1408A-1408N, and a set of registers 1410A-1440N. To perform logic operations, the slices 1401A-1401N can include a set of additional function units (AFUs 1412A-1412N), floating-point units (FPU 1414A-1414N), integer arithmetic logic units (ALUs <NUM>-1416N), address computational units (ACU 1413A-1413N), double-precision floating-point units (DPFPU 1415A-1415N), and matrix processing units (MPU 1417A-1417N).

Some of the computational units operate at a specific precision. For example, the FPUs 1414A-1414N can perform single-precision (<NUM>-bit) and half-precision (<NUM>-bit) floating point operations, while the DPFPUs 1415A-1415N perform double precision (<NUM>-bit) floating point operations. The ALUs 1416A-1416N can perform variable precision integer operations at <NUM>-bit, <NUM>-bit, and <NUM>-bit precision, and can be configured for mixed precision operations. The MPUs 1417A-1417N can also be configured for mixed precision matrix operations, including half-precision floating point and <NUM>-bit integer operations. The MPUs <NUM>-1417N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). The AFUs 1412A-1412N can perform additional logic operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

As shown in <FIG>, a general-purpose processing unit (GPGPU) <NUM> can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units. Additionally, the GPGPU <NUM> can be linked directly to other instances of the GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks. The GPGPU <NUM> includes a host interface <NUM> to enable a connection with a host processor. The host interface <NUM> is a PCI Express interface. However, the host interface can also be a vendor specific communications interface or communications fabric. The GPGPU <NUM> receives commands from the host processor and uses a global scheduler <NUM> to distribute execution threads associated with those commands to a set of compute clusters 1436A-<NUM>. The compute clusters 1436A-<NUM> share a cache memory <NUM>. The cache memory <NUM> can serve as a higher-level cache for cache memories within the compute clusters 1436A-<NUM>.

The GPGPU <NUM> includes memory 14434A-14434B coupled with the compute clusters 1436A-<NUM> via a set of memory controllers 1442A-1442B. The memory 1434A-1434B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

The compute clusters 1436A-<NUM> each include a set of graphics cores, such as the graphics core <NUM> of <FIG>, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example and at least a subset of the floating point units in each of the compute clusters 1436A-<NUM> can be configured to perform <NUM>-bit or <NUM>-bit floating point operations, while a different subset of the floating point units can be configured to perform <NUM>-bit floating point operations.

Multiple instances of the GPGPU <NUM> can be configured to operate as a compute cluster. The communication mechanism used by the compute cluster for synchronization and data exchange varies. The multiple instances of the GPGPU <NUM> communicate over the host interface <NUM>. The GPGPU <NUM> includes an I/O hub <NUM> that couples the GPGPU <NUM> with a GPU link <NUM> that enables a direct connection to other instances of the GPGPU. The GPU link <NUM> is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU <NUM>. The GPU link <NUM> couples with a high speed interconnect to transmit and receive data to other GPGPUs or parallel processors. The multiple instances of the GPGPU <NUM> are located in separate data processing systems and communicate via a network device that is accessible via the host interface <NUM>. The GPU link <NUM> can be configured to enable a connection to a host processor in addition to or as an alternative to the host interface <NUM>.

While the illustrated configuration of the GPGPU <NUM> can be configured to train neural networks, one example provides alternate configuration of the GPGPU <NUM> that can be configured for deployment within a high performance or low power inferencing platform. In an inferencing configuration the GPGPU <NUM> includes fewer of the compute clusters 1436A-<NUM> relative to the training configuration. Additionally, the memory technology associated with the memory 1434A-1434B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. The inferencing configuration of the GPGPU <NUM> can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more <NUM>-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks.

As mentioned above, ray tracing is a graphics processing technique in which a light transport is simulated through physically-based rendering. One of the key operations in ray tracing is processing a visibility query which requires traversal and intersection testing of nodes in a bounding volume hierarchy (BVH).

Ray- and path-tracing based techniques compute images by tracing rays and paths through each pixel, and using random sampling to compute advanced effects such as shadows, glossiness, indirect illumination, etc. Using only a few samples is fast but produces noisy images while using many samples produces high quality images, but is cost prohibitive.

In the last several years, a breakthrough solution to ray-/path-tracing for real-time use has come in the form of "denoising" - the process of using image processing techniques to produce high quality, filtered/denoised images from noisy, low-sample count inputs. The most effective denoising techniques rely on deep/machine learning where convolutional neural networks (CNN) learn what a noisy image would likely look like if it had been computed with more samples. This works by producing training data with low-sample count inputs and ground-truth, a fully converged solution for the same scene and viewpoint, and training the CNN to predict the converged pixel from a neighborhood of noisy pixel inputs around the pixel in question.

Though not perfect, this AI-based denoising technique has proven surprisingly effective. The caveat, however, is that good training data is required, since the network may otherwise predict the wrong results. For example, if an animated movie studio trained a denoising CNN on past movies with scenes on land and then attempted to use the trained CNN to denoise frames from a new movie set on water, the denoising operation will perform sub-optimally.

To address this problem, one example gathers learning data dynamically, while rendering, and continuously trains a machine learning engine, such as a CNN, based on the data on which it is currently being run, thus continuously improving the machine learning engine for the task at hand. This example may still perform a training phase prior to runtime, but continues to adjust the machine learning weights as needed during runtime. In addition, this example avoids the high cost of computing the reference data required for the training by restricting the generation of learning data to a sub-region of the image every frame or every N frames. In particular, the noisy inputs of a frame are generated for denoising the full frame with the current network. in addition, a small region of reference pixels are generated and used for continuous training, as described below.

Existing de-noising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined which receives a region of NxN pixels with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive IDs, and albedo and generates a final pixel color. A set of "representative" training data is generated using one frame's worth of low-sample count inputs, and referencing the "desired" pixel colors computed with a very high sample count. The network is trained towards these inputs, generating a set of "ideal" weights for the network. In these implementations, the reference data is used to train the network's weights to most closely match the network's output to the desired result.

At runtime, the given, pre-computed ideal network weights are loaded and the network is initialized. For each frame, a low-sample count image of denoising inputs (i.e., the same as used for training) is generated. For each pixel, the given neighborhood of pixels' inputs is run through the network to predict the "denoised" pixel color, generating a denoised frame.

<FIG> illustrates one example of an initial training implementation. A machine learning engine <NUM> (e.g., a CNN) receives a region of N x N pixels as high sample count image data <NUM> with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive IDs, and albedo and generates final pixel colors. Representative training data is generated using one frame's worth of low-sample count inputs <NUM>. The network is trained towards these inputs, generating a set of "ideal" weights <NUM> which the machine learning engine <NUM> subsequently uses to denoise low sample count images at runtime.

To improve the above techniques, one example of the invention augments the denoising phase to generate new training data every frame or a subset of frames (e.g., every N frames where N = <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc). In particular, as illustrated in <FIG>, this example chooses one or more regions in each frame, referred to here as "new reference regions" <NUM> which are rendered with a high sample count into a separate high sample count buffer <NUM>. A low sample count buffer <NUM> stores the low sample count input frame <NUM> (including the low sample region <NUM> corresponding to the new reference region <NUM>).

The location of the new reference region <NUM> is randomly selected. Alternatively, the location of the new reference region <NUM> may be adjusted in a pre-specified manner for each new frame (e.g., using a predefined movement of the region between frames, limited to a specified region in the center of the frame, etc).

Regardless of how the new reference region is selected, it is used by the machine learning engine <NUM> to continually refine and update the trained weights <NUM> used for denoising. In particular, in one embodiment, reference pixel colors from each new reference region <NUM> and noisy reference pixel inputs from a corresponding low sample count region are rendered. Supplemental training is then performed on the machine learning engine <NUM> using the high-sample-count reference region <NUM> and the corresponding low sample count region. In contrast to the initial training, this training is performed continuously during runtime for each new reference region <NUM> - thereby ensuring that the machine learning engine <NUM> is precisely trained. For example, per-pixel data channels (e.g., pixel color, depth, normal, normal deviation, etc) may be evaluated, which the machine learning engine <NUM> uses to make adjustments to the trained weights <NUM>. As in the training case (<FIG>), the machine learning engine <NUM> is trained towards a set of ideal weights <NUM> for removing noise from the low sample count input frame <NUM> to generate the denoised frame <NUM>. However, the trained weights <NUM> are continually updated, based on new image characteristics of new types of low sample count input frames <NUM>.

The re-training operations performed by the machine learning engine <NUM> are executed concurrently in a background process on the graphics processor unit (GPU) or host processor. The render loop, which may be implemented as a driver component and/or a GPU hardware component, continuously produces new training data (e.g., in the form of new reference regions <NUM>) which it places in a queue. The background training process, executed on the GPU or host processor, continuously reads the new training data from this queue, re-trains the machine learning engine <NUM>, and updates it with new weights <NUM> at appropriate intervals.

<FIG> illustrates an example of one such implementation in which the background training process <NUM> is implemented by the host CPU <NUM>. In particular, the background training process <NUM> uses the high sample count new reference region <NUM> and the corresponding low sample region <NUM> to continually update the trained weights <NUM>, thereby updating the machine learning engine <NUM>.

As illustrated in <FIG>, in one implementation such as in a multi-player online game, different host machines <NUM>-<NUM> individually generate reference regions which a background training process 1700A-C transmits to a server <NUM> (e.g., such as a gaming server). The server <NUM> then performs training on a machine learning engine <NUM> using the new reference regions received from each of the hosts <NUM>-<NUM>, updating the weights <NUM> as previously described. It transmits these weights <NUM> to the host machines <NUM> which store the weights 1605A-C, thereby updating each individual machine learning engine (not shown). Because the server <NUM> may be provided a large number of reference regions in a short period of time, it can efficiently and precisely update the weights for any given application (e.g., an online game) being executed by the users.

As illustrated in <FIG>, the different host machines may generate new trained weights (e.g., based on training/reference regions <NUM> as previously described) and share the new trained weights with a server <NUM> (e.g., such as a gaming server) or, alternatively, use a peer-to-peer sharing protocol. A machine learning management component <NUM> on the server generates a set of combined weights <NUM> using the new weights received from each of the host machines. The combined weights <NUM>, for example, may be an average generated from the new weights and continually updated as described herein. Once generated, copies of the combined weights 1605A-C may be transmitted and stored on each of the host machines <NUM>-<NUM> which may then use the combined weights as described herein to perform de-noising operations.

This semi-closed loop update mechanism can be used by the hardware manufacturer. For example, the reference network may be included as part of the driver distributed by the hardware manufacturer. As the driver generates new training data using the techniques described herein and continuously submits these back to the hardware manufacturer, the hardware manufacturer uses this information to continue to improve its machine learning implementations for the next driver update.

In one implementation (e.g., in batch movie rendering on a render farm) the renderer transmits the newly generated training regions to a dedicated server or database (in that studio's render farm) that aggregates this data from multiple render nodes over time. A separate process on a separate machine continuously improves the studio's dedicated denoising network, and new render jobs always use the latest trained network.

A method in accordance with one embodiment of the invention is illustrated in <FIG>. The method may be implemented on the architectures described herein, but is not limited to any particular system or graphics processing architecture.

At <NUM>, as part of the initial training phase, low sample count image data and high sample count image data are generated for a plurality of image frames. At <NUM>, a machine-learning denoising engine is trained using the high/low sample count image data. For example, a set of convolutional neural network weights associated with pixel features may be updated in accordance with the training. However, any machine-learning architecture may be used.

At <NUM>, at runtime, low sample count image frames are generated along with at least one reference region having a high sample count. At <NUM>, the high sample count reference region is used by the machine-learning engine and/or separate training logic (e.g., background training module <NUM>) to continually refine the training of the machine learning engine. For example, the high sample count reference region is used in combination with a corresponding portion of the low sample count image to continue to teach the machine learning engine <NUM> how to most effectively perform denoising. In a CNN implementation, for example, this may involve updating the weights associated with the CNN.

Multiple variations of the examples described above may be implemented, such as the manner in which the feedback loop to the machine learning engine is configured, the entities which generate the training data, the manner in which the training data is fed back to training engine, and how the improved network is provided to the rendering engines. In addition, while the above examples described above perform continuous training using a single reference region, any number of reference regions may be used. Moreover, as previously mentioned, the reference regions may be of different sizes, may be used on different numbers of image frames, and may be positioned in different locations within the image frames using different techniques (e.g., random, according to a predetermined pattern, etc).

In addition, while a convolutional neural network (CNN) is described as one example of a machine-learning engine <NUM>, the underlying principles of the invention may be implemented using any form of machine learning engine which is capable of continually refining its results using new training data. By way of example, and not limitation, other machine learning implementations include the group method of data handling (GMDH), long short-term memory, deep reservoir computing, deep belief networks, tensor deep stacking networks, and deep predictive coding networks, to name a few.

In examples, the term "engine" or "module" or "logic" may refer to, be part of, or include an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. In examples, an engine, module, or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware, and software.

Embodiments of the invention include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals - such as carrier waves, infrared signals, digital signals, etc.).

Claim 1:
An apparatus comprising:
a graphics rendering engine of a graphics processing unit, GPU (<NUM>), configured to render a first plurality of images during runtime at a first sample count; and
at least one processor (<NUM>, <NUM>) configured to:
execute first program code to perform image denoising by a machine-learning engine (<NUM>, <NUM>, <NUM>), wherein the machine-learning engine (<NUM>, <NUM>, <NUM>) is configured to denoise each of the first plurality of images during runtime using trained weights (<NUM>);
generate, during runtime, one or more new reference regions (<NUM>) in one or more of the first plurality of images at a second sample count greater than the first sample count;
render reference pixel colors from each new reference region (<NUM>) and noisy reference pixel inputs from a corresponding low sample count region; and
perform runtime training of the machine-learning engine (<NUM>, <NUM>, <NUM>) using the one or more new reference regions (<NUM>), wherein runtime training comprises an evaluation of the one or more new reference regions (<NUM>) in combination with the corresponding low sample count region in the at least one of the first plurality of images to update the trained weights (<NUM>) accordingly.