Patent Description:
An Eye Open Monitor (EOM) is used to grasp quality characteristics of signals transmitted to and received from a channel. In general, received signals from the channel include time-varying voltages, that is, waveforms. For example, an eye of a signal received at a signal receiving end of a memory system (e.g., a receiver of the memory device) may be measured to improve the quality of signal transmission and reception between the memory device and the host device.

The EOM receives and processes pattern data. At this time, the pattern data includes a data symbol used for information delivery, a control symbol for controlling transmission and reception of the signal, a filler symbol for maintaining locking of a Phase Lock Loop (PLL) of the receiving end and the like.

When the EOM is performed on the basis of non-data symbols such as the control symbol and the filler symbol, the EOM results do not properly reflect the actual channel characteristics and the reliability of the EOM results may be degraded. Accordingly, there is a need for a solution to this problem. <CIT> describes how I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.

One or more example embodiments provide an operating method of a memory device that may improve the reliability of an EOM result.

One or more example embodiments also provide an operating method of a host device that may improve the reliability of an EOM result.

One or more example embodiments also provide a memory device in which the reliability of an EOM result is improved.

According to an aspect of an example embodiment, there is provided a method of operating a memory device, the method including: receiving, from a host device, a command requesting an EOM (Eye Open Monitor) operation; receiving pattern data including one or more data symbols and one or more non-data symbols from the host device, wherein the one or more data symbols includes an information symbol and/or a pattern symbol; counting, in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols; not counting, in the error count, second errors corresponding to the one or more non-data symbols; and transmitting, to the host device, an EOM response signal including the error count.

Also provided herein is a method of operating a host device, the method including: transmitting, to a memory device, a command requesting an EOM operation; transmitting pattern data including one or more data symbols and one or more non-data symbols to the memory device; and receiving, from the memory device, an EOM response signal including an error count associated with the pattern data, wherein the error count is based on the one or more data symbols and is not based on the non-data symbols.

According to an aspect of an example embodiment, there is provided a memory device including: an interfacing device; and a device controller configured to control an operation of the interfacing device, wherein the interfacing device is configured to: receive a command requesting an EOM operation, receive, from a host device, pattern data including one or more data symbols and one or more non-data symbols, wherein the one or more data symbols includes an information symbol and/or a pattern symbol, perform an EOM operation by operations including: counting, in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols, and not counting, in the error count, second errors corresponding to the one or more non-data symbols, and transmit, to the host device, an EOM response signal including the error count.

According to an aspect of an example embodiment, there is provided a data receiving device including: an interfacing device; and a controller configured to control an operation of the interfacing device, wherein the interfacing device is configured to receive a command requesting an EOM operation, receiving pattern data including one or more data symbols and one or more non-data symbols from a data transmission device, wherein the one or more data symbols includes an information symbol and/or a pattern symbol; counting, in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols; not counting, in the error count, second errors corresponding to the one or more non-data symbols; and transmitting, to the data transmission device, an EOM response signal including the error count.

Embodiments discussed herein apply EOM error counting only to data symbols, and do not apply EOM error counting to non-data symbols (such as control data or filler data). This improves the reliability of the EOM results, as the inclusion of non-data symbols within these error counts can degrade the reliability of the EOM results.

Not counting, in the error count, second errors corresponding to the one or more non-data symbols may comprise inhibiting the counting of errors for non-data symbols and/or ignoring errors within or corresponding to non-data symbols.

At least some of the above and other aspects of the invention are set out in the claims.

Embodiments are described in the detailed description given below.

The above and/or other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments thereof referring to the attached drawings, in which:.

Hereinafter, example embodiments will be described referring to the accompanying drawings.

<FIG> is a diagram showing a memory system according to some embodiments. <FIG> is a diagram showing a Universal Flash Storage (UFS) interconnect (UIC) layer of <FIG>. <FIG> is a diagram showing a clock data recovery (CDR) block of <FIG>. <FIG> is a diagram for explaining an EOM operation. <FIG> is a diagram showing a non-data symbol detector of <FIG>.

Hereinafter, a memory system will be described by taking an example of a system that complies with a UFS standard announced at Joint Electron Device Engineering Council (JEDEC). However, embodiments are not limited thereto, and the aspects of the memory system implemented within the same technical idea may be implemented with various modifications.

Referring to <FIG>, the UFS system <NUM> may include a host device <NUM>, a memory device <NUM>, and a UFS interface <NUM>.

The host device <NUM> and the memory device <NUM> may be connected to each other through the UFS interface <NUM>. In some embodiments, the host device <NUM> may be implemented as a part of an application processor.

The host device <NUM> may include a UFS host controller <NUM>, an application <NUM>, a UFS driver <NUM>, a host memory <NUM>, and a UIC layer <NUM>.

The memory device <NUM> may include a UFS device controller <NUM>, a non-volatile storage <NUM>, a storage interface <NUM>, a device memory <NUM>, a UIC layer <NUM>, and a regulator <NUM>.

The non-volatile storage <NUM> may be made up of a plurality of storage units <NUM>. Although such a storage unit <NUM> may include a V-NAND flash memory of 2D structure or 3D structure, it may also include other types of non-volatile memory such as a PRAM and/or a RRAM.

The UFS device controller <NUM> and the non-volatile storage <NUM> may be connected to each other through the storage interface <NUM>. The storage interface <NUM> may be implemented to comply with standards such as Toggle or ONFI. The operation between the UFS device controller <NUM> and the non-volatile storage <NUM> using the Toggle will be described later.

The application <NUM> may be a program that wants to communicate with the memory device <NUM> to utilize the functions of the memory device <NUM>. The application <NUM> may transmit an input-output request (IOR) to the UFS driver <NUM> for input and output to and from the memory device <NUM>. The input-output request (IOR) may mean, but is not necessarily limited to, data read request, write request and/or erase request, or the like.

The UFS driver <NUM> may manage the UFS host controller <NUM> through a UFS-HCI (host controller interface). The UFS driver <NUM> may convert the input-output request generated by the application <NUM> into UFS command defined by the UFS standard, and may send the converted UFS command to the UFS host controller <NUM>. A single input-output request may be converted into a plurality of UFS commands. The UFS commands may basically be commands defined by a Small Computer System Interface (SCSI) standard, but may also be UFS standard-only commands.

The UFS host controller <NUM> may transmit the UFS commands converted by the UFS driver <NUM> to the UIC layer <NUM> of the memory device <NUM> through the UIC layer <NUM> and the UFS interface <NUM>. In this procedure, the UFS host register <NUM> of the UFS host controller <NUM> may act as a command queue (CQ).

The UIC layer <NUM> on the host device <NUM> side may include a MIPI M-PHY® and a MIPI UniPro®, and the UIC layer <NUM> on the memory device <NUM> side may also include a MIPI M-PHY® and a MIPI UniPro®.

The UFS interface <NUM> may include a line that transmits a reference clock REF_CLK, a line that transmits a hardware reset signal RESET_n of the memory device <NUM>, a pair of lines that transmits differential input signal pairs DIN_T and DIN_C, and a pair of lines that transmits differential output signal pairs DOUT_T and DOUT_C.

A frequency value of the reference clock provided from the host device <NUM> to the memory device <NUM> may be, but is not necessarily limited to, one of four values of <NUM>, <NUM>, <NUM> and <NUM>. The host device <NUM> may change the frequency value of the reference clock even during operation, that is, even during data transmission and reception between the host device <NUM> and the memory device <NUM>.

The memory device <NUM> may generate clocks of various frequencies from the reference clock provided from the host device <NUM>, by utilizing a phase-locked loop (PLL) or the like. Further, the host device <NUM> may set a data rate value between the host device <NUM> and the memory device <NUM> through the frequency value of the reference clock. That is, the value of the data rate may be determined depending on the frequency value of the reference clock.

The UFS interface <NUM> may support a plurality of lanes, and each lane may be implemented as a differential pair. For example, the UFS interface <NUM> may include one or more receive lanes and one or more transmit lanes. In <FIG>, the pair of lines that transmits the differential input signal pairs DIN_T and DIN_C may constitute the receive lane, and the pair of lines that transmits the differential output signal pairs DOUT_T and DOUT_C may constitute the transmit lane, respectively. In <FIG>, although one transmit lane and one receive lane are shown, the number of transmit lanes and receive lanes may be modified.

The receive lane and the transmit lane may transmit the data in a serial communication manner, and a full-duplex type communication between the host device <NUM> and the memory device <NUM> is enabled by a structure in which the receive lane and the transmit lane are separated. That is, the memory device <NUM> may transmit data to the host device <NUM> through the transmit lane, even while receiving the data from the host device <NUM> through the receive lane. Also, control data such as command from the host device <NUM> to the memory device <NUM>, and user data to be stored in the non-volatile storage <NUM> of the memory device <NUM> or to be read from the non-volatile storage <NUM> by the host device <NUM> may be transmitted through the same lane. Accordingly, it is not necessary to further provide a separate lane for data transmission, in addition to the pair of transmit lanes and the pair of receive lanes, between the host device <NUM> and the memory device <NUM>.

Referring to <FIG>, the UIC layer <NUM> may include an equalizer <NUM> including an analog front end (AFE), a CDR block <NUM>, a decoder <NUM>, a descrambler <NUM>, a symbol remover <NUM>, a lane merger <NUM>, and a symbol translator 259a.

The equalizer <NUM> receives differential input signal pairs DIN_T and DIN_C from the host device (<NUM> of <FIG>), and may perform equalizing to output serial bits SB. In some embodiments, the host device (<NUM> of <FIG>) provides differential input signal pairs DIN_T and DIN_C which are serial signals to the equalizer <NUM>, and the equalizer <NUM> may output the serial bit SB from it.

The CDR block <NUM> may perform clock data recovery (CDR) and data deserialization to output an N-bit (N is a natural number) signal. The CDR block <NUM> may include an EOM block <NUM> that performs the EOM operation to measure the signal quality of the communication channel with the host device (<NUM> of <FIG>), and a non-data symbol detector <NUM> that controls the performance of the EOM operation of the EOM block <NUM>.

In some embodiments, although the EOM operation performed in the CDR block <NUM> may be performed using, for example, an SFR (Special Function Register) <NUM>, the embodiments are not limited thereto.

Referring to <FIG> and <FIG>, the EOM operation performed in the CDR block <NUM> may be performed by measuring the quality of the signal received from the host device <NUM>, using the SFR <NUM> under specific offset conditions. In general, the received signal is a waveform including information symbols, pattern symbols and/or non-data symbols.

Specifically, the EOM operation may be performed by comparing a main path signal MS of a main path indicated by a solid line in <FIG> with an EOM path signal ES of an EOM path indicated by a dotted line in <FIG>.

The main path may recover the clock from a serial bit SB received from the host device <NUM> and passing through the equalizer <NUM>, using a clock recovery circuit 253b, extract data of the serial bit SB using the recovered clock RCK, and then generate a main path signal MS through the deserializer 253a. The main path signal MS thus generated may be sent to the comparator 255b.

The EOM path may generate a clock dxRCK which reflects a specific offset value dX on the clock RCK recovered from the serial bit SB received from the host device <NUM> and passing through the equalizer <NUM>, extract data of the serial bit SB by reflecting the clock dxRCK and the specific offset value dY, and then generate an EOM path signal ES through the deserializer 255a. The EOM path signal ES thus generated may be sent to the comparator 255b.

For example, the main path signal MS may be data extracted from the reference conditions XR and YR of <FIG>, and the EOM path signal ES may be data extracted from the offset conditions dX and dY of <FIG>.

When the EOM path signal ES is recognized as the same signal as the main path signal MS, the comparator 255b does not output the error count signal EC. When the EOM path signal ES is not recognized as the same signal as the main path signal MS, the comparator 255b may output the error count signal EC. That is, the error counting may be performed by the error count EC that is output to the comparator 255b.

Further, the comparator 255b may output a sampling count signal SC each time such sampling (for example, comparison of the EOM path signal ES and the main path signal MS) is performed once.

In some embodiments, an offset value dX may include a time offset value, a phase offset value, and the like, and an offset value dY may include a voltage offset, or the like. However, the embodiments are not limited thereto.

In some embodiments, although the offset dX, the offset dY, the error count value according to the error count signal EC, the sampling number information according to the sampling count signal SC, and the like may be stored in the SFR <NUM>, the embodiments are not limited thereto.

The non-data symbol detector <NUM> monitors the main path signal MS through the deserializer 253a, and when the received data is a filler symbol, the non-data symbol detector <NUM> may apply a control signal CS that stops the output of the error count signal EC to the comparator 255b. That is, when the received data is a filler symbol, the non-data symbol detector <NUM> may stop the operation of the comparator 255b so that the EOM error counting is not performed on the filler symbol (e.g. the EOM operation is inhibited).

The host device <NUM> may transmit the filler symbol while the data symbol used for information delivery is not transmitted to maintain the PLL locking of the memory device <NUM>. In some cases, a proportion of filler symbol may be much larger than the data symbol in the pattern data received from the host device <NUM>. A data symbol may be referred to herein as an information symbol or as a pattern symbol. The pattern data may be referred to herein as a waveform. The received pattern data, that is, the received waveform, may include information symbols, pattern symbols and/or non-data symbols. Incidentally, since such a filler symbol is an artificially generated symbol for maintaining the PLL locking, when performing the EOM error counting on the filler symbol, accurate quality evaluation may not be performed on the data symbol transmission environment. That is, the reliability of the EOM result may be degraded. Therefore, in this embodiment, when the received symbol is the filler symbol other than the data symbol, by stopping the error counting thereof to exclude the filler symbol from the final EOM result, reliability of the EOM result may be improved. In general, a highly random sequence of symbols is good for the EOM function. User information symbols may provide this randomness, or the host <NUM> or the device <NUM> may store a table of random symbols.

In some embodiments, the comparator 255b may also stop the output of the sampling count signal SC when the control signal CS is received from the non-data symbol detector <NUM>. That is, when the control signal CS is received from the non-data symbol detector <NUM>, the comparator 255b stops both the outputs of the error count signal EC and the sampling count signal SC, thereby completely excluding the EOM operation of the filler symbol.

Referring to <FIG>, the non-data symbol detector <NUM> may include a comparison logic 254a which receives the N-bit signal output from the deserializer 253a and determines whether the N-bit signal is a predetermined symbol. In some embodiments, although the N-bit signal may be a <NUM>-bit signal, the embodiments are not limited thereto.

In some embodiments, the comparison logic 254a may determine whether the N-bit signal is a K28. <NUM> symbol, which means the start of signal reception. Specifically, when the N-bit signal is a <NUM>-bit signal, the comparison logic 254a determines whether the input signal is a K28. <NUM> symbol which is <NUM> or <NUM>, and may provide the symbol locking signal SLS to the deserializer 253a when the input signal corresponds to the K28. <NUM> symbol.

Further, the comparison logic 254a may determine whether the N-bit signal is a K28. <NUM> symbol which means filler data. Specifically, when the N-bit signal is a <NUM>-bit signal, the comparison logic 254a determines whether the input signal is the K28. <NUM> symbol which is <NUM> or <NUM>, and may provide the comparator 255b with a control signal CS that stops the error count performing operation, when corresponding to the K28. <NUM> symbol. Accordingly, the comparator 255b may not perform the EOM operation on the filler symbol (e.g. the EOM operation is inhibited).

Referring to <FIG> again, the decoder <NUM> may decode the N-bit signal which is output from the CDR block <NUM> to an M-bit (M is a natural number greater than N) signal and a distinction signal DS. In some embodiments, although the N-bit signal may be a <NUM>-bit signal and the M-bit signal may be an <NUM>-bit signal, the embodiments are not limited thereto.

When the input N-bit signal is a data symbol, the decoder <NUM> may output the data signal D as the distinction signal DS. When the input N-bit signal is a control symbol, the decoder <NUM> may output the control signal K as the distinction signal DS.

The descrambler <NUM> may perform descrambling on the input M-bit signal and output it. The symbol remover <NUM> may remove skip symbol such as a marker and a filler symbol from the input M-bit signal. The lane merger <NUM> may merge the signals input to each lane and provide them to the symbol translator 259a. The symbol translator 259a may translate and output the symbols.

Referring to <FIG> again, the UFS device controller <NUM> of the memory device <NUM> may generally control the operation of the memory device <NUM>.

The UFS device controller <NUM> may manage the non-volatile storage <NUM> through a LU (logical unit) <NUM>, which is a logical storage unit of data. Although the number of LUs <NUM> may be, for example, eight, the embodiments are not limited thereto.

The UFS device controller <NUM> may include a flash translation layer (FTL), and may convert a logical data address sent from the host device <NUM>, for example, an LBA (logical block address), into a physical data address, for example, a PBA (physical block address) or a PPN (physical page number), using the address mapping information of the FTL. In the UFS system <NUM>, the logical block for storing user data may have a size of a predetermined range. For example, the minimum size of the logical block may be set to <NUM> Kbytes.

When a command from the host device <NUM> is input to the memory device <NUM> through the UIC layer <NUM>, the UFS device controller <NUM> performs an operation according to the input command, and may transmit the completion response to the host device <NUM> when the operation is completed.

For example, when the host device <NUM> tries to store user data in the memory device <NUM>, the host device <NUM> may transmit a data write command to the memory device <NUM>. When a response which is ready to receive the user data (ready-to-transfer) is received from the memory device <NUM>, the host device <NUM> may transmit the user data to the memory device <NUM>. The UFS device controller <NUM> temporarily stores the transmitted user data in the device memory <NUM>, and may store the user data temporarily stored in the device memory <NUM> at a selected position of the non-volatile storage <NUM> on the basis of the address mapping information of the FTL.

As still another example, when the host device <NUM> tries to read user data stored in the memory device <NUM>, the host device <NUM> may transmit the data read command to the memory device <NUM>. When receiving the command, the UFS device controller <NUM> reads the user data from the non-volatile storage <NUM> on the basis of the data read command, and may temporarily store the read user data in the device memory <NUM>. In such a read procedure, the UFS device controller <NUM> may detect and correct errors of the read user data, using a built-in ECC (error correction code) circuit (not shown). Further, the UFS device controller <NUM> may transmit the user data temporarily stored in the device memory <NUM> to the host device <NUM>.

Furthermore, the UFS device controller <NUM> may further include an AES (advanced encryption standard) circuit (not shown), and the AES circuit may encrypt or decrypt data which is input to the UFS device controller <NUM>, using a symmetric-key algorithm.

The host device <NUM> may store the commands to be transmitted to the memory device <NUM> in order in the UFS host register <NUM> which may function as a command queue, and transmit the commands to the memory device <NUM> in that order. At this time, the host device <NUM> may transmit the next command waiting in the command queue to the memory device <NUM>, even when the previously transmitted command is still being processed by the memory device <NUM>, that is, even before receiving the notification that the previously transmitted command is completely processed by the memory device <NUM>. Accordingly, the memory device <NUM> may also receive the next command from the host device <NUM>, even while processing the previously transmitted command. The maximum number of commands (queue depth) that may be stored in such a command queue may be, for example, thirty two. In addition, the command queue may be implemented as a circular queue type that indicates a start and an end of a command row stored in the queue through a head pointer and a tail pointer.

Each of the plurality of storage units <NUM> may include a memory cell array (not shown), and a control circuit (not shown) that controls the operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a cell (single level cell, SLC) that stores <NUM>-bit information, but each memory cell may also be a cell that stores <NUM>-bits or more information, such as a MLC (multi level cell), a TLC (triple level cell), and a QLC (quadruple level cell). A three-dimensional memory cell array may include a vertical NAND string which is vertically oriented so that at least one memory cell is located above another memory cell. More specific description thereof will be provided below.

VCC, VCCQ1, VCCQ2, and the like as a power supply voltage may be input to the memory device <NUM>. The VCC is a main power supply voltage for the memory device <NUM>, and may have, for example, a value of <NUM> to <NUM>. A VCCQ1 is a power supply voltage for supplying voltage of a low range, is mainly for the UFS device controller <NUM>, and may include, for example, a value of <NUM> and <NUM>. A VCCQ2 is a power supply voltage for supplying a voltage of a range lower than the VCC but higher than the VCCQ1, is mainly for input-output interfaces such as MIPI M-PHY® <NUM>, and may include, for example, a value of <NUM> to <NUM>. The power supply voltages may be supplied for each component of the memory device <NUM> via the regulator <NUM>. The regulator <NUM> may be implemented as a set of unit regulators, each connected to different ones among the aforementioned power supply voltages.

<FIG> is a diagram in which the UFS device controller, the storage interface, and the non-volatile storage of <FIG> are reconfigured.

The storage interface <NUM> of <FIG> may include a controller interface circuit 230a and the memory interface circuit 230b of <FIG>. In some embodiments, the storage device <NUM> shown in <FIG> may correspond to the single storage unit <NUM> of <FIG>. Also, in some embodiments, the storage device <NUM> may correspond to the non-volatile storage <NUM> of <FIG>.

The storage device <NUM> may include first to eighth pins P11 to P18, a memory interface circuit 230b, a control logic circuit <NUM>, and a memory cell array <NUM>.

The memory interface circuit 230b may receive a chip enable signal nCE from the device controller <NUM> through the first pin P11. The memory interface circuit 230b may transmit and receive signals to and from the device controller <NUM> through second to eighth pins P12 to P18 in accordance with the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable status (e.g., a low level), the memory interface circuit 230b may transmit and receive signals to and from the device controller <NUM> through second to eighth pins P12 to P18.

The memory interface circuit 230b may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the device controller <NUM> through second to fourth pins P12 to P14. The memory interface circuit 230b may receive the data signal DQ from the device controller <NUM> or transmit the data signal DQ to the device controller <NUM> through the seventh pin P17. The command CMD, the address ADDR, and the data may be sent through the data signal DQ. For example, the data signal DQ may be sent through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals.

The memory interface circuit 230b may acquire the command CMD from the data signal DQ received in an enable section (e.g., a high level status) of the command latch enable signal CLE on the basis of toggle timings of the write enable signal nWE. The memory interface circuit 230b may acquire the address ADDR from the data signal DQ received in the enable section (e.g., a high level status) of the address latch enable signal ALE on the basis of the toggle timings of the write enable signal nWE.

In some embodiments, the write enable signal nWE holds a static status (e.g., a high level or a low level) and then may be toggled between the high level and the low level. For example, the write enable signal nWE may be toggled at the section in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit 230b may acquire the command CMD or the address ADDR on the basis of the toggle timings of the write enable signal nWE.

The memory interface circuit 230b may receive a read enable signal nRE from the device controller <NUM> through the fifth pin P15. The memory interface circuit 230b may receive a data strobe signal DQS from the device controller <NUM> through a sixth pin P16, or may transmit the data strobe signal DQS to the device controller <NUM>.

In a data DATA output operation of the storage device <NUM>, the memory interface circuit 230b may receive the toggling read enable signal nRE through the fifth pin P15 before outputting the data DATA. The memory interface circuit 230b may generate the toggling data strobe signal DQS on the basis of the toggling of the read enable signal nRE. For example, the memory interface circuit 230b may generate the data strobe signal DQS that starts to toggle after a predetermined delay (e.g., tDQSRE) on the basis of the toggling start time of the read enable signal nRE. The memory interface circuit 230b may transmit the data signal DQ including the data DATA on the basis of the toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be arranged at the toggle timing of the data strobe signal DQS and transmitted to the device controller <NUM>.

In a data DATA input operation of the storage device <NUM>, when the data signal DQ including the data DATA is received from the device controller <NUM>, the memory interface circuit 230b may receive the toggling data strobe signal DQS together with the data DATA from the device controller <NUM>. The memory interface circuit 230b may acquire the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 230b may acquire the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS.

The memory interface circuit 230b may transmit a ready/busy output signal nR/B to the device controller <NUM> through an eighth pin P18. The memory interface circuit 230b may transmit the status information of the storage device <NUM> to the device controller <NUM> through the ready/busy output signal nR/B. When the storage device <NUM> is in a busy status (that is, when the internal operations of the storage device <NUM> are being performed), the memory interface circuit 230b may transmit the ready/busy output signal nR/B indicating the busy status to the device controller <NUM>. When the storage device <NUM> is in a ready status (i.e., the internal operations of the storage device <NUM> are not performed or are completed), the memory interface circuit 230b may transmit the ready/busy output signal nR/B indicating the ready status to the device controller <NUM>. For example, while the storage device <NUM> reads the data DATA from the memory cell array <NUM> in response to a page read command, the memory interface circuit 230b may transmit the ready/busy output signal nR/B indicating the busy status (e.g., a low level) to the device controller <NUM>. For example, while the storage device <NUM> programs the data DATA to the memory cell array <NUM> in response to the program command, the memory interface circuit 230b may transmit the ready/busy output signal nR/B indicating the busy status to the device controller <NUM>.

The control logic circuit <NUM> may generally control various operations of the storage device <NUM>. The control logic circuit <NUM> may receive the command/address CMD/ADDR acquired from the memory interface circuit 230b. The control logic circuit <NUM> may generate control signals for controlling other components of the storage device <NUM> in accordance with the received command/address CMD/ADDR. For example, the control logic circuit <NUM> may generate various control signals for programing the data DATA in the memory cell array <NUM> or reading the data DATA from the memory cell array <NUM>.

The memory cell array <NUM> may store the data DATA acquired from the memory interface circuit 230b under the control of the control logic circuit <NUM>. The memory cell array <NUM> may output the stored data DATA to the memory interface circuit 230b under the control of the control logic circuit <NUM>.

The memory cell array <NUM> may include a plurality of memory cells. For example, a plurality of memory cells may be flash memory cells. However, embodiments are not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, and MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments will be described mainly on the basis of an embodiment in which the memory cells are NAND flash memory cells.

The device controller <NUM> may include first to eighth pins P21 to P28, and a controller interface circuit 230a. The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the storage device <NUM>.

The controller interface circuit 230a may transmit the chip enable signal nCE to the storage device <NUM> through a first pin P21. The controller interface circuit 230a may transmit and receive signals to and from the storage device <NUM> selected through the chip enable signal nCE, through the second to eighth pins P22 to P28.

The controller interface circuit 230a may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the storage device <NUM> through the second to fourth pins P22 to P24. The controller interface circuit 230a may transmit the data signal DQ to the storage device <NUM> or receive the data signal DQ from the storage device <NUM> through a seventh pin P27.

The controller interface circuit 230a may transmit the data signal DQ including the command CMD or the address ADDR to the storage device <NUM> along with a toggling write enable signal nWE. The controller interface circuit 230a may transmit the data signal DQ including the command CMD to the storage device <NUM> with transmission of the command latch enable signal CLE having the enable status, and may transmit the data signal DQ including the address ADDR to the storage device <NUM> with transmission of the address latch enable signal ALE having the enable status.

The controller interface circuit 230a may transmit the read enable signal nRE to the storage device <NUM> through a fifth pin P25. The controller interface circuit 230a may receive the data strobe signal DQS from the storage device <NUM> through a sixth pin P26, or may transmit the data strobe signal DQS to the storage device <NUM>.

In the data DATA output operation of the storage device <NUM>, the controller interface circuit 230a may generate a toggling read enable signal nRE, and may transmit the read enable signal nRE to the storage device <NUM>. For example, the controller interface circuit 230a may generate the read enable signal nRE that changes from the static status (e.g., a high level or a low level) to the toggle status before the data DATA is output. Accordingly, the toggling data strobe signal DQS may be generated in the storage device <NUM> on the basis of the read enable signal nRE. The controller interface circuit 230a may receive the data signal DQ including the data DATA along with the toggling data strobe signal DQS from the storage device <NUM>. The controller interface circuit 230a may acquire the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS.

In the data DATA input operation of the storage device <NUM>, the controller interface circuit 230a may generate the toggling data strobe signal DQS. For example, the controller interface circuit 230a may generate the data strobe signal DQS that changes from the static status (e.g., a high level or a low level) to the toggle status before transmitting the data DATA. The controller interface circuit 230a may transmit the data signal DQ including the data DATA to the storage device <NUM> on the basis of the toggle timings of the data strobe signal DQS.

The controller interface circuit 230a may receive a ready/busy output signal nR/B from the storage device <NUM> through an eighth pin P28. The controller interface circuit 230a may discriminate the status information of the storage device <NUM> on the basis of the ready/busy output signal nR/B.

<FIG> is a block diagram showing the storage device of <FIG>.

Referring to <FIG>, the storage device <NUM> may include a control logic circuit <NUM>, a memory cell array <NUM>, a page buffer unit <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. Although not shown in <FIG>, the storage device <NUM> may further include the memory interface circuit 230b shown in <FIG>, and may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The control logic circuit <NUM> may generally control various operations inside the storage device <NUM>. The control logic circuit <NUM> may output various control signals in response to the command CMD and/or the address ADDR from the memory interface circuit 230b. For example, the control logic circuit <NUM> may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array <NUM> may be connected to the page buffer unit <NUM> through the bit lines BL, and may be connected to the row decoder <NUM> through word lines WL, string selection lines SSL, and ground selection lines GSL.

In an embodiment, the memory cell array <NUM> may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on the substrate. In an embodiment, the memory cell array <NUM> may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings placed along row and column directions.

The page buffer unit <NUM> may include a plurality of page buffers PB1 to PBn (n is an integer of three or more), and each of the plurality of page buffers PB1 to PBn may be connected to the memory cells through a plurality of bit lines BL. The page buffer unit <NUM> may select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer unit <NUM> may operate as an entry driver or a detection amplifier, depending on the operating mode. For example, at the time of the program operation, the page buffer unit <NUM> may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. At the time of the read operation, the page buffer unit <NUM> may detect the current or voltage of the selected bit line and detect the data stored in the memory cell.

The voltage generator <NUM> may generate various types of voltages for performing program, read, and erasure operations on the basis of the voltage control signal CTRL_vol. For example, the voltage generator <NUM> may generate a program voltage, a read voltage, a program verification voltage, an erasure voltage, and the like, as a word line voltage VWL.

The row decoder <NUM> may select one of a plurality of word lines WL, and select one of a plurality of string selection lines SSL in response to the row address X-ADDR. For example, the row decoder <NUM> may apply a program voltage and a program verification voltage to the selected word line at the time of the program operation, and may apply a read voltage to the selected word line at the time of the read operation.

<FIG> is a diagram for explaining a 3D V-NAND structure according to some embodiments.

When the storage module of the storage device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the storage module may be represented by an equivalent circuit as shown in <FIG>.

A memory block BLKi shown in <FIG> shows a three-dimensional memory block formed in a three-dimensional structure on the substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to <FIG>, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. A plurality of memory NAND strings NS11 to NS33 may each include a string selection transistor SST, a plurality of memory cells MC1, MC2,. , MC8, and a ground selection transistor GST. Although <FIG> shows that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2,. , MC8, the embodiment is not necessarily limited thereto.

The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. The plurality of memory cells MC1, MC2,. , MC8 may each be connected to the corresponding gate lines GTL1, GTL2,. , and GTL8. The gate lines GTL1, GTL2,. , GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2,. , GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

The word lines (e.g., WL1) of the same height are connected in common, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Although <FIG> shows that the memory block BLK is connected to eight gate lines GTL1, GTL2,. , and GTL8 and three bit lines BL1, BL2, and BL3, the embodiment is not necessarily limited thereto.

<FIG> is a flowchart for explaining the operation of the memory system according to some embodiments. <FIG> are diagrams for explaining the operation of the memory system according to some embodiments.

First, referring to <FIG>, the host device <NUM> transmits a command for requesting the EOM (Eye Open Monitor) operation performance to the memory device <NUM> (S110).

In some embodiments, such a request command may be implemented in the form of WRITE BUFFER COMMAND shown in <FIG> which complies with the JEDEC UFS standard. <FIG> is a diagram showing a CDB (Command Descriptor Block) of a WRITE BUFFER COMMAND which complies with the JEDEC UFS standard, and <FIG> is a diagram showing a description of the mode (MODE) field setting values of the WRITE BUFFER COMMAND.

Specifically, referring to <FIG>, <FIG> and <FIG>, the UFS host controller <NUM> of the host device <NUM> sets the mode (MODE) field of the WRITE BUFFER COMMAND to 1F, and may request the UFS device controller <NUM> of the memory device <NUM> to perform the EOM operation. Further, the UFS device controller <NUM> that receives the request may prepare for the EOM operation.

In some embodiments, the operations of the UFS host controller <NUM> and the operations of the UFS device controller <NUM> may be performed by controlling the UFS host controller <NUM> and the UFS device controller <NUM> using a predetermined firm ware. However, the embodiments are not limited thereto.

Referring to <FIG> shows an example in which the EOM operation is requested when the setting value of the mode (MODE) field of WRITE BUFFER COMMAND is 1F. However, the embodiment is not limited to the shown example. If necessary, the setting value of the mode (MODE) field that requests the EOM operation may be modified into another setting value (for example, other setting values set as 'Reserved' in the standard specifications such as 1D and 1E).

On the other hand, referring to <FIG> and <FIG>, the UFS host controller <NUM> may send the size of EOM data to be described later to the UFS device controller <NUM>, using a parameter list length field of the WRITE BUFFER COMMAND.

Next, referring to <FIG>, the memory device <NUM> transmits response to the WRITE BUFFER COMMAND to the host device <NUM> (S120).

In some embodiments, such a response may include data capacity information which is receivable by the memory device <NUM>. That is, when the memory device <NUM> responds to the host device <NUM>, for example, by k (k is a natural number) bytes as a response, the host device <NUM> may transmit data to be transmitted to the memory device <NUM> later (for example, data necessary for performing the EOM operation) by dividing the data in units of k bytes.

Next, referring to <FIG>, the host device <NUM> transmits the generated EOM data to the memory device <NUM>, and the memory device <NUM> transmits the response to the EOM data reception to the host device <NUM> (S130, S140).

In this embodiment, the host device <NUM> may generate the EOM data required for the EOM operation to be performed in the memory device <NUM>.

A generation time point of the EOM data may be before a time point (S110) when the host device <NUM> transmits a command for requesting the EOM operation performance to the memory device <NUM>, and may be after a time point (S120) when the response to WRITE BUFFER COMMAND is received from the memory device <NUM> to the host device <NUM>.

Further, in some embodiments, the generation time point of the EOM data may be a time point between the time point (S110) when the host device <NUM> transmits the command for requesting the EOM operation performance to the memory device <NUM> and the time point (S120) when the response to WRITE BUFFER COMMAND is received from the memory device <NUM> to the host device <NUM>. That is, the timing when the host device <NUM> generates the EOM data required for the EOM operation to be performed in the memory device <NUM> may be modified as much as possible.

In some embodiments, the EOM data generated by the host device <NUM> may include parameters required for performing the EOM operation and pattern data required for performing the EOM operation.

In some embodiments, the parameters required for performing the EOM operation may include offset values dX and dY required for performing the EOM operation of the memory device <NUM> described above.

An offset value dX may include a time offset value, a phase offset value, and the like, and an offset value dY may include a voltage offset value, or the like. However, the embodiments are not limited thereto.

Further, the parameters required for performing the EOM operation may include phase resolution information. Such phase resolution information may be used for receiving the pattern data from the host device <NUM> by the memory device <NUM>.

In some embodiments, the pattern data necessary for performing the EOM operation is a serial bit (SB of <FIG>) provided from the host device <NUM> required to perform the EOM operation of the memory device <NUM> described above.

In some embodiments, the host device <NUM> may generate a plurality of pattern data, and such a plurality of pattern data are generated by combination of various bit sequences as much as possible, and the EOM operation performance result may be generated using a consistent data pattern. A symbol in the pattern data may be referred to as a pattern symbol.

Although examples of the pattern data include PRBS (pseudorandom binary sequence) data, CRPAT (Compliant Random Test Pattern) data, CJTPAT (Compliant jitter tolerance pattern) data, and the like, the embodiments are not limited thereto.

<FIG> is a diagram showing a structure of EOM data transmitted to the memory device <NUM> by the host device <NUM> according to some embodiments.

Referring to <FIG>, the EOM data may include an EOM data header EDH and an EOM data pattern EDP.

The EOM data header EDH may include parameters required to perform the EOM operation. For example, the phase selection field (PHASE SELELCT) includes the time offset value or phase offset value to be sent to the memory device <NUM>, and the reference voltage control field (VREF CONTROL) may include a voltage offset value to be sent to the memory device <NUM>.

That is, the time offset value or the phase offset value required to perform the EOM operation described above referring to <FIG> and <FIG> in the memory device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the phase selection field (PHASE SELELCT). Also, the voltage offset value required to perform the EOM operation described above referring to <FIG> and <FIG> in the memory device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the reference voltage control field (VREF CONTROL).

On the other hand, the phase resolution information (gear information) referred to by the memory device <NUM> for receiving the pattern data from the host device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the phase resolution field (PHASE RESOLUTION).

Further, the number of samplings performed (number of samples obtained) by the memory device <NUM> while performing the EOM operation may be provided from the host device <NUM> to the memory device <NUM> through the sampling number field (NUMBER OF SAMPLING).

Further, the size of the pattern data to be received from the host device <NUM> by the memory device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the data length field (EOM DATA LENGTH).

Although <FIG> shows an example of an EOM data header EDH made up of <NUM> bytes, the embodiments are not limited thereto, and the size of the EOM data header EDH may be modified as much as possible.

The EOM data pattern EDP may include pattern data necessary for performing the EOM operation. As shown in <FIG>, the EOM data pattern EDP may include a plurality of pattern data. In some embodiments, N shown in <FIG> may be a natural number greater than <NUM>.

Referring to <FIG>, the EOM data header EDH and the EOM data pattern EDP may be transmitted from the host device <NUM> to the memory device <NUM> several times. At this time, receivable data capacity information by which the memory device <NUM> responses to the host device <NUM> in step S110 of <FIG> above may be considered in determining a method of transmitting the EOM data header EDH and the EOM data pattern EDP to the memory device <NUM> from the host device <NUM>.

For example, in step S110 of <FIG>, if the receivable data capacity information by which the memory device <NUM> responds to the host device <NUM> is <NUM> bytes, the host device <NUM> may transmit the EOM data header EDH and the EOM data pattern EDP to the memory device <NUM> by the method as shown in <FIG>.

Specifically, the host device <NUM> first transmits the EOM data header EDH having a <NUM>-byte size to the memory device <NUM> (S130a). Further, the memory device <NUM> responds to the host device <NUM> that the EOM data header EDH is received (S140a).

Subsequently, the host device <NUM> transmits the <NUM>-byte size EOM data pattern EDP among the EOM data pattern EDP to the memory device <NUM> (S130b). Further, the memory device <NUM> responds to the host device <NUM> that the EOM data pattem EDP is received (S140b). Further, the host device <NUM> transmits the subsequent <NUM>-byte size EOM data pattern EDP among the EOM data pattern EDP to the memory device <NUM> (S130c). Further, the memory device <NUM> responds to the host device <NUM> that the EOM data pattern EDP is received (S140c). By repeating such a manner, all the EOM data patterns EDP shown in <FIG> may be provided from the host device <NUM> to the memory device <NUM>.

On the other hand, the structure of the EOM data to be transmitted to the memory device <NUM> by the host device <NUM> is not limited to the example shown in <FIG>.

<FIG> is a diagram showing a structure of EOM data to be transmitted to the memory device <NUM> by the host device <NUM> according to some other embodiments.

The EOM data header EDH may include the parameters required to perform the EOM operation.

For example, a timing offset field and a timing step field may include a time offset value or a phase offset value to be sent to the memory device <NUM>, and a voltage offset field and a voltage step field may include the voltage offset value to be sent to the memory device <NUM>.

That is, the time offset value or phase offset value required to perform the EOM operation described above referring to <FIG> and <FIG> in the memory device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the timing offset field and the timing step field. Further, the voltage offset values required to perform the EOM operation described above referring to <FIG> and <FIG> in the memory device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the voltage offset field and the voltage step field.

That is, in this embodiment, the offset value dX and the offset value dY shown in <FIG> and <FIG> are not indicated by one value as in the embodiment shown in <FIG>, but are expressed by two fields of the reference value (reference phase or reference voltage) and the offset value of the reference value (offset phase value or offset voltage value).

On the other hand, the number of samplings performed by the memory device <NUM> while performing the EOM operation may be provided from the host device <NUM> to the memory device <NUM> through the sampling number field (Number of Sampling).

Further, the size of the pattern data to be received to the memory device <NUM> from the host device <NUM> may be provided from the host device <NUM> to the memory device <NUM> through the data length field (Total Data Length).

Referring to <FIG> again, the memory device <NUM> provided with the EOM data performs the EOM operation (S150).

In some embodiments, the EOM operation may be performed during reception of the EOM data pattern (EDP of <FIG>) after the EOM data header (EDH of <FIG>) is received. However, the embodiments are not limited thereto, and the EOM operation may also be performed after all the EOM data patterns (EDP of <FIG>) have been received.

Referring to <FIG> and <FIG>, the comparator 255b may perform an error counting operation of outputting an error counting signal EC to each symbol in the pattern data provided from the host device <NUM>, and a sampling count operation of outputting a sampling count signal SC.

Referring to <FIG> and <FIG>, if the symbol in the pattern data EDP is a data symbol D, the non-data symbol detector <NUM> does not output the control signal CS. As a result, the comparator 255b performs the error counting operation of outputting the error count signal EC and the sampling count signal SC (a CO section).

After that, if the symbol in the pattern data EDP is the filler symbol F, the non-data symbol detector <NUM> outputs the control signal CS. As a result, the comparator 255b does not perform the error counting operation of outputting the error count signal EC and the sampling count signal SC (an NCO section). As a result, the EOM operation is not performed on the filler symbol F in the pattern data EDP (e.g. the EOM operation is inhibited).

The sampling count signal SC may be used to determine whether the sampling number of the sampling number field (NUMBER OF SAMPLING) provided to the memory device <NUM> from the host device <NUM> is the same as the sampling number performed by the memory device <NUM>.

The error count signal EC may be used to calculate the error count value corresponding to the phase offset value provided through the phase selection field (PHASE SELELCT) and the voltage offset value provided through the reference voltage control field (VREF CONTROL), for all pattern data received from the host device <NUM>.

For example, if one hundred data symbols and one hundred filler symbols are transmitted to the pattern data EDP from the host device <NUM> for performing the EOM operation of the memory device <NUM>, the comparator 255b performs the error counting operation on the one hundred data symbols, but does not perform the error counting operation on the one hundred filler symbols.

Referring to <FIG> again, after performing the EOM operation, the memory device <NUM> transmits a response signal including the performance result of the EOM operation to the host device <NUM> (S160).

At this time, the response signal may include the success or failure of the EOM operation performance, and the error count value corresponding to the phase offset value and the voltage offset value. In this embodiment, such an error count value is an error count value of a data symbol in the pattern data EDP.

For example, if the sampling number of the sampling number field (NUMBER OF SAMPLING) provided from the host device <NUM> to the memory device <NUM> is the same as the number of sampling count signal SC output from the comparator 255b of the memory device <NUM>, the memory device <NUM> may determine that the EOM operation performance is completed, and may transmit completion information to the host device <NUM>.

In contrast, if the sampling number of the sampling number field (NUMBER OF SAMPLING) provide from the host device <NUM> to the memory device <NUM> is different from the number of the sampling count signal SC output from the comparator 255b of the memory device <NUM>, the memory device <NUM> may determine that the EOM operation performance is not completed, and may transmit failure information to the host device <NUM>.

<FIG> is a diagram showing a structure of a response UFS protocol information unit (UPIU) to be transmitted to the host device <NUM> by the memory device <NUM> according to some embodiments.

In some embodiments, although the success or failure of the EOM operation performance may be provided to the host device <NUM>, for example, through the response field (Response) shown in <FIG>, the embodiment is not limited thereto.

Also, in some embodiments, although the error count values described above may be provided to, for example, the host device <NUM> through the four sense data fields (Sense Data[<NUM>], Sense Data[<NUM>], Sense Data[<NUM>], and Sense Data[<NUM>]) shown in <FIG>, the embodiment is not limited thereto.

The EOM operation performance result thus generated may be referred to and used for changing the signal driving characteristics of the host device <NUM> or changing the signal receiving characteristics of the memory device <NUM>.

In the memory system described above, another external device is not required to grasp the quality characteristics of the signals transmitted and received between the host device <NUM> and the memory device <NUM>. Further, the signal line on which the EOM operation is performed is also the same as the signal line on which the host device <NUM> and the memory device <NUM> actually transmit and receive signals. This makes it possible to perform the EOM operation which is easy and has high reliability. Also, since the EOM operation is not performed on the filler symbol, it is possible to improve the reliability of EOM measurement.

<FIG> is a flowchart for explaining the operation of the memory system according to some other embodiments.

Hereinafter, repeated explanation of the above-described embodiment will be omitted as much as possible, and differences will be mainly described.

Referring to <FIG>, the host device <NUM> transmits a command for requesting the EOM operation performance to the memory device <NUM> (S200). Further, the memory device <NUM> transmits a response to the WRITE BUFFER COMMAND to the host device <NUM> (S210).

Subsequently, the memory device <NUM> transmits the pattern data necessary for performing the EOM operation to the host device <NUM> (S220).

Referring to <FIG>, in some embodiments, although the pattern data necessary for performing the EOM operation is stored in the non-volatile memory <NUM> of the memory device <NUM>, and then may be transmitted to the host device <NUM>, the embodiments are not limited thereto.

That is, in this embodiment, unlike the embodiment described above referring to <FIG>, the host device <NUM> does not generate the pattern data necessary for performing the EOM operation, but uses the pattern data stored in the memory device <NUM> for performing the EOM operation.

After that, the host device <NUM> transmits the EOM data including the parameters necessary for performing the EOM operation and the pattern data received from the memory device <NUM> to the memory device <NUM> (S230). Further, the memory device <NUM> transmits a response to the reception of the EOM data to the host device <NUM> (S240). The memory device <NUM> provided with the EOM data performs the EOM operation (S250), and the memory device <NUM> that performs the EOM operation transmits a response signal including the EOM operation performance result to the host device <NUM> (S260).

<FIG> is a diagram showing a non-data symbol detector according to some other embodiments. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to <FIG>, the non-data symbol detector <NUM> may include a comparison logic 254a which receives the N-bit signal that is output from the deserializer 253a, and determines whether the N-bit signal is a predetermined symbol. In some embodiments, although the N-bit signal is a <NUM>-bit signal, the embodiments are not limited thereto.

In this embodiment, the comparison logic 254a may further determine whether the N-bit signal is a D07. <NUM> symbol which means filler data. When the received signal is a scrambled signal, the comparison logic 254a may determine whether the N-bit signal is a D07. <NUM> symbol and determine the filler symbol.

Specifically, the comparison logic 254a determines whether the input signal is the D07. <NUM> symbol which is <NUM> or <NUM> when the N-bit signal is a <NUM>-bit signal, and if the input signal corresponds to the D07. <NUM> symbol, the comparison logic 254a may provide the control signal CS for stopping the performance of the error count operation to the comparator (255b of <FIG>). Accordingly, the comparator (255b of <FIG>) may not perform the EOM operation on the filler symbol.

<FIG> is a diagram showing a UIC layer according to some other embodiments. <FIG> is a diagram for explaining the operation of the UIC layer according to some other embodiments. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to <FIG> and <FIG>, in this embodiment, the non-data symbol detector (<NUM> of <FIG>) is not placed in the CDR block (<NUM> of <FIG>) of a front stage of the decoder <NUM>, but the distinction signal DS output from the decoder <NUM> is used as the control signal of the comparator 255b.

The decoder <NUM> may compare the input N-bit signal with the data symbol lookup table and the control symbol lookup table. Further, when the N-bit signal is a data symbol, the decoder <NUM> may output the M-bit signal and the data signal D as the distinction signal DS. Further, when the N-bit signal is the control symbol, the decoder <NUM> may output the M-bit signal and the control signal K as the distinction signal DS. In some embodiments, although the N-bit signal may be a <NUM>-bit signal and the M-bit signal may be an <NUM>-bit signal, the embodiments are not limited thereto.

When the distinction signal DS output from the decoder <NUM> is the data signal D, the comparator 255b according to the present embodiment performs the error counting operation and performs EOM, and when the distinction signal DS to be output is the control signal K, the error counting operation is not performed and the EOM is not performed (e.g. the EOM operation is inhibited). Accordingly, the EOM is not performed on all control symbols including the filler symbol described above.

<FIG> is a diagram showing a UIC layer according to some other embodiments. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to <FIG>, in the present embodiment, when the received signal is a scrambled signal, the descrambling is performed through the descrambler <NUM>, and the signal is provided to the symbol remover <NUM>. Here, when the symbol remover <NUM> performs the operation of removing the skip symbol which is a non-data symbol, the symbol remover <NUM> generates the control signal CS and provide it to the comparator (e.g., 255b of <FIG>), thereby stopping, or inhibiting, the error counting operation. According to such a configuration, there may be a slight delay between the time point when the non-data symbol is received to the CDR block <NUM> and the time point when the error counting operation of the comparator (e.g., 255b of <FIG>) is stopped.

<FIG> are diagrams for explaining a method for performing the EOM operation according to some embodiments.

Referring to <FIG>, a physical layer of the signal receiver (e.g., UIC layer <NUM> of <FIG>) may include a PMA (Physical Medium Attachment) block (PMA) and a PCS (Physical Coding Sublayer) block.

The PMA block (PMA) may receive P-bit (P is a natural number) data, decode the P-bit data, and output Q-bit (Q is a natural number smaller than P) data and a sync bit including <NUM> bits. In some embodiments, although the P-bit data may include <NUM>-bit data and the Q-bit data may include <NUM>-bit data, the embodiments are not limited thereto.

The sync bit including <NUM> bits may be defined as shown in <FIG>. That is, when the sync bit is <NUM> or <NUM>, this case indicates that there is an error in the P-bit data. When the sync bit is <NUM>, this case indicates that the P-bit data is a data bit. When the sync bit is <NUM>, this case may indicate that the P-bit data is a control bit.

The PMA block (PMA) may stop (or inhibit) the EOM operation performance, including the error counting operation, when <NUM>-bit sync bits are <NUM>.

<FIG> is a diagram showing a memory system according to some other embodiments. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to <FIG>, in this embodiment, the UIC layer <NUM> of the host device <NUM> performs the above-mentioned EOM operation. For example, the UIC layer <NUM> of the host device <NUM> may perform the EOM operation on the differential output signal pairs DOUT_T and DOUT_C received from the memory device <NUM>.

Referring to <FIG>, in this embodiment, both the UIC layer <NUM> of the host device <NUM> and the UIC layer <NUM> of the memory device <NUM> perform the aforementioned EOM operation.

<FIG> is a diagram showing a data transmitting/receiving device system according to some embodiments.

Referring to <FIG>, a first data transmitting/receiving device <NUM> includes a first interface <NUM>. The second data transmitting/receiving device <NUM> includes a second interface <NUM>.

The first interface <NUM> and the second interface <NUM> may perform the aforementioned EOM operation. That is, the data symbol sent between the first data transmitting/receiving device <NUM> and the second data transmitting/receiving device <NUM> may be subjected to the EOM operation including the error counting, and the control symbol including the filler symbol may not be subjected to the EOM operation including the error counting.

In some embodiments, the first data transmitting/receiving device <NUM> may be a camera module, and the second data transmitting/receiving device <NUM> may be an application processor. Further, in some embodiments, the first data transmitting/receiving device <NUM> may be a display driver IC, and the second data transmitting/receiving device <NUM> may be a display panel. In addition, the first data transmitting/receiving device <NUM> and the second data transmitting/receiving device <NUM> may be implemented by being modified into various electronic devices which are not shown.

<FIG> is a flowchart for explaining the EOM performance operation.

Referring to <FIG>, an initial offset value is set (S300).

For example, referring to <FIG> and <FIG>, the host device <NUM> may set offset values to be included in the EOM data header EDH (e.g., a value to be included in the phase selection field (PHASE SELELCT) and/or a value to be included in a reference voltage control field (VREF CONTROL)).

Next, the EOM operation is performed at the set offset value (S310). Further, the EOM result is checked and the preset value is stored (S320).

For example, the host device <NUM> and the memory device <NUM> may perform the EOM operation described above and check the result.

If the EOM operation for all offset values is not performed (S330-N), the offset value is changed (S340), the EOM operation is performed, the result is checked, and the new preset value is stored (S310, S320). That is, the EOM operation may be performed on offset values of the number enough to grasp the quality characteristics of the signal transmitted and received between the host device <NUM> and the memory device <NUM>, and the preset values may be stored.

If the EOM operation for all offset values is performed (S330-Y), parameters of the transmission terminal and reception terminal of the host device <NUM> and the memory device <NUM> are set on the basis of the EOM results (S350).

For example, the host device <NUM> may set parameters related to signal driving or reception on the basis of the EOM results, and the memory device <NUM> may also set parameters related to signal driving or reception. However, the embodiments are not limited thereto, and the setting method of the transmission and reception parameters may be modified as much as possible.

<FIG> illustrates logic <NUM> for improving EOM performance according to the embodiments described above. At operation <NUM> of <FIG>, a command requesting an EOM operation is received. At operation <NUM>, a waveform is received. At operation <NUM>, errors associated with data symbols are counted. A counting of errors associated with non-data symbols is inhibited at operation <NUM>. At operation <NUM>, an EOM signal is sent to a host with the improved error count.

Claim 1:
A method of operating a memory device, the method comprising:
receiving (<NUM>), from a host device (<NUM>), a command requesting an Eye Open Monitor, hereinafter referred to as EOM, operation;
receiving (<NUM>) pattern data including one or more data symbols and one or more non-data symbols from the host device (<NUM>), wherein the one or more data symbols includes an information symbol and/or a pattern symbol;
counting (<NUM>), in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols;
not counting, in the error count, second errors corresponding to the one or more non-data symbols; and
transmitting (<NUM>), to the host device (<NUM>), an EOM response signal including the error count.