Patent Description:
For a device that transmits data via serial communication, there is a system having a mechanism to transmit multiple pieces of data to a plurality of data transmission devices by daisy-chaining the data transmission devices. In such a system, it is necessary to transmit data by superimposing multiple data strings on a serial communication path. Methods of superimposing different pieces of data on the serial communication path include a method to packetize data and transmit packets of the data and a time-division multiplex (TDM) method to divide the path by a fixed length of time and transmit data. By using the TDM method, it becomes possible to superimpose multiple stable bands in a simple circuit configuration. There are disclosed literatures regarding data transmission by the TDM method, for example, PTL <NUM>, etc..

Patent Literature <CIT> discloses methods and apparatus for transporting digital audio-related signals over point-to-point, non-circuit-switched, non-packet-based, local area connections.

Literature <NPL> discloses a <NUM> Mbit/s multiservice optical local area network (LAN) using as synchronous TDM loop structure.

Patent Literature <CIT> disclose systems and methods for clock sustain in a two-wire communication systems and applications thereof.

In a case where serial data is transmitted between daisy-chained data transmission devices, it is necessary to cause an entire network to work in synchronization with one data transmission device. However, even if the one data transmission device to be the basis of a clock becomes unnecessary, it is not possible to remove the one data transmission device from a system, which makes it difficult to dynamically switch the daisy chain connection. Furthermore, a serial transmission path from the one data transmission device also serves as a clock transmission path; therefore, in a case where there arises an issue in communication between the data transmission devices, transmission that does not have an issue also suffers disruption of communication.

According to the present disclosure, there is provided a serial data transmission device as defined in the appended set of claims.

According to the present disclosure, there is provided a serial data transmission device including: a receiver that receives data serially transmitted by a time-division multiplex method from another device daisy-chained to the serial data transmission device; a transmitter that serially transmits data by the time-division multiplex method to another device daisy-chained to the serial data transmission device; and a controller that controls serial transmission by the receiver and the transmitter, in which the controller performs control to make the serial transmission by the transmitter adjustable.

Furthermore, according to the present disclosure, there is provided a clock recovery device including: a receiver that receives data from another device; and a clock recovery circuit that recovers a clock by means of a fractional PLL in accordance with reception of the data by the receiver, in which the clock recovery circuit calculates a division ratio of a frequency divider of the fractional PLL from a value obtained by computing a counter value of a first counter that counts up at timing of reception of data by the receiver and counts down at timing of a recovered clock.

As described above, according to the present disclosure, it is possible to provide novel and improved serial data transmission device and clock recovery device that make it possible to dynamically switch a band or a data transmission path and enhance the stability to failure while multiplexing and transmitting data by the TDM method when serial data is transmitted between a plurality of daisy-chained data transmission devices.

It is to be noted that the effects described above are not necessarily limitative, and there may be any of effects described in the present specification or another effect conceivable from the present specification besides the above-described effects or instead of the above-described effects.

In the following, preferred embodiments of the present disclosure are described in detail with reference to accompanying drawings. It is to be noted that in the present specification and the drawings, components having substantially the same functional configuration are assigned the same reference numeral to omit repetition of description.

It is to be noted that description is given in the following order.

First, an outline of a first embodiment of the present disclosure is described.

For a device that transmits data via serial communication, there is a system having a mechanism to transmit multiple pieces of data to a plurality of data transmission devices by daisy-chaining the data transmission devices. In such a system, it is necessary to transmit data by superimposing multiple data strings on a serial communication path. Methods of superimposing different pieces of data on the serial communication path include a method to packetize data and transmit packets of the data and a time-division multiplex (TDM) method to divide the path by a fixed length of time and transmit data.

The packet division method is a method of dividing data into data strings having a given length and transmitting the data added with header information representing what information the data is about. While this method has a high degree of freedom in use of a serial communication band, the timing to transmit a packet to the communication path varies, and thus a transmitter and a receiver have to store packets to adjust the timing, which requires a large memory and increases the communication latency.

On the other hand, the TDM transmission method is a method of using the serial communication path divided by a fixed length of time. By using the TDM method, it becomes possible to superimpose multiple stable bands in a simple circuit configuration. However, in a case of performing daisy chain transmission using the TDM method in this way, it generally requires network synchronization of an entire network.

<FIG> is an explanatory diagram illustrating a serial data transmission system in which three serial data transmission devices 100a, 100b, and 100c are daisy-chained. In a case where serial transmission is performed between the three daisy-chained serial data transmission devices 100a, 100b, and 100c, for example, it is necessary to cause the entire network to work in synchronization with the serial data transmission device 100a.

Here, when there is introduced a system that dynamically switches the data input/output or the band allocation of each serial data transmission device, the clock of the serial data transmission device 100a is necessary at all times; therefore, even in a case where the serial data transmission device 100a becomes unnecessary, it is not possible to disconnect the serial data transmission device 100a. Therefore, in the system that dynamically switches the data input/output or the band allocation of each serial data transmission device, it is difficult to dynamically switch the daisy chain connection. Furthermore, a serial transmission path from the serial data transmission device 100a also serves as a clock transmission path; therefore, in a case where an issue occurs in communication between the serial data transmission device 100a and the serial data transmission device 100b, transmission on an unrelated path also suffers disruption of communication.

Accordingly, in the present embodiment, there is provided a technology that makes it possible to dynamically switch a band or a data transmission path and enhance the stability to failure while multiplexing and transmitting data by the TDM method when serial data is transmitted between a plurality of daisy-chained data transmission devices.

Subsequently, a configuration example and an operation example of the serial data transmission system according to the present embodiment are described. In the present embodiment, as illustrated in <FIG>, the serial data transmission system in which the plurality of (three, in <FIG>) serial data transmission devices 100a, 100b, and 100c are daisy-chained is used. The serial data transmission devices 100a, 100b, and 100c each have a data input port and/or a data output port. Respective pieces of data inputted to the serial data transmission devices 100a and 100b are superimposed and transmitted in TDM serial transmission. In <FIG>, the serial data transmission device 100a and the serial data transmission device 100b are coupled by a transmission path 10a, and the serial data transmission device 100b and the serial data transmission device 100c are coupled by a transmission path 10b.

A signal serially transmitted in the serial data transmission system illustrated in <FIG> is divided by a time unit called SLOT that is a unit of specific size. Each SLOT is assigned a number, and all SLOTs are transmitted in sequence. A unit of a cycle of these SLOT numbers is called a frame. Furthermore, a control code other than SLOT data is allotted a certain period of time, and is used for low-speed control channel transmission of other than the SLOT data. <FIG> is an explanatory diagram illustrating a relationship among SLOT, control code, and frame. In the present embodiment, one frame includes eight SLOTs and eight control codes. Needless to say, the respective numbers of SLOTs and control codes included in one frame are not limited to this example.

The frame transmission period is fixed to an approximately constant period in the entire network; however, the number of SLOTs allocated for each serial transmission is able to be set to a different value. The data amount per SLOT is constant, and, as a result, the data rate of each serial transmission path in the daisy chain is able to be made variable as needed. Thus, it is possible to ensure the minimum band and reduce the power consumption.

<FIG> is an explanatory diagram illustrating a configuration example of the serial data transmission system according to the embodiment of the present disclosure. The serial data transmission devices 100a, 100b, and 100c have a similar configuration. Here, a configuration example of the serial data transmission device 100a is described with the serial data transmission device 100a as an example.

The serial data transmission device 100a includes a serial receiver 110a, a data unloader (unloader FIFO) 120a, a data buffer (daisy chain FIFO) 130a, a serial transmitter 140a, and a data loader (loader FIFO) 150a.

The serial receiver 110a receives data from the input-stage serial data transmission device through a transmission path (in the example illustrated in <FIG>, the input-stage serial data transmission device does not exist). Specific data, for example, data for the serial data transmission device 100a that the serial receiver 110a has received is read out from the data unloader 120a, and data for the other devices is sent to the data buffer 130a.

The data unloader 120a outputs the specific data, for example, the data for the serial data transmission device 100a that the serial receiver 110a has received in a first-in, first-out (FIFO) manner.

The data buffer 130a buffers data directed to the output-stage serial data transmission device (in the example illustrated in <FIG>, the serial data transmission device 100b or 100c). Then, the data buffer 130a sends the buffered data to the serial transmitter 140a in a FIFO manner. Therefore, the data buffer 130a temporarily stores, of the data received by the serial receiver 110a, data to be sent to the output-stage serial data transmission device, and outputs the stored data to the serial transmitter 140a.

The serial transmitter 140a outputs data directed to the output-stage serial data transmission device to the transmission path 10a. The data directed to the serial data transmission device includes data sent from the data buffer 130a and data sent from the data loader 150a.

The data loader 150a inputs data directed to the output-stage serial data transmission device. The data that the data loader 150a has inputted is sent to the serial transmitter 140a in a FIFO manner.

The serial data transmission devices each have a unique ID in the daisy chain connection. A data string loaded from each data transmission device has an ID of the serial data transmission device that has loaded it as a data ID. Then, through each of the transmission paths 10a and 10b, information of which of data SLOTs currently being transmitted is allocated data of what ID or is not allocated anything (hereinafter, this information is referred to as a Slot No/ID table) is transmitted by use of a control signal path.

<FIG> is an explanatory diagram that describes the Slot No/ID table transmitted through the transmission path of the serial data transmission system according to the present embodiment. In an example illustrated in <FIG>, SLOTs <NUM> to <NUM> are allocated data of ID <NUM>, SLOTs <NUM> and <NUM> are allocated data of ID <NUM>, and SLOTs <NUM> and <NUM> are allocated data of ID <NUM>. Each transmission device autonomously determines which of SLOTs is allocated data of what ID. An example of data allocation is described below.

<FIG> is an explanatory diagram for explaining how data is allocated in the serial data transmission system according to the present embodiment. The data loader (for example, the data loader 150a) built into each serial data transmission device determines the number of SLOTs desired to load data in accordance with content of input data or a request from a user. This number of SLOTs is referred to as LOAD_SLOT_SIZE in the present embodiment.

As illustrated in <FIG>, each serial data transmission device allocates as many pieces of data as the requested number of SLOTs to SLOTs, and performs transmission of the data through the transmission path. In an example of <FIG>, the serial data transmission device 100a determines LOAD_SLOT_SIZE = <NUM>, and assigns SLOTs <NUM> to <NUM> ID <NUM> that is an ID of the serial data transmission device 100a. The serial data transmission device 100b determines LOAD_SLOT_SIZE = <NUM>, and assigns SLOTs <NUM> and <NUM> ID <NUM> that is an ID of the serial data transmission device 100b, and assigns SLOTs <NUM> to <NUM> ID <NUM> that is an ID of the serial data transmission device 100a. The serial data transmission device 100c determines LOAD_SLOT_SIZE = <NUM>, and assigns SLOTs <NUM> and <NUM> ID <NUM> that is an ID of the serial data transmission device 100c, and assigns SLOTs <NUM> and <NUM> ID <NUM> that is an ID of the serial data transmission device 100b, and then assigns SLOTs <NUM> to <NUM> ID <NUM> that is an ID of the serial data transmission device 100a.

Here, for example, in a case where data to be loaded by the serial data transmission device 100b has run out, the serial data transmission device 100b stops allocation of data of ID <NUM> to SLOTs. As information that this allocation to SLOTs has been canceled is transmitted to a downstream device in the daisy chain, the allocation to SLOTs with ID1 is all canceled. However, as long as the transmission continues, assignments of other IDs are continued, and a change of allocated SLOTs is not made. Thus, it is possible for the serial data transmission system according to the present embodiment to continue the transmission of other data even when a particular serial data transmission device has stopped the transmission of data.

<FIG> is an explanatory diagram for explaining how data is allocated in the serial data transmission system according to the present embodiment. <FIG> illustrates an example where the serial data transmission device 100b stops allocation of data of ID <NUM> to SLOTs because data to be loaded by the serial data transmission device 100b has run out. As the serial data transmission device 100b has stopped the allocation of data of ID <NUM> to SLOTs, the output-stage serial data transmission device 100c also stops the allocation of data of ID <NUM> to SLOTs.

In this state, assume here that the serial data transmission device 100b again starts the transmission with LOAD_SLOT_SIZE set to <NUM>. In that case, each downstream serial data transmission device assigns empty SLOTs ID <NUM>. Also in this case, each downstream serial data transmission device uses the empty SLOTs without changing the existing assignments of the IDs. Therefore, it becomes possible for the serial data transmission system according to the present embodiment to re-start the data transmission by the serial data transmission device 100b without affecting the other data transmission.

<FIG> is an explanatory diagram for explaining how data is allocated in the serial data transmission system according to the present embodiment. The serial data transmission device 100b determines LOAD_SLOT_SIZE = <NUM>, and assigns SLOTs <NUM>, <NUM>, and <NUM> ID <NUM> that is an ID of the serial data transmission device 100b, and assigns SLOTs <NUM> to <NUM> ID <NUM> that is an ID of the serial data transmission device 100a. That is, the existing assignment of ID <NUM> is not changed. Then, the serial data transmission device 100c determines LOAD_SLOT_SIZE = <NUM>, and assigns SLOTs <NUM> and <NUM> ID <NUM> that is an ID of the serial data transmission device 100c, and assigns SLOTs <NUM>, <NUM>, and <NUM> ID <NUM> that is an ID of the serial data transmission device 100b, and then assigns SLOTs <NUM> to <NUM> ID <NUM> that is an ID of the serial data transmission device 100a.

Subsequently, SLOT mapping and a data transmission mechanism of the serial data transmission device are described. <FIG> is an explanatory diagram illustrating a functional configuration example of the serial data transmission device <NUM>.

The serial receiver <NUM> receives a Slot No/ID table <NUM> from the input-stage serial data transmission device through a control channel, and updates a transmitting-side Slot No/ID table <NUM> with a LOAD_SLOT_TABLE and an ID of its own device.

The serial data transmission device <NUM> updates the transmitting-side Slot No/ID table <NUM> in the following procedure.

First, the serial data transmission device <NUM> checks if as many IDs of SLOTs as those included in the receiving-side Slot No/ID table <NUM> exist in the transmitting-side Slot No/ID table <NUM>. In a case where the number of IDs included in the Slot No/ID table <NUM> is smaller than the number of IDs included in the Slot No/ID table <NUM>, the serial data transmission device <NUM> assigns an empty SLOT an additional ID. Meanwhile, in a case where the number of IDs included in the Slot No/ID table <NUM> is smaller than the number of IDs included in the Slot No/ID table <NUM>, the serial data transmission device <NUM> deletes the assignments of the IDs from the Slot No/ID table <NUM>.

Then, in a case where the Slot No/ID table <NUM> includes an ID that is not included in the Slot No/ID table <NUM> and is not its own ID, the serial data transmission device <NUM> deletes the ID.

Then, the serial data transmission device <NUM> checks if there are empty SLOTs equivalent to LOAD_SLOT_SIZE in the Slot No/ID table <NUM>. In a case where the number of empty SLOTs in the Slot No/ID table <NUM> is smaller than LOAD_SLOT_SIZE, the serial data transmission device <NUM> assigns an empty SLOT an additional ID. In a case where LOAD_SLOT_SIZE is smaller than the number of empty SLOTs in the Slot No/ID table <NUM>, the serial data transmission device <NUM> deletes the assignments of the IDs from the Slot No/ID table <NUM>.

Then, in a case where there is an ID that is not desired to be propagated in the daisy chain, the serial data transmission device <NUM> excludes the ID from the assignment, and deletes the assignment of the ID from the Slot No/ID table <NUM>.

Through this procedure, the serial data transmission device <NUM> is able to dynamically switch the data path without changing the once assigned SLOT numbers as much as possible and without changing the existing assignments of the IDs to SLOTs.

Using the Slot No/ID table <NUM>, the serial data transmission device <NUM> creates a Slot map table (a TX Slot map table). The Slot map table is generated by a map table generator <NUM>. The Slot map table is a table including, with respect to each SLOT, information of (<NUM>) allocation of a received SLOT + a number of the received SLOT, (<NUM>) allocation from the data loader <NUM>, and (<NUM>) no allocation. With reference to this table, the serial data transmission device <NUM> allocates data coming from the serial receiver <NUM> and data coming from the data loader <NUM> to SLOTs. Actual allocation is performed by a transmission stream mapper <NUM>. The transmission stream mapper <NUM> may serve as an example of a controller of the present disclosure. As described above, the frame transmission period is fixed to an approximately constant period in the entire network; however, the number of SLOTs allocated for each serial transmission is able to be set to a different value. Therefore, the transmission stream mapper <NUM> is able to make the data rate of the serial transmission path variable as needed by changing the number of SLOTs allocated for serial transmission to the output-stage serial data transmission device.

<FIG> is an explanatory diagram illustrating an example of data allocation to SLOTs by the serial data transmission device <NUM>. <FIG> illustrates an example of data allocation to SLOTs by the serial data transmission device <NUM> when data coming from the serial receiver <NUM> and data inputted from the data loader <NUM> are outputted on the basis of contents of a Slot map table.

Referring to the Slot map table, it is described that data of receiving-side SLOT <NUM> is allocated to transmitting-side SLOT <NUM>. Likewise, it is described that data of receiving-side SLOT <NUM> is allocated to transmitting-side SLOT <NUM>, and data of receiving-side SLOT <NUM> is allocated to transmitting-side SLOT <NUM>. Furthermore, it is described that data inputted from the data loader <NUM> is allocated to transmitting-side SLOTs <NUM>, <NUM>, and <NUM>. Then, it is described that nothing is allocated to transmitting-side SLOTs <NUM> and <NUM>.

Therefore, in the example of <FIG>, A2 that is the data of receiving-side SLOT <NUM> is stored in transmitting-side SLOT <NUM>; A3 that is the data of receiving-side SLOT <NUM> is stored in transmitting-side SLOT <NUM>; L0 that is the first data from the data loader <NUM> is stored in transmitting-side SLOT <NUM>; and L1 that is the second data from the data loader <NUM> is stored in transmitting-side SLOT <NUM>.

Likewise, A6 that is the data of receiving-side SLOT <NUM> is stored in transmitting-side SLOT <NUM>; and L2 that is the third data from the data loader <NUM> is stored in transmitting-side SLOT <NUM>. Furthermore, no data is allocated to transmitting-side SLOTs <NUM> and <NUM> (blank).

Data coming from the serial receiver <NUM> is inputted to the data buffer <NUM> having a width equivalent to the number of SLOTs (= a width equivalent to one frame). In a case where data on its own device side is desired by reference to the Slot map table, the serial data transmission device <NUM> outputs data of a corresponding SLOT. A read address of the data buffer <NUM> is incremented each time the transmitting side transmits one frame.

Data inputted from the data loader <NUM> is also temporarily stored in the FIFO, and, in a case where the data from the data loader <NUM> is desired by reference to the Slot map table, is read out from the FIFO and outputted from the serial transmitter <NUM>.

Furthermore, in a case where nothing is allocated to the Slot map table, some meaningless data is outputted from the serial transmitter <NUM>.

In either case, in a case where there exists no data when data is read out from the FIFO, non-typical invalid data (null) indicating that there is no data is outputted to a SLOT. Thus, even if the transmit frame rate becomes higher than the receive frame rate, data is automatically padded with this null data, and therefore it does not affect the data transmission.

In a case where the transmit frame rate is lower than the receive frame rate, a buffer overflow occurs in the data buffer <NUM>. Therefore, in a case where the transmit frame rate is lower than the receive frame rate, the serial data transmission device <NUM> increases the data transmission rate and controls the transmitting-side frame rate to be equal to or higher than the receiving-side frame rate, and then starts the transmission of data. At this time, the transmission data transmission rate is desired to be swept at a sufficiently low rate to prevent disconnection in the existing serial communication.

<FIG> is an explanatory diagram illustrating an example of a circuit configuration for controlling the clock speed of the serial transmitter <NUM> of the serial data transmission device <NUM>. In <FIG>, a division ratio control circuit <NUM> and a fractional phase-locked loop (PLL) <NUM> are illustrated. The fractional PLL <NUM> includes a fractional divider <NUM>, a phase comparator (a phase frequency detector (PFD)) <NUM>, a charge pump (CP) <NUM>, and a voltage-controlled oscillator (VCO) <NUM>.

The division ratio control circuit <NUM> receives a frame receive pulse from the serial receiver <NUM> and a frame transmit pulse from the serial transmitter <NUM>, and compares their periods. In a case where the period of the pulse from the serial transmitter <NUM> is longer, the fractional PLL <NUM> that generates a clock of the serial transmitter <NUM> is controlled to increase the data rate of the serial transmitter <NUM> until the respective periods of a frame receive pulse and a frame transmit pulse become equal. When the respective periods of a frame receive pulse and a frame transmit pulse have become equal, the serial data transmission device <NUM> accesses the data buffer and outputs data to the serial transmitter <NUM>. The serial data transmission device <NUM> performs feedback control at all times even after the restart of data transmission.

<FIG> is an explanatory diagram illustrating an example of a detailed circuit configuration for controlling the clock speed of the serial transmitter <NUM> of the serial data transmission device <NUM>. The division ratio control circuit <NUM> includes a period comparator <NUM>, a counter <NUM>, a multiplier <NUM>, a low-pass filter <NUM>, and an adder <NUM>. Then, <FIG> is a flowchart illustrating an operation example for controlling the clock speed of the serial transmitter <NUM>. A control phase of the clock speed of the serial transmitter <NUM> is divided into a coarse adjustment phase and a precise adjustment phase as illustrated in <FIG> to suppress large variation of clocks.

The division ratio control circuit <NUM> receives a frame receive pulse from the serial receiver <NUM> and a frame transmit pulse from the serial transmitter <NUM>, and compares their periods by means of the period comparator <NUM> (Step S101). If the period of the frame transmit pulse is longer than the period of the frame receive pulse, a given value is added to the counter <NUM> (Step S102), and the division ratio control circuit <NUM> returns to the comparison at Step S101. A counter value of the counter <NUM> is sent to the multiplier <NUM> and is multiplied by a predetermined gain constant, and passes through the low-pass filter <NUM> and becomes a division ratio additional value. The division ratio additional value is sent to the adder <NUM> and is added to a normal frequency division value, and then is provided as a division ratio to the fractional PLL <NUM>.

That is, in the coarse adjustment phase, by means of the period comparator <NUM>, the value of the counter is added up at constant speed until the period of a frame transmit pulse becomes equal to or longer than the period of a frame receive pulse. As a result, the rate of data transmission from the serial transmitter <NUM> is increased at a constant rate.

Meanwhile, if the period of a frame transmit pulse is shortened by the control of the division ratio control circuit <NUM>, and the period of a frame transmit pulse becomes shorter than the period of a frame receive pulse, the division ratio control circuit <NUM> makes the control phase transition to the precise adjustment phase. In the precise adjustment phase, the division ratio control circuit <NUM> starts the update of the counter value of the counter <NUM> based on the frame receive pulse and the frame receive pulse (Step S103). The counter value of the counter <NUM> is incremented by one if a frame receive pulse is inputted to the period comparator <NUM>, and, if a frame transmit pulse is inputted to the period comparator <NUM>, is decremented by one only in a case where the counter value is greater than <NUM>. That is, the counter value is controlled not to become <NUM> or less.

<FIG> is an explanatory diagram illustrating an example of control of the clock speed of the serial transmitter <NUM> of the serial data transmission device <NUM> in a graphic form. As illustrated in <FIG>, in the coarse adjustment phase, the rate of data transmission from the serial transmitter <NUM> is increased at a constant rate. Then, if the period of a frame transmit pulse becomes shorter than the period of a frame receive pulse, the control phase makes transition to the precise adjustment phase, and the period of a frame transmit pulse becomes closer to the period of a frame receive pulse to coincide with the period of a frame receive pulse. By performing control in this way, the division ratio control circuit <NUM> is able to bring the clock speed of the serial transmitter <NUM> closer to the receive rate of the serial receiver <NUM> without causing it to fluctuate around the receive rate of the serial receiver <NUM>.

As described above, according to the first embodiment of the present disclosure, there is provided the serial data transmission device <NUM> that makes it possible to realize, in a simple circuit configuration, the operation to change the state of daisy chain connection while keeping the existing data transmission or change the way of data superimposition when a large number of data strings are superimposed and transmitted simultaneously between the daisy-chained serial data transmission devices by the time-division multiplex method.

Subsequently, an outline of a second embodiment of the present disclosure is described.

In recent years, a system that performs communicating by imposing a signal on another transmit/receive clock having a different clock frequency from data to be transmitted when the data is transmitted through a signal path is widely used. In this case, a data receiver is required to extract a valid packet or word from received data, and recover a clock in accordance with the received data, and then output a signal imposed on the clock. For example, <CIT> discloses a configuration in which the data amount of arrived data is stored in a buffer, and a recovered clock frequency is increased or decreased depending on whether or not the stored amount is larger than a target threshold.

In this configuration, in a case where there is no fluctuation in a clock frequency of arrived data, the system works stably; however, in a case where the frequency fluctuates, the following capability of a clock with respect to fluctuation is weak, and there may be an issue in transmission stability. <FIG> is an explanatory diagram illustrating an example of variation in a recovered clock frequency in a case where an ideal recovered clock frequency varies in a typical clock recovery device. As illustrated in <FIG>, in the typical clock recovery device, in a case where the ideal recovered clock frequency varies, a recovered clock frequency comes closer to the ideal recovered clock frequency over time. Thus, the typical clock recovery device is weak in the following capability of a clock with respect to fluctuation.

Furthermore, in the existing method, binary control, in which a frequency is increased or decreased on the basis of whether or not a remaining capacity of the data buffer exceeds a threshold, is performed. Thus, when a clock frequency to be recovered fluctuates, as illustrated in <FIG>, a change rate of the recovered clock frequency is constant, and thus, when the frequency varies greatly, it requires a lot of time to follow it. Therefore, the size of the data buffer is also required to be increased to absorb a time lag of data at the time of this variation.

Accordingly, in the second embodiment of the present disclosure, there is provided a clock recovery device that makes it possible to improve tolerance for clock fluctuation and reduce the size of the data buffer at the same time.

In the following description, there is provided an example of a configuration for the serial receiver <NUM> to recover received data in the serial data transmission device <NUM> described in the first embodiment; however, the present disclosure is not limited to this example. The technology described in the present embodiment is also applicable to any device that extracts a valid packet or word from received data, and recovers a clock in accordance with the received data, and then outputs a signal imposed on the clock.

<FIG> is an explanatory diagram illustrating a configuration example of a clock recovery circuit in the serial data transmission device <NUM> according to the second embodiment of the present disclosure. In <FIG>, the serial receiver <NUM>, a data buffer <NUM>, a data counter <NUM>, a multiplier <NUM>, an adder <NUM>, and a fractional PLL <NUM> are illustrated. Then, the fractional PLL <NUM> includes a fractional divider <NUM>, a PFD <NUM>, a CP <NUM>, and a VCO <NUM>.

The clock recovery circuit illustrated in <FIG> creates a recovered clock from a receive clock received by the serial receiver <NUM> and received data synchronized with the clock by means of the fractional PLL <NUM>, and outputs recovered data imposed on the clock from the data buffer <NUM>.

The data counter <NUM> is a counter that counts up when having received data from the serial receiver <NUM>, and counts down on the basis of a recovered clock from the fractional PLL <NUM>. Therefore, if a frequency of the recovered clock from the fractional PLL <NUM> is lower than a frequency when the data has been received from the serial receiver <NUM>, a counter value of the data counter <NUM> becomes larger, and becomes smaller in an opposite case.

The multiplier <NUM> multiplies the counter value from the data counter <NUM> by a predetermined gain correction value and outputs the multiplied value. The adder <NUM> adds a predetermined reference value to the value outputted from the multiplier <NUM>. The adder <NUM> sends the value after the addition as a division ratio to the fractional divider <NUM>.

Using the division ratio sent from the adder <NUM>, the fractional PLL <NUM> generates a recovered clock from a reference clock. If the division ratio of the fractional divider <NUM> increases, a recovered clock frequency increases, and the fractional PLL <NUM> is subjected to feedback control to obtain a frequency desired to recover data through feedback to the fractional PLL <NUM>.

<FIG> is an explanatory diagram illustrating a schematic drawing of an open-loop transfer function of a control loop of the fractional PLL <NUM>. In a case where a loop band of the control loop of the fractional PLL <NUM> is set to a band lower than a PLL band, this loop is a primary loop, and becomes an inherently stable control loop. By setting the loop band of the control loop of the fractional PLL <NUM> to a band lower than the PLL band, the control stability is ensured, and at the same time, smooth following with respect to fluctuation in a clock becomes possible.

<FIG> is an explanatory diagram illustrating an example of variation in a recovered clock frequency in a case where an ideal recovered clock frequency varies in a typical clock recovery device. <FIG> is an explanatory diagram illustrating an example of variation in a recovered clock frequency in a case where an ideal recovered clock frequency varies in the clock recovery circuit illustrated in <FIG>. In the clock recovery circuit according to the present embodiment, when an ideal recovered clock frequency varies greatly, the frequency greatly follows the ideal frequency. As illustrated in <FIG>, the clock recovery circuit according to the present embodiment is therefore able to cause the frequency to follow the ideal frequency at higher speed than the typical clock recovery device. By causing the frequency to follow the ideal frequency at higher speed, the clock recovery circuit according to the present embodiment makes it possible to reduce a phase shift of the clock to be absorbed by the data buffer <NUM> and reduce the size of the data buffer <NUM>.

<FIG> is an explanatory diagram illustrating a modification example of the clock recovery circuit according to the second embodiment of the present disclosure. In <FIG>, the serial receiver <NUM>, the data buffer <NUM>, data counters <NUM> and <NUM>, the multiplier <NUM>, the adder <NUM>, a state machine <NUM>, and the fractional PLL <NUM> are illustrated.

The data counter <NUM> is a data counter that determines how many pieces of received data arrive in a given period of time on the basis of a reference clock. The data counter <NUM> determines how many pieces of received data arrive in the given period of time on the basis of a reference clock, thereby estimating an approximate frequency of a recovered clock. The data counter <NUM> estimates an approximate frequency of a recovered clock, and sends information of the frequency to the state machine <NUM>.

The state machine <NUM> outputs a gain correction value outputted to the multiplier <NUM>, a reference value outputted to the adder <NUM>, and setting of PLL mode outputted to the fractional PLL <NUM> on the basis of the information of the approximate frequency of the recovered clock sent from the data counter <NUM>. The setting of PLL mode outputted to the fractional PLL <NUM> is, for example, settings of a pre-divider (a divider provided in the input stage of the PFD <NUM>), a post-divider (the fractional divider <NUM>), and the VCO <NUM>, and the like.

The clock recovery circuit illustrated in <FIG> estimates an approximate frequency of a recovered clock by means of the data counter <NUM>, and changes the gain correction value, the reference value, and the setting of PLL mode by means of the state machine <NUM>, thereby making it possible to recover a clock over a wider range of frequencies.

<FIG> is a flowchart illustrating an operation example of the clock recovery circuit illustrated in <FIG>. The clock recovery circuit illustrated in <FIG> estimates a recovered clock speed by means of the data counter <NUM> (Step S111), and sets parameters for the fractional PLL <NUM> and setting of a division ratio by means of the state machine <NUM> (Step S112).

Then, the clock recovery circuit illustrated in <FIG> activates the data counter <NUM>, and starts feedback control on the fractional PLL <NUM> (Step S113), and then waits for the recovered clock to become stable (Step S114). Then, the clock recovery circuit illustrated in <FIG> starts writing of data in the data buffer <NUM> (Step S115), and waits for data stored in the data buffer <NUM> to reach a predetermined amount, for example, half the capacity of the data buffer <NUM>. When data stored in the data buffer <NUM> reaches the predetermined amount, the clock recovery circuit illustrated in <FIG> starts reading of data from the data buffer <NUM> (Step S116).

Here, if the value of the data counter <NUM> varies greatly, and the degree of variation exceeds a predetermined allowable value, i.e., an approximate frequency of a recovered clock varies greatly, the clock recovery circuit illustrated in <FIG> returns to the process at Step S111. A variation amount of the value of the data counter <NUM> that causes the clock recovery circuit to return to the process at Step S111 is not limited to a specific amount; however, for example, if a frequency of a recovered clock is increased and becomes a frequency that causes the data buffer <NUM> to be filled up with data in a predetermined time, the clock recovery circuit illustrated in <FIG> returns to the process at Step S111.

<FIG> is an explanatory diagram illustrating a modification example of the clock recovery circuit according to the second embodiment of the present disclosure. In <FIG>, the serial receiver <NUM>, the data buffer <NUM>, the data counters <NUM> and <NUM>, the multiplier <NUM>, the adder <NUM>, the state machine <NUM>, a low-pass filter <NUM>, and the fractional PLL <NUM> are illustrated.

The low-pass filter <NUM> is a digital low-pass filter for smoothing of fluctuation when a frequency of a recovered clock outputted from the fractional PLL <NUM> fluctuates. That is, the clock recovery circuit illustrated in <FIG> applies the low-pass filter <NUM> to the counter value of the data counter <NUM>, which makes it possible to suppress the fluctuation in a frequency of a recovered clock.

In <FIG>, a data output circuit <NUM> is also illustrated. The data output circuit <NUM> is a circuit that sends out a data request signal to the data buffer <NUM>, thereby reading out data stored in the data buffer <NUM> and outputting the read data. In a case of performing intermittent data output, the clock recovery circuit illustrated in <FIG> uses a data request signal from the data output circuit <NUM> as a trigger for subtraction of the data counter <NUM>. That is, the clock recovery circuit illustrated in <FIG> is able to apply feedback to the PLL to adjust a clock when the data output circuit <NUM> performs intermittent readout.

As described above, according to the first embodiment of the present disclosure, it is possible to provide the serial data transmission device <NUM> that makes it possible to realize, in a simple circuit configuration, the operation to change the state of daisy chain connection while keeping the existing data transmission or change the way of data superimposition when a large number of data strings are superimposed and transmitted simultaneously between the daisy-chained serial data transmission devices by the time-division multiplex method.

Furthermore, according to the second embodiment of the present disclosure, it is possible to provide the clock recovery device that performs counting based on the amount of data received and a clock generated by the fractional PLL, thereby making it possible to improve tolerance for clock fluctuation and reduce the size of the data buffer at the same time.

As above, the preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings; however, the technical scope of the present disclosure is not limited to these examples. It is obvious that those having ordinary skill in the technical field of the present disclosure could easily arrive at various alterations or modifications within the scope of the technical idea described in claims, and it is understood that these also should naturally fall under the technical scope of the present disclosure.

Claim 1:
A serial data transmission device (100a; 100b; 100c) comprising:
a receiver (110a; 110b; 110c) that is configured to receive first data allocated in a predetermined number of time slots (LOAD_SLOT_SIZE) during a frame transmission period, the time slots are serially transmitted by a time-division multiplex method with a predetermined receiving-side repetition period from a first device (100a; 100b; 100c) daisy-chained to the serial data transmission device (100a; 100b; 100c);
wherein the time slots in the time-division multiplex method have a specific size and are transmitted in sequence, and wherein the frame transmission period is a predetermined constant period,
a controller (145a, 150a; 145b, 150b; 145c, 150c) that is configured to determine a second number of time slots (LOAD_SLOT_SIZE) required for a second data to be transmitted by a time-division multiplex method with a predetermined transmitting-side repetition period the serial data transmission device (100a; 100b; 100c) to a second device (100a; 100b; 100c), and
is further configured to uniquely allocate the second data into the determined second number of time slots (LOAD_SLOT_SIZE), and
is further configured to maintain the signal allocation of the first data, and
further comprising a clock adjusting circuit (<NUM>, <NUM>) that is configured to increase a transmitting-side clock speed only in a case where the transmitting-side repetition period of the time slots to be time-division multiplexed is longer than the receiving-side repetition period, and
further comprising a transmitter (140a; 140b; 140c) configured to serially transmit the second data and the first data by the time-division multiplex method with the predetermined transmitting-side repetition period to a second device (100a; 100b; 100c) daisy-chained to the serial data transmission device (100a; 100b; 100c).