Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

<CIT> teaches a semiconductor device with source slit having support structures which are dividing blocks.

<CIT> teaches a semiconductor memory device with dummy memory structures, which can be used as support structure.

<CIT> teaches another semiconductor memory device with dummy channel structures, providing mechanical support.

Embodiments of 3D memory devices and methods for forming the 3D memory devices are provided.

Although specific configurations and arrangements are discussed, this should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

As used herein, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A "step" or "staircase" refers to a vertical shift in the height of a set of adjoined surfaces. In the present disclosure, the term "staircase" and the term "step" refer to one level of a staircase structure and are used interchangeably. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with the top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.

NAND flash memory devices, widely used in various electronic produces, are non-volatile, light-weighted, of low power consumption and good performance. Currently, planar NAND flash memory devices have reached its storage limit. To further increase the storage capacity and reduce the storage cost per bit, 3D NAND memory devices have been proposed. The process to form an existing 3D NAND memory device often includes the following operations. First, a stack structure of a plurality of interleaved sacrificial layers and insulating layers are formed over a substrate. A channel hole is formed extending in the stack structure. The bottom of the channel hole is etched to form a recess in the substrate. An epitaxial portion is formed at the bottom of the channel hole by selective epitaxial growth. A semiconductor channel, conductively connected to the epitaxial portion, is formed in the channel hole. The sacrificial layers can be removed and replaced with conductor layers. The conductor layers function as word lines in the 3D NAND memory device.

An existing 3D NAND memory device often includes a plurality of memory blocks. Adjacent memory blocks are often separated by a gate line slit (GLS), in which an array common source (ACS) is formed. In the fabrication method to form the existing 3D NAND memory device, the feature size of the GLS is susceptible to fluctuation, potentially affecting the performance of the 3D NAND memory device.

The present disclosure provides 3D memory devices (e.g., 3D NAND memory devices) with support structures in a slit structure (e.g., a GLS), and methods for forming the 3D memory devices. A 3D memory device employs one or more support structures being in contact with at least a sidewall of a slit structure. For example, a width of the support structure is equal to or greater than a width of a slit structure. Thus, the support structures provide support to the entire structure of the 3D memory device during the formation of conductor layers/portions and source contacts. The 3D memory device is then less susceptible to deformation or damages during the fabrication process. In some embodiments, the support structures are filled with insulating materials include a different material than the sacrificial layers, such as silicon dioxide or polysilicon, so that the support structure has little or no damages during the gate-replacement process in which the sacrificial layers are etched away. By applying the structures and methods of the present disclosure, adjacent memory blocks are in contact with each other through the support structures during the formation of slit structures and source contacts, the 3D memory device is thus less likely to deform during the fabrication process. The feature size of the slit structure is less susceptible to fluctuation.

<FIG> illustrates a plan view of an exemplary 3D memory device <NUM>, according to some embodiments. <FIG> illustrates a cross-sectional view of the 3D memory device <NUM> shown in <FIG> along the C-D direction. <FIG> illustrates a cross-sectional view of the 3D memory device <NUM> shown in <FIG> along the A-B direction. As shown in <FIG>, 3D memory device <NUM> may be divided into a core region and a staircase region (not shown), e.g., along the y-direction. Channel structures and support pillars can be formed in the core region. Staircases and electric connection between conductor layers and outside circuits (e.g., contact plugs) can be formed in the staircase region. The core region may include one or more source regions <NUM> and block region <NUM> extending along the x-direction. A source structure may be formed in each source region <NUM>. A channel structure may be formed in each block region <NUM>.

As shown in <FIG>, 3D memory device <NUM> may include a substrate <NUM>, a buffer oxide layer <NUM>, and a stack structure <NUM> over buffer oxide layer <NUM>. In block region <NUM>, stack structure <NUM> may include a plurality of conductor layers and a plurality of insulating layers <NUM> interleaved over buffer oxide layer <NUM>. In some embodiments, the plurality of conductor layers may include a top conductor layer <NUM> having a plurality of top select conductor layers, a bottom conductor layer <NUM> having a plurality of bottom select conductor layers, and control conductor layers <NUM> between top conductor layer <NUM> and bottom conductor layer <NUM>. Stack structure <NUM> may also include a dielectric cap layer <NUM> covering the plurality of conductor layers (i.e., <NUM>-<NUM>) and insulating layers <NUM>. In block region <NUM>, 3D memory device <NUM> may also include a plurality of channel structures <NUM> extending from a top surface of dielectric cap layer <NUM> into substrate <NUM> along a vertical direction (e.g., the z-direction) and support pillars <NUM> extending from a top surface of dielectric cap layer <NUM> to substrate <NUM> along a vertical direction (e.g., the z-direction). Each channel structure <NUM> may include an epitaxial portion <NUM> at a bottom portion, a drain structure <NUM> at a top portion, and a semiconductor channel <NUM> between epitaxial portion <NUM> and drain structure <NUM>. Semiconductor channel <NUM> may include a memory film <NUM>, a semiconductor layer <NUM>, and a dielectric core <NUM>. Epitaxial portion <NUM> may contact and be conductively connected to substrate <NUM>, and semiconductor channel <NUM> may contact and be conductively connected to drain structure <NUM> and epitaxial portion <NUM>. A plurality of memory cells may be formed by semiconductor channels <NUM> and control conductor layers <NUM>.

A source structure may be formed in source region <NUM> to extend along the x-direction in the core region and the staircase region (not shown). The source structure may include a source contact <NUM> in an insulating structure <NUM>. The source structures may extend vertically through stack structure <NUM> and contact substrate <NUM>, applying a source voltage on the memory cells through substrate <NUM>. According to the invention, 3D memory device <NUM> includes multiple support structures <NUM> aligned along the x-direction and being in contact with at least a sidewall of the respective source structure. In some embodiments, support structure <NUM> is in contact with at least one adjacent block region <NUM> through its contact/connection with the sidewall of the source structure. For example, each one of support structure <NUM> is in contact with both sidewalls of the respective source region <NUM>. In some embodiments, each support structure <NUM> is in contact with adjacent block regions <NUM> through its contact/connection with the source structure. Support structure <NUM> may provide support to 3D memory device <NUM> during the formation of the source structures and conductor layers (e.g., <NUM>-<NUM>). The 3D memory device is thus less likely to deform during the fabrication process. The feature size of the slit structure is less susceptible to fluctuation.

Substrate <NUM> can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some embodiments, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, substrate <NUM> includes silicon.

Channel structures <NUM> may form an array and may each extend vertically above substrate <NUM>. Channel structure <NUM> may extend through a plurality of pairs each including a conductor layer (e.g., <NUM>, <NUM>, or <NUM>) and an insulating layer <NUM> (referred to herein as "conductor/insulating layer pairs"). In some embodiments, buffer oxide layer <NUM> is formed between substrate <NUM> and stack structure <NUM>. At least on one side along a horizontal direction (e.g., x-direction and/or y-direction), stack structure <NUM> can include a staircase structure, e.g., in a staircase region (not shown). The number of the conductor/insulating layer pairs in stack structure <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) determines the number of memory cells in 3D memory device <NUM>. In some embodiments, conductor layers (e.g., <NUM>-<NUM>) and insulating layers <NUM> in stack structure <NUM> are alternatingly arranged along the vertical direction in block region <NUM>. Conductor layers (e.g., <NUM>-<NUM>) can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Insulating layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, buffer oxide layer <NUM> and dielectric cap layer <NUM> each includes a dielectric material such as silicon oxide. In some embodiments, top conductor layer <NUM> includes a plurality of top select conductor layers, which function as the top select gate electrodes. Control conductor layers <NUM> may function as select gate electrodes and form memory cells with intersecting channel structures <NUM>. In some embodiments, bottom conductor layer <NUM> includes a plurality of bottom select conductor layers, which function as the bottom select gate electrodes. Top select gate electrodes and bottom select gate electrodes can respectively be applied with desired voltages to select a desired memory block/finger/page.

As shown in <FIG>, channel structure <NUM> can include a semiconductor channel <NUM> extending vertically through stack structure <NUM>. Semiconductor channel <NUM> can include a channel hole filled with a channel-forming structure, e.g., semiconductor materials (e.g., as a semiconductor layer <NUM>) and dielectric materials (e.g., as a memory film <NUM>). In some embodiments, semiconductor layer <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a memory layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole of semiconductor channel <NUM> can be partially or fully filled with a dielectric core <NUM> including dielectric materials, such as silicon oxide. Semiconductor channel <NUM> can have a cylinder shape (e.g., a pillar shape). Dielectric core <NUM>, semiconductor layer <NUM>, the tunneling layer, the memory layer, and the blocking layer are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the memory layer can include a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

In some embodiments, channel structure <NUM> further includes an epitaxial portion <NUM> (e.g., a semiconductor plug) in the lower portion (e.g., at the lower end of bottom) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the vertical direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the vertical direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Epitaxial portion <NUM> can include a semiconductor material, such as silicon, which is epitaxially grown from substrate <NUM> in any suitable directions. It is understood that in some embodiments, epitaxial portion <NUM> includes single crystalline silicon, the same material as substrate <NUM>. In other words, epitaxial portion <NUM> can include an epitaxially-grown semiconductor layer grown from substrate <NUM>. Epitaxial portion <NUM> can also include a different material than substrate <NUM>. In some embodiments, epitaxial portion <NUM> includes at least one of silicon, germanium, and silicon germanium. In some embodiments, part of epitaxial portion <NUM> is above the top surface of substrate <NUM> and in contact with semiconductor channel <NUM>. Epitaxial portion <NUM> may be conductively connected to semiconductor channel <NUM>. In some embodiments, a top surface of epitaxial portion <NUM> is located between a top surface and a bottom surface of a bottom insulating layer <NUM> (e.g., the insulating layer at the bottom of stack structure <NUM>).

In some embodiments, channel structure <NUM> further includes drain structure <NUM> (e.g., channel plug) in the upper portion (e.g., at the upper end) of channel structure <NUM>. Drain structure <NUM> can be in contact with the upper end of semiconductor channel <NUM> and may be conductively connected to semiconductor channel <NUM>. Drain structure <NUM> can include semiconductor materials (e.g., polysilicon) or conductive materials (e.g., metals). In some embodiments, drain structure includes an opening filled with Ti/TiN or Ta/TaN as an adhesion layer and tungsten as a conductor material. By covering the upper end of semiconductor channel <NUM> during the fabrication of 3D memory device <NUM>, drain structure <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in semiconductor channel <NUM>, such as silicon oxide and silicon nitride.

As shown in <FIG>, source region <NUM> separates different block regions <NUM>. A plurality of channel structures <NUM> (e.g., memory cells) can be formed in each block region <NUM>. In some embodiments, source region <NUM> may extend along the x-direction. The number of source region <NUM> and a block region <NUM> (i.e., memory block) may range from <NUM> to n, n being a positive integer. The number of n should be determined based on the design and/or fabrication of 3D memory device <NUM> and should not be limited by the embodiments of the present disclosure. For illustrative purposes, n is equal to <NUM> in the present disclosure.

According to the invention, a source structure includes a source contact <NUM> in an insulating structure <NUM>, extending along the x-direction in a respective source region <NUM>. Source contact <NUM> may be in contact with and form a conductive connection with substrate <NUM> for applying a source voltage on memory cells. In some embodiments, source contact <NUM> includes one or more of polysilicon, silicide, germanium, silicon germanium, copper, aluminum, cobalt, and tungsten. In some embodiments, insulating structure <NUM> includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

At least one support structure <NUM> may be formed in contact with one or both sidewalls of the source structure along the y-direction. As shown in <FIG>, support structure <NUM> may be in contact with one or both block regions <NUM> through its contact/connection with the source structure. In some embodiments, support structure <NUM> may be in contact with both sidewalls of the respective source structure and thus in contact with both adjacent block regions <NUM>. As shown in <FIG>, support structure <NUM> may extend along the z-direction to substrate <NUM>. Support structure <NUM> may include a single-layer structure or a multi-layer structure. For example, support structure <NUM> may include a single material or more than one material. In some embodiments, when support structure <NUM> includes more than one material, the different material may be deposited as a stack in support hole <NUM>, forming a stack structure. The specific number of materials and number of layers of support structure <NUM> should be determined based on the design and/or fabrication of 3D memory device <NUM> and should not be limited by the embodiments of the present disclosure.

As shown in <FIG>, the plurality of support structures <NUM> divides the source structure into a plurality of source contacts <NUM> and insulating structures <NUM> along the x-direction. Source contact <NUM> (e.g., and respective insulating structure <NUM>) and adjacent source contact <NUM> (e.g., and respective adjacent insulating structure <NUM>) are disconnected from one another because the support structure <NUM> in between is in contact with both block regions adjacent to the source structure. In some embodiments, sidewalls of support structure <NUM> are each in contact with the respective source structure, e.g., along the x-direction.

In some embodiments, support structure <NUM> includes a suitable support material that has sufficient stiffness and strength and may sustain the gate replacement process for the formation of conductor layers (e.g., <NUM>-<NUM>) and conductor portions (e.g., <NUM> and <NUM>). The support material includes polysilicon or silicides, i.e. a different material than the sacrificial material (e.g., so that support structures <NUM> and support pillars <NUM> have little or no damages during the gate-replacement process in which the sacrificial layers are etched away. In some embodiments, support structure <NUM> and support pillar <NUM> may include the same material. In some embodiments, a depth of support structure <NUM> and support pillar <NUM> may be the same along the z-axis, e.g., from the top surface of substrate <NUM> to the top surface of dielectric cap layer <NUM>.

A width of support structure <NUM> along the y-direction may be less than, equal to, or greater than the width of the source structure along the y-direction. In some embodiments, the width of support structure <NUM> is equal to or greater than the width of the source structure along the y-direction. <FIG> illustrates an enlarged plan view <NUM> of support structure <NUM>, adjacent source contacts <NUM>, and adjacent insulating structures <NUM>. As shown in <FIG>, a width d2 of support structure <NUM> along the y-direction is less than, equal to, or greater than a width d1 of the respective source structure along the y-direction. Support structure <NUM> can be in contact with at least one adjacent block region <NUM> during the fabrication process of the slit structure and the source structure, supporting entire 3D memory device <NUM> and preventing stack structure <NUM> from collapsing. In some embodiments, d2 is greater than or equal to d1 and support structure <NUM> is in contact with both adjacent block regions <NUM>. A cross-sectional shape of support pillar along the x-y plane may include any suitable shape that can be formed in a fabrication process. For example, the cross-sectional shape may include a circular shape, a triangular shape, a rectangular, a pentagonal shape, a hexagonal shape, an arbitrary shape, or a combination thereof. For ease of illustration, support structure <NUM> has a circular cross-section along the x-y plane. The dimensions (e.g., diameter) of support structure <NUM> may or may not vary along the z-direction, depending on the structure and fabrication process of 3D memory device <NUM>.

3D memory device <NUM> can be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., NAND channel structures) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, 3D memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate <NUM>) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It is understood that in some embodiments, the memory array device substrate (e.g., substrate <NUM>) is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate (e.g., substrate <NUM>) can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the backside of the thinned memory array device substrate.

<FIG> illustrate a fabrication process to form 3D memory device <NUM> shown in <FIG>. <FIG> is a flowchart of a method <NUM> illustrated in <FIG>. For ease of illustration, same or similar parts are labeled with the same numerals in <FIG> of the present disclosure.

At the beginning of the process, a stack structure of interleaved a plurality of initial insulating layers and a plurality of initial sacrificial layers are formed (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>.

As shown in <FIG>, a stack structure <NUM> having a dielectric stack of interleaved initial insulating layers 104i and initial sacrificial layers 103i is formed over substrate <NUM>. Initial sacrificial layers 103i may be used for subsequent formation of control conductor layers <NUM>. Stack structure <NUM> may also include a top initial sacrificial layer 106i and a bottom initial sacrificial layer 145i respectively for subsequent formation of top conductor layer <NUM> and bottom conductor layer <NUM>. In some embodiments, stack structure <NUM> includes a dielectric cap layer <NUM> over initial sacrificial layers (e.g., 103i, 145i, and 106i) and initial insulating layers 104i. 3D memory device <NUM> may include a core region for forming channel structures <NUM> and support pillars <NUM>, and a staircase region (not shown) for forming staircases and contact plugs on the staircases. The core region may include a block region <NUM> for forming channel structures <NUM>. In some embodiments, block region <NUM> may be between a pair of source regions <NUM>.

Stack structure <NUM> may have a staircase structure. The staircase structure can be formed by repetitively etching a material stack that includes a plurality of interleaved sacrificial material layers and insulating material layers using an etch mask, e.g., a patterned PR layer over the material stack. The interleaved sacrificial material layers and the insulating material layers can be formed by alternatingly depositing layers of sacrificial material and layers of insulating material over buffer oxide layer <NUM> until a desired number of layers is reached. In some embodiments, a sacrificial material layer is deposited over buffer oxide layer <NUM>, and an insulating material layer is deposited over the sacrificial material layer, so on and so forth. The sacrificial material layers and insulating material layers can have the same or different thicknesses. In some embodiments, a sacrificial material layer and the underlying insulating material layer are referred to as a dielectric pair. In some embodiments, one or more dielectric pairs can form one level/staircase. During the formation of the staircase structure, the PR layer is trimmed (e.g., etched incrementally and inwardly from the boundary of the material stack, often from all directions) and used as the etch mask for etching the exposed portion of the material stack. The amount of trimmed PR can be directly related (e.g., determinant) to the dimensions of the staircases. The trimming of the PR layer can be obtained using a suitable etch, e.g., an isotropic dry etch such as a wet etch. One or more PR layers can be formed and trimmed consecutively for the formation of the staircase structure. Each dielectric pair can be etched, after the trimming of the PR layer, using suitable etchants to remove a portion of both the sacrificial material layer and the underlying insulating material layer. The etched sacrificial material layers and insulating material layers may form initial sacrificial layers (e.g., 103i, 106i, and 145i) and initial insulating layers 104i. The PR layer can then be removed.

The insulating material layers and sacrificial material layers may have different etching selectivities during the subsequent gate-replacement process. In some embodiments, the insulating material layers and the sacrificial material layers include different materials. In some embodiments, the insulating material layers include silicon oxide, and the deposition of insulating material layers include one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering. In some embodiments, the sacrificial material layers include silicon nitride, and the deposition of insulating material layers include one or more of CVD, PVD, ALD, and sputtering. In some embodiments, the etching of the sacrificial material layers and the insulating material layers include one or more suitable anisotropic etching process, e.g., dry etch.

Referring back to <FIG>, at least one support hole, at least one channel hole, and at least one pillar hole are formed. In some embodiments, the at least one channel hole and the at least one pillar hole are formed by the same operation that forms the at least one support hole (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>. As shown in <FIG>, at least one of support hole <NUM> is formed in source region <NUM>. In some embodiments, at least one of support hole <NUM> is formed in each source region <NUM> along the x-direction, separated from one another. Along the x-direction, a length of support hole <NUM> may be less than a length L (in <FIG>) of the source structure to be formed (or the length of source region <NUM>, or the slit structure in which the source structure is formed). The at least one of support hole <NUM> may have the same or different dimensions. In some embodiments, the at least one of support hole <NUM> may have the same shapes (e.g., cylinder shapes, such as a pillar shape or cuboid shape) and dimensions along the x-y plane, and same depth along the z-direction. Along the y-direction, a width of support hole <NUM> may be less than, greater than, or equal to a width of the source structure to be formed. In some embodiments, along the y-direction, the width of support hole <NUM> is equal to or greater than a width of source region <NUM>. In some embodiments, support hole <NUM> exposes substrate <NUM>.

In some embodiments, at least one channel hole <NUM> is formed in the plurality of block regions <NUM> and at least one pillar hole <NUM> is formed in the staircase region and/or the plurality of block regions <NUM>. In some embodiments, at least one channel hole <NUM> and at least one pillar hole <NUM> are formed in each block region <NUM> along the x-direction, separated from one another. In some embodiments, a bottom surface of channel hole <NUM> and a bottom surface of pillar hole <NUM> each exposes substrate <NUM>. The layout shown in the figures of the present disclosure is for illustrative purposes only and not to scale.

The at least one of support hole <NUM>, the at least one channel hole <NUM>, and the at least one pillar hole <NUM> may be formed by a suitable patterning process. For example, an etch mask may be used, e.g., a patterned PR layer, over stack structure <NUM> to expose the areas corresponding to support holes <NUM>, channel holes <NUM>, and pillar hole <NUM>, and an etching process, such as a dry etch and/or wet etch, may be performed to remove portions of stack structure <NUM> and form the at least one of support hole <NUM>, the at least one channel hole <NUM> and the at least one pillar hole <NUM>. The PR layer can then be removed.

Referring back to <FIG>, A sacrificial structure <NUM> can be formed to fill in the at least one channel hole <NUM> (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>. As shown in <FIG>, channel holes <NUM> may be filled with sacrificial structure <NUM> to, e.g., prevent contamination caused by the deposition of a support material when filling support hole <NUM> and pillar hole <NUM> with the support material. Sacrificial structure <NUM> includes a sacrificial material that has one or more of silicon oxide, silicon nitride, and polysilicon, and the deposition process includes one or more of CVD, PVD, sputtering, and ALD. Optionally, a planarization process (e.g., CMP and/or recess etch) is performed to remove any excess material (e.g., sacrificial material) on stack structure <NUM>.

Referring back to <FIG>, a support structure and a support pillar are formed in the support hole and the pillar hole respectively (Operation <NUM>). The support structure and the support pillar can be formed by deposing a support material to the support hole and pillar hole respectively. <FIG> illustrate the corresponding structure <NUM>. As shown in <FIG>, support hole <NUM> and pillar hole <NUM> are each filled with the support material to form support structures <NUM> and support pillars <NUM>. The support material may include a different material than materials of initial sacrificial layers (e.g., 103i, 106i, and 145i) and sacrificial structures <NUM> so that support structures <NUM> and support pillars <NUM> have little or no damages during the gate-replacement process in which the sacrificial layers are etched away and during the process that sacrificial structure <NUM> is etched away. In some embodiments, support hole <NUM> and pillar hole <NUM> may be filled with a single layer of support material. For example, the support material may be formed by deposing the support material into support hole <NUM> and pillar hole <NUM>. Optionally, a planarization process, e.g., dry/wet etch and/or CMP, is performed to remove any excess material on the top surface of stack structure <NUM>. In some other embodiments, multiple layers of support material may be formed in support hole <NUM> and pillar hole <NUM>. For example, layers of different materials may be deposited sequentially to fill up support hole <NUM> and pillar hole <NUM>.

Referring back to <FIG>, sacrificial material in the channel hole is removed and channel structures are formed in at least one channel hole (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>. As shown in <FIG>, a plurality of channel structures <NUM> can be formed in each of channel hole <NUM>. In some embodiments, sacrificial structure <NUM> in channel hole <NUM> are removed and a plurality of channel holes <NUM> are reformed. After removing sacrificial structure <NUM>, substrate <NUM> is exposed in channel hole <NUM>. A recess region may be formed at the bottom of each channel hole <NUM> to expose a top portion of substrate <NUM> by the same etching process that initially forms the channel hole <NUM> above substrate <NUM> and/or by a separate recess etching process. In some embodiments, a semiconductor plug is formed at the bottom of each channel hole, e.g., over the recess region. The semiconductor plug may be formed by an epitaxial growth process and/or a deposition process. In some embodiments, the semiconductor plug is formed by epitaxial growth and is referred to as epitaxial portion <NUM>. Optionally, a recess etch (e.g., dry etch and/or wet etch) may be performed to remove excess semiconductor material on the sidewall of channel hole <NUM> and/or control the top surface of epitaxial portion <NUM> at a desired position. In some embodiments, the top surface of epitaxial portion <NUM> is located between the top and bottom surfaces of the bottom initial insulating layer 104i.

In some embodiments, epitaxial portion <NUM> includes single crystalline silicon is formed by epitaxially grown from substrate <NUM>. In some embodiments, epitaxial portion <NUM> includes polysilicon formed by a deposition process. The formation of epitaxially-grown epitaxial portion <NUM> can include, but not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof. The formation of deposited epitaxial portion <NUM> may include, but not limited by, CVD, PVD, and/or ALD.

In some embodiments, a semiconductor channel <NUM> is formed over and contacting epitaxial portion <NUM> in channel hole <NUM>. Semiconductor channel can include a channel-forming structure that has a memory film <NUM> (e.g., including a blocking layer, a memory layer, and a tunneling layer), a semiconductor layer <NUM> formed above and connecting epitaxial portion <NUM>, and a dielectric core <NUM> filling up the rest of the channel hole. In some embodiments, memory film <NUM> is first deposited to cover the sidewall of the channel hole and the top surface of epitaxial portion <NUM>, and semiconductor layer <NUM> is then deposited over memory film <NUM> and above epitaxial portion <NUM>. The blocking layer, memory layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor layer <NUM> can then be deposited on the tunneling layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, dielectric core <NUM> is filled in the remaining space of the channel hole by depositing dielectric materials after the deposition of semiconductor layer <NUM>, such as silicon oxide.

In some embodiments, drain structure <NUM> is formed in the upper portion of each channel hole. In some embodiments, parts of memory film <NUM>, semiconductor layer <NUM>, and dielectric core <NUM> on the top surface of stack structure <NUM> and in the upper portion of each channel hole can be removed by CMP, grinding, wet etching, and/or dry etching to form a recess in the upper portion of the channel hole so that a top surface of semiconductor channel may be between the top surface and the bottom surface of dielectric cap layer <NUM>. Drain structure <NUM> then can be formed by depositing conductive materials, such as metals, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. A channel structure <NUM> is thereby formed. A plurality of memory cells may subsequently be formed by the intersection of semiconductor channels <NUM> and control conductor layers <NUM>. Optionally, a planarization process, e.g., dry/wet etch and/or CMP, is performed to remove any excess material on the top surface of stack structure <NUM>.

In some embodiments, Operation <NUM> and Operation <NUM> may be performed in a different order. For example, operation <NUM> may be performed before Operation <NUM>. For example, a channel structure in each of the at least one channel hole may be formed before forming the support structure and the support pillar. For example, at <NUM>, a sacrificial structure may be formed in each of the at least one support hole <NUM> and at least one pillar hole <NUM>. After forming the channel structure <NUM> in each of the at least one channel hole <NUM>, support structures <NUM> and support pillars <NUM> may be formed respectively in each of the at least one support hole <NUM> and the at least one pillar hole <NUM> by removing the sacrificial structure in each of the at least one support hole <NUM> and the at least one pillar hole <NUM>.

Referring back to <FIG>, portions of the stack structure in source regions may be removed to form at least one slit structure extending laterally and vertically (Operation <NUM>). <FIG> illustrates a corresponding structure <NUM>. As shown in <FIG>, a slit structure <NUM> may be formed in source region <NUM> extending laterally along the x-direction. A plurality of interleaved sacrificial layers and insulating layers <NUM> may be formed in each block region <NUM>. Slit structure <NUM> may extend vertically along the z-direction, exposing substrate <NUM>. One or more support structures <NUM> may be distributed along the x-direction in source region <NUM>, dividing the respective slit structure <NUM> into a plurality of slit openings. Sidewalls of support structure <NUM> may be in contact with slit structure <NUM>, e.g., along the x-direction. Support structure <NUM> may be in contact with at least one sidewall of slit structure <NUM> (i.e., at least one adjacent block region <NUM> of stack structure <NUM>). In some embodiments, support structure <NUM> is in contact with both sidewalls of slit structure <NUM>. That is, support structure <NUM> may be in contact with both adjacent block regions <NUM> along the y-direction. A width of support structure <NUM> along the y-direction may be less than, equal to, or greater than the width of the respective slit structure <NUM> along the y-direction. <FIG> illustrates an enlarged plan view <NUM> of support structure <NUM> and slit structure <NUM>. As shown in <FIG>, a width d2 of support structure <NUM> along the y-direction is equal to or greater than a width d1 of slit structure <NUM> along the y-direction. In some embodiments, d2 is greater than d1. In some embodiments, support structure <NUM> is in contact with at least one adjacent block region <NUM> during the formation of slit structure <NUM>. That is, support structures <NUM> may provide support to the adjacent block region <NUM> during the formation of slit structures <NUM> and subsequent formation of source structures to prevent slit structure <NUM> (e.g., block regions <NUM>) from deformation. In some embodiments, d2 is equal to or greater than d1 and support structure <NUM> is in contact with both adjacent block regions <NUM> during the formation of slit structure <NUM> and the source structure, providing support to stack structure <NUM>. In some embodiments, support structures <NUM> is used as an etch mask and an anisotropic etching process, e.g., dry etch, is performed to remove portions of stack structure <NUM> in source region <NUM> to form slit structure <NUM>. Portions of stack structure <NUM> around (e.g., adjacent to) each support structure <NUM> may be removed to expose substrate <NUM>, forming slit structure <NUM>. An anisotropic etching process, e.g., dry etch, may be performed to form slit structures <NUM>.

Referring back to <FIG>, a source structure is formed in each slit structure, and a plurality of conductor layers and a plurality of memory blocks are formed (Operation <NUM>). <FIG> illustrate a corresponding structure <NUM>. As shown in <FIG>, sacrificial layers retained in block region <NUM> from the formation of slit structures <NUM> may be removed to form a plurality of lateral recesses. As shown in <FIG>, a suitable conductor material may be deposited to fill up the lateral recesses, in block region <NUM>, to form a plurality of conductor layers (e.g., <NUM>-<NUM>) and another suitable conductor material may be deposited to fill up the lateral recesses, in source region <NUM> to form a plurality of source structure.

In some embodiments, initial sacrificial layers (e.g., 103i, 106i, and 145i) in block regions <NUM> are removed to form a plurality of lateral recesses, and a suitable conductor material is deposited to fill up the lateral recesses, forming a plurality of conductor layers (e.g., <NUM>-<NUM>) in block regions <NUM>. Control conductor layers <NUM> may intersect with semiconductor channels <NUM> and form a plurality of memory cells in block region <NUM>, which forms a memory block. In some embodiments, the top sacrificial layer in the block regions may form a top conductor layer <NUM>, and the bottom sacrificial layer in the block regions may form a bottom conductor layer <NUM>.

The conductor material may include one or more of tungsten, aluminum, copper, cobalt, silicides, and polysilicon. A suitable isotropic etching process, e.g., wet etch, can be performed to remove sacrificial layers and sacrificial portions, and form the plurality of lateral recesses. A suitable deposition process, such as CVD, PVD, ALD, and/or sputtering can be performed to deposit the conductor material into the lateral recesses to form conductor layers (e.g., <NUM>-<NUM>).

As shown in <FIG>, an insulating structure <NUM> may be formed in each slit structure <NUM>, and a source contact <NUM> may be formed in the respective insulating structure. The insulating structures <NUM> and source contacts <NUM> in each source region <NUM> may form a source structure. Insulating structure <NUM> and source contacts <NUM> may be formed on each side of support structure <NUM> along the x-direction. Support structure <NUM> may separate adjacent source contacts <NUM> and insulating structures <NUM> along the x-direction and may be in contact with at least one adjacent memory block along the y-direction. In some embodiments, insulating structures <NUM> includes silicon oxide, and is deposited by one or more of CVD, PVD, ALD, and sputtering. A recess etch may be performed to remove portions of insulating structures <NUM> at the bottom of the respective slit structure <NUM> to expose substrate <NUM>. In some embodiments, source contacts <NUM> include one or more of tungsten, aluminum, copper, cobalt, silicides, and polysilicon, and a suitable deposition process, e.g., one or more of CVD, PVD, ALD, and sputtering, is performed to deposit source contacts <NUM> into respective slit structures <NUM>.

<FIG> illustrate another fabrication process to form 3D memory device <NUM>, and <FIG> illustrates a flowchart <NUM> of the fabrication process, according to some embodiments. Different from the fabrication process illustrated in <FIG>, two stack structures of interleaved a plurality of initial insulating layers and a plurality of initial sacrificial layers are formed. For ease of illustration, same or similar operations illustrated in <FIG> are not repeated in the description.

At the beginning of the process, a first stack structure <NUM> of interleaved a plurality of initial insulating layers and a plurality of initial sacrificial layers are formed (Operation <NUM>). This operation may be similar to Operation <NUM> in method <NUM>.

At Operation <NUM>, at least one first support hole <NUM> extending vertically in the first stack structure <NUM> and into substrate <NUM> are formed and at least one first channel hole <NUM> and at least one first pillar hole <NUM> are formed in the plurality of block regions by the same operation that forms the at least one first support hole <NUM> on the first dielectric stack. This operation may be similar to Operation <NUM> in method <NUM>.

At Operation <NUM>, a sacrificial structure <NUM> is formed in each of the at least one least one first support hole <NUM>, the at least one first channel hole <NUM> and the at least one first pillar hole <NUM> respectively. Sacrificial structure <NUM> may be formed by filling each of the at least one first support hole <NUM>, the at least one first channel hole <NUM> and the at least one first pillar hole <NUM> with sacrificial materials. The formation of sacrificial structures <NUM> may be referred to Operation <NUM> in method <NUM>. Optionally, a planarization process (e.g., CMP and/or recess etching) is performed to remove any excess dielectric material from the deposition process for a second stack structure <NUM> to be formed on the first stack structure <NUM>.

At Operation <NUM>, a second stack structure <NUM> of interleaved a plurality of initial insulating layers and a plurality of initial sacrificial layers are formed on first stack structure <NUM>. This operation may be similar to Operation <NUM> in method <NUM>.

At Operation <NUM>, at least one second support hole <NUM> extending vertically in stack structure <NUM> is formed. At least one second channel hole <NUM> and at least one second pillar hole <NUM> may be formed in second stack structure <NUM> by the same operation that forms at least one second support hole <NUM>. In some embodiments, each second support hole <NUM> is vertically aligned with a corresponding first support hole <NUM> in first stack structure <NUM> along the z-direction. A bottom of second support hole <NUM> may expose sacrificial structure <NUM> formed in the corresponding first support hole <NUM>. Also, each second channel hole <NUM> is vertically aligned with a corresponding first channel hole <NUM> and exposes the corresponding sacrificial structure <NUM> formed in the corresponding first channel hole. Each second pillar hole <NUM> is vertically aligned with a corresponding first pillar hole <NUM> and exposes the corresponding sacrificial structure formed in the corresponding first pillar hole <NUM>.

At Operation <NUM>, a sacrificial structure <NUM> is formed in each of at least one second channel hole <NUM>. The Operation may be similar to Operation <NUM>. Thus, the same sacrificial structure is formed in second channel hole <NUM> and first channel hole <NUM>. The second channel hole <NUM> and first channel hole <NUM> may form a channel hole <NUM>-<NUM>.

Sacrificial material in at least one first support hole <NUM> and at least one first pillar hole <NUM> are removed. Thus, second support hole <NUM> is connected with first support hole <NUM> and the connected second support hole <NUM> and first support hole <NUM> may form a support hole <NUM>-<NUM>. Second pillar hole <NUM> is connected with first pillar hole <NUM> and the connected second pillar hole <NUM> and first pillar hole <NUM> may form a pillar hole <NUM>-<NUM> similar to pillar hole <NUM> in method <NUM>.

At Operation <NUM>, channel structures <NUM>, at least one support structure <NUM> and at least one support pillars <NUM> may be formed in channel hole <NUM>-<NUM>, support hole <NUM>-<NUM> and pillar hole <NUM>-<NUM> respectively, in Operations similar to Operation <NUM> and Operation <NUM>.

At Operation <NUM>, at least one slit structure, a source structure in each of the at least one slit structure, a plurality of conductor layers and a plurality of memory blocks are formed in Operations similar to Operation <NUM> and Operation <NUM>.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional (3D) memory device, comprising:
a stack structure (<NUM>) comprising a plurality of conductor layers (<NUM>-<NUM>) and a plurality of insulating layers (<NUM>) interleaved over a substrate (<NUM>); and
at least one source structure extending vertically and laterally and dividing the stack structure (<NUM>) into a plurality of block regions (<NUM>),
wherein the at least one source structure comprises a plurality of support structures (<NUM>) extending along the vertical direction to the substrate (<NUM>), the plurality of support structures (<NUM>) being in contact with both adjacent block regions (<NUM>), characterized in that
the plurality of support structures (<NUM>) divide the source structure into a plurality of insulating structures (<NUM>) with a respective source contact (<NUM>) formed therein, characterised in that each of the support structures includes a support material, wherein the support material includes polysilicon or silicides.