Patent Description:
The disclosure relates to a technical field of semiconductors, particularly to a package structure, a packaging method and a semiconductor device.

With the rapid increase in the popularity rate of electronic equipment and the vigorous development of the electronic equipment market, electronic products are increasingly required to evolve towards miniaturization and thinness while having a high performance, multifunctionality, high reliability and convenience. Such requirements put forward better, lighter, thinner, higher package density, better electrical and thermal properties, higher reliability and higher cost performance requirements for packaging of semiconductor devices.

In order to ensure the performance of a semiconductor device to meet corresponding requirements, it is necessary to prepare ports for testing and executing functional interactions on a package structure.

<CIT> discloses a semiconductor device and method of making wafer level chip scale package, a method of making a semiconductor device comprising: providing a semiconductor wafer; forming a redistribution layer including an interconnect site over the semiconductor wafer; forming a first insulating layer over the redistribution layer with an opening in the first insulating layer over the interconnect site; and forming an interconnect structure within the opening to cover a top surface of the redistribution layer and a side surface of the redistribution layer. <CIT> is silent on after completing a first type test, removing part of the first pad to form a fourth pad, wherein an area of the fourth pad is smaller than an area of the first pad, i.e. silent on a pad with an area less than a cross-sectional area of the via hole.

<CIT> discloses a semiconductor chip, semiconductor package including the same, and method of fabricating the same, A semiconductor chip comprising: an integrated circuit on a substrate; a center pad on the substrate and electrically connected to the integrated circuit; a lower insulating structure on the center pad, the lower insulating structure having a contact hole exposing the center pad therethrough, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate; a conductive pattern including a contact portion, a pad portion, and a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, the conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion; and an upper insulating structure on the conductive pattern, the upper insulating structure having a first opening exposing the pad portion, the upper insulating structure including an upper insulating layer and a polymer layer, the upper including layer covering the lower insulating structure and the conductive pattern, the polymer layer on the upper insulating layer.

<CIT> discloses a semiconductor package with improved redistribution layer design and fabricating method thereof, A semiconductor package comprising: a semiconductor die comprising a plurality of bond pads; a first redistribution layer (RDL) formed on the semiconductor die, the first RDL having a first end coupled to a bond pad and a second end coupled to a solder bump via one or more under bump metal layers; and a second RDL formed in a same plane of the semiconductor die as at least a portion of the first RDL, the second RDL being electrically isolated from the first RDL, wherein a first end of the second RDL is coupled to at least one of said plurality of bond pads, and the second RDL passes underneath, but is electrically isolated from, the solder bump coupled to the second end of the first RDL.

<CIT> discloses a Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance, an electronic component array, comprising: a backplane substrate; a plurality of integrated circuit elements disposed on the backplane substrate, each of the integrated circuit elements comprising a chiplet substrate, a connection pad, and a conductor element disposed on a surface of the chiplet substrate, wherein the connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad, and wherein at least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and a plurality of conductive wires on the backplane substrate, wherein the connection pad of each of the plurality of integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding that the at least one of the integrated circuit elements is misaligned on the backplane substrate.

<CIT> discloses a Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads, <NUM>. an integrated circuit topography, comprising a first row and a second row of bonding pads spaced from each other across the topography, wherein every other bonding pad within the first row is connected to every other probe pad within a third row, and wherein every other bonding pad within the second row is connected to every probe pad within a fourth row.

The invention is set out in the appended claims <NUM>-<NUM>.

<NUM>, semiconductor functional structure; <NUM>, semiconductor functional layer; <NUM>, interconnecting layer; <NUM>, isolation layer; <NUM>, via hole; <NUM>, first pad; <NUM>, fourth pad; <NUM>, redistribution layer; <NUM>, first insulating layer; <NUM>, second pad; <NUM>, third pad; <NUM>, groove; <NUM>, second insulating layer; <NUM>, conductive pillar; <NUM>, third insulating layer; <NUM>, semiconductor functional structure layout layer; <NUM>, package structure layout layer; <NUM>, first type pad region; 5021a, partial interconnecting layer region; 5021b, first pad region; <NUM>, conductive pillar region; <NUM>, second type pad region; 5023a, redistribution layer region; 5023b, second pad region; and 5023c, third pad region.

In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may represent similar parts in different examples. The various embodiments discussed herein are generally shown in the accompanying drawings by way of example.

The technical solutions of the disclosure will be further described in detail below with reference to the drawings and embodiments. While exemplary implementing modes of the disclosure are shown in the drawings it should be understood that the disclosure may be implemented in various forms and should not be limited by the embodiments set forth herein, and only be limited by the claims. In contrast, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to a person skilled in the art.

The embodiments of the disclosure are described in more detail by way of example in the following paragraphs with reference to the drawings. The advantages and features of the disclosure will become clearer according to the following descriptions and claims. It should be noted that the accompanying drawings are all in very simplified forms and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the disclosure.

It is understood that the meanings of "on", "above" and "over" of the disclosure should be interpreted in the widest manner so that "on" not only means that it is "on" something without an intervening feature or layer being in between (i.e. directly on something), but also includes that it is "above" something with an intervening feature or layer being in between.

In the embodiments of the disclosure, the term "A is connected to B" includes the situation that A and B are in direct contact, and the situation that A and B are indirectly in contact through an intermediate conductive structure.

In the embodiments of the disclosure, the terms "first "and "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

In the embodiments of the disclosure, the term "layer" refers to part of material that includes a region having a thickness. A layer may extend over a surface of a lower or upper structure, or may have an area smaller than an extent of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, having a thickness less than the thickness of the continuous structure. For example, a layer may be between a top surface and the bottom surface of a continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically and/or along an inclined surface. A layer may include multiple sub-layers. For example, an interconnection layer may include one or more conductors and contact sub-layers (in which interconnecting wires and/or via hole contacts are formed), and one or more dielectric sub-layers.

It should be noted that technical solutions described in the embodiments of the disclosure can be arbitrarily combined as long as there is no conflict.

A semiconductor functional structure described in the embodiments of the disclosure is used for subsequent processes and forms part of a final semiconductor device, and is a core part to realize a main function of the semiconductor device. Here, the final semiconductor device may include, but is not limited to a memory.

In a design of a packaging structure of a semiconductor device, such as a dynamic random access memory (DRAM), a pad (also called bonding pad) can be disposed in two manners: one is top metal layer windowing, and the other is redistribution layer (RDL) windowing.

The top metal layer windowing refers to that a passivation layer or an insulating layer is formed on a top metal layer of the semiconductor functional structure to protect the semiconductor functional structure from being damaged, and then a windowing region is formed in the passivation layer or the insulating layer to expose part of the top metal layer and thus form the pad. A prode card sticking test may be carried out on the pad to realize an electrical property test of the semiconductor functional structure, and a bonding wire may be leaded out from the pad to realize an electrical leading out of the semiconductor functional structure.

The redistribution layer windowing refers to that a redistribution layer is formed on a top metal layer of the semiconductor functional structure, and a passivation layer or an insulating layer is formed on the redistribution layer, and then a windowing region is formed in the passivation layer or the insulating layer to expose part of the redistribution layer and thus form two pads arranged side by side. One of the two pads is used for performing a probe card sticking test, and the other pad is used for leading out a bonding wire therefrom. Here, the redistribution layer can play a role of adjusting a position of a pad in a semiconductor device, and can also play a role of enhancing a power supplying network of a power ground.

Understandably, the top metal layer is relatively thin, and there is a gasket structure below it, which can support the probe card sticking test first, and then the bonding wire packaging in a packaging factory on the same windowing metal region without affecting the yield of packaging and wiring. The material of the redistribution layer is generally a metal, and the redistribution layer is thicker than the top metal layer, and thus there are usually deep and rough sticking traces on the surface after the probe card sticking test. Such sticking traces may affect the yield of packaging and wiring. Therefore, in the redistribution layer, the pad used for testing and the pad used for leading out bonding wires are different. No matter which of the above windowing manners is adopted in a package structure, it has little influence on the function of a semiconductor device. The redistribution layer windowing is beneficial to improving the performance, but it increases the production cycle and production cost.

In the related art, one of the above two windowing manners is generally selected to design a package structure according to an actual requirement of a semiconductor device. However, in practical applications, in a production process of semiconductor devices, the requirement is no single, and there are often multiple requirements. Here are several examples of such multiple requirements.

Exemplarily, before a mass production of a semiconductor device (or referred to as "product"), there is a long term of the functional debugging process. In the debugging process, a test is completed with a low running speed of a semiconductor functional structure. In this situation, only the top metal windowing is needed to be adopted to complete the packaging and the testing of the semiconductor functional structure. However, when the manufacturing process of the product is mature and it is necessary to test the semiconductor functional structure under a state of running at a high speed, the redistribution layer windowing is needed to be adopted for a packaging test.

Exemplarily, when a semiconductor functional structure itself has different functional demands, a test for the same semiconductor functional structure can be classified into a standard grade test and an advanced grade test according to different demands. The requirements for windowing modes of the different test grades of the semiconductor functional structure are also different. When the standard grade test is performed on the semiconductor functional structure, the top metal layer windowing can be adopted for the packaging and testing, and the role of a redistribution layer is not apparent. When the advanced grade test is performed on the semiconductor functional structure, the redistribution layer windowing is needed to be adopted for the packaging and testing, to improve the performance of the product.

To sum up, in the related art, adopts one of the two windowing manners in a package structure of a semiconductor functional structure cannot meet different test demands to the semiconductor functional structure of a semiconductor device during different manufacturing process stages. In view of this, in order to solve at least one of the above problems, the embodiments of disclosure provides a package structure, a packaging method and a semiconductor device, which are compatible with the two types of tests, meet the requirements that a semiconductor functional structure can be subjected to different types of tests in different manufacturing process stages, improve flexibility of testing, shorten the production cycle and reduce manufacturing cost.

<FIG> is a schematic flowchart of a method for manufacturing a package structure provided by an example of the present disclosure, the example is not in accordance with the claimed invention and is present for illustration purpose only. As shown in <FIG>, a method for manufacturing a package structure includes the following operations.

At S101, a semiconductor functional structure is provided, in which an interconnecting layer is disposed on a surface of the semiconductor functional structure.

At S102, an isolation layer exposing part of the interconnecting layer is formed, in which the exposed part of the interconnecting layer acts as a first pad, and the first pad is used for performing a first type test.

At S103, after completing the first type test, a redistribution layer is formed on the first pad and the isolation layer, in which the redistribution layer and the interconnecting layer are electrically connected.

At S104, a first insulating layer exposing parts of the redistribution layer is formed, in which the exposed parts of the redistribution layer act as a second pad and a third pad, respectively, the second pad is used for performing a second type test, and the third pad is used for executing a functional interaction corresponding to contents of the second type test; and a running speed of the semiconductor functional structure when performing the first type test is lower than a running speed when performing the second type test.

It should be understood that the operations shown in <FIG> are not exclusive and that other operations may be performed before, after, or between any of the operations; and the order of the operations shown in <FIG> can be adjusted according to actual requirements. <FIG> are cross-sectional diagrams of structures during a manufacturing process of an package structure provided by an embodiment of the disclosure; <FIG> are cross-sectional diagrams of structures during a manufacturing process of a conductive pillar provided by an example of the present disclosure, the example is not in accordance with the claimed invention and is present for illustration purpose only; and <FIG> are cross-sectional diagrams of structures during a manufacturing process of another package structure provided by an embodiments of the disclosure. The method for manufacturing an package structure provided will be described in detail below with reference to <FIG>, <FIG>, <FIG> and <FIG>.

At S101, a semiconductor functional structure <NUM> is provided.

Referring to <FIG>, providing the semiconductor functional structure <NUM> includes providing a substrate (not shown in <FIG>), in which a semiconductor functional layer <NUM> is provided on the substrate, and an interconnecting layer <NUM> is provided on the semiconductor functional layer <NUM>.

Here, the material constituting the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe) or the like. In other embodiments, the material of the substrate may also include a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI).

The semiconductor functional layer <NUM> includes a monolayer thin film or multilayer thin films. The semiconductor functional layer <NUM> has a conductive layer and/or a dielectric layer. According to actual requirements, multiple microstructure layers may be provided in the semiconductor functional layer <NUM>, in which formation methods of the various microstructure layers may be the same or different. Based on this, a process for forming the semiconductor functional layer <NUM> includes but is not limited to a process of epitaxis, deposition, etching, polishing and grinding, or the like.

The interconnecting layer <NUM> can be used for electrically connecting electrical signals of the semiconductor functional layer <NUM> with other interconnecting structures (for example, a conductive pillar, a interconnecting layer, etc.) and may also be used for playing a supporting role. In some embodiments, the interconnecting layer may include a top metal layer. In some specific embodiments, the material of the interconnecting layer includes, but is not limited to copper (Cu).

Here, the interconnecting layer <NUM> is formed on the semiconductor functional layer <NUM> by a process of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

It should be noted that any signal connected by the redistribution layer formed in the subsequent manufacturing process is connected to the interconnecting layer <NUM>, that is, the function of the semiconductor functional structure <NUM> is guaranteed to be complete even without the redistribution layer.

In some embodiments, referring to <FIG>, parts of the interconnecting layer <NUM> are removed before forming the isolation layer <NUM> to reduce the total area of the interconnecting layer corresponding to the redistribution layer.

Here, the removed parts of the interconnecting layer <NUM> are the parts that are not physically connected to other interconnecting structures. The process for removing the part of the interconnecting layer <NUM> includes, but is not limited to an etching process.

Understandably, considering that parasitic capacitance may be introduced with the introduction of the redistribution layer to the large area where the top metal layer is windowed in a subsequent process, reducing the total area of the interconnecting layer is equivalent to reduction of an area of a electrode of the parasitic capacitance formed by the interconnecting layer and the redistribution layer, so that the reduction of the total area of the interconnecting layer <NUM> is beneficial to reducing additional parasitic capacitance caused by the interconnecting layer <NUM>.

It should be noted that <FIG> shows a cross-sectional diagram of a partial section after parts of the interconnecting layer <NUM> are removed. In practical application, the parts of the interconnecting layer are not separated, but interconnected, that is, from another cross section view, the parts of the interconnecting layer are continuous.

At S102, the first pad for performing a first type test is formed.

Specifically, referring to <FIG>, the isolation layer <NUM> is formed on the interconnecting layer <NUM>.

Here, the isolation layer <NUM> is used to protect the interconnecting layer <NUM> from being damaged. The material of the isolation layer <NUM> includes, but is not limited to, tetraethyl orthosilicate (TEOS). A process for forming the isolation layer <NUM> includes, but is not limited to, a process of PVD, CVD, ALD or the like.

In the embodiment of the disclosure, a part region of the isolation layer <NUM> is removed so that the isolation layer <NUM> has a plurality of via holes <NUM>. Each via hole <NUM> exposes part of the interconnecting layer <NUM>, and the exposed part of the interconnecting layer <NUM> acts as the first pad <NUM>.

Here, the via hole <NUM> may have a shape of a cylinder or an inverted trapezoid or any suitable shapes. A cross-sectional area of the via hole includes an area of the orthographic projection of the via hole <NUM> on the plane where the interconnecting layer is located. However, it should be noted that when the via hole <NUM> has a shape of inverted trapezoid, the cross-sectional area of the first pad <NUM> is the smallest cross-sectional area of the via hole <NUM>.

In practical application, on the one hand, the first pad <NUM> is used for performing the first type test; on the other hand, it can be used for executing functional interactions corresponding to contents of the first type test.

The first type test is understood as some tests performed on the semiconductor functional structure when a running speed is low.

It should be noted that in a memory, a running speed refers to the reading or writing speed of the memory.

Here, the first pad <NUM> can be used to contact with a probe card to realize an electrical connection between the interconnecting layer and other test systems when performing the first type test, and can also be used for leading out a bonding wire which is electrically connected to the interconnecting layer <NUM> by the first pad <NUM>.

On the one hand, it is understandable that due to the limitation of a test probe card and a pad of wire bonding package, there is a minimum area requirement for windowing region (that is, the area of the first pad) in the top metal layer windowing manner. While, in the redistribution layer windowing manner, there is only a limitation of the minimum area of the region connected to the interconnecting layer.

On the other hand, considering that in the embodiment of the disclosure, both the top metal layer windowing manner and the redistribution layer windowing manner are adopted, a top metal layer and a redistribution layer respectively with a large area are inevitably required, either of which introduces additional parasitic capacitance. Exemplarily, the introduced additional parasitic capacitance is detrimental to high-speed ports of a low power double data rate (LPDDR).

Based on this, after that the test at a low speed is stable (after first type test meets a preset condition) and the process is mature, it is necessary to start to debug the performance at a high speed, and pads of the redistribution layer are needed. In this case, the large top metal layer prepared for windowing can be tailored, provided that it meets the design requirements.

After completing the first type test, the first pad can be cut to reduce its area to a minimum area as long as it satisfies the connection between the redistribution layer an the interconnecting layer.

In view of this, in this Application, referring to <FIG>, after completing the first type test, part of the first pad <NUM> is removed to form a fourth pad <NUM>. The area of the fourth pad <NUM> is smaller than an area of the first pad <NUM>.

Here, the removed part of the interconnecting layer <NUM> is the part of the first pad <NUM>, and the remaining part of the first pad <NUM> is the fourth pad <NUM>. As can be seen from the drawings, the area of the first pad <NUM> is slightly greater than a cross-sectional area of the via hole <NUM>, and the area of the fourth pad <NUM> is apparently less than the cross-sectional area of the via hole <NUM>. Based on this, it can be understood that the area of fourth pad <NUM> is less than the cross-sectional area of the via hole <NUM>.

It is understandable that, by reducing the area of the first pad <NUM>, on one hand, additional parasitic capacitance caused by the first pad <NUM> can be reduced; on the other hand, parasitic resistance and electro-migration are reduced, thereby further meeting the production requirements.

Exemplarily, referring to <FIG>, the area of the first pad <NUM> is reduced to the area of the fourth pad <NUM>, and the parasitic capacitance of a semiconductor device is decreased by <NUM>%.

It should be noted that <FIG> shows corresponding top views of <FIG> and <FIG>.

In an actual manufacturing process not forming part of the present invention but useful for understanding, whether to reduce the area of the first pad to the area of the fourth pad can be selected according to actual requirements. In the present invention, the area of the first pad is reduced to the area of the fourth pad.

However, in order to clearly describe the disclosure, in the following part, description is made by taking the case that the first pad area is not reduced as an example. That is, in <FIG>, the redistribution layer is still formed on the basis of the first pad, but the description applies correspondingly to the fourth pad.

At S103, referring to <FIG>, after completing the first type test, a redistribution layer <NUM> is formed.

It should be noted that completing the first type test includes performing and passing the first type test. Passing the first type test includes that a result of the first type test meets the preset conditions. The preset conditions can be understood as the test requirements set for the semiconductor functional structure <NUM> according to actual requirements.

Here, after the result of the first type test meets the preset conditions, the redistribution layer <NUM> is formed on the first pad <NUM> and the isolation layer <NUM>. The redistribution layer <NUM> and the interconnecting layer <NUM> are electrically connected.

In some embodiments, when the result of the first type test does not meet the preset conditions, the subsequent process of the packaging method provided by the embodiment of the disclosure for the further manufacture may not be carried out, and the tested semiconductor functional structure <NUM> is adjusted until a result of the first type test meets the preset condition, and then the subsequent process of the packaging method provided by the embodiment of the disclosure for the further manufacture is carried out.

Here, the material constituting the redistribution layer <NUM> includes, but is not limited to, a metal. Preferably, the material of the redistribution layer is aluminum (Al).

In some specific examples, a specific manner of forming the redistribution layer <NUM> includes: forming a new wire pattern on the isolation layer <NUM> in an exposure and development manner, and then forming the redistribution layer <NUM> according to the new wire pattern by an electroplating technique. The redistribution layer <NUM> includes new wire paths, which are electrically connected to the interconnecting layer <NUM>.

In some specific example, forming the redistribution layer on the first pad and the isolation layer includes: forming the redistribution layer <NUM> on the first pad <NUM> and the isolation layer <NUM> by a maskless deposition process.

The maskless deposition process can be understood as forming the redistribution layer <NUM> directly on the first pad <NUM> and the isolation layer <NUM> without forming a mask.

In this way, adopting the maskless deposition process can not only save costs of a mask plate and a manufacturing equipment thereof, but also improves flexibility of the deposition process and improves the production efficiency, thereby shortening the production cycle and reducing the manufacturing costs.

At S104, referring to <FIG>, a first insulating layer <NUM> is formed on the redistribution layer <NUM>.

The first insulating layer <NUM> covers the redistribution layer to protect the redistribution layer <NUM> from being damaged. In addition, parts of the first insulating layer <NUM> are removed, to expose parts of the redistribution layer <NUM>.

The material of the first insulating layer <NUM> includes, but is not limited to, polyimide (PI).

Here, a process for forming the first insulating layer <NUM> includes, but is not limited to, a PVD process, a CVD process, an ALD process or the like. The removal process includes, but is not limited to, an etching process or the like. It should be noted that, in some example, the first insulating layer <NUM> not only exposes parts of the redistribution layer to form a second pad <NUM> and a third pad <NUM>, but also exposes the redistribution layer <NUM> located on the first pad <NUM>, such that a second insulating layer is filled in a groove formed by the redistribution layer <NUM> subsequently. At this time, the density of the second insulating layer may be equal to or less than the density of the first insulating layer <NUM>. In other examples, the first insulating layer <NUM> also covers the bottom surface and the sidewalls of the groove formed by the redistribution layer <NUM>, and the second insulating layer is subsequently formed in a groove formed by the first insulating layer <NUM>.

Referring to <FIG>, the exposed parts of the redistribution layer include the second pad <NUM> and the third pad <NUM>. The second pad <NUM> is used for performing a second type test, and the third pad <NUM> is used for executing a functional interaction corresponding to the contents of the second type test.

The second type test is understood as some tests performed on the semiconductor functional structure when the running speed is high. Executing a functional interaction corresponding to the contents of the second type test can be understood as leading out a bonding wire from the third pad.

Here, positions of the second pad <NUM> and the third pad <NUM> can be selected and disposed according to actual requirements.

That is, in some example of the disclosure, the redistribution layer <NUM> and the interconnecting layer <NUM> are electrically connected to lead out the electrical signals of the semiconductor functional structure <NUM>. Then, windowing positions of the second pad <NUM> and the third pad <NUM> are disposed according to actual requirements. Next, the electrical test and the functional interaction thereof are performed on the semiconductor functional structure <NUM> by the second pad <NUM> and the third pad <NUM>.

In other words, the redistribution layer <NUM> is used to redistribute wire paths based on the layout of the wire paths of the first pad <NUM>. Here, the redistributed wire paths are more conducive to the electrical test and functional interaction thereof of the semiconductor device.

In some embodiments, the second pad <NUM> is located at a side close to an edge of the semiconductor functional structure; and the third pad <NUM> is located at a side away from the edge of the semiconductor functional structure.

It is understandable that, controllability or adjustability of a process for leading out the bonding wire on the pad is relatively flexible, and a process for aligning the pad with the probe card is relatively difficult. Here, when the second pad <NUM> is disposed at a side close to the edge of the semiconductor functional structure; it is beneficial to reducing the difficulty of aligning the pad and the probe card, thereby reserving more flexibility for the probe card during performing the test.

In other embodiments, the second pad <NUM> is located at a side away from the edge of the semiconductor functional structure, and the third pad <NUM> is located at a side close to the edge of the semiconductor functional structure.

It is understandable that, referring to <FIG>, when the third pad <NUM> is disposed at the side close to the edge of the semiconductor functional structure, it is beneficial to shorten the length of a bonding wire welded on the third pad <NUM>, and enlarge the bonding process window.

In some example, referring to <FIG>, after the redistribution layer <NUM> is formed, the groove <NUM> is provided in the middle region of the redistribution layer <NUM> on the first pad <NUM>.

Referring to <FIG>, the method further includes forming a second insulating layer <NUM> in the groove <NUM> enclosed with the redistribution layer. A hardness of the material of the second insulating layer <NUM> is less than a hardness of the material of the redistribution layer <NUM>.

Here, as the hardness of the material of the second insulating layer <NUM> is smaller, on the one hand, it is beneficial to reduce the stress of the package structure, and increase the reliability; on the other hand, compared to the case of filling the groove with the redistribution layer, filling the groove <NUM> with the material of the second insulating layer <NUM> can avoid generating greater parasitic capacitance.

Exemplarily, the material constituting the second insulating layer <NUM> includes, but is not limited to, polyimide (PI). A process for forming the second insulating layer <NUM> includes, but is not limited to, a process of PVD, CVD, ALD or the like.

In some embodiments, materials of the second insulating layer <NUM> and the first insulating layer <NUM> may be the same. Correspondingly, the second insulating layer <NUM> may be formed in the same operation for forming the first insulating layer <NUM>. The second insulating layer <NUM> and the first insulating layer <NUM> are an integrated structure.

As mentioned above, the redistribution layer <NUM> is formed directly on the first pad <NUM> and the isolation layer <NUM> by the maskless deposition process, so that the redistribution layer <NUM> and the first pad <NUM> are electrically conductive by a physical contact manner.

Here, another conductive manner between the redistribution layer <NUM> and the first pad <NUM> is provided, that is, the redistribution layer <NUM> and the first pad <NUM> are electrically conductive by a conductive pillar. This manner is described in detail with reference to <FIG>, <FIG> and <FIG>.

In some examples not forming part of the present invention but useful for understanding, referring to <FIG>, <FIG> and <FIG>, the method further includes the following operations.

After completing the first type test, a conductive pillar <NUM> is formed on the first pad <NUM>; and forming the redistribution layer <NUM> on the first pad <NUM> and the isolation layer <NUM> includes: forming the redistribution layer <NUM> on the conductive pillar <NUM> and the isolation layer <NUM>. The redistribution layer <NUM> and the interconnecting layer <NUM> are electrically connected by the conductive pillar <NUM>.

Referring to <FIG>, the material of the conductive pillar <NUM> and the material of the redistribution layer <NUM> may be the same or different. It should be noted that the height of the conductive pillar <NUM> may be equal to or less than the depth of the via hole <NUM>, and <FIG> shows the case that the height of the conductive pillar <NUM> is equal to the depth of the via hole <NUM>.

Exemplarily, the material constituting the conductive pillar <NUM> includes Al, copper (Cu) or the like. A process for forming the conductive pillar includes, but is not limited to, a process of PVD, CVD, ALD or the like.

Referring to <FIG>, the redistribution layer <NUM> is formed on the first pad <NUM> and the isolation layer <NUM>. Here, the redistribution layer <NUM> and the interconnecting layer <NUM> are electrically connected by the conductive pillar <NUM>.

Referring to <FIG>, a first insulating layer <NUM> is formed on the redistribution layer <NUM>, and parts of the first insulating layer <NUM> are removed, exposing parts of the redistribution layer <NUM>.

Referring to <FIG>, the exposed parts of the redistribution layer <NUM> include a second pad <NUM> and a third pad <NUM>. The second pad <NUM> is used for performing a second type test, and the third pad <NUM> is used for executing the functional interaction corresponding to the contents of the second type test.

Here, positions of the second pad <NUM> and the third pad are selected and disposed according to actual requirements.

It should be noted that the processes for forming the redistribution layer <NUM>, the first insulating layer <NUM>, the second pad <NUM> and the third pad <NUM> have been described above and will not be repeated here.

It should be noted that, in the embodiments, referring to <FIG>, when the first type test is completed, part of the first pad <NUM> is removed to form a fourth pad <NUM>.

Referring to <FIG>, the conductive pillar <NUM> is formed on the surface of the fourth pad <NUM>.

Since the area of the fourth pad <NUM> is less than the area of the via hole <NUM>, actually, the conductive pillar <NUM> need not to fill up the via hole <NUM>, since filing up the via hole <NUM> will increase additional parasitic capacitance. In actual operations of the process, the deposition process may be performed by using the mask for etching the first pad <NUM> to form the fourth pad <NUM>, to form a third insulating layer <NUM> filling part of the via hole <NUM>, and after the third insulating layer <NUM> is formed, the conductive pillar <NUM> is formed, filling up the via hole <NUM>.

The material of the third insulating layer <NUM> includes, but is not limited to, polyimide (PI). A process for forming the third insulating layer <NUM> includes, but is not limited to, a process of PVD, CVD, ALD or the like.

Referring to <FIG>, the redistribution layer <NUM> is formed on the conductive pillar <NUM> and the isolation layer <NUM>.

In other words, the conductive pillar <NUM> is located between the fourth pad <NUM> and the redistribution layer <NUM>, and the redistribution layer <NUM> and the interconnecting layer <NUM> are electrically connected by the conductive pillar <NUM>.

It should be noted that <FIG> shows the cross-sectional diagram where the conductive pillar <NUM> has filled part of the via hole <NUM>. In practical application, the conductive pillar <NUM> may also be disposed with other shapes or at other positions.

The exposed parts of the redistribution layer <NUM> include a second pad <NUM> and a third pad <NUM>. The second pad <NUM> is used for performing a second type test, and the third pad <NUM> is used for executing the functional interaction corresponding to the contents of the second type test.

Here, positions of the second pad <NUM> and the third pad can be selected and disposed according to actual requirements.

It should be noted that the processes for forming the fourth pad <NUM>, the conductive pillar <NUM>, the redistribution layer <NUM>, the first insulating layer <NUM>, the second pad <NUM> and the third pad <NUM> are described above and will not be repeated here.

The number of the conductive pillar <NUM> formed in the same via hole <NUM> in the above embodiment may be one or more. Accordingly, each conductive pillar <NUM> corresponds to a fourth pad <NUM>, that is, when the number of conductive pillar <NUM> is more than one, a plurality of fourth pad <NUM> are provided at the bottom of the same one via hole <NUM>.

It can be understood that when the number of conductive pillar <NUM> includes multiple ones, the multiple conductive pillars <NUM> are respectively connected to the redistribution layer <NUM> and the interconnecting layer <NUM>, so that reliability of the electrical connection between the redistribution layer <NUM> and the interconnecting layer <NUM> can be increased.

In other words, in a package structure with multiple conductive pillars <NUM>, when one conductive pillar fails to electrically connect to the redistribution layer <NUM> and the interconnecting layer <NUM>, the other conductive pillars can connect the redistribution layer and the interconnecting layer, thereby improving the reliability of the electrical connection between the redistribution layer, the conductive pillars and the interconnecting layer.

Based on this, in the embodiments of the disclosure, the first pad is disposed on the semiconductor functional structure, which is used for performing the first type test when the running speed of the semiconductor functional structure is low,; after completing the first type test, removing part of the first pad to form a fourth pad, wherein an area of the fourth pad is smaller than an area of the first pad; after forming the fourth pad, the redistribution layer and the insulating layer are formed on the fourth pad to further form the second pad and the third pad, and the second pad is used for performing the second type test when the running speed of the semiconductor functional structure is high, and the third pad is used for executing the functional interaction corresponding to the contents of the second type test. In this way, the package structure compatible with the two types of tests is adopted in the disclosure, so that the semiconductor functional structure is satisfied with different types of tests in different process stages, thereby improving flexibility of testing, shortening the production cycle and reducing the manufacturing costs.

The isolation layer covers a surface of an interconnecting layer, the via hole exposes part of the interconnecting layer, and the interconnecting layer is disposed on a surface of a semiconductor functional structure.

The fourth pad consists of the interconnecting layer exposed by the isolation layer, an area of the fourth pad is less than a cross-sectional area of the via hole, and the cross-sectional area of the via hole is set according to requirements of a first type test.

The redistribution layer covers the isolation layer and is electrically connected with the fourth pad.

The first insulating layer covers and exposes parts of the redistribution layer.

The exposed parts of the redistribution layer include a second pad and a third pad. The second pad is used for performing a second type test, and the third pad is used for executing a functional interaction corresponding to contents of the second type test. A running speed of the semiconductor functional structure when performing the first type test is lower than a running speed when performing the second type test.

In some embodiments, the package structure further includes a conductive pillar.

The conductive pillar is located between the fourth pad and the redistribution layer, and the redistribution layer and the interconnecting layer are electrically connected by the conductive pillar.

In some embodiments, the number of the conductive pillar is one or more.

In some embodiments, the package structure further includes: a second insulating layer.

The second insulating layer is located in a groove surrounded the redistribution layer.

A hardness of a material of the second insulating layer is less than a hardness of a material of the redistribution layer.

In some embodiments, the second pad is located at a side close to an edge of the semiconductor functional structure; and the third pad is located at a side away from the edge of the semiconductor functional structure.

According to another aspect of the disclosure, embodiments of the disclosure further provide a semiconductor device, including: the package structure described in the foregoing embodiments of the disclosure.

In some embodiments, the semiconductor device further includes: a substrate and a plurality of bare chips.

The plurality of dies are stacked, each die includes a semiconductor functional structure and the package structure located on the semiconductor functional structure.

Each die is electrically connected to the substrate by a lead on a third pad of the package structure.

It should be noted that in the above embodiment of the disclosure, the package structure compatible with the two types of tests is adopted, so that the semiconductor functional structure can satisfied with the different types of tests in different manufacture procedure stages. However, it should be noted that in a layout design of the package structure, the position of the via hole of the redistribution layer needs to be reserved on the top metal layer to ensure that when the redistribution layer needs to be added, it is not necessary to modify the top metal layer or any photolithography plate and the process.

In addition, in the layout design, it is necessary to consider the layout of the top metal layer and its windowing (such as, the interconnecting layer and the first pad) and the layout of the redistribution layer and its windowing (the second pad and the third pad) at the same time. When a process is performed corresponding to different layout levels or photolithography plates, the two windowing regions cannot be opened at the same time.

Based on this, referring to <FIG>, according to an aspect of embodiments of the disclosure, a semiconductor device layout structure is also provided, including: a semiconductor functional structure layout layer <NUM> and a package structure layout layer <NUM> which are stacked. The package structure layout layer <NUM> includes a plurality of first type pad regions <NUM>, in which each first type pad region includes a partial interconnecting layer region 5021a and a first pad region5021b located in the partial interconnecting layer region 5021b; a plurality of conductive pillar regions <NUM>, in which each conductive pillar region is located on a corresponding first type pad region; and a plurality of second type pad regions <NUM>, in which each second type pad region is located on a corresponding conductive pillar region of the first type pad region, and includes: a redistribution layer region 5023a, and a second pad region 5023b and a third pad region 5023c located in the redistribution layer region. An orthographic projection of the first pad region on a preset plane and an orthographic projection of the redistribution layer region on the preset plane have an overlapping region, an orthographic projection of the conductive pillar region on the preset plane is located in the overlapping region, and the preset plane is perpendicular to the stacking direction.

Based on the above semiconductor device layout structure, embodiments of the disclosure also provide an application method of the semiconductor device layout structure, which includes: by utilizing the semiconductor device layout structure described in the above embodiments of the disclosure, forming a semiconductor functional structure and a plurality of first type pads, or forming a semiconductor functional structure, a plurality of first type pads, and a plurality of second type pads.

It should be noted that in a design, the layout of the top metal layer windowing (the first type pad regions) and the layout of the redistribution layer windowing (the second type pad regions) are designed at the same time, but the two windowing correspond to different layout levels or photolithography plates, that is, it is guaranteed that two windowing regions cannot be opened at the same time. That is, the semiconductor functional structure, the plurality of first type pads, the plurality of second type pads and their corresponding layout structures illustrated in the embodiments of the disclosure can be used separately.

In several embodiments provided by the disclosure, it should be understood that the disclosed devices and methods may be implemented in a non-target way. The above-described device embodiments are only schematic. For example, the division of the units is only a logical function division, and there may be other division modes in actual implementation, such as, multiple units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the components shown or discussed may be coupled, or directly coupled to each other.

The units described above as separate parts may or may not be physically separate, and the parts shown as a unit may or may not be a physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units may be selected according to actual requirements to achieve the purpose of the solutions of the embodiments of the disclosure.

The features disclosed in several embodiments of the method or the device provided by the disclosure may be arbitrarily combined, as long as there is no conflict, to obtain a new embodiment of the method or a new embodiment of the device.

The above are only specific embodiments of the disclosure, and the scope of protection of the disclosure is only limited to the claims. Changes or replacements can be easily conceived of by any person skilled in the art. Therefore, the protection scope of the disclosure is defined by the protection scope of the claims.

Claim 1:
A packaging method, comprising:
providing a semiconductor functional structure (<NUM>), the semiconductor functional structure (<NUM>) comprising a semiconductor functional layer (<NUM>) and an interconnecting layer (<NUM>) being provided on a surface of the semiconductor functional layer (<NUM>);
forming an isolation layer (<NUM>) exposing part of the interconnecting layer (<NUM>), the exposed part of the interconnecting layer (<NUM>) acting as a first pad (<NUM>), and the first pad (<NUM>) being used for performing a first type test;
after completing the first type test, removing part of the first pad (<NUM>) to form a fourth pad (<NUM>), wherein an area of the fourth pad (<NUM>) is smaller than an area of the first pad (<NUM>); after forming the fourth pad (<NUM>), forming a redistribution layer (<NUM>) on the fourth pad (<NUM>) and the isolation layer (<NUM>), the redistribution layer (<NUM>) and the interconnecting layer (<NUM>) being electrically connected; and
forming a first insulating layer (<NUM>) exposing parts of the redistribution layer (<NUM>), the exposed parts of the redistribution layer (<NUM>) acting as a second pad (<NUM>) and a third pad (<NUM>), the second pad (<NUM>) being used for performing a second type test, and the third pad (<NUM>) being used for executing a functional interaction corresponding to contents of the second type test; wherein a running speed of the semiconductor functional structure (<NUM>) when performing the first type test is lower than a running speed of the semiconductor functional structure (<NUM>) when performing the second type test.