Patent Description:
Address translation units are commonly used by operating systems to translate one address domain into another address domain. In some instances, the other address domain is larger than the original address domain, thereby enabling the operating system to shift to an expanded number of address domains. <CIT> discloses a processing device for transforming and managing linear memory address in computing device, has linear address transformation circuit for replacing each of set of metadata bits with constant value.

The subject disclosure describes, among other things, illustrative embodiments for performing address translations. Other embodiments are described in the subject disclosure.

One or more aspects of the subject disclosure include a method for receiving addressable information on an address bus, receiving attribute information on an attribute bus having a number of attribute bit lines, remapping the address bus into a first remapped address bus by replacing bit lines of the address bus with the attribute bit lines of the attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the address bus, the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the address bus, and the first remapped address bus supplying updated address information, connecting the first remapped address bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to an expanded address bus, and remapping the expanded address bus into a second remapped address bus by replacing bit lines of the expanded address bus with the bit lines of the address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the expanded address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the expanded address bus, and the second remapped address bus supplying updated translated address information.

One or more aspects of the subject disclosure include an integrated circuit device having a first address bus, and an address translation unit (ATU). The integrated circuit can be configured for remapping the first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the first address bus, and the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the first address bus, and the first remapped address bus supplying updated first address information, connecting the first remapped address bus to the ATU, the ATU configured to translate the updated first address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the second address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the second address bus, and the second remapped address bus supplying updated translated address information.

One or more aspects of the subject disclosure include a method for remapping a first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the first remapped address bus supplying updated address information, connecting the first remapped address bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing bit lines of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the second remapped address bus changing the translated address information into updated translated address information. The method may further comprise supplying at least a portion of the updated translated address information to a bus of an integrated circuit device. The ATS may operate in a processor. The method may further comprise connecting a first register and a second register to the ATU, the first register identifying a window size, and the second register supplying addressable data to a portion of the second address bus. An operating system may utilize the first register, the second register, attribute bus, or combinations thereof to control translation operations performed by the ATS.

<FIG> is a block diagram illustrating an exemplary, non-limiting embodiment of an Address Translation Unit (ATU) <NUM> in accordance with various aspects described herein. In one embodiment, the ATU <NUM> can be supplied from a first register (REG1) <NUM>, a second register (REG2) <NUM> and an address bus <NUM>. The first register (REG1) <NUM> can correspond to, for example, an outbound translated extended address register (herein referred to as OTEA register <NUM>). The second register (REG2) <NUM> can correspond to an outbound window size register (herein referred to as OWS register <NUM>). The OWS register <NUM> can be a five-bit register for identifying a window size in increments of <NUM> Kbytes increments * <NUM>n (where n is the value of the OWS register <NUM>). This results in table entries ranging from, for example, <NUM> Kbytes (<NUM>) to <NUM> GBytes (<NUM>). The window size can be used by the ATU <NUM> as an index into a look-up table in the ATU <NUM> to determine a translation range for address information supplied by a set of bit lines of the address bus <NUM> (e.g., upper bit lines Addr[<NUM>:<NUM>]).

If the ATU <NUM> determines that the address information supplied by the set of bit lines of the address bus <NUM> matches the translation range associated with the window size selected according to the OWS register <NUM>, then the ATU <NUM> performs an address translation of the address information supplied by the set of bit lines of the address bus <NUM>. If there is no match, then in one embodiment the ATU <NUM> performs a pass thru of the address information or supplies a default address supplied in the table entry selected by the OWS register <NUM>. The result of the translation operation is supplied to a translated address bus <NUM> that may be the same size or larger than the address bus <NUM> (e.g., <NUM>-bit address translated to a <NUM>-bit address). The translated address bus <NUM> in turn can be connected in whole or in part to an Integrated Circuit (IC) <NUM> such as a volatile memory (e.g., DRAM, SRAM, etc.), non-volatile memory (e.g., Flash drive or SSD, Hard Disk Drive or HDD, etc.), or other suitable device that can make use of the translated address bus <NUM>.

<FIG> is a block diagram illustrating an exemplary, non-limiting embodiment of the address translation performed by the ATU <NUM> of <FIG> in accordance with various aspects described herein. In this illustration, the input sources of the ATU <NUM> are the OTEA register <NUM> [<NUM>:<NUM>], the OWS register <NUM> [<NUM>:<NUM>] and the address bus <NUM> [<NUM>:<NUM>]. As depicted in <FIG>, the translated bus <NUM> (labeled as ATU_OUT in the table) corresponds to an expanded <NUM>-bit bus. The upper <NUM> bits (ATU_out [<NUM>:<NUM>]) correspond to a pass-thru of the OTEA register [<NUM>:<NUM>]. Similarly, the lower <NUM> bits (ATU_out[<NUM>:<NUM>]) correspond to a pass-thru of the lower <NUM> bits of the address bus <NUM> (Addr in [<NUM>:<NUM>]).

The OWS register <NUM> provides a window size to the ATU <NUM>. The ATU <NUM> uses the window size to select a table entry having a given address range to determine whether the address information provided in the portion Addr_in [<NUM>:<NUM>] of the address bus <NUM> matches the address range in the selected table. If there is a match, the address information provided in Addr_in [<NUM>:<NUM>] is replaced with a pre-define address supplied by the table. The translation is then supplied to ATU_out [<NUM>:<NUM>]. If the address information in Addr_in [<NUM>:<NUM>] does not match the address range in the selected table, then the ATU <NUM> can be configured to pass-thru the address information in Addr_in [<NUM>:<NUM>] or a default address in the table that is supply to ATU_out [<NUM>:<NUM>]. All or a portion of the bit lines of the translated address bus <NUM> can be connected to one or more devices (e.g., volatile or non-volatile memories, or other devices) that can make use of the address translation.

It will be appreciated that the above illustrations can be adapted for larger or smaller address bus translations (e.g., <NUM>-bit address bus translated to a <NUM>-bit expanded address bus). The ATU <NUM> illustrations of <FIG> enable a selective translation of some or all addresses from one address space into another address space. Examples of its use include remapping a virtual address in a system running multiple virtual operating systems (OSes) to a physical address, and/or remapping a <NUM>-bit address of a system memory map into a larger actual memory map.

<FIG> is a block diagram illustrating an exemplary, non-limiting embodiment of an Address Translation System (ATS) <NUM> in accordance with various aspects described herein. The ATS <NUM> differs from the ATU <NUM> of <FIG> in that it provides additional remapping capabilities without altering the operations of the ATU <NUM>. In particular, the ATS <NUM> can provide additional address translation capabilities by ignoring certain address bits of the address bus <NUM> that are not used during the translation process performed by the ATU <NUM> (e.g., address bits Addr_in[<NUM>:<NUM>]). The unused bits are depicted by bus <NUM>, which as will be shown are restored after the translation is performed.

In one embodiment, the ATS <NUM> comprises two remapping stages <NUM> and <NUM> that are positioned, respectively, at the input bus <NUM> and translated address bus <NUM> of the ATU <NUM>. The first remapping stage <NUM> receives inputs from an attribute bus <NUM> and the address bus <NUM>. The attribute bus <NUM> can be sourced from, for example, sideband information that is known by and provided by a processor with each transaction on a bus, such as whether a transaction contains code versus data, or whether it is a secure or non-secure transaction, or what domain a transaction is associated with (for processors capable of supporting multiple domains). The processor can represent one or more central processing units (CPUs) executing one or more operating systems, each performing memory management functions. It will be appreciated that the processor may correspond to one or more virtual machines (VMs) that each can be reprogrammed so as to adapt the number of CPUs, memory resources assigned to each VM.

The attribute bus <NUM> can be used by the one or more operating systems to expand control of the address translation function performed by the ATU <NUM>. <FIG> depicts non-limiting embodiments that describe how the remapping stages <NUM> and <NUM> can be used without changing the original function of the ATU <NUM> previously described in <FIG>. In one embodiment, the first remapping stage <NUM> does not connect to the input bus <NUM> of the ATU <NUM> the unused bits of the address bus <NUM> depicted as Addr_in[<NUM>:<NUM>] to make room for an attribute bus <NUM>. Instead, the unused bits are fed into the second remapping stage <NUM> depicted as bus <NUM>. The remaining lower <NUM> bits of the address bus <NUM> Addr_in[<NUM>:<NUM>] are connected to the input bus <NUM> as ATU_in[<NUM>:<NUM>].

In one embodiment, the attribute bus <NUM> can correspond to a <NUM>-bit bus depicted as Attr[<NUM>:<NUM>] which is remapped by the first remapping stage <NUM> into the upper <NUM>-bits of the input bus <NUM> of the ATU <NUM>, depicted as ATU_in[<NUM>:<NUM>]. In one embodiment, placing the attribute bus <NUM> in the upper <NUM>-bits of the input bus <NUM> requires an exact match by the ATU <NUM> during the matching process. A portion of the remaining upper bits of the address bus <NUM> Addr_in[<NUM>:<NUM>] are connected to the remaining upper bits of the input bus <NUM> of the ATU <NUM>, depicted as ATU_in[<NUM>:<NUM>]. These bits serve as a <NUM>-bit window base address that are matched subject to the window size provided by the OWS register <NUM>. The foregoing remapping process results in window sizes of the OWS register <NUM> in increments of 1MB increments * <NUM>n (where n is the value of the OWS register <NUM>). This results in table entries ranging from, for example, 1MB (<NUM>) to 2GB (<NUM>), which is in contrast to the 64KB increments * <NUM>n ranging from 64KB to 2GB as described in <FIG>. Although the OWS register <NUM> has an adjusted window size of 1MB increments * <NUM>n, to the ATU <NUM> the window size increments remain as 64KB increments * <NUM>n.

The removal of bit lines Addr_in[<NUM>:<NUM>] from the input bus <NUM>, makes room for the attribute bus <NUM>, depicted as Attr[<NUM>:<NUM>], to be connected to the upper <NUM> bits ATU_in[<NUM>:<NUM>] of the <NUM>-bit input bus <NUM>. The <NUM>-bit window base Addr_in[<NUM>:<NUM>] is remapped to ATU_in[<NUM>:<NUM>] of the <NUM>-bit input bus <NUM> to make room for the attribute bus <NUM> in the upper <NUM> bits of the input bus <NUM>. As previously described, the ATU <NUM> has two input register inputs <NUM> and <NUM>, respectively, that for this illustration serve as OTEA register [<NUM>:<NUM>] and OWS register <NUM> [<NUM>:<NUM>], respectively. In this arrangement, the ATU <NUM> is configured to produce a translated bus that is expanded to <NUM> bits. The OTEA register [<NUM>:<NUM>] is supplied to bit lines ATS_out[<NUM>:<NUM>], while ATU_in[<NUM>:<NUM>] is supplied to bit lines ATS_out[<NUM>:<NUM>] with no translation. The ATU <NUM> will be configured to translate (or not translate) the combination of the attribute bus <NUM> represented by ATU_in[<NUM>:<NUM>] and the <NUM>-bit window base Addr_in[<NUM>:<NUM>] depending on the table entry associated with the window size provided by the OWS register <NUM>. If the portion of the attribute bus <NUM> located in bit lines ATU_in[<NUM>:<NUM>] and at least a portion of bit lines ATU_in[<NUM>:<NUM>] matches the address range in the selected table entry, then the ATU <NUM> will generate an address translation, which will be placed in bit lines ATS_out[<NUM>:<NUM>].

If a match does not occur, the ATU <NUM> will either cause a pass-thru of bit lines ATU_in[<NUM>:<NUM>], supply a default address to bit lines ATS_out[<NUM>:<NUM>], or a combination thereof. The second remapping stage <NUM> can be configured to update the translated address bus <NUM> and generate a remapped address bus <NUM>. The remapped address bus <NUM> restores address bit lines Addr_in[<NUM>:<NUM>] by placing them in bit lines ATS_out[<NUM>:<NUM>]. This remapping process effectively results in a pass-thru of bit lines Addr_in[<NUM>:<NUM>] of the address bus <NUM> to bit lines ATS_out[<NUM>:<NUM>]. As shown in <FIG>, the second remapping stage <NUM> causes a pass-thru of the OTEA register <NUM> to bit lines ATS_out[<NUM>:<NUM>], an address translation (if any) into ATS_out[<NUM>:<NUM>], a restoration of address bit lines Addr_in[<NUM>:<NUM>] in bit lines ATS_out[<NUM>:<NUM>], and a pass thru of Addr_in[<NUM>:<NUM>] in ATS_out[<NUM>:<NUM>]. All or a portion of the <NUM>-bit remapped address bus <NUM> depicted as ATS_out[<NUM>:<NUM>] is then supplied to IC <NUM>.

The foregoing process takes advantage of unused bit lines from the address bus <NUM> to add more flexibility in controlling the address translation process performed by the ATU <NUM> without altering the ATU <NUM> itself. It will be appreciated that the illustrations of <FIG> and <FIG> can be adapted to more or less bits (e.g., <NUM>-bit line address bus <NUM> and <NUM>-bit line remapped address bus <NUM>). It will be further appreciated that a larger or smaller attribute bus <NUM> can be used depending on the input size of the address bus <NUM> and a number of available unused (untranslatable) bit lines of the address bus <NUM>.

<FIG> depicts an illustrative embodiment of a method <NUM> that can be used to in accordance with various aspects described herein. Method <NUM> can begin at step <NUM> in which a first address bus and attribute bus are connected to a first remapping module. The first remapping module is configured to perform bit line remapping to a first remapped address bus. At step <NUM>, for example, bit lines of the first address bus and bit lines of the attribute bus can be remapped by the first remapping module to produce the first remapped address bus. To remap the attribute bus into the first remapped address bus, the first remapping module can be configured to withdraw (or ignore) certain untranslatable bit lines of the first address bus to make room for the attribute bus in the first remapped address bus.

The first remapped address bus is connected to an ATU at step <NUM>. At step <NUM>, the ATU can be configured to select a translation table according to an OWS register (or other data) to perform a translation of address information included in the first remapped address bus into new address information supplied by the ATU to a translated address bus connected to the ATU. In one embodiment, the translated address bus can have the same number of bit lines as the first remapped address bus (e.g., <NUM>-bit address translated to a new <NUM>-bit address). In another embodiment, the translated address bus can have a greater number of bit lines than the first remapped address bus (e.g., <NUM>-bit address translated to a new <NUM>-bit address). Having a greater number of bit lines in the translated address bus enables translating an address domain of the first remapped address bus to another address domain of the translated address bus.

At step <NUM>, the ATU can be configured to determine if a portion of the address information (address bits) supplied in the bit lines of the first remapped address bus matches an address range of the table entry selected at step <NUM>. The address information included in the portion of the bit lines used for determining whether a match exists can include, for example, bit information provided in bit lines of the attribute bus that were remapped at step <NUM> into bit lines of the first remapped address bus and a portion of the address bits retained in bit lines of the first address bus that were similarly remapped at step <NUM> into bit lines of the first remapped address bus.

If a match is not detected at step <NUM>, the ATU can proceed to step <NUM> and pass thru a portion of the address information of the first remapped address bus (or a default address supplied by the table entry) to the translated address bus. If a match is detected at step <NUM>, the ATU can translate at step <NUM> a portion of the address information in the first remapped address bus and supply the translated address to the translated address bus. At step <NUM>, bit lines of the translated address bus can be remapped, by a second remapping module, into bit lines of a second remapped address bus by, for example, restoring at least a portion of the unused (or ignored) address bit lines of the first address bus that made room for the attribute bus during the remapping process performed by the first remapping module at step <NUM>. The second remapped address bus can be connected in whole or in part at step <NUM> to an IC device to control, for example, volatile or non-volatile memory usage of the IC device.

While for purposes of simplicity of explanation, the respective processes are shown and described as a series of blocks in <FIG>, it is to be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein. Moreover, not all illustrated blocks may be required to implement the methods described herein.

Turning now to <FIG>, there is illustrated a block diagram of a computing environment in accordance with various aspects described herein. In order to provide additional context for various embodiments of the embodiments described herein, <FIG> and the following discussion are intended to provide a brief, general description of a suitable computing environment <NUM> in which the various embodiments of the subject disclosure can be implemented. In particular, computing environment <NUM> can be used in the implementation of network elements <NUM>, <NUM>, <NUM>, <NUM>, access terminal <NUM>, base station or access point <NUM>, switching device <NUM>, media terminal <NUM>, and/or VNEs <NUM>, <NUM>, <NUM>, etc. Each of these devices can be implemented via computer-executable instructions that can run on one or more computers, and/or in combination with other program modules and/or as a combination of hardware and software. For example, computing environment <NUM> can facilitate in whole or in part portions of the systems of <FIG> and <FIG> for managing memory usage of any of the volatile or non-volatile memory devices described below for the computing environment <NUM>. Particularly, the processing unit <NUM> can be configured to use the ATS <NUM> to perform address translations as previously described in <FIG>. It will be further appreciated that the ATS <NUM> can be placed in other locations in <FIG> such as, for example, between Video Adaptor <NUM> and the Bus <NUM>, or between Input Device Interface <NUM> and the Bus <NUM>, or between Network Adaptor <NUM> and the Bus <NUM>.

Generally, program modules comprise routines, programs, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the methods can be practiced with other computer system configurations, comprising single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as personal computers, hand-held computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

As used herein, a processing circuit includes one or more processors as well as other application specific circuits such as an application specific integrated circuit, digital logic circuit, state machine, programmable gate array or other circuit that processes input signals or data and that produces output signals or data in response thereto. It should be noted that while any functions and features described herein in association with the operation of a processor could likewise be performed by a processing circuit.

The illustrated embodiments of the embodiments herein can be also practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

Computing devices typically comprise a variety of media, which can comprise computer-readable storage media and/or communications media, which two terms are used herein differently from one another as follows. Computer-readable storage media can be any available storage media that can be accessed by the computer and comprises both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, computer-readable storage media can be implemented in connection with any method or technology for storage of information such as computer-readable instructions, program modules, structured data or unstructured data.

Computer-readable storage media can comprise, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory, Flash drive such as a Solid-State Drive (SSD), or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or other tangible and/or non-transitory media which can be used to store desired information. In this regard, the terms "tangible" or "non-transitory" herein as applied to storage, memory or computer-readable media, are to be understood to exclude only propagating transitory signals per se as modifiers and do not relinquish rights to all standard storage, memory or computer-readable media that are not only propagating transitory signals per se.

Computer-readable storage media can be accessed by one or more local or remote computing devices, e.g., via access requests, queries or other data retrieval protocols, for a variety of operations with respect to the information stored by the medium.

Communications media typically embody computer-readable instructions, data structures, program modules or other structured or unstructured data in a data signal such as a modulated data signal, e.g., a carrier wave or other transport mechanism, and comprises any information delivery or transport media. The term "modulated data signal" or signals refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in one or more signals. By way of example, and not limitation, communication media comprise wired media, such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

With reference again to <FIG>, the example environment can comprise a computer <NUM>, the computer <NUM> comprising a processing unit <NUM>, a system memory <NUM> and a system bus <NUM>. The system bus <NUM> couples system components including, but not limited to, the system memory <NUM> to the processing unit <NUM>. The processing unit <NUM> can be any of various commercially available processors. Dual microprocessors and other multiprocessor architectures can also be employed as the processing unit <NUM>.

The system bus <NUM> can be any of several types of bus structure that can further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory <NUM> comprises ROM <NUM> and RAM <NUM>. A basic input/output system (BIOS) can be stored in a non-volatile memory such as ROM, erasable programmable read only memory (EPROM), EEPROM, which BIOS contains the basic routines that help to transfer information between elements within the computer <NUM>, such as during startup. The RAM <NUM> can also comprise a high-speed RAM such as static RAM for caching data, Dynamic RAM (DRAM), or combinations thereof.

The computer <NUM> further comprises an internal hard disk drive (HDD) <NUM> (e.g., EIDE, SATA), which internal HDD <NUM> can also be configured for external use in a suitable chassis (not shown), a magnetic floppy disk drive (FDD) <NUM>, (e.g., to read from or write to a removable diskette <NUM>) and an optical disk drive <NUM>, (e.g., reading a CD-ROM disk <NUM> or, to read from or write to other high-capacity optical media such as the DVD). The HDD <NUM>, magnetic FDD <NUM> and optical disk drive <NUM> can be connected to the system bus <NUM> by a hard disk drive interface <NUM>, a magnetic disk drive interface <NUM> and an optical drive interface <NUM>, respectively. The hard disk drive interface <NUM> for external drive implementations comprises at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) <NUM> interface technologies. Other external drive connection technologies are within contemplation of the embodiments described herein.

The drives and their associated computer-readable storage media provide nonvolatile storage of data, data structures, computer-executable instructions, and so forth. For the computer <NUM>, the drives and storage media accommodate the storage of any data in a suitable digital format. Although the description of computer-readable storage media above refers to a hard disk drive (HDD), a removable magnetic diskette, and a removable optical media such as a CD or DVD, it should be appreciated by those skilled in the art that other types of storage media which are readable by a computer, such as zip drives, magnetic cassettes, flash memory cards, a Flash drive such as a Solid-State Drive (SSD), cartridges, and the like, can also be used in the example operating environment, and further, that any such storage media can contain computer-executable instructions for performing the methods described herein.

A number of program modules can be stored in the drives and RAM <NUM>, comprising an operating system <NUM>, one or more application programs <NUM>, other program modules <NUM> and program data <NUM>. All or portions of the operating system, applications, modules, and/or data can also be cached in the RAM <NUM>. The systems and methods described herein can be implemented utilizing various commercially available operating systems or combinations of operating systems.

A user can enter commands and information into the computer <NUM> through one or more wired/wireless input devices, e.g., a keyboard <NUM> and a pointing device, such as a mouse <NUM>. Other input devices (not shown) can comprise a microphone, an infrared (IR) remote control, a joystick, a game pad, a stylus pen, touch screen or the like. These and other input devices are often connected to the processing unit <NUM> through an input device interface <NUM> that can be coupled to the system bus <NUM>, but can be connected by other interfaces, such as a parallel port, an IEEE <NUM> serial port, a game port, a universal serial bus (USB) port, an IR interface, etc..

A monitor <NUM> or other type of display device can be also connected to the system bus <NUM> via an interface, such as a video adapter <NUM>. It will also be appreciated that in alternative embodiments, a monitor <NUM> can also be any display device (e.g., another computer having a display, a smart phone, a tablet computer, etc.) for receiving display information associated with computer <NUM> via any communication means, including via the Internet and cloud-based networks. In addition to the monitor <NUM>, a computer typically comprises other peripheral output devices (not shown), such as speakers, printers, etc..

The computer <NUM> can operate in a networked environment using logical connections via wired and/or wireless communications to one or more remote computers, such as a remote computer(s) <NUM>. The remote computer(s) <NUM> can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network node, and typically comprises many or all of the elements described relative to the computer <NUM>, although, for purposes of brevity, only a remote memory/storage device <NUM> is illustrated. The logical connections depicted comprise wired/wireless connectivity to a local area network (LAN) <NUM> and/or larger networks, e.g., a wide area network (WAN) <NUM>. Such LAN and WAN networking environments are commonplace in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to a global communications network, e.g., the Internet.

When used in a LAN networking environment, the computer <NUM> can be connected to the LAN <NUM> through a wired and/or wireless communication network interface or adapter <NUM>. The adapter <NUM> can facilitate wired or wireless communication to the LAN <NUM>, which can also comprise a wireless AP disposed thereon for communicating with the adapter <NUM>.

When used in a WAN networking environment, the computer <NUM> can comprise a modem <NUM> or can be connected to a communications server on the WAN <NUM> or has other means for establishing communications over the WAN <NUM>, such as by way of the Internet. The modem <NUM>, which can be internal or external and a wired or wireless device, can be connected to the system bus <NUM> via the input device interface <NUM>. In a networked environment, program modules depicted relative to the computer <NUM> or portions thereof, can be stored in the remote memory/storage device <NUM>. It will be appreciated that the network connections shown are example and other means of establishing a communications link between the computers can be used.

The computer <NUM> can be operable to communicate with any wireless devices or entities operatively disposed in wireless communication, e.g., a printer, scanner, desktop and/or portable computer, portable data assistant, communications satellite, any piece of equipment or location associated with a wirelessly detectable tag (e.g., a kiosk, news stand, restroom), and telephone. This can comprise Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices.

Wi-Fi can allow connection to the Internet from a couch at home, a bed in a hotel room or a conference room at work, without wires. Wi-Fi is a wireless technology similar to that used in a cell phone that enables such devices, e.g., computers, to send and receive data indoors and out; anywhere within the range of a base station. Wi-Fi networks use radio technologies called IEEE <NUM> (a, b, g, n, ac, ag, etc.) to provide secure, reliable, fast wireless connectivity. A Wi-Fi network can be used to connect computers to each other, to the Internet, and to wired networks (which can use IEEE <NUM> or Ethernet). Wi-Fi networks operate in the unlicensed <NUM> and <NUM> radio bands for example or with products that contain both bands (dual band), so the networks can provide real-world performance similar to the basic 10BaseT wired Ethernet networks used in many offices.

The terms "first," "second," "third," and so forth, as used in the claims, unless otherwise clear by context, is for clarity only and does not otherwise indicate or imply any order in time. For instance, "a first determination," "a second determination," and "a third determination," does not indicate or imply that the first determination is to be made before the second determination, or vice versa, etc..

In the subject specification, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component, refer to "memory components," or entities embodied in a "memory" or components comprising the memory. It will be appreciated that the memory components described herein can be either volatile memory or nonvolatile memory, or can comprise both volatile and nonvolatile memory, by way of illustration, and not limitation, volatile memory, non-volatile memory, disk storage, and memory storage.

Moreover, it will be noted that the disclosed subject matter can be practiced with other computer system configurations, comprising single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as personal computers, hand-held computing devices (e.g., PDA, phone, smartphone, watch, tablet computers, netbook computers, etc.), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network; however, some if not all aspects of the subject disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

As used in some contexts in this application, in some embodiments, the terms "component," "system" and the like are intended to refer to, or comprise, a computer-related entity or an entity related to an operational apparatus with one or more specific functionalities, wherein the entity can be either hardware, a combination of hardware and software, software, or software in execution. As an example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, computer-executable instructions, a program, and/or a computer.

In addition, the words "example" and "exemplary" are used herein to mean serving as an instance or illustration. Any embodiment or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word example or exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

As employed herein, the term "processor" can refer to substantially any computing processing unit or device comprising, but not limited to comprising, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. Processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units.

As used herein, terms such as "data storage," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component, refer to "memory components," or entities embodied in a "memory" or components comprising the memory. It will be appreciated that the memory components or computer-readable storage media, described herein can be either volatile memory or nonvolatile memory or can include both volatile and nonvolatile memory.

What has been described above includes mere examples of various embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing these examples, but one of ordinary skill in the art can recognize that many further combinations and permutations of the present embodiments are possible. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim.

As may also be used herein, the term(s) "operably coupled to", "coupled to", and/or "coupling" includes direct coupling between items and/or indirect coupling between items via one or more intervening items. Such items and intervening items include, but are not limited to, junctions, communication paths, components, circuit elements, circuits, functional blocks, and/or devices. As an example of indirect coupling, a signal conveyed from a first item to a second item may be modified by one or more intervening items by modifying the form, nature or format of information in a signal, while one or more elements of the information in the signal are nevertheless conveyed in a manner than can be recognized by the second item. In a further example of indirect coupling, an action in a first item can cause a reaction on the second item, as a result of actions and/or reactions in one or more intervening items.

Claim 1:
An integrated circuit device, comprising:
a first address bus; and
an address translation unit, ATU (<NUM>), wherein the integrated circuit is configured for:
remapping the first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines of an attribute bus, the replacing resulting in substitute bit lines and remaining bit lines of the first address bus, and the first remapped address bus comprising the substitute bit lines and the remaining bit lines of the first address bus, and the first remapped address bus supplying updated first address information;
connecting the first remapped address bus to the ATU (<NUM>), the ATU (<NUM>) configured to translate the updated first address information into translated address information supplied to a second address bus; and
remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the replacing resulting in restored bit lines and remaining bit lines of the second address bus, the second remapped address bus comprising the restored bit lines and the remaining bit lines of the second address bus, and the second remapped address bus supplying updated translated address information.