Patent Description:
Memristors have been the subject of discussion and research, but have not been used in many commercial applications. <CIT> describes a multilayer memory array. <CIT> and <CIT> describe a resistive random access memory <CIT> is directed to a asymmetric switching rectifier comprising memristive switching devices.

The present invention is directed to a system comprising a multi-lead memristor according to the independent device claim <NUM> and to a method according to the independent method claim <NUM>.

In some embodiments, for a memristor element, a desired signal response can be achieved by using (e.g., modifying) at least one particular material (e.g., at least one memristor material) as a transmission medium. In some embodiments, the signal response of the memristor can be modified by controlling an oxygen vacancy transmission rate of the at least one particular material. For example, controlling the oxygen vacancy transmission rate of the at least one particular material can be achieved by a physical modification and/or a chemical modification. In some embodiments, the signal response can provide an asymmetric time based response (e.g., a homogenous asymmetric time based response and/or a compartmentalized asymmetric time based response).

Some embodiments may allow memristor characteristics to be tuned (e.g., tuned in real time during operation) to meet system design needs. Some embodiments may allow memristor elements to be tuned (e.g., additively tuned) around application specific integrated circuit (ASIC) circuitry, sometimes referred to as trimming. Some embodiments may provide circuit modification (e.g., additive circuit modification) of a memristor to improve ASIC shortcomings. Some embodiments may include tuning (e.g., additively tuning) memristor components to address timing specific needs of signal lines (e.g., key signal lines). For example, some embodiments may allow for custom signal optimization to account for a build process of circuit variance.

Some embodiments may include physically changing an order and configuration of memristor structures to develop features with unique electrical responses. For example, by controlling a geometry of a medium that is passing a signal, a movement and effect of oxygen vacancies can be controlled so as to modify a response temporarily or permanently. Such responses can inhibit an asymmetric response, a permanent penalty associated with drive direction, a time based response modification, and/or a combination thereof.

Some embodiments may allow for a potential to provide an element of repeatable uniqueness for use in anti-counterfeiting of electronic devices. Some embodiments may facilitate a generation of behavior based response techniques. Some embodiments may be useful for applications that need unique but repeatable responses (e.g., a unique fingerprint). Some embodiments may provide authenticity validation through unique but repeatable electrical responses.

Some embodiments may include at least one filter (e.g., a high pass filter and/or a low pass filter), which may include at least one memristor instead of a capacitor.

Some embodiments may include at least one multi-lead memristor.

Referring now to <FIG>, <FIG>, <FIG>, and <FIG>, examples of a system <NUM> according to the inventive concepts disclosed herein are depicted. The system <NUM> may be implemented as any suitable system, such as at least one vehicle system (e.g., at least one aircraft, at least one watercraft, at least one submersible craft, at least one automobile, and/or at least one train), a communication system, an optical system, a computing device system, a multiple computing device system, a radiofrequency (RF) device system, and/or a multiple RF device system.

For example, as shown in <FIG>, the system <NUM> may include at least one device (e.g., at least one memristor <NUM>) including at least two terminals <NUM>, at least two conductive plates <NUM>, and/or at least one memristor material <NUM>. Some or all of the at least one memristor <NUM> and/or any other components of the system <NUM> may be communicatively coupled at any given time. Some examples may include multiple memristors <NUM> implemented as a memristor network <NUM> (as shown in <FIG>). For example, the memristor network <NUM> may include a plurality of at least partially communicatively coupled (e.g., at least partially interconnected) memristors <NUM> that may be arranged in an array, in parallel, and/or in series. In some embodiments, the at least one memristor <NUM> may be fabricated on an integrated circuit (IC) device (e.g., IC <NUM>, as shown in <FIG>). The at least one memristor <NUM> may be part of a memory device (e.g., <NUM>, as shown in <FIG>).

For example, a first conductive plate <NUM> may be configured at least to receive an input signal via a first terminal <NUM>; and a second conductive plate <NUM> may be configured at least to output an output signal via a second terminal <NUM>. For example, the at least one memristor material <NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>.

The at least one memristor material <NUM> may be composed of any suitable memristor material, such as any suitable ionic-covalent metal compound. For example, each of the at least one memristor material <NUM> may comprise at least one of: at least one metal oxide (e.g., TiO<NUM>, ZrO<NUM>, NiO, CuO, CoO, Fe<NUM>O<NUM>, MoO, VO<NUM>, and/or HfO<NUM>), at least one metal sulfide, at least one metal selenide, at least one metal telluride, at least one metal nitride, at least one metal phosphite, and/or at least one metal arsenide. TiO<NUM>, ZrO<NUM>, NiO, CuO, CoO, Fe<NUM>O<NUM>, MoO, VO<NUM>, and HfO<NUM> are known in the art to be suitable memristor materials. Each memristor material <NUM> has oxygen vacancy and/or anion vacancy characteristics. Oxygen vacancy refers to a point defect in a crystal or glass where an oxygen ion is missing at an expected lattice or structure position, which results in a net positive charge, a trapped electron, and a metastable atomic structure. Anion vacancy refers to a point defect in a crystal or glass where an anion ion is missing at an expected lattice or structure position, which results in a net positive charge, a trapped electron, and a metastable atomic structure.

For example, as shown in <FIG>, the system <NUM> may include at least one computing device <NUM>. If the system <NUM> includes multiple computing devices <NUM>, some or all of the computing devices <NUM> may be communicatively coupled at any given time.

The computing device <NUM> may include at least one processor <NUM> and/or at least one memory device <NUM>, some or all of which may be communicatively coupled at any given time. Each of the processor <NUM> and/or the memory device <NUM> may include at least one circuit (e.g., at least one IC <NUM>, as shown in <FIG>).

The at least one processor <NUM> may be implemented as any suitable type and number of processors. For example, the at least one processor <NUM> may include at least one general purpose processor (e.g., at least one central processing unit (CPU)), at least one digital signal processor (DSP), at least one application specific integrated circuit (ASIC), at least one field-programmable gate array (FPGA), at least one complex programmable logic device (CPLD), and/or at least one graphics processing unit (GPU). The at least one processor <NUM> may be configured to perform (e.g., collectively perform if more than one processor) any or all of the operations disclosed throughout. The processor <NUM> may be configured to run various software and/or firmware applications and/or computer code stored (e.g., maintained) in a non-transitory computer-readable medium (e.g., memory device <NUM>) and configured to execute various instructions or operations. For example, the at least one processor <NUM> may be configured to: output a signal; receive a signal; output data to the memory device <NUM>; receive data from the memory device <NUM>; determine and/or use a signature of a received signal; perform anti-piracy operations based at least on the signature; perform cyber security authentication operations based at least on the signature; perform unique data storage operations based at least on the signature; perform usage temperature authentication operations based at least on the signature; cause a barrier material to be fused; and/or cause an activation of at least one of a blocking material, a permanent modification material, or a transfer rate modification material.

The memory device <NUM> may include the at least one memristor <NUM>, which may be implemented as the memristor network <NUM> if more than one memristor <NUM>. For example, the memory device <NUM> may be a non-volatile and/or persistent memory device. For example, the memory device <NUM> may be configured to: store data; read data; write data; output data; receive data; receive input signals; output signals; determine and/or use a signature of a received signal; perform anti-piracy operations based at least on the signature; perform cyber security authentication operations based at least on the signature; perform unique data storage operations based at least on the signature; perform usage temperature authentication operations based at least on the signature; cause a barrier material to be fused; and/or cause an activation of at least one of a blocking material, a permanent modification material, or a transfer rate modification material.

For example, as shown in <FIG>, the system <NUM> may include at least one RF tuning device <NUM>. If the system <NUM> includes multiple RF tuning devices <NUM>, some or all of the RF tuning devices <NUM> may be communicatively coupled at any given time.

The RF tuning device <NUM> may include at least one processor <NUM>, at least one IC <NUM>, and/or at least one memory device <NUM>, some or all of which may be communicatively coupled at any given time. Each of the processor <NUM>, the IC <NUM>, and/or the memory device <NUM> may include at least one circuit (e.g., at least one IC <NUM>, as shown in <FIG>). The RF tuning device <NUM> may be configured to tune RF signal outputs.

The at least one processor <NUM> may be implemented similarly and function similarly to the processor <NUM> shown in <FIG>, except that the at least one processor <NUM> may be further configured to cause RF tuning operations to be performed.

The IC <NUM> may include the at least one memristor <NUM>, which may be implemented as the memristor network <NUM> if more than one memristor <NUM>. The at least one IC <NUM> may be configured to perform (e.g., collectively perform if more than one IC) any or all of the operations disclosed throughout. The IC <NUM> may be configured to run various software and/or firmware applications and/or computer code stored (e.g., maintained) in a non-transitory computer-readable medium (e.g., memory device <NUM>) and configured to execute various instructions or operations. For example, the IC <NUM> may be configured to: output a signal; receive a signal; output data to the memory device <NUM>; receive data from the memory device <NUM>; determine and/or use a signature of a received signal; perform anti-piracy operations based at least on the signature; perform cyber security authentication operations based at least on the signature; perform unique data storage operations based at least on the signature; perform usage temperature authentication operations based at least on the signature; cause a barrier material to be fused; cause an activation of at least one of a blocking material, a permanent modification material, or a transfer rate modification material; and/or perform RF signal tuning operations.

For example, as shown in <FIG>, the system <NUM> may include at least one circuit (e.g., at least one IC <NUM>). If the system <NUM> includes multiple ICs <NUM>, some or all of the ICs <NUM> may be communicatively coupled at any given time. The at least one IC <NUM> may be implemented similarly and function similarly to the IC <NUM> shown in and described with respect to <FIG>.

Referring now to <FIG>, examples not forming part of the invention of the system <NUM> including at least one memristor <NUM> are depicted.

Referring now to <FIG>, an example of at least one memristor <NUM> is depicted.

For example, the memristor <NUM> may include a first conductive plate <NUM> configured at least to receive an input signal, a second conductive plate <NUM> configured at least to output an output signal, and at least two memristor materials (e.g., a first memristor material <NUM>-<NUM> and a second memristor material <NUM>-<NUM>). The first memristor material <NUM>-<NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>. The second memristor material <NUM>-<NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>. The first memristor material <NUM>-<NUM> and the second memristor material <NUM>-<NUM> may be in parallel electrically. The first memristor material <NUM>-<NUM> may be different from the second memristor material <NUM>-<NUM>. For example, the first memristor material <NUM>-<NUM> may be a relatively slower or faster response material than the second memristor material <NUM>-<NUM>. Memristor response may depend on the crystal chemistry, crystal phase, the amount of underproportination and disproportionation, etc. Memristor response may be influenced by the cation-anion bond strength and the cation-anion size ratio. The responsiveness of the memristor materials <NUM> can be measured. The responsiveness of the memristor materials <NUM> can be approximated by Gibbs Free Energy of Formation since Gibbs Free Energy of Formation incorporates several energy well/barrier type quantities. Based on approximated responsiveness using Gibbs Free Energy of Formation, some examples of memristor materials <NUM> ordered from relatively slower approximated responsiveness to relatively faster approximated responsiveness are: Ti<NUM>O<NUM> at - <NUM>,<NUM>,<NUM>ΔGf° (kJ/mol); Ta<NUM>O<NUM> at -<NUM>,<NUM>,<NUM>ΔGf° (kJ/mol); Sc<NUM>O<NUM> at -<NUM>,<NUM>,<NUM>ΔGf° (kJ/mol); Nb<NUM>O<NUM> at -<NUM>,<NUM>,<NUM>ΔGf° (kJ/mol); TiO<NUM> (Rutile) at -<NUM>,<NUM>ΔGf° (kJ/mol); TiO<NUM> (Anatase) at -<NUM>,<NUM>ΔGf° (kJ/mol); NbO<NUM> at -<NUM>,<NUM>ΔGf° (kJ/mol); MgO at -<NUM>,<NUM>ΔGf° (kJ/mol); and NbO at -<NUM>,<NUM>ΔGf° (kJ/mol).

The first memristor <NUM>-<NUM> material has a first current-voltage (I-V) curve, the second memristor material <NUM>-<NUM> has a second I-V curve, and the memristor <NUM> has a third I-V curve, wherein each of the first, second, and third I-V curves are different. For example, as shown in <FIG>, the third I-V curve is indicative of an asymmetric time-based response (e.g., a homogenous asymmetric time-based response). The output signal of the memristor <NUM> may have a signature based at least on the asymmetric time-based response. For example, the signature may be at least semi-unique (e.g., unique, unique to a product, or unique to a manufacturer) and/or may be indicative of at least one of an identity or an authenticity of an electronic component or device. A circuit (e.g., an IC <NUM>) may be configured to receive and use the signature of the output signal for at least one of: anti-piracy, cyber security authentication, unique data storage, electronic serialization, or usage temperature authentication (e.g., by fusing the barrier material <NUM>). For example, the signature can be achieved by strategically selection of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>), dimensions of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>), and/or an arrangement of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>). For example, the signature may be used as an identification feature for part authentication.

For example, the memristor <NUM> may be implemented similarly and function similarly to the memristor of <FIG>, except that the memristor <NUM> of <FIG> may include at least one barrier material <NUM>.

For example, the barrier material <NUM> may extend from the first conductive plate <NUM> to the second conductive plate <NUM>. The barrier material <NUM> may be positioned between the first memristor material <NUM>-<NUM> and the second memristor material <NUM>-<NUM> such that the first memristor material <NUM>-<NUM> is not in contact with the second memristor material <NUM>-<NUM>. The barrier material <NUM> may be a fuse configured to permanently configure the memristor <NUM>, for example, that may be activated thermally. For example, some examples of suitable barrier materials may include any noble metal (e.g., Au, Pt, Ag, Ir, Rh, Ru, Pd, and/or Os), highly covalently bonded material (e.g., carbon allotropes, silicon allotropes, Ge, Te, and/or Se, etc.. ), mostly elemental forms of nonmetals and metalloids which form solids at standard temperature and pressure (STP) for periodic table groups <NUM>, <NUM>, and <NUM>, or some combination thereof.

The first memristor <NUM>-<NUM> material has a first current-voltage (I-V) curve, the second memristor material <NUM>-<NUM> has a second I-V curve, and the memristor <NUM> has a third I-V curve, wherein each of the first, second, and third I-V curves are different. For example, as shown in <FIG>, the third I-V curve is indicative of an asymmetric time-based response (e.g., a compartmentalized asymmetric time-based response). The output signal of the memristor <NUM> may have a signature based at least on the asymmetric time-based response. For example, the signature may be at least semi-unique (e.g., unique, unique to a product, or unique to a manufacturer) and/or may be indicative of at least one of an identity or an authenticity of an electronic component or device. A circuit (e.g., an IC <NUM>) may be configured to receive and use the signature of the output signal for at least one of: anti-piracy, cyber security authentication, unique data storage, electronic serialization, or usage temperature authentication (e.g., by fusing the barrier material <NUM>). For example, the signature can be achieved by strategic selection of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>), dimensions of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>), and/or an arrangement of the at least two memristor materials (e.g., <NUM>-<NUM>, <NUM>-<NUM>). For example, the signature may be used as an identification feature for part authentication.

For example, the memristor <NUM> may be implemented similarly and function similarly to the memristor of <FIG> and/or <NUM>, except that the memristor <NUM> of <FIG> may include at least two of the first memristor material <NUM>-<NUM>, at least two of the second memristor material <NUM>-<NUM>, and at least two barrier material <NUM>. For example, the first memristor material <NUM>-<NUM> sections, the second memristor material <NUM>-<NUM> sections, and barrier material <NUM> sections may be interspersed (e.g., in one dimension or two dimensions (e.g., in a two-dimensional array)). In some embodiments, one or more of the barrier material <NUM> sections may be omitted. The memristor <NUM> may include more than one (e.g., two, three, four, or more) type of memristor material <NUM>.

Referring to <FIG>, the barrier material <NUM> may be used to permanently change the memristor <NUM>. For example, the barrier material <NUM> may be used to permanently change a phase of the memristor <NUM>.

For example, the barrier material <NUM> may be used to permanently configure the memristor <NUM>, for example, to set the memristor <NUM> to a known value. For example, the barrier material <NUM> may be activated thermally and act as a fusing structure. Different materials for the memristor materials <NUM>-<NUM>, <NUM>-<NUM> and/or the barrier material(s) <NUM> may be used to control a speed of and an amount of oxygen depletion transfer.

Memristors <NUM> may be arranged in an array as a memristor network <NUM>. For example, the memristor network <NUM> (e.g., which may be implemented in the RF tuning device <NUM>) may be used for configuring test values (e.g., resistance values). For example, the memristor network <NUM> may be used to tune a circuit (e.g., an IC <NUM>, such as an ASIC) by trimming resistance values (e.g., by using test selects). For example, the memristor network <NUM> may be used to tune a resistor-capacitor (RC) circuit delay. For example, such tuning may be similar to how mixed signals circuits are tuned by swapping resistors after a characterization test is complete, then retesting for proper performance. The memristor network <NUM> may be configured as multiple interconnected memristors <NUM> or as a single memristor <NUM> having multiple fuseable barrier materials <NUM>. One memristor <NUM> of the memristor network <NUM> may influence another memristor <NUM> of the memristor network <NUM>, for example, based on a fusing of a barrier material <NUM>.

At least one memristor <NUM> having at least one barrier material <NUM> may be used in the memory device <NUM> (e.g., a non-volatile memory device).

Referring now to <FIG>, an exemplary graph of current versus time is shown. The graph shows a first curve <NUM>, a second curve <NUM>, and a third curve <NUM>. The first curve <NUM> demonstrates a responsiveness of the first memristor material <NUM>-<NUM>. The second curve <NUM> demonstrates a responsiveness of the second memristor material <NUM>-<NUM>. The third curve <NUM> demonstrates a responsiveness of the memristor <NUM> having the first memristor material <NUM>-<NUM> and the second memristor material <NUM>-<NUM>. The third curve <NUM> may be indicative of an asymmetric time-based response (e.g., a homogenous asymmetric time-based response and/or a compartmentalized asymmetric time-based response) that may be associated with a signature as discussed herein.

Referring now to <FIG>, an exemplary graph of current versus time for a memristor <NUM> is shown. For example, values of the output current for the memristor <NUM> can be read at various times (e.g., <NUM> times, as shown). The combination of the values read at different times can be used as a signature as discussed herein.

Referring now to <FIG>, examples not forming part of the invention of the system <NUM> including at least one memristor <NUM> are depicted Each memristor <NUM> may include at least one blocking material <NUM>, at least one permanent modification material <NUM>, and/or at least one transfer rate modification material <NUM>.

A blocking material <NUM> may be any suitable material that does not permit transmission of a memristor charge carrying mechanism. Some examples of suitable blocking materials <NUM> include gold (Au), platinum (Pt), and/or palladium (Pd).

A permanent modification material <NUM> may be any suitable material that absorbs memristor charge carriers. An example may be a cation oxidation number change that results in absorption or generation of total oxygen vacancies. Some examples of suitable permanent modification materials <NUM> may include a metal oxide (e.g., a metal oxide near the surface of the electrode whose cation is reduced to its metallic form and whose anion fills the oxygen vacancy), such as a noble metal oxide.

A transfer rate modification material <NUM> may be any suitable material that changes a transmission rate of memristor charge carriers. An example may be a transient or residual crystallographic phase change which results in a change in oxygen vacancy transmission rate. For example, a transfer rate modification material <NUM> may be implemented by depositing a material in a metastable crystal phase or glassy phase (which may be inherently metastable) such that a thermal or optical stimulus initiates a phase shift to the more stable phase at the usage temperature. Depositing in a metastable phase can be accomplished by modifying the deposition rate, substrate biasing, and/or deposition pressure. Since the oxygen vacancy conduction rate is dependent on the crystal phase, the memristor response will be different after the phase transformation. For such an example, TiO2 in Rutile and Anatase may have a different memristor response since the bond strength is different and the crystal geometry is different. Additionally, for example, a transfer rate modification material <NUM> may be implemented by depositing a material that has a crystal phase transition over the operation temperature. The memristor response would change discontinuously at the temperature where the crystal phase changes. For example, VO<NUM> has a monoclinic to tetragonal crystal phase transition around <NUM> degrees Celsius and may be a suitable transfer rate modification material <NUM>.

Referring now to <FIG>, an example of at least one memristor <NUM> is depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor <NUM> of <FIG>, except that the memristor <NUM> of <FIG> may include at least one transfer rate modification material <NUM>.

The transfer rate modification material <NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>. At least a portion of the transfer rate modification material <NUM> may abut the memristor material <NUM>. The transfer rate modification material <NUM> may provide a shift in a stabilization time to the output signal after a signal is driven from the second conductive plate <NUM> (B) to the first conductive plate <NUM> (A).

Referring now to <FIG>, an exemplary graph of current versus time is shown. The graph shows a first curve <NUM> and a second curve <NUM>. The first curve <NUM> is associated with a baseline signal (e.g., an unmodified signal) before activation of the transfer rate modification material <NUM>. The second curve <NUM> is associated with a modified signal after activation of the transfer rate modification material <NUM>. For example, this modification may result in a modified output signal from the first conductive plate <NUM> (A) to the second conductive plate <NUM> (B).

Referring now to <FIG>, an example of at least one memristor <NUM> is depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor <NUM> of <FIG>, except that the memristor <NUM> of <FIG> may include at least one permanent modification material <NUM>.

The permanent modification material <NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>. At least a portion of the permanent modification material <NUM> may abut the memristor material <NUM>. The permanent modification material <NUM> may provide a permanent signal modification (e.g., a permanent uniform signal modification) to the output signal after a signal is driven from the second conductive plate <NUM> (B) to the first conductive plate <NUM> (A). For example, this modification may result in a modified output signal from the first conductive plate <NUM> (A) to the second conductive plate <NUM> (B). Each subsequent activation (e.g., by driving a signal from the second conductive plate <NUM> (B) to the first conductive plate <NUM> (A)) of the permanent modification material <NUM> may compound modification effects.

Referring now to <FIG>, an exemplary graph of current versus time is shown. The graph shows a first curve <NUM> and a second curve <NUM>. The first curve <NUM> is associated with a baseline signal (e.g., an unmodified signal) before activation of the permanent modification material <NUM>. The second curve <NUM> is associated with a modified signal after activation of the permanent modification material <NUM>.

Referring now to <FIG>, an example of at least one memristor <NUM> is depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor <NUM> of <FIG>, except that the at least one permanent modification material <NUM> does not fully extend along the first plate <NUM> (A). For example, the memristor material <NUM> may abut a first surface area of the first conductive plate <NUM> (A). The memristor material <NUM> may abut a second surface area of the second conductive plate <NUM> (B). The first surface area and the second surface area may be different. The permanent signal modification may be a permanent asymmetric signal modification.

Referring now to <FIG>, an exemplary graph of current versus time is shown. The graph shows a first curve <NUM>, a second curve <NUM>, and a reduction slope <NUM>. The first curve <NUM> is associated with a baseline signal (e.g., an unmodified signal) before activation of the permanent modification material <NUM>. The second curve <NUM> is associated with a modified signal after activation of the permanent modification material <NUM>.

Referring now to <FIG>, an example of at least one memristor <NUM> according to the inventive concepts disclosed herein is depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor of <FIG>, except that the memristor <NUM> may be a notch filter.

Referring now to <FIG>, an example of at least one device 102A is depicted. The device 102A may be implemented similarly and function similarly to the memristor <NUM> of <FIG>, except that the device 102A may further include at least one dielectric material <NUM>, a third conductive plate <NUM>, and a third terminal <NUM>.

The device 102A may include the first conductive plate <NUM>, the second conductive plate <NUM>, the memristor material <NUM>, a third conductive plate <NUM>, a dielectric material <NUM>, a first terminal <NUM> electrically coupled to the first conductive plate <NUM>, a second terminal <NUM> electrically coupled to the second conductive plate <NUM>, and a third terminal <NUM> electrically coupled to the third conductive plate <NUM>. The dielectric material <NUM> may be positioned between the second conductive plate <NUM> and the third conductive plate <NUM>. The device 102A may have memristor functionality and capacitor functionality. The device <NUM> may be a bandpass filter, which for example, may be combined RC time constant.

Referring now to <FIG>, examples not forming part of the invention of at least one memristor <NUM> are depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor of <FIG>, except that in <FIG>: the memristor material <NUM> may abut a first surface area of the first conductive plate <NUM> (A); the memristor material <NUM> may abut a second surface area of the second conductive plate <NUM> (B); and the first surface area and the second surface area may be different (e.g., the first surface area may be less the second surface area as shown in <FIG>). The memristor of <FIG> may provide an asymmetric signal response. For example, the response can be modified to create greater oxygen vacancy density on the first conductive plate <NUM> (A) and lower density on the second conductive plate <NUM> (B). For example, such asymmetric application can be tailored by modification of a location and an amount of surface area covered by the blocking material <NUM> (as shown in <FIG>).

The asymmetric response of the memristor <NUM> of <FIG> can be used for: phase shifting an input signal (e.g., a digital clock phase shift); filtering by using only resistive elements; control system feedback; integrated analog compensation for undesired hysteresis effects (e.g., a lag in a temperature sensor reading versus actual instantaneous temperature) that can reduce or eliminate a need to compensate for such effects through software.

As shown in <FIG>, opposing faces of the first and second conductive plates <NUM> may have different surface areas.

As shown in <FIG>, the memristor <NUM> may further include a blocking material <NUM>. The blocking material <NUM> may be positioned between the first conductive plate <NUM> and the second conductive plate <NUM>. The blocking material <NUM> may abut the memristor material <NUM> and one of the first conductive plate <NUM> or the second conductive plate <NUM>.

Referring now to <FIG>, an exemplary graph of current (I) versus voltage (V) is shown. The graph shows a first I-V curve <NUM> and a second I-V curve <NUM>. The first I-V curve <NUM> is associated with a baseline signal (e.g., an unmodified signal) of a hypothetical memristor <NUM> with a first surface area of the first conductive plate <NUM> equal to the second surface area of the second conductive plate <NUM>. The second I-V curve <NUM> may be an I-V curve for the output signal of the memristor <NUM> of <FIG>.

Referring now to <FIG>, at least one memristor <NUM> is depicted. The memristor <NUM> may be implemented similarly and function similarly to the memristor of <FIG>, except that in <FIG>: the memristor <NUM> includes a permanent modification material <NUM> and a transfer rate modification material <NUM>; the permanent modification material <NUM> may be positioned between the first conductive plate <NUM> (A) and the second conductive plate <NUM> (B); the transfer rate modification material <NUM> may be positioned between the first conductive plate <NUM> (A) and the second conductive plate <NUM> (B); the permanent modification material <NUM> and the transfer rate modification material <NUM> may be in parallel electrically; at least a portion of the permanent modification material <NUM> may abut the memristor material <NUM>; at least a portion of the transfer rate modification material <NUM> may abut the memristor material <NUM>; a combination of the permanent modification material <NUM> and the transfer modification material <NUM> may provide a modification to the output signal after a signal is driven from the second conductive plate <NUM> (B) to the first conductive plate <NUM> (A).

Referring now to <FIG>, an exemplary graph of current (I) versus voltage (V) is shown. The graph shows a first I-V curve <NUM> and a second I-V curve <NUM>. The first I-V curve <NUM> is associated with a baseline signal (e.g., an unmodified signal) of a memristor <NUM> as shown in <FIG>. The second I-V curve <NUM> may be an I-V curve for the output signal of the memristor <NUM> of <FIG>.

The system <NUM> may include a memristor network <NUM> having any combination of type and/or number of at least two memristors <NUM>, such as shown in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and/or <NUM>.

Referring now to <FIG>, an example of a method <NUM> may include one or more of the following steps. Additionally, for example, some examples may include performing one more instances of the method <NUM> iteratively, concurrently, and/or sequentially. Additionally, for example, at least some of the steps of the method <NUM> may be performed in parallel and/or concurrently. Additionally, At least some of the steps of the method <NUM> may be performed non-sequentially. Additionally, at least some of the steps of the method <NUM> may be performed in sub-steps of providing various components. The method <NUM> may be performed by a semiconductor fab tool(s).

A step <NUM> may include providing a first conductive plate configured to receive an input signal.

A step <NUM> may include providing a second conductive plate configured to output an output signal.

A step <NUM> may include providing a first memristor material positioned between the first conductive plate and the second conductive plate.

A step <NUM> may include providing a second memristor material positioned between the first conductive plate and the second conductive plate, the first memristor material and the second memristor material being in parallel electrically, the first memristor material being different from the second memristor material.

Referring now to <FIG>, an example of a method <NUM> not forming part of the invention may include one or more of the following steps. Additionally, for example, some examples may include performing one more instances of the method <NUM> iteratively, concurrently, and/or sequentially. Additionally, for example, at least some of the steps of the method <NUM> may be performed in parallel and/or concurrently. Additionally, in some examples, at least some of the steps of the method <NUM> may be performed non-sequentially. Additionally, in some examples, at least some of the steps of the method <NUM> may be performed in sub-steps of providing various components. The method <NUM> may be performed by a semiconductor fab tool(s).

A step <NUM> may include providing a first conductive plate configured at least to receive an input signal.

A step <NUM> may include providing a second conductive plate configured at least to output an output signal.

A step <NUM> may include providing a memristor material positioned between the first conductive plate and the second conductive plate.

Referring now to <FIG>, further exemplary embodiments of the system <NUM> according to the inventive concepts disclosed herein are depicted. For example, the at least one memristor <NUM> may be at least one multi-lead memristor 102B. The multi-lead memristor 102B may include any or all of the elements and/or any or all of the arrangement of the elements described with respect to the memristor <NUM>, as disclosed throughout.

Referring now to <FIG>, an exemplary embodiment of the system <NUM> according to the inventive concepts disclosed herein is depicted. The system <NUM> may include at least one (e.g., two (as shown) or more) multi-lead memristor 102B communicatively coupled to at least one controller <NUM>. In some embodiments, multiple multi-lead memristors 102B may be part of a memristor network <NUM>, as described above.

The at least one controller <NUM> may function similarly to the processor <NUM>. The at least one controller <NUM> may be configured to perform (e.g., collectively perform if more than one controller) any or all of the operations disclosed throughout. The controller <NUM> may be configured to run various software and/or firmware applications and/or computer code stored (e.g., maintained) in a non-transitory computer-readable medium and configured to execute various instructions or operations.

The controller <NUM> is configured to configure (e.g., set) each multi-lead memristor 102B. For example, the controller is configured to set oxygen vacancies of the multi-lead memristor 102B, such as more fully described with respect to <FIG> below. The controller <NUM> is configured to adjust an order of circuit activation within each multi-lead memristor 102B, for example, to alter an output response of each multi-lead memristor 102B according to a prescribed input application. The controller <NUM> controls which lead (e.g., <NUM>) is driving oxygen vacancies in each multi-lead memristor 102B, thus allowing each multi-lead memristor 102B to be pre-set prior to subsequent readings; this allows each multi-lead memristor 102B to be reconfigured or to have multiple baseline configuration states related to an initial activation scheme.

For example, each multi-lead memristor 102B may function as at least one of a predefined or reconfigurable logic structure. In some embodiments, each multi-lead memristor 102B may function as a trimmer capacitor (e.g., a custom low stack trimmer capacitor). In some embodiments, each multi-lead memristor 102B may be configured to optimize and/or modify at least one analog circuit. In some embodiments, each multi-lead memristor 102B may be configured to allow trimming adjustments on electrical signals that use a resistive component. Some embodiments may allow for a size reduction when applied with thin film vapor deposition technology. Some embodiments may allow for a significant reduction in quantity of supporting electrical discrete parts. Some embodiments may eliminate and/or consolidate discrete components.

Referring now to <FIG>, an exemplary embodiment of a multi-lead memristor 102B according to the inventive concepts disclosed herein is depicted.

The multi-lead memristor 102B may include at least three (e.g., three, as shown in <FIG>) leads <NUM> (e.g., terminals <NUM>), at least two (e.g., two, as shown in <FIG>) memristor materials <NUM> with each memristor material <NUM> including oxygen vacancies <NUM>.

The multi-lead memristor 102B may include a first lead <NUM>, a second lead <NUM>, and third lead <NUM>, wherein the second lead <NUM> is positioned between the first lead <NUM> and the third lead <NUM>. The multi-lead memristor 102B may include at least one first memristor material <NUM> positioned between the first lead <NUM> and the second lead <NUM>. The multi-lead memristor 102B may include at least one second memristor material <NUM> positioned between the second lead <NUM> and the third lead <NUM>. For example, the at least one first memristor material <NUM> may be a first memristor material <NUM>, the at least one second memristor material <NUM> may be a second memristor material <NUM>, and the first memristor material <NUM> may be a same or different material from the second memristor material <NUM>.

Referring now to <FIG>, an exemplary embodiment of a multi-lead memristor 102B according to the inventive concepts disclosed herein is depicted. The multi-lead memristor 102B of <FIG> may include elements similar to and function similarly to the multi-lead memristor 102B of <FIG>, except that the multi-lead memristor 102B of <FIG> may include more than three (e.g., four, five,. , ten, etc.) leads <NUM> and more than two (e.g., three, four,. , nine, etc.) memristor materials <NUM>.

Referring now to <FIG>, an exemplary embodiment of the controller <NUM> exemplarily setting oxygen vacancies <NUM> of a multi-lead memristor 102B according to the inventive concepts disclosed herein is depicted.

As shown in <FIG>, the controller <NUM> is configured to: use a direct current (DC) field applied to the first lead <NUM> and the second lead <NUM> to set oxygen vacancies <NUM> of the at least one first memristor material <NUM> toward (e.g., fully toward) the second lead <NUM>. As shown in <FIG>, the controller <NUM> is configured to: use a DC field applied to the second lead <NUM> and the third lead <NUM> to set oxygen vacancies <NUM> of the at least one second memristor material <NUM> toward (e.g., fully toward) the third lead <NUM>. The oxygen vacancies <NUM> of the at least one first memristor material <NUM> may be in phase with the oxygen vacancies <NUM> of the at least one second memristor material <NUM>. As shown in <FIG>, the multi-lead memristor 102B alternating current (AC) response is similar to a memristor <NUM> having a single memristor material <NUM> as because the oxygen vacancies <NUM> are in phase.

Referring now to <FIG>, exemplary embodiments of the controller <NUM> exemplarily setting oxygen vacancies <NUM> of a multi-lead memristor 102B according to the inventive concepts disclosed herein are depicted.

In one embodiment, as shown in <FIG>, the controller <NUM> is configured to: use a direct current (DC) field applied to the first lead <NUM> and the second lead <NUM> to set oxygen vacancies <NUM> of the at least one first memristor material <NUM> toward (e.g., fully toward) the first lead <NUM>. As shown in <FIG>, the controller <NUM> is configured to: use a DC field applied to the second lead <NUM> and the third lead <NUM> to set oxygen vacancies <NUM> of the at least one second memristor material <NUM> toward (e.g., fully toward) the third lead <NUM>. The oxygen vacancies <NUM> of the at least one first memristor material <NUM> may be out of phase with the oxygen vacancies <NUM> of the at least one second memristor material <NUM>. As shown in <FIG>, because the oxygen vacancies <NUM> are out of phase with each other, the low voltage IV curve may either show an open or high resistance response depending on the circuit and memristor 102B construction. With a higher voltage alternating side, oxygen vacancies <NUM> may be brought back into phase in an AC or DC field.

In another embodiment, as shown in <FIG>, the controller <NUM> is configured to: use a direct current (DC) field applied to the first lead <NUM> and the second lead <NUM> to set oxygen vacancies <NUM> of the at least one first memristor material <NUM> toward (e.g., fully toward) the second lead <NUM>. As shown in <FIG>, the controller <NUM> is configured to: use a DC field applied to the second lead <NUM> and the third lead <NUM> to set oxygen vacancies <NUM> of the at least one second memristor material <NUM> toward (e.g., fully toward) the second lead <NUM>. The oxygen vacancies <NUM> of the at least one first memristor material <NUM> may be out of phase with the oxygen vacancies <NUM> of the at least one second memristor material <NUM>. As shown in <FIG>, because the oxygen vacancies <NUM> are out of phase with each other, the low voltage IV curve may either show an open or high resistance response depending on the circuit and memristor 102B construction. With a higher voltage alternating side, oxygen vacancies <NUM> may be brought back into phase in an AC or DC field.

As shown in <FIG>, the controller <NUM> is configured to: use a direct current (DC) field applied to the first lead <NUM> and the second lead <NUM> to set oxygen vacancies <NUM> of the at least one first memristor material <NUM> fully toward one of the first lead <NUM> or the second lead <NUM>. As shown in <FIG>, the controller <NUM> is configured to: use a DC field applied to the second lead <NUM> and the third lead <NUM> to set oxygen vacancies <NUM> of the at least one second memristor material <NUM> in between (a) fully toward the second lead <NUM> and (b) fully toward the third lead <NUM>. The oxygen vacancies <NUM> of the at least one first memristor material <NUM> may be out of phase with the oxygen vacancies <NUM> of the at least one second memristor material <NUM>. As shown in <FIG>, because the oxygen vacancies <NUM> are out of phase with each other, the low voltage IV curve may look like memristor <NUM> with a smaller memristance response than either the first memristor material <NUM> or the second memristor material <NUM> taken alone. This type of multi-lead memristor 106B setting may be analogous to starting the multi-lead memristor 106B in a condition intermediate to a starting response and ending response of the high voltage response shown in <FIG>, where the IV curve spirals out with AC cycles as oxygen vacancies synchronize phase.

Referring now to <FIG>, an exemplary embodiment of a method <NUM> according to the inventive concepts disclosed herein may include one or more of the following steps. Additionally, for example, some embodiments may include performing one more instances of the method <NUM> iteratively, concurrently, and/or sequentially. Additionally, for example, at least some of the steps of the method <NUM> may be performed in parallel and/or concurrently. Additionally, in some embodiments, at least some of the steps of the method <NUM> may be performed non-sequentially. Additionally, in some embodiments, at least some of the steps of the method <NUM> may be performed in sub-steps of providing various components.

A step <NUM> may include setting, by a controller, oxygen vacancies of a multi-lead memristor, the multi-lead memristor comprising: a first lead; a second lead; a third lead, the second lead positioned between the first lead and the third lead; at least one first memristor material positioned between the first lead and the second lead; and at least one second memristor material positioned between the second lead and the third lead.

As will be appreciated from the above, embodiments of the inventive concepts disclosed herein may be directed to a method and a system including at least one device (e.g., at least one memristor) having at least one memristor material.

As used throughout and as would be appreciated by those skilled in the art, "at least one non-transitory computer-readable medium" may refer to as at least one non-transitory computer-readable medium (e.g., at least one memory device (e.g., a non-volatile memory device); e.g., at least one memristor; e.g., at least one computer-readable medium implemented as hardware; e.g., at least one non-transitory processor-readable medium, at least one memory (e.g., at least one nonvolatile memory, at least one volatile memory, or a combination thereof; e.g., at least one random-access memory, at least one flash memory, at least one read-only memory (ROM) (e.g., at least one electrically erasable programmable read-only memory (EEPROM)), at least one on-processor memory (e.g., at least one on-processor cache, at least one on-processor buffer, at least one on-processor flash memory, at least one on-processor EEPROM, or a combination thereof), or a combination thereof), at least one storage device (e.g., at least one hard-disk drive, at least one tape drive, at least one solid-state drive, at least one flash drive, at least one readable and/or writable disk of at least one optical drive configured to read from and/or write to the at least one readable and/or writable disk, or a combination thereof), or a combination thereof).

Claim 1:
A system, comprising:
a multi-lead memristor, comprising:
a first lead (<NUM>);
a second lead (<NUM>);
a third lead (<NUM>), the second lead positioned between the first lead (<NUM>) and the third lead;
at least one first memristor material (<NUM>-<NUM>) positioned between the first lead and the second lead; and
at least one second memristor material (<NUM>-<NUM>) positioned between the second lead and the third lead, and further comprising a controller (<NUM>), wherein the controller is further configured to use a direct current field applied to the first lead and the second lead to set oxygen vacancies (<NUM>) of the at least one first memristor material toward the second lead; and use a direct current field applied to the second lead and the third lead to set oxygen vacancies of the at least one second memristor material toward the third lead, and characterized in that the oxygen vacancies of the at least one first memristor material are controlled to be in phase with the oxygen vacancies of the at least one second memristor material.