Patent Description:
In wireless frequency division duplex (FDD) systems the received and transmitted radio frequency (RF) signals are located at different radio frequencies. The received RF signal is downconverted around DC frequency, i.e. zero frequency, with a local oscillator (LO) signal into a baseband signal at the receiver. At the downconverter output the downconverted transmitted signal is at a duplex distance, i.e. the distance between the received signal and transmitted signal, while the downconverter im2 product. i.e. the second order nonlinearity, is centered around zero frequency. The second order nonlinearity is mostly due to mismatch between switches in the mixer of analogue and digital downconverters. The second order nonlinearity limits the signal-to-noise and distortion ratio (SNDR) of the received signal.

In conventional downconverters the second-order input intercept point (IIP2) calibration is performed by tuning the DC bias voltage of the LO signals independently for each of the switches of the mixer. By tuning the DC level of the LO signals, the mismatch between the switches of the mixer can be compensated. In order to tune the DC level of the LO signals, DC decoupling between mixer gate terminals and LO signals is required.

In a conventional analog mixer of a downconverter the gate terminals of the switches are decoupled from the LO signals with the use of capacitors and the DC bias voltages are connected to the gate terminals of the switches via large resistors. The DC bias voltages can be used for compensating the mismatch of the switches of the mixer. For example, if the threshold voltage is 20mV higher on a switch a first DC bias voltage can be tuned 20mV higher than a second DC bias voltage to compensate the threshold voltage mismatch. The threshold voltage is the voltage between the gate and the source terminal of the switch. Typically, the DC voltage of the source terminal (and drain terminal) is set by the analog baseband filter at the output of the mixer which is typically half the supply voltage, i.e. VDD/<NUM>, for all mixer outputs.

Further, <CIT> refers to a receiver including a direct digital frequency synthesizer (DDFS) and first and second mixers. The DDFS has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS may be implemented using first and second memories storing portions of a sinusoidal waveform and extra memories supporting the phase offset.

Further, the document<NPL>, refers to a RF Front-End of Direct Conversion Receiver RFIC for CDMA-<NUM>.

Further, <CIT> refers to a radio frequency receiver on an integrated circuit (RFIC) including an oscillator circuit, which generates a radio frequency (RF) oscillatory signal having a predetermined frequency that is outside of an intermediate frequency passband of the RFIC. An amplitude modulator modulates the RF oscillatory signal to produce an amplitude modulated signal, which is applied to a mixer that downconverts the amplitude modulated signal. A calibration circuit receives the downconverted signal, including second order modulation (IM2) products, and, responsive to the IM2 products, generates a bias signal that is applied to the mixer to reduce the IM2 products.

The above and further objectives are solved by the subject matter of the independent claims. Further advantageous embodiments of the invention can be found in the dependent claims.

According to a first aspect of the invention, the above mentioned and other objectives are achieved with a digital frequency synthesis circuit according to claim <NUM>.

An advantage of the digital frequency synthesis circuit according to the first aspect is that all desired LO frequencies can be generated from a single clock frequency (CLK). Also, the LO signal waveform can be freely chosen. Moreover, the calibration can be done on the digital side. Hence, no additional components such as decoupling capacitors and resistors are needed on the analog side in the mixer of the downconverter. This implies more compact layout (smaller chip size) in the mixer and cost saving when producing the mixer. Further, better matching between cells of the mixer is achieved which results in improved SNDR and lower current consumption due to lower parasitic effects in the mixer.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the converter block further is configured to
reduce the amplitude of the LO signal from digital full-scale.

An advantage with this implementation form is that the LO signal waveform is maintained after adding the calibration code. If the LO signal waveform clips the harmonic content of the LO is changed thus degrading the harmonic rejection of the mixer.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the converter block further is configured to
convert the phase slope signal to the LO signal using a square wave signal or a sine wave signal.

An advantage with this implementation form is that by using a square wave signal higher conversion gain is possible which means that the signal at the mixer output is higher. By using a sine wave signal the LO signal does not mix from its harmonics since the sinewave does not have harmonics.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the adder block further is configured to
add a calibration code value to the LO signal so that a maximum value of the LO signal including the calibration code value is less than digital full-scale.

An advantage with this implementation form is that the LO signal waveform is maintained after adding the calibration code.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the adder block further is configured to
add a calibration code value to the LO signal so that a minimum value of the LO signal including the calibration code value is greater than zero.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the calibration code value is a constant value.

An advantage with this implementation form is that the calibration can be done at factory and correct calibration values for the mixer application can be selected from predefined tables. This means that the mixer is already calibrated at delivery since no calibration is needed at start-up of the mixer/downconverter.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the constant value is predefined and tuned for a mixer of the downconverter.

An advantage with this implementation form is that no calibration is needed at start-up of the mixer/downconverter.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the calibration code value is tuned for removing second order nonlinearities of the mixer.

An advantage with this implementation form is that the second order nonlinearities of the mixer are removed or mitigated.

An advantage of the mixer according to the second aspect is that the calibration can be done on the digital side.

In an implementation form of a mixer according to the second aspect, the mixer further lacking decoupling capacitors and bias resistors. This implies more compact layout (smaller chip size) in the mixer and cost saving when producing the mixer. Further, better matching between cells of the mixer is achieved which results in improved SNDR and lower current consumption due to lower parasitic effects in the mixer.

According to a third aspect (an embodiment) of the invention, the above mentioned and other objectives are achieved with a downconverter for downconverting a radio frequency signal to a baseband signal, the downconverter comprising.

According to a fourth aspect of the invention, the above mentioned and other objectives are achieved with a method according to claim <NUM>.

The method according to the fourth aspect can be extended into implementation forms corresponding to the implementation forms of the digital frequency synthesis circuit according to the first aspect. Hence, an implementation form of the method comprises the feature(s) of the corresponding implementation form of the digital frequency synthesis circuit.

The advantages of the methods according to the fourth aspect are the same as those for the corresponding implementation forms of the digital frequency synthesis circuit according to the first aspect.

As aforementioned the IIP2 calibration of conventional digital downconverters is performed by changing the DC bias voltages of the calibration voltages for the I-path and Q-path, respectively. However, according to the invention the IIP2 calibration is performed in the digital side contrary to conventional solutions. By changing the DC bias voltage of the digital LO signal, any mismatch of the switches of the mixer can be compensated hence moving the IIP2 calibration functionality from the analog side to the digital side. Furthermore, according to aspects of the invention instead of generating full-scale LO signal in the Direct Digital Frequency Synthesis (DDFS), the LO signal amplitude is lowered, i.e. backed-off from digital full-scale, so as to leaving room for DC level adjustments. The offset value, i.e. the IIP2 calibration value, can then be added in the DDFS to the digital LO signal to compensate the switching mismatch in the mixer of the downconverter.

<FIG> shows a block diagram of a DDFS <NUM> according to an embodiment of the invention. The DDFS <NUM> includes both an I-path and a Q-path, and further comprises a phase accumulator block <NUM> configured to obtain a register output value and generate a phase slope signal by adding a frequency control word (FCW) to the register output value. The DDFS further comprises a converter block <NUM> configured to convert the phase slope signal to a LO signal and an adder block <NUM> configured to add a calibration code value (CCV) IIP2CAL_I, IIP2CAL_Q to the LO signal. The DDFS <NUM> further comprises a differential block <NUM> configured to generate a phase shifted LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q by phase shifting the LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q.

<FIG> shows a flow chart of a corresponding method <NUM> for generating a LO signal for a digital frequency synthesis circuit <NUM>, such as the one shown in <FIG>. The method <NUM> comprises obtaining <NUM> a register output value and generating <NUM> a phase slope signal by adding a FCW to the register output value. The method <NUM> further comprises converting <NUM> the phase slope signal to a LO signal and adding <NUM> a calibration code value IIP2CAL_I, IIP2CAL_Q to the LO signal. The method <NUM> further comprises generating <NUM> a phase shifted LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q by phase shifting the LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q.

<FIG> shows a digital downconverter <NUM> comprising a DDFS <NUM> according to an embodiment of the invention. The general function of the downconverter <NUM> and its mixer <NUM> is to convert a high frequency RF input signal, e.g. around <NUM> to zero frequency, to obtain a baseband signal representation of the RF signal. The mixer <NUM> therefore multiplies the <NUM> input signal with the <NUM> LO signal which results in a zero-frequency output signal.

The DDFS <NUM> comprises as aforementioned a phase accumulator block <NUM>, a phase-to-amplitude converter block <NUM>, an adder block <NUM>, and a single-ended-to-differential block <NUM> which are described more in detail in the following disclosure. The corresponding signal waveforms at the DDFS <NUM> for different processing steps are illustrated in <FIG>.

Furthermore, the DDFS <NUM> in <FIG> is connected to a mixer <NUM> of a downconverter <NUM>. Hence, the differential block <NUM> is configured to provide the phase shifted LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q to the mixer <NUM>. In embodiments, the mixer <NUM> includes an I-path and a Q-path. The mixer <NUM> also comprises a first input(s) <NUM> configured to receive a radio frequency signal RF_i, RF_q for downconversion, and to provide the RF signal RF_i, RF_q, respectively, to a plurality of switches M1[<NUM>] - M4[<NUM>]. The mixer <NUM> further comprises a second input(s) <NUM> configured to receive a phase shifted LO signal including a calibration code value, i.e. LOIP, LOIN, LOQP, LOON from the DDFS <NUM> as previously mentioned. The second input <NUM> is further configured to provide the phase shifted LO signal including the calibration code value LOIP, LOIN, LOQP, LOON to the plurality of switches M1[<NUM>] - M4[<NUM>]. The mixer <NUM> further comprises output(s) <NUM> configured to output a baseband signal comprising the radio frequency signal RF_i, RF_q multiplied with the phase shifted LO signal including the calibration code value LOIP, LOIN, LOQP, LOQN.

In the digital downconverter architecture in <FIG> the mixer switches are split into many cells 250n. First mixer cell includes switches M1[<NUM>] - M4[<NUM>], second mixer cell includes switches M1[<NUM>] - M4[<NUM>], etc. On total the mixer <NUM> has n number of cells. The number n should be chosen high enough to meet SNDR requirements and may also depend on weighing method selected, e.g. binary weighing or equal weighing. The cells can be binary or some other way weighted. Each cell is driven with its own digital LO signal, i.e. LOIP[n:<NUM>], LOIN[n:<NUM>], etc. In the digital mixer there is only switch transistors that can be arranged closely together to achieve best possible matching. Hence no capacitors or resistances as in conventional mixers are needed in a digital mixer <NUM>.

To provide deep understanding of embodiments of the invention, the different blocks of the DDFS <NUM> will be described more in detail in the following disclosure.

The DDFS <NUM> comprises a phase accumulator block <NUM> which is driven by FCWs and constant clock (CLK) signals. The phase accumulator block <NUM> is configured to add a FCW to an output value of a register for each clock sample of the CLK. After reset said value is zero and then increases at the slope given by the FCW. The FCW determines the phase slope and thus the DDFS frequency which is equal to the LO frequency, i.e. "PA_out" (phase accumulator output) in <FIG>. PA_out is the value held at the register output plus the FCW for each clock sample.

The phase accumulator block <NUM> therefore comprises a register block <NUM>, an adder block <NUM> and a feedback line <NUM> from the register block <NUM> output to the adder block <NUM> as shown in <FIG>. The register block <NUM> changes a register input value to a register output value at each rise of the CLK signal, i.e. once per clock period. This value is held at the output until the CLK signal rises again. For example, if the FCW value is <NUM>, starting from reset:.

The PA_out is thereafter outputted to the phase-to-amplitude converter block <NUM>.

The DDFS <NUM> comprises a phase-to-amplitude converter block <NUM> which is coupled to the phase accumulator block <NUM>. The phase-to-amplitude converter block <NUM> converts the phase slope signal received from the phase accumulator block <NUM> to a LO signal, i.e. the "PAC_out" (phase to amplitude converter output) in <FIG>.

In embodiments the converter block <NUM> is configured to convert the phase slope signal to the LO signal using a square wave function or a sine wave function. This means that the LO signal or PAC_out in <FIG> is the square wave signal or sinewave signal waveform output for each CLK hence not a continuous signal but a sampled signal. The PAC_out is outputted to the adder block <NUM>.

In embodiments the converter block <NUM> is configured to reduce the amplitude of the LO signal from digital full-scale. Hence, the signal from the phase-to-amplitude block <NUM> is backed off from the full-scale so as to make room for calibration offset value.

The DDFS <NUM> comprises an adder block <NUM> which is coupled to phase-to-amplitude converter block <NUM>. The adder block <NUM> is configured to receive the LO signal (PAC_out) from the phase-to-amplitude converter block <NUM> and add a calibration code value, i.e. IIP2CAL_I and IIP2CAL_Q, respectively, depending on whether the path is I-path or Q-path, to the LO signal output from the phase-to-amplitude converter block <NUM>. The calibration code value is received by the adder block <NUM>, e.g. from a memory of the DDFS <NUM>.

In embodiments the calibration value is a constant value in the respect that it does not change over time. More specifically, the constant value is predefined and tuned for a mixer <NUM> of the downconverter <NUM>. This implies that the calibration is performed in factory at production of the DDFS <NUM>. Predefined tables can be provided which indicates different calibration values for different mixer applications. Hence, a suitable calibration value can be pick at production. The calibration value can be stored in a memory (not shown) of the downconverter <NUM> and fetched from the memory when needed.

In embodiments, the calibration code value is tuned for removing second order nonlinearities of the mixer <NUM>.

In further embodiments, the calibration code value is different for different receivers but constant for one downconverter/receiver. The nonidealities during the manufacturing process causes mismatch in different properties, such as threshold voltage, of the mixer switches. Further, the non-symmetrical layout design by the designer can cause mismatch. However, these effects are not changed over time but stays constant for one physical instance of the mixer. Therefore, the calibration values can be constant and fixed for a single mixer <NUM>. Moreover, the calibrated code effectively creates a mismatch to the LO port to counter the mismatch in the mixer switch itself. Therefore, the output is perfectly in balance and no second order nonlinearity is created.

In further embodiments, the adder block <NUM> is configured to add a calibration code value to the LO signal so that a maximum value of the LO signal including the calibration code value is less than digital full-scale.

In further embodiments, the adder block <NUM> is also configured to add a calibration code value to the LO signal so that a minimum value of the LO signal including the calibration code value is greater than zero.

The LO signal including the calibration code must be less than the full-scale in order to maintain the LO waveform. Also, if the LO signal is higher than the maximum value and lower than the minimum value, hence clips at both ends, even the calibration functionality is lost.

The DDFS <NUM> comprises a single-ended-to-differential block <NUM> coupled to the adder block <NUM>. The single-ended-to-differential block <NUM> is configured to receive the LO signal including the calibration code value from the adder block <NUM> and add a <NUM>-degree phase shift to the output signal added with the calibration signal. The <NUM>-degree phase shift signal is required to create differential downconverter output signals. The differential outputs are required to suppress the second order nonlinearity. With the LO signal including the optimal calibration code and non-ideal mixer the differential outputs (IP, IN) are in balance and therefore have no differential second order nonlinearity component. Without the differential output there is no way of suppressing the second order nonlinearity.

The output of the differential block <NUM> are the digital LO signals LOIP[n:<NUM>], LOIN[n:<NUM>], LOQP[n:<NUM>], LOQN[n:<NUM>], used for IIP2 calibration of the switches in the digital mixer <NUM> of the downconverter <NUM>. Hence, the output of the single-ended-to-differential block <NUM> is <NUM>-degree phase shift of the PAC_out + constant calibration code value signal (shown in <FIG>) which is equal to the digital LO signal used for IIP2 calibration of the switches in the digital mixer of the downconverter.

It noted that for simplicity only the processing of the I-path according to the invention is illustrated in <FIG> and <FIG>. However, the processing of the Q-path is the same as for the I-path except for a <NUM>-degree phase shift on the PAC output. Typically, the calibration of the I-path and the Q-path is performed separately. Also, said calibration is usually not performed in parallel but in series. In zero inter frequency (IF) receivers the baseband signal can be downconverted around DC with the I (in-phase) and the Q (quadrature) signals. By using IQ signals the analog baseband (ABB) filter can be simple lowpass filter. The I- and Q-paths are added together in the digital domain (see <FIG>) to construct the complex signal, i.e. I+jQ.

Further, it is noted that each n signal of the LOIP [n: <NUM>] signals in <FIG> is a digital zero "<NUM>" or a digital one "<NUM>". When the sinewave signal is at maximum all n signals have value "<NUM>", and all n signals have values "<NUM>" when the sinewave is at minimum. At other time instances some of the n signals have the value "<NUM>" and others have the value "<NUM>" to effectively create the sinewave curve for mixing of RF signals with LO signals at the mixer <NUM>.

<FIG> shows a digital <NUM>-bit full-scale waveform calibration signal LOIP[n:<NUM>] without DC offset. The DC level in <FIG> is shown with dashed line which is exactly at the center value. It can be seen that there is no room for DC adjustment without clipping the signal. <FIG> shows the backed-off from full-scale waveform calibration signal with DC offset added as previously described. The DC level is again shown with dashed line which now is above the center value illustrated with the arrow. In the DDFS <NUM> there is a single-ended to differential buffer which drives the positive (M1[n:<NUM>]) switches with a stronger LO signal. This effect can be used for compensating the mismatch of switches in the mixer <NUM>.

<FIG> shows a downconverter according to an embodiment of the invention. A calibration signal is inserted into a low noise amplifier (LNA) of a radio frequency integrated circuit (RFIC). The LNA is typically the first block of the RFIC. The LNA amplifies the signal and adds as little noise as possible. The next block is the downconverter <NUM> including the LO signal which converts the amplified RF signal to baseband around zero frequency. The ABB filters the unwanted blocker signals including the transmitter (TX) signal and amplifies the signal to a correct level for the analog to digital (A/D) converter (ADC) which converts the filtered signal to the digital domain (DIGITAL) and applies further filtering and combines the I- and Q-paths to a complex IQ signal (I+jQ).

Moreover, it is recognized that IIP2 calibration needs test tones to mixer input that can generated with external generators or with own TX through loopback switch in the Front-end Module (FEM). After the test tones are added, the second order intermodulation product is minimized by optimizing the IIP2CAL calibration values. The calibration is done separately for the I-path and Q-path. The test tone frequencies are at duplex distance of LO frequency and 2xdf apart (<NUM> for example) which is illustrated in the left signal diagram in <FIG>. Power is the maximum transmit power at the LNA input. The second order intermodulation is at <NUM>*df which is illustrated in the right signal diagram in <FIG>.

<FIG> and <FIG> shows simulation results of the proposed IIP2 calibration scheme.

<FIG> shows the simulation results for IIP2 with different DC offset values added. The x-axis shows different IIP2 calibration values (IIP2CAL), and the y-axis shows the IIP2 value in dBm in <FIG>. This means that the higher value the better. In <FIG> the calibration value, i.e. IIP2CAL constant value, is swept from -<NUM> to <NUM>. It can be seen from <FIG> that by changing the value of the calibration signal IIP2CAL by <NUM> the IIP2 is improved by <NUM> dBm.

<FIG> shows simulation results for second and third order intermodulation and the gain. In <FIG> there is second and third order intermodulation products as well as gain as a function of the LO offset, i.e. the calibration value (IIP2CAL constant). The x-axis shows the LO offset values (IIP2CAL), i.e. calibration values, and the y-axis shows the intermodulation hence the lower value the better. As seen from <FIG> the second order intermodulation product is minimized and the third order intermodulation is kept quite constant. Furthermore, it is noted from <FIG> that the gain is not affected by IIP2 calibration.

The downconverter <NUM> and hence also the DDFS <NUM> and the mixer <NUM> according to embodiments of the invention can in non-limiting examples be implemented/comprised in a client device <NUM> and/or a network access node <NUM> of a wireless communication system <NUM>, such as 3GPP new radio (NR). <FIG> illustrates a wireless communication system <NUM> according to an embodiment of the invention. The wireless communication system <NUM> comprises a client device <NUM> and a network access node <NUM> configured to operate in the wireless communication system <NUM>. For simplicity, the wireless communication system <NUM> shown in <FIG> only comprises one client device <NUM> and one network access node <NUM>. However, the wireless communication system <NUM> may comprise any number of client devices <NUM> and any number of network access nodes <NUM> without deviating from the scope of the invention. The client device <NUM> and a network access node <NUM> can perform uplink and/or downlink communication.

The client device <NUM>, may be denoted as a user device, a User Equipment (UE), a mobile station, an internet of things (IoT) device, a sensor device, a wireless terminal and/or a mobile terminal, is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system. The UEs may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability. The UEs in this context may be, for example, portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile devices, enabled to communicate voice and/or data, via the radio access network, with another entity, such as another receiver or a server. The UE can be a Station (STA), which is any device that contains an IEEE <NUM>-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The UE may also be configured for communication in 3GPP related LTE and LTE-Advanced, in WiMAX and its evolution, and in fifth generation wireless technologies, such as New Radio.

The network access node <NUM> may also be denoted as a radio network access node, an access network access node, an access point, or a base station, e.g. a Radio Base Station (RBS), which in some networks may be referred to as transmitter, "gNB", "gNodeB", "eNB", "eNodeB", "NodeB" or "B node", depending on the technology and terminology used. The radio network access nodes may be of different classes such as e.g. macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size. The radio network access node can be a Station (STA), which is any device that contains an IEEE <NUM>-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The radio network access node may also be a base station corresponding to the fifth generation (<NUM>) wireless systems.

Claim 1:
A digital frequency synthesis circuit (<NUM>) for generating a <NUM>°-phase shifted local oscillator, LO, signal for a digital mixer (<NUM>) of a downconverter (<NUM>), wherein the digital frequency synthesis circuit (<NUM>) includes an I-path and a Q-path, and comprises:
• a phase accumulator block (<NUM>) configured to:
∘ obtain a register output value,
∘ generate a phase slope signal by adding a frequency control word, FCW, to the register output value;
• a converter block (<NUM>) configured to:
o convert the phase slope signal to a LO signal;
• an adder block (<NUM>) configured to:
o add a calibration code value (IIP2CAL_I, IIP2CAL_Q) to the LO signal, wherein the calibration code value (IIP2CAL_I, IIP2CAL_Q) is for second order input intercept point, IIP, calibration of the switches of the digital mixer (<NUM>); and
• a differential block (<NUM>) configured to:
∘ generate the <NUM>°-phase shifted LO signal, the <NUM>°-phase shifted LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q), by phase shifting the LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q), and
∘ provide the <NUM>°-phase shifted LO signal to the digital mixer (<NUM>).