Patent Description:
It is now more common for nuclear power plants to utilize one or more field-programmable gate arrays (FPGAs) in at least one of their various control circuits. In addition to including one or more FPGAs, such control circuits also include other devices/components such as, for example, sensors, input/outputs cards, analog-to digital converters and processors to monitor and/or control the operation of the nuclear power plant. In general, output signals generated by the sensors, which are indicative of a sensed or measured parameter, are input to input/output cards, which are connected to an FPGA, which in turn can be connected to a processor. For instances where an output signal generated by a sensor is an analog signal, an analog-to-digital converter is utilized to convert the analog signal to a corresponding digital signal. In various configurations, the analog-to-digital conversion can be performed by the input/output card, by an analog-to-digital converter connected to the input/output card, or by the FPGA.

In some nuclear power plant control circuits, several of these devices/components are packaged together in an electronic device such as, for example, the CompactRIO (cRIO) controller manufactured National Instruments. In applications where the electronic device provides only a monitoring function, a digital value output by the FPGA of the electronic device may be input to a computer system or other processing device that aggregates the outputs of multiple FPGAs. In applications where the electronic device functions as a controller, the electronic device may perform a control function based on the output signal of one or more of the sensors (or on other conditions).

In order to ensure that such control circuits are operating properly, the calibration of the control circuit can be verified. In particular, the calibration of the timing of the control circuit and the calibration of the analog voltages present within the control circuit can be verified. If the calibrations of either the timing or the analog voltages are not verified, the calibrations can be adjusted so that the control circuit is in proper calibration going forward. Known processes for verification and calibration are time consuming processes. For example, one known process includes verifying the timing of the control circuit and then individually injecting multiple different voltage levels to verify the analog voltages present within the control circuit Similar processes are currently utilized to verify calibrations of devices and/or systems.

Document <CIT>discloses a calibration system and a method as defined in the pre-characterizing portion of the independent system and method claims.

There is room for improvement in systems and methods of calibrating devices, circuits and/or systems.

The novel features of the aspects described herein are set forth with particularity in the appended claims. The aspects, however, both as to organization and methods of operation may be better understood by reference to the following description, taken in conjunction with the accompanying drawings.

It is to be understood that at least some of the figures and descriptions of the invention have been simplified to illustrate elements that are relevant for a clear understanding of the invention, while eliminating, for purposes of clarity, other elements that those of ordinary skill in the art will appreciate may also comprise a portion of the invention. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the invention, a description of such elements is not provided herein.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols and reference characters typically identify similar components throughout several views, unless context dictates otherwise. The illustrative aspects described in the detailed description, drawings and claims are not meant to be limiting. Other aspects may be utilized, and other changes may be made, without departing from the scope of the technology described herein.

Other examples, features, aspects, embodiments and advantages of the technology will become apparent to those skilled in the art from the following description, which is by way of illustration, one of the best modes contemplated for carrying out the technology.

It is further understood that any one or more of the teachings, expressions, aspects, embodiments, examples, etc. described herein may be combined with any one or more of the other teachings, expressions, aspects, embodiments, examples, etc. that are described herein. The following described teachings, expressions, aspects, embodiments, examples, etc. should therefore not be viewed in isolation relative to each other.

Before explaining the various aspects of the calibration system in detail, it should be noted that the various aspects disclosed herein are not limited in their application or use to the details of construction and arrangement of parts illustrated in the accompanying drawings and description. Rather, the disclosed aspects may be positioned or incorporated in other aspects, embodiments, variations and modifications thereof, and may be practiced or carried out in various ways. Accordingly, aspects of the calibration system disclosed herein are illustrative in nature and are not meant to limit the scope or application thereof. Furthermore, unless otherwise indicated, the terms and expressions employed herein have been chosen for the purpose of describing the aspects for the convenience of the reader and are not meant to limit the scope thereof. In addition, it should be understood that any one or more of the disclosed aspects, expressions of aspects, and/or examples thereof, can be combined with any one or more of the other disclosed aspects, expressions of aspects, and/or examples thereof, without limitation.

Also, in the following description, it is to be understood that terms such as inward, outward, upward, downward, above, top, below, floor, left, right, side, interior, exterior and the like are words of convenience and are not to be construed as limiting terms. Terminology used herein is not meant to be limiting insofar as devices described herein, or portions thereof, may be attached or utilized in other orientations. The various aspects will be described in more detail with reference to the drawings.

<FIG> illustrates a calibration system <NUM>, in accordance with at least one aspect of the present disclosure. The calibration system <NUM> will be described in the context of its use to calibrate a control circuit <NUM> of a nuclear power plant. However, it will be appreciated that the calibration system <NUM> can be utilized to calibrate any number of different devices (an FPGA, a computer, a programmable logic controller, an input/output circuit, etc.), circuits and/or systems. The calibration system <NUM> includes a waveform generator <NUM> and a controller <NUM>. The controller <NUM> includes an input/output circuit <NUM>, an analog-to-digital (A/D) converter <NUM> and an FPGA <NUM>. According to various aspects, the calibration system <NUM> may also include a processor <NUM> connected to the FPGA <NUM>.

The waveform generator <NUM> is configured to generate one or more waveforms. For example, according to various aspects, the waveform generator <NUM> may be configured to generate one or more waveforms such as triangular waves, sine waves, square waves, sawtooth waves, etc. of different amplitudes over a wide range of frequencies. An exemplary triangular wave generated by the waveform generator <NUM> is shown in <FIG>, where the triangular wave is a <NUM> Hx, <NUM>-<NUM> V triangular wave. An exemplary sine wave generated by the waveform generator <NUM> is shown in <FIG>. where the sine wave is a <NUM>, <NUM>-<NUM> V sine wave. Of course, different frequencies, amplitudes and/or waveforms other than those shown in <FIG> may be generated by the waveform generator <NUM>. As shown in <FIG>, the waveform generator <NUM> is connected to (in signal communication with) the control circuit <NUM>. More specifically, the waveform generator <NUM> is connected to (in signal communication with) the input/output circuit <NUM> of the controller <NUM>.

The input/output circuit <NUM> is configured to receive analog signals at its input terminals (not shown for purposes of clarity). For example, the input/output circuit <NUM> may receive analog signals from a sensor <NUM>. Although only one sensor <NUM> is shown in <FIG>, it will be appreciated that the input/output circuit <NUM> may receive analog signals from a plurality of sensors <NUM> such as, for example, flow sensors, position sensors, pressure sensors, temperature sensors, etc. According to various aspects, the input/output circuit <NUM> may include any number of input/output cards (analog I/O cards, digital I/O cards and/or mixed I/O cards) and may be configured to accommodate both analog and digital inputs/outputs. For example, according to various aspects, the input/output circuit <NUM> is further configured to output a control signal to an actuator <NUM>. Although only one actuator <NUM> is shown in <FIG>, it will be appreciated that the input/output circuit <NUM> may output control signals to a plurality of actuators <NUM> to control a valve, a motor, a pump, etc..

The A/D converter <NUM> is connected to (in signal communication with) the input/output circuit <NUM>, and is configured to convert the analog signals received from the input/output circuit <NUM> into corresponding digital signals or digital values which are representative of the analog signals. Although only one A/D converter <NUM> is shown in <FIG> for purposes of clarity, it will be appreciated that the controller <NUM> may include any number of A/D converters <NUM>. For example, according to various aspects, the controller <NUM> includes a separate A/D converter <NUM> for each analog input/output card in the input/output circuit <NUM>. According to various aspects, the A/D converter <NUM> forms a part of the input/output circuit <NUM>.

The FPGA <NUM> is connected to (in signal communication with) the A/D converter <NUM>, and is configured to process the digital signals and/or digital values received from the A/D converter <NUM>. According to various aspects, the A/D converter <NUM> forms a part of the FPGA <NUM>. In addition to performing signal processing, the FPGA <NUM> may also be utilized for control, filtering, timing and/or other logic functions. As shown in <FIG>, according to various aspects, the FPGA <NUM> also includes a processor <NUM> which is in signal communication with the FPGA <NUM>. The processor <NUM> may be utilized for communication, signal processing and/or executing algorithms or routines which are stored in a memory associated with the processor <NUM>. The processor <NUM> can execute one or more such algorithms or routines to implement and control the functionality of the FPGA <NUM>. According to various aspects, the processor <NUM> interprets the digital signals or digital values output by the A/D converter <NUM> and responsively causes the FPGA <NUM> to output one or more digital signals. Such signals may be control signals to control one or more components of the control circuit <NUM> and/or informational signals to provide information such as a characteristic sensed by an analog sensor <NUM>. According to various aspects, the FPGA <NUM>, or the combination of the FPGA <NUM> and the processor <NUM>, may be considered a processing circuit.

The processor <NUM> can be in signal communication with the processor <NUM>, and may be utilized, for example, to format information provided by the processor <NUM> (e.g., information associated with an analog sensor <NUM> connected to the input/output circuit <NUM>) so that the information can be displayed on a monitor (not shown) connected to the processor <NUM>.

In order to ensure that certain control circuits employed in nuclear power plants or other applications are operating properly, the calibration of the control circuit can be verified by a calibration algorithm or routine executed by the processor <NUM> of the FPGA <NUM>. With the calibration algorithm or routine, the processor <NUM> can verify the timing and voltage levels of the control circuit <NUM> based on a waveform generated by the waveform generator <NUM>. For example, the sampling rate of the analog signals received by the input/output circuit <NUM> can be utilized to verify the timing of the control circuit <NUM> and the voltage levels of the analog signals received by the input/output circuit <NUM> can be utilized to verify the voltage levels of the control circuit <NUM>. If the calibrations of either the timing or the analog voltages are not verified, the calibrations can be adjusted so that the control circuit <NUM> is in proper calibration going forward. For example, with respect to the timing of the control circuit <NUM>, loop times utilized by the FPGA <NUM> can be adjusted to bring the timing into proper calibration. According to other aspects, the calibration or routine can be executed by a processing circuit other than the FPGA <NUM> and the processor <NUM>.

According to various aspects, to calibrate the control circuit <NUM>, a periodic waveform generated by the waveform generator <NUM> is input to the input/output circuit <NUM>. The waveform may be input to a test terminal block (not shown) of the input/output circuit <NUM>. The processor <NUM> initiates the execution of the calibration algorithm or routine. The calibration algorithm or routine may be initiated automatically, such as in response to receiving the periodic waveform at a particular input of the input/output circuit <NUM> (e.g. a test terminal block), or manually in response to an input or command from a user or device.

Information indicating the type of periodic waveform, the frequency of the periodic waveform and various voltage test points on the periodic waveform may be stored in a memory accessible by the processor <NUM>. According to various aspects, information indicating threshold tolerances for the timing and for each of the voltage test points may also be stored in the memory accessible by the processor <NUM>. The information may be stored in the memory when the FPGA <NUM> is programmed, such as at time of manufacture. However, it will be appreciated that the FPGA <NUM> programming can be subsequently updated.

As part of the calibration algorithm or routine, the processor <NUM> is configured to verify that the timing of the control circuit <NUM> is within a predetermined threshold tolerance. According to various aspects, the analog signal of the periodic waveform is sampled, and the sampled analog values are converted to digital signals or digital values by the A/D converter <NUM>. The digital signals or digital values are provided to the FPGA <NUM> and in turn to the processor <NUM>. The processor <NUM> utilizes the digital signals or digital values to determine the frequency of the periodic waveform. The processor <NUM> can then compare the determined frequency of the periodic waveform with the known frequency of the periodic waveform stored in the memory. If the determined frequency is within the predetermined threshold tolerance of the known frequency, the timing calibration of the control circuit <NUM> is considered to be verified. For example, if the periodic waveform has a known frequency of <NUM> and the predetermined threshold tolerance is <NUM> %, the timing calibration of the control circuit <NUM> will be considered to be verified if the determined frequency is within <NUM>% of the known frequency of <NUM>.

However, if the determined frequency is not within the predetermined threshold tolerance, the FPGA <NUM> (or the processor <NUM> of the FPGA <NUM>) can be utilized to adjust the calibration of the timing (e.g., by adjusting loop times utilized by the FPGA <NUM>) to bring the timing into proper calibration (i.e., within the predetermined threshold tolerance).

As part of the calibration algorithm or routine, the processor <NUM> is also configured to verify that each of the sampled voltage levels along the periodic waveform is within a predetermined threshold tolerance. Once the timing of the control circuit <NUM> has been verified or brought into proper calibration, the processor <NUM> can utilize the verified timing to verify each of the sampled voltage levels along the periodic waveform is within the predetermined threshold tolerance. For example, voltage levels associated with a <NUM>-10V periodic waveform such as the triangular wave of <FIG> include 0V, <NUM>. 5V, 5V, <NUM>. 5V, and 10V. Because the timing of the control circuit <NUM> and the frequency of the periodic waveform are known, the calibration algorithm or routine knows when these voltage levels should occur in the periodic waveform. For the <NUM>, <NUM>-10V triangular wave of <FIG>, the amplitude of the periodic waveform should be 5V at <NUM> and at <NUM> after the start of a period of the waveform, as is shown for example in <FIG>. Since the timing has been verified or brought into proper calibration as described above, the processor <NUM> can utilize the digital signals or digital values corresponding to each of the sampled voltage levels at specific times to compare the sampled voltage values with the expected voltage values. If the sampled voltage values are each within the predetermined threshold tolerance of the expected voltage values, the voltage value calibration of the control circuit <NUM> is considered to be verified.

However, if any of the sampled voltage values are not within the predetermined threshold tolerance of the expected voltage values, the FPGA <NUM> (or the processor <NUM> of the FPGA <NUM>) can be utilized to adjust the calibration of the voltage values (e.g., by adjusting the amplitude of analog signals at the input/output circuit <NUM>) to bring the voltage values into proper calibration (i.e., within the predetermined threshold tolerance). It will be appreciated that any number of voltage levels may be sampled and verified or adjusted, and that any predetermined threshold tolerance (e.g., <NUM>%, <NUM>%, <NUM>%, etc.) may be utilized for the verification or calibration process. In general, a given predetermined threshold tolerance will be set on a case-by-case basis.

When the control circuit <NUM> is properly calibrated, the timing and voltage levels it utilizes to make control decisions are accurate to the extent they are within the predetermined threshold tolerances of the known/expected timing and voltage levels. If the predetermined threshold tolerance for a given application is <NUM>% and the control circuit <NUM> interprets an actual <NUM>. 5V analog signal as being a <NUM>. 8Y analog signal, the control circuit <NUM> is not properly calibrated and a control operation based on the interpreted voltage level could be unintended, improper and/or unsafe. For these and other reasons, verifying proper calibration and/or adjusting calibration have calibration become part of ongoing maintenance in nuclear plants or other applications. By utilizing the calibration algorithm or routine as described above, the time taken to verify and/or adjust the calibrations are significantly reduced. For example, the control circuit <NUM> can use as little as one period of a periodic waveform received from the waveform generator <NUM> to calibrate itself or verify its own calibration, greatly increasing the speed of the calibration process. As a facility such as a nuclear plant may include numerous control circuits <NUM> that need calibrated, increasing the speed of calibration significantly reduces maintenance time.

<FIG> illustrates a method <NUM> of calibrating a control circuit, in accordance with at least one aspect of the present disclosure. Although the method <NUM> is described in the context of calibrating the control circuit <NUM>, it will be appreciated that the method <NUM> may be utilized to calibrate any number of different devices (an FPGA, a computer, a programmable logic controller, an input/output circuit, etc.), circuits and/or systems. The method <NUM> may be implemented using the calibration system <NUM> or other similar systems. For purposes of simplicity, the implementation of the method <NUM> will be described in the context of the control circuit <NUM>.

For the method <NUM>, a periodic waveform is generated <NUM> by, for example, the waveform generator <NUM>. The periodic waveform is input <NUM> to an analog input of the input/output circuit <NUM>. The analog signal of the periodic waveform is sampled <NUM> by the FPGA <NUM>, and the sampled analog values are converted <NUM> to digital signals or digital values by the A/D converter <NUM>.

The digital signals or digital values are utilized by the processor <NUM> to determine <NUM> the frequency of the periodic waveform. The processor <NUM> compares <NUM> the determined frequency to the known frequency of the periodic waveform. If the determined frequency is within a predetermined threshold tolerance of the known frequency, the timing of the control circuit <NUM> is considered to be properly calibrated. If the determined frequency is not within the predetermined threshold tolerance of the known frequency, the timing of the control circuit <NUM> is adjusted to bring the timing into proper calibration.

After the calibration of the timing of the control circuit <NUM> has been verified or adjusted to be brought into proper calibration, the digital signals or digital values corresponding to the various sampled voltage levels along the periodic waveform and the known frequency of the periodic waveform are utilized by the processor <NUM> to compare <NUM> each of the sampled voltage levels along the periodic waveform with the expected voltage levels (the calibration algorithm or routine knows when the expected voltage levels should occur in the periodic waveform). If each of the various sampled voltage levels is within a predetermined threshold tolerance of the expected voltage levels, the voltage levels of the control circuit <NUM> are considered to be properly calibrated. If each of the various sampled voltage levels is not within a predetermined threshold tolerance of the expected voltage levels, the voltage levels of the control circuit <NUM> are adjusted to bring the voltage levels into proper calibration. The plurality of voltage levels can be compared to the expected voltage levels sequentially or in parallel.

The above-described method <NUM> may be repeated periodically or continuously, and may be repeated any number of times.

Although the various aspects of the calibration system <NUM> and calibration method <NUM> have been described herein in connection with certain disclosed aspects, many modifications and variations to those aspects may be implemented. Also, where materials are disclosed for certain components, other materials may be used. Furthermore, according to various aspects, a single component may be replaced by multiple components, and multiple components may be replaced by a single component, to perform a given function or functions. The foregoing description and the appended claims are intended to cover all such modifications and variations as falling within the scope of the disclosed aspects.

Claim 1:
A calibration system, comprising:
a waveform generator (<NUM>) configured to generate a periodic waveform; and
a control circuit (<NUM>) in signal communication with the waveform generator (<NUM>), wherein the control circuit (<NUM>) and comprises:
an analog-to-digital converter (<NUM>) configured to convert the periodic waveform to digital values; and
an electronic device in signal communication with the analog-to-digital converter (<NUM>),
characterized in that
the control circuit (<NUM>) is configured to output a control signal to an actuator (<NUM>) associated with a nuclear power plant, and
the electronic device is configured to execute a calibration routine to verify calibration of the following based on the periodic waveform:
timing of the control circuit (<NUM>); and
different voltage levels of the control circuit (<NUM>).