Patent Description:
In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is "diced" to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as "streets. " The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about <NUM> mils, whereby <NUM> mil = <NUM> (<NUM> mil is a thousandth of an inch, whereby <NUM> inch = <NUM>) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.

With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative.

Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <<NUM>>direction of the crystalline structure.

Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate <NUM> microns, whereby <NUM> micron = <NUM>, thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma etching of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.

<CIT> relates to masking methods for dicing substrates having a plurality of ICs. A method includes forming a mask comprising a laser energy absorbing material layer soluble in water over the semiconductor substrate. The laser energy absorbing material layer may be UV curable, and either remain uncured or be cured prior to removal with a water rinse. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the laser energy absorbing mask protecting the ICs for during the plasma etch. The soluble mask is then dissolved subsequent to singulation.

A first aspect of the present invention is a method of dicing a semiconductor wafer as defined in claim <NUM>.

A second aspect of the present invention is a mask configured for a wafer singulation process according to claim <NUM>.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as light-absorbing mask materials and treatments, laser scribing conditions, and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

To provide context, during singulation of a wafer into individual die, the wafer is cut or sectioned along dicing streets between the dies. Traditionally, dicing has been performed with a mechanical saw. Mobile devices and other technology drivers may require more advanced singulation approaches to reduce cracking, delamination, and chipping defects. A laser and etch wafer dicing approach may involve applying a water soluble protective coating to a substrate, removing the coating any device test layers in the street regions removed by laser scribing to open up the underlying substrate material, which is typically silicon (Si). The exposed Si is then plasma etched through its entire thickness to singulate the wafer into the individual die. The protective coating is removed in a deionized (DI) water based cleaning operation. Water soluble protective coatings may be desirable due to environmental considerations and ease of processing. Such a water soluble coating may primarily be used as an etch mask during the plasma etching step, and also as a layer that collects any debris generated during laser scribing. To provide further context, femtosecond lasers may be preferred in the laser scribing portion of the process. Unlike nanosecond and other long pulse lasers, femtosecond lasers have little heat effect because of the associated ultra-short pulses. Another advantage of femtosecond lasers may be the capability to remove most materials including absorptive, reflective and transparent materials. On typical wafers, there are metals which are reflective and absorptive, the dielectrics which are transparent, and the silicon substrate which is absorptive to most laser light. The water-soluble protective coating is totally or mostly transparent. These listed materials can be ablated by femtosecond lasers.

Typical femtosecond lasers have a so-called "Gaussian beam," which has high intensity near the center of the beam and low intensity toward the edge of the beam. Gaussian beams may become problematic when a femtosecond laser is used to process wafers with transparent layers on absorptive substrates, for example, a transparent protecting coating (e.g., water-soluble mask) on silicon or on dielectric layers on silicon. In order to remove the transparent layer(s), a laser process requires a suitably high intensity (e.g., leading portion of a Gaussian beam) to produce nonlinear absorption. However, since the low intensity portion (trailing portion) of the Gaussian beam does not have enough intensity to produce nonlinear absorption, the low intensity portion of the Gaussian beam passes through transparent layers with little attenuation. However, the low intensity portion of the Gaussian beam is absorbed by silicon. Such a scenario can cause heating of the transparent layer/silicon interface which can lead to delamination between the transparent layers and silicon, and to chipping or even cracking in both transparent layers and silicon. As a result, the Gaussian beam typically produces a laser damaged area, which is much wider than the intended scribe area. In another embodiment, however, the laser is not a Gaussian beam, but instead a non-Gaussian beam having high intensity portions and low intensity portions.

In accordance with the present invention, light absorbers are used in a water-soluble mask, to prevent the low intensity portion of the Gaussian beam from reaching the transparent layer/silicon interface. A laser damaged zone is significantly reduced or removed altogether. Inclusion light-absorber species in an otherwise transparent mask material enables a scribing process where a trailing portion of a Gaussian beam is kept in or confined to a mask during laser scribing, and permitting only a leading portion of the Gaussian beam to penetrate into substrate.

It is to be appreciated that although many embodiments described below are associated with femto-second laser scribing, in other embodiments, laser scribing with other laser beam types may also be compatible with masking materials described herein. It is also to be appreciated that although many embodiments described below are associated with scribing streets having metallized features, in other embodiments, metal free scribing streets may also be considered. As such, in an aspect of the present invention, a light-absorbing mask is used for a singulation process based on a combination of a laser scribing process with a plasma etching process to dice a semiconductor wafer into singulated integrated circuits. <FIG> is a Flowchart <NUM> representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention. <FIG> illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart <NUM>, in accordance with an embodiment of the present invention. Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, a mask <NUM> is formed above a semiconductor wafer or substrate <NUM>. The mask <NUM> covers and protects integrated circuits <NUM> formed on the surface of semiconductor wafer <NUM>. The mask <NUM> also covers intervening streets <NUM> formed between each of the integrated circuits <NUM>. In an embodiment, the mask <NUM> includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix.

In one embodiment, the water soluble matrix is a polyvinyl alcohol (PVA)-based water soluble matrix, where the PVA is the solid component. In another embodiment, the solid component for the water soluble matrix is selected from the group consisting of polyethylene oxide, polyethylene glycol, polyacryclic acid, polyacrylamide, polystyrene-maleic acid copolymer, hydroxyethyl cellulose and hydroxyethyl starch. In one embodiment, the water-soluble matrix includes approximately <NUM>-<NUM> weight % of the solid component with the remainder water.

In one embodiment, forming the mask <NUM> above the semiconductor wafer <NUM> includes spin-coating the mask <NUM> on the semiconductor wafer <NUM>. In a specific embodiment, prior to coating, a plasma or chemical pre-treatment is performed to enable better wettability and coating of the wafer.

Mask <NUM> is a water soluble mask that it is readily dissolvable in an aqueous media. For example, in one embodiment, the as deposited water-soluble mask <NUM> is composed of a material that is soluble in one or more of an alkaline solution, an acidic solution, or in deionized water. In a specific embodiment, the as-deposited water-soluble mask <NUM> has an etch or removal rate in an aqueous solution approximately in the range of <NUM> - <NUM> microns per minute and, more particularly, approximately <NUM> microns per minute.

In an embodiment, for a <NUM> nanometer green laser, the light absorber species is selected from the group consisting of Rhodamine B, Rhodamine G, and D&C red <NUM>. In an embodiment, for a <NUM> nanometer green laser, the light absorber species is selected from the group of dyes or pigments that absorb <NUM> light, where examples of dyes are Rhodamine B, Rhodamine G, betanin and D&C red <NUM>. It is to be appreciated that since a relatively larger pigment dispersion may scatter light and have a negative effect on wafer alignment, water-soluble dyes may be preferred light absorbers. However, in an embodiment, a nano-dispersion of pigments (dispersion of pigment particles having a size on the nanometer scale) is used and exhibits relatively low light scattering. In one embodiment, the dispersion of pigment particles is composed of carbon black, iron oxide, or gold colloids. In an embodiment, a dispersion of CeO<NUM> particles is used as a UV-absorbing species.

In an additional aspect, typical water soluble polymers do not have high resistance to plasma etching, while polymers that have good etch resistance are typically not soluble in water. Etch selectivity may be defined as the ratio of the amount of substrate material (e.g., Si) removed to the amount of mask loss during the etch process. Water soluble polymers typically have relatively low selectivity, and it may be advantageous to enhance the selectivity of the mask without sacrificing water solubility. Embodiments may address potential needs for improved etch resistance in a water soluble dicing mask. In a specific example, a polyvinyl alcohol (PVA) matrix with silica particles dispersed therein is provided as an etch mask. More generally, in an embodiment, particle dispersions are mixed with water soluble polymers to form a composite mask. Materials such as oxides and polymers, which are not water soluble, can be incorporated into water soluble polymer mixtures as dispersions. Suitable particle dispersions may be colloidal dispersions of inorganic particles and polymers. Suitable inorganic particles may include oxide, such as silicon oxide, aluminum oxide, titanium oxide, and cerium oxide, and other particles such as calcium carbonate, barium sulfate, etc. Suitable polymer particles may include polystyrene and PTFE. It is to be appreciated that low haze is usually required for the mask since the mask is laser scribed. To minimize haze, in an embodiment, particles smaller than <NUM> nanometers may be included in the matrix.

Thus, a plurality of particles is dispersed throughout the water-soluble matrix of the mask that includes light-absorber species. The plurality of particles is different from the light-absorber species. In one embodiment, the plurality of particles has an average diameter approximately in the range of <NUM>-<NUM> nanometers. In one embodiment, a ratio of weight % of the solid component of the water-soluble matrix to weight % of the plurality of particles is approximately in the range of <NUM>:<NUM> - <NUM>:<NUM>. In one embodiment, the plurality of particles has an average diameter approximately in the range of <NUM>-<NUM> nanometers, and a ratio of weight % of the solid component of the water-soluble matrix to weight % of the plurality of particles is approximately in the range of <NUM>:<NUM> - <NUM>:<NUM>. In one embodiment, the plurality of particles has an average diameter approximately in the range of <NUM>-<NUM> nanometers. It is to be appreciated that a smaller diameter may be preferable in order to mitigate or negate any potential laser light scattering or haze. In one embodiment, the ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of <NUM>:<NUM> - <NUM>:<NUM>.

In one embodiment, the plurality of particles is a plurality of particles selected from the group consisting of silica (SiO<NUM>) particles, alumina (Al<NUM>O<NUM>) particles, alumina-coated silicon particles, polytetrafluoroethylene (PTFE) particles, and combinations thereof. It is to be appreciated that other oxides, such as titanium oxide, cerium oxide, zinc oxide, indium tin oxide, zirconium oxide, and other inorganic particles such as calcium carbonate, barium sulfate, etc., may also be used as particle additives. Suitable polymer particles also include polystyrene, epoxies, etc. In one embodiment, the plurality of particles is a plurality of absorber species.

In an embodiment, semiconductor wafer or substrate <NUM> is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate <NUM> is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer <NUM> includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate <NUM> is composed of a III-V material such as, e.g., a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In an embodiment, semiconductor wafer or substrate <NUM> has disposed thereon or therein, as a portion of the integrated circuits <NUM>, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits <NUM>. Materials making up the streets <NUM> may be similar to or the same as those materials used to form the integrated circuits <NUM>. For example, streets <NUM> may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets <NUM> includes test devices similar to the actual devices of the integrated circuits <NUM>.

In an optional embodiment, the mask <NUM> is baked prior to laser patterning of the mask. In an embodiment, the mask <NUM> is baked to increase the etch resistance of the mask <NUM>. In a specific embodiment, the mask <NUM> is baked at a relatively high temperature approximately in the range of <NUM> to <NUM> degrees Celsius. Such higher temperature baking may cause crosslink of the mask <NUM> so as to significantly increase etch resistance. For example, when the mask <NUM> mask is baked at or near <NUM> degrees Celsius for approximately <NUM> minutes, the resulting enhanced light-absorbing and etch resistant mask is robust against a silicon etch process. In one embodiment, baking is performed using a hot plate technique or a heat (light) radiation applied from the wafer front side (e.g., non-tape mounted side in the case of the use of a substrate carrier) or other suitable techniques.

Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, the mask <NUM> is patterned with a laser scribing process to provide patterned mask <NUM> with gaps <NUM>, exposing regions of the semiconductor wafer or substrate <NUM> between the integrated circuits <NUM>. As such, the laser scribing process is used to remove the material of the streets <NUM> originally formed between the integrated circuits <NUM>. In accordance with an embodiment of the present invention, patterning the mask <NUM> with the laser scribing process further includes forming trenches <NUM> partially into the regions of the semiconductor wafer <NUM> between the integrated circuits <NUM>, as is also depicted in <FIG>.

In an embodiment, the mask <NUM> is patterned with a Gaussian laser beam. The light-absorber species of the mask substantially confines a trailing portion of the Gaussian beam to the mask <NUM> during the patterning. A leading portion of the Gaussian beam is substantially confined to the semiconductor wafer or substrate <NUM> during the patterning. In an embodiment, in the case where the mask <NUM> further includes a plurality of particles for increasing etch resistance, the plurality of particles of the mask <NUM> does not substantially interfere with the laser scribing process during the patterning of the mask <NUM> with the laser scribing process.

In an embodiment, a femtosecond-based laser is used as a source for a laser scribing process.

For example, in an embodiment, a laser with a wavelength in the visible spectrum plus the ultraviolet (UV) and infra-red (IR) ranges (totaling a broadband optical spectrum) is used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (<NUM>-<NUM> seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask <NUM>, the streets <NUM> and, possibly, a portion of the semiconductor wafer or substrate <NUM>.

In order to determine the effect of light absorbers on a laser scribe process, e.g., as relative amounts of a light-absorber, liquid coatings were prepared with and without light-absorber species and were then tested in a scribing environment. <FIG> illustrates scanning electron microscope (SEM) images taken from a trench profile perspective following laser scribing but prior to mask removal for dye concentrations of <NUM>%, <NUM>% and <NUM>%, in accordance with an embodiment of the present invention. <FIG> illustrates scanning electron microscope (SEM) images and optical microscope images of trench surfaces following laser scribing mask removal for dye concentrations of <NUM>%, <NUM>% and <NUM>%, in accordance with an embodiment of the present invention.

Referring to <FIG> and <FIG>, transparent water-soluble mask samples were prepared to include no light absorber, <NUM> weight % light absorber and <NUM> weight % light absorber. The light absorber used was D&C Red <NUM>. The water soluble mask materials were coated on bare silicon (Si) wafers with the coating materials. The coatings were baked to dry. A laser scribe process was used to open the mask material. A plasma etch was performed to achieve a desired trench etch depth in the Si. The wafers were cleaved/cross-sectioned into samples to obtain SEM images and measurements of the width of laser affected areas. As shown in <FIG> and <FIG>, <NUM>% D&C red <NUM> significantly reduces the width of the laser damaged zones.

It is to be appreciated that by using a laser beam profile with contributions from the femtosecond range, heat damage issues are mitigated or eliminated versus longer pulse widths (e.g., nanosecond processing). The elimination or mitigation of damage during laser scribing may be due to a lack of low energy recoupling or thermal equilibrium. It is also to be appreciated that laser parameter selection, such as beam profile, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example, <FIG> illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present invention. Referring to <FIG>, a street region <NUM> includes the top portion <NUM> of a silicon substrate, a first silicon dioxide layer <NUM>, a first etch stop layer <NUM>, a first low K dielectric layer <NUM> (e.g., having a dielectric constant of less than the dielectric constant of <NUM> for silicon dioxide), a second etch stop layer <NUM>, a second low K dielectric layer <NUM>, a third etch stop layer <NUM>, an undoped silica glass (USG) layer <NUM>, a second silicon dioxide layer <NUM>, and a scribing and/or etch mask <NUM> (such as a mask described above in association with mask <NUM>). Copper metallization <NUM> is disposed between the first and third etch stop layers <NUM> and <NUM> and through the second etch stop layer <NUM>. In a specific embodiment, the first, second and third etch stop layers <NUM>, <NUM> and <NUM> are composed of silicon nitride, while low K dielectric layers <NUM> and <NUM> are composed of a carbon-doped silicon oxide material.

Under conventional laser irradiation (such as nanosecond-based irradiation), the materials of street <NUM> behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based irradiation. In an embodiment, a femto-second based laser scribing process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper.

In case that the laser beam it is a femtosecond-based laser beam, in an embodiment, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of <NUM> femtoseconds to <NUM> femtoseconds, although preferably in the range of <NUM> femtoseconds to <NUM> femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of <NUM> nanometers to <NUM> nanometers, although preferably in the range of <NUM> nanometers to <NUM> nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of <NUM> microns to <NUM> microns, though preferably approximately in the range of <NUM> microns to <NUM> microns or between <NUM>-<NUM> microns.

In an embodiment, the laser source has a pulse repetition rate approximately in the range of <NUM> to <NUM>, although preferably approximately in the range of <NUM> to <NUM>. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of <NUM> uJ to <NUM> uJ, although preferably approximately in the range of 1uJ to 5uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of <NUM>/sec to <NUM>/sec, although preferably approximately in the range of <NUM>/sec to <NUM>/sec.

The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably <NUM>-<NUM> passes. In one embodiment, the scribing depth in the work piece is approximately in the range of <NUM> microns to <NUM> microns deep, preferably approximately in the range of <NUM> microns to <NUM> microns deep. In an embodiment, the kerf width of the laser beam generated is approximately in the range of <NUM> microns to <NUM> microns, although in silicon wafer scribing/dicing preferably approximately in the range of <NUM> microns to <NUM> microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth.

It is to be appreciated that the dicing or singulation process could be stopped after the above described laser scribing in a case that the laser scribing is used to pattern the mask as well as to scribe fully through the wafer or substrate in order to singulate the dies. In accordance with such an approach, in an embodiment, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask is patterned and the integrated circuits of the semiconductor wafer are singulated with a laser scribing process. In a particular such embodiment, the mask is patterned with a Gaussian beam. The light-absorber species of the mask substantially confines a trailing portion of the Gaussian beam to the mask during the patterning. A leading portion of the Gaussian beam is substantially confined to the semiconductor wafer during the patterning. The laser scribing completes the singulation. Accordingly, in an embodiment, further singulation processing such as plasma etching to effect singulation is not required. However, the embodiments that follow may be considered in cases where laser scribing alone is not implemented for total singulation.

In an optional embodiment, subsequent to the laser scribing process and prior to a plasma etching singulation process, an intermediate post mask-opening cleaning operation is performed. In an embodiment, the post mask-opening cleaning operation is a plasma-based cleaning process. In an example, as described below, the plasma-based cleaning process is non-reactive to the trenches <NUM> of the substrate <NUM> exposed by the gaps <NUM>.

In accordance with one embodiment, the plasma-based cleaning process is non-reactive to exposed regions of the substrate <NUM> in that the exposed regions are not or only negligible etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, Ar or another non-reactive gas (or the mix) is used to perform a highly-biased plasma treatment both for mask condensation and cleaning of scribed openings. The approach may be suitable for water-soluble masks such as mask <NUM>. In another such embodiment, separate mask condensation (densification of the surface layer) and scribed trench cleaning operations are used, e.g., an Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation is first performed, and then an Ar +SF<NUM> plasma cleaning of a laser scribed trench is performed. This embodiment may be suitable for cases where Ar-cleaning is not sufficient for trench cleaning due to too thick of a mask material.

Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, the semiconductor wafer <NUM> is etched through the gaps <NUM> in the patterned mask <NUM> to singulate the integrated circuits <NUM>. In accordance with an embodiment of the present invention, etching the semiconductor wafer <NUM> includes ultimately etching entirely through semiconductor wafer <NUM>, as depicted in <FIG>, by etching the trenches <NUM> initially formed with the laser scribing process. The patterned mask <NUM> protects the integrated circuits during the plasma etching.

In accordance with an embodiment of the present invention, plasma etching the semiconductor wafer through the gaps involves plasma etching a single crystalline silicon wafer. In one such embodiment, a ratio of an etch rate of the single crystalline silicon wafer to an etch rate of the mask <NUM> is approximately in the range of <NUM>:<NUM> - <NUM>:<NUM> during the plasma etching.

In an embodiment, patterning the mask <NUM> with the laser scribing process involves forming trenches in the regions of the semiconductor wafer between the integrated circuits, and plasma etching the semiconductor wafer involves extending the trenches to form corresponding trench extensions. In one such embodiment, each of the trenches has a width, and each of the corresponding trench extensions has the width.

Etching the semiconductor wafer <NUM> includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer <NUM> is greater than <NUM> microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, CA, USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer <NUM> at an etch rate greater than approximately <NUM>% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally a fluorine-based gas such as SF<NUM>, C<NUM> F<NUM>, CHF<NUM>, XeF<NUM>, or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the light-absorbing water soluble patterned mask <NUM> is removed after the singulation process, as depicted in <FIG>, and as is described in greater detail below. In another embodiment, the plasma etching operation described in association with <FIG> employs a conventional Bosch-type dep/etch/dep process to etch through the substrate <NUM>. Generally, a Bosch-type process consists of three sub-operations: deposition, a directional bombardment etch, and isotropic chemical etch which is run through many iterations (cycles) until silicon is etched through.

In an embodiment, following the singulation process, the patterned mask <NUM> is removed. In an embodiment, the patterned mask <NUM> is removed using an aqueous solution. In one such embodiment, the patterned mask <NUM> is removed by a hot aqueous treatment, such as a hot water treatment. In a specific embodiment, the patterned mask <NUM> is removed in a hot water treatment at a temperature approximately in the range of <NUM> - <NUM> degrees Celsius. In a particular embodiment, the patterned mask <NUM> is removed in a hot water treatment at a temperature approximately in the range of <NUM> - <NUM> degrees Celsius. It is to be appreciated that the hotter the temperature of the water, the less time may be needed for the hot water treatment. In accordance with an embodiment of the present invention, a plasma cleaning process can also be performed after etching to aid in the removal of the patterned mask <NUM>.

It is to be appreciated that other circumstances may benefit from a lower water treatment temperature. For example, in the case that a wafer for dicing is supported on a dicing tape that may be impacted by a higher temperature water treatment (e.g., through loss of adhesion), a relatively lower water treatment temperature may be employed, albeit for a longer duration that a relatively higher water treatment temperature. In one such embodiment, the water treatment is between room temperature (i.e., the water is un-heated), but below a temperature of approximately <NUM> degrees Celsius. In a specific such embodiment, the patterned mask <NUM> is removed in a warm water treatment at a temperature approximately in the range of <NUM> - <NUM> degrees Celsius.

Accordingly, referring again to Flowchart <NUM> and <FIG>, wafer dicing may be preformed by initial ablation to ablate through an mask <NUM>, through wafer streets (including metallization), and partially into a silicon substrate. Die singulation may then be completed by subsequent through-silicon deep plasma etching. A specific example of a materials stack for dicing is described below in association with <FIG>, in accordance with an embodiment of the present invention.

Referring to <FIG>, a materials stack for hybrid laser ablation and plasma etch dicing includes a mask <NUM>, a device layer <NUM>, and a substrate <NUM>. The mask layer <NUM>, device layer <NUM>, and substrate <NUM> are disposed above a die attach film <NUM> which is affixed to a backing tape <NUM>. In other embodiments, direct coupling to a standard dicing tape is used. In an embodiment, the mask <NUM> is one such as described above in association with mask <NUM>. The device layer <NUM> includes an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as copper layers) and one or more low K dielectric layers (such as carbon-doped oxide layers). The device layer <NUM> also includes streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits. The substrate <NUM> is a bulk single-crystalline silicon substrate. In an embodiment, the mask <NUM> is fabricated using a thermal treatment or bake <NUM>, such as described above.

In an embodiment, the bulk single-crystalline silicon substrate <NUM> is thinned from the backside prior to being affixed to the die attach film <NUM>. The thinning may be performed by a backside grind process. In one embodiment, the bulk single-crystalline silicon substrate <NUM> is thinned to a thickness approximately in the range of <NUM> - <NUM> microns. It is important to note that, in an embodiment, the thinning is performed prior to a laser ablation and plasma etch dicing process. In an embodiment, the mask <NUM> has a thickness approximately in the range of <NUM>-<NUM> microns and the device layer <NUM> has a thickness approximately in the range of <NUM> - <NUM> microns. In an embodiment, the die attach film <NUM> (or any suitable substitute capable of bonding a thinned or thin wafer or substrate to the backing tape <NUM>, such as dicing tapes consisting of an upper adhesive layer and a base film) has a thickness approximately in the range of <NUM>-<NUM> microns. Referring to <FIG>, the mask <NUM>, the device layer <NUM> and a portion of the substrate <NUM> are patterned with a laser scribing process <NUM> to form trenches <NUM> in the substrate <NUM>.

Referring to <FIG>, a through-silicon deep plasma etch process <NUM> is used to extend the trench <NUM> down to the die attach film <NUM>, exposing the top portion of the die attach film <NUM> and singulating the silicon substrate <NUM>. The device layer <NUM> is protected by the mask <NUM> during the through-silicon deep plasma etch process <NUM>.

Referring to <FIG>, the singulation process may further include patterning the die attach film <NUM>, exposing the top portion of the backing tape <NUM> and singulating the die attach film <NUM>. In an embodiment, the die attach film is singulated by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portions of substrate <NUM> (e.g., as individual integrated circuits) from the backing tape <NUM>. In one embodiment, the singulated die attach film <NUM> is retained on the back sides of the singulated portions of substrate <NUM>. In an alternative embodiment, in the case that substrate <NUM> is thinner than approximately <NUM> microns, the laser scribing process <NUM> is used to completely singulate substrate <NUM> without the use of an additional plasma process. Embodiments may further include removing the mask <NUM> from the device layer <NUM>. Removal of the mask <NUM> can be as described above for removal of the patterned mask <NUM>.

A single process tool may be configured to perform many or all of the operations in a hybrid laser ablation and plasma etch singulation process utilizing a light-absorbing water soluble mask. For example, <FIG> illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present invention.

Referring to <FIG>, a process tool <NUM> includes a factory interface <NUM> (FI) having a plurality of load locks <NUM> coupled therewith. A cluster tool <NUM> is coupled with the factory interface <NUM>. The cluster tool <NUM> includes one or more plasma etch chambers, such as plasma etch chamber <NUM>. A laser scribe apparatus <NUM> is also coupled to the factory interface <NUM>. The overall footprint of the process tool <NUM> may be, in one embodiment, approximately <NUM> millimeters (<NUM> meters) by approximately <NUM> millimeters (<NUM> meters), as depicted in <FIG>.

In an embodiment, the laser scribe apparatus <NUM> houses a laser assembly configured to provide a femto-second based laser beam. In an embodiment, the laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus <NUM>, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, the laser is also moveable. The overall footprint of the laser scribe apparatus <NUM> may be, in one embodiment, approximately <NUM> millimeters by approximately <NUM> millimeters, as depicted in <FIG>.

In an embodiment, the one or more plasma etch chambers <NUM> is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers <NUM> is configured to perform a deep silicon etch process. In a specific embodiment, the one or more plasma etch chambers <NUM> is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, CA, USA. The etch chamber may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber <NUM> to facilitate high silicon etch rates. In an embodiment, more than one etch chamber is included in the cluster tool <NUM> portion of process tool <NUM> to enable high manufacturing throughput of the singulation or dicing process.

The factory interface <NUM> may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus <NUM> and cluster tool <NUM>. The factory interface <NUM> may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool <NUM> or laser scribe apparatus <NUM>, or both.

Cluster tool <NUM> may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, a deposition and/or bake chamber <NUM> is included. The deposition and/or bake chamber <NUM> may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. Such a mask material may be baked prior to the dicing process, as is described above. Such a mask material may be water soluble, as is also described above.

In an embodiment, referring again to <FIG>, a wet station <NUM> is included. The wet station may be suitable for cleaning performing a room temperature or a hot aqueous treatment for removing a light-absorbing water soluble mask, as is described above, subsequent to a laser scribe and plasma etch singulation process of a substrate or wafer, or subsequent to a laser scribe-only singulation process. In an embodiment, although not depicted, a metrology station is also included as a component of process tool <NUM>. The cleaning chamber can include atomized mist and/or megasonics nozzle hardware that adds a physical component to the cleaning process, enhancing the dissolution rate of the mask.

Configurations may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. The computer system is coupled with process tool <NUM> described in association with <FIG>. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc..

<FIG> illustrates a diagrammatic representation of a machine in the exemplary form of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. Alternatively, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system <NUM> includes a processor <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory <NUM> (e.g., a data storage device), which communicate with each other via a bus <NUM>.

Processor <NUM> represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor <NUM> is configured to execute the processing logic <NUM> for performing the operations described herein.

The computer system <NUM> may further include a network interface device <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), and a signal generation device <NUM> (e.g., a speaker).

The secondary memory <NUM> may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) <NUM> on which is stored one or more sets of instructions (e.g., software <NUM>) embodying any one or more of the methodologies or functions described herein. The software <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processor <NUM> also constituting machine-readable storage media. The software <NUM> may further be transmitted or received over a network <NUM> via the network interface device <NUM>.

While the machine-accessible storage medium <NUM> can be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

A machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits, such as one or more of the methods described herein.

Claim 1:
A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light-absorber species throughout the water-soluble matrix;
patterning the mask and a portion of the semiconductor wafer with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits,
wherein patterning with a laser scribing process comprises patterning with a laser beam, wherein the light-absorber species of the mask substantially confines a first low intensity portion of
the laser beam to the mask during the patterning, and wherein a second high intensity portion of the laser beam is substantially confined to the semiconductor wafer during the patterning; and
plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits, wherein the patterned mask protects the integrated circuits during the plasma etching , wherein the light-absorber species is a water soluble dye dissolved in the water-soluble matrix, and wherein the mask further comprises a plurality of particles dispersed throughout the water-soluble matrix, the plurality of particles being different from the light-absorber species.