Patent Description:
<CIT> discloses a superhetrodyne receiver, comprising: a sampling mixer being configured to sample an analog radio frequency signal using a certain sampling rate to obtain a discrete-time sampled signal, and to shift the discrete-time sampled signal towards a first intermediate frequency to obtain an intermediate discrete-time sampled signal towards a first intermediate frequency to obtain an intermediate discrete-time signal sampled at the sampling rate; a discrete-time filter being configured to filter the intermediate discrete-time signal at the sampling rate to obtain a filtered signal; and a discrete-time mixer being configured to shift the filtered signal towards a second intermediate frequency.

The present invention comprises a receiver path circuit and a composite baseband filter as defined in the claims. Embodiments that do not fall within the scope of the claims are to be interpreted as examples useful for understanding the invention.

Typical baseband architectures in receivers can be composed of continuous time analogue filtering that provides enough anti-aliasing before entering the signal to a data converter. Such continuous time filters can be built around analogue components (resistors and capacitors) that can be typically trimmed and whose native values deviate with temperature once calibrated. This variation necessitates in some receiver circuits the need for periodic calibration, that requires fine trim resolution, to track value deviations that may occur with process, voltage and temperature, etc. Also, as technology nodes scale down, the dynamic range to process analogue signals has drastically reduced making legacy implementations more difficult to port to finer technology modes. Looking to specific function (localization) for Internet of Things (IoT), the spread of group delay and its deviation with temperature become hard to maintain under control.

<FIG> shows a receiver (RX) chain <NUM> with a RX baseband. The downconverted signal after the low noise amplifier (LNA) <NUM> and mixer <NUM> is filtered by an analog baseband filter <NUM>, which is shown to be in series with a baseband gain control stage <NUM>. The outputs of the baseband gain control stage <NUM> are provided to analogue to digital converters (ADCs) <NUM>, which are clocked at ant ADC clocking frequency (Fadc). The type, order and bandwidth (BW) of the baseband filter <NUM> are application dependent. RX structures such as those shown in <FIG> can be implemented in one of many possible ways, either in voltage or current domain, using single-ended or differential implementations, employing a combination of active or passive circuit elements, etc.. Furthermore, the implemented baseband filter <NUM> can comprise real or complex poles.

<FIG> shows an example embodiment of a receiver circuit <NUM>. The receiver circuit <NUM> includes a first stage <NUM>, a down-sampler <NUM> and a second stage <NUM>. In this example, the down-sampler <NUM> is illustrated as separate from the first stage <NUM> and the second stage <NUM>. In other examples, as will be described below, the functionality of the down-sampler <NUM> can be provided as part of the first stage <NUM> or the second stage <NUM>.

The first stage <NUM> filters a received mixer-output-signal <NUM> in order to provide a first-stage-output-signal <NUM>. The mixer-output-signal <NUM> can be provided by a mixer such as the one illustrated in <FIG>. The first stage <NUM> can be configured such that it reduces undesirable aliasing effects at harmonics of a transition-frequency (which will be discussed below). The filter of the first stage <NUM> comprises a passive filter, which can assist with lowering the power consumption of the first stage <NUM>. The filter of the first stage <NUM> in this example is a continuous time filter, although as will be discussed below in other examples it can be a discrete time filter.

The down-sampler <NUM> down-samples the first-stage-output-signal <NUM> to provide a transition-signal <NUM>, which has a transition-frequency. The transition-frequency is lower than the frequency of the first-stage-output-signal. For instance, if the frequency of the first-stage-output-signal is <NUM>, the transition-frequency can be <NUM>. In this example, the down-sampler <NUM> is clocked by a down-sampler-clock-signal <NUM> that is provided by a local oscillator (LO), which is also used to provide a clock signal for the mixer. Advantageously, this can mean that the down-sampler <NUM> does not require any separate high-rate clocks in addition to the output of the LO that is already available from the mixer. As proposed, all clock signals are isochroous with the LO. Therefore, the frequency of the down-sampler-clock-signal <NUM> can also be <NUM>.

The second stage <NUM> comprises a switched-capacitor circuit. A switched-capacitor circuit uses switches to selectively charge and discharge one or more capacitors, as is known in the art. The switches are controlled such that the charge transfer is well-defined and deterministic. The switched-capacitor circuit of the second stage <NUM> filters, and reduces the frequency of, the transition-signal <NUM> in order to provide a second-stage-output-signal <NUM> for an ADC. As discussed below there may be one or more components in between the second stage <NUM> and the ADC. The second-stage-output-signal <NUM> has a frequency that is suitable for the downstream ADC. To continue the numerical example from above, the frequency of the second-stage-output-signal <NUM> may be the nearest matched to the sampling clock of the data path ADC in MHz. In this example, the second stage <NUM> is clocked by a second-stage-clock-signal <NUM> that has a frequency that is lower than that of the down-sampler-clock-signal <NUM>. For instance, the second-stage-clock-signal <NUM> can have a frequency that is an integer division of the frequency of the down-sampler-clock-signal <NUM>. In this numerical example, the frequency of the second-stage-clock-signal <NUM> is <NUM> (the same as the transition-frequency) and the frequency of the down-sampler-clock-signal <NUM> is <NUM>.

Advantageously, use of the two stages in the receiver circuit <NUM> of <FIG> can result in a relatively low power consumption. Furthermore, the second-stage-output-signal <NUM> has a relatively low frequency that still enables acceptable performance of the downstream ADC without the ADC consuming a relatively large amount of power that would be required for a higher frequency signal.

In this way, examples disclosed herein can provide a novel RX baseband architecture (that is especially useful for IoT) that include switched capacitor circuits. Two different anti-aliasing stages can be combined in order to enable a low-power low-sampling rate ADC.

<FIG> shows another example embodiment of a receiver circuit <NUM>. Features of the receiver circuit <NUM> of <FIG> that are also shown in <FIG> are given corresponding reference numbers in the <NUM> series and will not necessarily be described again here.

In <FIG>, the functionality of the down-sampler of <FIG> has been incorporated into the first stage <NUM> of <FIG>. In this example, the first stage <NUM> comprises a first-stage down-sampling filter that provides the filtering functionality of the first stage of <FIG> and also the functionality of the down-sampler if <FIG>. One way that such a first-stage down-sampling filter can be implemented is a switched-capacitor circuit, as will be described in detail with reference to <FIG> in particular.

The first-stage down-sampling filter of the first stage <NUM> in this example is clocked by a down-sampler-clock-signal <NUM> that is provided by a LO, and therefore has a LO frequency that is also used by the mixer (not shown). The output of the first stage <NUM> in <FIG> is the transition-signal <NUM>. That is, the transition-signal <NUM> can also be considered as a first-stage-output-signal in this example.

<FIG> shows another example embodiment of a receiver circuit <NUM>. Features of the receiver circuit <NUM> of <FIG> that are also shown in <FIG> are given corresponding reference numbers in the <NUM> series and will not necessarily be described again here. This includes a first stage <NUM>, which receives a received mixer-output-signal <NUM>.

In <FIG>, the functionality of the down-sampler of <FIG> has been incorporated into the second stage <NUM> of <FIG>. In this example, the second stage <NUM> receives the down-sampler-clock-signal <NUM> in order to down-sample the first-stage-output-signal <NUM> to provide the transition-signal (not shown in <FIG> because it is internal to the second stage <NUM>) having a transition-frequency. The second stage also receives the second-stage-clock-signal <NUM> in order to filter and reduce the frequency of the transition-signal to provide the second-stage-output-signal <NUM> in the same way as <FIG>.

<FIG> shows a block diagram of a switched capacitor RX baseband filter that includes two receiver circuits <NUM> that are similar to that of <FIG>.

<FIG> shows a LNA <NUM>, which receives an input signal from an antenna (not shown) and provide an output signal to a mixer <NUM>. As is known in the art, the mixer <NUM> mixes the output signal from the LNA with a clock signal that is provided by a local oscillator (LO). In this example, the LO frequency is about <NUM>.

The mixer <NUM> provides a mixer-output-signal <NUM>, which is provided as an input signal to two identical receiver path circuits <NUM> that are in parallel with each other. The components of only one of the receiver path circuits <NUM> are labelled with reference numbers so as not to overload the drawing with reference numbers. One of the receiver path circuits <NUM> is used to process in-phase signals and the other receiver path circuit <NUM> is used to process quadrature signals.

In other examples, instead of having two separate receiver path circuits <NUM>, a single receiver path circuit can be used to process the in-phase and quadrature signals. Such a receiver path can have two inputs and two output outputs, and can be referred to as a poly-phase filter or a "complex" filter.

The receiver path circuits <NUM> include a first stage <NUM>, which in this example is implemented as a first switched-capacitor filter (resistor-capacitor infinite impulse response (RC-IIR)). The first stage <NUM> receives a down-sampler-clock-signal <NUM>, in this example from the LO that provides the clock signal to the mixer <NUM>, such that switches of the first stage <NUM> are operated at the LO rate (~<NUM> in this example). Further details of an example implementation of the first switched-capacitor filter of the first stage <NUM> are provided below with reference to <FIG>. In this way, the first stage <NUM> can filter the mixer-output-signal <NUM> and also down-sample in order to provide a transition-signal <NUM> having a transition-frequency that is less than the frequency of the mixer-output-signal <NUM>. In this example, the transition-frequency is LO/<NUM> (in this example about <NUM>).

The receiver path circuits <NUM> also include a second stage <NUM>, which in this example is implemented as a <NUM>nd switched-capacitor filter (Weighted Tapped Sampling Filter (WTSF)). The second stage <NUM> receives a second-stage-clock-signal <NUM>, which has a frequency that is a fraction of the LO rate (LO/<NUM>=<NUM>, in this example). In this way, switches of the second stage <NUM> are operated at the second-stage-clock-signal <NUM>, which is also the transition-frequency. The output of the second stage <NUM> is a second-stage-output-signal <NUM>, which has a frequency that is suitable for a downstream ADC <NUM>. In this example, the frequency of the second-stage-output-signal <NUM> is <NUM>, which is the same frequency as an ADC-clock-signal <NUM> that is used to clock the ADC <NUM>. This is a relatively low frequency and therefore is good for reducing the power consumption of the ADC <NUM>. Further details of an example implementation of the 2nd switched-capacitor filter (WTSF) of the second stage <NUM> are provided below with reference to <FIG>.

Since the second stage <NUM> includes a switched-capacitor circuit, the second-stage-output-signal <NUM> that it provides as an output signal is in the charge domain. In this example, <FIG> also includes two Bank to ADC (B2A) stages <NUM>; each one connected to the output terminal of one of the respective receiver path circuits <NUM>. The Bank to ADC (B2A) stages <NUM> convert the charge output of the second stage filters to a voltage swing for a respective one of two ADCs <NUM>. The architecture and implementation of the B2A stages <NUM> can be chosen based on the targeted ADC type and other specifics of an implementation.

<FIG> shows an example embodiment of a first-stage down-sampling filter <NUM> that can be provided as part of a first stage of any of the receiver circuits that are disclosed herein. In this example the first-stage down-sampling filter comprises a first-stage switched capacitor circuit, which has a switched-capacitor based RxBB filter structure.

The upper portion of <FIG> shows a circuit diagram of the down-sampling filter <NUM>. The lower portion of <FIG> shows a timing diagram for the down-sampling filter <NUM>, and illustrates that there are four <NUM>% duty cycle phases of the LO signal used for sampling an input-capacitor <NUM> (which can also be referred to as a history capacitor). That is, a complete sampling period (Ts) equals a period of the local oscillator (Tlo) that provides a clock signal to the mixer. Equivalently, a sampling frequency equals a local oscillator frequency.

The first-stage down-sampling filter <NUM> includes a first-stage-input-node <NUM>, a first-stage-intermediate-node <NUM>, a first-stage-output-node <NUM> and a first-stage-reset-node <NUM>. The first-stage-input-node <NUM> receives a mixer-output-signal from a mixer, in the same way as described above. The first-stage-output-node <NUM> is for providing a transition-signal. As discussed above, the transition-signal has a transition-frequency, which is a lower frequency than that of the first-stage-output-signal.

The first-stage down-sampling filter <NUM> also includes a sampling-capacitor <NUM> (Cs), the input-capacitor <NUM> (Ch), an output-capacitor <NUM> (Co), an intermediate-capacitor <NUM> (Co); and a first-stage-switch <NUM> having a switch-node <NUM>.

The input-capacitor <NUM> (Ch) is connected between the first-stage-input-node <NUM> and ground <NUM>. The sampling-capacitor <NUM> (Cs) is connected between the switch-node <NUM> of the first-stage-switch <NUM> and ground <NUM>. The intermediate-capacitor <NUM> (Co) is connected between the first-stage-intermediate-node <NUM> and ground <NUM>. The output-capacitor <NUM> (Co) is connected between the first-stage-output-node <NUM> and ground <NUM>. The first-stage-reset-node is connected to ground <NUM>.

<FIG> also shows a capacitor <NUM> (Cw) that represents the equivalent impedance of the second stage, and is connected between the first-stage-output-node <NUM> and ground <NUM>.

The first-stage-switch <NUM> is operable to connect the switch-node <NUM> to each of the first-stage-input-node <NUM>, the first-stage-intermediate-node <NUM>, the first-stage-output-node <NUM> and the first-stage-reset-node <NUM> in turn. The timing diagram in the lower portion of <FIG> has four plots <NUM>, <NUM>, <NUM>, <NUM>:.

The first-stage down-sampling filter <NUM> is passive and therefore has relatively low power consumption; its power consumption comes primarily from routing the clocks. Also, the first-stage down-sampling filter <NUM> of this implementation does not require any high-rate clocks, except the LO phases that are already available from the mixer. The first-stage down-sampling filter <NUM> can be referred to as a rotating capacitor circuit, which provides good noise performance and can reduce any gain loss. The first-stage down-sampling filter <NUM> can be considered as a N-path filter whose clocks are the LO phase. The structure of the first-stage down-sampling filter <NUM> can beneficially preserve its gain and linearity even at much higher filtering orders. The gain can remain the same simply because no additional charge loss occurs in the system.

The first-stage down-sampling filter <NUM> is arranged as a third order filter in this example using the four LO phases that are available from a passive <NUM>% duty cycle mixer. The dynamic range at the filter input (the first-stage-input-node <NUM>) presents a compromise between the LNA/MIXER output linearity, and the noise of the switches that compose the filters. The filter chain gain is proportional to Gm/C as the noise of the filter is proportional to sqrt(<NUM>/C). So, the lower the capacitance C at the input of the first stage, the better the signal to noise ratio (SNR). Consequently, the higher the voltage swing, the higher are intermodulation products.

A front-end low noise amplifier and mixer (not shown in <FIG>) provide charges to the input capacitor <NUM> (Ch) giving a first pole located close to zero. This is why in <FIG> and the following equation set, the input is represented by a charge Q. (Note that Yi in the following equations are voltages. ) Charge sampling happens in the first position of the filter (when the switch-node <NUM> is connected to the first-stage-input-node <NUM>). During this time, the current provided by the transimpedance of the LNA (TLNA) is integrated in time window (LO phases of interest) on the input capacitor <NUM> (Ch); it forms a continuous-time (CT) sinc-type antialiasing filter prior to sampling and filtering.

The rotating capacitor (sampling-capacitor <NUM> (Cs)) first resets by being connected to the first-stage-reset-node <NUM> (position d), and then connects to the first-stage-input-node <NUM> (position a), the first-stage-intermediate-node <NUM> (position b), a first-stage-output-node <NUM> (position d). In this example there are four positions as four LO phases are available. Each position (except the reset (d)) acts are a first order filter. Since there are three positions (excluding reset) that each provide the functionality of a first order filter, the filter order is three. In other examples, it can be possible to provide a different reset mechanism for discharging the sampling-capacitor <NUM> (Cs) such that a reset position is not required in the switching cycle for the rotating capacitor (sampling-capacitor <NUM> (Cs)) and therefore greater flexibility can be provided with setting the order of the first-stage down-sampling filter <NUM>.

The set of equations that is labelled below 'Equations I' details the different phases steps over one LO period. In <FIG> there are four steps in each LO period. We assume a differential LNA and differential filter signalling, so charges arrive at two time slots n+<NUM>/<NUM> & n+<NUM>/<NUM>. Time stamps (for the Z transform) n, n+<NUM>, n+<NUM> represent the output rate of the filter (i.e. the LO rate). Cw represents the equivalent impedance of the second stage.

The complete transfer function is complex to express in closed-form, as the second stage disconnects Cw capacitor <NUM> and reconnects Cw capacitor <NUM> at a rate that is lower than the LO rate. The proposed structure comprises a sampled multi-rate linear time varying system. Nevertheless, the equations that correspond to the two configurations of the system, clearly show that there are three poles in the transfer function.

Equations I - describing the operation of the first stage filter when sampling input using multiple phases on the LO signal:.

Capacitor Cw connects and disconnect at a lower rate than the LO rate. For example, if the ratio between the LO and the clock rate of the WTSF is K, then Cw will remains connected to first filter for n=<NUM>. K LO periods. Next round a new Cw (that has been reset) will replace the previous one, etc. So a round starts with Cw*<NUM> (no charge as it is reset) and for the next (K-<NUM>) LO period it starts each period with Cw*Y2n charges.

Equations II - Composite transfer function of the first stage filter, showing the impact of resetting the sampling capacitor:.

These two sets of equations define a time varying system interface. Cw either remains connected (without reset case) or it disconnects, and a new reset capacitor connects (with reset case). Note that if Cs>>Cw, both transfer functions become similar.

<FIG> shows an example embodiment of a second stage <NUM> that can be provided as part of any of the receiver circuits that are disclosed herein. In this example the second stage comprises a switched-capacitor circuit that is implemented as a Weighted Tapped Sampling Filter (WTSF).

The left-hand portion of <FIG> shows a circuit diagram of the second stage <NUM>. The right-hand portion of <FIG> shows a timing diagram for the second stage <NUM>.

The second stage <NUM> includes a second-stage-input-node <NUM> and a second-stage-output-node <NUM>. The second-stage-input-node <NUM> is for receiving the transition-signal. As discussed above, the transition-signal has a transition-frequency that is lower than the frequency of the first-stage-output-signal. The second-stage-output-node <NUM> is for providing the second-stage-output-signal. The second-stage-output-signal <NUM> a frequency that is suitable for the downstream ADC, and is lower than the transition-frequency.

The second stage <NUM> includes a bank of capacitors <NUM>, which is connected between the second-stage-input-node <NUM> and a second-stage-output-node <NUM>. In some examples, as will be discussed below, the second stage <NUM> may include a plurality of banks of capacitors <NUM> in parallel with each other between the second-stage-input-node <NUM> and a second-stage-output-node <NUM>.

The bank of capacitors <NUM> comprises a plurality of branches <NUM>, which are connected in parallel with each other between the second-stage-input-node <NUM> and the second-stage-output-node <NUM>. Each branch <NUM> includes:.

In <FIG> a first branch 743a and a last branch 743b are shown. Some components of the first branch 743a are labelled with a subscript '<NUM>'. Some components of the last branch 743b are labelled with a subscript 'nrot-<NUM>'. In this way, the number of branches <NUM> in the bank of capacitors <NUM> is 'nrot'. As will be appreciated from the description that follows, 'nrot' can be considered as the number of rotations in the bank of capacitors <NUM>.

The second-stage-holding-switches <NUM> of each of the branches <NUM> are operable to selectively connect the second-stage-input-node <NUM> to a respective one of the second-stage-capacitors <NUM> sequentially in turn as part of a second stage sampling mode of operation. This is illustrated by the first two plots <NUM>, <NUM> on the right-hand side of <FIG>. The two plots that are shown here correspond to the two branches <NUM>. It will be appreciated that for circuits with more than two branches <NUM> there will correspondingly be more than two plots for sampling the charge at the second-stage-input-node <NUM> on to a respective second-stage-capacitor <NUM>.

The first plot <NUM> represents a connection, by the second-stage-holding-switch <NUM> of the first branch 743a, between the second-stage-input-node <NUM> and the second-stage-intermediate-node <NUM> of the first branch 743a. The first plot <NUM> has a high value (and therefore the second-stage-input-node <NUM> is connected to the second-stage-intermediate-node <NUM> of the first branch 743a) for a first portion of a sampling period of time <NUM>. As shown in <FIG>, the duration of this first portion is Nacc*Tlo, where: Nacc is the number of LO periods for which the capacitor stays connected to the output of the first stage; and Tlo is the period of the local oscillator. While the second-stage-holding-switch <NUM> of the first branch 743a is closed, the charge at the second-stage-input-node <NUM> is stored on the second-stage-capacitor <NUM> of the first branch 743a. When the second-stage-holding-switch <NUM> of the first branch 743a is closed, the second-stage-holding-switch <NUM> of the other branches <NUM> is closed (in this example the only other branch that is shown in the first branch 743a).

When the second-stage-holding-switch <NUM> of the first branch 743a is opened (and the value of the first plot <NUM> returns to zero), the second-stage-holding-switch <NUM> of another of the branches is immediately closed. (Although there is a gap between the second-stage-holding-switch <NUM> of the first branch 743a being opened in the first plot <NUM> and the second-stage-holding-switch <NUM> of the second branch 743b being closed in <FIG>, this is schematic to indicate that second-stage-holding-switches <NUM> of one or more additional branches <NUM> could be operated in the intervening period.

The second plot <NUM> represents a connection, by the second-stage-holding-switch <NUM> of the last branch 743b, between the second-stage-input-node <NUM> and the second-stage-intermediate-node <NUM> of the last branch 743b. The second plot <NUM> has a high value (and therefore the second-stage-input-node <NUM> is connected to the second-stage-intermediate-node <NUM> of the last branch 743b) for a last portion of the sampling period of time <NUM>. The duration of the last portion of the sampling period of time <NUM> is the same as that of the first portion; i.e. Nacc*Tlo.

The total duration of the sampling period of time <NUM> is shown in <FIG> as Nrot*Nacc*Tlo, where: Nrot is the number of branches <NUM> in the bank of capacitors <NUM>; Nacc is the number of LO periods for which the capacitor stays connected to the output of the first stage; and Tlo is the period of the local oscillator.

The second-stage-discharge-switches <NUM> of each of the branches <NUM> are operable to selectively connect the second-stage-capacitors <NUM> of each of the branches <NUM> to the second-stage-output-node <NUM> at the same time as part of a second stage discharging mode of operation. The third plot <NUM> in <FIG> represents a connection, by the second-stage-discharge-switches <NUM> of each of the branches <NUM>, between the associated second-stage-intermediate-nodes <NUM> and the second-stage-output-node <NUM>. In this way, all of the second-stage-discharge-switches <NUM> are operated together to discharge the second-stage-capacitors <NUM> of each of the branches <NUM> at the same time. The second-stage-discharge-switches <NUM> are closed for a discharge period of time <NUM>, which has a duration of Nrot*Nacc*Tlo/Nups, where: Nrot*Nacc*Tlo corresponds to the sampling period of time <NUM> (as discussed above), and Nups represents the number of banks of capacitors <NUM> that should be interleaved in order to match the output data rate with the input data rate. In this example, where only one bank of capacitors <NUM> is shown, Nups equals <NUM> and therefore the discharge period of time <NUM> is the same as the sampling period of time <NUM>. Also, Nups defines the number of periods available to transfer charges and rest capacitors before re-using the bank for a new round. If this time would have been zero (immediate reset/transfer) then Nbnk=(Mrot*Nacc)/Nups. Otherwise, if an Nups period is provided for the transfer / reset operation then Nbnk=(Nort*Nacc)/Nups + <NUM>; that is the number of physical banks. In the below equation we assume that the transfer / reset are immediate.

As shown in the timing diagram in <FIG>, the second-stage-holding-switches <NUM> and the second-stage-discharge-switches <NUM> are operated to perform the second stage discharging mode of operation (as represented by the discharge period of time <NUM>) and the second stage sampling mode of operation (as represented by the sampling period of time <NUM>) sequentially in turn.

In this way, the second stage <NUM> can be composed of Nbnk interleaved banks composed of Nrot capacitors <NUM>. Each capacitor <NUM> of each bank connects for Nacc LO periods to the first stage. After Nrot*Nacc LO periods all capacitors <NUM> are charged. Total charge resulting of the sum of Nrot capacitors <NUM> are transferred to a next gain stage and the capacitors are reset in preparation for a next round.

The throughput rate for the second stage <NUM> is the ADC sampling rate. the input rate is at the LO rate, so the following rule applies: Nrot*Nacc/Nbnk = Flo/Fadc. As, the charge transfer is not instantaneous, the corrected equation is Nrot*Nacc/(Nbnk-<NUM>) = Flo/Fadc, with the time for transfer of changes to be <NUM>/Fadc.

The filter transfer function periodicity is (Flo/Nacc)*(Nbnk-<NUM>); it presents either notches or in-band rejection at (Flo/Nacc)/Nrot and sampling bumps every (Flo/Nacc)*(Nbnk-<NUM>). A purpose of the filtering in the first stage can be to provide low-pass filtering that lowers these replica bumps, especially close-in to the signal of interest to provide the anti-aliasing that is desired to meet the challenging selectivity requirements for the receiver line-up.

Note that the numbers of notches created as described must be kept low (a notch at all Fadc multiple can be particularly advantageous in some applications) in order to keep the notches wide enough to filter all frequency regions that can potentially alias in band.

Also, note that it is the combination of the filtering in both the first stage and the second stage that provides good anti-aliasing properties of the RX baseband, while decimating the switched capacitor output in the sampling domain.

Equations III - depicting the second stage transfer function and the anti-aliasing notches:
Nacc number of Tlo periods Crot connects to input
Nrot number of Crot per bank
Nbnk number of interleaved banks
Wi weigth of the rotating capacitor (FIR filter coeff) (default value = <NUM>).

The system behaves as a FIR filter clocked at Flo whose output is resampled at <MAT> <MAT> <MAT> <MAT>.

<FIG> shows frequency responses of the WTSF filter using example rectangle (<NUM>-taps) and equi-ripple windows of size <NUM> & <NUM> taps.

The second stage can also be built as a low-pass filter that would reject in-band signal aliasing. As an example, <FIG> depicts three configurations; for this purpose we assume that Fs=<NUM>, Fadc=<NUM>/<NUM>=<NUM>, and that BW=<NUM> centered at DC.

Note that the filters-coefficients for the second and third configurations <NUM>, <NUM> are not equally weighted over filter taps (i.e., no rectangular shape); their coefficients (the second-stage-capacitors <NUM> that are used in the filter banks) have been computed, in this example, with an accuracy of <NUM>/<NUM> (or <NUM>-bits quantization). Furthermore, in case the second-stage-capacitors <NUM> are much smaller in comparison with the output capacitor of the first stage, then there is no need to present fixed load (i.e. sum of all capacitor of all banks that connect at first stage output at each time stamp do not need to be constant over taps). This feature can avoid a need to add an extra "dummy" bank in the layout.

<FIG> shows a block diagram of a receiver circuit <NUM> that illustrates how a single-ended first stage <NUM> (the rotating capacitor <NUM>rd order IIR filter of <FIG>) and a single-ended second stage <NUM> (the switched capacitor weighted accumulation filters of <FIG>) are provided together to constitute a complete receiver baseband stage.

In order to provide improved anti-aliasing, the receiver circuit <NUM> of <FIG> combines two passive switched capacitor filter stages:.

In combination, these filters advantageously significantly enhance the anti-aliasing properties that are needed for low-power yet high-performance applications, such as IoT.

<FIG> shows a block diagram description of an assembly of a fully differential structure of a composite baseband filter according to an embodiment of the present disclosure. The structure of <FIG> includes in-phase and quadrature processing paths (I and Q), each of which includes two complementary processing paths (N and P). Each of these <NUM> processing paths includes a mixer <NUM>, a first stage <NUM>, a second stage <NUM> that includes two banks of capacitors in parallel with each other (BANK and BANK_Nups-<NUM>), a B2A stage <NUM> and an ADC <NUM>. Each of these components has been described in detail above, for instance with reference to <FIG>. <FIG> shows how <NUM> phases (<NUM>°, <NUM>° <NUM>°, <NUM>°) of a LO can be provided as clock signals for the mixers <NUM> and the first stage <NUM>. Furthermore, the clock signals for the second stages <NUM>, the B2A stages <NUM> and the ADCs <NUM> can be derived from the LO clock signals.

If the ADCs <NUM> are a Nyquist type, the B2A (Bank to ADC) stages <NUM> adapt the dynamic of filter output to the ADC full scale. They can also perform extra filtering. If the ADCs <NUM> are a DELTA-SIGMA type, then the B2A stages <NUM> can be skipped and the charges stored in the filter banks of the second stage <NUM> are read, directly transfer to the first integrator feedback capacitance.

In some examples DC offset compensation (DCOC) can be placed either in front of the input to the first stage <NUM>, at the inputs to the second stage <NUM>, or at the input to the B2A stages <NUM>.

Examples described herein can use a passive switched-capacitor based implementation and low-rate data converter for low power operation. Thanks to switched-capacitor techniques, the transfer function can depend only on capacitor ratio; which is relatively well controlled over process and generally presents negligible temperature deviation. Also, it is easier to layout circuit structures that are robust against mismatches. This can be considered better than switched-capacitor techniques such as Multi-Tap Direct Sampling Mixer (MTDSM) that can suffer from poor anti-aliasing and require a high-rate data converter that consumes higher power.

<FIG> and <FIG> show the frequency domain characteristics of the transfer function of the receiver path circuit <NUM> (combined filter1 + filter <NUM>) of <FIG> using a rectangular window. <FIG> is a zoomed-in view of <FIG> that is focussed on the signal of interest at <NUM>.

The following plots are shown in <FIG> and <FIG>:.

Advantageously, the second-stage-output-signal (represented by plot <NUM>) shows three good notches <NUM> at multiples of the ADC clock frequency either side of the frequency of interest (at <NUM>).

<FIG> and <FIG> depict transfer gain from LNA input to LNA output (plot <NUM>), MIXER output (plot <NUM>), INTER STAGE (plot <NUM>) and FILTER output (plot <NUM>). Note that the level at FILTER output (plot <NUM>) is measured prior to charge dump at a subsequent gain stage.

The MIXER output (plot <NUM>) shows a first order behavior. The INTER STAGE (plot <NUM>) shows the higher order (<NUM> in this particular case) filtering effect. The INTER STAGE (plot <NUM>) also depicts the time varying effect as some bumps disturb the "smoothed" curve.

The FILTER output (plot <NUM>) clearly shows the benefit of the second stage, which has a transfer function that presents extra smooth filtering and zeros at all multiple of ADC clock frequency (Flo/(Nacc*Nrot)).

<FIG> shows the combined frequency domain transfer function of the receiver path circuit <NUM> of <FIG> using weighted capacitor banks in the second stage filter.

The zoomed-in frequency domain characteristics of <FIG> show a comparison of the combined filter transfer function when various weighted capacitor coefficients are implemented in the second stage filter, as identified in the figure.

One or more of the examples described herein relate to a switched capacitor-based receiver baseband that avoids the following shortcomings of prior art switched capacitor based direct sampling mixers:.

One or more of the switched capacitor-based receiver basebands described herein can have the following attributes:.

Applications of one or more of the circuits described herein include:.

It will appreciated that various circuit / implementation level variations of the proposed two stage filtering can be used, whilst still achieving the desired functionality. These include the following, non-limiting, examples:.

Claim 1:
A receiver path circuit (<NUM>) comprising:
a first-stage-down-sampling-filter (<NUM>) configured to provide the functionality of
a first stage (<NUM>) configured to:
filter a mixer-output-signal (<NUM>) received from a mixer; and
provide a first-stage-output-signal (<NUM>); and
a down-sampler (<NUM>) configured to:
down-sample the first-stage-output-signal to provide a transition-signal (<NUM>) having a transition-frequency, wherein the transition-frequency is a lower than the frequency of the first-stage-output-signal,
wherein the first-stage-down-sampling-filter comprises a first-stage-input-node for receiving the mixer-output-signal;
a first-stage-intermediate node (<NUM>);
a first-stage input node (<NUM>)
for providing the transition-signal;
a sampling-capacitor (<NUM>);
an input-capacitor (<NUM>);
an output-capacitor (<NUM>);
an intermediate-capacitor (<NUM>);
and
a first-stage-switch (<NUM>) having a switch-node (<NUM>);
wherein:
the input-capacitor is connected between the first-stage-input-node and ground;
the sampling-capacitor is connected between the switch-node of the first-stage-switch and ground;
the intermediate-capacitor is connected between the first-stage-intermediate-node and ground;
the output-capacitor is connected between the first-stage-output-node and ground;
the first-stage-switch is operable to connect the switch-node to each of the first-stage-input-node, the first-stage-intermediate-node and the first-stage-output-node in turn, over a sampling period,
a second stage (<NUM>), which comprises a switched-capacitor circuit that is configured to:
filter and reduce the frequency of the transition-signal in order to provide a second-stage-output-signal (<NUM>) to an ADC.