Patent Description:
Memory is a common semiconductor structure. With the continuous decrease of semiconductor structure size, more memories can be integrated into the chip, which contributes to the increase of product capacity. In a dynamic random access memory (DRAM), it is necessary to write/read data to/from memory cells by using word lines and bit lines and operate on the basis of a voltage applied to the word lines.

As the DRAM capacity increases, the number of memory cells connected to one word line increases, the distance between the word lines decreases, and a speed delay problem may occur. In order to improve the delay of the word line voltage, one word line can be divided into a plurality of sub word-lines and each sub word-line can be driven by using a sub word-line driver (SWD).

However, the current word line drivers have the problems of large layout area and poor driving ability. Background may be found in <CIT> and <CIT>.

The embodiments of the present disclosure provide a word line driver. The word line driver includes a substrate, first gates and a plurality of second gates. The substrate includes an NMOS (N-Metal-Oxide-Semiconductor) area and a PMOS (P-Metal-Oxide-Semiconductor) area. The PMOS area includes a plurality of first active areas extending along a first direction, and each first active area includes a first channel area, and a first source area and a first drain area respectively located on opposite sides of the first channel area. The NMOS area and the PMOS area are arranged along a second direction. The NMOS area includes a plurality of second active areas extending along the first direction, and each second active area includes a second channel area, and a second source area and a second drain area respectively located on opposite sides of the second channel area. The each second active area further includes a third channel area, and a third source area and a third drain area respectively located on opposite sides of the third channel area. The first gates are electrically connected to a main word line. A first gate, a first source area and a first drain area constitute a pull-up transistor. A first gate, a second source area and a second drain area constitute a pull-down transistor. The pull-up transistor and the pull-down transistor are electrically connected to a same sub word-line, and an extension direction of first gates corresponding to a first active area are inclined compared with the first direction. Each second gate covers a corresponding third channel area, and a second gate, a third source area and a third drain area constitute a holding transistor. For a same holding transistor, a third drain area is electrically connected to a second drain area of a pull-down transistor, and a third source area is electrically connected to a second drain area of another pull-down transistor.

In some embodiments, each first gate extends along the second direction and covers a plurality of first channel areas and a plurality of second channel areas, and a first drain area of a pull-up transistor is electrically connected to a first drain area of a pull-down transistor, and is electrically connected to a corresponding sub word-line.

In some embodiments, the PMOS area is located on one side of the NMOS area.

In some embodiments, the NMOS area includes a first NMOS area and a second NMOS area respectively located on opposite sides of the PMOS area.

In some embodiments, the third channel area is located on one side of the second source area or the second drain area along the second direction. The third drain area of the holding transistor and a second drain area of a pull-down transistor are shared, and the third source area of the holding transistor and a second drain area of another pull-down transistor are shared.

In some embodiments, the word line driver further includes first contact structures. Each first contact structure is electrically connected to a first source area or a first drain area, and extension directions of orthographic projections, of at least a partial number of the first contact structures, on a surface of the substrate are inclined compared with the first direction.

In some embodiments, an orthographic projection, of a first contact structure near edges of a first active area, on the surface of substrate is triangular, and an extension direction of an orthographic projection, of a boundary of the first contact structure, on the substrate surface is inclined compared with the first direction, where the boundary towards a first gate.

In some embodiments, an extension direction of first gates corresponding to the second active area is inclined compared with the first direction.

In some embodiments, a length of a second active area is greater than a length of a first active area in the first direction, an angle between an extending direction of the first gates corresponding to the second active area and the first direction is a first angle, an angle between an extending direction of first gates corresponding to the first active area and the first direction is a second angle, and the first angle is less than the second angle.

In some embodiments, the word line driver further includes second contact structures. Each second contact structure is used to electrically connect to a second source area, a second drain area, and a third source area or third drain area. An extension direction of an orthographic projection, of the second contact structure, on a surface of the substrate is inclined compared with the first direction.

In some embodiments, a partial area of the orthographic projection, of the second contact structure, on the surface of the substrate is located outside a second active area.

In some embodiments, the word line driver further includes third contact structures. Each third contact structure is used to electrically connect to adjacent second active areas.

In some embodiments, a second drain area of a pull-down transistor corresponding a first gate and a third drain area of the holding transistor are shared, and a second drain area of another pull-down transistor corresponding the same first gate and a third source area of the same holding transistor are shared.

In some embodiments, a second drain area of a pull-down transistor corresponding to a first gate and a third drain area of the holding transistor are shared, and a second drain area of a pull-down transistor corresponding to another first gate and a third source area of the same holding transistor are shared.

In some embodiments, a second gate is located between adjacent first gates.

In some embodiments, the holding transistor includes a first transistor and a second transistor. Two pull-down transistors electrically connected to a same first transistor share a first gate. For a same second transistor, a third drain area is electrically connected to a second drain area of a pull-down transistor and a third source area is electrically connected to a second drain area of another pull-down transistor. Two pull-down transistors electrically connected to a same second transistor correspond to two first gates.

In some embodiments, the NMOS area includes a first NMOS area and a second NMOS area that are respectively located at opposite sides of the PMOS area. The first transistor is located in the first NMOS area, the second transistor is located in the second NMOS area, a part number of pull-down transistors are located in the first NMOS area, and a remaining number of the pull-down transistors are located in the second NMOS area.

In some embodiments, each first gate includes at least two extension portions arranged at intervals along the first direction and a connecting portion. Each extension portion covers a plurality of first channel areas and a plurality of second channel areas, and is inclined compared with the first direction. The connecting portion connects extension portions arranged adjacent to each other in the first direction.

In some embodiments, a first gate covers <NUM>×N first channel areas and <NUM>×N second channel areas, and pull-up transistors and pull-down transistors composed of each first gate are electrically connected to <NUM>×N holding transistors. Where, N is a positive integer greater than or equal to <NUM>.

Accordingly, the embodiments of the present disclosure also provide a memory device. The memory device includes a memory cell array and a word line driver provided by any of the above embodiment. A memory cell array includes a plurality of memory cells connected to a plurality of sub word-lines and a plurality of bit lines.

In the technical solution of the word line driver provided by the embodiments of the present disclosure, the word line driver includes a plurality first active area. Each first active area includes a first channel area, a first source area and a first drain area. The first gates are electrically connected to a main word line. A first gate, a first source area and a first drain area constitute a pull-up transistor. A first gate, a second source area and a second drain area constitute a pull-down transistor. The pull-up transistor and the pull-down transistor are electrically connected to a same sub word-line, so that the pull-up transistor and the pull-down transistor can respectively transmit a driving signal to the sub word-line through the first drain area, thereby controlling the driving and closing of the sub word-line. The word line driver further includes a plurality of second gates. A second gate covers a third channel area. A second gate, a third source area and a third drain area form a holding transistor. A third drain area and a third source area of the holding transistor are electrically connected to the second drain areas of two different pull-down transistors. That is, two pull-down transistors share a same holding transistor. In this way, when a sub word-line connected to a pull-down transistor is driven, the holding transistor can control the sub word-line connected to the other pull-down transistor to be in an unselected state at the same time to decrease the area occupied by the holding transistor in a case of maintaining the performance of the word line driver unchanged, thereby decreasing the layout area of the word line driver. In addition, the extension direction of the first gates corresponding to a first active area is set to be inclined compared with the extension direction of the first active areas, so that the first gates in the first active area have a larger size, which is equivalent to increasing the channel size of the pull-up transistor, thereby improving the driving ability of the first gate to the pull-up transistor.

One or more embodiments are exemplarily described by the pictures in the corresponding appended drawings. These exemplary descriptions do not constitute a limitation on the embodiments. The figures in the drawings do not constitute a limitation of scale unless specifically stated. To more clearly explain the embodiments of the present disclosure or the technical solution in the conventional technique, the drawings needed to be used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative effort for an ordinary skilled person in the art.

It can be seen from the background technology that the current word line driver has the problems of large layout area and poor driving ability. Through analysis, one of the reasons for the large layout area of the current word line driving circuit is that, referring to <FIG> and <FIG>, currently, the word line driving circuit includes at least one sub word-line driver, and the sub word-line driver is connected to a main word line MWLb and a sub word-line WL. The sub word-line driver further includes a holding transistor. A first end of the holding transistor <NUM> is connected to the sub word-line WL, and the other end of the holding transistor <NUM> is coupled to the low level VKK. The sub word-line driver receives an enable signal and a driving signal PXID, and supplies the driving signal PXID to the sub word-line WL to drive the sub word-line WL. When the sub word-line WL is not needed to be selected, the first end and the second end of the holding transistor can be conductive in response to the enable signal, the driving signal PXID, and the driving signal PXIB, so that the first end of the holding transistor <NUM> is coupled to the low level VKK, and further the sub word-line WL connected to the first end of the holding transistor <NUM> is also pulled low to the low level VKK to close the sub word-line WL. That is, one holding transistor is only used to control one sub word-line so that the sub word-line remains in an unselected state. As can be seen from <FIG>, when two main word lines (denoted as MWLb1 and MWLb2 respectively) are included in the word line driving circuit, each main word line corresponds to two sub word-line drivers SWD respectively, each holding transistor is electrically connected to one sub word-line (a plurality of sub word-lines are denoted as WL0 to WL15 in the figure), so that the sub word-line drivers are respectively responsive to the corresponding driving signal PXIB and the corresponding driving signal PXID to control the closing of the sub word-lines, which occupies more space in the word line driving circuit layout.

In addition, when the layout area of the word line driver is decreased, it is likely that the overall size of the pull-up transistors, the pull-down transistors, or the holding transistors is reduced, so that the channel area of the pull-up transistor, the pull-down transistor, or the holding transistor is decreased, thereby reducing the driving capability of the word line driver.

Embodiments of the present disclosure provide a word line driver. The word line driver includes a plurality first active area. Each first active area includes a first channel area, a first source area and a first drain area. A first gate, a first source area and a first drain area constitute a pull-up transistor. The first drain area of the pull-up transistor is electrically connected to the second drain area of the pull-down transistor, and is electrically connected to the corresponding sub word-line, so that the pull-up transistor and the pull-down transistor can respectively transmit a driving signal to the sub word-line through the first drain area and the second drain area, thereby controlling the driving and closing of the sub word-line. A third drain area and a third source area of the holding transistor are set to electrically connect to the second drain areas of two different pull-down transistors. That is, two pull-down transistors share a same holding transistor. In this way, when a sub word-line connected to a pull-down transistor is driven, the holding transistor can control the sub word-line connected to the other pull-down transistor to be in an unselected state at the same time to decrease the area occupied by the holding transistor in a case of maintaining the performance of the word line driver unchanged, thereby decreasing the layout area of the word line driver. In addition, the extension direction of the first gates corresponding to a first active area is set to be inclined compared with the extension direction of the first active areas, so that the first gates in the first active area have a larger size, which is equivalent to increasing the channel size of the pull-up transistor, thereby improving the driving ability of the first gate to the pull-up transistor.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understood that in various embodiments of the present disclosure, numerous technical details have been presented in order to enable the reader to better understand the present disclosure. However, even without these technical details and various variations and modifications based on the following embodiments, the claimed technical solutions of the present disclosure may be implemented.

<FIG> is a schematic diagram of the layout structure of the first word line driver provided by the embodiments of the present disclosure. <FIG> is a schematic diagram of the layout structure of the second word line driver provided by the embodiments of the present disclosure.

Referring to <FIG>, the word line driver includes a substrate, first gates <NUM> and a plurality of second gates <NUM>. The substrate includes an NMOS (N-Metal-Oxide-Semiconductor) area <NUM> and a PMOS (P-Metal-Oxide-Semiconductor) area <NUM>. The PMOS area <NUM> includes a plurality of first active areas <NUM> extending along a first direction X, and each first active area <NUM> includes a first channel area, and a first source area <NUM> and a first drain area <NUM> respectively located on opposite sides of the first channel area. The NMOS area <NUM> and the PMOS area <NUM> are arranged along a second direction Y. The NMOS area <NUM> includes a plurality of second active areas <NUM> extending along the first direction X, and each second active area <NUM> includes a second channel area <NUM>, and a second source area <NUM> and a second drain area <NUM> respectively located on opposite sides of the second channel area <NUM>. Each second active area <NUM> further includes a third channel area, and a third source area <NUM> and a third drain area respectively located on opposite sides of the third channel area. The first gates <NUM> are electrically connected to a main word line. A first gate <NUM>, a first source area <NUM> and a first drain area <NUM> constitute a pull-up transistor. A first gate <NUM>, a second source area <NUM> and a second drain area <NUM> constitute a pull-down transistor. The pull-up transistor and the pull-down transistor are electrically connected to a same sub word-line, and an extension direction of first gates <NUM> corresponding to a first active area <NUM> are inclined compared with the first direction X. Each second gate <NUM> covers a corresponding third channel area, and a second gate <NUM>, a third source area <NUM> and a third drain area constitute a holding transistor. For a same holding transistor, a third drain area is electrically connected to a second drain area <NUM> of a pull-down transistor, and a third source area <NUM> is electrically connected to a second drain area <NUM> of another pull-down transistor.

The pull-up transistor and the pull-down transistor are electrically connected to the sub word-line, so that driving and closing of the sub word-line can be controlled. Specifically, in some embodiments, each first gate <NUM> extends along a second direction Y and covers a plurality of first channel areas and a plurality of second channel areas <NUM>. A first drain area of a pull-up transistor is electrically connected to a second drain area of a pull-down transistor and is electrically connected to a corresponding sub word-line. That is to say, a same sub word-line is electrically connected to a first drain area of a pull-up transistor and a second drain area of a pull-down transistor at the same time, so that the pull-up transistor may transmit a driving signal to the sub word-line through the first drain area to drive the sub word-line, and the pull-down transistor may transmit the driving signal to the sub word-line through the second drain area to close the sub word-line.

A third drain area and a third source area <NUM> of a holding transistor are set to electrically connect to second drain areas <NUM> of two different pull-down transistors, so that two pull-down transistors share a same holding transistor. In this way, when a sub word-line connected to one of the two pull-down transistors is driven, the holding transistor can control the sub word-line connected to the other pull-down transistor to be in an unselected state at the same time to decrease the layout area of the word line driver in a case of maintaining the performance of the word line driver unchanged. In addition, the extension direction of the first gates <NUM> corresponding to a first active area <NUM> is set to be inclined compared with the extension direction of the first active areas <NUM>, so that the first gates <NUM> in the first active area <NUM> have a larger size, which is equivalent to increasing the channel size of the pull-up transistor, thereby improving the driving ability of the first gate <NUM> to the pull-up transistor.

In some embodiments, the material of the substrate is a semiconductor material. Specifically, in some embodiments, the material of the substrate is silicon. In other embodiments, the substrate may be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon substrate on an insulator.

The PMOS area <NUM> is used for forming PMOS transistors, and the pull-up transistor is located in the PMOS area <NUM>. That is, the pull-up transistor is a PMOS transistor. The NMOS area <NUM> is used for forming NMOS transistors, and the pull-down transistor is located in the NMOS area <NUM>, such that the pull-down transistor is an NMOS transistor. The first drain area <NUM> is used for forming the drain of the pull-up transistor, and the second drain area <NUM> is used for forming the drain of the pull-down transistor. The first drain area <NUM> of the pull-up transistor is electrically connected to the second drain area <NUM> of the pull-down transistor, and the first drain area <NUM> and the second drain area <NUM> are also electrically connected to a sub word-line, respectively. Thus, a driving signal for driving the sub word-line may be transmitted through the source of the pull-up transistor to the drain of the pull-up transistor and be input to the sub word-line to control the driving of the sub word-line. A driving signal for closing the sub word-line may be transmitted through the source of the pull-down transistor to the drain of the pull-down transistor and be input to the sub word-line to control the closing of the sub word-line. Moreover, since the pull-up transistor and the pull-down transistor are different types of transistors, the pull-down transistor is closed when the pull-up transistor is conductive, so that the pull-up transistor may be used to drive sub word-line, and the pull-up transistor is closed when the pull-down transistor is conductive, so that the pull-down transistor may be used to drive the sub word-line. That is, the pull-up transistor and the pull-down transistor may be used to drive and close the sub word-line, respectively.

It should be understood that a pull-up transistor and a pull-down transistor may be used to form a sub word-line driver <NUM> for driving and closing a sub word-line. Since the pull-up transistor and the pull-down transistor are different types of transistors, and the pull-up transistor is located in the PMOS area <NUM> and the pull-down transistor is located in the NMOS area <NUM>, in some embodiments, the sub word-line driver <NUM> further includes a metal layer for electrically connecting the first drain area <NUM> of the pull-up transistor and the second drain area <NUM> of the pull-down transistor. Specifically, in some embodiments, the metal layer and the first drain area <NUM> may be electrically connected by a conductive plug, and the metal layer and the second drain area <NUM> also may be electrically connected by a conductive plug.

The first gates <NUM> may serve as a main word line, and serve as gates of a plurality of pull-up transistors and a plurality of pull-down transistors at the same time, so that a plurality of pull-up transistors and a plurality of pull-down transistors may drive a plurality of sub word-line in response to an enable signal provided by the first gates <NUM>.

The third drain area is used as the drain of the holding transistor, the third source area <NUM> is used as the source of the holding transistor, and the third source area <NUM> and the third drain area of the same holding transistor are respectively electrically connected to the second drain areas <NUM> of two different pull-down transistors. That is, the source and drain of the same holding transistor are respectively connected to the drains of two different pull-down transistors. Since the drains of the two different pull-down transistors are further connected to two different sub word-lines, the source and drain of the same holding transistor are further electrically connected to the two different sub word-lines, so that one holding transistor may have a function of keeping the voltage of the two different sub word-lines stable. That's because the word line driver can drive only one sub word-line at the same time. For example, if the number of sub word-lines is <NUM>, when one of the sub word-lines connected to the holding transistor is selected, the other sub word-line is in an unselected state. When the selected sub word-line needs to be closed, the source and drain of the holding transistor are conductive, so that the level of the selected sub word-line is pulled to be coincided with the level of the unselected sub word-line, thereby ensuring that the selected sub word-line may be completely closed.

Compared with a holding transistor for controlling one sub word-line, in the embodiments of the present disclosure, the source and drain of a holding transistor are respectively electrically connected to two sub word-lines, thereby being used for controlling the two sub word-lines, thereby greatly decreasing the number of holding transistors in a word line driver and further decreasing the layout area of the word line driver.

An extension direction of the first gates <NUM> corresponding to a first active area <NUM> is set to be inclined compared with the first direction X. That is, the extension direction of the first gates <NUM> corresponding to a first active area <NUM> is inclined compared with the extension direction of the first active areas <NUM>. Comparing with the first gates <NUM> extending perpendicularly to the extension direction of the first active areas <NUM>, the length of the first gate <NUM> is greater, so that the size of the first gate <NUM> may be increased. In this way, the contact area between the first gate <NUM> and the channel area is increased, so that the channel size of the formed pull-up transistor is increased, so that the driving and controlling ability of the first gate <NUM> to the pull-up transistor can be improved. Thus, the driving capability of the word line driver is increased while decreasing the layout area of the word line driver.

Referring to <FIG>, in some embodiments, the word line driver further includes first contact structures <NUM>. Each first contact structure is electrically connected to the first source area <NUM> or the first drain area <NUM>. Extension directions of orthographic projections, of at least a part number of the first contact structures <NUM>, on a surface of the substrate are inclined compared with the first direction X. The first contact structure <NUM> is electrically connected to the first source area <NUM> or the first drain area <NUM>, so that the first contact structure <NUM> may provide an external electrical signal to the pull-up transistor. On the other hand, it may also be used to draw out the electrical signal of the pull-up transistor. Compared with setting the extension direction of orthographic projection, of the first contact structure <NUM>, on a surface of the substrate to be perpendicular to the first direction X (that is, perpendicular to the extension direction of the first active areas <NUM>), the first contact structure <NUM> is set to be inclined compared with the extension direction of the first active areas <NUM>, so that the length of the first contact structure <NUM> in the extension direction is increased, thereby increasing the size of the first contact structure <NUM>, facilitating the decreasing of the resistance of the first contact structure <NUM>, increasing the speed for transmitting the electrical signal by the first contact structure <NUM>, further increasing the starting speed of the pull-up transistor, and further improving the driving capability of the pull-up transistor to the sub word-line.

The extension direction of the first contact structures <NUM> may be the same as the extension direction of the first gates <NUM> corresponding to the first active areas <NUM>, so that the first contact structures <NUM> and the first gates <NUM> may be prevented from having a problem of crossing lines.

In some embodiments, the material of the first contact structure <NUM> may be any one of copper, aluminum or tungsten.

Referring to <FIG>, in some embodiments, an orthographic projection, of a first contact structure <NUM> near an edge of a first active area <NUM>, on the surface of substrate is triangular. An extension direction of an orthographic projection, of a boundary of the first contact structure <NUM>, on the substrate surface is inclined compared with the first direction X, the boundary towards a first gate <NUM>. Herein, the edge position of the first active area <NUM> refers to the edge position of the first active area <NUM> in the first direction X. In some embodiments, the shape of the first active area <NUM> is rectangular. When the first gates <NUM> of the first active area <NUM> are inclined compared with the extension direction of the first active areas <NUM>, the edge position of the first active area <NUM> has more free space, and the first gate <NUM> and edges of the first active area <NUM> form a triangular area. Based on this, the orthographic projection, of the first contact structure <NUM> near the edge of the first active area <NUM>, on the surface of the substrate is set to be triangular, so that the shape of the first contact structure <NUM> is adapted to the shape of the triangular area. The free space of the first active area <NUM> may be fully utilized, so that the size of the first contact structure <NUM> reaches a larger level in the available space, thereby decreasing the resistance of the first contact structure <NUM>, thereby further increasing the speed for transmitting the electrical signal by the first contact structure <NUM> and improving the driving capability of the pull-up transistor to the sub word-line.

It should be understood that the first contact structure <NUM> located between two adjacent first gates <NUM> may be rectangular, and the extension direction of the first contact structures <NUM> is the same as that of the first gates <NUM>, so that the first contact structures <NUM> and the first gates <NUM> may be prevented from having a problem of crossing lines.

With continued reference to <FIG>, in some embodiments, the extension direction of the first gates <NUM> corresponding to a second active area <NUM> is inclined compared with the first direction X. That is, the extension direction of the first gates <NUM> corresponding to a second active area <NUM> is inclined compared with the extension direction of the second active areas <NUM>. While the extension direction of the first gates <NUM> corresponding to a first active area <NUM> is inclined compared with the extension direction of the first active areas <NUM>, the extension direction of the first gates <NUM> of a second active area <NUM> is set to be inclined compared with the direction of the second active areas <NUM>, so that the length of the first gate <NUM> of the second active area <NUM> is also greater, thereby increasing the length of the first gate <NUM> of the second active area <NUM>. Since the first gate <NUM> of the second active area <NUM> is used to form the pull-down transistor, the channel size of the formed pull-down transistor is correspondingly increased, the driving capability and the control capability of the first gate <NUM> to the pull-down transistor are improved, and the speed of closing the sub word-line by word line driver is increased.

The first active area <NUM> is located in the PMOS area <NUM> and is used for forming a pull-up transistor, and the second active area <NUM> is located in the NMOS area <NUM> and is used for forming a pull-down transistor and a holding transistor. The number of pull-up transistors is the same as the number of pull-down transistors, and the number of the holding transistors is half of the number of pull-down transistors. That is, the number of transistors formed in the first active area <NUM> is greater than the number of transistors formed in the second active area <NUM>. That is, the number of holding transistors is additional. Thus, compared with the second active area <NUM>, third channel area needs to be formed in the first active area <NUM>. In order to provide more space for forming the third channel area, in some embodiments, the length of the second active area <NUM> is longer than the length of the first active area <NUM> in the first direction X, such that the second active area <NUM> may form a plurality of second channel areas <NUM> and a plurality of third channel area in the first direction X, thereby forming a plurality of pull-down transistors and a plurality of holding transistors.

Referring to <FIG>, in some embodiments, an inclined angle between an extending direction of the first gates <NUM> corresponding to a second active area <NUM> and the first direction X is a first angle I, and an inclined angle between an extending direction of first gates <NUM> corresponding to a first active area <NUM> and the first direction X is a second angle II, and the first angle I is less than the second angle II. Since the length of the second active area <NUM> is longer than the length of the first active area <NUM> in the first direction X, it is necessary to set the overall size of the second active area <NUM> not to be too great in order to keep the overall size of the sub word-line driver less. Therefore, it is necessary to set the width of the second active area <NUM> less in the second direction Y. It should be understood that when the width of the second active area <NUM> in the second direction Y is constant, the less the inclined angle between an extending direction of the first gates <NUM> corresponding to the second active area <NUM> and the first direction X is, that is, the less the first angle is, the extension direction of the first gates <NUM> is closer to being parallel to the first direction X, so that the length of the first gate <NUM> will be greater, thereby increasing the size of the first gate <NUM> and increasing the driving capability for the pull-down transistor. Therefore, the first angle is set to be less than the second angle, so that the difference between the size of the first gate <NUM> corresponding to the second active area <NUM> and the size of the first gate <NUM> corresponding to the first active area <NUM> is not too great, so that the driving ability of the first gate <NUM> to both the pull-up transistor and the pull-down transistor is strong.

In addition, when the first gate <NUM> is used to form a plurality of pull-down transistors, the number of second channel areas <NUM> covered by the first gate <NUM> in the second active area <NUM> is great, and the plurality of second channel areas <NUM> are arranged at intervals in the second direction Y. Based on this, when the first gate <NUM> in the second active area <NUM> needs to cover a plurality of second channel areas <NUM>, the first gates <NUM> corresponding to two adjacent second channel areas <NUM> are connected and have an included angle with each other. Since the width of the second active area <NUM> in the second direction Y is less, the angle between the first gates <NUM> corresponding to the two adjacent second channel areas <NUM> is less. Thus, an inclined angle between an extending direction of the first gates <NUM> corresponding to the second active area <NUM> and the first direction X is less, that is, the first angle is less, which is beneficial to adapting to the second active area <NUM> with a less size, and improving the driving capability of the word line driver under the condition of decreasing the layout area of the word line driver.

In some embodiments, the word line driver further includes second contact structures <NUM>. Each second contact structure is used to electrically connect to a second source area <NUM>, a second drain area <NUM>, a third source area <NUM> or a third drain area. An extension direction of an orthographic projection, of the second contact structure <NUM>, on a surface of the substrate is inclined compared with the first direction X. The second contact structure <NUM> is electrically connected to the second source area <NUM>, the second drain area <NUM>, the third source area <NUM> or the third drain area, so that the second contact structure <NUM> may provide an external electrical signal to the pull-down transistor and the holding transistor. Comparing with setting the second contact structure <NUM> to be perpendicular to the direction of extension of the second active areas <NUM>, the second contact structure <NUM> is set to be inclined compared with an extension direction of the second active areas <NUM>, so that the length of the second contact structure <NUM> in the extension direction is increased, thereby increasing the size of the second contact structure <NUM>, facilitating the decreasing of the resistance of the second contact structure <NUM>, speeding up the speed for transmitting the electrical signal by the second contact structure <NUM>, further increasing the starting speeds of the pull-down transistor and the holding transistor, and improving the closing speed to the sub word-line by the word line driver.

The extension direction of the second contact structures <NUM> may be the same as the extension direction of the first gates <NUM> corresponding to a second active area <NUM>, so that the second contact structures and the first gates <NUM> in the second active areas <NUM> may be prevented from having a problem of crossing lines.

In some embodiments, the material of the second contact structure <NUM> may be the same as the material of the first contact structure <NUM>, so that the first contact structure <NUM> and the second contact structure <NUM> may be formed simultaneously in the same process step, which is beneficial to save process flow.

Referring to <FIG>, in some embodiments, partial area of the orthographic projection, of the second contact structure <NUM>, on the surface of the substrate is located outside of a second active area <NUM>. That is, the second contact structure <NUM> extends to the outside of the second active area <NUM>. Compared with the fact that the second contact structure <NUM> is only located inside of the second active area <NUM>, the length size of the second contact structure <NUM> in the extension direction is increased, thereby increasing the volume of the second contact structure <NUM>, which is beneficial to decreasing the resistance of the second contact structure <NUM> and increasing the transmission speed of the second contact structure <NUM> for electrical signals.

In some embodiments, the second active area <NUM> where the second contact structure <NUM> is located may also extend outward, and the second contact structure <NUM> is located on the second active area <NUM> that is outward extended, so that the contact area between the second contact structure <NUM> and the second source area <NUM>, the second drain area <NUM>, the third source area <NUM> or the third drain area is increased, the contact resistance is decreased, and the signal delay is reduced.

In some embodiments, the word line driver further includes third contact structures <NUM>. Each third contact structure <NUM> is used to electrically connect to adjacent second active areas. The third contact structure <NUM> is located between two adjacent second active areas <NUM>, and may be used to electrically connect to the second source area <NUM> and to electrically connect to the ground, so that a low-level driving signal is provided to the pull-down transistor to close the sub word-line. The third contact structure <NUM> is set to electrically connect the adjacent second active areas <NUM>, that is, two pull-down transistors of the adjacent two second active areas <NUM> may share the same third contact structure <NUM>, so that the occupied area of the third contact structure <NUM> may be decreased and the layout area may be decreased. In addition, since the third contact structure <NUM> spans the distance between the two second active areas <NUM>, the size of the third contact structure <NUM> is great. Thus, the resistance of the third contact structure <NUM> may be less, so that the transmission speed of the third contact structure <NUM> for the electrical signal is fast. That is, a strong driving capability of the pull-down transistor is kept while decreasing the layout area of the second active area <NUM>.

Referring to <FIG>, in some embodiments, the PMOS area <NUM> may be located on one side of the NMOS area <NUM>. The first drain area <NUM> in the PMOS area <NUM> corresponds to the second drain area <NUM> in the NMOS area <NUM>. That is, each first drain area <NUM> in the PMOS area <NUM> is electrically connected to each second drain area <NUM> in the NMOS area <NUM>, so that the drain of one pull-up transistor is electrically connected to the drain of the other pull-down transistor. Only one PMOS area <NUM> and one NMOS area <NUM> are set, and are used for forming pull-up transistors, pull-down transistors and holding transistors. Thus, when the pull-up transistors, the pull-down transistors and the holding transistors are manufactured in practice, the substrate in the same area may be doped to form the first active areas <NUM> and the second active areas <NUM>, and the pull-down transistors and the holding transistors may be formed in the same step, which is beneficial to simplifying the manufacturing process.

Referring to <FIG> and <FIG>, in other embodiments, the NMOS area <NUM> may include a first NMOS area <NUM> and a second NMOS area <NUM> respectively located on opposite sides of the PMOS area <NUM>. A part number of pull-down transistors are located in the first NMOS area <NUM> and the remaining part number of pull-down transistors is located in the second NMOS area <NUM>. Considering the complexity of layout design, the NMOS area <NUM> is divided into a first NMOS area <NUM> and a second NMOS area <NUM>, thereby flexibly adjusting the layout position of the NMOS area <NUM>, which is beneficial to improving the rationality of layout.

In some embodiments, referring to <FIG>, when the NMOS area <NUM> includes the first NMOS area <NUM> and the second NMOS area <NUM> located on opposite sides of the PMOS area <NUM>, only the extension direction of the first gates <NUM> corresponding to the first active areas <NUM> in the PMOS area <NUM> may be inclined compared with the first direction X, and the extension direction of the first gates <NUM> corresponding to the second active areas <NUM> in the first NMOS area <NUM> and the second NMOS area <NUM> is perpendicular to the first direction X.

In other embodiments, referring to <FIG>, when the NMOS area <NUM> includes the first NMOS area <NUM> and the second NMOS area <NUM> located on opposite sides of the PMOS area <NUM>, the extension directions of the first gates <NUM> in the PMOS area <NUM> and the first gates <NUM> in the first NMOS area <NUM> and the second NMOS area <NUM> may be inclined compared with the first direction X, thereby greatly increasing the overall size of the first gate <NUM>.

With continued reference to <FIG>, in some embodiments, a second drain area <NUM> of a pull-down transistor corresponding to a first gate <NUM> and a third drain area of a holding transistor are shared, and a second drain area <NUM> of a pull-down transistor corresponding to another first gate <NUM> and a third source area <NUM> of the same holding transistor are shared. That is, the second gate <NUM> is located on the surface of the third channel area, and forms a holding transistor with a second drain area <NUM> of the pull-down transistor and a second drain area <NUM> of the other pull-down transistor. Thus, the area of the second active area <NUM> may be decreased, thereby decreasing the layout area of the word line driver.

Specifically, in some embodiments, the second gate <NUM> is located between adjacent first gates <NUM>. That is, the third channel area is located on one side of the second source area <NUM> or the second drain area <NUM> along the first direction X. Since the second gate <NUM> is located between two adjacent first gates <NUM>, and the first gates <NUM> on two sides of the second gate <NUM> are respectively used to form two different pull-down transistors, so that the holding transistor is electrically connected to the pull-down transistors corresponding to the two different first gates <NUM> respectively. The second drain area <NUM> on one side of the third channel area may be used as a drain of a pull-down transistor corresponding to a first gate <NUM>, and the second drain area <NUM> on the other side of the third channel area may be used as a drain of a pull-down transistor corresponding to another first gate <NUM>. In some embodiments, two adjacent pull-down transistors corresponding to the same first gate <NUM> may also share the second source area <NUM>, thereby further decreasing the layout area of the word line driver.

Specifically, the reference of the word line driving circuit corresponding to the word line driver in <FIG> is made to <FIG>. The word line driving circuit includes at least two sub word-line drivers <NUM>. Each sub word-line driver is connected to a main word line and a sub word-line, and the main word line is used for providing an enable signal. The first end and the second end of the holding transistor <NUM> are respectively connected to different sub word-lines. The two sub word--lines connected to the first end and the second end of the holding transistor <NUM> correspond to different main word lines, respectively. The gate of the holding transistor <NUM> receives the second driving signal PXIB. The gate of the pull-up transistor <NUM> is connected to the main word line. The source of the pull-up transistor <NUM> receives the first driving signal PXID. The drain of the pull-up transistor <NUM> is connected to the sub word-line and the first end or the second end of the holding transistor <NUM>. The gate of the pull-down transistor <NUM> is connected to the main word line. The drain of the pull-down transistor <NUM> is connected to the drain of the pull-up transistor <NUM>. The source of the pull-down transistor <NUM> receives the third driving signal VKK. The sub word-line driver <NUM> is configured to provide, in response to the first driving signal PXID and the enable signal, a first driving signal PXID to a selected sub word-line which is a sub word-line connected to a first end or a second end of the holding transistor <NUM>, and to conduct, in response to the first driving signal PXID, the enable signal, and the second driving signal PXIB, the first end and the second end of the holding transistor <NUM>.

That is, the two main word lines may share the same holding transistor <NUM>, and the word line driver conducts the first end and second end of the holding transistor <NUM> in response to the first driving signal PXID, the enable signal, and the second driving signal PXIB, so that the level of the selected sub word-line is pulled to be coincided with the level of the unselected sub word-line to close the selected word line. That is, when the sub word-line connected to one end of the holding transistor <NUM> is driven, the holding transistor <NUM> may cause the sub word-line connected to the other end of the holding transistor <NUM> to be in an unselected state, thereby decreasing the area occupied by the word line driving circuit and decreasing the layout area of the word line driving circuit under a condition of keeping the performance of the word line driving circuit unchanged.

Since a sub word-line driver <NUM> is connected to a sub word-line, and a holding transistor <NUM> is connected to two different sub word-lines respectively, in the word line driving circuit, the number of sub word-line drivers <NUM> is twice the number of holding transistors <NUM>. That is, two sub word-lines connected to a holding transistor <NUM> are also connected to two sub word-line drivers <NUM>, respectively.

It should be noted that in the word line driving circuit, when one of the word line drivers drives the sub word-line connected thereto, the sub word-lines connected to the remaining sub word-line drivers <NUM> are all in an unselected state. That is, only one sub word-line may be selected at a same moment in the word line driving circuit. Therefore, when the sub word-line connected to one of the first end or the second end of the holding transistor <NUM> is selected, the sub word-line connected to the other of the first end or the second end of the holding transistor <NUM> is in an unselected state. Thus, when the first end and the second end of the holding transistor <NUM> are conductive, the level of the sub word-line connected to the first end of the holding transistor <NUM> is pulled to be coincided with the level of the sub word-line connected to the second end of the holding transistor <NUM>, so that the level of the selected sub word-line is pulled down to be coincided with the level of the unselected sub word-line, and the selected sub word-line is in a closed state.

The pull-up transistor <NUM> pulls up the sub word-line to the level of the first driving signal PXID in response to the enable signal and the first driving signal PXID, and the sub word-line is driven in response to the first driving signal PXID. The pull-down transistor <NUM> pulls down the sub word-line to the level of the third driving signal VKK in response to the enable signal, and the sub word-line is closed in response to the third driving signal VKK. In some embodiments, the first driving signal PXID may be at a high level and the third driving signal VKK may be at a low level. For example, the voltage of the third driving signal VKK may be <NUM> or less than <NUM>.

The pull-up transistor <NUM> includes a PMOS transistor. The pull-down transistor <NUM> includes an NMOS transistor. The holding transistor <NUM> includes an NMOS transistor. That is, the pull-up transistor <NUM> is conductive in response to a low-level signal, and the pull-down transistor <NUM> is conductive in response to a high-level signal, so that the pull-up transistor <NUM> and the pull-down transistor <NUM> may not be interfered with each other, and may control the driving and closing of sub word- lines, respectively.

Specifically, when the pull-up transistor <NUM> is a PMOS transistor, the pull-down transistor <NUM> is an NMOS transistor, and the holding transistor <NUM> includes an NMOS transistor, the operation principle of the word line driving circuit is as follows.

Two sub word-line drivers <NUM> are designated as a first sub word-line driver and a second sub word-line driver, respectively, a sub word-line connected to the first end of the holding transistor <NUM> is designated as a first sub word-line, and a sub word-line connected to the second end of the holding transistor <NUM> is designated as a second sub word-line. The first sub word-line is connected to the first sub word-line driver and the second sub word-line is connected to the second sub word-line driver.

The first sub word-line driver drives the first sub word-line, and at this time, the second sub word-line is in an unselected state.

The first sub word-line driver drives the first sub word-line in response to an enable signal of a low level, a first driving signal PXID of a high level, and a second driving signal PXIB of a low level. Specifically, the pull-up transistor <NUM> is conductive in response to an enable signal of a low level, the first driving signal PXID of the high level is transmitted from the source of the pull-up transistor <NUM> to the drain of the pull-up transistor <NUM>. At the same time, the holding transistor <NUM> is closed in response to the second driving signal PXIB of the low level, so that the level of the first sub word-line is pulled up to the first driving signal PXID and has a high level, thereby the first sub word-line is driven.

The first sub word-line driver closes the first sub word-line in response to an enable signal of a high level, a first driving signal PXID of a low level, and a second driving signal PXIB of a high level. The pull-down transistor <NUM> is conductive in response to an enable signal of a high level, and the pull-up transistor <NUM> is closed in response to an enable signal of a low level. A third driving signal VKK is transmitted from the source of the pull-down transistor <NUM> to the drain of the pull-down transistor <NUM>, so that the level of the first sub word-line is pulled down to the third driving signal VKK, and the first sub word-line has a low level. At the same time, the holding transistor <NUM> is conductive in response to the second driving signal PXIB of the high level, so that the level of the first sub word-line coincides with the level of the second sub word-line. Since the second sub word-line is in the unselected state, it is ensured that the first sub word-line is closed and thus the first sub word-line becomes the unselected state.

The principle of the second sub word-line driver driving the second sub word-line and closing the sub word-line is the same as that of the first sub word-line driver, and will not be described in detail below. It should be noted that since the first sub word-line driver and the second sub word-line driver correspond to the same holding transistor <NUM>, when the selected second sub word-line is needed to be closed, the level of the second sub word-line may be pulled down to the level of the first sub word-line by conducting the first end and the second end of the holding transistor <NUM>, so that the second sub word-line is closed. That is to say, a holding transistor <NUM> may be set to connect to two different sub word-lines to control the closing of the two sub word-lines.

It should be understood that since the enable signal or the third driving signal VKK may have a problem of instability, or since the word line driving circuit may be disturbed by external noise, the level of the sub word-line may not be less than <NUM>. The sub word-line may not be completely closed only by the third driving signal VKK. In the embodiments of the present disclosure, since the first end and the second end of the holding transistor <NUM> are set to be connected to two different sub word-lines, when the first end and the second end of the holding transistor <NUM> are conductive, the voltage of the selected word line will be pulled down to be coincided with the voltage of the unselected word line. That is, the voltage of the selected word line may be coupled to the level of the negative voltage by the holding transistor <NUM>, so that the selected word line is closed. Therefore, no matter how the level of the enable signal or of the third driving signal VKK changes, the unselected word line may keep a stable voltage value.

It should be understood that, since the first sub word-line driver and the second sub word-line driver are respectively connected to different main word lines, the first word line driver and the second word line driver may respectively drive the connected sub word-lines in response to an enable signal from the first main word line and an enable signal from the second main word line, respectively.

With continued reference to <FIG>, in some embodiments, the number of first channel areas covered by a first gate <NUM> may be four, and each of first channel areas is respectively located in different first active areas <NUM>. That is, the first gate <NUM> spans four first active areas <NUM> arranged at intervals. The number of second channel areas <NUM> covered by the first gate <NUM> may be four, and each of second channel areas <NUM> is respectively located in different second active areas <NUM>, so that the first gate <NUM> spans four second active areas <NUM> arranged at intervals. In the word line driving circuit formed in such a way, referring to <FIG>, the number of pull-up transistors connected to the same main word line is four, and the number of pull-down transistors connected to the same main word line is four. That is to say, each main word line is connected to four sub word-line drivers <NUM>, and the two sub word-line drivers <NUM> corresponding to the two main word lines may share the same holding transistor. That is to say, eight sub word-lines may be driven by two main word lines, and only four holding transistors are needed, so that the number of holding transistors in the word line driver may be decreased, and the layout area of the word line driving circuit is smaller.

Referring to <FIG>, in other embodiments, the number of first channel areas covered by the first gate <NUM> may also be six. That is, the first gate <NUM> spans six first active areas <NUM> arranged at intervals. The number of the second channel areas <NUM> covered by the first gate <NUM> may be six. That is, the first gate <NUM> spans six second active areas <NUM> arranged at intervals.

In the word line driving circuit formed in such a way, the number of pull-up transistors connected to a same main word line is six, and the number of pull-down transistors connected to the same main word line is six. That is to say, each main word line is connected to six sub word-line drivers <NUM> and the two main word lines may drive a total of twelve sub word-lines. It should be understood that in the embodiments of the present disclosure, the number of the first active areas <NUM> may be flexibly set, so that the number of the first channel areas covered by the first gate <NUM> is different, thereby changing the number of sub word-lines that a main word line may drive.

In other embodiments, a second drain area <NUM> of a pull-down transistor corresponding to a first gate <NUM> and a third drain area of the holding transistor are shared, and a second drain area <NUM> of the other pull-down transistor corresponding to the same first gate <NUM> and a third source area <NUM> of the same holding transistor are shared. That is, two pull-down transistors corresponding to the same first gate <NUM> share a same holding transistor, and the same holding transistor is used to control two different sub word-lines corresponding to the same main word line, so that the numbers of the third source areas <NUM> and the third drain areas in the second active area <NUM> may be decreased, the size of the second active area <NUM> may be greatly decreased, and the layout area of the word line driver may be decreased under a condition of keeping the controlling ability of the word line driver unchanged.

Specifically, referring to <FIG>, in some embodiments, the third channel area is located on one side of the second source area <NUM> or the second drain area <NUM> along the second direction Y. A third drain area of a holding transistor and a second drain area <NUM> of a pull-down transistor are shared, and a third source area <NUM> of the holding transistor and a second drain area <NUM> of the other pull-down transistor are shared. The second active area <NUM> includes a plurality of second source areas <NUM> and a plurality of second drain areas <NUM>. The plurality of second source areas <NUM> are arranged at intervals in the second direction Y, and the plurality of second drain areas <NUM> are arranged at intervals in the second direction Y. The third channel area is located between the second drain areas <NUM> of two different pull-down transistors, such that the third channel area and the second drain areas <NUM> on two sides of the third channel area are located on a same side of the first gate <NUM> along the first direction X. The second drain area <NUM> on one side of the third channel area and the first gate <NUM> are used to form a pull-down transistor, and the second drain area <NUM> on the other side of the third channel area and the same first gate <NUM> are used to form another pull-down transistor. That is to say, two pull-down transistors connected to the same holding transistor correspond to the same first gate <NUM>. That is, one holding transistor is used to control sub word-lines corresponding to the same main word line. The source and drain of the holding transistor and the drains of two different pull-down transistors are set to be shared, thereby decreasing the occupied area of the second active area <NUM>, and improving the integration level of the word line driver.

Specifically, the reference of the word line driving circuit corresponding to the word line driver in <FIG> is made to <FIG>. The word line driving circuit includes at least two sub word-line drivers <NUM>, and each sub word-line driver <NUM> is connected to a main word line and a sub word-line. The first end and the second end of the holding transistor <NUM> are respectively connected to different sub word-lines, and two sub word-lines connected to the first end and the second end of the holding transistor <NUM> correspond to the same main word line. That is, two sub word-line drivers <NUM> correspond to the same main word line. The gate of the pull-up transistor <NUM> is connected to the main word line, the gate of the pull-down transistor <NUM> is connected to the main word line, and the drain of the pull-down transistor <NUM> is connected to the drain of the pull-up transistor <NUM>.

The operation principle of the word line driving circuit in <FIG> for driving and closing the sub word-line is the same as that of the word line driving circuit in <FIG>, and will not be described hereafter. It should be understood that, since the two sub word-line drivers <NUM> are connected to the same main word line, when the main word line inputs an enable signal, the gates of the two pull-up transistors corresponding to the two sub word-line drivers <NUM> will simultaneously receive the enable signal from the main word line. Considering that only one sub word-line may be driven, the level of the first driving signal PXID received by the source of the pull-up transistor <NUM> of one sub word-line driver <NUM> may be set to be different from the level of the first driving signal PXID received by the source of the pull-up transistor <NUM> of the other sub word-line driver <NUM>, so as to prevent two sub word-lines from being conductive at the same time.

With continued reference to <FIG>, in some embodiments, when two pull-down transistors corresponding to the same first gate <NUM> share a same holding transistor, the number of first channel areas covered by the first gate <NUM> may be four, and each of first channel areas is respectively located in different first active areas <NUM>. That is, the first gate <NUM> spans four first active areas <NUM> arranged at intervals. The number of second channel areas <NUM> covered by the first gate <NUM> may be four. The first gate <NUM> covers two second channel areas <NUM> in the first NMOS area <NUM> and two second channel areas <NUM> in the second NMOS areas <NUM>, and each of second channel areas <NUM> is respectively located in different second active areas <NUM>, so that the first gate <NUM> spans four second active areas <NUM>. In the word line driving circuit formed in such a way, referring to <FIG>, the number of pull-up transistors connected to a same main word line is four, and the number of pull-down transistors connected to the same main word line is <NUM>. That is, each main word line is respectively connected to four sub word-line drivers <NUM>. Two sub word-line drivers <NUM> corresponding to the same main word line share the same holding transistor. That is, one main word line corresponds to two holding transistors.

Referring to <FIG>, in other embodiments, the number of first channel areas covered by the first gate <NUM> may also be six. That is, the first gate <NUM> spans six first active areas <NUM> arranged at intervals. The number of the second channel areas <NUM> covered by the first gate <NUM> may be six. That is, the first gate <NUM> spans six second active areas <NUM> arranged at intervals. In the word line driving circuit formed in such a way, the number of pull-up transistors connected to a same main word line is six, and the number of pull-down transistors connected to the same main word line is six. That is, each main word line is connected to six sub word-line drivers <NUM>. Two sub word-line drivers <NUM> corresponding to the same main word line share a same holding transistor. That is, one main word line corresponds to three holding transistors.

In some embodiments, the holding transistor includes a first transistor (not shown in the figures) and a second transistor (not shown in the figures). Two pull-down transistors electrically connected to a same first transistor share a first gate <NUM>. For a same second transistor, a third drain area is electrically connected to a second drain area <NUM> of a pull-down transistor, a third source area <NUM> is electrically connected to a second drain area <NUM> of another pull-down transistor, and two pull-down transistors electrically connected to a same second transistor correspond to two first gates <NUM>. That is to say, two pull-down transistors electrically connected to the first transistor correspond to a same main word line, so that the first transistor controls two sub word-lines corresponding to the same main word line. Two pull-down transistors electrically connected to a same second transistor correspond to the two first gates <NUM>, respectively. That is, the two pull-down transistors electrically connected to the second transistor correspond to two different main word lines, so that the second transistor may control two different main word lines. That is, the connection between the holding transistor and different sub word-lines may be flexibly set, so that the area occupied by the word line driving circuit may be decreased under the condition of keeping the performance of the word line driving circuit unchanged, thus decreasing the layout area of the word line driving circuit.

In some embodiments, the NMOS area <NUM> includes a first NMOS area and a second NMOS area respectively located on opposite sides of the PMOS area <NUM>. The first transistor is located in the first NMOS area. The second transistor is located in the second NMOS area. A part number of pull-down transistors is located in the first NMOS area, and the remaining number of pull-down transistors is located in the second NMOS area. Since the two pull-down transistors electrically connected to the first transistor share the first gate <NUM>, the two pull-down transistors electrically connected to the same second transistor correspond to the two first gates <NUM>, respectively, so that the connection mode between the first transistor and the first gate <NUM> and the connection mode between the second transistor and the first gate <NUM> are different. Therefore, the first transistor is set in the first NMOS area and the second transistor is set in the second NMOS area, which is beneficial to forming the first transistor and the second transistor respectively and simplifying the complexity of layout design. In addition, a pull-down transistor electrically connected to the first transistor is set in the first NMOS area, the pull-down transistor electrically connected to the second transistor is set in the second NMOS area, so that when the pull-down transistor is electrically connected to the first transistor and the second transistor, respectively, it is beneficial to shorten the line length of the metal layer, thereby reducing the signal delay in the metal layer.

In some embodiments, each first gate <NUM> includes at least two extension portions arranged at intervals along a first direction X and a connecting portion. Each extension portion covers a plurality of first channel areas and a plurality of second channel areas <NUM>, and the each extension portion is inclined compared with the first direction X. The connecting part is connected to the extension portions arranged adjacent to each other in the first direction. The two extension portions cover the plurality of first channel areas and the plurality of second channel areas <NUM>, so that one first gate <NUM> is electrically connected to the plurality of first channel areas and the plurality of second channel areas <NUM>, and is used for controlling the plurality of pull-up transistors and conduction of the pull-up transistors. The connecting portion connects the extension portions arranged adjacent to each other in the first direction X, so that the two extension portions arranged at intervals are electrically connected to form a main word line for controlling the conduction of a plurality of pull-up transistors and a plurality of second pull-down transistor, so that the number of sub word-lines that may be controlled by one main word line is increased. Specifically, when the number of the first channel areas covered by one extension portion is four and the number of the second channel areas <NUM> covered by one extension portion is four, four sub word-lines may be controlled. When the connecting portion connects the two extension portions to form a first gate <NUM>, since each extension portion may control four sub word-lines, the first gate <NUM> may control eight sub word-lines.

In some embodiments, the material of the first gate <NUM> may include at least one of polysilicon or metal.

In some embodiments, each first gate <NUM> covers <NUM>×N first channel areas and <NUM>×N second channel areas <NUM>. The pull-up transistors and pull-down transistors composed of each first gate <NUM> are electrically connected to <NUM>×N holding transistors. N is a positive integer greater than or equal to <NUM>. That is, the number of the first channel areas and the number of the second channel areas <NUM> remain equal, so that the number of pull-up transistors and the number of pull-down transistors are the same, and each pull-up transistor and a pull-down transistor <NUM> constitute a sub word-line driver <NUM>. The number of holding transistors is half of the number of pull-up transistors or pull-down transistors <NUM>, so that the two sub word-line drivers <NUM> may share one holding transistor, thereby facilitating to decrease the number of holding transistors in the word line driver, and decreasing the layout area of the word line driver.

In the word line driver provided by the above-described embodiments, the pull-up transistor and the pull-down transistor may respectively transmit a driving signal to the sub word-line through the first drain area <NUM> and the second drain area <NUM>, thereby controlling the driving and closing of the sub word-line. A third drain area and a third source area <NUM> of the holding transistor are electrically connected to second drain areas <NUM> of two different pull-down transistors, so that two pull-down transistors share the same holding transistor. Thus, when one sub word-line connected to one of the pull-down transistors is driven, the holding transistor may control the sub word-line connected to the other pull-down transistor to be in an unselected state, thereby decreasing the layout area of the word line driver under a condition of keeping the performance of the word line driver unchanged. In addition, the extension direction of the first gate <NUM> corresponding to the first active area <NUM> is set to be inclined compared with the extension direction of the first active area <NUM>, so that the first gate <NUM> in the first active area <NUM> has a greater size, which is equivalent to increasing the channel size of the pull-up transistor, thereby improving the driving ability of the first gate <NUM> to the pull-up transistor.

Accordingly, the embodiments of the present disclosure also provide a memory device. The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of sub word-lines and a plurality of bit lines, and a word line driving circuit provided by any of the above embodiments or a word line driver provided by any of the above embodiments. In some embodiments, the memory cell may be a DRAM memory cell.

Claim 1:
A word line driver comprising:
a substrate comprising an NMOS, N-Metal-Oxide-Semiconductor, area (<NUM>) and a PMOS, P-Metal-Oxide-Semiconductor, area (<NUM>);
wherein the PMOS area comprises a plurality of first active areas (<NUM>) extending along a first direction (X), and each first active area comprises a first channel area, and a first source area (<NUM>) and a first drain area (<NUM>) respectively located on opposite sides of the first channel area,
wherein the NMOS area and the PMOS area are arranged along a second direction (Y) perpendicular to the first direction, the NMOS area comprises a plurality of second active areas (<NUM>) extending along the first direction, each second active area comprises a second channel area (<NUM>), and a second source area (<NUM>) and a second drain area (<NUM>) respectively located on opposite sides of the second channel area, and the each second active area further comprises a third channel area, and a third source area (<NUM>) and a third drain area respectively located on opposite sides of the third channel area;
first gates (<NUM>), wherein the first gates are electrically connected to a main word line, a first gate, a first source area and a first drain area constitute a pull-up transistor (<NUM>), a first gate, a second source area and a second drain area constitute a pull-down transistor (<NUM>), the pull-up transistor and the pull-down transistor are electrically connected to a same sub word-line, and an extension direction of first gates corresponding to a first active area are inclined compared with the first direction; and
a plurality of second gates (<NUM>), wherein each second gate covers a corresponding third channel area, and a second gate, a third source area and a third drain area constitute a holding transistor (<NUM>),
wherein, for a same holding transistor, a third drain area is electrically connected to a second drain area of a pull-down transistor and a third source area is electrically connected to a second drain area of another pull-down transistor.