Patent Description:
The present disclosure relates generally to methods and apparatuses with improved isolation among input or output (I/O) ports and in particular improving isolation by operation of an isolation circuit.

A computing device (e.g., a laptop, a mobile phone, etc.) may perform various functions, such as telephony, wireless data access, and camera/video function, etc. Such computing device may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. Increasingly, modem applications demand higher performance while reducing physical dimensions of such computing device. Components of the computing are placed in closer proximity, resulting in undesired coupling. An example of coupling may be transfer of electrical energy from one component to another. Undesired coupling may be unintended and/or coupling that interference with intended operations of the computing device.

One such example is a transceiver configured to transmit and to receive radio frequency (RF) signals based on multiple RF communication standards and/or using multiple antennas (e.g., operating a multiple-input and multiple output system). Thus, an apparatus incorporating the transceiver may include multiple chains (e.g., collections of circuits to transmit and/or to receive RF signals). Coupling among the chains, even on a package, is a concern. For example, the transceiver may be incorporated within a device, and such device may be a packaged chip, a multi-die assembly (e.g., a die stack or a multi-die package), a multi-chip assembly (e.g., a chip stack or package-on-package assembly), and/or a mixed-die-chip assembly. Coupling among I/O pins, I/O bond pads, and/or wirings outside of the transceiver may result from proximity of those elements. Coupling among different (e.g., RF) functions may degrade performance of the device. Improved isolation for such device is needed.

Attention is drawn to <CIT> relating to a MIMO antenna including: a first antenna, a second antenna, and an adjustable decoupling structure. The adjustable decoupling structure is disposed between the first antenna and the second antenna, and is configured to reduce coupling between the first antenna and the second antenna. The adjustable decoupling structure includes a first adjustable capacitor and a second adjustable capacitor that are connected in series and a first adjustable inductor and a second adjustable inductor that are connected in parallel.

This summary identifies features of some example aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Additional features and aspects are described and will become apparent to persons skilled in the art upon reading the following detailed description and viewing the drawings that form a part thereof.

Various aspects of apparatus and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:.

The detailed description includes specific details for providing a thorough understanding of various concepts. In some instances, well known structures and components are shown in block diagram form to avoid obscuring such concepts.

As used herein, the term "coupled to" in the various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B), to operate certain intended functions. In the case of electrical components, the term "coupled to" may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" mean a transfer of electrical energy between elements A and B, to operate certain intended functions.

In some examples, the term "electrically connected" mean having an electric current or configurable to having an electric current flowing between the elements A and B. For example, the elements A and B may be connected via resistors, transistors, or an inductor, in addition to a wire, trace, or other electrically conductive material and components. Furthermore, for radio frequency functions, the elements A and B may be "electrically connected" via a capacitor.

The terms "first," "second," "third," etc. are employed for ease of reference and may not carry substantive meanings. Likewise, names for components/modules may be adopted for ease of reference and might not limit the components/modules. For example, such non-limiting names may include "control" module. Modules and components presented in the disclosure may be implemented in hardware, software, or a combination of hardware and software.

The term "bus system" may provide that elements coupled to the "bus system" may exchange information therebetween, directly or indirectly. In such fashion, the "bus system" may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc..

Methods and apparatuses for adjusting isolation (e.g., to improve isolation by reducing coupling) among I/O ports are presented herein. The I/O ports may be I/O pond pads on a semiconductor die (hereinafter "die") or I/O pins (e.g., pins, balls, or stubs, etc.) on a device. The device may be, for example, a package chip (herein after "chip"), a multi-die assembly, a multi-chip assembly, and/or a mixed-die-chip assembly, etc. The device may, for example, incorporate the die, and the die may include a transceiver. The transceiver may include at least one processor coupled to a memory. The presented methods and apparatus for adjusting isolation may further improve coupling among wirings outside of the die (e.g., bond wires, conductive pillars, interconnects on an interposer, etc.).

<FIG> illustrates components of an apparatus <NUM> with coupling between chains of RF circuits. The apparatus <NUM> may, for example, be one of a computing system (e.g., servers, datacenters, desktop computers), mobile computing device (e.g., laptops, cell phones, vehicles, etc.), Internet of Things device, virtual reality system, or augmented reality system. The apparatus <NUM> may include some or all of a device <NUM>, wiring <NUM> outside of the device, and a circuit board <NUM> (e.g., a printed circuit board or PCB). The device <NUM> may be, for example, a die, a chip incorporating the die, a multi-die assembly (e.g., a package containing multiple dies), a multi-chip assembly incorporating multiple dies (e.g., an assembly of package-on-package chips), and/or a mixed-die-chip assembly. The wiring <NUM> outside of the device <NUM> (e.g., outside of the die incorporated within the device) may electrically connect the device <NUM> to the circuit board <NUM> and may be, for example, bond wires, conductive pillars, interconnects on an interposer, etc..

The apparatus <NUM> may further include multiple chains of radio frequency (RF) circuits. A chain may be a collection of circuits for performing various RF functions, such as transmitting or receiving RF signaling. As illustrates, the apparatus <NUM> includes a first chain of RF circuits 140_1 and a second chain of RF circuits 140_2. In some examples, the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 may be part of a multiple-input and multiple-output (MIMO) system and as such, perform MIMO functions. In some examples, each of the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 may be configured for transmission or receiving of RF signaling of different wireless radio technologies, such as Wi-Fi or cellular telephony. In some examples, each of the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 may be part of a transceiver on a die. In some examples, the first chain of RF circuits 140_1 or the second chain of RF circuits 140_2 may be configured for transmission or receiving of RF signaling via wireline interface.

The first chain of RF circuits 140_1 may include various circuits on the device <NUM> for RF signal transmission and/or receiving. For example, the first chain of RF circuits 140_1 may include filters (e.g., a transmission filter 141_1 and a receiver filter 142_1), mixers (e.g., a transmission mixer 143_1 and a receiver filter 144_1), and/or amplifiers (e.g., a driver amplifier 145_1, a low-noise amplifier 146_1, a transconductance amplifier 147_1). The first chain of RF circuits 140_1 may further include a control module 148_1 configured to control, at least in part, RF functions of the first chain of RF circuits 140_1.

The second chain of RF circuits 140_2 may include filters (e.g., a transmission filter 141_2 and a receiver filter 142_2), mixers (e.g., a transmission mixer 143_2 and a receiver filter 144_2), and/or amplifiers (e.g., a driver amplifier 145_2, a low-noise amplifier 146_2, a transconductance amplifier 147_2). The second chain of RF circuits 140_2 may further include a control module 148_2 configured to control, at least in part, RF functions of the first chain of RF circuits 140_2.

The device <NUM> may be electrically connected to the circuit board <NUM> via the wiring <NUM> outside of the device <NUM> and input and/or output ports (I/O ports). The I/O ports 152_1, 154_1, 156_1, 152_2, 154_2, and/or 156_2 may be I/O pads on a die within the device <NUM>, and the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 may be part of the die. In some examples, the I/O ports may be pins of device <NUM> (pins may broadly refer to I/O interconnects into and/or out of the device <NUM>, such as pins, balls, stubs, etc.). The wiring <NUM> outside of the device <NUM> may include a wiring 122_1, 124_1, 126_1, 122_2, 124_2, and/or 126_2.

The first chain of RF circuits 140_1 may include an I/O port 152_1 electrically connected to the wiring 122_1. The I/O port 152_1 and the wiring 122_1 may be configured to provide RF signals for transmission. The first chain of RF circuits 140_1 may include an I/O port 154_1 electrically connected to the wiring 124_1. The I/O port 154_1 and the wiring 124_1 may be configured to provide received RF signals to the device <NUM>. The first chain of RF circuits 140_1 may further include an I/O port 156_1 configured to carry information of RF signals transmitted by the second chain of RF circuits 140_2. Accordingly, the I/O port 156_1 may be electrically connected to a signal coupler 138_2 of the second chain of RF circuits 140_2. The second chain of RF circuits 140_2 may be similarly connected, and discussion thereof is omitted.

The circuit board <NUM> may include certain components affixed thereto as part of the RF circuit chains. For example, the first chain of RF circuits 140_1 may include an external power amplifier 132_1 configured to amplify transmission signals; an external low-noise amplifier 139_1 configured to amplify received signals; and/or an antenna 136_1 configured to transmit (e.g., to radiate) and to receive RF signals over the air. The first chain of RF circuits 140_1 may also include a signal coupler 138_1 configured to provide information on the transmission RF signals and a transmission/receiving switch 134_1 (e.g., a duplexer) configured to switch a signal path for the antenna 136_1 between transmission and receiving functions. The external power amplifier 132_1, the external low-noise amplifier 139_1, the antenna 136_1, the signal coupler 138_1, and/or the transmission/receiving switch 134_1 may be affixed onto the circuit board <NUM>.

The second chain of RF circuits 140_2 may include an external power amplifier 132_2 configured to amplify transmission signals; an external low-noise amplifier 139_2 configured to amplify received signals; and/or an antenna 136_2 configured to transmit (e.g., to radiate) and to receive RF signals over the air. The second chain of RF circuits 140_2 may also include a signal coupler 138_2 configured to provide information on the transmission RF signals and a transmission/receiving switch 134_2 (e.g., a duplexer) configured to switch a signal path for the antenna 136_2 between transmission and receiving functions. The external power amplifier 132_2, the external low-noise amplifier 139_2, the antenna 136_2, the signal coupler 138_2, and/or the transmission/receiving switch 134_2 may be affixed onto the circuit board <NUM>.

The wiring <NUM> outside of the device <NUM> may include various wirings electrically connecting the device <NUM>, via the I/O ports, to the components affixed to the circuit board <NUM>. The wiring <NUM> may include, for example, bond wires, bumps, connective traces on interposers, pillars, etc. In some examples, the wiring <NUM> may include electrical connections between a die/chip to another die/wafer/chip/circuit board. For example, the first chain of RF circuits 140_1 may include the wiring 122_1 to electrically connect the I/O port 151_1 to a component (e.g., to the external power amplifier 132_1) on the circuit board <NUM>. The wiring 122_1 may be configured to provide RF transmission signals to the antenna 136_1, via the signal coupler 138_1. The first chain of RF circuits 140_1 may further include the wiring 124_1 to electrically connect the I/O port 154_1 to a component (e.g., to the external low-noise amplifier 139_1) on the circuit board <NUM>. The wiring 124_1 may be configured to provide received RF signals from the antenna 136_1, via the transmission/receiving switch 134_1.

The wiring <NUM> outside of the device <NUM> may further include the wiring 126_1 to electrically connect the I/O port 156_1 to, for example, the signal coupler 138_2 (of the second chain of RF circuits 140_2). The wiring 126_1 may be configured to provide, to the first chain of RF circuits 140_1 on the device <NUM>, signaling information (e.g., power and/or signal quality information) of the RF transmission signals of the second chain of RF circuits 140_2. In some examples, the control module 148_1 may be coupled to the I/O port 156_1 (e.g., via various components not shown) and configured to determine power and/or signal quality of RF transmission signals of the second chain of RF circuits 140_2 (e.g., for MIMO functions).

The second chain of RF circuits 140_2 may include the wiring 122_2 to electrically connect the I/O port 151_2 to a component (e.g., to the external power amplifier 132_2) on the circuit board <NUM>. The wiring 122_2 may be configured to provide RF transmission signals to the antenna 136_2, via the signal coupler 138_2. The first chain of RF circuits 140_2 may further include the wiring 124_2 to electrically connect the I/O port 154_2 to a component (e.g., to the external low-noise amplifier 139_2) on the circuit board <NUM>. The wiring 124_2 may be configured to provide received RF signals from the antenna 136_2, via the transmission/receiving switch 134_2.

The wiring <NUM> outside of the device <NUM> may further include the wiring 126_2 to electrically connect the I/O port 156_2 to, for example, the signal coupler 138_1 (of the first chain of RF circuits 140_1). The wiring 126_2 may be configured to provide, to the second chain of RF circuits 140_2 on the device <NUM>, signaling information (e.g., power and/or signal quality information) of the RF transmission signals of the first chain of RF circuits 140_1. In some examples, the control module 148_2 may be coupled to the I/O port 156_2 (e.g., via various components not shown) and configured to determine power and/or signal quality of RF transmission signals of the first chain of RF circuits 140_1 (e.g., for MIMO functions).

As dimensions of apparatus <NUM> decrease, and demands for performance increase, coupling among the I/O ports and/or among the wiring <NUM> becomes increasingly disruptive. For example, the device <NUM> may include a transceiver, and undesired coupling between different signals paths may cause performance of certain RF functions to degrade. <FIG> illustrates a potential, undesirable coupling <NUM> (shown by dash arrows) at least in part outside of the device <NUM> (e.g., between the I/O port 152_1 and the I/O port 156_1 or between the wiring 122_1 and the wiring 126_1). The coupling <NUM> may be unintended and causing impairment of intended RF functions. For example, the coupling <NUM> may impair residual sideband calibration, cause error vector magnitude degradation or Spectrum Emission Mask violation in a MIMO system, reduce power control accuracy, cause a receiver path de-sensing in a Frequency Division Duplex system, and/or degrade noise figure, etc..

<FIG> illustrations I/O ports placement of the device <NUM> of <FIG>. For examples, the I/O ports may be I/O pins (pin, balls, stubs, etc.) of the device <NUM> or I/O bond pads of a die incorporated within the device <NUM>. X-axis is shown in the horizontal direction, and Y-axis is shown in the vertical direction. <FIG> includes an I/O port 252_1 (which may be an instance of the I/O port 152_1 of <FIG>) and I/O port 254_1 (which may be an instance of the I/O port 154_1 of <FIG>). The I/O port 254_1 may include a positive terminal 254_1_P and a negative terminal 254_1_N. In other words, the received RF signals may be differential signals (see <FIG>). <FIG> further includes an I/O port 256_1, which may be an instance of the I/O port 156_1 of <FIG>.

A potential coupling <NUM> is shown between the I/O port 252_ <NUM> and the I/O port 256_1. The coupling <NUM> may be due to coupling between the I/O port 252_ <NUM> and the I/O port 256_1 or due to coupling between the wiring <NUM> coupled to the respective I/O ports 252_1 and 256_1. The coupling <NUM> may thus occur outside of the device <NUM>. Due to proximity between the I/O port 252_ <NUM> and the I/O port 256_1, isolation therebetween may be about <NUM> dB. In an example, the first chain of RF circuits 140_1 (<FIG>; the I/O port 252_1 as an instance of the I/O port 152_1) may couple to the second chain of RF circuits 140_2 (<FIG>; the I/O port 256_1 as an instance of the I/O port 156_1 coupled to the second chain of RF circuits 140_2).

The potential coupling <NUM> of the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 may lead to spectrum emission mask (SEM) violation and/or EVM degradation. To address these issues, the isolation between the I/O port 252_ <NUM> and the I/O port 256_1 preferably should be greater than <NUM> dB. To achieve such isolation performance, the distance between the I/O port 252_ <NUM> and the I/O port 256_1 may need to substantially increase. Such solution may be unpractical for modem devices. For example, in order to achieve the <NUM>-dB isolation, the distance between the I/O port 252_ <NUM> and the I/O port 256_1 may need to be increased six times from a minimum distance allowed by a assembling technology. A resulting increase in size of the device and added expense are not viable for modern applications.

<FIG> illustrates an apparatus <NUM> incorporating an isolation circuit <NUM> to adjust isolation between I/O ports and/or between wirings associated with a device <NUM>, in accordance with certain aspects of present disclosure. <FIG> includes, as an example, a device <NUM> incorporating a die <NUM>. The device <NUM> may be, for example, quad-flat no-leads or QFN package, and may be a functional substitute for the device <NUM> in the apparatus <NUM>, as illustrated in <FIG> (e.g., an instance of the device <NUM> with additional circuitries or modifications). The device <NUM> may include an I/O port 352_1 (e.g., an example of the I/O port 152_1 of <FIG>), an I/O port 354_1 (e.g., an example of the I/O port 154_1 of <FIG>), an I/O port <NUM>, and an I/O port 356_1 (e.g., an example of the I/O port 156_1 of <FIG>). These I/O ports may be, for example, I/O pins (e.g., pins, balls, stubs, etc.) of the device <NUM>.

The I/O ports of the device <NUM> may electrically connect to the circuit board <NUM> via wiring <NUM> (which may be an example of the wiring <NUM> of <FIG>). The circuit board <NUM> may be an instance of the circuit board <NUM> of <FIG>. The wiring <NUM> may include a wiring 322_1 (e.g., an example of the wiring 122_1 of <FIG>), a wiring 324_1 (e.g., an example of the wiring 124_1 of <FIG>), a wiring <NUM>, and a wiring 326_1 (e.g., an instance of the wiring 126_1 of <FIG>). The wiring 322_1 may be electrically connected to the I/O port 352_1. The wiring 324_1 may be electrically connected to the I/O port 354_1. The wiring <NUM> may be electrically connected to the I/O port <NUM>. The wiring 326_1 may be electrically connected to the I/O port 356_1.

The die <NUM> may be, for example, a transceiver die including at least one processor. The at least one processor may be coupled with a memory <NUM> via a bus system <NUM> to perform RF functions of the transceiver. For example, the at least one processor may operate with the memory <NUM>, at least in part, to perform the functions of the first chain of RF circuits 140_1 and/or second chain of RF circuits 140_2 (<FIG>). For example, the at least one processor may receive data, instructions, or parameters for RF functions from the memory <NUM> via the bus system <NUM>. In some examples, the die <NUM> include the memory <NUM>. In some examples, the memory <NUM> is outside of the die <NUM>.

The die <NUM> may include various I/O bond pads. The I/O bond pads electrically connect to the I/O ports of the device <NUM> via wiring <NUM> outside of the die <NUM>. The wiring <NUM> may include, for example, a wiring 362_1, a wiring 364_1, a wiring <NUM>, and/or a wiring 366_1. A I/O bond pad 312_1 may be electrically connected to the I/O port 352_1 via the wiring 362_1. A I/O bond pad 314_1 may be electrically connected to the I/O port 354_1 via the wiring 364_1. A I/O bond pad <NUM> may be electrically connected to the I/O port <NUM> via the wiring <NUM>. A I/O bond pad 316_1 may be electrically connected to the I/O port 356_1 via the wiring 366_1. In some examples, the I/O bond pads of the die <NUM> may be examples of the I/O ports of the present disclosure.

In a case of coupling (e.g., coupling <NUM> of <FIG>), the I/O port 356_1, the wiring 326_1, the I/O bond pad 316_1, and/or the wiring 366_1 may be part of an aggressor circuit (e.g., causing an interference). The I/O port 352_1, the wiring 322_1, the I/O bond pad 312_1, and/or the wiring 362_1 may be part of a victim circuit (signals carried thereon being distorted by the interference). <FIG> illustrates an isolation circuit <NUM> to adjust isolation (e.g., to improve isolation by reducing coupling) between the aggressor and the victim without having to increase a distance between the aggressor and the victim.

The isolation circuit <NUM> may include, for example, a variable capacitor <NUM> (e.g., incorporated within the die <NUM>; semiconductor layers of the die <NUM> constituting the variable capacitor <NUM>), the I/O bond pad <NUM>, the wiring (outside of the die <NUM>) <NUM>, the I/O port <NUM>, and/or the wiring (outside of the device <NUM>) <NUM>. The isolation circuit <NUM> may be connected to various passive elements on the circuit board <NUM>. For example, the isolation circuit <NUM> may further include an inductor 337_A or a capacitor 337_B electrically connected to the I/O port <NUM>, via the wiring <NUM>. Alternatively, the isolation circuit <NUM> may electrically connect to ground on the circuit board <NUM>. As presented below, a control module <NUM> (e.g., as part of the at least one processor operating at least in part with the memory <NUM>) may dynamically tune the variable capacitor <NUM> (e.g., adjust a capacitance setting) to actively attenuate or cancel coupling (e.g., the coupling <NUM> of <FIG>) between the aggressor circuit and the victim circuit. In some examples, isolation circuit <NUM> may be dedicated to isolation improvement and does not perform intended RF functions (or any other functions in general).

In some example, the control module <NUM> may adjust a setting of the variable capacitor <NUM> (to improve isolation between I/O ports by reducing coupling) based on a measurement or simulation result of potential, undesired coupling (e.g., the coupling <NUM> of <FIG>). In some examples, the control module <NUM> may adjust the setting of the variable capacitor <NUM> based on a determination of undesired coupling. Referring to <FIG>, the control module 148_1 may be configured to determine such undesired coupling based on, for example, information received via the I/O port 156_1. Such determination may be made for changing operating conditions (e.g., when and where there are weak RF signaling) and/or for changing operating modes (e.g., the device <NUM> changes among different radio access technologies). In response, the control module <NUM> may actively and dynamically adjust the setting of the variable capacitor <NUM> to improve isolation between I/O ports, in response to changing operating conditions or operating modes.

For example, the at least one processor (e.g., the control module <NUM>) operates at least in part with the memory <NUM> to adjust the setting of the variable capacitor <NUM>. The at least one processor may receive data, instructions, or parameters to adjust the setting of the variable capacitor <NUM> from the memory <NUM> via the bus system <NUM>. In some examples, the die <NUM> include the memory <NUM>. In some examples, the memory <NUM> is outside of the die <NUM>.

<FIG> illustrates physical placements of the I/O ports of <FIG>, in accordance with certain aspects of the present disclosure. X-axis is shown in the horizontal direction, and Y-axis is shown in the vertical direction. <FIG> includes the I/O port 352_1 (victim circuit; <FIG>), the I/O port 354_1 (<FIG>). The I/O port 354_1 may include a positive terminal 354_1_P and a negative terminal 354_1_N, in a case the received RF signals being differential signals. <FIG> may further include the I/O port <NUM>, which may be part of the isolation circuit <NUM> (<FIG>), and the I/O port 356_1 (aggressor circuit see <FIG>). The I/O port <NUM> is (physically) disposed between the I/O port 352_1 (the victim circuit) and the I/O port 356_1 (the aggressor circuit), at least in the Y-axis, to adjust or to improve isolation therebetween. An I/O port 357_Y is likewise (physically) disposed between the I/O port 352_1 (the victim circuit) and the I/O port 356_1 (the aggressor circuit), at least in the Y-axis, to adjust or to improve isolation therebetween. The I/O port 357_Y will be presented with <FIG>.

<FIG> illustrates operation of the isolation circuit <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. <FIG> includes an aggressor circuit (e.g., the aggressor circuit of <FIG>, a circuit coupled to the I/O port 356_1) illustrated as an inductor, the isolation circuit <NUM> (<FIG>) illustrated as an inductor, and a victim circuit (e.g., the victim circuit of <FIG>; a circuit coupled to the I/O port 352_1) illustrated as an inductor. The aggressor circuit has a current i1 flowing therethrough during operation of an RF function (e.g., functions of the first chain of RF circuits 140_1 and/or the second chain of RF circuits 140_2 presented with <FIG>). The aggressor circuit may be coupled to the victim circuit via a coupling <NUM>, creating a current i1' flowing in the victim circuit. The aggressor circuit may also be coupled to the isolation circuit <NUM> via a coupling <NUM>, creating a current i2 flowing therein.

The isolation circuit <NUM> may be coupled to the victim circuit via a coupling <NUM>, creating a current i2' flowing in the victim circuit. The current i2 flowing in the isolation circuit <NUM> may be tuned by the variable capacitor <NUM>. In such fashion, the control module <NUM> (e.g., as part of the at least one processor operating at least in part with the memory <NUM>) may change a capacitance setting of the variable capacitor <NUM> to adjust the current i2' flowing in the victim circuit. The victim circuit may have a current i3 flowing therethrough, the current i3 being a result of the coupling <NUM> and the coupling <NUM>. The current i3 may be expressed i1' - i2'. Accordingly, the variable capacitor <NUM> may be tuned to adjust the current i2, such that the current i3 is zero at a desired frequency range (e.g., tuning i2' to equal i1').

<FIG> illustrates another implementation of the isolation circuit <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. <FIG> illustrates that the isolation circuit <NUM> may include multiple I/O ports (and/or wiring outside of the device <NUM> or outside of the die <NUM> of <FIG>) to adjust or improve isolation at multiple operating frequencies. For example, <FIG> illustrates that the isolation circuit <NUM> may include a second variable capacitor 372_Y, an additional I/O bond pad 317_Y, an additional wiring 367_Y outside of the die <NUM>, an additional I/O port 357_Y, an additional wiring 327_Y outside of the device <NUM>, and/or additional ground or passive components on the circuit board <NUM>. The second variable capacitor 372_Y may be electrically connected to the additional I/O bond pad 317_Y. The additional wiring 367_Y outside of the die <NUM> may electrically connect the additional I/O bond pad 317_Y and the additional I/O port 357_Y. The additional wiring 327_Y outside of the device <NUM> may electrically connect the additional I/O port 357_Y and the circuit board <NUM>. The control module <NUM> (e.g., as part of the at least one processor operating in part with the memory <NUM>) may dynamically and actively tune the second variable capacitor 372_Y (e.g., adjust a capacitance setting thereof) to reduce coupling at a second frequency. A second operating frequency at which coupling is reduced may be different from a first operating frequency at which coupling is reduced, by the variable capacitor <NUM>. See <FIG> presented below.

In some example, the control module <NUM> may adjust a setting of the variable capacitor 373_Y (to improve isolation between I/O ports) based on a measurement or simulation result of potential, undesired coupling (e.g., the coupling <NUM> of <FIG>). In some examples, the control module <NUM> may adjust the setting of the variable capacitor 373_Y (to improve isolation between I/O ports) based on a determination of undesired coupling. Referring to <FIG>, the control module 148_1 may be configured to determine such undesired coupling based on, for example, information received via the I/O port 156_1. Such determination may be made for changing operating conditions (e.g., when and where there are weak RF signaling) and/or for changing operating modes (e.g., the device <NUM> changes among different radio access technologies). In response, the control module <NUM> may actively and dynamically adjust the setting of the variable capacitor 373_Y to improve isolation between I/O ports, in response to changing operating conditions or operating modes.

For example, the at least one processor (e.g., the control module <NUM>) operates at least in part with the memory <NUM> to adjust the setting of the variable capacitor 372_Y. The at least one processor may receive data, instructions, or parameters to adjust the setting of the variable capacitor 372_Y from the memory <NUM> via the bus system <NUM>. In some examples, the die <NUM> include the memory <NUM>. In some examples, the memory <NUM> is outside of the die <NUM>.

<FIG> illustrates isolation performance for various schemes, including the isolation circuit <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. Operating frequency (e.g., of the device <NUM> of <FIG>) is shown as the X-axis, and isolation expressed as dB is shown as the Y-axis. <FIG> includes an isolation curve <NUM>, an isolation curve <NUM>, and an isolation curve <NUM>. The isolation curve <NUM> is a result of, for example, isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) without any isolation circuit (e.g., without the isolation circuit <NUM> of <FIG>). At point A, at an operating frequency of <NUM> (which may be an operating frequency needing the best isolation), the isolation curve <NUM> shows isolation of about <NUM> dB.

The isolation curve <NUM> is also a result of, for example, isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) without operations of the variable capacitor <NUM>. For example, for the isolation curve, the capacitance of the variable capacitor <NUM> and the variable capacitor 372_Y may be considered to be at zero. For the isolation curve <NUM>, referring to <FIG>, the I/O bond pad <NUM>, the wiring <NUM> outside of the die <NUM>, and/or the I/O port <NUM> (without the variable capacitor <NUM>) may be grounded. At point B, at the operating frequency of <NUM>, the isolation curve <NUM> shows some improvement at <NUM> dB.

The isolation curve <NUM> is a result of, for example, isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) having the variable capacitor <NUM> (<FIG>) dynamically and actively tuned to improve isolation at a desired operating frequency (e.g., <NUM>). At point C, at the operating frequency of <NUM>, the isolation curve <NUM> shows vastly improved isolation at <NUM> dB. Referring to <FIG>, the control module <NUM> may be configured to dynamically and actively tune the variable capacitor <NUM> to achieve the improved isolation (e.g., to adjust the variable capacitor <NUM> to account for process variation and/or the desired operating frequency). Moreover, the desired operating frequency at which the variable capacitor <NUM> operates to reduce coupling may be effected by the passive components (e.g., the inductor 337_A, the capacitor 337_B, and/or ground on the circuit board <NUM> at <FIG>) of the circuit board <NUM>.

<FIG> illustrates isolation performance for various schemes, including the isolation circuit <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. Operating frequency (e.g., of the device <NUM> of <FIG>) is shown as the X-axis, and isolation expressed as dB is shown as the Y-axis. <FIG> includes an isolation curve <NUM>, an isolation curve <NUM>, and an isolation curve <NUM>. The isolation curve <NUM> may a result of, for example, isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) without any isolation circuit (e.g., without the isolation circuit <NUM> of <FIG>). At point A1, at a first desired operating frequency of <NUM> (which may be an operating frequency needing improved isolation), the isolation curve <NUM> shows isolation of about <NUM> dB. At point A2, at a second desired operating frequency of <NUM> (which may be another operating frequency needing improved isolation), the isolation curve <NUM> shows isolation of about <NUM> dB.

The isolation curve <NUM> may result from isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) without operations of the variable capacitor <NUM> and the variable capacitor 372_Y (<FIG>). For example, for the isolation curve, the capacitance of the variable capacitor <NUM> and the variable capacitor 372_Y may be considered to be at zero. For the isolation curve <NUM>, referring to <FIG>, the I/O bond pad <NUM> and the I/O bond pad 317_Y, the wiring <NUM> and the wiring 367_Y outside of the die <NUM>, and/or the I/O port <NUM> and the I/O port 357_Y (without the variable capacitor <NUM> and without the variable capacitor 372_Y) may be grounded to improve isolation. At point B1, at the operating frequency of <NUM>, the isolation curve <NUM> shows some improvement at <NUM> dB. At point B2, at the operating frequency of <NUM>, the isolation curve <NUM> shows some improvement at <NUM> dB.

The isolation curve <NUM> may be a result of, for example, isolation between the I/O port 352_1 and the I/O port 356_1 (<FIG>) having the variable capacitor <NUM> and the variable capacitor 372_Y (<FIG>) dynamically and actively tuned to nullified coupling (e.g., the coupling <NUM> of <FIG>) at a first desired operating frequency (e.g., <NUM>) and a second desired operating frequency (e.g., <NUM>). At point C1, at the operating frequency of <NUM>, the isolation curve <NUM> shows improved isolation at <NUM> dB. At point C2, at the operating frequency of <NUM>, the isolation curve <NUM> shows improved isolation at <NUM> dB. Referring to <FIG>, the control module <NUM> (e.g., as part of the at least one processor operating with the memory <NUM> in part) may be configured to dynamically, actively, and/or individually tune the variable capacitor <NUM> and the variable capacitor 372_Y to achieve the improved isolation at two different, desired operating frequencies. For example, the control module <NUM> may tune the variable capacitor <NUM> to nullify coupling at a first desired operating frequency (e.g., at <NUM>) and tune the variable capacitor 372_Y to nullify coupling at a second desired operating frequency (e.g., at <NUM>). Moreover, the desired operating frequencies may be further effected by the passive components (e.g., the inductor 337_A, the capacitor 337_B, and/or ground on the circuit board <NUM> at <FIG>) of the circuit board <NUM>.

<FIG> illustrates a method to adjust isolation among I/O ports, in accordance with certain aspects of the disclosure. The operations of <FIG> may be implemented by, for example, the apparatus <NUM> of <FIG> or <FIG>. The arrows indicate certain relationships among the operations, but not necessarily sequential relationships. At <NUM>, a first RF function is performed by a die, via a first I/O port. For example, referring to <FIG>, the apparatus <NUM> may include a device <NUM> and/or a circuit board <NUM>. The device <NUM>, which may be a packaged chip, a multi-die assembly, a multi-chip assembly, or a mixed-chip-die assembly, may include therein the die <NUM>. In some examples, the die <NUM> may include at least one processor performing various transceiver functions (e.g., the die <NUM> include a transceiver having at least one processor). The die <NUM> (e.g., the at least one processor) is coupled to a memory <NUM>, via a bus system <NUM>, to perform the transceiver functions (RF functions; transmitting and/or receiving RF signals). The I/O port 352_1 (e.g., the first I/O port) may be in instance of the I/O port 152_1 and a part of the first chain of RF circuits 140_1 (FGI. The device <NUM> (e.g., the device <NUM> of <FIG>) may include the die <NUM> to transmit RF signals (e.g., the first RF function) via the I/O port 352_1. The at least one processor may operate with the memory <NUM>, at least in part, to perform RF functions of the first chain of RF circuits 140_1 (FGI. For example, the at least one processor may receive instructions or parameters for the RF functions from the memory <NUM> via the bus system <NUM>.

At <NUM>, a variable capacitor electrically connected to a second I/O port is tuned to adjust isolation between the first I/O port and a third I/O port, the second I/O port being between the first I/O port and the third I/O port. Referring to <FIG>, for example, the variable capacitor <NUM> may be incorporated within the die <NUM> (e.g., semiconductor layers of the die <NUM> configured as the variable capacitor <NUM>). The variable capacitor <NUM> may be electrically connected to the I/O port <NUM> (e.g., the second I/O port). The die <NUM> (e.g., the at least one processor), via the control module <NUM>, tunes the variable capacitor <NUM> to reduce a coupling (e.g., the coupling <NUM> of <FIG>) between the I/O port 352_1 (e.g., the first I/O port) and the I/O port 356_1 (e.g., the third I/O port). In such fashion, isolation between the I/O port 352_1 (e.g., the first I/O port) and the I/O port 356_1 (e.g., the third I/O port) is adjusted or improved. See an operating example presented with <FIG>. The I/O port <NUM> (e.g., the second I/O port) may be physically disposed between the I/O port 352_1 (e.g., the first I/O port) and the I/O port 356_1 (e.g., the third I/O port)(see <FIG>).

In some examples, the control module <NUM> adjusts the setting of the variable capacitor <NUM> (to improve isolation between I/O ports) based on a determination of undesired coupling. Referring to <FIG>, the control module 148_1 may be configured to determine such undesired coupling based on, for example, information received via the I/O port 156_1. Such determination is made for changing operating conditions (e.g., when and where there are weak RF signaling) and/or for changing operating modes (e.g., the device <NUM> changes among different radio access technologies). In response, the control module <NUM> actively and dynamically adjusts the setting of the variable capacitor <NUM> to improve isolation between I/O ports, in response to changing operating conditions or operating modes.

At <NUM>, a second RF function is performed by the die via a third I/O port. For example, referring to <FIG>, the I/O port 356_1 (e.g., the third I/O port) may be in instance of the I/O port 156_1 and receives RF signal information from the second chain of RF circuits 140_2 (FGI. The device <NUM> (e.g., the device <NUM> of <FIG>) may include the die <NUM> to receive RF signal information (e.g., the second RF function) via the I/O port 356_1. The first RF function performed via the I/O port 352_1 (e.g., as part of the first chain of RF circuits 140_1 of <FIG>) and the second RF function performed via the I/O port 356_1 (e.g., receiving RF information from the second chain of RF circuits 140_2 of <FIG>) may be part of MIMO functions, and the I/O port 352_1 and the I/O port 356_1 may be part of a MIMO system. For example, the first chain of RF circuits 140_1 and the second chain of RF circuits 140_2 of <FIG> may transmit and receive RF signals to different antennae of the MIMO system. In some examples, the I/O port 352_1 (e.g., the first I/O port), the first I/O port, the second I/O port, and/or the third I/O port may be pins of the device <NUM>.

In some examples, the first I/O port, the second I/O port, and the third I/O port may be I/O bond pads of the die <NUM>. For example, the I/O bond pad 312_1 (the first I/O port) of the die <NUM> (<FIG>) may be an instance of the I/O port 152_1 of <FIG>. The I/O bond pad 316_1 (the second I/O port) of the die <NUM> (<FIG>) may be an instance of the I/O port 156_1 of <FIG>. The I/O bond pad <NUM> may correspond to the second I/O port. In such fashion, the variable capacitor <NUM> is tuned to reduce coupling (e.g., the coupling <NUM> of <FIG>) between the I/O bond pad 312_1 and the I/O bond pad 316_1 of the die <NUM> (<FIG>).

At <NUM>, a current is flowed between the variable capacitor and ground or at least one passive component on a circuit board, via the second I/O port. Referring to <FIG>, for example, the circuit board <NUM> may include passive elements (e.g., the inductor 337_A and the capacitor 337_B) and ground. The die <NUM> (e.g., the at least one processor via the control module <NUM>) may tune the variable capacitor <NUM> to reduce coupling and to improve isolation among I/O ports, as presented with <FIG>. The variable capacitor <NUM> is electrically connected to the inductor 337_A, the capacitor 337_B and/or ground (e.g., via the I/O bond pad <NUM> and the I/O port <NUM>) and thereby flows a current therebetween. See, for example, the current i2 in <FIG>. In some examples, the isolation circuit <NUM> performs on RF functions (e.g., the die <NUM> performs no RF functions via the I/O bond pad <NUM> and the I/O port <NUM>). For example, the isolation circuit <NUM> performs only isolation improvement function presented above. The isolation circuit <NUM>, including the variable capacitor <NUM>, is not electrically connected (e.g., there is no electrical energy flowing via a capacitor, resistor, inductor, or wire) and/or intentionally coupled to one or more antenna to perform intended RF functions, such as transmitting or receiving RF signals.

Claim 1:
An apparatus (<NUM>), comprising:
a device (<NUM>) comprising a die and comprising a first input or output, I/O, port (314_1, 354_1), a second I/O port (<NUM>, <NUM>), and a third I/O port (316_1, 356_1),
a circuit board outside the device, the circuit board including at least a portion of a radio frequency, RF, chain,
wherein the first, second, and third I/O ports are electrically coupled to the circuit board (<NUM>) and are electrically coupled to the die,
the second I/O port located between the first I/O port and the third I/O port, wherein the first, second, and third I/O ports are located along at least one geometric axis; and
a variable capacitor (<NUM>) electrically connected to the second I/O port and configurable to adjust isolation between the first I/O port and the third I/O port, wherein the variable capacitor is not electrically connected to an antenna contained in the circuit board,
wherein the variable capacitor is electrically connected to ground on the circuit board or is electrically connected to passive elements on the circuit board which are connected to ground.