Patent Description:
Modern computing devices may include general-purpose processor cores as well as a variety of hardware accelerators for offloading compute-intensive workloads or performing specialized tasks. Hardware accelerators may include, for example, one or more field-programmable gate arrays (FPGAs) which may include programmable digital logic resources that may be configured by the end user or system integrator. Hardware accelerators may also include one or more application-specific integrated circuits (ASICs). Hardware accelerators may be embodied as I/O devices that communicate with the processor core over an I/O interconnect. Additionally, hardware accelerators may include one or more graphics processing units (GPUs) implemented to process graphics data.

<CIT> relates to trusted local memory management in a virtualized GPU. An apparatus includes one or more processors including a trusted execution environment (TEE); a GPU including a trusted agent; and a memory, the memory including GPU local memory. The trusted agent tries to ensure proper allocation/deallocation of the local memory and verify translations between graphics physical addresses (PAs) and PAs for the apparatus. The local memory is partitioned into protection regions including a protected region and an unprotected region, and the protected region storse a memory permission table maintained by the trusted agent. The memory permission table includes any virtual function assigned to a trusted domain, a per process graphics translation table to translate between graphics virtual address (VA) to graphics guest PA (GPA), and a local memory translation table to translate between graphics GPAs and PAs for the local memory.

<CIT> discloses methods which include receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

<CIT> is directed to providing a secure address translation service. A system includes a memory for storage of data, an Input/Output Memory Management Unit (IOMMU) coupled to the memory via a host-to-device link the IOMMU to perform operations, comprising receiving a memory access request from a remote device via a host-to-device link, wherein the memory access request comprises a host physical address (HPA) that identifies a physical address within the memory pertaining to the memory access request and a first message authentication code (MAC), generating a second message authentication code (MAC) using the host physical address received with the memory access request and a private key associated with the remote device, and performing at least one of allowing the memory access to proceed when the first MAC and the second MAC match and the HPA is not in an invalidation tracking table (ITT) maintained by the IOMMU; or blocking the memory operation when the first MAC and the second MAC do not match.

Advantageous embodiments are subject to the dependent claims.

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

Referring now to <FIG>, a computing device <NUM> for secure I/O with an accelerator device includes a processor <NUM> and an accelerator device <NUM>, such as a field-programmable gate array (FPGA). In use, as described further below, a trusted execution environment (TEE) established by the processor <NUM> securely communicates data with the accelerator <NUM>. Data may be transferred using memory-mapped I/O (MMIO) transactions or direct memory access (DMA) transactions. For example, the TEE may perform an MMIO write transaction that includes encrypted data, and the accelerator <NUM> decrypts the data and performs the write. As another example, the TEE may perform an MMIO read request transaction, and the accelerator <NUM> may read the requested data, encrypt the data, and perform an MMIO read response transaction that includes the encrypted data. As yet another example, the TEE may configure the accelerator <NUM> to perform a DMA operation, and the accelerator <NUM> performs a memory transfer, performs a cryptographic operation (i.e., encryption or decryption), and forwards the result. As described further below, the TEE and the accelerator <NUM> generate authentication tags (ATs) for the transferred data and may use those ATs to validate the transactions. The computing device <NUM> may thus keep untrusted software of the computing device <NUM>, such as the operating system or virtual machine monitor, outside of the trusted code base (TCB) of the TEE and the accelerator <NUM>. Thus, the computing device <NUM> may secure data exchanged or otherwise processed by a TEE and an accelerator <NUM> from an owner of the computing device <NUM> (e.g., a cloud service provider) or other tenants of the computing device <NUM>. Accordingly, the computing device <NUM> may improve security and performance for multitenant environments by allowing secure use of accelerator devices.

The computing device <NUM> may be embodied as any type of device capable of performing the functions described herein. For example, the computing device <NUM> may be embodied as, without limitation, a computer, a laptop computer, a tablet computer, a notebook computer, a mobile computing device, a smartphone, a wearable computing device, a multiprocessor system, a server, a workstation, and/or a consumer electronic device. As shown in <FIG>, the illustrative computing device <NUM> includes a processor <NUM>, an I/O subsystem <NUM>, a memory <NUM>, and a data storage device <NUM>. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component. For example, the memory <NUM>, or portions thereof, may be incorporated in the processor <NUM> in some embodiments.

The processor <NUM> may be embodied as any type of processor capable of performing the functions described herein. For example, the processor <NUM> may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. As shown, the processor <NUM> illustratively includes secure enclave support <NUM>, which allows the processor <NUM> to establish a trusted execution environment known as a secure enclave, in which executing code may be measured, verified, and/or otherwise determined to be authentic. Additionally, code and data included in the secure enclave may be encrypted or otherwise protected from being accessed by code executing outside of the secure enclave. For example, code and data included in the secure enclave may be protected by hardware protection mechanisms of the processor <NUM> while being executed or while being stored in certain protected cache memory of the processor <NUM>. The code and data included in the secure enclave may be encrypted when stored in a shared cache or the main memory <NUM>. The secure enclave support <NUM> may be embodied as a set of processor instruction extensions that allows the processor <NUM> to establish one or more secure enclaves in the memory <NUM>. For example, the secure enclave support <NUM> may be embodied as Intel® Software Guard Extensions (SGX) technology.

The memory <NUM> may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory <NUM> may store various data and software used during operation of the computing device <NUM> such as operating systems, applications, programs, libraries, and drivers. As shown, the memory <NUM> may be communicatively coupled to the processor <NUM> via the I/O subsystem <NUM>, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor <NUM>, the memory <NUM>, and other components of the computing device <NUM>. For example, the I/O subsystem <NUM> may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, sensor hubs, host controllers, firmware devices, communication links (i.e., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.) and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the memory <NUM> may be directly coupled to the processor <NUM>, for example via an integrated memory controller hub. Additionally, in some embodiments, the I/O subsystem <NUM> may form a portion of a system-on-a-chip (SoC) and be incorporated, along with the processor <NUM>, the memory <NUM>, the accelerator device <NUM>, and/or other components of the computing device <NUM>, on a single integrated circuit chip. Additionally, or alternatively, in some embodiments the processor <NUM> may include an integrated memory controller and a system agent, which may be embodied as a logic block in which data traffic from processor cores and I/O devices converges before being sent to the memory <NUM>.

As shown, the I/O subsystem <NUM> includes a direct memory access (DMA) engine <NUM> and a memory-mapped I/O (MMIO) engine <NUM>. The processor <NUM>, including secure enclaves established with the secure enclave support <NUM>, may communicate with the accelerator device <NUM> with one or more DMA transactions using the DMA engine <NUM> and/or with one or more MMIO transactions using the MMIO engine <NUM>. The computing device <NUM> may include multiple DMA engines <NUM> and/or MMIO engines <NUM> for handling DMA and MMIO read/write transactions based on bandwidth between the processor <NUM> and the accelerator <NUM>. Although illustrated as being included in the I/O subsystem <NUM>, it should be understood that in some embodiments the DMA engine <NUM> and/or the MMIO engine <NUM> may be included in other components of the computing device <NUM> (e.g., the processor <NUM>, memory controller, or system agent), or in some embodiments may be embodied as separate components.

The data storage device <NUM> may be embodied as any type of device or devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, non-volatile flash memory, or other data storage devices. The computing device <NUM> may also include a communications subsystem <NUM>, which may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the computing device <NUM> and other remote devices over a computer network (not shown). The communications subsystem <NUM> may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, <NUM>, <NUM> LTE, etc.) to effect such communication.

The accelerator device <NUM> may be embodied as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a coprocessor, or other digital logic device capable of performing accelerated functions (e.g., accelerated application functions, accelerated network functions, or other accelerated functions), GPUs, etc. Illustratively, the accelerator device <NUM> is an FPGA, which may be embodied as an integrated circuit including programmable digital logic resources that may be configured after manufacture. The FPGA may include, for example, a configurable array of logic blocks in communication over a configurable data interchange. The accelerator device <NUM> may be coupled to the processor <NUM> via a highspeed connection interface such as a peripheral bus (e.g., a PCI Express bus) or an interprocessor interconnect (e.g., an in-die interconnect (IDI) or QuickPath Interconnect (QPI)), or via any other appropriate interconnect. The accelerator device <NUM> may receive data and/or commands for processing from the processor <NUM> and return results data to the processor <NUM> via DMA, MMIO, or other data transfer transactions.

As shown, the computing device <NUM> may further include one or more peripheral devices <NUM>. The peripheral devices <NUM> may include any number of additional input/output devices, interface devices, hardware accelerators, and/or other peripheral devices. For example, in some embodiments, the peripheral devices <NUM> may include a touch screen, graphics circuitry, a graphical processing unit (GPU) and/or processor graphics, an audio device, a microphone, a camera, a keyboard, a mouse, a network interface, and/or other input/output devices, interface devices, and/or peripheral devices.

Referring now to <FIG>, an illustrative embodiment of a field-programmable gate array (FPGA) <NUM> is shown. As shown, the FPGA <NUM> is one potential embodiment of an accelerator device <NUM>. The illustratively FPGA <NUM> includes a secure MMIO engine <NUM>, a secure DMA engine <NUM>, one or more accelerator functional units (AFUs) <NUM>, and memory/registers <NUM>. As described further below, the secure MMIO engine <NUM> and the secure DMA engine <NUM> perform in-line authenticated cryptographic operations on data transferred between the processor <NUM> (e.g., a secure enclave established by the processor) and the FPGA <NUM> (e.g., one or more AFUs <NUM>). In some embodiments, the secure MMIO engine <NUM> and/or the secure DMA engine <NUM> may intercept, filter, or otherwise process data traffic on one or more cache-coherent interconnects, internal buses, or other interconnects of the FPGA <NUM>.

Each AFU <NUM> may be embodied as logic resources of the FPGA <NUM> that are configured to perform an acceleration task. Each AFU <NUM> may be associated with an application executed by the computing device <NUM> in a secure enclave or other trusted execution environment. Each AFU <NUM> may be configured or otherwise supplied by a tenant or other user of the computing device <NUM>. For example, each AFU <NUM> may correspond to a bitstream image programmed to the FPGA <NUM>. As described further below, data processed by each AFU <NUM>, including data exchanged with the trusted execution environment, may be cryptographically protected from untrusted components of the computing device <NUM> (e.g., protected from software outside of the trusted code base of the tenant enclave). Each AFU <NUM> may access or otherwise process stored in the memory/registers <NUM>, which may be embodied as internal registers, cache, SRAM, storage, or other memory of the FPGA <NUM>. In some embodiments, the memory <NUM> may also include external DRAM or other dedicated memory coupled to the FPGA <NUM>.

Referring now to <FIG>, in an illustrative embodiment, the computing device <NUM> establishes an environment <NUM> during operation. The illustrative environment <NUM> includes a trusted execution environment (TEE) <NUM> and the accelerator <NUM>. The TEE <NUM> further includes a trusted agent <NUM>, host cryptographic engine <NUM>, a transaction dispatcher <NUM>, a host validator <NUM>, and a direct memory access (DMA) manager <NUM>. The accelerator <NUM> includes an accelerator cryptographic engine <NUM>, a memory range selection engine <NUM>, an accelerator validator <NUM>, a memory mapper <NUM>, an authentication tag (AT) controller <NUM>, and a DMA engine <NUM>. The various components of the environment <NUM> may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment <NUM> may be embodied as circuitry or collection of electrical devices (e.g., host cryptographic engine circuitry <NUM>, transaction dispatcher circuitry <NUM>, host validator circuitry <NUM>, DMA manager circuitry <NUM>, accelerator cryptographic engine circuitry <NUM>, accelerator validator circuitry <NUM>, memory mapper circuitry <NUM>, AT controller circuitry <NUM>, and/or DMA engine circuitry <NUM>). It should be appreciated that, in such embodiments, one or more of the host cryptographic engine circuitry <NUM>, the transaction dispatcher circuitry <NUM>, the host validator circuitry <NUM>, the DMA manager circuitry <NUM>, the accelerator cryptographic engine circuitry <NUM>, the accelerator validator circuitry <NUM>, the memory mapper circuitry <NUM>, the AT controller circuitry <NUM>, and/or the DMA engine circuitry <NUM> may form a portion of the processor <NUM>, the I/O subsystem <NUM>, the accelerator <NUM>, and/or other components of the computing device <NUM>. Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another.

The TEE <NUM> may be embodied as a trusted execution environment of the computing device <NUM> that is authenticated and protected from unauthorized access using hardware support of the computing device <NUM>, such as the secure enclave support <NUM> of the processor <NUM>. Illustratively, the TEE <NUM> may be embodied as one or more secure enclaves established using Intel SGX technology. The TEE <NUM> may also include or otherwise interface with one or more drivers, libraries, or other components of the computing device <NUM> to interface with the accelerator <NUM>.

The host cryptographic engine <NUM> is configured to generate an authentication tag (AT) based on a memory-mapped I/O (MMIO) transaction and to write that AT to an AT register of the accelerator <NUM>. For an MMIO write request, the host cryptographic engine <NUM> is further configured to encrypt a data item to generate an encrypted data item, and the AT is generated in response to encrypting the data item. For an MMIO read request, the AT is generated based on an address associated with MMIO read request.

The transaction dispatcher <NUM> is configured to dispatch the memory-mapped I/O transaction (e.g., an MMIO write request or an MMIO read request) to the accelerator <NUM> after writing the calculated AT to the AT register. An MMIO write request may be dispatched with the encrypted data item.

The host validator <NUM> may be configured to verify that an MMIO write request succeeded in response dispatching the MMIO write request. Verifying that the MMIO write request succeeded may include securely reading a status register of the accelerator <NUM>, securely reading a value at the address of the MMIO write from the accelerator <NUM>, or reading an AT register of the accelerator <NUM> that returns an AT value calculated by the accelerator <NUM>, as described below. For MMIO read requests, the host validator <NUM> may be further configured to generate an AT based on an encrypted data item included in a MMIO read response dispatched from the accelerator <NUM>; read a reported AT from a register of the accelerator <NUM>; and determine whether the AT generated by the TEE <NUM> matches the AT reported by the accelerator <NUM>. The host validator <NUM> may be further configured to indicate an error if those ATs do not match, which provides assurance that data was not modified on the way from the TEE <NUM> to the accelerator <NUM>.

The accelerator cryptographic engine <NUM> is configured to perform a cryptographic operation associated with the MMIO transaction and to generate an AT based on the MMIO transaction in response to the MMIO transaction being dispatched. For an MMIO write request, the cryptographic operation includes decrypting an encrypted data item received from the TEE <NUM> to generate a data item, and the AT is generated based on the encrypted data item. For an MMIO read request, the cryptographic operation includes encrypting a data item from a memory of the accelerator <NUM> to generate an encrypted data item, and the AT is generated based on that encrypted data item.

The accelerator validator <NUM> is configured to determine whether the AT written by the TEE <NUM> matches the AT determined by the accelerator <NUM>. The accelerator validator <NUM> is further configured to drop the MMIO transaction if those ATs do not match. For MMIO read requests, the accelerator validator <NUM> may be configured to generate a poisoned AT in response to dropping the MMIO read request, and may be further configured to dispatch a MMIO read response with a poisoned data item to the TEE <NUM> in response to dropping the MMIO read request.

The memory mapper <NUM> is configured to commit the MMIO transaction in response to determining that the AT written by the TEE <NUM> matches the AT generated by the accelerator <NUM>. For an MMIO write request, committing the transaction may include storing the data item in a memory of the accelerator <NUM>. The memory mapper <NUM> may be further configured to set a status register to indicate success in response to storing the data item. For an MMIO read request, committing the transaction may include reading the data item at the address in the memory of the accelerator <NUM> and dispatching an MMIO read response with the encrypted data item to the TEE <NUM>.

The DMA manager <NUM> is configured to securely write an initialization command to the accelerator <NUM> to initialize a secure DMA transfer. The DMA manager <NUM> is further configured to securely configure a descriptor indicative of a host memory buffer, an accelerator <NUM> buffer, and a transfer direction. The transfer direction may be host to accelerator <NUM> or accelerator <NUM> to host. The DMA manager <NUM> is further configured to securely write a finalization command to the accelerator <NUM> to finalize an authentication tag (AT) for the secure DMA transfer. The initialization command, the descriptor, and the finalization command may each be securely written and/or configured with an MMIO write request. The DMA manager <NUM> may be further configured to determine whether to transfer additional data in response to securely configuring the descriptor, the finalization command may be securely written in response to determining that no additional data remains for transfer.

The AT controller <NUM> is configured to initialize an AT in response to the initialization command from the TEE <NUM>. The AT controller <NUM> is further configured to finalize the AT in response to the finalization command from the TEE <NUM>.

The DMA engine <NUM> is configured to transfer data between the host memory buffer and the accelerator <NUM> buffer in response to the descriptor from the TEE <NUM>. For a transfer from host to accelerator <NUM>, transferring the data includes copying encrypted data from the host memory buffer and forwarding the plaintext data to the accelerator <NUM> buffer in response to decrypting the encrypted data. For a transfer from accelerator <NUM> to host, transferring the data includes copying plaintext data from the accelerator <NUM> buffer and forwarding encrypted data to the host memory buffer in response encrypting the plaintext data.

The accelerator cryptographic engine <NUM> is configured to perform a cryptographic operation with the data in response to transferring the data and to update the AT in response to transferring the data. For a transfer from host to accelerator <NUM>, performing the cryptographic operation includes decrypting encrypted data to generate plaintext data. For a transfer from accelerator <NUM> to host, performing the cryptographic operation includes encrypting plaintext data to generate encrypted data.

The host validator <NUM> is configured to determine an expected AT based on the secure DMA transfer, to read the AT from the accelerator <NUM> in response to securely writing the finalization command, and to determine whether the AT from the accelerator <NUM> matches the expected AT. The host validator <NUM> may be further configured to indicate success if the ATs match and to indicate failure if the ATs do not match.

<FIG> illustrates another embodiment of a computing device <NUM>. Computing device <NUM> represents a communication and data processing device including or representing (without limitations) smart voice command devices, intelligent personal assistants, home / office automation system, home appliances (e.g., washing machines, television sets, etc.), mobile devices (e.g., smartphones, tablet computers, etc.), gaming devices, handheld devices, wearable devices (e.g., smartwatches, smart bracelets, etc.), virtual reality (VR) devices, head - mounted display (HMDs) , Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, set - top boxes (e.g., Internet based cable television set - top boxes, etc.), global positioning system (GPS) - based devices, automotive infotainment devices, etc..

In some embodiments, computing device <NUM> includes or works with or is embedded in or facilitates any number and type of other smart devices, such as (without limitation) autonomous machines or artificially intelligent agents, such as a mechanical agents or machines, electronics agents or machines, virtual agents or machines, electromechanical agents or machines, etc. Examples of autonomous machines or artificially intelligent agents may include (without limitation) robots, autonomous vehicles (e.g., self-driving cars, self - flying planes, self - sailing boats, etc.), autonomous equipment self - operating construction vehicles, self-operating medical equipment, etc.) , and / or the like. Further, "autonomous vehicles" are not limed to automobiles but that they may include any number and type of autonomous machines, such as robots, autonomous equipment, household autonomous devices, and/or the like, and any one or more tasks or operations relating to such autonomous machines may be interchangeably referenced with autonomous driving.

Further, for example, computing device <NUM> may include a computer platform hosting an integrated circuit ("IC"), such as a system on a chip ("SOC" or "SOC") , integrating various hardware and / or software components of computing device <NUM> on a single chip.

As illustrated, in one embodiment, computing device <NUM> may include any number and type of hardware and / or software components, such as (without limitation) graphics processing unit ("GPU" or simply "graphics processor") <NUM>, graphics driver (also referred to as "GPU driver", "graphics driver logic", "driver logic", user-mode driver (UMD), user-mode driver framework (UMDF), or simply "driver ") <NUM>, central processing unit ("CPU" or simply "application processor") <NUM>, hardware accelerator <NUM> (such as an FPGA, ASIC, a re-purposed CPU, or a re-purposed GPU, for example), memory <NUM>, network devices, drivers, or the like, as well as input/output (I/O) sources <NUM>, such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc. Computing device <NUM> may include operating system (OS) <NUM> serving as an interface between hardware and/or physical resources of the computing device <NUM> and a user.

It is to be appreciated that a lesser or more equipped system than the example described above may be utilized for certain implementations. Therefore, the configuration of computing device <NUM> may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances.

Embodiments may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a parent board, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). The terms "logic", "module", "component", "engine", "circuitry", "element", and "mechanism" may include, by way of example, software, hardware and / or a combination thereof , such as firmware.

Computing device <NUM> may host network interface device(s) to provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN) , Bluetooth , a cloud network, a mobile network (e.g., 3rd Generation (<NUM>), 4th Generation (<NUM>), etc.), an intranet, the Internet, etc. Network interface(s) may include, for example, a wireless network interface having antenna, which may represent one or more antenna(s). Network interface(s) may also include, for example, a wired network interface to communicate with remote devices via network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

Embodiments may be provided, for example, as a computer program product which may include one or more machine - readable media having stored thereon machine executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein. A machine - readable medium may include, but is not limited to, floppy diskettes , optical disks, CD - ROMs (Compact Disc - Read Only Memories), and magneto - optical disks, ROMs, RAMS, EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories) , magnetic or optical cards, flash memory, or other type of media / machine - readable medium suitable for storing machine - executable instructions.

Moreover, embodiments may be downloaded as a computer program product , wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client ) by way of one or more data signals embodied in and / or modulated by a carrier wave or other propagation medium via a communication link (e.g., a modem and / or network connection).

Throughout the document, term "user" may be interchangeably referred to as "viewer", "observer", "speaker", "person", "individual", "end - user", and / or the like. It is to be noted that throughout this document, terms like "graphics domain" may be referenced interchangeably with "graphics processing unit", "graphics processor", or simply "GPU" and similarly, "CPU domain" or "host domain" may be referenced interchangeably with "computer processing unit", "application processor", or simply "CPU".

It is to be noted that terms like "node", "computing node", "server", "server device", "cloud computer", "cloud server", "cloud server computer", "machine", "host machine", "device", "computing device", "computer", "computing system", and the like, may be used interchangeably throughout this document. It is to be further noted that terms like "application", "software application", "program", "software program", "package", "software package", and the like, may be used interchangeably throughout this document. Also, terms like "job", "input", "request", "message ", and the like, may be used interchangeably throughout this document.

<FIG> illustrates one embodiment of a distributed computing platform <NUM>, according to an embodiment of the invention. As shown in <FIG>, platform <NUM> includes computer systems A and B that are coupled (e.g., via a network). In one embodiment, each system includes host <NUM> (e.g., 510A and 510B) and an accelerator <NUM> (e.g., 520A and 520B). Each host operates a trusted execution environment (TEE) <NUM> (e.g., 505A and 505B) that secures an application <NUM> and a user-mode driver (UMD) <NUM> (e.g., 502A and 502B). In such an embodiment, TEE <NUM> provides for a secure interface (or channel) between each host <NUM> and its respective accelerator <NUM>.

According to one embodiment, a UMD <NUM> may issue instructions instructs received at a kernel mode driver (KMD) to perform an operation at an accelerator 520A. For example, UMD 502A may issue an instruction to perform an operation to store a result at a virtual address (e.g., result @ va1) at accelerator 520A, while UMD 502B may issue an instruction to perform an operation to read data from a first virtual address at accelerator 520B and store the data at a second virtual address at accelerator 520B (read from va1' (=va1@acc1) into va2').

Each KMD <NUM> programs and controls a page table <NUM> within a respective accelerator, and facilitates execution of instructions from a host <NUM> at an accelerator <NUM> via page tables <NUM>. Page tables <NUM> include a mapping between virtual addresses (VAs) and physical addresses (PAs). For example, page table 524A at accelerator 520A maps va1 to pa1. Each accelerator <NUM> also includes local memory <NUM>, which includes a kernel (or program code) that, when executed by one or more processing units <NUM>, computes the results indicated by the UMD <NUM> operation and stores the result in a PA in memory <NUM> mapped to the VA indicated in the operation. For example, the kernel within memory 522A, when executed by the one or more processing units 540A, computes the result and writes the results to va1. As shown in page table 524A va1 maps to pa1, which is where the result is stored within memory 522A.

The operation within accelerator 520B operates similarly. For example, the kernel within memory 522B, when executed by the one or more processing units 540B, reads from va1'and computes a result that is stored into va2. However, page table 524B indicates that va1' maps to pa1 located in memory 522A of accelerator 520A. Thus, accelerator 520B needs to read the memory 522A.

However, a security issue exists with the sharing of memory 522A accelerator 520B. The problem is that local memory <NUM> is conventionally managed by the host KMD <NUM>, which is outside the trusted computing base (TCB) of the host TEE <NUM>. Accordingly, workloads in local memory <NUM> may be vulnerable to multiple different attacks, such as attacks via page table address translation manipulations. For example, data belonging to a victim on accelerator 520A may be provided to an attacker running on accelerator 520B, causing loss of confidentiality due to unauthorized access. Additionally, data may be read from an incorrect address on accelerator 520A into accelerator 520B (or incorrect number of bytes can be read), compromising the integrity of the result computed on accelerator 520B.

According to one embodiment, each accelerator <NUM> incudes a trusted agent <NUM> (e.g., 530A and 530B) that is implemented to validate address translations submitted by a KMD <NUM>. In such an embodiment, trusted agent <NUM> receives a randomly generated key (or token) from host 510A that is used to validate an accelerator <NUM> (e.g., accelerator 520B) requesting access to local memory <NUM> (e.g., 522A) access prior to sharing data. In a further embodiment, the token is shared with both trusted agents 530A and 530B prior to memory sharing, and is used to confirm that an external accelerator <NUM> has been authorized to access the local memory <NUM> of another accelerator <NUM>. Accordingly, trusted agents <NUM> use a token to validate address translations to ensure that memory sharing between accelerator 520A and accelerator 520B may be performed in a trusted manner.

In one embodiment, the token is shared during a shared memory protocol. <FIG> is a flow diagram illustrating one embodiment of the memory sharing protocol. At processing block <NUM>, UMD 502A (or UMD1) transmits a message to UMD 502B (or UMD2) indicating an exported buffer at a VA (e.g., address va) of a location at memory 522A that is to be shared. Additionally, the message includes a token (T) to be used authorize memory sharing. At processing block <NUM>, UMD1 transmits an authorization message to trusted agent 530A (or trusted agent <NUM>) indicating that trusted agent <NUM> is to export a particular byte length (e.g., len bytes) at address va to accelerator 520B (or accelerator <NUM>) upon receiving the token.

At processing block <NUM>, UMD2 transmits a message to trusted agent 530B (or trusted agent <NUM>) indicating that buffer of byte length is to be imported from virtual address va' into memory 522B at accelerator <NUM> using the token. In one embodiment, KMD 504A and 504B ensures that va maps to pa on 520A and va' maps to pa' on 520B, respectively, and that pa = pa'. As a result, the physical address of the exported buffer on 520A matches the source address for the buffer imported on 520B. At processing block <NUM>, confirms whether the translation entry (e.g., va' -> pa') is validated (e.g., whether the entry is present in page table 524B. In one embodiment, the confirmation is performed by determining whether a present bit associated with the translation entry in the page table is enabled. Trusted agent <NUM> flags an unvalidated translation entry.

At processing block <NUM>, trusted agent <NUM> transmits a message to trusted agent <NUM> including the token and a request to import a byte length into physical address pa' (e.g., import len, pa', T). At processing block <NUM>, trusted agent <NUM> validates the request using the previous export authorization from UMD1. As a result, trusted agent <NUM> validates the requestor using the token (e.g., accelerator <NUM>, len, T). For example, trusted agent <NUM> determines whether the token received from UMD1 matches the token received from trusted agent <NUM>. Additionally, trusted agent <NUM> validates whether the accelerator <NUM> and accelerator <NUM> physical addresses match (e.g., pa (from va->pa mapping) = pa').

At processing block <NUM>, trusted agent <NUM> transmits a message to trusted agent <NUM> indicating that the results of the validation. In one embodiment, accelerator <NUM> is granted access to the memory 522A upon a determination that the validation passes, and is not granted access to the memory 522A upon a determination that the validation fails. At processing block <NUM>, trusted agent <NUM> flags its page table entry is valid upon receiving an indication that the physical addresses match. Subsequently, accelerator <NUM> has shared access to memory at accelerator <NUM>. <FIG> is a sequence diagram illustrating another embodiment of the process.

Although described above with reference to memory reads, the above-described mechanism similarly processes memory writes. Thus, the above-described mechanism prevents untrusted software from bypassing sharing protocols since a trusted agent requires a protocol to be followed prior to permitting external memory access. Validation of token prevents a malicious application from requesting an import of memory that was not authorized, while physical address validation prevents copying from incorrect memory addresses or an incorrect number of bytes. Additionally, embodiments may be implemented in a network having more than accelerators 520A and 520B. In such embodiments, the above-described process is implemented to enable an external accelerator to access the local memory of another accelerator.

<FIG> is a schematic diagram of an illustrative electronic computing device to enable enhanced protection against adversarial attacks according to some embodiments. In some embodiments, the computing device <NUM> includes one or more processors <NUM> including one or more processors cores <NUM> and a TEE <NUM>, the TEE including a machine learning service enclave (MLSE) <NUM>. In some embodiments, the computing device <NUM> includes a hardware accelerator <NUM>, the hardware accelerator including a cryptographic engine <NUM> and a machine learning model <NUM>. In some embodiments, the computing device is to provide enhanced protections against ML adversarial attacks, as provided in <FIG>.

The computing device <NUM> may additionally include one or more of the following: cache <NUM>, a graphical processing unit (GPU) <NUM> (which may be the hardware accelerator in some implementations), a wireless input/output (I/O) interface <NUM>, a wired I/O interface <NUM>, memory circuitry <NUM>, power management circuitry <NUM>, non-transitory storage device <NUM>, and a network interface <NUM> for connection to a network <NUM>. The following discussion provides a brief, general description of the components forming the illustrative computing device <NUM>. Example, non-limiting computing devices <NUM> may include a desktop computing device, blade server device, workstation, or similar device or system.

In embodiments, the processor cores <NUM> are capable of executing machine-readable instruction sets <NUM>, reading data and/or instruction sets <NUM> from one or more storage devices <NUM> and writing data to the one or more storage devices <NUM>. Those skilled in the relevant art will appreciate that the illustrated embodiments as well as other embodiments may be practiced with other processor-based device configurations, including portable electronic or handheld electronic devices, for instance smartphones, portable computers, wearable computers, consumer electronics, personal computers ("PCs"), network PCs, minicomputers, server blades, mainframe computers, and the like.

The processor cores <NUM> may include any number of hardwired or configurable circuits, some or all of which may include programmable and/or configurable combinations of electronic components, semiconductor devices, and/or logic elements that are disposed partially or wholly in a PC, server, or other computing system capable of executing processor-readable instructions.

The computing device <NUM> includes a bus or similar communications link <NUM> that communicably couples and facilitates the exchange of information and/or data between various system components including the processor cores <NUM>, the cache <NUM>, the graphics processor circuitry <NUM>, one or more wireless I/O interfaces <NUM>, one or more wired I/O interfaces <NUM>, one or more storage devices <NUM>, and/or one or more network interfaces <NUM>. The computing device <NUM> may be referred to in the singular herein, but this is not intended to limit the embodiments to a single computing device <NUM>, since in certain embodiments, there may be more than one computing device <NUM> that incorporates, includes, or contains any number of communicably coupled, collocated, or remote networked circuits or devices.

The processor cores <NUM> may include any number, type, or combination of currently available or future developed devices capable of executing machine-readable instruction sets.

The processor cores <NUM> may include (or be coupled to) but are not limited to any current or future developed single- or multi-core processor or microprocessor, such as: on or more systems on a chip (SOCs); central processing units (CPUs); digital signal processors (DSPs); graphics processing units (GPUs); application-specific integrated circuits (ASICs), programmable logic units, field programmable gate arrays (FPGAs), and the like. Unless described otherwise, the construction and operation of the various blocks shown in <FIG> are of conventional design. Consequently, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art. The bus <NUM> that interconnects at least some of the components of the computing device <NUM> may employ any currently available or future developed serial or parallel bus structures or architectures.

The system memory <NUM> may include read-only memory ("ROM") <NUM> and random access memory ("RAM") <NUM>. A portion of the ROM <NUM> may be used to store or otherwise retain a basic input/output system ("BIOS") <NUM>. The BIOS <NUM> provides basic functionality to the computing device <NUM>, for example by causing the processor cores <NUM> to load and/or execute one or more machine-readable instruction sets <NUM>. In embodiments, at least some of the one or more machine-readable instruction sets <NUM> cause at least a portion of the processor cores <NUM> to provide, create, produce, transition, and/or function as a dedicated, specific, and particular machine, for example a word processing machine, a digital image acquisition machine, a media playing machine, a gaming system, a communications device, a smartphone, or similar.

The computing device <NUM> may include at least one wireless input/output (I/O) interface <NUM>. The at least one wireless I/O interface <NUM> may be communicably coupled to one or more physical output devices <NUM> (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wireless I/O interface <NUM> may communicably couple to one or more physical input devices <NUM> (pointing devices, touchscreens, keyboards, tactile devices, etc.). The at least one wireless I/O interface <NUM> may include any currently available or future developed wireless I/O interface. Example wireless I/O interfaces include, but are not limited to: BLUETOOTH®, near field communication (NFC), and similar.

The computing device <NUM> may include one or more wired input/output (I/O) interfaces <NUM>. The at least one wired I/O interface <NUM> may be communicably coupled to one or more physical output devices <NUM> (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wired I/O interface <NUM> may be communicably coupled to one or more physical input devices <NUM> (pointing devices, touchscreens, keyboards, tactile devices, etc.). The wired I/O interface <NUM> may include any currently available or future developed I/O interface. Example wired I/O interfaces include, but are not limited to: universal serial bus (USB), IEEE <NUM> ("FireWire"), and similar.

The computing device <NUM> may include one or more communicably coupled, non-transitory, data storage devices <NUM>. The data storage devices <NUM> may include one or more hard disk drives (HDDs) and/or one or more solid-state storage devices (SSDs). The one or more data storage devices <NUM> may include any current or future developed storage appliances, network storage devices, and/or systems. Non-limiting examples of such data storage devices <NUM> may include, but are not limited to, any current or future developed non-transitory storage appliances or devices, such as one or more magnetic storage devices, one or more optical storage devices, one or more electro-resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof. In some implementations, the one or more data storage devices <NUM> may include one or more removable storage devices, such as one or more flash drives, flash memories, flash storage units, or similar appliances or devices capable of communicable coupling to and decoupling from the computing device <NUM>.

The one or more data storage devices <NUM> may include interfaces or controllers (not shown) communicatively coupling the respective storage device or system to the bus <NUM>. The one or more data storage devices <NUM> may store, retain, or otherwise contain machine-readable instruction sets, data structures, program modules, data stores, databases, logical structures, and/or other data useful to the processor cores <NUM> and/or graphics processor circuitry <NUM> and/or one or more applications executed on or by the processor cores <NUM> and/or graphics processor circuitry <NUM>. In some instances, one or more data storage devices <NUM> may be communicably coupled to the processor cores <NUM>, for example via the bus <NUM> or via one or more wired communications interfaces <NUM> (e.g., Universal Serial Bus or USB); one or more wireless communications interfaces <NUM> (e.g., Bluetooth®, Near Field Communication or NFC); and/or one or more network interfaces <NUM> (IEEE <NUM> or Ethernet, IEEE <NUM>, or Wi-Fi®, etc.).

Processor-readable instruction sets <NUM> and other programs, applications, logic sets, and/or modules may be stored in whole or in part in the system memory <NUM>. Such instruction sets <NUM> may be transferred, in whole or in part, from the one or more data storage devices <NUM>. The instruction sets <NUM> may be loaded, stored, or otherwise retained in system memory <NUM>, in whole or in part, during execution by the processor cores <NUM> and/or graphics processor circuitry <NUM>.

The computing device <NUM> may include power management circuitry <NUM> that controls one or more operational aspects of the energy storage device <NUM>. In embodiments, the energy storage device <NUM> may include one or more primary (i.e., non-rechargeable) or secondary (i.e., rechargeable) batteries or similar energy storage devices. In embodiments, the energy storage device <NUM> may include one or more supercapacitors or ultracapacitors. In embodiments, the power management circuitry <NUM> may alter, adjust, or control the flow of energy from an external power source <NUM> to the energy storage device <NUM> and/or to the computing device <NUM>. The power source <NUM> may include, but is not limited to, a solar power system, a commercial electric grid, a portable generator, an external energy storage device, or any combination thereof.

For convenience, the processor cores <NUM>, the graphics processor circuitry <NUM>, the wireless I/O interface <NUM>, the wired I/O interface <NUM>, the storage device <NUM>, and the network interface <NUM> are illustrated as communicatively coupled to each other via the bus <NUM>, thereby providing connectivity between the above-described components. In alternative embodiments, the above-described components may be communicatively coupled in a different manner than illustrated in <FIG>. For example, one or more of the above-described components may be directly coupled to other components, or may be coupled to each other, via one or more intermediary components (not shown). In another example, one or more of the above-described components may be integrated into the processor cores <NUM> and/or the graphics processor circuitry <NUM>. In some embodiments, all or a portion of the bus <NUM> may be omitted and the components are coupled directly to each other using suitable wired or wireless connections.

The above Detailed Description includes references to the accompanying drawings, which form a part of the Detailed Description. The drawings show, by way of illustration, specific embodiments that may be practiced. " Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

" In addition, "a set of" includes one or more elements. In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein. " Also, in the following claims, the terms "including" and "comprising" are openended; that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," "third," etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.

The terms "logic instructions" as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and examples are not limited in this respect.

The terms "computer readable medium" as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and examples are not limited in this respect.

The term "logic" as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and examples are not limited in this respect.

Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.

Claim 1:
An apparatus comprising:
a first host (510A); and
a first accelerator (520A) communicatively coupled to the first host (510A), including:
a first memory (522A);
a first page table (524A) to perform a translation of virtual addresses to physical addresses in the first memory (522A); and
a first trusted agent (530A) to validate the address translations, wherein the first trusted agent (530A) validating the address translations comprises:
using tokens to validate a request to access the first memory (522A), wherein the request is received from a second trusted agent (53oB) at a second accelerator (520B) and includes a physical address to be accessed in the first memory (522A), and
determining whether the physical address in said request received from the second trusted agent (530B) matches a physical address associated with a virtual address received from the host.