Patent Description:
A memory with column redundancy will include redundancy logic that determines whether a read or write operation to a column should be shifted to an adjacent column due to a column defect. Each column includes redundancy multiplexers for the shifting of the read or write operation to the adjacent column. However, existing design-for-test (DFT) scan chains do not test for errors in the redundancy logic or in the redundancy multiplexers. Further attention is drawn to <CIT> describing a memory comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch. Attention is also drawn to <CIT> describing a memory which includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

Further embodiments of the invention are described in the dependent claims.

These and additional advantages may be better appreciated through the following detailed description.

Implementations of the disclosure and their advantages are best understood by referring to the detailed description that follows.

Improved column redundancy schemes are provided for memories to allow a DFT scan chain to scan for errors in the redundancy logic and in a column's redundancy multiplexers. An example memory <NUM> with this improved column redundancy is shown in <FIG>. Memory <NUM> includes a plurality of N + <NUM> columns of bitcells, ranging from an Nth column to a zeroth column, N being a positive integer. Memory <NUM> also includes at least one redundant column. For brevity, the expression "column" without any further clarification will be understood herein to refer to a non-redundant column. During testing of memory <NUM>, it may be the case that there are no defective columns. In that case, the redundant column (or columns) is not used. A read or write operation that is addressed to a particular column will thus occur to that column. All of the columns many then be deemed to be un-shifted columns since there is no shifting as column redundancy is not enabled. But that is not the case if there is a defective column. The array of columns may then be divided into un-shifted columns and shifted columns depending upon the location of the defective column. For example, suppose that an ith column is defective. The subsequent columns from an (i + <NUM>)th column up to the (N + <NUM>) column are un-shifted whereas the preceding columns from the ith column to the zeroth column are shifted. For example, if a read or write operation is addressed to the zeroth column when column redundancy is enabled, the read or write operation actually occurs to the redundant column.

To implement column redundancy, a fuse decoder (not illustrated) may function to decode a fuse word to produce a plurality of decoded redundancy address signals. For example, the decoding may produce three decoded redundancy address signals fa<<NUM>:<NUM>>, fb<<NUM>:<NUM>>, and fc<<NUM>:<NUM>>. The number of decoded address redundancy signals and their bit width may be varied in alternative implementations. To process the decoded redundancy address signals, each column is associated with a corresponding redundancy logic circuit. There is thus an Nth redundancy logic circuit (red logic col (N)) for the Nth column, a (N-<NUM>)th redundancy logic circuit (red logic col (N-<NUM>)) for the (N-<NUM>)th column, and so on such that there is a zeroth redundancy logic circuit (red logic col (<NUM>)) for the zeroth column. Each column's redundancy logic circuit receives one bit each from the decoded redundancy address signals fa<<NUM>:<NUM>>, fb<<NUM>:<NUM>>, and fc<<NUM>:<NUM>>. Each redundancy logic circuit thus receives three redundancy address bits fa, fb, and fc.

In one implementation, the decoded redundancy address bits fa, fb, and fc are active low. The defective column is thus identified by its decoded redundancy address bits fa, fb, and fc all being logical zeroes in an active-low implementation. Alternatively, an active-high implementation may be used in which the decoded redundancy address bits fa, fb, and fc would all be logical ones. As used herein, a binary signal is deemed to be asserted when the binary logic signal is true, regardless of whether the true binary state is represented by an active-low or an active-high convention. Each redundancy logic circuit is configured to assert a column redundancy signal (designated as match_next) should its decoded redundancy address bits fa, fb, and fc be logically true (asserted). The terms "column redundancy signal" and "match_next" are used interchangeably herein. In an active-high implementation, each redundancy logic circuit is thus configured to assert its match_next signal if its bits fa, fb, and fc are all binary ones.

The redundancy logic circuits may be deemed to be arranged in series starting from the Nth redundancy logic circuit to the zeroth redundancy logic circuit. The match_next signal from a preceding redundancy logic circuit in this serial arrangement is received as a match_prev signal at the subsequent redundancy logic circuit. For example, the match_next signal from the Nth redundancy logic circuit is received by the (N-<NUM>)th redundancy logic circuit as its match_prev signal. Each redundancy logic circuit is configured to assert its match_next signal if its match_prev signal was asserted. In the example discussed earlier in which the ith column is the defective column, the ith redundancy logic circuit will thus asserts its match_next signal. The subsequent redundancy logic circuits from the (i-<NUM>)th redundancy logic circuit to the zeroth redundancy logic circuit will thus also assert their match_next signal since each of their match_prev signals will be asserted. In the following discussion, it will be assumed that the match_next signal is a logic-high signal such that it is a logical one when asserted.

An example redundancy logic circuit <NUM> is shown in more detail in <FIG>. A logic gate such as a NAND gate <NUM> processes the fa, fb, and fc decoded redundancy address bits to produce an output signal that is inverted by an inverter <NUM>. A NOR gate <NUM> NORs an output signal from inverter <NUM> with the match_prev signal. An inverter <NUM> inverts an output signal from NOR gate <NUM> to produce the match_next signal. If any one of the bits fa, fb, and fc is a logical zero, the output of NAND gate <NUM> is a logical one. This logical one is inverted by inverter <NUM> to produce a logical zero to NOR gate <NUM>. If the match_prev signal is a logical zero as well, the output of NOR gate <NUM> will thus be a logical one that is inverted by inverter <NUM> to force the match_next signal to be logical zero. However, if fa, fb, and fc bit signals are all logical ones and/or the match_prev signal is a logical one, the match_next signal is asserted.

Referring again to memory <NUM>, note that each column receives the match_next signal from its corresponding redundancy logic circuit. As will be explained further herein, each column includes a write column redundancy multiplexer and a read column redundancy multiplexer. In a write operation to a column having an asserted match_next signal, the write column redundancy multiplexer directs the write data bit to the preceding column. For example, if the ith column has an asserted match_next signal, its write column redundancy multiplexer directs the write data bit to be written to the (i-<NUM>)th column. But if the ith column has a false match_next signal, its write column redundancy multiplexer directs the write data bit to the ith column's write driver. The read column redundancy multiplexer is analogous in that it either selects for a retrieved bit from the current column or from the preceding column depending upon whether the current column's match_next signal is true or false.

In a conventional memory with column redundancy, it was typical that neither the write column redundancy multiplexer nor the read column redundancy multiplexer was covered by a DFT scan chain. An example conventional column <NUM> is shown in <FIG>. For illustration clarity, just a single bitcell <NUM> is shown coupling to a bit line bl and a complement bit line blb but it will be appreciated that a column such as column <NUM> includes a plurality of bit cells arranged according to rows. During a write operation to column <NUM>, an input data bit din from a core power domain powered by a core power supply is level shifted by a level-shifter (LS) <NUM> to a memory power supply domain din signal powered by a memory power supply. During a scan mode of operation, a shift-in signal is provided by scan chain flip-flop such as a master-slave flip-flop <NUM> for a scan chain. During a write operation, a write column redundancy multiplexer (write red mux) <NUM> routes the level-shifted din signal depending upon whether the match_next signal is asserted or de-asserted. If the match_next signal is false, write column redundancy multiplexer <NUM> passes the level-shifted din signal to a write driver <NUM>. But if the match_next signal is true, write column redundancy multiplexer <NUM> passes the level-shifted din signal to a preceding column as a din_next signal. Should a subsequent column already have its match_next signal asserted, column <NUM> would receive this subsequent column's din_next signal as a din_prev signal at write driver <NUM>. Based upon the write driver's input signal (either the level-shifted din signal in the case of no redundancy or the din_prev signal should the subsequent column have its match_next signal asserted), write driver <NUM> drives a write data signal (wd) and a complement write data signal (wd_n) accordingly.

During the write operation to column <NUM>, a write multiplexer signal wm is asserted to switch on an n-type-metal-oxide-semiconductor (NMOS) write multiplexer transistor M1 to couple the wd signal to the bit line bl. Similarly, the assertion of the write multiplexer signal wm switches on another NMOS write multiplexer transistor M2 to couple the wd_n signal to the complement bit line blb. Bitcell <NUM> may then be written to accordingly to complete the write operation.

During a read operation in which column <NUM> is not defective, an active-low read multiplexer signal rm is discharged to switch on a p-type-metal-oxide-semiconductor (PMOS) read multiplexer transistor P1 to couple the true bit line to a sense amplifier (SAMP) <NUM>. Similarly, the discharging of the read multiplexer signal rm switches on another PMOS read multiplexer transistor P2 to couple the complement bit line blb to SAMP <NUM>. SAMP <NUM> may then make a bit decision. A read column redundancy multiplexer (read red mux) <NUM> selects for the bit decision from SAMP <NUM> should the match_next signal for column <NUM> be false. If the match_next signal is true, read column redundancy multiplexer <NUM> selects for the bit decision (SAMP next) from the preceding column. During a read operation to a subsequent column that has its match_next signal asserted, the subsequent column selects for the bit decision from SAMP <NUM> (SAMP prev).

During the read operation, a scan signal for a DFT scan of column <NUM> is not asserted. The scan signal controls a scan multiplexer (scan mux) <NUM> that selects for the bit decision from read column redundancy multiplexer <NUM> during a read operation. A data output latch (Dout latch) <NUM> may then latch the output data bit to complete the read operation. During a scan mode of operation, scan multiplexer <NUM> responds to the assertion of the scan signal by selecting for a shift-in signal from master-slave flip-flop <NUM>. Such a conventional DFT scan thus bypasses the operation of the write column redundancy multiplexer <NUM> and the read column redundancy multiplexer <NUM>.

To provide an ability to include the write and read column redundancy multiplexers in a DFT scan, an improved column <NUM> is provided as shown in <FIG>. As discussed for column <NUM>, just a single bitcell <NUM> is shown in column <NUM> coupling to a bit line bl and a complement bit line blb but it will be appreciated that column <NUM> includes a plurality of bit cells arranged according to rows. Referring again to memory <NUM>, each of the columns ranging from the Nth column to the zeroth column may be implemented as shown for column <NUM>. As also discussed analogously for column <NUM>, an input data bit din from a core power domain powered by a core power supply is level shifted by a level shifter (LS) <NUM> in column <NUM> to a memory power supply domain din signal powered by a memory power supply during a write operation to column <NUM>. During a scan mode of operation, a shift-in signal is provided by a master latch in a master-slave flip-flop <NUM> included in a scan chain. A write column redundancy multiplexer (write red mux) <NUM> multiplexes the level-shifted din signal depending upon whether the match_next signal is true or false. If the match_next signal for column <NUM> is false, write column redundancy multiplexer <NUM> passes the level-shifted din signal through a first output terminal to an input terminal of write driver <NUM> during a write operation. But if the match_next signal is true, write column redundancy multiplexer <NUM> passes the level-shifted din signal through a second output terminal to a preceding column as a din_next signal. Should a subsequent column already have its match_next signal asserted, column <NUM> would receive this subsequent column's din_next signal as a din_prev signal at write driver <NUM>. Based upon the write driver's input signal (either the level-shifted din signal in the case of no redundancy or the din_prev signal should the subsequent column have its match_next signal asserted), write driver <NUM> drives a write data signal (wd) and a complement write data signal (wd_n) accordingly.

During the write operation to column <NUM>, an active-high write multiplexer signal wm is asserted to switch on write multiplexer transistor M1 to couple the wd signal to the bit line bl and to switch on write multiplexer transistor M2 to couple the wd_n signal to the complement bit line blb. Bitcell <NUM> may then be written to accordingly to complete the write operation.

A read operation to column <NUM> also occurs analogously as discussed for column <NUM>. During a read operation in which column <NUM> is not defective, an active-low read multiplexer signal rm is discharged to switch on read multiplexer transistors P1 and P2 to couple the true bit line and complement bit line to a scan multiplexer <NUM>. A source of read multiplexer transistor P1 may be deemed to form a read terminal. Similarly, a source of read multiplexer transistor P2 may be deemed to form a complement read terminal. Scan multiplexer <NUM> includes a first pair of input terminals coupled to the read terminal and the complement read terminal. During a read operation, a scan signal is de-asserted to control scan multiplexer <NUM> to select for its first pair of input terminals and thus select for the bit line signals as routed through the read multiplexer transistors P1 and P2. SAMP <NUM> may then make a bit decision. A read column redundancy multiplexer (read red mux) <NUM> includes a first input terminal coupled to an output terminal of SAMP <NUM>. Read column redundancy multiplexer <NUM> selects for this first input terminal to thus select for the bit decision from SAMP <NUM> should the match_next signal for column <NUM> be false. SAMP <NUM> also includes a second input terminal coupled to a sense amplifier in a preceding column. If the match_next signal is true, read column redundancy multiplexer <NUM> selects for this second input terminal to thus select for the bit decision (SAMP next) from the preceding column. A data output latch (Dout latch) <NUM> includes an input terminal coupled to an output terminal of read column redundancy multiplexer <NUM> so that data output latch <NUM> may then latch the output data bit to complete the read operation. During a read operation to a subsequent column that has its match_next signal asserted, the subsequent column selects for the bit decision from SAMP <NUM> (SAMP prev).

During a scan mode of operation, master-slave flip-flop <NUM> provides the shifted-in signal that is routed through the write column redundancy multiplexer <NUM> and write driver <NUM>. Write driver <NUM> has a first output terminal for the write data signal wd (or the shifted-in signal during the scan mode) and a second output terminal for the complement write data signal wd_n (or the complement shifted-in signal during the scan mode). Scan multiplexer <NUM> includes a second pair of input terminals coupled to the first and second output terminals of write driver <NUM>. Should the scan signal be asserted, scan multiplexer <NUM> selects for its second pair of input terminals to select for the pair of output signals from write driver <NUM>. The sense amplifier SAMP <NUM> then makes a bit decision based upon the shifted-in signal. If the match_next signal is false, the shifted-in signal bit decision from SAMP <NUM> is routed through the read column redundancy multiplexer <NUM> to be latched in the Dout latch <NUM>. Conversely, if the match_next signal is true, the read column redundancy multiplexer <NUM> selects for the shifted-in signal bit decision (SAMP next) from the sense amplifier in the preceding column. Advantageously, the operation of the write column redundancy multiplexer <NUM> may also be tested in the scan mode as the level-shifted shifted-in signal will be routed through the write column redundancy multiplexer <NUM> to write driver <NUM> (and ultimately to Dout latch <NUM>) if the match_next signal is false. If the match_next signal is true, the shifted-in signal routes through write column redundancy multiplexer <NUM> to the write driver in the preceding column.

An alternative column implementation that also enables the scanning of the read and write column redundancy multiplexers is shown in <FIG> for a column <NUM>. Referring again to memory <NUM>, each of the columns ranging from the Nth column to the zeroth column may be implemented as shown for column <NUM>. Read and write operations occur analogously as discussed for column <NUM>. For example, an input data bit din from a core power domain powered by a core power supply is level shifted by a level shifter (LS) <NUM> to a memory power supply domain din signal powered by a memory power supply during a write operation to column <NUM>. During a scan mode of operation, a shifted-in signal may be provided by a master-slave flip-flop <NUM> for a scan chain. During a write operation, write column redundancy multiplexer (write red mux) <NUM> multiplexes the level-shifted din signal depending upon whether the match_next signal is true or false. If the match_next signal for column <NUM> is false, write column redundancy multiplexer <NUM> passes the level-shifted din signal to a write driver <NUM>. But if the match_next signal is asserted for column <NUM>, write column redundancy multiplexer <NUM> passes the level-shifted din signal to a preceding column as a din_next signal. Should a subsequent column already have its match_next signal asserted, column <NUM> may receive this subsequent column's din_next signal as a din_prev signal at write driver <NUM>. Based upon the write driver's input signal during a write operation (either the level-shifted din signal in the case of no redundancy or the din_prev signal should the preceding column have its match_next signal asserted), write driver <NUM> drives a write data signal (wd) and a complement write data signal (wd_n) accordingly.

A read operation to column <NUM> also occurs analogously as discussed for column <NUM>. During a read operation in which the match_next signal for column <NUM> is false, an active-low read multiplexer signal rm is discharged to switch on read multiplexer transistors P1 and P2 to couple the true bit line and complement bit line to sense amplifier <NUM>. SAMP <NUM> may then make a bit decision. Read column redundancy multiplexer (read red mux) <NUM> selects for the bit decision from SAMP <NUM> should the match_next signal for column <NUM> be false. If the match_next signal is true for column <NUM>, read column redundancy multiplexer <NUM> selects for the bit decision (SAMP next) from the preceding column. A data output latch (Dout latch) <NUM> may then latch the output data bit to complete the read operation. During a read operation to a subsequent column that has its match_next signal asserted, the subsequent column selects for the bit decision from SAMP <NUM> (SAMP prev).

In a scan mode of operation, a memory controller (not illustrates) switches on the read multiplexer transistors M1 and M2 simultaneously with the write multiplexer transistors P1 and P2. Master-slave flip-flop <NUM> provides the shift-in signal. If the match_next signal for column <NUM> is false, the shift-in signal passes through the write column redundancy multiplexer <NUM> to be driven in true and complement form as the wd and wd_n signals, respectively. The wd signal during the scan mode of operation couples through write multiplexer transistor M1 to bit line bl and also through read multiplexer transistor P1 to drive the sense amplifier <NUM>. Similarly, the wd_n signal couples through write multiplexer transistor M2 and read multiplexer transistor P2 to drive the sense amplifier <NUM> during the scan mode of operation. If the match_next signal is true during the scan mode of operation, the write column redundancy multiplexer <NUM> passes the shift-in signal to the write driver in the preceding column. The write multiplexer and read multiplexer transistors are both on in this preceding column as discussed for column <NUM>.

In the scan mode of operation for column <NUM>, sense amplifier <NUM> recovers the shift-in signal from the wd and wd_n signals. If the match_next signal for column <NUM> is false, read column redundancy multiplexer <NUM> selects for the recovered shift-in signal so that it may be latched in Dout latch <NUM>. A direct electrical connection <NUM> extends from an output terminal of read column redundancy multiplexer <NUM> to an input terminal of Dout latch <NUM>. As used herein, the term "direct electrical connection" refers to an electrical path or lead that does not contain any switching elements such as transistors within a multiplexer. If the match_next signal is false, the shift-in signal will thus pass through the write column redundancy multiplexer <NUM>, the read column redundancy multiplexer <NUM>, and direct electrical path <NUM> to be latched in Dout latch <NUM>. A scan mode of operation may thus test the operation of both write column redundancy multiplexer <NUM> and read column redundancy multiplexer <NUM> during the scan mode of operation with the match_next signal being false. If the match_next signal is true during the scan mode of operation, the operation of the write column redundancy multiplexer <NUM> in column <NUM> and a read column redundancy multiplexer <NUM> in the preceding column are tested analogously. A scan mode for the redundancy logic circuits and a redundancy decoder will now be discussed.

It is customary for a redundancy decoder to be responsive to a redundancy enable signal. During a scan mode of operation with such a conventional redundancy decoder, the assertion of the redundancy enable signal may occur well before the assertion of the triggering edge of the scan clock signal for the DFT scan chain. Referring again to memory <NUM>, the decoded redundancy address signals are thus presented to the redundancy logic circuits relatively early before the scan clock signal edge is asserted. The match_next signals from the various redundancy logic circuits then have ample time to settle. This is problematic as there may be a resistive path fault that will go undetected. For example, a resistive path fault may exist in one of NAND gate <NUM>, inverters <NUM> and <NUM>, or NOR gate <NUM> in redundancy logic circuit <NUM>. Such a resistive path fault causes redundancy logic circuit <NUM> to take too much time to assert its match_next signal, which may lead to read or write errors. But such resistive path faults may not be detectable if the redundancy decoder is merely triggered by the redundancy enable signal.

A redundancy decoder <NUM> shown in <FIG> advantageously allows the redundancy logic circuits such as discussed for <FIG> and <FIG> to be tested by a scan mode of operation, including the detection of resistive path faults. When enabled during a scan mode of operation, redundancy decoder <NUM> decodes a fuse word fuse<<NUM>:<NUM>> to produce the three decoded redundancy address signals fa<<NUM>:<NUM>>, fb<<NUM>:<NUM>>, and fc<<NUM>:<NUM>>. The bit width of the fuse word as well as the number and bit width of the decoded redundancy address signals may be varied in alternative implementations. A gating logic gate such as a NAND gate <NUM> controls the enabling of the redundancy decoder <NUM>. NAND gate <NUM> gates an active-low redundancy enable signal fc_en with an active-low gating signal (shift_n) signal that is asserted a known time prior to the assertion of a triggering edge of the scan clock signal for the DFT scan chain. The following discussion will assume that the triggering edge of the scan clock signal is a rising edge without loss of generality. When the shift_n signal discharged shortly before the assertion of the scan clock signal and with the redundancy enable signal fc_en already discharged, an output signal from NAND gate <NUM> is asserted. The asserted NAND gate output may then be level-shifted from the core (CX) power domain to the memory (MX) power domain by a level-shifter <NUM> to form a gated enable signal received at an enable input terminal of a fuse decoder <NUM>. Fuse decoder <NUM> is configured to decode the fuse word fuse<<NUM>:<NUM>> into the decoded redundancy address signals fa<<NUM>:<NUM>>, fb<<NUM>:<NUM>>, and fc<<NUM>:<NUM>> when enabled by an assertion of the gated enable signal.

Referring again to memory <NUM>, a scan chain flip-flop <NUM> registers the match_next signal from the zeroth redundancy logic circuit when clocked by the scan clock signal. Flip-flop <NUM> shifts out the sampled match_next signal as a redundancy scan out signal (red_scan_out). A timer (not illustrated) may then determine the delay between the discharge of the gating signal (shift_n) and the assertion of the redundancy scan out signal. Should this delay be greater than a threshold delay, a resistive path fault in the redundancy logic circuit is detected. For example; the scan may begin by testing the zeroth redundancy logic circuit. If the zeroth redundancy logic circuit asserts its match_next signal so that the threshold delay is not reached, the scan may continue to test the first redundancy logic circuit, and so on until the Nth redundancy logic circuit is finally tested.

A timing diagram for the redundancy decoder signals fc_en, shift_n, the fuse word, the scan clock signal, and the redundancy scan out signal is shown in <FIG>. Prior to a time t0, the fuse word fuse<<NUM>:<NUM>> is received at the redundancy decoder and the redundancy enable signal fc_en is asserted by being discharged in an active-low implementation. The fuse word is coded so that the addressed redundancy logic circuit should assert its match_next signal. To test whether this assertion of the match_next signal is subject to a resistive path delay, the active-low gating signal shift_n is not asserted by being discharged until a time t0. The scan clock rising edge is not asserted until a time t1 approximately <NUM> ns later. In general, the delay between the shift_n and scan clock edges may be greater or smaller than <NUM> ns depending upon the distinction between a normal processing delay and a resistive path delay. Should the delay between the shift_n falling edge and the rising edge of the redundancy scan out signal (Red_scan_out) be excessive, a resistive path delay is deemed to be detected in the targeted redundancy logic circuit. The redundancy enable signal is then de-asserted by being charged to a power supply voltage at a time t2. This time may also be controlled to be a known time (e.g., <NUM> ns) before the next rising edge of the scan clock signal at a time t3 to determine whether the redundancy scan out signal is taking too long to be discharged.

A method of scanning the redundancy multiplexers in a column according to the invention will now be discussed with reference to the flowchart of <FIG>. The acts in this flowchart are responsive to a triggering edge of a scan clock signal during a scan mode of operation in which the column redundancy signal for the column is false. The method includes an act <NUM> of routing a shift-in signal through a write column redundancy multiplexer to a write driver. The routing of the shift-in signal through write column redundancy multiplexer <NUM> in column <NUM> is an example of act <NUM>. The method also includes an act <NUM> of processing the shift-in signal through the write driver to form a pair of write driver output signals. The processing of the shift-in signal in write driver <NUM> in column <NUM> is an example of act <NUM>. The method further includes an act <NUM> of routing the pair of write driver output signals through a scan multiplexer to a sense amplifier. The routing through scan multiplexer <NUM> in column <NUM> is an example of act <NUM>. In addition, the method includes an act <NUM> of sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal. The sensing in sense amplifier <NUM> in column <NUM> in an example of act <NUM>. Finally, the method includes an act <NUM> of routing the sensed version of the shift-in signal through a read column redundancy multiplexer to a data output latch. The routing through read column redundancy multiplexer <NUM> in column <NUM> is an example of act <NUM>.

Claim 1:
A memory (<NUM>), comprising:
a plurality of columns (<NUM>), each column including:
a bit line;
a complement bit line;
a first read multiplexer transistor coupled to the bit line and having a read terminal;
a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal;
a write driver (<NUM>) having a write data output terminal and a complement write data output terminal;
a scan multiplexer (<NUM>) having a first pair of input terminals coupled to the write data output terminal and the complement write data output terminal and having a second pair of input terminals coupled to the read terminal and the complement read terminal; and
a sense amplifier (<NUM>) coupled to an output from the scan multiplexer, the memory further configured in response to a column redundancy signal for a column of the plurality of the columns being false during a scan mode of operation to:
responsive (<NUM>) to a triggering edge of a scan clock signal, route a shift-in signal through a write column redundancy multiplexer (<NUM>) to the write driver (<NUM>);
process (<NUM>) the shift-in signal through the write driver to form a pair of write driver output signals;
route (<NUM>) the pair of write driver output signals through the scan multiplexer (<NUM>) to the sense amplifier (<NUM>);
sense (<NUM>) the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and
route (<NUM>) the sensed version of the shift-in signal through a read column redundancy multiplexer (<NUM>) to a data output latch (<NUM>).