Patent Description:
Analog-to-Digital Converters (ADC) are widely used in many applications. Some applications require both high precision and high sampling speed. High precision can be achieved using multi-bit ADC's, such as <NUM>-bits to <NUM>-bits of precision.

<FIG> shows a capacitor array in an ADC. Converter <NUM> has a weighted array of capacitors <NUM>, <NUM>, <NUM> that share charge to the inputs to comparator <NUM> that generates a digital bit VCOMP that is <NUM> when the + input to comparator has a higher voltage than the - input.

A controller or sequencer (not shown) controls switches <NUM>, <NUM> that allow various voltages to be switched to the outer or bottom plates of capacitors <NUM>, <NUM>, <NUM>. Each switch can be individually controlled. A Successive-Approximation (SA) routine may be used to switch successively smaller capacitors on or off to test different digital values to see which digital value is closest to the analog input voltage.

For example, converter <NUM> may be initialized by setting all switches <NUM>, <NUM> to connect a common-mode voltage VCM to the outer plates of all capacitors <NUM>, <NUM>, <NUM>. The + and - input lines to comparator <NUM> may also be driven to VCM by equalizing switches (not shown). VCM can be generated as a midpoint between the reference voltages, such as (Vrefp+Vrefn)/<NUM>, using a <NUM>:<NUM> resistor divider.

Then in a sampling phase the true analog voltage Vinp may be applied by switches <NUM>, <NUM> to the outer plates of all capacitors <NUM>, <NUM> that have inner (top) plates connected to the + input of comparator <NUM>, while the complement analog voltage Vinn is applied by switches <NUM>, <NUM> to the outer plates of all capacitors <NUM>, <NUM> that have inner plates connected to the - input of comparator <NUM>. VCM is applied to both inputs of comparator <NUM>. The differential analog input voltage is thus sampled into the plates of capacitors <NUM>, <NUM>, <NUM>.

Next, during an evaluation phase switches <NUM>, <NUM> drive VCM to all output plates, but a Successive-Approximation routine tests successively smaller capacitors that are driven with the reference voltage rather than with VCM.

For example, when the Most-Significant Bit (MSB) capacitors <NUM>, <NUM> are being tested, upper switch <NUM> connects reference Vrefn to the outer plate of MSB capacitor <NUM>, while lower switch <NUM> connects reference Vrefp to the outer plate of MSB capacitor <NUM>. This switching causes charge sharing and charges to be shifted between MSB capacitors <NUM>, <NUM> and the + and - input lines to comparator <NUM>, which may flip the digital output VCOMP. The SA routine can watch VCOMP for the flip and set to clear bits in a Successive-Approximation-Register (SAR) as a result. By testing successively smaller capacitors <NUM>, the SA routine can fill the SAR with a good approximation of the analog input voltage.

<FIG> shows a prior art multi-stage ADC with a residue amplifier. Rather than have a single converter <NUM> with many bits of resolution, multiple converters <NUM>, <NUM> may be used in multiple stages. For example, rather than have a <NUM>-bit single converter <NUM>, first converter <NUM> may generate <NUM> bits (Most-Significant Bits, MSB), while second converter <NUM> generates another <NUM> bits (Least-Significant Bits, LSB).

Input voltage VIN is applied to first converter <NUM>, which can have an array of capacitors and switches such as shown for converter <NUM> (<FIG>). First converter <NUM> uses a SA routine to toggle switches until a final code is found and stored in a first SAR, SAR1 <NUM>.

Then the residual voltage, on the + input to comparator <NUM> in <FIG>, is applied to the inverting (-) input of residue amplifier <NUM> and amplified to drive the analog voltage input to second converter <NUM>. Like converter <NUM>, second converter <NUM> has an array of capacitors and switches and uses a SA routine to toggle switches until a final code is found and stored in a second SAR, SAR2 <NUM>.

Feedback capacitor <NUM> feeds back the output of residue amplifier <NUM> to its inverting (-) input, while the non-inverting (+) input of residue amplifier <NUM> is connected to ground. The closed-loop gain is C1/C2 > <NUM>, where C1 is the capacitance of first converter <NUM> and C2 is the capacitance of feedback capacitor <NUM>. C1 does not vary with the code in SAR1 <NUM>.

In actual circuits there is a small non-zero offset error in residue amplifier <NUM> that can be modeled by offset voltage <NUM> connected between the non-inverting (+) input of residue amplifier <NUM> and ground. This VOS error can be caused by mismatches in residue amplifier <NUM>. Since VOS occurs before the input to residue amplifier <NUM>, this VOS error is amplified by the closed-loop gain of residue amplifier <NUM> and applied to the input to second converter <NUM>. When this error is large, second converter <NUM> may not be able to correct this error.

For example, is the open-loop gain of residue amplifier <NUM> is »<NUM>, such as <NUM> dB, the output of residue amplifier <NUM>, Vo, can be approximated as:
<MAT>
where Vi is the quantization noise of first converter <NUM>, and, VOSi,RA is input-equivalent offset voltage of residue amplifier <NUM>, or VOS, offset voltage <NUM>.

Notice that if C<NUM>/C<NUM> is <NUM> and VOSi,RA is [-10mV,+10mV], then the output equivalent offset voltage will be [-50mV,+50mV]. This value is too far out of the redundancy range in this example, so second converter <NUM> is required to cancel such an offset voltage.

Correction by second converter <NUM> to cancel the offset amplified by residue amplifier <NUM> is normally performed in the foreground and can't track environmental changes. Also, in real applications, the correction range may need to be [-80mV,+80mV] in second converter <NUM>, which would require a very precise DAC, such as 250uV LSB, for a 10b DAC, which is hard to achieve. Drift on the output of residue amplifier <NUM> can be more than [-10mV, +10mV], which can be out of the redundancy range, causing long-term reliability issues.

Over time, offset VOS can change, such as when the circuit heat up, or as the circuit ages. Offset VOS can change with Process, Voltage, and Temperature (PVT). It is desirable to track such changes in offset voltage VOS and correct these offset errors.

What is desired is an offset detection and correction circuit for a residue amplifier in a multi-stage ADC. A discrete-time offset-compensation circuit embedded in a residue amplifier is desired for use in a high speed and high resolution pipeline ADC. A residue amplifier offset corrector that tracks changes to offset over time and conditions is desirable. A real-time offset corrector is desired that operates during ADC conversions. The article titled "<NPL>) describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -<NUM> dB THD in the Nyquist band, with a <NUM>-V supply. The ADC is realized in standard single-poly <NUM>-metal <NUM>-µm CMOS, measures <NUM><sup><NUM> </sup>, and dissipates <NUM> mW. The patent document <CIT>) discloses an amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage non-inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit. The article titled "<NPL>) presents a <NUM> bit <NUM>/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in <NUM> CMOS.

A multi-stage Analog-to-Digital Converter (ADC) with an embedded offset corrector is provided and includes: a first ADC stage that converts an analog input into a first M digital bits that represent an analog value of the analog input, wherein M is a whole number of at least <NUM>, the first ADC stage outputting a residue after quantization of the analog input to the first M digital bits; a residue amplifier having a first input that receives the residue from the first ADC stage and generates a first output; a feedback capacitor connected between the first input and the first output of the residue amplifier; a second ADC stage that converts the first output from the residue amplifier into a second N digital bits that represent an analog value of the first output from the residue amplifier, wherein N is a whole number of at least <NUM>; an offset capacitor for storing an offset; an offset corrector that filters the first output of the residue amplifier to generate a filtered offset that is stored on the offset capacitor; and an offset switch, connected between the offset capacitor and the first input of the residue amplifier, the offset switch applying the offset stored on the offset capacitor to the first input. The offset corrector comprises: a low-pass filter that receives the first output from the residue amplifier, and generates a filtered offset; and an offset amplifier that receives the filtered offset and generates a buffered offset.

Further, preferably, in the multi-stage ADC with an embedded offset corrector, wherein the offset capacitor has an input terminal and an output terminal; the offset corrector further includes an offset-loading switch that connects the buffered offset to the input terminal of the offset capacitor; wherein the offset switch is connected to the output terminal of the offset capacitor; wherein the offset corrector further includes: an input grounding switch that grounds the input terminal of the offset capacitor; an output grounding switch that grounds the output terminal of the offset capacitor.

Further, preferably, the multi-stage ADC with an embedded offset corrector further includes: a first stage switch connected between a residue output of the first ADC stage and the first input, for connecting the residue to the first input of the residue amplifier; a second stage switch connected between the first output of the residue amplifier and the second ADC stage, for connecting an amplified residue output from the residue amplifier to an analog input of the second ADC stage.

Further, preferably, the multi-stage ADC with an embedded offset corrector further includes: a first phase clock that is active during an autozeroing phase of the residue amplifier; a second phase clock that is inactive during the autozeroing phase of the residue amplifier and is active during an amplifying phase of the residue amplifier; wherein the output grounding switch and the offset-loading switch each further include a first-phase clock input that receives the first phase clock and causes switch closure when the first phase clock is active and switch opening when the first phase clock is inactive; wherein the first stage switch, the second stage switch, the input grounding switch, and the offset switch each further include a second-phase clock input that receives the second phase clock and causes switch closure when the second phase clock is active and switch opening when the second phase clock is inactive.

Further, preferably, in the multi-stage ADC with an embedded offset corrector, during the autozeroing phase: the first input and the first output of the residue amplifier are grounded; the output grounding switch is closed to ground the output terminal of the offset capacitor; and the offset-loading switch is closed to connect the buffered offset to the input terminal of the offset capacitor; and the first stage switch, the second stage switch, the input grounding switch, and the offset switch are open and block current flow; wherein during the amplifying phase: the first stage switch, the second stage switch, the input grounding switch, and the offset switch are closed and allow current flow; the output grounding switch is open; and the offset-loading switch is open to disconnect the buffered offset from the input terminal of the offset capacitor.

Further, preferably, in the multi-stage ADC with an embedded offset corrector, the residue amplifier is a differential amplifier and further includes a second input and a second output, wherein the first input and the second output are inverting and the second input and the first output are non-inverting; wherein the first ADC stage outputs the residue and a complement residue; wherein the second ADC stage converts the first output and the second output from the residue amplifier into the second N digital bits; further including: a second feedback capacitor connected between the second input and the second output of the residue amplifier; a complement offset capacitor for storing a complement offset; wherein the offset corrector filters the first output and the second output of the residue amplifier to further generate a complement filtered offset that is stored on the complement offset capacitor; wherein the offset amplifier further receives the complement filtered offset and generates a complement buffered offset; a complement offset switch, connected between the complement offset capacitor and the second input of the residue amplifier, the complement offset switch applying the complement offset stored on the complement offset capacitor to the second input.

Further, preferably, in the multi-stage ADC with an embedded offset corrector, the complement offset capacitor has a complement input terminal and a complement output terminal; a complement offset-loading switch that connects the complement buffered offset to the complement input terminal of the complement offset capacitor; wherein the complement offset switch is connected to the complement output terminal of the complement offset capacitor.

Further, preferably, in the multi-stage ADC with an embedded offset corrector, the complement offset corrector further includes: a complement input grounding switch that grounds the complement input terminal of the complement offset capacitor; a complement output grounding switch that grounds the complement output terminal of the complement offset capacitor.

Further, preferably, the multi-stage ADC with an embedded offset corrector further includes: a complement first stage switch connected between the complement residue output of the first ADC stage and the second input, for connecting the complement residue to the second input of the residue amplifier; a complement second stage switch connected between the second output of the residue amplifier and the second ADC stage, for connecting an amplified complement residue output from the residue amplifier to a complement analog input of the second ADC stage; an equalizing switch, connected between the first output and the second output of the residue amplifier, for connecting the first output to the second output during the autozeroing phase.

An offset-correcting multi-stage Analog-to-Digital Converter (ADC) is provided and includes: a first Analog-to-Digital Converter (ADC) stage having an analog input and switched capacitors for quantizing the analog input to generate M Most-Significant Bits (MSBs) that represent the analog input, and generating a residue of quantization on a first ADC P output and a first ADC N output; wherein M is a whole number of at least <NUM>; a Residue Amplifier (RA) having an inverting input and a non-inverting input, and generating a RA P output and a RA N output; a first feedback capacitor connected between the inverting input and the RA P output; a second feedback capacitor connected between the non-inverting input and the RA N output; a first stage P switch that connects the first ADC P output to the inverting input during an amplifying phase; a first stage N switch that connects the first ADC N output to the non-inverting input during the amplifying phase; a second ADC stage, having a second P input and a second N input, for converting an analog difference between the second P input and the second N input into a second N digital bits, wherein N is a whole number of at least <NUM>; a second stage P switch that connects the RA P output to the second P input during the amplifying phase; a second stage N switch that connects the RA N output to the second N input during the amplifying phase; and an offset corrector that receives the RA P output and the RA N output, and filters the RA P output and the RA N output to generate a P filtered error and an N filtered error; wherein the P filtered error is stored and applied to the inverting input of the residue amplifier, and the N filtered error is stored and applied to the non-inverting input of the residue amplifier to correct offset error. The offset corrector comprises: a P offset capacitor having a P first terminal and a P second terminal; an N offset capacitor having a N first terminal and an N second terminal; a low-pass filter that receives the RA P output and the RA N output, and filters the RA P output and the RA N output to generate a P filtered node and an N filtered node; and an amplifier that receives the P filtered node and the N filtered node and drives a P error to the P first terminal for storage on the P offset capacitor, and drives an N error to the N first terminal for storage on the N offset capacitor.

Further, preferably, in the offset-correcting multi-stage ADC, the offset corrector further includes: a P offset switch that connects the P second terminal to the inverting input of the residue amplifier during the amplifying phase; a P offset-storing switch that connects the P filtered error to the P first terminal during an autozeroing phase; an N offset switch that connects the N second terminal to the non-inverting input of the residue amplifier during the amplifying phase; an N offset-storing switch that connects the N filtered error to the N first terminal during the autozeroing phase.

Further, preferably, the offset-correcting multi-stage ADC further includes: a first P grounding switch that grounds the P first terminal during the amplifying phase; a second P grounding switch that grounds the P second terminal during the autozeroing phase; a first N grounding switch that grounds the N first terminal during the amplifying phase; and a second N grounding switch that grounds the N second terminal during the autozeroing phase.

Further, preferably, in the offset-correcting multi-stage ADC, the low-pass filter has a time constant of at least <NUM> cycles of the autozeroing phase and the amplifying phase, wherein the low-pass filter has a long time constant.

Further, preferably, in the offset-correcting multi-stage ADC, the low-pass filter is a second-order filter.

Further, preferably, the offset-correcting multi-stage ADC further includes: an equalizing switch that connects the RA P output to the RA N output during the autozeroing phase.

Further, preferably, in the offset-correcting multi-stage ADC, the first ADC stage further includes a first Successive-Approximation-Register (SAR) and a first capacitor array of weighted capacitors and switches that are controlled by bits in the first SAR, wherein a Successive-Approximation routine is executed during the autozeroing phase of the residue amplifier to adjust bits in the first SAR to quantize the analog input; wherein the second ADC stage further includes a second SAR and a second capacitor array of weighted capacitors and switches that are controlled by bits in the second SAR, wherein a Successive-Approximation routine is executed during the autozeroing phase of the residue amplifier to adjust bits in the second SAR during quantization.

The present invention relates to an improvement in ADC offset correction. The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

<FIG> shows a single-ended multi-stage pipelined ADC with an offset correction circuit embedded in the residue amplifier between stages. A first converter receives input analog voltage VIN and has first capacitor array <NUM> with switches controlled by SAR1 <NUM>. A comparator (not shown) compares voltage VX connected to the switched capacitors in first capacitor array <NUM> to a reference to allow a SA routine to decide when to set or clear bits in SAR1 <NUM>. The bits in SAR1 <NUM> are MSB's of the digital output, such as <NUM> MSBs.

Switch <NUM> closes in phase P2 to connect VX to VI and the inverting (-) input of residue amplifier <NUM>. Switch <NUM> opens and the non-inverting (+) input of residue amplifier <NUM> is grounded. Feedback capacitor <NUM> connects the output of residue amplifier <NUM>, VO, with its input, VI.

Switch <NUM> closes during phase P2 to connect output VO of residue amplifier <NUM> to the analog input of the second converter, which has second capacitor array <NUM> with switches controlled by SAR2 <NUM>. A comparator (not shown) compares voltage VY connected to the switched capacitors in second capacitor array <NUM> to a reference to allow a SA routine to decide when to set or clear bits in SAR2 <NUM>. The bits in SAR2 <NUM> are LSB's of the digital output, such as <NUM> LSBs.

Switch <NUM> drives VY to ground during phase P2 while switch <NUM> drives VO to ground during phase P1.

Offset detection and correction is provided by offset corrector <NUM>. Output VO of residue amplifier <NUM> is filtered by low-pass filter <NUM> and then amplified by amplifier <NUM> to generate a filtered detected offset that is driven onto offset capacitor <NUM> during phase P1 when switch <NUM> closes, and switch <NUM> closes to ground the back terminal, node VC, of offset capacitor <NUM>. Amplifier <NUM> can have a closed-loop gain of 4x to 10x in some embodiments.

During phase P2, the offset stored on offset capacitor <NUM> at node VC is driven through switch <NUM> to VI and the inverting input of residue amplifier <NUM>. The filtered detected offset stored on offset capacitor <NUM> is thus applied to the (-) input of residue amplifier <NUM> and effectively subtracted from the RA input voltage. Node VX from first capacitor array <NUM> is connected through switch <NUM> while node VC is connected through switch <NUM> during phase P2, so VC is combined with VX.

Switch <NUM> grounds the first terminal of offset capacitor <NUM> during phase P2 to drive the filtered stored offset from offset capacitor <NUM> through switch <NUM> to be combined with VX.

<FIG> shows modeling of the single-ended multi-stage pipelined ADC with an offset correction circuit embedded in the residue amplifier between stages. The actual offset of residue amplifier <NUM> is modeled as offset voltage VOS generated by offset voltage generator <NUM>. Offset voltage generator <NUM> is not a physical component but is a modeled component for circuit simulation to account for physical offsets and mismatches from various physical sources, such as from mismatches in residue amplifier <NUM>.

Resistor <NUM> connects VO to ground when switch <NUM> is closed. Resistor <NUM> is not a physical component but represents the finite ON resistance of switch <NUM>.

<FIG> highlights the autozeroing phase model of the single-ended multi-stage pipelined ADC with the offset correction circuit embedded in the residue amplifier between stages. Phase P1 is RA autozeroing, where residue amplifier <NUM> is equalized and reset. Phase P1 is also the ADC conversion phase, since analog-to-digital conversions are performed by first capacitor array <NUM>, SAR1 <NUM>, second capacitor array <NUM>, and SAR2 <NUM>.

In phase P1, all P2 switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are open. All P1 switches <NUM>, <NUM>, <NUM>, <NUM> are closed. Switch <NUM> closes to connect the inverting (-) and non-inverting (+) inputs of residue amplifier <NUM> together to equalize them.

Switch <NUM> closes to allow amplifier <NUM> to drive the filtered detected offset onto the first terminal of offset capacitor <NUM>, while switch <NUM> closes to ground the second terminal of offset capacitor <NUM>, node VC. Thus the offset is detected and stored onto offset capacitor <NUM> during autozeroing phase P1. Low-pass filter <NUM> averages the output voltage VO of residue amplifier <NUM> over many cycles of P1, P2, such as thousands of cycles.

Switch <NUM> closes to drive the output VO of residue amplifier <NUM> to ground, causing residue amplifier <NUM> to act as a Gm transconductance due to the small resistance of resistor <NUM>. The output voltage VO of residue amplifier <NUM> during autozeroing phase P1 can be given as:
<MAT>
wherein Gm is the gain of residue amplifier <NUM>, Ron is the resistance of resistor <NUM>, and VOSi,RA is the input-equivalent offset voltage of residue amplifier <NUM>, or VOS, from offset voltage generator <NUM>.

Low-pass filter <NUM> has a very low frequency to detect the DC voltage of VO. At a high speed and low offset, residue amplifier <NUM> has an open-loop DC gain of Aos. Therefore the offset voltage V3 sampled on offset capacitor <NUM> with capacitance C3 is given by:
<MAT>.

In advanced circuit design, a relatively constant GmRONAOS with variations of +/- <NUM>% from nominal value may be obtained. For instance, constant Gm biasing (i.e., IBIAS α <NUM>/R) can be used to obtain constant Gm over process, supply and temperature such that both Gm and AOS = GmOS * R can be flat over PVT. Thin film resistors can be used in a CMOS process to have an accurate resistance R. Switch ON resistance RON can be designed with bootstrapping switches such that the variation of on the ON resistance can be made small over PVT. With such an approach, GmRONAOS can be designed with less variation over PVT to keep the offset correction drift low over variations.

<FIG> highlights the amplify phase model of the single-ended multi-stage pipelined ADC with the offset correction circuit embedded in the residue amplifier between stages. Phase P2 is RA amplifying, where residue amplifier <NUM> is amplifying its inputs. Phase P2 is also the ADC equalize phase, since first capacitor array <NUM> and second capacitor array <NUM> are equalized and prepared for analog-to-digital conversions in the next P1 phase.

In phase P2, all P2 switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are closed. All P1 switches <NUM>, <NUM>, <NUM>, <NUM> are open. The quantization error or residual voltage on VX in first capacitor array <NUM>, after SAR1 <NUM> has found the closest match, is passed through switch <NUM> to VI, the inverting (-) input of residue amplifier <NUM>. The offset stored on offset capacitor <NUM> is driven from node VC through switch <NUM> to be combined with VX at node VI, and effectively subtracted by residue amplifier <NUM>. Switch <NUM> closes to drive the first terminal of offset capacitor <NUM> to ground to pull charge through offset capacitor <NUM> from VC and VI. Switches <NUM>, <NUM> are open to permit this charge transfer or charge sharing on VI. Thus the offset voltage is applied to residue amplifier <NUM> for offset correction from offset corrector <NUM>.

The output of residue amplifier <NUM>, VO is connected to the analog input of second capacitor array <NUM> through switch <NUM>, while combining node VY in second capacitor array <NUM> is grounded through switch <NUM>.

During phase P2, with switch <NUM> open, residue amplifier <NUM> acts as an open-loop amplifier with a gain of Aos. The output voltage Vo of residue amplifier <NUM> is given by:
<MAT>
wherein C1 is the capacitance of first capacitor array <NUM> as configured by SAR1 <NUM>, C2 is the capacitance of feedback capacitor <NUM>, C3 is the capacitance of offset capacitor <NUM>, and C4 is the capacitance of second capacitor array <NUM> as configured by SAR2 <NUM>. VQ,SAR1 is the quantization noise of SAR1 <NUM>.

To perfectly compensate for the offset voltage, the loop gain is given by:
<MAT>.

Therefore, amplifier <NUM> in offset corrector <NUM> is given by:
<MAT>.

When amplifier <NUM> is implemented as a proper differential amplifier, it can have a gain of k*<NUM>/GmRON, where k is capacitor ratio given by <NUM>+(C<NUM>+C<NUM>)/C<NUM>. Note that the <NUM>/<NUM> multiplier accounts for a half circuit in a fully differential circuit.

<FIG> show embodiments of the low-pass filter. In <FIG>, a first-order low-pass filter <NUM> is shown. Resistor <NUM> is connected between the input and the output of low-pass filter <NUM>, while capacitor <NUM> is connected between the output of low-pass filter <NUM> and ground. A first-order filter network is simple but less effective than a second-order filter network.

In <FIG>, a second-order low-pass filter <NUM>' is shown. Resistor <NUM> is connected between the input of low-pass filter <NUM> and an internal node, while resistor <NUM> is connected between the internal node and the output of low-pass filter <NUM>'. Capacitor <NUM> is connected between the internal node and ground. Capacitor <NUM> is connected between the output of low-pass filter <NUM>' and ground.

Although more complex, second-order low-pass filter <NUM>' can be more effective than first-order low-pass filter <NUM>. Second-order low-pass filter <NUM>' can replace first-order low-pass filter <NUM> in the various embodiments of <FIG>, <FIG>.

Low-pass filter <NUM> is used to sense the DC offset and reject the AC signal of output VO, so the bandwidth of low-pass filter <NUM> is designed to have a very low frequency (e.g. <NUM>) for a high speed ADC. Low-pass filter <NUM> is also used to bandlimited noise power feedback to the analog input. Second order low-pass filter <NUM>' is preferred to have roll off of -40dB/decade.

<FIG> shows in more detail the amplifier in the offset corrector. Amplifier <NUM> has tail current source <NUM> that sinks current from the sources of n-channel transistors <NUM>, <NUM>. Current mirror p-channel transistors <NUM>, <NUM> have their gates connected together and to the drain of transistor <NUM> as mirrored current sources. The drains of transistors <NUM>, <NUM> connect together and to the gates of transistors <NUM>, <NUM>, while the drains of transistors <NUM>, <NUM> connect together and drive the output VOUT.

The input VINP to amplifier <NUM> is applied to the gate of transistor <NUM> while a fixed bias voltage VB is applied to the gate of transistor <NUM>. P-channel transistors <NUM>, <NUM> can be long channel devices while n-channel transistors <NUM>, <NUM> can be short channel, fast devices with good Gm.

<FIG> shows a loading-free embodiment of the single-ended multi-stage pipelined ADC with the offset correction circuit embedded in the residue amplifier between stages. In this variation, feedback switch <NUM> closes during phase P2 to connect the combining node VY in second capacitor array <NUM> with input VI to residue amplifier <NUM>. Thus during the RA amplifying phase, VY is fed back rather than grounded as in <FIG>. This is considered to be a loading-free configuration, since VY is not grounded or otherwise loaded.

A loading free architecture can use less current in residue amplifier <NUM> to have a higher settling speed during the amplification phase to transfer quantization noise of SAR1 to SAR2 via residue amplifier <NUM>. This can make the circuit implementation of residue amplifier <NUM> to be more power efficient.

<FIG> shows a fully differential multi-stage pipelined ADC with the offset correction circuit embedded in the residue amplifier between stages. A differential analog input AINP, AINN is applied to first capacitor array <NUM>' that has capacitors switched by SAR1 <NUM>. AINP is switched to capacitors connected to VXP while AINN is switched to capacitors connected to VXN. During phase P1, a SA routine tests different bits of SAR1 <NUM> that switch different capacitors in first capacitor array <NUM>' until a best match digital value is found for the MSB's.

Switch <NUM> closes during phase P2 to connect VXP to VIP and the inverting (-) input of differential residue amplifier <NUM>', and also switch <NUM> closes during phase P2 to connect VXN to VIN and the non-inverting (+) input of differential residue amplifier <NUM>'. Feedback capacitor <NUM> connects the - input VIP and the + output VOP of residue amplifier <NUM>', while feedback capacitor <NUM> connects the + input VIN and the - output VON of residue amplifier <NUM>'.

Also during amplifying phase P2, switches <NUM>, <NUM> close to connect VOP to AINP2, and to connect VON to AINN2. AINP2, AINN2 are the differential analog inputs to second capacitor array <NUM>'. AINP2 is switched to capacitors connected to VYP while AINN2 is switched to capacitors connected to VYN. During phase P1, a SA routine tests different bits of SAR2 <NUM> that switch different capacitors in second capacitor array <NUM>' until a best match digital value is found for the LSB's.

Differential offset corrector <NUM> receives the VOP, VON outputs of residue amplifier <NUM>', filters them, and stores the offset. The stored offset is then applied to inputs VIP, VIN to residue amplifier <NUM>' to subtract the offset. Offset-correcting residue amplifier <NUM> has offset corrector <NUM> embedded with residue amplifier <NUM>'.

<FIG> shows the fully-differential offset corrector in more detail. Differential output VOP, VON of differential residue amplifier <NUM>' is filtered by low-pass filter <NUM> in differential offset corrector <NUM> and then amplified by differential amplifier <NUM> to generate a filtered detected offset on its + and - outputs.

During phase P1, switches <NUM>, <NUM> close to connect the + output of differential amplifier <NUM> to the first terminal of offset capacitor <NUM>, while the second terminal, node VCP, is grounded. Also during phase P1, switches <NUM>, <NUM> close to connect the - output of differential amplifier <NUM> to the first terminal of offset capacitor <NUM>, while the second terminal, node VCN, is grounded. The offset filtered by low-pass filter <NUM> is driven onto offset capacitors <NUM>, <NUM> during phase P1.

During phase P2, the offset stored on offset capacitor <NUM> at node VCP is driven through switch <NUM> to VIP and the inverting input of residue amplifier <NUM>'. Also the offset stored on offset capacitor <NUM> at node VCN is driven through switch <NUM> to VIN and the non-inverting input of residue amplifier <NUM>'. Switch <NUM> grounds the first terminal of offset capacitor <NUM> during phase P2 to drive the filtered stored offset from offset capacitor <NUM> through switch <NUM> to be combined with VXP at node VIP. Similarly, switch <NUM> grounds the first terminal of offset capacitor <NUM> during phase P2 to drive the filtered stored offset from offset capacitor <NUM> through switch <NUM> to be combined with VXN at node VIN.

The offset generated by residue amplifier <NUM>' is only valid during the amplifying P2 phase. During the autozeroing P1 phase, residue amplifier <NUM> is being reset and low-pass filter <NUM> should not read the outputs of residue amplifier <NUM>' Switch <NUM> closes during phase P1 to equalize VOP, VON so that no erroneous offset is accumulated into low-pass filter <NUM>. A similar equalizing switch (not shown) can be placed between VIP, VIN to equalize the during phase P1, or switches to VCM can be added to VIP, VIN.

<FIG> show embodiments of the differential low-pass filter. In <FIG>, a first-order differential low-pass filter <NUM> is shown. Resistor <NUM> is connected between the IP input and the OP output of differential low-pass filter <NUM>, while capacitor <NUM> is connected between the OP and ON outputs of differential low-pass filter <NUM>. Resistor <NUM> is connected between the IN input and the ON output of differential low-pass filter <NUM>. A first-order filter network is simple but less effective than a second-order filter network.

In <FIG>, a second-order differential low-pass filter <NUM>' is shown. Resistor <NUM> is connected between the IP input of differential low-pass filter <NUM> and an internal P node, while resistor <NUM> is connected between the internal P node and the OP output of differential low-pass filter <NUM>'.

Resistor <NUM> is connected between the IN input of differential low-pass filter <NUM> and an internal N node, while resistor <NUM> is connected between the internal N node and the ON output of differential low-pass filter <NUM>'. Capacitor <NUM> is connected between the internal P node and the internal N node. Capacitor <NUM> is connected between the OP and ON outputs of differential low-pass filter <NUM>'.

Although more complex, second-order differential low-pass filter <NUM>' can be more effective than first-order differential low-pass filter <NUM>. Second-order differential low-pass filter <NUM>' can replace first-order differential low-pass filter <NUM> in various embodiments such as <FIG>.

<FIG> shows in more detail the differential amplifier in the offset corrector. Differential amplifier <NUM> has tail current source <NUM> that sinks current from the sources of n-channel transistors <NUM>, <NUM>. Current mirror p-channel transistors <NUM>, <NUM> have their gates connected together as mirrored current sources. Resistors <NUM>, <NUM> are in series between the drains of transistors <NUM>, <NUM>, with a midpoint node between resistors <NUM>, <NUM> that drives the gates of transistors <NUM>, <NUM>.

The drains of transistors <NUM>, <NUM> connect together to drive the VOUTN output, while the drains of transistors <NUM>, <NUM> connect together and drive the output VOUTP. VOUTP, VOUTN form a differential output, while VINP, VINN are the differential input.

The input VINP to differential amplifier <NUM> is applied to the gate of transistor <NUM> while the input VINN to differential amplifier <NUM> is applied to the gate of transistor <NUM>. P-channel transistors <NUM>, <NUM> can be long channel devices while n-channel transistors <NUM>, <NUM> can be short channel, fast devices with good Gm. Resistors <NUM>, <NUM> can be well-matched resistors, such as thin-film resistors.

Differential amplifier <NUM> can be designed as a sense amplifier k*<NUM>/GmRON where k is (C<NUM>+C<NUM> +C<NUM>)/C<NUM>.

The gain of differential amplifier <NUM> is related to:
<MAT>
where R1a,1b is the resistance of each of resistors <NUM>, <NUM>, and Gm1a,1b is the gain of each of transistors <NUM>, <NUM>.

The offset can be reduced by as much as <NUM>% using offset corrector <NUM> or differential offset corrector <NUM>. As temperature gradually changes, low-pass filter <NUM> will adjust the offset for the new environmental conditions, allowing the ADC to track temperature changes. Similarly, aging of the circuit is compensated for by offset corrector <NUM> as the offset changes over time.

Several other embodiments are contemplated by the inventor. For example level shifters may be added, such as between the core reference buffer and the multiple ADC channels. The voltage levels assigned to power and ground may be shifted, so that the common-mode or middle of the supply range is defined as ground with a positive and a negative supply terminals, where the negative supply terminal is the old ground.

Equalizing could be performed by a switch connecting the P and N lines together, or by multiple switches connecting the P and the N line to a fixed voltage, such as ground or VCM. Switch <NUM> between VOP, VON could also have additional switches to VCM, as one example.

Many variations of the ADC stages are possible. The analog inputs AINP, AINN to first capacitor array <NUM>' may connect to VINP, VINN, respectively, of <FIG>, and the outputs of switches <NUM>, <NUM> may connect to VINP, VINN, respectively, of another instance of the circuit of <FIG> that implement second capacitor array <NUM>'. The inputs to comparator <NUM> of <FIG> can be combining nodes VXP, VXN for first capacitor array <NUM>' and VYP, VYN for second capacitor array <NUM>'. This is sometimes referred to as bottom plate sampling.

Another alternative is top plate sampling, wherein the analog inputs AINP, AINN to first capacitor array <NUM>' may connect to combining nodes VXP, VXN to comparator <NUM> (<FIG>). The circuit of <FIG> is changed to have AINP or VINP switched to VXP to the upper input of comparator <NUM>, and to have AINN or VINN switched to VXN to the lower input of comparator <NUM>. Signal loss can be reduced with top plate sampling, but additional calibration may be needed. Other variations are possible.

While switched-capacitor SAR ADC stages have been shown, flash-ADC stages may be substituted for a pipeline-flash ADC. A hybrid ADC may have a flash ADC for one stage, and a SAR-ADC for the other stage. While first capacitor array <NUM> with a <NUM>-bit resolution and second capacitor array <NUM> with an <NUM>-bit resolution have been described, other resolutions may be substituted, such as <NUM>-bit/<NUM>-bit, <NUM>-bit/<NUM>-bit, etc. Various redundancy and calibration may be implemented.

While two stages with SAR1 <NUM>, first capacitor array <NUM>, and SAR2 <NUM>, second capacitor array <NUM>, have been shown, more stages could be added, such as by having second capacitor array <NUM> output its residue voltage to another residue amplifier <NUM>, which then drives a third capacitor array that is converted by a third SAR. Offset corrector <NUM> could be embedded with each residue amplifier, or only in the first residue amplifier and not in subsequent residue amplifiers.

While a single-ended ADC has been shown and described for better understanding of the principles and operation, the differential ADC shown has better matching and noise rejection. While an embodiment of amplifier <NUM> and of differential amplifier <NUM> have been shown, other amplifier circuits and types of amplifiers may be substituted. Likewise, first and second order low-pass filters <NUM> and differential low-pass filter <NUM> have been shown, other filter circuits may be used. Additional components may be added. Many circuit implementations of residue amplifier <NUM> and differential residue amplifier <NUM> are also possible. Variations of offset corrector <NUM> and differential offset corrector <NUM> are also possible. Offset voltage can be reduced by <NUM>-<NUM>% using offset correction.

Terms such as top, bottom, up, down, upper, lower, etc. are relative and are not meant to be limiting. Inversions may be added, such as by swapping + and - inputs or outputs, or by adding inverters. While a simple two-phase clocking scheme has been described, with phase P1 and phase P2, more complex clocking may be substituted, and three, four, or more phases may be used. Clock signals may be delayed to some switches. Timing skews may be added. Additional equalizing or biasing switches may be added, such as between VIN, VIP in <FIG>. While analog voltages have been described, analog currents could also be converted and the residue could be a residue current.

While n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and p-channel transistors have been described, other kinds of transistors that can be substituted, such as bipolar NPN, PNP, Fin Field-Effect Transistor (FinFET), or Junction FET (JFET).

Current sources could be approximated or implemented as transistors having gate and drains connected together, or depletion mode transistors or native transistors. Self-biasing or bandgap reference voltages may be used.

Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also be present. Enabling and disabling the circuit could be accomplished with additional transistors or in other ways. Pass-gate transistors or transmission gates could be added for isolation. Inversions may be added, or extra buffering. Capacitors may be connected together in parallel to create larger capacitors that have the same fringing or perimeter effects across several capacitor sizes. Switches could be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors, or more complex circuits, either passive or active, amplifying or non-amplifying.

The background of the present invention section may contain background information about the problem or environment of the present invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant.

Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.

Claim 1:
A multi-stage Analog-to-Digital Converter , ADC, with an embedded offset corrector comprising:
a first ADC stage that converts an analog input into a first M digital bits that represent an analog value of the analog input, wherein M is a whole number of at least <NUM>, the first ADC stage outputting a residue after quantization of the analog input to the first M digital bits;
a residue amplifier (<NUM>) having a first input that receives the residue from the first ADC stage and generates a first output;
a feedback capacitor (<NUM>) connected between the first input and the first output of the residue amplifier (<NUM>);
a second ADC stage that converts the first output from the residue amplifier (<NUM>) into a second N
digital bits that represent an analog value of the first output from the residue amplifier (<NUM>), wherein N is a whole number of at least <NUM>;
an offset corrector (<NUM>) comprising a low-pass filter (<NUM>) that directly receives the first output from the residue amplifier (<NUM>) and generates a filtered offset; an offset amplifier (<NUM>) that receives the filtered offset and generates a buffered offset; an offset capacitor (<NUM>) for storing the buffered offset; and
an offset switch (<NUM>), connected between the offset capacitor (<NUM>) and the first input of the residue amplifier (<NUM>), the offset switch (<NUM>) applying the buffered offset stored on the offset capacitor (<NUM>) to the first input to permit charge transfer or charge sharing on the first input.