Patent Description:
Virtual machines running on a host may use memory addresses that differ from those used by the operating system of the host. As such, when the operating system arranges for data to be read from, or written to, a persistent storage device, address translations may be performed. The communications that may occur between the host and the persistent storage device regarding such address translations may affect the latency of operations performed by the persistent storage device.

It is with respect to this general technical environment that aspects of the present disclosure are related.

<CIT> relates to managing an asymmetric memory system as a cache device.

In some embodiments, the host may prepopulate an address translation cache of the persistent storage device with the address translation before, or in parallel with, sending the input-output command to the persistent storage device. In such an embodiment, the persistent storage device may begin performing direct memory access to execute the input-output command without first requesting, and waiting for, the address translation.

According to an embodiment of the present disclosure, there is provided a method, including: receiving, by a persistent storage device, a first address translation cache entry; receiving, by the persistent storage device, an input-output command; and executing the input-output command, by the persistent storage device, the executing of the input-output command including performing direct memory access of a memory location at an address calculated based on the input-output command and based on the first address translation cache entry.

In some embodiments, the input-output command is a write command.

In some embodiments, the receiving of the first address translation cache entry includes receiving a Peripheral Component Interconnect Express (PCIe) command including the first address translation cache entry.

In some embodiments, the PCIe command further includes an identifier identifying a host process, a virtual address used by the host process, and an address translation.

In some embodiments, the method further includes storing the first address translation cache entry in a segment of an address translation cache of the persistent storage device, the segment being reserved for prepopulated address translation cache entries.

In some embodiments, the method further includes: determining a first weight for the first address translation cache entry; determining a second weight for a second address translation cache entry stored in an address translation cache of the persistent storage device; determining that the first weight exceeds the second weight; evicting the second address translation cache entry from the address translation cache; and storing the first address translation cache entry in the address translation cache.

In some embodiments, the receiving of the first address translation cache entry includes: implementing, by the persistent storage device, a snoop of an address location; detecting, by the persistent storage device, through the snoop, that a value stored at the address location has been replaced with a new value; and copying, by the persistent storage device, the new value into an address translation cache of the persistent storage device.

In some embodiments, the memory location is the memory location of a Scatter Gather List (SGL) pointer or of a Physical Region Page (PRP) pointer.

According to an embodiment of the present disclosure, there is provided a method, including: detecting, by a host, a write of an input-output command into a submission queue; and sending, by the host, in response to the detecting, a first address translation cache entry to a persistent storage device.

In some embodiments, the sending of the first address translation cache entry includes sending a Peripheral Component Interconnect Express (PCIe) command including the first address translation cache entry.

In some embodiments, the method further includes reserving a segment of an address translation cache of the persistent storage device for prepopulated address translation cache entries.

In some embodiments, the method further includes detecting, by the host, that the input-output command is at a position in the submission queue leading a head doorbell of the submission queue by a set number.

According to an embodiment of the present disclosure, there is provided a persistent storage device, including: a processing circuit; and a memory, operatively connected to the processing circuit and storing instructions that, when executed by the processing circuit, cause the persistent storage device to perform a method, the method including: receiving a first address translation cache entry; receiving an input-output command; and executing the input-output command, the executing of the input-output command including performing direct memory access of a memory location at an address calculated based on the input-output command and based on the first address translation cache entry.

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of a system and method for host provided address translation cache prepopulation provided in accordance with the present disclosure and is not intended to represent the only forms in which the present disclosure may be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the disclosure. As denoted elsewhere herein, like element numbers are intended to indicate like elements or features.

When a persistent storage device receives an input-output command from a virtual machine running on a host connected to the persistent storage device, the persistent storage device may request an address translation from a translation agent of the host. The persistent storage device may then translate a virtual address that is part of the input-output command into a physical address in the memory of the host, and execute the input-output command, accessing host memory at the physical address using direct memory access. The steps involved in obtaining and applying the address translation may increase the latency exhibited by the persistent storage device in executing the input-output command.

As such, in some embodiments, the host may send an address translation to the persistent storage device without waiting for the persistent storage device to request the address translation. For example, a virtual machine monitor in the host may monitor submission queue entries generated by virtual machines running in the host. When the virtual machine monitor determines, from a submission queue entry, that the persistent storage device will need an address translation to process the submission queue entry, it may request, from the translation agent, on behalf of the persistent storage device, the address translation that the persistent storage device will need, and the translation agent may then send the address translation to the persistent storage device, where the address translation may be placed in an address translation cache.

<FIG> is a block diagram of a host <NUM> connected to a persistent storage device <NUM>. The persistent storage device <NUM> may be, for example, a nonvolatile memory express (NVMe) solid state drive (SSD), and it may share an enclosure with the host <NUM>, or it may be an external persistent storage device <NUM>. The host <NUM> may include a host processor including one or more Central Processing Units (CPUs) <NUM>, a memory <NUM>, a translation agent (TA) <NUM> connected to an Address Translation and Protection Table (ATPT) <NUM> and a Root Complex (RC) <NUM> (which may be a Peripheral Component Interconnect Express (PCIe) Root Complex). The persistent storage device <NUM> may include a controller <NUM>, an address translation cache (ATC) <NUM>, and a nonvolatile memory <NUM> (which may be, e.g., NAND Flash memory). The controller <NUM> may be, or include, a processing circuit, discussed in further detail below. The nonvolatile memory <NUM> may store instructions that, when executed by the processing circuit, cause the first server to perform one or more of the methods disclosed herein.

In operation, a host process (e.g., a virtual machine (VM)) may be running on the CPU <NUM>. The host process (e.g., the virtual machine) may use virtual addresses (or "virtualized addresses"), and it may send commands (e.g., input-output commands such as read commands and write commands) to the persistent storage device <NUM>. A read command, for example, may be a command sent to the persistent storage device <NUM> instructing it to place certain data in the memory <NUM>, beginning at a specified physical address in the memory <NUM>, using direct memory access (DMA). Such a command, when sent by a virtual machine, may include a reference to a virtual address or virtual address range used by the virtual machine; this virtual address range may differ by one or more offsets over portions of the virtual address range from the physical address range(s), in the memory <NUM>, to which the data are to be written. In one embodiment, the range of contiguous addresses may be called "Page Size". Each Page may have a different offset, and this offset may be referred to as an "address translation". Similarly, if the input-output command is a write command, the command may include a virtual address which may need to be translated to a physical address from which the persistent storage device <NUM> will fetch, using direct memory access, the data to be stored in the persistent storage device <NUM>. Similarly, if the input-output command uses metadata such as Protection Information (PI) to protect the data while in transit and in storage, the persistent storage device <NUM> will fetch, using direct memory access, the data to be stored and used for the PI checks. <FIG> shows the fields of an NVMe submission queue (SQ) entry. Within this SQ entry, the fields that may contain virtual addresses which may be translated before data transfers using direct memory access are performed include a metadata pointer, and pointers to (i) Physical Region Page (PRP) Entry <NUM> (or Scatter Gather List (SGL) part <NUM>) and to (ii) PRP Entry <NUM> (or SGL part <NUM>). Other fields in the SQ entry include (i) an OpCode, which specifies whether a read, write, or other command is to be performed, (ii) a PRP/SGL flag, specifying either the data are in SGL or PRP format, (iii) a starting LBA specifying the starting logical block address for the logical blocks to be read or written within the persistent storage device <NUM>, and (iv) a number of LBAs, specifying the number of logical blocks to be read or written.

The address translation may be in the address translation cache <NUM> of the persistent storage device <NUM>, e.g., if it was recently used. If the address translation is not in the address translation cache <NUM>, the persistent storage device <NUM> may request the address translation from the translation agent <NUM> (which may determine the address translation based on values stored in the Address Translation and Protection Table <NUM>) before beginning to access (e.g., read from or write to) the memory <NUM> using direct memory access. A Page Request Interface (PRI) may or may not be paired with the address translation request, depending on whether the data to be accessed has been swapped out of the memory <NUM>. Once the address translation has been saved in the address translation cache <NUM>, data transfer to or from the host memory (which may be, e.g., host SRAM inside the processor or host DRAM connected to the processor) using direct memory access may begin.

The steps of requesting, and waiting for, an address translation, by the persistent storage device <NUM>, after having received a command from the host, may contribute significantly to the latency exhibited by the persistent storage device <NUM>. As such, in some embodiments, the host <NUM> may prepopulate the address translation cache <NUM> with the address translation without waiting for a request, from the persistent storage device <NUM>, for the address translation. The host <NUM> may be aware of the set of addresses that will be needed by the device for the metadata, SGL, and PRP. Both PRP and SGL may be pointers to additional memory addresses that require additional address translations. The SGLs, for example, may include SGL1 and SGL2 pointing to another SGL descriptor. SGL2 may be an SGL descriptor that may be located using an address translation. Therefore in order to locate all parts of the metadata, SGL, and PRPs in host memory, the memory addresses that are pointers within the metadata, SGL, and PRP structures may also be translated.

Referring to <FIG>, the host <NUM> may include a virtual machine monitor <NUM>, which may monitor the submission queues of the virtual machines running in the host <NUM>. When the virtual machine monitor <NUM> detects that a new entry has been placed in the submission queue of a virtual machine (or, as discussed in further detail below, that a submission queue entry, for which address translation cache <NUM> has not yet been prepopulated, is within a threshold lead amount of the head doorbell of the submission queue), it prepopulates the address translation cache <NUM> with the address translations (e.g., including (i) one or more address translations for the three fields shown in <FIG> that may contain virtual addresses which may be translated before data transfers using direct memory access are performed, and additional translations, if needed, for SGL pointers or PRP pointers, as described above) needed to execute the input-output command associated with the submission queue entry.

The host <NUM> may prepopulate the address translation cache <NUM> as follows. The CPU or the virtual machine monitor <NUM> may send, on behalf of the persistent storage device <NUM>, to the translation agent <NUM>, an address translation command requesting that an address translation be determined (e.g., calculated, or looked up in the Address Translation and Protection Table <NUM>) and sent to the persistent storage device <NUM>. The address translation command may include the target PCIe device (e.g., an identifier identifying the PCIe device to which the address translation is to be sent), optionally an identifier for the virtual machine such that the Translation Agent understands how to do the translation, and the virtual address for which an address translation will be needed by the persistent storage device <NUM>. The PCIe device may be a single PCIe device or a function within a PCIe device. It may optionally be identified by a PASID (Process Address Space ID) and or Requester ID of the target PCIe device.

An address translation caching command (e.g., a PCIe command) may then be sent, by the translation agent <NUM>, to the persistent storage device <NUM>. The PCIe standard may be extended to include such a command. The address translation caching command may include (i) an identifier identifying the host process (e.g., the virtual machine) that originated the input-output command (e.g., it may include the Requestor ID (identifying the persistent storage device <NUM>; it may be referred to as the "Requestor ID" even though in some embodiments the virtual machine monitor <NUM> is making the request, on behalf of the persistent storage device <NUM>)), (ii) the virtual address used by the host process (e.g., used by the virtual machine), (iii) the address translation to be saved to the address translation cache <NUM> (and to be used to determine the physical address in the memory <NUM> to be accessed using direct memory access), (iv) a length which represents a range of how many address translations were provided, (v) optionally an identifier of the VM monitor or a flag (e.g., a new response code or identifying field in the PCIe packet) indicating that the address translation was requested by something other than the persistent storage device <NUM> itself. Upon receipt of the address translation caching command, the persistent storage device <NUM> may store the address translation in the address translation cache <NUM>, for use in direct memory access in executing the corresponding input-output command, when the corresponding input-output command is being processed.

In some embodiments the host <NUM> or the persistent storage device <NUM> may incorporate measures (or "policies") to avoid overfilling the address translation cache <NUM>, which may result in (i) the persistent storage device <NUM> declining to store an address translation it receives from the host (e.g., if the address translation cache <NUM> is full or nearly full), or in (ii) the persistent storage device <NUM> evicting one or more entries from the address translation cache <NUM> to accommodate a newly received address translation. For example, the persistent storage device <NUM> may store, in the address translation cache <NUM>, both (i) all entries that the persistent storage device <NUM> has received from the translation agent <NUM> in response to requests submitted to the translation agent <NUM> by the persistent storage device <NUM>, and (ii) entries that the persistent storage device <NUM> has received from the translation agent <NUM> in response to requests submitted to the translation agent <NUM> by the virtual machine monitor <NUM>. A function for assigning a respective weight to each entry in the address translation cache <NUM> may be defined, and this function may be evaluated for some or all of the entries in the address translation cache <NUM>, e.g., periodically, or when new entries for the address translation cache <NUM> are received, to determine whether to store newly received entries and whether to evict entries in the address translation cache <NUM>. For example, the function may assign a greater weight to recently received entries, or to recently used entries, and it may assign a high weight (e.g., a weight that prevents eviction under all circumstances) to an entry that is being used for a direct memory access data transfer that is still in progress. For example, a function may assign a medium weight for recently received entries the persistent storage device <NUM> requested itself, and a function may assign a low weight for recently received entries the virtual machine monitor <NUM> sent on behalf of the persistent storage device <NUM>.

As another example, the address translation cache <NUM> may be partitioned into two segments, which may be referred to as a "host-controlled" segment and a "device-controlled" segment. For example, the host <NUM> may send a command to the persistent storage device <NUM> instructing the persistent storage device <NUM> to reserve a segment of the address translation cache <NUM> as the host-controlled segment, or the persistent storage device <NUM> may, e.g., at startup, communicate to the host <NUM> the size of the host-controlled segment. The contents of the host-controlled segment may be controlled exclusively by the host <NUM>, e.g., to prepopulate the address translation cache <NUM>. The host <NUM> may then have choices regarding how to populate the host-controlled segment. For example, the host-controlled segment may operate as a first-in, first-out (FIFO) data structure (with the oldest entry evicted first, when the host-controlled segment is full), or candidates for eviction from the host-controlled segment may be selected according to another algorithm (e.g., using random replacement, using a queue-based policy, using a recency-based policy (e.g., one in which the least-recently used entry may be evicted first), using a frequency-based policy, or using a policy based on machine learning). Either the host <NUM> or the persistent storage device <NUM> may control eviction from the host-controlled segment. In some embodiments, the host <NUM> specifies, to the persistent storage device <NUM>, the algorithm (or "policy") to be used to control eviction from the host-controlled segment, and the persistent storage device <NUM> executes the specified algorithm to control evictions. The device-controlled segment may be used by the persistent storage device <NUM> to store address translations that it receives after requesting them from the translation agent <NUM>.

In some embodiments, if the host submission queue is deeply queued, then there may be a risk of the host <NUM> flooding the address translation cache <NUM> of the persistent storage device <NUM> with more prepopulated address translations than it can accommodate. As such, to avoid overfilling the address translation cache <NUM>, the host <NUM> may receive the submission queue head doorbell updates from the drive, assume that the persistent storage device <NUM> drive progress will prioritize commands near the submission queue head doorbell, and therefore prioritize the sending of address translation cache entries that are nearer the head doorbell. For example, referring to <FIG>, in some embodiments, therefore, the host <NUM> monitors updates of the submission queue head doorbell (HDB) <NUM>, as the persistent storage device <NUM> reads entries from the submission queue and advances the submission queue head doorbell. The host may then send one or more new address translation requests to the translation agent on behalf of the device when the input-output command (to which the entry corresponds) is at a position <NUM> in the submission queue leading the submission queue head doorbell by no more than a set number (e.g., by no more than ten, which would mean that the input-output command is tenth in line to be read into the persistent storage device <NUM>). In another embodiment, the host <NUM> may wait until there are no entries left in the submission queue for which an address translation has already been sent to the persistent storage device <NUM>, and it may then send a fixed number N (e.g., ten) entries to the address translation cache <NUM>. In another embodiment, the host <NUM> may request that the translation agent <NUM> send a number of address translation requests as a function of the device's speed (submission queue (SQ) entries or completion queue entries per second). In another embodiment, the host <NUM> may have a number N for reads and a different number M for writes. The virtual machine monitor <NUM> may send the translation request depending on the SQ HDB progress and the command type of the submission queue entry (SQE). Write operations may use address translation immediately, to transfer the data into the device immediately, whereas a read operation may not transfer data into the host until after some time delay and may not use address translation immediately. As such, in some embodiments, the virtual machine monitor <NUM> may choose to not send translation requests for reads, or it may choose to send translation requests for reads after a time delay.

In operation, the host <NUM> may fill out one or more submission queue entries, and update the submission queue tail doorbell (TDB) <NUM> to inform the persistent storage device <NUM> of the new commands in the submission queue. The persistent storage device <NUM> may, at the same time, be independently reading one or more submission queue entries from the other side of the submission queue. The persistent storage device <NUM> may update the submission queue head doorbell as it does so, to inform the host <NUM> that those submission queue entries have been parsed by the persistent storage device <NUM> and that they are being processed within the persistent storage device <NUM>.

The host <NUM> then uses the submission queue head doorbell value and the submission queue entry format to identify, within the submission queue entries, memory addresses that will need address translation by the persistent storage device <NUM> (e.g., the three fields, of the fields shown in <FIG>, that may contain virtual addresses which may be translated before data transfers using direct memory access are performed). The host <NUM> then sends an address translation command to the translation agent <NUM> to instruct the translation agent <NUM> to send the address translations to the device, using the address translation caching command. The persistent storage device <NUM> receives the address translation caching command and, in accordance with policies it has in place for managing the address translation cache <NUM>, stores the address translations in the address translation cache <NUM> (or, if the policies dictate otherwise, discards the address translations).

In some embodiments, instead of the host <NUM> sending address translations to the persistent storage device <NUM>, the host <NUM> may make the address translations available for the persistent storage device <NUM> to fetch. For example, the host <NUM> may request an address translation from the translation agent <NUM> for some or all relevant addresses for an input-output command (e.g., for the three fields, of the fields shown in <FIG>, that may contain virtual addresses which may be translated before data transfers using direct memory access are performed), and put the address translations in one location (e.g., in the memory <NUM>) for the persistent storage device <NUM> to fetch (e.g., using direct memory access) and to insert into the address translation cache <NUM>. For example, the location may be an additional metadata area in the memory <NUM>, or unused space in a submission queue entry (to accomplish this the size of submission queue entries may be increased), or in a permanently agreed-upon location in Compute Express Link cache (CXL. cache) address space, such that the persistent storage device <NUM> is able to recognize the update from the host <NUM>, and it is able to copy it into the address translation cache <NUM>.

Other memory locations (e.g., in the memory <NUM>, in PCIe Base Address Register (BAR) space, in Controller Memory Buffers (CMBs), or in CXL. mem) may be used in an analogous manner; in such a case the persistent storage device <NUM> may not receive snoop alerts and may therefore periodically trigger re-reads of these locations.

In such an embodiment, the virtual machine monitor <NUM> may be requesting the address translations from the translation agent <NUM> when the submission queue entry has already been sent to the persistent storage device <NUM>. This may mean that a translation agent <NUM> initiating an address translation invalidation may only know of the virtual machine monitor <NUM> requesting the translation. Therefore, invalidations may be sent to the virtual machine monitor <NUM>, but the persistent storage device <NUM> may be reading this shared memory location at any time. This may result in a race condition of the address translation invalidation and the device reading the address translation. The CPU <NUM> may therefore be responsible for implementing a coherent read and update scheme on such a memory space. In one embodiment, a CPU <NUM> may implement a vendor specific coherency scheme. In another embodiment, the coherency of CXL. cache may be leveraged. The persistent storage device <NUM> may set up a snoop to be alerted when there are writes on the shared memory location. In another embodiment, the host <NUM> may implement a locking scheme over the shared memory location for the address translations. The layout of address translation values in such a memory location may include (i) DWORD <NUM>: Number of valid translations, (ii) DWORD <NUM>&<NUM>: virtual address, and (iii) DWORD <NUM>&<NUM>: physical address. The CPU may then lock the shared memory location, update the header and modify the address translation list, and unlock the shared memory location. In another embodiment, the translation agent <NUM> may broadcast address translation invalidations to all connected memory address users independent of their location, for example by appending an "invalidate entry" or lock and modifying address translation values.

In some embodiments, instead of the host <NUM> sending address translations to the persistent storage device <NUM> using an address translation caching command, the host <NUM> may populate a pre-translated address in the submission queue entry. The host <NUM> may then also communicate to the persistent storage device <NUM> that it has already provided the translated address. This communication may take the form, for example, of (i) one or more bits in the submission queue entry stating that the addresses (e.g., in the three fields, of the fields shown in <FIG>, that may contain virtual addresses which may be translated before data transfers using direct memory access are performed) are already translated; or (ii) a setting on the persistent storage device <NUM>, NVMe Subsystem, NVMe controller, NVMe Namespace, etc., that informs the persistent storage device <NUM> that it will always be provided translated addresses.

In another embodiment, the NVMe expectations for metadata, PRP, and/or SGL data locations may be modified. For example, the PRP or SGL linked lists may be modified to first point to a buffer of relevant address translations of all of the PRPs and SGLs followed by the normal PRPs and SGLs required for the command. In this embodiment, the virtual machine might leave the first segment blank followed by filling out the normal PRP and SGL information. The virtual machine monitor <NUM> may then fill out the first PRP or SGL with valid address translations and mark them as valid translations. Such an embodiment may avoid the need for the persistent storage device <NUM> to request a translation or to fill space in the address translation cache because each address in the submission queue entry may already be correct.

Although examples are given herein in the context of a host <NUM> interacting with a persistent storage device <NUM>, it will be understood that the systems and methods disclosed herein are equally applicable to peers on PCIe and Fabrics and different memory locations. Moreover, in some embodiments, an address translation request may be made on behalf of the persistent storage device <NUM> by another component. For example, a second host processor (e.g., in the case of a dual ported host) may send an address translation request to the translation agent <NUM> within the first host <NUM>, or a graphics processing unit (GPU) may send an address translation request to the translation agent <NUM> within the first host processor.

The persistent storage device <NUM> may have a form factor that is any one of a plurality of form factors suitable for persistent storage devices, including but not limited to <NUM>", <NUM>", MO-<NUM>, MO-<NUM>, M. <NUM>, and Enterprise and Data Center SSD Form Factor (EDSFF), and it may have an electrical interface, through which it may be connected to the host <NUM>, that is any one of a plurality of interfaces suitable for persistent storage devices, including Peripheral Component Interconnect (PCI), PCI express (PCIe), Ethernet, Small Computer System Interface (SCSI), Serial AT Attachment (SATA), and Serial Attached SCSI (SAS).

<FIG> is a flowchart of a first method. In some embodiments, the method includes receiving, at <NUM> by a persistent storage device, a first address translation cache entry; receiving, at <NUM>, by the persistent storage device, an input-output command; and executing, at <NUM>, the input-output command, by the persistent storage device, the executing of the input-output command including performing direct memory access of a memory location at an address calculated based on the input-output command and based on the first address translation cache entry. <FIG> is a flowchart of a second method. In some embodiments, the method includes detecting, at <NUM>, by a host, a write of an input-output command into a submission queue; and sending, at <NUM>, by the host, in response to the detecting, a first address translation cache entry to a persistent storage device.

As used herein, "a portion of" something means "at least some of" the thing, and as such may mean less than all of, or all of, the thing. As such, "a portion of" a thing includes the entire thing as a special case, i.e., the entire thing is an example of a portion of the thing. As used herein, the term "or" should be interpreted as "and/or", such that, for example, "A or B" means any one of "A" or "B" or "A and B".

The background provided in the Background section of the present disclosure section is included only to set context, and the content of this section is not admitted to be prior art. Any of the components or any combination of the components described (e.g., in any system diagrams included herein) may be used to perform one or more of the operations of any flow chart included herein. Further, (i) the operations are example operations, and may involve various additional steps not explicitly covered, and (ii) the temporal order of the operations may be varied.

The term "processing circuit" is used herein to mean any combination of hardware, firmware, and software, employed to process data or digital signals. Processing circuit hardware may include, for example, application specific integrated circuits (ASICs), general purpose or special purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs). In a processing circuit, as used herein, each function is performed either by hardware configured, i.e., hard-wired, to perform that function, or by more general-purpose hardware, such as a CPU, configured to execute instructions stored in a non-transitory storage medium. A processing circuit may be fabricated on a single printed circuit board (PCB) or distributed over several interconnected PCBs. A processing circuit may contain other processing circuits; for example, a processing circuit may include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

As used herein, when a method (e.g., an adjustment) or a first quantity (e.g., a first variable) is referred to as being "based on" a second quantity (e.g., a second variable) it means that the second quantity is an input to the method or influences the first quantity, e.g., the second quantity may be an input (e.g., the only input, or one of several inputs) to a function that calculates the first quantity, or the first quantity may be equal to the second quantity, or the first quantity may be the same as (e.g., stored at the same location or locations in memory as) the second quantity.

Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "<NUM> to <NUM>" or "between <NUM> and <NUM>" is intended to include all subranges between (and including) the recited minimum value of <NUM> and the recited maximum value of <NUM>, that is, having a minimum value equal to or greater than <NUM> and a maximum value equal to or less than <NUM>, such as, for example, <NUM> to <NUM>. Similarly, a range described as "within <NUM>% of <NUM>" is intended to include all subranges between (and including) the recited minimum value of <NUM> (i.e., (<NUM> - <NUM>/<NUM>) times <NUM>) and the recited maximum value of <NUM> (i.e., (<NUM> + <NUM>/<NUM>) times <NUM>), that is, having a minimum value equal to or greater than <NUM> and a maximum value equal to or less than <NUM>, such as, for example, <NUM> to <NUM>. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

Claim 1:
A method, comprising:
receiving (<NUM>), by a persistent storage device (<NUM>), a first address translation cache entry;
receiving (<NUM>), by the persistent storage device (<NUM>), an input-output command;
executing (<NUM>) the input-output command, by the persistent storage device (<NUM>),
the executing (<NUM>) of the input-output command comprising performing direct memory access of a memory location at an address calculated based on the input-output command and based on the first address translation cache entry; and
storing the first address translation cache entry in a segment of an address translation cache (<NUM>) of the persistent storage device (<NUM>), the segment being reserved for prepopulated address translation cache entries.