Patent Description:
The demand for IC dies or chip assemblies for higher performance, higher capacity and lower cost has driven the demand for small sizes and more capable microelectronic components. Furthermore, the distribution and the distance among the IC dies also becomes denser and closer. Proper thermal management and cooling of the chip assemblies during operation has become increasing important.

However, due to the space constraints of the IC package, some chip assemblies may have lower cooling efficiency than others, resulting in overheating. Such overheating may result in device failure or electrical performance deterioration.

<CIT> discloses methods and apparatus for dissipating heating from a die assembly.

All following occurrences of the word "embodiments(s)", if referring to feature combinations different from those defined by the independent claims, refer to examples which were originally filed but which do not represent embodiments of the presently claimed invention; these examples are still shown for illustrative purposes only.

The present disclosure relates to an IC die comprising a temperature control element. The temperature control element may be an integral part of the IC die that may assist temperature control of the IC die when in operation. When such IC die with temperature control element is assembled in an IC package, the thermal dissipation efficiency for the overall IC package is then enhanced. In one example, an integrated circuit (IC) die includes a substrate. A temperature control element is formed on a first side of the substrate. A plurality of device structures is formed on a second side of the substrate. The temperature control element is formed as an integral part of the IC die.

In one example, the first side is opposite to the second side. An activation layer is formed between the plurality of device structures and the temperature control element. In one example, the temperature control element includes a plurality of vias formed in a base structure. The vias are blind vias having an end embedded in the base structure. The vias are open vias having both ends formed at outer surfaces of the base structure. A heat dissipation material is disposed in the vias in the base structure. The heat dissipation material includes at least one of ceramic materials, semiconductor materials, graphite, diamond, or organic materials.

In one example, the plurality of vias includes a first group of the vias having a first pitch density formed in an edge portion of the base structure. A second group of the vias having a second pitch density different from the first pitch density formed in a center portion of the base structure. The base structure comprises silicon. The IC die is an application specific integrated circuit (ASIC).

Another aspect of the technology is directed to an integrated circuit (IC) package. The IC package includes an IC die disposed on a package substrate. The IC die has a temperature control element disposed on a first side of a substrate and a plurality of devices formed on a second side of the substrate. One or more memory stacks are formed on the package substrate adjacent to the IC die. A heat distribution device is disposed on the IC die.

In one example, the temperature control element has an upper surface facing the heat distribution device and a lower surface facing the first side of the substrate. The temperature control element includes a plurality of vias formed in a base structure. The temperature control element includes a heat dissipation material disposed in the vias in the base structure. The heat dissipation material comprises at least one of conductive materials, ceramic materials, metal-ceramic composite materials, metal alloy materials, semiconductor materials, graphite, diamond, or organic materials.

In one example, the plurality of vias includes a first group of the vias having a first pitch density formed in an edge portion of the base structure. A second group of the vias having a second pitch density different from the first pitch density is formed in a center portion of the base structure. The base structure comprises silicon.

Yet another aspect of the technology is directed to a method for manufacturing a temperature control element in an IC die. The method includes reducing a thickness from a first side of a substrate, wherein the substrate has the first side and a second side opposite to the first side, wherein the second side has a plurality of devices formed thereon and bonding a temperature control element on the first side of the substrate.

In one example, the temperature control element comprises a plurality of vias formed in a silicon base structure.

The technology relates generally to an IC die including a temperature control element. The temperature control element may be an integral part of an IC die that may assist temperature control of the IC die when in operation. In one example, the IC die may have a substrate having a first side coupled to the temperature control element and a second side including a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like formed therein. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation. The heat dissipation material disposed in the temperature control element may be distributed in a manner that can dissipate localized thermal energy generated by the plurality of devices when the devices are in operation. Thus, different configurations of the temperature control element may accommodate different device layouts with different thermal energy generation across the substrate in the IC die.

The present disclosure may comprise the following: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

<FIG> depicts a cross sectional-view of an IC package <NUM> including multiple chip assemblies formed on an interposer <NUM>. For example, the IC package <NUM> may include at least one IC die <NUM>, such as at least a core or main IC logic die. A plurality of memory devices chip assemblies 105a, 105b may be formed in close proximity to the IC die <NUM>. In the example depicted in <FIG>, two memory device chip assemblies 105a, 105b are shown and disposed in close proximity to one IC die <NUM>. It is noted that the IC die and the devices chip assemblies disposed in the IC package <NUM> may be in any numbers. In one example, the IC die <NUM> utilized herein may be a graphics processing unit (GPU), custom application-specific integrated circuit (ASIC), or the like. The memory device chip assemblies 105a, 105b utilized herein may be high-bandwidth memory (HBM) components or any other type of memory or non-memory devices or stacks.

In one example, the IC die <NUM> and the memory device chip assemblies 105a, 105b are disposed on the interposer <NUM> through the plurality of connectors <NUM>. The connectors <NUM> may be gold, nickel, tin, copper, solder, aluminum, tungsten or other suitable conductive materials. The IC die <NUM> and the memory devices chip assemblies 105a, 105b are electrically and/or physically connected through respective plurality of connectors (not shown) formed in the interposer <NUM>.

The interposer <NUM> may have a plurality of through substrate vias (TSVs) <NUM> formed across a body of the interposer <NUM>. The TSVs <NUM> may provide electrical connection channels to facilitate electrical connection of the IC dies <NUM> and the memory devices 105a, 105b to a package substrate <NUM> disposed thereunder. The interposer <NUM> and the package substrate <NUM> may assist integrating and stacking multiple dies, components, devices, chip assemblies and chiplets in a vertical three-dimensional (3D) fashion. Such arrangement may improve the packaging density.

In one example, the package substrate <NUM> may further have TSVs or interconnection channels <NUM> to facilitate connection of the package substrate <NUM> to a printed circuit board (PCB) <NUM>, socket, or other such chip carrier, through a plurality of solder balls <NUM> arranged in a ball grid array (BGA). Other such arrangements and connectors may include contacts arranged in a land grid array (LGA), connector pins arranged in a pin grid array (PGA), etc..

The numbers and positions of the connectors <NUM>, TSVs <NUM>, <NUM>, or solder balls <NUM> depicted in <FIG> are only for illustration and can be arranged in any manners or arrangement based on the device performance designs, layouts and considerations.

In some examples wherein the interposer <NUM> is not present, the IC die <NUM> and the memory devices 105a, 105b may be disposed on the package substrate <NUM> or printed circuit board (PCB) <NUM> directly.

A heat distribution device <NUM> overlies a thermal interface material (TIM) <NUM> in contact with the IC die <NUM> and the memory devices chip assemblies 105a, 105b or other chip assemblies, if available. In one example, the heat distribution device <NUM> may include a plate lid <NUM> disposed on a plate base <NUM>. The plate base <NUM> may include a bottom surface <NUM> in direct contact with the TIM <NUM> and an opposed top surface <NUM> in contact with the plate lid <NUM>. Similarly, the plate lid <NUM> may include a bottom surface <NUM> facing the top surface <NUM> of the plate base <NUM>, and an opposed top surface <NUM> from which an inlet 176A and one or more outlets 176B may extend. In other examples, the number and configuration of inlets and outlets can vary, such as there being two outlets directly adjacent to one another. The plate base <NUM> and the plate lid <NUM> may be manufactured using molding, machining, or similar processes.

The plate base <NUM> may include a plurality of thermally conductive fins <NUM>, which help to facilitate cooling of heat distribution device <NUM>. A first recess 165A and a second recess 165B are formed around the plurality of thermally conductive fins <NUM>. The fins <NUM> may be longitudinal structures protruding away from the top surface <NUM> of the plate lid <NUM>. The fins <NUM> may be integrally formed with the plate base <NUM> or with the plate lid <NUM> or may be attached to the plate base <NUM> by soldering, adhesive or the like. In this example, the fins <NUM> are integrally formed with the plate base <NUM>.

The plate lid <NUM> overlies the plate base <NUM>, such that the bottom surface <NUM> of plate lid <NUM> is directly adjacent to the top surface <NUM> of plate base <NUM>. Although not required, O-rings <NUM> may be provided within an edge portion of the plate base <NUM> so as to form a seal between plate base <NUM> and plate lid <NUM>. When joined together, the plate base <NUM> and the plate lid <NUM> enable fluids and/or gases, such as coolants, to flow into the heat distribution device <NUM> through the inlet 176A, and out of the heat distribution device <NUM> through the outlets 176B. O-rings <NUM> may also be provided adjacent to the inlets 176A and the outlets 176B to provide a seal between the inlet 176A and the outlets 176B and the components which may be connected thereto.

The plate base <NUM> and the plate lid <NUM> may be formed from known heat dissipating materials, such as aluminum, copper, silver, metal alloys, etc. In the example depicted in <FIG>, the plate base <NUM> and plate lid <NUM> are formed from the same or different materials.

A stiffener <NUM> extends between the heat distribution device <NUM> and the package substrate <NUM>. In one example, the stiffener <NUM> may be in ring or circular shape. The ring or circular shape of the stiffener <NUM> defines a center aperture <NUM> configured to surround the IC die <NUM> and the memory device chip assemblies 105a, 105b. The stiffener <NUM> may be disposed between the package substrate <NUM> and the plate base <NUM> of the heat distribution device <NUM>. An adhesive material (not shown) may be utilized at the interfaces between the package substrate <NUM> and the plate base <NUM> of the heat distribution device <NUM>. In one example, the size and shape and position of the center aperture <NUM> may be adapted based on circuitry of the underlying package substrate <NUM> to be exposed through the center aperture <NUM> or the arrangement of the IC die <NUM> and the memory device chip assemblies 105a, 105b or the interposer <NUM> within the center aperture <NUM>.

In one example, the stiffener <NUM> can be comprised of various materials. In one example, the stiffener <NUM> is formed from copper and is later plated with nickel (or similar metal) to promote adhesion to the package substrate <NUM>.

In one example, the thermal interface material (TIM) <NUM> may be manufactured from a material having a high thermal conductivity. The TIM <NUM> may be a first surface <NUM> in direct contact with the bottom surface <NUM> of plate base <NUM>. The TIM <NUM> has a second surface <NUM> opposite and parallel to the first surface <NUM>. The second surface <NUM> of the TIM <NUM> is in direct contact with the rear surfaces 144A, 144B, 144C of the IC die <NUM> and the memory device chip assemblies 105a, 105b respectively. The TIM <NUM> may be a high thermal conductivity material as well as having a low melting temperature. Suitable examples of TIM <NUM> include metal or graphite, such as nano Ag or Indium, but other high thermal conductivity TIM materials may be implemented. Additionally, in some implementations, an ultra-high thermal conductivity or low thermal conductivity material may be utilized for the TIM <NUM>.

The TIM <NUM> may be provided in any desired form, such as liquid, solid, semisolid, and the like. For example, the TIM <NUM> may be applied in liquid form, which will later be cured to form a soft elastomer. In some examples, the TIM <NUM> can be a grease, film, or solder.

<FIG> depicts a cross sectional view of an IC package <NUM> including an IC die <NUM>, which includes a temperature control element <NUM>, and the memory devices chip assemblies 105a, 105b. The structure of the IC package <NUM> is substantially similar to the IC package <NUM> depicted in <FIG> except that the configuration of the IC die <NUM> disposed in the IC package <NUM> may differ from the dies or chip assemblies disposed in the IC package <NUM>. For example, the IC die <NUM> may include a temperature control element <NUM> formed therein in close proximity to the devices formed in the IC die <NUM>. The IC die <NUM> is fabricated in a manner that includes the temperature control element <NUM> disposed therein. The temperature control element <NUM> may be disposed on a substrate <NUM> having a plurality of devices, such as semiconductor transistors, circuit or electric components, formed therein to perform the desired electrical functions and operations. The temperature control element <NUM> may include one or more heat dissipation materials formed therein to assist dissipating heat generated during operation. Details for the temperature control element <NUM> in the IC die <NUM> will be described below with reference to <FIG>, <FIG>, <FIG> and <FIG>.

In one example, the IC die <NUM> and/or the memory devices chip assemblies 105a, 105b may be in direct contact to the TIM <NUM> to further couple to the heat distribution device <NUM> so that the heat generated from the IC die <NUM> and/or the memory device chip assemblies 105a, 105b may be properly dissipated with the assistance from the heat distribution device <NUM>.

<FIG> depicts a cross sectional view of an integrated circuit (IC) package <NUM>, including an IC die <NUM>, which includes a temperature control element <NUM> and the memory devices chip assemblies 105a, 105b. The IC die <NUM> is fabricated in a manner that includes the temperature control element <NUM> disposed therein. The temperature control element <NUM> may be disposed on a substrate <NUM> having a plurality of devices, such as semiconductor transistors, circuits or electric components, formed therein to perform the desired electrical functions and operations. In one example, the temperature control element <NUM> may include one or more heat dissipation materials formed therein that have different configurations from the heat dissipation material configured in the temperature control element <NUM> depicted in <FIG>. It is noted that the configurations of the temperature control elements <NUM>, <NUM> utilized in the disclosure herein may include several different examples, which will be described further below with reference to <FIG>, <FIG>, <FIG> and <FIG>.

In one example, the IC die <NUM> and/or the memory devices chip assemblies 105a, 105b may be in direct contact to the TIM <NUM> to further couple to the heat distribution device <NUM>. In this example, the heat generated from the IC die <NUM> and/or the memory devices chip assemblies 105a, 105b may be dissipated with the assistance from the heat distribution device <NUM>. The fluids and/or gases, such as coolants, circulated into the heat distribution device <NUM> may assist dissipating away the thermal energy generated from the IC die <NUM> and/or the memory devices chip assemblies 105a, 105b during operation.

<FIG> depicts an example for forming an IC die <NUM>, such as the IC die <NUM>, <NUM> depicted in <FIG>, to include a temperature control element formed therein. In the example depicted in <FIG>, the IC die <NUM> includes a substrate <NUM>, such as a semiconductor substrate, having a substrate body <NUM>. The substrate <NUM> may include materials selected from at least one of crystalline silicon, such as Si<<NUM>> or Si<<NUM>>, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass and sapphire. In some examples, the substrate <NUM> may include a SOI structure, or a buried dielectric layer disposed on a silicon crystalline substrate or the like.

In the embodiments depicted herein, the substrate <NUM> is a material containing silicon , such as crystalline silicon substrate. Moreover, the substrate <NUM> is not limited to any particular size, shape or materials. The substrate <NUM> may be a round/circular substrate having a <NUM> diameter, a <NUM> diameter or other diameters, such as <NUM>, among others. The substrate <NUM> may also be any polygonal, square, rectangular, curved or otherwise noncircular workpiece, such as a polygonal glass substrate as needed.

In one example, the substrate body <NUM> includes a first side <NUM> and a second side <NUM> opposite to and substantially parallel to the first side <NUM>. A device region <NUM> is formed in and from the second side <NUM> of the substrate <NUM>. In one example, the device region <NUM> may include a plurality of transistors, electric components, circuits or devices <NUM>. The plurality of transistors, electric components, circuits or devices <NUM> may include a gate structure <NUM>, such as a FINFET structure, gate wrapped-around structure, gate all around structure or the like, in connection with an interconnection wire structure <NUM> and/or other required elements or components to enable the semiconductor device operations and functions. The plurality of transistors, electric components, circuits or devices <NUM> may be formed on a base region <NUM> in the substrate body <NUM>. The base region <NUM> may include other structures formed therein, such as shallow trench isolation (STI) structures with diffusion regions, such as active regions, formed therein and/or a fin structure formed around shallow trench isolation structure, such as a FINFET structure, gate wrapped-around structure, or gate all around structures, or any other suitable structures utilized in a semiconductor substrate.

As the transistors, electric components, circuits or devices <NUM> are formed on and from the second side <NUM> of the substrate <NUM>, an unused portion <NUM> of the substrate body <NUM> under the base region <NUM> remains unprocessed without the transistors, electric components, circuits or devices <NUM> formed therein. Such unused portion <NUM> of the substrate body <NUM> may be a certain thickness to facilitate manufacturing of the transistors or devices <NUM> from the second side <NUM> of the substrate <NUM> during the transistor manufacturing process, such as allowing robot arms to grip the substrate for processing without breaking the substrate. Once the transistors, electric components, circuits or devices <NUM> are formed, the unused portion <NUM> of the substrate body <NUM> may be polished away or removed to a desired thickness range for certain process requirements, such as for the subsequent chip packaging process. In one example depicted herein, the unused portion <NUM> of the substrate body <NUM> may be removed, thinned or polished away to a certain thin thickness level to facilitate forming a temperature control element thereon. In one example, a thickness of the unused portion <NUM> removed from the substrate may be in a range between about <NUM> and about <NUM>.

To facilitate polishing away the thickness of the unused portion <NUM> of the substrate body <NUM>, a sacrificial glue layer <NUM> may be formed on the second side <NUM> of the substrate <NUM>, as shown in <FIG>. Subsequently, a sacrificial carrier <NUM> may then be formed on the sacrificial glue layer <NUM>, as shown in <FIG>. The sacrificial carrier <NUM> may serve as a holding structure that allows a polishing head to carry the substrate <NUM> through the sacrificial carrier <NUM> during the backside polishing process without damaging the substrate <NUM>. In one example, the sacrificial carrier <NUM> may be any suitable substrate that may be bonded to the substrate <NUM> and carry the substrate <NUM> during the backside polishing process.

After the sacrificial carrier <NUM> is securely bonded to the substrate <NUM> through the sacrificial glue layer <NUM>, the substrate <NUM> may be transferred into a polishing tool <NUM> for performing the backside polishing process, as shown in <FIG>. The polishing tool <NUM>, as depicted in <FIG>. may be a chemical-mechanical polishing (CMP) tool, a single side grounding tool, or other suitable polishing tools. It is noted that the substrate <NUM> may be polished by any suitable polishing or material removal processes.

In one example, the polishing tool <NUM> includes a polishing head <NUM> configured to hold the sacrificial carrier <NUM>, thus, facing the first side <NUM> of the substrate <NUM> toward a polishing pad <NUM> disposed opposite to the polishing head <NUM> in the polishing tool <NUM>. The polishing pad <NUM> is positioned on a supporting pedestal <NUM>, which may be actuated to rotate during the polishing process. Once the polishing head <NUM> secures the sacrificial carrier <NUM> in place, an actuator <NUM> in the polishing tool <NUM> may actuate the polishing head <NUM> to rotate while lowering down the polishing head <NUM> to push the first side <NUM> of the substrate <NUM> against a top surface <NUM> of the polishing pad <NUM> for polishing. The pressure generated at the interface between the first side <NUM> of the substrate <NUM> and top surface <NUM> of the polishing pad <NUM> facilitates mechanical polishing therebetween to remove the materials from the first side <NUM> of the substrate <NUM>. The polishing pad <NUM> may also be rotated by the actuation from the supporting pedestal <NUM>. During polishing, a chemical slurry may or may not be supplied to the polishing pad <NUM> to facilitate polishing the substrate <NUM>, thinning the substrate body <NUM> until a predetermined thickness <NUM> of the substrate body <NUM> is reached. The polishing process polishes the substrate <NUM> from a total substrate thickness <NUM> to the predetermined thickness <NUM> with a selected removable thickness <NUM> configured to be removed from the substrate <NUM>. The polishing process may start from polishing from the first side <NUM> of the substrate <NUM> until between about <NUM> and about <NUM> of the thickness <NUM> of the unused portion <NUM> of the substrate <NUM> is removed. For example, the polishing process may be continuously performed until the selected removable thickness <NUM> of the substrate <NUM> is removed from the substrate <NUM>, forming an exposed surface <NUM> of the substrate <NUM>. After a desired amount of the substrate <NUM> is removed, the polishing process may be terminated and the substrate <NUM> may be removed from the polishing tool <NUM>.

<FIG> depicts the substrate <NUM> after the polishing process, forming the exposed surface <NUM> after the selected removable thickness <NUM> of the substrate <NUM> is removed from the substrate <NUM> so that the substrate <NUM> has a predetermined thickness <NUM>. In one example, the predetermined thickness <NUM> of the substrate <NUM> that substantially includes the device region <NUM> is between about <NUM> and about <NUM>.

Subsequently, a surface treatment or activation process may be performed to form an activation layer <NUM> on the exposed surface <NUM> of the substrate <NUM>. It is noted that the example depicted in <FIG> is rotated <NUM> degrees, as opposed to the example depicted in <FIG>, to have the exposed surface <NUM> facing up for ease of explanation.

In one example, the surface activation process may be a surface oxidation process, a thermal treatment process, a plasma treatment process, or other suitable process to activate and/or modify a surface property of the exposed surface <NUM> of the substrate <NUM>. In one example, the surface activation process is performed by supplying an oxygen containing gas or an oxygen containing agent to the exposed surface <NUM> of the substrate <NUM>. A thermal energy, a plasma energy, a laser energy or other types of energy may be applied when supplying the oxygen containing gas or the oxygen containing agent to the exposed surface <NUM> of the substrate <NUM>. The energy may dissociate the oxygen containing gas or an oxygen containing agent as supplied to incorporate oxygen elements into the exposed surface <NUM> of the substrate <NUM>, forming the activation layer <NUM> on the exposed surface <NUM> of the substrate <NUM>.

After the activation layer <NUM> is formed on the exposed surface <NUM> of the substrate <NUM>, a temperature control element <NUM> having a bonding layer <NUM> formed thereon, as shown in <FIG>, may be attached and/or bonded to the activation layer <NUM>, as shown in <FIG>. The temperature control element <NUM> is bonded to the substrate <NUM> by a thermal bonding process. The thermal bonding process allows the bonding layer <NUM> from the temperature control element <NUM> to be adhered onto the activation layer <NUM> formed on the substrate <NUM>. The bonding layer <NUM> and the activation layer <NUM> may be manufactured from similar materials, such as an oxygen containing material. Thus, after the bonding process, the bonding layer <NUM> and the activation layer <NUM> may become a unitary film in form of a single layer present at the interface between the substrate <NUM> and the temperature control element <NUM>, as shown in <FIG>. After the temperature control element <NUM> is attached to the substrate <NUM>, a mechanical structure <NUM> may be utilized to debond or remove the sacrificial carrier <NUM> from the substrate <NUM>, as shown in <FIG>. After the sacrificial carrier <NUM> is removed, along with the sacrificial glue layer <NUM> or using another manufacturing procedure, an IC die <NUM> having the temperature control element <NUM> disposed on the substrate <NUM> having the device region <NUM> formed therein is obtained, as shown in <FIG>. Thus, the resultant IC die <NUM> includes a first side having the temperature control element <NUM> formed therein while including a second side having the device region <NUM> configured to perform its electrical functions and purposes when in operation. In one example, the device region <NUM> of the IC die <NUM> is an ASIC having the temperature control element <NUM> formed in the IC die <NUM>.

In one example, the activation layer <NUM> may also serve as a barrier layer so that the heat dissipating material from the temperature control element <NUM> is not in direct contact or in electrical communication with the devices or transistors located in the device region <NUM> in the substrate <NUM>. Thus, the vias where the heat dissipating material is filled in the temperature control element <NUM> are not in contact with the devices or transistors located in the device region <NUM> in the substrate <NUM> so that the thermal energy dissipated therethrough would not be inadvertently reverted back to the devices or transistors located in the device region <NUM> in the substrate <NUM>.

<FIG> depicts different examples of temperature control elements <NUM>, <NUM>, <NUM>, <NUM> disposed on a substrate, such as the substrate <NUM>, having devices formed therein that may be utilized in an IC die, such as the IC die <NUM>, <NUM>, <NUM>. In the example depicted in <FIG>, the temperature control element <NUM> may include a plurality of vias <NUM>, such as through-substrate vias (TSV) formed in a base structure <NUM>. In one example, the base structure <NUM> may be a silicon substrate, similar to the material utilized to manufacture the substrate <NUM>. In the example depicted herein, the plurality of vias <NUM> is utilized for heat dissipation for three-dimensional vertical stacking in IC package structure. In one example, a heat dissipation material <NUM> is disposed in the vias <NUM>. Other materials (not shown), such as a liner, a diffusion barrier layer or other suitable layers, may be utilized in the vias <NUM> surrounding or adjacent to the heat dissipation material <NUM> to facilitate interface management between the vias <NUM> and the base structure <NUM> as well as preventing the heat dissipation material <NUM> disposed in the vias <NUM> to be in direct contact with the base structure <NUM>. In one example, the plurality of vias <NUM> is formed in and extended through the body of the base structure <NUM> by one or more etching processes. By adjusting process parameters of the one or more etching process, the depth of the vias <NUM> formed in the base structure <NUM> may be adjusted or varied. In the example depicted in <FIG>, the vias <NUM> are through vias, such as open vias, having a first end <NUM> exposed on a top surface <NUM> of the base structure <NUM> and a second end <NUM> exposed to a bottom surface <NUM> of the base structure <NUM>. The second end <NUM> of the vias <NUM> may be sealed by a bonding layer <NUM> disposed on the bottom surface <NUM> of the base structure <NUM>.

In one example, the vias <NUM> may have a width <NUM> (W) in a range from <NUM> to about <NUM>. In some embodiments, the vias <NUM> may have a depth <NUM> (D) in a range from <NUM> to about <NUM>. In some embodiments, the vias <NUM> may have an aspect ratio (D/W) in a range from <NUM> to about <NUM>.

In one example, the heat dissipation material <NUM> that may be utilized to be disposed in the vias <NUM> may be ceramic materials, semiconductor materials, graphite, diamond, or organic materials. Suitable examples of the ceramic materials include a high dielectric constant, such as high-k, material, such as HfO<NUM>, Si<NUM>N<NUM>, Al<NUM>O<NUM>, ZnO<NUM>, or the like. SiO<NUM> may also be used for the heat dissipation material <NUM>.

In the example depicted in <FIG>, the plurality of vias <NUM> formed in the base structure <NUM> are blind vias, where at least one end <NUM> of the vias <NUM> are embedded in the base structure <NUM> without openings formed on the top surface <NUM> of the base structure <NUM>. The depth <NUM> of the blind vias <NUM> formed in the base structure <NUM> may be varied based on different process requirements. For example, when the efficiency requirement of the heat dissipation is not required to be overly high, the depth of the blind vias <NUM> may be controlled at a relatively short range. This may save manufacturing cost, such as reducing the via etching time as well as heat dissipation material filling time and cost.

In the example depicted in <FIG>, the temperature control element <NUM> may include a plurality of vias <NUM> formed in a base structure <NUM>. A heat dissipation pad <NUM> may be formed substantially at a center portion of the base structure <NUM> close to the bonding layer <NUM>. The heat dissipation pad <NUM> may provide a relatively large heat dissipation area, as opposed to the vias <NUM>, to assist dissipating heat at certain local spot at a greater dissipation rate. For example, during operation, some areas with a relatively greater amount of transistors, gate structures or devices disposed therein often accumulate a greater amount of heat, as opposed to the areas where merely some metal interconnection pins or wires are formed. Thus, utilization of the heat dissipation pad <NUM> may assist dissipating the heat generated at certain local hot spots at a faster rate so as to efficiently carry away the heat from an IC die.

In another example depicted in <FIG>, an additional heat dissipation pad <NUM> may be formed on an upper portion of the temperature control element <NUM>, along with a bottom heat dissipation pad <NUM> disposed therein. Similarly, the one or more heat dissipation pads <NUM>, <NUM> may provide additional heat dissipating area to assist dissipating heat at certain local hot spots at a greater heat dissipating rate or efficiency.

<FIG> depicts additional examples of temperature control elements <NUM>, <NUM> formed in an IC die. The temperature control elements <NUM>, <NUM> may include a plurality of vias <NUM>, <NUM> with different pitch densities formed at different locations of the base structure <NUM>, <NUM>. In some examples, the plurality of vias <NUM>, <NUM> formed across the base structures <NUM>, <NUM> may have different pitch densities due to various reasons. For example, as the vias <NUM>, <NUM> formed in the base structure <NUM>, <NUM> are often configured to have high aspect ratios, reactive etchants supplied during the via etching process may not always be able to travel down or reach to the bottom of the vias <NUM>, <NUM> to form the vias <NUM>, <NUM> with the desired high aspect ratios. Thus, by arranging different pitch densities of the vias <NUM>, <NUM> at different locations across the base structure <NUM>, <NUM>, the reactive etchants may be distributed across the base structures <NUM>, <NUM> in a relatively more uniform way, or also to avoid micro-loading effect, so as to assist the reactive etchants to travel down through the vias <NUM>, <NUM> to form the vias <NUM>, <NUM> with the desired profiles and aspect ratios.

In the example depicted in <FIG>, a first group 750a, 750b of vias <NUM> located at an edge portion 770a, 770b of the base structure <NUM> may have a pinch density less than a pinch density of a second group <NUM> of the vias <NUM> located a center portion <NUM> of the base structure <NUM>. For example, a pitch <NUM> between the vias <NUM> located at the edge portions 770a, 770b may be longer than a pitch <NUM> between the vias <NUM> located at the center portion <NUM> of the base structure <NUM>. It is noted that when a pitch between the vias is relatively shorter, a higher pitch density is obtained. In contrast, when a pitch between the vias is relatively longer, a lower pitch density is obtained.

In the example depicted in <FIG>, in contrast, a first group 760a, 760b of vias <NUM> may have a pitch density greater than a pitch density of a second group <NUM> of the vias <NUM> located in the center portion <NUM> of the base structure <NUM>. For example, a pitch <NUM> between the first group 760a, 760b of the vias <NUM> is smaller than a pitch <NUM> between the second group <NUM> of the vias <NUM> located in the center potion <NUM> of the base structure <NUM>.

It is noted that the pitch density may be varied and distributed differently across different portions of the base structures based on heat dissipation efficiency and manufacturing cost and complexity considerations.

<FIG> depict top views of different examples of the temperature control elements <NUM>, <NUM> that have vias formed in different patterns. For example, in the example depicted in <FIG>, the vias <NUM> may be formed as vertical arrays having equal distance to each other in a base structure <NUM> without horizontal interception. In the example depicted in <FIG>, the vias <NUM> may be formed as both longitudinal vertical and horizontal bars across and orthogonal to each other. It is noted that the vias formed in the temperature control elements may be in any configurations to facilitate dissipating heat with a desired dissipation rate and efficiency.

<FIG> depicts a flow diagram for manufacturing an IC package, such as the IC package <NUM>, <NUM> depicted in <FIG> including an IC die <NUM>, <NUM> having the temperature control element <NUM>, <NUM> formed therein in accordance with aspects of the disclosure. Such method may be performed using suitable manufacturing processes, including depositing, etching, lithography, polishing, soldering, or any suitable techniques. It should be understood that the operations involved in the following methods need not be performed in the precise order described. Rather, various operations may be handled in a different order or simultaneously, and operations may be added or omitted.

Referring to <FIG>, in block <NUM>, a substrate is provided having device structures, transistors, or other electronic components formed on a device region of the substrate.

In block <NUM>, a polishing process is performed on a first side of the substrate opposite to a second side where the device region is formed in the substrate.

In block <NUM>, a thickness of the substrate is reduced during the polishing process until a desired amount of the thickness of the substrate is removed from the substrate, forming an exposed surface on the first side of the substrate.

In block <NUM>, a surface activation process may be performed to form an activation layer on the exposed surface of the substrate.

In block <NUM>, subsequently, a temperature control element is formed on the activation layer to form an IC die with the temperature control element disposed therein.

In block <NUM>, the IC die with the temperature control element disposed therein may be packed in an IC package under a heat distribution device.

The features described herein allow a temperature control element being formed as an integral part of an IC die that may have high heat dissipation efficiency during operation. The temperature control element may assist temperature control of the IC die when in operation. In one example, the IC die may have a substrate having a first side coupled to the temperature control element and a second side including a plurality of devices, such as semiconductors transistors, formed therein. The temperature control element includes a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation. Different patterns, features, and structures along with different selected materials for the heat dissipation material utilized in the temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.

Claim 1:
An integrated circuit, IC, die, comprising:
a substrate (<NUM>);
a temperature control element (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) formed on a first side of the substrate (<NUM>); and
a plurality of device structures formed on a second side of the substrate (<NUM>), wherein the temperature control element (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is formed as an integral part of the IC die (<NUM>),
wherein the temperature control element (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises a plurality of vias (<NUM>, <NUM>, <NUM>) formed in a base structure (<NUM>, <NUM>, <NUM>),
wherein the IC die (<NUM>) further comprises a heat dissipation material (<NUM>) disposed in the plurality of vias (<NUM>, <NUM>, <NUM>) in the base structure (<NUM>, <NUM>, <NUM>),
wherein the heat dissipation material (<NUM>) comprises at least one of ceramic materials, semiconductor materials, graphite, diamond, or organic materials.