Patent Description:
In semiconductor devices there is a continuous need for an increased degree of integration in order to increase capacity and reduce energy consumption.

To provide an increased degree of integration, three-dimensional semiconductor memory devices including transistors three-dimensionally arranged have been proposed. Technologies for decreasing a volume so as to increase the degree of integration of three-dimensional memory devices are being developed, and stability of memory devices is needed in proportion to an increase in degree of integration.

<CIT> discloses a nonvolatile memory device and method of performing an erase operation in the same in which an erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.

<CIT> discloses a flash memory device which includes a selection transistor for selecting a cell string; and a plurality of memory cells connected in series to the selection transistor, and the selection transistor is programmed such that a threshold voltage of the selection transistor is higher than a non-selection read voltage Vread, for protecting data stored in at least one of the plurality of memory cells. The flash memory according to an embodiment of the inventive concept adjusts the threshold value of the selection transistor or a dummy memory, thus protecting data permanently or temporarily within a short time and recovering original data easily without data loss if necessary.

<CIT> discloses a method for setting an initial threshold voltage of a charge-trap type NAND flash memory to set the initial threshold voltage at a predictable and controllable value, by programming the distribution of a random initial threshold voltage of a selection transistor. According to a method for setting an initial threshold voltage of a charge-trap type NAND flash memory device including a selection transistor and a cell transistor having a non-conductive charge storage layer, the cell transistor and the selection transistor are erased; the erased state of the cell transistor and the selection transistor is verified; the selection transistor is programmed to have predetermined threshold voltage characteristics; and the programmed state of the selection transistor is verified.

One or more example embodiments provide a non-volatile memory device, which is programmed using a ground selection line (coded-GSL) scheme, and an operating method of the non-volatile memory device.

According to an aspect of the present invention there is provided a non-volatile memory device and an operating method of a non-volatile memory device as claimed in the independent claims.

Optional features of the non-volatile memory device and the operating method of the non-volatile memory device are defined according to the dependent claims.

The above and other objects and features will be more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which:.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Each example embodiment provided in the following description is not excluded from being associated with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be also understood that, even if a certain step or operation of manufacturing an apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

<FIG> is a block diagram of a memory system <NUM> according to an example embodiment.

Referring to <FIG>, the memory system <NUM> may include a memory device <NUM> and a memory controller <NUM>, and the memory device <NUM> may include a transistor array <NUM> and a control logic (i.e., control circuitry) <NUM>. The memory device <NUM> may further include a voltage generator, which generates various voltages associated with programming/reading/erasing of data, and a page buffer and various other elements, which are connected with the transistor array <NUM> through bit lines. The transistor array <NUM> according to an example embodiment may be a memory cell array.

According to an example embodiment, the memory device <NUM> includes a non-volatile memory device. For example, the memory device <NUM> includes a non-volatile memory device, such as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RAM), phase-change memory, or magnetoresistive RAM. In some example embodiments, the memory device <NUM> or the memory system <NUM> may be implemented as an embedded memory embedded in an electronic device, or may be implemented as an external memory which is attachable or detachable on or from an electronic device. For example, the memory device <NUM> or the memory system <NUM> may be implemented as various types, such as a universal flash storage (UFS) memory device, an embedded multimedia card (eMMC), a solid state drive (SSD), a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro secure digital (micro-SD) card, a mini secure digital (mini-SD) card, an extreme digital (xD) card, and a memory stick.

In response to a write/read request from a host HOST, the memory controller <NUM> may read data stored in the memory device <NUM>, or may control the memory device <NUM> to write (or program) data in the memory device <NUM>. In detail, the memory controller <NUM> may provide an address ADD and a command CMD to the memory device <NUM>, and thus, may control a program operation, a read operation, and an erase operation on the memory device <NUM>. Also, data DATA to be written in the memory device <NUM> and data DATA read from the memory device <NUM> may be transferred and received between the memory controller <NUM> and the memory device <NUM>.

The transistor array <NUM> may include a plurality of cell blocks CB1 to CBN. When the memory device <NUM> corresponds to a vertical NAND flash memory device, each of the plurality of cell blocks CB1 to CBN may include a plurality of cell strings. For example, a plurality of cell strings may be connected with one bit line, and in performing a data program/read operation, one cell string selected from among a plurality of cell strings may be electrically connected with a bit line.

The plurality of cell blocks CB1 to CBN may store various kinds of data. For example, the plurality of cell blocks CB1 to CBN may include special cell blocks <NUM> which store various pieces of information other than user data and normal cell blocks <NUM> which store the user data. According to an example embodiment, the normal cell blocks <NUM> and the special cell blocks <NUM> may be implemented to have different structures, or may be driven based on different schemes. The special cell blocks <NUM> according to an example embodiment may store various pieces of information associated with security. However, the kind of data stored in the special cell blocks <NUM> may vary according to example embodiments.

According to an example embodiment, each of the plurality of cell blocks CB1 to CBN may include a ground selection line (GSL) region where a plurality of ground selection lines GSL are arranged. For example, when a first cell block CB1 corresponds to the special cell block <NUM> and an Nth cell block CBN corresponds to the normal cell block <NUM>, each of the first cell block CB1 and the Nth cell block CBN may include a GSL region. As described above, the GSL region of the first cell block CB1 and the GSL region of the Nth cell block CBN may physically have different structures. Alternatively, the GSL region of the first cell block CB1 and the GSL region of the Nth cell block CBN may be differently managed, and for example, management may be differently performed on a plurality of ground selection transistors (for example, GST of <FIG>) connected with ground selection lines disposed in the GSL region of the first cell block CB1 and a plurality of ground selection transistors GST connected with ground selection lines disposed in the GSL region of the Nth cell block CBN. For example, a plurality of ground selection transistors GST included in each of the plurality of cell blocks CB1 to CBN may be programmed to have certain threshold voltages in a process of manufacturing the memory device <NUM>, and threshold voltages of the ground selection transistors GST disposed in the GSL region of the first cell block CB1 and threshold voltages of the ground selection transistors GST disposed in the GSL region of the Nth cell block CBN may be differently programmed.

Furthermore, according to an example embodiment, the control logic <NUM> may include GSL control information <NUM>. For example, the control logic <NUM> may include a fuse circuit, an anti-fuse circuit, and a certain storage circuit which is non-volatile and stores information. The control logic <NUM> may control a program operation on the plurality of ground selection transistors GST of the plurality of cell blocks CB1 to CBN, based on the GSL control information <NUM>. In an example embodiment, the GSL control information <NUM> may be stored in the storage circuit of the control logic <NUM> in a process of manufacturing the memory device <NUM>, or the GSL control information <NUM> may be provided to the control logic <NUM> in an initial driving process of the memory device <NUM>.

<FIG> is a circuit diagram illustrating a memory block BLKi included in a memory device <NUM> according to an example embodiment. The memory device <NUM> of <FIG> according to one embodiment may include at least one memory block BLKi.

Referring to <FIG>, the memory block BLKi may include a plurality of cell strings CS11 to CS41 and CS12 to CS42. The plurality of cell strings CS11 to CS41 and CS12 to CS42 may be arranged in a row direction and a column direction to configure rows and columns.

Each of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may include a ground selection transistor GST, memory cells MC1 to MC6, and a string selection transistor SST. The ground selection transistor GST, the memory cells MC1 to MC6, and the string selection transistor SST of each cell string may be stacked in a height direction perpendicular to an upper surface of a substrate.

The rows of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be respectively connected with different string selection lines. For example, the string selection transistors SST of the cell strings CS11 and CS12 may be connected with the string selection line SSL1 in common. The string selection transistors SST of the cell strings CS21 and CS22 may be connected with the string selection line SSL2 in common. The string selection transistors SST of the cell strings CS31 and CS32 may be connected with the string selection line SSL3 in common. The string selection transistors SST of the cell strings CS41 and CS42 may be connected with the string selection line SSL4 in common.

The columns of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be respectively connected with different bit lines BL1 and BL2. For example, the string selection transistors SST of the cell strings CS11 to CS41 may be connected with the bit line BL1 in common. The string selection transistors SST of the cell strings CS12 to CS42 may be connected with the bit line BL2 in common.

The rows of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be respectively connected with different ground selection lines GSL1 to GSL4. For example, the ground selection transistors GST of the cell strings CS11 and CS12 may be connected with the ground selection line GSL1 in common. The ground selection transistors GST of the cell strings CS21 and CS22 may be connected with the ground selection line GSL2 in common. The ground selection transistors GST of the cell strings CS31 and CS32 may be connected with the ground selection line GSL3 in common. The ground selection transistors GST of the cell strings CS41 and CS42 may be connected with the ground selection line GSL4 in common.

Memory cells disposed at the same height from the substrate (or ground selection transistors GST) may be connected with one word line in common, and memory cells disposed at different heights may be respectively connected with different word lines WL1 to WL6. For example, the memory cells MC1 may be connected with the word line WL1 in common. The memory cells MC2 may be connected with the word line WL2 in common. The memory cells MC3 may be connected with the word line WL3 in common. The memory cells MC4 may be connected with the word line WL4 in common. The memory cells MC5 may be connected with the word line WL5 in common. The memory cells MC6 may be connected with the word line WL6 in common.

The ground selection transistors GST of the cell strings CS11 to CS41 and CS12 to CS42 may be connected with a common source line CSL in common.

The memory block BLKi illustrated in <FIG> is an example. Example embodiments are not limited to the memory block BLKi illustrated in <FIG>. For example, the number of rows of cell strings may increase or decrease. As the number of rows of cell strings is changed, the number of string selection lines connected with the rows of the cell strings and the number of cell strings connected with one bit line may be changed also. As the number of rows of cell strings is changed, the number of ground selection lines connected with the rows of the cell strings may be changed also.

The number of columns of cell strings may increase or decrease. As the number of columns of cell strings is changed, the number of bit lines connected with the columns of the cell strings and the number of cell strings connected with one string selection line may be changed also.

Heights of cell strings may increase or decrease. For example, the number of memory cells stacked on each of cell strings may increase or decrease. As the number of memory cells stacked on each cell string is changed, the number of word lines may be changed also. For example, the number of string selection transistors or ground selection transistors provided in each of cell strings may increase. As the number of string selection transistors or ground selection transistors provided in each of cell strings increases, the number of string selection lines or ground selection lines may be changed also. When the number of string selection transistors or ground selection transistors increases, the string selection transistors or the ground selection transistors may be stacked like the memory cells MC1 to MC6.

For example, a write operation and a read operation may be performed by row units of the cell strings CS11 to CS41 and CS12 to CS42. The cell strings CS11 to CS41 and CS12 to CS42 may be selected by one row units (e.g. on a row-by-row basis) by using the ground selection lines GSL1 to GSL4, and the cell strings CS11 to CS41 and CS12 to CS42 may be selected by one row units (e.g. on a row-by-row basis) by using the string selection lines SSL1 to SSL4. Also, a voltage may be applied to at least two ground selection lines GSL1 and GSL2 or GSL3 and GSL4 of the ground selection lines GSL1 to GSL4 by one unit (e.g. a voltage may be applied to at least two selected ground selection lines). A voltage may be applied to all of the ground selection lines GSL1 to GSL4 by one unit (e.g. a voltage may be applied to all of the ground selection lines). The ground selection lines GSL1 to GSL4 according to an example embodiment may be programmed to have a predetermined threshold voltage.

A write operation and a read operation may be performed, by page units, on a selected row of the cell strings CS11 to CS41 and CS12 to CS42. A page may be one row of memory cells connected with one word line. Memory cells may be selected in a selected row of the cell strings CS11 to CS41 and CS12 to CS42 by page units (e.g. on a page row by page row basis) by using the word lines WL1 to WL6.

<FIG> is a circuit diagram for describing a configuration of a memory block included in a memory device <NUM> according to an example embodiment. Hereinafter, a first cell memory block CB1 of memory blocks according to an example embodiment is described. However, cell blocks included in the memory device <NUM> are not limited thereto, and the memory device <NUM> may further include a plurality of cell blocks. Also, the memory device <NUM> according to an example embodiment may be a three-dimensional (3D) memory device.

Referring to <FIG>, a first cell block CB1 according to an example embodiment may include a plurality of cell string regions CS01, CS11, and CS21, and the cell string regions CS01, CS11, and CS21 may be respectively connected with string selection lines SSL0, SSL1, and SSL2. For example, the first cell block CB1 may include a first cell string region CS01, a second cell string region CS11, and a third cell string region CS21. However, the number of cell string regions is not limited thereto, and the first cell block CB1 may further include other numbers of cell string regions. Also, the first cell string region CS01 may be connected with a first string selection line SSL0, the second cell string region CS11 may be connected with a second string selection line SSL1, and the third cell string region CS21 may be connected with a third string selection line SSL2.

The cell string regions CS01, CS11, and CS21 according to an example embodiment may include a plurality of transistors TR01 to TR29. For example, the cell string regions CS01, CS11, and CS21 according to an example embodiment may be configured with the plurality of transistors TR01 to TR29. The first cell string region CS01, the second cell string region CS11, and the third cell string region CS21 according to an example embodiment may be connected with one another through a word line. For example, transistors of the first cell string region CS01, the second cell string region CS11, and the third cell string region CS21 may be respectively connected with different string selection lines.

A ground selection line GSL according to an example embodiment may activate transistors included in an arbitrary cell string region. For example, when an arbitrary cell string selection line SSL activates an arbitrary cell string, transistors of a region connected with a corresponding ground selection line GSL may be activated.

Some of word lines according to an example embodiment may be configured with programmed ground selection lines Coded-GSLO, Coded-GSL1, Coded-GSL2, Coded-GSL3, and Coded-GSL4 where a ground selection function is programmed. For example, the programmed ground selection lines Coded-GSLO, Coded-GSL1, Coded-GSL2, Coded-GSL3, and Coded-GSL4 may be programmed to have different threshold voltages and may control whether to activate the transistors of each cell string.

A ground dummy line G. DMY according to an example embodiment may be between the programmed ground selection lines Coded-GSL0, Coded-GSL1, Coded-GSL2, Coded-GSL3, and Coded-GSL4 and an adjacent word line WL0. Also, a dummy line DUMO according to an example embodiment may be between the programmed ground selection lines Coded-GSL0, Coded-GSL1, Coded-GSL2, Coded-GSL3, and Coded-GSL4 and the ground selection line GSL. Because the ground dummy line G. DMY and the dummy line DUMO are provided, the memory device <NUM> according to an example embodiment may perform stable ground selection line programming.

<FIG> is a block diagram of a memory device <NUM> according to an example embodiment.

Referring to <FIG>, the memory device <NUM> according to an example embodiment may include a programmed first ground selection line 111a and a programmed second ground selection line 111b and a control logic <NUM>.

According to an example embodiment, the programmed first ground selection line 111a and the programmed second ground selection line 111b may use some of word lines of a memory block. Each of transistors connected with the programmed first ground selection line 111a may be programmed to have a first threshold voltage. According to an example embodiment, each of transistors connected with the programmed second ground selection line 111b may be programmed to have a second threshold voltage. The second threshold voltage according to an example embodiment may be set to be different from the first threshold voltage. For example, the second threshold voltage may be set to have a value which is greater than that of the first threshold voltage.

The transistors connected with the programmed first ground selection line 111a according to an example embodiment may be referred to as first ground selection transistors, and the transistors connected with the programmed second ground selection line 111b may be referred to as second ground selection transistors.

The control logic <NUM> according to an example embodiment may perform an erase operation ERS and a rewrite operation Re-Write on each transistor. For example, the control logic <NUM> may determine whether a threshold voltage of at least one first ground selection transistor connected with the programmed first ground selection line 111a is greater than a predetermined first criterion. When the threshold voltage of the at least one first ground selection transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion, the control logic <NUM> according to an example embodiment may determine that programming of the first threshold voltage fails. The first criterion according to an example embodiment may be a criterion for determining whether the first threshold voltage is normally set. For example, the first criterion may be an upper limit of the first threshold voltage which is preprogrammed.

When the threshold voltage of the at least one first ground selection transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion, the control logic <NUM> according to an example embodiment may determine that programming of the first threshold voltage has failed and performs the erase operation ERS on the first ground selection transistors having the threshold voltage which is greater than the first criterion. Before performing the erase operation ERS, by comparing the predetermined first criterion with the threshold voltage of each of the ground selection transistors connected with the programmed first ground selection line 111a, the memory device <NUM> performs a stable erase operation ERS. Also, the memory device <NUM> performs the erase operation ERS on transistors having a threshold voltage which is greater than the first criterion and may thus perform a stable rewrite operation later.

When an erase operation on the ground selection transistors connected with the programmed first ground selection line 111a is completed, the control logic <NUM> according to an example embodiment compares a predetermined second criterion with threshold voltages of a plurality of second ground selection transistors connected with the programmed second ground selection line 111b. The second criterion according to an example embodiment may be a lower limit of the second threshold voltage. When it is determined that a threshold voltage of each of second ground selection transistors connected with the programmed second ground selection line 111b is less than the second criterion, the control logic <NUM> according to an example embodiment may determine that programming of the second threshold voltage on the programmed second ground selection line 111b fails.

When an erase operation on a transistor connected with the programmed first ground selection line 111a is completed, the control logic <NUM> according to an example embodiment may perform a rewrite operation on first ground selection transistors having a threshold voltage which is less than the first criterion. For example, the control logic <NUM> may perform a rewrite operation on transistors where programming of the first threshold voltage has succeeded. When the threshold voltage of the at least one first ground selection transistor connected with the programmed first ground selection line 111a is less than the predetermined first criterion, the control logic <NUM> according to an example embodiment may perform the erase operation ERS on the first ground selection transistors.

The control logic <NUM> according to an example embodiment may perform the erase operation ERS on transistors where programming of the first threshold voltage has failed. For example, when a voltage region of the at least one first ground selection transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion, the control logic <NUM> may perform the erase operation ERS on the first ground selection transistors. When there are first ground selection transistors where programming of the first threshold voltage has failed, the control logic <NUM> according to an example embodiment may perform the erase operation ERS on all of the first ground selection transistors where programming of the first threshold voltage has succeeded and the first ground selection transistors where programming of the first threshold voltage has failed. By performing the erase operation ERS on all of the first ground selection transistors where programming of the first threshold voltage has succeeded and the first ground selection transistors where programming of the first threshold voltage has failed, the control logic <NUM> according to an example embodiment may perform a stable rewrite operation and may maintain the robustness of the ground selection line.

When an erase operation on the first ground selection transistors is completed, the control logic <NUM> according to an example embodiment may determine whether programming of a threshold voltage of each of a plurality of second ground selection transistors connected with the programmed second ground selection line 111b has succeeded and may perform the erase operation ERS.

For example, the control logic <NUM> may perform the erase operation ERS on second ground selection transistors where programming of the second threshold voltage has failed. When an erase operation on the second ground selection transistors is completed, the control logic <NUM> according to an example embodiment may determine a rewrite operation on the second ground selection transistors. When it is determined that programming of a threshold voltage of at least one transistor of the plurality of second ground selection transistors connected with the programmed second ground selection line 111b has failed, the control logic <NUM> according to an example embodiment may perform a rewrite operation on all transistors connected with the programmed second ground selection line 111b and may thus perform a stable rewrite operation.

When a plurality of transistors of the second ground selection transistors connected with the programmed second ground selection line 111b include a voltage region which is greater than the first criterion (e.g. when the plurality of transistors include a voltage region which includes a voltage which is greater than the first criterion), the control logic <NUM> according to an example embodiment may perform a first rewrite operation on the second ground selection transistors connected with the programmed second ground selection line 111b, and when the first rewrite operation is completed, a second rewrite operation may be performed on the first ground selection transistors connected with the programmed first ground selection line 111a. The first rewrite operation according to an example embodiment may be an operation of re-setting threshold voltages of the second ground selection transistors, and the second rewrite operation may be an operation of re-setting threshold voltages of the first ground selection transistors.

For example, when programming of the first threshold voltage and programming of the second threshold voltage have all failed, the amount of shift of the second threshold voltage may be greater than the amount of shift of the first threshold voltage in performing a rewrite operation. The control logic <NUM> according to an example embodiment may first perform a rewrite operation on the second threshold voltage where the amount of shift is relatively high and may perform a rewrite operation on the first threshold voltage after the rewrite operation on the second threshold voltage is completed, and thus, may perform a stable rewrite operation.

A rewrite operation according to an example embodiment may be performed based on a predetermined criterion. For example, the control logic <NUM> may previously program an order of rewrite operations, and where programming of threshold voltages has failed for a plurality of transistors, the control logic <NUM> may perform a first rewrite operation and may then perform a second rewrite operation when the first rewrite operation is completed.

<FIG> is a flowchart of an operating method of a memory device <NUM>, according to an example embodiment.

Referring to <FIG> and <FIG>, the memory device <NUM> according to an example embodiment may be programmed so that a plurality of first ground selection transistors have the first threshold voltage, in operation S510. For example, each of a plurality of first ground selection transistors connected with the programmed first ground selection line 111a may be programmed to have the first threshold voltage.

When the plurality of first ground selection transistors are programmed to have the first threshold voltage, each of a plurality of second ground selection transistors connected with the programmed second ground selection line 111b may be programmed to have the second threshold voltage, in operation S520.

The programmed second ground selection line 111b according to an example embodiment may include at least one of word lines of a word line block and may be configured to have the second threshold voltage. For example, each of transistors provided in the programmed second ground selection line 111b may be programmed to have the second threshold voltage. The second threshold voltage according to an example embodiment may be set to be different from the first threshold voltage. For example, the second threshold voltage may be set to have a value which is greater than that of the first threshold voltage. The first threshold voltage according to an example embodiment may be a threshold voltage having a lower state, and the second threshold voltage may be a threshold voltage having an upper state. For example, the first threshold voltage may have an average of -<NUM> V, and the second threshold voltage may have an average of +<NUM> V.

When the plurality of first ground selection transistors connected with the programmed first ground selection line 111a are programmed to have the first threshold voltage and a threshold voltage of at least one first ground selection transistor is greater than the predetermined first criterion, an erase operation on the at least one first ground selection transistor is performed by the memory device <NUM> in operation S530.

For example, the memory device <NUM> may determine whether a voltage region of at least one transistor connected with the programmed first ground selection line 111a is greater than the predetermined criterion (e.g. the memory device <NUM> may determine whether the voltage region includes a voltage which is greater than the predetermined criterion). When it is determined that a voltage region of at least one transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion (e.g. when it is determined that the voltage region includes a voltage which is greater than the predetermined first criterion), the memory device <NUM> according to an example embodiment may determine that programming of the first threshold voltage has failed. The first criterion according to an example embodiment may be a criterion for determining whether the first threshold voltage is normally set. For example, the first criterion may be an upper limit of the first threshold voltage which is preprogrammed. When it is determined that a voltage region of at least one transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion (e.g. when it is determined that a voltage region of at least one transistor connected with the programmed first ground selection line 111a includes a voltage which is greater than the predetermined first criterion), the memory device <NUM> according to an example embodiment may determine that programming of the first threshold voltage has failed and may perform an erase operation ERS on the first ground selection transistors having the threshold voltage which is greater than the first criterion.

When an erase operation is performed on at least one first ground selection transistor, the memory device <NUM> compares a predetermined second criterion with threshold voltages of a plurality of second ground selection transistors in operation S540.

Referring to <FIG> and <FIG>, when an erase operation on a transistor connected with the programmed first ground selection line 111a is completed, the memory device <NUM> according to an example embodiment may determine whether programming of a threshold voltage of each of transistors connected with the programmed second ground selection line 111b has succeeded and may perform the erase operation ERS. The second criterion according to an example embodiment may be a lower limit of the second threshold voltage. When it is determined that a voltage region of each of transistors connected with the programmed second ground selection line 111b is less than the second criterion (e.g. when it is determined that a voltage region of each of transistors connected with the programmed second ground selection line 111b includes a voltage which is less than the second criterion), the memory device <NUM> according to an example embodiment may determine that programming of the second threshold voltage on the programmed second ground selection line 111b has failed.

When a threshold voltage of each of transistors connected with the programmed second ground selection line 111b is compared with the predetermined second criterion, the memory device <NUM> according to an example embodiment may perform a control operation which includes performing a rewrite operation on transistors.

For example, the memory device <NUM> may perform a rewrite operation on transistors where programming of the first threshold voltage has succeeded. In this case, when a voltage region of at least one transistor connected with the programmed first ground selection line 111a is less than the predetermined first criterion (e.g. when a voltage region of at least one transistor connected with the programmed first ground selection line 111a includes a voltage which is less than the predetermined first criterion), the memory device <NUM> according to an example embodiment may perform an erase operation ERS on the transistors connected with the programmed first ground selection line 111a and may perform a rewrite operation.

The memory device <NUM> according to an example embodiment may perform an erase operation ERS on transistors where programming of the first threshold voltage has failed. For example, when the voltage region of the at least one transistor connected with the programmed first ground selection line 111a is greater than the predetermined first criterion (e.g. when the voltage region of the at least one transistor connected with the programmed first ground selection line 111a includes a voltage which is greater than the predetermined first criterion), the memory device <NUM> may perform an erase operation ERS on all transistors connected with the programmed first ground selection line 111a. When there are transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on all of the transistors where programming of the first threshold voltage has succeeded and transistors where programming of the first threshold voltage has failed. By performing the erase operation ERS on all of the transistors where programming of the first threshold voltage has succeeded and the transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform a stable rewrite operation and may maintain the robustness of a ground selection line.

The memory device <NUM> according to an example embodiment may perform a rewrite operation on transistors connected with the programmed second ground selection line 111b. When it is determined that programming of a threshold voltage of at least one transistor of transistors connected with the programmed second ground selection line 111b has failed, the memory device <NUM> according to an example embodiment may perform a rewrite operation on all transistors connected with the programmed second ground selection line 111b and may thus perform a stable rewrite operation.

<FIG> is a flowchart of a process of performing an erase operation on ground selection lines in an operating method of a memory device <NUM>, according to an example embodiment.

Referring to <FIG>, the memory device <NUM> according to an example embodiment may determine a voltage level of each of first ground selection transistors in operation S610.

For example, the memory device <NUM> may determine a threshold voltage distribution of each of transistors connected with the programmed first ground selection line 111a. The memory device <NUM> according to an example embodiment may calculate an average value of the threshold voltage distribution of each transistor and may determine the calculated average value as a voltage level of a corresponding transistor.

When a voltage level of each of the first ground selection transistors is determined, the memory device <NUM> according to an example embodiment may determine whether a threshold voltage of at least one first ground selection transistor is greater than the predetermined first criterion in operation S620.

The first criterion according to an example embodiment may be a criterion for determining whether the first threshold voltage is normally set. For example, the first criterion may be an upper limit of the first threshold voltage which is preprogrammed. When it is determined that a voltage region of at least one transistor connected with the programmed first ground selection line 111a has a threshold voltage that is greater than the predetermined first criterion, the memory device <NUM> according to an example embodiment may determine that programming of the first threshold voltage has failed.

When it is determined that there is a voltage region where the threshold voltage of the first ground selection transistor is greater than the predetermined first criterion, the memory device <NUM> performs an erase operation on first ground selection transistors having a threshold voltage which is greater than the predetermined first criterion in operation S630.

However, when it is determined that there is no voltage region where the threshold voltage of the first ground selection transistor is greater than the predetermined first criterion, the memory device <NUM> according to an example embodiment may perform an erase operation on first ground selection transistors connected with a first ground selection line in operation S640.

"A threshold voltage of at least one first ground selection transistor" can be a reference for whether to perform an erase operation on selected transistors or on all transistors.

When there are transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on transistors selected from among transistors where programming of the first threshold voltage has succeeded and transistors where programming of the first threshold voltage has failed.

However, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on all transistors connected with the programmed first ground selection line 111a. By performing the erase operation ERS on all of the transistors where programming of the first threshold voltage has succeeded and the transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform a stable rewrite operation and may maintain the robustness of a ground selection line.

When an erase operation ERS is performed on first ground selection transistors, the memory device <NUM> compares the predetermined second criterion with threshold voltages of a plurality of second ground selection transistors in operation S650.

The second criterion according to an example embodiment may be a lower limit of the second threshold voltage. When it is determined that there is a voltage region of each of transistors connected with the programmed second ground selection line 111b which is less than the second criterion (e.g. when it is determined that there is a voltage region of each of transistors connected with the programmed second ground selection line 111b which includes a voltage which is less than the second criterion), the memory device <NUM> according to an example embodiment may determine that programming of the second threshold voltage on the programmed second ground selection line 111b has failed.

When the predetermined second criterion is compared with threshold voltages of a plurality of second ground selection transistors, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on first and second ground selection transistors in operation S660.

For example, the memory device <NUM> may perform a rewrite operation on transistors where programming of the first threshold voltage has succeeded. In this case, when a voltage region of at least one transistor connected with the programmed first ground selection line 111a is less than the predetermined first criterion, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on the transistors connected with the programmed first ground selection line 111a and may perform a rewrite operation. The memory device <NUM> according to an example embodiment may perform a rewrite operation on transistors connected with the programmed second ground selection line 111b. When it is determined that programming of a threshold voltage of at least one transistor of transistors connected with the programmed second ground selection line 111b has failed, the memory device <NUM> according to an example embodiment may perform a rewrite operation on all transistors connected with the programmed second ground selection line 111b and may thus perform a stable rewrite operation.

<FIG> and <FIG> are flowcharts of a process of performing a rewrite operation in an operating method of a memory device, according to an example embodiment. <FIG> is a flowchart of a process of performing a rewrite operation when there are a plurality of transistors where programming of a threshold voltage according to an example embodiment has failed. <FIG> is a flowchart of a case where a rewrite operation is performed based on whether the rewrite operation satisfies a predetermined rewrite criterion, according to an example embodiment.

Referring to <FIG>, the memory device <NUM> according to an example embodiment may perform a rewrite operation in operation S710. For example, the memory device <NUM> may determine whether programming of the first threshold voltage and programming of the second threshold voltage have succeeded and may perform a rewrite operation, based on a result of the determination.

When a rewrite operation starts, the memory device <NUM> according to an example embodiment may determine whether there are a plurality of transistors, having a voltage region which is greater than the first criterion (e.g. having a voltage region which includes a voltage which is greater than the first criterion), of at least one first ground selection transistors in operation S720.

When it is determined that there are the plurality of transistors, having a voltage region which is greater than the first criterion (e.g. having a voltage region which includes a voltage which is greater than the first criterion), of the at least one first ground selection transistors, the memory device <NUM> according to an example embodiment may perform a first rewrite operation on a plurality of second ground selection transistors in operation S730.

The first rewrite operation according to an example embodiment may be an operation of re-setting a threshold voltage of each of transistors connected with the programmed second ground selection line 111b.

When a voltage region of at least one transistor of transistors connected with the programmed first ground selection line 111a is greater than the first criterion (e.g. when a voltage region of at least one transistor of transistors connected with the programmed first ground selection line 111a includes a voltage which is greater than the first criterion), the memory device <NUM> according to an example embodiment may determine that programming of the first threshold voltage has failed and may perform a rewrite operation on the transistors connected with the programmed second ground selection line 111b. For example, when programming of the first threshold voltage and programming of the second threshold voltage have all failed, the amount of shift of the second threshold voltage may be greater than the amount of shift of the first threshold voltage in performing a rewrite operation. The memory device <NUM> according to an example embodiment may first perform a rewrite operation on the second threshold voltage where the amount of shift is relatively high.

However, when it is determined that there are no transistors, which have a voltage region which is greater than the first criterion (e.g. which have a voltage region which includes a voltage which is greater than the first criterion), of the at least one first ground selection transistors, the memory device <NUM> according to an example embodiment may perform an erase operation ERS on the first ground selection transistors in operation S740.

The memory device <NUM> according to an example embodiment may perform the erase operation ERS on all transistors connected with the programmed first ground selection line 111a. By performing the erase operation ERS on all of the transistors where programming of the first threshold voltage has succeeded and the transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform a stable rewrite operation and may maintain the robustness of a ground selection line.

When the erase operation ERS is performed on the first ground selection transistors, the memory device <NUM> according to an example embodiment may perform a second rewrite operation on the first ground selection transistors in operation S750.

The second rewrite operation may be an operation of re-setting a threshold voltage of each of the transistors connected with the programmed first ground selection line 111a. The amount of shift of a threshold voltage based on the first rewrite operation according to an example embodiment may be greater than the amount of shift of a threshold voltage based on the second rewrite operation.

The memory device <NUM> according to an example embodiment may perform a rewrite operation on the first threshold voltage where a rewrite operation on the second threshold voltage is completed and may thus perform a stable rewrite operation.

Referring to <FIG>, the memory device <NUM> according to an example embodiment may perform a rewrite operation in operation S810. For example, the memory device <NUM> may determine whether programming of the first threshold voltage and programming of the second threshold voltage have succeeded and may perform a rewrite operation, based on a result of the determination.

When a rewrite operation starts, the memory device <NUM> according to an example embodiment may determine whether the rewrite operation satisfies a predetermined rewrite criterion in operation S820. The rewrite criterion according to an example embodiment may depend on whether an operation of performing a rewrite operation results in transistors which have a shift of a threshold voltage which is high.

When it is determined that the rewrite operation satisfies the predetermined rewrite criterion, the memory device <NUM> according to an example embodiment may perform a first rewrite operation on a plurality of second ground selection transistors in operation S830.

The memory device <NUM> according to an example embodiment may perform the first rewrite operation on the transistors connected with the programmed second ground selection line 111b in operation S830. The first rewrite operation according to an example embodiment may be an operation of re-setting a threshold voltage of each of the transistors connected with the programmed second ground selection line 111b.

However, when it is determined that the rewrite operation is not performed based on the predetermined rewrite criterion, the memory device <NUM> according to an example embodiment may perform the erase operation ERS on the first ground selection transistors in operation S840. The memory device <NUM> according to an example embodiment may perform an erase operation ERS on all transistors connected with the programmed first ground selection line 111a. By performing the erase operation ERS on all of the transistors where programming of the first threshold voltage has succeeded and the transistors where programming of the first threshold voltage has failed, the memory device <NUM> according to an example embodiment may perform a stable rewrite operation and may maintain the robustness of a ground selection line.

When the erase operation ERS is performed on the first ground selection transistors, the memory device <NUM> according to an example embodiment may perform a second rewrite operation on the first ground selection transistors in operation S850.

The second rewrite operation may be an operation of re-setting the threshold voltage of each of the transistors connected with the programmed first ground selection line 111a.

<FIG> is a diagram for describing an example embodiment of a case where a ground selection line of a memory device <NUM> according to an example embodiment is programmed.

Referring to <FIG>, a word line of the memory device <NUM> according to an example embodiment may be programmed as a ground selection line.

For example, in a case where the memory device <NUM> is programmed by a first program Coded-GSL#<NUM>, a first word line WL0 may be a ground selection dummy line GMDY, and a second word line WL1 may be programmed as a ground selection line Coded-GSL. Also, a third word line WL2 may be the ground selection dummy line GMDY, and a fourth word line WL3 may be programmed as the ground selection line Coded-GSL. Also, a fifth word line WL4 may be the ground selection dummy line GMDY, and a sixth word line WL5 may be a main word line. The memory device <NUM> according to an example embodiment may include dummy lines DUMO and DUM1.

In a case where the memory device <NUM> according to an example embodiment is programmed by a second program Coded-GSL#<NUM>, the first word line WL0 may be programmed as the ground selection line Coded-GSL. The second word line WL1 may be programmed as the ground selection dummy line GMDY. Also, the third word line WL2 may be the ground selection line Coded-GSL, and the fourth word line WL3 may be programmed as the ground selection line Coded-GSL. Also, the fifth word line WL4 may be the ground selection dummy line GMDY, and the sixth word line WL5 may be the main word line. In the memory device <NUM> according to an example embodiment, the first dummy line DUMO of the dummy lines may be programmed as a dummy region, and the second dummy line DUM1 may be programmed as the ground selection line Coded-GSL.

In a case where the memory device <NUM> according to an example embodiment is programmed by a third program Coded-GSL#<NUM>, the first word line WL0 may be programmed as the ground selection line Coded-GSL. The second word line WL1 may be programmed as the ground selection dummy line GMDY. Also, the third word line WL2 may be the ground selection line Coded-GSL, and the fourth word line WL3 may be programmed as the ground selection dummy line GMDY. Also, the fifth word line WL4 may be the ground selection dummy line GMDY, and the sixth word line WL5 may be programmed as a main word line. In the memory device <NUM> according to an example embodiment, the first dummy line DUMO of the dummy lines may be programmed as a dummy region, and the second dummy line DUM1 may be programmed as the ground selection dummy line GMDY.

In a case where the memory device <NUM> according to an example embodiment is programmed by a fourth program Coded-GSL#<NUM>, the first word line WL0 may be programmed as the ground selection dummy line GMDY. The second word line WL1 may be programmed as the ground selection line Coded-GSL. Also, the third word line WL2 may be the ground selection dummy line GMDY, and the fourth word line WL3 may be programmed as the ground selection line Coded-GSL. Also, the fifth word line WL4 may be the ground selection dummy line GMDY, and the sixth word line WL5 may be programmed as a main word line. In the memory device <NUM> according to an example embodiment, the first dummy line DUMO of the dummy lines may be programmed as a dummy region, and the second dummy line DUM1 may be programmed as the ground selection line Coded-GSL.

A method of programming ground selection lines in the memory device <NUM> is not limited to the method illustrated in <FIG> and may include a plurality of programming methods.

<FIG> and <FIG> are diagrams for describing an example where a rewrite operation is performed on a first ground selection line, in a memory device <NUM> according to an example embodiment. Hereinafter, the terms "first", "second", and "third" used in <FIG> may be for simply differentiating between string selection lines and ground selection lines.

Referring to <FIG>, a word line block of a cell region selected by string selection lines (for example, first to third string selection lines) SSL0, SSL1, and SSL2 according to an example embodiment may include a plurality of programmed ground selection lines (for example, programmed first to third ground selection lines) Coded-GSL1, Coded-GSL2, and Coded-GSL3.

In a case where a voltage region of a transistor of a programmed first ground selection line Coded-GSL1 of the first string selection line SSL0 according to an example embodiment is greater than a first criterion UCL1 (e.g. where a voltage region of a transistor of a programmed first ground selection line Coded-GSL1 of the first string selection line SSL0 according to an example embodiment includes a voltage which is greater than a first criterion UCL1), the memory device <NUM> according to an example embodiment may perform a first rewrite operation (<NUM>st Re-write) on the transistor of the programmed first ground selection line Coded-GSL1. For example, the memory device <NUM> may determine that first threshold voltage programming of a transistor of the programmed first ground selection line Coded-GSL1 has failed and may perform the first rewrite operation (<NUM>st Re-write) on the transistor of a programmed first ground selection line Coded-GSL1 of the third string selection line SSL2.

In a case where a rewrite operation is performed on the transistor of the programmed first ground selection line Coded-GSL1, the memory device <NUM> according to an example embodiment may perform the first rewrite operation (<NUM>st Re-write) on a transistor of the programmed second ground selection line Coded-GSL2. In a case where the first rewrite operation (<NUM>st Re-write) is performed on the transistor of the programmed first ground selection line Coded-GSL1, the memory device <NUM> according to an example embodiment may perform the first rewrite operation (<NUM>st Re-write) on the transistor of the programmed second ground selection line Coded-GSL2 and may thus remove an adverse effect, caused by a variation of a threshold voltage, on an adjacent ground selection line.

Referring to <FIG>, when it is determined that first threshold voltage programming of a programmed second ground selection line Coded-GSL2 of the third string selection line SSL2 of the memory device <NUM> according to an example embodiment has failed, the memory device <NUM> may perform the first rewrite operation (<NUM>st Re-write) on the programmed second ground selection line Coded-GSL2, the programmed first ground selection line Coded-GSL1 adjacent to the programmed second ground selection line Coded-GSL2, and the programmed third ground selection line Coded-GSL3.

In a case where a voltage region of a transistor of a programmed second ground selection line Coded-GSL2 of a third string selection line SSL2 according to an example embodiment is greater than the first criterion UCL1 (e.g. where a voltage region of a transistor of a programmed second ground selection line Coded-GSL2 of a third string selection line SSL2 according to an example embodiment includes a voltage which is greater than the first criterion UCL1), the memory device <NUM> according to an example embodiment may perform a first rewrite operation (<NUM>st Re-write) on the transistor of the programmed second ground selection line Coded-GSL2. For example, the memory device <NUM> may determine that first threshold voltage programming of the transistor of the programmed second ground selection line Coded-GSL2 has failed and may perform the first rewrite operation (<NUM>st Re-write) on a transistor of a programmed second ground selection line Coded-GSL2 of a second string selection line SSL1.

In a case where a rewrite operation is performed on the transistor of the programmed second ground selection line Coded-GSL2, the memory device <NUM> according to an example embodiment may perform the first rewrite operation (<NUM>st Re-write) on the transistor of each of the programmed first ground selection line Coded-GSL1 and the programmed third ground selection line Coded-GSL3. In a case where the first rewrite operation (<NUM>st Re-write) is performed on the transistor of the programmed second ground selection line Coded-GSL2, the memory device <NUM> according to an example embodiment may perform the first rewrite operation (<NUM>st Re-write) on the transistor of each of the programmed first ground selection line Coded-GSL1 and the programmed third ground selection line Coded-GSL3 and may thus remove an adverse effect, caused by a variation of a threshold voltage, on an adjacent ground selection line.

<FIG> is a diagram for describing an example where a rewrite operation is performed on a second ground selection line, in a memory device <NUM> according to an example embodiment.

Referring to <FIG>, in a case where a voltage region of a transistor of a programmed first ground selection line Coded-GSL1 of a third string selection line SSL2 is less than the second criterion UCL2 (e.g. where a voltage region of a transistor of a programmed first ground selection line Coded-GSL1 of a third string selection line SSL2 includes a voltage which is less than the second criterion UCL2), the memory device <NUM> according to an example embodiment may perform a second rewrite operation (<NUM>nd Re-write) on a transistor of a programmed first ground selection line Coded-GSL1. For example, the memory device <NUM> may determine that second threshold voltage programming of the transistor of the programmed first ground selection line Coded-GSL1 has failed and may perform the second rewrite operation (<NUM>nd Re-write) on the transistor of the programmed first ground selection line Coded-GSL1 of a third string selection line SSL2. The second rewrite operation (<NUM>nd Re-write) according to an example embodiment may not include a rewrite operation on transistors of an adjacent ground selection line.

<FIG> is a diagram for describing an example where a rewrite operation is performed on a plurality of transistors of a memory device <NUM> according to an example embodiment.

Referring to <FIG>, when it is determined that there are transistors, which have a voltage region which is greater than the first criterion (e.g. when it is determined that there are transistors, which have a voltage region which includes a voltage which is greater than the first criterion), of transistors connected with a programmed first ground selection line Coded-GSL1, a programmed second ground selection line Coded-GSL2, or a programmed third ground selection line Coded-GSL3, the memory device <NUM> according to an example embodiment may perform a first rewrite operation PGM#<NUM> and a second rewrite operation PGM#<NUM>. The amount of shift of a threshold voltage based on the first rewrite operation PGM#<NUM> according to an example embodiment may be greater than the amount of shift of a threshold voltage based on the second rewrite operation PGM#<NUM>.

When the first rewrite operation PGM#<NUM> is completed, the memory device <NUM> according to an example embodiment may perform the second rewrite operation PGM#<NUM>. The memory device <NUM> according to an example embodiment may first perform a rewrite operation where the amount of shift of a threshold voltage is higher, and thus, may decrease an adverse effect, caused by a variation of the threshold voltage, on adjacent ground selection lines.

<FIG> is a block diagram of a memory device <NUM> applicable to a programmed ground selection line, according to an example embodiment.

Referring to <FIG>, the memory device <NUM> may include a memory cell array <NUM> and a peripheral circuit <NUM>, and the peripheral circuit <NUM> may include a page buffer <NUM>, a control logic <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. The peripheral circuit <NUM> may further include various elements, such as a data input/output (I/O) circuit or an I/O interface.

The memory cell array <NUM> may be connected with the page buffer <NUM> through bit lines BL and may be connected with the row decoder <NUM> through word lines WL, string selection lines SSL, and ground selection lines GSL. The memory cell array <NUM> may include a plurality of cell blocks, and each of the plurality of cell blocks may include a plurality of cell strings. Also, the plurality of cell blocks of the memory cell array <NUM> may include a special cell block CB(S) and a normal cell block CB(N).

The control logic <NUM> may program data in the memory cell array <NUM>, based on a command CMD, an address ADD, and a control signal CTRL, and may output various control signals (for example, a voltage control signal CTRL_vol, a row address X_ADD, and a column address Y_ADD) for reading data from the memory cell array <NUM>. The control logic <NUM> may adjust a level of a voltage generated by the voltage generator <NUM>.

The voltage generator <NUM> may generate various kinds of voltages for performing a program operation, a read operation, and an erase operation on the memory cell array <NUM>, based on the voltage control signal CTRL_vol. In <FIG>, it is illustrated that the voltage generator <NUM> generates a word line voltage VWL, and the word line voltage VWL may include a voltage provided to the word lines WL of the memory cell array <NUM>, a voltage provided to the string selection line SSL, and a voltage provided to the ground selection line GSL.

According to an example embodiment, the special cell block CB(S) and the normal cell block CB(N) may have different structures. For example, a same number of lines connected with the row decoder <NUM> may be disposed in each of the special cell block CB(S) and the normal cell block CB(N), and more dummy lines and/or more ground selection lines may be disposed in the normal cell block CB(N) than a GSL region of the special cell block CB(S). Therefore, the number of word lines WL connected with memory cells, storing information or data, of the special cell block CB(S) may have a value which is less than the number of word lines WL of the normal cell block CB(N). That is, the number of memory cells storing information or data in the special cell block CB(S) may be less than the normal cell block CB(N).

Furthermore, the control logic <NUM> may control a voltage level for coding of a GSL region included in the special cell block CB(S) and the normal cell block CB(N). For example, based on control by the control logic <NUM>, a program operation may be performed so that a level of each of threshold voltages of ground selection transistors included in the special cell block CB(S) differs from that of each of threshold voltages of ground selection transistors included in the normal cell block CB(N). Also, the control logic <NUM> may control a voltage control operation for adjusting a threshold voltage level of each of dummy cells included in the special cell block CB(S).

<FIG> is a cross-sectional view illustrating a memory device <NUM> including a B-VNAND structure, according to an example embodiment.

<FIG> is a diagram for describing the memory device <NUM> according to an example embodiment.

Referring to <FIG>, the memory device <NUM> may have a chip to chip (C2C) structure. Here, the C2C structure may denote that at least one upper chip including a cell region CELL and a lower chip including a peripheral circuit region PERI are each manufactured, and then, the at least one upper chip is connected with the at least one lower chip through a bonding process. For example, the bonding process may denote a process of electrically or physically connecting a bonding metal pattern, formed on an uppermost metal layer of the upper chip, with a bonding metal pattern formed on an uppermost metal layer of the lower chip. For example, in a case where the bonding metal patterns include copper (Cu), the bonding process may be a Cu-Cu bonding process. As another example, the bonding metal patterns may include aluminum (Al) or tungsten (W).

The memory device <NUM> may include one or more upper chips each including a cell region. For example, as illustrated in <FIG>, the memory device <NUM> may be implemented to include two upper chips. However, this is provided as an example, and the number of upper chips is not limited thereto. In a case where the memory device <NUM> is implemented to include two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including the peripheral circuit region PERI may each be manufactured, and then, the first upper chip, the second upper chip, and the lower chip may be connected with one another by a bonding process, thereby manufacturing the memory device <NUM>. The first upper chip may be reversed (e.g. turned upside down) and connected with the lower chip by a bonding process, and the second upper chip may be reversed (e.g. turned upside down) and connected with the first upper chip by a bonding process. In the following description, upper portions and lower portions of the first and second upper chips may be referred to with respect to a state before the first upper chip and the second upper chip are reversed (e.g. turned upside down). That is, in <FIG>, an upper portion of the lower chip may denote an upper portion with respect to a +Z-axis direction, and an upper portion of each of the first and second upper chips may denote an upper portion with respect to a -Z-axis direction. However, this is provided as an example, and only one of the first upper chip and the second upper chip may be reversed (e.g. turned upside down) and the first upper chip and the second upper chip may be connected with each other by a bonding process.

Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device <NUM> may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

The peripheral circuit region PERI may include a first substrate <NUM> and a plurality of circuit devices 220a to 220c provided on the first substrate <NUM>. An interlayer insulation layer <NUM> including one or more insulation layers may be provided on the plurality of circuit devices 220a to 220c, and a plurality of metal wirings connecting the plurality of circuit devices 220a to 220c with one another may be provided in the interlayer insulation layer <NUM>. For example, the plurality of metal wirings may include first metal wirings 230a to 230c respectively connected with the plurality of circuit devices 220a to 220c and second metal wirings 240a to 240c formed on the first metal wirings 230a to 230c. The plurality of metal wirings may include at least one of various conductive materials. For example, the first metal wirings 230a to 230c may include tungsten which is relatively high in electrical resistivity, and the second metal wirings 240a to 240c may include copper which is relatively low in electrical resistivity.

Herein, only the first metal wirings 230a to 230c and the second metal wirings 240a to 240c are illustrated, but example embodiments are not limited thereto and one or more additional metal wirings may be further formed on the second metal wirings 240a to 240c. In this case, the second metal wirings 240a to 240c may include aluminum. Also, at least a portion of each of the additional metal wirings formed on the second metal wirings 240a to 240c may include copper having electrical resistivity which is lower than that of aluminum of the second metal wirings 240a to 240c.

The interlayer insulation layer <NUM> may be disposed on the first substrate <NUM> and may include an insulating material such as silicon oxide or silicon nitride.

Each of the first and second cell regions CELL1 and CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate <NUM> and a common source line <NUM>. A plurality of word lines <NUM> to <NUM> (<NUM>) may be stacked on the second substrate <NUM> in a direction (a Z-axis direction) perpendicular to an upper surface of the second substrate <NUM>. String selection lines and a ground selection line may be disposed on and under the word lines <NUM>, and a plurality of word lines <NUM> may be disposed between the string selection lines and the ground selection line. Likewise, the second cell region CELL2 may include a third substrate <NUM> and a common source line <NUM>, and a plurality of word lines <NUM> to <NUM> (<NUM>) may be stacked on the third substrate <NUM> in a direction (the Z-axis direction) perpendicular to an upper surface of the third substrate <NUM>. The second substrate <NUM> and the second substrate <NUM> may include various materials, and for example, may each be a substrate including a monocrystalline epitaxial layer grown on a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline silicon substrate. A plurality of channel structures CH may be formed in each of the first and second cell regions CELL1 and CELL2.

In an example embodiment, as illustrated in A1, the channel structure CH may be provided in the bit line bonding region BLBA, and the channel structure CH may extend in a direction perpendicular to the upper surface of the third substrate <NUM> and may pass through the word lines <NUM>, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulation layer. The channel layer may be electrically connected with the first metal wiring 350c and the second metal wiring 360c in the bit line bonding region BLBA. For example, the second metal wiring 360c may be a bit line and may be connected with the channel structure CH through the first metal wiring 350c. The bit line 360c may extend in a first direction (a Y-axis direction) parallel to an upper surface of the second substrate <NUM>.

In an example embodiment, as illustrated in A2, the channel structure CH may include a lower channel LCH and an upper channel UCH, which are connected with each other. For example, the channel structure CH may be formed through a process on the lower channel LCH and a process of the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate <NUM> and may pass through the common source line <NUM> and the lower word lines <NUM> and <NUM>. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulation layer and may be connected with the upper channel UCH. The upper channel UCH may pass through the upper word lines <NUM> to <NUM>. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulation layer, and the channel layer of the upper channel UCH may be electrically connected with the first metal wiring 350c and the second metal wiring 360c. As a length of a channel increases, it may be difficult to form a channel having a certain width for process reasons. The memory device <NUM> according to an example embodiment may include a channel having width uniformity improved through the lower channel LCH and the upper channel UCH, which are formed through sequential processes.

As illustrated in A2, in a case where the channel structure CH is formed to include the lower channel LCH and the upper channel UCH, a word line disposed at a boundary portion between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the word line <NUM> and the word line <NUM> each configuring a boundary between the lower channel LCH and the upper channel UCH may each be a dummy word line. In this case, data may not be stored in memory cells connected with the dummy word line. Alternatively, the number of pages corresponding to the memory cells connected with the dummy word line may be less than the number of pages corresponding to memory cells connected with a normal word line. A voltage level applied to the dummy word line may differ from a voltage level applied to the normal word line, and thus, a non-uniform channel width between the lower channel LCH and the upper channel UCH may decrease an adverse effect on a memory device.

Furthermore, in A2, it is illustrated that the number of lower word lines <NUM> and <NUM> through which the lower channel LCH passes is less than the number of upper word lines <NUM> to <NUM> through which the upper channel UCH passes. However, this is provided as an example, and example embodiments are not limited thereto. As another example, the number of lower word lines passing through the lower channel LCH may be greater than or equal to the number of upper word lines passing through the upper channel UCH. Also, a connection relationship and a structure of the channel structure CH disposed in the first cell region CELL1 described above may be identically applied to the channel structure CH disposed in the second cell region CELL2.

In the bit line bonding region BLBA, a first through via THV1 may be provided in the first cell region CELL1, and a second through via THV2 may be provided in the second cell region CELL2. As illustrated in <FIG>, the first through via THV1 may pass through the common source line <NUM> and the plurality of word lines <NUM>. However, this is provided as an example, and the first through via THV1 may further pass through the second substrate <NUM>. The first through via THV1 may include a conductive material. Alternatively, the first through via THV1 may include a conductive material which is surrounded by an insulating material. The second through via THV2 may be provided in the same shape and structure as those of the first through via THV1.

In an example embodiment, the first through via THV1 and the second through via THV2 may be electrically connected with a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d may be formed at a lower end of the first upper chip including the first cell region CELL1, and the second through metal pattern 472d may be formed at an upper end of the second upper chip including the second cell region CELL2. The first through via THV1 may be electrically connected with the first metal wiring 350c and the second metal wiring 360c. A lower via 371d may be formed between the first through via THV1 and the first through metal pattern 372d, and an upper via 471d may be formed between the second through via THV2 and the second through metal pattern 472d. The first through metal pattern 372d may be connected with the second through metal pattern 472d by a bonding process.

Also, in the bit line bonding region BLBA, an upper metal pattern <NUM> may be formed on the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern <NUM> having the same shape as that of the upper metal pattern <NUM> may be formed on the uppermost metal layer of the first cell region CELL1. The upper metal pattern <NUM> of the first cell region CELL1 may be electrically connected with the upper metal pattern <NUM> of the peripheral circuit region PERI by a bonding process. In the bit line bonding region BLBA, a bit line 360c may be electrically connected with a page buffer included in the peripheral circuit region PERI. For example, some of the circuit devices 220c of the peripheral circuit region PERI may provide the page buffer, and the bit line 360c may be electrically connected with the circuit devices 220c, providing the page buffer, through the upper bonding metal 370c of the first cell region CELL1 and the upper bonding metal 270c of the peripheral circuit region PERI.

Continuously, referring to <FIG>, in the word line bonding region WLBA, the word lines <NUM> of the first cell region CELL1 may extend in a second direction (an X-axis direction) parallel to the upper surface of the second substrate <NUM> and may be connected with a plurality of cell contact plugs <NUM> to <NUM> (<NUM>). A first metal wiring 350b and a second metal wiring 360b may be sequentially connected with upper portions of the cell contact plugs <NUM> connected with the word lines <NUM>. The cell contact plugs <NUM> may be connected with the peripheral circuit region PERI through the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI, in the word line bonding region WLBA.

The cell contact plugs <NUM> may be electrically connected with a row decoder included in the peripheral circuit region PERI. For example, some of the circuit devices 220b of the peripheral circuit region PERI may provide the row decoder, and the cell contact plugs <NUM> may be electrically connected with the circuit devices 220b, providing the row decoder, through the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI. In an example embodiment, an operation voltage of each of the circuit devices 220b providing the row decoder may differ from that of each of the circuit devices 220c providing the page buffer. For example, the operation voltage of each of the circuit devices 220c providing the page buffer may differ from that of each of the circuit devices 220b providing the row decoder.

Likewise, in the word line bonding region WLBA, the word lines <NUM> of the second cell region CELL2 may extend in the second direction (the X-axis direction) parallel to an upper surface of the third substrate <NUM> and may be connected with a plurality of cell contact plugs <NUM> to <NUM> (<NUM>). The cell contact plugs <NUM> may be connected with the peripheral circuit region PERI through an upper metal pattern of the second cell region CELL2, a lower metal pattern and an upper metal pattern of the first cell region CELL1, and the cell contact plug <NUM>.

In the word line bonding region WLBA, the upper bonding metal 370b may be formed in the first cell region CELL1, and the upper bonding metal 270b may be formed in the peripheral circuit region PERI. The upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI may be electrically connected with each other by a bonding process. The upper bonding metal 370b and the upper bonding metal 270b may include aluminum, copper, or tungsten.

In the external pad bonding region PA, a lower metal pattern 371e may be formed at a lower portion of the first cell region CELL1, and an upper metal pattern 472a may be formed at an upper portion of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 may be connected with the upper metal pattern 472a of the second cell region CELL2 by a bonding process, in the external pad bonding region PA. Likewise, an upper metal pattern 372a may be formed at an upper portion of the first cell region CELL1, and an upper metal pattern 272a may be formed at an upper portion of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 may be connected with the upper metal pattern 272a of the peripheral circuit region PERI by a bonding process.

Common source line contact plugs <NUM> and <NUM> may be disposed in the external pad bonding region PA. The common source line contact plugs <NUM> and <NUM> may include a conductive material such as metal, a metal compound, or doped polysilicon. The common source line contact plug <NUM> of the first cell region CELL1 may be electrically connected with the common source line <NUM>, and the common source line contact plug <NUM> of the second cell region CELL2 may be electrically connected with the common source line <NUM>. The first metal wiring 350a and the second metal wiring 360a may be sequentially stacked on the common source line contact plug <NUM> of the first cell region CELL1, and the first metal wiring 450a and the second metal wiring 460a may be sequentially stacked on the common source line contact plug <NUM> of the second cell region CELL2.

A plurality of I/O pads (for example, first to third I/O pads) <NUM>, <NUM>, and <NUM> may be disposed in the external pad bonding region PA. Referring to <FIG>, a lower insulation layer <NUM> may cover a lower surface of the first substrate <NUM>, and the first I/O pad <NUM> may be formed on the lower insulation layer <NUM>. The first I/O pad <NUM> may be connected with, through the first I/O contact plug <NUM>, at least one of the plurality of circuit devices 220a disposed in the peripheral circuit region PERI and may be isolated from the first substrate <NUM> by the lower insulation layer <NUM>. Also, a side insulation layer may be disposed between the first I/O contact plug <NUM> and the first substrate <NUM> and may electrically disconnect the first I/O contact plug <NUM> from the first substrate <NUM>.

An upper insulation layer <NUM> covering an upper surface of the third substrate <NUM> may be formed on the third substrate <NUM>. The second I/O pad <NUM> and/or the third I/O pad <NUM> may be disposed on the upper insulation layer <NUM>. The second I/O pad <NUM> may be connected with, through the second I/O contact plugs <NUM> and <NUM>, at least one of the plurality of circuit devices 220a disposed in the peripheral circuit region PERI, and the third I/O pad <NUM> may be connected with, through the third I/O contact plugs <NUM> and <NUM>, at least one of the plurality of circuit devices 220a disposed in the peripheral circuit region PERI.

In an example embodiment, the third substrate <NUM> may not be disposed in a region where an I/O contact plug is disposed. For example, as illustrated in B, the third I/O contact plug <NUM> may be isolated from the third substrate <NUM> in a direction parallel to the upper surface of the third substrate <NUM> and may be connected with the third I/O pad <NUM> via the interlayer insulation layer <NUM> of the second cell region CELL2. In this case, the third I/O contact plug <NUM> may be formed by various processes.

For example, as illustrated in B1, the third I/O contact plug <NUM> may extend in a third direction (a Z-axis direction) and may have a diameter which increases progressively toward the upper insulation layer <NUM>. That is, a diameter of the channel structure CH described in A1 may decrease progressively toward the upper insulation layer <NUM>, and a diameter of the third I/O contact plug <NUM> may increase progressively toward the upper insulation layer <NUM>. For example, the third I/O contact plug <NUM> may be formed after the second cell region CELL2 is bonded to the first cell region CELL1 by a bonding process.

Also, for example, as illustrated in B2, the third I/O contact plug <NUM> may extend in the third direction (the Z-axis direction) and may have a diameter which decreases progressively toward the upper insulation layer <NUM>. That is, like the channel structure CH, a diameter of the third I/O contact plug <NUM> may be formed to decrease progressively toward the upper insulation layer <NUM>. For example, the third I/O contact plug <NUM> may be formed along with the cell contact plugs <NUM> before the second cell region CELL2 is bonded to the first cell region CELL1.

In another example embodiment, an I/O contact plug may be disposed to overlap the third substrate <NUM>. For example, as illustrated in C, the second I/O contact plug <NUM> may be formed to pass through the interlayer insulation layer <NUM> of the second cell region CELL2 in the third direction (the Z-axis direction) and may be electrically connected with the second I/O pad <NUM> through the third substrate <NUM>. In this case, a connection structure between the second I/O contact plug <NUM> and the second I/O pad <NUM> may be implemented as various types.

For example, as illustrated in C1, an opening portion <NUM> passing through the third substrate <NUM> may be formed, and the second I/O contact plug <NUM> may be directly connected with the second I/O pad <NUM> through the opening portion <NUM> formed in the third substrate <NUM>. In this case, as illustrated in C1, a diameter of the second I/O contact plug <NUM> may increase progressively toward the second I/O pad <NUM>. However, this is provided as an example, and a diameter of the second I/O contact plug <NUM> may decrease progressively toward the second I/O pad <NUM>.

For example, as illustrated in C2, the opening portion <NUM> passing through the third substrate <NUM> may be formed, and a contact <NUM> may be formed in the opening portion <NUM>. One end portion of the contact <NUM> may be connected with the second I/O pad <NUM>, and the other end portion may be connected with the second I/O contact plug <NUM>. Accordingly, the second I/O contact plug <NUM> may be electrically connected with the second I/O pad <NUM> through the contact <NUM> of the opening portion <NUM>. In this case, as illustrated in C2, a diameter of the contact <NUM> may increase progressively toward the second I/O pad <NUM>, and a diameter of the second I/O contact plug <NUM> may decrease progressively toward the second I/O pad <NUM>. For example, the third I/O contact plug <NUM> may be formed along with the cell contact plugs <NUM> before the second cell region CELL2 is bonded to the first cell region CELL1, and the contact <NUM> may be formed after the second cell region CELL2 is bonded to the first cell region CELL1.

Also, for example, as illustrated in C3, a stopper <NUM> may be further formed on an upper surface of the opening portion <NUM> of the third substrate <NUM> unlike C2. The stopper <NUM> may be a metal wiring which is formed on the same layer as the common source line <NUM>. However, this is provided as an example, and the stopper <NUM> may be a metal wiring which is formed on the same layer as at least one of the word lines <NUM>. The second I/O contact plug <NUM> may be electrically connected with the second I/O pad <NUM> through the contact <NUM> and the stopper <NUM>.

Furthermore, similarly to the second and third I/O contact plugs <NUM> and <NUM> of the second cell region CELL2, each of the second and third I/O contact plugs <NUM> and <NUM> of the first cell region CELL1 may have a diameter which decreases progressively toward the lower metal pattern 371e, or may have a diameter which increases progressively toward the lower metal pattern 371e.

Furthermore, according to example embodiments, a slit <NUM> may be formed in the third substrate <NUM>. For example, the slit <NUM> may be formed at an arbitrary position of the external pad bonding region PA. For example, as illustrated in D, as seen in a plan view, the slit <NUM> may be disposed between the second I/O pad <NUM> and the cell contact plugs <NUM>. However, this is provided as an example, and as seen in a plan view, the slit <NUM> may be formed so that the second I/O pad <NUM> is disposed between the slit <NUM> and the cell contact plugs <NUM>.

For example, as illustrated in D1, the slit <NUM> may be formed to pass through the third substrate <NUM>. The slit <NUM>, for example, may be used for preventing the third substrate <NUM> from being finely cracked when forming the opening portion <NUM>. However, this is provided as an example, and the slit <NUM> may be formed to have a depth of about <NUM>% to about <NUM>% with respect to a thickness of the third substrate <NUM>.

Also, for example, as illustrated in D2, a conductive material <NUM> may be formed in the slit <NUM>. The conductive material <NUM>, for example, may be used for discharging a leakage current occurring when circuit devices of the external pad bonding region PA are being driven. In this case, the conductive material <NUM> may be connected with an external ground line.

Also, for example, as illustrated in D3, an insulating material <NUM> may be formed in the slit <NUM>. The insulating material <NUM>, for example, may be formed for electrically disconnecting the word line bonding region WLBA from the second I/O pad <NUM> and the second I/O contact plug <NUM> each disposed in the external pad bonding region PA. The insulating material <NUM> may be formed in the slit <NUM>, and thus, may prevent a voltage supplied through the second I/O pad <NUM> from adversely affecting a metal layer disposed on the third substrate <NUM> of the voltage word line bonding region WLBA.

Furthermore, according to example embodiments, the first to third I/O pads <NUM>, <NUM>, and <NUM> may be selectively formed. For example, the memory device <NUM> may be implemented to include only the first I/O pad <NUM> disposed on the first substrate <NUM>, include only the second I/O pad <NUM> disposed on the third substrate <NUM>, or include only the third I/O pad <NUM> disposed on the upper insulation layer <NUM>.

Furthermore, according to example embodiments, at least one of the second substrate <NUM> of the first cell region CELL1 and the third substrate <NUM> of the second cell region CELL2 may be used as a sacrificial substrate, and all or only a portion thereof may be removed before or after a bonding process. An additional layer may be stacked after a substrate is removed. For example, the second substrate <NUM> of the first cell region CELL1 may be removed before or after the peripheral circuit region PERI is bonded to the first cell region CELL1, and a conductive layer for connection or an insulation layer covering an upper surface of the common source line <NUM> may be formed. Similarly, the third substrate <NUM> of the second cell region CELL2 may be removed before or after the first cell region CELL1 is bonded to the second cell region CELL2, and a conductive layer for connection or an upper insulation layer <NUM> covering the upper surface of the common source line <NUM> may be formed.

<FIG> is a block diagram illustrating an example where a memory device according to an example embodiment is applied to a solid state drive (SSD) system <NUM>.

Referring to <FIG>, the SSD system <NUM> may include a host <NUM> and an SSD <NUM>. The SSD <NUM> may transmit or receive a signal to or from a host through a signal connector and may be supplied with power through a power connector. The SSD <NUM> may include an SSD controller <NUM>, an auxiliary power supply <NUM>, and memory devices 723_1 to 723_n. The memory devices 723_1 to 723_n may each be a vertical stack type NAND flash memory device. In this case, the SSD <NUM> may be implemented by using the example embodiments described above with reference to <FIG>. That is, each of the memory devices 723_1 to 723_n may include a plurality of cell blocks, and at least one of the plurality of cell blocks may correspond to a special cell block. Also, a GSL region included in the special cell block may have a structure illustrated in <FIG>, or GSL region coding may be performed based on a method illustrated in <FIG>.

In some example embodiments, each of the components represented by a block as illustrated in <FIG>, <FIG>, <FIG>, and <FIG> may be implemented as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to example embodiments. For example, at least one of these components may include various hardware components including a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), transistors, capacitors, logic gates, or other circuitry using a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components may include a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Also, at least one of these components may further include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Functional aspects of example embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements, modules or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

Claim 1:
A non-volatile memory device (<NUM>) including memory blocks, each of the memory blocks including a plurality of cell strings connected in parallel between a bitline and a common source line, each of the cell strings comprising
a plurality of memory cells respectively connected with a plurality of word lines and at least a first ground selection transistor connected with a first ground selection line (111a) and a second ground selection transistor connected with a second ground selection line (111b); wherein
a plurality of first ground selection transistors connected with the first ground selection line (111a) is programmed to have a first threshold voltage;
a plurality of second ground selection transistors connected with the second ground selection line (<NUM>) is programmed to have a second threshold voltage which differs from the first threshold voltage; and
a control circuit (<NUM>) configured to:
control an erase operation (S630, S640) to be performed on each of at least one first ground selection transistor of the plurality of first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and
control a threshold voltage of each of the plurality of second ground selection transistors to be compared (S650) with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed.