Patent Description:
The BSPDN semiconductor architecture separates the signal wiring from the power distribution network (PDN) in a semiconductor device by providing an integrated circuit including active transistors, signal wires, and buried power rails (BPRs) on a first side of a wafer and providing the PDN on a second side of the wafer. The BSPDN semiconductor architecture may minimize the routing congestion and allow for down scaling of an area of the semiconductor architecture. A BSPDN semiconductor architecture may result in a ~<NUM> % reduction and an improved current-resistance (IR) drop as compared to a general PDN semiconductor architecture.

However, there may be difficulties in manufacturing BSPDN semiconductor architectures because accurately aligning an integrated circuit and a PDN provided on each side of a wafer may be difficult. For example, a misalignment between a buried power rail (BPR) included in the integrated circuit integrated on the first side of the wafer with a through-silicon via (TSV) protruding from the PDN integrated on the second side of the wafer may occur. Such misalignment between the BPR and the TSV may lead to an increase in resistance and device failure of the semiconductor architecture.

Technologies to improve alignment between the BPR and TSV by providing the TSV at a greater depth have been developed. For example, additional etching for the TSV may be carried out after the BPR is provided. However, increasing the depth of the TSV may damage the semiconductor architecture. Further, the additional etching would depend on a size of the BPR provided which would limit the manufacturing process of the additional etching, and the misalignment between the TSV and the BPR may still exist.

From document <CIT> it is known a method that includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions.

From document <CIT> it is known an integrated circuit has a buried interconnect in a buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Information disclosed in this Background section has already been known to the inventors before achieving the embodiments of the present application or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form the prior art that is already known to the public.

Object of the present invention is to provide an improved backside power distribution network (BSPDN) semiconductor architecture in which aforementioned problems are mitigated and a method of manufacturing the same. The object of the invention is attained by a semiconductor architecture according to claim <NUM> and a method of manufacturing a semiconductor architecture according to claim <NUM>. Further developments are specified by the dependent claims.

The example embodiments described herein are examples, and thus, the present disclosure is not limited thereto, and may be realized in various other forms.

In addition, it should be understood that all descriptions of principles, aspects, examples, and example embodiments are intended to encompass structural and functional equivalents thereof. In addition, these equivalents should be understood as including not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same functions regardless of the structures thereof.

It will be understood that when an element, component, layer, pattern, structure, region, or so on (hereinafter collectively "element") of a semiconductor device is referred to as being "over," "above," "on," "below," "under," "beneath," "in contact with," "connected to" or "coupled to" another element the semiconductor device, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or an intervening element(s) may be present. In contrast, when an element of a semiconductor device is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly in contact with, " "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numerals refer to like elements throughout this disclosure.

Spatially relative terms, such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," "top," and "bottom," and the like, may be used herein for ease of description to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of a semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Herein, when a term "same" is used to compare a dimension of two or more elements, the term may cover a "substantially same" dimension.

It will be understood that, although the terms "first," "second," "third," "fourth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

It will be also understood that, even if a certain step or operation of manufacturing an apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of the example embodiments (and intermediate structures). Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. Further, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, general elements to semiconductor devices may or may not be described in detail herein.

<FIG> illustrates a perspective view of a general PDN semiconductor architecture and a BSPDN semiconductor architecture according to a comparative example which as such is outside the scope of the appended claims.

Referring to <FIG>, a general PDN semiconductor architecture <NUM> includes a PDN/signal wiring device <NUM> on one side of the wafer <NUM>. However, such configuration of the general PDN semiconductor architecture <NUM> causes routing congestion in the PDN/signal wiring device <NUM> and increases an area of the semiconductor architecture. In addition, a resistance of the general PDN semiconductor architecture <NUM> may be relatively high.

As illustrated in <FIG>, according to an example embodiment, a BSPDN semiconductor architecture <NUM> is configured to separate the signal wiring semiconductor device <NUM>, to be provided on a first side of the wafer <NUM>, from a power distribution network (PDN) semiconductor device <NUM> to be provided on a second side of the wafer <NUM> opposite to the signal wiring semiconductor device <NUM>. The BSPDN semiconductor architecture <NUM> according to an example embodiment may reduce the routing congestion and the area of the semiconductor architecture by removing the PDN from the first side of the wafer, and hence may also improve an IR drop. For example, the area of the semiconductor architecture may be reduced by <NUM> % compared to the general PDN semiconductor architecture <NUM>. However, embodiments are not limited thereto.

<FIG> illustrates a BSPDN semiconductor architecture according to a comparative example which as such is outside the scope of the appended claims.

Referring the <FIG>, the semiconductor architecture <NUM> may include a wafer <NUM>, a first semiconductor device 1200a provided on a first surface of the wafer <NUM>, and a second semiconductor device 1200b provided on a second surface of the wafer <NUM>. The first semiconductor device 1200a may be an integrated circuit for signal routing including components such as, for example, active transistors, signal wires, and BPRs <NUM>, etc. The active transistors may include a power tapping epitaxial layer and a non-power tapping epitaxial layer. The signal wires are connected to the non-power tapping epitaxial layer of the active transistors for signal routing between the active transistors. The BPRs <NUM> are connected to the power tapping epitaxial layer of the active transistors and are not connected to the signal wires. The BPRs <NUM> are respectively configured to deliver power to the active transistors. The second semiconductor device 1200b may be a PDN integrated circuit. A TSV <NUM> configured as a power connecting structure may protrude from the semiconductor device 1200b.

As illustrated in <FIG>, the BPR <NUM> included in the first semiconductor device 1200a and the TSV <NUM> protruding from the second semiconductor device 1200b may be misaligned with each other. The misalignment between the BPR <NUM> and the TSV <NUM> may increase the resistance of the semiconductor architecture <NUM> and may lead to a device failure of the semiconductor architecture <NUM>.

<FIG> illustrate a method of manufacturing a BSPDN semiconductor architecture according to a comparative example which as such is outside the scope of the appended claims.

As illustrated in <FIG>, the method may include providing a wafer <NUM> including a sacrificial layer 1100a, an etch stop layer <NUM>, and a carrier substrate 1100b. The sacrificial layer 1100a may be a silicon (Si) bulk layer, and the carrier substrate 1100b may be a Si layer. The etch stop layer <NUM> may be provided between the sacrificial layer 1100a and the carrier substrate 1100b.

A first semiconductor device 1200a may be provided on a first surface of the carrier substrate 1100b. The first semiconductor device 1200a may be an integrated circuit including components such as, for example, active transistors, signal wires, and BPRs <NUM>. The BPR <NUM> may be provided on a first surface of the carrier substrate 1100b.

Referring to <FIG>, a wafer-to-wafer bonding process may be carried out. For example, a second wafer <NUM> may be provided on a first surface of the first semiconductor device 1200a. The second wafer <NUM> may be bonded by an adhesive layer <NUM> provided between the first semiconductor device 1200a and the second wafer <NUM>. The wafer-to-wafer bonded semiconductor architecture is flipped.

Referring to <FIG>, the sacrificial layer 1100a may be removed, and the etch stop layer <NUM> may be removed to expose the second surface of the carrier substrate 1100b.

Referring to <FIG>, a second semiconductor device 1200b may be provided on the exposed second surface of the carrier substrate 1100b. The second semiconductor device 1200b may be a PDN integrated circuit with, for example, a TSV <NUM> protruding from a first surface of the second semiconductor device 1200b. The TSV <NUM> may be formed to penetrate the carrier substrate 1100b. The second semiconductor device 1200b may be provided on the second surface of the carrier substrate 1100b based on a location of the BPR <NUM> included in the first semiconductor device 1200a to land on the BPR <NUM>.

However, as illustrated in <FIG>, a misalignment may occur between the TSV <NUM> and the BPR <NUM> because it is difficult to accurately detect a location of the BPR <NUM> during a TSV <NUM> landing process when integrating the second semiconductor device 1200b on a second side of the carrier substrate 1100b. Due to the misalignment between the TSV <NUM> and the BPR <NUM> which results in a misalignment between the first semiconductor device 1200a and the second semiconductor device 1200b, a resistance of the semiconductor architecture <NUM> may increase. In addition, the misalignment between the first semiconductor device 1200a and the second semiconductor device 1200b may lead to a failure of the semiconductor architecture <NUM>.

<FIG> illustrates a perspective view of a BSPDN semiconductor architecture according to an example embodiment.

As illustrated in <FIG>, the BSPDN semiconductor architecture <NUM> includes a wafer <NUM>, a first semiconductor device 200a provided on a first surface of the wafer <NUM>, and a second semiconductor device 200b provided on a second surface of the wafer <NUM> opposite to the first semiconductor device 200a. The first semiconductor device 200a and the second semiconductor device 200b may be integrated to each other and may form a BSPDN semiconductor architecture <NUM>.

The wafer <NUM> may include, for example, a Si substrate, a glass substrate, a sapphire substrate, etc. However, embodiments are not limited thereto. As illustrated in <FIG>, the wafer <NUM> may be a circular panel, but the shape of the wafer <NUM> is not limited thereto. For example, the wafer <NUM> may be a tetragonal panel. The wafer <NUM> may include a single layer or multiple layers.

<FIG> illustrates a cross-sectional view taken along line I-I' of <FIG> according to an example embodiment.

The example BSPDN semiconductor architecture <NUM> includes a first semiconductor device 200a provided on a first surface of the wafer <NUM> and a second semiconductor device 200b provided on a second surface of the wafer <NUM>. The first semiconductor device 200a is an integrated circuit including components such as, for example, active transistors, signal wires, and BPRs <NUM>, etc. The BPR <NUM> may be provided to face the first surface of the wafer <NUM>. The active transistors may include a power tapping epitaxial layer and a non-power tapping epitaxial layer. The signal wires are connected to the non-power tapping epitaxial layer of the active transistors for signal routing between the active transistors. The BPRs <NUM> are connected to the power tapping epitaxial layer of the active transistors and are not connected to the signal wires. The BPRs <NUM> are respectively configured to deliver power to the active transistors. The second semiconductor device 200b is a PDN integrated circuit. A TSV <NUM> configured as a power connecting structure may be formed to protrude from a first surface of the second semiconductor device 200b and penetrate the wafer <NUM>.

Referring to <FIG>, the BSPDN semiconductor architecture <NUM> also includes a landing pad <NUM>. The landing pad <NUM> is provided between the BPR <NUM> and the TSV <NUM>. The landing pad <NUM> is covered by a TSV etch stop layer <NUM> and an encapsulant <NUM>. A second surface of the landing pad <NUM> is covered by a TSV etch stop layer <NUM> and the first surface of the landing pad <NUM> is covered by an encapsulant. The side surfaces of the landing pad <NUM> may be covered or encapsulated by the encapsulant <NUM>. The landing pad <NUM> may have a rectangular shape from a cross-sectional view and have flat first and second surfaces, but shapes of the landing pad <NUM> are not limited thereto. The landing pad <NUM> may be formed of metal having a relatively low resistance. For example, the landing pad <NUM> may be formed of copper (Cu), cobalt (Co), ruthenium (Ru), etc. However, embodiments are not limited thereto. A width of the landing pad <NUM> may be greater than a width of the BPR <NUM> and a width of the TSV <NUM>, but embodiments are not limited thereto.

As illustrated in <FIG>, the alignment between the BPR <NUM> and the TSV <NUM> may be improved as compared to the related embodiment by providing the landing pad <NUM> which is included in the wafer <NUM> prior to providing the BPR <NUM> and the TSV <NUM>. Accordingly, the first semiconductor device 200a and the second semiconductor device 200b may be more accurately aligned with each other as compared to the related embodiment. Based on the improved alignment of the first semiconductor device 200a and the second semiconductor device 200b, the integration and performance of the BSPDN semiconductor architecture <NUM> may be improved. Further, by providing semiconductor devices on both of the first surface of the wafer <NUM> and the second surface of the wafer <NUM>, the area and the resistance of the BSPDN semiconductor architecture <NUM> may be reduced.

<FIG> illustrate a method of manufacturing a BSPDN semiconductor architecture according to an example embodiment.

Referring to <FIG>, the method includes providing a wafer <NUM> including a sacrificial layer 100a, an etch stop layer <NUM>, and a carrier substrate 100b. The sacrificial layer 100a may be a Si bulk layer. The etch stop layer <NUM> may be provided on the sacrificial layer 100a. For example, the etch stop layer <NUM> may be provided by an epitaxial growth of silicon germanium (SiGe) on the sacrificial layer 100a. However, embodiments are not limited thereto. For example, the etch stop layer <NUM> may be an oxide layer in a silicon-on-insulator (SOI) wafer. The carrier substrate 100b may include, for example, a Si substrate, a glass substrate, a sapphire substrate, etc. However, embodiments are not limited thereto.

A TSV etch stop layer <NUM> is provided on a first surface of the carrier substrate 100b.

Referring to <FIG>, a landing pad <NUM> is formed on a first surface of the TSV etch stop layer <NUM> by depositing and patterning a metal material. The metal material of the landing pad <NUM> may be a material having a relatively low resistance such as, for example, Cu, Co, Ru, etc. However, embodiments are not limited thereto. According to an example embodiment, the landing pad <NUM> may have a rectangular shape from a cross-sectional view and have flat first and second surface. However, embodiments are not limited thereto and the landing pad <NUM> may have various shapes. An encapsulant <NUM> is provided on the landing pad <NUM> and the first surface of the TSV etch stop layer <NUM> to protect the landing pad <NUM>. For example, the encapsulant <NUM> may encapsulate the landing pad <NUM> and the first surface of the TSV etch stop layer <NUM>. The encapsulant <NUM> may be formed of epoxy resin, silica, etc. However, materials of the encapsulant <NUM> are not limited thereto.

The encapsulant <NUM> and the TSV etch stop layer <NUM> may be removed in areas other than in the area covering the first surface and side surfaces of the landing pad <NUM> to expose the first surface of the carrier substrate 100b. The encapsulant <NUM> and the TSV etch stop layer <NUM> may be removed by, for example, patterned etching. However, embodiments are not limited thereto.

A substrate layer 100b' may be provided on the landing pad <NUM> and the exposed first surface of the carrier substrate 100b. The substrate layer 100b' may be, for example, a Si layer. The substrate layer 100b' may be provided to carry out, for example, a front-end-of-line (FEOL) and middle-end-of-line (MEOL) integration in a first semiconductor device 200a. The carrier substrate 100b and the substrate layer 100b' may be integrally formed, and may be together referred to as the carrier substrate 100b.

Referring to <FIG>, a first semiconductor device 200a is provided on a first surface of the carrier substrate 100b. The first semiconductor device 200a is an integrated circuit including components such as, for example, active transistors, signal wires, and BPRs <NUM>, etc. The BPR <NUM> may be provided on a first surface of the carrier substrate 100b to be in contact with the landing pad <NUM> based on a location of the landing pad <NUM>. The location of the landing pad <NUM> may be detected based on a preset alignment key, but embodiments are not limited thereto.

The landing pad <NUM> may have a greater width than a width of the BPR <NUM>, but embodiments are not limited thereto. For example, a width of the BPR <NUM> may range from around <NUM> to <NUM>. However, a width of the BPR <NUM> is not limited thereto. Based on the width of the landing pad <NUM> being greater than the width of the BPR <NUM>, aligning and connecting the BPR <NUM> with the landing pad <NUM> may be facilitated during a manufacturing process. In addition, as the landing pad <NUM> is formed prior to providing the BPR <NUM>, the size and shape of the landing pad <NUM> is not limited by shape and size of the BPR <NUM> which may facilitate the manufacturing process of the landing pad <NUM>.

Referring to <FIG>, a wafer-to-wafer bonding process may be carried out. For example, a second wafer <NUM> may be provided on a first surface of the first semiconductor device 200a. The second wafer <NUM> may be bonded to the first semiconductor device 200a by providing an adhesive layer <NUM> between the first semiconductor device 200a and the second wafer <NUM>. However, embodiments are not limited thereto. According to another example embodiment, the second wafer <NUM> may be directly provided on the first semiconductor device 200a. For example, the second wafer <NUM> may be directly bonded to the first semiconductor device 200a by a Si direct bonding without using an adhesive layer. The wafer-to-wafer bonded semiconductor architecture may be flipped.

Referring to <FIG>, the sacrificial layer 100a may be removed, and the etch stop layer <NUM> may be removed to expose the second surface of the carrier substrate 100b. For example, the sacrificial layer 100a and the etch stop layer <NUM> may be removed by a grinding process including, for example, chemical-mechanical polishing (CMP) or dry etching. However, embodiments are not limited thereto.

Referring to <FIG>, a second semiconductor device 200b is provided on the second surface of the carrier substrate 100b. The second semiconductor device 200b is a PDN integrated circuit with, for example, a TSV <NUM> protruding from a first surface of the second semiconductor device 200b. The TSV <NUM> may be formed to penetrate the carrier substrate 100b to contact the landing pad <NUM> based on a location of the landing pad <NUM>. The location of the landing pad <NUM> may be detected based on the preset alignment key, but embodiments are not limited thereto.

The landing pad <NUM> may have a greater width than a width of the TSV <NUM>, but embodiments are not limited thereto. For example, a width of the TSV <NUM> may range around <NUM> to <NUM>. However, a width of the TSV <NUM> is not limited thereto. Based on the width of the landing pad <NUM> being greater than the width of the TSV <NUM>, aligning and connecting the TSV <NUM> to the landing pad <NUM> may be easier. As the TSV <NUM> is better aligned with the landing pad <NUM> which is connected to the BPR <NUM>, the alignment between the TSV <NUM> and the BPR <NUM> may be improved. In addition, even when surfaces of the BPR <NUM> and the TSV <NUM> are not fully in contact with the landing pad <NUM>, the connectivity of the BPR <NUM> and TSV <NUM> may be improved by being connected through the metal landing pad <NUM>.

As illustrated in <FIG>, as the alignment and connectivity between the BPR <NUM> and the TSV <NUM> improves, the resistance of the BSPDN semiconductor architecture <NUM> may be reduced and the IR drop may be improved. In addition, the first semiconductor device 200a and the second semiconductor device 200b may be more accurately aligned and connected with each other to improve the performance of the BSPDN semiconductor architecture <NUM>.

According to the example embodiment, based on the improved alignment between the first semiconductor device 200a and the second semiconductor device 200b, the integration and the performance of the BSPDN semiconductor architecture <NUM> may be improved. In addition, moving the PDN semiconductor device from the first side to the second side of the wafer <NUM> may reduce the size and resistance of the BSPDN semiconductor architecture <NUM>.

<FIG> illustrate a method of manufacturing a BSPDN semiconductor architecture <NUM> according to another example embodiment.

Referring to <FIG>, the method includes providing a wafer <NUM> including a sacrificial layer 100a, an etch stop layer <NUM>, and a carrier substrate 100b. The sacrificial layer 100a may be a Si bulk layer. The etch stop layer <NUM> may be provided on the sacrificial layer 100a. For example, the etch stop layer <NUM> may be provided by an epitaxial growth of silicon germanium (SiGe) on the sacrificial layer100a. However, embodiments are not limited thereto. For example, the etch stop layer <NUM> may be an oxide layer in a silicon-on-insulator (SOI) wafer. The wafer <NUM> may include, for example, a Si substrate, a glass substrate, a sapphire substrate, etc. However, embodiments are not limited thereto.

A trench <NUM> is provided on the carrier substrate 100b. For example, the trench <NUM> may be provided by etching the carrier substrate 100b and may have a rectangular shape from a cross-sectional view. However, embodiments are not limited thereto.

Referring to <FIG>, a TSV etch stop layer <NUM> is provided on a top surface of the carrier substrate 100b and the trench <NUM>. For example, the TSV etch stop layer <NUM> is provided to cover the top surface of the carrier substrate 100b and the trench <NUM>. A metal material <NUM>' is provided on the carrier substrate 100b and the trench <NUM>. The metal material <NUM>' may fill the trench <NUM>. The metal material <NUM>' may be a material having a relatively low resistance such as, for example, Cu, Co, Ru, etc. However, embodiment are not limited thereto. The metal material <NUM>' and the TSV etch stop layer <NUM> may be removed in areas other than the area of a first surface of the trench <NUM> filled with the metal material <NUM>' to form the landing pad <NUM> and to expose the first surface of the carrier substrate 100b. The first surface of the landing pad <NUM> is coplanar to the exposed first surface of the carrier substrate 100b. The metal material <NUM>' and the TSV etch stop layer <NUM> may be removed by a grinding process such as, for example, CMP or dry etching. As the shape of the landing pad <NUM> corresponds to the shape of the trench <NUM>, the landing pad <NUM> may have a rectangular shape. However, embodiments are not limited thereto.

Referring to <FIG>, an encapsulant <NUM> is provided on an area of the landing pad <NUM>. For example, the encapsulant <NUM> may cover the landing pad <NUM> and have a greater size than the landing pad <NUM> from a plan view. The encapsulant <NUM> may include epoxy resin, silica, etc., but materials of the encapsulant <NUM> are not limited thereto. A substrate layer 100b' may be provided on the landing pad <NUM> and the exposed first surface of the carrier substrate 100b. The substrate layer 100b' may be, for example, a Si layer. The substrate layer 100b' may be provided to carry out, for example, a FEOL and a MEOL process. The carrier substrate 100b and the substrate layer 100b' may be integrally formed, and may be together referred to as the carrier substrate 100b.

Referring to <FIG>, a first semiconductor device 200a is provided on a first surface of the carrier substrate 100b. The first semiconductor device 200a is an integrated circuit including components such as, for example, active transistors, signal wires, BPRs <NUM>, etc. The BPR <NUM> may be provided on a first surface of the carrier substrate 100b to be in contact with the landing pad <NUM> based on a location of the landing pad <NUM>. The location of the landing pad <NUM> may be detected based on a preset alignment key, but embodiments are not limited thereto.

The landing pad <NUM> may have a greater width than a width of the BPR <NUM>, but embodiments are not limited thereto. For example, a width of the BPR <NUM> may range from around <NUM> to <NUM>. However, a width of the BPR <NUM> is not limited thereto. Based on the width of the landing pad <NUM> being greater than the width of the BPR <NUM>, aligning and connecting the BPR <NUM> to the landing pad <NUM> may be easier. In addition, as the landing pad <NUM> is formed prior to providing the BPR <NUM>, the size and shape of the landing pad <NUM> is not necessarily limited by the size and shape of the BPR <NUM>, and thus, a manufacturing process of the landing pad <NUM> may be facilitated.

Referring to <FIG>, the sacrificial layer 100a may be removed, and the etch stop layer <NUM> may be removed to expose the second surface of the carrier substrate 100b. For example, the sacrificial layer 100a and the etch stop layer <NUM> may be removed by a grinding process including, for example, CMP or dry etching, but embodiments are not limited thereto.

Referring to <FIG>, a second semiconductor device 200b may be provided on the second surface of the carrier substrate 100b. The second semiconductor device 200b may be a PDN integrated circuit with, for example, a TSV <NUM> protruding from a first surface of the second semiconductor device 200b. The TSV <NUM> may be formed to penetrate the carrier substrate 100b and land on the landing pad <NUM> based on the location of the landing pad <NUM>. The location of the landing pad <NUM> may be detected based on the preset alignment key, but embodiments are not limited thereto.

The landing pad <NUM> may have a greater width than a width of the TSV <NUM>, but embodiments are not limited thereto. For example, a width of the TSV <NUM> may range around <NUM> to <NUM>. However, a width of the TSV <NUM> is not limited thereto. Based on the width of the landing pad <NUM> being greater than the width of the TSV <NUM>, aligning and connecting the TSV <NUM> to the landing pad <NUM> may be easier. As the TSV <NUM> is better aligned with the landing pad <NUM> which is connected to the BPR <NUM>, the alignment between the TSV <NUM> and the BPR <NUM> may be improved. In addition, even when surfaces of the BPR <NUM> and the TSV <NUM> are not fully in contact with the landing pad <NUM>, the connectivity of the BPR <NUM> and TSV <NUM> may be improved based on being connected through the metal landing pad <NUM>.

As illustrated in <FIG>, as the alignment and connectivity between the BPR <NUM> and the TSV <NUM> is improved, the resistance of the BSPDN semiconductor architecture <NUM> may be reduced and the IR drop may be improved. In addition, the first semiconductor device 200a and the second semiconductor device 200b may be more accurately aligned with and connected to each other.

According to the example embodiment, based on the improved alignment between the first semiconductor device 200a and the second semiconductor device 200b, the integration and performance of the semiconductor architecture <NUM> may be improved.

<FIG> illustrates a flowchart of a method of manufacturing a BSPDN semiconductor architecture according to an example embodiment.

According to an example embodiment, a wafer may be provided (S110). The wafer may include a sacrificial layer, an etch stop layer, and a carrier substrate. The sacrificial layer may be a Si bulk layer. The etch stop layer may be provided on the sacrificial layer by an epitaxial growth of silicon germanium (SiGe) on the sacrificial layer, but embodiments are not limited thereto. For example, the etch stop layer may be an oxide layer in a silicon-on-insulator (SOI) wafer. The carrier substrate may include, for example, a Si substrate, a glass substrate, a sapphire substrate, etc..

A landing pad is formed in the wafer (S120). The landing pad may be formed by depositing and patterning a metal material on the carrier substrate, as described in more detail with reference to <FIG> and <FIG>. A substrate is provided on the carrier substrate (S130). The substrate may be a Si layer and may be integrally formed with the carrier substrate.

A first semiconductor device may be provided on the carrier substrate (S140). The first semiconductor device is an integrated circuit including components such as, for example, active transistors, signal wires, and BPRs. The BPR may be provided on a first surface of the carrier substrate to be in contact with the landing pad based on a location of the landing pad.

A second wafer may be provided on the first semiconductor device (S150). The second wafer may be bonded to the first semiconductor device by providing an adhesive layer between the first semiconductor device and the second wafer. According to another example embodiment, the second wafer may be directly provided on the first semiconductor device by, for example, a Si direct bonding without using an adhesive layer. The wafer-to-wafer bonded semiconductor architecture may be flipped.

The sacrificial layer and the etch stop layer may be removed (S150). The etch stop layer may be removed to expose the second surface of the carrier substrate. The sacrificial layer and the etch stop layer may be removed by a grinding process such as, for example, CMP or dry etching, but embodiments are not limited thereto.

A second semiconductor device is provided on the second surface of the carrier substrate (S170). The second semiconductor device is a PDN integrated circuit with a TSV protruding from a first surface of the second semiconductor device. The TSV may be formed to penetrate the carrier substrate to be in contact with the landing pad based on the location of the landing pad.

According to the example embodiment, the alignment and connectivity between the BPR and the TSV may be improved, and the resistance of the BSPDN semiconductor architecture <NUM> may be reduced. In addition, based on the signal wiring device and the PDN being more accurately aligned with each other, performance of the semiconductor architecture may be improved.

<FIG> illustrates a flowchart of a method of manufacturing a landing pad in a semiconductor wafer according to an example embodiment.

Referring to <FIG>, a wafer including a sacrificial layer, an etch stop layer, and a carrier substrate is provided (S210). A TSV etch stop layer is provided on a first surface of the wafer (S220). A metal material is deposited and patterned on the TSV etch stop layer to form a landing pad (S230). The landing pad may have a rectangular shape. An encapsulant is provided on the landing pad and the first surface of the carrier wafer (S240). The encapsulant and the TSV etch stop layer are removed in areas other than in the area covering the first surface and side surfaces of the landing pad (S250). The encapsulant and TSV etch stop layer may be etched to expose the first surface of the wafer. A substrate is provided on the wafer and the landing pad (S260). The substrate may be a Si layer and may be integrally formed with the carrier substrate.

<FIG> illustrates a flowchart of a method of manufacturing a landing pad in a semiconductor wafer according to another example embodiment.

Referring to <FIG>, a wafer including a sacrificial layer, an etch stop layer, and a carrier substrate is provided (S310). A trench is formed in the wafer (S320). The trench may be etched and may have a rectangular shape. A TSV etch stop layer is provided on the first surface of the wafer and the trench (S330). A metal material may be provided on the first surface of the wafer and fill the trench (S340). The metal material and the TSV etch stop layer may be removed in areas other than the area of a first surface of the trench filled with the metal material to form the landing pad (S350). The metal material and the TSV etch stop layer may be removed by, for example, CMP or dry etching. An encapsulant is provided on an area of the landing pad (S360). A size of the encapsulant may be greater than a size of the landing pad from a plan view. A substrate is provided on the wafer and the landing pad (S370). The substrate may be a Si layer and may be integrally formed with the carrier substrate.

According to example embodiments, as the landing pad is formed prior to the integration of the semiconductor devices on the wafer, manufacturing of the landing pad may be facilitated. For example, a size and shape of the landing pad may not be limited by a size and shape of components of the semiconductor devices such as, for example, a BPR, a TSV, etc..

<FIG> illustrates a semiconductor package that may incorporate the BSPDN semiconductor architectures according to example embodiments.

Referring to <FIG>, a semiconductor package <NUM> according to an example embodiment may include a processor <NUM> and semiconductor devices <NUM> that are mounted on a substrate <NUM>. The processor <NUM> and/or the semiconductor devices <NUM> may include one or more of BSPDN semiconductor architecture <NUM> described in the above example embodiments.

<FIG> illustrates a schematic block diagram of an electronic system which may include one or more of BSPDN semiconductor architecture <NUM> described in the above example embodiments.

Referring to <FIG>, an electronic system <NUM> in accordance with an embodiment may include a microprocessor <NUM>, a memory <NUM>, and a user interface <NUM> that perform data communication using a bus <NUM>. The microprocessor <NUM> may include a central processing unit (CPU) or an application processor (AP). The electronic system <NUM> may further include a random access memory (RAM) <NUM> in direct communication with the microprocessor <NUM>. The microprocessor <NUM> and/or the RAM <NUM> may be implemented in a single module or package. The user interface <NUM> may be used to input data to the electronic system <NUM>, or output data from the electronic system <NUM>. For example, the user interface <NUM> may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, a lighting, or various other input/output devices without limitation. The memory <NUM> may store operational codes of the microprocessor <NUM>, data processed by the microprocessor <NUM>, or data received from an external device. The memory <NUM> may include a memory controller, a hard disk, or a solid state drive (SSD).

At least the microprocessor <NUM>, the memory <NUM> and/or the RAM <NUM> in the electronic system <NUM> may include BSPDN semiconductor architecture <NUM> as described in the above example embodiments.

It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation.

Claim 1:
A semiconductor architecture comprising:
a wafer (<NUM>);
a landing pad (<NUM>) included in the wafer (<NUM>);
an integrated circuit for signal routing (200a) provided on a first surface of the wafer (<NUM>), the integrated circuit for signal routing (200a) comprising a buried power rail, BPR, (<NUM>) provided on the landing pad (<NUM>);
a power distribution network, PDN, integrated circuit (200b) provided on a second surface of wafer (<NUM>); and
a through-silicon via, TSV, (<NUM>) protruding from the PDN integrated circuit (200b) being provided on the landing pad (<NUM>), the landing pad (<NUM>) being provided between the BPR (<NUM>) and the TSV (<NUM>); and
characterized by further comprising:
a TSV etch stop layer (<NUM>) provided between the landing pad (<NUM>) and the TSV (<NUM>); and
an encapsulant (<NUM>) provided between the landing pad (<NUM>) and the BPR (<NUM>).