Patent Description:
"<NPL>, discusses two constructions for the Toffoli gate which reduce resource costs in fault-tolerant quantum computing.

The subject matter of the present specification relates to technologies for producing quantum circuits, such as quantum circuits with low T gate counts.

According to an aspect of the present invention, there is provided a method for performing a temporary logical AND operation on two control qubits comprising the features of claim <NUM>.

According to another aspect of the present invention, there is provided a quantum computing device comprising the features of claim <NUM>.

Details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below.

The surface code is a quantum error correcting code that may operate on a two dimensional (2D) nearest-neighbor array of qubits and achieve a threshold error rate of approximately <NUM>%. This makes the surface code a likely component in the architecture of future error corrected quantum computers, since 2D arrays of qubits with nearest-neighbor connections may be implemented using many qubit technologies and other known error correcting codes have lower thresholds or require stronger connectivity.

One downside of the surface code is that it has no cheap mechanism to apply non-Clifford operations such as T gates that perform <NUM> degree rotations around the Z axis of the Bloch sphere. Instead, T gates are performed by distilling and consuming |A > = <MAT>) states. Consuming an |A〉 state to perform a T gate is simple, but distilling |A〉 states has significant cost. Because T gates are so expensive for the surface code, and the surface code is a likely component of future quantum computers, it may be advantageous to reduce the number of T gates used by quantum circuits to perform certain quantum computing operations.

This specification describes methods and constructions that may be implemented in a quantum circuit on a quantum device for improving the number of T gates needed to perform a first Toffoli gate that is later un-computed by a second Toffoli gate. The first Toffoli gate is performed indirectly by targeting a clean ancilla qubit and then using the ancilla qubit to toggle the intended target. The ancilla qubit is not un-computed and re-computed if it will be provided as a resource for additional operations. If a T gate is used to compute or un-compute an |A〉 state, an |A〉 state is passed in or recovered. The ancilla qubit is un-computed by measurement of the ancilla qubit and application of a classically controlled operation (also described as a measure-and-correct process herein).

In this specification, initializing the ancilla qubit is referred to as "computing the logical-AND of the controls", un-computing the ancilla qubit as "erasing the logical-AND", and the combination of both pieces as a "temporary AND gate".

<FIG> is a circuit representation <NUM> of a Toffoli construction. A Toffoli gate is a universal reversible quantum logic gate. A Toffoli gate acts on three qubits. If the first two qubits are in the state |<NUM>>, the Toffoli gate <NUM> flips the state of the third qubit and otherwise leaves it unchanged. In <FIG>, the Toffoli gate <NUM> acts on three qubits represented by the three parallel horizontal lines <NUM>, <NUM> and <NUM>. In <FIG>, qubits <NUM> and <NUM> represent control qubits, and qubit <NUM> represents a target qubit. A Toffoli gate can be implemented using the construction <NUM>. The construction <NUM> includes eight Clifford gates - Controlled-NOT (CNOT) gates, e.g., CNOT gate <NUM>, and Hadamard gates, e.g., Hadamard gate <NUM>. The expanded circuit representation <NUM> includes seven T gates, e.g., T gate <NUM> and <NUM>.

Under the assumption that the construction <NUM> is not permitted to involve other qubits or to share work with other operations, this construction was previously considered optimal. Otherwise, the construction may be optimized. For example, in cases where N adjacent Toffoli gates share the same control qubits, the multiple Toffoli gates may be replaced by N-<NUM> CNOT gates and one Toffoli gate. The T-count of N adjacent Toffoli gates sharing the same controls is therefore <NUM>·N+O(<NUM>), where the marginal T-count is zero because each additional Toffoli can be replaced with CNOTs framing a root Toffoli.

It may not be common for adjacent Toffoli gates to have the same control qubits, however it may be common for a first Toffoli to later be un-computed by a second matching Toffoli, that is for the effect of the first Toffoli gate to be temporary. When this occurs, the three T gates on the control qubits of the construction shown above with reference to <FIG> can be omitted. In some cases, this may introduce phase errors. However the second Toffoli gate can un-compute those errors while un-computing the state permutation.

Based on the Toffoli gate construction described with reference to <FIG>, an n-bit quantum adder may contain <NUM>n+O(<NUM>) Toffoli gates, which in turn implies a naive T-count of <NUM>n+O(<NUM>). However, almost all of the Toffoli gates in the first half of an adder are un-computed by Toffoli gates in the second half. This allows the T gates on the controls of the Toffoli gates to be omitted, reducing their T-count from <NUM> to <NUM> and the T-count of addition to <NUM>n+O(<NUM>). Even if a Toffoli is not paired with a second Toffoli that un-computes its effects, it is still possible to perform the Toffoli with T-count of <NUM> by using an ancilla qubit, a measurement, and a conditional fixup operation.

<FIG> depicts an exemplary system <NUM> for implementing temporary Toffoli gates and logical AND operations. The system <NUM> is an example of a system implemented as quantum or classical computer programs on one or more quantum computing devices or classical computers in one or more locations, in which the systems, components, and techniques described below can be implemented.

The system <NUM> includes a quantum computing device <NUM> in data communication with one or more classical processors <NUM>. The quantum computing device <NUM> includes components for performing quantum computation. For example, the quantum computing device <NUM> includes a quantum system <NUM>, control devices <NUM>, and T factories <NUM>. The quantum system <NUM> includes one or more multi-level quantum subsystems, e.g., a register of qubits. In some implementations the multi-level quantum subsystems may be superconducting qubits, e.g., Gmon qubits. The type of multi-level quantum subsystems that the system <NUM> utilizes may vary. For example, in some cases it may be convenient to include one or more resonators attached to one or more superconducting qubits, e.g., Gmon or Xmon qubits. In other cases ion traps, photonic devices or superconducting cavities (with which states may be prepared without requiring qubits) may be used. Further examples of realizations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots or phosphorus impurity qubits.

Quantum circuits may be constructed and applied to the register of qubits included in the quantum system <NUM> via multiple control lines that are coupled to multiple control devices <NUM>. Example control devices <NUM> that operate on the register of qubits include quantum logic gates or circuits of quantum logic gates, e.g., Hadamard gates, controlled-NOT (CNOT) gates, controlled-phase gates, or T gates. In some implementations T gates may be stored in one or more T factories <NUM> included in the quantum computing device <NUM>.

The control devices <NUM> may further include measurement devices, e.g., readout resonators. Measurement results obtained via measurement devices may be provided to the classical processors <NUM> for processing and analyzing.

One innovative aspect of present disclosure describes a construction that improves the T-count of a single Toffoli gate by performing the Toffoli indirectly instead of directly.

<FIG> is a flow diagram of an example process <NUM> for indirectly performing a Toffoli gate on two control qubits and a target qubit. For convenience, the process <NUM> will be described as being performed by a quantum computing device in communication with one or more classical computing devices located in one or more locations. For example, the system <NUM> of <FIG>, appropriately programmed in accordance with this specification, can perform the process <NUM>.

The system obtains an ancilla qubit in an A-state (step <NUM>).

The system computes a logical-AND of the two control qubits and stores the computed logical-AND in the state of the ancilla qubit by replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits (step <NUM>). To compute a logical-AND of the two control qubits and store the computed logical-AND in the state of the ancilla qubit, the system may first apply a CNOT gate between the ancilla qubit in the |A> state and a first control qubit. The system may then apply the Hermitian conjugate of a T gate to the ancilla qubit. The system may then apply a CNOT gate between the ancilla qubit and a second control qubit. The system may then apply a T gate to the ancilla qubit. The system may then apply a CNOT gate between the ancilla qubit and the first control qubit. The system may then apply the Hermitian conjugate of a T gate to the ancilla qubit. The system may then apply a Hadamard gate to the ancilla qubit to store the logical AND of the two control qubits in the state of the ancilla qubit. An example circuit representation of computing a logical-AND of two control qubits and storing the computed logical-AND in the state of an ancilla qubit is illustrated below with reference to <FIG>.

In some implementations the computation performed in step <NUM> may introduce phase errors. Such phase errors may be corrected by applying a controlled-S quantum logic gate to the two control qubits. The effect of an application of a controlled-S gate S = diag(<NUM>, eiπ/<NUM>) to the two control qubits is to apply a phase factor of i to the amplitudes of computational basis states where both controls are on. Since the output of the step <NUM> is a qubit whose state indicates whether or not both control qubits are on, the controlled-S gate on the two control qubits can be replaced with an uncontrolled-S gate on the ancilla qubit storing the logical-AND of the two control qubits.

The system applies a CNOT quantum logic gate between (i) the ancilla qubit storing the logical-AND of the two control qubits, and (ii) the target qubit, the ancilla qubit acting as a control qubit for the CNOT quantum logic gate (step <NUM>).

The system provides the ancilla qubit storing the logical-AND of the two control qubits as a resource for one or more additional operations (step <NUM>).

The system un-computes the logical-AND of the two control qubits and recovers the A-state of the ancilla qubit by replacing the state of the ancilla qubit storing the computed logical-AND of the two control qubits with an A-state (step <NUM>).

For example, the system may apply a Hadamard gate to the ancilla qubit storing the logical-AND of the two control qubits. The system may then apply a T gate to the ancilla qubit. The system may then apply a CNOT gate between the ancilla qubit and a first control qubit. The system may then apply the Hermitian conjugate of a T gate to the ancilla qubit. The system may then apply a CNOT gate between the ancilla qubit and a second control qubit. The system may then apply a T gate to the ancilla qubit. The system may then apply a CNOT gate between the ancilla qubit and the first control qubit to leave the ancilla qubit in an |A> state. An example circuit representation of un-computing a logical-AND of two control qubits and recovering an A-state of an ancilla qubit is illustrated below with reference to <FIG>.

In cases where the system applies an S gate during the computation of the logical AND described above with reference to step <NUM>, the system may apply the Hermitian adjoint of the S gate prior to applying the first Hadamard gate to the ancilla qubit storing the logical AND of the two control qubits.

The system provides the ancilla qubit in the recovered A-state as a resource for one or more additional operations (step <NUM>). For example, the system may provide the ancilla qubit in the A-state to perform a T gate.

In some implementations a first iteration of the process <NUM> may be used to perform a first temporary Toffoli quantum logic gate on two first control qubits and a first target qubit. The system may then provide the ancilla qubit in the recovered A-state as a resource for a second iteration of the process <NUM> on two second control qubits and a second target qubit.

<FIG> is an illustration <NUM> of an example quantum circuit for indirectly performing a Toffoli gate <NUM> on two control qubits and a target qubit, as described above with reference to process <NUM> of <FIG>. In illustration <NUM>, a first control qubit of the two control qubits is represented by horizontal line <NUM>. A second control qubit of the two control qubits is represented by horizontal line <NUM>. Horizontal line <NUM> represents the target qubit.

To perform the Toffoli gate <NUM> on the two control qubits <NUM>, <NUM> and target qubit <NUM>, an ancilla qubit, represented by horizontal line <NUM>, in an A-state <NUM> is obtained. For example, the ancilla qubit <NUM> may be prepared in a <NUM>-state. A Hadamard gate and T gate may be applied to the ancilla qubit in the <NUM>-state to obtain the A-state.

The logical AND of the two control qubits <NUM>, <NUM> is computed <NUM> and stored in the state of the ancilla qubit <NUM>. This includes application of: a CNOT gate <NUM> between the ancilla qubit <NUM> in the |A> state and the first control qubit <NUM>, the Hermitian conjugate of a T gate <NUM> to the ancilla qubit <NUM>, a CNOT gate <NUM> between the ancilla qubit <NUM> and the second control qubit <NUM>, a T gate <NUM> to the ancilla qubit <NUM>, a CNOT gate <NUM> between the ancilla qubit <NUM> and the first control qubit <NUM>, the Hermitian conjugate of a T gate <NUM> to the ancilla qubit <NUM>, and a Hadamard gate <NUM> to the ancilla qubit <NUM>.

A CNOT quantum logic gate <NUM> is applied to (i) the ancilla qubit <NUM> storing the logical-AND of the two control qubits <NUM>, <NUM>, and (ii) the target qubit <NUM>, the ancilla qubit <NUM> acting as a control qubit for the CNOT quantum logic gate <NUM>.

The logical AND of the two control qubits <NUM>, <NUM> is un-computed <NUM>. This includes application of: a Hadamard gate <NUM> to the ancilla qubit <NUM> storing the logical-AND of the two control qubits <NUM>, <NUM>, a T gate <NUM> to the ancilla qubit <NUM>, a CNOT gate <NUM> between the ancilla qubit <NUM> and the first control qubit <NUM>, the Hermitian conjugate of a T gate <NUM> to the ancilla qubit <NUM>, a CNOT gate <NUM> between the ancilla qubit <NUM> and the second control qubit <NUM>, a T gate <NUM> to the ancilla qubit <NUM>, and a CNOT gate <NUM> between the ancilla qubit <NUM> and the first control qubit <NUM>. The ancilla qubit <NUM> may be returned to the <NUM>-state by application of the Hermitian conjugate of a T gate <NUM> and a Hadamard gate <NUM>.

The indirect-Toffoli construction described with reference to <FIG> and <FIG> appears to have a T-count of <NUM>. However, the last T gate <NUM> in the circuit is unnecessary. In fact, in some cases it may be actively harmful. By removing the T gate <NUM> and the following Hadamard <NUM>, the T-count of the Toffoli gate is reduced from <NUM> to <NUM>. In addition, the ancilla qubit is left in an |A〉 state that can be consumed to perform a T gate elsewhere. This improves the net T-count of the Toffoli gate to <NUM>.

This optimization construction may apply to multiple quantum circuits. For example, the optimization may be useful in circuits where an initial Toffoli gate is later un-computed by a second Toffoli gate. Instead of computing and un-computing the ancilla qubit for the first Toffoli gate, then re-computing and re-un-computing the ancilla qubit for the second Toffoli gate, the ancilla qubit may be maintained until the second Toffoli gate is un-computed. This halves the T-count of the pair from <NUM> to <NUM>, as illustrated in <FIG>.

<FIG> is an illustration <NUM> of an example quantum circuit for computing and un-computing multiple Toffoli gates <NUM> on two control qubits <NUM>, <NUM> and a target qubit <NUM> using an ancilla qubit <NUM>. As shown in illustration <NUM>, maintaining the ancilla qubit until Toffoli gate <NUM> is un-computed results in a net T-count of <NUM>. Many circuits involve computing and later un-computing a Toffoli, e.g., due to addition operations. Previously, it was believed that each Toffoli gate had a T-count of <NUM>, the pair of Toffoli gates therefore having a T-count of <NUM>. The process and construction described in <FIG> and <FIG> reduces the T-count of the pair from <NUM> to <NUM>.

<FIG> is a flow diagram of an example process <NUM> for performing a temporary logical AND operation on two control qubits. For convenience, the process <NUM> will be described as being performed by a quantum computing device in communication with one or more classical computing devices located in one or more locations. For example, the system <NUM> of <FIG>, appropriately programmed in accordance with this specification, can perform the process <NUM>.

The system computes a logical-AND of the two control qubits and stores the computed logical-AND in the state of the ancilla qubit by replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits (step <NUM>). In some implementations, to correct any introduced phase errors, the system may further apply an uncontrolled-S gate to the ancilla qubit. As described above with reference to <FIG>, computing the logical-AND of the two control qubits includes applying three T gates, optionally approximately in parallel.

The system maintains the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied (step <NUM>). In some implementations maintaining the ancilla qubit storing the logical-AND of the two control qubits may include providing the ancilla qubit as a resource for one or more additional operations, e.g., operations that would otherwise be conditioned on the two control qubits.

The system erases the ancilla qubit when the first condition is satisfied (step <NUM>). For example, the system may erase the ancilla qubit when the one or more additional operations described above with reference to step <NUM> have been performed. In some implementations erasing the ancilla qubit may include transitioning the ancilla qubit into a state that is independent of the state of the two control qubits and does not cause the two control qubits to decohere.

To erase the ancilla qubit, the system may apply a measure-and-correct process that includes one or more Clifford operations (with no T-count) instead of un-computing the ancilla qubit using a mirror of the process used to compute the ancilla qubit. By starting with a process that obviously performs the un-computation, e.g., as described above with reference to <FIG>, the process can be altered to generate the measure-and-correct process. The un-computation process described in <FIG> includes a Toffoli gate, which clears the ancilla qubit since the ancilla qubit was computed with a Toffoli gate and Toffoli gates are their own inverse. Since the cleared ancilla qubit is eventually discarded, it is possible to apply a Hadamard gate and a measurement to it after the Toffoli gate but before discarding it. The Hadamard may then be hopped over the Toffoli gate, transforming it into a CCZ operation. The CCZ may be rearranged so that the ancilla qubit is one a control qubit, which is possible because the control qubits and target qubit of a CCZ are interchangeable. Finally, the deferred measurement principle may be invoked to hop the measurement over the CCZ, turning the quantum control into a classical control. That is, to perform the measure-and-correct process the system may apply a Hadamard quantum logic gate to the ancilla qubit, measure the ancilla qubit to generate a measurement result and analyze the generated measurement result. In response to determining that the generated measurement result indicates that the two control qubits are both ON, the system may apply a CZ gate to the control qubits.

<FIG> is an illustration <NUM> of an example quantum circuit for performing a temporary logical AND operation <NUM> on two control qubits <NUM>, <NUM>. As shown in illustration <NUM>, the computation of the logical AND gate is drawn as an ancilla qubit wire <NUM> emerging vertically from two controls then heading rightward.

Performing the temporary logical AND operation <NUM> includes obtaining an ancilla qubit <NUM> in an A-state, applying a CNOT gate <NUM> between the first control qubit <NUM> and the ancilla qubit <NUM>, applying a CNOT gate <NUM> between the second control qubit <NUM> and the ancilla qubit <NUM>, applying two CNOT gates <NUM> between the first control qubit <NUM>, second control qubit <NUM> and ancilla qubit <NUM> (the order of which is irrelevant), applying a Hermitian conjugate of a T gate <NUM>, <NUM> to the first control qubit <NUM> and to the second control qubit <NUM> and a T gate <NUM> to the ancilla qubit <NUM> (the T gates <NUM>, <NUM>, <NUM> may be applied approximately in parallel), applying two CNOT gates <NUM> between the first control qubit <NUM>, second control qubit <NUM> and ancilla qubit <NUM> (the order of which is irrelevant), applying a Hadamard gate <NUM> to the ancilla qubit <NUM> and, optionally, applying a S gate <NUM> to the ancilla qubit <NUM>. The T count of the operation <NUM> is therefore <NUM> (including the T gate required to prepare the A-state of the ancilla qubit <NUM>).

<FIG> is an illustration <NUM> of an example quantum circuit for un-computing a temporary logical AND operation <NUM> on two control qubits <NUM>, <NUM>. As shown in illustration <NUM>, the un-computation of the logical AND gate <NUM> is drawn as an ancilla qubit wire <NUM> coming in from the left then merging vertically into the two control qubits <NUM>, <NUM> that created it.

Un-computing the temporary logical AND operation <NUM> includes performing a measure-and-correct process. A Hadamard gate <NUM> is applied to the ancilla qubit <NUM>. The ancilla qubit <NUM> is measured <NUM>. A CZ gate <NUM> is applied to the control qubits <NUM>, <NUM> if the generated measurement result from measurement operation <NUM> indicates that the two control qubits <NUM>, <NUM> are both ON. The T count of the operation <NUM> is zero.

The above described processes and constructions may be used improve the complexity of several quantum circuits. For example, known adder constructions such as the Cuccaro adder contain many Toffoli gates that are later un-computed by another Toffoli. The presently described processes and constructions do not fundamentally change the structure of such known adders. Therefore, an improved adder construction based on temporary Toffoli gates may be synthesized using the above described temporary AND gate construction, halving the T count of the adder.

<FIG> illustrates a per-bit building block <NUM> of an improved adder construction with a T count of <NUM>. The building block <NUM> may be used as part of a ripple-carry approach to performing addition, and can be used to construct an n-bit adder by nesting n copies of the building block <NUM> inside of each other. The compute carry bit box <NUM> represents computation of the majority of the three input bits ck, ik, tk, that is whether or not the sum of the three bits will cause a carry into the next bit k+<NUM>, and storing of the computed majority into the new wire that will feed into the next bit's k+<NUM> adder. The un-compute carry bit box <NUM> represents the inverse operations of the majority computed in the compute carry bit box <NUM>, as well as operations for ensuring that the output bit has been toggled if the input bit is on.

<FIG> is an illustration a <NUM> bit adder with a T count of <NUM>, constructed by tiling the per-bit building block <NUM> shown in <FIG>. Since the low bit corresponding to does not have a carry-in, the circuit has been optimized to omit that part. Also, since the high bit doesn't have a carry-out, that has also been optimized to omit that part. The bits corresponding to the input register are labelled i0, i1, i2, i3, i4. The target bits are labelled t0, t1, t2, t3, t4. After the circuit has been performed, the target bits have been modified such that the target register's new value is the sum of the input and the target register's old value, e.g., (t +i)<NUM>.

The building block <NUM> for the improved adder construction can be modified such that the sum computed by the adder can be made available for use as soon as the carry signal hits the first control bit - instead of needing to wait for the un-computation sweep to finish. This can halve the T-count of the addition when it is going to be un-computed. Instead of using 4n+O(<NUM>) T gates to compute the addition, and then 4n+O(<NUM>) more T gates to un-compute the addition, the intermediate state of a single addition computation is utilized.

Furthermore, in some cases additions may be conditioned on a control qubit, e.g., additions performed in Shor's algorithm. In some cases a controlled-addition construction may have a T-count of 21n+O(<NUM>). Using the presently described temporary AND gate construction can improve this to 8n+O(<NUM>).

The presently described temporary AND gate may also be applicable to other operations. For example, temporary AND operations can be useful for applying phase rotations to multiple qubits approximately simultaneously. Given a b-bit ancilla register G prepared in the state <MAT> (a 'phase gradient state'), using the adder construction described above to add a register Q into G will cause phase kickback that applies the operation <MAT> to Q. The Grad operation is equivalent to applying the phase gate Z<NUM>-k to the qubit position at k for each qubit within Q. Since some quantum Fourier transform circuits involve conditional uses of Grad, temporary-AND operations may be used to improve the T-count of those circuits.

In some cases it may be estimated that factoring a <NUM>-bit number may take <NUM> hours and <NUM> x <NUM><NUM> distilled |A〉 states. This time estimate is based on each Toffoli having a T-depth of <NUM>, and the |A〉 state count estimate is based on Toffoli gates having a T-count of <NUM>. The presently described processes and constructions reduce many existing estimates of the cost of quantum computation, improving the computational efficiency of quantum computations. For example, because Shor's algorithm is dominated by the cost of additions, the presently described techniques multiply the T-count and T depth for factoring a <NUM>-bit number by <NUM>/<NUM> and <NUM>/<NUM>, respectively. This reduces the estimates to <NUM> hours and <NUM> x <NUM><NUM> distilled |A〉 states.

Other examples of operations implemented by quantum devices which benefit from cheaper temporary AND gates include but are not limited to: integer comparisons, integer multiplication, incrementing and counting, integer arithmetic in general, modular arithmetic, expanding a binary register into a unary register, operations with a target qubit indexed by a binary qubit register, phasing a register by a computable function f (i.e. applying the operation), temporary permutations, or oracles in Grover's algorithm.

Implementations of the digital and/or quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-embodied digital and/or quantum computer software or firmware, in digital and/or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

Implementations of the digital and/or quantum subject matter described in this specification can be implemented as one or more digital and/or quantum computer programs, i.e., one or more modules of digital and/or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The digital and/or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal that is capable of encoding digital and/or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and/or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

The term "data processing apparatus" refers to digital and/or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and/or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and/or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A digital and/or quantum computer program may, but need not, correspond to a file in a file system. A digital and/or quantum computer program can be deployed to be executed on one digital or one quantum computer or on multiple digital and/or quantum computers that are located at one site or distributed across multiple sites and interconnected by a digital and/or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

The processes and logic flows described in this specification can be performed by one or more programmable digital and/or quantum computers, operating with one or more digital and/or quantum processors, as appropriate, executing one or more digital and/or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and/or quantum computers.

For a system of one or more digital and/or quantum computers to be "configured to" perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more digital and/or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by digital and/or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

Digital and/or quantum computers suitable for the execution of a digital and/or quantum computer program can be based on general or special purpose digital and/or quantum processors or both, or any other kind of central digital and/or quantum processing unit. Generally, a central digital and/or quantum processing unit will receive instructions and digital and/or quantum data from a read-only memory, a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof.

The essential elements of a digital and/or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and/or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a digital and/or quantum computer will also include, or be operatively coupled to receive digital and/or quantum data from or transfer digital and/or quantum data to, or both, one or more mass storage devices for storing digital and/or quantum data, e.g., magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information. However, a digital and/or quantum computer need not have such devices.

Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Control of the various systems described in this specification, or portions of them, can be implemented in a digital and/or quantum computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more digital and/or quantum processing devices.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of the appended claims, but rather as descriptions of features that may be specific to particular implementations. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Claim 1:
A method for performing a temporary logical AND operation (<NUM>) on two control qubits (<NUM>, <NUM>), the method being implemented in a quantum device comprising a register of qubits, a plurality of control lines coupled to the register of qubits, a plurality of control devices, wherein each control device comprises one or more control circuits that are coupled to the plurality of control lines, the register of qubits comprising the two control qubits and an ancilla qubit (<NUM>) having an initial state, the method comprising:
computing (<NUM>), by at least one of the plurality of control devices, a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, thereby replacing the initial state of the ancilla qubit with the logical-AND of the two control qubits;
using, by at least one of the plurality of control devices, the ancilla qubit storing the logical-AND of the two control bits as a control qubit for one or more additional operations; and
erasing (<NUM>), by at least one of the plurality of control devices that includes at least one measurement device, the ancilla qubit, when the one or more additional operations have been performed, by applying a measure-and-correct process configured to un-compute the ancilla qubit;
wherein computing the logical-AND of the two control qubits comprises applying one T gate (<NUM>, <NUM>) to each of the two control qubits and applying one T gate (<NUM>) to the ancilla qubit; and
wherein the measure-and-correct process has a T gate count of zero and comprises:
applying a Hadamard quantum logic gate (<NUM>) to the ancilla qubit;
measuring the ancilla qubit to generate a measurement result;
in response to determining that the generated measurement result indicates that the two control qubits are both ON, applying a CZ gate to the two control qubits.