Patent Description:
As an example, servers in a data center are increasingly consuming large amounts of power. The consumption of power is partly the result of power loss from the dissipation of energy even when the CMOS circuits are inactive. This is because even when such circuits are inactive, and are not consuming any dynamic power, they still consume power because of the need to maintain the state of CMOS transistors. In addition, because CMOS circuits are powered using DC voltage, there is a certain amount of current leakage even when the CMOS circuits are inactive. Thus, even when such circuits are not processing information, a certain amount of power is wasted not only as a result of the requirement to maintain the state of the CMOS transistors, but also as a result of the current leakage.

An alternative approach to the use of processors and related components, based on CMOS technology, is the use of superconducting logic based circuits. <NPL> describes that a quantum-accurate waveform with an rms output amplitude of <NUM> V has been synthesized for the first time. This fourfold increase in voltage over previous systems was achieved through developments and improvements in bias electronics, pulse-bias techniques, Josephson junction array circuit fabrication, and packaging. A recently described ac-coupled bipolar pulse-bias technique was used to bias a superconducting integrated circuit with <NUM><NUM> junctions, which are equally divided into four series-connected arrays, into the second quantum state. The authors describe these advancements and present the measured <NUM> V spectra for <NUM> and <NUM> sine waves that remained quantized over a <NUM> mA current range. The authors also demonstrate a <NUM> sine wave produced with another bias technique that requires no compensation current and remains quantized at an rms voltage of <NUM> mV over a <NUM> mA current range. Increasing the clock frequency to <NUM> also allowed the authors to achieve a maximum rms output voltage for a single array of <NUM> mV.

In one example, the present disclosure relates to a superconducting integrated circuit comprising a first clock line coupled via a first capacitor to a first superconducting circuit comprising a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit. The superconducting integrated circuit further comprises a second clock line coupled via a second capacitor to a second superconducting circuit comprising a second Josephson junction, where the second capacitor is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit, where the second phase is different from the first phase.

Examples described in this disclosure relate to capacitively coupled superconducting integrated circuits powered using alternating current (AC). Certain examples described in this disclosure relate to reciprocal quantum logic (RQL) circuits that may be implemented using wave pipelined logic or phase-mode logic. Such RQL circuits may act as low-power superconductor logic circuits.

Unlike CMOS transistors, the RQL circuits are superconductor circuits that use Josephson junction based devices. An exemplary Josephson junction may include two superconductors coupled via a region that impedes current. The region that impedes current may be a physical narrowing of the superconductor itself, a metal region, or a thin insulating barrier. As an example, the Superconductor-Insulator-Superconductor (SIS) type of Josephson junctions may be implemented as part of the RQL circuits. As an example, superconductors are materials that can carry a direct electrical current (DC) in the absence of an electric field. Such materials have almost zero resistance at or below their critical temperature. One example superconductor, niobium, has a critical temperature (Tc) of <NUM> Kelvin. At temperatures below Tc, niobium is superconductive; however, at temperatures above Tc, it behaves as a normal metal with electrical resistance. Thus, in the SIS type of Josephson junctions, superconductors may be niobium superconductors and insulators may be Al<NUM>O<NUM> barriers. In SIS type of junctions, when a wave function tunnels through the barrier, a changing phase difference in time in the two superconductors creates a potential difference between the two superconductors. In RQL circuits, in one example, the SIS type of junction may be part of a superconducting loop. When the potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer multiple of a single quantum of magnetic flux. The voltage pulse associated with the single quantum of magnetic flux is referred to as a single-flux-quantum (SFQ) pulse. As an example, overdamped Josephson junctions can create individual single-flux-quantum (SFQ) pulses. In RQL circuits, each Josephson junction may be part of one or more superconducting loops. The phase difference across the junction may be modulated by the magnetic flux applied to the loop.

Various RQL circuits, including transmission lines, can be formed by coupling multiple Josephson junctions by inductors or other components, as needed. SFQ pulses can travel via these transmission lines under the control of at least one clock. The SFQ pulses can be positive or negative. As an example, when a sinusoidal bias current is supplied to a junction, then both positive and negative pulses can travel rightward, during opposite clock phases, on a transmission line. The RQL circuits may advantageously have zero static power dissipation because of the absence of bias resistors. In addition, the RQL circuits may be powered using alternating current (AC) power, thereby eliminating the ground return current. The AC power supply may also act as a stable clock reference signal for the RQL circuits. In one example, the digital data may be encoded using a pair of positive and negative (reciprocal) SFQ pulses. As an example, a logical one bit may be encoded as a reciprocal pair of SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logical zero bit may be encoded by the absence of positive/negative pulse pairs during a clock cycle. The positive SFQ pulse may arrive during the positive part of the clock, whereas the negative pulse may arrive during the negative part of the clock.

The building blocks of exemplary RQL circuits may include various types of logic gates. Exemplary logic gates include an AND gate, an OR gate, a logical A-and-not-B gate and a logical AND/OR gate. The A-and-not-B gate may have two inputs and one output. An input pulse A may propagate to the output when favorable clock conditions may be present on an output Josephson transmission line (JTL), unless an input pulse B comes first with respect to either input pulse A or the favorable clock conditions on the output JTL. The logical behavior of the gate is based on the reciprocal data encoding mentioned earlier. As an example, a positive pulse changes the internal flux state of the inductive loop, but the trailing negative pulse erases the internal state every clock cycle, which in turn produces combinational logic behavior.

Certain examples described in this disclosure relate to the use of capacitors to couple AC power to superconducting circuits including Josephson junctions. The capacitors are selected to have a smaller capacitance compared to the capacitance of a Josephson junction device so as not to load the superconducting circuit. The smaller size of the capacitors relative to transformers that are used for inductively coupling AC power to such superconducting circuits may advantageously allow the technology to scale to smaller feature sizes and larger integrated circuit die. In addition, the use of capacitive coupling to superconducting circuits, such as RQL circuits may further improve these circuits for several reasons. As an example, capacitive coupling may increase the performance of the superconducting circuits because of faster Josephson junction switching. In addition, because capacitors are easier to fabricate than transformers the fabrication complexity may be reduced. Moreover, the elimination of the bias inductors and the associated DC flux bias may further reduce the area required for supplying AC power to the superconducting circuits. Additionally, the use of capacitors in the clock network may result in less dissipation of energy, particularly at high frequencies. Also, as explained later, the use of capacitors to couple AC power may enable full-data rate for phase-mode logic circuits using bipolar bias. Alternatively, an AC clock that is a multiple of the data rate may be used for low-latency phase-mode logic circuits. Finally, the use of capacitive coupling may support a wider range of data encoding schemes, including unipolar single-flux quantum (SFQ) pulses and multiple SFQ pulses per clock cycle.

<FIG> is a diagram of a superconducting integrated circuit <NUM> including circuits that are capacitively coupled to clock lines in accordance with one example. Superconducting integrated circuit <NUM> may include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the CLOCK I terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the CLOCK Q terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the CLOCK -I terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the CLOCK -Q terminal. Data input may be received via the DATA terminal that may be coupled to superconducting circuit <NUM> via an inductor <NUM>. Superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and a ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N1. The node N1 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

With continued reference to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N2. The node N2 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

Still referring to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N3. The node N3 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

With continued reference to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N4. The node N4 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees. Although <FIG> shows a certain number of components of superconducting integrated circuit <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently. As an example, although <FIG> shows a schematic of a shift register circuit, superconducting integrated circuit <NUM> may be any other type of circuit, such as a logic gate, a flip-flop, or a memory circuit. In addition, although <FIG> shows a phase separation of <NUM> degrees and four clock lines, a phase separation of <NUM> degrees and three clock lines may also be used. Moreover, although <FIG> shows certain phase values associated with the clock lines, the clock lines need not receive clock signals with the phase value shown in <FIG>. As an example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Other phase allocations may also be used.

In terms of the operation of superconducting integrated circuit <NUM>, each clock line may receive the respective AC clock signal and provide a respective bias current to a respective superconducting circuit. The AC clock signal with different phases coupled via different capacitors may propagate digital ones as a pair of single flux quantum (SFQ) pulses. In this example, the pulses are shown as loop currents that move through superconducting integrated circuit <NUM> with a half cycle of separation. The four-phase clock signals may provide directionality such that the positive pulse may ride the leading edge of the clock from one phase to the next and arrive at the output after one cycle of delay, and the negative pulse may follow with a half cycle of separation. In sum, in terms of the operation of superconducting integrated circuit <NUM>, in this example, capacitive coupling supports bipolar pulses (e.g., SFQ pulses). The capacitors <NUM>, <NUM>, <NUM>, and <NUM> are selected to have a smaller capacitance compared to the capacitance of a Josephson junction device so as not to load the superconducting circuit.

<FIG> is a diagram of another superconducting integrated circuit <NUM> including circuits that are capacitively coupled to clock lines in accordance with one example. Superconducting integrated circuit <NUM> may include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the Clock I terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the Clock Q terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the Clock -I terminal. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> coupled to the Clock -Q terminal. Superconducting integrated circuit <NUM> may include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM>. Data input may be received via the DATA terminal that may be coupled to superconducting circuit <NUM> via an inductor <NUM>.

Superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and a ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N1. The node N1 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

With continued reference to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N4. The node N4 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

Superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N5. The node N5 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

With continued reference to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N6. The node N6 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

Still referring to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N7. The node N7 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees.

With continued reference to <FIG>, superconducting circuit <NUM> may include a Josephson junction (JJ) <NUM> coupled between one end of inductor <NUM> and the ground terminal. JJ <NUM> may further be coupled to inductor <NUM>, which may be coupled to a node N8. The node N8 may be coupled to capacitor <NUM> and an inductor <NUM>. Another JJ <NUM> may be coupled between one end of inductor <NUM> and the ground terminal. In addition, superconducting circuit <NUM> may be coupled via capacitor <NUM> to receive an AC clock signal with a phase of <NUM> degrees. Although <FIG> shows a certain number of components of superconducting integrated circuit <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently. As an example, although <FIG> shows a schematic of a shift register circuit, superconducting integrated circuit <NUM> may be any other type of circuit, such as a logic gate, a flip-flop, or a memory circuit. In addition, although <FIG> shows a phase separation of <NUM> degrees between the clock signals and four clock lines, a phase separation of <NUM> degrees between the clock signals and three clock lines may also be used. Moreover, although <FIG> shows certain phase values associated with the clock lines, the clock lines need not receive clock signals with the phase value shown in <FIG>. As an example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Other phase allocations may also be used.

In terms of the operation of superconducting integrated circuit <NUM>, each clock line may receive the respective AC clock signal and provide a respective bias current to a respective superconducting circuit. The AC clock signal with different phases coupled via different capacitors may propagate digital ones as a single flux quantum (SFQ) pulse. In this example, the pulses are shown as loop currents that move through superconducting integrated circuit <NUM> with one cycle of separation. The four-phase clock signals may provide directionality such that the positive pulses may ride the leading edge of the clock from one phase to the next and arrive at the output after one cycle of delay. In sum, in terms of the operation of superconducting integrated circuit <NUM>, in this example, capacitive coupling supports unipolar pulses (e.g., only positive SFQ pulses). In circuits using inductive biasing, there is a need for time-interleaving of negative pulses with positive pulses, which serves to restore the bias current. Capacitive coupling has no such requirement, as the capacitor breaks the loop with respect to the bias supply. This means the capacitive coupling supports a superset of the data encodings supported by inductive coupling, including interleaved positive and negative pulses, one or multiple positive or negative clock pulses per cycle, or any combination thereof. The capacitors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are selected to have a smaller capacitance compared to the capacitance of a Josephson junction device so as not to load the superconducting circuit.

<FIG> is a diagram showing graphs <NUM> of junction potentials under alternating-current (AC) bias for both capacitively coupled and inductively coupled superconducting circuits in accordance with one example. Graphs <NUM> show the Josephson junction potential at four points in the AC clock cycle for both inductively coupled AC clock power and capacitively coupled AC clock power. As shown in graphs <NUM>, for inductive coupling each positive phase advance (if any) must be followed by a negative phase advance. In contrast, for capacitive coupling additional possibilities of phase advance exist. As an example, as shown in graphs <NUM>, positive phase could advance by more than one. Each of graphs <NUM>, <NUM>, <NUM>, and <NUM> shows Josephson junction (JJ) phase (shown in radians) along the horizontal axis and the energy stored in the JJ (shown in atto-Joules (aJ)) shown along the vertical axis. In this example, the energy difference between adjacent local minima may correspond to the amount of the energy that it takes for the Josephson junction to undergo a 2π-radian phase rotation, producing an SFQ data pulse. The potential energy profile is a function of the Josephson junction and the bias current network. In graph <NUM>, for inductive coupling, particle <NUM> shows the energy at a JJ phase when AC clock power is at its maximum value. For capacitive coupling, particle <NUM> shows the energy at the JJ phase when AC clock power is at its maximum value. As shown by curve <NUM>, for the inductive coupling case, the phase advance is a single phase advance (e.g., 2π radian). However, for the capacitive coupling, as shown by curve <NUM>, the phase advance is a double phase advance (e.g., 4π radian). As shown in graph <NUM>, when the AC clock power is at zero value, there is no phase advance for both the capacitive coupling case (particle <NUM>) and the inductive coupling case (particle <NUM>). In graph <NUM>, for inductive coupling, particle <NUM> shows the energy at a JJ phase when AC clock power is at its minimum value. For capacitive coupling, particle <NUM> shows the energy at the JJ phase when AC clock power is at its minimum value. As shown by curve <NUM>, for the inductive coupling case, the phase advance is a single phase advance (e.g., 2π radian). However, for the capacitive coupling, as shown by curve <NUM>, the phase advance is a double phase advance (e.g., 4π radian). As shown in graph <NUM>, when the AC clock power is at zero value again, there is no phase advance for both the capacitive coupling case (particle <NUM>) and the inductive coupling case (particle <NUM>). Although <FIG> shows double phase advance for the capacitive coupling case, other possibilities exist. As an example, the phase may advance by a multiple of four (e.g., 8π radian). In addition, the junction potentials for capacitive coupling are larger, producing faster JJ switching. Moreover, because the junction potentials for capacitive coupling are periodic they allow for a wider range of data encodings.

<FIG> is a diagram of another superconducting integrated circuit <NUM> including circuits that are capacitively coupled to clock lines in accordance with one example. Superconducting integrated circuit <NUM> is configured to operate in phase-mode logic (PML) mode. In the PML based devices, a logical ` <NUM>' may be encoded as a phase high and a logical '<NUM>' may be encoded as phase low. The transitions between phase high and phase low may be event-triggered by single flux quantum (SFQ) pulses. Unlike wave pipelined RQL mode where the waveform is returned to zero even when a logical value does not change, in the phase-mode logic circuits the waveform is not returned to zero until the logical value of the signal changes. Thus, if a signal has ten logical one values in succession the waveform would go high when the first logical high value is presented and stay high for the remaining logical high values. When superconducting integrated circuit <NUM> is configured in phase-mode logic, the latency of signal propagation is proportional to the transitions between positive and negative phase transitions. By enabling both positive and negative phase transitions at the same points in the clock cycle, capacitive coupling supports low-latency phase-mode logic circuits, such as superconducting integrated circuit <NUM>. In contrast, the use of inductive coupling would not allow this and there will be at least half a clock cycle latency. Thus, capacitive coupling, including capacitive bias taps, enables low latency, greater efficiency, and smaller size circuits in phase-mode logic.

With continued reference to <FIG>, superconducting integrated circuit <NUM> may include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> (coupled to the CLOCK I terminal) and further coupled via capacitor <NUM> to clock line <NUM> (coupled to the CLOCK -I terminal). As shown, in this example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Capacitor <NUM> may be configured to have twice the amount of capacitance (2C) relative to an amount of the capacitance (C) of capacitor <NUM>. This is because the bias current produced by capacitor <NUM> may have an amplitude that is twice the amplitude of the bias current produced by capacitor <NUM>. This in turn produces equal and opposite current through junctions <NUM> and <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> (coupled to the CLOCK Q terminal) and further coupled via capacitor <NUM> to clock line <NUM> (coupled to the -Q terminal). As shown, in this example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Capacitor <NUM> may be configured to have twice the amount of capacitance (2C) relative to an amount of the capacitance (C) of capacitor <NUM>. This is because the bias current produced by capacitor <NUM> may have an amplitude that is twice the amplitude of the bias current produced by capacitor <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> and further coupled via capacitor <NUM> to clock line <NUM>. As shown, in this example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Capacitor <NUM> may be configured to have twice the amount of capacitance (2C) relative to an amount of the capacitance (C) of capacitor <NUM>. This is because the bias current produced by capacitor <NUM> may have an amplitude that is twice the amplitude of the bias current produced by capacitor <NUM>. Superconducting integrated circuit <NUM> may further include superconducting circuit <NUM> coupled via capacitor <NUM> to clock line <NUM> and further coupled via capacitor <NUM> to clock line <NUM>. As shown, in this example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Capacitor <NUM> may be configured to have twice the amount of capacitance (2C) relative to an amount of the capacitance (C) of capacitor <NUM>. This is because the bias current produced by capacitor <NUM> may have an amplitude that is twice the amplitude of the bias current produced by capacitor <NUM>. Data input may be received via the DATA terminal that may be coupled to superconducting circuit <NUM> via an inductor <NUM>.

Still referring to <FIG>, superconducting circuit <NUM> may include a node N1 coupled to receive an AC clock signal via clock line <NUM> and a node N2 coupled to receive an AC clock signal via clock line <NUM>. Superconducting circuit <NUM> may further include a Josephson junction (JJ) <NUM> coupled between the node N1 and the node N2. A resistor <NUM> may also be coupled between the node N1 and the node N2. Another JJ <NUM> may be coupled between the node N2 and a ground terminal. A resistor <NUM> may also be coupled between the node N2 and the ground terminal. At about the same time during the clock cycle, JJ <NUM> may be positively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>), whereas JJ <NUM> may be negatively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>) resulting in a positive phase transition and a negative transition at about the same time during the clock cycle. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>.

With continued reference to <FIG>, superconducting circuit <NUM> may include a node N3 coupled to receive an AC clock signal via clock line <NUM> and a node N4 coupled to receive an AC clock signal via clock line <NUM>. Superconducting circuit <NUM> may further include a Josephson junction (JJ) <NUM> coupled between the node N3 and the node N4. A resistor <NUM> may also be coupled between the node N3 and the node N4. Another JJ <NUM> may be coupled between the node N4 and the ground terminal. A resistor <NUM> may also be coupled between the node N4 and the ground terminal. At about the same time during the clock cycle, JJ <NUM> may be positively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>), whereas JJ <NUM> may be negatively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>) resulting in a positive phase transition and a negative transition at about the same time during the clock cycle. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>.

As shown in <FIG>, superconducting circuit <NUM> may include a node N5 coupled to receive an AC clock signal via clock line <NUM> and a node N6 coupled to receive an AC clock signal via clock line <NUM>. Superconducting circuit <NUM> may further include a Josephson junction (JJ) <NUM> coupled between the node N5 and the node N6. A resistor <NUM> may also be coupled between the node N5 and the node N6. Another JJ <NUM> may be coupled between the node N6 and the ground terminal. A resistor <NUM> may also be coupled between the node N6 and the ground terminal. At about the same time during the clock cycle, JJ <NUM> may be negatively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>), whereas JJ <NUM> may be positively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>) resulting in a positive phase transition and a negative transition at about the same time during the clock cycle. Superconducting circuit <NUM> may be coupled via inductor <NUM> to superconducting circuit <NUM>.

Still referring to <FIG>, superconducting circuit <NUM> may include a node N7 coupled to receive an AC clock signal via clock line <NUM> and a node N8 coupled to receive an AC clock signal via clock line <NUM>. Superconducting circuit <NUM> may further include a Josephson junction (JJ) <NUM> coupled between the node N7 and the node N8. A resistor <NUM> may also be coupled between the node N7 and the node N8. Another JJ <NUM> may be coupled between the node N8 and the ground terminal. A resistor <NUM> may also be coupled between the node N8 and the ground terminal. At about the same time during the clock cycle, JJ <NUM> may be negatively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>), whereas JJ <NUM> may be positively biased (e.g., via the AC clock signal having a phase of <NUM> degrees, which is received via clock line <NUM>) resulting in a positive phase transition and a negative transition at about the same time during the clock cycle.

Although <FIG> shows a certain number of components of superconducting integrated circuit <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently. As an example, although <FIG> shows a schematic of a shift register circuit, superconducting integrated circuit <NUM> may be any other type of circuit, such as a logic gate, a flip-flop, or a memory circuit. In addition, although <FIG> shows a phase separation of <NUM> degrees between the clock signals and four clock lines, a phase separation of <NUM> degrees between the clock signals and three clock lines may also be used. Moreover, although <FIG> shows certain phase values associated with the clock lines, the clock lines need not receive clock signals with the phase value shown in <FIG>. As an example, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees, and clock line <NUM> may receive an AC clock signal with a phase of <NUM> degrees. Other phase allocations may also be used.

In terms of the operation of superconducting integrated circuit <NUM>, the AC clock signals may once again provide bias current to Josephson junction. However, unlike the superconducting circuits described earlier that include Josephson junctions that are either biased positively or biased negatively, superconducting circuits <NUM>, <NUM>, <NUM>, and <NUM> include Josephson junctions coupled in series such that one of the JJs can be biased positively while the other JJ can be biased negatively. Thus, superconducting integrated circuit <NUM> is configured such that both positive and negative transitions may occur at about the same point in the clock cycle. As explained earlier, in phase-mode logic the latency is proportional to the transitions between positive and negative phase transitions. By enabling both positive and negative phase transitions at the same points in the clock cycle, capacitive coupling supports low-latency phase-mode logic circuits, such as superconducting integrated circuit <NUM>. In other words, the phase-mode logic circuits may operate without a phase boundary.

In addition, superconducting integrated circuits may be implemented using large scale integrated circuit manufacturing techniques using a process involving niobium metal layers to form the clock lines and the ground plane. Capacitors may be manufactured to have sufficient thickness to suppress Josephson junction tunnel current. In one example, capacitors may have aluminum-oxide as the insulator layer. In this example, capacitors may be manufactured to have a permittivity of approximately <NUM>, a thickness of approximately <NUM>, a capacitance of approximately <NUM> femtoFarad(fF)/µm<NUM>. The capacitors may be configured to support a voltage of <NUM> mV and should have a low loss tangent. To determine the amount of capacitance required for the capacitors for use with an integrated circuit the following equation may be used: V<NUM>πfC = IJJ, where IJJ represents the Josephson junction current, V is the voltage across the capacitor, f is the frequency of the alternating current clock signal, and C is the capacitance of the capacitor. In this example, the impedance (Zc) seen by the clock signal may be represented by the equation: Zc = <NUM>/{<NUM>πfC}. Advantageously, capacitive coupling allows the use of highfrequency clock signals because the impedance seen by the clock signal is inversely proportional to the frequency of the clock signal. In addition, lower latency for phase-mode logic superconducting circuits can be achieved by increasing the frequency of the AC clock signals to some multiple of the required data rate. Capacitive coupling enables the higher frequency phase-mode logic circuits because unlike inductive coupling the frequency losses are frequency independent.

In conclusion, in one example, the present disclosure relates to a superconducting integrated circuit comprising a first clock line coupled via a first capacitor to a first superconducting circuit comprising a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit. The superconducting integrated circuit further comprises a second clock line coupled via a second capacitor to a second superconducting circuit comprising a second Josephson junction, where the second capacitor is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit, where the second phase is different from the first phase.

The superconducting integrated circuit may further include a third clock line coupled via a third capacitor to a third superconducting circuit comprising a third Josephson junction, where the third capacitor is configured to receive a third clock signal having a third phase and couple a third bias current to the third superconducting circuit, where the third phase is different from each of the first phase and the second phase. The superconducting integrated circuit may be configured such that a combined effect of the first bias current and the second bias current allows propagation of pulses via the first superconducting circuit and the second superconducting circuit in a first direction.

The first clock signal may comprise a first alternating current clock signal and where the second clock signal may comprise a second alternating current clock signal. The first alternating current clock signal may be configured to supply power to the first superconducting circuit via a first capacitive coupling between the first capacitor and the first alternating current clock signal and where the second alternating current clock signal may be configured to supply power to the second superconducting circuit via a second capacitive coupling between the second capacitor and the second alternating current clock signal.

Neither the first superconducting circuit nor the second superconducting circuit may be configured to receive power via inductive coupling. The first phase may comprise <NUM> degrees, the second phase may comprise <NUM> degrees, and the third phase may comprise <NUM> degrees.

The superconducting integrated circuit further comprises a third clock line coupled via a third capacitor to a third superconducting circuit comprising a third Josephson junction, where the third capacitor is configured to receive a third clock signal having a third phase and couple a third bias current to the third superconducting circuit. The superconducting integrated circuit further comprises a fourth clock line coupled via a fourth capacitor to a fourth superconducting circuit comprising a fourth Josephson junction, where the fourth capacitor is configured to receive a fourth clock signal having a fourth phase and couple a fourth bias current to the fourth superconducting circuit, where each of the first phase, the second phase, the third phase, and the fourth phase is different from each other.

The first clock signal may comprise a first alternating current clock signal, the second clock signal may comprise a second alternating current clock signal, the third clock signal may comprise a third alternating current clock signal, and the fourth clock signal comprises a fourth alternating current clock signal. The first alternating current clock signal may be configured to supply power to the first superconducting circuit via a first capacitive coupling between the first capacitor and the first alternating current clock signal, the second alternating current clock signal may be configured to supply power to the second superconducting circuit via a second capacitive coupling between the second capacitor and the second alternating current clock signal, the third alternating current clock signal may be configured to supply power to the third superconducting circuit via a third capacitive coupling between the third capacitor and the third alternating current clock signal, and the fourth alternating current clock signal may be configured to supply power to the fourth superconducting circuit via a fourth capacitive coupling between the fourth capacitor and the fourth alternating current clock signal.

None of the first superconducting circuit, the second superconducting circuit, the third superconducting circuit, or the fourth superconducting circuit may be configured to receive power via inductive coupling. The first phase may comprise <NUM> degrees, the second phase may comprise <NUM> degrees, the third phase may comprise <NUM> degrees, and the fourth phase may comprise <NUM> degrees.

The superconducting integrated circuit may be configured such that a combined effect of the first bias current, the second bias current, the third bias current, and the fourth bias current allows propagation of only positive single flux quantum (SFQ) pulses. Alternatively, the superconducting integrated circuit may be configured such that a combined effect of the first bias current, the second bias current, the third bias current, and the fourth bias current allows propagation of both positive single flux quantum (SFQ) pulses and negative SFQ pulses.

It is to be understood that the methods, modules, devices, systems, and components depicted herein are merely exemplary. Alternatively, or in addition, the functionally described herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "coupled," to each other to achieve the desired functionality.

The functionality associated with the examples described in this disclosure can also include instructions stored in a non-transitory media. The term "non-transitory media" as used herein refers to any media storing data and/or instructions that cause a machine to operate in a specific manner. Exemplary non-transitory media include non-volatile media and/or volatile media. Non-volatile media include, for example, a hard disk, a solid state drive, a magnetic disk or tape, an optical disk or tape, a flash memory, an EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory, such as, DRAM, SRAM, a cache, or other such media. Non-transitory media is distinct from, but can be used in conjunction with transmission media. Transmission media is used for transferring data and/or instruction to or from a machine. Exemplary transmission media include coaxial cables, fiber-optic cables, copper wires, and wireless media, such as radio waves.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Claim 1:
A superconducting integrated circuit (<NUM>) comprising:
a first clock line (<NUM>) coupled via a first capacitor (<NUM>) to a first superconducting circuit comprising (<NUM>) a first Josephson junction (<NUM>), wherein the first capacitor (<NUM>) is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit (<NUM>); and
a second clock line (<NUM>) coupled via a second capacitor (<NUM>) to a second superconducting circuit (<NUM>) comprising a second Josephson junction (<NUM>), wherein the second capacitor (<NUM>) is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit (<NUM>), wherein the second phase is different from the first phase.