Patent Description:
A spin transfer torque-magnetic random access memory (STT-MRAM) is a new memory that has advantages of non-volatile property, fast working speed, infinite times of erasing and writing, and the like. Compared with a static random access memory (Static Random Access Memory, SRAM), the STT-MRAM has great advantages in terms of static power consumption and area, in addition to having high performance of the SRAM. With the progress of a semiconductor process, the STT-MRAM faces an increasingly high integration requirement and various electrical problems caused by high integration.

US patent, <CIT>, provides a MRAM cell having an isolation transistor on a semiconductor A further example may be found in US patent, <CIT>.

This application provides a memory, to improve integration density of the memory.

A first aspect of this application provides a memory according to independent claim <NUM>, including a storage area, where the storage area includes several storage units disposed on a substrate; each storage unit includes a transistor disposed on the substrate and an MTJ storage element electrically connected to the transistor; and the MTJ storage element includes a bottom electrode, a top electrode, and an MTJ located between the two. The bottom electrode is electrically connected to a drain electrode of the transistor by using a conduction structure. A plurality of wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers. The conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole between the first metal wire and the second metal wire. The plurality of wiring layers include a first wiring layer, a second wiring layer, and a third wiring layer, and the third wiring layer is disposed between the first wiring layer and the second wiring layer. The first wiring layer includes the first metal wire, the second wiring layer includes the second metal wire, and the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer. A first connection passage is disposed in the first via hole, the first connection passage is directly connected to the first metal wire and the second metal wire, and the first connection passage is not directly connected to a metal wire at the third wiring layer.

In the conduction structure configured to electrically connect the drain electrode of the transistor to the bottom electrode of the MTJ storage element, the first via hole of the first conduction part penetrates the third wiring layer located between the first wiring layer and the second wiring layer, and the first connection passage disposed in the first via hole is directly connected to the first metal wire and the second metal wire. Therefore, compared with the case that the first metal wire and the second metal wire are electrically connected by using the third metal wire located between the first metal wire and the second metal wire and disposed at the third wiring layer, the third metal wire is omitted in this application. Therefore, space occupied by the third metal wire can be released. On this basis, in one aspect, the space released from the third metal wire may be used for circuit wiring, so as to ease overall circuit wiring congestion. In another aspect, after the third metal wire is omitted, when the minimum distance of wiring is met, an area occupied by each storage unit can be reduced, and therefore, integration density of the memory can be improved. In still another aspect, resistance of the via hole mainly comes from an interface between the via hole and a metal wire in contact with a lower part (close to the substrate) of the via hole. In this application, because the first via hole crosses the third wiring layer, no interface exists between the first via hole and the metal wire at the third wiring layer, lower resistance is caused, and a parasitic capacitance can be reduced, thereby improving overall performance of the memory.

With reference to the first aspect, in a possible implementation, the transistor is configured to control writing, changing, or reading of information in the storage unit.

With reference to the first aspect, according to the present invention, a second via hole is disposed in the storage area, and the second via hole penetrates the third wiring layer. The first via hole is adjacent to the second via hole, and no metal wire exists on a part that is of the third wiring layer and that is located between the first via hole and the second via hole.

With reference to the first aspect, in another possible implementation, a third via hole is disposed in the storage area, one end of the third via hole starts from the third wiring layer, a third connection passage in the third via hole is connected to the metal wire at the third wiring layer, and the third via hole is adjacent to the first via hole.

With reference to the first aspect, in another possible implementation, transistors in two adjacent storage elements share a drain electrode. Therefore, integration density of the memory can be further improved.

With reference to the first aspect, in another possible implementation, there are at least two first conduction parts, and all the first conduction parts are disposed along a thickness direction of the substrate.

On this basis, optionally, any two adjacent first conduction parts share the second metal wire or the first metal wire.

With reference to the first aspect, in another possible implementation, the conduction structure further includes a second conduction part, and the second conduction part is disposed between the first conduction part and the MTJ storage element. The second conduction part includes a fourth metal wire and a fourth via hole. The plurality of wiring layers further include a fourth wiring layer, and the fourth wiring layer includes the fourth metal wire. The fourth via hole penetrates a dielectric layer between the fourth wiring layer and the first conduction part. A fourth connection passage is disposed in the fourth via hole, and the fourth connection passage is directly connected to the fourth metal wire and the first metal wire or the second metal wire adjacent to the fourth metal wire.

With reference to the first aspect, in another possible implementation, the conduction structure further includes a third conduction part, and the third conduction part is disposed between the first conduction part and the transistor. The third conduction part includes a fifth via hole, and the fifth via hole penetrates a dielectric layer between the first conduction part and the drain electrode of the transistor. A fifth connection passage is disposed in the fifth via hole, and the fifth connection passage is directly connected to the drain electrode of the transistor and the first metal wire or the second metal wire adjacent to the drain electrode of the transistor.

With reference to the first aspect and the foregoing possible implementations, in another possible implementation, the first via hole penetrates one or two third wiring layers between the first wiring layer and the second wiring layer. When there are at least two first conduction parts of the conduction structure, a first via hole of each first conduction part penetrates one or two third wiring layers.

With reference to the first aspect and the foregoing possible implementations, in another possible implementation, in each first conduction part, the first connection passage and a first metal wire or a second metal wire that is located on a side of the first connection passage away from the substrate and that is directly connected to the first connection passage form an integrated structure. A diffusion barrier layer is disposed on a side surface and a bottom surface of the integrated structure, and the bottom surface is close to the substrate. A part of the diffusion barrier layer that is located on a side surface and a bottom surface of the first connection passage is located in the first via hole.

On this basis, optionally, when the conduction structure further includes the second conduction part, the fourth connection passage and the fourth metal wire form an integrated structure. On this basis, the diffusion barrier layer may be further disposed on a side surface and a bottom surface of the integrated structure including the fourth connection passage and the fourth metal wire, and the bottom surface is close to the substrate. A part of the diffusion barrier layer that is located on a side surface and a bottom surface of the fourth connection passage is located in the fourth via hole.

Optionally, when the conduction structure further includes the third conduction part, the fifth connection passage and the first metal wire or the second metal wire that is located on a side of the fifth connection passage away from the substrate and that is directly connected to the fifth connection passage form an integrated structure. The diffusion barrier layer may be further disposed on a side surface and a bottom surface of the integrated structure including the fifth connection passage and one of the first metal wire and the second metal wire, and the bottom surface is close to the substrate. A part of the diffusion barrier layer that is located on a side surface and a bottom surface of the fifth connection passage is located in the fifth via hole.

With reference to the first aspect, in another possible implementation, a dielectric layer disposed between adjacent wiring layers includes at least a first sublayer and a second sublayer, where the second sublayer is an etch barrier layer and is disposed on a side of the first sublayer close to the substrate.

On this basis, optionally, a material of the first sublayer is a dielectric material of a low dielectric constant or an ultra-low dielectric constant.

With reference to the first aspect and the foregoing possible implementations, in another possible implementation, the first metal wire and the second metal wire are parallel in a length direction.

Further, optionally, a length direction of the fourth metal wire is parallel to length directions of the first metal wire and the second metal wire. On this basis, in a width direction of the first metal wire and the second metal wire, a size of the storage unit is reduced, thereby improving integration density of the memory.

A second aspect of this application provides another memory according to independent claim <NUM>, including a storage area, where the storage area includes several storage units disposed on a substrate; each storage unit includes a transistor disposed on the substrate and an MTJ storage element electrically connected to the transistor; and the MTJ storage element includes a bottom electrode, a top electrode, and an MTJ located between the bottom electrode and the top electrode. The bottom electrode is electrically connected to a drain electrode of the transistor by using a conduction structure. A plurality of wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers and between a wiring layer closest to the transistor and the transistor. The conduction structure includes a first conduction part. The first conduction part includes a first metal wire and a first via hole. The plurality of wiring layers include a first wiring layer and a second wiring layer, and the second wiring layer is disposed between the first wiring layer and the transistor. The first wiring layer includes the first metal wire, and the first via hole penetrates a dielectric layer and the second wiring layer that are located between the first wiring layer and the transistor. A first connection passage is disposed in the first via hole, the first connection passage is directly connected to the first metal wire and the drain electrode of the transistor, and the first connection passage is not directly connected to a metal wire at the second wiring layer.

In the conduction structure configured to electrically connect the drain electrode of the transistor to the bottom electrode of the MTJ storage element, the first via hole of the first conduction part penetrates the second wiring layer between the first wiring layer and the transistor, so that the first connection passage disposed in the first via hole is directly connected to the first metal wire and the drain electrode of the transistor. Therefore, compared with the case that the first metal wire and the drain electrode of the transistor are electrically connected by using the metal wire that is located between the first metal wire and the drain electrode of the transistor and that is disposed at the second wiring layer, space occupied by the metal wire at the second wiring layer can be released in this application. On this basis, in one aspect, the space released by the second wiring layer may be used for circuit wiring, so as to ease overall circuit wiring congestion. In another aspect, after the metal wire that is on the second wiring layer and that is used to connect the drain electrode to the first metal wire is omitted, when a minimum distance of wiring is met, an area occupied by each storage unit can be reduced, and therefore, integration density of the memory can be improved. In still another aspect, resistance of the via hole mainly comes from an interface between the via hole and a metal in contact with a lower part (close to the substrate) of the via hole. In this application, because the first via hole crosses the second wiring layer, no interface exists between the first via hole and the metal wire at the second wiring layer, lower resistance is caused, and a parasitic capacitance can be reduced, thereby improving overall performance of the memory.

With reference to the second aspect, in a possible implementation, the transistor is configured to control writing, changing, or reading of information in the storage unit.

With reference to the second aspect, in another possible implementation, transistors in two adjacent storage elements share a drain electrode. Therefore, integration density of the memory can be further improved.

With reference to the second aspect, in another possible implementation, there are at least two first conduction parts, and all the first conduction parts are disposed along a thickness direction of the substrate; and any adjacent first conduction parts are directly connected.

With reference to the second aspect, according to the present invention, the conduction structure further includes a second conduction part. The second conduction part is disposed on a side of the first conduction part away from the substrate. The second conduction part includes a fourth metal wire and a fourth via hole. The plurality of wiring layers further include a fourth wiring layer, and the fourth wiring layer includes the fourth metal wire. The fourth via hole penetrates a dielectric layer between the fourth wiring layer and the first conduction part. A fourth connection passage is disposed in the fourth via hole, and the fourth connection passage is directly connected to the fourth metal wire and the first metal wire.

On this basis, optionally, there are at least two second conduction parts, and all the second conduction parts are disposed along the thickness direction of the substrate. In all the second conduction parts, a fourth connection passage in a second conduction part closest to the first conduction part is directly connected to the fourth metal wire and the first metal wire. In any adjacent second conduction parts, a fourth metal wire and a fourth connection passage that separately belong to the adjacent second conduction parts are directly connected.

Optionally, a length direction of the fourth metal wire is parallel to a length direction of the first metal wire. On this basis, in a width direction of the first metal wire, a size of the storage unit is reduced, thereby improving integration density of the memory.

With reference to the second aspect and the foregoing possible implementations, in another possible implementation, the first via hole penetrates one or two second wiring layers between the first wiring layer and the transistor.

With reference to the second aspect and the foregoing possible implementations, in another possible implementation, in each first conduction part, the first connection passage and the first metal wire that is directly connected to the first connection passage form an integrated structure. A diffusion barrier layer is disposed on a side surface and a bottom surface of the integrated structure, and the bottom surface is close to the substrate. A part of the diffusion barrier layer that is located on a side surface and a bottom surface of the first connection passage is located in the first via hole.

On this basis, when the conduction structure further includes the second conduction part, the fourth connection passage and the fourth metal wire form an integrated structure. On this basis, the diffusion barrier layer may be further disposed on a side surface and a bottom surface of the integrated structure including the fourth connection passage and the fourth metal wire, and the bottom surface is close to the substrate. A part of the diffusion barrier layer that is located on a side surface and a bottom surface of the fourth connection passage is located in the fourth via hole.

With reference to the second aspect, in another possible implementation, a dielectric layer disposed between adjacent wiring layers includes at least a first sublayer and a second sublayer, where the second sublayer is an etch barrier layer and is disposed on a side of the first sublayer close to the substrate.

On this basis, optionally, a material of the first sublayer is a material of a low dielectric constant or an ultra-low dielectric constant.

The following describes the technical solutions in this application with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are merely some but not all of the embodiments of this application.

In addition, in the descriptions of this application, unless otherwise specified, "several" and "a plurality of" mean two or more than two.

This application provides a memory. As shown in <FIG>, the memory includes a storage area <NUM>, and the storage area <NUM> includes several storage units disposed on a substrate <NUM>. As shown in <FIG>, each storage unit <NUM> includes a transistor <NUM> disposed on the substrate <NUM> and a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) storage element <NUM> electrically connected to the transistor <NUM>.

As shown in <FIG>, the MTJ storage element <NUM> includes a bottom electrode <NUM>, a top electrode <NUM>, and an MTJ <NUM> located between the bottom electrode <NUM> and the top electrode <NUM>. The bottom electrode <NUM> is electrically connected to a drain electrode <NUM> of the transistor <NUM> by using a conduction structure <NUM>. A plurality of wiring layers are disposed between the transistor <NUM> and the MTJ storage element <NUM> in the storage area <NUM>, and a dielectric layer <NUM> is filled between adjacent wiring layers.

Still referring to <FIG>, the conduction structure <NUM> includes a first conduction part <NUM>, and the first conduction part <NUM> includes a first metal wire <NUM>, a second metal wire <NUM>, and a first via hole <NUM> located between the first metal wire <NUM> and the second metal wire <NUM>. The plurality of wiring layers include a first wiring layer <NUM>, a second wiring layer <NUM>, and a third wiring layer <NUM>, and the third wiring layer <NUM> is disposed between the first wiring layer <NUM> and the second wiring layer <NUM>. The first wiring layer <NUM> includes the first metal wire <NUM>, the second wiring layer <NUM> includes the second metal wire <NUM>, and the first via hole <NUM> penetrates the third wiring layer <NUM> and the dielectric layer <NUM> that are located between the first wiring layer <NUM> and the second wiring layer <NUM>. A first connection passage <NUM> is disposed in the first via hole <NUM>, the first connection passage <NUM> is directly connected to the first metal wire <NUM> and the second metal wire <NUM>, and the first connection passage <NUM> is not directly connected to a metal wire at the third wiring layer <NUM>.

It should be noted that as shown in <FIG>, a word line <NUM> and a bit line <NUM> are further disposed in the storage area <NUM>. The word line <NUM> is configured to control on or off of the transistor <NUM>, and the bit line <NUM> is configured to read/write data from or to a corresponding MTJ storage element <NUM> when the transistor <NUM> is on. Generally, a gate electrode <NUM> of a transistor <NUM> in each storage unit <NUM> is electrically connected to the word line <NUM>, a source electrode <NUM> is electrically connected to a source electrode line <NUM>, and the top electrode <NUM> of the MTJ storage element <NUM> is electrically connected to the bit line <NUM>.

In addition to the storage unit <NUM>, the memory of this application further includes a peripheral circuit, such as a sense amplification circuit and a read/write circuit. Circuit wiring may be located in a peripheral area of the storage area <NUM>, and wiring of the peripheral circuit (including the word line <NUM>, the source electrode line <NUM>, and the bit line <NUM>) is also disposed in the storage area <NUM>. Circuit wiring of the peripheral circuit is distributed at each wiring layer.

In addition, in this application, all metal wires in the storage area <NUM>, except the transistor <NUM> and the MTJ storage element <NUM>, on a same plane (the plane is parallel to or substantially parallel to an upper surface of the substrate <NUM>) of the dielectric layer <NUM> are referred to as one wiring layer. For metal wires that constitute a same wiring layer, there is a distance between different metal wires, and a dielectric material is filled in the distance. The dielectric layer <NUM> covers the storage area <NUM>.

For the third wiring layer <NUM>, the first via hole <NUM> penetrates the third wiring layer <NUM>, but the first connection passage <NUM> disposed in the first via hole <NUM> is not directly connected to the metal wire at the third wiring layer <NUM>. That is, no metal wire is disposed at a position that is of the third wiring layer <NUM> and that is corresponding to the first via hole <NUM>, so as to meet this condition. "Direct connection" means direct physical contact without passing through another structure.

Because the first via hole <NUM> penetrates the third wiring layer <NUM> and the dielectric layer <NUM> that are located between the first wiring layer <NUM> and the second wiring layer <NUM>, and the first connection passage <NUM> disposed in the first via hole <NUM> is directly connected to the first metal wire <NUM> and the second metal wire <NUM>, it may be learned that both ends of the first via hole <NUM> are directly connected to the first metal wire <NUM> and the second metal wire <NUM> respectively.

On the basis of the foregoing, a person skilled in the art should understand that the conduction structure <NUM> used to connect the bottom electrode <NUM> of the MTJ storage element and the drain electrode <NUM> of the transistor is the same in each storage unit <NUM>.

Referring to <FIG>, in addition to the drain electrode <NUM>, the transistor <NUM> further includes a source electrode <NUM>, a gate dielectric layer <NUM>, and a gate electrode <NUM>. To distinguish between two electrodes other than the gate electrode <NUM> of the transistor <NUM>, one electrode of the two electrodes is referred to as the source electrode <NUM>, and the other electrode is referred to as the drain electrode <NUM>. Therefore, the source electrode <NUM> and the drain electrode <NUM> in this application are only used to distinguish from each other, which does not indicate that when the transistor <NUM> is actually connected to a circuit, the drain electrode <NUM> can be connected to another device in the circuit only as the drain electrode of the transistor <NUM> in the circuit.

For example, as shown in <FIG>, the transistor <NUM> may further include a source electrode region <NUM> and a drain electrode region <NUM>. The source electrode region <NUM> is in contact with the source electrode <NUM>, the drain electrode region <NUM> is in contact with the drain electrode <NUM>, and a region between the source electrode region <NUM> and the drain electrode region <NUM> is a passage region. The source electrode region <NUM> and the drain electrode region <NUM> may be obtained by performing a doping process on the substrate <NUM>. In this case, the substrate <NUM> is a semiconductor material, such as silicon.

Optionally, the transistor <NUM> is configured to control writing, changing, or reading of information in the storage unit <NUM>. That is, the transistor <NUM> is used as a selector device to control writing, changing, or reading of information in the storage unit <NUM>.

A dielectric material is also filled between the transistor <NUM> and a wiring layer closest to the transistor <NUM> (for example, the first wiring layer <NUM> shown in <FIG>).

The MTJ storage element <NUM> is usually integrated in a middle of line process or a back end of line process, and a plurality of wiring layers (the plurality of wiring layers are disposed along a thickness direction of the substrate <NUM>) are disposed between the transistor <NUM> and the MTJ storage element <NUM> in the storage area <NUM>.

For example, one first wiring layer <NUM>, one second wiring layer <NUM>, and one third wiring layer <NUM> are disposed between the transistor <NUM> and the MTJ storage element <NUM>, the first wiring layer <NUM> is close to the substrate <NUM>, and the third wiring layer <NUM> is disposed between the first wiring layer <NUM> and the second wiring layer <NUM>. As shown in <FIG>, in each storage unit <NUM>, the drain electrode <NUM> of the transistor <NUM> may be electrically connected to the bottom electrode <NUM> of the MTJ storage element <NUM> in the following manner: The second metal wire <NUM> at the second wiring layer <NUM> is directly connected to the bottom electrode of the MTJ storage element <NUM>; in addition, the second metal wire <NUM> at the second wiring layer <NUM> is directly connected to a third metal wire <NUM> at the third wiring layer <NUM> by using a via hole penetrating the dielectric layer <NUM> between the second wiring layer <NUM> and the third wiring layer <NUM> and a connection passage disposed in the via hole; the third metal wire <NUM> at the third wiring layer <NUM> is further directly connected to the first metal wire <NUM> at the first wiring layer <NUM> by using a via hole penetrating the dielectric layer <NUM> between the third wiring layer <NUM> and the first wiring layer <NUM> and a connection passage disposed in the via hole; and the first metal wire <NUM> at the first wiring layer <NUM> is further directly connected to the drain electrode <NUM> of the transistor <NUM> by using a via hole penetrating the dielectric layer <NUM> between the first wiring layer <NUM> and the transistor <NUM> and a connection passage disposed in the via hole, so that the drain electrode <NUM> of the transistor <NUM> is electrically connected to the bottom electrode <NUM> of the MTJ storage element <NUM>.

With evolution of a semiconductor technology process node, metal interconnects in an integrated circuit gradually change from two-dimensional wiring to strict one-dimensional wiring. Therefore, in <FIG>, the second metal wire <NUM>, the third metal wire <NUM>, and the first metal wire <NUM> that are used to electrically connect the drain electrode <NUM> of the transistor <NUM> to the bottom electrode <NUM> of the MTJ storage element <NUM> may be disposed in a manner shown in <FIG>, and a metal wire at each layer is laid out in a one-dimensional manner.

Due to a limitation of a metal wire manufacturing process, a size of a metal wire at a wiring layer needs to meet a requirement of a minimum area (a plane area). The requirement of the minimum area of the metal wire may be converted into a requirement of a minimum length L of the metal wire (shown in <FIG>) when a width of the metal wire is a minimum line width. However, there is also a requirement of a minimum distance d between ends of the metal wire (shown in <FIG>). Therefore, based on the manner of electrically connecting the drain electrode <NUM> of the transistor to the bottom electrode <NUM> of the MTJ storage element in <FIG>, the requirement of the minimum length of the metal wire and the requirement of the minimum distance between ends of adjacent metal wires at a same wiring layer limit integration of the memory.

The requirement of the minimum area of the metal wire continues to deteriorate with the development of a technology node. As can be seen from <FIG> that, from a <NUM> node to a <NUM> node, to meet the requirement of the minimum area, the requirement of the minimum length of the metal wire has increased from <NUM> times a minimum metal line width to <NUM> times. That is, with the development of the technology node, the minimum length of the metal wire gradually increases. Therefore, the requirement of the minimum length of the metal wire gradually becomes a bottleneck that prevents memory integration density from being further improved.

In this application, referring to <FIG>, the first via hole <NUM> penetrates the third wiring layer <NUM>, that is, no metal wire is disposed at a position that is of the third wiring layer <NUM> and that is corresponding to the first via hole <NUM>. Therefore, by comparing <FIG> with <FIG>, because the first via hole <NUM> is disposed in <FIG>, the third metal wire <NUM> in <FIG>, located between the first metal wire <NUM> and the second metal wire <NUM> and disposed at the third wiring layer <NUM> may be omitted. The third metal wire <NUM> located between the first metal wire <NUM> and the second metal wire <NUM> and disposed at the third wiring layer <NUM> is omitted, so that corresponding space occupied due to the requirement of the minimum length of the metal wire can be released.

In the memory provided in this application, in the conduction structure <NUM> configured to electrically connect the drain electrode <NUM> of the transistor <NUM> to the bottom electrode <NUM> of the MTJ storage element <NUM>, the first via hole <NUM> of the first conduction part <NUM> penetrates the third wiring layer <NUM> located between the first wiring layer <NUM> and the second wiring layer <NUM>, and the first connection passage <NUM> disposed in the first via hole <NUM> is directly connected to the first metal wire <NUM> and the second metal wire <NUM>. Therefore, compared with <FIG> that the first metal wire <NUM> and the second metal wire <NUM> are electrically connected by using the third metal wire <NUM> located between the first metal wire <NUM> and the second metal wire <NUM> and disposed at the third wiring layer <NUM>, the third metal wire <NUM> is omitted in this application. Therefore, space occupied by the third metal wire <NUM> can be released. On this basis, in one aspect, the space released from the third metal wire <NUM> may be used for circuit wiring, so as to ease overall circuit wiring congestion. In another aspect, after the third metal wire <NUM> is omitted, when the minimum distance of wiring is met, an area occupied by each storage unit <NUM> can be reduced, and therefore, integration density of the memory can be improved. In still another aspect, resistance of the via hole mainly comes from an interface between the via hole and a metal wire in contact with a lower part (close to the substrate <NUM>) of the via hole. In this application, because the first via hole <NUM> crosses the third wiring layer <NUM>, no interface exists between the first via hole <NUM> and the metal wire at the third wiring layer <NUM>, lower resistance is caused, and a parasitic capacitance can be reduced, thereby improving overall performance of the memory.

Optionally, in this application, the first metal wire <NUM> and the second metal wire <NUM> are parallel in a length direction. On this basis, in a width direction of the first metal wire <NUM> and the second metal wire <NUM>, a size of the storage unit <NUM> is reduced, thereby further improving integration density of the memory.

Optionally, when the source electrode <NUM> and the drain electrode <NUM> of the transistor <NUM> are symmetrical, the source electrode <NUM> and the drain electrode <NUM> are not different. Therefore, as shown in <FIG>, transistors <NUM> in two adjacent storage units <NUM> may share a drain electrode <NUM>. Therefore, integration density of the memory can be further improved.

According to the invention (first aspect; claim <NUM>), as shown in <FIG>, a second via hole <NUM> is disposed in the storage area <NUM>, and the second via hole <NUM> penetrates the third wiring layer <NUM>. The first via hole <NUM> is adjacent to the second via hole <NUM>, and no metal wire exists on a part that is of the third wiring layer <NUM> and that is located between the first via hole <NUM> and the second via hole <NUM>.

Herein, the first via hole <NUM> is adjacent to the second via hole <NUM>, that is, no other via hole exists between the first via hole <NUM> and the second via hole <NUM>. A function of the second via hole <NUM> is not limited, and the second via hole <NUM> may be used to connect circuit wiring at different wiring layers.

It should be noted that, compared with a cross-sectional view shown in <FIG>, a cross-sectional view shown in <FIG> is a cross-sectional view taken in another direction of the storage area <NUM>. A connection between the second via hole <NUM> and the metal wire at the second wiring layer <NUM> and the first wiring layer <NUM> in <FIG> is only an example.

When no metal wire is disposed at positions of the third wiring layer <NUM> that are corresponding to the first via hole <NUM> and the second via hole <NUM>, and the metal wire of the third wiring layer <NUM> does not exist between the first via hole <NUM> and the second via hole <NUM>, the first via hole <NUM> and the second via hole <NUM> need to meet only a requirement of a via hole distance during disposing. Therefore, integration density of the memory can be higher.

Optionally, as shown in <FIG>, a third via hole <NUM> is disposed in the storage area <NUM>, one end of the third via hole <NUM> starts from the third wiring layer <NUM>, a third connection passage <NUM> in the third via hole <NUM> is connected to the metal wire at the third wiring layer <NUM>, and the third via hole <NUM> is adjacent to the first via hole <NUM>.

Herein, the third via hole <NUM> is adjacent to the first via hole <NUM>, that is, no other via hole exists between the third via hole <NUM> and the first via hole <NUM>. A function of the third via hole <NUM> is not limited, and the third via hole <NUM> may be used to connect circuit wiring at different wiring layers.

It should be noted that, compared with the cross-sectional view shown in <FIG>, a cross-sectional view shown in <FIG> is a cross-sectional view taken in another direction of the storage area <NUM>. A connection between the third via hole <NUM> and the metal wire at the first wiring layer <NUM> in <FIG> is only an example.

Compared with the technical solution in <FIG>, the third metal wire <NUM> is omitted in the solution of this application. Therefore, corresponding released space may be used for circuit wiring.

Optionally, as shown in <FIG> and <FIG>, there are at least two first conduction parts <NUM>, and all the first conduction parts <NUM> are disposed in the thickness direction of the substrate <NUM>.

It should be noted that, two adjacent first conduction parts <NUM> may be connected by using a sixth via hole <NUM> and a sixth connection passage <NUM> located in the sixth via hole <NUM> as shown in <FIG>, or may be directly connected as shown in <FIG>.

Based on different positions of the MTJ storage element <NUM>, in particular, when the MTJ storage element <NUM> is integrated in the back end of line process, at least two first conduction parts <NUM> may be disposed in the conduction structure <NUM>, so as to improve integration density of the memory.

Further, optionally, as shown in <FIG>, any two adjacent first conduction parts <NUM> share the second metal wire <NUM> or the first metal wire <NUM>.

In <FIG>, two first conduction parts <NUM> are used as an example. In this example, if a plurality of wiring layers disposed between the transistor <NUM> and the MTJ storage element <NUM> in the storage area <NUM> are successively a first wiring layer <NUM>, a third wiring layer <NUM>, a second wiring layer <NUM>, a third wiring layer <NUM>, and a first wiring layer <NUM> starting from the one closest to the substrate <NUM>, the two first conduction parts <NUM> share the second metal wire <NUM>.

It may be understood that if the plurality of wiring layers disposed between the transistor <NUM> and the MTJ storage element <NUM> in the storage area <NUM> are successively a second wiring layer <NUM>, a third wiring layer <NUM>, a first wiring layer <NUM>, a third wiring layer <NUM>, and a second wiring layer <NUM> starting from the one closest to the substrate <NUM>, the two first conduction parts <NUM> share the first metal wire <NUM>.

When there are three first conduction parts <NUM>, and the first conduction part <NUM> located in the middle is separately adjacent to the first conduction parts <NUM> on its both sides in a direction perpendicular to the substrate <NUM>, the first conduction part <NUM> located in the middle shares the second metal wire <NUM> with the first conduction part <NUM> on one side, and the first conduction part <NUM> located in the middle shares the first metal wire <NUM> with the first conduction part <NUM> on the other side.

Optionally, as shown in <FIG>, the conduction structure <NUM> further includes a second conduction part <NUM>, and the second conduction part <NUM> is disposed between the first conduction part <NUM> and the MTJ storage element <NUM>. The second conduction part <NUM> includes a fourth metal wire <NUM> and a fourth via hole <NUM>. The plurality of wiring layers further include a fourth wiring layer <NUM>, and the fourth wiring layer <NUM> includes the fourth metal wire <NUM>. The fourth via hole <NUM> penetrates a dielectric layer <NUM> between the fourth wiring layer <NUM> and the first conduction part <NUM>. A fourth connection passage <NUM> is disposed in the fourth via hole <NUM>, and the fourth connection passage <NUM> is directly connected to the fourth metal wire <NUM> and the first metal wire <NUM> or the second metal wire <NUM> adjacent to the fourth metal wire <NUM>.

A length direction of the fourth metal wire <NUM> may be parallel to length directions of the first metal wire <NUM> and the second metal wire <NUM>.

<FIG> is a schematic diagram by using an example in which the fourth wiring layer <NUM> is disposed adjacent to the second wiring layer <NUM>. In this case, the fourth connection passage <NUM> is directly connected to the fourth metal wire <NUM> and the second metal wire <NUM>. The fourth wiring layer <NUM> is adjacent to the second wiring layer <NUM>, that is, no other wiring layer exists between the fourth wiring layer <NUM> and the second wiring layer <NUM>.

If the fourth wiring layer <NUM> is disposed adjacent to the first wiring layer <NUM>, the fourth connection passage <NUM> is directly connected to the fourth metal wire <NUM> and the first metal wire <NUM>. The fourth wiring layer <NUM> is adjacent to the first wiring layer <NUM>, that is, no other wiring layer exists between the fourth wiring layer <NUM> and the first wiring layer <NUM>.

It should be noted that, regardless of a quantity of first conduction parts <NUM>, all first conduction parts <NUM> should be considered as a whole, and the second conduction part <NUM> is disposed between the first conduction part <NUM> and the MTJ storage element <NUM>. That is, when there are a plurality of first conduction parts <NUM>, the second conduction part <NUM> is disposed between a first conduction part <NUM> closest to the MTJ storage element <NUM> and the MTJ storage element <NUM>.

In addition, in the accompanying drawings related to this application, arrowed lines next to "<NUM>", "<NUM>", "<NUM>", and "<NUM>" are used to indicate one wiring layer.

Optionally, referring to <FIG>, the conduction structure <NUM> further includes a third conduction part <NUM>, and the third conduction part <NUM> is disposed between the first conduction part <NUM> and the transistor <NUM>. The third conduction part <NUM> includes a fifth via hole <NUM>, and the fifth via hole <NUM> penetrates the dielectric layer <NUM> between the first conduction part <NUM> and the drain electrode <NUM> of the transistor. A fifth connection passage <NUM> is disposed in the fifth via hole <NUM>, and the fifth connection passage <NUM> is directly connected to the drain electrode <NUM> of the transistor <NUM> and the first metal wire <NUM> or the second metal wire <NUM> adjacent to the drain electrode <NUM> of the transistor <NUM>.

<FIG> are schematic diagrams by using an example in which the first wiring layer <NUM> is closer to the transistor <NUM>. In this case, the fifth connection passage <NUM> is directly connected to the drain electrode <NUM> of the transistor <NUM> and the first metal wire <NUM>.

If the second wiring layer <NUM> is closer to the transistor <NUM>, the fifth connection passage <NUM> is directly connected to the drain electrode <NUM> of the transistor <NUM> and the second metal wire <NUM>.

It should be noted that, regardless of a quantity of first conduction parts <NUM>, all first conduction parts <NUM> should be considered as a whole, and the third conduction part <NUM> is disposed between the first conduction part <NUM> and the transistor <NUM>. That is, when there are a plurality of first conduction parts <NUM>, the third conduction part <NUM> is disposed between the first conduction part <NUM> closest to the substrate <NUM> and the transistor <NUM>.

Optionally, the first via hole <NUM> penetrates one or two third wiring layers <NUM> between the first wiring layer <NUM> and the second wiring layer <NUM>.

When there are at least two first conduction parts <NUM> of the conduction structure <NUM>, a first via hole <NUM> of each first conduction part <NUM> penetrates one or two third wiring layers <NUM>.

That is, for example, when the conduction structure <NUM> includes two first conduction parts <NUM>, a first via hole <NUM> of one first conduction part <NUM> may penetrate one third wiring layer <NUM>, and a first via hole <NUM> of the other first conduction part <NUM> may penetrate two third wiring layers <NUM> (shown in <FIG>); or first via holes <NUM> of both the two first conduction parts <NUM> penetrate one third wiring layer <NUM> (shown in <FIG>); or first via holes <NUM> of both the two first conduction parts <NUM> penetrate two third wiring layers <NUM>.

Optionally, as shown in <FIG>, in each first conduction part <NUM>, a first connection passage <NUM> and a first metal wire <NUM> or a second metal wire <NUM> that is located on a side of the first connection passage <NUM> away from the substrate <NUM> and that is directly connected to the first connection passage <NUM> form an integrated structure. On this basis, a diffusion barrier layer <NUM> is disposed on a side surface and a bottom surface of the integrated structure, and the bottom surface is close to the substrate <NUM>. A part of the diffusion barrier layer <NUM> that is located on a side surface and a bottom surface of the first connection passage <NUM> is located in the first via hole <NUM>.

<FIG> is a schematic diagram by using an example in which one first conduction part <NUM> is disposed. In the first conduction part <NUM>, the second metal wire <NUM> is located on a side of the first connection passage <NUM> away from the substrate <NUM>. Therefore, the first connection passage <NUM> and the second metal wire <NUM> directly connected to the first connection passage <NUM> form an integrated structure. On this basis, the diffusion barrier layer <NUM> is disposed on a side surface and a bottom surface of the first connection passage <NUM> and the second metal wire <NUM> of the integrated structure, and a part of the diffusion barrier layer <NUM> that is located on the side surface and the bottom surface of the first connection passage <NUM> is located in the first via hole <NUM>.

<FIG> and <FIG> are schematic diagrams by using an example in which two first conduction parts <NUM> are disposed. For a first conduction part <NUM> closer to the substrate <NUM>, because the second metal wire <NUM> is located on a side of the first connection passage <NUM> away from the substrate <NUM>, in the first conduction part <NUM>, the first connection passage <NUM> and the second metal wire <NUM> directly connected to the first connection passage <NUM> form an integrated structure. The diffusion barrier layer <NUM> is disposed on a side surface and a bottom surface of the first connection passage <NUM> and the second metal wire <NUM> of the integrated structure, and a part of the diffusion barrier layer <NUM> that is located on the side surface and the bottom surface of the first connection passage <NUM> is located in the first via hole <NUM>. For the other first conduction part <NUM>, because the first metal wire <NUM> is located on a side of the first connection passage <NUM> away from the substrate <NUM>, in the first conduction part <NUM>, the first connection passage <NUM> and the first metal wire <NUM> directly connected to the first connection passage <NUM> form an integrated structure. The diffusion barrier layer <NUM> is disposed on a side surface and a bottom surface of the first connection passage <NUM> and the first metal wire <NUM> of the integrated structure, and a part of the diffusion barrier layer <NUM> that is located on the side surface and the bottom surface of the first connection passage <NUM> is located in the first via hole <NUM>.

The "integrated structure" means that two parts of materials constituting the integrated structure are the same and are simultaneously formed. Specifically, when the first connection passage <NUM> and the first metal wire <NUM> that is located on the side of the first connection passage <NUM> away from the substrate <NUM> and that is directly connected to the first connection passage <NUM> form an integrated structure, the first connection passage <NUM> and the first metal wire <NUM> that is located on the side of the first connection passage <NUM> away from the substrate <NUM> and that is directly connected to the first connection passage <NUM> are simultaneously formed. When the first connection passage <NUM> and the second metal wire <NUM> that is located on the side of the first connection passage <NUM> away from the substrate <NUM> and that is directly connected to the first connection passage <NUM> form an integrated structure, the first connection passage <NUM> and the second metal wire <NUM> that is located on the side of the first connection passage <NUM> away from the substrate <NUM> and that is directly connected to the first connection passage <NUM> are simultaneously formed.

Because some interconnect metal materials, such as copper (Cu), are easy to diffuse, resulting in circuit performance degradation or failure, the diffusion barrier layer <NUM> needs to be disposed to prevent diffusion. For different interconnect metal materials, different materials of the diffusion barrier layer <NUM> need to be used correspondingly, so as to ensure a barrier function of the diffusion barrier layer <NUM>, adhesion to the integrated structure and the dielectric layer <NUM>, and the like.

For example, when a material of the integrated structure is Cu, a tantalum nitride (TaN)/tantalum (Ta) double-layer structure may be used as the diffusion barrier layer <NUM>, or a TaN/cobalt (Co) double-layer structure may be used as the diffusion barrier layer <NUM>.

It should be noted that the interconnect metal material applied to the memory in this application may further be Co, ruthenium (Ru), tungsten (W), or the like, and whether to dispose the diffusion barrier layer <NUM> may be determined based on diffusivity of these materials.

Further, optionally, when the conduction structure <NUM> further includes the second conduction part <NUM>, as shown in <FIG>, the fourth connection passage <NUM> and the fourth metal wire <NUM> form an integrated structure. On this basis, the diffusion barrier layer <NUM> may be further disposed on a side surface and a bottom surface of the integrated structure including the fourth connection passage <NUM> and the fourth metal wire <NUM>, and the bottom surface is close to the substrate <NUM>. A part of the diffusion barrier layer <NUM> that is located on a side surface and a bottom surface of the fourth connection passage <NUM> is located in the fourth via hole <NUM>.

Optionally, when the conduction structure <NUM> further includes the third conduction part <NUM>, as shown in <FIG>, the fifth connection passage <NUM> and the first metal wire <NUM> or the second metal wire <NUM> that is located on a side of the fifth connection passage <NUM> away from the substrate <NUM> and that is directly connected to the fifth connection passage <NUM> form an integrated structure. The diffusion barrier layer <NUM> may be further disposed on a side surface and a bottom surface of the integrated structure including the fifth connection passage <NUM> and one of the first metal wire <NUM> and the second metal wire <NUM>, and the bottom surface is close to the substrate <NUM>. A part of the diffusion barrier layer <NUM> that is located on a side surface and a bottom surface of the fifth connection passage <NUM> is located in the fifth via hole <NUM>.

<FIG> is a schematic diagram by using an example in which a fifth connection passage <NUM> and a first metal wire <NUM> form an integrated structure.

It should be noted that the foregoing describes only cases in which the diffusion barrier layer <NUM> is disposed at a position of the conduction structure <NUM>. For circuit wiring and related via holes, a corresponding diffusion barrier layer <NUM> may also be disposed based on a used interconnect metal material. Details are not described in this application. <FIG> is used as an example. It may be seen from the cross-sectional view that the third wiring layer <NUM> has circuit wiring. Therefore, as shown in <FIG>, the diffusion barrier layer <NUM> may also be disposed on a side surface and a bottom surface of circuit wiring of the third wiring layer <NUM>.

Optionally, as shown in <FIG> and <FIG>, a dielectric layer <NUM> disposed between adjacent wiring layers includes at least a first sublayer <NUM> and a second sublayer <NUM>, where the second sublayer <NUM> is an etch barrier layer and is disposed on a side of the first sublayer <NUM> close to the substrate <NUM>.

The second sublayer <NUM> is disposed on the side of the first sublayer <NUM> close to the substrate <NUM>, that is, the second sublayer <NUM> is formed, and then the first sublayer <NUM> is formed.

The dielectric layer <NUM> includes the first sublayer <NUM> and the second sublayer <NUM>, where the second sublayer <NUM> is an etch barrier layer and is disposed on the side of the first sublayer <NUM> close to the substrate <NUM>, thereby avoiding impact on a wiring layer formed when a wiring layer above (that is, a side away from the substrate <NUM>) the dielectric layer <NUM> is formed.

Further, optionally, a material of the first sublayer <NUM> is a material of a low dielectric constant or an ultra-low dielectric constant.

It should be noted that a dielectric of a low dielectric constant or an ultra-low dielectric constant is a dielectric material whose dielectric constant value is less than a dielectric constant (the dielectric constant is <NUM> to <NUM>) of silicon dioxide.

When the material of the first sublayer <NUM> is the material of a low dielectric constant or an ultra-low dielectric constant, a parasitic capacitance between adjacent wiring layers can be reduced.

This application further provides a memory. As shown in <FIG>, the memory includes a storage area <NUM>, and the storage area <NUM> includes several storage units <NUM> disposed on a substrate <NUM>. As shown in <FIG>, each storage unit <NUM> includes a transistor <NUM> disposed on the substrate <NUM> and an MTJ storage element <NUM> electrically connected to the transistor <NUM>.

As shown in <FIG>, the MTJ storage element <NUM> includes a bottom electrode <NUM>, a top electrode <NUM>, and an MTJ <NUM> located between the bottom electrode <NUM> and the top electrode <NUM>. The bottom electrode <NUM> is electrically connected to a drain electrode <NUM> of the transistor <NUM> by using a conduction structure <NUM>. A plurality of wiring layers are disposed between the transistor <NUM> and the MTJ storage element <NUM> in the storage area <NUM>, and a dielectric layer <NUM> is filled between adjacent wiring layers and between a wiring layer closest to the transistor <NUM> and the transistor <NUM>.

Still referring to <FIG>, the conduction structure <NUM> includes a first conduction part <NUM>. The first conduction part <NUM> includes a first metal wire <NUM> and a first via hole <NUM>. The plurality of wiring layers include a first wiring layer <NUM> and a second wiring layer <NUM>, and the second wiring layer <NUM> is disposed between the first wiring layer <NUM> and the transistor <NUM>. The first wiring layer <NUM> includes the first metal wire <NUM>, and the first via hole <NUM> penetrates a dielectric layer <NUM> and the second wiring layer <NUM> that are located between the first wiring layer <NUM> and the transistor <NUM>. A first connection passage <NUM> is disposed in the first via hole <NUM>, the first connection passage <NUM> is directly connected to the first metal wire <NUM> and the drain electrode <NUM> of the transistor <NUM>, and the first connection passage <NUM> is not directly connected to a metal wire at the second wiring layer <NUM>.

It should be noted that, for the second wiring layer <NUM>, the first via hole <NUM> penetrates the second wiring layer <NUM>, but the first connection passage <NUM> disposed in the first via hole <NUM> is not directly connected to the metal wire at the second wiring layer <NUM>. That is, no metal wire is disposed at a position that is of the second wiring layer <NUM> and that is corresponding to the first via hole <NUM>, so as to meet this condition.

Referring to <FIG>, in addition to the drain electrode <NUM>, the transistor <NUM> further includes a source electrode <NUM>, a gate dielectric layer <NUM>, and a gate electrode <NUM>. To distinguish between the two electrodes other than the gate electrode <NUM> of the transistor <NUM>, one electrode is referred to as the source electrode <NUM>, and the other electrode is referred to as the drain electrode <NUM>.

For example, as shown in <FIG>, the transistor <NUM> may further include a source electrode region <NUM> and a drain electrode region <NUM>. The source electrode region <NUM> is in contact with the source electrode <NUM>, the drain electrode region <NUM> is in contact with the drain electrode <NUM>, and a region between the source electrode region <NUM> and the drain electrode region <NUM> is a passage region. The source electrode region <NUM> and the drain electrode region <NUM> may be obtained by performing a doping process on the substrate <NUM>. In this case, the substrate <NUM> is a semiconductor material.

Optionally, the transistor <NUM> controls writing, changing, or reading of information in the storage unit <NUM>. That is, the transistor <NUM> is used as a selector device to control writing, changing, or reading of information in the storage unit <NUM>.

In the memory, in the conduction structure <NUM> used to electrically connect the drain electrode <NUM> of the transistor <NUM> to the bottom electrode <NUM> of the MTJ storage element <NUM>, the first via hole <NUM> of the first conduction part <NUM> penetrates the second wiring layer <NUM> between the first wiring layer <NUM> and the transistor <NUM>, so that the first connection passage <NUM> disposed in the first via hole <NUM> is directly connected to the first metal wire <NUM> and the drain electrode <NUM> of the transistor <NUM>. Therefore, compared with the case that the first metal wire <NUM> and the drain electrode <NUM> of the transistor <NUM> are electrically connected by using the metal wire that is located between the first metal wire <NUM> and the drain electrode <NUM> of the transistor <NUM> and that is disposed at the second wiring layer <NUM>, space occupied by the metal wire at the second wiring layer <NUM> can be released in this application. On this basis, in one aspect, the space released by the second wiring layer <NUM> may be used for circuit wiring, so as to ease overall circuit wiring congestion. In another aspect, after a metal wire that is on the second wiring layer <NUM> and that is used to connect the drain electrode <NUM> to the first metal wire <NUM> is omitted, when a minimum distance of wiring is met, an area occupied by each storage unit <NUM> can be reduced, and therefore, integration density of the memory can be improved. In still another aspect, resistance of the via hole mainly comes from an interface between the via hole and a metal in contact with a lower part (close to the substrate <NUM>) of the via hole. In this application, because the first via hole <NUM> crosses the second wiring layer <NUM>, no interface exists between the first via hole <NUM> and the metal wire at the second wiring layer <NUM>, lower resistance is caused, and a parasitic capacitance can be reduced, thereby improving overall performance of the memory.

Optionally, as shown in <FIG>, there are at least two first conduction parts <NUM>, and all the first conduction parts <NUM> are disposed along a thickness direction of the substrate <NUM>. Any adjacent first conduction parts <NUM> are directly connected.

Based on different positions of the MTJ storage element <NUM>, in particular, when the MTJ storage element <NUM> is integrated in a back end of line process, at least two first conduction parts <NUM> may be disposed in the conduction structure <NUM>, so as to improve integration density of the memory.

According to the invention (second aspect; claim <NUM>), as shown in <FIG>, the conduction structure <NUM> further includes a second conduction part <NUM>. The second conduction part <NUM> is disposed on a side of the first conduction part <NUM> away from the substrate <NUM>. The second conduction part <NUM> includes a fourth metal wire <NUM> and a fourth via hole <NUM>. The plurality of wiring layers further include a fourth wiring layer <NUM>, and the fourth wiring layer <NUM> includes a fourth metal wire <NUM>. The fourth via hole <NUM> penetrates a dielectric layer <NUM> between the fourth wiring layer <NUM> and the first conduction part <NUM>. A fourth connection passage <NUM> is disposed in the fourth via hole <NUM>, and the fourth connection passage <NUM> is directly connected to the fourth metal wire <NUM> and the first metal wire <NUM>.

A length direction of the fourth metal wire <NUM> may be parallel to a length direction of the first metal wire <NUM>.

It should be noted that the fourth via hole <NUM> penetrates the dielectric layer <NUM> between the fourth wiring layer <NUM> and the first conduction part <NUM>, and the fourth connection passage <NUM> is directly connected to the fourth metal wire <NUM> and the first metal wire <NUM>. Therefore, it may be learned that the fourth wiring layer <NUM> and the first wiring layer <NUM> are disposed adjacent to each other in a direction of the substrate <NUM>, and the fourth wiring layer <NUM> is disposed on a side of the first wiring layer <NUM> away from the substrate <NUM>. The fourth wiring layer <NUM> is disposed adjacent to the first wiring layer <NUM>, that is, no other wiring layer is disposed between the fourth wiring layer <NUM> and the first wiring layer <NUM>.

In addition, regardless of a quantity of first conduction parts <NUM>, all first conduction parts <NUM> should be considered as a whole, and the second conduction part <NUM> is disposed between the first conduction part <NUM> and the MTJ storage element <NUM>. That is, when there are a plurality of first conduction parts <NUM>, the second conduction part <NUM> is disposed between a first conduction part <NUM> closest to the MTJ storage element <NUM> and the MTJ storage element <NUM>.

Optionally, as shown in <FIG>, there are at least two second conduction parts <NUM>, and all the second conduction parts <NUM> are disposed along the thickness direction of the substrate <NUM>. In all the second conduction parts <NUM>, a fourth connection passage <NUM> in a second conduction part <NUM> closest to the first conduction part <NUM> is directly connected to the fourth metal wire <NUM> and the first metal wire <NUM>. In any adjacent second conduction parts <NUM>, a fourth metal wire <NUM> and a fourth connection passage <NUM> that separately belong to the adjacent second conduction parts <NUM> are directly connected.

<FIG> is a schematic diagram by using an example in which two second conduction parts <NUM> are disposed in a conduction structure <NUM>.

Optionally, the first via hole <NUM> penetrates one second wiring layer <NUM> (shown in <FIG>) or two second wiring layers <NUM> (shown in <FIG>) between the first wiring layer <NUM> and the transistor <NUM>.

Optionally, as shown in <FIG>, in each first conduction part <NUM>, the first connection passage <NUM> and the first metal wire <NUM> that is directly connected to the first connection passage <NUM> form an integrated structure. On this basis, a diffusion barrier layer <NUM> is disposed on a side surface and a bottom surface of the integrated structure, and the bottom surface is close to the substrate <NUM>. A part of the diffusion barrier layer <NUM> that is located on a side surface and a bottom surface of the first connection passage <NUM> is located in the first via hole <NUM>.

Because some interconnect metal materials (such as Cu) are easy to diffuse, resulting in circuit performance degradation or failure, the diffusion barrier layer <NUM> needs to be disposed to prevent diffusion. For different metal conductive materials, different materials of the diffusion barrier layer <NUM> need to be used correspondingly, so as to ensure a barrier function of the diffusion barrier layer <NUM>, adhesion to the integrated structure and the dielectric layer <NUM>, and the like.

For example, when a material of the integrated structure is Cu, a TaN/Ta double-layer structure may be used as the diffusion barrier layer <NUM>, or a TaN/Co double-layer structure may be used as the diffusion barrier layer <NUM>.

It should be noted that the interconnect metal material applied to the memory in this application may be Co, Ru, W, or the like, and whether to dispose the diffusion barrier layer <NUM> may be determined based on diffusivity of these materials.

It should be noted that the foregoing describes only cases in which the diffusion barrier layer <NUM> is disposed at a position of the conduction structure <NUM>. For circuit wiring and related via holes, a corresponding diffusion barrier layer <NUM> may also be disposed based on a used interconnect metal material. Details are not described in this application. <FIG> is used as an example. It may be seen from the cross-sectional view that the first wiring layer <NUM> further has circuit wiring. Therefore, as shown in <FIG>, the diffusion barrier layer <NUM> may be disposed on a side surface and a bottom surface of circuit wiring of the third wiring layer <NUM>.

Optionally, as shown in <FIG>, a dielectric layer <NUM> disposed between adjacent wiring layers includes at least a first sublayer <NUM> and a second sublayer <NUM>, where the second sublayer <NUM> is an etch barrier layer and is disposed on a side of the first sublayer <NUM> close to the substrate <NUM>.

Claim 1:
A memory, comprising a storage area (<NUM>), wherein the storage area comprises several storage units (<NUM>) disposed on a substrate (<NUM>); each storage unit comprises a transistor (<NUM>) disposed on the substrate and a magnetic tunnel junction, MTJ (<NUM>), storage element electrically connected to the transistor;
the MTJ storage element comprises a bottom electrode (<NUM>), a top electrode (<NUM>), and an MTJ (<NUM>) located between the two, and the bottom electrode is electrically connected to a drain electrode (<NUM>) of the transistor by using a conduction structure (<NUM>);
a plurality of wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer (<NUM>) is filled between adjacent wiring layers;
the conduction structure comprises a first conduction part (<NUM>), and the first conduction part comprises a first metal wire (<NUM>), a second metal wire (<NUM>), and a first via hole (<NUM>) located between the first metal wire and the second metal wire; the plurality of wiring layers comprise a first wiring layer (<NUM>), a second wiring layer (<NUM>), and a third wiring layer (<NUM>), and the third wiring layer is disposed between the first wiring layer and the second wiring layer; the first wiring layer comprises the first metal wire, the second wiring layer comprises the second metal wire, and the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer; and a first connection passage is disposed in the first via hole, the first connection passage (<NUM>) is directly connected to the first metal wire and the second metal wire, and the first connection passage is not directly connected to a metal wire at the third wiring layer,
wherein the second via hole (<NUM>) is disposed in the storage area, and the second via hole penetrates the third wiring layer; and
the first via hole is adjacent to the second via hole, and no metal wire exists on a part that is of the third wiring layer and that is located between the first via hole and the second via hole..