Patent Description:
Ranging systems using an indirect time of flight (ToF) method have been known. In such a ranging system, signal charges obtained by receiving reflected light of active light that is emitted from a light emitting diode (LED) or a laser at a certain phase and is reflected by an object are distributed to different regions at high speed. Therefore, a sensor capable of the distribution is necessary.

In view of this, a technology has been suggested for enabling high-speed modulation of a wide region in a substrate of a sensor by applying voltage directly to the substrate and thus generating electric current in the substrate, for example (see PTL <NUM>, for example). Such a sensor is also called a current assisted photonic demodulator (CAPD) sensor.

<CIT> discloses that a part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and that electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels. A device known from the aforementioned document can also be provided with a first exhausting gate electrode and a second exhausting gate electrode. Said first and second exhausting gate electrodes are added so as to be oppositely arranged, along a direction orthogonal to a transfer direction of the signal charges.

<CIT> discloses a back-illuminated distance measuring sensor comprising a plurality of pixels, wherein each pixel comprises a photogate electrode, a first and a second gate electrodes provided adjacent to the photogate electrode, and a first and a second floating diffusion regions.

<CIT> discloses a solid-state imaging device that has a substrate and multiple photoelectric converters that are formed on the substrate. An insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film that has a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate. <NPL> discloses a CMOS Time-of-Flight (ToF) range imager using pinned-photodiode based high-speed <NUM>-tap lock-in pixels with lateral-electric-field charge modulators (LEFM) in a <NUM> CIS process. The proposed lock-in pixel structure using lateral electric field control is suitable for implementing a multiple-tap charge modulator while achieving high-speed charge transfer for high time resolution.

<CIT> discloses an image sensor that has a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region. The pixel cell unit has a fourth transfer gate transistor gate on the semiconductor surface coupled between a first infrared photodiode region and a second capacitance region.

However, it is difficult to obtain a CAPD sensor with sufficient characteristics by the above described technology.

For example, the above described CAPD sensor is a surface-illuminated sensor in which wiring lines and the like are disposed on the surface of the substrate on the side on which light from outside is received. To secure the photoelectric conversion region, it is desirable that there is no wiring line or the like that blocks the light path of incident light on the light receiving surface side of a photodiode (PD) or a photoelectric conversion portion. In a surface-illuminated CAPD sensor, however, wiring lines for extracting charges, various kinds of control lines, and signal lines are disposed on the light receiving surface side of a PD, depending on the structure. As a result, the photoelectric conversion region is limited. That is, it is difficult to secure a sufficient photoelectric conversion region, and characteristics such as the pixel sensitivity might be degraded. Further, in a case where a CAPD sensor is used in a place subjected to external light, the external light component becomes a noise component in the indirect ToF method in which ranging is performed with active light. Therefore, to secure a sufficient signal-to-noise ratio (SN ratio) and obtain distance information, it is necessary to secure a sufficient saturation signal amount (Qs). In a surface-illuminated CAPD sensor, however, there is a limitation on the wiring layout, and therefore, it is necessary to take a measure to use a technique not involving a wiring capacitor, such as providing an additional transistor for securing capacitance.

In many cases, near-infrared light of a wavelength of about <NUM>, which corresponds to a window of sunlight, is used as the light source. Near-infrared light has low quantum efficiency because the absorption coefficient of the silicon forming a semiconductor layer is low. Therefore, it is necessary to increase the thickness of the silicon forming the photoelectric conversion region. In a case where the silicon is thick, charges subjected to photoelectric conversion take a long time to reach the electrode for attracting the charges. After the distribution is switched, some charges reach the electrode in some cases, resulting in an erroneous signal. As a result, the ranging accuracy might become lower. In other words, the characteristics of the sensor might be degraded.

The present technology has been made in view of those circumstances, and is to enable improvement in the characteristics of a ToF sensor.

According to a first aspect, the present invention provides a light receiving element in accordance with independent claim <NUM>. According to a second aspect, the present invention provides an electronic apparatus in accordance with claim <NUM>. Further aspects are set forth in the dependent claims, the drawings and the following description.

According to the invention, characteristics can be improved.

Note that the effects of the present technology are not limited to the effects described herein, and may include any of the effects described in the present disclosure.

In the following, the expressions "an example configuration", "an embodiment of the present technology" and "the present technology", insofar as they do not refer to the present invention, refer to examples that may be useful for understanding the invention.

The following is descriptions of modes for carrying out the present technology. Note that explanation will be made in the following order.

<FIG> is a block diagram schematically showing an example configuration of a light receiving element to which the present technology is applied.

A light receiving element <NUM> shown in <FIG> is an element that outputs ranging information according to the indirect ToF method.

The light receiving element <NUM> receives light (reflected light) that is light (irradiation light) emitted from a predetermined light source has been incident on and then reflected by an object, and outputs a depth image in which information indicating the distance to the object is stored as a depth value. Note that the irradiation light emitted from the light source is infrared light having a wavelength of <NUM> to <NUM>, for example, and is pulse light that repeatedly turns on and off at predetermined intervals.

The light receiving element <NUM> includes a pixel array unit <NUM> formed on a semiconductor substrate (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit <NUM>. The peripheral circuit unit is formed with a vertical drive unit <NUM>, a column processing unit <NUM>, a horizontal drive unit <NUM>, and a system control unit <NUM>, for example.

The light receiving element <NUM> further includes a signal processing unit <NUM> and a data storage unit <NUM>. Note that the signal processing unit <NUM> and the data storage unit <NUM> may be mounted on the same substrate as the light receiving element <NUM>, or may be disposed on a substrate in a module different from the light receiving element <NUM>. The pixel array unit <NUM> generates charges corresponding to the amount of received light, and pixels <NUM> that output signals corresponding to the charges are two-dimensionally arranged in the row direction and the column direction in a matrix fashion. In other words, the pixel array unit <NUM> has a plurality of pixels <NUM> that photoelectrically convert incident light, and output signals corresponding to the resultant charges. The pixel <NUM> will be described later in detail, with reference to <FIG> and the subsequent drawings.

Here, the row direction refers to the array direction of the pixels <NUM> in the horizontal direction, and the column direction refers to the array direction of the pixels <NUM> in the vertical direction. The row direction is the lateral direction in the drawing, and the column direction is the longitudinal direction in the drawing.

In the matrix-like pixel array of the pixel array unit <NUM>, pixel drive lines <NUM> are arranged in the row direction for the respective pixel rows, and two vertical signal lines <NUM> are arranged in the column direction for each pixel column. For example, the pixel drive lines <NUM> transmit drive signals for performing driving when signals are read from the pixels <NUM>. Note that, in <FIG>, each pixel drive line <NUM> is shown as one wiring line, but is not necessarily one wiring line. One end of each of the pixel drive lines <NUM> is connected to the output end of the vertical drive unit <NUM> corresponding to the respective rows.

The vertical drive unit <NUM> is formed with a shift register, an address decoder, and the like, and drives the respective pixels <NUM> in the pixel array unit <NUM> collectively or row by row, for example. In other words, the vertical drive unit <NUM>, together with the system control unit <NUM> that controls the vertical drive unit <NUM>, forms a drive unit that controls operations of the respective pixels <NUM> in the pixel array unit <NUM>.

Detection signals output from the respective pixels <NUM> in the pixel row according to the drive control performed by the vertical drive unit 22are input to the column processing unit <NUM> through the vertical signal lines <NUM> The column processing unit <NUM> performs predetermined signal processing on the detection signals output from the respective pixels <NUM> through the vertical signal lines <NUM>, and temporarily stores the detection signals subjected to the signal processing. Specifically, the column processing unit <NUM> performs a noise removal process, an analog-to-digital (AD) conversion process, and the like as the signal processing.

The horizontal drive unit <NUM> is formed with a shift register, an address decoder, and the like, and sequentially selects the unit circuits corresponding to the pixel columns of the column processing unit <NUM>. Through this selective scanning performed by the horizontal drive unit <NUM>, the detection signals subjected to the signal processing by the column processing unit <NUM> for the respective unit circuits are sequentially output.

The system control unit <NUM> includes a timing generator that generates various timing signals, and performs drive control on the vertical drive unit <NUM>, the column processing unit <NUM>, the horizontal drive unit <NUM>, and the like, on the basis of the various timing signals generated by the timing generator.

The signal processing unit <NUM> has at least an arithmetic processing function, and performs various kinds of signal processing such as arithmetic processing, on the basis of the detection signals that are output from the column processing unit <NUM>. The data storage unit <NUM> temporarily stores the data necessary for the signal processing to be performed by the signal processing unit <NUM>.

The light receiving element <NUM> configured as described above outputs a depth image in which information indicating the distance to the object is stored as a depth value in a pixel value. The light receiving element <NUM> is mounted on a vehicle, for example, and may be mounted on an in-vehicle system that measures the distance to an object outside the vehicle, a gesture recognition device that measures the distance to an object such as the user's hand and recognizes a gesture of the user from the result of the measurement, or the like.

<FIG> is a cross-sectional view showing a first example configuration of the pixels <NUM> arranged in the pixel array unit <NUM>.

According to the present invention, the light receiving element <NUM> includes a semiconductor substrate <NUM> and a multilayer wiring layer <NUM> formed on the front surface side (the lower side in the drawing).

The semiconductor substrate <NUM> is formed with silicon (Si), for example, and has a thickness of <NUM> to <NUM>, for example. In the semiconductor substrate <NUM>, N-type (a second conductivity type) semiconductor regions <NUM> are formed pixel by pixel in a P-type (a first conductivity type) semiconductor region <NUM>, for example, so that photodiodes PD are formed on a pixel-by-pixel basis. The P-type semiconductor region <NUM> provided on both the front and back surfaces of the semiconductor substrate <NUM> also serves as a hole charge storage region for reducing dark current.

The upper surface of the semiconductor substrate <NUM>, which is the upper side in <FIG>, is the back surface of the semiconductor substrate <NUM>, and is a light incident surface through which light enters. An antireflective film <NUM> is formed on the upper surface on the back surface side of the semiconductor substrate <NUM>.

The antireflective film <NUM> has a stack structure in which a fixed charge film and an oxide film are stacked, for example, and a high-dielectric-constant (high-k) insulating thin film formed by atomic layer deposition (ALD), for example, may be used as the antireflective film <NUM>. Specifically, hafnium oxide (HfO<NUM>), aluminum oxide (Al<NUM>O<NUM>), titanium oxide (TiO<NUM>), strontium titan oxide (STO), or the like may be used. In the example illustrated in <FIG>, the antireflective film <NUM> is formed with a hafnium oxide film <NUM>, an aluminum oxide film <NUM>, and a silicon oxide film <NUM> that are stacked.

Interpixel light blocking films <NUM> that prevent incident light from entering adjacent pixels are formed on the upper surface of the antireflective film <NUM> and at the boundary portions <NUM> (hereinafter also referred to as the pixel boundary portions <NUM>) between the pixels <NUM> adjacent to one another in the semiconductor substrate <NUM>. The material of the interpixel light blocking films <NUM> may be any material that blocks light, and it is possible to use a metal material such as tungsten (W), aluminum (Al), or copper (Cu), for example.

On the upper surface of the antireflective film <NUM> and the upper surfaces of the interpixel light blocking films <NUM>, a planarization film <NUM> is formed with an insulating film of silicon oxide (SiO<NUM>), silicon nitride (SiN), silicon oxynitride (SiON), or the like, or an organic material such as resin, for example.

Further, on-chip lenses <NUM> are formed on the upper surfaces of the planarization film <NUM> for the respective pixels. For example, the on-chip lenses <NUM> are formed with a resin material such as styrene resin, acrylic resin, styrene-acrylic copolymer resin, or siloxane resin. The light gathered by the on-chip lenses <NUM> is efficiently made to enter the photodiode PD.

Further, at the pixel boundary portions <NUM> on the back surface side of the semiconductor substrate <NUM>, interpixel separation portions <NUM> that separate adjacent pixels from one another are formed in the depth direction of the semiconductor substrate <NUM>, to reach a predetermined depth in the substrate depth direction from the back surface side of the semiconductor substrate <NUM> (on the side of the on-chip lenses <NUM>). The outer peripheral portions including the bottom and side walls of the interpixel separation portions <NUM> are covered with the hafnium oxide film <NUM>, which is part of the antireflective film <NUM>. The interpixel separation portions <NUM> prevent incident light from reaching the adjacent pixels <NUM>, and confine the incident light in the respective pixels. The interpixel separation portions <NUM> also prevent leakage of incident light from the adjacent pixels <NUM>.

In the example illustrated in <FIG>, the silicon oxide film <NUM>, which is the material of the uppermost layer of the antireflective film <NUM>, is buried in trenches (grooves) dug from the back surface side, so that the silicon oxide film <NUM> and the interpixel separation portions <NUM> are simultaneously formed. Accordingly, the silicon oxide film <NUM>, which is part of the stack film serving as the antireflective film <NUM>, is formed with the same material as the interpixel separation portions <NUM>, but is not necessarily formed with the same material. The material to be buried as the interpixel separation portions <NUM> in the trenches (grooves) dug from the back surface side may be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN), for example.

According to the invention, on the front surface side of the semiconductor substrate <NUM> on which the multilayer wiring layer <NUM> is formed, two transfer transistors TRG1 and TRG2 are formed for the one photodiode PD formed in each pixel <NUM>. Further, on the front surface side of the semiconductor substrate <NUM>, floating diffusion regions FD1 and FD2 as charge storage portions that temporarily hold the charges transferred from the photodiodes PD are formed with high-concentration N-type semiconductor regions (N-type diffusion regions).

The multilayer wiring layer <NUM> includes a plurality of metal films M and an interlayer insulating film <NUM> between the metal films M. <FIG> shows an example in which the metal films M include three layers: a first metal film M1 through a third metal film M3.

Of the plurality of metal films M in the multilayer wiring layer <NUM>, a region of the first metal film M1 closest to the semiconductor substrate <NUM> and located below the formation region of each photodiode PD, or the region overlapping at least part of the formation region of each photodiode PD in plan view, has a metal wiring line of copper, aluminum, or the like formed as a light blocking member <NUM>.

The light blocking member <NUM> blocks infrared light that has entered the semiconductor substrate <NUM> from the light incident surface via the on-chip lens <NUM>, and passed through the semiconductor substrate <NUM> without being photoelectrically converted in the semiconductor substrate <NUM>, with the first metal film M1 closest to the semiconductor substrate <NUM>, so that the infrared light does not reach the second metal film M2 and the third metal film M3 located below the first metal film M1. By virtue of this light blocking function, the infrared light that has not been photoelectrically converted in the semiconductor substrate <NUM> and has passed through the semiconductor substrate <NUM> is prevented from being scattered by the metal films M below the first metal film M1 and entering the neighboring pixels. Thus, it is possible to prevent erroneous light detection at the neighboring pixels.

Further, the light blocking members <NUM> also has a function to reflect infrared light that has entered the semiconductor substrate <NUM> from the light incident surface via the on-chip lenses <NUM> and passed through the semiconductor substrate <NUM> without being photoelectrically converted in the semiconductor substrate <NUM>, so that the infrared light reenters the semiconductor substrate <NUM>. In view of this, the light blocking members <NUM> may also be regarded as reflective members. With this reflective function, the amount of infrared light to be photoelectrically converted in the semiconductor substrate <NUM> can be increased, and the quantum efficiency (QE), which is the sensitivity of the pixels <NUM> to infrared light, can be improved.

Note that the light blocking members <NUM> may also form a structure that reflects or blocks light with polysilicon, an oxide film, or the like, other than a metal material.

Further, each light blocking member <NUM> may not be formed with a single metal film M, but may be formed with a plurality of metal films M, such as a grid-like structure formed with the first metal film M1 and the second metal film M2, for example.

Of the plurality of metal films M in the multilayer wiring layer <NUM>, a predetermined metal film M, such as the second metal film M2, has wiring capacitors <NUM> that are patterns formed in a comb-like shape, for example. The light blocking members <NUM> and the wiring capacitors <NUM> may be formed in the same layer (metal film M). In a case where the light blocking members <NUM> and the wiring capacitors <NUM> are formed in different layers, however, the wiring capacitors <NUM> formed in a layer farther from the semiconductor substrate <NUM> than the light blocking members <NUM>. In other words, the light blocking members <NUM> are formed closer to the semiconductor substrate <NUM> than the wiring capacitors <NUM>. As described above, the light receiving element <NUM> has a back-illuminated structure in which the semiconductor substrate <NUM> that is a semiconductor layer is disposed between the on-chip lenses <NUM> and the multilayer wiring layer <NUM>, and incident light is made to enter the photodiodes PD from the back surface side on which the on-chip lenses <NUM> are formed.

Further, according to the invention, the pixels <NUM> each include two transfer transistors TRG1 and TRG2 for the photodiode PD provided in each pixel, and are designed to be capable of distributing charges (electrons) generated through photoelectric conversion performed by the photodiode PD to the floating diffusion region FD1 or FD2.

Furthermore, the pixels <NUM> in the first example configuration have the interpixel separation portions <NUM> formed at the pixel boundary portions <NUM>, to prevent incident light from reaching the adjacent pixels <NUM>, and prevent leakage of incident light from the adjacent pixels <NUM> while confining the incident light in the respective pixels. The light blocking members <NUM> are then formed in a metal film M below the formation regions of the photodiodes PD, so that infrared light that has passed through the semiconductor substrate <NUM> without being photoelectrically converted in the semiconductor substrate <NUM> is reflected by the light blocking members <NUM> and is made to reenter the semiconductor substrate <NUM>.

With the above configuration, the amount of infrared light to be photoelectrically converted in the semiconductor substrate <NUM> can be increased, and the quantum efficiency (QE), which is the sensitivity of the pixels <NUM> to infrared light, can be improved.

<FIG> shows the circuit configuration of each of the pixels <NUM> two-dimensionally arranged in the pixel array unit <NUM>.

A pixel <NUM> includes a photodiode PD as a photoelectric conversion element. The pixel <NUM> also includes two sets of a transfer transistor TRG, a floating diffusion region FD, an additional capacitor FDL, a switch transistor FDG, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL. According to the invention, the pixel <NUM> further includes a charge ejection transistor OFG.

Here, in a case where the two sets of a transfer transistor TRG, a floating diffusion region FD, an additional capacitor FDL, a switch transistor FDG, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL are distinguished from each other in the pixel <NUM>, the transistors are referred to as transfer transistors TRG1 and TRG2, floating diffusion regions FD1 and FD2, additional capacitors FDL1 and FDL2, switch transistors FDG1 and FDG2, amplification transistors AMP1 and AMP2, reset transistors RST1 and RST2, and selection transistors SEL1 and SEL2, as shown in <FIG>. The transfer transistors TRG, the switch transistors FDG, the amplification transistors AMP, the selection transistors SEL, the reset transistors RST, and the charge ejection transistor OFG include N-type MOS transistors, for example.

When a transfer drive signal TRGlg supplied to the gate electrode of the transfer transistor TRG1 enters an active state, the transfer transistor TRG1 enters a conductive state, to transfer the charges accumulated in the photodiode PD to the floating diffusion region FD1. When a transfer drive signal TRG2g supplied to the gate electrode of the transfer transistor TRG2 enters an active state, the transfer transistor TRG2 enters a conductive state, to transfer the charges accumulated in the photodiode PD to the floating diffusion region FD2. The floating diffusion regions FD1 and FD2 are charge storage portions that temporarily hold the charge transferred from the photodiode PD. When an FD drive signal FDGlg supplied to the gate electrode of the switch transistor FDG1 enters an active state, the switch transistor FDG1 enters a conductive state, to connect the additional capacitor FDL1 to the floating diffusion region FD1. When an FD drive signal FDG2g supplied to the gate electrode of the switch transistor FDG2 enters an active state, the switch transistor FDG2 enters a conductive state, to connect the additional capacitor FDL2 to the floating diffusion region FD2. The additional capacitors FDL1 and FDL2 are formed with the wiring capacitor <NUM> shown in <FIG>.

When a reset drive signal RSTg supplied to the gate electrode of the reset transistor RST1 enters an active state, the reset transistor RST1 enters a conductive state, to reset the potential of the floating diffusion region FD1. When a reset drive signal RSTg supplied to the gate electrode of the reset transistor RST2 enters an active state, the reset transistor RST2 enters a conductive state, to reset the potential of the floating diffusion region FD2. Note that, when the reset transistors RST1 and RST2 are made to enter an active state, the switch transistors FDG1 and FDG2 are also made to enter an active state at the same time, and further, the additional capacitors FDL1 and FDL2 are reset.

For example, at a high-illuminance time at which the amount of incident light is large, the vertical drive unit <NUM> causes the switch transistors FDG1 and FDG2 to enter an active state, to connect the floating diffusion region FD1 and the additional capacitor FDL1, and connect the floating diffusion region FD2 and the additional capacitor FDL2. Thus, more charges can be accumulated at a high-illuminance time. At a low-illuminance time at which the amount of incident light is small, on the other hand, the vertical drive unit <NUM> causes the switch transistors FDG1 and FDG2 to enter an inactive state, to disconnect the additional capacitors FDL1 and FDL2 from the floating diffusion regions FD1 and FD2, respectively. Thus, conversion efficiency can be increased.

When an ejection drive signal OFGlg supplied to the gate electrode of the charge ejection transistor OFG enters an active state, the charge ejection transistor OFG enters a conductive state, to eject the charges accumulated in the photodiode PD.

When the source electrode of the amplification transistor AMP1 is connected to a vertical signal line 29A via the selection transistor SEL1, the amplification transistor AMP1 is connected to a constant current source (not shown), to form a source follower circuit. When the source electrode of the amplification transistor AMP2 is connected to a vertical signal line 29B via the selection transistor SEL2, the amplification transistor AMP2 is connected to a constant current source (not shown), to form a source follower circuit.

The selection transistor SEL1 is connected between the source electrode of the amplification transistor AMP1 and the vertical signal line 29A. When a selection signal SELlg supplied to the gate electrode of the selection transistor SEL1 enters an active state, the selection transistor SEL1 enters a conductive state, to output a detection signal VSL1 output from the amplification transistor AMP1 to the vertical signal line 29A.

The selection transistor SEL2 is connected between the source electrode of the amplification transistor AMP2 and the vertical signal line 29B. When a selection signal SEL2g supplied to the gate electrode of the selection transistor SEL2 enters an active state, the selection transistor SEL2 enters a conductive state, to output a detection signal VSL2 output from the amplification transistor AMP2 to the vertical signal line 29B.

The transfer transistors TRG1 and TRG2, the switch transistors FDG1 and FDG2, the amplification transistors AMP1 and AMP2, the selection transistors SEL1 and SEL2, and the charge ejection transistor OFG of the pixel <NUM> are controlled by the vertical drive unit <NUM>.

In the pixel circuit shown in <FIG>, the additional capacitors FDL1 and FDL2, and the switch transistors FDG1 and FDG2 that control connection of the additional capacitors FDL1 and FDL2 may be omitted. However, as the additional capacitors FDL are provided and are appropriately used depending on the amount of incident light, a high dynamic range can be secured.

Operation of the pixel <NUM> is now briefly described.

First, before light reception is started, a reset operation for resetting the charges in the pixel <NUM> is performed in all the pixels. Specifically, the charge ejection transistor OFG, the reset transistors RST1 and RST2, and the switch transistors FDG1 and FDG2 are turned on, and the stored charges in the photodiode PD, the floating diffusion regions FD1 and FD2, and the additional capacitors FDL1 and FDL2 are ejected.

After the stored charges are ejected, light reception is started in all the pixels.

During the light reception period, the transfer transistors TRG1 and TRG2 are alternately driven. Specifically, during a first period, control is performed, to turn on the transfer transistor TRG1, and turn off the transfer transistor TRG2. During the first period, the charges generated in the photodiode PD are transferred to the floating diffusion region FD1. During a second period following the first period, control is performed, to turn off the transfer transistor TRG1, and turn on the transfer transistor TRG2. During the second period, the charges generated in the photodiode PD are transferred to the floating diffusion region FD2. As a result, the charges generated in the photodiode PD are distributed to the floating diffusion regions FD1 and FD2, and are accumulated therein.

Here, the transfer transistor TRG and the floating diffusion region FD from which charges (electrons) obtained through photoelectric conversion are read out are also referred to as the active tap. Conversely, the transfer transistor TRG and the floating diffusion region FD from which no charges obtained through photoelectric conversion are read out are also referred to as the inactive tap.

When the light reception period comes to an end, the respective pixels <NUM> in the pixel array unit <NUM> are then selected in the order of the lines. In the selected pixel <NUM>, the selection transistors SEL1 and SEL2 are turned on. As a result, the charges accumulated in the floating diffusion region FD1 are output as the detection signal VSL1 to the column processing unit <NUM> via the vertical signal line 29A. The charges accumulated in the floating diffusion region FD2 are output as the detection signal VSL2 to the column processing unit <NUM> via the vertical signal line 29B.

One light receiving operation is completed in the above manner, and the next light receiving operation starting from a reset operation is then performed.

The reflected light to be received by the pixel <NUM> is delayed from the time when the light source emitted light, in accordance with the distance to the object. Since the distribution ratio between the charges accumulated in the two floating diffusion regions FD1 and FD2 varies depending on the delay time corresponding to the distance to the object, the distance to the object can be calculated from the distribution ratio between the charges accumulated in the two floating diffusion regions FD1 and FD2.

<FIG> is a plan view showing an example of arrangement in the pixel circuit shown in <FIG>.

The lateral direction in <FIG> corresponds to the row direction (horizontal direction) in <FIG>, and the longitudinal direction corresponds to the column direction (vertical direction) in <FIG>.

As shown in <FIG>, the photodiode PD is formed with an N-type semiconductor region <NUM> in the central region of the rectangular pixel <NUM>.

Outside the photodiode PD, the transfer transistor TRG1, the switch transistor FDG1, the reset transistor RST1, the amplification transistor AMP1, and the selection transistor SEL1 are linearly arranged along a predetermined side of the four sides of the rectangular pixel <NUM>, and the transfer transistor TRG2, the switch transistor FDG2, the reset transistor RST2, the amplification transistor AMP2, and the selection transistor SEL2 are linearly arranged along another side of the four sides of the rectangular pixel <NUM>.

Further, the charge ejection transistor OFG is disposed along a side different from the two sides of the pixel <NUM> along which the transfer transistors TRG, the switch transistors FDG, the reset transistors RST, the amplification transistors AMP, and the selection transistors SEL are formed.

Note that the arrangement in the pixel circuit shown in <FIG> is not limited to this example, and may be some other arrangement.

<FIG> shows another example circuit configuration of each pixel <NUM>.

In <FIG>, the components equivalent to those shown in <FIG> are denoted by the same reference numerals as those used in <FIG>, and explanation of the components will not be repeated below.

A pixel <NUM> includes a photodiode PD as a photoelectric conversion element. The pixel <NUM> also includes two sets of a first transfer transistor TRGa, a second transfer transistor TRGb, a memory MEM, a floating diffusion region FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

Here, in a case where the two sets of a first transfer transistor TRGa, a second transfer transistor TRGb, a memory MEM, a floating diffusion region FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL are distinguished from each other in the pixel <NUM>, the transistors are referred to as first transfer transistors TRGa1 and TRGa2, second transfer transistors TRGb1 and TRGb2, transfer transistors TRG1 and TRG2, memories MEM1 and MEM2, floating diffusion regions FD1 and FD2, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2, as shown in <FIG>. Accordingly, the pixel circuit in <FIG> differs from the pixel circuit in <FIG> in that the transfer transistors TRG are replaced with the two kinds transfer transistors, which are the first transfer transistors TRGa and the second transfer transistors TRGb, and the memories MEM are added. Further, the additional capacitors FDL and the switch transistors FDG are omitted.

The first transfer transistors TRGa, the second transfer transistors TRGb, the reset transistors RST, the amplification transistors AMP, and the selection transistors SEL include N-type MOS transistors, for example.

In the pixel circuit shown in <FIG>, charges generated in the photodiode PD are transferred to and held in the floating diffusion regions FD1 and FD2. In the pixel circuit in <FIG>, on the other hand, charges generated in the photodiode PD are transferred to and held in the memories MEM1 and MEM2 provided as charge storage portions. Specifically, when a first transfer drive signal TRGa1g supplied to the gate electrode of the first transfer transistor TRGa1 enters an active state, the first transfer transistor TRGa1 enters a conductive state, to transfer the charges accumulated in the photodiode PD to the memory MEM1. When a first transfer drive signal TRGa2g supplied to the gate electrode of the first transfer transistor TRGa2 enters an active state, the first transfer transistor TRGa2 enters a conductive state, to transfer the charges accumulated in the photodiode PD to the memory MEM2.

Further, when a second transfer drive signal TRGb1g supplied to the gate electrode of the second transfer transistor TRGb1 enters an active state, the second transfer transistor TRGb1 enters a conductive state, to transfer the charges accumulated in the memory MEM1 to the floating diffusion region FD1. When a second transfer drive signal TRGb2g supplied to the gate electrode of the second transfer transistor TRGb2 enters an active state, the second transfer transistor TRGb2 enters a conductive state, to transfer the charges accumulated in the memory MEM2 to the floating diffusion region FD2. When a reset drive signal RST1g supplied to the gate electrode of the reset transistor RST1 enters an active state, the reset transistor RST1 enters a conductive state, to reset the potential of the floating diffusion region FD1. When a reset drive signal RST2g supplied to the gate electrode of the reset transistor RST2 enters an active state, the reset transistor RST2 enters a conductive state, to reset the potential of the floating diffusion region FD2. Note that, when the reset transistors RST1 and RST2 are made to enter an active state, the second transfer transistors TRGb1 and TRGb2 are also made to enter an active state at the same time, and further, the memories MEM1 and MEM2 are reset.

In the pixel circuit in <FIG>, the charges generated in the photodiode PD are distributed to the memories MEM1 and MEM2, and are accumulated therein. At the timing of readout, the charges stored in the memories MEM1 and MEM2 are then transferred to the floating diffusion regions FD1 and FD2, respectively, and are output from the pixel <NUM>.

Outside the photodiode PD, the first transfer transistor TRGa1, the second transfer transistor TRGb1, the reset transistor RST1, the amplification transistor AMP1, and the selection transistor SEL1 are linearly arranged along a predetermined side of the four sides of the rectangular pixel <NUM>, and the first transfer transistor TRGa2, the second transfer transistor TRGb2, the reset transistor RST2, the amplification transistor AMP2, and the selection transistor SEL2 are linearly arranged along another side of the four sides of the rectangular pixel <NUM>. The memories MEM1 and MEM2 are formed with buried N-type diffusion regions, for example.

With the light receiving element <NUM> described above, the following effects can be achieved.

First, since the light receiving element <NUM> is of a back-illuminated type, quantum efficiency (QE) × aperture ratio (fill factor (FF)) can be maximized, and the ranging characteristics of the light receiving element <NUM> can be improved.

For example, as indicated by an arrow W11 in <FIG>, a normal surface-illuminated image sensor has a structure in which wiring lines <NUM> and wiring lines <NUM> are formed on the light incident surface side through which light from outside enters a PD <NUM> that is a photoelectric conversion portion.

Therefore, part of light that obliquely enters the PD <NUM> from outside at a certain angle as shown by an arrow A21 and an arrow A22, for example, might be blocked by the wiring lines <NUM> or the wiring lines <NUM>, and does not enter the PD <NUM>.

On the other hand, a back-illuminated image sensor has a structure in which wiring lines <NUM> and wiring lines <NUM> are formed on the surface on the opposite side from the light incident surface through which light from outside enters a PD <NUM> that is a photoelectric conversion portion, as indicated by an arrow W12, for example.

Accordingly, it is possible to secure a sufficient aperture ratio, compared with that in a case with a surface-illuminated type. Specifically, as indicated by an arrow A23 and an arrow A24, for example, light obliquely incident on the PD <NUM> at a certain angle enters the PD <NUM> from outside without being blocked by any wiring line. Thus, a larger amount of light can be received, and pixel sensitivity can be improved.

The pixel sensitivity improving effect achieved with such a back-illuminated type can also be achieved with the light receiving element <NUM>, which is a back-illuminated ToF sensor.

Specifically, in the structure of a surface-illuminated ToF sensor, wiring lines <NUM> and wiring lines <NUM> are formed on the light incident surface side of a PD <NUM> that is a photoelectric conversion portion, as indicated by an arrow W13. Therefore, part of light that obliquely enters the PD <NUM> from outside at a certain angle as shown by an arrow A25 and an arrow A26, for example, might be blocked by the wiring lines <NUM> or the wiring lines <NUM> or the like, and does not enter the PD <NUM>.

On the other hand, a back-illuminated ToF sensor has a structure in which transfer transistors for reading out charges are formed on the surface on the opposite side from the light incident surface of a PD <NUM> that is a photoelectric conversion portion, as indicated by an arrow W14, for example. Further, wiring lines <NUM> and wiring lines <NUM> are formed on the surface on the opposite side from the light incident surface of the PD <NUM>. With this arrangement, as indicated by an arrow A28 and an arrow A29, for example, light obliquely incident on the PD <NUM> at a certain angle enters the PD <NUM> without being blocked by any wiring line.

Accordingly, in the back-illuminated ToF sensor, a sufficient aperture ratio can be secured compared with that in a case with a surface-illuminated ToF sensor. Thus, quantum efficiency (QE) × aperture ratio (FF) can be maximized, and the ranging characteristics can be improved. <FIG> shows cross-sectional views of pixels of a surface-illuminated ToF sensor and a back-illuminated ToF sensor.

In the surface-illuminated ToF sensor on the left side in <FIG>, the upper side of a substrate <NUM> in the drawing is the light incident surface, and a wiring layer <NUM> including a plurality of wiring lines, an interpixel light blocking film <NUM>, and an on-chip lens <NUM> are stacked on the light incident surface side of the substrate <NUM>.

In the back-illuminated ToF sensor on the right side in <FIG>, a wiring layer <NUM> including a plurality of wiring lines is formed on the lower side of a substrate <NUM> on the opposite side from the light incident surface in the drawing, and an interpixel light blocking film <NUM> and an on-chip lens <NUM> are stacked on the upper side of the substrate <NUM>, which is the light incident surface side.

Note that, in <FIG>, each shaded trapezoidal shape indicates a region in which the light intensity is high because infrared light is gathered by the on-chip lens <NUM>.

For example, in the surface-illuminated ToF sensor, there is a region R11 in which charge readout transfer transistors TG1 and TG2 exist on the light incident surface side of the substrate <NUM>. In the surface-illuminated ToF sensor, the intensity of infrared light is high in the region R11 near the light incident surface of the substrate <NUM>, and accordingly, the probability of photoelectric conversion of infrared light in the region R11 is high. That is, since the amount of infrared light entering the area near the inactive tap is large, the number of signal carriers that are not detected by the active tap increases, and charge separation efficiency decreases.

In the back-illuminated ToF sensor, on the other hand, there is a region R12 in which the active tap and the inactive tap are formed at positions far from the light incident surface of the substrate <NUM>, or at positions near the surface on the opposite side from the light incident surface side. The substrate <NUM> corresponds to the semiconductor substrate <NUM> shown in <FIG>.

The region R12 is located at a portion of the surface on the opposite side from the light incident surface side of the substrate <NUM>, and the region R12 is also located at a position far from the light incident surface. Accordingly, in the vicinity of the region R12, the intensity of incident infrared light is relatively low.

Signal carriers obtained through photoelectric conversion in a region in which the intensity of infrared light is high, such as a region near the center of the substrate <NUM> or near the light incident surface, are guided to the active tap by the electric field gradient formed by the active tap and the inactive tap, and are detected in the floating diffusion region FD of the active tap.

In the vicinity of the region R12 including the inactive tap, on the other hand, the intensity of incident infrared light is relatively low, and accordingly, the probability of photoelectric conversion of infrared light in the region R12 is low. That is, the amount of infrared light entering an area in the vicinity of the inactive tap is small. Accordingly, the number of signal carriers (electrons) that are generated through photoelectric conversion in the vicinity of the inactive tap and move to the floating diffusion region FD of the inactive tap becomes smaller, and thus, the charge separation efficiency can be improved. As a result, the ranging characteristics can be improved.

Further, in the back-illuminated light receiving element <NUM>, the thickness of the semiconductor substrate <NUM> can be reduced, and thus, it is possible to increase the efficiency in extracting electrons (charges) that are signal carriers.

For example, in a surface-illuminated ToF sensor, it is difficult to secure a sufficient aperture ratio. Therefore, to secure a higher quantum efficiency and prevent a decrease in quantum efficiency × aperture ratio, there is a need to increase the thickness of a substrate <NUM> to a certain value, as indicated by an arrow W31 in <FIG>.

As a result, the potential gradient becomes lower in the region near the surface on the opposite side from the light incident surface in the substrate <NUM>, or in a region R21, for example, and the electric field in a direction perpendicular to the substrate <NUM> substantially becomes weaker. In this case, the moving velocity of the signal carriers becomes lower, and therefore, the time elapsing from the photoelectric conversion to the transfer of the signal carriers to the floating diffusion region FD of the active tap becomes longer. Note that, in <FIG>, the arrows in the substrate <NUM> indicate the electric field in the direction perpendicular to the substrate <NUM> in the substrate <NUM>.

Further, when the substrate <NUM> is thick, the moving distance of the signal carriers from a position far from the active tap in the substrate <NUM> to the floating diffusion region FD of the active tap is long. Accordingly, at the position far from the active tap, the time elapsing from the photoelectric conversion to the transfer of the signal carriers to the floating diffusion region FD of the active tap becomes even longer. Therefore, after switching of the transfer transistors TG is completed, some signal carriers might reach the active tap, and turn into an erroneous signal.

<FIG> shows the relationship between the position in the thickness direction of the substrate <NUM> and the moving velocity of the signal carriers. The region R21 corresponds to a diffusion current region.

In a case where the substrate <NUM> is thick as described above, when the drive frequency is high, or when switching between the active tap and the inactive tap is performed at high speed, for example, electrons generated at a position far from the active tap, such as the region R21, are not completely drawn into the floating diffusion region FD of the active tap. In other words, in a case where the time during which the tap is active is short, some electrons (charges) generated in the region R21 or the like are not detected in the floating diffusion region FD of the active tap, and the electron extraction efficiency becomes lower.

In the back-illuminated ToF sensor, on the other hand, a sufficient aperture ratio can be secured. Thus, even when a substrate <NUM> is made thinner as indicated by an arrow W32 in <FIG>, for example,.

sufficient quantum efficiency × aperture ratio can be secured. Here, the substrate <NUM> corresponds to the semiconductor substrate <NUM> in <FIG>, and the arrows in the substrate <NUM> indicate the electric field in a direction perpendicular to the substrate <NUM>.

<FIG> shows the relationship between the position in the thickness direction of the substrate <NUM> and the moving velocity of the signal carriers.

When the thickness of the substrate <NUM> is reduced in this manner, the electric field in a direction perpendicular to the substrate <NUM> becomes substantially stronger, and only the electrons (charges) in a drift current region in which the moving velocity of the signal carriers is high are used while the electrons in the diffusion current region in which the moving velocity of the signal carriers is low are not used. As only the electrons (charges) in the drift current region are used, the time elapsing from the photoelectric conversion to detection of the signal carriers in the floating diffusion region FD of the active tap becomes shorter. Further, as the thickness of the substrate <NUM> becomes smaller, the moving distance of the signal carriers to the floating diffusion region FD of the active tap also becomes shorter.

In view of the above facts, in the back-illuminated ToF sensor, even when the drive frequency is high, the signal carriers (electrons) generated in the respective regions in the substrate <NUM> can be sufficiently drawn into the floating diffusion region FD of the active tap, and thus, the electron extraction efficiency can be increased. Further, as the thickness of the substrate <NUM> is reduced, sufficient electron extraction efficiency can be secured even at a high drive frequency, and resistance to high-speed drive can be increased.

Particularly, in the back-illuminated ToF sensor, a sufficient aperture ratio can be obtained. Thus, the pixels can be miniaturized accordingly, and the miniaturization resistance of the pixels can be increased.

Furthermore, as the light receiving element <NUM> is of a back-illuminated type, freedom is allowed in the back end of line (BEOL) design, and thus, it is possible to increase the degree of freedom in setting a saturation signal amount (Qs).

<FIG> is a cross-sectional view showing a second example configuration of the pixels <NUM>.

In <FIG>, the components equivalent to those of the first example configuration shown in <FIG> are denoted by the same reference numerals as those used in <FIG>, and explanation of the components will not be unnecessarily repeated.

The second example configuration in <FIG> is the same as the first example configuration in <FIG>, except that the interpixel separation portions <NUM> that are deep trench isolation (DTI) formed by digging from the back surface side (the side of the on-chip lenses <NUM>) of the semiconductor substrate <NUM> are replaced with interpixel separation portions <NUM> penetrating the semiconductor substrate <NUM>.

The interpixel separation portions <NUM> are formed in the following manner: trenches are formed from the back surface side (the side of the on-chip lenses <NUM>) or from the front surface side of the semiconductor substrate <NUM> until reaching the substrate surface on the opposite side, and the trenches are filled with the silicon oxide film <NUM>, which is the material of the uppermost layer of the antireflective film <NUM>. The material to be buried as the interpixel separation portions <NUM> in the trenches may be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN), for example, other than an insulating film such as the silicon oxide film <NUM>.

As such interpixel separation portions <NUM> are formed, it is possible to completely separate adjacent pixels electrically from each other. As a result, the interpixel separation portions <NUM> prevent incident light from reaching the neighboring pixels <NUM>, and confine the incident light in the respective pixels. The interpixel separation portions <NUM> also prevent leakage of incident light from the adjacent pixels <NUM>.

As the second example configuration is also a pixel structure of a back-illuminated type, a sufficient aperture ratio can be secured compared with that in a case with a surface-illuminated structure. Thus, quantum efficiency (QE) × aperture ratio (FF) can be maximized. Further, of the plurality of metal films M in the multilayer wiring layer <NUM>, the first metal film M1 closest to the semiconductor substrate <NUM> has the light blocking members (the reflective members) <NUM> in regions located below the formation regions of the photodiodes PD, so that infrared light that has not been photoelectrically converted in the semiconductor substrate <NUM> and has passed through the semiconductor substrate <NUM> is reflected by the light blocking members <NUM> and is made to reenter the semiconductor substrate <NUM>. With this arrangement, the amount of infrared light to be photoelectrically converted in the semiconductor substrate <NUM> can be further increased, and the quantum efficiency (QE), which is the sensitivity of the pixels <NUM> to infrared light, can be improved. Further, the infrared light that has not been photoelectrically converted in the semiconductor substrate <NUM> and has passed through the semiconductor substrate <NUM> is prevented from being scattered by the metal films M and entering the neighboring pixels. Thus, it is possible to prevent erroneous light detection at the neighboring pixels.

<FIG> is a cross-sectional view showing a third example configuration of the pixels <NUM>.

In the third example configuration in <FIG>, PD upper regions <NUM> located above the formation regions of the photodiodes PD in (the P-type semiconductor region <NUM> of) the semiconductor substrate <NUM> each have a moth-eye structure in which minute concavities and convexities are formed. Further, in conformity with the moth-eye structures in the PD upper regions <NUM> in the semiconductor substrate <NUM>, an antireflective film <NUM> formed on the upper surfaces thereof also has a moth-eye structure. The antireflective film <NUM> is formed with a stack of a hafnium oxide film <NUM>, an aluminum oxide film <NUM>, and a silicon oxide film <NUM>, as in the first example configuration.

As the PD upper regions <NUM> of the semiconductor substrate <NUM> are moth-eye structures as described above, it is possible to alleviate the abrupt change in the refractive index at the substrate interface, and reduce the influence of reflected light.

Note that, in <FIG>, the interpixel separation portions <NUM> formed with DTI formed by digging from the back surface side (the side of the on-chip lenses <NUM>) of the semiconductor substrate <NUM> are formed to reach slightly deeper positions than the interpixel separation portions <NUM> of the first example configuration in <FIG>. The depth in the substrate thickness direction in which the interpixel separation portions <NUM> are formed may be set at any depth as above.

In the other aspects, the third example configuration is similar to the first example configuration.

<FIG> is a cross-sectional view showing a fourth example configuration of the pixels <NUM>.

In <FIG>, the components equivalent to those of the first through third example configurations described above are denoted by the same reference numerals as those used above, and explanation of the components will not be unnecessarily repeated.

The fourth example configuration in <FIG> is the same as the third example configuration shown in <FIG> in that the PD upper regions <NUM> each include a substrate interface having a moth-eye structure and the antireflective film <NUM>.

The fourth example configuration in <FIG> is also the same as the second example configuration shown in <FIG> in including the interpixel separation portions <NUM> penetrating the entire semiconductor substrate <NUM>.

In other words, the fourth example configuration in <FIG> includes both the interpixel separation portions <NUM> of the second example configuration, and the semiconductor substrate <NUM> and the antireflective film <NUM> having moth-eye structures of the third example configuration. In the other aspects, the fourth example configuration is similar to the second example configuration or the third example configuration.

As the third and fourth example configurations are also pixel structures of a back-illuminated type, a sufficient aperture ratio can be secured compared with that in a case with a surface-illuminated structure. Thus, quantum efficiency (QE) × aperture ratio (FF) can be maximized.

Further, the light blocking member (the reflective member) <NUM> is provided in a predetermined metal film M in the multilayer wiring layer <NUM>, the sensitivity of the pixels <NUM> to infrared light can be increased, and erroneous light detection at neighboring pixels can be prevented.

<FIG> is a cross-sectional view showing a fifth example configuration of the pixels <NUM>.

In <FIG>, the components equivalent to those of the first through fourth example configurations described above are denoted by the same reference numerals as those used above, and explanation of the components will not be unnecessarily repeated.

In the first through fourth example configurations described above, the interpixel separation portions <NUM> or the interpixel separation portions <NUM> provided in the pixel boundary portions <NUM> may be omitted. For example, if the interpixel separation portions <NUM> of the third example configuration described above or the interpixel separation portions <NUM> of the fourth example configuration described above are omitted, the structure shown in <FIG> is obtained.

The fifth example configuration in <FIG> has the configuration of the third example configuration minus the interpixel separation portions <NUM> or the configuration of the fourth example configuration minus the interpixel separation portions <NUM>. In the fifth example configuration, the antireflective film <NUM> is formed as a flat film in each of the pixel boundary portions <NUM>. In the other aspects, the fifth example configuration is similar to the third example configuration or the fourth example configuration.

<FIG> is a perspective view of a moth-eye structure formed in a PD upper region <NUM> of the semiconductor substrate <NUM>.

In the moth-eye structure in the semiconductor substrate <NUM>, a plurality of quadrangular pyramidal regions of substantially the same shape having its apex on the side of the semiconductor substrate <NUM> and of substantially the same size is regularly arranged (in a grid-like pattern), as shown in <FIG>, for example.

Note that, in <FIG>, the upper side of the semiconductor substrate <NUM> is the light incident side, which is the side of the on-chip lens <NUM>.

The moth-eye structure is formed on the light incident surface side of the semiconductor substrate <NUM>, and has an inverse pyramid structure in which a plurality of quadrangular pyramidal regions having their apexes on the side of the photodiode PD is regularly arranged. The bottom surface of each quadrangular pyramid has a square shape, and the semiconductor substrate <NUM> is dug so that each quadrangular pyramidal region is convex on the side of the photodiode PD. In <FIG>, a portion indicated by an arrow W51 is the concave portion of the apex portion of each quadrangular pyramidal region on the side of the photodiode PD, for example. The concave portion indicated by the arrow W51 has a curvature, and has a roundish shape, for example.

Note that not only the respective concave portions of the respective quadrangular pyramids in the moth-eye structure but also the oblique portions of the respective quadrangular pyramidal regions, which are shaded portions in <FIG>, may also have a certain curvature. As the oblique portions also have a curvature, it is possible to further improve the effect to reduce formation unevenness and peeling of the planarization film <NUM>.

<FIG> are perspective views showing another example of a moth-eye structure in the semiconductor substrate <NUM>.

In the example described above with reference to <FIG>, the moth-eye structure is an inverse pyramid structure formed with quadrangular pyramidal regions having apexes on the side of the photodiode PD. However, the moth-eye structure may be a forward pyramid structure as shown in <FIG>, for example.

Specifically, as shown in <FIG>, the moth-eye structure is formed on the surface of the semiconductor substrate <NUM> on the light incident side. Further, the moth-eye structure is a forward pyramid structure in which a plurality of quadrangular pyramidal regions having apexes on the side of the on-chip lens <NUM>, which is the light incident side, is regularly arranged in a grid-like pattern.

In <FIG>, the plurality of quadrangular pyramidal regions also has substantially the same shape and substantially the same size, and the bottom surface of each quadrangular pyramid has a square shape. Furthermore, the semiconductor substrate <NUM> is dug to form the quadrangular pyramidal regions, so that the respective quadrangular pyramidal regions are convex on the opposite side from the side of the photodiode PD.

For example, a portion indicated by an arrow W71 is the concave portion of the base portion of each quadrangular pyramidal region on the side of the photodiode PD. The concave portion indicated by the arrow W71 has a portion that is convex on the side of the photodiode PD when viewed in a cross-section substantially parallel to the direction from the light incident side of the semiconductor substrate <NUM> toward the photodiode PD. The convex portion has a curvature, and has a roundish shape, as in the example shown in <FIG>.

In <FIG>, the shaded portions formed with the bases of the respective quadrangular pyramids having apexes on the upper side may be formed to have a curvature. In this case, it is possible to reduce formation unevenness and peeling of the planarization film <NUM> formed on the semiconductor substrate <NUM>, as in the example shown in <FIG>.

<FIG> are perspective views showing other examples of a moth-eye structure in the semiconductor substrate <NUM>.

In the moth-eye structure, the bottom surfaces of the minute concavities and convexities may have a rectangular shape, as shown in <FIG>, for example.

The moth-eye structure shown in <FIG> is formed on the light incident surface side of the semiconductor substrate <NUM>, and has long linear concave portions in the longitudinal direction (vertical direction) or the lateral direction (horizontal direction) of the pixel <NUM>.

More specifically, the moth-eye structure shown in <FIG> has a sawtooth shape when viewed in a cross-section in the same direction as the cross-sectional views in <FIG>, and has a shape in which a plurality of triangular prisms of substantially the same shape and substantially the same size is arranged in one direction while one vertex of each triangle and one rectangular surface of each triangular prism face the photodiode PD.

In <FIG>, a portion indicated by an arrow W91 is a concave portion, for example, and a portion indicated by an arrow W92 is a convex portion, for example. The shaded portion of each concave portion has a roundish shape with a predetermined curvature. Accordingly, it is also possible to reduce formation unevenness and peeling of the planarization film <NUM> formed on the semiconductor substrate <NUM> in this example.

Further, other than a structure in which quadrangular pyramidal shapes of substantially the same size are regularly arranged, the moth-eye structure in the semiconductor substrate <NUM> may be a structure in which quadrangular pyramidal shapes of different sizes from one another may be irregularly arranged as shown in <FIG>.

The example shown in <FIG> is a forward pyramid structure in which quadrangular pyramidal regions having apexes on the side of the on-chip lens <NUM> are irregularly arranged. Furthermore, the sizes of the plurality of quadrangular pyramidal regions are not the same size. In other words, the sizes and the arrangement of the quadrangular pyramids are random.

For example, portions indicated by an arrow W93 and an arrow W94 are concave portions, and the concave portions have a curvature and have roundish shapes. With this arrangement, it is possible to reduce formation unevenness and peeling of the planarization film <NUM> formed on the semiconductor substrate <NUM>.

<FIG> shows a moth-eye structure having a forward pyramid structure in which a plurality of quadrangular pyramidal regions having apexes on the side of the on-chip lens <NUM> is randomly arranged. However, the inverse pyramid structure shown in <FIG> may of course be a structure in which the sizes and the arrangement of the plurality of quadrangular pyramidal regions are random.

The moth-eye structure of the semiconductor substrate <NUM> formed in the PD upper regions <NUM> can be formed to have the shape shown in any of <FIG>, for example. With this, it is possible to alleviate the sudden change in the refractive index at the substrate interface, and reduce the influence of reflected light.

Note that, in the third through fifth example configurations in which a moth-eye structure is adopted, in a case where the antireflection effect of the moth-eye structure is sufficient, the antireflective film <NUM> thereon may be omitted.

<FIG> is a cross-sectional view showing a sixth example configuration of the pixels <NUM>.

In <FIG>, the components equivalent to those of the first through fifth example configurations described above are denoted by the same reference numerals as those used above, and explanation of the components will not be unnecessarily repeated.

In the first through fifth example configurations described above, the light receiving element <NUM> is formed with a single semiconductor substrate, or only with the semiconductor substrate <NUM>. In the sixth example configuration in <FIG>, however, the light receiving element <NUM> is formed with two semiconductor substrates: the semiconductor substrate <NUM> and a semiconductor substrate <NUM>. In the description below, for easy understanding, the semiconductor substrate <NUM> and the semiconductor substrate <NUM> will be also referred to as the first substrate <NUM> and the second substrate <NUM>, respectively.

The sixth example configuration in <FIG> is similar to the first example configuration in <FIG> in that the interpixel light blocking films <NUM>, the planarization film <NUM>, and the on-chip lenses <NUM> are formed on the light incident surface side of the first substrate <NUM>. The sixth example configuration is also similar to the first example configuration in <FIG> in that the interpixel separation portions <NUM> are formed in the pixel boundary portions <NUM> on the back surface side of the first substrate <NUM>.

The sixth example configuration is also similar to the first example configuration in that the photodiodes PD as the photoelectric conversion portions are formed in the first substrate <NUM> for the respective pixels, and in that the two transfer transistors TRG1 and TRG2, and the floating diffusion regions FD1 and FD2 as the charge storage portions are formed on the front surface side of the first substrate <NUM>.

On the other hand, a different aspect from the first example configuration in <FIG> is that an insulating layer <NUM> of a wiring layer <NUM> on the front surface side of the first substrate <NUM> is bonded to an insulating layer <NUM> of the second substrate <NUM>.

The wiring layer <NUM> of the first substrate <NUM> includes at least one metal film M, and the light blocking members <NUM> are formed with the metal film M in regions located below the formation regions of the photodiodes PD.

Pixel transistors Tr1 and Tr2 are formed at the interface on the opposite side from the side of the insulating layer <NUM>, which is the bonding surface side of the second substrate <NUM>. The pixel transistors Tr1 and Tr2 are amplification transistors AMP and selection transistors SEL, for example.

In other words, in the first through fifth example configurations only including the single semiconductor substrate <NUM> (the first substrate <NUM>), all of the pixel transistors including the transfer transistors TRG, the switch transistors FDG, the amplification transistors AMP, and the selection transistors SEL are formed in the semiconductor substrate <NUM>. In the light receiving element <NUM> of the sixth example configuration including a stack structure of two semiconductor substrates, on the other hand, the pixel transistors other than the transfer transistors TRG, or the switch transistors FDG, the amplification transistors AMP, and the selection transistors SEL are formed in the second substrate <NUM>.

A multilayer wiring layer <NUM> including at least two metal films M is formed on the opposite side of the second substrate <NUM> from the side of the first substrate <NUM>. The multilayer wiring layer <NUM> includes a first metal film M11, a second metal film M12, and an interlayer insulating film <NUM>.

The transfer drive signal TRGlg for controlling the transfer transistors TRG1 is supplied from the first metal film M11 of the second substrate <NUM> to the gate electrodes of the transfer transistors TRG1 of the first substrate <NUM> by through silicon vias (TSVs) <NUM>-<NUM> penetrating the second substrate <NUM>. The transfer drive signal TRG2g for controlling the transfer transistors TRG2 is supplied from the first metal film M11 of the second substrate <NUM> to the gate electrodes of the transfer transistors TRG2 of the first substrate <NUM> by TSVs <NUM>-<NUM> penetrating the second substrate <NUM>.

Likewise, the charges accumulated in the floating diffusion regions FD1 are transferred from the side of the first substrate <NUM> to the first metal film M11 of the second substrate <NUM> by TSVs <NUM>-<NUM> penetrating the second substrate <NUM>. The charges accumulated in the floating diffusion regions FD2 are transferred from the side of the first substrate <NUM> to the first metal film M11 of the second substrate <NUM> by TSVs <NUM>-<NUM> penetrating the second substrate <NUM>.

The wiring capacitors <NUM> are formed in a region (not shown) of the first metal film M11 or the second metal film M12. The metal film M in which the wiring capacitors <NUM> are formed is designed to have a high wiring density for capacitor formation, and the metal film M connected to the gate electrodes of the transfer transistors TRG, the switch transistors FDG, or the like is designed to have a low wiring density to reduce induced current. The wiring layer (metal film M) to be connected to the gate electrodes may vary with each pixel transistor. As described above, the pixels <NUM> of the sixth example configuration can be formed by stacking two semiconductor substrates: the first substrate <NUM> and the second substrate <NUM>. The pixel transistors other than the transfer transistors TRG are formed in the second substrate <NUM>, which is different from the first substrate <NUM> including the photoelectric conversion portions. Further, the vertical drive unit <NUM> that controls driving of the pixels <NUM>, the pixel drive lines <NUM>, the vertical signal lines <NUM> that transmit detection signals, and the like are also formed in the second substrate <NUM>. Thus, the pixels can be miniaturized, and the degree of freedom in the back end of line (BEOL) design becomes higher.

As the sixth example configuration is also a pixel structure of a back-illuminated type, a sufficient aperture ratio can be secured compared with that in a case with a surface-illuminated structure. Thus, quantum efficiency (QE) × aperture ratio (FF) can be maximized. Further, the regions of the wiring layer <NUM> that is the closest to the first substrate <NUM> and overlaps the formation regions of the photodiodes PD include the light blocking members (the reflective members) <NUM>, so that infrared light that has not been photoelectrically converted in the semiconductor substrate <NUM> and has passed through the semiconductor substrate <NUM> is reflected by the light blocking members <NUM> and is made to reenter the semiconductor substrate <NUM>. With this arrangement, the amount of infrared light to be photoelectrically converted in the semiconductor substrate <NUM> can be further increased, and the quantum efficiency (QE), which is the sensitivity of the pixels <NUM> to infrared light, can be improved. Further, the infrared light that has not been photoelectrically converted in the semiconductor substrate <NUM> and has passed through the semiconductor substrate <NUM> can be prevented from entering the side of the second substrate <NUM>.

Referring now to <FIG>, a manufacturing method in the sixth example configuration is described.

First, as shown in <FIG>, after the photodiodes PD as the photoelectric conversion portions and the floating diffusion regions FD are formed pixel by pixel in predetermined regions in the first substrate <NUM>, the gate electrodes <NUM> of the transfer transistors TRG are formed.

Next, as shown in <FIG>, after an insulating film <NUM> is formed on the gate electrodes <NUM> of the transfer transistors TRG and the upper surface of the first substrate <NUM>, the light blocking members <NUM> corresponding to the regions of the photodiodes PD are formed as a pattern.

Next, as shown in <FIG>, an insulating film is further stacked on the light blocking members <NUM> and the insulating film <NUM>, to form the insulating layer <NUM>, and the wiring layer <NUM> that is the front surface side of the first substrate <NUM> is formed. Then, the insulating layer <NUM> on the back surface side of the second substrate <NUM> in which the pixel transistors Tr1 and Tr2 such as the amplification transistors AMP and the selection transistors SEL are formed in advance is bonded to the insulating layer <NUM> of the first substrate <NUM>.

Next, as shown in <FIG>, after an insulating layer <NUM> is formed on the upper surface of the second substrate <NUM>, trenches <NUM>-<NUM> and <NUM>-<NUM> for contact with the gate electrodes of the pixel transistors Tr1 and Tr2 are formed. Further, trenches <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> penetrating the second substrate <NUM> are formed at the portions necessary for electrically connecting the first substrate <NUM> and the second substrate <NUM>, such as the gate electrodes of the transfer transistors TRG1 and TRG2, and the floating diffusion regions FD1 and FD2.

Next, as shown in <FIG>, the trenches <NUM>-<NUM> and <NUM>-<NUM>, and the trenches <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are filled with a metal material such as tungsten (W). As a result, the TSVs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are formed.

Next, as shown in <FIG>, the first metal film M11, the second metal film M12, and an insulating layer are formed on the insulating layer <NUM>, and thus, the multilayer wiring layer <NUM> is formed.

After <FIG>, the antireflective film <NUM>, the on-chip lenses <NUM>, and the like are formed on the back surface side that is the light incident surface of the first substrate <NUM>. Thus, the light receiving element <NUM> in <FIG> is completed.

Note that the sixth example configuration shown in <FIG> is a configuration formed by modifying the first example configuration shown in <FIG> into a stack structure of two semiconductor substrates. However, it is of course possible to adopt a configuration formed by modifying any of the second through fifth example configurations into a stack structure of two semiconductor substrates.

Each pixel <NUM> in the first through sixth example configurations is a so-called two-tap pixel structure that has two transfer transistors TRG1 and TRG2 as the transfer gates for one photodiode PD, has two floating diffusion regions FD1 and FD2 as charge storage portions, and distributes charges generated in the photodiode PD to the two floating diffusion regions FD1 and FD2.

On the other hand, a pixel <NUM> may be a so-called four-tap pixel structure that has four transfer transistors TRG1 through TRG4 and floating diffusion regions FD1 through FD4 for one photodiode PD, and distributes charges generated in the photodiode PD to the four floating diffusion regions FD1 through FD4.

<FIG> is a plan view of a pixel <NUM> in a case of a four-tap pixel structure.

The pixel <NUM> includes four sets of a first transfer transistor TRGa, a second transfer transistor TRGb, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

Outside the photodiode PD, one set of a first transfer transistor TRGa, a second transfer transistor TRGb, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is linearly arranged along each one side of the four sides of the rectangular pixel <NUM>.

In <FIG>, each set of a first transfer transistor TRGa, a second transfer transistor TRGb, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL, which are arranged along one of the four sides of the rectangular pixel <NUM>, are denoted with one of the numbers <NUM> through <NUM>, and thus, is distinguished from the other sets.

As described above, a pixel <NUM> may have a structure that distributes charges generated in the photodiode PD to two taps, or a structure that distributes the charges to four taps. A pixel <NUM> does not necessarily have a two-tap structure, and may have a structure with three or more taps.

For example, in a case where a pixel <NUM> has a two-tap structure, driving is performed to distribute generated charges to the two floating diffusion regions FD by shifting the phase (the light reception timing) by <NUM> degrees between the first tap and the second tap. In a case where a pixel <NUM> has a four-tap structure, on the other hand, driving may be performed to distribute generated charges to four floating diffusion regions FD by shifting the phase (the light reception timing) by <NUM> degrees between each two taps among the first through fourth taps. The distance to the object can be then determined, on the basis of the distribution ratio of the charges accumulated in the four floating diffusion regions FD.

<FIG> is a block diagram showing an example configuration of a ranging module that outputs ranging information, using the light receiving element <NUM> described above.

A ranging module <NUM> includes a light emitting unit <NUM>, a light emission controller <NUM>, and a light receiving unit <NUM>.

The light emitting unit <NUM> has a light source that emits light of a predetermined wavelength, and emits irradiation light whose brightness periodically changes, to an object. For example, the light emitting unit <NUM> has a light emitting diode that emits infrared light having a wavelength of <NUM> to <NUM> as the light source, and emits irradiation light in synchronization with a square-wave light emission control signal CLKp supplied from the light emission controller <NUM>. Note that the light emission control signal CLKp is not necessarily of a square wave, but has to be a periodic signal. For example, the light emission control signal CLKp may be a sine wave.

The light emission controller <NUM> supplies the light emission control signal CLKp to the light emitting unit <NUM> and the light receiving unit <NUM>, and controls the timing to emit irradiation light. The frequency of the light emission control signal CLKp is <NUM> megahertz (MHz), for example. Note that the frequency of the light emission control signal CLKp is not necessarily <NUM> megahertz (MHz), and may be <NUM> megahertz (MHz) or the like.

The light receiving unit <NUM> receives light reflected from the object, calculates distance information for each pixel in accordance with the light reception result, and generates and outputs a depth image in which the depth value corresponding to the distance to the object (subject) is stored as a pixel value.

A light receiving element <NUM> having the pixel structure of any of the above described first through sixth example configuration is used as the light receiving unit <NUM>. For example, the light receiving element <NUM> as the light receiving unit <NUM> calculates distance information for each pixel, from the signal intensity corresponding to the charges that have been distributed to the floating diffusion region FD1 or FD2 of each pixel <NUM> in the pixel array unit <NUM> on the basis of the light emission control signal CLKp. Note that the number of taps of each pixel <NUM> may be four or the like as described above.

As described above, a light receiving element <NUM> having the pixel structure of any of the first through sixth example configurations described above can be incorporated as the light receiving unit <NUM> into the ranging module <NUM> that calculates and outputs information indicating the distance to the object by an indirect ToF method. Thus, the ranging characteristics of the ranging module <NUM> can be improved.

Note that a light receiving element <NUM> can be applied to a ranging module as described above, and can also be applied to various electronic apparatuses such as an imaging device like a digital still camera or a digital video camera having a ranging function, and a smartphone having a ranging function, for example.

<FIG> is a block diagram showing an example configuration of a smartphone as an electronic apparatus to which the present technology is applied.

As shown in <FIG>, a smartphone <NUM> includes a ranging module <NUM>, an imaging device <NUM>, a display <NUM>, a speaker <NUM>, a microphone <NUM>, a communication module <NUM>, a sensor unit <NUM>, a touch panel <NUM>, and a control unit <NUM>, which are connected via a bus <NUM>. Further, in the control unit <NUM>, a CPU executes a program, to achieve functions as an application processing unit <NUM> and an operation system processing unit <NUM>.

The ranging module <NUM> IN <FIG> is applied to the ranging module <NUM>. For example, the ranging module <NUM> is disposed in the front surface of the smartphone <NUM>, and performs ranging for the user of the smartphone <NUM>, to output the depth value of the surface shape of the user's face, hand, finger, or the like as a measurement result.

The imaging device <NUM> is disposed in the front surface of the smartphone <NUM>, and acquires an image showing the user by performing imaging of the user of the smartphone <NUM> as the subject. Note that, although not illustrated, the imaging device <NUM> may also be disposed in the back surface of the smartphone <NUM>.

The display <NUM> displays an operation screen for performing processing with the application processing unit <NUM> and the operation system processing unit <NUM>, an image captured by the imaging device <NUM>, or the like. The speaker <NUM> and the microphone <NUM> output the voice from the other end, and collect the voice of the user, when a voice call is made with the smartphone <NUM>, for example.

The communication module <NUM> performs network communication via a communication network such as the Internet, a public telephone network, a wide area communication network for wireless mobile objects, such as a so-called <NUM> network or a <NUM> network, a wide area network (WAN), or a local area network (LAN), short-range wireless communication such as Bluetooth (registered trademark) or near field communication (NFC), or the like. The sensor unit <NUM> senses velocity, acceleration, proximity, and the like, and the touch panel <NUM> acquires a touch operation performed by the user on an operation screen displayed on the display <NUM>.

The application processing unit <NUM> performs processing for providing various services through the smartphone <NUM>. For example, the application processing unit <NUM> can perform a process of creating a face by computer graphics that virtually reproduces the user's expression and displaying the face on the display <NUM>, on the basis of the depth value supplied from the ranging module <NUM>. The application processing unit <NUM> can also perform a process of creating three-dimensional shape data of a three-dimensional object, for example, on the basis of the depth value supplied from the ranging module <NUM>.

The operation system processing unit <NUM> performs a process to achieve the basic functions and operations of the smartphone <NUM>. For example, the operation system processing unit <NUM> can perform a process of authenticating the user's face on the basis of the depth value supplied from the ranging module <NUM>, and releasing the lock on the smartphone <NUM>. Further, the operation system processing unit <NUM> performs a process of recognizing a gesture of the user on the basis of the depth value supplied from the ranging module <NUM>, and then performs a process of inputting various operations in accordance with the gesture, for example.

In the smartphone <NUM> configured as above, the ranging module <NUM> described above is used as the ranging module <NUM>, so that the distance to a predetermined object can be measured and displayed, or three-dimensional shape data of the predetermined object can be created and displayed, for example.

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be embodied as an apparatus mounted on any type of moving object, such as an automobile, an electrical vehicle, a hybrid electrical vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a vessel, or a robot.

<FIG> is a block diagram schematically showing an example configuration of a vehicle control system that is an example of a moving object control system to which the technology according to the present disclosure can be applied.

A vehicle control system <NUM> includes a plurality of electronic control units connected via a communication network <NUM>. In the example shown in <FIG>, the vehicle control system <NUM> includes a drive system control unit <NUM>, a body system control unit <NUM>, an external information detection unit <NUM>, an in-vehicle information detection unit <NUM>, and an overall control unit <NUM>. A microcomputer <NUM>, a sound/image output unit <NUM>, and an in-vehicle network interface (I/F) <NUM> are also shown as the functional components of the overall control unit <NUM>.

The drive system control unit <NUM> controls operations of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit <NUM> functions as control devices such as a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

The body system control unit <NUM> controls operations of the various devices mounted on the vehicle body according to various programs. For example, the body system control unit <NUM> functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal lamp, a fog lamp, or the like. In this case, the body system control unit <NUM> can receive radio waves transmitted from a portable device that substitutes for a key, or signals from various switches. The body system control unit <NUM> receives inputs of these radio waves or signals, and controls the door lock device, the power window device, the lamps, and the like of the vehicle.

The external information detection unit <NUM> detects information outside the vehicle equipped with the vehicle control system <NUM>. For example, an imaging unit <NUM> is connected to the external information detection unit <NUM>. The external information detection unit <NUM> causes the imaging unit <NUM> to capture an image of the outside of the vehicle, and receives the captured image. In accordance with the received image, the external information detection unit <NUM> may perform an object detection process for detecting a person, a vehicle, an obstacle, a sign, characters on the road surface, or the like, or perform a distance detection process.

The imaging unit <NUM> is an optical sensor that receives light, and outputs an electrical signal corresponding to the amount of received light. The imaging unit <NUM> can output an electrical signal as an image, or output an electrical signal as distance measurement information. Further, the light to be received by the imaging unit <NUM> may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit <NUM> detects information about the inside of the vehicle. For example, a driver state detector <NUM> that detects the state of the driver is connected to the in-vehicle information detection unit <NUM>. The driver state detector <NUM> includes a camera that captures an image of the driver, for example, and, in accordance with detected information input from the driver state detector <NUM>, the in-vehicle information detection unit <NUM> may calculate the degree of fatigue or the degree of concentration of the driver, or determine whether the driver is dozing off.

In accordance with the external/internal information acquired by the external information detection unit <NUM> or the in-vehicle information detection unit <NUM>, the microcomputer <NUM> can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control to achieve the functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance or impact mitigation, follow-up running based on the distance between vehicles, vehicle speed maintenance running, vehicle collision warning, vehicle lane deviation warning, or the like.

The microcomputer <NUM> can also perform cooperative control to conduct automatic driving or the like for autonomously running not depending on the operation of the driver, by controlling the driving force generation device, the steering mechanism, the braking device, or the like in accordance with information about the surroundings of the vehicle, the information having being acquired by the external information detection unit <NUM> or the in-vehicle information detection unit <NUM>.

The microcomputer <NUM> can also output a control command to the body system control unit <NUM>, in accordance with the external information acquired by the external information detection unit <NUM>. For example, the microcomputer <NUM> controls the headlamp in accordance with the position of the leading vehicle or the oncoming vehicle detected by the external information detection unit <NUM>, and performs cooperative control to achieve an anti-glare effect by switching from a high beam to a low beam, or the like.

The sound/image output unit <NUM> transmits an audio output signal and/or an image output signal to an output device that is capable of visually or audibly notifying the passenger(s) of the vehicle or the outside of the vehicle of information. In the example shown in <FIG>, an audio speaker <NUM>, a display unit <NUM>, and an instrument panel <NUM> are shown as output devices. The display unit <NUM> may include an on-board display and/or a head-up display, for example.

<FIG> is a diagram showing an example of installation positions of imaging units <NUM>.

In <FIG>, a vehicle <NUM> includes imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> as the imaging units <NUM>.

Imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are provided at the following positions: the front end edge of a vehicle <NUM>, a side mirror, the rear bumper, a rear door, and an upper portion of the front windshield inside the vehicle, for example. The imaging unit <NUM> provided on the front end edge and the imaging unit <NUM> provided on the upper portion of the front windshield inside the vehicle mainly capture images ahead of the vehicle <NUM>. The imaging units <NUM> and <NUM> provided on the side mirrors mainly capture images on the sides of the vehicle <NUM>. The imaging unit <NUM> provided on the rear bumper or a rear door mainly captures images behind the vehicle <NUM>. The front images acquired by the imaging units <NUM> and <NUM> are mainly used for detection of a vehicle running in front of the vehicle <NUM>, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that <FIG> shows an example of the imaging ranges of the imaging units <NUM> through <NUM>. An imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided on the front end edge, imaging ranges <NUM> and <NUM> indicate the imaging ranges of the imaging units <NUM> and <NUM> provided on the respective side mirrors, and an imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided on the rear bumper or a rear door. For example, image data captured by the imaging units <NUM> through <NUM> are superimposed on one another, so that an overhead image of the vehicle <NUM> viewed from above is obtained.

At least one of the imaging units <NUM> through <NUM> may have a function of acquiring distance information. For example, at least one of the imaging units <NUM> through <NUM> may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for phase difference detection.

For example, in accordance with distance information obtained from the imaging units <NUM> through <NUM>, the microcomputer <NUM> calculates the distances to the respective three-dimensional objects within the imaging ranges <NUM> through <NUM>, and temporal changes in the distances (the speeds relative to the vehicle <NUM>). In this manner, the three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle <NUM> and is traveling at a predetermined speed (<NUM>/h or higher, for example) in substantially the same direction as the vehicle <NUM> can be extracted as the vehicle running in front of the vehicle <NUM>. Further, the microcomputer <NUM> can set beforehand an inter-vehicle distance to be maintained in front of the vehicle running in front of the vehicle <NUM>, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this manner, it is possible to perform cooperative control to conduct automatic driving or the like to autonomously travel not depending on the operation of the driver. For example, in accordance with the distance information obtained from the imaging units <NUM> through <NUM>, the microcomputer <NUM> can extract three-dimensional object data concerning three-dimensional objects under the categories of two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, utility poles, and the like, and use the three-dimensional object data in automatically avoiding obstacles. For example, the microcomputer <NUM> classifies the obstacles in the vicinity of the vehicle <NUM> into obstacles visible to the driver of the vehicle <NUM> and obstacles difficult to visually recognize. The microcomputer <NUM> then determines collision risks indicating the risks of collision with the respective obstacles. If a collision risk is equal to or higher than a set value, and there is a possibility of collision, the microcomputer <NUM> outputs a warning to the driver via the audio speaker <NUM> and the display unit <NUM>, or can perform driving support for avoiding collision by performing forced deceleration or avoiding steering via the drive system control unit <NUM>.

At least one of the imaging units <NUM> through <NUM> may be an infrared camera that detects infrared light. For example, the microcomputer <NUM> can recognize a pedestrian by determining whether or not a pedestrian exists in images captured by the imaging units <NUM> through <NUM>. Such pedestrian recognition is carried out through a process of extracting feature points from the images captured by the imaging units <NUM> through <NUM> serving as infrared cameras, and a process of performing a pattern matching on the series of feature points indicating the outlines of objects and determining whether or not there is a pedestrian, for example. If the microcomputer <NUM> determines that a pedestrian exists in the images captured by the imaging units <NUM> through <NUM>, and recognizes a pedestrian, the sound/image output unit <NUM> controls the display unit <NUM> to display a rectangular contour line for emphasizing the recognized pedestrian in a superimposed manner. The sound/image output unit <NUM> may also control the display unit <NUM> to display an icon or the like indicating the pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the external information detection unit <NUM> and the imaging units <NUM> in the above described configuration. Specifically, the light receiving element <NUM> or the ranging module <NUM> can be applied to the distance detection processing block of the external information detection unit <NUM> or the imaging unit <NUM>. As the technology according to the present disclosure is applied to the external information detection unit <NUM> or the imaging unit <NUM>, the distance to an object such as a person, a car, an obstacle, a signpost, or characters on a road surface can be measured with high accuracy. With the obtained distance information, it is possible to alleviate the driver's fatigue, and enhance the safety of the driver and the vehicle.

Embodiments of the present technology are not limited to the above described embodiments, and various modifications can be made to them without departing from the scope of the present technology.

Further, in the light receiving element <NUM> described above, an example in which electrons are used as signal carriers has been described. However, holes generated through photoelectric conversion may also be used as signal carriers.

Claim 1:
A light receiving element (<NUM>), comprising:
a plurality of pixels (<NUM>);
a semiconductor layer (<NUM>) configured to photoelectrically convert infrared light and disposed between on-chip lenses (<NUM>) for respective pixels (<NUM>) and a multi wiring layer (<NUM>) in a cross-sectional view; wherein each pixel includes:
an on-chip lens (<NUM>);
a first deep trench isolation portion (<NUM>) disposed in the semiconductor layer (<NUM>);
a second deep trench isolation portion (<NUM>) disposed adjacent to the first deep trench isolation portion (<NUM>) in the semiconductor layer (<NUM>) in the cross-sectional view;
a photodiode (PD) disposed between the first deep trench isolation portion (<NUM>) and the second deep trench isolation portion (<NUM>) in the semiconductor layer (<NUM>) in the cross-sectional view;
a first transfer transistor (TRG1) configured to transfer electric charge generated in the photodiode (PD) to a first floating diffusion region (FD1);
a second transfer transistor (TRG2) configured to transfer electric charge generated in the photodiode (PD) to a second floating diffusion region (FD2); and
a charge ejection transistor (OFG) configured to eject charges accumulated in the photodiode (PD), wherein one of a source and a drain of the charge ejection transistor (OFG) is coupled to the photodiode (PD), and wherein another one of the source and the drain of the charge ejection transistor (OFG) is coupled to a wiring configured to receive a voltage source potential;
wherein the first deep trench isolation portion (<NUM>) and the second deep trench isolation portion (<NUM>) are formed in a depth direction from a back side of the semiconductor layer (<NUM>) facing the on-chip lens (<NUM>);
wherein the first transfer transistor (TRG1), the second transfer transistor (TRG2) and the charge ejection transistor (OFG) are formed on a front side of the semiconductor layer (<NUM>) opposite to the back side; and
wherein the first deep trench isolation portion (<NUM>) and the second deep trench isolation portion (<NUM>) are configured to separate adjacent pixels (<NUM>) from one another and to prevent incident light from reaching an adjacent pixel.