Patent Description:
Ultra-Thick Metal (UTM) conductors have reduced resistance as compared to conventional metal layer leads. It is thus conventional to form UTM inductors to provide a high quality factor for RF filters and related circuits. To further increase the quality factor, the UTM conductors are deposited on low-k dielectric materials. To even further increase performance, the UTM conductors are deposited over extreme low-k (ELK) dielectric materials, which have a dielectric constant (k) of approximately <NUM> or less. It is difficult to engineer the dielectric constant so low such that ELK dielectric materials tend to be porous such as porous SiOCH. Although low k and ELK dielectrics advantageously enhance the electrical performance of the corresponding UTM structures, their porosity leads to poor mechanical strength. The tensile strength, hardness, and cohesive strength of ELK dielectrics are much lower than the corresponding strengths for traditional dielectric materials such as silicon dioxide. Delamination of the robust UTM conductors from low k and ELK dielectrics is thus problematic. To strengthen the dielectric layer to inhibit delamination, it is conventional to use a dummy metal fill outside of the UTM footprint. No dummy metal fill is used underneath (within the footprint) of the UTM conductor to prevent reduction of the resulting quality factor due to electrical coupling of the metal fill to the UTM conductor. But delamination remains a problem due to the poor mechanical strength of ELK dielectrics.

Accordingly, there is a need in the art for improving the strength of low-k dielectric and ELK dielectric to prevent the delamination of UTM conductors.

<CIT> relates to a semiconductor device, including an interlayer insulating film of a porous low-k film which has a two-layer structure. <CIT> relates to a method of obtaining high conductivity in a high frequency region without delamination or void concentration.

<CIT> relates to a stress reduction apparatus comprising a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and in inverted cup shaped stress reduction layer formed over the metal structure wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

<CIT> relates to a device including a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about <NUM>.

<CIT> relates to forming Metal-Insulator-Metal capacitors over a top metal layer. A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.

An ultra-thick metal (UTM) inductor is provided on a dielectric layer that includes a plurality of metal layers configured with vias into a partial metal fill within a footprint of the UTM inductor. The partial metal fill includes a plurality of interrupted via stacks that couple through pads within the metal layers. The interrupted via stacks do not extend through all the metal layers to inhibit their electrical coupling with the UTM inductor so as to provide a suitably-high quality factor. The dielectric layer may be an extreme-low-k dielectric layer yet the UTM inductor is protected against delamination from the dielectric layer due to the strengthening of the dielectric layer through the partial metal fill.

Outside of the footprint of the UTM inductor on the dielectric layer, the metal layers may be configured with vias to form a plurality of uninterrupted via stacks. The uninterrupted via stacks extend through all the metal layers by coupling through a corresponding metal pad within each metal layer. The uninterrupted via stacks further strengthen the dielectric layer so as to inhibit delamination of the UTM inductor without significantly affecting its quality factor due to the displacement of the uninterrupted via stacks from the UTM inductor.

These and additional advantages may be better appreciated through the following detailed description.

Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows.

To provide increased resistance to delamination, a substrate is provided with a dielectric layers including a plurality of metal layers. Each metal layer is patterned with pads - that are interconnected by vias. Since the patterned metal layers and vias do not provide electrical coupling to any circuits, they may be designated as "dummy" metal fill. The dielectric layer lies between the substrate and a ultra-thick-metal (UTM) conductor having a footprint on the dielectric layers. Within the footprint, the metal vias are arranged to form interrupted vias chains that do not extend through all the metal layers. These interrupted vias chains hinder delamination of the UTM conductor from the dielectric layers without unduly lowering the quality factor for the UTM conductor. In contrast, the via chains extend through all the metal layers outside of the footprint to provide additional strength to the dielectric layers to further hinder delamination of the UTM conductor from the dielectric layers. Since the dielectric layers are homogeneous, the following discussion will refer to "a dielectric layer" for brevity when referring to the dielectric layers separating the metal layers.

Turning now to the drawings, a plan view of an UTM metal inductor <NUM> within an integrated circuit package <NUM> is shown in <FIG>. UTM metal inductor <NUM> occupies a footprint <NUM> on dielectric layer <NUM>. Dielectric layer <NUM> comprise a low-k or ultra-low-k dielectric material. Examples of suitable ultra-low-k dielectric materials include porous polymeric materials, fluorine-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, xerogels, aerogels, Teflon, and F-doped amorphous carbon. Outside of footprint <NUM>, the metal layers within dielectric layer <NUM> are arranged into uninterrupted via stacks <NUM> that extend through all the metal layers. Within footprint <NUM>, the metal layers (not illustrated in <FIG>) are arranged into staggered interrupted via stacks as will be discussed further herein. UTM metal inductor <NUM> forms a number of coils within footprint <NUM> that are driven through a port <NUM> and a port <NUM>. These ports couple to leads (not illustrated) within the metal layers in dielectric layer <NUM> so that an external circuit may drive UTM inductor <NUM> with an appropriate RF signal. To increase the quality factor for UTM inductor <NUM>, footprint <NUM> has a lateral extent that is defined by the lateral extension of port <NUM> and port <NUM> from the inductor coils. Outside of the ports, the border of the footprint <NUM> is thus spaced apart from the outermost coil of UTM inductor <NUM> by the lateral extension of port <NUM> and port <NUM> to further reduce the quality-factor-lowering effect of uninterrupted via stacks <NUM>.

The number of metal layers within dielectric layer <NUM> depends upon the particular process being implemented. As shown in the cross-sectional view of <FIG>, there are four metal layers in one embodiment, ranging from a lowermost metal layer M1 through an uppermost metal layer M4. Below metal layer M1 is a substrate <NUM>. Substrate <NUM> may comprise a dielectric such as silicon oxide or glass or may comprise a semiconductor such as silicon, silicon germanium, or other suitable materials. Each metal layer is patterned to form a plurality of pads <NUM>. As shown in plan view in <FIG>, pads <NUM> may be square or rectangular. In alternative embodiments, pads <NUM> may be non-rectangular or irregular in shape. Given such an arrangement of pads <NUM> in each metal layer, dielectric layer <NUM> is strengthened to inhibit delamination of UTM <NUM> from dielectric layer <NUM>. Referring again to <FIG>, vias <NUM> couple between pads <NUM> in adjacent metal layers to form interrupted via stacks <NUM> to further inhibit the delamination of UTM inductor <NUM>. Each via stack <NUM> does not extend beyond its corresponding pair of neighboring metal layers. By limiting the height of each via stack <NUM> to no more than two metal layers, the electrical coupling between interrupted via stacks <NUM> and UTM inductor <NUM> is limited to improve its quality factor.

To further reduce the electrical coupling, interrupted via stacks <NUM> are staggered from one pair of neighboring metal layers to the next pair of neighboring metal layers. This staggering depends upon the arrangement of metal pads <NUM> within each metal layer. For example, metal pads <NUM> may be arranged in rows and columns as shown in <FIG>. Within each row, alternating ones of metal pads <NUM> are denoted as "A" pads separated by "B" pads. This alternation of A and B pads is reversed from row to row. The A pads represent the metal pads <NUM> that couple to vias <NUM> to form via stacks <NUM> in a first neighboring pair of metal layers such as metal layers M4 and M3. The B pads represent the metal pads <NUM> that couple to vias <NUM> to form interrupted via stacks <NUM> in the subsequent neighboring pair of metal layers such as metal layers M3 and M2. This alternation or staggering of via stacks <NUM> from a first pair of neighboring metal layers to the subsequent pair of neighboring metal layers further reduces the electrical coupling between UTM inductor <NUM> and interrupted via stacks <NUM>. Depending upon this alternation, either the A pads or the B pads in metal layer M1 and M4 will not be included in a via stack <NUM>. For metal layers M2 and M3, the A pads will couple to interrupted via stacks <NUM> extending in a first direction (either extending above or below the corresponding metal layer) whereas the B pads will couple to interrupted via stacks <NUM> extending in the opposite direction (the reverse of the first direction).

Metal pads <NUM> need not be arranged into rows and columns within each metal layer as shown in <FIG>. For example, adjacent rows of metal pads <NUM> may be displaced laterally with respect to each other as shown in <FIG> for adjacent rows <NUM> and <NUM>. In this embodiment, the lateral displacement of row <NUM> is approximately one half of the separation between metal pads <NUM> in row <NUM>. A third row <NUM> is then displaced with regard to row <NUM> such that rows <NUM> and <NUM> are not displaced with respect to each other. In alternative embodiments, row <NUM> may be displaced with regard to rows <NUM> and <NUM>. It is believed that the lateral displacement of adjacent rows as shown in <FIG> helps to reduce the electrical coupling to UTM inductor <NUM> to the metal layers in the partial metal fill.

Referring again to <FIG>, each uninterrupted via stack <NUM> outside of footprint <NUM> includes vias <NUM> that couple a metal pad <NUM> from each metal layer M1 through M4 together. Each uninterrupted via stack <NUM> thus extends through all the metal layers to form a dummy metal fill. Although such an extension would undesirably produce too strong of an electrical coupling to UTM inductor <NUM> if present within footprint <NUM>, the presence of uninterrupted via stacks <NUM> has relatively little electrical coupling to UTM inductor <NUM> due to the displacement of uninterrupted via stacks <NUM> from UTM inductor <NUM> by being located outside of footprint <NUM>.

With regard to the interrupted via stacks <NUM> within footprint <NUM>, the "orphaned" metal pads <NUM> in metal layers M1 and M4 that are not included in an interrupted via stack <NUM> help guard against delamination of UTM inductor <NUM>. However, they still produce some electrical coupling that reduces the quality factor for UTM inductor <NUM>. To eliminate this coupling, the metal pads <NUM> in metal layers M1 and M4 that do not couple to any interrupted via stacks <NUM> may be absent as shown in <FIG> for an integrated circuit package <NUM>. Within metal layers M2 and M3, metal pads <NUM> are arranged such as discussed with regard to <FIG> and <FIG>. But in metal layers M1 and M4, only the A pads (or just the B pads) are present from such pad arrangements. The quality factor for UTM inductor <NUM> may thus be improved at the cost of slightly reduced delamination resistance.

A similar compromise between delamination resistance and quality factor involves lengthening the interrupted via stacks beyond just a pair of neighboring metal layers such as shown for interrupted via stacks <NUM> in a UTM circuit package <NUM> of <FIG>. Each interrupted via stack <NUM> extends across three neighboring metal layers using two vias <NUM> and three metal pads <NUM>. Such an extension gives greater delamination resistance as compared to interrupted via stacks <NUM> but introduces slightly more electrical coupling with UTM inductor <NUM>. Interrupted via stacks <NUM> are staggered such as discussed with regard to <FIG> and <FIG>. In an embodiment with only four metal layers, there are only two metal layer combinations for each interrupted via stack <NUM>: either they extend across metal layers M4, M3 and M2 or they extend across metal layers M3, M2, and M1. Given such an arrangement, either the A metal pads or B metal pads in metal layers M1 and M4 will be isolated from interrupted via stacks <NUM>. These isolated metal pads <NUM> are indicated with dotted lines in <FIG> since their presence is optional as discussed analogously with regard to <FIG>. The inclusion of isolated metal pads <NUM> provides greater delamination resistance at the cost of a reduced quality factor for UTM inductor <NUM>. Should a dielectric layer for a UTM inductor package include more than four metal layers, a mixture of interrupted vias stacks <NUM> and interrupted vias stacks <NUM> may be included. In one embodiment, interrupted via stacks <NUM> and <NUM> may be deemed to comprise examples of a partial metal fill means within a footprint of the UTM conductor on a dielectric layer for strengthening the dielectric layer against delamination of the UTM conductor from the dielectric layer.

A method of manufacturing a UTM inductor on a dielectric metal layer including a partial metal fill will now be discussed with regard to the flowchart of <FIG>. The method includes an act <NUM> of, within a footprint for a to-be-deposited ultra-thick-metal (UTM) conductor, patterning a plurality of metal layers within a dielectric layer to include a plurality of pads, wherein the plurality of metal layers includes at least four metal layers. Referring to <FIG>, the patterning of metal pads <NUM> within metal layers M1 through M4 is an example of act <NUM>. Each metal layer may be deposited and patterned using conventional deposition and lithography/etching techniques. After a given metal layer is patterned, a layer of dielectric material is deposited over it so that a subsequent metal layer may be deposited over the new layer of dielectric material. The dielectric layers may be deposited using CVD or spin-on techniques. The metal layer thickness may vary but will generally be a nanometer or less in thickness such as <NUM> A. The metal layers may comprise copper or another suitable metal such as aluminum.

The method also includes an act <NUM> of connecting individual ones of the pads with vias extending through no more than three of the metal layers. The deposition of the vias is performed for a given metal layer prior to the deposition of the subsequent metal layer using conventional lithography and etching techniques. The formation of interrupted via stacks <NUM> or <NUM> is an example of act <NUM>.

Finally, the method includes an act <NUM> of depositing the UTM conductor over the dielectric layer within the footprint. The deposition of UTM inductor <NUM> is an example of act <NUM> and will generally comprise copper. The deposition of the UTM conductor may be performed using conventional electrodeposition techniques. The thickness of the UTM conductor may vary but will generally be at least three times thicker than the underlying metal layers such as several nanometers.

Claim 1:
A circuit package, comprising:
a substrate (<NUM>);
a dielectric layer (<NUM>) on a surface of the substrate;
a plurality of metal layers (M1-M4) within the dielectric layer, wherein the plurality of metal layers equals at least four metal layers; and
an ultra-thick-metal, UTM, conductor (<NUM>) on a surface of the dielectric layer; wherein the plurality of metals layers are configured into a plurality of metal pads (<NUM>);
characterised in that
the dielectric layer within a footprint (<NUM>) of the UTM conductor is configured with a plurality of vias (<NUM>, <NUM>) connecting individual ones of the metal pads between neighboring pairs of the metal layers into a plurality of dummy metal fill interrupted via stacks (<NUM>, <NUM>) that do not extend across more than three of the metal layers.