Patent Description:
For instance, embodiments as described herein can be applied in producing Wafer Level Chip Scale Package, WLCSP (integrated circuit) semiconductor devices.

The designation Wafer Level Chip Scale Package, WLCSP applies to a technology where integrated circuits are packaged at the wafer level, rather than as individual units after dicing them from a wafer.

The final device resulting from WLCSP processing is a semiconductor chip or die with an array of bumps or solder balls attached at an input/output pitch that facilitates circuit board assembly processes. The resulting package is thus essentially of the same size of the chip or die.

WLCSP technology advantageously dispenses with bond wires or similar connections and, in addition to a reduced package size, may also provide a reduced inductance from a die to a substrate (a printed circuit board, PCB, for instance).

One WLCSP category called "fan-in" limits redirection of solder balls to pads only on top of chip then sizing at chip size but also have no overmold then exposing chip substrate sidewall.

A problem that may arise in applying WLCSP technology is related to package insertion in test socket cavity when aligning (centering) a device on contact pins such as so-called "pogo" pins. These are electrical connectors that are used in view of their resilience to mechanical shock and vibration.

This handling might advantageously take place in a centering phase where a module is placed in a "personalization" socket taking advantage of auto-centering chamfers.

It is noted that applying such an approach to WLCSP devices may not be particularly attractive, as this may result in undesired damage of corner, sidewall and active face of the die.

This militates against personalizing (customizing) fan-in WLCSP packages when using reel-to-reel handling machines using pick&place technology, for instance vs. wafer level personalization before dicing.

Document <CIT> discloses an accommodation portion for a semiconductor device to be mounted formed of an accommodation portion of a positioning member that is restricted in its position to a socket body and supported on the same, and an accommodation portion of a positioning member that is supported on the socket body relatively movably with respect to the socket body.

Document <CIT> discloses a method of positioning integrated circuits (ICs) and an IC handler wherein a positioning wall piece encloses a table, with two pairs of inner faces, each pair of which are facing each other, and lower portions of each pair formed into vertical faces and mutually separated with a distance corresponding to outermost edges of the IC, with upper portions of each pair formed into slope faces whose distance is gradually made longer in an upward direction. An elastic member elastically supports the positioning wall piece, which is capable of moving vertically. The vertical mechanism is located above the positioning mechanism and pushes the positioning wall piece downwardly so as to correspond the upper face of the table to the upper portions when the IC is mounted on the table, and allows movement of the positioning wall piece upwardly so as to correct a horizontal deviation of the IC by the slope faces and to position the same by the vertical faces after the IC is mounted on the table.

Solutions as described herein aim at addressing the issues discussed in the foregoing.

Such an object can be achieved via a method having the features set forth in the claims that follow.

One or more embodiments relate to a corresponding apparatus.

The claims are an integral part of the technical teaching provided in respect of the embodiments.

In solutions as described herein a tool such as a vacuum cup can be used to pick up a die and to co-operate with a "nest" to facilitate mechanical pre-alignment at a nest level without unduly constraining placement accuracy at a "socket" level.

In that way, the edges of an alignment device may come into contact with the back or bottom side of the die which is usually provided with a protective layer (coating), instead of coming into contact to the front or top (active) side, sidewall or corner which are fragile.

Solutions as described herein facilitate pick&place sampling and preproduction activities, making these activities faster by enhancing alignment accuracy in comparison with conventional solutions, where sampling and preproduction are at wafer level, thus being expensive and hardly compatible with desired time-to-market strategies.

The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description.

Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments within the scope of the appended claims.

For simplicity and ease of explanation, throughout this description, and unless the context indicates otherwise, like parts or elements may be indicated in the various figures with like reference signs, and a corresponding description will not be repeated for each and every figure.

<FIG> is exemplary of placing an (integrated circuit, IC) semiconductor device D in a "personalization" socket CS provided with auto-centering chamfers C.

This is essentially a mechanical centering method that can be implemented using a pick&place tool <NUM> (of a known type) that picks the device D (from above in the case illustrated) and places, namely inserts or advances, the device D in a personalization socket CS taking advantage of auto-centering chamfers C provided therein.

Such an approach may be considered for centering a WLCSP device on pogo-pins P, namely electrical connectors that are used in view of their resilience to mechanical shock and vibration.

It is noted that applying such an approach to a WLCSP device may result in undesired damage F at the edge of the front or top surface, the sidewall or the corners of the chip or die as schematically illustrated in <FIG>, where <FIG> is a view of the portion of <FIG> indicated by the arrow III.

In fact, the final device resulting from WLCSP processing is a semiconductor chip or die (as used herein, these two terms are considered as synonymous) with an array of bumps or solder balls S attached to a front or top surface D1 in order to facilitate circuit board assembly processes (coupling to pogo-pins P, for instance).

In an arrangement as exemplified in <FIG>, if applied to a WLCSP device, the edges of the alignment chamfers C will come into contact with the front or top (active) side, which may be fragile (bare silicon, for instance), thus possibly producing damage as exemplified by the reference F.

This militates against personalizing fan-in WLCSP packages using reel-to-reel handling machines using pick&place technology, for instance.

One or more embodiments are based on the recognition that the structure of a WLCSP device D may be as exemplified in <FIG> and thus comprise a device body having:.

These features of a WLCSP device - essentially the fact that a WLCSP device D has (only) one "robust" and non-active surface (the coated back or bottom side D2) - can be exploited in handling a WLCSP device with the steps illustrated in <FIG>, in order to align onto an array of pogo-pins P for electrical testing, for instance.

<FIG> are exemplary of steps in aligning electrical contact formations (such as bumps or solder balls S in an array of electrical contact formations carried by a first surface D1 of a semiconductor device D) with electrically conductive pins in an array of electrically conductive pins such as "pogo" pins P.

As used herein, "aligning" is used to indicate the action of achieving a desired mutual positioning of electrical contact formations (bumps or solder balls, for instance) S and electrically conductive pins ("pogo" pins, for instance) P, in view of achieving electrical coupling
While the wording centering may also be used in more common language, the wording aligning may represent a more accurate description of such a desired mutual positioning aiming at having an array electrical contact formations facing a complementary array of electrically conductive pins lying in an adjacent plane.

In fact, while desired to be mutually positioned "in register" with each other, an array of electrical contact formations S and an array of electrically conductive pins P may not have a central point on a same axis.

One or more embodiments as exemplified in <FIG> may take advantage of the fact that a semiconductor device D such as a WLCSP device comprises, opposite the first surface D1, a second surface D2 protected by a protection layer such as the layer A.

It will be otherwise appreciated that the sequence of steps of <FIG> is merely exemplary insofar as:.

The steps illustrated in <FIG> provide a mechanical alignment (centering) method that can be implemented using a pick&place tool <NUM> (such as a vacuum cup of a known type) that picks the device D (from above in the case illustrated) and aligns the device D with respect to a "nest" member <NUM>.

As illustrated, such alignment (briefly, centering) is facilitated by chamfers C12 provided in the nest member <NUM>.

As illustrated, the chamfers C12 are upwardly converging chamfers and the device D is aligned (centered) with respect to the nest member <NUM> by being pulled upwardly by the tool (vacuum cup) <NUM> as indicated by an upward arrow T at the top of <FIG>.

As illustrated, the chamfered surface C12 in the first alignment member (nest member) <NUM> comprises a tapered surface (frusto-conical, for instance) converging in a tapering direction (here, in the upward direction of the arrow T) from a first end at the bottom of the member <NUM> towards a second end at the top of the member <NUM>.

As visible in <FIG>, aligning the semiconductor device D to the first alignment member <NUM> may thus comprise picking - via a tool <NUM> such as a vacuum cup <NUM> - the semiconductor device D (<FIG>) and advancing the semiconductor device D (picked at the second surface D2, here pointing upwardly) with respect to the chamfered surface C12 in the tapering direction thereof with the second surface D2 (protected by the layer A) exposed to the chamfered (tapered) surface C12.

In a positioning apparatus as illustrated in <FIG> such an pick-up advance/lifting movement (here exemplified by an arrow T in <FIG>) can be imparted to the tool <NUM> and/or the device D carried thereby via a motorization M (of a known type to those of skill in the art of pick&place machinery, for instance).

Alignment can thus take place during lifting the device D in response to the device D possibly sliding (in a lateral horizontal direction, for instance, here exemplified by an arrow L in <FIG>) under the picker tool <NUM> or with the picker tool <NUM> capable of moving correspondingly sidewise with respect to the nest member <NUM>.

In that way, in response to the displacement with respect to the chamfered surface C12 of the nest member <NUM>, the device (die) D can be adequately aligned (already) during the "pick" phase, with only the robust side (the back or bottom side D2 protected by the layer A) exposed to possible interaction (sliding, for instance) with the chamfers C12 (and with the picking tool <NUM>).

Thanks to the perfect alignment of the nest (member <NUM>) and the device D, the risk of damage at the (fragile) surface D1 as exemplified by reference F in <FIG> is thus effectively countered.

As illustrated in <FIG>, the nest member <NUM> - having the device D adequately aligned therein (during the pick phase: see <FIG>), can be coupled, and thus aligned, with a mating socket member <NUM> to let the bumps or balls S in the device D finally "land" (<FIG>) on the pins P that are aligned (in a manner known per se to those of skill in the art) with the socket member <NUM>.

In an apparatus as depicted in <FIG>, such a landing movement can be in response to the picking tool <NUM> carrying the aligned (centered) device D being lowered towards the socket member <NUM> (and the pins P) as indicated by an arrow L in <FIG> via a motorization of a known type. This can be the same motorization M used for the picking/lifting movement T used for aligning the device D with the nest member <NUM> as illustrated <FIG>.

Provided the nest member <NUM> and the socket member <NUM> are properly mutually aligned, the device D - and, more to the point, the bumps or balls S at the underside of the device D - will land on the pogo-pins P in (precise) alignment therewith as desired, in view of subsequent coupling via soldering, for instance.

This result can be achieved by providing the nest member <NUM> and the socket member <NUM> with mating formations ("fiducials") R1, R2 configured to facilitate (accurate) mutual alignment.

As illustrated, these fiducials R1, R2 may comprise cavities R1 at the (here lower) surface of the nest member <NUM> configured to be engaged by mating projections R2 (pins, for instance) at the (here upper) surface of the socket member <NUM>.

In a complementary manner, these fiducials R1, R2 may comprise cavities at the surface of the socket member <NUM> configured to be engaged by corresponding mating projections (pins, for instance) at the adjacent surface of the nest member <NUM>.

Also mixed arrangements, with the fiducials R1, R2 comprising cavities and projections carried by both the nest member <NUM> and the socket member <NUM> are feasible.

Advantageously, the fiducials R1, R2 may comprises self-centering mating features configured to mutually co-operate in a centering cone arrangement. In various embodiments, such features may include ramp formations protruding from the second alignment member (socket member <NUM>) to engage the chamfered surface C12 in the first alignment member (nest member <NUM>) in a centering cone arrangement.

Whatever the specific implementation of the mutual alignment features R1, R2, the device D (which is aligned with the nest member <NUM>) and more to the point, the bumps or balls S at the first surface D1, will be aligned as desired with the pogo-pins P (which are aligned with the socket member <NUM>).

To summarize, an apparatus as illustrated in <FIG> comprises a first alignment member (the nest member <NUM>) and a second alignment member (the socket member <NUM>) that configured to be coupled in a mutually aligned relationship (via centering features such as the "fiducials" R1, R2, for instance).

During the "pick" phase of <FIG>, the semiconductor device D (and thus the formations S at the surface D1) are aligned to the first alignment member <NUM>.

This can be achieved by exposing to the chamfered surface C12 in the nest member <NUM> (only) the second surface D2 of the device D, which is protected by the protective layer A.

As illustrated in <FIG> and <FIG>, the second centering member (the socket member <NUM>) is aligned with respect to the array of electrically conductive pins P.

As a result, the array of electrical contact formations (bumps or balls S) in the device D ends up by being aligned with respect to the array of electrically conductive pins P as desired in so far as the first alignment member (nest member <NUM>) and the second alignment member (socket member <NUM>) are mutually coupled.

As illustrated, this may take place in response to the device D being "landed" onto the pins P in an aligned relationship due to the presence of the complementary formations R1, R2, for instance) with the alignment members <NUM> and <NUM> having in turn aligned therewith:.

<FIG> is exemplary of a conventional personalization flow of a WLCSP device based on waferlevel personalization (as represented by block <NUM>) of a bumped wafer BW based on design data such as operating system, OS, profile and data generation information <NUM> as provided by a source such as a telecom operator <NUM>.

As illustrated in <FIG>, the results of waferlevel personalization of block <NUM> can be subjected to singulation (wafer dicing) as represented by block <NUM>, after which WLCSP devices in reel form WR can be made available to delivery as represented by block <NUM>.

<FIG> is exemplary of a personalization flow of a WLCSP device according to embodiments of the present description.

In such a flow, personalization as represented by block <NUM> in <FIG> can be performed based on personalization information <NUM> on pick&place equipment as illustrated in <FIG> operating on WLCSP devices that already are in reel form WR in view of delivery as represented by block <NUM>.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection.

Claim 1:
A method, comprising:
aligning electrical contact formations (S) in an array of electrical contact formations on a first surface (D1) of a semiconductor device (D) with electrically conductive pins in an array of electrically conductive pins (P), wherein the semiconductor device (D) comprises, opposite the first surface (D1), a second surface (D2) protected by a protection layer (A), wherein the method comprises:
aligning the semiconductor device (D) to a first alignment member (<NUM>) by exposing said protected second surface (D2) of the semiconductor device (D) to a chamfered surface (C12) in the first alignment member (<NUM>), and
aligning the first alignment member (<NUM>) with a second alignment member (<NUM>) having the array of electrically conductive pins (P) aligned therewith, wherein the array of electrical contact formations (S) is aligned with respect to the array of electrically conductive pins (P) in response to the first (<NUM>) and second (<NUM>) alignment members being mutually aligned (R1, R2).