Patent Description:
For communication links between integrated circuits, or between circuits within an integrated circuit, it is generally desirable to limit the number of wires in order to reduce chip area. One solution for reducing the number of wires is to create a plurality of virtual channels that share a single physical channel. This is for example achieved by time multiplexing a plurality of data streams.

In the case of synchronous communications links, a clock signal is used at the receiver in order to correctly receive the transmitted data streams. This clock signal is generally transmitted over the communication link alongside the data. Such a solution is relatively robust against propagation delay variations over the communications link, as the propagation delays of the data streams and of the clock signal will remain substantially equal.

In such synchronous communications links, it has been proposed to implement flow control using a system of credits. A buffer, such as a FIFO (first-in-first-out) buffer is present on the transmission side to store data waiting to be sent over the communications link, and a further buffer, which is also for example a FIFO, is present on the reception side to store the data received over the communications link. If the data transmission rate over the communications link is too high, the FIFO on the reception side may become full, leading an interruption of the data transmission over the communications link. This issue is overcome by credit-based flow control, according to which the transmission circuit may only transmit a data value over the communications link in response to a credit received from the reception circuit. The reception circuit issues a credit each time a data value is read from its FIFO.

While existing solutions for credit-based flow control are relatively effective in preventing overflow in the FIFO of the reception circuit, they tend to require relatively large FIFOs, and bulky circuits for handling credits. There is thus a need in the art for a credit-based flow control solution addressing these issues.

<CIT> relates to a processor having first and second clock domains and involving the use of write credits.

<CIT> relates to an apparatus and method for providing a bidirectional communications link between a master device and a slave device.

It is an aim of embodiments of the present disclosure to at least partially address one or more needs in the prior art.

The foregoing and other features and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:.

Throughout the following description, the following terms will be given the following definitions:.

<FIG> illustrates an example of a communications link <NUM> according to an embodiment that has been proposed. A circuit having some similarities with the circuit of <FIG> is for example described in the publication entitled "ARM CoreLink TLX-<NUM> Network Interconnect Thin Links, Revision r0p3, Supplement to ARM CoreLink NIC-<NUM> Network Interconnect Technical Reference Manual", available at www. The communications link <NUM> comprises a transmitting circuit (TX) <NUM> and a receiving circuit <NUM>.

The transmitting circuit <NUM> receives a plurality of data streams <NUM> in corresponding buffers <NUM>, of which three are shown in <FIG>. The buffers <NUM> are bi-synchronous FIFO (first-in-first-out) buffers, data being input to these buffers under control of a clock signal CLK_T of a clock domain <NUM> of the transmitting circuit, and data being output from these buffers under control of a clock signal CLK of the communications link.

Each of the buffers <NUM> has its output coupled to a corresponding input of a multiplexer <NUM>, which applies time multiplexing to the data streams from the buffers <NUM> in order to provide a plurality of virtual channels over the communications link. The multiplexer <NUM> is controlled by a channel selection signal CHANNEL provided by a finite state machine (FSM) <NUM>. The output of the multiplexer <NUM> is coupled to a flip-flop <NUM> clocked by the clock signal CLK of the link, which transmits the data stream in the form of a data payload (PAYLOAD) to the receiving circuit <NUM>, over one or more wires. The channel selection signal CHANNEL is provided via a further flip-flop <NUM>, also clocked by the clock signal CLK, to the receiving circuit <NUM>, over one or more further wires. The clock signal CLK is also transmitted to the receiving circuit <NUM> on one or more further wires.

The receiving circuit <NUM> comprises a flip-flop <NUM> receiving the payload, and a flip-flop <NUM> receiving the channel selection signal CHANNEL. The flip-flops <NUM>, <NUM> are clocked by the clock signal CLK' received from the transmitting circuit <NUM>. The payload data and channel selection signal are stored in a bi-synchronous FIFO <NUM>, data being input to the FIFO <NUM> under control of the clock signal CLK', and data being output from the FIFO <NUM> under control of a clock signal CLK_R of a clock domain <NUM> of the receiving circuit <NUM>.

The payload data from the FIFO <NUM> is provided to the input of a demultiplexer <NUM> controlled by the channel selection signal CHANNEL at the output of the FIFO <NUM>. The outputs of the demultiplexer <NUM> are coupled to respective FIFOs <NUM> clocked by the clock signal CLK_R, one FIFO <NUM> being provided for each data stream <NUM>' received over the communications link.

The FSM <NUM> in the transmitting circuit permits data values of a channel to be transmitted only if a corresponding credit has been received from the receiving circuit <NUM>. The credits are generated by the receiving circuit <NUM> based on the data output from the synchronous FIFO buffers <NUM>. The credits being generated in the clock domain <NUM> of the receiving circuit, they are transmitted to the transmitting circuit <NUM> via a virtual channel of a further communications link formed of a transmitting circuit <NUM> and a receiving circuit <NUM>, which are similar to the circuits <NUM> and <NUM> respectively.

A drawback of the communications link <NUM> of <FIG> is that the use of the transmitting and receiving circuits <NUM>, <NUM> for the transmission of credits to the transmitting circuit <NUM> introduces a significant latency. This leads to FIFOs in the circuit that are relatively large. Indeed, the size of the FIFOs, and thus the number of credits that are available, should be greater than the number of clock cycles needed for an outward data transmission and return credit transmission. In the circuit of <FIG>, the flip-flops <NUM>, <NUM> of the circuits <NUM>, <NUM>, and the corresponding flip-flops of the circuits <NUM>, <NUM>, will each introduce a delay of one clock cycle, and the bi-synchronous FIFO <NUM>, and those of the circuits <NUM>, <NUM>, will each introduce a delay of up to three cycles, leading to an overall delay of around <NUM> cycles.

<FIG> illustrates a receiving circuit <NUM> according to an alternative implementation to the receiving circuit <NUM> of <FIG>. Many features of the receiving circuit <NUM> are the same as those of the circuit <NUM>, and like features have been labelled with like reference numerals and will not be described again in detail. In the receiving circuit <NUM>, the bi-synchronous FIFO <NUM> is omitted, and the FIFOs <NUM> are replaced by bi-synchronous FIFOs <NUM>. While such a solution allows the latency to be reduced by one cycle in each direction, the latency is still relatively high.

<FIG> schematically illustrates a communication link <NUM> according to an example embodiment of the present disclosure. The communications link <NUM> for example comprises a transmitting circuit (TX) <NUM> and a receiving circuit (RX) <NUM>.

The transmitting circuit <NUM> for example receives a plurality of data streams <NUM> in corresponding buffers <NUM>, three of which are shown in the example of <FIG>. The number of FIFOs <NUM> will depend on the number of data streams, and could be equal to one or more. The FIFOs <NUM> are for example bi-synchronous FIFOs, data being input to these buffers under control of a clock signal CLK_T of a clock domain <NUM> of the transmitting circuit, and data being output from these buffers under control of a clock signal CLK_V of the communications link.

Each of the FIFOs <NUM> for example has its output coupled to a corresponding input of a multiplexer <NUM>, which applies time multiplexing to the data streams from each buffer <NUM> in order to provide a plurality of virtual channels over the communications link. The multiplexer <NUM> is for example controlled by a channel selection signal CHANNEL provided by credit management circuit, implemented for example by a finite state machine (FSM) <NUM>. The output of the multiplexer <NUM> is for example coupled to a flip-flop <NUM> clocked by a clock signal CLK_V of the link, which transmits the data stream in the form of a data payload (PAYLOAD) to the receiving circuit <NUM>, over one or more wires. The channel selection signal CHANNEL is provided via a further flip-flop <NUM>, also clocked by the clock signal CLK_V, to the receiving circuit <NUM>, for example over one or more further wires. Credits (CREDITS) are for example received from the receiving circuit <NUM> on one or more input wires <NUM>, these wires being coupled to the input of a flip-flop <NUM> clocked by a clock signal CLK_V‴.

In some embodiments, the clock signal CLK_V is transmitted to the receiving circuit <NUM>. However, in the embodiment of <FIG>, a further clock signal CLK_V' is transmitted to the receiving circuit <NUM>. Each of the clock signals CLK_V' and CLK_V‴ are for example generated by a clock generation circuit <NUM> based on the clock signal CLK_V. The circuit <NUM> for example comprises the series connection of a variable delay element <NUM> and an inverting element <NUM> for providing the clock signal CLK_V‴, and the series connection of a variable delay element <NUM> and an inverting element <NUM> for providing the clock signal CLK_V'. The variable delay elements <NUM>, <NUM> each for example receive the clock signal CLK_V. The inverting elements <NUM>, <NUM> for example selectively invert the clock signals. The inverting element <NUM> for example comprises a multiplexer having a non-inverting input and an inverting input each coupled to the output of the variable delay element <NUM>. Similarly, the inverting element <NUM> for example comprises a multiplexer having a non-inverting input and an inverting input each coupled to the output of the variable delay element <NUM>. The delays introduced by the elements <NUM>, <NUM>, and the inversion or non-inversion of each of the signals by the elements <NUM>, <NUM>, are for example controlled by a control circuit (CTRL) <NUM>.

For example, the control circuit <NUM> is configured to calibrate the clocks signals CLK_V' and CLK_V‴ based on a calibration pattern transmitted over the communications link, the timing being adjusted until the calibration pattern is received correctly. Additionally or alternatively, a bit error rate (BER) of the data signals received via the communications link can be calculated, and the control circuit <NUM> for example calibrates the timing of the clock signals CLK_V' and CLK_V‴ such that the BER is reduced and/or minimized. As yet a further possibility, a stability detector based on early and late error or warning signals can be implemented as described in more detail in the patent application published as <CIT>, having the same applicant, inventor and filing date as the present application, and entitled "Method and device for improving synchronization in a communications link".

The receiving circuit <NUM> comprises a flip-flop <NUM> receiving the payload, and a flip-flop <NUM> receiving the channel selection signal CHANNEL. The flip-flops <NUM>, <NUM> are for example clocked by the clock signal CLK_V' received from the transmitting circuit <NUM>, which is relabelled CLK_V" in the receiver, the signal CLK_V" including the delay introduced by the wire between the transmitting and receiving circuits <NUM>, <NUM>.

The payload data is for example provided to the input of a demultiplexer <NUM>, which directs received data values to one of a plurality of FIFOs <NUM> corresponding to each of the virtual channels. This selection is for example based on the channel selection signal CHANNEL provided by the flip-flop <NUM>. The FIFOs <NUM> are for example clocked by the clock signal CLK_V". The FIFOs <NUM> are for example synchronous devices under control of a single clock signal, rather than bi-synchronous devices like the FIFOs <NUM> of <FIG>.

The output of each FIFO <NUM> is for example coupled to the input of a corresponding further FIFO <NUM>. The FIFOs <NUM> are for example bi-synchronous FIFOs, data values being input into these FIFOs <NUM> under control of the clock signal CLK_V", and data being output from these FIFOs <NUM> under control of the clock signal CLK_R of a clock domain <NUM> of the receiving circuit <NUM>. The FIFOs <NUM> output the data streams <NUM>' recuperated from the communications link.

In the embodiment of <FIG>, a credit signal generation circuit (CREDIT GEN) <NUM> generates credits based on the states of the synchronous FIFOs <NUM>. For example, the circuit <NUM> receives a credit trigger signal from each FIFO <NUM> indicating when a read operation of a data value stored in the FIFO has occurred. For example, in some embodiments this signal corresponds to the read pointer of the FIFO, and a read operation is indicated by an incrementation of this read pointer. The credit signal generation circuit <NUM> is for example clocked by the clock signal CLK_V", and outputs the credits, under control of this clock signal, on the wires <NUM> for transmission to the transmitting circuit <NUM>.

A number of different coding schemes can be used to encode the credit information onto the wires <NUM>. For example, in some embodiments one of the following encoding schemes is used:.

The number of bits used to encode the credit signal on each cycle will depend on the number of virtual channels and the particular credit encoding scheme that is adopted.

In the transmitting circuit <NUM>, the credits are for example received by the FSM <NUM> via the flip-flop <NUM>. The FSM <NUM> for example comprises a counter associated with each virtual channel, and increments the corresponding counter for each credit that is received for the given virtual channel. When a data value is waiting in one of the FIFOs <NUM>, and at least one credit is available in the corresponding counter of the FSM <NUM>, the FSM <NUM> for example controls the multiplexer <NUM> to select this data value to be transmitted to the receiver. For example, each FIFO <NUM> for example sends a signal to the FSM <NUM> indicating the availability of data to be transmitted. One credit is then deducted for this virtual channel, for example by decrementing the count value of the corresponding counter in the FSM <NUM>.

An advantage of the embodiment of <FIG> is that credits are generated based on read operations from FIFOs made in the clock domain of the communications link, in other words based on the clock CLK_V. Thus the credits can be transmitted to the transmitting circuit <NUM> using the same clock signal as is used to receive the data values at the receiving circuit <NUM>. This significantly reduces the number of clock cycles between the transmission of a data value and the reception by the transmitting circuit <NUM> of the corresponding credit. For example, while the delay in the embodiment of <FIG> and <FIG> was around <NUM> or <NUM> cycles, in the case of <FIG>, the delay is of only <NUM> clock cycles. Thus the size of the FIFOs <NUM> and <NUM>, and the number of bits representing each credit, can be relatively low.

The operations of the circuit of <FIG> will now be described in more detail with reference to the timing diagram of <FIG>.

<FIG> illustrates the signal CLK_V, the payload (PAYLOAD) output from the transmitting circuit <NUM>, the clock signal CLK_V' generated by the circuit <NUM>, the clock signal CLK_V" received by the receiving circuit, the data (RECEIVED DATA) received by the receiving circuit, the credits (SEND CREDITS) generated by the circuit <NUM>, the clock signal CLK_V‴ and the credits (RECEIVED CREDITS) received by the transmitting circuit <NUM>.

In the example of <FIG>, the payload comprises data values DATA1, DATA2, etc., transmitted on rising edges of the clock signal CLK_V. Furthermore, in the example of <FIG> the clock signal CLK_V' is a simple inversion of the clock signal CLK_V. The clock signal CLK_V" corresponds to the clock signal CLK_V' delayed by a delay DPROP1, equal to the delay introduced by the transmission channel between the transmitting circuit <NUM> and receiving circuit <NUM>. In the example of <FIG>, the rising edges of the clock signal CLK_V" are used to clock the received data, this data having been received after substantially the same delay as the propagation delay DPROP1 of the clock signal CLK_V'. The delay element <NUM> of <FIG> can be used to correct small differences between the propagation delays of the PAYLOAD data signal and of clock signal CLK_V'.

Credits CREDIT1, CREDIT2, etc., are for example generated on each rising edge of the clock signal CLK_V", and transmitted to the transmitting circuit <NUM>. The credits are for example received after a propagation delay DPROP2, which is for example substantially equal to the propagation delay DPROP1. The received credits are for example clocked by rising edges of the clock signal CLK_V‴. The relative timing of the clock signals CLK_V and CLK_V‴ is for example chosen such that the credits can be correctly received at the transmitting circuit. In the example of <FIG>, rising edges of the clock signal CLK_V‴ are for example adjusted, by the circuit <NUM> of <FIG>, to fall at around the mid-point between the transitions of the received credit data signal.

In an alternative embodiment to that of <FIG>, the synchronous FIFOs <NUM> could be replaced by bi-synchronous FIFOs, allowing the bi-synchronous FIFOs <NUM> to be omitted, in a similar manner to the embodiment of <FIG>. However, in such a case the bi-synchronous FIFOs are for example modified to provide a credit trigger signal, synchronous with the clock CLK_V", indicating when a read operation has occurred, as will now be described in more detail with reference to <FIG>. In this way, credits can be generated and transmitted to the transmitting circuit <NUM> without crossing from one clock domain to another.

<FIG> illustrates a modified bi-synchronous FIFO <NUM> according to an example embodiment. Such a circuit for example implements each of the bi-synchronous FIFOs of the receiving circuit <NUM>. As with the bi-synchronous FIFOs <NUM> of <FIG>, the bi-synchronous FIFO <NUM> inputs data values under control of the clock signal CLK_V", and outputs data values under control of the clock signal CLK_R. The bi-synchronous FIFO <NUM> additionally comprises a credit trigger generation circuit <NUM>. The circuit <NUM> for example determines, based on a read pointer of the FIFO <NUM>, when a read operation has occurred, and activates the output signal SCREDIT accordingly.

<FIG> represents the storage locations and read and write pointers of the FIFO <NUM> according to an example embodiment. In the example of <FIG>, the FIFO <NUM> comprises <NUM> storage locations each capable of storing a data value, and represented by segments of donut-shaped ring. Of course, in practise the FIFO <NUM> could comprise a greater number or fewer storage locations. A write pointer i points to the storage location being written to, and a read pointer j points to the storage location being read, and x's in the figure designate storage locations storing data. As indicated above, the write pointer is for example synchronous with the clock CLK_V", whereas the read pointer is for example synchronous with the clock CLK_R.

<FIG> illustrates the credit generation module <NUM> of the FIFO <NUM> in more detail according to an example embodiment.

The module <NUM> for example receives the clock signal CLK_V" and the read pointer j. Two flip-flops <NUM>, <NUM> coupled in series are for example used to resynchronize the value of the read pointer j with the clock signal CLK_V". The resynchronized read pointer j' at the output of the flip-flop <NUM> is for example provided to a subtractor <NUM>, which subtracts from the value j' a count value m, and provides the result d to a comparator <NUM>. The comparator <NUM> determines whether the result d is greater than zero, and if so, activates the signal SCREDIT to generate a credit. This signal also causes the count value m to be incremented. For example the count value m is provided to an adder <NUM>, which increments the count value m each time the signal SCREDIT is activated. The result m' of the addition performed by the adder <NUM> is for example provided to a flip-flop <NUM>, which stores the value m' on each significant clock edge of the clock signal CLK_V". Thus an increment of the read pointer j will cause, following a subsequent significant edge of the clock signal CLK_V", a credit to be issued, and the count value m to be incremented so that another credit will not be issued until j' is again incremented. The count value m is for example initiated at zero following a reset of the module <NUM>.

<FIG> is a cross-section view of a 3D circuit <NUM> according to an example embodiment.

The circuit for example comprises chiplets <NUM>, three of which are illustrated in the example of <FIG>. Each chiplet <NUM> is for example mounted on an interposer <NUM>, which provides active or passive buffering between the chiplets, and for example implements the communications link described herein. The interposer <NUM> is for example mounted on a package <NUM>.

In alternative embodiments, the communications link described herein could be applied to other applications, such as to communications interfaces within a same integrated circuit, between circuits of an NoC (Network-On-Chip), or to interconnect several NoCs.

An advantage of the embodiments described herein is that the delay for the transmission of a data value across a communications link and for the return of a corresponding credit can be significantly reduced with respect to existing solutions. This permits the size of at least some of the FIFOs of the communications link to be reduced, and also for a reduction in size of the credit counters.

Having thus described at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, while in the embodiment of <FIG> the clock signal CLK_V' is transmitted to the receiving circuit <NUM>, in alternative embodiments no clock signal could be transmitted, and instead a clock signal could be recuperated by the receiving circuit from the data stream.

Furthermore, while the example embodiment of <FIG> presents a single data rate (SDR) implementation, it will be apparent to those skilled in the art that the architecture could be modified to provide a double data rate (DDR) implementation. In such a case, half of the payload data is for example transmitted during the high state of the clock signal CLK_V, and the other half of the data is sent during the low state of the clock signal CLK_V. The registers <NUM> and <NUM> for example latch half of the payload on rising edges and the other half of the payload on falling edges. The registers <NUM>, <NUM> on the receive side operate in a similar manner, latching the data on rising and falling edges. This results in a time multiplexing that allows the number of payload wires to be reduced by a factor of two. Indeed, the full payload can be sent during a full clock cycle using half the number of wires. Alternatively, for a same number of payload wires, the amount of data transmitted can be increased by a factor of two.

Claim 1:
A receiving circuit of a communications link, the receiving circuit comprising:
a first data buffer (<NUM>, <NUM>) configured to input, under control of a first clock signal (CLK_V"), data of a first data stream transmitted by a transmitting circuit (<NUM>), and to generate a credit trigger signal indicating when a data value is read from the first data buffer (<NUM>, <NUM>), wherein the first clock signal is received from the transmitting circuit (<NUM>) or recuperated by the receiving circuit from the first data stream, and wherein said data value is read from the first data buffer (<NUM>), or from a further data buffer (<NUM>) of the receiving circuit coupled to the output of the first data buffer (<NUM>, <NUM>), under control of a second clock signal (CLK_R); and
a credit generation circuit (<NUM>) configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit (<NUM>) under control of the first clock signal (CLK_V"), the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.