Patent Description:
An example of a trimmable circuit is an operational transconductance amplifier. One source of error associated with an operational transconductance amplifier is the offset current present on the output. If set properly, trim current can be used to negate the effects of the offset current of the operational to around zero.

In certain instances, it is necessary to produce a very small trim current because a respective error source to be corrected is very small. However, a small current is not easy to generate, since it would imply, for example, a strong scaling of a bandgap current (IB=VBG/R). Such a scaling can be done via either a large resistor and/or with a current mirror having a huge aspect ratio, both of which are undesirable.

<CIT> discloses a pre-amplifier with a selectable threshold voltage in a decision feedback equalization circuit to reduce tap weight variation. A decision feedback equalization circuit includes a summer circuit and a preamplifier with an offset generator, wherein the pre-amplifier includes a pair of differential amplifiers and each biased by a respective current bias and each having first and second output nodes coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistor, or any other active or passive circuitry for establishing a resistance. The inputs of first differential amplifier are coupled to the summer's output. The inputs of second differential amplifier are coupled to a reference voltage circuit that comprised of a resistive element and a respective current DAC (IDAC).

This disclosure includes the observation that conventional techniques of producing trim currents are undesirable. For example, as previously discussed, large integrated resistors used in conventional trim circuits typically occupy a large area and introduce noise in a respective system. Additionally, having current mirrors with a large scaling ratio could compromise respective matching, because the matched structures start to be very different from each other. Yet further, a current mirror conducting current in the nano-ampere range means that the CMOS field effect transistor devices are most likely working in the sub-threshold region. This operating area is not always well-modelled; therefore, there is the risk of designing a circuit whose real behavior is completely different than expected.

Embodiments herein provide improved trimming over conventional techniques.

The invention is defined by the appended independent claims and preferred embodiments are set out in the dependent claims.

Note that embodiments herein are useful over conventional techniques. For example, the trim system as described herein provides a novel way of signal tracking (between an output signal of a driver resource and a generated trim signal) in which the generated trim signal (of low magnitude) ratiometrically tracks a respective control signal to provide correction of one or more operational parameters of an electronic component (such as an integrated circuit) being trimmed.

These and other more specific embodiments are disclosed in more detail below.

Note that any of the resources implemented in system as discussed herein can include one or more computerized devices, mobile communication devices, servers, base stations, wireless communication equipment, communication management systems, controllers, workstations, user equipment, handheld or laptop computers, or the like to carry out and/or support any or all of the method operations disclosed herein. In other words, one or more computerized devices or processors can be programmed and/or configured to operate as explained herein to carry out the different embodiments as described herein.

Yet other embodiments not forming part of the claimed invention herein include software programs to perform the steps and operations summarized above and disclosed in detail below. One such embodiment comprises a computer program product including a non-transitory computer-readable storage medium (i.e., any computer readable hardware storage medium) on which software instructions are encoded for subsequent execution. The instructions, when executed in a computerized device (hardware) having a processor, program and/or cause the processor (hardware) to perform the operations disclosed herein. Such arrangements are typically provided as software, code, instructions, and/or other data (e.g., data structures) arranged or encoded on a non-transitory computer readable storage medium such as an optical medium (e.g., CD-ROM), floppy disk, hard disk, memory stick, memory device, etc., or other a medium such as firmware in one or more ROM, RAM, PROM, etc., or as an Application Specific Integrated Circuit (ASIC), etc. The software or firmware or other such configurations can be installed onto a computerized device to cause the computerized device to perform the techniques explained herein.

Accordingly, embodiments herein are directed to a method, system, computer program product, etc., that supports operations as discussed herein.

One embodiment not forming part of the claimed invention includes a computer readable storage medium and/or system having instructions stored thereon to produce a trim signal. The instructions, when executed by computer processor hardware, cause the computer processor hardware (such as one or more co-located or disparately located processor devices or hardware) to: produce an output signal; derive a differential drive signal from the output signal; and generate a (differential) trim signal from the differential drive signal.

The ordering of the steps above has been added for clarity sake. Note that any of the processing steps as discussed herein can be performed in any suitable order.

Other embodiments not forming part of the claimed invention of the present disclosure include software programs and/or respective hardware to perform any of the method embodiment steps and operations summarized above and disclosed in detail below.

It is to be understood that the system, method, apparatus, instructions on computer readable storage media, etc., as discussed herein also can be embodied strictly as a software program, firmware, as a hybrid of software, hardware and/or firmware, or as hardware alone such as within a processor (hardware or software), or within an operating system or a within a software application.

Note further that although embodiments as discussed herein are applicable to trimming, the concepts disclosed herein may be advantageously applied to any other suitable topologies.

Also, note that this preliminary discussion of embodiments herein purposefully does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention(s). Instead, this brief description only presents general embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives (permutations) of the invention(s), the reader is directed to the Detailed Description section (which is a summary of embodiments) and corresponding figures of the present disclosure as further discussed below.

The foregoing and other objects, features, and advantages of embodiments herein will be apparent from the following more particular description herein, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, with emphasis instead being placed upon illustrating the embodiments, principles, concepts, etc..

As previously discussed, according to one embodiment, a trim system includes an adjustable driver resource, a differential voltage generator, and a trim current generator. The adjustable driver resource produces an output signal. The differential voltage generator receives the output signal from the adjustable driver resource and produces a differential drive signal. The trim current generator derives a trim signal from the differential drive signal received from the differential voltage generator. According to one configuration, the trim current generator outputs the trim signal to an electronic component, correcting one or more operational parameters of the electronic component.

Now, with reference to the drawings, <FIG> is an example diagram illustrating a simplified representation of a trim system according to embodiments herein. As shown, the example trim system <NUM> (such as a trim circuit) in <FIG> includes driver resource <NUM> (such as controllable drive resource), differential voltage generator <NUM>, and trim current generator <NUM>. In this example embodiment, the driver resource <NUM> is operable to receive control signal <NUM> from the controller <NUM>. Driver resource <NUM> produces output signal <NUM> based on the control signal <NUM>.

Differential voltage generator <NUM> is coupled to receive signal <NUM> from the driver resource <NUM>. Signal <NUM> is an output signal with respect to the driver resource <NUM> and an input signal with respect to the differential voltage generator <NUM>.

Further, trim current generator <NUM> is coupled to receive differential drive signal <NUM> (such as drive signal <NUM>-<NUM> and drive signal <NUM>-<NUM>) from the differential voltage generator <NUM>.

Based on the differential drive signal <NUM>, trim current generator <NUM> produces differential trim signal <NUM> (trim signal <NUM>-<NUM> and trim signal <NUM>-<NUM>) to provide trimming to the electronic component <NUM>.

In general, embodiments herein provide improved trimming over conventional techniques. For example, during operation, the (adjustable) driver resource <NUM> produces signal <NUM> (such as an output signal from adjustable driver resource and input signal to the differential voltage generator <NUM>) based on control signal <NUM> provided by controller <NUM>.

The control signal <NUM> controls an amount of current (associated with signal <NUM>) outputted from the driver resource <NUM> to the differential voltage generator <NUM>.

Yet further, the differential voltage generator <NUM> produces a differential drive signal <NUM> (such as drive signal <NUM>-<NUM> and drive signal <NUM>-<NUM>) based on the received signal <NUM> (such as current) from the driver resource <NUM>. The trim current generator <NUM> derives one or more trim signals (such as differential trim signal <NUM> including trim signal <NUM>-<NUM> and trim signal <NUM>-<NUM>) from the differential drive signal <NUM> received from the differential voltage generator <NUM>.

In one embodiment, the trim current generator <NUM> outputs the one or more trim signals <NUM> to an electronic component <NUM> being trimmed. Trimming provides increased accuracy of the electronic component <NUM>.

In accordance with the invention a magnitude of the differential trim signal <NUM> ratiometrically tracks the amount of current inputted to the differential voltage generator <NUM> via the signal <NUM>. For example, in one nonlimiting example embodiment, a difference in current (measured in amperes) between the trim signal <NUM>-<NUM> and <NUM>-<NUM> tracks a magnitude of the current provided by signal <NUM> to the differential voltage generator <NUM>. The trim signal(s) outputted from the trim system <NUM> corrects an operational parameter of the electronic component <NUM> such as an input offset current or other operational parameter of the electronic component <NUM> requiring one or more trim signals to provide correction.

Note that the trim system as described herein can be instantiated in any suitable manner. For example, the trim system <NUM> can be implemented on an integrated circuit on which the electronic component resides, as one or more integrated circuits (a. , a semiconductor chip), discrete circuit components, etc..

<FIG> is an example diagram illustrating details of a trimmer system according to embodiments herein. In this example embodiment, driver resource <NUM> is a current source supplying signal <NUM> (such as current IB2) to the differential voltage generator <NUM>. The controller <NUM> produces and outputs control signal <NUM> to control a magnitude of the current associated with signal <NUM> (IB2) delivered to the differential voltage generator <NUM>.

As further shown, the differential voltage generator <NUM> is configured as or configured to include a resistor R1 (having resistance R) and common mode source VCM (i.e., circuit component).

In this example embodiment, resistor R1 is coupled between the driver resource <NUM> and the common mode voltage source VCM. Accordingly, embodiments herein include a circuit component (common mode voltage source) disposed between the differential voltage generator <NUM> and a reference voltage (ground reference).

As described herein, the circuit component (i.e. common mode source Vcm) provides an offset of the differential drive signal (VDIFF) with respect to a corresponding reference voltage such as ground reference voltage.

Trim current generator <NUM> includes current source <NUM>, resistor R2, resistor R3, transistor P1 (a. , a first trim current control element) and transistor P2 (a. , a second trim current control element).

During operation, current source <NUM> receives power from input voltage source VDD. Current source <NUM> drives corresponding current IB3 (signal) through the parallel circuit paths including transistor P1 and transistor P2.

More specifically, a first transistor path of trim current generator <NUM> includes a series combination of resistor R2 and transistor P2 (switch); a second transistor path of trim current generator <NUM> includes a series combination of resistor R3 and transistor P1 (switch).

As further shown, transistor P1 controls generation of trim signal <NUM>-<NUM>; transistor P2 controls generation of trim current <NUM>-<NUM>.

In one embodiment, the resistance of R2 is K times the resistance of resistor R1; the resistance of resistor R3 is K times the resistance of resistor R1.

Further in this example embodiment, the input to the differential voltage generator <NUM> (a. , a cell) is current IB2, which creates a differential voltage VDIFF across resistor R1 as previously discussed. This differential voltage VDIFF (magnitude of VD2-VD1 or VD1-VD2) appears in series with the common mode source (VCM) of the differential voltage generator <NUM>.

In one embodiment, the common mode source Vcm is the common voltage of the differential element pair constituted by transistors P1 and P2, which collectively control generation of differential trim current <NUM>.

In this example embodiment, the voltage VD2 drives the gate node of transistor P2; the voltage VD1 drives the gate node of transistor P1.

Based on the magnitude of the voltage VD1 applied to its gate, transistor P1 (a. , current flow control element such as a switch, field effect transistor, bipolar junction transistor, etc.) controls a magnitude of current provided by trim signal <NUM>-<NUM>; based on the magnitude of the voltage VD2 applied to its gate, transistor P2 (a. , current flow control element such as a switch, field effect transistor, bipolar junction transistor, etc.) controls generation of trim signal <NUM>-<NUM>.

During conditions in which IB2 is zero, then VDIFF is also zero and the differential pair is at equilibrium. In such an instance, each of the respective circuit paths (such as a first circuit path including transistor P1 and resistor R2 (which equals k times the resistance of R1), and a second circuit path including transistor P2 and resistor R3 (which equals K times the resistance of R1) conduct a current at a magnitude equal to IB3/<NUM>, and therefore the differential trim current I1-I2 is null (i.e., zero).

If, on the other hand, the current IB2 is different than a zero setting, then differential voltage VDIFF is non-zero and creates an unbalance in the differential pair current I1 (<NUM>-<NUM>) and I2 (<NUM>-<NUM>). A magnitude of the difference between I1 and I2 varies depending upon the magnitude of the current IB2 provided by drive resource <NUM> to the differential voltage generator <NUM>.

Assuming that the magnitude of the perturbation is small with respect to the magnitude of the quiescent point, this unbalance will create a differential current I_DIFF equal to: <MAT> where gm represents the transconductance of transistors P1 and P2.

Assuming now that gm * K * R1 >> <NUM> and knowing that VDIFF = R1 * IB2, then eq. (<NUM>) becomes: <MAT>.

The above expression essentially shows that the output current of the degenerated transconductor is a function of the input current IB2 and of the resistor-ratio K (for example ratio of resistances R2/R1 = K, ratio of resistances R3/R1 = K). Therefore, a current scaling of ratio K is potentially attainable via trim system <NUM>.

The control current IB2 is fairly large with respect to the trim current (trim signal <NUM>-<NUM> and trim signal <NUM>-<NUM>), which is much smaller depending on the magnitude of the ratio, K.

<FIG> is an example diagram illustrating implementation of an analog-to-digital converter in a trimmer circuit according to embodiments herein.

In this example embodiment, the driver resource <NUM> is or includes a digital-to-analog converter <NUM>. In such an instance, the LSB of the driver resource <NUM> is now IB/K, where K can be set to any suitable value in a range between <NUM> and <NUM>, or K is a value in a range between <NUM> and <NUM>, or any suitable value outside these example ranges. In one embodiment, the ratio between IB and IB2 is greater or less than <NUM> such as between <NUM>/<NUM> and <NUM>.

In such an instance, this means that IB2 (if it were otherwise used as the final trim current itself) does not need to be in the nano-amperes range, which eliminates the necessity of huge resistors and large current mirror ratios to generate it. Instead, the current IB2 (signal <NUM>) is used as a base drive current through the differential voltage generator <NUM> to ratiometrically control a magnitude of the differential trim signal <NUM>. In other words, in one embodiment, the trim current <NUM> (IDIFF I1 - I2) is IB2 * (<NUM>/K). Thus, embodiments herein provide a way to generate a very small current from a base current signal <NUM>.

Another benefit of the proposed solution is the fact that the transistors making up the current mirrors do not need to work in the sub-threshold region, which makes the circuit less dependent on the models of the devices. The same observation is valid for transistors P1 and P2, which can easily operate in the saturation region even though their differential current is in the nano-amperes range.

Finally, via embodiments herein, the circuit designer has an additional degree of freedom with respect to choosing a value for K. In particular, the LSB also depends on the resistor ratio K, which can be adjusted separately from other circuit parameters.

<FIG> is an example diagram illustrating details of a trimmer circuit according to embodiments herein. In this example embodiment of trim system <NUM>-<NUM>, the current source <NUM> supplies respective current IB2_max/<NUM> to node <NUM> of the differential voltage generator <NUM>-<NUM> (such as resistor R1); corresponding current source <NUM> sinks current IB2 from node <NUM>. Current source <NUM> drives current I to node <NUM> of the differential voltage generator <NUM>-<NUM>. Controller <NUM> controls a magnitude of current IB2.

As previously discussed, a magnitude of the differential trim current (IDIFF = I1 - I2) varies depending on the differential voltage VDIFF across resistor R1, which itself varies depending on the applied drive current IB2.

Embodiments herein include sweeping a range of different drive currents inputted through the resistor R1 to vary the magnitude of the trim current as shown in <FIG>.

<FIG> is an example diagram illustrating adjustment of a trim signal over a range of trim value settings according to embodiments herein. As previously discussed, a respective digital-to-analog converter associated with the adjustable driver resource <NUM> can include any number of bits. As shown in timing diagram <NUM>, for an example <NUM> bit digital-to-analog converter, the input of a respective digital-to-analog converter varies in a range between <NUM> and <NUM> to produce different trim current values.

More specifically, controller <NUM> produces control signal <NUM> to set the analog-to-digital converter. IB2 from current source <NUM> equals IB2_max when control signal <NUM> = <NUM>; thus, IB2_max represents the maximum current of IB2 outputted by current source <NUM> (such as a digital-to-analog converter) when control signal <NUM> is <NUM>.

IB2 = IB2_max/<NUM> when control signal <NUM> is set to <NUM>; thus, IB2_max/<NUM> represents the middle point current of IB2 outputted by current source <NUM> (such as a digital-to-analog converter) when control signal <NUM> is <NUM>.

Current source <NUM> applies current I to node <NUM> of the resistor R1.

With further reference to the trim system <NUM>-<NUM> in <FIG>, when I > IB2, for <NUM> ≤ IB2 < IB2_max/<NUM> (such as IB2 varying based on input settings between <NUM> and <NUM>), VDIFF > <NUM> and there is the maximum positive correction for IB2 = <NUM>.

For a condition in which IB2 = IB2_max/<NUM>, VDIFF = <NUM>, IDIFF = <NUM>, there isn't any trim correction because I1 = I2.

For a condition in which IB2_max/<NUM> < IB2 ≤ IB2_max (such as IB2 varying based on input between <NUM> and <NUM>), VDIFF < <NUM> and there is the maximum negative correction for IB2 = IB2_max.

Note that a respective designer could decide how many steps and the preferred step size template information to implement trimming.

Additionally, note that if a voltage supply is used as reference voltage in the circuit, the current source <NUM> producing IB is not necessary anymore.

The advantage of this solution in <FIG> and <FIG> is that only one trim ramp (varying between input digital-to-analog converter range <NUM> and <NUM>) is necessary to find the correct trim setting for electronic component <NUM>.

<FIG> is an example diagram illustrating application of a trim signal to an electronic component according to embodiments herein. In this example embodiment, the trim system <NUM>-<NUM> provides trim adjustment to electronic component <NUM>-<NUM>.

Electronic component <NUM>-<NUM> includes current source <NUM> and devices M1, M2, M3, and M4. Note that each of the devices M1, M2, M3, and M4 can be any suitable type of resources such as a field effect transistor, bipolar junction transistor, etc..

In one embodiment, electronic component <NUM>-<NUM> is an amplifier such as an operational amplifier circuit. In one embodiment, the electronic component <NUM>-<NUM> is a transconductance amplifier having a differential output. Node <NUM> represents an inverting input (-) of the active load of the operational amplifier circuit. Node <NUM> represents the noninverting input (+) of the active load of the operational amplifier circuit.

As further shown, device M1 is connected in series with device M3; device M2 is connected in series with device M4.

Ideally, the current source <NUM> produces the current IBIAS that is split between flowing through switch M1 and switch M2 of the electronic component <NUM>-<NUM>. However, in this example embodiment, the electronic component <NUM>-<NUM> has an error of IOFFSET associated with the non-inverting input node <NUM>.

As previously discussed, embodiments herein include substantially reducing or eliminating this source of error via a respective differential trim signal <NUM>.

In such an instance, as shown in <FIG>, the switch M1 inputs current IBIAS/<NUM> - IOFFSET/<NUM> into the node <NUM>; the switch M2 inputs current IBIAS/<NUM> + IOFFSET/<NUM> into the node <NUM>. As previously discussed, IOFFSET represents an error in the electronic component <NUM>-<NUM> that will be corrected via the trim signal <NUM>.

As further discussed below, embodiments herein include controlling the trim system <NUM>-<NUM> to produce a respective differential trim signal <NUM> such that the IOFFSET of the electronic component <NUM>-<NUM> is substantially reduced to zero.

For example, as shown, the trim signal <NUM>-<NUM> is inputted to the node <NUM>. The trim signal <NUM>-<NUM> is inputted to the node <NUM>. As further discussed below, input of the trim signal to the electronic component <NUM>-<NUM> eliminates the offset current error IOFFSET to zero or substantially reduces it to be around zero.

Accordingly, embodiments herein include generation of a trim signal <NUM> to cancel an offset current (IOFFSET) associated with the inverting input node <NUM> and the non-inverting input node <NUM> of the respective electronic component <NUM>-<NUM>.

As further discussed below, embodiments herein include operating the electronic component <NUM>-<NUM> in a test mode in which both nodes <NUM> and <NUM> are driven with a same voltage value (such as from common mode source Vcm). The monitor resource <NUM> monitors an output <NUM> of the electronic component <NUM>-<NUM> while the controller <NUM> varies a magnitude of the current driving the resistor R1 to determine a proper amount of trim current <NUM> needed to reduce IOFFSET to zero or substantially zero.

<FIG> is an example diagram illustrating adjustment of a trim signal over a range of settings to select a trim setpoint according to embodiments herein. As previously discussed, one way to identify a respective setpoint for the trim system <NUM>-<NUM> (to substantially eliminate the IOFFSET current) is to set the node <NUM> and node <NUM> of the electronic component <NUM>-<NUM> (circuit being trimmed) to a same common mode voltage (such as ground or any other suitable value) as shown in <FIG>.

Monitor resource <NUM> monitors the output voltage (at output <NUM>) of the electronic component <NUM>-<NUM> while the trim system <NUM>-<NUM> applies different trim settings (trims signals) to the respective nodes <NUM> and <NUM> as shown.

As shown in <FIG>, while stepping through the range (such as starting at setting <NUM> and monotonically stepping through the different settings <NUM>, <NUM>, <NUM>, etc., to increase a magnitude of the trim current) of possible trim currents via control of current source <NUM> as shown in graph <NUM> of <FIG>, the monitor resource <NUM> keeps track of a corresponding trim control setting applied by controller <NUM> to the current resource <NUM> when detecting that the output voltage (at output <NUM>) of the electronic component <NUM>-<NUM> switches from one state to another, such as from a logic low to a logic high state.

In this example embodiment, the value (such as <NUM> or <NUM>) represents the setting of the trim system <NUM>-<NUM> that is needed to substantially reduce the IOFFSET error current associated with the electronic component <NUM>-<NUM> to zero (or around zero). In other words, setting the current through resistor R1 based on setting <NUM> produces an appropriate trim signal to eliminate IOFFSET.

Further embodiments herein include storing the identified value (<NUM> or <NUM>) and operating the trim system <NUM>-<NUM> at this setting during a non-test mode in which the electronic component <NUM>-<NUM> is used in a respective circuit application.

Thus, embodiments herein identifying an appropriate trim setting to correct the parameter associated with the electronic component <NUM>-<NUM> and then implement the identified trim setting in a non-test mode implementation of the electronic component <NUM>-<NUM> to provide increased accuracy of the electronic component <NUM>-<NUM>.

<FIG> is an example diagram illustrating a trimmer system including a network of switches according to embodiments herein. This example embodiment includes network of switches <NUM> (such as switches S1, S2, S3, and S4) enabling conveyance of the voltage VD1 (of differential voltage VDIFF) at node <NUM> of differential voltage generator <NUM> (such as resistor R1) to either gate of transistor P1 or gate of transistor P2 depending on settings of the network of switches <NUM>.

The network of switches <NUM> also enables conveyance of the voltage VD2 (of differential voltage VDIFF) at node <NUM> of differential voltage generator <NUM> (such as resistor R1) to either gate of transistor P2 or gate of transistor P1 depending on settings of the network of switches <NUM>.

For example, controller <NUM> generates control signals <NUM> to control states of respective switches S1, S2, S3, and S4 in network of switches <NUM>.

In a first operational mode, as further discussed below, activation of both switch S2 and switch S3 at the same time (while switch S1 and switch S4 are open) causes the voltage VD1 of the differential voltage VDIFF at node <NUM> to drive the gate node of transistor P1 and the voltage VD2 of the differential voltage VDIFF at node <NUM> to drive the gate node of transistor P2.

Conversely, in a second operational mode, as further discussed below, activation of both switch S1 and switch S4 closed at the same time (while switch S2 and switch S3 are open) causes the voltage VD1 at node <NUM> to drive the gate node of transistor P2 and the voltage VD2 at node <NUM> to drive the gate node of transistor P1.

The advantage of the solution as described herein (including network of switches <NUM>) is that the current consumption is lower and the circuit area to instantiate a respective trim system is smaller.

In a similar manner as previously discussed, the controller <NUM> can be configured to step through different settings to determine an appropriate trim current needed to reduce or eliminate the offset current error IOFFSET to zero or around zero.

<FIG> is an example diagram illustrating adjustment of a trim signal over a range of trim value settings according to embodiments herein. Graph <NUM> illustrates different settings of controlling current source <NUM> in <FIG> between range #<NUM> (switches S1 and S4 closed, switches S2 and S3 open) of corresponding settings <NUM> and <NUM> (midpoint) of current source <NUM> (digital-to-analog converter) producing IB2 as well as between range #<NUM> of corresponding settings <NUM> and <NUM> (endpoint) of corresponding current source <NUM> producing IB2.

In a manner as previously discussed, embodiments herein include controller <NUM> being set to different values within range #<NUM> and/or range #<NUM> to set the corresponding differential trim signal <NUM> (trim signal <NUM>-<NUM> and trim signal <NUM>-<NUM>) to the appropriate setting.

Thus, with respect to trim system <NUM>-<NUM> in <FIG>: as shown in <FIG>, for <NUM> ≤ IB2 < IB2_MAX/<NUM> (where IB2_MAX2 is unrelated to IB2_max in prior example) and switch SB2_Msb closed (i.e., switches S2 and S3 closed circuit, low resistance path) and switches SB2_Msb opened (i.e., switches S1 and S4 open circuit, high resistance), VDIFF ≥ <NUM>.

For <NUM> ≤ IB2 < IB2_MAX2 and SB2_Msb opened (i.e., switches S2 and S3 open circuit, high resistance), and S B2_Msb closed (i.e., switches S1 and S4 closed circuit, low resistance path), VDIFF ≥ <NUM>.

<FIG> is an example diagram illustrating example computer architecture operable to execute one or more methods according to embodiments herein. As previously discussed, any of the resources (such as controller <NUM>, any part of trim system <NUM>, monitor resource <NUM>, etc.) as discussed herein can be configured to include computer processor hardware and/or corresponding executable instructions to carry out the different operations as discussed herein.

As shown, computer system <NUM> of the present example includes an interconnect <NUM> that couples computer readable storage media <NUM> such as a non-transitory type of media (which can be any suitable type of hardware storage medium in which digital information can be stored and retrieved), a processor <NUM> (computer processor hardware), I/O interface <NUM>, and a communications interface <NUM>. I/O interface(s) <NUM> supports connectivity to trim system <NUM>.

Computer readable storage medium <NUM> can be any hardware storage device such as memory, optical storage, hard drive, floppy disk, etc. In one embodiment, the computer readable storage medium <NUM> stores instructions and/or data.

As shown, computer readable storage media <NUM> can be encoded with trim application <NUM>-<NUM> (e.g., including instructions) to carry out any of the operations as discussed herein.

During operation of one embodiment, processor <NUM> accesses computer readable storage media <NUM> via the use of interconnect <NUM> in order to launch, run, execute, interpret or otherwise perform the instructions in trim application <NUM>-<NUM> stored on computer readable storage medium <NUM>. Execution of the trim application <NUM>-<NUM> produces trim process <NUM>-<NUM> to carry out any of the operations and/or processes as discussed herein.

Those skilled in the art will understand that the computer system <NUM> can include other processes and/or software and hardware components, such as an operating system that controls allocation and use of hardware resources to execute trim application <NUM>-<NUM>.

In accordance with different embodiments, note that computer system may reside in any of various types of devices, including, but not limited to, a power supply, switched-capacitor converter, power converter, a mobile computer, a personal computer system, a wireless device, a wireless access point, a base station, phone device, desktop computer, laptop, notebook, netbook computer, mainframe computer system, handheld computer, workstation, network computer, application server, storage device, a consumer electronics device such as a camera, camcorder, set top box, mobile device, video game console, handheld video game device, a peripheral device such as a switch, modem, router, set-top box, content management device, handheld remote control device, any type of computing or electronic device, etc. The computer system <NUM> may reside at any location or can be included in any suitable resource in any network environment to implement functionality as discussed herein.

Functionality supported by one or more resources as described herein are discussed via flowchart in <FIG>. Note that the steps in the flowcharts below can be executed in any suitable order.

<FIG> is a flowchart <NUM> illustrating an example method according to embodiments herein. Note that there will be some overlap with respect to concepts as discussed above. In processing operation <NUM>, the driver resource <NUM> produces (output) signal <NUM>. In processing operation <NUM>, the differential voltage generator <NUM> derives a differential drive signal <NUM> from the (output) signal <NUM>. In processing operation <NUM>, the trim current generator <NUM> generates a differential trim signal <NUM> from the differential drive signal <NUM>.

As previously discussed, in one embodiment, the trim system <NUM> outputs the differential trim signal <NUM> to an electronic component <NUM> such as an amplifier to correct an operational parameter such as the input offset current.

Accordingly, embodiments herein include a trimming method, apparatus, system, etc., for producing ultra-low offset currents (trim currents). One embodiment of a proposed trimming circuit as described herein is based on a "degenerated transconductor" cell.

More specifically, as previously discussed, the input of the "degenerated transconductor" is current IB2, which comes from a digitally controlled current mirror. Current IB2 creates a differential voltage VDIFF across resistor R1. This differential voltage creates an unbalance in the differential pair formed by transistors P1 and P2. Assuming that the magnitude of the perturbation is small with respect to the magnitude of the quiescent point, this unbalance will create a differential current ITRIM (a. , IDIFF) that is directly proportional to IB2 and inversely proportional to K, the ratio of the source resistors R2 and R3 to resistor R1. The assumption is also that gmkR1 >> <NUM>, with gm the transconductance of the differential pair devices.

Depending on the value of IB, on the current mirror ratio, and on the parameter K, the LSB value of ITRIM can easily reach the nano-amperes range. This goal is achieved without using huge resistors or large current mirror ratios. Moreover, all the devices can perfectly work in the saturation region, therefore avoiding the weak-inversion region and all the problems associated to it.

The novel solution offers an additional degree of freedom for generating IDIFF = ITRIM = I1 - I2 not attainable in the prior art. Specifically, the resistor ratio K, which can be adjusted separately from the other circuit's parameters.

One application of the trimming method as described herein is to cancel (or reduce) the offset current of the circuit of interest (such as amplifiers) in order to obtain accuracies such as on the order of single digit nano-amperes, tens of nano-amperes, hundreds of nano-amperes, etc..

Claim 1:
An apparatus comprising:
an adjustable driver (<NUM>) configured to provide an output current (<NUM>) based on a control signal (<NUM>);
a differential voltage generator (<NUM>) configured to produce a differential drive signal (<NUM>-<NUM>, <NUM>-<NUM>) based on the output current (<NUM>) received from the adjustable driver (<NUM>); and
a trim current generator (<NUM>) configured to produce a trim signal (<NUM>-<NUM>, <NUM>-<NUM>) based on the differential drive signal (<NUM>-<NUM>, <NUM>-<NUM>) received from the differential voltage generator (<NUM>),
wherein the differential voltage generator (<NUM>) is a first resistor (R1) through which the output current of the adjustable driver passes to produce the differential drive signal (<NUM>-<NUM>, <NUM>-<NUM>),
wherein the differential drive signal (<NUM>-<NUM>, <NUM>-<NUM>) is a voltage signal including a first drive voltage (<NUM>-<NUM>) and a second drive voltage (<NUM>-<NUM>),
wherein the trim current generator comprises a first series circuit of a second resistor (R2) and a first transistor (P1) and a second series circuit of a third resistor (R3) and a second transistor (P2),
wherein the first drive voltage (<NUM>-<NUM>) drives a gate node of the first transistor (P1) and the second drive voltage (<NUM>-<NUM>) drives a gate node of the second transistor (P2),
wherein a resistance of the second resistor (R2) is K times greater than a resistance of the first resistor (R1);
wherein a magnitude of a resistance of the third resistor (R3) is K times greater than a resistance of the first resistor (R1); and
wherein K represents a ratio value.