Patent Description:
An embodiment of the present application relates to the field of semiconductors, in particular to a semiconductor structure.

In order to realize the integration and assembly of chips in a Z-axis direction, interconnection between the chips is usually realized through a Through-Silicon Vias, TSV, technology. Specifically, the TSV technology is to form through holes for connecting the upper side and the lower side of a wafer, and the through holes are filled with conductive materials to form an interconnection structure. The conductive materials include different types of metal materials.

However, in an actual application process, the arrangement of the interconnection structure will affect elements arranged on the surface of the silicon wafer and elements arranged in the dielectric layer on the silicon wafer.

The document <CIT> discloses a semiconductor device comprising a through-substrate via (TSV) extending through the substrate and through a dielectric layer, wherein the TSV is surrounded by a single annular capacitor.

An embodiment of the present application provides a semiconductor structure, which is beneficial to reduce the influence of the deformation stress generated by a conductive plug on functional elements.

The embodiment of the present application provides a semiconductor structure, which includes: a substrate and a dielectric layer arranged on the substrate; a conductive plug, a first portion of the conductive plug being arranged in the substrate, and a second portion of the conductive plug being arranged in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug.

The technical solution provided by the embodiment of the present application has the following advantages.

The capacitor array is used as a deformation isolation structure, and more interfaces may be provided in the capacitor array. Each interface includes a contact interface between an upper electrode and a lower electrode. When the deformation stress is transmitted in the capacitor array, the deformation stress needs to continuously pass through the interfaces or bypass the interfaces, so that relatively high transmission attenuation will be generated. In this way, it is beneficial to ensure that the deformation stress has a small impact on the functional elements arranged on a side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance.

One or more embodiments are exemplarily explained through the figures in accompanying drawings corresponding thereto, these exemplary explanations do not constitute a limitation to the embodiments, elements having the same reference numerals in the accompanying drawings are denoted as similar elements; and unless otherwise specifically declared, the figures in the accompanying drawings do not constitute a limitation of proportion.

With reference to <FIG> is a schematic cross-sectional diagram of a semiconductor structure in the related art, and <FIG> is a top view of a semiconductor structure shown in <FIG>. The semiconductor structure includes: a substrate <NUM> and a dielectric layer <NUM> arranged on the substrate <NUM>; and a conductive plug <NUM>, in which the conductive plug <NUM> is arranged in the substrate <NUM> and the dielectric layer <NUM>.

The conductive plug <NUM> usually contains a metal material, and the metal material is prone to expand and contract when subjected to a thermal stress. When a thermal expansion coefficient of the conductive plug <NUM> is different from a thermal expansion coefficient of the dielectric layer <NUM> and a thermal expansion coefficient of the substrate <NUM>, a stress concentration phenomenon may occur, which in turn causes the substrate <NUM> and the dielectric layer <NUM> to deform. The deformation of the substrate <NUM> and the dielectric layer <NUM> may affect the characteristics of the functional elements in the functional zone, and even cause structural damage to the semiconductor structure.

The functional zone is a workable zone of the functional elements, and includes a surface of the substrate <NUM> and an interior of the dielectric layer <NUM>. The functional elements on the surface of the substrate <NUM> are generally referred to as active areas.

It should be noted that in addition to the direct stress from the conductive plug <NUM>, the stress that causes the substrate <NUM> and the dielectric layer <NUM> to deform may also come from the secondary stress caused by the deformation of other adjacent film layers. For example, the compressive stress of the conductive plug <NUM> causes the substrate <NUM> to deform, and the deformed substrate <NUM> applies stress to the dielectric layer <NUM> due to the structural change thereof, which in turn causes the dielectric layer <NUM> to deform.

At present, only a grounded isolation ring structure <NUM> is provided to shield part of the electric field of the conductive plug <NUM>, so as to reduce the influence of the electric field of the conductive plug <NUM>, but there is no method to solve or counteract the deformation of the substrate <NUM> and the dielectric layer <NUM>. In order to prevent the deformation of the substrate <NUM> and the dielectric layer <NUM> from affecting the functional elements in the functional zone, the functional elements are usually arranged outside a Keep Out Zone, KOZ, that is, the functional elements are arranged away from the conductive plug <NUM>. However, such a solution will greatly compress the reserved space for the functional elements, which is not conducive to the integration of the chips or the functional elements.

According to a semiconductor structure provided in an embodiment of the present application, a capacitor array surrounding the conductive plug is provided, so as to reduce the magnitude of the deformation stress passing through the capacitor array, and to ensure that the deformation stress has a small impact on the functional zone arranged on a side of the capacitor array away from the conductive plug, thereby ensuring that the functional elements in the functional zone may work effectively and that the semiconductor structure has good performance.

In order to make the objectives, technical solutions and advantages of the embodiments of the present application more apparent, hereinafter, the respective embodiments of the present application will be described in detail in connection with the accompanying drawings. However, those ordinary skilled in the art may understand that, in the respective embodiments of the present application, numerous technical details are set forth in order to provide a reader with a better understanding of the present application. However, the technical solutions claimed in the present application can also be implemented without these technical details and various changes and modifications based on the respective embodiments below.

In the embodiment of the present application, with reference to <FIG> and <FIG>, the semiconductor structure includes: a substrate <NUM>; a dielectric layer <NUM> arranged on the substrate <NUM>; a conductive plug <NUM>, in which a first portion of the conductive plug <NUM> is arranged in the substrate <NUM>, and a second portion of the conductive plug <NUM> is arranged in the dielectric layer <NUM>; and a capacitor array <NUM>, in which the capacitor array <NUM> at least surrounds the second portion of the conductive plug <NUM>.

The capacitor array <NUM> is formed by a plurality of capacitor units 24a. In a direction parallel to a surface of the substrate <NUM> and away from the conductive plug <NUM>, the capacitor array <NUM> has a plurality of interfaces. The interfaces will hinder the transmission of the deformation stress, that is, attenuate the deformation stress, so as to ensure that the deformation stress transmitted to the functional zone <NUM> is relatively small, and ensure that the functional elements in the functional zone <NUM> have good performance.

In the embodiment of the present application, each capacitor unit 24a includes a double-sided capacitor unit. The capacitor array <NUM> includes multiple double-sided capacitor units 24a which are successively arranged. The interface in the capacitor array <NUM> mainly refers to a contact interface between a lower electrode 24b and an upper electrode 24c. In some embodiments of the present application, each capacitor unit includes a single-sided capacitor unit. The capacitor array may include multiple capacitor units spaced apart from each other, and the interfaces in the capacitor array also include the side wall surfaces of the capacitor units.

In the embodiment of the present application, the substrate <NUM> includes a KOZ <NUM> and a functional zone <NUM>. The functional zone <NUM> is arranged on a side of the KOZ <NUM> away from the conductive plug <NUM>. Each of the KOZ <NUM> and the functional zone <NUM> is provided with the capacitor array <NUM>, and the capacitor array <NUM> in the KOZ <NUM> surrounds the second portion of the conductive plug <NUM>. By setting the capacitor array <NUM> at the edge of the KOZ <NUM> as a transition, a difference between an element arrangement density in the KOZ <NUM> and an element arrangement density in the functional zone <NUM> is prevented from being too large, so as to ensure that the functional elements with a relatively large element arrangement density can be provided in the functional zone <NUM>, and to ensure that the functional elements in the functional zone <NUM> can work effectively.

It should be noted that in the structure shown in <FIG>, the fact that only the capacitor array <NUM> is provided in the functional zone <NUM> is taken as an example. In fact, any functional elements may be provided in the functional zone <NUM>. In addition, hereinafter, for the sake of simplicity of description, the capacitor array <NUM> in the KOZ <NUM> is referred to as a first capacitor array <NUM>, and the capacitor array <NUM> in the functional zone <NUM> is referred to as a second capacitor array <NUM>.

In the embodiment of the present application, the substrate <NUM> is provided with an active area <NUM> in the KOZ <NUM>, and the first capacitor array <NUM> is electrically connected to the active area <NUM> in the KOZ <NUM>. In this way, it is beneficial to ensure that the first capacitor array <NUM> may be actuated through the active area <NUM>, so that the first capacitor array <NUM> may be used as a backup capacitor and put into use during fuse repair.

In some embodiments of the present application, the KOZ <NUM> is also provided with a capacitor contact window 24d for connecting the active area <NUM> and the first capacitor array <NUM> with each other, and necessary bit lines (not shown), word lines (not shown), or other structures. That is, the electrical structure of the KOZ <NUM> may be exactly the same as the electrical structure of the functional zone <NUM>. The difference between the electrical structure of the KOZ <NUM> and the electrical structure of the functional zone <NUM> is only that the positions of the KOZ <NUM> and the functional zone <NUM> are different from each other, and the electrical structure of the KOZ <NUM> is not put into use before fuse repair.

In some embodiments of the present application, in the KOZ <NUM>, the substrate <NUM> is also provided with an isolation structure <NUM> for isolating two adjacent active areas <NUM> from one another. Since the first capacitor array <NUM> includes a plurality of capacitor units 24a, the first capacitor array <NUM> corresponds to a plurality of active areas <NUM> and a plurality of isolation structures <NUM>. The existence of the plurality of isolation structures <NUM> may increase the transmission attenuation of the deformation stress in the substrate <NUM>, so as to avoid the deformation stress from passing through the substrate <NUM> to cause a relatively large impact on the functional elements in the dielectric layer <NUM>.

In the embodiment of the present application, a pattern of the first capacitor array <NUM> is the same as a pattern of the second capacitor array <NUM>. In this way, the first capacitor array <NUM> and the second capacitor array <NUM> may be formed through the same manufacturing process, which is beneficial to reduce the difficulty of the manufacture of the semiconductor structure.

In the embodiment of the present application, when the capacitor array <NUM> is used to surround the conductive plug <NUM>, the capacitor array <NUM> at the edge of the structure, which is formed through the same manufacturing process, is selected as the capacitor array <NUM> surrounding the conductive plug <NUM>. Since the capacitor array <NUM> at the edge of the structure is easily affected by the edge effect of the structure during the formation, for example, among the multiple trenches formed by etching through a same mask, the top openings of the trenches at the edge of the structure are relatively small, the data storage performance of the capacitor array <NUM> at the edge of the structure may be relatively poor.

In the case where the data storage performance of the capacitor array <NUM> at the edge of the structure may be relatively poor, the capacitor array <NUM> is used as a transitional high-density functional element arranged in the KOZ <NUM>, which is beneficial to realize the function of the capacitor array <NUM> at the edge of the structure and avoid the capacitor array <NUM> at the edge of the structure from occupying the space in the functional zone <NUM>, so that more capacitor arrays <NUM> with good performance are provided in the functional zone <NUM> to improve the performance of the semiconductor structure.

In some embodiments of the present application, when a capacitor array is used to surround the conductive plug, the reserved space region for the conductive plug may be embedded in the entire region of the capacitor array. In this case, the capacitor array which is close to and surrounds a partial region of the reserved space region is easily affected by the conductive plug. The partial region of reserved space region may be defined as a KOZ, and the capacitor array in the partial region of reserved space region may be defined as a backup capacitor.

In the embodiment of the present application, in a direction from the KOZ <NUM> to the functional zone <NUM>, a first predetermined distance d1 is formed between the first capacitor array <NUM> and the second capacitor array <NUM>. The existence of the first predetermined distance d1 is beneficial to avoid the first capacitor array <NUM> affected by the conductive plug <NUM> from affecting the second capacitor array <NUM>, so as to ensure that the second capacitor array <NUM> has better performance.

The influence of the first capacitor array <NUM> on the second capacitor array <NUM> includes potential influence and structural influence.

For the potential influence: in the embodiment of the present application, in order to prevent the electric field of the conductive plug <NUM> from affecting the performance of the functional elements in the functional zone <NUM>, the first capacitor array <NUM> is grounded, or the first capacitor array <NUM> is grounded through the active area <NUM>, the capacitor contact window 24d, the word line or the bit line, so as to form an electrostatic shielding. Correspondingly, the grounded first capacitor array <NUM> is at a low potential, and at least a portion of the capacitor units 24a in the second capacitor array <NUM> for data storage stores charges, that is, at least the portion of the capacitor units 24a are at a high level. In order to avoid charges from being transferred and leaking due to the potential difference, the first predetermined distance d1 is used for isolation, which can effectively block the transfer path of the charges, thereby ensuring the accuracy and effectiveness of the data storage of the second capacitor array <NUM>.

The grounded first capacitor array <NUM> may be disconnected from a ground wire when it is subsequently put into use, so as to perform data storage.

For structural influence: since the upper electrode 24c of the current capacitor array <NUM> is usually a continuous film layer integrally formed, without an internal interface therein, the deformation stress can be transmitted through the upper electrode 24c with a relatively low transmission attenuation. In this way, continuous arrangement of the first capacitor array <NUM> and the second capacitor array <NUM> may cause the second capacitor array <NUM> to be more susceptible to the deformation stress. Electrodes of the capacitor array <NUM> are usually of a structure with a high height-to-width ratio, so that the electrodes are more sensitive to the deformation stress, and are prone to collapse when subjected to the deformation stress. Therefore, the first predetermined distance d1 is set, so that the upper electrodes 24c of different capacitor arrays <NUM> may be spaced apart from each other, which is beneficial to ensure that the deformation stress to which the second capacitor array <NUM> is subjected is relatively small, and that the second capacitor array <NUM> has high structural stability.

In the embodiment of the present application, the first predetermined distance d1 is comprised between <NUM> and <NUM>, for example, <NUM>, <NUM>, or <NUM>. If the first predetermined distance d1 is too small, the first capacitor array <NUM> will affect the data storage accuracy and structural stability of the second capacitor array <NUM>. If the first predetermined distance d1 is too large, the reserved space in the functional zone <NUM> may be compressed.

In other embodiments, with reference to <FIG> and <FIG>, the capacitor array <NUM> is a structure continuously integrally formed, and the first capacitor array <NUM> and the second capacitor array <NUM> are continuously arranged. In this way, the first capacitor array <NUM> and the second capacitor array <NUM> can be continuously formed by using the same mask, so as to reduce the difficulty of manufacture of the semiconductor structure.

In the embodiment of the present application, the second capacitor array <NUM> surrounds the second portion of the conductive plug <NUM>, and the surrounding configuration of the first capacitor array <NUM> is different from the surrounding configuration of the second capacitor array <NUM>.

In some embodiments of the present application, both the first capacitor array <NUM> and the second capacitor array <NUM> completely surround the conductive plug <NUM>, but the surrounding configuration of the first capacitor array and the surrounding configuration of the second capacitor array are different from each other. In this way, the distances between the first capacitor array <NUM> and the second capacitor array <NUM> may be different in different directions away from the conductive plug <NUM>. Further, the portion of the second capacitor array <NUM>, which is more sensitive to the deformation stress, is arranged farther from the first capacitor array <NUM>, so as to ensure that any portion of the second capacitor array <NUM> has high structural stability.

In some embodiments of the present application, the first capacitor array <NUM> may be in a circular shape, and the second capacitor array <NUM> may be in an elliptical shape. A part corresponding to an end point of the long axis of the ellipse is the portion of the second capacitor array <NUM> which is more sensitive to the deformation stress. Alternatively, the first capacitor array <NUM> is in a square shape, and the second capacitor array <NUM> is in a circular shape. Alternatively, the first capacitor array <NUM> is in a circular shape, and the second capacitor array <NUM> is in a polygonal shape, such as in a rhombus shape.

In some embodiments of the present application, the first capacitor array <NUM> does not completely surround the conductive plug <NUM>, while the second capacitor array <NUM> completely surrounds the conductive plug <NUM>. In this way, the first capacitor array <NUM> may be arranged in the partial region, so that the sensitive portion in the second capacitor array <NUM> can be protected, thereby ensuring that the whole second capacitor array <NUM> has high structural stability.

In some embodiments of the present application, the first capacitor array <NUM> may be in an arc shape, and the second capacitor array <NUM> may be in a circular shape. The first capacitor array <NUM> may be in a linear shape, and the second capacitor array <NUM> may be in a square shape.

In the embodiment of the present application, the semiconductor structure further includes an isolation ring structure <NUM>. The isolation ring structure <NUM> at least surrounds the second portion of the conductive plug <NUM>. The isolation ring structure <NUM> is arranged between the conductive plug <NUM> and the first capacitor array <NUM>. An arrangement density of the first capacitor array <NUM> is greater than an arrangement density of the isolation ring structure <NUM>. In this way, the functional elements with a relatively large arrangement density may be provided in the functional zone <NUM>.

In some embodiments of the present application, the isolation ring structure <NUM> may be grounded. The first capacitor array <NUM> may not be grounded. The isolation ring structure <NUM> plays a role of electrostatic shielding, and the first capacitor array <NUM> plays a role of blocking the deformation stress. In this way, when the first capacitor array <NUM> is subsequently put into use, there is no need to disconnect the ground wire of the first capacitor array <NUM>, which is beneficial to improve the applicability of the semiconductor structure.

The isolation ring structure <NUM> may include a contact portion extending in the same direction as the conductive plug <NUM>, and a metal portion arranged at the top of the contact portion.

In some embodiments of the present application, with reference to <FIG>, the capacitor array <NUM> includes a plurality of discontinuous capacitor sub-arrays. The isolation ring structure <NUM> includes a plurality of discontinuous isolation sub-rings. Each isolation sub-ring is arranged between two adjacent capacitor sub-arrays. The isolation ring structure <NUM> and the capacitor array <NUM> form a pattern surrounding the conductive plug <NUM>. The pattern may be in any shape, such as a square shape, a circular shape, an elliptical shape, or a polygon shape.

The isolation ring structure <NUM> is electrically isolated from the capacitor array <NUM>. The isolation ring structure <NUM> is grounded to play a role of electrostatic shielding, and the capacitor array <NUM> is not grounded to play a role of blocking the deformation stress.

In some embodiments of the present application, with reference to <FIG>, the capacitor array <NUM> including a plurality of capacitor sub-arrays constitutes a first pattern surrounding the conductive plug <NUM>, and the isolation ring structure <NUM> including a plurality of isolation sub-rings constitutes a second pattern surrounding the conductive plug <NUM>. The first pattern and the second pattern have the same shape but are at different positions. In a direction from the conductive plug <NUM> to the capacitor array <NUM>, an orthographic projection of the second pattern may be complementary to the first pattern, so as to constitute a complete enclosed pattern.

In some embodiments of the present application, the shape of the first pattern and the shape of the second pattern may also be different from each other, and the orthographic projection of the second pattern may also partially overlap with the first pattern, or there may be a gap between the orthographic projection of the second pattern and the first pattern.

In the embodiment of the present application, in a direction from the conductive plug <NUM> to the first capacitor array <NUM>, a second predetermined distance d2 is formed between the conductive plug <NUM> and the first capacitor array <NUM>. The second predetermined distance d2 is comprised between <NUM> to <NUM>, for example, <NUM>, <NUM> or <NUM>. If the second predetermined distance d2 is too small, the first capacitor array <NUM> is easily damaged by the deformation stress of the conductive plug <NUM>, so that the first capacitor array <NUM> cannot achieve the effect of deformation isolation, and the first capacitor array <NUM> cannot be used as a backup capacitor. If the second predetermined distance d2 is too large, the reserved space in the functional zone <NUM> may be compressed.

In the embodiment of the present application, in a direction perpendicular to a surface of the substrate <NUM>, a top surface of the second portion of the conductive plug <NUM> is lower than or flush with a top surface of the first capacitor array <NUM>. In this way, it is beneficial that the deformation stress generated by the conductive plug <NUM> to be applied to the dielectric layer <NUM> must pass through the interfaces in the first capacitor array <NUM> or bypass the first capacitor array <NUM>, instead of directly affecting the active area <NUM> on the surface of the substrate <NUM> or the functional element in the dielectric layer <NUM>. That is, the deformation stress transmitted to the functional elements or the active area <NUM> is reduced, thereby ensuring that each of the functional elements or the active area <NUM> has good performance.

In the embodiment of the present application, the capacitor array is used as a deformation isolation structure, and more interfaces may be provided in the capacitor array. Each interface includes a contact interface between the upper electrode and the lower electrode. When the deformation stress is transmitted in the capacitor array, the deformation stress needs to continuously pass through the interfaces or bypass the interfaces, so that relatively high transmission attenuation will be generated. In this way, it is beneficial to ensure that the deformation stress has a small impact on an element arranged on a side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance.

Those of ordinary skill in the art may understand that the above embodiments are specific embodiments to implement the present application. The protection scope of the present application is defined by the appended claims.

Claim 1:
A semiconductor structure, comprising:
a substrate (<NUM>) and a dielectric layer (<NUM>) arranged on the substrate (<NUM>);
a conductive plug (<NUM>, <NUM>, <NUM>), a first portion of the conductive plug (<NUM>, <NUM>, <NUM>) being arranged in the substrate (<NUM>), and a second portion of the conductive plug (<NUM>, <NUM>, <NUM>) being arranged in the dielectric layer (<NUM>); and
a capacitor array (<NUM>, <NUM>, <NUM>, <NUM>), characterized in that
the capacitor array (<NUM>, <NUM>, <NUM>, <NUM>) at least surrounds the second portion of the conductive plug (<NUM>, <NUM>, <NUM>).