Patent Description:
A hybrid charge pump and control circuit for use in a memory device is disclosed.

Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.

One prior art non-volatile memory cell <NUM> is shown in <FIG>. The split gate SuperFlash (SF) memory cell <NUM> comprises a semiconductor substrate <NUM> of a first conductivity type, such as P type. The substrate <NUM> has a surface on which there is formed a first region <NUM> (also known as the source line SL) of a second conductivity type, such as N type. A second region <NUM> (also known as the drain line) also of a second conductivity type, such as N type, is formed on the surface of the substrate <NUM>. Between the first region <NUM> and the second region <NUM> is a channel region <NUM>. A bit line (BL) <NUM> is connected to the second region <NUM>. A word line (WL) <NUM> (also referred to as the select gate) is positioned above a first portion of the channel region <NUM> and is insulated therefrom. The word line <NUM> has little or no overlap with the second region <NUM>. A floating gate (FG) <NUM> is over another portion of the channel region <NUM>. The floating gate <NUM> is insulated therefrom, and is adjacent to the word line <NUM>. The floating gate <NUM> is also adjacent to the first region <NUM>. A coupling gate (CG) <NUM> (also known as control gate) is over the floating gate <NUM> and is insulated therefrom. An erase gate (EG) <NUM> is over the first region <NUM> and is adjacent to the floating gate <NUM> and the coupling gate <NUM> and is insulated therefrom. The erase gate <NUM> is also insulated from the first region <NUM>.

One exemplary operation for erase and program of prior art non-volatile memory cell <NUM> is as follows. The cell <NUM> is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate EG <NUM> with other terminals equal to zero volt. Electrons tunnel from the floating gate FG <NUM> into the erase gate EG <NUM> causing the floating gate FG <NUM> to be positively charged, turning on the cell <NUM> in a read condition. The resulting cell erased state is known as '<NUM>' state. Another embodiment for erase is by a applying a positive voltage Vegp on the erase gate EG <NUM>, a negative voltage Vcgn on the coupling gate CG <NUM>, and others terminal equal to zero volts. The negative voltage Vcgn couples negatively the floating gate FG <NUM>, hence less positive voltage Vcgp is required for erasing. Electrons tunnel from the floating gate FG <NUM> into the erase gate EG <NUM> causing the floating gate FG <NUM> to be positively charged, turning on the cell <NUM> in a read condition (cell state '<NUM>'). Alternately the wordline WL <NUM> (Vwle) and the source line SL <NUM> (Vsle) can be negative to further reduce the positive voltage on the erase gate FG <NUM> needed for erase. The magnitude of negative voltage Vwle and Vsle in this case is small enough not to forward the pin junction. The cell <NUM> is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate CG <NUM>, a high voltage on the source line SL <NUM>, a medium voltage on the erase gate EG <NUM>, and a programming current on the bit line BL <NUM>. A portion of electrons flowing across the gap between the word line WL <NUM> and the floating gate FG <NUM> acquire enough energy to inject into the floating gate FG <NUM> causing the floating gate FG <NUM> to be negatively charged, turning off the cell <NUM> in read condition. The resulting cell programmed state is known as '<NUM>' state.

The cell <NUM> can be inhibited in programming (if, for instance, another cell in its row is to be programmed but cell <NUM> is to not be programmed) by applying an inhibit voltage on the bit line BL <NUM>. The cell <NUM> is more particularly described in <CIT>, whose disclosure is incorporated herein by reference in its entirety.

Exemplary operating voltages for the prior art design of <FIG> is shown below in Table <NUM>:.

Typical values for the values listed in Table <NUM> are shown in Table <NUM>:.

<FIG> depicts a typical prior art architecture for a two-dimensional prior art flash memory system. Die <NUM> comprises: memory array <NUM> and memory array <NUM> for storing data, the memory array optionally utilizing memory cell <NUM> as in <FIG>; pad <NUM> and pad <NUM> for enabling electrical communication between the other components of die <NUM> and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip; high voltage circuit <NUM> used to provide positive and negative voltage supplies for the system; control logic <NUM> for providing various control functions, such as redundancy and built-in self-testing; analog logic <NUM>; sensing circuits <NUM> and <NUM> used to read data from memory array <NUM> and memory array <NUM>, respectively; row decoder circuit <NUM> and row decoder circuit <NUM> used to access the row in memory array <NUM> and memory array <NUM>, respectively, to be read from or written to; column decoder <NUM> and column decoder <NUM> used to access the column in memory array <NUM> and memory array <NUM>, respectively, to be read from or written to; charge pump circuit <NUM> and charge pump circuit <NUM>, used to provide increased voltages for program and erase operations for memory array <NUM> and memory array <NUM>, respectively; high voltage driver circuit <NUM> shared by memory array <NUM> and memory array <NUM> for read and write (erase/program) operations; high voltage driver circuit <NUM> used by memory array <NUM> during read and write operations and high voltage driver circuit <NUM> used by memory array <NUM> during read and write (erase/program) operations; and bitline inhibit voltage circuit <NUM> and bitline inhibit voltage circuit <NUM> used to un-select bitlines that are not intended to be programmed during a write operation for memory array <NUM> and memory array <NUM>, respectively. These functional blocks are understood by those of ordinary skill in the art, and the block layout shown in <FIG> is known in the prior art.

As can be seen from the foregoing, charge pumps play an important role in the operation of flash memory devices. High voltages are required for the program and erase functions.

<FIG> depicts prior art charge pumps. During a program operation, SL pump <NUM> is used to generate the Vslp and Vegp voltages (which are typically around 4V to 5V), and CG-EG pump <NUM> is used to generate the Vcgp voltage (which is typically around 9V to 10V). During an erase operation, SL pump <NUM> is not used, and CG-EG pump is used to generate the Vege voltage (which is typically around <NUM> to <NUM>. These voltages are relatively high voltages that consume significant levels of power.

What is needed are improved charge pumps that can generate voltages for the program and erase operations in flash memory devices that are lower voltages than those used in prior art charge pumps.

<CIT> discloses that an output voltage of a negative voltage generator contains a ripple because of a ripple occurring in a voltage produced by a charge pump circuit in the negative voltage generator. When the negative voltage is supplied to an FET amplifier, there arises a possibility that an unwanted spurious component occurs in an output of the FET amplifier. Since each of pair of circuits, that generate a negative voltage, are made mutually complementary, two charge pump circuits are used to cancel ripples. A ripple appearing in an output voltage can therefore be suppressed, and a negative voltage can eventually be supplied more stably. When the negative voltage generator is connected to, for example, an FET amplifier in order to supply a gate bias voltage to each FET in the FET amplifier, an unwanted spurious component that may be contained in an output of the FET amplifier can be removed.

<CIT> disclses that an exemplary negative voltage generating circuit includes a voltage input, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first capacitor, a second capacitor, a switch controller, and a voltage output. The voltage input is connected to ground via the first switch transistor, the first capacitor, and a source electrode and the second switch transistor. The first switch transistor is connected to the second switch transistor via the third switch transistor, the second capacitor, and the fourth switch transistor. The third switch transistor is connected to ground. The fourth switch transistor is connected to the voltage output. The first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are connected to the switch controller.

<FIG> depicts improved charge pump examples. During a program operation, Cpump1 <NUM> generates Vslp and Vegp (which typically are around <NUM>- 5V as in the prior art), and CG-EG pump <NUM> generates Vcgp (which typically is around <NUM>-5V as in the prior art). However, during an erase operation, Cpump1 <NUM> generates Vcge (which is around -8V), and CG-EG pump <NUM> generates Vege (which is around 8V). Thus, during an erase operation, around 8V will be applied to erase gate <NUM> and around -8V will be applied to control gate <NUM>. Alternatively a negative voltage can be applied (e. g, -04v) on the wordline <NUM> (vwle) and source line <NUM> (Vsle) respectively with the negative voltage derived from the Cpump1 <NUM>.

<FIG> depicts charge pump circuit <NUM>. Charge pump circuit <NUM> comprises switch <NUM>, switch <NUM>, voltage source phase driver <NUM>, voltage source phase driver <NUM>, and three charging stages (each comprising a diode and capacitor, the pairing of which depending on which switch is turned on) comprising diode <NUM>, diode <NUM>, diode <NUM>, diode <NUM>, capacitor <NUM>, capacitor <NUM>, and capacitor <NUM>. When switch <NUM> is turned on and switch <NUM> is turned off, positive charging will occur, and Voutp <NUM> will contain a positive voltage (such as 8V), in which instance charge pump circuit <NUM> can serve as CG-EG pump <NUM> to generate Vege. When switch <NUM> is turned off and switch <NUM> is turned on, negative charging will occur, and Voutn <NUM> will contain a negative voltage (such as -8V), in which instance charge pump circuit <NUM> can serve as Cpump1 <NUM> to generate Vcge. Thus, unlike in the prior art system, the highest voltage generated is 8V instead of <NUM>. This can save on power usage and also can increase the reliability of the flash memory product. Diode <NUM>,<NUM>,<NUM>,<NUM> can be made by enhancement NMOS and PMOS transistors or by PIN junction diode. Capacitor <NUM>,<NUM>,<NUM> can be made by enhancement NMOS and PMOS transistors or by MOM (metal-oxide-metal) capacitor or combination thereof. The switch <NUM> is implemented as an enhancement PMOS. Alternative example for switch <NUM> is NMOS transistor, in this case its bulk p-substrate terminal needs to be isolated from the negative output Voutn <NUM>. The switch <NUM> is implemented as an enhancement NMOS. Alternative embodiment for switch <NUM> is PMOS transistor, in this case its bulk Nwell terminal needs to be isolated from the positive output Voutp <NUM>. The phase driver <NUM> and <NUM> are generated by a phase driver circuit (not shown) and they are typically non-overlapping clocking phases at typically <NUM>-<NUM>.

Another example is depicted in <FIG>. During a program operation, Cpump1 <NUM> generates Vslp and Vegp (which typically are around 5V as in the prior art), and CG-EG pump <NUM> generates Vcgp (which typically is around 5V as in the prior art). However, during an erase operation, Cpump1+Mstg <NUM> is reconfigured to generate Vcge (which is around-8V), and CG-EG pump+N stg <NUM> is reconfigured to generate Vege (which is around 8V). The reconfiguration is done by splitting the CG_EG pump <NUM> into N stage pump and M stage pump. Then by combining M stage pump of the CG_EG pump <NUM> into the Cpump1 <NUM> to make a new pump <NUM>. The N stage is left with the original CG+EG pump <NUM> to make a new pump <NUM> The benefit of this system is that a hybrid charge pump can be used to generate the high Vege voltage but also to generate the much smaller Vcgp and Vcgn voltages.

<FIG> depicts the hybrid reconfigurable charge pump <NUM>. Charge pump <NUM> contains two charge pump components, each of which is its own charge pump. Charge pump component <NUM> comprises N charging stages (here, N=<NUM>, but N can be any positive integer), and charge pump component <NUM> comprises M charging stages (here, M=<NUM>, but M can be any positive integer). Charge pump component <NUM> and charge pump component <NUM> are coupled by switch <NUM>. When switch <NUM> is on, charge pump component <NUM> and charge pump component <NUM> are coupled together as one charge pump of N+M charging stages. When switch <NUM> is off, charge pump component <NUM> and charge pump component <NUM> are not coupled together and operate as separate charge pumps. Thus the chargepump <NUM> can be configured to be a pump with N+M stages or two separate pump, a N stage pump and a M stage pump. The charge pump <NUM> is for positive operation (pumping to higher positive voltage). Alternative example is for negative operation with similar reconfigurability (as shown in <FIG>). Different combination negative/positive segment pump for different segment pumps is done such as N stage pump <NUM> is negative and M stage pump <NUM> is positive by reconfiguring them.

Charge pump component <NUM> comprises voltage source phase driver <NUM>, voltage source phase driver <NUM>, diode <NUM>, diode <NUM>, diode <NUM>, diode <NUM>, capacitor <NUM>, capacitor <NUM>, capacitor <NUM>, and generates output <NUM>. Diode <NUM>,<NUM>,<NUM>,<NUM> can be made by enhancement NMOS and PMOS transistors or by PIN junction diode. Capacitor <NUM>,<NUM>,<NUM> can be made by enhancement NMOS and PMOS transistors or by MOM (metal-oxide-metal) capacitor or combination thereof. The phase driver <NUM> and <NUM> are generated by a phase driver circuit (not shown) and they are typically non-overlapping clocking phases at typically <NUM>-<NUM>.

<FIG> depicts hybrid charge pump control circuit <NUM>. Charge pump control circuit takes a charge pump output, steps it down (or up, for negative voltages), compares the result to reference voltage, and then generates an enable signal that will continue the charge pump operation when high and will discontinue the charge pump operation when low.

When the voltage of interest is positive, such as VPOS <NUM>, switches <NUM> are turned on, and switches <NUM> are turned off. VPOS <NUM> is supplied to a sequence of transistors <NUM>, whereby VPOS <NUM> is diminished by a threshold voltage through each transistor. The result is compared to a reference voltage by comparator <NUM>. If the reference voltage is greater than the stepped-down VPOS voltage, then enable signal <NUM> is asserted. Enable signal <NUM> can be sent to a charge pump oscillator (not shown which feeds into a phase driver circuit to generate phase driver clocks such as signal <NUM> and <NUM> in <FIG>) which will keep the charge pump operating. If the reference voltage is lower than the stepped-down VPOS voltage, then enable signal <NUM> is de-asserted, and the charge pump will stop operating.

When the voltage of interest is negative, such as VNEG <NUM>, switches <NUM> are turned on, and switches <NUM> are turned off. VNEG <NUM> is supplied to a sequence of transistors <NUM>, whereby VNEG is increased by a threshold voltage through each transistor. The result is compared to a reference voltage by comparator <NUM>. If the reference voltage is lower than the stepped-up VNEG voltage, then enable signal <NUM> is asserted. Enable signal <NUM> can be sent to a charge pump oscillator (not shown) which will keep the charge pump operating. If the reference voltage is higher than the stepped-up VNEG voltage, then enable signal <NUM> is de-asserted, and the charge pump will stop operating.

<FIG> depicts an inverter circuit <NUM> that inverts the output of a charge pump. For example, if VHVP-IN <NUM> is +10V, VHVN-OUT will be -10V. Inverter circuit <NUM> comprises PMOS transistor <NUM>, NMOS transistor <NUM>, capacitor <NUM>, PMOS transistor <NUM>, PMOS transistor <NUM>, PMOS transistor <NUM>, PMOS transistor <NUM>, and output capacitor <NUM>. These components are coupled together as shown in <FIG>. The operation is as following. First PMOS transistor <NUM> is enabled to charge up terminal <NUM> of the capacitor <NUM> to the VHVP-IN <NUM> level. The node VHVN <NUM> will be clamped at a Vt (threshold voltage of the PMOS transistor <NUM>,<NUM>) above ground. Next the PMOS transistor <NUM> is turned off and the NMOS transistor <NUM> is turned on, which in turns pull the terminal <NUM> to ground, by capacitor coupling action, the node <NUM> will be pulled to negative, then in turn it pulls output node <NUM> to negative by the PMOS transistors <NUM> and <NUM>. Then the sequence repeats until the output node <NUM> is substantially equal to VHV-P IN <NUM>.

<FIG> depicts another inverter circuit <NUM> that inverts the output of a charge pump. For example, if VHVP-IN <NUM> is +10V, VHVN-OUT <NUM> will be -10V Inverter circuit <NUM> comprises PMOS transistor <NUM>, PMOS transistor <NUM>, PMOS transistor <NUM>, capacitor <NUM>, NMOS transistor <NUM>, NMOS transistor <NUM>, NMOS transistor <NUM>, and switch <NUM>. These components are coupled together as shown in <FIG>. The operation is similar to that of <FIG>. The NMOS transistors <NUM>,<NUM> together with the switch <NUM> now controls node <NUM> to ground at the charging phase.

Claim 1:
An inverter circuit (<NUM>, <NUM>), comprising:
a first PMOS transistor (<NUM>, <NUM>) comprising a first terminal connected to an input (VHVP-IN) of the inverter circuit, a second terminal, and a gate;
a first capacitor (<NUM>, <NUM>) comprising a first terminal coupled to the second terminal of the first PMOS transistor and a second terminal;
a first NMOS transistor (<NUM>, <NUM>) comprising a first terminal connected to the first terminal of the first capacitor, a second terminal connected to ground, and a gate;
a second MOS transistor (<NUM>, <NUM>) comprising a first terminal coupled to the second terminal of the first capacitor, a second terminal, and a gate;
a third MOS transistor (<NUM>, <NUM>) comprising a first terminal coupled to the second terminal of the second MOS transistor, a second terminal coupled to ground, and a gate coupled to the gate of the second MOS transistor;
a fourth PMOS transistor (<NUM>, <NUM>) comprising a first terminal, a second terminal coupled to the second terminal of the first capacitor, and a gate coupled to the second terminal of the first capacitor; and
a fifth PMOS transistor (<NUM>, <NUM>) comprising a first terminal coupled to an output (VHVN-OUT) of the inverter circuit, a second terminal coupled to the first terminal of the fourth PMOS transistor, and a gate coupled to the second terminal of the first capacitor;
wherein the inverter circuit inverts a voltage on the input to generate a voltage on the output.