Patent Description:
Integrated circuit devices traverse a broad range of electronic devices. One particular type include memory devices, oftentimes referred to simply as memory. Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.

Integrated circuit devices generally include capacitors in a variety of uses. For example, decoupling capacitors might be connected between power busses and a ground. In addition, voltage generation devices might utilize coupling capacitors and storage capacitors in the generation and regulation of an output voltage level, either positive or negative. Where such capacitors are damaged during fabrication of an integrated circuit device, that integrated circuit device might become unusable.

Document <CIT> forms part of the relevant background art and discloses semiconductor devices useful for conversion between analog and digital signals and fabrication methods integrating both bipolar and field effect devices.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term "semiconductor" used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term "conductive" as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term "connecting" as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

<FIG> is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device) <NUM>, in communication with a second apparatus, in the form of a processor <NUM>, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor <NUM>, e.g., a controller external to the memory device <NUM>, may be a memory controller or other external host device.

Memory device <NUM> includes an array of memory cells <NUM> logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown in <FIG>) of at least a portion of array of memory cells <NUM> are capable of being programmed to one of at least two target data states.

A row decode circuitry <NUM> and a column decode circuitry <NUM> are provided to decode address signals. Address signals are received and decoded to access the array of memory cells <NUM>. Memory device <NUM> also includes input/output (I/O) control circuitry <NUM> to manage input of commands, addresses and data to the memory device <NUM> as well as output of data and status information from the memory device <NUM>. An address register <NUM> is in communication with I/O control circuitry <NUM> and row decode circuitry <NUM> and column decode circuitry <NUM> to latch the address signals prior to decoding. A command register <NUM> is in communication with I/O control circuitry <NUM> and control logic <NUM> to latch incoming commands.

A controller (e.g., the control logic <NUM> internal to the memory device <NUM>) controls access to the array of memory cells <NUM> in response to the commands and generates status information for the external processor <NUM>, i.e., control logic <NUM> is configured to perform access operations (e.g., sensing operations [which may include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells <NUM>, and might be configured to perform methods in accordance with embodiments. The control logic <NUM> is in communication with row decode circuitry <NUM> and column decode circuitry <NUM> to control the row decode circuitry <NUM> and column decode circuitry <NUM> in response to the addresses.

Control logic <NUM> is also in communication with a cache register <NUM>. Cache register <NUM> latches data, either incoming or outgoing, as directed by control logic <NUM> to temporarily store data while the array of memory cells <NUM> is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data may be passed from the cache register <NUM> to the data register <NUM> for transfer to the array of memory cells <NUM>; then new data may be latched in the cache register <NUM> from the I/O control circuitry <NUM>. During a read operation, data may be passed from the cache register <NUM> to the I/O control circuitry <NUM> for output to the external processor <NUM>; then new data may be passed from the data register <NUM> to the cache register <NUM>. The cache register <NUM> and/or the data register <NUM> may form (e.g., may form a portion of) a page buffer of the memory device <NUM>. A page buffer may further include sensing devices (not shown in <FIG>) to sense a data state of a memory cell of the array of memory cells <NUM>, e.g., by sensing a state of a data line connected to that memory cell. A status register <NUM> may be in communication with I/O control circuitry <NUM> and control logic <NUM> to latch the status information for output to the processor <NUM>.

Memory device <NUM> receives control signals at control logic <NUM> from processor <NUM> over a control link <NUM>. The control signals might include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP#. Additional or alternative control signals (not shown) may be further received over control link <NUM> depending upon the nature of the memory device <NUM>. Memory device <NUM> receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor <NUM> over a multiplexed input/output (I/O) bus <NUM> and outputs data to processor <NUM> over I/O bus <NUM>.

For example, the commands may be received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and may then be written into command register <NUM>. The addresses may be received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and may then be written into address register <NUM>. The data may be received over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device at I/O control circuitry <NUM> and then may be written into cache register <NUM>. The data may be subsequently written into data register <NUM> for programming the array of memory cells <NUM>. For another embodiment, cache register <NUM> may be omitted, and the data may be written directly into data register <NUM>. Data may also be output over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device. Although reference may be made to I/O pins, they may include any conductive node providing for electrical connection to the memory device <NUM> by an external device (e.g., processor <NUM>), such as conductive pads or conductive bumps as are commonly used.

Memory device <NUM> and/or processor <NUM> may receive power from a power supply <NUM>. Power supply <NUM> may represent any combination of circuitry for providing power to memory device <NUM> and/or processor <NUM>. For example, power supply <NUM> might include a stand-alone power supply (e.g., a battery), a line-connected power supply (e.g., a switched-mode power supply common in desktop computers and servers or an AC adapter common for portable electronic devices), or a combination of the two. Power is typically received from the power supply <NUM> using two or more voltage supply nodes <NUM>, such as a supply voltage node (e.g., Vcc or Vccq) and a reference voltage node (e.g., Vss or Vssq, such as ground or 0V). It is not uncommon for a power supply <NUM> to provide more than two voltage supply nodes <NUM>. For simplicity, distribution of power from the voltage supply nodes <NUM> to components within the memory device <NUM> is not depicted.

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device <NUM> of <FIG> has been simplified. It should be recognized that the functionality of the various block components described with reference to <FIG> may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of <FIG>. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of <FIG>.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) may be used in the various embodiments.

<FIG> is a schematic of a portion of an array of memory cells 200A, such as a NAND memory array, as could be used in a memory of the type described with reference to <FIG>, e.g., as a portion of array of memory cells <NUM>. Memory array 200A includes access lines, such as word lines <NUM><NUM> to <NUM>N, and data lines, such as bit lines <NUM><NUM> to <NUM>M. The word lines <NUM> may be connected to global access lines (e.g., global word lines), not shown in <FIG>, in a many-to-one relationship. For some embodiments, memory array 200A may be formed over a semiconductor that, for example, may be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array 200A might be arranged in rows (each corresponding to a word line <NUM>) and columns (each corresponding to a bit line <NUM>). Each column may include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings <NUM><NUM> to <NUM>M. Each NAND string <NUM> might be connected (e.g., selectively connected) to a common source (SRC) <NUM> and might include memory cells <NUM><NUM> to <NUM>N. The memory cells <NUM> may represent non-volatile memory cells for storage of data. The memory cells <NUM> of each NAND string <NUM> might be connected in series between a select gate <NUM> (e.g., a field-effect transistor), such as one of the select gates <NUM><NUM> to <NUM>M (e.g., that may be source select transistors, commonly referred to as select gate source), and a select gate <NUM> (e.g., a field-effect transistor), such as one of the select gates <NUM><NUM> to <NUM>M (e.g., that may be drain select transistors, commonly referred to as select gate drain). Select gates <NUM><NUM> to <NUM>M might be commonly connected to a select line <NUM>, such as a source select line (SGS), and select gates <NUM><NUM> to <NUM>M might be commonly connected to a select line <NUM>, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates <NUM> and <NUM> may utilize a structure similar to (e.g., the same as) the memory cells <NUM>. The select gates <NUM> and <NUM> might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

A source of each select gate <NUM> might be connected to common source <NUM>. The drain of each select gate <NUM> might be connected to a memory cell <NUM><NUM> of the corresponding NAND string <NUM>. For example, the drain of select gate <NUM><NUM> might be connected to memory cell <NUM><NUM> of the corresponding NAND string <NUM><NUM>. Therefore, each select gate <NUM> might be configured to selectively connect a corresponding NAND string <NUM> to common source <NUM>. A control gate of each select gate <NUM> might be connected to select line <NUM>.

The drain of each select gate <NUM> might be connected to the bit line <NUM> for the corresponding NAND string <NUM>. For example, the drain of select gate <NUM><NUM> might be connected to the bit line <NUM><NUM> for the corresponding NAND string <NUM><NUM>. The source of each select gate <NUM> might be connected to a memory cell <NUM>N of the corresponding NAND string <NUM>. For example, the source of select gate <NUM><NUM> might be connected to memory cell <NUM>N of the corresponding NAND string <NUM><NUM>. Therefore, each select gate <NUM> might be configured to selectively connect a corresponding NAND string <NUM> to the corresponding bit line <NUM>. A control gate of each select gate <NUM> might be connected to select line <NUM>.

The memory array in <FIG> might be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source <NUM>, NAND strings <NUM> and bit lines <NUM> extend in substantially parallel planes. Alternatively, the memory array in <FIG> might be a three-dimensional memory array, e.g., where NAND strings <NUM> may extend substantially perpendicular to a plane containing the common source <NUM> and to a plane containing the bit lines <NUM> that may be substantially parallel to the plane containing the common source <NUM>.

Typical construction of memory cells <NUM> includes a data-storage structure <NUM> (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate <NUM>, as shown in <FIG>. The data-storage structure <NUM> may include both conductive and dielectric structures while the control gate <NUM> is generally formed of one or more conductive materials. In some cases, memory cells <NUM> may further have a defined source/drain (e.g., source) <NUM> and a defined source/drain (e.g., drain) <NUM>. Memory cells <NUM> have their control gates <NUM> connected to (and in some cases form) a word line <NUM>.

A column of the memory cells <NUM> may be a NAND string <NUM> or a plurality of NAND strings <NUM> selectively connected to a given bit line <NUM>. A row of the memory cells <NUM> may be memory cells <NUM> commonly connected to a given word line <NUM>. A row of memory cells <NUM> can, but need not, include all memory cells <NUM> commonly connected to a given word line <NUM>. Rows of memory cells <NUM> may often be divided into one or more groups of physical pages of memory cells <NUM>, and physical pages of memory cells <NUM> often include every other memory cell <NUM> commonly connected to a given word line <NUM>. For example, memory cells <NUM> commonly connected to word line <NUM>N and selectively connected to even bit lines <NUM> (e.g., bit lines <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc.) may be one physical page of memory cells <NUM> (e.g., even memory cells) while memory cells <NUM> commonly connected to word line <NUM>N and selectively connected to odd bit lines <NUM> (e.g., bit lines <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc.) may be another physical page of memory cells <NUM> (e.g., odd memory cells). Although bit lines <NUM><NUM>-<NUM><NUM> are not explicitly depicted in <FIG>, it is apparent from the figure that the bit lines <NUM> of the array of memory cells 200A may be numbered consecutively from bit line <NUM><NUM> to bit line <NUM>M. Other groupings of memory cells <NUM> commonly connected to a given word line <NUM> may also define a physical page of memory cells <NUM>. For certain memory devices, all memory cells commonly connected to a given word line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines <NUM><NUM>-<NUM>N (e.g., all NAND strings <NUM> sharing common word lines <NUM>). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

Although the example of <FIG> is discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS or other data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

<FIG> is another schematic of a portion of an array of memory cells 200B as could be used in a memory of the type described with reference to <FIG>, e.g., as a portion of array of memory cells <NUM>. Like numbered elements in <FIG> correspond to the description as provided with respect to <FIG>. <FIG> provides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate vertical structures which may include semiconductor pillars where a portion of a pillar may act as a channel region of the memory cells of NAND strings <NUM>. The NAND strings <NUM> may be each selectively connected to a bit line <NUM><NUM>-<NUM>M by a select transistor <NUM> (e.g., that may be drain select transistors, commonly referred to as select gate drain) and to a common source <NUM> by a select transistor <NUM> (e.g., that may be source select transistors, commonly referred to as select gate source). Multiple NAND strings <NUM> might be selectively connected to the same bit line <NUM>. Subsets of NAND strings <NUM> can be connected to their respective bit lines <NUM> by biasing the select lines <NUM><NUM>-<NUM>K to selectively activate particular select transistors <NUM> each between a NAND string <NUM> and a bit line <NUM>. The select transistors <NUM> can be activated by biasing the select line <NUM>. Each word line <NUM> may be connected to multiple rows of memory cells of the memory array 200B. Rows of memory cells that are commonly connected to each other by a particular word line <NUM> may collectively be referred to as tiers.

The three-dimensional NAND memory array 200B might be formed over peripheral circuitry <NUM>. The peripheral circuitry <NUM> might represent a variety of circuitry for accessing the memory array 200B. The peripheral circuitry <NUM> might include complementary circuit elements. For example, the peripheral circuitry <NUM> might include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience. The peripheral circuitry <NUM> might further include capacitor structures (not shown in <FIG>) in accordance with embodiments for use as decoupling capacitors, coupling capacitors and/or storage capacitors.

<FIG> are schematics of portions of an integrated circuit device having a capacitor in accordance with an embodiment. <FIG> depict examples of the use of decoupling capacitors between power rail voltages within an integrated circuit device, while <FIG> and <FIG> depict examples of the use of coupling capacitors and storage capacitors within voltage generation circuits of an integrated circuit device. Voltage generation circuits typically increase or decrease an input supply voltage in order to provide a higher or lower output voltage, respectively, required to operate circuit elements in integrated circuits. The decoupling capacitors, coupling capacitors and/or storage capacitors as described below might be distributed among the peripheral circuitry <NUM> of three-dimensional NAND memory array 200B of <FIG>, for example.

<FIG> depicts voltage supply nodes <NUM><NUM> and <NUM><NUM> connected to conductive nodes <NUM><NUM> and <NUM><NUM>, respectively, of a memory device <NUM>. The conductive nodes <NUM><NUM> and <NUM><NUM> might each represent conductive nodes providing for electrical connection to the memory device <NUM> by an external device (e.g., processor <NUM>), such as conductive pads or conductive bumps as are commonly used. The voltage supply node <NUM><NUM> might be configured to supply a bottom rail supply voltage, such as VssQ, while the voltage supply node <NUM><NUM> might be configured to supply a low top rail supply voltage, such as VccQ. As an example, VssQ and VccQ might represent power rails for a data path of the memory device <NUM>. As a further example, typical values of VssQ might be 0V or ground, while a typical value of VccQ might be <NUM>. The conductive nodes <NUM><NUM> and <NUM><NUM> might be connected to conductors <NUM><NUM> and <NUM><NUM>, respectively, for distributing the rail voltages to various circuitry of the memory device <NUM>. One or more decoupling capacitors <NUM> might be connected between the conductors <NUM><NUM> and <NUM><NUM> to decouple high frequency noise from the rail voltages. Such decoupling capacitors <NUM> might be distributed across a die containing the memory device <NUM> between conductors carrying VccQ and VssQ in order to mitigate VccQ bus noise during high-speed data communications.

<FIG> depicts voltage supply node <NUM><NUM> connected to a first input of a voltage regulator <NUM> and connected to conductive node <NUM><NUM> of a memory device <NUM>. <FIG> further depicts voltage supply node <NUM><NUM> connected to a second input of the voltage regulator <NUM>, which has an output connected to conductive node <NUM><NUM>. The conductive nodes <NUM><NUM> and <NUM><NUM> might each represent conductive nodes providing for electrical connection to the memory device <NUM> by an external device (e.g., processor <NUM> and/or voltage regulator <NUM>), such as conductive pads or conductive bumps as are commonly used. The voltage supply node <NUM><NUM> might be configured to supply a bottom rail supply voltage, such as Vss, while the voltage supply node <NUM><NUM> might be configured to supply a top rail supply voltage, such as VccX. The voltage regulator <NUM> might be configured to generate a regulated top rail voltage VccR. As an example, Vss and VccR might represent power rails for operation of internal logic of the memory device <NUM>. As a further example, typical values of Vss might be 0V or ground, and typical values of VccX might be <NUM>-<NUM>. 6V, while typical values of VccR might be <NUM>-<NUM>. The conductive nodes <NUM><NUM> and <NUM><NUM> might be connected to conductors <NUM><NUM> and <NUM><NUM>, respectively, for distributing the rail voltages to various circuitry of the memory device <NUM>. One or more decoupling capacitors <NUM> might be connected between the conductors <NUM><NUM> and <NUM><NUM> to decouple high frequency noise from the rail voltages. Such decoupling capacitors <NUM> might be distributed across a die containing the memory device <NUM> between conductors carrying VccR and Vss in order to mitigate VccR bus noise from the internal logic of the memory device <NUM>.

<FIG> depicts voltage node <NUM><NUM>, which might be a voltage node internal to the memory device <NUM> and configured to supply a bottom rail voltage, such as VssPump, while the voltage node <NUM><NUM> might be a voltage node internal to the memory device <NUM> and configured to supply a top rail voltage, such as VccPump. As an example, VssPump and VccPump might represent power rails received from a voltage generation circuit of the memory device <NUM>. As a further example, typical values of VssPump might be 0V or ground, and typical values of VccPump might be <NUM>-32V. The voltage nodes <NUM><NUM> and <NUM><NUM> might be connected to conductors <NUM><NUM> and <NUM><NUM>, respectively, for distributing the rail voltages to various circuitry of the memory device <NUM>. One or more decoupling capacitors <NUM> might be connected between the conductors <NUM><NUM> and <NUM><NUM> to decouple high frequency noise from the rail voltages.

<FIG> depicts an example of a negative charge pump, e.g., for developing a decreasing voltage level at its output. The charge pump of <FIG> receives an input voltage Vin. A first clock signal CLK1 may be received at one input of coupling capacitor <NUM><NUM>, while a second clock signal CLK2 may be received at one input of coupling capacitor <NUM><NUM>. Clock signals CLK1 and CLK2 would generally have opposite phases, the same frequency, and similar (e.g., the same) amplitudes, which may correspond to the amplitude of a supply voltage. Although the coupling capacitors <NUM><NUM> and <NUM><NUM> are each depicted as single capacitors, one or both might alternatively each represent multiple capacitors connected in parallel.

The charge pump of <FIG> might include two parallel stages <NUM>. The stages <NUM><NUM> and <NUM><NUM> may each include a coupling capacitor <NUM><NUM> and <NUM><NUM>, respectively. The stages <NUM><NUM> and <NUM><NUM> may further include a voltage isolation device <NUM><NUM> and <NUM><NUM>, respectively, e.g., a transistor configured to function as a diode. The voltage isolation devices <NUM> may be included to protect a load, e.g., circuitry configured to receive the output voltage Vout. In the charge pump of <FIG>, the voltage isolation devices <NUM> may generally mitigate charge or discharge of the coupling capacitors <NUM> between cycles of their respective clock signal CLK1 or CLK2. Cross-coupled transistors (e.g., p-type field effect transistors) <NUM><NUM> and <NUM><NUM> may be included to discharge their respective coupling capacitor <NUM><NUM> and <NUM><NUM> while their respective clock signal CLK1 and CLK2 is logic high (e.g., due to the capacitive effect of the logic low level of the complementary clock signal), and to isolate their respective coupling capacitor <NUM><NUM> and <NUM><NUM> when their respective clock signal CLK1 and CLK2 transitions to logic low. Thus, the charge pump of <FIG> may progressively remove charge from the coupling capacitor <NUM> of each stage, and can produce a decreasing voltage level. A storage capacitor <NUM> might be connected between the output of the charge pump of <FIG> and a voltage node (e.g., ground node) <NUM>. Although the storage capacitor <NUM> is depicted as a single capacitor, it might alternatively represent multiple capacitors connected in parallel.

<FIG> depicts an example of a positive charge pump, e.g., for developing an increasing voltage level at its output. The charge pump of <FIG> receives an input voltage Vin, which might be Vcc for example. A first clock signal CLK1 may be received at one input (e.g., electrode) of alternating coupling capacitors, e.g., coupling capacitors <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc., while a second clock signal CLK2 may be received at one input (e.g., electrode) of alternating coupling capacitors, e.g., coupling capacitors <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, etc. While coupling capacitors <NUM><NUM>, <NUM><NUM> and <NUM><NUM> are not directly shown in <FIG>, it is apparent from the numbering of coupling capacitors <NUM> from <NUM> to N. Although the coupling capacitors <NUM> are each depicted as single capacitors, one or more might alternatively each represent multiple capacitors connected in parallel. Clock signals CLK1 and CLK2 would generally have opposite phases, the same frequency, and similar (e.g., the same) amplitudes, which may correspond to the amplitude of a supply voltage.

The charge pump of <FIG> may include N stages <NUM>. The stages <NUM><NUM> through <NUM>N-<NUM> may each include a coupling capacitor <NUM>. The stages <NUM><NUM> through <NUM>N may further include a voltage isolation device <NUM>, e.g., a diode. The Nth stage <NUM>N of the charge pump of <FIG> may contain voltage isolation device <NUM>N without a corresponding coupling capacitor <NUM>. The voltage isolation device <NUM>N may be included to protect a load, e.g., circuitry configured to receive the output voltage Vout. In the charge pump of <FIG>, the voltage isolation devices <NUM> may generally mitigate charge or discharge of the coupling capacitors <NUM> between cycles of their respective clock signal CLK1 or CLK2. Thus, the charge pump of <FIG> may progressively store more charge on the coupling capacitor of each stage, and several such stages being placed together in the charge pump can produce an increasing voltage level. A storage capacitor <NUM> might be connected between the output of the charge pump of <FIG> and a voltage node, e.g., ground node, <NUM>. Although the storage capacitor <NUM> is depicted as a single capacitor, it might alternatively represent multiple capacitors connected in parallel.

The various uses of capacitors described with reference to <FIG> may be critical to effective operation of the integrated circuit device in which they are contained. However, charge build-up within the capacitors may occur during fabrication, and uncontrolled discharge of such charge build-up can punch through the dielectric of a capacitor, which can create a conductive path between its electrodes, effectively destroying that capacitor.

<FIG> are cross-sectional views of a capacitor of the related art to provide an example of such hazards. The capacitor of <FIG> includes a first conductive region <NUM> formed in a semiconductor <NUM>. The semiconductor <NUM> might have a first conductivity type. For example, the semiconductor <NUM> might be a p-type or n-type monocrystalline silicon or other semiconductor. The first conductive region <NUM> might have a second conductivity type, different than the first conductivity type, and might function as a first electrode of the capacitor. For example, where the semiconductor <NUM> is a p-type semiconductor, the first conductive region <NUM> might have an n-type conductivity. The capacitor of <FIG> further includes a second conductive region <NUM> formed in the semiconductor <NUM>. The second conductive region <NUM> might have the first conductivity type. Other circuitry of the integrated circuit device incorporating the capacitor of <FIG> might be formed in the second conductive region <NUM>.

The capacitor of <FIG> further includes a dielectric <NUM> and a conductor <NUM>. The dielectric <NUM> might generally be formed of one or more dielectric materials, while the conductor <NUM> might generally be formed of one or more conductive materials. The conductor <NUM> might function as a second electrode of the capacitor.

During fabrication of the capacitor, static charge <NUM> might be transferred to, and stored in, the first conductive region <NUM> as depicted in <FIG>. For example, plasma processing having a non-uniform plasma doping (PLAD) may produce static charge. Mechanically induced static charge may occur during chemical-mechanical planarization (CMP). Other fabrication processes might also lead to static charge build-up, such as non-uniform chemical vapor deposition (CVD), non-uniform dry etch plasma, non-uniform implant beam energy, etc. Regardless of the mechanism, such static charge <NUM> might be transferred to the first conductive region <NUM>. This stored charge can lead to high voltage levels within the first conductive region <NUM>, and may exceed 25V. However, due to a typically low tunneling barrier of the dielectric <NUM>, the conductor <NUM> might be at a substantially similar voltage level. Subsequent processing might then result in the conductor <NUM> being connected to a ground node <NUM> as depicted in <FIG>. For example, conductive wet or plasma process may result in grounding of the conductor <NUM>. Alternatively, grounding of the conductor <NUM> might occur during formation of additional conductors, such as metal layer formation. With the resulting voltage differential across the dielectric <NUM>, the energy stored in the first conductive region <NUM> might be suddenly released through the dielectric <NUM>, and may cause the first conductive region <NUM> to fuse with the conductor <NUM>, creating a permanent capacitor short. Designs of the related art might typically provide for connecting the conductor <NUM> to a diode, e.g., a button diode, during subsequent processing in order to provide protection against static discharge. Such connections generally rely on the formation of an additional conductor, e.g., a metal line, connected to the conductor <NUM> and to the diode, which generally might occur subsequent to metal layer formation or other processing that could inadvertently ground the conductor <NUM> prior to connection to the diode. As such, this diode protection may not be available until after damage from static discharge has occurred.

Various embodiments provide capacitor structures to facilitate mitigation of uncontrolled release of stored energy from an electrode of the capacitor. Some embodiments provide for a reversed biased, e.g., N-P, junction between a first conductive region forming an electrode of the capacitor and having a conductivity type, e.g., an n-type conductivity, and a second conductive region having a different conductivity type, e.g., a p-type conductivity.

<FIG> are cross-sectional views of a capacitor structure in accordance with an embodiment at various stages of fabrication. <FIG> depicts a semiconductor <NUM>, a first conductive region (e.g., well) <NUM> formed in the semiconductor <NUM>, and a second conductive region (e.g., well) <NUM> formed in the semiconductor <NUM>.

The semiconductor <NUM> might have a first conductivity type. For example, the semiconductor <NUM> might be a p-type or n-type monocrystalline silicon or other semiconductor. The first conductive region <NUM> might have a second conductivity type, different than the first conductivity type, and might function as a first electrode of the capacitor structure. For example, where the semiconductor <NUM> is a p-type semiconductor, the first conductive region <NUM> might have an n-type conductivity, such as an N+ conductivity. As is typical in integrated circuit fabrication, the "+" indicates higher levels of doping, e.g., sufficient to impart conductivity to this region of the semiconductor <NUM>. The second conductive region <NUM> might have the first conductivity type, e.g., a p-type conductivity in this example, such as a P+ conductivity. Other circuitry of the integrated circuit device incorporating the capacitor structure of <FIG> might be formed in the second conductive region <NUM>.

The first conductive region <NUM> and the second conductive region <NUM> might be formed by implanting respective dopant species into the semiconductor <NUM>. As is well understood in the art, such implantation might commonly involve acceleration of ions directed at a surface of the semiconductor <NUM>. To produce an n-type conductivity, the dopant species might include ions of arsenic (As), antimony (Sb), phosphorus (P) or another n-type impurity. To produce a p-type conductivity, the dopant species might include ions of boron (B) or another p-type impurity. Other methods of forming conductive regions in a semiconductor are known and embodiments herein are not limited to any method of forming the conductive regions.

In <FIG>, a dielectric <NUM> might be formed overlying the first conductive region <NUM>, the semiconductor <NUM> and the second conductive region <NUM>. A conductor <NUM> might be formed overlying the dielectric <NUM>. The conductor <NUM> may generally be formed of one or more conductive materials. For example, the conductor <NUM> may comprise, consist of, or consist essentially of conductively doped polysilicon and/or may comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material. The conductor <NUM> might have a conductivity type. As one example, the conductor <NUM> might be a conductively doped silicon material, e.g., a polycrystalline silicon commonly referred to as polysilicon. For such embodiments, the conductivity type might be either the first conductivity type or the second conductivity type.

The dielectric <NUM> may generally be formed on one or more dielectric materials. For example, the dielectric <NUM> may comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide, and/or may comprise, consist of, or consist essentially of a high-K dielectric material, such as aluminum oxides (AlOx), hafnium oxides (HfOx), hafnium aluminum oxides (HfAlOx), hafnium silicon oxides (HfSiOx), lanthanum oxides (LaOx), tantalum oxides (TaOx), zirconium oxides (ZrOx), zirconium aluminum oxides (ZrAlOx), yttrium oxide (Y<NUM>O<NUM>), etc., as well as any other dielectric material. As one example, the dielectric <NUM> might be a thermal oxide formed by reaction of an underlying silicon-containing first conductive region <NUM>, semiconductor <NUM> and second conductive region <NUM>.

In <FIG>, the conductor <NUM>, the dielectric <NUM>, the first conductive region <NUM> and the second conductive region <NUM> might be patterned to form trenches <NUM>. Patterning might include an isotropic etch or other suitable process or processes for removal of these materials. Formation of the trenches <NUM> might define a first island <NUM><NUM> of the first conductive region <NUM>, a second island <NUM><NUM> of the first conductive region <NUM>, an island <NUM> of the second conductive region <NUM>, a first dielectric portion <NUM><NUM> overlying the first island <NUM><NUM> of the first conductive region <NUM>, a second dielectric portion <NUM><NUM> overlying the second island <NUM><NUM> of the first conductive region <NUM> and overlying the island <NUM> of the second conductive region <NUM>, a first conductor portion <NUM><NUM> overlying the first dielectric portion <NUM><NUM>, and a second conductor portion <NUM><NUM> overlying the second dielectric portion <NUM><NUM>. The first conductor portion <NUM><NUM>, the first dielectric portion <NUM><NUM>, and the first island <NUM><NUM> of the first conductive region <NUM> might collectively form a capacitor of the capacitor structure of <FIG>. The trenches <NUM> might then be filled with a dielectric material to form isolation regions <NUM> as depicted in <FIG>. The isolation regions <NUM> might surround the first and second conductor portions <NUM><NUM> and <NUM><NUM> as depicted in <FIG>.

In <FIG>, the second conductor portion <NUM><NUM> and the second dielectric portion <NUM><NUM> might be removed to expose the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>, as well as any portion of the semiconductor <NUM> between the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>. In <FIG>, a third conductive region <NUM> might be formed in the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>, as well as in any portion of the semiconductor <NUM> between the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>. The third conductive region <NUM> might be formed by implanting a dopant species into these formations. The third conductive region <NUM> might have a same or different conductivity type as the first conductive region <NUM>. Additional dielectric material might be formed overlying the third conductive region <NUM> to fill the gap depicted in <FIG>.

<FIG> is a plan view of a capacitor structure in accordance with an embodiment at a stage of fabrication corresponding to <FIG>. In particular, <FIG> depicts the first conductor portion <NUM><NUM> and the second conductor portion <NUM><NUM> surrounded by isolation region <NUM>. Although the first conductor portion <NUM><NUM> and the second conductor portion <NUM><NUM> are depicted as regular quadrilaterals in profile, other shapes might also be used. The first conductor portion <NUM><NUM> might subsequently be connected to a conductor <NUM>, e.g., conductor <NUM><NUM>, configured to provide a rail voltage, e.g., a top rail voltage, as described with reference to <FIG> for use of the capacitor structure as a decoupling capacitor. As another example, the first conductor portion <NUM><NUM> might subsequently be connected to receive a clock signal CLK1 or CLK2, as described with reference to <FIG> and <FIG> for use of the capacitor structure as a coupling capacitor. As a further example, the first conductor portion <NUM><NUM> might subsequently be connected to a voltage node <NUM>, as described with reference to <FIG> and <FIG> for use of the capacitor structure as a storage capacitor.

<FIG> are cross-sectional views of portions of capacitor structures in accordance with embodiments at a stage of fabrication corresponding to <FIG>. <FIG> depict portions of the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>, as well as any portion of the semiconductor <NUM> between the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM> prior to removal of the second conductor portion <NUM><NUM>.

Using the common example of the first conductive region <NUM> having an N+ conductivity and the second conductive region <NUM> having a P+ conductivity, the second conductor portion <NUM><NUM> of <FIG> might have an N+ conductivity, while the second conductor portion <NUM><NUM> of <FIG> might have a P+ conductivity. In both cases, a conductive path <NUM> might be established from the first conductive region <NUM> to the second conductive region <NUM> through a diode <NUM>, e.g., a reverse biased Zener diode, resulting between the second conductor portion <NUM><NUM> and the island <NUM> of the second conductive region <NUM> in the case of <FIG>, or between the second island <NUM><NUM> of the first conductive region <NUM> and the second conductor portion <NUM><NUM> in the case of <FIG>. In both cases, the second conductor portion <NUM><NUM> may form one terminal of the diode <NUM>, while the island <NUM> of the second conductive region <NUM> or the second island <NUM><NUM> of the first conductive region <NUM> might form the second terminal of the diode <NUM> for <FIG>, respectively.

Due to the nature of the doped junctions, a Zener voltage of the diode <NUM> might be expected to be less than, e.g., much less than, the breakdown voltage between the first conductive region <NUM> and the first conductor portion <NUM><NUM>. , e.g., possibly around 5V versus <NUM>-30V. As one example, the Zener voltage of the diode <NUM> might be in a range of <NUM>-7V. As such, stored energy within the first conductive region <NUM> might be discharged to the second conductive region <NUM> through the diode <NUM> at a very early stage of fabrication without damage to the capacitor. Specifically, the stored energy within the first conductive region <NUM> might be discharged before connecting the first conductor portion <NUM><NUM> to any other circuitry, e.g., while the first conductor portion <NUM><NUM> might be isolated from other conductive materials. Damage to the second dielectric portion <NUM><NUM> might be inconsequential as it may be considered sacrificial.

<FIG> are cross-sectional views of portions of capacitor structures in accordance with embodiments at a stage of fabrication corresponding to <FIG>. <FIG> depict portions of the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM>, as well as any portion of the semiconductor <NUM> between the second island <NUM><NUM> of the first conductive region <NUM> and the island <NUM> of the second conductive region <NUM> after formation of the third conductive region <NUM>.

Using the common example of the first conductive region <NUM> having an N+ conductivity and the second conductive region <NUM> having a P+ conductivity, the third conductive region <NUM> of <FIG> might have an N+ conductivity, while the third conductive region <NUM> of <FIG> might have a P+ conductivity. In both cases, a conductive path <NUM> might be established from the first conductive region <NUM> to the second conductive region <NUM> through a diode <NUM>, e.g., a reverse biased Zener diode, resulting between the third conductive region <NUM> and the island <NUM> of the second conductive region <NUM> in the case of <FIG>, or between the second island <NUM><NUM> of the first conductive region <NUM> and the third conductive region <NUM> in the case of <FIG>. In both cases, the third conductive region <NUM> may form one terminal of the diode <NUM>, while the island <NUM> of the second conductive region <NUM> or the second island <NUM><NUM> of the first conductive region <NUM> might form the second terminal of the diode <NUM> for <FIG>, respectively. For reasons similar to those presented with respect to <FIG>, this structure might likewise continue to provide protection of the capacitor before and after connecting the first conductor portion <NUM><NUM> to any other circuitry.

<FIG> is a flowchart of a method of forming a capacitor structure in accordance with embodiments. At <NUM>, a first conductive region having a first conductivity type might be formed in a semiconductor material, and a second conductive region having a second conductivity type, different than the first conductivity type, might be formed in the semiconductor material. The semiconductor material might have the first conductivity type or the second conductivity type.

At <NUM>, a dielectric might be formed overlying the first conductive region and overlying the second conductive region. At <NUM> a conductor might be formed overlying the dielectric.

At <NUM>, the conductor, dielectric, first conductive region and second conductive region might be patterned to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric separated from a second portion of the dielectric, and a first portion of the conductor separated from a second portion of the conductor.

Optionally, at <NUM>, the second portion of the conductor and the second portion of the dielectric might be removed, and, at <NUM>, a third conductive region extending from the second island of the first conductive region to the island of the second conductive region might be formed. The third conductive region might have the first conductivity type or the second conductivity type.

Claim 1:
A capacitor structure, comprising:
a first conductive region (<NUM>) having a first conductivity type, the first conductive region comprising a first protrusion portion (<NUM><NUM>) and a second protrusion portion (<NUM><NUM>);
a second conductive region (<NUM>) having a second conductivity type different than the first conductivity type, the second conductive region (<NUM>) comprising a protrusion portion (<NUM>);
a first dielectric (<NUM>, <NUM><NUM>) overlying the first protrusion portion (<NUM><NUM>) of the first conductive region;
a first conductor (<NUM>) overlying the first dielectric (<NUM>); and
a terminal of a diode overlying the second protrusion portion (<NUM><NUM>) of the first conductive region (<NUM>) and overlying the protrusion portion (<NUM>) of the second conductive region (<NUM>), the terminal of the diode comprising a second conductor isolated from the first conductor (<NUM>).