Patent Description:
Some analog-to-digital converters have one or more voltage-to-delay (V2D) components and operate, at least in part, in a delay domain. Delay-based analog-to-digital converters are described in <CIT>), <CIT>), and <CIT>). The entire disclosures of <CIT>, <CIT>, and <CIT> are incorporated herein by reference. In addition, the entire disclosures of the five U. patent applications identified below in Table <NUM> are incorporated herein by reference. Delay-based analog-to-digital converters may be operated, if desired, at high speed, with reduced area and power requirements. The article "<NPL>" discloses a folding voltage to time converter. Further, <CIT> discloses a conversion and folding circuit including a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

Like elements are designated by like reference numerals and other characters throughout the drawings.

<FIG> illustrates an analog-to-digital converter system <NUM> constructed in accordance with the present disclosure. The analog-to-digital converter system <NUM> has a multiplexer <NUM> for receiving an input voltage VIN on an input line <NUM>, and a voltage-to-delay preamplifier array <NUM> for receiving a sampled voltage V from the multiplexer <NUM> on a sampled voltage line <NUM>. The multiplexer <NUM> may include an analog multiplexer.

As illustrated in <FIG>, the preamplifier array <NUM> has first and second through Nth preamplifiers <NUM>, <NUM> and <NUM> (N = <NUM>, <NUM>, <NUM> or more). In operation, the preamplifiers <NUM>, <NUM> and <NUM> generate first and second output signals OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_MN and OUT_PN based on differences between the sampled voltage V and threshold voltages TH<NUM>, TH<NUM> and THN (TH<NUM> < TH<NUM> < THN) applied to the preamplifiers <NUM>, <NUM> and <NUM>. In the illustrated configuration, the threshold voltages TH<NUM>, TH<NUM> and THN are applied to the preamplifiers <NUM>, <NUM> and <NUM> by a suitable voltage divider <NUM>. The present disclosure should not be limited, however, to the illustrated configuration. If desired, all or some of the preamplifiers <NUM>, <NUM> and <NUM> may be threshold-integrated preamplifiers.

The analog-to-digital converter system <NUM> (<FIG>) also has a folding delay multiplexer <NUM>, which receives the output signals OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_MN and OUT_PN (<FIG>). In an operational phase, the folding delay multiplexer <NUM> generates first and second delay signals OUT_M and OUT_P (on lines <NUM> and <NUM>) corresponding to the output signals of the most relevant one of the preamplifiers <NUM>, <NUM> and <NUM> (that is, the one preamplifier within the array <NUM> whose threshold voltage is closest to the sampled voltage V).

An example of a folding circuit of the folding delay multiplexer <NUM> is illustrated in <FIG> and is described in more detail below. The delay multiplexer <NUM> is a data selector in the delay domain (where information is represented by delay). The delay multiplexer <NUM> selects one pair of delay signals from several pairs of delay signals and outputs a single pair of signals with delay corresponding to the selected pair of signals. The illustrated delay multiplexer <NUM> uses logic gates to perform a folding process as shown in <FIG> and as described in more detail below.

In the example illustrated in <FIG>, if the sampled voltage V is closer to the threshold voltage TH<NUM> of the first preamplifier <NUM> than it is to any of the other threshold voltages TH<NUM> and THN, then the first preamplifier <NUM> is the most relevant preamplifier within the array <NUM>, and the relative timings of the leading edges of the delay signals OUT_M and OUT_P correspond to the relative timings of the leading edges of the first and second output signals OUT_M<NUM> and OUT_P<NUM> of the first preamplifier <NUM>.

On the other hand, if the sampled voltage V is closer to the threshold voltage TH<NUM> of the second preamplifier <NUM> than it is to any of the threshold voltages TH<NUM> and THN of the other preamplifiers <NUM> and <NUM>, then the second preamplifier <NUM> is the most relevant preamplifier, and the relative timings of the leading edges of the delay signals OUT_M and OUT_P correspond to the relative timings of the leading edges of the output signals OUT_M<NUM> and OUT_P<NUM> of the second preamplifier <NUM>.

The analog-to-digital converter system <NUM> (<FIG>) also has an analog-to-digital converter backend <NUM> for receiving and processing input signals on lines <NUM> and <NUM> where the input signals (<NUM> and <NUM>) are based at least in part on the delay signals OUT_M and OUT_P. The analog-to-digital converter backend <NUM> generates digital signals (codes) that are transmitted to a calibration engine/processor <NUM> on a suitable line <NUM>. Timing control for the analog-to-digital converter backend <NUM> is provided by the calibration engine/processor <NUM> on another suitable line <NUM>.

The analog-to-delay converter backend <NUM> has a first delay comparator <NUM> for generating a single-bit digital signal on line <NUM> to indicate which one of the delay signals OUT_M and OUT_P (or, which one of the signals on lines <NUM> and <NUM>) reaches the delay comparator <NUM> first. The digital signal on line <NUM> is representative of the order in which signals (<NUM> and <NUM>) are received at the delay comparator <NUM>. A residue delay signal is output from the first delay comparator <NUM>, on a suitable line <NUM>, to a second delay comparator (not illustrated in <FIG> and <FIG>). Examples of the structure and operation of the delay comparator <NUM>, the second delay comparator, and successive comparators are illustrated in <FIG>.

In the illustrated configuration, the delay-resolving backend <NUM> includes a cascade of delay-based stages. The first delay-based stage <NUM> (<FIG>) is connected to successive delay-based stages by the suitable line <NUM>. In the example shown in <FIG> all of the delay-based stages are single-bit stages. According to other aspects of the present disclosure, the delay-resolving back end <NUM> may have one or more multi-bit stages. For example, one or more delay-based stages may be two-bit stages and/or one or more delay-based stages may be four-bit stages. For example, the first stage <NUM> may be a single-bit stage, while second, third, and fourth successive stages may be four-bit, single-bit, and two-bit stages, respectively, and residual delay-based stages after the fourth stage may all be single-bit stages. Each stage may have one or more delay comparators. Thus, the analog-to-digital converter backend <NUM> may have two, three, four or more delay comparators. Digital signals generated by the delay comparators are used by the calibration engine/processor <NUM> to determine less significant bits of the value of the sampled voltage V.

During a calibration phase, a digital (whether binary, hexadecimal or other format) version of known voltage VDAC is established by a digital code generated by the calibration engine/processor <NUM> and output on line <NUM>. Digital-to-analog (D/A) converter (DAC) <NUM> (<FIG>) converts the digital version of known voltage VDAC to analog and outputs this signal on a second input line <NUM> of multiplexer <NUM>. The multiplexer <NUM> selects and applies either the input voltage VIN or the known voltage VDAC to the sampled voltage line <NUM> (as the sampled voltage V), under the control (SEL<NUM> signal) of the calibration engine/processor <NUM>, via a control line <NUM>.

During the operational phase of the analog-to-digital converter system <NUM>, the input voltage VIN is transmitted (as the sampled voltage V) to the preamplifier array <NUM>, and a digital code representative of the input voltage VIN is generated by the calibration engine/processor <NUM>, using digital information received from the preamplifier array <NUM> and the comparators of the backend <NUM>, as described in more detail below. The representative digital code is output on an output line <NUM>.

In the example illustrated in <FIG>, during the operational phase, a select signal SEL<NUM> on the control line <NUM> is low ("<NUM>"), such that the sampled voltage V equals, or corresponds to, the input voltage VIN, but during the calibration phase, the select signal SEL<NUM> is high ("<NUM>"), such that the sampled voltage V equals, or corresponds to, the known voltage VDAC. The select signal SEL<NUM> is generated by the calibration engine/processor <NUM>.

The preamplifier array <NUM> is configured to generate digital signals that are transmitted to the calibration engine/processor <NUM> on a suitable line <NUM> (<FIG>). The digital signals may be used to determine the most significant bit or bits of the value of the sampled voltage V, and to identify the most relevant preamplifier within the preamplifier array <NUM> (that is, the preamplifier which generates the most significant delay information). The voltage-to-delay preamplifier array <NUM> is operated under the control of a suitable timing signal CLK (<FIG>) generated by the calibration engine/processor <NUM>. The timing signal CLK is transmitted to the preamplifiers <NUM>, <NUM> and <NUM> (<FIG>) on a suitable line <NUM>.

In the example illustrated in <FIG>, when the timing signal CLK is high ("<NUM>"), the analog-to-digital converter system <NUM> is in an active phase A, and the delay signals OUT_M and OUT_P may have high components <NUM> and low components <NUM>. When the timing signal CLK is low ("<NUM>"), the analog-to-digital converter system <NUM> is in a reset phase R, and all components of the delay signals OUT_M and OUT_P are low (<NUM>). In an operational phase, the timings of the leading edges of the delay signals OUT_M and OUT_P correspond to the timings of the leading edges of the output signals from the most relevant preamplifier within the array <NUM>. At the start of each reset phase R, the timing signal CLK (on line <NUM>) causes the preamplifiers <NUM>, <NUM> and <NUM> to reset. As a result, the delay signals OUT_M and OUT_P are both low (<NUM>) throughout each reset phase R.

The folding delay multiplexer <NUM> (<FIG>) is operated under the control of one or more signals, including a second select signal SEL<NUM>, from the calibration engine/processor <NUM>, on line <NUM>. In an operational phase, the folding delay multiplexer <NUM> causes the delay signals OUT_M and OUT_P to be based on the corresponding output signals from the most relevant preamplifier within the array <NUM>. In the calibration phase, the calibration engine/processor <NUM> can override the selection and select any one of the preamplifiers <NUM>, <NUM> and <NUM> instead of the most relevant preamplifier.

In summary, the analog-to-digital converter system <NUM> has a voltage-to-delay preamplifier array frontend (including preamplifiers <NUM> and multiplexer <NUM>) followed by a delay-resolving analog-to-digital backend <NUM>. One or more elements of the frontend <NUM>, <NUM> and the backend <NUM> may be integrated into an integrated circuit (IC) <NUM> and/or formed on or over a single semiconductor die (not shown in the drawings) according to various semiconductor and/or other processes. The conductive lines may be metal structures formed in insulating layers over the semiconductor die, doped regions (that may be silicided) formed in the semiconductor die, or doped semiconductor structures (that may be silicided) formed over the semiconductor die. Transistors used to implement the circuit structures of the example embodiments may be bipolar junction transistors (BJT) or metal-oxide-semiconductor field-effect transistors (MOSFET) and can be n-type or p-type. The integrated devices and elements may also include resistors, capacitors, logic gates, and other suitable electronic devices that are not shown in the drawings for the sake of clarity.

The first delay-based stage <NUM> (<FIG>) is connected (by lines <NUM> and <NUM>) to the folding delay multiplexer <NUM>. The successive delay-based stages are connected (by lines <NUM> and <NUM>) to the first delay-based stage <NUM>. In operation, the analog-to-digital backend <NUM> generates digital signals based on the selected delay signal, and, in the calibration phase, one or more of the illustrated preamplifiers <NUM>, <NUM> and <NUM> is adjusted based on the digital signals output by the analog-to-digital backend <NUM>. The present disclosure should not be limited, however, to the configuration illustrated in the drawings and described by way of example herein.

If desired, the analog-to-digital converter system <NUM> may be operated at high speed (for example, > <NUM> GSPS) and with high performance (for example, > <NUM> dBFS). Moreover, if desired, the analog-to-digital converter system <NUM> may consume less power than a conventional pipeline-based analog-to-digital converter. A delay-based analog-to-digital converter system constructed in accordance with the present disclosure may be used, if desired, to overcome barriers of speed, area, and power that are characteristic of conventional analog-to-digital converters.

The preamplifiers <NUM>, <NUM> and <NUM> (<FIG>) within the array <NUM> have varying gains as a result of various factors, which may include design, process, input voltage VIN, and/or temperature. According to one aspect of the present disclosure, the gains and ranges of the preamplifiers <NUM>, <NUM> and <NUM> may be adjusted, and preferably matched across the preamplifier array <NUM>. The preamplifiers <NUM>, <NUM> and <NUM> may be first calibrated, then adjusted for maximum, or improved, gain, and then corrected for gain mismatch across the array <NUM>, all while avoiding a saturation condition. Gain mismatch should be avoided because, among other reasons, it could prevent the most relevant preamplifier from being selected by the folding delay multiplexer <NUM>. In particular, gain mismatch could potentially cause a preamplifier other than the most relevant preamplifier to generate delay signals that are the latest of the earliest, and the earliest of the latest, of the signals generated by the preamplifiers in the array.

Threshold voltage calibration may be achieved by applying suitable offset voltages (having values of n1, n2, n3. ) to the threshold voltage for the most relevant preamplifier within the array <NUM>. The offset which causes the digital output of the first delay comparator <NUM> (on line <NUM>) to toggle (that is, to change from high ("<NUM>") to low ("<NUM>") and vice versa) is then used as the offset to calibrate the most relevant preamplifier. The example illustrated in <FIG> assumes that the first preamplifier <NUM> is the most relevant preamplifier within the array <NUM> (that is, that the threshold voltage TH<NUM> of the first preamplifier <NUM> is closer to the sampled voltage V than are the thresholds TH<NUM> and THN of the other preamplifiers <NUM> and <NUM>). When the sampled voltage V is closer to another threshold, then the preamplifier whose threshold voltage is closest to the sampled voltage V is the most relevant preamplifier.

As indicated above, during the calibration phase, the select signal SEL<NUM> is high ("<NUM>"), such that the sampled voltage V equals, or corresponds to, the known voltage VDAC. In the example illustrated in <FIG>, the analog-to-digital converter system <NUM> is in the calibration phase, and therefore the first select signal SEL<NUM> is high. Moreover, in the illustrated example, the sampled voltage V (= VDAC during calibration) is equal to the threshold voltage TH<NUM> of the first preamplifier <NUM> (causing the first preamplifier <NUM> to be the most relevant preamplifier within the array <NUM>), and voltage offsets, whose values are <NUM>, n1, n2, n3, -n1 and -n2 (where <NUM> < n1 < n2 < n3), are added, one at a time, to the threshold voltage TH<NUM>. In the illustrated example, the single-bit digital output of the first delay comparator <NUM>, on line <NUM>, toggles when the voltage offset is <NUM> (as shown in region <NUM> in <FIG>), indicating that the first preamplifier <NUM> does not need any threshold voltage correction. In the illustrated example, when the value of the offset is n1 or n2 (as shown in regions <NUM> and <NUM>), the comparator output (Comp Out) on line <NUM> is high ("<NUM>"), because the leading edge <NUM>, <NUM> of the second delay signal OUT_P precedes the corresponding leading edge <NUM>, <NUM> of the first delay signal OUT_M, but when the value of the offset is -n1 or -n2 (as shown in regions <NUM> and <NUM>), the comparator output on line <NUM> is low ("<NUM>"), because the leading edge <NUM>, <NUM> of the second delay signal OUT_P trails the leading edge <NUM>, <NUM> of the first delay signal OUT_M.

In the example illustrated in <FIG>, when the value of the offset is <NUM> (as shown in region <NUM>), the comparator output on line <NUM> toggles high/low, because the leading edge <NUM> of the second delay signal OUT_P coincides with the leading edge <NUM> of the first delay signal OUT_M. Therefore, in the example illustrated in <FIG>, the threshold voltage TH<NUM> of the first preamplifier <NUM> does not need correction, and an offset voltage equal to <NUM> is applied to the threshold voltage TH<NUM>.

In a different example, if it is determined that applying an offset voltage value of n1 or n2 causes the first preamplifier <NUM> to toggle the digital output (<NUM>) of the first delay comparator <NUM>, then the threshold voltage TH<NUM> of the first preamplifier <NUM> is corrected to TH<NUM> + n2 or TH<NUM> + n3, respectively. The offset correction process may be repeated for each one of the preamplifiers <NUM>, <NUM> and <NUM> within the array <NUM>. Thus, each preamplifier threshold voltage may be corrected during the calibration phase by setting the digital-to-analog converter <NUM> so that the known voltage VDAC equals an ideal threshold, and then correcting bulk voltage until the bit generated by the first delay comparator <NUM> flips from high to low (or from low to high).

After the threshold voltages TH<NUM>, TH<NUM> and THN of the preamplifiers <NUM>, <NUM> and <NUM> are corrected (to the extent required) by the application of suitable offsets, three adjustment processes may be performed. The three adjustment processes are as follows: One (referred to as "Process One"), maximizing (or at least increasing, if possible) gain of each one of the preamplifiers <NUM>, <NUM> and <NUM>. Two (referred to as "Process Two"), normalizing (or at least improving normalization of) gains of first and second zones within each one of the preamplifiers <NUM>, <NUM> and <NUM>. Three (referred to as "Process Three"), normalizing (or at least improving normalization of) gain across the preamplifier array <NUM>. According to a preferred sequence, calibration and maximization of gains of the preamplifiers <NUM>, <NUM> and <NUM> occur first, and then gain mismatches across the preamplifier array <NUM> are corrected. After, or in connection with, each one of the three adjustment processes, a saturation check (discussed in more detail below) may be performed and appropriate action may be taken in response to the saturation check. For example, if a saturation condition is detected, action may be taken to avoid such a condition, as discussed below.

The threshold voltage correction process and the three adjustment processes may all be performed by observing the single-bit output of the first delay comparator <NUM> (<FIG>) on line <NUM>. Except during the gain measurement process described below, the output on line <NUM> is high "<NUM>" when the rising edge of the second delay signal OUT_P precedes the rising edge of the first delay signal OUT_M, which in turn indicates that the sampled voltage V is greater than the threshold of the most relevant preamplifier. As described below in connection with <FIG>, folding selects the most relevant preamplifier, that is, the preamplifier whose threshold voltage is closest to the sampled voltage V.

The transfer function (voltage difference to delay) for each one of the preamplifiers <NUM>, <NUM> and <NUM> is non-linear. The delay output for a given preamplifier is the difference in timing between the rising edges of its two outputs. In the example graphically represented in <FIG>, where the first preamplifier <NUM> is the most relevant preamplifier in the array <NUM>, the delay output of the first preamplifier <NUM> as a function of the sampled voltage V may be calculated as follows: delay output = D + g1*Vdiff + g2*(Vdiff<NUM>) + g3*(Vdiff<NUM>) +. , where Vdiff = |(V - TH<NUM>)|, and D, g1, g2, and g3. are constants. In the example illustrated in <FIG>, D may be zero or near zero. The non-linear equation described herein for delay output is a mathematical representation of the non-linear voltage-to-delay pre-amp characteristics represented in <FIG>. The characteristics cannot be approximated to a linear equation with just D and g1 being non-zero.

Referring again to <FIG>, each preamplifier in the array <NUM>, under the control of the timing signal CLK, has reset phases R where the preamplifier is reset, and active phases A where the preamplifier provides outputs. The reset phase R begins and ends when the clock signal CLK falls and rises, respectively. The active phase A begins and ends when the clock signal rises and falls, respectively. The relevant delay information is the time difference between the rising edges of the two outputs from the most relevant preamplifier.

A saturation condition (SAT) occurs when the gain of the most relevant preamplifier is so large that the later-arriving rising edge of the output signals from the most relevant preamplifier does not arrive before the end of the active phase A. An example of a saturation condition (SAT) is illustrated in <FIG>, in region <NUM>, where VDAC = TH<NUM> + n3 such that OUT_P precedes OUT_M, and the rising edge of OUT_M does not arrive before the end of the corresponding active phase A. In the illustrated configuration, a saturation condition may be detected by latching the outputs of a preamplifier at the end of an active phase A and checking whether both of the preamplifier's outputs are high ("<NUM>"). If either one of the outputs is low ("<NUM>") and remains low throughout the active phase A, then there is a saturation condition.

Two different processes for maximizing gains of individual preamplifiers (Process One) are illustrated in <FIG> and <FIG>. An object of each process is to maximize gain of each preamplifier within the array <NUM> without creating a saturation condition in any of the preamplifiers. In general, decreasing current through a preamplifier increases the gain of the preamplifier. Thus, in a current-driven process (<FIG>), the calibration engine/processor <NUM> causes the current common to all of the preamplifiers <NUM>, <NUM> and <NUM> to be set at the lowest value possible without the first preamplifier <NUM> (n = <NUM>; Step <NUM>) being subject to a saturation condition (Step <NUM>).

The saturation check (Step <NUM>) may be performed by decreasing the common current on a step-wise basis until a saturation condition is identified, and then setting the common current at the value that was applied immediately before the saturation condition was identified. The lack of a saturation condition at a particular common current may be determined by confirming that neither output from the most relevant preamplifier is low ("<NUM>") throughout a corresponding active phase A across the whole voltage range of the preamplifier. If either of the outputs from the preamplifier is low throughout the active phase A, at any point within the voltage range of the preamplifier, then the preamplifier is subject to a saturation condition at that common current value.

After Step <NUM>, a determination is made as to whether the second preamplifier <NUM> (n = <NUM>, after Step <NUM>) is subject to a saturation condition (Step <NUM>) when the sampled voltage V is in the vicinity of the second threshold voltage TH<NUM>. If the second preamplifier <NUM> is subject to a saturation condition, at any point within the range of the second preamplifier <NUM>, the common current is increased (Step <NUM>) until the second preamplifier <NUM> is not subject to a saturation condition (by repeating Steps <NUM> and <NUM> until the second preamplifier <NUM> is not subject to a saturation condition).

After each gain-reduction (that is, after each time through Step <NUM>), there is a check for saturation (Step <NUM>), and further reduction of gain (increase in current) (Step <NUM>) if the outcome of the saturation check indicates that it is desirable, before proceeding to the next preamplifier (NO from Step <NUM>, and incrementing value of n by proceeding through Step <NUM>). When gains of all the preamplifiers have been adjusted, that is, when n = N, the process illustrated in <FIG> may be concluded (Step <NUM>).

For preamplifiers of the type described herein, delay (gain) = C*V/I, where C is capacitance, I is current, and V is voltage (fixed to VDD). Thus, gain increases as current decreases, and gain increases as capacitance increases. In the illustrated configuration, current I is common across all of the preamplifiers <NUM>, <NUM> and <NUM> (<FIG>). Therefore, if current I is changed, the gains of all of the preamplifiers <NUM>, <NUM> and <NUM> are changed. On the other hand, in the illustrated configuration, capacitances of the individual preamplifiers <NUM>, <NUM> and <NUM> may be different from each other. If the capacitance of one preamplifier is changed, only the gain of that one preamplifier is thereby changed; the gains of the other preamplifiers are not changed.

Various suitable circuits and devices may be used to adjust the common current I. In the illustrated configuration, adjustment of the common current I may be made by a variable current circuit <NUM> (<FIG>) which has an array of current sources <NUM>, <NUM>, <NUM> and <NUM> in parallel, with all but one of the current sources <NUM> having its own switch <NUM>, <NUM> and <NUM>. In a default condition, a first switch <NUM> may be closed, such that only first and second current sources <NUM> and <NUM> are active. To increase the common current I, one or more of the other switches <NUM> and <NUM> may be closed, under the control of the calibration engine/processor <NUM>, to activate the other current sources <NUM> and <NUM>. To decrease the common current I from the default condition, the first switch <NUM> may be opened, under the control of the calibration engine/processor <NUM>, to deactivate the second current source <NUM>.

The process illustrated in <FIG> is the same as the common-current process illustrated in <FIG>, except that the <FIG> process involves capacitance of individual preamplifiers. In general, increasing capacitance of a preamplifier increases gain of the preamplifier. Thus, instead of causing the current common to all of the preamplifiers <NUM>, <NUM> and <NUM> to be set at the lowest value possible without the first preamplifier <NUM> being subject to a saturation condition (Step <NUM>), the <FIG> process causes the capacitance of the first preamplifier <NUM> to be set at the greatest value possible without the first preamplifier <NUM> being subject to a saturation condition (Step <NUM>). Setting the capacitance in Step <NUM> may be done incrementally, with measurements being made using the measurement system illustrated in <FIG>, until the capacitance is at a value where the preamplifier <NUM> is just about to be saturated.

Various suitable circuits and devices may be used to adjust the capacitance of each one of the preamplifiers <NUM>, <NUM> and <NUM>. In the illustrated configuration, adjustment of capacitance may be made by a variable capacitance circuit <NUM> (<FIG>) which has an array of capacitive elements <NUM>, <NUM>, <NUM> and <NUM> in parallel, with all but one of the capacitive elements <NUM> having its own switch <NUM>, <NUM> and <NUM>. In a default condition, a first switch <NUM> may be closed, such that only first and second capacitive elements <NUM> and <NUM> are active. To increase the capacitance of the preamplifier which contains the variable capacitance circuit <NUM>, one or more of the other switches <NUM> and <NUM> may be closed, under the control of the calibration engine/processor <NUM>, to activate the other capacitive elements <NUM> and <NUM>. To decrease the capacitance from the default condition, the first switch <NUM> may be opened, under the control of the calibration engine/processor <NUM>, to deactivate the second element <NUM>. In the illustrated configuration, there is a separate variable capacitance circuit <NUM> for each one of the preamplifiers <NUM>, <NUM> and <NUM>.

In the <FIG> (capacitance based) process, the saturation check (Step <NUM>) may be performed the same way as in the <FIG> (common-current based) process, but instead of increasing the current common to all of the preamplifiers, the <FIG> process decreases capacitance of individual preamplifiers that are found to be subject to a saturation condition (Step <NUM> after Step <NUM>). Within each preamplifier, the negative and positive zones need to be checked for saturation. The flow chart of <FIG> only shows steps to be performed for one preamplifier. The <FIG> process is repeated for each one of the preamplifiers <NUM>, <NUM> and <NUM>.

Referring again to <FIG>, gain of a preamplifier may be measured using two delay multiplexers <NUM> and <NUM> and a line <NUM> carrying a delay-locked loop signal DLL. The first delay multiplexer <NUM> receives the first delay signal OUT_M and the delay-locked loop signal DLL. The second delay multiplexer <NUM> receives the second delay signal OUT_P and the delay-locked loop signal DLL. The delay multiplexers <NUM> and <NUM> may be controlled by suitable signals from the calibration engine/processor <NUM>. To measure gain of the most relevant preamplifier, the rise times of leading edges of the two delay signals OUT_M and OUT_P are separately measured, relative to the delay-locked loop signal DLL, using the measurement system illustrated in <FIG>. The further apart the rise times are in time, the greater the gain.

In the measurement system illustrated in <FIG>, the delay-locked loop signal DLL on line <NUM> contains a delay generated by a delay-locked loop (not illustrated), with a fine resolution (the resolution may be, for example, about <NUM> ps). In operation, to measure the timing of the second delay signal OUT _P, the second delay signal OUT_P is transmitted to the delay comparator <NUM> (via multiplexer <NUM>) while line <NUM> is connected to the comparator <NUM> (via multiplexer <NUM>) instead of the first delay signal OUT_M. The delay in line <NUM> is incrementally increased until the comparator <NUM> toggles. The delay in line <NUM> which causes the delay comparator <NUM> to toggle (on line <NUM>) is a measure of the delay of the second output signal OUT_P.

A similar approach is taken to measure the delay of the first delay signal OUT_M. The first delay signal OUT_M is transmitted to the delay comparator <NUM> (via multiplexer <NUM>) while line <NUM> is connected to the comparator <NUM> (via multiplexer <NUM>), via line <NUM>, instead of the second delay signal OUT_P. The delay in line <NUM> is incrementally increased until the comparator <NUM> toggles. In this case, the delay in line <NUM> at which the delay comparator <NUM> toggles is a measure of the delay of the first output signal OUT_M. Gain of the preamplifier <NUM> is then calculated as a function of the two measured delays, as follows: gain = delay_out/(V - TH<NUM>), where delay_out = |(doutp - doutm)|, and doutp and doutm are the measured delays of the second and first delay signals OUT_P and OUT_M.

There are also other ways to measure gain within the context of the present disclosure. For example, instead of using the delay-locked loop (DLL) line <NUM>, the known calibration voltage may be set to Vth + X, where X is such that the preamplifier is still the relevant preamplifier. The digital code output by the delay-resolving backend <NUM> is then itself a representation of the gain of the preamplifier.

Referring to Process Two, there are two zones for each one of the N preamplifiers <NUM>, <NUM> and <NUM> where, if the sampled voltage V is within one of those zones for a preamplifier, that preamplifier is the most relevant preamplifier. For each preamplifier, the sampled voltage V is greater than the threshold voltage in one of the zones, and the sampled voltage is less than the threshold voltage in the other zone. Therefore, the preamplifier array <NUM> has 2N zones. <FIG> schematically represents gain of a preamplifier as a function of the sampled voltage V. In the unequal condition represented by solid lines <NUM> and <NUM>, gain of the preamplifier while the sampled voltage V is less than the threshold voltage TH is less than gain of the preamplifier while the sampled voltage V is greater than the sampled voltage V.

By shifting the threshold voltage TH to another value THc, the relationship between the gain of the preamplifier and the voltage V can be shifted, in both zones of the preamplifier, as represented by dotted lines <NUM> and <NUM>, such that gain at the opposite ends of the voltage range of the preamplifier is the same (that is, Gain_Diff = <NUM>). To achieve such normalization of gain within the two zones of a preamplifier, it is desirable to employ fine gain control which may be achieved by adjusting bulk (body) voltage. Such bulk voltage adjustment may include shifting the threshold voltage of the preamplifier by applying an offset voltage to the threshold voltage. Adjusting the bulk voltage may provide finer gain control than adjusting the capacitance of the preamplifier.

A gain normalization process is illustrated in <FIG>. The illustrated process includes the steps performed for one preamplifier. The process is repeated for each one of the other preamplifiers. Thus, starting with the first preamplifier <NUM> (Step <NUM>), gains are measured for both zones of the preamplifier <NUM>, using the measurement system illustrated in <FIG>. If the difference between the two gains Gain_Diff is greater than a predetermined limit (that is, too large) (Yes from Step <NUM>), then the bulk voltage for the preamplifier <NUM> is changed so that the gain difference for the preamplifier <NUM> is less than or equal to the predetermined limit (Step <NUM>). Changing the bulk voltage may be done incrementally, with measurements being made using the measurement system illustrated in <FIG>, until the gain difference for the preamplifier <NUM> is less than or equal to the predetermined limit. The bulk voltage may be changed by, for example, changing the threshold voltage of the preamplifier. The process is then repeated for each one of the other preamplifiers <NUM> and <NUM>. As used herein, the term "bulk voltage" is synonymous with "back-gate voltage.

<FIG> illustrates an iterative, algorithmic approach to normalizing gain across the preamplifier array <NUM> (Process Three). The approach may be used, if desired, to maximize performance of the analog-to-digital converter system <NUM> by identifying the preamplifier which has the minimum gain, and then increasing the gain of that preamplifier, if possible considering other constraints. One such constraint is avoiding a saturation condition.

In operation, the gains of all of the preamplifiers within the array <NUM> may be determined using the measuring system illustrated in <FIG>, such that the preamplifier within the array <NUM> which has the least gain and the preamplifier within the array which has the most gain may be identified. The gain-normalization process may then begin by determining whether the difference between the highest and lowest gains is within a predetermined limit (Step <NUM>). If the difference is within the predetermined limit (Yes from Step <NUM>), then the gain range of the preamplifier array is acceptable, and the process is completed (Step <NUM>). If the gain range is not acceptable (NO from Step <NUM>), then the preamplifier which has the minimum gain is selected (Step <NUM>), and a current kick is given to the selected preamplifier and the capacitance of the preamplifier is increased to increase its gain (Step <NUM>).

Applying a current-kick improves the response time of a preamplifier by taking the preamplifier away from saturation. If the preamplifier without any current kick is close to saturation, then any further increase in capacitance (gain) causes saturation. Since the current kick brings the preamplifier away from saturation, the capacitance (gain) of the preamplifier can be increased without creating a saturation condition. Current kick by itself does not change the gain of the preamplifier. As illustrated in <FIG>, the timing difference, d, between the leading edge of the first delay signal OUT_M and the second delay signal OUT_P is the same both without current kick and with current kick. However, current kick enables an increase in gain by bringing the preamplifier away from saturation (that is, by advancing (by moving leftward in <FIG>) the leading edges of the first and second delay signals OUT_M, OUT_P within each active phase A). Hence, current kick allows a higher capacitance setting before the preamplifier saturates. The timing of a clock signal CLKKICK for applying the current kick to the preamplifiers <NUM>, <NUM> and <NUM> is controlled by the calibration engine/processor <NUM>. The current-kick clock signal CLKKICK is timed to increase the common current I during an initial portion of each active phase A. The common current I is the current that is applied to all of the preamplifiers. The common current I has a nominal value INOM during the portion of the active phase A when the clock signal CLK is high and the current-kick clock signal CLKKICK is low. The common current I has a current-kick value IKICK (IKICK > INOM) during the portion of the active phase A when both the clock signal CLK and the current-kick clock signal CLKKICK are high.

If the current kick and the increase in capacitance create a saturation condition within the selected preamplifier (YES from Step <NUM>), then gain of the selected amplifier is decreased by decreasing its capacitance (Step <NUM>).

Then, if the selected preamplifier does not still have the minimum gain, the process returns to Step <NUM> (NO from Step <NUM>). But if the selected preamplifier still has the least gain within the preamplifier array (YES from Step <NUM>), then gain of the preamplifier which has the greatest gain in the array <NUM> is decreased by decreasing its capacitance (Step <NUM>), and the process is returned to Step <NUM>, unless the capacitance cannot be decreased without creating a saturation condition (YES from Step <NUM>) in which case the process is ended (Step <NUM>).

According to the present disclosure, it may be the case that, even after a current kick is applied and gain for a selected preamplifier is maximized by increasing its capacitance (Step <NUM>), the selected preamplifier still has the least gain after sorting of all of the preamplifiers within the array <NUM>. Where that is the case (YES from Step <NUM>), the preamplifier having the maximum gain is selected and its gain is reduced by reducing its capacitance setting (Step <NUM>), if possible without creating a saturation condition. After every change of gain (Steps <NUM>, <NUM>), a saturation check is done to ensure there is no saturation condition (Steps <NUM> and <NUM>).

The process illustrated in <FIG> may end (Step <NUM>) when all of the preamplifier gains are within a limit (YES from Step <NUM>), gain of the minimum-gain preamplifier cannot be increased and gain of the maximum-gain preamplifier cannot be decreased (Yes from Step <NUM>), or after a programmable number of iterations (in the illustrated example, when m = M). Gain should not be increased if doing so would cause a preamplifier to become saturated. As described above, a saturation check may be performed by confirming that the later-arriving edge of the delay signals OUT_M and OUT_P rises within the active region A across the range of the preamplifier under consideration.

A method of using, or operating, an analog-to-digital converting system is illustrated in <FIG>. The method includes receiving a sampled voltage V corresponding to one of an input voltage VIN and a known voltage VDAC (Step <NUM>). As explained above, the input voltage VIN is selected by the multiplexer <NUM> during an operational phase, while the known voltage VDAC is selected by the multiplexer <NUM> during a calibration phase, under the control of a select signal SEL<NUM>. Further, the method illustrated in <FIG> also includes causing N preamplifiers <NUM>, <NUM> and <NUM> to generate output signals OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT _P<NUM>, OUT_MN and OUT _PN based on the sampled voltage V (Step <NUM>), and generating first and second signals OUT_M and OUT_P based on the output signals OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_MN and OUT _PN (Step <NUM>). In the configuration illustrated in <FIG>, a folding delay multiplexer <NUM> causes the relative timings of the first and second signals OUT_M and OUT_P to correspond to the relative timings of the output signals of the most relevant one of the preamplifiers.

Referring to <FIG>, the illustrated method includes causing a delay-resolving analog-to-digital backend <NUM> to generate a single-bit digital signal (on line <NUM>) representing an order of receipt of the first and second signals OUT_M and OUT_P (Step <NUM>), and adjusting one or more of the preamplifiers <NUM>, <NUM> and <NUM> based on the single-bit digital signal (on line <NUM>) (Step <NUM>). According to one aspect of the present disclosure, the gains and ranges of the preamplifiers <NUM>, <NUM> and <NUM> may be adjusted, and preferably matched across the preamplifier array <NUM>. After the preamplifiers <NUM>, <NUM> and <NUM> have been calibrated, the preamplifiers <NUM>, <NUM> and <NUM> may be adjusted for maximum, or improved, gain, and then corrected for gain mismatch across the array <NUM>, all while avoiding a saturation condition.

As illustrated in <FIG>, by way of example, the preamplifier array <NUM> may have first, second, third, and fourth preamplifiers <NUM>, <NUM>, <NUM> and <NUM> (N = <NUM>; TH<NUM> < TH<NUM> < THN) which generate respective output signals OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_PN and OUT_MN having different timings, and thereby develop delay information representative of the sampled voltage V. The output signals OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_PN and OUT_MN are transmitted on respective conductive lines <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>.

In operation, the delay information developed by the preamplifiers <NUM>, <NUM>, <NUM> and <NUM> is processed by first, second, third, fourth and fifth OR gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM> and first, second, third, fourth and fifth AND gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. The processing causes signals generated by the preamplifiers to be folded into a single pair of signals which contain all of the information of interest. If desired, the folding circuit illustrated in <FIG> may be constructed and operated as shown and described in <CIT>. In the configuration illustrated in <FIG>, the OR gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM> and the AND gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are elements of the folding delay multiplexer <NUM>, and are employed within the folding delay multiplexer <NUM> in the operational phase. The first one of the first output lines <NUM> is connected to inputs of the first OR and AND gates <NUM> and <NUM>, and the first one of the second output lines <NUM> is connected to inputs of the first OR and AND gates <NUM> and <NUM>. In like manner, the first and second output lines <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of the other preamplifiers <NUM>, <NUM> and <NUM> are connected to inputs of the respective second, third and fourth OR and AND gates <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>.

Output signals generated by the first through fourth OR gates <NUM>, <NUM>, <NUM> and <NUM> (on conductive lines <NUM>, <NUM>, <NUM> and <NUM>) are input to the fifth AND gate <NUM>, and output signals generated by the first through fourth AND gates <NUM>, <NUM>, <NUM> and <NUM> (on conductive lines <NUM>, <NUM>, <NUM> and <NUM>) are input to the fifth OR gate <NUM>. In each case, the timing of the output signals generated by the OR gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM> corresponds to the timing of the first signal to arrive at the respective inputs of the OR gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, whereas the timing of the output signals generated by the AND gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM> corresponds to the timing of the last signal to arrive at the respective inputs of the AND gates <NUM>, <NUM>, <NUM>, <NUM> and <NUM>.

In operation, the preamplifier array <NUM> generates preamplifier outputs with early and late rising edges. When the system <NUM> is in the calibration phase, the folding delay multiplexer <NUM> transmits timing signals directly from a desired preamplifier to lines <NUM> and <NUM>, under the control of select signal SEL<NUM> (<FIG>). When the system <NUM> is in the operational mode, the first through fourth OR gates <NUM>, <NUM>, <NUM> and <NUM> select the signals which reach them first (earlier), and generate signals on lines <NUM>, <NUM>, <NUM> and <NUM> with timings which correspond to the selected (earlier-arriving) signals. Meanwhile, the first through fourth AND gates <NUM>, <NUM>, <NUM> and <NUM> select the signals which reach them last (later), and generate signals on lines <NUM>, <NUM>, <NUM> and <NUM> with timings which correspond to the selected (later-arriving) signals.

In the operational phase, the fifth AND gate <NUM> generates a signal (OUT_P) on conductive line <NUM> which preserves the timing of the latest-arriving of the earlier-arriving signals, and the fifth OR gate <NUM> generates a signal (OUT_M) on a conductive line <NUM> which preserves the timing of the earliest-arriving of the later signals. A method of operating the folding circuit illustrated in <FIG> is described in <CIT>. Other folding circuits that may be employed in the system <NUM>, and methods of operating such circuits are also described in <CIT>.

<FIG> illustrates a backend delay-to-digital converter <NUM> for the system <NUM>. In the illustrated configuration, the delay-to-digital converter has three or more stages <NUM>, <NUM> and <NUM>, with respective AND gates <NUM>, <NUM> and <NUM> and delay comparators <NUM>, <NUM> and <NUM>. Please note that the illustrated AND gates are merely examples of logic gates that may be employed according to this disclosure. If desired, this disclosure may be implemented with or without AND gates and/or with or without gates other than AND gates.

In the illustrated configuration, the second and third AND gates <NUM> and <NUM> are essentially identical to the first AND gate <NUM>, and the second and third delay comparators <NUM> and <NUM> are essentially identical to the first delay comparator <NUM>. The conductive output lines <NUM> and <NUM> are both coupled to inputs of the first AND gate <NUM>. A first one of the conductive lines <NUM> is also coupled to a first input <NUM> of the first delay comparator <NUM>, and the second one of the conductive lines <NUM> is coupled to a threshold input <NUM> of the first delay comparator <NUM>.

An output line <NUM> from the first AND gate <NUM> is electrically coupled to one of the inputs of the second AND gate <NUM>, and to the first input <NUM> of the second delay comparator <NUM>. A conductive line <NUM> from the first delay comparator <NUM> is electrically coupled to the other one of the inputs of the second AND gate <NUM>, and to the threshold input <NUM> of the second delay comparator <NUM>. In like manner, an output line <NUM> from the second AND gate <NUM> is electrically coupled to one of the inputs of the third AND gate <NUM>, and to the first input <NUM> of the third delay comparator <NUM>, and a conductive line <NUM> from the second delay comparator <NUM> is electrically coupled to the other one of the inputs of the third AND gate <NUM>, and to the threshold input <NUM> of the third delay comparator <NUM>.

The pattern created by the second and third stages <NUM> and <NUM> may be continued, if desired, for a fourth stage or for as many additional stages as desired. Each successive stage has an AND gate and a delay comparator essentially identical to the AND gates <NUM> and <NUM> and the delay comparators <NUM> and <NUM> of the second and third stages <NUM> and <NUM>, and electrically coupled to the AND gate and delay comparator of a preceding stage in the same way that the third AND gate <NUM> and the third delay comparator <NUM> are electrically coupled to the second AND gate <NUM> and the second delay comparator <NUM>.

In operation, signals AN and BN (where N = <NUM>, <NUM>, <NUM>. for the first, second, third. stages <NUM>, <NUM>, <NUM>. respectively) are applied to respective ones of the AND gates <NUM>, <NUM> and <NUM>, causing the AND gates <NUM>, <NUM> and <NUM> to generate corresponding signals AN+<NUM>. For each one of the AND gates <NUM>, <NUM> and <NUM>, the timing of the leading edge of signal AN+<NUM> tracks the timing of the leading edge of the later-arriving of signals AN and BN.

In particular, for each one of the AND gates <NUM>, <NUM> and <NUM>, the timing of the leading edge of signal AN+<NUM> is equal to the timing of the leading edge of the earlier-arriving of signals AN and BN plus an amount of time (<NUM>, <FIG>) that is related to the extent to which the leading edge of the later-arriving of signals AN and BN lags behind the leading edge of the earlier-arriving of signals AN and BN. In operation, the input signal delay T_IN for a given stage N is the extent to which signal AN lags behind signal BN. The delay <NUM> caused by the respective AND gate (that is, the extent to which the leading edge of the respective signal AN+<NUM> lags behind the leading edge of the earlier-arriving of the corresponding signals AN and BN) is linearly related to the absolute value of the input signal delay T_IN.

Meanwhile, signals AN and BN are also applied to the first inputs <NUM> and threshold inputs <NUM>, respectively, of the delay comparators <NUM>, <NUM> and <NUM>, causing the delay comparators <NUM>, <NUM> and <NUM> to generate corresponding signals BN+<NUM>. For each one of the delay comparators <NUM>, <NUM> and <NUM>, the timing of the leading edge of signal BN+<NUM> tracks the timing of the leading edge of the earlier-arriving of signals AN and BN. In particular, for each one of the delay comparators <NUM>, <NUM> and <NUM>, the timing of the leading edge of signal BN+<NUM> is equal to (<NUM>) the timing of the leading edge of the earlier-arriving of signals AN and BN plus (<NUM>) a delay <NUM> (<FIG>) that is logarithmically inversely related to the absolute value of the input signal delay T_IN.

Subtracting the delay <NUM> generated by the AND gate from the delay <NUM> generated by the comparator yields the output signal delay T_OUT (<FIG>) for any given stage. When the absolute value of the input signal delay T_IN is less than a threshold delay T_THRES, then the output signal delay T_OUT is a positive value (meaning that the leading edge of signal BN+<NUM> generated by the respective delay comparator <NUM>, <NUM> and <NUM> precedes the leading edge of signal AN+<NUM> generated by the respective AND gate <NUM>, <NUM> and <NUM>). On the other hand, when the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, then the output signal delay T_OUT is a negative value (meaning that the leading edge of signal BN+<NUM> lags behind the leading edge of corresponding signal AN+<NUM>).

In operation, the first delay comparator <NUM> issues a first sign signal ("<NUM>" or "<NUM>") on a first digital line <NUM> to the calibration engine/processor. The first sign signal is based on which one of the leading edges of the signals A<NUM> and B<NUM> is first received by the first delay comparator <NUM>, such that the first sign signal reflects the order of the leading edges of signals A<NUM> and B<NUM> applied to the first and threshold inputs <NUM> and <NUM> of the first delay comparator <NUM>. Then, the first AND gate <NUM> and the first delay comparator <NUM> generate signals A<NUM> and B<NUM> which are applied to the AND gate <NUM> and the delay comparator <NUM> of the second stage <NUM>. The second delay comparator <NUM> issues a second sign signal ("<NUM>" or "<NUM>") on a second digital line <NUM> to the calibration engine/processor <NUM>. The second sign signal is based on which one of the leading edges of the signals A<NUM> and B<NUM> is first received by the second delay comparator <NUM>, such that the second sign signal reflects the order of the leading edges of the signals A<NUM> and B<NUM> applied to the inputs <NUM> and <NUM> of the second delay comparator <NUM>.

Then, the second AND gate <NUM> and the second delay comparator <NUM> generate signals A<NUM> and B<NUM> which are applied to the AND gate <NUM> and the delay comparator <NUM> of the third stage <NUM>. The third delay comparator <NUM> issues a third sign signal ("<NUM>" or "<NUM>") on a third digital line <NUM> to the calibration engine/processor <NUM>. The third sign signal is based on which one of the leading edges of the signals A<NUM> and B<NUM> is first received by the third delay comparator <NUM>, such that the third sign signal reflects the order of the leading edges of the signals A<NUM> and B<NUM> applied to the inputs <NUM> and <NUM> of the third delay comparator <NUM>. The pattern may be continued for a fourth stage or for more than four stages, as desired.

Since the delay between signals A<NUM> and B<NUM> can be predicted as a function of the voltage V, and vice versa, and since the delay between the signals AN+<NUM> and BN+<NUM> output to a successive stage can be predicted as a function of the signals AN and BN received by the preceding stage, and vice versa, the sign signals output on lines <NUM>, <NUM> and <NUM> by the delay comparators <NUM>, <NUM> and <NUM> of the cascade of stages <NUM>, <NUM> and <NUM> can be predicted as a function of the voltage V, and vice versa. Therefore, during the operation mode, a code made up of the sign signals may be reliably compared to a predetermined correlation to determine an approximation of the input voltage VIN.

Referring now to <FIG>, the delay comparator <NUM> has a comparator circuit <NUM> which has first, second, third, fourth, fifth, sixth, seventh and eighth transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. The timing of the delay comparator <NUM> is controlled by a signal from a clock applied to the gates of the first and fourth transistors <NUM> and <NUM>, on a conductive line <NUM>. The first and second signals A<NUM> and B<NUM> on lines <NUM> and <NUM> are applied to the gates of the sixth and fifth transistors <NUM> and <NUM>, respectively. The drains of the first, second and fifth transistors <NUM>, <NUM> and <NUM> are electrically connected to each other, and to the gates of the third and eighth transistors <NUM> and <NUM>, via a first conductive line <NUM>. The drains of the third, fourth and sixth transistors <NUM>, <NUM> and <NUM> are likewise electrically connected to each other, and to the gates of the second and seventh transistors <NUM> and <NUM>, via a second conductive line <NUM>.

The first and second conductive lines <NUM> and <NUM> of the comparator circuit <NUM> are electrically connected to a sign-out circuit <NUM> via respective third and fourth conductive lines <NUM> and <NUM>. As illustrated in <FIG>, the sign-out circuit <NUM> is merged with the comparator circuit <NUM>. The sign-out circuit <NUM> has first, second, third, and fourth transistors <NUM>, <NUM>, <NUM> and <NUM>. The third conductive line <NUM> is electrically connected to the gate and the source of the first and second transistors <NUM> and <NUM> of the sign-out circuit <NUM>, respectively, while the fourth conductive line <NUM> is electrically connected to the source and the gate of the first and second transistors <NUM> and <NUM> of the sign-out circuit <NUM>, respectively.

In operation, when the delay comparator <NUM> is enabled by the clock signal on line <NUM>, a sign signal is generated within the sign-out circuit <NUM> on line <NUM>. The sign signal is forwarded to the calibration engine/processor <NUM> on line <NUM>, and represents the order in which the output signals A<NUM> and B<NUM> arrive at the first and threshold inputs <NUM> and <NUM> (<FIG>) of the delay comparator <NUM>. The operation of the sign-out circuit <NUM> is controlled by an inverted clock signal CLKZ applied to the gates of the third and fourth transistors <NUM> and <NUM> of the sign-out circuit <NUM>. The inverted clock signal CLKZ is an inverted version of the clock signal that is applied to the gates of the first and fourth transistors <NUM> and <NUM> of the comparator circuit <NUM> on line <NUM>.

The third and fourth conductive lines <NUM> and <NUM> are also electrically connected to a delay-out circuit <NUM>. As illustrated in <FIG>, the delay-out circuit <NUM> is merged with the comparator circuit <NUM>. The delay-out circuit <NUM> has first, second and third transistors <NUM>, <NUM> and <NUM>. The third conductive line <NUM> is electrically connected to the gate and the source of the first and second transistors <NUM> and <NUM> of the delay-out circuit <NUM>, respectively, while the fourth conductive line <NUM> is electrically connected to the source and the gate of the first and second transistors <NUM> and <NUM> of the delay-out circuit <NUM>, respectively.

In operation, a delay signal B<NUM> is generated on line <NUM>, which is electrically connected to the drains of both of the first and second transistors <NUM> and <NUM> of the delay-out circuit <NUM>. The timing of the leading edge of the delay signal B<NUM> on line <NUM> relative to the timing of the earlier-arriving of the leading edges of the signals A<NUM> and B<NUM> on inputs <NUM> and <NUM> is the comparator delay. The operation of the delay-out circuit <NUM> is controlled by the same inverted clock signal CLKZ that is applied to the third and fourth transistors <NUM> and <NUM> of the sign-out circuit <NUM>. The inverted clock signal CLKZ is applied to the gate of the third transistor <NUM> of the delay-out circuit <NUM>. The drain of the third transistor <NUM> of the delay-out circuit <NUM> is electrically connected to the drains of the first and second transistors <NUM> and <NUM> of the delay-out circuit <NUM>.

A clock-less delay comparator 50A is illustrated in <FIG>. If desired, the clock-less delay comparator 50A may be used in the system <NUM> in place of the delay comparator <NUM> illustrated in <FIG>. The clock-less delay comparator 50A is similar to the delay comparator <NUM> illustrated in <FIG> except that (<NUM>) the clock-less delay comparator 50A has a comparator circuit 2083A which uses the later-arriving of the signals A<NUM>, B<NUM>, applied to the first and threshold inputs <NUM> and <NUM>, instead of the clock signal, and (<NUM>) inverted signals -A<NUM> and -B<NUM> are used to control the operation of a sign-out circuit 2420A and a delay-out circuit 2450A.

As illustrated in <FIG>, the comparator circuit 2083A has first and second extra transistors <NUM> and <NUM>. The first input signal A<NUM> is applied, on the first input line <NUM>, to the gates of the fourth and first-extra transistors <NUM> and <NUM>, and the second input signal B<NUM> is applied, on the threshold input line <NUM>, to the first and second-extra transistors <NUM> and <NUM>. The first and first-extra transistors <NUM> and <NUM> are electrically connected to each other in series, and the fourth and second-extra transistors <NUM> and <NUM> are electrically connected to each other in series. Thus, the clock-less delay comparator 50A is enabled by the arrival of the later-arriving of the two input signals A<NUM> and B<NUM>.

At the same time, the first and second input signals A<NUM> and B<NUM> are applied to respective inverter gates <NUM> and <NUM>, which generate respective inverted signals -A<NUM>, -B<NUM>. The logic levels of the inverted signals -A<NUM>, -B<NUM> are the opposite of those of the respective input signals A<NUM>, B<NUM>. In operation, when the clock-less delay comparator 2083A is enabled, a sign signal is generated within the sign-out circuit 2420A, on line <NUM>. As illustrated in <FIG>, the sign-out circuit 2420A is merged with the comparator circuit 2083A. Similar to the operation of the delay comparator <NUM> illustrated in <FIG>, the sign signal in the <FIG> configuration is forwarded to the calibration engine/processor <NUM> on line <NUM>, and represents the order in which the output signals A<NUM>, B<NUM> arrive at the first and threshold inputs <NUM> and <NUM> of the clock-less delay comparator 50A.

The inverted signals -A<NUM> and -B<NUM> are applied to the third and fourth transistors <NUM> and <NUM> of the sign out circuit 2420A, and to two extra transistors <NUM> and <NUM>. In the illustrated configuration, the first inverted signal -A<NUM> is applied to the fourth and first-extra transistors <NUM> and <NUM> of the sign-out circuit 2420A, and the third and first-extra transistors <NUM> and <NUM> of the sign-out circuit 2420A are electrically connected to each other in series. The second inverted signal -B<NUM> is applied to the third and second-extra transistors <NUM> and <NUM> of the sign-out circuit 2420A, and the fourth and second-extra transistors <NUM> and <NUM> of the sign-out circuit 2420A are electrically connected to each other in series. Thus, the operation of the sign-out circuit 2420A is controlled by both of the inverted signals -A<NUM> and -B<NUM>.

As illustrated in <FIG>, the first and second conductive lines <NUM> and <NUM> of the comparator circuit 2083A are also electrically connected to a delay-out circuit 2450A, via the third and fourth conductive lines <NUM> and <NUM>. The delay-out circuit 2450A is merged within the clock-less delay comparator 50A. The delay-out circuit 2450A has an extra transistor <NUM>. In operation, when the clock-less delay comparator 50A is enabled, a delay signal B<NUM> is generated on line <NUM>. The timing of the leading edge of the delay signal B<NUM> on line <NUM> relative to the timing of the earlier-arriving of the leading edges of the signals A<NUM> and B<NUM> on inputs <NUM> and <NUM> is the comparator delay. The timing of the delay-out circuit 2450A is controlled by both of the inverted signals -A<NUM> and -B<NUM>, which are applied to the third transistor <NUM> and the extra transistor <NUM>. In the <FIG> configuration, the third and extra transistors <NUM> and <NUM> of the delay-out circuit 2450A are connected to each other in series between the drains of the first and second transistors <NUM> and <NUM> of the delay-out circuit 2450A and ground.

Whereas the merged clock-less comparator 50A illustrated in <FIG> has a P barrier configuration, a second merged clock-less comparator 50B illustrated in <FIG> has an N barrier configuration. The second clock-less delay comparator 50B is similar to the clock-less delay comparator 50A illustrated in <FIG> except that (<NUM>) the non-inverted input signals A<NUM> and B<NUM> are used to control the operation of inverted sign-out and inverted delay-out circuits 2420B and 2450B in the second clock-less delay comparator 50B, and (<NUM>) inverter gates <NUM> and <NUM> are used in the <FIG> configuration to generate the non-inverted sign signal on digital line <NUM> and the non-inverted delay signal B<NUM> on line <NUM>.

As illustrated in <FIG>, the inverted sign-out circuit 2420B, which is merged with the comparator circuit 2083B, has first, second, third, fourth, fifth and sixth transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. The sources of the fifth and sixth transistors <NUM>, <NUM> are electrically connected to the third and fourth conductive lines <NUM> and <NUM>, respectively. The gates of the fifth and sixth transistors <NUM> and <NUM> are electrically connected to the fourth and third conductive lines <NUM> and <NUM>, respectively. In operation, an inverted sign signal is generated within the inverted sign-out circuit 2420B, on line 52B.

The inverted sign signal on line 52B is inverted by one of the inverter gates <NUM> to generate the non-inverted sign-out signal on line <NUM>, which is applied to the calibration engine/processor <NUM> (not illustrated in <FIG>). The non-inverted sign-out signal represents the order in which the input signals A<NUM> and B<NUM> arrive at the first and threshold inputs <NUM> and <NUM> of the second clock-less delay comparator 50B. The operation of the inverted sign-out circuit 2420B is controlled by the first and second input signals A<NUM> and B<NUM>, which are applied to the first and fourth transistors <NUM> and <NUM>, and to the second and third transistors <NUM> and <NUM>, respectively, on the first and threshold inputs <NUM> and <NUM>, respectively.

The first and second conductive lines <NUM> and <NUM> are electrically connected to the inverted delay-out circuit 2450B via the third and fourth conductive lines <NUM> and <NUM>, respectively. The inverted delay-out circuit 2450B has first, second, third and fourth transistors <NUM>, <NUM>, <NUM> and <NUM>. In operation, when the second clock-less delay comparator 50B is enabled, an inverted delay signal -B<NUM> is generated on line 55B. The inverted delay signal -B<NUM> is inverted by the second inverter <NUM> to generate the non-inverted delay signal B<NUM>. The timing of the leading edge of the non-inverted delay signal B<NUM> on line <NUM> relative to the timing of the earlier-arriving of the leading edges of the signals A<NUM> and B<NUM> on the comparator inputs <NUM> and <NUM> is the comparator delay.

As illustrated in <FIG>, the sources of the third and fourth transistors <NUM>, <NUM> of the inverted delay-out circuit 2450B are electrically connected to the third and fourth conductive lines <NUM> and <NUM>, respectively. The gates of the third and fourth transistors <NUM> and <NUM> of the inverted delay-out circuit 2450B are electrically connected to the fourth and third conductive lines <NUM> and <NUM>, respectively. The operation of the inverted delay-out circuit 2450B is controlled by both of the input signals A<NUM> and B<NUM>, which are applied to the gates of the second and first transistors <NUM> and <NUM> of the inverted delay-out circuit 2450B. As illustrated in <FIG>, the first and second transistors <NUM> and <NUM> of the inverted delay-out circuit 2450B are electrically connected to each other in series.

The present disclosure describes many advantageous features. Among other things, an algorithm has been described by which gain within two zones of a preamplifier can be normalized. The gain normalization may be performed by changing bulk voltage. Moreover, an iterative method of normalizing gain across the array <NUM>, preferably using current kick to reduce response time, has been described. Moreover, a technique has been described herein for detecting a saturation condition of a voltage-to-delay preamplifier.

An advantageous feature described in this disclosure relates to the use of only a single-bit output to perform all calibration and adjustment processes. Moreover, the present disclosure describes a process for calculating gain of a preamplifier by, among other things, measuring delays of output signals using a delay-locked loop-generated signal. The present disclosure also describes a method of maximizing gains of preamplifiers by a combination of current adjustment and capacitance adjustment.

The analog-to-digital converter system <NUM> described herein may be incorporated into a radio-frequency sampling analog-to-digital converter with high operational speed and performance, and low power usage. The system <NUM> may be incorporated into a highly integrated radio-frequency sampling based transceiver for use in wireless infrastructure, especially for higher bandwidth multi-band applications. Among other things, devices constructed in accordance with the present disclosure may have low power consumption and small area requirements.

In general, it is possible to reduce non-linearity in certain devices by over-designing the devices. However, the over-design approach tends to undesirably increase area and power requirements, sometimes drastically, especially to accommodate a wide range of temperatures. And over-designing may not be scalable at lower process nodes, since the analog domain at such nodes tends to be more non-linear. Moreover, in general, it may be possible to perform calibration using a factory trim process. However, it may be difficult to trim later stages of an analog-to-digital device where such stages operate in a highly non-linear manner. It may not be possible to track changes, especially in the later stages, as needed for a factory trim process.

The present disclosure represents an improvement over the concept of reducing non-linearity by over-design, because over-design may increase area and power drastically to support wider temperature, and is not scalable at lower process nodes where analog processing is more non-linear. Methods performed in connection with the present disclosure may also represent an improvement over factory-trimming processes, which may still require over-design since trimming is not accurate and cannot track temperature.

Claim 1:
A method of using an analog-to-digital converter system (<NUM>), comprising:
receiving (<NUM>) a sampled voltage (V) corresponding to one of an input voltage (Vin) and a known voltage (VDAC);
causing (<NUM>) preamplifiers (<NUM>, <NUM>, <NUM>) to generate output signals (OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_MN, OUT _PN) based on differences between the sampled voltage (V) and different threshold voltages (TH<NUM>, TH<NUM>, THN) applied to the preamplifiers (<NUM>, <NUM>, <NUM>);
generating (<NUM>) first and second delay signals (OUT_M, OUT_P) based on the output signals (OUT_M<NUM>, OUT_P<NUM>, OUT_M<NUM>, OUT_P<NUM>, OUT_MN, OUT_PN) using a folding delay multiplexer, the first and second delay signals (OUT_M, OUT_P) corresponding to the output signals of that preamplifier of the preamplifiers (<NUM>, <NUM>, <NUM>) whose threshold voltage is closest to the sampled voltage (V);
causing (<NUM>) a delay comparator (<NUM>) of a delay-resolving delay-to-digital backend (<NUM>) to generate a single-bit digital signal representing an order of receipt of the first and second delay signals (OUT_M, OUT_P);
adjusting (<NUM>) one or more of the preamplifiers (<NUM>, <NUM>, <NUM>) based on the single-bit digital signal; and
the step of using a delay-locked loop, DLL, line (<NUM>) to apply delay signals of different values to the delay comparator (<NUM>) to measure gain of the preamplifiers (<NUM>, <NUM>, <NUM>).