Patent Description:
<CIT> discloses a smart IC module according to the preamble of claim <NUM>. <CIT> discloses a chip card module for a chip card. The chip card module includes a carrier with a first side and an opposite second side, a chip arranged over the first side of the carrier and an antenna arranged over the carrier. <CIT> discloses a process for producing an electronic module. A single-sided film consists of contact zones and a dielectric comprises openings. <CIT> discloses a method for producing a flexible circuit for a chip card module. Conductive pads are used, which are located on the same face of the module as the contacts intended to establish a connection with a card reader, in order to produce an electrical connection between an antenna and an electronic chip. The connections with conductive pads are located partly inside an encapsulation area and partly outside said encapsulation area and respectively to either side of same. An IC card may be formed by combining a smart IC module and a card module.

The smart IC module is a substrate on which an IC that stores personal security information required for electronic residence cards, credit card USIMs, etc. is mounted and may serve to transmit the corresponding information to a reader in a form of an electrical signal.

The smart IC module may be classified into a single type and a dual type according to a structure of the substrate and may be classified into contact, contactless, hybrid, and combi cards according to a form of a card used.

In detail, the contact smart IC module uses a method of transmitting and receiving information by physical contact, and the contactless smart IC module uses a method of transmitting and receiving information without physical contact using an NFC (traffic card, etc.) function, and the combi smart IC module and the hybrid smart IC module use a method that includes both the physical contact function and the NFC function without physical contact.

Meanwhile, recently, the combi card or the hybrid IC card to which the NFC function is applied has been widely used.

In order to implement the NFC function in the IC card, a signal exchange between the card module and the smart IC module should be performed. To this end, antennas may be disposed in each of the card module and the smart IC module, and the NFC function may be implemented by exchanging signals between the antennas disposed in the card module and the smart IC module.

In the related art, in order to place the antenna in the smart IC module, a separate antenna sheet including the antenna is inserted into the IC card, and the antenna sheet and the smart IC module are electrically connected by a flip chip method using a conductive adhesive or the like.

However, an antenna function of the smart IC module may be deteriorated due to a poor adhesion between the smart IC module and the antenna sheet, and accordingly, NFC characteristics of the IC card may be deteriorated.

In addition, when the antenna is directly disposed on the smart IC module, there may be a problem that an adhesive region for the smart IC module to be adhered to the card module is reduced due to arrangement of the antenna. In addition, after connecting the chip of the smart IC module and the antenna, there is a problem that the adhesive region of the smart IC module is reduced due to a molding member for protecting a connection region.

Therefore, there are required a smart IC substrate, a smart IC module, and an IC card including the same having a new structure capable of solving the above problems.

An embodiment is directed to providing a smart IC substrate, a smart IC module, and an IC card including the same, which may be easily adhered to the smart IC module and a card module and have improved adhesion.

A smart IC module according to an embodiment can include a coil pattern for transmitting and receiving radio frequencies.

In this case, a position of a molding member due to the connection between the coil pattern and a chip can be disposed inside the coil pattern by connecting both the coil pattern and the chip inside the coil pattern.

Therefore, it is possible to prevent an adhesive region of the smart IC module due to the molding member from being reduced. In detail, the smart IC module is combined in an opening region of a card module to form an IC card, and in this case, the smart IC module can be adhered to the card module by applying an adhesive to an edge of a substrate.

At this time, since the coil pattern is disposed on the edge of the substrate, when the molding member extends to the outside of the coil pattern, the adhesive region on the substrate is reduced, so that the smart IC module and the card module may not be easily adhered, and adhesion may be deteriorated due to the reduction of the adhesive region.

Therefore, the smart IC module according to the embodiment forms a bending region bent in a chip direction on the coil pattern, thereby increasing the adhesive region of the smart IC module.

In addition, since the smart IC module according to the embodiment connects a wire for wire bonding of the coil pattern and the chip inside the coil pattern through a connection circuit pattern and a connection member disposed on a via of the connection circuit pattern, it is possible to prevent the molding member for protecting the wire from passing to the outside of the coil pattern.

Accordingly, since the smart IC module according to the embodiment can secure the adhesive region combined to the card module with a sufficient size, the smart IC module and the card module can be easily adhered, and the adhesion can be improved by increasing the adhesive region.

In addition, the smart IC module according to the embodiment does not directly wire-bond the chip and a second terminal of the coil pattern, and the smart IC module connects by wire bonding in a region closer to the chip than the second terminal through the connection member, thereby reducing the arrangement area of the molding member.

Therefore, since it is not necessary to dispose the molding member up to the second terminal disposed on the edge of the substrate, the smart IC module and the card module can be easily adhered through the edge of the substrate.

In addition, unless expressly otherwise defined and described, the terms used in the embodiments of the present invention (including technical and scientific terms) may be construed the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and the terms such as those defined in commonly used dictionaries may be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art.

Hereinafter, a smart IC substrate, a smart IC module, and an IC card including the same according to an embodiment will be described with reference to the drawings.

<FIG> and <FIG> are views showing top views of a first surface and a second surface of the smart IC substrate according to the embodiment.

Referring to <FIG> and <FIG>, a smart IC substrate <NUM> may include a first surface <NUM> and a second surface <NUM> opposite to the first surface. A chip may be mounted on the smart IC substrate <NUM> to form a smart IC module. The first surface <NUM> may be a contact side of the smart IC substrate <NUM>. In addition, the second surface <NUM> may be a bonding side of the smart IC substrate <NUM>.

That is, the first surface <NUM> may be a surface capable of recognizing information of the smart IC module through direct or indirect contact with the IC card, and the second surface <NUM> may be a surface adhered to a card module <NUM>.

Referring to <FIG>, a circuit pattern <NUM> and a connection circuit pattern <NUM> are disposed on the first surface <NUM>. In detail, a plurality of circuit patterns <NUM> disposed on the substrate <NUM> and spaced apart from each other and the connection circuit pattern <NUM> spaced apart from the circuit pattern <NUM> may be disposed on the first surface <NUM>.

In addition, referring to <FIG>, a coil pattern <NUM> may be disposed on the second surface <NUM>. In detail, the coil pattern <NUM> disposed on the substrate <NUM> may be disposed on the second surface <NUM>.

In addition, a plurality of vias V may be formed on the second surface <NUM>. In detail, the via V may be disposed at a position corresponding to each of the plurality of circuit patterns <NUM> and the connection circuit pattern <NUM> disposed on the first surface <NUM>.

In addition, the second surface <NUM> may include a chip mounting region CSA in which a chip connected to the circuit pattern <NUM>, the connection circuit pattern <NUM>, and the coil pattern <NUM> is disposed. That is, the chip may be disposed on the second surface <NUM>, and the chip may be disposed on the chip mounting region CSA.

<FIG> is a view showing a top view of a second surface of a smart IC substrate in which a chip is not disposed in a chip mounting region, and <FIG> is a view showing a top view of a second surface of a smart IC module in which the chip is disposed in the chip mounting region.

Referring to <FIG> and <FIG>, the circuit pattern <NUM> and the chip <NUM> may be connected. In detail, a first via V1 may be formed on a region of the substrate <NUM> corresponding to the circuit pattern <NUM>, and the chip <NUM> may be electrically connected to the circuit pattern <NUM> exposed through the first via V1 by bonding of a wire <NUM>. That is, the first via V1 may be defined as a via for connecting the chip <NUM> and the circuit pattern <NUM>.

In addition, the coil pattern <NUM> and the chip <NUM> may be connected. In detail, the coil pattern <NUM> may include a coil pad portion. In detail, a first terminal <NUM> of the coil pattern <NUM> may be connected to a first coil pad portion <NUM>, and a second terminal <NUM> of the coil pattern <NUM> may be connected to a second coil pad portion <NUM>.

The first coil pad portion <NUM> may be a part of a fourth layer to be described below. That is, the fourth layer may be used as it is without forming the first coil pad portion <NUM> through a separate process. In this case, the fourth layer may be formed through plating.

In addition, the second coil pad portion <NUM> may be a part of a connection member <NUM> to be described below. That is, a part of the connection member <NUM> may be used as it is without forming the second coil pad portion <NUM> through a separate process. That is, the second coil pad portion <NUM> may be integrally formed with the connection member <NUM>. In this case, a width of the second coil pad portion <NUM> may be greater than a width of the second via V2.

The coil pattern <NUM> may be electrically connected to the chip <NUM> through the coil pad portion.

For example, the coil pattern <NUM> may be connected to the chip <NUM> through wire bonding. In this case, any one of the first coil pad portion <NUM> and the second coil pad portion <NUM> of the coil pattern <NUM> may not be directly bonded to the wire <NUM> and may be indirectly connected with the wire <NUM>.

Accordingly, when the smart IC module is adhered to the card module, an adhesive region of the smart IC module may be secured wide. The connection between the coil pattern <NUM> and the chip <NUM> will be described in detail below.

Hereinafter, the connection between the circuit pattern and the chip and the connection between the coil pattern and the chip of the smart IC module according to an embodiment will be described in detail with reference to <FIG>.

<FIG> is a cross-sectional view taken along line A-A' of <FIG> and is a cross-sectional view of a connection region between the circuit pattern <NUM> and the chip <NUM>.

Referring to <FIG>, the smart IC module may include the substrate <NUM>. The substrate <NUM> may be an insulating substrate. The substrate <NUM> may include a resin material. The substrate <NUM> may include one surface <NUM> and the other surface <NUM>. The one surface <NUM> may be defined as a surface corresponding to the first surface <NUM> of the smart IC substrate or module described above, and the other surface <NUM> may be defined as a surface corresponding to the second surface <NUM> of the smart IC substrate or module described above.

The substrate <NUM> may include prepreg including glass fiber. In detail, the substrate <NUM> may include an epoxy resin and a material in which glass fiber and a silicon-based filler are dispersed in the epoxy resin.

In addition, the substrate <NUM> may be rigid or flexible. For example, the substrate <NUM> may include glass or plastic. In detail, the substrate <NUM> may include a chemically tempered/semi-tempered glass, such as soda lime glass, aluminosilicate glass, etc., a tempered or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc., or sapphire.

In addition, the substrate <NUM> may include a photoisotropic film. For example, the substrate <NUM> may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), photoisotropic polycarbonate (PC), photoisotropic polymethyl methacrylate (PMMA), or the like.

Further, the substrate <NUM> may be partially bent while having a curved surface. That is, the substrate <NUM> may partially have a plane and may partially be bent while having a curved surface. In detail, an end portion of the substrate <NUM> may be bent while having a curved surface or may be bent or crooked while having a surface with a random curvature.

Furthermore, the substrate <NUM> may be a flexible substrate having flexibility. Also, the substrate <NUM> may be a curved or bent substrate.

An adhesive layer <NUM> may be disposed on the one surface <NUM> and the other surface <NUM> of the substrate <NUM>. The adhesive layer <NUM> may be disposed on the entire surface of the one surface and the other surface of the substrate <NUM>. In detail, the adhesive layer <NUM> may be disposed on the entire surface of the one surface and the other surface of the substrate except for a via-formed region.

The adhesive layer <NUM> may include a resin material. For example, the adhesive layer <NUM> may include at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the adhesive layer <NUM> may further include additives such as natural rubber, a plasticizer, a hardner, a phosphorus-based flame retardant, and the like in order to impart flexibility to the adhesive layer <NUM>.

A circuit pattern <NUM> may be disposed on the one surface <NUM> of the substrate <NUM>. The circuit pattern <NUM> may be disposed on the adhesive layer <NUM> on the substrate <NUM>. The circuit pattern <NUM> may be formed by depositing a metal material on the adhesive layer <NUM> and then patterning the metal material by exposure, development, and etching processes.

The circuit pattern <NUM> may include multiple layers. For example, the circuit pattern <NUM> may include a first layer <NUM> and a second layer <NUM> on the first layer <NUM>.

The first layer <NUM> may include a metal material having high electrical conductivity. For example, the first layer <NUM> may include at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first layer <NUM> may include copper (Cu).

The second layer <NUM> may be disposed on the first layer <NUM>. The second layer <NUM> may be disposed on the first layer <NUM> to protect the first layer <NUM>. That is, the second layer <NUM> may be disposed on the first layer <NUM> to prevent corrosion of the first layer <NUM>. That is, the second layer <NUM> may be a protective layer of the circuit pattern <NUM>.

The second layer <NUM> may include nickel-gold (Ni-Au) or nickel-lead (Ni-Pd), but the embodiment is not limited thereto. For example, the second layer <NUM> may be formed by forming a nickel layer on the first layer <NUM> and then disposing a gold layer on the nickel layer or by forming the nickel layer on the first layer <NUM> and then disposing a lead layer on the nickel layer. In this case, a nickel-gold alloy layer may be formed between the nickel layer and the gold layer, and a nickel-lead alloy layer may be formed between the nickel layer and the lead layer.

The second layer <NUM> may implement various colors depending on the type of material to give a color to the contact side of the smart IC module.

The first layer <NUM>, the second layer <NUM>, and the adhesive layer <NUM> may have different thicknesses.

In detail, the thickness of the first layer <NUM> may be greater than the thickness of the second layer <NUM> and the thickness of the adhesive layer <NUM>. Also, the thickness of the adhesive layer <NUM> may be greater than the thickness of the second layer <NUM>.

For example, the thickness of the first layer <NUM> may be <NUM> to <NUM>, the thickness of the second layer <NUM> may be <NUM> or less, and the thickness of the adhesive layer <NUM> may be <NUM> to <NUM>.

The coil pattern <NUM> may be disposed on the other surface <NUM> of the substrate <NUM>. The coil pattern <NUM> may be disposed on the adhesive layer <NUM> on the other surface <NUM> of the substrate <NUM>.

The coil pattern <NUM> may be formed by depositing a metal material on the adhesive layer <NUM> and then patterning the metal material by exposure, development, and etching processes.

The coil pattern <NUM> may include multiple layers. For example, the coil pattern <NUM> may include a third layer <NUM> and a fourth layer <NUM> on the third layer <NUM>.

The third layer <NUM> may include a metal material having high electrical conductivity. For example, the third layer <NUM> may include a material the same as or similar to that of the first layer <NUM> described above. For example, the third layer <NUM> may include at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the third layer <NUM> may include copper (Cu).

The fourth layer <NUM> may be disposed on the third layer <NUM>. The fourth layer <NUM> may be disposed on the third layer <NUM> to protect the third layer <NUM>. That is, the fourth layer <NUM> may be disposed on the third layer <NUM> to prevent corrosion of the third layer <NUM>. That is, the fourth layer <NUM> may be a protective layer of the coil pattern <NUM>.

The fourth layer <NUM> may include a material the same as or similar to that of the second layer <NUM> described above. For example, the fourth layer <NUM> may include nickel-gold (Ni-Au) or nickel-lead (Ni-Pd), but the embodiment is not limited thereto. For example, the fourth layer <NUM> may be formed by forming a nickel layer on the third layer <NUM> and then disposing a gold layer on the nickel layer or by forming the nickel layer on the third layer <NUM> and then disposing a lead layer on the nickel layer. In this case, a nickel-gold alloy layer may be formed between the nickel layer and the gold layer, and a nickel-lead alloy layer may be formed between the nickel layer and the lead layer.

The fourth layer <NUM> may implement various colors depending on the type of material to give a color to the contact side of the smart IC module.

The third layer <NUM>, the fourth layer <NUM>, and the adhesive layer <NUM> may have different thicknesses.

In detail, the thickness of the third layer <NUM> may be greater than the thickness of the fourth layer <NUM> and the thickness of the adhesive layer <NUM>. Also, the thickness of the adhesive layer <NUM> may be greater than the thickness of the fourth layer <NUM>.

For example, the thickness of the third layer <NUM> may be <NUM> to <NUM>, the thickness of the fourth body <NUM> may be <NUM> or less, and the thickness of the adhesive layer <NUM> may be <NUM> to <NUM>.

Meanwhile, the fourth layer <NUM> may also be disposed on the circuit pattern <NUM> through the first via V1. In detail, the second layer <NUM> may be disposed on one surface of the circuit pattern <NUM> exposed through the first via V1, and the fourth layer <NUM> may be disposed on the other surface.

Accordingly, a circuit pad portion <NUM> formed by the fourth layer may be disposed on the other surface of the circuit pattern <NUM> exposed through the first via V1.

Each of the plurality of circuit patterns <NUM> may be connected to the chip <NUM>. In detail, the circuit pattern <NUM> may be electrically connected to the chip <NUM> by a wire bonding method.

Referring to <FIG> and <FIG>, the first via V1 may be formed on the substrate <NUM> and the adhesive layer <NUM> to connect the circuit patterns <NUM> and the chip <NUM>. That is, the first via V1 may be formed by removing the other surface <NUM> of the substrate <NUM> in a region corresponding to the circuit pattern <NUM> to be connected to the chip <NUM> and the adhesive layer <NUM> on the other surface <NUM>. That is, the first via V1 may be formed on a region corresponding to each of the plurality of circuit patterns <NUM> disposed on one surface <NUM> of the substrate <NUM>.

Accordingly, the circuit pattern <NUM> may be exposed through the first via V1. The chip <NUM> may be wire-bonded to the circuit pad portion <NUM> of the circuit pattern <NUM> exposed through the first via V1 by the wire <NUM>. Subsequently, a molding member for protecting the wire bonding may be formed on the wire <NUM>.

Accordingly, the plurality of circuit patterns <NUM> may be respectively connected to the chip <NUM> by wire bonding, whereby the plurality of circuit patterns <NUM> may be electrically connected to the chip <NUM>.

<FIG> are cross-sectional views for describing the connection between the coil pattern <NUM> and the chip <NUM>.

<FIG> is a cross-sectional view taken along line B-B' of <FIG> and is a cross-sectional view of a connection region between the coil pattern <NUM> and the chip <NUM>.

Referring to <FIG>, the coil pattern <NUM> may be electrically connected to the first terminal <NUM> and the second terminal <NUM>. The first terminal <NUM> may be a terminal connected to one end portion of the coil pattern <NUM>, and the second terminal <NUM> may be a terminal connected to the other end portion of the coil pattern <NUM>.

The coil pattern <NUM> may be formed in a loop shape as a whole while extending from the first terminal <NUM> to the second terminal <NUM>.

Accordingly, the other surface <NUM> of the substrate <NUM> on which the coil pattern <NUM> is disposed may include a first region 1A defined inside a loop of the coil pattern <NUM> and a second region 2A defined outside the loop of the coil pattern <NUM>. That is, the first region 1A may be a region surrounded by the coil pattern <NUM>, and the second region 2A may be an external region of the coil pattern <NUM>.

The chip mounting region CSA may be disposed in the first region 1A. That is, the chip <NUM> disposed in the chip mounting region CSA may be disposed surrounded by the coil pattern <NUM>.

In addition, the first terminal <NUM> may be disposed in the first region 1A, and the second terminal <NUM> may be disposed in the second region 2A. That is, the first terminal <NUM> and the second terminal <NUM> may be disposed in different regions based on the loop-shaped coil pattern <NUM>.

In addition, the first via V1 may be disposed in the same region as the first terminal <NUM>. In detail, both the first via V1 and the first terminal <NUM> may be disposed in the first region 1A.

The coil pattern <NUM> may include at least one bending region CA. In detail, the coil pattern <NUM> may include a first bending region CA1 and a second bending region CA2. The first bending region CA1 may be disposed in a corner region of the coil pattern <NUM>. The coil pattern <NUM> may be disposed in a loop shape by the first bending regions CA1.

The second bending region CA2 may be disposed between the first bending regions CA1. The second bending region CA2 may be a region in which the coil pattern <NUM> is bent in a convex shape so as to be close in a direction of the chip mounting region CSA or the chip <NUM>.

<FIG> illustrate that the coil pattern <NUM> includes only one second bending region CA2, but the embodiment is not limited thereto, and the coil pattern <NUM> may include a plurality of second bending regions.

The second bending region CA2 may be bent in a convex shape. In detail, the second bending region CA2 may be formed in the convex shape bent in the direction of the chip mounting region CSA or the chip <NUM>. Accordingly, the second bending region CA2 of the coil pattern <NUM> may be disposed closer to the chip mounting region CSA or the chip <NUM> than other regions that are not bent.

A length of the coil pattern <NUM> may be increased by the second bending region CA2. Accordingly, as the length of the coil pattern increases, it is possible to improve sensing characteristics of surrounding radio frequency signals when the IC card is used.

Referring to <FIG> and <FIG>, the first terminal <NUM> of the coil pattern <NUM> may be connected to the chip <NUM>. In detail, the first terminal <NUM> may be connected to the first coil pad portion <NUM>, and the chip <NUM> and the first coil pad portion <NUM> may be wire-bonded by the wire <NUM> to be electrically connected.

The first coil pad portion <NUM> may include a material the same as or similar to that of the fourth layer <NUM> described above.

Alternatively, as described above, the first coil pad portion <NUM> may be omitted, and the wire <NUM> may be bonded to the fourth layer <NUM> to be electrically connected.

Subsequently, the molding member for protecting the wire bonding may be formed on the wire <NUM>. Accordingly, the chip <NUM> and the first terminal <NUM> may be directly connected.

Meanwhile, the second terminal <NUM> of the coil pattern <NUM> should also be connected to the chip <NUM>. At this time, when the second terminal <NUM> disposed on the second region 2A, that is, the outside of the coil pattern <NUM> is directly connected to the chip <NUM> by the wire, the adhesive region of the smart IC module may not be sufficiently secured by the molding member formed for protecting the wire bonding after the connection.

Accordingly, in the smart IC module according to the embodiment, the second terminal <NUM> of the coil pattern is indirectly connected to the chip <NUM> to solve the above problem.

<FIG> is a cross-sectional view taken along line C-C' of <FIG>, and <FIG> is a cross-sectional view taken from the second terminal of the coil pattern in the direction of the chip <NUM>.

Referring to <FIG> and <FIG>, the connection circuit pattern <NUM> may be disposed on one surface of the substrate <NUM>, and the coil pattern <NUM> may be disposed on the other surface of the substrate <NUM>. In detail, the second terminal <NUM> of the coil pattern <NUM> may be disposed on the other surface of the substrate <NUM>.

That is, the second terminal <NUM> may be disposed on a region overlapping the connection circuit pattern <NUM>.

The connection circuit pattern <NUM> among the plurality of circuit patterns disposed on one surface of the substrate <NUM> may be a circuit pattern for indirectly connecting the second terminal <NUM> of the coil pattern <NUM> and the chip <NUM>.

The connection circuit pattern <NUM> may be disposed in the first region 1A and the second region 2A. In detail, the connection circuit pattern <NUM> may extend toward the second region 2A from the first region 1A. That is, the connection circuit pattern of the first region 1A and the connection circuit pattern of the second region 2A may be integrally formed.

In addition, the second via V2 may be formed on the substrate <NUM>. In detail, the second via V2 formed by removing the other surface <NUM> of the substrate <NUM> and the adhesive layer <NUM> on the other surface <NUM> may be formed in the substrate <NUM> adjacent to the second terminal <NUM>. Accordingly, the connection circuit pattern <NUM> disposed on one surface of the substrate <NUM> may be exposed through the second via V2. That is, the second via V2 may be formed on a region corresponding to the connection circuit pattern <NUM> of the second region 2A, and the connection circuit pattern <NUM> of the second region 2A may be exposed by the second via V2.

The second via V2 may be disposed in a region different from that of the first via V1. In detail, the second via V2 may be disposed in the second region 2A, and the first via V1 may be disposed in the first region 1A. That is, the first via V1 may be disposed inside the coil pattern <NUM>, and the second via V2 may be disposed outside the coil pattern <NUM>.

The connection member <NUM> is disposed inside the second via V2. In detail, the connection member <NUM> connecting the connection circuit pattern <NUM> and the coil pattern <NUM> are disposed inside the second via V2.

The connection member <NUM> includes a conductive material. In detail, the connection member <NUM> includes a conductive paste. For example, the connection member <NUM> may include a conductive paste including a conductive material of at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), and as the conductive paste is cured after filling the second via V2, the connection member <NUM> may be disposed inside the second via V2.

Accordingly, the connection circuit pattern <NUM> and the second terminal <NUM> of the coil pattern are connected to each other by the connection member <NUM>.

In detail, the second terminal <NUM> of the coil pattern may be connected to the second coil pad portion <NUM>, and the connection member <NUM> may be connected to the second coil pad portion <NUM>. Accordingly, the connection member <NUM> may be connected to the connection circuit pattern <NUM> and the second coil pad portion <NUM>. The second coil pad portion <NUM> may include the same material as the connection member <NUM>. Alternatively, the second coil pad portion <NUM> may include a material the same as or similar to that of the fourth layer <NUM>.

Referring to <FIG>, the connection circuit pattern <NUM> may be disposed on one surface of the substrate <NUM>, and the coil pattern <NUM> may be disposed on the other surface of the substrate <NUM>.

A third via V3 may be formed in the substrate <NUM>. In detail, the third via V3 formed by removing the other surface <NUM> of the substrate <NUM> and the adhesive layer <NUM> on the other surface <NUM> may be formed in the substrate <NUM> of a region corresponding to the connection circuit pattern <NUM> of the first region 1A. That is, the third via V3 may be formed on the region corresponding to the connection circuit pattern <NUM> of the first region 1A, and the connection circuit pattern <NUM> of the first region 1A may be exposed by the third via V3. Accordingly, the connection circuit pattern <NUM> disposed on one surface of the substrate <NUM> may be exposed through the third via V3.

The third via V3 may be disposed in the same region as the first via V1. In detail, the first via V1 and the third via V3 may be disposed in the first region 1A. That is, the first via V1 and the third via V3 may be disposed inside the coil pattern <NUM>.

In addition, a distance d1 between the chip <NUM> and the second via V2 may be different from a distance d2 between the chip <NUM> and the third via V3.

For example, the distance d1 between the chip <NUM> and the second via V2 may be greater than the distance d2 between the chip and the third via V3.

Through this, the smart IC module may be efficiently mounted when mounting on the smart card, and a thickness of a region occupied by the smart IC module in the smart card may be reduced, thereby reducing the overall thickness of the smart card.

The chip <NUM> and the connection circuit pattern <NUM> may be electrically connected to each other. In detail, a connection circuit pad portion <NUM> may be disposed on the connection circuit pattern <NUM> exposed through the third via V3, and the chip <NUM> and the connection circuit pad portion <NUM> may be wire-bonded by the wire <NUM> to be electrically connected. That is, the third via V3 may be defined as a via for connecting the chip <NUM> and the connection circuit pattern <NUM>.

Accordingly, the chip <NUM> and the second terminal <NUM> may be electrically connected. That is, the chip <NUM> and the second terminal <NUM> may be indirectly connected. That is, the chip <NUM> may be not wire-bonded to the second terminal <NUM> and may be electrically connected to the second terminal <NUM> by the wire <NUM>, the connection circuit pattern <NUM>, and the connection member <NUM>.

Accordingly, the chip <NUM> and the coil pattern <NUM> may be connected to the coil pattern <NUM> by wire bonding in the first region 1A, that is, inside the coil pattern <NUM>. That is, the first terminal <NUM> may be directly connected to the chip <NUM> by wire bonding, and the second terminal <NUM> may be indirectly connected to the chip <NUM> through the wire, the connection circuit pattern <NUM>, and the connection member <NUM>.

Therefore, after wire bonding the chip <NUM> and the coil pattern <NUM>, the molding member for protecting the wire and the wire connection region may be formed only in the first region 1A and may not be formed in the second region 2A.

Accordingly, since the molding member is not formed in the second region 2A where the adhesive region of the smart IC module is positioned, it is possible to prevent the adhesive region of the smart IC module from being decreased by the molding member.

The smart IC module according to the embodiment may include a coil pattern for transmitting and receiving radio frequencies.

In this case, a position of the molding member due to the connection between the coil pattern and the chip may be disposed inside the coil pattern by connecting both the coil pattern and the chip inside the coil pattern.

Therefore, it is possible to prevent the adhesive region of the smart IC module due to the molding member from being reduced. In detail, the smart IC module is combined in an opening region of the card module to form the IC card, and in this case, the smart IC module may be adhered to the card module by applying an adhesive to an edge of the substrate.

Therefore, the smart IC module according to the embodiment forms the bending region bent in a chip direction on the coil pattern, thereby increasing the adhesive region of the smart IC module.

In addition, since the smart IC module according to the embodiment connects both wire bonding of the coil pattern and the chip inside the coil pattern through the connection circuit pattern and the connection member disposed on the via of the connection circuit pattern, it is possible to prevent the molding member for protecting the wire from passing to the outside of the coil pattern.

Accordingly, since the smart IC module according to the embodiment may secure the adhesive region combined to the card module with a sufficient size, the smart IC module and the card module may be easily adhered, and the adhesion may be improved by increasing the adhesive region.

In addition, even though a distance between the second terminal of the coil pattern and the chip is increased, a wire length is not increased by wire bonding with the chip, and thus, when forming the coil pattern, it is possible to reduce the restriction on design freedom due to the distance from the chip.

Hereinafter, a smart IC module according to another embodiment will be described with reference to <FIG>.

In the description of the smart IC module according to another embodiment, descriptions the same as or similar to those of the smart IC module according to the above-described embodiment are omitted, and the same reference numerals are given to the same components.

Referring to <FIG>, the smart IC module according to another embodiment may include a molding member <NUM>.

The molding member <NUM> may be disposed while surrounding a connection region of the chip <NUM>, the circuit pattern <NUM> connected through the chip <NUM> and the wire <NUM>, and the coil pattern <NUM>. That is, the molding member <NUM> may be disposed on the other surface <NUM> of the substrate.

<FIG> illustrates that the molding member <NUM> is disposed up to a position where the coil pattern <NUM> partially overlaps the second bending region CA2, but the embodiment is not limited thereto, and the molding member <NUM> may also be formed while having a bending region so as not to overlap the second bending region CA2.

Referring to <FIG> and <FIG>, the molding member <NUM> may be disposed while surrounding the chip <NUM>, the wire <NUM>, and the first via V1.

That is, the first via V1 may be disposed at a position overlapping the molding member <NUM>. That is, the first via V1 may be surrounded by the molding member <NUM>.

Accordingly, the wire connecting the circuit pattern <NUM> and the chip <NUM> may be protected by the molding member <NUM>.

Referring to <FIG> and <FIG>, the molding member <NUM> may be disposed while partially surrounding the chip <NUM>, the wire <NUM>, and the coil pattern <NUM>.

That is, the first terminal <NUM> of the coil pattern <NUM> may be disposed at a position overlapping the molding member <NUM>. That is, the first terminal <NUM> may be surrounded by the molding member <NUM>.

Accordingly, the wire <NUM> connecting the first terminal <NUM> of the coil pattern <NUM> and the chip <NUM> may be protected by the molding member <NUM>.

Referring to <FIG> and <FIG>, the molding member <NUM> may be disposed while surrounding the chip <NUM> and the wire <NUM>.

The molding member <NUM> may be disposed on a partial region of the smart IC module. Accordingly, the substrate <NUM> may include a third region 3A where the molding member <NUM> is not disposed and a fourth region 4A where the molding member <NUM> is disposed.

The second via V2 may be disposed at a position that does not overlap the molding member <NUM>, and the third via V3 may be disposed at a position that overlaps the molding member <NUM>. That is, the second via V2 may be disposed outside the molding member <NUM>, and the third via V3 may be disposed inside the molding member <NUM>. That is, the second via V2 may be disposed on the third region 3A, and the third via V3 may be disposed on the fourth region 4A.

That is, the connection circuit pattern <NUM> may extend toward the inside of the molding member from the outside of the molding member, the second via V2 may be formed in a region corresponding to the connection circuit pattern outside the molding member <NUM>, and the third via V3 may be formed in a region corresponding to the connection circuit pattern inside the molding member <NUM>.

In other words, the connection circuit pattern <NUM> may extend toward the fourth region 4A from the third region 3A, the second via V2 may be formed on a region corresponding to the connection circuit pattern on the third region 3A, and the third via V3 may be formed on a region corresponding to the connection circuit pattern on and the fourth region 4A.

Accordingly, a plurality of coil patterns may be disposed between the second via V2 and the fourth region 4A. Alternatively, the plurality of coil patterns may be disposed between the second terminal <NUM> and the fourth region 4A.

That is, at least a part of the coil pattern <NUM> may be disposed in the third region 3A. That is, at least a part of the coil pattern <NUM> may be disposed in the third region 3A, and another part may be disposed in the fourth region 4A.

In addition, a part of the second bending region CA2 may be disposed in the third region 3A. That is, a part of the second bending region CA2 may be disposed in the third region 3A, and another part may be disposed in the fourth region 4A.

Accordingly, the second via V2 may be formed at a position that does not overlap the molding member <NUM>, and the third via V3 may be formed at a position that overlaps the molding member <NUM>.

Therefore, the second via V2 and the connection member <NUM> may be disposed outside the molding member <NUM> and may be disposed at a position that does not overlap the molding member <NUM>, and the third via V3 and the connection circuit pad portion <NUM> may be disposed at a position that overlaps the molding member <NUM> and may be disposed while being surrounded by the molding member <NUM>.

That is, the smart IC module according to another embodiment does not directly wire-bond the chip and the second terminal of the coil pattern, and the smart IC module connects by wire bonding in a region closer to the chip than the second terminal through the connection member, thereby reducing the arrangement area of the molding member.

Therefore, since it is not necessary to dispose the molding member up to the second terminal disposed on the edge of the substrate, the smart IC module and the card module may be easily adhered through the edge of the substrate.

Hereinafter, an IC card including a smart IC module according to an embodiment will be described with reference to <FIG>.

Referring to <FIG>, an IC card <NUM> according to the embodiment may include a smart IC module <NUM> and a card module <NUM>.

In detail, the card module <NUM> may include an opening region OA, and the smart IC module <NUM> may be disposed inside the opening region OA.

The card module <NUM> may have the standard of a credit card or transportation card that are generally used, but the embodiment is not limited thereto.

The card module <NUM> may be formed by stacking at least one transparent or opaque synthetic resin sheet and then performing thermocompression bonding. For example, in the card module <NUM>, the transparent or opaque synthetic resin sheet may include any one resin material among a polyvinylchloride (PVC) sheet, a polycarbonate (PC) sheet, a polyethylene terephthalate (PET) sheet, a glycol modified polyethylene terephthalate (PETG) sheet, a sheet made of a mixture of polyvinylchloride (PVC) and acrylonitrile butadiene styrene (ABS) resin, a sheet made of a mixture of polycarbonate (PC) and glycol modified polyethylene terephthalate (PETG) resin, and a polyester-based synthetic paper.

In addition, the embodiment is not limited thereto, and the card module may include a metal material.

The smart IC module <NUM> and the card module <NUM> may each include an antenna. In detail, the smart IC module <NUM> and the card module <NUM> may each include an antenna including a coil pattern. In more detail, the smart IC module <NUM> may include a first coil pattern including the coil pattern described above, and the card module <NUM> may include a second coil pattern <NUM>.

The first coil pattern and the second coil pattern may be not in physical contact with each other and may exchange signals with each other to recognize information according to the signal from the chip.

The second coil pattern <NUM> may be disposed along an edge of the card module <NUM>. In addition, the second coil pattern <NUM> may also be disposed gradually closer to the smart IC module <NUM> from the edge of the card module <NUM>.

<FIG> illustrates that the card module <NUM> includes the second coil pattern, but the embodiment is not limited thereto. The IC card according to the embodiment may include only the coil pattern of the smart IC module.

Referring to <FIG>, the smart IC module <NUM> and the card module <NUM> may be adhered to each other. In detail, the smart IC module may be adhered to the card module <NUM> inside the opening region OA of the card module <NUM> through an adhesive layer <NUM>.

As described above, in the IC card according to the embodiment, the smart IC module and the card module may be easily adhered by sufficiently securing the adhesive region of the smart IC module, that is, a region where the adhesive layer <NUM> is disposed.

The characteristics, structures and effects described in the embodiments above are included in at least one embodiment but are not limited to one embodiment. Furthermore, the characteristic, structure, and effect illustrated in each embodiment may be combined or modified for other embodiments by a person skilled in the art. Thus, it should be construed that contents related to such a combination and such a modification are included in the scope of the present invention.

Claim 1:
A smart IC module comprising:
a smart IC substrate (<NUM>); and
a chip (<NUM>) disposed on the smart IC substrate,
wherein the smart IC substrate (<NUM>) comprising:
a substrate (<NUM>) including one surface (<NUM>) and the other surface (<NUM>) on which a chip mounting region (CSA) is formed;
a circuit pattern (<NUM>) on the one surface (<NUM>) of the substrate (<NUM>);
a connection circuit pattern (<NUM>) disposed on the one surface (<NUM>) of the substrate (<NUM>) and spaced apart from the circuit pattern (<NUM>); and
a coil pattern (<NUM>) disposed on the other surface (<NUM>) of the substrate (<NUM>) and including a first terminal (<NUM>) provided at one end and a second terminal (<NUM>) provided at the other end,
the substrate includes a first region (1A) disposed inside the coil pattern (<NUM>) and a second region (1B) disposed outside the coil pattern (<NUM>),
the first terminal (<NUM>) is disposed in the first region (1A),
the second terminal (<NUM>) is disposed in the second region (1B),
characterized in that:
the substrate (<NUM>) includes a first via (V1) formed in the first region (1A) corresponding to the circuit pattern (<NUM>), a second via (V2) formed in the second region (1B) corresponding to one end of the connection circuit pattern (<NUM>), and a third via (V3) formed in the first region (1A) corresponding to the other end of the connection circuit pattern (<NUM>),
a connection member (<NUM>) is disposed in the second via (V2) and electrically connects between the one end of the connection circuit pattern (<NUM>) and the second terminal (<NUM>), and
the chip (<NUM>) is bonded to the other end of the connection circuit pattern (<NUM>) exposed through the third via (V3) by a wire (<NUM>).-