Patent Description:
Field effect transistors (FETs) consisting of a multiple (stacked) channel structure have drawn attention recently for increased current density and reduced on-resistance for power amplifier and power switch applications. For a single channel FET, conventional alloyed ohmic contacts are formed by annealing a stack of thin metal layers (such as Ti/Al/Mo/Au for GaN FETs, AuGe/Ni/Au for GaAs/InGaAs FETs); the sunk metals form an ohmic contact to the channel layer. However, this method does not work well for multi-channel FET structures, where the distance between the top semiconductor surface and the stacked channels is larger, because the alloyed metals do not reach the deep channels. This results in high contact resistance for multi-channel transistors.

Document <CIT> discloses a GaN based semiconductor field effect transistor comprising a mesa protrusion having a super-lattice structure including trenches at interface with respect to the mesa protrusion.

"Regrown" ohmic contacts are another technology used to form low-resistance ohmic contacts. A low ohmic contact resistance in laterally regrown n+GaN on a single 2DEG channel has been demonstrated. However, contact resistance in a multiple channel FET may be higher than desired.

An ohmic contact for a multiple channel FET is presented. The present invention relates to an ohmic contact according to claim <NUM>. According to the invention, the present ohmic contact comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer of the FET. The recesses are aligned linearly with each other, with the line of recesses oriented perpendicular to the direction of current flow between the FET's source and drain. Ohmic metals in and on the sidewalls of each slit-shaped recess provides ohmic contact to each of the multiple channel layers. The sidewalls are preferably sloped, with the angle of the sidewalls being between <NUM>° and <NUM>°.

Each of the slit-shaped recesses has an inside edge which current flows to or from and an outside edge. In a preferred embodiment, a linear connecting recess which is contiguous with the outside edge of each of the slit-shaped recesses is provided. Ohmic metals are also deposited in the linear connecting recess such that they interconnect the slit-shaped recesses and the linear connecting recess with the multiple channel layers.

The present ohmic contact may also include an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses in the line of recesses, as well as over the linear connecting recess (if present).

The present ohmic contact typically serves as a source and/or drain contact for a multiple channel FET. The FET may be, for example, a GaN FET, with ohmic metals comprising Ti, Al, Mo, and/or Au. Another example would be a GaAs/InGaAs FET, with ohmic metals comprising AuGe, Ni, and/or Au. Additional examples are provided below.

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.

As an overview, in one possible embodiment, the present ohmic contact, intended for use with FETs having a multiple (stacked) channel structure, is formed by recess etching small slit patterns prior to ohmic metal deposition. The recesses are made deeper than the depth of the bottom channel layer. Ohmic metals are directly deposited onto the sidewalls of each recess, thereby forming simultaneous contact to each channel. The length, width, and shape of the slit structure is preferably optimized based on the materials' sheet resistance and the lateral contact resistance between the metal and the channel, so that overall contact resistance is minimized.

Also described is a similar concept applied to more recent regrown ohmic contact technology, where a regrown material makes ohmic contact with the sidewalls of multiple channels. As describes herein, the regrown material preferably has a corrugated structure, which increases contact area by increasing contact periphery two dimensionally, thereby decreasing effective contact resistance. The length, width, and shape of the corrugated structure is preferably optimized based on the materials' sheet resistance and the lateral contact resistance between the metal and the channel, so that overall contact resistance is minimized.

One possible embodiment of the "slit pattern" approach is illustrated in <FIG>, in which ohmic contacts <NUM>, <NUM> (source and drain) are provided for a multiple channel FET <NUM>. Each ohmic contact comprises a plurality of slit-shaped recesses <NUM> in a wafer <NUM> on which a multiple channel FET resides. Each recess <NUM> has a depth at least equal to the depth of the lowermost channel layer <NUM> of the FET, with the recesses aligned linearly with each other. The line of recesses is oriented perpendicular to the direction of current flow between the FET's source and drain. Ohmic metals (not numbered) are in and on the sidewalls of each of the slit-shaped recesses such that ohmic contact is made to each of the multiple channel layers - with contact to the channel layers being made laterally. The width and pitch of the slits is preferably chosen to optimize material conductivity and interfacial resistance.

The present ohmic contact may further comprise an ohmic metal contact layer <NUM> on the top surface of wafer <NUM> over and in contact with the ohmic metals in each of the recesses <NUM>. The ohmic metal contact layer <NUM> has an inside edge <NUM> and an outside edge <NUM>; the line of recesses <NUM> is preferably set back from the ohmic metal contact layer's inside edge <NUM> by a distance ≥ <NUM> such that each of the recesses is completely overlapped (covered) by the ohmic metal contact layer.

Ohmic metal contact layer <NUM> has an associated width W1 defined as the distance between inside edge <NUM> and outside edge <NUM>. Each of recesses <NUM> also has an associated common width W2 defined in the same direction as W1. The minimum value for W1 is preferably equal to W2. W1 can be considerably greater than W2, as illustrated in <FIG>. Alternatively, as illustrated in <FIG>, ohmic metal contact layer <NUM> can be relatively narrow - with a width W1 equal or nearly equal to W2.

<FIG> shows a multiple channel FET <NUM> as described herein, with the cross-sectional views (taken along section lines A-A' and B-B') shown in <FIG> illustrating possible shapes for the sidewalls <NUM>, <NUM> of recesses <NUM>. As shown in <FIG>, sidewalls <NUM>,<NUM> may be vertical. However, in <FIG>, sidewalls <NUM>, <NUM> are sloped, with the angle of the sidewalls preferably being between <NUM>° and <NUM>°.

When arranged as shown in <FIG>, current paths <NUM> are formed between ohmic contacts <NUM> and <NUM> - formed as described above with slit-shaped recesses <NUM> - as shown in <FIG>. Another possible embodiment is shown in <FIG>. As before, slit-shaped recesses <NUM> are formed. In addition, and according to the present invention, linear connecting recesses <NUM> are formed which are contiguous with the outside edge of each of slit-shaped recesses <NUM>. Ohmic metals fill both linear connecting recess <NUM> and recesses <NUM> such that the slit-shaped recesses and linear connecting recess of each ohmic contact are interconnected with the multiple channel layers. Now, in addition to current paths <NUM>, additional current paths <NUM> are provided between linear connecting recesses <NUM>.

Note that at least two different embodiments are contemplated for an ohmic contact with a linear connecting recess as shown in <FIG>. For example, in the configuration shown in <FIG>, an ohmic contact layer <NUM> is over and in contact with the ohmic metals in each of the recesses <NUM> and <NUM>. As before, the line of recesses <NUM> is preferably set back from the ohmic metal contact layer's inside edge <NUM> by a distance ≥ <NUM> such that each of the recesses is completely covered by ohmic metal contact layer <NUM>. Alternatively, as shown in <FIG>, no ohmic metal contact layer is provided over recesses <NUM> and <NUM>.

The present ohmic contacts can be used with multiple channel FETs made from various materials. For example, the multiple channel FET may be a n-type AlGaN/GaN FET; here, suitable ohmic metals comprise Ti, Al, Mo, and/or Au; for a p-type AlGaN/GaN FET, Pd, Ni, Pt and/or Au are suitable ohmic metals. As another example, the multiple channel FET may be a GaAs/InGaAs FET; here, suitable ohmic metals comprise AuGe, Ni, and/or Au. Another example is an AlGa<NUM>O<NUM>/Ga<NUM>O<NUM> FET; here, suitable ohmic metals comprise Ti and Au. In general, the ohmic metals should be chosen to provide a desired contact resistance; this would typically be empirically determined.

Note that, though multiple channel FETs are described as the primary application of the present ohmic contact, they can more generally find application with any FET having one or more channel layers. For example, the ohmic contacts might be useful with a FET having a single thick channel layer, such as a bulk channel (instead of 2DEG) which has been uniformly doped with an n-type or p-type dopant, for which a conventional alloyed ohmic contact from the top surface cannot reach to the entire channel layer. A MESFET is an example.

A similar approach can be applied for more recent "regrown" ohmic contact technology. Here, rather than forming contacts by depositing metal, a regrown material such as, for example, n+GaN, is directly deposited on the sidewalls of multiple channels - using MBE or MOCVD, for example. This is illustrated in <FIG>. In <FIG>, ohmic source and drain contacts <NUM>, <NUM> are formed on a multiple channel FET <NUM>, using a regrown material <NUM> on a wafer <NUM> on which a multiple channel FET resides. Regrown material <NUM> laterally contacts the sidewalls of each channel layer <NUM> of the multiple channel FET.

A preferred embodiment using this concept is shown in <FIG>. Here, the regrown material <NUM> has an inside edge <NUM> which is perpendicular to the top surface of the wafer <NUM> on which the FET resides and which contacts the sidewalls of each channel layer <NUM>, with inside edge <NUM> having a corrugated shape. A corrugated structure increases total contact periphery two dimensionally, resulting in reduced contact resistance per transistor gate width. The length, width, and shape of the corrugated structure is preferably optimized based on the materials' sheet resistance and the lateral contact resistance between the regrown material and the channels, so that overall contact resistance is minimized.

Examples of suitable regrown materials for various FET types are as follows:.

As noted above for the slit-shaped recess approach, the regrown material approach described herein can more generally find application with any FET having one channel layer or multiple channel layers.

Both the 'slit' and 'regrown' approaches offer much reduced contact resistance to the multiple channels over prior art methods by (<NUM>) having ohmic metals or regrown materials directly contact multiple channels simultaneously, and (<NUM>) increasing contact periphery by introducing slit/corrugated structures.

One possible method of forming ohmic contacts using slit-shaped recesses as described herein is shown in <FIG>. In step <NUM>, slit-shaped recesses are etched in a wafer on which a multiple channel FET is being fabricated. Each recess is etched to a depth at least equal to the depth of the lowermost channel layer of the FET. The recesses are aligned linearly with each other, and the line of recesses is oriented perpendicular to the direction of current flow between the FET's source and drain. In step <NUM>, ohmic metals are deposited in and on the sidewalls of each of the slit-shaped recesses such that ohmic contact is made to each of the multiple channel layers.

Optionally, for manufacturing an ohmic contact according to the present invention, in step <NUM>, a linear connecting recess is etched which is contiguous with the outside edge of each of the slit-shaped recesses (as illustrated in <FIG>). If a linear connecting recess has been etched, ohmic metals are also deposited in the linear connecting recess such that the ohmic metals interconnect the slit-shaped recesses and the linear connecting recess with the multiple channel layers (step <NUM>).

Another optional step is shown in step <NUM>: an ohmic metal contact layer is deposited on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses (as illustrated in <FIG>). In accordance with the present invention, either steps <NUM>/<NUM> or step <NUM> can be performed, both can be performed, or neither can be performed.

The etching steps are preferably performed with a dry etch, such as a reactive ion etch (RIE) or an inductively-coupled plasma etch (ICP-RIE). The depositing of the ohmic metals preferably comprises evaporating or sputtering the ohmic metals sequentially in one process step. As noted previously, the sidewalls of the recesses may be sloped, with the angle of the sidewalls being between <NUM>° and <NUM>°. The etching and metal deposition steps are preferably performed before the FET's gate is formed.

One possible method of forming ohmic contacts using regrown material as described herein is shown in <FIG>. In step <NUM>, a multiple channel FET is etched to expose the sidewalls of each channel layer. In step <NUM>, a regrown material such as, for example, n+GaN, is directly deposited such that it laterally contacts the sidewalls of each of the channel layers. Optionally (and preferably), in step <NUM>, the inside edge of the regrown material is given a corrugated shape. As noted above, the regrown material is preferably deposited using MBE or MOVCD.

The present ohmic contact for multiple channel FETs can be used in numerous applications. For example, power amplifier MMICs with high output power, low noise amplifier MMICs with high linearity, RF switch MMICs with low insertion loss and high isolation, and power switch transistors with low dynamic on-resistance and breakdown voltages are just several possible applications.

Claim 1:
An ohmic contact (<NUM>, <NUM>) for a multiple channel FET, comprising:
a plurality of slit-shaped recesses (<NUM>) in a wafer (<NUM>) on which a multiple channel FET (<NUM>) resides, each recess having a depth at least equal to the depth of the lowermost channel layer of said FET, said recesses aligned linearly with each other, said line of recesses oriented perpendicular to the direction of current flow between said FET's source and drain;
ohmic metals in and on the sidewalls of each of said slit-shaped recesses such that ohmic contact is made to each of said multiple channel layers;
wherein each of said slit-shaped recesses (<NUM>) has an inside edge which current flows to or from and an outside edge,
characterised in that, the ohmic contact further comprises a linear connecting recess (<NUM>) which is contiguous with the outside edge of each of said slit-shaped recesses (<NUM>), said ohmic metals also in said linear connecting recess such that said ohmic metals interconnect said slit-shaped recesses and said linear connecting recess with said multiple channel layers.