Patent Description:
The host system may fully decode the raw video streams in real-time (as received) in order to detect operational events such as motion by people or objects or to perform facial recognition. Detection of an operational event may cause the host system to control the video cameras to increase resolution, pan, title, zoom, etc. This conventional approach to video processing increases stress on the data processing and power resources of the host system.

<CIT> discloses a networked surveillance and control system.

<CIT> discloses video monitoring apparatus for detecting an event from an image or video.

Reference is made herein to example video codecs (e.g., MPEG video codecs) that utilize I (intra) frame, P (predicted) frames, and B (bi-directional frames). I frames are frames encoded using intraframe encoding; P frames are encoded using motion compression using past I frames or past P frames; and B frames are encoded using motion compression by either past or future I frames or P frames. Although used as examples, the techniques disclosed herein are not limited to use with codecs utilizing such frames.

<FIG> illustrates a system <NUM> in which a host system <NUM> and a supervisor device <NUM> are connected to a video distribution network <NUM> over which one or more raw video stream generated by one or more video camera <NUM> is communicated. The supervisor device <NUM> is optional and may be utilized, for example, to monitor the output of the one or more video camera <NUM> in real-time.

In various embodiments, the video distribution network <NUM> may include the Internet, a local area network ("LAN"), a wide area network ("WAN"), and/or other data network. In addition to traditional data-networking protocols, in some embodiments, data may be communicated according to protocols and/or standards including near field communication ("NFC"), Bluetooth, power-line communication ("PLC"), and the like. In some embodiments, the video distribution network <NUM> may also include a voice network that conveys not only voice communications, but also non-voice data such as Short Message Service ("SMS") messages, as well as data communicated via various cellular data communication protocols, and the like.

In various embodiments, the supervisor device <NUM> may include desktop PCs, mobile phones, laptops, tablets, wearable computers, or other computing devices that are capable of connecting to the video distribution network <NUM> and communicating with the host system <NUM>, which in some embodiments is a video surveillance server comprising host system logic <NUM>. Generally the host system <NUM> is any one or more computer system meeting the performance requirements of the particular implementation, such as for storing one or more raw video streams.

In various embodiments, additional infrastructure (e.g., short message service centers, cell sites, routers, gateways, firewalls, and the like), as well as additional devices may be present. Further, in some embodiments, the functions described as being provided by some or all of the host system <NUM> and the supervisor device <NUM> may be implemented via various combinations of physical and/or logical devices. However, it is not necessary to show such infrastructure and implementation details in <FIG> in order to describe an illustrative embodiment.

<FIG> is an example block diagram of a computing device <NUM> that may incorporate embodiments of the present invention. For example, the host system <NUM> may be implemented by an embodiment of the computing device <NUM>. <FIG> is merely illustrative of a machine system to carry out aspects of the technical processes described herein, and does not limit the scope of the claims. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. In one embodiment, the computing device <NUM> typically includes a monitor or graphical user interface <NUM>, a host system <NUM>, a communication network interface <NUM>, input device(s) <NUM>, output device(s) <NUM>, and the like.

As depicted in <FIG>, the host system <NUM> may include one or more processor(s) <NUM> that communicate with a number of peripheral devices via a bus subsystem <NUM> or the video distribution network <NUM>. These peripheral devices may include input device(s) <NUM>, output device(s) <NUM>, communication network interface <NUM>, and a storage subsystem, such as a volatile memory <NUM> and a non-volatile memory system <NUM>. The video camera <NUM> in this example is both an input device and an output device. Inputs to the video camera <NUM> include controls for one or more of zoom, pan, tilt, focus, and resolution of the video codec <NUM> utilized by the video camera <NUM>. Many video cameras implement more than one video codec <NUM> and so the control inputs to a video camera <NUM> of this type may include a selection of which video codec <NUM> to use in operation. The video camera <NUM> outputs include at least a raw video stream.

The volatile memory <NUM> and/or the non-volatile memory system <NUM> may store computer-executable instructions and thus forming host system logic <NUM> that when applied to and executed by the processor(s) <NUM> implement embodiments of the processes disclosed herein. The non-volatile memory system <NUM> in this example may function as both an input device for storing a raw video stream and an output device for detecting events, as described more fully below.

The input device(s) <NUM> include devices and mechanisms for inputting information to the host system <NUM>. These may include a keyboard, a keypad, a touch screen incorporated into the monitor or graphical user interface <NUM>, audio input devices such as voice recognition systems, microphones, and other types of input devices. In various embodiments, the input device(s) <NUM> may be embodied as a computer mouse, a trackball, a track pad, a joystick, wireless remote, drawing tablet, voice command system, eye tracking system, and the like. The input device(s) <NUM> typically allow a user to select objects, icons, control areas, text and the like that appear on the monitor or graphical user interface <NUM> via a command such as a click of a button or the like.

The output device(s) <NUM> include devices and mechanisms for outputting information from the host system <NUM>. These may include the monitor or graphical user interface <NUM>, speakers, printers, infrared LEDs, and so on as well understood in the art.

The communication network interface <NUM> provides an interface to communication networks (e.g., video distribution network <NUM>) and devices external to the host system <NUM>. The communication network interface <NUM> may serve as an interface for receiving data from and transmitting data to other systems. Embodiments of the communication network interface <NUM> may include an Ethernet interface, a modem (telephone, satellite, cable, ISDN), (asynchronous) digital subscriber line (DSL), FireWire, USB, a wireless communication interface such as Bluetooth or WIFI, a near field communication wireless interface, a cellular interface, and the like.

The communication network interface <NUM> may be coupled to the video distribution network <NUM> via an antenna, a cable, or the like. In some embodiments, the communication network interface <NUM> may be physically integrated on a circuit board of the host system <NUM>, or in some cases may be implemented in software or firmware, such as "soft modems", or the like.

The computing device <NUM> may include logic that enables communications over a network using protocols such as HTTP, TCP/IP, RTP/RTSP, IPX, UDP and the like.

The volatile memory <NUM> and the non-volatile memory system <NUM> are examples of tangible media configured to store computer readable data and instructions to implement various embodiments of the processes described herein. Other types of tangible media include removable memory (e.g., pluggable USB of SD memory devices, mobile device SIM cards), semiconductor memories such as flash memories, networked storage devices, and the like. The volatile memory <NUM> and the non-volatile memory system <NUM> may be configured to store the basic programming and data constructs that provide the functionality of the disclosed processes and other embodiments thereof that fall within the scope of the present invention.

Host system logic <NUM> that implements embodiments of the present invention may be stored in the volatile memory <NUM> and/or the non-volatile memory system <NUM>. Said host system logic <NUM> may be read from the volatile memory <NUM> and/or non-volatile memory system <NUM> and executed by the processor(s) <NUM>. The volatile memory <NUM> and the non-volatile memory system <NUM> may also provide a repository for storing data and instructions used by the host system logic <NUM>.

The volatile memory <NUM> and the non-volatile memory system <NUM> may include a number of memories including a main random access memory (RAM) for storage of instructions and data during program execution and a read only memory (ROM) in which read-only non-transitory instructions are stored. The volatile memory <NUM> and the non-volatile memory system <NUM> may include a file storage subsystem providing persistent (non-volatile) storage for instructions and data. The volatile memory <NUM> and the non-volatile memory system <NUM> may include removable storage systems, such as removable flash memory.

The bus subsystem <NUM> provides a mechanism for enabling the various components and subsystems of host system <NUM> communicate with each other as intended. Although the bus subsystem <NUM> a communication network interface <NUM> are depicted schematically as each being a single bus, some embodiments of the bus subsystem <NUM> and/or communication network interface <NUM> may utilize multiple distinct busses.

It will be readily apparent to one of ordinary skill in the art that the computing device <NUM> may be a device such as a smartphone, a desktop computer, a laptop computer, a rack-mounted computer system, a computer server, or a tablet computer device, among other possibilities. As commonly known in the art, the computing device <NUM> may be implemented as a collection of multiple networked computing devices. Further, the computing device <NUM> will typically include operating system logic (not illustrated), applications, and other logic the types and nature of which are well known in the art.

<FIG> illustrates a conventional video recording system <NUM> in one embodiment. In addition to elements already introduced, the video recording system <NUM> comprises a decoder/event detector <NUM> and host system-based control logic <NUM>. A decoder refers to logic to reverse the encoding of data to recover the raw, unencoded data. Control logic refers to logic to generate signals to control other logic and thus control logic may in some cases control other control logic. Although illustrated separately the non-volatile memory system <NUM> may be part of the host system <NUM> either integrally or as a plug-in device.

The video camera <NUM> and video codec <NUM> generate a raw video stream that is received by the decoder/event detector <NUM> of the host system <NUM>. The decoder/event detector <NUM> detects an event which is provided to the host system-based control logic <NUM> which in turn controls the video codec <NUM> or video camera <NUM>. Concurrently the raw video stream is stored to the non-volatile memory system <NUM> by the host system <NUM>.

<FIG> illustrates a video recording system <NUM> in one embodiment. In addition to features already introduced, the video recording system <NUM> the non-volatile memory system <NUM> includes a partial decoder/event detector <NUM> and a memory system-based control logic <NUM>. A partial decoder refers to logic to partially decode raw video, as opposed to a decoder (implicitly, a full decoder) that performs a full decoding of the video. A partial decoder may analyze only a subset of frames and/or may only perform decoding sufficient to detect particular events. A decoder may be indicated as a partial decoder by context, for example if the decoder is described as partially decoding a raw video stream.

The partial decoder/event detector <NUM> may for example be implemented as processor-executable instructions in a volatile memory or non-volatile memory of the non-volatile memory system <NUM> (the non-volatile memory system <NUM> will typically include some volatile memory as well as, typically, a larger capacity of non-volatile memory). Alone, or together with the memory system-based control logic <NUM>, the partial decoder/event detector <NUM> may thus implement event detection logic. Event detection logic refers to logic to detect events such as objects, motion, faces, and combinations thereof, in video. Object recognition refers to the detection of particular objects (inanimate or animate) in video. The partial decoder/event detector <NUM> and memory system-based control logic <NUM> may also be at least partially implemented in hardware, e.g., as integrated circuit, FPGA, etc..

In some embodiments the event detection logic is configurable with a frame-to-frame delta threshold indicative of an event and/or an operational event. An operational event refers to an event associated with taking a control action on a video camera or video codec. A frame-to-frame delta refers to a quantitative or qualitative metric of differences between video frames. Operational events may include operational events to undo settings to a video codec or camera made in response to a prior operational event.

The partial decoder portion of the partial decoder/event detector <NUM> may also be configurable with a desired level of decoding to perform on the raw video stream, e.g., how many frames to analyze of the incoming raw video stream and to what resolution.

An embodiment of a video recording and control process <NUM> utilizing the video recording system <NUM> is explained in more detail in conjunction with <FIG>.

Utilizing the video recording system <NUM> design enables the host system-based control logic <NUM> to be backward-compatible with conventional approaches. In other words, the host system-based control logic <NUM> may be unmodified or substantially unmodified from the host system-based control logic in conventional video recording systems.

The control signals from the host system-based control logic <NUM> to the memory system-based control logic <NUM> may include signals to control, for example, the extent of decoding to be performed by the partial decoder/event detector <NUM> in order to meet performance requirements of the implementation, events for the partial decoder/event detector <NUM> to detect, operational events to be reported to the host system-based control logic <NUM>, performance, threshold, and other control factors.

In one embodiment all of the raw video stream from the video codec <NUM> is stored by the non-volatile memory system <NUM>. In other implementations, the host system <NUM> may control the extent to which the raw video stream is stored.

Certain video codecs (e.g., the MPEG class of video codecs) utilize a set of frames referred as Group of Pictures (GOP) that is a sequence of frames starting with an I frame followed by one or more P frames. Each P frames utilizes temporal compression that represents differences from a preceding I frame and are usually low on entropy when there is no motion in the raw video stream. Thus comparing the entropy in a P frame (or B frame) with a frame-to-frame delta threshold provides a manner of event detection with only partial decoding of the raw video stream. Another partial decoding technique is to decode P frames (or B frames) on a periodic basis, the period of which may be configurable.

The period for partially decoding I frames or P frames (or B frames) may be dynamically configured according to run-time factors such as available processing resources of the non-volatile memory system and/or performance requirements for event detection.

In yet another variation, the video codec may be configured (either by the host system or the non-volatile memory system) to encode only I frames, and the event detection logic of the non-volatile memory system may determine the frame-to-frame delta of successive or periodic I frames and generate events to the host system based on the frame-to-frame delta exceeding a threshold.

The events to the host can be raised through one or more mechanisms, e.g., hardware interrupts, extension to storage/memory commands typically used between the host and the non-volatile memory system <NUM>, etc. The partial decoding may use volatile memory within the non-volatile memory system <NUM> during the decoding process. If the non-volatile memory system <NUM> lacks sufficient volatile memory, the host's volatile memory is used, e.g., as supported by the NVMe interface.

In some embodiments the operational event sent to the host may include an event indicating that a previous operational event condition no longer exists. For example, the non-volatile memory system may generate an operational event to the host system indicating that a previously detected motion, object, face, etc. is no longer being detected. The host system may respond by reversing the video camera control for the previous operational event, e.g., lowering the resolution of the video codec, zooming back to a wider angle, changing a tilt or pan setting, etc..

By way of example an event may include the video quadrant <NUM> and event coordinates <NUM> (e.g., cartesian or polar event coordinates) within the video quadrant <NUM> to which the video camera <NUM> or video codec <NUM> should focus, tilt, zoom, or sample at a higher video resolution. Event coordinates refer to data specifying a spatial location of an event detected in video. In some cases event coordinates may also specify a temporal location (e.g., a frame) of the event. A video quadrant is a group of macro blocks that exactly or approximately forms a Cartesian quadrant in a video frame. A macro block refers to a grouping of samples used by video codecs based on linear block transforms, such as certain MPEG codecs and certain H. 26x codecs.

The event may in some cases further include an indication of the video frame <NUM>, and type of event, such as object or human identification or motion, facial recognition, and the like. The type of events detected and generated may vary according to the needs of a particular implementation.

While the description herein focuses on encoded video data, the partial decoding and event trigger mechanism may be used on for other encoded data, such as audio data.

<FIG> illustrates a video recording and control process <NUM> in one embodiment. At action <NUM> the raw video stream is started. The system logic (e.g., the partial decoder/event detector <NUM> or memory system-based control logic <NUM>) determines the video file type and video codec type for the raw video stream (action <NUM> and action <NUM>). At action <NUM> partial video decoding begins, and in one embodiment, can continue for as long as the raw video stream is received. In other embodiments, the partial decoding can be activated as needed or as pre-configured. The raw video stream is also recorded to non-volatile memory (action <NUM>). If an operational event is detected (decision action <NUM>), for example if a frame-to-frame delta between I frames or P frames or B frames or any combination thereof exceeds a configured frame-to-frame delta, an operational event is formed at action <NUM> and the operational event is communicated to the host system at action <NUM>. In this manner, video that is typically recorded into non-volatile memory can be analyzed in line as part of the memory write process without host involvement, and event notification can be triggered based on the partial decoding mechanism described herein. In other embodiments, the partial decoding and event trigger mechanism may be performed as part of other data operations, such as read, data copy, data migration, data refresh, garbage collection, etc..

In certain embodiments, the system logic (e.g., the partial decoder/event detector <NUM> or memory system-based control logic <NUM>) could be implemented in a device separate from the non-volatile memory system <NUM>. For example it could be part of a device (e.g., router, bus, bridge) that handles/manages data transport among the host, the memory system, and/or source of data such as a surveillance system.

<FIG> is a block diagram of an exemplary non-volatile memory system <NUM>. The non-volatile memory system <NUM> may include one or more memory die <NUM>. The memory die <NUM> includes a memory structure <NUM> of memory cells, such as an array of memory cells herein referred to as a memory array, address controller <NUM>, and read/write circuits <NUM>. The memory structure <NUM> is addressable by word lines via a row decoder <NUM> and by bit lines via a column decoder <NUM>. The read/write circuits <NUM> include multiple sense blocks SB1, SB2,. , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically the memory system-based control logic <NUM> is included in the same non-volatile memory system <NUM> (e.g., a removable storage card) as the one or more memory die <NUM>. Control commands and data (e.g., a raw video stream) are transferred between the host system <NUM> and memory system-based control logic <NUM> via a data bus <NUM>, and between the controller and the one or more memory die <NUM> via lines <NUM>. The data bus <NUM> may for example be a PCIe serial memory bus.

The memory structure <NUM> can be 2D (laid out in a single fabrication plane) or 3D (laid out in multiple fabrication planes). The memory structure <NUM> may comprise one or more array of memory cells including a 3D array. In one embodiment, the memory structure <NUM> may comprise a monolithic three-dimensional memory structure (3D array) in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure <NUM> may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure <NUM> may be in a non-volatile memory device (e.g. Non-volatile memory system <NUM>) having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

The address controller <NUM> cooperates with the read/write circuits <NUM> to perform memory operations on memory cells of the memory structure <NUM>, and includes a state machine <NUM>, an address decoder <NUM>, and a power control <NUM>. The state machine <NUM> provides control of memory operations. A store region selector <NUM> may be provided, e.g., for programming parameters as described further below.

The address decoder <NUM> provides an address interface between that used by the host or a memory system-based control logic <NUM> to the hardware address used by the row decoder <NUM> and column decoder <NUM>. The power control <NUM> controls the power and voltages supplied to the various control lines during memory operations. The power control <NUM> and/or read/write circuits <NUM> can include drivers for word lines, source gate select (SGS) transistors, drain gate select (DGS) transistors, bit lines, substrates (in 2D memory structures), charge pumps, and source lines. The sense blocks can include bit line drivers and sense amplifiers in one approach.

An SGS transistor is a select gate transistor at a source end of a memory string, and a DGS transistor is a select gate transistor at a drain end of a memory string.

In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure <NUM>, can be thought of as at least one control circuit or controller which is configured to perform the techniques described herein. For example, a control circuit may include any one of, or a combination of, address controller <NUM>, state machine <NUM>, address decoder <NUM>, column decoder <NUM>, power control <NUM>, control processor <NUM>, sense blocks SB1, SB2,. , SBp, read/write circuits <NUM>, memory system-based control logic <NUM>, and so forth.

The memory system-based control logic <NUM> may comprise a control processor <NUM> and memory devices such as controller read-only memory <NUM> and controller volatile memory <NUM>.

The memory devices of the memory system-based control logic <NUM> may comprise code such as a set of instructions, that configure the control processor <NUM> to execute the set of instructions to provide aspects of the functionality described herein. Alternatively or additionally, the control processor <NUM> can access code from the memory structure <NUM>, such as a reserved area of memory cells in one or more word lines.

For example, code can be used by the memory system-based control logic <NUM> to access the memory structure <NUM>, controller read-only memory <NUM>, or controller volatile memory <NUM> for partial decoding and/or event detection logic. In some embodiments the control logic may utilize the host system volatile memory <NUM> for caching some or all of the raw video stream for partial decoding and event detection, using for example direct memory access technology (DMA) over the data bus <NUM>. The control logic may further include drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

Generally, the control logic can include software and other logic (e.g., circuits, firmware) to perform the functions described herein. The control logic may comprise a sequencer to control the timing (start and stop times, durations, spacing etc.) of the various signals described herein. The state machine <NUM> may also be utilized to implement aspects of the control logic.

In one embodiment, the host system <NUM> is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (host system volatile memory <NUM>, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the one or more processors to perform aspects of the techniques described herein. The host system <NUM> may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors, as well as other components well known in the art.

The store region selector <NUM> may be a non-volatile memory such as NAND flash memory, or another type. The store region selector <NUM> identifies blocks of the memory structure <NUM> for reading and writing, among other things, as known in the art.

One of skill in the art will recognize that the non-volatile memory system <NUM> is an example and that various implementations will include additional components, or exclude or combine some of the illustrated components, in manners known in the art.

Terms used herein should be accorded their ordinary meaning in the relevant arts, or the meaning indicated by their use in context, but if an express definition is provided, that meaning controls.

"Circuitry" refers to electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes or devices described herein), circuitry forming a memory device (e.g., forms of random access memory), or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment).

"Firmware" refers to software logic embodied as processor-executable instructions stored in read-only memories or media.

"Hardware" refers to logic embodied as analog or digital circuitry.

"Logic" refers to machine memory circuits, non transitory machine readable media, and/or circuitry which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter).

"Software" refers to logic implemented as processor-executable instructions in a machine memory (e.g. read/write volatile or nonvolatile memory or media).

Herein, references to "one embodiment" or "an embodiment" do not necessarily refer to the same embodiment, although they may. Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to. " Words using the singular or plural number also include the plural or singular number respectively, unless expressly limited to a single one or multiple ones. Additionally, the words "herein," "above," "below" and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the claims use the word "or" in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list, unless expressly limited to one or the other. Any terms not expressly defined herein have their conventional meaning as commonly understood by those having skill in the relevant art(s).

Various logic functional operations described herein may be implemented in logic that is referred to using a noun or noun phrase reflecting said operation or function. For example, an association operation may be carried out by an "associator" or "correlator". Likewise, switching may be carried out by a "switch", selection by a "selector", and so on.

Within this disclosure, different entities (which may variously be referred to as "units," "circuits," other components, etc.) may be described or claimed as "configured" to perform one or more tasks or operations. This formulation-[entity] configured to [perform one or more tasks]-is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be "configured to" perform some task even if the structure is not currently being operated. A "credit distribution circuit configured to distribute credits to a plurality of processor cores" is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as "configured to" perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The term "configured to" is not intended to mean "configurable to. " An unprogrammed FPGA, for example, would not be considered to be "configured to" perform some specific function, although it may be "configurable to" perform that function after programming.

As used herein, the term "based on" is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase "determine A based on B. " This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on.

As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase "perform A in response to B. " This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.

As used herein, the terms "first," "second," etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, and not, for example, just logical registers <NUM> and <NUM>.

Claim 1:
A non-volatile memory system (<NUM>) comprising:
a non-volatile memory;
a volatile memory;
a decoder configured to output a partially-decoded video stream based at least in part on a raw video stream data to be written into the non-volatile memory;
event detection logic to detect operational events from the partially-decoded video stream output from the decoder; and
logic responsive to the event detection logic to generate a notification to a host system (<NUM>) to notify the host system (<NUM>) of operational events;
wherein the operational events comprise event coordinates (<NUM>) within the raw video stream, the event coordinates comprising a subregion of a video frame (<NUM>) and one or more of polar coordinates and Cartesian coordinates;
wherein the decoder is configured to use the volatile memory of the non-volatile memory system during the decoding process, and wherein the decoder is configured to use a volatile memory (<NUM>) of the host system (<NUM>) if the non-volatile memory system lacks sufficient volatile memory.