Patent Description:
Transistors are widely used as switching devices or driving devices in the field of electronic apparatuses. In particular, because a thin film transistor can be manufactured on a glass substrate or a plastic substrate, the thin film transistor is widely used as a switching device of a display apparatus such as a liquid crystal display apparatus or an organic light emitting apparatus.

The display apparatus may include, for example, a switching thin film transistor and a driving thin film transistor. Generally, it is preferable that the driving thin film transistor has a large s-factor (or sub-threshold swing) to represent a gray scale. However, the thin film transistors generally have a small s-factor to ensure on-off characteristics. Thus, when thin film transistors are applied to the driving thin film transistor of the display apparatus, it is difficult to represent a gray scale of the display apparatus.

Therefore, the thin film transistor applied to the driving thin film transistor of the display apparatus also needs to have a large s-factor to easily represent a gray scale. Also, even though the thin film transistor has a large s-factor, the thin film transistor should have excellent current characteristics in an ON-state.

<CIT> in a machine translation of an abstract states that "An embodiment of the present invention includes a first gate electrode and a second gate electrode that are spaced apart from each other and overlap, and a first active layer and a second active layer disposed between the first gate electrode and the second gate electrode. and an active layer wherein the active layer includes a channel portion, a first connection portion in contact with one side of the channel portion, and a second connection portion in contact with the other side of the channel portion, and the channel portion includes a first channel portion disposed in parallel. and a second channel portion, wherein the first channel portion and the second channel portion extend from the first connection portion to the second connection portion, respectively, and the first channel portion includes the first gate electrode and the second gate electrode. Overlapping, the second channel portion does not overlap the first gate electrode but overlaps the second gate electrode, and the first active layer is a thin film transistor made of a material having a lower mobility than the second active layer, and such a display device including a thin film transistor is provided.

<CIT> in an abstract states that "One embodiment of the present disclosure provides a thin film transistor including an auxiliary electrode, a gate electrode, and an active layer disposed between the auxiliary electrode and the gate electrode, the active layer includes a channel portion overlapping with the gate electrode, a first connection portion disposed on one side of the channel portion, and a second connection portion disposed on the other side of the channel portion, and the channel portion includes a portion overlapping with the auxiliary electrode and a portion not overlapping with the auxiliary electrode. One embodiment of the present disclosure also provides a display device including the thin film transistor.

The present disclosure has been made in view of the above problems and it is an object of the present disclosure to provide a thin film transistor that has a large s-factor and has excellent current characteristics in an ON-state.

It is another object of the present disclosure to provide a thin film transistor having a large current value in an ON-state while having a large s-factor by partially stacking two different types of oxide semiconductor layers to form a two-channel structure.

It is still another object of the present disclosure to provide a thin film transistor designed such that an interval between a gate electrode and an active layer is not greater than necessary to have excellent ON-current characteristics as the interval between the gate electrode and the active layer does not need to be increased to increase an s-factor of the thin film transistor.

It is further still another object of the present disclosure to provide a display apparatus including a driving thin film transistor having a large s-factor and large ON-current characteristics to have an excellent gray scale representation capability and excellent current characteristics.

In addition to the objects of the present disclosure as mentioned above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

In accordance with an aspect of the present disclosure, the above and other objects are accomplished by including a thin film transistor having an active layer, and a gate electrode at least partially overlapped with the active layer. Further, the active layer includes a channel portion (e.g. a channel), a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, the active layer includes a first active layer and a second active layer on the first active layer, the channel portion includes a first overlap area in which the first active layer and the second active layer overlap each other based on a plan view (from above), and a first non-overlap area in which the first active layer and the second active layer do not overlap each other based on the plan view. Also, each of the first active layer and the second active layer extends from the first connection portion to the second connection portion in the channel portion. In this instance, the second active layer can have a mobility greater (electron mobility) than a mobility of the first active layer.

In addition, the first overlap area can extend from the first connection portion to the second connection portion, and first non-overlap area can extend from the first connection portion to the second connection portion. The second active layer can cover an entire upper surface of the first active layer in the channel portion, and the second active layer can be disposed in an entire area of the channel portion based on the plan view. Also, the first active layer is not disposed in the first non-overlap area.

The active layer may further include a third active layer on the second active layer, and the third active layer can extend from the first connection portion to the second connection portion in the channel portion. The third active layer can also have a mobility smaller than a mobility of the second active layer. Also, the third active layer can be disposed in the first overlap area and the first non-overlap area. However, the third active layer may not be disposed in the first non-overlap area.

In addition, the channel portion can further include a second non-overlap area in which the first active layer and the second active layer do not overlap each other based on the plan view, and the second non-overlap area can be spaced apart from the first non-overlap area and may extend from the first connection portion to the second connection portion. The first active layer may not be disposed in the second non-overlap area.

Further, the active layer can further include a third active layer on the second active layer, and the third active layer can extend from the first connection portion to the second connection portion in the channel portion. The third active layer can also have a mobility smaller than a mobility of the second active layer, and be disposed in the first overlap area, the first non-overlap area and the second non-overlap area. Also, the third active layer may not be disposed in the second non-overlap area.

In addition, the channel portion can further include a second overlap area in which the first active layer and the second active layer overlap each other based on the plan view, and the second overlap area can be spaced apart from the first overlap area, and thus can extend from the first connection portion to the second connection portion.

The active layer can further include a third active layer on the second active layer, and the third active layer can extend from the first connection portion to the second connection portion in the channel portion. The third active layer can also have a mobility smaller than a mobility of the second active layer, and be disposed in the first overlap area, the first non-overlap area and the second overlap area. However, the third active layer may not be disposed in the first non-overlap area.

In addition, the first active layer can include at least one of an IGZO(InGaZnO)-based oxide semiconductor material, a GZO(GaZnO)-based oxide semiconductor material, an IGO(InGaO)-based oxide semiconductor material, or a GZTO(GaZnSnO)-based oxide semiconductor material, and when the oxide semiconductor material of the first active layer includes gallium (Ga) and indium (In), a concentration of gallium (Ga) may be higher than a concentration of indium (In) based on the number of moles [Ga concentration > In concentration].

The second active layer may include at least one of an IGZO(InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO(InSnZnO)-based oxide semiconductor material, an IGZTO(InGaZnSnO)-based oxide semiconductor material, a FIZO(FeInZnO)-based semiconductor material, a ZnO-based oxide semiconductor material, a SIZO(SiInZnO)-based oxide semiconductor material, or a ZnON(Zn-Oxynitride)-based oxide semiconductor material, and when the oxide semiconductor material of the second active layer includes gallium (Ga) and indium (In), a concentration of indium (In) may be higher than a concentration of gallium (Ga) based on the number of moles [Ga concentration < In concentration].

In accordance with another aspect of the present disclosure, the above and other objects can be accomplished by the provision of a display apparatus comprising the above-described thin film transistor.

The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following examples described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully explain the present disclosure to those skilled in the art.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing examples of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification.

When 'comprise', 'have', and 'include' described in the present specification are used, another part may be added unless 'only~' is used. The terms of a singular form may include plural forms unless referred to the contrary. In describing a position relationship, for example, when the position relationship is described as 'upon~', 'above~', 'below~', and 'next to~', one or more portions may be arranged between two other portions unless 'just' or 'direct' is used.

Spatially relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein to easily describe a relationship of one element or elements to another element or elements as illustrated in the figures. These terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device illustrated in the figure is reversed, the device described to be arranged "below," or "beneath" another device may be arranged "above" another device. Therefore, an exemplary term "below or beneath" may include "below or beneath" and "above" orientations. Likewise, an exemplary term "above" or "on" may include "above" and "below or beneath" orientations.

In describing a temporal relationship, for example, when the temporal order is described as "after," "subsequent," "next," and "before," a case which is not continuous may be included, unless "just" or "direct" is used. Although the terms "first", "second ," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to partition one element from another.

The term "at least one" should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.

Features of various examples of the present disclosure can be partially or overall coupled to or combined with each other, and be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The examples of the present disclosure can be performed independently from each other, or be performed together in a co-dependent relationship.

In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings. In the examples of the present disclosure, a source electrode and a drain electrode are distinguished from each other, for convenience of description. However, the source electrode and the drain electrode may be used interchangeably. Further, the source electrode can be the drain electrode, and the drain electrode can be the source electrode. Also, the source electrode in any one example of the present disclosure can be the drain electrode in another example of the present disclosure, and the drain electrode in any one example of the present disclosure can be the source electrode in another example of the present disclosure.

In some examples of the present disclosure, for convenience of description, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, the examples of the present disclosure are not limited to this structure. For example, a source region can be a source electrode, and a drain region can be a drain electrode. Also, a source region can be a drain electrode, and a drain region can be a source electrode. In addition, in some examples of the present disclosure, the term "channel" may mean "channel portion", and the term "channel portion" may mean "channel".

Next, <FIG> is a plan view illustrating a thin film transistor according to one example of the present disclosure, <FIG> is a cross-sectional view taken along line I-I' of <FIG>, <FIG> is a cross-sectional view taken along line II-II' of <FIG>, and <FIG> is a cross-sectional view taken along line III-III' of <FIG>.

As shown, a thin film transistor <NUM> according to one example of the present disclosure includes an active layer <NUM> and a gate electrode <NUM> that at least partially overlaps the active layer <NUM>. The active layer <NUM> includes a channel portion 130n, a first connection portion 130a contacting one side of the channel portion 130n, and a second connection portion 130b contacting the other side of the channel portion 130n. Also, the active layer <NUM> includes a first active layer <NUM> and a second active layer <NUM> on the first active layer <NUM>. In the examples of the present disclosure, the channel portion can be referred to as "channel", and the channel portion 130n may be referred to as "channel 130n".

In addition, as shown in <FIG>, the channel portion 130n includes a first overlap area OA1 in which the first active layer <NUM> and the second active layer <NUM> overlap each other based on the plan view, and a first non-overlap area NOA1 in which the first active layer <NUM> and the second active layer <NUM> do not overlap each other based on the plan view. In the channel portion 130n, each of the first active layer <NUM> and the second active layer <NUM> is extended from the first connection portion 130a to the second connection portion 130b.

Hereinafter, the thin film transistor <NUM> according to one example of the present disclosure will be described in more detail with reference to <FIG>. Referring to <FIG>, the thin film transistor <NUM> is disposed on a substrate <NUM>. Glass or plastic can be used as the substrate <NUM>. A transparent plastic having a flexible property, for example, polyimide can be used as the plastic. When polyimide is used as the substrate <NUM>, a heat-resistant polyimide capable of enduring a high temperature can be used considering that a high temperature deposition process is performed on the substrate <NUM>.

Also, a light shielding layer <NUM> can be disposed on the substrate <NUM>. The light shielding layer <NUM> has light shielding characteristics to shield light incident from the outside, thereby protecting the channel portion 130n. The light shielding layer <NUM> can be disposed to overlap at least the channel portion 130n of the active layer <NUM>.

Further, the light shielding layer <NUM> can include a metal, and have electrical conductivity. For example, the light shielding layer <NUM> may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), or iron (Fe). The light shielding layer <NUM> can also have a multi-layered structure that includes at least two conductive layers having different respective physical properties.

A buffer layer <NUM> is also disposed on the substrate <NUM> and the light shielding layer <NUM>. The buffer layer <NUM> can include at least one selected from silicon oxide, silicon nitride or metal-based oxide as an insulating material. The buffer layer <NUM> can also have a single-layered structure or a multi-layered structure.

Further, the buffer layer <NUM> planarizes an upper portion of the substrate <NUM>. In addition, the buffer layer <NUM> can have air and moisture barrier properties and insulating properties to protect the thin film transistor <NUM>. The buffer layer <NUM> also allows the light shielding layer <NUM> and the channel portion 130n to be spaced apart from and insulated from each other.

As shown, the active layer <NUM> is disposed on the buffer layer <NUM>. The active layer <NUM> can be formed by a semiconductor material. According to one example of the present disclosure, the active layer <NUM> may include an oxide semiconductor material.

Referring to <FIG>, the active layer <NUM> includes a first active layer <NUM> and a second active layer <NUM> on the first active layer <NUM>. The first active layer <NUM> can be disposed to overlap the second active layer <NUM>. In addition, the second active layer <NUM> can have a mobility greater than that of the first active layer <NUM>. As a result, in the thin film transistor <NUM>, the second active layer <NUM> may serve as a main layer of a current flow. According to one example of the present disclosure, the second active layer <NUM> can have a mobility that is twice or greater than that of the first active layer <NUM>. The second active layer <NUM> can have a mobility of <NUM> to <NUM> times as compared with the first active layer <NUM>.

For example, the first active layer <NUM> can have a mobility of <NUM><NUM>/V·s to <NUM><NUM>/V·s. In more detail, the first active layer <NUM> can have a mobility of <NUM><NUM>/V·s to <NUM><NUM>/V·s, or can have a mobility of about <NUM><NUM>/V·s. The second active layer <NUM> can have a mobility of <NUM><NUM>/V·s or more. In more detail, the second active layer <NUM> can have a mobility of <NUM><NUM>/V·s to <NUM><NUM>/V·s. In more detail, the second active layer <NUM> can have a mobility in the range of <NUM><NUM>/V·s to <NUM><NUM>/V·s or <NUM><NUM>/V·s to <NUM><NUM>/V·s.

Further, the second active layer <NUM> can have a mobility greater than that of the first active layer <NUM> as much as <NUM><NUM>/V·s to <NUM><NUM>/V·s. The second active layer <NUM> can have a mobility greater than that of the first active layer <NUM> as much as <NUM><NUM>/V·s to <NUM><NUM>/V·s, <NUM><NUM>/V·s to <NUM><NUM>/V·s, or <NUM><NUM>/V·s to <NUM><NUM>/V·s.

The first active layer <NUM> can include an oxide semiconductor material having excellent stability. In addition, the first oxide semiconductor layer <NUM> supports the second oxide semiconductor layer <NUM>. Therefore, the first oxide semiconductor layer <NUM> is also referred to as a "support layer. " The first active layer <NUM> can include at least one of, for example, an IGZO(InGaZnO)-based oxide semiconductor material, a GZO(GaZnO)-based oxide semiconductor material, an IGO(InGaO)-based oxide semiconductor material, or a GZTO(GaZnSnO)-based oxide semiconductor material. When the oxide semiconductor material constituting the first active layer <NUM> includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is set to be higher than that of indium (In) based on the number of moles [Ga concentration > In concentration].

The second active layer <NUM> can include an oxide semiconductor material having high mobility. The second active layer <NUM> may include at least one of, for example, an IGZO(InGaZnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO(InSnZnO)-based oxide semiconductor material, an IGZTO(InGaZnSnO)-based oxide semiconductor material, a FIZO(FeInZnO)-based semiconductor material, a ZnO-based oxide semiconductor material, a SIZO(SiInZnO)-based oxide semiconductor material, or a ZnON(Zn-Oxynitride)-based oxide semiconductor material. When the oxide semiconductor material constituting the second active layer <NUM> includes gallium (Ga) and indium (In), a concentration of indium (In) is set to be higher than that of gallium (Ga) based on the number of moles [Ga concentration < In concentration].

However, the type of the oxide semiconductor material is not limited to the above example, and the first active layer <NUM> and the second active layer <NUM> can include other oxide semiconductor materials known in the art. Referring to <FIG>, <FIG> and <FIG>, the active layer <NUM> includes a channel portion 130n, a first connection portion 130a contacting one side of the channel portion 130n, and a second connection portion 130b contacting the other side of the channel portion 130n.

The channel portion 130n overlaps the gate electrode <NUM>, and serves as a channel of the thin film transistor <NUM>. One side of the channel portion 130n contacts the first connection portion 130a, and the other side of the channel portion 130n contacts the second connection portion 130b.

As shown, the first connection portion 130a and the second connection portion 130b of the active layer <NUM> do not overlap the gate electrode <NUM>. In addition, the first connection portion 130a and the second connection portion 130b can be formed by selective conductorization of a semiconductor material. According to one example of the present disclosure, providing a conductivity to a selected portion of the active layer <NUM> will be referred to as selective conductorization. The selective conductorization can be performed by doping, plasma treatment or the like.

For example, selective conductorization for the active layer <NUM> can be performed by dopant doping using the gate electrode <NUM> or photoresist as a mask. Implantation of dopant ions into a selected area of the active layer <NUM> will be referred to as dopant doping. The dopant may include at least one of, for example, boron (B), phosphorus (P), fluorine (F) or hydrogen (H).

When the selective conductorization for the active layer <NUM> is performed by dopant doping or implantation, an area doped with a dopant in the active layer <NUM> is selectively conductorized to become the first connection portion 130a or the second connection portion 130b. An area of the active layer <NUM>, which is not doped with a dopant, is not conductorized, and becomes the channel portion 130n.

In addition, the selective conductorization for the active layer <NUM> can be performed by plasma treatment applied to a process of patterning a gate insulating layer <NUM>. For example, plasma can be used in the process of patterning the gate insulating layer <NUM>, and a portion of the active layer <NUM>, which is in contact with the plasma, can be selectively conductorized to become the first connection portion 130a or the second connection portion 130b. A portion of the active layer <NUM>, which is protected by the gate insulating layer <NUM> and does not contact the plasma, is not conductorized, and can become the channel portion 130n.

The first connection portion 130a and the second connection portion 130b are portions made of an oxide semiconductor material and then given conductivity. Therefore, the first connection portion 130a and the second connection portion 130b have a greater electrical conductivity than that of the channel portion 130n. That is, by conductorization, the first connection portion 130a and the second connection portion 130b can have an electrical conductivity similar to that of a metal used as an electrical wiring.

Referring to <FIG>, the channel portion 130n may include a channel portion 131n of the first active layer <NUM> and a channel portion 132n of the second active layer <NUM>. The first connection portion 130a includes a first connection portion 131a of the first active layer <NUM> and a first connection portion 132a of the second active layer <NUM>. Also, the second connection portion 130b includes a second connection portion 131b of the first active layer <NUM> and a second connection portion 132b of the second active layer <NUM>.

Further, the first connection portion 130a of the active layer <NUM> can be a source area, and the second connection portion 130b thereof can be a drain area. Therefore, the first connection portion 130a can serve as a source electrode, and the second connection portion 130b can serve as a drain electrode. However, the present disclosure is not limited to the above example, and the first connection portion 130a can be a drain area, and the second connection portion 130b can be a source area.

In addition, the channel portion 130n includes a first overlap area OA1 in which the first active layer <NUM> and the second active layer <NUM> overlap each other based on a plan view, and a first non-overlap area NOA1 in which the first active layer <NUM> and the second active layer <NUM> do not overlap each other based on the plan view.

As shown, each of the first active layer <NUM> and the second active layer <NUM> in the channel portion 130n extends from the first connection portion 130a to the second connection portion 130b. As a result, the first overlap area OA1 can extend from the first connection portion 130a to the second connection portion 130b. In addition, the first non-overlap area NOA1 can be extend from the first connection portion 130a to the second connection portion 130b.

Because the first overlap area OA1 and the first non-overlap area NOA1 can be extended from the first connection portion 130a to the second connection portion 130b, both the first overlap area OA1 and the first non-overlap area NOA1 can serve as channels of the thin film transistor <NUM>.

Referring to <FIG> and <FIG>, the second active layer <NUM> can be disposed in the entire area of the channel portion 130n based on the plan view. In addition, the first active layer <NUM> can be disposed only in the first overlap area OA1 without being disposed in the first non-overlap area NOA1. According to one example of the present disclosure, in the channel portion 130n, the second active layer <NUM> can cover an entire upper surface of the first active layer <NUM>.

<FIG> is a cross-sectional view illustrating a first overlap area OA1, and <FIG> is a cross-sectional view illustrating a first non-overlap area NOA1. As shown in <FIG> and <FIG>, the first active layer <NUM> and the second active layer <NUM> are disposed to overlap each other in the first overlap area OA1, whereas only the second active layer <NUM> is disposed in the first non-overlap area NOA1. Therefore, the first overlap area OA1 can have a carrier that is more abundant than that of the first non-overlap area NOA1. In more detail, the first overlap area OA1 can have an electron carrier that is more abundant than that of the first non-overlap area NOA1.

As a result, the ON-current of the thin film transistor <NUM> can be improved by the first overlap area OA1. Therefore, the thin film transistor <NUM> having the first overlap area OA1 can have excellent current characteristics.

Also, the first non-overlap area NOA1 has a carrier having a concentration lower than that of the first overlap area OA1. In more detail, the first non-overlap area NOA1 can have an electron carrier of a concentration lower than that of the first overlap area OA1. Therefore, before the thin film transistor <NUM> is completely turned on by applying a gate voltage, a current increase rate of the thin film transistor can be delayed. As a result, an s-factor (sub-threshold swing) of the thin film transistor <NUM> can be increased.

As described above, the channel portion 130n includes the first overlap area OA1 and the first non-overlap area NOA1 together, so that the ON-current of the thin film transistor <NUM> can be improved and at the same time, the s-factor can be increased.

Referring to <FIG>, the gate insulating layer <NUM> is disposed on the active layer <NUM> and protects the channel portion 130n. The gate insulating layer <NUM> can include at least one of silicon oxide, silicon nitride or metal-based oxide and can have a single-layered structure or a multi-layered structure.

Referring to <FIG>, the gate insulating layer <NUM> can be integrally formed on the entire surface of the substrate <NUM>, but the present disclosure is not limited thereto, and the gate insulating layer <NUM> can be patterned. For example, the gate insulating layer <NUM> can be patterned to have a shape corresponding to that of the gate electrode <NUM>.

Further, the gate electrode <NUM> is disposed on the gate insulating layer <NUM> and overlaps the channel portion 130n of the active layer <NUM>. The gate electrode <NUM> can include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The gate electrode <NUM> can also have a multi-layered structure that includes at least two conductive layers having their respective physical properties different from each other.

An interlayer insulating layer <NUM> is disposed on the gate electrode <NUM> and is an insulating layer made of an insulating material. The interlayer insulating layer <NUM> can be made of an organic material or an inorganic material, or can be made of a stacked body of an organic material layer and an inorganic material layer.

A source electrode <NUM> and a drain electrode <NUM> are disposed on the interlayer insulating layer <NUM>. As shown, the source electrode <NUM> is connected to the active layer <NUM> through a contact hole H2. In more detail, the source electrode <NUM> can be electrically connected to the first connection portion 130a of the active layer <NUM> through the contact hole H2. The source electrode <NUM> can also be connected to the light shielding layer <NUM> through a contact hole H1. As a result, the light shielding layer <NUM> can be connected to the first connection portion 130a of the active layer <NUM>.

In addition, the drain electrode <NUM> is spaced apart from the source electrode <NUM> and is thus connected to the active layer <NUM> through a contact hole H3. In more detail, the drain electrode <NUM> can be electrically connected to the second connection portion 130b of the active layer <NUM> through a contact hole H3.

Each of the source electrode <NUM> and the drain electrode <NUM> can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or their alloy. Each of the source electrode <NUM> and the drain electrode <NUM> can also be formed of a single layer made of a metal or a metal alloy, or can be formed of a multi-layer of two or more layers.

However, the present disclosure is not limited to the above example, and the first connection portion 130a can be a source electrode and an electrode indicated by a reference numeral "<NUM>" can be a connection electrode or a bridge. Likewise, the second connection portion 130b can be a drain electrode and an electrode indicated by a reference numeral "<NUM>" can be a connection electrode or a bridge.

Hereinafter, the s-factor will be described in more detail. At a threshold voltage Vth of a drain-source current graph for a gate voltage of the thin film transistor <NUM>, the s-factor (sub-threshold swing) can be used as an index indicating a change level of the drain-source current for the gate voltage. The s-factor can be described by a current-change graph shown in <FIG>, for example.

In particular, <FIG> illustrates a drain-source current IDS for a gate voltage VGS. At the threshold voltage Vth of the thin film transistor <NUM>, a reciprocal of a slope in the graph of the drain-source current IDS for the gate voltage VGS can be defined as the s-factor. When the slope of the graph is steep, the s-factor is small, and when the slope of the graph is small, the s-factor is large. When the s-factor is large, a change rate of the drain-source current IDS for the gate voltage at a period of the threshold voltage Vth is slow. When the s-factor is large, since the change rate of the drain-source current IDS for the gate voltage is slow, it is easy to adjust a magnitude of the drain-source current IDS by adjusting the gate voltage VGS.

In the display apparatus driven by the current, for example, in an organic light emitting display apparatus, a gray scale of a pixel can be controlled by adjusting the magnitude of the drain-source current IDS of the driving thin film transistor. The magnitude of the drain-source current IDS of the driving thin film transistor is determined by the gate voltage. Therefore, in the organic light emitting display apparatus driven by the current, it is easy to adjust a gray scale of a pixel as the s-factor of the driving thin film transistor TR becomes large.

As a method for adjusting the s-factor of the thin film transistor <NUM> includes adjusting a thickness of the gate insulating layer <NUM>. In more detail, <FIG> are schematic views illustrating a gate voltage applied to a thin film transistor.

As shown, <FIG> schematically illustrates a capacitance Cap that can be generated when a gate voltage VGS is applied to the thin film transistor. In particular, <FIG> schematically illustrates a relation of the capacitance Cap and a voltage before the thin film transistor is completely turned on. In <FIG>, the gate voltage VGS is a voltage between the source electrode <NUM> and the gate electrode <NUM>. The gate voltage VGS can be referred to as a voltage between the first connection portion 130a and the gate electrode <NUM>.

As shown in <FIG>, when the gate voltage VGS is applied to the thin film transistor, a capacitance CGI can be formed between the channel portion 130n of the active layer <NUM> and the gate electrode <NUM> (Gate), and a capacitance CCH can be also formed between the channel portion 130n and the first connection portion 130a (Source). The capacitance CCH formed between the channel portion 130n and the first connection portion 130a (Source) can be referred to as a capacitance formed by a voltage difference between the drain electrode <NUM>, which is a high voltage terminal, and the source electrode <NUM>, which is a low voltage terminal, in the channel portion 130n made of an oxide semiconductor layer having N-type semiconductor characteristics.

The relation between the capacitance Cap and the voltage according to <FIG> can be represented as shown in <FIG>. Referring to <FIG>, due to the capacitance CCH between the channel portion 130n and the first connection portion 130a (Source), not all gate voltages VGS are effectively applied to the channel portion 130n. As a result, voltage loss can be generated.

Referring to <FIG>, when one of the gate voltages VGS, which is effectively applied to the channel portion 130n during driving of the thin film transistor, is referred to as an effective gate voltage Veff, the effective gate voltage Veff can be obtained by the following Equation <NUM>.

In order to increase the s-factor of the thin film transistor <NUM>, when the thickness of the gate insulating layer <NUM> is increased, a capacitance CGI is reduced between the channel portion 130n of the active layer <NUM> and the gate electrode <NUM> (Gate), so that an effective gate voltage Veff, which is effectively applied to the channel portion 130n, among the gate voltages VGS can be reduced. As a result, the s-factor can be increased, but the effective gate voltage Veff calculated by the Equation <NUM> is also reduced, and the ON-Current of the thin film transistor <NUM> is reduced.

On the other hand, according to one example of the present disclosure, because the channel portion 130n includes the first overlap area OA1 and the first non-overlap area NOA1 together, the s-factor of the thin film transistor <NUM> can be increased without reducing the ON-Current.

Next, <FIG> are schematic views illustrating a gate voltage applied to the thin film transistor <NUM> and describing an example that the light shielding layer <NUM> is connected to the source electrode <NUM>. As shown in <FIG>, when the gate voltage VGS is applied to the thin film transistor <NUM>, the capacitance CGI can be formed between the channel portion 130n of the active layer <NUM> and the gate electrode <NUM>, the capacitance CCH can be formed between the channel portion 130n and the first connection portion 130a (Source), and a capacitance CBUF can be additionally formed between the channel portion 130n and the light shielding layer <NUM>.

The relation between the capacitance Cap and the voltage according to <FIG> can be represented as shown in <FIG>. Referring to <FIG>, due to the capacitance CCH between the channel portion 130n and the first connection portion 130a (Source) and the capacitance CBUF between the channel portion 130n and the light shielding layer <NUM>, not all gate voltages VGS are effectively applied to the channel portion 130n, and voltage loss can be generated.

When the light shielding layer <NUM> and the source electrode <NUM> are electrically connected to each other, the capacitance CBUF is additionally generated between the channel portion 130n and the light shielding layer <NUM>, so that a lower capacitance CCH + CBUF causing a voltage loss is increased. In more detail, when a voltage of the gate voltages VGS, which is effectively applied to the channel portion 130n, is referred to as the effective gate voltage Veff in <FIG>, the effective gate voltage Veff can be obtained by the following Equation <NUM>.

Referring to the Equation <NUM>, a denominator value of the Equation <NUM> is increased due to the capacitance CBUF formed between the channel portion 130n and the light shielding layer <NUM>. Therefore, when the capacitance CBUF between the channel portion 130n and the light shielding layer <NUM> is increased, the effective gate voltage Veff is reduced, whereby the increase rate of the drain-source current IDS in the thin film transistor <NUM> is reduced. As a result, the s-factor is increased.

Referring to the Equation <NUM>, the capacitance CBUF between the channel portion 130n and the light shielding layer <NUM> can be increased to increase the s-factor of the thin film transistor <NUM>. A method for increasing the capacitance CBUF between the channel portion 130n and the light shielding layer <NUM> includes reducing a thickness of the buffer layer <NUM>. However, when the thickness of the buffer layer <NUM> is reduced, the channel portion 130n of the thin film transistor <NUM> can be damaged by hydrogen, oxygen or moisture, and the ON-current of the thin film transistor <NUM> is reduced.

According to one example of the present disclosure, because the channel portion 130n includes the first overlap area OA1 and the first non-overlap area NOA1 together, the s-factor of the thin film transistor <NUM> can be increased even though the thickness of the buffer layer <NUM> is not reduced, and at the same time the ON-current of the thin film transistor <NUM> can be also increased.

Next, <FIG> is a cross-sectional view illustrating a thin film transistor <NUM> according to another example of the present disclosure. In particular, <FIG> corresponds to a cross-section taken along line II-II' of <FIG>. Referring to <FIG>, the gate insulating layer <NUM> can be patterned without being formed on the entire surface of the substrate <NUM>. For example, as shown in <FIG>, the gate insulating layer <NUM> can be patterned in the same planar shape as that of the gate electrode <NUM>.

In addition, <FIG> is a plan view illustrating a thin film transistor <NUM> according to still another example of the present disclosure, and <FIG> is a cross-sectional view taken along line Ia-Ia' of <FIG>. Referring to <FIG> and <FIG>, the active layer <NUM> can further include a third active layer <NUM> on the second active layer <NUM>. The third active layer <NUM> can be extended from the first connection portion 130a to the second connection portion 130b in the channel portion 130n. The third active layer <NUM> can also be also disposed in the first connection portion 130a and the second connection portion 130b.

Further, the third active layer <NUM> can protect the second active layer <NUM>. To protect the second active layer <NUM>, the third active layer <NUM> can be made of an oxide semiconductor material having an excellent stability. The third active layer <NUM> can also serve as a protective layer for protecting the second active layer <NUM>.

In addition, the third active layer <NUM> can have a mobility smaller than that of the third active layer <NUM>. The second active layer <NUM> can have a mobility greater than that of the third active layer <NUM> as much as two times or more. In more detail, the second active layer <NUM> can have a mobility of <NUM> to <NUM> times as compared with the third active layer <NUM>. The third active layer <NUM> can have a mobility of <NUM><NUM>/V·s to <NUM><NUM>/V·s. In more detail, the third active layer <NUM> can have a mobility of <NUM><NUM>/V·s to <NUM><NUM>/V·s, or can have mobility of about <NUM><NUM>/V·s.

Further, the second active layer <NUM> can have a mobility greater than that of the third active layer <NUM> as much as <NUM><NUM>/V·s to <NUM><NUM>/V·s. The second active layer <NUM> can also have a mobility greater than that of the third active layer <NUM> as much as <NUM><NUM>/V·s to <NUM><NUM>/V·s, <NUM><NUM>/V·s to <NUM><NUM>/V·s, or <NUM><NUM>/V·s to <NUM><NUM>/V·s.

The third active layer <NUM> can include at least one of, for example, an IGZO(InGaZnO)-based oxide semiconductor material, a GZO(GaZnO)-based oxide semiconductor material, an IGO(InGaO)-based oxide semiconductor material, or a GZTO(GaZnSnO)-based oxide semiconductor material. When the oxide semiconductor material constituting the third active layer <NUM> includes gallium (Ga) and indium (In), a concentration of gallium (Ga) is set to be higher than that of indium (In) based on the number of moles [Ga concentration > In concentration].

Thus, with the third active layer <NUM>, the second active layer <NUM>, which is an intermediate layer in the manufacturing process, can be effectively protected. For example, in the manufacturing process, the first active layer <NUM> can protect the second active layer <NUM>, which is an intermediate layer, from gas, for example, hydrogen (H), moisture (H<NUM>O), oxygen (O<NUM>), etc. generated from the buffer layer <NUM> therebelow or another insulating layer, and the third active layer <NUM> can protect the second active layer <NUM>, which is an intermediate layer, from an etching solution used during a patterning process or gas, for example, hydrogen (H), moisture (H<NUM>O), oxygen (O<NUM>), etc. generated from an upper insulating layer, for example, the gate insulating layer <NUM>, the interlayer insulating layer <NUM>, etc..

Referring to <FIG> and <FIG>, the third active layer <NUM> can be disposed in the first overlap area OA1 and the first non-overlap area NOA1. The third active layer <NUM> can be disposed to cover the entire upper surface of the second active layer <NUM>, but the present disclosure is not limited thereto, and the third active layer <NUM> can cover a portion of the upper surface of the second active layer <NUM>.

Referring to <FIG> and <FIG>, because the third active layer <NUM> is disposed in the first non-overlap area NOA1 and also serves as a protective layer for protecting the second active layer <NUM>, an effect of increasing the carrier due to the third active layer <NUM> is not significant. Therefore, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

Next, <FIG> is a plan view illustrating a thin film transistor <NUM> according to still another example of the present disclosure, and <FIG> is a cross-sectional view taken along line Ib-Ib' of <FIG>. Referring to <FIG> and <FIG>, the active layer <NUM> can include a third active layer <NUM> on the second active layer <NUM>, and the third active layer <NUM> can be disposed on a portion of the upper surface of the second active layer <NUM>. In more detail, the third active layer <NUM> is not disposed in the first non-overlap area NOA1 and is disposed only in the first overlap area OA1.

The third active layer <NUM> is disposed in the first overlap area OA1, so that the upper portion of the second active layer <NUM> can be effectively protected in at least the first overlap area OA1. In addition, the electron carrier of the first overlap area OA1 can be increased due to the carrier included in the third active layer <NUM>. In a structural aspect, a thickness of the first overlap area OA1 is increased due to the third active layer <NUM>, whereby the physical stability of the first overlap area OA1 can be improved. As a result, the stability of the thin film transistor <NUM> can be improved, and the ON-current of the thin film transistor <NUM> can be improved by the first overlap area OA1. On the other hand, as the third active layer <NUM> is not disposed in the first non-overlap area NOA1, the carrier of the first non-overlap area NOA1 is not increased. As a result, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

Next, <FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure, and <FIG> is a cross-sectional view taken along line IV-IV' of <FIG>. The thin film transistor <NUM> of <FIG> further includes a second non-overlap area NOA2 as compared with the thin film transistor <NUM> of <FIG>.

Referring to <FIG> and <FIG>, the channel portion 130n can further include a second non-overlap area NOA in which the first active layer <NUM> and the second active layer <NUM> do not overlap each other based on the plan view. The second non-overlap area NOA2 can be spaced apart from the first non-overlap area NOA1 and extend from the first connection portion 130a to the second connection portion 130b. The first non-overlap area NOA1 and the second non-overlap area NOA2 can be disposed to be spaced apart from each other with the first overlap area OA1 interposed therebetween.

As shown, the first active layer <NUM> may not be disposed in the second non-overlap area NOA2. Further, the second non-overlap area NOA2 includes a carrier (electron carrier) having a concentration lower than that of the first overlap area OA1 in the same manner as the first non-overlap area NOA1. Therefore, the second non-overlap area NOA2 can serve to increase the s-factor of the thin film transistor <NUM> in the same manner as the first non-overlap area NOA1.

Next, <FIG> is a cross-sectional view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure. In particular, <FIG> is a cross-sectional view taken along line IV-IV' of <FIG>.

Referring to <FIG>, the active layer <NUM> can further include a third active layer <NUM> on the second active layer <NUM>. The third active layer <NUM> can be extended from the first connection portion 130a to the second connection portion 130b in the channel portion 130n. The third active layer <NUM> can also be disposed in the first connection portion 130a and the second connection portion 130b.

In addition, the third active layer <NUM> can be disposed in the first overlap area OA1, the first non-overlap area NOA1 and the second non-overlap area NOA2. The third active layer <NUM> can also be disposed to cover the entire upper surface of the second active layer <NUM>, but the present disclosure is not limited thereto, and the third active layer <NUM> can cover a portion of the upper surface of the second active layer <NUM>.

Referring to <FIG>, the third active layer <NUM> is disposed in the first non-overlap area NOA1 and the second non-overlap area NOA2, but an effect of increasing the carrier due to the third active layer <NUM> is not significant. Therefore, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

Next, <FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure, and <FIG> is a cross-sectional view taken along line IVa-IVa' of <FIG>. Referring to <FIG> and <FIG>, the active layer <NUM> can include a third active layer <NUM> on the second active layer <NUM>, and the third active layer <NUM> can be disposed on a portion of the upper surface of the second active layer <NUM>.

In more detail, the third active layer <NUM> can be disposed in the first overlap area OA1. The third active layer <NUM> may not be disposed in the first non-overlap area NOA1. In addition, the third active layer <NUM> may not be disposed in the second non-overlap area NOA2. The third active layer <NUM> is not disposed in the second non-overlap area NOA2, so that a carrier of the second non-overlap area NOA2 may not be increased. As a result, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

Next, <FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure, and <FIG> is a cross-sectional view taken along the line V-V' of <FIG>. The thin film transistor <NUM> of <FIG> further includes a second overlap area OA2 as compared with the thin film transistor <NUM> of <FIG>.

Referring to <FIG> and <FIG>, the channel portion 130n can further include a second overlap area OA2 in which the first active layer <NUM> and the second active layer <NUM> overlap each other based on the plan view. The second overlap area OA2 can be spaced apart from the first overlap area OA1 and extend from the first connection portion 130a to the second connection portion 130b. In addition, the first overlap area OA1 and the second overlap area OA2 can be spaced apart from each other with the first non-overlap area NOA1 interposed therebetween.

According to one example of the present disclosure, the first active layer <NUM> is not disposed in the first non-overlap area NOA1, and can be disposed in the first overlap area OA1 and the second overlap area OA2. Also, the second overlap area OA2 includes a carrier (electron carrier) of a concentration higher than that of the first non-overlap area NOA1 in the same manner as the first overlap area OA1. Therefore, the second overlap area OA2 can serve to improve the ON-current of the thin film transistor <NUM> in the same manner as the first overlap area OA1.

<FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure, and <FIG> is a cross-sectional view taken along line Va-Va' of <FIG>. Referring to <FIG> and <FIG>, the active layer <NUM> can further include a third active layer <NUM> on the second active layer <NUM>. As shown, the third active layer <NUM> can be extended from the first connection portion 130a to the second connection portion 130b in the channel portion 130n. The third active layer <NUM> can be also disposed in the first connection portion 130a and the second connection portion 130b.

Further, the third active layer <NUM> can be disposed in the first overlap area OA1, the first non-overlap area NOA1 and the second overlap area OA2. Also, the third active layer <NUM> can be disposed to cover the entire upper surface of the second active layer <NUM>, but the present disclosure is not limited thereto, and the third active layer <NUM> can cover a portion of the upper surface of the second active layer <NUM>.

Referring to <FIG> and <FIG>, the third active layer <NUM> is disposed in the first non-overlap area NOA1, but the effect of increasing the carrier due to the third active layer <NUM> is not significant. Therefore, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

Next, <FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another example of the present disclosure, and <FIG> is a cross-sectional view taken along the line Vb-Vb' of <FIG>. Referring to <FIG> and <FIG>, the active layer <NUM> can include a third active layer <NUM> on the second active layer <NUM>, and the third active layer <NUM> can be disposed on a portion of the upper surface of the second active layer <NUM>. In more detail, the third active layer <NUM> can be disposed in the first overlap area OA1 and the second overlap area OA2. The third active layer <NUM> may not be disposed in the first non-overlap area NOA1.

As the third active layer <NUM> is not disposed in the first non-overlap area NOA1, the carrier of the first non-overlap area NOA1 is not increased. As a result, an s-factor of the thin film transistor <NUM> can be maintained at a high level.

As described previously, <FIG> are schematic views illustrating a gate voltage applied to a thin film transistor in which the light shielding layer <NUM> is not disposed, and <FIG> are schematic views illustrating a gate voltage applied to a thin film transistor in which the light shielding layer <NUM> is disposed.

As described previously, <FIG> is a graph illustrating a relation between an s-factor and an ON-current. In addition, <FIG> is a graph illustrating threshold voltages of thin film transistors. Referring to <FIG>, in the thin film transistor in which the light shielding layer <NUM> is disposed, when the thickness of the buffer layer BUF <NUM> is increased or the thickness of the gate insulating layer GI <NUM> is reduced, the ON-current of the thin film transistor can be increased, but the s-factor can be reduced.

On the other hand, in the thin film transistor in which the light shielding layer <NUM> is disposed, when the thickness of the buffer layer BUF <NUM> is reduced or the thickness of the gate insulating layer GI <NUM> is increased, the s-factor of the thin film transistor can be increased, but the ON-current can be reduced.

<FIG> illustrates threshold voltages of various thin film transistors. In <FIG>, "Example <NUM>" is a threshold voltage graph for the thin film transistor <NUM> of <FIG>, "Comparative Example <NUM>" is a threshold voltage graph of a thin film transistor in which the thickness of the gate insulating layer <NUM> is reduced to improve the ON-Current, and "Comparative Example <NUM>" is a threshold voltage graph of a thin film transistor in which the thickness of the gate insulating layer <NUM> is increased to improve the s-factor.

Referring to the "Comparative Example <NUM> ," when the thickness of the gate insulating layer <NUM> is reduced, the ON-current of the thin film transistor is improved but the s-factor is reduced. In addition, referring to the "Comparative Example <NUM> ," when the thickness of the gate insulating layer <NUM> is increased, the s-factor of the thin film transistor is increased but the ON-current is reduced. On the other hand, the thin film transistor of the Example <NUM> according to example <NUM> of the present disclosure has excellent ON-current characteristics while having a large s-factor.

Hereinafter, the display apparatus comprising the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> will be described in detail. In particular, <FIG> is a schematic view illustrating a display apparatus <NUM> according to further still another example of the present disclosure.

As shown in <FIG>, the display apparatus <NUM> according to further still another example of the present disclosure includes a display panel <NUM>, a gate driver <NUM>, a data driver <NUM> and a controller <NUM>. Gate lines GL and data lines DL are disposed in the display panel <NUM>, and pixels P are disposed in intersection areas of the gate lines GL and the data lines DL. An image is displayed by driving of the pixels P.

The controller <NUM> controls the gate driver <NUM> and the data driver <NUM>. In addition, the controller <NUM> outputs a gate control signal GCS for controlling the gate driver <NUM> and a data control signal DCS for controlling the data driver <NUM> by using a signal supplied from an external system. Also, the controller <NUM> samples input image data input from the external system, realigns the sampled data and supplies the realigned digital image data RGB to the data driver <NUM>.

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst and a gate clock GCLK. Also, control signals for controlling a shift register can be included in the gate control signal GCS. The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL.

The data driver <NUM> supplies a data voltage to the data lines DL of the display panel <NUM>. In more detail, the data driver <NUM> converts the image data RGB input from the controller <NUM> into an analog data voltage and supplies the data voltage to the data lines DL. The gate driver <NUM> may include a shift register <NUM>.

In addition, the shift register <NUM> sequentially supplies gate pulses to the gate lines GL for one frame by using the start signal and the gate clock, which are transmitted from the controller <NUM>. In this instance, one frame means a time period at which one image is output through the display panel <NUM>. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) disposed in the pixel P.

Also, the shift register <NUM> supplies a gate-off signal capable of turning off the switching device, to the gate line GL for the other period of one frame, at which the gate pulse is not supplied. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

According to one example of the present disclosure, the gate driver <NUM> can be packaged on the substrate <NUM>. In this way, a structure in which the gate driver <NUM> is directly packaged on the substrate <NUM> will be referred to as a Gate In Panel (GIP) structure.

Next, <FIG> is a circuit view illustrating any one pixel P of <FIG>, <FIG> is a plan view illustrating a pixel P of <FIG>, and <FIG> is a cross-sectional view taken along line VI-VI' of <FIG>. The circuit view of <FIG> is an equivalent circuit view for the pixel P of the display apparatus <NUM> that includes an organic light emitting diode (OLED) as a display device <NUM>.

As shown, the pixel P includes a display device <NUM> and a pixel driving circuit PDC for driving the display device <NUM>. The pixel driving circuit PDC of <FIG> includes a first thin film transistor TR1 that is a switching transistor and a second thin film transistor TR2 that is a driving transistor. For example, the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> described in the examples can be used as the second thin film transistor TR2. The thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> described in the examples can be also used as the first thin film transistor TR1.

As shown, the first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL. The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls applying of the data voltage Vdata.

A driving power line PL provides a driving voltage Vdd to the display device <NUM>, and the second thin film transistor TR2 controls the driving voltage Vdd. In addition, the driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode (OLED) that is the display device <NUM>.

When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver <NUM> through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to a gate electrode G2 of the second thin film transistor TR2 connected with the display device <NUM>. Further, the data voltage Vdata is charged in a first capacitor C1 formed between the gate electrode G2 and a source electrode S2 of the second thin film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

The amount of a current supplied to the organic light emitting diode (OLED), which is the display device <NUM>, through the second thin film transistor TR2 is controlled in accordance with the data voltage Vdata, whereby a gray scale of light emitted from the display device <NUM> can be controlled.

Referring to <FIG> and <FIG>, the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the substrate <NUM>. The substrate <NUM> can be made of glass or plastic. Plastic having a flexible property, for example, polyimide (PI) can be used as the substrate <NUM>.

The light shielding layer <NUM> is disposed on the substrate <NUM>. Referring to <FIG> and <FIG>, the light shielding layer <NUM> is disposed only below the second thin film transistor TR2 that is a driving transistor, but the present disclosure is not limited thereto, and the light shielding layer <NUM> can be also disposed below the first thin film transistor TR1.

A buffer layer <NUM> is disposed on the light shielding layer <NUM>. The buffer layer <NUM> is made of an insulating material, and protects active layers A1 and A2 from external moisture or oxygen. The active layer A1 of the first thin film transistor TR1 and the active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer <NUM>. The active layers A1 and A2 may include, for example, a first active layer <NUM>, a second active layer <NUM> and a third active layer <NUM>. The active layers A1 and A2 can have any one of the structures of <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

In addition, a gate insulating layer <NUM> is disposed on the active layers A1 and A2. The gate insulating layer <NUM> may cover entire upper surfaces of the active layers A1 and A2, or may cover only a portion of the active layers A1 and A2. The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer <NUM>. Also, a first capacitor electrode CE1 can be disposed on the gate insulating layer <NUM>. The first capacitor electrode CE1 can be connected to the gate electrode G2 of the second thin film transistor TR2.

An interlayer insulating layer <NUM> is disposed on the gate electrodes G1 and G2 and the first capacitor electrode CE1. The data line DL, the driving power line PL, source electrodes S1 and S2 and drain electrodes D1 and D2 are disposed on the interlayer insulating layer <NUM>. A portion of the data line DL can be extended to become the source electrode S1 of the first thin film transistor TR1. The source electrode S1 of the first thin film transistor TR1 can be connected to the active layer A1 of the first thin film transistor TR1 through a contact hole H11.

Referring to <FIG> and <FIG>, the drain electrode D1 of the first thin film transistor TR1 and the source electrode S2 of the second thin film transistor TR2 are disposed on the interlayer insulating layer <NUM>. The drain electrode D1 of the first thin film transistor TR1 can be connected to the active layer A1 of the first thin film transistor TR1 through a contact hole H12. In addition, the drain electrode D1 of the first thin film transistor TR1 can be connected to the first capacitor electrode CE1 through a contact hole H13. As a result, the data voltage can be applied to the first capacitor electrode CE1 and the gate electrode G2 of the second thin film transistor TR2.

The source electrode S2 of the second thin film transistor TR2 can be connected to the light shielding layer <NUM> through one contact hole H14, and can be connected to the active layer A2 of the second thin film transistor TR2 through another contact hole H15. As a result, the light shielding layer <NUM> can be connected to the source electrode S2 of the second thin film transistor TR2.

In addition, the source electrode S2 of the second thin film transistor TR2 can be extended to become a second capacitor electrode CE2. The second capacitor electrode CE2 overlaps the first capacitor electrode CE1 to form the first capacitor C1. A portion of the driving power line PL can be extended to become the drain electrode D2 of the second thin film transistor TR2. The drain electrode D2 of the second thin film transistor TR2 can be connected to the active layer A2 of the second thin film transistor TR2 through a contact hole H16.

A planarization layer <NUM> is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, the drain electrodes D1 and D2 and the second capacitor electrode CE2. The planarization layer <NUM> planarizes upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

Further, a first electrode <NUM> of the display device <NUM> is disposed on the planarization layer <NUM>. The first electrode <NUM> of the display device <NUM> contacts the source electrode S2 of the second thin film transistor TR2 and the second capacitor electrode CE2 through a contact hole H17 formed in the planarization layer <NUM>.

Also, a bank layer <NUM> is disposed at an edge of the first electrode <NUM>. The bank layer <NUM> defines a light emission area of the display device <NUM>. An organic light emitting layer <NUM> is further disposed on the first electrode <NUM>, and a second electrode <NUM> is disposed on the organic light emitting layer <NUM>. Therefore, the display device <NUM> is completed. The display device <NUM> shown in <FIG> is an organic light emitting diode (OLED). Therefore, the display apparatus <NUM> according to one example of the present disclosure is an organic light emitting display apparatus.

According to another example of the present disclosure, the second thin film transistor TR2 can have a large s-factor. The second thin film transistor TR2 can be used as a driving transistor to improve a gray scale representation capability of the display apparatus <NUM>.

Next, <FIG> is a circuit view illustrating any one pixel P of a display apparatus <NUM> according to further still another example of the present disclosure. In particular, <FIG> is an equivalent circuit view illustrating a pixel P of an organic light emitting display apparatus.

The pixel P of the display apparatus <NUM> shown in <FIG> includes an organic light emitting diode (OLED) that is a display device <NUM> and a pixel driving circuit PDC for driving the display device <NUM>. The display device <NUM> is connected with the pixel driving circuit PDC. In the pixel P, signal lines DL, GL, PL, RL and SCL for supplying a signal to the pixel driving circuit PDC are disposed.

The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving the pixel is supplied to the driving power line PL, a reference voltage Vref is supplied to a reference line RL, and a sensing control signal SCS is supplied to a sensing control line SCL.

Referring to <FIG>, assuming that a gate line of an (n)th pixel P is "GLn ," a gate line of an (n-<NUM>)th pixel P adjacent to the (n)th pixel P is "GLn-<NUM>" and the gate line "GLn-<NUM>" of the (n-<NUM>)th pixel P serves as a sensing control line SCL of the (n)th pixel P. The pixel driving circuit PDC includes, for example, a first thin film transistor TR1 (switching transistor) connected with the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling a magnitude of a current output to the display device <NUM> in accordance with the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (reference transistor) for sensing characteristics of the second thin film transistor TR2.

A first capacitor C1 is positioned between the gate electrode G2 of the second thin film transistor TR2 and the display device <NUM>. The first capacitor C1 is referred to as a storage capacitor Cst. The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transmit the data voltage Vdata, which is supplied to the data line DL, to the gate electrode G2 of the second thin film transistor TR2.

The third thin film transistor TR3 is connected to a first node n1 between the second thin film transistor TR2 and the display device <NUM> and the reference line RL, and thus is turned on or off by the sensing control signal SCS and senses characteristics of the second thin film transistor TR2, which is a driving transistor, for a sensing period. A second node n2 connected with the gate electrode G2 of the second thin film transistor TR2 is connected with the first thin film transistor TR1. The first capacitor C1 is formed between the second node n2 and the first node n1.

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2. When the second thin film transistor TR2 is turned on, the current is supplied to the display device <NUM> through the second thin film transistor TR2 in accordance with the driving voltage Vdd for driving the pixel, whereby light is output from the display device <NUM>.

Next, <FIG> is a circuit view illustrating any one pixel of a display apparatus <NUM> according to further still another example of the present disclosure. The pixel P of the display apparatus <NUM> shown in <FIG> includes an organic light emitting diode (OLED) that is a display device <NUM> and a pixel driving circuit PDC for driving the display device <NUM>. The display device <NUM> is connected with the pixel driving circuit PDC.

The pixel driving circuit PDC includes thin film transistors TR1, TR2, TR3 and TR4. In the pixel P, signal lines DL, EL, GL, PL, SCL and RL for supplying a driving signal to the pixel driving circuit PDC are disposed. In comparison with the pixel P of <FIG>, the pixel P of <FIG> further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL. Also, the pixel driving circuit PDC of <FIG> further includes a fourth thin film transistor TR4 that is an emission control transistor for controlling a light emission timing of the second thin film transistor TR2, in comparison with the pixel driving circuit PDC of <FIG>.

Referring to <FIG>, assuming that a gate line of an (n)th pixel P is "GLn ," a gate line of an (n-<NUM>)th pixel P adjacent to the (n)th pixel P is "GLn-<NUM>" and the gate line "GLn-<NUM>" of the (n-<NUM>)th pixel P serves as a sensing control line SCL of the (n)th pixel P. A first capacitor C1 is positioned between the gate electrode G2 of the second thin film transistor TR2 and the display device <NUM>. Also, a second capacitor C2 is positioned between one of terminals of the fourth thin film transistor TR4, to which a driving voltage Vdd is supplied, and one electrode of the display device <NUM>.

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transmit the data voltage Vdata, which is supplied to the data line DL, to the gate electrode G2 of the second thin film transistor TR2. The third thin film transistor TR3 is connected to the reference line RL, and thus is turned on or off by the sensing control signal SCS and senses characteristics of the second thin film transistor TR2, which is a driving transistor, for a sensing period.

In addition, the fourth thin film transistor TR4 transfers the driving voltage Vdd to the second thin film transistor TR2 in accordance with the emission control signal EM, or shields the driving voltage Vdd. When the fourth thin film transistor TR4 is turned on, a current is supplied to the second thin film transistor TR2, whereby light is output from the display device <NUM>. The pixel driving circuit PDC according to further still another example of the present disclosure can be formed in various structures in addition to the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

According to the present disclosure, the following advantages are obtained.

Claim 1:
A thin film transistor (<NUM>) comprising:
an active layer (<NUM>); and
a gate electrode (<NUM>) at least partially overlapped with the active layer,
wherein the active layer (<NUM>) includes:
a first active layer (<NUM>) and a second active layer (<NUM>) on the first active layer;
a channel (130n);
a first connection portion (130a) contacting a first side of the channel; and
a second connection portion (130b) contacting a second side of the channel,
wherein the channel includes:
a first overlap area (OA1) in which the first active layer and the second active layer overlap each other based on a plan view; and
a first non-overlap area (NOA1) in which the first active layer (<NUM>) and the second active layer (<NUM>) do not overlap each other based on the plan view,
wherein in the channel of the active layer, each of the first active layer and the second active layer extends from the first connection portion (130a) to the second connection portion (130b), and
wherein the second active layer (<NUM>) has a mobility greater than a mobility of the first active layer (<NUM>);
wherein the active layer (<NUM>) further includes a third active layer (<NUM>) on the second active layer (<NUM>),
wherein the third active layer (<NUM>) extends from the first connection portion (130a) to the second connection portion (130b) in the channel, and
wherein the third active layer (<NUM>) has a mobility smaller than a mobility of the second active layer (<NUM>).