Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the sub-<NUM> range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

Devices and methods of the prior art are described by <CIT>; <NPL>); <CIT>, <CIT>, <CIT>. None of these describe a combination of adhesion layers and voids in the plate lines or undercut etching as defined by the independent claims.

The invention is set forth in the independent claims including a memory device comprising the features of claim <NUM> and a method for fabricating a memory device comprising the features of claim <NUM>. Embodiments of the invention are described in the dependent claims.

According to an embodiment the method of fabricating a memory device comprises forming an access transistor at the base level of the memory device. A stack of alternating dummy nitride material and an insulating material is blanket deposited over a substrate and in an isolation region. A node is formed over the access transistor for at least two ferroelectric capacitors, the node formed through the stack of alternating dummy nitride material and the insulating material. A staircase etch is performed on the stack of alternating dummy nitride material in the insulator material. The dummy nitride material is removed during a dummy replacement process by performing an undercut etch on the dummy nitride material selective to the insulating material, which leaves rows of the insulating material and empty spaces therebetween. An adhesion layer is deposited along a top and bottom services of the rows of the insulating material and depositing a conformal metal material on top of the stack and in between the rows of insulating material to begin formation of plate lines. A spacer anisotropic etch is performed to remove excess metal material from the top and sidewalls of the insulating material so that sidewalls of the plate lines are vertically aligned with sidewalls of the insulating material. An interlayer dielectric (ILD) is formed over the isolation region and defining contact and via locations. An etch of the ILD is performed over the contact and Via locations that stops on the metal material to form vias through the ILD and the isolation region that land on each of the plate lines to form separate capacitors that have a common node at the center.

According to an embodiment the method further comprises depositing the dummy nitride material as silicon nitride, aluminum oxide, silicon oxide nitride, or any combination thereof.

According to an embodiment the method further comprises depositing the insulating material as oxide, silicon oxide, silicon dioxide, a carbon doped oxide, or any combination thereof.

According to an embodiment the method further comprises depositing the metal material as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, ruthenium, molybdenum or any combination thereof.

According to an embodiment the method further comprises that forming the node further comprises: etching a hole through the stack of alternating dummy nitride material and the insulating material down to a source or drain of the access transistor; and depositing a ferroelectric or antiferroelectric material conformal to sidewalls of the holes.

According to an embodiment the method further comprises depositing the ferroelectric material as any combination of one or more of: hafnium, zirconium, and oxygen; hafnium, oxygen, and silicon; hafnium, oxygen, and germanium; hafnium, oxygen, and aluminum; hafnium, oxygen, and yttrium; hafnium, oxygen, and lanthanum; lead, zirconium, and titanium; barium, zirconium and titanium; hafnium, zirconium, barium, and titanium; and hafnium, zirconium, barium, and lead.

According to an embodiment the method further comprises depositing the metal material using atomic layer deposition.

According to an embodiment the method further comprises depositing the metal material such that voids are formed in the metal material.

According to an embodiment the method further comprises fabricating the memory device as a 3D FRAM.

According to an embodiment the method further comprises that forming the access transistor further comprises patterning a plurality of substantially parallel bitlines along a first direction within an insulating material over a substrate and forming a plurality of substantially parallel wordlines along a second direction orthogonal to the direction of the bitlines, and forming the access transistor at the intersection of the one of the bitlines and one of the wordlines.

A metal replacement plate line process for 3D-Ferroelectric Random (3D-FRAM) is described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than <NUM> metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments may be implemented to realize a metal replacement plate line process for 3D-Ferroelectric Random (3D-FRAM). To provide context, a FRAM is a random-access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. Conventionally, both FRAM and DRAM are one transistor (1T)/one capacitor (1C) cell arrays, where each cell comprises an access transistor in the front end coupled to a single capacitor. The capacitor may be coupled to a bitline (COB) higher in the stack in the semiconductor back end.

<FIG> illustrates a cross-section of a 3D FRAM memory. The 3D FRAM memory <NUM> comprises a 3D array of ferroelectric capacitors <NUM> arranged in one or more vertical stacks <NUM> or columns, each of the ferroelectric capacitors <NUM> in the stack is coupled to a single access transistor <NUM> at the base of the stack. The 3D FRAM memory <NUM> includes a base level having a plurality of substantially parallel bitlines <NUM> along a first direction. On a base +<NUM> level, the 3D array comprises a plurality of substantially parallel wordlines <NUM> along a second direction, typically orthogonal to the first direction. The access transistor <NUM> is located at the intersection of a respective bitline <NUM> and a respective wordline <NUM> and is coupled to the respective bitline <NUM> and wordline <NUM>. A gate dielectric <NUM> may be along sides of the wordline <NUM> beneath each stack <NUM>.

Each stack <NUM> in the 3D array comprises a first ferroelectric capacitor <NUM> vertically aligned with and coupled to the access transistor <NUM> and at least a second ferroelectric capacitor <NUM> vertically aligned with the first ferroelectric capacitor <NUM> and also coupled to the access transistor <NUM>, wherein both the first ferroelectric capacitor <NUM> and the second ferroelectric capacitor <NUM> are controlled by the access transistor <NUM>. In the example shown, the stack comprises four vertically stacked ferroelectric capacitors <NUM>. In one embodiment, the access transistor <NUM> may be coupled to <NUM>-<NUM> ferroelectric capacitors <NUM>.

Over the access transistor <NUM> is a stack of alternating plate lines <NUM> (e.g., PL1, PL2, PL3, PL4) and an insulating material <NUM> (e.g., an interlayer dielectric (ILD)) that may be substantially parallel to the bitlines <NUM>. In one embodiment, the number of plate lines <NUM> equals the number of ferroelectric capacitors <NUM> in the stack <NUM>. Accordingly, in the example shown, there are four ferroelectric capacitors <NUM>, and four plate lines <NUM> separated by four layers of insulating material <NUM>. Vias <NUM> or pillars are connected to edges of the plate lines <NUM>.

In one embodiment, a node <NUM> of each of the ferroelectric capacitors <NUM> is formed and located in a hole through the stack of alternating plate lines <NUM> and the insulating material <NUM> in alignment with the access transistor <NUM>. The node <NUM> is one of the terminals of each of the ferroelectric capacitors <NUM> and is connected to, or comprises, a drain of the access transistor <NUM>. Thus, the node <NUM> and the drain of the access transistor <NUM> are basically the same electrical point. The node <NUM> is surrounded by a ferroelectric (or antiferroelectric) material <NUM> that is conformal to sidewalls of the hole. The ferroelectric material <NUM> stores the memory state for a bit cell as a form of polarization, which can be switched by an electric field. The node <NUM> is further connected to one plate line <NUM> of each of the ferroelectric capacitors <NUM> in the stack <NUM>. Each of the plate lines <NUM> acts as a first electrode and the node <NUM> acts as a second electrode for the corresponding ferroelectric capacitor <NUM> in the stack <NUM>.

One advantage of the 3D FRAM memory <NUM> is that it enables cell scaling due to immunity to leakage and data is stored in the form of polarization in the capacitor. This type of storage allows the capacitors to be stacked to further scale the cell and achieve X Bit/Area monolithic integration where X is the number of stacked capacitors.

However, the 3D FRAM memory <NUM> is fabricated by a blanket depositing an alternating stack of metal plate lines <NUM> and the insulating material <NUM>. One problem with this process is the stack of thick metal layers cannot be seen through for lithography purposes so that in subsequent processing steps an additional frame reveal mask is required to create openings through the alternating stack of metal plate lines <NUM> and the insulating material <NUM> to reveal the alignment marks on the first level of the wafer. Alignment marks are typically formed on the first level to provide means for registering the photomask for the subsequent photolithography step. The additional frame reveal mask requires an additional lithography step and a high aspect ratio metal etch, which adds costs.

One or more embodiments described herein are directed to structures and architectures for fabricating a 3D-FRAM using a metal replacement plate line fabrication process. Rather than starting the fabrication process by depositing an alternating stack of metal plate lines and the insulating material, one or more embodiments is directed to starting the fabrication process by depositing an alternating stack of dielectric materials, such as silicon nitride and silicon oxide, so that lithography can be used to see through the stack to find the alignment marks, eliminating the need for the additional frame reveal mask and corresponding lithography step. Thereafter, the silicon nitride is removed and replaced with a metal to form the plate lines. In other words, the fabrication process replaces initial use of a metal with a dummy nitride layer, removes the dummy nitride layer in subsequent 3D FRAM processing steps, and replaces the dummy nitride layer with a low resistance metal to complete the processing.

As a result of the fabrication process, a 3D FRAM memory device is formed having an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. (The presence of the voids in the metal material as a result of the dummy nitride replacement process that conformally deposits the metal into horizontal areas between the insulating materials after removal of the dummy nitride. ) Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines.

A 3D-FRAM is fabricated with a dummy nitride process that eliminates the need for an additional frame reveal mask and corresponding lithographic process. It also allows using metals with low resistivity to reduce plateline resistance. The 3D-FRAM having multiple bits per access transistor and a high bit-density of <NUM>-<NUM> times greater than traditional FRAM and DRAM memories with low cost and area per bit. Embodiments may include or pertain to one or more of memory, ferroelectric memory, 3D ferroelectric memory and system-on-chip (SoC) technologies.

<FIG> illustrates a cross-section of a 3D FRAM memory according to the invention. The 3D FRAM memory <NUM> is similar to the 3D FRAM memory <NUM> but has a different fabrication process. The 3D FRAM memory <NUM> includes a base level having a plurality of substantially parallel (e.g., within +-<NUM> degrees) bitlines <NUM> along a first direction and a plurality of substantially parallel wordlines <NUM> along a second direction orthogonal (e.g., within +-<NUM> degrees) to the first direction (e.g., in and out of the page in this view). The base level further comprises a plurality of access transistors <NUM>, where each respective access transistor <NUM> comprises a respective bitline <NUM> and a respective wordline <NUM>. The wordline <NUM> comprises a channel region of the access transistor <NUM> and a gate dielectric <NUM> is along sides of the wordline <NUM>. In one embodiment, the channel region has substantially a same lateral dimension as the wordline <NUM>, and the gate length may be measured in the vertical direction. The access transistor <NUM> may comprise any type of transistor, such as a planar transistor, a thin film transistor, a fin field effect transistor (FinFET), a 2D channel transistor, a polysilicon transistor or any layered transfer transistor, for example.

Over each access transistor <NUM> is an isolation region <NUM> having a series of alternating plate lines <NUM> (e.g., PL1, PL2, PL3, PL4) and an insulating material <NUM> (e.g., an interlayer dielectric (ILD)) formed therein. The plate lines <NUM> each comprise an adhesion material <NUM> on a top and a bottom thereof and a metal material <NUM> in between the adhesion material <NUM>, where the metal material <NUM> has one or more voids <NUM> formed therein. The voids <NUM> are a result of a dummy nitride replacement process of the disclosed embodiments that is used to fabricate the 3D FRAM memory <NUM>, as explained further below.

The alternating plate lines <NUM> and an insulating material <NUM> may be substantially parallel to the bitlines <NUM> in one embodiment. The 3D FRAM memory <NUM> further comprises a 3D array of two or more stacks of ferroelectric capacitors <NUM> that are formed over the access transistor <NUM> and through the series of alternating plate lines <NUM> and the insulating material <NUM>, such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and where the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor <NUM>. A plurality of vias <NUM> is formed through an interlayer dielectric (ILD) <NUM> and the isolation region <NUM> so that each via <NUM> lands on a respective one of the plate lines <NUM>. In one embodiment, the plurality of vias <NUM> comprise the same metal material <NUM> as the plate lines <NUM>.

The ferroelectric capacitors <NUM> are arranged in a vertical stack <NUM> or column, where the stack <NUM> of ferroelectric capacitors <NUM> is coupled to the access transistor <NUM> at the base of the stack <NUM>. Each stack <NUM> in the 3D array comprises a first ferroelectric capacitor <NUM> vertically aligned with and coupled to the access transistor <NUM> and at least a second ferroelectric capacitor <NUM> vertically aligned with the first of ferroelectric capacitor <NUM> and also coupled to the access transistor <NUM>, wherein both the first ferroelectric capacitor <NUM> and the second ferroelectric capacitor <NUM> are controlled by the access transistor <NUM>. In the example shown, each stack <NUM> in the 3D array comprises four vertically stacked ferroelectric capacitors <NUM>. In one embodiment, each access transistor <NUM> may be coupled to <NUM>-<NUM> ferroelectric capacitors <NUM>.

In one embodiment, the number of plate lines <NUM> equals the number of ferroelectric capacitors <NUM> in the stack <NUM>. Accordingly, in the example shown, there are four ferroelectric capacitors <NUM>, and four plate lines <NUM> separated by four layers of insulating material <NUM>. In one embodiment, a node <NUM> of each of the capacitors <NUM> is formed and located in a hole <NUM> through the stack of alternating plate lines <NUM> and the insulating material <NUM> in alignment with the corresponding channel region and the access transistor <NUM>.

The node <NUM> is one of the terminals of each of the ferroelectric capacitors <NUM> and is connected to, or comprises, a drain of the access transistor <NUM>. Thus, the node <NUM> and the drain of the access transistor <NUM> are basically the same electrical point. The node <NUM> is surrounded by a ferroelectric (or antiferroelectric) material <NUM> that is conformal to sidewalls of the hole <NUM>. The ferroelectric material <NUM> stores the memory state for a bit cell as a form of polarization, which can be switched by an electric field. The node <NUM> is further connected to one plate line <NUM> of each of the ferroelectric capacitors <NUM> in the stack <NUM>. Each of the plate lines <NUM> acts as a first electrode and the node <NUM> acts as a second electrode for the corresponding ferroelectric capacitor <NUM> in the stack <NUM>. In this embodiment, the bitline <NUM> may be the source of the access transistor <NUM>.

As described previously, the number of plate lines <NUM> may range from <NUM>-<NUM> using existing ferroelectric materials in the hole <NUM>. The hole <NUM> may be approximately <NUM>-<NUM> in diameter/width, and in some embodiments up to <NUM>. The plate lines <NUM> may be up to approximately <NUM>-<NUM> in thickness, while the insulating material <NUM> may be up to approximately <NUM> in thickness. In one embodiment, the nodes <NUM> in each stack <NUM> may be up to approximately a maximum <NUM> microns in height (<NUM> times x <NUM> plate lines). The node <NUM> and the channel region are aligned and have the same width, which provides the best area for a memory cell.

In some embodiments, the node <NUM> may comprise conductive material(s), e.g., metals, such as titanium, titanium nitride, or SrRuO<NUM> (SRO), as examples.

In some embodiments, one or more of the bitlines <NUM>, the wordlines <NUM>, the plate lines <NUM> and the via <NUM> may comprise conductive material(s), e.g., metals, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, and/or ruthenium, among other conductive materials and/or combinations thereof.

In some embodiments, the ferroelectric/antiferroelectric material <NUM> comprising the ferroelectric capacitor may include, for example, materials exhibiting ferroelectric behavior at thin dimensions, such as hafnium zirconium oxide (HfZrO, also referred to as HZO, which includes hafnium, zirconium, and oxygen), zirconium oxide ZrO, Lanthanum-doped hafnium oxide La-HfO, Lanthanum-doped hafnium zirconium oxide La-HZO, silicon-doped (Si-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and silicon), germanium-doped (Ge-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and germanium), aluminum-doped (Al-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and aluminum), yttrium-doped (Y- doped) hafnium oxide (which is a material that includes hafnium, oxygen, and yttrium), lead zirconate titanate (which is a material that includes lead, zirconium, and titanium), barium zirconate titanate (which is a material that includes barium, zirconium and titanium), and combinations thereof. Some embodiments include hafnium, zirconium, barium, titanium, and/or lead, and combinations thereof. In one embodiment, the ferroelectric material <NUM> may range from approximately <NUM> to <NUM> in thickness.

In one embodiment, insulating material <NUM> comprises interlayer dielectric (ILD) layers. In one embodiment, the insulating material <NUM> is an oxide layer, e.g., a silicon oxide layer. In one embodiment, insulating material <NUM> is a low-k dielectric, e.g., silicon dioxide, silicon oxide, carbon doped oxide ("CDO"), or any combination thereof. In one embodiment, the insulating material <NUM> can include a nitride, oxide, a polymer, phosphosilicate glass, "fluorosilicate ( "SiOF" ( glass, organosilicate glass ( "SiOCH or any combination thereof. In another embodiment, the insulating materials <NUM> can include a nitride layer, e.g., silicon nitride layer. In alternative embodiments, the insulating materials <NUM> can include an aluminum oxide, silicon oxide nitride, other oxide/nitride layer, any combination thereof, or other electrically insulating layer determined by an electronic device design.

Each ferroelectric capacitor <NUM> and plate line <NUM> combination forms one of the bit cells that are vertically stacked over the access transistor <NUM>. The dimensional requirements of the bit cells are determined primarily by the ferroelectric capacitor <NUM> or the wordline pitch and bitline pitch. The disclosed embodiment provide a 3D FRAM memory <NUM> having vertical geometry that provides benefits of <NUM>-<NUM><NUM>× area/bit and cost/bit scaling. In one embodiment, the 3D FRAM memory <NUM> may have a bit cell area of <NUM>F<NUM>/n, where n ≈ <NUM>.

The dummy replacement process will now be described. In general, the process for fabricating a 3D FRAM comprises forming an access transistor at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and an insulating material substantially parallel to the wordlines are formed over the access transistor. Two or more ferroelectric capacitors are formed over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. The plate lines are formed using dummy replacement process, which comprises depositing a dummy nitride material in locations of the plate lines between the insulating material. An undercut etch is performed on the dummy nitride that is selective to the insulating material, leaving rows of the insulating material and empty spaces therebetween. An adhesion layer is deposited along a top and bottom surfaces of the rows of the insulating material, and a conformal metal material is deposited between the rows of insulating material to form the plate lines.

<FIG> illustrate cross-sectional views showing a process for fabricating a 3D FRAM according to the invention in further detail, where like reference numerals from <FIG> have like reference numerals. For brevity, <FIG> illustrate the process after the standard fabrication process of forming an array of FEOL access transistors <NUM> (not shown) at the base level of the 3D FRAM. This may be done by lithography to form pattern a plurality of substantially parallel bitlines <NUM> along a first direction within an insulating material over a substrate and forming a plurality of substantially parallel wordlines <NUM> along a second direction orthogonal to the direction of the bitlines <NUM>, and forming access transistors at the intersections of the bitlines and wordlines.

<FIG> shows the process after a stack of alternating dummy nitride material <NUM> and an insulating material <NUM> are blanket deposited over a substrate and in an isolation region <NUM>, and more specifically over the FEOL transistors in the base level. Depositing the dummy nitride material <NUM> is in contrast to depositing metal plate lines or doped poly-silicon line from the beginning of the fabrication process. In one embodiment, the dummy nitride material <NUM> comprises silicon nitride. In alternative embodiments, the dummy nitride material <NUM> can include an aluminum oxide, silicon oxide nitride, other oxide/nitride layer, any combination thereof, or other electrically insulating layer determined by an electronic device design. In one embodiment, the insulating material <NUM> may comprise an oxide layer, e.g., a silicon oxide layer. In another embodiment, insulating material <NUM> is a low-k dielectric, e.g., silicon dioxide, carbon doped oxide ("CDO"), or any combination thereof.

<FIG> further shows that after the deposition, a node <NUM> is formed over the access transistor for at least two ferroelectric capacitors, wherein the node <NUM> is formed through the stack of alternating dummy nitride material <NUM> and the insulating material <NUM>. In further detail, a lithographic process is performed to etch holes <NUM> through the stack of alternating dummy nitride material <NUM> and the insulating material <NUM> down to a source or drain of the access transistor. A ferroelectric (or antiferroelectric) material <NUM> is deposited conformal to sidewalls of the holes <NUM> and spacerized. The remainder of the hole <NUM> is filled with a metal and planarized to form the node <NUM>.

<FIG> shows the process after a staircase etch is performed on the stack of alternating dummy nitride material <NUM> and the insulating material <NUM>. The staircase etch begins by depositing a thick hardmask on top of the stack, and a first etch is performed from the top of the stack of the nitride/insulating material insulating layers down to a top of the bottom insulating material <NUM> to form the first stairstep. An isotropic etch is performed on the hardmask so that the hardmask shrinks on four sides, where one of the sides stops vertically over the position of the next stairstep. A second etch is performed on the stack of the nitride/insulating material insulating layers down to the top of the second to bottom insulating material <NUM> to form a second stairstep. Another isotropic etch is performed on the hardmask and the process repeats until the top nitride/insulating material insulating layer is etched.

<FIG> shows the process after the staircase etch, the dummy nitride material <NUM> is removed during dummy replacement process by performing an undercut etch selective to the insulating material <NUM>. The undercut etch leaves rows the insulating material <NUM> and empty spaces between rows of the insulating material <NUM>. The rows of the insulating material <NUM> are attached to and supported by the node <NUM> and by the isolation region <NUM> along the sides (shown in black).

Anywhere up to this point, a lithography step may be performed through the stack of the nitride/insulating material insulating layers to see the alignment marks on the first level of the wafer through the stack without having to each through a stack of metal.

<FIG> shows the dummy nitride material <NUM> is replaced by depositing an adhesion layer along <NUM> top and bottom surfaces of the rows of insulating material <NUM>, and by depositing a conformal metal material <NUM> on top of the stack and in-between the rows of insulating material <NUM> to begin formation of plate lines <NUM>. In one embodiment, the metal material <NUM> is deposited using atomic layer deposition (ALD). Due to the conformal deposition process, voids/keyholes or lines, hereinafter voids <NUM>, may be present in the metal material <NUM> comprising the plate as a result of the metals touching from top and bottom during the ALD process. In one embodiment, the metal material <NUM> used as a replacement may be the same or different as a metal material used for the node <NUM>.

In one embodiment, the adhesion layer <NUM> may comprise titanium nitride and/or tantalum nitride. The metal material <NUM> may comprise metals, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, tungsten nitride, molybdenum, and/or ruthenium, among other conductive materials and/or combinations thereof. For instance, in some cases in which a given conductive line comprises Cu, for example, it may be desirable to include between such conductive line and insulating material <NUM> a barrier and/or adhesion layer comprising a material such as, but not necessarily limited to: tantalum (Ta); tantalum nitride (TaN); titanium nitride (TiN); and the like.

<FIG> shows the process after anisotropic/vertical etch is performed to directionally remove excess metal material <NUM> from the top and sidewalls of the insulating material <NUM> on each of the stair steps so that sidewalls of the plate lines <NUM> are vertically aligned with sidewalls of the insulating material <NUM>. The anisotropic/vertical etch only etches the metal material <NUM> and stops on the next layer of insulating material <NUM> to isolate the plate lines <NUM>.

<FIG> shows the process after another ILD <NUM> is formed over isolation region <NUM>. A lithographic process is performed on the ILD <NUM> to define contact and via locations. An etch is performed through the ILD <NUM> over the contact and via locations that stops on the metal material <NUM> to form vias <NUM> through the ILD <NUM> and isolation region <NUM> that land on each of the plate lines <NUM> to form separate capacitors <NUM> that have a common node <NUM> at the center.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus, <FIG> are top views of a wafer and dies that include one or more ferroelectric trench capacitors, in accordance with one or more of the embodiments disclosed herein.

Referring to <FIG>, a wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having integrated circuit (IC) structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more ferroelectric trench capacitors, such as described above. After the fabrication of the semiconductor product is complete, the wafer <NUM> may undergo a singulation process in which each of the dies <NUM> is separated from one another to provide discrete "chips" of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer <NUM> (e.g., not singulated) or the form of the die <NUM> (e.g., singulated). The die <NUM> may include one or more embedded non-volatile memory structures based independently scaled selectors and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer <NUM> or the die <NUM> may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>. For example, a memory array formed by multiple memory devices may be formed on a same die <NUM> as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

<FIG> illustrates a block diagram of an electronic system <NUM>, in accordance with an embodiment of the present disclosure. The electronic system <NUM> can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system <NUM> may include a microprocessor <NUM> (having a processor <NUM> and control unit <NUM>), a memory device <NUM>, and an input/output device <NUM> (it is to be appreciated that the electronic system <NUM> may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system <NUM> has a set of instructions that define operations which are to be performed on data by the processor <NUM>, as well as, other transactions between the processor <NUM>, the memory device <NUM>, and the input/output device <NUM>. The control unit <NUM> coordinates the operations of the processor <NUM>, the memory device <NUM> and the input/output device <NUM> by cycling through a set of operations that cause instructions to be retrieved from the memory device <NUM> and executed. The memory device <NUM> can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device <NUM> is embedded in the microprocessor <NUM>, as depicted in <FIG>. In an embodiment, the processor <NUM>, or another component of electronic system <NUM>, includes one or more ferroelectric trench capacitors, such as those described herein.

<FIG> is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more ferroelectric trench capacitors, in accordance with one or more of the embodiments disclosed herein.

Referring to <FIG>, an IC device assembly <NUM> includes components having one or more integrated circuit structures described herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>. Generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include a number of ferroelectric trench capacitors, such as disclosed herein.

In some embodiments, the circuit board <NUM> may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>. It is to be appreciated that additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), or any other suitable component. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a ball grid array (BGA) of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the disclosure. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more ferroelectric trench capacitors, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Claim 1:
A memory device (<NUM>), comprising:
an access transistor (<NUM>) comprising a bitline (<NUM>) and a wordline (<NUM>);
a series of alternating plate lines (<NUM>) and an insulating material (<NUM>) over the access transistor (<NUM>), the plate lines (<NUM>) comprising an adhesion material (<NUM>) on a top and a bottom thereof and a metal material (<NUM>) in between the adhesion material (<NUM>), of the metal material (<NUM>) having one or more voids (<NUM>) therein;
two or more ferroelectric capacitors (<NUM>) over the access transistor (<NUM>) and through the series of alternating plate lines (<NUM>) and an insulating material (<NUM>) such that a first one of the ferroelectric capacitors (<NUM>) is coupled to a first one of the plate lines (<NUM>) and a second one of the ferroelectric capacitors (<NUM>) is coupled to a second one of the plate lines (<NUM>), and wherein the two or more ferroelectric capacitors (<NUM>) are each coupled to and controlled by the access transistor (<NUM>); and
a plurality of vias (<NUM>) each via (<NUM>) landing on a respective one of the plate lines (<NUM>), the plurality of vias (<NUM>) comprising a same metal material as the plate lines (<NUM>).