Patent Description:
Radio frequency (RF) switches are commonly used in communication transceivers to selectively connect transmitter and receiver circuitry to an antenna or other communication means. To configure the transceiver in a transmit state, an RF switch is controlled to provide a signal path between transmitter and antenna ports of the RF switch, while establishing a high impedance (e.g., open circuit) between the antenna and receiver ports of the RF switch. Conversely, to configure the transceiver in a receive state, the RF switch is controlled to provide a signal path between the antenna and receiver ports, while establishing a high impedance (e.g., open circuit) between the transmitter and antenna ports.

Some RF switches include stacks (i.e., series-coupled arrangements) of field effect transistors (FETs) between their transmit, receive, and antenna ports to achieve higher power handling capability. However, non-uniform RF voltage distribution across the FETs in a stack may result in a relatively low power handling capability for the stack. Conventional techniques for balancing the RF voltage distribution may result in undesirably high levels of leakage currents when the stack is in the off state, which may in turn lead to undesirably high signal losses. Accordingly, what are needed are RF switches that are capable of withstanding higher off-state RF voltages, when compared with conventional RF switches, while achieving lower off-state leakage currents. <CIT> describes a harmonic cancellation circuit for an RF switch branch.

Embodiments of the inventive subject matter include radio frequency (RF) switches and transceivers for use in cellular base stations or other applications. In various embodiments, an RF switch includes at least one branch with a stack of series-coupled transistors. The stack includes a capacitor network coupled between terminals of the transistors, and the capacitor network functions to balance RF voltages (or more generally, "AC voltages") across the transistors when the stack is in an off state. At least one capacitor in the capacitor network is coupled across multiple transistors in the stack, which may result in reduced off-state leakage currents, when compared with conventional stacks with capacitive balancing networks. This configuration enables the stack to withstand relatively high power signals with relatively low off-state leakage currents and associated signal losses.

Before describing RF switch embodiments in detail, examples of systems, devices, and modules in which such RF switch embodiments may be implemented are described in conjunction with <FIG>. It is to be understood that the later-described RF switch embodiments may be implemented in a wide variety of other systems, devices, modules, and circuits. Therefore, the example system, device, and module illustrated in <FIG> are not to be construed as limiting the scope of the inventive subject matter.

<FIG> is a simplified block diagram of an example of an RF transceiver system <NUM> that includes an RF switch <NUM>, a transmitter <NUM>, a receiver <NUM>, an antenna <NUM>, and an RF switch controller <NUM>. Transceiver system <NUM> is a half-duplex transceiver, in which only one of the transmitter <NUM> or the receiver <NUM> are coupled, through the RF switch <NUM>, to the antenna <NUM> at any given time. More specifically, the state of the RF switch <NUM> is controlled by RF switch controller <NUM> to alternate between coupling an RF transmit signal produced by the transmitter <NUM> to the antenna <NUM>, or coupling an RF receive signal received by the antenna <NUM> to the receiver <NUM>.

The transmitter <NUM> may include, for example, a transmit (TX) signal processor <NUM> and a power amplifier <NUM>. The transmit signal processor <NUM> is configured to produce transmit signals, and to provide the transmit signals to the power amplifier <NUM>. The power amplifier <NUM> amplifies the transmit signals and provides the amplified transmit signals to the RF switch <NUM>. The receiver <NUM> may include, for example, a receive amplifier <NUM> (e.g., a low noise amplifier) and a receive (RX) signal processor <NUM>. The receive amplifier <NUM> is configured to amplify relatively low power received signals from the RF switch <NUM>, and to provide the amplified received signals to the receive signal processor <NUM>. The receive signal processor <NUM> is configured to consume or process the receive signals.

During each transmit time interval, when the transceiver <NUM> is in a "transmit mode," the RF switch controller <NUM> controls the RF switch <NUM> to be in a first or "transmit" state, as depicted in <FIG>, in which a conductive transmit signal path is established between transmitter node <NUM> and antenna node <NUM>, and in which a receive signal path is in a high impedance state (e.g., open circuit) between antenna node <NUM> and receiver node <NUM>. Conversely, during each receive time interval, when the transceiver <NUM> is in a "receive mode," the RF switch controller <NUM> controls the RF switch <NUM> to be in a second or "receive" state, in which a conductive receive signal path, indicated by a dashed line in <FIG>, is established between antenna node <NUM> and receiver node <NUM>, and in which the transmit signal path is in a high impedance state (e.g., open circuit) between transmitter node <NUM> and antenna node <NUM>.

<FIG> is a simplified block diagram of another example of RF transceiver system <NUM> that includes an RF switch <NUM>, a circulator <NUM>, a transmitter <NUM>, a receiver <NUM>, an antenna <NUM>, and an RF switch controller <NUM>. The transmitter <NUM> and the receiver <NUM> are coupled to the antenna <NUM> through the circulator <NUM>. More specifically, the circulator <NUM> is a three-port device, with a first port <NUM> coupled to the transmitter <NUM>, a second port <NUM> couplable to the receiver <NUM> through RF switch <NUM>, and a third port <NUM> coupled to the antenna <NUM>. The RF switch <NUM> also is a three-port device, with a first port <NUM> coupled to the receiver port <NUM> of the circulator <NUM>, a second port <NUM> coupled to the receiver <NUM>, and a third port <NUM> coupled to a ground reference node <NUM> through a resistor <NUM>.

Again, the transmitter <NUM> may include, for example, a TX signal processor <NUM> and a power amplifier <NUM>. The transmit signal processor <NUM> is configured to produce transmit signals, and to provide the transmit signals to the power amplifier <NUM>. The power amplifier <NUM> amplifies the transmit signals and provides the amplified transmit signals to the antenna <NUM> through the circulator <NUM>. The receiver <NUM> may include, for example, a receive amplifier <NUM> (e.g., a low noise amplifier) and an RX signal processor <NUM>. The receive amplifier <NUM> is configured to amplify relatively low power received signals received from the antenna <NUM> (through the circulator <NUM> and the RF switch <NUM>), and to provide the amplified received signals to the receive signal processor <NUM>. The receive signal processor <NUM> is configured to consume or process the receive signals.

The circulator <NUM> is characterized by a signal-conduction directivity, which is indicated by the arrows within the depiction of circulator <NUM>. Essentially, RF signals may be conveyed between the circulator ports <NUM>-<NUM> in the indicated direction (counter-clockwise), and not in the opposite direction (clockwise). Accordingly, during normal operations, signals may be conveyed through the circulator <NUM> from transmitter port <NUM> to antenna port <NUM>, and from antenna port <NUM> to receiver port <NUM>, but not directly from transmitter port <NUM> to receiver port <NUM> or from receiver port <NUM> to antenna port <NUM>.

In some situations, while the transceiver <NUM> is in the transmit mode, the circulator <NUM> may not be able to convey signal energy received through transmitter port <NUM> from the transmitter <NUM> to the antenna <NUM> through antenna port <NUM>. For example, the antenna <NUM> may be disconnected from the antenna port <NUM>, or may otherwise be in a very high impedance state. In such situations, the circulator <NUM> may convey signal energy from the transmitter <NUM> (i.e., signal energy received through transmitter port <NUM>) past the antenna port <NUM> to the receiver port <NUM>. To avoid conveying transmitter signal energy into the receiver <NUM> while the transceiver <NUM> is in the transmit mode, the RF switch controller <NUM> operates the RF switch <NUM> as a fail-safe switch by coupling the first port <NUM> to a ground reference node <NUM>.

More specifically, when the transceiver <NUM> is in a receive mode, the RF switch <NUM> is controlled by RF switch controller <NUM> to be in a receive state, as shown in <FIG>. In the receive state, the receiver port <NUM> of the circulator <NUM> is coupled through RF switch <NUM> to the receiver <NUM> (i.e., RF switch controller <NUM> configures RF switch <NUM> to have a conductive path between ports <NUM> and <NUM>, and a high-impedance, open-circuit condition between ports <NUM> and <NUM>). Conversely, when the transceiver <NUM> is in a transmit mode, the RF switch <NUM> is controlled by RF switch controller <NUM> to be in a transmit state, in which the receiver port <NUM> of the circulator <NUM> is coupled through the RF switch <NUM> to the ground termination <NUM> through resistor <NUM> (i.e., RF switch controller <NUM> configures RF switch <NUM> to have a conductive path, indicated by a dashed line in <FIG>, between ports <NUM> and <NUM>, and a high-impedance, open-circuit condition between ports <NUM> and <NUM>). Accordingly, if the transmitter signal energy bypasses the antenna port <NUM> while the transceiver <NUM> is in the transmit mode, any signal energy that is conveyed through the receiver port <NUM> of the circulator <NUM> to the RF switch <NUM> will be shunted to the ground termination <NUM> through port <NUM> of the RF switch <NUM>.

The RF transceiver systems <NUM>, <NUM> (<FIG>) may be physically implemented using a variety of active and passive electrical devices, which may be housed in one or more device packages and/or on one or more printed circuit boards (PCBs) and/or other substrates. More specifically, various components of the RF transceiver systems <NUM>, <NUM> may be implemented in self-contained modules or electrical devices, which may be coupled to a substrate that electrically connects the module/devices to other portions of the RF transceiver system <NUM>, <NUM>. As used herein, the term "module" means a set of active and/or passive electrical devices (e.g., ICs and components) that are physically contained within a single housing (e.g., the device(s) are coupled to a common "module substrate" or within a single device package). A "module" also includes a plurality of conductive terminals for electrically connecting the set of devices to external circuitry that forms other portions of an electrical system. Essentially, the module substrate configuration, the method of coupling the device(s) to the module's terminals, and the number of devices within the module defines the module type. For example, in various embodiments, a module may be in the form of a PCB-based system, a surface mount device, a chip carrier device, a ball, pin, or land grid array device, a flat package device (e.g., a quad or dual flat no-lead package), a chip scale packaged device, a system-in-package (SiP) device, or in the form of some other type of integrated circuit package. Although two particular types of modules/devices are described below in conjunction with <FIG>, it is to be understood that embodiments of the inventive subject matter may be included in other types of modules/devices, as well.

For example, <FIG> is a top view of a device <NUM> that embodies a portion of the RF transceiver system <NUM> of <FIG>, in accordance with an embodiment. More specifically, <FIG> illustrates that portions of the transceiver may be packaged in a surface mount package. Device <NUM> is packaged as a quad flat no-lead (QFN) device, which includes a conductive pad <NUM> and a plurality of terminals (e.g., terminals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) held in a fixed spatial relationship with non-conductive encapsulation <NUM> (e.g., plastic encapsulation). Device <NUM> also includes a plurality of ICs coupled to the conductive pad <NUM>, including an RF switch integrated circuit (IC) <NUM> (e.g., an IC that embodies RF switch <NUM>, <FIG>), a receive amplifier IC <NUM> (e.g., receive amplifier <NUM>, <FIG>), a receive matching circuit IC <NUM>, and an RF switch controller IC <NUM> (e.g., an IC that embodies RF switch controller <NUM>, <FIG>). In addition, device <NUM> includes a transmit signal input terminal <NUM> (e.g., corresponding to transmitter node <NUM>, <FIG>), a receive signal output terminal <NUM> (e.g., corresponding to receiver node <NUM>, <FIG>), an antenna terminal <NUM> (e.g., corresponding to antenna terminal <NUM>, <FIG>), a transmit/receive (TX/RX) control signal terminal <NUM>, one or more ground terminals <NUM>, <NUM>, and one or more power terminals <NUM>.

The various ICs <NUM>, <NUM>, <NUM>, <NUM> and terminals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>-<NUM> are electrically connected together through a plurality of wirebonds (e.g., wirebond <NUM>). In other embodiments, various ones of the ICs <NUM>, <NUM>, <NUM>, <NUM> and terminals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>-<NUM> may be electrically connected together using other conductive structures. In various embodiments, the device <NUM> may be housed in an air-cavity package or an overmolded (e.g., encapsulated) package, although the device <NUM> may be considered to be complete without such packaging, as well.

After incorporation of device <NUM> into a transceiver system (e.g., system <NUM>, <FIG>), and during operation of the transceiver system, power and ground reference voltages may be provided to device <NUM> through power and ground terminals <NUM>-<NUM>. RF switch controller IC <NUM> may receive transmit/receive mode control signals through a control signal terminal <NUM>. Based on the received mode control signals, the RF switch controller IC <NUM> provides switch control signals to, or "drives", the control terminals (e.g., gates) of various transistors (e.g., transistors within branches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) of the RF switch IC <NUM>. As will be described in more detail later, the switch control signals determine whether each of the various transistors is in a conducting or non-conducting state at any given time. More specifically, the switch control signals determine whether the RF switch IC <NUM> is in a transmit state (i.e., a state in which the switch is configured to convey an RF signal from the transmitter <NUM> to the antenna <NUM>) or a receive state (i.e., a state in which the switch is configured to convey an RF signal from the antenna <NUM> to the receiver <NUM>) at any given time.

When the switch control signals configure the RF switch IC <NUM> in the transmit state, transmit signals received by the RF switch IC <NUM> from a power amplifier (e.g., power amplifier <NUM>, <FIG>) through the transmit signal input terminal <NUM> are passed through the RF switch IC <NUM> to the antenna terminal <NUM>. Conversely, when the switch control signals place the RF switch IC <NUM> in the receive state, signals received from the antenna terminal <NUM> are passed through the RF switch IC <NUM> to the receive matching circuit IC <NUM>. The receive matching circuit IC <NUM> may include one or more integrated passive devices (e.g., capacitors, inductors, and/or resistors). The integrated passive devices, along with inductances of the wirebonds <NUM> between the receive matching circuit IC <NUM>, the RF switch IC <NUM>, and the receive amplifier IC <NUM>, compose an impedance matching circuit between the RF switch IC <NUM> and the receive amplifier IC <NUM>. In an alternate embodiment, the receive matching circuit IC <NUM> may be replaced by discrete components. Either way, the impedance matching circuit also may perform filtering of receive signals that pass from the RF switch IC <NUM> to the receive amplifier IC <NUM> through the impedance matching circuit. The receive amplifier IC <NUM> receives the receive signals from the receive matching circuit IC <NUM>, and amplifies the receive signals. The receive amplifier IC <NUM> then provides the amplified receive signals to receive signal output terminal <NUM>.

<FIG> is a perspective view of a module <NUM> that embodies a portion of the RF transceiver system <NUM> of <FIG>, in accordance with an embodiment. More specifically, <FIG> illustrates that portions of the transceiver may be configured as a printed circuit board (PCB) module. The components of module <NUM> are mounted on (or coupled to) a system substrate <NUM>, which may be, for example, a multi-layer PCB or other type of substrate. More specifically, module <NUM> includes a plurality of ICs and devices coupled to the system substrate <NUM>, including a transmit amplifier module <NUM> (e.g., a module that embodies RF amplifier <NUM>, <FIG>), an RF switch and receive amplifier module <NUM> (e.g., a module that embodies RF switch <NUM> and the receive amplifier <NUM>, <FIG>), a circulator <NUM> (e.g., circulator <NUM>, <FIG>), and an RF switch controller IC <NUM> (e.g., an IC that embodies RF switch controller <NUM>, <FIG>). In addition, device <NUM> includes a transmit signal input connector <NUM> (e.g., corresponding to the input to amplifier <NUM>, <FIG>), a receive signal output connector <NUM> (e.g., corresponding to the output of amplifier <NUM>, <FIG>), and an antenna connector <NUM> (e.g., corresponding to an input to antenna <NUM>, <FIG>). The various ICs, devices, and connectors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are electrically connected together through a plurality of conductive traces on and within the system substrate <NUM>.

After incorporation of module <NUM> into a transceiver system (e.g., system <NUM>, <FIG>), and during operation of the transceiver system, power and ground reference voltages may be provided to device <NUM> through power and ground terminals (not numbered). RF switch controller IC <NUM> may receive transmit/receive mode control signals through a control signal terminal (not numbered). Based on the received mode control signals, the RF switch controller IC <NUM> provides switch control signals to control terminals (e.g., gates) of various transistors (e.g., transistors within branches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) of the RF switch (e.g., RF switch <NUM>, <FIG>) within the RF switch and receive amplifier module <NUM>. As will be described in more detail later, the switch control signals determine whether each of the various transistors is in a conducting or non-conducting state at any given time. More specifically, the switch control signals determine whether the RF switch within module <NUM> is in a transmit state or a receive state. When the RF switch is in the transmit state, the RF switch is configured to convey an RF signal from the circulator <NUM> to a ground reference terminal (e.g., node <NUM>, <FIG>). When the RF switch is in the receive state, the RF switch is configured to convey an RF signal from the circulator <NUM> to the receive amplifier (e.g., amplifier <NUM>, <FIG>) within module <NUM>.

Those of skill in the art would understand, based on the description herein, that although the transceiver <NUM> of <FIG> is shown in <FIG> to be implemented as a surface-mount device (i.e., QFN device <NUM>, <FIG>), transceiver <NUM> alternatively could be implemented as a PCB-based module (e.g., similar to PCB-based module <NUM>, <FIG>). Similarly, those of skill in the art would understand, based on the description herein, that although the transceiver <NUM> of <FIG> is shown in <FIG> to be implemented as a PCB-based module (i.e., module <NUM>, <FIG>), transceiver <NUM> alternatively could be implemented as a surface-mount device (e.g., similar to QFN device <NUM>, <FIG>). Transceivers <NUM>, <NUM> could be implemented and/or packaged in other forms, as well.

Details regarding embodiments of an RF switch (e.g., RF switch <NUM>, <NUM>, <FIG>) will now be discussed. In particular, <FIG> is a simplified circuit diagram of an RF switch <NUM>, in accordance with an embodiment. RF switch <NUM> may provide the functionality of RF switch <NUM> (<FIG>) and/or RF switch <NUM> (<FIG>). RF switch <NUM> includes a plurality of input/output (I/O) ports, including a first port <NUM> (e.g., port <NUM>, <NUM>, <FIG>), a second port <NUM> (e.g., port <NUM>, <NUM>, <FIG>), a third port <NUM> (e.g., port <NUM>, <NUM>, <FIG>), and voltage reference ports <NUM>, <NUM>, in an embodiment.

Further, RF switch <NUM> includes a plurality of "branches" <NUM>, <NUM>, <NUM>, <NUM> electrically coupled between the various ports <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. As used herein, a switch "branch" includes the switching circuitry connected between any two ports of an RF switch. Accordingly, RF switch <NUM> is shown to include four branches, where a first branch <NUM> ("TX series branch") includes switch circuitry between ports <NUM> and <NUM>, a second branch <NUM> ("TX shunt branch") includes switch circuitry between ports <NUM> and <NUM>, a third branch <NUM> ("RX series branch") includes switch circuitry between ports <NUM> and <NUM>, and a fourth branch <NUM> ("RX shunt branch") includes switch circuitry between ports <NUM> and <NUM>.

According to the illustrated embodiment, each branch <NUM>, <NUM>, <NUM>, <NUM> includes a "switch" <NUM>, <NUM>, <NUM>, <NUM>. As used herein, the term "switch", as it applies to each of elements <NUM>, <NUM>, <NUM>, <NUM>, may mean a single active switching device (e.g., a single FET) or a plurality of active switching devices (e.g., multiple FETs) that are coupled in series between two ports of an RF switch, thus comprising a "stack" of FET switches, or a "FET stack," as will be defined later.

If RF switch <NUM> were implemented in the transceiver <NUM> of <FIG>, for example, port <NUM> may correspond to port <NUM>, and thus may be coupled to transmitter <NUM>. Port <NUM> may correspond to port <NUM>, and thus may be coupled to receiver <NUM>. Port <NUM> may correspond to port <NUM>, and thus may be coupled to antenna <NUM>. Finally, ports <NUM>, <NUM> may be coupled to ground reference nodes. In an alternate embodiment, if RF switch <NUM> were implemented in the transceiver of <FIG>, port <NUM> may correspond to port <NUM>, and thus may be coupled to receiver <NUM>, and port <NUM> may correspond to port <NUM>, and thus may be coupled to transmitter <NUM>.

Conversely, if RF switch <NUM> were implemented in the transceiver <NUM> of <FIG>, for example, port <NUM> may correspond to port <NUM>, and thus may be coupled to the receiver port <NUM> of circulator <NUM>. Port <NUM> may correspond to port <NUM>, and thus may be coupled to receiver <NUM>. Port <NUM> may correspond to port <NUM>, and thus may be coupled to ground reference node <NUM> through resistor <NUM>. Finally, ports <NUM>, <NUM> also may be coupled to ground reference nodes. In an alternate embodiment, if RF switch <NUM> were implemented in the transceiver of <FIG>, port <NUM> may correspond to port <NUM>, and thus may be coupled to receiver port <NUM> of circulator <NUM>, and port <NUM> may correspond to port <NUM>, and thus may be coupled to ground reference node <NUM> through resistor <NUM>.

During operation of RF switch <NUM>, the state of the RF switch <NUM> is controlled (e.g., by RF switch controller <NUM>, <NUM>, <FIG>) based on whether the system (e.g., transceiver <NUM>, <NUM>, <FIG>) is in a transmit mode or a receive mode (e.g., during a transmit time interval or a receive time interval, respectively, of a wireless communication session). More specifically, when the system is in a transmit mode (as shown in <FIG>), the state of the RF switch <NUM> is controlled to establish a low-impedance connection between port <NUM> and port <NUM>, and to establish a high-impedance between port <NUM> and port <NUM>. Further, in the transmit mode, the state of the RF switch <NUM> is controlled to establish a low-impedance connection between port <NUM> and port <NUM>, and to establish a high-impedance between port <NUM> and port <NUM>. In other words, in the transmit mode, switches <NUM> and <NUM> are closed, and switches <NUM> and <NUM> are open.

Conversely, when the system is in a receive mode, the state of the RF switch <NUM> is controlled to establish a low-impedance connection between port <NUM> and port <NUM>, and to establish a high-impedance between port <NUM> and port <NUM>. Further, in the receive mode, the state of the RF switch <NUM> is controlled to establish a low-impedance connection between port <NUM> and port <NUM>, and to establish a high-impedance between port <NUM> and port <NUM>. In other words, in the receive mode, switches <NUM> and <NUM> are closed, and switches <NUM> and <NUM> are open.

According to an embodiment, each switch <NUM>, <NUM>, <NUM>, <NUM> is implemented as a "stack" of series-coupled FETs that is electrically coupled between two ports. For example, <FIG> is a simplified circuit diagram of a stack <NUM> of FETs that may be used in one or more branches (e.g., one or more of branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>) of an RF switch (e.g., switch <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <FIG>), in accordance with an example embodiment.

As used herein, the terms "stack" and "FET stack" refer to multiple FETs that are coupled in series with each other (or "series-coupled") between two ports of an RF switch. Each stack may be considered to be a "switch" or a "variably-conductive path", in that the conductivity of a signal through the stack (or more specifically through the series of channels of the FETs in the stack) can be controlled or varied (i.e., increased or decreased) based on control signals provided at the stack control terminals (e.g. terminals <NUM>, <NUM>, <FIG>, <FIG>). In other words, a stack (or switch or variably-conductive path) can be placed in a low-impedance state (e.g., closed, "on state" or "on-state") or a high-impedance state (e.g., open, "off state" or "off-state") based on control signals provided at the stack control terminal. Further, the terms "coupled in series" and "series-coupled," in reference to the electrical coupling between multiple FETs in a stack, means that the current-conducting terminals (e.g., source/drain terminals) of the multiple FETs are connected together to provide a continuous electrically conductive channel/path between a first port (e.g., port <NUM>, <NUM>, <FIG>, <FIG>) and a second port (e.g., port <NUM>, <NUM>, <FIG>, <FIG>) when the multiple FETs are in a conducting state (e.g., "on" or "closed").

<FIG> is a simplified circuit diagram of a stack <NUM> of FETs <NUM>-<NUM> that may be used in one or more branches of an RF switch (e.g., one or more of branches <NUM>, <NUM>, <NUM>, <NUM> of switch <NUM>, <FIG>), in accordance with an example embodiment. According to the embodiment illustrated in <FIG>, stack <NUM> includes a plurality of series-coupled FETs <NUM>, <NUM>, <NUM>, <NUM>, <NUM> that are electrically coupled between port <NUM> and port <NUM>. As best depicted in the enlarged view of FET <NUM> to the left of stack <NUM>, each FET <NUM>-<NUM> includes a gate terminal <NUM> (or "control terminal"), a source terminal <NUM>, and a drain terminal <NUM>. According to some embodiments, each FET <NUM>-<NUM> also may include a body bias terminal <NUM>, which enables a DC bias voltage to be provided to the FET body. The electrical conductivity of a variable-conductivity channel between the source and drain terminals of any given FET is controlled by control signals provided to the FET's gate terminal (e.g., terminal <NUM>). Some (and possibly all) of the above-discussed FETs may be "single-gate FETs", although some or all of the FETs may be "multiple-gate FETs", as well. Essentially, a single-gate FET is a monolithic transistor device that includes a variable-conductivity channel between drain and source terminals, along with only one gate positioned over the channel. Conversely, a multiple-gate FET is a monolithic transistor device that includes a variable-conductivity channel between drain and source terminals, along with multiple gates positioned over the channel. Electrical signals provided to the multiple gates control the conductivity of the channel during operation of the FET. In some applications, utilization of multiple gates may enable better electrical control over the channel, when compared with single-gate FETs. This, in turn, may enable more effective suppression of off-state leakage current, and/or enhanced current in the on state (i.e., drive current).

As used herein, a "current-conducting node" is a conductive node of stack <NUM> that is directly coupled to a source and/or drain terminal of one or more of the FETs <NUM>-<NUM> of the stack <NUM>. In the series-coupled sequence of FETs corresponding to stack <NUM>, the source terminal <NUM> of FET <NUM> may be coupled through current-conducting node <NUM> to port <NUM>, the drain terminal <NUM> of FET <NUM> may be coupled through current-conducting node <NUM> to the source terminal of FET <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> to the source terminal of FET <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> to the source terminal of FET <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> (and through zero or more additional FETs, not illustrated) to the source terminal of FET <NUM>, and the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> to port <NUM>.

The stack <NUM> of <FIG> is depicted to include five series-coupled FETs <NUM>-<NUM>. However, as indicated by the ellipses between FETs <NUM> and <NUM>, a stack may include more than five FETs. A stack also may include fewer than five FETs. Further, although the description herein refers to series-coupled arrangements in which a first FET has a source terminal connected to a port, and has a drain terminal connected to a source terminal of a second FET, the source and drain terminal connections could be reversed, in other embodiments (e.g., a series-coupled arrangement may have a first FET with a drain terminal connected to a port, and a source terminal connected to a drain terminal of a second FET). More generally, each of the source and drain terminals of a FET may be referred to as a "current-conducting terminal," and that term could be used interchangeably for either a source terminal or a drain terminal.

According to an embodiment, during operation, the control signals provided to the series-coupled FETs in stack <NUM> are synchronous, in that they simultaneously cause all of the FETs in the stack <NUM> either to be substantially conducting (e.g., "on" or "closed") or substantially non-conducting (e.g., "off' or "open"). To accomplish simultaneous control of all FETs in each stack <NUM>, the gate terminals of the FETs in each stack may be electrically coupled to a single control node. For example, in <FIG>, the gate terminals of FETs <NUM>-<NUM> are electrically coupled to stack control terminal <NUM>.

In addition to the FETs <NUM>-<NUM>, stack <NUM> may include a DC bias distribution network of high-value (e.g., multiple kiloohm) resistors (e.g., including resistor <NUM>), in an embodiment, where each resistor is coupled between the source and drain terminals of a FET <NUM>-<NUM> (e.g., resistor <NUM> has a first terminal coupled to the source terminal of FET <NUM>, and a second terminal coupled to the drain terminal of FET <NUM>). The DC bias distribution network essentially ensures that the DC bias voltage provided to the drains/sources of each FET <NUM>-<NUM> in the stack is the same.

Stack <NUM> also may include an RF blocking network of high-value (e.g., multiple kiloohm) resistors (e.g., resistor <NUM>) coupled between the gate terminals of the FETs <NUM>-<NUM> and the stack control terminal <NUM>, in an embodiment. The RF blocking network presents a high impedance to RF signal energy to ensure that the RF signal energy conveyed through a branch does not leak to the control/driver circuitry (e.g., to controller <NUM>, <NUM>, <FIG>).

Further still, stack <NUM> also may include body bias circuitry coupled between the body node of each FET, if included, and the body bias terminal (e.g., body bias terminal <NUM>, <FIG>). The body bias circuitry also may include an RF blocking network of high-value (e.g., multiple kiloohm) resistors (e.g., resistor <NUM>) coupled between the body nodes of the FETs and a body bias terminal <NUM> for the stack <NUM>, in an embodiment. Again, the RF blocking network presents a high impedance to RF signal energy to ensure that the RF signal energy conveyed through a branch does not leak to the body bias circuitry.

As indicated previously, a system that includes stack <NUM> may include a switch controller (e.g., switch controller <NUM>, <NUM>, <FIG>) with a driver that is coupled to the stack control terminal <NUM>. To cause the entire stack <NUM> to become substantially conductive between the ports to which the stack is connected (e.g., to turn the stack "on" or to "close" the switch), the driver provides a control signal (or "drive signal") to the stack control terminal <NUM>. That control signal causes all of the FETs <NUM>-<NUM> within the stack <NUM> simultaneously to become substantially conducting, thus causing stack <NUM> to become substantially conductive between ports <NUM> and <NUM>. In other words, the FETs <NUM>-<NUM> and stack <NUM> are in the "on state". As shown in box <NUM> to the right of stack <NUM>, in the "on state", each FET <NUM>-<NUM> may be simply modeled as a resistor <NUM> with a first terminal corresponding to the drain terminal <NUM>, and a second terminal corresponding to the source terminal <NUM>. Alternatively, the driver may provide a control signal to stack control terminal <NUM>, which simultaneously causes all of FETs <NUM>-<NUM> to become substantially non-conducting, thus causing stack <NUM> to become substantially non-conductive between ports <NUM> and <NUM>. In other words, the FETs <NUM>-<NUM> and stack <NUM> are in the "off state". As shown in box <NUM> to the right of stack <NUM>, in the "off state", each FET <NUM>-<NUM> may be simply modeled as a capacitor <NUM> ("Cds") with a first terminal corresponding to the drain terminal <NUM>, and a second terminal corresponding to the source terminal <NUM>, along with a first additional shunt capacitance <NUM> ("Csub1") between the source terminal and a ground reference, and a second additional shunt capacitance <NUM> ("Csub2") between the drain terminal and the ground reference. Csub1 <NUM> and Csub2 <NUM> represent the parasitic capacitance from the transistor body to the semiconductor substrate on which the FET is formed.

In the off state, the parasitic capacitances modeled by Csub1 <NUM> and Csub2 <NUM> each may facilitate an undesirable leakage current between the FET and the substrate, which ultimately results in RF signal loss. Further, these leakage currents may create an unequal or non-uniform RF voltage division across the stack <NUM>. This non-uniform voltage distribution across the stack <NUM> may lead to a lower power handling capability for the stack <NUM>, because in the off state, the first and/or first few FETs in the stack may experience the stack breakdown voltage before the rest of the FETs in the off-state branch.

To balance the voltage distribution across the stack <NUM>, and thus to increase the RF voltage handling capability of the stack <NUM>, stack <NUM> also includes a network <NUM> of "balancing" capacitors <NUM>-<NUM>, in an embodiment. The balancing capacitors <NUM>-<NUM> are coupled between some (but not all) of the current-conducting nodes <NUM>-<NUM> of the stack <NUM>, in an embodiment, meaning that each balancing capacitor is connected across a different group of multiple FETs <NUM>-<NUM> in the stack <NUM>. In the embodiment of <FIG>, for example, each balancing capacitor <NUM>-<NUM> is connected across a different group of two adjacent FETs in the series-coupled arrangement of FETs <NUM>-<NUM> in stack <NUM>, where "two adjacent FETs" means two FETs that are directly connected together through an intermediate current-conducting node (e.g., FETs <NUM> and <NUM> are "adjacent" because the drain of FET <NUM> is directly connected to the source of FET <NUM> through intermediate current-conducting node <NUM>). More specifically, a first balancing capacitor <NUM> is coupled across a first group of two FETs <NUM> and <NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>). Node <NUM> may be considered to be an "input" of the first group of FETs <NUM>, <NUM>, and node <NUM> may be considered to be an "output" of the first group of FETs <NUM>, <NUM>. A second balancing capacitor <NUM> is coupled across a second group of two FETs <NUM> and <NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>). Node <NUM> may be considered to be an "input" of the second group of FETs <NUM>, <NUM>, and node <NUM> may be considered to be an "output" of the second group of FETs <NUM>, <NUM>. Finally, a third balancing capacitor <NUM> is coupled across a third group of two FETs (including a non-illustrated FET and FET <NUM>). As indicated by the ellipses in <FIG>, additional groups of FETs and associated balancing capacitors may be coupled between FETs <NUM> and <NUM>. It should be noted that current-conducting nodes that are in-between the FETs in any given group (e.g., current-conducting nodes <NUM> and <NUM>) are not directly connected to the network <NUM> of balancing capacitors <NUM>-<NUM>. According to an embodiment, each of the balancing capacitors <NUM>-<NUM> has a capacitance value in a range of about <NUM> femtofarads (fF) to about <NUM> fF, although the capacitance values may be lower or higher, as well.

In some embodiments, balancing capacitors <NUM>-<NUM> are connected across all of the groups of FETs <NUM>-<NUM> in the stack <NUM>. In other embodiments, balancing capacitors may be connected across some, but not all, FETs in the stack <NUM>. For example, as indicated with the dashed-line connections between balancing capacitor <NUM> and nodes <NUM>, <NUM>, balancing capacitor <NUM> may be omitted. In other embodiments, one or more other or additional balancing capacitors may be omitted (e.g., balancing capacitor <NUM> and/or <NUM> also or alternatively may be omitted).

By utilizing balancing capacitors <NUM>-<NUM> connected as shown in <FIG>, AC voltage swings may be substantially equalized across all FETs in an off-state FET branch of an RF switch, thereby potentially preventing the first and/or first few FETs from experiencing the stack breakdown voltage before the rest of the FETs in the off-state branch. This may significantly improve the power handling capability of the switch branch.

In the stack <NUM> of <FIG>, each of the balancing capacitors <NUM>-<NUM> is connected across a different group of two adjacent, series-coupled FETs in the stack <NUM>. In alternate embodiments, the balancing capacitors may be connected across groups of more than two series-coupled FETs, and/or the balancing capacitors may be connected across groups of FETs that include different numbers of series-coupled FETs. To illustrate this concept in a more generic way, reference is made to <FIG>, which is a simplified circuit diagram of a stack <NUM> of FETs <NUM>-<NUM> that may be used in one or more branches of an RF switch (e.g., one or more of branches <NUM>, <NUM>, <NUM>, <NUM> of switch <NUM>, <FIG>), in accordance with another embodiment. Each FET <NUM>-<NUM> includes gate, source, drain, and (optionally) body bias terminals (e.g., terminals <NUM>-<NUM>, <FIG>), and the on and off states of the FETs <NUM>-<NUM> may be modeled as depicted in boxes <NUM>, <NUM> (<FIG>), respectively. Further, each FET <NUM>-<NUM> may be a single-gate FET or a multiple-gate FET.

The FETs <NUM>-<NUM> of stack <NUM> are divided into groups <NUM>, <NUM>, <NUM> of FETs, where each group <NUM>-<NUM> includes three or more (as indicated by the ellipses) adjacent, series-coupled FETs. In various embodiments, each group <NUM>-<NUM> may include from three to <NUM> FETs, for example, and the number of FETs in each group <NUM>-<NUM> may be the same or different. Although stack <NUM> is shown to include three groups <NUM>-<NUM> of FETs, stack <NUM> may include as few as two groups, or more than three groups, in other embodiments.

In the series-coupled sequence of FETs corresponding to stack <NUM>, the source terminal of FET <NUM> may be coupled through current-conducting node <NUM> to port <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> to the source terminal of FET <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> (and through zero or more additional FETs, not illustrated) to the source terminal of FET <NUM>, the drain terminal of FET <NUM> may be coupled through current-conducting node <NUM> (and through zero or more additional FETs, not illustrated) to the source terminal of FET <NUM>, and so on, with the drain terminal of FET <NUM> being coupled through current-conducting node <NUM> to port <NUM>.

As with the stack <NUM> depicted in <FIG>, simultaneous control of all FETs <NUM>-<NUM> in the stack <NUM> is accomplished by electrically coupling the gate terminals of the FETs <NUM>-<NUM> to a single stack control terminal <NUM>. To cause the entire stack <NUM> to become substantially conductive between the ports to which the stack is connected (e.g., to turn the stack "on" or to "close" the switch), a driver (e.g., of switch controller <NUM>, <NUM>, <FIG>) provides a drive signal to the stack control terminal <NUM>. That control signal causes all of the FETs <NUM>-<NUM> within the stack <NUM> simultaneously to become substantially conducting, thus causing stack <NUM> to become substantially conductive between ports <NUM> and <NUM>.

In addition, stack <NUM> may include a DC bias distribution network of high-value (e.g., multiple kiloohm) resistors (e.g., including resistor <NUM>), in an embodiment, where each resistor is coupled between the source and drain terminals of a FET <NUM>-<NUM>. Further, stack <NUM> also may include an RF blocking network of high-value (e.g., multiple kiloohm) resistors (e.g., resistor <NUM>) coupled between the gate terminals of the FETs <NUM>-<NUM> and the stack control terminal <NUM>, in an embodiment. Further still, stack <NUM> also may include body bias circuitry coupled between the body node of each FET, if included, and the body bias terminal (e.g., body bias terminal <NUM>, <FIG>). The body bias circuitry also may include an RF blocking network of high-value (e.g., multiple kiloohm) resistors (e.g., resistor <NUM>) coupled between the body nodes of the FETs and a body bias terminal <NUM> for the stack <NUM>, in an embodiment.

To balance the voltage distribution across the stack <NUM>, and thus to increase the RF voltage handling capability of the stack <NUM>, stack <NUM> also includes a network <NUM> of balancing capacitors <NUM>-<NUM>, in an embodiment. Again, the balancing capacitors <NUM>-<NUM> are coupled between some (but not all) of the current-conducting nodes <NUM>-<NUM> of the stack <NUM>, in an embodiment, meaning that each balancing capacitor is connected across a different group of multiple FETs <NUM>-<NUM> in the stack <NUM>. In the embodiment of <FIG>, for example, each balancing capacitor <NUM>-<NUM> is connected across a different group of three or more adjacent FETs in the series-coupled arrangement of FETs <NUM>-<NUM> in stack <NUM>. More specifically, a first balancing capacitor <NUM> is coupled across a first group <NUM> of three or more FETs <NUM>-<NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>). Node <NUM> may be considered to be an "input" of the first group of FETs <NUM>-<NUM>, and node <NUM> may be considered to be an "output" of the first group of FETs <NUM>-<NUM>. A second balancing capacitor <NUM> is coupled across a second group <NUM> of three or more FETs <NUM>-<NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>). Node <NUM> may be considered to be an "input" of the second group of FETs <NUM>-<NUM>, and node <NUM> may be considered to be an "output" of the second group of FETs <NUM>-<NUM>. Finally, a third balancing capacitor <NUM> is coupled across a third group <NUM> of three or more FETs <NUM>-<NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and terminal <NUM>). Node <NUM> may be considered to be an "input" of the third group of FETs <NUM>-<NUM>, and node <NUM> may be considered to be an "output" of the third group of FETs <NUM>-<NUM>. It should be noted that current-conducting nodes that are in-between the FETs in any given group (e.g., current-conducting nodes <NUM> and <NUM>) are not directly connected to the network <NUM> of balancing capacitors <NUM>-<NUM>. In addition, although <FIG> depicts three groups <NUM>-<NUM> of FETs, stack <NUM> may have as few as two groups or more than three groups, in other embodiments. According to an embodiment, each of the balancing capacitors <NUM>-<NUM> has a capacitance value in a range of about <NUM> fF to about <NUM> fF, although the capacitance values may be lower or higher, as well.

An embodiment of an RF switch integrated circuit (IC) that embodies circuitry consistent with <FIG> will now be described. More particularly, <FIG> is a top view of a monolithic RF switch IC <NUM> that embodies the RF switch <NUM> of <FIG> with FET stacks (or branches), each of which includes a balancing capacitor network <NUM> (e.g., network <NUM>, <FIG>), in accordance with an example embodiment. RF switch IC <NUM> includes a plurality of branches <NUM>, <NUM>, <NUM>, <NUM> (e.g., branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>). Each branch includes a FET stack <NUM>, <NUM>, <NUM>, <NUM> (e.g., each similar to stack <NUM>, <FIG>), and each FET stack includes four, series-coupled FETs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>. According to an embodiment, the branches <NUM>, <NUM>, <NUM>, <NUM> may form portions of a single, monolithic semiconductor chip (i.e., a single semiconductor substrate). Alternatively, some or all of the branches <NUM>, <NUM>, <NUM>, <NUM> may be included within distinct semiconductor chips that are electrically connected together using wirebonds and/or other electrically conductive structures.

According to on embodiment, the RF switch IC <NUM> is "monolithic," in that the FETs <NUM>-<NUM> are formed in and on a single integrated circuit substrate <NUM>. For example, according to an embodiment, the RF switch IC <NUM> may be formed on a gallium arsenide (GaAs)-based substrate <NUM>, although those of skill in the art would understand, based on the description herein, that the circuitry of the RF switch may be formed on other types of substrates, as well, including silicon (Si)-based substrates (e.g., bulk Si CMOS, silicon-on insulator (SoI) CMOS, and so on) and gallium nitride (GaN)-based substrates (e.g., GaN on silicon, GaN on silicon carbide (SiC), and so on). Further, the FETs may include metal oxide semiconductor FETs (MOSFETs), high electron mobility transistors (HEMTs), metal-semiconductor field effect transistors (MESFETs), laterally diffused metal-oxide semiconductor (LDMOS) FETs, Enhancement-mode MOSFETs (EMOSFETs), and/or junction gate FETs (JFETs), to name a few.

In addition to branches <NUM>, <NUM>, <NUM>, <NUM>, RF switch IC <NUM> includes a plurality of I/O, control, and voltage reference nodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, each of which may provide for electrical connectivity with external circuitry (e.g., connectivity with antenna <NUM>, transmitter <NUM>, receiver <NUM>, <NUM>, circulator <NUM>, RF switch controller <NUM>, <NUM>, and so on) and/or electrical connectivity with one or more power sources and/or voltage references (e.g., power, ground and other voltage references). For example, some or all of the I/O, control, and voltage reference nodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be implemented as conductive pads that are exposed at a top surface of the RF switch IC <NUM>. Accordingly, the various nodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may serve as bond pads for wirebonds (e.g., wirebonds <NUM>, <FIG>), which provide for electrical connectivity to the above-mentioned external circuitry or to other circuitry. According to an embodiment, the various nodes include a first node <NUM> (e.g., node <NUM>, <NUM>, <NUM>, <FIG>, <FIG>), a second node <NUM> (e.g., node <NUM>, <NUM>, <NUM>, <FIG>, <FIG>), a third node <NUM> (e.g., node <NUM>, <NUM>, <NUM>, <FIG>, <FIG>), and voltage reference nodes <NUM>, <NUM> (e.g., reference nodes <NUM>, <NUM>, <FIG>).

For each FET <NUM>-<NUM>, the electrical conductivity of the FET channel between the source and drain terminals is controlled by control signals provided to each gate structure through a gate terminal (e.g., terminal <NUM>, <FIG>). To enable such channel conductivity control, RF switch IC <NUM> also includes a plurality of control nodes (not illustrated in <FIG>, but corresponding to control terminal <NUM>, <FIG>) that enable control signals to be provided by external circuitry to the gate terminals of the FETs <NUM>-<NUM>. According to an embodiment, the control signals provided to the FETs in any particular branch <NUM>, <NUM>, <NUM>, <NUM> are synchronous, in that they simultaneously cause all of the FETs in that branch either to be substantially conducting (e.g., "on" or "closed") or substantially non-conducting (e.g., "off' or "open").

A first branch <NUM>, consisting of a first stack <NUM> of series-coupled FETs <NUM>, <NUM>, <NUM>, <NUM> (e.g., FETs <NUM>-<NUM>, <FIG>), is electrically coupled between node <NUM> and node <NUM>. More specifically, a source terminal of FET <NUM> is electrically coupled to node <NUM>, a drain terminal of FET <NUM> is electrically coupled to a source terminal of FET <NUM>, a drain terminal of FET <NUM> is electrically coupled to a source terminal of FET <NUM>, a drain terminal of FET <NUM> is electrically coupled to a source terminal of FET <NUM>, and a drain terminal of FET <NUM> is electrically coupled to node <NUM>, in an embodiment.

In addition to the series-coupled FETs <NUM>-<NUM>, the first branch <NUM> also includes a network <NUM> of balancing capacitors <NUM>, <NUM> (e.g., similar to network <NUM>, <FIG>) coupled to stack <NUM>. In the embodiment of <FIG>, a first balancing capacitor <NUM> is coupled across a first group of two FETs <NUM> and <NUM>, where a first terminal of capacitor <NUM> is coupled to node <NUM> (and thus to the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to intermediate current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>). A second balancing capacitor <NUM> is coupled across a second group of two FETs <NUM> and <NUM>, where a first terminal of capacitor <NUM> is coupled to current-conducting node <NUM> (and thus to the drain of FET <NUM> and the source of FET <NUM>), and a second terminal of capacitor <NUM> is coupled to node <NUM> (and thus to the drain of FET <NUM>). It should be noted that current-conducting nodes that are in-between the FETs in any given group (e.g., current-conducting nodes <NUM> and <NUM>) are not directly connected to the network <NUM> of balancing capacitors <NUM>, <NUM>.

According to an embodiment, each of the capacitors <NUM>, <NUM> in the balancing capacitor network <NUM> may be a metal-insulator-metal (MIM) capacitor that is integrally formed with the substrate (e.g., a first electrode formed from a portion of a first metal layer, a second electrode formed from a portion of a second metal layer, and an insulating layer (e.g., silicon nitride or other suitable insulating materials) sandwiched between the first and second electrodes). In other embodiments, capacitors <NUM>, <NUM> may be discrete capacitors that are electrically coupled to the top surface of the semiconductor substrate.

A second branch <NUM>, consisting of a second stack <NUM> of series-coupled FETs <NUM>, <NUM>, <NUM>, <NUM>, is electrically coupled between node <NUM> and voltage reference node <NUM>. More specifically, in stack <NUM>, a drain terminal of FET <NUM> is electrically coupled to node <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, and a source terminal of FET <NUM> is electrically coupled to voltage reference node <NUM>. Similar to branch <NUM>, the second branch <NUM> also includes a network <NUM> of balancing capacitors, which are electrically coupled to FETs <NUM>-<NUM> in a manner similar to the connection of network <NUM> to stack <NUM>.

A third branch <NUM>, consisting of a third stack <NUM> of series-coupled FETs <NUM>, <NUM>, <NUM>, <NUM>, is electrically coupled between node <NUM> and node <NUM>. More specifically, in stack <NUM>, a drain terminal of FET <NUM> is electrically coupled to node <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, and a source terminal of FET <NUM> is electrically coupled to node <NUM>. Also similar to branch <NUM>, the third branch <NUM> also includes a network <NUM> of balancing capacitors, which are electrically coupled to FETs <NUM>-<NUM> in a manner similar to the connection of network <NUM> to stack <NUM>.

Finally, a fourth branch <NUM>, consisting of a fourth stack <NUM> of series-coupled FETs <NUM>, <NUM>, <NUM>, <NUM>, is electrically coupled between node <NUM> and voltage reference node <NUM>. More specifically, a drain terminal of FET <NUM> is electrically coupled to node <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, and a source terminal of FET <NUM> is electrically coupled to a drain terminal of FET <NUM>, and a source terminal of FET <NUM> is electrically coupled to voltage reference node <NUM>, in an embodiment. Also similar to branch <NUM>, the fourth branch <NUM> also includes a network <NUM> of balancing capacitors, which are electrically coupled to FETs <NUM>-<NUM> in a manner similar to the connection of network <NUM> to stack <NUM>. When incorporated into a larger electrical system (e.g., transceiver <NUM>, <NUM>, <FIG>), voltage reference nodes <NUM>, <NUM> typically would be coupled to a ground reference (e.g., zero volts), although nodes <NUM>, <NUM> alternatively could be coupled to a positive or negative DC voltage reference, as well.

<FIG> is a flowchart of a method of operating an RF switch (e.g., RF switch <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) in an RF transceiver (e.g., transceiver <NUM>, <NUM>, <FIG>), in accordance with an embodiment. The method may begin, in block <NUM>, when a determination is made (e.g., by RF switch controller <NUM>, <NUM>, <FIG>) whether the RF transceiver should be configured in a transmit (TX) mode or a receive (RX) mode. For example, this determination may be made based on a TX/RX control signal from a higher-level communication controller.

When the transceiver is to be configured in a transmit mode configuration, then in block <NUM>, the FET stacks in the TX series and RX shunt branches (e.g., branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) simultaneously are turned on, while the FET stacks in the RX series and the TX shunt branches (e.g., branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) simultaneously are turned off. To achieve this, the drivers of the RF switch controller provide control signals to the control nodes (e.g., terminals <NUM>, <NUM>, <FIG>, <FIG>) of the various FET stacks of the RF switch to configure the RF switch in the transmit mode configuration. For example, to configure the RF switch <NUM> of <FIG> into the transmit mode configuration, one or more drivers of the RF switch controller may send first control signals to stack control terminals of branches <NUM> and <NUM> to simultaneously turn on branches <NUM> and <NUM> (i.e., to close switches <NUM>, <NUM> to establish low-impedance paths between nodes <NUM> and <NUM>, and between nodes <NUM> and <NUM>). At the same time, one or more drivers of the RF switch controller may send second control signals to stack control terminals of branches <NUM> and <NUM> to simultaneously turn off branches <NUM> and <NUM> (i.e., to open switches <NUM>, <NUM> to establish high-impedance conditions between nodes <NUM> and <NUM> and between nodes <NUM> and <NUM>). The RF switch controller continues to send these control signals to the various control nodes until a determination is made (in block <NUM>) that the transceiver is to be configured in a receive mode.

When the transceiver is to be configured in a receive mode configuration, then in block <NUM>, the FET stacks in the RX series and TX shunt branches (e.g., branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) simultaneously are turned on, while the FET stacks in the TX series and the RX shunt branches (e.g., branches <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) simultaneously are turned off. To achieve this, the drivers of the RF switch controller provide control signals to the control nodes (e.g., terminals <NUM>, <NUM>, <FIG>, <FIG>) of the various FET stacks of the RF switch to configure the RF switch in the receive mode configuration. For example, to configure the RF switch <NUM> of <FIG> into the receive mode configuration, one or more drivers of the RF switch controller may simultaneously send third control signals to stack control terminals of branches <NUM> and <NUM> to simultaneously turn on branches <NUM> and <NUM> (i.e., to close switches <NUM>, <NUM> to establish low-impedance paths between nodes <NUM> and <NUM>, and between nodes <NUM> and <NUM>). At the same time, one or more drivers of the RF switch controller may send fourth control signals to stack control terminals of branches <NUM> and <NUM> to simultaneously turn off branches <NUM> and <NUM> (i.e., to open switches <NUM>, <NUM> to establish high-impedance conditions between nodes <NUM> and <NUM> and between nodes <NUM> and <NUM>). The RF switch controller continues to send these control signals to the various control nodes until a determination again is made (in block <NUM>) that the transceiver is to be configured in a transmit mode.

A switch circuit includes a transistor stack coupled between first and second ports. The transistor stack includes a group of multiple, adjacent, series-coupled transistors, and at least one additional transistor coupled in series with the group between the first and second ports to provide a first variably-conductive path between the first and second ports. The switch circuit also includes a balancing capacitor with a first terminal coupled to an input of the group of multiple, adjacent, series-coupled transistors, and a second terminal coupled to an output of the group of multiple, adjacent, series-coupled transistors.

The foregoing detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration. " Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the foregoing technical field, background, or detailed description.

For the sake of brevity, conventional semiconductor fabrication techniques may not be described in detail herein. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

The foregoing description refers to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.

Claim 1:
A switch circuit (<NUM>) comprising:
a first port (<NUM>, <NUM>);
a second port (<NUM>, <NUM>);
a first transistor stack (<NUM>, <NUM>) coupled between the first and second ports (<NUM>; <NUM>), wherein the first transistor stack (<NUM>) comprises a first group (<NUM>) of multiple, adjacent, series-coupled transistors, and a second group (<NUM>) of multiple, adjacent, series-coupled transistors coupled in series with the first group between the first and second ports to provide a first variably-conductive path between the first and second ports;
a first balancing capacitor (<NUM>) with a first terminal coupled to an input of the first group (<NUM>) of multiple, adjacent, series-coupled transistors, and a second terminal coupled to an output of the first group of multiple, adjacent, series-coupled transistors; and
a second balancing capacitor (<NUM>) with a first terminal coupled to an input of the second group (<NUM>) of multiple, adjacent, series-coupled transistors, and a second terminal coupled to an output of the second group of multiple, adjacent, series-coupled transistors.