Patent Description:
In conventional computing architecture, some multipliers are typically designed to handle a large number of calculations that need to be handled by an application, which may cause large delays for complex multiplier processing when handling large numbers in cross pattern calculations, such as matrices. These complex multiplier calculations are used in machine learning applications, and some types of conventional multiplier designs typically implement multi-bit logic that is built to handle large numbers. Also, some other multiplier designs may use various other multi-bit signed logic that is built to handle large numbers. However, these types of complex multipliers typically exhibit glitching and delay problems due to complicated and inefficient memory designs. Thus, there exists a need to improve physical design implementation of some multiplier circuitry so as to provide for more efficient binary multiplication operations.

<CIT> discloses a mechanism to store a matrix of numbers in a storage entity which may reside in a processing unit.

<CIT> discloses a multi-port memory array associated with wordlines and bit-lines to perform read/write operations.

<CIT> discloses a transpose accessing memory device with row and column access modes.

<CIT> discloses a semiconductor storage device for suppressing an increase in circuit size.

According to a first aspect of the present invention, there is provided a device according to independent claim <NUM>.

According to a second aspect of the present invention, there is provided a method according to independent claim <NUM> Preferred aspects are defined in dependent claims <NUM>-<NUM> and <NUM>-<NUM>.

Only embodiments or implementations comprising all the features of independent claim <NUM> or of independent claim <NUM> fall under the scope of protection of the present invention.

Implementations of various techniques are described herein with reference to the accompanying drawings. It should be understood, however, that the accompanying drawings illustrate only various implementations described herein and are not meant to limit embodiments of various techniques described herein.

The scope of protection of the present invention is defined by appended claims <NUM>-<NUM>.

Various implementations described herein refer to memory architecture having bitcell circuitry with multiple read bitlines. For instance, various schemes and techniques described herein may provide for ultra-fast high-density memory architecture that may be used as custom memory for an in-core matrix accelerator. Some aspects of the various schemes and techniques described herein provide for sixteen (<NUM>) entries with <NUM> bytes per entry and with one (<NUM>) read or one (<NUM>) write per cycle. Also, the various schemes and techniques described herein may provide for write operations that may be configured to update all <NUM> bytes of an entry in a single cycle. Also, the various schemes and techniques described herein may also provide multiple modes for read operations, such as, e.g., a single entry read and a block read. For instance, the single entry read may refer to reading all <NUM> bytes (i.e., read <NUM> bits) of an entry in a single cycle, and the block read may refer to reading the same <NUM> bytes for all <NUM> entries (i.e., read <NUM> bits) in a single cycle.

In some implementations, various schemes and techniques described herein may provide for a write operation that updates all <NUM> bytes of an entry in a single cycle, e.g., by writing data to four (<NUM>) banks of 128x16 bitcells via activation of a single write wordline (WWL), wherein this technique is used to write <NUM> bits in a single cycle. Also, in some implementations, various schemes and techniques described herein may provide for an entry read operation that reads all <NUM> bytes of an entry in a single cycle, e.g., by reading data from four (<NUM>) banks of 128x16 bitcells via activation of a single read wordline (RWL), wherein this technique is used to read <NUM> bits in a single cycle. Further, in some implementations, the various schemes and techniques described herein may provide for a block read operation that block reads a 32x16 bitcell array in a single cycle, e.g., by block reading data from <NUM> bits in a single cycle.

Various implementations of high-density memory architecture will be described in greater detail herein with reference to <FIG> and <FIG>.

<FIG> illustrates a diagram <NUM> of memory circuitry <NUM> associated with a bitcell in accordance with various implementations described herein.

In various implementations, the memory circuitry <NUM> may be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for a physical circuit design and related structures. In some instances, a method of designing, providing and building the memory circuitry <NUM> as an integrated system or device may involve use of various IC circuit components described herein so as to implement the various memory array architecture associated therewith. The memory circuitry <NUM> may be integrated with computing circuitry and related components on a single chip, and the memory circuitry <NUM> may be implemented in embedded systems for electronic, mobile and Internet-of-things (IoT) applications, including sensor nodes.

As shown in <FIG>, the memory circuitry <NUM> may be associated with memory architecture that is implemented as a bitcell or memory cell. In some instances, the bitcell <NUM> may refer to a device or structure having a single bitcell that is configured to store a data bit that is accessible via multiple wordlines and multiple bitlines. The bitcell <NUM> may utilize multiple wordlines including a write wordline (WWL), a read wordline (RWL), and a global read wordline (GRWL) coupled to the bitcell. The bitcell <NUM> may utilize multiple horizontal bitlines (WBL, NWBL, RBL_H0, RBL_H1, RBL_H2, RBL_H3) coupled to the bitcell. The bitcell <NUM> may utilize multiple vertical bitlines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7) coupled to the bitcell. Various aspects and structural features associated with various layout designs of memory array architecture of the memory circuitry <NUM> associated with the bitcell <NUM> along with various schemes and techniques related thereto is described in greater detail herein.

<FIG> illustrates a diagram <NUM> of a bitcell structure <NUM> in accordance with various implementations described herein. In some implementations, the bitcell structure <NUM> of <FIG> is associated with the bitcell <NUM> of <FIG>.

In various implementations, the bitcell structure <NUM> may be implemented as a memory device having various IC components that are arranged and coupled together as an assemblage or combination of parts that allow for a physical layout design and related structures. In some instances, a method of designing, providing and fabricating the bitcell structure <NUM> as an integrated device may involve use of various IC circuit components described herein so as to implement the various memory array architecture associated therewith. The bitcell structure <NUM> may be integrated with computing circuitry and related components on a single chip, and also, the bitcell structure <NUM> may be used in embedded systems for electronic, mobile and Internet-of-things (IoT) applications.

As shown in <FIG>, the bitcell structure <NUM> may refer to a device having a single bitcell with multiple transistors that are arranged and configured to store a data bit that is accessible via multiple wordlines and multiple bitlines. In some implementations, the bitcell structure <NUM> may include eight transistors that are arranged and configured to provide a single <NUM>-transistor (8T) bitcell. For instance, the bitcell structure <NUM> may include transistors (T1, T2) arranged as a first inverter, transistors (T3, T4) arranged as a second inverter, write access transistors (T5, T6), and read transistors (T7, T8). Also, the bitcell structure <NUM> may include multiple wordlines including a write wordline (WWL), a read wordline (RWL), and a global read wordline (GRWL). The write wordline (WWL) may be coupled to gates of transistors (T5, T6), and the read wordline (RWL) may be coupled to a gate of transistor (T7). Also, a first write bitline (WBL) may be coupled to transistor (T6), and a second write bitline (NWBL) may be coupled to transistor (T5).

In some implementations, the bitcell structure <NUM> may have multiple horizontal bitlines (WBL, NWBL, RBL_H0, RBL_H1, RBL_H2, RBL_H3) coupled to the bitcell. The multiple horizontal bitlines may include first read bitlines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) disposed in a horizontal direction with respect to the bitcell, and the multiple horizontal bitlines may also include the first write bitline (WBL) and the second write bitline (NWBL) that is a complement to the first write bitline (WBL). Therefore, the horizontal bitlines may include six horizontal bitlines that include the four (<NUM>) horizontal read bitlines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) along with the two horizontal write bitlines (WBL, NWBL) that are disposed in the horizontal direction with respect to the bitcell.

In some implementations, the bitcell structure <NUM> may have multiple vertical bitlines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7) coupled to the bitcell. The multiple vertical bitlines may refer to multiple second read bitlines (RBL) disposed in a vertical direction with respect to the bitcell, and also, the second read bitlines may include eight (<NUM>) vertical read bitlines that are disposed in the vertical direction with respect to the bitcell.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells <NUM> arranged in a 1x8 array in accordance with implementations described herein.

As shown in <FIG>, the memory array circuitry <NUM> may include the 1x8 array of bitcells <NUM> that are arranged in a single row of <NUM> bitcells <NUM>. The 1x8 array of bitcells <NUM> may be arranged in the single row of bitcells <NUM> and may include a first bitcell BC[<NUM>], a second bitcell BC[<NUM>], a third bitcell BC[<NUM>], a fourth bitcell BC[<NUM>], a fifth bitcell BC[<NUM>], a sixth bitcell BC[<NUM>], a seventh bitcell BC[<NUM>], and an eighth bitcell BC[<NUM>] that are coupled to corresponding write wordlines (WWL) and read wordlines (RWL). In some instances, a first write wordline WWL[<NUM>] and a first read wordline RWL[<NUM>] may be coupled to the first bitcell BC[<NUM>], a second write wordline WWL[<NUM>] and a second read wordline RWL[<NUM>] may be coupled to the second bitcell BC[<NUM>], and so on to an eight write wordline WWL[<NUM>] and an eighth read wordline RWL[<NUM>] that is coupled to the eighth bitcell BC[<NUM>]. Also, in some instances, each bitcell <NUM> may have eight transistors that are arranged and configured to provide an <NUM>-transistor (8T) bitcell in the row of <NUM> bitcells <NUM>.

In some implementations, the horizontal bitlines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) may be coupled to the bitcells <NUM> in the 1x8 array, and the horizontal bitlines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) may include the first read bitlines disposed in a horizontal direction with respect to the array of bitcells. The first read bitlines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) include the four (<NUM>) horizontal read bitlines that are disposed in the horizontal direction with respect to the bitcells <NUM>. In some instances, a first read bitline (RBL_H0) may be coupled to the fourth bitcell BC[<NUM>] and the eighth bitcell BC[<NUM>], and a second read bitline (RBL_H1) may be coupled to the third bitcell BC[<NUM>] and the seventh bitcell BC[<NUM>]. Also, a third read bitline (RBL_H2) may be coupled to the second bitcell BC[<NUM>] and the sixth bitcell BC[<NUM>], and a fourth read bitline (RBL_H3) may be coupled to the first bitcell BC[<NUM>] and the fifth bitcell BC[<NUM>].

In some implementations, the horizontal bitlines may also include the first write bitline (WBL) along with the second write bitline (NWBL) that is a complement to the first write bitline (WBL). As shown in <FIG>, the write bitlines (WBL, NWBL) are coupled to each of the bitcells <NUM> in the 1x8 array of bitcells. Therefore, as shown, the 1x8 array of bitcells <NUM> may include eight (<NUM>) bitcells that are arranged in a single row with eight (<NUM>) columns, and at least four (<NUM>) bitcells <NUM> in the 1x8 array may be read in a single cycle, such as, e.g., a read cycle (READ) during a read operation. Also, in some instances, the 1x8 bitcell array may be configured to allow for at least four (<NUM>) wordlines to be active and read in a single cycle, such as, e.g., a read cycle (READ) during a read operation.

Also, in some implementations, the multiple vertical bitlines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7) disclosed in reference to <FIG> may be coupled to the bitcells <NUM> in the 1x8 array of <FIG>, and the vertical bitlines may refer to second read bitlines disposed in a vertical direction with respect to the 1x8 array of bitcells <NUM>. Further, in some instances, the second read bitlines may include the eight (<NUM>) vertical read bitlines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7) that are disposed in the vertical direction with respect to the bitcells <NUM> in the 1x8 array.

Moreover, in some implementations, the 1x8 array of bitcells <NUM> as shown in <FIG> may be modified to include additional rows of bitcells <NUM> in a larger array. For instance, the 1x8 array may be modified to include <NUM> copies of the 1x8 bitcell arrays, e.g., by extending the 1x8 bitcell array to include <NUM> rows of bitcells <NUM> so as to thereby provide an 8x8 array of bitcells <NUM>. In this instance, the memory circuitry <NUM> shown in <FIG> may be adapted to provide an 8x8 array of bitcells <NUM> that may include sixty-four (<NUM>) bitcells that are arranged in eight (<NUM>) rows with eight (<NUM>) columns, and also, thirty-two (<NUM>) bitcells of the bitcells <NUM> in the 8x8 array may be read in a single cycle, such as, e.g., a read cycle (READ) during a read operation. Also, in some instances, the 8x8 bitcell array may be configured to allow for at least four (<NUM>) wordlines to be active and read in a single cycle, such as, e.g., a read cycle (READ) during a read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells <NUM> arranged in a 16x8 array in accordance with implementations described herein.

As shown in <FIG>, the memory array circuitry <NUM> may include multiple 8x8 arrays of bitcells <NUM> that are arranged in a multiple blocks or banks of 8x8 bitcell arrays 412A, 412B. The memory array circuitry <NUM> may also include multiple logic arrays 418A, 418B that are coupled to the multiple 8x8 bitcell arrays 412A, 412B, wherein the multiple logic arrays 418A, 418B are configured to access data stored in bitcells <NUM> of the multiple 8x8 bitcell arrays 412A, 412B. For instance, a first logic array 418A may be coupled to a first 8x8 bitcell array 412A via multiple logic gates (LG0A, LG1A,. , LG7A), and data stored in bitcells <NUM> of the first 8x8 bitcell array 412A may be accessed with multiple read wordlines (RWL[<NUM>]. RWL[<NUM>],. , RWL[<NUM>]) and multiple global read wordlines (GWRL[<NUM>], GRWL[<NUM>],. , GWRL[<NUM>]).

In some instances, in reference to the first logic array 418A, a first write wordline signal (WLA_EN[<NUM>]) may be provided to first logic gates (LG0A, LG1A, LG2A, LG3A) along with a global read enable signal via global read wordlines (GWRL[<NUM>], GRWL[<NUM>], GRWL[<NUM>], GWRL[<NUM>]) for selecting one or more corresponding read wordline (RWL[<NUM>]. RWL[<NUM>], RWL[<NUM>], RWL[<NUM>]) in the first 8x8 bitcell array 412A. Also, a second write wordline signal (WLB_EN[<NUM>]) may be provided to second logic gates (LG4A, LG5A, LG6A, LG7A) along with a global read enable signal via global read wordlines (GWRL[<NUM>], GRWL[<NUM>], GRWL[<NUM>], GWRL[<NUM>]) for selecting one or more corresponding read wordlines (RWL[<NUM>], RWL[<NUM>], RWL[<NUM>] , RWL[<NUM>]) in the first 8x8 bitcell array 412A. Also, in some instances, the first logic array 418A may be coupled to sixty-four (<NUM>) bitcells in a first block of the 8x8 bitcell array 412A for accessing data stored in the first block.

In some instances, in reference to the second logic array 418B, a first write wordline signal (WLA_EN[<NUM>]) may be provided to second logic gates (LG0B, LG1B, LG2B, LG3B) along with a global read enable signal via global read wordlines (GWRL[<NUM>], GRWL[<NUM>], GRWL[<NUM>], GWRL[<NUM>]) for selecting one or more corresponding read wordline (RWL[<NUM>]. RWL[<NUM>], RWL[<NUM>], RWL[<NUM>]) in the second 8x8 bitcell array 412B. Also, a second write wordline signal (WLB_EN[<NUM>]) may be provided to second logic gates (LG4B, LG5B, LG6B, LG7B) along with a global read enable signal via global read wordlines (GWRL[<NUM>], GRWL[<NUM>], GRWL[<NUM>], GWRL[<NUM>]) for selecting one or more corresponding read wordlines (RWL[<NUM>], RWL[<NUM>], RWL[<NUM>] , RWL[<NUM>]) in the second 8x8 bitcell array 412B. In addition, the second logic array 418B may be coupled to sixty-four (<NUM>) bitcells in a second block of the 8x8 bitcell array 412B for accessing data stored in the second block.

Moreover, in some implementations, the 1x8 bitcell array as shown in <FIG> may be extended or modified to include the multiple 8x8 arrays 412A, 412B. For instance, the 1x8 array may be modified to include <NUM> copies of the 1x8 bitcell arrays for each 8x8 bitcell array 412A, 412B so as to thereby provide multiple 8x8 arrays of bitcells <NUM>. In this instance, the memory circuitry <NUM> shown in <FIG> may be adapted to provide a 16x8 memory array of bitcells <NUM> that may include <NUM> copies of the 8x8 memory array having one-hundred twenty-eight (<NUM>) bitcells that are arranged in two (<NUM>) blocks of eight (<NUM>) rows and eight (<NUM>) columns. Also, sixty-four (<NUM>) bitcells in a first block of the 8x8 array 412A may be read in a first single cycle, such as, e.g., a first read cycle (READ) during a read operation. Also, sixty-four (<NUM>) bitcells in a second block of the 8x8 array 412A may be read in a second single cycle, such as, e.g., a second read cycle (READ) during the read operation. Thus, a double-pulse read operation may be used to read <NUM> bits in <NUM> cycles, wherein <NUM> bitcells are read in a first read cycle, and <NUM> other bitcells are read in a second read cycle. Also, the multiple blocks of 8x8 bitcell arrays 412A, 412B may be configured to allow for at least four (<NUM>) wordlines to be active and read in each read cycle of the double-pulse read cycles (READ) during the read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells <NUM> arranged in a 32x16 array in accordance with implementations described herein.

As shown in <FIG>, the memory array circuitry <NUM> may include a 32x16 array having multiple blocks of 16x8 arrays (514A, 514B, 514C, 514D), which include multiple 8x8 arrays (512A, 512B,. For instance, the 32x16 array <NUM> may include a first 16x8 array 514A with multiple 8x8 arrays 512A, 512B, and also, the 32x16 array <NUM> may include a second 16x8 array 514B with multiple 8x8 arrays 512C, 512D. In addition, the 32x16 array <NUM> may include a third 16x8 array 514C with multiple 8x8 arrays 512E, 512F, and also, the 32x16 array <NUM> may include a fourth 16x8 array 514D with multiple 8x8 arrays <NUM>, <NUM>. Also, in some instances, each 8x8 array (512A, 512B,. , <NUM>) may have corresponding logic arrays (518A, 518B,. , <NUM>) that function and operate in a manner as described in <FIG>.

In some instances, the memory array circuitry <NUM> may include control circuitry for each block or bank of bitcell arrays, such as, e.g., an upper or top bank (514A, 514C) and a lower or bottom (bot) bank (514B, 514D). For instance, a first sense amplifier and driver logic (SA + Drivers) 530A along with a first multiplexer and input-output logic (Mux + IO) 540A may be provided as shared control circuitry for the upper bank having the first 16x8 array 514A and the third 16x8 array 514C. Also, a second sense amplifier and driver logic (SA + Drivers) 530B along with a second multiplexer and input-output logic (Mux + IO) 540B may be provided as shared control circuitry for the lower bank having the second 16x8 array 514B and the fourth 16x8 array 514D. In some instances, the memory array circuitry <NUM> may include other shared control circuitry, such as, e.g., first wordline driver circuitry (WDX) 520A for the first 16x8 array 514A and the second 16x8 array 514B along second first wordline driver circuitry (WDX) 520B for the third 16x8 array 514C and the fourth 16x8 array 514D. Further, in some instances, the memory array circuitry <NUM> may include clock circuitry (CLK) <NUM> and input-output clock circuitry (IO CLK) <NUM> that is shared between the four 16x8 arrays (514A, 514B, 514C, 514D).

Moreover, in some implementations, the 1x8 bitcell array as shown in <FIG> may be extended or modified to include the 32x16 memory array <NUM> having multiple 16x8 arrays 514A, 514B, 514C, 514D. For instance, the 1x8 array may be modified to include <NUM> copies of 8x8 bitcell arrays for each 16x8 bitcell array 514A, 514B, 514C, 514D so as to thereby provide the 32x16 memory array <NUM> of bitcells <NUM>. In this instance, the 32x16 memory circuitry <NUM> shown in <FIG> may be adapted to provide a 32x16 memory array of bitcells <NUM> that may include <NUM> copies of the 16x8 memory array having five-hundred twelve (<NUM>) bitcells that are arranged in four (<NUM>) blocks of sixteen (<NUM>) rows and eight (<NUM>) columns. Also, two-hundred fifty-six (<NUM>) bitcells in a first block and a second block of the 16x8 arrays 512A, 512B may be read in a first single cycle, such as, e.g., a first read cycle (READ) during a read operation. Also, two-hundred fifty-six (<NUM>) bitcells in a third block and a fourth block of the 16x8 arrays 512C, 512D may be read in a second single cycle, such as, e.g., a second read cycle (READ) during the read operation. Therefore, a double-pulse read operation may be used to block read <NUM> bits in <NUM> cycles, wherein <NUM> bitcells are read in a first read cycle, and also <NUM> other bitcells are read in a second read cycle. Further, the multiple blocks of 16x8 bitcell arrays 514A, 514B, 514C, 514D may be configured to allow for at least eight (<NUM>) wordlines to be active and read in each read cycle of the double-pulse read cycles (READ) during the read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells arranged in multiple interleaved blocks of 32x16 bitcell arrays in accordance with various implementations described herein. In some implementations, the multiple blocks of 32x16 bitcell arrays may be interleaved to distribute pins during a write operation, wherein block reads may be performed on the same <NUM> bytes from all <NUM> entries.

As shown in <FIG>, the memory array circuitry <NUM> includes multiple blocks of 32x16 arrays with each having multiple blocks of 16x8 arrays, which each have multiple 8x8 arrays. For instance, the multiple blocks of 32x16 arrays may include a first 32x16 block[<NUM>] array with eight (<NUM>) 8x8 arrays, and also, the multiple blocks of 32x16 arrays may include a second 32x16 block[<NUM>] array with eight (<NUM>) 8x8 arrays. In addition, the multiple blocks of 32x16 arrays may include a third 32x16 block[<NUM>] array with eight (<NUM>) 8x8 arrays, and also, the multiple blocks of 32x16 arrays may include a fourth 32x16 block[<NUM>] array with eight (<NUM>) 8x8 arrays. Also, in some instances, each 32x16 array (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) may function and operate in a manner as described in <FIG>.

Moreover, in some implementations, the 1x8 bitcell array as shown in <FIG> may be extended or modified to include the four (<NUM>) 32x16 memory block arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) with each having eight (<NUM>) 8x8 arrays. For instance, the 1x8 array may be modified to include <NUM> copies of 8x8 bitcell arrays for each 32x16 bitcell block array (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) so as to thereby provide the <NUM> blocks of 32x16 memory arrays <NUM> of bitcells <NUM>. In this instance, the 32x16 memory circuitry <NUM> as shown in <FIG> may be adapted to provide the <NUM> blocks of 32x16 memory bitcell arrays that may include <NUM> copies of the 32x16 memory arrays having five-hundred twelve (<NUM>) bitcells that are arranged and also interleaved in four (<NUM>) blocks of thirty-two (<NUM>) rows and sixteen (<NUM>) columns. Also, five-hundred twelve (<NUM>) bitcells in a first block and a second block of the 32x16 arrays (block[<NUM>], block[<NUM>]) may be read in a first single cycle, such as, e.g., a first read cycle (READ) during a read operation. Also, five-hundred twelve (<NUM>) bitcells in a third block and a fourth block of the 32x16 arrays (block[<NUM>], block[<NUM>]) may be read in a second single cycle, such as, e.g., a second read cycle (READ) during the read operation. Therefore, a double-pulse read operation may be used to block read <NUM> bits in <NUM> cycles, wherein <NUM> bitcells are read in a first read cycle, and also <NUM> other bitcells are read in a second read cycle. Further, the multiple blocks of 32x16 bitcell block arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) may be adapted and configured to allow for at least eight (<NUM>) wordlines (e.g., <NUM> vertical wordlines) to be active and read in each read cycle of the double-pulse read cycles (READ) during the read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells arranged in multiple banks of 128x16 arrays in accordance with various implementations described herein. In some implementations, the multiple blocks of 128x16 bitcell arrays may include four (<NUM>) banks of 128x16 memory arrays (bank_0, bank_1, bank_2, bank_3), wherein entry reads may be performed in reference to <NUM> entries with each entry having <NUM> bytes, which refers to <NUM> bits. Also, block reads may be performed in reference to <NUM> blocks of 32x16 arrays, wherein a single block read of 32x16 may be utilized to read <NUM> bitcells in two cycles during a block read operation.

As shown in <FIG>, the memory array circuitry <NUM> includes multiple banks of 128x16 arrays (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) with each having multiple blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>],. , block[<NUM>]), which are based on multiple 8x8 arrays. For instance, the multiple banks of 128x16 arrays include a first 128x16 bank[<NUM>] array with four (<NUM>) blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]), and also, the multiple banks of 128x16 arrays may include a second 128x16 bank[<NUM>] array with four (<NUM>) blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]). In addition, the multiple banks of 128x16 arrays may include a third 128x16 bank[<NUM>] array with four (<NUM>) blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]), and also, the multiple banks of 128x16 arrays may include a fourth 128x16 bank[<NUM>] array with four (<NUM>) blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]). Also, in some instances, each 128x16 bank array (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) may function and operate in a manner as described in reference to <FIG>.

Moreover, in some implementations, the 1x8 bitcell array as shown in <FIG> may be extended or modified to include the four (<NUM>) 128x16 memory bank arrays (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) with each having four (<NUM>) 32x16 arrays. For instance, the 1x8 array may be modified to include <NUM> copies of 8x8 bitcell arrays for each 128x16 bitcell bank array (bank[<NUM>], b[<NUM>], bank[<NUM>], bank[<NUM>]) so as to thereby provide the <NUM> banks of 128x16 memory arrays <NUM> of bitcells <NUM>. In this instance, the 128x16 memory circuitry <NUM> as shown in <FIG> may be adapted to provide the <NUM> banks of 128x16 memory bitcell arrays that may include <NUM> copies of 128x16 memory arrays with each copy having five-hundred twelve (<NUM>) bitcells that are arranged in four (<NUM>) blocks of thirty-two (<NUM>) rows and sixteen (<NUM>) columns. Also, five-hundred twelve (<NUM>) bitcells in a first block and a second block of the 32x16 arrays in each bank may be read in a first single cycle, such as, e.g., a first read cycle (READ) during a read operation. Also, five-hundred twelve (<NUM>) bitcells in a third block and a fourth block of the 32x16 arrays in each bank may be read in a second single cycle, such as, e.g., a second read cycle (READ) during the read operation.

Therefore, a double-pulse read operation may be used to block read <NUM> bits in <NUM> cycles, wherein <NUM> bitcells are read in a first read cycle, and also <NUM> other bitcells are read in a second read cycle. Further, the multiple banks of 128x16 bitcell bank arrays (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) may be adapted and configured to allow for at least eight (<NUM>) wordlines (e.g., <NUM> vertical wordlines) to be active and read in each read cycle of the double-pulse read cycles (READ) during the read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells arranged in multiple interleaved blocks in a 64x16 bitcell array in accordance with various implementations described herein. In some implementations, the multiple blocks in 64x16 bitcell arrays may be block interleaved with eight (<NUM>) copies of 16x8, and block reads may be performed on <NUM> bitcells in a single cycle. When writing, column addresses (CA) may be interleaved based on corresponding row addresses (RA) for each block or for multiple blocks in each bank. In addition, each block of the multiple blocks for each bank may be interleaved during write operations, e.g., by interleaving column addresses (CA) based on row address (RA) for each block or the multiple blocks for each bank.

As shown in <FIG>, the memory array circuitry <NUM> includes a 64x16 bitcell array having multiple interleaved 16x8 blocks with each having multiple 4x8 arrays. For instance, the multiple blocks of 16x8 arrays may include first 4x8 block arrays (block[<NUM>]) with sixteen (<NUM>) 8x8 arrays, and the multiple blocks of 16x8 arrays may include second 4x8 block arrays (block[<NUM>]) with sixteen (<NUM>) 8x8 arrays. Further, each 4x8 array (block[<NUM>], block[<NUM>]) may interleaved during a write operation. Moreover, in some implementations, five-hundred twelve (<NUM>) bitcells may be read in a single cycle, such as, e.g., a first read cycle (READ) during a read operation. Further, the multiple blocks of 4x8 bitcell arrays (block[<NUM>], block[<NUM>]) may be adapted and configured to allow for at least eight (<NUM>) wordlines (e.g., <NUM> vertical wordlines) to be active and read in each read cycle of the single-pulse read cycle (READ) during the read operation.

<FIG> illustrates a diagram <NUM> of memory array circuitry <NUM> with the bitcells arranged in multiple interleaved blocks of 32x16 bitcell arrays in accordance with various implementations described herein. In some implementations, the multiple blocks of 16x8 bitcell arrays may be interleaved to distribute pins during a write operation, wherein block reads may be performed on the same <NUM> bytes from all <NUM> entries.

As shown in <FIG>, the memory array circuitry <NUM> includes multiple blocks of 32x16 arrays with each having multiple interleaved blocks of 16x8 arrays, which each have two 8x8 arrays. For instance, the multiple blocks of 32x16 arrays may include first 32x16 block[<NUM>] arrays with eight (<NUM>) interleaved 8x8 arrays, and also, the multiple blocks of 32x16 arrays may include a second 32x16 block[<NUM>] array with eight (<NUM>) interleaved 8x8 arrays. In addition, the multiple blocks of 32x16 arrays may include a third 32x16 block[<NUM>] array with eight (<NUM>) 8x8 interleaved arrays, and also, the multiple blocks of 32x16 arrays may include a fourth 32x16 block[<NUM>] array with eight (<NUM>) interleaved 8x8 arrays. Also, in some instances, each 32x16 interleaved array (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) may function and operate in a manner as described in <FIG>.

Moreover, in some implementations, five-hundred twelve (<NUM>) bitcells in a first block and a second block of the 32x16 arrays (block[<NUM>], block[<NUM>]) may be read in a first single read cycle (READ) during a read operation. Also, five-hundred twelve (<NUM>) bitcells in a third block and a fourth block of the 32x16 arrays (block[<NUM>], block[<NUM>]) may be read in a second single read cycle (READ) during the read operation. Therefore, a double-pulse read operation may be used to block read <NUM> bits in <NUM> cycles, wherein <NUM> bitcells are read in a first read cycle, and <NUM> other bitcells are read in a second read cycle. Further, the multiple blocks of 32x16 bitcell block arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]) may be adapted and configured to allow for at least eight (<NUM>) wordlines (<NUM> vertical wordlines) to be active and read in each read cycle of the double-pulse read cycles.

<FIG> illustrate multiple diagrams 1000A, 1000B of memory array circuitry 1002A, 1002B with the bitcells in multiple banks of 128x16 arrays in accordance with implementations described herein. In some implementations, each 128x16 bank of the multiple banks of 128x16 arrays are arranged in multiple interleaved blocks of 32x16 bitcell arrays, and the multiple blocks of 16x8 bitcell arrays may be interleaved to distribute pins during a write operation, wherein block reads may be performed on the same <NUM> bytes from all <NUM> entries. Further, in some implementations, the memory array circuitry 1002A, 1002B may include four (<NUM>) banks of 128x16 memory arrays, wherein <NUM> entries may be read during an entry read operation with each entry having <NUM> bytes (<NUM> bits). Also, in reference to a block read operation, <NUM> blocks of 32x16 bitcells may be read in two cycles, wherein a single block of 32x16 (<NUM> bits) may be read in two cycles.

As shown in <FIG>, the multi-bank memory array circuitry 1000A, 1000B includes multiple banks of 128x16 arrays (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) with each having multiple interleaved blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>],. , block[<NUM>]), which are based on multiple interleaved 16x8 arrays. For instance, the multiple banks of 128x16 arrays include a first 128x16 bank[<NUM>] array with four (<NUM>) interleaved blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]), and also, the multiple banks of 128x16 arrays may include a second 128x16 bank[<NUM>] array with four (<NUM>) interleaved blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]). In addition, the multiple banks of 128x16 arrays may include a third 128x16 bank[<NUM>] array with four (<NUM>) interleaved blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]), and also, the multiple banks of 128x16 arrays may include a fourth 128x16 bank[<NUM>] array with four (<NUM>) interleaved blocks of 32x16 arrays (block[<NUM>], block[<NUM>], block[<NUM>], block[<NUM>]). Further, in various instances, each 128x16 bank array (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) may function, operate and/or behave in a manner as described in reference to <FIG>.

Moreover, in some implementations, the 1x8 bitcell array as shown in <FIG> may be extended or modified to include the four (<NUM>) 128x16 memory bank arrays (bank[<NUM>], bank[<NUM>], bank[<NUM>], bank[<NUM>]) with each having four (<NUM>) interleaved 32x16 bitcell arrays. For instance, the 1x8 array may be modified to include <NUM> copies of interleaved 8x8 bitcell arrays for each 128x16 bitcell bank array (bank[<NUM>], b[<NUM>], bank[<NUM>], bank[<NUM>]) so as to thereby provide <NUM> banks of 128x16 memory arrays <NUM> of bitcells <NUM>. In this instance, the 128x16 memory circuitry 1002A, 1002B as shown in <FIG> may be adapted to provide the <NUM> banks of 128x16 memory bitcell arrays that may include <NUM> copies of 128x16 memory arrays with each copy having five-hundred twelve (<NUM>) bitcells that are arranged in four (<NUM>) interleaved blocks of thirty-two (<NUM>) rows and sixteen (<NUM>) columns. Also, five-hundred twelve (<NUM>) bitcells in a first block and a second block of the 32x16 arrays in each bank may be read in a first single read cycle during a read operation. In addition, five-hundred twelve (<NUM>) bitcells in a third block and a fourth block of the 32x16 arrays in each bank may be read in a second single read cycle during the read operation.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. The first element and the second element are both elements, respectively, but they are not to be considered the same element.

The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "includes," "including," "comprises," and/or "comprising," when used in this specification, specify a presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

As used herein, the term "if" may be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" may be construed to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upwardly" and "downwardly"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of various technologies described herein.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.

Claim 1:
A device, comprising:
an array (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) of bitcells (<NUM>, <NUM>); multiple horizontal bitlines (WBL, NWBL, and RBL_H0 - RBL_H3) coupled to the array of bitcells, wherein the multiple horizontal bitlines include first read bitlines (RBL_H0 - RBL_H3) disposed in a horizontal direction with respect to the array of bitcells, a first write bitline (WBL), and a second write bitline (NWBL), wherein the first read bitlines are different from the first write bitline (WBL) and the second write bitline (NWBL);
wherein a first read bitline (RBL_H3) of the first read bitlines is coupled to a first bitcell (BC[<NUM>]) and a fifth bitcell (BC[<NUM>]) in the array of bitcells,
wherein a second read bitline (RBL_H2) of the first read bitlines is coupled to a second bitcell (BC[<NUM>]) and a sixth bitcell (BC[<NUM>]) in the array of bitcells,
wherein a third read bitline (RBL_H1) of the first read bitlines is coupled to a third bitcell (BC[<NUM>]) and a seventh bitcell (BC[<NUM>]) in the array of bitcells, and
wherein a fourth read bitline (RBL_H0) of the first read bitlines is coupled to a fourth bitcell (BC[<NUM>]) and an eighth bitcell (BC[<NUM>]) in the array of bitcells;
multiple vertical bitlines (RBL_V0 - RBL_V7) coupled to the array of bitcells, the multiple vertical bitlines including eight (<NUM>) second read bitlines that are disposed in a vertical direction with respect to the array of bitcells; and
multiple wordlines coupled to the array of bitcells, wherein the multiple wordlines include a write wordline (WWL) and a read wordline (RWL) corresponding to each of the bitcells in the array of bitcells.