Patent Description:
In a Peripheral Component Interconnect Express (Peripheral Component Interconnect express, PCIe) system, devices having PCIe ports may transmit a packet by using the PCIe ports. For example, a central processing unit (Central Processing Unit, CPU) is connected to an upstream port (Upstream Port, UP) of a PCIe switch by using a PCIe port, and a downstream port (Downstream Port, DP) of the PCIe switch is connected to an endpoint (Endpoint, EP) device. When the CPU sends a packet to the EP, first, the CPU sends the packet to the UP of the PCIe switch; next, the UP of the PCIe switch sends the packet to the DP connected to the EP; and next, the DP sends the packet to the EP.

When a link between two PCIe ports becomes faulty, to-be-sent packets are piled up at a PCIe port, that is, packet backpressure occurs. If packet backpressure cannot be detected in a timely manner, instruction timeout occurs in a device for sending a packet. Consequently, the device hangs (hang), and cannot work normally.

An existing packet backpressure detection method is as follows: All to-be-sent packets at a PCIe port are stored in a cache unit. A timer is set for each packet stored in the cache unit, and records storage duration of the packet in the cache unit. When a timer that is set for any packet expires, it is determined that packet backpressure occurs at the PCIe port, and an error packet indicating packet backpressure at the PCIe port is sent to an error processing unit.

However, one device may include multiple PCIe ports, and generally, a large quantity of to-be-sent packets are stored in a cache unit at each PCIe port. In the packet backpressure detection method in the prior art, a large quantity of timer resources are applied for, and an error processing unit receives a large quantity of error processing reports. Consequently, bandwidth within a device is excessively occupied, and resources within the device are wasted.

Document <CIT> discloses Multi-port network device using lookup cost backpressure.

Document <CIT> discloses a method for early cache eviction.

Document <CIT> discloses a method for a configurable packet routing, buffering and scheduling scheme.

This application provides a packet backpressure detection method, apparatus, and device, so as to resolve a prior-art problem that there is an overlarge quantity of overheads in a packet backpressure detection solution. The present invention is defined by the method of independent claim <NUM> and by the apparatus of independent claim <NUM>.

According to a first aspect, a packet backpressure detection method by a device having a Peripheral Component Interconnect Express, PCIe, port, is provided, and the method comprises: storing a plurality of packets that are to be transmitted via the PCIe port in a packet queue in a first buffer and storing a packet that is to be transmitted next in a second buffer; recording a storage duration of each packet stored in the second buffer; determining that packet backpressure occurs at the PCIe port and removing the packet from the second buffer after the packet is transmitted via the PCIe port, when recorded storage duration of any packet in the second buffer reaches a first value; and generating an indication of packet backpressure at the PCIe port.

According to a second aspect, a packet backpressure detection apparatus is provided, wherein the apparatus is applied to a device having a PCIe port, and the apparatus comprises: a cache module, configured to: store a plurality of packets that are to be transmitted via the PCIe port in a packet queue in a first buffer and storing a packet that is to be transmitted next in a second buffer; a timing module, configured to: record a storage duration of each packet stored in the second buffer; a determining module, configured to: determine that packet backpressure occurs at the PCIe port and remove the packet from the second buffer after the packet is transmitted via the PCIe port, when recorded storage duration of any packet in the second buffer reaches a first value; and generate an indication of packet backpressure at the PCIe port.

To describe the technical solutions in the embodiments of this application more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show only some embodiments of this application, and persons of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

To facilitate understanding of the embodiments of this application, the following first describes a PCIe system and a packet backpressure detection method in the prior art.

<FIG> is a schematic diagram of a possible implementation of a PCIe system. An RP <NUM> is a PCIe port of a CPU <NUM>. An SW <NUM> is a PCIe switch (Switch, SW). A UP <NUM> is an upstream port of the SW <NUM>, a DP <NUM> to a DP <NUM> are downstream ports of the SW <NUM>, and an EP <NUM> to an EP <NUM> are endpoint devices. The CPU <NUM> may be a set of multiple CPUs.

The UP <NUM> is configured to: receive, from the RP <NUM> of the CPU <NUM>, a packet to be sent by the CPU <NUM> to an EP, and send the packet to a DP connected to the EP. For example, after receiving a packet to be sent by the CPU <NUM> to the EP <NUM>, the UP <NUM> sends the packet to the DP <NUM> connected to the EP <NUM>, and uses the DP <NUM> to send the packet to the EP <NUM>.

When a link between a DP and an EP becomes faulty, packets to be sent by the CPU to the EP are piled up at the DP, and packet backpressure occurs. If packet backpressure is not found in a timely manner, packet processing in the CPU slows down or becomes stale, and serious instruction timeout even occurs in the CPU. Consequently, the CPU hangs, and cannot work normally.

<FIG> shows a packet detection method in the prior art. In this method, all to-be-sent packets at a DP of a PCIe switch are stored in a cache unit. A timer <NUM> is set for each packet stored in the cache unit, and is configured to record storage duration of the packet in the cache unit. After the packet is sent from a PCIe port, the timer terminates timing performed on the storage duration of the packet. If the timer <NUM> expires, it indicates that the packet is stored in the cache unit for an excessively long time. In other words, the packet fails to be sent from the PCIe port within timeout duration, and it indicates that packet backpressure occurs at the PCIe port. The timer <NUM> reports, to an error processing unit <NUM>, an error report indicating that backpressure occurs at the PCIe port.

However, the PCIe switch includes multiple DPs, and multiple packets (for example, <NUM> packets) can be cached in a cache unit of each DP. If a timer is set for each packet at each DP, a large quantity of timers need to be set in the PCIe switch. Consequently, system overheads increase substantially. In addition, once a link between a DP and an EP becomes faulty, after a timer corresponding to a packet in a cache unit of the DP expires, timers corresponding to a large quantity of other packets in the cache unit expire one after another, the error processing unit <NUM> receives a large quantity of error reports indicating that packet backpressure occurs at one PCIe port, an error report storm even occurs, and a difficulty in resolving a packet backpressure problem by the error processing unit <NUM> is increased. Consequently, bandwidth within a device is excessively occupied, resources within the device are wasted, and normal processing of packet backpressure at the PCIe port by the error processing unit <NUM> is affected.

To resolve the foregoing problems in the prior art, the embodiments of this application provide a packet backpressure detection method and apparatus. The following describes technical solutions of this application in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and specific features of the embodiments are intended to describe the technical solutions of this application in detail, but are not intended to limit the technical solutions of this application. The embodiments of this application and the technical features of the embodiments may be combined with each other if they do not conflict with each other.

<FIG> shows a schematic diagram of a PCIe system in an embodiment of this application. A device <NUM> includes a PCIe port <NUM>, and a device <NUM> includes a PCIe port <NUM>. A packet is transmitted between the device <NUM> and the device <NUM> by using a link between the PCIe port <NUM> and the PCIe port <NUM>.

In the following, an example that the device <NUM> detects packet backpressure that occurs at the PCIe port <NUM> is used for description. <FIG> is a schematic diagram of a detailed structure of the device <NUM>. A cache unit <NUM> is configured to store a to-be-sent packet of the PCIe port <NUM>. When each to-be-sent packet in a packet sending queue of the PCIe port <NUM> becomes a packet that currently needs to be sent at the PCIe port <NUM>, the device <NUM> stores, in a buffer <NUM>, the packet that currently needs to be sent. The packet stored in the buffer <NUM> is removed from the buffer after being sent by using the PCIe port <NUM>. The buffer stores a maximum of one packet at any moment. For example, the packet sending queue of the PCIe port <NUM> is {packet <NUM>, packet <NUM>, packet <NUM>,. The packet <NUM> is the first packet in the packet sending queue, that is, a packet that is in the packet sending queue of the PCIe port and that currently needs to be sent. The packet <NUM> is stored in the buffer <NUM>. After the packet <NUM> is sent by using the PCIe port <NUM>, the stored packet <NUM> is removed from the buffer <NUM>, and the packet <NUM> that is in a packet sending queue {packet <NUM>, packet <NUM>,. } obtained after the packet <NUM> is sent and that currently needs to be sent is stored, and so on. The buffer <NUM> is configured to store, at any moment, one packet that is in the packet sending queue of the PCIe port and that currently needs to be sent. The buffer <NUM> can store another packet only after the stored packet is sent from the PCIe port <NUM>. The buffer <NUM> may be an independent register or another storage device, such as a random access memory RAM or a flash; or the buffer <NUM> may be a storage area obtained by dividing a register or another storage device.

It should be noted that for packets in the cache unit, a sending sequence of the packets may be determined according to packet priorities carried in a request message, or the packets may be sorted according to a preset arbitration policy, and the packets are sent according to a sequence. The present invention imposes no limitation.

Optionally, a capacity of the buffer <NUM> may be that at least two packets in the cache unit <NUM> can be stored. Multiple packets are sorted according to a sending sequence in the cache unit <NUM>. For example, both the packet <NUM> and the packet <NUM> in the cache unit <NUM> in <FIG> are stored in the buffer <NUM>. The packet <NUM> is the first packet in the packet queue of the cache unit <NUM>, that is, a packet that is in the packet sending queue of the PCIe port and that currently needs to be sent. The packet <NUM> is the second packet that needs to be sent in the cache unit <NUM>. The device <NUM> stores the packet <NUM> in the buffer <NUM> in advance, so as to prefetch a to-be-sent packet in the cache unit <NUM>, thereby reducing packet processing duration and improving packet processing efficiency.

A processor <NUM> is responsible for detecting packet backpressure that occurs at the PCIe port <NUM>. Specifically, the processor <NUM> is configured to: record storage duration of each packet stored in the buffer, and accumulate the recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the PCIe port <NUM>.

Optionally, when multiple packets are stored in the buffer, the processor <NUM> is configured to record storage duration of one packet in the buffer. The packet is the first packet in the packet queue of the buffer. For example, as shown in <FIG>, if a sequence of to-be-sent packets in the cache unit <NUM> is {packet <NUM>, packet <NUM>, packet <NUM>,. } and two packets are allowed to store in the device <NUM>, when the packet <NUM> and the packet <NUM> are stored in the buffer <NUM>, a detection sequence of the packet queue of the buffer <NUM> is {packet <NUM>, packet <NUM>}, and the processor <NUM> is configured to record storage duration of the packet <NUM>. After the packet <NUM> is sent from the PCIe port, a detection sequence of the packet queue of the buffer <NUM> is {packet <NUM>, packet <NUM>}, and the processor <NUM> is configured to record storage duration of the packet <NUM>; and so on. The processor <NUM> is configured to: record storage duration of the first packet in the packet queue of the buffer <NUM>, and accumulate recorded storage duration of each packet, so as to obtain the accumulated duration of packet storage in the buffer; and when the accumulated duration reaches the first threshold, determine that packet backpressure occurs at the PCIe port <NUM>.

The processor <NUM> may be a processing component, or may be a set of multiple processing components. The processor <NUM> may be an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), or one or more integrated circuits configured to control program execution of the solution of the present invention. Alternatively, the processor <NUM> is a general purpose processor, such as a central processing unit CPU. The CPU reads an application program instruction in a memory that is in the device <NUM> and that is used to store an executable instruction, and executes the application program instruction, so as to implement functions implemented by the processor <NUM>.

In the solution in which the device <NUM> determines that packet backpressure occurs at the PCIe port <NUM>, timing is performed, at any moment, only on storage duration of a packet stored in the buffer <NUM>, and a quantity of packets stored in the buffer <NUM> is not greater than <NUM>. Therefore, compared with a prior-art solution in which timing is simultaneously performed on all to-be-sent packets at a PCIe port, this solution can substantially reduce system overheads. In addition, when packet backpressure occurs at the PCIe port due to link failure, the device <NUM> generates a packet backpressure error only once for the link failure, thereby avoiding occurrence of an error storm and improving system stability. Moreover, because whether packet backpressure occurs is determined according to the accumulated duration of packet storage in the buffer, the following case can be avoided: although storage duration of no packet exceeds a specified threshold, the device cannot work normally because an accumulated value of storage duration of multiple packets is excessively large.

Optionally, the processor <NUM> of the device <NUM> may set a value of the accumulated duration to the first threshold, and subtract the storage duration of each packet from the accumulated duration each time after recording storage duration of a packet in the buffer <NUM>. When the accumulated duration is less than or equal to <NUM>, the device <NUM> determines that packet backpressure occurs. By using this method, a prior-art problem can be resolved, system overheads are reduced, and accuracy of packet backpressure detection is improved.

Optionally, the processor <NUM> is further configured to reduce the recorded accumulated duration of packet storage in the buffer <NUM> in a prereset condition, so that a case in which the processor <NUM> determines that packet backpressure occurs at the PCIe port because accumulated storage duration of an overlarge quantity of normal packets other than backpressure packets reaches the first threshold can be avoided, and accuracy of packet backpressure detection is improved.

Optionally, an implementation in which the processor <NUM> reduces the recorded accumulated duration of packet storage in the buffer <NUM> in the prereset condition is that the processor <NUM> resets the accumulated duration of packet storage in the buffer <NUM> to <NUM> in a preset condition.

Optionally, an implementation in which the processor <NUM> resets the accumulated duration of packet storage in the buffer <NUM> to <NUM> in the preset condition is to set a resetting timer, perform timing, and when a time recorded by the resetting timer reaches a second threshold, reset the accumulated duration of packet storage in the buffer <NUM> to <NUM>.

Specifically, the time recorded by the resetting timer is a system runtime, that is, the time recorded by the resetting timer starts timing after the device <NUM> is started. The time recorded by the resetting timer is an uninterrupted accumulated time, including a time in which each packet is stored in the buffer, a time in which a packet is moved from the cache unit to the buffer, a time in which the packet is removed from the buffer, and a time in which the buffer is idle. The accumulated duration recorded by the processor <NUM> is only used to record storage duration of a packet in the buffer <NUM>, and a recorded time is an accumulation of multiple time segments. In addition, the second threshold is greater than the first threshold. When the accumulated duration recorded by the processor <NUM> reaches the first threshold, it may be determined that packet backpressure occurs, but no processing is performed on the accumulated duration. When the time recorded by the resetting timer reaches the second threshold, the accumulated duration of packet storage in the buffer <NUM> is reset to <NUM>, so as to improve accuracy of packet backpressure detection.

Optionally, a value of the resetting timer may be directly set to a second threshold, and decreases gradually on a basis of the second threshold. When the value of the resetting timer is equal to <NUM>, the accumulated duration is reset to <NUM>.

Optionally, an implementation in which the processor <NUM> resets the accumulated duration of packet storage in the buffer <NUM> to <NUM> in the preset condition is to record a quantity of packets that have been stored in the buffer <NUM>, and when the recorded quantity reaches a third threshold, reset the accumulated duration of packet storage in the buffer <NUM> to <NUM>.

Optionally, an implementation in which the processor <NUM> reduces the recorded accumulated duration of packet storage in the buffer <NUM> in the prereset condition is as follows: the storage duration that is of each packet in the buffer <NUM> and is successively recorded forms a duration queue. When a length of the duration queue reaches a fourth threshold, the processor deletes earliest- recorded storage duration from the duration queue, and subtracts, from the accumulated duration, the earliest-recorded storage duration that is deleted from the duration queue. In this implementation, the duration queue is similar to a window having a fixed length. When a new packet is stored in the buffer <NUM>, the window moves, so that the accumulated duration is a sum of storage duration, in the buffer <NUM>, of a specified quantity (a value of the specified quantity is the fourth threshold) of packets recently cached in the buffer. By using the window having the fixed length, a peak value of packet storage duration does not fall within two statistical period, so that it is ensured that the peak value of the packet storage duration can always be detected, and sensitivity of packet backpressure detection is improved.

Optionally, the processor <NUM> is further configured to: when recorded storage duration of any packet in the buffer <NUM> reaches a fifth threshold, the device determine that packet backpressure occurs at the PCIe port <NUM>, where the fifth threshold is less than the first threshold. In this implementation, when a packet is cached in the buffer <NUM> for an excessively long time but the accumulated duration does not exceed the first threshold, the processor can determine as soon as possible that packet backpressure occurs at the PCIe port <NUM>, so that sensitivity of packet backpressure detection is improved.

In this embodiment of this application, the device <NUM> may be a CPU, and the PCIe port <NUM> is a PCIe port of the CPU, such as a root port (Root Port, RP) of a root complex (Root Complex, RC) of the CPU. The device <NUM> connected to the CPU may be a switch or an EP. Alternatively, the device <NUM> may be a PCIe switch, and the PCIe port <NUM> is a UP or a DP of the PCIe switch. When the PCIe port <NUM> is a UP, the device <NUM> is a CPU or a DP of another switch. When the PCIe port <NUM> is a DP, the device <NUM> is an EP or a UP of another switch. When the PCIe port <NUM> used as a DP is a non-transparent (non-transparant, NT) port, the device <NUM> may be a CPU. Alternatively, the device <NUM> may be an EP, and the device <NUM> may be a CPU or switch connected to the EP; or the device <NUM> is an EP used as a root complex (Root Complex, RC) in an extended PCIe structure, the PCIe port <NUM> is a port of the RC in the extended PCIe structure, and the device <NUM> is a switch, another EP, or a CPU.

By using an example that the device <NUM> is a PCIe switch, the following describes a packet backpressure detection method provided in an embodiment of this application.

<FIG> is a schematic diagram of a PCIe switch SW <NUM> according to an embodiment of this application. The SW <NUM> includes a UP <NUM> used for connecting to a CPU and a DP <NUM> used for connecting to an EP. The SW <NUM> may include at least one DP, and the DP <NUM> is any one DP of the SW <NUM>. At the DP <NUM>, there is one or more packets to be sent to the EP, and these packets form a packet sending queue. The DP <NUM> sends the packets successively according to a sequence of the packets in the packet sending queue. These to-be-sent packets are stored in a cache unit <NUM> and a buffer <NUM>. The buffer <NUM> stores the first packet in the packet sending queue, that is, a packet that currently needs to be sent, and the buffer <NUM> stores a maximum of one packet at any moment. The cache unit <NUM> is configured to store the second packet and a subsequent packet in the packet sending queue. When a packet stored in the buffer <NUM> is sent to the EP by using the DP <NUM>, a packet that is previously stored in the cache unit <NUM> and that needs to be first sent becomes a packet that currently needs to be sent at the DP <NUM>, and is moved from the cache unit <NUM> to the buffer <NUM>.

Optionally, a capacity of the buffer <NUM> may be that at least two packets can be stored. The capacity of the buffer <NUM> is less than a capacity of the cache unit. Multiple packets are sorted according to a sending sequence in the cache unit <NUM>.

The SW <NUM> further includes a processor <NUM>, configured to: record storage duration of each packet stored in the buffer <NUM>, and accumulate the recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer <NUM>; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the DP <NUM>. For an implementation of the processor <NUM>, refer to the implementation of the processor <NUM>.

Persons skilled in the art may know that <FIG> shows only an example of a packet backpressure detection solution used when the device <NUM> is a PCIe switch, and <FIG> cannot limit the protection scope of this application. For example, when the DP <NUM> is an NT port, the DP <NUM> may be connected to another CPU. For another example, the buffer <NUM> is configured to store a packet that is in a sending queue of packets to be sent by the DP <NUM> to the UP <NUM> and that currently needs to be sent. The processor <NUM> determines, according to accumulated duration of packet storage in the buffer <NUM>, whether packet backpressure occurs in a packet sending direction from the DP <NUM> to the UP <NUM>. Likewise, the packet backpressure detection method is also applicable to detecting whether packet backpressure occurs in a packet sending direction from the UP <NUM> to the DP <NUM>, and is applicable to detecting whether packet backpressure occurs in a packet sending direction from the UP <NUM> to the CPU.

Optionally, the device <NUM> may set a value of the accumulated duration to the first threshold, and subtract the storage duration of each packet from the accumulated duration each time after recording storage duration of a packet in the buffer <NUM>. When the accumulated duration is less than or equal to <NUM>, the device <NUM> determines that packet backpressure occurs. By using this method, a prior-art problem can be resolved, system overheads are reduced, and accuracy of packet backpressure detection is improved.

With reference to the PCIe switch provided in <FIG>, an embodiment of this application provides a method for detecting packet backpressure that occurs at a first port of the PCIe switch. The first port may be either an upstream port or a downstream port of the PCIe switch. Referring to <FIG>, the packet backpressure detection method includes the following steps.

Step <NUM>: when each to-be-sent packet in a packet sending queue of the first port becomes a packet that currently needs to be sent at the first port, the PCIe switch stores, in a buffer, the packet that currently needs to be sent, where the packet stored in the buffer is removed from the buffer after being sent by using the first port, and the buffer stores a maximum of one packet at any moment.

Specifically, the packet that currently needs to be sent at the first port is a packet that should be first sent among all packets that are not sent at the first port. The buffer stores a maximum of one packet at any moment, and stores a next packet only after the stored packet is sent by using the first port. For an implementation of the buffer, refer to the buffer <NUM>.

Because a packet may be sent in an upstream direction or in a downstream direction of the first port, the buffer is configured to store a packet that currently needs to be sent in one of the directions of the first port. When the first port is an upstream port, the upstream direction of the first port is a direction in which a packet is sent from the first port to a CPU, and the downstream direction of the first port is a direction in which a packet is sent from the first port to a downstream port of the PCIe switch. When the first port is a downstream port, the upstream direction of the first port is a direction in which a packet is sent from the first port to an upstream port of the PCIe switch, and the downstream direction of the first port is a direction in which a packet is sent from the first port to an end point EP device.

Step <NUM>: The PCIe switch records storage duration of each packet stored in the buffer, and accumulates the recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer.

For example, it is assumed that no packet is stored in the buffer before a time moment t<NUM>, and the accumulated duration is <NUM>. A packet <NUM> enters the buffer at a time moment t<NUM> after t<NUM>, and is sent from the first port to a destination end (for example, the EP) at a time moment t<NUM> after t<NUM>. Recorded storage duration of the packet <NUM> in the buffer is t<NUM> - t<NUM>, and the accumulated duration of packet storage in the buffer is t<NUM> - t<NUM>. A packet <NUM> enters the buffer at a time moment t<NUM> after t<NUM>, and is sent from the first port to the destination end at a time moment t<NUM> after t<NUM>. Recorded storage duration of the packet <NUM> in the buffer is t<NUM> - t<NUM>, and the accumulated duration of packet storage in the buffer is (t<NUM> - t<NUM>) + (t<NUM> - t<NUM>).

That the PCIe switch records the storage duration of each packet stored in the buffer may be implemented by a processor of the PCIe switch. The processor may be a general purpose processor such as a CPU, and a function of performing timing on the packet stored in the buffer may be implemented by the processor by executing an application program instruction, or may be implemented by the processor by invoking a hardware module used as a timer. Alternatively, the processor may be an integrated circuit such as an ASIC, and a function of performing timing on the packet stored in the buffer may be implemented by a partial circuit structure in the integrated circuit of the processor.

Step <NUM>: When the recorded accumulated duration reaches a first threshold, the PCIe switch determines that packet backpressure occurs at the first port.

Specifically, specific data of the first threshold may be determined by a packet pile-up degree tolerated by a device, and may be set to an empirical value, for example, <NUM>. The first threshold may be set in the PCIe switch by default, or may be set by a user. For example, the processor of the PCIe switch includes a configuration unit, and the configuration unit is configured to: receive configuration data of the user, and determine the first threshold according to the configuration data. When the recorded accumulated duration reaches the first threshold, it indicates that a packet sending speed of the first port is excessively slow, and the processor determines that packet backpressure occurs at the first port.

In the packet backpressure detection method, for packet backpressure in one direction of one PCIe port, timing is performed only on storage duration of one packet in the buffer at any moment. Therefore, compared with a prior-art solution in which timing is simultaneously performed on all to-be-sent packets at a PCIe port, this solution can substantially reduce system overheads. In addition, when packet backpressure occurs at the PCIe port due to link failure, the PCIe switch generates a packet backpressure error only once for the link failure, thereby avoiding occurrence of an error storm and improving system stability. Moreover, because whether packet backpressure occurs is determined according to the accumulated duration of packet storage in the buffer, the following case can be avoided: although storage duration of no packet exceeds a specified threshold, a CPU for sending a packet cannot work normally because an accumulated value of storage duration of multiple packets is excessively large. For example, the PCIe switch includes <NUM> DPs. When the packet backpressure detection method shown in <FIG> is used, a timer corresponding to each packet at each DP does not expire, but storage duration of each packet approximates timeout duration. Because the CPU is affected by packet backpressure at the <NUM> DPs, and storage duration of the packets at the <NUM> DPs in the cache unit approximates the timeout duration, it is likely that instruction timeout occurs in the CPU.

Optionally, referring to <FIG>, in this embodiment of this application, the packet backpressure detection method further includes the following step:
Step <NUM>: The PCIe switch reduces the recorded accumulated duration of packet storage in the buffer in a specified condition.

Step <NUM> may include multiple implementations that include but are not limited to the following manners.

Manner <NUM>: the PCIe switch resets the accumulated duration of packet storage in the buffer <NUM> to <NUM> in a preset condition.

Likewise, the manner <NUM> may have multiple implementations that include the following manners.

In a resetting manner <NUM>, the PCIe switch sets a resetting timer, performs timing, and when a time recorded by the resetting timer reaches a second threshold, resets the accumulated duration of packet storage in the buffer to <NUM>.

For example, the second threshold is set to <NUM>. The resetting timer starts to perform timing from <NUM>, and once the time reaches <NUM>, the processor resets the determined accumulated duration to <NUM>.

After resetting the accumulated duration to <NUM>, the resetting timer starts to perform timing from <NUM> again. Alternatively, after resetting the accumulated duration to <NUM>, the resetting timer continues to perform timing based on the recorded second threshold, and when a value of the resetting timer in each time of timing is increased by the second threshold, resets the accumulated duration to <NUM>.

The resetting timer may be implemented by the processor of the PCIe switch. When the processor is a general purpose processor, the resetting timer may be implemented by the processor by executing an application program instruction, or may be implemented by the processor by invoking a hardware module used as a timer. When the processor is an integrated circuit such as an ASIC, the resetting timer may be implemented by a partial circuit structure in the integrated circuit of the processor.

In a resetting manner <NUM>, the PCIe switch records a quantity of packets that have been stored in the buffer, and when the recorded quantity reaches a third threshold, resets the accumulated duration of packet storage in the buffer to <NUM>.

For example, the third threshold is set to <NUM>. The PCIe switch starts counting from the first packet that is cached in the buffer, and once a quantity obtained by means of counting reaches <NUM>, the PCIe switch resets the accumulated duration of packet storage in the buffer to <NUM>.

After resetting the accumulated duration to <NUM>, for packets that have been stored in the buffer after the accumulated duration is reset to <NUM>, the PCIe switch starts counting from <NUM> again. Alternatively, the PCIe switch continues, based on the recorded third threshold, to count a quantity of packets that have been stored in the buffer, and when a quantity obtained by means of counting is increased by the third threshold, resets the accumulated duration to <NUM>.

That the PCIe switch records a quantity of all packets stored in the buffer may be implemented by the processor of the PCIe switch. When the processor is a general purpose processor, the counting function may be implemented by the processor by executing an application program instruction, or may be implemented by the processor by invoking a hardware module used as a counter. When the processor is an integrated circuit such as an ASIC, the counting function may be implemented by a partial circuit structure in the integrated circuit of the processor.

Either the resetting manner <NUM> or the resetting manner <NUM> may be selected for implementation, or both the two resetting manners may be implemented. When both the two resetting manners are implemented, once the time recorded by the resetting timer reaches the second threshold or the quantity that is of packets stored in the buffer and that is obtained by means of counting reaches the third threshold, the PCIe switch resets, to <NUM>, the accumulated duration determined by the resettinga packet timer to <NUM>. In an optional implementation, when the time recorded by the resetting timer reaches the second threshold, the PCIe switch needs to reset, to <NUM>, both the time recorded by the resetting timer and the quantity that is of packets stored in the buffer and that is obtained by means of counting. When the quantity that is of packets stored in the buffer and that is obtained by means of counting reaches the third threshold, the PCIe switch needs to reset, to <NUM>, both the time recorded by the resetting timer and the quantity that is of packets stored in the buffer and that is obtained by means of counting. In another optional implementation, when the time recorded by the resetting timer reaches the second threshold, the PCIe switch resets, to <NUM>, the time recorded by the resetting timer, but does not reset, to <NUM>, the quantity that is of packets stored in the buffer and that is obtained by means of counting. When the quantity that is of packets stored in the buffer and that is obtained by means of counting reaches the third threshold, the PCIe switch resets, to <NUM>, the quantity that is of packets stored in the buffer and that is obtained by means of counting, but does not reset, to <NUM>, the time recorded by the resetting timer.

Because storage duration of any packet that is cached in the buffer is greater than <NUM>, after a sufficient quantity of packets are cached in the buffer, or after a packet is cached in the buffer for an enough long time, the accumulated duration of packet storage in the buffer can certainly reach the first threshold. It can be learned from this embodiment of this application that packet backpressure does not occur in a case in which the accumulated duration of packet storage in the buffer reaches the first threshold because the buffer caches a packet for an excessively long time. Likewise, packet backpressure does not occur in a case in which the accumulated duration of packet storage in the buffer reaches the first threshold because an overlarge quantity of packets are cached in the buffer buffer.

In the manner <NUM>, after a packet is stored in the buffer for an enough long time (that is, the second threshold), or a sufficient quantity (that is, the third threshold) of packets are stored in the buffer, the PCIe switch can reset the accumulated duration of packet storage in the buffer to <NUM>, so that a case in which the PCIe switch determines that packet backpressure occurs at the first port because accumulated storage duration of an overlarge quantity of normal packets other than backpressure packets reaches the first threshold can be avoided, and accuracy of packet backpressure detection is improved.

Manner <NUM>: The storage duration that is of each packet in the buffer and is successively recorded by the PCIe switch forms a duration queue. When a length of the duration queue reaches a fourth threshold, the PCIe switch deletes the first recorded storage duration from the duration queue, and subtracts, from the accumulated duration, the first recorded storage duration that is deleted from the duration queue.

Specifically, the PCIe switch successively records storage duration of packets in the buffer, and the recorded duration forms a duration queue according to a recording sequence. Duration at the beginning of the duration queue is the earliest-recorded storage duration in the duration queue. For example, first, a packet <NUM> is stored the buffer, and storage duration is Δt<NUM>. Next, a packet <NUM> is stored, and storage duration is Δt<NUM>. Next, a packet <NUM> is stored, and storage duration is Δt<NUM>. In this case, the duration queue is (Δt<NUM>, Δt<NUM>, Δt<NUM>), and Δt<NUM> at the beginning of the duration queue is the earliest-recorded duration in all the storage duration included in the duration queue. It is assumed that the fourth threshold is <NUM>. A packet <NUM> is stored in the buffer after the packet <NUM> is sent, and a resetting timer records storage duration Δt<NUM> of the packet <NUM>. In this case, a length of the duration queue reaches <NUM>, and the restting timer deletes the earliest-recorded storage duration Δt<NUM> from the duration queue, to form a new duration queue (Δt<NUM>, Δt<NUM>, Δt<NUM>). Correspondingly, the accumulated duration, recorded by the resetting timer, of packet storage in the buffer changes from (Δt<NUM> + Δt<NUM> + Δt<NUM>) to (Δt<NUM> + Δt<NUM> + Δt<NUM>).

Referring to a diagram of a relationship between packet storage duration and a packet sequence number shown in <FIG>, the duration queue is similar to a window having a fixed length. When a new packet is stored in the buffer, the window moves, so that the accumulated duration is a sum of storage duration, in the buffer, of a specified quantity (a value of the specified quantity is the fourth threshold) of packets recently cached in the buffer. By using the window having the fixed length, a peak value of packet storage duration does not fall within two statistical units, so that it is ensured that the peak value of the packet storage duration can always be detected, and sensitivity of packet backpressure detection is improved.

An example that the peak value of packet storage duration falls within two statistical units is as follows: assuming that the third threshold is <NUM>, a packet counter starts counting from a packet whose number is <NUM>, and when counting to a packet whose number is <NUM>, the packet counter resets, to <NUM>, the accumulated duration determined by the resetting timer. Because a sum of storage duration of packets whose numbers are <NUM> to <NUM> does not exceed the first threshold, packet backpressure fails to be detected. Likewise, when a packet whose number is <NUM> is detected, the packet counter again resets, to <NUM>, the accumulated duration determined by the resetting timer. Because a sum of storage duration of packets whose numbers are <NUM> to <NUM> does not exceed the first threshold, packet backpressure fails to be detected. However, because the peak value of the packet storage duration appears near the packet whose number is <NUM>, actually, a sum of storage duration of packets whose numbers are <NUM> to <NUM> is already greater than the first threshold, and packet backpressure already occurs. However, because the peak value of the packet storage duration falls within two statistical units, packet backpressure fails to be detected.

Either the manner <NUM> or the manner <NUM> may be implemented, or both the two manners may be implemented. When both the two manners are implemented, the fourth threshold is set to be less than a numeric value of the third threshold, for example, the third threshold is <NUM>, and the fourth threshold is <NUM>.

Alternatively, in the manner <NUM>, the PCIe switch accumulates all duration in a duration queue, so as to obtain window duration, and when a length of the duration queue reaches a fourth threshold, deletes the earliest-recorded storage duration from the duration queue, and subtracts, from the window duration, the earliest-recorded storage duration that is deleted from the duration queue. When the window duration reaches a sixth threshold, the PCIe switch determines that packet backpressure occurs at the first port. Because the window duration is not reset to <NUM>, it is ensured that a peak value of packet storage duration can always be detected, and sensitivity of packet backpressure detection is improved.

Optionally, in a possible embodiment of this application, the packet backpressure detection method further includes the following step:.

Step <NUM>: When recorded storage duration of any packet in the buffer reaches a fifth threshold, the PCIe switch determines that packet backpressure occurs at the first port, where the fifth threshold is less than the first threshold.

Specifically, the PCIe switch can not only determine, according to the accumulated duration of a packet cache time, whether packet backpressure occurs, but also determine that packet backpressure occurs, provided that storage duration of any packet is greater than the fifth threshold. Therefore, when a packet is cached in the buffer for an excessively long time but the accumulated duration does not exceed the first threshold, the PCIe switch determines as soon as possible that packet backpressure occurs, so that sensitivity of packet backpressure detection is improved. The fifth threshold is less than the first threshold, for example, the first threshold is <NUM>, and the fifth threshold is <NUM>.

Optionally, in this embodiment of this application, after determining that packet backpressure occurs, the PCIe switch generates a packet backpressure error, and processes packet backpressure according to the packet backpressure error. For a manner in which the PCIe switch processes packet backpressure, refer to various packet backpressure processing manners in the prior art, for example, the PCIe switch disconnects a link in which packet backpressure occurs, or sends a message signal interrupt (Message Signal Interrupt, MSI) to the CPU. In addition, the packet backpressure error report generated by the PCIe switch may further include packet header information of a packet that makes the accumulated duration reach the first threshold.

Optionally, in a possible embodiment of this application, the second threshold to the sixth threshold may be set by default, or may be set by a user. Specifically, the processor of the PCIe switch includes a configuration unit, and the configuration unit is configured to: receive configuration data of the user, and determine the second threshold to the sixth threshold according to the configuration data.

Optionally, in a possible embodiment of this application, a PCIe switch can detect packet backpressure in upstream and downstream two directions of one port (a UP or a DP) of the PCIe switch by using a same processor.

As shown in <FIG>, a buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from a DP <NUM> to an EP and that currently needs to be sent. A second buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from the DP <NUM> to a UP <NUM> and that currently needs to be sent. A second cache unit <NUM> is configured to store the second packet and a subsequent packet in the packet sending queue in the sending direction from the DP <NUM> to the UP <NUM>. A processor <NUM> is configured to: record storage duration of each packet in the buffer <NUM>, and accumulate the recorded storage duration, so as to obtain a first accumulated duration of packet storage in the buffer <NUM>; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the DP <NUM>. The processor <NUM> is further configured to: record storage duration of each packet in the second buffer <NUM>, and accumulate the recorded storage duration, so as to obtain second accumulated duration of packet storage in the second buffer <NUM>; and when the second accumulated duration reaches the first threshold, determine that packet backpressure occurs at the DP <NUM>.

In an optional implementation, the processor <NUM> is configured to reduce the accumulated duration and the second accumulated duration in a prereset condition. The processor <NUM> reduces the first accumulated duration and the second accumulated duration by using the manner <NUM>, the manner <NUM>, or a combination of the two manners.

For an implementation in which the processor <NUM> detects packet backpressure in the packet sending direction from the DP <NUM> to the UP <NUM> and in the packet sending direction from the DP <NUM> to the EP, refer to the implementations of step <NUM> to step <NUM>.

Optionally, in this embodiment of this application, a PCIe switch can detect, by using a same processor, packet backpressure occurs at different ports of the PCIe switch.

As shown in <FIG>, a buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from a DP <NUM> to an EP <NUM> and that currently needs to be sent. A third buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from a DP <NUM> to an EP <NUM> and that currently needs to be sent. A third cache unit <NUM> is configured to store the second packet and a subsequent packet in the packet sending queue in the sending direction from the DP <NUM> to EP <NUM>. A processor <NUM> is configured to: record storage duration of each packet in the buffer <NUM>, and accumulate the recorded storage duration, so as to obtain accumulated duration of packet storage in the buffer <NUM>; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the DP <NUM>. The processor <NUM> is further configured to: record storage duration of each packet in the third buffer <NUM>, and accumulate the recorded storage duration, so as to obtain third accumulated duration of packet storage in the third buffer <NUM>; and when the third accumulated duration reaches the first threshold, determine that packet backpressure occurs at the DP <NUM>.

In an optional implementation, the processor <NUM> is further configured to: reduce the first accumulated duration in a prereset condition, and reduce the second accumulated duration in a prereset condition. The processor <NUM> reduces the first accumulated duration and the second accumulated duration by using the manner <NUM>, manner <NUM>, or a combination thereof.

For an implementation in which the processor <NUM> detects packet backpressure in the packet sending direction from the DP <NUM> to the EP <NUM> and in the packet sending direction from the DP <NUM> to the EP <NUM>, refer to the implementations of step <NUM> to step <NUM>.

Optionally, in a possible embodiment of this application, a PCIe switch can detect, by using different processors, packet backpressure that occurs at different ports of the PCIe switch.

As shown in <FIG>, a buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from a DP <NUM> to an EP <NUM> and that currently needs to be sent. A third buffer <NUM> is configured to store a packet that is in a packet sending queue in a sending direction from a DP <NUM> to an EP <NUM> and that currently needs to be sent. A processor <NUM> is configured to: record storage duration of each packet in the buffer <NUM>, and accumulate the recorded storage duration, so as to obtain accumulated duration of packet storage in the buffer <NUM>; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the DP <NUM>. A processor <NUM> is configured to: record storage duration of each packet in a third buffer <NUM>, and accumulate the recorded storage duration, so as to obtain fourth accumulated duration of packet storage in the third buffer <NUM>; and when the fourth accumulated duration reaches the first threshold, determine that packet backpressure occurs at the DP <NUM>.

In an optional implementation, the processor <NUM> is further configured to reduce the first accumulated duration in a prereset condition, and the processor <NUM> is further configured to reduce the fourth accumulated duration in a prereset condition. The processor <NUM> and the processor <NUM> respectively reduce the first accumulated duration and the fourth accumulated duration by using the manner <NUM>, the manner <NUM>, or a combination of the two manners.

For an implementation in which the processor <NUM> detects packet backpressure in the packet sending direction from the DP <NUM> to the EP <NUM> and an implementation in which the processor <NUM> detects packet backpressure in the packet sending direction from the DP <NUM> to the EP <NUM>, refer to the implementations of step <NUM> to step <NUM>.

It should be noted that the packet backpressure detection method corresponding to <FIG> is also applicable to detecting whether packet backpressure occurs at a PCIe port of a CPU or an EP. Details are not described herein again in this embodiment of this application.

<FIG> is a schematic diagram of a packet backpressure detection apparatus <NUM> according to an embodiment of this application. The apparatus <NUM> is applied to a device having a PCIe port, and the apparatus <NUM> includes:.

The apparatus <NUM> may be implemented by using an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC) or a programmable logic device (Programmable Logic Device, PLD). The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL), or any combination thereof. When the packet backpressure detection method shown in <FIG> is implemented by using software, the apparatus <NUM> and the modules of the apparatus <NUM> may be software modules.

Optionally, the buffer of the apparatus <NUM> stores a maximum of one packet at any moment.

Optionally, the buffer of the apparatus <NUM> may store at least two packets. Multiple packets are sorted according to a sending sequence in a cache unit. A capacity of the buffer is less than a capacity of the cache unit. The device is configured to: record storage duration of a packet in the buffer, where the packet is the first packet in a packet queue of the buffer, and accumulate recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer; and when the accumulated duration reaches the first threshold, determine that packet backpressure occurs at the PCIe port.

In an optional implementation, the device may subtract the storage duration of each packet from the first threshold each time after recording storage duration of a packet in the buffer. When the first threshold is less than or equal to <NUM>, the device determines that packet backpressure occurs. By using this method, a prior-art problem can be resolved, system overheads are reduced, and accuracy of packet backpressure detection is improved.

Optionally, in this embodiment of this application, the apparatus <NUM> further includes:
a time resetting module <NUM>, configured to reset the accumulated duration determined by the timing module to <NUM> in a preset condition.

Optionally, in this embodiment of this application, the time resetting module <NUM> is specifically configured to:
set a resetting timer, perform timing, and when a time recorded by the resetting timer reaches a second threshold, reset the accumulated duration determined by the timing module to <NUM>.

Optionally, in a possible embodiment of this application, the time resetting module <NUM> is specifically configured to:
record a quantity of packets that have been stored in the buffer, and when the quantity reaches a third threshold, reset the accumulated duration determined by the timing module to <NUM>.

Optionally, in a possible embodiment of this application, the storage duration that is of each packet and is successively recorded by the timing module <NUM> forms a duration queue, and the apparatus <NUM> further includes:
a timing control module <NUM>, configured to: when a length of the duration queue reaches a fourth threshold, delete earliest-recorded storage duration from the duration queue, and subtract, from the accumulated duration determined by the timing module, the earliest-recorded storage duration that is deleted from the duration queue.

Optionally, in a possible embodiment of this application, the determining module <NUM> is further configured to:when storage duration that is of any packet in the buffer and is recorded by the timing module reaches a fifth threshold, determine that packet backpressure occurs at the PCIe port, where the fifth threshold is less than the first threshold.

For implementations of the modules included in the apparatus <NUM>, refer to the implementations of step <NUM> to step <NUM>. It should be noted that the apparatus <NUM> is not limited to being applied to a PCIe switch, but may be applied to a CPU or an EP.

<FIG> is a schematic diagram of a packet backpressure detection device <NUM> according to an embodiment of this application. The device <NUM> includes a bus <NUM>, and a PCIe port <NUM>, a memory <NUM>, and a processor <NUM> that are separately connected to the bus <NUM>.

The PCIe port <NUM> is configured to send a packet.

The memory <NUM> is configured to store a packet sending queue of the PCIe port.

The processor <NUM> is configured to: when each to-be-sent packet in the packet sending queue of the PCIe port <NUM> becomes a packet that currently needs to be sent at the PCIe port <NUM>, store, in a buffer, the packet that needs to be sent, where the packet stored in the buffer is removed from the buffer after being sent by using the PCIe port <NUM>; record storage duration of each packet stored in the buffer, and accumulate the recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer; and when the accumulated duration reaches a first threshold, determine that packet backpressure occurs at the PCIe port <NUM>.

Optionally, in this embodiment of this application, the memory <NUM> is further configured to store an instruction.

The processor <NUM> is configured to execute the instruction stored in the memory <NUM>, so as to implement a function of the processor <NUM>.

Optionally, the buffer stores a maximum of one packet at any moment.

Optionally, a capacity of the buffer may be that at least two packets can be stored, and the capacity of the buffer is less than a capacity of a cache unit. The processor <NUM> is configured to: record storage duration of the first packet in a packet queue of the buffer, and accumulate recorded storage duration of each packet, so as to obtain accumulated duration of packet storage in the buffer.

Optionally, in this embodiment of this application, the processor <NUM> is further configured to reset the accumulated duration to <NUM> in a preset condition.

Optionally, in this embodiment of this application, that the processor <NUM> is configured to reset the accumulated duration to <NUM> in the preset condition includes:
setting a resetting timer, performing timing, and when a time recorded by the resetting timer reaches a second threshold, resetting the accumulated duration to <NUM>.

Optionally, in this embodiment of this application, that the processor <NUM> is configured to reset the accumulated duration to <NUM> in the preset condition includes:
recording a quantity of packets that have been stored in the buffer, and when the quantity reaches a third threshold, resetting the accumulated duration to <NUM>.

Optionally, in this embodiment of this application, the storage duration that is of each packet and is successively recorded by the processor <NUM> forms a duration queue, and the processor <NUM> is further configured to:
when a length of the duration queue reaches a fourth threshold, delete the first recorded storage duration from the duration queue, and subtract, from the accumulated duration, the first recorded storage duration that is deleted from the duration queue.

Optionally, in this embodiment of this application, the processor <NUM> is further configured to:
when recorded storage duration of any packet in the buffer reaches a fifth threshold, determine that packet backpressure occurs at the PCIe port, where the fifth threshold is less than the first threshold.

Optionally, in this embodiment of this application, the device further includes a second PCIe port <NUM>.

The processor <NUM> is further configured to: when each to-be-sent packet in a packet sending queue of the second PCIe port <NUM> becomes a packet that currently needs to be sent at the second PCIe port, store, in a third buffer, the packet that needs to be sent at the second PCIe port <NUM>, where the packet stored in the third buffer is removed from the third buffer after being sent by using the second PCIe port <NUM>, and the third buffer stores a maximum of one packet at any moment; record storage duration of each packet stored in the third buffer, and accumulate the recorded storage duration of each packet stored in the third buffer, so as to obtain third accumulated duration of packet storage in the third buffer; and when the third accumulated duration reaches the first threshold, determine that packet backpressure occurs at the second PCIe port <NUM>.

For implementations of the components of the device <NUM>, refer to the implementations of step <NUM> to step <NUM>. It should be noted that the device <NUM> is not limited to a PCIe switch, but may also be a CPU or an EP.

The processor <NUM> may be a CPU, may be an MCPU, or may be another general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), another programmable logic device, or the like. The general purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The memory includes: any medium that can store program code, such as a universal serial bus (Universal Serial Bus, USB) flash drive, a removable hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc.

An embodiment of this application provides a server, and the server includes a device <NUM> that can implement the packet backpressure detection method.

An embodiment of this application provides a storage controller, and the storage controller includes a device <NUM> that can implement the packet backpressure detection method.

An embodiment of this application further provides a computer-readable medium, configured to store a computer program. The computer program includes an instruction for performing steps in a packet backpressure detection method corresponding to any one of <FIG> or <FIG> and in any optional implementation of the method.

Further embodiments of the present invention are provided in the following. It should be noted that the numbering used in the following section does not necessarily need to comply with the numbering used in the previous sections.

Embodiment <NUM>. A packet backpressure detection method, wherein the method is applied to a device having a Peripheral Component Interconnect Express PCIe port, and the method comprises:.

when the accumulated duration reaches a first threshold, determining, by the device, that packet backpressure occurs at the PCIe port.

Embodiment <NUM>. The method according to embodiment <NUM>, wherein:
the buffer stores a maximum of one packet at any moment.

Embodiment <NUM>. The method according to embodiment <NUM>, further comprising:
a capacity of the buffer is that at least two packets can be stored, and the capacity of the buffer is less than a capacity of a cache unit.

Embodiment <NUM>. The method according to any one of embodiments <NUM> to <NUM>, further comprising:
resetting, by the device, the accumulated duration to <NUM> in a preset condition.

Embodiment <NUM>. The method according to embodiment <NUM>, wherein the resetting, by the device, the accumulated duration to <NUM> in a preset condition comprises:
setting, by the device, a resetting timer, performing timing, and when a time recorded by the resetting timer reaches a second threshold, resetting the accumulated duration to <NUM>.

Embodiment <NUM>. The method according to embodiment <NUM>, wherein the resetting, by the device, the accumulated duration to <NUM> in a preset condition comprises:
recording, by the device, a quantity of packets that have been stored in the buffer, and when the quantity reaches a third threshold, resetting the accumulated duration to <NUM>.

Embodiment <NUM>. The method according to any one of embodiments <NUM> to <NUM>, wherein the storage duration that is of each packet and is successively recorded by the device forms a duration queue, and the method further comprises:
when a length of the duration queue reaches a fourth threshold, deleting, by the device, the earliest-recorded storage duration from the duration queue, and subtracting, from the accumulated duration, the earliest-recorded storage duration that is deleted from the duration queue.

Embodiment <NUM>. The method according to any one of embodiments <NUM> to <NUM>, further comprising:
when recorded storage duration of any packet in the buffer reaches a fifth threshold, determining, by the device, that packet backpressure occurs at the PCIe port, wherein the fifth threshold is less than the first threshold.

Embodiment <NUM>. The method according to any one of embodiments <NUM> to <NUM>, wherein the storing, by the device in a buffer when each to-be-sent packet in a packet sending queue of the PCIe port becomes a packet that currently needs to be sent at the PCIe port, the packet that needs to be sent comprises:.

Embodiment <NUM>. A packet backpressure detection apparatus, wherein the apparatus is applied to a device having a PCIe port, and the apparatus comprises:.

Embodiment <NUM>. The apparatus according to embodiment <NUM>, wherein:
the buffer stores a maximum of one packet at any moment.

Embodiment <NUM>. The apparatus according to embodiment <NUM>, further comprising:
a capacity of the buffer is that at least two packets can be stored, and the capacity of the buffer is less than a capacity of a cache unit.

Embodiment <NUM>. The apparatus according to any one of embodiments <NUM> to <NUM>, further comprising:
a time resetting module, configured to reset the accumulated duration determined by the timing module to <NUM> in a preset condition.

Embodiment <NUM>. The apparatus according to embodiment <NUM>, wherein the time resetting module is specifically configured to:
set a resetting timer, perform timing, and when a time recorded by the resetting timer reaches a second threshold, reset the accumulated duration determined by the timing module to <NUM>.

Embodiment <NUM>. The apparatus according to claim <NUM>, wherein the time resetting module is specifically configured to:
record a quantity of packets that have been stored in the buffer, and when the quantity reaches a third threshold, reset the accumulated duration determined by the timing module to <NUM>.

Embodiment <NUM>. The apparatus according to any one of embodiments <NUM> to <NUM>, wherein the storage duration that is of each packet and is successively recorded by the timing module forms a duration queue, and the apparatus further comprises:
a timing control module, configured to: when a length of the duration queue reaches a fourth threshold, delete earliest-recorded storage duration from the duration queue, and subtract, from the accumulated duration determined by the timing module, the earliest-recorded storage duration that is deleted from the duration queue.

Embodiment <NUM>. The apparatus according to any one of embodiments <NUM> to <NUM>, wherein the determining module is further configured to:
when storage duration that is of any packet in the buffer and is recorded by the timing module reaches a fifth threshold, determine that packet backpressure occurs at the PCIe port, wherein the fifth threshold is less than the first threshold.

Embodiment <NUM>. A packet backpressure detection device, comprising a processor, a memory, a PCIe port, and a bus, wherein the processor, the memory, and the PCIe port are connected and implement mutual communication by using the bus, the memory is configured to store a computer execution instruction, and when the device runs, the processor executes the computer execution instruction in the memory, so as to execute the operation of the method according to any one of claims <NUM> to <NUM> by using a hardware resource in the device.

In an embodiment of this application, combination may be made on a basis of implementations provided in the foregoing aspects, so as to provide more implementations.

Persons skilled in the art should understand that the embodiments of this application may be provided as a method, a system, or a computer program product. Moreover, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a disk memory, a CD-ROM, and an optical memory) that include computer-usable program code.

Claim 1:
A packet backpressure detection method by a device having a Peripheral Component Interconnect Express, PCIe, port, and the method comprises:
storing a plurality of packets that are to be transmitted via the PCIe port in a packet queue in a first buffer and storing a packet that is to be transmitted next in a second buffer (<NUM>);
recording a storage duration of each packet stored in the second buffer (<NUM>);
determining that packet backpressure occurs at the PCIe port and removing the packet from the second buffer after the packet is transmitted via the PCIe port, when recorded storage duration of any packet in the second buffer reaches a first value (<NUM>); and
generating an indication of packet backpressure at the PCIe port.