Patent Description:
Advances in integrated circuit technology have made it possible to embed an entire system, such as including a processor core, a memory controller, and a bus, in a single semiconductor chip. This type of chip is commonly referred to as a system-on-chip (SoC). Other SoCs can have different components embedded therein for different applications. The SoC provides many advantages over traditional processor-based designs. It is an attractive alternative to multi-chip designs because the integration of components into a single device increases overall speed while decreasing size. The SoC is also an attractive alternative to fully customized chips, such as an application specific integrated circuit (ASIC), because ASIC designs tend to have a significantly longer development time and larger development costs. A configurable SoC (CSoC), which includes programmable logic, has been developed to implement a programmable semiconductor chip that can obtain benefits of both programmable logic and SoC.

An SoC can contain a packet network structure known as a network on a chip (NoC) to route data packets between logic blocks in the SoC - e.g., programmable logic blocks, processors, memory, and the like. A NoC in a non-programmable SoC has an irregular topology, static route configurations, fixed quality-of-service (QoS) paths, non-programmable address mapping, non-programmable routes, and egress/ingress nodes with a fixed interface protocol, width, and frequency. It is desirable to provide a more programmable and configurable NoC within an SoC.

The <CIT> discloses a configurable directional 2D router for Networks on Chips (NOCs). The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one <NUM>-LUT or <NUM>-input ALM logic cell per router per bit of router link width.

The <CIT> discloses a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

The <CIT> and <CIT> disclose a method of generating a configuration for a network on chip (NoC) in a programmable device including: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

Techniques for providing a configurable NoC for a programmable device are described.

These and other aspects may be understood with reference to the following detailed description.

It is to be noted that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described.

<FIG> is a block diagram depicting a programmable device with an embedded system-on-chip (SoC) subsystem (SoC <NUM>) according to an example. The SoC <NUM> is an integrated circuit (IC) that includes a plurality of regions having circuitry with different functionalities. In the example, the SoC <NUM> includes programmable logic (PL) regions <NUM>, a processing system (PS) <NUM>, a network-on-chip (NoC) <NUM>, and input/output (IO) region <NUM>. In some examples, the SoC <NUM> includes hardened circuits <NUM>, such as memory controllers, math engines, or the like. The programmable logic region(s) <NUM> can include any number of configurable logic blocks (CLBs), which may be programmed or configured to form specific circuitry. The PS <NUM> can include one or more processor cores and associated support circuitry. For example, the processing system can include a number of ARM-based embedded processor cores. The NoC <NUM> includes an interconnecting network for sharing data between endpoint circuits in the SoC <NUM>. The endpoint circuits can be disposed in the PL regions <NUM>, the PS <NUM>, the hardened circuits <NUM>, and/or the IO region <NUM>. The NoC <NUM> can include high-speed data paths with dedicated switching. In an example, the NoC <NUM> includes horizontal paths, vertical paths, or both horizontal and vertical paths. The IO region <NUM> can include input/output blocks (IOBs) and the like for transmitting and receiving signals external to the SoC <NUM>. The arrangement and number of regions shown in <FIG> is merely an example. In general, the SoC <NUM> includes one or more PL regions <NUM>, a PS <NUM>, and a NoC <NUM>.

<FIG> is a block diagram depicting the NoC <NUM> according to an example. The NoC <NUM> includes NoC master units (NMUs) <NUM>, NoC slave units (NSUs) <NUM>, a network <NUM>, NoC peripheral interconnect (NPI) <NUM>, and registers <NUM>. Each NMU <NUM> is an ingress circuit that connects an endpoint circuit to the NoC <NUM>. Each NSU <NUM> is an egress circuit that connects the NoC <NUM> to an endpoint circuit. The NMUs <NUM> are connected to the NSUs <NUM> through the network <NUM>. In an example, the network <NUM> includes NoC packet switches <NUM> ("NPSs") and routing <NUM> between the NoC packet switches <NUM>. Each NoC packet switch <NUM> performs switching of NoC packets. The NoC packet switches <NUM> are connected to each other and to the NMUs <NUM> and NSUs <NUM> through the routing <NUM> to implement a plurality of physical channels. The NoC packet switches <NUM> also support multiple virtual channels per physical channel. The NPI <NUM> includes circuitry to program the NMUs <NUM>, NSUs <NUM>, and NoC packet switches <NUM>. For example, the NMUs <NUM>, NSUs <NUM>, and NoC packet switches <NUM> can include registers <NUM> that determine functionality thereof. The NPI <NUM> includes a peripheral interconnect coupled to the registers <NUM> for programming thereof to set functionality. The registers <NUM> in the NoC <NUM> support interrupts, QoS, error handling and reporting, transaction control, power management, and address mapping control. The registers <NUM> can be initialized in a usable state before being reprogrammed, such as by writing to the registers <NUM> using write requests. Configuration data for the NoC <NUM> can be stored in a non-volatile memory (NVM) and provided to the NPI <NUM> for programming the NoC <NUM> and/or other endpoint circuits.

The NMUs <NUM> are traffic ingress points. The NSUs <NUM> are traffic egress points. Endpoint circuits coupled to the NMUs <NUM> and NSUs <NUM> can be hardened circuits (e.g., hardened circuits <NUM>) or circuits configured in programmable logic. A given endpoint circuit can be coupled to more than one NMU <NUM> or more than one NSU <NUM>.

<FIG> is a block diagram depicting connections between endpoint circuits in an SoC through the NoC <NUM> according to an example. In the example, endpoint circuits <NUM> are connected to endpoint circuits <NUM> through the NoC <NUM>. The endpoint circuits <NUM> are master circuits, which are coupled to NMUs <NUM> of the NoC <NUM>. The endpoint circuits <NUM> are slave circuits coupled to the NSUs <NUM> of the NoC <NUM>. Each endpoint circuit <NUM> and <NUM> can be a circuit in the processing system <NUM>, a circuit in a programmable logic region <NUM>, or a circuit in another subsystem (e.g., hardened circuits <NUM>). Each endpoint circuit in the programmable logic region <NUM> can be a dedicated circuit (e.g., a hardened circuit) or a circuit configured in programmable logic.

The network <NUM> includes a plurality of physical channels <NUM>. The physical channels <NUM> are implemented by programming the NoC <NUM>. Each physical channel <NUM> includes one or more NoC packet switches <NUM> and associated routing <NUM>. An NMU <NUM> connects with an NSU <NUM> through at least one physical channel <NUM>. A physical channel <NUM> can also have one or more virtual channels <NUM>.

Connections through the network <NUM> use a master-slave arrangement. In an example, the most basic connection over the network <NUM> includes a single master connected to a single slave. However, in other examples, more complex structures can be implemented.

<FIG> is a block diagram depicting the NoC <NUM> according to another example. In the example, the NoC <NUM> includes vertical portions <NUM> (VNoC) and horizontal portion <NUM> (HNoC). Each VNoC <NUM> is disposed between PL regions <NUM>. The HNoC <NUM> is disposed between the PL regions <NUM> and the IO regions <NUM>. The hardened circuits <NUM> include memory interfaces <NUM>. The PS <NUM> is coupled to the HNoC <NUM>.

In the example, the PS <NUM> includes a plurality of NMUs <NUM> coupled to the HNoC <NUM>. The VNoC <NUM> includes both NMUs <NUM> and NSUs <NUM>, which are disposed in the PL regions <NUM>. The memory interfaces <NUM> include NSUs <NUM> coupled to the HNoC <NUM>. Both the HNoC <NUM> and the VNoC <NUM> include NPSs <NUM> connected by routing <NUM>. In the VNoC <NUM>, the routing <NUM> extends vertically. In the HNoC <NUM>, the routing extends horizontally. In each VNoC <NUM>, each NMU <NUM> is coupled to an NPS <NUM>. Likewise, each NSU <NUM> is coupled to an NPS <NUM>. NPSs <NUM> are coupled to each other to form a matrix of switches. Some NPSs <NUM> in each VNoC <NUM> are coupled to other NPSs <NUM> in the HNoC <NUM>.

Although only a single HNoC <NUM> is shown, in other examples, the NoC <NUM> can include more than one HNoC <NUM>. In addition, while two VNoCs <NUM> are shown, the NoC <NUM> can include more than two VNoCs <NUM>. Although memory interfaces <NUM> are shown by way of example, it is to be understood that other hardened circuits can be used in place of, or in addition to, the memory interfaces <NUM>.

<FIG> is a flow diagram depicting a method <NUM> of programming the NoC <NUM> according to an example. At step <NUM>, a processor in the PS <NUM> receives NoC programming data at boot time. In an example, the processor is a platform management controller (PMC). At step <NUM>, the processor in the PS <NUM> (e.g., the PMC) loads the NoC programming data to the registers <NUM> through the NPI <NUM> to create physical channels <NUM>. In an example, the programming data can also include information for configuring routing tables in the NPSs <NUM>. At step <NUM>, the processor in the PS (e.g., the PMC) boots the SoC <NUM>. In this manner, the NoC <NUM> includes at least configuration information for the physical channels <NUM> between NMUs <NUM> and NSUs <NUM>. Remaining configuration information for the NoC <NUM> can be received during runtime, as described further below. In another example, all or a portion of the configuration information described below as being received during runtime can be received at boot time.

<FIG> is a flow diagram depicting a method <NUM> of programming the NoC <NUM> according to an example. At step <NUM>, a processor in the PS <NUM> (e.g., the PMC) receives NoC programming data during runtime. At step <NUM>, the processor in the PS <NUM> (e.g., the PMC) loads the programming data to NoC registers <NUM> through the NPI <NUM>. In an example, at step <NUM>, the processor in the PS <NUM> configures routing tables in the NPSs <NUM>. At step <NUM>, the processor in the PS <NUM> configures QoS paths over the physical channels <NUM>. At step <NUM>, the processor in the PS <NUM> configures address space mappings. At step <NUM>, the processor in the PS <NUM> configures ingress/egress interface protocol, width, and frequency. The QoS paths, address space mappings, routing tables, and ingress/egress configuration are discussed further below.

<FIG> is a block diagram depicting a data path <NUM> through the NoC <NUM> between endpoint circuits according to an example. The data path <NUM> includes an endpoint circuit <NUM>, an AXI master circuit <NUM>, an NMU <NUM>, NPSs <NUM>, an NSU <NUM>, an AXI slave circuit <NUM>, and an endpoint circuit <NUM>. The endpoint circuit <NUM> is coupled to the AXI master circuit <NUM>. The AXI master circuit <NUM> is coupled to the NMU <NUM>. In another example, the AXI master circuit <NUM> is part of the NMU <NUM>. The NMU <NUM> is coupled to an NPS <NUM>. The NPSs <NUM> are coupled to each other to form a chain of NPSs <NUM> (e.g., a chain of five NPSs <NUM> in the present example). In general, there is at least one NPS <NUM> between the NMU <NUM> and the NSU <NUM>. The NSU <NUM> is coupled to one of the NPSs <NUM>. The AXI slave circuit <NUM> is coupled to the NSU <NUM>. In another example, the AXI slave circuit <NUM> is part of the NSU <NUM>. The endpoint circuit <NUM> is coupled to the AXI slave circuit <NUM>.

The endpoint circuits <NUM> and <NUM> can each be a hardened circuit or a circuit configured in programmable logic. The endpoint circuit <NUM> functions as a master circuit and sends read/write requests to the NMU <NUM>. In the example, the endpoint circuits <NUM> and <NUM> communicate with the NoC <NUM> using an Advanced Extensible Interface (AXI) protocol. While AXI is described in the example, it is to be understood that the NoC <NUM> may be configured to receive communications from endpoint circuits using other types of protocols known in the art. For purposes of clarity by example, the NoC <NUM> is described as supporting the AXI protocol herein. The NMU <NUM> relays the request through the set of NPSs <NUM> to reach the destination NSU <NUM>. The NSU <NUM> passes the request to the attached AXI slave circuit <NUM> for processing and distribution of data to the endpoint circuit <NUM>. The AXI slave circuit <NUM> can send read/write responses back to the NSU <NUM>. The NSU <NUM> can forward the responses to the NMU <NUM> through the set of NPSs <NUM>. The NMU <NUM> communicates the responses to the AXI master circuit <NUM>, which distributes the data to the endpoint circuit <NUM>.

<FIG> is a flow diagram depicting a method <NUM> of processing read/write requests and responses according to an example. The method <NUM> begins at step <NUM>, where the endpoint circuit <NUM> sends a request (e.g., a read request or a write request) to the NMU <NUM> through the AXI master <NUM>. At step <NUM>, the NMU <NUM> processes the response. In an example, the NMU <NUM> performs asynchronous crossing and rate-matching between the clock domain of the endpoint circuit <NUM> and the NoC <NUM>. The NMU <NUM> determines a destination address of the NSU <NUM> based on the request. The NMU <NUM> can perform address remapping in case virtualization is employed. The NMU <NUM> also performs AXI conversion of the request. The NMU <NUM> further packetizes the request into a stream of packets.

At step <NUM>, the NMU <NUM> sends the packets for the request to the NPSs <NUM>. Each NPS <NUM> performs a table lookup for a target output port based on the destination address and routing information. At step <NUM>, the NSU <NUM> processes the packets of the request. In an example, the NSU <NUM> de-packetizes the request, performs AXI conversion, and performs asynchronous crossing and rate-matching from the NoC clock domain to the clock domain of the endpoint circuit <NUM>. At step <NUM>, the NSU <NUM> sends the request to the endpoint circuit <NUM> through the AXI slave circuit <NUM>. The NSU <NUM> can also receive a response from the endpoint circuit <NUM> through the AXI slave circuit <NUM>.

At step <NUM>, the NSU <NUM> processes the response. In an example, the NSU <NUM> performs asynchronous cross and rate-matching from the clock domain of the endpoint circuit <NUM> and the clock domain of the NoC <NUM>. The NSU <NUM> also packetizes the response into a stream of packets. At step <NUM>, the NSU <NUM> sends the packets through the NPSs <NUM>. Each NPS <NUM> performs a table lookup for a target output port based on the destination address and routing information. At step <NUM>, the NMU <NUM> processes the packets. In an example, the NMU <NUM> de-packetizes the response, performs AXI conversion, and performs asynchronous crossing and rate-matching from the NoC clock domain to the clock domain of the endpoint circuit <NUM>. At step <NUM>, the NMU <NUM> sends the response to the endpoint circuit <NUM> through the AXI master circuit <NUM>.

<FIG> is a block diagram depicting an NMU <NUM> according to an example. The NMU <NUM> includes an AXI master interface <NUM>, packetizing circuitry <NUM>, an address map <NUM>, de-packetizing circuitry <NUM>, QoS circuitry <NUM>, VC mapping circuitry <NUM>, and clock management circuitry <NUM>. The AXI master interface <NUM> provides an AXI interface to the NMU <NUM> for an endpoint circuit. In other examples, a different protocol can be used and thus the NMU <NUM> can have a different master interface that complies with a selected protocol. The NMU <NUM> routes inbound traffic to the packetizing circuitry <NUM>, which generates packets from the inbound data. The packetizing circuitry <NUM> determines a destination ID from the address map <NUM>, which is used to route the packets. The QoS circuitry <NUM> can provide ingress rate control to control the injection rate of packets into the NoC <NUM>. The VC mapping circuitry <NUM> manages QoS virtual channels on each physical channel. The NMU <NUM> can be configured to select which virtual channel the packets are mapped to. The clock management circuitry <NUM> performs rate matching and asynchronous data crossing to provide an interface between the AXI clock domain and the NoC clock domain. The de-packetizing circuitry <NUM> receives return packets from the NoC <NUM> and is configured to de-packetize the packets for output by the AXI master interface <NUM>.

<FIG> is a block diagram depicting an NSU <NUM> according to an example. The NSU <NUM> includes an AXI slave interface <NUM>, clock management circuitry <NUM>, packetizing circuitry <NUM>, de-packetizing circuitry <NUM>, and QoS circuitry <NUM>. The AXI slave interface <NUM> provides an AXI interface to the NSU <NUM> for an endpoint circuit. In other examples, a different protocol can be used and thus the NSU <NUM> can have a different slave interface that complies with a selected protocol. The NSU <NUM> routes inbound traffic from the NoC <NUM> to the de-packetizing circuitry <NUM>, which generates de-packetized data. The clock management circuitry <NUM> performs rate matching and asynchronous data crossing to provide an interface between the AXI clock domain and the NoC clock domain. The packetizing circuitry <NUM> receives return data from the slave interface <NUM> and is configured to packetize the return data for transmission through the NoC <NUM>. The QoS circuitry <NUM> can provide ingress rate control to control the injection rate of packets into the NoC <NUM>.

<FIG> is a cross-section of a multi-chip module (MCM) <NUM> according to an example. The MCM <NUM> includes an IC die <NUM>, an IC die <NUM>, and a substrate <NUM>. The IC die <NUM> and the IC die <NUM> are mechanically and electrically coupled to the substrate <NUM>. The IC die <NUM> comprises an SoC <NUM> described above. The IC die <NUM> is mechanically and electrically coupled to the substrate <NUM> through external contacts <NUM>. The IC die <NUM> comprises another SoC <NUM> and is mechanically and electrically coupled to the substrate <NUM> through the external contacts <NUM>. The substrate <NUM> includes external contacts <NUM>. The substrate <NUM> can be a package substrate, an interposer, or the like.

In the example, the IC die <NUM> includes an NPS <NUM>. The NPS <NUM> is coupled to the IC die <NUM> through a conductor <NUM> of the substrate <NUM>. The IC die <NUM> includes an NPS <NUM>. The NPS <NUM> is coupled to the conductor <NUM> of the substrate <NUM>. In general, any number of switches can be coupled in this way through conductors on the substrate <NUM>. Thus, the NoC in the IC die <NUM> is coupled to the NoC in the IC die <NUM>, thereby forming a large NoC that spans both IC dies <NUM> and <NUM>. Although the conductor <NUM> of the substrate <NUM> is shown on a single layer, the substrate <NUM> can include any number of conductive layers having conductors coupled to NoC switches on the dies <NUM> and <NUM>.

<FIG> is a schematic diagram of an extended NoC <NUM> according to an example. The extended NoC <NUM> includes one or more VNOCs <NUM> (e.g., three are shown) that extend across a boundary <NUM> between IC dies. Some NPSs 206A of the NPSs <NUM> in the VNOC <NUM> are connected using conductors <NUM> on the substrate <NUM>. In the example, the extended NoC <NUM> includes two horizontal channels at each die edge. However, the extended NoC <NUM> can include any number of horizontal channels at the die edge. Further, each VNOC <NUM> is shown has having two vertical channels, but can include any number of vertical channels that span the boundary <NUM> between IC dies.

<FIG> is a block diagram depicting communication between NPSs 206A on difference IC dies according to an example. Each NPS 206A includes an NPS <NUM> and a FIFO <NUM>. Each NPS <NUM> is coupled to a FIFO <NUM> in the opposing NPS 206A. Each NPS <NUM> includes a clock path and a data path to the FIFO <NUM> in the opposing NPS 206A. In the example, each NPS 206A operates in a separate clock domain (e.g., clk1 and clk2). The clock domains do not have to be phased aligned to each other (e.g., the clock domains are phase independent). Each NPS <NUM> forwards the clock of its respective clock domain to the FIFO <NUM>. The FIFOs <NUM> realign the data to the clock domain of the respective NPS 206A.

<FIG> is a block diagram depicting a programmable IC <NUM> according to an example in which the NoC <NUM> described herein can be used. The programmable IC <NUM> includes programmable logic <NUM>, configuration logic <NUM>, and configuration memory <NUM>. The programmable IC <NUM> can be coupled to external circuits, such as nonvolatile memory <NUM>, DRAM <NUM>, and other circuits <NUM>. The programmable logic <NUM> includes logic cells <NUM>, support circuits <NUM>, and programmable interconnect <NUM>. The logic cells <NUM> include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits <NUM> include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits <NUM> can be interconnected using the programmable interconnect <NUM>. Information for programming the logic cells <NUM>, for setting parameters of the support circuits <NUM>, and for programming the programmable interconnect <NUM> is stored in the configuration memory <NUM> by the configuration logic <NUM>. The configuration logic <NUM> can obtain the configuration data from the nonvolatile memory <NUM> or any other source (e.g., the DRAM <NUM> or from the other circuits <NUM>). In some examples, the programmable IC <NUM> includes a processing system <NUM>. The processing system <NUM> can include microprocessor(s), memory, support circuits, IO circuits, and the like.

<FIG> is a block diagram depicting a System-on-Chip (SoC) implementation of the programmable IC <NUM> according to an example. In the example, the programmable IC <NUM> includes the processing system <NUM> and the programmable logic <NUM>. The processing system <NUM> includes various processing units, such as a real-time processing unit (RPU) <NUM>, an application processing unit (APU) <NUM>, a graphics processing unit (GPU) <NUM>, a configuration and security unit (CSU) <NUM>, a platform management unit (PMU) <NUM>, and the like. The processing system <NUM> also includes various support circuits, such as on-chip memory (OCM) <NUM>, transceivers <NUM>, peripherals <NUM>, interconnect <NUM>, DMA circuit <NUM>, memory controller <NUM>, peripherals <NUM>, and multiplexed IO (MIO) circuit <NUM>. The processing units and the support circuits are interconnected by the interconnect <NUM>. The PL <NUM> is also coupled to the interconnect <NUM>. The transceivers <NUM> are coupled to external pins <NUM> or connected to the external pins <NUM> through a protocol block (not shown) (e.g., PCle, Ethernet, etc.). The PL <NUM> is coupled to external pins <NUM>. The memory controller <NUM> is coupled to external pins <NUM>. The MIO <NUM> is coupled to external pins <NUM>. The PS <NUM> is generally coupled to external pins <NUM>. The APU <NUM> can include a CPU <NUM>, memory <NUM>, and support circuits <NUM>. The APU <NUM> can include other circuitry, including L1 and L2 caches and the like. The RPU <NUM> can include additional circuitry, such as L1 caches and the like. The interconnect <NUM> can include cache-coherent interconnect or the like.

Referring to the PS <NUM>, each of the processing units includes one or more central processing units (CPUs) and associated circuits, such as memories, interrupt controllers, direct memory access (DMA) controllers, memory management units (MMUs), floating point units (FPUs), and the like. The interconnect <NUM> includes various switches, busses, communication links, and the like configured to interconnect the processing units, as well as interconnect the other components in the PS <NUM> to the processing units.

The OCM <NUM> includes one or more RAM modules, which can be distributed throughout the PS <NUM>. For example, the OCM <NUM> can include battery backed RAM (BBRAM), tightly coupled memory (TCM), and the like. The memory controller <NUM> can include a DRAM interface for accessing external DRAM. The peripherals <NUM>, <NUM> can include one or more components that provide an interface to the PS <NUM>. For example, the peripherals <NUM> can include a graphics processing unit (GPU), a display interface (e.g., DisplayPort, high-definition multimedia interface (HDMI) port, etc.), universal serial bus (USB) ports, Ethernet ports, universal asynchronous transceiver (UART) ports, serial peripheral interface (SPI) ports, general purpose IO (GPIO) ports, serial advanced technology attachment (SATA) ports, PCle ports, and the like. The peripherals <NUM> can be coupled to the MIO <NUM>. The peripherals <NUM> can be coupled to the transceivers <NUM>. The transceivers <NUM> can include serializer/deserializer (SERDES) circuits, MGTs, and the like.

<FIG> illustrates a field programmable gate array (FPGA) implementation of the programmable IC <NUM> that includes a large number of different programmable tiles including transceivers <NUM>, configurable logic blocks ("CLBs") <NUM>, random access memory blocks ("BRAMs") <NUM>, input/output blocks ("IOBs") <NUM>, configuration and clocking logic ("CONFIG/CLOCKS") <NUM>, digital signal processing blocks ("DSPs") <NUM>, specialized input/output blocks ("I/O") <NUM> (e.g., configuration ports and clock ports), and other programmable logic <NUM> such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. The FPGA can also include PCle interfaces <NUM>, analog-to-digital converters (ADC) <NUM>, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element ("INT") <NUM> having connections to input and output terminals <NUM> of a programmable logic element within the same tile, as shown by examples included at the top of <FIG>. Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments <NUM>) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments <NUM>) can span one or more logic blocks. The programmable interconnect elements <NUM> taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.

In an example implementation, a CLB <NUM> can include a configurable logic element ("CLE") <NUM> that can be programmed to implement user logic plus a single programmable interconnect element ("INT") <NUM>. A BRAM <NUM> can include a BRAM logic element ("BRL") <NUM> in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile <NUM> can include a DSP logic element ("DSPL") <NUM> in addition to an appropriate number of programmable interconnect elements. An IOB <NUM> can include, for example, two instances of an input/output logic element ("IOL") <NUM> in addition to one instance of the programmable interconnect element <NUM>. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element <NUM> typically are not confined to the area of the input/output logic element <NUM>.

In the pictured example, a horizontal area near the center of the die (shown in <FIG>) is used for configuration, clock, and other control logic. Vertical columns <NUM> extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated in <FIG> include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

Note that <FIG> is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of <FIG> are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

Claim 1:
A programmable integrated circuit, IC (<NUM>), comprising:
a processor;
a plurality of endpoint circuits;
a network-on-chip, NoC (<NUM>) having NoC master units, NMUs (<NUM>), NoC slave units, NSUs (<NUM>), NoC programmable switches, NPSs (<NUM>), a plurality of registers (<NUM>), and a NoC programming interface, NPI (<NUM>);
wherein the processor is coupled to the NPI (<NUM>) and is configured to program the NPSs (<NUM>) by loading first programming data to the registers (<NUM>) through the NPI (<NUM>) for providing physical channels between NMUs (<NUM>) to the NSUs (<NUM>) and providing data paths between the plurality of endpoint circuits;
wherein the processor is further configured to receive second programming data during runtime and loading the second programming data to the registers (<NUM>) in the NoC (<NUM>) through the NPI (<NUM>), wherein the second programming data configures routing tables in NoC programmable switches, NPSs (<NUM>) in the NoC (<NUM>).