Patent Description:
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a substrate like a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.

Bonded (or stacked) wafers are frequently used in the semiconductor industry. One or more ultrathin wafers bonded to a carrier wafer is an example of a bonded wafer, though other semiconductor wafer designs also can be bonded wafers. For example, a bonded wafer can include a top wafer (e.g., a device wafer) bonded to a carrier wafer. These bonded wafers can be used for both memory and logic applications. Three-dimensional integrated circuits (3D IC) can be produced using bonded wafers.

Bonded wafers can have complex edge profiles. The various layers of a bonded wafer can have different heights and diameters. These dimensions can be affected by the size of the various wafers prior to stacking or by processing steps.

Bonded wafers with fabrication errors can cause problems during manufacturing. For example, centricity of the bonded wafer affects the CMP process or increases handling risks. During CMP, centricity affects placement of the polishing pad with respect to the center of the bonded wafer and subsequent planarization. During wafer handling, the balance of a bonded wafer or clearance within manufacturing equipment can be affected by centricity of the bonded wafer.

Improper centricity can even ruin a bonded wafer or damage manufacturing equipment. If the bonded wafer is undercut, improperly bonded together, or contains too much glue, then the bonded wafer can break within the CMP tool, contaminating or damaging the CMP tool. Such contamination or damage leads to unwanted downtime or can even stop production within a semiconductor fab.

Furthermore, a CMP process on a bonded wafer with improper centricity can result in undesired edge profiles on the bonded wafer. For example, too much or not enough material may be removed during a CMP process or the CMP process may result in undercuts, overhangs, or whiskers. These undesired edge profiles can affect device yield or can impact later manufacturing steps.

Therefore, what is needed are improved techniques for bonded wafer metrology and associated systems.

<CIT> discloses a rotational misalignment measuring device of bonded substrate, rotational misalignment measuring method of bonded substrate, and method of manufacturing bonded substrate.

A metrology system as recited in claim <NUM> is provided in a first embodiment.

In a second embodiment, a method as recited in claim <NUM> is provided.

In a third embodiment, a non-transitory computer readable medium storing a program as recited in claim <NUM> is provided.

Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined only by reference to the appended claims.

As part of 3D-integration process, semiconductor wafers can be stacked and bonded together. At least one top wafer, which may be a device wafer or some other type of wafer, is placed on a carrier wafer. The top wafer and the carrier wafer can be connected by an adhesive material. Several process parameters such as an amount of adhesive, force, temperature, wafer shape, and placement accuracy may cause a wafer displacement between the top wafer and the carrier wafer, such as the carrier wafer and the top wafer not being centered relative to each other. Methods and systems to measure wafer-to-wafer displacement of two or more wafers (e.g., top wafer and carrier wafer) in a bonded wafer are disclosed. For example, displacement in the X and Y dimensions can be determined. The X, Y, and Z coordinates of the wafer edge can be used to determine the center of each of the bonded wafers.

Wafer edge profile images can be acquired, such as using a system disclosed in <CIT>. <FIG> is an exemplary wafer edge profile image of a circumferential edge of a bonded wafer having a carrier wafer <NUM> and a top wafer <NUM>. <FIG> is an example of a shadowgram image. From the edge contour and the wafer rotation angle, the X, Y, and Z coordinates of the wafer edge are extracted with Z being the thickness of the wafers in the bonded wafer. From these coordinates, the center of each of the bonded wafers can be determined.

In an embodiment, image processing techniques are used to isolate vertically-connected pixels along the contour of the edge profiler image. Based on user-defined zones and slope tolerance parameters, vertically connected pixels (e.g., vertical line segments) are grouped into two regions. One region is associated with the top wafer and the other region is associated with the carrier wafer. Average X distances of these line segments can then be calculated from the edge of the image frame or some other reference point for the two groups. Absolute offset is calculated as difference between these average values. This is repeated for all wafer edge profile images acquired around the wafer (e.g., every <NUM> degrees around the circumference of the bonded wafer) to generate an offset curve. A model is then applied to calculate the X and Y offsets between the top wafer and the carrier wafer from this curve.

An example is illustrated in <FIG>. <FIG> is a contour extracted from the wafer edge profile image of <FIG>. The wafer edge profile image of <FIG> may be sharpened or otherwise cleaned up prior to extraction, such as to remove scale bars. Scale bars may be removed by, for example, cropping the image. Other pre-processing, such as fringe removal, noise filtering, or color depth reduction down to two bit (black and white), also may be performed.

The contour of the edge profile in <FIG> may be extracted, such as by using a high pass filter. In an instance, a canny edge extraction method is used during which some smoothing may be performed to avoid noisy edges in the images. Other smoothing may be performed during edge extraction depending on the edge extraction algorithm.

<FIG> illustrates vertical line segments of the contour shown in <FIG> after grouping. The line segments can be grouped into regions associated with the top wafer and the carrier wafer. The vertical line segments represent or approximate an extent of the wafer and are circled in <FIG> with a dotted line. Xtop is an average X distance of the top line segments (e.g., the top wafer) and Xbot is an average X distance of the bottom line segments (e.g., the carrier wafer). Xtop and Xbot can be, for example, an average distance from the edge of an image frame or other reference. For example, this may be an average distance with respect to left hand side of image frame. The actual average or reference point for the two averages may not matter because a difference between two averages is used.

A Hough Transform based technique, local slope calculation, or other techniques known in the art may be used to determine vertical line segments on the edge contour. In an instance, the local slope calculation is based on a few pixels and only those pixels are selected whose local slope indicates a vertical edge.

An offset between the two vertical line segments is then calculated. For example, an average X distance from the edge of image frame for lines in each group is calculated based on <FIG>. A total offset as difference between these two average values is also calculated based on <FIG>.

The process in <FIG> and <FIG> can be repeated for all wafer edge profile images (e.g., every <NUM> degrees around the circumference of the bonded wafer) and an offset curve is generated. An exemplary offset curve is illustrated in <FIG> and <FIG> also illustrates the data being modelled from a sinusoidal fit. A sinusoidal model can be applied to calculate X and Y offsets from the total offset curve. <FIG> is a model description, though other models may be possible. When there is offset in both X and Y in <FIG>, a = A cos (θ-Φ) + C. A, Φ, and C are the unknowns. In <FIG>, θ is measured with respect to horizontal axis, Φ is an angle between a line joining two centers and a horizontal axis, C1 is the center of the top wafer, C2 is the center of the carrier wafer, A is the distance between the centers of the two wafers, X is the X offset between the two wafers, and Y is the Y offset between the two wafers. From a modeled fit, the top wafer offsets with respect to the carrier wafer is calculated as follows. <MAT> <MAT>.

C can be ignored in some simple cases. The pixel size may be, for example, <NUM>, though other sizes are possible.

Input parameters for this embodiment that isolates vertically-connected pixels can include slope tolerance and zone. For slope tolerance, a user can set how much tolerance is allowed from a perfect vertical line. For zone, a user can define top and bottom wafer zones for accurate computation during grouping.

Since the offset between two wafers in a bonded wafer is calculated from a single image, any wafer-to-stage placement error does not impact computations involved in isolating vertically-connected pixels. Thus, any wafer placement on a stage may be acceptable. This measurement also is free from any shift in the image coordinate space due to calibration drifts because the difference between two averages is calculated to have the offset curve. Thus, the difference will not be impacted even if the individual averages change because of the drift.

In an instance, the embodiment of <FIG> may include a step to remove messy edges or artifacts. This may occur prior to finding the vertical line segments. In another instance, a wafer edge profile image with messy edges or artifacts can be skipped and other wafer edge profile images of a wafer can be relied upon instead.

In another embodiment, shown in <FIG>, a model-based approach is used. In a pre-processing step, the contour coordinates of the edge profile images are extracted. The coordinates for wafer bevel and apex are then used to fit an elliptical model.

<FIG> includes an exemplary wafer edge profile image of a circumferential edge of a wafer on the left and extracted edge contour coordinates from the wafer edge profile image on the right. Edge coordinates can be extracted from the wafer edge profile image using, for example, a high pass filter. Stage effects can be corrected. Coordinates of points at the bevel and apex (circled with the dotted line in <FIG>) can be saved or otherwise noted. This process can be repeated for all wafer edge profile images for a wafer (e.g., every <NUM> degrees around the circumference of the bonded wafer). At least three images may be needed to provide the relative center offset, but more images can proved higher accuracy in terms of reduce roughness at the edge or the circularity error. For example, <NUM> images may be taken.

Edge data can then be fitted to a model. <FIG> illustrates an algorithm analyzing the wafer edge profile image of <FIG> slice by slice. The coordinates are fitted to an elliptical model, such as that illustrated in <FIG>, on a slice-by-slice basis. In <FIG>, CoR is the center of rotation and CoW is the center of the wafer. This results in a center of wafer per slice, as shown in <FIG>. A typical step size may be <NUM> microns. For each slice, there may be <NUM> edge position points, though other values or ranges are possible. Each point comes from one image. Its coordinate can be the orientation (θ) and radius, shown as solid line in <FIG>. Then these points are fitted into a model, as seen in <FIG>. The parameters of the model include CoR and CoW currently set as the reference. The wafer circularity is modeled as an ellipse with its long axis R+δ, and short axis R-δ. Given a hypotheses model parameters, the position of images is calculated, shown as dots in <FIG>. A non-linear regression algorithm can be used to adjust the hypotheses model parameters so that the model prediction (dots in <FIG>) is best matched with the measured value (solid line in <FIG>). The model parameters that give best match are reported as the measurement results, in terms of CoR, wafer radius, wafer ellipticity as shown in <FIG>.

For example, using least-squares fitting, the center positions of the wafers are calculated from the results of the slices. The calculated center positions are sorted into N sets where N is the number of wafers in a bonded wafer (i.e., N><NUM>). The sorting may be done using knowledge of wafer thicknesses and/or filtering. Filtering can include deviation from median and/or knowledge about the height location. The center positions of each wafer can be calculated for each set corresponding to a wafer by averaging, using a median, or with other techniques.

<FIG> illustrate wafer radius and circularity results. The calculated wafer centers with respect to the center of rotation in <FIG> and <FIG> show the wafer radius at different slices and the ellipticity.

The embodiment of <FIG> may use an elliptical model. In an instance, the ellipse equation is Ax<NUM> + Bxy + Cy<NUM> + Dx + Ey + F = <NUM>. This may provide improved results because the wafers may not be perfectly circular. However, other models (e.g., a circular model) may still provide acceptable performance.

While the embodiments of <FIG> and <FIG> can be used separately or in the alternative, both the embodiment of <FIG> and the embodiment of <FIG> are used together in the present invention. The embodiment of <FIG> is performed first. Then the embodiment of <FIG> may be performed to verify results. The embodiment of <FIG> may provide more accurate results because its analysis includes more non-ideal factors in the model, may provide more information because detailed edge information is preserved in the analysis process, and may be faster.

In another example, the embodiment of <FIG> may be a backup if the embodiment of <FIG> is unable to provide acceptable or clear results.

In the embodiments disclosed herein, the wafer edge data/coordinates are acquired using wafer edge profile images. A profiler, laser triangulation, or other techniques could be used to generate the inputs instead.

<FIG> is a flowchart of an embodiment of a bonded wafer metrology method. At <NUM>, wafer edge profile images are analyzed at locations around a bonded wafer, which may have a top wafer and a carrier wafer. At <NUM>, an offset curved is generated based on the wafer edge profile images. At <NUM>, displacement of the top wafer to the carrier wafer is determined based on the offset curve. The wafer edge profile images may be generated at multiple locations around the wafer prior to the analysis <NUM>. The wafer edge profile images may be shadowgram images.

While two wafers (e.g., a carrier wafer and a top wafer) are illustrated, more than two wafers may be bonded together. For example, three wafers may be bonded to a carrier wafer. The offset between adjacent wafer, between pairs of wafers, or for the overall bonded wafer can be calculated.

In an instance of the analyzing <NUM>, a first vertical line segment in each of the edge profile images for the top wafer is determined and a second vertical line segment in each of the edge profile images for the carrier wafer is determined. The lateral position of the first vertical line segment and the second vertical line segment is compared for each of the edge profile images. Determining the first vertical line segment and the determining the second vertical line segment can include isolating vertically connected pixels along a contour of the wafer edge profile images using a Hough Transform. A sinusoidal model may be used to determine the displacement.

In another instance of the analyzing <NUM>, edge coordinates are extracted from each of the edge profile images. Coordinates of points at a bevel and an apex in each of the edge profile images are determined. The coordinates are fitted to an elliptical model. A center position of the top wafer and the carrier wafer is calculated. Stage effects can be corrected after the extracting.

Additional wafer properties can be obtained from the image analysis, such as wafer circularity or other irregularities such as the shape of the individual wafer edges. For example, whether the wafer edge is angled and the direction of the angle can be determined. Thus, the systems and methods disclosed herein can be used for concurrent wafer edge inspection and edge profiling.

<FIG> are a top view and corresponding cross-sectional side view along A-A of a block diagram of a system <NUM> in accordance with an embodiment of the present disclosure. <FIG> is a perspective view of a system <NUM> corresponding to the embodiment of <FIG>. System <NUM> is configured to perform metrology of a bonded wafer by acquiring images that are shadowgrams. A shadowgram applies a shadowgraph technique and visualizes or images a shadow of the bonded wafer <NUM>, such as a circumferential edge of the bonded wafer <NUM>. A stage <NUM> can be configured to rotate a bonded wafer <NUM>, though the system <NUM> also can rotate with respect to the bonded wafer <NUM>. Such rotation can be stepped or continuous. The bonded wafer <NUM> also may not rotate during imaging and components of the system <NUM> may be fixed.

The exemplary bonded wafer <NUM> is shown with a carrier wafer <NUM> and a top wafer <NUM>. The carrier wafer <NUM> and top wafer <NUM> may have different diameters, such as those illustrated in <FIG>. For example, the carrier wafer <NUM> can be a carrier wafer and the top wafer <NUM> can be a device wafer. Alternatively, the carrier wafer <NUM> and top wafer <NUM> can both be device wafers or more than the carrier wafer <NUM> and top wafer <NUM> can form the bonded wafer <NUM>.

A light source <NUM> is configured to direct collimated light <NUM> at an edge of the bonded wafer <NUM>. In some embodiments, the collimated light <NUM> is directed tangentially, with respect to the bonded wafer <NUM>, so as to create a shadow of the edge profile. Thus, the bonded wafer <NUM> blocks some of the collimated light <NUM>. The collimated light <NUM> is illustrated as approximately circular, but can be other shapes. In an exemplary embodiment, the light source <NUM> utilizes a light-emitting diode (LED). Other suitable light sources <NUM>, such as a lamp that produces collimated light, laser, supercontinuum laser, laser-driven phosphor, or laser-driven lamp, will be apparent in light of the present disclosure. Combinations of light sources <NUM>, such as a laser and an LED, may be utilized. The light source <NUM> can include both single band and broadband light sources in a single system or multiple systems. The collimated light <NUM> may be parallel to a plane of the bonded wafer <NUM>. For example, the collimated light <NUM> may be parallel to the plane of the carrier wafer <NUM> on which the top wafer <NUM> is disposed. Diffraction suppression techniques may be used to remove diffraction-related artifacts that may adversely affect measurements. Approximately a few millimeters of the bonded wafer <NUM> are seen in a profile using the collimated light <NUM>, though other dimensions are possible.

A detector <NUM> located apart from the light source <NUM> receives at least some of the collimated light <NUM>. The detector <NUM> is located such that when a bonded wafer <NUM> is being imaged, at least a portion of the shadow (i.e., the light producing the shadow) is received by the detector <NUM>. The detector <NUM> can be, for example, a charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS) camera. In this way, an image of the wafer edge silhouette is formed (i.e., a wafer edge profile image). The detector <NUM> can be configured to collect hundreds of wafer edge profile images of the bonded wafer <NUM> for high sampling. For example, between <NUM> and <NUM> wafer edge profile image of the bonded wafer <NUM> may be collected, though more images can be collected. In an example, <NUM> wafer edge profile images of a bonded wafer are collected. In another example, <NUM> wafer edge profile images of a bonded wafer are collected. In another example, <NUM> wafer edge profile images of a bonded wafer are collected.

The collimated light <NUM> may have a wavelength or wavelengths that produce a shadow. For example, visible light such as blue light or white light may be used. Other suitable collimated light <NUM> will be apparent in light of the present disclosure. For example, ultraviolet light can be used. The collimated light <NUM> may be polarized and may be pulsed or continuous.

While only a single light source <NUM> and detector <NUM> are illustrated in <FIG>, multiple light sources <NUM> and detectors <NUM> may be used. Multiple light sources <NUM> and detectors <NUM> may be placed at various locations around the perimeter of the bonded wafer <NUM> to collect images at different locations of the bonded wafer <NUM>. This may increase inspection throughput or increase the number of images produced while minimizing the impact to inspection throughput. If multiple light sources <NUM> and detectors <NUM> are placed at various locations around the perimeter of the bonded wafer <NUM>, then the bonded wafer <NUM> may not rotate with respect to the light source <NUM> or detector <NUM>.

A controller <NUM> is operatively connected to the detector <NUM>. The controller <NUM> is configured to analyze an image of the edge of the bonded wafer <NUM> and can control the acquisition of the images using the detector <NUM>. For example, the controller <NUM> can rotate the bonded wafer <NUM> with respect to the light source <NUM> or detector <NUM>. The controller <NUM> also can control the timing or locations of image acquisition on the bonded wafer <NUM>. The controller <NUM> may be configured to perform other functions or additional steps using the output of the detector <NUM>. For example, the controller <NUM> may be programmed to perform some or all of the steps of <FIG>. The controller <NUM> can include a processor <NUM> and a memory <NUM>.

The controller <NUM>, other system(s), or other subsystem(s) described herein may take various forms, including a personal computer system, workstation, image computer, mainframe computer system, workstation, network appliance, internet appliance, parallel processor, or other device. In general, the term "controller" may be broadly defined to encompass any device having one or more processors that executes instructions from a memory medium. The subsystem(s) or system(s) may also include any suitable processor known in the art, such as a parallel processor. In addition, the subsystem(s) or system(s) may include a platform with high speed processing and software, either as a standalone or a networked tool.

If the system includes more than one subsystem, then the different subsystems may be coupled to each other such that images, data, information, instructions, etc. can be sent between the subsystems. For example, one subsystem may be coupled to additional subsystem(s) by any suitable transmission media, which may include any suitable wired and/or wireless transmission media known in the art. Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).

In another embodiment, the controller <NUM> may be communicatively coupled to any of the various components or sub-systems of system <NUM> in any manner known in the art. Moreover, the controller <NUM> may be configured to receive and/or acquire data or information from other systems by a transmission medium that may include wireline and/or wireless portions. In this manner, the transmission medium may serve as a data link between the controller <NUM> and other subsystems of the system <NUM> or systems external to system <NUM>.

An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a controller for performing a computer-implemented method for bonded wafer metrology, such as for performing the techniques disclosed herein. In particular, as shown in <FIG>, the controller <NUM> can include a memory <NUM> or other electronic data storage medium with non-transitory computer-readable medium that includes program instructions executable on the controller <NUM>. The computer-implemented method may include any step(s) of any method(s) described herein, such as that disclosed with respect to <FIG>. The memory <NUM> or other electronic data storage medium may be a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid state memory, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.

The program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), SSE (Streaming SIMD Extension), or other technologies or methodologies, as desired.

In some embodiments, various steps, functions, and/or operations of system <NUM> and the methods disclosed herein are carried out by one or more of the following: electronic circuits, logic gates, multiplexers, programmable logic devices, application-specific integrated circuits (ASICs), analog or digital controls/switches, microcontrollers, or computing systems. Program instructions implementing methods such as those described herein may be transmitted over or stored on carrier medium. A carrier medium may include an electronic data storage medium, such as that of the memory <NUM>, or a transmission medium such as a wire, cable, or wireless transmission link. For instance, the various steps described throughout the present disclosure may be carried out by a single controller <NUM> (or computer system) or, alternatively, multiple controllers <NUM> (or multiple computer systems). Moreover, different sub-systems of the system <NUM> may include one or more computing or logic systems. Therefore, the above description should not be interpreted as a limitation on the present invention but merely an illustration.

As used throughout the present disclosure, a "wafer" may refer to a substrate formed of a semiconductor or non-semiconductor material. For example, a semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide, or indium phosphide. A wafer may include one or more layers. For example, such layers may include, but are not limited to, a resist, a dielectric material, a conductive material, or a semiconductive material. Many different types of such layers are known in the art, such as, but not limited to, isolation layers, implantation layers, and the like. The term "wafer" as used herein is intended to encompass a substrate on which any of such layers may be formed.

Each of the steps of the method may be performed as described herein. The methods also may include any other step(s) that can be performed by the controller and/or computer subsystem(s) or system(s) described herein. The steps can be performed by one or more computer systems, which may be configured according to any of the embodiments described herein. In addition, the methods described above may be performed by any of the system embodiments described herein.

Claim 1:
A metrology system (<NUM>) comprising:
a stage (<NUM>) configured to support a bonded wafer (<NUM>), wherein the bonded wafer has a top wafer (<NUM>) disposed on a carrier wafer (<NUM>);
an imaging system configured to generate wafer edge profile images of a circumferential edge of the bonded wafer, wherein the imaging system includes a light source (<NUM>) configured to generate collimated light (<NUM>) and a detector (<NUM>) configured to generate the wafer edge profile images; and
a controller (<NUM>) in electronic communication with the imaging system, wherein the controller is programmed to:
analyze the wafer edge profile images at a plurality of locations around the bonded wafer (<NUM>) in a first instance,
wherein during the first instance of the analyzing, the controller (<NUM>) is further configured to:
extract edge coordinates from each of the edge profile images;
determine coordinates of points at a bevel and an apex in each of the edge profile images;
fit the coordinates to an elliptical model on a slice-by-slice basis; and
calculate a center position of the top wafer (<NUM>) and the carrier wafer (<NUM>);
analyze the wafer edge profile images at the plurality of locations around the bonded wafer (<NUM>) in a second instance which is subsequent to the first instance,
wherein during the second instance of the analyzing, the controller (<NUM>) is further configured to:
determine a first vertical line segment in each of the edge profile images for the top wafer (<NUM>);
determine a second vertical line segment in each of the edge profile images for the carrier wafer (<NUM>); and
compare the lateral position of the first vertical line segment and the second vertical line segment for each of the edge profile images to determine a difference between the lateral positions of the first and second vertical line segments;
generate an offset curve based on the wafer edge profile images, wherein the offset curve is generated based on the difference between the lateral positions of the first and second vertical line segments acquired for each of the edge profile images at the plurality of locations around the bonded wafer;
determine a displacement of the top wafer (<NUM>) to the carrier wafer (<NUM>) based on the offset curve.