Patent Description:
In the related art, in order to reduce a processing load of an industrial controller, an industrial control system of a type that uses various units operated in cooperation with a controller together is known. In such a system, the controller and the units share the same memory, and the controller or the units may be operated to access the shared memory and read and write data. However, when the controller and the units can disorderly access the shared memory, "memory contention" will occur because each access occurs at the same timing, and as a result, reading/writing of data to be processed with priority may be delayed.

Here, in the related art, examples of technologies for avoiding occurrence of such memory contention are proposed in, for example, Patent Literatures <NUM> and <NUM>.

Patent Literature <NUM> discloses a memory access arbitration device including a first control unit configured to output a request signal to obtain use permission of the shared memory at a random timing, a second control unit configured to output a request signal to obtain use permission of the shared memory at each constant cycle, and an arbitration unit configured to arbitrate the request signal output from each of the first control unit and second control unit, wherein a determination unit configured to receive the output of the request signal from the second control unit and output an ack prohibition signal that prohibits the arbitration unit from outputting an ack signal to the first control unit to the arbitration unit is provided.

Patent Literature <NUM> discloses an arbitration system configured to arbitrate use requests of a plurality of devices with respect to a shared resource according to a prescribed priority ranking and selectively permit use of the shared resource, including a time counting part configured to count a time from a use request permission start of a specific device having a need to transfer data within a constant time in the plurality of devices that are arbitration objects to the next use request permission start and generate a timeout signal when it is detected that selection of the use request permission of the specific device is not within a predetermined time, and an arbitration unit configured to permit a use request of the specific device at each constant time by changing a priority ranking of the specific device to the highest or at least the second highest according to the timeout signal from the time counting part.

Attention is drawn to <CIT> relating to an I2C communication speed-up system for transmitting heterogeneous network data and a method for controlling the same capable of performing a write operation without time delays by transmitting an ACK signal in advance to reduce reduction of data transmission speed which is inevitably generated in a heterogeneous separated I2C bus structure. The I2C communication speed-up system for transmitting heterogeneous network data comprises: a first master device; a first slave device which is connected to the first master device through a first bus; and a second master device which is connected to the first slave device through a second bus and is connected to at least one second slave device through a third bus. When the first master device transmits a plurality of pieces of data to be transmitted to one target slave device among at least one second slave device, the first slave device transmits first ACK for first data to the first master device instead of the target slave device when the first data among the plurality of pieces of data is received in a first transmitting section from the first master device; and transmits the first data to the second master device through the second bus. When the first ACK is received, the first master device transmits second data which is next data of the first data to the first slave device in a second transmitting section which is a next transmitting section of the first transmitting section. This document discloses the preamble of claim <NUM>.

The present invention is set forth in the independent claim <NUM>.

In the technology of Patent Literature <NUM>, both of the first control unit and the second control unit need to access to the arbitration unit to arbitrate and receive the access to the memory. For this reason, for example, when the first control unit is used as a CPU of an industrial controller, since a processing load (request transmission, ACK reception, or the like) of the CPU for arbitration is increased, a control cycle of the CPU is increased. As a result, there is a problem that the CPU cannot execute processing in a constant cycle.

Even in the technology of Patent Literature <NUM>, the plurality of devices and the one CPU need to access the arbitration circuit to avoid memory contention. Accordingly, since the processing load (request transmission, ACK reception, or the like) of the CPU for arbitration is increased, the control cycle of the CPU becomes longer. As a result, there is a problem that the CPU cannot execute processing in a constant cycle.

In order to solve the above-mentioned problems, an objective of the present invention is to prevent occurrence of memory contention without executing arbitration processing in a computation unit of a control device to prevent the memory contention.

According to the aspect of the present invention, it is possible to minimize occurrence of memory contention without executing arbitration processing for preventing memory contention in a computation unit of a control device.

Hereinafter, an embodiment related to one aspect of the present invention (hereinafter, referred to as "the embodiment") will be described with reference to the accompanying drawings.

§<NUM> <FIG> and <FIG> description As shown in <FIG>, a unit <NUM> according to the embodiment is an information processing device connected to a PLC <NUM> in a control system <NUM> and operates in cooperation with the PLC <NUM>. A protocol control part <NUM> in the unit <NUM> shares a CPU <NUM> in the PLC <NUM> and a memory <NUM> in the PLC <NUM>, both of which communicate with the memory <NUM> via a serial bus <NUM>. That is, the CPU <NUM> and the protocol control part <NUM> share the memory <NUM>. A combination configured to prevent memory contention between the CPU <NUM> and the protocol control part <NUM> is incorporated in the control system <NUM>.

As shown in <FIG>, when a predetermined control cycle is started, the PLC <NUM> reads control data (first data) from the memory <NUM> to control a control object in the control system <NUM> and transmits the data to the control object. The protocol control part <NUM> of the unit <NUM> divides large capacity data into a plurality of pieces of smallest payload data, and transmits each piece of smallest payload data to the memory <NUM> via the serial bus <NUM> in the control cycle. When transmission of the control data and transmission of the large capacity data simultaneously occur in the serial bus <NUM>, so-called memory contention can occur between the CPU <NUM> and the protocol control part <NUM>.

The protocol control part <NUM> calculates a transmission time T2 of smallest payload data D6 transmitted to the memory <NUM> at a time t4 based on, for example, a time t5 when ACK with respect to the smallest payload data D6 is received. When it is determined that the calculated transmission time T2 exceeds a predetermined reference value set in the unit <NUM>, the protocol control part <NUM> assumes that memory contention occurs between the CPU <NUM> and the protocol control part <NUM>, and transmission of smallest payload data D8 transmitted subsequently to smallest payload data D7 upon transmission at an ACK reception point of time is on standby for a predetermined duration T3. Accordingly, since transmission of the large capacity data is on standby during the duration T3, even when the CPU <NUM> continues transfer of the control data in the duration T3, memory contention does not easily occur. As a result, in each control cycle, occurrence of memory contention between the CPU <NUM> and the protocol control part <NUM> can be minimized.

<FIG> is a block diagram showing a major part configuration of the control system <NUM> according to the embodiment. In the example shown, the control system <NUM> includes the programmable logic controller (PLC) <NUM> (a control device) and the unit <NUM>. The PLC <NUM> of <FIG> includes the central processing unit (CPU) <NUM> (a first communication part), the memory <NUM> (a first memory), a switching part <NUM>, a protocol control part <NUM>, and the serial bus <NUM>. The unit <NUM> in <FIG> includes an MPU <NUM>, a memory <NUM> (a second memory), a switching part <NUM>, a protocol control part <NUM>, and a transfer part <NUM>. The transfer part <NUM> in <FIG> includes a direct memory access controller (DMAC) <NUM> (a second communication part), a protocol control part <NUM>, and the protocol control part <NUM>. The protocol control part <NUM> includes a smallest payload data generating part <NUM> (a generating part, a transmission control part), a communication interface <NUM> (a transmission part, a reception part, an acquisition part), and an ACK monitoring part <NUM> (a computation part, a determination part).

The control system <NUM> is a system configured to control production facilities in which a plurality of control objects such as various instruments or facilities (not shown) are installed. The PLC <NUM> is a type of controller configured to control these control objects in the control system <NUM>. The PLC <NUM> and the control objects are connected to a network of a control system such as a field network or the like (not shown). The PLC <NUM> transmits and receives various control data to the control object and thus controls the production facilities by periodically communicating with the control objects via the network of the control system. The PLC <NUM> further generates large capacity data used for statistics processing or the like of an operational status or the like of the control system <NUM> on the basis of the data collected from each of the control objects, and stores the data in the memory <NUM>.

The unit <NUM> is a device (an information processing device) connected to the PLC <NUM> and operates in cooperation with the PLC <NUM>. In the embodiment, the unit <NUM> takes charge of various types of processing applied to the large capacity data generated by the PLC <NUM> to reduce, for example, a processing load of the CPU <NUM> of the PLC <NUM>. As such processing, for example, packet division processing, abnormality processing, and the like, are exemplified.

In the PLC <NUM>, each of the CPU <NUM>, the memory <NUM>, and the switching part <NUM> is connected to the serial bus <NUM>. One end of the serial bus <NUM> is connected to the communication interface <NUM> in the protocol control part <NUM> of the unit <NUM>. The serial bus <NUM> is a communication route on which serial communication is executed, for example, a Peripheral Component Interconnect express (PCIe) bus.

The CPU <NUM> is a processor configured to generally control operations of the PLC <NUM>. The memory <NUM> is any of various types of non-volatile recording media such as a read only memory (ROM) or the like. The switching part <NUM> switches a communication partner of the transfer part <NUM> to the CPU <NUM> or the memory <NUM>. The CPU <NUM> can relay communication between the CPU <NUM> and the memory <NUM>. Accordingly, the CPU <NUM> relays each of communication between the transfer part <NUM> and the memory <NUM> and communication between the transfer part <NUM> and the CPU <NUM>. The protocol control part <NUM> transmits and receives data according to a communication protocol appropriate for serial communication on the serial bus <NUM>.

Control data is stored in the memory <NUM> to control the control object in the control system <NUM>. The CPU <NUM> reads the control data from the memory <NUM>, and periodically transmits the data to the control object. The CPU <NUM> starts one control cycle upon occurrence of any event (for example, reading start of the control data) as a trigger. Then, while the control cycle continues, various types of controls (for example, transmission of the control data or the like) to be executed in each cycle are executed.

The MPU <NUM>, the memory <NUM>, the switching part <NUM>, and the DMAC <NUM> are connected to a serial bus <NUM> in the unit <NUM>. Specifically, the DMAC <NUM> is connected to the serial bus <NUM> via the protocol control part <NUM>. The DMAC <NUM> is also further connected to the serial bus <NUM> via the protocol control part <NUM>. The serial bus <NUM> is, for example, a Peripheral Component Interconnect express (PCIe) bus. Both the CPU <NUM> and the DMAC <NUM> are connected to the memory <NUM> via the serial bus <NUM>, and thus the CPU <NUM> and the DMAC <NUM> share the memory <NUM>.

The micro processing unit (MPU) <NUM> is a processor configured to generally control operations of the unit <NUM>. The MPU <NUM> executes various types of processing such as the above-mentioned packet division processing, abnormality processing, and the like. The memory <NUM> is various types of non-volatile recording media such as a read only memory (ROM) and the like. The large capacity data or the like transferred from the unit <NUM> is stored in the memory <NUM>.

The switching part <NUM> switches a communication partner of the transfer part <NUM> to the MPU <NUM> or the memory <NUM>. Accordingly, each of communication between the transfer part <NUM> and the memory <NUM> and communication between the transfer part <NUM> and the MPU <NUM> is relayed. The switching part <NUM> can also relay communication between the MPU <NUM> and the memory <NUM>. The protocol control part <NUM> transmits and receives data to and from the protocol control part <NUM> according to a communication protocol appropriate for serial communication on the serial bus <NUM>.

The transfer part <NUM> executes data transfer between the PLC <NUM> and the unit <NUM> according to control by the MPU <NUM> or the CPU <NUM>. The DMAC <NUM> and the protocol control part <NUM> in the transfer part <NUM> take charge of communication with the memory <NUM> via the serial bus <NUM>. The DMAC <NUM> is a controller configured to read and write large capacity data in the memory <NUM> through direct access to the memory <NUM> with no intervention of the CPU <NUM>. The DMAC <NUM> transfers, for example, the large capacity data read from the memory <NUM> to the DMAC <NUM> through serial communication on the serial bus <NUM>, further transfers the data to the memory <NUM> through serial communication on the serial bus <NUM>, and thus writes the data on the memory <NUM>. The DMAC <NUM> can also write the large capacity data read from the memory <NUM> on the memory <NUM> by transferring the data to the memory <NUM> through serial communication on the serial bus <NUM>.

The protocol control part <NUM> cooperates with the protocol control part <NUM> and executes serial communication of data on the serial bus <NUM> according to a communication protocol appropriate for the serial communication on the serial bus <NUM>.

The protocol control part <NUM> cooperates with the protocol control part <NUM> and executes serial communication of data on the serial bus <NUM> according to a communication protocol appropriate for the serial communication on the serial bus <NUM>. The smallest payload data generating part <NUM> in the protocol control part <NUM> receives the large capacity data transferred to the memory <NUM> by the DMAC <NUM> from the DMAC <NUM>, divides the data into a plurality of pieces of smallest payload data, and thus generates each piece of smallest payload data. The smallest payload data is data of a minimum unit communicated upon serial communication on the serial bus <NUM>. The smallest payload data generating part <NUM> transmits the generated smallest payload data to the communication interface <NUM>. The smallest payload data generating part <NUM> outputs the transmission instruction of the smallest payload data to the ACK monitoring part <NUM> and the communication interface <NUM> at each constant time. The communication interface <NUM> receives this and transmits each piece of smallest payload data to the memory <NUM> via the serial bus <NUM> one by one at each constant time.

The ACK monitoring part <NUM> monitors whether an ACK with respect to the transmitted smallest payload data is received. The ACK is a completion report indicating that the smallest payload data is written on the memory <NUM>. The protocol control part <NUM> of the unit <NUM> transmits the ACK indicating that writing of the smallest payload data is terminated to the unit <NUM> via the serial bus <NUM> when the smallest payload data received from the unit <NUM> is written on the memory <NUM>. The ACK monitoring part <NUM> can calculate a transmission time of the smallest payload data based on reception of the ACK.

<FIG> is a sequence diagram showing an example of a flow of processing by the control system <NUM> according to the embodiment. The CPU <NUM> starts reading of the control data from the memory <NUM> at a time t1. In <FIG>, the CPU <NUM> transfers the control data constituted by five pieces of smallest payload data R1 to R5 from the memory <NUM> to the CPU <NUM>. The CPU <NUM> starts a control cycle C1 at the time t1. When a length of the control cycle C1 is indefinite and the CPU <NUM> completes processing of the control data read from the memory <NUM> and transmission to the control object, the control cycle C1 is terminated.

The protocol control part <NUM> does not start transmission of the large capacity data at the time t1. Accordingly, after the time t1, the CPU <NUM> continues transfer of the control data without causing memory contention with the transfer part <NUM>. The CPU <NUM> completes transfer of the five pieces of smallest payload data R1 to R5 from the time t1 to a time t2, and thus completes transfer of the control data to the CPU <NUM> in the control cycle C1.

The transfer part <NUM> starts transmission of the large capacity data to the memory <NUM> at the time t2 in the control cycle C1. Here, the smallest payload data generating part <NUM> outputs a transmission instruction of smallest payload data D1 of the transmission object to the ACK monitoring part <NUM> and the communication interface <NUM>. The ACK monitoring part <NUM> receives this and starts reception monitoring of the ACK with respect to the smallest payload data D1. The communication interface <NUM> receives this and transmits the smallest payload data D1 to the memory <NUM> via the serial bus <NUM>. In the PLC <NUM>, the protocol control part <NUM> receives the smallest payload data D1. Here, since the CPU <NUM> does not transfer the control data via the serial bus <NUM>, memory contention does not occur. Accordingly, the protocol control part <NUM> writes the received smallest payload data D1 on the memory <NUM> with no delay. In the example in <FIG>, writing of the smallest payload data D1 is terminated at a time t3. The protocol control part <NUM> transmits the ACK indicating that writing of the smallest payload data D1 is completed to the transfer part <NUM> via the serial bus <NUM> at the time t3.

The communication interface <NUM> in the transfer part <NUM> receives the ACK with respect to the smallest payload data D1 at the time t3 and outputs the ACK to the ACK monitoring part <NUM>. The ACK monitoring part <NUM> calculates a transmission time T1 of the smallest payload data D1 based on the time t2 when the monitoring is started and the time t3 when the ACK is received. Here, the transmission time T1 is an elapsed time from the time t2 to the time t3. The ACK monitoring part <NUM> determines whether the calculated transmission time T1 exceeds a reference value at the time t3. The reference value greater than the transmission time T1 is set in the unit <NUM> in advance. Accordingly, the ACK monitoring part <NUM> determines that the transmission time T1 does not exceed the reference value at the time t3. Accordingly, a prohibition signal is not output to the smallest payload data generating part <NUM>.

The smallest payload data generating part <NUM> outputs the transmission instruction of the next smallest payload data D2 to the ACK monitoring part <NUM> and the communication interface <NUM> at the time t3 because the prohibition signal is not input at the time t3. The ACK monitoring part <NUM> receives this and newly starts reception monitoring of the ACK with respect to the smallest payload data D2. The communication interface <NUM> transmits the input smallest payload data D2 to the memory <NUM> via the serial bus <NUM>. After that, the same processing is repeated until the time t4 when the control cycle C1 is terminated. That is, since the control data is not transferred after the time t4, the transmission time of each of the pieces of smallest payload data D2 to D5 does not exceed the reference value. Accordingly, the transfer part <NUM> transmits and writes the smallest payload data D2 to D5 on the memory <NUM> in sequence with no delay without causing the memory contention. As a result, in the example of <FIG>, the CPU <NUM> and the transfer part <NUM> do not cause memory contention throughout the control cycle C1.

The CPU <NUM> terminates the control cycle C1 at the time t4, and starts the next control cycle C2. The CPU <NUM> starts transfer of the smallest payload data R1 of the control data from the memory <NUM> to the CPU <NUM> at the time t4. Meanwhile, the protocol control part <NUM> transmits the smallest payload data D6 of the large capacity data to the memory <NUM> at the time t4 (a first point of time). As a result, since the CPU <NUM> and the protocol control part <NUM> access the memory <NUM> at the same time, memory contention occurs. The protocol control part <NUM> of the PLC <NUM> gives priority to the memory access by the CPU <NUM>, reads the smallest payload data R1 in the memory <NUM> from the memory <NUM>, and transmits the data to the CPU <NUM>. The transmission is terminated at the time t41. The CPU <NUM> starts transfer of the next smallest payload data R2 from the memory <NUM> at the time t41.

The time t41 is equal to a time when the transfer part <NUM> should start transmission of the next smallest payload data D7. The smallest payload data generating part <NUM> outputs the transmission instruction of the next smallest payload data D7 to the ACK monitoring part <NUM> and the communication interface <NUM> at the time t41 based on the lapse of the constant time after the time t4. Since the ACK monitoring part <NUM> has not yet received the ACK of the smallest payload data D6, even when a new transmission instruction is received, ACK reception monitoring of the smallest payload data D6 is continued. The communication interface <NUM> transmits the input smallest payload data D7 to the memory <NUM> via the serial bus <NUM> at the time t41.

The protocol control part <NUM> writes the smallest payload data D6, writing of which is on standby due to memory contention, on the memory <NUM> at the time t41. The writing is terminated at the time t5. The protocol control part <NUM> transmits the ACK with respect to the smallest payload data D6 to the transfer part <NUM> at the time t5.

The communication interface <NUM> receives the ACK with respect to the smallest payload data D6 at the time t5 (a second point of time) and outputs the ACK to the ACK monitoring part <NUM>. The ACK monitoring part <NUM> calculates the transmission time T2 of the smallest payload data D6 based on the time t4 when the monitoring is started and the time t5 when the ACK is received. Here, the transmission time T2 is an elapsed time from the time t4 to the time t5. The ACK monitoring part <NUM> determines whether the calculated transmission time T2 exceeds the reference value at the time t5. In the example of <FIG>, the transmission time T2 is substantially equal to a sum of the transmission time T1 when two pieces of smallest payload data are transmitted with no delay, and thus has a value of about two times the transmission time T1. Accordingly, the ACK monitoring part <NUM> determines that the transmission time T2 exceeds the reference value at the time t5. Accordingly, the prohibition signal is output to the smallest payload data generating part <NUM> at the time t5.

The time t5 is equal to a time when the transfer part <NUM> should start transmission of the next smallest payload data D8. The smallest payload data generating part <NUM> does not immediately output the transmission instruction of the next smallest payload data D8 based on the prohibition signal being input, and the output of the instruction transmission is on standby until the predetermined duration T3 (a constant duration) elapses to become a time t6 (a third point of time) after the time t5. The duration T3 is set to the unit <NUM> in advance as a standby duration in which transmission of the next smallest payload data is on standby at the communication interface <NUM> when the memory contention occurs. In the example of <FIG>, the smallest payload data generating part <NUM> causes transmission of the next smallest payload data D8 to the memory <NUM> to be on standby at the communication interface <NUM> during the duration T3 from the time t4 to the time t5.

Reading of the smallest payload data R2 from the memory <NUM> and writing of the smallest payload data D7 on the memory <NUM> at the time t5 are not yet terminated. That is, the CPU <NUM> and the protocol control part <NUM> cause memory contention again. Execution of both of reading of the smallest payload data R2 and writing of the smallest payload data D7 is delayed to the duration T3. The protocol control part <NUM> reads the smallest payload data R1 from the memory <NUM> to transfer the data to the CPU <NUM>, and then writes the smallest payload data D7 on the memory <NUM>. After the time t5, the CPU <NUM> sequentially executes transfer of the remaining smallest payload data R3 to R5. All of the timings when this data is transferred to the CPU <NUM> are within the duration T3. During the duration T3, since transmission of the smallest payload data D8 is on standby, transmission of the large capacity data is not executed. Accordingly, the CPU <NUM> does not cause memory contention with respect to the smallest payload data R3 to R5, i.e., can read it out of the memory <NUM> with no delay. In the example of <FIG>, the control data that causes memory contention is only the initial two pieces of smallest payload data R1 and R2, and none of the remaining three pieces of smallest payload data R3, R4 and R5 causes memory contention.

<FIG> is a sequence diagram showing an example of a flow of processing by a control system in the related art according to a comparative example. In the comparative example, transmission standby processing of the smallest payload data as shown in <FIG> is not executed. For this reason, after the CPU <NUM> and the protocol control part <NUM> cause the memory contention at the time t2, the memory contention is not terminated in the control cycle C2, and the memory contention continues to occur till the termination point of time of the control cycle C2. That is, in the control cycle C2, all of five pieces of smallest payload data of the control data and five pieces of smallest payload data of the large capacity data cause the memory contention. Accordingly, each smallest payload data of the control data and each smallest payload data of the large capacity data will be transferred alternately and sequentially one by one.

As shown in <FIG>, the smallest payload data generating part <NUM> causes transmission of the smallest payload data D8 to be on standby at the communication interface <NUM> in the duration T3 from the time t5 when it is determined that the transmission time T2 of the smallest payload data D6 exceeds the reference value in the control cycle C2 to the time t6 when the communication interface <NUM> transmits the smallest payload data D8, which is transmitted after the latest smallest payload data D7 is transmitted at the time t5. Accordingly, since transmission of the smallest payload data D8 of the large capacity data is on standby during the duration T3 after the time t3 when the memory contention occurs, the memory contention with respect to the smallest payload data R3 to R5 do not occur. As a result, occurrence of the memory contention in the control cycle C2 can be minimized compared to the comparative example shown in <FIG>.

The ACK monitoring part <NUM> calculates the transmission time T1 of the smallest payload data D1 based on time t1 when transmission of the smallest payload data D1 is started and the time t2 when the ACK with respect to the smallest payload data D1 is received in the control cycle C1. In addition, in the control cycle C2, the ACK monitoring part <NUM> calculates the transmission time T2 of the smallest payload data D6 in the control cycle C2 based on the time t4 when transmission of the smallest payload data D6 is started and the time t5 when the ACK with respect to the smallest payload data D6 is received. In both cases, since the transmission time is calculated based on reception of the ACK with respect to one smallest payload data D1 or D6, a large time difference does not occur when an occurrence point of time of the memory contention due to transmission of certain smallest payload data and a point of time upon determination of whether the memory contention occurs. Accordingly, when the memory contention occurs, since the fact can be determined quickly, it is possible to quickly take a measure to minimize the memory contention upon occurrence thereof.

<FIG> is a sequence diagram showing an example of ACK transmission according to the embodiment. In the example of <FIG>, the ACK monitoring part <NUM> starts ACK monitoring of the smallest payload data at a monitoring start time Ts. The protocol control part <NUM> transmits nth smallest payload data to the PLC <NUM> at the monitoring start time Ts. In the PLC <NUM>, the protocol control part <NUM> receives the nth smallest payload data and store the data on the memory <NUM>. Here, the protocol control part <NUM> does not transmit the ACK that the nth smallest payload data is written to the protocol control part <NUM>. The protocol control part <NUM> continuously transmit (n+<NUM>)th to (n+<NUM>)th smallest payload data to the PLC <NUM> in sequence. The protocol control part <NUM> receives these pieces of smallest payload data and writes the data on the memory <NUM>. Here, when writing of the (n+<NUM>)th smallest payload data is terminated, the protocol control part <NUM> generates the ACK that total four pieces of nth to (n+<NUM>)th smallest payload data are written, and transmits the data to the protocol control part <NUM>. ACK: n+<NUM> in <FIG> indicates that the ACK is a writing completion report related to the nth to (n+<NUM>)th smallest payload data.

The protocol control part <NUM> outputs the received ACK: n+<NUM> to the ACK monitoring part <NUM>. The ACK monitoring part <NUM> determines that the point of time when the ACK: n+<NUM> is received is a monitoring termination time Te. Then, a transmission time corresponding to one of the four pieces of smallest payload data n to n+<NUM>, which are continuously transmitted, is calculated based on the monitoring start time Ts and the monitoring termination time Te. Specifically, the transmission time is calculated by dividing the elapsed time from the monitoring termination time Te to the monitoring start time Ts by <NUM>.

The ACK monitoring part <NUM> determines whether the calculated transmission time exceeds the reference value, and outputs the prohibition signal to the smallest payload data generating part <NUM> when it is determined as exceeding.

In the example of <FIG>, even in the control system <NUM> that does not transmit the ACK for each transmitted smallest payload data and transmits the ACK for each of the plurality of lump smallest payload data, it is possible to determine whether a transmission delay (i.e., the memory contention) of the smallest payload data occurs upon transmission of the large capacity data. Accordingly, it is possible to minimize occurrence of the memory contention after occurrence of the transmission delay. In the example of <FIG>, further, since the number of determination executions is reduced in comparison with the case in which determination processing is executed for each smallest payload data, it is possible to reduce a determination load in the control system <NUM>.

<FIG> is a sequence diagram showing another example of a flow of processing by the control system <NUM> according to the embodiment. In the example of <FIG>, the CPU <NUM> reads the control data with a larger capacity than in <FIG> from the CPU <NUM>. Specifically, the control data constituted by fifteen pieces of smallest payload data R1 to R15 are stored in the memory <NUM>, and the CPU <NUM> reads this from the CPU <NUM> in the control cycle C1. A long time is required due to the transfer because a capacity of the control data is large, and thus, it is more likely to cause the memory contention.

For example, at the time t11 at the start point of time in the control cycle C1, since the CPU <NUM> is trying to read the smallest payload data R1 from the memory <NUM> and the protocol control part <NUM> is trying to write the smallest payload data D1 on the memory <NUM>, the memory contention occurs. Accordingly, the ACK monitoring part <NUM> determines that the transmission time T2 of the smallest payload data D1 exceeds the reference value at the time t12 when the transmission of the smallest payload data D1 is completed. As a result, the communication interface <NUM> stands by the transmission of the smallest payload data D3 during the duration T3 after the time t12. The communication interface <NUM> receives the transmission instruction of the smallest payload data D3 from the smallest payload data generating part <NUM> at the time t13, and thus, transmits the smallest payload data D3 to the memory <NUM> at the time t13.

In the example of <FIG>, since the CPU <NUM> is trying to read the smallest payload data R6 from the memory <NUM> at the time t15 and the protocol control part <NUM> is trying to write the smallest payload data D3 on the memory <NUM>, the memory contention occurs. That is, after the transmission is on standby by the duration T3, the memory contention occurs again. Accordingly, the ACK monitoring part <NUM> determines that the transmission time T2 of the smallest payload data D3 exceeds the reference value at the time t15 when transmission of the smallest payload data D3 is completed. As a result, the communication interface <NUM> stands by transmission of the smallest payload data D5 during the duration T3 after the time t14. The communication interface <NUM> receives the transmission instruction of the smallest payload data D5 from the smallest payload data generating part <NUM> at the time t15, and thus, transmits the smallest payload data D3 to the memory <NUM> at the time t15.

In the example of <FIG>, since the CPU <NUM> is trying to read the smallest payload data R11 from the memory <NUM> at the time t15 and the protocol control part <NUM> is trying to write the smallest payload data D5 on the memory <NUM>, the memory contention occurs. That is, after the transmission is on standby by the duration T3, the memory contention occurs again. Accordingly, the ACK monitoring part <NUM> determines that the transmission time T2 of the smallest payload data D3 exceeds the reference value at the time t16 when transmission of the smallest payload data D3 is completed.

The ACK monitoring part <NUM> determines whether events that the transmission time of the smallest payload data exceeds the reference value occur continuously constant times at the time t16. In <FIG>, three times are previously set to the unit <NUM> as the certain number. Accordingly, the ACK monitoring part <NUM> determines that the events that the transmission time of the smallest payload data exceeds the reference value occur continuously the constant times. As a result, the ACK monitoring part <NUM> does not output the prohibition signal to the smallest payload data generating part <NUM> at the time t16. Accordingly, the smallest payload data generating part <NUM> outputs immediately the transmission instruction of the smallest payload data D7 transmitted after the smallest payload data D6 that has been transmitted at the point of time upon the time t16 to the ACK monitoring part <NUM> and the communication interface <NUM> without waiting for the lapse of the duration T3. Accordingly, the communication interface <NUM> transmits the smallest payload data D7 to the memory <NUM> at the time t16. After that, the ACK monitoring part <NUM> does not transmit the prohibition signal to the smallest payload data generating part <NUM> regardless of the transmission time of each smallest payload data. Accordingly, the smallest payload data generating part <NUM> outputs the transmission instruction to the communication interface <NUM> for each prescribed constant time with respect to the smallest payload data D8, D9,. transmitted after the smallest payload data D7.

As shown in <FIG>, after transmission of the smallest payload data D7, reading any one of the smallest payload data R12 to R15 and writing any one of the smallest payload data D6 toD9 always cause the memory contention. Meanwhile, after the time t16, since the transmission of the large capacity data is executed without waiting for the duration T3, while causing the memory contention, transmission of the large capacity data will be executed little by little without waiting for transfer completion of the control data. Accordingly, it is possible to prevent transmission of the large capacity data from being delayed more than necessity when the memory contention occurs repeatedly.

<FIG> is a block diagram showing a major part configuration of the control system 1A according to the embodiment. The control system <NUM> includes the PLC <NUM>, the unit <NUM>, and a setting device <NUM>. Since internal configurations of the PLC <NUM> and the unit <NUM> of <FIG> are the same as the internal configurations of the PLC <NUM> and the unit <NUM> of <FIG>, respectively, detailed description thereof will not be repeated.

The setting device <NUM> is an external device connected to the PLC <NUM> and operated by a user such as a manager or the like of the control system <NUM>. The setting device <NUM> includes a program creating part <NUM>, a simulation execution part <NUM>, and a setting part <NUM>. The setting part <NUM> is connected to the CPU <NUM> of the PLC <NUM>. The PLC <NUM> is a device configured to execute a program created by a user, and the setting device <NUM> is a device configured to allow the user to create the program.

The program creating part <NUM> creates a program executed in the PLC <NUM> according to the operation of the setting device <NUM> by the user. The setting part <NUM> provides the created program to the CPU <NUM>. The CPU <NUM> executes the provided program. The simulation execution part <NUM> executes the created program through simulation. In other words, a behavior when the CPU <NUM> executes the program in the PLC <NUM> is simulated in the setting device <NUM>. The simulation execution part <NUM> calculates a communication time when the CPU <NUM> communicates the control data with the memory <NUM> through simulation by executing the created program through simulation.

<FIG> is a sequence diagram showing an example of a flow of processing by the control system <NUM> according to the embodiment. In the example of <FIG>, the simulation execution part <NUM> calculates a time Tcpu required for transfer of the control data constituted by the five pieces of smallest payload data R1 to R5. The setting part <NUM> outputs the calculated time Tcpu to the CPU <NUM>. The CPU <NUM> generates information indicating the received time Tcpu, and transmits the information to the protocol control part <NUM> via the serial bus <NUM>. In the protocol control part <NUM>, the communication interface <NUM> receives the information indicating the time Tcpu, and outputs the information to the ACK monitoring part <NUM>. In other words, the communication interface <NUM> acquires the information indicating the time Tcpu from the CPU <NUM>. The ACK monitoring part <NUM> outputs the input information to the smallest payload data generating part <NUM>. The smallest payload data generating part <NUM> sets the duration T3 to the unit <NUM> based on the information indicating the input time Tcpu. In the example of <FIG>, the duration T3 is set by dividing the time Tcpu by a predetermined coefficient N. The coefficient N is previously set to the unit <NUM>. In the example of <FIG>, N = <NUM>. That is, a length of the duration T3 is equal to the time Tcpu calculated through simulation. A value of N may be an arbitrary value according to an operational status of the control system <NUM>, for example, may be <NUM> or <NUM>. The user can set the value of the coefficient N to the setting device <NUM>. In this case, the setting part <NUM> outputs the value of the coefficient N set by the user to the CPU <NUM>. The CPU <NUM> provides the value of the coefficient N to the smallest payload data generating part <NUM> via the serial bus <NUM> or the like, similar to the case in which the time Tcpu is provided to the protocol control part <NUM>. The smallest payload data generating part <NUM> sets the provided value of the coefficient N to the unit <NUM>.

Since the duration T3 is set based on the time Tcpu calculated through simulation, an appropriate duration T3 is automatically set to the unit <NUM>. That is, since each user of the control system <NUM> does not have to calculate the duration T3 by oneself, the user's trouble of setting an appropriate duration T3 to the unit <NUM> is eliminated. In other words, the smallest payload data generating part <NUM> sets automatically the appropriate duration T3 to the unit <NUM> as long as the user creates the program executed by the PLC <NUM> in his/her control system <NUM>.

The CPU <NUM> can measure the transfer time when the CPU <NUM> transfers the control data to and from the memory <NUM> during the operation of the PLC <NUM>, i.e., during execution of the program created by the user. The CPU <NUM> corrects the information indicating the time Tcpu provided from the setting part <NUM> based on the transfer time measured by the CPU <NUM> when the transfer time is measured. For example, the time Tcpu indicated by the information approaches the transfer time measured by the CPU <NUM>. The CPU <NUM> transmits the information after correction to the unit <NUM>. Accordingly, the smallest payload data generating part <NUM> can set the duration T3 to the unit <NUM> based on the time Tcpu close to the actual transfer time of the control data by the CPU <NUM>. Accordingly, when the memory contention occurs, the communication interface <NUM> can be on standby for the more appropriate duration T3 until the next smallest payload data is transmitted. In addition, when the transfer time of the control data by the CPU <NUM> is changed together with advance of an operation of the control system <NUM>, since the time Tcpu can be adjusted appropriately according to the change of the transfer time, the appropriate.

The control block (in particular, the transfer part <NUM> and the DMAC <NUM>) of the unit <NUM> may be realized by a logical circuit (hardware) constituted by an integrated circuit (IC chip) or the like, or may be realized by software.

In the case of the latter, each of the units <NUM>, 20A, and <NUM> includes a computer configured to execute a command of a program that is software configured to realize each function. The computer includes, for example, at least one processor, and also includes a computer-readable recording medium on which the program is stored. Then, in the computer, the processor is executed by reading the program from the recording medium, and the purposes of the present invention are accomplished. For example, a central processing unit (CPU) can be used as the processor. As the recording medium, "a non-temporary tangible medium," for example, in addition to the read only memory (ROM), a tape, a disk, a card, a semiconductor memory, a programmable logical circuit, and the like, can be used. In addition, the random access memory (RAM) or the like configured to deploy the program may be further provided. In addition, the program may be supplied to the computer via an arbitrary transmission medium (a communication network, a broadcast medium, or the like) that can transmit the program. Further, the aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the program is embodied through electronic transmission.

The system according to the invention is defined by claim <NUM>.

According to the configuration, when it is determined that the transmission time of the smallest payload data transmitted to the first memory at the first point of time exceeds the predetermined reference value, the transmission of the smallest payload data transmitted next to the latest smallest payload data that has been transmitted at the second point of time determined in this way is on standby for a constant duration. Accordingly, since the second communication part does not transmit the communication data to the first memory during the constant duration after the second point of time, a memory contention does not occur between the first communication part and the second communication part. Here, since avoidance of the memory contention is realized based on the transmission time of the smallest payload data calculated by the computation part, the first communication part does not need to execute arbitration processing to prevent memory contention. In this way, the information processing device according to the aspect of the present invention can minimize occurrence of memory contention without causing the first communication part of the control device to execute arbitration processing to prevent the memory contention. Accordingly, a load of the first communication part can be reduced.

In the above-mentioned system, the information processing device includes a reception part configured to receive a completion report indicating that the smallest payload data transmitted at the first point of time is written on the first memory, and the computation part calculates the transmission time based on the first point of time and a point of time when the completion report is received.

According to the configuration, when the memory contention occurs, since the fact can be quickly determined, a measure can be quickly taken to minimize the memory contention upon occurrence of the memory contention.

In the above-mentioned configuration, the reception part receives the completion report indicating that the plurality of continuously transmitted smallest payload data are written on the first memory, the computation part calculates the transmission time of each of the smallest payload data based on the first point of time and the point of time when the completion report is received, and the determination part determines whether the transmission time of each of the smallest payload data exceeds the reference value.

According to the configuration, the present invention can also be applied to the information processing device configured to conclusively receive a writing completion report for the plurality of pieces of smallest payload data. In addition, since the number of executions of determination can be reduced, a load of determination in the information processing device can be reduced.

In the above-mentioned system, the control device is connected to an external device configured to calculate a transmission time when the first communication part transfers first data to and from the first memory through simulation and configured to provide information indicating the calculated transmission time to the control device, and the information processing device includes: an acquisition part configured to acquire the information provided from the external device to the control device from the control device, and a setting part configured to set the constant duration based on the information.

According to the configuration, since the constant duration is set based on the time calculated through simulation, an appropriate constant duration is automatically set to the information processing device. That is, since it is not necessary for each user of the control system to calculate a constant duration by himself/herself, it is possible to eliminate the user's trouble for setting an appropriate constant duration.

In the above-mentioned system, the first communication part measures a transmission time when the first data is transmitted to the first memory during an operation of the control device and corrects information indicating the transmission time based on the measured transmission time, and the acquisition part acquires the corrected information from the control device.

According to the configuration, when the transfer time of the first data by the first communication part is changed together with advance of the operation of the control system, since the set constant duration can be appropriately prepared according to the change of the transfer time, the appropriate constant duration can be continuously set to the information processing device.

In the above-mentioned system, the transmission control part makes the transmission part transmitting the next smallest payload data without making the transmission part stand by when the events that the transmission time is determined as exceeding the reference value occur continuously constant times.

According to the configuration, it is possible to prevent transmission of the communication data from being delayed more than necessity.

Claim 1:
A system comprising:
a serial bus (<NUM>);
a control device (<NUM>) comprising:
a first memory (<NUM>) connected to the serial bus (<NUM>);
a first communication part (<NUM>) connected to the serial bus (<NUM>) and configured to communicate with the first memory (<NUM>) via the serial bus (<NUM>);
an information processing device (<NUM>) connected to the control device;
wherein the information processing device (<NUM>) comprises:
a generating part (<NUM>) configured to generate a plurality of pieces of smallest payload data from communication data transmitted to the first memory via the serial bus;
a transmission part (<NUM>) configured to sequentially transmit at each constant time a corresponding smallest payload data of the plurality of pieces of smallest payload data to the first memory via the serial bus;
a computation part (<NUM>) configured to calculate a transmission time of the smallest payload data transmitted by the transmission part at a first point of time;
a determination part (<NUM>) configured to determine whether the calculated transmission time exceeds a predetermined reference value; and
a transmission control part (<NUM>) configured to cause the transmission part to stand by for transmission of the smallest payload data during a constant duration from a second point of time when it is determined that the transmission time has been determined as exceeding the reference value to a third point of time when the transmission part transmits the smallest payload data transmitted after the latest smallest payload data that has been transmitted at the second point of time,
characterized in that the system further comprises an external device (<NUM>) wherein the control device (<NUM>) is connected to the external device (<NUM>) configured to calculate a transmission time when the first communication part (<NUM>) transfers first data to and from the first memory (<NUM>) through simulation and configured to provide information indicating the calculated transmission time to the control device, and the information processing device comprises:
an acquisition part (<NUM>) configured to acquire the information provided from the external device to the control device from the control device, and
a setting part (<NUM>) configured to set the constant duration based on the information.