Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logical operations on data (e.g., one or more operands). For example, functional unit circuitry may be used to perform arithmetic operations such as addition, subtraction, multiplication, and division on operands via a number of operations.

A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and data may be retrieved from the memory array and sequenced and buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and data may also be sequenced and buffered.

In many instances, the processing resources (e.g., processor and associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory device, in which a processor may be implemented internal and near to a memory (e.g., directly on a same chip as the memory array). A processing-in-memory device may save time by reducing and eliminating external communications and may also conserve power. However, data movement between and within banks of a processing-in-memory device may influence the data processing time of the processing-in-memory device.

By way of further background, reference is made to the following publications.

United States Patent Application Publication No.: <CIT>describes an apparatus comprising: a memory device, comprising: an array of memory cells; sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including a sense amplifier; a controller configured to couple to the array and sensing circuitry; and a shared I/O line configured to couple a source location to a destination location.

United States Patent Application Publication No.: <CIT> describes a memory device that has memory cells addressable through word lines and bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

The present disclosure includes apparatuses and methods for data movement, e.g., for processor-in-memory (PIM) structures, among other configurations described herein or otherwise. In at least one embodiment, the apparatus includes a memory device configured to couple to a host via a data bus and a control bus. A bank in the memory device includes an array of memory cells and sensing circuitry, e.g., formed on pitch with the array, coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location and a destination location, e.g., between a pair of bank locations.

As described in more detail below, the embodiments can allow a host system to allocate a number of locations, e.g., sub-arrays (or "subarrays") and portions of subarrays, in one or more DRAM banks to hold (e.g., store) data. A host system and a controller may perform the address resolution on an entire block of program instructions, e.g., PIM command instructions, and data and direct (e.g., control) allocation and storage of data and commands into allocated locations, e.g., subarrays and portions of subarrays within a destination (e.g., target) bank. Writing data and commands may utilize a normal DRAM write path to the DRAM device. As the reader will appreciate, while a DRAM-style PIM device is discussed with regard to examples presented herein, embodiments are not limited to a PIM DRAM implementation.

Data movement between and within PIM banks, e.g., subarrays and portions of subarrays therein, may affect whether PIM operations are completed (performed) efficiently. Accordingly, the present disclosure presents structures and processes that can increase a speed, rate, and efficiency of data movement in a PIM array by using an improved data path, e.g., a shared I/O line of a DRAM implementation, as described herein.

In previous approaches, data may be transferred from the array and sensing circuitry (e.g., via a bus comprising input/output (I/O) lines) to a processing resource external to the memory array, such as a processor, microprocessor, and/or compute engine that may be located on a host, which may comprise ALU circuitry and other functional unit circuitry configured to perform the appropriate operations. However, transferring data from a memory array and sensing circuitry to such processing resource(s) can involve significant power consumption. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry, which can involve performing a sense line (which may be referred to herein as a digit line or data line) address access (e.g., firing of a column decode <NUM> signal) in order to transfer data from sense lines onto I/O lines (e.g., local and global I/O lines), moving the data to a periphery of the memory array, and providing the data to the compute function.

Furthermore, the circuitry of the processing resource(s) (e.g., a compute engine) may not conform to pitch rules associated with a memory array. For example, the cells of a memory array may have a 4F<NUM> or 6F<NUM> cell size, where "F" is a feature size corresponding to the cells. As such, the devices (e.g., logic gates) associated with ALU circuitry of previous PIM systems may not be capable of being formed on pitch with the memory cells, which can affect chip size and memory density, for example.

A number of embodiments of the present disclosure include sensing circuitry and compute circuitry formed on pitch with an array of memory cells. The sensing circuitry and compute circuitry are capable of performing data sensing and compute functions and storage, e.g., caching, of data local to the array of memory cells.

In order to appreciate the improved data movement techniques described herein, a discussion of an apparatus for implementing such techniques, e.g., a memory device having PIM capabilities and associated host, follows. According to various embodiments, program instructions, e.g., PIM commands, involving a memory device having PIM capabilities can distribute implementation of the PIM commands and data over multiple sensing circuitries that can implement operations and can move and store the PIM commands and data within the memory array, e.g., without having to transfer such back and forth over an A/C and data bus between a host and the memory device. Thus, data for a memory device having PIM capabilities can be accessed and used in less time and using less power. For example, a time and power advantage can be realized by increasing the speed, rate, and efficiency of data being moved around and stored in a computing system in order to process requested memory array operations (e.g., reads, writes, etc.).

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

As used herein, designators such as "X", "Y", "N", "M", etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" include singular and plural referents, unless the context clearly dictates otherwise, as do "a number of", "at least one", and "one or more" (e.g., a number of memory arrays can refer to one or more memory arrays), whereas a "plurality of" is intended to refer to more than one of such things. Furthermore, the words "can" and "may" are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term "include," and derivations thereof, means "including, but not limited to". The terms "coupled" and "coupling" mean to be directly or indirectly connected physically or for access to and movement (transmission) of instructions (e.g., control signals) and data, as appropriate to the context.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be taken in a limiting sense.

<FIG> is a block diagram of an apparatus in the form of a computing system <NUM> including a memory device <NUM> in accordance with a number of embodiments of the present disclosure. As used herein, a memory device <NUM>, controller <NUM>, channel controller <NUM>, memory array <NUM>, sensing circuitry <NUM>, including sensing amplifiers and compute circuitry, and peripheral sense amplifier and logic <NUM> might each also be separately considered an "apparatus.

The system <NUM> can include a host <NUM> coupled (e.g., connected) to memory device <NUM>, which includes the memory array <NUM>. Host <NUM> can be a host system such as a personal laptop computer, a desktop computer, a tablet computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host <NUM> can include a system motherboard and backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system <NUM> can include separate integrated circuits or both the host <NUM> and the memory device <NUM> can be on the same integrated circuit. The system <NUM> can be, for instance, a server system and a high performance computing (HPC) system and a portion thereof. Although the example shown in <FIG> illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, description of the system <NUM> has been simplified to focus on features with particular relevance to the present disclosure. For example, in various embodiments, the memory array <NUM> can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and NOR flash array, for instance. The memory array <NUM> can include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although a single memory array <NUM> is shown in <FIG>, embodiments are not so limited. For instance, memory device <NUM> may include a number of memory arrays <NUM> (e.g., a number of banks of DRAM cells, NAND flash cells, etc.) in addition to a number subarrays, as described herein. Accordingly, descriptions in the present disclosure may be made with regard to PIM and/or DRAM architectures by way of example and/or clarity. However, unless explicitly stated otherwise, the scope of the present disclosure and claims is not limited to PIM and/or DRAM architectures.

The memory device <NUM> can include address circuitry <NUM> to latch address signals provided over a data bus <NUM> (e.g., an I/O bus from the host <NUM>) by I/O circuitry <NUM> (e.g., provided to external ALU circuitry and to DRAM DQs via local I/O lines and global I/O lines). Status and exception information can be provided from the controller <NUM> on the memory device <NUM> to a channel controller <NUM>, for example, through a high speed interface (HSI) out-of-band bus <NUM>, which in turn can be provided from the channel controller <NUM> to the host <NUM>. Address signals are received through address circuitry <NUM> and decoded by a row decoder <NUM> and a column decoder <NUM> to access the memory array <NUM>. Data can be sensed (read) from memory array <NUM> by sensing voltage and current changes on sense lines (digit lines) using a number of sense amplifiers, as described herein, of the sensing circuitry <NUM>. A sense amplifier can read and latch a page (e.g., a row) of data from the memory array <NUM>. Additional compute circuitry, as described herein, can be coupled to the sensing circuitry <NUM> and can be used in combination with the sense amplifiers to sense, store, e.g., cache and buffer, and move data. The I/O circuitry <NUM> can be used for bi-directional data communication with host <NUM> over the data bus <NUM> (e.g., a <NUM> bit wide data bus). The write circuitry <NUM> can be used to write data to the memory array <NUM>.

Controller <NUM>, e.g., bank control logic and sequencer, can decode signals (e.g., commands) provided by control bus <NUM> from the host <NUM>. The controller <NUM> can control operations by issuing control signals determined from the decoded commands from the host <NUM>. These signals can include chip enable signals, write enable signals, and address latch signals that can be used to control operations performed on the memory array <NUM>, including data sense, data store, data move, data write, and data erase operations, among other operations. In various embodiments, the controller <NUM> can be responsible for executing instructions from the host <NUM> and accessing the memory array <NUM>. The control signals may be executed by processing resources external to and/or internal to a memory array <NUM> (e.g., by compute components <NUM> in sensing circuitry <NUM>, as described herein). The controller <NUM> can be a state machine, a sequencer, or some other type of controller. The controller <NUM> can control shifting data (e.g., right or left) in a row of an array, e.g., memory array <NUM>.

Examples of the sensing circuitry <NUM> are described further below, e.g., in <FIG> and <FIG>. For instance, in a number of embodiments, the sensing circuitry <NUM> can include a number of sense amplifiers and a number of compute components, which may serve as an accumulator and can be used to perform operations (e.g., on data associated with complementary sense lines).

In a number of embodiments, the sensing circuitry <NUM> can be used to perform operations using data stored in memory array <NUM> as inputs and participate in movement of the data for writing and storage operations back to a different location in the memory array <NUM> without transferring the data via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry <NUM> rather than (or in association with) being performed by processing resources external to the sensing circuitry <NUM> (e.g., by a processor associated with host <NUM> and other processing circuitry, such as ALU circuitry, located on device <NUM>, such as on controller <NUM> or elsewhere).

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry, e.g., in the host, via I/O lines (e.g., via local I/O lines and global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry <NUM> is configured to perform operations on data stored in memory array <NUM> and store the result back to the memory array <NUM> without enabling a local I/O line and global I/O line coupled to the sensing circuitry <NUM>, e.g., for read and/or write operations based on host commands. In contrast, the data movement operations described herein utilize a cooperative interaction between the sensing circuitry <NUM> and shared I/O lines <NUM> described herein. The sensing circuitry <NUM> and the shared I/O lines <NUM> may be formed on pitch with the memory cells of the array. Additional peripheral sense amplifier and logic <NUM> can be coupled to the sensing circuitry <NUM>. The sensing circuitry <NUM> and the peripheral sense amplifier and logic <NUM> can cooperate in performing operations, according to some embodiments described herein.

As such, in a number of embodiments, circuitry external to memory array <NUM> and sensing circuitry <NUM> is not needed to perform compute functions as the sensing circuitry <NUM> can perform the appropriate operations in order to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry <NUM> may be used to complement and to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

In a number of embodiments, the sensing circuitry <NUM> may be used to perform operations (e.g., to execute instructions) in addition to operations performed by an external processing resource (e.g., host <NUM>). For instance, either of the host <NUM> and the sensing circuitry <NUM> may be limited to performing only certain operations and a certain number of operations.

Enabling a local I/O line and global I/O line, e.g., for read and/or write operations, can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode <NUM> signal) and a source/drain coupled to the local I/O line and/or global I/O line. However, embodiments are not limited to not enabling a local I/O line and global I/O line. For instance, in a number of embodiments, the sensing circuitry <NUM> can be used to perform operations, such as data movement, without enabling column decode lines <NUM> of the array. However, the local I/O line(s) and global I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the memory array <NUM> (e.g., to an external register).

<FIG> is a block diagram of a bank section <NUM> to a memory device in accordance with a number of embodiments of the present disclosure. For example, bank section <NUM> can represent an example section of a number of bank sections to a bank of a memory device (e.g., bank section <NUM>, bank section <NUM>,. , bank section M). As shown in <FIG>, a bank architecture can include a plurality of memory columns <NUM> shown horizontally as X (e.g., <NUM>,<NUM> columns in an example DRAM bank and bank section). Additionally, the bank section <NUM> may be divided into subarray <NUM>, subarray <NUM>,. , and subarray N-<NUM> (e.g., <NUM> subarrays) shown at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>, respectively, that are separated by amplification regions configured to be coupled to a data path, e.g., the shared I/O line described herein. As such, the subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> can each have amplification regions shown <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> that correspond to sensing component stripe <NUM>, sensing component stripe <NUM>,. , and sensing component stripe N-<NUM>, respectively.

Each column <NUM> is configured to be coupled to sensing circuitry <NUM>, as described in connection with <FIG> and elsewhere herein. As such, each column in a subarray can be coupled individually to a sense amplifier and compute component that contribute to a sensing component stripe for that subarray. For example, as shown in <FIG>, the bank architecture can include sensing component stripe <NUM>, sensing component stripe <NUM>,. , sensing component stripe N-<NUM> that each have sensing circuitry <NUM> with sense amplifiers and compute components that can, in various embodiments, be used as registers, cache and data buffering and that are coupled to each column <NUM> in the subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>. The compute component within the sensing circuitry <NUM> coupled to the memory array <NUM>, as shown in <FIG>, can complement the cache <NUM> associated with the controller <NUM>.

Each of the of the subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> can include a plurality of rows <NUM> shown vertically as Y (e.g., each subarray may include <NUM> rows in an example DRAM bank). Example embodiments are not limited to the example horizontal and vertical orientation of columns and rows described herein or the example numbers thereof.

As shown in <FIG>, the bank architecture can be associated with controller <NUM>. The controller <NUM> shown in <FIG> can, in various examples, represent at least a portion of the functionality embodied by and contained in the controller <NUM> shown in <FIG>. The controller <NUM> can direct (e.g., control) input of control signals based on commands and data <NUM> to the bank architecture and output of data from the bank architecture, e.g., to the host <NUM>, along with control of data movement in the bank architecture, as described herein. The bank architecture can include a data bus <NUM> (e.g., a <NUM> bit wide data bus) to DRAM DQs, which can correspond to the data bus <NUM> described in connection with <FIG>.

<FIG> is a block diagram of a bank <NUM> to a memory device in accordance with a number of embodiments of the present disclosure. For example, bank <NUM> can represent an example bank to a memory device (e.g., bank <NUM>, bank <NUM>,. As shown in <FIG>, a bank architecture can include an address/control (A/C) path <NUM>, e.g., a bus, coupled a controller <NUM>. Again, the controller <NUM> shown in <FIG> can, in various examples, represent at least a portion of the functionality embodied by and contained in the controller <NUM> shown in <FIG> and <FIG>.

As shown in <FIG>, a bank architecture can include a plurality of bank sections, e.g., bank section <NUM>, in a particular bank <NUM>. As further shown in <FIG>, a bank section <NUM> can be subdivided into a plurality of subarrays (e.g., subarray <NUM>, subarray <NUM>,. , subarray N-<NUM> shown at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>) respectively separated by sensing component stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>, as shown in <FIG>, that include sensing circuitry and logic circuitry <NUM>/<NUM>, as shown in <FIG> and described further in connection with <FIG>.

As described herein, an I/O line can be selectably shared by a plurality of partitions, subarrays, rows, and particular columns of memory cells via the sensing component stripe coupled to each of the subarrays. For example, the sense amplifier and/or compute component of each of a selectable subset of a number of columns (e.g., eight column subsets of a total number of columns) can be selectably coupled to each of the plurality of shared I/O lines for data values stored (cached) in the sensing component stripe to be moved (e.g., transferred, transported, and/or fed) to each of the plurality of shared I/O lines. Because the singular forms "a", "an", and "the" can include both singular and plural referents herein, "a shared I/O line" can be used to refer to "a plurality of shared I/O lines", unless the context clearly dictates otherwise. Moreover, "shared I/O lines" is an abbreviation of "plurality of shared I/O lines".

As shown schematically in <FIG>, an architecture of a bank <NUM> and each section <NUM> of the bank can include a plurality of shared I/O lines <NUM> (e.g., data path, bus) configured to couple to the plurality of subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> of memory cells of the bank section <NUM> and a plurality of banks (not shown). The shared I/O lines <NUM> can be selectably coupled between subarrays, rows, and particular columns of memory cells via the sensing component stripes represented by <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> shown in <FIG>. As noted, the sensing component stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> each include sensing circuitry <NUM> with sense amplifiers and compute components configured to couple to each column of memory cells in each subarray, as shown in <FIG> and described further in connection with <FIG>.

The shared I/O lines <NUM> can be utilized to increase a speed, rate, and efficiency of data movement in a PIM array, e.g., between subarrays. In at least one embodiment, using the shared I/O lines <NUM> provides an improved data path by providing at least a thousand bit width. In one embodiment, <NUM> shared I/O lines are coupled to <NUM>,<NUM> columns to provide a <NUM> bit width. The illustrated shared I/O lines <NUM> can be formed on pitch with the memory cells of the array.

In some embodiments, the controller <NUM> may be configured to provide instructions (control signals based on commands) and data to a plurality of locations of a particular bank <NUM> in the memory array <NUM> and to the sensing component stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> via the shared I/O lines <NUM> with control and data registers <NUM>. For example, the control and data registers <NUM> can provide instructions to be executed using by the sense amplifiers and the compute components of the sensing circuity <NUM> in the sensing component stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>. <FIG> illustrates an instruction cache <NUM> associated with the controller <NUM> and coupled to a write path <NUM> to each of the subarrays <NUM>-<NUM>,. , <NUM>-N-<NUM> in the bank <NUM>.

Implementations of PIM DRAM architecture may perform processing at the sense amplifier and compute component level. Implementations of PIM DRAM architecture may allow only a finite number of memory cells to be connected to each sense amplifier (e.g., around <NUM> memory cells). A sensing component stripe <NUM> may include from around <NUM>,<NUM> to around <NUM>,<NUM> sense amplifiers. For example, a sensing component stripe <NUM> may be configured to couple to an array of <NUM> rows and around <NUM>,<NUM> columns. A sensing component stripe can be used as a building block to construct the larger memory. In an array for a memory device, there may be <NUM> sensing component stripes, which corresponds to <NUM> subarrays, as described herein. Hence, <NUM> rows times <NUM> sensing component stripes would yield around <NUM>,<NUM> rows intersected by around <NUM>,<NUM> columns to form around a <NUM> gigabit DRAM.

As such, when processing at the sense amplifier level, there are only <NUM> rows of memory cells available to perform logic functions with each other and it may not be possible to easily perform logic functions on multiple rows where data is coupled to different sensing component stripes. To accomplish processing of data in different subarrays coupled to different sensing component stripes, all the data to be processed is moved into the same subarray in order to be coupled to the same sensing component stripe.

However, DRAM implementations have not been utilized to move data from one sensing component stripe to another sensing component stripe. As mentioned, a sensing component stripe can contain as many as <NUM>,<NUM> sense amplifiers, which corresponds to around <NUM>,<NUM> columns or around <NUM>,<NUM> data values, e.g., bits, of data to be stored, e.g., cached, from each row. A DRAM DQ data bus, e.g., as shown at <NUM> in <FIG>, may be configured as a <NUM> bit part. As such, to transfer (move) the entire data from a <NUM>,<NUM> bit row from one sensing component stripe to another sensing component stripe using a DRAM DQ data bus would take, for instance, <NUM> cycles, e.g., <NUM>,<NUM> divided by <NUM>.

In order to achieve data movement conducted with a high speed, rate, and efficiency from one sensing component stripe to another in PIM DRAM implementations, shared I/O lines <NUM> are described herein. For example, with <NUM> shared I/O lines configured as a <NUM> bit wide shared I/O line <NUM>, movement of data from a full row, as just described, would take <NUM> cycles, a <NUM> times increase in the speed, rate, and efficiency of data movement. As such, compared other PIM DRAM implementations (e.g., relative to a <NUM> bit wide data path), utilization of the structures and processes described in the present disclosure saves time for data movement. In various embodiments, time may be saved, for example, by not having to read data out of one bank, bank section, and subarray thereof, storing the data, and then writing the data in another location and/or by reducing the number of cycles for data movement.

<FIG> is a schematic diagram illustrating sensing circuitry <NUM> in accordance with a number of embodiments of the present disclosure. The sensing circuitry <NUM> can correspond to sensing circuitry <NUM> shown in <FIG>.

A memory cell can include a storage element (e.g., capacitor) and an access device (e.g., transistor). For instance, a first memory cell can include transistor <NUM>-<NUM> and capacitor <NUM>-<NUM>, and a second memory cell can include transistor <NUM>-<NUM> and capacitor <NUM>-<NUM>, etc. In this embodiment, the memory array <NUM> is a DRAM array of 1T1C (one transistor one capacitor) memory cells, although other embodiments of configurations can be used (e.g., 2T2C with two transistors and two capacitors per memory cell). In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read).

The cells of the memory array <NUM> can be arranged in rows coupled by access (word) lines <NUM>-X (Row X), <NUM>-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., digit lines DIGIT(D) and DIGIT(D)_ shown in <FIG> and DIGIT_0 and DIGIT_0* shown in <FIG> and <FIG>). The individual sense lines corresponding to each pair of complementary sense lines can also be referred to as digit lines <NUM>-<NUM> for DIGIT (D) and <NUM>-<NUM> for DIGIT (D)_, respectively, or corresponding reference numbers in <FIG> and <FIG>. Although only one pair of complementary digit lines are shown in <FIG>, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and digit lines (e.g., <NUM>,<NUM>, <NUM>,<NUM>, <NUM>,<NUM>, etc.).

Memory cells can be coupled to different digit lines and word lines. For example, a first source/drain region of a transistor <NUM>-<NUM> can be coupled to digit line <NUM>-<NUM> (D), a second source/drain region of transistor <NUM>-<NUM> can be coupled to capacitor <NUM>-<NUM>, and a gate of a transistor <NUM>-<NUM> can be coupled to word line <NUM>-Y. A first source/drain region of a transistor <NUM>-<NUM> can be coupled to digit line <NUM>-<NUM> (D)_, a second source/drain region of transistor <NUM>-<NUM> can be coupled to capacitor <NUM>-<NUM>, and a gate of a transistor <NUM>-<NUM> can be coupled to word line <NUM>-X. A cell plate, as shown in <FIG>, can be coupled to each of capacitors <NUM>-<NUM> and <NUM>-<NUM>. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.

The memory array <NUM> is configured to couple to sensing circuitry <NUM> in accordance with a number of embodiments of the present disclosure. In this embodiment, the sensing circuitry <NUM> comprises a sense amplifier <NUM> and a compute component <NUM> corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary digit lines). The sense amplifier <NUM> can be coupled to the pair of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM>. The compute component <NUM> can be coupled to the sense amplifier <NUM> via pass gates <NUM>-<NUM> and <NUM>-<NUM>. The gates of the pass gates <NUM>-<NUM> and <NUM>-<NUM> can be coupled to operation selection logic <NUM>.

The operation selection logic <NUM> can be configured to include pass gate logic for controlling pass gates that couple the pair of complementary digit lines un-transposed between the sense amplifier <NUM> and the compute component <NUM> and swap gate logic for controlling swap gates that couple the pair of complementary digit lines transposed between the sense amplifier <NUM> and the compute component <NUM>. The operation selection logic <NUM> can also be coupled to the pair of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM>. The operation selection logic <NUM> can be configured to control continuity of pass gates <NUM>-<NUM> and <NUM>-<NUM> based on a selected operation.

The sense amplifier <NUM> can be operated to determine a data value (e.g., logic state) stored in a selected memory cell. The sense amplifier <NUM> can comprise a cross coupled latch, which can be referred to herein as a primary latch. In the example illustrated in <FIG>, the circuitry corresponding to sense amplifier <NUM> comprises a latch <NUM> including four transistors coupled to a pair of complementary digit lines D <NUM>-<NUM> and (D)_ <NUM>-<NUM>. However, embodiments are not limited to this example. The latch <NUM> can be a cross coupled latch, e.g., gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) <NUM>-<NUM> and <NUM>-<NUM> are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) <NUM>-<NUM> and <NUM>-<NUM>). The cross coupled latch <NUM> comprising transistors <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> can be referred to as a primary latch.

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the digit lines <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ will be slightly greater than the voltage on the other one of digit lines <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_. An ACT signal and an RNL* signal can be driven low to enable (e.g., fire) the sense amplifier <NUM>. The digit lines <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ having the lower voltage will turn on one of the PMOS transistor <NUM>-<NUM> or <NUM>-<NUM> to a greater extent than the other of PMOS transistor <NUM>-<NUM> or <NUM>-<NUM>, thereby driving high the digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ having the higher voltage to a greater extent than the other digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ is driven high.

Similarly, the digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ having the higher voltage will turn on one of the NMOS transistor <NUM>-<NUM> or <NUM>-<NUM> to a greater extent than the other of the NMOS transistor <NUM>-<NUM> or <NUM>-<NUM>, thereby driving low the digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ having the lower voltage to a greater extent than the other digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ is driven low. As a result, after a short delay, the digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ having the slightly greater voltage is driven to the voltage of the supply voltage VCC through a source transistor, and the other digit line <NUM>-<NUM> (D) or <NUM>-<NUM> (D)_ is driven to the voltage of the reference voltage (e.g., ground) through a sink transistor. Therefore, the cross coupled NMOS transistors <NUM>-<NUM> and <NUM>-<NUM> and PMOS transistors <NUM>-<NUM> and <NUM>-<NUM> serve as a sense amplifier pair, which amplify the differential voltage on the digit lines <NUM>-<NUM> (D) and <NUM>-<NUM> (D)_ and operate to latch a data value sensed from the selected memory cell. As used herein, the cross coupled latch of sense amplifier <NUM> may be referred to as a primary latch <NUM>.

Embodiments are not limited to the sense amplifier <NUM> configuration illustrated in <FIG>. As an example, the sense amplifier <NUM> can be a current-mode sense amplifier and a single-ended sense amplifier (e.g., sense amplifier coupled to one digit line). Also, embodiments of the present disclosure are not limited to a folded digit line architecture such as that shown in <FIG>.

The sense amplifier <NUM> can, in conjunction with the compute component <NUM>, be operated to perform various operations using data from an array as input. In a number of embodiments, the result of an operation can be stored back to the array without transferring the data via a digit line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across local and global I/O lines in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased (e.g., faster) processing capability as compared to previous approaches.

The sense amplifier <NUM> can further include equilibration circuitry <NUM>, which can be configured to equilibrate the digit lines <NUM>-<NUM> (D) and <NUM>-<NUM> (D)_. In this example, the equilibration circuitry <NUM> comprises a transistor <NUM> coupled between digit lines <NUM>-<NUM> (D) and <NUM>-<NUM> (D)_. The equilibration circuitry <NUM> also comprises transistors <NUM>-<NUM> and <NUM>-<NUM> each having a first source/drain region coupled to an equilibration voltage (e.g., VDD/<NUM>), where VDD is a supply voltage associated with the array. A second source/drain region of transistor <NUM>-<NUM> can be coupled digit line <NUM>-<NUM> (D), and a second source/drain region of transistor <NUM>-<NUM> can be coupled digit line <NUM>-<NUM> (D)_. Gates of transistors <NUM>, <NUM>-<NUM>, and <NUM>-<NUM> can be coupled together, and to an equilibration (EQ) control signal line <NUM>. As such, activating EQ enables the transistors <NUM>, <NUM>-<NUM>, and <NUM>-<NUM>, which effectively shorts digit lines <NUM>-<NUM> (D) and <NUM>-<NUM> (D)_ together and to the equilibration voltage (e.g., VCC/<NUM>).

Although <FIG> shows sense amplifier <NUM> comprising the equilibration circuitry <NUM>, embodiments are not so limited, and the equilibration circuitry <NUM> may be implemented discretely from the sense amplifier <NUM>, implemented in a different configuration than that shown in <FIG>, or not implemented at all.

As described further below, in a number of embodiments, the sensing circuitry <NUM> (e.g., sense amplifier <NUM> and compute component <NUM>) can be operated to perform a selected operation and initially store the result in one of the sense amplifier <NUM> or the compute component <NUM> without transferring data from the sensing circuitry via a local or global I/O line (e.g., without performing a sense line address access via activation of a column decode signal, for instance).

Performance of logical operations (e.g., Boolean logical functions involving data values) is fundamental and commonly used. Boolean logic functions are used in many higher level functions. Consequently, speed and power efficiencies that can be realized with improved logical operations, can translate into speed and power efficiencies of higher order functionalities.

As shown in <FIG>, the compute component <NUM> can also comprise a latch, which can be referred to herein as a secondary latch <NUM>. The secondary latch <NUM> can be configured and operated in a manner similar to that described above with respect to the primary latch <NUM>, with the exception that the pair of cross coupled p-channel transistors (e.g., PMOS transistors) included in the secondary latch can have their respective sources coupled to a supply voltage (e.g., VDD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch can have their respective sources selectively coupled to a reference voltage (e.g., ground), such that the secondary latch is continuously enabled. The configuration of the compute component <NUM> is not limited to that shown in <FIG>, and various other embodiments are feasible.

<FIG> is a schematic diagram illustrating circuitry for data movement to a memory device in accordance with a number of embodiments of the present disclosure. <FIG> shows eight sense amplifiers, e.g., sense amplifiers <NUM>, <NUM>,. , <NUM> shown at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>, respectively, each coupled to a pair of complementary sense lines, e.g., digit lines <NUM>-<NUM> and <NUM>-<NUM>. <FIG> also shows eight compute components, e.g., compute components <NUM>, <NUM>,. , <NUM> shown at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>, each coupled to a sense amplifier, e.g., as shown for sense amplifier <NUM><NUM>-<NUM>, via pass gates and digit lines <NUM>-<NUM> and <NUM>-<NUM>. For example, the pass gates can be connected as shown in <FIG> and can be controlled by an operation selection signal, Pass. For example, an output of the selection logic can be coupled to the gates of the pass gates and digit lines <NUM>-<NUM> and <NUM>-<NUM>. Corresponding pairs of the sense amplifiers and compute components can contribute to formation of the sensing circuitry indicated at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>,.

Data values present on the pair of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM> can be loaded into the compute component <NUM>-<NUM> as described in connection with <FIG>. For example, when the pass gates are open, data values on the pair of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM> can be passed from the sense amplifiers to the compute component, e.g., <NUM>-<NUM> to <NUM>-<NUM>. The data values on the pair of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM> can be the data value stored in the sense amplifier <NUM>-<NUM> when the sense amplifier is fired.

The sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> in <FIG> can each correspond to sense amplifier <NUM> shown in <FIG>. The compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> shown in <FIG> can each correspond to compute component <NUM> shown in <FIG>. A combination of one sense amplifier with one compute component can contribute to the sensing circuitry, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>, of a portion of a DRAM memory subarray <NUM> configured to couple to a shared I/O line <NUM>, as described herein. The paired combinations of the sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> and the compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>, shown in <FIG>, can be included in a sensing component stripe, as shown at <NUM> in <FIG> and at <NUM> in <FIG> and <FIG>.

The configurations of embodiments illustrated in <FIG> are shown for purposes of clarity and are not limited to these configurations. For instance, the configuration illustrated in <FIG> for the sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> in combination with the compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> and the shared I/O line <NUM> is not limited to half the combination of the sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> with the compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM> of the sensing circuitry being formed above the columns <NUM> of memory cells (not shown) and half being formed below the columns <NUM> of memory cells. Nor are the number of such combinations of the sense amplifiers with the compute components forming the sensing circuitry configured to couple to a shared I/O line limited to eight. In addition, the configuration of the shared I/O line <NUM> is not limited to being split into two for separately coupling each of the two sets of complementary digit lines <NUM>-<NUM> and <NUM>-<NUM>, nor is the positioning of the shared I/O line <NUM> limited to being in the middle of the combination of the sense amplifiers and the compute components forming the sensing circuitry, e.g., rather than being at either end of the combination of the sense amplifiers and the compute components.

The circuitry illustrated in <FIG> also shows column select circuitry <NUM>-<NUM>, <NUM>-<NUM> that is configured to implement data movement operations on particular columns <NUM> of a subarray <NUM> and the complementary digit lines <NUM>-<NUM> and <NUM>-<NUM> thereof (e.g., as directed by the controller <NUM> shown in <FIG>), coupling sensed data values to the shared I/O line <NUM>. For example, column select circuitry <NUM>-<NUM> has select lines <NUM>, <NUM>, <NUM>, and <NUM> that are configured to couple with corresponding columns, such as column <NUM> (<NUM>-<NUM>), column <NUM>, column <NUM>, and column <NUM>. Column select circuitry <NUM>-<NUM> has select lines <NUM>, <NUM>, <NUM>, and <NUM> that are configured to couple with corresponding columns, such as column <NUM>, column <NUM>, column <NUM>, and column <NUM>.

Controller <NUM> can be coupled to column select circuitry <NUM> to control select lines, e.g., select line <NUM>, to access data values stored in the sense amplifiers, compute components and/or present on the pair of complementary digit lines, e.g., <NUM>-<NUM> and <NUM>-<NUM> when selection transistors <NUM>-<NUM>, <NUM>-<NUM> are enabled via signals from column select line <NUM>. Opening the selection transistors <NUM>-<NUM>, <NUM>-<NUM> (e.g., as directed by the controller <NUM>) enables coupling of sense amplifier <NUM><NUM>-<NUM> and compute component <NUM><NUM>-<NUM> to couple with complementary digit lines <NUM>-<NUM> and <NUM>-<NUM> of column <NUM> (<NUM>-<NUM>) to move data values on digit line <NUM> and digit line <NUM>* for a particular row <NUM> stored in sense amplifier <NUM>-<NUM> and/or compute component <NUM>-<NUM>. Data values from rows in each of columns <NUM> through <NUM> can similarly be selected by controller <NUM> coupling, via an appropriate select line, a particular combination of a sense amplifier and a compute component with a pair of complementary digit lines by opening the appropriate selection transistors.

Moreover, opening the selection transistors, e.g., selection transistors <NUM>-<NUM>, <NUM>-<NUM>, enables a particular sense amplifier and/or compute component, e.g., <NUM>-<NUM> and/or <NUM>-<NUM>, to be coupled with a shared I/O line <NUM> such that the sensed (stored) data values can be placed on, e.g., transferred to, the shared I/O line <NUM>. In some embodiments, one column at a time is selected, e.g., column <NUM><NUM>-<NUM>, to be coupled to a particular shared I/O line <NUM> to move, e.g., transfer, the sensed data values. In the example configuration of <FIG>, the shared I/O line <NUM> is illustrated as a shared, differential I/O line pair, e.g., shared I/O line and shared I/O line*. Hence, selection of column <NUM><NUM>-<NUM> could yield two data values (e.g., two bits with values of <NUM> and/or <NUM>) from a row, e.g., <NUM>, stored in the sense amplifier and/or compute component associated with complementary digit lines <NUM>-<NUM> and <NUM>-<NUM>. These data values could be input in parallel to each of the shared, differential I/O pair, shared I/O and shared I/O*, of the shared differential I/O line <NUM>.

According to various embodiments of the present disclosure, a memory device, e.g., <NUM> in <FIG>, can be configured to couple to a host, e.g., <NUM>, via a data bus, e.g., <NUM>, and a control bus, e.g., <NUM>. A bank section in the memory device, e.g., <NUM> in <FIG>, can include an array of memory cells, e.g., <NUM> in <FIG>, and sensing circuitry, e.g., <NUM> in <FIG>, coupled to the array via a plurality of sense lines, e.g., <NUM>-<NUM> and <NUM>-<NUM> in <FIG> and at corresponding reference numbers in <FIG>, <FIG> and <FIG>. The sensing circuitry can include a sense amplifier and a compute component, e.g., <NUM> and <NUM>, respectively, in <FIG> and at corresponding reference numbers in <FIG>, <FIG> and <FIG>, coupled to a sense line and configured to implement operations on pitch with the array, as described herein. A controller, e.g., <NUM>, in the memory device can be configured to couple to the array and sensing circuitry. A shared I/O line (e.g., <NUM> in <FIG>, <NUM> in <FIG>, and <NUM>-<NUM> and <NUM>-M in <FIG> and <FIG>) in the memory device can be configured to couple a source location, e.g., subarray <NUM> (<NUM>-<NUM>) in <FIG> and <FIG>, and a destination location, e.g., subarray N-<NUM> (<NUM>-N-<NUM>) in <FIG> and <FIG>, between a pair of bank section locations.

As described herein, the array of memory cells can include an implementation of DRAM memory cells where the controller is configured, in response to a command, to use DRAM logical and electrical interfaces to move data from the source location to the destination location via a shared I/O line. According to various embodiments, the source location can be in a first bank and the destination location can be in a second bank in the memory device and the source location can be in a first subarray of one bank in the memory device and the destination location can be in a second subarray of the same bank. According to various embodiments, the first subarray and the second subarray can be in the same section of the bank or the subarrays can be in different sections of the bank.

According to various embodiments described herein, the apparatus can be configured to move data from a source location, including a particular row (e.g., <NUM> in <FIG>) and column address associated with a first number of sense amplifier and compute component, e.g., <NUM>-<NUM> and <NUM>-<NUM>, respectively, in subarray <NUM> (<NUM>-<NUM>), to a shared I/O line, e.g., <NUM>-<NUM>. In addition, the apparatus can be configured to move the data to a destination location, including a particular row and column address associated with a second number of sense amplifier and compute component, e.g., <NUM>-<NUM> and <NUM>-<NUM>, respectively, in subarray N-<NUM> (<NUM>-N-<NUM>), using the shared I/O line, e.g., <NUM>-<NUM>. As the reader will appreciate, each shared I/O line, e.g., <NUM>-<NUM>, can actually include a complementary pair of shared I/O lines, e.g., shared I/O line and shared I/O line* as shown in the example configuration of <FIG>. In some embodiments described herein, <NUM> shared I/O lines, e.g., complementary pairs of shared I/O lines, can be configured as a <NUM> bit wide shared I/O line.

<FIG> and <FIG> provide another schematic diagram illustrating circuitry for data movement in a memory device in accordance with a number of embodiments of the present disclosure. As illustrated in <FIG> and shown in more detail in <FIG> and <FIG>, a bank section of a DRAM memory device can include a plurality of subarrays, which are indicated in <FIG> and <FIG> at <NUM>-<NUM> as subarray <NUM> and at <NUM>-N-<NUM> as subarray N-<NUM>.

<FIG>, which are to be considered as horizontally connected, illustrate that each subarray, e.g., subarray <NUM><NUM>-<NUM> partly shown in <FIG> and partly shown in <FIG>, can have a number of associated sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM> and compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM>. For example, each subarray, <NUM>-<NUM>,. , <NUM>-N-<NUM>, can have one or more associated sensing component stripes (e.g., <NUM>-<NUM>,. , <NUM>-N in <FIG>). According to embodiments described herein, each subarray, <NUM>-<NUM>,. , <NUM>-N-<NUM>, can be split into portions <NUM>-<NUM> (shown in <FIG>), <NUM>-<NUM>,. , <NUM>-M (shown in <FIG>). The portions <NUM>-<NUM>,. , <NUM>-M may be defined by configuring a predetermined number of the sense amplifiers and compute components (e.g., sensing circuitry <NUM>), along with the corresponding columns, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-<NUM>, among columns <NUM>-<NUM>,. , <NUM>-X-<NUM> to a given shared I/O line, e.g., <NUM>-M. Corresponding pairs of the sense amplifiers and compute components can contribute to formation of the sensing circuitry indicated at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM> in <FIG>.

In some embodiments, as shown in <FIG>, <FIG> and <FIG>, the predetermined number of the sense amplifiers and compute components, along with the corresponding columns, configured per shared I/O line, can be eight. The number of portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M of the subarray can be the same as the number of shared I/O lines <NUM>-<NUM>, <NUM>, <NUM>,. , <NUM>-M configured to couple to the subarray. The subarrays can be arranged according to various dynamic random access memory (DRAM) architectures for coupling shared I/O lines <NUM>-<NUM>, <NUM>, <NUM>,. , <NUM>-M between subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>.

For example, portion <NUM>-<NUM> of subarray <NUM><NUM>-<NUM> in <FIG> can correspond to the portion of the subarray illustrated in <FIG>. As such, sense amplifier <NUM><NUM>-<NUM> and compute component <NUM><NUM>-<NUM> can be coupled to column <NUM>-<NUM>. As described herein, a column can be configured to include a pair of complementary digit lines referred to as digit line <NUM> and digit line <NUM>*. However, alternative embodiments can include a single digit line <NUM>-<NUM> (sense line) for a single column of memory cells. Embodiments are not so limited.

As illustrated in <FIG> and shown in more detail in <FIG>, a sensing component stripe can, in various embodiments, extend from one end of a subarray to an opposite end of the subarray. For example, as shown for subarray <NUM> (<NUM>-<NUM>), sensing component stripe <NUM> (<NUM>-<NUM>, shown schematically above and below DRAM columns in a folded sense line architecture) can include and extend from sense amplifier <NUM> (<NUM>-<NUM>) and compute component <NUM> (<NUM>-<NUM>) in portion <NUM>-<NUM> to sense amplifier X-<NUM> (<NUM>-X-<NUM>) and compute component X-<NUM> (<NUM>-X-<NUM>) in portion <NUM>-M of subarray <NUM> (<NUM>-<NUM>).

As described in connection with <FIG>, the configuration illustrated in <FIG> for the sense amplifiers <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM> in combination with the compute components <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM> and shared I/O line <NUM> (<NUM>-<NUM>) through shared I/O line M-<NUM> (<NUM>-M) is not limited to half the combination of the sense amplifiers with the compute components of the sensing circuitry, e.g., <NUM>, being formed above the columns of memory cells and half being formed below the columns of memory cells <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-X-<NUM> in a folded DRAM architecture. For example, in various embodiments, a sensing component stripe <NUM> for a particular subarray <NUM> can be formed with any number of the sense amplifiers and compute components of the sensing amplifier stripe being formed above and below the columns of memory cells. Accordingly, in some embodiments as illustrated in <FIG>, all of the sense amplifiers and compute components of the sensing circuitry and corresponding sensing amplifier stripes can be formed above or below the columns of memory cells.

As described in connection with <FIG>, each subarray can have column select circuitry, e.g., <NUM>, that is configured to implement data movement operations on particular columns <NUM> of a subarray, such as subarray <NUM> (<NUM>-<NUM>), and the complementary digit lines thereof, coupling stored data values from the sense amplifiers <NUM> and/or compute components <NUM> to given shared I/O lines <NUM>-<NUM>,. , <NUM>-M, e.g., complementary shared I/O lines <NUM> in <FIG>. For example, the controller <NUM> can direct that data values of memory cells in a particular row, e.g., row <NUM>, of subarray <NUM> (<NUM>-<NUM>) be sensed and moved to a same or different numbered row of subarray N-<NUM> (<NUM>-N-<NUM>) in a same or different numbered column, e.g., different portion of the two subarrays (e.g., not necessarily from portion <NUM>-<NUM> of subarray <NUM> to portion <NUM>-<NUM> of subarray N-<NUM>). For example, in some embodiments data values may be moved from a column in portion <NUM>-<NUM> to a column in portion <NUM>-M using shifting techniques.

The column select circuitry, e.g., <NUM> in <FIG>, can direct movement, e.g., sequential movement, of each of the eight columns, e.g., digit/digit*, in the portion, e.g., <NUM>-<NUM>, of the subarray, e.g., <NUM>-<NUM>, for a particular row such that the sense amplifiers and compute components of the sensing component stripe, e.g., <NUM>-<NUM>, for that portion can store (cache) and move all data values to the shared I/O line in a particular order, e.g., in an order in which the columns were sensed. With complementary digit lines, digit/digit*, and complementary shared I/O lines <NUM>, for each of eight columns, there can be <NUM> data values (e.g., bits) sequenced to the shared I/O line from one portion of the subarray such that one data value (e.g., bit) is input to each of the complementary shared I/O lines at a time from each of the sense amplifiers and compute components.

As such, with <NUM> portions of subarrays each having eight columns (e.g., subarray portion <NUM>-<NUM> of each of subarrays <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>), and each configured to couple to a different shared I/O line, e.g., <NUM>-<NUM> through <NUM>-M, <NUM> data values (e.g., bits) could be moved to the plurality of shared I/O lines at substantially the same point in time, e.g., in parallel. Accordingly, the present disclosure describes configuring the plurality of shared I/O lines to be at least a thousand bits wide (e.g., <NUM> bits wide) to increase the speed, rate, and efficiency of data movement in a DRAM implementation (e.g., relative to a <NUM> bit wide data path).

As illustrated in <FIG>, in each subarray, e.g., subarray <NUM><NUM>-<NUM>, one or more multiplexers <NUM>-<NUM>, <NUM>-<NUM> can be coupled to the sense amplifiers and compute components of each portion <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M of the sensing component stripe <NUM>-<NUM> for the subarray. The multiplexers <NUM>-<NUM>, <NUM>-<NUM> can be configured to access, select, receive, coordinate, combine, and transport the data values (e.g., bits) stored (cached) by the number of selected sense amplifiers and compute components in a portion (e.g., portion <NUM>-<NUM>) of the subarray to be input to the shared I/O line (e.g., shared I/O line <NUM><NUM>-<NUM>). As such, a shared I/O line, as described herein, can be configured to couple a source location and a destination location between a pair of bank section locations for improved data movement.

According to various embodiments of the present disclosure, a controller, e.g., <NUM>, can be coupled to a bank of a memory device, e.g., <NUM>, to execute a command to move data in the bank from a source location, e.g., subarray <NUM><NUM>-<NUM>, to a destination location, e.g., subarray N-<NUM><NUM>-N-<NUM>. A bank section can, in various embodiments, include a plurality of subarrays of memory cells in the bank section, e.g., subarrays <NUM>-<NUM> through <NUM>-N-<NUM> and <NUM>-<NUM> through <NUM>-N-<NUM>. The bank section can, in various embodiments, further include sensing circuitry, e.g., <NUM>, coupled to the plurality of subarrays via a plurality of columns, e.g., <NUM>-<NUM> and <NUM>-<NUM> and <NUM>-<NUM>, of the memory cells. The sensing circuitry can include a sense amplifier and a compute component, e.g., <NUM> and <NUM>, respectively, in <FIG> and at corresponding reference numbers in <FIG>, <FIG> and <FIG>, coupled to each of the columns and configured to implement the command to move the data.

The bank section can, in various embodiments, further include a shared I/O line, e.g., <NUM>, <NUM>, and <NUM>-<NUM> and <NUM>-M, to couple the source location and the destination location to move the data. In addition, the controller can be configured to couple to the plurality of subarrays and to the sensing circuitry to perform a data write operation on the moved data to the destination location, e.g., in the bank section.

As such, the controller <NUM> can be configured to direct writing of the data, moved via the shared I/O lines, to particular memory cells in the destination location, e.g., to memory cells in a particular row of a subarray. Performing a data write operation as such on the moved data can be in addition to the alternative pathway, e.g., as shown in <FIG>, of the controller <NUM> being configured to direct writing of data to the memory array <NUM>, where the data is transferred from the host <NUM> over the data bus <NUM> (e.g., a <NUM> bit wide data bus) via the I/O circuitry <NUM> and the write circuitry <NUM>.

According to various embodiments, the apparatus can include a sensing component stripe, e.g., <NUM> and <NUM>, configured to include a number of a plurality of sense amplifiers and compute components that corresponds to a number of the plurality of columns of the memory cells, e.g., where each column of memory cells is configured to couple to a sense amplifier and a compute component. The number of a plurality of sensing component stripes in the bank section, e.g., <NUM>-<NUM> through <NUM>-N-<NUM>, can correspond to a number of a plurality of subarrays in the bank section, e.g., <NUM>-<NUM> through <NUM>-N-<NUM>.

The number of sense amplifiers and compute components can be configured to be selectably, e.g., sequentially, coupled to the shared I/O line, e.g., as shown by column select circuitry at <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in <FIG>. The column select circuitry can be configured to selectably sense data in a particular column of memory cells of a subarray by being selectably coupled to, for example, eight sense amplifiers and compute components in the source location, e.g., as shown in subarray <NUM> in <FIG> and subarray portions <NUM>-<NUM> through <NUM>-M in <FIG>. As such, the eight sense amplifiers and compute components in the source location can be configured to sequentially couple to the shared I/O line. According to the embodiments described herein, a number of shared I/O lines formed in the array can be configured by division of a number of columns in the array by the eight sense amplifiers and compute components coupled to each of the shared I/O lines. For example, when there are <NUM>,<NUM> columns in the array (e.g., bank section), or in each subarray thereof, and one sense amplifier and compute component per column, <NUM>,<NUM> columns divided by eight yields <NUM> shared I/O lines.

The apparatus can, in various embodiments, include a number of multiplexers, e.g., as shown at <NUM>-<NUM> and <NUM>-<NUM> in portions <NUM>-<NUM> through <NUM>-M of various subarrays in <FIG>. As such, according to various embodiments, the apparatus can include a plurality of sense amplifiers and compute components and a multiplexer to select a sense amplifier and a compute component to couple to the shared I/O line. The multiplexers can be formed between the sense amplifiers and compute components and the shared I/O line to access, select, receive, coordinate, combine, and transport selected data to be input to the coupled shared I/O line.

According to various embodiments described herein, an array of memory cells can include a column of memory cells having a pair of complementary sense (digit) lines, e.g., <NUM>-<NUM> and <NUM>-<NUM> in <FIG>. The sensing circuitry can, in some embodiments, include a sense amplifier, e.g., <NUM>-<NUM>, selectably coupled to each of the pair of complementary sense (digit) lines and a compute component, e.g., <NUM>-<NUM>, coupled to the sense amplifier via pass gates, e.g., <NUM>-<NUM>, <NUM>-<NUM>.

According to some embodiments, a source sensing component stripe, e.g., <NUM> and <NUM>, can include a number of sense amplifiers and compute components that can be selected and configured to send an amount of data, e.g., a number of bits, sensed from a row of the source location in parallel to a plurality of shared I/O lines. For example, in response to control signals for sequential sensing through the column select circuitry, the memory cells of selected columns of a row of the subarray can sense and store (cache) an amount of data, e.g., the number of bits, until that amount reaches a threshold and then send the data via the plurality of shared I/O lines. In some embodiments, the threshold amount of data can correspond to the at least a thousand bit width of the plurality of shared I/O lines.

In some embodiments, the source sensing component stripe can include a number of sense amplifiers and compute components that can be selected and configured to store data, e.g., bits, sensed from a row of the source location when an amount of sensed data, e.g., the number of data bits, exceeds the at least a thousand bit width of the plurality of shared I/O lines. In this embodiment, the source sensing component stripe can be configured to send the data sensed from the row of the source location when coupled to the plurality of shared I/O lines as a plurality of subsets. For example, the amount of at least a first subset of the data can correspond to the at least a thousand bit width of the plurality of shared I/O lines.

The controller can, as described herein, be configured to move the data from a selected row and a selected sense line in the source location to a selected row and a selected sense line in the destination location via the shared I/O line, e.g., in response to control signals from the controller <NUM>. According to various embodiments, a selected row and a selected sense line in the source location (e.g., a first subarray) input to the controller can be different from a selected row and a selected sense line in the destination location (e.g., a second subarray).

As described herein, a location of the data in memory cells of the selected row and the selected sense line in a source subarray can be different from a location of the data moved to memory cells of a selected row and the selected source line in a destination subarray. For example, the source location may be a particular row and digit lines of portion <NUM>-<NUM> of subarray <NUM><NUM>-<NUM> in <FIG> and the destination may be a different row and digit lines of portion <NUM>-M in subarray N-<NUM><NUM>-N-<NUM> in <FIG>.

According to embodiments herein, a destination sensing component stripe, e.g., <NUM> and <NUM>, can be the same as a source sensing component stripe. For example, a plurality of sense amplifiers and compute components can be selected and configured, e.g., depending on the control signal from the controller, to selectably send sensed data to the coupled shared I/O line and selectably receive the data from one of a plurality of coupled shared I/O lines, e.g., to be moved to the destination location. Selection of sense amplifiers and compute components in the destination sensing component stripe can be performed using the column select circuitry described herein, e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in <FIG>.

The controller can, according to some embodiments, be configured to write an amount of data, e.g., a number of data bits, selectably received by the plurality of selected sense amplifiers and compute components in the destination sensing component stripe to a selected row and a selected sense line of the destination location in the destination subarray. In some embodiments, the amount of data to write corresponds to the at least a thousand bit width of a plurality of shared I/O lines.

The destination sensing component stripe can, according to some embodiments, include a plurality of selected sense amplifiers and compute components configured to store received data, e.g., bits, when an amount of received data, e.g., number of data bits, exceeds the at least a thousand bit width of the plurality of shared I/O lines. The controller can, according to some embodiments, be configured to write the stored data, e.g., the number of data bits, to a selected row and a plurality of selected sense lines in the destination location as a plurality of subsets. In some embodiments, the amount of data of at least a first subset of the written data can correspond to the at least a thousand bit width of the plurality of shared I/O lines. According to some embodiments, the controller can be configured to write the stored data, e.g., the number of data bits, to the selected row and the selected sense line in the destination location as a single set, e.g., not as subsets of data.

Embodiments of the present disclosure provide a method to increase a speed, rate, and efficiency of data movement in a PIM array by using an improved data path, e.g., a shared I/O line of a DRAM implementation. According to various embodiments as described herein, a source location and a destination location in a pair of bank locations in a memory device can be configured to couple via a plurality of shared I/O lines. A bank in the memory device can, as described herein, include an array of memory cells, sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and compute components configured to implement operations, and a controller coupled to the array and the sensing circuitry.

The method can include receiving a control signal from the controller to move data from the source location to the destination location, e.g., of a DRAM array of the memory cells. The method can further include moving the data from the source location to the destination location, e.g., of the DRAM array, using the sense amplifiers and compute components via the plurality of shared I/O lines.

In some embodiments, the method can include configuring <NUM> shared I/O lines as a <NUM> bit wide shared I/O line. According to some embodiments, a number of cycles for moving the data from a first row in the source location to a second row in the destination location can be configured by dividing a number of columns in the array intersected by a row of memory cells in the array by the <NUM> bit width of the plurality of shared I/O lines. For example, an array, e.g., a bank, a bank section, and a subarray thereof, can have <NUM>,<NUM> columns, which can correspond to <NUM>,<NUM> data values in a row, which when divided by the <NUM> bit width of the plurality of shared I/O lines intersecting the row can yield eight cycles, each separate cycle being at substantially the same point in time, e.g., in parallel, for movement of all the data in the row. Alternatively or in addition, a bandwidth for moving the data from a first row in the source location to a second row in the destination location can be configuring by dividing the number of columns in the array intersected by the row of memory cells in the array by the <NUM> bit width of the plurality of shared I/O lines and multiplying the result by a clock rate of the controller. In some embodiments, determining a number of data values in a row of the array can be based upon the plurality of sense (digit) lines in the array.

A source location in a first subarray of memory cells can be configured to couple via a plurality of shared I/O lines to a destination location in a second subarray of memory cells, where the plurality of shared I/O lines can be configured as at least a thousand bit wide shared I/O line. The method can include configuring a first sensing component stripe, e.g., <NUM>-<NUM>, for the first subarray, e.g., <NUM>-<NUM>, and second sensing component stripe, e.g., <NUM>-N-<NUM>, for second subarray, e.g., <NUM>-N-<NUM>, to include a sense amplifier and a compute component, e.g., <NUM>-<NUM> and <NUM>-<NUM>, respectively, coupled to each corresponding column of memory cells in the first and second subarrays, e.g., <NUM>-<NUM> through <NUM>-X-<NUM>. A controller can be configured to couple to the memory cells of the first and second subarrays and the first and second sensing component stripes, e.g., via the column select circuitry <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>.

The method can include moving the data from the source location in the first subarray via the plurality of shared I/O lines to the destination location in the second subarray using the first sensing component stripe for the first subarray and the second sensing component stripe for the second subarray. The first amplifier stripe for the first subarray and the second sensing component stripe for the second subarray can, accordingly to various embodiment, be configured to couple to the plurality of shared I/O lines, e.g., via the column select circuitry <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in <FIG> and the multiplexers <NUM>-<NUM> and <NUM>-<NUM> in <FIG>.

According to some embodiments, the source location in the first subarray and the destination location in the second subarray can be in a single bank section of a memory device, e.g., as shown in <FIG> and <FIG>. Alternatively or in addition, the source location in the first subarray and the destination location in the second subarray can be in separate banks and bank sections of the memory device coupled to a plurality of shared I/O lines. In some embodiments, movement of data between two separate banks can include a number of intermediate registers (not shown) coupled to the plurality of shared I/O lines between the two banks in order to temporarily hold, e.g., to perform cache and/or data buffering functions, the moved data. Temporarily holding the moved data as such may resolve timing issues, e.g., with control signals, synchronization of data movement, etc., with movement of the data between the two banks using the shared I/O lines. As such, the method can include moving the data, e.g., in parallel, from the first sensing component stripe for the first subarray via the plurality of shared I/O lines to the second sensing component stripe for the second subarray.

The method can, according to various embodiments, include configuring a sensing component stripe, e.g., all sensing component stripes <NUM>-<NUM> through <NUM>-N-<NUM>, in each of a plurality of subarrays, e.g., subarrays <NUM>-<NUM> through <NUM>-N-<NUM>, to couple to the plurality of shared I/O lines, e.g., shared I/O line <NUM>-<NUM>. In some embodiments, the method can include coupling only one of eight columns of complementary sense lines at a time in the first subarray to one of the plurality of shared I/O lines using the first sensing component stripe, e.g., sensing component stripe <NUM>-<NUM>, and coupling only one of eight columns of complementary sense lines at a time in the second subarray to one of the plurality of shared I/O lines using the second sensing component stripe, e.g., sensing component stripes <NUM>-N-<NUM>.

The method can include moving the data from a number of sense amplifiers and compute components of the first sensing component stripe via the plurality of shared I/O lines to a corresponding number of sense amplifiers and compute components of the second sensing component stripe. For example, the data sensed from each sense amplifier and compute component of the source location can be moved to a corresponding sense amplifier and compute component in the destination location.

According to various embodiments, the method can include the controller selecting, e.g., opening, a first row of memory cells, which corresponds to the source location, for the first sensing component stripe to sense data stored therein, coupling, e.g., opening, the plurality of shared I/O lines to the first sensing component stripe, and coupling, e.g., opening, the second sensing component stripe to the plurality of shared I/O lines, e.g., via the column select circuitry <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> and the multiplexers <NUM>-<NUM> and <NUM>-<NUM>. As such, the method can include moving the data in parallel from the first sensing component stripe to the second sensing component stripe via the plurality of shared I/O lines. The method can include the first sensing component stripe storing, e.g., caching, the sensed data and the second sensing component stripe storing, e.g., caching, the moved data.

The method can include the controller selecting, e.g., opening, a second row of memory cells, which corresponds to the destination location, for the second sensing component stripe, e.g., via the column select circuitry <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> and the multiplexers <NUM>-<NUM> and <NUM>-<NUM>. The controller can then direct writing the data moved to the second sensing component stripe to the destination location in the second row of memory cells.

In a DRAM implementation, a shared I/O line can be used as a data path to move data in the memory cell array between various locations, e.g., subarrays, in the array. The shared I/O line can be shared between all sensing component stripes. In various embodiments, one sensing component stripe or one pair of sensing component stripes, e.g., coupling a source location and a destination location, can communicate with the shared I/O line at any given time. The shared I/O line is used to accomplish moving the data from one sensing component stripe to the other sensing component stripe. A row in the first sensing component stripe can be opened and the data values of the memory cells in the row can be sensed. After sensing, the first sensing component stripe can be opened to the shared I/O line, along with opening the second sensing component stripe to the same shared I/O line. The second sensing component stripe can still be in a pre-charge state, e.g., ready to accept data. After the data from the first sensing component stripe has been moved, e.g., driven, into the second sensing component stripe, the second sensing component stripe can fire, e.g., latch, the data into respective sense amplifiers and compute components. A row coupled to the second sensing component stripe can be opened, e.g., after latching the data, and the data that resides in the sense amplifiers and compute components can be written into the destination location of that row.

<FIG> illustrates a timing diagram <NUM> associated with performing a number of data movement operations using circuitry in accordance with a number of embodiments of the present disclosure. The timing diagram <NUM> schematically illustrated in <FIG> is shown as an example of a sequence of signals in circuitry to enable movement of data, as described herein. A time scale <NUM> horizontally demarcated in signaling units (t<NUM>, t<NUM>, t<NUM>,. , t<NUM>) of arbitrary length is shown by way of example.

According to various embodiments of the present disclosure, a controller, e.g., <NUM> in <FIG>, can be configured to couple to one or more banks and bank sections of a memory device, e.g., <NUM>/<NUM> in <FIG>, to execute a command to move data from a source subarray, e.g., a source subarray <NUM>-<NUM> and <NUM>-<NUM>, to a destination subarray, e.g., a destination subarray <NUM>-N-<NUM> and <NUM>-N-<NUM>.

As such, at t<NUM> the controller can provide a signal to enable a pre-charge of the source sensing component stripe <NUM> of the source subarray <NUM>-<NUM> to be driven low to enable, e.g., fire, the source sensing component stripe to read and store sensed data. A signal can be input at t<NUM> to the selected source row <NUM> to enable a read (sense) of the data values in the memory cells of the row by the row being driven to high. A signal can be input at t<NUM> to the sense circuitry <NUM>, e.g., sense amplifiers and compute components, associated with the source sensing component stripe to enable sensing of the data values in the memory cells of the row by the sense circuitry being driven to high. A signal can be input at t<NUM> to the selected source columns <NUM> to enable a read (sense) of the data values in the memory cells of the selected source columns of the row by the columns being driven to high.

According to various embodiments, at t<NUM> the controller can provide a signal to enable a pre-charge of a number of shared I/O lines <NUM> to couple a number of shared I/O lines with the source sensing component stripe of the source subarray by being driven low. Between around t<NUM> through t<NUM>, the sensed data can be conducted through the number of shared I/O lines <NUM> so as to be accessible by components of the destination subarray <NUM>-N-<NUM>. For example, as described herein, the data from sequentially selected columns, e.g., columns <NUM> through <NUM>, configured to be coupled to each of the number of shared I/O lines can be sequentially sent through the coupled number of shared I/O lines during the time period from around t<NUM> through t<NUM>. In some embodiments, as shown at <NUM>, the data conducted through the number of shared I/O lines can include data sensed from complementary sense lines.

The controller can provide a signal at t<NUM> to enable a pre-charge of the destination sensing component stripe <NUM> of the destination subarray <NUM>-N-<NUM> to be driven low to enable, e.g., fire, the destination sensing component stripe to receive and store moved data by being coupled to the number of shared I/O lines <NUM>. A signal can be input at t<NUM> to the selected destination columns <NUM> to enable movement of the data values to the sense circuitry <NUM>, e.g., sense amplifiers and compute components, associated with the destination sensing component stripe for the selected columns by the selected destination columns being driven to high. A signal can be input at t<NUM> to latch the data moved to the destination sensing component stripe to be stored in the sense circuitry <NUM>, e.g., sense amplifiers and compute components, associated with the source sensing component stripe by the sense circuitry being driven to high. A signal can be input at t<NUM> to the selected destination row <NUM> to enable the data stored in the sense circuitry to be moved and written to selected memory cells thereof by being driven to high.

Various time frames can be implemented for signal conduction pathways to remain enabled, e.g., opened, before a signal is provided to disable, e.g., close, the signal conduction pathways. According to some embodiments, the data stored in the sense circuitry <NUM>, e.g., sense amplifiers and compute components, by the sense circuitry being driven to high at t<NUM> can remain accessible to the selected destination row <NUM> until a signal is input at t<NUM> to disable the signal conduction pathway by being driven to low. As such, the signal conduction pathway for the sense circuitry <NUM> can be open from t<NUM> through t<NUM>, which encompasses the time frame from t<NUM> through t<NUM> during which the signal conduction pathway for the selected destination row is open.

According to various embodiments of the present disclosure, a source row of a source subarray, e.g., any one of <NUM> rows, can be different from, e.g., need not match, a destination row of a destination subarray, where the source and destination subarrays can, in various embodiments, be in the same or different banks and bank sections of memory cells. Moreover, a selected source column, e.g., any one of eight configured to be coupled to a particular shared I/O line, can be different from, e.g., need not match, a selected destination column of a destination subarray.

While example embodiments including various combinations and configurations of sensing circuitry, sense amplifiers, compute components, sensing component stripes, shared I/O lines, column select circuitry, multiplexers, signal timing sequences, etc., have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuitry, sense amplifiers, compute components, sensing component stripes, shared I/O lines, column select circuitry, multiplexers, signal timing sequences, etc., disclosed herein are expressly included within the scope of this disclosure.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure.

Claim 1:
An apparatus, comprising:
a memory device (<NUM>), comprising:
an array (<NUM>, <NUM>) of memory cells;
sensing circuitry (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) coupled to the array (<NUM>, <NUM>) via a plurality of sense lines (<NUM>, <NUM>, <NUM>), the sensing circuitry including sense amplifiers (<NUM>, <NUM>, <NUM>) and compute components (<NUM>, <NUM>, <NUM>) that are in sensing component stripes corresponding to respective subarrays, wherein the sense amplifiers and the compute components are configured to perform compute operations on data values individually sensed from the array via the plurality of sense lines;
a controller (<NUM>) configured to couple to the array (<NUM>, <NUM>) and the sensing circuitry (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>);
a plurality of shared I/O lines (<NUM>, <NUM>, <NUM>); and
a multiplexer (<NUM>) coupled to a respective shared I/O line (<NUM>, <NUM>, <NUM>) and the sensing circuitry (<NUM>, <NUM>, <NUM>, <NUM>), wherein the multiplexer (<NUM>) is configured to:
select a respective sense amplifier (<NUM>, <NUM>, <NUM>) and a respective compute component (<NUM>, <NUM>, <NUM>) in a respective sensing component stripe; and
couple the selected respective sense amplifier (<NUM>, <NUM>, <NUM>) and the selected respective compute component (<NUM>, <NUM>, <NUM>) of the respective sensing component stripe to the respective shared I/O line (<NUM>, <NUM>, <NUM>);
wherein each of the plurality of shared I/O lines is coupled to selected sense amplifiers and selected compute components in a portion of a subarray, and wherein the plurality of shared I/O lines (<NUM>, <NUM>, <NUM>) are configured to:
move the data values from a first sensing component stripe corresponding to a source location in a first subarray to a second sensing component stripe corresponding to a destination location in a second subarray by selectively coupling the selected sense amplifiers (<NUM>, <NUM>, <NUM>) and the selected compute components (<NUM>, <NUM>, <NUM>) from a corresponding portion of the subarray to the respective shared I/O line (<NUM>, <NUM>, <NUM>) from the plurality of shared I/O lines (<NUM>, <NUM>, <NUM>).