Patent Description:
As a chip process node increasingly drops, chip integration is increasingly improved. A small size, a high rate, and high performance have become a development trend of an electronic component. An increasing quantity of transistors per unit area in a chip leads to an increasingly high power density and increasingly challenging thermal management on the chip. In a system-level chip package (System-in-Package, SiP) structure, multiple heterogeneous chips and discrete devices are packaged and integrated into a small-size system. Because different chips have different power consumption in different operating states, a problem such as heat accumulation or uneven heat dissipation easily occurs in a system-in-package structure. At present, a commonly used technology for improving a heat dissipation capability of the chip is to add a heat dissipation apparatus, such as a metal heat sink or a thermo electric cooler (TEC), on a passive surface of the chip by using a thermal interface material (TIM). Heat generated by the chip is finally transferred to the air. However, for a system-level chip package, this heat dissipation manner cannot achieve rapid and even heat dissipation of the multiple heterogeneous chips and discrete devices, and therefore is not conducive to improving heat dissipation efficiency for the system-level chip package.

Japanese patent application JP <CIT> provides an electrical device. The electrical device includes a substrate, multiple electrical devices on the substrate P, and some electrical devices.

US patent <CIT> discloses a chip including semiconductor dies covered by a PET sheet.

Embodiments of the present invention provide a chip package structure and a manufacturing method thereof, according to the attached claims, so as to implement rapid and even heat dissipation for multiple chips and multiple discrete devices in a system-level chip package, and improve heat dissipation efficiency for the system-level chip package structure.

A first aspect of the embodiments of the present invention provides a chip package structure according to independent claim <NUM>. In the chip package structure, the heat dissipation apparatus including the insulation layer and the thermally conductive layer that are laminated is disposed, and the insulation layer completely encloses the multiple chips and multiple discrete devices in the chip package and the upper surface of the substrate, so as to effectively increase a heat dissipation area, and implement even and rapid heat dissipation for the multiple chips and the multiple discrete devices.

In an implementation, the insulation layers are further configured to conduct the heat generated by the multiple chips and the multiple discrete devices to the air, so that the heat generated by the multiple chips and the multiple discrete devices is directly dissipated by using the insulation layer.

Because the insulation layer is in direct contact with the air at an edge position close to the substrate, the heat generated by the multiple chips and the multiple discrete devices may be further directly dissipated by using the insulation layer, so as to further improve a heat dissipation speed.

The thermally conductive material is evenly doped with the formable insulating material to form the thermally conductive layer. On the one hand, the thermally conductive layer can also have good formability by means of formability of the insulating material. On the other hand, the evenly doped thermally conductive material is used to ensure that all areas of the thermally conductive layer have even thermal conductivity, so as to implement even heat dissipation for the multiple chips and the multiple discrete devices.

In an implementation, the thermally conductive material includes one or more of graphene, a graphite sheet, or a boron nitride sheet.

In an implementation, the formable insulating material includes at least one of an epoxy resin or a polyimide.

The graphene, the graphite sheet, or the boron nitride sheet is evenly doped with the epoxy resin or the polyimide in different proportions to form the thermally conductive layer. On the one hand, good thermal conduction efficiency can be ensured, and a heat dissipation speed can be improved. On the other hand, it can be ensured that the thermally conductive layer has good formability. Therefore, when the heat dissipation apparatus is being cured to a system-level chip package, the thermally conductive layer can change with shape changes of the outer surfaces of the multiple chips, the outer surfaces of the multiple discrete devices, and the upper surface of the substrate in a manner such as thermo compression, so as to further increase a heat dissipation area, and improve heat dissipation efficiency for an entire system-level chip package.

In an implementation, the chip includes any one of a wire bonding chip or a flip chip.

In an implementation, the chip package structure further includes multiple solder balls, and the multiple solder balls are disposed in an array on a lower surface of the substrate.

A second aspect of the embodiments of the present invention provides a method for manufacturing a chip package structure according to independent claim <NUM>.

In the method for manufacturing a chip package structure, the heat dissipation apparatus is laminated to the upper surface of the substrate, so that the insulation layer completely encloses and adheres to the outer surfaces of the multiple chips, the outer surfaces of the multiple discrete devices, and the upper surface of the substrate, so as to effectively increase a heat dissipation area, and implement even and rapid heat dissipation for the multiple chips and the multiple discrete devices.

The following describes the embodiments of the present invention with reference to the accompanying drawings.

Referring to <FIG>, an embodiment of the present invention provides a system-level chip package structure <NUM>, including a substrate <NUM>. Multiple chips <NUM> and <NUM> and multiple discrete devices <NUM> are packaged on an upper surface of the substrate <NUM>. Multiple solder balls <NUM> are disposed on a lower surface of the substrate <NUM>. In this embodiment, the chip <NUM> is packaged on the upper surface of the substrate <NUM> in a flip chip (Flip Chip) manner. The chip <NUM> is packaged on the upper surface of the substrate <NUM> in a wire bonding (Wire bonding) manner. The multiple discrete devices <NUM> are packaged on the upper surface of the substrate <NUM> in a surface-mount manner. It may be understood that when the system-level chip package structure <NUM> is operating, the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> are heat sources. To allow an operating temperature of the system-level chip package structure <NUM> to be within a rated temperature range, heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> needs to be evenly and rapidly dissipated, so as to ensure stable operation of the system-level chip package structure <NUM>. It may be understood that types of the chips <NUM> and <NUM> include but are not limited to a wire bonding chip and a flip chip, and the discrete devices include but are not limited to a capacitor and an inductor.

The system-level chip package structure <NUM> further includes a heat dissipation apparatus <NUM>. The heat dissipation apparatus <NUM> includes an insulation layer <NUM> and a thermally conductive layer <NUM> that are laminated. The insulation layer <NUM> completely encloses and adheres to outer surfaces of the multiple chips <NUM> and <NUM>, outer surfaces of the multiple discrete devices <NUM>, and the upper surface of the substrate <NUM>, and is configured to conduct the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> to the thermally conductive layer <NUM> and the substrate <NUM>, so that the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> is dissipated by using the thermally conductive layer <NUM> and the substrate <NUM>. The lamination means that two or more layers of a same material or different materials are combined as a whole by means of heating and pressing with or without use of a binder. In this embodiment, the insulation layer <NUM> and the thermally conductive layer <NUM> are combined as a whole under the action of heat and pressure. In this embodiment, the insulation layer <NUM> and the thermally conductive layer <NUM> that are laminated coincide in a projection direction perpendicular to the upper surface of the substrate <NUM>.

It may be understood that the insulation layer <NUM> is further configured to conduct the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> to the air, so that the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> is directly dissipated by using the insulation layer <NUM>. The insulation layer <NUM> has good formability and specific thermal conductivity. Therefore, the heat dissipation apparatus <NUM> can be cured to the substrate <NUM> in a thermo compression manner, and the insulation layer <NUM> can closely adhere to the outer surfaces of the multiple chips <NUM> and <NUM>, the outer surfaces of the multiple discrete devices <NUM>, and the upper surface of the substrate <NUM>, so as to effectively increase a heat dissipation area, and implement rapid heat dissipation for the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM>. In this embodiment, the insulation layer <NUM> is made of a formable insulating material, including but not limited to, for example, an epoxy resin or a polyimide. The thermally conductive layer <NUM> is made of graphene, a graphite sheet, or a boron nitride sheet doped with an epoxy resin or a polyimide in different proportions. It may be understood that the thermally conductive layer <NUM> is not limited to being made of the graphene, the graphite sheet, or the boron nitride sheet doped with the epoxy resin or the polyimide, and may be alternatively made of another thermally conductive material that has similar performance to the graphene, the graphite sheet, or the boron nitride sheet and is evenly doped in a specific proportion with another formable insulating material that has similar performance to the epoxy resin or the polyimide.

According to the present invention, the heat dissipation apparatus <NUM> includes multiple insulation layers <NUM> and multiple thermally conductive layers <NUM>. The multiple insulation layers <NUM> and the multiple thermally conductive layers <NUM> are alternately laminated. When the heat dissipation apparatus <NUM> includes multiple insulation layers <NUM> and multiple thermally conductive layers <NUM>, a bottom layer is an insulation layer <NUM>, configured to completely enclose the outer surfaces of the multiple chips <NUM> and <NUM>, the outer surfaces of the multiple discrete devices <NUM>, and the upper surface of the substrate <NUM>; a top layer is a thermally conductive layer <NUM>, configured to conduct the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> to the air. It may be understood that different insulation layers <NUM> and different thermally conductive layers <NUM> may have different thermal conductivity coefficients and different electrical conductivity coefficients.

Referring to <FIG>, when the system-level chip package structure <NUM> is being manufactured, the corresponding chips <NUM> and <NUM> and discrete devices <NUM> may be first packaged on the upper surface of the substrate <NUM>, and then the heat dissipation apparatus <NUM> is cured to the upper surface of the substrate <NUM> in the thermo compression manner. Specifically, the insulation layer <NUM> and the thermally conductive layer <NUM> may be laminated together in advance to form the heat dissipation apparatus <NUM>, and the heat dissipation apparatus <NUM> is further cured to the upper surface of the substrate <NUM> in the thermo compression manner with the insulation layer <NUM> facing the upper surface of the substrate <NUM>, as shown in <FIG>. Alternatively, the insulation layer <NUM> may be first cured to the upper surface of the substrate <NUM> in the thermo compression manner, and then the thermally conductive layer <NUM> is cured to an upper surface of the insulation layer <NUM> in the thermo compression manner. It may be understood that a process condition for curing the heat dissipation apparatus <NUM> to the upper surface of the substrate <NUM> may include but is not limited to a temperature condition and a pressure condition.

Referring to <FIG>, the insulation layer <NUM> of the heat dissipation apparatus <NUM> completely encloses the outer surfaces of the multiple chips <NUM> and <NUM>, the outer surfaces of the multiple discrete devices <NUM>, and the upper surface of the substrate <NUM>, so as to form an omnidirectional heat dissipation path around the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM>, and implement even and efficient heat dissipation for the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM>. Specifically, a heat dissipation path of the system-level chip package structure <NUM> is indicated by arrows in <FIG>. Because the insulation layer <NUM> is in close contact with the upper surface of the substrate <NUM> and the thermally conductive layer <NUM>, On the one hand, the heat generated by the multiple chips <NUM> and <NUM> and the multiple discrete devices <NUM> may be conducted to the substrate <NUM> by using the insulation layer <NUM>, and the heat is further dissipated to the air by using the substrate <NUM>; On the other hand, the heat may be conducted to the thermally conductive layer <NUM> by using the insulation layer <NUM>, and the heat is further dissipated to the air by using the thermally conductive layer <NUM>. In addition, heat at an edge position near the substrate <NUM> may be directly conducted to the air by using the insulation layer <NUM> to implement heat dissipation. Because the insulation layer <NUM> is in close contact with all chips <NUM> and <NUM> and all discrete devices <NUM>, the heat generated by the chips <NUM> and <NUM> and the discrete devices <NUM> can be more evenly conducted to the thermally conductive layer <NUM> and the substrate <NUM>, and performance of an entire system-level chip package structure <NUM> can be effectively prevented from being affected because of an excessively high temperature of an individual chip or discrete device.

Referring to <FIG>, an embodiment of the present invention provides a terminal <NUM>, including a system-level chip package structure <NUM> and a mainboard <NUM>. A pad <NUM> is disposed on the mainboard <NUM>, and the system-level chip package structure <NUM> is welded to the pad <NUM> by using the solder balls <NUM>, so as to implement an electrical connection with the mainboard <NUM>. The system-level chip package structure <NUM> is the system-level chip package structure <NUM> in the embodiment shown in <FIG>. For details, refer to the related description in the embodiment shown in <FIG>. It may be understood that the system-level chip package structure <NUM> includes a heat dissipation apparatus <NUM>, so as to implement even and efficient heat dissipation for chips <NUM> and <NUM> and discrete devices <NUM> in the system-level chip package structure <NUM>, improve heat dissipation performance of the terminal <NUM>, and ensure operation stability of the terminal <NUM>. The terminal may be, but is not limited to, a mobile phone, a tablet computer, a smartwatch, or the like.

Referring to <FIG>, an example for a better understanding provides a method for manufacturing a system-level chip package structure, including:.

In this embodiment, the first temperature and the third temperature are both <NUM> degrees. The second temperature and the fourth temperature are both <NUM> degrees. The first pressure and the second pressure are both <NUM>-<NUM> kgf/cm<NUM> (kgf/cm<NUM>). The first time period and the third time period are both <NUM> seconds. The second time period and the fourth time period are both one hour. It may be understood that a temperature condition, a pressure condition, and duration for laminating the insulation layer may be the same as or different from a temperature condition, a pressure condition, and duration for laminating the thermally conductive layer, and a temperature condition and duration for curing the insulation layer may be the same as or different from a temperature condition and duration for curing the thermally conductive layer. Selection may be specifically performed according to different materials.

In this embodiment, in this embodiment, the first temperature is <NUM> degrees, the second temperature is <NUM> degrees, the first pressure is <NUM>-<NUM> kgf/cm<NUM>, the first time period is <NUM> seconds, and the second time period is one hour.

It may be understood that process parameters used in each step in the method examples shown in <FIG> and <FIG> are merely example parameters, and are not intended to limit the protection scope of the present invention. The process parameters may be appropriately changed according to different materials used by the insulation layer and the thermally conductive layer.

Claim 1:
A chip package structure (<NUM>), comprising a substrate (<NUM>), multiple chips (<NUM>, <NUM>) and multiple discrete devices (<NUM>) that are packaged on an upper surface of the substrate (<NUM>), and a heat dissipation apparatus (<NUM>), characterized in that, the heat dissipation apparatus (<NUM>) comprises multiple cured insulation layers (<NUM>) and multiple cured thermally conductive layers (<NUM>) that are alternately laminated and coincide in a projection direction perpendicular to the upper surface of the substrate, one of the insulation layers (<NUM>) is a bottom layer, which is cured to the upper surface of the substrate (<NUM>), one of the thermally conductive layers (<NUM>) is cured to an upper surface of the bottom layer (<NUM>) cured to the upper surface of the substrate (<NUM>), and the bottom layer is completely enclosing and adhered to outer surfaces of the multiple chips (<NUM>, <NUM>), outer surfaces of the multiple discrete devices (<NUM>), and the upper surface of the substrate (<NUM>), and is configured to conduct heat generated by the multiple chips (<NUM>, <NUM>) and the multiple discrete devices (<NUM>) to the thermally conductive layers (<NUM>) and the substrate (<NUM>), so that the heat generated by the multiple chips (<NUM>, <NUM>) and the multiple discrete devices (<NUM>) is dissipated by using the thermally conductive layers (<NUM>) and the substrate (<NUM>), and another one the thermally conductive layers (<NUM>) is a top layer, which is configured to conduct the heat generated by the multiple chips (<NUM>, <NUM>) and the multiple discrete devices (<NUM>) to the air,
wherein, the thermally conductive layers (<NUM>) are made of a thermally conductive material and a formable insulating material, the thermally conductive material is evenly doped with the formable insulating material.