Patent Description:
Antenna arrays are in widespread use today in diverse applications at microwave and millimeter wave frequencies, such as in aircraft, satellites, vehicles, watercraft, and base stations for general land-based communications. Such antenna arrays typically include microstrip radiating elements driven with phase shifting beamforming circuitry to generate a phased array for beam steering. It is typically desirable for an entire antenna system, including the antenna array and beamforming circuitry, to occupy minimal space with a low profile.

An integrated antenna array may be defined as an antenna array constructed with antenna elements integrated with radio frequency (RF) integrated circuit chips (RFICs) (interchangeably called "beamformer ICs" (BFICs)) in a compact structure. An integrated antenna array may have a sandwich type configuration in which the antenna elements are disposed in an exterior facing component layer and the RFICs are distributed across the effective antenna aperture within a proximate, parallel component layer behind the antenna element layer. The RFICs may include RF power amplifiers (PAs) for transmit and/or low noise amplifiers (LNAs) for receive and/or phase shifters for beam steering. By distributing PAs / LNAs in this fashion, higher efficiency on transmit and/or improved noise performance on receive are attainable, along with higher reliability relative to non-distributed IC designs.

<CIT> describes a phased array antenna module, phase array antenna system including the same and calibration method using the same.

In an aspect of the present disclosure, an antenna apparatus according to claim <NUM>, where the upper surface interconnect could be a wirebond, ribbon bond or edge contact pair.

Thereby, the at least one RFIC chip within an integrated antenna structure has multiple surface interfaces, which may lead to performance and manufacturing advantages for the antenna apparatus.

A phased array antenna is defined in independent claim <NUM>.

The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings in which like reference characters indicate like elements or features. Various elements of the same or similar type may be distinguished by annexing the reference label with an underscore / dash and second label that distinguishes among the same / similar elements (e.g., _1, _2), or directly annexing the reference label with a second label. However, if a given description uses only the first reference label, it is applicable to any one of the same / similar elements having the same first reference label irrespective of the second label. Elements and features may not be drawn to scale in the drawings.

The following description, with reference to the accompanying drawings, is provided to assist in a comprehensive understanding of certain exemplary embodiments of the technology disclosed herein for illustrative purposes. The description includes various specific details to assist a person of ordinary skill the art with understanding the technology, but these details are to be regarded as merely illustrative. For the purposes of simplicity and clarity, descriptions of well-known functions and constructions may be omitted when their inclusion may obscure appreciation of the technology by a person of ordinary skill in the art.

<FIG> is a top plan view of an example antenna apparatus <NUM> according to an embodiment, and <FIG> is a front side view of antenna apparatus <NUM>. Referring collectively to <FIG> and <FIG>, antenna apparatus <NUM> (hereafter, "antenna <NUM>") includes an antenna substrate <NUM> having an upper surface <NUM> upon which multiple radio frequency integrated circuit (RFIC) chips 150_1 to 150_K are attached. (Note that RFIC chips <NUM> may also be called beamformer IC (BFIC) chips, interchangeably. ) N antenna elements 125_1 to 125_N forming a planar array <NUM> may be disposed at a lower surface <NUM> of antenna substrate <NUM>. Each antenna element 125_i is coupled to an RFIC chip 150_ j (i, j = any integer) through a via <NUM> (forming a probe feed) and an RF contact <NUM> at the lower surface of RFIC chip 150_ j. Each RF contact <NUM> is in turn coupled to an RF signal conductor <NUM>_s at an upper surface of RFIC chip 150_ j through beamforming circuitry that includes one or more active circuit units (ACUs) such as 130_1, 130_2. The values of integers K and N may differ from embodiment to embodiment depending on the application. In the following discussion (and as shown in <FIG>), a "small array" example in which K=<NUM> and N=<NUM> will be discussed for simplicity of understanding.

Antenna substrate <NUM> may include a dielectric layer <NUM>, a ground plane <NUM> for reflecting signal energy from antenna elements <NUM>, and a layer region <NUM> ("redistribution layer (RDL) layer") including conductive lines for DC and/or control signals supplied to RFIC chips <NUM>. At least one transmission line ("TL") section <NUM> has a lower surface attached to upper surface <NUM> of antenna substrate <NUM>. TL section <NUM> has an upper surface at which a signal conductor 181_s of the transmission line is disposed and coupled at K locations to RF signal conductors 151_s through respective upper surface interconnects ("USINs") <NUM>. (Each of the K locations of signal conductor 181_s may be referred to as a branch arm of a combiner / divider. ) An USIN <NUM> is an interconnect made directly between conductors at the upper surfaces of an RFIC chip <NUM> and TL section <NUM>. Thus, an USIN <NUM> does not include vias in either the RFIC chip <NUM> or TL section <NUM> to interconnect conductors <NUM>, <NUM> at the upper surfaces through conductive elements within antenna substrate <NUM>. Some examples of an USIN <NUM> include a wirebond, a ribbon bond, and an edge contact pair (an edge contact on RFIC chip <NUM> fused with an edge contact on TL section <NUM>.

TL section <NUM> may include <NUM>:<NUM> RF couplers 118_1, 118_2 and 118_3 such as Wilkinson or hybrid couplers to form an overall K:<NUM> combiner / divider. In the embodiment illustrated, the transmission line medium of both TL section <NUM> and RFIC chips <NUM> is coplanar waveguide (CPW). In the CPW mediums, a pair of ground conductors 181_g1 and 181_g2 are arranged on opposite sides of signal conductor 181_s, and a pair of ground conductors 151_g1 and 151_g2 are arranged on opposite sides of signal conductor 151_s. Each ground conductor 151_g1 and 151_g2 is interconnected with an adjacent portion of ground conductor 181_g1 and 181_g2, respectively, through an USIN <NUM>. Alternatively, the transmission line medium in RFIC chips <NUM> and TL section <NUM> is microstrip, in which case the ground conductors <NUM> and <NUM> are omitted. Herein, an RFIC chip <NUM> having CPW beamforming circuitry will be referred to as a CPW chip, and an RFIC chip <NUM> having microstrip beamforming circuitry will be referred to as a microstrip chip. Analogous terminology may be used for TL section <NUM>. In an alternative embodiment to that illustrated in <FIG>, a microstrip chip <NUM> may be interconnected with a CPW TL section <NUM> through a hybrid transition within microstrip chip <NUM>. This embodiment will be described later in connection with <FIG>. In any case, one example material of a dielectric substrate <NUM> of TL section <NUM> is alumina. In medium or large element arrays, antenna <NUM> may include a plurality of TL sections <NUM> to facilitate manufacturing, particularly in the handling of brittle alumina substrates. The plurality of TL sections <NUM> may be interconnected by wirebonds or the like, if necessary.

With the interconnection structure and layout of antenna <NUM>, the upper portions of RFIC chips <NUM> are active die sides ("active regions") of the chips, where beamforming circuitry comprising amplifiers and/or phase shifters reside. For instance, doping regions and metallization of beamforming circuitry transistors, as well as combiner / divider <NUM> conductors are located within the active regions. By using upper surface interconnects <NUM> between RFICs <NUM> and transmission line section <NUM> to interconnect upper surface conductors, an extra transmission line layer within antenna substrate <NUM> to form the RF connections between RFICs <NUM> and TL section <NUM> can be avoided. Thus, the fabrication of antenna substrate <NUM> may be facilitated by omitting the process steps for forming another transmission line layer. Antenna substrate <NUM>, which may thereby be formed with a single layer of dielectric <NUM>, is referred to herein as a "single RF layer" substrate. Meanwhile, a polymer layer of layer region <NUM> may form the top surface <NUM> of antenna substrate <NUM>. In an alternative embodiment to that shown in <FIG>, RFICs <NUM> may be flipped such that the active die side faces the antenna substrate. This may result in a higher loss interface due to the proximity of the polymer layer and, in some cases, an underfill surrounding connection joints <NUM>. ) When the active die side faces up as shown in <FIG>, it is spaced relatively far from antenna ground plane <NUM>. This makes the configuration less prone to oscillations due to reflections between ground plane <NUM> and the active die side.

Each ACU <NUM> includes an amplifier and/or a phase shifter to adjust a transmit signal and/or a receive signal provided to/from an antenna element <NUM>. With RFIC chips <NUM> distributed across the effective aperture of antenna <NUM> and each coupled to one or more antenna elements <NUM>, antenna <NUM> may be understood as an active antenna array. In embodiments where the ACUs <NUM> include phase shifters for dynamic phase shifting of the signals, antenna <NUM> functions as a phased array. In such a phased array embodiment, a beam formed by antenna <NUM> is steered to a desired beam pointing angle set mainly according to the phase shifts of the phase shifters. Additional amplitude adjustment capability within RFICs <NUM> may also be included to adjust the antenna pattern. In any case, antenna <NUM> may be configured as a transmitting antenna system, a receiving antenna system, or both a transmitting and receiving antenna system.

A connector <NUM> may be side mounted or top mounted and connect to signal conductor 181_s. In the transmit direction, an input RF transmit signal is applied to connector <NUM> and divided into K divided transmit signals by couplers <NUM> and the K divided transmit signals are applied to RFIC chips 150_1 to 150_K, respectively. (A schematic illustration of signal flow is shown in <FIG>, discussed later. ) If an RFIC 150_ j includes a plurality M of ACUs <NUM>, RFIC 150_ j may further include an M:<NUM> combiner / divider <NUM> that splits the divided transmit signal into M further divided signals, each applied to one of the ACUs <NUM>. Once adjusted by the ACUs <NUM>, the adjusted signals are "element signals" each applied to one of antenna elements <NUM>.

A reverse signal flow occurs in the receive direction, in which an element signal is received by an ACU <NUM> from an antenna element <NUM>, and adjusted by a receive amplifier and/or a phase shifter (and typically filtered). The adjusted receive signal is routed through combiner / dividers <NUM> and <NUM> to produce a composite receive signal at connector <NUM>. It is noted here that a beam forming network (BFN) may be considered to encompass all of the signal paths between signal connector <NUM> and antenna elements 125_1 to 125_N. In the BFN, a single input transmit signal is divided into N element signals, and/or N element signals received from antenna elements <NUM> are combined into a single composite receive signal.

<FIG> also illustrates that antenna <NUM> may include a cover <NUM> (not shown in <FIG>) protecting at least the upper side from external elements. Since USINs <NUM> may be fragile, they should be protected from dust, moisture, etc.; cover <NUM> is suitably attached to the remaining assembly to provide such protection. In other examples, a printed wiring assembly (PWA) is attached to the upper side of antenna <NUM> in place of cover <NUM> and provides the desired protection from external elements. A radome may also be provided at the lower surface to protect antenna elements <NUM>.

In <FIG> and <FIG>, two antenna elements <NUM> are shown coupled to each RFIC <NUM> as an example. In other examples, each RFIC chip <NUM> is coupled to a single antenna element <NUM>, or to three or more antenna elements <NUM>. Antenna <NUM> is also shown to include additional chips 160_1 and 160_2, such as serial peripheral interface (SPI) chips. Chips <NUM> may function to provide DC signals and/or control signals to the RFICs <NUM> through signal lines such as 304_1, 308_1 formed within layer region <NUM> of antenna substrate <NUM>. The DC signals may bias amplifiers and/or control switching states of switches within ACUs <NUM>. The control signals may control phase shifts of phase shifters within ACUs <NUM>.

Antenna elements <NUM> may each be a microstrip patch antenna element printed on antenna substrate <NUM>. Other types of antenna elements such as dipoles or monopoles may be substituted. When embodied as microstrip patches, antenna elements <NUM> may have any suitable shape such as circular (as exemplified in <FIG>), square, rectangular or elliptical, and may be fed and configured in a manner sufficient to achieve a desired polarization, e.g., circular, linear, or elliptical. The number of antenna elements <NUM>, their type, sizes, shapes, inter-element spacing, and their feed mechanism may vary from embodiment to embodiment according to performance objectives of the application. While an example of antenna <NUM> is illustrated with eight antenna elements <NUM>, a typical embodiment for achieving a narrow antenna beam may include hundreds or thousands of antenna elements <NUM>. In embodiments described below, each antenna element <NUM> is a microstrip patch fed with a single probe feed. The probe feed may be implemented as a via <NUM> that electrically connects to an RF contact <NUM> of an RFIC <NUM>, interchangeably called an input / output (I/O) pad. An I/O pad is an interface that allows signals to come into or out of the RFIC <NUM>. In another example, each antenna element <NUM> is fed by two offset vias <NUM> using a different circular polarization feeding method. In other examples, an electromagnetic feed mechanism is used instead of a via <NUM>, where each antenna element <NUM> is excited from a respective feed point with near field energy.

In an example, antenna <NUM> is configured for operation over a millimeter (mm) wave frequency band, generally defined as a band within the <NUM> to <NUM> range. In other cases, antenna <NUM> operates in a microwave range from about <NUM> to <NUM>, or in a sub-microwave range below <NUM>. Herein, a radio frequency (RF) signal denotes a signal with a frequency anywhere from below <NUM> up to <NUM>. Note that an RFIC configured to operate at microwave or millimeter wave frequencies is often referred to as a monolithic microwave integrated circuit (MMIC), and is typically composed of III-V semiconductor materials such as indium phosphate (InP) or gallium arsenide (GaAs), or other materials such as silicon-germanium (SiGe).

<FIG> is a cross-sectional view of a portion of antenna <NUM> taken along the lines 3A-3A of <FIG>, and illustrates an example interconnection structure suitable for an embodiment with CPW chips <NUM> and a CPW transmission line section <NUM>. An antenna element 125_i is coupled to beamforming circuitry of an ACU 130_i formed within an active die side <NUM> of RFIC chip 150_ j (i, j = any integers). Such coupling may be made through a first via <NUM>, a catch pad <NUM>, an electrically conductive joint <NUM>, an RF contact <NUM>, a second via <NUM>, and a conductor <NUM>. (One or more ground vias that form a GS or GSG connection set together with second via <NUM> may also be included to reduce noise, as shown in <FIG> and discussed below. ) First via <NUM> may form at least part of a probe feed for the antenna element 125_i. First via <NUM> is formed within dielectric <NUM> and electrically connects antenna element 125_i to catch pad <NUM> formed on upper surface <NUM> of antenna substrate <NUM>. First via <NUM> passes through opening <NUM> formed in ground plane <NUM> to prevent shorting to the ground plane. Opening <NUM> may be annularly surrounded by an isolation material <NUM> such as a polymer at the depth level of ground plane <NUM>. Isolation material <NUM> may be composed of the same material as that within isolation layers of layer region <NUM>.

Layer region <NUM> may include, in order from upper surface <NUM> to ground plane <NUM>, a first isolation layer <NUM>, a first conductive layer <NUM>, a second isolation layer <NUM>, a second conductive layer <NUM>, and a third isolation layer <NUM>. First and second conductive layers <NUM>, <NUM> may be patterned to form signal lines such as 304_1 and 308_1 (see <FIG>) used to route DC and/or control signals to RFIC chips <NUM>, e.g., from SPI chips 160_1, 160_2. Conductive layers <NUM> and <NUM> are composed of metal or other conductive material. Openings may have been formed in conductive layers <NUM>, <NUM>, e.g. by not depositing conductive material in regions of the openings during the respective layer formation. The openings may be annularly surrounded by isolation material, so that first via <NUM> traverses the openings and does not short to conductive layers <NUM>, <NUM>. Note that each of the layers <NUM>, <NUM>, etc. within layer region <NUM> may be at least one order of magnitude thinner than dielectric <NUM>. For example, each of these layers may have a thickness (in the z direction) on the order of <NUM>-10pm, whereas dielectric <NUM> may be on the order of <NUM> thick. First and second conductive layers <NUM> and <NUM> may each form signal / ground lines in the x-y plane having a width on the order of <NUM> and spaced from one another by a spacing on the order of <NUM>. Each of layers <NUM> and <NUM> may have been etched or otherwise patterned to form tens, hundreds or thousands of signal lines and ground lines in a typical embodiment of antenna <NUM>. Nevertheless, in other embodiments, layer region <NUM> may be omitted, in which case bias voltages and signals are routed to RFICs <NUM> via other means.

Contact pad <NUM> is electrically connected to RF contact <NUM> through a conductive joint <NUM> such as a solder ball, gold bump, copper pillar with a solder cap, thermocompression bond or conductive epoxy. RF contact <NUM> is in turn connected to conductor <NUM> through the second via <NUM> which is formed within RFIC chip 150_j through the chip material <NUM>, e.g., InP or GaAs. Conductor <NUM> may directly connect to, or form part of, metallization of a transistor terminal or other circuit element of the beamforming circuitry. Conductor <NUM> may be printed metallization atop upper surface <NUM> of RFIC chip 150_j, in which case second via <NUM> may be formed as a through substrate via (TSV) that extends completely through the chip material <NUM>. Alternatively, conductor <NUM> is located below top surface <NUM> and second via <NUM> is formed as a blind via that connects on its upper end to conductor <NUM> within chip material <NUM>. Conductor <NUM> corresponds to a circuit point p of the beamforming circuitry, where circuit point p may be an input node of ACU <NUM>. The output of ACU <NUM>, corresponding to a circuit point w, may connect to a branch arm port (output port) of combiner / divider <NUM> (if present).

An input port of combiner / divider <NUM> electrically connects to conductor 151_s at a circuit point "q". USIN <NUM> connects conductor 151_s to conductor 181_s of TL section <NUM>. If USIN <NUM> is a wire bond, it may have a cylindrical or circular cross-section. If USIN <NUM> is a ribbon bond, it may have an elliptical or rectangular cross-section. Conductor 181_s may be printed metallization on the upper surface of dielectric <NUM> of TL section <NUM>. If TL section <NUM> is coplanar waveguide, the lower surface of dielectric <NUM> may be adhered to the top surface <NUM> of antenna substrate <NUM> (the upper surface of polymer layer <NUM>) using a nonconductive or conductive epoxy <NUM>.

In a typical embodiment, RFIC chip 150_ j may have tens or over one hundred electrical contacts such as <NUM>, <NUM> at its lower surface. These contacts may receive bias voltages and/or control signals from signal lines formed in first and second conductive layers <NUM> and <NUM>, through interconnects with conductive joints <NUM>. For instance, to connect a signal line formed in first conductive layer <NUM> to an electrical contact <NUM> of RFIC chip 150_j, an opening may have been made in first isolation layer <NUM> to expose the signal line of the first conductive layer <NUM>, and a conductive well <NUM> may have been formed in the opening. The opening in first isolation layer <NUM> may have been made by placing resist material on layer <NUM> in the location of the subsequent opening and then depositing the isolation material of isolation layer <NUM> in regions that exclude the resist material. A contact pad <NUM> may have been formed on the well <NUM>, and a conductive joint <NUM> formed by a heating / cooling process may connect contact pad <NUM> with contact <NUM>. Alternatively, contact pad <NUM> is omitted and conductive joint <NUM> conductively adheres to well <NUM>.

In a similar fashion, to connect a signal line formed in second conductive layer <NUM> to an electrical contact <NUM> of RFIC chip 150_j, an opening may have been formed in each of first isolation layer <NUM>, first conductive layer <NUM> and second isolation layer <NUM>. The process of forming the openings may have likewise involved placing resist material in the locations of the subsequent openings, one layer at a time, while the corresponding layer material is deposited. Additional isolation material <NUM> e.g., the same material as that of isolation layers <NUM>, <NUM>) may have been deposited in an annular region around the opening in first conductive layer <NUM>. This material prevents shorting to a subsequent conductive well <NUM> formed by deposition or the like within a cavity produced by the series of openings. A contact pad <NUM> may have been formed on conductive well <NUM>. A conductive joint <NUM> connects electrical contact <NUM> to contact pad <NUM>, or electrical contact <NUM> directly to conductive well <NUM> if contact pad <NUM> is omitted.

In some cases it is desirable to form a direct electrical connection between an electrical contact of RFIC <NUM> and antenna ground plane <NUM>. For instance, electrical contact <NUM> is electrically connected to ground plane <NUM> through a connection joint <NUM>, a contact pad <NUM> and a conductive well <NUM> (connection joint <NUM> may directly interface with conductive well <NUM> if contact pad <NUM> is omitted). A ground surface <NUM> may be present at the lower surface of RFIC chip <NUM> and may conductively adhere to contact <NUM>. Ground surface <NUM> may be a DC ground and/or a transmission line ground (e.g. a microstrip, CPW or stripline ground conductor). Note that in some cases there may be different types of transmission line mediums present in a single RFIC chip <NUM>. Conductive well <NUM> may have been formed in a similar manner as conductive well <NUM>, with a process that forms additional openings through second conductive layer <NUM> and third isolation layer <NUM> to expose a surface of ground plane <NUM>. Additional isolation material <NUM> may have been deposited in an annular region surrounding the opening in second conductive layer <NUM> to prevent shorting to conductive well <NUM> which is subsequently formed.

An underfill material <NUM> may surround at least some of the connection joints <NUM> to provide mechanical support to the connection joints and thereby improve their reliability. Typically, underfill material <NUM> may be a mixed material composed primarily of amorphous fused silica.

<FIG> is a cross-sectional view of an example interconnection structure within antenna <NUM> along a plane orthogonal to the plane shown in <FIG>. The view of <FIG> (a y-z plane view) intersects first via <NUM> and second via <NUM> (both depicted in the x-z plane in <FIG>) and illustrates a ground-signal-ground (GSG) transition from ground plane <NUM> to coplanar waveguide at the upper surface of RFIC chip 150_j. The GSG transition may prevent radiation from second via <NUM> from impacting the beamforming circuitry performance.

The coplanar waveguide at the upper surface of RFIC chip 150_ j includes signal conductor <NUM> and first and second ground conductors 344_1, 344_2 on opposite sides thereof. A first ground via 356_1 has an upper end connected to first ground conductor 344_1 to define a first ground point g1 (discussed in schematics below). First ground via 356_1 may connect at its lower end to a catch pad 327_1 at the lower surface of RFIC chip 150_j. An interconnect between catch pad 327_1 and a connection point of ground plane <NUM> at one side of first via <NUM> may include a conductive joint <NUM>, a catch pad 369_1 and a conductive well 374_1. Likewise, a second ground via 356_2 has an upper end connected to second ground conductor 344_2 to define a second ground point g2. Second ground via 356_2 may connect at its lower end to a catch pad 327_2. An interconnect between catch pad 327_2 and a connection point of ground plane <NUM> at the opposite side of first via <NUM> may include a conductive joint <NUM>, a catch pad 369_2 and a conductive well 374_2.

Isolation material <NUM> annularly surrounds a region between first via <NUM> and first and second conductive wells 374_1, 374_2 to prevent first via <NUM> from shorting to ground. With this configuration, a probe feed may be understood to be launched from the level (in the z direction) of the ground plane <NUM>, such that unwanted radiation between ground plane <NUM> and the upper surface of RFIC chip 150_j is minimized. It is noted here that alternative configurations may employ only a single ground via <NUM> to form a ground-signal (GS) transition; or, three or more ground vias <NUM> surrounding second via <NUM> (which may still be considered a GSG transition). Yet another alternative employs a slotline transition as a substitute for second via <NUM> and the first and second ground vias 356_1, 356_2.

<FIG> is a cross-sectional view of a portion of antenna <NUM> along the lines 3A-3A of <FIG> in an embodiment employing a microstrip chip and a microstrip transmission line section. In this example, it is assumed that ground conductors 151_g1, 151_g2, 181_g1 and 181_2 are omitted and each of signal conductors 151_s and 181_s is a microstrip signal conductor. A microstrip ground plane <NUM> may be present at the lower surface of RFIC chip 150_ j. Microstrip ground plane <NUM> may be a ground plane for a microstrip medium with signal conductors such as 151_s and other signal conductors of beamforming circuitry of ACU <NUM> and combiner / divider <NUM> within active region <NUM>. Microstrip ground plane <NUM> may electrically connect to antenna ground plane <NUM> through contact pad <NUM>, a conductive joint <NUM>, contact pad <NUM> and conductive well <NUM>, discussed above. Transmission line section <NUM> of <FIG> includes microstrip inner conductor 181_s at the upper surface and a ground plane <NUM> at the lower surface. Ground plane <NUM> may likewise connect to antenna ground plane <NUM> through a conductive joint <NUM>, a contact pad <NUM> and a conductive well <NUM> similar to conductive well <NUM>.

<FIG> is a cross-sectional view of an example interconnection structure within antenna <NUM>, configured with microstrip as in <FIG>, along a plane orthogonal to the plane shown in <FIG>. The view of <FIG> intersects first via <NUM> and second via <NUM> and illustrates a GSG transition from ground plane <NUM> to a microstrip medium formed by: microstrip ground plane <NUM>; signal conductors such as <NUM> of beamforming circuitry within the active die side <NUM>; and the chip material <NUM> separating the signal conductors and the microstrip ground plane <NUM>. An interconnect between microstrip ground plane <NUM> and a connection point of ground plane <NUM> at one side of first via <NUM> may include catch pad 327_1, a conductive joint <NUM>, catch pad 369_1 and conductive well 374_1. An interconnect of the same construction to connect the two ground planes <NUM>, <NUM> may be made on the opposite side of first via <NUM> with catch pad 327_2, another connection joint <NUM>, catch pad 369_2 and conductive well 374_2. Similar to the CPW case of <FIG>, the GSG transition of <FIG> may prevent radiation from second via <NUM> from affecting beamforming circuitry performance. Other aspects and operations of the antenna structure of <FIG> and <FIG> may be the same as that discussed above for <FIG>.

<FIG> is a top plan view of an antenna apparatus, <NUM>', according to alternative embodiment. <FIG> is a top plan view depicting a portion of an RFIC chip of antenna apparatus <NUM>', and <FIG> is a cross-sectional view of an example interconnection structure taken along the lines <NUM>-<NUM> of <FIG>. Referring collectively to <FIG>, <FIG> and <FIG>, antenna <NUM>' differs from antenna <NUM> illustrated in <FIG> above by configuring RFIC chips 150_1 to 150_K as microstrip chips rather than CPW chips. Microstrip RFIC chips <NUM> may include a microstrip combiner / divider <NUM>, microstrip ACUs <NUM>, and a microstrip to CPW transition, hereafter called a "hybrid transition". Combiner / divider <NUM> may include a microstrip signal conductor <NUM>_s at its input port, and output branches connected to respective ACUs <NUM>. The hybrid transition may be formed by: an input portion of signal conductor 551_s at the edge of RFIC chip <NUM>; first and second ground pads 551_g1 and 551_g2 on opposite sides of signal conductor 551_s; and first and second ground vias 655_1 and 655_2.

First and second ground vias 655_1 and 655_2 respectively connect ground pads 551_g1 and 551_g2 to microstrip ground surface <NUM>. <FIG>, which shows a cross-sectional view partly through first ground pad 551_g1 of RFIC chip 150_j (with distal structures omitted for clarity), illustrates ground via 655_1 electrically connecting first ground pad 551_g1 to microstrip ground surface <NUM>. Second ground via 655_2 may have the same or similar structure. Additionally, the same or similar interconnect as described above between ground surface <NUM> and antenna ground plane <NUM> may be formed. This interconnect may include contact / catch pads <NUM> and <NUM>, conductive joint <NUM> therebetween, and conductive well <NUM>. Upper surface interconnects <NUM> may be respectively provided to connect: signal conductor 551_s to signal conductor 181_s; first ground pad 551_g1 to ground conductor 181_g1; and second ground pad 551_g2 to second ground conductor 181_g2. Other aspects of antenna <NUM>' may be the same as that described above for antenna <NUM>.

<FIG> is a top plan view depicting a portion of a microstrip RFIC chip 150_j of an alternative embodiment of antenna <NUM>, in which active die sides of the RFIC chips <NUM> face the antenna substrate <NUM>. In other words, RFICs <NUM> are flipped as compared to the embodiments discussed above, such that the outer surfaces of the active die sides <NUM> are considered the lower surfaces of RFICs <NUM>. In this case, upper surface interconnects (USINs) <NUM> are still utilized to interconnect the beamforming circuitry within the active die sides (albeit through vias within RFICs <NUM>), to the upper surface conductors of TL sections <NUM>. A microstrip ground plane <NUM> may be present at the upper surface of RFIC chip 150_j, and a signal conductor 651_s may be in the form of an "island" isolated from ground plane <NUM> within an annular opening in ground plane <NUM> exposing chip material <NUM>. A via 655_s may be formed between active region <NUM> at the lower surface and signal conductor <NUM>_s on the upper surface. USINs <NUM> may be wirebonds or ribbon bonds, and if TL section <NUM> is CPW, a first USIN <NUM> connects conductor 651_s to conductor 181_s, and second and third USINs <NUM> connect points of ground plane <NUM> on opposite sides of conductor 651_s to respective ground conductors 181_g1 and 181_g2. If TL section <NUM> is microstrip, the second and third USINs <NUM> connected to ground plane <NUM> may be omitted.

<FIG> is a top plan view depicting a portion of a CPW RFIC chip 150_j of an alternative embodiment of antenna <NUM>, in which active die sides of the RFIC chips <NUM> face the antenna substrate <NUM>. As in the embodiment of <FIG>, RFICs <NUM> are flipped as compared to the earlier described embodiments, such that the outer surfaces of the active die sides <NUM> are considered the lower surfaces of RFICs <NUM>. The upper surface of RFIC chip <NUM>_ j may resemble that shown in <FIG>, with ground pads 551_g1 and 551_g2 but with a signal conductor 651_s in the form of a pad. In this case, a first via 655_s may be provided to connect the CPW signal conductor within active region <NUM> to signal conductor <NUM>_s; and second and third vias 655_g1 and 655_g2 are provided to connect first and second ground conductors within the active region <NUM> to ground pads 551_g1 and 551_g2, respectively. First, second and third USINs <NUM> may be provided for the connection to TL section <NUM> in the same manner as discussed for <FIG>, if TL section <NUM> is CPW. If TL section <NUM> is microstrip, ground pads 551_g1, 551_g2 and vias 655_g1, 655_g2 may be omitted.

<FIG> shows example beamforming circuitry of an active circuit unit (ACU) 130_i configured for a receive path (antenna receiving direction) of an RFIC chip <NUM>. ACU 130_i may include front end receiving circuitry between the input point p (as shown in <FIG>) and the output point w, which may include a low noise amplifier (LNA) <NUM>, a receive path phase shifter <NUM> and a bandpass filter <NUM> connected in series. In the CPW chip case of <FIG>, first and second ground points g1 and g2 may be coplanar waveguide ground points of LNA <NUM>, and circuit point p may be an input point of a signal conductor of LNA <NUM>. Phase shifter <NUM> and filter <NUM> may also be designed as CPW components. In an embodiment with microstrip chips, microstrip ground plane <NUM> (seen in <FIG> and <FIG>) may be a ground plane for all components of ACU 130_i. LNA <NUM> and phase shifter <NUM> may receive bias / control voltages from vias / signal lines (not shown) within RFIC chip <NUM> extending from electrical contacts such as <NUM>, <NUM> (seen in <FIG>, <FIG> and <FIG>).

<FIG> depicts example beamforming circuitry of an active circuit unit (ACU) 130_i configured for a transmit path (antenna transmitting direction) of an RFIC chip <NUM>. Here, front end circuitry within ACU 130_i may include a power amplifier (PA) <NUM>, a transmit path phase shifter <NUM> and a bandpass filter <NUM> connected in series. In the CPW chip case of <FIG>, first and second ground points g1 and g2 may be coplanar ground points of PA <NUM>, and circuit point p may be an output point of a signal conductor of PA <NUM>. Phase shifter <NUM> and filter <NUM> may also be designed as CPW components. In a microstrip chip embodiment, microstrip ground plane <NUM> may be a ground plane for all components of ACU 130_i. PA <NUM> and phase shifter <NUM> may receive bias / control voltages from vias / signal lines (not shown) within RFIC chip <NUM> extending from electrical contacts such as <NUM>, <NUM>.

<FIG> shows example beamforming circuitry of an active circuit unit (ACU) 130_i configured for both a receive path and a transmit path of an RFIC chip <NUM>. In this case, (ACU) 130_i includes first transmit / receive (T/R) circuitry <NUM> having an input port connected to input point p, and second T/R circuitry <NUM> with an input port connected to output point w. A receive path including LNA <NUM> and phase shifter <NUM> may be connected between first output ports of T/R circuitry <NUM>, <NUM>. A transmit path including phase shifter <NUM> and PA <NUM> may be connected between second output ports of T/R circuit circuitry <NUM>, <NUM>. T/R circuitry <NUM>, <NUM> may each include bandpass filters and/or switches to allow both transmit and receive path signals to pass from the input port to a respective output port. In some examples, different frequency bands are used for transmit vs. receive signals and bandpass filtering is sufficient to provide isolation between the paths. Time division multiplexed based switching may provide further or alternative isolation between the paths. In a CPW embodiment, first and second ground points g1 and g2 may be ground points of T/R circuitry <NUM>.

<FIG> schematically illustrates example beamforming circuitry comprising multiple ACUs within an RFIC chip. An RFIC 150_j may include a plurality of ACUs 130_1 to 130_M with respective input ports at circuit points p_1 to _M, respectively, and output ports at circuit points w_1 to w_M, respectively. The integer M can vary from embodiment to embodiment from as low as two (as in the example shown in <FIG>) to any suitable number of ACUs <NUM> that may be packaged within a single RFIC chip 150_j. Circuit points p_1 to P_M may be coupled to antenna elements 125_1 to 125_M through feeds <NUM>_1 to 601_M, where each feed <NUM> includes a second via <NUM>, a first via <NUM> and interconnect structures therebetween as described above for <FIG> in relation to circuit point p. For instance, in a CPW chip embodiment, each ACU 130_i may have first and second ground conductors tied to first and second ground points g1_ i and g2 _ i. An M:<NUM> combiner <NUM> combines receive signal outputs from the ADCs <NUM> at points w_1 to w_M into a combined receive signal at point q in a receive path operation, and / or divides a transmit signal applied at point q into M divided transmit signals applied at points w_1 to w_M to ACUs 130_1 to 130_M.

<FIG> is a schematic diagram depicting an example beamforming network (BFN) <NUM> within antenna <NUM>. BFN <NUM> may include a K:<NUM> combiner / divider <NUM> formed within transmission line section <NUM>, and K RFIC chips 150_1 to 150_ K, each having the configuration of RFIC 150_ j of <FIG>. K:<NUM> combiner / divider <NUM> has an input port at a circuit point t connected to connector <NUM>, and K output ports at circuit points q_1 to q_K connected to RFIC chips 150_1 to 150_K. Each RFIC chip <NUM> may be coupled to M antenna elements such as 125_1 to 125_M through M respective RF contacts <NUM>. Thus, there may be N antenna elements 125_1 to 125_N, where N = M x K. As noted earlier, the number N may number in the hundreds or thousands for a typical antenna <NUM> that forms a narrow antenna beam. In the example illustrated in <FIG>, K =<NUM>, M=<NUM> and N=<NUM>.

<FIG> is a flow chart of an example method, <NUM>, of fabricating antenna <NUM>. The order of the shown operations may be modified as desired. In method <NUM>, an antenna substrate <NUM> may be formed from a wafer and first vias <NUM> may be formed therein by drilling holes and filling them with conductive material in an electroplating or like process (S802). Antenna elements <NUM> and ground plane <NUM> may then be respectively printed on the lower and upper surfaces of the antenna substrate (S804). An RDL region <NUM> may thereafter be formed on the antenna substrate <NUM> above the ground plane (S806).

RFIC chips <NUM> are separately fabricated with beamforming circuitry <NUM>, <NUM>; second vias <NUM>; ground vias <NUM> (in the case of a CPW embodiment); RF contacts <NUM>; and other electrical contacts such as <NUM>, <NUM> (S808). Transmission line (TL) section(s) <NUM> may be separately formed with a BFN combiner / divider <NUM> (S810). Conductive joints <NUM> may be initially adhered to RF contacts <NUM> and other electrical contacts of RFIC chips <NUM> and/or to catch pads <NUM> / other contacts at the upper surface of antenna substrate <NUM> (S812). The RFIC chips <NUM>, other IC chips <NUM> and TL section(s) <NUM> may be placed on antenna substrate <NUM> (S814). A heating / cooling cycle may be performed to melt and cool solder or other conductive material of the conductive joints <NUM> and conductively adhere the RFIC chips, other IC chips, and the TL section(s) to the antenna substrate (S816). Upper surface interconnects <NUM> such as wirebonds or ribbon bonds may then be attached on opposite ends to RFIC chip conductors <NUM> or <NUM> and the TL section <NUM> conductors (branch arms) to interconnect the same (S818). A connector <NUM> may be attached to TL section <NUM>, and a cover <NUM> or PWA may be attached to the resulting assembly (S820).

Claim 1:
An antenna apparatus (<NUM>, <NUM>') comprising:
an antenna substrate (<NUM>) having opposite first (<NUM>) and second (<NUM>) surfaces;
at least one antenna element (<NUM>) disposed at the first surface (<NUM>) of the antenna substrate;
at least one radio frequency integrated circuit, RFIC, chip (150_j) having a lower surface attached to the second surface of the antenna substrate and having an RF contact (<NUM>) at the lower surface, the RF contact being coupled to the at least one antenna element through the antenna substrate, the RFIC chip having an RF signal conductor (151_s, 551_s) at an upper surface (<NUM>) thereof and beamforming circuitry (130_i, <NUM>) coupled between the RF contact and the RF signal conductor; and
a transmission line section (<NUM>) having a lower surface attached to the second surface of the antenna substrate, and having an upper surface at which a transmission line conductor (181_s) is disposed and electrically connected to the RF signal conductor of the RFIC chip through an upper surface interconnect (<NUM>).