Patent Description:
Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications that are expected to provide significant enhancements to national security applications where communication signal integrity or computing power are needed. They are operated at temperatures <<NUM> kelvin. Efforts on fabrication of superconducting devices have mostly been confined to university or government research labs, with little published on the mass producing of superconducting devices. Therefore, many of the methods used to fabricate superconducting devices in these laboratories utilize processes or equipment incapable of rapid, consistent fabrication. Recently there has been a movement to mass producing superconducting circuits utilizing similar techniques as those utilized in conventional semiconductor processes.

One well-known semiconductor process is the formation of contacts and conductive lines in a multi-level interconnect stack to couple devices to one another over different layers of an integrated circuit. One such fabrication process for formation of conductive contacts and lines is known as a dual damascene process. This technique has recently been attempted in the formation of superconducting circuits. During the fabrication of dual damascene superconducting circuits, via/trench structures are patterned, etched, filled with metal (e.g., niobium, tantalum, aluminum), then polished back using a chemical mechanical polishing (CMP) process. The next level dielectric is then deposited, and the sequence begins again, building up a multi-level interconnect stack. The CMP process and any exposure to oxygen prior to deposition of the next dielectric layer can result in oxidization of the conductive contacts and lines, which degrades performance. <CIT> proposes a method of forming a superconductor structure. <CIT> proposes a method of forming a superconductor device interconnect structure. <CIT> proposes a method for forming a microelectronics device. <CIT> proposes a method for forming an adhesion/barrier liner. <CIT> proposes an amorphous silicon dielectric.

The invention is defined by the independent claim. Various embodiments are described by the dependent claims.

In one example, a method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

The superconducting interconnect element may include a superconducting contact or conductive line having a top surface aligned with a top surface of a first dielectric layer, wherein a top surface of the superconducting contact or conductive line has an oxidized layer, and the top surface of the first dielectric layer has an oxidized layer. The plasma clean etch process may remove the oxidized layer from the superconducting contact or conductive line and the oxidized layer from the first dielectric layer.

The present invention is directed to methods for forming a superconductor interconnect structure. The method incorporates a preclean process to remove oxide layers from superconducting metal interconnect elements (e.g., conductive lines, contacts) and the interlayer dielectric (ILD) surfaces prior to encapsulation of the metal interconnect elements in the next level of dielectric. The oxides can be as a result of a chemical mechanical process (CMP), and/ or as a result of the exposure of the superconductor interconnect structure to oxygen outside of a vacuum environment. In one example, the method integrates a plasma preclean process into a dual damascene process for scaling into a high-density multilevel interconnect submicron technology. The method employs a nitrogen trifluoride (NF3) gas based in-situ plasma preclean etch process prior to dielectric deposition of a next layer in the dual damascene process to assure a smooth clean surface of the metal interconnect elements and the ILD surface on the underlying layer.

In typical damascene superconducting fabrication architectures, oxide removal by etching of the metal interconnect oxide (typically niobium oxide) and ILD surface oxide utilizes either an etch chamber separate from the deposition chamber on the same mainframe so the transfer is done in vacuo or by utilizing an oxide etch chamber on a different mainframe whereby the wafer is transported between mainframes. In either case, oxides form on the surfaces during the transfer even when transfers occur close to vacuum.

A system and method are disclosed herein is to preclean by etching contaminants from a Silicon (Si), dielectric, or metal surface of a superconductor structure and the deposition of an overlying dielectric layer within a single dielectric deposition chamber. This process is of particular significance with respect to eliminating surface oxides prior to dielectric deposition of superconducting interconnects. The removal of these surface oxides supports the following improvements in a superconducting electronics fabrication process: eliminating oxygen sources from interface which can diffuse into superconducting metallization (e.g., Niobium) during subsequent processing and reduce interconnect critical current (Ic) performance; eliminating unintended oxide layers during the deposition of Josephson Junction metallization which reduce the yield, uniformity, and repeatability of these structures; and the eliminating of high-loss interface oxides between dielectric material and superconducting traces which reduce the effective loss tangent of superconducting circuit elements.

In one example, a system is provided that includes a plasma enhanced chemical vapor deposition (PECVD) platform that is configured to support both an independent preclean process and dielectric deposition process in a single PECVD chamber. The Process of Record (POR) uses two chambers <NUM>) preclean chamber and <NUM>) deposition chamber. This disclosure combines both the preclean and deposition process into a single chamber, which prevent any further oxidation from occurring during the transfer from an external etch chamber to a deposition chamber. The intention of the system and method of the present disclosure is to eliminate unintended oxidation by establishing the capability to etch surface oxides/contaminants and dielectric deposition in a single chamber. This technique eliminates exposing a clean wafer surface to the oxidizing environment prior to dielectric deposition, for example, in transfer/buffer chambers employed in cluster tools.

<FIG> illustrates cross-sectional view of a superconducting interconnect structure <NUM>, for example, formed on a portion of a wafer. The superconducting interconnect structure <NUM> includes an active layer <NUM> overlying a substrate <NUM>. The substrate <NUM> can be formed of silicon, glass or other substrate material. The active layer <NUM> can be a ground layer or a device layer. A first dielectric layer <NUM> overlies the active layer <NUM>, and a second dielectric layer <NUM> overlies the first dielectric layer <NUM>. Both the first and the second dielectric layers <NUM> and <NUM> can be formed of a non-oxide based dielectric material. A first conductive line <NUM> is embedded in the first dielectric layer <NUM>. A first conductive contact <NUM> extends from the first conductive line <NUM> at a first end to a second conductive line <NUM> in the second dielectric layer <NUM>, and a second conductive contact <NUM> extends from the first conductive line <NUM> at a second end to a third conductive line <NUM> in the second dielectric layer <NUM>. A third dielectric layer overlies the second conductive line <NUM>, the third conductive line <NUM> and the second dielectric layer <NUM>. Each dielectric layer can be formed of a non-oxide based dielectric, such as silicon nitride, amorphous silicon, or amorphous SiC.

Each of the contacts and conductive lines are formed of a superconducting material, such as niobium. A cleaning process as described herein is performed prior to deposition of the third dielectric layer with both the cleaning process and the dielectric deposition process being performed in a single dielectric deposition chamber. A cleaning process can also be performed prior to deposition of the second dielectric layer <NUM> with both the cleaning process and the deposition of the second dielectric layer being performed in the same single dielectric deposition chamber.

Turning now to <FIG>, fabrication is discussed in connection with formation of interconnects in the superconducting device of <FIG>. It is to be appreciated that the present example is discussed with respect to a process flow that starts with the formation of either a single or dual damascene layer of superconducting metal in an insulating dielectric. The present example will be illustrated with respect to a single damascene trench etched into a dielectric thin film to form a bottom conductive line followed by a dual damascene process to form top conductive lines.

<FIG> illustrates a cross-sectional view of a superconductor structure <NUM> in its early stages of fabrication. The superconductor structure <NUM> resides in an etch chamber for forming vias and trenches in one or more dielectric layers. The superconductor structure <NUM> includes an active layer <NUM>, such as a ground layer or device layer, that overlays an underlying substrate <NUM>. The underlying substrate <NUM> can be, for example, a silicon or glass wafer that provides mechanical support for the active layer <NUM> and subsequent overlying layers. A first dielectric layer <NUM> is formed over the active layer <NUM>. Any suitable technique for forming the first dielectric layer <NUM> may be employed such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), sputtering or spin-on techniques to a thickness suitable for providing an interconnect layer. Alternatively, the first dielectric layer <NUM> can be formed directly on the substrate <NUM> in examples in which the active layer <NUM> is omitted. A conductive line <NUM> resides within the first dielectric layer <NUM> and has a top surface that is flush with a top surface of the first dielectric layer <NUM>. The conductive line <NUM> can be formed in a single damascene process, and goes through a cleaning process prior to deposition of the next dielectric layer.

The cleaning process is in situ plasma NF<NUM> clean in a deposition chamber prior to the next dielectric layer <NUM> being deposited to remove any oxide from the surface of the conductive line <NUM>. This process will be explained in further detail with reference to <FIG>. The second dielectric layer <NUM> overlies the first dielectric layer <NUM> and includes a pair of vias <NUM> that extend from a top surface of the second dielectric layer <NUM> to a top surface of the conductive line <NUM> that resides in the first dielectric layer <NUM>. The dielectric material employed in the first dielectric layer <NUM> and the second dielectric layer <NUM> can be formed from a non-oxide based dielectric material. The pair of vias <NUM> were formed in a first portion of a dual damascene process. <FIG> illustrates a second portion of the dual damascene process. As illustrated in <FIG>, a photoresist material layer <NUM> has been applied to cover the structure and patterned and developed to expose trench openings <NUM> in the photoresist material layer <NUM> in accordance with a trench pattern. The photoresist material layer <NUM> can have a thickness that varies in correspondence with the wavelength of radiation used to pattern the photoresist material layer <NUM>. The photoresist material layer <NUM> may be formed over the second dielectric layer <NUM> via spin-coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the trench openings <NUM>.

<FIG> also illustrates performing of an etch <NUM> (e.g., anisotropic reactive ion etching (RIE)) on the second dielectric layer <NUM> to form extended trench openings <NUM> (<FIG>) in the second dielectric layer <NUM> based on the trench pattern in the photoresist material layer <NUM>. The etch <NUM> can be a dry etch and employ an etchant which selectively etches the underlying second dielectric layer <NUM> at a faster rate than the underlying conductive line <NUM> and the overlying photoresist material layer <NUM>. For example, the second dielectric layer <NUM> may be anisotropically etched with a plasma gas(es), herein carbon tetrafloride (CF<NUM>) containing fluorine ions, in a commercially available etcher, such as a parallel plate RIE apparatus or, alternatively, an electron cyclotron resonance (ECR) plasma reactor to replicate the mask pattern of the patterned of the photoresist material layer <NUM> to thereby create the extended trench openings <NUM>. The photoresist material layer <NUM> is thereafter stripped (e.g., ashing in an O<NUM> plasma) so as to result in the structure shown in <FIG>.

Next, as illustrated in <FIG>, the structure is placed into a material deposition chamber <NUM> and undergoes a contact material fill to deposit a superconducting material <NUM>, such as niobium, into the via openings <NUM> and the trench openings <NUM> to form the resultant structure shown in <FIG>. The contact material fill can be deposited employing a standard contact material deposition. Following deposition of the contact material fill, the superconducting material <NUM> is placed into a polish chamber <NUM> and is polished via chemical mechanical polishing (CMP) down to the surface level of the dielectric layer <NUM> to form conductive lines <NUM> and contacts <NUM> that form part of the metal interconnects and provide the resultant structure of <FIG>.

However, during the CMP process, an oxide surface <NUM> may grow on the surface of the metal to a thickness of approximately <NUM>Å, and remain after the CMP process is complete. This oxide grows, for example, due to the presence of ammonium hydroxide and hydrogen peroxide in the CMP process. In the case where niobium is employed as the metal, a niobium oxide is formed. The presence of this niobium oxide will degrade the performance of the superconducting circuits (losses in the metal lines), so it needs be removed prior to the deposition of the next dielectric layer. A silicon oxide is formed on the deposited dielectric surface (e.g., on silicon nitride). The presence of this niobium oxide and silicon oxide will degrade the performance of the superconducting circuits through a variety of RF loss mechanisms typically associated with amorphous oxides so it needs to be removed prior to the deposition of the next dielectric layer.

The resultant structure is then placed into a dielectric deposition chamber <NUM> to undergo a precleaning process followed by a vacuum process and a dielectric deposition process, as illustrated in <FIG>. The resultant structure could have an oxidized surface layer on the superconducting material due to its exposure to oxygen when being removed from the CMP chamber to the dielectric deposition chamber, or an oxidized layer in addition to the oxide layers formed from the CMP process. The purpose of the precleaning process is to remove these oxide layers from the metal interconnect surfaces and the top surface of the dielectric layer prior to their encapsulation in the next level dielectric layer.

As illustrated in <FIG>, the dielectric deposition chamber <NUM> includes an Argon source <NUM> that provides Argon (Ar) gas into the dielectric deposition chamber <NUM> at a flow rate based on an Argon flow control device <NUM>, and a nitrogen trifluoride (NF3) gas source <NUM> that provides NF<NUM> gas into the dielectric deposition chamber <NUM> at a flow rate based on a NF<NUM> flow control device <NUM>. The dielectric deposition chamber <NUM> also includes a pressure controller <NUM> that sets the pressure inside the chamber <NUM>, a RF power controller <NUM> that sets the power in the dielectric deposition chamber <NUM> and a temperature controller <NUM> that sets the temperature in the dielectric deposition chamber <NUM>. In one example, the dielectric deposition chamber <NUM> is an Applied Materials DxZ plasma enhanced chemical vapor deposition (PECVD) chamber attached to a Centura mainframe. However, this process could be used in a number of different PECVD chambers that are properly configured with NF<NUM> gas and plasma capabilities.

In this example, the NF<NUM> plasma is a parallel plate and not a remote plasma. Plasma is directed from a top plate <NUM> to a bottom plate <NUM>, which could be a chuck, that holds the wafer. Typically, remote plasma NF<NUM> etches/cleans are used as chamber wall cleans and are not used as a process etch gas with a wafer present in the deposition chamber. However, it is possible to use remote NF<NUM> plasmas for the preclean process as well.

In one example, the wafer moves through a transfer chamber to the dielectric deposition chamber <NUM>. Once the wafer is in the dielectric deposition chamber <NUM>, the gas flows and pressures are stabilized, then a plasma is ignited to perform the preclean process <NUM> that etches the oxides <NUM> that have formed on the surfaces of the ILD and the superconducting interconnect metal. A typical process condition utilizes an NF<NUM> and Argon (Ar) gas mixture. Additionally, N<NUM> can be added to the gas mixture. In one example, NF<NUM> oxide preclean etch process conditions are as follows: NF<NUM> flow is set to about <NUM> sccm to about <NUM> sccm, Ar flow is set to about <NUM> sccm to about <NUM> sccm, N<NUM> flow (if applicable) is set to about <NUM> to about <NUM> sccm, power is set to about 700W, process pressure is set to about <NUM> Torr, and the process time is set to greater than <NUM> seconds. A representative etch rate is about <NUM>Å/min to about <NUM>Å/min with a typical process temperature set to about <NUM>.

Once the NF<NUM> preclean process is complete, the process gases are then pumped in a direction along arrow <NUM> by a pump <NUM>, as shown in <FIG>, to exhaust the gases to prepare the chamber <NUM> for the dielectric deposition process. Only the NF<NUM> and Ar gases are evacuated while the N<NUM> gas continues to flow during the pumping process. A detail of note is that the wafer that was etched in the preclean process remains in the deposition chamber throughout the vacuum process and the subsequent dielectric deposition process. Typically, the vacuum process can take about <NUM> seconds to complete.

Next, as illustrated in <FIG>, the wafer surface oxide <NUM> that was etched in the preclean process is encapsulated in a PECVD deposited dielectric layer <NUM> by undergoing a dielectric deposition process <NUM>. This PECVD dielectric layer <NUM> could be silicon nitride, amorphous silicon, amorphous SiC, or any other non-oxide based PECVD deposited dielectric relevant to superconducting devices based on a damascene architecture.

In previous techniques, the millitorr level vacuum in the transfer chamber of the wafer between a preclean process and a dielectric deposition process is sufficient to regrow a surface oxide on both the interconnect metal (i.e. Nb) and the ILD (i.e. silicon nitride). Typically, this oxide is approximately a monolayer thick and can only be detected by a technique like secondary ion mass spectrometry (SIMS) where detection limits are below <NUM>% for oxygen. Techniques like x-ray photoelectron spectroscopy and energy dispersive x-ray spectroscopy are not sensitive enough to detect oxygen that is formed on the dielectric and metal surfaces during this in vacuo transport step.

Claim 1:
A method of forming a superconductor device interconnect structure (<NUM>), the method comprising:
forming a first dielectric layer (<NUM>) overlying a substrate (<NUM>);
forming a superconducting interconnect element in the first dielectric layer (<NUM>), the superconducting interconnect element having a top surface aligned with a top surface of the first dielectric layer (<NUM>) to form a first interconnect layer;
moving the superconductor device interconnect structure into a dielectric deposition chamber;
performing a nitrogen trifluoride (NF<NUM>) based plasma clean etch process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer;
pumping the NF<NUM> based plasma and argon (Ar) gas from the dielectric deposition chamber while maintaining flow of N<NUM> gas into the dielectric deposition chamber; and
depositing a second dielectric layer (<NUM>) over the first interconnect layer in the dielectric deposition chamber.