Patent Description:
Cloud computing and cloud storage provides users with capabilities to store and process their data in third-party data centers. Cloud computing facilitates the ability to provision a virtual machine (VM) for a customer quickly and easily, without requiring the customer to purchase hardware or to provide floor space for a physical server. The customer may easily expand or contract the VM according to changing preferences or requirements of the customer. Typically, a cloud computing provider provisions the VM, which is physically resident on a server at the provider's data center. Customers are often concerned about the security of data in the VM, particularly since computing providers often store more than one customer's data on the same server. Customers may desire security between their own code/data and the cloud computing provider's code/data, as well as between their own code/data and that of other VMs running at the provider's site. In addition, the customer may desire security from the provider's administrators as well as against potential security breaches from other code running on the machine.

To handle such sensitive situations, cloud service providers may implement security controls to ensure proper data isolation and logical storage segregation. The extensive use of virtualization in implementing cloud infrastructure results in unique security concerns for customers of cloud services as virtualization alters the relationship between an operating system (OS) and the underlying hardware, be it computing, storage, or even networking hardware. This introduces virtualization as an additional layer that itself must be properly configured, managed and secured.

In general, a VM, running as a guest under the control of a host hypervisor, relies on that hypervisor to transparently provide virtualization services for that guest. These services include memory management, instruction emulation, and interruption processing.

In the case of memory management, the VM can move (page-in) its data from a disk to be resident in memory and the VM can also move its data back out (page-out) to the disk. While the page is resident in memory, the VM (guest) uses dynamic address translation (DAT) to map the pages in memory from a guest virtual address to a guest absolute address. In addition, the host hypervisor has its own DAT mapping (from host virtual address to host absolute address) for the guest pages in memory and it can, independently and transparently to the guest, page the guest pages in and out of memory. It is through the host DAT tables that the hypervisor provides memory isolation or sharing of guest memory between two separate guest VMs. The host is also able to access the guest memory to simulate guest operations, when necessary, on behalf of the guest.

In the case of instruction emulation and interruption processing, when the guest executes a particular instruction, based on controls set by the hypervisor, the machine gives control back to the hypervisor so that the hypervisor can emulate that particular instruction on behalf of the guest. Load program status word (LPSW) or load control (LCTL) instructions, for example, may be emulated by the hypervisor so that it can monitor interruption enablement and present pending interruptions being maintained by the hypervisor to the guest in the proper priority. Document <CIT> is considered to be a relevant prior art that is related to securing a trusted VM from an untrusted hypervisor by controlling the access of the hypervisor via a firmware to a protected memory of the VM.

In accordance with one or more embodiments, a method is provided by a secure interface control of a computer that provides a partial instruction interpretation for an instruction which enables an interruption. The secure interface control fetches a program status word or a control register value from a secure guest storage. The secure interface control notifies an untrusted entity of guest interruption mask updates. The untrusted entity is executed on and in communication with hardware of the computer through the secure interface control to support operations of a secure entity executing on the untrusted entity. The secure interface control receives, from the untrusted entity, a request to present a highest priority, enabled guest interruption in response to the notifying of the guest interruption mask updates. The secure interface control moves interruption information into a guest prefix page and injecting the interruption in the secure entity when an injection of the interruption is determined to be valid. The technical effects and benefits of the one or more embodiment herein include reducing complexity and risk by having this complex code reside in a single place without allowing access by the untrusted entity to the secure guest state or memory.

In accordance with one or more embodiments or the above method embodiment, the method can further include issuing, by the secure entity, load program status word or load control that is being monitored by the untrusted entity.

In accordance with one or more embodiments or any of the above method embodiments, the method can further include loading, by the secure interface control, the program status word or control register in response to the fetching.

In accordance with one or more embodiments or any of the above method embodiments, the method can further include prioritizing, by the untrusted entity, pending and enabled interruptions to determine the highest priority, enabled guest interruption.

In accordance with one or more embodiments or any of the above method embodiments, the method can further include storing, by the untrusted entity, interruption information for the highest priority, enabled guest interruption in non-secure storage.

In accordance with one or more embodiments or any of the above method embodiments, the untrusted entity can provide the interruption information in a state description.

In accordance with one or more embodiments or any of the above method embodiments, the untrusted entity can issue an instruction to provide the interruption information to the secure interface control and the interruption information is passed as a parameter for the instruction.

In accordance with one or more embodiments or any of the above method embodiments, the method can further include issuing, by the secure interface control, an exception to the untrusted entity when the injection of the interruption is determined to be invalid. The technical effects and benefits of the one or more embodiment herein include reducing complexity and risk by having this complex code reside in a single place without allowing access by the untrusted entity to the secure guest state or memory.

In accordance with one or more embodiments or any of the above method embodiments, the method can further include executing, by the secure entity, an interruption handler in response to receiving the injected interruption,.

In accordance with one or more embodiments or any of the above method embodiments, the secure entity can include a secure guest and the untrusted entity comprises a hypervisor.

In accordance with one or more embodiments, any of the above method embodiments can be implemented as a computer program product or system.

Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

The diagrams depicted herein are illustrative. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term "coupled" and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.

The invention is defined in the independent claims <NUM>, <NUM> and <NUM>. One or more embodiments herein leverage an efficient, lightweight interface between the software and the machine to provide additional security. In this case, this interface is used to allow a secure interface control to emulate a majority of an interruption enablement instructions (e.g., Load Program Status Word or Load Control) while still allowing an untrusted entity to maintain pending interruptions on behalf of a secure entity. This pending interruption structure is required by the untrusted entity to handle the prioritization of interruptions based on the secure entity not being dispatched on the hardware. The technical effects and benefits of the one or more embodiment herein include reducing complexity and risk by having this complex code reside in a single place without allowing access by the untrusted entity to the secure guest state or memory.

A virtual machine (VM), running as a guest under the control of a host hypervisor (e.g., an untrusted entity), relies on that hypervisor to transparently provide virtualization services for that guest. These services can apply to any interface between a secure entity and another untrusted entity that traditionally allows access to the secure resources by this other entity. As mentioned previously, these services can include, but are not limited to memory management, instruction emulation, and interruption processing. For example, for interrupt and exception injection, the hypervisor typically reads and/or writes into a prefix area (low core) of the guest. The term "virtual machine" or "VM" as used herein refers to a logical representation of a physical machine (computing device, processor, etc.) and its processing environment (operating system (OS), software resources, etc.). The VM is maintained as software that executes on an underlying host machine (physical processor or set of processors). From the perspective of a user or software resource, the VM appears to be its own independent physical machine. The terms "hypervisor" and "VM Monitor (VMM)" as used herein refer to a processing environment or platform service that manages and permits multiple VM's to execute using multiple (and sometimes different) OS's on a same host machine. It should be appreciated that deploying a VM includes an installation process of the VM and an activation (or starting) process of the VM. In another example, deploying a VM includes an activation (or starting) process of the VM (e.g., in case the VM is previously installed or already exists).

In presently available technical solutions, the hypervisor (e.g., z/VM® by IBM® or open source software Kernel Based Virtual machine (KVM)) dispatches a new VM virtual CPU (vCPU) on a physical processing unit, or host server, by issuing a Start-Interpretive-Execution (SIE) instruction which causes the SIE Entry millicode to be invoked. Millicode is trusted firmware that operates as an extension to the processor hardware. The operand of the SIE instruction is a control block, referred to as the state description, which contains the guest state. During SIE Entry, this guest state (including general purpose and control registers, guest instruction-address and guest program-status-word (PSW)) is loaded by millicode into the hardware. This allows the guest vCPU to run on the physical processor. While the vCPU is running on the hardware, the guest state is maintained in the hardware. At some point, the hardware/millicode must return control back to the hypervisor. This is often referred to as SIE Exit. This may be required, for example, if this vCPU executes an instruction which requires emulation by the hypervisor or if the vCPU time-slice (i.e., the time allocated for this vCPU to run on the physical processor) expires. Existing hypervisors rely on using such an interface through the SIE instruction to dispatch vCPUs.

In order to facilitate and support secure guests (e.g., secure entity), a technical challenge exists where additional security is required between the hypervisor and the secure guests without relying on the hypervisor, such that the hypervisor cannot access data from the VM, and hence, cannot provide services in the way described above.

The secure execution described herein provides a hardware mechanism to guarantee isolation between secure storage and non-secure storage as well as between secure storage belonging to different secure users. For secure guests, additional security is provided between the "untrusted" non-secure hypervisor and the secure guests. In order to do this, many of the functions that the hypervisor typically does on behalf of the guests need to be incorporated into the machine. A new secure interface control, also referred to herein as "UV", is described herein to provide a secure interface between the hypervisor and the secure guests. The terms secure interface control and UV are used interchangeably herein. The secure interface control works in collaboration with the hardware to provide this additional security.

The secure interface control, in one example, is implemented in internal, secure, and trusted hardware and/or firmware. For a secure guest or entity, the secure interface control provides the initialization and maintenance of the secure environment as well as the coordination of the dispatch of these secure entities on the hardware. While the secure guest is actively using data and it is resident in host storage, it is kept "in the clear" in secure storage. Secure guest storage can be accessed by that single secure guest - this being strictly enforced by the hardware. That is, the hardware prevents any non-secure entity (including the hypervisor or other non-secure guests) or different secure guest from accessing that data. In this example, the secure interface control runs as a trusted part of the lowest levels of firmware. The lowest level, or millicode, is really an extension of the hardware and is used to implement the complex instructions and functions defined for example in zAarchitecture® from IBM. Millicode has access to all parts of storage, which in the context of secure execution, includes its own secure UV storage, non-secure hypervisor storage, secure guest storage, and shared storage. This allows it to provide any function needed by the secure guest or by the hypervisor in support of that guest. The secure interface control also has direct access to the hardware which allows the hardware to efficiently provide security checks under the control of conditions established by the secure interface control.

In accordance with one or more embodiments of the present invention, a secure-storage bit is provided in the hardware to mark a secure page. When this bit is set, the hardware prevents any non-secure guest or hypervisor from accessing this page. In addition, each secure or shared page is registered in a zone-security table and is tagged with a secure-guest-domain identification (ID). When the page is non-secure it is marked as such in the zone-security table. This zone-security table is maintained by the secure interface control per partition or zone. There is one entry per host absolute page which is used by the hardware on any DAT translation made by a secure entity to verify that the page is only accessed by the secure guest or entity that owns it.

In accordance with one or more embodiments of the present invention, the software uses an UV Call (UVC) instruction to request the secure interface control to perform a specific action. For example, the UVC instruction can be used by the hypervisor to initialize the secure interface control, create the secure guest domain (e.g., secure guest configuration), and create the virtual CPUs within that secure configuration. It can also be used to import (decrypt and assign to secure guest domain) and export (encrypt and allow host access to) a secure guest page as part of the hypervisor page-in or page-out operations. In addition, the secure guest has the ability to define storage shared with the hypervisor, make secure-storage shared, and make shared-storage secure.

To provide security, when the hypervisor is transparently paging the secure guest data in and out, the secure interface control, working with the hardware, provides and guarantees the decryption and encryption of the data. In order to accomplish this, the hypervisor is required to issue new UVCs when paging the guest secure data in and out. The hardware, based on controls setup by the secure interface control during these new UVCs, will guarantee that these UVCs are indeed issued by the hypervisor.

In this new secure environment, whenever the hypervisor is paging-out a secure page, it is required to issue a new convert from secure storage (export) UVC. The UV, or secure interface control, in response to this export UVC, will <NUM>) indicate that the page is "locked" by the UV, <NUM>) encrypt the page, <NUM>) set the page to non-secure, and, <NUM>) reset the UV lock. Once the export UVC is complete, the hypervisor can now page-out the encrypted guest page.

In addition, whenever the hypervisor is paging-in a secure page, it must issue a new convert to secure storage (import) UVC. The UV, or secure interface control, in response to this import UVC, will <NUM>) mark the page as secure in the hardware, <NUM>) indicate that the page is "locked" by the UV, <NUM>) decrypt the page, <NUM>) set authority to a particular secure guest domain, and <NUM>) reset the UV lock. Whenever an access is made by a secure entity, the hardware performs authorization checks on that page during translation. These checks include <NUM>) a check to verify that the page does indeed belong to the secure guest domain which is trying to access it and <NUM>) a check to make sure the hypervisor has not changed the host mapping of this page while this page has been resident in guest memory. Once a page is marked as secure, the hardware prevents access to any secure page by either the hypervisor or by a non-secure guest VM. The additional translation steps prevent access by another secure VM and prevent remapping by the hypervisor.

There are cases where the hypervisor emulates instructions on behalf of a non-secure guest. For a secure guest, however, the secure interface control must intervene and provide any function which might allow an "untrusted" hypervisor to compromise the secure guest state. This intervention may be necessary for a number of reasons. For example, emulation of this instruction may require access to secure guest memory or to secure guest facilities. In some cases, the UV will completely emulate the instruction. In other cases, the secure interface control will complete emulation of the instruction but will notify the Hypervisor of some update to the guest state. In yet other cases, an interface is used to pass limited information between the secure interface control and hypervisor without compromising the guest state. This approach leverages the lightweight interface between the secure interface control and hypervisor allowing us to minimize, in this case, the duplication of the pending interruption structure in the secure interface control. This pending interruption structure is Turning now to <FIG>, a table <NUM> for zone security is generally shown in accordance with one or more embodiments of the present invention. The zone-security table <NUM> shown in <FIG> is maintained by the secure interface control and is used by the secure interface control and hardware to guarantee secure access to any page accessed by a secure entity. The zone-security table <NUM> is indexed by the host absolute address <NUM>. That is, there is one entry for each page of host absolute storage. Each entry includes information that is used to verify the entry as belonging to the secure entity making the access.

Further, as shown in <FIG>, the zone-security table <NUM> includes a secure domain ID <NUM> (identifies the secure domain associated with this page); a UV-bit <NUM> (indicates that this page was donated to the secure interface control and is owned by the secure interface control); a disable address compare (DA)-bit <NUM> (used to disable the host address pair compare in certain circumstances such as when a secure interface control page that is defined as host absolute does not have an associated host virtual address); a shared (SH)-bit <NUM> (indicates that the page is shared with the non-secure hypervisor) and a host virtual address <NUM> (indicates the host virtual address registered for this host absolute address, which is referred to as the host-address pair). Note that a host-address pair indicates a host absolute and associated, registered host virtual address. The host-address pair represents the mapping of this page, once imported by the hypervisor, and the comparison guarantees that the host does not remap that page while it is being used by the guest.

Dynamic address translation (DAT) is used to map virtual storage to real storage. When a guest VM is running as a pageable guest under the control of a hypervisor, the guest uses DAT to manage pages resident in its memory. In addition, the host, independently, uses DAT to manage those guest pages (along with its own pages) when the pages are resident in its memory. The hypervisor uses DAT to provide isolation and/or sharing of storage between different VMs as well as to prevent guest access to hypervisor storage. The hypervisor has access to all of the guests' storage when guests are running in a non-secure mode.

DAT enables isolation of one application from another while still permitting them to share common resources. Also, it permits the implementation of VMs, which may be used in the design and testing of new versions of OSs along with the concurrent processing of application programs. A virtual address identifies a location in virtual storage. An address space is a consecutive sequence of virtual addresses, together with the specific transformation parameters (including DAT tables) which allow each virtual address to be translated to an associated absolute address which identifies that address with a byte location in storage.

DAT uses a multi-table lookup to translate the virtual address to the associated absolute address. This table structure is typically defined and maintained by a storage manager. This storage manager transparently shares the absolute storage between multiple programs by paging out one page, for example, to bring in another page. When the page is paged-out, the storage manager will set an invalid bit in the associated page table, for example. When a program tries to access a page that was paged-out, the hardware will present a program interruption, often referred to as a page fault, to the storage manager. In response, the storage manager will page-in the requested page and reset the invalid bit. This is all done transparent to the program and allows the storage manager to virtualize the storage and share it among various different users.

When a virtual address is used by a CPU to access main storage, it is first converted, by means of DAT, to a real address, and then, by means of prefixing, to an absolute address. The designation (origin and length) of the highest-level table for a specific address space is called an address-space-control element (ASCE) and defines the associated address space.

Turning now to <FIG>, example virtual address spaces <NUM> and <NUM> and an absolute address space <NUM> for performing DAT are generally shown in accordance with one or more embodiments of the present invention. In the example shown in <FIG>, there are two virtual address spaces: virtual address space <NUM> (defined by address space control element (ASCE) A <NUM>) and virtual address space <NUM> (defined by ASCE B <NUM>). Virtual pages A1. V 212a1, A2. V 212a2, and A3. V 212a3 are mapped, by the storage manager in a multi-table (segment <NUM> & page tables 232a, 232b) lookup, using ASCE A <NUM>, to absolute pages A1. A 220a1, A2. A 220a2 and A3. Similarly, virtual pages B1. V 214b1 and B2. V 214b2 are mapped in a two-table <NUM> & <NUM> lookup, using ASCE B <NUM>, to absolute pages B1. A 222b1 and B2. A 222b2, respectively.

Turning now to <FIG>, an example of a nested, multi-part DAT translation used to support a VM running under a hypervisor is generally shown in accordance with one or more embodiments of the present invention. In the example shown in <FIG>, guest A virtual address space A <NUM> (defined by guest ASCE (GASCE) A <NUM>) and guest B virtual address space B <NUM> (defined by GASCEB <NUM>) both reside in a shared host (hypervisor) virtual address space <NUM>. As shown, virtual page A1. GV 310a1, A2. GV 310a2, and A3. GV 310a3, belonging to guest A, are mapped, by the guest A storage manager, using GASCEA <NUM> to guest absolute pages A1. HV 340a1, A2. HV 340a2, and A3. HV 340a3, respectively; virtual page B1. GV 320b1 and B2. GV 320b2, belonging to guest B, are mapped, independently by the guest B storage manager, using GASCEB <NUM> to guest absolute pages B1. HV 360b1 and B2. HV 360b2, respectively. In this example, these guest absolute pages map directly into the shared host virtual address space <NUM> and subsequently go through an additional host DAT translation to a host absolute address space <NUM>. As shown, host virtual addresses A1. HV 340a1, A3. HV 340a3, and B1. HV 360b1 are mapped, by the host storage manager using host ASCE (HASCE) <NUM> to A1. HA 370a1, A3. HA 370a3, and B1. Host virtual address A2. HV 340a2, belonging to guest A, and B2. HV 360b2, belonging to guest B, are both mapped to the same host absolute page AB2. This enables data to be shared between these two guests. During the guest DAT translation, each of the guest table addresses is treated as a guest absolute and undergoes an additional, nested host DAT translation.

Embodiments of the present invention described herein provide secure guest and UV storage protection. Access to secure storage by non-secure guests and the hypervisor is prohibited. The hypervisor provides that, for a given resident secure guest page, the following occurs. The associated host absolute address is only accessible through a single hypervisor (host) DAT mapping. That is, there is a single host virtual address that maps to any given host absolute address assigned to a secure guest. The hypervisor DAT mapping (host virtual to host absolute) associated with a given secure guest page does not change while it is paged-in. The host absolute page associated with a secure guest page is mapped for a single secure guest.

Sharing of storage between secure guests is also prohibited according to one or more embodiments of the present invention. Storage is shared between a single secure guest and the hypervisor under control of the secure guest. UV storage is secure storage and is accessible by the secure control interface but not the guests/hosts. Storage is allocated to the secure control interface by the hypervisor. According to one or more embodiments of the present invention, any attempted violation of these rules is prohibited by the hardware and secure control interface.

Turning now to <FIG>, an example of mapping of secure guest storage is generally shown in accordance with one or more embodiments of the present invention. <FIG> resembles <FIG>, except that the example of <FIG> does not allow for sharing of storage between secure guest A and secure guest B. In the non-secure example of <FIG>, both host virtual address A2. HV 340a2, belonging to guest A, and B2. HV 360b2, belonging to guest B, are mapped to the same host absolute page AB2. In the secure guest storage example of <FIG>, host virtual address A2. HV 340a2, belonging to guest A, maps to host absolute address A2. HA 490a, whereas B2. HV 360b2, belonging to guest B, maps to its own B2. In this example, there is no sharing between secure guests.

While the secure guest page resides on disk, it is encrypted. When the hypervisor pages-in a secure guest page, it issues a UV Call (UVC), which causes the secure control interface to mark the page as secure (unless shared), decrypt it (unless shared), and register it (in the zone-security table) as belonging to the appropriate secure guest (guest A, for example). In addition, it registers the associated host virtual address (A3. HV 340a3, for example) to that host absolute page (referred to as host-address pair). If the hypervisor fails to issue the correct UVC, it receives an exception when trying to access the secure guest page. When the hypervisor pages out a guest page, a similar UVC is issued which encrypts the guest page (unless shared) before marking the guest page as non-secure and registering it in the zone-security table as non-secure.

In an example having five given host absolute pages K, P, L, M, and N, each of the host absolute pages are marked as secure by the secure control interface when the hypervisor pages them in. This prevents non-secure guests and the hypervisor from accessing them. Host absolute pages K, P, and M are registered as belonging to guest A when the hypervisor pages them in; host absolute pages L and N are registered to guest B when paged-in by the Hypervisor. Shared pages, pages shared between a single secure guest and the hypervisor, are not encrypted or decrypted during paging. They are not marked as secure (allows access by hypervisor) but are registered with a single secure guest domain in the zone-security table.

In accordance with one or more embodiments of the present invention, when a non-secure guest or the hypervisor tries to access a page that is owned by a secure guest, the hypervisor receives a secure-storage access (PIC3D) exception. No additional translation step is required to determine this.

In accordance with one or more embodiments, when a secure entity tries to access a page, the hardware performs an additional translation check that verifies that the storage does indeed belong to that particular secure guest. If not, a non-secure access (PIC3E) exception is presented to the hypervisor. In addition, if the host virtual address being translated does not match the host virtual address from the registered host-address pair in the zone-security table, a secure-storage violation ('3F'x) exception is recognized. To enable sharing with the hypervisor, a secure guest may access storage that is not marked as secure as long as the translation checks allow for access.

Turning now to <FIG>, a system schematic <NUM> of a DAT operation is generally shown in accordance with one or more embodiments of the present invention. The system schematic <NUM> includes a host primary virtual address space <NUM> and a host home virtual address space <NUM>, from which pages are translated (e.g., see host DAT translation <NUM>; note that the dotted lines represent mapping through the DAT translation <NUM>) to a hypervisor (host) absolute address space <NUM>. For instance, <FIG> illustrates the sharing of host absolute storage by two different host virtual address spaces and also the sharing of one of those host virtual addresses between not only two guests but, in addition, with the host itself. In this regard, the host primary virtual address space <NUM> and the host home virtual address space <NUM> are examples of two host virtual address spaces, each of which is addressed by a separate ASCE, the host primary ASCE (HPASCE) <NUM> and host home ASCE (HHASCE) <NUM>, respectively. Note that all secure interface control storage (both virtual and real) is donated by the hypervisor and marked as secure. Once donated, the secure interface control storage can only be accessed by the secure interface control for as long as an associated secure entity exists.

As illustrated, the host primary virtual address space <NUM> includes a Guest A absolute page A1. HV, a Guest A absolute page A2. HV, a guest B absolute page B1. HV, and a host virtual page H3. The host home virtual address space <NUM> includes a secure-interface-control virtual page U1. HV, a host virtual page H1. HV, and a host virtual page H2.

In accordance with one or more embodiments of the present invention, all secure guest (e.g., secure Guest A & secure Guest B) storage is registered, in the zone-security table described herein, as belonging to a secure guest configuration, and the associated host virtual address (e.g., A1. HV) is also registered as part of a host-address pair. In one or more embodiments, all secure guest storage is mapped in the host primary virtual space. In addition, all secure interface control storage is registered, also in the zone-security table, as belonging to the secure interface control and may be further differentiated in the zone-security table based on the associated secure guest domain. In accordance with one or more embodiments of the present invention, UV virtual storage is mapped in host home virtual space and the associated host virtual address is registered as part of the host-address pair. In accordance with one or more embodiments, UV real storage does not have an associated host virtual mapping, and the DA bit in the zone-security table (which indicates that the virtual address comparison is disabled) is set to indicate this. Host storage is marked as non-secure and is also registered in the zone-security table as non-secure.

Thus, in the case where 'guest absolute = host virtual,' the hypervisor (host) primary DAT tables (defined by the HPASCE <NUM>) translate the pages of the host primary virtual address space <NUM> as follows: the Guest A Absolute Page A <NUM>. 14V is mapped to a Host Absolute A1. HA belonging to Secure Guest A; the Guest A Absolute Page A2. HV is mapped to a Host Absolute A2. HA belonging to Secure Guest A; the Guest B Absolute Page B1. HV is mapped to a Host Absolute B1. HA belonging to Secure Guest B; and the Host Virtual Page H3. HV is mapped to a Host Absolute Page H3. HA Non-Secure Host (and there is no host-address pair since it is non-secure). Further, the hypervisor (host) home DAT tables (defined by the HHASCE <NUM>) translate the pages of the host home virtual address space <NUM> as follows: the Secure Interface Control Virtual Page U1. HV is mapped to a Host Absolute Page U1. HA defined as Secure UV Virtual; the Host Virtual Page H1. HV is mapped to a Host Absolute Page H1. HA defined as Non-Secure; and the Host Virtual Page H2. HV is mapped to a Host Absolute Page H2. HA defined as Non-Secure. There is no host-address pair associated with either H1. HA since they are non-secure.

In operation, if a secure guest tries to access a secure page assigned to the secure interface control, a secure-storage violation (`3F'X) exception is presented by the hardware to the hypervisor. If a non-secure guest or the hypervisor tries to access any secure page (including those assigned to the secure interface control), a secure-storage access ('3D'X) exception is presented by the hardware to the hypervisor. Alternatively, an error condition can be presented for attempted accesses made to secure interface control space. If the hardware detects a mismatch in the secure assignment (e.g., the storage is registered in the zone-security table as belonging to a secure guest rather than to the secure interface control, or there is mismatch in host-address pair being used with the registered pair) on a secure interface control access, a check is presented.

In other words, the host primary virtual address space <NUM> includes host virtual pages A1. HV (belonging to secure guest A) and B1. HV (belonging to secure guest B), which map to host absolute A1. HA, and B1. HA, respectively. In addition, the host primary virtual address space <NUM> includes host (hypervisor) page H3. HV, which maps to host absolute H3. The host home virtual space <NUM> includes two host virtual pages H1. HV, which map into host absolute pages H1. Both the host primary virtual address space <NUM> and the host home virtual address space <NUM> map into the single host absolute <NUM>. The storage pages belonging to secure guest A and secure guest B are marked as secure and registered in the zone-security table <NUM> shown in <FIG> with their secure domains and associated host virtual addresses. The host storage, on the other hand, is marked as non-secure. When the hypervisor is defining the secure guests, it must donate host storage to the secure interface control to use for secure control blocks needed in support of these secure guests. This storage can be defined in either host absolute or host virtual space and, in one example, specifically, in host home virtual space. Returning to <FIG>, a host absolute pages U1. HA Secure UV Absolute is secure-interface-control storage that is defined as host absolute storage. As a result, these pages are marked as secure and registered in the zone-security table <NUM> shown in <FIG> as belonging to the secure interface control and with an associated secure domain. Since the pages are defined as host absolute addresses, there is no associated host virtual address so the DA-bit is set in the zone-security table <NUM>.

After the translation, an example of the Hypervisor (Host) Absolute Address Space <NUM> can be found in <FIG>. The <FIG> a system schematic <NUM> regarding a secure interface control memory is depicted according to one or more embodiments of the present invention. The system schematic <NUM> illustrates a Hypervisor (Host) Absolute Address Space <NUM> including a Host Absolute Page A2. HA Secure Guest A (for A2. HV); a Host Absolute Page B1. HA Secure Guest B (for B1. HV); a Host Absolute Page H1. HA Non-Secure (Host); a Host Absolute Page H2. HA Non-Secure (Host); a Host Absolute Page U3. HA Secure UV Real (no HV mapping); a Host Absolute Page U1. HA Secure UV Virtual (for U1. HV); and a Host Absolute Page A1. HA Secure Guest A (for A1.

Turning now to <FIG>, a process flow <NUM> for an import operation is generally shown according to one or more embodiments of the present invention. When a secure guest accesses a page that was paged-out by the hypervisor, a sequence of events such as that shown in the process flow <NUM> occur in order to securely bring that page back in. The process flow <NUM> beings at block <NUM>, where the secure guest accesses the guest virtual page. Since the page, for example, is invalid, the hardware presents a host page fault, indicated by program-interruption-code <NUM> (PIC <NUM>), to the hypervisor (see block <NUM>). The hypervisor, in turn, identifies an available non-secure host absolute page for this guest page (see block <NUM>) and pages-in the encrypted guest page to the identified host absolute page (see block <NUM>).

At block <NUM>, the host absolute page is then mapped in the appropriate (based on host virtual address) host DAT tables. At block <NUM>, the hypervisor host then re-dispatches the secure guest. At block <NUM>, the secure guest re-accesses the guest secure page. The page fault no longer exists but since this a secure guest access and the page is not marked as secure in the zone-security table <NUM> of FIG. <NUM>, the hardware presents a non-secure-storage exception (PIC3E) to the hypervisor, at block <NUM>. This PIC3E prevents access by the guest to this secure page until the necessary import has been issued. Next, the process flow <NUM> proceeds to "A", which is connected to <FIG>.

Turning now to <FIG>, a process flow <NUM> for performing an import operation is generally shown in accordance with one or more embodiments of the present invention. A well-behaved hypervisor (e.g., performing in an expected manner without errors), in response to the PIC3E, will issue an import UVC (see block <NUM>). Note that at this point, a page to be imported is marked as non-secure and can only be accessed by the hypervisor, other non-secure entities, and the secure interface control. It cannot be accessed by secure guests.

As part of the import UVC, the trusted firmware acting as the secure interface control checks to see if this page is already locked by the secure interface control (see decision block <NUM>). If it is, the process flow <NUM> proceeds to block <NUM>. At block <NUM>, a "busy" return code is returned to the hypervisor that will, in response, delay (see block <NUM>) and reissue the Import UVC (the process flow <NUM> returns to block <NUM>). If the page is not already locked then, the process flow <NUM> proceeds to decision block <NUM>.

At decision block <NUM>, the secure interface control checks to see if the page is a page which is shared with the non-secure hypervisor. If it is shared (the process flow <NUM> proceeds to decision block <NUM>), the secure interface control registers the host absolute address in the zone-security table with the associated secure guest domain, host virtual address and as shared. This page remains marked as non-secure. This completes the import UVC and the page is now available to be accessed by the guest. Processing continues with the hypervisor re-dispatching guest (block <NUM>) and the secure guest accessing the page successfully (block <NUM>).

If the host virtual page to be imported is not shared with the hypervisor (the process flow <NUM> proceeds to block <NUM>), the secure interface control will mark the page as secure, so that the hypervisor can no longer access the page. At block <NUM>, the secure interface control locks the page, so that no other UVC can modify the page status. Once the lock is set (at block <NUM>), the secure interface control will verify that the contents of the guest page did not change while it was encrypted. If they did change then an error return code is returned to the hypervisor, otherwise, the secure interface control will decrypt the secure page.

At block <NUM>, the secure interface control unlocks the page, allowing access by other UVCs, registers the page in the zone-security table, as secure and associated with the appropriate guest domain and host virtual address to complete the host-address HV->HA pair. This allows access by the guest and completes the UVC.

Turning now to <FIG>, a process flow <NUM> regarding a donated memory operation is generally shown in accordance with one or more embodiments of the present invention. The process flow <NUM> begins at block <NUM>, where a hypervisor issues a query - UVC to the secure interface control. At block <NUM>, the secure interface control returns data (e.g., Query UVC). This data can include an amount of base zone-specific host-absolute storage required; an amount of base secure-guest-domain-specific host-absolute storage required; an amount of variable secure-guest-domain-specific host-virtual storage required per MB; and/or amount of base secure-guest-CPU-specific host-absolute storage required.

At block <NUM>, the hypervisor reserves base host-absolute zone-specific storage (e.g., based on a size returned by query UVC). At block <NUM>, the hypervisor issues an initialization to the secure interface control. In this regard, the hypervisor can issue an initialize UVC that provides donated storage for the UV control blocks that are needed to coordinate between the secure guest configurations for the entire zone. The initialize UVC specifies a base zone-specific storage origin.

At block <NUM>, the secure interface control implements the initialization (e.g., initialize UVC) by registering donated storage to UV and marking as secure. For the initialize UVC, the secure interface control can mark donated storage as secure; assign some of that donated storage for the zone-security table; and register the donated storage in zone-security table for UV use with a unique secure-domain, but with no associated secure-guest-domain and as having no associated host-virtual address pair.

At block <NUM>, the hypervisor reserves storage (e.g., base and variable secure-guest-domain-specific storage). For example, the hypervisor reserves base and variable (e.g., based on a size of secure-guest-domain storage) secure-guest-domain-specific storage (e.g., a size returned by the query UVC). At block <NUM>, the hypervisor issues a create configuration to the secure interface control. In this regard, the hypervisor can issue a create-secure-guest-config UVC that specifies base and variable secure-guest-domain-specific storage origin. Further, the create-secure-guest-config UVC provides donated storage for the UV control blocks that are needed to support this secure guest configuration.

At block <NUM>, the secure interface control implements the create configuration (e.g., create-secure-guest-config UVC). For the create-secure-guest-config UVC, the secure interface control can mark donated storage as secure; register the donated storage in the zone-security table for UV use; and register the donated storage with the associated secure-guest-domain. The donated base (host-absolute) storage is registered as having no associated host-virtual address pair. The donated variable (host-virtual) storage is registered with the associated host-virtual address pair.

At block <NUM>, the hypervisor reserves base secure-guest-CPU-specific storage (e.g., a size returned by the query-UV). At block <NUM>, the hypervisor specifies a storage origin. For instance, the hypervisor issues to the UV create-secure-guest-CPU that specifies a base secure-guest-CPU-specific storage origin. At block <NUM>, the secure interface control implements the create-CPU (e.g., create-secure-guest-CPU UVC). For the create-secure-guest-CPU UVC, the secure interface control can mark donated storage as secure and register donated storage in the zone-security table for UV use, but with no associated secure-guest-domain and as having no associated host-virtual address pair.

Turning now to <FIG>, a process flow <NUM> regarding a transition of non-secure hypervisor pages to secure pages of a secure interface control is generally shown in accordance with one or more embodiments of the present invention. In the process flow <NUM>, three hypervisor pages are shown (e.g., a non-secure hypervisor Page A, a non-secure hypervisor Page B, and a non-secure hypervisor Page C).

The hypervisor (non-secure) Pages A, B and C can be accessed by a non-secure entity (including the hypervisor). Further, hypervisor (non-secure) Pages A, B and C are marked as non-secure (NS), along with registered in a zone-security table (e.g., the zone-security table <NUM> shown in <FIG>) as non-secure and non-shared. At arrow <NUM>, an initialize UVC is issued, which transitions Guest Page A to secure interface control real storage page <NUM> associated with an entire zone (UV2). The secure interface control real storage <NUM> can be marked as secure, along with registered in a zone-security table (e.g., the zone-security table <NUM> shown in <FIG>) as UV with no secure guest domain and no hypervisor to host absolute (HV->HA) mapping. Instead it is registered with a unique UV2 secure domain and the DA-bit is set to <NUM>. Note that the secure interface control real storage <NUM> can be accessed by the secure interface control as real.

From the hypervisor (Non-secure) Page B, at arrow <NUM>, create-SG-config or create-SG-CPU UVC is issued, which transitions this page to a secure interface control real storage <NUM> associated with a secure guest domain (UVS). The secure interface control real storage <NUM> can be marked as secure, along with registered in a zone-security table (e.g., the zone-security table <NUM> shown in <FIG>) as UV with an associated secure guest domain and no hypervisor to host absolute (HV->HA) mapping (i.e., DA-bit=<NUM>). Note that the secure interface control real storage <NUM> can be accessed by the secure interface control as real on behalf of a secure guest domain.

From the hypervisor (non-secure) Page C, at arrow <NUM>, create-SG-config UVC is issued, which transitions this page to a secure interface control virtual storage <NUM> associated with a secure guest domain (UVV). The secure interface control virtual storage <NUM> can be marked as secure, along with registered in a zone-security table (e.g., the zone-security table <NUM> shown in <FIG>) as UV with a secure guest domain and hypervisor to host absolute (HV->HA) mapping. Note that the secure interface control virtual storage <NUM> can be accessed as UV virtual on behalf of a secure guest domain.

Turning now to <FIG>, a process flow <NUM> regarding a secure storage access made by the program or the secure interface control is depicted in accordance with one or more embodiments. This represents the situation where the secure interface control is going to access guest storage or secure interface control storage and must tag that access correctly in order to allow the hardware to verify the security of that access. <NUM> describes this tagging of storage accesses by the secure interface control. The process flow <NUM> begins at block <NUM>, where the secure interface control determines whether it is making an access to a secure interface control storage.

If this is not an access to the secure interface control storage, then the process flow <NUM> proceeds to decision block <NUM> (as shown by the NO arrow). At decision block <NUM>, the secure interface control determines whether it is making an access to a secure guest storage. If this is not an access to the secure guest storage, then the process flow <NUM> proceeds to proceeds to "B" (which is connected to process flow <NUM> of <FIG>) which will use the default setting for non-secure accesses. If this is an access to the secure guest storage, then the process flow <NUM> proceeds to decision block <NUM>, where the secure interface control determines if a default secure guest domain is being used. If yes, then the process flow <NUM> proceeds to proceeds to "B" (which is connected to process flow <NUM> of <FIG>) which will use the default setting for secure guest accesses. If no, then the process flow <NUM> proceeds to block <NUM>. At block <NUM>, an appropriate secure guest domain is loaded into SG-secure-domain register (and proceeds to "B", which is connected to process flow <NUM> of <FIG>).

If this is an access to the secure interface control storage, then the process flow <NUM> proceeds to block <NUM> (as shown by the YES arrow). At block <NUM>, the access is tagged as secure-UV (e.g., uses UV-secure-domain register).

The process flow <NUM> then proceeds to decision block <NUM>, where the secure interface control determines whether this is an access to UVV space (e.g., SG-Config Variable Table). If it is an access to UVV space, then the process flow <NUM> proceeds to block <NUM> (as shown by the YES arrow). At block <NUM>, the access is tagged as virtual. At block <NUM>, an applicable secure guest domain is loaded into UV-secure-domain register. At block <NUM>, DAT translation and access storage is ready to begin. Returning to decision block <NUM>, if this is not an access to UVV space, then the process flow <NUM> proceeds to block <NUM> (as shown by the NO arrow). At block <NUM>, the access is tagged as real.

At decision block <NUM>, the secure interface control determines whether this is an access to UVS space (e.g., SG Configuration or CPU table). If this is an access to UVS space, then the process flow <NUM> proceeds to block <NUM> (as shown by the YES arrow). If this is not an access to UVS space, then the process flow <NUM> proceeds to block <NUM> (as shown by the NO arrow). This access would then be an access to UV2 space (e.g., Zone-Security Table). At block <NUM>, a unique UV2 secure domain is loaded into UV-secure-domain register.

<FIG> depicts a process flow <NUM> in accordance with one or more embodiments of the present invention. When a guest is dispatched, SIE Entry firmware can indicate to the hardware that a guest is running (e.g., guest mode active) and can indicate whether the guest is secure. If the guest is secure, the associated secure guest domain can be loaded into the hardware (e.g., in the SG-secure-domain register). When a program is accessing storage, the hardware can tag the access based on the current state of the program at the time of the access. <FIG> illustrates an example of this process in process flow <NUM>. At block <NUM>, the hardware can determine whether the machine is currently running in guest mode and if not, can tag the access as being a host access at block <NUM> and as being a non-secure access at block <NUM>. If the machine is running in guest mode at block <NUM>, the access can be tagged as a guest access at block <NUM> and further determine whether the current guest is a secure guest at block <NUM>. If the guest is not secure, the access can be tagged as non-secure at block <NUM>. If the guest is secure, the hardware can tag the guest as secure at block <NUM>, which can associate the secure guest with the SG-secure-domain register that was loaded when the secure guest was dispatched. For both non-secure and secure guests, a DAT status can be checked at block <NUM>. The access can be tagged as real at block <NUM>, if DAT is off. The access can be tagged as virtual at block <NUM>, if DAT is on. Once the access is tagged as real at block <NUM> with DAT off or as virtual at block <NUM> with DAT on, the hardware is ready to begin translation and access storage at block <NUM>, as further described in <FIG>.

<FIG> depicts an example of translation done by the hardware to support both secure and non-secure accesses in process flow <NUM> in accordance with one or more embodiments of the present invention. At block <NUM>, the hardware can determine whether the access is tagged as a guest translation, and if so, and the access is virtual at block <NUM>, then guest DAT can be performed at block <NUM>. During guest DAT translation, there can be nested, intermediate fetches for guest DAT tables. The table fetches can be tagged as guest real and as secure if the original translation was tagged as secure. The table fetches can also follow the translation process of process flow <NUM>. After the guest DAT is performed for an access tagged as guest virtual at block <NUM> and for any access tagged as guest real at block <NUM> (virtual=No), guest prefixing and guest memory offset can be applied at block <NUM>. At the completion of the guest translation process, the resulting address can be tagged as host virtual and as secure if the original guest translation was tagged as secure at block <NUM>. The process <NUM> can continue as for any access tagged as host virtual. If the original access is a host access at block <NUM>, (guest=No) and virtual at block <NUM>, then host DAT can be performed block <NUM>. Host table fetches can be marked as non-secure at block <NUM>. After host DAT is performed at block <NUM>, or if the original host access was tagged as real (virtual=No) at block <NUM>, then host prefixing can be applied at block <NUM>. The resulting address can be a host absolute address at block <NUM>.

<FIG> depicts an example of DAT translation with secure storage protection that can be performed by the hardware in process flow <NUM> in accordance with one or more embodiments of the present invention. Continuing from block <NUM> of <FIG>, if a secure-UV access is identified at block <NUM>, then the hardware can verify whether the storage is registered as secure-UV storage at block <NUM>, and if not, an error is presented at block <NUM>. A secure-UV access can be made by the secure control interface when accessing UV storage. If the storage is registered as secure-UV storage at block <NUM>, then protection checks can continue as may be performed for any secure access except the UV-secure-domain-register (setup by the secure control interface before making a secure-UV access) can be used as the specified secure domain for the domain check at block <NUM> where processing continues. In addition, any violation that is detected (entry point D) for a UV access at block <NUM> can be presented as an error at block <NUM> rather than an exception to the hypervisor at block <NUM> as is done for a secure guest violation at block <NUM> (Secure-UV=No).

For access that are not tagged as secure-UV accesses at block <NUM>, the hardware determines if the access is a secure guest access at block <NUM>, and if not, and if the page is marked as secure at block <NUM>, an exception can be presented to the hypervisor at block <NUM>. Otherwise, if the access is not a secure guest access at block <NUM> and the page is not marked as secure at block <NUM>, then translation is successful at block <NUM>.

If the access is a secure guest access at block <NUM> or a secure-UV access to storage registered as secure-UV storage at block <NUM>, the hardware can check to make sure the storage is registered to the secure entity associated with the access at block <NUM>. If this is a secure-UV access, the specified secure-domain can be obtained from the UV-secure-domain register (loaded by the secure control interface based on secure-UV storage being accessed) and for a secure-guest access, the specified secure-domain is obtained from the SG-secure-domain register (loaded when the secure entity is dispatched). If the storage being accessed is not registered to the specified secure-domain at block <NUM>, then for secure-UV accesses at block <NUM> an error is taken at block <NUM> and for secure-guest accesses at block <NUM> (secure-UV=No) an exception is presented to the hypervisor at block <NUM>.

For secure accesses to storage at block <NUM> and block <NUM> that are registered to the specified secure-domain at block <NUM>, if the virtual address check is disabled, i.e., the DA-bit=<NUM> at block <NUM> and the access is real at block <NUM>, then translation is complete at block <NUM>. If, however, the DA-bit=<NUM> at block <NUM> but the access is virtual at block <NUM> (real=No), then for secure-UV accesses at block <NUM> an error is taken at block <NUM> and for secure-guest accesses at block <NUM> (secure-UV=No) an exception is presented to the hypervisor at block <NUM>. If the DA-bit=<NUM> at block <NUM> and the access is a virtual access at block <NUM>, then the hardware can determine if the host virtual to host absolute mapping of the access matches that registered for this host absolute address at block <NUM>. If so, then translation completes successfully at block <NUM>. If the mapping does not match at block <NUM>, then for secure-UV accesses at block <NUM> an error is taken at block <NUM> and for secure-guest accesses at block <NUM> (secure-UV=No) an exception is presented to the hypervisor at block <NUM>. If the DA-bit=<NUM> and the access is a real access at block <NUM> (virtual=No) then for secure-UV accesses at block <NUM> an error is taken at block <NUM> and for secure-guest accesses at block <NUM> (secure-UV=No) an exception is presented to the hypervisor at block <NUM>; alternately, the translation may complete successfully at block <NUM>. Any access by the I/O subsystem at block <NUM> can check to see if the page is marked as secure at block <NUM> and if the page is secure, an exception can be presented to the hypervisor at block <NUM>; if the page is not marked as secure, the translation is successful at block <NUM>.

Various checks of storage registration and mapping can be managed collectively through zone security table interface <NUM>. For example, blocks <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> can interface with a zone security table that is associated with a same zone to manage various accesses.

As discussed herein, one or more embodiments herein leverage an efficient, lightweight ultravisor interface between the software and the machine to provide this additional security. In this case, this interface is used to allow the ultravisor to emulate a majority of an interruption enablement instructions (e.g., Load Program Status Word or Load Control) while still allowing a hypervisor to maintain pending interruptions on behalf of the guest. This pending interruption structure is required by the hypervisor to handle the prioritization of interruptions when the secure guest is not dispatched on the hardware. The technical effects and benefits of the one or more embodiment herein include reducing complexity and risk by having this complex code reside in a single place without allowing access by the hypervisor to the secure guest state or memory.

In view of the above, operations for secure interface control high-level instruction interception for interruption enablement are discussed with respect to <FIG>. Turning now to <FIG>, a process flow <NUM> for secure interface control high-level instruction interception for interruption enablement is depicted according to one or more embodiments of the present invention. The process flow <NUM> overlays a secure entity <NUM> (e.g., secure guest or container), a secure interface control <NUM>, and a untrusted entity <NUM> (e.g., hypervisor or OS) to illustrate which operation is being performed by a component of the secure environment.

The process flow <NUM> being at block <NUM>, where the secure entity <NUM> issues an instruction which may enable for interruptions (e.g., LPSW and LCTL), which is being monitored by the untrusted entity <NUM>. At block <NUM>, the secure interface control <NUM> fetches a new PSW (e.g., for LPSW) or a control register value (e.g., for LCTL) from secure guest storage. At block <NUM>, the secure interface control <NUM> loads the new PSW or control register into the secure entity state, which can be in response to the fetching.

At block <NUM>, the secure interface control <NUM> notifies the untrusted entity <NUM> of guest interruption enablement updates. At block <NUM>, the untrusted entity <NUM> prioritizes pending and enabled interruptions to determine the highest priority, enabled guest interruption. At block <NUM>, the untrusted entity <NUM> stores interruption information for highest priority interruption (e.g., the highest priority, enabled guest interruption) in non-secure storage. In one example, this non-secure storage can be the state description associated with this guest interruption. In another example, this non-secure storage is the parameter block which will be used as input into an Inject Interruption UVC instruction. The process flow <NUM> proceeds to Circle Z, which is connected to <FIG> and process flow <NUM>.

Turning now to <FIG>, a process flow <NUM> for secure interface control high-level instruction interception for interruption enablement is depicted according to one or more embodiments of the present invention. The process flow <NUM> overlays a secure entity <NUM>, a secure interface control <NUM>, and an untrusted entity <NUM> to illustrate which operation is being performed by a component of the secure environment. Note that the secure entity <NUM>, the secure interface control <NUM>, and the untrusted entity <NUM> of <FIG> are similar to the secure entity <NUM>, the secure interface control <NUM>, and the untrusted entity <NUM> of <FIG>.

The process flow <NUM> being at block <NUM>, where the untrusted entity <NUM> requests the secure interface control <NUM> to present the highest priority, enabled guest interruption. This request can be in response to the notification. In one example, this request can be a SIE dispatch with an indication that an interruption should be injected and information about that interruption. In another example, this request can be an Inject Interruption UVC instruction with the interruption information and an indication of the associated guest in the parameter block associated with the UVC. At decision block <NUM>, the secure interface control <NUM> determines whether the interruption injection is valid. For example, the secure interface control <NUM> determines whether the associated guest is enabled for the interruption being injected. If the interruption injection is not valid, the process flow <NUM> proceeds to block <NUM> (as shown by the NO arrow). At block <NUM>, the secure interface control <NUM> issues an exception the untrusted entity <NUM>.

If the interruption injection is valid, the process flow <NUM> proceeds to block <NUM> (as shown by the YES arrow). At block <NUM>, the secure interface control <NUM> moves interruption information into a guest prefix page and injects the interruption in the secure entity <NUM> (e.g., updating guest state). At block <NUM>, the secure entity <NUM> executes an interruption handler in response to receiving the injected interruption.

Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, VMs, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service.

As depicted, the following layers and corresponding functions are provided:
Hardware and software layer <NUM> includes hardware and software components.

Workloads layer <NUM> provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation <NUM>; software development and lifecycle management <NUM>; virtual classroom education delivery <NUM>; data analytics processing <NUM>; transaction processing <NUM>; and high-level Instruction interception for interruption enablement <NUM>. It is understood that these are just some examples and that in other embodiments, the layers can include different services.

Turning now to <FIG>, a system <NUM> is depicted in accordance with one or more embodiments of the present invention. The system <NUM> includes an example node <NUM> (e.g., a hosting node) that is in direct or indirect communication with one or more client devices 20A-20E, such as via a network <NUM>. The node <NUM> can be a datacenter or host server, of a cloud-computing provider. The node <NUM> executes a hypervisor <NUM>, which facilitates deploying one or more VMs <NUM> (15A-15N). The node <NUM> further includes a hardware/firmware layer <NUM> that provides direct support for functions required by the VMs 15A-N and hypervisor <NUM> as well as facilitates the hypervisor <NUM> in providing one or more services to the VMs <NUM>. In contemporary implementations communication is provided between the hardware/firmware layer <NUM> and the hypervisor <NUM>, between the hardware/firmware layer <NUM> and the VMs <NUM>, between the hypervisor <NUM> and the VMs <NUM>, and between the hypervisor <NUM> and the VMs <NUM> via the hardware/firmware layer <NUM>. In accordance with one or more embodiments, of the present invention, a secure interface control is provided in the hardware/firmware layer <NUM>, and the direct communication between the hypervisor <NUM> and the VMs <NUM> is eliminated.

For example, the node <NUM> can facilitate a client device 20A to deploy one or more of the VMs 15A-15N. The VMs 15A-15N may be deployed in response to respective requests from distinct client devices 20A-20E. For example, the VM 15A may be deployed by the client device 20A, the VM 15B may be deployed by the client device 20B, and the VM 15C may be deployed by the client device 20C. The node <NUM> may also facilitate a client to provision a physical server (without running as a VM). The examples described herein embody the provisioning of resources in the node <NUM> as part of a VM, however the technical solutions described can also be applied to provision the resources as part of a physical server.

In an example, the client devices 20A-20E may belong to the same entity, such as a person, a business, a government agency, a department within a company, or any other entity, and the node <NUM> may be operated as a private cloud of the entity. In this case, the node <NUM> solely hosts VMs 15A-15N that are deployed by the client devices 20A-20E that belong to the entity. In another example, the client devices 20A-20E may belong to distinct entities. For example, a first entity may own the client device 20A, while a second entity may own the client device 20B. In this case, the node <NUM> may be operated as a public cloud that hosts VMs from different entities. For example, the VMs 15A-15N may be deployed in a shrouded manner in which the VM 15A does not facilitate access to the VM 15B. For example, the node <NUM> may shroud the VMs 15A-15N using an IBM z Systems® Processor Resource/Systems Manager (PRISM) Logical Partition (LPAR) feature. These features, such as PRISM LPAR provide isolation between partitions, thus facilitating the node <NUM> to deploy two or more VMs 15A-15N for different entities on the same physical node <NUM> in different logical partitions.

A client device 20A from the client devices 20A-20e is a communication apparatus such as a computer, a smartphone, a tablet computer, a desktop computer, a laptop computer, a server computer, or any other communication apparatus that requests deployment of a VM by the hypervisor <NUM> of the node <NUM>. The client device 20A may send a request for receipt by the hypervisor via the network <NUM>. A VM 15A, from the VMs 15A-15N is a VM image that the hypervisor <NUM> deploys in response to a request from the client device 20A from the client devices 20A-20e. The hypervisor <NUM> is a VM monitor (VMM), which may be software, firmware, or hardware that creates and runs VMs. The hypervisor <NUM> facilitates the VM 15A to use the hardware components of the node <NUM> to execute programs and/or store data. With the appropriate features and modifications the hypervisor <NUM> may be IBM z Systems®, Oracle's VM Server, Citrix's XenServer, Vmware's ESX, Microsoft Hyper-V hypervisor, or any other hypervisor. The hypervisor <NUM> may be a native hypervisor executing on the node <NUM> directly, or a hosted hypervisor executing on another hypervisor.

Turning now to <FIG>, a node <NUM> for implementing the teachings herein is shown in according to one or more embodiments of the invention. The node <NUM> can be an electronic, computer framework comprising and/or employing any number and combination of computing device and networks utilizing various communication technologies, as described herein. The node <NUM> can be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of others.

In this embodiment, the node <NUM> has a processor <NUM>, which can include one or more central processing units (CPUs) 2001a, 2001b, 2001c, etc. The processor <NUM>, also referred to as a processing circuit, microprocessor, computing unit, is coupled via a system bus <NUM> to a system memory <NUM> and various other components. The system memory <NUM> includes read only memory (ROM) <NUM> and random access memory (RAM) <NUM>. The ROM <NUM> is coupled to the system bus <NUM> and may include a basic input/output system (BIOS), which controls certain basic functions of the node <NUM>. The RAM is read-write memory coupled to the system bus <NUM> for use by the processor <NUM>.

The node <NUM> of <FIG> includes a hard disk <NUM>, which is an example of a tangible storage medium readable executable by the processor <NUM>. The hard disk <NUM> stores software <NUM> and data <NUM>. The software <NUM> is stored as instructions for execution on the node <NUM> by the processor <NUM> (to perform process, such as the processes described with reference to <FIG>. The data <NUM> includes a set of values of qualitative or quantitative variables organized in various data structures to support and be used by operations of the software <NUM>.

The node <NUM> of <FIG> includes one or more adapters (e.g., hard disk controllers, network adapters, graphics adapters, etc.) that interconnect and support communications between the processor <NUM>, the system memory <NUM>, the hard disk <NUM>, and other components of the node <NUM> (e.g., peripheral and external devices). In one or more embodiments of the present invention, the one or more adapters can be connected to one or more I/O buses that are connected to the system bus <NUM> via an intermediate bus bridge, and the one or more I/O buses can utilize common protocols, such as the Peripheral Component Interconnect (PCI).

As shown, the node <NUM> includes an interface adapter <NUM> interconnecting a keyboard <NUM>, a mouse <NUM>, a speaker <NUM>, and a microphone <NUM> to the system bus <NUM>. The node <NUM> includes a display adapter <NUM> interconnecting the system bus <NUM> to a display <NUM>. The display adapter <NUM> (and/or the processor <NUM>) can include a graphics controller to provide graphics performance, such as a display and management of a GUI <NUM>. A communications adapter <NUM> interconnects the system bus <NUM> with a network <NUM> enabling the node <NUM> to communicate with other systems, devices, data, and software, such as a server <NUM> and a database <NUM>. In one or more embodiments of the present invention, the operations of the software <NUM> and the data <NUM> can be implemented on the network <NUM> by the server <NUM> and the database <NUM>. For instance, the network <NUM>, the server <NUM>, and the database <NUM> can combine to provide internal iterations of the software <NUM> and the data <NUM> as a platform as a service, a software as a service, and/or infrastructure as a service (e.g., as a web application in a distributed system).

Embodiments described herein are necessarily rooted in computer technology, and particularly computer servers that host VMs. Further, one or more embodiments of the present invention facilitate an improvement to the operation of computing technology itself, in particular computer servers that host VMs, by facilitating the computer servers that host VMs to host secure VMs, in which even the hypervisor is prohibited from accessing memory, registers, and other such data associated with the secure VM. In addition, one or more embodiments of the present invention provide significant steps towards the improvements of the VM hosting computing servers by using a secure interface control (also referred to herein as an "ultravisor" or "UV") that includes hardware, firmware (e.g., millicode), or a combination thereof to facilitate a separation of the secure VM and the hypervisor, and thus maintaining a security of the VMs hosted by the computing server. The secure interface control provides lightweight intermediate operations to facilitate the security, without adding substantial overhead to securing VM state during initialization/exit of VMs as described herein.

Embodiments of the invention disclosed herein may include system, method, and/or computer program product (herein a system) that implement secure interface control high-level Instruction interception for interruption enablement. Note that, for each of explanation, identifiers for elements are reused for other similar elements of different figures.

Various embodiments of the invention are described herein with reference to the related drawings. Alternative embodiments of the invention can be devised without departing from the scope of this invention. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

Additionally, the term "exemplary" is used herein to mean "serving as an example, instance or illustration. " Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms "a plurality" may be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both an indirect "connection" and a direct "connection.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.

Claim 1:
A method comprising:
fetching, by a secure interface control (<NUM>) of a computer (<NUM>) that provides a partial instruction interpretation for an instruction which enables an interruption, a program status word or a control register value from a secure guest storage (<NUM>);
notifying, by the secure interface control (<NUM>), an untrusted entity (<NUM>) of guest interruption mask updates, the untrusted entity (<NUM>) being executed on and in communication with hardware of the computer (<NUM>) through the secure interface control (<NUM>) to support operations of a secure entity (<NUM>) executing on the untrusted entity (<NUM>);
receiving, by the secure interface control (<NUM>) from the untrusted entity (<NUM>), a request to present a highest priority, enabled guest interruption in response to the notifying of the guest interruption mask updates; and
moving, by the secure interface control (<NUM>), interruption information into a guest prefix page and injecting the interruption in the secure entity (<NUM>) when an injection of the interruption is determined to be valid,
wherein the secure interface control (<NUM>) includes a secure interface implemented in internal, secure and trusted hardware and/or firmware between the untrusted entity (<NUM>) and the secure entity (<NUM>), the secure interface including a hardware mechanism that prevents the untrusted entity from accessing contents of the secure guest storage (<NUM>).