Patent Description:
For semiconductor power devices, super-junction (also referred to as charge balance) designs offer several advantages. For example, super-junction devices demonstrate reduced resistance and reduced conduction losses per unit area relative to traditional unipolar device designs. In silicon (Si) super-junction devices, an active area may be formed by implanting or diffusing a number of vertical pillars of a first dopant type (e.g., p-type) into a Si device layer of a second dopant type (e.g., n-type). The vertical pillars of these Si super-junction devices extend through the thickness (e.g., tens of micrometers) of the Si epitaxial device layer, which can be achieved using existing Si epitaxy, implantation and/or diffusion methods.

However, in silicon carbide (SiC), dopants have significantly lower diffusion coefficient /implantation range than in Si. As a result, when a feature (e.g., a vertical charge- balance region) is formed into a SiC epitaxial layer using an implantation energy that is typical of Si processing, the dopants are unable to penetrate into the SiC layer as deep as they would into the Si layer. For example, typical commercial ion implantation systems for Si device fabrication enable dopant implantation energies up to about <NUM> keV. Such implantation energies only enable dopant implantation to a maximum depth between approximately <NUM> and approximately <NUM> into the surface of a SiC epitaxial layer. Pu Hong-Bin et al (Modeling of <NUM>-SiC multi-floating-junction Schottky barrier diode) relate to an analytical model for the specific on-resistance and electric field distribution along the critical path for <NUM>-SiC multi-floating junction Schottky barrier diode. <CIT> relates to t a semiconductor device such as a power MOSFET and SIT and a method for manufacturing the same, and is particularly suitable for use in a semiconductor device made of silicon carbide. <CIT> relates to a silicon carbide semiconductor device and a method for manufacturing the same.

In a first aspect, there is provided a silicon carbide (SiC) super-junction (SJ) device according to claim <NUM>.

In a second aspect, there is provided method of manufacturing a silicon carbide (SiC) super-junction (SJ) device according to claim <NUM>.

In a third aspect, there is provided method of manufacturing a silicon carbide (SiC) super-junction (SJ) device according to claim <NUM>.

As used herein, the term "room temperature" refers to the temperature range between approximately <NUM> and approximately <NUM>.

Present embodiments are directed toward designs and methods for manufacturing SiC vertical charge-balance devices, also referred to as SiC super-junction (SiC-SJ) devices. The disclosed designs and methods are useful in the manufacture of SiC-SJ devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), diodes, as well as other SiC-SJ devices that may be useful for medium-voltage (e.g., <NUM> kV - <NUM> kV) and high-voltage (e.g., greater than <NUM> kV) power conversion related applications. As discussed below, the disclosed SiC-SJ device designs include multi-layered active cell structures implemented using repeated epitaxial growth and dopant implantation steps. As used herein, the term "multi-layered," as well as references to a particular number of layers (e.g., "two-layered," "three-layered," "four-layered,"), refers to the number of epitaxial layers of the SiC super-junction device.

The disclosed multi-layered SiC-SJ designs and manufacturing techniques enable the production of SiC-SJ devices, despite the aforementioned low diffusion coefficients of dopants in
SiC compared to Si. The disclosed multi-layered SiC-SJ designs offer reduced conduction losses and switching losses compared to existing SiC or Si power devices having the same current/voltage rating. Further, the disclosed multi-layered SiC-SJ designs enable operation at significantly higher current densities than conventional SiC high-voltage unipolar devices, and higher switching frequencies than conventional SiC high-voltage bipolar devices. The disclosed SiC-SJ device designs are also generally robust to both n-type and p-type doping variability, which improves device yield and performance. Further, having drift layers doped higher than allowed by the one-dimensional (<NUM>-D) limit of conventional designs, the disclosed SiC-SJ devices enable lower conduction losses for a given blocking voltage rating compared to conventional <NUM>-D designs. Additionally, certain disclosed SiC-SJ device embodiments may be manufactured using common semiconductor fabrication equipment, such as ion implantation systems used by existing Si/SiC device manufacturing, to provide additional cost benefits.

As discussed in detail below, the disclosed SiC-SJ active cell designs include floating regions of n-type or p-type doping (e.g., floating charge-balance blocks) that reshape the electric field in the active area of a SiC-SJ power device. These regions are referred to herein as "floating" in that are disposed within the drift layers of the SiC-SJ device and are not in contact with a device terminal. For the disclosed SiC-SJ device embodiments, as discussed below, these designs utilizing discrete floating regions enable low conduction losses and high blocking voltages while still maintaining a relatively simple fabrication process.

As set forth above, the presently disclosed SiC-SJ device embodiments' fabrication steps generally include repeated cycles of epitaxial overgrowth and ion implantation to form a multi-layered device structure. <FIG> is a schematic illustrating a cross-sectional view of the active area <NUM> of an embodiment of the invention of a SiC-SJ device <NUM> (i.e., a Schottky diode), in accordance with embodiments of the invention of the present approach. The illustrated SiC-SJ device <NUM> includes a top contact <NUM> disposed on an upper SiC epitaxial layer <NUM>. While the upper SiC epitaxial layer <NUM> is doped during epitaxial growth, the layer <NUM> of the illustrated SiC-SJ device <NUM> does not include implanted doped regions. It may be noted that, for other types of SiC-SJ devices (e.g., MOSFETs, JBS, MPS, UMOSFETs, JFETs), the upper SiC epitaxial layer <NUM> may include doped regions or other suitable features, in accordance with the present disclosure. The illustrated SiC- SJ device <NUM> also includes a bottom contact <NUM> disposed below a SiC substrate layer <NUM> of the device <NUM>.

In addition to epitaxial layer <NUM>, the active area <NUM> of the SiC-SJ device <NUM> illustrated in <FIG> includes two epitaxial layers or "charge balance" (CB) layers 24A and 24B, each having floating regions <NUM>, in accordance with the present invention. However, in certain embodiments, not forming part of the present invention, but useful for understanding it, the SiC-SJ device <NUM> may include any suitable number of CB layers (e.g., <NUM> and <NUM>, in accordance with the present invetion, <NUM>, <NUM>, <NUM>, or more, not forming part of the present invention, but useful for understanding it) yielding a multi-layered active cell structure <NUM>. As discussed below, certain embodiments of the SiC-SJ device <NUM> may include a certain number of CB layers to provide desirable blocking capability (e.g., from approximately <NUM> kV to approximately <NUM> kV). The CB layers 24A and 24B each have a dopant concentration, which may be the same or different, in certain embodiments. Similarly, the dopant concentration in the floating regions <NUM> of the drift layer 24A and in the floating regions <NUM> of the drift layer 24B may be the same or different, in certain embodiments.

In terms of dimensions, the CB layers 24A and 24B have thicknesses 32A and 32B, respectively, that may be the same or different, in certain embodiments. In terms of dimensions, the floating regions <NUM> in the drift layers 24A and 24B of the illustrated SiC-SJ device <NUM> have a particular thickness <NUM>, a particular width <NUM>, and a particular spacing <NUM>. In other embodiments, the dimensions (e.g., thickness <NUM>, width <NUM>, and/or spacing <NUM>) of the floating regions <NUM> may be different in different CB layers.

For the illustrated SiC-SJ device <NUM> of <FIG>, the floating regions <NUM> are oppositely doped relative to the remainder <NUM> of the SiC CB layers 24A and 24B. In other words, for SiC-SJ devices <NUM> having n-type SiC CB layers 24A and 24B, the floating regions <NUM> are p-type, and for SiC-SJ devices <NUM> having p-type CB layers 24A and 24B, the floating regions <NUM> are n-type. In different embodiments, these floating regions <NUM> may have different cross-sectional shapes (e.g., round, rectangular, triangular, or irregular shapes). For present embodiments, the shape of the floating regions may not substantially vary along the Z-axis.

As mentioned, the remainder <NUM> of CB layers <NUM> (i.e., the portion of the CB layers 24A and 24B that are not part of the floating regions <NUM>) has the opposite conductivity -type relative to the floating regions <NUM>. The floating regions <NUM> and the remainder <NUM> of the CB layers <NUM> each generally provide similar amounts of effective charge (e.g., per cm2 , normalized to device active area) from ionized dopants under reverse bias. As such, the illustrated charge balance structure allows the SiC-SJ device <NUM> to achieve high breakdown voltage and low on- state resistance, since the p-type semiconductor and the n-type semiconductor portions are both completely depleted under nominal blocking conditions.

It should be noted that the floating regions <NUM> in the active area <NUM> of the SiC-SJ device <NUM> are not vertically connected through (i.e., do not extend through the entire thicknesses 32A and 32B) of the CB layers <NUM>. As such, the SiC-SJ device <NUM> may be described, more specifically, as being a partial super-junction device <NUM>. It may be appreciated that this feature is in contrast to other SJ device designs in which the charge-balance regions are continuous (e.g., continuous vertical pillars that extend through the entire thicknesses 32A and 32B of the layers 24A and 24B) and are vertically connected to provide what may be described, more specifically, as a full charge-balance or full super-junction device. Full charge-balance devices are capable of providing low conduction losses and high blocking voltage. However, fabricating charge-balance regions that extend through the thicknesses 32A and 32B of layers 24A and 24B is challenging due to the aforementioned difficulty when doping SiC.

For example, in order to form charge balance regions that extend through the entire thickness of the drift region, as present in a full charge-balance device, numerous (e.g., <NUM>+) thin epitaxial growth/shallow ion implantation steps may be performed. Alternatively, high energy implantation may be used along with high stopping power masking (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high-Z metals such as platinum, molybdenum, gold), which are not common for current high-volume Si/SiC manufacturing processes. In contrast, the floating regions <NUM> of the SiC-SJ device <NUM> are amenable to existing and maturing Si/SiC fabrication techniques and infrastructure. For example, as mentioned above, present (high volume) ion implantation tooling limits implant acceleration energies to much less than IMeV (e.g., approximately <NUM> keV). At these energies, the projected range (e.g., the penetration depth) of most commonly used SiC dopants (e.g., nitrogen, phosphorus, aluminum) is approximately <NUM>µITI or less, which is suitable for implantation of the floating regions <NUM>, as discussed below.

<FIG> illustrate cross-sectional views of the SiC-SJ device <NUM> of <FIG> at various stages during a method of fabrication, in accordance with the present invention. The method begins with a first epitaxial layer 24A being formed on top of the SiC substrate layer <NUM> using epitaxial SiC growth techniques to yield the structure illustrated in <FIG>. Subsequently, as illustrated in <FIG>, the floating regions <NUM> are formed in the epitaxial layer 24A using ion implantation to yield the CB layer 24A. The dimensions and positions of the floating regions <NUM> for various embodiments are discussed in greater detail below.

Next, as illustrated in <FIG>, a second epitaxial layer 24B (i.e., another epitaxial SiC layer) is formed on top of the first drift layer 24B. Subsequently, as illustrated in <FIG>, ion implantation may be used to form the floating regions <NUM> in the epitaxial layer 24B to yield the CB layer 24B. Then, as illustrated in <FIG>, the upper SiC epitaxial layer <NUM> is formed on top of the uppermost SiC layer 24B. It should be understood that the steps illustrated in <FIG> may be repeated multiple (e.g., <NUM>, <NUM>, <NUM>, <NUM>, or more) times to yield multi-layered (e.g., three-layered, in accordance with the present invetion, four-layered, five-layered, or more) SiC-SJ device embodiments, in accordance with the present disclosure. After the upper SiC epitaxial layer <NUM> is completed, then standard device processing steps may be performed (e.g., including forming the top contact <NUM> and bottom contact <NUM> illustrated in <FIG>), to yield the SiC-SJ device <NUM>.

The performance benefits of the presently disclosed SiC-SJ device <NUM> were demonstrated through computational simulations and confirmed through fabrication and testing of various embodiments of the invention of the SiC-SJ device <NUM> illustrated in <FIG>, as presented in the electrical data below with respect to <FIG>. In particular, the device characteristics presented in <FIG> are representative of embodiments of the invention of an example 3kV SiC-SJ device <NUM> having p- type floating regions <NUM> disposed within two n-type CB layers 24A and 24B, as illustrated in <FIG>. It is presently recognized, based on the data below, that particular parameters of the SiC- SJ device <NUM> enable desirable electrical performance for the SiC-SJ <NUM>, including the doping of the layers <NUM>, the doping of the floating regions <NUM>, the thicknesses of the layers <NUM>, the thickness <NUM> of the floating regions <NUM>, the width <NUM> of the floating regions <NUM>, and the spacing <NUM> between the floating regions <NUM>, the doping of the floating regions <NUM>. Ranges for these parameters are discussed below for various embodiments.

For the embodiments of the SiC-SJ device <NUM> of <FIG>, the doping concentration of the floating regions <NUM> divided by the thickness <NUM> is greater than or equal to approximately 5xl0<NUM> cm-<NUM> and less than or equal to approximately 5xl0<NUM> cm-<NUM>. In certain embodiments, the doping concentration of the floating regions <NUM> may be greater than or equal to <NUM>×<NUM><NUM> cm-<NUM> and less than or equal to l×l0<NUM> cm-<NUM>. In certain embodiments, the doping concentration of the floating regions <NUM> may be greater than or equal to <NUM>×<NUM><NUM> cm-<NUM> and less than or equal to <NUM>×<NUM><NUM> cm-<NUM>. Additionally, in certain embodiments, the effective sheet doping concentration of the floating regions <NUM> is less than or equal to l. l×l0<NUM> cm-<NUM>. It may be appreciated that the effective sheet doping of the floating regions <NUM> may be calculated by normalizing the doping concentration of these floating regions <NUM> to the unit cell area of the SiC-SJ device. The motivation behind the upper and lower bounds of these ranges is discussed in detail below.

For the embodiments of the invention of the SiC-SJ device <NUM> of <FIG>, if the doping concentration of the p-type floating regions <NUM> is low (e.g., less than approximately 2xl0<NUM> cm-<NUM>), then the doping concentration of the n-type layers 24A and 24B would be commensurately low in order to provide a charge balanced SiC-SJ device <NUM>. <FIG> is a graph <NUM> illustrating breakdown voltage versus the spacing <NUM> between the floating regions <NUM> for embodiments of the invention the SiC-SJ device <NUM>. In particular, <FIG> illustrates the breakdown voltage for five different embodiments of the invention of the SiC-SJ
device <NUM>, each having a different dopant concentration for their respective n-type SiC epitaxial layers 24A and 24B (i.e., curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×<NUM><NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; and curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ), with different spacing <NUM> between the floating regions <NUM> (i.e., ranging from <NUM> to <NUM>). Further, for the embodiments of the invention of the SiC- SJ device <NUM> represented in <FIG>, the dopant concentration of the floating regions <NUM> is <NUM>×l0<NUM> cm-<NUM> , the thicknesses 32A and 32B of the n-type drift layers are <NUM>, the width <NUM> of the floating regions <NUM> is <NUM>, and the thickness <NUM> of the floating regions <NUM> is <NUM>.

<FIG> is a graph <NUM> illustrating room temperature specific on-resistance of a drift layer (at current density equal to <NUM> A/cm<NUM> ) versus the spacing <NUM> between the floating regions <NUM> for the various SiC-SJ device embodiments represented in <FIG>. In particular five curves are illustrated in the graph <NUM> of <FIG>, each representing a different doping concentrations of the n-type epi layers 24A and 24B (i.e., curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM> ; and curve <NUM> representing a dopant concentration of <NUM>×l0<NUM> cm-<NUM>). As may be seen in <FIG>, using the dopant concentration discussed above (i.e., <NUM>×l0<NUM> cm-<NUM>) in the layers <NUM>, the resulting specific drift on-resistance of the SiC-SJ device embodiments range from approximately <NUM> mOhm-cm<NUM> to greater than <NUM> mOhm-cm<NUM>^, when the spacing <NUM> between the floating regions <NUM> ranges between <NUM> and <NUM>. As shown in <FIG> and <FIG>, the disclosed SiC-SJ device designs enables blocking voltages greater than or equal to 3kV and specific on- resistance of drift region less than <NUM> mOhm-cm<NUM> , which represent performance improvements over conventional unipolar devices.

For the embodiments of the SiC-SJ device <NUM> of <FIG>, if the doping concentration of the floating regions <NUM> is too high (e.g., greater than approximately 5xl0<NUM> cm-<NUM>), then the feature sizes that would provide the best performance are difficult fabricate using existing SiC fabrication processes. <FIG> is a graph <NUM> illustrating breakdown voltage versus thickness <NUM> of the floating regions <NUM> for two different embodiments of the SiC-SJ device <NUM> having different doping concentrations in the floating regions <NUM> (i.e., curve <NUM> representing a doping concentration of <NUM>×l0<NUM> cm-<NUM> ; and curve <NUM> representing a doping concentration of l×lO<NUM> cm-<NUM>). For the embodiments of the SiC-SJ device <NUM> represented in <FIG>, the spacing <NUM> between the floating regions <NUM> is <NUM>, the thicknesses 32A and 32B of each of the drift layers is <NUM>, and the width <NUM> of the floating regions <NUM> is <NUM>. To increase block doping concentration above 5xl0<NUM> cm-<NUM> (e.g., l×l0<NUM> cm-<NUM> ) the thickness <NUM> of the floating regions <NUM> would become less than <NUM>, which is impractical for implant and epitaxial overgrowth processes.

For the embodiments of the SiC-SJ device <NUM> of <FIG>, to achieve a blocking voltage of <NUM> kV (as illustrated by horizontal line <NUM> in <FIG>), the thickness <NUM> of the floating regions <NUM> should be less than approximately <NUM> and the width <NUM> of the floating regions <NUM> should be less than <NUM>. Accordingly, using more moderate doping in the floating regions <NUM> enables good performance using feature sizes that are manageable using existing semiconductor fabrication processes. It may also be appreciated that fabricating floating regions <NUM> having very small thickness <NUM> and/or very narrow widths <NUM> may be difficult with the multiple epitaxial SiC regrowth steps, in which in-situ etching prior to growth is typically used and may consume a portion of the implanted floating regions <NUM>. Additionally, autodoping, outdiffusion, lateral straggle, and/or finite diffusion of implanted dopants may occur during the multiple exposures to the high temperature (e.g., greater than approximately <NUM>° C) epitaxial SiC growth steps, which may also present problems when using exceedingly small lateral features.

As discussed in greater detail below, the spacing <NUM> between the floating regions <NUM> for embodiments of the invention of the SiC-SJ device <NUM> of <FIG> may be greater than or equal to <NUM>% of the thickness of the CB layer (e.g., <NUM>% of the thickness 32A of layer 24A), and the spacing <NUM> may be less than or equal to the thickness of the CB layer thickness (e.g., the thickness 32A of the layer 24A). In certain embodiments, the spacing <NUM> between the floating regions <NUM> may be greater than or equal to <NUM> and less than or equal to approximately <NUM>. The motivation behind the upper and lower bounds of these ranges is discussed in detail below.

For the embodiments of the SiC-SJ device <NUM> of <FIG>, when the spacing <NUM> between the floating regions <NUM> is small, the SiC-SJ device <NUM> may become increasingly sensitive to process variations (e.g., lateral diffusion, variations in partem feature size, as illustrated in <FIG>. ), and variations in doping concentration throughout the drift layers 24A and 24B. As illustrated by the curve <NUM> of <FIG>, in order to maintain low drift layer specific on-resistance with narrow spacing <NUM> between the floating regions <NUM> of charge, the n-type doping concentration of the CB layers 24A and 24B should be relatively high (e.g., greater than or equal to l×l0<NUM> cm-<NUM> ). However, in order to maximize the blocking voltage for the embodiment of the SiC-SJ device <NUM>, the doping concentration should be such that the integrated doping of the epitaxial layer of a CB layer (e.g., CB layer 24A or 24B) is below a particular value. For example, in certain embodiments of the SiC-SJ device <NUM>, the product of the thickness 32A and the uniform n-type dopant concentration of the epi layer 24A may be less than approximately
l. l×l0<NUM> cm-<NUM> in order to provide efficient charge balance. Moving toward the lower manufacturable limit for minimum spacing <NUM> between the floating regions <NUM> (e.g., approximately <NUM> for processes involving multiple SiC epitaxial regrowth steps), drift layer specific on-resistance is minimized at a n-type dopant concentration in the drift layers 24A and 24B of approximately <NUM>×<NUM><NUM> cm-<NUM>.

With the foregoing in mind, in certain embodiments, the thicknesses 32A and 32B of each of the drift layers 24A and 24B may be between approximately <NUM> to approximately <NUM> (e.g., between approximately <NUM> to approximately <NUM>) in order to provide the desired charge balance. As such, certain embodiments the SiC-SJ device <NUM> may involve up to four epitaxial growth/ion implantation steps to provide a 3kV blocking voltage with doping concentrations in the drift layers 24A and 24B of <NUM>×<NUM><NUM> cm-<NUM>. Since additional SiC epitaxial growth/implantation cycles increase cost, complexity, and potentially lowers the yield for embodiments of the SiC-SJ device <NUM>, the spacing <NUM> between the floating regions <NUM> may be greater than approximately <NUM>, as set forth above, in certain embodiments, to reduce the number of epitaxial growth steps and enable charge balance device performance benefits. Additionally, the spacing <NUM> between the floating regions <NUM> may also be maintained below a maximum value to enable practical implementation and fabrication of the SiC-SJ device structure. For example, if the spacing <NUM> between the floating regions <NUM> is exceedingly large (e.g., if the spacing <NUM> is greater than the thickness 32A or 32B of the drift layers 24A or 24B), then the n-type doping concentration in the SiC epitaxial layers 24A and 24B may be lower to maintain BV, which may undesirably increase the specific on-resistance of the device.

<FIG> includes contour plots <NUM> representative of the specific on-resistance of the drift layer (at room temperature) and the breakdown voltage as a function of doping concentration in the floating regions <NUM> and doping concentration in the CB layers 24A and 24B for embodiments of the SiC-SJ device <NUM>, in accordance with the present invention. It may be noted that, for the embodiments of the invention represented in <FIG>, the epi doping concentration of in the layer <NUM> is substantially the same as the epi doping concentration of the CB layers 24A and 24B. For the SiC-SJ device embodiment of the invention represented in <FIG>, the thicknesses 32A and 32B of each of the n-type drift layers 24A and 24B is <NUM>, the thickness <NUM> of the floating regions <NUM> is <NUM>, and the width <NUM> of the floating regions <NUM> is <NUM>, and the spacing <NUM> between the floating regions <NUM> is <NUM>. The contour plots <NUM> and <NUM> include dopant concentration of the floating regions <NUM> on the vertical axes and n-type dopant concentration of the epi layers 24A and 24B on the horizontal axes. The graph <NUM> on the left in <FIG> illustrates drift specific on-resistance contours, and, as indicated by the key <NUM>, each contour of the graph <NUM> represents a different specific on-resistance value ranging from
<NUM> mOhm cm-<NUM> to <NUM> mOhm cm-<NUM>. The graph <NUM> on the right in <FIG> illustrates breakdown voltage contours, and, as indicated by the key <NUM>, each contour of the graph <NUM> represents a different breakdown voltage ranging from <NUM> kV to <NUM> kV.

For embodiments of the invention of the SiC-SJ device <NUM> represented in the graph <NUM> of <FIG>, the solid horizontal line <NUM> represents the desired dopant concentration of approximately <NUM>×l0<NUM> cm-<NUM> for the floating regions <NUM>, which is within the ranges discussed above. The dashed horizontal lines <NUM> and <NUM> respectively represent a doping concentration that is <NUM>% lower and <NUM>% higher than the target dopant concentration for the floating regions <NUM>. As such, these dashed horizontal lines <NUM> and <NUM> define a ±<NUM>% range to represent potential variation in the dopant concentration of the floating regions <NUM> that may result from variation in the implantation process and/or material properties. The points <NUM> and <NUM> are positioned at the intersection of the desired dopant concentration of the floating regions <NUM> (e.g., approximately <NUM>×<NUM><NUM> cm-<NUM> ) and the desired dopant concentration of the two n-type SiC epitaxial layers 24A and 24B (e.g., approximately <NUM>×<NUM><NUM> cm-<NUM> ).

Further, the dashed vertical lines <NUM> and <NUM> of <FIG> respectively represent a doping concentration that is <NUM>% lower and <NUM>% higher than the target dopant concentration for the CB layers 24A and 24B. As such, these dashed vertical lines <NUM> and <NUM> define a ±<NUM>% range to represent variation in the dopant concentration of the CB layers 24A and 24B that may result from epitaxial growth process and/or material properties variation. Accordingly, the regions <NUM> and <NUM> formed by the intersections of the horizontal and vertical dashed lines <NUM>, <NUM>, <NUM>, and <NUM> represent realistic practical ranges for the dopant concentration of the floating regions <NUM> and the dopant concentration in CB layers 24A and 24B that still provide desirable device performance. Accordingly, in order to maximize performance benefits, embodiments of the invention of the SiC-SJ device <NUM> provide desirable device performance (e.g., specific on-resistance of <NUM> mOhm-cm"<NUM> or below, a blocking voltage of <NUM> kV or above) within the practically expected ranges of variation for the dopant concentrations of the floating regions <NUM> and the CB layers 24A and 24B (e.g., within the entire regions <NUM> and <NUM>).

As illustrated in the graph <NUM> of <FIG>, for embodiments of the invention of the SiC-SJ device <NUM>, the specific on-resistance of the drift layer at room temperature is between <NUM> mOhm-cm-<NUM> and <NUM> mOhm-cm-<NUM> over the practically controllable range of dopant concentration for the floating regions <NUM> and the epi layers <NUM> (e.g., over the entire area <NUM>). Further, as illustrated in the graph <NUM> of <FIG>, the blocking voltage of the drift layer for the SiC-SJ device <NUM> is greater than <NUM> kV over the practically controllable range of dopant concentration for the floating regions
<NUM> and the drift layers <NUM> (e.g., over the entire area <NUM>). Since the specific on-resistance of an ideal <NUM> kV <NUM>-D device drift layer design is approximately <NUM> mOhm cm-<NUM> , it should be appreciated that the represented embodiments of the three-layer SiC-SJ device <NUM> enables a <NUM>% to <NUM>% reduction in specific on-resistance of a drift region compared to that of an ideal 3kV <NUM>-D device drift layer design.

Another embodiment of the invention of a multi-layered SiC-SJ device <NUM> is illustrated in <FIG>. The illustrated embodiment of the invention of <FIG> is a <NUM> kV SiC-SJ Schottky device <NUM> having a similar structure to the SiC-SJ <NUM> illustrated in <FIG>. However, the SiC-SJ device <NUM> illustrated in <FIG> has three CB layers <NUM>, including a lower layer 24A, a middle layer 24B, and an upper layer 24C. The illustrated SiC-SJ <NUM> has a doping concentration in the floating regions <NUM>, as well as a spacing <NUM> between the floating regions <NUM>, falling within the ranges set forth above.

<FIG> is a contour plot graph <NUM> representative of the specific on-resistance of the drift layer at room temperature (in graph <NUM>) and breakdown voltage (in graph <NUM>) for embodiments of the invention of the SiC-SJ device <NUM> illustrated in <FIG>. More specifically, the contour graph <NUM> of <FIG> includes dopant concentration of the floating regions <NUM> on the vertical axes and n- type dopant concentration of the SiC CB layers <NUM> on the horizontal axes of the graphs <NUM> and <NUM>. The graph <NUM> on the left in <FIG> illustrates specific on-resistance contours, and, as indicated by the key <NUM>, each contour of the graph <NUM> represents a different specific on- resistance value ranging from <NUM> mOhm-cm-<NUM> to <NUM> mOhm-cm-<NUM>. The graph <NUM> on the right in <FIG> illustrates breakdown voltage contours, and, as indicated by the key <NUM>, each contour of the graph <NUM> represents a different breakdown voltage ranging from <NUM> kV to <NUM> kV. Additionally, for the embodiments of the invention of the SiC-SJ device <NUM> represented in <FIG>, the width <NUM> of the floating regions <NUM> is <NUM>, the thicknesses 32A, 32B, and 32C of each of the three n-type SiC epitaxial layers <NUM> A, 24B, and 24C is <NUM>, the spacing <NUM> between the floating regions <NUM> is <NUM>, and the thickness <NUM> of the floating regions <NUM> is <NUM>.

Like the graph <NUM> of <FIG>, the solid horizontal line <NUM> of <FIG> represents a desired dopant concentration of approximately <NUM>×l0<NUM> cm-<NUM> for the floating regions <NUM>, which is within the ranges set forth above. The dashed horizontal lines <NUM> and <NUM> in <FIG> define a ±<NUM>% range to represent anticipated variation in the dopant concentration of the floating regions <NUM> that may result from process and/or material variation. The points <NUM> and <NUM> are positioned at the intersection of the desired dopant concentration of the floating regions <NUM> (e.g., approximately <NUM>×l0<NUM> cm-<NUM> ) and the desired n-type dopant concentration for the n-type CB layers <NUM> (e.g., approximately <NUM>×l0<NUM> cm-<NUM>). Further, the dashed vertical lines <NUM> and <NUM> define
a ±<NUM>% range to represent anticipated variation in the dopant concentration of the CB layers <NUM> that may result from process and/or material variation. As such, the regions <NUM> and <NUM> formed by the intersections of the horizontal and vertical dashed lines <NUM>, <NUM>, <NUM>, and <NUM> represent practically controllable ranges for the dopant concentration of the floating regions <NUM> and the drift layers <NUM>.

As illustrated in the graph <NUM> of <FIG>, the specific on-resistance for embodiments of the invention of the four-layer SiC-SJ device <NUM> is between <NUM> mOhm-cm-<NUM> and <NUM> mOhm-cm-<NUM> over the practically controllable range of dopant concentration for the floating regions <NUM> and the CB layers <NUM> (e.g., over the entire area <NUM>). As illustrated in the graph <NUM> of <FIG>, the blocking voltage for embodiments of the invention of the four-layer SiC-SJ device <NUM> is greater than <NUM> kV over most of the practically controllable range of dopant concentration for the floating regions <NUM> and the CB layers <NUM> (e.g., over most of the area <NUM>). Since the specific on-resistance of an ideal <NUM> kV <NUM>- D device design is approximately <NUM> mOhm-cm-<NUM> , it should be appreciated that embodiments of the invention of the four-layer SiC-SJ device <NUM> enable a <NUM>% to <NUM>% reduction in drift region specific on- resistance compared to that of an ideal <NUM>-D device design.

Claim 1:
A silicon carbide, SiC, super-junction, SJ, device (<NUM>), comprising:
an active area (<NUM>) including two or three charge balance, CB, layers (<NUM>), wherein each CB layer (<NUM>) comprises:
a semiconductor layer having a first conductivity-type; and
a plurality of floating regions (<NUM>) having a second conductivity-type disposed in a surface of the semiconductor layer, wherein
the plurality of floating regions and the semiconductor layer are both configured to deplete to provide equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device (<NUM>);
the plurality of floating regions has a dopant concentration of <NUM>×<NUM><NUM>cm-<NUM> ± <NUM>%;
the semiconductor layer (<NUM>) has a dopant concentration of either <NUM>×<NUM><NUM>cm-<NUM> ± <NUM>% or <NUM>×<NUM><NUM>cm-<NUM> ± <NUM>%;
wherein if the semiconductor layer (<NUM>) has a dopant concentration of <NUM>×<NUM><NUM>cm-<NUM> ± <NUM>%, then the active area includes three CB layers (<NUM>);
and wherein if the semiconductor layer (<NUM>) has a dopant concentration of <NUM>×<NUM><NUM>cm-<NUM> ± <NUM>%, then the active area includes two CB layers (<NUM>);
a thickness of each of the plurality of floating regions (<NUM>) is <NUM>;
a width of each of the plurality of floating regions (<NUM>) is <NUM>;
a spacing between the plurality of floating regions (<NUM>) is <NUM>; and
the two or three CB layers (<NUM>) each has a thickness of <NUM>.