Patent Description:
A semiconductor device having a structure in which semiconductor components each including a semiconductor substrate and a wiring structure are stacked and the wiring structures are bonded together is known.

<CIT> discusses a semiconductor device having a structure in which a conductor portion and an insulation film are located on an uppermost surface of each of wiring structures of two semiconductor components, and the conductor portions are bonded together and the insulation films are bonded together, thereby bonding the two semiconductor components.

In the case of bonding two semiconductor components by bonding the conductor portions and bonding the insulation films on a bonded surface, it is important for the bonded surface to have a high degree of flatness in terms of reliability of bonding. For example, if at least one of dies obtained by cutting a wafer is used as a semiconductor component, the flatness of the bonded surface may be impaired during cutting.

Document <CIT> discloses a semiconductor device and a method of manufacturing thereof including providing first and second wafers, forming a first device layer in a top portion of the first wafer, forming a second device layer in a top portion of the second wafer, forming a first groove in the first device layer, forming a second groove in the second device layer, bonding the first and second wafers together after at least one of the first and second grooves is formed, and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.

In view of the above-described issue, the present invention is directed to improving the reliability of bonding in a semiconductor device obtained by bonding two semiconductor components on a bonded surface.

According to a first aspect of the present invention, there is provided a semiconductor device as specified in claims <NUM> to <NUM>. According to a second aspect of the present invention, there is provided equipment as specified in claim <NUM>. According to a third aspect of the present invention, there is provided a manufacturing method as specified in claims <NUM> to <NUM>.

Modes for carrying out the present invention will be described below with reference to the drawings. In the following description and the drawings, components common among a plurality of drawings are denoted by the same reference numerals. The common components will be described by cross-referring to the plurality of drawings, and descriptions of the components denoted by the same reference numerals will be omitted as appropriate. Components that have the same names and are denoted by different reference numerals may be distinguished by expressions "nth", for example, a first component, a second component, and a third component, as appropriate.

<FIG> are diagrams for illustrating a semiconductor device <NUM>. <FIG> is a sectional view illustrating the semiconductor device <NUM> according to a first exemplary embodiment. <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on a virtual plane.

The semiconductor device <NUM> includes a first semiconductor component <NUM> (first circuit component) and a second semiconductor component <NUM> (second circuit component). The semiconductor device <NUM> has a structure in which the first semiconductor component <NUM> and the second semiconductor component <NUM> are stacked. In the following description, a direction in which the first semiconductor component <NUM> and the second semiconductor component <NUM> are stacked is defined as a stacking direction Z, and directions perpendicular to the stacking direction Z are defined as directions X and Y, respectively. The directions X and Y are directions perpendicular to each other. In the stacking direction Z, a direction from the first semiconductor component <NUM> to the second semiconductor component <NUM> in the semiconductor device <NUM> is defined as a positive direction.

The first semiconductor component <NUM> includes a first semiconductor substrate <NUM> and a first wiring structure <NUM>.

The first wiring structure <NUM> has a structure in which at least one wiring layer and at least one insulation layer are stacked. The at least one wiring layer and the at least one insulation layer are alternately stacked and formed on the first semiconductor substrate <NUM>. The first semiconductor component <NUM> has a first surface S1 located on a side of the first wiring structure <NUM> that is opposite to the first semiconductor substrate <NUM>.

The first surface S1 is a surface of an insulation layer <NUM> that is opposite to the first semiconductor substrate <NUM>. The insulation layer <NUM> is located farthest from the first semiconductor substrate <NUM> in the at least one insulation layer forming the first wiring structure <NUM>. The first surface S1 is a flat surface. The insulation layer <NUM> includes a plurality of conductor portions <NUM>.

The insulation layer <NUM> has a damascene structure in which the conductor portions <NUM> are respectively embedded in a plurality of concave portions formed in an insulator portion <NUM> that forms the insulation layer <NUM>. The conductor portions <NUM> are each exposed to the first surface S1. In other words, the first surface S1 is formed of the plurality of conductor portions <NUM> and the insulator portion <NUM> included in the insulation layer <NUM>.

Each of the conductor portions <NUM> may preferably contain metal. The conductor portions <NUM> may preferably contain copper (Cu), but instead may contain, for example, gold (Au) or silver (Ag). In particular, the conductor portions <NUM> may be preferably composed mainly of Cu. The insulator portion <NUM> may be preferably composed mainly of a silicon compound. A barrier metal layer may be located on portions of the conductor portions <NUM> that are adjacent to the insulator portion <NUM>. The barrier metal layer may contain tantalum or titanium. The first semiconductor substrate <NUM> includes a semiconductor element such as a transistor (not illustrated). This semiconductor element is electrically connected to the conductor portions <NUM> through the wiring layer included in the first wiring structure <NUM>. The material of the first semiconductor substrate <NUM> is not particularly limited. Silicon or compound semiconductor, such as III - V semiconductors or II - VI semiconductors, can be used. The first semiconductor substrate <NUM> may contain at least one of indium gallium arsenide (InGaAs), indium arsenic antimony (InAsSb), Indium arsenide (InAs), indium antimonide (InSb), and mercury cadmium telluride (HgCdTe).

The second semiconductor component <NUM> includes a second semiconductor substrate <NUM> and a second wiring structure <NUM>.

The second wiring structure <NUM> has a structure in which at least one wiring layer and at least one insulation layer are stacked. The second wiring structure <NUM> is formed by the at least one wiring layer and the at least one insulation layer alternately being stacked on the second semiconductor substrate <NUM>. The second semiconductor component <NUM> has a second surface S2 located on a side of the second wiring structure <NUM> that is opposite to the second semiconductor substrate <NUM>.

The second surface S2 is a surface of an insulation layer <NUM> that is opposite to the second semiconductor substrate <NUM>. The insulation layer <NUM> is located farthest from the second semiconductor substrate <NUM> in the at least one insulation layer forming the second wiring structure <NUM>. The second surface S2 is a flat surface. The insulation layer <NUM> includes a plurality of conductor portions <NUM>.

The insulation layer <NUM> has a damascene structure in which the conductor portions <NUM> are respectively embedded in a plurality of concave portions formed in an insulator portion <NUM> that forms the insulation layer <NUM>. The plurality of conductor portions <NUM> are each exposed to the second surface S2. In other words, the second surface S2 is formed of the plurality of conductor portions <NUM> and the insulator portion <NUM> included in the insulation layer <NUM>.

The conductor portions <NUM> may preferably contain metal. The conductor portions <NUM> may preferably contain Cu, but instead may contain Au or Ag. In particular, the conductor portions <NUM> may be preferably composed mainly of Cu. The insulator portion <NUM> may be preferably composed mainly of a silicon compound. A barrier metal layer may be located on portions of the conductor portions <NUM> that are adjacent to the insulator portion <NUM>. The barrier metal layer may contain tantalum or titanium. The second semiconductor substrate <NUM> includes a semiconductor element such as a transistor (not illustrated). This semiconductor element is electrically connected to the conductor portions <NUM> through the wiring layer included in the second wiring structure <NUM>. The material of the second semiconductor substrate <NUM> is not particularly limited. Silicon or compound semiconductor, such as III - V semiconductors or II - VI semiconductors, can be used. The second semiconductor substrate <NUM> may contain any one of InGaAs, InAsSb, InAs, InSb, and HgCdTe.

As illustrated in <FIG>, in the semiconductor device <NUM>, the first semiconductor component <NUM> and the second semiconductor component <NUM> are bonded together on a bonded surface S3 in a state where the wiring structures (first wiring structure <NUM> and second wiring structure <NUM>) included in the first semiconductor component <NUM> and the second semiconductor component <NUM>, respectively, face each other and overlap each other. In other words, the first surface S1 of the first semiconductor component <NUM> and the second surface S2 of the second semiconductor component <NUM> are bonded together. On the bonded surface S3, a conductor portion <NUM> included in the first wiring structure <NUM> and a conductor portion <NUM> included in the second wiring structure <NUM> are bonded together. On the bonded surface S3, the insulator portion <NUM> included in the first wiring structure <NUM> and the insulator portion <NUM> included in the second wiring structure <NUM> are bonded together.

Next, the size and arrangement relationship of the first semiconductor component <NUM> and the second semiconductor component <NUM> that constitute the semiconductor device <NUM> according to the present exemplary embodiment will be described with reference to <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane. Assuming that a plane parallel to the first surface S1 is defined as a virtual plane VP, consider a region obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane VP in a normal direction of the virtual plane VP. Assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first surface S1 on the virtual plane VP is a first region A1 and a region having a circumference corresponding to a shape obtained by vertically projecting the second surface S2 on the virtual plane VP is a second region A2. In other words, the first region A1 is a region surrounded by the shape obtained by vertically projecting the first surface S1 on the virtual plane VP, and the second region A2 is a region surrounded by the shape obtained by vertically projecting the second surface S2 on the virtual plane VP. Also, assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first wiring structure <NUM> on the virtual plane VP is a third region A3 and a region having a circumference corresponding to a shape obtained by vertically projecting the second wiring structure <NUM> on the virtual plane VP is a fourth region A4. In other words, the third region A3 is a region surrounded by the shape obtained by vertically projecting the first wiring structure <NUM> on the virtual plane VP, and the fourth region A4 is a region surrounded by the shape obtained by vertically projecting the second wiring structure <NUM> on the virtual plane VP.

As illustrated in <FIG>, in the semiconductor device <NUM>, the first to fourth regions A1 to A4 satisfy the following relations (<NUM>) to (<NUM>).

As illustrated in <FIG>, in the semiconductor device <NUM>, the area of the first region A1 is smaller than the area of the third region A3 and is smaller than the area of the fourth region A4. In the present exemplary embodiment, the semiconductor device <NUM> satisfies the relation that (area of first region A1) < (area of second region A2) = (area of fourth region A4) < (area of third region A3).

As described in detail below, in the present exemplary embodiment, the contour of the first surface S1 is formed by an etching process, and the contour of the second surface S2 is formed by a dicing process such as blade dicing. In general, during the dicing process such as blade dicing, damage can be added to a target to be processed, which can cause a phenomenon called chipping in which a chip end face is chipped off after cutting. If chipping occurs during cutting of the second semiconductor component <NUM>, the flatness of the second surface S2 decreases in the vicinity of the contour of the second surface S2, which may result in generation of a step. Thus, in the present exemplary embodiment, a step is more likely to occur in the vicinity (peripheral portion) of the contour of the second surface S2 of the second semiconductor component <NUM> than in the vicinity of the contour of the first surface S1 of the first semiconductor component <NUM>.

When the above-described relations (<NUM>) and (<NUM>) are satisfied, the circumference of the bonded surface S3 where the first semiconductor component <NUM> and the second semiconductor component <NUM> are bonded together is determined by the circumference of the first surface S1. In other words, the bonded surface S3 matches the first surface S1 and a portion of the second surface S2 that does not overlap the first surface S1 is not included in the bonded surface S3. Accordingly, when the above-described relations (<NUM>) and (<NUM>) are satisfied, at least a part of the area (peripheral portion) in the vicinity of the contour of the second surface S2 is not included in the bonded surface S3. This results in preventing a portion of the second surface S2 where the flatness is likely to decrease from being included in the bonded surface S3. This leads to an increase in bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM>, and also leads to an increase in the reliability of bonding.

As described below, in the present exemplary embodiment, the second semiconductor component <NUM> in the shape of a chip (die) is bonded to the wafer, and then the wafer is diced to cut the first semiconductor component <NUM> from the wafer, thereby manufacturing the semiconductor device <NUM>. In this case, when the above-described relations (<NUM>) and (<NUM>) are satisfied, damage to the second semiconductor component <NUM> during the dicing process after bonding can be prevented. This leads to an increase in the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM>, and also leads to an increase in the reliability of bonding.

Assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first semiconductor substrate <NUM> on the virtual plane VP is a fifth region A5 and a region having a circumference corresponding to a shape obtained by vertically projecting the second semiconductor substrate <NUM> on the virtual plane VP is a sixth region A6. In other words, the fifth region A5 is a region surrounded by the shape obtained by vertically projecting the first semiconductor substrate <NUM> on the virtual plane VP, and the sixth region A6 is a region surrounded by the shape obtained by vertically projecting the second semiconductor substrate <NUM> on the virtual plane VP. As illustrated in <FIG>, in the semiconductor device <NUM>, the fifth region A5 and the sixth region A6 may preferably satisfy the following relations (<NUM>) and (<NUM>).

When the relation (<NUM>) is satisfied in addition to the relations (<NUM>) and (<NUM>), the circumference of the first region A1 does not overlap the circumference of the second region A2 as illustrated in <FIG>, and the circumference of the first region A1 is located at a distance from the circumference of the second region A2 on the inside of the circumference of the second region A2. Thus, the entire circumferential portion of the second surface S2 where the flatness is likely to decrease is not included in the bonded surface S3. Consequently, the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM> can be further increased and the reliability of bonding can be further increased.

When the above-described relation (<NUM>) is satisfied, assuming that a shortest distance between the circumference of the first region A1 and the circumference of the second region A2 is represented by "c", the distance "c" may preferably be more than or equal to <NUM> micrometers (µm). When the distance "c" is more than or equal to <NUM>, the portion of the second surface S2 where the flatness is likely to decrease can reliably be prevented from being included in the bonded surface S3, thereby further increasing the reliability of bonding. The upper limit of the distance "c" is not particularly limited, but may be less than or equal to <NUM>, may be less than or equal to <NUM>, or may be less than or equal to <NUM>.

As illustrated in <FIG>, in the present exemplary embodiment, the first semiconductor component <NUM> includes a concave portion <NUM> that is recessed toward the first semiconductor substrate <NUM> from the first surface S1. The concave portion <NUM> includes a bottom <NUM>. The bottom <NUM> of the concave portion <NUM> may be a deepest portion from the first surface S1. In the present exemplary embodiment, the bottom <NUM> of the concave portion <NUM> is located inside the first wiring structure <NUM>. However, the location of the bottom <NUM> of the concave portion <NUM> is not particularly limited. The bottom <NUM> of the concave portion <NUM> may be located inside the first semiconductor substrate <NUM>.

In the length that is vertical to the first surface S1 on a section of the first semiconductor component <NUM> taken along a plane vertical to the first surface S1, the first semiconductor component <NUM> includes a first portion <NUM> with a first length and a second portion <NUM> with a second length longer than the first length. The first length and the second length correspond to the length in a Z-direction of the first portion <NUM> and the length in the Z-direction of the second portion <NUM>, respectively, in <FIG>. In other words, the position of the bottom <NUM> described above corresponds to the position of the upper surface of the second portion <NUM>.

The concave portion <NUM> may preferably surround the first surface S1 in a planar view of the first surface S1. In other words, the second portion <NUM> may preferably surround the first portion <NUM> in a planar view of the first surface S1. When the concave portion <NUM> is provided around the first surface S1 in a planar view, the above-described relations (<NUM>), (<NUM>), and (<NUM>) can be satisfied. Consequently, the reliability of bonding can be further increased as described above.

Assume herein that the depth of the concave portion <NUM>, or the difference between the first length and the second length is represented by "b". The depth "b" of the concave portion <NUM> corresponds to the depth of the bottom <NUM> of the concave portion <NUM> based on a plane including the first surface S1. In other words, the depth "b" corresponds to the distance from the plane including the first surface S1 to the bottom <NUM> of the concave portion <NUM>. Also, assume that the depth of the bottom of each conductor portion <NUM> included in the first semiconductor component <NUM> is represented by "e". The depth "e" of the bottom of each conductor portion <NUM> corresponds to the depth of the bottom of each conductor portion <NUM> based on the plane including the first surface S1. In other words, the depth "e" corresponds to the distance from the plane including the first surface S1 to the bottom of each conductor portion <NUM>.

In this case, the depth "b" of the concave portion <NUM> may preferably be greater than the depth "e" of the bottom of each conductor portion <NUM> (b > e). In other words, the bottom <NUM> of the concave portion <NUM> may preferably be located at a position further from the plane including the first surface S1 than the bottom of each conductor portion <NUM>. The depth "b" of the concave portion <NUM> may preferably be greater than the thickness of the wiring layer forming the first surface S1 in the at least one wiring layer forming the first wiring structure <NUM>. As described below, in the case of bonding the first semiconductor component <NUM> and the second semiconductor component <NUM>, a heat treatment is performed after the first surface S1 of the first semiconductor component <NUM> and the second surface S2 of the second semiconductor component <NUM> are bonded together, thereby increasing the bonding strength.

In the heat treatment, heat deformation can occur due to, for example, a difference in the coefficient of thermal expansion of materials forming the conductor portions <NUM> and <NUM> and the insulator portions <NUM> and <NUM>. According to the present exemplary embodiment, the depth "b" of the concave portion <NUM> is set to be greater than the depth "e" of the bottom of each conductor portion <NUM> and the thickness of the wiring layer forming the first surface S1, thereby making it possible to perform bonding while reducing effects due to heat deformation. This leads to an increase in the reliability of bonding.

The first semiconductor component <NUM> may include a sealing ring <NUM>, and the second semiconductor component <NUM> may include a sealing ring <NUM>. The sealing ring <NUM> is provided in the first wiring structure <NUM> and the sealing ring <NUM> is provided in the second wiring structure <NUM>. The sealing ring <NUM> and the sealing ring <NUM> are each composed of conductive wires and via-holes formed over a plurality of wring layers and insulation layers. The provision of the sealing ring <NUM> and the sealing ring <NUM> prevents penetration of water from a chip end face of each of the first semiconductor component <NUM> and the second semiconductor component <NUM>.

As illustrated in <FIG>, the distance from the sealing ring <NUM> to a side wall of the concave portion <NUM> is represented by "d". In this case, the distance "d" may preferably be more than or equal to <NUM>. Assuming that a region obtained by projecting the sealing ring <NUM> on the virtual plane VP in the normal direction of the virtual plane VP is a seventh region A7, the shortest distance "d" between the circumference of the seventh region A7 and the circumference of the first surface S1 may be preferably more than or equal to <NUM>. When the distance "d" is more than or equal to <NUM>, damage to the first semiconductor component <NUM> can be reduced during formation of the concave portion <NUM>. When the distance "d" is more than or equal to <NUM>, penetration of water can be prevented even in a case where the concave portion <NUM> is formed.

It may be preferable that the contour of the first region A1 have no internal angle of less than or equal to <NUM>°. In the present exemplary embodiment, the contour of the first region A1 has no angle and the long sides and short sides of the contour are smoothly connected with a curve as illustrated in <FIG>. As described below, the process of bonding the first semiconductor component <NUM> and the second semiconductor component <NUM> is completed by bonding the entire first surface S1 to the second surface S2. In this case, if the contour of the first region A1 has an internal angle of less than or equal to <NUM>°, progress in bonding between the first surface S1 and the second surface S2 may be inhibited at the angle and the bonding may progress unevenly. This may cause a bonding failure and deterioration in the reliability of bonding. In contrast, according to the present exemplary embodiment, the contour of the first region A1 is set to have no internal angle of less than or equal to <NUM>°, thereby preventing the bonding from progressing unevenly, which leads to an increase in the reliability of bonding.

While the present exemplary embodiment illustrates an example where the long sides and short sides of the contour of the first region A1 are smoothly connected with a curve having an arc shape, the present exemplary embodiment is not limited to this example. The long sides and short sides may be smoothly connected with curves having a shape other than an arc shape. The curvature of the curve is not particularly limited, as long as the first region A1 includes a curved portion. The contour of the first region A1 may have an internal angle of more than <NUM>°. <FIG> illustrates a projection of a modified example of the semiconductor device <NUM> according to the present exemplary embodiment obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane VP in the same manner as in <FIG>. As illustrated in <FIG>, the contour of the first region A1 may have a polygonal shape, and each internal angle of the contour of the first region A1 may be greater than <NUM>°. Also, in this shape, the same advantageous effects can be obtained.

Next, a manufacturing method of the semiconductor device <NUM> will be described. A manufacturing method of a wafer for the first semiconductor component <NUM> and a manufacturing method of the second semiconductor component <NUM> will be described first, and then a manufacturing method of the semiconductor device <NUM> using the wafer for the first semiconductor component <NUM> and the second semiconductor component <NUM> will be described. The wafer for the first semiconductor component <NUM> and the second semiconductor component <NUM> may be manufactured in an arbitrary order. For example, the wafer for the first semiconductor component <NUM> and the second semiconductor component <NUM> may be manufactured in this order, and the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> may be manufactured in this order. Alternatively, these components may be simultaneously manufactured in parallel.

A manufacturing method of the wafer for the first semiconductor component <NUM> will now be described with reference to a flowchart illustrated in <FIG> and <FIG>. <FIG> is a flowchart illustrating a manufacturing method of the wafer for the first semiconductor component <NUM>. <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the wafer for the first semiconductor component <NUM>. <FIG> each illustrate a part of the wafer.

A wafer P1 that is a part of a semiconductor wafer for the first semiconductor component <NUM> is prepared. The wafer P1 includes the first semiconductor substrate <NUM> and a semiconductor element (not illustrated) such as a transistor formed on the first semiconductor substrate <NUM>. Although not illustrated, a gate electrode that forms the transistor, and insulation layers and wiring layers that cover the gate electrode are stacked and formed on the first semiconductor substrate <NUM>. A wire included in each wiring layer is electrically connected to the gate electrode, source, and drain of the transistor via a contact plug. Each insulation layer includes a via plug that electrically connects wires included in upper and lower wiring layers. The guard ring <NUM> is also formed when the insulation layers and wiring layers are formed. The detailed description of the manufacturing method of the wafer P1 is omitted.

As illustrated in <FIG>, an insulation film <NUM> is formed on the wafer P1. Examples of the insulation film <NUM> include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, and a fluoride-containing silicon oxide film. The insulation film <NUM> may be formed of a single layer made of one type of material, or may be formed of a plurality of layers made of different types of materials. In this case, for example, a silicon oxide film is formed and then planarization is performed by chemical mechanical polishing (CMP), thereby making it possible to reduce defects caused due to a step in the subsequent processes.

Next, as illustrated in <FIG>, a plurality of concave portions <NUM> in which a conductor material is to be buried is formed in the insulation layer <NUM>. At least some of the concave portions <NUM> are formed to reach the uppermost wiring layer of the wafer P1. The concave portions <NUM> are formed with an appropriate density on the entire chip area. The concave portions <NUM> may be formed such that a bottom portion of at least some of the concave portions <NUM> reaches the uppermost wiring layer of the wafer P1, or holes (via-holes) may be formed below the concave portions <NUM>. The order of forming the concave portions <NUM> and the holes is not particularly limited.

Next, a conductor material <NUM> is formed over the entire surface as illustrated in <FIG>.

In this case, the concave portions <NUM> are buried with the conductor material <NUM>. If holes are formed below the concave portions <NUM>, the holes are also buried with the conductor material <NUM>. Copper can be used as the conductor material <NUM>.

Next, as illustrated in <FIG>, an extra amount of the conductor material <NUM> is removed by using a chemical mechanical polishing (CMP) method to form the conductor portions <NUM>. If holes are formed below the concave portions <NUM>, via-holes located below the conductor portions <NUM> are formed in the portions corresponding to the holes. The formation of the conductor portions <NUM> with an appropriate density over the entire chip area can prevent dishing or erosion from occurring due to the CMP process during the CMP process. This leads to an improvement in the flatness of the surface of the semiconductor wafer for the first semiconductor component <NUM> before bonding, and also leads to a reduction in defects caused due to a step during bonding. Through this process, the first wiring structure <NUM> is completed.

Next, the concave portion <NUM> is formed by photolithography and etching as illustrated in <FIG>. On the upper surface of the wafer for the first semiconductor component <NUM>, the region surrounded by the concave portion <NUM> corresponds to the first surface S1. Accordingly, the contour of the first surface S1 is formed by the etching process.

<FIG> is a top view of the wafer for the first semiconductor component <NUM> obtained after step S106. As described above, the first surface S1 is surrounded by the concave portion <NUM>. Assuming that the width of the narrowest portion of the concave portion <NUM> is represented by "a", it may be preferable to satisfy a > c. The width "a" may be preferably more than or equal to <NUM>, and more preferably, more than or equal to <NUM>. When a > c is satisfied and the width "a" is more than or equal to <NUM>, the portion in the vicinity of the contour of the second surface S can be prevented from contacting the wafer for the first semiconductor component <NUM> during bonding even in a case where the above-described distance "c" is more than or equal to <NUM>. As described in detail below, a step can be generated in the vicinity of the contour of the second surface S2. This portion is prevented from contacting the wafer for the first semiconductor component <NUM>, thereby achieving excellent contact properties of the portions of the first surface S1 and the second surface S2 that form the bonded surface S3 during bonding.

As illustrated in <FIG>, in the present exemplary embodiment, the concave portion <NUM> is formed such that the first surface S1 has no internal angle of less than or equal to <NUM>°. As a result, the bonding can progress evenly and smoothly in the process of bonding the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> by bringing the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> into contact with each other in step S302 to be described below. This leads to an increase in the reliability of bonding.

While <FIG> illustrates an example where only one portion corresponding to the first semiconductor component <NUM> is formed on the wafer P1, the present exemplary embodiment is not limited to this example. A plurality of portions corresponding to the first semiconductor component <NUM> may be formed on the wafer P1.

Through the above-described processes, the first semiconductor component <NUM> before bonding is completed.

A manufacturing method of the second semiconductor component <NUM> will now be described with reference to a flowchart illustrated in <FIG> and <FIG>. <FIG> is a flowchart illustrating a manufacturing method of the second semiconductor component <NUM>. <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the second semiconductor component <NUM>. <FIG> each illustrate a part of the wafer.

A wafer P2 that is a part of a semiconductor wafer for the second semiconductor component <NUM> is prepared. The wafer P2 includes the second semiconductor substrate <NUM> and a semiconductor element (not illustrated) such as a transistor formed on the second semiconductor substrate <NUM>. Although not illustrated, a gate electrode that forms the transistor, and insulation layers and wiring layers that cover the gate electrode are stacked and formed on the second semiconductor substrate <NUM>. A wire included in each wiring layer is electrically connected to the gate electrode, source, and drain of the transistor via a contact plug. Each insulation layer includes a via plug that electrically connects wires included in upper and lower wiring layers. The guard ring <NUM> is also formed when the insulation layers and wiring layers are formed. The detailed description of the manufacturing method of the wafer P2 is omitted.

As illustrated in <FIG>, an insulation film <NUM> is formed on the wafer P2. Examples of the insulation film <NUM> include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, and a fluoride-containing silicon oxide film. The insulation film <NUM> may be formed of a single layer made of one type of material, or may be formed of a plurality of layers made of different types of materials. In this case, for example, a silicon oxide film is formed and then planarization is performed by CMP, thereby making it possible to reduce defects caused due to a step in the subsequent processes.

Next, a plurality of concave portions <NUM> in which a conductor material is to be buried is formed in the insulation layer <NUM> as illustrated in <FIG>. The concave portions <NUM> may be formed such that a bottom portion of at least some of the concave portions <NUM> reaches the uppermost wiring layer of the wafer P2. The concave portions <NUM> are formed with an appropriate density over the entire chip area. The plurality of concave portions <NUM> may be formed such that the bottom portion of at least some of the concave portions <NUM> reaches the uppermost wiring layer of the wafer P2, or holes (via-holes) may be formed below the concave portions <NUM>. The order of forming the plurality of concave portions <NUM> and the holds is not particularly limited.

Next, an extra amount of the conductor material <NUM> is removed by the CMP method to form the conductor portions <NUM> as illustrated in <FIG>. If holes are formed below the concave portions <NUM>, via-holes located below the conductor portions <NUM> are formed in the portions corresponding to the holes. The formation of the conductor portions <NUM> with an appropriate density over the entire chip area can prevent dishing or erosion from occurring due to the CMP process during the CMP process. This leads to an improvement in the flatness of the surface of the semiconductor wafer for the second semiconductor component <NUM> before bonding, and also leads to a reduction in defects caused due to a step during bonding. Through this process, the second wiring structure <NUM> is completed.

Next, as illustrated in <FIG>, the wafer planarized by the CMP method in step S205 is diced to form the second semiconductor component <NUM>. As a dicing method, a dicing process such as blade dicing using a blade, or laser dicing using a laser is used. Two or more types of these methods may be used in combination.

Through the above-described processes, the second semiconductor component <NUM> before bonding illustrated in <FIG> is completed.

The contour of the second surface S2 serving as the bonded surface of the second semiconductor component <NUM> is formed by dicing in step S206. If chipping occurs in the dicing process, the flatness of the second surface S2 decreases in the vicinity of the contour of the second surface S2, which may result in generation of a step. Accordingly, the second semiconductor component <NUM> may include a step in the normal direction of the second surface S2 in the vicinity of the contour of the second surface S2.

Through the above-described processes, the second semiconductor component <NUM> before bonding is completed.

Lastly, a manufacturing method of the semiconductor device <NUM> will be described with reference to a flowchart illustrated in <FIG> and <FIG>. <FIG> is a flowchart illustrating a manufacturing method of the semiconductor device <NUM>. <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the semiconductor device <NUM>. <FIG> each illustrate a part of the wafer.

As illustrated in <FIG>, the second semiconductor component <NUM> is reversed to face the wafer to be used for the first semiconductor component <NUM>. More specifically, the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> are opposed to each other so that the second surface S2 of the second semiconductor component <NUM> and the first surface S1 of the first semiconductor component <NUM> face each other.

An alignment process is performed such that the conductor portions <NUM> of the first semiconductor component <NUM> and the conductor portions <NUM> of the second semiconductor component <NUM> overlap each other in a planar view and the insulator portion <NUM> of the first semiconductor component <NUM> and the insulator portion <NUM> of the second semiconductor component <NUM> overlap each other in a planar view. The alignment process may be performed by rotating the first semiconductor component <NUM> in an XY direction within an XY plane, or may be performed by rotating the second semiconductor component <NUM> in the XY direction within the XY plane, or may be performed using these methods in combination.

According to the present exemplary embodiment, in this process, the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> are aligned such that the first region A1 obtained by vertically projecting the first surface S1 on the virtual plane VP is included in the second region A2 obtained by vertically projecting the second surface S2 on the virtual plane VP. This prevents the contour of the second surface S2 of the second semiconductor component <NUM> from contacting the first surface S1 of the first semiconductor component <NUM> even when the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> are bonded together in the subsequent processes. As described above, the second semiconductor component <NUM> can include a step in the vicinity of the contour of the second surface S2. However, according to the present exemplary embodiment, the portion where the flatness of the second surface S2 is likely to decrease can be prevented from being included in the bonded surface S3. This leads to an increase in the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM> can be increased, and also leads to an increase in the reliability of bonding.

Further, the contour of the second surface S2 of the second semiconductor component <NUM> may preferably fully overlap the concave portion <NUM> of the wafer for the first semiconductor component <NUM> in a state where the alignment is completed in this process. In other words, the entire region (shape) obtained by vertically projecting the contour of the second surface S2 on the virtual plane VP may be preferably included in the region obtained by vertically projecting the concave portion <NUM> on the virtual plane VP. This enables the contour of the second surface S2 to face the concave portion <NUM> even when the second semiconductor component <NUM> and the wafer to be used for the first semiconductor component <NUM> are bonded together in the subsequent process. Accordingly, the contour of the second surface S2 of the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> can be prevented from contacting each other during bonding. This leads to an increase in the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM> can be increased, and also leads to an increase in the reliability of bonding.

The above-described distance "c" corresponds to the width of the narrowest portion of the region where the second surface S2 of the second semiconductor component <NUM> and the concave portion <NUM> overlap each other in a planar view (see <FIG>). As described above, when the distance "c" is more than or equal to <NUM>, the portion of the second surface S2 where the flatness is likely to decrease can be more reliably prevented from being included in the bonded surface S3, thereby further increasing the reliability of bonding.

Next, the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> are bonded together on the bonded surface S3 as illustrated in <FIG>. After bonding, the structure is obtained in which the second semiconductor component <NUM> is stacked on the wafer for the first semiconductor component <NUM>. Bonding may be performed by, for example, performing a temporary bonding process and then performing a main bonding process. First, the insulator portion <NUM> of the first surface S1 and the insulator portion <NUM> of the second surface S2 are activated by plasma activation and then the activated insulator portions <NUM> and <NUM> are bonded together, thereby performing the temporary bonding process for bonding the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM>. Thereafter, for example, a heat treatment is performed at <NUM> to thereby bond the insulator portion <NUM> and the insulator portion <NUM> on the bonded surface S3 more tightly (main bonding process) than in the temporary bonding process. The conductor portions <NUM> and the conductor portions <NUM> are bonded together by interdiffusion of copper between the conductor portions <NUM> and the conductor portions <NUM>.

The heat treatment may cause heat deformation due to the difference in the coefficient of thermal expansion between the conductor portions <NUM> and <NUM> and the insulator portions <NUM> and <NUM>. If heat deformation occurs, the flatness of each of the first surface S1 and the second surface S2 decreases, which leads to a decrease in bonding strength. Accordingly, in the present exemplary embodiment, the depth "b" of the concave portion <NUM> is set to be greater than the depth "e" of the bottom of each conductor portion <NUM> and the thickness of the wiring layer forming the first surface S1. Consequently, bonding can be performed while reducing effects due to heat deformation that can be caused during the heat treatment. This leads to an increase in the reliability of bonding.

After bonding, a process for processing the second semiconductor component <NUM> stacked on the wafer used for the first semiconductor component <NUM> may be provided. For example, a process for reducing the thickness of the second semiconductor substrate <NUM> of the second semiconductor component <NUM> may be provided. As a method for reducing the thickness of the second semiconductor substrate <NUM>, backgrinding, CMP, etching, or the like can be used. Alternatively, a film formation process for forming a film, such as a metal oxide film, an antireflection film, or an insulation film, may be provided.

Steps S301 and S302 may be repeatedly performed to stack a plurality of second semiconductor components <NUM> on a single wafer for the first semiconductor component <NUM> as illustrated in <FIG>. In this case, the temporary bonding process is performed on each of the plurality of second semiconductor components <NUM>, and the main bonding process may be collectively performed on the plurality of second semiconductor components <NUM>. Examples of the configuration in which the plurality of second semiconductor components <NUM> is stacked on a single wafer for the first semiconductor component <NUM> include a configuration in which the plurality of second semiconductor components <NUM> is stacked on different regions, respectively, on the wafer for the first semiconductor component <NUM>. Alternatively, one second semiconductor component <NUM> may be stacked on another second semiconductor component <NUM> that is already stacked on the wafer for the first semiconductor component <NUM>. According to this configuration, a semiconductor component formed by stacking three or more components (semiconductor components) can be obtained.

Next, the wafer for the first semiconductor component <NUM> is diced to obtain the semiconductor device <NUM> as illustrated in <FIG>. Thus, the semiconductor device <NUM> is completed.

The present exemplary embodiment described above illustrates a configuration example where the first semiconductor component <NUM> in the shape of a wafer is bonded to the second semiconductor component <NUM> that is diced and in the shape of a chip (also called a die). This bonding method is also called die-to-wafer bonding. However, the bonding method is not limited to this example. The first semiconductor component <NUM> that is diced and in the shape of a chip may also be bonded to the second semiconductor component <NUM> that is in the shape of a chip. Also, in this case, the first semiconductor component <NUM> is provided with the concave portion <NUM>, which leads to an increase in the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM>, and also leads to an increase in the reliability of bonding.

<FIG> each illustrate the semiconductor device <NUM> according to a second exemplary embodiment. <FIG> is a sectional view of the semiconductor device <NUM>. <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on a virtual plane VP. In the present exemplary embodiment, components similar to those in a sectional structure of the semiconductor device <NUM> illustrated in <FIG> are denoted by the same reference numerals, and repeated descriptions are omitted.

As illustrated in <FIG>, in the present exemplary embodiment, the second semiconductor component <NUM> includes a concave portion <NUM> that is recessed toward the second semiconductor substrate <NUM> from the second surface S2. The concave portion <NUM> includes a bottom <NUM>. The bottom <NUM> of the concave portion <NUM> may be a deepest portion from the second surface S2. The second semiconductor component <NUM> includes a fourth surface S4 located on a side of the concave portion <NUM> that is opposite to the second surface S2.

The size and layout relationship of the first semiconductor component <NUM> and the second semiconductor component <NUM> that constitute the semiconductor device <NUM> according to the present exemplary embodiment will be described with reference to <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane. Assuming that a plane parallel to the first surface S1 is defined as the virtual plane VP, consider a region obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane VP in the normal direction of the virtual plane VP. Assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first surface S1 on the virtual plane VP is the first region A1, and a region having a circumference corresponding to a shape obtained by vertically projecting the second surface S2 on the virtual plane VP is an eighth region A8. In other words, the first region A1 is a region surrounded by the shape obtained by vertically projecting the first surface S1 on the virtual plane VP, and the eighth region A8 is a region surrounded by the shape obtained by vertically projecting the second surface S2 on the virtual plane VP. Also, assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first wiring structure <NUM> on the virtual plane VP is the third region A3, and a region having a circumference corresponding to a shape obtained by vertically projecting the second wiring structure <NUM> on the virtual plane VP is the fourth region A4. In other words, the third region A3 is a region surrounded by the shape obtained by vertically projecting the first wiring structure <NUM> on the virtual plane VP, and the fourth region A4 is a region surrounded by the shape obtained by vertically projecting the second wiring structure <NUM> on the virtual plane VP.

As illustrated in <FIG>, in the semiconductor device <NUM>, the regions (first region A1, third region A3, fourth region A4, and eighth region A8) satisfy the following relations (<NUM>) to (<NUM>).

As illustrated in <FIG>, in the semiconductor device <NUM>, the area of the first region A1 is smaller than the area of the third region A3 and is smaller than the area of the fourth region A4. In the present exemplary embodiment, the semiconductor device <NUM> satisfies the relation that (area of first region A1) < (area of eighth region A8) < (area of fourth region A4) < (area of third region A3).

As described in detail below, in the present exemplary embodiment, the contour of the first surface S1 is formed by the etching process, the contour of the second surface S2 is formed by the etching process, and the contour of the fourth surface S4 is formed by the dicing process such as blade dicing. In general, during the dicing process such as blade dicing, damage can be added to an object to be processed, which can cause a phenomenon called chipping in which a chip end face is chipped off after cutting. If chipping occurs during cutting of the second semiconductor component <NUM>, the flatness of the fourth surface S4 decreases in the vicinity of the contour of the fourth surface S4, which may result in generation of a step. Thus, in the present exemplary embodiment, a step is more likely to occur in the vicinity (peripheral portion) of the contour of the fourth surface S4 of the second semiconductor component <NUM> than in the vicinity of the contour of the first surface S1 of the first semiconductor component <NUM>.

When the above-described relations (<NUM>) and (<NUM>) are satisfied, at least a part of the area in the vicinity (peripheral portion) of the contour of the fourth surface S4 is not included in the second surface S2. As a result, the portion of the second surface S2 where the flatness is likely to decrease can be prevented from being included in the bonded surface S3. This leads to an increase in the bonding strength between the first semiconductor component <NUM> and the second semiconductor component <NUM>, and also leads to an increase in the reliability of bonding.

Assume that a region having a circumference corresponding to a shape obtained by vertically projecting the first semiconductor substrate <NUM> on the virtual plane VP is the fifth region A5, and a region having a circumference corresponding to a shape obtained by vertically projecting the second semiconductor substrate <NUM> on the virtual plane VP is the sixth region A6. In other words, the fifth region A5 is a region surrounded by the shape obtained by vertically projecting the first semiconductor substrate <NUM> on the virtual plane VP, and the sixth region A6 is a region surrounded by the shape obtained by vertically projecting the second semiconductor substrate <NUM> on the virtual plane VP. As illustrated in <FIG>, in the semiconductor device <NUM>, the fifth region A5 and the sixth region A6 may preferably satisfy the following relations (<NUM>) and (<NUM>).

When the relation (<NUM>) is satisfied in addition to the relations (<NUM>) and (<NUM>), the circumference of the first region A1 and the circumference of the eighth region A8 do not overlap each other and the circumference of the first region A1 is located at a distance from the circumference of the eighth region A8 on the inside of the circumference of the eighth region A8 as illustrated in <FIG>. Thus, the entire circumferential portion of the second surface S2 is not included in the bonded surface S3.

As illustrated in <FIG>, in the present exemplary embodiment, the second semiconductor component <NUM> includes the concave portion <NUM> that is recessed toward the second semiconductor substrate <NUM> from the second surface S2. In the present exemplary embodiment, the bottom <NUM> of the concave portion <NUM> is located inside the second wiring structure <NUM>. However, the location of the bottom <NUM> of the concave portion <NUM> is not limited to this example. The bottom <NUM> of the concave portion <NUM> may be located inside the second semiconductor substrate <NUM>.

In the length that is vertical to the second surface S2 on a section of the second semiconductor component <NUM> taken along a plane vertical to the second surface S2, the second semiconductor component <NUM> includes a third portion <NUM> with a third length, and a fourth portion <NUM> with a fourth length longer than the third length. The third length and the fourth length correspond to the length in the Z-direction of the third portion <NUM> and the length in the Z-direction of the fourth portion <NUM>, respectively, in <FIG>. In other words, the position of the bottom <NUM> described above corresponds to the position of the lower surface of the fourth portion <NUM>.

The concave portion <NUM> may preferably surround the second surface S2 in a planar view of the second surface S2. In other words, the fourth portion <NUM> may preferably surround the third portion <NUM> in a planar view of the second surface S2. If the concave portion <NUM> is formed to surround the second surface S2 in a planar view, the above-described relations (<NUM>) and (<NUM>) can be satisfied. This leads to a further increase in the reliability of bonding as described above.

Assume that the depth of the concave portion <NUM>, or the difference between the third length and the fourth length is represented by "f". In other words, the depth "f" of the concave portion <NUM> corresponds to the depth of the bottom <NUM> of the concave portion <NUM> based on a plane including the second surface S2, or corresponds to the distance from the plane including the second surface S2 to the bottom <NUM> of the concave portion <NUM>.

Also, assume that the depth of the bottom of each conductor portion <NUM> included in the second semiconductor component <NUM> is represented by "g". In other words, the depth "g" of the bottom of each conductor portion <NUM> corresponds to the depth of the bottom of each conductor portion <NUM> based on the plane including the second surface S2, or corresponds to the distance from the plane including the second surface S2 to the bottom of each conductor portion <NUM>.

In this case, the depth "f" of the concave portion <NUM> may preferably be greater than the depth "g" of the bottom of each conductor portion <NUM> (f > g). In other words, the bottom <NUM> of the concave portion <NUM> may preferably be located at a position further from the plane including the second surface S2 than the bottom of each conductor portion <NUM>. The depth "f" of the concave portion <NUM> may preferably be greater than the thickness of the wiring layer forming the second surface S2 in the at least one wiring layer forming the second wiring structure <NUM>. As described below, in the process of bonding the first semiconductor component <NUM> and the second semiconductor component <NUM>, the first surface S1 of the first semiconductor component <NUM> and the second surface S2 of the second semiconductor component <NUM> are bonded together and then a heat treatment is performed, thereby increasing the bonding strength. In the heat treatment, heat deformation can occur due to, for example, a difference in the coefficient of thermal expansion of materials forming the conductor portions <NUM> and <NUM> and the insulator portions <NUM> and <NUM>. According to the present exemplary embodiment, the depth "f" of the concave portion <NUM> is set to be greater than the depth "g" of the bottom of each conductor portion <NUM> and the thickness of the wiring layer forming the second surface S2, thereby making it possible to perform bonding while reducing effects due to heat deformation. This leads to an increase in the reliability of bonding.

As illustrated in <FIG>, the distance from the sealing ring <NUM> to a side wall of the concave portion <NUM> is represented by "h". In this case, the distance "h" may be preferably more than or equal to <NUM>. Assuming that a region obtained by projecting the sealing ring <NUM> on the virtual plane VP in the normal direction of the virtual plane VP is a ninth region S9, the shortest distance "h" between the circumference of the ninth region S9 and the circumference of the second region A2 may be preferably more than or equal to <NUM>. When the distance "h" is more than or equal to <NUM>, damage to the second semiconductor component <NUM> during formation of the concave portion <NUM> can be reduced. When the distance "h" is more than or equal to <NUM>, penetration of water can be prevented even in a case where the concave portion <NUM> is formed.

It may be preferable that the contour of the eighth region A8 have no internal angle of less than or equal to <NUM>°. In the present exemplary embodiment, the contour of the eighth region A8 has no corner and the long sides and short sides of the contour are smoothly connected with a curve having an arc shape as illustrated in <FIG>. As described below, the process of bonding the first semiconductor component <NUM> and the second semiconductor component <NUM> is completed by bonding the entire first surface S1 to the second surface S2. In this case, if the contour of the eighth region A8 has an internal angle of less than or equal to <NUM>°, progress in bonding between the first surface S1 and the second surface S2 may be inhibited at the angle and the bonding may progress unevenly. This may cause deterioration in the reliability of bonding. In contrast, according to the present exemplary embodiment, the contour of the eighth region A8 is set to have no internal angle of less than or equal to <NUM>°, thereby preventing the bonding from progressing unevenly, which leads to an increase in the reliability of bonding.

While the present exemplary embodiment illustrates an example where the long sides and short sides of the contour of the eighth region A8 are smoothly connected with a curve having an arc shape, the present exemplary embodiment is not limited to this example. The long sides and short sides may be smoothly connected with a curve having a shape other than an arc shape. The curvature of each curve is not particularly limited, as long as the eighth region A8 includes a curved portion. The contour of the eighth region A8 may have an internal angle of more than <NUM>°.

Next, a manufacturing method of the semiconductor device <NUM> will be described. In the present exemplary embodiment, repeated descriptions of processes in the manufacturing method that are similar to those in the above-described exemplary embodiment are omitted. A manufacturing method of the wafer for the second semiconductor component <NUM> will be described.

A manufacturing method of the wafer for the second semiconductor component <NUM> will now be described with reference to <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the wafer for the second semiconductor component <NUM>. <FIG> each illustrate a part of the wafer.

<FIG> are similar to steps S201 to S205, respectively, and thus repeated descriptions thereof are omitted.

The concave portion <NUM> is formed by photolithography and etching as illustrated in <FIG>. The region surrounded by the concave portion <NUM> on the upper surface of the wafer for the second semiconductor component <NUM> corresponds to the second surface S2. Accordingly, the contour of the second surface S2 is formed by the etching process.

Next, the wafer is diced to form the second semiconductor component <NUM> as illustrated in <FIG>. As a dicing method, a dicing process such as blade dicing using a blade, or laser dicing using a laser is used. Two or more types of these methods may be used in combination.

Through the above-described processes, the second semiconductor component <NUM> before bonding as illustrated in <FIG> is completed.

The contour of the fourth surface S4 of the second semiconductor component <NUM> is formed by dicing in step S402. If chipping occurs in the dicing process, the flatness of the fourth surface S4 decreases in the vicinity of the contour of the fourth surface S4, which may result in generation of a step. Accordingly, the second semiconductor component <NUM> may include a step in the normal direction of the fourth surface S4 in the vicinity of the contour of the fourth surface S4.

<FIG> each illustrate the semiconductor device <NUM> according to a third exemplary embodiment. <FIG> is a sectional view of the semiconductor device <NUM>, and <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane VP. In the present exemplary embodiment, components similar to those in the sectional structure of the semiconductor device <NUM> illustrated in <FIG> and <FIG> are denoted by the same reference numerals, and repeated descriptions are omitted.

As illustrated in <FIG>, in the present exemplary embodiment, the first semiconductor component <NUM> includes the concave portion <NUM> that is recessed toward the first semiconductor substrate <NUM> from the first surface S1. A side surface of the concave portion <NUM> that faces the first wiring structure <NUM> may preferably have no internal angle of less than or equal to <NUM>°. In the present exemplary embodiment, as illustrated in <FIG>, the side surface of the concave portion <NUM> has an internal angle of more than or equal to <NUM>° and the side surfaces of the concave portion <NUM> are in contact with the contour of the third region A3.

The semiconductor device <NUM> is diced by a dicing process, such as blade dicing using a blade, or laser dicing using a laser. In this case, a side surface <NUM> of the concave portion <NUM> that faces the first wiring structure <NUM> is formed to have no internal angle of less than or equal to <NUM>°, thereby preventing damage to the first wiring structure <NUM> due to stress concentration on a corner portion during the dicing process, which leads to an increase in the reliability of bonding.

More specifically, as illustrated in <FIG>, in the present exemplary embodiment, the side surface <NUM> formed in a range from the first surface S1 to the third region A3 in a sectional view has a tapered shape. If dicing is performed in the state illustrated in <FIG>, stress is concentrated on corner portions included in the circumference of the first wiring structure <NUM> and on corner portions included in the circumference of the second wiring structure <NUM> during the dicing process. In contrast, the side surface <NUM> has a tapered shape, which makes it possible to reduce the stress concentration, according to the present exemplary embodiment.

The second semiconductor component <NUM> also includes the concave portion <NUM> that is recessed toward the second semiconductor substrate <NUM> from the second surface S2. A side surface <NUM> of the concave portion <NUM> that faces the second wiring structure <NUM> may preferably have no internal angle of less than or equal to <NUM>°. In the present exemplary embodiment, the side surface <NUM> of the concave portion <NUM> has an internal angle of more than or equal to <NUM>° as illustrated in <FIG>, and the side surface <NUM> of the concave portion <NUM> is in contact with the contour of the fourth region A4.

More specifically, in the present exemplary embodiment, the side surface <NUM> formed in a range from the second surface S2 to the fourth region A4 in a sectional view has a tapered shape as illustrated in <FIG>. If dicing is performed in the state illustrated in <FIG>, stress is concentrated on corner portions included in the circumference of the first wiring structure <NUM> and on corner portions included in the circumference of the second wiring structure <NUM> during the dicing process. In contrast, according to the present exemplary embodiment, the side surface <NUM> has a tapered shape, which makes it possible to reduce the stress concentration.

The second semiconductor component <NUM> is diced by a dicing process, such as blade dicing using a blade, or laser dicing using a laser. In this case, the side surface <NUM> of the concave portion <NUM> that faces the second wiring structure <NUM> is formed to have no internal angle of less than or equal to <NUM>°. This configuration can prevent damage to the second wiring structure <NUM> due to stress concentration on the corner portions during the dicing process, and lead to an increase in the reliability of bonding.

While the present exemplary embodiment described above illustrates an example where the side surfaces of the concave portion <NUM> of the first semiconductor component <NUM> and the concave portion <NUM> of the second semiconductor component <NUM> have no internal angle of less than or equal to <NUM>° (the example having a tapered shape), the present exemplary embodiment is not limited to this example. Only the concave portion <NUM> of the first semiconductor component <NUM> may include a side surface having no internal angle of less than or equal to <NUM>°. Alternatively, only the concave portion <NUM> of the second semiconductor component <NUM> may include a side surface having no internal angle of less than or equal to <NUM>° (having a tapered shape).

Next, a manufacturing method of the semiconductor device <NUM> will be described. Repeated descriptions of processes in the manufacturing method according to the present exemplary embodiment that are similar to those in the manufacturing methods according to the first to fourth exemplary embodiments are omitted. A manufacturing method of the wafer for the first semiconductor component <NUM> before bonding will be described below.

A manufacturing method of the wafer for the first semiconductor component <NUM> will now be described with reference to <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the wafer for the first semiconductor component <NUM>. <FIG> each illustrate a part of the wafer.

<FIG> are similar to steps S101 to S105, respectively, and thus repeated descriptions thereof are omitted.

As illustrated in <FIG>, an insulation film <NUM> is formed on a wafer P3. Examples of the insulation film <NUM> include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, and a fluoride-containing silicon oxide film. The insulation film <NUM> may be formed of a single layer made of one type of material, or may be formed of a plurality of layers made of different types of materials.

Next, a concave portion <NUM> is formed by photolithography and etching.

As illustrated in <FIG>, an extra amount of the insulation film <NUM> on the conductor portions <NUM> is then removed by CMP to form the conductor portions <NUM>. Planarization is performed by CMP, thereby actively polishing the corner portions of the concave portion <NUM>. Thus, the side surface <NUM> is formed into a tapered shape. The formation of the conductor portions <NUM> with an appropriate density over the entire chip area makes it possible to prevent dishing or erosion from occurring due to the CMP process during the CMP process. This leads to an improvement in the flatness of the surface of the semiconductor wafer for the first semiconductor component <NUM> before bonding, and also leads to a reduction in defects caused due to a step during bonding. Through this process, the first wiring structure <NUM> is completed.

Lastly, a manufacturing method of the semiconductor device <NUM> in a case where only the concave portion <NUM> of the first semiconductor component <NUM> includes a side surface <NUM> having no internal angle of less than or equal to <NUM>° will be described with reference to <FIG> are schematic diagrams each illustrating a process in the manufacturing method of the semiconductor device <NUM>. <FIG> each illustrate a part of the wafer. The manufacturing method of the second semiconductor component <NUM> is similar to that of the first exemplary embodiment, and thus repeated descriptions thereof are omitted.

As illustrated in <FIG>, the second semiconductor component <NUM> is reversed to face the wafer for the first semiconductor component <NUM>. More specifically, the second semiconductor component <NUM> and the first semiconductor component <NUM> are opposed to each other so that the second surface S2 of the second semiconductor component <NUM> and the first surface S1 of the wafer for the first semiconductor component <NUM> face each other. The alignment process is then performed such that the conductor portions <NUM> of the first semiconductor component <NUM> and the conductor portions <NUM> of the second semiconductor component <NUM> overlap each other in a planar view and the insulator portion <NUM> of the first semiconductor component <NUM> and the insulator portion <NUM> of the second semiconductor component <NUM> overlap each other in a planar view. The alignment process may be performed by rotating the first semiconductor component <NUM> in the XY direction within the XY plane, or by rotating the second semiconductor component <NUM> in the XY direction within the XY plane, or may be performed using these methods in combination.

Next, the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM> are brought into contact with each other and bonded together on the bonded surface S3 as illustrated in <FIG>. After bonding, the structure is thereby obtained in which the second semiconductor component <NUM> is stacked on the wafer for the first semiconductor component <NUM>. Bonding may be achieved by, for example, performing the temporary bonding process and then performing the main bonding process. First, the insulator portion <NUM> of the first surface S1 and the insulator portion <NUM> of the second surface S2 are activated by plasma activation. The activated insulator portions <NUM> and <NUM> are then bonded together, thereby performing a temporary bonding process for bonding the second semiconductor component <NUM> and the wafer for the first semiconductor component <NUM>. Thereafter, for example, a heat treatment is performed at <NUM> to thereby bond the insulator portion <NUM> and the insulator portion <NUM> on the bonded surface S3 more tightly than in the temporary bonding process (main bonding process). The conductor portions <NUM> and the conductor portions <NUM> are bonded together by interdiffusion of copper between the conductor portions <NUM> and the conductor portions <NUM>.

After bonding, a process for processing the second semiconductor component <NUM> stacked on the wafer for the first semiconductor component <NUM> may be provided. For example, a process for reducing the thickness of the second semiconductor substrate <NUM> of the second semiconductor component <NUM> may be provided. As a method for reducing the thickness of the second semiconductor substrate <NUM>, backgrinding, CMP, etching, or the like can be used. Alternatively, a film formation process for forming a film may be provided, such as a metal oxide film, an antireflection film, and an insulation film.

Next, as illustrated in <FIG>, the wafer for the first semiconductor component <NUM> is diced to obtain the semiconductor device <NUM>. The side surface <NUM> of the concave portion <NUM> has a tapered shape and is formed to have no internal angle "i" of less than or equal to <NUM>°. This prevents stress from being locally concentrated on the corner portions of the concave portion <NUM> during dicing of the semiconductor device <NUM>, thereby preventing damage to the first wiring structure <NUM>. The semiconductor device <NUM> is thus completed. The present exemplary embodiment described above illustrates a configuration example where the first semiconductor component <NUM> in the shape of a wafer is bonded to the second semiconductor component <NUM> that is diced to be in the shape of a chip (also called a die). This bonding method is also called die-to-wafer bonding. However, the present exemplary embodiment is not limited to this example. The first semiconductor component <NUM> that is also diced to be in the shape of a chip may be bonded to the second semiconductor component <NUM> that is in the shape of a chip.

<FIG> each illustrate the semiconductor device <NUM> according to a fourth exemplary embodiment. <FIG> is a sectional view of the semiconductor device <NUM>, and <FIG> illustrates a projection of the semiconductor device <NUM> obtained by vertically projecting each portion of the semiconductor device <NUM> on the virtual plane VP. In the present exemplary embodiment, components similar to those in a sectional structure of the semiconductor device <NUM> illustrated in <FIG>, <FIG>, and <FIG> are denoted by the same reference numerals, and repeated descriptions are omitted.

In the present exemplary embodiment, the first semiconductor component <NUM> includes the concave portion <NUM> recessed toward the first semiconductor substrate <NUM> from the first surface S1 as illustrated in <FIG>. The side surface <NUM> of the concave portion <NUM> that faces the first wiring structure <NUM> is preferably smoothly connected with a curve having an arc shape and may preferably have no internal angle of less than or equal to <NUM>°. This configuration prevents stress from being locally concentrated on the corner portions of the concave portion <NUM> during dicing of the semiconductor device <NUM>, thereby preventing damage to the first wiring structure <NUM>. While the present exemplary embodiment illustrates an example where the side surface <NUM> of the concave portion <NUM> that faces the first wiring structure <NUM> is smoothly connected with a curve having an arc shape, the present exemplary embodiment is not limited to this example. The side surface <NUM> of the concave portion <NUM> may be smoothly connected with a curve having a shape other than an arc shape. The curvature of the curve is not particularly limited. Although not illustrated, the side surface <NUM> illustrated in <FIG> may be formed with an arc shape instead of a tapered shape.

Equipment EQP including the semiconductor device <NUM> in the above-described exemplary embodiments will be described in detail below with reference to <FIG> is a block diagram illustrating a schematic configuration of the equipment EQP.

The equipment EQP includes a package PKG for packaging the semiconductor device <NUM>. In the present exemplary embodiment, a photoelectric conversion apparatus (solid image capturing apparatus) is used as the semiconductor device <NUM>. The semiconductor device <NUM> includes a pixel region PX in which pixel circuits PXC are arranged in a matrix, and a peripheral region PR that is located near the pixel region PX. Peripheral circuits can be provided in the peripheral region PR. The pixel region PX may be provided in one of the first semiconductor component <NUM> and the second semiconductor component <NUM>, and the peripheral region PR may be provided in the other of the first semiconductor component <NUM> and the second semiconductor component <NUM>.

The package PKG can include a base to which the semiconductor device <NUM> is fixed, a lid that is opposed to the semiconductor device <NUM> and is made of glass or the like, and connection members, such as a bonding wire and a bump, to connect terminals provided on the base to terminals provided on the semiconductor device <NUM>.

The equipment EQP may include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN.

The optical system OPT is configured to form an image on the semiconductor device <NUM>. The optical system OPT includes, for example, a lens, a shutter, and a mirror.

The control device CTRL is configured to control the semiconductor device <NUM>. The control device CTRL is, for example, an arithmetic device, such as an application specific integrated circuit (ASIC). The processing device PRCS is configured to process a signal output from the semiconductor device <NUM>. The processing device PRCS is an arithmetic device, such as a central processing unit (CPU) or an ASIC, to configure an analog front-end (AFE) or a digital front-end (DFE).

The display device DSPL is an organic electroluminescence (EL) display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device <NUM>. The storage device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device <NUM>. The storage device MMRY is a volatile memory, such as a static random access memory (SRAM), a dynamic RAM, or a nonvolatile memory, such as a flash memory or a hard disk drive.

The mechanical device MCHN includes a movable portion such as a motor or an engine, or a propulsion portion. The equipment EQP displays signals output from the semiconductor device <NUM> on the display device DSPL and transmits the signals to the outside using a communication apparatus (not illustrated) included in the equipment EQP. Thus, the equipment EQP may preferably include the storage device MMRY and the processing device PRCS separately from a storage circuit and an arithmetic circuit included in the semiconductor device <NUM>. The mechanical device MCHN may be controlled based on signals output from the semiconductor device <NUM>.

The equipment EQP is suitably used as electronic equipment, such as an information terminal (e.g., a smartphone and a wearable terminal) having an image capturing function, and a camera (e.g., a lens-interchangeable camera, a compact camera, a video camera, and a monitoring camera). The mechanical device MCHN in a camera is configured to drive components of the optical system OPT to perform a zooming operation, a focusing operation, and a shutter operation.

The equipment EQP can be transport equipment such as a vehicle, a ship, or a flight vehicle. The mechanical device MCHN in transport equipment can be used as a movable device. The equipment EQP serving as transport equipment is suitably used for equipment for transporting the semiconductor device <NUM>, and equipment for assisting and/or automation of driving (operation) using the image capturing function. The processing device PRCS for assisting and/or automation of driving (operation) is configured to perform processing for operating the mechanical device MCHN as a movable device based on information obtained by the semiconductor device <NUM>. Alternatively, the equipment EQP may be medical equipment such as an endoscope, measurement equipment such as a ranging sensor, or analysis equipment such as an electron microscope.

According to the present exemplary embodiment, the reliability of a bonded portion of a semiconductor device can be improved. Thus, the use of the semiconductor device according to the present exemplary embodiment enhances the performance of the semiconductor device. For example, when the semiconductor device is mounted on transport equipment, an excellent image quality and high measurement accuracy can be obtained during image capturing on the outside of the transport equipment or during measurement of an external environment, accordingly. In terms of enhancement of the performance of transport equipment, it is therefore advantageous to determine to mount the semiconductor device according to the present exemplary embodiment on transport equipment to manufacture and sell the transport equipment.

An image capturing system according to a sixth exemplary embodiment of the present invention will now be described with reference to <FIG> is a block diagram illustrating a schematic configuration of the image capturing system according to the sixth exemplary embodiment.

The semiconductor device <NUM> (image capturing apparatus) described in the above-described exemplary embodiments can be applied to various image capturing systems. The applicable image capturing systems are not particularly limited. Examples of the applicable image capturing systems include various types of equipment, such as a digital still camera, a digital camcorder, a monitoring camera, a copying machine, a facsimile machine, a cellular phone, an on-vehicle camera, an observation satellite, and a medical camera. Examples of the applicable image capturing systems also include a camera module including an optical system (i.e., a lens), and an image capturing apparatus (photoelectric conversion apparatus). <FIG> illustrates a block diagram of a digital still camera as an example of the applicable image capturing systems.

As illustrated in <FIG>, an image capturing system <NUM> includes an image capturing apparatus <NUM>, an image capturing optical system <NUM>, a CPU <NUM>, a lens control unit <NUM>, an image capturing apparatus control unit <NUM>, and an image processing unit <NUM>. The image capturing system <NUM> also includes a diaphragm shutter control unit <NUM>, a display unit <NUM>, an operation switch <NUM>, and a recording medium <NUM>.

The image capturing optical system <NUM> is an optical system for forming an optical image of an object, and includes a lens group and a diaphragm <NUM>. The diaphragm <NUM> has a light amount adjustment function to be used during image capturing by adjusting the aperture diameter of the diaphragm <NUM> and a function of an exposure time adjustment shutter during still image capturing. The lens group and the diaphragm <NUM> are held to be movable forward and backward along an optical axis, and a linked operation of these elements implements a scaling function (zooming function) and a focus adjustment function. The image capturing optical system <NUM> may be integrated with the image capturing system <NUM>, or may be an image capturing lens that is mountable on the image capturing system <NUM>.

The image capturing apparatus <NUM> is located such that an image capturing surface is located in the image space of the image capturing optical system <NUM>. The image capturing apparatus <NUM> corresponds to the semiconductor device <NUM> described in the first exemplary embodiment, and includes a complementary metal-oxide semiconductor (CMOS) sensor (pixel portion) and peripheral circuits (peripheral circuit region). The image capturing apparatus <NUM> includes pixels having a plurality of photoelectric conversion portions arranged two-dimensionally and color filters arranged on the pixels, thereby forming a two-dimensional single-plate color sensor. The image capturing apparatus <NUM> photoelectrically converts an object image formed by the image capturing optical system <NUM>, and outputs an image signal and a focus detection signal.

The lens control unit <NUM> is configured to control forward/backward driving of the lens group of the image capturing optical system <NUM> to perform the scaling function and the focus adjustment function, and includes circuits and processing devices configured to implement these functions. The diaphragm shutter control unit <NUM> is configured to change the aperture diameter of the diaphragm <NUM> and adjust the amount of image capturing light (with an aperture value as variable), and includes circuits and processing devices configured to implement these functions.

The CPU <NUM> is a control device in a camera for performing various control operations on a camera body, and the CPU <NUM> includes an arithmetic unit, a read-only memory (ROM), a RAM, an analog-to-digital (A/D) converter, a digital-to-analog (D/A) converter, and a communication interface circuit. The CPU <NUM> controls the operation of each unit in the camera according to computer programs stored in the ROM or the like, and executes a series of image capturing operations, such as an autofocus (AF) operation including detection (focus detection) of a focus state of the image capturing optical system <NUM>, image processing, and recording. The CPU <NUM> also functions as a signal processing unit.

The image capturing apparatus control unit <NUM> controls the operation of the image capturing apparatus <NUM>, performs A/D conversion on a signal output from the image capturing apparatus <NUM>, and transmits the signal to the CPU <NUM>. The image capturing apparatus control unit <NUM> includes circuits and control devices configured to implement these functions. The A/D conversion function may be included in the image capturing apparatus <NUM>. The image processing unit <NUM> is a processing device that performs image processing, such as γ-conversion or color interpolation, on the signal obtained after the A/D conversion, thereby generating an image signal. The image processing unit <NUM> includes circuits and control devices configured to implement these functions. The display unit <NUM> is a display device such as a liquid crystal display device (LCD), and displays, for example, information about camera image capturing modes, a preview image before image capturing, an image for checking after image capturing, and an in-focus state during focus detection. The operation switch <NUM> includes a power supply switch, a release (image capturing trigger) switch, a zoom operation switch, and an image capturing mode selection switch. The recording medium <NUM> is used for recording captured images and the like. The recording medium <NUM> may be incorporated in the image capturing system, or may be a detachable medium such as a memory card.

As described above, the image capturing system <NUM> to which the semiconductor device <NUM> according to the first exemplary embodiment is applied is configured to thereby implement the image capturing system with a high performance.

An image capturing system and a moving body according to a seventh exemplary embodiment of the present invention will be described with reference to <FIG> each illustrate a schematic configuration of each of the image capturing system and the moving body according to the seventh exemplary embodiment.

<FIG> illustrates an example of an image capturing system <NUM> for an on-vehicle camera. The image capturing system <NUM> includes an image capturing apparatus <NUM>. The image capturing apparatus <NUM> corresponds to the semiconductor device <NUM> according to the first exemplary embodiment described above. The image capturing system <NUM> includes an image processing unit <NUM> as a processing device that performs image processing on a plurality of pieces of image data acquired by the image capturing apparatus <NUM>. The image capturing system <NUM> also includes a parallax acquisition unit <NUM> as a processing device that calculates a parallax (a phase difference between parallax images) based on a plurality of pieces of image data acquired by the image capturing apparatus <NUM>. The image capturing system <NUM> also includes a distance acquisition unit <NUM> as a processing device that calculates a distance to an object based on the calculated parallax. The image capturing system <NUM> also includes a collision determination unit <NUM> as a processing device that determines the possibility of occurrence of a collision based on the calculated distance. In this case, the parallax acquisition unit <NUM> and the distance acquisition unit <NUM> are examples of an information acquisition unit that acquires information, such as distance information indicating a distance to an object. In other words, the distance information is information about, for example, a parallax, a defocus amount, and a distance to an object. The collision determination unit <NUM> may determine the possibility of occurrence of a collision using any one of the distance information. The above-described processing devices may be implemented by exclusively-designed hardware, or may be implemented by general-purpose hardware used for calculations based on software modules. Alternatively, the processing devices may be implemented by a field programmable gate array (FPGA), an ASIC, or the like, or a combination thereof.

The image capturing system <NUM> is connected to a vehicle information acquisition apparatus <NUM>, and can obtain vehicle information, such as a vehicle speed, a yaw rate, and a steering angle. The image capturing system <NUM> is also connected to a control ECU <NUM> serving as a control device that outputs a control signal for causing a breaking force on a vehicle based on the determination result from the collision determination unit <NUM>. In other words, the control ECU <NUM> is an example of a moving body control unit that controls a moving body based on the distance information. The image capturing system <NUM> is also connected to an alarm apparatus <NUM> that issues an alarm to a driver based on the determination result from the collision determination unit <NUM>. For example, if it is highly likely that a collision may occur based on the determination result from the collision determination unit <NUM>, the control ECU <NUM> performs a vehicle control for avoiding a collision or reducing a damage by, for example, applying a brake, releasing an accelerator, or suppressing an engine output. The alarm apparatus <NUM> issues an alarm to a user by, for example, issuing an alarm such as sound, displaying alarm information on a screen of a car navigation system or the like, or applying a vibration to a seat belt or a steering wheel.

In the present exemplary embodiment, the image capturing system <NUM> captures an image of the periphery of the vehicle, for example, the front or the back of the vehicle. <FIG> illustrates a configuration example of the image capturing system <NUM> when an image of a front portion (image capturing range <NUM>) of the vehicle is captured. The vehicle information acquisition apparatus <NUM> sends an instruction to operate and cause the image capturing system <NUM> to execute image capturing. The use of the semiconductor device <NUM> according to the first exemplary embodiment as the image capturing apparatus <NUM> enables the image capturing system <NUM> according to the present exemplary embodiment to further improve the ranging accuracy.

While the above-described exemplary embodiment illustrate an example of the control operation for preventing one vehicle from colliding with another vehicle, the present exemplary embodiment can also be applied to, for example, a control operation for automatic driving by following another vehicle, and a control operation for automatic driving to prevent the vehicle from deviating from a lane. The image capturing system <NUM> can be applied to a vehicle such as automobile, and a moving body (transportation equipment), such as a ship, an aircraft, or an industrial robot. Examples of the movable device in the moving body (transport equipment) include various drive sources such as an engine, a motor, a wheel, and a propeller. Additionally, the movable device can be applied not only to a moving body, but also to a wide variety of equipment that uses object recognition, such as an intelligent transportation system (ITS).

According to an aspect of the present invention, it is possible to provide a technique that is advantageous in improvement in reliability of bonding in a semiconductor device obtained by bonding two semiconductor components on a bonded surface.

Claim 1:
A semiconductor device (<NUM>) comprising:
a first semiconductor component (<NUM>) including a first semiconductor substrate (<NUM>) and a first wiring structure (<NUM>) including at least one wiring layer and at least one insulation layer (<NUM>) stacked on the first semiconductor substrate, the first semiconductor component having a first surface (S1) located on a side of the first wiring structure that is opposite to the first semiconductor substrate; and
a second semiconductor component (<NUM>) including a second semiconductor substrate (<NUM>) and a second wiring structure (<NUM>) including at least one wiring layer and at least one insulation layer (<NUM>) stacked on the second semiconductor substrate, the second semiconductor component having a second surface (S2) located on a side of the second wiring structure opposite to the second semiconductor substrate, the first surface of the first semiconductor component and the second surface of the second semiconductor component being bonded together,
wherein in a case where a region having a circumference corresponding to a shape obtained by projecting the first surface on a virtual plane parallel to the first surface in a normal direction of the virtual plane is a first region (A1), a region having a circumference corresponding to a shape obtained by projecting the second surface on the virtual plane in the normal direction of the virtual plane is a second region (A2), a region having a circumference corresponding to a shape obtained by projecting the first wiring structure on the virtual plane in the normal direction of the virtual plane is a third region (A3), and a region having a circumference corresponding to a shape obtained by projecting the second wiring structure on the virtual plane in the normal direction of the virtual plane is a fourth region (A4), an area of the first region is smaller than an area of the second region, an entire circumference of the first region is included in the second region,
characterized in that
an area of the fourth region is smaller than an area of the third region, and an entire circumference of the fourth region is included in the third region.