Patent Description:
The present invention relates generally to quantum and classical digital superconducting circuits, and specifically to a reciprocal quantum logic (RQL) phase-mode flip-flop.

In the field of digital logic, extensive use is made of well known and highly developed CMOS (complimentary metal-oxide semiconductor) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions (JJs), with typical signal power of around <NUM> nanowatts (nW), at a typical data rate of <NUM> gigabits per second (Gb/s) or greater, and operating temperatures of around <NUM> kelvins.

A flip-flop is a bistable multivibrator, a two-stable-state circuit that can therefore be used to store state information and to change state by signals applied to one or more control inputs. In modern computing and communications electronics, flip-flops are the basic storage element in sequential logic. A conventional D flip-flop, e.g., one implemented in CMOS, has two binary inputs, a data input D and a clock input, and at least one output, Q. The D flip-flop captures the value of the D input at a definite portion of an input clock cycle, e.g., a rising edge or a falling edge, known as the capture time. That captured value becomes the Q output. The output Q does not change except at the capture time (or some small propagation delay thereafter). In practical implementations it is required that a data input D be stable for some setup time prior to the capture time and for some hold time after the capture time for the input to be reliably captured and propagated to the output.

Phase-mode logic allows digital values to be encoded as superconducting phases of one or more JJs. For example, a logical "<NUM>" may be encoded as a high phase and a logical "<NUM>" may be encoded as a low phase. For example, the phases may be encoded as being zero (meaning, e.g., logical "<NUM>") or 2π (meaning, e.g., logical "<NUM>"). These values persist across RQL AC clock cycles because there is no requirement for a reciprocal pulse to reset the JJ phase. Examples of RQL circuits including bi-stable loops (i.e. configured to have two states) are described in <CIT>, <CIT>, and <CIT>.

The invention is set out in the appended claims and defines in claim <NUM> a reciprocal quantum logic (RQL) phase-mode flip-flop that includes a storage loop and a comparator. The storage loop receives a data input signal on a data input line as positive or negative single flux quantum (SFQ) pulse and stores the data input signal in the storage loop, the storage loop being configured to contain one of -Φ0, zero, or +Φ0 of current. The comparator receives a logical clock input signal on a logical clock input line and compares the received logical clock input signal with the stored data input signal. The flip-flop further has an output signal line that transmits an output signal corresponding to a logical "<NUM>" or logical "<NUM>" value based on comparison, e.g., as a positive or negative SFQ pulse based on the data input signal as read substantially during a time of a logical clock input signal. By "substantially during times of logical clock input signals," it is meant that setup and hold times, including negative hold times, if applicable, are accounted for. The output pulse can correspond to a <NUM> or 2π quantum phase of an output Josephson junction (JJ).

According to the invention independent claim <NUM> defines a method of writing and reading a logical value to and from an RQL flip-flop. In the method, a data input SFQ pulse that is one of either positive or negative is provided to a data input of an RQL flip-flop. A storage loop in the RQL flip-flop is set from a ground state to a state that is the one of either positive or negative. A reciprocal SFQ pulse pair is provided to a clock input of the RQL flip-flop. An output signal corresponding to a logical "<NUM>" or logical "<NUM>" value is transmitted out of an output of the RQL flip-flop. The output signal can be, e.g., an SFQ pulse that is the one of either positive or negative. The storage loop is returned to the ground state.

This disclosure relates generally to quantum and classical digital superconducting circuits, and specifically to a reciprocal quantum logic (RQL) phase-mode flip-flop. The RQL phase-mode flip-flop can be implemented, for example, in a memory system (e.g., a quantum computing memory system) to store a logic state of an addressed memory cell. As an example, the inputs and the output can each be provided via a Josephson transmission line (JTL), such as in an RQL superconducting circuit.

An RQL phase-mode flip-flop can include a storage loop and a comparator, each of which can include Josephson junctions (JJs). A data input, which can be provided as a positive or negative single flux quantum SFQ pulse, can be stored in the storage loop to set the storage loop in a positive or negative state, respectively, effectively biasing an output JJ that can be shared between the storage loop and a comparator. The data input can be captured to the output upon the receipt of a logical clock SFQ reciprocal pulse pair to the comparator, when one of the pulses in the pair can cause the output JJ to preferentially trigger over an escape JJ in the comparator, owing to the output JJ having been biased by current in the storage loop.

<FIG> is an example block diagram of an RQL phase-mode flip-flop <NUM> having data input D, logical clock input LCLK, and output Q. The D and LCLK inputs and Q output follow the traditional flip-flop nomenclature described above, with logical clock input LCLK being the equivalent of an AC clock CLK in a CMOS flip-flop. Logical clock input LCLK can provide an SFQ signal and should not be confused with an RQL AC clock that may be used to provide reciprocal clock signals in an RQL system. Flip-flop <NUM> can include storage loop <NUM> configured to receive a data input signal from data input D and store it. Storage loop <NUM> can be configured to have three possible states, a ground state, a positive state, and a negative state. Flip-flop <NUM> can further include comparator <NUM> configured to receive a logical clock input signal from logical clock input LCLK and render a comparison between the received logical clock input signal and a stored data input signal, i.e., the state of the storage loop.

The combined function of storage loop <NUM> and comparator <NUM> can provide output Q. For example, flip-flop <NUM> can be configured such that if the storage loop is in the positive state and a positive signal is received on the logical clock input signal, output Q is asserted to its logical "<NUM>" value; and if the storage loop is in the negative state and a negative signal is received on the logical clock input signal, output Q is de-asserted to its logical "<NUM>" value. In such an example, any other combination of signals will have no effect on the logical state of output Q. Thus, for example, any received logical clock input signal, whether positive or negative, will not change the logical state of output Q when the storage loop is in its ground state; a negative logical clock signal will not de-assert output Q when the storage loop is in its positive state; and a positive logical clock signal will not assert output Q when the storage loop is in its negative state.

For example, SFQ pulses arriving at input D can consist of alternating positive and negative pulses consistent with RQL phase-mode data encoding. Multiple pulses can be allowed to arrive between assertions of the LCLK input. These successive pulses can serve to alternate the state of the internal storage loop <NUM> between the ground state and the positive state if the last output at Q was a logical "<NUM>" or between the ground state and the negative state if the last output at Q was a logical "<NUM>. " Only the state of the storage loop <NUM> when LCLK is asserted affects the output Q.

Each of storage loop <NUM> and comparator <NUM> can have at least one JJ. For example, storage loop <NUM> can have two JJs arranged in a loop, such that the direction of a current through the loop, or the absence of such current, determine which of the three aforementioned states the storage loop is in. Also, for example, comparator <NUM> can have two JJs that are directly connected to each other. The JJs in comparator <NUM> can be configured such that each time an SFQ pulse input comes in on logical clock input LCLK, only one of the two JJs in comparator <NUM> will trigger, and input D determines which of the two JJs in comparator <NUM> will trigger. Storage loop <NUM> and comparator <NUM> may also share a JJ, such that one of the JJs in storage loop <NUM> is also one of the JJs in comparator <NUM>.

The logic value of flip-flop <NUM> can be stored, for example, as the superconducting phase of a JJ. For example, the logic value of flip-flop <NUM> can be stored as the phase of a JJ that is shared between storage loop <NUM> and comparator <NUM>. As an example, a <NUM> phase of the JJ can encode a logic "<NUM>" value and a 2π phase of the JJ can encode a logic "<NUM>" value, but other combinations can work equally well.

<FIG> is an example circuit diagram of an efficient RQL phase-mode D flip-flop <NUM> that can correspond to the flip-flop <NUM> shown in <FIG>. Flip-flop <NUM> can include three JJs <NUM>, J2, J3 and two inductors L1, L2. An input signal from data input D triggers data input JJ J3 and stores a superconducting current in a storage loop formed by data input JJ J3, storage inductor L2, and output JJ J2. This storage loop can correspond to storage loop <NUM> in <FIG>. The storage loop is connected, at the bottom of <FIG>, by a low-voltage rail, e.g., a ground node. Owing to the comparatively large size of storage inductor L2, the current stored there will not be enough to trigger output JJ J2 on its own. Thus, an LCLK signal is required to "clock" the D input by triggering output JJ J2 (output JJ J2 having been biased by current in the storage loop) and thus to provide an output signal to output Q.

In some example's comparator JJs J1 and J2 can each be configured to exhibit critical currents between <NUM> microamperes and <NUM> microamperes, e.g., between <NUM> microamperes and <NUM> microamperes. Data input JJ J3 may be configured to exhibit a critical current at a larger current, e.g., between <NUM> microamperes and <NUM> microamperes, e.g., <NUM> microamperes. Storage inductor L2 may be configured to have an inductance value between <NUM> picohenries (pH) and <NUM> pH, e.g., between <NUM> pH and <NUM> pH. Storage inductor L2 and data input JJ J3 can be configured such that the product of the inductance of L2 and critical current of J3 is between <NUM> and <NUM> mApH. Comparator JJs J1 and J2 can be configured to exhibit critical currents similar to each other. Comparator JJs J1 and J2 need not exhibit critical currents at exactly the same currents, but comparator JJs J1 and J2 can be close in critical current size to one another, e.g., within <NUM>% of each other.

The storage loop comprising data input JJ J3, storage inductor L2, and output JJ J2 has three possible states, a ground state where there is no current in the storage loop, a positive state where there is one single flux quantum Φ<NUM> (e.g., Φ<NUM> = <NUM> mA-pH) of current circulating in the clockwise direction, and a negative state where there is one Φ<NUM> of current circulating in the counter-clockwise direction. Storage inductor L2 is sized to be relatively large such that in the positive and negative states, the induced current is insufficient to trigger storage loop JJs J2 or J3 even when combined with any AC bias leaking in from the surrounding JTLs. Input D is used to induce current in this storage loop. Positive pulses on input D, which can be driven nonreturn-to-zero (NRZ), induce clockwise current in the storage loop, and negative pulses on input D induce counter-clockwise current in the storage loop.

Comparator JJs J1 and J2 of flip-flop <NUM> form a comparator that can correspond to comparator <NUM> of <FIG>. Escape JJ J1 can be configured to have a smaller critical current than output JJ J2. The current in the storage loop can be used to adjust the biasing of output JJ J2. The input of logical clock LCLK can be used to trigger the comparator and read out the state of the storage loop to output Q. The logical clock LCLK can be driven with a return-to-zero (RZ) pulse pair.

In the ground state of the storage loop formed by data input JJ J3, storage inductor L2, and output JJ J2, there is no current in the storage loop. In this state, any pulses, positive or negative, arriving from the logical clock input LCLK trigger the escape JJ J1. This destroys the incoming LCLK pulse and leaves the state of both the storage loop and the output Q of flip-flop <NUM> unchanged. As such, any positive-negative pulse pair from LCLK has no effect when the storage loop is in the ground state. Despite the three states of the storage loop, the flip-flop has only two states, corresponding to binary logical values "<NUM>" and "<NUM>", as encoded by the phase of output JJ J2, either <NUM> or 2π.

<FIG> illustrate a sequence showing the writing of a logical "<NUM>" value to the flip-flop <NUM>. <FIG> shows the input D asserted with a positive SFQ pulse <NUM>, causing data input JJ J3 to switch, i.e., from a <NUM> phase to a 2π phase. As shown in <FIG>, this switching puts one Φ<NUM> of current <NUM> into the storage loop in the clockwise direction and also cancels <NUM> the incoming pulse from input D. Current loop <NUM> can be thought of as the result of a phase differential between J3 and J2, J3 having a 2π phase while J2 still has a <NUM> phase. Because of the presence and direction of superconducting current <NUM>, the storage loop is now in the positive state. This positive state of the storage loop preferentially biases output JJ J2 towards switching in the positive direction.

<FIG> illustrate a sequence showing the reading of the stored logical "<NUM>" value from the flip-flop <NUM>. Following from the state shown in <FIG>, a reciprocal pulse pair is input via the LCLK input. When the positive pulse <NUM> arrives, as shown in <FIG>, it puts current through comparator JJs J1 and J2 and clock input inductor L1. Because output JJ J2 has been preferentially biased by the current <NUM> in the storage loop, it will now trigger instead of escape JJ J1. As shown in <FIG>, this will, in turn, drive a positive SFQ pulse in all directions away from output JJ J2 through the node connecting comparator JJs J1 and J2. Thus, in <FIG>, the triggering of output JJ J2 will drive a positive SFQ pulse <NUM> out of the output Q, asserting it. Additionally, it will cancel both the currents through escape JJ J1 and clock input inductor L1, <NUM>, as well as the clockwise current in the storage loop, <NUM>. Thus, the output Q has now been asserted and the storage loop has been returned to the ground state. When the negative pulse of the reciprocal pulse pair is driven into the LCLK input (not shown), the circuit <NUM> is in ground state and the escape JJ J1 triggers, destroying the pulse without affecting the output or state of the storage loop.

The triggering of output JJ J2 shown in <FIG> as the result of the positive logical clock input SFQ pulse <NUM> in <FIG> changes the phase of output JJ J2 from <NUM> to 2π, which phase persists even with a return pulse opposite to output pulse <NUM> that arrives as the result of the triggering of a first JJ in a JTL to which output Q may be connected (not shown). Thus, although current <NUM> may be destroyed, the 2π phase of output JJ J2 encoding the logical "<NUM>" value of flip-flop <NUM> remains.

<FIG> illustrate a sequence showing the writing of a logical "<NUM>" value to the flip-flop <NUM>. <FIG> shows the input D driven with a negative SFQ pulse <NUM>, causing data input JJ J3 to switch, i.e., from a 2π phase back to a <NUM> phase. As shown in <FIG>, this switching puts one Φ<NUM> of current <NUM> into the storage loop in the counter-clockwise direction and also cancels <NUM> the incoming pulse from input D. Current loop <NUM> can be thought of as the result of a phase differential between J2 and J3, J2 having a 2π phase while J3 now has a <NUM> phase. Because of the presence and direction of superconducting current <NUM>, the storage loop is now in the negative state. This preferentially biases output JJ J2 towards switching in the negative direction.

<FIG> illustrate a sequence showing the reading of the stored logical "<NUM>" value from the flip-flop <NUM>. Following from the state shown in <FIG>, a reciprocal pulse pair is input via the LCLK input. When the positive pulse arrives (not shown), escape JJ J1 triggers, destroying the pulse without affecting the output or state of the storage loop. When the negative pulse <NUM> arrives, as shown in <FIG>, it puts current through comparator JJs J1 and J2 and clock input inductor L1. Because output JJ J2 has been preferentially biased by the current <NUM> in the storage loop, it will now trigger instead of escape JJ J1. As shown in <FIG>, this will, in turn, drive a negative SFQ pulse in all directions away from output JJ J2 through the node connecting comparator JJs J1 and J2. Thus, in <FIG>, the triggering of output JJ J2 will drive a negative SFQ pulse <NUM> out of the output Q, de-asserting it. Additionally, it will cancel both the currents through escape JJ J1 and clock input inductor L1, <NUM>, as well as the counter-clockwise current in the storage loop, <NUM>. The flip-flop <NUM> has now returned to the ground state.

The triggering of output JJ J2 shown in <FIG> as the result of the negative logical clock input SFQ pulse <NUM> in <FIG> changes the phase of output JJ J2 from 2π to <NUM>, which phase persists even with a return pulse opposite to output pulse <NUM> that arrives as the result of the triggering of a first JJ in a JTL to which output Q may be connected (not shown). Thus, although current <NUM> may be destroyed, the <NUM> phase of output JJ J2 encoding the logical "<NUM>" value of flip-flop <NUM> remains.

As noted previously with respect to the example of <FIG>, each time an SFQ pulse input comes in on logical clock input LCLK, one and only one of the comparators JJs J1 or J2 will trigger, and input D determines which of comparator JJs J1 or J2 will trigger. If input D has not put any current into the storage loop, or has effectively destroyed any current from the storage loop by supplying an opposite pulse, any inputs on LCLK will trigger escape JJ J1 alone, effectively rejecting such LCLK inputs, and no output is created on Q. If input D has put a current into the storage loop, thus changing the bias condition of output JJ J2, and because output JJ J2 will see current stored in that loop but escape JJ J1 does not, output JJ J2 will preferentially trigger and generate output on Q. In arrangement <NUM>, when comparator JJs J1 and J2 are close to the same size, and when there is no current in the storage loop, escape JJ J1 will trigger first, because it sees all of the current from input LCLK, whereas output JJ J2 sees only most of such current, since some of such current will leak out through the storage loop and output Q given that each branch emanating from the node connecting comparator JJs J1 and J2 together form an inductive network in parallel.

Flip-flop <NUM> is a "phase-mode" flip-flop inasmuch as the logic value of flip-flop <NUM> is stored as the superconducting phase (either <NUM> or 2π) of output JJ J2, i.e., the JJ that is shared between the storage loop of flip-flop <NUM> and the comparator of flip-flop <NUM>. Flip-flop <NUM> is efficient in terms of its use of devices, requiring only three JJs and two inductors, apart from any devices used for race condition avoidance phasing of input signals.

Because there may exist setup and hold requirements on the input D relative to the input LCLK, applying a <NUM>° phase offset between the inputs can improve performance of the flip-flop <NUM> in terms of timing. Here "phasing" and "phase offset" refer to the timing of the supplied AC waveforms, not the superconducting phases (<NUM> or 2π) of individual JJs. <FIG> illustrates an example flip-flop circuit <NUM> that corresponds to circuit <NUM> but with input delay buffer <NUM> configured to delay a logical clock signal relative to the input timing <NUM> of input D. The indicated delay buffers <NUM>, <NUM>, <NUM> may be, for example, Josephson transmission lines (JTLs). The state of the internal loop formed by data input JJ J3, storage inductor L2, and output JJ J2-whether ground, positive, or negative-at the time the LCLK pulses arrive determines what state will be read out to output Q. Thus, any new input must arrive prior to the LCLK pulses. Particularly, positive SFQ pulses at D must arrive prior to positive SFQ pulses at LCLK and negative SFQ pulses at D must arrive prior to negative SFQ pulses at LCLK. Using a delay buffer (e.g., JTLs) to drive the input D that has a phase assignment <NUM>° ahead of the one at the LCLK input and Q output, as shown in <FIG>, can help enforce setup requirements. Similar phasing schemes, not shown and too numerous to list, can likewise assist in meeting the setup and hold requirements and thus to avoid undesirable race conditions where an LCLK signal arrives before an intended D signal resulting in the capturing and output of wrong data. As examples, the buffers (e.g., JTLs) could be respectively configured such that input D has a phase assignment <NUM>° or <NUM>° ahead of the LCLK input.

A notable consequence of the above-described setup and hold requirements is that it can be possible to assert the clock with a consistent waveform at input D that will affect no value change at the output regardless of whether the current output value is a logical "<NUM>" or a logical "<NUM>. " To accomplish this, the last arriving input pulse at D prior to the positive pulse of input LCLK must have been a negative pulse and the last arriving input pulse at D prior to the negative pulse of LCLK must have been a positive pulse.

<FIG> is an example timing diagram plotted in terms of superconducting phase, derived from analog simulation, demonstrating the functioning of an RQL phase-mode flip-flop of the previous examples. Except those at <NUM> and <NUM>, LCLK signals consist of pulse pairs comprising a positive SFQ pulse followed very close in time by a negative SFQ pulse, e.g., separated by roughly <NUM>°. Logical value changes in D signals can be spaced arbitrarily further apart in time than this. Tiny transients that may be noted in Q signals not effecting a logical value change in Q signals and corresponding to pulses on LCLK may result, for example, from the triggering of escape JJ J1 in circuit <NUM> as shown in <FIG>. The latching behavior of the flip-flop is exemplified as shown.

LCLK pulse pair <NUM> made while input D is logical "<NUM>" <NUM> before, during, and after the LCLK pulse pair <NUM> results in no change in output Q from its logical "<NUM>" value <NUM>. However, when LCLK pulse pair <NUM> is made while input D is logical "<NUM>" <NUM>, and specifically on the positive pulse of the pulse pair <NUM>, Q is asserted to a logical "<NUM>" <NUM>, which is not changed by the transition of D to a logical "<NUM>" <NUM> in absence of a logical clock pulse pair or by LCLK pulse pair <NUM> once D has returned to its logical "<NUM>" value <NUM>. However, on the reciprocal (negative) pulse of LCLK pulse pair <NUM>, when D is again logical "<NUM>" <NUM>, Q is de-asserted to a logical "<NUM>" <NUM>, which is not changed by LCLK pulse pair <NUM> made while D is still logical "<NUM>" <NUM> or by the transition of D to a logical "<NUM>" <NUM> in absence of a logical clock pulse pair.

LCLK pulse pair <NUM>, made very shortly in time after the transition of <NUM>) from logical "<NUM>" to logical "<NUM>" 63η. , results in output Q being asserted to logical "<NUM>" because the setup time requirement was nonetheless met. LCK pulse pair <NUM> has the positive pulse and negative pulse being more distant in time from each other than the previous pulse pairs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. Even though the positive pulse of the pulse pair <NUM> arrives while D is briefly logical "<NUM>" <NUM>, i.e., while a "<NUM>" value has been briefly written to the flip-flop, because only a negative pulse on LCLK can de-assert output Q to read out a "<NUM>" input on D to Q, and because D returns to logical "<NUM>" <NUM> prior to the negative pulse of pulse pair <NUM>, the "<NUM>" output <NUM> at Q remains unchanged. From this result it can also be concluded that the hold time requirement for the logical "<NUM>" <NUM> on D was not met, i.e., D's "<NUM>" value <NUM> was not held long enough for the negative pulse of LCLK pulse pair <NUM> to translate the input to an output. The hold time is met, however, when D next goes logical "<NUM>" <NUM>, and the negative pulse of LCLK pulse pair <NUM> sends output Q to a logical "<NUM>" once again <NUM>.

Like LCLK pulse pair <NUM>, LCLK pulse pair <NUM> is also protracted in time. That the positive pulse of pulse pair <NUM>, while D is still logical "<NUM>," has no effect on the logical "<NUM>" value <NUM> of output Q may be unremarkable. However, Q is still unaffected from its logical "<NUM>" value <NUM> when input D again rises to logical "<NUM>" <NUM> during the pendency of LCLK pulse pair <NUM>. This is because a falling edge of LCLK, i.e., the negative pulse of an LCLK pulse pair, can only de-assert Q to logical "<NUM>," and cannot serve as the capture time for a logical "<NUM>" signal. It can be concluded that the setup time requirement for the logical "<NUM>" on D was not met, i.e., the signal sending input D positive <NUM> arrived after the positive pulse of LCLK pulse pair <NUM> and was not sent to the output Q.

<FIG> illustrates a method <NUM> of writing and reading a logical "<NUM>" value to and from an RQL flip-flop <NUM>. A positive SFQ pulse provided <NUM> to a data input of an RQL, flip-flop, such as to data input D of flip-flop <NUM> in <FIG> or flip-flop <NUM> in <FIG>, sets <NUM> a storage loop, such as storage loop <NUM> illustrated in <FIG>, into a positive state, e.g., by putting one single flux quantum of current into the storage loop in a first direction. A reciprocal SFQ pulse pair provided <NUM> to a clock input of the RQL flip-flop, such as clock input LCLK of flip-flop <NUM> in <FIG> or flip-flop <NUM> in <FIG>, induces the transmitting <NUM> of an output signal corresponding to a logical "<NUM>" value out of an output of the RQL flip-flop, asserting it, e.g., by driving a positive SFQ pulse out of the output of the RQL flip-flop, and returns <NUM> the storage loop to the ground state.

<FIG> illustrates a method <NUM> of writing and reading a logical "<NUM>" value to and from an RQL flip-flop. A negative SFQ pulse provided <NUM> to a data input of an RQL flip-flop, such as to data input D of flip-flop <NUM> in <FIG> or flip-flop <NUM> in <FIG>, sets <NUM> a storage loop, such as storage loop <NUM> illustrated in <FIG>, into a negative state, e.g., by putting one single flux quantum of current into the storage loop in a second direction that is counter to the aforementioned first direction. A reciprocal SFQ pulse pair provided <NUM> to a clock input of the RQL flip-flop, such as clock input LCLK of flip-flop <NUM> in <FIG> or flip-flop <NUM> in <FIG>, induces the transmitting <NUM> of an output signal corresponding to a logical "<NUM>" value out of an output of the RQL flip-flop, de-asserting it, e.g., by driving a negative SFQ pulse out of the output, and returns <NUM> the storage loop to the ground state.

The methods shown in <FIG> can be generalized to a single method of writing and reading a logical value to and from an RQL flip-flop. As shown in <FIG>, such a method <NUM> includes providing <NUM> a data input SFQ pulse that is one of either positive or negative to a data input of an RQL flip-flop; setting <NUM> a storage loop in the RQL flip-flop from a ground state to a state that is the one of either positive or negative; providing <NUM> a reciprocal SFQ pulse pair to a clock input of the RQL flip-flop; transmitting <NUM> an output signal corresponding to a logical "<NUM>" or logical "<NUM>" value out of an output of the RQL flip-flop, e.g., by driving an output SFQ pulse that is the one of either positive or negative out of an output of the RQL flip-flop; and returning <NUM> the storage loop to a ground state. If the "one of either positive or negative" for each action is positive, a logical "<NUM>" value can be said to have been written and read, whereas if the "one of either positive or negative" is negative, a logical "<NUM>" value can be said to have been written and read. Because the designation of "<NUM>" and "<NUM>" as assigned to positive or negative states may be arbitrary in the context of the logic of the larger system in which the flip-flop is implemented, the logical values may be inversed in some examples, e.g., negative input and output pulses might encode logical "<NUM>" whereas positive input and output pulses might encode logical "<NUM>. " The output can be based on the data input and the logical clock input.

Claim 1:
A reciprocal quantum logic, RQL, phase-mode flip-flop (<NUM>; <NUM>; <NUM>) comprising:
a storage loop (<NUM>) configured to receive a data input signal on a data input line (D) as positive or negative single flux quantum, SFQ, pulse (<NUM>, <NUM>) and to store the data input signal in the storage loop, the storage loop being configured to contain one of -Φ<NUM>, zero, or +Φ<NUM> of current (<NUM>, <NUM>);
a comparator (<NUM>) configured to receive a logical clock input signal on a logical clock input line (LCLK) and to compare the received logical clock input signal with the stored data input signal; and
an output signal line (Q) configured to transmit an output signal corresponding to a logical "<NUM>" or logical "<NUM>" value based on the comparison.