Patent Description:
Conventionally, glass plates having a chamfered outer periphery portion are known (see Patent Literature <NUM>). The glass plate described in Patent Literature <NUM> is used as a support plate for supporting a workpiece substrate in fan-out wafer-level packaging.

According to Patent Literature <NUM>, since a notch-shaped or orientation flat-shaped alignment portion of the glass plate is chamfered, damage on the glass plate originating from a positioning member such as positioning pin can be effectively avoided when brought into contact with the positioning member.

However, damageability of plate-like objects including glass plates and semiconductor substrates is different depending on characteristics of material such as cleavage planes in a crystal, and the shape of the chamfered portion which can effectively suppress damage is thus also different depending on the material of the plate-shaped object. Therefore, even if the shape of the chamfered portion of the glass plate described in Patent Literature <NUM> is applied to a plate-shaped object formed of another material, it is not necessarily possible to effectively suppress damages.

It is an object of the invention to provide a semiconductor substrate which includes a gallium oxide-based semiconductor single crystal and is configured to effectively suppress occurrence of damage, as well as a method for manufacturing the semiconductor substrate.

A gallium oxide-based single crystal substrate is e.g. known from document <CIT>. The known semiconductor substrate comprises a chamfered portion at its outer periphery.

According to the invention, a semiconductor substrate and a method for manufacturing a semiconductor substrate are defined in the independent claims. Embodiments of the invention are subject to the dependent claims.

<FIG> is a perspective view showing a semiconductor substrate <NUM> in the embodiment of the invention. The semiconductor substrate <NUM> is a semiconductor substrate that is formed of a gallium oxide-based semiconductor single crystal and has a chamfered (beveled) portion <NUM> at an outer periphery portion.

Gallium oxide-based semiconductor here means β-Ga<NUM>O<NUM>, or means β-Ga<NUM>O<NUM> containing a substitutional impurity such as Al, In, or a dopant such a Sn, Si.

The chamfered portion <NUM> is provided to prevent damage on the semiconductor substrate <NUM> during polishing or conveyance in the manufacturing process, or during handling such as conveyance and alignment, etc. If the chamfered portion <NUM> is not provided and edges of the semiconductor substrate <NUM> (boundaries between principal surfaces <NUM>, <NUM> and a side surface) are square edges, e.g., the edges are damaged during polishing of the principal surfaces <NUM>, <NUM>, and also, broken pieces scratch or contaminate the principal surfaces <NUM>, <NUM>.

The plane orientations of the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are not specifically limited, but damage due to cleavage is particularly likely to occur when the principal surfaces are (<NUM>) planes or (<NUM>) planes. Therefore, an effect of suppressing damage in the invention is thus particularly important.

<FIG> is a schematic diagram illustrating a crystal structure of β-Ga<NUM>O<NUM> that is a typical example of a gallium oxide-based semiconductor constituting the semiconductor substrate <NUM>. The (<NUM>) plane and the (<NUM>) plane are cleavage planes of the gallium oxide-based semiconductor and cleavage is likely to occur along these planes. In more particular, it is most likely to cleave along the (<NUM>) plane and it is next most likely to cleave along the (<NUM>) plane.

In addition, when polishing the semiconductor substrate <NUM>, polishability is different since a surface having a plane orientation close to the cleavage plane is relatively soft and a surface having a plane orientation far from the cleavage plane is relatively hard. The gallium oxide-based semiconductor is monoclinic. Therefore, when the semiconductor substrate <NUM> is a substrate including a curved line in an outer contour of its planar shape, such as a circular substrate, the plane orientation of the polished portion continuously changes during chamfering of the outer periphery portion and it is highly difficult to process.

When the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are the (<NUM>) planes, cleavage is likely to occur along the (<NUM>) plane intersecting the principal surfaces <NUM>, <NUM> at <NUM>°, and cleavage can also occur along the (<NUM>) plane parallel to the principal surfaces <NUM>, <NUM>. Cleavage along the (<NUM>) plane hardly occurs during polishing of the principal surfaces <NUM>, <NUM> but can occur during processing of the substrate end face, such as during chamfering.

When the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are the (<NUM>) planes, cleavage is likely to occur along the (<NUM>) plane parallel to the principal surfaces <NUM>, <NUM> and cleavage can occur along the (<NUM>) plane intersecting the principal surfaces <NUM>, <NUM> at <NUM>°. Cleavage along the (<NUM>) plane occurs during processing of the substrate end face but is also likely to occur during polishing of the principal surfaces <NUM>, <NUM>.

When the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are (-<NUM>) planes, cleavage can occur along the (<NUM>) plane intersecting the principal surfaces <NUM>, <NUM> at <NUM>° but hardly occurs along the (<NUM>) plane intersecting the principal surfaces at <NUM>°.

<FIG> are partially enlarged vertical cross-sectional views showing the semiconductor substrate <NUM>. <FIG> show vertical cross-sectional shapes around the chamfered portion <NUM> of the semiconductor substrate <NUM>.

The chamfered portion <NUM> of the semiconductor substrate <NUM> has an inclined surface <NUM> on the principal surface <NUM> side of the semiconductor substrate <NUM>, an inclined surface <NUM> on the principal surface <NUM> side opposite to the principal surface <NUM>, and an end face <NUM> located between the inclined surface <NUM> and the inclined surface <NUM> at a leading end of the chamfered portion <NUM>.

The inclined surface <NUM> is an annularly continuous surface that is located on the outer side of the principal surface <NUM> and is linear at an edge in the vertical cross section of the semiconductor substrate <NUM>. The inclined surface <NUM> is an annularly continuous surface that is located on the outer side of the principal surface <NUM> and is linear at an edge in the vertical cross section of the semiconductor substrate <NUM>. The end face <NUM> is an annularly continuous surface that can be regarded as a side surface of the semiconductor substrate <NUM>.

When the semiconductor substrate <NUM> is, e.g., a circular substrate as shown in <FIG>, the inclined surface <NUM>, the inclined surface <NUM> and the end face <NUM> are respectively annularly continuous.

A width bt of the end face <NUM> in a thickness direction of the semiconductor substrate <NUM> is within the range of not less than <NUM>% and not more than <NUM>% of a thickness t of the semiconductor substrate <NUM>. When the width bt is not less than <NUM>% of the thickness t, it is possible to effectively suppress damage on the leading end of the chamfered portion <NUM> including the end face <NUM>, particularly, damage due to cleavage, during a step of forming the chamfered portion <NUM> (Step S5 in a manufacturing process described later), during steps thereafter (Steps S6, S7), and even during handling such as conveyance or alignment of the semiconductor substrate <NUM>. Meanwhile, when the width bt is not more than <NUM>% of the thickness t, it is possible to effectively suppress the above-mentioned damage on the edge of the semiconductor substrate <NUM>, particularly scratches caused by broken pieces during polishing of the principal surfaces <NUM>, <NUM>.

In case that the width bt of the end face <NUM> in the thickness direction of the semiconductor substrate <NUM> is within the range of not less than <NUM>% and not more than <NUM>% of the thickness t of the semiconductor substrate <NUM>, it is possible to effectively suppress damage on the semiconductor substrate <NUM> such as the above-described damage on the leading end of the chamfered portion <NUM> and scratches caused by broken pieces during polishing even when the plane orientations of the principal surfaces <NUM>, <NUM> are (<NUM>) or (<NUM>). In other words, regardless of the plane orientations of the principal surfaces <NUM>, <NUM>, it is possible to effectively suppress damage on the semiconductor substrate <NUM>.

In addition, to suppress damage on the semiconductor substrate <NUM> more effectively, the width bt is preferably within the range of not less than <NUM>% and not more than <NUM>% of the thickness t, more preferably, within the range of not less than <NUM>% and not more than <NUM>%. A distance bs1 from a boundary between the end face <NUM> and the inclined surface <NUM> to the outermost point of the end face <NUM> in an in-plane direction of the semiconductor substrate <NUM> (a direction parallel to the principal surfaces <NUM>, <NUM>) is typically equal to, but may be different from, a distance bs2 from a boundary between the end face <NUM> and the inclined surface <NUM> to the outermost point of the end face <NUM> in the in-plane direction of the semiconductor substrate <NUM>.

Widths as1 and as2 of the inclined surface <NUM> and the inclined surface <NUM> in the in-plane direction of the semiconductor substrate <NUM> (a direction parallel to the principal surfaces <NUM>, <NUM>) are preferably within the range of not less than <NUM> and not more than <NUM>. When the widths as1, as2 are not less than <NUM>, it is possible to effectively suppress the above-described damage on the edge of the semiconductor substrate <NUM>, particularly scratches caused by broken pieces during polishing of the principal surfaces <NUM>, <NUM>. Meanwhile, when the width as1, as2 are not more than <NUM>, a chamfering amount is reduced, hence, an effect of improving chamfering efficiency and an effect of reducing the manufacturing cost of the semiconductor substrate <NUM> by suppressing wear of the grinding wheel used for chamfering, etc., are obtained.

To obtain such effects more reliably, the widths as1, as2 are preferably within the range of not less than <NUM> and not more than <NUM>, more preferably, within the range of not less than <NUM> and not more than <NUM>. The width as1 and a width at1 of the inclined surface <NUM> (the width at1 along the thickness direction of the semiconductor substrate <NUM>) are typically respectively equal to, but may be different from, the width as2 and a width at2 of the inclined surface <NUM> (the width at2 along the thickness direction of the semiconductor substrate <NUM>.

The end face <NUM> may be curved along the thickness direction of the semiconductor substrate <NUM> so as to bulge outward as shown in <FIG>, or may be flat along the thickness direction of the semiconductor substrate <NUM> as shown in <FIG>.

The end face <NUM> when curved along the thickness direction of the semiconductor substrate <NUM> as shown in <FIG> has a smaller contact area with the grinding wheel during processing and stress is less likely to concentrate, hence, damage on the leading end of the chamfered portion <NUM> including the end face <NUM> can be suppressed more effectively. The end face <NUM> may be flat along the thickness direction of the semiconductor substrate <NUM> when damage during processing is suppressed sufficiently. In addition, when the leading end of the chamfered portion <NUM> is too sharp, cleavage is likely to occur at the leading end. Therefore, a curvature radius of the end face <NUM> in the vertical cross section of the semiconductor substrate <NUM> is preferably not less than <NUM>.

The thickness of the semiconductor substrate <NUM> is preferably less than <NUM>, more preferably, less than <NUM>. It is because the semiconductor substrate <NUM> formed of a gallium oxide-based semiconductor has a lower thermal conductivity than substrates formed of other semiconductors and is thus required to be thin to ensure heat dissipation of device. In addition, to suppress cracks during handling such as conveyance or work at the time of using the semiconductor substrate <NUM> (epitaxial growth, device manufacturing, etc.,), the thickness of the semiconductor substrate <NUM> is preferably not less than <NUM>, more preferably, not less than <NUM>. Even when the chamfered portion <NUM> has a shape capable of suppressing damage on the semiconductor substrate <NUM> as described above, the semiconductor substrate <NUM> when too thin may crack due to stress generated during conveyance or handling.

<FIG> is a top view showing the semiconductor substrate <NUM> that has an orientation flat. The semiconductor substrate <NUM> may have an orientation flat for alignment, as shown in <FIG>. When the orientation flat is provided, an orientation flat portion is also chamfered in the same manner as for the outer periphery portion not having the orientation flat to form a chamfered portion having the same vertical cross-sectional shape.

In the example shown in <FIG>, the semiconductor substrate <NUM> has (<NUM>) planes on the principal surfaces <NUM>, <NUM> and has an orientation flat 13a along a <<NUM>> direction that is a direction of a line of intersection between the principal surface <NUM> and a (<NUM>) plane as a cleavage plane. Since a portion with a small (<NUM>) plane area in the vicinity of the outer periphery portion of the substrate is removed by providing the orientation flat 13a along the <<NUM>> direction, it is possible to suppress cleavage along the (<NUM>) plane on the orientation flat 13a side of the semiconductor substrate <NUM>.

Additionally, an orientation flat 13b along the <<NUM>> direction may be provided on the semiconductor substrate <NUM> on the opposite side to the orientation flat 13a. It is thereby possible to suppress cleavage along the (<NUM>) plane also on the orientation flat 13b side of the semiconductor substrate <NUM>.

Meanwhile, since it is not possible to distinguish front and back of the semiconductor substrate <NUM> only by the orientation flat 13a or only by the orientation flats 13a, 13b, an orientation flat 13c for distinguishing front and back may be provided along a <<NUM>> direction, etc., that is orthogonal to the <<NUM>> direction.

The planar shape of the semiconductor substrate <NUM> is typically a circular shape or a circle with an orientation flat, but may be another shape such as a polygonal shape. Also in such a case, the outer periphery portion of the substrate is chamfered in the same manner as when having a circular shape to form a chamfered portion having the same vertical cross-sectional shape.

<FIG> is a flowchart showing an example of a process of manufacturing the semiconductor substrate <NUM>. <FIG> are schematic diagrams illustrating states of a crystalline substance as a material of the semiconductor substrate <NUM> in the process of manufacturing the semiconductor substrate <NUM>. Next, a process flow of manufacturing the semiconductor substrate <NUM> will be described along with the flowchart in <FIG>.

Firstly, a bulk single crystal <NUM> as shown in <FIG> is prepared (Step S1). The bulk single crystal <NUM> is a gallium oxide-based semiconductor single crystal block that is cut out of a single crystal ingot grown by a single crystal growth method such as the EFG (Edge Defined Film Fed Growth) method, the VB (Vertical Bridgman) method, the FZ (Floating Zone) method or the CZ (Czochralski) method.

The square plate-shaped bulk single crystal <NUM> shown in <FIG> is an example of the bulk single crystal <NUM> that is cut out of a plate-shaped ingot grown by the EFG method. The bulk single crystal <NUM> cut out of a circular column-shaped ingot grown by the VB method, the FZ method or the CZ method, etc., has a circular plate shape.

Next, plural single crystal plates <NUM> shown in <FIG> are obtained by slicing the bulk single crystal <NUM> (Step S2). The bulk single crystal <NUM> is sliced using, e.g., a multi-wire saw. It is possible to use a fixed abrasive wire saw or a free abrasive wire saw, and a slicing speed is preferably about <NUM> to <NUM>/min.

Next, a cutout step is performed on the plural single crystal plates <NUM> to cut out the plural semiconductor substrates <NUM> shown in <FIG> (Step S3). The cutout step of the single crystal plates <NUM> is performed by, e.g., wire electrical discharge machining, grinding the outer periphery, ultrasonic machining, or coring using a core drill, etc. In this regard, the order of the slicing step in Step S2 and the cutout step in Step S3 may be reversed.

When orientation flats are formed on the semiconductor substrates <NUM>, for example, the semiconductor substrate <NUM> having a shape including an orientation flat may be cut out by wire electrical discharge machining, grinding the outer periphery, or ultrasonic machining, etc., in the cutout step in Step S3, or the semiconductor substrate <NUM> cut out into a circular shape by the cutout step may be partially cut off by a slicing machine.

Next, the semiconductor substrates <NUM> are heat-treated to relieve processing strain and thereby reduce the amount of warpage (Step S4). For example, heat treatment during heating up is performed in an oxygen atmosphere, and heat treatment while holding temperature after heating up is performed in an inert atmosphere such as nitrogen atmosphere, argon atmosphere or helium atmosphere. The holding temperature is preferably <NUM> to <NUM>.

Next, the outer periphery portion of each semiconductor substrate <NUM> is chamfered to form the chamfered portion <NUM> (Step S5). Chamfering is performed using, e.g., an outer periphery machining device provided with a circular plate-shaped grinding wheel. The size of the semiconductor substrate <NUM> may be adjusted by grinding the outer periphery before chamfering.

When forming the chamfered portion <NUM>, a step of forming the inclined surfaces <NUM>, <NUM> and a step of forming the end face <NUM> are preferably separately performed in such a manner that the end face <NUM> is formed after forming the inclined surfaces <NUM>, <NUM>. As a result, it is possible to suppress damage due to cleavage during the step of forming the end face <NUM>.

<FIG> is a perspective view showing a grinding wheel <NUM> that can be used to chamfer the semiconductor substrate <NUM>. The circular plate-shaped grinding wheel <NUM> has plural grooves <NUM> along the side surface thereof, and a shaft <NUM> is attached thereto so as to be located on the center axis thereof.

<FIG> is a partially enlarged vertical cross-sectional view showing the grinding wheel <NUM>. <FIG> shows a vertical cross-sectional shape of the side surface of the grinding wheel <NUM> on which the grooves <NUM> are provided. When chamfering the semiconductor substrate <NUM> using the grinding wheel <NUM>, the semiconductor substrate <NUM> is brought close to the grinding wheel <NUM> from the side while rotating the grinding wheel <NUM> about the rotational axis of the shaft <NUM>, so that the outer periphery portion of the semiconductor substrate <NUM> proceeds into the grooves <NUM> and is ground by inner surfaces of the grooves <NUM>.

When forming the inclined surfaces <NUM>, <NUM>, it is preferable to use a relatively hard grinding wheel as the grinding wheel <NUM> to suppress changes in the shape of the grooves <NUM> due to wear of the grinding wheel <NUM>. On the other hand, when forming the end face <NUM>, a grinding wheel softer than the grinding wheel used to form the inclined surfaces <NUM>, <NUM> is preferably used as the grinding wheel <NUM> since damage due to cleave along the (<NUM>) plane or the (<NUM>) plane is likely to occur when a hard grinding wheel is used. In this case, a metal bonded grinding wheel (e.g., grit #<NUM>) can be used to form the inclined surfaces <NUM>, <NUM>, and a resin bonded grinding wheel (e.g., grit #<NUM>) can be used to form the end face <NUM>.

When the semiconductor substrate <NUM> has a circular shape, the entire region of the outer periphery portion is polished by the grinding wheel <NUM> while rotating the semiconductor substrate <NUM>. When an orientation flat is formed on the semiconductor substrate <NUM>, the orientation flat portion is chamfered by laterally sliding the semiconductor substrate <NUM> relative to the grinding wheel <NUM> without rotating the semiconductor substrate <NUM>.

Next, the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are polished (Step S6). The polishing step of the principal surfaces <NUM>, <NUM> is performed by, e.g., lapping using a single-sided polishing machine or a double-sided polishing machine, and then polishing. Dry etching, chemical etching or thermal etching, etc., may be performed in addition to mechanical polishing such as lapping and polishing. An amount of polishing each of the principal surfaces <NUM>, <NUM> in this polishing step is about <NUM> to <NUM> in the thickness direction of the semiconductor substrate <NUM>.

In a specific example of the polishing step in Step S6, firstly, the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are ground or lapped and polished using a diamond grinding wheel or using a polishing platen and a diamond-based slurry. The grit of the diamond grinding wheel is preferably about #<NUM> to <NUM> (specified by JIS B <NUM>). The polishing platen is preferably formed of a metal-based, glass-based, or resin-based material. The grain size of diamond-based abrasive grains contained in the diamond-based slurry is preferably about <NUM> to <NUM>. Next, the principal surfaces <NUM>, <NUM> of the semiconductor substrate <NUM> are polished using a polishing cloth and a CMP (Chemical Mechanical Polishing) slurry until atomic level flatness (e.g., an average roughness Ra of <NUM> to <NUM>) is obtained. The polishing cloth is preferably formed of nylon, cotton fibers or urethane, etc. It is preferable to use colloidal silica as abrasive grains in the slurry.

After that, the semiconductor substrate <NUM> is cleaned and dried (Step S7). In particular, e.g., ultrasonic cleaning or scrub cleaning using an acid-based or alkaline-based detergent, <NUM> minutes of running water cleaning, <NUM> minutes of sulfuric acid-water cleaning, and <NUM> minutes of running water cleaning are subsequently performed. Next, the drying is performed by a method such as spin drying, vacuum drying, Marangoni drying, hot air drying or lift frying, etc..

The semiconductor substrate <NUM> after the polishing step in Step S6 satisfies the condition that the width bt of the end face <NUM> in the thickness direction of the semiconductor substrate <NUM> is within the range of not less than <NUM>% and not more than <NUM>% of the thickness t of the semiconductor substrate <NUM>. Thus, damage on the semiconductor substrate <NUM> in Steps S5 to S7 can be suppressed.

In the embodiment described above, by forming the chamfered portion <NUM> having a shape that satisfies the conditions described above, it is possible to effectively suppress occurrence of damage during the manufacturing process or handling of the semiconductor substrate <NUM> formed of a gallium oxide-based single crystal.

Ten types of the semiconductor substrates <NUM> with the chamfered portions <NUM> having different shapes (samples A to J) were made, and it was examined whether or not damage occurred on each sample during the step of forming the chamfered portion <NUM> and during the step of polishing the principal surfaces <NUM>, <NUM>. The samples A to J, each consisting of a <NUM> inch-diameter (<NUM>,<NUM>) sample and a <NUM> inch-diameter (<NUM>,<NUM>) sample, were made and evaluated.

Each of the samples A to J is a substrate that is formed of β-Ga<NUM>O<NUM>, has the (<NUM>)-oriented principal surfaces <NUM>, <NUM>, and is provided with the orientation flats 13a to 13c. In addition, each of the samples A to J is symmetric in the thickness direction and is formed such that the width as1 and the width as2 are equal (representatively referred to as the "width as"), the width at1 and the width at2 are equal (representatively referred to as the "width at"), and the distance bs1 and the distance bs2 are equal (representatively referred to as the "distance bs").

In addition, when forming each of the samples A to J, the inclined surfaces <NUM>, <NUM> were formed by polishing with a # <NUM> metal bonded grinding wheel and the end face <NUM> was formed by polishing with a # <NUM> resin bonded grinding wheel.

<FIG> are vertical cross-sectional views showing the chamfered portion <NUM> and therearound of the sample A respectively before and after polishing the principal surfaces <NUM>, <NUM> in Step S6. <FIG> are vertical cross-sectional views showing the chamfered portion <NUM> and therearound of the sample B respectively before and after polishing the principal surfaces <NUM>, <NUM> in Step S6.

<FIG> are vertical cross-sectional views respectively showing the chamfered portions <NUM> and therearound of the samples C and D after polishing the principal surfaces. The samples C and D both have the end face <NUM> curved along the thickness direction of the semiconductor substrate <NUM>, and have the same thickness t of <NUM> and the same inclination angle (at/as) at the inclined surfaces <NUM>, <NUM>, but the distance bt is smaller in the sample D. That is, the chamfered portion <NUM> of the sample D has a shape obtained by stretching the leading end of the chamfered portion <NUM> of the sample C so as to be sharper.

<FIG> are vertical cross-sectional views respectively showing the chamfered portions <NUM> and therearound of the samples E and F after polishing the principal surfaces. The samples E and F both have the end face <NUM> curved along the thickness direction of the semiconductor substrate <NUM>, and have the same thickness t of <NUM> and the same inclination angle (at/as) at the inclined surfaces <NUM>, <NUM>, but the distance bt is smaller in the sample F. That is, the chamfered portion <NUM> of the sample F has a shape obtained by stretching the leading end of the chamfered portion <NUM> of the sample E so as to be sharper.

<FIG> are vertical cross-sectional views respectively showing the chamfered portions <NUM> and therearound of the samples G and H after polishing the principal surfaces. The samples G and H both have the end face <NUM> flat along the thickness direction, have the same thickness t of <NUM> and both have the relatively small inclined surfaces <NUM>, <NUM>, but the inclined surfaces <NUM>, <NUM> are smaller in the sample H.

<FIG> are vertical cross-sectional views respectively showing the chamfered portions <NUM> and therearound of the samples I and J after polishing the principal surfaces. The samples I and J both have the end face <NUM> flat along the thickness direction, have the same thickness t of <NUM> and both have the relatively small inclined surfaces <NUM>, <NUM>, but the inclined surfaces <NUM>, <NUM> are smaller in the sample J.

The curvature radius of the end face <NUM> was <NUM> to <NUM> in each of the samples A to F in which the end face <NUM> was curved along the thickness direction of the semiconductor substrate <NUM>.

Table <NUM> below shows dimensions of the samples A to J and also shows whether or not damage occurred. In Table <NUM>, "Damage (chamfering)" indicates whether or not damage (cleavage crack, chip or scratches) occurred on the inclined surfaces <NUM>, <NUM> or the end face <NUM> during the step of forming the chamfered portion <NUM> in Step S5. "Damage (principal surface polishing)" indicates whether or not damage (polishing scratches) occurred on the principal surfaces <NUM>, <NUM> during the step of polishing the principal surfaces <NUM>, <NUM> in Step S6. Then, "Sample A (before polishing)" and "Sample B (before polishing)" means respectively the sample A and the sample B before polishing the principal surfaces <NUM>, <NUM> in Step S6. Regarding each of the samples A to J, the result (whether or not damage occurred) from the <NUM> inch-diameter (<NUM>,<NUM>) sample and the <NUM> inch-diameter (<NUM>,<NUM>) sample was the same.

As shown in Table <NUM>, in the samples D and F, damage was observed on the chamfered portion <NUM> immediately after chamfering. It is considered that cleavage crack occurred since the width bt was less than <NUM>% of the thickness t and the leading end of the chamfered portion <NUM> was sharp.

Also as shown in Table <NUM>, in the samples H and J, damage was observed on the polished principal surface <NUM>, <NUM>. It is considered that damage occurred in the vicinity of the edges of the polished principal surface <NUM>, <NUM> and polishing scratches were caused by broken pieces since the width bt was more than <NUM>% of the thickness t and the inclined surfaces <NUM>, <NUM> were too small.

On the other hand, as shown in Table <NUM>, in the samples A to C, E, G and I in which the width bt was within the range of not less than <NUM>% and not more than <NUM>% of the thickness t, damage was not observed on the chamfered portion <NUM> and the principal surface <NUM>, <NUM>.

Although the embodiment and Example of the invention have been described, the invention is not limited to the embodiment and Example, and the various kinds of modifications can be implemented without departing from the gist of the invention.

Claim 1:
A semiconductor substrate (<NUM>), comprising:
a gallium oxide-based semiconductor single crystal; and
a chamfered portion (<NUM>) at an outer periphery portion;
wherein the chamfered portion (<NUM>) comprises a first inclined surface (<NUM>) located on the outer side of a first principal surface (<NUM>) of the semiconductor substrate (<NUM>) and being linear at an edge in a vertical cross section of the semiconductor substrate (<NUM>), a second inclined surface (<NUM>) located on the outer side of a second principal surface (<NUM>) on the opposite side to the first principal surface (<NUM>) of the semiconductor substrate (<NUM>) and being linear at an edge in the vertical cross section of the semiconductor substrate (<NUM>), and an end face (<NUM>) located between the first inclined surface (<NUM>) and the second inclined surface (<NUM>) at a leading end of the chamfered portion (<NUM>), and
wherein a width of the end face (<NUM>) in a thickness direction of the semiconductor substrate (<NUM>) is within the range of not less than <NUM>% and not more than <NUM>% of a thickness of the semiconductor substrate (<NUM>).