Patent Description:
The disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof.

In the fields of computers, communications, etc., it is generally necessary to use semiconductor structures having different functions. The semiconductor structure generally includes an anti-fuse device structure and a core device structure. When not activated, the anti-fuse device structure does not conduct electricity. When activated (subjected to breakdown, metal diffusion, or transformation of amorphous silicon into polycrystalline silicon, etc.), the anti-fuse device structure may conduct electricity, so that two device structures electrically isolated are selectively conducted to change a circuit connection inside the semiconductor structure. The core device structure may be a transistor.

In a related art, an anti-fuse device structure and a core device structure in a semiconductor structure are generally prepared simultaneously. During preparation, a substrate having a core device region and an anti-fuse device region outside the core device region is provided. A dielectric layer is then formed on the substrate. A conductive layer is then formed on the dielectric layer. The substrate, the dielectric layer and the conductive layer in the anti-fuse device region constitute the anti-fuse device structure. The substrate, the dielectric layer and the conductive layer in the device region constitute the core device structure.

However, since the dielectric layer in the anti-fuse device structure is generally thick, a programming voltage of the anti-fuse device structure turns out to be high.

Related arts can be found in <CIT>, <CIT>, <CIT> and <CIT>.

In view of this, the disclosure provides a semiconductor structure and a preparation method thereof, which are intended to solve the technical problem of high programming voltage of an anti-fuse device structure.

According to a first aspect, the disclosure provides a preparation method of a semiconductor structure. The preparation method may include: providing a substrate including a core device region and an anti-fuse device region; forming a first dielectric layer covering the core device region and the anti-fuse device region; forming a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer; removing the second dielectric layer on the anti-fuse device region; and forming a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.

The preparation method of the semiconductor structure provided by the disclosure has the following advantages.

According to the preparation method of the semiconductor structure provided by the disclosure, a substrate having a core device region and an anti-fuse device region is provided. A first dielectric layer and a second dielectric layer are then sequentially formed on the substrate. The first dielectric layer covers the core device region and the anti-fuse device region. The second dielectric layer covers the first dielectric layer and has a dielectric constant larger than a dielectric constant of the first dielectric layer. The second dielectric layer on the anti-fuse device region is then removed, and the second dielectric layer on the core device region is retained. A conductive layer is formed on the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region. By removing the second dielectric layer on the anti-fuse device region, a film layer between the conductive layer and the substrate on the anti-fuse device region is thin and has a small dielectric constant, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced. In addition, the second dielectric layer on the core device region is retained, and the second dielectric layer has a dielectric constant larger than a dielectric constant of the first dielectric layer, so that the film layer between the conductive layer and the substrate on the core device region is thick and has a large dielectric constant, thereby improving the reliability of a subsequently formed core device structure.

In the above-described preparation method of the semiconductor structure, after the step of removing the second dielectric layer on the anti-fuse device region and before the step of forming a conductive layer, the preparation method of the semiconductor structure may further include: forming a sacrificial layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region; removing a part of the sacrificial layer and a part of the first dielectric layer on the anti-fuse device region, and removing a part of the sacrificial layer, a part of the second dielectric layer and a part of the first dielectric layer on the core device region; and removing remaining parts of the sacrificial layer to remove the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.

In the above-described preparation method of the semiconductor structure, after the step of removing a part of the sacrificial layer and a part of the first dielectric layer on the anti-fuse device region, and removing a part of the sacrificial layer, a part of the second dielectric layer and a part of the first dielectric layer on the core device region, the preparation method of the semiconductor structure may further include: forming side walls covering side surfaces of the first dielectric layer and the sacrificial layer on the anti-fuse device region and covering side surfaces of the first dielectric layer, the second dielectric layer and the sacrificial layer on the core device region.

In the above-described preparation method of the semiconductor structure, after the step of removing a part of the sacrificial layer and a part of the first dielectric layer on the anti-fuse device region, and removing a part of the sacrificial layer, a part of the second dielectric layer and a part of the first dielectric layer on the core device region, the preparation method of the semiconductor structure may further include forming doped regions. The doped regions of the core device region may be located on two sides of the first dielectric layer on the core device region and be in contact with the first dielectric layer, and the doped regions of the anti-fuse device region may be located on one or two sides of the first dielectric layer on the anti-fuse device region and be in contact with the first dielectric layer.

In the above-described preparation method of the semiconductor structure, the step of removing a part of the sacrificial layer and a part of the first dielectric layer on the anti-fuse device region and removing a part of the sacrificial layer, a part of the second dielectric layer and a part of the first dielectric layer on the core device region may include: forming a mask layer covering the sacrificial layer; etching away the sacrificial layer and the first dielectric layer on the anti-fuse device region, and etching away the sacrificial layer, the second dielectric layer and the first dielectric layer on the core device region; and removing the mask layer.

In the above-described preparation method of the semiconductor structure, before the step of removing remaining parts of the sacrificial layer, the preparation method of the semiconductor structure may further include: forming a silicide layer covering the substrate and the sacrificial layer; forming an Inter Level Dielectric (ILD) layer covering the silicide layer; and planarizing the silicide layer and the ILD layer to expose the sacrificial layer corresponding to the core device region and the anti-fuse device region.

In the above-described preparation method of the semiconductor structure, after the step of forming a first dielectric layer on the substrate and before the step of forming a second dielectric layer on the first dielectric layer, the preparation method of the semiconductor structure may further include: forming an oxynitride layer that is formed after nitrogen-containing annealing of the first dielectric layer.

In the above-described preparation method of the semiconductor structure, the step of forming a conductive layer may include: forming a metal layer that is evaporated, sputtered, or formed by Chemical Vapor Deposition (CVD) on the first dielectric layer on the anti-fuse device region and on the second dielectric layer on the core device region; and planarizing the metal layer.

In the above-described preparation method of the semiconductor structure, the first dielectric layer may be formed on a surface of the substrate by thermal oxidation treatment; or, the first dielectric layer may be formed on the substrate by deposition.

According to a second aspect, the disclosure provides a semiconductor structure. The semiconductor structure may include: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region. The second dielectric layer may have a dielectric constant larger than the first dielectric constant.

The semiconductor structure provided by the disclosure has the following advantages:.

The semiconductor structure provided by the disclosure includes: a core device region and an anti-fuse device region formed on the same substrate, a first dielectric layer disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant, a second dielectric layer disposed on the first dielectric layer corresponding to the core device region, and a conductive layer disposed on the second dielectric layer corresponding to the core device region and the first dielectric layer corresponding to the anti-fuse device region. The second dielectric layer has a dielectric constant larger than the first dielectric constant. Therefore, a film layer between the conductive layer and the substrate on the anti-fuse device region is thin and has a small dielectric constant, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced.

In the above-described semiconductor structure, the second dielectric layer may be a high dielectric constant layer having a dielectric constant of <NUM> to <NUM>.

In the above-described semiconductor structure, a material of the first dielectric layer may include silicon oxide, silicon nitride or silicon oxynitride, and a material of the second dielectric layer may include zirconium oxide or hafnium oxide.

In the above-described semiconductor structure, the first dielectric layer may have a thickness of <NUM> to <NUM>, and the second dielectric layer may have a thickness of <NUM> to <NUM>.

In the above-described semiconductor structure, the semiconductor structure may further include: side walls, disposed on side surfaces of the first dielectric layer and the conductive layer on the anti-fuse device region, and on side surfaces of the first dielectric layer, the second dielectric layer and the conductive layer on the core device region.

In the above-described semiconductor structure, the semiconductor structure may further include doped regions. The doped regions of the core device region may be located on two sides of the first dielectric layer on the core device region and be in contact with the first dielectric layer, and the doped regions of the anti-fuse device region may be located on one or two sides of the first dielectric layer on the anti-fuse device region and be in contact with the first dielectric layer.

In the above-described semiconductor structure, the semiconductor structure may further include: a Shallow Trench Isolation (STI) structure, disposed between the doped regions of the anti-fuse device region of the substrate.

In addition to the above-described technical problems to be solved by the embodiments of the disclosure, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of the technical solutions, other technical problems to be solved by the semiconductor structure and the preparation method thereof provided by the disclosure, other technical features contained in the technical solutions, and the beneficial effects brought by the technical features will be explained in further detail in the detailed description.

A semiconductor structure generally includes an anti-fuse device structure and a core device structure. During preparation, a substrate having a core device region and an anti-fuse device region is provided. A dielectric layer and a conductive layer are then sequentially formed on the substrate. The substrate, the dielectric layer and the conductive layer in the anti-fuse device region constitute the anti-fuse device structure. The substrate, the dielectric layer and the conductive layer in the core device region constitute the core device structure. However, with the above-described method, the dielectric layer of the anti-fuse device structure is thick, and a programming voltage of the anti-fuse device structure is high.

An embodiment of the disclosure provides a preparation method of a semiconductor structure. A first dielectric layer and a second dielectric layer are sequentially formed on a substrate having a core device region and an anti-fuse device region. After the second dielectric layer on the anti-fuse device region is removed, a conductive layer is formed on the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region. By removing the second dielectric layer on the anti-fuse device region, a film layer between the conductive layer and the substrate on the anti-fuse device region is thin and has a small dielectric constant, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced.

To more clarify the objects, technical solutions, and advantages of the embodiments of the disclosure, the technical solutions in the embodiments of the disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the disclosure. It will be apparent that the described embodiments are some, but not all, embodiments of the disclosure. Based on the embodiments in the disclosure, all other embodiments obtained by those of ordinary skill in the art without involving any inventive effort are within the scope of protection of the disclosure.

Referring to <FIG> is a flowchart of a preparation method of a semiconductor structure according to an embodiment of the disclosure. The preparation method may form an anti-fuse device structure having a thin dielectric layer to reduce a programming voltage of the anti-fuse device structure. The preparation method includes the following steps.

In step S101, a substrate including a core device region and an anti-fuse device region is provided.

Referring to <FIG>, a substrate <NUM> in an embodiment of the disclosure includes a core device region and an anti-fuse device region that is located outside the core device region. Exemplarily, the core device region, shown as part B in <FIG> and the anti-fuse device region, shown as part A in <FIG> are spaced apart.

The substrate <NUM> may be a semiconductor substrate <NUM>. In the embodiment of the disclosure, the substrate <NUM> may be a Silicon (Si) substrate. Certainly, the embodiment of the disclosure is not limited thereto. The substrate <NUM> may also be a Germanium (Ge) substrate, a Silicon on Insulator (SOI) substrate, a Silicon Germanide (SiGe) substrate, a Silicon Carbide (SiC) substrate, or a Gallium Nitride (GaN) substrate, etc..

In the embodiment of the disclosure, the substrate <NUM> in the core device region and various film layers located on the core device region may constitute a core device structure, such as a Metal Oxide Semiconductor (MOS) transistor. The substrate <NUM> in the anti-fuse device region and various layers located on the anti-fuse device region may constitute an anti-fuse device structure.

In step S102, a first dielectric layer covering the core device region and the anti-fuse device region is formed.

With continued reference to <FIG>, a first dielectric layer <NUM> covers the core device region and the anti-fuse device region of the substrate <NUM>. The first dielectric layer <NUM> may be made of an oxide, such as silicon oxide (SiO2). The first dielectric layer <NUM> may have a thickness of <NUM>-<NUM>.

The first dielectric layer <NUM> may be formed on the substrate <NUM> by a deposition process. For example, the first dielectric layer <NUM> may be formed on the substrate <NUM> by a CVD process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD) process, etc..

The first dielectric layer <NUM> may also be formed on a surface of the substrate <NUM> by thermal oxidation treatment, that is, an upper part of the substrate <NUM> is formed into the first dielectric layer <NUM> by subjecting an upper surface of the substrate <NUM> shown in <FIG> to thermal oxidation treatment. For example, the first dielectric layer <NUM> is grown on the substrate <NUM> by an In-Situ Steam Generation (ISSG) process.

After forming the first dielectric layer <NUM>, the first dielectric layer <NUM> may be subjected to nitrogen-containing annealing to form an oxynitride layer, such as a silicon oxynitride layer. In this way, the silicon oxynitride layer has better electrical performance, and a threshold voltage of the silicon oxynitride layer is smaller under the same thickness, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced.

In step S103, a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer is formed.

With continued reference to <FIG>, a second dielectric layer <NUM> covers the first dielectric layer <NUM>. Exemplarily, the second dielectric layer <NUM> may be formed on the first dielectric layer <NUM> corresponding to the core device region and the anti-fuse device region by CVD. The second dielectric layer <NUM> may have a thickness of <NUM> to <NUM>.

The second dielectric layer <NUM> has a dielectric constant larger than a dielectric constant of the first dielectric layer <NUM>. Exemplarily, the first dielectric layer <NUM> may be a high dielectric constant layer having a dielectric constant of <NUM> to <NUM> and may be made of Hafnium Oxide (HfO<NUM>) or Zirconium Oxide (ZrO<NUM>), etc. In this way, a breakdown voltage of the second dielectric layer <NUM> may be improved to improve the reliability of a subsequently formed core device structure.

In step S104, the second dielectric layer on the anti-fuse device region is removed.

Referring to <FIG>, the second dielectric layer <NUM> on the anti-fuse device region is removed, and the second dielectric layer <NUM> on the core device region is retained. For example, the second dielectric layer <NUM> on the anti-fuse device region is removed by dry etching or wet etching so that the first dielectric layer <NUM> is retained on the anti-fuse device region.

After removing of a part of the second dielectric layer <NUM>, the thickness of a film layer (the first dielectric layer <NUM>) on the anti-fuse device region is smaller than that of a film layer (the first dielectric layer <NUM> and the second dielectric layer <NUM>) on the core device region, and a dielectric constant of the film layer on the anti-fuse device region is smaller than that of the film layer on the core device region, so that the programming voltage of the subsequently formed anti-fuse device structure is low, and the breakdown voltage of the core device structure is high.

In step S105, a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region is formed.

A conductive layer is deposited on the first dielectric layer <NUM> on the anti-fuse device region and the second dielectric layer <NUM> on the core device region. The conductive layer may be a metal layer, and may be made of one or more of Titanium (Ti), Aluminum (Al), Tungsten (W), Nickel (Ni), and Cobalt (Co). For example, the conductive layer is a TiNx film or an AlNx film.

Exemplarily, the conductive layer may be formed by the following process. A metal layer is formed. The metal layer is evaporated, sputtered, or formed by CVD on the first dielectric layer on the anti-fuse device region and on the second dielectric layer on the core device region. The metal layer is then planarized so that a surface of the metal layer away from the substrate <NUM> is flush. For example, the above-described metal layer is planarized by a Chemical Mechanical Polishing (CMP) process.

Referring to <FIG>, the substrate <NUM> of the anti-fuse device region, and the first dielectric layer <NUM> and the conductive layer <NUM> on the anti-fuse device region form the anti-fuse device structure in the embodiment of the disclosure. The substrate <NUM> of the core device region, and the first dielectric layer <NUM>, the second dielectric layer <NUM> and the conductive layer <NUM> on the core device region form the core device structure in the embodiment of the disclosure.

According to the preparation method of the semiconductor structure provided by the embodiment of the disclosure, a substrate <NUM> having a core device region and an anti-fuse device region is provided. A first dielectric layer <NUM> and a second dielectric layer <NUM> are then sequentially formed on the substrate <NUM>. The first dielectric layer <NUM> covers the core device region and the anti-fuse device region. The second dielectric layer <NUM> covers the first dielectric layer <NUM>, and the second dielectric layer <NUM> has a dielectric constant larger than a dielectric constant of the first dielectric layer <NUM>. The second dielectric layer <NUM> on the anti-fuse device region is then removed, and the second dielectric layer <NUM> on the core device region is retained. A conductive layer <NUM> is then formed on the first dielectric layer <NUM> on the anti-fuse device region and the second dielectric layer <NUM> on the core device region. By removing the second dielectric layer <NUM> on the anti-fuse device region, a film layer between the conductive layer <NUM> and the substrate <NUM> on the anti-fuse device region is thin and has a small dielectric constant, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced. In addition, the second dielectric layer <NUM> on the core device region is retained, and the second dielectric layer <NUM> has a dielectric constant larger than a dielectric constant of the first dielectric layer <NUM>, so that the film layer between the conductive layer <NUM> and the substrate <NUM> on the core device region is thick and has a large dielectric constant, thereby improving the reliability of a subsequently formed core device.

It should be noted that in the embodiment of the disclosure, referring to <FIG>, after the step of removing the second dielectric layer <NUM> on the anti-fuse device region and before the step of forming the conductive layer <NUM>, the preparation method of the semiconductor structure further includes the following steps.

A sacrificial layer <NUM> covering the first dielectric layer <NUM> on the anti-fuse device region and the second dielectric layer <NUM> on the core device region is formed. Referring to <FIG>, the sacrificial layer <NUM> may be formed on the first dielectric layer <NUM> on the anti-fuse device region and the second dielectric layer <NUM> on the core device region by CVD. The sacrificial layer <NUM> may be made of polycrystalline silicon.

After forming the sacrificial layer <NUM>, a part of the sacrificial layer <NUM> and a part of the first dielectric layer <NUM> on the anti-fuse device region are removed, and a part of the sacrificial layer <NUM>, a part of the second dielectric layer <NUM> and a part of the first dielectric layer <NUM> on the core device region are removed.

Exemplarily, the step of removing a part of the sacrificial layer <NUM> and a part of the first dielectric layer <NUM> on the anti-fuse device region and removing a part of the sacrificial layer <NUM>, a part of the second dielectric layer <NUM> and a part of the first dielectric layer <NUM> on the core device region includes the following operations. A mask layer covering the sacrificial layer <NUM> is formed. The sacrificial layer <NUM> and the first dielectric layer <NUM> on the anti-fuse device region are then etched away, and the sacrificial layer <NUM>, the second dielectric layer <NUM> and the first dielectric layer <NUM> on the core device region are etched away. The mask layer is removed.

The sacrificial layer <NUM> and the first dielectric layer <NUM> on the anti-fuse device region are etched away. As shown in <FIG>, right parts of the sacrificial layer <NUM> and the first dielectric layer <NUM> on the anti-fuse device region are etched away to expose the substrate <NUM> of the anti-fuse device region, and required patterns are formed on the sacrificial layer <NUM> and the first dielectric layer <NUM> corresponding to the anti-fuse device region, so as to facilitate subsequent formation of the anti-fuse device structure.

The sacrificial layer <NUM>, the second dielectric layer <NUM> and the first dielectric layer <NUM> on the core device region are etched away simultaneously. As shown in <FIG>, left and right parts of the sacrificial layer <NUM>, the second dielectric layer <NUM> and the first dielectric layer <NUM> on the core device region are etched away to expose the substrate <NUM> of the core device region, and required patterns are formed on the sacrificial layer <NUM>, the second dielectric layer <NUM> and the first dielectric layer <NUM> corresponding to the core device region, so as to facilitate subsequent formation of the core device structure.

It will be appreciated that in the step of removing a part of the sacrificial layer <NUM> and a part of the first dielectric layer <NUM> on the anti-fuse device region and removing a part of the sacrificial layer <NUM>, a part of the second dielectric layer <NUM> and a part of the first dielectric layer <NUM> on the core device region, single-side parts, e.g. right parts, of the sacrificial layer <NUM> and the first dielectric layer <NUM> on the anti-fuse device region may be removed to form a structure shown in <FIG>. Two-side parts, e.g. left and right parts, of the sacrificial layer <NUM> and the first dielectric layer <NUM> on the anti-fuse device region may also be removed to form a structure shown in <FIG>.

After removing a part of the sacrificial layer <NUM> and a part of the first dielectric layer <NUM> on the anti-fuse device region and removing a part of the sacrificial layer <NUM>, a part of the second dielectric layer <NUM> and a part of the first dielectric layer <NUM> on the core device region, remaining parts of the sacrificial layer <NUM> is removed, and the first dielectric layer <NUM> on the anti-fuse device region and the second dielectric layer <NUM> on the core device region are exposed. Referring to <FIG>, the sacrificial layer <NUM> on the anti-fuse device region is removed, and the first dielectric layer <NUM> on the anti-fuse device region is exposed. The sacrificial layer <NUM> on the core device region is removed, and the second dielectric layer <NUM> on the core device region is exposed.

In some possible examples, before the step of removing remaining parts of the sacrificial layer <NUM>, the preparation method of the semiconductor structure further includes the following steps.

First, a silicide layer covering the substrate <NUM> and the sacrificial layer <NUM> is formed.

Then, an ILD layer covering the silicide layer is formed.

And then, the silicide layer and the ILD layer are planarized to expose the sacrificial layer <NUM> corresponding to the core device region and the anti-fuse device region.

It should be noted that referring to <FIG>, after the step of removing a part of the sacrificial layer <NUM> and a part of the first dielectric layer <NUM> on the anti-fuse device region and removing a part of the sacrificial layer <NUM>, a part of the second dielectric layer <NUM> and a part of the first dielectric layer <NUM> on the core device region, the preparation method of the semiconductor structure in the embodiment of the disclosure further includes the following steps.

Side walls <NUM> covering side surfaces of the first dielectric layer <NUM> and the sacrificial layer <NUM> on the anti-fuse device region and covering side surfaces of the first dielectric layer <NUM>, the second dielectric layer <NUM> and the sacrificial layer <NUM> on the core device region are formed.

As shown in <FIG>, side walls <NUM> are respectively formed on the side surfaces of the first dielectric layer <NUM> and the sacrificial layer <NUM> on the anti-fuse device region and the side surfaces of the first dielectric layer <NUM>, the second dielectric layer <NUM> and the sacrificial layer <NUM> on the core device region to protect and support film layers located between the side walls <NUM>.

It should be noted that the side walls <NUM> may be formed on a single side of the first dielectric layer <NUM> on the anti-fuse device region as shown in <FIG>, the side walls <NUM> may also be formed on two sides of the first dielectric layer <NUM> on the anti-fuse device region as shown in <FIG>, and the side walls <NUM> may be disposed according to design requirements.

As shown in <FIG>, after the conductive layer <NUM> is subsequently formed, the side walls <NUM> are in contact with the side surfaces of the first dielectric layer <NUM> and the conductive layer <NUM> on the anti-fuse device region, and the side surfaces of the first dielectric layer <NUM>, the second dielectric layer <NUM> and the conductive layer <NUM> on the core device region.

Doped regions <NUM> are formed. The doped regions <NUM> of the core device region are located on two sides of the first dielectric layer <NUM> on the core device region and are in contact with the first dielectric layer <NUM>. The doped regions <NUM> of the anti-fuse device region are located on one or two sides of the first dielectric layer <NUM> on the anti-fuse device region and are in contact with the first dielectric layer <NUM>.

As shown in <FIG>, the doped region <NUM> of the anti-fuse device region may be located on a right side of the first dielectric layer <NUM> on the anti-fuse device region and be in contact with the first dielectric layer <NUM>. Or as shown in <FIG>, the doped regions <NUM> of the anti-fuse device region may be located on left and right sides of the first dielectric layer <NUM> on the anti-fuse device region and be in contact with the first dielectric layer <NUM>.

The doped regions <NUM> may be formed by implanting ions into the substrate <NUM>. Exemplarily, the substrate <NUM> may be a P-type substrate <NUM>, and the above-described doped region <NUM> is formed by implanting N-type ions into the substrate <NUM>. The doped region <NUM> may be formed after the side walls <NUM>, i.e., the side walls <NUM> are formed before the doped region <NUM> is formed.

Referring to <FIG>, a well may be formed in the substrate <NUM>, a P-well <NUM> (P-Well) may be formed in the substrate <NUM> located in the core device region <NUM>, and an N-well <NUM> (N-Well) may be formed in the substrate <NUM> located in the anti-fuse device region. The doped region <NUM> may be an N-type doped region <NUM>, and the N-type doped region <NUM> is located in the well.

Referring to <FIG>, the substrate <NUM> in the embodiment of the disclosure may further include an STI structure <NUM>. The STI structure <NUM> is disposed on the anti-fuse device region of the substrate <NUM> and is in contact with the first dielectric layer <NUM> corresponding to the anti-fuse device region.

The STI structure <NUM> is used to isolate the N-well <NUM> in the anti-fuse device region of the substrate <NUM>. The STI structure <NUM> may be in contact with the N-well <NUM> as shown in <FIG>, and may be spaced apart therefrom as shown in <FIG>. When the STI structure <NUM> and the N-well <NUM> are disposed as shown in <FIG>, a breakdown point of the subsequently formed anti-fuse structure is located at a contact of the doped region <NUM> and the first dielectric layer <NUM>, so that the resistance consistency of an anti-fuse structure after breakdown is good.

In some possible examples, referring to <FIG>, the anti-fuse device region is provided with a doped region <NUM>, the first dielectric layer <NUM> of the anti-fuse device region is located between the STI structure <NUM> and the doped region <NUM> of the anti-fuse device region, and two sides of the first dielectric layer <NUM> are in contact with the STI structure <NUM> and the doped region <NUM>, respectively. The doped region <NUM> is disposed in the N-well <NUM>, and the N-well <NUM> is spaced apart from the STI structure <NUM>. A side of the first dielectric layer <NUM> corresponding to the doped region <NUM> is provided with the side walls <NUM> in contact therewith.

In other possible examples, as shown in <FIG>, the anti-fuse device region is provided with two doped regions <NUM>, and the STI structure <NUM> is disposed between the two doped regions <NUM>. The first dielectric layer <NUM> of the anti-fuse device region is located between the two doped regions <NUM>, two sides of the first dielectric layer <NUM> are respectively in contact with the two doped regions <NUM>, and a middle part of the first dielectric layer <NUM> is in contact with the STI structure <NUM>. Each doped region <NUM> is disposed in the corresponding N-well <NUM>, and the two N-wells <NUM> are spaced apart from the STI structure <NUM>. Two sides of the first dielectric layer <NUM> are provided with the side walls <NUM> in contact therewith. In this way, two anti-fuse structures sharing the first dielectric layer <NUM> and the conductive layer <NUM> may be formed to increase the number of anti-fuse structures.

Referring to <FIG>, an embodiment of the disclosure provides a semiconductor structure including a core device region and an anti-fuse device region. The core device region and the anti-fuse device region are disposed on a same substrate <NUM>. The anti-fuse device region may be located outside the core device region. Exemplarily, the core device region which may be shown as part B in <FIG> and the anti-fuse device region which may be shown as part A in <FIG> are spaced apart.

The substrate <NUM> may be a semiconductor substrate. Exemplarily, the substrate <NUM> may be a Si substrate, a Ge substrate, an SOI substrate, a SiGe substrate, a SiC substrate, or a GaN substrate, etc. As shown in <FIG>, doped regions <NUM> are also formed in the substrate <NUM>.

The doped regions <NUM> may be formed by implanting ions into the substrate <NUM>. Exemplarily, the substrate <NUM> may be a P-type substrate <NUM>, and the doped region <NUM> is formed by doping N-type ions into the substrate <NUM> by an ion implantation process. As shown in <FIG>, a doped region <NUM> is formed on an upper surface of the substrate <NUM> of the anti-fuse device region, and a doped region <NUM> is formed on an upper surface of the substrate <NUM> of the core device region.

It should be noted that referring to <FIG>, a well may be formed in the substrate <NUM>, a P-well <NUM> (P-Well) may be formed in the substrate <NUM> located in the core device region <NUM>, and an N-well <NUM> (N-Well) may be formed in the substrate <NUM> located in the anti-fuse device region. The doped region <NUM> may be an N-type doped region <NUM>, and the N-type doped region <NUM> is located in the well.

It should be noted that an STI structure <NUM> may also be formed in the substrate <NUM> of the anti-fuse device region. As shown in <FIG>, the STI structure <NUM> is disposed in the anti-fuse device region of the substrate <NUM> and is exposed to a surface of the substrate <NUM>.

The STI structure <NUM> may be in contact with the N-well <NUM> of the substrate <NUM> as shown in <FIG>, and may be spaced apart therefrom as shown in <FIG>. When the STI structure <NUM> and the N-well <NUM> of the substrate <NUM> are disposed as shown in <FIG>, a breakdown point of a subsequently formed anti-fuse structure is located at a contact of the doped region <NUM> and a first dielectric layer <NUM>, so that the resistance consistency of an anti-fuse structure after breakdown is good.

With continued reference to <FIG>, the substrate <NUM> is provided with a first dielectric layer <NUM>. The first dielectric layer <NUM> is in contact with the doped region <NUM>, i.e. the first dielectric layer <NUM> covers a part of the doped region <NUM>. The doped regions <NUM> of the anti-fuse device region are located on one or two sides of the first dielectric layer <NUM> on the anti-fuse device region and are in contact with the first dielectric layer <NUM>. The doped regions <NUM> of the core device region are located on two sides of the first dielectric layer <NUM> on the core device region and are in contact with the first dielectric layer <NUM>.

In some possible examples, referring to <FIG>, the anti-fuse device region is provided with a doped region <NUM>, the first dielectric layer <NUM> of the anti-fuse device region is located between the STI structure <NUM> and the doped region <NUM> of the anti-fuse device region, and two sides of the first dielectric layer <NUM> are in contact with the STI structure <NUM> and the doped region <NUM>, respectively. The doped region <NUM> is disposed in the N-well <NUM>, and the N-well is spaced apart from the STI structure <NUM>.

In other possible examples, as shown in <FIG>, the anti-fuse device region is provided with two doped regions <NUM>, and the STI structure <NUM> is disposed between the two doped regions <NUM>. The first dielectric layer <NUM> of the anti-fuse device region is located between the two doped regions <NUM>, two sides of the first dielectric layer <NUM> are respectively in contact with the two doped regions <NUM>, and a middle part of the first dielectric layer <NUM> is in contact with the STI structure <NUM>. Each doped region <NUM> is disposed in the corresponding N-well <NUM>, and the two N-wells are spaced apart from the STI structure <NUM>. In this way, two anti-fuse structures sharing the first dielectric layer <NUM> and the conductive layer <NUM> may be formed to increase the number of anti-fuse structures.

The first dielectric layer <NUM> may be made of silicon oxide, silicon nitride or silicon oxynitride. The first dielectric layer <NUM> may have a thickness of <NUM> to <NUM>. The first dielectric layer <NUM> may be formed on the upper surface of the substrate <NUM> by thermal oxidation treatment or formed on the substrate <NUM> by a deposition process.

With continued reference to <FIG>, a second dielectric layer <NUM> is disposed on the first dielectric layer <NUM> corresponding to the core device region, and the second dielectric layer <NUM> may have a thickness of <NUM> to <NUM>. The second dielectric layer <NUM> has a dielectric constant larger than the first dielectric constant, i.e., the second dielectric layer <NUM> may be a high dielectric constant layer having a dielectric constant of <NUM> to <NUM>. The second dielectric layer <NUM> may be made of ZrO<NUM> or HfO<NUM>, etc..

A conductive layer <NUM> is disposed on the first dielectric layer <NUM> corresponding to the anti-fuse device region and the second dielectric layer <NUM> corresponding to the core device region. An upper surface of the conductive layer <NUM> corresponding to the anti-fuse device region as shown in <FIG> may be flush with an upper surface of the conductive layer <NUM> corresponding to the core device region.

The conductive layer <NUM> may be a metal layer, and the conductive layer <NUM> may be made of one or more of Ti, Al, W, Ni, and Co. For example, the conductive layer <NUM> is a TiNx film or an AlNx film.

It should be noted that referring to <FIG>, the semiconductor structure in the embodiment of the disclosure may further include side walls <NUM>. The side walls <NUM> are formed on side surfaces of the first dielectric layer <NUM> and the conductive layer <NUM> on the anti-fuse device region and side surfaces of the first dielectric layer <NUM>, the second dielectric layer <NUM> and the conductive layer <NUM> on the core device region to protect and support film layers in the side walls <NUM>.

The side walls <NUM> cover the part of the doped region <NUM>, and a part of the doped region <NUM> away from the first dielectric layer <NUM> is exposed outside the side walls <NUM>, so as to ensure that the formed core device structure and anti-fuse device structure may work normally.

It should be noted that the side walls <NUM> may be located on a single side of the first dielectric layer <NUM> on the anti-fuse device region as shown in <FIG>, or may also be formed on two sides of the first dielectric layer <NUM> on the anti-fuse device region as shown in <FIG>. The side walls <NUM> may be disposed according to design requirements.

As shown in <FIG>, the substrate <NUM> of the anti-fuse device region, and the first dielectric layer <NUM> and the conductive layer <NUM> on the anti-fuse device region form the anti-fuse device structure in the embodiment of the disclosure. The substrate <NUM> of the core device region, and the first dielectric layer <NUM>, the second dielectric layer <NUM> and the conductive layer <NUM> on the core device region form the core device structure in the embodiment of the disclosure.

The semiconductor structure provided by the embodiment of the disclosure includes: a core device region and an anti-fuse device region formed on the same substrate <NUM>, a first dielectric layer <NUM> disposed on the substrate <NUM> of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant, a second dielectric layer <NUM> disposed on the first dielectric layer <NUM> corresponding to the core device region, and a conductive layer <NUM> disposed on the second dielectric layer <NUM> corresponding to the core device region and the first dielectric layer <NUM> corresponding to the anti-fuse device region. The second dielectric layer <NUM> has a dielectric constant larger than the first dielectric constant. Therefore, a film layer between the conductive layer <NUM> and the substrate <NUM> on the anti-fuse device region is thin and has a small dielectric constant, so that a programming voltage of a subsequently formed anti-fuse device structure is reduced. In addition, the film layer between the conductive layer <NUM> and the substrate <NUM> on the core device region is thick and has a large dielectric constant, so that the reliability of a subsequently formed core device is improved.

The embodiments or implementations described in this specification are described in an incremental manner, with each embodiment being described with emphasis on differences from the other embodiments, and with reference to like parts throughout the various embodiments.

Those skilled in the art will appreciate that in the disclosure of the disclosure, orientation or positional relationships indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, which are merely intended to facilitate describing the disclosure and to simplify the description rather than indicating or implying that the referenced system or element must have a particular orientation and be constructed and operated in a particular orientation. Therefore, the above terms are not to be construed as limiting the disclosure.

Claim 1:
A preparation method of a semiconductor structure, comprising:
providing (S101) a substrate comprising a core device region and an anti-fuse device region;
forming (S102) a first dielectric layer covering the core device region and the anti-fuse device region;
forming (S103) a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer;
removing (S104) the second dielectric layer on the anti-fuse device region; and
forming (S105) a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.