Patent Description:
One or more embodiments may be applied to manufacturing integrated circuits (ICs).

Semiconductor devices such as integrated circuits may be provided with packages of various types. For instance, quad-flat no-leads (QFN) packages and land grid array (LGA) packages are examples of surface-mount technology (SMT) packages known in the art.

QFN packages are near chip-scale plastic encapsulated packages provided with a planar leadframe substrate, wherein perimeter lands on the package rear (e.g., bottom) side are configured to provide electrical connections to a printed circuit board (PCB). The leads of the leadframe are thus fully incorporated in the package molding compound. QFN packages may include an exposed thermal pad to improve heat transfer out of the integrated circuit, into the printed circuit board.

LGA packages also have leads fully incorporated in the package molding compound, and comprise a (rectangular) grid of contacts on the bottom side of the package. The contacts on the package are configured to be coupled to a grid of contacts on the PCB.

Both QFN and LGA packages (as well as other SMT packages) do not have external leads, but rather have "lands" or "pads" that are directly couplable to the PCB pads for soldering by means of solder paste or solder alloy. The mounting (soldering) step may be complex and may result in a wide variability of welding strength and structure. Additionally, the different coefficients of thermal expansion between the package and the printed circuit board may lead to high stress in the solder material and/or to high thermal fatigue of QFN/LGA packages once mounted on a printed circuit board.

In this context, the use of "wettable flanks" is known in the art. Wettable flanks help increasing leads wettability with the purpose of improving solder adhesion and overall welding strength by increasing the solder attach area on the vertical side of the lands or pads. Wettable flanks may only slightly improve the solder joint reliability, and facilitate automatic optical inspection of the solder joint after the surface mounting process, for surface mount process control.

Document <CIT> discloses an integrated circuit packaging system including an integrated circuit die, package leads, a die attach paddle, conductive connectors, and an encapsulation. The manufacturing method of the packaging system includes providing a conductive panel including an assembly side and a base side opposite the assembly side. A plating phase includes selectively plating with a plating over the conductive panel, the plating being applied to the assembly side and the base side. A first removal phase includes removal of a portion of the conductive panel over the assembly side to form first elongated cavities having curved surfaces. A masking phase includes a mask layer applied around the first elongated base surface and over the plating facing away from the base side, the first curved surface, and the first curved end. A second removal phase includes removal of the first elongated base surface and a portion of the conductive panel around the mask layer to form second elongated cavities in the first elongated cavities. The second elongated cavities are formed by a second curved surface having a second curved end intersecting a second elongated base surface of the conductive panel. A mask removal process can be used to remove the mask layer to expose a protrusion separating the second curved surface from the first curved surface. In an integration phase, the integrated circuit die can be mounted over the central structure of the conductive panel on the side opposite the base side. The conductive connectors can be attached to circuitry of the integrated circuit die and the plating of the base structures using a connection process. The second elongated base surface, the base structures, the central structure, the plating, the conductive connectors, and the integrated circuit die can be covered with the encapsulation during the integration phase using an encapsulating process. A base removal phase includes removal of a portion of the conductive panel between the plating of the base side.

Document <CIT> discloses a process for manufacturing a semiconductor package. A semiconductor chip is mounted on a semiconductor mounting area of a semiconductor lead frame. Electrodes of the semiconductor chip are electrically connected to internal-terminal plating layers through bonding wires. An encapsulating resin is supplied to fill in a space on and above the top surface of the metal plate by using a mold, thereby encapsulating the top surface side, which is the semiconductor chip mounting side, of the metal plate. The metal plate is etched from the back surface side by using the external-terminal plating layers as an etching mask. By processing the metal plate by an etchback process, a semiconductor mounting part and the lead parts are isolated from each other. The semiconductor chip mounting part and each of the lead parts are formed so as to have an inversed trapezoid cross-sectional shape, that is, a reverse tapered lateral surface shape after the etchback process, thereby preventing the semiconductor chip mounting part and each of the lead parts from falling off from the encapsulating resin. The back surface side of the metal plate after the etchback process is encapsulated with a second resin.

Document <CIT> discloses a method of manufacturing light-emitting devices. According to the method, metal bodies (i.e., die pads and leads) are embedded in a resin. The metal areas of the metal bodies exposed to the surface of the resin are electroplated with a noble metal having a thickness between <NUM> and <NUM>. After plating, an LED chip is mounted on the die pad and connected by bonding wires to the leads. The LED chip and the bonding wires are encapsulated in a transparent resin.

Packaged semiconductor devices providing improved solder joint reliability and/or stronger anchorage to the PCB are desirable.

An object of one or more embodiments is to contribute in providing packaged semiconductor devices, e.g., comprising a QFN- or LGA-type package, with improved solder joint reliability and/or stronger anchorage to the printed circuit board.

According to one or more embodiments, such an object can be achieved by means of a method of manufacturing semiconductor devices (e.g., integrated circuits) having the features set forth in annexed claim <NUM>.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

One or more embodiments provide a packaged semiconductor device (e.g., comprising a QFN or LGA package) comprising at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

By way of introduction to the detailed description of exemplary embodiments, reference may be first had to <FIG>, which are exemplary of a semiconductor device <NUM> comprising a QFN package.

While reference is made mainly to QFN packages in the present description and drawings for the sake of conciseness, one or more embodiments may be applied to other types of "leadless" packages, e.g., LGA packages.

As current in the art, together with other elements/features not visible in the Figures, a semiconductor device <NUM> as exemplified herein may comprise package molding material <NUM> encapsulating a semiconductor die (not visible in <FIG>), the molding material <NUM> being shaped to provide a rear (e.g., bottom) side 10A of the semiconductor device <NUM> configured for electrical and mechanical coupling to a printed circuit board.

A set of electrically conductive "lands" or "pads" <NUM> may be provided on the rear (or bottom) side 10A, e.g., at the periphery thereof, as illustrated in <FIG>. Additionally or alternatively, the pads <NUM> may be arranged over the entire area of the rear side 10A, as customary in LGA packages. The pads <NUM> may be electrically coupled to the semiconductor die encapsulated in the molding material <NUM>.

Optionally, the package may include an exposed thermal pad <NUM> on the rear side 10A. The thermal pad <NUM> may be thermally coupled to the semiconductor die encapsulated in the molding material <NUM> to improve heat transfer out of the integrated circuit <NUM>.

Overall, the electrical pads <NUM> and the thermal pad <NUM> may provide the leadframe of the integrated circuit <NUM>.

The (minimum) spacing between two subsequent pads <NUM> may be constrained by manufacturing constraints of the leadframe. Typically, the corresponding solder pads on a PCB may be wider and/or less spaced. For instance, <FIG> shows a bottom view of an exemplary integrated circuit <NUM> having electrical pads <NUM> and a thermal pad <NUM> (illustrated with solid lines), and a corresponding exemplary arrangement of solder pads <NUM>' and <NUM>' as may be present on a printed circuit board configured for coupling to the integrated circuit <NUM>.

<FIG> is a magnified view exemplary of a portion of the rear side 10A of the integrated circuit <NUM>, e.g., portion <NUM> illustrated in <FIG>. <FIG> is a corresponding side view of portion <NUM>, exemplary of the integrated circuit <NUM> mounted on a printed circuit board <NUM> by means of soldering material <NUM> interposed between the electrical pads <NUM> of the integrated circuit <NUM> and the respective solder pads <NUM>' on the PCB <NUM>.

It is noted that, as a consequence of the spacing Do between pads <NUM> being (considerably) larger than the spacing d between pads <NUM>', electro-mechanical coupling of the integrated circuit <NUM> to the PCB <NUM> may turn out to be unsatisfactory.

In one or more embodiments as exemplified in <FIG>, reliability of such electro-mechanical coupling may be improved by increasing the area of the electrical pads <NUM> of the integrated circuit <NUM>.

<FIG> is a magnified view exemplary of a portion <NUM> of the rear side 10A of an integrated circuit <NUM> according to one or more embodiments. <FIG> is a corresponding side view of portion <NUM>, exemplary of the integrated circuit <NUM> mounted on a printed circuit board <NUM> by means of soldering material <NUM>.

As exemplified herein, a metallic layer may be selectively provided at the pads <NUM> after molding of the package material <NUM> to provide enlarged end portions <NUM> of the pads. The enlarged end portions <NUM> may thus partially extend over the molding material <NUM> at the interface between the pads <NUM> and the molding material <NUM> (e.g., "sidewise" of the body portion <NUM> of the pads which are embedded in the molding material), thereby increasing the area of the pads suitable for electrical and/or mechanical coupling to the soldering pads <NUM>'.

Therefore, in one or more embodiments, a (thick) "pedestal" of metal material may be grown over the surface of the pads <NUM> and/or <NUM> left exposed by the molding material <NUM>, thereby providing larger pads (i.e., providing a reduced spacing Dn between pads <NUM>, which increase the soldering surface) and an increase of the standoff between the semiconductor package <NUM> and the printed circuit board <NUM>. As a result, solder joint reliability may be improved and/or a stronger anchorage of the integrated circuit to the PCB may be obtained.

In one or more embodiments, the enlarged end portions <NUM> may be provided (e.g., grown) over the pads <NUM> and/or <NUM> after molding of the package material <NUM> by means of galvanic plating.

Providing the enlarged end portions <NUM> by galvanic plating may be advantageous insofar as it may facilitate growing the metal <NUM> (sidewise) over the molding compound <NUM> at the interface between the pads <NUM> and/or <NUM> and the molding compound <NUM>, i.e., it may facilitate properly increasing the area of the pads (as exemplified in <FIG>).

In one or more embodiments, the thickness of the enlarged end portions <NUM> may be in the range of <NUM> to <NUM> pm, preferably <NUM> to <NUM>.

The enlarged end portions <NUM> extend (sidewise) over the molding compound <NUM> from the interface between the respective body portion of pad <NUM> and/or <NUM> and the molding compound <NUM> (see length Dp in <FIG>) for <NUM> to <NUM> pm, preferably <NUM> to <NUM>.

In one or more embodiments, the enlarged end portions <NUM> may comprise at least one metal selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au). Preferably, the enlarged end portions <NUM> comprise copper (Cu).

In one or more embodiments, a further metallic layer may be provided over the enlarged end portions <NUM>. For instance, the further metallic layer may comprise tin (Sn) plated over the enlarged end portions <NUM> at the pads <NUM> and/or <NUM>.

One or more embodiments may provide improved reliability (e.g., longer life on board) over previous solutions, e.g., over solutions involving wettable flanks.

<FIG> are exemplary of possible steps of a method of manufacturing semiconductor devices according to one or more embodiments. In such Figures, manufacturing of a pair of semiconductor devices in exemplified.

As exemplified in <FIG>, an otherwise conventional leadframe may be provided as a first manufacturing step. For each semiconductor device, the leadframe may comprise a die pad <NUM> and respective leads <NUM>.

As exemplified in <FIG>, at least one semiconductor die <NUM> may be mounted on each die pad <NUM> of the leadframe. For instance, the semiconductor dies <NUM> may be attached on the die pads <NUM> via die attach material <NUM>, e.g., soft-solder die attach material and/or glue.

As exemplified in <FIG>, wire bonding may be carried out to provide electrical coupling between a semiconductor die <NUM> and the respective leads <NUM> via bonding wires <NUM>.

As exemplified in <FIG>, package molding material <NUM> may be molded to encapsulate the semiconductor dies <NUM> and the leadframe, leaving exposed the electrical pads <NUM> and the thermal pads <NUM> at the rear side of the semiconductor devices.

As exemplified in <FIG>, a metallic layer <NUM> may be provided at the pads <NUM> and/or <NUM> after molding of the package material <NUM>, thereby providing metallic "bumps" (the enlarged end portions) at the package leads. The enlarged end portions <NUM> are grown by galvanic plating. The thickness (t) of the enlarged end portions <NUM> may be in the range of <NUM> to <NUM>, preferably <NUM> to <NUM>. The lateral extension (Dp) of the enlarged end portions <NUM> is in the range of <NUM> to <NUM> pm, preferably <NUM> to <NUM>. The enlarged end portions <NUM> may comprise one or more metals selected out of copper (Cu), nickel (Ni), palladium (Pd) and gold (Au).

As exemplified in <FIG>, a further metallic layer <NUM> may be provided over the metallic layer <NUM>, e.g., by plating. The further metallic layer <NUM> may comprise tin (Sn).

As exemplified in <FIG>, the manufacturing method may comprise singulating the semiconductor devices <NUM>, e.g., by cutting or sawing along sawing lines, as conventional in the art.

Claim 1:
A method comprising:
- providing a leadframe comprising at least one die pad and at least one respective set of electrically conductive leads,
- mounting at least one semiconductor die (<NUM>) onto said at least one die pad,
- electrically coupling (<NUM>) the at least one semiconductor die (<NUM>) to electrically conductive leads in the respective at least one set of electrically conductive leads,
- molding package molding material (<NUM>) onto the at least one semiconductor die (<NUM>) and the leadframe, the package molding material (<NUM>) exposing at least a portion of the electrically conductive leads at a rear surface (10A) of the package molding material (<NUM>) to provide electrically conductive pads (<NUM>) that comprise body portions (<NUM>) embedded in the package molding material (<NUM>), and
- providing, by galvanic plating, enlarged end portions (<NUM>) of the electrically conductive pads (<NUM>), the enlarged end portions (<NUM>) protruding from the package molding material (<NUM>) and extending at least partially over the package molding material (<NUM>) sidewise of said body portions (<NUM>) for a length (Dp) of <NUM> to <NUM> pm, the enlarged end portions (<NUM>) configured for coupling to a printed circuit board (<NUM>) .