Patent Description:
An integrated circuit package typically includes an integrated circuit die and a substrate on which the die is mounted. The die can be coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die may then travel through the bonding wires or solder bumps to the substrate.

As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, more and more applications demand a packaged solution with more integration than possible in one silicon die. In an effort to meet this need, more than one die may be placed within a single integrated circuit package (i.e., a multichip package). As different types of devices cater to different types of applications, more dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, an integrated circuit package may include multiple dies arranged laterally along the same plane.

EMIBs are small silicon dies that are sometimes embedded in the substrate of a multichip package and are used to interconnect integrated circuit dies within that multichip package. Traditionally, these EMIBS have limited power delivery capability compared to other interposer technologies such as silicon interposers.

It is within this context that the embodiments described herein arise.

<CIT> describes a coreless package substrate with dual solder resist layers. The coreless package substrate includes a build-up structure <NUM> containing an alternating arrangement of insulating layers <NUM> and conductive layers. The conductive layers may be electrically coupled to one another through the insulating layers by vias. The coreless package substrate includes an embedded device within the build-up structure. The embedded device may be an embedded interconnect bridge formed of a silicon, an organic, or a glass material.

<CIT> describes an integrated device package which includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

<CIT> describes an apparatus including a package substrate including a plurality of layers 0f conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones 0f the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers.

<CIT> describes a low-cost integrated circuit package for packaging integrated circuits. The package comprises a flexible circuit that is laminated to a stiffener using a dielectric adhesive, with the conductive traces on the flexible circuit facing toward the stiffener but separated therefrom by the adhesive. The conductive traces include an array of flip-chip attachment pads. A window is formed in the stiffener over the attachment pad array, such as by etching. The adhesive is then removed over the attachment pads by laser ablation, but left in place between the pads, thus forming a flip-chip attachment site.

<CIT> describes a multilayer printed wiring board. A large-diameter through hole at an outer peripheral part is a signal line. A small-diameter through hole at a central part is a power source line and ground line, thus arraying multiple power source lines and ground lines and shortening the wiring length from an IC chip to a daughter board. So the inductance component of the power source line and ground line to the IC chip is reduced, preventing malfunction of the IC chip.

<CIT> describes a multi-chip package that includes multiple integrated circuits. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.

The invention is set forth in the independent claims. Embodiments of the invention are described in the dependent claims.

An integrated circuit package may include a package substrate and one or more integrated circuit dies mounted on the package substrate. The package substrate may include an embedded multi-die interconnect bridge (EMIB) embedded within the package substrate. An EMIB is a silicon die that may be used to interconnect two integrated circuits in a multi-chip package. The integrated circuit dies mounted on the package substrate may communicate with one another through the EMIB. The EMIB may have a front side that faces the integrated circuit dies and a back side that opposes the front side. The package substrate may include a conductive path that is electrically coupled to the EMIB from the back side of the EMIB and that supplies power to the EMIB. The package substrate may be mounted on a printed circuit board that provides power to the EMIB through the conductive path.

The package substrate may also include a conductive layer (e.g., back side conductor) on which the EMIB is mounted. The conductive path may be connected to the conductive layer and may provide power to the EMIB through the conductive layer. A patterned adhesive layer may be applied to the conductive layer before the EMIB is mounted on the conductive layer and may include openings that accommodate conductive pads (e.g., contact pads) formed at the back side of the EMIB. In other words, once the EMIB is mounted on the conductive layer, the patterned adhesive layer may laterally surround the conductive pads formed at the back side of the EMIB. Additional contact pads may be formed at the front side of the EMIB.

The package substrate may include a first via directly connected to a contact pad formed at the front side of the EMIB, and may include a second via that is coupled to a contact pad formed at the back side of the EMIB through the conductive layer. The second via may have a diameter that is greater than a diameter of the first via.

The EMIB may include a conductive routing trace (e.g., interconnect) that is coupled to the integrated circuit dies. A microvia formed in the EMIB may be coupled between one of the conductive pads formed at the back side of the EMIB and the conductive routing trace. Power supply voltage signals or data signals may be provided to the conductive routing trace through the microvia.

The EMIB may include multiple through-silicon vias that extend from the back side of the EMIB to the front side of the EMIB. These through-silicon vias may be used to transfer power or data signals from the conductive path to the integrated circuit dies through the EMIB.

The conductive layer may include multiple conductive regions that are electrically isolated from one another. Each region of the conductive layer may receive a different power supply voltage signal or data signal from each other region of the conducive layer.

Fabricating an integrated circuit package may include multiple processing steps. A first dielectric layer may be formed. A via may be formed through the first dielectric layer. A conductive layer may be formed on the first dielectric layer in direct physical contact with the via. Forming the conductive layer may involve forming multiple conductive regions that are electrically isolated from one another. A silicon die (e.g., an EMIB) may be mounted on the conductive layer. Additional dielectric layers may be formed covering the silicon die. A first integrated circuit die may be mounted on the additional dielectric layers. A second integrated circuit die may be mounted on the additional dielectric layers. The silicon die may include a conductive routing trace that couples the first integrated circuit die to the second integrated circuit die.

Before forming the additional dielectric layer, a second dielectric layer may be formed on the first dielectric layer. A cavity may be formed in the second dielectric layer directly over the conductive layer. Mounting the silicon die on the conductive layer may include inserting the silicon die into the cavity. A patterned adhesive layer may be formed between the silicon die and the conductive layer. The patterned adhesive die may include a plurality of openings to accommodate contact pads formed on a bottom surface of the silicon die.

Further features of the present invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.

Embodiments of the present invention relate to integrated circuits, and more particularly, to ways of improving power delivery through an embedded multi-die interconnect bridge in a multichip package.

As integrated circuit fabrication technology scales towards smaller process nodes, it becomes increasingly challenging to design an entire system on a single integrated circuit die (sometimes referred to as a system-on-chip). Designing analog and digital circuitry to support desired performance levels while minimizing leakage and power consumption can be extremely time consuming and costly.

One alternative to single-die packages is an arrangement in which multiple dies are placed within a single package. Such types of packages that contain multiple interconnected dies may sometimes be referred to as systems-in-package (SiPs), multi-chip modules (MCM), or multichip packages. Placing multiple chips (dies) into a single package may allow each die to be implemented using the most appropriate technology process (e.g., a memory chip may be implemented using the <NUM> technology node, whereas the radio-frequency analog chip may be implemented using the <NUM> technology node), may increase the performance of die-to-die interface (e.g., driving signals from one die to another within a single package is substantially easier than driving signals from one package to another, thereby reducing power consumption of associated input-output buffers), may free up input-output pins (e.g., input-output pins associated with die-to-die connections are much smaller than pins associated with package-to-board connections), and may help simplify printed circuit board (PCB) design (i.e., the design of the PCB on which the multi-chip package is mounted during normal system operation).

In order to facilitate communications between two chips on a multi-chip package, the package may include an embedded multi-die interconnect bridge (EMIB) that is designed and patented by INTEL Corporation. An EMIB is a small silicon die that is embedded in the underlying substrate of a multi-chip package and that offers dedicated ultra-high-density interconnection between dies within the package. EMIBs generally include wires of minimal length, which help to significantly reduce loading and directly boost performance.

EMIB solutions may be advantageous over other multi-chip packaging schemes that use a silicon interposer, which is prone to issues such as warpage and requires a comparatively large number of microbumps and through-silicon vias (TSVs) to be formed on and within the interposer, thereby reducing overall yield and increasing manufacturing complexity and cost. The number of dies that can be integrated using an interposer is also limited to that supported by EMIB technology.

The EMIB technology described above may be used as an interface between one or more integrated circuit dies in a system. <FIG> is a diagram of an illustrative system <NUM> of interconnected electronic devices. The system of interconnected electronic devices may have multiple electronic devices such as device A, device B, device C, device D, and interconnection resources <NUM>. Interconnection resources <NUM> such as conductive lines and busses, optical interconnect infrastructure, or wired and wireless networks with optional intermediate switching circuitry may be used to send signals from one electronic device to another electronic device or to broadcast information from one electronic device to multiple other electronic devices. For example, a transmitter in device B may transmit data signals to a receiver in device C. Similarly, device C may use a transmitter to transmit data to a receiver in device B.

The electronic devices may be any suitable type of electronic device that communicates with other electronic devices. Examples of such electronic devices include basic electronic components and circuits such as analog circuits, digital circuits, mixed-signal circuits, circuits formed within a single package, circuits housed within different packages, circuits that are interconnected on a printed-circuit board (PCB), etc..

As shown in <FIG>, a multi-chip package <NUM> may include a main die <NUM>, a transceiver die <NUM>, a memory die <NUM>, and additional auxiliary dies <NUM>. Main die <NUM>, for example, may be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or any other desired processor or logic device. Secondary integrated circuit dies such as transceiver die <NUM>, memory die <NUM>, and auxiliary dies <NUM> may be coupled to main die <NUM> and may communicate with main die <NUM>. Memory die <NUM>, for example, may be an erasable-programmable read-only memory (EPROM) chip, a non-volatile memory (e.g., 3D XPoint) chip, a volatile memory (e.g., high bandwidth memory) chip, or any other suitable memory device. Auxiliary dies <NUM> may include additional memory dies, transceiver dies, programmable logic devices, and any other suitable integrated circuit devices.

An EMIB may be embedded in a multi-chip package to connect two adjacent integrated circuit dies on the package. As shown in <FIG>, main die <NUM> and secondary die <NUM> may be mounted onto package substrate <NUM> using solder bumps <NUM> and solder microbumps <NUM>. Package substrate <NUM> may be mounted onto printed circuit board (PCB) <NUM> using solder (e.g., solder balls, solder bumps) <NUM>. The terms solder "balls" or solder "bumps" may sometimes be use interchangeably. Signals (e.g., data signals and power supply voltage signals) may be transferred between PCB <NUM> and dies <NUM> and <NUM> through solder balls <NUM>, package vias <NUM> in package <NUM>, and solder bumps <NUM>.

Main die <NUM> may be coupled to a secondary die <NUM> using EMIB <NUM> that is embedded in package substrate <NUM>. Signals being passed between main die <NUM> and secondary die <NUM> may pass through interconnects (e.g., conductive paths) <NUM> and microbumps <NUM>. EMIB <NUM> may have a front side that faces main die <NUM> and secondary die <NUM> and may have a back side that faces package substrate <NUM>. An EMIB is traditionally formed on a solid, electrically floating conductive plate for structural support. It is therefore difficult to provide power to microbumps <NUM> that overlap with regions <NUM> and <NUM> of main die <NUM> and secondary die <NUM>, as power cannot be delivered vertically from the PCB through the EMIB to regions <NUM> and <NUM> because back side routing is blocked by the conductive plate.

<FIG> shows a top view of package substrate <NUM> in regions <NUM> and <NUM> and illustrates possible means of power and ground signal delivery to microbump arrays in regions <NUM> and <NUM>. Two microbump arrays in regions <NUM> and <NUM> may overlap with EMIB <NUM> formed in package substrate <NUM>. Each microbump array, for example, may correspond to an edge of an integrated circuit die (e.g., main die <NUM> and secondary die <NUM> of <FIG>). Three different voltage signals may be applied to the pads of package substrate <NUM>: (<NUM>) a common voltage signal Vss (e.g., ground power supply voltage signal), (<NUM>) a power supply voltage signal Vcc1 for region <NUM> (e.g., for secondary die <NUM> in <FIG>), and a power supply voltage signal Vcc2 for region <NUM> (e.g., for main die <NUM> of <FIG>). It should be noted that a portion of the microbumps in region <NUM> may also receive power supply voltage signal Vcc1.

These power supply and common voltage signals may be delivered to peripheral microbumps in regions <NUM> and <NUM> without exceptional loss in power efficiency. For example, voltage signals Vss, Vcc1, and Vcc2 may be delivered to the microbumps at the edges of the microbump arrays of regions <NUM> and <NUM> using conductors (e.g., copper traces) formed in a top layer of the package substrate.

Additionally, microbumps in the center (e.g., not at the periphery) of the microbump arrays of regions <NUM> and <NUM> may have voltage signals Vss, Vcc1, and Vcc2 routed to them by forming conductors (e.g., copper traces) in a top layer of the package substrate arranged to extend vertically across a given microbump array. Only microbumps in the path of one of these conductors may receive the respective voltage signal carried by that conductor. However, extending one of these conductors to cover the entire width of a microbump array may undesirably result in a loss in power efficiency. It would therefore be advantageous to provide alternate means of power delivery for microbumps in the center of the microbump arrays of regions <NUM> and <NUM>.

One alternative to the topside microbump power delivery described above is to deliver power and ground signals to the microbumps from the PCB vertically through the package substrate and the EMIB from the back side. As shown in <FIG>, main die <NUM> may be mounted onto package substrate <NUM> using solder bumps (e.g., controlled collapse chip connection (C4) bumps) <NUM> and microbumps <NUM>. It should be noted that the pitch width of solder bumps <NUM> may be greater than the pitch width of microbumps <NUM>, such that microbumps <NUM> have greater connection density than solder bumps <NUM>. The diameter of microbumps <NUM> are also generally smaller than the diameter of C4 bumps <NUM> (e.g., bumps <NUM> may be at least two times smaller, at least four times smaller, etc.).

Solder bumps <NUM> may be provided with signals (e.g., data signals or power supply voltage signals) from a printed circuit board (e.g., PCB <NUM> of <FIG>) through vias <NUM> and traces <NUM> formed in routing layers <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> of package substrate <NUM>. If desired, the package substrate may include additional layers (e.g., the number of layers in the package substrate is not limited to four).

Microbumps <NUM> may be provided with signals (e. g, data signals or power supply voltage signals) from EMIB <NUM> through vias <NUM> and traces <NUM>. The signals provided to microbumps <NUM> may be received from another chip coupled to EMIB <NUM> or from a PCB (e.g., PCB <NUM> of <FIG>) on which package substrate <NUM> is mounted. It should be noted that vias <NUM> may be smaller than vias <NUM> and vias <NUM>'.

According to the claimed invention, EMIB <NUM> may be mounted on a back side conductor (e.g., conductive layer or copper conductive layer) <NUM> in layer <NUM>-<NUM> of package substrate <NUM> using an adhesive layer <NUM> during fabrication of package substrate <NUM>. A cavity <NUM> may be included adjacent to EMIB <NUM> in order to account for differences between the coefficient of thermal expansion between EMIB <NUM> and package substrate <NUM>, which may reduce thermal stresses placed on EMIB <NUM>.

EMIB <NUM> may include through-silicon vias (TSVs) that extend vertically from the front side of EMIB <NUM> to the back side of EMIB <NUM> to connect contact pads <NUM> formed on the front side of EMIB <NUM> to contact pads <NUM> formed on the back side of EMIB <NUM>. Adhesive layer <NUM> may be patterned to accommodate contact pads <NUM> to ensure that contact pads <NUM> are in electrical contact with back side conductor <NUM>. In other words, adhesive layer <NUM> may laterally surround contact pads <NUM> of EMIB <NUM> without being interposed between contact pads <NUM> and back side conductor <NUM>.

In accordance with an embodiment, back side conductor <NUM> may receive power supply voltage signals and/or data signals from a PCB (e.g., PCB <NUM> of <FIG>) through vias <NUM>' and traces <NUM>' and may provide these signals to contact pads <NUM> of EMIB <NUM>. It should be noted that vias <NUM>' may have a diameter that is larger than the diameter of vias <NUM>. Having a larger diameter allows vias <NUM>' to carry more power than would be achievable with vias having a comparatively smaller diameter.

By providing signals to EMIB <NUM> from the PCB through back side conductor <NUM>, vias <NUM>', and traces <NUM>', and providing power to one or both circuit dies through TSVs <NUM> in EMIB <NUM>, vertical power distribution may be achieved through EMIB <NUM>.

Conventional EMIB arrangements lack such back side vertical power distribution paths and instead are limited to passing power between chips connected by the EMIB over the EMIB itself or by routing power to these chips around the EMIB. Both of these conventional power distribution options disadvantageously reduce power efficiency of the system containing the EMIB by requiring smaller gauge traces or longer traces for power delivery compared to the vertical power distribution path coupled to EMIB <NUM>.

Thus, the vertical power distribution path coupled between the PCB and the back side of EMIB <NUM> that includes back side conductor <NUM>, vias <NUM>', and traces <NUM>' is advantageous over these conventional EMIB arrangements in terms of power efficiency.

Signals may also be provided from the PCB to internal interconnects of EMIB <NUM>. As shown in <FIG>, EMIB <NUM> may include interconnects (e.g., conductive routing traces) <NUM> and <NUM>. Contact pads <NUM>-<NUM> and <NUM>-<NUM> may receive power supply voltage signals, ground voltage signals, or data signals (e.g., from back side conductor <NUM> of <FIG>), and may pass these signals to EMIB microvias <NUM> and <NUM>. Microvia <NUM> may include a portion interposed between interconnect <NUM> and contact pad <NUM>-<NUM>, such that signals received by contact pad <NUM>-<NUM> may be passed to interconnect <NUM>. Microvia <NUM> may also include a portion interposed between interconnect <NUM> and contact pad <NUM>-<NUM>, such that signals received by contact pad <NUM>-<NUM> may also be passed to contact pad <NUM>-<NUM> and thereby to any microbumps coupled to contact pad <NUM>-<NUM>.

Microvia <NUM> may only extend from contact pad <NUM>-<NUM> to interconnect <NUM>. Contact pad <NUM>-<NUM> may pass received signals to interconnect <NUM> through microvia <NUM>. Optionally, an additional microvia <NUM>' may be interposed between interconnect <NUM> and interconnect <NUM> and/or may be interposed between contact pad <NUM>-<NUM> and interconnect <NUM>. This arrangement allows for signals received by contact pad <NUM>-<NUM> to be passed to each of interconnects <NUM> and <NUM> and to contact pad <NUM>-<NUM> and thereby to any microbumps coupled to contact pad <NUM>-<NUM>.

If desired, back side conductor <NUM> of <FIG> may be separated into multiple regions that are electrically isolated from one another, where each region may receive a different power supply voltage signal, ground voltage signal, or data signal from the PCB. Some possible arrangements of back side conductor <NUM> are described below in connection with <FIG>.

As shown in <FIG>, back side conductor <NUM> may be horizontally separated into regions <NUM>, <NUM>, and <NUM> that are each electrically isolated from one another. Power supply voltage signal Vcc1 may be applied to region <NUM>. Common (e.g., ground) power supply voltage signal Vss may be applied to region <NUM>. Power supply voltage signal Vcc2 may be applied to region <NUM>. This arrangement of back side conductor <NUM> allows for the three different types of power/ground voltage signals to be applied to the microbumps of either of the two chips connected to one another through the EMIB (e.g., EMIB <NUM>) attached to back side conductor <NUM>.

As shown in <FIG>, back side conductor <NUM> may be vertically separated into regions <NUM>, <NUM>, and <NUM> that are each electrically isolated from one another. Power supply voltage signal Vcc2 may be applied to region <NUM>. Common (e.g., ground) power supply voltage signal Vss may be applied to region <NUM>. Power supply voltage signal Vcc3 may be applied to region <NUM>. This arrangement of back side conductor <NUM> allows for power supply voltage signal Vcc2 to be applied to the microbumps of one of the two chips connected to one another through the EMIB (e.g., EMIB <NUM>) attached to back side conductor <NUM>, for power supply voltage signal Vcc3 to be applied to the microbumps of the other chip of the two chips, and for common signal Vss to be applied to either or both of the two chips.

As shown in <FIG>, back side conductor <NUM> may be separated into three vertically separated regions that are each electrically isolated from one another, similar to the arrangement of <FIG>. Each vertically separated region may receive one of power supply voltage signal Vcc1, power supply voltage signal Vcc2, and common signal Vss. Back side conductor <NUM> may further include two horizontal regions <NUM> and <NUM> that are electrically isolated from one another and from the three separated vertical regions. Data signal SIG1 may be applied to region <NUM> and data signal SIG <NUM> may be applied to region <NUM>. In this way, data signals may also be passed to the EMIB (e.g., EMIB <NUM>) that is mounted on back side conductor <NUM>.

The arrangements of back side conductor <NUM> shown in <FIG> are merely illustrative. If desired, back side conductor <NUM> may include any number of regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal (e.g., from a printed circuit board).

<FIG> shows the illustrative steps performed when manufacturing package substrate <NUM> of <FIG>.

At step <NUM>, first dielectric layer <NUM>-<NUM> may be formed. Vias <NUM> and <NUM>' in layer <NUM>-<NUM> and traces <NUM> and <NUM>' may also be formed at this step.

At step <NUM>, second dielectric layer <NUM>-<NUM> may be formed. Via <NUM>, trace <NUM>, and back side conductor <NUM> may also be formed in layer <NUM>-<NUM> at this step. As described in connection with <FIG> above, back side conductor <NUM> may be formed having multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal.

At step <NUM>, third dielectric layer <NUM>-<NUM> may be formed. Via <NUM> and trace <NUM> may be formed in layer <NUM>-<NUM> at this step.

At step <NUM>, A cavity may be formed in second dielectric layer <NUM>-<NUM> and third dielectric layer <NUM>-<NUM> (e.g., using photolithographic etching, lapping, or drilling). The cavity may overlap back side conductor <NUM> and may extend through layers <NUM>-<NUM> and <NUM>-<NUM> so as to expose back side conductor <NUM>.

At step <NUM>, adhesive layer <NUM> may be patterned within the cavity, such that openings are formed in adhesive layer <NUM> to accommodate contact pads <NUM> of EMIB <NUM>.

At step <NUM>, EMIB <NUM> may be placed on the patterned adhesive within the cavity, and may thereby be mounted on back side conductor <NUM>. It should be noted that any TSVs or internal EMIB microvias may already be formed within EMIB <NUM> prior to the placement of EMIB <NUM> in the cavity (e.g., during fabrication of EMIB <NUM>).

At step <NUM>, remaining dielectric layers including dielectric layer <NUM>-<NUM> and the portion of dielectric layer <NUM>-<NUM> disposed over EMIB <NUM> may be formed. Vias <NUM> and <NUM> and traces (e.g., via pads) <NUM> and <NUM> may also be formed at this step.

Optionally, step <NUM> may be omitted and the entirety of layer <NUM>-<NUM> may be formed during step <NUM>. In this optional case, the cavity only needs to be formed in second dielectric layer <NUM>-<NUM> during step <NUM>.

The embodiments thus far have been described with respect to integrated circuits. The methods and apparatuses described herein may be incorporated into any suitable circuit. For example, they may be incorporated into numerous types of devices such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.

Claim 1:
A multi-chip package, comprising:
an interconnect bridge (<NUM>) having a first contact pad (<NUM>) and a second contact pad (<NUM>) thereon, and a third contact pad (<NUM>) and fourth contact pad (<NUM>) underneath, the interconnect bridge (<NUM>) connected to the first and second contact pads (<NUM>) and the third and fourth contact pads (<NUM>), the third and fourth contact pads (<NUM>) in electrical contact with a conductive layer (<NUM>) under the interconnect bridge (<NUM>);
a first dielectric layer (<NUM>-<NUM>), the first dielectric layer laterally adjacent the interconnect bridge (<NUM>), and the first dielectric layer laterally adjacent and in contact with the conductive layer (<NUM>);
a second dielectric layer (<NUM>-<NUM>) on the first dielectric layer (<NUM>-<NUM>), the second dielectric layer over the interconnect bridge (<NUM>) and over the conductive layer (<NUM>);
a first via in the second dielectric layer, the first via coupled to the first contact pad;
a second via in the second dielectric layer, the second via coupled to the second contact pad;
a third via in the second dielectric layer, the third via coupled to a via (<NUM>) in the first dielectric layer (<NUM>-<NUM>);
a third dielectric layer (<NUM>-<NUM>) on the second dielectric layer, the third dielectric layer over the interconnect bridge (<NUM>) and over the conductive layer (<NUM>);
a first conductive trace (<NUM>) in the third dielectric layer (<NUM>-<NUM>), the first conductive trace coupled to the first via;
a second conductive trace (<NUM>) in the third dielectric layer (<NUM>-<NUM>), the second conductive trace coupled to the second via;
a first die over the third dielectric layer, the first die over the interconnect bridge (<NUM>) and over the conductive layer (<NUM>) and the first die (<NUM>) coupled to the first conductive trace and to the second conductive trace; and
a second die over the interconnect bridge (<NUM>), the second die coupled to the first die by the interconnect bridge (<NUM>).