Patent Description:
An aspect of the invention is a delay circuit that includes : afirst, a second, a third and a fourth transistor; a first inverter coupled to the first transistor and the second transistor, wherein the first transistor is connected to the second transistor in parallel, the first inverter is configured to receive a first intermediate delayed clock signal from the parallel first and second transistors and generate a positive delayed clock signal to be received by a first NAND gate of a comparator; a second inverter coupled to the third transistor and the fourth transistor, wherein the third transistor is connected to the fourth transistor in parallel, the second inverter configured to receive a second intermediate delayed clock signal from the parallel third and fourth transistors and generate a negative delayed clock signal to be received by a second NAND gate of the comparator; wherein the delay circuit is arranged such that the resistance of the first transistor in parallel with the second transistor determines a delay in the positive delayed clock signal; and the resistance of the third transistor in parallel with the fourth transistor determines a delay in the negative delayed clock signal; and a pair of cross-coupled capacitors cross coupling the first and second inverters.

Yet another aspect of <NUM>. the invention is a comparator that includes a differential input pair of transistors and the delay circuit. The differential input pair of transistors includes a first input transistor and a second input transistor.

In this description, the term "couple" or "couples" means either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. Also, in this description, the recitation "based on" means "based at least in part on. " Therefore, if X is based on Y, then X may be based on Y and any number of other factors.

ADCs are used to convert analog signals into a digital representation of the same signal. ADCs are used in a wide variety of applications, ranging from medical and entertainment to communications (both voice and data). One key design block of any ADC is the comparator. The comparator generates digital output signals based on the comparison of an analog input signal with a reference voltage.

For example, in a SAR ADC, the comparator compares a sampled analog input signal to the analog output of an internal DAC and outputs a digital output signal to a SAR circuit that generates a digital code of the analog input signal voltage which is provided to the DAC. The SAR circuit is initialized so that the most significant bit (MSB) is equal to digital one. This digital code is output into the DAC which converts the digital code into an analog equivalent based on a reference signal. The DAC's analog output is then received by the comparator. If the analog input signal has a voltage that is greater than the voltage of the DAC's analog output, the comparator will output a HIGH signal (thus causing the SAR to keep the MSB as one); however, if the analog signal has a voltage that is less than the voltage of the DAC's analog output, the comparator will output a LOW signal (thus causing the SAR to reset the MSB as zero). Each bit in the SAR is tested in a similar manner against the analog input signal by the comparator until every bit has been set The resulting code is output as the digital output signal that represents the analog input signal. Comparators are similarly important in sigma-delta modulated ADCs, flash ADCs, high speed radio frequency (RF) sampling converters, etc..

Because the comparator is essential to ADCs, the speed of the comparator affects the speed of the entire ADC. In other words, by increasing the speed of the comparator, the speed of the ADC may also be increased. Conventional high speed ADCs include comparators that require input information (e.g., the analog input signal and reference signal) until the comparator gives a valid decision (e.g., generates the output signal). In <NUM> technology, the time for a comparator to make a decision is typically greater than 100ps. Therefore, ADCs using conventional comparators typically require an amplifier that drives the comparators to hold the input for at least 100ps. In other words, conventional systems require the amplifier that drives the comparator to hold the input signal for a relatively long period of time. Therefore, the operation of the ADC is slowed. Furthermore, because the input signal is held for a relatively long period of time, timing complexities are introduced into these conventional systems.

In accordance with various examples, a relatively high speed latch comparator is provided. Such a comparator includes, in various examples, a voltage controlled delay circuit that converts the input voltage information into time information. The input clock of the comparator (LATP) is delayed by the delay circuit in proportion to the input voltage. Therefore, the delayed input signals (which can include a pair of differential delayed input signals (INPD and INMD) include the input information (e.g., input voltage) in the time domain. Depending on which of the signals INPD or INMD arrives at the latch first, the latch triggers, allowing the comparator to generate an output signal. For such a comparator, the delay generated by the delay circuit is relatively low (e.g., approximately 25ps). Furthermore, input voltage movements (e.g., change in the input voltage) after the signals INPD and INMD are generated will not affect the decision of the comparator (e.g., will not affect the outputted signal). Therefore, input information is not needed when the comparator is making a decision. In this way, the speed of the comparator is increased, and timing complexities are reduced. Additionally, the input information is not corrupted during processing.

<FIG> shows an illustrative block diagram of an ADC <NUM> in accordance with various examples not covered by the invention. The ADC <NUM> includes, in an embodiment, a comparison circuit <NUM>, DAC <NUM>, and a summation circuit <NUM>. The summation circuit <NUM> is configured to receive an analog input signal <NUM> (e.g., a time-varying analog voltage) and an analog feedback signal <NUM> which is an analog version of the comparison circuit output signal <NUM>. The summation circuit <NUM> is further configured to sum the analog input signal <NUM> and the analog feedback signal <NUM> to generate the summed analog signal <NUM>.

The comparison circuit <NUM> includes at least one comparator <NUM>. For example, the comparator <NUM> can be configured to compare the summed analog input signal <NUM> with a reference signal <NUM> and generate a digital comparison circuit output signal <NUM>. Thus, for example, if the summed analog input signal <NUM>, which corresponds with the analog input signal <NUM>, has a voltage that is greater than the voltage of the reference signal <NUM>, the comparator <NUM> will output a HIGH signal as the digital comparison circuit output signal <NUM>; however, if the summed analog input signal <NUM> has a voltage that is less than the voltage of the reference signal <NUM>, the comparator <NUM> will output a LOW signal as the digital comparison circuit output signal <NUM>. The DAC <NUM> receives the digital comparison circuit output signal <NUM> and generates an analog version of the digital comparison circuit output signal <NUM> as the analog feedback signal <NUM>.

As discussed above, the comparator <NUM> can be one of numerous comparators in the comparison circuit <NUM>. Thus, for example, the comparison circuit <NUM> can include a number of comparators that generate separate bits of the digital comparison circuit output signal <NUM>.

<FIG> shows an illustrative circuit diagram of comparator <NUM> in accordance with various examples. The comparator <NUM> includes, in an example, a pair of back-to-back negative-AND (NAND) gates that are made up of the differential input pair of transistors <NUM>-<NUM> and the regeneration transistors <NUM>-<NUM> and <NUM>-<NUM>. For example, one NAND gate can include the transistors <NUM>, <NUM>, and <NUM> while the second NAND gate can include the transistors <NUM>, <NUM>, and <NUM>. The comparator <NUM> also includes timing transistors <NUM> and <NUM> which are configured to receive the triggering clock signal LATP and delay elements <NUM>-<NUM>. The delay elements <NUM>-<NUM> are coupled to the back-to-back NAND gates and are configured to modulate the triggering clock signal LATP by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. For example, the input voltage received by the comparator <NUM> can be a differential signal composed of the positive input signal (INP) 222a and the negative input signal (INM) 222b. More particularly, the delay element <NUM> is configured to receive INP 222a while delay element <NUM> is configured to receive INM 222b. Additionally, the delay elements <NUM>-<NUM> are configured to receive a reference signal, which, in an example, is a differential signal composed of the positive reference signal (REFP) 224a and the negative reference signal (REFM) 224b. More particularly, the delay element <NUM> is configured to receive REFM 224b while delay element <NUM> is configured to receive REFP 224a. In some examples, the reference signals REFP 224a and REFM 224b are set so that the threshold of the comparator <NUM> is equal to the voltage of REFP 224a minus the voltage of REFM 224b.

The delay element <NUM> is configured to generate a positive delayed clock signal (INPD) 226a whose delay is proportional to the voltage level of the INP 222a. In other words, the input transistor <NUM> receives a delayed version of the triggering clock signal LATP, the delay amount being proportional to INP 222a. The delay element <NUM> is configured to generate a negative delayed clock signal (INMD) 226b whose delay is proportional to the voltage level of INM 222b. In other words, the input transistor <NUM> receives a delayed version of the triggering clock signal LATP, the delay amount being proportional to INM 222b. In this way, the delay in the delayed clock signal is proportional to the input voltage. In other words, the input voltage signal is converted into time information before being processed by the back-to-back NAND gates.

<FIG> shows an illustrative circuit diagram for a delay circuit <NUM> of comparator <NUM> in accordance with various examples. The delay circuit <NUM> can include the delay elements <NUM>-<NUM> shown in <FIG>. The delay circuit <NUM> includes, in an example, the transistors <NUM>-<NUM>, inverters <NUM>-<NUM>, and a pair of cross-coupled capacitors that include capacitors <NUM>-<NUM>. In some examples, the transistors <NUM>-<NUM> are n-channel metal-oxide-semiconductor field-effect (NMOS) transistors. However, in other examples, the transistors <NUM>-<NUM> can be p-channel metal-oxide-semiconductor field-effect (PMOS) transistors, bipolar junction transistors (BITs) or any combination thereof (e.g., a combination of NMOS transistors and PMOS transistors). The transistors <NUM>-<NUM> are, in an example, PMOS transistors; however, the transistors <NUM>-<NUM> can be NMOS transistors, BITs or any combination thereof (e.g., a combination of NMOS transistors and PMOS transistors).

The transistors <NUM>-<NUM> are configured to receive the triggering clock signal LATP which then is provided to the transistors <NUM>-<NUM>. More particularly, transistors <NUM>-<NUM> are in parallel with one another, and transistors <NUM>-<NUM> are in parallel with one another. The transistor <NUM> is configured to receive at its gate INP 222a. Therefore, the resistance of the transistor <NUM> is proportional to the voltage level of INP 222a. The transistor <NUM> is configured to receive at its gate REFM 224b. Therefore, the resistance of the transistor <NUM> is proportional to the voltage level of REFM 224b. Transistor <NUM> is configured to receive at its gate INM 222b. Therefore, the resistance of the transistor <NUM> is proportional to the voltage level of INM 222b. Transistor <NUM> is configured to receive at its gate REFP 224a. Therefore, the resistance of the transistor <NUM> is proportional to the voltage level of REFP 224a.

For example, the parallel transistors <NUM>-<NUM> receive the triggering clock signal LATP and generate an intermediate delayed clock signal 352a (a delayed version of LATP) that is based on the resistance of the parallel transistors <NUM>-<NUM> (and thus based on the voltage level of INP 222a and REFM 224b). Thus, if the resistance of the parallel transistors <NUM>-<NUM> is relatively large, then the delay in LATP will be relatively large in the resulting intermediate delayed clock signal 352a. However, if the resistance of the parallel transistors <NUM>-<NUM> is relatively small, then the delay in LATP will be relatively small in the resulting intermediate delayed clock signal 352a. In this way, the resistance (caused by the voltage levels of INP 222a and REFM 224b) of the parallel transistors <NUM>-<NUM> determines the delay in the intermediate delayed clock signal 352a and thus, INPD 226a.

Similarly, the parallel transistors <NUM>-<NUM> receive the triggering clock signal LATP and generate an intermediate delayed clock signal 352b (a delayed version of LATP) that is based on the resistance of the parallel transistors <NUM>-<NUM> (and thus based on the voltage level of INM 222b and REFP 224a). Thus, if the resistance of the parallel transistors <NUM>-<NUM> is relatively large, then the delay in LATP will be relatively large in the resulting intermediate delayed clock signal 352b. However, if the resistance of the parallel transistors <NUM>-<NUM> is relatively small, then the delay in LATP will be relatively small in the resulting intermediate delayed clock signal 352b. In this way, the resistance (caused by the voltage levels of INM 222b and REFP 224a) of the parallel transistors <NUM>-<NUM> determines the delay in the intermediate delayed clock signal 352b and thus, INMD 226b.

The delay difference between the intermediate delayed clock signal 352a and the intermediate delayed clock signal 352b can be relatively small; therefore, the pair of cross-coupled capacitors that includes the capacitors <NUM>-<NUM> are included in some examples to provide more resolution in the delay difference between INPD 226a and INMD 226b. For example, the inverter <NUM> is configured, in an example, to receive the intermediate delayed clock signal 352a from the parallel transistors <NUM>-<NUM> and invert the intermediate delayed clock signal 352a to generate INPD 226a. Similarly, the inverter <NUM> is configured, in an example, to receive the intermediate delayed clock signal 352b from the parallel transistors <NUM>-<NUM> and invert the intermediate delayed clock signal 352b to generate INMD 226b. Due to the presence of the capacitors <NUM>-<NUM> in a cross-coupled configuration, if INPD 226a transitions HIGH before INMD 226b transitions HIGH, then the transition of INMD 226b to HIGH is delayed. Similarly, if INMD 226b transitions HIGH before INPD 226a transitions HIGH, then the transition of INPD 226a to HIGH is delayed. The higher resolution in the delay difference between INPD 226a and INMD 226b enables the comparator <NUM> to provide an accurate decision as its output signal.

In one specific example to generate a high resolution delay difference between INPD 226a and INMD 226b, the drains of transistors <NUM>-<NUM> are connected to the input terminal of inverter <NUM> and a first terminal of capacitor <NUM>. Thus, the first terminal of capacitor <NUM> is connected to the input terminal of inverter <NUM>. The drains of transistors <NUM>-<NUM> are connected to the input terminal of inverter <NUM> and a first terminal of capacitor <NUM>. Thus, the first terminal of capacitor <NUM> is connected to the input terminal of inverter <NUM>. The second terminal of capacitor <NUM> is connected to the output terminal of inverter <NUM> and thus, to INMD 226b. The second terminal of capacitor <NUM> is connected to the output terminal of inverter <NUM> and thus, to INPD 226a.

<FIG> shows an illustrative timing diagram <NUM> of LATP, INPD 226a and INMD 226b in delay circuit <NUM> of comparator <NUM> in accordance with various examples. More particularly, the timing diagram <NUM> shows the timing of the signals LATP, INPD 226a, and INMD 226b if the voltage of INP 222a minus the voltage of INM 222b is greater than the voltage of REFP 224a minus the voltage of REFM 224b (i.e., (INP - INM) > (REFP - REFM)). Thus, as shown in <FIG>, when (INP - INM) > (REFP - REFM), INPD 226a triggers before INMD 226b triggers.

<FIG> shows an illustrative timing diagram <NUM> of LATP, INPD 226a, and INMD 226b in delay circuit <NUM> of comparator <NUM> in accordance with various examples. More particularly, the timing diagram <NUM> shows the timing of the signals LATP, INPD 226a, and INMD 226b if the voltage of INP 222a minus the voltage of INM 222b is less than the voltage of REFP 224a minus the voltage of REFM 224b (i.e., (INP - INM) < (REFP - REFM)). Thus, as shown in <FIG>, when (INP - INM) < (REFP - REFM), INMD 226b triggers before INPD 226a triggers.

<FIG> shows an illustrative block diagram of flash ADC comparison circuit <NUM> in accordance with various examples. The example comparison circuit <NUM> includes, in an example, delay circuits <NUM>, <NUM>, and <NUM>, first level comparators <NUM>-<NUM> and <NUM>, interpolation comparators <NUM>-<NUM>, and dummy comparators <NUM>-<NUM> and <NUM>-<NUM>. The comparators <NUM>-<NUM> and <NUM>-<NUM> are, in an example, similar to the comparator <NUM> from <FIG> without the delay elements <NUM>-<NUM>. The delay circuits <NUM> and <NUM> are similar, in an example, to the delay circuit <NUM> except with one or more different input signals. For example, while the delay circuit <NUM> receives INP 222a, INM 222b, REFP 224a, and REFM 224b, the delay circuit <NUM> receives different reference signals (e.g., REFP 574a and REFM 574b) in addition to INP 222a and INM 222b and the delay circuit <NUM> receives the triggering clock signal LATP-IN as the only input.

The comparators <NUM>-<NUM> are configured to generate triggering clock signals for successive levels of comparators, each level delayed from the previous level. For example, the clock signal LATP_IN is used as the triggering clock signal for the first level comparators <NUM>-<NUM>, LATP1 is used as the triggering clock signal for the second level of comparators that includes interpolation comparator <NUM> and the dummy comparators <NUM>-<NUM>, the triggering clock signal LATP2 is used as the triggering clock signal for the third level of comparators that includes interpolation comparators <NUM>-<NUM> and the dummy comparators <NUM>-<NUM>, and the triggering clock signal LATP3 is used as the triggering clock signal for the fourth level of comparators that includes interpolation comparators <NUM>-<NUM>.

The first level comparator <NUM> compares the positive delayed clock signal generated by the delay circuit <NUM> with the negative delayed clock signal generated by the delay circuit <NUM> and generates a differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). Similarly, the first level comparator <NUM> compares the positive delayed clock signal generated by the delay circuit <NUM> with the negative delayed clock signal generated by the delay circuit <NUM> and generates a differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). The interpolation comparator <NUM> receives the negative comparator output signal from the comparator <NUM> and the positive comparator output signal from the comparator <NUM> and generates a second level differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). The dummy comparators <NUM>-<NUM> are utilized to match the timing difference generated by the interpolation comparator <NUM> for the third level of comparators.

The third level of comparators works in a similar manner as the second level of comparators except that there are now two interpolation comparators (e.g., interpolation comparators <NUM>-<NUM>). For example, the interpolation comparator <NUM> receives the negative comparator output signal from the interpolation comparator <NUM> and the positive comparator output signal from the dummy comparator <NUM> and generates a third level differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). The interpolation comparator <NUM> receives the positive comparator output signal from the interpolation comparator <NUM> and the negative comparator output signal from the dummy comparator <NUM> and generates a third level differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). The dummy comparators <NUM>-<NUM> are utilized to match the timing difference generated by the interpolation comparators <NUM>-<NUM> for the fourth level of comparators.

The fourth level of comparators works in a similar manner as the second level of comparators and the third level of comparators except that there are now four interpolation comparators (e.g., interpolation comparators <NUM>-<NUM>). For example, the interpolation comparator <NUM> receives the negative comparator output signal from the dummy comparator <NUM> and the positive comparator output signal from the interpolation comparator <NUM> and generates a single bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that makes up a single bit of the comparison circuit <NUM> output signal <NUM>. The interpolation comparator <NUM> receives the negative comparator output signal from the interpolation comparator <NUM> and the positive comparator output signal from the dummy comparator <NUM> and generates a single bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that makes up a single bit of the comparison circuit <NUM> output signal <NUM>. The interpolation comparator <NUM> receives the negative comparator output signal from the dummy comparator <NUM> and the positive comparator output signal from the interpolation comparator <NUM> and generates a single bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that makes up a single bit of the comparison circuit <NUM> output signal <NUM>. The interpolation comparator <NUM> receives the negative comparator output signal from the interpolation comparator <NUM> and the positive comparator output signal from the dummy comparator <NUM> and generates a single bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that makes up a single bit of the comparison circuit <NUM> output signal <NUM>.

Thus, the input information (INP 222a, INM 222b, REFP 224a, REFP 224b, REFP 574a, and REFM 574b) is needed only for the duration of the delay element of the delay circuits <NUM> and <NUM> to modulate the input triggering clock LATP_IN. The entire conversion can follow asynchronous operation and thus, only one input triggering clock is needed. Furthermore, as the last level of comparators (e.g., the fourth level of comparators) is in a decision phase, the first level of comparators can begin processing the next input sample. Moreover, each level of interpolation gives a gain for the next level of comparators, thus, all the comparators need not be designed for noise.

Claim 1:
A delay circuit, comprising:
a first, a second, a third and a fourth transistor (<NUM>, <NUM>, <NUM>, <NUM>);
a first inverter (<NUM>) coupled to the first transistor (<NUM>) and the second transistor (<NUM>), wherein the first transistor (<NUM>) is connected to the second transistor (<NUM>) in parallel, the first inverter (<NUM>) is configured to receive a first intermediate delayed clock signal from the parallel first and second transistors and generate a positive delayed clock signal (226a) to be received by a first negative-AND NAND gate of a comparator;
a second inverter (<NUM>) coupled to the third transistor (<NUM>) and the fourth transistor (<NUM>), wherein the third transistor (<NUM>) is connected to the fourth transistor (<NUM>) in parallel, the second inverter (<NUM>) configured to receive a second intermediate delayed clock signal from the parallel third and fourth transistors and generate a negative delayed clock signal to be received by a second NAND gate of the comparator; wherein the delay circuit is arranged such that
the resistance of the first transistor (<NUM>) in parallel with the second transistor (<NUM>) determines a delay in the positive delayed clock signal (226a); and
the resistance of the third transistor (<NUM>) in parallel with the fourth transistor (<NUM>) determines a delay in the negative delayed clock signal; characterized by
a pair of cross-coupled capacitors (<NUM>, <NUM>) cross coupling the first and second inverters (<NUM>, <NUM>).