Patent Description:
As DRAM technology has evolved, storage arrays in successive DRAM generations have been organized in increasingly complex and flexible ways intended to provide increased performance over previous generations. For example, storage arrays have been organized in banks, and banks have been organized in bank groups, etc. Also, as memory bus widths have increased, the manner in which memory buses have been organized in channels has continued to evolve.

A memory controller architecture may attempt to leverage these more complex DRAM organizational features to improve performance for memory clients. Nevertheless, a computing device may have several memory clients (e.g., CPU, GPU, NPU, etc.), not all of which may benefit equally from a particular memory controller architecture. Attention is drawn to <CIT> describing a memory device that includes at least two independent interface paths, an interface path including multiple memory banks. The memory device can selectively operate in a bank mode or a bank group mode. In bank mode, banks are operated as logical banks, where separate physical banks from different interface paths operate in parallel. When a logic bank is accessed, all physical banks belonging to the logical bank are accessed in parallel across the interface paths. In bank group mode, banks are operated independently, but accessed in bank groups. A separate interface path is operated as an independent bank group, and a bank is individually accessed in its bank group. In bank group mode, back to back access to separate bank groups is possible without resulting in access delay. Attention is further drawn to <CIT> describing a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder. Further attention is drawn to <CIT> describing apparatuses and methods for dual channel memory architecture with reduced interface pin requirements. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

Further examples of the invention are described in the dependent claims.

Systems, methods, computer-readable media, and other examples are disclosed for accessing data in a dynamic random access memory (DRAM). Data is accessed by a memory controller selecting a broadcast mode or a non-broadcast mode.

A method for accessing data in a DRAM is defined by claim <NUM>.

A system for accessing data in a DRAM is defined by claim <NUM>.

An exemplary DRAM may include a plurality of DRAM storage arrays and a DRAM command interface. The DRAM command interface may be configured to receive a command having a selectable pseudo-channel broadcast mode indication. The DRAM command interface may further be configured to concurrently access a first portion of the requested data in the DRAM storage arrays via a first pseudo-channel and a second portion of the requested data in the DRAM storage arrays via a second pseudo-channel in response to the command when the state of the pseudo-channel broadcast mode indication indicates the broadcast mode. The DRAM command interface may still further be configured to access the requested data in the DRAM storage arrays via a selected one of the first and second pseudo-channels in response to the command when the state of the pseudo-channel broadcast mode indication indicates the non-broadcast mode.

" The word "illustrative" may be used herein synonymously with "exemplary.

As illustrated in <FIG>, a system <NUM> may include a system-on-a-chip ("SoC") <NUM> coupled to at least one dynamic random access memory ("DRAM") device <NUM> via a memory bus <NUM>. Although not shown for purposes of clarity, the system <NUM> may be included in a computing device, which may be of any type.

The DRAM device <NUM> may double data-rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to for brevity as "DDR. " As DDR technology has evolved, DDR versions such as fourth generation low-power DDR ("LPDDR4") and fifth generation low-power DDR ("LPDDR5") have been developed.

The DRAM device <NUM> may include two storage array groups <NUM>: a first storage array group 108A and a second storage array group 108B. Although not shown for purposes of clarity, each storage array group <NUM> may be organized in the form of eight bank groups ("BG"s), and each of the eight bank BGs may be organized in the form of two banks. Each storage array group <NUM> thus consists of <NUM> banks in the illustrated embodiment.

The first storage array group 108A may be coupled to a first input/output ("I/O") interface 110A of the DRAM device <NUM>, and the second storage array group 108B may be coupled to a second I/O interface 110B of the DRAM device <NUM>. The number of data lines coupling each storage array group <NUM> to its respective I/O interface 110A or 110B may be, for example, <NUM> bits.

In the illustrated embodiment, the memory bus <NUM> may be <NUM> bits wide (i.e., consisting of <NUM> data lines). In the illustrated embodiment, the data lines may be organized in the form of <NUM> lower-order bits (i.e., two lower-order data bytes) and <NUM> higher-order bits (i.e., two higher-order data bytes), represented in <FIG> in the notation "DQ[<NUM>:<NUM>]" and "DQ[<NUM>:<NUM>]," respectively. In addition to the data lines, the memory bus <NUM> may include a first read strobe signal associated with the lower-order data bytes DQ[<NUM>:<NUM>] and a second read strobe signal associated with the higher-order data bytes DQ[<NUM>:<NUM>]. The first and second read strobe signals may be in the form of differential (i.e., a pair of true and complement) signals and represented in <FIG> in the notation "(RDQS0_t,RDQS0_c)" and "(RDQS1 t,RDQSO_c)," respectively. The memory bus <NUM> may further include a first data clock signal associated with the lower-order data bytes DQ[<NUM>:<NUM>] and a second data clock signal associated with the higher-order data bytes DQ[<NUM>:<NUM>]. The first and second data clock signals may be in the form of differential signals and represented in <FIG> in the notation "(WCK0_t,WCK0_c)" and "(WCK1_t,WCK0_c)," respectively. The memory bus <NUM> may still further include a first data mask inversion signal ("DMI0") associated with the lower-order data bytes DQ[<NUM>:<NUM>] and a second data mask inversion signal ("DMI1") associated with the higher-order data bytes DQ[<NUM>:<NUM>].

The lower-order data byte signals DQ[<NUM>:<NUM>], the first data mask inversion signal DMI0, the first data clock signal (WCK0_t,WCK0_c ), and the first read strobe signal (RDQS0_t,RDQS0_c) may be coupled to the first I/O interface 110A. The higher-order data byte signals DQ[<NUM>:<NUM>], the second data mask inversion signal DMI1, the second data clock signal (WCK1_t,WCK1_c ), and the second read strobe signal (RDQS1_t,RDQS1_c) may be coupled to the second I/O interface 110B.

Another portion of the memory bus <NUM> may include control signals. The control signals may include a command and address ("CA") bus. The CA bus may be of any size and represented in <FIG> in the notation "CA[<NUM>:n]. " The control signals may also include a clock signal associated with the CA bus. The clock signal associated with the CA bus may be in the form of differential signals and represented in <FIG> in the notation "(CK_t,CK_c). " The control signals may further include a chip-select ("CS") signal and a reset ("RESET") signal. The DRAM device <NUM> may include a command/address and clock interface <NUM> configured to receive the control signal portion of the memory bus <NUM>.

Conceptually, the memory bus <NUM> may be configured as two pseudo-channels: a first pseudo-channel 114A and a second pseudo-channel 114B. The first pseudo-channel 114A (also referred to as "PC0") may include the lower-order data byte signals DQ[<NUM>:<NUM>], the first data mask inversion signal DMI0, the first data clock signal (WCK0_t,WCK0_c), the first read strobe signal (RDQS0_t,RDQS0_c), the clock signal (CK_t,CK_c) associated with the CA bus, the chip-select signal, and the reset signal. The second pseudo-channel 114B (also referred to as "PC1") may include the higher-order data byte signals DQ[<NUM>:<NUM>], the second data mask inversion signal DMI1, the second data clock signal (WCK1 _t,WCK1_c), the second read strobe signal (RDQS1_t,RDQS1_c), the clock signal (CK_t,CK_c) associated with the CA bus, the chip-select signal, and the reset signal. Note that the control signal portion of the memory bus, comprising the clock signal (CK_t,CK_c) associated with the CA bus, the chip-select signal, and the reset signal, is shared by or common to the first pseudo-channel 114A and a second pseudo-channel 114B. The first and second pseudo-channels 114A and 114B are referred to herein as "pseudo" channels rather than actual channels because they share their control signals.

The SoC <NUM> may include a physical memory interface or "PHY" <NUM> coupled to the memory bus <NUM> and a memory controller <NUM> coupled to the PHY <NUM>. Through a bus-like interconnect <NUM> (sometimes referred to as a fabric), the memory controller <NUM> may communicate with any of various processing engines <NUM>, such as, for example, a multi-core central processing unit ("CPU") 121A, a graphics processing unit ("GPU") and multi-media engine 122B, a neural processing unit ("NPU") 122C, etc. Any of the processing engines <NUM> may act as a client device with respect to the DRAM device <NUM> to initiate memory access operations with the DRAM device <NUM> through the memory controller <NUM>. Although in the embodiment illustrated in <FIG> there are three client devices, in other embodiments there may be any number of client devices.

In <FIG>, a timing diagram <NUM> illustrates an example of operation of the above-described system <NUM> (<FIG>). With additional reference to <FIG>, the exemplary operation (timing diagram <NUM>) represents the memory controller <NUM> concurrently receiving (via the PHY <NUM>) a first portion of some requested data from the DRAM (i.e., DRAM device <NUM>) via the first pseudo-channel 114A and a second portion of the requested data from the DRAM via the second pseudo-channel 114B. This operation illustrated in the timing diagram <NUM> is referred to herein as a "broadcast" mode. As described below, the system <NUM> may selectively perform memory read operations in the broadcast mode or in a non-broadcast mode. The memory controller <NUM> may initiate the data access in response to a request received from a client device, as further described below.

As illustrated in <FIG>, before a time T0 and through a time T1 the memory controller <NUM> may issue a CAS command that includes a pseudo-channel broadcast ("PCB") mode indication set to a state that indicates the broadcast mode. For example, a predetermined bit of the CAS command may be a PCB mode bit set to a value of "<NUM>" (i.e., PCB=<NUM>) to indicate the broadcast mode. Then, before a time T2 and through a time T3 the memory controller <NUM> may issue a Read command. The Read command may likewise include a PCB mode bit set to a value of "<NUM>" (i.e., PCB=<NUM>) to indicate the broadcast mode. For brevity, in <FIG> the notation "CAS PCB=<NUM>" indicates the CAS command and "Read PCB=<NUM>" indicates the Read command, but it should be understood that the commands may include other bits. For example, a write clock-to-clock sync option bit may be asserted: WS_RD=<NUM>.

The Read command may include an indication of the amount of data requested, such as <NUM> bytes in the example illustrated in <FIG>. The Read command may also include a burst length ("BL") indication, such as a burst length of <NUM> in the example illustrated in <FIG>. As well understood by one of ordinary skill in the art, the chip-select signal may be asserted during the CAS and Read commands. Other aspects of the timing diagram <NUM> and corresponding configurations of the memory controller <NUM> and DRAM device <NUM> (<FIG>), etc., which are similarly well understood by one of ordinary skill in the art are not described herein for brevity.

Continuing in <FIG>, in response to the Read command, a first <NUM>-byte portion of the requested <NUM> bytes of data may arrive from the DRAM (DRAM device <NUM>) on the first pseudo-channel 114A portion of the memory bus <NUM> (<FIG>), i.e., DQ[<NUM>:<NUM>], after a delay or time interval beginning at time T3. This time interval may be equal to a read latency ("RL"), which begins at time T3, plus four cycles of the clock signal (WCK0_t,CK_c) or read strobe signal (RDQS0_t,RDQS0_c). In a notation in which "nCK" means "number of clock cycles," this time interval may be expressed as RL+4nCK, i.e., RL plus four clock cycles. Similarly, in response to the Read command, a second <NUM>-byte portion of the requested <NUM> bytes of data may arrive from the DRAM on the second pseudo-channel 114B portion of the memory bus <NUM>, i.e., DQ[<NUM>:<NUM>], after the same delay or time interval beginning at time T3: RL+4nCK. That is, when a read operation is performed in broadcast mode the first and second portions of the requested amount of data arrive concurrently with each other on the first and second pseudo-channels 114A and 114B, respectively, after a time interval of RL+4nCK. Although not shown in the timing diagram <NUM>, the memory controller <NUM> then conveys the requested data back to the requesting client device.

In <FIG>, a timing diagram <NUM> illustrates another example of operation of the above-described system <NUM> (<FIG>). With reference to <FIG>, the exemplary operation (timing diagram <NUM>) represents the memory controller <NUM> sequentially receiving (via the PHY <NUM>) a first portion of some requested data from the DRAM (i.e., DRAM device <NUM>) via the first pseudo-channel 114A and a second portion of the requested data from the DRAM via the second pseudo-channel 114B. The timing diagram <NUM> illustrates an example of the system <NUM> operating in a "non-broadcast" mode.

As illustrated in <FIG>, before a time T0 and through a time T1 the memory controller <NUM> may issue a first CAS command that includes the PCB mode indication set to a state that indicates the non-broadcast mode as well as a pseudo-channel selection indication ("PCS") set to a state that indicates a selected one of the first and second pseudo-channels 114A (PCO) and 114B (PC1). In the illustrated example, the above-described PCB mode bit may be set to a value of "<NUM>" (i.e., PCB=<NUM>) to indicate the non-broadcast mode. Another predetermined bit of the first CAS command may be a PCS bit set to a value of "<NUM>" (i.e., PCS=<NUM>) to indicate selection of the first pseudo-channel 114A (PCO) in the illustrated example. Then, before a time T2 and through a time T3 the memory controller <NUM> may issue a first Read command. The first Read command may likewise include the PCB mode bit set to a value of "<NUM>" to indicate the non-broadcast mode and the PCS bit set to a value of "<NUM>" to indicate selection of the first pseudo-channel 114A (PCO). For brevity, in <FIG> the notation "CAS PC0" indicates the first CAS command and "Read" indicates the first Read command, but it should be understood that in this example the first CAS command and first Read command include PCB=<NUM> and PCS=<NUM>. The first CAS command may also include other bits that are similarly not indicated in <FIG> for brevity, such as WS_RD=<NUM>.

Before a time T4 and through a time T5 the memory controller <NUM> may issue a second CAS command that includes the PCB mode indication set to a state that indicates the non-broadcast mode and the PCS indication set to a state that indicates selection of the second pseudo-channel 114B (PC1). That is, in the illustrated example: PCB=<NUM> and PCS=<NUM>. Then, before a time T6 and through a time T7 the memory controller <NUM> may issue a second Read command. The second Read command may likewise include the PCB mode bit set to a value of "<NUM>" to indicate the non-broadcast mode and the PCS bit set to a value of "<NUM>" to indicate selection of the first pseudo-channel 114A (PCO). For brevity, in <FIG> the notation "CAS PC1" indicates the second CAS command and "Read" indicates the second Read command, but it should be understood that in this example the second CAS command and second Read command include PCB=<NUM> and PCS=<NUM>. The second CAS command may also include other bits that are similarly not indicated in <FIG> for brevity, such as WS_RD=<NUM>.

Each of the first and second Read commands may also include an indication of the amount of data requested, such as, for example, <NUM> bytes, for a total of <NUM> bytes of requested data in the example illustrated in <FIG>. The Read commands may also include a BL indication of <NUM> in the example illustrated in <FIG>. Other aspects of the timing diagram <NUM> and corresponding configurations of the memory controller <NUM> and DRAM device <NUM> (<FIG>), etc., which are well understood by one of ordinary skill in the art are not described herein for brevity.

Continuing in <FIG>, in response to the first Read command, a first <NUM>-byte portion of the requested <NUM> bytes of data may arrive from the DRAM on the first pseudo-channel 114A portion of the memory bus <NUM> (<FIG>), i.e., DQ[<NUM>:<NUM>], after a delay or time interval beginning at time T3 (<FIG>). Similarly, in response to the second Read command, a second <NUM>-byte portion of the requested <NUM> bytes of data may arrive from the DRAM on the second pseudo-channel 114B portion of the memory bus <NUM>, i.e., DQ[<NUM>:<NUM>], after another delay or time interval beginning at time T7 (<FIG>). When a read operation is performed in a non-broadcast mode the first and second portions of the requested amount of data arrive sequentially with each other on the first and second pseudo-channels 114A (PCO) and 114B (PC1), respectively, in response to the first and second Read commands, respectively. That is, when a read operation is performed in a non-broadcast mode the first portion of the requested data arrives first on DQ[<NUM>:<NUM>], and the second portion of the requested data arrives on DQ [<NUM>:<NUM>] after the first portion of the requested data has arrived on DQ[<NUM>:<NUM>]. The total delay or time interval from the first Read command to the arrival of all <NUM> bytes of the requested data is RL +8nCK in the example illustrated in <FIG>. Although not shown in the timing diagram <NUM>, the memory controller <NUM> then conveys the requested data back to the requesting client device.

In <FIG>, a timing diagram <NUM> illustrates still another example of operation of the above-described system <NUM> (<FIG>). With reference to <FIG>, the exemplary operation (timing diagram <NUM>) represents the memory controller <NUM> sequentially receiving (via the PHY <NUM>) a first portion of some requested data from the DRAM (i.e., DRAM device <NUM>) via the first pseudo-channel 114A and a second portion of the requested data from the DRAM via the second pseudo-channel 114B. The timing diagram <NUM> illustrates another example of the system <NUM> operating in the "non-broadcast" mode.

As illustrated in <FIG>, before a time T0 and through a time T1 the memory controller <NUM> may issue a first CAS command that includes the PCB mode indication set to a state that indicates the non-broadcast mode as well as the PCS indication set to a state that indicates selection of the first pseudo-channel 114A (PCO). That is, in the illustrated example: PCB=<NUM> and PCS=<NUM>. Then, before a time T2 and through a time T3 the memory controller <NUM> may issue a first Read command. The first Read command may likewise include the PCB mode bit set to a value of "<NUM>" to indicate the non-broadcast mode and the PCS bit set to a value of "<NUM>" to indicate selection of the first pseudo-channel 114A (PCO). For brevity, in <FIG> the notation "CAS PC0" indicates the first CAS command and "Read" indicates the first Read command, but it should be understood that in this example the first CAS command and first Read command include PCB=<NUM> and PCS=<NUM>. The first CAS command may also include other bits that are similarly not indicated in <FIG> for brevity, such as WS_RD=<NUM>.

Each of the first and second Read commands may also include an indication of the amount of data requested, such as, for example, <NUM> bytes (per Read command) in the example illustrated in <FIG>. The Read commands may also include a BL indication of <NUM> in the example illustrated in <FIG>. Other aspects of the timing diagram <NUM> and corresponding configurations of the memory controller <NUM> and DRAM device <NUM> (<FIG>), etc., which are well understood by one of ordinary skill in the art are not described herein for brevity.

Continuing in <FIG>, in response to the first Read command, a first <NUM>-byte portion of the requested data may arrive from the DRAM on the first pseudo-channel 114A (PC0), i.e., DQ[<NUM>:<NUM>], after a delay or time interval beginning at time T3 (<FIG>). Similarly, in response to the second Read command, a second <NUM>-byte portion of the requested data may arrive from the DRAM on the second pseudo-channel 114B (PC1), i.e., DQ[<NUM>:<NUM>], after another delay or time interval beginning at time T7 (<FIG>). Then, again in response to the first Read command, a third <NUM>-byte portion of the requested data may arrive from the DRAM on the first pseudo-channel 114A (PC0), i.e., DQ[<NUM>:<NUM>]. And again in response to the second Read command, a fourth <NUM>-byte portion of the requested data may arrive from the DRAM on the second first pseudo-channel 114B (PC1), i.e., DQ[<NUM>:<NUM>]. That is, a first <NUM> bytes of the requested data arrive on DQ[<NUM>:<NUM>] and a second <NUM> bytes of the requested data arrive on DQ [<NUM>:<NUM>]. The delay or time interval from the first Read command to the arrival of <NUM> bytes of the requested data on DQ[<NUM>:<NUM>] in this example is RL +12nCK. Likewise, the delay or time interval from the second Read command to the arrival of <NUM> bytes of the requested data on DQ[<NUM>:<NUM>] in this example is RL +12nCK. Although not shown in the timing diagram <NUM>, the memory controller <NUM> then conveys the requested data back to the requesting client device.

It should be understood that the examples of operation of the system <NUM> (<FIG>) described above with regard to the timing diagrams <NUM> (<FIG>), <NUM> (<FIG>) and <NUM> (<FIG>) are not the only examples. Additional examples of operation of the system <NUM> will occur readily to one of ordinary skill in the art in view of the teachings herein. For example, while the above-described examples of operation of the system <NUM> relate to read accesses, there may be additional examples that relate to write accesses. Also, it should be understood that while the timing diagrams <NUM>-<NUM> illustrate some significant aspects of operation of the system <NUM>, there may be other aspects that are not illustrated in the timing diagrams <NUM>-<NUM>, such as aspects that are well understood by one of ordinary skill in the art. For example, as understood by one of ordinary skill in the art, there may be various other commands that the memory controller may issue in association with a DRAM access sequence, such as Activate ("ACT"), Pre-charge ("PRE"), etc..

In <FIG>, a method <NUM> for reading data from a DRAM is illustrated in flow diagram form. As indicated by block <NUM>, a memory controller may provide a Read command having a selectable PCB mode indication to a DRAM. The first Read command is associated with a request for data (e.g., by a client device). As indicated by block <NUM>, in response to the Read command, when the state of the PCB mode indication indicates the broadcast mode the memory controller may concurrently receive first and second portions of the requested data from the DRAM via first and second pseudo-channels, respectively. As indicated by block <NUM>, in response to the Read command, when the state of the PCB mode indication indicates the non-broadcast mode, the memory controller may receive the requested data from the DRAM via a selected one of the first and second pseudo-channels. The Read command may include a PCS indication, indicating which of the first and second pseudo-channels is selected.

In <FIG>, a method <NUM> for controlling memory access requests is illustrated in flow diagram form. As indicated by block <NUM>, a memory controller may receive a memory access request from a client device. The memory access request may include a target address and may also include other information, such as, for example, a flag, access priority indication, etc..

As indicated by block <NUM>, the memory controller may determine whether a received memory access request is associated with the broadcast mode. Whether the memory access request is associated with the broadcast mode may be determined in any way. In an exemplary embodiment, a memory access request having a target address within a first range may be associated with the broadcast mode. That is, if the target address is within the first range, then the memory access request is associated with the broadcast mode. But if the target address is not within the first range, then the memory access request is not associated with the broadcast mode (and thus may be associated with the non-broadcast mode). Different types of client devices may issue memory access requests having target addresses within different address ranges based on client type. For example, a CPU may use target addresses within a first range, while a GPU may use target addresses within a range other than the first range (i.e., a second range), etc. In another exemplary embodiment, a memory access request may include a flag. If the memory access request includes the flag, then the memory access request is associated with the broadcast mode. But if the memory access request does not include the flag, then the memory access request is not associated with the broadcast mode (and thus may be associated with the non-broadcast mode). Different client devices may include or not include the flag in their memory access requests. In still another exemplary embodiment, whether a memory access request is associated with the broadcast mode may be determined based on a memory access priority associated with the requesting client device.

As indicated by block <NUM>, if the memory controller determines that the memory access request is associated with the broadcast mode, then the memory controller may set the PCB mode indication (e.g., to "<NUM>") to indicate the broadcast mode in any of various commands the memory controller may issue in association with the memory access request. Such commands may include, for example, activate ("ACT"), write ("WRITE"), read ("READ"), pre-charge ("PRE"), etc. As indicated by block <NUM>, if the memory controller determines that the memory access request is not associated with the broadcast mode, then the memory controller may set the PCB mode indication (e.g., to "<NUM>") to indicate the non-broadcast mode in any of such commands. As indicated by block <NUM>, the memory controller may cause the memory access operations to be executed through a physical interface or PHY coupled to the DRAM by a memory bus.

As illustrated in <FIG>, a memory controller <NUM> may include a first DRAM read data first-in-first-out ("FIFO") buffer <NUM>, a second DRAM read data FIFO buffer <NUM>, a first interleave storage buffer <NUM>, a second interleave storage buffer <NUM>, a data handler <NUM>, a client read data buffer <NUM>, a DRAM command queue <NUM>, a read data pending command queue <NUM>, and a client Read command buffer <NUM>. The memory controller <NUM> may be an example of the above-described memory controller <NUM> (<FIG>). It should be understood that the memory controller <NUM> is shown in conceptual form in <FIG>, and the foregoing elements may be configured in operation by control logic (not shown), such as, for example, through operation of one or more processors (as configured by software or firmware), through operation of one or more finite state machines, or through operation of any other type of control logic. Also not shown in <FIG> are elements of the memory controller <NUM> relating to memory controller functions other than those described herein. For example, in addition to the memory controller functions described herein, the memory controller <NUM> may be configured to generate command sequences in response to the memory access requests received from client devices or in response to other conditions. Such other conditions may include, for example, a requirement of the DRAM to be periodically refreshed, and the memory controller <NUM> may be configured to generate refresh-related commands.

The DRAM command queue <NUM> may be configured to temporarily store commands generated in the manner described above before sending the commands on to the DRAM via the PHY (not shown in <FIG>). The read data pending command queue <NUM> may be configured to temporarily store information identifying each Read command sent to the DRAM until the memory controller <NUM> receives the read data from the DRAM in response to that Read command. The first DRAM FIFO buffer <NUM> may be configured to store read data received from the DRAM through the first pseudo-channel PC0. The second DRAM read data FIFO buffer <NUM> may be configured to store read data received from the DRAM through the second pseudo-channel PC1.

In an example of operation in which each of two successive Read commands requests <NUM> bytes of data, the first DRAM read data FIFO buffer <NUM> and the second DRAM read data FIFO buffer <NUM> each may be configured to receive <NUM> bits of read data from the PHY in response to each Read command. The first DRAM read data FIFO buffer <NUM> and the second DRAM read data FIFO buffer <NUM> each may be configured to receive <NUM> bits of read data in two memory controller clock cycles. The first and second interleave storage buffers <NUM> and <NUM> may be configured to store data that is output by the first and second DRAM read data FIFO buffers <NUM> and <NUM>, respectively. In this example (of <NUM>-byte requests), during a first memory controller clock cycle, the first interleave storage buffer <NUM> may send <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM> via the data handler <NUM>. In this example, during a second memory controller clock cycle, the first interleave storage buffer <NUM> may send another <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM> via the data handler <NUM>. Also, in this example, during a third memory controller clock cycle, the second interleave storage buffer <NUM> may send <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM> via the data handler <NUM>. Further, in this example, during a fourth memory controller clock cycle, the second interleave storage buffer <NUM> may send another <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM> via the data handler <NUM>. Thus, in this example (of <NUM>-byte requests), in the first two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the first pseudo-channel PC0, and in the next two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the second pseudo-channel PC1. That is, in an example in which the data is received in response to <NUM>-byte requests, in four memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of read data from each of the first and second pseudo-channels PC0 and PC1.

As read data is stored in the client read data buffer <NUM>, the read data pending command queue <NUM> may provide information identifying the Read commands associated with that read data to the client Read command buffer <NUM>. The client read data buffer <NUM> and the client Read command buffer <NUM> are configured to send the received read data along with the information identifying the associated commands to the requesting client. Each read access request received from a client may include information, which may be referred to as a "client ID," identifying the requesting client. Based on the client ID, the read data and information identifying the commands may be sent together or otherwise in association with each other to the requesting client. As described above, each command includes a PCB mode indication, indicating whether the DRAM is to provide the requested data to the memory controller <NUM> in broadcast mode or in non-broadcast mode. The read data pending command queue <NUM> may use the PCB mode indications to control the interleave storage buffers <NUM> and <NUM>.

In another example of operation, in which a Read command requests <NUM> bytes of data, the first DRAM read data FIFO buffer <NUM> and the second DRAM read data FIFO buffer <NUM> each may be configured to receive <NUM> bits of read data from the PHY in response to each Read command, as in the <NUM>-byte request example described above. The first DRAM read data FIFO buffer <NUM> and the second DRAM read data FIFO buffer <NUM> each may be configured to receive <NUM> bits of read data in two memory controller clock cycles, as in the <NUM>-byte request example described above. However, in this example (of <NUM>-byte requests): during a first memory controller clock cycle, the first interleave storage buffer <NUM> may send <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM>; during a second memory controller clock cycle, the first interleave storage buffer <NUM> may send another <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM>; during a third memory controller clock cycle, the second interleave storage buffer <NUM> may send <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM>; during a fourth memory controller clock cycle, the second interleave storage buffer <NUM> may send another <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM> via the data handler <NUM>; during a fifth memory controller clock cycle, the first interleave storage buffer <NUM> may send still another <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM>; during a sixth memory controller clock cycle, the first interleave storage buffer <NUM> may send yet another <NUM> bits of data received from the DRAM on the first pseudo-channel PC0 to the client read data buffer <NUM>; during a seventh memory controller clock cycle, the second interleave storage buffer <NUM> may send still another <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM>; and during an eighth memory controller clock cycle, the second interleave storage buffer <NUM> may send yet another <NUM> bits of data received from the DRAM on the second pseudo-channel PC1 to the client read data buffer <NUM>.

Thus, in this example (of <NUM>-byte requests): in the first two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the first pseudo-channel PC0; in the next two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the second pseudo-channel PC1; in the next two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the first pseudo-channel PC0; and in the next two memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of data received from the DRAM on the second pseudo-channel PC1. That is, in an example in which the data is received in response to a <NUM>-byte request, in eight memory controller clock cycles the client read data buffer <NUM> receives <NUM> bytes of read data from each of the first and second pseudo-channels PC0 and PC1.

In <FIG>, an example of a portable computing device ("PCD") <NUM> in which exemplary embodiments of systems, methods, computer-readable media, and other examples in which accessing data in a DRAM may be provided is illustrated. For purposes of clarity, some data buses, clock signals, power supply voltages, etc., are not shown in <FIG>.

The PCD <NUM> may include an SoC <NUM>. The SoC <NUM> may include a CPU <NUM>, an NPU <NUM>, a GPU <NUM>, a DSP <NUM>, an analog signal processor <NUM>, or other processors. The CPU <NUM> may include one or more CPU cores, such as a first CPU core 804A, a second CPU core 804B, etc., through an Nth CPU core 804N.

A display controller <NUM> and a touch-screen controller <NUM> may be coupled to the CPU <NUM>. A touchscreen display <NUM> external to the SoC <NUM> may be coupled to the display controller <NUM> and the touch-screen controller <NUM>. The PCD <NUM> may further include a video decoder <NUM> coupled to the CPU <NUM>. A video amplifier <NUM> may be coupled to the video decoder <NUM> and the touchscreen display <NUM>. A video port <NUM> may be coupled to the video amplifier <NUM>. A universal serial bus ("USB") controller <NUM> may also be coupled to CPU <NUM>, and a USB port <NUM> may be coupled to the USB controller <NUM>. A subscriber identity module ("SIM") card <NUM> may also be coupled to the CPU <NUM>.

One or more memories may be coupled to the CPU <NUM>. The one or more memories may include both volatile and non-volatile memories. Examples of volatile memories include static random access memory ("SRAM") <NUM> and DRAM <NUM> and <NUM>. Such memories may be external to the SoC <NUM>, such as the DRAM <NUM>, or internal to the SoC <NUM>, such as the DRAM <NUM>. A DRAM controller <NUM> coupled to the CPU <NUM> may control the writing of data to, and reading of data from, the DRAMs <NUM> and <NUM>. The DRAM controller <NUM> may be an example of the above-described DRAM controller <NUM> (<FIG>) or <NUM> (<FIG>).

A stereo audio CODEC <NUM> may be coupled to the analog signal processor <NUM>. Further, an audio amplifier <NUM> may be coupled to the stereo audio CODEC <NUM>. First and second stereo speakers <NUM> and <NUM>, respectively, may be coupled to the audio amplifier <NUM>. In addition, a microphone amplifier <NUM> may be coupled to the stereo audio CODEC <NUM>, and a microphone <NUM> may be coupled to the microphone amplifier <NUM>. A frequency modulation ("FM") radio tuner <NUM> may be coupled to the stereo audio CODEC <NUM>. An FM antenna <NUM> may be coupled to the FM radio tuner <NUM>. Further, stereo headphones <NUM> may be coupled to the stereo audio CODEC <NUM>. Other devices that may be coupled to the CPU <NUM> include one or more digital (e.g., CCD or CMOS) cameras <NUM>.

A modem or RF transceiver <NUM> may be coupled to the analog signal processor <NUM> and the CPU <NUM>. An RF switch <NUM> may be coupled to the RF transceiver <NUM> and an RF antenna <NUM>. In addition, a keypad <NUM>, a mono headset with a microphone <NUM>, and a vibrator device <NUM> may be coupled to the analog signal processor <NUM>.

The SoC <NUM> may have one or more internal or on-chip thermal sensors 870A and may be coupled to one or more external or off-chip thermal sensors 870B. An analog-to-digital converter ("ADC") controller <NUM> may convert voltage drops produced by the thermal sensors 870A and 870B to digital signals. A power supply <NUM> and a PMIC <NUM> may supply power to the SoC <NUM>.

The PCD <NUM> is only one example of a device or system in which exemplary embodiments of systems, methods, computer-readable media, and other embodiments of accessing data in a DRAM may be provided. Other examples may include other types of computing devices or computing systems, such as those used in datacenter, automotive, and other contexts.

Firmware or software may be stored in any of the above-described memories, such as DRAM <NUM> or <NUM>, SRAM <NUM>, etc., or may be stored in a local memory directly accessible by the processor hardware on which the software or firmware executes. Execution of such firmware or software may control aspects of any of the above-described methods or configure aspects any of the above-described systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as the term is understood in the patent lexicon.

In <FIG>, a table <NUM> illustrates that a memory controller may employ different memory access schemes based on client device type. For example, a memory controller may employ a broadcast memory access scheme shown in the first column of the table <NUM> in response to read requests received from latency-sensitive clients, and may employ a non-broadcast memory access scheme shown in the second column of the table <NUM> in response to read requests received from bandwidth-sensitive clients. Examples of latency-sensitive clients may include a CPU, a modem, or similar clients. Examples of memory bandwidth-sensitive clients may include a GPU, an NPU, or similar clients.

As indicated in the first column of the table <NUM>, when a broadcast memory access scheme is employed, the memory controller may access the DRAM in a manner as though the DRAM were organized in the form of eight bank groups of two banks each. The latency for accessing <NUM> bytes of data using a broadcast memory access scheme is RL+4nCK. The latency for accessing <NUM> bytes of data using a broadcast memory access scheme (i.e., with BL=<NUM>) is also RL+4nCK. The latency for accessing <NUM> bytes of data using a broadcast memory access scheme (with BL=<NUM>) is RL+12nCK.

Claim 1:
A method (<NUM>) for accessing data in a dynamic random access memory, DRAM, (<NUM>) comprising:
providing (<NUM>) to the DRAM, by a memory controller (<NUM>), a command having a selectable channel broadcast mode indication, the command associated with requested data;
concurrently accessing (<NUM>), by the memory controller, a first portion of the requested data in the DRAM via a first channel (114A) and a second portion of the requested data in the DRAM via a second channel (114B) in response to the command when a state of the channel broadcast mode indication indicates a broadcast mode; and
accessing (<NUM>), by the memory controller, the requested data in the DRAM via a selected one of the first and second channels in response to the command when the state of the channel broadcast mode indication indicates a non-broadcast mode.