Patent Description:
Embodiments of the present disclosure relate to semiconductor devices and fabrication and operation methods thereof.

<CIT> discloses a memory device, comprising:.

<CIT> discloses three-dimensional (3D) memory with an array and control circuitry in separately processed and bonded wafers. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells.

<CIT> discloses structures and methods for testing three-dimensional (3D) memory devices. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.

Flash memory controllers (also known as Flash controllers) manage the data stored in Flash memory and communicate with a computer and/or electronic device. Flash memory controllers can provide various control functions to prevent a heavier burden on the host processor. Currently, there are two types of Flash memory controllers available for Flash memory devices. The first option is a discrete Flash controller, which is an individual chip to communicate with the host processor and NAND Flash memory chip through system buses. The other option is an integrated Flash controller in the same package with the NAND Flash memory chip, which, however, still requires a separate Flash controller chip connected to the NAND Flash memory chip through wire bonding.

Embodiments of bonded memory devices having a Flash memory controller and fabrication and operation methods thereof are disclosed herein.

Embodiments in accordance with the claimed invention are defined in the appended claims.

In one example, a memory device includes a first semiconductor structure including a Flash memory controller, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts. The memory device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. Further features of the memory device are defined in Claim <NUM>.

In another example, a method for forming the memory device is disclosed.

In still another example, a method for operating the memory device is disclosed.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> illustrate embodiments in accordance with the claimed invention.

All other figures illustrate examples not falling within the scope of the claims but useful for the understanding thereof.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only.

Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow.

As used herein, the term "3D NAND memory string" refers to a vertically-oriented string of memory cell transistors connected in series on a laterally-oriented substrate so that the string of memory cell transistors extends in the vertical direction with respect to the substrate.

For existing NAND Flash memory, the Flash memory controller is either a discrete chip on the circuit board (e.g., PCB) or integrated into the same package with the NAND memory chip but still as a separate chip. However, the Flash controller on the PCB occupies additional PCB space and uses relatively slow data buses between the NAND memory chip and the host processor. As to the integrated Flash controller, additional cost is added to the device for adding the Flash controller chip, and extra space is required in the package. Moreover, data communication between the Flash controller chip and the NAND memory chip is also relatively slow through wire bonding.

Various embodiments in accordance with the present disclosure provide a memory device integrating a Flash memory controller and NAND memory into a single bonded chip, with improved bidirectional data processing and transfer throughput between the Flash memory controller and the NAND memory within the same chip, thereby achieving overall faster system speed, while reducing PCB footprint at the same time. In some embodiments, the peripheral circuit of the NAND memory is formed on the same substrate with the Flash memory controller. The NAND memory cell array (either 2D or 3D) can be formed on another substrate and then bonded to the substrate on which the Flash controller is formed.

<FIG> illustrates a schematic view of a cross-section of an exemplary memory device <NUM>, according to some embodiments. Memory device <NUM> represents an example of a bonded chip. The components of memory device <NUM> (e.g., Flash memory controller/peripheral circuit and NAND memory) are formed separately on different substrates and then joined to form a bonded chip. Memory device <NUM> includes a first semiconductor structure <NUM> having a Flash memory controller and a peripheral circuit of the NAND memory. In some embodiments, the Flash memory controller and the peripheral circuit in first semiconductor structure <NUM> use complementary metal-oxide-semiconductor (CMOS) technology. Both the Flash memory controller and the peripheral circuit can be implemented with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) to achieve high speed.

The Flash memory controller manages the data stored in NAND Flash memory and communicates with a host (e.g., a processor of a computing device or any other electronic devices). In some embodiments, the Flash memory controller is designed for operating in a low duty-cycle environment like Secure Digital (SD) cards, Compact Flash (CF) cards, USB Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the Flash memory controller is designed for operating in a high duty-cycle environment like solid-state drives (SSDs) or embedded MultiMedia-Cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The Flash memory controller is configured to control operations of Flash memory (i.e. the NAND memory in <FIG>), such as read, write, erase, and program operations. The Flash memory controller can also be configured to manage various functions with respect to the data stored or to be stored in the Flash memory including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, and so on. In some embodiments, the Flash memory controller is further configured to process error correction codes (ECCs) with respect to the data read from or written to the Flash memory. Any other suitable functions may be performed by the Flash memory controller as well, for example, formatting the Flash memory.

The peripheral circuit (also known as the control and sensing circuits) can include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the NAND memory. For example, the peripheral circuit can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). According to the claimed invention the peripheral circuit includes one or more page buffers and word line drivers.

Memory device <NUM> also includes a second semiconductor structure <NUM> including the NAND memory having an array of NAND memory cells. That is, second semiconductor structure <NUM> is a NAND Flash memory in which memory cells are provided in the form of an array of 3D NAND memory strings and/or an array of 2D NAND memory cells. NAND memory cells can be organized into pages which are then organized into blocks, in which each NAND memory cell is electrically connected to a separate line called a bit line (BL). All cells with the same position in the NAND memory cell can be electrically connected through the control gates by a word line (WL). In some embodiments, a plane contains a certain number of blocks that are electrically connected through the same bit line. Second semiconductor structure <NUM> can include one or more planes, and the peripheral circuit that is needed to perform all the read/write/erase/program operations can be included in the first semiconductor structure <NUM> as described above.

In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating-gate transistor. The array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (e.g., <NUM> to <NUM> memory cells) connected in series (resembling a NAND gate) and two select transistors, according to some embodiments. Each 2D NAND memory string is arranged in the same plane on the substrate (in 2D), according to some embodiments. In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically above the substrate (in 3D) through a memory stack. Depending on the 3D NAND technology (e.g., the number of layers/tiers in the memory stack), a 3D NAND memory string typically includes <NUM> to <NUM> NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

As shown in <FIG>, memory device <NUM> further includes a bonding interface <NUM> vertically between a first semiconductor structure <NUM> and a second semiconductor structure <NUM>. As described below in details, the first and second semiconductor structures <NUM> and <NUM> can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of the first and second semiconductor structures <NUM> and <NUM> does not limit the processes of fabricating another one of the first and second semiconductor structures <NUM> and <NUM>. Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through bonding interface <NUM> to make direct, short electrical connections between first semiconductor structure <NUM> and second semiconductor structure <NUM>, as opposed to the long-distance chip-to-chip data bus on the circuit board (e.g., Printed Circuit Board (PCB)), thereby avoiding chip interface delay and achieving high-speed In/Out (I/O) throughput with reduced power consumption. Data transfer between the NAND memory in second semiconductor structure <NUM> and the Flash memory controller in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>. By vertically integrating first and second semiconductor structures <NUM> and <NUM>, the chip size can be reduced, and the memory cell density can be increased. Furthermore, by integrating multiple discrete chips (e.g., Flash memory controller and NAND memory) into a single bonded chip (e.g., memory device <NUM>), faster system speed and smaller PCB size can be achieved as well.

It is understood that the relative positions of stacked first and second semiconductor structures <NUM> and <NUM> are not limited. <FIG> illustrates a schematic view of a cross-section of another exemplary memory device <NUM>, according to some embodiments. Different from memory device <NUM> in <FIG> in which second semiconductor structure <NUM> including the array of NAND memory cells is above first semiconductor structure <NUM> including the Flash memory controller and the peripheral circuit, in memory device <NUM> in <FIG>, first semiconductor structure <NUM> including the Flash memory controller and the peripheral circuit is above second semiconductor structure <NUM> including the array of NAND memory cells. Nevertheless, bonding interface <NUM> is formed vertically between first and second semiconductor structures <NUM> and <NUM> in memory device <NUM>, and first and second semiconductor structures <NUM> and <NUM> are jointed vertically through bonding (e.g., hybrid bonding) according to some embodiments. Data transfer between the NAND memory in second semiconductor structure <NUM> and the Flash memory controller in first semiconductor structure <NUM> are performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having a Flash memory controller <NUM>, according to some embodiments. Semiconductor structure <NUM> may be one example of first semiconductor structure <NUM>. Semiconductor structure <NUM> includes the peripheral circuit for controlling and sensing NAND memory, including word line drivers <NUM>, page buffers <NUM>, and any other suitable devices. Semiconductor structure <NUM> can further include Flash memory controller <NUM> on the same substrate as the peripheral circuit and fabricated using the same logic process as the peripheral circuit. <FIG> shows an exemplary layout of the peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>) and Flash memory controller <NUM> in which peripheral circuit and Flash memory controller <NUM> are formed in different regions on the same plane. For example, the peripheral circuit may be formed outside of Flash memory controller <NUM>. It is understood that the layout of semiconductor structure <NUM> is not limited to the exemplary layout in <FIG>. According to the claimed invention, the peripheral circuit, and Flash memory controller <NUM> are stacked one over another, i.e. in different planes. Flash memory controller <NUM> is formed above or below the peripheral circuit to further reduce the chip size and therefore increase memory cell density.

<FIG> illustrates a cross-section of an exemplary memory device <NUM> having 3D NAND memory, according to some embodiments. As one example of memory device <NUM> described above with respect to <FIG>, memory device <NUM> is a bonded chip including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are jointed at a bonding interface <NUM> therebetween, according to some embodiments. As shown in <FIG>, first semiconductor structure <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of memory device <NUM> can include a device layer <NUM> above substrate <NUM>. It is noted that x- and y-axes are added in <FIG> to further illustrate the spatial relationship of the components in memory device <NUM>. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., memory devices <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

In some embodiments, device layer <NUM> includes a Flash memory controller <NUM> on substrate <NUM> and a peripheral circuit <NUM> on substrate <NUM> and outside of Flash memory controller <NUM>. In some embodiments, Flash memory controller <NUM> includes a plurality of logic transistors <NUM> forming any suitable components thereof as described below in details. In some embodiments, logic transistors <NUM> further form peripheral circuit <NUM>, e.g., any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of the 3D NAND memory including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference. Logic transistors <NUM> can be formed "on" substrate <NUM>, in which the entirety or part of logic transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of logic transistors <NUM>) can be formed in substrate <NUM> as well. Logic transistors <NUM> are high-speed logic transistors with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments.

In accordance with the claimed invention, first semiconductor structure <NUM> of memory device <NUM> further includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from Flash memory controller <NUM> and peripheral circuit <NUM>. Interconnect layer <NUM> includes a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer <NUM> can further include one or more inter-layer dielectric (ILD) layers (also known as "inter-metal dielectric (IMD) layers" for BEOL) in which the interconnect lines and via contacts can form. That is, interconnect layer <NUM> can include interconnect lines and via contacts in multiple interlayer dielectric (ILD) layers. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

In accordance with the claimed invention, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. Peripheral circuit <NUM> is electrically connected to Flash memory controller <NUM> through interconnect layer <NUM>.

As shown in <FIG>, first semiconductor structure <NUM> of memory device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM> (Flash memory controller <NUM> and peripheral circuit <NUM>). Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> also includes a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

As described above, second semiconductor structure <NUM> can be bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. According to the invention, bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. According to the claimed invention, bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

According to the claimed invention, second semiconductor structure <NUM> of memory device <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, second semiconductor structure <NUM> of memory device <NUM> includes a NAND Flash memory in which memory cells are provided in the form of an array of 3D NAND memory strings <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Each 3D NAND memory string <NUM> extends vertically through a plurality of pairs each including a conductor layer <NUM> and a dielectric layer <NUM>, according to some embodiments. The stacked and interleaved conductor layers <NUM> and dielectric layer <NUM> are also referred to herein as a memory stack <NUM>. Interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> alternate in the vertical direction, according to some embodiments. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductor layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductor layers <NUM> on both sides. Conductor layers <NUM> can each have the same thickness or different thicknesses. Similarly, dielectric layers <NUM> can each have the same thickness or different thicknesses. Conductor layers <NUM> can include conductor materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, each 3D NAND memory string <NUM> is a "charge trap" type of NAND memory string including a semiconductor channel <NUM> and a memory film <NUM>. In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite dielectric layer including a tunneling layer, a storage layer (also known as "charge trap/storage layer"), and a blocking layer. Each 3D NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). Semiconductor channel <NUM>, the tunneling layer, the storage layer, and the blocking layer of memory film <NUM> are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the blocking layer can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In another example, the blocking layer can include a high-k dielectric layer, such as aluminum oxide (Al<NUM>O<NUM>), hafnium oxide (HfO<NUM>) or tantalum oxide (Ta<NUM>O<NUM>) layer, and so on.

In some embodiments, 3D NAND memory strings <NUM> further include a plurality of control gates (each being part of a word line). Each conductor layer <NUM> in memory stack <NUM> can act as a control gate for each memory cell of 3D NAND memory string <NUM>. In some embodiments, each 3D NAND memory string <NUM> includes two plugs <NUM> and <NUM> at respective end in the vertical direction. Plug <NUM> can include a semiconductor material, such as single-crystal silicon, that is epitaxially grown from a semiconductor layer <NUM>. Plug <NUM> can function as the channel controlled by a source select gate of 3D NAND memory string <NUM>. Plug <NUM> can be at the upper end of 3D NAND memory string <NUM> and in contact with semiconductor channel <NUM>. As used herein, the "upper end" of a component (e.g., 3D NAND memory string <NUM>) is the end father away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., 3D NAND memory string <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of memory device <NUM>. Another Plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductor materials (e.g., metals). In some embodiments, plug <NUM> includes an opening filled with titanium/titanium nitride (Ti/TiN, as a glue layer) and tungsten (as a conductor). By covering the upper end of 3D NAND memory string <NUM> during the fabrication of second semiconductor structure <NUM>, plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in 3D NAND memory string <NUM>, such as silicon oxide and silicon nitride. In some embodiments, plug <NUM> functions as the drain of 3D NAND memory string <NUM>.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above memory stack <NUM> and 3D NAND memory strings <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which memory stack <NUM> and 3D NAND memory strings <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon from which plugs <NUM> can be epitaxially grown. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, Salicide, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., functioning as an array common source (ACS) for 3D NAND memory strings <NUM>, not shown). Isolation regions (not shown) can extend across the entire thickness or part of the thickness of semiconductor layer <NUM> to electrically isolate the doped regions. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and semiconductor layer <NUM>.

It is understood that 3D NAND memory strings <NUM> are not limited to the "charge trap" type of 3D NAND memory strings and may be "floating gate" type of 3D NAND memory strings in other embodiments. Semiconductor layer <NUM> may include polysilicon as the source plate of the "floating gate" type of 3D NAND memory strings.

As shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. Pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between memory device <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, Flash memory controller <NUM> can be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Peripheral circuit <NUM> is also electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, Flash memory controller <NUM>, peripheral circuit <NUM>, and array of 3D NAND memory strings <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of an exemplary memory device <NUM> having 2D NAND memory, according to some embodiments. Similar to memory device <NUM> described above in <FIG>, memory device <NUM> represents an example of a bonded chip including first semiconductor structure <NUM> having Flash memory controller <NUM> and peripheral circuit <NUM>. Different from memory device <NUM> described above in <FIG> that includes second semiconductor structure <NUM> having 3D NAND memory strings <NUM>, memory device <NUM> in <FIG> includes a second semiconductor structure <NUM> having 2D NAND memory cells <NUM>. Similar to memory device <NUM> described above in <FIG>, first and second semiconductor structures <NUM> and <NUM> of memory device <NUM> are bonded in a face-to-face manner at bonding interface <NUM>, as shown in <FIG>. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both memory devices <NUM> and <NUM> may not be repeated below.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> also includes a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> are used for hybrid bonding. According to the claimed invention, second semiconductor structure <NUM> of memory device <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form.

In some embodiments, second semiconductor structure <NUM> of memory device <NUM> includes a NAND Flash memory in which memory cells are provided in the form of an array of 2D NAND memory cells <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Array of 2D NAND memory cells <NUM> can include a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells <NUM> connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. In some embodiments, each 2D NAND memory string further includes one or more select gates and/or dummy gates besides select transistors <NUM>. In some embodiments, each 2D NAND memory cell <NUM> includes a floating-gate transistor having a floating gate <NUM> and a control gate <NUM> stacked vertically. Floating gate <NUM> can include semiconductor materials, such as polysilicon. Control gate <NUM> can be part of the word line of the NAND Flash memory device and include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In some embodiments, the floating-gate transistor further includes dielectric layers, such as a blocking layer disposed vertically between control gate <NUM> and floating gate <NUM> and a tunneling layer disposed above floating gate <NUM>. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. The tunneling layer can include silicon oxide, silicon oxynitride, or a combination thereof. Channels can be formed laterally between sources/drains <NUM> and above the gate stacks (including the tunneling layer, floating gate <NUM>, the blocking layer, and control gate <NUM>). Each channel is controlled by the voltage signal applied to the corresponding gate stack through control gate <NUM>, according to some embodiments. It is understood that 2D NAND memory cell <NUM> may include a charge-trap transistor, which replaces floating gate <NUM> with a storage layer as described above in details. In some embodiments, the storage layer includes silicon nitride, silicon oxynitride, or any combination thereof and has a thickness smaller than that of floating gate <NUM>.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above and in contact with array of 2D NAND memory cells <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which 2D NAND memory cells <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> includes polysilicon, amorphous silicon, SiGe, GaAs, Ge, Salicide, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., functioning as sources/drains <NUM> of 2D NAND memory cells <NUM>).

As shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> includes interconnects, e.g., contact pads <NUM>, in one or more ILD layers, according to some embodiments. Pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. The interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between memory device <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending vertically through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, Flash memory controller <NUM> can be electrically connected to 2D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Peripheral circuit <NUM> is electrically connected to 2D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, Flash memory controller <NUM>, peripheral circuit <NUM>, and 2D NAND memory cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of another exemplary memory device <NUM> having 3D NAND memory, according to some embodiments. Similar to memory device <NUM> described above in <FIG>, memory device <NUM> represents an example of a bonded chip in which a first semiconductor structure <NUM> including 3D NAND memory strings and a second semiconductor structure <NUM> including a Flash memory controller and a peripheral circuit of the 3D NAND memory strings are formed separately and bonded in a face-to-face manner at a bonding interface <NUM>. Different from memory device <NUM> described above in <FIG> in which first semiconductor structure <NUM> including the Flash memory controller and the peripheral circuit is below second semiconductor structure <NUM> including the 3D NAND memory strings, memory device <NUM> in <FIG> includes second semiconductor structure <NUM> including a Flash memory controller and a peripheral circuit disposed above first semiconductor structure <NUM> including 3D NAND memory strings. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both memory devices <NUM> and <NUM> may not be repeated below.

First semiconductor structure <NUM> of memory device <NUM> can include a substrate <NUM> and a memory stack <NUM> including interleaved conductor layers <NUM> and dielectric layers <NUM> above substrate <NUM>. In some embodiments, an array of 3D NAND memory cells <NUM> each extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> above substrate <NUM>. Each 3D NAND memory cell <NUM> can include a semiconductor channel layer <NUM> and a memory film <NUM>. Each 3D NAND memory cell <NUM> further includes two plugs <NUM> and <NUM> at its lower end and upper end, respectively. 3D NAND memory cells <NUM> can be "charge trap" type of 3D NAND memory strings or "floating gate" type of 3D NAND memory strings. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and substrate <NUM>.

In some embodiments, first semiconductor structure <NUM> of memory device <NUM> also includes an interconnect layer <NUM> above memory stack <NUM> and 3D NAND memory cells <NUM> to transfer electrical signals to and from 3D NAND memory cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, first semiconductor structure <NUM> of memory device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and memory stack <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

As shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> includes another bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>. In some embodiments, second semiconductor structure <NUM> of memory device <NUM> also includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts.

Second semiconductor structure <NUM> of memory device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. According to the claimed invention, device layer <NUM> includes a Flash memory controller <NUM> above interconnect layer <NUM> and bonding layer <NUM> and a peripheral circuit <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of Flash memory controller <NUM>.

According to the claimed invention, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. Peripheral circuit <NUM> is electrically connected to Flash memory controller <NUM> through interconnect layer <NUM>. In some embodiments, Flash memory controller <NUM> includes a plurality of logic transistors <NUM> forming any suitable components thereof as described below in detail. Device layer <NUM> can also include peripheral circuit <NUM> of the 3D NAND memory formed by logic transistors <NUM> as described above in detail. Logic transistors <NUM> can be formed "on" a semiconductor layer <NUM>, in which the entirety or part of logic transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of logic transistors <NUM>) can be formed in semiconductor layer <NUM> as well.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which logic transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, Salicide, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions.

As shown in <FIG>, second semiconductor structure <NUM> of memory device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between memory device <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, Flash memory controller <NUM> can be electrically connected to array of 3D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Peripheral circuit <NUM> is electrically connected to array of 3D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, Flash memory controller <NUM>, peripheral circuit <NUM>, and array of 3D NAND memory cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of another exemplary memory device <NUM> having 2D NAND memory, according to some embodiments. Similar to memory device <NUM> described above in <FIG>, memory device <NUM> represents an example of a bonded chip including second semiconductor structure <NUM> having Flash memory controller <NUM> and peripheral circuit <NUM>. Different from memory device <NUM> described above in <FIG> that includes first semiconductor structure <NUM> having 3D NAND memory cells <NUM>, memory device <NUM> in <FIG> includes a first semiconductor structure <NUM> having 2D NAND memory cells <NUM>. Similar to memory device <NUM> described above in <FIG>, first and second semiconductor structures <NUM> and <NUM> of memory device <NUM> are bonded in a face-to-face manner at bonding interface <NUM>, as shown in <FIG>. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both memory devices <NUM> and <NUM> may not be repeated below.

In some embodiments, first semiconductor structure <NUM> of memory device <NUM> includes a NAND Flash memory in which memory cells are provided in the form of an array of 2D NAND memory cells <NUM> on substrate <NUM>. Array of 2D NAND memory cells <NUM> can include a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. In some embodiments, each 2D NAND memory cell <NUM> includes a floating-gate transistor having a floating gate <NUM> and a control gate <NUM> stacked vertically. In some embodiments, the floating-gate transistor further includes dielectric layers, such as a blocking layer disposed vertically between control gate <NUM> and floating gate <NUM> and a tunneling layer disposed below floating gate <NUM>. Channels can be formed laterally between sources/drains <NUM> and below the gate stacks (including the tunneling layer, floating gate <NUM>, the blocking layer, and control gate <NUM>). Each channel is controlled by the voltage signal applied to the corresponding gate stack through control gate <NUM>, according to some embodiments. It is understood that 2D NAND memory cell <NUM> may include a charge-trap transistor, which replaces floating gate <NUM> with a storage layer as described above in details.

In some embodiments, first semiconductor structure <NUM> of memory device <NUM> also includes an interconnect layer <NUM> above 2D NAND memory cells <NUM> to transfer electrical signals to and from 2D NAND memory cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, first semiconductor structure <NUM> of memory device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and 2D NAND memory cells <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

<FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having a Flash memory controller, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having 3D NAND memory strings, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary memory device, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for forming a memory device, according to some embodiments. Examples of the memory device depicted in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> include memory device <NUM> depicted in <FIG> and memory device <NUM> depicted in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

As depicted in <FIG>, a first semiconductor structure including a Flash memory controller, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts is formed. The Flash memory controller includes a host interface operatively coupled to a host processor, a NAND memory interface operatively coupled to the array of NAND memory cells, a management module, and an ECC module. As depicted in <FIG> and <FIG>, a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts is formed. The peripheral circuit includes one or more page buffers and word line drivers of the array of 3D NAND memory strings. As depicted in <FIG> and <FIG>, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which the Flash memory controller and the peripheral circuit are formed on a first substrate. The first substrate can be a silicon substrate. In some embodiments, to form the Flash memory controller and the peripheral circuit, a plurality of transistors are formed on the first substrate.

As illustrated in <FIG>, a plurality of logic transistors <NUM> are formed on a silicon substrate <NUM>. Logic transistors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of logic transistors <NUM>. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition. A device layer <NUM> including a Flash memory controller (having logic transistors <NUM>) and a peripheral circuit (having logic transistor <NUM>) is thereby formed. Logic transistors <NUM> can be patterned and made in different regions of device layer <NUM> to form the Flash memory controller and the peripheral circuit.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first interconnect layer is formed above the Flash memory controller and the peripheral circuit. The first interconnect layer can include a first plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> is formed above device layer <NUM> including the Flash memory controller and peripheral circuit (each having logic transistors <NUM>). Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with device layer <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. Fabrication processes to form interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first bonding layer is formed above the first interconnect layer. The first bonding layer includes a plurality of first bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack is formed above a second substrate. The second substrate can be a silicon substrate. As illustrated in <FIG>, interleaved sacrificial layers (not shown) and dielectric layers <NUM> are formed above a silicon substrate <NUM>. The interleaved sacrificial layers and dielectric layers <NUM> can form a dielectric stack (not shown). In some embodiments, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer <NUM> includes a layer of silicon oxide. The interleaved sacrificial layers and dielectric layers <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a memory stack <NUM> can be formed by a gate replacement process, e.g., replacing the sacrificial layers with conductor layers <NUM> using wet/dry etch of the sacrificial layers selective to dielectric layers <NUM> and filling the resulting recesses with conductor layers <NUM>. As a result, memory stack <NUM> can include interleaved conductor layers <NUM> and dielectric layers <NUM>. In some embodiments, each conductor layer <NUM> includes a metal layer, such as a layer of tungsten. It is understood that memory stack <NUM> may be formed by alternatingly depositing conductor layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without the gate replacement process in other embodiments. In some embodiments, a pad oxide layer including silicon oxide is formed between memory stack <NUM> and silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the array of 3D NAND memory strings extending vertically through the memory stack are formed. As illustrated in <FIG>, 3D NAND memory strings <NUM> are formed above silicon substrate <NUM>, each of which extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> include forming a channel hole through memory stack <NUM> and into silicon substrate <NUM> using dry etching/and or wet etching, such as deep reactive-ion etching (DRIE), followed by epitaxially growing a plug <NUM> in the lower portion of the channel hole from silicon substrate <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> also include subsequently filling the channel hole with a plurality of layers, such as a memory film <NUM> (e.g., a tunneling layer, a storage layer, and a blocking layer) and a semiconductor layer <NUM>, using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> further include forming another plug <NUM> in the upper portion of the channel hole by etching a recess at the upper end of 3D NAND memory string <NUM>, followed by filling the recess with a semiconductor material using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of 3D NAND memory strings. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above memory stack <NUM> and array of 3D NAND memory strings <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with 3D NAND memory strings <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer includes a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at the bonding interface. The bonding is hybrid bonding. In some embodiments, the first substrate on which the Flash memory controller and the peripheral circuit are formed (e.g., the first semiconductor structure) is disposed above the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) after the bonding. In some embodiments, the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) is disposed above the first substrate on which the Flash memory controller and the peripheral circuit are formed (e.g., the first semiconductor structure) after the bonding.

As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., 3D NAND memory strings <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., the Flash memory controller and peripheral circuit therein) can be electrically connected to 3D NAND memory strings <NUM>. It is understood that in the bonded chip, 3D NAND memory strings <NUM> may be either above or below device layer <NUM> (e.g., the Flash memory controller and peripheral circuit therein). Nevertheless, bonding interface <NUM> can be formed between 3D NAND memory strings <NUM> and device layer <NUM> (e.g., the Flash memory controller and peripheral circuit therein) after the bonding as illustrated in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate or the second substrate is thinned to form a semiconductor layer. In some embodiments, the first substrate of the first semiconductor structure, which is above the second substrate of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second substrate of the second semiconductor structure, which is above the first substrate of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer.

As illustrated in <FIG>, the substrate at the top of the bonded chip (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. The thickness of the thinned substrate can be between about <NUM> and about <NUM>, such as between <NUM> and <NUM>, or between about <NUM> and about <NUM>, such as between <NUM> and <NUM>. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. Pad contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example, by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

As described above, 2D NAND memory cells, instead of 3D NAND memory strings, may be formed on a separate substrate and bonded into the memory device. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having 2D NAND memory cells, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming another exemplary memory device, according to some embodiments. <FIG> is a flowchart of another exemplary method <NUM> for forming a memory device, according to some embodiments. Examples of the memory device depicted in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> include memory device <NUM> depicted in <FIG> and memory device <NUM> depicted in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an array of 2D NAND memory cells are formed on a second substrate. As illustrated in <FIG>, 2D NAND memory cells <NUM> are formed on silicon substrate <NUM> in the form of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. 2D NAND memory cells <NUM> and select transistors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as sources/drains <NUM>. In some embodiments, isolation regions (e.g., STIs, not shown) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition.

In some embodiments, a gate stack is formed for each 2D NAND memory cell <NUM>. The gate stack can include a tunneling layer, a floating gate <NUM>, a blocking layer, and a control gate <NUM> from bottom to top in this order for "floating gate" type of 2D NAND memory cells <NUM>. In some embodiments, floating gate <NUM> is replaced by a storage layer for "charge trap" type of 2D NAND memory cells. The tunneling layer, floating gate <NUM> (or storage layer), blocking layer, and control gate <NUM> of the gate stack can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of 2D NAND memory cells. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above array of 2D NAND memory cells <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with 2D NAND memory cells <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., 2D NAND memory cells <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., the Flash memory controller and peripheral circuit therein) can be electrically connected to 2D NAND memory cells <NUM>. It is understood that in the bonded chip, 2D NAND memory cells <NUM> may be either above or below device layer <NUM> (e.g., the Flash memory controller and peripheral circuit therein).

As illustrated in <FIG>, the substrate at the top of the bonded chip (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate <NUM>. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

As described above, in existing NAND Flash memory, the Flash memory controller and memory (e.g., NAND memory chip) are placed on the PCB as discrete chips, which communicate with each other through relatively long and slow interlinks (e.g., various data buses) on the PCB, thereby suffering from relatively low data throughput. Moreover, the large number of discrete chips occupy large PCB area. Conventionally, <FIG> illustrates a schematic diagram of a discrete host processor <NUM>, a Flash memory controller <NUM>, and NAND memory <NUM> on a PCB <NUM> and operations thereof. Each one of host processor <NUM>, Flash memory controller <NUM>, and NAND memory <NUM> is a discrete chip with its own package and mounted on PCB <NUM>. Host processor <NUM> is a specialized processor, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor. Data is transmitted between host processor <NUM> and Flash memory controller <NUM> through an interlink, such as a processor bus. NAND memory <NUM> is a 3D NAND memory or a 2D NAND memory, which transfers data with Flash memory controller <NUM> through another interlink.

In another conventional example (not shown), the chips of Flash memory controller <NUM> and NAND memory <NUM> may be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package, and electrically connected through wire bonding. Flash memory controller <NUM> then may transfer data with host processor <NUM> through an interlink, such as a processor bus, which is driven by a software driver, such as a UFS driver software or an MMC driver software.

<FIG> illustrates a schematic diagram of an exemplary memory device <NUM> having a Flash memory controller <NUM> on a PCB <NUM> and operations thereof, in accordance with the claimed invention. <FIG> illustrates a detailed schematic diagram of one example of Flash memory controller <NUM> in <FIG>, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for operating a memory device, according to some embodiments. Examples of the memory device depicted in <FIG> include memory device <NUM> depicted in <FIG> and <FIG>. <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>. As illustrated in <FIG>, memory device <NUM> includes Flash memory controller <NUM>, NAND memory <NUM> having an array of NAND memory cells, and a peripheral circuit <NUM> of NAND memory <NUM>. Flash memory controller <NUM>, NAND memory <NUM> (either a 3D NAND memory or a 2D NAND memory), and peripheral circuit <NUM> can be formed in the same bonded chip as described above in detail, such as memory device <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which an instruction is received by a Flash memory controller from a host processor. As illustrated in <FIG>, any suitable type of instruction generated by host processor <NUM> can be transferred to flash memory controller <NUM> of memory device <NUM>, for example, instructions for performing the read/ write/ erase or program operations on NAND memory <NUM>. As illustrated in <FIG>, Flash memory controller <NUM> includes a host interface (I/F) <NUM> operatively coupled to host processor <NUM>, for example, through a processor bus, and configured to receive the instruction from host processor <NUM>. Host I/F <NUM> can include a serial attached SCSI (SAS), parallel SCSI, PCI express (PCIe), NVM express (NVMe), advanced host controller interface (AHCI), to name a few.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which control signals are transmitted by the Flash memory controller to an array of NAND memory cells through a plurality of bonding contacts to control operations of the array of NAND memory cells based on the instruction. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which status signals indicative of the operations from the array of NAND memory cells are received by the Flash memory controller through the plurality of bonding contacts.

As illustrated in <FIG>, electrical signals (including data, control signals, and status signals) can be bidirectionally transferred between Flash memory controller <NUM> and NAND memory <NUM> through direct electrical connections by a plurality of bonding contacts (e.g., over millions of bonding contacts in parallel) as described above in detail, which have shortened distance, higher throughput, and lower power consumption compared with the conventional on-board chip-to-chip data bus, for example, shown in <FIG>. Similarly, electrical signals (including data, control signals, and status signals) can be bidirectionally transferred between peripheral circuit <NUM> and NAND memory <NUM> through direct electrical connections by the plurality of bonding contacts (e.g., over millions of bonding contacts in parallel). As illustrated in <FIG>, bidirectional transfer of electrical signals can be achieved between Flash memory controller <NUM> and peripheral circuit <NUM> as well through direct electrical connections by interconnects in the same chip.

As illustrated in <FIG>, Flash memory controller <NUM> also includes a management module <NUM> and a NAND memory interface (I/F) <NUM>. In some embodiments, management module <NUM> is operatively coupled to host I/F <NUM> and NAND memory I/F <NUM> and configured to generate one or more control signals to control operations (e.g., read, write, erase, and program operations) of NAND memory <NUM> based on the instruction received from host processor <NUM> and send the control signals to NAND memory I/F <NUM>. Management module <NUM> can be any suitable control and state machine. In some embodiments, NAND memory I/F <NUM> is configured to transmit the control signals to NAND memory <NUM> and receive the status signals from NAND memory <NUM>. The status signal can indicate the status of each operation performed by NAND memory <NUM> (e.g., failure, success, delay, etc.), which can be sent back to management module <NUM> as feedbacks. NAND memory I/F <NUM> can include single data rate (SDR) NAND Flash interface, open NAND Flash interface (ONFI), Toggle double data rate (DDR) interface, to name a few.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which data is stored in the array of NAND memory cells. As illustrated in <FIG>, data from host processor <NUM> can be stored in NAND memory <NUM> as controlled by Flash memory controller <NUM>, for example, by the write operations.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the an ECC with respect to the data is processed by the Flash memory controller. As illustrated in <FIG>, Flash memory controller <NUM> further includes an ECC module <NUM> operatively coupled to management module <NUM> and configured to process the ECC. The data written into or read from NAND memory <NUM> can be encoded or decoded based on an ECC to reduce errors in the data. ECC can add redundancy to the transmitted data using an algorithm including, for example, Hamming code, Bose-Chaudhuri-Hocquenghem (BCH) code, and Reed-Solomon code.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which at least one of bad-block management, garbage collection, logical-to-physical address conversion, or wear leveling with respect to the data is managed by the Flash memory controller. As illustrated in <FIG>, management module <NUM> of Flash memory controller <NUM> can be further configured to perform any suitable management functions with respect to the data written into or read from NAND memory <NUM> to reduce the burden on host processor <NUM>. The management functions include, but not limited to, bad-block management, garbage collection, logical-to-physical address conversion, and wear leveling.

According to one aspect of the present disclosure, a memory device includes a first semiconductor structure including a Flash memory controller, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts. The memory device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

In some embodiments, the first semiconductor structure includes a substrate, the Flash memory controller on the substrate, the peripheral circuit on the substrate and outside of the Flash memory controller, and the first bonding layer above the Flash memory controller and the peripheral circuit.

In some embodiments, the second semiconductor structure includes the second bonding layer above the first bonding layer, a memory stack above the second bonding layer, an array of 3D NAND memory strings extending vertically through the memory stack, and a semiconductor layer above and in contact with the array of 3D NAND memory strings.

In some embodiments, the second semiconductor structure includes the second bonding layer above the first bonding layer, an array of 2D NAND memory cells above the second bonding layer, and a semiconductor layer above and in contact with the array of 2D NAND memory cells.

In some embodiments, the 3D memory device further includes a pad-out interconnect layer above the semiconductor layer. In some embodiments, the semiconductor layer includes polysilicon. In some embodiments, the semiconductor layer includes single-crystal silicon.

In some embodiments, the second semiconductor structure includes a substrate, a memory stack above the substrate, an array of 3D NAND memory strings extending vertically through the memory stack, and the second bonding layer above the memory stack and the array of 3D NAND memory strings.

In some embodiments, the second semiconductor structure includes a substrate, an array of 2D NAND memory cells on the substrate, and the second bonding layer above the memory stack and the array of 2D NAND memory cells.

In some embodiments, the first semiconductor structure includes the first bonding layer above the second bonding layer, the Flash memory controller above the first bonding layer, the peripheral circuit above the first bonding layer and outside of the Flash memory controller, and a semiconductor layer above and in contact with the Flash memory controller and the peripheral circuit. In some embodiments, the memory device further includes a pad-out interconnect layer above the semiconductor layer.

In accordance with the claimed invention, the Flash memory controller and the peripheral circuit are stacked one over another.

According to the invention, the peripheral circuit includes one or more page buffers and word line drivers of the array of NAND memory cells.

According to the invention, the first semiconductor structure includes a first interconnect layer vertically between the first bonding layer and the Flash memory controller, and the second semiconductor structure includes a second interconnect layer vertically between the second bonding layer and the array of NAND memory cells.

In some embodiments, the Flash memory controller is electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts.

According to the invention, the peripheral circuit is electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts.

According to the invention, the peripheral circuit is electrically connected to the Flash memory controller through the first interconnect layer.

According to the invention, the Flash memory controller includes a host interface operatively coupled to a host processor, a NAND memory interface operatively coupled to the array of NAND memory cells, a management module, and an ECC module. In some embodiments, the ECC module is configured to process an ECC, and the management module is configured to manage at least one of bad-block management, garbage collection, logical-to-physical address conversion, or wear leveling.

According to another aspect of the present disclosure, a method for forming a memory device is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes a Flash memory controller, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

According to the invention, to form the first semiconductor structure, the Flash memory controller and the peripheral circuit are formed on a first substrate, a first interconnect layer is formed above the Flash memory controller and the peripheral circuit, and the first bonding layer is formed above the first interconnect layer.

In some embodiments, to form the Flash memory controller and the peripheral circuit, a plurality of transistors are formed on the first substrate.

In some embodiments, to form the second semiconductor structure, a memory stack is formed above a second substrate, an array of 3D NAND memory strings extending vertically through the memory stack are formed, a second interconnect layer is formed above the array of 3D NAND memory strings, and the second bonding layer is formed above the second interconnect layer.

In some embodiments, to form the second semiconductor structure, an array of 2D NAND memory cells are formed on a second substrate, a second interconnect layer is formed above the array of 2D NAND memory cells, and the second bonding layer is formed above the second interconnect layer.

In some embodiments, the second semiconductor structure is above the first semiconductor structure after the bonding. In some embodiments, the second substrate is thinned to form a semiconductor layer after the bonding, and a pad-out interconnect layer is formed above the semiconductor layer.

In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding. In some embodiments, the first substrate is thinned to form a semiconductor layer after the bonding, and a pad-out interconnect layer is formed above the semiconductor layer.

In some embodiments, the bonding includes hybrid bonding.

According to the invention, the Flash memory controller includes a host interface operatively coupled to a host processor, a NAND memory interface operatively coupled to the array of NAND memory cells, a management module, and an ECC module.

According to still another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a Flash memory controller, a peripheral circuit, and an array of NAND memory cells in a same bonded chip. An instruction from a host processor is received by the Flash memory controller. Control signals are transmitted by the Flash memory controller to the array of NAND memory cells through a plurality of bonding contacts to control operations of the array of NAND memory cells based on the instruction. Status signals indicative of the operations are received by the Flash memory controller from the array of NAND memory cells through the plurality of bonding contacts.

In some embodiments, data is transferred between the peripheral circuit and the array of NAND memory cells through the plurality of bonding contacts.

In some embodiments, the data is stored in the array of NAND memory cells.

In some embodiments, an ECC with respect to the data is processed by the Flash memory controller, and at least one of bad-block management, garbage collection, logical-to-physical address conversion, or wear leveling with respect to the data is managed by the Flash memory controller.

The Summary section may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, is not intended to limit the present disclosure and the appended claims in any way.

Claim 1:
A memory device (<NUM>), comprising:
a first semiconductor structure (<NUM>) comprising a Flash memory controller (<NUM>), a peripheral circuit (<NUM>), and a first bonding layer (<NUM>) comprising a plurality of first bonding contacts (<NUM>);
a second semiconductor structure (<NUM>) comprising an array of NAND memory cells (<NUM>, <NUM>) and a second bonding layer (<NUM>) comprising a plurality of second bonding contacts (<NUM>);
wherein the peripheral circuit comprises one or more page buffers (<NUM>) and word line drivers (<NUM>) of the array of NAND memory cells, and wherein the Flash memory controller comprises a host interface (<NUM>) operatively coupled to a host processor (<NUM>), a NAND memory interface (<NUM>) operatively coupled to the array of NAND memory cells, a management module (<NUM>), and an error correction code, ECC, module (<NUM>);
wherein the first semiconductor structure comprises a first interconnect layer (<NUM>) vertically between the first bonding layer and the Flash memory controller, and the second semiconductor structure comprises a second interconnect layer (<NUM>) vertically between the second bonding layer and the array of NAND memory cells; and
a bonding interface (<NUM>) between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, and wherein the bonding interface between the first bonding layer and the second bonding layer is as a result of hybrid bonding that obtains metal-metal bonding and dielectric-dielectric bonding simultaneously;
wherein the peripheral circuit is electrically connected to the Flash memory controller through the first interconnect layer; and
wherein the peripheral circuit is electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts,
characterised in that
the Flash memory controller and the peripheral circuit are stacked one over another.