Patent Description:
An integrated circuit (IC) includes at least one power supply pin for receiving a supply voltage from a power supply. The supply voltage received by the IC is used to provide power to circuitry formed on the IC.

When attached to a circuit board, the IC receives the supply voltage by way of a circuit board trace. For example, the circuit board can correspond to a printed circuit board (PCB) that has been patterned to form a power supply bus for delivering the supply voltage to the IC.

The following documents are relevant: <CIT> which discusses a current compensation circuit and a semiconductor memory device and <CIT> which discusses a stacked power amplifier power control.

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing.

Apparatus and methods for compensating supply sensitive circuits for supply voltage variation are provided. In accordance with the invention, an electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a group of integrated circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a supply sensing circuit that generates a sense signal based on a local voltage level of the supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between the nominal voltage level and the local voltage level of the supply voltage, and a signal processing circuit biased by the bias signal.

By implementing the ICs with supply voltage compensation in this manner, the signal processing circuits exhibit supply invariant performance. Absent such compensation, the performance of the signal processing circuits are impacted by changes in the voltage level of the supply voltage relative to the nominal voltage level. For example, the signal processing circuits can perform a variety of analog and/or RF signaling functions including, but not limited to, amplification, phase shifting, and/or frequency dependent processing, and the performance of such functionality can be impacted by the particular voltage level of the supply voltage.

Thus, the signal processing circuit have a dynamically adjusted bias to account for supply voltage variation. Each signal processing circuit includes an RF amplifier having a DC operating point set by the bias signal, and the bias control circuit of each IC adjusts the local bias signal to maintain a gain of the amplifier substantially constant.

In certain implementations, each signal processing circuit corresponds to a signal processing channel for the electronic system, and an output of each signal processing circuit is combined to generate a combined signal. For example, the electronic system can correspond to a phased array antenna system, and the signal processing circuits can be used for gain control and/or phase control in forming a signal beam.

In such applications, the overall performance of the electronic system is enhanced by reducing or eliminating the impact of supply voltage drop on channel-to-channel variation. For example, in a beamforming application, the outputs of the signal processing circuits can be used to generate a signal beam with precise scanning angle.

<FIG> is a schematic diagram of one embodiment of an electronic system <NUM> with compensation for supply voltage variation. The electronic system <NUM> includes an IC <NUM>, a power supply <NUM>, and a supply conductor <NUM>. An integrated circuit, such as the IC <NUM> of <FIG>, is also referred to herein as a semiconductor die or semiconductor chip.

As shown in <FIG>, the power supply <NUM> generates a supply voltage VSUP, which is provided to one or more supply pins of the IC <NUM> by way of the supply conductor <NUM>. In certain implementations, the electronic system <NUM> is implemented on a circuit board, and the supply conductor <NUM> corresponds to conductive trace of the circuit board. In some implementations, the power supply <NUM> can correspond to another IC, such as a power management IC that includes at least one switched-mode power supply and/or at least one DC-to-DC converter.

Due to non-zero impedance of the supply conductor <NUM>, losses cause a local voltage level of a supply voltage VSUP' received at the IC <NUM> being lower than a nominal voltage level of the supply voltage VSUP directly at the output of the power supply <NUM>. For example, the supply conductor <NUM> can have a resistance that leads to current-resistor (I*R) voltage drops and a corresponding difference between the nominal voltage level and the local voltage level. Moreover, even when the supply conductor <NUM> is very wide and thick for low resistivity, voltage drop can arise in applications in which the IC <NUM> draws a relatively large amount of current.

In the illustrated embodiment, the IC <NUM> includes a signal processing circuit <NUM>, a supply sensing circuit <NUM>, and a bias control circuit <NUM>.

The signal processing circuit <NUM> receives an input signal IN and generates an output signal OUT. The signal processing circuit <NUM> also receives a bias signal BIAS for biasing the signal processing circuit <NUM>. For example, the signal processing circuit <NUM> can include analog and/or RF circuitry that operates with a DC bias point that is set by the bias signal BIAS. Although shown as outputting one output signal and receiving one input signal and one bias signal, the signal processing circuit <NUM> can be adapted to include any number of inputs and/or outputs.

Absent compensation, the performance of the signal processing circuit <NUM> is impacted by changes in the voltage level of the supply voltage VSUP'. For example, the signal processing circuit <NUM> can perform a variety of analog and/or RF signaling functions, such as amplification, phase shifting, and/or frequency dependent processing, and the performance of such functionality can be impacted by the particular voltage level of the supply voltage VSUP'.

To account for supply voltage variation, the supply sensing circuit <NUM> senses the voltage level of the supply voltage VSUP', and generates a sense signal SENSE that is provided to the bias control circuit <NUM>. The bias control circuit <NUM> processes the sense signal SENSE to provide an adjustment to the bias signal BIAS such that the performance of the signal processing circuit <NUM> is substantially the same in the presence of variation of the supply voltage VSUP'. Thus, even if the local voltage level was below the nominal voltage level by 10mV, 50mV, or 100mV, the adjustment to the bias signal BIAS maintains the operation of the signal processing circuit <NUM> constant across all such supply voltage scenarios.

Accordingly, by implementing the IC <NUM> with supply voltage compensation, the signal processing circuit <NUM> exhibits supply invariant performance.

<FIG> is a schematic diagram of another embodiment of an electronic system <NUM> with compensation for supply voltage variation. The electronic system <NUM> includes ICs 1a, 1b,. 1n, a power supply <NUM>, and a supply conductor <NUM>'.

In comparison to the electronic system <NUM> of <FIG>, the electronic system <NUM> of <FIG> includes multiple ICs that are powered by the supply voltage VSUP provided by the power supply <NUM>. Although an example with three ICs is shown, more or fewer ICs can be included as indicated by the ellipsis.

As shown in <FIG>, the supply voltage VSUP is routed from the output of the power supply <NUM> to pins of the ICs 1a, 1b,. 1n by way of the supply conductor <NUM>'. In certain implementations, the electronic system <NUM> is implemented on a circuit board, and the supply conductor <NUM>' corresponds to conductive trace of the circuit board.

The length of conductor between the power supply <NUM> and each IC 1a, 1b,. 1n varies, which gives rise to differences in the supply voltage level received by each IC. Moreover, even in implementations in which the length of conductor is matched between the power supply <NUM> and each IC 1a, 1b,. 1n, local supply voltage differences can nevertheless arise due to differences in the amount of current drawn by each IC and/or over different sections of the supply conductors.

In the illustrated example, the IC 1a includes one or more supply pins that receive a supply voltage VSUP'. Additionally, the IC 1b includes one or more supply pins that receive a supply voltage VSUP", while the IC 1n includes one or more supply pins that receive a supply voltage VSUP‴. Thus, the supply voltage level received by each of the ICs 1a, 1b,. 1n (the local voltage level of the supply voltage) can vary from IC to IC.

To account for supply voltage variation, each of the ICs 1a, 1b,. 1n is implemented using the configuration of <FIG>. For example, the IC 1a includes a supply sensing circuit 12a that generates a sense signal SENSE', a bias control circuit 13a that generates a bias signal BIAS' adjusted by the sense signal SENSE', and a signal processing circuit 11a that is biased by the bias signal BIAS' and processes an input signal INa to generate an output signal OUTa.

Likewise, the IC 1b includes a supply sensing circuit 12b that generates a sense signal SENSE", a bias control circuit 13b that generates a bias signal BIAS" adjusted by the sense signal SENSE", and a signal processing circuit 11b that is biased by the bias signal BIAS" and that processes an input signal INb to generate an output signal OUTb. Furthermore, the IC 1n includes a supply sensing circuit 12n that generates a sense signal SENSE‴, a bias control circuit 13n that generates a bias signal BIAS‴ adjusted by the sense signal SENSE‴, and a signal processing circuit 11n that is biased by the bias signal BIAS‴ and that processes an input signal INn to generate an output signal OUTn.

In certain implementations, the signal processing circuits 11a, 11b,. 11n correspond to signal processing channels that operate in combination with one another to generate a combined signal. In one example, the signal processing circuits 11a, 11b,. 11n correspond to RF signal channels of a beamforming communication system, which is also referred to herein as a phased array antenna system. In applications in which the signal processing channels operate in combination with another, variations in the performance of a given channel can degrade the accuracy of the overall system. For instance, in the beamforming context, the scanning angle for beamforming can be degraded when power supply variation degrades the performance of each channel.

To compensate for power supply variation, each of the ICs 1a, 1b,. 1n is operable to sense the local supply voltage level and provide adjustments to bias signal levels accordingly. Thus, even when the voltages levels of VSUP", VSUP", and VSUP‴ vary from one another, internal IC bias adjustment results in substantially uniform performance across the ICs 1a, 1b,.

<FIG> is a schematic diagram of an IC <NUM> with compensation for supply voltage variation according to another embodiment. The IC <NUM> includes at least one pin <NUM> for receiving a supply voltage VSUP. Additionally, the IC <NUM> further includes a supply sensing circuit <NUM>, a DC operating point adjustment circuit <NUM>, and a signal processing circuit <NUM> that includes at least one amplifier <NUM>.

As shown in <FIG>, the supply sensing circuit <NUM> receives the local supply voltage VSUP and generates a sense signal SENSE that changes in relation to the supply voltage level. Additionally, the DC operating point adjustment circuit <NUM> generates a bias signal BIAS based on the sense signal SENSE. In particular, the DC operating point adjustment circuit <NUM> generates the bias signal BIAS to bias the DC operating point of the amplifier <NUM> such that a gain of the amplifier <NUM> is substantially constant across variations in the supply voltage VSUP.

<FIG> is a graph of one example of supply current ISUP versus supply voltage VSUP for one implementation of the IC <NUM> of <FIG>.

In certain implementations herein, an IC implemented with compensation for supply voltage variation exhibits a decrease in the supply current ISUP as the supply voltage VSUP increases. Thus, rather than having a flat profile of supply current versus supply voltage or a profile of supply current that increases with supply voltage, the IC can exhibit the profile of <FIG>.

Although an example in which the profile of the supply current ISUP versus the supply voltage VSUP is substantially linear, other profiles are possible.

<FIG> is a schematic diagram of a supply insensitive amplifier <NUM> according to one embodiment. The supply insensitive amplifier <NUM> includes a supply sensing circuit <NUM>, a controllable bias current source <NUM>, a first bias p-type field effect transistor (PFET) <NUM>, a second bias PFET <NUM>, a first bias n-type field effect transistor (NFET) <NUM>, a second bias NFET <NUM>, an amplifier common source NFET <NUM>, an amplifier cascode NFET <NUM>, a bias resistor <NUM>, and a choke inductor <NUM>. The supply insensitive amplifier <NUM> is powered by a supply voltage VSUP, and is used to amplify an input signal received on an input terminal IN to generate an output signal on an output terminal OUT.

Although one embodiment of a circuit compensated for supply voltage variation is depicted, the teachings herein are applicable to a wide variety of signal processing circuits.

In the illustrated embodiment, the controllable bias current source <NUM> includes a first end electrically connected to a ground voltage and a second end electrically connected to a gate and a drain of the first bias PFET <NUM> and to a gate of the second bias PFET <NUM>. Additionally, the first bias PFET <NUM> and the second bias PFET <NUM> each include a source electrically connected to the supply voltage VSUP. The second bias PFET <NUM> further includes a drain that is electrically connected to a drain of the second bias NFET <NUM>, to a gate of the first bias NFET <NUM>, and to a first end of the bias resistor <NUM>. The first bias NFET <NUM> further includes a source electrically connected to the ground voltage and a drain electrically connected to a source of the second bias NFET <NUM>. A cascode bias voltage VCAS is used to bias a gate of the second bias NFET <NUM> and a gate of the amplifier cascode NFET <NUM>. The cascode bias voltage VCAS can be generated using any suitable biasing circuitry.

With continuing reference to <FIG>, the input terminal IN is connected to a second end of the bias resistor <NUM> and to a gate of the amplifier common source NFET <NUM>. The amplifier common source NFET <NUM> includes a source electrically connected to the ground voltage and a drain electrically connected to a source of the amplifier cascode NFET <NUM>. The amplifier cascode NFET <NUM> further includes a drain electrically connected to the output terminal OUT. The choke inductor <NUM> includes a first end electrically connected to the supply voltage VSUP and a second end electrically connected to the output terminal OUT.

As shown in <FIG>, the supply sensing circuit <NUM> adjusts the amount of bias current IBIAS from the controllable bias current source <NUM> based on the sensed voltage difference between the supply voltage VSUP and the ground voltage. Additionally, the first bias PFET <NUM> and the second bias PFET <NUM> serve as a current mirror that mirrors the adjusted bias current IBIAS to generate a mirrored current that flows through the series combination of the second bias NFET <NUM> and the first bias NFET <NUM> to generate a bias voltage VBIAS. Additionally, the bias voltage VBIAS is provided to the gate of the amplifier common source NFET <NUM> through the bias resistor <NUM>.

In the illustrated embodiment, the amplifier is implemented using a cascode amplifier topology in which the amplifier cascode NFET <NUM> is included between the drain of the amplifier common source NFET <NUM> and the choke inductor <NUM>. In this example, one cascode device is included, but additional cascode devices can be included or a cascode device can be omitted. Furthermore, although a FET implementation is depicted, implementations using bipolar transistors or a combination using FET and bipolar transistors are also possible.

Although using a cascode amplifier topology mitigates the impact of supply variation on gain, absent compensation a cascode amplifier can nevertheless have gain that changes with supply voltage level.

By adjusting the bias current IBIAS to account for variation of the supply voltage VSUP, the amplifier <NUM> operates with insensitivity to supply voltage variation.

<FIG> is a schematic diagram of a supply insensitive amplifier <NUM> according to another embodiment. The supply insensitive amplifier <NUM> includes a first bias PFET <NUM>, a second bias PFET <NUM>, a first bias NFET <NUM>, a second bias NFET <NUM>, an amplifier common source NFET <NUM>, an amplifier cascode NFET <NUM>, a bias resistor <NUM>, and a choke inductor <NUM>, which can be as described above with respect to <FIG>. The supply insensitive amplifier <NUM> further includes a first sense NFET <NUM>, a second sense NFET <NUM>, a third bias NFET <NUM>, a fourth bias NFET <NUM>, and a bias current source <NUM>.

In the illustrated embodiment, the first sense NFET <NUM> includes a source electrically connected to the ground voltage, a drain electrically connected to the supply voltage VSUP, and a gate electrically connected to the supply voltage VSUP and to a gate of the second sense NFET <NUM>. The bias current source <NUM> includes a first end electrically connected to the supply voltage VSUP and a second end electrically connected to a drain of the second sense NFET <NUM>, to a gate of the fourth bias NFET <NUM>, and to a gate and a drain of the third bias NFET <NUM>. The second sense NFET <NUM>, the third bias NFET <NUM>, and the fourth bias NFET <NUM> each include a source connected to the ground voltage.

The first sense NFET <NUM> and the second sense NFET <NUM> serve to generate a sense current ISENSE that changes in relation to the supply voltage VSUP. The sense current ISENSE is subtracted from the bias current IBIAS of the bias current source <NUM> to generate an amplifier current IAMP. The amplifier current IAMP is mirrored by the third bias NFET <NUM> and the fourth bias NFET <NUM> and subsequently processed by the depicted bias circuitry to generate the amplifier bias voltage VBIAS.

<FIG> is a schematic diagram of a supply insensitive amplifier <NUM> according to another embodiment. The supply insensitive amplifier <NUM> of <FIG> is similar to the supply insensitive amplifier <NUM> of <FIG>, except that the supply insensitive amplifier <NUM> further includes a resistor calibration circuit <NUM> and a calibrated sense resistor <NUM>.

As shown in <FIG>, the calibrated sense resistor <NUM> includes a first end electrically connected to the supply voltage VSUP and a second end electrically connected to a gate of the second sense NFET <NUM> and to a gate and a drain of the first sense NFET <NUM>. The calibrated sense resistor <NUM> is calibrated by the resistor calibration circuit <NUM> so as to operate with a fixed resistance RSENSE that is calibrated to account for at least process variation.

By including the calibrated sense resistor <NUM>, enhanced control over a sense current IRSENSE that is subtracted from the bias current IBIAS is realized. Thus, enhanced accuracy in compensation for supply voltage variation is achieved.

<FIG> is a schematic diagram of a supply insensitive amplifier <NUM> according to another embodiment. In comparison to the supply insensitive amplifier <NUM> of <FIG>, the supply insensitive amplifier <NUM> of <FIG> omits the first sense NFET <NUM> and the second sense NFET <NUM> of <FIG> in favor of including a first voltage divider resistor <NUM>, a second voltage divider resistor <NUM>, a differential amplifier <NUM>, a regulated NFET <NUM>, a resistor calibration circuit <NUM> and a calibrated sense resistor <NUM>.

As shown in <FIG>, the first voltage divider resistor <NUM> includes a first end electrically connected to the supply voltage VSUP and a second end electrically connected to a first input of the differential amplifier <NUM> and to a first end of the second voltage divider resistor <NUM>. Additionally, the differential amplifier <NUM> includes an output electrically connected to a gate of the regulated NFET <NUM> and a second input electrically connected to a source of the regulated NFET <NUM> and to a first end of the calibrated sense resistor <NUM>. The calibrated sense resistor <NUM> and the second voltage divider resistor <NUM> each further include a second end electrically connected to the ground voltage. The calibrated sense resistor <NUM> is calibrated by the resistor calibration circuit <NUM> to operate with a fixed resistance RSENSE.

In the illustrated embodiment, a drain of the regulated NFET <NUM> draws a sense current IV2ISENSE, which is subtracted from the bias current IBIAS to generate the amplifier current IAMP. The depicted sense circuitry operates as a voltage to current (V2I) loop that converts a sensed supply voltage level (as detected by the resistive voltage divider) to a corresponding sense current IV2ISENSE.

<FIG> is a schematic diagram of a supply insensitive amplifier <NUM> according to another embodiment. In comparison the supply insensitive amplifier <NUM> of <FIG>, the supply insensitive amplifier <NUM> of <FIG> further includes a PVT calibration circuit <NUM> for providing calibration to account for process, voltage, and/or temperature variation, thereby providing another layer of enhancement of the ability to account for supply voltage variation in the amplifier.

In this example, the PVT calibration circuit <NUM> adjusts at least one of a resistance of the first voltage divider resistor <NUM>', a resistance of the second voltage divider resistor <NUM>', or a current of the bias current source <NUM>'. However other component(s) can be adjusted to provide such PVT compensation. In certain configurations, the PVT compensation is custom to a specific IC, and can be based on storing data in a non-volatile memory, such as flash memory, magnetic memory, or a fuse.

<FIG> is a graph of one example of plots of gain versus frequency for three different supply voltage levels. The plots correspond to an example of a supply sensitive amplifier in which supply voltage compensation is not used. In the graph of <FIG>, plots of gain versus frequency are provided for supply voltage levels of <NUM>. 15V, <NUM>. 25V, and <NUM>.

As shown in <FIG>, large changes in gain (as indicated by a vertical offset of one plot to another) can occur as a result of supply voltage variation.

<FIG> is a graph of another example of plots of gain versus frequency for three different supply voltage levels. The plots correspond to an example of one implementation of the supply sensitive amplifier <NUM> of <FIG>.

As shown by a comparison of <FIG>, providing supply voltage compensation reduces variation in amplifier gain.

Although one example of simulation results are depicted, other simulation results are possible. For example, simulation results can vary with circuit topology, simulation models, simulation parameters, and/or simulation tools. Accordingly, other results are possible.

<FIG> is a schematic diagram of a multi-chip beamforming system <NUM> according to one embodiment. The multi-chip beamforming system <NUM> includes a circuit board <NUM>, a voltage regulator <NUM>, an array of beamforming ICs <NUM>, and a supply conductor <NUM>.

In the illustrated embodiment, the array of beamforming ICs <NUM> includes <NUM> totals ICs (indexed with indices <NUM> through <NUM>) attached to the circuit board <NUM>. However, other implementations are possible, such as IC arrays including more or fewer ICs. In certain implementations, each of the ICs <NUM> controls RF signals transmitted to and/or received from one or more corresponding antennas of an antenna array.

The voltage regulator <NUM> outputs a supply voltage VSUP to the supply conductor <NUM>. The voltage regulator <NUM> can be implemented in a wide variety of ways, such as using a switched-mode power supply or DC-to-DC converter. Although shown as being off of the circuit board <NUM>, the voltage regulator <NUM> can alternatively be attached thereto.

When powering a large number of ICs using a common voltage regulator, a large DC current (IDC) can flow from the voltage regulator <NUM>. Since the supply conductor <NUM> has finite resistivity (as depicted in <FIG> by segments with resistance R, in this example), the flow of current can lead to I*R drop and variation in local supply voltage levels for the ICs in the array <NUM>. For example, absent compensation, the upper-leftmost IC of the array <NUM> (with index <NUM>) can have the highest supply voltage level and highest gain, while the bottom-rightmost IC of the array <NUM> (with index <NUM>) can have the lowest supply voltage level and lowest gain.

By implementing the array of ICs <NUM> in accordance with the teachings herein, gain of the ICs in the array <NUM> is maintained substantially constant, and variation in supply voltage arising from I*R drop is compensated for.

<FIG> is a schematic diagram of a phased array antenna system <NUM> according to one embodiment. The phased array antenna system <NUM> includes a voltage regulator <NUM>, a digital processing circuit <NUM>, a data conversion circuit <NUM>, a channel processing circuit <NUM>, RF front end ICs 205a, 205b,. 205n, and antennas 206a, 206b,. Although an example with three RF front end ICs and three antennas is illustrated, the phased array antenna system <NUM> can include more or fewer RF front end ICs and/or more or fewer antennas as indicated by the ellipses. Furthermore, in certain implementations, the phased array antenna system <NUM> is implemented with separate antennas for transmitting and receiving signals.

The phased array antenna system <NUM> illustrates one embodiment of an electronic system that can include one or more ICs implemented in accordance with the teachings herein. However, the circuitry herein can be used in a wide range of electronics. A phased array antenna system is also referred to herein as an active scanned electronically steered array.

As shown in <FIG>, the channel processing circuit <NUM> is coupled to antennas 206a, 206b,. 206n through RF front end ICs 205a, 205b,. 205n, respectively. The channel processing circuit <NUM> includes a splitting/combining circuit <NUM>, a frequency up/down conversion circuit <NUM>, and a phase and amplitude control circuit <NUM>, in this embodiment. The channel processing circuit <NUM> provides RF signal processing of RF signals transmitted by and received from each communication channel. In the illustrated embodiment, each communication channel is associated with a corresponding RF front end IC and antenna.

With continuing reference to <FIG>, the digital processing circuit <NUM> generates digital transmit data for controlling a transmit beam radiated from the antennas 206a, 206b,. The digital processing circuit <NUM> also processes digital receive data representing a receive beam. In certain implementations, the digital processing circuit <NUM> includes one or more baseband processors.

As shown in <FIG>, the digital processing circuit <NUM> is coupled to the data conversion circuit <NUM>, which includes digital-to-analog converter (DAC) circuitry for converting digital transmit data to one or more baseband transmit signals and analog-to-digital converter (ADC) circuitry for converting one or more baseband receive signals to digital receive data.

The frequency up/down conversion circuit <NUM> provides frequency upshifting from baseband to RF and frequency downshifting from RF to baseband, in this embodiment. However, other implementations are possible, such as configurations in which the phased array antenna system <NUM> operates in part at an intermediate frequency (IF). In certain implementations, the splitting/combining circuit <NUM> provides splitting to one or more frequency upshifted transmit signals to generate RF signals suitable for processing by the RF front end ICs 205a, 205b,. 205n and subsequent transmission on the antennas 206a, 206b,. Additionally, the splitting/combining circuit <NUM> combines RF signals received vias the antennas 206a, 206b,. 206n and RF front end ICs 205a, 205b,. 205n to generate one or more baseband receive signals for the data conversion circuit <NUM>.

The channel processing circuit <NUM> also includes the phase and amplitude control circuit <NUM> for controlling beamforming operations. For example, the phase and amplitude control circuit <NUM> controls the amplitudes and phases of RF signals transmitted or received via the antennas 206a, 206b,. 206n to provide beamforming. With respect to signal transmission, the RF signal waves radiated from the antennas 206a, 206b,. 206n aggregate through constructive and destructive interference to collectively generate a transmit beam having a particular direction. With respect to signal reception, the channel processing circuit <NUM> generates a receive beam by combining the RF signals received from the antennas 206a, 206b,. 206n after amplitude scaling and phase shifting.

Phased array antenna systems are used in a wide variety of applications including, but not limited to, mobile communications, military and defense systems, and/or radar technology.

As shown in <FIG>, the RF front ends 205a, 205b,. 205n each include one or more controllable gain amplifiers 211a, 211b,. 211n, which are used to scale the amplitude of RF signals transmitted or received by the antennas 206a, 206b,. 206n, respectively. Additionally, the RF front end ICs 205a, 205b,. 205n each include one or more controllable phase shifters 212a, 212b,. 212n for phase-shifting the RF signals. For example, in certain implementations the phase and amplitude control circuit <NUM> generates gain control signals for controlling the amount of gain provided by the controllable amplifiers 211a, 211b,. 211n and phase control signals for controlling the amount of phase shifting provided by the phase shifters 212a, 212b,.

The phased array antenna system <NUM> operates to generate a transmit beam or receive beam including a main lobe pointed in a desired direction of communication. The phased array antenna system <NUM> realizes increased signal to noise (SNR) ratio in the direction of the main lobe. The transmit or receive beam also includes one or more side lobes, which point in different directions than the main lobe and are undesirable.

An accuracy of beam direction of the phased array antenna system <NUM> is based on a precision in controlling the phases of the RF signals communicated via the antennas 206a, 206b,. For example, when one or more of the RF signals has a large phase error, the beam can be broken and/or pointed in an incorrect direction. Furthermore, the size or magnitude of beam side lobe levels is based on an accuracy in controlling the amplitude of the RF signals.

Accordingly, it is desirable to tightly control the phase and amplitude of RF signals communicated by the antennas 206a, 206b,. 206n to provide robust beamforming operations.

As shown in <FIG>, the voltage regulator <NUM> provides a supply voltage to the front end ICs 205a, 205b,. By implementing the front end ICs 205a, 205b,. 205n in accordance with the teachings herein, beamforming operations of the phased array antenna system <NUM> are enhanced by providing insensitivity to power supply variation.

Devices employing the above described schemes can be implemented into various electronic devices. Examples of electronic devices include, but are not limited to, RF communication systems, consumer electronic products, electronic test equipment, communication infrastructure, etc. For instance, the circuitry herein can be included in a wide range of RF communication systems, including, but not limited to, radar systems, base stations, mobile devices (for instance, smartphones or handsets), phased array antenna systems, laptop computers, tablets, and/or wearable electronics.

The teachings herein are applicable to RF communication systems operating over a wide range of frequencies, including not only RF signals between <NUM> and <NUM>, but also to higher frequencies, such as those in the X band (about <NUM> to <NUM>), the Ku band (about <NUM> to <NUM>), the K band (about <NUM> to <NUM>), the Ka band (about <NUM> to <NUM>), the V band (about <NUM> to <NUM>), and/or the W band (about <NUM> to <NUM>). Accordingly, the teachings herein are applicable to a wide variety of RF communication systems, including microwave communication systems.

The signals amplified by the signal processing circuits herein can be associated with a variety of communication standards, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), wideband CDMA (W-CDMA), <NUM>, Long Term Evolution (LTE), <NUM>, and/or <NUM>, as well as other proprietary and non-proprietary communications standards.

The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Claim 1:
An electronic system (<NUM>) comprising:
a supply conductor (<NUM>') configured to route a supply voltage having a nominal voltage level; and
a plurality of semiconductor dies (1a, 1b, 1n) each configured to receive the supply voltage from the supply conductor (<NUM>'), wherein each of the plurality of semiconductor dies (1a, 1b, 1n) comprises:
a supply sensing circuit (12a, 12b, 12n) configured to generate a sense signal based on a local voltage level of the supply voltage;
a bias control circuit (13a, 13b, 13n) configured to adjust a bias signal based on the sense signal to account for a difference between the nominal voltage level and the local voltage level of the supply voltage; and
a signal processing circuit (11a, 11b, 11n) biased by the bias signal, wherein the signal processing circuit (11a, 11b, 11n) includes a radio frequency, RF, amplifier having a DC operating point set by the bias signal, the RF amplifier being configured to amplify an RF signal based at least in part on the bias signal.