Patent Description:
Deep Learning is a class of machine learning algorithms. Deep learning architectures, such as deep neural networks, have been applied to fields including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics and drug design.

Inference and training, two tools used for deep learning, are tending towards low precision arithmetic. Maximizing throughput of deep learning algorithms and computations may assist in meeting the needs of deep learning processors, for example, those performing deep learning in a data center.

Sparse-dense matrix multiplication (SDMM) operations are useful in a deep learning context. But traditional CPU and GPU instruction set architectures require symmetric inputs having the same density, which limits the ability to gain a performance advantage by taking advantage of the sparsity of a sparse input matrix.

<NPL>, relates to efficient Dense and Sparse Matrix Multiplication on GP-SIMD. The GP-SIMD is a hybrid general purpose SIMD computer architecture that eliminates synchronization by in-memory computing, combining data storage and massively parallel processing.

The present invention is defined in the independent claims <NUM> and <NUM>.

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:.

In the following description, numerous specific details are set forth. However, it is understood that some embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Further, when a feature, structure, or characteristic is described about an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic about other embodiments if explicitly described.

Disclosed embodiments maximize execution throughput of a sparse-dense matrix multiplication (SDMM) instruction having variable precision inputs, such as a virtual neural network (VNN) matrix multiplication instruction having one sparse matrix input and one dense matrix input. Using the circuitry disclosed herein, the disclosed SDMM instructions are expected to yield a performance gain over matrix multiplication instructions having symmetric operands.

Disclosed embodiments, by not using a conventional, symmetric matric multiplication circuit, are expected to improve a computer's SDMM instruction throughput by a factor proportional to the sparsity of the sparse input matrix. As used herein, sparsity relates to the proportion of matrix elements having zero or null values. For example, an SDMM instruction operating on a sparse matrix having <NUM> sparsity with only <NUM>/<NUM> of the elements having non-zero values is expected to have an <NUM>-fold increase in throughput. For another example, an SDMM instruction operating on a sparse matrix having <NUM> sparsity with only <NUM>/<NUM> of the elements having non-zero values is expected to have a <NUM>-fold increase in throughput.

In some embodiments, SDMM instructions are executed by execution circuitry having SIMD processing lanes using a grid of fused multiply-add (FMA) circuits. The SIMD lane width can differ in different embodiments. For example, SIMD lane width can include any of <NUM> elements, <NUM> elements, <NUM> elements, and <NUM> elements, and the elements can be any of <NUM> bits, <NUM> bits, <NUM> bits, <NUM> bits, and <NUM> bits, without limitation. SIMD lanes are used to execute an instruction in parallel on multiple data elements.

In some embodiments, multi-bank memories are used for intermediate data and result storage by the multiple SIMD lanes. For example, a SIMD execution circuitry having <NUM>, <NUM>-bit SIMD lanes may use an <NUM>-bank memory.

<FIG> is a block diagram illustrating processing components for executing a sparse-dense matrix multiplication (SDMM) instruction, such as a virtual neural network instruction (SDMVNNI), having asymmetric inputs, according to some embodiments. A virtual neural network instruction is applied in a deep learning context and is one type of instruction that can benefit from a sparse-dense matrix multiplication. There are other types of applications that may benefit from a SDMM instruction, such as Galois Field New Instructions(GFNI). Disclosed SDMM instructions are thus not meant to be limited to VNNI instructions. As illustrated, storage <NUM> stores an SDMM instruction <NUM> to be executed.

The SDMM instruction <NUM> is fetched from storage <NUM> by fetch circuit <NUM>. The fetched SDMM instruction <NUM> is decoded by decode circuit <NUM>. For example, decode circuit <NUM> receives the fetched SDMM instruction107 from fetch circuit <NUM>. The SDMM instruction format, as described further below and with respect to <FIG>, has fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements being less than one. Decode circuit <NUM> decodes the fetched SDMM instruction <NUM> into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry <NUM>). The decode circuit <NUM> also decodes instruction suffixes and prefixes (if used). Execution circuitry <NUM> is further described and illustrated below, including at least respect to <FIG> and <FIG>, below.

In some embodiments, register renaming, register allocation, and/or scheduling circuit <NUM> provides functionality for one or more of: <NUM>) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), <NUM>) allocating status bits and flags to the decoded instruction, and <NUM>) scheduling the decoded SDMM instruction <NUM> for execution on execution circuitry <NUM> out of an instruction pool (e.g., using a reservation station in some embodiments).

Registers (register file) and/or memory <NUM> store data as operands of decoded SDMM instruction <NUM> to be operated on by execution circuitry <NUM>. Exemplary register types include writemask registers, packed data registers, general purpose registers, and floating point registers, as further described and illustrated below, at least with respect to <FIG>.

In some embodiments, write back circuit <NUM> commits the result of the execution of the decoded SDMM instruction <NUM>.

<FIG> is a block diagram illustrating a data flow for processing a sparse-dense matrix multiplication (SDMM) instruction, according to some embodiments. As shown, SDMM instruction <NUM> has fields to specify an opcode <NUM> (SDMMVNNIW), a dense output matrix <NUM>, a dense source matrix <NUM>, and a sparse source matrix <NUM>. As shown, the specified sparse source matrix <NUM> is logically a M=<NUM> row by K=<NUM>-column matrix having a sparsity of non-zero elements being roughly equal to <NUM>%. In other words, only <NUM>% of the elements of the sparse source matrix have non-zero values. Processing the SDMM instruction <NUM> according to embodiments disclosed herein improves the throughput of the processor by up to six times, when compared to using a conventional symmetric matrix multiplication circuit. Disclosed embodiments avoid wasting processing cycles on zero-valued elements of the specified sparse source matrix <NUM>. In some embodiments, the sparsity of the specified sparse source matrix <NUM> is limited to less than <NUM>%. In the context of virtual neural networks, and as shown, the sparse and dense source matrices can represent an activation matrix and a weights vector.

In some embodiments, the specified sparse source matrix <NUM> is logically a M by K matrix, but only its non-zero elements are stored in memory in a compressed sparse row (CSR) or compressed sparse column (CSC) format, which in some embodiments is prepared in advance. CSC and CSR formats are further described below, at least with reference to <FIG>.

In some embodiments, SDMM instruction <NUM> further specifies an element size (here, opcode <NUM> includes a "W" suffix, specifying Word-sized elements). The format of SDMM instruction is further illustrated and described below, at least with respect to <FIG>. In some embodiments, one or more of the identified matrices are stored in registers, such as in a register file of a processor, for example as illustrated and discussed below with reference to <FIG>. In some embodiments, one or more of the identified matrices are stored in a memory location.

As shown, specified sparse source matrix <NUM> is a matrix logically having M rows (equal to <NUM>) and K columns (equal to <NUM>), with non-zero elements at (<NUM>,<NUM>), (<NUM>,<NUM>), and (<NUM>,<NUM>). Hence, specified sparse source matrix <NUM> has a sparsity of around <NUM>%, and processing the instruction according to disclosed embodiments provides an up to six-times improvement in processor throughput. Specified dense source matrix <NUM> has K rows (equal to <NUM>), and N columns (equal to <NUM>). The specified dense output matrix <NUM> is shown as having M rows and N columns. As described herein, capital letters, M, N, and K, are used to refer to the maximal dimensions of the matrices, whereas lower-case letters, m, n, and k, are used as indices to element positions within the matrices.

In operation, as shown by data flow indictors <NUM>, <NUM> and <NUM>, for each non-zero element at row m and column k of the specified sparse source matrix <NUM>, execution circuitry generates a product of the non-zero element and all the corresponding dense elements at row k of the specified dense source matrix <NUM>. Execution circuitry then accumulates each generated product with previous values of a corresponding output element at row m of the specified dense output matrix <NUM>. In some embodiments, execution circuitry writes the accumulated sum to the corresponding elements of the specified dense output matrix <NUM>. In some embodiments, execution circuitry writes the accumulated sum to a scratchpad memory (Not shown) before writing to the dense output matrix.

<FIG> is a block diagram illustrating a data flow for processing a sparse-dense matrix multiplication (SDMM) instruction, according to some embodiments. As shown, SDMM instruction <NUM> has fields to specify an opcode <NUM> (SDMMVNNI), a dense output matrix <NUM>, a dense source matrix <NUM>, and a sparse source matrix <NUM>. The specified sparse source matrix <NUM> is logically a M=<NUM> by K=<NUM> matrix, with non-zero elements in the first and third columns. Hence, the specified sparse source matrix <NUM> has a sparsity of <NUM>. In other words, <NUM>% of the elements of the specified sparse source matrix <NUM> have non-zero values. SDMM instruction <NUM>, processed according to embodiments disclosed herein, improves the throughput of the processor by two times, when compared to using a conventional symmetric matrix multiplication circuit. Disclosed embodiments avoid wasting processing cycles on zero-valued source elements. In some embodiments, the sparsity of specified sparse source matrix <NUM> is limited to less than <NUM>%. In some embodiments, one or more of the identified matrices are stored in registers, such as in a register file of a processor, for example as illustrated and discussed below with reference to <FIG>. In some embodiments, one or more of the specified sparse source, dense source, and dense output matrices are stored in a memory location.

As shown, specified sparse source matrix <NUM> is a matrix logically having M rows (equal to <NUM>) and K columns (equal to <NUM>), with eight non-zero elements at column <NUM> and column <NUM>. specified dense source matrix <NUM> has K rows (equal to <NUM>), and N columns (equal to <NUM>). As described herein, capital letters, M, N, and K, are used to refer to the maximal dimensions of the matrices, whereas lower-case letters, m, n, and k, are used to refer to indices of the element positions within the matrices.

In operation, according to some embodiments, for each non-zero element at row m and column k of specified sparse source matrix <NUM>, execution circuitry generates a product of the non-zero element and each corresponding element at row k and column {<NUM>, n-<NUM>} of specified dense source matrix <NUM>. In this embodiment, as shown at step <NUM><NUM>, each of the non-zero elements of the first column of specified sparse source matrix <NUM> is multiplied by every element at corresponding first row of specified dense source matrix <NUM>. As shown at step <NUM><NUM>, each of the non-zero elements of the third column of the specified sparse source matrix <NUM> is multiplied by every element at the corresponding third row of the specified dense source matrix <NUM>. Then, execution circuitry accumulates the products generated in step <NUM><NUM> and step <NUM><NUM> with previous values of corresponding output element at row m and column n of specified dense output matrix <NUM>. For simplicity, here, the previous values of the output matrix are not shown, but are assumed to be zero. In some embodiments, execution circuitry writes the accumulated sums to the corresponding elements of the dense output matrix. In some embodiments, execution circuitry writes the accumulated sum to a scratchpad memory before writing to the dense output matrix.

<FIG> is a block diagram illustrating an execution circuit for processing a sparse-dense matrix multiplication (SDMM) instruction, according to some embodiments. As shown, SDMM instruction <NUM> has fields to specify an opcode <NUM> (SDMMVNNI), a dense output matrix <NUM>, a sparse source matrix <NUM>, and a dense source matrix <NUM>. As illustrated, specified sparse source matrix <NUM> has a sparsity of non-zero elements being, for illustration, around <NUM>. In other words, around <NUM>% of the elements of the specified sparse source matrix have non-zero values. Processing the SDMM instruction according to embodiments disclosed herein improves the throughput of the processor by roughly <NUM> times, when compared to using a conventional symmetric matrix multiplication circuit. Disclosed embodiments avoid wasting processing cycles on zero-valued source elements. In some embodiments, the sparsity of the sparse source matrix is limited to less than <NUM>%. In some embodiments, one or more of the identified matrices are stored in registers, such as in a register file of a processor, for example as illustrated and discussed below with reference to <FIG>. In some embodiments, one or more of the identified matrices are stored in a memory location.

As shown, specified sparse source matrix <NUM> is a matrix having M rows (equal to <NUM>) and K columns (equal to <NUM>), with one non-zero elements at row <NUM> and column <NUM>. Specified dense source matrix <NUM> has K rows (equal to <NUM>), and N columns (equal to <NUM>). The specified dense output matrix <NUM> is shown as having M rows (equal to <NUM>) and N columns (equal to <NUM>).

In operation, according to some embodiments, for each non-zero element at row m and column k of specified sparse source matrix <NUM>, execution circuitry generates a product of the non-zero element and each corresponding dense element at row k and column n of specified dense source matrix <NUM>. As shown the non-zero element at element (<NUM>,<NUM>) of specified sparse source matrix <NUM> is multiplied by every element at corresponding row <NUM> of specified dense source matrix <NUM> using multipliers <NUM>. Execution circuitry then generates an accumulated sum of the products generated by multipliers <NUM> and previous values of the corresponding elements of specified dense output matrix <NUM> using adders/accumulators <NUM>. Here, the previous values of the output matrix are not shown, but, for simplicity, are assumed to be zero. In some embodiments, execution circuitry writes the accumulated sums to the corresponding elements of specified dense output matrix <NUM>. In some embodiments, execution circuitry writes the accumulated sums to a scratchpad memory <NUM> before writing to specified dense output matrix <NUM>.

Execution circuitry to execute the SDMM instruction according to disclosed embodiments is further illustrated and discussed at least with respect to <FIG>, and <FIG>.

<FIG> is a block diagram illustrating an execution circuit <NUM> for processing a sparse-dense matrix multiplication (SDMM) instruction, according to some embodiments. As shown, SDMM instruction <NUM> has fields to specify an opcode <NUM> (SDMMVNNI), a dense output matrix <NUM>, a sparse source matrix <NUM>, and a dense source matrix <NUM>. In the illustrated embodiment, the specified dense output, dense source, and sparse source matrices have dimensions M=N=<NUM> and K=<NUM> of <NUM>-byte-precision entries and the specified sparse source matrix has a sparsity of <NUM>.

In some embodiments, the specified sparse source matrix is stored in sparse format in memory <NUM>, such that the execution circuit <NUM> reads the sparsely-formatted matrix, but only buffers the non-zero values in sparse buffers <NUM>.

To avoid unnecessary memory accesses and to conserve memory space, however, some embodiments store only the non-zero elements of the sparse source matrix in memory <NUM> in compressed sparse row (CSR) or compressed sparse column (CSC) format. With CSR and CSC formats, only the non-zero elements of the sparse source matrix, organized in row-major format or column-major format, respectively, are stored. In some embodiments, the CSR or CSC-formatted sparse source matrices are prepared in memory <NUM> in advance of the operation by specialized hardware or software.

The specified sparse source matrix in the illustrated embodiment is logically a 256X512 matrix having <NUM> non-zero elements per column, i.e., at a sparsity of <NUM>. The illustrated embodiment uses CSC format to store the sparse source matrix in the sparse buffers <NUM> and each column of the sparse source sparse matrix is partitioned into <NUM> banks based on the row index M. In operation, <NUM> non-zero elements per column of the sparse source matrix are stored in <NUM> banks of the sparse buffers <NUM>, equally distributed among them in the ideal case. In some embodiments, each of the sparse buffer entries uses up to five bytes, which includes two bytes to store a data value, and up to <NUM> bytes to specify a matrix position of the element within the specified sparse source matrix. In some embodiments, the specified sparse source matrix logically has M=<NUM> rows and K=<NUM> columns, and the <NUM>-byte matrix position specifies an offset of the element within the <NUM> elements. In some embodiments, the specified sparse source matrix has M=<NUM> rows and K=<NUM> columns, and the <NUM>-byte matrix position includes a nibble to specify the column and a nibble to specify the row in which the element is located.

In the illustrated embodiment, the multiplier array is of size 8X32 where the <NUM> rows of the multiplier array are connected to the <NUM> banks of the sparse buffers <NUM> providing the <NUM> multiplier values per cycle needed for multiplication. <NUM> elements of row k of the specified dense source matrix which form the multiplicand are broadcasted and multiplied across <NUM> elements of the sparse buffers <NUM>, thus performing <NUM> multiplications per cycle. The <NUM>-element partial product generated per bank is then accumulated in accumulator array <NUM>. In some embodiments, the <NUM> elements of the specified dense source matrix are buffered in registers (not shown) before the multiplications. In some embodiments, as shown, the <NUM> elements are fed into multiplier array <NUM> as they are loaded from memory <NUM>. In some embodiments, multiplier array <NUM> comprises a grid of fused-multiply-add (FMA) hardware units.

As shown, accumulator array <NUM> includes <NUM> accumulators divided into <NUM> banks, each connected to the corresponding bank of sparse buffers <NUM> and multiplier array <NUM>. In operations, accumulators (<NUM> per bank) in accumulator array <NUM> accumulate the products generated by multiplier array <NUM> with previous values of corresponding elements of the dense output matrix specified by the dense output matrix <NUM> field of SDMM instruction <NUM>.

In some embodiments, the products generated by multiplier array <NUM> and accumulated by accumulator array <NUM> are high-precision intermediate results represented by at least twice as many bits as used by the data elements of the specified matrices. In some embodiments, rounding and saturation circuit <NUM> saturates the intermediate results to a predefined maximum and rounds them to fit within the number of bits of elements of the dense output matrix specified by the dense output matrix <NUM> field of the SDMM instruction <NUM>, which here is <NUM> bits.

In the case of floating point arithmetic, rounding and saturation circuit <NUM> may round the intermediate results according to the IEEE <NUM> floating point standard, established in <NUM> and updated in <NUM> by the Institute of Electrical and Electronics Engineers. The IEEE <NUM> floating point standard defines rounding rules to be applied, including round to nearest with ties to even, round to nearest with ties away from zero, toward zero, toward positive infinity, and toward negative infinity. In some embodiments, rounding and saturation circuit <NUM> includes a software-accessible rounding control register (not shown) to specify the rounding rule to apply.

In some embodiments, each of the FMA hardware units in multiplier array <NUM> performs the rounding by itself. In some embodiments, each of the FMA hardware units in multiplier array <NUM> checks for saturation and performs the saturating itself.

As shown, execution circuit <NUM> includes scratchpad <NUM> to store intermediate execution results. In some embodiments, as here, scratchpad <NUM> is a <NUM> kB memory, partitioned into eight (<NUM>) banks, each connected one to one with the corresponding row of the multiplier array and bank of the accumulator. In some embodiments, all of the banks of scratchpad <NUM> communicate with corresponding banks of accumulator array <NUM> in parallel, yielding a high-bandwidth connection. Using the CSC format for multiplication, whereby only non-zero elements of the specified sparse source matrix are stored in sparse buffers <NUM> and supplied to multiplier array <NUM> obviates the need to use an expensive gather scatter circuit to gather and supply non-zero data to multiplier array <NUM> and accumulator array <NUM>.

In some embodiments, as here, execution circuit <NUM> utilizes one or more single-instruction, multiple data (SIMD) processing lanes, for example, <NUM> lanes, to perform a same operation on multiple data elements at the same time. In some embodiments, a SIMD processing lane has a lane width of <NUM> elements, and <NUM> SIMD processing lanes are used to perform <NUM> operations on <NUM> elements of data.

In some embodiments, two or more SIMD processing lanes operate concurrently, and in parallel. The number of lanes in a SIMD processor, as well as the number of elements assigned to each lane, can vary, without limitation. According to some embodiments, a SIMD processing lane is implemented as having a lane width being one <NUM> elements, <NUM> elements, or <NUM> element s, with element widths of <NUM>-bits, <NUM> bits, <NUM> bits, or <NUM>-bits, without limitation.

In some embodiments, execution circuit <NUM> performs the SDMM instruction <NUM> by performing multiply-accumulate operations using fused multiply-add (FMA) hardware units to generate the products of each non-zero element of the specified sparse source matrix and each of the elements in a corresponding row of the specified dense source matrix, and to accumulate products with the previous values of corresponding elements of the dense output matrix specified by the dense output matrix <NUM> field of SDMM instruction <NUM>.

As used herein, the term "corresponding" has a different interpretation based on its context. In the context of generating the products, the corresponding elements of the dense source matrix specified by the dense source matrix <NUM> field that correspond to each non-zero element (m, k) of the sparse source matrix specified by the sparse source matrix <NUM> field of SDMM instruction <NUM> are the corresponding elements, (k, n), in a corresponding row, k of the dense source matrix specified by the dense source matrix <NUM> field of the SDMM instruction <NUM>. In the context of accumulating the products with previous contents of the dense output matrix specified by the dense output matrix <NUM> field of SDMM instruction <NUM>. The corresponding elements of the specified dense output matrix are those at locations (m, n).

Accordingly, execution circuit <NUM>, by executing an SDMM instruction <NUM> specifying a sparse source matrix <NUM> having a sparsity of <NUM>, improves the throughput of the processor in which it is incorporated by <NUM> times, when compared to using a symmetric matrix multiplication circuit.

Execution circuitry to execute the SDMM instruction according to disclosed embodiments is further illustrated and discussed, at least with respect to <FIG>, and <FIG>.

<FIG> is pseudocode illustrating operation of execution circuitry to process instructions calling for matrix multiplication, here, a virtual neural network instruction (VNNI). For illustrative purposes, pseudocode <NUM> and <NUM> illustrate implementation of a VNNI matrix multiplication instruction on symmetric source operands. As described herein, capital letters, M, N, and K, are used to refer to the maximal dimensions of the matrices, whereas lower-case letters, m, n, and k, are used to refer to indices of element positions within the matrices. Pseudocode <NUM> and pseudocode <NUM> both illustrate executing a VNNI instruction on a M-row by K-column(M x K) source matrix A and a K-row by N-column (K x N) source matrix B to generate results of a M-row by N-column (M x N) output matrix C. Pseudocodes <NUM> and <NUM>, on the other hand, illustrate executing the SDMM instruction according to disclosed embodiments, wherein only the non-zero elements of sparse source matrix A are processed, thereby increasing processor throughput in proportion to the sparsity of source matrix A.

Execution circuitry to execute the SDMM instruction according to disclosed embodiments is illustrated and discussed at least with respect to <FIG>, and <FIG>.

<FIG> is a process flow diagram illustrating execution of a sparse-dense matrix multiplication (SDMM) instruction by a processor, according to some embodiments. At <NUM>, the processor fetches, from code storage using fetch circuitry, the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one. The SDMM instruction fetched at <NUM> may be referred to as an asymmetric SDMM instruction, insofar as one source is a sparse matrix and the other source is a dense matrix. At <NUM>, the processor decodes, by decode circuitry, the fetched SDMM instruction. At <NUM>, the processor optionally schedules execution of the decoded SDMM instruction by a SIMD execution circuit. Operation <NUM> is optional, as indicated by its dashed border, insofar as scheduling execution of the decoded instruction may occur at a different time, or not at all. At <NUM>, the processor executes, by execution circuitry, the decoded SDMM instruction to, for each non-zero element at row M and column K of the sparse source matrix, generate a product of the non-zero element and each corresponding dense element at row K and column N of the dense source matrix; and accumulates each generated product with a previous value of a corresponding output element at row M and column N of the dense output matrix. At <NUM>, the processor optionally commits or retires the executed SDMM instruction. Operation <NUM> is optional, as indicated by its dashed border, insofar as it may occur at a different time, or not at all.

<FIG> is an exemplary format of a sparse-dense matrix multiplication (SDMM) instruction, according to some embodiments. As shown, SDMM instruction <NUM> includes opcode <NUM> (SDMMVNNI*), and fields to specify a dense output matrix <NUM>, dense source matrix <NUM>, and sparse source matrix <NUM>. SDMM instruction <NUM> further includes optional fields to specify element size <NUM>, and M, N, and K dimensions, <NUM>, <NUM>, and <NUM>. In some embodiments, one or more of optional dimensions <NUM>, <NUM>, and <NUM> is specified by a software programmable model specific register (MSR), which may be a predetermined MSR. As shown in <FIG>, the optional element size <NUM> may be specified by part of the opcode, and the M, N, and K dimensions, <NUM>, <NUM>, and <NUM> may be specified by a MSR, as part of the opcode, or a combination thereof. Opcode <NUM> is shown as including an asterisk to indicate that it may optionally include additional prefixes or suffixes to specify instruction behaviors. For example, opcode <NUM> may include a suffix, such as "B," "W," "D," or "Q," to specify an element size of eight, sixteen, thirty-two, and sixty-four bits, respectively. If the SDMM instruction <NUM> does not specify any of the optional parameters, predetermined default values are used. The format of the SDMM instruction is further illustrated and described below with respect to <FIG>, <FIG>, and <FIG><FIG>.

Referring again to <FIG>, the specified compressed sparse source matrix (CSR or CSC) in some embodiments is prepared in advance. CSC and CSR formats are further illustrated and described, at least with reference to <FIG>.

In some examples not falling within the scope of the present invention, SDMM instruction <NUM> is used to cause the processor to prepare a sparse source matrix in compressed format (either CSR, or CSC, as further illustrated and described with respect to <FIG>). The opcode <NUM> may include a prefix or a suffix, such as "PREP," to instruct the processor to prepare a compressed sparse source matrix. The dense output matrix <NUM> field specifies a memory address at which to store the compressed sparse source matrix, and sparse source matrix <NUM> specifies a memory location at which a sparse data set is stored, the sparse data set comprising a large block of memory having a sparsity of valid elements, the validity being determined by the data values themselves (e.g., invalid being null, zero, or below a threshold value), or by a control field appended to and indicating validity of each element. The size of the sparse data set is by the dense source matrix <NUM> field.

In one example, SDMM instruction <NUM> includes an opcode <NUM> having a "PREP" suffix, specifies a dense output matrix <NUM> where to store the condensed sparse source matrix, uses the sparse source matrix <NUM> field to specify where a sparse data set comprising tens, hundreds, thousands, millions, or billions of data elements, with invalid elements having null values, and uses the dense source matrix <NUM> field to specify a size of the sparse data set. In response, the processor loads the data elements from the specified sparse source matrix <NUM> location, uses the dense source matrix <NUM> field to determine the size of the sparse data set, determines whether each data element is valid, and writes the valid elements, in compressed format (CSR or CSC) to the specified dense output matrix <NUM> location, which is a cache-line-aligned location. The processor thus packs the valid elements of the sparse data set in compressed format (CSR or CSC) to the specified output matrix, which can serve as a sparse source matrix for a subsequent SDMM instruction.

In another example, SDMM instruction <NUM> includes an opcode <NUM> having a "PREP" suffix, specifies a dense output matrix <NUM> where to store the condensed sparse source matrix, uses the sparse source matrix <NUM> field to specify where a sparse data set comprising tens, hundreds, thousands, millions, or billions of data elements, with each element including a control fields including at least a valid bit, and uses the dense source matrix <NUM> field to specify a size (i.e., number of elements) of the sparse data set. In response, the processor loads the data elements from the specified sparse source matrix <NUM> location, uses the dense source matrix <NUM> field to determine the size of the sparse data set, determines whether each data element is valid, and writes the valid elements, in compressed format (CSR or CSC) to the specified dense output matrix <NUM> location, which in some embodiments is a cache-line-aligned location. The processor thus packs the valid elements of the sparse data set in compressed format (CSR or CSC) to the specified output matrix, which can serve as a sparse source matrix for a subsequent SDMM instruction.

A processor responding to an instance of SDMM instruction <NUM> having an opcode with a "PREP" suffix operates in the background by opportunistically scheduling execution of its requisite loads and stores only when a processor activity level is below a threshold value. In some embodiments, a processor responding to an instance of SDMM instruction <NUM> having an opcode with a "PREP" suffix generates an interrupt upon completion of compressing the specified sparse data set.

An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in each one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® <NUM> and IA-<NUM> Architectures Software Developer's Manual, September <NUM>; and see Intel® Advanced Vector Extensions Programming Reference, October <NUM>).

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format.

<FIG> are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to some embodiments. <FIG> is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to some embodiments; while <FIG> is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to some embodiments. Specifically, a generic vector friendly instruction format <NUM> for which are defined class A and class B instruction templates, both of which include no memory access <NUM> instruction templates and memory access <NUM> instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

While some embodiments will be described in which the vector friendly instruction format supports the following: a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes) (and thus, a <NUM> byte vector consists of either <NUM> doubleword-size elements or alternatively, <NUM> quadword-size elements); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); and a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., <NUM> byte vector operands) with more, less, or different data element widths (e.g., <NUM> bit (<NUM> byte) data element widths).

The class A instruction templates in <FIG> include: <NUM>) within the no memory access <NUM> instruction templates there is shown a no memory access, full round control type operation <NUM> instruction template and a no memory access, data transform type operation <NUM> instruction template; and <NUM>) within the memory access <NUM> instruction templates there is shown a memory access, temporal <NUM> instruction template and a memory access, non-temporal <NUM> instruction template. The class B instruction templates in <FIG> include: <NUM>) within the no memory access <NUM> instruction templates there is shown a no memory access, write mask control, partial round control type operation <NUM> instruction template and a no memory access, write mask control, vsize type operation <NUM> instruction template; and <NUM>) within the memory access <NUM> instruction templates there is shown a memory access, write mask control <NUM> instruction template.

The generic vector friendly instruction format <NUM> includes the following fields listed below in the order illustrated in <FIG>.

Format field <NUM> - a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format.

Base operation field <NUM> - its content distinguishes different base operations.

Register index field <NUM> - its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include enough bits to select N registers from a PxQ (e.g. 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).

Modifier field <NUM> - its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access <NUM> instruction templates and memory access <NUM> instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.

Augmentation operation field <NUM> - its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field <NUM>, an alpha field <NUM>, and a beta field <NUM>. The augmentation operation field <NUM> allows common groups of operations to be performed in a single instruction rather than <NUM>, <NUM>, or <NUM> instructions.

Scale field <NUM> - its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses <NUM>scale * index + base).

Displacement Field 862A- its content is used as part of memory address generation (e.g., for address generation that uses <NUM>scale * index + base + displacement).

Displacement Factor Field 862B (note that the juxtaposition of displacement field 862A directly over displacement factor field 862B indicates one or the other is used) - its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N) - where N is the number of bytes in the memory access (e.g., for address generation that uses <NUM>scale * index + base + scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field <NUM> (described later herein) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used for the no memory access <NUM> instruction templates and/or different embodiments may implement only one or none of the two.

Data element width field <NUM> - its content distinguishes which one of many data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.

Write mask field <NUM> - its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field <NUM> allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While some embodiments are described in which the write mask field's <NUM> content selects one of many write mask registers that contains the write mask to be used (and thus the write mask field's <NUM> content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's <NUM> content to directly specify the masking to be performed.

Immediate field <NUM> - its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.

Class field <NUM> - its content distinguishes between different classes of instructions. With reference to <FIG><FIG>the contents of this field select between class A and class B instructions. In <FIG><FIG>rounded corner squares are used to indicate a specific value is present in a field (e.g., class A 868A and class B 868B for the class field <NUM> respectively in <FIG><FIG>.

In the case of the non-memory access <NUM> instruction templates of class A, the alpha field <NUM> is interpreted as an RS field 852A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 852A. <NUM> and data transform 852A. <NUM> are respectively specified for the no memory access, round type operation <NUM> and the no memory access, data transform type operation <NUM> instruction templates), while the beta field <NUM> distinguishes which of the operations of the specified type is to be performed. In the no memory access <NUM> instruction templates, the scale field <NUM>, the displacement field 862A, and the displacement scale filed 862B are not present.

In the no memory access full round control type operation <NUM> instruction template, the beta field <NUM> is interpreted as a round control field 854A, whose content(s) provide static rounding. While in the described embodiments the round control field 854A includes a suppress all floating point exceptions (SAE) field <NUM> and a round operation control field <NUM>, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field <NUM>).

SAE field <NUM> - its content distinguishes if to disable the exception event reporting; when the SAE field's <NUM> content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

Round operation control field <NUM> - its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field <NUM> allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's <NUM> content overrides that register value.

In the no memory access data transform type operation <NUM> instruction template, the beta field <NUM> is interpreted as a data transform field 854B, whose content distinguishes which one of many data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access <NUM> instruction template of class A, the alpha field <NUM> is interpreted as an eviction hint field 852B, whose content distinguishes which one of the eviction hints is to be used (in <FIG>, temporal 852B. <NUM> and non-temporal 852B. <NUM> are respectively specified for the memory access, temporal <NUM> instruction template and the memory access, non-temporal <NUM> instruction template), while the beta field <NUM> is interpreted as a data manipulation field 854C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access <NUM> instruction templates include the scale field <NUM>, and optionally the displacement field 862A or the displacement scale field 862B.

Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are transferred is dictated by the contents of the vector mask that is selected as the write mask.

Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

In the case of the instruction templates of class B, the alpha field <NUM> is interpreted as a write mask control (Z) field 852C, whose content distinguishes whether the write masking controlled by the write mask field <NUM> should be a merging or a zeroing.

In the case of the non-memory access <NUM> instruction templates of class B, part of the beta field <NUM> is interpreted as an RL field 857A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 857A. <NUM> and vector length (VSIZE) 857A. <NUM> are respectively specified for the no memory access, write mask control, partial round control type operation <NUM> instruction template and the no memory access, write mask control, VSIZE type operation <NUM> instruction template), while the rest of the beta field <NUM> distinguishes which of the operations of the specified type is to be performed. In the no memory access <NUM> instruction templates, the scale field <NUM>, the displacement field 862A, and the displacement scale filed 862B are not present.

In the no memory access, write mask control, partial round control type operation <NUM> instruction template, the rest of the beta field <NUM> is interpreted as a round operation field 859A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field 859A - just as round operation control field <NUM>, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 859A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's <NUM> content overrides that register value.

In the no memory access, write mask control, VSIZE type operation <NUM> instruction template, the rest of the beta field <NUM> is interpreted as a vector length field 859B, whose content distinguishes which one of many data vector lengths is to be performed on (e.g., <NUM>, <NUM>, or <NUM> byte).

In the case of a memory access <NUM> instruction template of class B, part of the beta field <NUM> is interpreted as a broadcast field 857B, whose content distinguishes if the broadcast type data manipulation operation is to be performed, while the rest of the beta field <NUM> is interpreted the vector length field 859B. The memory access <NUM> instruction templates include the scale field <NUM>, and optionally the displacement field 862A or the displacement scale field 862B.

About the generic vector friendly instruction format <NUM>, a full opcode field <NUM> is shown including the format field <NUM>, the base operation field <NUM>, and the data element width field <NUM>. While one embodiment is shown where the full opcode field <NUM> includes these fields, the full opcode field <NUM> includes less than these fields in embodiments that do not support all of them. The full opcode field <NUM> provides the operation code (opcode).

The augmentation operation field <NUM>, the data element width field <NUM>, and the write mask field <NUM> allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths.

The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the invention). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: <NUM>) a form having only instructions of the class(es) supported by the target processor for execution; or <NUM>) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code.

<FIG> is a block diagram illustrating an exemplary specific vector friendly instruction format according to some embodiments. <FIG> shows a specific vector friendly instruction format <NUM> that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format <NUM> may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields from <FIG> into which the fields from <FIG> map are illustrated.

It should be understood that, although some embodiments are described with reference to the specific vector friendly instruction format <NUM> in the context of the generic vector friendly instruction format <NUM> for illustrative purposes, the invention is not limited to the specific vector friendly instruction format <NUM> except where claimed. For example, the generic vector friendly instruction format <NUM> contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format <NUM> is shown as having fields of specific sizes. By way of specific example, while the data element width field <NUM> is illustrated as a one bit field in the specific vector friendly instruction format <NUM>, the invention is not so limited (that is, the generic vector friendly instruction format <NUM> contemplates other sizes of the data element width field <NUM>).

EVEX Prefix (Bytes <NUM>-<NUM>) <NUM> - is encoded in a four-byte form.

Format Field <NUM> (EVEX Byte <NUM>, bits [<NUM>:<NUM>]) - the first byte (EVEX Byte <NUM>) is the format field <NUM> and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the invention).

The second-fourth bytes (EVEX Bytes <NUM>-<NUM>) include a number of bit fields providing specific capability.

REX field <NUM> (EVEX Byte <NUM>, bits [<NUM>-<NUM>]) - consists of a EVEX. R bit field (EVEX Byte <NUM>, bit [<NUM>] - R), EVEX. X bit field (EVEX byte <NUM>, bit [<NUM>] - X), and 857BEX byte <NUM>, bit[<NUM>] - B). X, and EVEX. B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using <NUM> complement form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX. X, and EVEX.

REX' field <NUM> - this is the first part of the REX' field <NUM> and is the EVEX. R' bit field (EVEX Byte <NUM>, bit [<NUM>] - R') that is used to encode either the upper <NUM> or lower <NUM> of the extended <NUM> register set. In one embodiment of the invention, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 <NUM>-bit mode) from the BOUND instruction, whose real opcode byte is <NUM>, but does not accept in the MOD R/M field (described below) the value of <NUM> in the MOD field; alternative some embodiments do not store this and the other indicated bits below in the inverted format. A value of <NUM> is used to encode the lower <NUM> registers. In other words, R'Rrrr is formed by combining EVEX. R, and the other RRR from other fields.

Opcode map field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>] - mmmm) - its content encodes an implied leading opcode byte (0F, 0F <NUM>, or 0F <NUM>).

Data element width field <NUM> (EVEX byte <NUM>, bit [<NUM>] - W) - is represented by the notation EVEX. W is used to define the granularity (size) of the datatype (either <NUM>-bit data elements or <NUM>-bit data elements).

vvvv <NUM> (EVEX Byte <NUM>, bits [<NUM>:<NUM>]-vvvv)- the role of EVEX. vvvv may include the following: <NUM>) EVEX. vvvv encodes the first source register operand, specified in inverted (<NUM> complement) form and is valid for instructions with <NUM> or more source operands; <NUM>) EVEX. vvvv encodes the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) EVEX. vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX. vvvv field <NUM> encodes the <NUM> low-order bits of the first source register specifier stored in inverted (<NUM> complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to <NUM> registers.

U <NUM> Class field (EVEX byte <NUM>, bit [<NUM>]-U) - If EVEX. U = <NUM>, it indicates class A or EVEX. U0; if EVEX. U = <NUM>, it indicates class B or EVEX.

Prefix encoding field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-pp) - provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only <NUM> bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (<NUM>, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field's content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the <NUM> bit SIMD prefix encodings, and thus not require the expansion.

Alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH; also known as EVEX. write mask control, and EVEX. N; also illustrated with α) - as previously described, this field is context specific.

Beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-SSS, also known as EVEX. s<NUM>-<NUM>, EVEX. r<NUM>-<NUM>, EVEX. LLB; also illustrated with βββ) - as previously described, this field is context specific.

REX' field <NUM> - this is the remainder of the REX' field and is the EVEX. V' bit field (EVEX Byte <NUM>, bit [<NUM>] - V') that may be used to encode either the upper <NUM> or lower <NUM> of the extended <NUM> register set. This bit is stored in bit inverted format. A value of <NUM> is used to encode the lower <NUM> registers. In other words, V'VVVV is formed by combining EVEX.

Write mask field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-kkk) - its content specifies the index of a register in the write mask registers as previously described. In one embodiment of the invention, the specific value EVEX. kkk=<NUM> has a special behavior implying no write mask is used for the particular instruction (this may be implemented in a variety of ways including the use of a write mask hardwired to all ones or hardware that bypasses the masking hardware).

Real Opcode Field <NUM> (Byte <NUM>) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field <NUM> (Byte <NUM>) includes MOD field <NUM>, Reg field <NUM>, and R/M field <NUM>. As previously described, the MOD field's <NUM> content distinguishes between memory access and non-memory access operations. The role of Reg field <NUM> can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field <NUM> may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte <NUM>) - As previously described, the scale field's <NUM> content is used for memory address generation. xxx <NUM> and SIB. bbb <NUM> - the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field 862A (Bytes <NUM>-<NUM>) - when MOD field <NUM> contains <NUM>, bytes <NUM>-<NUM> are the displacement field 862A, and it works the same as the legacy <NUM>-bit displacement (disp32) and works at byte granularity.

Displacement factor field 862B (Byte <NUM>) - when MOD field <NUM> contains <NUM>, byte <NUM> is the displacement factor field 862B. The location of this field is that same as that of the legacy x86 instruction set <NUM>-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between -<NUM> and <NUM> bytes offsets; in terms of <NUM> byte cache lines, disp8 uses <NUM> bits that can be set to only four really useful values -<NUM>, - <NUM>, <NUM>, and <NUM>; since a greater range is often needed, disp32 is used; however, disp32 requires <NUM> bytes. In contrast to disp8 and disp32, the displacement factor field 862B is a reinterpretation of disp8; when using displacement factor field 862B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 862B substitutes the legacy x86 instruction set <NUM>-bit displacement. Thus, the displacement factor field 862B is encoded the same way as an x86 instruction set <NUM>-bit displacement (so no changes in the ModRM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset). Immediate field <NUM> operates as previously described.

<FIG> is a block diagram illustrating the fields of the specific vector friendly instruction format <NUM> that make up the full opcode field <NUM> according to one embodiment of the invention. Specifically, the full opcode field <NUM> includes the format field <NUM>, the base operation field <NUM>, and the data element width (W) field <NUM>. The base operation field <NUM> includes the prefix encoding field <NUM>, the opcode map field <NUM>, and the real opcode field <NUM>.

<FIG> is a block diagram illustrating the fields of the specific vector friendly instruction format <NUM> that make up the register index field <NUM> according to one embodiment of the invention. Specifically, the register index field <NUM> includes the REX field <NUM>, the REX' field <NUM>, the MODR/M. reg field <NUM>, the MODR/M. r/m field <NUM>, the VVVV field <NUM>, xxx field <NUM>, and the bbb field <NUM>.

<FIG> is a block diagram illustrating the fields of the specific vector friendly instruction format that makes up the augmentation operation field <NUM> according to one embodiment of the invention. When the class (U) field <NUM> contains <NUM>, it signifies EVEX. U0 (class A 868A); when it contains <NUM>, it signifies EVEX. U1 (class B 868B). When U=<NUM> and the MOD field <NUM> contains <NUM> (signifying a no memory access operation), the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the rs field 852A. When the rs field 852A contains a <NUM> (round 852A. <NUM>), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as the round control field 854A. The round control field 854A includes a one bit SAE field <NUM> and a two bit round operation field <NUM>. When the rs field 852A contains a <NUM> (data transform 852A. <NUM>), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as a three bit data transform field 854B. When U=<NUM> and the MOD field <NUM> contains <NUM>, <NUM>, or <NUM> (signifying a memory access operation), the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the eviction hint (EH) field 852B and the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as a three bit data manipulation field 854C.

When U=<NUM>, the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the write mask control (Z) field 852C. When U=<NUM> and the MOD field <NUM> contains <NUM> (signifying a no memory access operation), part of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>]- S<NUM>) is interpreted as the RL field 857A; when it contains a <NUM> (round 857A. <NUM>) the rest of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>-<NUM>]- S<NUM>-<NUM>) is interpreted as the round operation field 859A, while when the RL field 857A contains a <NUM> (VSIZE <NUM>. A2) the rest of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>-<NUM>]-S<NUM>-<NUM>) is interpreted as the vector length field 859B (EVEX byte <NUM>, bit [<NUM>-<NUM>]- L<NUM>-<NUM>). When U=<NUM> and the MOD field <NUM> contains <NUM>, <NUM>, or <NUM> (signifying a memory access operation), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as the vector length field 859B (EVEX byte <NUM>, bit [<NUM>-<NUM>]- L<NUM>-<NUM>) and the broadcast field 857B (EVEX byte <NUM>, bit [<NUM>]- B).

<FIG> is a block diagram of a register architecture <NUM> according to one embodiment of the invention. In the embodiment illustrated, there are <NUM> vector registers <NUM> that are <NUM> bits wide; these registers are referenced as zmm0 through zmm31. The lower order <NUM> bits of the lower <NUM> zmm registers are overlaid on registers ymm0-<NUM>. The lower order <NUM> bits of the lower <NUM> zmm registers (the lower order <NUM> bits of the ymm registers) are overlaid on registers xmm0-<NUM>. The specific vector friendly instruction format <NUM> operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field 859B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field 859B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format <NUM> operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers <NUM> - in the embodiment illustrated, there are <NUM> write mask registers (k0 through k7), each <NUM> bits in size. In an alternate embodiment, the write mask registers <NUM> are <NUM> bits in size. As previously described, in one embodiment of the invention, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

General-purpose registers <NUM> - in the embodiment illustrated, there are sixteen <NUM>-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) <NUM>, on which is aliased the MMX packed integer flat register file <NUM> - in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to some embodiments. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to some embodiments. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units <NUM>/<NUM> and a shared L2 cache unit <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core, along with its connection to the on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to some embodiments. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> and vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core is stored in its L2 cache subset <NUM> and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset <NUM> and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is <NUM>-bits wide per direction.

<FIG> is an expanded view of part of the processor core in <FIG> according to some embodiments. <FIG> includes an L1 data cache 1206A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> is a <NUM>-wide vector processing unit (VPU) (see the <NUM>-wide ALU <NUM>), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 1222A-B, and replication with replication unit <NUM> on the memory input. Write mask registers <NUM> allow predicating resulting vector writes.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to some embodiments. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 1302A, a system agent <NUM>, a set of one or more bus controller units <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 1302A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 1302A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 1302A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 1302A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of many process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit <NUM> interconnects the integrated graphics logic <NUM> (integrated graphics logic <NUM> is an example of and is also referred to herein as special purpose logic), the set of shared cache units <NUM>, and the system agent unit <NUM>/integrated memory controller unit(s) <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 1302A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 1302A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1302A-N and the integrated graphics logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 1302A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1302A-N may be capable of execution the same instruction set, while others may can execute only a subset of that instruction set or a different instruction set.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> to avoid obscuring other aspects of <FIG>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 1302A-N, which include cache units 1304A-N, and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a Static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Some embodiments may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

In fact, the mechanisms described herein are not limited in scope to any programming language.

Such representations, known as "IP cores" may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.

Accordingly, some embodiments also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Claim 1:
A processor to execute a sparse-dense matrix multiplication, SDMM, instruction (<NUM>, <NUM>, <NUM>), comprising:
fetch circuitry (<NUM>) to fetch, from code storage (<NUM>), the SDMM instruction (<NUM>, <NUM>, <NUM>) having fields to specify an opcode (<NUM>), a dense output matrix (<NUM>, <NUM>), a dense source matrix (<NUM>, <NUM>), and a sparse source matrix (<NUM>, <NUM>) having a sparsity of non-zero elements, the sparsity being less than one, the sparse source matrix (<NUM>) being in a compressed format, the compressed format including only non-zero elements of the sparse source matrix (<NUM>), each non-zero element being represented by a data value and a matrix location, and dimensions (<NUM>, <NUM>, <NUM>) of the dense source matrix (<NUM>) and the sparse source matrix (<NUM>) being specified by the SDMM instruction (<NUM>, <NUM>, <NUM>) or a register;
decode circuitry (<NUM>) to decode the fetched SDMM instruction; and
execution circuitry (<NUM>), responsive to the decoded SDMM instruction to, for each non-zero element at row M and column K of the specified sparse source matrix (<NUM>):
generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix (<NUM>); and
generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix (<NUM>).