Patent Description:
<CIT> and <CIT> describe refresh methods for a volatile memory device. A row hammer event is detected in response to a number of row accesses reaching a threshold, and a refresh command is sent to cause the memory device to refresh the victimized row. Document <CIT> discloses a DRAM comprising input/output, termed I/O, interface circuitry configured to receive signals from and send signals to an I/O interface on a host apparatus, the I/O interface including an alert signal line; row hammer, termed RH, detection circuitry configured to detect a RH attack on one or more rows of memory cells; DRAM-side RH mitigation circuitry configured to perform DRAM-side operations in connection with an RH mitigation and/or recovery process; wherein, in response to detection of an RH attack, the DRAM device is configured to assert a logic low signal on the alert signal line. The document alternatively contemplates a polling scheme wherein a RH indicia stored on the DRAM device is modified to indicate to the host apparatus via polling that an RH attack has been detected.

The invention provides a DRAM device and a system as claimed hereinafter.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:.

Embodiments of methods and apparatus for row hammer mitigation and recovery are described herein. In the following description, numerous specific details are set forth (such as to provide a thorough understanding of embodiments of the invention.

In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

For clarity, individual components in the Figures herein may also be referred to by their labels in the Figures, rather than by a particular reference number. Additionally, reference numbers referring to a particular type of component (as opposed to a particular component) may be shown with a reference number followed by "(typ)" meaning "typical. " It will be understood that the configuration of these components will be typical of similar components that may exist but are not shown in the drawing Figures for simplicity and clarity or otherwise similar components that are not labeled with separate reference numbers. Conversely, "(typ)" is not to be construed as meaning the component, element, etc. is typically used for its disclosed function, implement, purpose, etc..

To better understand aspects of the teachings and principles of the embodiments disclosed herein, a brief primer on the operation of DRAM is provided with reference an exemplary memory subsystem illustrated in <FIG> and <FIG>. As shown in <FIG>, selective elements of a memory subsystem <NUM> include a memory controller <NUM> coupled to a DIMM <NUM> showing two ranks of DRAM devices <NUM>. Generally, a DRAM DIMM may have one or more ranks. Each DRAM device includes a plurality of banks comprising an array of DRAM cells <NUM> that are organized (laid out) and as rows and columns. Each row comprises a Wordline (or wordline), while each column comprises a Bitline (or bitline). Each DRAM device <NUM> further includes control logic <NUM> and sense amps <NUM> that are used to access DRAM cells <NUM>.

As further shown in <FIG>, memory controller provides inputs comprising address/commands <NUM> and chip select <NUM>. For memory Writes, the memory controller inputs further include data <NUM> that are written to DRAM cells <NUM> based on the address and chip select inputs. Similarly, for memory Reads, data <NUM> stored in DRAM cells <NUM> identified by the address and chip select inputs is returned to memory controller <NUM>.

As described herein, reference to memory devices being DRAM devices can apply to different dynamic volatile memory types. Volatile memory is memory whose state (and therefore the data stored on it) is indeterminate if power is interrupted to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain state. One example of dynamic volatile memory includes DRAM, or some variant such as synchronous DRAM (SDRAM). A memory subsystem as described herein may be compatible with a number of memory technologies or standards, such as DDR3 (<NPL>), DDR4 (<NPL>), LPDDR3 (<NPL>), LPDDR4 (<NPL>), WIO2 (<NPL>), HBM (<NPL>), <NPL>), HBM2 ((<NPL>), DDR5 (<NPL>), or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

Under conventional (S)DRAM memory, data are generally accessed (Read and Written) using cachelines (also called cache lines) comprising a sequence of memory cells (bits) in a wordline. The cachelines for a given memory architecture generally have a predetermined width or size, such as <NUM> Bytes, noting other widths/sizes maybe used.

Referring to <FIG>, the DRAM device <NUM> structure includes a bank <NUM> including an array of memory cells called bitcells organized as wordlines and bitlines. A bitcell may have an open state or closed state (or otherwise have a capacitor that is charged or uncharged). A bitline pre-charge <NUM> and a word inline decoder <NUM> are coupled to bank <NUM>. A bitline decoder <NUM> is used for selecting bitlines. An optional bitline mux (multiplexer) <NUM> may be used to multiplex the outputs of sense amps <NUM>.

To change the logic level for a cell, the cell's transistor is used to charge or discharge the capacitor. A charged capacitor represents a logic high, or '<NUM>', while a discharged capacitor represents a logic low, or '<NUM>'. The charging/discharging is done via the wordline and bitline. During a read or write, the wordline goes high and the transistor connects the capacitor to the bitline. Whatever value is on the bitline ('<NUM>' or '<NUM>') gets stored or retrieved from the capacitor. Thus, to access data in a given row, the wordline for the row is activated (this is also referred to as row activation).

Generally, the charge stored on each capacitor is too small to be read directly and is instead measured by a sense amplifier (e.g., sense amps <NUM>). The sense amplifier detects the minute differences in charge and outputs the corresponding logic level. The act of reading from the bitline forces the charge to flow out of the capacitor. Thus, in DRAM, Reads are destructive. To get around this, an operation known as precharging is done to put the value read from the bitline back into the capacitor.

Equally problematic is the fact that the capacitors leak charge over time. Therefore, to maintain the data stored in memory the capacitors must be refreshed periodically. Refreshing works just like a read and ensures data is never lost. This is where DRAM gets the "Dynamic" moniker from-the charge on a DRAM cell is dynamically refreshed every so often (e.g., every <NUM>).

Under an RH attack, row or rows adjacent to a targeted row is/are read at a very high frequency. This results in repeated activation of the wordline(s) for the/those row(s). Under one embodiment, means are provided for detecting RH attacks on a DRAM die, such as depicted by an RH detector <NUM> in <FIG>. Under one approach the RH detector is configured to count the number of activations of individual rows/wordlines within a configurable timeframe. If the number of activations exceeds some critical threshold (as applied to the timeframe), an RH attack is detected. For example, in one implementation the number of activations is <NUM> within <NUM> microseconds (us). Generally, the timeframe and count threshold may vary as a function of the memory bandwidth and/or other considerations.

In accordance with aspects of the embodiments disclosed herein, two RH mitigation and prevention modes are provided in DRAM: <NUM>) ALERT_n; and <NUM>) polling. Under one aspect of polling, the CPU/host (e.g., memory controller) can change a DRAM RH counter threshold to a tighter value than under ALERT_n to enable earlier RH mitigation and recovery operations. In one embodiment, the ALERT_n and polling modes are selectable by toggling bit states in a mode register.

In addition to RH mitigation/prevention, a Central Processing Unit (CPU) and/or other host (e.g., memory controller) should be able to cater to Isochronous traffic (Quality of Service requirement for guaranteed bandwidth and bounded latency) bandwidth during RH mitigation. Accordingly, some embodiments provide RH mitigation and prevention while supporting Isochronous traffic bandwidth by limiting the number of ACTs that are allowed during RH recovery. Also, a novel RH handshaking method of RH polling between CPU/host and DRAM is provided.

Under various embodiments, DRAM that supports on-die RH mitigation (such as but not limited to DDR5 DRAM) may request a CPU host to back off so that it can keep up with the on-die RH mitigation. Two separate methods are provided for a handshake between DRAM and host. One is to use ALERT_n signal and the other is to poll a Mode Register (MR) bit in a mode register indicating the level of row hammering has reached a critical threshold. In one embodiment, a mode register bit or bits are used to enable the RH back off feature and then select one of the above two methods (ALERT_n or Polling) disclosed herein.

For a Row Hammer triggered Alert_n, DDRS DRAM that supports on-die row hammer mitigation uses an ALERT_n signal to provide better protection against attacks. The ALERT_n signal is an active low signal that is provided at a pin on the controller. Under this technique, DRAM asserts the ALERT_n signal and sets an MR bit in a mode register indicating that ALERT_n is asserted as part of RH mitigation. In one embodiment the DRAM continues to execute all commands (received from the controller) while ALERT_n is asserted so the DRAM internal state on a rank stays synchronized with other DRAMs on the same rank. This will mitigate any requirements on a host to replay commands. In addition, the host continues to send refresh commands while in an ALERT_n recovery state (also referred to an an RH mitigation state).

In one embodiment, an ALERT_n signal asserted in response to detection of an RH has a minimum pulse width of tRH_ALERT_PW_min. Generally, the ALERT_n signal pin may be used for other ALERT_n assertions, such as DQ CRC or Command Address (CA) parity errors from the Registered Clock Driver (RCD) (e.g., see DDR4 and DDR5 DRAM specifications) The use of tRH_ALERT_PW_min helps the host to distinguish an ALERT_n asserted in response to detection of an RH attack detection from ALERTs asserted for write DQ CRC or Command Address (CA) parity errors. This assumes that RCD is programmed for pulse width mode for CA parity errors. The host may optionally read the MR status to figure out the source of an ALERT_n assertion.

If the ALERT_n is still low at the end of tRH_ALERT_PW_min then the host will send multiple RFM (Refresh Management) commands as defined by the value for RH_RFM in TABLE <NUM> below. The DRAM de-asserts ALERT_n after it has caught up with internal RH mitigation. Upon sampling ALERTn high, the host will stop sending additional RFM commands. The DRAM also clears the MR bit that indicates RH mitigation is needed.

Another aspect of the RH mitigation methods disclosed herein is the ability to support isochronous traffic bandwidth during the RH mitigation/recovery operations. During the RH mitigation, in a system with RCD, a host will (or may) issue only RFM (Refresh management) and REF (Refresh) commands during the RH mitigation. Conversely, in a system without RCD, during the RH mitigation a host can issue normal DRAM commands to DRAM. However, the number of Activates are restricted by "RH_ACT" in TABLE <NUM>.

<FIG> shows a timing diagram <NUM> illustrating an example implementation of the RH back off protocol using ALERT_n. A clock timing diagram (<NUM>) illustrating the states for CK_c and CK_t clock inputs is shown at the top <FIG>, along with time indicators, such as T0, T1, T2, etc, for each clock cycle. The 'S' shaped symbols in the figures herein including <FIG> show breaks in the timeline, since an actual timeline over the time period depicted might have <NUM>'s of thousands of clock cycles. The middle section of the diagram depicts Activations (ACT) or Refreshes (REF) <NUM>, and RFMs <NUM> and <NUM>. The state (logic level) of the ALERT_n signal <NUM> is shown in the lower portion of timing diagram <NUM>.

At time Ta0 the DRAM detects an RH attack and asserts ALERT_n, which changes the logic level of ALERTn signal <NUM> from high to low. In addition to the change of the ALERT_n logic level, an MR bit is set to indicate RH mitigation is needed. As further shown, this begins a tRH_ALERT_PW (RH_ALERT pulsewidth) time period <NUM> and tRH_ALERT_PW_min time period <NUM>. At the end of tRH_ALERT_PW_min time period <NUM> the host has determined the ALERT_n assertion corresponds to an RH attack and begins an RH mitigation/recovery period by de-asserting ALERT_n (returning the logic level to '<NUM>'. During RH mitigation/recovery the host sends RFMs <NUM> and <NUM>. As depicted, the host should send RFM at least as many as RH_RFM. During RH mitigation/recovery, the number of activations for the row is restricted by the RH_ACT value in TABLE <NUM>.

In some embodiments, PDE (Power down enable)/PDX (Power down exit) and SREF (Self-refresh entry)/SRX (Self-refresh exit) are allowed during RH mitigation. In PDE/PDX, DRAM continues to assert ALERT_n, while the host will continue mitigation after exiting the power down state. In SREF mode, DRAM stops driving ALERT_n as low. Upon SRX, if DRAM still needs the host to back off then it will assert ALERT_n to continue mitigation.

In one embodiment a tRH_ALERT_Delay parameter is used to define the minimum amount of time before DRAM can (re)assert ALERT_n. Example values for the tRH_ALERT_DELAY parameter are shown in TABLE <NUM> below.

<FIG> shows a timing diagram <NUM> illustrating the logic states of an ALERT_n signal <NUM> during tRH_ALERT_PW periods <NUM> and <NUM> and a tRH_ALERT_Delay period <NUM>. A similar pattern may be repeated.

PDE (Power down enable)/PDX (Power down exit) and SREF (Self-refresh entry)/SRX (Self-refresh exit) are allowed during RH mitigation. In PDE/PDX, DRAM continues to assert ALERT_n'. Host will continue mitigation after exiting power down state.

In SREF mode, DRAM stops driving ALERT_n as low. Upon SRX, if DRAM still needs host to back off then it will assert ALERT_n to continue mitigation.

Under the Row Hammer polling method, DRAM can request host assistance for row hammer mitigation is by using polling. DRAM sets a MR bit a mode register indicating that it has reached a critical threshold. In one embodiment, the host polls every tRH_Poll to check the status of the bit. As shown in TABLE <NUM> below, tRH_Poll is a parameter that may be changed. If the MR bit is set, then the recovery method is similar to the ALERT_n based method discussed above. The host sends multiple RFM commands as defined by RH_RFM in TABLE <NUM>. The host will also read the MR status to check if DRAM has cleared the bit before it stops sending RFM commands. The host continues to send refresh commands while in row hammer recovery state.

Combination timing and flow diagrams illustrating examples of the RH polling method are shown in <FIG> and <FIG>. As before, clock signals for CK_c and CK_t are shown at the top of the diagram, along with relative time values. An MR bit logic state <NUM> is shown in the lower part of the timing diagram portion of <FIG>. While the MR bit logic state is '<NUM>' (i.e., cleared), normal memory access operations are enabled, such as activations and refreshes <NUM>.

Periodically, logic in the DRAM die or on the DRAM DIMM will poll the MR bit using a tRH_Poll polling interval <NUM> based on the value of tRH_Poll. During the first poll shown, the MR bit state is cleared. Subsequently, a time Tb0, a RH critical threshold s reached. For example, the critical threshold begins at <NUM> activations in one embodiment (where those <NUM> activations would be within a given sampling period having a predetermined duration). In response to reaching the RH critical threshold, the MR bit state is set (i.e., logic '<NUM>').

At this time, normal memory operations continue to be enabled until a second polling occurs, where the time between when the MR bit state is set and the MR bit is polled represents a variable length polling delay <NUM>. The polling delay is variable because while the tRH_Poll polling interval <NUM> is periodic, the RH critical threshold condition may occur at any time thus is asynchronous to the polling. As a result, when the polling delay will the difference between which an RH critical threshold condition is reached and when the next MR pit poll occurs. Note, polling delay <NUM> will always be less that tRH_Poll polling interval <NUM>.

Upon polling a set MR bit state, the host will initiate an RH mitigation/recovery over a tRH_Mitigation_PW period <NUM>. The RH mitigation/recovery is similar to that shown in <FIG> for the ALERT_n method, including use of RFMs <NUM> and <NUM>, where restrictions for RFMs and RH_ACT are defined in TABLE <NUM>. At the conclusion of the tRH_Mitigation_PW <NUM> the host clears the MR bit to return its logic state to '<NUM>'. In one embodiment, tRH_Mitigation_PW <NUM> is a parameter managed by the host that can be modified.

As shown by the flow diagram portion of <FIG>, the MR bit is periodically polled in a block <NUM> using the rRH_Poll polling period. In a decision block <NUM> a determination is made to whether the MR bit is set. If it is not set, the answer to decision block <NUM> is NO and the logic loops back to block <NUM> to perform a next MR bit poll at the end of the next rRH_Poll polling period. If the MR bit is set, the answer to decision block <NUM> is YES, and the logic proceeds to perform RH mitigation and recovery in a block <NUM> during the tRH_Mitigation_PW period <NUM>. Upon completion of the RH mitigation and recovery period the MR bit is cleared in a block <NUM> and the logic returns to perform the next MR bit poll in block <NUM>.

As discussed and illustrated above, polling delay <NUM> will be variable. This polling delay may result in excessive RH activations before RH mitigation and recovery begins. This can be addressed in two ways: reduce tRH_Poll and/or reduce the RH critical threshold value. Under one embodiment, if a counter-based scheme such as perfect row hammer tracking (PRHT) is used where DRAM tracks the number of activates to any given row, then the DRAM will set the counter threshold to a lower value than used under the ALERT_n method. This will result in the host detecting the MR bit is set earlier. For example, suppose the rRC=60ns and the host is polling every tRH_Poll or <NUM>. If the threshold is reduced by <NUM>, the MR bit set condition will be determined earlier.

An example of the result of reducing the RH critical threshold is shown in <FIG>, where the timeline value have been shifted (relative to those shown in <FIG>). In this example, since the RH critical threshold is reduced in <FIG>, the RH critical threshold condition occurs earlier at time Ta0 rather than time Tb0.

Under one embodiment of the polling method, the DRAM can provide the bank address (or addresses) that needs mitigation. This will allow host to send RFMpb (RFM per bank) commands as opposed to all bank commands. DRAM can also provide a count of the number of RFM commands needed for mitigation. This will help for more precise mitigation method without requiring the host to continuously poll to see if DRAM has caught up with the internal mitigation.

The embodiments described and illustrated herein provide several advantages over existing approaches. By having two RH modes the DRAM logic supporting these two modes can be implemented in systems with or without an ALERT_n pin. The polling mode also provides flexibility by tailoring the RH critical threshold values. The embodiments also have adjustable parameters to cater to isochronous traffic bandwidth during the RH mitigation/recovery operations.

<FIG> illustrates an example system <NUM>. In some examples, as shown in <FIG>, system <NUM> includes a processor and elements of a memory subsystem in a computing device. Processor <NUM> represents a processing unit of a computing system that may execute an operating system (OS) and applications, which can collectively be referred to as the host or the user of the memory subsystem. The OS and applications execute operations that result in memory accesses. Processor <NUM> can include one or more separate processors. Each separate processor may include a single processing unit, a multicore processing unit, or a combination. The processing unit may be a primary processor such as a central processing unit (CPU), a peripheral processor such as a graphics processing unit (GPU), or a combination. Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices may be integrated with the processor in some systems or attached to the processer via a bus (e.g., a PCI express bus), or a combination. System <NUM> may be implemented as a system on a chip (SOC) or may be implemented with standalone components.

Descriptions referring to a "DRAM", "SDRAM, "DRAM device" or "SDRAM device" refer to a DRAM device.

The memory device, SDRAM or DRAM may refer to the die itself, to a packaged memory product that includes one or more dies, or both. In some examples, a system with volatile memory that needs to be refreshed may also include at least some nonvolatile memory.

Memory controller <NUM>, as shown in <FIG>, may represent one or more memory controller circuits or devices for system <NUM>. Also, memory controller <NUM> may include logic and/or features that generate memory access commands in response to the execution of operations by processor <NUM>. In some examples, memory controller <NUM> may access one or more memory device(s) <NUM>. Memory device(s) <NUM> are SDRAM or DRAM devices in accordance with any referred to above. Memory device(s) <NUM> may be organized and managed through different channels, where these channels may couple in parallel to multiple memory devices via buses and signal lines. Each channel may be independently operable. Thus, separate channels may be independently accessed and controlled, and the timing, data transfer, command and address exchanges, and other operations may be separate for each channel. Coupling may refer to an electrical coupling, communicative coupling, physical coupling, or a combination of these. Physical coupling may include direct contact. Electrical coupling, for example, includes an interface or interconnection that allows electrical flow between components, or allows signaling between components, or both. Communicative coupling, for example, includes connections, including wired or wireless, that enable components to exchange data.

According to some examples, settings for each channel are controlled by separate mode registers or other register settings. For these examples, memory controller <NUM> may manage a separate memory channel, although system <NUM> may be configured to have multiple channels managed by a single memory controller, or to have multiple memory controllers on a single channel. In one example, memory controller <NUM> is part of processor <NUM>, such as logic and/or features of memory controller <NUM> are implemented on the same die or implemented in the same package space as processor <NUM>, sometimes referred to as an integrated memory controller or IMC.

Memory controller <NUM> includes Input/Output (I/O) interface circuitry <NUM> to couple to a memory bus, such as a memory channel as referred to above. I/O interface circuitry <NUM> (as well as I/O interface circuitry <NUM> of memory device(s) <NUM>) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware to connect the devices, or a combination of these. I/O interface circuitry <NUM> may include a hardware interface. As shown in <FIG>, I/O interface circuitry <NUM> includes at least drivers/transceivers for signal lines. Commonly, wires within an integrated circuit interface couple with a pad, pin, or connector to interface signal lines or traces or other wires between devices. I/O interface circuitry <NUM> can include drivers, receivers, transceivers, or termination, or other circuitry or combinations of circuitry to exchange signals on the signal lines between memory controller <NUM> and memory device(s) <NUM>. The exchange of signals includes at least one of transmit or receive. While shown as coupling I/O interface circuitry <NUM> from memory controller <NUM> to I/O interface circuitry <NUM> of memory device(s) <NUM>, it will be understood that in an implementation of system <NUM> where groups of memory device(s) <NUM> are accessed in parallel, multiple memory devices can include I/O interface circuitry to the same interface of memory controller <NUM>. In an implementation of system <NUM> including one or more memory module(s) <NUM>, I/O interface circuitry <NUM> may include interface hardware of memory module(s) <NUM> in addition to interface hardware for memory device(s) <NUM>. Other memory controllers <NUM> may include multiple, separate interfaces to one or more memory devices of memory device(s) <NUM>.

In some examples, memory controller <NUM> may be coupled with memory device(s) <NUM> via multiple signal lines. The multiple signal lines may include at least a clock (CLK) <NUM>, a command/address (CMD) <NUM>, and write data (DQ) and read data (DQ) <NUM>, and zero or more other signal lines <NUM>. According to some examples, a composition of signal lines coupling memory controller <NUM> to memory device(s) <NUM> may be referred to collectively as a memory bus. The signal lines for CMD <NUM> may be referred to as a "command bus", a "C/A bus" or an ADD/CMD bus, or some other designation indicating the transfer of commands. The signal lines for DQ <NUM> may be referred to as a "data bus".

According to some examples, independent channels may have different clock signals, command buses, data buses, and other signal lines. For these examples, system <NUM> may be considered to have multiple "buses," in the sense that an independent interface path may be considered a separate bus. It will be understood that in addition to the signal lines shown in <FIG>, a bus may also include at least one of strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or a combination of these additional signal lines. It will also be understood that serial bus technologies can be used for transmitting signals between memory controller <NUM> and memory device(s) <NUM>. An example of a serial bus technology is 8B10B encoding and transmission of high-speed data with embedded clock over a single differential pair of signals in each direction. In some examples, CMD <NUM> represents signal lines shared in parallel with multiple memory device(s) <NUM>. In other examples, multiple memory devices share encoding command signal lines of CMD <NUM>, and each has a separate chip select (CS_n) signal line to select individual memory device(s) <NUM>.

In some examples, the bus between memory controller <NUM> and memory device(s) <NUM> includes a subsidiary command bus routed via signal lines included in CMD <NUM> and a subsidiary data bus to carry the write and read data routed via signal lines included in DQ <NUM>. In some examples, CMD <NUM> and DQ <NUM> may separately include bidirectional lines. In other examples, DQ <NUM> may include unidirectional write signal lines to write data from the host to memory and unidirectional lines to read data from the memory to the host.

According to some examples, in accordance with a chosen memory technology and system design, signals lines included in other <NUM> may augment a memory bus or subsidiary bus. For example, strobe line signal lines for a DQS. Based on a design of system <NUM>, or memory technology implementation, a memory bus may have more or less bandwidth per memory device included in memory device(s) <NUM>. The memory bus may support memory devices included in memory device(s) <NUM> that have either a x32 interface, a x16 interface, a x8 interface, or other interface. The convention "xW," where W is an integer that refers to an interface size or width of the interface of memory device(s) <NUM>, which represents a number of signal lines to exchange data with memory controller <NUM>. The interface size of these memory devices may be a controlling factor on how many memory devices may be used concurrently per channel in system <NUM> or coupled in parallel to the same signal lines. In some examples, high bandwidth memory devices, wide interface memory devices, or stacked memory devices, or combinations, may enable wider interfaces, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface width.

According to some examples, memory device(s) <NUM> represent memory resources for system <NUM>. For these examples, each memory device included in memory device(s) <NUM> is a separate memory die. Separate memory devices may interface with multiple (e.g., <NUM>) channels per device or die. A given memory device of memory device(s) <NUM> may include I/O interface circuitry <NUM> and may have a bandwidth determined by an interface width associated with an implementation or configuration of the given memory device (e.g., x16 or x8 or some other interface bandwidth). I/O interface circuitry <NUM> may enable the memory devices to interface with memory controller <NUM>. I/O interface circuitry <NUM> may include a hardware interface and operate in coordination with I/O interface circuitry <NUM> of memory controller <NUM>.

In some examples, multiple memory device(s) <NUM> may be connected in parallel to the same command and data buses (e.g., via CMD <NUM> and DQ636). In other examples, multiple memory device(s) <NUM> may be connected in parallel to the same command bus but connected to different data buses. For example, system <NUM> may be configured with multiple memory device(s) <NUM> coupled in parallel, with each memory device responding to a command, and accessing memory resources <NUM> internal to each memory device. For a write operation, an individual memory device of memory device(s) <NUM> may write a portion of the overall data word, and for a read operation, the individual memory device may fetch a portion of the overall data word. As non-limiting examples, a specific memory device may provide or receive, respectively, <NUM> bits of a <NUM>-bit data word for a read or write operation, or <NUM> bits or <NUM> bits (depending for a x8 or a x16 device) of a <NUM>-bit data word. The remaining bits of the word may be provided or received by other memory devices in parallel.

According to some examples, memory device(s) <NUM> may be disposed directly on a motherboard or host system platform (e.g., a PCB (printed circuit board) on which processor <NUM> is disposed) of a computing device. Memory device(s) <NUM> may be organized into memory module(s) <NUM>. In some examples, memory module(s) <NUM> may represent dual inline memory modules (DIMMs). In some examples, memory module(s) <NUM> may represent other organizations or configurations of multiple memory devices that share at least a portion of access or control circuitry, which can be a separate circuit, a separate device, or a separate board from the host system platform. In some examples, memory module(s) <NUM> may include multiple memory device(s) <NUM>, and memory module(s) <NUM> may include support for multiple separate channels to the included memory device(s) <NUM> disposed on them.

In some examples, memory device(s) <NUM> may be incorporated into a same package as memory controller <NUM>. For example, incorporated in a multi-chip-module (MCM), a package-on-package with through-silicon via (TSV), or other techniques or combinations. Similarly, in some examples, memory device(s) <NUM> may be incorporated into memory module(s) <NUM>, which themselves may be incorporated into the same package as memory controller <NUM>. It will be appreciated that for these and other examples, memory controller <NUM> may be part of or integrated with processor <NUM>.

As shown in <FIG>, in some examples, memory device(s) <NUM> include memory resources <NUM>. Memory resources <NUM> may represent individual arrays of memory locations or storage locations for data. Memory resources <NUM> may be managed as rows of data, accessed via wordline (rows) and bitline (individual bits within a row) control. Memory resources <NUM> may be organized as separate channels, ranks, and banks of memory. Channels may refer to independent control paths to storage locations within memory device(s) <NUM>. Ranks may refer to common locations across multiple memory devices (e.g., same row addresses within different memory devices). Banks may refer to arrays of memory locations within a given memory device of memory device(s) <NUM>. Banks may be divided into sub-banks with at least a portion of shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks, allowing separate addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other organizations of the memory locations, and combinations of the organizations, can overlap in their application to access memory resources <NUM>. For example, the same physical memory locations can be accessed over a specific channel as a specific bank, which can also belong to a rank. Thus, the organization of memory resources <NUM> may be understood in an inclusive, rather than exclusive, manner.

According to some examples, as shown in <FIG>, memory device(s) <NUM> include one or more register(s) <NUM>. Register(s) <NUM> may represent one or more storage devices or storage locations that provide configuration or settings for operation memory device(s) <NUM>. In one example, register(s) <NUM> may provide a storage location for memory device(s) <NUM> to store data for access by memory controller <NUM> as part of a control or management operation. For example, register(s) <NUM> may include one or more mode registers (MRs) <NUM> and/or may include one or more multipurpose registers.

In some examples, writing to or programming one or more registers of register(s) <NUM> may configure memory device(s) <NUM> to operate in different "modes". For these examples, command information written to or programmed to the one or more register may trigger different modes within memory device(s) <NUM>. Additionally, or in the alternative, different modes can also trigger different operations from address information or other signal lines depending on the triggered mode. Programmed settings of register(s) <NUM> may indicate or trigger configuration of I/O settings. For example, configuration of timing, termination, on-die termination (ODT), driver configuration, or other I/O settings.

In some examples, as shown in <FIG>, memory device(s) <NUM> includes controller <NUM>. Controller <NUM> may represent control logic within memory device(s) <NUM> to control internal operations within memory device(s) <NUM>. For example, controller <NUM> decodes commands sent by memory controller <NUM> and generates internal operations to execute or satisfy the commands. Controller <NUM> may be referred to as an internal controller and is separate from memory controller <NUM> of the host. Controller <NUM> may include logic and/or features to determine what mode is selected based on programmed or default settings indicated in register(s) <NUM> and configure the internal execution of operations for access to memory resources <NUM> or other operations based on the selected mode. Controller <NUM> generates control signals to control the routing of bits within memory device(s) <NUM> to provide a proper interface for the selected mode and direct a command to the proper memory locations or addresses of memory resources <NUM>. Controller <NUM> includes command (CMD) logic <NUM>, which can decode command encoding received on command and address signal lines. Thus, CMD logic <NUM> can be or include a command decoder. With command logic <NUM>, memory device can identify commands and generate internal operations to execute requested commands.

Referring again to memory controller <NUM>, memory controller <NUM> includes CMD logic <NUM>, which represents logic and/or features to generate commands to send to memory device(s) <NUM>. The generation of the commands can refer to the command prior to scheduling, or the preparation of queued commands ready to be sent. Generally, the signaling in memory subsystems includes address information within or accompanying the command to indicate or select one or more memory locations where memory device(s) <NUM> should execute the command. In response to scheduling of transactions for memory device(s) <NUM>, memory controller <NUM> can issue commands via I/O interface circuitry <NUM> to cause memory device(s) <NUM> to execute the commands. In some examples, controller <NUM> of memory device(s) <NUM> receives and decodes command and address information received via I/O interface circuitry <NUM> from memory controller <NUM>. Based on the received command and address information, controller <NUM> may control the timing of operations of the logic, features and/or circuitry within memory device(s) <NUM> to execute the commands. Controller <NUM> may be arranged to operate in compliance with standards or specifications such as timing and signaling requirements for memory device(s) <NUM>. Memory controller <NUM> may implement compliance with standards or specifications by access scheduling and control.

In some examples, memory controller <NUM> includes refresh (REF) logic <NUM>. REF logic <NUM> may be used for memory resources that are volatile and need to be refreshed to retain a deterministic state. REF logic <NUM>, for example, may indicate a location for refresh, and a type of refresh to perform. REF logic <NUM> may trigger self-refresh within memory device(s) <NUM> or execute external refreshes which can be referred to as auto refresh commands by sending refresh commands, or a combination. According to some examples, system <NUM> supports all bank refreshes as well as per bank refreshes. All bank refreshes cause the refreshing of banks within all memory device(s) <NUM> coupled in parallel. Per bank refreshes cause the refreshing of a specified bank within a specified memory device of memory device(s) <NUM>. In some examples, controller <NUM> within memory device(s) <NUM> includes a REF logic <NUM> to apply refresh within memory device(s) <NUM>. REF logic <NUM>, for example, may generate internal operations to perform refresh in accordance with an external refresh received from memory controller <NUM>. REF logic <NUM> may determine if a refresh is directed to memory device(s) <NUM> and determine what memory resources <NUM> to refresh in response to the command.

Memory device(s) <NUM> further include logic for implementing the DRAM-side of the RH ALERT_n and RH polling methods described and illustrated herein, as depicted by RH ALERT_n mode logic <NUM> and RH Polling mode logic <NUM>. Parameters in TABLES <NUM>-<NUM> above may be part of these logic blocks or may be stored elsewhere, such as in registers <NUM>.

As further illustrated, memory controller <NUM> includes host-side RH mitigation/recovery mode logic <NUM> including RH ALERT_n mode logic <NUM> and RH polling mode logic <NUM>. This logic is used to perform the host-side aspects of the RH ALERT_n and RH polling modes described herein. Although shown as part of memory controller <NUM>, all or a portion of the host-side RH mitigation/recovery mode logic may be implemented on processor <NUM> when memory controller <NUM> is not integrated on processor <NUM>.

<FIG> illustrates an example compute platform <NUM> in which aspects of the embodiments may be practiced. Compute platform <NUM> represents a computing device or computing system in accordance with any example described herein, and can be a server, laptop computer, desktop computer, or the like. More generally, compute platform <NUM> is representative of any type of computing device or system employing DRAM DIMMs.

Compute platform <NUM> includes a processor <NUM>, which provides processing, operation management, and execution of instructions for compute platform <NUM>. Processor <NUM> can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for compute platform <NUM>, or a combination of processors. Processor <NUM> controls the overall operation of compute platform <NUM>, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

In one example, compute platform <NUM> includes interface <NUM> coupled to processor <NUM>, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem <NUM> or graphics interface components <NUM>. Interface <NUM> represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface <NUM> interfaces to graphics components for providing a visual display to a user of compute platform <NUM>. In one example, graphics interface <NUM> can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately <NUM> PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, <NUM> (ultrahigh definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface <NUM> generates a display based on data stored in memory <NUM> or based on operations executed by processor <NUM> or both.

Memory subsystem <NUM> represents the main memory of compute platform <NUM> and provides storage for code to be executed by processor <NUM>, or data values to be used in executing a routine. Memory <NUM> of memory subsystem <NUM> may include one or more memory devices such as DRAM DIMMs, read-only memory (ROM), flash memory, or other memory devices, or a combination of such devices. Memory <NUM> stores and hosts, among other things, operating system (OS) <NUM> to provide a software platform for execution of instructions in compute platform <NUM>. Additionally, applications <NUM> can execute on the software platform of OS <NUM> from memory <NUM>. Applications <NUM> represent programs that have their own operational logic to perform execution of one or more functions. Processes <NUM> represent agents or routines that provide auxiliary functions to OS <NUM> or one or more applications <NUM> or a combination. OS <NUM>, applications <NUM>, and processes <NUM> provide software logic to provide functions for compute platform <NUM>. In one example, memory subsystem <NUM> includes memory controller <NUM>, which is a memory controller to generate and issue commands to memory <NUM>. It will be understood that memory controller <NUM> could be a physical part of processor <NUM> or a physical part of interface <NUM>. For example, memory controller <NUM> can be an integrated memory controller, integrated onto a circuit with processor <NUM>.

While not specifically illustrated, it will be understood that compute platform <NUM> can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard <NUM> bus.

In one example, compute platform <NUM> includes interface <NUM>, which can be coupled to interface <NUM>. Interface <NUM> can be a lower speed interface than interface <NUM>. In one example, interface <NUM> represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface <NUM>. Network interface <NUM> provides compute platform <NUM> the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface <NUM> can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface <NUM> can exchange data with a remote device, which can include sending data stored in memory or receiving data to be stored in memory.

In one example, compute platform <NUM> includes one or more I/O interface(s) <NUM>. I/O interface(s) <NUM> can include one or more interface components through which a user interacts with compute platform <NUM> (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface <NUM> can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to compute platform <NUM>. A dependent connection is one where compute platform <NUM> provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, compute platform <NUM> includes storage subsystem <NUM> to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage subsystem <NUM> can overlap with components of memory subsystem <NUM>. Storage subsystem <NUM> includes storage device(s) <NUM>, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage device(s) <NUM> holds code or instructions and data <NUM> in a persistent state (i.e., the value is retained despite interruption of power to compute platform <NUM>). A portion of the code or instructions may comprise platform firmware that is executed on processor <NUM>. Storage device(s) <NUM> can be generically considered to be a "memory," although memory <NUM> is typically the executing or operating memory to provide instructions to processor <NUM>. Whereas storage device(s) <NUM> is nonvolatile, memory <NUM> can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to compute platform <NUM>). In one example, storage subsystem <NUM> includes controller <NUM> to interface with storage device(s) <NUM>. In one example controller <NUM> is a physical part of interface <NUM> or processor <NUM> or can include circuits or logic in both processor <NUM> and interface <NUM>.

Compute platform <NUM> may include an optional Baseboard Management Controller (BMC) <NUM> that is configured to effect the operations and logic corresponding to the flowcharts disclosed herein. BMC <NUM> may include a microcontroller or other type of processing element such as a processor core, engine or micro-engine, that is used to execute instructions to effect functionality performed by the BMC. Optionally, another management component (standalone or comprising embedded logic that is part of another component) may be used.

Power source <NUM> provides power to the components of compute platform <NUM>. More specifically, power source <NUM> typically interfaces to one or multiple power supplies <NUM> in compute platform <NUM> to provide power to the components of compute platform <NUM>. In one example, power supply <NUM> includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source <NUM>. In one example, power source <NUM> includes a DC power source, such as an external AC to DC converter. In one example, power source <NUM> can include an internal battery or fuel cell source.

Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.

In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Additionally, "communicatively coupled" means that two or more elements that may or may not be in direct contact with each other, are enabled to communicate with each other. For example, if component A is connected to component B, which in turn is connected to component C, component A may be communicatively coupled to component C using component B as an intermediary component.

An embodiment is an implementation or example of the inventions. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments.

If the specification states a component, feature, structure, or characteristic "may", "might", "can" or "could" be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the element.

An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

As discussed above, various aspects of the embodiments herein may be facilitated by corresponding software and/or firmware components and applications, such as software and/or firmware executed by an embedded processor or the like. Thus, embodiments of this invention may be used as or to support a software program, software modules, firmware, and/or distributed software executed upon some form of processor, processing core or embedded logic a virtual machine running on a processor or core or otherwise implemented or realized upon or within a non-transitory computer-readable or machine-readable storage medium. A non-transitory computer-readable or machine-readable storage medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a non-transitory computer-readable or machine-readable storage medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a computer or computing machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). The content may be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). A non-transitory computer-readable or machine-readable storage medium may also include a storage or database from which content can be downloaded. The non-transitory computer-readable or machine-readable storage medium may also include a device or product having content stored thereon at a time of sale or delivery. Thus, delivering a device with stored content, or offering content for download over a communication medium may be understood as providing an article of manufacture comprising a non-transitory computer-readable or machine-readable storage medium with such content described herein.

Various components referred to above as processes, servers, or tools described herein may be a means for performing the functions described. The operations and functions performed by various components described herein may be implemented by software running on a processing element, via embedded hardware or the like, or any combination of hardware and software. Such components may be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, ASICs, DSPs, etc.), embedded controllers, hardwired circuitry, hardware logic, etc. Software content (e.g., data, instructions, configuration information, etc.) may be provided via an article of manufacture including non-transitory computer-readable or machine-readable storage medium, which provides content that represents instructions that can be executed. The content may result in a computer performing various functions/operations described herein.

Claim 1:
A Dynamic Random Access Memory, termed DRAM, device (<NUM>), comprising:
plurality of memory cells (<NUM>) arranged in rows and columns;
input/output, termed I/O, interface circuitry (<NUM>) configured to receive signals from and send signals to an I/O interface (<NUM>) on a host apparatus, the I/O interface including an alert signal line (ALERT_n);
row hammer, termed RH, detection circuitry configured to detect a RH attack on one or more rows of memory cells
DRAM-side RH mitigation circuitry (<NUM>, <NUM>) configured to perform DRAM-side operations in connection with an RH mitigation and/or recovery process; and
means for setting an RH mode comprising one of an RH alert mode and an RH polling mode,
wherein, in response to detection of an RH attack, the DRAM device is configured to,
i) when the RH mode is set to the RH alert mode, assert a logic low signal on the alert signal line and
ii) when the RH mode is set to the RH polling mode, modify an RH indicia stored on the DRAM device to indicate to the host apparatus via polling that an RH attack has been detected.