Patent Description:
A self-luminous display element that displays an image without a color filter and a backlight may use an LED inorganic self-luminous element that emits light by itself.

The LED is operated by a thin film transistor (TFT), and is disposed on a thin film transistor substrate including a plurality of thin film transistors.

The manufactured thin film transistor substrate determines whether the manufactured thin film transistor substrate is electrically operated by applying an electrical signal to a connection pad formed on the thin film transistor substrate and transmitting the electrical signal to the LED.

However, in an electrical test of the thin film transistor substrate of a display module, when the size of the LED and the size of the corresponding connection pad are reduced, it may be difficult to conduct the electrical test of the thin film transistor substrate.

Patent document <CIT> describes an organic light emitting pixel display panel, including a pixel unit having a plurality of pixels displaying mutually different colors, a plurality of data pads electrically connected to wirings extending from data lines and a test array unit.

Provided is a display module having a thin film transistor substrate with improved electrical test convenience and manufacturing efficiency, and a manufacturing method of the display module.

There is provided a display module and a manufacturing method as defined in the independent claims that follow. Other aspects of the invention are set forth in the dependent claims.

According to an embodiment, there is provided a display module including: a glass substrate; a thin film transistor layer disposed in a first area of the glass substrate; a plurality of connection pads disposed in a second area extending from the first area of the glass substrate and electrically connected to the thin film transistor layer; a plurality of test pads disposed in a third area extending from the second area of the glass substrate and electrically connected to the plurality of connection pads, respectively; and a plurality of connection wirings electrically connecting the plurality of connection pads and the plurality of test pads.

The plurality of connection wirings may be disposed in the second and third areas of the glass substrate. The plurality of connection wirings may include at least one of molybdenum (Mo), titanium (Ti) and TiMo, and insulating layers may be disposed on upper and lower portions of the plurality of connection wirings, respectively.

The plurality of test pads may be removed after a substrate test is performed, and the plurality of test pads may be disposed in zigzag along the third area.

An area of each of the plurality of test pads may be greater than an area of each of the plurality of connection pads.

The plurality of test pads may be formed integrally with the plurality of connection pads corresponding to each other.

The display module may further include a plurality of low resistance wirings disposed between each of the plurality of test pads and the plurality of connection wirings.

The glass substrate may be a quadrangular shape, and the third area may include two adjacent side surface portions of the glass substrate.

The plurality of connection wirings includes a plurality of sub-connection wirings spaced apart from each other at a predetermined interval.

According to another embodiment, there is provided a display module including: a glass substrate; a thin film transistor layer formed on a first surface of the glass substrate; a plurality of light emitting diodes (LEDs) mounted on the thin film transistor layer; a plurality of connection pads formed on the first surface; a plurality of driving pads formed on a second surface of the glass substrate; a plurality of side wirings configured to electrically connect the plurality of connection pads and the plurality of driving pads corresponding to each of the plurality of connection pads; and a plurality of connection wirings configured to connect a plurality of connection pads and the plurality of test pads in a dummy area extending to an edge area of the glass substrate, where the plurality of test pads and a portion of each of the plurality of connection wirings corresponding to the plurality of test pads may be removed after a substrate test is performed.

The plurality of connection wirings may be electrically connected to the plurality of side wirings.

Each of the plurality of connection wirings may be covered with a first insulating layer on one surface and a second insulating layer on the other surface.

The plurality of connection pads may be formed integrally with the plurality of removed test pads, and one surface of each of the plurality of connection wirings may be connected to the plurality of connection pads.

Each of the plurality of connection wirings includes a plurality of sub-connection wirings spaced apart from each other at a predetermined interval.

According to another embodiment, there is provided a manufacturing method of a display module, the manufacturing method comprising:
forming a thin film transistor substrate layer of a thin film transistor substrate on a glass substrate; forming a plurality of test pads along a dummy area in an outer portion of the glass substrate; testing whether the thin film transistor substrate operates by contacting a test needle to the plurality of test pads; removing the dummy area including the plurality of test pads; forming a plurality of side wirings along at least one side surface of the glass substrate from which the dummy area is removed; and transferring a plurality of light emitting diodes (LEDs) on the thin film transistor layer.

The forming of the plurality of test pads further includes forming a plurality of connection wirings configured to electrically connect each of a plurality of thin film transistors and each of the plurality of test pads, on the thin film transistor layer.

The forming of the plurality of test pads may further include forming a first insulating layer on an upper portion of the plurality of connection wirings and forming a second insulating layer on a lower portion of the plurality of connection wirings.

The removing the dummy area may further include simultaneously cutting a portion of the glass substrate, the plurality of connection wirings, and the first and second insulating layers by a laser.

The manufacturing method may further include, after the removing of the dummy area, polishing the removed glass substrate along a cutting surface of the glass substrate.

The manufacturing method may further include, after the removing of the dummy area, chamfering at least one corner of a cutting surface of the glass substrate.

The forming of the plurality of side wirings may further include disposing the plurality of side wirings to connect the plurality of connection pads disposed on one surface of the glass substrate and a plurality of driving pads disposed on the other surface of the glass substrate.

The above and/or other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description with reference to the accompanying drawings, in which:.

In order to fully understand the configuration and effects of the disclosure, embodiments of the disclosure will be described with reference to the accompanying drawings. However, the disclosure is not limited to embodiments disclosed herein, but may be implemented in various forms and may be modified in various ways. However, the description of the embodiments is provided only to make the disclosure complete, and to fully inform the scope of the disclosure to those skilled in the art. In the accompanying drawings, for convenience of description, the size of the components is illustrated to be larger than the actual size, and the ratio of each component may be exaggerated or reduced.

When one component is referred to as being "on" or "in contact with" another component, it may be understood that one component may be directly in contact with or connected to another component, but also, there may be another component therebetween. On the other hand, when one component is referred to as being "directly on" or "directly in contact with" another component, it may be understood that there may not be a third component therebetween. Other expressions describing a relationship between the components, for example, "between", "directly between", and the like should be similarly interpreted.

Terms such as "first" and "second" may be used to describe various components, but the components should not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the disclosure, a first component may be referred to as a second component, and similarly, the second component may also be referred to as the first component.

Singular expressions may include plural expressions unless the context clearly indicates otherwise. The term "comprises" or "having" is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described on the specification, and that one or more other features or numbers, and it may be interpreted that steps, operations, components, parts or combinations thereof may be added.

A display module according to the disclosure may be installed and applied to a wearable device, a portable device, a handheld device, and an electronic product or an electronic device requiring various displays in a single unit, and may be applied to a display device such as a monitor for a personal computer (PC), a high resolution TV and signage (or a digital signage), an electronic display, and the like through a plurality of assembly arrangements in a matrix type.

Unless otherwise defined, terms used in the embodiments herein may be interpreted as terms commonly known to those skilled in the art.

Hereinafter, a structure of a thin film transistor substrate <NUM> according to an embodiment will be described with reference to <FIG>.

<FIG> is a top view illustrating a thin film transistor substrate <NUM> according to an embodiment and <FIG> is a cross-sectional view taken along line A-A of <FIG>.

The thin film transistor substrate <NUM> includes a glass substrate <NUM>, a plurality of thin film transistors <NUM> disposed on one surface 50a of the glass substrate <NUM>, a plurality of connection pads <NUM> electrically connected to the plurality of thin film transistors <NUM> and disposed on one surface 50a of the glass substrate <NUM>, a plurality of test pads <NUM> disposed along an edge of one surface 50a of the glass substrate <NUM>, and a connection wiring <NUM> for electrically connecting each of the plurality of connection pads <NUM> and each of the plurality of test pads <NUM>.

The thin film transistor substrate <NUM> may operate a plurality of LEDs <NUM> disposed on the thin film transistor substrate <NUM> to implement a display screen of a display device.

The thin film transistor substrate <NUM> may form a structure in which a thin film transistor layer <NUM> including the plurality of thin film transistors <NUM> is coupled onto the glass substrate <NUM>.

Accordingly, a driving driver <NUM> (shown in <FIG>) for driving the thin film transistor substrate <NUM> may be disposed on the thin film transistor substrate <NUM>. Further, the driving driver <NUM> may be implemented in the form of a chip on glass (COG) on the thin film transistor substrate <NUM>.

The glass substrate <NUM> may form a base layer of the thin film transistor substrate <NUM>, and the thin film transistor layer <NUM> may be formed on the glass substrate <NUM>.

Specifically, the thin film transistor layer <NUM> may include the plurality of thin film transistors <NUM>, the plurality of connection pads <NUM>, the plurality of test pads <NUM>, and the connection wiring <NUM>.

The thin film transistor layer <NUM> may be formed by repeating a process of laminating, etching, and the like on the glass substrate <NUM>.

The glass substrate <NUM> may have predetermined softness and may be formed of a material having a predetermined light transmittance.

The glass substrate <NUM> may have a quadrangular shape.

The thin film transistor <NUM> may be disposed on one surface 50a of the glass substrate <NUM> and may be disposed in the thin film transistor layer <NUM>.

The thin film transistor <NUM> may control and drive the plurality of LEDs <NUM> and may be electrically connected to at least one LED <NUM>.

Accordingly, the thin film transistor <NUM> may selectively drive the LED <NUM> by controlling a current flowing through the LED <NUM>. That is, the thin film transistor <NUM> may serve as a switch for controlling a pixel, which is a basic unit of a display.

For example, the thin film transistor <NUM> may be electrically connected to a first electrode pad <NUM> and a second electrode pad <NUM> disposed on the thin film transistor <NUM>.

Accordingly, the thin film transistor <NUM> that receives the electrical signal for driving the LED <NUM> from the driving driver <NUM> may control an operation of the LED <NUM> by selectively flowing a current to the LED <NUM> through the first electrode pad <NUM> and the second electrode pad <NUM>.

Further, there may be a plurality of thin film transistors <NUM> disposed in a matrix form.

In addition, the thin film transistor <NUM> may be disposed below the LED <NUM>. However, the position of the thin film transistor <NUM> is not limited thereto, but may be disposed at a position adjacent to the LED <NUM> to drive the LED <NUM>.

The plurality of connection pads <NUM> may be electrically connected to the plurality of thin film transistors <NUM> and may be arranged in a form of an L-shape on the glass substrate <NUM>. In addition, the plurality of connection pads <NUM> may be arranged along the edge of the glass substrate <NUM> or may be arranged along both edges of the glass substrate <NUM> facing each other.

For example, the plurality of connection pads <NUM> may be disposed on one side of each column and row of the plurality of LEDs <NUM> arranged in a matrix form.

Specifically, the plurality of connection pads <NUM> may include first connection pads <NUM>-<NUM> disposed in a vertical direction, that is, in at least one column, on the thin film transistor substrate <NUM>, and second connection pads <NUM>-<NUM> disposed in a horizontal direction, that is, in at least one row, on the thin film transistor substrate <NUM>.

The first connection pads <NUM>-<NUM> may be connected to a first driving driver <NUM>-<NUM> and may receive a control signal for sequentially controlling horizontal lines of the plurality of LEDs <NUM> disposed in the matrix form by one line per an image frame from the first driving driver <NUM>-<NUM>.

The second connection pads <NUM>-<NUM> may be connected to a second driving driver <NUM>-<NUM> and may receive a control signal for sequentially controlling vertical lines of the plurality of LEDs <NUM> disposed in the matrix form by one line per an image frame from the second driving driver <NUM>-<NUM>.

In addition, the connection pads <NUM> may not be included in the dummy area DA, but may be used as a reference for forming the dummy area DA. For example, the dummy area DA may include the plurality of test pads <NUM>, and may include space between each of the plurality of test pads <NUM> and each of the plurality of connection pads <NUM>. Accordingly, the dummy area DA may be spaced apart from the plurality of connection pads <NUM> by a predetermined interval, and formed along the directions in which the plurality of first connection pads <NUM>-<NUM> and the plurality of second connection pads <NUM>-<NUM> are disposed.

Further, the first connection pads <NUM>-<NUM> may be disposed in a vertical direction on the thin film transistor substrate <NUM>, and the second connection pads <NUM>-<NUM> may be disposed in a horizontal direction on the thin film transistor substrate <NUM>.

Further, the connection pad <NUM> may include a connection pad transfer part <NUM> electrically connected to the thin film transistor <NUM> and the test pad <NUM>, and a connection pad part <NUM> forming a connection surface of the connection pad <NUM>.

The connection pad transfer part <NUM> may be disposed in the thin film transistor layer <NUM>, and may transmit a signal received from the connection pad part <NUM> to the thin film transistor <NUM>.

The connection pad part <NUM> may protect the connection pad transfer part <NUM> from the outside and may be electrically connected to the connection pad transfer part <NUM> to transmit the signal received from the driving driver <NUM> to the connection pad transfer part <NUM>.

The connection pad transfer part <NUM> and the connection pad part <NUM> may be formed of a conducting material, and each of them may be made of different materials. That is, the connection pad transfer part <NUM> may be made of one material and the connection pad part <NUM> may be made of another material.

For example, the connection pad <NUM> may have a size of about <NUM> or less in length and width, respectively.

The test pads <NUM> may be disposed along an edge of one surface 50a of the glass substrate <NUM>, and are electrically connected to the connection pads <NUM> through the connection wiring <NUM>.

Here, the edge may include a side surface portion of the glass substrate <NUM> when the glass substrate <NUM> has a quadrangular shape. That is, for example, in a glass substrate <NUM> with a rectangular shape, the edge may include at least one of one vertical side surface <NUM>-<NUM> of the glass substrate <NUM> and one horizontal side surface <NUM>-<NUM> adjacent to one vertical side surface <NUM>-<NUM>.

In addition, the test pad <NUM> is not limited to the pad but may be referred to as a terminal.

Accordingly, the test pad <NUM> is electrically connected to the components included in the thin film transistor layer <NUM>, such as the connection pad <NUM> and the thin film transistor <NUM>. Therefore, it is possible to check whether the thin film transistor substrate <NUM> is electrically connected by selectively contacting an electrical needle N to the test pad <NUM>. Further, the manufacturer may check whether the manufactured thin film transistor substrate <NUM> is properly operating.

The test pad <NUM> may include a test pad transfer part <NUM>, a test pad part <NUM>, and a low resistance wiring <NUM>.

The test pad transfer part <NUM> may be disposed in the thin film transistor layer <NUM> and is electrically connected to the connection pad <NUM> through the connection wiring <NUM>. For example, the test pad transfer part <NUM> may be electrically connected to the connection pad transfer part <NUM> through the connection wiring <NUM> formed in the thin film transistor layer <NUM>.

The test pad part <NUM> may protect the test pad transfer part <NUM> from the outside and may be electrically connected to the connection pad part <NUM> to transmit the signal received from the driving driver <NUM> to the connection pad transfer part <NUM>.

The test pad transfer part <NUM> and the test pad part <NUM> may be formed of a conductor, and each of them may be made of a different material.

The low resistance wiring <NUM> may be disposed between each of the plurality of test pads <NUM> and the connection wiring <NUM>. Further, there may be a plurality of low resistance wirings <NUM> configured to be disposed between each of the plurality of test pads <NUM> and the connection wiring <NUM>.

For example, the low resistance wiring <NUM> may be disposed between the test pad transfer part <NUM> and the connection wiring <NUM>.

The low resistance wiring <NUM> may be made of a material having a lower resistance than the test pad transfer part <NUM> and the test pad part <NUM>. For example, the low resistance wiring <NUM> may be made of aluminum (Al), copper (Cu), or the like.

Accordingly, the low resistance wiring <NUM> may adjust a minimum resistance requirement value at the time of an electrical test of the thin film transistor substrate <NUM>. Therefore, by adjusting a value of a test current flowing in the thin film transistor substrate <NUM> through the low resistance wiring <NUM>, it is possible to prevent a high current flowing in the thin film transistor substrate <NUM> and damaging the components inside the thin film transistor substrate <NUM>.

Further, if the minimum resistance requirement value of the thin film transistor substrate <NUM> is not low, the low resistance wiring <NUM> may not be formed.

The test pad <NUM> may be configured in plural, and a cross-sectional area of each of the plurality of test pads <NUM> may be greater than the cross-sectional area of each of the plurality of connection pads <NUM>.

For example, the test pad <NUM> may have a quadrangular shape with a length and a width of about <NUM>. Accordingly, in the case of performing an electrical test of the manufactured thin film transistor substrate <NUM>, a test needle N may more easily be in contact with the test pad <NUM> having a greater cross-sectional area than the connection pad <NUM>.

Therefore, the electrical test of the manufactured thin film transistor substrate <NUM> may be performed more easily and the test needle N may be stably in contact with the test pad <NUM>, thereby increasing test performance and efficiency.

In addition, even if a damage occurs to the test pad <NUM> during the electrical test of the manufactured thin film transistor substrate <NUM>, the test pad <NUM> may be removed and replaced in a subsequent process. Therefore, it is possible to prevent a problem of unstable driving of the thin film transistor substrate <NUM> due to the damaged connection pad <NUM>.

In addition, the number of the plurality of test pads <NUM> may correspond to the number of the plurality of connection pads <NUM>. That is, one test pad <NUM> may be electrically connected to one connection pad <NUM>.

Therefore, by testing each of the plurality of test pads <NUM>, it is possible to test whether the components of the thin film transistor layer <NUM> connected to each of the plurality of connection pads <NUM> are properly operating.

Further, the plurality of test pads <NUM> may be disposed in zigzag configuration along the edge of the glass substrate <NUM>. Accordingly, the number of the plurality of test pads <NUM> may correspond to the number of the plurality of connection pads <NUM> and a space in which the plurality of test pads <NUM> are disposed may be minimized.

For example, because the plurality of connection pads <NUM> have a minute size, thousands of connection pads may be disposed in a line at predetermined intervals. Therefore, even when the plurality of test pads <NUM> are disposed as few as tens to as many as thousands, the plurality of test pads <NUM> may be entirely disposed on the thin film transistor substrate <NUM> without expanding the size of the manufactured thin film transistor substrate <NUM>.

That is, even when the dummy area DA including the area where the plurality of test pads <NUM> are disposed on the manufactured thin film transistor substrate <NUM> is removed, a portion removed on the manufactured thin film transistor substrate <NUM> may be minimized by minimizing the dummy area DA. Therefore, the thin film transistor substrate <NUM> may be easily tested through the plurality of test pads <NUM>, and the manufacturing cost may be reduced by minimizing the area occupied by the plurality of test pads <NUM>.

The connection wiring <NUM> electrically connects the connection pad <NUM> and the test pad <NUM> and may be formed in the thin film transistor layer <NUM>. The connection wiring <NUM> may be made of a material having low flexibility.

For example, the connection wiring <NUM> may be made of at least one of molybdenum (Mo), titanium (Ti) and TiMo. However, the connection wiring is not limited hereto. Therefore, even if the dummy area DA is removed along a first cutting line C-<NUM> and a second cutting line C-<NUM> included in the dummy area DA, by-products generated by the connection wiring <NUM> may be minimized.

Specifically, when the connection wiring <NUM> is made of an elastic material, many by-products may be generated along the first cutting line C-<NUM> and the second cutting line C-<NUM> in a cutting process. Therefore, in a subsequent process, an additional process of removing the generated by-products may be necessary.

Therefore, when the connection wiring <NUM> is made of an inelastic or rigid material, the process of removing the by-products may be minimized or omitted by minimizing the generation of the by-products in the cutting process, thereby reducing the manufacturing cost.

In addition, the connection wiring <NUM> may be formed in the form of one layer of the thin film transistor layer <NUM>.

Further, because the connection wiring <NUM> connects each of the plurality of test pads <NUM> and each of the plurality of connection pads <NUM>, the connection wiring <NUM> is configured in plural. For example, the number of connection wirings <NUM> may correspond to the number of the plurality of test pads <NUM> and the plurality of connection pads <NUM>.

Further, first and second insulating layers <NUM> and <NUM> may be disposed on upper and lower portions of the connection wiring <NUM>, respectively. For example, the first insulating layer <NUM> may be disposed on the upper portion of the connection wiring <NUM>, and the second insulating layer <NUM> may be disposed on the lower portion of the connection wiring <NUM>.

That is, the first insulating layer <NUM> and the second insulating layer <NUM> may be formed to surround the connection wiring <NUM>.

Therefore, when a current flows through the connection wiring <NUM>, the current is prevented from flowing into a space other than the connection wiring <NUM>, thereby improving stability of the electrical test of the thin film transistor substrate <NUM>.

The first insulating layer <NUM> and the second insulating layer <NUM> may be integrally formed with a layer formed around the thin film transistor <NUM>. That is, in the process of forming the thin film transistor layer <NUM> on the glass substrate <NUM>, the first insulating layer <NUM> and the second insulating layer <NUM> may be formed.

In addition, if necessary, polycrystalline silicon (p-Si) may be disposed below each of the first insulating layer <NUM> and the second insulating layer <NUM>.

Further, the first insulating layer <NUM> and the second insulating layer <NUM> may be in contact with each other at a position where the connection wiring <NUM> is not formed.

Further, the first insulating layer <NUM> and the second insulating layer <NUM> may be formed of an organic insulating layer or an inorganic insulating layer, and materials constituting each insulating layer may be different.

Between the glass substrate <NUM> and the second insulating layer <NUM>, a buffer layer <NUM> may be formed to alleviate strain caused by a difference in lattice constant and coefficient of thermal expansion between the glass substrate <NUM> and the thin film transistor layer <NUM>. The buffer layer <NUM> may be made of GaN, AlN, AlGaN, or SiNx, which are high heat resistance materials, to enable GaN layer deposition through a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process.

Further, the thin film transistor substrate <NUM> may include a plurality of electrode pads formed on each of the plurality of thin film transistors <NUM> and on which the plurality of LEDs <NUM> are disposed.

For example, the plurality of electrode pads may include a first electrode pad <NUM> and a second electrode pad <NUM> representing different electrodes.

Accordingly, as illustrated in <FIG>, a first electrode <NUM> of the LED <NUM> may be disposed on the first electrode pad <NUM>, and a second electrode <NUM> of the LED <NUM> may be disposed on the second electrode pad <NUM>.

Therefore, the electrical signal transmitted from the thin film transistor <NUM> may be transmitted to the LED <NUM> through the plurality of electrode pads <NUM> and <NUM>.

In addition, the plurality of thin film transistors <NUM> and the plurality of electrode pads <NUM> and <NUM> may be disposed in a matrix form on the glass substrate <NUM>. Therefore, the plurality of LEDs <NUM> mounted on the plurality of electrode pads <NUM> and <NUM> may also be disposed in the matrix form on the glass substrate <NUM>.

Next, a process of manufacturing the thin film transistor substrate <NUM> according to an embodiment will be described with reference to <FIG>.

<FIG> is a top view illustrating the thin film transistor substrate <NUM> according to an embodiment, <FIG> is a cross-sectional view taken along line A-A of <FIG>, <FIG> is a top view illustrating a dummy area DA that is removed from a structure of <FIG>, <FIG> is a cross-sectional view taken along line E-E of <FIG>, <FIG> is a cross-sectional view illustrating a chamfered structure of the structure shown in <FIG>, <FIG> is a top view illustrating a side wiring <NUM> formed in a structure of <FIG>, <FIG> is a cross-sectional view taken along line F-F of <FIG>, <FIG> is a block diagram illustrating the LED <NUM> and the driving driver <NUM>, <FIG> is a top view illustrating an arrangement of a plurality of manufactured display modules <NUM> and <NUM>, and <FIG> is a flowchart illustrating a manufacturing method of the thin film transistor substrate <NUM> according to an embodiment.

First, as illustrated in <FIG>, a plurality of test pads <NUM> may be formed along an edge of the glass substrate <NUM>. Specifically, a thin film transistor layer <NUM> may be formed on the glass substrate <NUM> (S1).

Here, the thin film transistor layer <NUM> may include a plurality of connection pads <NUM>, a plurality of test pads <NUM>, a connection wiring <NUM>, first and second inorganic insulating layers <NUM> and <NUM>, and a plurality of electrode pads <NUM> and <NUM>.

That is, in a process of forming the plurality of test pads <NUM>, the thin film transistor layer <NUM> may be formed through an iterative process of stacking and etching.

For example, in the operation of forming the plurality of test pads <NUM>, the connection wiring <NUM> that electrically connects each of the plurality of thin film transistors <NUM> and each of the plurality of test pads <NUM> disposed on the glass substrate <NUM> may be formed.

In addition, in the operation of forming the plurality of test pads <NUM>, the insulating layers <NUM> and <NUM> may be formed on upper and lower portions of the connection wiring <NUM>.

Next, as illustrated in <FIG>, a test needle N may be in contact with the plurality of test pads <NUM> to test whether the manufactured thin film transistor substrate <NUM> is properly operating (S2).

Specifically, each of the plurality of test pads <NUM> may be electrically connected to each of the plurality of connection pads <NUM> through the connection wiring <NUM>, and each of the plurality of connection pads <NUM> may be electrically connected to the plurality of thin film transistors <NUM> through electrical wiring formed in the thin film transistor layer <NUM>.

Accordingly, in a state in which the test needle N is in contact with the plurality of test pads <NUM>, the current allows to flow through the test needle N, thereby making possible to test whether the current may flow through the plurality of transistors <NUM>.

Here, the number of test needles N smaller than the number of test pads <NUM> may be disposed to determine whether the thin film transistor substrate <NUM> is operated by repeatedly contacting the plurality of test pads <NUM>, or the number of test needles N equal to or greater than the number of test pads <NUM> may be disposed to determine whether the thin film transistor substrate <NUM> is operating by simultaneously contacting the plurality of test pads <NUM>.

In addition, the test needle N is only an example, and various configurations that may be used to perform the electrical test, such as a test pad.

Therefore, before an additional process is performed on the manufactured thin film transistor substrate <NUM>, it is possible to check whether or not the thin film transistor substrate <NUM> is poorly manufactured.

Here, the additional process may mean various processes such as disposing the plurality of LEDs <NUM> on the thin film transistor substrate <NUM> or removing the dummy area DA of the thin film transistor substrate <NUM>.

Therefore, it is possible to determine whether the additional process needs to be performed, thereby improving the manufacturing efficiency of the thin film transistor substrate <NUM>.

In addition, the cross-sectional area of each of the plurality of test pads <NUM> may be greater than the size of the cross-sectional area of each of the plurality of connection pads <NUM>. Therefore, because the test needle N does not make contact with the plurality of connection pads <NUM> of fine size, but instead, makes contact with the plurality of test pads <NUM>, the test needle N may stably perform electrical tests on the plurality of test pads <NUM>.

Accordingly, in the test process, due to the large cross-sectional area of the plurality of test pads <NUM>, the probability that the test needle N may be in contact with the plurality of test pads <NUM> may increase, and the test may be stably performed. In other words, test efficiency and stability of the manufactured thin film transistor substrate <NUM> may be improved.

Further, in the test process, even if the plurality of test pads <NUM> are damaged, the plurality of test pads <NUM> may be removed and replaced, and thus the plurality of damaged test pads <NUM> may not affect the operation of the display module <NUM> (shown in <FIG>) in a state in which the plurality of LEDs <NUM> are disposed.

Next, after the test of the manufactured thin film transistor substrate <NUM> is finished, a predetermined dummy area DA of the glass substrate <NUM> in which the plurality of test pads <NUM> are disposed may be removed (S3).

Here, the operation of removing the dummy area DA may mean not only removing the glass substrate <NUM>, but also removing a portion of the thin film transistor layer <NUM> formed on the glass substrate <NUM>. For example, in the operation of removing the dummy area DA, the glass substrate <NUM>, the insulating layers <NUM>, <NUM>, and the connection wiring <NUM> may be simultaneously removed.

The dummy area DA may be an area including the plurality of connection pads <NUM> on the manufactured thin film transistor substrate <NUM>. Specifically, the dummy area DA may include an edge area of the thin film transistor substrate <NUM>.

For example, the dummy area DA may include one vertical side surface <NUM>-<NUM> and one horizontal side surface <NUM>-<NUM> of the glass substrate <NUM>.

In addition, the dummy area DA may include a first cutting line C-<NUM> and a second cutting line C-<NUM> between the plurality of connection pads <NUM> and the plurality of test pads <NUM> of the glass substrate <NUM>. Specifically, the first cutting line C-<NUM> may be disposed between the first connection pads <NUM>-<NUM> disposed in one column and the plurality of test pads <NUM>, and the second cutting line C-<NUM> may be disposed between the second connection pads <NUM>-<NUM> disposed in one row and the plurality of test pads <NUM>.

Here, the first cutting line C-<NUM> and the second cutting line C-<NUM> may be perpendicular to each other. However, the intersection of the first cutting line C-<NUM> and the second cutting line C-<NUM> are not limited hereto.

Further, in the operation of removing the dummy area DA, the glass substrate <NUM> may be removed such that the plurality of connection pads <NUM> electrically connected to the plurality of thin film transistors <NUM> and disposed on one surface of the glass substrate <NUM> are positioned at edges of the etched glass substrate <NUM>.

That is, as illustrated in <FIG>, after the dummy area DA is removed, the glass substrate <NUM> and the thin film transistor substrate <NUM> may have a first cutting surface <NUM>-1a in a vertical direction and a second cutting surface <NUM>-2a in a horizontal direction adjacent to the first cutting surface <NUM>-1a.

For example, the first cutting surface <NUM>-1a may be parallel to the first connection pads <NUM>-<NUM> disposed in a column, and the second cutting surface <NUM>-2a may be parallel to the second connection pads <NUM>-<NUM> disposed in a row.

Further, in the operation of removing the dummy area DA, the glass substrate <NUM> may be removed through a laser emitted from a laser cutter. However, the means for removing the glass substrate <NUM> is not limited to the laser, and the glass substrate <NUM> may also be removed by various mechanical apparatuses such as a grinder.

In addition, as illustrated in <FIG> and <FIG>, after the etching is performed along the first cutting line C-<NUM> and the second cutting line C-<NUM>, the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM> may be polished along a polishing line D.

Accordingly, after the cutting process, by-products generated in the glass substrate <NUM> and the thin film transistor layer <NUM> may be removed by polishing the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM>.

In addition, a side wiring <NUM> formed on the first and second cutting surfaces <NUM>-1a and <NUM>-2a may be stably formed without being lifted or disconnected by smoothing the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM>. Accordingly, when the manufactured display modules <NUM> and <NUM> operate, electrical signals transmitted from the driving driver <NUM> disposed at the rear surface of the display modules <NUM> and <NUM> may be stably transmitted to the plurality of LEDs <NUM> through the side wiring <NUM>.

In addition, as illustrated in <FIG>, after the cutting process is performed along the first and second cutting lines C-<NUM> and C-<NUM>, corners of the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM> may be chamfered.

That is, one surface of at least one of the thin film transistor layer <NUM> and the glass substrate <NUM> may be chamfered to form a chamfered surface CF. Specifically, the chamfered surfaces CF may be formed on the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM>.

Accordingly, the shortest distance of the side wiring <NUM> connecting the plurality of connection pads <NUM> disposed on one surface of the glass substrate <NUM> and a plurality of driving pads <NUM> disposed on the other surface of the glass substrate <NUM> may be reduced, thereby reducing loss in current and signal. In addition, it is possible to structurally prevent the side wiring <NUM> from being disconnected by sharp corners of the first and second cutting surfaces <NUM>-1a and <NUM>-2a.

Further, the plurality of LEDs <NUM> are disposed on the plurality of electrode pads <NUM> and <NUM> formed on the plurality of thin film transistors <NUM>.

However, the operation of disposing the plurality of LEDs <NUM> may be performed after the operation of testing the manufactured thin film transistor substrate <NUM>.

Here, the LED <NUM> may be made of an inorganic light emitting material having a size of about <NUM> or less in width, length, and height, and may be a micro LED that is disposed on the thin film transistor substrate <NUM> and emits light by itself.

Referring to <FIG> and <FIG>, the LED <NUM> may be configured by a single pixel <NUM>', and one pixel may include a red LED <NUM> emitting red light, a green LED <NUM> emitting green light, and a blue LED <NUM> emitting blue light, which are sub-pixels, and a pixel driving circuit <NUM> for driving the plurality of sub-pixels.

That is, one pixel <NUM>' may include the red LED <NUM> emitting red light, the green LED <NUM> emitting green light, the blue LED <NUM> emitting blue light, and the pixel driving circuit <NUM> for driving the plurality sub-pixels.

The sub-pixels <NUM>, <NUM>, and <NUM> may be arranged in a matrix form or sequentially arranged in one pixel <NUM>'. However, the form of the arrangement of the sub-pixels <NUM>, <NUM>, and <NUM> is only an example, and the sub-pixels <NUM>, <NUM>, and <NUM> may be disposed in various forms within each single pixel <NUM>'.

The LED <NUM> may have fast response speed, low power consumption, and high luminance, and thus has been in the spotlight as a light emitting device of next generation display. Specifically, the LED <NUM> may have a higher efficiency of converting electricity into photons than those of conventional LCDs.

In other words, the LED <NUM> has a higher "brightness per watt" compared to conventional LCD displays. As a result, the LED <NUM> may emit the same brightness with about half of the energy required for the conventional LCDs.

Furthermore, the LED <NUM> may implement high resolution, excellent color, contrast, and brightness, thereby accurately expressing a wide range of colors, and implementing a clear screen even in bright sunlight. In addition, because the LED <NUM> generates less heat, a long service life is ensured without deformation.

In addition, the LED <NUM> may be a flip chip.

Next, as illustrated in <FIG>, a plurality of driving pads <NUM> and a plurality of link pads <NUM> connected to the plurality of driving pads <NUM> may be formed on the other surface 50b of the etched glass substrate <NUM>.

The plurality of driving pads <NUM> may be disposed at positions facing the positions where the plurality of connection pads <NUM> are formed.

Further, the plurality of link pads <NUM> may be disposed to be adjacent to the plurality of driving pads <NUM>, and may be electrically connected to the driving driver <NUM>.

After the plurality of driving pads <NUM> and the plurality of link pads <NUM> are formed, a side wiring <NUM> may be formed along the first and second cutting surfaces <NUM>-1a and <NUM>-2a of the glass substrate <NUM> to connect the plurality of connection pads <NUM> disposed on one surface 50a of the glass substrate <NUM> and the plurality of driving pads <NUM> disposed on the other surface 50b of the glass substrate <NUM>.

Accordingly, the manufactured thin film transistor substrate <NUM> may operate as the first display module <NUM> capable of implementing one display screen after undergoing various processes.

Specifically, signal information of the display screen may be generated from the driving driver <NUM> disposed on the other surface 50b of the first display module <NUM>, and the signal information may be transmitted to the LED <NUM> through the link pads <NUM>, the driving pads <NUM>, the side wiring <NUM>, the connection pads <NUM>, and the thin film transistor <NUM> which are connected to the driving driver <NUM>.

Accordingly, the LED <NUM> receiving the signal information of the display screen being operated, the first display module <NUM> may implement the display screen.

Further, as illustrated in <FIG>, the second display module <NUM> having the same manufacturing structure as the first display module <NUM> may be disposed in parallel to the first display module <NUM> to implement one display screen.

That is, the plurality of display modules <NUM> and <NUM> may be arranged in accordance with the size of the display to be implemented by each of the display modules <NUM> and <NUM> manufactured in a module form to form one display screen.

For example, when the first and second display modules <NUM> and <NUM> are disposed in parallel to each other in the horizontal direction, the display screen may be implemented to have a longer length in the horizontal direction than that in the vertical direction.

Alternatively, when the first and second display modules <NUM> and <NUM> are disposed in parallel to each other in the vertical direction, the display screen may be implemented to have a longer length in the vertical direction than that in the horizontal direction.

Therefore, the display screens of various sizes and shapes may be implemented according to the number and shape of the plurality of arranged display modules.

Hereinafter, a structure of the connection wiring <NUM> according to an embodiment will be described with reference to <FIG>.

<FIG> is a top view illustrating the connection wiring <NUM> according to an embodiment not forming part of the present invention.

As illustrated in <FIG>, the connection wiring <NUM> may electrically connect one test pad <NUM> and one connection pad <NUM>. In this case, the connection wire <NUM> may be formed to have a predetermined length with respect to the test pad <NUM> and the connection pad <NUM>.

Hereinafter, a structure of a connection wiring <NUM>' according to a modified example will be described with reference to <FIG>.

<FIG> is a top view illustrating the connection wiring <NUM>' according to the claimed invention.

As illustrated in <FIG>, each of the connection wirings <NUM>' includes a plurality of sub-connection wirings <NUM>'-<NUM> and <NUM>'-<NUM> spaced apart from each other by a predetermined interval.

The plurality of sub-connection wirings <NUM>'-<NUM> and <NUM>'-<NUM> are disposed to have a separation space S disposed between the sub-connection wiring <NUM>'-<NUM> and <NUM>'-<NUM>, and the number of the plurality of sub-connection wirings may vary.

Accordingly, because the plurality of sub-connection wirings <NUM>'-<NUM> and <NUM>'-<NUM> are disposed to have the separation space S spaced apart from each other, by-products generated in the connection wrings <NUM>' may be reduced according to the separation space S when cutting is performed between the connection pad <NUM> and the test pad <NUM>.

Therefore, when the connection wiring <NUM>' is made of an inelastic or sturdy material, the process of removing the by-products may be minimized or omitted by minimizing the generation of the by-products in the cutting process, thereby reducing the manufacturing cost.

Further, by preventing the inclusion of the by-products in the side wiring <NUM> when the side wiring <NUM> is connected to the connection pad <NUM>, it is possible to implement stable signal transmission in the display modules <NUM> and <NUM>.

Hereinafter, a structure of a connection wiring <NUM>" according to another embodiment will be described with reference to <FIG>.

<FIG> is a top view illustrating a connection wiring <NUM>" according to another embodiment.

As illustrated in <FIG>, each of the connection wirings <NUM>" includes a plurality of sub-connection wirings <NUM>"-<NUM> and <NUM>"-<NUM> spaced apart from each other by a predetermined interval, and connection portions <NUM>"-<NUM> formed to be adjacent to each of the plurality of connection pads <NUM> and each of the plurality of test pads <NUM>.

Specifically, the connection portions <NUM>"-<NUM> may be formed at one end and the other end of the plurality of sub-connection wirings <NUM>"-<NUM> and <NUM>"-<NUM>, respectively, and may increase a cross-sectional area of the connection wiring <NUM>".

By adjusting resistance based on the cross-sectional area of the connection wiring <NUM>", a current value between the connection pad <NUM> and the test pad <NUM> may be adjusted, and by-products generated in the connection wring <NUM>" may be reduced according to the separation space S when cutting is performed between the connection pad <NUM> and the test pad <NUM>.

<FIG> is a cross-sectional view illustrating a thin film transistor substrate according to another embodiment and <FIG> is a plan view illustrating a second area A2 and a dummy area DA illustrated in <FIG>.

Referring to <FIG> and <FIG>, a thin film transistor substrate 1a according to another embodiment may have a dummy area DA in which a plurality of test pads are disposed similarly to the thin film transistor substrate <NUM> described above. In this case, the dummy area DA may be removed when the test of the thin film transistor substrate 1a is completed.

The thin film transistor substrate 1a according to another embodiment may have substantially the same structure as the structure of the thin film transistor substrate <NUM> described above, but may be different in some configurations.

Hereinafter, a structure of the thin film transistor substrate 1a according to another embodiment will be described.

The thin film transistor substrate 1a according to another embodiment may include a glass substrate <NUM>, a thin film transistor layer <NUM> formed in a first area A1 of the glass substrate <NUM>, a plurality of connection pads <NUM> disposed in a second area A2 of the glass substrate <NUM>, and a plurality of test pads <NUM> disposed in a dummy area DA of the glass substrate <NUM>.

A buffer layer <NUM> that is in contact with a bottom surface of the thin film transistor layer <NUM> may be disposed on an upper surface of the glass substrate <NUM>. The buffer layer <NUM> may alleviate strain caused by a difference in lattice constant and coefficient of thermal expansion between the glass substrate <NUM> and the thin film transistor layer <NUM>.

The dummy area DA of the glass substrate <NUM> may be defined as an area to be removed during a cutting process in a process of manufacturing a display module 10a (as shown in <FIG>) as the outermost portion of the glass substrate <NUM>. In this case, the dummy area DA may be an area including at least one of four sides when the glass substrate <NUM> has a quadrangular shape. The dummy area DA and the second area A2 may also be divided with a cutting line C as a boundary.

The first area A1 of the glass substrate <NUM> may be defined as an area occupied by the thin film transistor layer <NUM>, and the second area A2 may be defined as an edge area of the glass substrate <NUM> in a state in which the dummy area DA is removed by the cutting process. That is, the second area A2 may correspond to the outermost portion of the glass substrate <NUM> when the dummy area DA is removed.

The thin film transistor layer <NUM> may include gate wirings 251a and 251b, data wirings 253a, 253b, 255a, and 255b, Vdd power wirings 211a and 211b connected to some 253a and 255b of the data wirings, Vss power wirings <NUM> and <NUM>, and pixel electrodes 215a and 215b.

In this case, a plurality of thin film transistor layers <NUM> may include a gate insulating layer <NUM> and first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> sequentially stacked upward from an upper surface of the buffer layer <NUM>. The first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM> and <NUM> may be made of an inorganic or organic insulating material. For example, the first, third and fifth insulating layers <NUM>, <NUM>, and <NUM> may be made of an inorganic insulating material, and the second and fourth insulating layers <NUM> and <NUM> may be made of an organic insulating material.

The first, second, fourth, and fifth insulating layers <NUM>, <NUM>, <NUM>, and <NUM> may be formed up to the dummy area DA. In particular, a connection wiring <NUM> that electrically connects the plurality of connection pads <NUM> and the plurality of test pads <NUM> may be disposed between the fourth and fifth insulating layers <NUM> and <NUM> in the first area A1. Accordingly, upper and lower portions of the connection wiring <NUM> may be covered with the fourth and fifth insulating layers <NUM> and <NUM>.

The plurality of connection pads <NUM> disposed in the second area A2 of the glass substrate <NUM> and the plurality of test pads <NUM> disposed in the dummy area DA are electrically connected to each other through the connection wiring <NUM>. The connection wiring <NUM> may be a wiring extending from the Vss power wiring <NUM>.

Referring to <FIG>, the connection wiring <NUM> may be formed to be disposed across the second area A2 and the dummy area DA. Accordingly, when the cutting is performed along the cutting line C, a portion 242a of the connection wiring <NUM> may be exposed on a cutting surface of the thin film transistor substrate 1a in a state in which the dummy area DA is removed.

The connection wiring <NUM> may include a first connection part <NUM> to which the connection pad <NUM> is electrically connected to the upper surface thereof, a second connection part <NUM> to which the test pad <NUM> is electrically connected to the upper surface thereof, and a bridge part <NUM> connecting the first and second connection parts <NUM> and <NUM> to each other. A portion 242a of the bridge part <NUM> may be disposed in the second area A2 and the remaining portion 242b may be positioned in the dummy area DA.

In this case, a width of the bridge part <NUM> may be thinner than the width of the first and second connection parts <NUM> and <NUM>. However, the width of the bridge part <NUM> is not limited thereto and may be formed to be the same as that of the first and second connection parts <NUM> and <NUM>.

In addition, the thin film transistor layer <NUM> may be formed by a low temperature poly silicon (LTPS) TFT process or an oxide TFT process, and according to each process, at least some of the gate wirings 251a and 251b, the data wirings 253a, 253b, 255a and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings <NUM> and <NUM>, and the connection wiring <NUM> may be made of a low resistance metal material.

For example, in the case of the thin film transistor layer <NUM> formed by the LTPS TFT process, the gate wirings 251a and 251b may be made of molybdenum (Mo) having high heat resistance, and the data wirings 253a, 253b, 255a, and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings <NUM> and <NUM>, and the connection wiring <NUM> may be made of aluminum (Al), which is the low resistance metal material.

In addition, in the case of the thin film transistor layer <NUM> formed by the oxide TFT process, the gate wirings 251a and 251b, the data wirings 253a, 253b, 255a and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings <NUM> and <NUM> and the connection wiring <NUM> are all made of aluminum (Al) or copper (Cu), which are the low resistance metal materials.

In a case in which the connection wiring <NUM> is formed of the low resistance metal material, a minimum resistance requirement value may be adjusted at the time of an electrical test of the thin film transistor substrate 1a. Therefore, by adjusting a value of a test current flowing in the thin film transistor substrate 1a through the connection wiring <NUM>, it is possible to prevent a high current flowing in the thin film transistor substrate 1a and damaging the components inside the thin film transistor substrate 1a.

The thin film transistor substrate 1a may include a plurality of driving pads <NUM> on the other surface of the glass substrate <NUM> and a plurality of link pads <NUM> electrically connected to the respective driving pads through a wiring <NUM>. In this case, the wiring <NUM> may be covered by the insulating layer <NUM>.

The plurality of driving pads <NUM>, the plurality of link pads <NUM>, the wiring <NUM>, and the insulating layer <NUM> may be formed together when the thin film transistor layer <NUM> is formed, may be subsequently formed after forming the thin film transistor layer <NUM>, or may be formed after removing the dummy area DA.

Hereinafter, a process of manufacturing a display module 10a using the thin film transistor substrate 1a according to another embodiment will be described sequentially with reference to <FIG> and <FIG>. Because the process of manufacturing the display module 10a is the same as the process of manufacturing the display module <NUM> described above, it will be described schematically.

<FIG> is a flowchart illustrating a process of manufacturing a display module using a thin film transistor substrate according to another embodiment and <FIG> is a cross-sectional view illustrating a display module according to another embodiment.

First, the thin film transistor substrate 1a having the plurality of test pads <NUM> disposed in the dummy area DA may be prepared (S11).

Next, an electrical test of the thin film transistor substrate 1a may be performed (S12). In this case, the electrical test may be performed by contacting the test needle N (as shown in <FIG>) to the plurality of test pads <NUM>. By adjusting a value of a test current flowing in the thin film transistor substrate 1a through the connection wiring <NUM>, which is a low resistance wiring, during such an electrical test, it is possible to prevent a high current flowing in the thin film transistor substrate 1a and damaging the components inside the thin film transistor substrate 1a.

When the electrical test of the thin film transistor substrate 1a is completed, the plurality of test pads <NUM> are no longer needed, and the dummy area DA is thus removed from the thin film transistor substrate 1a along the cutting line C (S13).

Next, a process of polishing the cutting surface of the thin film transistor substrate 1a may be performed (S14). By-products generated in the glass substrate <NUM> and the thin film transistor layer <NUM> may be removed through the polishing process.

When the polishing process is completed, corners of the cutting surface of the thin film transistor substrate 1a (in this case, the cutting surface forms a flat surface by the polishing process) are chamfered (S15). If the corner portions of the cutting surface of the thin film transistor substrate 1a are removed through the chamfering process, chamfered surfaces CF1 and CF2 may be formed as illustrated in <FIG>.

The chamfered surfaces CF1 and CF2 of the thin film transistor substrate 1a may prevent the side wiring <NUM> formed on the cutting surface of the thin film transistor substrate 1a from being disconnected by the sharp-edged corners in advance.

If the chamfering process is completed, a plurality of side wirings <NUM> may be formed to electrically connect the plurality of connection pads <NUM> disposed on one surface of the glass substrate <NUM> and the plurality of driving pads <NUM> disposed on the other surface of the glass substrate <NUM> (S16).

Both end portions <NUM> and <NUM> of each side wiring <NUM> may be formed to cover at least a portion of the connection pad <NUM> and the driving pad <NUM>, respectively, and a central portion <NUM> thereof may be formed to cover the chamfered surfaces CF1 and CF2 and the cutting surface of the glass substrate <NUM>.

Next, the LED may be transferred or inserted so that the LED is electrically connected to the plurality of pixel electrodes 215a and 215b provided in the thin film transistor layer <NUM> (S17). In this case, the LED transfer may be performed through any one of a laser transfer method, a stamp transfer method, a roller transfer method, and an electrostatic transfer method.

<FIG> is a cross-sectional view illustrating a thin film transistor substrate according to still another embodiment, <FIG> is a plan view illustrating a second area A2 and a dummy area DA illustrated in <FIG>, and <FIG> is a cross-sectional view illustrating a display module according to a still another embodiment.

A thin film transistor substrate 1b according to still another embodiment may have substantially the same structure as the structure of the thin film transistor substrate 1a described above, but may differ in that the connection pad and the test pad are integrally formed. Hereinafter, the thin film transistor substrate 1b according to still another embodiment will be described, but a configuration different from that of the thin film transistor substrate 1a will be more specifically described.

Referring to <FIG> and <FIG>, an integrated pad <NUM> may be formed by integrally forming the connection pad <NUM> and the test pad <NUM> described above, and may have the same function of the connection pad <NUM> and the function of the test pad <NUM> described above.

The integrated pad <NUM> may include a connection pad part <NUM> electrically connected to a first connection part <NUM> of a connection wiring <NUM>, a test pad part <NUM> electrically connected to a second connection part <NUM> of the connection wiring <NUM>, and a link part <NUM> electrically connected along a bridge part <NUM> of the connection wiring <NUM>.

A portion 422a of the link part <NUM> may correspond to a portion 442a of the bridge part <NUM>, and the remaining portion 422b of the link part <NUM> may be disposed at a position corresponding to the remaining portion 442b of the bridge part <NUM>.

Accordingly, when the dummy area DA is removed along the cutting line C, the portion 422a of the link part of the integrated pad <NUM> and the portion 442a of the bridge part <NUM> of the connection wiring <NUM> may be exposed at the cutting surface of the glass substrate <NUM>.

Referring to <FIG>, the thin film transistor substrate 10b in the state in which the dummy area DA is removed may have the portion 422a of the link part of the integrated pad disposed up to the chamfered surface CF1. Accordingly, one end portion <NUM> of a side wiring <NUM> may be formed to cover only the portion 422a of the link part of the integrated pad.

However, one end portion <NUM> of a side wiring <NUM> is not limited thereto and may also be formed to cover the portion 422a of the link part of the integrated pad and the connection pad part <NUM>.

In addition, the other end portion <NUM> of the side wiring <NUM> may be formed to cover at least a portion of the driving pad <NUM>, and a central portion <NUM> thereof may be formed to cover the respective chamfered surfaces CF1 and CF2 and the cutting surface of the glass substrate <NUM>.

Although various embodiments have been individually described hereinabove, the respective embodiments are not necessarily implemented individually, but may also be implemented so that configurations and operations thereof are combined with those of one or more other embodiments.

Although the embodiments of the disclosure have been illustrated and described hereinabove, the disclosure is not limited to the specific embodiments described above, but may be variously modified by those skilled in the art to which the disclosure pertains without departing from the scope of the invention as defined by the claims. Such modifications should not be individually understood from the scope of the invention as defined by the claims.

Claim 1:
A display module comprising:
a glass substrate (<NUM>);
a thin film transistor layer (<NUM>) disposed on a first area of the glass substrate (<NUM>);
a plurality of connection pads (<NUM>) disposed in a second area of the glass substrate (<NUM>) extending from the first area of the glass substrate (<NUM>) and electrically connected to the thin film transistor layer (<NUM>);
a plurality of test pads (<NUM>) disposed in a third area of the glass substrate (<NUM>) extending from the second area of the glass substrate (<NUM>) and electrically connected to the plurality of connection pads (<NUM>), respectively;
a plurality of connection wirings (<NUM>) electrically connecting the plurality of connection pads (<NUM>) and the plurality of test pads (<NUM>); and
a plurality of light emitting diodes (<NUM>) on the thin film transistor layer (<NUM>), wherein a thin film transistor (<NUM>) on the thin film transistor layer (<NUM>) is electrically connected to at least one light emitting diode of the plurality of light emitting diodes (<NUM>),
characterized in that each of the connection wirings of the plurality of connection wirings connects one test pad and one connection pad and comprises a plurality of sub-connection wirings (<NUM>'-<NUM>, <NUM>'-<NUM>) spaced apart from each other at a predetermined interval.