Patent Description:
It may be desirable to use a computational storage device (e.g., a solid state drive (SSD) with an embedded processor or Field Programmable Gate Array (FPGA)), for various data processing tasks, as such a storage device may help provide efficient and cost-effective data processing solutions. For example, a computational storage device may provide a platform for performing at least a portion of the data processing functions that may otherwise be performed by a host CPU processor, within the storage device itself.

Thus, it is desirable to have a system and method for quickly determining whether one or more components of a computational storage device are verified components.

<CIT> discloses: Methods and systems for dynamic spectrum access (DSA) in a wireless network are provided. A DSA-enabled device may sense spectrum use in a region and, based on the detected spectrum use, select one or more communication channels for use. The devices also may detect one or more other DSA-enabled devices with which they can form DSA networks. A DSA network may monitor spectrum use by cooperative and non-cooperative devices, to dynamically select one or more channels to use for communication while avoiding or reducing interference with other devices.

<CIT> discloses: An information processing apparatus includes a communication apparatus and a different communication apparatus connected to the communication apparatus via a plurality of transmission paths. The communication apparatus includes a transmitting unit and a control unit. In response to designation of a transmission path targeted for diagnosis, selected amongst the transmission paths while the communication apparatus is in a state capable of data communication with the different communication apparatus using the transmission paths, the transmitting unit transmits a test signal to the targeted transmission path while the state capable of data communication with the different communication apparatus is maintained using remaining transmission paths of the transmission paths other than the targeted transmission path. The control unit diagnoses the presence or absence of an abnormality sign in the targeted transmission path based on the result of detecting the test signal in the targeted transmission path and outputs the diagnostic result.

<CIT> discloses techniques for improving the tamper-resistibility of hardware. The tamper-resistant hardware may be advantageously used in a transaction system that provides the off-line transaction protocol. Amongst these techniques for improving the tamper-resistibility are trusted bootstrapping by means of secure software entity modules, a use of hardware providing a Physical Unclonable Function, and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware.

Embodiments of the present disclosure are directed to a storage device configured for hardware verification. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first verification logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion, wherein the criterion is detecting start of a reset period when a device is inserted into a slot of a computer system without stopping or shutting down the system. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second verification logic, where the second verification logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second verification logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.

According to one embodiment, the first hardware component includes at least one of a field gate programmable array (FPGA) or an application-specific integrated circuit, and the second hardware component includes non-volatile memory.

According to one embodiment, the expected signal is associated with an identifier stored in memory of the second hardware component.

According to one embodiment, the connector is a connector supporting a peripheral component interconnect express (PCIe) protocol.

According to one embodiment, the first signal is provided over a preset pin of the connector.

According to one embodiment, the result comprises an indication of a match of the received first signal with the expected signal, and the action comprises enabling an acceleration feature of the storage device.

According to one embodiment, the result comprises an indication of a mismatch of the received first signal with the expected signal, and the action comprises disabling an acceleration feature of the storage device.

According to one embodiment, the result comprises an indication of a mismatch of the received first signal with the expected signal, and the action comprises displaying a notification on a display device.

According to one embodiment, the second hardware component is coupled to a host via a second connector.

Embodiments of the present disclosure are also directed to a method for hardware verification by a storage device. The method comprises detecting, via a first verification logic in a first hardware component, a criterion; generating, via a connector in the first hardware component, a first signal in response to detecting the criterion, wherein the criterion is detecting start of a reset period when a device is inserted into a slot of a computer system without stopping or shutting down the system; monitoring and receiving, by a second verification logic in a second hardware component, the first signal, the second hardware component being coupled to the first hardware component via the connector; and comparing, by the second verification logic, in response to receiving the first signal, the received first signal to an expected signal, and generating a result, wherein the storage device is configured to take an action in response to the result.

As a person of skill in the art should recognize, embodiments of the present disclosure provide a mechanism for quickly determining whether one or more components of a computational storage device are verified components. This may help avoid, for example, unpredictable behavior or failure of the device due to use of an unverified component.

Non-limiting and non-exhaustive embodiments of the present embodiments are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numbers refer to like elements throughout. The present invention, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present disclosure may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof may not be repeated. Further, in the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity.

A computational storage device may at times be modular in design or construction. In such a case, the computational storage device may be constructed from different removable components including, for example, a storage component (e.g. solid state memory) and a processing component (e.g. a field programmable gate array (FPGA). The modular components of the computational storage device may be obtained from different vendors. As such, there is a likelihood that one may attempt to construct the computational storage device from unauthorized/unqualified vendors which may compromise the quality of the constructed computational storage device.

In general terms, embodiments of the present disclosure are directed to a system and method for detecting, via hardware, whether a storage device (e.g., an SSD) or a processor device (e.g., an FPGA) forming part of a computational storage device, is an authorized component. The verification process may be performed, for example, during a reset of all or a portion of the computational storage device. The verification process may be performed, for example, to verify that the device has authorized components before the FPGA has down loaded an image and/or bit-file that configures the FPGA to operate in a predetermined manner.

In one embodiment, the verification can be conducted via a hardware verification logic included in the processor device and in the storage device. The hardware verification logic may be configured to utilize a reserved pin of a connector (e.g., a U. <NUM> connector, or the like) that connects the storage device to the processor device. In one embodiment, the reserved pin can include pin E6 pin of the U. <NUM> connector.

According to one embodiment, hardware verification by an initiator of a target occurs during a reset period. The initiator may be an initiator as described by the NVMe standard, although embodiments of the disclosure are not limited thereto. The initiator may be the processor device, with the target being the storage device, or vice versa. The reset period may occur, for example, when a device is inserted into a slot of a computer system without stopping or shutting down the system, or when the entire computer system is rebooted. During the reset period, the initiator may be configured to monitor the reserved pin for determining whether traffic is detected through the pin. In one embodiment, an authorized target drives the reserved pin with a verification ID (also referred to as a verification signal) that notifies the initiator that the target is an authorized device. The verification ID may include, for example, a predefined waveform pattern/signal. In response to verifying that the target is an authorized device, the initiator may enable certain functionalities of the device that would not be enabled without such verification. The functionalities may include, for example, downloading proprietary bit files and/or enabling certain acceleration features.

<FIG> are block diagrams of exemplary computational storage devices 100a-100c (collectively referenced as <NUM>) with modular hardware components according to one exemplary embodiment. The various modular components described herein may also be referred to as hardware components.

The computation storage device 100a of <FIG> includes a modular storage component <NUM> that may be removably coupled to one or more processor components 104a, 104b. The modular storage component <NUM> may be, for example, an SSD including a storage controller <NUM> and various flash drives <NUM>. The SDD may be, for example, a Non-Volatile Memory express (NVMe) SSD, an NVMe over Fabrics (NVMe-oF)-compatible Ethernet SSD (eSSD), or any other suitable persistent (non-volatile) memory device.

The one or more processor components 104a, 104b may include, for example, one or more FPGAs 110a, 110b. In some embodiments, a GPU (graphics processing unit), TPU (tensor processing unit), and/or another ASIC (application-specific integrated circuit) conventional in the art may be used in addition or in lieu of the FPGA.

In the example of <FIG>, the modular storage component <NUM> connects to a host device over a connector 111a, which may be, for example, a small-form-factor-technology-affiliate-100x (SFF-TA-100X) connector (where X is an integer value equal to <NUM>, <NUM>, <NUM>, <NUM>, etc.). A user may create a computational storage device of choice by adding the one or more processor components 104a, 104b to the storage component <NUM> as desired.

In one embodiment, the modular storage component <NUM> connects to the one or more processor components 104a, 104b, over connectors 112a, 112b. The connectors 112a, 112b may be standard connectors such as, for example, U. <NUM>, Next Generation Small Form Factor (NF1), or Enterprise & Data Center SSD Form Factor (EDSFF) connectors. Communication between the storage component <NUM> and the one or more processor components 104a, 104b may occur, for example, via the connectors 112a, 112b, over PCIe links 114a, 114b.

The computational storage device 100b in the example of <FIG> includes a modular processor component <NUM> that may be removably coupled to one or more modular storage components 122a-122d (collectively referenced as <NUM>), over a connector 124a-124d. The processor device in the modular processor component <NUM> may be, for example, an FPGA, and the one or more modular storage components <NUM> may be, for example, an SSD. In the example of <FIG>, the processor component <NUM> connects to the host device over a connector 111b. A user may create a computational storage device of choice by adding the one or more modular storage components <NUM> to the processor component <NUM> as desired.

The computational storage device 100c of <FIG> can be similar (but not necessarily identical) to the computational storage device 100a of <FIG>, except that dual processor components 130a, 130b are coupled to a storage component <NUM> over a connector <NUM> having a dual port configuration. The connector may be, for example, a U. <NUM> connector or a PCIe interface. In the example of <FIG>, the processor components 130a, 130b connect to the host device over a connector 111c. A user may design a computational storage device of choice by adding the modular storage component <NUM> of choice to the processor components 130a, 130b as desired.

In the modular configuration of the computational storage device <NUM> in the examples of <FIG>, it is possible that a particular modular component may be obtained from an unauthorized/unqualified vendor that may, for example, compromise the quality (e.g., performance) of the computational storage device. It may be desirable, therefore, to have a system and method for determining whether one or more components of the computational storage device are verified components. Once an added modular component is verified to be an authorized component, certain acceleration features may be enabled, such as, for example, compression and/or encryption functionalities by the computational storage device.

In one embodiment, in the event that the added modular component cannot be verified, the computational storage device may be configured to download or otherwise receive, for example, standard FPGA bit files without downloading proprietary FPGA bit files. This may allow, for example, the computational storage device to function as it normally would, but without the acceleration capabilities. The device can additionally transmit a message to inform a user or application that the added device is unauthorized.

<FIG> is a block diagram of verification modules 200a, 200b (collectively referenced as <NUM>) for performing hardware verification of a modular component of a computational storage device according to one exemplary embodiment. In one embodiment, the verification modules <NUM> are installed in an initiator component and in a target component. The verification modules may respectively include hardware verification logics 202a, 202b (collectively referenced as <NUM>) that may be described, for example, as state machines.

In one embodiment, the verification modules <NUM> further include multiplexors 204a, 204b (collectively referenced as <NUM>). Input to a particular one of the multiplexors <NUM> may be provided by the corresponding hardware verification logic <NUM> and by a reserved pin <NUM>. In one embodiment, the reserved pin <NUM> is a reserved pin of a connector <NUM> (similar to connector <NUM>, <NUM>, <NUM>). When the connector is implemented as a U. <NUM> connector, the pin <NUM> may be pin "E6" that is defined as a reserved (RSVD) pin (or any other suitable pin). Although the U. <NUM> connector is used as an example of a connector for connecting the processor module to the storage module, a person of skill in the art should recognize that the connector may also be an M. <NUM> or NF1 connector having one or more reserved pins.

Outputs of the multiplexors 204a, 204b are coupled to the reserved pin <NUM> of the connector <NUM>. A reset pin <NUM> may control the multiplexors 204a, 204b so outputs of the hardware verification logic <NUM> are selected during a reset period when the reset pin <NUM> is asserted (e.g. asserted low). When the reset pin <NUM> is de-asserted, the multiplexors transmit a chassis type through the reserved pin <NUM>.

In one embodiment, the hardware verification logic <NUM> in the initiator and target devices initiate a verification cycle in response to a reset by a host processor. In one embodiment, the reset drives the reset pin <NUM> to be asserted low, causing the multiplexor <NUM> to select the hardware verification logic <NUM> to communicate via the reserved pin <NUM> of the connector <NUM> during the reset.

In one embodiment, the initiator is a device that is installed first on the host computer that seeks verification of the target, which may be a later-added modular component. Either the processor component or the storage component may be the initiator or the target. In one example, the initiator is the processor component <NUM>, <NUM> of <FIG>, <FIG>, and the target is the storage component <NUM>, <NUM> of <FIG>, <FIG>. In another example, the initiator is the storage component <NUM> of <FIG> and the target is the processor component <NUM> of <FIG>.

Assuming, for illustration purposes, that the initiator is an FPGA and the target is an SSD, the initiator may execute the hardware verification logic 202a including, for example, a verification identifier (ID), from a non-volatile memory device upon the occurrence of a reset. The non-volatile memory device may be, for example, an EEPROM (electrically erasable programmable read-only memory). The download may be due to the fact that the reset wipes out any logic programmed in the FPGA.

In one embodiment, the hardware verification logic 202a of the initiator monitors the reserved pin <NUM> during the reset period for activity on the pin. The monitoring may continue until the reserved pin is no longer asserted low.

Turning now to the target, as with the initiator, the multiplexor 204b selects the hardware verification logic 202b in the SSD for communicating with the FPGA over the connector <NUM> in response to the reset pin <NUM> being asserted low. In one embodiment, given that the target is the device to be verified, the hardware verification logic 202b drives the reserved pin <NUM> of the connector <NUM> with the verification ID during the reset period. In one embodiment, the hardware verification logic 202b of the target receives the verification ID that is to be transmitted via the reserved pin <NUM> from the FPGA or the host processor, or the like.

The hardware verification logic 202a of the FPGA detects the verification ID on the monitored reserved pin <NUM>, and compares the received verification ID with an expected verification ID downloaded from the memory device. If the verification IDs fail to match, verification of the target SSD fails. The hardware verification logic 202a of the FPGA may write the results of the failed verification process to a defined register location. For example, a result of "not verified" may be written to the defined register location. If, however, the verification is successful, the hardware verification logic 202a of the FPGA may be configured to write a "verified" status to the defined register location.

In one embodiment, the FGPA may check the results of the verification in the defined register location prior to taking certain actions. Such actions may be, for example, to download or not, a proprietary bit file in addition to a standard bit file, during a boot sequence, and/or enable or disable certain acceleration features of the FPGA including compression, encryption, and the like. Other acceleration features that may be enabled or disabled depending on the verification results may include, for example, enabling/disabling a double data rate fourth generation synchronous dynamic random-access (DDR4) channel (if supported), enabling/disabling a high bandwidth memory (HBM) (if present), and or the like.

<FIG> is a block diagram of the exemplary computational storage device of <FIG> configured with the verification modules 200a, 200b of <FIG>, according to an exemplary embodiment. The hardware verification logic 202a that is executed by the storage component <NUM> may be incorporated into an initialization logic that is run by the storage controller during cold reboots. The hardware verification logic 202a that is executed by the processor component <NUM> may be stored in a non-volatile memory, such as an EEPROM, and loaded to the FPGA <NUM> upon a reset.

In one embodiment, the multiplexors 204a, 204b are respectively incorporated into the storage component <NUM> and the processor component <NUM>. In some embodiments, the multiplexors 204a, 204b may reside outside of the storage and/or processor components.

<FIG> is an exemplary signaling diagram of the verification modules <NUM> according to one exemplary embodiment. At a rise of a particular clock cycle <NUM>, the reset pin <NUM> is asserted low <NUM>, and a reset period begins. The reset period may last, for example, several seconds. In one embodiment, no activity of the rebooted device occurs during the reset period, and the lack of activity is utilized for performing verification by the initiator of the target device. In one example, the hardware verification logic 202b in the target device causes the reserved pin <NUM> to be driven from a low state <NUM> to a high state <NUM> as many times as needed based on a predetermined pattern dictated by the verification ID. In one embodiment, a minimum requirement may be that the pin be driven from a low state to a high state for at least one clock period, and from the high state to the low state for at least another clock period.

The initiator monitoring the reserved pin <NUM> during the reset period receives the verification ID. In one embodiment, a fixed counter is invoked by the initiator when a first signal is received on the reserved pin <NUM>. When the fixed counter reaches a particular value corresponding to the size of the expected verification ID, the initiator concludes that all of the verification ID has been received. Further, the initiator may cause the reserved pin <NUM> (not shown) to be driven to a low state <NUM>. This may occur, for example, prior to expiration of the reset period. The initiator compares the received verification ID against the expected verification ID for determining a match.

In one embodiment, when the reset pin <NUM> is no longer asserted <NUM> (e.g. at the expiration of the reset period), the reserved pin <NUM> serves to provide a chassis type. For example, the reserved pin <NUM> in a low state may indicate a chassis type of NVMe, and the reserved pin in a high state may indicate a chassis type of NVMe-oF.

<FIG> is a flow diagram of a hardware verification process according to one exemplary embodiment. It should be understood that the sequence of steps of the process is not fixed, but can be altered into any desired sequence as recognized by a person of skill in the art.

In act <NUM>, a reset is asserted by the host processor for a particular slot (e.g. in response to a host insertion of a device into the slot), or for the entire system.

In act <NUM>, the hardware verification logic 202a, 202b in the initiator and target is initiated in response to the reset. In one embodiment, a determination as to which modular component of the computational storage device is the initiator, and which modular component is the target, may depend on the device that connects first to the host device. In one embodiment, configuration or the module as the initiator or target may be via a programmable pin.

In act <NUM>, the hardware verification logic 202a of the initiator monitors the reserved pin <NUM> for determining whether the target is an authorized target. In one embodiment, the hardware verification logic 202a of the initiator compares the signals received via the reserved pin <NUM>, to the verification ID expected by the initiator. If the received signals match the expected verification ID, the target may be deemed to be authorized, and a "verified" status may be stored in a particular register location.

In act <NUM>, in response to verifying the target, the initiator takes one or more actions that are allowed to be performed with authorized targets. Such actions may include, for example, downloading FPGA bit files that are proprietary to the vendor providing the FPGA (in addition to the standard FPGA bit files) during a boot sequence, and continuing a PCIe link training sequence to establish a high speed I/O connection between the initiator and the target devices. Other actions may include enabling acceleration features of the processor component, enabling a DDR4 channel, and/or enabling a high bandwidth memory.

Referring again to act <NUM>, if the hardware verification logic 202a of the initiator is unable to verify the target (e.g. due to a mismatch of the received verification ID with the expected verification ID), the hardware verification logic 202a stores a "not verified" status in the particular register location in act <NUM>.

In act <NUM>, the initiator takes one or more actions in response to the target component failing the verification. Such actions may include, for example, proceeding with the boot sequence by downloading standard FPGA bit files without downloading a proprietary FPGA bit file, disabling certain acceleration features of the FPGA (e.g. compression, encryption, etc.), disabling the DDR4 channel, and/or disabling the HBM if present. In this manner, the computational storage device with the un-verified target component can be functional, but with limited capabilities.

In one embodiment, a notification is transmitted in act <NUM> for informing a user that the target device is not an authorized device. The notification may be displayed to the user, for example, as part of the functionality of the BIOS (Basic Input Output System).

Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "<NUM> to <NUM>" is intended to include all subranges between (and including) the recited minimum value of <NUM> and the recited maximum value of <NUM>, that is, having a minimum value equal to or greater than <NUM> and a maximum value equal to or less than <NUM>, such as, for example, <NUM> to <NUM>. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

Claim 1:
A storage device (100a, 100b, 100c) configured for hardware verification comprising:
a first hardware component (200a) comprising a connector (<NUM>) and a first verification logic (202a), the first verification logic (202a) configured to detect a criterion and generate a first signal via the connector (<NUM>) in response to detecting the criterion, wherein the criterion is detecting start of a reset period when a device is inserted into a slot of a computer system without stopping or shutting down the system; and
a second hardware component (200b) coupled to the first hardware component (200a) via the connector (<NUM>), the second hardware component (200b) comprising a second verification logic (202b), the second verification logic (202b) configured to monitor and receive the first signal via the connector (<NUM>),
wherein in response to receiving the first signal, the second verification logic (202b) is configured to compare the received first signal to an expected signal and generate a result,
wherein the storage device (100a, 100b, 100c) is configured to take an action in response to the result.