Patent Description:
Direct conversion of thermal energy into electric energy (and vice-versa) by Seebeck effect is a promising approach for harvesting energy from heat sources, particularly when reduced temperature gradients are involved and that, as such, would otherwise not be exploited (such as waste heat of industrial plants, residual heat of car engines, low temperature thermal sources).

Thermoelectric generators are low enthalpy waste heat exploitation devices that are used, for example, in battery-free radiator valve actuators or in torches (in this latter case, exploiting the difference in temperature between the human body temperature and the ambient temperature).

Thermoelectric generators make use of thermoelectric materials that are capable of generating power directly from the heat by converting temperature differences into electric voltage.

A good thermoelectric material should have both high electrical conductivity (σ) and low thermal conductivity (κ). Having low thermal conductivity ensures that when one side of the material is made hot, the other material side stays cold, which helps to generate a significant voltage even with a low temperature gradient.

Tellurium-based thermoelectric generators make use, as thermoelectric material, of materials based on Tellurium.

Tellurium compounds, such as Bismuth Telluride (Bi<NUM>Te<NUM>), exhibit good Seebeck coefficients (the Seebeck coefficient, also known as thermopower, thermoelectric power, thermoelectric sensitivity, of a material is a measure of the magnitude of an induced thermoelectric voltage in response to a temperature difference across that material, as induced by the Seebeck effect), high electrical conductivity and low thermal conductivity (just as an example, the thermal conductivity of Bismuth Telluride is 2W/mK). These properties make Bismuth Telluride suitable to be used to form the "thermoelectrically active elements" of a thermoelectric generator (by "thermoelectrically active elements" or "active elements" it is meant the thermoelectric elements in thermoelectric material that are capable of converting a thermal drop or temperature gradient across them into an electric potential by Seebeck effect).

A Tellurium-based thermoelectric generator includes a plurality of interconnected n-doped Bismuth Telluride active elements and p-doped Bismuth Telluride active elements (the active elements being also referred to as "legs") between a pair of opposite ceramic substrates provided with metal (Cu or Au) contact regions and conductive lines, that interconnect the plurality of n-doped and p-doped Bismuth Telluride active elements. The n-doped Bismuth Telluride active elements are formed as discrete elements, typically by means of a process that involves forming ingots starting from powder material and then dicing the ingots to form pellets that will then form the Seebeck legs when the pellets are put (in a manual or semi-automatic assembling stage) between the two ceramic substrate.

The existing Tellurium-based thermoelectric generators are therefore discrete components. Bismuth Telluride is not suitable to be used as a material in standard Integrated Circuit (IC) manufacturing processes, which instead are based on Silicon.

Moreover, Tellurium-based thermoelectric generators typically exhibit a relatively good efficiency only in a limited temperature range (usually, of the order of <NUM> around room temperature) and thermoelectric properties that rapidly degrade as temperature increases. This reduces the fields of application of the Tellurium-based thermoelectric generators.

Additionally, Tellurium is a relatively rare element, which inherently limits a widespread use thereof.

Furthermore, an extensive use of Tellurium compounds, such as Bismuth Telluride, could pose environmental problems, in particular in term of end-of-life device disposal.

In silicon-based thermoelectric generators, materials based on Silicon (n-doped and p-doped, so as to exhibit different Seebeck coefficients) are used as thermoelectric material to form the active elements.

Silicon-based thermoelectric generators manufactured with Silicon-compatible technologies can be classified in two families: in devices of a first family the heat flow is parallel to the substrate whereas in the other family the heat flow is orthogonal to the substrate ("out-of-plane" heat flux). The architectures of these integrated thermoelectric generators generally comprise a number of elementary cells having n-p doped legs, arranged in such a way that the elementary cells are thermally in parallel and electrically in series. Typically, integrated thermoelectric generators in which heat flows parallel to the substrate may have conductive legs of thermoelectrically active materials deposited over a very high thermal resistance material or a membrane, suspended several hundreds of micrometers above the substrate, or the legs of active materials themselves are free-standing (membrane-less).

Out-of-plane heat flux thermoelectric generators minimizes thermal losses, simplify thermal coupling at system level, enhancing overall performance, and are amenable to miniaturization and integration in microelectronic and optoelectronic devices, among other applications.

The paper by <NPL>, Honolulu, United States, <NUM>-<NUM>/<NUM>/<NUM> criticizes planar Si-based thermoelectric generators employing long Si-nanowires about <NUM>-<NUM> as active elements, which are suspended on a cavity to cutoff the bypass of the heat current to secure the temperature difference across the Si-nanowires. The authors of the paper propose a design concept of planar and short thermoelectric generator without cavity structure, which uses a steep temperature gradient formed in the vicinity of the main heat current.

<CIT> discloses an integrated thermoelectric generator of out-of-plane heat flux configuration. The generator further includes a top capping layer deposited onto a free surface, oriented in an opposite direction in respect to said void spaces, of said planar electrically non-conductive cover layer so as to occlude the through holes of the non-conductive cover layer.

The article "<NPL> discloses generators using BiCMOS technology by forming thermocouples of opposite conductivity silicon in a thick poly-Si or poly Si-Ge layer that is patterned to form the n- and p- legs. LOCOS oxide is used to thermally isolate the cold and the hot side.

<CIT> discloses a thermoelectric generator comprising columnar elements of polysilicon and opposite conductivities extending from a substrate that are grown in separate steps.

<CIT>, <CIT> and <CIT> disclose other thermoelectric generators of SiGe, or semiconductor alloys or metals.

The Applicant has realized that the Silicon-based thermoelectric generators proposed in the art exhibit drawbacks.

Silicon has a large electrical conductivity and a good Seebeck coefficient, but, as a thermoelectric material, it has the disadvantage of featuring a high thermal conductivity (<NUM> W/mK) compared to Bismuth Telluride (which has a thermal conductivity of <NUM> W/mK). Furthermore, Silicon-based thermoelectric generators having a cavity have a low mechanical stability because of the presence of the cavity. Other drawbacks of known Silicon-based thermoelectric generators are: difficulty to industrialize; low power (~ <NUM>µW /cm<NUM>); and high semiconductor area consumption.

The Applicant has tackled, among others, the problem of devising a novel thermoelectric converter overcoming, among others, the drawbacks that affect known thermoelectric generators.

According to the invention, a method of fabricating a thermoelectric converter and an integrated thermoelectric converter are provided, as defined in the attached claims.

The features and advantages of the present disclosure will be made apparent by the following description of example embodiments thereof, provided merely as non-limitative examples.

For its better intelligibility, the following description should be read making reference to the attached drawings, wherein:.

It is pointed out that the drawings in the figures are not necessarily drawn to scale.

In the following, reference will be made to the drawings, which show some steps of fabrication methods of a thermoelectric converter according to example embodiments of the present disclosure. In the drawings, like and/or corresponding elements are denoted by like reference numerals.

Reference is firstly made to <FIG>, which show some steps of a fabrication method.

Starting from a Silicon substrate (first Silicon wafer) <NUM>, a surface of the Silicon substrate <NUM> is oxidized (e.g., by means of thermal oxidation) to form a layer of oxide <NUM>, e.g., Silicon dioxide (SiO<NUM>). Then, a layer <NUM> of polycrystalline SiGe is formed over the layer of oxide <NUM>. The resulting structure is schematically depicted in <FIG>.

The layer <NUM> of polycrystalline SiGe is for example a layer of polycrystalline Si<NUM>Ge<NUM>. The layer <NUM> of polycrystalline SiGe can for example be formed by means of deposition, for example, but not limitatively, chemical deposition, for example, Chemical Vapor Deposition (CVD); among the several different CVD techniques, Low Pressure CVD (LPCVD) can for example be exploited. Deposition takes place from silane (SiH<NUM>) and germane (GeH<NUM>). Alternatively, the layer <NUM> of SiGe polysilicon can be formed by means of epitaxial growth in an epitaxial reactor. Both techniques produce a conformal layer <NUM> of polycrystalline SiGe.

The layer <NUM> of polycrystalline SiGe can for example have a thickness of some microns, e.g., about <NUM>.

Then, as depicted in <FIG>, alternated n+ doped regions 120a and p+ doped regions 120b of n+ doped and, respectively, p+ doped polycrystalline SiGe are formed in the layer <NUM> of polycrystalline SiGe. The dopants (donor dopants for the n+ doped regions 120a and acceptor dopants for the p+ doped regions 120b) can be selectively introduced into the layer <NUM> of polycrystalline SiGe by ion implantation. For example, suitable donor dopants can be Phosphorus or Arsenic, a suitable acceptor dopant can be Boron. The n+ doped regions 120a and p+ doped regions 120b can for example take shape of substantially parallel strips formed in the layer <NUM> of polycrystalline SiGe (where "parallel" is meant to intend along a direction orthogonal to the plane of the drawing sheet of <FIG>), alternated and for example (but not limitatively) contiguous to each other (in a direction from the left to the right of the drawing sheet).

The steps of forming a layer of polycrystalline SiGe and forming, in the layer of polycrystalline SiGe, n+ and p+ doped regions are repeated twice or more times. As depicted in <FIG>, every new layer of polycrystalline SiGe is formed (for example by the same technique as the first layer <NUM> of polycrystalline SiGe) on the preceding layer of polycrystalline SiGe, and in each newly formed layer of polycrystalline SiGe n+ and p+ doped regions 120a and 120b are formed (for example, by ion implantation) in (vertical, e.g., in a direction from the bottom to the top of the drawing sheet of <FIG>) alignment with the previously formed n+ and p+ doped regions 120a and 120b formed in the preceding layer(s) of polycrystalline SiGe. In this way, stacks 125a of n+ doped regions and stacks 125b of p+ doped regions are obtained, from which the thermoelectric elements of the thermoelectric converter will be formed. In this way, the stacks 125a of n+ doped regions and the stacks 125b of p+ doped regions take the form of substantially parallel strips formed in the stack of layers of polycrystalline SiGe (where, again, "parallel" is meant to intend along the direction orthogonal to the plane of the drawing sheet of <FIG>), alternated and for example (but not limitatively) contiguous to each other (in the direction from the left to the right of the drawing sheets), as visible, e.g., in <FIG>.

The number of times that the steps of forming a layer of polycrystalline SiGe and forming, in the layer of polycrystalline SiGe, n+ and p+ doped regions are repeated depends on the thickness of each one of the layers of polycrystalline SiGe (the stacked layers of polycrystalline SiGe may have all the same thickness or different thicknesses from each other), and on the desired overall thickness of the stack of layers of polycrystalline SiGe. The overall thickness of the stack of layers of polycrystalline SiGe should be such as to ensure a sufficient thermal difference between the bottom and the top of the stacks 125a of n+ doped regions and stacks 125b of p+ doped regions, even for relatively low temperature gradients. For example, the overall thickness of the stack of layers of polycrystalline SiGe can be of some tens of microns, particularly from about <NUM> to about <NUM> (thus, for an example thickness of the generic layer of polycrystalline SiGe of about <NUM>, the steps of forming a layer of polycrystalline SiGe and forming, in the layer of polycrystalline SiGe, n+ and p+ doped regions are repeated some tens of times).

Trenches <NUM> are then formed in the stacks 125a of n+ doped regions and in the stacks 125b of p+ doped regions. The trenches <NUM> are for example formed as cylindrical shells. The trenches <NUM> extend down to the layer of oxide <NUM>. Multiple trenches <NUM> are formed along each stack 125a and 125b, that are strip-like shaped, as shown in <FIG>. Each trench <NUM> delimits a respective (e.g., cylindrical) portion 133a of a respective stack 125a of n+ doped regions or a respective (e.g., cylindrical) portion 133b of a respective stack 125b of p+ doped regions, which portions 133a and 133b remain separated from the rest of the respective stack 125a of n+ doped regions and stack 125b of p+ doped regions. The (e.g., cylindrical) portions 133a and 133b of the stacks 125a of n+ doped regions and of the stacks 125b of p+ doped regions will form the thermoelectrically active elements (e.g., the "legs") of the thermoelectric converter.

By means of an oxidation process the trenches <NUM> are filled with oxide and the top surface of the structure (e.g., the surface opposite to the Silicon substrate <NUM>) is covered by an oxide layer <NUM>. The oxide can for example be SiO<NUM>. In particular, the oxidation process can involve a thermal oxidation process for coating the lateral walls of the trenches <NUM> with oxide, followed by a deposition of a thick oxide layer using TEOS (TetraEthyl OrthoSilicate) filling the trenches and covering the surface of the structure with the oxide layer <NUM>. The resulting structure is shown in <FIG>. In this way, the (e.g., cylindrical) portions of the stacks 125a of n+ doped regions and of the stacks 125b of p+ doped regions which are delimited by the trenches <NUM> remain insulated from the remaining of the respective stacks 125a of n+ doped regions and stacks 125b of p+ doped regions. As mentioned, the (e.g., cylindrical) portions of the stacks 125a of n+ doped regions and of the stacks 125b of p+ doped regions which are delimited by the trenches <NUM> will form the thermoelectric elements (e.g., the "legs") 133a (n doped, e.g., having a first Seebeck coefficient, particularly of a first sign, e.g., positive) and 133b (p doped, e.g., having a second, different Seebeck coefficient, particularly of an opposite sign, e.g., negative) of the thermoelectric converter.

As visible in <FIG>, contact openings are formed in the oxide layer <NUM> in correspondence of the n+ doped thermoelectric elements 133a and of the p+ doped thermoelectric elements 133b delimited by the trenches <NUM>, and a conductive layer <NUM>, e.g., of a metal, is formed on the oxide layer <NUM> and then patterned to define conductive lines <NUM> interconnecting the n+ doped thermoelectric elements 133a and the p+ doped thermoelectric elements 133b. The surface of the structure is then covered by a layer <NUM> of oxide, e.g., SiO<NUM>.

Reference is now made to <FIG>, which show some steps of a method.

Starting from a Silicon substrate (first Silicon wafer) <NUM>, a surface of the Silicon substrate <NUM> is oxidized to form a layer of oxide <NUM>, e.g., Silicon dioxide (SiO<NUM>).

Then, a (relatively thick) layer <NUM> of polycrystalline Silicon ("epi-poly") is formed over the layer of oxide <NUM>. The layer <NUM> of polycrystalline Silicon is for example formed by means of epitaxial growth in an epitaxial reactor.

The resulting structure is depicted in <FIG>.

The thickness J of the layer <NUM> of polycrystalline Silicon should be such as to ensure a sufficient thermal difference between the bottom and the top of the thermoelectric elements that will be formed therewithin (as described in the following), even for relatively low ambient temperature gradients. For example, the thickness of the layer <NUM> can be of some tens of microns, particularly from about <NUM> to about <NUM>.

A surface of the layer <NUM> of polycrystalline Silicon is then oxidized to form a layer <NUM> of oxide, for example a layer of Silicon dioxide (SiO<NUM>). The resulting structure is shown in <FIG>.

As shown in <FIG>, trenches <NUM> are then formed in the layer <NUM> of polycrystalline Silicon. The trenches <NUM> extend down to the layer of oxide <NUM> that covers the surface of the Silicon substrate <NUM>. The trenches <NUM> may for example be cylindrical. The trenches <NUM> may for example have a width w of about <NUM>.

The walls of the trenches <NUM> are then covered by a layer of oxide <NUM>, e.g., a layer of Silicon dioxide (SiO<NUM>), as depicted in <FIG>, e.g., by means of thermal oxidation. In this way, cylindrical shells of oxide <NUM> are created inside the trenches <NUM>.

A layer <NUM> of n+ doped polycrystalline SiGe is formed over the surface of the structure (e.g., the surface opposite to the Silicon substrate <NUM>). The layer <NUM> of n+ doped polycrystalline SiGe is for example a layer of n+ doped polycrystalline Si<NUM>Ge<NUM> polysilicon. The layer <NUM> of n+ doped polycrystalline SiGe can for example be formed by means of deposition, particularly chemical deposition, even more particularly Chemical Vapor Deposition (CVD); among the several different CVD techniques, Low Pressure CVD (LPCVD) can be exploited. Deposition takes place from silane (SiH<NUM>) and germane (GeH<NUM>). The n+ doped polycrystalline SiGe is conformal. During the deposition process, n+ doped polycrystalline SiGe fills the trenches <NUM> (with walls covered by the oxide <NUM>). The resulting structure is shown in <FIG>.

By means of a Chemical-Mechanical Polishing ("CMP") step, the layer <NUM> of n+ doped polycrystalline SiGe is removed from over the surface of the layer <NUM> of oxide, leaving only (e.g., cylindrical) portions <NUM> of the n+ doped polycrystalline SiGe within the trenches <NUM> (with walls covered by the oxide <NUM>), as depicted in <FIG>.

Further trenches <NUM> are then formed in the layer <NUM>. Like the trenches <NUM>, the further trenches <NUM> extend down to the layer of oxide <NUM> covering the surface of the Silicon substrate <NUM>. The further trenches <NUM> may for example be cylindrical. Like the trenches <NUM>, the trenches <NUM> may for example have a width of about <NUM>. The further trenches <NUM> are formed so as to obtain a structure, shown in <FIG>, in which the further trenches <NUM> are alternated with the trenches <NUM>.

The walls of the further trenches <NUM> are then covered by a layer of oxide <NUM>, e.g., a layer of Silicon dioxide (SiO<NUM>), for example by means of a thermal oxidation process, as depicted in <FIG>. In this way, cylindrical shells of oxide <NUM> are created inside the trenches <NUM>.

A layer <NUM> of p+ doped polycrystalline SiGe is formed over the surface of the structure. The layer <NUM> of p+ doped polycrystalline SiGe is for example a layer of p+ doped polycrystalline Si<NUM>Ge<NUM>. The layer <NUM> of p+ doped polycrystalline SiGe can for example be formed by means of deposition, particularly chemical deposition, even more particularly Chemical Vapor Deposition (CVD); among the several different CVD techniques, Low Pressure CVD (LPCVD) can be exploited. Deposition takes place from silane (SiH<NUM>) and germane (GeH<NUM>). The p+ doped polycrystalline SiGe is conformal. During the deposition process, p+ doped polycrystalline SiGe fills the further trenches <NUM> (with walls covered by the oxide <NUM>). The resulting structure is shown in <FIG>.

By means of a Chemical-Mechanical Polishing ("CMP") step, the layer <NUM> of p+ doped polycrystalline SiGe is removed from over the surface of the layer <NUM> of oxide, leaving only (e.g., cylindrical) portions <NUM> of the p+ doped polycrystalline SiGe within the further trenches <NUM> (with walls covered by the oxide <NUM>), as depicted in <FIG>.

In this way, the (e.g., cylindrical) portions <NUM> of n+ doped polycrystalline SiGe and the (e.g., cylindrical) portions <NUM> of p+ doped polycrystalline SiGe which are delimited by the trenches <NUM> and <NUM> (with walls covered by the oxide <NUM> and <NUM>) remain insulated from the surrounding layer <NUM> of polycrystalline Silicon. These (e.g., cylindrical) portions <NUM> of n+ doped polycrystalline SiGe and portions <NUM> of p+ doped polycrystalline SiGe will form the thermoelectric elements (e.g., the "legs") of the thermoelectric converter.

It is pointed out that each of the portions <NUM> of n+ doped polycrystalline SiGe and each of the portions <NUM> of p+ doped polycrystalline SiGe which are visible in <FIG> may identify a respective array of portions <NUM> of n+ doped polycrystalline SiGe (each one formed inside a respective trench <NUM> with walls covered by the oxide <NUM>) and a respective array of portions <NUM> of n+ doped polycrystalline SiGe (each one formed inside a respective further trench <NUM> with walls covered by the oxide <NUM>), extending along a direction orthogonal to the plane of the drawing sheet of <FIG> (as can be clearly understood looking at <FIG>, to be described later on).

The surface of the structure (opposite to the Silicon substrate <NUM>) is then oxidized, to form a layer of oxide <NUM>, e.g., a layer of Silicon dioxide (SiO<NUM>), covering the whole surface of the structure, as shown in <FIG>.

As visible in <FIG>, contact openings are formed in the oxide layer <NUM> in correspondence of each of the portions <NUM> of n+ doped polycrystalline SiGe and each of the portions <NUM> of p+ doped polycrystalline SiGe, and a conductive layer <NUM>, e.g., of a metal, is formed on the oxide layer <NUM> and then patterned to define first conductive lines <NUM> interconnecting the thermoelectric elements <NUM> and <NUM>. The surface of the structure is then covered by a further oxide layer <NUM>, e.g., SiO<NUM>. Oxide layers <NUM> and <NUM> form, together a surface oxide layer <NUM> embedding the first conductive lines <NUM>.

According to the invention, the thermoelectric elements <NUM> and <NUM>, instead of being made of n+ doped and p+ doped polycrystalline SiGe, respectively, are made of n-doped and p-doped porous Silicon, respectively. Porous Silicon has an advantageously small thermal conductivity (<NUM> -<NUM> W/m K for porosity - <NUM>%). The n-doped and p-doped porous Silicon thermoelectric elements <NUM> and <NUM> can be obtained by converting n+ and p+ doped polycrystalline Silicon, respectively.

<FIG> depicts some steps of a process for forming the thermoelectric elements <NUM> and <NUM> made of porous Silicon.

Starting from the structure shown in <FIG>, a mask layer <NUM> (e.g., a Silicon nitride layer or a thick oxide layer) is formed over the layer <NUM> of oxide, as depicted in <FIG>.

As shown in <FIG>, trenches <NUM> are then formed by selective etching, which trenches <NUM>, starting from the surface of the mask layer <NUM> (that protects the structure from etching where tranches are not to be formed), extend down to the layer of oxide <NUM> that covers the Silicon substrate <NUM>. The trenches <NUM> can be similar to the trenches <NUM> of the previously described embodiment (for example, cylindrical trenches having a width of about <NUM>.

As depicted in <FIG>, the walls of the trenches <NUM> are then coated by a layer of oxide <NUM>, for example by means of a thermal oxidation process.

As shown in <FIG>, a mask layer <NUM> of, e.g., Silicon nitride is then deposited over the whole structure. The material of the mask layer <NUM> penetrates into the trenches <NUM> and coats the walls and the bottom of the trenches <NUM>.

Moving to <FIG>, the structure is subjected to an etch process during which part of the mask layer <NUM> is etched away; the etch stops when the material of the mask layer <NUM> and the portion of the layer of oxide <NUM> at the bottom of the trenches <NUM> are removed, thereby leaving the Silicon substrate <NUM> exposed at the bottom of the trenches <NUM>.

Process steps similar to those shown in <FIG> are then performed to fill the trenches <NUM> with n+ and p+ doped polycrystalline Silicon.

After a chemical-mechanical polishing step, the structure depicted in <FIG> is obtained (in this and in the following figures the layer of Silicon nitride which, after the etch of step 3E, remains at the top surface and on the lateral walls of the trenches <NUM>, is not shown for the sake of better intelligibility). The trenches <NUM> are filled with (e.g., cylindrical) pillars 325a and 325b of n+ and p+ doped polycrystalline Silicon, respectively.

The pillars 325a and 325b of n+ and p+ doped polycrystalline Silicon are then converted into pillars of n+ and p+ doped porous Silicon. To this purpose, the structure is immersed in a tank or anodization cell, e.g., made of Teflon, filled with a solution of hydrofluoric (HF) acid and provided with an anode and a cathode. The structure to be processed is connected to the anode (the cathode can for example be a mesh electrode made of Platinum). The HF acid affects the pillars 325a and 325b of n+ and p+ doped polycrystalline Silicon, transforming them into pillars of n+ and p+ doped porous Silicon. Preferably, the process is stopped before the bottom portions (base) of the pillars 325a and 325b of n+ and p+ doped polycrystalline Silicon are transformed into porous Silicon. This ensures that the integrity of the porous silicon is preserved during the subsequent phases of the fabrication process. The resulting structure is depicted in <FIG>, where references 330a and 330b denotes the pillars of n+ and p+ doped porous Silicon, respectively, and reference <NUM> denotes the bottom portions of the pillars 330a and 330b that have not undergone the transformation into porous Silicon.

In embodiments, the process may envisage the formation (e.g., by deposition) of a layer of polycrystalline Silicon <NUM> over the surface of the structure. Donor and acceptor dopant ions are then selectively implanted into the polycrystalline Silicon <NUM> to form n+ and p+ doped polycrystalline Silicon areas 345a and 345b over the pillars of n+ and p+ doped porous Silicon 330a and 330b, respectively. The resulting structure is depicted in <FIG>. The remaining portions of the layer of polycrystalline Silicon <NUM> (other than the n+ and p+ doped polycrystalline Silicon areas 345a and 345b) are then etched away, to obtain the structure depicted in <FIG>. In this way, the n+ and p+ doped polycrystalline Silicon areas 345a and 345b over the pillars of n+ and p+ doped porous Silicon 330a and 330b provide enlarged contact areas to the pillars of n+ and p+ doped porous Silicon 330a and 330b that may facilitate the formation of electrical contacts to the pillars. Similar considerations may apply to the first two embodiments described in the foregoing.

<FIG> show some steps of a method according to an example embodiment of the present disclosure for proceeding with the fabrication of the thermoelectric converter of any one of the previously described embodiments. Despite the steps of the fabrication method which will be described hereafter apply as well to any of the embodiments described so far, for mere reasons of simplicity they will be described and shown making reference to the second embodiment described in <FIG>.

As shown in <FIG>, starting from the structure of <FIG>, a second Silicon wafer <NUM> is bonded to the surface of the structure opposite to the Silicon substrate (first Silicon wafer) <NUM>.

The Silicon substrate (first Silicon wafer) <NUM> is then removed, as shown in <FIG> (in which figure, as well as in the following figures <FIG> and <FIG>, the structure is depicted upside-down compared to <FIG>). After removal of the Silicon substrate (first Silicon wafer) <NUM>, the layer <NUM> of oxide remains uncovered.

Contacts openings are formed in the layer <NUM> of oxide in correspondence of the thermoelectric elements <NUM> and <NUM>, and a conductive layer <NUM>, e.g., of a metal, is formed on the oxide layer <NUM> and then patterned to define second conductive lines <NUM> interconnecting the thermoelectric elements <NUM> and <NUM>. The resulting structure is shown in <FIG>.

The surface of the structure is then covered by a further layer <NUM> of oxide, e.g., SiO<NUM>, obtaining the structure of <FIG>.

The second Silicon wafer <NUM> is then selectively etched to form trenches, leaving the material of the second Silicon wafer only over the thermoelectric elements <NUM>, <NUM>, and, where the second Silicon wafer <NUM> is removed, the oxide layer <NUM> that covered the first conductive lines <NUM> is etched and removed to leave portions <NUM>', <NUM>" of the first conductive lines <NUM> exposed; the exposed portions <NUM>', <NUM>" of the first conductive lines <NUM> will form contact pads of the thermoelectric converter, for soldering bonding wires <NUM> (similar portions of the conductive lines <NUM> in the structure of <FIG> will form the contact pads). The resulting structure is shown in <FIG> (oriented similarly to <FIG>).

The side of the structure where there is the (portion of the) second Silicon wafer <NUM> (left and not removed) will, in use, be for example the "hot" side of the thermoelectric converter (e.g., the side where the temperature of the environment where the thermoelectric converter is inserted is higher), while the opposite side of the structure will, in use, be for example the "cold" side of the thermoelectric converter (e.g., the side where the temperature of the environment where the thermoelectric converter is inserted is lower). Naturally, in use the role of the "hot" and "cold" sides of the thermoelectric converter can be reverted: generally, the two sides of the thermoelectric converter will in use experiment a temperature gradient. The portion(s) of the second Silicon wafer <NUM> left and not removed can form a structural support for the device.

<FIG> shows an alternative to steps 4D and 4E for the formation of contact pads for the bonding wires <NUM>. In this case, the contact pads can be portions of the second conductive lines <NUM> interconnecting the thermoelectric elements <NUM> and <NUM>. To open contact areas for the contact pads, the layer <NUM> of oxide is selectively etched. It is not necessary to selectively etch the second Silicon wafer <NUM>, which can be left as it is for acting as a mechanical support for the structure.

<FIG> shows the layout of the structure obtained by the fabrication process of <FIG> and subsequent steps like those shown in <FIG>. The device comprises a plurality of first thermoelectric elements 133a (n doped, e.g., having a first Seebeck coefficient, particularly of a first sign, e.g., positive) and a plurality of second thermoelectric elements 133b (p doped, e.g., having a second, different Seebeck coefficient, particularly of an opposite sign, e.g., negative). Each first thermoelectric element and each second thermoelectric element has a first end at the "hot" side of the device and a second end at the "cold" side of the device. The first and second thermoelectric elements 133a and 133b are arranged in alternated arrays that extend parallel to each other and are contacted (at the opposite ends of the thermoelectric elements, "hot" side and "cold" side") by the conductive lines <NUM> (here forming first conductive lines <NUM>) and second conductive lines <NUM>, in "zig-zag" fashion. The first conductive lines <NUM> have an input contact pad <NUM>' and an output contact pad <NUM>".

The first and second thermoelectric elements 133a and 133b are thermally in parallel and electrically in series.

<FIG> shows the layout of the structure obtained by the fabrication process of <FIG> (or 3A - <NUM>) and 4A - 4D and 4F.

Therefore, the device of <FIG> comprises a plurality of first thermoelectric elements <NUM> (n doped, e.g., having a first Seebeck coefficient, particularly of a first sign, e.g., positive) and a plurality of second thermoelectric elements <NUM> (p doped, e.g., having a second, different Seebeck coefficient, particularly of an opposite sign, e.g., negative). Each first thermoelectric element <NUM> and each second thermoelectric element <NUM> has a first end at the "hot" side of the device and a second end at the "cold" side of the device. The first and second thermoelectric elements <NUM> and <NUM> are arranged in alternated rows or arrays that extend parallelly to each other and are contacted (at the opposite ends of the thermoelectric elements, "hot" side and "cold" side") by the first conductive lines <NUM> and the second conductive lines <NUM>, in "zig-zag" fashion. The second conductive lines <NUM> have an input contact pad <NUM>' and an output contact pad <NUM>".

The first and second thermoelectric elements <NUM> and <NUM> are thermally in parallel and electrically in series.

<FIG> schematically shows in terms of a simplified block diagram an electronic system <NUM> comprising a thermoelectric converter according to an embodiment of the present disclosure.

The system <NUM> comprises a thermoelectric converter <NUM>, for example a thermoelectric generator, adapted to convert heat, represented by the arrows <NUM>, in an environment in which the system <NUM> is located, into electric energy which is exploited to charge a battery <NUM> of the system <NUM>. The battery <NUM> supplies electric energy to an application <NUM>, e.g., an electronic subsystem such as a smart watch, a wearable device, a torch, and so on.

The proposed solution exhibits several advantages. It is easy to industrialize, provides power levels of the order of mA, has a low consumption of semiconductor area, and works with low or high temperature differences. Moreover, the proposed solution allows the size of standard thermoelectric devices to be reduced from macroscale to microscale and exploiting technological steps typical of semiconductor (Silicon) manufacturing technology.

The thermoelectric converter according to the present disclosure can be exploited in several practical applications, such as wearable and fitness gears, pedometers and heart-rate meters, smart watches and wrist bands, wireless sensor nodes for smart homes and cities, as well as in other energy harvesting systems, as discussed below with reference to <FIG>.

Furthermore, the thermoelectric converter according to the present disclosure may be used in solar energy recovery devices, as disclosed herein.

<FIG> show some steps of a method according to an example embodiment of the present disclosure for manufacturing a solar energy recovery device using the thermoelectric converter of any one of the previously described embodiments. Despite the steps of the fabrication method which will be described hereafter apply as well to any of the embodiments described so far, for simplicity they will be described and shown as a continuation of the process steps described with reference to <FIG> and 4F. In the cross-sections of <FIG>, <FIG> (taken along cross-section plane VIII-VIII of <FIG>) and in the cross-section of <FIG> (taken along cross-section plane XI-XI of <FIG>), only the first conductive lines <NUM> are completely visible; second conductive lines <NUM> are visible only in part.

As shown in <FIG>, a third silicon wafer <NUM> is bonded to a surface 500A of the structure of <FIG>, here denoted by <NUM> and also called thermoelectric generator structure <NUM>; surface 500A is opposite to the second silicon wafer <NUM>. The third silicon wafer <NUM> may be a silicon wafer, in particular monocrystalline silicon, doped with acceptor dopants, thus of P type, and has a first surface 501A and a second surface 501B. The third silicon wafer <NUM> is bonded to thermoelectric generator structure <NUM> at its first surface 501A.

To this end, a bonding multilayer <NUM> is used; for example, bonding multilayer <NUM> may include a first bonding layer <NUM> extending on surface 500A of thermoelectric generator structure <NUM>; a second bonding layer <NUM> extending on first surface 501A of the third silicon wafer <NUM>; and an intermediate bonding layer <NUM>. The material of the first bonding layer <NUM> and of the second bonding layer <NUM> may be copper (Cu); the material of intermediate bonding layer <NUM> may be tin (Sn).

The first bonding layer <NUM>, the second bonding layer <NUM> and the intermediate bonding layer <NUM> may be applied on either the surface 500A of thermoelectric generator structure <NUM> or on the first surface 501A of the third silicon wafer <NUM>. In the alternative, the first bonding layer <NUM> may be applied to the surface 500A of thermoelectric generator structure <NUM>, the second bonding layer <NUM> may be applied to the first surface 501A of the third silicon wafer <NUM> and the intermediate bonding layer <NUM> may be applied on one of the latter.

In some embodiments, the bonding multilayer <NUM> is defined to form an annular portion 502A surrounding the area accommodating the thermoelectric elements <NUM>, <NUM> in the thermoelectric generator structure <NUM> (see also <FIG>). The bonding multilayer <NUM> further forms intermediate finger-like portions 502B that may be arranged in various ways in order to allow a good bonding and to allow connections to extend on surface 500A of thermoelectric generator structure <NUM> or on the first surface 501A of the third silicon wafer <NUM>.

For example, the thermoelectric elements <NUM>, <NUM> of <FIG> form a plurality of thermoelectric modules <NUM> (see <FIG>), coupled in parallel to each other. In the embodiment of <FIG>, <FIG> and <FIG>, each thermoelectric module <NUM> may comprise one row thermoelectric elements <NUM> and one row of thermoelectric elements <NUM> (see, e.g., <FIG>), coupled as also shown in <FIG>; in the alternative, each thermoelectric module <NUM> may comprise the entire structure shown in e.g., <FIG>.

In some embodiments, the thermoelectric modules <NUM> are coupled by connections <NUM> that may be formed partly in the oxide layer <NUM> and partly on the oxide layer <NUM> (<FIG>). Connections <NUM> are coupled to an input pad <NUM> and to an output pad <NUM> arranged on the periphery of the thermoelectric generator structure <NUM> in an interruption of the annular portion 502A of bonding multilayer <NUM>. Input pad <NUM> and output pad <NUM> may be coupled to input contact pad <NUM>' and to output contact pad <NUM>" of <FIG> by vias, in a per se known manner. In addition, the annular portion 502A forms a anode pad <NUM>, as explained hereinafter.

In <FIG>, an implant of N+-type doping species is performed in the third wafer <NUM> through the second surface 501B thereof. For example, suitable N+-type doping species may be phosphorus or arsenic.

Then, the implant is annealed and activated by a powerful laser beam pulse. The pulse length may be in the order of a hundred nanosecond (< <NUM> ns). Thereby, cathode region <NUM> is formed. The heat generated by the pulse is enough for local annealing, eliminating local implantation damages and activating the dopants. In particular, using a very short pulse, no temperature change is produced in the metal regions; thereby, the bonding multilayer <NUM>, the first and second conductive lines <NUM>, <NUM> and the connections <NUM> are not affected.

Cathode region <NUM> forms, together with the underlying portion of the third wafer <NUM> (also called hereinafter substrate <NUM>, of P-type), a diode that is able to convert solar energy into a current, in a per se known manner. Thereby, the third wafer <NUM> forms a solar photovoltaic cell wafer <NUM>.

In <FIG>, the third wafer <NUM> is etched, to remove a portion thereof overlying pads <NUM>-<NUM> (see also <FIG> showing the thermoelectric generator structure <NUM> and the third wafer <NUM> as if there were not yet bonded). Etching may be performed by laser or blade cutting. Thereby, a recess <NUM> is formed that exposes pads <NUM>-<NUM>.

Wires <NUM> are bonded to the input and output pads <NUM>, <NUM> and external connections 531A, 531B are bonded to the anode pad <NUM> and to the cathode region <NUM>, respectively. The external connections 531A, 531B may be wires or cables.

Thereby, a solar photovoltaic-thermoelectric module <NUM> is obtained.

<FIG> shows an example connection of three solar photovoltaic-thermoelectric modules <NUM> to form a hybrid solar energy recovery device <NUM>. In general, a plurality of solar photovoltaic-thermoelectric modules <NUM> may be coupled to each other in series or in parallel, with the input pads <NUM> of all solar photovoltaic-thermoelectric modules <NUM> coupled together and the output pads <NUM> of all solar photovoltaic-thermoelectric modules <NUM> coupled together, through respective external connections 531A, 531B.

Hybrid solar photovoltaic-thermoelectric device <NUM> is able to efficiently recover electric energy.

Conventional solar cells are able to absorb photon energy of the solar radiation only at frequencies that are near the solar cell band-gap and the remaining energy is converted into thermal energy and wasted. In addition, the conversion efficiency drops with temperature.

Vice versa, with the solar photovoltaic-thermoelectric modules of <FIG>, waste heat produced at the solar photovoltaic cell wafer <NUM> may be recovered by the thermoelectric generator structure <NUM> and the total power is the sum of the power supplied by the thermoelectric generator <NUM> and the power supplied by the solar photovoltaic cell wafer <NUM>, thereby providing a synergetic effect.

Manufacturing may be made using usual techniques in the semiconductor industry. For example, the solar photovoltaic cell wafer <NUM> is bonded before front end. In this way, possible breakages (for example of metal regions) that may occur during bonding due to the pressure exerted by the piston on the two wafers are avoided.

<FIG> and <FIG> show a thermoelectric generator, obtained by aerosol-jet printing of a semiconductor material. material which does not form part of the present invention. In particular, Maskless Mesoscale Material Deposition (M3D) may be used for depositing the semiconductor material. According to one aspect bismuth telluride (Bi<NUM>Te<NUM>) regions of opposite conductivity type are printed.

For example, <FIG> shows a first wafer <NUM> and a second wafer <NUM>. First and second wafers <NUM>, <NUM> may be silicon wafers, for example monocrystalline silicon wafers. One of the wafers <NUM>, <NUM>, here second wafer <NUM>, is P-type.

First wafer <NUM> has a surface 600A on which alternatively P-type bismuth telluride regions <NUM> and first adhesion regions <NUM> have been deposited using M3D.

Second wafer <NUM> has a surface 601A on which alternatively N-type bismuth telluride regions <NUM> and second adhesion regions <NUM> have been deposited using M3D.

P-type bismuth telluride regions <NUM> and first adhesion regions <NUM> are deposited on first metal regions <NUM> extending on the surface 600A of the first wafer <NUM>. N-type bismuth telluride regions <NUM> and second adhesion regions <NUM> are deposited on second metal regions <NUM>. First and second metal regions <NUM>, <NUM> may be, for example, of gold (Au).

For example, a bismuth telluride region <NUM> or <NUM> and an adhesion region <NUM> or <NUM> are formed on each metal region <NUM> and the distance between a P-type bismuth telluride region <NUM> and the adjacent first adhesion regions <NUM> is the same as the distance between an N-type bismuth telluride region <NUM> and the adjacent second adhesion regions <NUM>.

In addition, although completely visible in <FIG>, metal regions <NUM>, <NUM> typically have the pattern shown in <FIG> or <FIG> for the conductive lines <NUM> or <NUM> and <NUM> for connecting the bismuth telluride regions <NUM>, <NUM> in series. Adhesion regions <NUM> and <NUM> may be a tin-silver (Sn-Ag) alloy and have a lower thickness than the bismuth telluride regions <NUM>, <NUM>. Bismuth telluride regions <NUM>, <NUM> have here the same thickness, for example in the range <NUM>-<NUM>; adhesion regions <NUM>, <NUM> have the same thickness, for example in the range <NUM>-<NUM>.

First and second wafers <NUM>, <NUM> are bonded to each other by turning one wafer (here second wafer <NUM>) upside down and bonding the P-type bismuth telluride regions <NUM> to the second adhesion regions <NUM> and the N-type bismuth telluride regions <NUM> to the first adhesion regions <NUM>, <FIG>.

Bonding may be done by applying a pressure (e.g. <NUM>-<NUM> MPa) at a low temperature, e.g., about <NUM>.

After bonding, bismuth telluride regions <NUM>, <NUM> form thermoelectric elements.

Then, an implant of N+-type doping species is performed in one of the wafers <NUM>, <NUM>, here second wafer <NUM>, through its exposed surface. For example, phosphorus or arsenic ions are implanted.

Then, the implant is annealed and activated by a powerful laser beam pulse, forming cathode region <NUM>. The rest of the second wafer <NUM> forms an anode region <NUM>.

The structure of <FIG> may be subject to the manufacturing step discussed above with reference to <FIG>, <FIG>.

A plurality of solar photovoltaic-thermoelectric modules <NUM> may be coupled as shown in <FIG>, to form a hybrid solar energy recovery device.

<FIG> shows a solar photovoltaic-thermoelectric module <NUM> that is similar to solar photovoltaic-thermoelectric module <NUM> of <FIG> but for the arrangement of the bismuth telluride regions <NUM>, <NUM> that are here all formed on a same wafer, here the first wafer <NUM> and the adhesion regions, here denoted by reference number <NUM>, that are all formed on the other wafer, here the second wafer <NUM>. The other elements have been denoted by same reference numbers of <FIG>.

In some implementations, in the embodiment of <FIG>, through a M3D printing technique, both P-type and N-type bismuth telluride regions <NUM>, <NUM> are printed on the first wafer <NUM> (after forming the first metal regions <NUM>), and the adhesion regions <NUM> are printed all on the second wafer <NUM> (after forming the second metal regions <NUM>).

After bonding the first and second wafers <NUM>, <NUM>, the solar photovoltaic-thermoelectric module <NUM> is obtained.

The energy recovered by solar photovoltaic-thermoelectric module <NUM> of <FIG> or the solar photovoltaic-thermoelectric module <NUM> of <FIG> may be increased by the use of a passive cooling system, as shown in <FIG>.

<FIG> shows a solar energy recovery system <NUM> comprising a solar collector panel <NUM> and a loop <NUM> for recirculating a cooling fluid. In the considered system, the cooling fluid is water and the following description is made considering water; other cooling fluids may however be used.

A tank <NUM>, having a cold water input tap <NUM> and a warm water output tap <NUM>, is arranged along the water recirculation loop <NUM>.

The solar collector panel <NUM> accommodates a plurality of solar photovoltaic-thermoelectric modules <NUM>, <NUM> or <NUM>, coupled together as shown in <FIG>. The solar photovoltaic-thermoelectric modules <NUM>, <NUM> or <NUM> may be attached to a support wall <NUM> that delimits a water chamber <NUM> arranged along the loop <NUM>. The water chamber <NUM> has an input (cold) side 811A and an output (warm) side 811B; the tank <NUM> is arranged near the output (warm) side 811B of the water chamber <NUM>.

The water in the loop <NUM> circulate without the need of pumps, due to the temperature gradient between the input (cold) side 811A and the output (warm) side 811B, as well as because of the principle of communication vessels.

For example, the loop <NUM> may include an underground section <NUM> that extends under the ground level (indicated by <NUM> in <FIG>). In particular, by arranging underground section <NUM> at a depth of <NUM>-<NUM> below the ground level <NUM>, a particularly efficient extraction of heat from the cooling water is obtained, and no refrigeration machine or pump is needed.

The loop <NUM>, by recirculating the cooling water, provides a cooling of the solar collector panel <NUM> and thus a reduction in the temperature of the solar photovoltaic cell wafers <NUM>, <NUM> as well as an increase in the photovoltaic effect.

<FIG> shows a possible embodiment of a solar photovoltaic cell wafer <NUM>.

Solar photovoltaic cell wafer <NUM> is based on the use of amorphous silicon, in case passivated by hydrogen (a-Si:H) and comprises a stack formed by a first doped layer <NUM>, having an N-type conductivity; an intermediate, intrinsic layer <NUM>, overlying the first doped layer <NUM>; and a second doped layer <NUM>, having a P-type conductivity, overlying the intermediate, intrinsic layer <NUM>.

For example, the structure of <FIG> may be obtained starting from the structure of <FIG>, by depositing, above the third wafer <NUM>, an aluminum layer <NUM>, the first doped layer <NUM>, the intermediate, intrinsic layer <NUM>, the second doped layer <NUM>, a transparent conductive oxide (TCO) layer <NUM>, and a glass layer <NUM>.

In an embodiment, the first doped layer <NUM> may have a thickness of about <NUM>; the intermediate, intrinsic layer <NUM> may have a thickness of about <NUM>; and the second doped layer <NUM> may have a thickness of about <NUM>.

The TCO layer <NUM> may be, e.g., of indium-tin oxide.

Claim 1:
A method of fabricating a thermoelectric converter, comprising:
forming a plurality of first thermoelectrically active elements (133a; <NUM>; 330a) of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectrically active elements (133b; <NUM>; 330b) of a second thermoelectric semiconductor material having a second Seebeck coefficient in a layer (<NUM>; <NUM>) of silicon-based material, the layer of the silicon-based material having a first surface, a second surface opposite to the first surface, and a first thickness between the first surface and the second surface, the first and second thermoelectrically active elements each being formed to extend through the first thickness, from the first surface to the second surface; and
forming electrically conductive interconnections (<NUM>, <NUM>; <NUM>, <NUM>) over at least one of the first surface or the second surface of the layer of the silicon-based material (<NUM>; <NUM>), the electrically conductive interconnections each electrically interconnecting a first thermoelectrically active element of the plurality of first thermoelectrically active elements and a corresponding one of the plurality of second thermoelectrically active elements; and forming an input electrical terminal and an output electrical terminal electrically coupled to the electrically conductive interconnections,
wherein the first thermoelectric semiconductor material includes porous silicon and the second thermoelectric semiconductor material includes a silicon-based material selected from a group consisting of porous silicon and polycrystalline silicon.