Patent Description:
Integrated Circuit (IC) technology has advanced greatly over the past fifty years. ICs are now pervasive and present in electronic devices, machinery, vehicles, appliances, and many other devices. Large processing ICs now include billions of transistors while memory ICs include hundreds of billions of transistors. The density of transistors on ICs can reach <NUM> million transistors per square millimeter. However, the processing capability of a single IC may not be sufficient to meet required processing needs. Thus, ICs may be bonded together so that the two (or more) ICs are closely coupled and provide greater processing capabilities.

Die to Die (D2D) interconnects between ICs are enabled by interconnecting bond pads ("pads") on sandwiched ICs to create a multi-chip module. Soldering has been used to electrically couple the bond pads of one IC to the bond pads of another IC. However, soldering requires the bond pads to be spaced apart with sufficient pitch so that the solder does not bleed between bond pads to thereby short the bond pads to one another. A newer technique directly bonds the copper bond pads of one IC to the copper bond pads of another IC without using solder. This newer technique supports smaller pitch between adjacent bonds pads than the older technique that uses solder. In either implementation, when adjacent bond pads are shorted due to solder or bond pad faults or open due to defects such as particles or polish induced dishing, data transmitted between the ICs is corrupted.

One prior approach to overcoming the problems caused by bond pad shorts/opens was to use two or more redundant bond pads for at least some data. However, with a doubling of bond pads for redundancy, the Silicon area of the bond pad array increases proportionally with redundancy, resulting in high Silicon area cost, additional energy consumption from high capacitance load, and resultantly an increase in heat generation. A doubling of bond pads and connections is not preferred. <CIT> provides devices and methods for forming dice stacks on an interface die. <CIT> provides a triple orthogonally interleaved error correction system.

The present invention is defined by a multi-chip module in accordance to claim <NUM>. The multi-chip module includes a first Integrated Circuit (IC) die and a second IC die. The first IC die has an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads. The first interleaved interconnections include a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The plurality of first code group circuits is configured to encode data between the first IC die and the second IC die. The second IC die has a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads. The plurality of second code group circuits is configured to decode encoded data by the plurality of first code group circuits.

The multi-chip module provides important benefits and advantages over prior structures/devices. By encoding data for transmission to a differing IC and by interleaving the data after encoding, the first embodiment can correct one or more adjacent bond pad shorts, detect two or more adjacent bond pad shorts, and correct two or more bond pad opens (even if adjacent to one another). The level of correction and detection of bond pad shorts and bond pad opens depends upon the Error Correcting Code (ECC) used by the code group circuits and the interleaving employed. Thus, the first embodiment (and subsequent embodiments) protect data transmitted between IC dies of a multi-chip module with reduced coding and bond pad redundancy.

The present disclosure provides various aspects that may be employed with one or more of the embodiments. These aspects may be combined with one another singly, doubly, or in total. According to a first aspect of the first embodiment, each first code group circuit of the plurality of first code group circuits directly corresponds to a respective second code group circuit. According to a second aspect of the first embodiment, the first interleaved interconnections interleave data of at least two differing first code group circuits and the second interleaved interconnections interleave data of at least two differing corresponding second code group circuits.

The array of first bond pads is organized in rows and columns and the array of second bond pads is organized in rows and columns. With this aspect, for each row of first bond pads, adjacent first bond pads correspond to differing first code group circuits and for each column of first bond pads, adjacent first bond pads correspond to differing first code group circuits.

According to a first embodiment, each of the plurality of first code group circuits is configured to correct a single first bond pad short/open and detect two first bond pad shorts/opens. Further, depending upon the ECC employed and the interleaving pattern, greater numbers of shorts and opens may be detected and corrected.

According to an aspect of the first embodiment, the first interleaved interconnections interleave data of four differing first code group circuits and the second interleaved interconnections interleave data of four differing second code group circuits that correspond to the four differing first code group circuits. With this fifth aspect, for each row of first bond pads, the first interleaved interconnections may establish a four-way interleaving pattern that corresponds to the four differing first code group circuits and for each column of first bond pads, the first interleaved interconnections may establish a four-way interleaving pattern that corresponds to the four differing first code group circuits.

Utilizing interleave adjacent pads from different code group, we will correct adjacent pads failure without increasing the area of the bond pad array.

The the scope of present invention is defined by the appended claims.

<FIG> is a sectional side view illustrating a portion of a multi-chip module having a first Integrated Circuit (IC) <NUM> die and a second IC die <NUM> constructed according to a described embodiment. The first IC die <NUM> includes a plurality of processing systems 111A-111N that intercouple via a communications interface <NUM>. The communications I/F <NUM> may be a NoC (or a portion of a NoC) and may service all or a portion of the inter-IC die communications for the IC die <NUM>. The first IC die <NUM> may include additional inter-IC die communications interfaces than those shown in the embodiment <NUM> of <FIG>.

The second IC die <NUM> includes a plurality of processing systems 124A-124N that intercouple via a communications interface <NUM>. The communications I/F <NUM> may be a NoC and may service all or a portion of the inter-IC die communications for the second IC die <NUM>. The second IC die <NUM> may include additional inter-IC die communications interfaces than are shown in the embodiment <NUM> of <FIG>. The processing circuits 124A-124N may perform functions similar or complementary to the plurality of processing circuits 111A-111N of the first IC die <NUM>.

Each of the first IC die <NUM> and the second IC die <NUM> may be a System on a Chip (SoC) that includes the multiple processing systems, e.g., 111A-111N and 124A-124N, respectively, that perform respective functions and have respective structures, e.g., general processor, communications processor (cellular, WiFi, Bluetooth, etc.), network interface processor, image processor, audio processor, graphics processor, arithmetic unit processor, security processor, safety processor, and human interaction processor, memory controller, and computer bus interface processors, among other processing structures. SoCs are often smaller, less expensive, and consume less power than a device that includes separate processing systems. As is appreciated, the first IC die <NUM> and the second IC die <NUM> may have additional structures as well. The first IC die <NUM> and the second IC die <NUM> may be formed of a semiconductor substrate in a manufacturing process.

The first IC die <NUM> and the second IC die <NUM> include structures that allow them to communicate with one another efficiently and with no/few communication errors. To meet these communication requirements, the first IC die <NUM> also includes an array of first bond pads <NUM>, a plurality of first code group circuits 106A-106N, and first interleaved interconnections <NUM> between the plurality of first code group circuits 106A-106N and the array of first bond pads <NUM>. The first interleaved interconnections <NUM> include a first interleaving pattern causing data from different code group circuits 106A-106N to be coupled to adjacent first bond pads of the array of first bond pads <NUM>. The plurality of first code group circuits 106A-106N intercouple with the plurality of processing circuits 111A-111N via at least one communications I/F <NUM>.

The second IC die <NUM> also includes an array of second bond pads <NUM> that electrically couple to the array of first bond pads <NUM>. The second IC die <NUM> also includes a plurality of second code group circuits 116A-116N and second interleaved interconnections <NUM> between the plurality of second code group circuits 116A-116N and the array of second bond pads <NUM>. The second interleaved interconnections <NUM> include a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads <NUM>. The plurality of second code group circuits 116A-116N intercouple with the plurality of processing circuits 124A-124N via at least one communications I/F <NUM>.

The array of first bond pads <NUM> may be coupled to the array of second bond pads <NUM> via copper bond pad bonding <NUM>, which supports reduced pitch of first bond pads <NUM> and second bond pads <NUM>. Conventional copper bond pad to copper bond pad bonding techniques may be employed to bond the first bond pads <NUM> to the second bond pads <NUM>. In an alternative structure, solder balls may be used to bond the first bond pads <NUM> to the second bond pads <NUM>. Note that a gap is shown between the first IC die <NUM> and the second IC die <NUM> for illustrative purposes to show the bonding therebetween. In some embodiments, the silicon surface of the first IC die <NUM> and the second IC die <NUM> directly abut one another so that that the array of first bond pads <NUM> directly abuts the array of second bond pads <NUM>.

While a single sandwiched structure of the multi-chip module <NUM> is shown in <FIG> that includes two IC dies <NUM> and <NUM>, the principles described herein may be applied to a sandwiched structure having three or more IC dies. For example, one IC die may be sandwiched between two IC dies with intercoupling between adjacent IC dies via respective bond pads that are electrically coupled. Thus, an IC die that is sandwiched between two IC dies would have bond pads on both of its planar surfaces to service communications therebetween. Further, while not shown in <FIG>, the first IC die <NUM> and/or the second IC die may have additional bond pads (not shown) that service the coupling of the multi-chip module to external devices.

With the multi-chip module <NUM> of <FIG>, each first code group circuit of the plurality of first code group circuits 106A-106N directly corresponds to a respective second code group circuit 116A-116N, i.e., first code group circuit 106A corresponds to second code group circuit 116A, first code group circuit 106B corresponds to second code group circuit 116C, and first code group circuit 106C corresponds to second code group circuit 116C, ctc. As will be described further herein with reference to <FIG>, with inter IC die communications serviced according to the present disclosure, data between the first IC die <NUM> and the second IC die <NUM> is, for example, encoded by a first code group circuit 106A of the first IC die <NUM>, and coupled via the first interleaved interconnections <NUM> to respective first bond pads <NUM>. The data is then coupled to the second bond pads <NUM> and coupled by the second interleaved interconnections <NUM> from the second bond pads <NUM> to a second code group circuit 116B of the second IC die <NUM>. The second code group circuit <NUM> of the second IC die <NUM> decodes the encoded data to produce data for transmission to the second IC die <NUM>. With the coding/interleaving/decoding of the present disclosure, at least some bond pad shorts/opens may be overcome. The ability of the first IC die <NUM> and the second IC die <NUM> to detect and correct errors caused by bond pad shorts/opens is based upon the coding redundancy and the interleaving patterns employed.

With one particular example, the first interleaved interconnections <NUM> interleave data of at least two differing first code group circuits and the second interleaved interconnections <NUM> interleave data of at least two differing corresponding second code group circuits. With this example, each of the plurality of first code group circuits 106A-106B and the plurality of second code group circuits 116A-116B may be configured to correct a single adjacent bond pad short, detect two or more adjacent bond pad shorts, and correct two or more bond pad opens using one type of.

Error Correcting Code (ECC). With another particular example, the first interleaved interconnections <NUM> interleave data of four differing first code group circuits, e.g., 104A-104D and the second interleaved interconnections <NUM> interleave data of four differing second code group circuits that correspond to the four differing first code group circuits. Depending upon the coding used, with this example, the first code group circuits 106A-106D and the plurality of second code group circuits 116A-116D are able to correct at least two first bond pad <NUM> shorts/opens and detect at least three first bond pad <NUM> shorts/opens using one type of ECC. Of course, with higher error correcting performance using different ECCs using more redundancy bits, greater numbers of bond pad opens/shorts may be corrected and detected. The tradeoff between lesser and greater ECCs is based upon bond pad number and coding/decoding load.

As will be further illustrated in <FIG> and <FIG>, the array of first bond pads <NUM> is organized in rows and columns and the array of second bond pads <NUM> is organized in rows and columns. With one aspect of this structure, for each row of first bond pads <NUM>, adjacent first bond pads <NUM> correspond to differing first code group circuits 106A-106N and for each column of first bond pads <NUM>, adjacent first bond pads <NUM> correspond to differing first code group circuits 106A-106N. When first interleaved interconnections <NUM> interleave data of four differing first code group circuits 106A-106D, the second interleaved interconnections <NUM> interleave data of four differing second code group circuits 116A-116D that correspond to the four differing first code group circuits 106A-106D. In such case, for each row of first bond pads <NUM>, the first interleaved interconnections <NUM> establish a four-way interleaving pattern that corresponds to the four differing first code group circuits 106A-106D and for each column of first bond pads <NUM>, the first interleaved interconnections <NUM> establish a four-way interleaving pattern that corresponds to the four differing second code group circuits 116A-116D.

<FIG> is a sectional side view illustrating of the multi-chip module of <FIG> with a bond pad short and a bond pad open according to a described embodiment. As compared to the example <NUM> of <FIG>, the example <NUM> of <FIG> includes a bond pad short <NUM> that shorts adjacent first bond pads <NUM> and adjacent second bond pads <NUM>. Further, there is shown a bond pad open in which bond pads <NUM> and <NUM> fail to electrically couple. With the coding/interleaving/decoding structure described with reference to <FIG>, the adjacent bond pad short and/or single bond pad open is overcome to preserve the data link between the first IC die <NUM> and the second IC die <NUM>. <FIG> will described the operations that support this correction procedure. Depending upon the level of interleaving and the ECC used by the first code group circuits 106A-106D and the plurality of second code group circuits 116A-116D, the embodiments of the present disclosure have the capability to correct two or more adjacent bond pad failures and to detect three or more bond pad failures.

<FIG> is a diagrammatic top view of a portion <NUM> of the first IC die of <FIG> according to a first aspect of the embodiment of <FIG>. With the portion <NUM> of <FIG>, a portion <NUM> of the array of first bond pads <NUM> is organized in rows and columns with bond pads <NUM> denoted <NUM>IJ, where I refers to a row and J refers to a column. With the portion <NUM> of <FIG>, an illustrated portion of the first interleaved interconnections <NUM> interleave data of at least two differing first code group circuits, e.g., 106A and 106B. Thus, with the portion <NUM> of <FIG>, for each row of first bond pads <NUM>, adjacent first bond pads <NUM> correspond to differing first code group circuits 106A or 106B and for each column of first bond pads <NUM>, adjacent first bond pads <NUM> correspond to differing first code group circuits 106A or 106B.

With the portion <NUM> of <FIG>, each of the plurality of first code group circuits 106A-106B is configured to correct a single adjacent bond pad short <NUM> or <NUM>, to correct multiple bond pad opens, and detect two adjacent first bond pad <NUM> shorts with one ECC. Bond pad short <NUM> shorts the data of two differing first code group circuits 106A and 106B and bond bad short <NUM> shorts the data of two differing first code group circuits 106A and 106B. Based upon the coding used by the first code group circuits 106A and 106B and 116A and 116B, even though data associated with these two bond pads <NUM><NUM> and <NUM><NUM> (or <NUM><NUM> and <NUM><NUM>) is shorted, the data transmitted between the first IC die <NUM> and the second IC die <NUM> is correct. Using differing ECC, the portion <NUM> of <FIG> may correct more than one adjacent bond pad short, detect more than two adjacent bond pad shorts, and correct at least two bond pad opens.

While the components of the second IC die <NUM> are not shown in <FIG>, the second IC die <NUM> includes components that are complementary to the components of the first IC die <NUM>. The array of second bond pads <NUM> (not shown) is also organized in rows and columns and complements the array <NUM> of first bond pads <NUM>. Further, the example shown in <FIG> may be extended across all of the array of first bond pads <NUM> and the array of second bond pads <NUM> as well as to the other code group circuits.

<FIG> is a diagrammatic top view of a portion <NUM> of the first IC die of <FIG> according to a second aspect of the embodiment of <FIG>. The portion <NUM> of the array of first bond pads <NUM> is organized in rows and columns with bond pads denoted <NUM>IJ, where I refers to a row and J refers to a column. While the components of the second IC die <NUM> are not shown in <FIG>, analogous structure of the second IC die <NUM> complementary to the components of the first IC die <NUM> shown is present.

With the portion <NUM> of <FIG>, the first interleaved interconnections <NUM> interleave data of four differing first code group circuits 106A-106D and the second interleaved interconnections <NUM> interleave data of four differing second code group circuits 116A-116D that correspond to the four differing first code group circuits 106A-106D. In such case, for each row of first bond pads <NUM>, the first interleaved interconnections <NUM> establish a four-way interleaving pattern that corresponds to the four differing first code group circuits 106A-106D and for each column of first bond pads <NUM>, the first interleaved interconnections <NUM> establish a four-way interleaving pattern that corresponds to the four differing first code group circuits 106A-106D. The portion <NUM> of <FIG> is able to correct at least two adjacent first bond pad <NUM>, e.g., short <NUM> between first bond pads <NUM><NUM> and <NUM><NUM> and short <NUM> between first bond pad <NUM><NUM> and <NUM><NUM> using a first ECC. Likewise, the portion <NUM> of <FIG> is able to correct at least two adjacent first bond pad <NUM> shorts in a column, e.g., short <NUM> between first bond pads <NUM><NUM> and <NUM><NUM> and short <NUM> between first bond pad <NUM><NUM> and <NUM><NUM> using a first ECC. The portion <NUM> is also able to detect more than two adjacent first bond pad <NUM> shorts and indicate this to controlling circuitry of the first IC die <NUM> using a first ECC. The use of a differing, more robust, ECC enables for the correction of more than two adjacent bond pad shorts/opens and the detection of more than three adjacent bond pad shorts. Detection and correction of bond pad opens is serviced in similar fashion.

<FIG> is a block diagram illustrating a code group circuit constructed according to an embodiment of the present disclosure. The code group circuit <NUM> may be one of the first code group circuits 106A-106N formed in the first IC die <NUM> or one the second code group circuits 116A-116N formed in the second IC die <NUM> of <FIG>. Assuming that the code group circuit <NUM> is formed in the first IC die <NUM>, the first code group circuit <NUM> includes an IC data interface <NUM> that receives data (M bits) for transmission from the first IC die <NUM> to the second IC die <NUM>. Output data buffer <NUM> buffers the data, data coder <NUM> encodes the data according to a programmed ECC technique, and encoded data buffer <NUM> buffers the encoded data. Interconnect I/F <NUM> interfaces with interleaved interconnections, which couple the coded data to corresponding bond pads. Note that the interconnect I/F <NUM> services a single bi-directional data path. In different embodiments, there are separate transmit and receive data paths.

For data received from a differing IC die, the interconnect I/F <NUM> receives coded data from a differing IC die via bond pads and interleaved interconnections coupled thereto. Coded data buffer <NUM> buffers the coded data, coded data decoder <NUM> decodes the coded data to produce decoded data and the decoded data buffer <NUM> buffers the decoded data. The IC decoded data I/F <NUM> provides the decoded data internally to the IC die for further use. Note that the data and the decoded data have a width of M bits while the encoded data has a width of N bits, where N is greater than M by a coding factor. Various coding techniques may be used to perform the encoding/decoding functions, e.g., Hamming codes and other simple block codes. A tradeoff exists between the complexity of the coding technique used and the ability of the coding technique to detect/correct errors caused by bond pad shorts/opens.

<FIG> is a flow chart illustrating operations of a multi-chip module according to an embodiment of the present disclosure. The operations <NUM> of <FIG> begin with a first IC die producing data for transmission to the second IC die (step <NUM>). Operations <NUM> continue with the first IC die encoding the data to produce encoded data in a plurality of code groups (step <NUM>). Next, operations <NUM> continue with the first IC die distributing the encoded data to an array of first bond pads via first interleaved interconnections having a first interleaving pattern that causes the encoded data to be coupled to the array of first bond pads so that bits of each code group couple to non-adjacent first bond pads (step <NUM>).

Next, operations <NUM> include the second IC die receiving the encoded data via an array of second bond pads that electrically couple to the array of first bond pads and via second interleaved interconnections having a second interleaving pattern corresponding to the first interleaving pattern (step <NUM>). Operations <NUM> conclude with the second IC die decoding the encoded data to produce decoded data (step <NUM>).

The operations <NUM> of <FIG> may be employed with particular structure. With According to a first aspect of the embodiment of <FIG>, encoding the data to produce encoded data includes uses a plurality of first code group circuits of the first IC die and decoding the encoded data to produce the decoded data uses a plurality of second code group circuits of the second IC die that directly correspond to the plurality of first code group circuits. With this aspect, the first interconnections interleave data of at least two differing first code group circuits and the second interconnections interleave data of at least two differing corresponding second code group circuits.

According to a first aspect of this structure, the array of first bond pads may be organized in rows and columns and the array of second bond pads is organized in rows and columns. With a first aspect of this structure, for each row of first bond pads, adjacent first bond pads correspond to differing first code group circuits of a plurality of first code group circuits and for each column of first bond pads, adjacent first bond pads correspond to differing first code group circuits of a plurality of first code group circuits. With this aspect, the plurality of first code group circuits are each configured to correct a single first bond pad short/open and detect two first bond pad shorts/opens.

According to a second aspect of this structure, the first interleaved interconnections interleave data of four differing first code group circuits of a plurality of first code group circuits and the second interleaved interconnections interleave data of four differing second code group circuits of a plurality of second code group circuits that respectively correspond to the four differing first code group circuits. With this second aspect of this structure, for each row of first bond pads, a four-way interleaving pattern is established that corresponds to the four differing first code group circuits and for each column of first bond pads, a four-way interleaving pattern is established that corresponds to the four differing first code group circuits. In such case the plurality of first code group circuits are configured to correct at least two first bond pad shorts, and to detect at least three first bond pad shorts, and to correct at least three bond pad opens.

<FIG> is a flow chart illustrating operations of a first IC die communicating with an external device according to an embodiment of the present disclosure. The external device may be a second IC die of a multi-chip module, a differing IC die, or another device that is communication with the first IC die. The operations <NUM> of <FIG> begin with a first IC die producing data for transmission to the external device (step <NUM>). Operations <NUM> continue with the first IC die encoding the data to produce encoded data in a plurality of code groups (step <NUM>). Next, operations <NUM> continue with the first IC die distributing the encoded data to an array of first bond pads via first interleaved interconnections having a first interleaving pattern that causes the encoded data to be coupled to the array of first bond pads so that bits of each code group couple to non-adjacent first bond pads (step <NUM>).

Next, operations <NUM> include the first IC die receiving second encoded data from the external device via the array of first bond pads and via the first interleaved interconnections having the first interleaving pattern (step <NUM>). Operations <NUM> conclude with the first IC die decoding the second encoded data to produce second decoded data (step <NUM>). The operations <NUM> of <FIG> include various aspects that are same/similar to the aspects described with reference to <FIG>.

<FIG> is a flow chart illustrating operations of a first IC die of a multi-chip module according to an embodiment of the present disclosure. The operations <NUM> of <FIG> are consistent with the operations of <FIG> and <FIG> and the structure of <FIG>. Operations <NUM> begin with the first code group circuit of the first IC die receiving data to be transmitted to a second IC die (step <NUM>). The first code group circuit then buffers the data (step <NUM>). The first code group circuit then encodes the data to produce coded data (step <NUM>). Next, the first code group circuit buffers the encoded data (step <NUM>). Finally, the first code group circuit transmits the encoded data to a second IC die via first interleaved interconnections and an array of first bond pads (step <NUM>).

<FIG> is a flow chart illustrating operations of a second IC die of a multi-chip module according to an embodiment of the present disclosure. The operations <NUM> of <FIG> are complementary to the operations <NUM> of <FIG> but from the perspective of a second IC die that is receiving data from the first IC die. Operations <NUM> commence with a second code group circuit of a second IC die receiving encoded data from a first IC die via an array of second bond pads and second interleaved interconnections (step <NUM>). Operations <NUM> continue with the second code group circuit of the second IC die buffering the encoded data (step <NUM>) and the second code group circuit decoding the encoded data to produce decoded data (<NUM>). The second code group circuit then buffers the decoded data (step <NUM>) and then forwards the decoded data for use by the second IC die (step <NUM>).

Utilizing interleave adjacent pads from different code group, we will correct adjacent pads failure without increasing the area of the bond pad array.

Claim 1:
A multi-chip module comprising:
a first Integrated Circuit, IC, die (<NUM>) having:
an array of first bond pads (<NUM>);
a plurality of first code group circuits (106A, 106B...106N); and
first interleaved interconnections (<NUM>) between the plurality of first code group circuits (106A, 106B... 106N) and the array of first bond pads (<NUM>), the first interleaved interconnections (<NUM>) including a first interleaving pattern causing data from different code group circuits (106A, 106B... 106N) to be coupled to adjacent first bond pads (<NUM>), wherein each of the plurality of first code group circuits (106A, 106B...106N) is configured to encode data between the first IC die (<NUM>) and a second IC die (<NUM>) via interleaved interconnections of the first interleaved interconnections,
wherein the array of first bound pads (<NUM>) is organized in rows and columns, for each row of first bond pads (<NUM>), adjacent first bond pads (<NUM>) correspond to differing first code group circuits (106A-106N) and for each column of first bond pads (<NUM>), adjacent first bond pads (<NUM>) correspond to differing first code group circuits (106A-106N); and
the second IC die (<NUM>) having:
a second array of bond pads (<NUM>) that electrically couple to the array of first bond pads (<NUM>), wherein the array of second bond pads (<NUM>) is organized in rows and columns and is arranged to complement the array (<NUM>) of first bond pads (<NUM>);
a plurality of second code group circuits (116A, 116B...116N); and
second interleaved interconnections (<NUM>) between the plurality of second code group circuits (116A, 116B...116N) and the array of second bond pads (<NUM>), the second interleaved interconnections (<NUM>) including a second interleaving pattern causing data from different code group circuits to be coupled to adjacent second bond pads (<NUM>), wherein the plurality of second code group circuits (116A, 116B...116N) is configured to decode encoded data from the first Integrated Circuit (IC) die (<NUM>).