Patent Description:
Semiconductive device miniaturization during die-tiling packaging includes challenges to manage bump-thickness variations during assembly. Document <CIT> describes a printed circuit board and an electronic component module.

Disclosed embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings where like reference numerals may refer to similar elements, in which:.

Silicon bridge embedded patches are surrounded by a glass substrate, in a useful depth, whether the depth is a through-hole in the glass or it is a recess. The glass substrates provide warpage mitigation. Fabrication includes placing a silicon bridge and a glass substrate that has a useful depth on a dimensionally stable glass carrier with a temporary release layer followed by a redistribution layer (RDL) build-up that includes a photo imageable solder resist near die level. At least two dice are coupled to the silicon bridge using thermal compression bonding techniques, after which the glass carrier is removed. In an embodiment, the glass is a soda lime glass (SLG). In an embodiment, the glass is a silicon dioxide glass. In an embodiment, the glass is an aluminosilicate material. In an embodiment, the glass an aluminosilicate material with an additive of potassium and magnesium and sodium. The glass material for the substrate and carrier can be chosen appropriately to minimize warpage during RDL processing and during assembly. Other inorganic materials may be used that exhibit glass-like responses to thermal loads.

Modular die embodiments, also known as die-disaggregation and die partitioning, is done to as it enables heterogeneous die integration, miniaturization of form factor and high performance with useful yield.

<FIG> is a cross-section elevation of a modular semiconductive device <NUM> according to an embodiment. A "modular semiconductive device" may also be referred to as a disaggregated-die semiconductive device, or an embedded multi-die interconnect bridge (EMIB) disaggregated-die semiconductive device, or an EMIB modular-die system in package (EMIB SiP). Other designations may be useful.

A glass substrate <NUM> has an embedded multi-die interconnect bridge (EMIB) <NUM> in a through-hole <NUM> (see <FIG>) portion of the substrate <NUM>. The EMIB <NUM> is embedded in a patterned dielectric film <NUM>. Several through-glass vias (TGVs) <NUM> similarly penetrate the glass substrate <NUM> from a die side <NUM> to a land side <NUM>.

The EMIB <NUM> is at least partially embedded in the glass substrate <NUM>. This means the Z-height of the EMIB <NUM> may extend above the Z-height of the glass substrate <NUM>.

<FIG> is a cross-section elevation of the semiconductor device package <NUM> depicted in <FIG> during assembly according to an embodiment. An inorganic substrate <NUM> such as a semiconductor-packaging quality glass substrate <NUM> is patterned with contact corridors <NUM> in preparation for filling with metallic vias (see <FIG>). The glass substrate <NUM> has a die side <NUM> and a land side <NUM>, in reference to die and semiconductor package substrate locations depicted in <FIG> and during future assembly.

In an embodiment, the inorganic substrate <NUM> is a ceramic that has been fired and machined to allow the contact corridors <NUM> to have useful fiduciary quality for locating metallic vias. Hereinafter, the substrate <NUM> is referred to as a glass substrate <NUM>, but it may be a useful inorganic non-glass such as the ceramic-substrate embodiments.

<FIG> is a cross-section elevation <NUM> of the glass substrate <NUM> depicted in <FIG> after further processing according to an embodiment. A seed layer <NUM> is plated onto the glass substrate <NUM>, followed by an electroplating technique to fill the contact corridors <NUM> (see <FIG>) with a through-glass via (TGV) <NUM> according to an embodiment. In an embodiment, an electroless plating technique is done to locate the seed layer <NUM> such as a copper film <NUM> onto the respective die and land sides <NUM> and <NUM> of the glass substrate <NUM>, as well as into the contact corridors <NUM>. In an embodiment, sputtering technique is done to locate the seed layer <NUM> which is bi-layer of Titanium and Copper. In an embodiment, electroplating the TGV <NUM> uses a copper-electroplating technique.

<FIG> is a cross-section elevation <NUM> of the glass substrate <NUM> depicted in <FIG> after further processing according to an embodiment. A backgrinding process has removed the seed layer <NUM> and extra electrolytic plated copper from the respective die and land sides <NUM> and <NUM> of the glass substrate <NUM>, as well as the backgrinding process has formed the TGVs <NUM>.

In an embodiment after forming of the TGVs <NUM> as illustrated, a through-hole <NUM> is formed from the die side <NUM> to the land side <NUM>, in preparation for seating a silicon-bridge interconnect within the through-hole <NUM>. A "silicon-bridge interconnect" may be of a semiconductive material such as undoped silicon, or a III-V material. In an embodiment, a doped silicon material is used. After encasing the silicon bridge interconnect in a dielectric material, it is referred to as an EMIB.

<FIG> is a cross-section elevation <NUM> of the glass substrate <NUM> depicted in <FIG> after further processing according to an embodiment. The glass substrate <NUM> has been seated upon a carrier <NUM> such as a temporary glass carrier <NUM> with an adhesive <NUM> that secures the glass substrate <NUM> to a useful flatness for further processing.

<FIG> is a cross-section elevation of a semiconductor device package <NUM> after further processing of the glass substrate <NUM> depicted in <FIG> according to an embodiment. The semiconductor device package <NUM> has been processed by height-reducing (negative-Z direction) the glass substrate <NUM> such that the die side <NUM> is lowered, closer to the land side <NUM>. The height reduction is done when a specific silicon bridge of a given useful Z-height, is less than the Z-height of the glass substrate <NUM>. In an embodiment, no height reduction of the glass substrate <NUM> is done as a specific silicon bridge sufficiently matches the Z-height of the glass substrate <NUM>, within useful processing and assembly parameters.

Further assembly includes seating a silicon bridge <NUM> in the through-hole <NUM>. In an embodiment, a bridge adhesive <NUM> is located on the backside of the silicon bridge <NUM>, to facilitate locating the bridge die <NUM>. The bridge adhesive <NUM> may also be referred to as a die-attach film (DAF).

In an embodiment, the silicon bridge die <NUM> has several layers of metallization including Z-direction via portions if necessary, and longitudinal (X- and Y-direction) trace portions. Several bridge traces, e.g. <NUM>, <NUM> and <NUM>, among others, are depicted, among other bridge traces when useful. In an embodiment, the bridge die <NUM> is bumped to contact the metallization layers, such as with an electrical bump, one occurrence of which is depicted with reference number <NUM>.

In an embodiment, where the Z-height of the glass substrate <NUM> is unity, the Z-height of the silicon bridge <NUM> is in a range from <NUM> percent of unity, to <NUM> percent of unity. The Z-height ratio is controlled in part by selecting of bump size <NUM>.

<FIG> is a cross-section elevation of the semiconductor device package <NUM> depicted in <FIG> after further processing according to an embodiment. The semiconductor device package <NUM> has been processed by encapsulating the die side <NUM> with an EMIB-level dielectric film <NUM> upon the die side <NUM>. The EMIB-level dielectric film <NUM> fills into the through-hole <NUM> (see <FIG>) to embed the bridge die <NUM> such that it is useful as an embedded multi-die interconnect bridge (EMIB) die <NUM>.

In an embodiment, the Z-height of the bridge die <NUM> is taller than the Z-height of the glass substrate <NUM>, to make the bridge die <NUM> at least partially embedded. In an embodiment, the Z-height of the bridge die <NUM> is equal to the Z-height of the glass substrate <NUM> within processing parameters, to make the bridge die <NUM> at least partially embedded. In an embodiment, the Z-height of the bridge die <NUM> is less than the Z-height of the glass substrate <NUM>, to make the bridge die <NUM> at least partially embedded. In an embodiment, the Z-height of the bridge die <NUM> is about <NUM> percent the Z-height of the glass substrate <NUM>.

After seating and encapsulating the EMIB die <NUM>, processing is followed by patterning the EMIB-level dielectric film <NUM> to open middle contact corridors, one occurrence of which is indicated with reference number <NUM>. The middle contact corridors open to the TGVs <NUM>, which may be referred to as land-side filled vias <NUM>. Patterning the EMIB-level dielectric film <NUM> is also done above the electrical bumps <NUM> to open bridge-bump contact corridors, one occurrence of which is indicated with reference number <NUM>, which exhibit a smaller scale than the middle contact corridors <NUM> for exposing the TGVs <NUM>. In an embodiment, laser drilling techniques are used for each of the contact corridors <NUM> and <NUM>, depending upon contact-corridor aspect ratios of area and depth. In an embodiment, laser drilling is used to open the bridge-bump contact corridors <NUM>, and photolithography is used to open the middle contact corridors <NUM>.

<FIG> is a cross-section elevation of the semiconductor device package <NUM> depicted in <FIG> after further processing according to an embodiment. The semiconductor device package <NUM> has been processed by filling and patterning into the EMIB-level dielectric film <NUM>, second-level filled vias <NUM> and second-level EMIB vias <NUM>. The second-level package vias <NUM> and <NUM> are distinguished as being next to the TGVs <NUM>. Thereafter in an embodiment, the second-level vias <NUM> and the second-level EMIB vias <NUM> are added to, by patterning a die-level interlayer dielectric (ILD) <NUM>, and filling and patterning into the die-level ILD <NUM>, die-level filled vias <NUM> and die-level EMIB vias <NUM>. In an embodiment, a solder film <NUM> and <NUM> is applied to the respective die-level filled vias <NUM> and die-level EMIB vias <NUM>.

In an embodiment, patterning of the ILD <NUM>, involves using a photo-imageable dielectric (PID) <NUM>, patterning using light exposure, and removing material to leave contact corridors. As a result, the PID <NUM> may be referred to as a photoresist. In an embodiment, patterning of the ILD <NUM>, involves laser drilling contact corridors for the vias <NUM>, and photo imaging contact corridors for the vias <NUM>.

Reference is again made to <FIG>. After forming the die-level vias <NUM> and <NUM>, as well as the solder films <NUM> and <NUM>, a first semiconductive device <NUM> is bonded to the vias. In an embodiment, the first semiconductive device <NUM> includes an active surface and metallization <NUM>, coupled to substrate bond pads <NUM> for coupling to TGVs <NUM>, and EMIB bond pads <NUM> for coupling to the bridge traces, e.g. to the bridge trace <NUM> in the EMIB <NUM>.

In an embodiment to make a modular die <NUM>, a plurality of first-semiconductive-device chiplets are assembled to the first die <NUM>. For example, a first, first-die chiplet <NUM>, a subsequent, first-die chiplet <NUM> and a third, first-die chiplet <NUM> are coupled to the first die <NUM>. In an exemplary embodiment, the first, first-die chiplet <NUM> is coupled to EMIB <NUM> through the first die <NUM> by a through-silicon via (TSV) <NUM> that contacts the active surface and metallization <NUM> through the first die <NUM>, and emerges at a first-die backside surface <NUM>. In an embodiment, the chiplets are fabricated at a smaller design-rule geometry than that of the first and subsequent semiconductive devices. For example, the chiplet <NUM> is fabricated at a <NUM> nanometer (nm) design-rule geometry, and the first semiconductive device <NUM> is fabricated at a <NUM> design-rule geometry. The EMIB die <NUM> has routing lines capable of connecting backsides of the coarser devices <NUM> and <NUM>, while the coarser devices <NUM> and <NUM>, and the chiplets <NUM>, <NUM>, <NUM><NUM>, <NUM> and <NUM> are coupled face-to-face with the active surfaces contact across electrical bumps.

In an embodiment, a subsequent semiconductive device <NUM> is bonded to die-level vias <NUM> and <NUM>. In an embodiment, the subsequent semiconductive device <NUM> includes an active surface and metallization <NUM>, substrate bond pads <NUM> for coupling to TGVs <NUM>, and EMIB bond pads <NUM> for coupling to the bridge traces, e.g. to the bridge trace <NUM> in the EMIB <NUM>.

In an embodiment to further extend capabilities of the modular die <NUM>, a plurality of subsequent-semiconductive-device chiplets are assembled to the subsequent die <NUM>. For example, a first, subsequent-die chiplet <NUM>, a subsequent, subsequent-die chiplet <NUM> and a third, subsequent-die chiplet <NUM> are coupled to the subsequent die <NUM>. In an exemplary embodiment, the first, subsequent-die chiplet <NUM> is coupled to EMIB <NUM> through the subsequent die <NUM> by a TSV via <NUM> that contacts the active surface and metallization <NUM> through the subsequent die <NUM>, and emerges at a subsequent-die backside surface <NUM>.

After assembly of the several chiplets, and other useful structures to the die backside surfaces <NUM> and <NUM>, an encapsulation mass <NUM> covers the several first and subsequent dice as well as at least a portion of the first and subsequent-die chiplets <NUM>, <NUM> and <NUM>, and <NUM>, <NUM> and <NUM>, respectively.

<FIG> is a cross-section elevation of the modular die <NUM> depicted in <FIG> after further processing according to several embodiments. A semiconductor device package <NUM> is being assembled as the modular die <NUM> is being seated onto a semiconductor package substrate <NUM>, as indicated by the directional arrows.

In an embodiment, the semiconductor device package <NUM> is further assembled to a computing system, as a board <NUM> is being assembled to the semiconductor package substrate <NUM> as indicated by the directional arrows. In an embodiment, the board <NUM> is such as printed wiring board <NUM>. In an embodiment, the printed wiring board <NUM> includes an external shell <NUM> that acts as an external boundary of a computing system that houses the modular die <NUM>, where in an embodiment, the external shell <NUM> is the outside of a tablet computer or a wireless telephone.

After assembly, the modular die <NUM> is characterized at the bond pads <NUM>, <NUM> and <NUM> and <NUM> as first-level interconnects (FLIs), that also includes the solder films <NUM> and <NUM>. Further, electrical bumps <NUM> on the semiconductor package substrate <NUM> that face the land side <NUM>, are characterized as mid-level interconnects (MLIs). Further, electrical bumps <NUM> on the semiconductor package substrate <NUM> that face the board <NUM>, are characterized as substrate-level interconnects (SLIs).

<FIG> is a cross-section elevation of a modular semiconductive device <NUM> according to an embodiment.

A glass substrate <NUM> has an embedded multi-die interconnect bridge (EMIB) <NUM> in a recess <NUM> (see <FIG>) portion of the glass substrate <NUM>. The EMIB <NUM> is embedded in a patterned dielectric film <NUM>. Several through-glass vias (TGVs) <NUM> similarly penetrate the glass substrate <NUM> from a die side <NUM> to a land side <NUM>.

<FIG> is a cross-section elevation of the modular die package <NUM> depicted in <FIG> during assembly according to an embodiment. An inorganic substrate <NUM> such as a semiconductor-packaging quality glass substrate <NUM> is patterned with contact corridors <NUM> in preparation for filling with metallic vias (see <FIG>). The glass substrate <NUM> has a die side <NUM> and a land side <NUM>, in reference to die and semiconductor package substrate locations depicted in <FIG> and during future assembly.

<FIG> is a cross-section elevation <NUM> of the glass substrate <NUM> depicted in <FIG> after further processing according to an embodiment. A seed layer <NUM> is plated onto the glass substrate <NUM>, followed by an electroplating technique to fill the contact corridors <NUM> (see <FIG>) with a through-glass via (TGV) <NUM> according to an embodiment. In an embodiment, an electroless plating technique is done to locate the seed layer <NUM> as a copper film <NUM> onto the respective die and land sides <NUM> and <NUM> of the glass substrate <NUM>, as well as into the contact corridors <NUM>. In an embodiment, sputtering technique is done to locate the seed layer <NUM> is a which is bi-layer of Titanium and Copper. In an embodiment, electroplating the TGV <NUM> uses a copper-electroplating technique.

In an embodiment after forming of the TGVs <NUM> as illustrated, a recess <NUM> is formed from the die side <NUM> but not reaching the land side <NUM>, in preparation for seating a silicon-bridge interconnect within the recess <NUM>. A "silicon-bridge interconnect" may be of a semiconductive material such as undoped silicon, or a III-V material. In an embodiment, a doped silicon material is used. After encasing the silicon bridge interconnect in a dielectric material, it is referred to as an EMIB.

<FIG> is a cross-section elevation of a semiconductor device package <NUM> after further processing of the glass substrate <NUM> depicted in <FIG> according to an embodiment. The semiconductor device package is enhanced by seating a silicon bridge <NUM> in the recess <NUM>. In an embodiment, a bridge adhesive <NUM> is located on the backside of the silicon bridge <NUM>, to facilitate locating the bridge die <NUM>. The bridge adhesive <NUM> may also be referred to as a die-attach film (DAF) <NUM>.

In an embodiment, the silicon bridge die <NUM> has several layers of metallization including Z-direction via portions if necessary, and longitudinal (X- and Y-direction) trace portions. Several bridge traces, e.g. <NUM>, <NUM> and <NUM> are depicted, among other bridge traces when useful. In an embodiment, the bridge die <NUM> is bumped to contact the metallization layers, such as with an electrical bump, one occurrence of which is depicted with reference number <NUM>.

<FIG> is a cross-section elevation of the semiconductor device package <NUM> depicted in <FIG> after further processing according to an embodiment. The semiconductor device package <NUM> has been processed by encapsulating the die side <NUM> with an EMIB-level dielectric film <NUM> upon the die side <NUM>. The EMIB-level dielectric film <NUM> fills into the recess <NUM> (see also <FIG>) to embed the bridge die <NUM> such that it is useful as an embedded multi-die interconnect bridge (EMIB) die <NUM>.

After seating and encapsulating the EMIB die <NUM>, processing is followed by patterning the EMIB-level dielectric film <NUM> to open middle contact corridors, one occurrence of which is indicated with reference number <NUM>. The middle contact corridors open to the TGVs <NUM>, which may be referred to as land-side filled vias <NUM>. Patterning the EMIB-level dielectric film <NUM> is also done above the electrical bumps <NUM> to open bridge-bump contact corridors, one occurrence of which is indicated with reference number <NUM>, which exhibit a smaller scale than the middle contact corridors <NUM> for exposing the TGVs <NUM>. In an embodiment, laser drilling techniques are used for each of the contact corridors <NUM> and <NUM>, depending upon contact-corridor aspect ratios of area and depth. In an embodiment, laser drilling is used to open the bridge contact corridors <NUM>, and photolithography is used to open substrate contact corridors <NUM>.

<FIG> is a cross-section elevation of the semiconductor device package <NUM> depicted in <FIG> after further processing according to an embodiment. The semiconductor device package <NUM> has been processed by filling and patterning into the EMIB-level dielectric film <NUM>, second-level filled vias <NUM> and second-level EMIB vias <NUM>. The second-level vias <NUM> and <NUM> are distinguished as being next to the TGVs <NUM>. In an embodiment, the chiplets are fabricated at a smaller design-rule geometry than that of the first and subsequent semiconductive devices. For example, the chiplet <NUM> is fabricated at a <NUM> nanometer (nm) design-rule geometry, and the first semiconductive device <NUM> is fabricated at a <NUM> design-rule geometry. The EMIB die <NUM> has routing lines capable of connecting backsides of the coarser devices <NUM> and <NUM>, while the coarser devices <NUM> and <NUM>, and the chiplets <NUM>, <NUM>, <NUM><NUM>, <NUM> and <NUM> are coupled face-to-face with the active surfaces contact across electrical bumps. Thereafter in an embodiment, the second-level vias <NUM> and the second-level EMIB vias <NUM> are added to, by patterning a die-level interlayer dielectric (ILD) <NUM>, and filling and patterning into the die-level ILD <NUM>, die-level filled vias <NUM> and die-level EMIB vias <NUM>. In an embodiment, a solder film <NUM> and <NUM> is applied to the respective die-level filled vias <NUM> and die-level EMIB vias <NUM>.

Reference is again made to <FIG>. After forming the die-level vias <NUM> and <NUM>, as well as the solder films <NUM> and <NUM>, a first semiconductive device <NUM> is bonded to the vias. In an embodiment, the first semiconductive device <NUM> includes an active surface and metallization <NUM>, substrate bond pads <NUM> for coupling to TGVs <NUM>, and EMIB bond pads <NUM> for coupling to the bridge traces, e.g. to the bridge trace <NUM> in the EMIB <NUM>.

In an embodiment to make a modular die <NUM>, a plurality of first-semiconductive-device chiplets are assembled to the first die <NUM>. For example, a first, first-die chiplet <NUM>, a subsequent, first-die chiplet <NUM> and a third, first-die chiplet <NUM> are coupled to the first die <NUM>. In an exemplary embodiment, the first, first-die chiplet <NUM> is coupled to EMIB <NUM> through the first die <NUM> by a through-silicon via (TSV) <NUM> that contacts the active surface and metallization <NUM>, and emerges at a first-die backside surface <NUM>.

In an embodiment to further extend capabilities of the modular die <NUM>, a plurality of subsequent-semiconductive-device chiplets are assembled to the subsequent die <NUM>. For example, a first, subsequent-die chiplet <NUM>, a subsequent, subsequent-die chiplet <NUM> and a third, subsequent-die chiplet <NUM> are coupled to the subsequent die <NUM>. In an exemplary embodiment, the first, subsequent-die chiplet <NUM> is coupled to EMIB <NUM> through the subsequent die <NUM> by a TSV <NUM> that contacts the active surface and metallization <NUM> through the subsequent die <NUM>, and emerges at a subsequent-die backside surface <NUM>.

In an embodiment, the semiconductor device package <NUM> is further assembled to a computing system, such as a board <NUM> is being assembled to the semiconductor package substrate <NUM> as indicated by the directional arrows. In an embodiment, the board <NUM> is a printed wiring board <NUM>. In an embodiment, the printed wiring board <NUM> includes an external shell <NUM> that acts as an external boundary of a computing system that houses the modular die <NUM>, where in an embodiment, the external shell <NUM> is the outside of a tablet computer or a wireless telephone.

<FIG> is a top plan <NUM> of the modular die <NUM> depicted in <FIG> according to an embodiment. The modular die <NUM> depicted in <FIG> is seen at the cross-section line <NUM> - - <NUM>. The first semiconductive device <NUM> is seen in hidden lines as it is hidden in the encapsulation mass <NUM>, as well as is the subsequent semiconductive device <NUM>. The first-die chiplets <NUM>, <NUM> and <NUM> are seen above the first die <NUM>, and each chiplet emerges from the encapsulation mass <NUM> to expose backsides according to an embodiment. Similarly, the subsequent-die chiplets <NUM>, <NUM> and <NUM> are seen above the subsequent die <NUM>, and each chiplet emerges from the encapsulation mass <NUM> to expose backsides according to an embodiment.

In an embodiment, a <NUM> X <NUM> array of chiplet spaces is configured on the backside surface of the first die <NUM>, but four of the spaces are taken up by heat slugs <NUM> to facilitate heat removal from the first die <NUM> and into a heat sink such as an integrated heat spreader that contacts the heat slugs. Similarly in an embodiment, a <NUM> X <NUM> array of chiplet spaces is configured on the backside surface of the subsequent die <NUM>, but four of the spaces are taken up by heat slugs <NUM> to facilitate heat removal from the subsequent die <NUM> and into the same heat sink that contacts the heat slugs <NUM> according to an embodiment.

As illustrated, different useful patterns for heat slugs <NUM> and <NUM> are applied above the respective first and subsequent dice <NUM> and <NUM>, depending upon heat-extraction usefulness.

<FIG> is a cross-section elevation of a semiconductor device package <NUM> during processing of a glass substrate <NUM> according to an embodiment. The semiconductor device package <NUM> has different silicon-bridge-accommodating capabilities, where a through hole <NUM> accepts a silicon bridge <NUM> that is taller (Z-direction) compared to a recess <NUM>' that is accepting a silicon bridge <NUM>'. In the illustrated embodiment, at least two different-height silicon bridges <NUM> and <NUM>' are configured to service at least three semiconductive devices that couple to the two silicon bridges <NUM> and <NUM>'.

<FIG> is a process flow diagram according to several embodiments.

At <NUM>, the process includes filling a plated through-hole in a glass substrate. In a non-limiting example embodiment, a via <NUM> is plated into a through-hole <NUM> in the glass substrate <NUM>.

At <NUM>, the process includes seating a bridge die in a through-hole in the glass substrate. In a non-limiting example embodiment, the bridge die <NUM> is seated in the through-hole <NUM> in the glass substrate <NUM>.

At <NUM>, the process includes seating a bridge die in a recess in the glass substrate. In a non-limiting example embodiment, the bridge die <NUM> is seated in the recess <NUM> in the glass substrate <NUM>.

At <NUM>, the process includes connecting a first die and a subsequent die to the bridge die, above the glass substrate. In a non-limiting example embodiment, a first die <NUM> and a subsequent die <NUM> are connected to the bridge die <NUM> above the glass substrate <NUM>.

At <NUM>, the process includes seating at least one chiplet on one of the first die and the subsequent die. In a non-limiting example embodiment, a first-die first chiplet <NUM> is seated on the first die <NUM>.

At <NUM>, the process includes assembling the bridge-die-containing glass substrate to a computing system.

<FIG> is included to show an example of a higher-level device application for the disclosed embodiments. The bridge die in glass substrate bridge die in glass substrate embodiments may be found in several parts of a computing system. In an embodiment, the bridge die in glass substrate is part of a communications apparatus such as is affixed to a cellular communications tower. In an embodiment, a computing system <NUM> includes, but is not limited to, a desktop computer. In an embodiment, a system <NUM> includes, but is not limited to a laptop computer. In an embodiment, a system <NUM> includes, but is not limited to a netbook. In an embodiment, a system <NUM> includes, but is not limited to a tablet. In an embodiment, a system <NUM> includes, but is not limited to a notebook computer. In an embodiment, a system <NUM> includes, but is not limited to a personal digital assistant (PDA). In an embodiment, a system <NUM> includes, but is not limited to a server. In an embodiment, a system <NUM> includes, but is not limited to a workstation. In an embodiment, a system <NUM> includes, but is not limited to a cellular telephone. In an embodiment, a system <NUM> includes, but is not limited to a mobile computing device. In an embodiment, a system <NUM> includes, but is not limited to a smart phone. In an embodiment, a system <NUM> includes, but is not limited to an internet appliance. Other types of computing devices may be configured with the microelectronic device that includes bridge die in glass substrate embodiments.

In an embodiment, the processor <NUM> has one or more processing cores <NUM> and 612N, where 612N represents the Nth processor core inside processor <NUM> where N is a positive integer. In an embodiment, the electronic device system <NUM> using an embedded magnetic inductor and EMIB die embodiment that includes multiple processors including <NUM> and <NUM>, where the processor <NUM> has logic similar or identical to the logic of the processor <NUM>. In an embodiment, the processing core <NUM> includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In an embodiment, the processor <NUM> has a cache memory <NUM> to cache at least one of instructions and data for the embedded magnetic inductor and EMIB die in the system <NUM>. The cache memory <NUM> may be organized into a hierarchal structure including one or more levels of cache memory.

In an embodiment, the processor <NUM> includes a memory controller <NUM>, which is operable to perform functions that enable the processor <NUM> to access and communicate with memory <NUM> that includes at least one of a volatile memory <NUM> and a non-volatile memory <NUM>. In an embodiment, the processor <NUM> is coupled with memory <NUM> and chipset <NUM>. In an embodiment, the chipset <NUM> is part of a system-in-package with a bridge die in glass substrate depicted in <FIG>, <FIG>, <FIG>. The processor <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to at least one of transmit and receive wireless signals. In an embodiment, the wireless antenna interface <NUM> operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory <NUM> includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory <NUM> includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

The memory <NUM> stores information and instructions to be executed by the processor <NUM>. In an embodiment, the memory <NUM> may also store temporary variables or other intermediate information while the processor <NUM> is executing instructions. In the illustrated embodiment, the chipset <NUM> connects with processor <NUM> via Point-to-Point (PtP or P-P) interfaces <NUM> and <NUM>. Either of these PtP embodiments may be achieved using a bridge die in glass substrate embodiment as set forth in this disclosure. The chipset <NUM> enables the processor <NUM> to connect to other elements in a bridge die in glass substrate embodiment in a system <NUM>. In an embodiment, interfaces <NUM> and <NUM> operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In an embodiment, the chipset <NUM> is operable to communicate with the processor <NUM>, 605N, the display device <NUM>, and other devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The chipset <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to at least do one of transmit and receive wireless signals.

The chipset <NUM> connects to the display device <NUM> via the interface <NUM>. The display <NUM> may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, the processor <NUM> and the chipset <NUM> are merged into a bridge die in glass substrate in a computing system. Additionally, the chipset <NUM> connects to one or more buses <NUM> and <NUM> that interconnect various elements <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Buses <NUM> and <NUM> may be interconnected together via a bus bridge <NUM> such as at least one bridge die in glass substrate apparatus embodiment. In an embodiment, the chipset <NUM>, via interface <NUM>, couples with a non-volatile memory <NUM>, a mass storage device(s) <NUM>, a keyboard/mouse <NUM>, a network interface <NUM>, smart TV <NUM>, and the consumer electronics <NUM>, etc..

In an embodiment, the mass storage device <NUM> includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the network interface <NUM> is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

While the modules shown in <FIG> are depicted as separate blocks within the embedded magnetic inductor and a bridge die in glass substrate in a computing system <NUM>, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory <NUM> is depicted as a separate block within processor <NUM>, cache memory <NUM> (or selected aspects of <NUM>) can be incorporated into the processor core <NUM>.

Where useful, the computing system <NUM> may have a broadcasting structure interface such as for affixing the apparatus to a cellular tower.

Claim 1:
A modular semiconductive device (<NUM>), comprising:
an at least partially embedded multi-die interconnect bridge, EMIB, (<NUM>) in a glass substrate (<NUM>), wherein the glass substrate includes a die side (<NUM>) and a land side (<NUM>);
a plurality of through-glass vias, TGVs, (<NUM>) that communicate from the die side to the land side;
a first semiconductive device (<NUM>) coupled to the EMIB and to at least one TGV, wherein the first semiconductive device includes substrate bond pads (<NUM>) that couple to the at least one TGV, and EMIB bond pads (<NUM>) that couple to the EMIB; and
a subsequent semiconductive device (<NUM>) coupled to the EMIB and to at least one TGV, wherein the subsequent semiconductive device includes substrate bond pads (<NUM>) that couple to the at least one TGV, and EMIB bond pads (<NUM>) that couple to the EMIB.