Patent Description:
Conventional processor-based systems provide resources, such as system caches and/or memory access bandwidth, which may be shared among multiple resource clients. To increase parallelism, a resource may be subdivided into partitions that may be operated and/or accessed largely independently of one another. For instance, a system cache (e.g., a last-level cache, as a non-limiting example) may be partitioned into multiple "slices" or "instances," each providing a same number of cache ways. Cache access operations by different resource clients may be assigned to one of the cache partitions using conventional address-to-partition mapping techniques based on, for example, hashes of memory addresses of cache access operations.

To facilitate sharing, a Quality of Service (QoS) mechanism may selectively allocate portions of a resource among difference resource clients, which may operate under different priorities, relative importance, and/or performance goals. For instance, in the cache example described above, a "way mask" (i.e., a bit mask including a bit for each cache way) corresponding to a resource client may be used to allocate a subset of the cache ways for each cache partition for use by that resource client. As a non-limiting example, a <NUM>-way set-associative cache may be subdivided into eight (<NUM>) partitions, with each resource client's way mask having <NUM> bits to indicate which of the <NUM> ways are allocated to that resource client. Because each resource client's way mask is applied to all partitions, the minimum cache space that can be allocated to each resource client is <NUM>%, or one (<NUM>) of the <NUM> ways over the eight (<NUM>) partitions.

Likewise, memory access bandwidth may also be allocated using conceptually similar controls. As an example, a processor-based system may provide four (<NUM>) memory controllers as memory access bandwidth providers. Each resource client may be assigned a "memory stride value" of four (<NUM>) bits to indicate how requests for memory bandwidth are weighted for that resource client, with a lower memory stride value indicating a higher weight. Because the memory stride value may have <NUM> different values (i.e., <NUM>-<NUM>), the minimum memory access bandwidth that can be allocated to each resource client is <NUM>% (or <NUM>/<NUM>) of the total memory access bandwidth.

However, finer-grained QoS control may be desirable for allocation of shared resources. The QoS mechanisms described above permit only relatively coarse-grained controls that limit allocation resolution and restrict the number of resource clients that may access a given shared resource. Moreover, many mechanisms for implementing fine-grained QoS control may result in higher hardware implementation costs.

<CIT> provides shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines.

Aspects according to the disclosure as described herein with reference to the appended claims include providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems. In this regard, in one aspect, a processor-based system provides a partitioned resource (i.e., a system cache or memory access bandwidth to a shared system memory, as non-limiting examples) that is subdivided into a plurality of partitions and configured to service a plurality of resource clients. For each combination of resource client and partition, an allocation indicator is provided to indicate an allocation of the partition for the resource client. As a non-limiting example, aspects in which the partitioned resource is a partitioned cache having a plurality of ways may provide an allocation indicator to indicate how many ways of the partition may be allocated to the resource client. Similarly, aspects in which the partitioned resource is a plurality of memory access bandwidth providers may provide that the allocation indicator indicates a stride to be applied by a memory controller when performing a memory access operation for the resource client.

Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client. For instance, if the partitioned resource is a <NUM>-way set-associative cache divided into four (<NUM>) partitions, conventional QoS mechanisms would only allow the cache to be allocated with a minimum resolution of <NUM>% (i.e., a minimum allocation is <NUM> way out of <NUM>). However, according to aspects disclosed herein, the allocation indicators for a given resource client may vary for each partition. As a non-limiting example, a resource client may be allocated <NUM>% of the first and second partitions, and <NUM>% of the third and fourth partitions. This results in a total aggregate allocation of the cache of <NUM>% for the resource client.

In another aspect, a processor-based system for providing fine-grained QoS control of partitioned resources is disclosed. The processor-based system comprises a partitioned resource subdivided into a plurality of partitions and configured to service a plurality of resource clients. The processor-based system further comprises a resource allocation agent and a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of a plurality of resource clients, and representing an allocation of the partition for the resource client. The resource allocation agent is configured to allocate the partitioned resource among the plurality of resource clients based on an interpolation of the plurality of allocation indicators for each resource client of the plurality of resource clients.

In another aspect, a processor-based system for providing fine-grained QoS control of partitioned resources is disclosed. The processor-based system comprises a means for allocating a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

In another aspect, a method for providing fine-grained QoS control of partitioned resources is disclosed. The method comprises allocating, by a resource allocation agent of a processor-based system, a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

In another aspect, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores thereon computer-executable instructions which, when executed by a processor, cause the processor to allocate a partitioned resource, subdivided into a plurality of partitions, among a plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

Aspects disclosed in the detailed description include providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems. In this regard, <FIG> illustrates an exemplary processor-based system <NUM> that includes a central processing unit (CPU) <NUM> and a partitioned resource <NUM> that is shared among multiple resource clients <NUM>(<NUM>)-<NUM>(C). The partitioned resource <NUM> according to some aspects may comprise a system cache, such as a last-level cache, and/or memory access bandwidth for a shared system memory accessible via a plurality of memory controllers (not shown). The resource clients <NUM>(<NUM>)-<NUM>(C) may comprise concurrently executing software processes, virtual machines, hardware devices, or other entities configured to access the partitioned resource <NUM>, as non-limiting examples. It is to be understood that the processor-based system <NUM> of <FIG> may encompass any one of known digital logic elements, semiconductor circuits, and processing cores, and/or memory structures, among other elements, or combinations thereof. Aspects described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor dies or packages. It is to be understood that some aspects of the processor-based system <NUM> may include elements in addition to those illustrated in <FIG>.

To facilitate parallel usage by the resource clients <NUM>(<NUM>)-<NUM>(C) of the partitioned resource <NUM>, the processor-based system <NUM> provides that the partitioned resource <NUM> is subdivided into a plurality of partitions <NUM>(<NUM>)-<NUM>(P), each of which may be further divided into sub-units that can be selectively allocated among the resource clients <NUM>(<NUM>)-<NUM>(C). For instance, in aspects of the processor-based system <NUM> in which the partitioned resource <NUM> comprises a system cache (e.g., a last-level cache, as a non-limiting example), the partitions <NUM>(<NUM>)-<NUM>(P) may comprise cache "slices" or "instances," each of which provides a same number of cache ways. Similarly, aspects of the processor-based system <NUM> in which the partitioned resource <NUM> comprises memory access bandwidth providers for a shared system memory may provide that each of the partitions <NUM>(<NUM>)-<NUM>(P) comprises a memory access bandwidth provider such as a memory controller. In both aspects, an access request <NUM> from a resource client <NUM>(<NUM>)-<NUM>(C), such as the resource client <NUM>(<NUM>), is assigned to one of the partitions <NUM>(<NUM>)-<NUM>(P) based on, for example, a hash of a memory address associated with the access request <NUM>.

However, as noted above, conventional QoS mechanisms for allocating the partitioned resource <NUM> among the resource clients <NUM>(<NUM>)-<NUM>(C) may not provide sufficient allocation resolution (i.e., the smallest allocatable portion of the partitioned resource <NUM> that can be allocated by the QoS mechanism may still be too large for precise allocation). Moreover, such coarse-grained QoS mechanisms may impose an inherent limit on the number of resource clients that may access a given shared resource. Thus, it is desirable to implement a fine-grained QoS mechanism to provide higher allocation resolution without incurring excessively higher hardware implementation costs.

In this regard, the processor-based system <NUM> of <FIG> provides a resource allocation agent <NUM>. While the resource allocation agent <NUM> is illustrated as a standalone element in <FIG>, in some aspects the resource allocation agent <NUM> may be integrated into the CPU <NUM>, into a cache controller (not shown) or a memory management unit (MMU) (not shown), integrated into or distributed across other elements of the processor-based system <NUM>, and/or implemented in part by a software entity (not shown) such as an operating system or a hypervisor executed by the CPU <NUM> of the processor-based system <NUM>. The resource allocation agent <NUM> employs a plurality of allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) associated with the partitions <NUM>(<NUM>)-<NUM>(P). Each of the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) corresponds to a unique combination of one of the resource clients <NUM>(<NUM>)-<NUM>(C) and one of the partitions <NUM>(<NUM>)-<NUM>(P), and represents an allocation of the partition <NUM>(<NUM>)-<NUM>(P) for the corresponding resource client <NUM>(<NUM>)-<NUM>(C). For example, in <FIG>, assume that the allocation indicator <NUM>(<NUM>) corresponds to the partition <NUM>(<NUM>) for the resource client <NUM>(<NUM>), while the allocation indicator <NUM>'(<NUM>) corresponds to the partition <NUM>(P) for the resource client <NUM>(<NUM>). Depending on whether the access request <NUM> is assigned to the partition <NUM>(<NUM>) or the partition <NUM>(P), either the allocation indicator <NUM>(<NUM>) or the allocation indicator <NUM>'(<NUM>) will be used by the resource allocation agent <NUM> to determine how much of the corresponding partition <NUM>(<NUM>), <NUM>(P) may be allocated to the resource client <NUM>(<NUM>) to satisfy the access request <NUM>.

Unlike conventional QoS mechanisms, each of the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) for a given one of the resource clients <NUM>(<NUM>)-<NUM>(C) may vary across different partitions <NUM>(<NUM>)-<NUM>(P). As a result, a resource client such as the resource client <NUM>(<NUM>) may be allocated different portions of each of the partitions <NUM>(<NUM>)-<NUM>(P). By interpolating the different allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C), a higher allocation resolution may be attained, thus enabling a smaller portion of the partitioned resource <NUM> to be allocated to each of the resource clients <NUM>(<NUM>)-<NUM>(C) if desired.

To illustrate exemplary aspects of the processor-based system <NUM>, <FIG> are provided. <FIG> illustrates an exemplary implementation of the processor-based system <NUM> of <FIG> wherein the partitioned resource <NUM> comprises a system cache and the resource allocation agent <NUM> comprises a cache controller, while <FIG> illustrates an exemplary implementation of the processor-based system <NUM> of <FIG> wherein the partitioned resource <NUM> comprises memory access bandwidth providers for a shared system memory and the resource allocation agent <NUM> comprises an MMU. <FIG> and <FIG> are provided to illustrate how interpolation of the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) provides fine-grained QoS control in each of the aforementioned aspects.

As seen in <FIG>, one aspect of the processor-based system <NUM> may provide a cache controller <NUM> corresponding to the resource allocation agent <NUM> of <FIG>. <FIG> further provides a system cache <NUM> that corresponds to the partitioned resource <NUM> of <FIG>, and a plurality of cache partitions <NUM>(<NUM>)-<NUM>(H) corresponding to the partitions <NUM>(<NUM>)-<NUM>(P) of <FIG>. Accordingly, disclosures herein regarding the resource allocation agent <NUM>, the partitioned resource <NUM>, and the partitions <NUM>(<NUM>)-<NUM>(P) of <FIG> apply to the cache controller <NUM>, the system cache <NUM>, and the cache partitions <NUM>(<NUM>)-<NUM>(H), respectively, of <FIG>. The system cache <NUM> may comprise a Level <NUM> (L1) cache, a Level <NUM> (L2) cache, a Level <NUM> (L3) cache, and/or a last-level cache, as non-limiting examples. Upon receiving a cache access request <NUM> comprising a memory address <NUM>, the cache controller <NUM> assigns the cache access request <NUM> to one of the cache partitions <NUM>(<NUM>)-<NUM>(H) (e.g., based on a hash of the memory address <NUM>).

The allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) in the example of <FIG> each comprise a way mask (not shown) providing a plurality of bit indicators (not shown). Each bit indicator of the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) corresponds to one way of one of the cache partitions <NUM>(<NUM>)-<NUM>(H) of the system cache <NUM>, and indicates whether the corresponding way has been allocated to the associated resource client <NUM>(<NUM>)-<NUM>(C). Using the way masks provided by the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C), the cache controller <NUM> allocates a portion of the assigned cache partition <NUM>(<NUM>)-<NUM>(H) to carry out the cache access request <NUM> on behalf of the resource client <NUM>(<NUM>)-<NUM>(C).

<FIG> provides a more detailed illustration of how the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) in the example of <FIG> may be interpolated to provide fine-grained QoS control of the system cache <NUM> of <FIG>. In this example, assume that the number of cache partitions <NUM>(<NUM>)-<NUM>(H) is four (i.e., H=<NUM>), and further that the cache partitions <NUM>(<NUM>)-<NUM>(<NUM>) of the system cache <NUM> are made up of <NUM> ways. Accordingly, the allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) provide way masks <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>), each of which is made up of <NUM> bits corresponding to the <NUM> ways. The allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>) represent the allocation of the cache partitions <NUM>(<NUM>)-<NUM>(<NUM>), respectively, of the system cache <NUM> for the resource client <NUM>(<NUM>). The allocation indicators <NUM>'(<NUM>)-<NUM>'(<NUM>) similarly represent the allocation of the cache partitions <NUM>(<NUM>)-<NUM>(<NUM>), respectively, of the system cache <NUM> for the resource client <NUM>(C).

Because the system cache <NUM> in this example is made up of <NUM> ways, a conventional QoS mechanism would be able to allocate the system cache <NUM> only in increments of <NUM>%. However, by interpolating the allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) to determine aggregate allocations of the system cache <NUM> for the resource clients <NUM>(<NUM>), <NUM>(C), a higher allocation resolution can be attained. In the example of <FIG>, instead of a resolution of <NUM>%, the system cache <NUM> may be allocated in increments as small as <NUM>% (i.e., the number of ways (<NUM>) divided by the number of cache partitions <NUM>(<NUM>)-<NUM>(<NUM>), in this example) by allocating one (<NUM>) way in one (<NUM>) of the cache partitions <NUM>(<NUM>)-<NUM>(<NUM>), and allocating zero (<NUM>) ways allocated in the remaining cache partitions <NUM>(<NUM>)-<NUM>(<NUM>). It is to be understood that the percentages discussed above are specific to the example of <FIG>, and may vary in some aspects according to the number of ways and the number of cache partitions <NUM>(<NUM>)-<NUM>(H).

In the example of <FIG>, the allocation indicators <NUM>(<NUM>) and <NUM>(<NUM>) have the first five (<NUM>) bit indicators set to a value of one (<NUM>), indicating that the first five (<NUM>) ways (i.e., <NUM>%) of the cache partitions <NUM>(<NUM>) and <NUM>(<NUM>), respectively, are allocated to the resource client <NUM>(<NUM>). The allocation indicators <NUM>(<NUM>) and <NUM>(<NUM>) have the first six (<NUM>) bit indicators set to a value of one (<NUM>), indicating that the first six (<NUM>) ways (i.e., <NUM>%) of the cache partitions <NUM>(<NUM>) and <NUM>(<NUM>), respectively, are allocated to the resource client <NUM>(<NUM>). Thus, the total aggregate allocation of the system cache <NUM> for the resource client <NUM>(<NUM>) is <NUM>% (i.e., (<NUM>+<NUM>+<NUM>+<NUM>) / <NUM>). Likewise, the allocation indicators <NUM>'(<NUM>) and <NUM>'(<NUM>) have the last five (<NUM>) bit indicators set to a value of one (<NUM>), indicating that the last five (<NUM>) ways (i.e., <NUM>%) of the cache partitions <NUM>(<NUM>) and <NUM>(<NUM>), respectively, are allocated to the resource client <NUM>(C). The allocation indicators <NUM>'(<NUM>) and <NUM>'(<NUM>) have the last four (<NUM>) bit indicators set to a value of one (<NUM>), indicating that the last four (<NUM>) ways (i.e., <NUM>%) of the cache partitions <NUM>(<NUM>) and <NUM>(<NUM>), respectively, are allocated to the resource client <NUM>(C). The total aggregate allocation of the system cache <NUM> for the resource client <NUM>(C) is therefore <NUM>% (i.e., (<NUM>+<NUM>+<NUM>+<NUM>) / <NUM>), an allocation that would not be possible using conventional QoS mechanisms with coarser resolutions.

Referring now to <FIG>, in another aspect, the processor-based system <NUM> of <FIG> may provide an MMU <NUM> corresponding to the resource allocation agent <NUM> of <FIG>, memory access bandwidth providers <NUM> that corresponds to the partitioned resource <NUM> of <FIG>, and a plurality of memory controllers <NUM>(<NUM>)-<NUM>(M) corresponding to the partitions <NUM>(<NUM>)-<NUM>(P) of <FIG>. Disclosures herein regarding the resource allocation agent <NUM>, the partitioned resource <NUM>, and the partitions <NUM>(<NUM>)-<NUM>(P) of <FIG> thus may apply to the MMU <NUM>, the memory access bandwidth providers <NUM>, and the memory controllers <NUM>(<NUM>)-<NUM>(M), respectively, of <FIG>. The processor-based system <NUM> also includes a shared system memory <NUM> that is accessible by the resource clients <NUM>(<NUM>)-<NUM>(C) via the memory controllers <NUM>(<NUM>)-<NUM>(M). In some aspects, the shared system memory <NUM> may comprise dynamic random access memory (DRAM), as a non-limiting example.

In the example of <FIG>, the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) each comprise a memory stride value (not shown) that indicates a weight associated with requests for memory access bandwidth for the corresponding resource client <NUM>(<NUM>)-<NUM>(C). In some aspects, the memory stride values are inversely proportional to the weight assigned to the requests for memory access bandwidth, such that a lower memory stride value indicates a higher weight. When the MMU <NUM> receives a memory access request <NUM> comprising a memory address <NUM>, the MMU <NUM> assigns the memory access request <NUM> to be handled by one of the memory controllers <NUM>(<NUM>)-<NUM>(M). As a non-limiting example, the memory access request <NUM> may be assigned to one of the memory controllers <NUM>(<NUM>)-<NUM>(M) based on a hash of the memory address <NUM>.

<FIG> illustrates in greater detail how fine-grained QoS control of the memory access bandwidth providers <NUM> of <FIG> may be provided by interpolating the allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C). In <FIG>, it is assumed that the number of memory controllers <NUM>(<NUM>)-<NUM>(M) is four (i.e., M=<NUM>). The allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) provide memory stride values <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) that have a size of four (<NUM>) bits and that indicate the relative weights assigned to requests for memory access bandwidth for the corresponding resource clients <NUM>(<NUM>)-<NUM>(C) and the memory controllers <NUM>(<NUM>)-<NUM>(<NUM>). In particular, the allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>) represent the allocations of the memory controllers <NUM>(<NUM>)-<NUM>(<NUM>), respectively, of the memory access bandwidth providers <NUM> for the resource client <NUM>(<NUM>), while the allocation indicators <NUM>'(<NUM>)-<NUM>'(<NUM>) represent the allocations of the memory controllers <NUM>(<NUM>)-<NUM>(<NUM>), respectively, of the memory access bandwidth providers <NUM> for the resource client <NUM>(C).

Because there are <NUM> possible values for each of the four-bit memory stride values <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>), a conventional QoS mechanism would be able to allocate the memory access bandwidth providers <NUM> only in increments of <NUM>% (i.e., <NUM>/<NUM>). In the example of <FIG>, though, a higher allocation resolution can be achieved by interpolating the allocation indicators <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) to provide fractional memory stride values for the resource clients <NUM>(<NUM>), <NUM>(C). In the example of <FIG>, instead of a resolution of <NUM>%, the memory access bandwidth providers <NUM> may be allocated in increments as small as <NUM>% (i.e., <NUM>/<NUM> divided by the number of memory controllers <NUM>(<NUM>)-<NUM>(<NUM>), in this example) by selecting a memory stride value <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) of one (<NUM>) for one (<NUM>) of the memory controllers <NUM>(<NUM>)-<NUM>(M), and selecting a memory stride value <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) of zero (<NUM>) in the remaining memory controllers <NUM>(<NUM>)-<NUM>(<NUM>). It is to be understood that the percentages discussed above are specific to the example of <FIG>, and may vary in some aspects according to the size of the memory stride values <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>'(<NUM>)-<NUM>'(<NUM>) and the number of memory controllers <NUM>(<NUM>)-<NUM>(<NUM>).

As seen in <FIG>, the allocation indicators <NUM>(<NUM>) and <NUM>(<NUM>) have been assigned the memory stride values <NUM>(<NUM>) and <NUM>(<NUM>), respectively, each having a value of two (<NUM>). The allocation indicators <NUM>(<NUM>) and <NUM>(<NUM>) have been assigned the memory stride values <NUM>(<NUM>) and <NUM>(<NUM>), respectively, each of which has a value of one (<NUM>) Thus, the total aggregate memory stride value of the memory access bandwidth providers <NUM> for the resource client <NUM>(<NUM>) is <NUM>. Similarly, the allocation indicators <NUM>'(<NUM>) and <NUM>'(<NUM>) have been assigned the memory stride values <NUM>'(<NUM>) and <NUM>'(<NUM>), respectively, each having a value of four (<NUM>), while the allocation indicators <NUM>'(<NUM>) and <NUM>'(<NUM>) have been assigned the memory stride values <NUM>'(<NUM>) and <NUM>'(<NUM>), respectively, each having a value of three (<NUM>). The total aggregate memory stride value of the memory access bandwidth providers <NUM> for the resource client <NUM>(C) is therefore <NUM>.

<FIG> illustrates exemplary operations of the processor-based system <NUM> and the resource allocation agent <NUM> of <FIG> for providing fine-grained QoS control using interpolation for the partitioned resource <NUM>. For the sake of clarity, elements of <FIG> are referenced in describing <FIG>. In <FIG>, operations begin with the processor-based system <NUM> providing the partitioned resource <NUM> subdivided into a plurality of partitions <NUM>(<NUM>)-<NUM>(P) and configured to service a plurality of resource clients <NUM>(<NUM>)-<NUM>(C) (block <NUM>). In this regard, the processor-based system <NUM> may be referred to herein as "a means for providing a partitioned resource subdivided into a plurality of partitions and configured to service a plurality of resource clients.

The resource allocation agent <NUM> (e.g., the cache controller <NUM> of <FIG> and/or the MMU <NUM> of <FIG>, as non-limiting examples) then allocates the partitioned resource <NUM> among the plurality of resource clients <NUM>(<NUM>)-<NUM>(C) based on an interpolation of a plurality of allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C), each corresponding to a partition <NUM>(<NUM>)-<NUM>(P) of the plurality of partitions <NUM>(<NUM>)-<NUM>(P) and a resource client <NUM>(<NUM>)-<NUM>(C) of the plurality of resource clients <NUM>(<NUM>)-<NUM>(C), and representing an allocation of the partition <NUM>(<NUM>)-<NUM>(P) for the resource client <NUM>(<NUM>)-<NUM>(C) (block <NUM>). Accordingly, the resource allocation agent <NUM> may be referred to herein as "a means for allocating the partitioned resource among the plurality of resource clients based on an interpolation of a plurality of allocation indicators, each corresponding to a partition of the plurality of partitions and a resource client of the plurality of resource clients, and representing an allocation of the partition for the resource client.

To illustrate further exemplary operations of the resource allocation agent <NUM> of <FIG> for receiving and assigning an access request, such as the access request <NUM> of <FIG>, to the partitions <NUM>(<NUM>)-<NUM>(P) of the partitioned resource <NUM>, <FIG> is provided. Elements of <FIG> are referenced in describing <FIG>, for the sake of clarity. Operations in <FIG> begin with the resource allocation agent <NUM> receiving the access request <NUM> for the partitioned resource <NUM> from a resource client <NUM>(<NUM>)-<NUM>(C) of the plurality of resource clients <NUM>(<NUM>)-<NUM>(C) (block <NUM>). In aspects of the processor-based system <NUM> providing the system cache <NUM> of <FIG>, operations of block <NUM> for receiving the access request <NUM> may be carried out by the cache controller <NUM>, and may comprise receiving a cache access request <NUM> comprising a memory address <NUM> (block <NUM>). Likewise, aspects of the processor-based system <NUM> including the shared system memory <NUM> of <FIG> may provide that operations of block <NUM> for receiving the access request <NUM> may be carried out by the MMU <NUM>, and may comprise receiving a memory access request <NUM> comprising a memory address <NUM> (block <NUM>).

Next, the access request <NUM> is assigned to a partition <NUM>(<NUM>)-<NUM>(P) of the partitioned resource <NUM> (block <NUM>). Operations of block <NUM> for assigning the access request <NUM> according to the aspects illustrated in <FIG> and <FIG> may comprise selecting a cache partition <NUM>(<NUM>)-<NUM>(H) of the plurality of cache partitions <NUM>(<NUM>)-<NUM>(H) of the system cache <NUM>, based on a hash of the memory address <NUM> (block <NUM>). In aspects illustrated in <FIG> and <FIG>, operations of block <NUM> for assigning the access request <NUM> may comprise selecting a memory controller <NUM>(<NUM>)-<NUM>(M) of the plurality of memory controllers <NUM>(<NUM>)-<NUM>(M) to access the memory access bandwidth, based on a hash of the memory address <NUM> (block <NUM>). The resource allocation agent <NUM> (e.g., the cache controller <NUM> of <FIG> and/or the MMU <NUM> of <FIG>, as non-limiting examples) allocates a portion of the partition <NUM>(<NUM>)-<NUM>(P) of the partitioned resource <NUM> to the resource client <NUM>(<NUM>)-<NUM>(C) based on an allocation indicator <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) of the plurality of allocation indicators <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C), each corresponding to a partition <NUM>(<NUM>)-<NUM>(P) of the plurality of partitions <NUM>(<NUM>)-<NUM>(P) and a resource client <NUM>(<NUM>)-<NUM>(C) of the plurality of resource clients <NUM>(<NUM>)-<NUM>(C) (block <NUM>).

Providing fine-grained QoS control using interpolation for partitioned resources in processor-based systems according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that corresponds to the processor-based system <NUM> of <FIG>, <FIG>, and <FIG>, and that can employ the resource allocation agent <NUM> illustrated in <FIG>. The processor-based system <NUM> includes one or more CPUs <NUM>, each including one or more processors <NUM>. The CPU(s) <NUM> may have cache memory <NUM> that is coupled to the processor(s) <NUM> for rapid access to temporarily stored data, and that in some aspects may comprise the resource allocation agent <NUM> of <FIG>. The CPU(s) <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU(s) <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the CPU(s) <NUM> can communicate bus transaction requests to a memory controller <NUM> as an example of a slave device. According to some aspects, the memory controller <NUM> may correspond to the memory controllers <NUM>(<NUM>)-<NUM>(M) of <FIG>.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include a memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. In some aspects, the memory system <NUM> may comprise the resource allocation agent <NUM> of <FIG>. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include one or more memory units <NUM>(<NUM>)-<NUM>(N).

The CPU(s) <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure.

Claim 1:
A processor-based system (<NUM>) for providing fine-grained Quality of Service, QoS, control of partitioned resources (<NUM>), comprising:
a partitioned resource (<NUM>) subdivided into a plurality of partitions (<NUM>) and configured to service a plurality of resource clients (<NUM>);
a plurality of allocation indicators (<NUM>), each corresponding to a partition of the plurality of partitions and a resource client of a plurality of resource clients, wherein each of the plurality of allocation indicators corresponds to a unique combination of a resource client (<NUM>) and a partition (<NUM>) and represents an allocation of the partition (<NUM>) for the resource client (<NUM>); and
a resource allocation agent (<NUM>) configured to allocate the partitioned resource among the plurality of resource clients, the resource allocation agent configured to receive an access request (<NUM>) for the partitioned resource from a resource client (<NUM>) of the plurality of resource clients; assign the access request to a partition of the partitioned resource; and allocate a portion of the partition of the partitioned resource to the resource client based on an allocation indicator (<NUM>) of the plurality of allocation indicators corresponding to the partition and the resource client (<NUM>).