Patent Description:
With rapid development of integration of integrated circuit technology, packaging technology has reached an unprecedented and innovative technical level.

Electrical tests of packaged integrated circuits are mainly achieved by a probe card. In conventional technology, lifetimes of testing probes in a probe card are affected by ambient temperature, mechanical actuation, and current resistance, and testing probes thereof cannot overcome measurement errors caused by the above effects.

In addition, when conventional testing probes are used for wafer testing, there are demands, such as compliance and amount of displacement that the testing probes can withstand, so that the testing probes should have elasticity, that is, the ability to deform itself to adapt to height differences between various points to be measured. Due to the above demands, the testing probes must have a fine diameter. As a result, the ability of the testing probes to withstand current is bound to be limited. This ability to withstand large currents is a key factor when applied to test high frequency products such as <NUM> high frequency chips. Since the testing probes are formed with a large number, short-circuiting of the testing probes may be caused during operation, which may affect the measurement or even damage the circuit function, thereby adversely affecting the function of the probe card and the test results.

In addition, testing probes with its own deformability encounter problems such as a pitch that cannot be further reduced and rising costs under the trend that the contact points over the dies fabricated by modern semiconductor process become more and more, and a distance between the contact points is getting less and less.

Therefore, there is a need for a probe structure that can shorten the pitch between the probes, improve reliability, and increase current resistance, heat dissipation, and/or mechanical strength to overcome the above drawbacks.

<CIT> proposes a probe and a method for fabricate the same. <CIT> proposes a sheet-like probe, a method of manufacturing the same, and an application thereof. <CIT> proposes a semiconductor device, a circuit board, and an electronic instrument. <CIT> proposes a bonding pad structure. <CIT> proposes a multilayer wiring substrate and a method for manufacturing the same, and a substrate for use in an IC inspection device and a method for manufacturing the same.

In view of this, the present invention provides a metal probe structure and a method for fabricating the same to provide. A probe structure for a probe card having better reliability, current resistance, heat dissipation and/or mechanical strength can be provided. With the multi-layer flexible substrate possessed by the metal probe structure, the compliance can be achieved, and the metal probe with high rigidity and high current resistance can be adapted to the height difference of the points to be tests.

According to an aspect, a metal probe for testing an unpacked chip is defined in claim <NUM>.

According to another aspect, a method for fabricating a metal probe structure for testing an unpacked chip is defined in claim <NUM>.

The method for fabricating a metal probe structure of the embodiment of the invention and the metal probe structure formed by thereof is a composite metal probe structure made of a plurality of metal components formed by stacking a plurality of metal components and a metal layer physically connecting the metal stacks. In this way, properties of the metal probe structure including but not limited to such as the material, the number of layers, the pitch, and the aspect ratio of the metal stack and the metal layer can be designed and adjusted according to the type of the test wafer, thereby providing a metal probe with good reliability, electrical conductivity, heat dissipation and/or mechanical strength than the metal probe used in the conventional probe card. With the multi-layer flexible substrate possessed by the metal probe structure, the compliance effect can be achieved, and the metal probe with high rigidity and high current resistance can be adapted to the height differences of the testing points to be measured.

To detailly explain the technical schemes of the embodiments or existing techniques, drawings that are used to illustrate the embodiments or existing techniques are provided. Apparently, the illustrated embodiments are just a part of those of the present disclosure. It is easy for any person having ordinary skill in the art to obtain other drawings without labor for inventiveness.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure of the present specification. The present invention may be carried out or applied in various other specific embodiments, and various modifications and changes can be made without departing from the scope of the invention. In addition, the drawings of the present invention are merely illustrative and are not intended to be construed in terms of actual dimensions. The following embodiments will further explain the related technical content of the present invention, but the disclosure is not intended to limit the technical scope of the present invention.

<FIG> are schematic cross-sectional views showing a method for fabricating a metal probe structure in accordance with an embodiment of the present invention.

Referring to <FIG>, a multi-layer substrate <NUM> is first provided, having a first flexible dielectric layer <NUM> and a conductive layer <NUM> sequentially formed thereover. A conductive layer <NUM> is formed between the multi-layer substrate <NUM> and the flexible dielectric layer <NUM>, which is connected to the conductive layer <NUM>. A second flexible dielectric layer <NUM> is then formed over the first flexible dielectric layer <NUM> to cover the conductive layer <NUM>.

In one embodiment, the multi-layer substrate <NUM> is, for example, a flexible multi-layer substrate comprising a plurality of flexible dielectric layers and conductive layers (both not shown) that are sequentially interleaved to function as a probe card substrate having a multi-layer interconnect structure. The flexible dielectric layer uses polyimide (PI) having a low dielectric constant, and the conductive layer uses a metal line to function as a subsequent electrical connection.

Referring to <FIG>, a plurality of first openings 120a are formed in the second flexible dielectric layer <NUM>, and the first openings 120a respectively expose a portion of the conductive layer <NUM>. Then, a patterned photoresist layer <NUM> is formed over the second flexible dielectric layer <NUM>, and the patterned photoresist layer <NUM> comprises a plurality of second openings 99a respectively located over the first openings 120a and respectively exposing the first openings 120a and a portion of the conductive layer <NUM> exposed by the first openings 120a. Here, the number of the first opening 120a and the second opening 99a are illustrated by two as an example, but is not limited thereto.

Referring to <FIG>, a first metal component 140a is formed in each of the first openings 120a. Here, the first metal member 140a fills the first openings 120a and physically contacts the conductive layer <NUM>. After the patterned photoresist layer <NUM> (see <FIG>) is removed, a third flexible dielectric layer <NUM> is formed over the second flexible dielectric layer <NUM> and covers the first metal components 140a.

Referring to <FIG>, a plurality of first metal components <NUM> are formed in the third flexible dielectric layer <NUM>. The first metal components <NUM> can be obtained by repeating the steps in <FIG> once, and the formed first metal components <NUM> are respectively located over the previous first metal components 140a. A third flexible dielectric layer <NUM> is then formed over the third flexible dielectric layer <NUM> and the first metal features <NUM>.

Referring to <FIG>, the steps shown in <FIG> can be repeated once, and a plurality of third openings 150a are formed in the third flexible dielectric layer <NUM> to respectively expose each of the first metal components <NUM>, a first metal component <NUM> is then formed in the third openings 150a, respectively, to form a plurality of metal stacks comprising a plurality of first metal components 140a, <NUM>, and <NUM> which are sequentially stacked (see <FIG>).

In this embodiment, the first flexible dielectric layer <NUM>, the second flexible dielectric layer <NUM>, <NUM> and the third flexible dielectric layer <NUM> comprise polyimide, and the first metal components 140a, <NUM>, and <NUM> comprise copper or aluminum, and can be formed by, for example, evaporation deposition. The first metal components 140a, <NUM>, and <NUM> have a maximum width of about <NUM> to <NUM> micrometers and a maximum height of about <NUM> to <NUM> micrometers, respectively, and the metal stacks A have an aspect ratio of <NUM>:<NUM> to <NUM>:<NUM>, respectively.

Referring to <FIG>, an annealing process <NUM> is then performed to the metal stacks A (see <FIG>) comprising the plurality of first metal elements 140a, <NUM>, and <NUM> sequentially stacked, which is performed at a temperature of about <NUM>-<NUM> ° C.

Referring to <FIG>, an etching process <NUM> is then performed to remove the third flexible dielectric layers <NUM> and <NUM>, and a portion of the second flexible dielectric layer <NUM> to expose a portion of the metal stack A comprising these first metal components 140a, <NUM> and <NUM>, and the first metal components 140a, <NUM>, and <NUM> are already able to function as metal probes. In the present embodiment, the etching process <NUM> is, for example, dry etching using an etching gas such as fluoride or oxygen, and the metal stacks A have a pitch of <NUM> to <NUM>.

Referring to <FIG>, an optional electroplating process <NUM> can be next performed to form a metal layer <NUM> over the side and top surfaces of the metal stacks A to physically combine the metal stacks A, thereby forming these metal stacks A into a metal probe C. In this present embodiment, the electroplating process <NUM> can be, for example, an electroless plating process, and the metal layer <NUM> may comprise nickel, palladium, gold, and alloys thereof. In addition, the thickness of each film layer can be appropriately adjusted, so that the formed metal probe C may have an aspect ratio of <NUM>:<NUM> to <NUM>:<NUM>.

<FIG> are schematic cross-sectional views showing a method for fabricating a metal probe structure in accordance with another embodiment of the present invention.

Referring to <FIG>, a multi-layer substrate <NUM> is first provided, and a first flexible dielectric layer <NUM> and a conductive layer <NUM> are sequentially formed thereover. A conductive layer <NUM> is formed between the multi-layer substrate <NUM> and the flexible dielectric layer <NUM>. The conductive layer <NUM> is physically connected to the conductive layer <NUM>. A second flexible dielectric layer <NUM> is then formed over the first flexible dielectric layer <NUM> to cover the conductive layer <NUM>.

In one embodiment, the multi-layer substrate <NUM> can be, for example, a flexible multi-layer substrate comprising a plurality of flexible dielectric layers and conductive layers (both not shown) which are sequentially interleaved to function as a probe card substrate having a plurality of interconnect structures, wherein the flexible dielectric layers use polyimide (PI) having a low dielectric constant, and the conductive layers use a metal line for subsequent electrical connections.

Referring to <FIG>, a plurality of first openings 120a are formed in the second flexible dielectric layer <NUM>, and the first openings 120a respectively expose a portion of the conductive layer <NUM>. Here, the number of the first openings 120a are illustrated by two as an example, but is not limited thereto.

Referring to <FIG>, a first metal component <NUM> is formed in each of the first openings 120a. The first metal component <NUM> fills in the first openings 120a and physically contacts the conductive layer <NUM>. Then, a patterned photoresist layer <NUM> is formed over the second flexible dielectric layer <NUM>, wherein the patterned photoresist layer <NUM> has a plurality of second openings 99a respectively exposing the first metal components <NUM> located in the first openings <NUM>. Here, the number of the second openings 99a is illustrated by two, but is not limited thereto.

Referring to <FIG>, a second metal component 140b is formed in each of the second openings 99a. Here, the second metal component 140b fills the second openings 99a and physically contacts one of the first metal components <NUM>. Next, after the patterned photoresist layer <NUM> is removed, the second metal component 140b is left over each of the first metal components <NUM>.

Referring to <FIG>, a patterned third flexible dielectric layer <NUM> is formed on the second flexible dielectric layer <NUM> and covers the second metal components 140b, wherein the patterned third flexible dielectric layer <NUM> comprises a plurality of third openings 150b that respectively expose one of the second metal members 140b. Here, the number of the third openings 150b is illustrated by two as an example, but is not limited thereto.

Referring to <FIG>, another first metal component <NUM> is formed in the third openings 150b. The first metal component <NUM> fills each of the third openings 150b and physically contacts the second metal component 140b.

Referring to <FIG>, the fabrication method shown in <FIG> can be repeated again, and another third flexible dielectric layer <NUM> over the third flexible dielectric layer <NUM> and a plurality of second metal components 180a in the third flexible dielectric layer <NUM> are formed. The second metal components 180a and first metal components <NUM> are disposed in the same location and stacking relationship as the second metal component 140b and the first metal component <NUM> located in the third flexible dielectric layer <NUM>, and the second metal components 180a physically contacts one of the first metal components <NUM> below, respectively. Then, the fabrication method shown in <FIG> can be further repeated to form the second metal component <NUM> respectively located over the first metal component <NUM>, thereby forming a plurality of metal stacks A' (see <FIG>) comprising a plurality of first metal components <NUM>, <NUM>, and <NUM> and a plurality of second metal elements 140b, 180a and <NUM>.

In this embodiment, the first flexible dielectric layer <NUM>, the second flexible dielectric layer <NUM>, <NUM>, and the third flexible dielectric layer <NUM> comprise polyimide, and the first metal components <NUM>, <NUM>, and <NUM> comprise copper or aluminum and can be formed by, for example, evaporation deposition. The first metal components <NUM>, <NUM>, and <NUM> have a maximum width of <NUM> to <NUM> micrometers and a maximum height of <NUM> to <NUM> micrometers, respectively. In addition, the second metal components 140b, 180a, and <NUM> comprise nickel, palladium, gold, and alloys thereof, and may be formed by, for example, chemical electroless plating. The second metal components 140b, 180a, and <NUM> have a maximum width of <NUM> to <NUM> micrometers and a maximum height of <NUM> to <NUM> micrometers, respectively.

Referring to <FIG>, an annealing process <NUM> is performed to the metal stacks A' (see <FIG>) comprising the plurality of first metal elements <NUM>, <NUM>, and <NUM>, and the plurality of second metal elements 140b, <NUM>, and <NUM> sequentially stacked, which is performed at a temperature of about <NUM>-<NUM>.

Referring to <FIG>, an etching process <NUM> is performed to remove the third flexible dielectric layer <NUM>, <NUM>, and a portion of the second flexible dielectric layer <NUM>, thereby exposing a portion of the metal stacks A' (see <FIG>) comprising the plurality of first metal elements <NUM>, <NUM>, and <NUM>, and the plurality of second metal elements 140b, <NUM>, and <NUM>. In the present embodiment, the etching process <NUM> is, for example, dry etching using an etching gas including fluoride, oxygen, etc., and the metal stacks A' have a pitch of <NUM> to <NUM>, and the metal stacks have an aspect ratio of <NUM>:<NUM>-<NUM>:<NUM>, respectively.

Referring to <FIG>, an electroplating process <NUM> can be next performed to form a metal layer <NUM> over the side and top surfaces of the metal stacks A' to physically combine the metal stacks A', thereby forming these metal stacks A' into a metal probe C. In this present embodiment, the electroplating process <NUM> can be, for example, an electroless plating process, and the metal layer <NUM> may comprise nickel, palladium, gold, and alloys thereof. In addition, the thickness of each film layer can be appropriately adjusted, so that the formed metal probe C may have an aspect ratio of <NUM>:<NUM> to <NUM>:<NUM>.

<NUM>-<NUM> show top schematic views of metal probe structures in accordance with several embodiments of the present invention.

Referring to <FIG>, a top view of one of the metal probe structures shown in <FIG> and <FIG> is shown. Here, the metal probe C in the metal probe structure is composed of a metal layer <NUM> over a side and top surfaces of two metal stacks A/A' and the two metal stacks A/A', and the cross-sectional view shown in <FIG> and <FIG> mainly show the cross-sectional view along the line F-F in <FIG>.

In addition, referring to <FIG>, another top view of the metal probe structure shown in <FIG> and <FIG> is shown. Here, the metal probe C in the metal probe structure is composed of a metal layer <NUM> over a side and top surfaces of four metal stacks A/A' and the four metal stacks A/A', and the cross-sectional view shown in <FIG> and <FIG> only partially show the cross-sectional view of the two metal stacks A/A' along the line F-F in <FIG>.

Furthermore, please refer to <FIG>, which shows another schematic diagram of the metal probe structure shown in <FIG> and <FIG>. In other embodiments, the metal probe C of the metal probe structure shown in <FIG> and <FIG> may be composed only of the metal layer <NUM> over a side and top surfaces of a metal stack A/A' and the metal stack A/A', and the cross-sectional views shown in <FIG> and <FIG> only partially show the profile of a metal stack A/A' along the line F-F in <FIG>.

In summary, the method for fabricating the metal probe structure of the present invention and the metal probe structure formed by thereof is a composite metal probe structure made of a plurality of metal components formed by stacking a plurality of metal components and a metal layer physically connecting the metal stacks. In this way, properties of the metal probe structure including but not limited to such as the material, the number of layers, the pitch, and the aspect ratio of the metal stack and the metal layer can be designed and adjusted according to the type of the test wafer, thereby providing a metal probe with good reliability, electrical conductivity, heat dissipation and/or mechanical strength than the metal probe used in the conventional probe card.

Claim 1:
A metal probe structure for testing an unpacked chip, comprising:
a multi-layer substrate (<NUM>);
a first flexible dielectric layer (<NUM>) sequentially formed and disposed over the multi-layer substrate, having a conductive layer (<NUM>) formed thereover;
a second flexible dielectric layer (<NUM>) sequentially formed and disposed over the first flexible dielectric layer, covering the conductive layer; and
a plurality of first metal components (140a, <NUM>, <NUM>) sequentially formed and disposed over the conductive layer and partially in the second flexible dielectric layer to serve as a metal probe (C),
wherein dielectric layers in the multi-layer substrate (<NUM>), the first flexible dielectric layer (<NUM>), and the second flexible dielectric layer (<NUM>) are of the same material.