Patent Description:
For an integrated circuit chip/package that includes a processor, code and data caches closest to the processor may be referred to as first level (L1) caches (e.g., a L1 code cache and a L1 data cache). The next level caches (e.g., a second level (L2) cache, a third level cache (L3), etc.) may be referred to as mid-level cache (MLC) and may be shared by functional units in the same chip/package with the MLCs. A last level cache (LLC) may refer to a highest-level cache that may be shared by functional units in the same chip/package with the LLC. <CIT>, discloses partitioning an unified cache into a first portion of lines that only store copies of instructions retrieved from a memory and a second portion of lines that only store copies of data retrieved from the memory.

<CIT> discloses allocating data and instructions within a shared cache.

The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:.

Embodiments discussed herein variously provide techniques and mechanisms for controlling a cache. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including integrated circuitry which is operable to control or utilize a cache.

In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Some embodiments provide technology for dynamic shared cache partitioning for workloads with large code footprints. Feature-rich client and server applications may increasingly use deep software stacks to support enhanced computing experiences for the end user. Consequently, such workloads execute a large codebase and their code footprint may be multiple megabytes (MBs). Such a large code footprint may overwhelm smaller first level (L1) code caches (e.g., with a size of <NUM> to <NUM> kilobytes (KB)) employed in some processors. The increased number of code cache lines compete with data cache lines for limited storage capacity of unified (e.g., code plus data) caches (e.g., level <NUM> (L2), level <NUM> (L3), mid-level cache (MLC), etc.). As a result, the MLCs end up evicting numerous useful data cache lines, which reduces the overall performance of many workloads.

One approach to handle the problem of increasing code and data footprints is to increase the size of the L2 cache. Some processors may employ a L2 cache size of <NUM> to 2MB in order to serve increasing code and data footprints of more demanding datacenter software stacks and applications. A larger L2 cache size leads to better hit rates for code and data. Even with the increased area and power budget, however, larger L2 caches do not solve a problem of thrashing (e.g., interference) between code and data cache blocks. For some large code footprint workloads, the code footprint may be about one quarter (<NUM>/<NUM>) the size of the data footprint for the workload, but the code cache lines may occupy more than one half (><NUM>%) of the L2 storage capacity. The disproportionate amount of L2 cache occupied by code cache lines may contribute to the detrimental impact of thrashing between code and data on the presence and utility of data cache lines in the L2.

Some embodiments may provide technology for a processor's L2 cache to reduce such thrashing between code and data cache lines during the execution of large code footprint workloads. Embodiments of the technology described herein may also be employed in other shared caches, such as the LLC.

With reference to <FIG>, an embodiment of an integrated circuit <NUM> may include a core <NUM>, a first level core cache memory <NUM> coupled to the core <NUM>, a shared core cache memory <NUM> coupled to the core <NUM>, a first cache controller 114a coupled to the core <NUM> and communicatively coupled to the first level core cache memory <NUM>, a second cache controller 114b coupled to the core <NUM> and communicatively coupled to the shared core cache memory <NUM>, and circuitry <NUM> coupled to the core <NUM> and communicatively coupled to the first cache controller 114a and the second cache controller 114b to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory <NUM> into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero.

In some embodiments, the circuitry <NUM> may be configured to determine if the workload has the large code footprint based on a number of first level code cache misses from the workload and a number of first level data cache misses from the workload. For example, the circuitry <NUM> may be further configured to count the number of first level code cache misses from the workload, count the number of first level data cache misses from the workload, and determine that the workload has the large code footprint if the counted number of first level code cache misses exceeds the counted number of first level data cache misses after a counted number of first level cache misses exceeds a threshold. In some embodiments, the circuitry <NUM> may also be configured to reset the number of first level code cache misses to be half of the counted number of first level code cache misses after the counted number of first level cache misses exceeds the threshold, reset the number of first level data cache misses to be half of the counted number of first level data cache misses after the counted number of first level cache misses exceeds the threshold, and reset the number of first level cache misses to zero after the counted number of first level cache misses exceeds the threshold.

In some embodiments, the circuitry <NUM> may be further configured to restrict code cache lines from the workload to occupy the first chunk of ways for code for the workload, and restrict data cache lines from the workload to occupy the second chunk of ways for data for the workload. For example, the circuitry <NUM> may be configured to decrease priority of non-hit cache lines in only the first chunk of ways for code in response to a demand hit to a cache line in the first chunk of ways for code, and decrease priority of non-hit cache lines in only the second chunk of ways for data in response to a demand hit to a cache line in the second chunk of ways for data. The circuitry <NUM> may also be configured to evict a lowest priority cache line from only the first chunk of ways for code to insert a code cache line in the first chunk of ways for code, and evict a lowest priority cache line from only the second chunk of ways for data to insert a data cache line in the second chunk of ways for data.

Embodiments of the first level core cache memory <NUM>, the shared core cache memory <NUM>, the first cache controller 114a, the second cache controller 114b, and/or the circuitry <NUM> may be incorporated in a processor including, for example, the core <NUM> (<FIG>), the cores 1102A-N (<FIG>, <FIG>), the processor <NUM> (<FIG>), the co-processor <NUM> (<FIG>), the processor <NUM> (<FIG>), the processor/coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), and/or the processors <NUM>, <NUM> (<FIG>).

With reference to <FIG>, an embodiment of a method <NUM> of controlling a cache may include determining if a workload has a large code footprint at box <NUM>, and, if so determined, partitioning N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways (M> <NUM>) reserved for code cache lines from the workload and the second chunk of N minus M ways (N-M > <NUM>) reserved for data cache lines from the workload at box <NUM>, where N and M are positive integer values.

Some embodiments of the method <NUM> may include determining if the workload has the large code footprint based on a number of first level code cache misses from the workload and a number of first level data cache misses from the workload at box <NUM>. For example, the method <NUM> may include counting the number of first level code cache misses from the workload at box <NUM>, counting the number of first level data cache misses from the workload at box <NUM>, and determining that the workload has the large code footprint if the counted number of first level code cache misses exceeds the counted number of first level data cache misses after a counted number of first level cache misses exceeds a threshold at box <NUM>. Some embodiments of the method <NUM> may also include resetting the number of first level code cache misses to be half of the counted number of first level code cache misses after the counted number of first level cache misses exceeds the threshold at box <NUM>, resetting the number of first level data cache misses to be half of the counted number of first level data cache misses after the counted number of first level cache misses exceeds the threshold at box <NUM>, and resetting the number of first level cache misses to zero after the counted number of first level cache misses exceeds the threshold at box <NUM>.

Some embodiments of the method <NUM> may further include restricting code cache lines from the workload to occupy the first chunk of ways for code for the workload at box <NUM>, and restricting data cache lines from the workload to occupy the second chunk of ways for data for the workload at box <NUM>. For example, the method <NUM> may also include decreasing priority of non-hit cache lines in only the first chunk of ways for code in response to a demand hit to a cache line in the first chunk of ways for code at box <NUM>, and decreasing priority of non-hit cache lines in only the second chunk of ways for data in response to a demand hit to a cache line in the second chunk of ways for data at box <NUM>. Some embodiments of the method <NUM> may further include evicting a lowest priority cache line from only the first chunk of ways for code to insert a code cache line in the first chunk of ways for code at box <NUM>, and evicting a lowest priority cache line from only the second chunk of ways for data to insert a data cache line in the second chunk of ways for data at box <NUM>.

With reference to <FIG>, an embodiment of an apparatus <NUM> may include one or more processor cores <NUM>, a first level core cache memory <NUM>, a shared core cache memory <NUM>, a first cache controller 335A communicatively coupled to the first level core cache memory <NUM>, a second cache controller 335B communicatively coupled to the shared core cache memory <NUM>, and circuitry <NUM> communicatively coupled to the first cache controller 335A and the second cache controller 335B to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory <NUM> into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero.

Embodiments of the first level core cache <NUM>, the shared core cache <NUM>, the first cache controller 335A, the second cache controller 335B, and/or the circuitry <NUM> may be integrated with processors including, for example, the core <NUM> (<FIG>), the cores 1102A-N (<FIG>, <FIG>), the processor <NUM> (<FIG>), the co-processor <NUM> (<FIG>), the processor <NUM> (<FIG>), the processor/coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), and/or the processors <NUM>, <NUM> (<FIG>).

Some embodiments may provide technology to dynamically partition an L2 cache into separate (e.g., distinct) code and data ways. Some embodiments may first dynamically detect the execution of a large code footprint workload by observing the ratio of code to data requests at the L2 cache. When operating with large code footprints, some embodiments may dynamically partition the L2 cache in code and data ways by controlling mutually exclusive subsets of ways into which code and data requests can fill or for which code and data requests may modify least recently used (LRU) information associated with the cache entries. Advantageously, some embodiments may incur little or no hardware overhead and may reduce or eliminate thrashing between code and data in the shared L2 cache. As compared to increasing L2 cache size, some embodiments advantageously provide area and power efficient technology to increase the L2 hit rate and also provide performance gains for workloads with large code footprints. Embodiments may further provide dynamic learning technology to ensure that the dynamic shared cache partitioning does not lead to a negative impact for workloads that do not have large code footprints.

For a large number of large code footprint workloads, code cache lines may occupy greater than <NUM>-<NUM>% of the L2 cache capacity. Some embodiments may advantageously constrain code cache lines for a large code footprint workload to occupy a smaller portion of the L2 cache, such that data cache lines observe better locality, and the workload's overall performance increases (e.g., due to increased data hit rate in the L2 cache). Some embodiments detect the execution of large code footprint traces at run time. For such detected workloads, some embodiments dynamically partition the L2 cache in to distinct components for code and data. For an L2 cache with <NUM> ways, for example, some embodiments may restrict code cache lines to occupy only M ways and allow data cache lines to occupy the remaining <NUM>-M ways. Some embodiments may set M to a fixed value of about twenty five percent (<NUM>%) of the L2 space for code (e.g., M=<NUM>, or <NUM>% of the space for code in an L2 cache with <NUM> ways). Alternatively, some embodiments may provide technology for M to be configurable (e.g., per processor, based on the characteristics of a specific workload, based on an application/customer setting, etc.).

With reference to <FIG>, an embodiment of a method <NUM> of controlling a cache may include an example process for detecting large code footprint traces. The method <NUM> includes receiving an L2 cache request at box <NUM>. The method <NUM> may then proceed to determining if the request corresponds to a L1 code cache miss at box <NUM> and, if so, incrementing a code miss counter at box <NUM> (e.g., which may have been previously initialized with a zero value) and incrementing a L1 miss counter at box <NUM>. Otherwise, the method <NUM> may proceed to determining if the request corresponds to a L1 data cache miss at box <NUM> and, if so, incrementing a data miss counter at box <NUM> (e.g., which may have been previously initialized with a zero value) and incrementing the L1 miss counter at box <NUM>. If the L2 cache request does not correspond to either a L1 code cache miss at box <NUM> or a L1 data cache miss at box <NUM>, the method <NUM> may proceed to handle the L2 cache request at box <NUM>. After incrementing the L1 miss counter at box <NUM>, the method <NUM> may proceed to determining if the L1 miss counter exceeds a threshold (e.g., is greater than a threshold of <NUM> combined misses) at box <NUM>. If not, the method <NUM> may proceed to handle the L2 cache request at box <NUM>. If the L1 miss counter exceeds the threshold at box <NUM>, the method <NUM> may proceed to determining if the code miss counter is greater than the data miss counter at box <NUM>. If so, the method <NUM> may proceed to enabling dynamic L2 partitioning at box <NUM>. Otherwise, the method <NUM> may proceed to disabling dynamic L2 partitioning at box <NUM>. After dynamic L2 partitioning is either enabled at box <NUM> or disabled at box <NUM>, the method <NUM> may proceed to halving both of the code miss and data miss counters, and setting the L1 miss counter to zero at box <NUM> before handling the L2 cache request at box <NUM>.

Some embodiments of the method <NUM> may further include handling a demand to a cache line at box 431as follows. The method <NUM> may proceed to incrementing the priority of the hit cache line at box <NUM> and, if dynamic L2 partitioning is disabled at box <NUM>, decrementing the priority of the remaining cache lines in the set at box <NUM>. If dynamic L2 partitioning is enabled at box <NUM>, the method <NUM> may proceed to determining if the demand access is for code at box <NUM> and, if so, decrementing the priority of the remaining cache lines in only the ways reserved for code at box <NUM>. Otherwise, the method <NUM> may proceed to decrementing the priority of the remaining cache lines in only the ways reserved for data at box <NUM>.

Some embodiments of the method <NUM> may further include replacing a cache line at box 451as follows. If dynamic L2 partitioning is disabled at box <NUM>, the method <NUM> may proceed to evicting the least priority line in the entire cache set at box <NUM>. If dynamic L2 partitioning is enabled at box <NUM>, the method <NUM> may proceed to determining if the new cache line is for code at box <NUM> and, if so, evicting the least priority line in the ways reserved for code at box <NUM>. Otherwise, the method <NUM> may proceed to evicting the least priority line in the ways reserved for data at box <NUM>.

With reference to <FIG>, an embodiment of a cache system <NUM> includes a L1 cache controller 512a coupled to a core cache <NUM> and a shared cache controller 512b coupled to the core cache <NUM> and a LLC <NUM>. The core cache <NUM> includes a L1 code cache 514a, a L1 data cache 514b, and a L2 cache 514c. For example, the L2 cache 514c receives requests from three sources including the L1 code cache 514a, the L1 data cache 514b, and L2 prefetchers. For large code footprint workloads, the L2 cache 514b receives more requests from the L1 code cache 514a as compared to the L1 data cache 514b. To detect a workload with a large code footprint, the L1 cache controller 512a tracks the number of requests from each L1 cache source (e.g., with a <NUM>-bit counter). After an epoch of, for example, <NUM> L2 requests from these caches, the number of requests from each cache source are compared. If more L1 code cache requests were received as compared to L1 data cache requests, the shared cache controller 512b enables dynamic partitioning of the L2 cache 514c. Otherwise, the shared cache controller 512b disables dynamic partitioning and keeps the L2 cache 514c as un-partitioned. In some embodiments, the L1 cache controller 512a halves the L1 request counters after every epoch to add hysteresis to the partitioning logic.

When dynamic partitioning is enabled, the shared cache controller 512b enforces partitioning of the L2 cache 514c by assigning separate ways to store code and data cache lines. An example L2 cache set contains <NUM> ways that are shared by both code and data cache lines. To enable partitioning, the shared cache controller 512b reserves the first M (e.g., M = <NUM> for this example) ways to store code cache lines and remaining <NUM>-M (e.g., <NUM> for this example) ways to store data cache lines. The shared cache controller 512b may achieve the partitioning by modifying the flows that change the priority of an L2 cache line.

For a demand hit to a cache line in the L2 cache 514c when partitioning is disabled, for example, the shared cache controller 512b increments the priority of the hit cache line and decrements the priority of the remaining <NUM> lines in the cache set. For a demand hit to a cache line in the L2 cache 514c when partitioning is enabled, for example, depending on whether the demand access is for code or data, the shared cache controller 512b decrements the priority of only the lines belonging to the access type's reserved ways (e.g., for data: the remaining <NUM> lines of the <NUM> ways for data; and for code: the remaining <NUM> lines of the <NUM> ways for code). To replace a cache line for an unpartitioned cache (e.g., when partitioning is disabled), on inserting a new cache line, for example, the shared cache controller 512b evicts the least priority line in the entire cache set. For a partitioned cache (e.g., when partitioning is enabled), depending on whether the access is for code or data, the shared cache controller 512b evicts the least priority line in the reserved ways that correspond to the access type (e.g., for data: the controller picks the least priority line in the <NUM> ways for data; and for code: the controller picks the least priority line the <NUM> ways for code).

In some embodiments of the cache system <NUM>, the information about whether an access is for code or data is made available at the time of inserting the access in a buffer that stores cache requests that are waiting for L2 arbitration. Accesses emanating from the L1 code cache 514a and L1 data cache 514a are tagged as code and data accesses, respectively. Additionally, prefetches triggered due to a cache access are tagged with the same category as the original access.

Embodiments of the ways partitioned between data and code may be considered as mutually exclusive because accesses tagged as code are inserted in the code ways and accesses tagged as data are inserted in the data ways. With respect to the content, however, some workloads may include self-modifying code such that the workload can modify code at run time and may use the same cache line as data (e.g., to modify code) and code (e.g., while executing instructions in newly generated code). Some embodiments may provide technology to handle workloads with self-modifying code. For a cache lookup for example, the shared cache controller 512b may keep the lookup logic for the L2 cache 514c unchanged. Accordingly, regardless of whether the cache access is for code or data, the shared cache controller 512b will lookup all <NUM> ways of the L2 cache 514c.

The shared cache controller 512b may detect an incorrectly assigned partition as follows. At the time of modifying code, the workloads treat constituent cache lines for updated code region as data (e.g., because update to such lines is through stores coming from the L1 data cache). Accordingly, the shared cache controller 512b inserts such lines into the reserved data ways of the L2 cache 514c. On accessing such cache lines for code, the shared cache controller 512b detects this anomaly of cache line placement (e.g., in data reserved ways instead of code reserved ways). The shared cache controller 512b does not increase the priority for such cache lines, which ensures that the line remains at a lower priority, and accordingly, the line will be evicted from the L2 cache 514c and may be inserted at a later time in the correct reserved way.

Advantageously, embodiments of the cache system <NUM> may involve little or no hardware overhead to increase the hit rate for the L2 cache 514c and to reduce or eliminate thrashing between code and data in the shared L2 cache 514c. The increased L2 hit rate also provides significant overall performance gains for workloads with large code footprints.

Those skilled in the art will appreciate that a wide variety of devices may benefit from the foregoing embodiments. The following exemplary core architectures, processors, and computer architectures are non-limiting examples of devices that may beneficially incorporate embodiments of the technology described herein.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units <NUM>/<NUM> and a shared L2 cache unit <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core, along with its connection to the on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to embodiments of the invention. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> and vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core is stored in its L2 cache subset <NUM> and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset <NUM> and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is <NUM>-bits wide per direction.

<FIG> is an expanded view of part of the processor core in <FIG> according to embodiments of the invention. <FIG> includes an L1 data cache 1006A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> is a <NUM>-wide vector processing unit (VPU) (see the <NUM>-wide ALU <NUM>), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 1022A-B, and replication with replication unit <NUM> on the memory input. Write mask registers <NUM> allow predicating resulting vector writes.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 1102A, a system agent <NUM>, a set of one or more bus controller units <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 1102A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 1102A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 1102A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 1102A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of respective caches 1104A-N within the cores 1102A-N, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit <NUM> interconnects the integrated graphics logic <NUM>, the set of shared cache units <NUM>, and the system agent unit <NUM>/integrated memory controller unit(s) <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 1102A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 1102A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1102A-N and the integrated graphics logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 1102A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1102A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM> and an interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> in order to avoid obscuring other aspects of <FIG>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 1102A-N and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using an x86 compiler <NUM> to generate x86 binary code <NUM> that may be natively executed by a processor with at least one x86 instruction set core <NUM>. The processor with at least one x86 instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler <NUM> represents a compiler that is operable to generate x86 binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one x86 instruction set core <NUM> (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter <NUM> is used to convert the x86 binary code <NUM> into code that may be natively executed by the processor without an x86 instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code <NUM>.

Techniques and architectures for instruction set architecture opcode parameterization are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

Claim 1:
An integrated circuit, comprising:
a core (<NUM>);
a first level core cache memory (<NUM>) coupled to the core (<NUM>);
a shared core cache memory (<NUM>) coupled to the core (<NUM>);
a first cache controller (114a) coupled to the core (<NUM>) and communicatively coupled to the first level core cache memory (<NUM>);
a second cache controller (114b) coupled to the core (<NUM>) and communicatively coupled to the shared core cache memory (<NUM>) ; and
circuitry (<NUM>) coupled to the core (<NUM>) and communicatively coupled to the first cache controller (<NUM>) and the second cache controller (114b) to:
determine if a workload has a large code footprint based on a number of first level code cache misses from the workload and a number of first level data cache misses from the workload, and, if so determined,
partition N ways of the shared core cache memory (<NUM>) into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero,
characterized in that:
determining if a workload has a large code footprint comprises:
counting the number of first level code cache misses from the workload;
counting the number of first level data cache misses from the workload; and
determining that the workload has the large code footprint if the counted number of first level code cache misses exceeds the counted number of first level data cache misses after a counted number of first level cache misses exceeds a threshold.