Patent Description:
Spread spectrum topology can be used to reduce emissions in analog mixed signals. In many instances, a high frequency domain is modulated, which can result in noise in the low frequency domain.

These and other matters have presented challenges to efficiencies of modulating digital clock signal implementations, for a variety of applications.

United States patent application publication number <CIT> discloses a semiconductor apparatus and radio circuit. The apparatus includes a signal source that outputs a signal at a predetermined frequency, a frequency divider that receives the output signal and is capable of switching the output signal to two or more frequency division ratios, thereby producing two lower frequency signals. A bandpass filter is used to attenuate noise. <CIT> discloses a spread spectrum frequency modulated oscillator circuit comprising a reference component such as a resistor, a voltage controlled oscillator and a first circuit coupled to the reference component and voltage controlled oscillator. A second circuit configured to supply a random signal to the oscillator that causes the frequency of the oscillator to dither. To cause the oscillator to exhibit random frequency modulation that is fast enough to reduce EMI but not too fast for controlled devices such as switching regulators to track.

According to the present invention there is defined an apparatus and a method as defined in the independent claims. Various example embodiments are directed to issues such as those addressed above and/or others which may become apparent from the following disclosure concerning independent modulation of a main clock signal for different frequency domains. In certain example embodiments, aspects of the present disclosure involve independent modulation of a digital clock signal for two or more different frequency domains using digital divider circuitry and modulation circuitry.

In a more specific example embodiment, an apparatus includes first circuitry and second circuitry. The apparatus employs circuitry that operates in response to digital clock signal circuitry. The first circuitry produces a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency digital clock signal characterized by a low frequency modulated by a first type of modulation. The second circuitry produces another low-frequency digital clock signal by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal, wherein the disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is (sufficiently) independent of the first type of modulation and by cancellation and/or blocking of the radiative noise interference manifested by the circuitry operating in response to digital clock signal circuitry (e.g., in the other low-frequency digital clock signal).

The first circuitry and the second circuitry can improve electromagnetic compatibility (EMC) in both high and low frequency domains (e.g., above and below <NUM>) by spreading dynamic current on both DC/DC switching and digital switching and thus reducing peak currents, thereby facilitating efficiency of clock modulation associated with both modulations of a main clock and of divided portion of the main clock. For example, the first circuitry and second circuitry use the main clock signal to produce the high-frequency digital clock signal and the other low-frequency digital clock signal having independent modulation schemes, such as providing independent clock modulation of the main clock. In a number of embodiments, the first circuitry includes a pseudo-random modulator and a frequency modulation (FM) oscillator that produce the high-frequency digital clock signal as a function of the pseudo-random modulator. The high-frequency digital clock signal can be produced as a function of pseudo-random frequency modulation and based on at least four to five percent of the average non-modulated frequency of the main clock and/or at least twelve to sixteen steps. In related or other embodiments the second circuitry includes a triangular modulator and frequency divider circuitry that produces the other low-frequency digital clock signal as a function of the disparate modulation signal.

In a number of specific embodiments, the apparatus further includes additional circuitry. For example, the apparatus includes the circuitry that operates in response to the digital clock signal circuitry. Additionally, the apparatus can further include a power circuit operating by a battery, wherein the power circuit contributes to the radiative noise interference. In various embodiments and/or in addition, the apparatus includes a third circuitry the produces an additional low-frequency digital clock signal by combining another disparate modulation signal and another feedback signal derived from the additional low-frequency digital clock signal. The other disparate modulation signal is characterized by modulating the other feedback signal via another type of modulation that is independent of the first type of modulation (and, optionally, of the second type of modulation) and by cancellation of the radiative noise interference in the additional lower-frequency digital clock signal as produced by the third circuitry.

Other specific example embodiments are direct to a method involving an apparatus employing circuitry operating in response to digital clock signal circuitry. An example method includes producing, via first circuitry of the apparatus, a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency signal characterized by a low frequency modulated by a first type of modulation. The method further includes producing, via second circuitry of the apparatus, another low-frequency digital clock signal by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal, wherein the disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is independent of the first type of modulation and by cancellation and/or blocking of the radiative noise interference manifested by the circuitry operating in response to the digital clock signal circuitry. As previously described, the other low-frequency digital clock signal is produced as a function of the disparate modulation signal, for example, by spreading dynamic current on both DC/DC switching and digital switching, thereby reducing peak currents and facilitating-efficiency of clock modulation associated with both modulations of main clock and of divided portion of the main clock.

In a number of specific embodiments, the method further includes producing, by a third circuitry of the apparatus, an additional low-frequency digital clock signal by combining another disparate modulation signal and another feedback signal derived from the additional low-frequency digital clock signal. The other disparate modulation signal is characterized by modulating the other feedback signal via another type of modulation that is independent of the first and second type of modulation and cancels and/or blocks the radiative noise interference in the additional low-frequency digital clock signal as produced by the third circuitry.

Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving apparatuses that differently modulate a main digital clock signal. In certain implementations, aspects of the present disclosure have been shown to be beneficial when used in the context of differently modulating a main digital clock signal between two or more different frequency domains. In some embodiments, electromagnetic compatibility (EMC) is improved in both the high and low frequency domain by spreading dynamic current on both direct current (DC)/DC switching and digital switching generated from the main digital clock signal. While not necessarily so limited, various aspects may be appreciated through the following discussion of non-limiting examples which use exemplary contexts.

In the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and/or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination.

Various apparatuses employ circuitry that operates in response to digital clock signal circuitry which can manifest radiate noise interference, such as logic circuitry. With improvements in logic circuitry, based on reduced power levels, higher operational speeds, and reduced real estate, it can be difficult to control and/or limit radiative noise interference that inherently gets into the logic circuitry via the digital clock signal and the interconnected DC supply busses. Spread spectrum topologies are sometimes used to reduce emissions in such logic circuitry, such as analog mixed signals. Such topologies can include modulation circuitry and oscillator circuitry used to modulate the clock signal for the high-frequency domain. For example, the modulation frequency can be efficient for <NUM> and above and can be higher than <NUM>, which is the resolution bandwidth of a receiver in the frequency band between <NUM> and <NUM> to the EMC standard. In such specific examples and assuming <NUM> modulation frequency to take into account process and temperature variation of the system oscillator, the low-frequency domain (e.g., around <NUM>) may not be modulated and can generate radiative noise interference. Apparatuses in accordance with the present disclosure block or cancel the radiative noise interference manifested by the circuitry via independent modulation of different frequency digital clock signals. The different modulations are independent of one another. For example, the apparatus modulates the main digital clock in the high frequency domain and uses digital divider circuitry to filter it. The apparatuses use further digital diverter circuitry to provide low frequency domain modulation of the main digital clock. Embodiments are not limited to two frequency domains, and can include additional modulation and domains. Such embodiments improve the efficiency of the clock modulation and optimize radiative noise interface by providing main clock modulation (and modulation of divided portions of the main clock with different patterns of modulation (e.g., the low frequency domain DC/DC digital clocks)).

In more specific embodiments, an apparatus includes first circuitry and second circuitry. The apparatus employs circuitry that operates in response to digital clock signal circuitry. The first circuitry and the second circuitry can improve EMC in both high and low frequency domains (e.g., above and below <NUM>), by spreading dynamic current on both DC/DC switching and digital switching and thus reducing peak currents, thereby facilitating efficiency of clock modulation associated with both modulations of main clock and of a divided portion of the main clock. For example, the first circuitry and second circuitry use the main clock signal to produce the high-frequency digital clock signal and the other low-frequency digital clock signal having independent modulation schemes.

The first circuitry produces a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency digital clock signal characterized by a low frequency modulated by a first type of modulation. In specific embodiments, the first circuitry includes a pseudo-random modulator and a frequency modulation (FM) oscillator that produce the high-frequency digital clock signal as a function of the pseudo-random modulator. For example, the high-frequency digital clock signal is produced as a function of pseudo-random frequency modulation and based on at least four to five percent of the average non-modulated frequency of the main clock and/or at least twelve to sixteen steps.

The second circuitry produces another low-frequency digital clock signal by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal. The disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is (sufficiently) independent of the first type of modulation and by cancellation and/or blocking of the radiative noise interference manifested by the circuitry operating in response to digital clock signal circuitry (e.g., in the other low-frequency digital clock signal). In various embodiments, the second circuitry includes a triangular modulator and frequency divider circuitry that produces the other low-frequency digital clock signal as a function of the disparate modulation signal.

In a number of specific embodiments, the apparatus further includes additional circuitry. For example, the apparatus includes the circuitry that operates in response to the digital clock signal circuitry. Additionally, the apparatus can further include a power circuit operating by a battery, wherein the power circuit contributes to the radiative noise interference. In various specific embodiments and/or in addition, the apparatus includes a third circuitry the produces an additional low-frequency digital clock signal by combining another disparate modulation signal and another feedback signal derived from the additional low-frequency digital clock signal. The other disparate modulation signal is characterized by modulating the other feedback signal via another type of modulation that is independent of the first type of modulation and by cancellation of the radiative noise interference in the other lower-frequency digital clock signal as produced by the third circuitry.

Other specific embodiments are directed to methods of using the above-described apparatus, such as methods involving an apparatus employing circuitry operating in response to digital clock signal circuitry.

Turning now to the figures, <FIG> illustrates an example apparatus, in accordance with the present disclosure. Although not illustrated, the apparatus can employ circuitry operating in response to digital clock signal circuitry which can manifest radiative noise interference. In accordance with various embodiments, the apparatus blocks or cancels the radiative noise interference manifested by the circuitry via independent modulation of different frequency digital clock signals. Although not illustrated, the apparatus can further include a power circuit operating by a battery. The power circuit can contribute to the radiative noise interference.

As illustrated, the apparatus includes first circuitry <NUM> and second circuitry <NUM> that provide independent clock modulation of a main clock (e.g., clock signal <NUM> at <NUM>). The first and second circuitry <NUM>, <NUM> use the (same) main clock signal to produce a high-frequency digital clock signal and a modulated low-frequency digital clock signal, as well as another modulated low-frequency digital clock with the modulated digital clock signals having independent (e.g., separate) modulation schemes. In various embodiments, the first circuitry <NUM> and the second circuitry <NUM> improve EMC in both high and low frequency domains (e.g., above and below <NUM>), by spreading dynamic current on both DC/DC switching and digital switching, thus reducing peak currents, and thereby facilitating efficiency of clock modulation associated with both modulations of main clock (e.g., system clock <NUM> and of divided portion of this main clock (e.g., DC/DC clock <NUM>)).

The first circuitry <NUM> produces a high-frequency digital clock signal, e.g., system clock <NUM> characterized by a high frequency (e.g., <NUM>) which carries radiative noise interference and by a modulated low-frequency digital clock signal <NUM> characterized by a low frequency (e.g., <NUM>) modulated by a first type of modulation. In various embodiments, the first type of modulation includes a pseudo-random modulation. An example of a first type of modulation is illustrated by the graph <NUM>. In specific embodiments, the first circuitry <NUM> includes a pseudo-random modulator <NUM> and a frequency modulation (FM) oscillator <NUM> that produce the high-frequency digital clock signal (e.g., system clock <NUM> at <NUM>) as a function of the pseudo-random modulator <NUM>. In further specific embodiments, the first circuitry <NUM> further includes a frequency divider circuit <NUM> that is arranged with the pseudo-random modulator <NUM> to provide the modulated low-frequency digital clock signal <NUM> characterized by the low frequency (e.g., <NUM>). In more specific embodiments and/or in addition, the high-frequency clock digital clock signal (e.g., system clock <NUM>) and/or the modulated low-frequency digital clock signal <NUM> is produced as a function of pseudo-random frequency modulation and based on an at least sixteen steps and/or five percent of the average non-modulated frequency of the clock signal <NUM> (e.g., <NUM>). Although embodiments are not so limited and can include fewer than sixteen steps, such as twelve steps, and/or different percentages of the average non-modulated frequency of the clock signal <NUM>, such as four percent.

The second circuitry <NUM> produces another low-frequency digital clock signal (e.g., DC/DC clock <NUM> at the output port that is at <NUM>) by combining a disparate modulation signal <NUM> (e.g., output of the triangular modulator <NUM> as illustrated by the graph <NUM>) and a feedback signal derived from the other low-frequency digital clock signal (e.g., DC/DC clock <NUM>). In specific embodiments, the disparate modulation signal <NUM> (e.g., at <NUM>) is characterized by modulating the feedback signal via a second type of modulation that is (sufficiently) independent of the first type of modulation to cancel and/or block the radiative noise interference manifested by the circuitry operating in response to digital clock signal circuitry (e.g., in the other low-frequency digital clock signal or the DC/DC clock <NUM> at <NUM> at the output port as produced by the second circuitry <NUM>). In specific embodiments, the second type of modulation is a triangular modulation. An example of the second type of modulation is illustrated by the graph <NUM>. In further specific embodiments, the second circuitry <NUM> includes a triangular modulator <NUM> and frequency divider circuitry <NUM>, <NUM> that produce the other low-frequency digital clock signal (e.g., the DC/DC clock <NUM> at <NUM>) as a function of the disparate modulation signal <NUM> (e.g., at <NUM> as output by the triangular modulator <NUM>). In specific embodiments and/or in addition, the other modulated low-frequency digital clock signal (e.g., DC/DC clock <NUM>) are produced as a function of triangular frequency modulation and based on an at least sixteen steps and/or four percent of the average non-modulated frequency of the clock signal <NUM> (e.g., <NUM>). Although embodiments are not so limited and can include different steps, such as fewer or more than sixteen steps, and different percentages of the average non-modulated frequency of the clock signal <NUM>. A specific example of the second type of modulation is illustrated by the graph <NUM>.

In accordance with various embodiments, cancellation and/or blocking of radiative noise interference (e.g., electromagnetic interference (EMI)) at the clock used to drive the logic circuitry (using the related DC power supplies) can be advantageous because: (i) logic circuits can increase in terms of operational switching speed which is controlled by the clock signals including reduction in EMI for DC/DC clocks running in the range of hundreds of kHz (e.g., <NUM> DC/DC clock <NUM>) and well into higher frequencies which get close to and/or include the high-frequency digital clock signal in the Mhz range (e.g., <NUM>/system clock <NUM>); (ii) operational supply voltages for the logic circuits can decrease (e.g., below 5v and <NUM>. 5v and lower); and (iii) logic circuits can be implemented in smaller areas which make isolation of their digital (switching) signals more difficult (e.g., FET and technologies are requiring reduced dielectric separation areas). Accordingly, as described above, the apparatus independently controls modulation of the clock signal to produce a high-frequency digital clock signal (e.g., system clock <NUM> at <NUM>) characterized by a high frequency which carries radiative noise interference and a modulated low-frequency digital clock signal characterized by a low frequency (e.g., <NUM>) and another modulated low-frequency digital clock signal (e.g., DC/DC clock <NUM> at <NUM>). The low-frequency digital clock signal characterized being modulated by a first type of modulation (e.g., pseudo-random) and the other low-frequency digital clock signal (e.g., DC/DC clock <NUM> at <NUM>) being modulated by a second type of modulation (e.g., triangular).

In various embodiments, the modulation of the other low-frequency digital clock signal (e.g., the DC/DC clock <NUM>) is selectively enabled, as illustrated by the "enabled" signal input to the triangular modulator <NUM>. For one or more embodiments, it may be beneficial to not cancel or block the radiative noise interference and/or to otherwise control when modulation of the other low-frequency digital clock signal occurs. Although embodiments are not so limited, and in various embodiments, the triangular modulator <NUM> is always enabled such as by the enabled signal input.

<FIG> illustrate an example apparatus and resulting modulation of a digital clock signal, in accordance with the present disclosure. Various embodiments are not limited to first and second circuitry, such as the first and second circuitries <NUM>, <NUM> illustrated by <FIG>. <FIG> illustrate an example apparatus having first circuitry <NUM>, second circuitry <NUM>, and third circuitry <NUM>. Similarly to <FIG>, the apparatus employs circuitry operating in response to digital clock signal circuitry which can manifest radiative noise interference. The apparatus blocks or cancels the radiative noise interference manifested by the circuitry via independent modulation of different frequency digital clock signals. Although not illustrated, the apparatus can further include a power circuit operating by a battery, which can contribute to the radiative noise interference.

Similarly to the apparatus illustrated by <FIG>, the first circuitry <NUM> produces a high-frequency digital clock signal <NUM>, e.g., system clock, characterized by a high frequency (e.g., <NUM>) which carries radiative noise interference and by a modulated low-frequency digital clock signal <NUM> characterized by a low frequency (e.g., <NUM>) modulated by a first type of modulation. In a number of embodiments, the first type of modulation includes a pseudo-random modulation. An example of a first type of modulation is illustrated by <FIG>. In related and more specific embodiments, the first circuitry <NUM> includes a pseudo-random modulator <NUM> and an FM oscillator <NUM> that produces the high-frequency digital clock signal <NUM> (e.g., system clock at <NUM> FM) as a function of the pseudo-random modulator <NUM>. The first circuitry <NUM> can further include a frequency divider circuit <NUM> that is arranged with the pseudo-random modulator <NUM> to provide the modulated low-frequency digital clock signal <NUM> characterized by the low frequency (e.g., <NUM>). For example, the high-frequency digital clock signal <NUM> and/or the modulated low-frequency digital clock signal <NUM> are produced as a function of pseudo-random frequency modulation and based on an at least twelve steps and/or four percent of the average non-modulated frequency of the clock signal <NUM> (e.g., <NUM>). Although embodiments are not so limited and can include more or fewer than twelve steps, such as ten to twenty steps, and/or different percentages of the average non-modulated frequency of the clock signal <NUM>, such as five percent.

The second circuitry <NUM>, as previously described in connection with <FIG>, produces another low-frequency digital clock signal (e.g., slow DC/DC clock <NUM> that is at <NUM>) by combining a disparate modulation signal <NUM> (e.g., output clock of the triangular modulator <NUM> illustrated by the graph of <FIG>) and a feedback signal derived from the other low-frequency digital clock signal. The disparate modulation signal <NUM> (e.g., output clock at <NUM>) is characterized by modulating the feedback signal via a second type of modulation that is (sufficiently) independent of the first type of modulation to cancel and/or block the radiative noise interference manifested by the circuitry operating in response to digital clock signal circuitry. In various embodiments, the second type of modulation includes a triangular modulation. An example of the second type of modulation is illustrated by the graph of <FIG>. In more specific embodiments, the second circuitry <NUM> includes a triangular modulator <NUM> and frequency divider circuitry <NUM>, <NUM> that produce the other low-frequency digital clock signal (e.g., the slow DC/DC clock <NUM> at <NUM>) as a function of the disparate modulation signal <NUM> (e.g., at <NUM> as output by the triangular modulator <NUM>). The other modulated low-frequency digital clock signal (e.g., the slow DC/DC clock <NUM>) is produced as a function of triangular frequency modulation and based on an at least sixteen steps and/or four percent of the average non-modulated frequency of the clock signal <NUM> (e.g., <NUM>). Although embodiments are not so limited and can include different steps, such as fewer or more than sixteen steps, and different percentages of the average non-modulated frequency of the clock signal <NUM>.

The third circuitry <NUM> produces an additional low-frequency digital clock signal (e.g., fast DC/DC clock <NUM> at <NUM>) by combining another disparate modulation signal <NUM> (e.g., output clock signal of the other triangular modulator <NUM> illustrated by the graph of <FIG>) and another feedback signal derived from the additional low-frequency digital clock signal. The other disparate modulation signal <NUM> is characterized by modulating the other feedback signal via another type of modulation (e.g., a third type of modulation) that is independent of the first type of modulation (and optionally, the second type of modulation) and provides additional cancellation and/or blocking of the radiative noise interference in the additional low-frequency digital clock signal (e.g., the fast DC/DC clock <NUM> at <NUM>) as produced by the third circuitry <NUM>.

In a number of embodiments, the third type of modulation includes a triangular FM modulation. An example of the third type of modulation is illustrated by the graph of <FIG>. For example, the third circuitry <NUM> includes another triangular modulator <NUM> and other frequency divider circuitry <NUM>, <NUM> that produces the other low-frequency digital clock signal (e.g., the fast DC/DC clock <NUM> at <NUM>) as a function of the disparate modulation signal low frequency <NUM> (e.g., at <NUM> as output by the other triangular modulator <NUM>). The additional modulated low-frequency signal (e.g., the fast DC/DC clock <NUM>) is produced as a function of triangular frequency modulation and based on an at least twenty steps and/or five percent of the average non-modulated frequency of the clock signal <NUM> (e.g., <NUM>). Although embodiments are not so limited and can include different steps, such as fewer or more than twenty steps, and different percentages of the average non-modulated frequency of the clock signal <NUM>.

Similarly to the apparatus illustrated by <FIG>, the modulation of the other low-frequency digital clock signal (e.g., the slow DC/DC clock <NUM>) and/or of the additional low-frequency digital clock signal (e.g., the fast DC/DC clock <NUM>) can be selectively enabled (as illustrated by the "enabled" signal input to the triangular modulators <NUM>, <NUM> of the second and third circuitries <NUM>, <NUM>) such as when the apparatus is in a low power mode. Although embodiments are not so limited, and in various embodiments, one or more of the modulators <NUM>, <NUM> can always enabled, such as by the enabled signal input.

<FIG> illustrates a specific example of an apparatus employing circuitry that operates in response to digital clock signal circuitry, in accordance with the present disclosure. More specifically, the apparatus illustrated by <FIG> can be used to provide the illustrated cancellation and/or blocking of radiative noise interference, as illustrated further by <FIG>.

In various specific embodiments, a battery line <NUM> is separated from Vsup (supply of the integrated circuit) by a <NUM> uH inductor <NUM>. Vsup is supplying a 5V Low Drop Out (LDO) regulator <NUM> and high side switch <NUM>. The 5V LDO regulator <NUM> is supplying a high side driver <NUM> and <NUM>. 6V LDO <NUM>. The <NUM> V LDO <NUM> is supplying digital part <NUM> (e.g., one relatively large digital clock buffer plus twenty flip flops switched at the system clock frequency) and Digital Control Unit <NUM> (e.g., digital control frequency divider and modulator) that divides and modulates the low frequency clock as used by the high side driver <NUM> (Pulse Width Modulation with <NUM>% duty cycle). As also shown, receiver circuitry <NUM> is coupled to Vsup.

<FIG> illustrate examples of cancellation or blocking of radiative noise interference by apparatuses, in accordance with the present disclosure. More specifically, different example circuits are compared to illustrate resulting battery spectrum analysis. <FIG> illustrate the impact on the battery spectrum caused by noise propagation through supply lines. For example, the apparatus illustrated by <FIG> can be generated four times and implemented differently to observed noise propagation through supply lines and the impact on the battery spectrum, referred to as cases. The first case (e.g., case <NUM>), shown in each of <FIG>, illustrates example impacts on the battery spectrum when no FM is performed at <NUM> or <NUM>. The second case (e.g., case <NUM>), shown in <FIG>, illustrates an example impact on the battery spectrum when FM is performed at <NUM> and no FM is performed at <NUM>. The third case (e.g., case <NUM>), shown in <FIG>, illustrates an example impact on the battery spectrum when no FM is performed at <NUM> and FM is performed at <NUM> in accordance with various apparatuses of the present disclosure. The fourth case (e.g., case <NUM>), shown in <FIG>, illustrates an example impact on the battery spectrum when FM is performed at <NUM> and FM is performed at <NUM> in accordance with various apparatuses of the present disclosure.

The above-described apparatuses, as illustrated by <FIG>, <FIG>, and <FIG>, can be used to implement a variety of methods involving an apparatus employing circuitry operating in response to digital clock signal circuitry. An example method includes producing, via first circuitry of the apparatus, a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency digital clock signal characterized by a low frequency modulated by a first type of modulation (e.g., pseudo-random FM). The method further includes producing, via second circuitry of the apparatus, another low-frequency digital clock signal (e.g., DC/DC clock at <NUM>) by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal, wherein the disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is (sufficiently) independent of the first type of modulation and by cancellation/blocking of the radiative noise interference manifested by the circuitry operating in response to the digital clock signal circuitry. As previously described, the other low-frequency digital clock signal is produced as a function of the disparate modulation signal. In a number of specific embodiments, the method further includes producing, by a third circuitry of the apparatus, an additional low-frequency digital clock signal by combining another disparate modulation signal and another feedback signal derived from the additional low-frequency digital clock signal. The other disparate modulation signal is characterized by modulating the other feedback signal via another type of modulation (e.g., a third type of modulation) that is independent of the first and second type of modulation and cancels and/or blocks the radiative noise interference in the additional low-frequency digital clock signal as produced by the third circuitry.

Terms to exemplify orientation, such as upper/lower, left/right, top/bottom and above/below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented different from the orientation shown in the figures. Thus, the terms should not be construed in a limiting manner.

The skilled artisan would recognize that various terminology as used in the Specification (including claims) connote a plain meaning in the art unless otherwise indicated. As examples, the Specification describes and/or illustrates aspects useful for implementing the claimed disclosure by way of various circuits or circuitry which may be illustrated as or using terms such as blocks, modules, device, system, unit, controller, and/or other circuit-type depictions (e.g., reference numerals <NUM> and <NUM> of <FIG> depict a block/module as described herein). Such circuits or circuitry are used together with other elements to exemplify how certain embodiments may be carried out in the form or structures, steps, functions, operations, activities, etc. For example, in certain of the above-discussed embodiments, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged for implementing these operations/activities, as may be carried out in the approaches shown in <FIG> and <FIG>. In certain embodiments, such a programmable circuit is one or more computer circuits, including memory circuitry for storing and accessing a program to be executed as a set (or sets) of instructions (and/or to be used as configuration data to define how the programmable circuit is to perform), and an algorithm or process as described above is used by the programmable circuit to perform the related steps, functions, operations, activities, etc. Depending on the application, the instructions (and/or configuration data) can be configured for implementation in logic circuitry, with the instructions (whether characterized in the form of object code, firmware or software) stored in and accessible from a memory (circuit).

Claim 1:
An apparatus employing circuitry operating in response to digital clock signal circuitry, the apparatus comprising:
first circuitry (<NUM>), including a pseudo-random modulator (<NUM>) providing a first type of modulation, and a frequency modulation, FM, oscillator (<NUM>), the pseudo-random modulator and FM oscillator together configured and arranged to produce a high-frequency digital clock signal (<NUM>) having a high frequency which carries radiative noise interference, the first circuitry further including a frequency divider (<NUM>) operable on the high-frequency digital clock signal (<NUM>) and configured and arranged to produce a modulated low-frequency digital clock signal (<NUM>) having a low frequency modulated by the first type of modulation; and
second circuitry (<NUM>) including a triangular modulator (<NUM>) providing a second modulation signal (<NUM>), that is independent of the first type of modulation, and frequency divider circuitry (<NUM>) configured to frequency-divide the high-frequency digital clock signal (<NUM>), the triangular modulator and the frequency divider circuitry together configured and arranged to produce an other low-frequency digital clock signal (<NUM>) as a function of the second modulation signal (<NUM>), by combining the second modulation signal (<NUM>) and a feedback signal derived from the other low-frequency digital clock signal (<NUM>), wherein a further divider (<NUM>) is configured to frequency-divide the other low-frequency digital clock signal (<NUM>) to provide the feedback signal.