Patent Description:
In a system which includes a server <NUM> and a client device <NUM> that receives audio data from the server <NUM> as shown in <FIG>, measures to synchronize the audio data between the server <NUM> and the client device <NUM> have been taken. In synchronizing the audio data between the server <NUM> and the client device <NUM>, it is important to detect output timing of the audio data from the client device <NUM>, or a delay within the client device <NUM>. That is, in the system as shown in <FIG>, a delay occurs from a receipt of the audio data by the client device <NUM> (i.e., writing of the audio data to a buffer memory) to the outputting of the audio data by the client device <NUM>. This delay is mainly caused by software processing in the client device <NUM>, and thus the delay time corresponds to time required for the processing by a control unit <NUM> such as CPU (a central control unit) at the client device <NUM>. This delay time may be estimated. However, it is difficult to estimate or calculate the delay time precisely. Thus, to address this issue, it is necessary to accurately detect the delay time within the client device or detect the accurate output time of the audio data from the client device.

A delay also occurs at a DAC (Digital Analog Converter) <NUM>, which receives the audio data and the audio clock from the control unit <NUM> and outputs the processed audio data to a speaker <NUM>. The delay at the DAC <NUM> depends on the specific hardware of the DAC <NUM>, and thus the delay time is generally constant and fixed. Thus, it is more important to address the delay at the client device <NUM>.

In addition, each of the server <NUM> and the client device <NUM> generates a respective audio clock, and plays back the audio data based on the respective audio clock. Thus, when there is a phase difference between the audio clock of the server <NUM> and the audio clock of the client device <NUM>, a time lag occurs between the playback by the server <NUM> and the playback by the client device <NUM>.

Prior attempts disclose steps to synchronize the audio data between two or more devices. For example, <CIT> discloses that a server calculates a number of clock pulses of a server clock signal and sends the calculated number of the clock pulses to a client device. The client device also calculates a number of clock pulses of a client clock signal, and compares the received number of the clock pulses of the server clock signal and the calculated number of the clock pulses of the client clock signal. Then, the client device adjusts the frequency of the client clock signal based on the results of the comparison.

In addition, <CIT> discloses that the client device adjusts a frequency divider based on a difference between time T_Time, when the server transmits an audio frame to the client device, and time R_Time, when the client device receives it. In addition, the <CIT> publication discloses adjusting the frequency of the audio clock based on the difference between time P_ Time, attached to the audio data, and the time R_Time, when the client device receives it.

Document <CIT> discloses a system for clock synchronization that can be used in an audio system. Document <CIT> discloses an improved audio clock regenerator with a precise tracking mechanism. Document <CIT> discloses how to synchronize the transmission and reception of media streams over a network. Document <CIT> discloses clock compensation techniques for audio decoding. Document <CIT> discloses a packet receiving apparatus that has a plurality of receiving buffers to receive packets from a plurality of transmitting nodes located on a network. Document <CIT> discloses an analogue blender control arrangement for use between a power supply and a load. Document <CIT> discloses an automatic telephone answering machine. Document <CIT> discloses a sound field adjustment filter. Document <CIT> discloses a fast-locking phase locked loop.

An object of the present application is to provide an audio device, where the precise output time of the audio data is detected and the audio data is adjusted based on the detected output time, thereby synchronizing the start of the playback of the audio data. Another object is to provide an audio device, where a timing of an outputted audio clock is constantly detected and a speed of the audio clock is adjusted based on the detected timing, thereby eliminating the phase difference between a time stamp attached to the audio data and the audio clock within a predetermined period after the audio clock is initially output. Another object is to provide an edge detection mechanism which measures an edge time of data, thereby ensuring an accurate detection of the output time by the audio device and thus achieving the above results in the client device. Another object is to provide an audio device where the server is not required to take any measures to synchronize the server and the client device.

To achieve these objects, one aspect of the invention relates to an audio device with the features of claim <NUM>.

Other objects and aspects of the invention will be understood by the detailed description of the invention.

<FIG> shows an overall configuration of the system. A server <NUM> transmits audio data and a time stamp attached to the audio data to a client device <NUM> through a communication network <NUM> (either a wireless network or a wired network). The client device <NUM> receives the audio data and the time stamp attached to the audio data through a network interface <NUM>, and modifies the audio data so that output time of the audio data is synchronized with the server <NUM>. The client device <NUM> also generates an audio clock which indicates a timing of the playback of the audio data. The client device <NUM> changes a speed of the audio clock so that the phase difference between the time stamp and the audio clock is eliminated. The details of these processes will be explained later. The audio clock and the processed audio data are transmitted to a Digital Analog Converter (DAC) <NUM> through an audio interface <NUM>. The DAC <NUM> converts the received audio data into an analog audio signal with a timing indicated by the audio clock. After the audio data is processed at the DAC <NUM>, the audio signal is sent to a speaker (not shown) for playback. Further, in addition to outputting the audio data to the client device <NUM>, the server <NUM> also outputs the audio data for the playback.

As shown in <FIG>, the client device <NUM> includes one or more control unit <NUM> (e.g., CPU: Central Processing Unit) and a memory <NUM> such as ROM and RAM, where programs and necessary data are stored. The control unit <NUM> performs the functions of the client device <NUM> by executing the program stored in the memory <NUM>. For example, the control unit <NUM> includes an edge detection module <NUM>, which detects an edge time of the pulse data, which is output prior to the audio data, and also detects an edge time of the audio clock. The control unit <NUM> also includes a Phase Locked Loop (PLL) <NUM>, which generates an audio clock and adjusts a speed of the audio clock. In addition, the control unit <NUM> includes a clock <NUM> which is used for detecting the edge time of the audio clock and the edge time of pulse data. The clock <NUM> is different from a clock used for the overall system. The audio data is processed in view of the detection results of the edge detection module <NUM> at the "Audio data adjustment" section, as shown in <FIG>. The details of the functions of the control unit <NUM> will be described later.

The server <NUM> has a similar hardware structure as the client device <NUM>. The clock of the server <NUM> and the clock <NUM> of the client device <NUM> have common time information, and the clock of the server <NUM> and the clock <NUM> of the client device <NUM> are adjusted so that both clocks indicate same time. For example, the server <NUM> periodically sends a synchronizing signal, which includes time information, to the client device <NUM>. Then, the clock <NUM> in the client device <NUM> is adjusted based on the time information included in the synchronization signal.

The control unit <NUM> is not limited to the CPU, and a processor or a microcomputer may be used as the control unit <NUM>.

In this disclosure, the edge detection module <NUM> and the PLL <NUM> perform important functions and will be explained below.

The edge detection module <NUM> constantly monitors an amplitude of the data signal, and detects a point where the amplitude of the data signal changes from zero to a predetermined value (e.g., from <NUM> to +<NUM>). Then, the edge detection module <NUM> determines that the point where the amplitude of the data increased by the predetermined value is an edge. Here, as an example in this disclosure, the predetermined value is not zero. Thus, for example, in <FIG>, the edge detection module <NUM> determines that point A is an edge. Then, by referring to the clock <NUM>, the edge detection module <NUM> detects a time of point A (in other words, detecting an edge time of the pulse data Dp).

Thus, in this disclosure, by using this function, the edge detection module <NUM> detects (i) an edge of the pulse data, where the pulse data is used to determine a cueing position of the audio data (<FIG> shows one example of the pulse data Dp). Then, by referring to the clock <NUM>, the edge detection module <NUM> determines an edge time of the pulse data. The edge detection module <NUM> also detects (ii) an edge of the audio clock, which is generated in the client device <NUM>, and then detects an edge time of the audio clock by referring to the clock <NUM> (<FIG> shows one example of the audio clock Ca). The detected edge time of the audio clock and the time stamp attached to the audio data are used for determining a phase difference between the time stamp attached to the audio data and the audio clock, which will be explained in detail later.

The edge detection module <NUM> can detect a time of each edge when the data signal has a plurality of edges. Further, the edge detection module <NUM> also can detect the edge time every predetermined interval. For example, as shown in <FIG>, when the audio clock Ca has a frequency of <NUM>, the edge detection module <NUM> can detect the edge time every <NUM> edges. Thus, in <FIG>, the edge detection module <NUM> detects T1 and T2.

The edge detection <NUM> module does not necessarily have to be installed in the control unit <NUM> such as the CPU, and the client device <NUM> may implement the edge detection module <NUM> separately from the control unit <NUM>. <FIG> shows one example where the edge detection module <NUM> is separately formed from the CPU <NUM>, which works as the control unit. As shown in <FIG>, the edge detection module <NUM> detects the edge of the pulse data and the edge of the audio clock, and then by referring to the clock <NUM>, the edge detection module <NUM> detects the edge time of the audio clock and the edge time of the pulse data. Then, the detected results such as the edge times are sent to a register. The CPU <NUM> controls the edge detection module <NUM> and reads out the detected results (i.e., the edge times) through the register. When the edge detection module <NUM> is formed separately from the CPU <NUM> as shown in <FIG>, the edge detection module <NUM> may be connected to the CPU of the existing device. Thus, it becomes easier to form the client device <NUM> with the edge detection function by using the existing client device. Further, the central unit <NUM> may have two CPUs, one of the two CPUs having the edge detection module <NUM> (or an edge detection function) and the other CPU having the PLL <NUM>. The advantages discussed above (i.e., forming the client device <NUM> with the edge detection function by using the existing client device) also apply to this embodiment. The processor or the microcomputer may be used as the control unit instead of the CPU.

The clock <NUM> is used when detecting the edge time of the audio clock and the edge time of the pulse data, and is different from a clock used for the overall system. Each client device <NUM> has the respective clock <NUM>. The clock <NUM> may also be implemented outside of the edge detection module <NUM>.

A Phase-Locked-Loop (PLL) <NUM> has a function which controls a speed (in other words, a frequency) of the audio clock, and thus generates a changeable audio clock. That is, the PLL <NUM> generates and outputs the audio clock (e.g., <NUM>,<NUM>,<NUM>,<NUM>,<NUM>,<NUM>,<NUM>,<NUM>. ) which is timing information of the audio data. <FIG> shows one example of the audio clock Ca. The audio clock Ca has a predetermined frequency (e.g., <NUM>). Then, when there is the phase deference between the time stamp attached to the audio data and edge time (e.g., T1) of the audio clock Ca, the PLL adjusts the speed (in other words, the frequency) of the audio clock so that the edge time of the audio clock synchronizes with the time stamp of the audio data within a predetermined period. Here, as discussed above, the edge detection module <NUM> detects the edge time (e.g., T1) of the audio clock Ca and the time stamp attached to the audio data.

In this disclosure, the synchronization of the playback of the audio data between the server <NUM> and the client device <NUM> is performed in the following two aspects: (i) a synchronization of the output time of the audio data, thereby synchronizing the start of the playback between the server <NUM> and the client device <NUM>; and (ii) deleting the phase difference between the audio data from the server <NUM> and the adjusted audio data by the client device <NUM> so that the sound may be synchronously played within a predetermined time. The synchronization of these aspects between a plurality of the client devices <NUM> can be also achieved.

<FIG> show an example of the synchronization in this disclosure. In the synchronization of the output time of the audio data, a timing of the playback of the audio data in the client device <NUM> is adjusted so that the client device <NUM> outputs the audio data for the playback at the same time as the server <NUM> outputs the audio data for the playback, thereby the playbacks of the audio data by the server <NUM> and the client device <NUM> start at the same time (t=t<NUM>), as shown in <FIG> shows that the start of the playback of the audio data by the server <NUM> is at t<NUM>, while <FIG> shows that the client device <NUM> starts the playback of the audio data at t<NUM>.

In addition, because each of the server <NUM> and the client device <NUM> generates a respective audio clock, a phase difference is likely to occur between the audio clock of the server <NUM> and the audio clock of the client device <NUM>. Thus, in the production of the sound at the same timing (in other words, eliminating the phase difference), the speed of the audio clock transmitted from the client device <NUM> is controlled so that the phase difference between the time stamp attached to the audio data and the edge time of the audio clock is eliminated within a predetermined time, thereby the server <NUM> and the client device <NUM> produce the same sound within the predetermined period (e.g., t= tn) as shown in <FIG>.

Next, the steps to synchronize the output time of the audio data (i.e., synchronizing the starting time of the playback of the audio data) between the server <NUM> and the client device <NUM> and the steps to eliminating the phase difference between the server <NUM> and the client device <NUM> will be explained.

<FIG> shows steps of synchronizing an output time of the audio data between the server <NUM> and the client device <NUM> according to a possible embodiment of the present invention. The steps show how the received audio data is modified so that the client device <NUM> outputs the audio data at the same time with the server <NUM> (or the synchronization occurs at the time when the client device <NUM> starts outputting the audio data), thereby synchronizing the start time of the playback of the audio data between the server <NUM> and the client device <NUM>. In this embodiment, it is assumed that the CPU <NUM> performs the steps as the control unit by executing the program stored in the memory <NUM>. The steps proceed as follows.

At step <NUM>, the server <NUM> transmits the audio data Da, where a time stamp Ts is attached. At step <NUM>, the client device <NUM> receives the audio data Da with the time stamp Ts transmitted from the server <NUM> (see "Requested data timing" of <FIG>).

At step <NUM>, once the client device <NUM> receives the audio data Da which has the time stamp Ts, the client device <NUM> outputs pulse data Dp (<NUM>,<NUM>,<NUM>,<NUM>. ), as shown in <FIG>. The pulse data Dp has a predetermined length Tp with a starting point A and an end point B. The pulse data Dp is used to determine the output time of the audio data from the client device <NUM>, which will be discussed later. The length Tp of the pulse data Dp is determined based on the time stamp of the past audio data. One example of the length Tp of the pulse data Dp is <NUM> msec (millisecond). However, the length Tp of the pulse data Dp is not limited to this length, and the pulse data Dp may have any length as long as it performs its intended purpose. The pulse data Dp is stored in the memory <NUM> and is output once the client device <NUM> receives the audio data Da having the time stamp Ts from the server <NUM>.

As shown in <FIG> (see also <FIG>), at the starting point A, an amplitude of the pulse data Dp increases from <NUM> to +<NUM> (in other words, the amplitude increases by +<NUM>). Thus, at step <NUM>, the edge detecting module <NUM> determines that the starting point A of the pulse data Dp is an edge, and thus detects edge time Td of the pulse data Dp by referring to the clock <NUM>. The edge time Td is a start time of the pulse data Dp. This step is repeated until the edge time Td is detected. Once the edge time Td is detected, the process proceeds to step <NUM>.

At step <NUM>, the CPU <NUM> compares the time stamp Ts attached to the audio data Da and (Td+Tp), and determines whether Ts < (Td+Tp) or not. Here, (Td+Tp) is time of the end point B of the pulse data Dp. Thus, (Td+Tp) is the end time of the pulse data Dp. Thus, in this step <NUM>, it is determined whether the time stamp Ts attached to the audio data is earlier than the end time (Td+Tp) of the pulse data Dp or not. The end time (Td+Tp) of the pulse data Dp is calculated by adding the predetermined length Tp to the start time Td (=Td+Tp). The end time (Td+Tp) of the pulse data Dp is used to determine the output time of the audio data, as explained below.

At step <NUM>, when Ts < (Td+Tp), the CPU <NUM> cuts the audio data for an amount corresponding to the period of [(Td+Tp) -Ts]. Here, Ts < (Td+Tp) means that the time stamp Ts attached to the audio data is earlier than the end time (Td+Tp) of the pulse data Dp, as shown in <FIG>.

<FIG> shows how to adjust the audio data in step <NUM>. <FIG> shows the audio data Da (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) which the client device <NUM> receives (see "Requested data timing"), and the audio data Da (a5, a6, a7, a8, a9, a10, a11) and the pulse data Dp, which the client device <NUM> outputs (see "Output data"). These data are shown in line with time (t) of the clock <NUM>. The time stamp Ts, which is attached to the audio data Da (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) indicates the requested timing of the playback of the audio data Da. As shown in <FIG>, the time stamp Ts is earlier than the end time (Td+Tp) of the pulse data Dp, and the audio data Da of a0, a1, a2, a3, a4 corresponds to [(Td+Tp) -Ts]. Thus, the audio data Da of a0, a1, a2, a3, a4 is cut, and the audio data Da of a5, a6, a7, a8, a9, a10, a11 is output after the pulse data Dp (see "Output data"). By cutting a0, a1, a2, a3, a4 (which corresponds to the period of [(Td+Tp) -Ts]), the output time of the audio data Da (a5, a6, a7, a8, a9, a10, a11) in the client device <NUM> is set to be at the end time (Td+Tp) of the pulse data Dp (see "Output data"). Thus, at the end time (Td+Tp) of the pulse data Dp, the output time of the audio data Da (a5, a6, a7, a8, a9, a10, a11) matches between the server <NUM> and the client device <NUM>. Accordingly, the starting time of the playback of the audio data Da (a5, a6, a7, a8, a9, a10, a11) is synchronized between the server <NUM> and the client device <NUM>. Further, the end of time (Td+Tp) of the pulse data Dp is an actual start time of outputting the audio data Da (a5, a6, a7, a8, a9, a10, a11) in the client device <NUM>, and thus the synchronization is achieved from the time when the client device <NUM> starts outputting the audio data Da (a5, a6, a7, a8, a9, a10, a11).

The synchronization can be also achieved even where there are a plurality of client devices <NUM> because each client device <NUM> can adjust the output time of the audio data Da based on its own situation.

At step <NUM> shows the situation where in an embodiment Ts > (Td+Tp), the CPU <NUM> adds silent audio data for a period corresponds to the period of [Ts-(Td+Tp)]. The silent audio data is audio data which generates no sound when it is under the playback. Here, Ts > (Td+Tp) means that the time stamp Ts attached to the audio data Da is later than the end time (Td+Tp) of the pulse data Dp, as shown in <FIG>.

<FIG> show an embodiment of how to adjust the audio data in step <NUM>. <FIG> shows that the time stamp Ts attached to the audio data Da (a0, a1, a2, a3), which the client device <NUM> receives (see 'Requested data timing"), is later then the end time (Td+Tp) of the pulse data Dp (see "Pulse data"; see also time (t) of "clock <NUM>"). Thus, in this case, the CPU <NUM> adds silent audio data Ds, which corresponds to the period of [Ts-(Td+Tp)], to a beginning of the audio data Da (a0, a1, a2, a3), as shown in <FIG>. Then, the CPU <NUM> outputs the audio data Da (a0, a1, a2, a3) after the silent audio data Ds, which is outputted after the pulse data Dp. Accordingly, by adding the silent data Ds, the client device <NUM> starts outputting the audio data Da (a0, a1, a2, a3) at the same time (i.e., at Ts) with the server <NUM>, thereby synchronizing the starting time of the playback with the server <NUM>. The silent audio data Ds is initially stored in the memory <NUM> and is output when necessary. The synchronization can also be achieved even if there are a plurality of client devices <NUM> because each client device <NUM> can adjust the starting time based on its own situation.

Step <NUM> shows the situation where Ts = (Td+Tp). Thus, because the time stamp Ts of the audio data Da corresponds to the end time (Td+Tp) of the pulse data Dp, it is not necessary to adjust the audio data Da. Thus, the CPU <NUM> outputs the audio data Da without any modification.

The steps <NUM>, <NUM> and <NUM> are performed in "Audio data adjustment" section in <FIG>.

At step <NUM>, the CPU <NUM> outputs the audio data Da and the pulse data Dp received from steps <NUM>, <NUM>, and <NUM> through the audio interface <NUM> as shown in <FIG>. As discussed above, the audio data Da may include the silent data Ds or the initial parts of the audio data Da may be cut. At this step, the phase difference Df between the time stamp Ts and the audio clock is not adjusted yet (which will be performed in the following steps).

As discussed above, by using the pulse data Dp, the output time of the audio data Da is precisely adjusted based on the end time (Td+Tp) of the pulse data Dp at the client device <NUM>. Thus, the starting time of the playback of the audio data Da is synchronized between the server <NUM> and the client device <NUM>. In addition, the edge detection module <NUM> detects the edge time Td (i.e., the starting time) of the pulse data Dp, which subsequently utilized to calculate the end time (Td+ Tp) of the pulse data Dp. Thus, the edge detection module <NUM> ensures the above results.

Further, the synchronization can be also achieved even when there are a plurality of client devices <NUM>, because each client device <NUM> can adjust its output time of the audio data based on its own situation, and the server <NUM> is not required to take any measures. In addition, as discussed above, the processor or the microcomputer may work as the control unit. Thus, the processor or the microcomputer, instead of the CPU, may perform the above functions in the client device <NUM>.

The time stamp attached to the audio data is requested timing of the playback from the server <NUM>. The edge time of the audio clock is timing information which indicates an actual playback time) of the audio data from the client device <NUM>. Thus, the phase difference occurs when the edge time of the audio clock does not match the time stamp attached to the audio data.

<FIG> illustrates the phase difference Df (i.e., difference between the time stamp Ts and the edge time Te), which is calculated by using the edge detection module <NUM>. The edge detection module <NUM> detects edge time Te of the audio clock Ca by referring to the clock <NUM>. Then, the CPU <NUM> calculates the difference between time stamp Ts and the edge time Te, and the difference between the time stamp Ts and the edge time Te of the audio clock becomes the phase difference Df.

The phase difference Df can be expressed by using (Ts-(Td+Tp)) or ((Td+Tp) - Ts) as follows:
Df = (Ts - (Td+Tp)) mod (<NUM>/Fs) or Df= ((Td+Tp) - Ts)) mod (<NUM>/Fs), where mod is the modulo operation (sometimes called "modulus"), and Fs is a frequency of the audio data, which is constant and fixed in value. Thus, in the above step <NUM>, the CPU <NUM> outputs the audio data which has the phase difference Df, which is expressed by the above equation.

Further, because the phase difference Df is a difference between the edge time Te of the audio clock Ca and the time stamp Ts, the phase difference Df depends on the speed of the audio clock Ca. Thus, the CPU <NUM>, through controlling the PLL <NUM>, adjusts the speed of the audio clock Ca so that the edge time Te of the audio clock Ca corresponds to the time stamp Ts.

<FIG> shows one example of a phase adjusting process. The steps disclose an example of how the speed of the audio clock is adjusted so that the edge time Te of the audio clock Ca corresponds to the time stamp Ts, thereby eliminating the phase difference Df between the server <NUM> and the client device <NUM>. In this embodiment, it is assumed that in "n" seconds after outputting an initial audio clock, the edge time Te of the audio clock Ca matches the time stamp Ts (note: n ≧ <NUM>, and is integral). The audio clock Ca has a frequency of <NUM>, which means there are <NUM>,<NUM> edges per second; and the edge detection module <NUM> detects the edge time every <NUM> edges (see <FIG>). Thus, the edge detection module <NUM> detects the edge time every one second.

Further, in this embodiment, it is assumed that the CPU <NUM> performs the steps as the control unit by executing the program stored in the memory <NUM>. The steps proceed as follows.

At step <NUM>, the edge detection module <NUM> detects the edge time Te of the audio clock Ca at t=<NUM> by referring to the clock <NUM>, and determines the phase difference Df. Then, the CPU <NUM> determines that the phase difference Df at t=<NUM> is Acc (<NUM>).

<FIG> shows a positive phase difference. This is the situation where the time stamp Ts occurs while the audio clock Ca is at the level "<NUM>", which means that the edge time Te (in other words, the audio clock Ca) is faster than the time stamp Ts, and thus the phase difference is +Df.

On the other hand, <FIG> shows a negative phase difference. In this situation where the time stamp Ts occurs while the audio clock Ca is at the level "<NUM>", which means that the edge time Te (in other words, the audio clock Ca) is slower than the time stamp Ts, and thus the phase difference is -Df.

As shown in <FIG>, by setting the positive phase difference (+Df) and the negative phase difference (-Df), the initial phase difference Df can be set within one sample.

At step <NUM>, the CPU <NUM> starts the phase adjusting process (in other words, the synchronization process of the phase difference) by n=<NUM>. At step <NUM>, the CPU <NUM> determines whether the edge time T(n) is obtained or not. If the edge time T(n) is not obtained, the CPU <NUM> repeats this step until the edge time T(n) is obtained. If it is obtained, the process proceeds to step <NUM>. At step <NUM>, the CPU determines whether n=<NUM> or not. If n=<NUM>, the process proceeds to step <NUM>; and if n ≠<NUM>, the process proceeds to step <NUM>. At step <NUM>, the CPU <NUM> adds <NUM> to "n," and then proceeds to step <NUM>.

At step <NUM>, the CPU <NUM> calculates an adjusted phase difference (d) between the edge time T(n) and the edge time T(n-<NUM>). Because the edge time is measured every one second, the adjusted phase difference (d) is calculated by: <MAT>.

At step <NUM>, based on the adjusted phase difference (d), the CPU <NUM> calculates the phase difference at n second: Acc (n) = Acc (n-<NUM>) + d.

At step <NUM>, the CPU <NUM> determines whether Acc (n)= <NUM> or not. If yes, the process proceeds to step <NUM>. If no, the process proceeds to step <NUM>.

At step <NUM>, the CPU <NUM> determines whether Acc(n) ><NUM> or not. This means that the CPU <NUM> determines whether the audio clock Ca at t=n is faster than the time stamp Ts or not. If yes, the process proceeds to step <NUM>; and if no, the process proceeds to step <NUM>.

At steps <NUM> and <NUM>, the CPU <NUM>, through controlling the Phase-Locked-Loop (PLL) <NUM>, changes the speed of the audio clock Ca in view of the results of step <NUM> so that the phase difference Df is eliminated.

Step <NUM> shows the situation where Acc(n) ><NUM>, which means that the phase difference A(n) is positive. Thus, the edge time Te (in other words, the audio clock Ca) is faster than the time stamp Ts, as shown in <FIG>. Thus, the CPU <NUM>, through controlling the PLL <NUM>, reduces the speed of the audio clock Ca. In other words, the PLL <NUM> decreases the frequencies of the audio clock Ca. Then, the process returns to step <NUM>.

Step <NUM> shows the situation where Acc(n) <<NUM>, which means that the edge time Te (in other words, the audio clock Ca) proceeds slower than the time stamp Ts, as shown in <FIG>. Thus, the CPU <NUM>, through controlling the PLL <NUM>, increases the speed of the audio clock Ca. In other words, the PLL <NUM> increases the frequencies of the audio clock Ca. Then, the process returns to step <NUM>.

As discussed above, the edge detection module <NUM> constantly detects the edge time Te of the audio clock Ca and the time stamp Ts in a predetermined interval, thereby ensuring the detection of the phase difference Df. Then, based on the phase difference Df, the PLL <NUM> constantly adjusts the speed of the audio clock Ca (in other words, adjusting the frequencies of the audio clock Ca) so that the phase difference Df between the server <NUM> and the client device <NUM> is eliminated.

The PLL <NUM> generates a changeable audio clock and can change the speed or the frequencies of the audio clock by changing a PLL parameter value. The PLL <NUM> can change the frequencies of the audio data by the following parameters: (i) a positive parameter value, which increases the speed of the audio clock in accordance with a value of the parameter, or (ii) a negative parameter value, which reduces the speed of the audio clock in accordance with the value of the parameter. In step <NUM>, the PLL <NUM> parameter is set to be a negative value, while the PLL parameter value is set to be a positive value in step <NUM>.

By setting the appropriate parameter value, it is designed that A cc=<NUM> at step <NUM>. In other words, by setting the appropriate parameter value, it is possible that the initial phase difference becomes to zero at a certain point.

For example, the amount of adjustment PLL(n) at "n" seconds after outputting the initial audio clock may be set as follows:
PLL(n)=A × P × (Acc (n) + Constant) + B × PLL(n-<NUM>) + C × PLL (n-<NUM>). where A, B and C are filter factors, and P and Constant offset factors which indicate the relationship between phase difference Acc and the amount of the adjustment PLL (n).

Here, as one example, it is assumed that the relationship between the phase difference Acc and the amount of the adjustment PLL (n) is linear, and thus P=<NUM>, and Constant=<NUM>; and A=<NUM>/<NUM>, B=<NUM>/<NUM>, C=<NUM>/<NUM>.

Then, one example of the amount of the adjustment PLL (n) is defined as: <MAT> where PLL (-<NUM>) = PLL (-<NUM>) = PLL (<NUM>) = <NUM>.

<FIG> shows one example of the relationship between the phase difference Acc (n) and the amount of the adjustment PLL(n) by PLL control. In <FIG>, the line A shows the phase difference Acc (n) and the line B shows the amount of the adjustment PLL (n) expressed by the above equation. <FIG> shows how the amount of the adjustment PLL(n) reaches to the phase difference Acc (n). As shown in <FIG>, the amount of the adjustment PLL (n) increases gradually, which means that the speed of the audio clock is gradually changed, thereby the difference between the phase difference Acc (n) and the amount of the adjustment PLL (n) decreases gradually. Then, at a certain point (e.g., around <NUM> seconds), the amount of the adjustment PLL(n) becomes equal to the phase difference Acc (n), and thus the phase difference is eliminated. <FIG> shows an example where the phase difference is <NUM> nsec (nanosecond). However, the above equation PLL (n) can be used for the situation where the phase difference is different values. The above concept applies to both where the phase difference is a positive value and where the phase difference is a negative value.

In the above embodiment, the audio clock Ca has a frequency of <NUM>, and the edge detection module <NUM> detects the edge time every <NUM> edges (i.e., the edge detection module <NUM> detects the edge time every one second). However, the audio clock Ca is not limited to a frequency of <NUM>. Instead, the audio clock Ca may have a different frequency and the edge time may be detected at a different interval as long as the intended purpose is achieved. Further, as discussed above, the processor or the microcomputer, instead of the CPU, may perform the above steps.

Thus, as discussed above, the client device <NUM> can set a specific time (i.e., at the end of the pulse data), and determine the start of the output time of the audio data based on the specific time. Thus, it is possible to precisely determine the outputting time of the audio data regardless of the delay within the client device. Further, the start time of the outputting the audio data is determined regardless of whether the time stamp attached to the audio data is earlier or later than the specific time. In addition, the client device <NUM> can synchronize the output time of the audio data with the server <NUM> from the time when the client device <NUM> starts outputting the audio data. Thus, it is possible to start the playback of the audio data at the same time between the server <NUM> and the client device <NUM>. Further, the synchronization can be achieved even where there are a plurality of client devices <NUM> because each client device <NUM> can adjust the output time of the audio data based on its own situation.

In addition, the initial phase difference between the audio clock and the time stamp is limited to within one sample (see <FIG>). Thereafter, the phase difference between the output audio clock and the time stamp is constantly monitored and the PLL adjusts the speed of the audio clock, thereby eliminating (or synchronizing) the phase difference between the server <NUM> and the client device <NUM> within a predetermined time period. Because the output audio clock is monitored, the results of the monitor reflect the actual situation of the audio clock. Thus, a reliable synchronization can be achieved by adjusting the speed of the audio clock based on the actual situation of the audio clock. This is also achieved even where there are a plurality of client devices <NUM>, because each client device <NUM> can adjust the speed of the audio clock based on its own situation.

Further, when synchronizing the output time of the audio data and the phase difference between the server <NUM> and the client devices <NUM>, the edge detection module can be utilized. The edge detection module detects the edge time of the pulse data and the edge time of the audio clock, thereby assuring setting the correct output time of the audio clock and detecting the correct phase difference.

In addition, the above results do not require any additional or specific modification to the server <NUM>, and can be achieved with only the client device <NUM>. Thus, the above features can be used when there a plurality of client devices <NUM>.

Accordingly, the present disclosure provides the specific solutions to the technical problem related to the delay caused by the software processing within the client device <NUM>.

In the above embodiment, the client device <NUM> includes the DAC <NUM>, but does not include the speaker. However, the client device <NUM>, the DAC and the speaker may be formed integrally as a single device. Further, the client device <NUM> and the DAC <NUM> may be formed separately. In addition, in the above embodiment, the server <NUM> and the client device <NUM> may be used for many technical fields. For example, the server <NUM> and the client device <NUM> can be connected to a stereo with a right output and left output, respectively. Further, it is possible that each of the server <NUM> and the client device <NUM> is placed in a respective room and the audience can listen to the audio data in the respective room in a synchronized manner. The audio data may be a music. However, the audio data is not limited to music and other types of the audio data can be used. In addition, it is not necessary that the only the audio data is distributed from the server <NUM> to the client device <NUM>, and the principle of the present disclosure is applied for the audio data which is distributed with another data (e.g., image data) to the client device <NUM>.

Claim 1:
An audio device (<NUM>) which is configured to receive audio data (Da) from another device (<NUM>), comprising:
a memory (<NUM>) which stores instructions,
a clock (<NUM>) which has common time information with said another device (<NUM>), and
a processor (<NUM>) that is configured to execute the instructions stored in the memory (<NUM>),
wherein
the memory (<NUM>) stores pulse data (Dp), the pulse data (Dp) including a pulse provided at a start time (Td), the pulse data having a predetermined duration (Tp) in time from the start time (Td) to an end time (Td+Tp),
the processor (<NUM>) is configured to execute the instructions stored in the memory (<NUM>) to:
receive the audio data (Da) and a time stamp (Ts) attached to the audio data (Da), the time stamp (Ts) being a time when said another device (<NUM>) starts outputting the audio data (Da),
output the pulse data (Dp), the pulse data (Dp) being output when the audio device (<NUM>) receives the audio data (Da),
detect the start time (Td) of the pulse data (Dp) by referring to the clock (<NUM>),
calculate the end time (Td+Tp) of the pulse data (Dp) by adding the predetermined duration (Tp) to the start time (Td),
compare the end time (Td+Tp) of the pulse data (Dp) and the time stamp (Ts),
adjust the audio data (Da) based on the comparing result, and
output the adjusted audio data (Da), the adjusted audio data (Da) being output after the pulse data (Dp) is output,
wherein
the memory (<NUM>) stores silent audio data (Ds), and
when the time stamp (Ts) is later than the end time (Td+Tp) of the pulse data (Dp), the processor (<NUM>) is configured to (i) output the silent audio data (Ds) for a period corresponding to a difference between the time stamp (Ts) and the end time (Td+Tp) of the pulse data (Dp), and (ii) output the audio data (Da) after the silent audio data (Ds) is output;
when the time stamp (Ts) is earlier than the end time (Td+Tp) of the pulse data (Dp), the processor (<NUM>) is configured to (i) adjust the audio data (Da) by cutting the audio data (Da) for an amount corresponding to a difference between the time stamp (Ts) and the end time (Td+Tp) of the pulse data (Dp), and (ii) output the adjusted audio data (Da).