Patent Description:
<CIT> describes a method for forming a thin film transistor array substrate comprising the step of forming an active layer using a zinc target under an environment of oxygen and nitrogen in a sputtering chamber.

<CIT> describes a conductive layer for a thin film transistor (TFT) array panel including a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and including a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer.

<CIT> describes a semiconductor device which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer.

A display device such as a liquid crystal display (LCD) and an organic light emitting diode (OLED) display includes a display panel including a plurality of pixels displaying images, and a plurality of signal lines. Each pixel may include a pixel electrode receiving a data signal, and the pixel electrode may be connected to at least one transistor to receive the data signal.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

The present invention is defined by the subject matter of independent claim <NUM>. Preferred embodiments are defined in the sub claims.

Embodiments are also directed to a method for manufacturing a display panel including forming a plurality of layers including a first insulating layer on a substrate, sequentially stacking a first layer, a second layer, and a third layer that include a first metal on the first insulating layer, coating an organic material on a fourth layer as an oxidation layer formed on the third layer and executing a photo process to form a passivation layer having a contact hole on the fourth layer, and curing the passivation layer in a nitrogen (N<NUM>) atmosphere and at a predetermined temperature to form a fifth layer that is crystalline and disposed on the fourth layer, the fourth layer being amorphous.

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Further, in the specification, the word "on" or "above" means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.

Referring to <FIG>, the display panel <NUM> includes a substrate <NUM> including a display area DA as an area displaying an image in a plan view and a peripheral area PA disposed outside the display area DA. The peripheral area PA may not display an image, or may include an area displaying the image, as desired.

The substrate <NUM> may include an insulating material such as a plastic, a metal thin film, and a thin glass film. The substrate <NUM> may be a flexible substrate or may be a substantially rigid substrate. The substrate <NUM> may include a single layer or a plurality of layers. When the substrate <NUM> includes a plurality of layers, the substrate <NUM> may include at least one base layer including a polymer such as a polyimide, and at least one barrier layer including a silicon oxide, a silicon nitride, etc. The base layer and the barrier layer may be alternately stacked.

The display area DA may include a plurality of pixels PX and a plurality of signal lines. The display area DA may display the image on the surface parallel to the x direction and the y direction. The pixel PX may include at least one switching element and a pixel electrode connected thereto. The switching element may be a three-terminal element such as a transistor that is integrated in the display panel <NUM>. The pixel electrode may selectively receive a data signal through at least one switching element.

The peripheral area PA may include a circuit such as gate drivers 400a and 400b, a signal line such as a voltage transmitting line <NUM>, a pad portion 110P, etc..

The gate driver 400a and the gate driver 400b may be disposed in the peripheral area PA at right and left sides of the display area DA. Each of the gate drivers 400a and 400b may include a plurality of stages sequentially arranged in a direction approximately parallel to the x direction. The gate drivers 400a and 400b may be directly formed on the substrate <NUM> along with the plurality of signal lines and the switching element that are disposed in the display area DA. One of the two gate drivers 400a and 400b may be omitted.

The voltage transmitting line <NUM> may extend along at least three edges such as left, right, and upper edges of the display area DA. The voltage transmitting line <NUM> may transmit a predetermined voltage such as a common voltage EL VSS to the display area DA.

The pad portion 110P may be disposed at one side in a peripheral area PA (e.g., a lower side peripheral area PA) with respect to the display area DA. The pad portion 110P may include a plurality of pads for connecting an IC chip, a circuit film, etc. End portions of the signal lines disposed in the peripheral area PA may be connected to the pad portion 110P to receive the signal.

Referring to a cross-sectional view, a structure including a lower conductive layer including at least three layers that are sequentially stacked and an upper conductive layer disposed thereon and in contact with an uppermost layer of the lower conductive layer may be disposed in the display area DA and/or the peripheral area PA of the display panel <NUM>. <FIG> illustrates the cross-sectional structure of the pixel PX as an example in which this structure is disposed in the display area DA, and <FIG> illustrates the cross-sectional structure of the transistor circuit and the signal line as an example in which this structure is disposed in the peripheral area PA.

Referring to <FIG>, the display panel <NUM> may include at least one transistor Tp, a capacitor Cst and at least one light emitting diode (LED) ED that are disposed in one pixel PX, and at least one transistor Td disposed in the peripheral area PA.

Referring to the cross-sectional structure in detail, a barrier layer <NUM> made of the plurality of layers or the single layer may be disposed on the substrate <NUM>, and a plurality of active patterns <NUM> may be disposed on the barrier layer <NUM>. (Herein, an active pattern <NUM> may be referred to variously as an active layer or as an active pattern. ) The plurality of active patterns <NUM> may include source areas <NUM> and 136d and drain areas <NUM> and 137d, and channel areas <NUM> and 131d disposed between the source areas <NUM> and 136d and the drain areas <NUM> and 137d facing each other. The active pattern <NUM> may include a semiconductor material such as amorphous silicon, a polysilicon, an oxide semiconductor, etc. A part of the active pattern <NUM>, such as the channel areas <NUM> and 131d, may maintain a semiconductor characteristic, and other parts, such as the source areas <NUM> and 136d and the drain areas <NUM> and 137d, may have conductivity.

A first insulating layer <NUM> may be disposed on the active pattern <NUM>, and a first conductive layer including gate electrodes <NUM> and 155d and a first electrode 155a may be disposed on the first insulating layer <NUM>. The active pattern <NUM> and the gate electrodes <NUM> and 155d overlapping thereto may form respective ones of the transistors Tp and Td. The transistor Tp disposed in the pixel PX may include the channel area <NUM>, the source area <NUM>, and the drain area <NUM>, and the gate electrode <NUM> overlapping the channel area <NUM>. The transistor Td disposed in the peripheral area PA may include the channel area 131d, the source area 136d, and the drain area 137d, and the gate electrode 155d overlapping the channel area 131d. The transistor Td may be included in a circuit such as the gate drivers 400a and 400b.

A second insulating layer <NUM> may be disposed on the first conductive layer and the first insulating layer <NUM>, and a second conductive layer including a second electrode <NUM> may be disposed on the second insulating layer <NUM>. The first electrode 155a and the second electrode <NUM> overlapping each other, with the second insulating layer <NUM> in between, may form the capacitor Cst. The first electrode 155a may be connected to the gate electrode of another transistor included in the pixel PX. In this case, the capacitor Cst may function to maintain the voltage of the gate electrode connected to the first electrode 155a. The second electrode <NUM> may receive a predetermined voltage such as a driving voltage.

A third insulating layer <NUM> may be disposed on the second conductive layer and the second insulating layer <NUM>.

At least one among the barrier layer <NUM>, the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM> may include an inorganic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiON), and/or an organic insulating material. Some or all of the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM> may have a plurality of contact holes <NUM>, 66d, and <NUM>.

A third conductive layer <NUM> corresponding to the above-described lower conductive layer may be disposed on the third insulating layer <NUM>. The third conductive layer <NUM> may include a plurality of connection electrodes <NUM>, <NUM>, and <NUM> and a plurality of signal lines <NUM>. The plurality of signal lines <NUM> may include signal lines transmitting the various signals or voltages such as the voltage transmitting line <NUM>, the data line transmitting the data voltage, and the driving voltage line transmitting the driving voltage.

In the display area DA, the connection electrode <NUM> may be electrically connected to the source area <NUM> of the transistor Tp through the contact hole <NUM>, and the connection electrode <NUM> may be electrically connected to the drain area <NUM> of the transistor Tp through the contact hole <NUM>. In the peripheral area PA, the connection electrode <NUM> may be electrically connected to the source area 136d of the transistor Td through the contact hole 66d. The connection electrode <NUM> may be omitted.

At least one among the first conductive layer, the second conductive layer, and the third conductive layer <NUM> may include the conductive material such as a metal of copper (Cu), silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and/or an alloy of at least two among them.

For example, according to the present exemplary embodiment, the third conductive layer <NUM> may include a plurality of layers for optimizing the characteristics of the display panel <NUM>. The third conductive layer <NUM> may include a first layer 170a, a second layer 170b, and includes a third layer 170c, a fourth layer 170d, and a fifth layer 170e that are sequentially stacked in the upper direction with respect to the substrate <NUM>. The prefixes 'first', 'second', etc. used here are not intended to define a stacking order of layers, but to distinguish the layers, and may be used in other ways in other parts of the detailed description or in the claims.

The third layer 170c, the fourth layer 170d, and the fifth layer 170e commonly include the first metal. The fourth layer 170d and the fifth layer 170e include oxygen of a higher content ratio (e.g., a higher atom percent (at%)) than the third layer 170c. The atom percent of oxygen included in the first layer 170a may be similar to the atom percent of oxygen included in the third layer 170c. The atom percent of oxygen included in the third layer 170c may be between the atom percent of oxygen included in the fourth layer 170d and the atom percent of oxygen included in the first layer 170a. The fourth layer 170d and the fifth layer 170e are layers formed by oxidizing the first metal included in the third layer 170c. The fourth layer 170d includes the first metal and oxygen of a first composition ratio, the fifth layer 170e includes the first metal and oxygen of a second composition ratio. The first composition ratio and the second composition ratio are different from each other. The first composition ratio is the ratio (the first metal (at%)/oxygen (at%)) of the atom percent of the first metal with respect to the atom percent of oxygen included in the fourth layer 170d. The second composition ratio is the ratio (the first metal (at%)/oxygen (at%)) of the atom percent of the first metal with respect to the atom percent of oxygen included in the fifth layer 170e.

The fifth layer 170e has higher conductivity than the fourth layer 170d. The fourth layer 170d may be amorphous, and the fifth layer 170e may be crystalline. The fourth layer 170d may be a natural oxidation layer generated by naturally oxidizing the first metal included in the third layer 170c. The fifth layer 170e may be formed by crystallizing a part of the fourth layer 170d. This will be explained in more detail below.

The first metal may include at least one among titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), tungsten (W), neodymium (Nb), gold (Au), or alloys thereof. For example, when the first metal is titanium (Ti), the fourth layer 170d may be made of a titanium oxide (TiOx, where x is from <NUM> to <NUM>), the fifth layer 170e may be titanium monoxide (TiOx, where x is from <NUM> to <NUM>), and the fifth layer 170e has higher conductivity than the fourth layer 170d.

When the first metal is titanium (Ti), the crystalline structure of the fifth layer 170e may be a cubic structure.

When the first metal is titanium (Ti), the second composition ratio may be smaller than the first composition ratio. In detail, the first composition ratio may be larger than <NUM> (excess) and equal to or less than <NUM>, and the second composition ratio may be equal to or greater than <NUM> and equal to or less than <NUM>.

Among the layers of the third conductive layer <NUM>, the ratio with respect to the thickness of the fifth layer 170e in a sum of the thicknesses of the fourth layer 170d and the fifth layer 170e may be <NUM> % or more. For example, the sum of the thicknesses of the fourth layer 170d and the fifth layer 170e may be about <NUM> angstroms to about <NUM> angstroms. In this case, each thickness of the fourth layer 170d and the fifth layer 170e may be about <NUM> angstroms to about <NUM> angstroms.

As above-described, the fourth layer 170d and the fifth layer 170e having the higher oxygen content ratio (atom percent) than the third layer 170c are disposed on the third layer 170c. In some implementations, the first layer 170a having a similar composition ratio to the third layer 170c may be in direct contact with another underlying layer. For example, as shown in <FIG>, the first layer 170a included in the connection electrodes <NUM> and <NUM> may be in direct contact with the third insulating layer <NUM> or the source/drain area <NUM>/<NUM> of the transistor Tp. As another example, as shown in <FIG>, the first layer 170a included in the connection electrode <NUM> and the signal line <NUM> may be in direct contact with the third insulating layer <NUM> or the source area 136d of the transistor Td.

The second layer 170b may include a second metal that is different from the first metal. The second metal may include aluminum (Al) or an aluminum alloy. The conductivity of the second metal may higher than the conductivity of the first metal.

The thickness of the second layer 170b may be greater than the thickness of the first layer 170a or the third layer 170c. Unless stated otherwise, the term "thickness" refers to a thickness in a direction perpendicular to the upper surface of the substrate <NUM>, that is, the z direction.

The first layer 170a and the third layer 170c may prevent a reaction with other layers (e.g., the active pattern <NUM>, the third insulating layer <NUM>, or a passivation layer <NUM> and a fourth conductive layer <NUM> described below) disposed on or under the third conductive layer <NUM> and/or may prevent impurities from penetrating into the second layer 170b, thereby preventing the third conductive layer <NUM> from being corroded. Accordingly, a contact characteristic of the third conductive layer <NUM> with the other layers may be improved.

The passivation layer <NUM> as a fourth insulating layer may be disposed on the third conductive layer <NUM> and the third insulating layer <NUM>. The passivation layer <NUM> may have a contact hole <NUM> exposing the connection electrode <NUM>, a contact hole <NUM> exposing the connection electrode <NUM>, and a contact hole <NUM> exposing the signal line <NUM>. The contact hole <NUM> may expose a part (e.g., the end portion of the signal line <NUM>) of the signal line <NUM> to not be covered. The passivation layer <NUM> may include the inorganic insulating material and/or the organic insulating material such as a polyacryl-based resin and a polyimide-based resin. The upper surface of the passivation layer <NUM> may be substantially flat.

The fourth conductive layer <NUM>, including a pixel electrode <NUM>, a connecting member <NUM>, and a contact assistant <NUM>, may be disposed on the passivation layer <NUM>.

The pixel electrode <NUM> may be disposed in each pixel PX of the display area DA, and may be connected to the connection electrode <NUM> through the contact hole <NUM>, thereby receiving the data voltage. The connecting member <NUM> may be disposed in the peripheral area PA and may be connected to the connection electrode <NUM> through the contact hole <NUM>, thereby electrically connecting the transistor Td to another electrode or transistor. The contact assistant <NUM> may be disposed in the peripheral area PA, and may be electrically connected to the signal line <NUM> through the contact hole <NUM>. The contact assistant <NUM> may prevent the corrosion of the end portion of the signal line <NUM> that is not covered by the passivation layer <NUM>, and may assist with adhesion between a bump such as the IC chip or the printed circuit film and the signal line <NUM>. The end portion of the signal line <NUM> and the contact assistant <NUM> may be disposed in the pad portion 110P shown in <FIG>, for example.

The fourth conductive layer <NUM> may include a semi-transmissive conductive material layer or a reflective conductive material, as examples.

The fourth conductive layer <NUM> may include a single layer or a plurality of layers. When the fourth conductive layer <NUM> includes the plurality of layers, the fourth conductive layer <NUM> may include a first layer 190a, a second layer 190b, and a third layer 190c that are sequentially stacked in the upper direction with respect to the substrate <NUM>. The second layer 190b may include, for example, silver (Ag), and the first layer 190a and the third layer 190c may include, for example, ITO, etc. The first layer 190a and the third layer 190c may prevent the corrosion of the second layer 190b and may increase adherence of the fourth conductive layer <NUM> with another layer.

A pixel definition layer <NUM> may be disposed on the passivation layer <NUM>. The pixel definition layer <NUM> may have an opening (also referred to as a hole) <NUM> disposed on the pixel electrode <NUM>. The pixel definition layer <NUM> may be removed in the opening <NUM>, such that the pixel electrode <NUM> is not covered by the pixel definition layer <NUM> and is exposed. The pixel definition layer <NUM> may include a photosensitive organic material such as polyacryl-based resin, a polyimide-based resin, etc..

An emission layer <NUM> may be disposed on the pixel electrode <NUM>. The emission layer <NUM> may include a portion exposed in the opening <NUM> of the pixel definition layer <NUM>. The emission layer <NUM> may include an organic emission material or an inorganic emission material.

A common electrode <NUM> may be disposed on the emission layer <NUM>. The common electrode <NUM> may also be formed on the pixel definition layer <NUM>, thereby being continuously formed throughout the plurality of pixels PX. The common electrode <NUM> may include, for example, a conductive transparent material.

The pixel electrode <NUM>, the emission layer <NUM>, and the common electrode <NUM> in each pixel PX may together the light emitting diode (LED) (ED).

A capping layer <NUM> and/or a functional layer <NUM> may be disposed on the common electrode <NUM>. The capping layer <NUM> may play a role of increasing light efficiency through a refractive index adjustment. The functional layer <NUM> may play a role of increasing the light efficiency by preventing damage to the underlying layers. The functional layer <NUM> and the capping layer <NUM> may be omitted in at least part of the peripheral area PA. For example, as shown in the left side and the right side of <FIG>, the capping layer <NUM> may be disposed only in part of the peripheral area PA and the functional layer <NUM> may be omitted. As shown, for example, at the right side of <FIG>, the capping layer <NUM> and the functional layer <NUM> may be omitted in some parts.

An encapsulation layer <NUM> may be disposed on the functional layer <NUM>. The encapsulation layer <NUM> may encapsulate the light emitting diode (LED) (ED), thereby preventing moisture or oxygen from penetrating from the outside. The encapsulation layer <NUM> may include at least one of inorganic layers <NUM> and <NUM> including an inorganic material, and at least one organic layer <NUM> including an organic material. The inorganic layers <NUM> and <NUM> and the organic layer <NUM> may be alternately stacked. According to another exemplary embodiment, the encapsulation layer <NUM> may be another substrate facing the substrate <NUM>.

The third conductive layer <NUM> will be described in detail with reference to <FIG> along with <FIG>.

<FIG> shows a graph representing the content ratio (at%) change of elements included in a part of the third conductive layer <NUM> including titanium (Ti) and a part of the fourth conductive layer <NUM> including silver (Ag) and ITO as the first metal.

Referring to <FIG>, in an inventive example, most of the third layer 170c is made of titanium, and the atom percent of titanium is generally lower going from the third layer 170c to the fourth layer 170d and the fifth layer 170e, and the first layer 190a and the second layer 190b of the fourth conductive layer. The word "most" as used herein indicates more than <NUM>% of the entirety. The atom percent of oxygen (O) is generally higher going from the third layer 170c to the fourth layer 170d and the fifth layer 170e. For example, the first composition ratio as the ratio of the atom percent (at%) of titanium to the atom percent (at%) of oxygen included in the fourth layer 170d is larger than about <NUM> (excess)and less than or equal to about <NUM>. The second composition ratio as the ratio of the atom percent (at%) of titanium to the atom percent (at%) of oxygen included in the fifth layer 170e is greater than or equal to about <NUM> and less than or equal to <NUM> or less.

<FIG> illustrates a cross-sectional image of conductive layers of a display device according to an exemplary embodiment, and <FIG> illustrates a refraction photo filtering an AA area of the image shown in <FIG> by using Fourier transform.

As above-described, the fourth layer 170d is a natural oxidation layer that is generated when titanium included in the third layer 170c is naturally oxidized. In <FIG>, a boundary between the third layer 170c and the fourth layer 170d may be confirmed. The fifth layer 170e is a layer formed by crystallizing part of the fourth layer 170d as the natural oxidation layer of titanium. A boundary may also be confirmed between the fourth layer 170d and the fifth layer 170e. For example, as shown in the refraction image of <FIG>, the crystallized fifth layer 170e may have the cubic structure.

As shown in the several structures shown in <FIG> and <FIG>, the third conductive layer <NUM> may be in contact with the fourth conductive layer <NUM> while another conductive layer and transmits a voltage. If the contact resistance between the third conductive layer <NUM> and the fourth conductive layer <NUM> is high, the voltage could decrease such that a failure of the display could be generated. For example, it may be difficult to remove the fourth layer 170d of the third conductive layer <NUM> as the natural oxidation layer and the contact resistance may be increased. However, according to an exemplary embodiment, the fifth layer 170e may be disposed between the fourth layer 170d and the fourth conductive layer <NUM>, thereby decreasing the contact resistance. This effect may be confirmed in the graph illustrated in <FIG>.

A first curve Ga shown in <FIG> represents the contact resistance between the third conductive layer <NUM> of which the first metal is titanium and the fourth conductive layer <NUM> in the structure according to an exemplary embodiment. As a comparative example, the second curve Gr represents the contact resistance between the third conductive layer and the fourth conductive layer when the fifth layer 170e of the third conductive layer <NUM> does not exist. The resistance represented by the second curve Gr is from about <NUM> kΩ to about <NUM> kΩ, and the resistance represented by the first curve Ga is from about <NUM> kΩ to about <NUM> kΩ. In the structure according to an exemplary embodiment, it may be found that the contact resistance between the third conductive layer <NUM> and the fourth conductive layer <NUM> is lower by about one hundred to several hundreds compared to the contact resistance of the comparative example. Therefore, according to the exemplary embodiments, a reduction of the voltage transmitted from the third conductive layer <NUM> to the fourth conductive layer <NUM> may be prevented, thereby reducing defects of the display.

Now, the structure of the third conductive layer included in the display panel according to an exemplary embodiment will be described with reference to <FIG> along with the above-described drawings.

The cross-sectional structure shown in <FIG> schematically represents a structure in which the third conductive layer <NUM> and the fourth conductive layer <NUM> are in contact with each other through the contact hole of the passivation layer <NUM>. For example, the cross-sectional structure may be the cross-sectional structure shown in <FIG> and <FIG> as above-described, and a contact hole <NUM> of the passivation layer <NUM> may be one of the above-described contact holes <NUM>, <NUM>, and <NUM>.

Referring to <FIG>, the third conductive layer 170A according to an inventive embodiment may be substantially the same as the third conductive layer <NUM> of the above-described inventive embodiment. However a fifth layer 170e1 corresponding to the fifth layer 170e is included. The fifth layer 170e1 may not be disposed on the whole of the third conductive layer 170A. Instead, the fifth layer 170e1 may have a smaller plane area than the first layer 170a, the second layer 170b, the third layer 170c, and the fourth layer 170d. For example, the fifth layer 170e1 may be substantially disposed in the area corresponding to the contact hole <NUM>, instead of being under the passivation layer <NUM> disposed on the third conductive layer 170A. For example, the fifth layer 170e1 may be hardly disposed between the passivation layer <NUM> and the fourth layer 170d, such that the passivation layer <NUM> and the fourth layer 170d are in direct contact with each other in most areas.

Referring to <FIG>, most of a third conductive layer 170B according to an inventive embodiment may be the same as the above-described third conductive layer <NUM>, except that a fifth layer 170e2 corresponding to the fifth layer 170e of <FIG> is included. The fifth layer 170e2 may be disposed on most of the third conductive layer 170B. The fifth layer 170e2 may have different thicknesses depending on its position. For example, the fifth layer 170e2 may include a first portion 171e that is disposed in the area corresponding to the contact hole <NUM> and that does not overlap the passivation layer <NUM>. The fifth layer 170e2 may further include a second portion 172e connected to the first portion 171e and disposed between the passivation layer <NUM> and the fourth layer 170d to overlap the passivation layer <NUM>. A maximum thickness D2 of the second portion 172e may be less than a maximum thickness D1 of the first portion 171e.

Next, referring to <FIG>, a fifth layer 170e3 included in a third conductive layer 170C according to an inventive embodiment may be formed at a part of the third conductive layer 170C, like the fifth layer 170e1 of the third conductive layer 170A shown in <FIG>. The fifth layer 170e3 may include a first portion 173e that is disposed in the area corresponding to the contact hole <NUM> such that the first portion 173e does not overlap the passivation layer <NUM>. A second portion 174e connected to the first portion 173e may be disposed near the contact hole <NUM>, and may overlap the passivation layer <NUM>. The first portion 173e may be mainly disposed in the area corresponding to the contact hole <NUM> in which the passivation layer <NUM> is removed, similar to the fifth layer 170e1 of <FIG> as above-described. The second portion 174e may be disposed between the passivation layer <NUM> and the fourth layer 170d, similar to the fifth layer 170e2 of <FIG>, however the thickness thereof may be varied depending on its position. Most of the thickness D3 of the first portion 173e may be constant. The thickness D4 of the second portion 174e may gradually decrease in relation to a distance from the edge of the contact hole <NUM> and a distance from the first portion 173e. The thickness D4 of the second portion 174e may be less than the thickness D3 of the first portion 173e. The second portion 174e may be absent beyond an area at a certain distance from the edge of the contact hole <NUM>, such the passivation layer <NUM> and the fourth layer 170d in the area beyond the certain distance may be in direct contact.

Now, the manufacturing method of the display panel <NUM> according to an exemplary embodiment, particularly the manufacturing method of the third conductive layer and the passivation layer <NUM>, will be described with reference to <FIG> along with <FIG>.

After forming the several layers including the third insulating layer <NUM> on the substrate <NUM>, the first layer 170a, the second layer 170b may be, and and the third layer 170c is sequentially stacked on the third insulating layer <NUM>. The fourth layer 170d, as a natural oxidation layer, is formed on the third layer 170c after stacking the third layer 170c.

The material for the passivation layer <NUM>, for example the organic material such as the polyimide-based resin, is coated on the fourth layer 170d, and a photo process may be executed to form the plurality of contact holes <NUM>, <NUM>, <NUM>, and <NUM> in the passivation layer <NUM>. In a curing process for the passivation layer <NUM>, at least part of the fourth layer 170d is crystallized, thereby forming the fifth layers 170e, 170e1, 170e2, and 170e3 according to the inventive embodiments. The curing process of the passivation layer <NUM> may be executed, for example, in a nitrogen (N<NUM>) atmosphere at about <NUM> degrees (°C) to about <NUM> degrees (°C).

Claim 1:
A display panel (<NUM>), comprising:
a third conductive layer (<NUM>) including a third layer (170c), a fourth layer (170d), and a fifth layer (170e) that are sequentially stacked; and
a fourth conductive layer (<NUM>) disposed on the third conductive layer and in contact with the fifth layer (170e)
the third layer (170c) includes a first metal characterized in that
the fourth layer (170d) includes the first metal and oxygen in a first composition ratio,
the fifth layer (170e) includes the first metal and oxygen in a second composition ratio,
the first composition ratio and the second composition ratio being different from each other, and
conductivity of the fifth layer (170e) being higher than conductivity of the fourth layer (170d).