Patent Description:
This document pertains to signal acquisition circuitry and methods for performing correlated double sampling on a differential input signal.

High quality low power signal processing of sensor and other analog input signals is desirable, particularly in battery-powered or implantable applications. Many signal acquisition and analog-to-digital signal conversion circuits do not provide accuracy and low noise signal processing performance while also providing low power consumption. <CIT> discloses a correlated double sampling switched capacitor integrator.

An illustrative non-limiting example of an analog signal processing channel can include an input amplifier circuit for sampling an analog input signal, an analog-to-digital converter (ADC) circuit for converting the analog input signal, as buffered by the amplifier, into a digital value, a voltage reference circuit for providing a voltage reference to the ADC for performing an analog-to-digital (A2D) conversion, digital post-processing circuitry for further performing signal processing (e.g., decimation or other filtering, etc.), and control circuitry for timing operation of the ADC and switching circuitry used in the signal processing channel.

For battery-powered or other low power applications, average integrated power (e.g., energy consumed per signal measurement) matters. Some low-power applications need only infrequent signal acquisitions and corresponding signal processing for measurement. Powering down signal processing components between signal acquisitions and corresponding measurements can help save power. Such powering down can include putting one or more circuits into a low-power consumption state, or can include turning off one or more circuits, e.g., putting such circuits into a no power consumption state.

Not all signal processing circuitry components are equally suited for being powered down into a standby or inactive state. Some components may still have relatively high inactive quiescent power consumption. The present inventors have recognized, among other things, that it may be desirable, for example, to reduce inactive power toward or to a level that is at or below that of a self-discharge rate of a battery being used to power the signal processing circuitry.

Some components may additionally or alternatively have high active state power consumption or long turn-on or turn-off time requirements, which can lead to poor power consumption characteristics. Both active power consumption and inactive power consumption are important figures of merit in low power signal acquisition and processing systems. Providing users with flexibility to configure system that can span different throughput needs while scaling power consumption to accommodate such different throughput needs can also be helpful. In sum, if a large "power versus throughput" scaling span can be provided to the user, a wider range of applications can be better served by the same circuitry, leading to a more useful product.

The present inventors have also recognized, among other things, that for powering down signal acquisition, processing, and conversion circuitry, a successive approximation routine (SAR) ADC can be configured to use relatively fixed energy per A2D conversion, and can be carefully configured to be powered down into an inactive state with low inactive state leakage current, and a voltage reference circuit can also be carefully configured to support power-cycling or powering down into a low power state in spite of the long-time constant noise filtering needed to reduce the noise bandwidth of such a voltage reference circuit.

However, most signal conditioning amplifiers, for buffering, amplifying, or conditioning the input signal for further signal processing, signal conversion, or both, can face significant limitations including incomplete power-down performance, designed for resistive loads that consume power, and even chopper amplifiers often are limited by slow power-up settling, and provide chopping that is not always well-synchronized with the signal measurements to optimize power consumption.

For signal acquisition or signal conditioning amplifiers, the present inventors have recognized a need for, among other things: low inactive power consumption; fast turn-on from a powered-down state; low offset voltage; low referred-to-input (RTI) noise (including low <NUM>/f noise); good signal gain (e.g., to reduce RTI noise of an ADC coupled to an output of the amplifier); and good common-mode rejection, particularly for acquiring a differential input signal from a sensor or other source.

The present document describes subject matter that can include a signal acquisition or conditioning amplifier that can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications.

According to a first aspect of the invention, a signal acquisition circuitry is provided according to claim <NUM>. According to another aspect of the invention, a method of acquiring an input signal for correlated double sampling (CDS) of a differential input signal is provided according to claim <NUM>.

<FIG> shows an example of signal acquisition circuitry <NUM>, according to the invention as claimed, such as for performing correlated double sampling (CDS) on a differential input signal having components Vx and Vy, such for low power signal processing. <FIG> shows a timing diagram illustrating operation of various components of the signal acquisition circuitry <NUM> shown in <FIG>. In <FIG>, the signal acquisition circuitry <NUM> includes an amplifier <NUM> circuit, such as for signal acquisition or conditioning of the analog differential input signal having components Vx and Vy at differential signal input nodes 104A-B, respectively. In the example of <FIG>, the amplifier <NUM> can include an operational transconductance amplifier (OTA) that can operate to amplify a voltage between a first (e.g., non-inverting) amplifier input 106A and a second (e.g., inverting) amplifier input 106B into a current that can be provided at the amplifier output <NUM> using the transconductance gain (Gm) of the OTA. The current provided at the amplifier output <NUM> can be used to charge or discharge a capacitive load to provide a resulting voltage signal at the amplifier output <NUM> that can be converted by a successive approximation routine (SAR) or other analog-to-digital converter (ADC) <NUM> into a sampled digital output value at the ADC output <NUM>. The individual components Vx and Vy of the differential input signal are successively converted into a CDS pair of sampled digital output values at the ADC output <NUM>. By taking a difference between these two sampled digital output values at ADC output <NUM> forming the CDS pair sampling instance, a differential digital output signal (corresponding to a difference between the Vx and Vy components of the differential analog input signal is provided using the CDS sampling instance. The ADC <NUM> can be powered down, such as between successive CDS sampling instances. The ADC <NUM> can include or be coupled to a voltage reference circuit, for providing a voltage for use in comparisons during an A2D conversion, wherein the voltage reference circuit can be configured to be also powered down, such as between successive CDS sampling instances, such as described in<CIT>, including its description of a voltage reference suitable for being powered down.

If the signal being acquired is slow enough relative to the quick successive pair of samples of the CDS sampling shown and described with respect to <FIG>, nearly the same differential signal components Vx and Vy will be present during both samples of the CDS sampling, so the signal acquisition can be still regarded as "differential" and this document will not introduce terminology such as "quasi-differential" or "pseudo-differential" to complicate this point, even though such alternative terminology could be used.

The capacitive load driven by the OTA amplifier includes a storage capacitor, Ci, such as can be driven and charged or discharged by the OTA amplifier <NUM> via a feedback network about the OTA amplifier <NUM>. In the example shown in <FIG>, the feedback network is a capacitive feedback network, such as can include a feedback capacitor, Cf, located between the amplifier output <NUM> and the second amplifier input 106B. The storage capacitor, Ci, is coupled to the feedback network, such as by being coupled between the second amplifier input 106B and a ground or reference node <NUM>. The feedback network is used to establish a closed-loop gain around the OTA amplifier <NUM>. In the example shown in <FIG>, the closed-loop voltage gain can be shown to be (Ci/Cf +<NUM>), as shown in Equation <NUM>.

Using a capacitive feedback network in combination with an OTA amplifier <NUM> can be helpful in that the OTA amplifier <NUM> drives a capacitive load, yielding no quiescent current after the capacitive load is charged to a stable voltage value at the OTA amplifier output <NUM>, unlike a resistive load, which would continue to draw a quiescent current even after the amplifier output <NUM> reaches a stable voltage value. Another advantage of this configuration using an OTA amplifier <NUM> in combination with a capacitive feedback network, is that the OTA amplifier <NUM> can be "output compensated" such that its stability is effected via a "dominant pole" provided by the load capacitance at the amplifier output <NUM> (which "sees" both the capacitance of the capacitive feedback network and that of the SAR or other ADC circuit <NUM>. This can be compared to an operational amplifier ("op-amp") providing a voltage gain instead of a transconductance gain, which typically requires an "internal" compensation capacitor (e.g., which can be conceptualized as being "internal" to the operational amplifier, even though it may include an external capacitor coupled to internal nodes of the operational amplifier, such as between the first and second stages of a two-stage operational amplifier). The internal compensation capacitor of an operational amplifier requires a longer turn-on and turn-off time in order to stabilize, making it more difficult to power down (and to power up) an operational amplifier (e.g., recurrently between CDS samplings) than to similarly power down (and to power up) an output-compensated operational transconductance amplifier, which is not so limited.

For the capacitive feedback network shown in <FIG>, an initialization switch <NUM> is included to initialize a voltage of the storage capacitor, Ci, at the second amplifier input 106B, which would otherwise be "floating" when a high-input impedance OTA amplifier <NUM> is used, such as where each of the first and second inputs 106A-B of the OTA amplifier <NUM> is connected internal to the OTA amplifier to a capacitive gate terminal of a field-effect transistor (FET). The initialization switch <NUM> is located between the amplifier output <NUM> and the second amplifier input 106B, such as to auto-zero the OTA amplifier <NUM> when the initialization switch <NUM> is closed, such that the amplifier output <NUM> and the first and second amplifier inputs 106A-B are effectively ideally biased to the same voltage, when an offset voltage between the first and second amplifier inputs 106A-B is neglected. In reality, a small non-ideal offset voltage will appear across the first and second amplifier inputs 106A-B, however, its effect can be decreased or limited by the CDS sampling techniques described herein.

A CDS sampling instance is carried out as follows. First, the initialization switch E is closed to auto-zero the amplifier <NUM> and initialize the voltage on the storage capacitor Ci. Then, the initialization switch E is opened and-before or without again reinitializing the storage capacitor Ci by the next closing of the initialization switch E-the differential signal components Vx and Vy is respectively successively coupled to the first (e.g., non-inverting) input 106A of the amplifier <NUM>, such as via corresponding switches B and D, such as shown in the timing diagram of <FIG>, in which a "high" signal represents a closed switch. In response to each of the differential signal components Vx and Vy successively applied to the first input 106A of the amplifier <NUM>, the ADC performs a sampled analog-to-digital (A2D) conversion of the voltage present at the amplifier output <NUM>, yielding the pair of sampled digital values of the CDS sampling at times ADC1 and ADC2, such as shown in <FIG>. A difference between the individual digital values in the pair of sampled digital values of the CDS sampling is indicative of the differential signal present between the differential input signal nodes 104A-B. Offset voltage and <NUM>/f noise and other noise (such as the RTI noise of the ADC <NUM>) can be reduced or eliminated by the CDS sampling technique and arrangement such as described. Then, the OTA amplifier <NUM> can be powered down or even completely off, if desired, until the next CDS sampling instance is desired. The ADC <NUM> can similarly be powered down during this inactive time period until the next CDS sampling instance is desired. At that time, the OTA amplifier <NUM>, the ADC <NUM>, or both can be powered back up, and the storage capacitor Ci can be re-initialized, such as in the matter described above, for taking another CDS sampling without re-initializing the storage capacitor Ci between individual samples of the pair of samplings in the CDS sampling instance.

Because charging or discharging the input capacitance at the first input 106A of the OTA amplifier <NUM> can be viewed as an effective input current into the first input 106A of the OTA amplifier <NUM>, some degree of loading of the sensor or other signal source providing the input signal at the input nodes 104A-B may exist. Certain sensors may be affected by such an effective load current, which may affect sensor measurement accuracy. However, this can be ameliorated by including the buffer amplifiers 116A-B, each with a respective buffer amplifier input coupled to one of the differential signal inputs 104A-B, and each with a respective buffer amplifier output coupled via a respective one of switches A and C to the first input 106A of the amplifier <NUM>. The buffer amplifiers 116A-B can respectively be used for pre-charging the first input 106A (supplied by charge drawn from a power supply powering the buffer amplifier, rather than by charge drawn from the sensor or other signal source that may have its accuracy impacted by such an effective load current).

For example, as shown in the timing diagram of <FIG>, the differential signal component Vx can be first connected to the first input <NUM> of the amplifier <NUM> by closing the switch A, for pre-charging the first input <NUM> of the amplifier <NUM> via the buffer amplifier 116A. Then, switch A can be opened, and switch B can be closed to connect the actual signal component Vx to the first input <NUM> of the amplifier <NUM> for further settling, bypassing the buffer amplifier 116A, yielding immunity to noise performance or offset non-idealities of the buffer amplifier 116A.

Then, for example, as shown in the timing diagram of <FIG>, the differential signal component Vy can be first connected to the first input <NUM> of the amplifier <NUM> by closing the switch C, for pre-charging the first input <NUM> of the amplifier <NUM> via the buffer amplifier 116B. Then, switch C can be opened, and switch D can be closed to connect the actual signal component Vy to the first input <NUM> of the amplifier <NUM> for further settling, bypassing the buffer amplifier 116B, yielding immunity to noise performance or offset non-idealities of the buffer amplifier 116B. Buffer amplifiers 116A-B can be matched to each other to improve performance. Control circuitry <NUM> can be included in or coupled to the signal acquisition circuitry <NUM>, such as to provide the control signals for operating the switches shown, the ADC <NUM>, or both, such as to control operation as indicated in the timing diagram of <FIG>. The control circuitry <NUM> can include a dedicated digital hardware circuit, a programmable microcontroller circuit, or can use one or more of various other general-purpose or dedicated circuit implementations. The control circuitry <NUM> can control a multiplexer circuit, such as can include some or all of switches A, B, C, or D, shown in <FIG>.

The control circuitry <NUM> can be configured and operated to alter the sequencing of acquisition of the differential signal components Vx and Vy, such as alternatingly between successive CDS samplings. For example, the first CDS instance sampling pair could be acquired as Vx then Vy, the second CDS instance sampling pair could be acquired as Vy then Vx, the third CDS instance sampling pair could be acquired as Vx then Vy, and so forth, with operation of the ADC similarly alternatingly provided with a signal inversion to maintain a consistency in the differential digital signal output at the ADC output <NUM>.

The feedback network around the OTA amplifier <NUM> need not be a capacitive feedback network. Resistive feedback or a combination of resistive and reactive feedback can be provided, however, the capacitive feedback as shown advantageously does not require an ongoing quiescent current after the amplifier output <NUM> reaches the desired value.

The circuitry, apparatus, systems, and methods such as shown and describe herein can help provide several advantages. For example, initializing the storage capacitor Ci to the a bias voltage given by one component of the differential input signal (e.g., Vx) can help permit amplification of the differential signal (the difference between Vx and Vy) without overloading the amplifier <NUM>. In an example, the use of the CDS technique described herein can help reject offsets and low-frequency noise, particularly <NUM>/f noise, in the signal acquisition circuitry <NUM>. The CDS sampling can also help reject a common-mode signal as can be approximated by the differential signal component Vx. In an example, the ADC <NUM> can transform the two sampled values (based on Vx and Vy, respectively) into the digital domain, such that the differencing or correlation can be obtained using a simple digital subtraction of the two values. In an example, the pre-charge buffers 116A-B can supply the charge needed to shift the amplifier input capacitance between Vx and Vy, such that the sensor or other input signal source does not see this input-current loading at its output, to which the sensor may be sensitive. All of the amplifiers and the ADC can be efficiently power cycled, such as to power down one or all such components between CDS sampling instances, which can be carried out recurrently as often or as infrequently as needed by a particular application.

The above description includes references to the accompanying drawings, which form a part of the detailed description.

Geometric terms, such as "parallel", "perpendicular", "round", or "square", are not intended to require absolute mathematical precision, unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as "round" or "generally round," a component that is not precisely circular (e.g., one that is slightly oblong or is a many-sided polygon) is still encompassed by this description.

Claim 1:
A signal acquisition circuitry (<NUM>) for performing correlated double sampling, CDS, on a differential input signal, having components Vx and Vy, for low power signal processing, the circuitry comprising:
an amplifier (<NUM>), including or coupled to a feedback network configured to provide a closed-loop gain around the amplifier, the feedback network including or coupled to a storage capacitor (Ci), the amplifier being configured to provide gain between first (106A) and second (106B) amplifier inputs and an amplifier output (<NUM>), the storage capacitor (Ci) being located between the second amplifier input (106B) and a ground or other reference node (<NUM>);
an initialization switch (<NUM>) being located between the amplifier output (<NUM>) and the second amplifier input (106B), the initialization switch (<NUM>) being arranged to initialize the storage capacitor (Ci) before the CDS of the differential input signal;
control circuitry (<NUM>), configured to control operation of a multiplexer to sequentially couple the components Vx and Vy to the first amplifier input (106A) for respective first and second samplings of the CDS, the CDS of the differential input signal including settling and analog-to-digital sampling of each of the components Vx and Vy before reinitializing the storage capacitor (Ci) for a successive CDS sampling instance; and
an analog-to-digital converter, ADC, (<NUM>), coupled to the amplifier output (<NUM>), and wherein the control circuitry is configured to control the ADC (<NUM>) to perform analog-to-digital conversions of amplifier output samples of Vx and Vy for differencing of the digital representations of Vx and Vy to provide the correlation of the CDS in the digital domain.