Patent Description:
<NPL>) discloses quantum bit controller and observer circuits.

<CIT> discloses a system for quantum computing which includes a plurality of qubits and a control system. The control system generates control signals to control operation of the qubits and sets a bias point of each quit between a first position, in which the qubit is disabled and not responsive to the control signals, and a second positions in which the qubit is enabled and responsive to the control signals.

<NPL>) discloses controllable coupling of superconducting flux qubits.

In one aspect, the present invention provides a system according to claim <NUM>. In another aspect, the present invention provides a method according to claim <NUM>. Certain more specific aspects of the invention are set out in the dependent claims.

Examples described in this disclosure relate to a cryogenic-CMOS interface for controlling qubit gates. Controlling a quantum device requires generating a very large number of static and dynamic voltage signals, ideally at cryogenic temperatures in close integration with the quantum device. As used in this disclosure, the term "cryogenic temperature(s) means any temperature equal to or less than <NUM> Kelvin. This is a major challenge given that the cryo-environment strongly constrains power dissipation of any active electronics. In addition, the large number of voltage signals also need to be coupled to the qubit gates in the quantum computing device. This is because potentially many thousands of wires need to be connected to the voltage sources for driving the qubit gates in the quantum computing device. Moreover, conventionally qubits have been controlled with room temperature pulse generators that must generate large signals that are attenuated in the cryostat. The power required to overcome this attenuation, and furthermore the power needed to drive the cable impedance, is an impediment to scaling quantum computers.

Examples described in this disclosure relate to cryogenic control circuits and architecture for a quantum computing device. The control architecture includes an integrated circuit control chip, containing cryogenic control circuits, that is tightly integrated with the qubit plane. As an example, the control chip can be wire-bonded or flip-chip mounted to the qubit plane. In addition, the control chip stores a charge on a capacitor (that includes the interconnect capacitance) to generate a voltage bias. A single digital to analog converter may be used to set the charge on each capacitor, which at cryo-temperatures remains for a long time on account of the extremely low leakage pathways at these temperatures. Refresh of the charge can be made cyclically on timescale commensurate with qubit operation. The challenge associated with heat generated from attenuation is addressed by deploying a "charge-shuffle" circuit-moving charge between capacitors to generate a voltage pulse. The capacitance is reduced as much as possible via the tight integration between the cryogenic-CMOS control chip and the qubit plane. This tight integration, for example via chip-stack packaging approaches, can reduce the capacitance dramatically, thereby impacting the dissipated power.

In one example, the cryogenic-CMOS control chip may be implemented using the fully-depleted semiconductor on insulator (FDSOI) process. In one example, the FDSOI process based devices may include an undoped gate channel, an ultra-thin body, an ultra-thin buried oxide (BOX) below the source, drain, and the gate, and total dielectric isolation from the adjacent devices. The capacitors used for charge storage are implemented using on-chip devices. The back-gate or body bias of each transistor device can be used to configure the threshold voltage dynamically to account for effects associated with cooling. The control chip includes circuit blocks that are partitioned into domains that are given common back-gate bias. Example domains with separate bias include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back gate bias is provided for transistors with different aspect ratios.

The qubit plane may include topological computing gates that may operate at approximately <NUM> milli-Kelvin (~<NUM> mK). The quantum computing devices may process quantum information, e.g., qubits. A qubit may be implemented using various physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. The quantum state(s) may be encoded as a direction of spin, another aspect of spin, charge, energy, or excitation stages as part of a qubit, or a topological phase of superconducting matter. The example qubits may operate based on either low-frequency DC signals (e.g., bias currents) or high-frequency radio frequency signals (e.g., <NUM> signals) or based on a combination of both. In certain examples, microwave signals may be used to control the superconducting devices, including, for example the state of the quantum bits (qubits). Certain implementations of the gates for quantum bits (qubits) may require high-frequency microwave signals.

<FIG> shows a system <NUM> for controlling qubits in accordance with the invention. In this example, system <NUM> may include multiple stages, each of which may be configured to operate at a different temperature. Thus, system <NUM> may include stages <NUM>, <NUM>, and <NUM>. Stage <NUM> may include components configured to operate at the room temperature (e.g. the ambient temperature) or between <NUM> Kelvin and the room temperature. Stage <NUM> may include components configured to operate at or below <NUM> Kelvin and up to <NUM> Kelvin. Stage <NUM> may include components configured to operate at or around <NUM> milli-Kelvin (mK). Stage <NUM> may include a microcontroller <NUM> (or a microprocessor), a digital-to-analog converter (DAC) <NUM>, signal generators <NUM>, and measurement devices <NUM>. Microcontroller <NUM> may generate control signals configured to control qubits and other aspects of system <NUM>. DAC <NUM> may receive digital control signals from microcontroller <NUM> (or from other components) and convert those into an analog form. The analog signals may then be transmitted to the other stages, as needed. Signal generators <NUM> may include microwave signal generators and other clock signal generators, as needed. Measurement devices <NUM> may include instrumentation, such as spectrum analyzers.

With continued reference to <FIG>, stage <NUM> may include components configured to interconnect stage <NUM> with stage <NUM> in a manner that reduces thermal load and allows efficient connectivity between the components at room temperature and the components at <NUM> milli-Kelvin (mK). Thus, in this example, stage <NUM> may include component <NUM>, interconnect <NUM>, interconnect <NUM>, and interconnect <NUM>. In one example, component <NUM> may be implemented as high-electron-mobility transistor(s) (HEMT(s)) low noise amplifiers. Interconnects <NUM>, <NUM>, and <NUM> may be implemented as cables comprising conductors, such as niobium and copper. The conductors may be insulated within the interconnects using appropriate dielectric materials, such as polyimide.

Still referring to <FIG>, stage <NUM> may include a coupler <NUM>, readout multiplexing <NUM>, fast control multiplexing <NUM>, and qubits <NUM>. Coupler <NUM> may couple signals from the signal generators (e.g., signal generators <NUM>) to readout multiplexing <NUM>. Coupler <NUM> may also direct any reflected signals to component <NUM>. Readout multiplexing <NUM> and fast control multiplexing <NUM> may be implemented on a single control chip (sometimes referred to as the cryogenic-control CMOS chip). In one example, readout multiplexing <NUM> may be implemented using superconducting materials, such as niobium on an inert substrate, such as sapphire. Readout multiplexing <NUM> chip may contain multiple inductive, capacitive, and resistive elements of suitable sizes to form bank(s) of resonators. At cryogenic temperatures, resonator circuits exhibit superconductivity and produce a resonator with high quality factors. This may provide an efficient low loss frequency multiplexing mechanism. In one example, the cryogenic-CMOS control chip (e.g., an ASIC manufactured using a semiconductor technology, such as CMOS) may be mounted on the same substrate as the qubits (e.g., qubits <NUM>) and may be configured to operate at the same cryogenic temperature as the qubits (e.g., <NUM> mK).

<FIG> shows a common substrate <NUM> including a cryogenic-CMOS control chip <NUM>, a qubit chip <NUM>, and a resonator chip <NUM> in accordance with one example. Cryogenic-CMOS control chip <NUM> may be coupled to contact pads (e.g., contact pads <NUM> and <NUM>) via wire bonds (e.g., wire bonds <NUM> and <NUM>). Cryogenic-CMOS control chip <NUM> may further be coupled to contact pads (e.g., contact pads <NUM> and <NUM>) via wire bonds (e.g., wire bonds <NUM> and <NUM>). Cryogenic-CMOS control chip <NUM> may further be coupled to other contacts (e.g., contacts <NUM> and <NUM>) via wire bonds (e.g., wire bonds <NUM> and <NUM>). Qubit chip <NUM> may be coupled to contact pads (e.g., contact pads <NUM> and <NUM>) via wire bonds (e.g., wire bonds <NUM> and <NUM>). Qubit chip <NUM> may be coupled to resonator chip <NUM> via wire bonds (e.g., wire bonds <NUM> and <NUM>). Resonator chip <NUM> may be coupled to contacts (e.g., contacts <NUM> and <NUM>) via wire bonds (e.g., wire bonds <NUM> and <NUM>). Although not shown in <FIG>. , to mitigate unwanted heating of the quantum devices, the chip-packaging arrangement may also include thermal management by cementing each chip to separate gold-plated copper pillars that are in parallel thermal contact to the mixing-chamber stage of a dilution refrigerator. Although this example shows the tight integration between the control chip and the qubits via wire bonding, other techniques may also be used. As an example, the control chip may be flip-chip bonded to the substrate with the qubits. Alternatively, package-on-package, system-in-package, or other multi-chip assemblies may also be used.

In this example, the cryogenic-CMOS control chip may be implemented in <NUM>-FDSOI technology, an inherently low-power, low-leakage CMOS platform that is suited to cryogenic operation. Transistors in FDSOI may provide the utility of configuring a back-gate bias to offset changes in threshold voltage with temperature. This example platform provides high (<NUM>. 8V) and low (1V) voltage cells and also allows for individual back-gate control of n-type and p-type transistors or entire circuit blocks, a useful aspect in mixed-signal circuit design, such as the example control system.

<FIG> shows a block diagram of a control system <NUM> associated with fast control multiplexing <NUM> in accordance with one example. Control system <NUM> may be used to control the behavior of charge locking and fast gating (CLFG) cells <NUM> incorporated as part of the control chip. Control system <NUM> may include a serial peripheral interface (SPI) interface <NUM>, a waveform memory <NUM>, a voltage-controlled oscillator (VCO) <NUM>, a clock select multiplexer (CSEL) <NUM>, and finite state machines <NUM>. As shown, three different voltage levels may be coupled to the cells, including VHOLD, VHIGH, and VLOW. CSEL <NUM> is used to select the clock signal provided to the finite state machines. Additional details regarding the finite state machines and related registers are provided later.

In one example, control system <NUM> may be implemented as part of a cryogenic-CMOS control chip. <FIG> shows a floorplan of a cryogenic-CMOS control chip <NUM>, including a control system <NUM> (similar to control system <NUM> of <FIG>), in accordance with one example. Cryogenic-CMOS control chip <NUM> may include both digital and analog blocks. In this example, cryogenic-CMOS control chip <NUM> may include charge-locking and fast-gating (CLFG) cells and components corresponding to control system <NUM>. In this example, cryogenic-CMOS control chip <NUM> may include logic <NUM> and CLFG cells. In one example, logic <NUM> may include a series of coupled digital logic circuits that provide communication, waveform memory, and autonomous operation of the chip via two FSMs. Logic <NUM> may include a control system <NUM>, which may include an oscillator <NUM>, finite state machine(s) FSM and SPI interface (e.g., FSM + SPI interface) <NUM>, and memory <NUM>. Oscillator <NUM> may be implemented as a ring-oscillator with configurable length and frequency divider. Additional details regarding the FSM are provided later. Memory <NUM> may be configured as a <NUM>-bit register allowing arbitrary pulse-patterns to be stored. Tiled along the left and bottom edge of the chip may be a repeating analog circuit block "CLFG" that generates the static and dynamic voltages needed for controlling qubits. CLFG cells may include cells <NUM>, <NUM>, <NUM>, and <NUM>. In the example described here, although the CLFG cells are realized on a single die, they could be formed on a number of dies packaged together or otherwise interconnected. Although <FIG> shows a certain floor plan for cryogenic-CMOS control chip <NUM>, the chip may have a different floor plan. In addition, although <FIG> shows certain number of components arranged in a certain manner, cryogenic-CMOS control chip <NUM> may include additional or fewer components arranged differently.

<FIG> shows a CLFG cell <NUM> in accordance with one example. CLFG cell <NUM> may be configured to lock charge and provide a voltage output. Each CLFG cell <NUM> may correspond to any of N number of cells. CLFG cell <NUM> may include two portions: a portion <NUM> for coupling a static voltage to the output terminal (labeled as GATE<N>) and a portion <NUM> for coupling a dynamic voltage (based on one of voltage VHIGH or voltage VLOW) to the output terminal. Portion <NUM> of CLFG cell <NUM> may include a switch <NUM>, which may be operated in response to a signal GLOCK, N. This signal may be provided under the control of an appropriate finite state machine or another type of control logic or instructions. When switch <NUM> is closed the voltage VHOLD may be coupled to one plate of the capacitor labeled CPULSE, N, which represents the on-chip capacitance. Portion <NUM> of CLFG cell <NUM> may further include a switch <NUM> and a switch <NUM>. CLFG cell <NUM> may further include an inverter <NUM>. CLFG cell <NUM> may be configured such that only one of these switches (switch <NUM> and switch <NUM>) is closed at a time. In this example, the signal that is labeled GFG,N may control switch <NUM> and an inverted version of this signal (e.g., inverted by inverter <NUM>) may control switch <NUM>. This way at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the second plate of capacitor labeled CPULSE, N, which represents the on-chip capacitance.

With continued reference to <FIG>, CP may be the sum of parasitic capacitances due to the wiring in the cryogenic-CMOS control chip and the qubit chip(s) and the wires (or other interconnects) used to interconnect the two. A cell may first be selected for configuration by an on-chip finite state machine (FSM), which connects an external voltage source to the input terminal (labeled IN in <FIG>) of CLFG cell <NUM>, raising its potential to VHOLD. In this example, a single channel of a room temperature digital-to-analog converter (DAC) may be used as the source, and the FSM sequentially switches each CLFG cell into contact with this voltage-bias to energize the capacitors that will then lock the charge required to generate a static voltage at the high-impedance output. The circuit incorporates the on-chip capacitance CPULSE and the parasitic capacitance CP, which includes contributions from the bond-pads, bond-wires, and gate-interconnect on the qubit chip. Following charge-up, switch <NUM> is opened by the FSM (e.g., by de-asserting the GLOCK, N signal) leaving the charge on the capacitors and the qubit gate floating. This locked charge then remains even as CLFG cell <NUM> is de-selected, establishing a static voltage that can be used for configuring the offset bias of the qubit device. Although <FIG> shows a certain number of components arranged in a certain manner, CLFG cell <NUM> may include additional or fewer components arranged differently.

<FIG> shows example waveforms <NUM> associated with the operation of CLFG cell <NUM>. For dynamic control, a voltage pulse is required to rapidly change the potential of a gate and energy state of the qubit. Generating such a pulse remotely from the qubit plane requires significant energy since the generator must drive the cable impedance, even if power is not dissipated at the end of the open line. Alternatively, a sizable voltage pulse can be generated with little energy by the redistribution of local charge in a circuit with small capacitance. In this example, this concept is exploited to enable the dynamic operation of CLFG cell <NUM>. Under the control of a second FSM, cells are selected for pulsing and a pre-loaded pulse-pattern, stored in the register memory, is applied to the switch GFG.

Switches <NUM> and <NUM> are controlled in a manner to toggle the lower plate of capacitor CPULSE between two voltage sources VHIGH and VLOW. These sources can be external to the chip or derived from local, pre-charged capacitors. With the potential of the lower plate of the CPULSE switched to VLOW or VHIGH, charge is induced on the top-plate, changing the output voltage VOUT that is referenced with respect to ground.

In this example, the magnitude of the pulse is given by ΔVPULSE = (CPULSE/(CP + CPULSE))(VHIGH - VLOW), and the power dissipated PPULSE is given by the total capacitance, pulse frequency f, and voltage of the two levels, PPULSE = ((CP * CPULSE)/(CP + CPULSE))(VHIGH - VLOW)<NUM>f. Because CP and CPULSE are (pF) chip-scale capacitances, they require very little power to charge.

<FIG> and <FIG> show various blocks associated with a cryogenic-CMOS control chip <NUM> in accordance with one example. As explained earlier, cryogenic-CMOS control chip <NUM> may include both analog and digital components. In this example, cryogenic-CMOS control chip may include an analog-digital converter (ADC) buffer <NUM>, an ADC <NUM>, an ADC SRAM <NUM>, and an ADC control <NUM>. Cryogenic-CMOS control chip <NUM> may further include a clock driver <NUM>, a waveform generator <NUM>, and reference and bias generators <NUM>. These components may be coupled via various buses. Each bus may include at least one signal line. As shown in <FIG> and <FIG>, cryogenic-CMOS control chip <NUM> may receive various external signals, including clock signals, various voltages, and control signals. As shown, some of the clocks are externally generated and received via pins associated with the control chip.

With continued reference to <FIG>, cryogenic-CMOS control chip <NUM> may further include main control and registers <NUM> and various miscellaneous blocks <NUM>. Main control and registers <NUM> may include a serial-peripheral interface (SPI), which may allow communication with external processors. Miscellaneous blocks <NUM> may include a sample-and-hold (S&H) block <NUM>, a comparator <NUM>, and a radio frequency (RF) multiplexer (MUX) <NUM>. RF MUX <NUM> may allow selection between two radio frequency signals (RFIN1 and RFIN2). In this example, there is an advanced peripheral block clock (APBCLK) input for main control and registers <NUM> and a separate APBCLK input pin for the charge-locking and fast-gating block <NUM>. As shown in <FIG>, for charge-locking and fast-gating <NUM>, there is also the ability to switch to the local oscillator (e.g., VCO <NUM>). The local oscillator can also be divided down through a configuration register. The SPI clock (SCLK) comes from the SPI master. In this example, there is a clock ratio requirement between APBCLK and SCLK from the SPI master. In one example, APBCLK must be >= <NUM> * SCLK. To ensure proper clocking, a clock domain crossing (CDC) logic is arranged between the SCLK and the APBCLK and another CDC logic is arranged between the APBCLK and the divided oscillator clock.

<FIG> shows a diagram of some of the aspects of charge-locking and fast-gating <NUM>. Charge-locking and fast-gating <NUM> may include main control and registers <NUM>, a voltage controlled oscillator (VCO) <NUM>, and CLFG cell array <NUM>. Control and registers <NUM> may include an SPI interface. Control and registers <NUM> may include a register read/write block, which in turn may be coupled to a register file. VCO <NUM> may be configured to provide another clock signal for use with some of the aspects of charge-locking and fast-gating <NUM>. CLFG cell array <NUM> may include CLFG cells <NUM> and <NUM>, each of which may be similar to CLFG cell <NUM> of <FIG>.

<FIG> shows a block diagram of charge-locking and fast-gating (CLFG) <NUM> in accordance with one example. CLFG <NUM> may include SPI interface <NUM>, coupled via a bus (e.g., APB) to a register read/write interface <NUM>, which in turn may be coupled to registers <NUM> (e.g., registers may be included as part of a register file). CLFG <NUM> may further include finite state machine <NUM>, which may be configured to receive input from the registers and provide output signals to CLFG cell array <NUM>, which in turn may provide the voltage to the qubits. CLFG <NUM> may further include an oscillator <NUM>, a frequency divider (FDIV) <NUM> and a multiplexer <NUM>. Multiplexer <NUM> may receive the APB clock as one input and the frequency divider output as the other input. This way, in this example, the finite state machines can run off either APBCLK or a clock signal from the local oscillator. A clock control module may be used to divide down the local oscillator clock from integer values of <NUM> to <NUM>, and multiplexer <NUM> may be used to allow switching between the APBCLK and the divided oscillator clock. There are no duty cycle requirements on the divided clock. The clock output of the clock control module is referred to as XCLK and it is used to clock the finite state machines.

Table <NUM> below lists some of the signals and their descriptions for the cryogenic-CMOS control chip.

Table <NUM> lists some of the registers associated with the cryogenic-CMOS control chip. Since the description of most of the registers is self-explanatory, only some of the registers, and their functionality, are described to explain the operation of the cryogenic-CMOS control chip.

While Table <NUM> shows certain registers and their arrangement, additional or fewer registers may be used. In addition, the information presented in the tables may be communicated to the cryogenic-CMOS control chip via other modalities besides the registers. As an example, special instructions may be used to encode the information included in the registers. The architecture enabled by registers described in Table <NUM> assumes <NUM> charge-locking fast-gating (CLFG) cells. In this example, each CLFG cell can be DC charged independently and can be fast-pulsed according to the waveform stored in FGSRs registers. In this implementation <NUM> bits can be stored in four <NUM> bit registers (e.g. registers FGSR0-<NUM>) and any of the charge-locking fast-gating cells can be fast-pulsed according to the bit pattern stored in these registers. The bit pattern can be repeated continuously or played once under the control of the FSM. This implementation caters for two level pulsing, it can however be extended to multilevel pulsing. In this example architecture, the REG_CTL1 register described in Table <NUM> includes information that is used by the activated finite state machine to initiate and complete charging of the cells. As an example, bit <NUM> of this register controls when the counter for the FGSR select is enabled and incremented per clock cycle of the XCLK clock until it reaches <NUM> and then the counter rolls over. As another example, bits <NUM> and <NUM> of the REG_CTL1 register control whether a full DC charge sequence occurs to all of the <NUM> cells or whether a selective DC charge sequence occurs on only a subset of the <NUM> cells.

<FIG> shows an example of a fast gating circuit <NUM>. As described earlier, as part of Table <NUM>, four <NUM>-bit registers may control the output of fast gating circuit <NUM>. Fast gating circuit <NUM> may include a counter <NUM>, a multiplexer <NUM>, which may be coupled to receive the output of counter <NUM> as one input and the value corresponding to register REG_CTL<<NUM>> as another input. Fast gating circuit <NUM> may further include AND gate <NUM>, multiplexer <NUM>, and gate <NUM>, which may be coupled to each other as shown in <FIG>. These logic elements may further receive the signals shown in <FIG>. Counter <NUM> selects the bit position of the <NUM>-bit value to be output on the CL_FG terminal. In this example, this is a <NUM>-to-<NUM> mux. Each clock cycle (e.g., corresponding to the clock XCLK shown in <FIG>), counter <NUM> is incremented by <NUM>. Counter <NUM> wraps back to <NUM> and continues counting. The value of the bit stored in REG_CTL[<NUM>] enables counter <NUM>. Thus, in this example when REG_CTL[<NUM>]=<NUM>, the counter remains at <NUM> and does not increment. If the charge locking state machine is not idle, then the fast gating output CL_FG is <NUM>. The counter continues to increment in this case as long as REG_CTL[<NUM>]=<NUM>.

With continued reference to <FIG>, in one example, the programming sequence to update the <NUM>-bit FGSR and start a new fast gating sequence is as follows: (<NUM>) clear REG_CTL1[<NUM>] to hold counter at <NUM> or set REG_CTL1[<NUM>] to stop XCLK, (<NUM>) write new values to the four <NUM>-bit FGSR registers, and (<NUM>) set REG_CTL1[<NUM>] to allow counter to increment or clear REG_CTL1[<NUM>] to resume XCLK. In one example, the FG output can also be overridden. When REG_CTL1[<NUM>]=<NUM>, the CL_FG output equals REG_CTL1[<NUM>]. Although <FIG> shows fast gating circuit <NUM> with a certain number of components arranged in a certain manner, fast gating circuit <NUM> may include additional or fewer components arranged differently. In addition, other signals may be used to provide additional or less control.

<FIG> shows finite state machines <NUM> in accordance with one example. In this example, finite state machines <NUM> include two finite state machines: FSM A and FSM B. Each of the finite state machines is configured for DC charging of the CLFG cells (e.g., CLFG cell <NUM>). FSM A corresponds to a finite state machine that is configured to concurrently charge only those CLFG cells that are enabled according to the bits in the CL_EN register. FSM B corresponds to a finite state machine that is configured to sequentially charge all of the CLFG cells in the CLFG array (e.g., all of the <NUM> cells in a CLFG array that has <NUM> cells). In this example, bit values stored in a register (e.g., bits <NUM> and <NUM> of the <NUM> bit register REG_CTL1 corresponding to the field BEGIN_CHRG described in Table <NUM>) determine which of the two finite state machines is active. In this example, when the BEGIN_CHRG field transitions from <NUM> to <NUM> FSM A is activated; alternatively, when the BEGIN_CHRG field transitions from <NUM> to <NUM> FSM B is activated. The output signal from both FSM A and FSM B is provided as the CHRG signal, which is coupled to one of the inputs of multiplexer <NUM>. The other input of multiplexer <NUM> comprises the bit value stored in REG_CTL<<NUM>> (described in Table <NUM>). The output of multiplexer <NUM> is the global DC charge signal and is labeled as CL_CHRG. The value of the bit <NUM> (e.g., REG_CTL<<NUM>>) determines whether the output of FSM A and FSM B is provided as the DC charge signal or whether the DC charge signal is user selected to be the value of bit <NUM> of the REG_CTL register described in Table <NUM>.

With continued reference to <FIG> upon activation, FSM A starts in the IdleA0 state and transitions to the COUNTDOWN A state. As part of this transition, FSM A asserts the CHRG signal and begins a countdown to DC charge those CLFG cells that are enabled. During the entire operation of FSM A, the CL_EN value stays the same as was specified by a user previously. In this example, ith CLFG cell is enabled when the local enable signal for a specific CLFG cell (e.g., CL_EN<i> = <NUM>) is high. Thus, by gating the CHRG signal, the local enable signal ensures that the CLFG cell is charged only when it is enabled to be charged. After completion of the charging, FSM A enters idle state IdleA1. Table <NUM> below shows example correspondence between the transitions/states referenced to in <FIG> for FSM A and the example values of the bits and other signals.

Still referring to <FIG>, upon activation, FSM B enters the START_CHRG state and assuming there are <NUM> CLFG cells, starts charging of the <NUM>nd CLFG cell when CL_EN<<NUM>> bit is set to <NUM> and each of the other enable bits is set to <NUM>. As part of this process, FSM B enters the COUNTDOWN B state and counts down the clock cycles required for sequential charging of the CLFG cells (e.g., the DCSR clock cycles). Except for in states START_CHRG and COUNTDOWN B, during the entire operation of FSM B, the CL_EN value stays the same as was specified by a user previously. When CL_EN<<NUM>> bit is set to <NUM>, and rest of the enable bits are set to <NUM>, the DC charging of <NUM>nd CLFG cell finishes, and the DC charging of <NUM>st CLFG cell starts. In this example, these steps are repeated until all <NUM> CLFG cells are charged. Then, the FSM B transitions to an idle state (e.g., IdleB <NUM> state). Table <NUM> below shows example correspondence between the transitions/states referenced to in <FIG> for FSM B and the example values of the bits and other signals.

Although <FIG> shows specific finite state machines operating in a certain manner, other state machines may also be used. Although Tables <NUM> and <NUM> refer to specific bits and signals and respective values for the two finite state machines, other bits and signals and their respective values may also be used. In addition, the functionality associated with the state machines may be accomplished using other logic or instructions.

<FIG> and <FIG> show an example system <NUM> which may be used to generate enable signals as part of an example cryogenic-CMOS control chip. An FSM, described earlier, may be used to interface with system <NUM>, which may be used to generate enable signals that are used to select the CLFG cell that is charged. This example also assumes that there are <NUM> CLFG cells (arranged in a grid including <NUM> rows and <NUM> columns) that need to be controlled. System <NUM> may include a master logic and clock portion <NUM>, a row decoder <NUM>, and a column decoder <NUM>. Master logic and clock portion <NUM> may include circuits and logic configured to store and interpret instructions or commands in a manner similar to a memory controller. Row decoder <NUM> may be configured to receive a row address from master logic and clock portion <NUM> and assert one or more of signals labeled as R<NUM> to R<NUM>. Column decoder <NUM> may be configured to receive a column address from master logic and clock portion <NUM> and assert one or more of signals labeled as C<NUM> to C<NUM> and D<NUM> to D<NUM>.

Referring now to <FIG>, system <NUM> may further include a bus system to couple the signals generated by row decoder <NUM> and column decoder <NUM> to a circuit <NUM>. Circuit <NUM> may be configured to generate a signal, labeled OUTI,FG at its output terminal. This signal may be coupled to a qubit gate <NUM>. Circuit <NUM> is an example implementation similar to the "direct mode" of the CLFG cells described earlier. Thus, in this example, circuit <NUM> can be connected to voltage bus VLFG or VHFG when a respective row (RJ) signal and a respective column (CI) signal is high and the drive line (D) signal is high or low, respectively. Circuit <NUM> may also be implemented as an array of CLFG cells (e.g., as shown in <FIG> and described earlier). Although <FIG> shows system <NUM> as having certain components arranged in a certain manner, there could be more or fewer components arranged differently.

<FIG> shows a CLFG cell array <NUM> in accordance with one example. As an example, CLFG cell array <NUM> may correspond to CLFG cell array <NUM> of <FIG> and may be included as part of a cryogenic-CMOS control chip. In this example, CLFG cell array <NUM> may include <NUM> CLFG cells (e.g., CLFG cells <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>). Each of these CLFG cells may be configured to generate one of the OUTCL signals, which may be used to provide control or other type of voltages to qubits. Each CLFG cell may receive signals labeled as CL_FG, CL_CHRG, VICL, VHFG, and VLFG. These signals are described more in detail with respect to <FIG> and <FIG>. In addition, some of these signals have also been described earlier as part of the description associated with the cryogenic-CMOS control chip. Each CLFG cell may also receive an enable signal (e.g., CL_EN<<NUM>>, CL_EN<<NUM>>, CL_EN<<NUM>>, CL_EN<<NUM>>, or CL_EN<<NUM>>, as shown in <FIG>). The enable signals may allow selective or sequential DC charging as explained earlier with respect to the finite state machines description in <FIG>. Each of the CLFG cells shown in <FIG> may also include electrostatic discharge (ESD) circuitry, including ESD circuits <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The CLFG cells may operate either in the capacitive mode only or in a dual mode, including both the capacitive mode and the direct mode. As an example, CLFG cell array <NUM> may consist of <NUM> CLFG cells-<NUM> CLFG cells configured to operate in the capacitive mode and <NUM> CLFG cells configured to operate in the direct mode. In one example, half of each type of CLFG cells may also incorporate a custom analog pad with a reduced ESD protection to further minimize leakage through the standard pad structure. Although <FIG> shows CLFG cell array <NUM> as having certain components arranged in a certain manner, there could be more or fewer components arranged differently.

<FIG> shows an example of CLFG cell <NUM> configured to operate in a capacitive mode in accordance with one example. Unless indicated otherwise, the signals referred to in <FIG> have the same meaning as described earlier with respect to <FIG> and Tables <NUM> and <NUM>. CLFG cell <NUM> is configured in a similar manner as CLFG cell <NUM> of <FIG>. CLFG cell <NUM> is configured to lock charge and provide a voltage output at the output terminal (OUT) associated with the CLFG cell. Each CLFG cell <NUM> may correspond to any of N number of cells. A dynamic voltage (based on one of voltage received via the VHFG terminal (referred to as VHIGH in <FIG>) or a voltage received via the VLFG terminal (referred to as VLOW in <FIG>)) may be coupled to the output terminal. CLFG cell <NUM> may include a switch <NUM>, which may be operated in response a signal CL_EN<N> signal. This signal may be provided under the control of an appropriate finite state machine or another type of control logic as described with respect to <FIG>. When switch <NUM> is closed the voltage (referred to as VHOLD in <FIG>) received via the input terminal (IN) on signal line VICL may be coupled to one plate of the capacitor labeled CPULSE, N, which represents the on-chip capacitance. CLFG cell <NUM> may further include a switch <NUM> and a switch <NUM>. CLFG cell <NUM> may further include an inverter <NUM>. CLFG cell <NUM> may be configured such that only one of these switches is closed at a time. In this example, the signal that is labeled CL_EN<N> may control switch <NUM> and an inverted version of this signal (e.g., inverted by inverter <NUM>) may control switch <NUM>. This way at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the second plate of capacitor labeled CPULSE, N, which represents the on-chip capacitance. CLFG cell <NUM> may further include an ESD <NUM> coupled to the output terminal (OUT). CLFG cell <NUM> operates only in the capacitive mode since the output voltage supplied to a qubit gate is provided via the capacitive arrangement shown in <FIG>. Although <FIG> shows certain number of components arranged in a certain manner, CLFG cell <NUM> may include additional or fewer components arranged differently. As an example, CLFG cell <NUM> may not include ESD <NUM>.

<FIG> shows an example of CLFG cell <NUM> configured to operate in a dual mode including both a capacitive mode and a direct mode in accordance with one example. Unless indicated otherwise, the signals referred to in <FIG> have the same meaning as described earlier with respect to <FIG> and Tables <NUM> and <NUM>. CLFG cell <NUM> is configured to lock charge and provide a voltage output at the output terminal (OUT) associated with the CLFG cell. Each CLFG cell <NUM> may correspond to any of N number of cells. In the capacitive mode (enabled by the assertion of the signal labeled CL_MODE asserted via switch <NUM>), a dynamic voltage (based on one of voltage received via the VHFG terminal (referred to as VHIGH in <FIG>) or a voltage received via the VLFG terminal (referred to as VLOW in <FIG>)) may be coupled to the output terminal. CLFG cell <NUM> may include a switch <NUM>, which may be operated in response to the CL_EN<N> signal. This signal may be provided under the control of an appropriate finite state machine or another type of control logic as described with respect to <FIG>. When switch <NUM> is closed the voltage (referred to as VHOLD in <FIG>) is received via the input terminal (IN) on signal line VICL may be coupled to one plate of the capacitor labeled CPULSE, N, which represents the on-chip capacitance. CLFG cell <NUM> may further include a switch <NUM> and a switch <NUM>. CLFG cell <NUM> may further include an inverter <NUM>. CLFG cell <NUM> may be configured such that only one of these switches-<NUM> and <NUM>-is closed at a time. In this example, the signal that is labeled CL_EN<N> may control switch <NUM> and an inverted version of this signal (e.g., inverted by inverter <NUM>) may control switch <NUM>. This way at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the second plate of capacitor labeled CPULSE, N, which represents the on-chip capacitance. When CL_MODE signal is asserted, CLFG cell <NUM> operates in the capacitive mode since the output voltage supplied to a qubit gate is provided via the capacitive arrangement shown in <FIG>.

With continued reference to <FIG>, CLFG cell <NUM> may operate in the direct mode when the CL_MODE signal is de-asserted. Thus, when the CL_MODE signal is de-asserted, switch <NUM> is closed and depending on a status of the CL_EN<N> signal, either switch <NUM> or switch <NUM> is closed. As a result, at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the same terminal to which the VIN voltage via the input terminal (IN) is coupled. CLFG cell <NUM> may further include an ESD <NUM> coupled to the output terminal (OUT). Although <FIG> shows certain number of components arranged in a certain manner, CLFG cell <NUM> may include additional or fewer components arranged differently. As an example, CLFG cell <NUM> may not include ESD <NUM>.

In the cases of both CLFG cell <NUM> and CLFG cell <NUM>, once the capacitors are charged, the low leakage in the cryogenic environment ensures that they need to be refreshed less frequently. Each of the CLFG cells may receive voltage from a single DAC. The single DAC voltage may be used to charge all of the CLFG cells (e.g., <NUM> CLFG cells in the example described earlier) using a similar technique as rasterizing a display. Thus, in this example, the DAC voltage is provided to a capacitor by closing a switch in the pathway between the DAC voltage line and the capacitor; after the capacitor is charged, the switch is opened and the DAC voltage is used to charge the next capacitor in a round-robin fashion. By using a shared DAC, the number of the input/output lines between the control chip, including the CLFG cell array, and the room temperature electronics is significantly reduced. As described earlier, the interconnections between the cryogenic-CMOS control chip and the qubit plane are formed using wire bonding, flip-chip bonding or other low impedance interconnect techniques.

<FIG> shows example waveforms <NUM> associated with the signals for CLFG cell <NUM> and CLFG cell <NUM>. In this example, each of CLFG cell <NUM> and CLFG cell <NUM> is shown as operating in relation to the clock labeled XCLK. The CL_CHRG signal is asserted for a time period based on the clock cycles (or another metric) specified in a control register (e.g., REG_DCSR) associated with the cryogenic-CMOS control chip. The CL_FG control signal is used for charge shuffling. For CLFG cell <NUM> and for CLFG cell <NUM>, whenever this control signal is high, the voltage at the OUTCL terminal pulses between VICL + the difference between VHIGH voltage and the VLOW voltage. Whenever the CL_FG control signal is low, both CLFG cell <NUM> and CLFG cell <NUM> operate in the DC mode, such that the output voltage (represented by the waveform labeled OUTCL in DC MODE) is held at a voltage to which the capacitor is initially charged (e.g., by the CL_CHRG signal) and it, in the absence of a refresh, may dissipate over time. The waveform labeled OUTCL in CAPACITIVE MODE shows the output signal of CLFG cell <NUM>. This same waveform also shows the output of CLFG cell <NUM> when it operates in the capacitive mode. The waveform labeled OUTCL in DIRECT MODE shows the output signal of CLFG cell <NUM> when it operates in the direct mode. Each of these modes are explained earlier with respect to <FIG> and <FIG>.

With continued reference to <FIG>, a fast gating operating cycle using CLFG <NUM> in the capacitive mode includes a DC charging of the storage capacitor, followed by a series of pulses. In one example, the DC charging period is determined by the REG_DCSR value. The period and number of the pulses is determined by the content of the CL_FGSR register (explained earlier), which is set to <NUM> bits. In this example, the contents of this register are read one bit at a time (e.g., by a waveform generator) and applied as a control signal labeled: CL_FG. When using direct drive mode, fast gating consists of a series of pulses where the output is directly connected to VLFG or VHFG. In the direct drive mode, the charge cycle is still present and behaves the same as a value of "<NUM>" on CL_FGSR. Each of these modes is explained earlier with respect to <FIG> and <FIG>.

<FIG> shows example waveforms <NUM> associated with the simulation of CLFG cell <NUM> in the capacitive mode. The waveform labeled OUTCL represents the simulated output signal of CLFG cell <NUM> when operating in the capacitive mode. The waveform labeled CL_EN corresponds to the enable signal, which is used to enable a CLFG cell for charging. The CL_CHRG signal is used to charge the capacitor (or capacitors) associated with a CLFG cell. As explained earlier, the CL_CHRG signal is asserted for a time period based on the clock cycles (or another metric) specified in a control register (e.g., REG_DCSR) associated with the cryogenic-CMOS control chip. For CLFG cell <NUM>, whenever CL_FG control signal is high, the voltage at the OUTCL terminal pulses between VICL + the difference between VHIGH voltage and the VLOW voltage. The VICL voltage corresponds to the voltage at an input terminal of the CLFG cell, which may be received from a DAC (as explained earlier). The VHIGH voltage is received via the VHFG terminal and the waveform is also labeled as VHFG in <FIG>. The VLOW voltage is received via the VLFG terminal and the waveform is also labeled as VLFG in <FIG>.

With continued reference to <FIG>, portion <NUM> of the OUTCL waveform shows the locking of a DC voltage (e.g., <NUM> Volts) in the CLFG cell. Portion <NUM> of the OUTCL waveform shows fast gating of the voltages to generate pulses that can be used as control signals for qubits. Portion <NUM> shows restored locked DC voltage after the generation of the pulses. Portion <NUM> shows the voltage at the OUTCL terminal when the locked DC voltage is not refreshed or restored. Portion <NUM> shows the locking of a different level of DC voltage (e.g., <NUM> Volts) from the level of voltage locked in portion <NUM>. Portion <NUM> shows the fast gating of the voltages to generate pulses, having a different magnitude, which can also be used for controlling qubits or other such devices. Although <FIG> shows the OUTCL waveform as having rectangular pulses, the pulses may have a different shape. Although <FIG> shows the OUTCL waveform having two different magnitudes, the OUTCL waveform may have other variations in the magnitude. Similarly, the frequency of pulsing of the OUTCL waveform may also be controlled via the cryogenic-CMOS control chip described earlier. In addition, the OUTCL waveform may be used to modulate a high frequency signal, for example, a microwave tone to generate control signals for a qubit gate or another type of qubit device.

<FIG> shows a first view <NUM> and a second view <NUM> of an active area of an example qubit device <NUM> during a charge locking test. Qubit device <NUM> may be a gallium-arsenide (GaAs) based quantum dot device. In this example, as shown in view <NUM> and view <NUM>, multiple signals may be used to control the quantum dot. The cryogenic-CMOS control chip described earlier may be used to generate any of the control signals using either the capacitive mode or the direct mode associated with the CLFG cells described earlier. The signals for controlling the qubit may include a left wall (LW) signal, a left plunger (LP) signal, a center wall (CW) signal, a right plunger (RP) signal, and a right wall (RW signal). Additional signals related to sensing the quantum dot <NUM> in the qubit gate may include sensing dot top gate (SDT), sensing dot plunger (SDP), and sensing dot bottom gate (SDB). In this example, as shown in view <NUM>, the potential of control signals LW, LP, CW, RP, and RW may be locked using five CLFG cells based on a programmed finite state machine. Although <FIG> shows qubit device <NUM> with certain control signals, other types of qubit devices having other control signals may also be subjected to the voltages generated by the cryogenic-CMOS control chip described earlier.

<FIG> shows a view <NUM> of changes in the voltage and the current associated with the quantum point contact (QPC) in accordance with one example. Graph <NUM> shows the change in the QPC current with time. Graph <NUM> shows the change in the QPC current as a function of the change in the left wall voltage. Graph <NUM> shows the change in the cryogenic-CMOS control chip held voltage with time.

<FIG> shows example waveforms <NUM> corresponding to a cryogenic-CMOS control chip during testing of the fast gating operation with a quantum dot. Example waveform <NUM> corresponds to the readout signal when the fast gating is performed at <NUM>. Example waveform <NUM> corresponds to the readout signal when the fast gating is performed at <NUM>. Example waveform <NUM> corresponds to the readout signal when the fast gating is performed at <NUM>. The frequency can be varied using a frequency divider. The waveforms do not share a common time scale. Although <FIG> shows a certain duty cycle and amplitude of the voltage pulses associated with the waveforms, the duty cycle and the amplitude can be varied by the cryogenic-CMOS control chip. This advantageously removes the need for the control of the qubit gates from the room temperature equipment.

Controlling of the qubit gates from the room temperature would require attenuating the voltage pulses generated at the room temperature, resulting in a requirement to dissipate a large amount of heat from the room temperature voltage pulses. In addition, rather than requiring the voltage signals from the room temperature to deal with the load of a meter long (or longer) cable (e.g., <NUM> Ohms transmission line with greater than <NUM> pF in terms of the capacitive load), the cryogenic-CMOS control chip only needs to handle the capacitance of the flip-chip bonds and the very short interconnects between the control chip and the qubit gates. This capacitance may be as low as <NUM> pF. This allows the cryogenic-CMOS control chip to control the state of thousands of qubits without requiring large amounts of dissipation of heat. In addition, the power dissipation from fast gating is small and thus it allows the control chip to manage potentially thousands of qubits efficiently. In terms of the power requirements for the control of the qubits, in one example, assuming the readout clock frequency is set at <NUM>, the qubit interconnect has a capacitance of <NUM> pF, then the power consumption per <NUM> qubit gates for a <NUM> volt pulse is <NUM>µW. Assuming <NUM> gates per qubit, <NUM> mW of power can be used to control <NUM>,<NUM> qubits at a clock frequency of <NUM> or <NUM> qubits at a clock frequency of <NUM>.

<FIG> shows example readout waveforms <NUM> corresponding to the readout signal through a quantum dot during testing of the cryogenic-CMOS control chip. Waveforms <NUM> are generated when the CLFG cell voltages VHIGH and VLOW are used to generate the pulses for controlling the quantum dot and the voltage on the sensing dot plunger (SDP) gate is swept. Waveform <NUM> shows the variation in the VHIGH voltage and waveform <NUM> shows the variation in the VLOW voltage. Waveform <NUM> shows the pulses applied to the CLFG cell.

As described earlier, in one example, the cryogenic-CMOS control chip may be implemented using the fully-depleted semiconductor on insulator (FDSOI) process. In one example, the FDSOI process-based devices may include an undoped gate channel, an ultra-thin body, an ultra-thin buried oxide (BOX) below the source, drain, and the gate, and complete dielectric isolation from the adjacent devices. As explained earlier, FDSOI process-based devices may include both digital and analog devices (e.g., transistors or other devices). <FIG> shows an FDSOI digital device <NUM> in accordance with one example. FDSOI digital device <NUM> may include a substrate <NUM>. In this example, substrate <NUM> may be a silicon-on-insulator (SOI) substrate. A deep n-well <NUM> may be formed in substrate <NUM> by doping substrate with an n-type dopant. Additional wells may be formed in substrate <NUM> and deep n-well <NUM>. As an example, p-well <NUM> and n-well <NUM> may be formed. Next, using several lithographic steps, transistor device <NUM> and transistor device <NUM> may be formed. In this example, transistor device <NUM> is a p-type transistor with a gate channel <NUM> formed above a box <NUM>. Transistor device <NUM> may further include p+ type source/drain regions and contacts S and D to the source/drain. In this example, transistor device <NUM> is an n-type transistor with a gate channel <NUM> formed above a box <NUM>. Transistor device <NUM> may further include n+ type source/drain regions and contacts S and D to the source/drain. The capacitors used for charge storage may be implemented using such transistor devices. Various types of devices and regions may be isolated using shallow trench isolation (STI) regions formed using a dielectric. Example STI regions formed in FDSOI digital device <NUM> include STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, and STI <NUM>.

With continued reference to <FIG>, the back-gate or body bias of each transistor device can be used to configure the threshold voltage dynamically to account for effects associated with cooling. Thus, in this example, FDSOI digital device <NUM> includes back gate bias via the NBG terminal for the n-type devices and back gate bias via the PBG terminal for the p-type devices. In this example, while FDSOI digital device <NUM> includes the ability to vary the back-gate bias for both the n-type and the p-type devices, the back gate voltage of the n-type devices is not allowed to be lower than the back-gate voltage of the p-type devices.

Still referring to <FIG>, the back-gate or body bias of each transistor device can be used to configure the threshold voltage dynamically to account for the effects associated with the cooling of the chip in a cryogenic environment. The transistor devices and the related control circuits are designed such that using the back-gate bias control, the threshold voltage of the transistor devices can be tuned despite the huge change in the operating temperature of the transistor devices. The cryogenic-CMOS control chip may include circuit blocks that are partitioned into domains that are given common back-gate bias. Example domains with separate bias include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back gate bias is provided for transistors with different aspect ratios. Although <FIG> shows FDSOI digital device <NUM> including certain number and type of wells, FDSOI digital device <NUM> may include additional or fewer wells of other types. In addition, the transistor devices may be planar or non-planar (e.g., FinFET devices).

<FIG> shows an FDSOI analog device <NUM> in accordance with one example. Unlike FDSOI digital device <NUM>, FDSOI analog device <NUM> includes independent back-gate bias control where the back-gate voltage for the p-type devices can be raised above the voltage VDD, independent of the back gate voltage for n-type transistors. FDSOI analog device <NUM> may include a substrate <NUM>. In this example, substrate <NUM> may be a silicon-on-insulator (SOI) substrate. A deep n-well <NUM> may be formed in substrate <NUM> by doping substrate with an n-type dopant. A p-well <NUM> may be formed in deep n-well <NUM> and an n-well <NUM> may be formed in substrate <NUM>. Next, using several lithographic steps, transistor device <NUM> and transistor device <NUM> may be formed. In this example, transistor device <NUM> is a p-type transistor with a gate channel <NUM> formed above a box <NUM>. Transistor device <NUM> may further include p+ type source/drain regions and contacts S and D to the source/drain. In this example, transistor device <NUM> is an n-type transistor with a gate channel <NUM> formed above a box <NUM>. Transistor device <NUM> may further include n+ type source/drain regions and contacts S and D to the source/drain. Various type of devices and regions may be isolated using shallow trench isolation (STI) regions formed using a dielectric. Example STI regions formed in FDSOI analog device <NUM> include STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, STI <NUM>, and STI <NUM>.

With continued reference to <FIG>, the back-gate or body bias of each transistor device can be used to configure the threshold voltage dynamically to account for effects associated with cooling. Thus, in this example, FDSOI analog device <NUM> includes back gate bias via the NBG terminal for the n-type devices and back gate bias via the PBG terminal for the p-type devices. In this example, unlike FDSOI digital device <NUM>, FDSOI analog device <NUM> includes independent back-gate bias control where the back-gate voltage for the p-type devices can be raised above the voltage VDD, independent of the back gate voltage for n-type devices.

Still referring to <FIG>, the back-gate or body bias of each transistor device can be used to configure the threshold voltage dynamically to account for the effects associated with the cooling of the chip in a cryogenic environment. The transistor devices and the related control circuits are designed such that using the back-gate bias control, the threshold voltage of the transistor devices can be tuned despite the huge change in the operating temperature of the transistor devices. In some examples, different back gate bias is provided for transistors with different aspect ratios. Although <FIG> shows FDSOI analog device <NUM> including certain number and type of wells, FDSOI analog device <NUM> may include additional or fewer wells of other types. In addition, the transistor devices may be planar or non-planar (e.g., FinFET devices).

In one example cryogenic-CMOS control chip, the FDSOI digital device <NUM> may be used as part of the circuit blocks that require only a difference between a low value and a high value of voltages and are not concerned with the intermediate values. Because FDSOI digital device <NUM> occupies less area than FDSOI analog device <NUM>, it is advantageous to use it for most of the circuits as long as they are not too sensitive. In one example, only FDSOI analog device <NUM> is fabricated such that there is independent back-gate bias control for both n-type and p-type devices and independent back-gate bias control based on an aspect ratio of these devices. As mentioned earlier, the cryogenic-CMOS control chip may be partitioned into domains, such that each domain includes multiple transistor devices, but shares a common back-gate bias. In one example, there may be eight domains based on the combinations of the n-type versus p-type devices and the different aspect ratios associated with each type of the devices.

<FIG> shows a flowchart <NUM> corresponding to a method associated with the systems described in the present disclosure. In one example, the system for controlling qubit gates may include a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. As an example, the quantum device may correspond to qubits <NUM> of <FIG>. The system may further include a control circuit configured to operate at the cryogenic temperature, and where the control circuit comprises a plurality of charge locking circuits. As an example, the control circuit may correspond to the circuits included in the cryogenic-CMOS control chip described earlier. Each of the plurality of charge locking circuits may be coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate, where each of the plurality of charge locking circuits comprises a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, where the first voltage amount is greater than the second voltage amount. As an example, the charge locking circuits may be included as part of CLFG cells <NUM>. Each charge locking circuit may correspond to any of CLFG cell <NUM>, CLFG cell <NUM>, or CLFG cell <NUM> described earlier.

Step <NUM> may include operating a first subset of the plurality of charge locking circuits in a capacitive mode such that the voltage signal output to at least one qubit gate comprises a pulse signal having a first controlled magnitude, where the first controlled magnitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount. In one example, this step may relate to the operation of CLFG cell <NUM>. As described earlier, CLFG cell <NUM> may include a switch <NUM>, which may be operated in response to the CL_EN<N> signal. This signal may be provided under the control of an appropriate finite state machine or another type of logic as described with respect to <FIG>. When switch <NUM> is closed the voltage (referred to as VHOLD in <FIG>) received via the input terminal (IN) on signal line VICL may be coupled to one plate of the capacitor labeled CPULSE,N, which represents the on-chip capacitance. CLFG cell <NUM> may further include a switch <NUM> and a switch <NUM>. CLFG cell <NUM> may further include an inverter <NUM>. CLFG cell <NUM> may be configured such that only one of these switches is closed at a time. In this example, the signal that is labeled CL_EN<N> may control switch <NUM> and an inverted version of this signal (e.g., inverted by inverter <NUM>) may control switch <NUM>. This way at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the second plate of capacitor labeled CPULSE, N, which represents the on-chip capacitance.

Step <NUM> may include operating a second subset of the plurality of charge locking circuits in a direct mode such that the voltage signal output to at least one qubit gate comprises a signal having a second controlled magnitude where the second controlled magnitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount. In one example, this step may relate to the operation of CLFG cell <NUM>. As explained earlier, CLFG cell <NUM> may operate in the direct mode when the CL_MODE signal is de-asserted. Thus, when the CL_MODE signal is de-asserted, switch <NUM> is closed and depending on a status of the CL_EN<N> signal, either switch <NUM> or switch <NUM> is closed. As a result, at a time either voltage VHIGH or voltage VLOW may be coupled via one of the two switches to the same terminal to which the VIN voltage via the input terminal (IN) is coupled.

It is to be understood that the methods, modules, and components depicted herein are merely exemplary. For example, and without limitation, illustrative types of superconducting devices may include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc..

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above-described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the disclosure provides specific examples, various modifications and changes can be made. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.

Claim 1:
A system (<NUM>) for controlling qubit gates comprising:
a first packaged device (<NUM>) comprising a quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at a cryogenic temperature; and
a second packaged device (<NUM>) comprising a control system configured to operate at the cryogenic temperature, wherein the first packaged device (<NUM>) is coupled to the second packaged device (<NUM>), and wherein the control system comprises:
a plurality of charge locking circuits (<NUM>, <NUM>), wherein each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate, and
a control circuit (<NUM>) comprising a finite state machine (<NUM>) configured to provide at least one control signal to selectively enable at least one of the plurality of charge locking circuits (<NUM>, <NUM>) and to selectively enable a provision of at least one voltage signal to a selected one of the plurality of charge locking circuits (<NUM>, <NUM>);
wherein the control system further comprises a waveform generator (<NUM>) and a register (<NUM>) for storing a bit pattern corresponding to a waveform for generation by the waveform generator (<NUM>).