Patent Description:
Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by wireless communication technologies, such as Wi-Fi, long-term evolution (LTE), and fifth-generation new-radio (<NUM>-NR). To achieve the higher data rates in a mobile communication device, a radio frequency (RF) signal(s) may first be modulated by a transceiver circuit(s) based on a selected modulation and coding scheme (MCS) and then amplified by a power amplifier(s) prior to being radiated from an antenna(s). In many wireless communication devices, the power amplifier(s) and the antenna(s) are typically located in an RF front-end (RFFE) circuit communicatively coupled to the transceiver circuit(s) via an RFFE bus based on an RFFE protocol as defined in the MIPI® alliance specification for radio frequency front-end control interface, version <NUM> (hereinafter referred to as "RFFE specification").

In this regard, <FIG> is a schematic diagram of an example RFFE bus apparatus <NUM> as defined in the RFFE specification. The RFFE bus apparatus <NUM> includes an RFFE master <NUM> coupled to a number of RFFE slaves <NUM>(<NUM>)-<NUM>(M) over an RFFE bus <NUM>. According to the RFFE specification, the RFFE bus <NUM> is a two-wire serial bus that includes a data line <NUM> and a clock line <NUM> for communicating a bidirectional data signal SDATA and a clock signal SCLK, respectively. The RFFE bus <NUM> operates at a first data rate.

However, not all communications require a two-wire serial bus like the RFFE bus <NUM>. In some cases, a single-wire serial bus may be sufficient or even desired for carrying out certain types of communications between circuits. In this regard, <FIG> is a schematic diagram of an example conventional hybrid bus apparatus <NUM> in which a single-wire bus (SuBUS) bridge circuit <NUM> is configured to bridge communications between the RFFE master <NUM> in <FIG> with one or more SuBUS slaves <NUM>(<NUM>)-<NUM>(N). Common elements between <FIG> and <FIG> are shown therein with common element numbers and will not be re-described herein.

The SuBUS bridge circuit <NUM> is coupled to the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) over a SuBUS <NUM> having a single data wire <NUM>. Accordingly, the SuBUS <NUM> is configured to operate at a second data rate that can be faster or slower than the first data rate of the RFFE bus <NUM>. The SuBUS bridge circuit <NUM> may be coupled to the RFFE master <NUM> via the RFFE bus <NUM>. In this regard, the SuBUS bridge circuit <NUM> and the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) are also RFFE slaves, such as the RFFE slaves <NUM>(<NUM>)-<NUM>(M) coupled to the RFFE master <NUM> in the RFFE bus apparatus <NUM> of <FIG>.

Notably, the SuBUS <NUM> differs from the RFFE bus <NUM> in several aspects. First, the RFFE bus <NUM> includes the data line <NUM> and the clock line <NUM>, while the SuBUS <NUM> includes only the single data wire <NUM>. Second, the SuBUS bridge circuit <NUM> is configured to communicate with the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) based on SuBUS command sequences, which may be compatible but different from the RFFE command sequences communicated over the RFFE bus <NUM>. In this regard, the SuBUS bridge circuit <NUM> may perform command conversion between the RFFE command sequences and the SuBUS command sequences to facilitate communications between the RFFE bus <NUM> and the SuBUS <NUM>. Third, the RFFE bus <NUM> may be configured to operate at the first data rate and the SuBUS <NUM> may be configured to operate at the second data rate, which is different from the first data rate. In this regard, the SuBUS bridge circuit <NUM> may buffer SuBUS data payloads prior to communicating over the RFFE bus <NUM> to help compensate for a difference between the first data rate and the second data rate.

Besides the power amplifier(s) and the antenna(s), the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) can also include other types of active or passive circuits (e.g., audio circuits) that need to communicate with other types of masters via the SuBUS <NUM>. Given that the SuBUS bridge circuit <NUM> in the conventional hybrid bus apparatus <NUM> is only capable of bridging the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) with a single RFFE master <NUM> based exclusively on the RFFE protocol, it may be necessary to employ additional SuBUS bridge circuits to bridge the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) to additional types of masters. As a result, the conventional hybrid bus apparatus <NUM> may occupy a larger footprint and/or become more expensive.

<CIT> discusses a mixed-mode radio frequency front-end interface.

Aspects disclosed in the detailed description include a multi-protocol bus circuit. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

In one aspect, a multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each coupled to a respective on of multiple master buses. The multiple master circuits are each configured to communicate a respective one or more master bus commands based on a respective one of multiple master bus protocols. Each of the master bus protocols is different from at least another one of the master bus protocols. The multi-protocol bus circuit also includes one or more slave circuits each coupled to a slave bus. The slave circuits are each configured to communicate a respective one or more slave bus commands based on a slave bus protocol different from any of the master bus protocols. The multi-protocol bus circuit also includes a multi-protocol bridge circuit coupled to the master buses and the slave bus. The multi-protocol bridge circuit is configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols.

In another aspect, a multi-protocol bridge circuit is provided. The multi-protocol bridge circuit includes multiple master bus ports each coupled to a respective one of multiple master circuits configured to communicate a respective one or more master bus commands via a respective one of multiple master buses based on a respective one of multiple master bus protocols. Each of the master bus protocols is different from at least another one of the master bus protocols. The multi-protocol bridge circuit also includes a slave bus port coupled to one or more slave circuits. The slave circuits are each configured to communicate a respective one or more slave bus commands based on a slave bus protocol different from any of the master bus protocols. The multi-protocol bridge circuit also includes a control circuit. The control circuit is configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

In this regard, <FIG> is a schematic diagram of an example multi-protocol bus circuit <NUM> configured according to embodiments of the present disclosure to support bidirectional bus communications between multiple master circuits <NUM>(<NUM>)-<NUM>(M) and one or more slave circuits <NUM>(<NUM>)-<NUM>(N) based on heterogeneous bus protocols. Herein, the bidirectional bus communications refer to bus communications originated from any of the master circuits <NUM>(<NUM>)-<NUM>(M) and destined to any of the slave circuits <NUM>(<NUM>)-<NUM>(N) (a. forward communication), and bus communications originated from any of the slave circuits <NUM>(<NUM>)-<NUM>(N) and destined to any of the master circuits <NUM>(<NUM>)-<NUM>(M) (a. reverse communication).

The master circuits <NUM>(<NUM>)-<NUM>(M) are coupled to multiple master buses <NUM>(<NUM>)-<NUM>(M), respectively. Each of the master circuits <NUM>(<NUM>)-<NUM>(M) is configured to communicate a respective one or more master bus commands <NUM>(<NUM>)-<NUM>(K) based on a respective one of multiple master bus protocols PM1-PMM. In some embodiments, all of the master bus protocols PM1-PMM are different bus protocols. In this regard, each of the master bus protocols PM1-PMM is different from any other one of the master bus protocols PM1-PMM. In some other embodiments, only a subset of the master bus protocols PM1-PMM are different bus protocols. In this regard, each of the master bus protocols PM1-PMM is different from at least another one of the master bus protocols PM1-PMM.

The slave circuits <NUM>(<NUM>)-<NUM>(N) are each coupled to a slave bus <NUM> and configured to communicate a respective one or more slave bus commands <NUM>(<NUM>)-<NUM>(L) based on a slave bus protocol Ps that is different from any of the master bus protocols PM1-PMM. In a non-limiting example, the slave bus <NUM> is a single-wire bus (SuBUS) that is functionally equivalent to the SuBUS <NUM> in <FIG>. Accordingly, each of the slave circuits <NUM>(<NUM>)-<NUM>(N) can be functionally equivalent to the SuBUS slaves <NUM>(<NUM>)-<NUM>(N) in <FIG>.

To enable the bidirectional bus communications based on the heterogeneous bus protocols, the multi-protocol bus circuit is further configured to include a multi-protocol bridge circuit <NUM>. In an embodiment, the multi-protocol bridge circuit <NUM> includes multiple master ports <NUM>(<NUM>)-<NUM>(M), each coupled to a respective one of the master buses <NUM>(<NUM>)-<NUM>(M). The multi-protocol bridge circuit <NUM> also includes a slave bus port <NUM> coupled to the slave bus <NUM>. As discussed in further detail below, the multi-protocol bridge circuit <NUM> can be configured to perform a bidirectional conversion between the slave bus protocol Ps and each of the master bus protocols PM1-PMM. Herein, the bidirectional conversion refers to converting the master bus commands <NUM>(<NUM>)-<NUM>(K) from any of the master bus protocols PM1-PMM into the slave bus commands <NUM>(<NUM>)-<NUM>(L) in accordance with the slave bus protocol Ps, and vice versa. By bridging the master circuits <NUM>(<NUM>)-<NUM>(M) with the slave circuits <NUM>(<NUM>)-<NUM>(N) using the multi-protocol bridge circuit <NUM>, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal cost and/or footprint impact on the multi-protocol bus circuit <NUM>.

In an embodiment, the multi-protocol bridge circuit <NUM> includes a control circuit <NUM>, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. To enable the forward communication, the control circuit <NUM> can be configured to receive the respective master bus commands <NUM>(<NUM>)-<NUM>(K) from any of the master circuits <NUM>(<NUM>)-<NUM>(M) via a respective one of the master ports <NUM>(<NUM>)-<NUM>(M). Notably, the respective master bus commands <NUM>(<NUM>)-<NUM>(K) may be destined to any of the slave circuits <NUM>(<NUM>)-<NUM>(N) or to the multi-protocol bridge circuit <NUM> itself. In this regard, the control circuit <NUM> may be configured to first determine whether the respective master bus commands <NUM>(<NUM>)-<NUM>(K) are destined to at least one of the slave circuits <NUM>(<NUM>)-<NUM>(N). If the control circuit <NUM> determines that the respective master bus commands <NUM>(<NUM>)-<NUM>(K) are indeed destined to any of the slave circuits <NUM>(<NUM>)-<NUM>(N), the control circuit <NUM> will then convert the respective master bus commands <NUM>(<NUM>)-<NUM>(K) into the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) and provide the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) to any of the slave circuits <NUM>(<NUM>)-<NUM>(N) to which the respective master bus commands <NUM>(<NUM>)-<NUM>(K) are destined.

To enable the reverse communication, the control circuit <NUM> is configured to receive the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) from any of the one or more slave circuits <NUM>(<NUM>)-<NUM>(N) via the slave bus port <NUM>. Notably, the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) may be destined to any of the master circuits <NUM>(<NUM>)-<NUM>(M) or to the multi-protocol bridge circuit <NUM> itself. In this regard, the control circuit <NUM> may be configured to first determine whether the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) are destined to at least one of the master circuits <NUM>(<NUM>)-<NUM>(M). If the control circuit <NUM> determines that the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) are indeed destined to any of the master circuits <NUM>(<NUM>)-<NUM>(M), the control circuit <NUM> will then convert the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) into the respective master bus commands <NUM>(<NUM>)-<NUM>(M) and provide the respective master bus commands <NUM>(<NUM>)-<NUM>(M) to any of the master circuits <NUM>(<NUM>)-<NUM>(N) to which the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) are destined.

In an embodiment, the control circuit <NUM> can include at least one encoder-decoder circuit <NUM> (denoted as "CODEC"). Specifically, the encoder-decoder circuit <NUM> can be configured to convert the respective master bus commands <NUM>(<NUM>)-<NUM>(M) into the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) in the forward communication, and to convert the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) into the respective master bus commands <NUM>(<NUM>)-<NUM>) in the reverse communication.

In an embodiment, the multi-protocol bridge circuit <NUM> may simultaneously receive the respective master bus commands <NUM>(<NUM>)-<NUM>(M) from more than one of the master circuits <NUM>(<NUM>)-<NUM>(M). In this regard, upon converting the respective master bus commands <NUM>(<NUM>)-<NUM>(M) received from each of the master circuits <NUM>(<NUM>)-<NUM>(M) into the respective slave bus commands <NUM>(<NUM>)-<NUM>(L), the control circuit <NUM> determines an order for providing the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) to some or all of the slave circuits <NUM>(<NUM>)-<NUM>(N).

For example, the control circuit <NUM> can provide the respective slave bus commands <NUM>(<NUM>)-<NUM>(L), which are converted from the respective master bus commands <NUM>(<NUM>)-<NUM>(M) received simultaneously from more than one of the master circuits <NUM>(<NUM>)-<NUM>(M), to any of the slave circuits <NUM>(<NUM>)-<NUM>(N) based on a predefined priority of the master circuits <NUM>(<NUM>)-<NUM>(M). In this regard, the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) converted from the respective master bus commands <NUM>(<NUM>)-<NUM>(M) received from a higher priority one of the master circuits <NUM>(<NUM>)-<NUM>(M) will be sent to the slave bus port <NUM> before the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) converted from the respective master bus commands <NUM>(<NUM>)-<NUM>(M) are received from a lower priority one of the master circuits <NUM>(<NUM>)-<NUM>(M).

In a non-limiting example, the control circuit <NUM> can include a data buffer <NUM> that functions as a first-in first-out (FIFO) queue. In this regard, the control circuit <NUM> may be configured to enqueue the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) based on the predefined priority of the master circuits <NUM>(<NUM>)-<NUM>(M). In other words, the control circuit <NUM> will enqueue the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) that are converted from the respective master bus commands <NUM>(<NUM>)-<NUM>(M) received from the higher priority one of the master circuits <NUM>(<NUM>)-<NUM>(M) in the data buffer <NUM> before enqueuing the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) that are converted from the respective master bus commands <NUM>(<NUM>)-<NUM>(M) received from the lower priority one of the master circuits <NUM>(<NUM>)-<NUM>(M).

In an embodiment, the data buffer <NUM> may be utilized only for the forward communication. As for the reverse communication, the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) received from any of the slave circuits <NUM>(<NUM>)-<NUM>(N) are directly routed to the encoder-decoder circuit <NUM> from the slave bus port <NUM>. Accordingly, the encoder-decoder circuit <NUM> is configured to convert the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) destined to any of the master circuits <NUM>(<NUM>)-<NUM>(M) on a first come first serve basis.

In an embodiment, the multi-protocol bridge circuit <NUM> can include a storage circuit <NUM> (denoted as "REGMAP"), which can be a register bank, or a flash storage circuit, as an example. The storage circuit <NUM> may be programmed to store the predefined priority among the master circuits <NUM>(<NUM>)-<NUM>(M).

As previously mentioned, the respective master bus commands <NUM>(<NUM>)-<NUM>(K) originated from any of the master circuits <NUM>(<NUM>)-<NUM>(M) can be destined to the multi-protocol bridge circuit <NUM>, as opposed to any of the slave circuits <NUM>(<NUM>)-<NUM>(N). In this regard, the respective master bus commands <NUM>(<NUM>)-<NUM>(K), which are originated from any of the master circuits <NUM>(<NUM>)-<NUM>(M) and destined to the multi-protocol bridge circuit <NUM>, may be utilized to program (dynamically or statically) the predefined priority in the storage circuit <NUM>.

In an embodiment, each of the master circuits <NUM>(<NUM>)-<NUM>(M) may be configured to communicate the respective master bus commands <NUM>(<NUM>)-<NUM>(K) by asserting a respective one of multiple master bus voltages VM1-VMM on the respective one of the master buses <NUM>(<NUM>)-<NUM>(M). In contrast, each of the slave circuits <NUM>(<NUM>)-<NUM>(N) is configured to communicate the respective slave bus commands <NUM>(<NUM>)-<NUM>(L) based on a slave bus voltage Vs that is different from at least one of the master bus voltages VM1-VMM. Notably, any mismatch between the master bus voltages VM1-VMM and the slave bus voltage Vs can cause potential damage to the slave circuits <NUM>(<NUM>)-<NUM>(N), particularly when the slave bus voltage Vs is lower than any mismatched master bus voltage among the master bus voltages VM1-VMM.

In this regard, the multi-protocol bridge circuit <NUM> can be further configured to perform a bidirectional voltage conversion between the slave bus voltage VS and any of the master bus voltages VM1-VMM. In a non-limiting example, the multi-protocol bridge circuit <NUM> can further include multiple master bus interface circuits <NUM>(<NUM>)-<NUM>(M), each coupled to a respective one of the master ports <NUM>(<NUM>)-<NUM>(M). More specifically, each of the master bus interface circuits <NUM>(<NUM>)-<NUM>(M) can include a respective voltage conversion circuit <NUM>, which can be a capacitor-based or an inductor-based buck-boost converter, or a level shifter, as an example, for carrying out the bidirectional voltage conversion between the slave bus voltage Vs and any of the master bus voltage VM1-VMM.

As a non-limiting example, the multi-protocol bridge circuit <NUM> can include a radio-frequency front-end (RFFE) master circuit (e.g., the master circuit <NUM>(<NUM>)) and an inter-integrated circuit (I2C) master circuit (e.g., the master circuit <NUM>(M)). In this regard, the RFFE master circuit <NUM>(<NUM>) is configured to communicate one or more RFFE bus commands <NUM>(<NUM>)-<NUM>(K) over the RFFE bus <NUM>(<NUM>) based on an RFFE bus protocol and by asserting a respective one of the master bus voltage VM1-VMM on the RFFE bus <NUM>(<NUM>), and the I2C master circuit <NUM>(M) is configured to communicate one or more I2C bus commands <NUM>(<NUM>)-<NUM>(K) over the I2C bus <NUM>(M) based on a I2C bus protocol and by asserting a respective one of the master bus voltage VM1-VMM on the I2C bus <NUM>(M). Each of the slave circuits <NUM>(<NUM>)-<NUM>(N), on the other hand, is a SuBUS slave circuit configured to communicate the respective SuBUS slave bus commands <NUM>(<NUM>)-<NUM>(N) over the SuBUS <NUM> based on the SuBUS protocol.

Accordingly, the multi-protocol bridge circuit <NUM> is configured to perform the bidirectional conversion between the RFFE bus protocol, the I2C bus protocol, and the SuBUS bus protocol. In addition, the multi-protocol bridge circuit <NUM> may also perform the bidirectional voltage conversion should there be a mismatch between the RFFE master bus voltage VM1, the I2C master bus voltage VMM, and the SuBUS slave bus voltage Vs.

The multi-protocol bridge circuit <NUM> can further include a second RFFE master circuit (e.g., the master circuit <NUM>(<NUM>)), which is configured to communicate a respective one or more RFFE bus commands <NUM>(<NUM>)-<NUM>(K) over a respective one of the master buses (e.g., the master bus <NUM>(<NUM>)) based on the RFFE bus protocol. However, the second RFFE master circuit is configured to assert a different master bus voltage from the respective master bus voltage asserted by the RFFE master circuit <NUM>(<NUM>).

Claim 1:
A multi-protocol bus circuit (<NUM>) comprising:
a plurality of master circuits (<NUM>(<NUM>)-<NUM>(M)) each associated with a predefined priority and coupled to a respective one of a plurality of master buses (<NUM>(<NUM>)-<NUM>(M)) and configured to communicate a respective one or more master bus commands (<NUM>(<NUM>)-<NUM>(M)) based on a respective one of a plurality of master bus protocols (PM1-PMM), wherein each of the plurality of master bus protocols is different from at least another one of the plurality of master bus protocols;
one or more slave circuits (<NUM>(<NUM>)-<NUM>(N)) each coupled to a slave bus (<NUM>) and configured to communicate a respective one or more slave bus commands (<NUM>(<NUM>)-<NUM>(L)) based on a slave bus protocol (Ps) different from any of the plurality of master bus protocols; and
a multi-protocol bridge circuit (<NUM>) coupled to the plurality of master buses and the slave bus and configured to:
perform a bidirectional conversion between the slave bus protocol and each of the plurality of master bus protocols; and
provide the respective one or more master bus commands received from each of the plurality of master circuits to at least one of the one or more slave circuits in accordance with the predefined priority.