Patent Description:
<CIT> relates to a package substrate with microstrip architecture. The package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer, a solder resist layer and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate.

<CIT> discloses a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line.

For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor devices. The drive to scale-down features in ICs such as high-speed single-ended interconnects/busses, while optimizing the performance of each device, however is not without issue.

Transmission line loss and crosstalk noise coupling are typically the main factors limiting the performance scaling of high-speed single-ended interconnects, such as on-package input/output (I/O) (OPIO) and memory I/O. This problem will continue to become even-more challenging on future semiconductor platforms as system performance scales-down, bus speeds increase, and form factors shrink. For example, the main limitations of high-speed single-ended busses can subsequently bottleneck system form-factor miniaturization, compromise system performances, complicate system designs, and lead to product recalls for future systems due to platform level functional failures.

One existing solution to address the bandwidth-limited transmission line (TLINE) due to loss/intersymbol interference (ISI) and crosstalk includes an on-die active crosstalk cancellation circuitry, however this circuity is not feasible for the ever-growing low-power applications. Another solution is implementing signal conditioners with fixed/adaptive equalization, yet these signal conditioners substantially increase bill of materials (BOM) and board design complexity. Other existing solutions include a transmitter design with de-emphasis or/and pre-emphasis, but this solution is not feasible due to the increased physical layer (PHY) design complexity and the heightened power requirement. Lastly, another solution further includes a transmitter design with higher drive strength, however the design can cause reliability issues due to excessive signal overshoot/undershoot when the TLINE is overdriven.

Embodiments described herein illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar features. Furthermore, some conventional details have been omitted so as not to obscure from the inventive concepts described herein.

Described herein are electronic packages with three-dimensional (3D) transmission lines with array of periodic bumps (APBs) that enable high-speed single-ended signal transmissions and methods of forming such electronic packages. The electronic packages (e.g., semiconductor packages such as printed circuit boards (PCBs)) described below and methods of forming such electronic packages include a package substrate with a transmission line (TLINE) having one or more APBs below and/or above the TLINE, according to some embodiments.

As described herein, an "array of periodic bumps" (APB) refers to a plurality of conductive bumps disposed on a top surface and/or a bottom surface of a conductive transmission line (or a TLINE). Additionally, the APB may be formed of one or more metals such as copper, gold, or the like. The APB may have the same or different metal conductivity as the TLINE. For example, the metal conductivity of the APB may be selected based on the optimum skin-depth that corresponds to the equalization frequency range. In some embodiments, the APBs may be formed with one or more shapes in various orientations. The shapes of the APBs may include, but are not limited to, rectangles, squares, circles, diamonds, and polygons. Furthermore, as described below in further detail, the effectiveness of the APB, including the intersymbol interference (ISI) and crosstalk properties, may be improved based on the selected area/volume of the APB.

Accordingly, embodiments described herein include improvements of on-package electrical solutions by utilizing the transmission line skin-effect, and the transmission and self-coupling principles to transform the transmission line architecture to inherit the self-equalized and crosstalk-compensated properties. These embodiments of the APB of the package substrate enable (i) altering/increasing the high-frequency characteristic impedance to boost the launching energy of the high-frequency component to equalize the transmitted signal, and (ii) increasing the capacitive-coupling to the reference plane that enhances the crosstalk immunity. Additionally, the embodiments of the APBs described herein improve the eye opening of a TLINE by approximately <NUM>% or greater - without increasing the overshoot/undershoot levels. For example, both ISI and crosstalk impacts may notably be addressed and improved with the APBs, where the first-half of the eye opening could be substantially pre-amplified by the APBs and helped to restore the collapsed eyes, and APBs' performance could be further ascertained by S-parameters result in term of insertion loss, NEXT and FEXT, where the APBs yield improved such result (as compared to existing TLINEs). Furthermore, in regards to the XY-area trade-offs, the embodiments described herein have the same routing pitch or even smaller routing pitch as compared to existing/conventional TLINE design. Furthermore, the APBs can restore the impedance of the existing TLINE within the same XY-footprint/trace width by approximately 10ohm or greater, which is vital for the ever-narrowing/thinning of PCB designs.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as microelectromechanical systems (MEMS) based electrical systems, gyroscopes, advanced driving assistance systems (ADAS), <NUM> communication systems, cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments, the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices, including semiconductor packages having package substrates with TLINES that are disposed with one or more APBs below and/or above the TLINEs.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present embodiments, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As used herein the terms "top," "bottom," "upper," "lower," "lowermost," and "uppermost" when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration. Thus, an element described as an "uppermost element" or a "top element" in a device may instead form the "lowermost element" or "bottom element" in the device when the device is inverted. Similarly, an element described as the "lowermost element" or "bottom element" in the device may instead form the "uppermost element" or "top element" in the device when the device is inverted.

<FIG> is an illustration of a perspective view of a package substrate <NUM> with a TLINE <NUM> having a plurality of conductive bumps <NUM> (or APBs) below the TLINE <NUM>, according to one embodiment. In some embodiments, <FIG> illustrates one of the approaches that enables coupling the TLINE <NUM> and the conductive bumps <NUM> with a passive packaging solution by utilizing the transmission line skin-effect and transmission and self-coupling properties to transform the TLINE design/architecture to inherit the self-equalized and crosstalk-compensated properties. These embodiments of the package substrate <NUM> may be implemented by augmenting the transmission line <NUM> with the APBs <NUM> that are disposed (or coupled/merged) on the surfaces of the TLINE <NUM> using a via packaging patterning and electroplating process or the like.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In one embodiment, the package substrate <NUM> may include a conductive line <NUM>. The conductive line <NUM> may be a transmission line (TLINE) that is used to transmit signals in the package substrate <NUM>, such as a stripline, a microstrip, a dual-stripline, an embedded-microstrip, and/or the like. In some embodiments, the package substrate <NUM> may implement the transmission line <NUM> to be coupled with a plurality of conductive bumps <NUM>.

For one embodiment, the package substrate <NUM> may include, but is not limited to, a package, a substrate, a printed circuit board (PCB), and a motherboard. For one embodiment, the package substrate <NUM> is a PCB. For one embodiment, the PCB is made of an FR-<NUM> glass epoxy base with thin copper foil laminated on both sides. For certain embodiments, a multilayer PCB can be used, with pre-preg and copper foil used to make additional layers. For example, the multilayer PCB may include one or more dielectric layers <NUM>, where each dielectric layer can be a photosensitive dielectric layer. For one embodiment, the PCB <NUM> may include a plurality of conductive layers (e.g., a plurality of transmission lines <NUM>, a reference conductive layer <NUM>, etc.), which may further include copper (or metallic) traces, lines, pads, vias, via pads, holes, and/or planes.

The transmission line <NUM> may be formed of a conductive material (or a metallic material) such as copper, gold, or the like. For some embodiments, the transmission line <NUM> may be formed with one or more size parameters, including a width T1W and a thickness T1T. In an embodiment, the transmission line <NUM> may be a rectangle conductor having a conductive layer <NUM> as a reference plane. The conductive layer <NUM> may be a reference conductive plane, a ground reference plane, an electrical reference plane, or the like. In one embodiment, a dielectric layers <NUM> may disposed between the transmission line <NUM> and the reference plane <NUM>, where the dielectric layers <NUM> may surround the conductive bumps <NUM> and the bottom surface of the transmission line <NUM>. Furthermore, a solder resist layer <NUM> may be disposed over the transmission line <NUM> and the dielectric layers <NUM>, where the solder resist layer <NUM> may embed and surround the side walls and top surface of the transmission line <NUM>. In an alternate embodiment, the conductive bumps <NUM> and the transmission line <NUM> may be embedded solely within the dielectric layers <NUM> or the solder resist layer <NUM>; or the conductive bumps <NUM> and the transmission line <NUM> may be semi-embedded in both the dielectric layers <NUM> and the solder resist layer <NUM>.

As described above, the APBs <NUM> may be conductive bumps that are periodically disposed on a surface of the transmission line <NUM>. For example, as shown in <FIG>, the conductive bumps <NUM> may be an array of periodic bumps that are coupled onto the bottom surface of the transmission line <NUM>. The conductive bumps <NUM> are disposed on a bottom surface or a top surface of the transmission line <NUM> (e.g., as shown below in <FIG>).

Additionally, the conductive bumps <NUM> may be formed of one or more conductive material (or a metallic material) such as copper, gold, or the like. In one embodiment, the conductive bumps <NUM> may have a metal conductivity that is the substantially equal to (or the same as) a metal conductivity of the transmission line <NUM>. In another embodiment, the conductive bumps <NUM> may have a metal conductivity that is different than a metal conductivity of the transmission line <NUM>. The metal conductivity materials of the conductive bumps <NUM> may be selected based on the optimum skin-depth corresponding to the desired equalization frequency range. In some embodiments, the conductive bumps <NUM> may be formed as one or more shapes in one or more orientations. The shapes of the conductive bumps <NUM> may include, but are not limited to, rectangles, squares, circles, diamonds, and polygons.

In some embodiments, each of the conductive bumps <NUM> may be formed with a desired area (or volume) (e.g., as shown with the one or more thicknesses "Txx" illustrated in <FIG>), where the desired area is selected to optimize/improve the transmission line loss and crosstalk noise properties. For example, the conductive bumps <NUM> may be periodically patterned and disposed on the transmission line <NUM> to have or more size parameters, including a width T2W, a thickness T2T, a gap length T<NUM> between the conductive bumps <NUM>, and a length T<NUM>.

These size parameters combined with the metal conductivity of the conductive bumps <NUM> may be altered (or tuned) to optimize the skin depth, equalization effectiveness, and design of the transmission line <NUM>. In an embodiment, the conductive bumps <NUM> may have a length T<NUM> that is substantially less than a gap length T<NUM> of the conductive bumps <NUM>. Furthermore, the conductive bumps <NUM> may have a thickness T2T that is less than a thickness T1T of the transmission line <NUM>. In other embodiments, the conductive bumps <NUM> may have a thickness T2T that is approximately equal to a thickness T1T of the transmission line <NUM>. For one embodiment, the conductive bumps <NUM> may have a width T2W that is approximately equal to a width T1W of the transmission line <NUM>. For example, in one embodiment, the transmission line <NUM> may have a width T1W that is approximately <NUM> or less, and a thickness T1T that is approximately <NUM> or less; while the conductive bumps <NUM> may have a width T2W that is approximately <NUM> or less, a thickness T2T that is approximately <NUM> or less (or <NUM> or less), a gap length T<NUM> that is approximately <NUM> or less, and a length T<NUM> that is approximately <NUM> or less.

In the embodiments described herein, the conductive bumps <NUM> increase the high-frequency characteristic impedance of the transmission line <NUM> by increasing the self-inductance of the transmission line <NUM>, which is implemented/realized by concentrating the high-frequency current into the tiny conductive bump structures with the corresponding skin-depth. The overall effect is therefore an increase in current density, which in turn increases the overall inductance of the transmission line <NUM> (or the transmission line design). For example, when the high-frequency characteristic impedance increases, the high-frequency transmission coefficient also increases, which thus allows higher launching voltage for the high-frequency component to create the equalization (pre-emphasis) effects.

Additionally, in these embodiments described herein, the conductive bumps <NUM> increase the capacitive-coupling of the transmission line <NUM> by reducing the effective distance to the reference plane <NUM>, thereby making the electromagnetic field (EM-field) to be more confined and tightly coupled to the reference plane <NUM>. The overall effect is thus less fringing of the EM-field to the adjacent transmission line (not shown), which then reduces the crosstalk of the transmission lines.

Accordingly, the package substrate <NUM> may implement a desired area combined with a desired metal conductivity of the conductive bumps <NUM> to facilitate the bandwidth-limitations of the transmission line <NUM> associated with ISI and crosstalk. The conductive bumps <NUM> therefore enable an improved TLINE architecture with preselected design dimensions, which provides a desired scaling/configuration of the TLINE <NUM> and respectively exhibits higher transmission bandwidth with enhanced noise immunity.

In this embodiment, the conductive bumps <NUM> enable the transmission line <NUM> to yield substantially improved results for the bandwidth-limitations of the transmission line <NUM> based on ISI and crosstalk (as compared to existing transmission line designs/configurations). For example, a <NUM> Gbps signal may be implemented with the conductive bumps <NUM> of the transmission line <NUM>, where the transmission line <NUM> may be approximately a <NUM> on-package input/output (OPIO) interconnect/bus, thereby providing a voltage margin (or eye height) that may be approximately improved to <NUM> mV (e.g., as compared to using an existing TLINE with these same parameters having approximately a <NUM> mV voltage margin), a timing margin (or eye width) that may be approximately improved to <NUM> ps (e.g., as compared to using an existing TLINE with these same parameters having approximately a <NUM> ps timing margin), and an overshoot/undershoot voltage that may be negligible. Implementing the conductive bumps <NUM> also adequately enables implementing power and real-estate sensitive applications and low-power applications, while substantially reducing (i) the BOM and board design complexity, (ii) the physical layer (PHY) design complexity, (iii) the power requirements, and (iv) reliability issues that are typically associated with excessive signal overshoot/undershoot when transmission line is overdriven.

Note that the package substrate <NUM> may include fewer or additional packaging components based on the desired packaging design.

As described below in <FIG>, the conductive bumps (or APBs) may be disposed (or coupled/merged) onto several surfaces of the main transmission line (or TLINE) body to form various TLINE-APB configurations, including a package substrate <NUM> with the APBs <NUM> above the TLINE <NUM>, a package substrate <NUM> with the APBs <NUM> and <NUM> symmetrically aligned (or disposed) below and above the TLINE <NUM>, and a package substrate <NUM> with the APBs <NUM>-<NUM> asymmetrically aligned below and above the TLINE <NUM>. Note that, as described above, the TLINE-APB configurations of the package substrates may include a single APB or a plurality of APBs having the same or different type of conductivity and thicknesses/skin-depths.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. The semiconductor package <NUM> may be substantially similar to the package substrate <NUM> described above in <FIG>, with the exception that the conductive bumps <NUM> are disposed above the transmission line <NUM>, according to some embodiments. In one embodiment, the conductive bumps <NUM> are disposed on the top surface of the transmission line <NUM>, where the conductive bumps <NUM> and the transmission line <NUM> may be disposed over the dielectric layers <NUM>, and the conductive bumps <NUM> and the transmission line <NUM> may be embedded/surrounded with the solder resist layer <NUM>. The conductive bumps <NUM> of the transmission line <NUM> are substantially similar to the conductive bumps <NUM> of the transmission line <NUM> described above in <FIG>.

Note that the semiconductor package <NUM> may include fewer or additional packaging components based on the desired packaging design.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. The semiconductor package <NUM> may be substantially similar to the package substrates <NUM> and <NUM> described above in <FIG>, with the exception that the conductive bumps <NUM> and <NUM> are disposed below and above the transmission line <NUM>, according to some embodiments. In one embodiment, the conductive bumps <NUM> and <NUM> are patterned and disposed respectively on the bottom and top surfaces of the transmission line <NUM>, where the conductive bumps <NUM> and the transmission line <NUM> may be disposed over the dielectric layers <NUM>, the conductive bumps <NUM> and the transmission line <NUM> may be embedded/surrounded with the solder resist layer <NUM>, and the conductive bumps <NUM> may be embedded with the dielectric layers <NUM>. In an embodiment, the conductive bumps <NUM> may be positioned (or aligned) on the transmission line <NUM> to be substantially symmetrical to the conductive bumps <NUM> on the transmission line <NUM>.

In an embodiment, the conductive bumps <NUM> are symmetrically positioned below the transmission line <NUM> to be aligned with the conductive bumps <NUM> above the transmission line <NUM>. In this embodiment, the symmetrically disposed conductive bumps <NUM>-<NUM> enable the transmission line <NUM> to yield substantially improved results for the bandwidth-limitations of the transmission line <NUM> based on ISI and crosstalk (as compared to existing transmission line designs/configurations). For example, a <NUM> Gbps signal may be implemented with the symmetrical top/bottom conductive bumps <NUM>-<NUM> of the transmission line <NUM>, where the transmission line <NUM> may be approximately a <NUM> OPIO interconnect/bus, thereby providing a voltage margin that may be approximately improved to <NUM> mV (e.g., as compared to using an existing TLINE with these same parameters having approximately a <NUM> mV voltage margin), a timing margin that may be approximately improved to <NUM> ps (e.g., as compared to using an existing TLINE with these same parameters having approximately a <NUM> ps timing margin), and an overshoot/undershoot voltage that may be negligible.

The conductive bumps <NUM>-<NUM> of the transmission line <NUM> are substantially similar to the conductive bumps <NUM> of the transmission line <NUM> described above in <FIG>. In some embodiments, the conductive bumps <NUM> may have a thickness that is substantially equal to a thickness of the conductive bumps <NUM>. As described above, in some embodiments, the package substrate <NUM> may include the conductive bumps <NUM>-<NUM> having the same or different type of metal conductivity and thicknesses/skin-depths as the transmission line <NUM>. Note that the semiconductor package <NUM> may include fewer or additional packaging components based on the desired packaging design.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. The semiconductor package <NUM> may be substantially similar to the package substrates <NUM>, <NUM>, and <NUM> described above in <FIG>, with the exception that the conductive bumps <NUM> and <NUM> are disposed below the transmission line <NUM>, and the conductive bumps <NUM> and <NUM> are disposed above the transmission line <NUM>, according to some embodiments. In one embodiment, the conductive bumps <NUM> and <NUM> are patterned and stacked on the bottom surface of the transmission line <NUM>, while the conductive bumps <NUM> and <NUM> are patterned and stacked on the top surface of the transmission line <NUM>. In one embodiment, the conductive bumps <NUM> and <NUM> and the transmission line <NUM> may be disposed over the dielectric layers <NUM>, and may be embedded/surrounded with the solder resist layer <NUM>. Additionally, the conductive bumps <NUM> and <NUM> may be embedded with the dielectric layers <NUM>. In an embodiment, the conductive bumps <NUM> and <NUM> may be positioned (or aligned) on the transmission line <NUM> to be substantially symmetrical to the conductive bumps <NUM> and <NUM> on the transmission line <NUM>. However, in alternate embodiments, the conductive bumps <NUM> and <NUM> may be positioned (or aligned) asymmetrically on the transmission line <NUM> as compared to the conductive bumps <NUM> and <NUM> positioned/aligned on the transmission line <NUM>.

The conductive bumps <NUM>-<NUM> of the transmission line <NUM> are substantially similar to the conductive bumps <NUM> of the transmission line <NUM> described above in <FIG>. In some embodiments, the conductive bumps <NUM> may have a thickness that is substantially equal to a thickness of the conductive bumps <NUM>. Likewise, in some embodiments, the conductive bumps <NUM> may have a thickness that is substantially equal to a thickness of the conductive bumps <NUM>. In some embodiments, the conductive bumps <NUM>-<NUM> may have a thickness that is substantially equal to a thickness of the conductive bumps <NUM>-<NUM>, while the conductive bumps <NUM>-<NUM> may have a length and/or a width that is/are different than a length and/or a width of the conductive bumps <NUM>-<NUM>.

Additionally, the conductive bumps <NUM>-<NUM> may have a metal conductivity (or a plurality of conductive materials) that is different than a metal conductivity of the conductive bumps <NUM>-<NUM>, where the metal conductivity of the conductive bumps <NUM>-<NUM> is the same for both conductive bumps <NUM>-<NUM>. In other embodiments, the conductive bumps <NUM>-<NUM> may have the same metal conductivity, while the conductive bumps <NUM> may have a metal conductivity that is different than a metal conductivity of the conductive bumps <NUM>. As described above, in some embodiments, the package substrate <NUM> may include one or more of the conductive bumps <NUM>, <NUM>, <NUM>, and <NUM> having the same or different type of metal conductivity and thicknesses/skin-depths as the transmission line <NUM>. Note that the semiconductor package <NUM> may include fewer or additional packaging components based on the desired packaging design.

<FIG> are a series of cross-sectional illustrations that depict a package substrate <NUM> with a plurality of transmission lines <NUM> coupled/merged with conductive bumps, according to some embodiments. The process flow illustrated in <FIG> form the package substrate <NUM> that may be substantially similar to the package substrates <NUM>, <NUM>, <NUM>, and <NUM> described above in <FIG>. Accordingly, as described above, this process flow of the package substrate <NUM> illustrates one of the approaches to pattern and dispose conductive material to form transmission lines <NUM> that are coupled/merged with conductive bumps as described herein, according to some embodiments.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include a conductive layer <NUM>, a dielectric layers <NUM>, and a conductive layer <NUM>. The conductive layer <NUM> may be disposed over the dielectric layers <NUM> and the conductive layer <NUM>. In one embodiment, the conductive layer <NUM> may be a reference conductive plane such a ground plane or the like. For one embodiment, the conductive layers <NUM> and <NUM> may be formed of the same conductive (or metallic) materials, including copper or the like.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing a resist layer <NUM> on the conductive layer <NUM>. For one embodiment, the resist layer <NUM> may be a photoresist layer such as a dry-film resist (DFR) layer. In some embodiments, the resist layer <NUM> may be implemented to form (or pattern) a conductive base layer of a conductive transmission line with conductive bumps (or a TLINE-APB as described herein) in a subsequent process described below.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing a patterned mask 542A over the resist layer <NUM> and the conductive layer <NUM>. For one embodiment, the mask 542A may be patterned with openings <NUM> (or holes) that may expose one or more surfaces (or portions) of the resist layer <NUM>. In some embodiments, the mask 542A may be disposed over the resist layer <NUM> to pattern the base layer of the transmission line in a subsequent process described below.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include exposing the patterned mask 542A and the exposed surfaces of the resist layer <NUM> with a light source <NUM> (e.g., a laser direct imaging source, a ultraviolet (UV) light source, etc.). The laser <NUM> may be exposed through the openings of the patterned mask 542A and onto the exposed surfaces of the resist layer <NUM>, where the exposed surfaces of the resist layer <NUM> may be hardened to form a plurality of hardened resist portions <NUM> by the laser <NUM>. In one embodiment, the resist layer <NUM> may now include the hardened portions <NUM> over the conductive layer <NUM>.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include removing the resist layer as the hardened resist portions <NUM> remain patterned/disposed over the conductive layer <NUM>. The resist layer may be removed with an etching process or the like to dissolve/etch (or remove) the unhardened portions of the resist layer.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include removing the portions of the conductive layer <NUM> that are not covered with the hardened resist portions <NUM>. The conductive layer may be removed with an etching process or the like to etch away (or remove) the exposed portions of the conductive layer as the covered conductive portions <NUM> remain covered with the hardened resist portions <NUM>, and the remaining patterned hardened resist <NUM> and conductive portions <NUM> are both stacked over the dielectric layers <NUM>.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include removing (or stripping) the hardened resist portions <NUM> to expose the top surfaces of the conductive portions <NUM>. The patterned conductive portions <NUM> may be implemented as the conductive base layer of the transmission lines (as described herein) that are formed using a subtractive plating process or the like.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing a hardened resist layer <NUM> over the dielectric layers <NUM>, where the hardened resist layer <NUM> may surround the conductive portions <NUM>. The hardened resist layer <NUM> may be formed using a similar process as illustrated in <FIG> (e.g., a resist layer may have direct UV exposure - without a mask - to form the hardened resist layer <NUM>). In one embodiment, the hardened resist layer <NUM> may have a top surface that is substantially coplanar to the top surfaces of the conductive portions <NUM>.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing a resist layer <NUM> over the hardened resist layer <NUM> and the conductive portions <NUM>. The resist layer <NUM> may be an unhardened resist layer that is disposed over the hardened resist layer <NUM> and the conductive portions <NUM>.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing a patterned mask 542B over the resist layer <NUM>, the hardened resist layer <NUM>, and the conductive portions <NUM>. For one embodiment, the mask 542B may be patterned with openings that may expose one or more surfaces (or portions) of the resist layer <NUM>. In some embodiments, the mask 542B may be disposed over the stack of resist layer <NUM> and conductive portions <NUM> to form a conductive top layer of the transmission line in a subsequent process described below. This conductive top layer may be subsequently disposed (or formed) to be implemented as the conductive bumps above the transmission line (e.g., as shown with the transmission line design of the conductive bumps <NUM> and the transmission line <NUM> of <FIG>).

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include exposing the patterned mask 542B and the exposed surfaces of the resist layer <NUM> with a light source <NUM> as described above in <FIG>. The laser <NUM> may be exposed through the openings of the patterned mask 542B and onto the exposed surfaces of the resist layer <NUM>, where the exposed surfaces of the resist layer <NUM> may be hardened to form a thicker hardened resist layer <NUM>, while the unexposed surfaces of the resist layer (or the covered portions of the resist layer) may remain as unhardened resist portions directly over the conductive portions <NUM>. In one embodiment, the resist layer may now include the unhardened resist portions <NUM> over the conductive portions <NUM>.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include removing the unhardened resist portions to expose openings <NUM> over the top surfaces of the conductive portions <NUM>. The unhardened resist portions may be removed with an etching process or the like as described above. In one embodiment, the hardened resist layer <NUM> may now be patterned with the openings <NUM> that may be used to form a plurality of conductive bumps over the exposed top surfaces of the conductive portions <NUM>, as shown in the subsequent steps below.

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include disposing (or depositing) a conductive material in the openings through the hardened resist layer <NUM>, and over the exposed surfaces of the conductive portions <NUM> to form a plurality of conductive trench layers/formations. The conductive material may be disposed with an electrolytic plating process of the like. In one embodiment, the conductive material may now be implemented (or coupled/merged) to form a plurality of transmission lines <NUM> (i.e., the conductive base layer/portions) with the top conductive bumps (i.e., the conductive material disposed above for the trench/bump layers/formations).

Referring now to <FIG>, a cross-sectional illustration of a package substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the package substrate <NUM> may include removing (or stripping) the hardened resist portions to expose the combined conductive bumps and transmission lines <NUM> and the top surface of the dielectric layers <NUM>. In one embodiment, as shown with <FIG>, the second plating process used to form these conductive bumps and transmission lines <NUM> may be a semi-additive plating (SAP) process or the like.

Note that the package substrate <NUM> as shown with <FIG> may include fewer or additional packaging components based on the desired packaging design.

<FIG> is an illustration of a cross-sectional view of a semiconductor packaged system <NUM> including a die <NUM>, a substrate <NUM>, a package substrate <NUM>, and one or more build-up structures <NUM>, according to one embodiment. <FIG> illustrates a semiconductor package <NUM> including a die <NUM>, a substrate <NUM> (or an interposer), interconnect structures (e.g., the plurality of bumps disposed below the die <NUM> and the substrate <NUM>), and the package substrate <NUM>, where the substrate <NUM> and/or the package substrate <NUM> may include the transmission lines with conductive pumps (or TLINE-APBs) <NUM>, according to some embodiments.

For one embodiment, the semiconductor package <NUM> may implement the substrate <NUM> and/or the package substrate <NUM> to include the TLINE-APBs <NUM> (as the transmission line/conductive bumps structures of the package substrates described herein). In one embodiment, the TLINE-APB(s) <NUM> of the substrate <NUM> and/or the package substrate <NUM> may be substantially similar to the TLINE-APB(s) of the package substrates <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above in <FIG>. Note that the semiconductor package <NUM> is not limited to the illustrated semiconductor packaged system, and thus may be designed/formed with fewer, alternate, or additional packaging components and/or with different interconnecting structures.

According to one embodiment, the semiconductor package <NUM> is merely one example of an embodiment of a semiconductor packaged system. For one embodiment, the semiconductor package <NUM> may include a ball grid array (BGA) package, a land grid array (LGA) package, and/or a pin grid array (PGA) package. For one embodiment, a die <NUM> is coupled to a substrate <NUM> (e.g., an interposer) via one or more bumps/joints formed from respective microbumps. As described above, a solder joint formed by soldering of a microbump according to an embodiment may itself be referred to as a "bump" and/or a "microbump. " Additionally, for other embodiments, the die <NUM>, the substrate <NUM>, and the package substrate <NUM> may be coupled using anisotropic conductive film (ACF). For one embodiment, the substrate <NUM> may be, but is not limited to, a silicon interposer and/or a die with through silicon vias (TSVs). For an alternate embodiment, the semiconductor package <NUM> may omit the interposer/substrate <NUM>.

For some embodiments, the semiconductor package <NUM> may have the die <NUM> disposed on the interposer <NUM>, where both the stacked die <NUM> and interposer <NUM> are disposed on a package substrate <NUM>. According to some embodiments, the package substrate <NUM> may include, but is not limited to, a package, a substrate, a PCB, and a motherboard. For one embodiment, the package substrate <NUM> is a PCB. For one embodiment, the PCB is made of an FR-<NUM> glass epoxy base with thin copper foil laminated on both sides. For certain embodiments, a multilayer PCB can be used, with pre-preg and copper foil used to make additional layers. For example, the multilayer PCB may include one or more dielectric layers, where each dielectric layer can be a photosensitive dielectric layer. For one embodiment, the PCB <NUM> may also include conductive layers that comprise copper lines/traces, metallic pads, vias, via pads, planes, and/or holes.

For one embodiment, the die <NUM> may include, but is not limited to, a semiconductor die, an electronic device (e.g., a wireless device), an integrated circuit (IC), a central processing unit (CPU), a microprocessor, a platform controller hub (PCH), a memory, and/or a field-programmable gate array (FPGA). The die <NUM> may be formed from a material such as silicon and have circuitry thereon that is to be coupled to the interposer <NUM>. Although some embodiments are not limited in this regard, the package substrate <NUM> may in turn be coupled to another body, for example, a computer motherboard. One or more connections between the package substrate <NUM>, the interposer <NUM>, and the die <NUM> - e.g., including some or all of bumps <NUM>, <NUM>, and <NUM> - may include one or more interconnect structures and underfill layers <NUM> and <NUM>. In some embodiments, these interconnect structures (or connections) may variously comprise an alloy of nickel, palladium, and tin (and, in some embodiments, Cu).

Connections between the package substrate <NUM> and another body may be made using any suitable structure, such as the illustrative bumps <NUM> shown. The package substrate <NUM> may include a variety of electronic structures formed thereon or therein. The interposer <NUM> may also include electronic structures formed thereon or therein, which may be used to couple the die <NUM> to the package substrate <NUM>. For one embodiment, one or more different materials may be used for forming the package substrate <NUM> and the interposer <NUM>. In certain embodiments, the package substrate <NUM> is an organic substrate made up of one or more layers of polymer base material, with conducting regions for transmitting signals. In certain embodiments, the interposer <NUM> is made up of a ceramic base material including metal regions for transmitting signals. Although some embodiments are not limited in this regard, the semiconductor package <NUM> may include gap control structures <NUM> - e.g., positioned between the package substrate <NUM> and the interposer <NUM>. Such gap control structures <NUM> may mitigate a change in the height of the gap between the package substrate <NUM> and the interposer <NUM>, which otherwise might occur during reflowing while die <NUM> is attached to interposer <NUM>. Note that the semiconductor package <NUM> includes an underfill material <NUM> between the interposer <NUM> and the die <NUM>, and an underflow material <NUM> between the package substrate <NUM> and the interposer <NUM>. For one embodiment, the underfill materials (or layers) <NUM> and <NUM> may be one or more polymers that are injected between the layers. For other embodiments, the underfill materials may be molded underfills (MUF).

<FIG> is an illustration of a schematic block diagram illustrating a computer system <NUM> that utilizes a device package <NUM> (or a semiconductor package) with a package substrate having TLINEs with APBs below/above the TLINE, according to one embodiment. <FIG> illustrates an example of computing device <NUM>. Computing device <NUM> houses motherboard <NUM>. Motherboard <NUM> may include a number of components, including but not limited to processor <NUM>, device package <NUM> (or semiconductor package), and at least one communication chip <NUM>. Processor <NUM> is physically and electrically coupled to motherboard <NUM>. For some embodiments, at least one communication chip <NUM> is also physically and electrically coupled to motherboard <NUM>. For other embodiments, at least one communication chip <NUM> is part of processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

At least one communication chip <NUM> enables wireless communications for the transfer of data to and from computing device <NUM>. At least one communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. Computing device <NUM> may include a plurality of communication chips <NUM>.

Processor <NUM> of computing device <NUM> includes an integrated circuit die packaged within processor <NUM>. Device package <NUM> may be, but is not limited to, a substrate, a package substrate, and/or a PCB. In one embodiment, device package <NUM> may be a package substrate as described herein. Device package <NUM> may include a package substrate having transmission lines with conductive bumps (or stacked conductive bumps) disposed below and/or above the transmission lines (e.g., as illustrated and described above in <FIG>) - or any other components from the figures described herein.

Note that device package <NUM> may be a single component/device, a subset of components, and/or an entire system, as the materials, features, and components may be limited to device package <NUM> and/or any other component of the computing device <NUM> that may transmission lines with conductive bumps on the top surfaces, bottom surfaces, and/or both top/bottom surfaces (e.g., the motherboard <NUM>, the processor <NUM>, and/or any other component of the computing device <NUM> may need the embodiments of the package substrates as described herein).

For certain embodiments, the integrated circuit die may be packaged with one or more devices on a package substrate that includes a thermally stable RFIC and antenna for use with wireless communications and the device package, as described herein, to reduce the z-height of the computing device. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

At least one communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. For some embodiments, the integrated circuit die of the communication chip may be packaged with one or more devices on a package substrate that includes one or more device packages, as described herein.

Claim 1:
A package substrate (<NUM>, <NUM>, <NUM>, <NUM>), comprising:
a dielectric (<NUM>, <NUM>, <NUM>, <NUM>) over a conductive layer (<NUM>, <NUM>, <NUM>, <NUM>);
a conductive line (<NUM>, <NUM>, <NUM>, <NUM>) on the dielectric (<NUM>, <NUM>, <NUM>, <NUM>);
a plurality of conductive bumps (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) on at least one of a bottom surface and a top surface of the conductive line, wherein the plurality of conductive bumps (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) are conductively coupled to the conductive line (<NUM>, <NUM>, <NUM>, <NUM>); and
a solder resist (<NUM>, <NUM>, <NUM>, <NUM>) over the conductive line (<NUM>, <NUM>, <NUM>, <NUM>) and the dielectric (<NUM>, <NUM>, <NUM>, <NUM>);
wherein conductive bumps (<NUM>, <NUM>, <NUM>, <NUM>) below the conductive line (<NUM>, <NUM>, <NUM>, <NUM>) and conductively coupled to the bottom surface of the conductive line (<NUM>, <NUM>, <NUM>, <NUM>) are embedded in the dielectric, and
wherein conductive bumps (<NUM>, <NUM>, <NUM>, <NUM>) above the conductive line (<NUM>, <NUM>, <NUM>, <NUM>) and conductively coupled to the top surface of the conductive line are embedded in the solder resist (<NUM>, <NUM>, <NUM>, <NUM>).