Patent Description:
Planar semiconductor devices, such as memory cells, are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A 3D device architecture can address the density limitation in some planar semiconductor devices, for example, Flash memory devices.

A 3D semiconductor device can be formed by stacking semiconductor wafers or dies and interconnecting them vertically so that the resulting structure acts as a single device to achieve performance improvements at reduced power and a smaller footprint than conventional planar processes. Among the various techniques for stacking semiconductor substrates, bonding, such as hybrid bonding, is recognized as one of the promising techniques because of its capability of forming high-density interconnects. Exemplary, <CIT> discloses a semiconductor device and a method of manufacturing the same capable of reducing variations in the thickness of a semiconductor device, wherein the amount of oxygen implanted ions is less than the amount of implanted oxygen ions in the conventional epitaxial SIMOX wafers. <CIT> discloses a 3D semiconductor device including a peripheral circuitry on a substrate, which includes a plurality of peripheral devices, a first interconnect layer and a deep-trench-isolation, wherein the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices.

Methods for forming 3D semiconductor devices are disclosed herein.

A method for forming a 3D semiconductor device according to the invention is presented in claim <NUM>.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

For example, an interconnect layer can include one or more conductor and contact (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

One important aspect of 3D memory development is the increase in the number of memory cells, requiring an increase in integration level at all. An application to memory production is a multiplication of the number of metal lines, such as word lines or bit lines, resulting in a higher stair structure and increased thickness. Therefore, it is particularly important to reduce the thickness of the whole memory structure when increasing the number of layers of metal lines.

One of the manufacturing processes to reduce the thickness of the whole memory structure is to thin the substrate having semiconductor devices or array structures formed therein. After thinning the substrate, the subsequent interconnections could be formed on the thinned substrate to reduce the thickness of the whole memory structure. Another reason of thinning the substrate is to expose interconnects buried in the substrate, e.g., the through silicon contacts (TSCs) structure, and make it easier to make interconnections between the pad-out interconnect layer above the thinned substrate and the interconnects under the substrate in particular in a face-to-face bonded 3D architecture.

However, to thin the substrate having semiconductor devices or array structures formed therein, the substrate may be generally treated by a chemical-mechanical polishing (CMP) process, and the thickness of the substrate and the uniformity of the thinned surface are difficult to control in the CMP process. In addition, when using the CMP process to thin the substrate, several different CMP steps having different roughness of polishing are required to achieve the expected thickness and lead to high manufacturing cost.

To address the aforementioned issues, the present disclosure introduces a solution in which the substrate is formed a buried stop layer, and the thinning operation may be stopped by the buried stop layer. The buried material may be implanted in the substrate and diffused to a predefined depth. The buried material is synthesized to an oxide layer in the predefined depth during the anneal operation of forming array structure. The oxide layer functions as a buried stop layer. Since the buried stop layer is formed between the substrate and the doped semiconductor layer and the buried stop layer has a characteristic of anti-corrosion, the buried stop layer may protect the doped semiconductor layer when thinning the substrate. Therefore, the uniformity of the top surface of the doped semiconductor layer may be improved, the CMP operation may be simplified, and the manufacturing cost may be further decreased.

<FIG> illustrate cross-sections of an exemplary 3D semiconductor device <NUM> at different stages of a manufacturing process, according to some aspects of the present disclosure, and <FIG> illustrates a flowchart of an exemplary method <NUM> for forming a 3D semiconductor device, according to some aspects of the present disclosure. For the purpose of better explaining the present disclosure, the cross-sections of 3D semiconductor device <NUM> in <FIG> and the flowchart of method <NUM> in <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

It is noted that x and y axes are included in <FIG> to further illustrate the spatial relationship of the components in a 3D semiconductor device having a substrate. A substrate includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device is determined relative to the substrate of the semiconductor device in they-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

As shown in <FIG> and operation <NUM> of <FIG>, a buried material <NUM> is formed in a first substrate <NUM>. In some implementations, first substrate <NUM> may be a silicon substrate. In some implementations, first substrate <NUM> may be made of any suitable materials, such as silicon, polysilicon, glass, or sapphire. In some implementations, buried material <NUM> may include oxygen, and buried material <NUM> may be implanted into first substrate <NUM> by performing an oxygen ion implantation. In some implementations, buried material <NUM> may include carbon, and buried material <NUM> may be implanted into first substrate <NUM> by performing a carbon ion implantation. In some implementations, buried material <NUM> may be implanted into first substrate <NUM> with a depth D as shown in <FIG>. Buried material <NUM> may be synthesized to a buried stop layer in later operations, and 3D semiconductor device <NUM> is flipped over to perform the bonding and thinning operations. When thinning first substrate <NUM>, a portion of first substrate <NUM> would be protected by the buried stop layer. After thinning first substrate <NUM> and removing the buried stop layer, a remainder of the first substrate may have a thickness equals to the implantation depth D. In some implementations, depth D may be between <NUM> and <NUM>. In some implementations, depth D may be between <NUM> and <NUM>. In some implementations, depth D may be between <NUM> and <NUM>.

After forming buried material <NUM> in first substrate <NUM>, a second implantation may be performed on first substrate <NUM> to form a doped semiconductor layer <NUM> in first substrate <NUM> above buried material <NUM>, as shown in <FIG>. In some implementations, doped semiconductor layer <NUM> may be an n-type doped semiconductor layer. In some implementations, doped semiconductor layer <NUM> may include silicon doped with n-type dopant(s), such as phosphorus, arsenic, antimony, bismuth, or lithium. In some implementations, doped semiconductor layer <NUM> may include polysilicon doped with n-type dopant(s), such as phosphorus, arsenic, antimony, bismuth, or lithium.

As shown in <FIG> and operation <NUM> of <FIG>, a first semiconductor structure <NUM> is formed on first substrate <NUM>. In some implementations, first semiconductor structure <NUM> may include a memory array semiconductor structure including a plurality of channel structures (not shown) each extending vertically through a memory stack (not shown) formed on doped semiconductor layer <NUM>. It is understood that the example of the memory array semiconductor structure is merely illustrative and is not limiting, and those skilled in the art can change to other suitable semiconductor devices according to requirements, all of which are within the scope of the present disclosure. For example, first semiconductor structure <NUM> may include any suitable logic devices (e.g., central processing unit (CPU), graphics processing unit (GPU), and application processor (AP)), volatile memory devices (e.g., dynamic random-access memory (DRAM) and static random-access memory (SRAM)), non-volatile memory devices (e.g., NAND Flash memory, NOR Flash memory), or any combinations thereof.

In some implementations, when forming first semiconductor structure <NUM>, one or more thermal operations may be used in various process stages. For example, a thermal annealing operation may be used to prepare and clean bonding surface, another thermal annealing operation may be used to form monocrystalline layer, a Rapid Thermal Anneal (RTA) or laser anneal may be used for a silicidation operation, a thermal CVD operation may be used to deposit metal layers, or a post deposition annealing may be used after a deposition operation. During the one or more thermal operations for forming first semiconductor structure <NUM>, buried material <NUM> may be synthesized to a buried stop layer <NUM> by the high temperature, as shown in <FIG>.

In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, buried stop layer <NUM> may include silicon oxide layer or silicon carbon layer. Since buried stop layer <NUM> may be simultaneously formed during the thermal operations for forming first semiconductor structure <NUM>, no additional annealing process is required to form buried stop layer <NUM>. Hence, the process step could be simplified, and process cost could be lowered.

As shown in <FIG> and operation <NUM> of <FIG>, a second semiconductor structure <NUM> is formed on a second substrate <NUM>. Second substrate <NUM> may be a silicon substrate. In some implementations, second substrate <NUM> may be made of any suitable materials, such as silicon, polysilicon, glass, or sapphire. Second semiconductor structure <NUM> may include a plurality of transistors (not shown) formed therein. In some implementations, the plurality of transistors may be formed by using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some implementations, second semiconductor structure <NUM> may include the peripheral circuits on second substrate <NUM> for facilitating the operations of the channel structures in first semiconductor structure <NUM> on first substrate. It is understood that the example of the transistor layer is merely illustrative and is not limiting, and those skilled in the art can change to other suitable semiconductor devices according to requirements, all of which are within the scope of the present disclosure. For example, second semiconductor structure <NUM> may include any suitable logic devices (e.g., CPU, GPU, and AP), volatile memory devices (e.g., DRAM and SRAM), non-volatile memory devices (e.g., NAND Flash memory, NOR Flash memory), or any combinations thereof.

First substrate <NUM> and first semiconductor structure <NUM> are flipped over and bonded with second semiconductor structure <NUM> and second substrate <NUM> in a face-to-face manner, as shown in <FIG> and operation <NUM>. The face-to-face manner bonding of first substrate <NUM> and second substrate <NUM> is that first semiconductor structure <NUM> is bonded to second semiconductor structure <NUM> and first substrate <NUM> and second substrate <NUM> are located on outer side after the bonding. In some implementations, a first bonding layer (not shown) may be formed above first semiconductor structure <NUM>, and a second bonding layer (not shown) may be formed above second semiconductor structure <NUM>. When first substrate <NUM> and first semiconductor structure <NUM> are bonded to second semiconductor structure <NUM> and second substrate <NUM>, the first bonding layer and the second bonding layer may be bonded together to form a bonding interface <NUM> between first semiconductor structure <NUM> and second semiconductor structure <NUM>. In some implementations, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in the first bonding layer and the second bonding layer are aligned and in contact with one another, such that memory stack and channel structures formed therethrough can be electrically connected to the peripheral circuits. In some implementations, the bonding is performed by hybrid bonding also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some implementations, bonding interface <NUM> is the place at which the two bonding layers and are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of the bottom bonding layer and the bottom surface of the top bonding layer after the bonding.

As shown in <FIG> and operation <NUM> of <FIG>, a thinning operation is performed on first substrate <NUM>. In some implementations, the thinning operation may include one or more steps to remove a portion of first substrate <NUM> sequentially. In some implementations, a grinding operation may be performed to coarsely remove a portion of first substrate <NUM> until a thinned layer of first substrate <NUM> remains on buried stop layer <NUM>, as shown in <FIG>. In some implementations, a wet etching operation may be performed to remove the residual first substrate <NUM> on buried stop layer <NUM> until exposing buried stop layer <NUM>. In some implementations, a CMP operation may be performed to remove buried stop layer <NUM> to expose doped semiconductor layer <NUM>, as shown in <FIG>. It is understood that there are various ways to perform the thinning operation and the removal stages, the processes described above are merely illustrative and is not limiting, and those skilled in the art can change to other suitable removal processes according to requirements, all of which are within the scope of the present application. For example, the coarse removal operation of first substrate <NUM> may be performed by using grinding, wet etching, dry etching, or CMP operation, or the residual first substrate <NUM> may be removed by wet etching, dry etching, or CMP operation.

After exposing doped semiconductor layer <NUM>, an interconnect layer may be further formed above doped semiconductor layer <NUM>, as shown in operation <NUM> of <FIG>. In some implementations, the interconnect layer may connect the memory array and the peripheral devices for controlling signals to and from the memory array. In some implementations, the interconnect layer may include contacts or at least one conductor layer, in which formed in one or more dielectric layers. In some implementations, the interconnect layer may include a plurality of interconnects, including lateral interconnect lines and vertical interconnect access (via) contacts. In some implementations, the interconnect layer may broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some implementations, doped semiconductor layer <NUM> may function as a source line of the channel structures formed in first semiconductor structure <NUM>. It is understood that in case logic devices, such as transistors, are formed in first semiconductor structure <NUM>, doped semiconductor layer <NUM> may function as the well of the transistors as well.

Since buried stop layer <NUM> is formed in first substrate <NUM> above doped semiconductor layer <NUM> and buried stop layer <NUM> has a characteristic of anti-corrosion, buried stop layer <NUM> may protect doped semiconductor layer <NUM> when removing the residual first substrate <NUM>. Therefore, the uniformity of the top surface of doped semiconductor layer <NUM> may be improved, the CMP operation may be simplified, and the manufacturing cost may be further decreased.

<FIG> illustrate cross-sections of an exemplary 3D memory device <NUM> at different stages of a manufacturing process, according to some implementations of the present disclosure, and <FIG> illustrates a flowchart of an exemplary method <NUM> for forming a 3D memory device, according to some aspects of the present disclosure. For the purpose of better explaining the present disclosure, the cross-sections of 3D memory device <NUM> in <FIG> and the flowchart of method <NUM> in <FIG> will be described together. <FIG> shows a semiconductor structure including a first substrate <NUM>, a buried material <NUM>, and a doped semiconductor layer <NUM>. The process for forming buried material <NUM> and doped semiconductor layer <NUM> in first substrate <NUM> may be similar to the operations shown in <FIG>.

As shown in <FIG> and operation <NUM> and according to the invention, a first semiconductor structure including first device layer <NUM> and first substrate <NUM> is formed. According to the invention, the first device layer <NUM> is formed on doped semiconductor layer <NUM>, doped semiconductor layer <NUM> is formed on buried stop layer <NUM>, and doped semiconductor layer <NUM> and buried stop layer <NUM> are formed in first substrate <NUM>. Doped semiconductor layer <NUM> may include silicon or polysilicon doped with n-type dopant(s), such as phosphorus, arsenic, antimony, bismuth, or lithium, using ion implantation and/or thermal diffusion.

During the one or more thermal operations for forming first device layer <NUM>, buried material <NUM> may be synthesized to buried stop layer <NUM> by the high temperature. In some implementations, buried stop layer <NUM> may include silicon oxide layer or silicon carbon layer. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation to synthesize buried stop layer <NUM> may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. Since buried stop layer <NUM> may be simultaneously formed during the thermal operations for forming first device layer <NUM>, no additional annealing process is required to form buried stop layer <NUM>. Hence, the process step could be simplified, and process cost could be lowered.

As shown in <FIG>, a memory stack including a plurality pairs of a conductive layer <NUM> and a dielectric layer <NUM> is formed on doped semiconductor layer <NUM>. The memory stack includes interleaved conductive layer <NUM> and dielectric layer <NUM>. In some implementations, conductive layer <NUM> may include a layer of metal (e.g., tungsten), and dielectric layer <NUM> may include a layer of silicon oxide. The memory stack may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, followed by a gate replacement process. As illustrated in <FIG>, a staircase structure can be formed on the edge of the memory stack, and an array of channel structures <NUM> each extending vertically through the memory stack and into doped semiconductor layer <NUM> is formed in first device layer <NUM>.

The array of channel structure <NUM> may be formed by first forming a plurality of channel holes in the channel region of first device layer <NUM> to expose doped semiconductor layer <NUM>. Then, a plurality of channel-forming layers may be conformally formed on sidewall and bottom of each channel hole. For example, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a polysilicon layer may be sequentially and conformally form on sidewall and bottom of the channel hole. An etch operation may be then performed to remove a portion of the channel-forming layer (e.g., the part that is formed at the bottom of the channel hole) to expose doped semiconductor layer <NUM>. Then, a dielectric core (e.g., a silicon oxide layer) may fill in the space at the center of the channel hole and electrically contact doped semiconductor layer <NUM>. In some implementations, after the removal of the silicon oxide/silicon nitride/silicon oxide (ONO) layers at the bottom of the channel hole and prior to the formation of the dielectric core, a polysilicon layer may be deposited over the ONO layers along the sidewall and on the bottom of the channel hole to form the semiconductor channel of channel structure <NUM>. As shown in <FIG> and according to the invention, the bottom portion of the semiconductor channel (e.g., a polysilicon layer) of channel structure <NUM> is in contact with doped semiconductor layer <NUM> to form an electrical connection therebetween.

In the present disclosure, since doped semiconductor layer <NUM> may function as a source line, a silicon epitaxy layer is not required on the bottom of the channel hole. Therefore, the epitaxial growth process (e.g., selective epitaxial growth, SEG) can be omitted to reduce the manufacturing cost.

As shown in <FIG> and operation <NUM> of <FIG>, a second semiconductor structure including a second device layer <NUM> and a second substrate <NUM> is formed. Second device layer <NUM> is formed on second substrate <NUM>. Second substrate <NUM> may be a silicon substrate. In some implementations, second device layer <NUM> includes a plurality of transistors and may be formed on second substrate <NUM> using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some implementations, doped regions (not shown) are formed in second device layer <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some implementations, isolation regions (e.g., STIs) are also formed in second device layer <NUM> by wet etching and/or dry etching and thin film deposition. In some implementations, second device layer <NUM> includes the transistors and functions as the peripheral circuits on second substrate <NUM>.

As shown in <FIG> and operation <NUM>, a bonding layer <NUM> is formed above second device layer <NUM>, and the first semiconductor structure and the second semiconductor structure are bonded by bonding layer <NUM> in a face-to-face manner. Bonding layer <NUM> includes bonding contacts electrically connected to first device layer <NUM> and second device layer <NUM>. To form bonding layer <NUM>, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. The bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., reactive ion etching (RIE), followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

In operation <NUM>, a portion of first substrate <NUM> is removed. In some implementations, the thinning operation may include one or more steps to remove a portion of first substrate <NUM> sequentially. In some implementations, a grinding operation may be performed to coarsely remove a portion of first substrate <NUM> until a thin layer of first substrate <NUM> remains on buried stop layer <NUM>, as shown in <FIG>. In some implementations, a wet etching operation may be performed to remove the residual first substrate <NUM> on buried stop layer <NUM> until exposing buried stop layer <NUM>. In some implementations, a CMP operation may be performed to remove buried stop layer <NUM> to expose doped semiconductor layer <NUM>, as shown in <FIG>. It is understood that there are various ways to perform the thinning operation and the removal stages, the processes described above are merely illustrative and is not limiting, and those skilled in the art can change to other suitable removal processes according to requirements, all of which are within the scope of the present application. For example, the coarse removal operation of first substrate <NUM> may be performed by using grinding, wet etching, dry etching, or CMP operation, or the residual first substrate <NUM> may be removed by wet etching, dry etching, or CMP operation.

After exposing doped semiconductor layer <NUM>, an interconnect layer <NUM> may be further formed above doped semiconductor layer <NUM>, as shown in <FIG>. In some implementations, the interconnect layer may connect the memory array and the peripheral devices for controlling signals to and from the memory array. In some implementations, doped semiconductor layer <NUM> may function as a source line of the transistor formed in first device layer <NUM>.

Since buried stop layer <NUM> is formed between first substrate <NUM> and doped semiconductor layer <NUM> and buried stop layer <NUM> has a characteristic of anti-corrosion, buried stop layer <NUM> may protect doped semiconductor layer <NUM> when removing the residual first substrate <NUM>. Therefore, the uniformity of the top surface of doped semiconductor layer <NUM> may be improved, the CMP operation may be simplified, and the manufacturing cost may be further decreased. Moreover, doped semiconductor layer <NUM> may function as the common source line of array of channel structures <NUM>, which may replace the source line function of a slit structure <NUM> extending vertically through the memory stack. As a result, slit structure <NUM> may be filled with dielectric materials, such as silicon oxide, without a conductor to reduce the parasitic capacitance between slit structure <NUM> and conductive layers <NUM>.

<FIG> illustrates a block diagram of an exemplary system <NUM> having a memory device, according to some aspects of the present disclosure. System <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in <FIG>, system <NUM> can include a host <NUM> and a memory system <NUM> having one or more 3D memory devices <NUM> and a memory controller <NUM>. Host <NUM> can be a processor of an electronic device, such as a PU, or a system-on-chip (SoC), such as an AP. Host <NUM> can be configured to send or receive the data to or from 3D memory devices <NUM>.

3D memory device <NUM> can be any suitable 3D memory devices, which are fabricated using a buried stop layer in the substrate as disclosed herein, for example, according to <FIG>.

Memory controller <NUM> is coupled to 3D memory device <NUM> and host <NUM> and is configured to control 3D memory device <NUM>, according to some implementations. Memory controller <NUM> can manage the data stored in 3D memory device <NUM> and communicate with host <NUM>. In some implementations, memory controller <NUM> is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller <NUM> is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller <NUM> can be configured to control operations of 3D memory device <NUM>, such as read, erase, and program operations. Memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in 3D memory device <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to 3D memory device <NUM>. Any other suitable functions may be performed by memory controller <NUM> as well, for example, formatting 3D memory device <NUM>. Memory controller <NUM> can communicate with an external device (e.g., host <NUM>) according to a particular communication protocol. For example, memory controller <NUM> may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc..

Memory controller <NUM> and one or more 3D memory devices <NUM> can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single 3D memory device <NUM> may be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., host <NUM> in <FIG>). In another example as shown in <FIG>, memory controller <NUM> and multiple 3D memory devices <NUM> may be integrated into an SSD <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., host <NUM> in <FIG>). In some implementations, the storage capacity and/or the operation speed of SSD <NUM> is greater than those of memory card <NUM>.

It is understood that the buried stop layer and the fabrication method thereof described above are not limited to the applications of 3D memory devices, memory devices, or 3D semiconductor devices and may be applied to any suitable non-memory semiconductor device in 2D or <NUM>. 5D architectures. <FIG> illustrates a flowchart of an exemplary method <NUM> for forming a semiconductor device, according to some aspects of the present disclosure. In operation <NUM>, a first implantation is performed on a first substrate to implant a buried material in the first substrate. In some implementations, the first substrate may be made of any suitable materials, such as silicon, polysilicon, glass, or sapphire. In some implementations, the buried material may include oxygen or carbon, and the buried material may be implanted into the first substrate by performing an oxygen ion implantation or a carbon ion implantation. In some implementations, after forming the buried material in the first substrate, a second implantation may be performed on the first substrate to form a doped semiconductor layer in the first substrate above the buried material. In some implementations, the doped semiconductor layer may be an n-type doped semiconductor layer. In some implementations, the doped semiconductor layer may include silicon doped with n-type dopant(s), such as phosphorus, arsenic, antimony, bismuth, or lithium. In some implementations, the doped semiconductor layer may include polysilicon doped with n-type dopant(s), such as phosphorus, arsenic, antimony, bismuth, or lithium.

In operation <NUM>, a buried stop layer is formed from the buried material in the first substrate, and a first device layer is formed on the first substrate. In some implementations, the first semiconductor structure may include a memory array semiconductor structure including a plurality of channel structures each extending vertically through a memory stack formed on the doped semiconductor layer. In some implementations, when forming the first semiconductor structure, one or more thermal operations may be used in various process stages. For example, a thermal annealing operation may be used to prepare and clean bonding surface, another thermal annealing operation may be used to form monocrystalline layer, an RTA or laser anneal may be used for a silicidation operation, a thermal CVD operation may be used to deposit metal layers, or a post deposition annealing may be used after a deposition operation. During the one or more thermal processes for forming the first semiconductor structure, the buried material may be synthesized to a buried stop layer by the high temperature.

In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the thermal operation may be performed at a temperature higher than <NUM>. In some implementations, the buried stop layer may include silicon oxide layer or silicon carbon layer. Since the buried stop layer may be simultaneously formed during the thermal operations for forming the first semiconductor structure, no additional annealing process is required to form the buried stop layer. Hence, the process step could be simplified, and process cost could be lowered.

In operation <NUM>, a portion of the first substrate is removed until being stopped by the buried stop layer. In some implementations, the thinning operation may include one or more steps to remove a portion of the first substrate sequentially. In some implementations, a grinding operation may be performed to coarsely remove a portion of the first substrate until a thinned layer of the first substrate remains on the buried stop layer. In some implementations, a wet etching operation may be performed to remove the residual first substrate on the buried stop layer until exposing the buried stop layer. In some implementations, a CMP operation may be performed to remove the buried stop layer to expose the doped semiconductor layer. It is understood that there are various ways to perform the thinning operation and the removal stages, the processes described above are merely illustrative and is not limiting, and those skilled in the art can change to other suitable removal processes according to requirements, all of which are within the scope of the present application.

According to the invention, a method for forming a 3D semiconductor device is disclosed, wherein a first implantation is performed on a first substrate of a first semiconductor structure to form a buried stop layer in the first substrate, wherein a second semiconductor device is formed, wherein the first semiconductor structure and the second semiconductor device are bonded, wherein the first substrate is thinned and the buried stop layer is removed, and an interconnect layer is formed above the thinned first substrate.

According to the invention, the first implantation is performed on the first substrate of the first semiconductor structure to implant a buried material in the first substrate, and a thermal operation is performed on the first semiconductor structure to synthesize the buried stop layer from the buried material.

In some implementations, a second implantation is performed on a portion of the first substrate above the buried material to form a doped semiconductor layer in the first substrate above the buried material. In some implementations, an oxygen ion implantation is performed to implant oxygen ions to a predefined depth in the first substrate. In some implementations, a carbon ion implantation is performed to implant carbon ions to a predefined depth in the first substrate.

In some implementations, the buried stop layer includes silicon oxide or silicon carbon. In some implementations, an n-type doping operation is performed in the first substrate above the buried material. In some implementations, the first substrate is doped with phosphorus, arsenic, antimony, bismuth, or lithium.

In some implementations, a first portion of the first substrate thinner than a depth of the buried stop layer is removed, and a second portion of the first substrate is removed to remove the buried stop layer.

According to the invention, the first semiconductor structure includes the first substrate, a memory stack disposed on the first substrate and including a plurality of conductor/dielectric layer pairs, and a plurality of channel structures each extending vertically through the memory stack. According to the invention, each of the channel structures includes a semiconductor channel extending vertically through the conductor/dielectric layer pairs, and a memory film disposed laterally between the conductor/dielectric layer pairs and the semiconductor channel.

According to another aspect of the present disclosure, a method for forming a 3D semiconductor device is disclosed. A first semiconductor structure is formed, the first semiconductor structure includes a first substrate and a first device layer formed on a first substrate. A buried stop layer is formed in the first substrate. A second semiconductor structure is formed, and the second semiconductor structure includes a second device layer formed on a second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner. A portion of the first substrate is removed until being stopped by the buried stop layer.

In some implementations, a first implantation is performed on the first substrate to implant a buried material in the first substrate, a second implantation is performed on a portion of the first substrate above the buried material to form a doped layer in the first substrate above the buried material, and a thermal operation is performed on the first semiconductor structure to synthesize the buried stop layer from the buried material.

In some implementations, the thermal operation is performed when forming the first device layer on the first substrate. In some implementations, the buried material includes oxygen ion or carbon ion. In some implementations, the buried stop layer includes silicon oxide or silicon carbon.

In some implementations, a first thinning operation is performed to remove a portion of the first substrate thinner than a depth of the buried stop layer, and a second thinning operation is performed to remove a portion of the first substrate until exposing the buried stop layer. In some implementations, the portion of the first substrate is removed until exposing the buried stop layer and removing the buried stop layer. In some implementations, the first thinning operation includes a wafer grinding operation. In some implementations, the second thinning operation includes a dry etching, a wet etching, or a CMP operation.

In some implementations, at least one of the first and second device layers includes an array of channel structures. In some implementations, a remainder of the first substrate after the removing functions as a source line of the array of channel structures.

According to a further aspect of the present disclosure, a method for forming a semiconductor device is disclosed. According to the invention, a first implantation is performed on a first substrate to implant a buried material in the first substrate. A buried stop layer is formed from the buried material in the first substrate, and a first semiconductor structure is formed on the first substrate. A portion of the first substrate is removed until being stopped by the buried stop layer.

In some implementations, a first thinning operation is performed to remove a portion of the first substrate thinner than a depth of the buried stop layer, and a second thinning operation is performed to remove a portion of the first substrate until exposing the buried stop layer. In some implementations, the portion of the first substrate is removed until exposing the buried stop layer and removing the buried stop layer. In some implementations, the first thinning operation includes a wafer grinding operation. In some implementations, the second thinning operation includes a dry etching, a wet etching or a CMP operation.

In some implementations, a thermal operation is performed on the semiconductor device to synthesize the buried stop layer from the buried material. In some implementations, the buried material includes oxygen ion or carbon ion. In some implementations, the buried stop layer includes silicon oxide layer or silicon carbon layer.

Claim 1:
A method for forming a three-dimensional (3D) semiconductor device, comprising:
performing a first implantation on a first substrate (<NUM>) of a first semiconductor structure to form a buried stop layer (<NUM>) in the first substrate (<NUM>);
forming a second semiconductor structure (<NUM>);
bonding the first semiconductor structure and the second semiconductor structure (<NUM>);
forming the first semiconductor structure including a first device layer (<NUM>) and the first substrate (<NUM>);
forming a doped semiconductor layer (<NUM>) on the buried stop layer (<NUM>);
forming the first device layer (<NUM>) on the doped semiconductor layer (<NUM>);
forming the doped semiconductor layer (<NUM>) and the buried stop layer (<NUM>) in the first substrate (<NUM>);
wherein the first semiconductor structure includes the first substrate (<NUM>), a memory stack disposed on the first substrate (<NUM>) and including a plurality of conductor/dielectric layer pairs, and a plurality of channel structures (<NUM>) each extending vertically through the memory stack,
wherein each of the channel structures (<NUM>) includes a semiconductor channel extending vertically through the conductor/dielectric layer pairs, and a memory film disposed laterally between the conductor/dielectric layer pairs and the semiconductor channel, wherein a bottom portion of the semiconductor channel is in contact with the doped semiconductor layer (<NUM>) to form an electrical connection therebetween;
thinning the first substrate (<NUM>) and removing the buried stop layer (<NUM>); and
forming an interconnect layer (<NUM>) above the thinned first substrate (<NUM>).