Patent Description:
Multi-level Flying Capacitor Converters (FCCs) can be used in many applications, including DC-AC drives for electric motors, DC-AC amplifiers for powering loads that require high precision voltage and/or current regulation, such as gradient coils of MRI (Magnetic Resonance Imaging) scanners and linear motors of lithography machines, DC-DC interfaces for photo-voltaic installations, etc. They offer an attractive alternative to conventional two-level converter topologies, particularly in high-voltage applications, due to the higher number of voltage levels which enables the use of semiconductor switches with lower voltage rating which are generally cheaper and have relatively higher performance (i.e., they are more efficient) compared to switches with high voltage rating. Moreover, the higher number of voltage levels results in an increased effective switching frequency leading to smaller, cheaper (passive) output filters and increased control bandwidth of the output voltage and/or current. Compared to other multi-level converters the FCC offers additional advantages, i.e., due to the employment of a single DC source no isolated voltage sources are required as is the case for the cascaded H-bridge converters and no high-power clamping diodes, which are oftentimes accompanied with anti-parallel synchronously operated semiconductor switches, like in the Neutral Point Clamped (NPC) topologies. Moreover, FCCs can operate in bidirectional DC/DC, AC/DC, and DC/AC mode and can easily be paralleled to support high output current and output power levels which makes them particularly suitable for the use of new fast-switching Silicon Carbide (SiC) MOSFETs and Gallium Nitride (GaN) FETs which cannot be easily paralleled due to the need for ultra-precise gate-drive timing to avoid unequal current distribution and excessive switching losses. Lastly, interleaving of paralleled FCC stages enables an even higher effective switching frequency and a modular (scalable) design.

One drawback of FCCs is that balancing of the Flying Capacitor (FC) voltages is required in practice to avoid large increases of the harmonics in the output voltage as well as over-voltages across the semiconductor switches, which is especially challenging when (i) powering high-dynamic loads that cause large unequal steps in the duty cycles of the different switching cells within an FCC stage and are therefore a driving force for the imbalance of the FC voltages, (ii) powering loads that require arbitrary output voltage or current waveforms, particularly output current waveforms having large intervals with low current value that does not allow to perform active balancing of the FCs based on compensation of the Pulse-Width Modulated drive signals of the switches and (iii) connecting the FCC to a DC bus (DC source) with dynamically changing DC-bus voltage. The latter is the case when, for example, multiple FCCs or loads are connected to the same DC-bus requiring the FC voltages to 'follow' the DC-bus voltage change to keep the desired voltage ratio constant. Since the performance and reliability (related to over-voltages of the semiconductor switches) depend on the balancing of the individual FC voltages, FCCs are seldom employed in industry applications, despite the many advantages.

Modulation-inherent natural/passive FC balancing techniques are known, which rely on the natural balancing of the FC voltages resulting from the applied PWM modulation of the semiconductor switches in normal operation of the FCC and the currents correspondingly flowing in the converter. However, as has been extensively described in literature, these 'self-balancing' methods cannot guarantee balancing of the FC voltages in many practical applications and especially for the cases outlined above, since, inter alia, switching cells have to operate at the same duty cycle, the semiconductor switches must have the same characteristics, and the load current needs to be symmetrical and non-zero. Especially the constraint related to the symmetrical and non-zero load current is a major issue for loads requiring arbitrary output voltage and current waveforms such as for example the gradient coils of an MRI scanner or linear motors of lithography machines. On the other hand, modulation-inherent natural/passive FC balancing might be sufficiently effective in non-dynamic AC motor-drive applications where the output currents are sinusoidal and steady.

As opposed to the modulation-inherent FC balancing techniques, methods for achieving modulation-influencing active FC balancing operation using active (controlled) techniques that influence the converter modulation are known from:.

Even though these active balancing methods improve the balancing performance, the controlled change of the voltage of the FCs is heavily dependent on the amplitude of the load current meaning that adequate balancing is still impossible during time intervals when the load draws zero or quasi-zero current at the output of the FCC. Especially when the voltage of the DC-bus (DC source) is changing during such zero-load-current interval, e.g., when other loads connected to the same DC-bus are draining the DC-bus capacitors, the FC voltages cannot be actively controlled to follow the resulting DC-bus voltage change. A typical example of an application where such conditions exist is a gradient amplifier that powers the three gradient coils of an MRI scanner. It is a common situation that two of the three gradient coils are provided with maximum power and are draining the DC-bus capacitors while the current in the third gradient coils is zero for a certain interval. The FC voltages of the FCC that is driving this third coil cannot be adequately balanced in this situation. Moreover, so called intermediate modulation regions on an FCC exist in which redundant switching states of the topology are not effectively utilized. Adequate modulation-influencing active FC balancing is not possible in such intermediate regions.

To further improve balancing and to cope with all critical operating conditions of the aforementioned methods, including zero or quasi-zero output current or intermediate modulation regions, it is known to utilize additional (dissipative) passive components, so-called balance boosters (BBs). In <NPL>, these balance boosters are classified in internal and external boosters. Common for all balance boosters, is that a dissipative element (resistor and/or Zener diode) is used to draw the active power required to balance the FCs. This an important disadvantage due to the high losses which requires large and expensive components and additional heat extraction hardware, especially in high-power applications where large FCs need to be selected to deal with the high output currents and in highly dynamic applications where intensive repetitive balancing of the FC voltages takes place. Furthermore, balance boosters which include capacitors are increasing the effective capacitance parallel to the main semiconductor switches of the FCC, thus increasing the switching losses. In addition, balance boosters including capacitors operate only during a transient and are ineffective during converter standby or when modulation indices are close to the limits (i.e., duty-cycles close to <NUM> or to <NUM>).

There is therefore a need in the art to provide (multi-level) FC circuits with an improved voltage balancing circuit which overcomes the drawbacks of the prior art. It is a further object of the present disclosure to provide non-dissipative voltage balancing circuits capable of balancing the FC voltages of an FCC in a quasi-lossless manner. In particular, the non-dissipative balance boosters are configured to exchange energy between the FCs themselves and/or between the FCs and a voltage source, such as the DC-bus voltage source (e.g. capacitors).

According to a first aspect of the invention, there is therefore provided an electrical converter comprising a flying capacitor circuit as set out in the appended claim <NUM>.

By providing the balancing circuit according to the present disclosure, it is possible to charge and to discharge the flying capacitors by transferring energy in a non-dissipative manner, hence obtaining a nearly lossless voltage balancing of the flying capacitors. Therefore, the balancing circuits of the present disclosure advantageously do not need or comprise dissipative elements. Additionally, it was observed through simulations described further herein, that the balancing circuits according to the present disclosure allow for obtaining such capacitor voltage balancing with low balancing currents, hence allowing utilizing semiconductor switching devices with low current ratings. Moreover, it was observed that with the balancing circuits of the present disclosure, the flying capacitor converters can obtain a voltage at the switch node (output) with very low harmonic content of the main switching frequency.

The above advantages are particularly evident when the balancing circuit comprises active switching devices which are operated to discharge the at least one flying capacitor by connecting the at least one flying capacitor in parallel with the voltage source. A time differentiation logic is implemented, which shifts the turn-ON and/or turn-OFF instants of the active switching devices compared to synchronous operation with a respective one of the plurality of first switching devices. By so doing, balancing performance can be optimised in terms of speed of balancing and/or control of balancing currents, particularly to avoid large current spikes and saturation of the balancing inductor. This time differentiation logic is configured to delay turn-ON of the actively operated switching device with respect to a turn-ON instant of the respective one of the plurality of first switching devices and/or to reduce an ON-time of the actively operated switching device compared to an on-time of the respective one of the plurality of first switching devices. The turn-ON delay and/or the ON-time can be adapted based on the duty cycle of the respective one of the plurality of first switching devices and/or based on the output current of the converter.

Advantageously, the electrical converter comprises a control unit and at least one voltage measurement device coupled to the control unit and configured to sense a voltage across the at least one flying capacitor and/or the voltage source. The control unit is configured to generate pulse width modulation control signals for operating the plurality of first switching devices and further comprises control logic configured to generate control signals, which can be pulse width modulated signals, or be derived therefrom. These control signals are configured to operate the actively operated switching device to discharge the at least one flying capacitor based on the pulse width modulation control signal of a respective one of the plurality of first switching devices and on the sensed voltage by connecting the at least one flying capacitor in parallel with the voltage source or in parallel with another capacitor of the at least one flying capacitor. The control logic is advantageously configured to implement a voltage offset triggering operation of the actively operated switching device in discharge mode and/or to adjust an ON-time of the actively operated switching device compared to synchronous operation with the respective one of the plurality of first switching devices, e.g. by implementing a time differentiation logic, e.g. delay turn-ON of the actively operated switching device with respect to a turn-ON instant of the respective one of the plurality of first switching devices and/or to reduce an ON-time of the actively operated switching device compared to an on-time of the respective one of the plurality of first switching devices. The turn-ON delay and/or the ON-time are advantageously adjusted based on the sensed voltage to optimise balancing performance in terms of speed of balancing and/or control of balancing currents, particularly to avoid large current spikes and saturation of the balancing inductor.

According to a second aspect of the invention, there is provided an amplifier system as set out in the appended claim <NUM>.

There are described methods of balancing a voltage of a flying capacitor, such as a flying capacitor comprised in electrical converters of the present disclosure.

Referring to <FIG>, the general topology of a three-level flying capacitor converter <NUM> is first described for ease of understanding. FCC <NUM> comprises a DC-bus <NUM> comprising a series connection of two DC-bus capacitors CiXY, CiYZ each having a voltage of half the DC-bus voltage (νCiXY = νCiYZ = Vi/<NUM>). The terminals of the DC-bus capacitors are denoted X, Y, Z with terminal Y forming the common node between DC-bus capacitors CiXY, CiYZ and hence forming the midpoint of the DC-bus <NUM>. The FCC <NUM> further comprises a flying capacitor (FC) circuit <NUM> and an output filter with inductor and capacitor Lo, Co respectively. FC circuit <NUM> is arranged as a flying capacitor bridge leg and comprises a switch node sn, two half-bridge semiconductor switch pairs (i.e. half-bridge S1a,S1b and half-bridge S<NUM>a,S<NUM>b) and a flying capacitor C<NUM>. Each switch S<NUM>a, S<NUM>b and S<NUM>a, S<NUM>b can be formed of an actively operated semiconductor switch, particularly a metal oxide semiconductor field effect transistor (MOSFET) and a diode arranged in antiparallel with the MOSFET. The switches of the first switch pair S<NUM>a, S<NUM>b connect the respective positive and negative terminals of the FC C<NUM> to the switch node sn. The switches of the second switch pair S<NUM>a, S<NUM>b connect the respective positive and negative terminals of the FC C<NUM> to the upper and lower DC-bus nodes X, Z, respectively. The switches of each of the first and second switch pairs are generally operated in a complementary manner, as is well-known in the art, i.e. when one switch (e.g. S1a) is closed, the other one (e.g. S1b) is open and vice versa. The voltage (νC<NUM>) of FC C<NUM> is controlled to be equal to, or close to equal to, half the DC-bus voltage (i.e. νC<NUM> = Vi/<NUM>) to avoid large harmonic content in the output voltage νo and to assure equal distribution of the voltages across the semiconductor switches and thus avoid over-voltages. This principle can be extrapolated to FC circuits comprising additional flying capacitors, to provide additional voltage levels at the switch node.

For purpose of understanding aspects of the present disclosure, conventional modulation of the FCC is assumed, in which the outer half bridge (formed by S<NUM>a and S<NUM>b which are complementary switched) and the inner half bridge (formed by S<NUM>a and S<NUM>b which are complementary switched) are operated with equal duty-cycle d (i.e. ds<NUM>a = ds<NUM>a = νo/Vi + <NUM>/<NUM>, and ds<NUM>b = <NUM> - ds1a, ds<NUM>b = <NUM> - ds<NUM>a) and <NUM>° phase-shifted PWM signals. Knowing that the duty-cycle d, which is the relative on-time of a semiconductor switch within a switching period Ts = <NUM>/fs, with fs the switching frequency, can be controlled between <NUM> and <NUM>, the output-voltage range of the FCC <NUM> is -Vi/<NUM> ≤ νo ≤ Vi/<NUM> while the switch-node voltage νsn typically alternates between two of three possible voltage levels at a fundamental frequency component of <NUM> · fs.

The present disclosure provides non-dissipative balance boosters (i.e., voltage balancing circuits) that are capable of auto-balancing the FC voltages of a flying capacitor converter by exchanging energy between the FCs themselves and/or between the FCs and a voltage source, such as the DC-bus voltage sources (e.g. capacitors) in a quasi-lossless manner. The balance boosters of the present disclosure can be classified into two groups:.

In contrast with the dissipative balance boosters of the prior art which balance the FCs by removing energy from the FCs and dissipating this energy in dissipative passive components, i.e., resistors and/or Zener diodes (or the like, e.g. varistors), in the present disclosure balancing is obtained by exchanging energy between the FCs themselves and/or between the FCs and a voltage source, e.g. the DC-bus voltage sources (e.g. DC-bus capacitors) in a quasi-lossless manner through use of non-dissipative components:.

Furthermore, the balance booster (voltage balancing) circuits advantageously do not comprise additional capacitors that would increase the effective capacitance parallel to the main semiconductor switches of the FCC, avoiding a large increase of the switching losses. Nevertheless, the effective capacitance parallel to the power transistors is increased by the output capacitance of the diodes and/or semiconductor switches used in the disclosed balance booster circuits which is typically very low, especially since these devices are generally low-power rated and therefore have a small semiconductor area with low parasitic capacitance.

The passive non-dissipative charging balance boosters of group I rely on one or more passive components (at least one diode and one inductor) to charge a FC when its voltage is too low. The charging takes place in a non-controlled manner (passively) and is obtained by transferring energy from the voltage source (e.g., the DC-bus) to the FCs and/or between the FCs themselves.

A first implementation of such non-dissipative charging balance booster circuit is shown in <FIG>. The balance booster circuit <NUM> comprises a passive balancing diode DB,a<NUM> and balancing inductor LB,<NUM> which are connected in series between the upper terminal r<NUM> of the FC C<NUM> to be balanced and the DC-bus midpoint Y. When semiconductor switch S<NUM>b is in the on-state and voltage νC<NUM> < Vi/<NUM> (with Vi/<NUM> the required voltage of C<NUM>) a current will flow from Y into r<NUM> according to the path <NUM> shown in <FIG> (DC-bus capacitor CiYZ acts in parallel with C<NUM>), i.e. the current flows through inductor LB,<NUM> (iLB<NUM> > <NUM>) and diode DB,a<NUM>, charging C<NUM>. As long as νC<NUM> < Vi/<NUM>, energy will be transferred from the DC-bus capacitor CiYZ to C<NUM> in each interval of the switching period where SZb is in the on-state. This charging of C<NUM> occurs in a quasi-lossless manner as no dissipative components are present in the conduction path <NUM>. It will be convenient to note that the on-state of S2b occurs every switching cycle except for the case when ds<NUM>b = <NUM> which typically never occurs in a real application (at least not for a long time interval). Discharging of C<NUM> is not possible through inductor LB,<NUM> and diode DB,a<NUM> due to the unipolar current direction of the diode. The minimum voltage rating of the diode DB,a<NUM> is equal to Vi/<NUM> which is the same as the minimum voltage rating of the main semiconductor switches (S<NUM>a, S<NUM>a, S<NUM>b, S<NUM>b).

In <FIG>, an extended implementation of the voltage balancing (balance booster) circuit <NUM> of <FIG> is shown where an additional balancing diode DB,b<NUM> is connected between the lower terminal s<NUM> of C<NUM> and the anode of diode DB,a<NUM> forming a half-bridge pair (DB,a<NUM>, DB,b<NUM>). The inductor LB,<NUM> of the circuit <NUM> is connected between the DC-bus midpoint Y and the anode of diode DB,a<NUM>. When S2a is in the on-state and voltage νC<NUM> < Vi/<NUM> a current will flow from s<NUM> into Y according to the path <NUM> shown in <FIG> (DC-bus capacitor CiXY acts in parallel with C<NUM>), i.e. the current flows through inductor LB,<NUM> (iLB<NUM> < <NUM>) and diode DB,b<NUM>, charging C<NUM>. As long as νC<NUM> < Vi/<NUM>, energy will be transferred from the DC-bus capacitor CiXY to C<NUM> each interval of the switching period where S2a is in the on-state. In combination with the charging path <NUM> depicted in <FIG>, i.e. via switch S<NUM>b, inductor LB,<NUM> and diode DB,a<NUM>, an alternating balancing path and thus faster balancing of C<NUM> is obtained compared to the circuit of <FIG> with a single diode. In addition, a more symmetric charging with respect to the load conditions is achieved.

An alternative implementation of a balance booster circuit <NUM> to charge C<NUM> is shown in <FIG>, where two balancing inductors LB,a<NUM> and LB,b<NUM> are used which, however, each see a smaller average charging current compared to the inductor LB,<NUM> of circuit <NUM>, i.e. charging current flows from Y through DB,a<NUM> and LB,a<NUM> into r<NUM> when S<NUM>b is in the on-state and νC<NUM> < Vi/<NUM>, and charging current flows from s<NUM> through DB,b<NUM> and LB,b<NUM> into Y when S2a is in the on-state and νC<NUM> < Vi/<NUM>. So the charging current is distributed among two balancing inductors instead of shared by one.

The non-dissipative charging balance booster circuits <NUM>, <NUM> can also be applied for FCCs with a higher number of FCs, for example a four-level FCC <NUM> shown in <FIG> with three half-bridge semiconductor switch pairs (i.e. half-bridge S<NUM>a, S<NUM>b, half-bridge S<NUM>a,S<NUM>b and half-bridge S<NUM>a, S<NUM>b) connected between DC-bus terminals X,Z formed by a series connection of three DC-bus capacitors CiXY<NUM>, CiY<NUM>Y<NUM>, CiY<NUM>Z. The DC-bus <NUM> comprises four terminals X, Z and Y1, Y2, with Y1 and Y2 being common nodes of DC-bus capacitors CiXY<NUM>, CiY<NUM>Y<NUM> and CiY<NUM>Y<NUM>, CiY<NUM>Z respectively. The three DC-bus capacitors have a voltage of one third the DC bus voltage (νCiXY<NUM> = νCiY<NUM>Y2 = νCiY2Z = Vi/<NUM>). The FCC <NUM> further comprises an output filter Lo, Co, and two FCs C<NUM> and C<NUM> whose voltages need to be controlled to respectively one-third and two-third of the DC-bus voltage (i.e. νC<NUM> = Vi/<NUM>, νC<NUM> = <NUM>Vi/<NUM>) to avoid large harmonic content in the output voltage and to assure equal distribution of the voltages across the semiconductor switches and thus avoid over-voltages. The operating principle of this four-level FCC is similar to that of the three-level FCC <NUM>, i.e., the half-bridges are operated with equal duty-cycle (i.e. ds<NUM>a = ds<NUM>a = ds<NUM>a = νo/Vi + <NUM>/<NUM>, and d<NUM>b = <NUM> - ds<NUM>a, ds<NUM>b = <NUM> - ds<NUM>a, ds<NUM>b = <NUM> - ds3a) and <NUM>° phase-shifted PWM signals. Referring to <FIG>, a balance booster circuit <NUM> for the four-level FCC <NUM> comprises a first balancing circuit for C<NUM> consisting of balancing diodes DB,a<NUM> and DB,b<NUM> and balancing inductors LB,a<NUM> and LB,b<NUM> and a second balancing circuit for C<NUM> consisting of balancing diodes DB,a<NUM> and DB,b<NUM> and balancing inductors LB,a<NUM> and LB,b<NUM>. Inductors LB,a<NUM> and LB,b<NUM> are thus shared by both first and second balancing circuits and are respectively connected to the DC-bus voltage nodes Y1 and Y2 which have voltages of respectively <NUM>Vi/<NUM> and Vi/<NUM> with respect to the negative DC-bus rail Z.

Charging of C<NUM> can take place through inductor LB,b<NUM>, diode DB,a<NUM> and through switches S2b and S<NUM>b when they are both in the on-state, i.e., when voltage νC<NUM> < Vi/<NUM> a current will flow from Y2 into r<NUM> according to the path <NUM> shown in <FIG> (DC-bus capacitor CiY<NUM>Z acts in parallel with C<NUM>), i.e. the current flows through inductor LB,b<NUM> (iLBb<NUM> > <NUM>) and diode DB,a<NUM>, charging C<NUM>. As long as νC<NUM> < Vi/<NUM>, energy will be transferred from the DC-bus capacitor CiY<NUM>Z to C<NUM> in each interval of the switching period where S2b and S<NUM>b are in the on-state. Charging of C<NUM> can also take place through inductor LB,a<NUM>, diode DB,b<NUM> and through switches S2a and S3a when they are both in the on-state, i.e. when voltage νC<NUM> < Vi/<NUM> a current will flow from s<NUM> into Y1 according to the path <NUM> shown in <FIG> (DC-bus capacitor CiXY<NUM> acts in parallel with C<NUM>), i.e. the current flows through inductor LB,a<NUM> (iLBa<NUM> < <NUM>) and diode DB,b<NUM>, charging C<NUM>. As long as νC<NUM> < Vi/<NUM>, energy will be transferred from the DC-bus capacitor CiXY<NUM> to C<NUM> in each interval of the switching period where S<NUM>a and S3a are in the on-state. Since switches S<NUM>a, S2b and S<NUM>a, S<NUM>b are switched complementarily in conventional FCC operation, the current paths <NUM> and <NUM> are alternated.

Charging of C<NUM> can take place through inductor LB,a<NUM>, diode DB,a<NUM> and through switch S<NUM>b when it is in the on-state, i.e. when voltage νC<NUM> < <NUM>Vi/<NUM> a current will flow from Y1 into r<NUM> according to the path <NUM> shown in <FIG> (the series connection of DC-bus capacitors CiY<NUM>Y<NUM> and CiY<NUM>Z acts in parallel with C<NUM>), i.e. the current flows through inductor LB,a<NUM> (iLBa<NUM> > <NUM>) and diode DB,a<NUM>, charging C<NUM>. As long as νC<NUM> < <NUM>Vi/<NUM>, energy will be transferred from the DC-bus capacitors CiY<NUM>Y<NUM> and CiY<NUM>Z to C<NUM> in each interval of the switching period where S<NUM>b is in the on-state. Charging of C<NUM> can alternatively take place through inductor LB,b<NUM>, diode DB,b<NUM> and through switch S3a when it is in the on-state, i.e. when voltage νC<NUM> < <NUM>Vi/<NUM> a current will flow from s<NUM> into Y2 according to the path <NUM> shown in <FIG> (the series connection of DC-bus capacitors CiXY, and CiY<NUM>Y<NUM> acts in parallel with C<NUM>), i.e. the current flows through inductor LB,b<NUM> and diode DB,b<NUM>, charging C<NUM>. As long as νC<NUM> < 2Vi/<NUM>, energy will be transferred from the DC-bus capacitors CiXY<NUM> and CiY<NUM>Y<NUM> to C<NUM> in each interval of the switching period where S<NUM>a is in the on-state.

For the non-dissipative charging balance booster circuit <NUM>, two main semiconductor switches need to be simultaneously in the on-state in order to charge C<NUM>, i.e. either S2b and S<NUM>b, or S<NUM>a and S<NUM>a. Depending on the output voltage νo of the FCC <NUM> and depending on the applied modulation scheme (here conventional modulation is assumed), within a switching period there are typically always intervals where S2b and S<NUM>b are simultaneously in the on-state and/or intervals where S<NUM>a and S<NUM>a are simultaneously in the on-state, guaranteeing charging of C<NUM> in any load conditions. Balancing diodes DB,a<NUM> and DB,b<NUM> need to be rated for <NUM>Vi/<NUM> while balancing diodes DB,a<NUM> and DB,b<NUM> need to be rated for Vi/<NUM>.

Referring to <FIG>, an alternative implementation of a FCC <NUM> comprising a non-dissipative charging balance booster circuit <NUM> differs from the FCC <NUM> and balance booster circuit <NUM> in that FC C<NUM> of FCC <NUM> is now implemented as a series connection of two capacitors C2a and C2b whose voltages need to be controlled to one-third of the DC-bus voltage each (i.e. νC<NUM>a = νC<NUM>b = Vi/<NUM>). The flying capacitor circuit of FCC <NUM> hence comprises two capacitor cells <NUM>, <NUM> Capacitor cell <NUM> comprises capacitor C<NUM>. Capacitor cell <NUM> comprises capacitors C2a, C2b connected in series. All capacitors C<NUM>, C2a, C2b of the capacitor cells <NUM>, <NUM> have equal reference voltage corresponding to one third of the DC-bus voltage Vi.

Balance booster circuit <NUM> comprises a balancing circuit of C<NUM> which comprises balancing diodes DB,a<NUM> and DB,b<NUM> and balancing inductor LB,<NUM> connected to the midpoint t<NUM> of C2a and C<NUM>b. Charging of C<NUM> now occurs by transferring energy from C2a to C<NUM> when S<NUM>a is in the on-state and νC<NUM> < Vi/<NUM> assuming that νC<NUM>a = Vi/<NUM>, and by transferring energy from C2b to C<NUM> when S2b is in the on-state and νC<NUM> < Vi/<NUM> assuming that νC<NUM>b = Vi/<NUM>. The charging conduction path when S2a is in the on-state runs from capacitor C2a through S2a to capacitor C<NUM> and further from terminal s<NUM> through diode DB,b1 and inductor LB,<NUM> to node t<NUM>. The charging conduction path when S2b is in the on-state runs from capacitor C2b to node t<NUM>, inductor LB,<NUM>, diode DB,a1 and terminal r<NUM> to capacitor C<NUM> and further from terminal s<NUM> through S2b to C2b. Since S2a and S2b are switched complementarily, the two conductions paths alternate. Charging of C<NUM>, however, results in discharging of C2a and/or C2b which could result in νC<NUM>a and/or νC<NUM>b to drop below Vi/<NUM> causing an imbalance situation. This can be compensated by having balance booster circuit <NUM> comprise a balancing circuit of C2a and C2b which comprises balancing diodes DB,a<NUM> and DB,b<NUM> and balancing inductor LB,<NUM>. Charging of C2a occurs by transferring energy from CiXY, to C2a when S<NUM>a is in the on-state and νC<NUM>a < Vi/<NUM> assuming that νCiXY<NUM> = Vi/<NUM>. The conduction path runs from CiXY1 through S3a to C2a and further from node t<NUM> through inductor LB,<NUM> and diode DB,a2 to terminal Y1. Charging of C<NUM>b occurs by transferring energy from CiY<NUM>Z to C<NUM>b when S<NUM>b is in the on-state and νC<NUM>b < Vi/<NUM> assuming that νCiY<NUM>Z = Vi/<NUM>. The conduction path runs from CiY<NUM>Z (terminal Y2) through diode DB,b<NUM> and inductor LB,<NUM> to node t<NUM> and capacitor C2b and further through S<NUM>b to terminal Z. Note that here diodes DB,a<NUM> and DB,b<NUM>, as well as diodes DB,a<NUM> and DB,b<NUM> need to be rated for Vi/<NUM>. Generally it can be said that the non-dissipative charging balance booster circuit of <FIG> charges C2a, C2b and C<NUM> in a cascaded manner (C2a and C<NUM>b are charged from the DC-bus <NUM> while C<NUM> is charged from C2a and C2b).

When charging is required for all FCs (C<NUM>a,C<NUM>b, C<NUM>), the FCs C2a and C<NUM>b will reach the reference voltage (Vi/<NUM>) faster than C<NUM> as determined by complex charging dynamics, including FC ripple voltages which are influenced by the load conditions. The passive non-dissipative charging of the FCs via diodes can result in a slight voltage lift (offset voltage) of the average FC voltage with respect to the reference value. This is the result of a natural clamping mechanism where the balancing diodes conduct when the voltage of the respective FCs is lower than the voltage at the node to which they are clamped during the on-state of one of the switches of the FCC, as explained above. Therefore, and in case the FC voltages have a ripple voltage caused by the periodical flow of the load current through the FCs, the average value of the FC voltages can be slightly higher or lower than the reference voltage which is further referred to as FC voltage lift. This voltage lift results in a minor increase of the harmonics in the output voltage as well as slight unequal distribution of the voltage across the semiconductor switches, which are typically both within acceptable values and still greatly less than in case no balance booster circuit is used, as will also be illustrated in the simulation examples further below. This applies for all the charging balance booster circuits of the present disclosure.

In the following, some examples of active non-dissipative balance boosters (Group II) are described. These active balance boosters are capable of charging and discharging FCs. The below active non-dissipative balance boosters rely on one or more active balancing components, i.e. comprising at least one actively operated semiconductor switch, and passive balancing components, i.e. comprising at least one diode and one inductor, to discharge a FC when its voltage is too high and also charge the FC when its voltage is too low. The diode can refer to the internal anti-parallel body-diode of the actively operated semiconductor switch (e.g. MOSFET). The discharging takes place in a controlled manner through active operation of the at least one semiconductor switch and is obtained by transferring energy from the FCs to the DC-bus and/or between the FCs themselves. The charging can take place in a non-controlled manner, i.e. passively, through operation of the at least one diode and is obtained by transferring energy from the DC-bus to the FCs and/or between the FCs themselves according to the principles described for the Group I balance boosters.

For any of the circuits of Group I, during charging of a FC, a parallel connection of the particular FC whose voltage is too low with another source (e.g. DC-bus capacitor) occurs due to the closing of one or more of the main semiconductor switches of the FCC and due to forward bias condition of a balancing diode as a result of the voltage difference between the mentioned source and the particular FC to be charged. When the source voltage is higher than the FC voltage, the balancing diode is forward biased and a charging current will start to flow. This charging current is limited by the corresponding balancing inductor arranged in the path of the charging current, hence avoiding too high charging current. By connecting the balancing diode and inductor to appropriate voltage nodes (e.g. created at the DC-bus), the FCs are charged to the correct voltage levels. This also means that the voltage which is inducing the charging current in the balancing inductor is small and equal to the imbalance voltage between the source and the FC to be balanced.

By now adding active semiconductor balancing switches in anti-parallel with the balancing diodes, it is possible to also discharge the FCs when their voltage is higher than the mentioned source voltage. This is applicable for all the previously disclosed passive non-dissipative charging balance boosters (Group I) and is illustrated in <FIG> by extending the example of <FIG> considering a three-level FCC <NUM> with a single FC C<NUM> whose voltage needs to be controlled to be equal to, or close to equal to, half the DC-bus voltage (i.e. νC<NUM> = Vi/<NUM>). Compared to the passive balance booster circuit <NUM> of <FIG>, the active balance booster circuit <NUM> of <FIG> comprises active semiconductor switches SB,a1 and SB,b1 in replacement of the diodes DB,a1 and DB,b<NUM> of circuit <NUM>. Charging of C<NUM> is achieved through the (internal) anti-parallel diode of SB,b1 thereby obtaining the current path <NUM> as indicated in <FIG>. Discharging of C<NUM> can be achieved by switching balancing switch SB,a<NUM> synchronously with main semiconductor switch S<NUM>b so that FC C<NUM> is connected parallel to DC-bus capacitor CiYZ. SB,a<NUM> is advantageously turned on (synchronously with S2b) when νC<NUM> > Vi/<NUM>. Discharging of C<NUM> can alternatively or in addition be achieved by switching balancing switch SB,b<NUM> synchronously with main semiconductor switch S<NUM>a, so that FC C<NUM> is connected parallel to DC-bus capacitor CiXY. SB,b<NUM> is advantageously turned on (synchronously with S<NUM>a) when νC<NUM> > Vi/<NUM>.

Referring to <FIG>, in a practical control implementation, the control signals for the balancing switches of the balance booster circuit <NUM> can be derived from the pulse width modulation (PWM) control signals for the main switches of the FC circuit. The three-level FCC <NUM> can comprise a main control unit <NUM> configured to generate the PWM control signals pwmS2a and pwmS2b for operating switches S2a and S2b respectively. Additional control logic <NUM> can be provided to generate control signals pwmSB,a1 and pwmSB,b1 for operating balancing switches SB,a1 and SB,b1 respectively. The FCC as described herein can comprise voltage measurement devices <NUM>, <NUM> configured to sense the voltage across one or more of the DC-bus capacitors and/or across one or more of the flying capacitors as shown in <FIG> by the voltages vxy, vyz, vC1. The voltage measuring devices <NUM>, <NUM> can be coupled to the main control unit <NUM> and used to derive appropriate PWM control signals.

Due to the occurrence of an FC voltage lift described earlier above and/or of a voltage ripple of the FCs, due to a possibly large output current of the FCC and a relatively small FC capacitance value which is often selected to reduce costs and volume, it can be beneficial to select the discharge voltage level to be higher than Vi/<NUM> in order to avoid simultaneous charging and discharging (i.e. within a same switching period) of the FC which could result in unnecessary large currents in the circuit. In this case, SB,a<NUM> and SB,b1 are only enabled when νC<NUM> > (Vi/<NUM> + νB,offset). The offset voltage level νB,offset can be selected based on the occurring voltage ripple of the FC, the permissible currents in the circuit, and the desired voltages limits of the FC voltage νC<NUM>, e.g. the desired tolerance band around the reference value. Therefore, in a practical application, SB,a<NUM> can be driven by the same PWM signal as S2b (and SB,b<NUM> can be driven by the same PWM signal as S<NUM>a) in combination with an additional logic enable signal. The additional logic enable signal can be based on the comparison νC<NUM> > (Vi/<NUM> + νB,offset), i.e., the drive signals of SB,a<NUM> and SB,b<NUM> are disabled when this condition is not met. The offset voltage level can be selected zero or even negative, achieving tighter/better balancing at the cost of higher currents in the balancing circuit.

Additionally, it is provided that SB,a<NUM> (or SB,b<NUM>) turns on slightly later, and/or turns off slightly earlier, than defined by the PWM signal of S<NUM>b (or S<NUM>a) in order to avoid large current spikes and saturation of the balancing inductor which would be induced by the large voltage build-up during voltage commutation of S<NUM>b (or S<NUM>a) following its tum-on and turn-off. This can easily be implemented in control logic (software, or even analog hardware), for example using delayed tum-on possibly in combination with, or alternatively, an on-time limit ten,max for SB,a<NUM> and SB,b<NUM> that is smaller than the (minimum) on-time of the respective main semiconductor switch (S<NUM>b and S<NUM>a). A schematic representation of the control signals and control logic is represented in <FIG>, including voltage offset νB,offset and, in this particular case, a fixed on-time limit ten,max. It will be convenient to note that ten,max can also be variably controlled by the main controller <NUM>, for example based on the instantaneous duty-cycle of S<NUM>b and S<NUM>a.

Advantageously, the balancing semiconductor switches can additionally be operated when charging the FCs, for example by implementing synchronous switching with their anti-parallel diode. This reduces conduction losses, as is known in literature.

Advantageously, the active balance booster circuits of the present disclosure (Group II) comprise one or more freewheeling diodes to release the energy that is accumulated in the balancing inductor during the conduction state of the balancing switches (SB,a1 and SB,b1) at turn-off of the switch, avoiding over-voltage when turning off the switch while there is still a current flowing in the balancing inductor. For example, <FIG> shows the three-level FCC <NUM> with active non-dissipative charging/discharging balance booster <NUM> comprising only one balancing semiconductor switch SB,a<NUM> to discharge C<NUM> when its voltage is too high. Balance booster <NUM> further comprises a diode DB,b<NUM> which operates as a freewheeling diode and participates in the charging of C<NUM> when its voltage is too low, according to the operating principle described for the Group I balance boosters above. It will be convenient to note that the anode of diode DB,b<NUM> does not need to be connected to the negative terminal of C<NUM>, but can instead be connected to any other suitable voltage node, e.g. to terminal Z (negative DC rail). Alternatively, the (internal) anti-parallel diode of the active balancing switch can operate as the freewheeling diode, e.g. as in the balancing circuit <NUM> of <FIG>.

Referring to <FIG> the passive balancing circuit <NUM> of <FIG> can be converted into an active balancing circuit <NUM> by replacing the balancing diodes of circuit <NUM> with active balancing switches SB,a1, SB,b1, SB,a2 and SB,a2, enabling discharging of C<NUM>, C2a, and C2b in addition to the charging of these FC capacitors.

Referring to <FIG>, the passive balancing circuit <NUM> of <FIG> can be converted into an active balancing circuit <NUM> by replacing the balancing diodes of circuit <NUM> with active balancing switches SB,a1, SB,b1. Circuit <NUM> enables discharging of C<NUM>, C<NUM> in addition to the charging of these FC capacitors. Like circuit <NUM>, an additional inductor and active half bridge connected to terminal Y2 can be added to circuit <NUM>.

The voltage balancing circuits for both Group I and Group II advantageously allow a controlled pre-charge of the FCs when the DC-bus voltage is ramped up at turn-on of the converter. For example, referring to <FIG>, during ramp-up of the DC-bus voltage the following pre-charge scenarios for C<NUM> are possible:.

Alternatively, controlled pre-charge can be achieved in a similar way using balancing switch SB,b<NUM> (or its anti-parallel diode) and main semiconductor switch S<NUM>a, It is alternatively possible to alternate between the case where balancing switch SB,a<NUM> (or its anti-parallel diode) and main semiconductor switch S<NUM>b are used and the case where balancing switch SB,b<NUM> (or its anti-parallel diode) and main semiconductor switch S<NUM>a are used.

Controlled discharge of the FCs when the DC-bus voltage is ramped down at turn-off (intended turn-off or turn-off after an error) of the converter is also possible using the active balancing semiconductor switches of the Group II active non-dissipative charging/discharging balance boosters. For example, in <FIG>, during ramp-down of the DC-bus voltage the following discharge scenarios for C<NUM> are possible:.

Alternatively, controlled discharge can be achieved in a similar way using balancing switch SB,b<NUM> and main semiconductor switch S<NUM>a (or its anti-parallel diode). It is alternatively possible to alternate between the case where balancing switch SB,a<NUM> and main semiconductor switch S2b (or its anti-parallel diode) are used and the case where balancing switch SB,b<NUM> and main semiconductor switch S<NUM>a (or its anti-parallel diode) are used.

For the Group II active non-dissipative charging/discharging balance boosters, controlled discharge of C<NUM> during ramp-down of the DC-bus voltage at turn-off of the converter can also be obtained when the main semiconductor switches of the FCC bridge (e.g. half-bridges S<NUM>a,S<NUM>b and S<NUM>a,S<NUM>b in <FIG>) operate in a switching state where they generate an idle-state output voltage, for example <NUM> V. In this case, all main semiconductor switches are PWM modulated and the balancing circuit can maintain its regular operating mode as detailed in the above paragraphs.

In the presented examples, the balance booster circuits are connected to DC-bus terminals to or from which energy is transferred in order to balance the voltages of the FCs. When the net transferred energy over a longer period of time is non-zero, an increase or decrease of the DC-bus voltages can occur, i.e., particular DC-bus voltages of DC-bus capacitors of a series connection of DC-bus capacitors needed to create the DC-bus terminals. Since in a typical application the DC-bus capacitors have capacitances which are orders of magnitude larger (e.g. <NUM> times larger) than the FCs, this voltage increase/decrease is very small and therefore has quasi no influence on the normal operation of the FCC. Referring to <FIG>, the converters according to the present disclosure can comprise a power supply <NUM>, <NUM> for the three-level or four-level DC-bus <NUM> and <NUM> respectively. Power supply <NUM>, <NUM> can be equipped with a series connection of bidirectional DC/DC converters <NUM> or a multi-output-terminal DC/DC converter <NUM>, preferably isolated DC/DC converters. Power supply <NUM>, <NUM> can be configured to operate the DC/DC converters <NUM>, <NUM> to maintain voltage balance of the DC-bus capacitors by circulating energy between these capacitors. This energy circulation can occur at very low power levels since the FC balancing occurs at low levels of energy/power circulation. In case the DC/DC converters of the power supply are not bidirectional, discharge elements (e.g. a series connection of a resistor and controlled semiconductor switch) can be connected between DC-bus terminal pairs to discharge particular DC-bus capacitors when their voltage would become too high due to the FC balancing or small active balancing converters can be connected between DC-bus terminal pairs to circulate energy between DC-bus capacitors to balance their voltage, for example a Rain-Stick converter. The DC/DC converters <NUM>, <NUM> can be connected at their inputs with an AC/DC converter, which can receive power from a (three-phase) AC grid.

Even though the above examples all rely on the DC-bus capacitors as voltage source for charging the FCs, it will be convenient to note that the balance booster circuits can use a different voltage source instead. By way of example, the converter can comprise an additional DC/DC converter as voltage source and the balance booster circuits for charging the FCs can be configured to make a parallel connection between output terminals of the DC/DC converter and the FC whose voltage is to be balanced (charged).

Referring to <FIG>, the three-level flying capacitor converters <NUM>, <NUM> as described herein can be utilized as amplifiers <NUM> for driving a load <NUM>. Each amplifier <NUM> can comprise or consist of a stack of one or more flying capacitor converters as described herein. Multiple flying capacitor converters <NUM>, <NUM> can be arranged in parallel in the stack to obtain the amplifier <NUM>. The parallel connected flying capacitor converters can share a common DC-bus <NUM>, <NUM>. The output nodes v<NUM> of the flying capacitor converters are connected in parallel to obtain an output node <NUM> of the stack or amplifier <NUM>. The output node v<NUM> of the FC converter is connected to the load <NUM> through an optional L-C filter <NUM>. The (common) DC-bus of the FC converters can be connected to a power supply, such as the power supplies described herein in relation to <FIG>. By arranging two such FCC amplifiers <NUM> symmetrically with respect to load <NUM>, it is possible to apply an AC voltage vo,A - vo,B to load <NUM> utilizing DC/DC flying capacitor converters with DC output voltages vo,A and vo,B. A same arrangement can be obtained utilizing the four-level FCCs <NUM>, <NUM> as amplifiers <NUM>, as shown in <FIG>, or any higher level flying capacitor converters. The flying capacitor converters in each stack or amplifier <NUM>, <NUM> can be operated in parallel (simultaneous operation) or in an interleaved mode to provide an output v<NUM>,A or v<NUM>,B.

The FCCs can be part of a hybrid converter topology, such as a combined FC and neutral-point-clamped (NPC) converter structure. The FCCs with voltage balancing circuits as described herein can be used in MRI amplifiers, motor drive systems and in DC/DC converters for photo-voltaic applications.

In the following, simulation examples are provided that illustrate the operating principle and effectiveness of the Group I and Group II non-dissipative balance boosters. For each example, the output Lo-Co filter and the load terminals of the FCC are replaced by a controlled current source io connected between the switch-node terminal sn and the DC-bus midpoint which is referred to as ground GND. Also, the DC-bus capacitors are replaced by controlled voltage sources. Using these conditions, the FC balancing mechanisms can be clearly explained neglecting the effects of the in- and output filters on the waveforms. Furthermore, it shall be noted that the switch-node voltage νsn is the voltage between terminal sn and ground GND. For each example below, the voltage and current conventions for the semiconductor switches (here Metal-Oxide Field Effect Transistors; MOSFETs) and capacitors are as indicated in <FIG>.

The circuit used in simulation example <NUM> is shown in <FIG> and comprises a three-level FCC with flying capacitor C<NUM> = <NUM>µF and no voltage balancing circuit (balance booster) used. The purpose of simulation example <NUM> is to illustrate the imbalance problem in case no balance booster is used. The simulation is performed at the following conditions:.

The resulting waveforms are shown in <FIG>, where:.

In <FIG>, the ripple of the FC voltage νC<NUM> due to the current iC<NUM> (see <FIG>) flowing in capacitor C<NUM> is visible. Due to circuit imperfections and non-idealities, the average value of νC<NUM> is drifting away from its reference value VC<NUM>,ref(= Vi/<NUM>) as can be seen in <FIG> leading to a growing voltage imbalance which is also visible in the switch-node voltage waveform νsn of <FIG>. The result is that the harmonic components of νsn start to appear at the switching frequency fSW and multiples thereof, as can be seen in <FIG> (captured at time instant <NUM>). This is not desired since (i) it increases the required filtering effort and therewith limits the amplifier's bandwidth and (ii) it causes over-voltage of the main semiconductor switches. These are both effects that can become worse as FC voltage imbalance is not under control and can potentially become very large, potentially leading to destruction of the semiconductor switches due to over-voltage and making an FCC without a voltage balancing circuit practically unusable in many applications.

The circuit used in simulation example <NUM> is shown in <FIG> and comprises a three-level FCC and an active non-dissipative balance booster, with two balancing switches SB,a1 and SB,b<NUM> that include anti-parallel diodes. Flying capacitor C<NUM> = <NUM>µF.

The purpose of this simulation example <NUM> is to illustrate the discharging mechanism provided by the active balance boosters of the present disclosure by actively operating the balancing switches.

The simulation was performed at the following conditions:.

In this simulation example, only the discharging mechanism of the FC C<NUM> via the balancing switches SB,a<NUM> and SB,b<NUM> is illustrated and the control logic shown in <FIG> is utilized. The initial (i.e. at the start of the simulation) FC voltage νC<NUM>,init is set to the reference value added with an offset of +30V (νC<NUM>,init = VC<NUM>,ref + <NUM> V = Vi/<NUM> + <NUM> V = <NUM> V + <NUM> V = <NUM> V). Switching of SB,a<NUM> and SB,b<NUM> occurs synchronously with the main semiconductor switches S<NUM>b and S<NUM>a respectively, according to the control diagram of <FIG> selecting νB,offset = <NUM> V and ten,max = <NUM>. The inductance value of the balance inductor LB,<NUM> is <NUM>µH.

In <FIG>, the currents iSBa<NUM> and iSBb<NUM> in the balancing switches are visible which cause discharging of the FC C<NUM> as indicated in <FIG> where νC<NUM> is steadily reduced due to iSBa<NUM> and iSBb<NUM> causing a reduction of the average value of νC<NUM>. This is also clearly noticeable on a larger timescale in <FIG> where νC<NUM> converges towards its reference value VC<NUM>,ref. <FIG> and <FIG> show iSBa<NUM> and iSBb<NUM> on the larger timescale and are significantly low, which also can be seen in <FIG> and <FIG> where the contribution of iSBa<NUM> and iSBb<NUM> to the FC current iC<NUM> is very little. Therefore, one can conclude that the disclosed balancing circuit is capable of effectively balancing (i.e. in this particular example 'discharging') the voltage of the FC at low additional balancing currents and thus at low additional losses in the circuit and thus the additional balancing hardware can have low current ratings which provides a cost-effective solution and makes the FCC practically usable in many applications.

The same FCC circuit of simulation example <NUM> is used. In this example however, the two balancing switches SB,a1 and SB,b1 are disabled, and only diode operation of the balance booster is possible. The purpose of simulation example <NUM> is to illustrate the charging mechanism of the balance boosters of the present disclosure. The simulation was performed at the following conditions:.

In this simulation example, only the charging mechanism of the FC C<NUM> via the anti-parallel diodes of balancing switches SB,a<NUM> and SB,b<NUM> is illustrated by letting the DC-bus voltage (Vi = VCiXY + VCiYZ) rise from Vi(t = <NUM>) = <NUM> V to Vi(t = <NUM>) = <NUM> V and by disabling the PWM signals of SB,a<NUM> and SB,b<NUM> (resulting in diode operation of the balance booster). Conduction of the anti-parallel diodes of SB,a<NUM> and SB,b<NUM> occurs synchronously with the main semiconductor switches S2b and S2a respectively, according to the explanation of the charging mechanism of the passive non-dissipative charging balance boosters (Group I) above. In this example, the drive PWM signals (pwmSB,a<NUM>,pwmSB,b<NUM>) of SB,a<NUM> and SB,b<NUM> are thus disabled in the control diagram of <FIG>. The inductance value of the balance inductor LB,<NUM> is <NUM>µH. The resulting waveforms are shown in <FIG>, where:.

In <FIG>, the currents iSBa<NUM> and iSBb<NUM> in the anti-parallel diodes of SB,a<NUM> and SB,b<NUM> (remind that the PWM signals of SB,a<NUM> and SB,b<NUM> are disabled, resulting in diode operation only) are visible which cause charging of the FC C<NUM> as indicated in <FIG> where νC<NUM> is steadily increasing due to iSBa<NUM> and iSBb<NUM> causing an increase of the average value of vC<NUM>. This is also clearly noticeable on a larger timescale in <FIG> where νC<NUM> follows its reference value VC1,ref. <FIG> and <FIG> show iSBa<NUM> and iSBb<NUM> on the larger timescale and are significantly low, which also can be seen in <FIG> and <FIG> where the contribution of iSBa<NUM> and iSBb<NUM> to the FC current iC<NUM> is very little. Therefore, one can conclude that the disclosed balancing circuit is capable of effectively balancing (i.e. in this particular example 'charging') the voltage of the FC at low additional balancing currents and thus at low additional losses in the circuit and thus the current ratings of the additional balancing hardware can be low which provides a cost-effective solution and makes the FCC practically usable in many applications.

The purpose of simulation example <NUM> is to perform the same simulation as in comparative simulation example <NUM>, but now with the FCC including the balance booster circuit to prove its effectiveness.

The simulation was performed at identical conditions as comparative simulation example <NUM>. Switching of SB,a<NUM> and SB,b<NUM> occurs synchronously with the main semiconductor switches S2b and S2a respectively, according to the control diagram of <FIG> selecting νB,offset = <NUM> V and ten,max = <NUM>. The inductance value of the balance inductor LB,<NUM> is <NUM>µH.

In <FIG>, the currents iSBa<NUM> and iSBb<NUM> in the balancing switches are visible which cause the voltage νC<NUM> to follow its reference value VC<NUM>,ref as can be seen in <FIG> and in the enlarged view of <FIG>. Simultaneous charging and discharging (i.e. within a same switching period) of the FC occurs due to the relatively large ripple of voltage νC<NUM>, and due to a low offset voltage selection of νB,offset = <NUM> V (see control diagram of <FIG>) keeping voltage νC<NUM> tightly locked within a relatively narrow band around VC1,ref, resulting in a low value of the harmonic component of νsn at the switching frequency fSW as can be seen in <FIG>, i.e., the harmonic amplitude at fSW (<NUM>) is close to the value of the ideal case. <FIG> and <FIG> show iSBa<NUM> and iSBb<NUM> on the larger time-scale and are significantly low, which also can be seen in <FIG> where the contribution of iSBa<NUM> and iSBb<NUM> to the FC current iC<NUM> is very little. Therefore, one can conclude that the disclosed balancing circuit is capable of effectively balancing the voltage of the FC (i.e. within a relatively narrow band around VC<NUM>,ref) at low additional balancing currents and thus at low additional losses in the circuit and thus the current ratings of the additional balancing hardware can be low which provides a cost-effective solution and makes the FCC practically usable in many applications.

By comparing <FIG> and <FIG> showing the DC component (i.e. 800V) and amplitude of the harmonic components of the switch-node voltage νsn for comparative simulation example <NUM> and simulation example <NUM>, respectively, at simulation time <NUM>, it can be concluded that the voltage balancing circuits of the present disclosure are capable of obtaining a harmonic component of νsn at the switching frequency fSW (<NUM>) with very low harmonic amplitude, and almost five times smaller than the amplitude of the harmonic component at the switching frequency fSW for comparative simulation example <NUM>.

The circuit used in simulation example <NUM> is shown in <FIG> and comprises a four-level FCC. FC C<NUM> = <NUM>µF. FC C<NUM> = <NUM>µF. The FCC comprises an active non-dissipative balance booster according to aspects of the present disclosure, comprising four balancing switches that include anti-parallel diodes. The switching frequency of the main semiconductor switches of the FCC fSW = <NUM>. To keep C<NUM> balanced, switching of SB,a<NUM> and SB,b<NUM> occurred synchronously with the main semiconductor switches S<NUM>a, S<NUM>b, S<NUM>a, S<NUM>b according to the control diagram of <FIG> selecting νB,offset = <NUM> V and ten,max = <NUM>. To keep C<NUM> balanced, switching of SB,a2 and SB,b2 occurred synchronously with the main semiconductor switches S<NUM>a, S<NUM>b according to the control diagram of <FIG> selecting νB,offset = <NUM> V and ten,max = <NUM>. The inductance value of the balance inductors LB,a<NUM> and LB,b<NUM> is <NUM>µH.

The purpose of this simulation example was to illustrate the effectiveness of the balance booster circuits of the present disclosure for the following rather general and challenging operating conditions, which are graphically shown in <FIG>:.

A purpose of this simulation example was to show that the disclosed balance booster circuits are capable of operating under widely varying duty-cycles and fast changing DC-bus voltages, which do require the FC voltages to follow this change in order to maintain voltage balance in the FCC. The resulting waveforms are shown in <FIG>, where:.

Claim 1:
Electrical converter (<NUM>), comprising:
two first nodes (X, Z) and a switch node (sn),
a flying capacitor circuit comprising at least one flying capacitor (C<NUM>, C<NUM>) and a plurality of first switching devices (S1a, S1b, S2a, S2b, S3a, S3b) operable to convert between a first signal at the first nodes and a second signal at the switch node,
a balancing circuit (<NUM>, <NUM>, <NUM>, <NUM>) for balancing a voltage of the at least one flying capacitor, and a plurality of DC-bus voltage sources (CiXY, CiYZ, CiXY1, CiY1Y2, CiY2Z) connected in series between the two first nodes (X, Z),
wherein the balancing circuit comprises an inductor (LB,<NUM>) and at least one second switching device (DB,a1, DB,a2, DB,b1, DB,b2, SB,a1, SB,a2, SB,b1, SB,b2) connected to a terminal of the at least one flying capacitor, wherein the at least one second switching device comprises an actively operated switching device (SB,a1, SB,a2, SB,b1, SB,b2) configured to connect the at least one flying capacitor in parallel with a DC-bus voltage source (CiXY, CiYZ, CiXY1, CiY1Y2, CiY2Z) or in parallel with another capacitor of the at least one flying capacitor for discharging the at least one flying capacitor, wherein the inductor and the at least one flying capacitor are connected in series when the at least one switching device is configured to connect the at least one flying capacitor in parallel with the voltage source or the another capacitor, and wherein the inductor (LB,<NUM>) is connected to an intermediate node (Y, Y1, Y2) between the plurality of series connected DC-bus voltage sources,
characterised in that the electrical converter comprises a control unit (<NUM>) configured to implement time differentiation logic in order to operate the actively operated switching device (SB,a1, SB,a2, SB,b1, SB,b2) to discharge the at least one flying capacitor with a time delay compared to synchronous operation with a respective one of the plurality of first switching devices (S1a, S1b, S2a, S2b, S3a, S3b), wherein the time delay is configured to:
delay turn on of the actively operated switching device with respect to a turn-on instant of the respective one of the plurality of first switching devices (S1a, S1b, S2a, S2b, S3a, S3b), and/or
reduce an on-time of the actively operated switching device (SB,a1, SB,a2, SB,b1, SB,b2) compared to an on-time of the respective one of the plurality of first switching devices (S1a, S1b, S2a, S2b, S3a, S3b).