Patent Description:
The present disclosure relates to electronic transistors and to methods of forming electronic transistors.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is vastly used in electronics and computing industry. Complementary Metal Oxide Semiconductor (CMOS) is a type of MOSFET that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions.

CMOS is used for construing integrated circuits comprising processors, microprocessors, microcontrollers, memory chips (e.g., CMOS BIOS), and other digital logic circuits. These integrated circuits based on CMOS technology are vastly used in computing electronics. As downscaling the size (in nm) of the CMOS transistors, computing performance is improved.

In addition, current computing performance is based on Von Neumann architecture and uses discrete information processing approaches and/or hierarchical storage. It is ideal for solving complex computational problems but limits computational performance efficiency due to Von Neumann bottleneck.

To that end, neuromorphic computing has been developed to realize human brain functionality as an alternative to the Von Neumann approach. This approach offers massively parallel and distributed computation that combines processing and memory with a very low power consumption.

As reaching CMOS scaling limits, other computing devices and technologies need to be developed to overcome CMOS low voltage, low power, and high-performance limitations.

As a result, Electrolyte-gated transistors (EGTs) have been developed. Electrolyte gating offers significant advantages for the realization of neuromorphic devices/architectures, including ultralow-voltage operation and the ability to form parallel-interconnected networks.

In addition, three-terminal devices have been developed that use an electrolyte gated transistor to control the resistance and/or conductance of a channel via injection or extraction of ions (e.g., H+, Ag+, Li+, Cu<NUM>+, O<NUM>-) that is triggered by a voltage applied at the gate electrode where the electrolyte (e.g., solid or liquid), contacting the gate with the channel, conducts ions. By modifying the resistance and/or the conductance of the channel that contacts a drain electrode with a source electrode, a switch may be obtained. However, the switching of these devices may be slow and/or lacking reversible multilevel switching.

Nevertheless, EGTs and/or three terminal devices that uses EGTs are difficult to integrate with solid-state devices (e.g., CMOS-based devices). EGTs and/or three terminal devices are temperature sensitive and/or unstable under humidity. In the case of Li-ion conductors, reported materials present a poor stability in ambient atmosphere and self-discharge issues hinder their real implementation in EGTs. In the case of EGTs based on oxygen conductors, the lack of room and/or low-temperature of oxideionic conductors forces an operation at non-viable elevated temperature (e.g., above <NUM>).

In addition, these devices have poor/no compatibility with mainstream microelectronics fabrication processes (e.g., CMOS fabrication processes). CMOS fabrication processes permits scalability and well-known fabrication methods. Therefore, a need for EGTs that are compatible with CMOS fabrication process is needed.

<CIT> relates to a programmable-resistance memory cell, a method of fabrication and a non-volatile memory device incorporating such a memory cell.

<CIT>, <CIT>, <CIT>, and <NPL>" relate to devices with an electrolyte.

Examples of the present disclosure seek to at least partially reduce one or more of the aforementioned problems.

According to a first aspect, an electronic transistor is provided. The transistor may comprise a body. The body may comprise at least an electrolyte structure; a channel provided in contact with the electrolyte structure; a gate provided in contact with the electrolyte structure. The transistor may comprise at least three contact elements configured to be connected to an external circuit. At least one of the contact elements, referenced as Gate contact element, may be separated from the electrolyte structure by means of the gate. The other contact elements, referenced as Source contact element and Drain contact element, may be interconnected by means of the channel and may be separated from the electrolyte structure also by means of the channel. The electrolyte structure may comprise an oxygen ion conducting electrolyte structure. The oxygen ion conducting electrolyte structure may comprise a BiMEVOX structure, where Bi is Bismuth, ME is a Metal, V is Vanadium and OX is an oxide.

The BiMEVOX structure used as an electrolyte structure provides some advantages to the electronic transistor, such as stability (BiMEVOX structure, as an oxide structure, can be used to expand the redox potential window and thereby widen the gate voltage range due to the excellent stability under large dc bias application), no dependency from external conditions (e.g., humidity, etc.) because oxide ions migrate via a vacancy mechanism or an interstitial mechanism, both of which are a bulk conduction mechanism needing no surface absorption; enhancement of manufacturing compatibility (compatible with mainstream microelectronic technology) or its performance at low temperatures (e.g. operation temperature at room temperature). This way, the BiMEVOX structure provides the benefits of oxides, while enables room temperature operation.

This last feature opens the door to a full new range of applications in microelectronic sector, such as neuromorphic computing and stochastic computing. In this electronic transistor, a gate bias is applied through the room temperature-electrolyte (BiMEVOX structure) to change the oxygen stoichiometry of the channel by pumping oxygen ions across. In such a way, the gate voltage "programmes" the conductance of the channel that, in the absence of gate bias, remains unaltered for very long times (~years) giving rise to a non-volatile multistate transistor. Moreover, the electronic transistor is compatible with microfabrication technologies.

In summary, the main distinctive features of said electronic transistors compared to existing EGTs are:.

In some examples, the BiMEVOX structure may be configured to work in a temperature between <NUM> and <NUM>, for example, at room temperature.

In some examples, the metal ME may be selected from at least one of the following:.

For example, the BiCuVOX may be proposed due to its performance at low temperatures (i.e. between <NUM> and <NUM>).

In examples, the stoichiometry of the BiMEVOX structure is Bi<NUM>V<NUM>-xMExO<NUM>-δ,
where <NUM><x<<NUM> and <NUM><δ<<NUM>, for example, Bi<NUM>V<NUM>Cu<NUM>O<NUM>.

In some examples, the thickness of the BiMEVOX structure may be between <NUM> and <NUM>.

According to some examples, the channel may comprise a Mixed Ionic and Electronic Conductor (MIEC) oxide configured to vary its oxygen content, which supposes a consequent variation in its electronic conductivity.

In some examples, the gate may comprise a Mixed Ionic and Electronic Conductor (MIEC) oxide configured to vary its oxygen content, which supposes a consequent variation in its electronic conductivity.

In both cases, the Mixed Ionic and Electronic Conductor (MIEC) oxide may be selected from at least one of the following:.

In examples, the fluorite oxide may comprise Rare earth (Re) doped Ceria such as Ce<NUM>-xRexO<NUM>-δ, Re being selected from at least one of the following: Sm, Gd, Y, Pr, La.

In some examples, the Perovskites oxide may comprise La<NUM>-xSr<NUM>-xTmO<NUM>-δ, the Transition metal (Tm) being selected from at least one of the following: Ti, V, Cr, Mn, Fe, Co, Cu, Ni, and <NUM><x<<NUM>, for example, the Perovskites oxide may comprise a MIEC La<NUM>Sr<NUM>FeO<NUM>-δ (LSF), where <NUM><δ<<NUM>.

According to some examples, the Perovskite-derived structure may comprise a Ruddlesden-Popper phase La<NUM>-xSrxTmO<NUM>+δ, Tm being a Transition metal selected from at least one of the following: Mn, Cu, Ni, and <NUM><x<<NUM>.

In examples, the thickness of the channel is between <NUM> and <NUM>.

In examples, the thickness of the gate is between <NUM> and <NUM>.

In some examples, the material of each of the at least three contact elements may be selected from at least one of the following:.

The material of the contact elements may be of high electrical conductivity, for example, with conductivity greater than <NUM><NUM> S/cm.

In examples, the metal material may be selected from at least one of the following: Gold (Au); Nickel (Ni); Copper (Cu); Platinum (Pt); Palladium (Pd); any combination thereof.

According to some examples, the thickness of any of the at least three contact elements may be between <NUM> and <NUM>.

In some examples, the transistor may further comprise a seed between the Gate contact element and the gate and/or between at least one of the Source and the Drain contact elements, and the channel. The seed may be required to improve the adherence between a contact element and the channel. The seed may be the same or similar size of the contact element, occupying only the surface of the contact element.

According to another aspect, a method of forming an electronic transistor is provided. The method may comprise:.

It is important to note that the disclosed steps of the method may be executed in any suitable order to form an electronic transistor.

In some examples, depositing the channel and depositing the gate may comprise depositing the channel and the gate onto the same side of the deposited electrolyte structure, the channel and the gate being in contact with the electrolyte structure. This way, an in-plane configuration of an electronic transistor is obtained.

In some examples, depositing the electrolyte structure may comprise depositing the electrolyte structure onto the side of the deposited channel that is opposed to the side of the deposited channel in which the first contact element and the second contact element are formed, the channel being in contact with the electrolyte layer. In addition, depositing the gate onto the electrolyte structure may comprise depositing the gate onto the side of the electrolyte structure that is opposed to the side in which the electrolyte structure is in contact with the channel, the gate being in contact with the electrolyte structure. In this case, an out-of-plane configuration of an electronic transistor is obtained.

In some examples, the method may further comprise depositing a seed onto the channel before forming the first contact element and/or the second contact element, the seed being between the channel and the first contact element and/or the channel and the second contact element. One of the first and second contact elements or both of them may comprise the seed. The seed may be required to improve the adherence between a contact element and the channel. The seed may be the same or similar size of the contact element, occupying only the surface of the contact element.

In examples, the method may further comprise depositing a seed onto the gate before forming the third contact element, the seed being between the gate and the third contact element. The seed improve the adherence between the third contact element and the gate. The seed may be the same or similar size of the third contact element, occupying only the surface of the third contact element.

This way, an in-plane configuration of an electronic transistor is obtained.

According to yet another aspect, a method of forming an electronic transistor is provided. The method may comprise:.

This way, an out-of-plane configuration of an electronic transistor is obtained.

The term "structure" may be understood as a spatial pattern along <NUM> different directions (i.e. x, y, z) of a three-dimensional space which may be any suitable spatial arrangement such as, for example, a layer, a wafer, a cube, a cone, a cylinder, a disk, an hexagonal prism, a triangular prism, a pentagonal prism, a tetrahedron, an octahedron, a sphere and any combinations thereof.

The term "external medium" may be used to refer to the surroundings of the electronic transistor, e.g., the external environment and the external environment conditions.

The external environment conditions may comprise gas partial pressures (e.g., oxygen partial pressure); humidity conditions; and temperature.

The term "oxygen" may be used to refer to any allotrope of oxygen, e.g., O<NUM>, O<NUM>, O<NUM>.

Thus, the term "oxygen ions" may be used to refer to any ion of any allotrope of oxygen, e.g., O-, O<NUM>-.

In these figures the same reference signs have been used to designate matching elements.

<FIG> respectively show an example of an electronic transistor in an in-plane (<FIG>) and out-of-plane (<FIG>) configuration according to the present disclosure.

The electronic transistor <NUM> is a three-terminal device which may be an electrolyte-gated transistor (EGT). Electrolyte-gated transistors may offer significant advantages for the realization of neuromorphic devices/architectures, including ultralow-voltage operation and the ability to form parallel-interconnected networks.

An electronic transistor may be configured as a switch (i.e., switching operations comprising two different states that can be switched) or as an amplifier (i.e., when an input signal is amplified by the electronic transistor and an amplified output signal is obtained).

In <FIG>, the top side of an electrolyte structure <NUM> may contact a channel <NUM> at one end <NUM> of the electrolyte structure <NUM>. Similarly, in <FIG> the bottom side of an electrolyte structure <NUM> may contact a channel <NUM>.

In <FIG>, the electrolyte structure <NUM> is an oxygen ion conducting electrolyte structure. The oxygen ion conducting electrolyte structure may be solid or liquid. In this example, the electrolyte structure <NUM> is a solid oxygen ion conducting electrolyte structure and may have a thickness comprised between <NUM> and <NUM>, specifically the thickness of the ion conducting electrolyte structure may be between <NUM> and <NUM>.

In some examples, the electrolyte structure <NUM> may comprise a BiMeVOX structure, where Bi is Bismuth, Me is a metal, V is Vanadium and OX is an oxide. It is noted that the BiMeVOX structure is a solid ion conducting electrolyte structure.

The BiMeVOX structure has a layered aurivillius structure which comprises alternating [Bi<NUM>O<NUM>]<NUM>+ and transition metal-doped perovskite [VO]<NUM>- layers. The BiMeVOX structure may be used for ion (e.g., O<NUM>-) transport from an ion donor structure (i.e., a structure which may donate ions) to an ion receiver structure (i.e., a structure which may accept ions). Increasing disordered oxygen vacancies in the perovskite [VO]<NUM>- layers may improve ion (e.g., O<NUM>-) mobility. In addition, ion (e.g., O<NUM>-) mobility may be maximized when the tetragonal γ-phase of the BiMeVOX structure is stabilized. Tetragonal γ-phase may be achieved at working temperatures above i.e., <NUM>. Therefore, an ion conducting electrolyte structure with improved ion (e.g., O<NUM>-) conductivity may be obtained.

In addition, the tetragonal γ-phase of the BiMeVOX structure may be stabilized at lower working temperatures (i.e., below <NUM>) by doping the vanadium with different metals (i.e., by cationic substitutions in vanadium positions). Therefore, the BiMeVOX structure may work in a temperature between <NUM> and <NUM>, and more specifically at room temperature (i.e., <NUM> - <NUM>).

The metal Me of the BiMeVOX structure may be selected from at least one of the following metals: copper (forming a BiCuVOX structure); cobalt (forming a BiCoVOX structure); nickel (forming a BiNiVOX structure); or magnesium (forming a BiMgVOX structure). Other metals may be used.

In addition, the stoichiometry of the BiMeVOX structure is Bi<NUM>V<NUM>-xMxO<NUM>-δ where x is comprised between <NUM> < x< <NUM> and/or δ is comprised between <NUM> < δ < <NUM>.

Specifically, as an example, the stoichiometry of the BiMeVOX structure may be Bi<NUM>V<NUM>Cu<NUM>O<NUM>.

In some examples, the electrolyte structure <NUM> may be deposited via conventional synthesis and deposition methods such as physical vapor deposition (PVD), for example, cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition; thermal evaporation; electron-beam evaporation; sputtering, for example, diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering; ion-assisted deposition; chemical vapor deposition (CVD); sol-gel coatings; or atomic layer deposition (ALD).

Particularly, the electrolyte structure <NUM> may be deposited via pulsed laser deposition.

In this example (i.e., pulsed laser deposition), the electrolyte structure <NUM> may be deposited onto a substrate, for example, silicon, strontium titanate crystal SrTiO<NUM>, polymers, metals, or ceramics. Alternatively, the substrate may comprise a strontium titanate crystal (SrTiO<NUM>) layer with an underlying silicon layer. In addition, the substrate may be a substantially flat substrate and/or compatible with microelectronic fabrication. The thickness of the substrate may be between <NUM> and <NUM>, specifically the thickness of the substrate may be between <NUM> and <NUM>.

In addition, a BiMeVOX structure such as Bi<NUM>V<NUM>-xMxO<NUM>-δ (where x is comprised between <NUM> < x< <NUM> and/or δ is comprised between <NUM> < δ < <NUM>), specifically a BiMeVOX structure such as Bi<NUM>V<NUM>Cu<NUM>O<NUM>, may be grown epitaxially on (<NUM>) oriented substrates.

On the one hand, the BiMeVOX structure may present an anisotropy in oxygen ion conduction. The BiMeVOX structure may provide a first oxygen ion conduction along the in-plane principal axis [<NUM>] and [<NUM>].

On the other hand, the BiMeVOX structure along [<NUM>] axis may provide a second oxygen ion conduction which is orders of magnitude lower than the first oxygen ion conduction. As a result, the conductivity of oxygen ions along [<NUM>] axis is lower than the conductivity of oxygen ions along the in-plane principal axis [<NUM>] and [<NUM>].

Therefore, the deposition of (<NUM>) oriented BiMeVOX structures may allow to promote oxygen vacancy migration and / or oxygen ion conduction from the channel <NUM> to a gate <NUM>; and / or from the gate <NUM> to the channel <NUM>.

Furthermore, the substrates may be selected in function of their lattice parameters to match the lattice parameter of the BiMeVOX structure, which may allow an epitaxial growth of the BiMeVOX structure. Consequently, BiMeVOX structures may be grown epitaxially onto a substrate via pulsed laser deposition with a deposition pressure which may be between <NUM> mbar and <NUM> mbar, specifically the deposition pressure may be <NUM> mbar.

Consequently, ion conducting electrolyte structures, which may be stable at temperatures between <NUM> and <NUM>, and more specifically at room temperature (i.e. <NUM> - <NUM>), may be obtained. In addition, the ion conducting electrolyte structures may be compatible with CMOS fabrication processes.

As aforementioned before, the electrolyte structure <NUM> may contact the channel <NUM>. The channel <NUM> may comprise a Mixed Ionic and Electronic Conductor (MIEC) oxide layer. MIECs layers may be selected from at least one of the following: fluorite oxides, for example, Rare earth (Re) doped Ceria Ce<NUM>-xRexO<NUM>-δ with rare earth (Re) such as samarium (Sm), gadolinium (Gd), yttrium (Y), praseodymium (Pr), lanthanum (La); perovskites oxides La<NUM>-xSr<NUM>-xTmO<NUM>-δ with Tm transition metal such as titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), copper (Cu), nickel (Ni) where x may be comprised between <NUM> < x< <NUM>; or perovskite-derived structures such as Ruddlesden - Popper phase, for example, La<NUM>-xSrxTmO<NUM>+δ with Tm transition metal such as manganese (Mn), copper (Cu), nickel (Ni) where x may be comprised between <NUM> < x< <NUM>. Specifically, the channel <NUM> may be a perovskite oxide with the stoichiometry La<NUM>Sr<NUM>FeO<NUM>-δ (LSF), where δ may be comprised between <NUM> < δ < <NUM>. Alternatively, MIECs layers may have an ABO<NUM> structure.

In addition, the channel <NUM> may have a thickness comprised between <NUM> and <NUM>, specifically the thickness of the channel <NUM> may be between <NUM> and <NUM>.

In some examples, the channel <NUM> may be deposited via conventional synthesis and deposition methods such as physical vapor deposition (PVD) e.g. cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition; thermal evaporation; electron-beam evaporation; sputtering, for example, diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering; ion-assisted deposition; chemical vapor deposition (CVD); sol-gel coatings; or atomic layer deposition (ALD).

As will be described later on <FIG>, the oxygen content of the channel <NUM> may be varied, thereby decreasing or increasing the electronic conductivity of the channel such as the channel may be an insulator or a conductor depending on its oxygen content. Therefore, the channel <NUM> may be an ion donor structure (i.e., a structure which may donate ions) or an ion receiver structure (i.e., a structure which may accept ions).

Following the example, in <FIG>, the top side of the electrolyte structure <NUM> may contact the gate <NUM> at a second end <NUM> of the electrolyte structure <NUM>. Similarly, in <FIG>, the top side of the electrolyte structure <NUM> may contact the gate <NUM>. The gate <NUM> may comprise a Mixed Ionic and Electronic Conductor (MIEC) oxide layer. MIECs layers may be selected from at least one of the following: fluorite oxides, for example, Rare earth (Re) doped Ceria Ce<NUM>-xRexO<NUM>-δ with rare earth (Re) such as samarium (Sm), gadolinium (Gd), yttrium (Y), praseodymium (Pr), lanthanum (La); perovskites oxides La<NUM>-xSr<NUM>-xTmO<NUM>-δ with Tm transition metal such as titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), copper (Cu), nickel (Ni) where x may be comprised between <NUM> < x< <NUM>; or perovskite-derived structures such as Ruddlesden - Popper phase, for example, La<NUM>-xSrxTmO<NUM>+δ with Tm transition metal such as manganese (Mn), copper (Cu), nickel (Ni) where x may be comprised between <NUM> < x< <NUM>. Specifically, the gate <NUM> may be a perovskite oxide La<NUM>-xSr<NUM>-xTmO<NUM>-δ with the stoichiometry La<NUM>Sr<NUM>FeO<NUM>-δ (LSF), where δ may be comprised between <NUM> < δ < <NUM>. Alternatively, MIECs layers may have an ABO<NUM> structure.

In addition, the gate <NUM> may have a thickness comprised between <NUM> and <NUM>, specifically the thickness of the gate <NUM> may be between <NUM> and <NUM>.

In some examples, the gate <NUM> may be deposited via conventional synthesis and deposition methods such as physical vapor deposition (PVD), for example, cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition; thermal evaporation; electron-beam evaporation; sputtering e.g. diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering; ion-assisted deposition; chemical vapor deposition (CVD); sol-gel coatings; or atomic layer deposition (ALD).

As will be described later on <FIG>, the oxygen content of the gate <NUM> may be varied, thereby decreasing or increasing the electronic conductivity of the channel such as the channel may be an insulator or a conductor depending on its oxygen content. Therefore, the gate <NUM> may be an ion donor structure (i.e., a structure which may donate ions) or an ion receiver structure (i.e., a structure which may accept ions).

In summary, the electronic transistor <NUM> illustrated in <FIG> and/or <FIG> is a three-terminal device which may be an electrolyte-gated transistor (EGT) and may include a body <NUM> comprising the electrolyte structure <NUM>, the channel <NUM> and the gate <NUM>. In addition, depending on the orientation and/or position of the channel <NUM> and the gate <NUM> with respect to the electrolyte structure <NUM>, two different configurations of the electronic transistor <NUM> may be obtained.

Therefore, <FIG> may represent an in-plane configuration of the electronic transistor <NUM>. In this example (i.e., <FIG>), the transport of ions (e.g., O<NUM>-) may be pumped or transported across the electrolyte structure <NUM> where the channel <NUM> and the gate <NUM> may be at the same side (e.g., both on the top, or both on the bottom) of the electrolyte structure <NUM>. Alternatively, <FIG> may represent an out-of-plane configuration of the electronic transistor <NUM>. In this example (i.e., <FIG>), the transport of ions (e.g., O<NUM>-) may be pumped or transported across the electrolyte structure <NUM> where the channel <NUM> and the gate <NUM> may be at opposite sides (e.g., on the top and on the bottom) of the electrolyte structure <NUM>.

Again in <FIG>, the electronic transistor <NUM> may further comprise three contact elements. A Gate contact element <NUM> may be on the top of the electrolyte structure <NUM>. Therefore, the gate contact element <NUM> may be separated from the electrolyte structure <NUM> by means of the gate <NUM>. Similarly, a Source contact element <NUM> and a Drain contact element <NUM> may be on the opposite ends of the channel <NUM>. Therefore, the source contact element <NUM> and the drain contact element <NUM> may be separated from the electrolyte structure <NUM> by means of the channel <NUM>.

In some examples, a seed may be provided between the gate <NUM> and the gate contact element <NUM>; and/or between the channel <NUM> and the source contact element <NUM>; and/or between the channel <NUM> and the drain contact element <NUM>. The seed may improve the adhesion of the contact elements (i.e., the gate contact element <NUM>, the source contact element <NUM> and the drain contact element <NUM>).

It is noted that adhesion may refer to the molecular attraction that holds the surfaces of two dissimilar substances together.

The seed may be of a material suitable to improve the adhesion of the contact elements such as metals, for example, copper (Cu), gold (Au), palladium (Pd), or any combination thereof.

The contact elements (i.e., the gate contact element <NUM>, the source contact element <NUM> and the drain contact element <NUM>) may be of a material suitable for conducting electric charges (e.g., a material with an electrical conductivity above <NUM><NUM> S/cm) such as metals, for example, platinum (Pt), gold (Au), nickel (Ni), copper (Cu), palladium (Pd), or any combination thereof; electrically conductive polymers; or electrically conductive ceramics.

In addition, the contact elements may have a thickness comprised between <NUM> and <NUM>. More specifically, the thickness of the contact elements may be between <NUM> and <NUM>. The same thickness for all contact elements is not required.

The contact elements and/or the seed may be deposited via conventional synthesis and deposition methods such as physical vapor deposition PVD (e.g. cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition); thermal evaporation; electron-beam evaporation; sputtering (e.g. diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering); ion-assisted deposition; chemical vapor deposition CVD; sol-gel coatings; or atomic layer deposition ALD.

In addition, the source contact element <NUM> and the drain contact element <NUM> may establish electrical contact with channel <NUM>. Similarly, the gate contact element <NUM> may establish electrical contact with the gate <NUM>.

In some examples, a capping layer may be configured to be onto the channel <NUM> and / or the gate <NUM>.

In some of these examples, the capping layer may be configured to be additionally onto the electrolyte structure <NUM>, and / or the gate contact element <NUM>; and / or the source contact element <NUM>; and / or the drain contact element <NUM>.

In these examples, the capping layer may be of a material suitable for insulating oxygen ions, e.g., alumina Al<NUM>O<NUM> or magnesium oxide MgO. As a result, the capping layer may prevent leakage of oxygen ions from the electronic transistor <NUM> (e.g., from the channel <NUM>, from the gate <NUM>) to an external medium; and / or inclusion of oxygen from the external medium to the electronic transistor <NUM> (e.g., to the channel <NUM>, to the gate <NUM>).

In addition, the capping layer may comprise a thickness between <NUM> and <NUM>, specifically between <NUM> and <NUM>.

The capping layer may be deposited via conventional synthesis and deposition methods such as physical vapor deposition PVD (e.g. cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition); thermal evaporation; electron-beam evaporation; sputtering (e.g. diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering); ion-assisted deposition; chemical vapor deposition CVD; sol-gel coatings; or atomic layer deposition ALD.

In some examples, the capping layer may be deposited via atomic layer deposition ALD comprising a deposition chamber. In these examples, an aluminum precursor (e.g., metal alkyl trimethylaluminium TMA) may be chosen for alumina Al<NUM>O<NUM> deposition. Each ALD cycle may comprise:.

ALD cycles may be repeated to obtain a capping layer thickness of between <NUM> and <NUM>, specifically between <NUM> and <NUM>; and more specifically <NUM>. During the ALD cycles, the deposition chamber may be kept at <NUM>.

<FIG> illustrates a flow chart for operating switching operations of the electronic transistor. In <FIG>, the operation of the electronic transistor <NUM> is described. In this example, switching operations may be performed between two different states that can be switched.

At block <NUM>, a write voltage pulse may be applied at the gate contact element <NUM> through an external electrical circuit. As hereinbefore described in <FIG>, the gate <NUM> may contact the electrolyte structure <NUM>. Therefore, when a write voltage pulse is applied at the gate contact element <NUM>, the electrolyte structure <NUM> contacting the gate <NUM> that is in electrical contact with the gate contact element <NUM>, may transport and/or pump ions (e.g., O<NUM>-) from an ion donor structure (i.e., a structure which may donate ions) to an ion receiver structure (i.e., a structure which may accept ions).

When a positive write voltage pulse is applied at the gate contact element <NUM>, ions (e.g., O<NUM>-) may be transported across the electrolyte structure <NUM> from the gate <NUM> (i.e., the ion donor structure) to the channel <NUM> (i.e., the ion receiver structure). By injecting ions (e.g., O<NUM>-) to the channel <NUM>, the oxygen content of the channel <NUM> may be varied (i.e., increased). It is noted that the oxygen content of the channel <NUM> may vary the conductance of the channel <NUM> due to the ion gating effect. Consequently, the electrical conductivity of the channel may be inherently varied because of the variation of the conductance of the channel. Thereby, the electrical conductivity of the channel may be changed such as the channel <NUM> may be switched from an insulator state to a conductor state.

A negative write voltage pulse may serve to return the channel to its as-fabricated, insulator state, thereby permitting writing and re-writing operations to be performed. When a negative write voltage pulse is applied at the gate contact element <NUM>, ions (e.g., O<NUM>-) may be transported across the electrolyte structure <NUM> from the channel <NUM> (i.e., the donor ion structure) to the gate <NUM> (i.e., the receiver ion structure). Therefore, ions (e.g., O<NUM>-) may be extracted from the channel <NUM> to the gate <NUM>. Consequently, the oxygen content of the channel <NUM> may be varied (i.e., decreased). Thereby, the electrical conductivity of the channel may be changed such as the channel <NUM> may be switched from a conductor state to an insulator state. Thus, applying a negative write voltage pulse may restore the conductance of the channel <NUM> to its original state (prior to application of the positive write voltage pulse).

Additionally, depending on the voltage applied at the gate (i.e. the write voltage pulse), a plurality of intermediate channel states may be obtained between a first channel state where the conductance of the channel may correspond to an insulator state and a second channel state where the conductance of the channel may correspond to a conductor state. The conductance of the channel of each channel state of the plurality of intermediate channel states may be comprised between the conductance of the channel of the first channel state and the conductance of the channel of the second channel state. Therefore, a multilevel switching may be obtained between e.g. the first channel state and each channel state of the plurality of intermediate channel states; and/or between each channel state of the plurality of intermediate channel states and the second channel state. Consequently, the electronic transistor <NUM> may comprise a plurality of states (e.g. corresponding to the first channel state, the plurality of intermediate channel states, and/or the second channel state). Hence, the electronic transistor <NUM> may correspond to a plurality of CMOS transistors that may have only one state.

Consequently, an electronic transistor <NUM> configured to perform reversible and non-volatile write operations may be operated by applying a write voltage pulse (e.g. positive or negative) at the gate contact element <NUM>.

At block <NUM>, a read operation may be performed by the electronic transistor <NUM>. The conductance of the channel may be read between the source contact element <NUM> and the drain contact element <NUM>. Conductance switching may occur as ions (e.g., O<NUM>-) are reversibly injected or extracted in and out of the channel <NUM> when a write voltage pulse is applied at the gate contact element <NUM>.

<FIG> illustrates a flow chart of a method for forming an electronic transistor <NUM>.

At block <NUM>, a channel may be deposited via conventional synthesis and deposition methods.

At block <NUM>, a first contact element (i.e., source contact element) and a second contact element (i.e., drain contact element) may be deposited on the opposite ends of the channel via conventional synthesis and deposition methods.

At block <NUM>, an electrolyte structure may be deposited on the side of the channel that is opposed to the side of the channel in which the first contact element and the second contact element are formed (e.g., the electrolyte structure may be on the bottom side of the channel whereas the first contact element and the second contact element may be on the top side of the channel) via conventional synthesis and deposition methods.

At block <NUM>, a gate may be deposited on the electrolyte structure via conventional synthesis and deposition methods.

In some examples, the gate may be deposited on the side of the electrolyte structure that is opposed to the side of the electrolyte structure in which the channel is deposited (e.g., the gate may be on the bottom side of the electrolyte structure whereas the channel may be on the top side of the electrolyte structure).

Alternatively, the gate may be deposited on the side of the electrolyte structure in which the channel is deposited (e.g., the gate may be on the top side of the electrolyte structure and the channel may be on the top side of the electrolyte structure; or the gate may be on the bottom side of the electrolyte structure and the channel may be on the bottom side of the electrolyte structure).

At block <NUM>, a third contact element (i.e., gate contact element) may be deposited on the gate via conventional synthesis and deposition methods.

In some examples, the method of forming an electronic transistor may further comprise depositing a seed on the channel before forming the first contact element and/or the second contact element, the seed being between the channel and the first contact element and/or the channel and the second contact element. The seed may be deposited via conventional synthesis and deposition methods.

In some examples, the method of forming an electronic transistor may further comprise depositing a capping layer arranged on the electronic transistor. Specifically, the capping layer may be configured to be onto the channel and / or the gate.

In some of these examples, the capping layer may be configured to be additionally onto the electrolyte, and / or the gate contact element; and / or the source contact element; and / or the drain contact element.

It is noted that conventional synthesis and deposition methods may comprise physical vapor deposition (PVD), for example, cathodic arc deposition, electron-beam physical vapor deposition, close-space sublimation, pulsed laser deposition; thermal evaporation; electron-beam evaporation; sputtering e.g. diode sputtering, RF diode sputtering, triode sputtering, magnetron sputtering, reactive sputtering, or ion-beam sputtering; ion-assisted deposition; chemical vapor deposition (CVD); sol-gel coatings; or atomic layer deposition (ALD).

Claim 1:
An electronic transistor (<NUM>) comprising:
- a body comprising at least:
∘ an electrolyte structure (<NUM>);
∘ a channel (<NUM>) provided in contact with the electrolyte structure (<NUM>);
∘ a gate (<NUM>) provided in contact with the electrolyte structure (<NUM>);
- at least three contact elements configured to be connected to an external circuit, at least one of the contact elements, referenced as Gate contact element, being separated from the electrolyte structure (<NUM>) by means of the gate (<NUM>), and the other contact elements, referenced as Source contact element and Drain contact element, being interconnected and being separated from the electrolyte structure (<NUM>) by means of the channel (<NUM>);
characterized in that the electrolyte structure (<NUM>) comprises an oxygen ion conducting electrolyte structure (<NUM>), wherein the oxygen ion conducting electrolyte structure (<NUM>) comprises a BiMEVOX structure, where Bi is Bismuth, ME is a Metal, V is Vanadium and OX is an Oxide; wherein the stoichiometry of the BiMEVOX structure is Bi<NUM>V<NUM>-xMExO<NUM>-δ, where <NUM><x<<NUM> and <NUM><δ<<NUM>.