Patent Description:
Each of <CIT>, <CIT> and <CIT> discloses a memory device structure according to the preamble of claim <NUM>.

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Deck select transistors for <NUM>-Dimensional (<NUM>-D) cross point and methods of fabrication are described. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as operations associated with memory devices and transistors, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical or in magnetic contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms.

The term "adjacent" here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms.

Unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

Memory cells are used in conjunction with large arrays of decoder transistors for a variety of <NUM>-D cross point memory applications. A <NUM>-D cross point memory array includes a series of word lines on a first plane and series of bit lines on a second plane above the first plane, where the word lines cross over the bit lines (or vice versa). A memory cell is located at each point of cross over (cross-point) between the word line and the bit line, where the memory cell couples a word line with a corresponding bit line to form a single memory array deck, or herein deck.

A decoder transistor may be individually coupled with each word line and a bit line to address a particular memory cell in a deck. A number of decoder transistors required to address each memory cell (bit cell) is proportional to the number of memory cells in a <NUM>-D cross point array. The number can increase in proportion with increase in number of bit lines and word lines. To accommodate a larger number of decoder transistors in a vicinity of a cross point array, such as, for example below the <NUM>-D cross-point memory array, physical lengths of word lines and bit line may be increased. Alternatively, decoder transistors may occupy a region laterally adjacent to the memory array. In either example a larger chip area may be utilized.

Increasing number of layers (decks) of memory cells to form a <NUM> -dimensional array can increase memory density per unit area. However, increasing the number of memory cells also proportionately increases the number of decoder transistors required. In some examples a single deck may include <NUM> bit lines and <NUM> word lines. Thus, a single <NUM> by <NUM> deck can require <NUM> decoder transistors. Because the number of decoder transistors increases proportionally with the number of decks, enabling a high-density memory array for a given die size can be highly challenging.

However, the inventors have devised an arrangement that can reduce the number of number of decoder transistors below a <NUM>-D cross point memory array by integrating a deck select transistor within each word line and each bit line of a deck. Additionally, vertically spaced word lines (and bit lines) across multiple decks are collectively coupled together. In one example, a memory array may include two decks, where each word line of a first deck is coupled with a corresponding word line of a second deck directly below by an interconnect via. Each pair of word lines is coupled by a single decoder transistor below the memory array. For example, a first interconnect via can be used to couple the pair of word lines and a second interconnect via can couple the lowest word line to a decoder transistor. As the number of decks are increased, respective word lines from each successive deck may be coupled together by an intervening interconnect via. A lowest word line corresponding to a lowest level deck may be further coupled to a single decoder transistor below the lowest deck.

Similarly, each bit line of a first deck may be coupled with a corresponding bit line of a second deck directly below by an interconnect via. Each pair of bit lines is coupled to a single decoder transistor by an interconnect via. When the number of decks are increased, a respective bit line from each successive deck are coupled to each other and to a single decoder transistor. For example, a first bit line from a first deck may be coupled with a first bit line from a second deck directly above the first bit line. Thus, the total number of decoder transistors in a memory array is equal to a total number of word and bit lines on any given deck, and independent of the number of decks. During operation, while all word lines (bit lines) that are coupled across multiple decks may be biased simultaneously. However, because there is an intervening deck select transistor between the memory cell and the interconnect via on each deck, it is possible to select a single memory cell to program by biasing an appropriate deck select transistor.

When each deck include a large number of word lines and bit lines (<NUM> for example), turning on each deck select transistor will require a large number of routing lines. To mitigate the problem of individually routing each transistor, gates of each deck select transistor on each of the word lines (bit line) of a single deck may be electrically coupled together. A single routing conductor may be coupled with a single deck select transistor. During operation, all deck select transistors on word lines (bit lines) of a single deck will be at a same gate bias. However, a single deck select transistor and a single word line-bit line combination may be biased to program a single memory cell.

In a first deck select transistor embodiment, each word line (bit line) includes a line portion that is fully oxidized (herein, oxidized line portion) to form an electrical break and a channel material is adjacent to at least one sidewall of the oxidized line portion. In some such embodiments, a gate structure is adjacent to the channel material and the immediate conductive portions of the word line (or bit line) on either side of the oxidized line portion may function as source or drain regions of the deck select transistor. In some embodiments, the channel material completely clads the oxidized line portion, and the gate structure clads the channel material. In exemplary embodiments, the transistors are thin film transistors that include an amorphous or polycrystalline channel.

In a second deck select transistor embodiment, each word line (bit line) is divided into co-linear two conductive line segments with a channel material (also colinear) between and colinear with the two conductive line segments. The two conductive line segments on either side of the channel material may function as source or drain regions of the second deck select transistor embodiment. In some such embodiments, a gate structure is adjacent to two or more surfaces of the channel material. In an exemplary embodiment, the gate structure is on three surfaces (e.g., on a top surface and on two sidewall surfaces) of the channel material and the deck select transistor is a fin-FET device.

<FIG> is an isometric illustration of a memory device structure <NUM> according to an embodiment of the present invention, including deck select transistors, such as deck select transistor 101A and 101B. Memory device structure <NUM> includes a first line structure <NUM> (herein line structure <NUM>) along a first direction (for e.g., x-axis). The line structure <NUM> includes a line <NUM> (herein line <NUM>) adjacent to a line structure <NUM> (herein line <NUM>), where the line <NUM> includes a channel <NUM> and line <NUM> includes a transistor channel <NUM>. The memory device structure <NUM> further includes a second plurality of line structures <NUM> (herein line structure <NUM>) along a second direction (e.g., y-axis). As shown, line structure <NUM> is directed along the y-axis. Line structure <NUM> includes line <NUM> adjacent to a line <NUM>, where the line <NUM> includes a transistor channel <NUM> and the line <NUM> includes a transistor channel <NUM>.

The memory device structure <NUM> further includes a memory cell at each cross-point between the line structures <NUM> and the line structures <NUM>. The total number of memory cells per deck is equivalent to a product of the number of lines in line structures <NUM> and the number of lines in line structure <NUM>. The memory device structure <NUM> includes <NUM> memory cells on a single deck, as shown. Examples of memory device structure <NUM> includes a memory cell <NUM> at a cross point between line <NUM> and line structure <NUM>, a memory cell <NUM> at a cross point between line <NUM> and line <NUM>, a memory cell <NUM> at an intersection between line <NUM> and line structure <NUM>, for example.

The memory device structure <NUM> includes multiple layers of line structures such as line structures <NUM> and <NUM>. Each pair of line structures such as line structures <NUM> and <NUM> that are separated by an array of memory cells, such as memory cell array <NUM>, constitutes a memory deck. The lines in line structures <NUM> and <NUM> operate as multiple word and bit line pairs, respectively (or vice versa). In the illustrative embodiment, the memory structure <NUM> includes <NUM> decks. A first deck <NUM> includes line structures <NUM> and <NUM>, and memory cell array <NUM>.

In the illustrative embodiment, memory device structure <NUM> further includes a second deck <NUM> below the deck <NUM>. The deck <NUM> includes a plurality of line structures <NUM> (herein line structure <NUM>) parallel to the line structure <NUM>. The line structure <NUM> includes a line <NUM> and a line <NUM>, where line <NUM> includes a transistor channel <NUM> and the line <NUM> includes a transistor channel <NUM>. The lines in line structure <NUM> and in line structure134 operate as multiple word and bit line pairs, respectively (or vice versa).

The memory device structure <NUM> further includes a plurality of line structures <NUM> (herein line structure <NUM>) parallel to the line structure <NUM>. In the Figure, the line structure <NUM> has a longitudinal axis along the y-axis. The line structure <NUM> includes line structure <NUM> adjacent to a line structure <NUM>, where the line <NUM> includes a transistor channel <NUM> and the line <NUM> includes a transistor channel <NUM>. The deck <NUM> further includes a memory cell, at each cross-point between the line structure <NUM> and the line structure <NUM>. As shown, memory cell <NUM> is at a cross-point between line structures <NUM> and <NUM> and memory cell <NUM> is at a cross point between line structures <NUM> and <NUM>.

In the illustrative embodiment, the memory device structure <NUM> includes an array of <NUM> by <NUM> orthogonal lines per deck. Depending on embodiments, deck <NUM> or <NUM> can include between <NUM>-<NUM> lines.

Each deck select transistor, for example, transistor 101A includes a gate electrode adjacent to the channel and an intervening gate dielectric layer between the gate electrode and the channel. In the illustrative embodiment, individual gate electrodes of each deck select transistor, e.g., transistors 101A and 101B are coupled together. As shown gate structure <NUM> includes gate electrodes of adjacent transistor channels in each line of line structure <NUM>. The gate dielectric layer isolates each channel layer of each deck select transistor (101A, 101B etc) in the line structure <NUM>. In embodiments, coupling between gate electrodes of distinct deck select transistors 101A, 101B etc. advantageously enables simultaneous biasing of gate electrodes, saving significant real estate for other essential circuitry. In an embodiment, where lines structure <NUM> includes <NUM> lines, all <NUM> gate electrodes may be coupled by a single routing conductor.

The memory device structure <NUM> further includes gate structures <NUM>, <NUM> and <NUM> adjacent to a plurality of transistor channels. Gate structure <NUM>, <NUM> and <NUM> include one or more features of the gate structure <NUM> such as a gate electrode and a gate dielectric layer. It is to be appreciated that each gate structure <NUM>, <NUM>, <NUM> and <NUM> may be independently biased through one or more biasing electrodes (not shown in the Figure).

Memory device structure <NUM> may include different deck select transistor architectures including different gate and channel structures having different FET characteristic ( for e.g., N-FET a P-FET).

<FIG> is an isometric illustration of a deck select deck select transistor <NUM> in accordance with embodiments of the present invention. Portions of the channel <NUM> are removed to provide clarity. As shown, each line structure in the line structure <NUM> has various portions that have varying material compositions along a longitudinal length (e.g., x-axis). In the illustrative embodiment, each line in line structure <NUM> also has a cross-sectional area in the y-z plane that varies along the x-direction in regions within channel <NUM>. A portion of gate structure <NUM> and channel <NUM> is cut out to reveal a shape of a representative line, for example line <NUM> and channel, for example channel <NUM>. In an embodiment, the gate structure <NUM> includes a gate dielectric layer, and a gate electrode. In the illustrative embodiment, a gate dielectric layer is not shown for clarity. As shown, gate structure <NUM> is adjacent to each transistor channel in each line of the line structure <NUM>.

<FIG> is a cross sectional illustration of deck select transistor <NUM> through the line A-A' in the structure of <FIG>. In the illustrative embodiment, line <NUM> has a line portion 104A and a line portion 104B that includes a metal or an alloy including the metal, and a line portion 104C between line portion 104A and line portion 104B. In an embodiment, line portion 104C includes the metal and oxygen. The deck select transistor <NUM> includes channel <NUM>, and gate structure <NUM> on the channel <NUM>. As shown, gate structure <NUM> includes a gate dielectric layer 202A on the channel <NUM> and a gate electrode 202B on the gate dielectric layer 202A. In the illustrative embodiment, line portion 104A is a source or a drain region and line portion 104B is a drain or a source region of the deck select transistor <NUM>. In the illustrative embodiment, terminal interconnect is coupled with line portion 104B and memory cell <NUM> is on and coupled with line portion 104B. Only one memory cell is shown, though line portion 104B is long enough to include multiple memory cells as shown in <FIG>. Referring again to <FIG>, The entire line portion 104B may be considered to be a source or a drain, as the line portions 104A and 104B are conductive.

Line portion 104C is insulative and has a length, LO, along the x-axis. In some embodiments, LO is between <NUM> and <NUM>. The length of line portion 104C determines a maximum effective gate length, LG of deck select transistor <NUM>.

In the illustrative embodiment, line <NUM> also includes a line portion 104D between line portions 104B and 104C. Line portion 104D may have a same or substantially the same material composition as line portion 104B. As shown, line <NUM> also includes a portion 104E between line portions 104A and 104C. Line portion 104E has a same or substantially the same material composition as a material composition of line portion 104A or 104B. Line portions 104D and 104E may be considered to be lateral source or drain extensions under the channel <NUM>. In some embodiments the line structure portion 104A, 104D and 104E include a metal such as tungsten, tantalum or titanium. In other embodiments line structure portion 104A, 104D and 104E include nitrogen and at least one of tungsten tantalum or titanium.

As shown, line portions 104D and 104E have a length, L<NUM> and L<NUM>, respectively. In some embodiments, , L<NUM> and L<NUM>, range between <NUM> and <NUM> and <NUM> and <NUM>, respectively. L<NUM> may be equal to or be different than L<NUM>.

As shown, line <NUM> has a height relative to a lower most surface 104F that varies along the x-direction. In the illustrative embodiment, the height of line <NUM> decreases in the vicinity of channel <NUM> compared to away from the channel <NUM>. As shown line portions 104A and 104B have a height, H<NUM>. In embodiments, H<NUM> is between <NUM> and <NUM>. As shown portions 104C, 104D and 104E have a height, H<NUM> that is less than H<NUM>. In embodiments, H<NUM> is between <NUM> and <NUM>. In exemplary embodiments, H<NUM> is substantially uniform along the x-axis.

In the illustrative embodiment, the channel <NUM> extends laterally beyond line portion 104C along the x-axis, and over line portions 104D and 104E. Channel <NUM> has a thickness, TC. In the illustrative embodiment, the channel <NUM> has a thickness, TC that is substantially equal to a difference between respective heights of the line portions 104A and line portion 104C, 104D or 104E. In other embodiments TC is greater or less than a difference between respective heights of the line portions 104A and line portion 104C, 104D or 104E.

The gate structure <NUM> has a gate length that is less than a lateral width of the channel <NUM> (Leffective of deck select transistor <NUM>). In embodiments, LG, is between <NUM> and <NUM>. In the illustrative embodiment, the gate structure <NUM> does not extend over the line portions 104A and 104B.

In an embodiment, the gate electrode <NUM> includes at least one P-type work function metal or an N-type work function metal, depending on whether a transistor is to be a P-FET or an N-FET transistor. Examples of N type material include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide and examples of P type materials include ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides, e.g., ruthenium oxide.

In embodiments, the gate dielectric layer 202A includes a material having a high dielectric constant or high-K material. Examples of gate dielectric layer 202A include oxygen and one or more of elements such as hafnium, silicon, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, or zinc. Examples of high-K material that may be used in the gate dielectric layer 202A include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In some embodiments gate structure <NUM> includes one or more work function layers (gate electrode 202B), and a fill metal on the one or more work function layers, where the fill metal (not shown in illustration) fills a space between gate electrodes of respective adjacent lines. In some such embodiments, gate structure <NUM> includes a layer of additional conductive material extending above gate electrode 202B.

<FIG> is a cross illustration of the line portion 104A or 104B. In the illustrative embodiment, an outline of the line portion 104C (dashed lines) is illustrates relative widths of line portions 104C and 104A, 104B. As shown, line portion 104A or 104B is laterally wider than line portion 104C (along the y-direction). In one embodiment, line portion 104A and 104B have a width WA, and the line portion 104C has a width Wc, where W<NUM> is greater than Wc. In embodiments, WA is greater than WC by at least <NUM>.

<FIG> is a cross sectional illustration through the line C-C' of the structure in <FIG>. In the illustrative embodiment, the line portion 104C has a rectangular cross section in the y-z plane and channel <NUM> is on at least <NUM> surfaces of the line portion 104C. As shown channel <NUM> is adjacent to surface <NUM>, and sidewalls <NUM> and 104J of line portion 104C. Such a channel <NUM> may be referred to as a saddle channel <NUM>. As shown, the gate dielectric layer 202A and the gate electrode 202B are conformal with sidewalls <NUM> and 104J and surface <NUM>. In some such embodiments, the deck select transistor <NUM> is known as a saddle-FET.

<FIG> is an isometric illustration of a deck select transistor <NUM> in accordance with embodiments of the present invention. As shown, each line in line structure <NUM> has varying material compositions along a longitudinal length (x-axis). In the illustrative embodiment, each line of line structure <NUM> also has a cross-sectional area in the y-z plane that varies along the x-axis in regions within and away from transistor channel <NUM>. A portion of transistor channel <NUM> and gate structure <NUM> is cut out to reveal a shape of a representative line structure, such as line <NUM> and transistor channel <NUM>. A gate dielectric layer is not shown in the Figure to provide clarity. In the illustrative embodiment, transistor channel <NUM> surrounds line portions 104C, 104D (not visible) and 104E. In the illustrative embodiment, channel <NUM> asymmetrically surrounds the line <NUM>. In embodiments, gate structure <NUM> has one or more features of the gate structure <NUM>. As shown, gate structure <NUM> couples each transistor channel in each line of line structure <NUM>.

<FIG> is a cross sectional illustration of a deck select transistor <NUM> through the line A-A' in the structure of <FIG>. In the illustrative embodiment, line <NUM> has one or more of the features described above in association with <FIG>.

In the illustrative embodiment, transistor channel <NUM> extends laterally beyond line portion 104C along the x-axis, and over line portions 104D and 104E. Transistor channel <NUM> has a thickness, TC. In the illustrative embodiment, the transistor channel <NUM> has a thickness, TC that is substantially equal to a difference between respective heights of the line portions 104A and line portion 104C, 104D or 104E. In other embodiments TC is greater or less than a difference between respective heights of the line portions 104A and line portion 104C, 104D or 104E. However, as shown, the channel <NUM> has a lowermost surface 302A that is below the lowermost surface 104F of the line portion 104A. As shown, the gate dielectric layer 304A and gate electrode 304B of gate structure <NUM> are also below the lowermost surface 104F.

In embodiments, gate dielectric layer 304A and gate electrode 304B include a material that is the same or substantially the same as the material of the gate dielectric layer 204A and gate electrode 204B, respectively, as described in association with <FIG>. In an embodiment, the transistor channel <NUM> includes a material that is the same or substantially the same as the material of the channel <NUM>.

In some embodiments gate structure <NUM> includes one or more work function layers (gate electrode 304B), and a fill metal on the one or more work function layers, where the fill metal (not shown in illustration) fills a space between gate electrodes of respective adjacent lines. In some such embodiments, gate structure <NUM> includes a layer of additional conductive material extending above gate electrode 304B. The layer of additional conductive material may also extend below portion of the gate electrode 304B that is under surface 104F.

<FIG> is a cross sectional illustration through the line B-B' of the structure in <FIG>. In the illustrative embodiment, the line portion 104C has a rectangular cross section in the y-z plane and transistor channel <NUM> clads line portion 104C. As shown, the gate dielectric layer 304A clads line portion 104C and the channel <NUM>, and gate electrode 304B clads gate dielectric layer 304A. In some such embodiments, the deck select transistor <NUM> is known as a gate all round-FET. Depending on the application, deck select transistor <NUM> may be a P-FET or an N-FET.

In a third embodiment, a deck select transistor includes a fin-FET architecture (an example of a non-planar transistor). <FIG> is an isometric illustration of deck select transistor <NUM>, in accordance with embodiments of the present invention. A portion of gate structure <NUM> is cut out to reveal a shape of a representative transistor channel, such as transistor channel <NUM>. A gate dielectric layer is not shown in the Figure to provide clarity. Gate structure <NUM> is adjacent to each line of line structure <NUM>.

<FIG> is a cross sectional illustration of deck select transistor <NUM> through the line A-A' in the structure of <FIG>. In the illustrative embodiment, line <NUM> has first and second portions 104A and 104B. As shown, line <NUM> also includes deck select transistor channel <NUM> between the line portions 104A and 104B. In the illustrative embodiment, line portion 104A is one of a source or a drain region and line portion 104B is the other of the source or a drain region of deck select transistor <NUM>. Transistor channel <NUM> has a length, LO, as shown. In embodiments LO is between <NUM> and <NUM>.

Line portions 104A and 104B have a height, H<NUM>, as shown. In embodiments, H<NUM> is between <NUM> and <NUM>. Transistor channel <NUM> has a height, H<NUM>. As shown, H<NUM> is greater than H<NUM>. In embodiments, H<NUM> is between <NUM> and <NUM>. In exemplary embodiments, H<NUM> is substantially uniform along the x-axis. Depending on a desired fin height, H<NUM> may be less than H<NUM>.

As shown, gate structure <NUM> is on the channel <NUM> in the cross-sectional illustration. Depending on a fabrication process the gate structure <NUM> has a gate length, LG, that is less than or equal to a length, LO, of the transistor channel <NUM>. When LG, is less than LO, gate dielectric layer 402A may be adjacent to sidewalls of the gate electrode 402B. It is to be appreciated that memory cell <NUM> is coupled with line portion 104B of deck select transistor <NUM> and terminal interconnect <NUM> is coupled with line portion 104A of deck select transistor <NUM>.

In embodiments, gate dielectric layer 402A and gate electrode 402B include a material that is the same or substantially the same as the material of the gate dielectric layer 204A and gate electrode 204B, respectively. In an embodiment, the transistor channel <NUM> includes a material that is the same or substantially the same as the material of the channel <NUM>.

In some embodiments gate structure <NUM> includes one or more work function layers (gate electrode 402B), and a fill metal on the one or more work function layers, where the fill metal (not shown in illustration) fills a space between gate electrodes of respective adjacent lines. In some such embodiments, gate structure <NUM> includes a layer of additional conductive material extending above gate electrode 402B.

<FIG> is a cross sectional illustration through the line B-B' of the structure in <FIG>. In the illustrative embodiment, transistor channel <NUM> has a rectangular cross section on the y-z plane. As shown, transistor channel <NUM> has a rectangular cross section in a y-z plane. In the illustrative embodiment, gate dielectric layer 402A is on top surface 404A, and on sidewall surfaces 404B and 404C of transistor channel <NUM>. The gate electrode 402B is on the gate dielectric layer 402A adjacent to surfaces 404A, 404B and 404C. In some such embodiments, the deck select transistor <NUM> is known as a fin-FET (an example of a non-planar transistor). Depending on the application deck select transistor <NUM> may be a P-FET or an N-FET.

<FIG> is a cross sectional illustration through the line B-B' of the structure in <FIG>. In the illustrative embodiment, an outline of transistor channel <NUM> (dashed lines) illustrates relative widths of the line <NUM> and the channel <NUM>. As shown, line portion 104A and 104B are laterally wider (along the y-direction) than transistor channel <NUM>. As shown, line portion 104A and 104B have a width WA, and the line portion 104C has a width Wc. In the illustrative embodiment, WA is greater than Wc. In embodiments, WA is greater than WC by at least <NUM>.

Referring again to <FIG>, the memory device structure <NUM> further includes a group of terminal interconnects, that couple lines which are aligned along a same direction across two or more decks. In the illustrative embodiment, each terminal interconnect group <NUM> and <NUM>, includes a plurality of terminal interconnects. In the illustrative embodiment, each terminal interconnect in terminal interconnect group <NUM> is coupled between a single line in line structure <NUM> and a corresponding vertically aligned line in line structure <NUM>. For example, lines <NUM> and <NUM> are coupled by a terminal interconnect <NUM>, lines <NUM> and <NUM> are coupled by a terminal interconnect <NUM>. During operation, any single terminal interconnect, such as terminal interconnect <NUM> can simultaneously bias two lines <NUM> and <NUM> on two different decks to a same potential. However, a single memory cell such as memory cell <NUM> may be preferably programmed over memory cell <NUM> (below memory cell <NUM>) by applying a bias on deck select transistor 101A.

In the illustrative embodiment, each transistor channel, is between a terminal interconnect and a memory cell. For example, channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>, and transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>. Similarly, transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM> and transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>.

Also as shown, each terminal interconnect in terminal interconnect group <NUM> is coupled between a single line in line structure <NUM> of deck <NUM> and a corresponding vertically aligned line within line structure <NUM> of deck <NUM>. In the illustrative embodiment, lines <NUM> and <NUM> are coupled by a terminal interconnect <NUM>, and lines <NUM> and <NUM> are coupled by a terminal interconnect <NUM>. During operation, terminal interconnect <NUM> can simultaneously bias two line <NUM> and <NUM> on two different decks to a same potential.

In the illustrative embodiment, transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>, and transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>. Similarly, transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM> and transistor channel <NUM> is laterally between memory cell <NUM> and terminal interconnect <NUM>.

In an embodiment the lines in each of the line structures <NUM>, <NUM>, <NUM> and <NUM> include a metal such as tungsten, tantalum or titanium or an alloy that includes nitrogen and at least one of tungsten tantalum or titanium.

In an embodiment transistor channels <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> each include a polycrystalline or an amorphous material that is suitable for a thin film transistor.

In some embodiments, channels <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> etc. include an n-type semiconductor material. Examples of n-type semiconductor material include two or more of In,Ga, Zn, Mg, Al, Sn, Hf, O, W such as In<NUM>O<NUM>, Ga<NUM>O<NUM>, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, InWO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO or InMgZnO.

In embodiments an n-type channel may be doped with Ti, W, Cu, Mn, Mg, Fe, Hf, Al, Ni, CO or Ru. In embodiments, the dopant concentration is between <NUM><NUM> and <NUM><NUM>atoms/cm<NUM>, and wherein the channel comprises a thickness between <NUM> to <NUM>.

In other embodiments, channels <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, etc. include a p-type material. Examples of p-type semiconductor material include NbO, NiO, CoO, SnO, Cu<NUM>O, AgAlO, CuAlO<NUM>, AlScOC, Sr<NUM>BPO<NUM>, La<NUM>SiO<NUM>Se, LaCuSe, Rb<NUM>Sn<NUM>O<NUM>, La<NUM>O<NUM>S<NUM>, K<NUM>Sn<NUM>O<NUM>, Na<NUM>FeOSe<NUM>, ZnRh<NUM>O<NUM> or CuOx, where x is <NUM> or <NUM>.

In an embodiment, each of the interconnects <NUM>, <NUM>, <NUM>, <NUM> include copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, ruthenium, molybdenum, cobalt, and their alloys, or alloy including nitrogen and one or more of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, titanium, tin or lead. In some embodiments, each of the interconnects <NUM>, <NUM>, <NUM>, <NUM> include metal carbides such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide or aluminum carbide.

In the illustrative embodiment, memory device structure <NUM> further includes additional memory cells corresponding to an additional deck between deck <NUM> and deck <NUM>.

<FIG> is a cross sectional illustration through a line A-A' of the structure in <FIG> and illustrates arrangement of additional memory cells within a deck <NUM>. Deck <NUM> includes line structures <NUM> and <NUM>, and memory cell array <NUM>. In the cross-sectional illustration two memory cells are shown such as a memory cell <NUM> between line <NUM> and line <NUM>, and a memory cell <NUM> between line <NUM> and line <NUM>. Other memory cells at the intersection between the respective lines in each of the line structure <NUM> and <NUM> are not visible in the cross-sectional illustration.

In embodiments, associated transistors corresponding to each deck can all be P-FET or N-FET. In some embodiments, where both a P-FET or an N-FET is implemented in memory device structure <NUM>, the N-FET and P-FET transistors are on alternate line structures. For example, deck select transistors corresponding to channels <NUM> and <NUM> may be P-FET or N FET, deck select transistors corresponding to channels <NUM> and <NUM> may be N-FET or P-FET, deck select transistors corresponding to channels <NUM> and <NUM> may be P-FET or N-FET, and deck select transistors corresponding to channels <NUM> and <NUM> may be N-FET or P-FET.

It is to be appreciated that in some embodiments all memory cells within a given deck have a same configuration, i. e, either the non-volatile memory element is on the selector device, or vice versa.

In an embodiment, a memory cell <NUM> has a structure as shown in <FIG>, where a selector element <NUM> is above a non-volatile memory element <NUM>. In other embodiments selector element <NUM> is below non-volatile memory element <NUM>. The non-volatile memory element <NUM> may include phase change memory, a resistive random access memory (R-RAM), ovonic threshold switching (OTS) memory or a conductive bridge RAM.

Also as shown, each of the memory cells <NUM>, <NUM>, <NUM> and <NUM>, <NUM> and <NUM> have a height, HMC. In embodiments, HMC depends on thicknesses and structures of each of the respective selector element <NUM> and non-volatile memory element <NUM>.

<FIG> illustrates a cross-sectional view of an example non-volatile memory element <NUM> that includes a resistive random-access memory (RRAM) device that includes oxygen vacancy switching. In the illustrated embodiment, the RRAM material stack includes a bottom electrode <NUM>, a switching layer <NUM> over the bottom electrode <NUM>, an oxygen exchange layer <NUM> over the switching layer <NUM>, and a top electrode <NUM> on the oxygen exchange layer <NUM>.

In an embodiment, bottom electrode <NUM> includes an amorphous layer. In an embodiment, bottom electrode <NUM> is a topographically smooth electrode. In an embodiment, bottom electrode <NUM> includes a material such as W, Ta, TaN or TiN. In an embodiment, bottom electrode <NUM> is composed of Ru layers interleaved with Ta layers. In an embodiment, bottom electrode <NUM> has a thickness is between <NUM> and <NUM>. In an embodiment, top electrode <NUM> includes a material such as W, Ta, TaN or TiN. In an embodiment, top electrode <NUM> has a thickness is between <NUM> and <NUM>. In an embodiment, bottom electrode <NUM> and top electrode <NUM> are the same metal such as Ta or TiN.

Switching layer <NUM> may be a metal oxide, for example, including oxygen and atoms of one or more metals, such as, but not limited to Hf, Zr, Ti, Ta or W. In the case of titanium or hafnium, or tantalum with an oxidation state +<NUM>, switching layer <NUM> has a chemical composition, MOX, where O is oxygen and X is or is substantially close to <NUM>. In the case of tantalum with an oxidation state +<NUM>, switching layer <NUM> has a chemical composition, M<NUM>OX, where O is oxygen and X is or is substantially close to <NUM>. In an embodiment, switching layer <NUM> has a thickness is between <NUM> and <NUM>.

Oxygen exchange layer <NUM> acts as a source of oxygen vacancy or as a sink for O<NUM>-. In an embodiment, oxygen exchange layer <NUM> is composed of a metal such as but not limited to, hafnium, tantalum or titanium. In an embodiment, oxygen exchange layer <NUM> has a thickness is between <NUM> and <NUM>. In an embodiment, the thickness of oxygen exchange layer <NUM> is at least twice the thickness of switching layer <NUM>. In another embodiment, the thickness of oxygen exchange layer <NUM> is at least twice the thickness of switching layer <NUM>. In an embodiment, the RRAM device has a combined total thickness of the individual layers is between <NUM> and <NUM> and width is between <NUM> and <NUM>.

While an oxygen vacancy switching device is illustrated in <FIG>, RRAM devices may include other examples such as phase change devices.

<FIG> is a cross-sectional illustration of a structure of a memory element where an RRAM device includes a phase change layer. In the illustrative embodiment, non-volatile memory element <NUM> includes electrode layers <NUM> and <NUM> an insulator layer <NUM> between the electrode layers <NUM> and <NUM>.

In some such embodiments, the insulator layer <NUM> exhibits charge carrier tunneling behavior. In some such embodiments, the insulator layer <NUM> includes oxygen and a metal, such as, but not limited, to aluminum, hafnium, tantalum and titanium. In further embodiments, the insulator layer <NUM> is also doped with atoms of one or more metals, such as, but not limit to, copper, silver or gold. In some such embodiments, the insulator layer <NUM> is doped to a concentration between <NUM>%-<NUM>% (atomic) with atoms of one or more metals such as copper, silver or gold. In an embodiment, the insulator layer <NUM> has a thickness between <NUM> to <NUM>.

In another embodiment, the insulator layer <NUM> includes a threshold switching material such as a phase change material. In some examples, the insulator layer <NUM> may include a phase change material that exhibits at least two different electrical states characterized by two different resistances, a conductive state and a resistive state. In some examples, the phase change material exhibits at least two different material states, amorphous and crystalline that correspond to the two different resistance states. In an embodiment, a phase change material that is in a completely crystalline phase is conductive and resistive when the phase change material is in an amorphous state. However, by modulating the relative extent of crystalline phase and amorphous phase in a given volume of the phase change material the resistance of the phase change material can be tuned. In an embodiment, the resistance state of the phase change material may be set by heating and cooling the phase change material in a specific manner by application of a voltage bias, e.g., between electrodes <NUM> and <NUM> to induce joule heating.

In an embodiment, the phase change material includes Ge and Te. In an embodiment, the phase change material further includes Sb. In an embodiment, the phase change material includes a ternary alloy of Ge, Te and Sb such as Ge<NUM>Sb<NUM>Te<NUM>. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy including at least one element from the group V periodic table such as Te, Se, or S. In an embodiment, the phase change material includes a binary alloy, ternary alloy or a quaternary alloy which comprises at least one of Te, Se, or S, where the said alloy further comprises one element from the group V periodic table such as Sb. In an embodiment, the phase change material includes a dopant such as silver, indium, gallium, nitrogen, silicon or germanium. In an embodiment, the dopant concentration is between <NUM>% and <NUM>% of the total composition of the phase change material. In an embodiment, the insulator layer <NUM> has a thickness (measured along e.g., x-axis) that is between <NUM> and <NUM>.

<FIG> is a cross-sectional illustration of a structure of a selector element <NUM> of a memory cell in accordance with embodiments of the present invention. As shown, the selector device includes a metal-insulator-metal (MIM) stack. The MIM stack of selector element <NUM> includes a selector electrode <NUM>, an insulator layer <NUM> between the selector electrode <NUM> and a selector electrode <NUM>.

In embodiments, the insulator layer <NUM> includes a ovonic threshold switching material. In an embodiment, the insulator includes alloy of Ge, As and Se, such as GeAsSe, GeSe or AsSe. In embodiments the alloy Ge, As and Se may include dopants, for example As doped GeSe, Ge doped AsSe or GeAsSe doped with In, Te or Sb. In embodiments, the insulator layer <NUM> has a thickness that is material dependent, where the thickness is between <NUM> and <NUM>. Electrodes <NUM> and <NUM>. may include a material that is the same or substantially the same as a material of electrodes <NUM> and <NUM>.

In another embodiment, the insulator layer <NUM> includes a material that can undergo a reversible insulator to metal transition. In embodiments, the transition is triggered by a thermal process or by an electrical process. In some such embodiments, the insulator layer <NUM> includes oxygen and atoms of one or more metals, such as, but not limited to niobium, vanadium and tantalum. In some specific examples, the insulator layer <NUM> includes vanadium (IV) oxide, VO<NUM> and vanadium (V) oxide, V<NUM>O<NUM> and niobium (V) oxide, Nb<NUM>O<NUM>. In one specific example, the insulator layer <NUM> includes niobium (V) oxide, Nb<NUM>O<NUM> and may exhibit filamentary conduction. In an embodiment, the insulator layer <NUM> is amorphous. In an embodiment, the insulator layer <NUM> which can undergo an insulator to metal transition has a thickness between <NUM> and <NUM>.

In some embodiments where insulator-to-metal transition is to occur, the insulator layer <NUM> further includes a dopant such as silver, copper or gold. In an embodiment, the dopant concentration is between <NUM>-<NUM>% of the total composition of the insulator layer <NUM>. A dopant concentration between <NUM>-<NUM>% may facilitate filament conduction.

In an embodiment, selector electrode <NUM> and <NUM> include a conductive material such as TiN and TaN or a metal such as Ta, W or Pt. In an embodiment, the selector electrodes <NUM> and <NUM> have a thickness between <NUM> and <NUM>. Electrodes <NUM> and <NUM> may or may not have a same thickness.

<FIG> is a method <NUM> to fabricate a deck select transistor <NUM> or <NUM> of <FIG> and 3A-3D. The method <NUM> begins at operation <NUM> with the formation of a plurality of vias in a dielectric above a substrate. The method <NUM> continues at operation <NUM> with the formation of a plurality of lines above the individual ones of the vias. The method <NUM> continues at operation <NUM> with a process to oxidize a portion of the individual ones of the lines in the plurality of line to form an oxidized region within the individual ones of the lines, away from the vias. The method <NUM> continues at operation <NUM> with the formation of a transistor channel material on the oxidized region of each of the lines. The method <NUM> concludes at operation <NUM> with the formation of a gate structure on the channel material of each of the individual ones of the plurality of lines.

<FIG> is a cross-sectional illustration a terminal interconnect array <NUM> formed in a dielectric <NUM> over a substrate <NUM>.

In an embodiment, a plurality of vias are patterned into the dielectric <NUM> by a masking and an etching process. After formation of the plurality of vias, a liner layer followed by a fill metal is deposited into the plurality of vias and a planarization process is performed to form terminal interconnects <NUM>, <NUM>, <NUM> and <NUM>. In an embodiment, the dielectric <NUM> includes silicon and one or more of oxygen, nitrogen or carbon and the patterning process includes a plasma etch. In an embodiment, the terminal interconnects <NUM> and <NUM> includes a same material as the material of the terminal interconnects <NUM> and <NUM>.

<FIG> is an isometric illustration of the terminal interconnect array <NUM> formed in a dielectric <NUM> over a substrate <NUM>. In an embodiment, each terminal interconnect in the terminal interconnect array <NUM> has a substantially rectangular plan-view profile. In other embodiments, the plan view profile may be circular or elliptical.

<FIG> illustrates the structure of <FIG> following the formation of a plurality of line segments <NUM> above the substrate <NUM>. In an embodiment, each line segment <NUM> of the plurality of line segments <NUM> includes a conductive line <NUM>, a hardmask <NUM>, a dielectric <NUM> and a hardmask <NUM> on the dielectric <NUM>.

In an embodiment, a material layer stack of the plurality of line segment <NUM> is deposited on the dielectric <NUM> and on the terminal interconnects <NUM>. In an embodiment, forming the material layer stack includes depositing a layer of a first hardmask material on a conductive layer, depositing a dielectric layer on the layer of hardmask material and depositing a layer of second hardmask material on the dielectric layer. A resist mask may be formed on the layer of second hardmask material and the material layer stack is patterned. In an embodiment, the patterning process includes a plasma etch process. Individual layers in the material layer stack are patterned to form plurality of line segments <NUM>. The layer of second hardmask material is patterned to form a hardmask <NUM>, the dielectric layer is patterned to form dielectric <NUM>, the layer of first hardmask material is patterned to form hardmask <NUM> and the conductive layer is patterned to form a conductive line <NUM>. As shown, a portion of the dielectric <NUM> is also recessed during the patterning process. It is to be appreciated that the terminal interconnects <NUM> is not exposed during the patterning process. In the illustrative embodiment, four-line segments <NUM> are shown. Formation of the four-line segments <NUM> creates openings <NUM> between each line segment <NUM>. The number of lines in the line segments <NUM> equals the number of word or bit lines in the memory array.

In an embodiment, the hardmask <NUM> and <NUM> include silicon and one or more of oxygen, nitrogen or carbon. In an embodiment, the dielectric <NUM> includes silicon and one or more of oxygen, nitrogen or carbon. In exemplary embodiments, the dielectric <NUM> includes silicon and one or more of oxygen or carbon. In an embodiment, the conductive line <NUM> includes a material of the line <NUM>.

<FIG> is an isometric illustration of the structure in <FIG>.

<FIG> illustrates the structure of <FIG> following the formation of a dielectric <NUM> in each opening <NUM> to form a block <NUM>. In an embodiment, a dielectric <NUM> is deposited in openings <NUM>. The deposition process may include a PECVD (plasma enhanced chemical vapor deposition), physical vapor deposition (PVD), chemical vapor deposition (CVD) process. In an embodiment, the dielectric includes silicon and nitrogen and/or carbon. In an embodiment, the dielectric <NUM> is planarized. In an embodiment, a chemical mechanical polish (CMP) process is utilized to planarize the dielectric <NUM> which forms an uppermost surface 810A that is substantially co-planar, with an uppermost surface 808A of the hardmask <NUM>.

<FIG> illustrates the structure of <FIG> following the process of etching portions of the block <NUM>. In an embodiment, a plasma etch process is utilized to etch dielectric <NUM>, and portions of each line segment <NUM> to form a section 1000A and a section 1000B of the block <NUM>. A region <NUM> between the two sections 1000A and 1000B exposes line structures <NUM>.

In an embodiment, the plasma etch process etches the hardmask <NUM>, dielectric <NUM> and hardmask <NUM>, and exposes an uppermost surface of dielectric <NUM> adjacent to the conductive line <NUM>. A subsequent etch process is utilized to recess upper and side portions of the conductive line <NUM>. In an embodiment, a combination of wet chemical and plasma etch processes are utilized to form lateral and vertical recesses.

After the etch process, the exposed region <NUM> is partially masked and an oxidation process is performed. In an embodiment, a sacrificial mask includes a material that is not eroded by a plasma oxidation or a wet chemical process. An outline of the mask is defined by dashed lines <NUM>. The mask creates an opening over a portion of the region <NUM>. In an embodiment, a plasma oxidation or a wet chemical process is utilized to oxidize a portion of the conductive line <NUM> in the region <NUM>. The oxidation process forms an oxidized line portion 802A, between line portions 802B and 802C that are conductive. After the oxidation process, the sacrificial mask is removed. The length (along x-axis) of line portion 802A depends on a desired gate length of a transistor to be formed. In an embodiment, when the conductive line <NUM> includes a pure metal, such as W, Ta, Ti, or Ru or an alloy of the metal such as WN, TiN or TiN, line portion 802A is sufficiently oxidized to be non-conductive.

<FIG> is a cross-sectional illustration taken along the line A-A' of the structure in <FIG>. A cross section of the line portion 802A is shown. A cross section of an unetched portion the conductive line <NUM> (denoted by dashed lines) is superimposed to show the relative sizes between the conductive line <NUM> and line portion 802A. As shown line portion 802A has a width that is laterally reduced from a width, WA, to a lesser width, WC after the etching process. The width WC corresponds to a width of an unetched portion the conductive line <NUM>. A height of the line portion 802A is reduced from H<NUM> to H<NUM>. The reduction in height may be between <NUM> and <NUM>.

<FIG> illustrates the structure of <FIG> following the formation of a thin filmchannel material (herein channel material) <NUM> over line portions 802A, 802B and 802C of each conductive line <NUM>, in region <NUM>. In an embodiment, a mask (not shown in the Figure) is formed on the structure of <FIG>. A PVD, PEVCD, or a CVD deposition process may be utilized to deposit a channel material <NUM>. In an embodiment, channel material <NUM> includes a material that is the same or substantially the same as the material of the channel <NUM>. In an embodiment, the channel material <NUM> is deposited on all surfaces of the line portions 802A, 802B and 802C exposed by the mask. The channel material <NUM> is also deposited on exposed surfaces of dielectric <NUM>. In an embodiment, the channel material <NUM> is deposited to a thickness between <NUM> and <NUM>.

<FIG> is a cross-sectional illustration taken along the line A-A' (slice through line portion 802A) of the structure in <FIG>. In the illustrative embodiment, the channel material <NUM> is conformally deposited on sidewall and upper surfaces of the line portion 802A.

<FIG> is a cross-sectional illustration of the structure in <FIG> following the process to remove portions of the channel material <NUM> above dielectric <NUM> and adjacent to line portion 802A. In an embodiment, a mask <NUM> (inside dashed line <NUM>) is patterned over portions of the channel material <NUM> above the line portion 802A. In an embodiment, a plasma etch process is utilized to etch and remove exposed portions the channel material <NUM> uncovered by the mask <NUM>. The plasma etch process forms channel <NUM> adjacent to each line portion 802A (and on portions 802B and 802C in in and out of the plane of the Figure). It is to be appreciated that the process to isolate each channel associated with each conductive line <NUM>, enables each conductive line <NUM> to selectively program a memory cell in a memory device structure.

In some embodiments, channel material <NUM> is also removed from a top surface of each line portion 802A, as is shown in <FIG>. The process utilized to mask and etch described above in association with <FIG> may be utilized to form openings above the top surface of each line portion 802A. As shown, the plasma etch process forms channel <NUM> adjacent to sidewalls of the line portion 802A.

<FIG> illustrates the structure of <FIG> following the formation of a gate dielectric layer <NUM>. In an embodiment, gate dielectric layer <NUM> includes a material that is the same or substantially the same as the material of the gate dielectric layer 202A. In an embodiment, the gate dielectric layer <NUM> is blanket deposited on the structure of <FIG> by an atomic layer deposition (ALD) or a PVD process. In an embodiment, the gate dielectric layer is deposited conformally on the channel <NUM> (hidden in the illustration), on the dielectric <NUM>, on line portions 802B and 802C (hidden in the illustration), and on sidewalls of each line segment <NUM> exposed in section <NUM>, The gate dielectric layer <NUM> is also deposited on section 1000A and section 1000B, as shown.

<FIG> is a cross-sectional illustration taken along the line A-A' of the structure in <FIG>. As shown gate dielectric layer <NUM> is deposited conformally around channel <NUM>.

<FIG> illustrates the structure of <FIG> following the formation of a gate electrode <NUM>. In an embodiment, a material of gate electrode <NUM> is blanket deposited on the gate dielectric layer <NUM>.

In an embodiment, the material of gate electrode <NUM> is planarized. The planarization process may include, for example, a chemical mechanical polish (CMP) process. In the illustrative embodiment, the CMP process removes the material of gate electrode <NUM> and gate dielectric layer <NUM> in the regions 1000A and 1000B and forms gate electrode <NUM> in region <NUM>. In an embodiment, the process to form the gate electrode <NUM> completes a process to form a thin film transistor <NUM> that has one or more of the properties discussed in association with <FIG>. The planarization process is sufficiently selective to hardmask <NUM>. As shown, the CMP process does not remove hardmask <NUM> from above each line segment <NUM>. The hardmask <NUM> is also utilized as a polish stop during the fabrication process.

<FIG> is a cross-sectional illustration taken along the line A-A' of the structure in <FIG>. In the illustrative embodiment, the gate electrode <NUM> extends continuously across each channel <NUM> that clads each line portion 802A. It is to be appreciated that during operation the gate electrode <NUM> can activate each channel <NUM> above each line portion 802A, if desired.

Referring again to <FIG>, in an embodiment, in a subsequent operation a material to fabricate memory cells above each line structure can be deposited after removing hardmask <NUM>, dielectric <NUM> and hardmask <NUM> from above each conductive line <NUM>. In some embodiments, a dielectric may be blanket deposited on the structure of <FIG> and via openings may be formed to fabricate RRAM devices.

In other examples, transistor <NUM> may be fabricated by modifications to the process flow described in association with <FIG>. In one embodiment, <FIG> illustrates the structure of <FIG>, where an ALD deposition process is utilized to selectively deposit a thin film transistor channel material (channel material) <NUM> around the line portion 802A (hidden in Figure) and parts of line structure portion 802B and 802C not covered by a mask. In some such embodiments, the deposition process utilizes precursors that can favorably nucleate on oxidized metallic materials.

<FIG> is a cross-sectional illustration of the structure in <FIG> taken along a line A-A'. As shown, the deposit TFT channel material <NUM> is deposited to entirely clad the line portion 802A to form discrete channels <NUM>. The method to form a gate electrode is substantially the same as one or more process operations described in association with <FIG>.

In other examples, a transistor, for example transistor <NUM> described in association with <FIG> may be fabricated by modifications to the process flow described in association with <FIG>. <FIG> illustrates the structure of <FIG> following the formation of a plurality of openings <NUM> in region <NUM>. In the illustrative embodiment, a plurality of openings <NUM> are formed by completely etching out the line segment <NUM> completely.

<FIG> illustrates the structure of <FIG> following the formation of a sacrificial dielectric <NUM> in each opening <NUM>, on the dielectric <NUM> followed by the formation of a channel layer <NUM> on the dielectric <NUM>, in each of the plurality of openings <NUM>. A portion <NUM> of the region <NUM> is shown for clarity. In an embodiment, the dielectric is deposited by an ALD process. In an embodiment, the channel layer <NUM> is deposited or grown on the channel layer <NUM>. In embodiments, the channel layer <NUM> includes a material that is the same or substantially the same as the material of the channel layer <NUM>. In an embodiment, the dielectric <NUM> includes a material that is the same or substantially the same as the material of the dielectric <NUM>. In an embodiment, a lateral thickness of opening <NUM> (along the y-axis) and a deposition thickness of the dielectric <NUM> can be controlled to obtain a desired lateral thickness (y-axis) of the channel layer <NUM>.

<FIG> illustrates the structure of <FIG> following a process to reduce a height of the channel layer <NUM>. In an embodiment, the dielectric <NUM> and the channel layer <NUM> are recessed by a plasma etch process, a wet chemical etch process or a combination thereof. As shown dielectric <NUM> and channel layer <NUM> are recessed by a thickness T<NUM>, relative to an uppermost surface 1606A of the channel layer <NUM>. The channel layer <NUM> may be recessed vertically prior to recessing the dielectric to prevent reduction in lateral thickness of channel layer <NUM>). The channel layer <NUM> may be recessed to a desired height, HF, of a fin structure to be formed. As shown, a top surface 1606B of the channel layer <NUM> is substantially planar. In some embodiments, there is rounding of top edge portions of the channel layer <NUM>.

The process to selectively recess dielectric <NUM> and channel layer <NUM>, may be performed after masking region 1000A and a portion 1602A of the region <NUM>. In the illustrative embodiment, an exposed portion of the dielectric <NUM> in the region <NUM> is removed after recessing the dielectric <NUM> and channel layer <NUM>.

In an embodiment, exposed sidewalls of dielectric 1604A are removed prior to formation of a gate structure at a next operation.

<FIG> illustrates the structure of <FIG> following the formation of a gate dielectric layer <NUM> after removal of exposed sidewalls of dielectric 1604B (illustrated in <FIG>). The gate dielectric layer <NUM> includes a material that is the same or substantially the same as the material of the gate dielectric layer 202A. In the illustrative embodiment, the gate dielectric layer is deposited conformally around the channel layer <NUM>, on the dielectric <NUM> and adjacent to portions of dielectric <NUM> that is under the channel <NUM>. Gate dielectric layer <NUM> is also deposited on upper surfaces of hardmask <NUM> (hidden in Figure), and dielectric <NUM> on uppermost surface of channel layer 1606A and on the adjacent dielectric <NUM>. In an embodiment, the gate dielectric layer <NUM> is deposited by an ALD process to a thickness between <NUM> and <NUM>.

<FIG> illustrates the structure of <FIG> following the formation of a gate electrode <NUM> on the gate dielectric layer <NUM>. In an embodiment, the process to form the gate electrode <NUM> is the same or substantially the same as the process utilized to form gate electrode <NUM>. In an embodiment, a material of the gate electrode <NUM> is blanket deposited on gate dielectric layer <NUM> and a planarization is performed. In the illustrative embodiment, the planarization process isolates the gate electrode <NUM> but does not remove the gate dielectric layer <NUM>.

<FIG> illustrates the structure of <FIG> following the process to remove portions of gate dielectric layer <NUM>. In an embodiment, the gate dielectric layer is removed from above the hardmask <NUM>, dielectric <NUM>, from above portions of the dielectric <NUM> and channel layer <NUM> in region 1602A. In the illustrative embodiment, dielectric <NUM> and channel layer <NUM> in region 1602A are etched and removed after removing gate dielectric layer <NUM> in region 1602A. Openings <NUM> are formed in region <NUM> adjacent to region 1602B.

<FIG> illustrates the structure of <FIG> following the formation of source structure <NUM> adjacent to each channel <NUM> in region 1602B. In an embodiment, the source structure <NUM> includes a material such as the material of the line <NUM> to prevent barrier junction from forming between line <NUM> and the source structure <NUM>. The source structure may have a height that is above or below the conductive line <NUM>. The dielectric <NUM> is not shown in the illustration for clarity. While only the formation of the source structure 1616has been illustrated, a drain structure is formed on an opposite end of the source structure simultaneously during the fabrication process. Transistor <NUM> is an example of a fin-FET transistor and has one or more features of the transistor <NUM> described in association with <FIG>.

<FIG> is an isometric illustration of a system <NUM> where a memory device structure such as memory device structure <NUM> including a plurality of deck select transistors, is coupled by a plurality of logic decoder transistors and programming transistors. In the illustrative embodiment, line <NUM> and line <NUM> are coupled by decoder transistor <NUM> and <NUM>, respectively. While not shown, each line structure in the line structure <NUM> and <NUM> and deck <NUM> are coupled with a decoder transistor. In the illustrative embodiment, the line structures <NUM> and <NUM> are coupled to decoder transistors via the line structure <NUM> and <NUM>, respectively. In some such embodiments, the total number of decoder transistors such as decoder transistor <NUM> or <NUM> is equal to the total number of line structures in each of the plurality of lines structures <NUM> and <NUM>.

In the illustrative embodiment, each of the gate structures <NUM>, <NUM>, <NUM> and <NUM> are independently coupled with logic programming transistors <NUM>, <NUM>, <NUM> and <NUM>, respectively. In some such embodiments, the total number of programming transistors is equal to the total number of independent gate structures in the memory device structure <NUM>.

<FIG> is a block diagram of an example of a system <NUM> that includes a deck select transistor within a memory device structure to enable decoder transistor footprint scaling. System <NUM> represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, wearable computing device, or other mobile device, or an embedded computing device. It will be understood that certain of the components are shown generally, and not all components of such a device are shown in system <NUM>.

Memory <NUM> includes a memory device structure, such as for example memory device structure <NUM> of <FIG>. In one example, deck select transistors <NUM> represent deck select transistors in accordance with any example provided herein. The deck select transistors <NUM> enable memory <NUM> to provide selection of a target cell within the memory array. The use of the described deck select transistors enables selection with lower energy usage as compared to traditional decoder transistors.

System <NUM> includes processor <NUM>, which performs the primary processing operations of system <NUM>. Processor <NUM> can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting system <NUM> to another device, or a combination. The processing operations can also include operations related to audio I/O, display I/O, or other interfacing, or a combination. Processor <NUM> can execute data stored in memory. Processor <NUM> can write or edit data stored in memory.

In one example, system <NUM> includes one or more sensors <NUM>. Sensors <NUM> represent embedded sensors or interfaces to external sensors, or a combination. Sensors <NUM> enable system <NUM> to monitor or detect one or more conditions of an environment or a device in which system <NUM> is implemented. Sensors <NUM> can include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide, carbon dioxide, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiology sensors (e.g., biosensors, heart rate monitors, or other sensors to detect physiological attributes), or other sensors, or a combination. Sensors <NUM> can also include sensors for biometric systems such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user features. Sensors <NUM> should be understood broadly, and not limiting on the many different types of sensors that could be implemented with system <NUM>. In one example, one or more sensors <NUM> couples to processor <NUM> via a frontend circuit integrated with processor <NUM>. In one example, one or more sensors <NUM> couples to processor <NUM> via another component of system <NUM>.

In one example, system <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker or headphone output, as well as microphone input. Devices for such functions can be integrated into system <NUM>, or connected to system <NUM>. In one example, a user interacts with system <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes tactile components or touchscreen elements for a user to interact with the computing device. Display subsystem <NUM> includes display interface <NUM>, which includes the particular screen or hardware device used to provide a display to a user. In one example, display interface <NUM> includes logic separate from processor <NUM> (such as a graphics processor) to perform at least some processing related to the display. In one example, display subsystem <NUM> includes a touchscreen device that provides both output and input to a user. In one example, display subsystem <NUM> includes a high definition (HD) or ultra-high definition (UHD) display that provides an output to a user. In one example, display subsystem includes or drives a touchscreen display. In one example, display subsystem <NUM> generates display information based on data stored in memory or based on operations executed by processor <NUM> or both.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> can operate to manage hardware that is part of audio subsystem <NUM>, or display subsystem <NUM>, or both. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to system <NUM> through which a user might interact with the system. For example, devices that can be attached to system <NUM> might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> or display subsystem <NUM> or both. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of system <NUM>. Additionally, audio output can be provided instead of or in addition to display output. In another example, if display subsystem includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on system <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one example, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS), or other hardware that can be included in system <NUM>, or sensors <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one example, system <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation. Power management <NUM> manages power from power source <NUM>, which provides power to the components of system <NUM>. In one example, power source <NUM> includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion based power). In one example, power source <NUM> includes only DC power, which can be provided by a DC power source, such as an external AC to DC converter. In one example, power source <NUM> includes wireless charging hardware to charge via proximity to a charging field. In one example, power source <NUM> can include an internal battery or fuel cell source.

Memory subsystem <NUM> includes memory device(s) <NUM> for storing information in system <NUM>. Memory subsystem <NUM> can include nonvolatile (state does not change if power to the memory device is interrupted) or volatile (state is indeterminate if power to the memory device is interrupted) memory devices, or a combination. Memory <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether longterm or temporary) related to the execution of the applications and functions of system <NUM>. In one example, memory subsystem <NUM> includes memory controller <NUM> (which could also be considered part of the control of system <NUM>, and could potentially be considered part of processor <NUM>). Memory controller <NUM> includes a scheduler to generate and issue commands to control access to memory device <NUM>.

Connectivity <NUM> includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable system <NUM> to communicate with external devices. The external device could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. In one example, system <NUM> exchanges data with an external device for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory, or data already stored in memory, to read, write, or edit data.

Connectivity <NUM> can include multiple different types of connectivity. To generalize, system <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, LTE (long term evolution-also referred to as "<NUM>"), or other cellular service standards. Wireless connectivity <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth), local area networks (such as WiFi), or wide area networks (such as WiMax), or other wireless communication, or a combination. Wireless communication refers to transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs through a solid communication medium.

Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that system <NUM> could both be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. System <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading, uploading, changing, synchronizing) content on system <NUM>. Additionally, a docking connector can allow system <NUM> to connect to certain peripherals that allow system <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, system <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), or other type.

<FIG> is a block diagram of an example of a computing system that includes a deck select transistor within a memory device structure to enable decoder transistor footprint scaling. System <NUM> represents a computing device in accordance with any example herein, and can be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, embedded computing device, or other electronic device.

System <NUM> includes a memory device structure in memory <NUM>, such as for example memory device structure <NUM> of <FIG>. In one example, deck select transistors <NUM> represent deck select transistors in accordance with any example provided herein. The deck select transistors <NUM> enable memory <NUM> to provide selection of a target cell within the memory device structure. The use of the described deck select transistors enables selection with lower energy usage as compared to traditional decoder transistors.

System <NUM> includes processor <NUM> can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination, to provide processing or execution of instructions for system <NUM>. Processor <NUM> controls the overall operation of system <NUM>, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of such devices.

In one example, system <NUM> includes interface <NUM> coupled to processor <NUM>, which can represent a higher speed interface or a high throughput interface for system components that need higher bandwidth connections, such as memory subsystem <NUM> or graphics interface components <NUM>. Interface <NUM> represents an interface circuit, which can be a standalone component or integrated onto a processor die. Interface <NUM> can be integrated as a circuit onto the processor die or integrated as a component on a system on a chip. Where present, graphics interface <NUM> interfaces to graphics components for providing a visual display to a user of system <NUM>. Graphics interface <NUM> can be a standalone component or integrated onto the processor die or system on a chip. In one example, graphics interface <NUM> can drive a high definition (HD) display that provides an output to a user. In one example, the display can include a touchscreen display. In one example, graphics interface <NUM> generates a display based on data stored in memory <NUM> or based on operations executed by processor <NUM> or both.

Memory subsystem <NUM> represents the main memory of system <NUM> and provides storage for code to be executed by processor <NUM>, or data values to be used in executing a routine. Memory subsystem <NUM> can include one or more memory devices <NUM> such as readonly memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM or other memory devices, or a combination of such devices. In some embodiments memory subsystem <NUM> includes persistent memory (PMem) which may offer higher RAM capacity than traditional DRAM. PMem may operate in a persistent mode, i.e., utilizing non-volatile devices (e.g., RRAM, PCM, CBRAM etc.) integrated with selectors in a tier architecture, to store data without power applied to the memory subsystem <NUM> for nonvolatile data storage. In other embodiments, memory subsystem <NUM> includes solid state drives (SSDs), residing in a NAND package for fast storage.

Memory <NUM> stores and hosts, among other things, operating system (OS) <NUM> to provide a software platform for execution of instructions in system <NUM>. Additionally, applications <NUM> can execute on the software platform of OS <NUM> from memory <NUM>. Applications <NUM> represent programs that have their own operational logic to perform execution of one or more functions. Processes <NUM> represent agents or routines that provide auxiliary functions to OS <NUM> or one or more applications <NUM> or a combination. OS <NUM>, applications <NUM>, and processes <NUM> provide software logic to provide functions for system <NUM>. In one example, memory subsystem <NUM> includes memory controller <NUM>, which is a memory controller to generate and issue commands to memory <NUM>. It will be understood that memory controller <NUM> could be a physical part of processor <NUM> or a physical part of interface <NUM>. For example, memory controller <NUM> can be an integrated memory controller, integrated onto a circuit with processor <NUM>, such as integrated onto the processor die or a system on a chip.

While not specifically illustrated, it will be understood that system <NUM> can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or other bus, or a combination.

In one example, system <NUM> includes interface <NUM>, which can be coupled to interface <NUM>. Interface <NUM> can be a lower speed interface than interface <NUM>. In one example, interface <NUM> represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface <NUM>. Network interface <NUM> provides system <NUM> the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface <NUM> can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface <NUM> can exchange data with a remote device, which can include sending data stored in memory or receiving data to be stored in memory.

In one example, system <NUM> includes one or more input/output (I/O) interface(s) <NUM>. I/O interface <NUM> can include one or more interface components through which a user interacts with system <NUM> (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface <NUM> can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system <NUM>. A dependent connection is one where system <NUM> provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system <NUM> includes storage subsystem <NUM> to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage <NUM> can overlap with components of memory subsystem <NUM>. Storage subsystem <NUM> includes storage device(s) <NUM>, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage <NUM> holds code or instructions and data <NUM> in a persistent state (i.e., the value is retained despite interruption of power to system <NUM>). Storage <NUM> can be generically considered to be a "memory," although memory <NUM> is typically the executing or operating memory to provide instructions to processor <NUM>. Whereas storage <NUM> is nonvolatile, memory <NUM> can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system <NUM>). In one example, storage subsystem <NUM> includes controller <NUM> to interface with storage <NUM>. In one example controller <NUM> is a physical part of interface <NUM> or processor <NUM> or can include circuits or logic in both processor <NUM> and interface <NUM>.

Claim 1:
A memory device structure (<NUM>) comprising:
a first deck (<NUM>), wherein the first deck (<NUM>) comprises:
a first plurality of line structures (<NUM>), wherein individual ones of the first plurality of line structures (<NUM>) each comprise a first transistor channel (<NUM>, <NUM>);
a second plurality of line structures (<NUM>) substantially orthogonal to the first plurality of line structures (<NUM>), wherein individual ones of the second plurality of line structures (<NUM>) each comprise a second transistor channel (<NUM>, <NUM>); and
a memory cell (<NUM>, <NUM>, <NUM>) at each cross-point between the first plurality of line structures (<NUM>) and the second plurality of line structures (<NUM>); and
a second deck (<NUM>) above or below the first deck (<NUM>), wherein the second deck (<NUM>) comprises:
a third plurality of line structures (<NUM>) substantially parallel to the first plurality of line structures (<NUM>), wherein individual ones of the third plurality of line structures (<NUM>) each comprise a third transistor channel (<NUM>, <NUM>);
a fourth plurality of line structures (<NUM>) substantially parallel to the second plurality of line structures (<NUM>), wherein individual ones of the fourth plurality of line structures (<NUM>) each comprise a fourth transistor channel (<NUM>, <NUM>); and
a memory cell (<NUM>, <NUM>, <NUM>)
at each cross-point between the third plurality of line structures (<NUM>) and the fourth plurality of line structures (<NUM>),
characterised in that the memory device structure (<NUM>) further comprises a plurality of terminal interconnects (<NUM>, <NUM>) between the first deck (<NUM>) and the second deck (<NUM>), wherein individual ones of the plurality of terminal interconnects (<NUM>, <NUM>) are coupled between the individual ones of the line structures (<NUM>), (<NUM>) in the first deck (<NUM>) and corresponding individual ones of the line structures (<NUM>), (<NUM>) in the second deck (<NUM>); and
wherein individual ones of the transistor channels (<NUM>, <NUM>, <NUM>, <NUM>) are between individual ones of the terminal interconnects (<NUM>, <NUM>) and the memory cells (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>).