Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit designs, programming algorithms, and the fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. A typical 3D memory architecture includes a stack of gate electrodes arranged over a substrate, with a plurality of semiconductor channels through and intersecting word lines into the substrate. The intersection of a word line and a semiconductor channel forms a memory cell.

The 3D memory architecture requires an electrical contact scheme to allow the control of each individual memory cells. One electrical contact scheme is to form a staircase structure to connect to word lines of each individual memory cells. Staircase structures have been used to connect more than <NUM> word lines along a semiconductor channel in a typical 3D memory device.

As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, keep scaling more oxide/nitride (ON) layers. As a result, the existing multicycle etch and trim processes used to form such staircase structures suffer a low throughput and are expensive.

<CIT> discloses a channel structure region, wherein a first staircase region having a plurality of division block structures is arranged at the channel structure region. The different division block structures also have different heights with respect to the channel structure region.

<CIT> discloses a three-dimensional storage part and its manufacturing method.

Embodiments of contact structures for three-dimensional memory devices and methods for forming the same are described in the present disclosure.

A method for forming a three-dimensional (3D) memory device according to the invention is presented in claim <NUM>.

Embodiments of the invention are presented in the dependent claims.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of "on," "above," and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on" something, but also includes the meaning of "on" something with an intermediate feature or a layer therebetween. Moreover, "above" or "over" not only means "above" or "over" something, but can also include the meaning it is "above" or "over" something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process step in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

The substrate includes a top surface and a bottom surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate unless stated otherwise. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate.

A layer has a top side and a bottom side where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the extent of an underlying or overlying structure. For example, a layer can be located between any set of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

As used herein, the term "nominal/nominally" refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value.

In the present disclosure, the term "horizontal/horizontally/lateral/laterally" means nominally parallel to a lateral surface of a substrate. In the present disclosure, the term "each" may not only necessarily mean "each of all," but can also mean "each of a subset.

As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate.

In the present disclosure, for ease of description, "tier" is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as "a tier," a word line and the underlying insulating layer can together be referred to as "a tier," word lines of substantially the same height can be referred to as "a tier of word lines" or similar, and so on.

In some embodiments, a memory string of a 3D memory device includes a semiconductor pillar (e.g., silicon channel) that extends vertically through a plurality of conductive and dielectric layer pairs. The plurality of conductive and dielectric layer pairs are also referred to herein as an "alternating conductive and dielectric stack. " An intersection of the conductive layer and the semiconductor pillar can form a memory cell. The conductive layer of the alternating conductive and dielectric stack can be connected to a word line at the back-end-of-line, wherein the word line can electrically connect to one or more control gates. For illustrative purposes, word lines and control gates are used interchangeably to describe the present disclosure. The top of the semiconductor pillar (e.g., transistor drain region) can be connected to a bit line (electrically connecting one or more semiconductor pillars). Word lines and bit lines are typically laid perpendicular to each other (e.g., in rows and columns, respectively), forming an "array" of the memory, also called a memory "block" or an "array block".

A memory "die" may have one or more memory "planes", and each memory plane may have a plurality of memory blocks. An array block can also be divided into a plurality of memory "pages", wherein each memory page may have a plurality of memory strings. In a flash NAND memory device, erase operation can be performed for every memory block and read/write operation can be performed for every memory page. The array blocks are the core area in a memory device, performing storage functions. To achieve higher storage density, the number of vertical 3D memory stacks is increased greatly, adding complexity and cost in manufacturing.

A memory die has another region, called the periphery, which provides supporting functions to the core. The periphery region includes many digital, analog, and/or mixed-signal circuits, for example, row and column decoders, drivers, page buffers, sense amplifiers, timing and controls, and the like circuitry. Peripheral circuits use active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art.

In 3D memory device architectures, memory cells for storing data are vertically stacked to form a stacked storage structure. 3D memory devices can include a staircase structure formed on one or more sides of the stacked storage structure for purposes such as word line fan-out, where the stacked storage structure includes a plurality of semiconductor channels, where the semiconductor channels can be vertical or horizontal. As the demand for higher storage capacity continues to increase, the number of vertical levels of the stacked storage structure also increases. Accordingly, a thicker mask layer, such as photoresists (PR) layer, is needed to etch the staircase structure with increased levels. However, the increase of thickness of the mask layer can make the etch control of the staircase structure more challenging.

In the present disclosure, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. Each of the horizontal surfaces is referred as a "step" or "staircase" of the staircase structure. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with a top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.

A staircase structure can be formed from a dielectric stack layer by repetitively etching the dielectric stack layer using a mask layer formed over the dielectric stack layer. In some embodiments, the mask layer can include a photoresist (PR) layer. In the present disclosure, the dielectric stack layer includes a plurality of alternatively arranged dielectric layer pairs, and the thickness of each dielectric layer pair is one level. In other words, each of the dielectric layer pair is one level high vertically. In the present disclosure, term "step" refers to one level of a staircase structure, and term "staircase" refers to two or more levels of a staircase structure. A step (or staircase) exposes a portion of a surface of a dielectric layer pair. In some embodiments, each dielectric layer pair includes a first material layer and a second material layer. In some embodiments, the first material layer includes an insulating material layer. In some embodiments, the second material includes a sacrificial material layer which is to be replaced by a conductive material layer. In some embodiments, each dielectric layer pair can have nominally the same height over the substrate so that one set can form one step.

During the formation of the staircase structure, the mask layer is trimmed (e.g., etched incrementally and inwardly from the boundary of the dielectric stack layer) and used as the etch mask for etching the exposed portion of the dielectric stack. The amount of trimmed mask layer can be directly relevant (e.g., determinant) to the dimensions of the staircases. The trimming of the mask layer can be obtained using a suitable etch, e.g., an isotropic dry etch or a wet etch. One or more mask layers can be formed and trimmed consecutively for the formation of the staircase structure. Each dielectric layer pair can be etched, after the trimming of the mask layer, using suitable etchants to remove a portion of both the first material layer and the second material layer.

In some embodiments, the formed staircase structure can include multiple division block structures each including multiple staircases, and each staircase can include multiple steps. The multiple division block structures, multiple staircases, and multiple steps can be arranged along different directions. As such, the 3D space of the staircase structure can be efficiently used to form a large number of steps. During the fabricating process of the disclosed staircase structure can reduce a thickness of masks to be used, a number of masks to be used, and a number of trimming processes, thereby increasing a number of etching wafers per hour (WPH).

After the formation of the staircase structure, the mask layer can be removed. In some embodiments, the second material layers are conductive material layers, and therefore can be gate electrodes (or word lines) of the 3D memory structure. In some embodiments, the second material layers of the staircase structure are sacrificial material layers and can then be replaced with metal/conductor layers (e.g., tungsten) to form the gate electrodes (or word lines) of the 3D memory structure. As such, the multiple dielectric layer pairs can become dielectric/conductive layer pairs.

The staircase structure can provide an interconnection scheme as word line fan-out to control the semiconductor channels after an interconnect formation process. Each of the dielectric/conductive layer pairs in the staircase structure intersect to a portion of a semiconductor channel. Each of the conductive material layers in the staircase structure can control the portion of the semiconductor channel. An example of an interconnect formation process includes disposing or otherwise depositing, a second insulating material, such as silicon oxide, spin-on-dielectric, or borophosphosilicate glass (BPSG), over the staircase structure and planarizing the second insulating material. Each of the conductive material layers in the staircase structure is exposed to open a plurality of contact holes in the planarized second insulating material and the contact holes are filled with one or more conductive materials, such as titanium nitride and tungsten, to form a plurality of VIA (Vertical Interconnect Access) structures.

Other parts of the memory devices are not discussed for ease of description. In the present disclosure, a "memory device" is a general term and can be a memory chip (package), a memory die or any portion of a memory die.

Although using three-dimensional NAND devices as examples, in various applications and designs, the disclosed structures can also be applied in similar or different semiconductor devices to, e.g., to improve metal connections or wiring. The specific application of the disclosed structures should not be limited by the embodiments of the present disclosure.

<FIG> illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure <NUM>, in accordance with some embodiments. The memory array structure <NUM> includes a substrate <NUM>, an insulating film <NUM> over the substrate <NUM>, a tier of lower select gates (LSGs) <NUM> over the insulating film <NUM>, and a plurality of tiers of control gates <NUM>, also referred to as "word lines (WLs)," stacking on top of the LSGs <NUM> to form a film stack <NUM> of alternating conductive and dielectric layers. The dielectric layers adjacent to the tiers of control gates <NUM> are not shown in <FIG> for clarity.

The control gates <NUM> of each tier are separated by slit structures <NUM>-<NUM> and <NUM>-<NUM> through the film stack <NUM>. The memory array structure <NUM> also includes a tier of top select gates (TSGs) <NUM> over the stack of control gates <NUM>. The stack of TSG <NUM>, control gates <NUM> and LSG <NUM> is also referred to as "gate electrodes. " The memory array structure <NUM> further includes doped source line regions <NUM> in portions of substrate <NUM> between adjacent LSGs <NUM>. The memory array structure <NUM> can include a channel structure region <NUM> and two staircase regions <NUM>, <NUM> on both sides of the channel structure region <NUM>. The channel structure region <NUM> can include an array of memory strings <NUM>, each including a plurality of stacked memory cells <NUM>.

Each memory strings <NUM> includes a channel hole <NUM> extending vertically through the insulating film <NUM> and the film stack <NUM> of alternating conductive and dielectric layers. Memory strings <NUM> also includes a memory film <NUM> on a sidewall of the channel hole <NUM>, a channel layer <NUM> over the memory film <NUM>, and a core filling film <NUM> surrounded by the channel layer <NUM>. A memory cell <NUM> can be formed at the intersection of the control gate <NUM> and the memory string <NUM>. The memory array structure <NUM> further includes a plurality of bit lines (BLs) <NUM> connected to the memory strings <NUM> over the TSGs <NUM>.

The memory array structure <NUM> also includes a plurality of metal interconnect lines <NUM> connected to the gate electrodes through a plurality of contact structures <NUM>. In the two staircase regions <NUM> and <NUM>, the edge of the film stack <NUM> is configured in a staircase structure to allow an electrical connection to each tier of the gate electrodes. In some embodiments, a staircase structure can include a set of horizontal surfaces (e.g., along x-y plane) that have distances among each other in the vertical direction (e.g., along z-axis, or z-direction). For illustrative purposes, <FIG> only shows that the steps are configured along x-direction to gradually decrease the heights of the horizontal surfaces along z-direction. It is noted that, multiple steps in the staircase regions <NUM> and <NUM> can be configured in both x-direction and y-direction to increase and/or decrease the heights of the horizontal surfaces along z-direction. An exemplary configuration of multiple steps in staircase regions <NUM> and <NUM> will be further described in details below in connection with the following figures.

It is also noted that, in <FIG>, for illustrative purposes, three tiers of control gates <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are shown together with one tier of TSG <NUM> and one tier of LSG <NUM>. In this example, each memory string <NUM> can include three memory cells <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, corresponding to the control gates <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure <NUM> can also include other structures, for example, through array contact, TSG cut, common source contact and dummy channel structure. These structures are not shown in <FIG> for simplicity.

With the demand for higher storage capacity in a NAND flash memory, the number of vertical tiers of 3D memory cells <NUM> or word lines <NUM> increases accordingly, leading to more process complexity and higher manufacturing cost. When increasing the tiers of memory cells <NUM> or word lines <NUM> of the memory array structure <NUM>, it becomes more challenging to form multiple steps in one direction in the staircase structures and also more challenging to form contact structures <NUM> on the staircase structures.

For example, to form the contact structures <NUM> on a large number of vertically stacked word lines (gate electrodes), a high aspect ratio etching is needed to form contact holes. During prolonged high aspect ratio etching, the critical dimension (CD) of the contact holes on the lower level of the staircase structure can be much larger than the CD of contact holes on the top level of the staircase structure. In addition, profile of contact holes on the lower level of the staircase structure can have large bowing. Large CD bias and bowing profile among contact structures not only creates memory performance variation due to metal loading difference, but may also cause yield loss due to electrical shorts between neighboring contact structures.

As another example, in some existing memory array structure, one of the two staircase regions <NUM> and <NUM> is normally used as a dummy staircase region, which is not used for memory cell gate connection. That is, the multiple contact holes are formed in only one of the two staircase regions <NUM> and <NUM>. Thus, the unitization efficiency of the staircase structures is only <NUM>%. Further, using only one of the two staircase regions <NUM> and <NUM> reduces the division structure in y-direction of the staircase structure by half, resulting in more required masks.

Therefore, in the present disclosure, staircase structures with multiple divisions and fabrication methods thereof for a 3D memory device are disclosed to address the above challenges. Referring to <FIG>, a flow diagram of an exemplary method <NUM> for forming a 3D memory device including staircase structures with multiple divisions is illustrated in accordance with some embodiments. The process operations shown in method <NUM> are not exhaustive and other process operations can be performed as well before, after, or between any of the illustrated process operations. In some embodiments, some process operations of exemplary method <NUM> can be omitted or include other process operations that are not described here for simplicity. In some embodiments, process operations of method <NUM> can be performed in a different order and/or vary. <FIG> illustrate schematic views of various structures of an exemplary 3D memory device at certain fabricating stages of the method <NUM> shown in <FIG>, according to some embodiments of the present disclosure.

As shown in <FIG>, method <NUM> can start at S210, in which a film stack including multiple alternating dielectric layer pairs can be disposed on a substrate. <FIG> illustrates a cross-sectional view of an exemplary structure <NUM> of a 3D memory device, according to some embodiments, wherein the structure <NUM> includes a substrate <NUM> and a film stack <NUM>. The cross-sectional view of <FIG> is along WL direction (or x-direction) in <FIG>.

The substrate <NUM> can provide a platform for forming subsequent structures. In some embodiments, the substrate <NUM> can be any suitable semiconductor substrate having any suitable structure, such as a monocrystalline single-layer silicon substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc. The substrate <NUM> can include any other suitable material, for example, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), glass, gallium nitride, gallium arsenide, III-V compound, and/or any combinations thereof.

A front surface 130f of the substrate <NUM> is also referred to as a "main surface" or a "top surface" of the substrate herein. Layers of materials can be disposed on the front surface 130f of the substrate. A "topmost" or "upper" layer is a layer farthest or farther away from the front surface 130f of the substrate. A "bottommost" or "lower" layer is a layer closest or closer to the front surface 130f of the substrate. In some embodiments, the substrate <NUM> can further include an insulating film on the front surface 130f.

The film stack <NUM> extends in a lateral direction that is parallel to the front surface 130f of the substrate <NUM>. The film stack <NUM> includes a dielectric layer <NUM> (also referred to as "first dielectric layer") and a sacrificial layer <NUM> (also referred to as "second dielectric layer") alternatingly stacked on each other, wherein the dielectric layer <NUM> can be configured to be the bottommost and the topmost layers of the film stack <NUM>. In this configuration, each sacrificial layer <NUM> can be sandwiched between two dielectric layers <NUM>, and each dielectric layer <NUM> can be sandwiched between two sacrificial layers <NUM> (except the bottommost and the topmost layer).

The dielectric layer <NUM> and the underlying sacrificial layer <NUM> are also referred to as an alternating dielectric layer pair <NUM>. The formation of the film stack <NUM> can include disposing the dielectric layers <NUM> to each have the same thickness or to have different thicknesses. Example thicknesses of the dielectric layers <NUM> can range from <NUM> to <NUM>. Similarly, the sacrificial layer <NUM> can each have the same thickness or have different thicknesses. Example thicknesses of the sacrificial layer <NUM> can range from <NUM> to <NUM>. Although only <NUM> total layers are illustrated in the film stack <NUM> in <FIG>, it should be understood that this is for illustrative purposes only and that any number of layers may be included in the film stack <NUM>. In some embodiments, the film stack <NUM> can include layers in addition to the dielectric layer <NUM> and the sacrificial layer <NUM>, and can be made of different materials and with different thicknesses.

In some embodiments, the dielectric layer <NUM> includes any suitable insulating materials, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS or silicon oxide with F-, C-, N-, and/or H- incorporation. The dielectric layer <NUM> can also include high-k dielectric materials, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide films. The formation of the dielectric layer <NUM> on the substrate <NUM> can include any suitable deposition methods such as, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density-plasma CVD (HDP-CVD), thermal oxidation, nitridation, any other suitable deposition method, and/or combinations thereof.

In some embodiments, the sacrificial layer <NUM> includes any suitable material that is different from the dielectric layer <NUM> and can be removed selectively. For example, the sacrificial layer <NUM> can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon, and any combinations thereof. In some embodiments, the sacrificial layer <NUM> also includes amorphous semiconductor materials, such as amorphous silicon or amorphous germanium. The sacrificial layer <NUM> can be disposed using a similar technique as the dielectric layer <NUM>, such as CVD, PVD, ALD, thermal oxidation or nitridation, or any combination thereof.

In some embodiments, the sacrificial layer <NUM> can be replaced by a conductive layer, wherein the conductive layer can include any suitable conductive material, for example, poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon, or any combination thereof. In some embodiments, the conductive layer can also include amorphous semiconductor materials, such as amorphous silicon, amorphous germanium or any combination thereof. In some embodiments, the poly-crystalline or amorphous material of the conductive layer can be incorporated with any suitable type of dopant, such as boron, phosphorous, or arsenic, to increase the conductivity of the material. The formation of the conductive layer can include any suitable deposition methods such as, CVD, RTCVD, PECVD, LPCVD, MOCVD, HDP-CVD, PVD, ALD or any combination thereof. In some embodiments, poly-crystalline semiconductor material can be deposited in an amorphous state and converted to poly-crystalline through subsequent thermal treatments. In some embodiments, the dopants in the conductive layer can be incorporated through in-situ doping as the poly-crystalline or amorphous semiconductor material being deposited, by simultaneously flowing chemical gas, for example, diborane (B<NUM>H<NUM>) or phosphine (PH<NUM>). Other doping techniques for 3D structure, such as plasma doping, can also be used to increase conductivity of the conductive layer. In some embodiments, after dopant incorporation, a high temperature annealing process can be performed to active the dopants in the conductive layer. In some embodiments, the dielectric layer <NUM> can be silicon oxide and the conductive layer can be poly-crystalline silicon. In the present disclosure, the sacrificial layer <NUM> is illustrated as an example. However, a person skilled in the art can replace the sacrificial layer <NUM> with the conductive layer for the structures and methods described below.

In some embodiments, along the x-direction as shown in <FIG>, the structure <NUM> of the 3D memory device can include a channel structure region <NUM> and two staircase regions <NUM>, <NUM> on both sides of the channel structure region <NUM>. The channel structure region <NUM> can be used for forming an array of memory strings each including a plurality of stacked memory cells, as described above in connection with <FIG>. The two staircase regions <NUM> and <NUM> can be used for forming a staircase structure in the subsequent processes described in details below. It is noted that, for illustrative purpose, the width of the channel structure region <NUM> is less than the widths of the two staircase regions <NUM> and <NUM> in <FIG>. However, the dimension relationship between different components as shown in <FIG> does not limit the scope of the present disclosure.

Referring back to <FIG>, method <NUM> can proceed to operation S220, in which a top select gate staircase can be formed adjacent to a first staircase region, resulting in a vertical offset in the z-direction between the first staircase region and the second staircase region. <FIG> illustrates a top view of exemplary masks used in operations S220 and S230 according to some embodiments, and <FIG> illustrates a perspective view a structure <NUM> of the 3D memory device after operations S220 and S230 according to some embodiments.

As shown in <FIG>, in some embodiments, operation S220 can include forming a top step <NUM> in the channel structure region <NUM>. As shown in <FIG>, a first staircase mask <NUM> can be used to cover the channel structure region <NUM> and to expose the first and second staircase regions <NUM> and <NUM>. In some embodiments, the first staircase mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the first staircase mask <NUM> can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O<NUM> or CF<NUM> chemistry. Furthermore, the first staircase mask <NUM> can include any combination of photoresist and hard mask.

An etching process can be performed to remove at least one alternating dielectric layer pair <NUM> from the top in both exposed first and second staircase regions <NUM> and <NUM>. The etch depth is determined by a thickness of the top step <NUM>. In some embodiments, the thickness of the top step <NUM> can be a thickness of one alternating dielectric layer pair <NUM>. In this example, the etching process for the dielectric layer <NUM> can have a high selectivity over the sacrificial layer <NUM>, and/or vice versa. Accordingly, an underlying alternating dielectric layer pair <NUM> can function as an etch-stop layer. And as a result, the top step <NUM> can be formed in the channel structure region <NUM>, as shown in <FIG>.

In some embodiments, the top step <NUM> can be etched using an anisotropic etching such as a reactive ion etch (RIE) or other dry etching processes. In some embodiments, the dielectric layer <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layer <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to remove a single layer should not be limited by the embodiments of the present disclosure. In some embodiments, after the etching process, the first staircase mask <NUM> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

As shown in <FIG>, in some embodiments, operation S220 can further include forming a top select gate (TSG) staircase structure <NUM> at one edge of the channel structure region <NUM> adjacent to the first staircase region <NUM>. In some embodiments, the TSG staircase structure <NUM> can include three steps <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> that are configured along the x-direction.

As shown in <FIG>, a second staircase mask <NUM> can be used to cover the channel structure region <NUM> and the second staircase region <NUM> initially, and to expose the first staircase region <NUM>. In some embodiments, the second staircase mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the second staircase mask <NUM> can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O<NUM> or CF<NUM> chemistry. Furthermore, the second staircase mask <NUM> can include any combination of photoresist and hard mask.

The TSG staircase structure <NUM> can be formed by applying a repetitive etch-trim process (e.g., a three-time etch-trim process) on the film stack <NUM> in the exposed first staircase region <NUM> using the second staircase mask <NUM>. The etch-trim process includes an etching process and a trimming process. During the etching process, at least one alternating dielectric layer pair <NUM> from the top in the exposed first staircase region <NUM> can be removed. The etch depth is determined by a thickness of each step of the TSG staircase structure <NUM>. In some embodiments, the thickness of each step of the TSG staircase structure <NUM> can be a thickness of one alternating dielectric layer pair <NUM>. In this example, the etching process for the dielectric layer <NUM> can have a high selectivity over the sacrificial layer <NUM>, and/or vice versa. Accordingly, an underlying alternating dielectric layer pair <NUM> can function as an etch-stop layer. And as a result, one step (e.g., <NUM>-<NUM>, <NUM>-<NUM>, or <NUM>-<NUM>) of the TSG staircase structure <NUM> can be formed during each etch-trim cycle.

In some embodiments, each step (e.g., <NUM>-<NUM>, <NUM>-<NUM>, or <NUM>-<NUM>) of the TSG staircase structure <NUM> can be etched using an anisotropic etching such as a reactive ion etch (RIE) or other dry etching processes. In some embodiments, the dielectric layer <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layer <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to remove a single layer should not be limited by the embodiments of the present disclosure.

The trimming process includes applying a suitable etching process (e.g., an isotropic dry etch or a wet etch) on the second staircase mask <NUM> such that the second staircase mask <NUM> can be pulled back laterally, in directions in the x-y plane, parallel to the front surface 130f of the substrate <NUM>. From the top-down view in <FIG>, the second staircase mask <NUM> can be etched incrementally and inwardly from initial pattern defined by, for example, photoresist from lithography. In this example, the initial edge <NUM>-<NUM> of the second staircase mask <NUM> can be trimmed incrementally towards a second edge <NUM>-<NUM> and then towards to a third edge <NUM>-<NUM>. The lateral pull-back dimension in the x-direction at etch trimming process determines the lateral dimension of each step of the TSG staircase structure <NUM> in the x-direction. In some embodiments, each step of the TSG staircase structure <NUM> can have a different or same lateral dimension in the x-direction.

In some embodiments, trimming of the second staircase mask <NUM> can be isotropic in all directions in the x-y plane. In some embodiments, the lateral dimension of each step of the TSG staircase structure <NUM> in the x-direction can be between <NUM> and <NUM>. In some embodiments, the trimming process can include dry etching, such as RIE using O<NUM>, Ar, N<NUM>, etc. After trimming the second staircase mask <NUM>, one portion of the topmost surface of the top step <NUM> is exposed and the other potion of the top step <NUM> remains covered by the second staircase mask <NUM>. The next cycle of etch-trim process resumes with the etching process.

By repeating etch-trim process three times, three steps <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of the TSG staircase structure <NUM> can be formed from top to bottom between the top step <NUM> and the first staircase region <NUM>. During etch-trim process, some of the second staircase mask <NUM> may be consumed, and the thickness of the second staircase mask <NUM> may be reduced. After forming the TSG staircase structure <NUM>, the second staircase mask <NUM> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

Referring back to <FIG>, method <NUM> can proceed to operation S230, in which a first division step structure can be formed in the first staircase region and a second division step structure can be formed in the second staircase region. In some embodiments, as shown in <FIG>, the first division step structure <NUM> in the first staircase region <NUM> can be lower than the second division step structure <NUM> in the second staircase region <NUM> by three steps due to the TSG staircase structure <NUM>.

In some embodiments, a first staircase division pattern mask <NUM> can be used to form the first division step structure <NUM> and the second division step structure <NUM>. As shown in <FIG>, the first staircase division pattern (SDP) mask <NUM> can be used to cover the channel structure region <NUM> and a portion of the two staircase regions <NUM> and <NUM> adjacent to the channel structure region <NUM>, and to expose other portions of the two staircase regions <NUM> and <NUM>. The first staircase division pattern mask <NUM> can include multiple first division block patterns <NUM> extended in the x-direction into both staircase regions <NUM> and <NUM>, and arranged along the y-direction. In <FIG>, two first division block patterns <NUM> are shown in each side as an example. In some other embodiments, the first staircase division pattern mask <NUM> can include a number X<NUM> of first division block patterns <NUM> in each side, where X<NUM> is an integer equal to or larger than <NUM> (e.g., <NUM>, <NUM>, <NUM>, etc.).

In some embodiments, the first staircase division pattern mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the first staircase division pattern mask <NUM> can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O<NUM> or CF<NUM> chemistry. Furthermore, the first staircase division pattern mask <NUM> can include any combination of photoresist and hard mask.

The first division step structure <NUM> and the second division step structure <NUM> can be formed by applying a two-time etch-trim process on the film stack <NUM> in the first staircase region <NUM> and the second staircase region <NUM> by using the first staircase division pattern mask <NUM>. The etch-trim process includes an etching process and a trimming process. During the etching process, a portion of the film stack <NUM> with exposed surface can be removed. The etch depth is determined by a thickness of each step of the first division step structure <NUM> and the second division step structure <NUM>. In some embodiments, the thickness of step can be a thickness of one alternating dielectric layer pair <NUM>. In this example, the etching process for the dielectric layer <NUM> can have a high selectivity over the sacrificial layer <NUM>, and/or vice versa. Accordingly, an underlying alternating dielectric layer pair <NUM> can function as an etch-stop layer. And as a result, one step can be formed during each etch-trim cycle.

In some embodiments, the step of the first division step structure <NUM> and the second division step structure <NUM> can be etched using an anisotropic etching such as a reactive ion etch (RIE) or other dry etching processes. In some embodiments, the dielectric layer <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layer <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to remove a single layer should not be limited by the embodiments of the present disclosure.

The trimming process includes applying a suitable etching process (e.g., an isotropic dry etch or a wet etch) on the first staircase division pattern mask <NUM> such that the first staircase division pattern mask <NUM> can be pulled back laterally, in directions in the x-y plane, parallel to the front surface 130f of the substrate <NUM>. In some embodiments, the trimming process can include dry etching, such as RIE using O<NUM>, Ar, N<NUM>, etc. From the top-down view in <FIG>, the first staircase division pattern mask <NUM> can be etched inwardly from an initial edge <NUM>-<NUM> towards a final edge <NUM>-<NUM> in both of the first staircase region <NUM> and the second staircase region <NUM>. The lateral pull-back dimension at etch trimming process determines the lateral dimension of each step of the first division step structure <NUM> and the second division step structure <NUM>.

In some embodiments, each step of the first division step structure <NUM> and the second division step structure <NUM> can have a different or same lateral dimension in the x-direction and/or the y-direction. In some embodiments, trimming of the first staircase division pattern mask <NUM> can be isotropic in all directions in the x-y plane such that the widths of each step in the x-direction and the y-direction can be the same, and in a range between <NUM> and <NUM>.

By repeating etch-trim process two times, the first division step structure <NUM> including three steps <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> can be formed in the first staircase region <NUM>, and the second division step structure <NUM> including three steps <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> can be formed in the second staircase region <NUM>, as shown in <FIG>. The step <NUM>-<NUM> of the first division step structure <NUM> is lower than the step <NUM>-<NUM> of the second division step structure <NUM> by three steps. The step <NUM>-<NUM> of the first division step structure <NUM> is lower than the step <NUM>-<NUM> of the second division step structure <NUM> by three steps. The step <NUM>-<NUM> of the first division step structure <NUM> is lower than the step <NUM>-<NUM> of the second division step structure <NUM> by three steps.

It is noted that, the step difference along the z-direction is determined by number of steps of the TSG staircase structure <NUM>. In some embodiments, if the number of steps of the TSG staircase structure <NUM> is X<NUM>, which is an integer larger or equal to <NUM>. In such case, a same number X<NUM> of steps are formed in each of the first division step structure <NUM> and the second division step structure <NUM> respectively. That is, the number of the first steps in the first division step structure <NUM> and the second division step structure <NUM> is not limited.

As shown in <FIG>, the first division step structure <NUM> and the second division step structure <NUM> can each include two initial division block structures <NUM> respectively that are extended along the x-direction and periodically arranged along the y-direction. Each initial division block structure <NUM> corresponds to one first division block pattern <NUM>, and can be used to form a division staircase block structure in the subsequent processes. It is noted that, the number of initial division block structures <NUM> in the first division step structure <NUM> or in the second division step structure <NUM> can be determined by the number X<NUM> of the first division block patterns <NUM> of the first staircase division pattern mask <NUM>, such as <NUM>, <NUM>, <NUM>, etc..

During the etch-trim process, some of the first staircase division pattern mask <NUM> may be consumed, and the thickness of the first staircase division pattern mask <NUM> may be reduced. After the etch-trim process, the first staircase division pattern mask <NUM> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

Referring back to <FIG>, method <NUM> can proceed to operation S240, in which multiple staircases can be formed in the first division step structure and the second division step structure. <FIG> illustrates a top view of exemplary masks used in operations S220-S240 according to some embodiments, and <FIG> illustrates a perspective view a structure <NUM> of the 3D memory device after operation S240 according to some embodiments.

As shown in <FIG>, the staircases (e.g., <NUM>, <NUM>, <NUM>, <NUM>, etc.) can be arranged along the x-direction. Each staircase can include multiple steps (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, etc.) that are arranged along the y-direction. It is noted that, the staircases <NUM>, <NUM>, <NUM>, <NUM>, etc. are arranged alternatively in the first staircase region <NUM> and the second staircase region <NUM> respectively. Thus, in some embodiments as shown in <FIG>, the adjacent staircases (e.g., <NUM> and <NUM>. <NUM> and <NUM>, etc.) have a vertical offset in the z-direction of six steps. That is, if the number of steps of the TSG staircase structure <NUM> is X<NUM>, the adjacent steps along the x-direction (e.g., <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, etc.) have a vertical offset in the z-direction of a number 2X<NUM> of steps, and the adjacent steps along the y-direction (e.g., <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, etc.) have a vertical offset in the z-direction of one step.

In some embodiments, the multiple staircases <NUM>, <NUM>, <NUM>, <NUM>, etc. can be formed by using a third staircase mask <NUM> disposed over the channel structure region <NUM> and a portion of the first staircase region <NUM> and the second staircase region <NUM>. As shown in <FIG>, the third staircase mask <NUM> includes two initial edges <NUM>-<NUM> that cover a portion of the first division step structures <NUM> in the first staircase region <NUM> and the second division step structures <NUM> in the second staircase region <NUM>, and both extend in parallel along the y-direction.

In some embodiments, the third staircase mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the third staircase mask <NUM> can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O<NUM> or CF<NUM> chemistry. Furthermore, the second staircase mask <NUM> can include any combination of photoresist and hard mask.

The multiple staircases <NUM>, <NUM>, <NUM>, <NUM>, etc. can be formed by applying a repetitive etch-trim process (e.g., a three-time etch-trim process) on the exposed portion of the first division step structures <NUM> in the first staircase region <NUM> and the second division step structures <NUM> in the second staircase region <NUM> using the third staircase mask <NUM>. The etch-trim process includes an etching process and a trimming process. During the etching process, a number 2X<NUM> of alternating dielectric layer pair <NUM> from the top of the exposed surfaces of the first division step structures <NUM> in the first staircase region <NUM> and the second division step structures <NUM> in the second staircase region <NUM> can be removed. The etch depth determines the thickness of each staircase. And as a result, one staircase can be formed in each of the first staircase region <NUM> and the second staircase region <NUM> during each etch-trim cycle. Both staircases have a thickness of 2X<NUM> times the thickness of one step, and the staircase formed in the first staircase region <NUM> is lower than staircase formed in the second staircase region <NUM> by a depth of X<NUM> times the thickness of one step.

In some embodiments, the staircases can be etched using an anisotropic etching such as a reactive ion etch (RIE) or other dry etching processes. In some embodiments, the dielectric layers <NUM> are silicon oxide films. In this example, the etching of silicon oxide films can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layers can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layers <NUM> are silicon nitride films. In this example, the etching of silicon nitride films can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to remove a single layer should not be limited by the embodiments of the present disclosure.

The trimming process includes applying a suitable etching process (e.g., an isotropic dry etch or a wet etch) on the third staircase mask <NUM> such that the third staircase mask <NUM> can be pulled back laterally, in directions in the x-y plane, parallel to the front surface 130f of the substrate <NUM>. From the top-down view in <FIG>, the third staircase mask <NUM> can be etched incrementally and inwardly from initial pattern defined by, for example, photoresist from lithography. In this example, the initial edges <NUM>-<NUM> of the third staircase mask 640can be trimmed incrementally towards the final edge <NUM>-X<NUM>, wherein X<NUM> is an integer that determines a number of staircases can be formed from top to bottom in each of the first staircase region <NUM> and the second staircase region <NUM>. In the example as shown in <FIG> and <FIG>, X<NUM> equals to six, but it can be any other integer number that is larger than <NUM>. The lateral pull-back dimension in the x-direction at etch trimming process determines the lateral dimension of each staircase in the x-direction. In some embodiments, each staircase can have a different or same lateral dimension in the x-direction.

In some embodiments, trimming of the third staircase mask <NUM> can be isotropic in all directions in the x-y plane. In some embodiments, the lateral dimension of each staircase in the x-direction can be between <NUM> and <NUM>. In some embodiments, the trimming process can include dry etching, such as RIE using O<NUM>, Ar, N<NUM>, etc. After trimming the third staircase mask <NUM>, portions of the topmost surface of the first division step structures <NUM> in the first staircase region <NUM> and the second division step structures <NUM> in the second staircase region <NUM> are exposed and the other portions of the first division step structures <NUM> in the first staircase region <NUM> and the second division step structures <NUM> in the second staircase region <NUM> remain being covered by the third staircase mask <NUM>. The next cycle of etch-trim process resumes with the etching process.

By repeating etch-trim process three times, a number X<NUM> of staircases can be formed from top to bottom in each of the first staircase region <NUM> and the second staircase region <NUM>. As such, the multiple initial division block structures <NUM> become multiple first division block structures <NUM> in the first staircase region <NUM> and multiple second division block structure <NUM> in the second staircase region <NUM>. Each first division block structure <NUM> or second division block structures <NUM> includes a number X<NUM> of staircases that are arranged in the x-direction, as shown in <FIG>. Each staircase can include a number of (2X<NUM>-<NUM>) of steps that are distributed in a number X<NUM> of levels respectively, and are symmetrically arranged in the y-direction. In one example as shown in <FIG>, X<NUM> is three, and staircase <NUM> include five steps <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>', <NUM>-<NUM>, and <NUM>-<NUM>'. Steps <NUM>-<NUM> and <NUM>-<NUM>' are in a same level, and located symmetrically in the y-direction with respect to step <NUM>-<NUM>. Similarly, steps <NUM>-<NUM> and <NUM>-<NUM>' are in a same level, and located symmetrically in the y-direction with respect to step <NUM>-<NUM>.

During etch-trim process, some of the third staircase mask <NUM> may be consumed, and the thickness of the third staircase mask <NUM> may be reduced. After forming the multiple staircases in the first staircase region <NUM> and the second staircase region <NUM>, the third staircase mask <NUM> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

Referring back to <FIG>, the method <NUM> can proceed to operation S250, in which multiple division block structures can be formed in the first staircase region and the second staircase region. <FIG> illustrates a top view of exemplary masks used in operations S220-S250 according to some embodiments, and <FIG> illustrates a perspective view a structure <NUM> of the 3D memory device after operation S250 according to some embodiments.

In some embodiments, the multiple division block structures are formed by using a second staircase division pattern mask <NUM>. As shown in <FIG>, the second staircase division pattern mask <NUM> is used to cover the channel structure region <NUM> and at least one first division block structure <NUM> in the first staircase region <NUM> and at least one second division block structure <NUM> in the second staircase region <NUM>. The second staircase division pattern mask <NUM> also exposes at least one first division block structure <NUM> in the first staircase region <NUM> and at least one second division block structure <NUM> in the second staircase region <NUM>.

As shown in <FIG>, the second staircase division pattern mask <NUM> can have a T-shape with two arms extended in the x-direction to cover the at least one first division block structure <NUM> in the first staircase region <NUM> and the at least one second division block structure <NUM> in the second staircase region <NUM>. That is, the second staircase division pattern mask <NUM> can have edges <NUM>-<NUM> each being extended along the x-direction and longer than the total width of the multiple staircases in the first division block structure <NUM> or the second division block structure <NUM>.

In some embodiments, the second staircase division pattern mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the first staircase division pattern mask <NUM> can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O<NUM> or CF<NUM> chemistry. Furthermore, the second staircase division pattern mask <NUM> can include any combination of photoresist and hard mask.

The third division block structures <NUM> and the forth division block structures <NUM> as shown in <FIG> can be formed by an etching process to remove a portion of the exposed one first division block structure <NUM> in the first staircase region <NUM> and the exposed one second division block structure <NUM> in the second staircase region <NUM>. The etch depth is determined by a total thickness of the multiple staircases in the first division block structure <NUM> or the second division block structure <NUM>. In the inventive embodiments, the etch depth is a number 2X<NUM>X<NUM> times the thickness of one alternating dielectric layer pair <NUM>. In the example as shown in <FIG>, the etch depth can equal to a thickness of <NUM> steps.

In some embodiments, the etching process can include an anisotropic etching such as a reactive ion etch (RIE) or other dry etching processes. In some embodiments, the dielectric layer <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layer <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to remove a single layer should not be limited by the embodiments of the present disclosure.

After the etching process, a third division block structure <NUM> and a forth division block structure <NUM> can be formed, as shown in <FIG>. In some other embodiments, more than four division block structures can be formed by using an etch-trim process. For example, if there are three first division block structures <NUM> in the first staircase region <NUM> and three second division block structures <NUM> in the second staircase region <NUM>, the second staircase division pattern mask <NUM> can firstly cover two first division block structures <NUM> and two second division block structure <NUM>, and to expose one first division block structures <NUM> and one second division block structure <NUM>. After one etching process to remove a certain depth of the expose surface to form four division block structures, the second staircase division pattern mask <NUM> can be trimmed to cover one first division block structures <NUM> and one second division block structure <NUM>, and to expose two first division block structures <NUM> and two second division block structure <NUM>. That is, the edges <NUM>-<NUM> can be pulled back laterally in the y-direction to the boundary of next first division block structures <NUM> and second division block structure <NUM>. A following etching process can form six division block structures.

As such, four or more division block structures can be formed in the first staircase region <NUM> and the second staircase region <NUM>. In some embodiments, the number of division block structures can be equal to the number X<NUM> of the first division block patterns <NUM> of the first staircase division pattern mask <NUM> as described above in connection with <FIG>. Each division block structure can include a number X<NUM> of staircases that are arranged in the x-direction. Each staircase can include a number of (2X<NUM>-<NUM>) of steps that are distributed in a number X<NUM> of levels respectively, and are symmetrically arranged in the y-direction. In one example as shown in <FIG>, structure <NUM> of the 3D memory device can include four division block structures <NUM>, <NUM>, <NUM> and <NUM>. Each division block structure includes six staircases, and each staircase includes five steps that are in three levels.

In some embodiments, the two opposite division block structures that are located at the opposite sides of the channel structure region <NUM> respectively and arranged in a same position in the y-direction, such as <NUM> and <NUM> as shown in <FIG>, can have a vertical offset in the z-direction that equals to a height of a number X<NUM> of steps (or a number X<NUM> of alternating dielectric layer pairs). In one example as shown in <FIG>, X<NUM> equals to three, thus one step in the first division block structure <NUM> is three steps lower than the corresponding step (located in the same position in the y-direction) in the second division block structure <NUM>.

In the inventive embodiments, the two adjacent division block structures that are located at the same side of the channel structure region <NUM> and arranged in a same position in the x-direction, such as <NUM> and <NUM> as shown in <FIG>, have a vertical offset in the z-direction that equals to a height of a number 2X<NUM>X<NUM> of steps (or a number 2X<NUM>X<NUM> of alternating dielectric layer pairs). In one example as shown in <FIG>, X<NUM> equals to three and X<NUM> equals to six, thus the vertical offset in the z-direction between the second division block structure <NUM> and the fourth first division block structure <NUM> is thirty-six steps.

In some embodiments, the multiple steps in the multiple division block structures can be distributed in a number 2X<NUM>X<NUM>X<NUM> of different levels, wherein X<NUM> is the number of the division block structures, X<NUM> is the number of steps of the TSG staircase structure, and X<NUM> is the number of staircases in each division block structure. The total number of the multiple steps in the multiple division block structures can be 2X<NUM>(2X<NUM>-<NUM>)X<NUM>.

For example, as shown in <FIG>, X<NUM> equals to two, X<NUM> equals to three, and X<NUM> equals to six. Thus, the total number of levels of the steps in the multiple division block structures <NUM>, <NUM>, <NUM> and <NUM> is <NUM>. If the steps including the top step and the steps of the TSG staircase structure are numbered from top to bottom (two steps in a same level have a same number), the top step is No. <NUM>; the TSG staircase structure includes steps No. <NUM>-<NUM>; the second division block structure <NUM> include the steps No. <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>; the first division block structure <NUM> include the steps No. <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>; the forth division block structure <NUM> include the steps No. <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>; and the third division block structure <NUM> include the steps No. <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>.

Fabrication of the 3D memory device can be resumed after forming the staircase structures with multiple divisions, for example, forming channel holes, slit structures, replacement gates, and contact structures. Related processes and techniques for these subsequent structures are known to a person skilled in the art and therefore are not included in the present disclosure.

Accordingly, various embodiments of three-dimensional memory device and methods of making the same are described in the present disclosure. In the disclosed 3D memory device, multiple division block structures are formed on both sides of the channel structure region, and arranged along a second direction. Each division block structure includes multiple staircases arranged in a first direction. Each staircase includes multiple steps arranged in the second direction. As such, the 3D space of the disclosed 3D memory device can be efficiently used to form a large number of steps, resulting in a smaller die size, a higher device density, and improved performance compared with other 3D memory devices. Further, during the fabricating process of the disclosed 3D device, the number of masks to be used to form the multiple steps can be reduced, and the number of trimming processes can be also reduced, thereby increasing the number of etching wafers per hour (WPH). Further, forming multiple division block structures using a staircase division pattern mask can avoid using etch-trim process to form steps at a lower portion of the 3D memory device, thus reducing a thickness requirement of the photoresists layer in the etch-trim process.

One aspect of the present disclosure provides a three-dimensional (3D) memory device, comprising: a channel structure region including a plurality of channel structures; a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

In some embodiments, the 3D memory device further comprises a top select gate staircase structure including a number X<NUM> of steps arranged along the second direction in the channel structure region.

In some embodiments, a second vertical offset between the plurality of division block structures in the first staircase region and the plurality of division block structures in the second staircase region equals to X<NUM> times a thickness of one step.

In some embodiments, a third vertical offset between adjacent staircases equals to 2X<NUM> times the thickness of one step.

In some embodiments, each staircase includes a number (2X<NUM>-<NUM>) of steps distributed symmetrically in X<NUM> levels.

In some embodiments, the first staircase structure and the first staircase structure include a plurality of dielectric/conductive layer pairs; and each step includes a dielectric/conductive layer pair.

In some embodiments, the first direction and the second direction are perpendicular to each other and are in a plane parallel to an interface surface of the dielectric/conductive layer pair.

In some embodiments, a number of the plurality of division block structures in each of the first staircase region and the second staircase region is X<NUM>; and a number of the plurality of staircases in each division block structure is X<NUM>.

In some embodiments, the first vertical offset between adjacent of division block structures equals to 2X<NUM>X<NUM> times a thickness of one step.

In some embodiments, a total number of the plurality of steps in the first staircase structure and the second staircase structure is 2X<NUM>(2X<NUM>-<NUM>)X<NUM>; and the plurality of steps are distributed in a number of 2X<NUM>X<NUM>X<NUM> different levels.

In some embodiments, X<NUM> is two and X<NUM> is three.

Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device, comprising: forming a film stack with a plurality of dielectric layer pairs on a substrate; forming a channel structure region in the film stack including a plurality of channel structures; and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region, each of the first staircase structure and the second staircase structure including a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures, and each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

In some embodiments, the method further comprises forming a top select gate staircase structure including a number X<NUM> of steps arranged along the second direction in the channel structure region.

In some embodiments, forming the first staircase structure and the second staircase structure includes: forming a plurality of initial division step structures in the first staircase region and the second staircase region, each initial division step structure including the number X<NUM> of steps arranged along the first direction, wherein each step includes a dielectric layer pair.

In some embodiments, forming the plurality of initial division step structures includes: disposing a first staircase division pattern mask with a number 2X<NUM> of first division block patterns on the film stack; and using an etch-trim process based on the first staircase division pattern mask to form the plurality of initial division step structures.

In some embodiments, forming the first staircase structure and the second staircase structure further includes: forming a number X<NUM> of staircases in each of the initial division step structures to form a number X<NUM> of division block structures in each of the first staircase region and the second staircase region.

In some embodiments, forming the staircases includes: using an etch-trim process such that the staircases are formed along the second direction. The first direction and the second direction are perpendicular to each other and are in a plane parallel to an interface surface of the dielectric/conductive layer pair.

In some embodiments, an etching depth in each cycle of the etch-trim process is 2X<NUM> times a thickness of one step.

In some embodiments, forming the first staircase structure and the second staircase structure further includes: disposing a second staircase division pattern mask to cover at least two division block structures and expose at least two division block structures; and etching the exposed at least two division block structures by a depth equal to 2X<NUM>X<NUM> times the thickness of one step.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance.

The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

Claim 1:
A method (<NUM>) for forming a three-dimensional, 3D, memory device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
forming a film stack (<NUM>, <NUM>) with a plurality of dielectric layer pairs (<NUM>) on a substrate (<NUM>);
forming a channel structure region (<NUM>) in the film stack (<NUM>, <NUM>) including a plurality of channel structures;
forming a top select gate staircase structure (<NUM>) including a number X<NUM> of steps arranged along the second direction in the channel structure region (<NUM>); and
forming a first staircase structure in a first staircase region (<NUM>) and a second staircase structure in a second staircase region (<NUM>), each of the first staircase structure and the second staircase structure including a plurality of division block structures (<NUM>, <NUM>, <NUM>, <NUM>) arranged along a first direction;
wherein a first vertical offset defines a boundary between adjacent division block structures (<NUM>, <NUM>, <NUM>, <NUM>), and each division block structure (<NUM>, <NUM>, <NUM>, <NUM>) includes a plurality of staircases (<NUM>, <NUM>, <NUM>, <NUM>, etc.) arranged along a second direction that is different from the first direction, each staircase (<NUM>, <NUM>, <NUM>, <NUM>, etc.) including a plurality of steps arranged along the first direction, and the first vertical offset between two adjacent division block structures equals to 2X<NUM>X<NUM> times a thickness of one step,
wherein the two adjacent division block structures (<NUM>, <NUM>, <NUM>, <NUM>) are located at a same side of the channel structure region (<NUM>) and arranged in a same position in the second direction,
wherein a number of the plurality of staircases (<NUM>, <NUM>, <NUM>, <NUM>, etc.) in each division block structure (<NUM>, <NUM>, <NUM>, <NUM>) is X<NUM>,
wherein the plurality of division block structures (<NUM>, <NUM>, <NUM>, <NUM>) is formed by using a second staircase division pattern mask (<NUM>), wherein the second staircase division pattern mask (<NUM>) is used to cover the channel structure region (<NUM>) and at least one first division block structure (<NUM>) in the first staircase region (<NUM>) and at least one second division block structure (<NUM>) in the second staircase region (<NUM>), wherein the second staircase division pattern mask (<NUM>) also exposes at least one first division block structure (<NUM>) in the first staircase region (<NUM>) and at least one second division block structure (<NUM>) in the second staircase region (<NUM>) .