Patent Description:
This disclosure is related to the field of energy recovery drivers for piezoelectric actuators.

Piezoelectric actuators are small devices, constructed for example from lead zirconate titanate, that produce a small displacement with a relatively high force capability when a voltage is applied. There are many applications where a piezoelectric actuator may be used, such as in speakers and linearly driven micromirrors. Such piezoelectric actuators are driven with low to medium frequency signals (e.g., up to <NUM>) having a full-scale voltage range of up to 50V or more.

Piezoelectric actuators can be designed such that they are differentially driven and may be modeled as dual capacitive loads having capacitance values on the order of tens of nF. In order to achieve desired performance characteristics, piezoelectric actuator designs increasingly have higher capacitances, leading to stability/bandwidth issues when driven by conventional drivers.

Examples of drivers for pairs of piezoelectric actuators using capacitors as energy stores for recuperation of energy are shown, for example, in <CIT>, <CIT>, <CIT> or <CIT>.

Now described with reference to <FIG> is a conventional fully-differential linear driver <NUM> for a piezoelectric actuator that attempts to address the issues described above. The driver <NUM> includes a sigma-delta modulated digital to analog converter (DAC) <NUM> that receives data DAC_DATA as an input, is clocked by a clock DAC_CLK, and provides an analog version of the data DAC_DATA to a transimpedance amplifier (TIA) <NUM>. The output of the TIA <NUM> is first amplified by a low-voltage driver (LVD) <NUM>, and is then further amplified by a high-voltage driver (HVD) <NUM>. The output of the HVD <NUM> is differential (two signals that change symmetrically about a common mode), continuous, and fed to the components of the piezoelectric actuator represented as the capacitors PZT1, PZT2 to thereby drive the piezoelectric actuator as desired. Notice that the HVD <NUM> is powered by a high voltage VHV (on the order of tens of volts) that is generated by a boost converter <NUM> external to the driver <NUM>.

This design, however, suffers from several limitations. For example, power consumption is undesirably high. The use of multiple amplifiers <NUM>, <NUM>, and <NUM> that each consume a non-negligible amount of power, together with noise and linearity requirements, causes this high power consumption. In addition, since the HVD <NUM> is biased by the VHV voltage, and the quiescent current of the HVD <NUM> is non-negligible, further contributing to the high power consumption - worse, the higher the voltage VHV for a given quiescent current, the higher the contribution to the power consumption by the HVD <NUM>. Still further, since no energy recovery is performed, the capacitors PZT1, PZT2 contribute to power consumption, as the charge on the capacitors is lost when they are discharged to ground during operation. Moreover, since the power consumption by the capacitors PZT1, PZT2 can be described as a C · V<NUM> · f term (with C being the capacitance of PZT1, PZT2, V being the voltage of the driving signal applied thereto, f being the frequency of the driving signal applied thereto) and since each value of this term has been increasing with recent designs, conventional designs which discharge the capacitances to ground are increasingly undesirable.

On top of power consumption concerns, conventional driver designs suffer from additional drawbacks. For example, the value of the capacitances PZT1, PZT2 are increasing in current designs, having the effect of increasing the difficulty of stabilizing the HVD <NUM> and increasing the current consumption of the HVD <NUM>.

Still further, noise and THD (total harmonic distortion) performance is of concern. The resolution of the output differential signal used to drive the piezoelectric actuator represented by the capacitances PZT1, PZT2 is to be relatively high, for example <NUM>-bit, and therefore the noise and linearity of the output differential signal is to be compatible with this resolution, leading to increased power consumption by the amplifiers <NUM>, <NUM>, and <NUM> when they are sodesigned, leading also to increased area. Since the signal to be managed by the amplifiers <NUM>, <NUM>, and <NUM> is of low to medium frequency, the low frequency noise is to be carefully managed. To carefully manage this term with conventional designs, complex designs for the amplifiers <NUM>, <NUM>, and <NUM> are utilized.

In addition, there are technological issues with conventional designs. The designs of the amplifiers <NUM>, <NUM>, and <NUM> may utilize components such as high resistance resistors and high voltage capacitors. High resistance resistors (on the order of megaohms) that might be used suffer from excess area consumption, lack of linearity, contribute to power consumption, and may include undesirable parasitics. High voltage capacitors often have poor yield, increasing production costs.

In view of this panoply of drawbacks with conventional driver designs, further development is needed.

According to the invention, a driver system for a differential piezoelectric actuator system is provided, as defined in the attached claims.

Disclosed herein with initial reference to <FIG> is a driver <NUM> for a differential piezoelectric actuator PZT1, PZT2, together with control circuitry <NUM> for the driver <NUM>.

The differential piezoelectric actuator PZT1, PZT2 is represented as two capacitances respectively connected between nodes A1, A2 and ground because, from an electrical point of view, a piezoelectric actuator may be modeled as a capacitor at a first order approximation.

The driver <NUM> includes a first driver circuit <NUM> connected between node A1 and node L1, and a second driver circuit <NUM> connected between node A2 and node L2. The first and second driver circuits <NUM> and <NUM> are powered between a battery Vbatt and ground. An external inductor L is connected between nodes L1 and L2. The driver circuits <NUM>, <NUM> are integrated components (e.g., integrated within an integrated circuit), and the inductor L is an external component.

The driver circuit <NUM> includes a switch S3 connected between the battery Vbatt and node L1, a switch S2 connected between node L1 and ground, and a switch S1 connected between node A1 and node L1. The driver circuit <NUM> includes a switch S5 connected between a battery Vbatt and node L2, a switch S4 connected between node L2 and ground, and a switch S6 connected between node A2 and node L2.

The control circuitry <NUM> is clocked by the clock signal CK, which is the system clock at which the digital blocks operate. This is separate from the switching frequency (Fsw) at which the switches S1-S6 are operated; this switching frequency may be derived from the clock signal CK. By way of example, the clock frequency CK could be <NUM>, and the switching frequency could be FCK/<NUM> = <NUM>.

The control circuitry <NUM> receives as input the continuous time (instantaneous) value of the current I[L] through the inductor L. The control circuitry <NUM> averages the continuous time value of the current I[L] over a switching period (Tsw) to produce I_AVG[L], which as an example in the case of FCK/<NUM> = <NUM> would be an average over as <NUM> switching period. The control circuitry <NUM> also elaborates the continuous time value of the current I[L] to determine zero crosses thereof, the use of which is described below. The control circuitry <NUM> also receives as input a first differential voltage V[VA1-VA2] that is the difference between the voltage VA1 at node A1 and the voltage VA2 at node A2, and a common mode voltage between nodes A1, A2 represented as V[(VA1+VA2)/<NUM>]. The control circuitry <NUM> also receives as input a common mode reference voltage vcm_REF_DATA (represented digitally) and a differential reference voltage vdm_REF_DATA (represented digitally). The differential reference voltage vdm_REF_DATA may represent a sawtooth signal, or may represent other time varying signals such as sinusoids, which is enabled by the flexibility provided by the control circuitry <NUM> and driver <NUM> described herein.

The control circuitry <NUM> operates, based upon its inputs, to control the switches S1-S6 so as to operate the driver <NUM> in charging phases and recovery phases, with one charging phase or one recovery phase to be performed per switching period (which is a design parameter, and may be a multiple of the frequency FCK of the clock signal CK). Charging phases occur when charge is to be transferred from PZT1 to PZT2, or from PZT2 to PZT1, and there is insufficient charge from the transferor actuator to fully charge the transferee actuator. Recovery phases occur when charge is to be transferred from PZT1 to PZT2, or from PZT2 to PZT1, and there is more than sufficient charge from the transferor actuator to fully charge the transferee actuator.

Insufficient charge or more than sufficient charge is related to shape of the voltage wave that is to be applied to PZT1 and PZT2. In greater detail, at each switching period, charge is taken from PZT1 and provided to PZT2. The charge taken from PZT1 can be mathematically represented as <MAT>, and the charge provided to PZT2 can be mathematically represented as <MAT>. Since VPZT<NUM> is different from VPZT<NUM>, and since some sources for energy losses will be involved in this charge transfer, the imbalance between the two is transferred from or back to the battery Vbatt. This charge imbalance is therefore related to the variation of the potential voltage to be imposed on the actuators PZT1, PZT2 so that the differential voltage V[VA1-VA2] tracks the differential reference voltage vdm_REF_DATA during operation.

The charging phases include C12 (in which energy from the piezoelectric actuator PZT1, as well as energy from the battery Vbatt, is transferred to the inductor L and then the energy stored in the inductor L is transferred to the piezoelectric actuator PZT2) and C21 (in which energy from the piezoelectric actuator PZT2, as well as energy from the battery Vbatt, is transferred to the inductor L and then the energy from the inductor L is transferred to the piezoelectric actuator PZT1).

The recovery phases include R12 (in which energy from the piezoelectric actuator PZT1 is transferred to the inductor L and the energy from the inductor L is transferred to the piezoelectric actuator PZT2 while remainder energy within the inductor L is transferred to the battery Vbatt), and R21 (in which energy from the piezoelectric actuator PZT2 is transferred to the inductor L and the energy from the inductor L is transferred to the piezoelectric actuator PZT1 while remainder energy within the inductor L is transferred to the battery Vbatt).

The charging and recovery phases will now be described in detail and, thereafter, the operation of the control circuitry <NUM> to select which charging phase and which recovery phase to operate the driver <NUM> in, based upon current inputs, will be described.

Charging phase C12 is now described with reference to <FIG>. Charging phase C12 is separated into three sub-phases D1, D2, and D3, followed by a sub-phase D4.

In phase C12, sub-phase D1, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the piezoelectric actuator PZT1 to the inductor L for storage. This D1 sub-phase can be observed in <FIG>, where the current I[L] through the inductor L rises with a slope of VA1/L, and the current I[A1] flowing out of PZT1 rises with a slope of VA1/L.

Next, in phase C12, sub-phase D2, switches S3 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the battery Vbatt to the inductor L. The inductor current I[L] rises with a slope of Vbatt/L as a result, as can be observed in <FIG>,.

Since the voltage stored across PZT1 is actually greater than the battery voltage Vbatt, the slope Vbatt/L is less than the slope VA1/L (as long as VA1 is greater than Vbatt) in this example. Note that in other examples, the voltage stored across PZT1 can be lower than Vbatt, in which case the slope VA1/L will be lower than Vbatt/L - therefore, in this embodiment, the voltages stored across PZT1 and PZT2 can be close to ground, which is not possible with conventional drivers in which a large amount of headroom with respect to ground is to be maintained.

In phase C12, sub-phase D3, switches S2 and S6 are closed, while the other switches are kept open, having the effect of transferring energy from the inductor L to the piezoelectric actuator PZT2. Since the inductor current I[L] is flowing from the inductor L to PZT2 at this point, the inductor current I[L] falls with a slope of -VA2/L and the current I[A2] flowing into PZT2 falls with a slope of -VA2/L during sub-phase D3, as shown in <FIG>.

In phase C12, sub-phase D4, switches S2 and S4 are closed while the other switches are kept open, with the result being that the current is kept fixed, ideally at zero, ready for the next period in which the current may be reversed or not.

Charging phase C21 is effectively the inverse of charging phase C12, and is now described with reference to <FIG>. Charging phase C21 is separated into three sub-phases D1, D2, and D3, followed by a sub-phase D4.

In phase C21, sub-phase D1, switches S2 and S6 are closed, while the other switches are kept open, having the effect of transferring energy from the piezoelectric actuator PZT2 to the inductor L for storage. This D1 sub-phase can be observed in <FIG>, where the current I[L] through the inductor L rises with a slope of VA2/L, and the current I[A2] flowing out of PZT1 rises with a slope of VA2/L.

Next, in phase C21, sub-phase D2, switches S2 and S5 are closed, while the other switches are kept open, having the effect of transferring energy from the battery Vbatt to the inductor L. The inductor current I[L] rises with a slope of Vbatt/L as a result, as can be observed in <FIG>. Since the voltage stored across PZT2 is actually greater than the battery voltage Vbatt, the slope Vbatt/L is less than the slope VA2/L (as long as VA2 is greater than Vbatt) in this example.

In phase C21, sub-phase D3, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the inductor L to the piezoelectric actuator PZT1. Since the inductor current I[L] is flowing from the inductor L to PZT1 at this point, the inductor current I[L] falls with a slope of -VA1/L and the current I[A1] flowing into PZT1 falls with a slope of -VA1/L during sub-phase D3, as shown in <FIG>.

In phase C21, sub-phase D4, switches S2 and S4 are closed while the other switches are kept open, with the result being that the current is kept fixed, ideally at zero, ready for the next period in which the current may be reversed or not.

Recovery phase R12 is now described with reference to <FIG>. Recovery phase R12 is separated into three sub-phases D1, D2, and D3, followed by sub-phase D4.

In phase R12, sub-phase D1, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the piezoelectric actuator PZT1 to the inductor L for storage. This D1 sub-phase can be observed in <FIG>, where the current I[L] through the inductor L rises with a slope of VA1/L, and the current I[A1] flowing out of PZT1 rises with a slope of VA1/L.

Next, in phase R12, sub-phase D2, switches S2 and S6 are closed, while the other switches are kept open, having the effect of transferring energy from the inductor L to the piezoelectric actuator PZT2. Since the inductor current I[L] is flowing from the inductor L to PZT2 at this point, the inductor current I[L] falls with a slope of -VA2/L and the current I[A2] flowing into PZT2 falls with a slope of -VA2/L during sub-phase D2, as shown in <FIG>.

In phase R12, sub-phase D3, switches S2 and S5 are closed, while the other switches are kept open, having the effect of transferring remainder energy left in the inductor L to the battery Vbatt, with the inductor current I[L] falling with a slope of -Vbatt/L as a result as shown in <FIG>.

In phase R12, sub-phase D4, switches S2 and S4 are closed while the other switches are kept open, with the result being that the current is kept fixed, ideally at zero, ready for the next period in which the current may be reversed or not.

Recovery phase R21 is effectively the inverse of recovery phase R12, and is now described with reference to <FIG>.

Recovery phase R21 is separated into three sub-phases D1, D2, and D3, followed by sub-phase D4.

In phase R21, sub-phase D1, switches S2 and S6 are closed, while the other switches are kept open, having the effect of transferring energy from the piezoelectric actuator PZT2 to the inductor L for storage. This D1 sub-phase can be observed in <FIG>, where the current I[L] through the inductor L rises with a slope of VA2/L, and the current I[A2] flowing out of PZT2 rises with a slope of VA2/L.

Next, in phase R21, sub-phase D2, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the inductor L to the piezoelectric actuator PZT1. Since the inductor current I[L] is flowing from the inductor L to PZT1 at this point, the inductor current I[L] falls with a slope of -VA1/L and the current I[A1] flowing into PZT1 falls with a slope of -VA1/L during sub-phase D2, as shown in <FIG>.

In phase R21, sub-phase D3, switches S3 and S4 are closed, while the other switches are kept open, having the effect of transferring remainder energy left in the inductor L to the battery Vbatt, with the inductor current I[L] falling with a slope of -Vbatt/L as a result, as shown in <FIG>.

When phase R21, sub-phase D4 is performed, switches S2 and S4 are closed while the other switches are kept open, with the result being that the current is kept fixed, ideally at zero, ready for the next period in which the current may be reversed or not.

Operation of the control circuitry <NUM> to select which charging phase and which recovery phase to operate the driver <NUM> in, based upon current inputs, will be described. The voltage V[VA1-VA2] is the differential output voltage, and the difference between the differential output voltage V[VA1-VA2] and the differential reference voltage vdm_REF_DATA can be referred to as the "error". The current sign of the differential reference voltage vdm_REF_DATA can be referred to as the "reference sign", and the current sign of the slope of the differential reference voltage vdm_REF_DATA can be referred to as the "reference slope sign".

A single switching period is represented in the graphs of <FIG> and <FIG>. At the end of each switching period, the control circuitry <NUM> determines the phase (either a charging phase or a recovery phase, and in which direction charge transfer occurs, whether it be from PZT1 to PZT2 or from PZT2 to PZT1) in which to control the driver <NUM> during the next switching period, based upon the current phase, the error, the reference sign, and the reference slope sign. The relationships between the current phase, error, reference sign, reference slope sign, and the next phase are now described with additional reference to the table of <FIG>.

If the current phase is the recovery phase R21 and both the error and the reference sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the charging phase C21.

If the current phase is the recovery phase R21 and both the error and the reference slope sign are both positive, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the charging phase C12.

If the current phase is the charging phase C21 and both the error and reference slope sign are positive, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the recovery phase R12.

If the current phase is the recovery phase R12 and both the error and reference slope sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the charging phase C21.

If the current phase is the recovery phase R12 and both the error and reference sign are positive, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the recovery phase C12.

If the current phase is the charging phase C12 and both the error and reference slope sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM> to be in is the recovery phase R21.

The above relationships between the current state, error, reference sign, reference slope sign set the next state as shown in table form in <FIG>. If none of the conditions in the table of <FIG> can be verified, then the next state will be the current state (e.g., the state will not change).

The state change condition from recovery (either R12 or R21) to charge (C21 or C12) can be related to the residual energy after the D2 sub-phase. Specifically, the time duration of sub-phase D3 in the recovery phase is related to the extra energy stored in the inductor L, which in this sub-phase is transferred back to the battery. When the time duration of sub-phase D3 in the recovery phase approaches zero, it means that extra energy is not stored in the inductor L and therefore the next phase is to be a charging phase. Therefore, a state change condition can be added to the one described before, with this being related to state change from recovery to charge (R21 to C12 or R12 to C21) and the condition is the time duration of sub-phase D3 which approaches zero.

The pulse-widths of sub-phases D1 and D2 are determined by the control circuitry <NUM> based upon the value of the signals it receives as feedback, namely the differential voltage V[VA1-VA2] and common mode voltage V[(VA1+VA2)/<NUM>] as well as the continuous time value of the inductor current I[L] to be averaged over one period (i.e., I_AVG[L]). In general though, for whatever phase is to be performed, each feedback signal may be utilized. From a mathematical point of view, the control circuity <NUM> effectively use the voltages VA1 and VA2, but derives them from the measured differential and common mode voltages. This because it is more advantageous to implement a single double-ended differential readout circuit rather than two single-ended readout circuits. Thus, feedback signals may comprise any of: voltages VA1 and VA2; differential voltage V[VA1-VA2] and common mode voltage V[(VA1+VA2)/<NUM>]; inductor average current I_AVG[L] or other electrical signals measured on the driver circuit <NUM> or <NUM>.

The pulse-width D3 is instead defined by looking at the instantaneous value of the inductor current I[L] and, more precisely, by looking for the zero crossing.

A first detailed embodiment of the driver <NUM> and control circuitry <NUM> is now described with reference to <FIG>. In this embodiment, the switch S3 may be formed by: a first p-channel transistor MP1 having a source connected to the battery Vbatt, a drain connected to a source of a first n-channel transistor MN1, and a gate receiving a gate drive signal s[<NUM>]b; and the first n-channel transistor MN1 having its source connected to the drain of MP1, its drain connected to node L1, and its gate receiving a gate drive signal s[<NUM>], the gate drive signal s[<NUM>]b being a complement of the gate drive signal s[<NUM>]. The bulk of MP1 is connected to the source of MP1, and the bulk of MN1 is connected to the source of MN1. The first n-channel transistor MN1 may be a high-voltage transistor.

The switch S2 may be formed by a second n-channel transistor MN2 having its drain connected to node L1, its source connected to ground, and its gate receiving a gate drive signal s[<NUM>]. The bulk of MN2 is connected to the source of MN2. The second n-channel transistor MN2 may be a high-voltage transistor.

The switch S1 may be formed by a third n-channel transistor MN3 having its drain connected to node A1, its source connected to node L1, and its gate receiving a gate drive signal s[<NUM>]. The third n-channel transistor MN3 may be a high-voltage transistor, with the gate drive signal s[<NUM>] being a high voltage drive signal (e.g., on the order of 50V+). The bulk and the source of third n-channel transistor MN3 are connected together by switch Q1 when a low-voltage domain version s[<NUM>]' of the gate drive signal s[<NUM>] is at a logic high, and is connected to ground by switch Q2 when the inverse s[<NUM>]b' of the low-voltage domain gate drive signal s[<NUM>]' is at a logic high.

The switch S5 may be formed by: a second p-channel transistor MP2 having a source connected to the battery Vbatt, a drain connected to a source of a fourth n-channel transistor MN4, and a gate receiving a gate drive signal s[<NUM>]b; and the fourth n-channel transistor MN4 having its source connected to the drain of MP2, its drain connected to node L2, and its gate receiving a gate drive signal s[<NUM>], the gate drive signal s[<NUM>]b being a complement of the gate drive signal s[<NUM>]. The bulk and the source of second p-channel transistor MP2 are connected together, the bulk and the source of fourth n-channel transistor MN4 are connected together. Fourth n-channel transistor MN4 may be a high-voltage transistor.

The switch S4 may be formed by a fifth n-channel transistor MN5 having its drain connected to node L2, its source connected to ground, and its gate receiving a gate drive signal s[<NUM>]. The bulk of MN5 is connected to the source of MN5. Fifth n-channel transistor MN5 may be a high-voltage transistor.

The switch S6 may be formed by a sixth n-channel transistor MN6 having its drain connected to node A2, its source connected to node L2, and its gate receiving a gate drive signal s[<NUM>]. The sixth n-channel transistor MN6 may be a high-voltage transistor, with the gate drive signal s[<NUM>] being a high voltage drive signal (e.g., on the order of 50V+). The bulk and the source of sixth n-channel transistor MN6 are connected together by switch Q3 when a low-voltage domain version s[<NUM>]' of the gate drive signal s[<NUM>] is at a logic high, and is connected to ground by switch Q4 when the inverse s[<NUM>]b' of the low-voltage domain gate drive signal s[<NUM>]' is at a logic high.

The above described transistors may be formed from any technology suitable to produce transistors capable of withstanding the voltages to be utilized for the driver design.

The control circuitry <NUM> includes a zero cross detector (ZCD) <NUM> that receives the current I[L] and asserts a control signal D3 when the current I[L] crosses zero. Respective analog front ends (AFEs) and analog to digital converters (ADCs) within the control circuitry <NUM>, collectively reference <NUM>, receive the differential voltage V[A1-A2] and the common mode voltage V[(A1+A2)/<NUM>], digitally filtering the results in appropriate bandwidths, and provide them as output to a multi-input multi-output (MIMO) control loop and finite state machine (FSM) within the control circuitry <NUM>, collectively reference <NUM>. The MIMO control loop and FSM <NUM> also receives from analog front ends (AFEs) and analog to digital converters (ADCs) <NUM> the average inductor current I_AVG[L] over one switching period when it is to be evaluated for whatever phase is to be performed. The MIMO control loop / FSM <NUM> also receives the common mode reference voltage vcm_REF_DATA and the differential reference voltage vdm_REF_DATA as input. Common mode reference voltage vcm_REF_DATA and the differential reference voltage vdm_REF_DATA may be received from an external source or retrieved from internal storage in MIMO control loop / FSM <NUM> (not shown).

The MIMO control loop / FSM <NUM> generates the control values CD1, CD2 as output based upon its inputs. In particular the FSM <NUM>, by looking at the relationships between the current state, error, reference sign, reference slope sign, sets the next state as shown in table form in <FIG>. If none of the conditions in the table of <FIG> can be verified, then the next state will be the current state (e.g., the state will not change). Control signal D3 is defined by looking at the instantaneous value of the inductor current I[L] and, more precisely, by looking for a zero crossing thereof.

A pulse width modulation (PWM) circuit <NUM> receives the control values CD1, CD2, and the control signal D3, and, based on that, generates the gate drive signals s[<NUM>], s[<NUM>], s[<NUM>], s[<NUM>], s[<NUM>], s[<NUM>].

The gate drive signals s[<NUM>] and s[<NUM>] are passed through high-voltage drivers <NUM>, <NUM> (referenced to a high voltage VHV) to become high-voltage domain signals, the gate drive signals s[<NUM>], and s[<NUM>] are passed through standard drivers <NUM>, <NUM>, and the gate drive signals s[<NUM>] and s[<NUM>] are passed through boot-strapped drivers <NUM> and <NUM> that drive s[<NUM>] and s[<NUM>] to values higher than Vbatt.

The gate drive signal s[<NUM>]b is generated by passing the gate drive signal s[<NUM>] through an inverter <NUM>, and the gate drive signal s[<NUM>]b is generated by passing the gate drive signal s[<NUM>] through an inverter <NUM>.

The low-voltage domain gate drive signal s[<NUM>]' is generated by the PWM circuit <NUM> as having the same logic level as s[<NUM>], and is passed through a standard gate driver <NUM> to an inverter <NUM> to thereby generate the low-voltage domain gate drive signal s[<NUM>]b'.

Graphs of values of voltages within the driver <NUM> are seen in <FIG>, where it can be observed that the control is sufficient for the differential output voltage to well match the differential reference voltage, and for the common mode voltage to well match the common mode reference voltage. A graph of power spectral density can be seen in <FIG>, where it can be seen that the output PSD well matches the reference.

In the above-described embodiment, the high voltage VHV is generated by a boost converter external to the driver <NUM>. However, the inductor L already present within the driver <NUM> may be exploited to be part of a boost converter internal to the driver, as now described with reference to the driver <NUM>' of <FIG>. The driver <NUM>' contains the additions of a switch S7 connected between node L1 and a capacitor CVHV across which the high voltage VHV (on the order of <NUM>+ V) is formed, as well as a switch S8 connected between node L2 and the capacitor CVHV.

The switch S7 is formed by a high-voltage p-channel transistor MP3 having its source connected to the capacitor CVHV, its drain connected to node L1, and its gate receiving a gate drive signal s[<NUM>]b. The bulk and the source of high-voltage p-channel transistor MP3 are connected together. The switch S8 is formed by a high-voltage p-channel transistor MP4 having its source connected to the capacitor CVHV, its drain connected to node L2, and its gate receiving a gate drive signal s[<NUM>]b. The bulk and the source of high-voltage p-channel transistor MP4 are connected together. In addition, in the driver <NUM>', the switch S1 includes an n-channel transistor MN8 connected between the third n-channel transistor MN3 and node L1, with MN8 having its source connected to the source of the third n-channel transistor MN3, its drain connected to node L1, and its gate also receiving the gate drive signal s[<NUM>]. The bulk of MN8 is connected to the source of n-channel transistor MN8, and here the bulk of MN3 is connected to the source of MN3.

Furthermore, in the driver <NUM>', the switch S6 includes an n-channel transistor MN7 connected between the sixth n-channel transistor MN6 and node L2, with n-channel transistor MN7 having its source connected to the source of sixth n-channel transistor MN6, its drain connected to node L2, and its gate also receiving the gate drive signal s[<NUM>]. The bulk and the source of n-channel transistor MN7 are connected together, and here the bulk and source of sixth n-channel transistor MN6 are connected together.

The specifics of the control circuitry <NUM>' for this embodiment will be described below, but first the VHV generation sub-phases D5 and D6 in which the control circuitry <NUM>' operates the driver <NUM>' during each switching period will now be described with additional reference to <FIG>.

Note that, in this embodiment, sub-phase D4 is performed after D6. More precisely, the sub-phase D4 is performed whenever (D1+D2+D3+D5+D6)*Tsw<Tsw. If so, the sub-phase D4 is performed after D6 and its duration will be D4=<NUM>-(D1+D2+D3+D5+D6), thus covering the possible remainder time from the end of the sub-phase D6 to the end of Tsw.

In VHV generation sub-phase D5, the control circuitry <NUM>' closes switches S2 and S5 while leaving the other switches open. As a result, current flows from the battery Vbatt into the inductor L, generating a magnetic field and thereby storing energy in the inductor L. In VHV generation sub-phase D6, the control circuitry <NUM>' closes switches S4 and S7 while leaving the other switches open. The flow of current in the inductor from nodes L2 to L1 falls, and the strength of the magnetic field collapses as the stored energy is converter to current to attempt to maintain the current output from the inductor L. As a result, node L2 goes positive, meaning that the voltage across the inductor L from node L1 to node L2 is in series with the voltage being formed across capacitor CVHV, thereby providing a boosted voltage VHV to the capacitor CVHV which is greater than the battery voltage Vbatt. As such, generation sub-phases D5 and D6 serve to cause the driver <NUM>' to operate as a boost converter. It should be appreciated that this pattern of operation in the generation sub-phases D5 and D6 is but a possibility, and that in fact, VHV can be generated through different switching patterns - for example, in sub-phase D5, switches S2 and S5 could be closed while in sub-phase D6, switches S5 and S7 are closed.

Returning to the control circuitry <NUM>', the control circuitry <NUM>' additionally includes a boost controller <NUM> that generates control signals D5 and D6 from which the PWM circuit <NUM> generates the gate drive signals s[<NUM>] and s[<NUM>] according to the duration of the control signals D5 and D6.

The boost controller <NUM> includes here a comparator <NUM> that compares the current voltage VHV formed across the capacitor CVHV to a reference high voltage VHV_REF and asserts its output when VHV becomes equal to VHVREF. A control loop <NUM> receives the output of the comparator <NUM> and from it generates the control signals D5 and D6.

Advantages of the driver <NUM>, <NUM>' designs described above will now be described. First off, efficiency is high due to the transfer of energy between the actuators PZT1 and PZT2 instead of the discharge of that energy to ground as well as the recovery by the battery of excess energy stored in the inductor L, without the energy consumption that would be caused by the quiescent currents in the various amplifiers of prior art designs (for example the HVD <NUM> of <FIG>). Indeed, the limit on efficiency in these designs is simply that imposed by real world devices, such as the on-resistances of the devices forming the switches, the resistance of the inductor L, and the power consumption involved with the generation of the high voltage VHV.

Still further, the value of the capacitances of the actuators PZT1 and PZT2 is not a concern for stability or bandwidth because the use of a high voltage amplifier in the prior art is eliminated by the designs described herein. In addition, the designs described herein permit the increase of output full-scale, and the output differential voltage V[VA1-VA2] is effectively oversampled, which can be exploited in order to increase bandwidth and achieve increased output accuracy.

This ability to increase bandwidth permits the selection of the switching frequency as a trade-off between accuracy and power-consumption, and permits the driver to be used to drive a resonant device (e.g., micromirror).

While static power consumption of the components other than the driver is to be taken into account, the reduction in power consumption by the driver provides for an overall strong reduction in power consumption compared to prior systems utilizing prior drivers. In addition, assuming the control loop <NUM> is robust, feedback signals other than the differential output voltage have relaxed accuracy requirements. Noise performance is increased as well, with the relatively low noise present being related to PWM jitter and the driving of the switches as well as the noise of the feedback circuit.

It is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of this disclosure, as defined in the annexed claims. For example, in the embodiments described, the timing in the recovery phase R12 when switching from sub-phase D1 (with switches S1 and S4 closed) to sub-phase D2 (with switches S2 and S5 closed) is to be precise due to the fact that switch S5 is to close substantially simultaneously to the opening of switch S4. This is performed to provide for the current across the inductor L to flow continuously without interruption. If this switchover from sub-phase D1 to sub-phase D2 is performed incorrectly, the abrupt interruption in inductor current may cause a high voltage to appear at node L2, potentially causing damage. These same considerations, naturally, also apply to the recovery phase R21.

Therefore, to facilitate an embodiment in which more imprecise timing may be used, the embodiment of <FIG> was developed. The difference between the embodiments of <FIG> and <FIG> is that, in the embodiment of <FIG>, the switch S3 is a MOS transistor which includes an intrinsic body diode D3 having its anode connected to node L1 and its cathode connectable to the battery voltage Vbatt, and the switch S5 is a MOS transistor which includes an intrinsic body diode D5 that similarly has its anode connected to node L2 and its cathode connectable to the battery voltage Vbatt. Appreciate that the body diodes are intrinsic to the structure of the MOS devices, as stated, and are not discrete devices.

In phase R12, sub-phase D1, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring energy from the piezoelectric actuator PZT1 to the inductor L for storage. Sub-phase D1 can be observed in <FIG>, where the current I[L] through the inductor L rises with a slope of VA1/L, and the current I[A1] flowing out of PZT1 rises with a slope of VA1/L.

Next, in phase R12, sub-phase D2, switches S2 and S5 are closed, while the other switches are kept open, having the effect of transferring energy in the inductor L to the battery Vbatt, with the inductor current I[L] falling with a slope of -Vbatt/L as a result, as shown in <FIG>. To mitigate the effect of a timing mismatch between the opening of switch S4 and the closing of switch S5, the body diode D5 is made active through its related switch to provide for the continuous flow of inductor current I[L]. Specifically, at the instant when switch S4 opens, there is a brief period where there is no direct path for the inductor current I[L] to flow. Nevertheless, the inductor L continues to maintain the direction of inductor current I[L] flow, momentarily elevating the voltage at node L2. If switch S5 is not yet fully closed, this results in the voltage at L2 being higher than Vbatt, forward biasing the body diode D5. This condition allows current conduction through the body diode D5 to Vbatt, thereby providing a temporary path for the inductor current I[L] until switch S5 fully closes, as shown as phase R12 sub-phase "D2A" in <FIG>, giving time for switch S5 to close. Once switch S5 fully closes, the path through switch S5 becomes available, and since this path is much lower resistance than the path through the body diode D5, current flow is then through switch S5, which is illustrated as phase R12 sub-phase "D2B" in <FIG>.

Next, in phase R12 sub-phase D3, switches S2 and S6 are closed, while the other switches are kept open, having the effect of transferring remaining energy left in the inductor L to the piezoelectric actuator PZT2. Since the inductor current I[L] is flowing from the inductor L to PZT2 at this point, the inductor current I[L] falls with a slope of -VA2/L and the current I[A2] flowing into PZT2 falls with a slope of -VA2/L during sub-phase D3, as shown in <FIG>.

In phase R21 sub-phase D2, switches S3 and S4 are closed, while the other switches are kept open, having the effect of transferring energy in the inductor L to the battery Vbatt, with the inductor current I[L] falling with a slope of -Vbatt/L as a result as shown in <FIG>.

To mitigate the effect of a timing mismatch between the opening of switch S2 and the closing of switch S3, the body diode D3 is made active through its related switch to provide for the continuous flow of inductor current I[L]. Specifically, at the instant when switch S2 is opened, there is a brief period where there is no direct path for the inductor current I[L] to flow. Nevertheless, the inductor L continues to maintain the direction of inductor current I[L] to flow, momentarily elevating the voltage at node L1. If switch S3 is not yet fully closed, this results in the voltage at L1 being higher than Vbatt, forward biasing the body diode D3. This condition allows current conduction through the diode D3 to Vbatt, thereby providing a temporary path for the inductor current I[L] until switch S3 fully closes, as shown as phase R21 sub-phase "D2A" in <FIG>, giving time for switch S3 to fully close. Once switch S3 fully closes, the path through switch S3 becomes available, and since this path is much lower resistance than the path through the body diode D3, current flow is then through switch S3, which is illustrated as phase R21 sub-phase "D2B" in <FIG>.

In phase R21, sub-phase D3, switches S1 and S4 are closed, while the other switches are kept open, having the effect of transferring remaining energy left in the inductor L to the piezoelectric actuator PZT1. Since the inductor current I[L] is flowing from the inductor L to PZT1 at this point, the inductor current I[L] falls with a slope of -VA1/L and the current I[A1] flowing into PZT1 falls with a slope of -VA1/L during sub-phase D3, as shown in <FIG>.

When phase R21 sub-phase D4 is performed, switches S2 and S4 are closed while the other switches are kept open, with the result being that the current is kept fixed, ideally at zero, ready for the next period in which the current may be reversed or not.

Notice than when using the recovery phases R12 and R21 of <FIG>, each working phase (R12, R21, C12, and C21) can be divided into four sub-phases which follow the same general pattern:.

Operation of the control circuitry <NUM> to select which charging phase and which recovery phase to operate the driver <NUM>" in, based upon current inputs, is now described. The voltage V[VA1-VA2] is the differential output voltage, and the difference between the differential output voltage V[VA1-VA2] and the differential reference voltage vdm_REF_DATA can be referred to as the "error". The current sign of the differential reference voltage vdm_REF_DATA can be referred to as the "reference sign", and the current sign of the slope of the differential reference voltage vdm_REF_DATA can be referred to as the "reference slope sign".

A single switching period is represented in the graphs of <FIG>. At the end of each switching period, the control circuitry <NUM> determines the phase (either a charging phase or a recovery phase, and in which direction charge transfer occurs, whether it be from PZT1 to PZT2 or from PZT2 to PZT1) in which to control the driver <NUM>" during the next switching period, based upon the current phase, the error, the reference sign, and the reference slope sign. The relationships between the current phase, error, reference sign, reference slope sign, and the next phase are now described with additional reference to the table of <FIG>.

If the current phase is the recovery phase R21 and both the error and the reference sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the charging phase C21.

If the current phase is the recovery phase R21 and both the error and the reference slope sign are both positive, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the charging phase C12.

If the current phase is the charging phase C21 and both the error and reference slope sign are positive, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the recovery phase R12.

If the current phase is the recovery phase R12 and both the error and reference slope sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the charging phase C21.

If the current phase is the recovery phase R12 and both the error and reference sign are positive, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the recovery phase C12.

If the current phase is the charging phase C12 and both the error and reference slope sign are negative, then the next phase that the control circuitry <NUM> controls the driver <NUM>" to be in is the recovery phase R21.

The state change condition from recovery (either R12 or R21) to charge (C21 or C12) can be related to the residual energy after the D1 sub-phase. Specifically, the time duration of sub-phase D2 in the recovery phase is related to the extra energy stored in the inductor L, which in this sub-phase is transferred back to the battery. When the time duration of sub-phase D2 in the recovery phase approaches zero, it means that extra energy is not stored in the inductor L and therefore the next phase is to be a charging phase. Therefore, a state change condition can be added to the one described before, with this being related to state change from recovery to charge (R21 to C12 or R12 to C21) and the condition is the time duration of sub-phase D2 which approaches zero.

The pulse-widths of sub-phases D1 and D2 are determined by the control circuitry <NUM> based upon the value of the signals it receives as feedback, namely the differential voltage V[VA1-VA2] and common mode voltage V[(VA1+VA2)/<NUM>] as well as the continuous time value of the inductor current I[L] to be averaged over one period (i.e., I_AVG[L]). In general though, for whatever phase is to be performed, each feedback signal may be utilized. From a mathematical point of view, the control circuity <NUM> effectively use the voltages VA1 and VA2, but derives them from the measured differential and common mode voltages. This because it is more advantageous to implement a single double-ended differential readout circuit rather than two single-ended readout circuits.

Claim 1:
A driver system (<NUM>) for a differential piezoelectric actuator system, the driver system comprising:
an inductor (L);
a driver circuit (<NUM>, <NUM>) comprising driver switches (S1-S6) for selectively facilitating transfer of energy between first and second actuators (PZT1, PZT2) of the differential piezoelectric actuator system and the inductor (L) and between a voltage supply node (Vbatt) and the inductor; and
control circuitry (<NUM>) configured to:
determine whether a next phase in which to operate the driver circuit is a first charging phase or a first recovery phase;
in the first charging phase:
in a first sub-phase of the first charging phase, operate the driver switches (S1-S6) to transfer energy from the first actuator (PZT1) to the inductor (L);
in a second sub-phase of the first charging phase, operate the driver switches (S1-S6) to transfer energy from the voltage supply node (Vbatt) to the inductor (L); and
in a third sub-phase of the first charging phase, operate the driver switches (S1-S6) to transfer energy from the inductor (L) to the second actuator (PZT2); and
in the first recovery phase:
in a first sub-phase of the first recovery phase, operate the driver switches (S1-S6) to transfer energy from the first actuator (PZT1) to the inductor (L);
in a second sub-phase of the first recovery phase, operate the driver switches (S1-S6) to transfer energy from the inductor (L) to the second actuator (PZT2); and
in a third sub-phase of the first recovery phase, operate the driver switches (S1-S3) to transfer energy from the inductor (L) to the voltage supply node (Vbatt).