Patent Description:
A patch antenna is a type of radio antenna with a low profile, which can be mounted on a flat surface. It comprises a flat sheet or "patch" of metal, mounted over a larger sheet of metal called a ground plane. Note that the patch can be of many shapes, such as rectangular, circular, triangular, etc. The two metal sheets together form a resonant piece which can be thought of a microstrip transmission line with a length of approximately half a wavelength. The radiation mechanism arises from discontinuities at each truncated edge of the microstrip transmission line. Patch antennas are commonly used in telecommunication devices because they can be extremely compact. However, one issue of conventional patch antennas is their relatively narrow bandwidth. Known patch antenna designs are described in <CIT>, <CIT>, or <CIT>, for example.

Multiple-Input Multiple-Output (MIMO) could be integrated in the upcoming standard of "<NUM>". In order to benefit from the MIMO technique, the channel matrix has to fulfill some requirements, whereas one of them is that the component channels are uncorrelated. An advantageous way to get two uncorrelated channels in the mm-wave region (i.e., the wavelength is in the mm region) is to use dual polarized patch antennas since through dual polarization these antennas need less space than single polarized antennas (when all other antenna requirements stay the same, e.g. realized gain). A disadvantage of introducing a second polarization is that the patch antenna design looses a parameter to tune (e.g., the parameter "patch-width" for a simple patch antenna) which makes it harder to fulfill the ambitious bandwidth requirements in the mm-wave range (~<NUM>% relative bandwidth).

Thus it is desirable to improve existing patch antenna designs with respect to achievable bandwidth.

The invention is defined by the independent claim, optional features are set out in the dependent claims.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an "or", this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is "at least one of A and B". The same applies for combinations of more than <NUM> Elements.

Note that terms such as vertical and horizontal as used in this specification are merely relative terms and do not signify a particular orientation relative to the earth or anything else. Rather, the term "horizontal" or "horizontal direction" generally refers to the direction parallel to a patch plane defined by a large (e.g. square) surface of the patch and the term "vertical" or "vertical direction" generally refers to the direction perpendicular to the large surface of the patch.

<FIG> are top and side views of a patch antenna element <NUM>.

Patch antenna element <NUM> comprises a dielectric substrate <NUM> (for example, Bakelite, FR4 Glass Epoxy, RO4003, Taconic TLC or RT Duroid) bearing a metal patch <NUM> on the top surface thereof, wherein patch <NUM> has length l and width w. The length l of patch <NUM> typically is selected to be ½ of the wavelength λ of the signal that patch <NUM> is intended to radiate (or receive), so that patch <NUM> resonates at the frequency of the signal and thereby transmits the desired wireless signal. The "length" of a patch antenna generally refers to the distance between the radiating edges of the patch. Thus, for example, in a square patch, this would be the length of a side of the square. For a circular patch, this would be the diameter of the patch. For a rectangular patch, it would be the orthogonal distance between the two radiating edges of the patch (which could be either the short or the long edges depending on the design).

In the example of <FIG>, metal patch <NUM> is peripherally surrounded by a frame structure <NUM>, which will also be referred to as top ground plane. Metal patch <NUM> is separated from top ground plane <NUM> by gap G. Top ground plane <NUM> can be implemented in the same metal layer as metal patch <NUM>. Patch <NUM> and top ground plane <NUM> may be created by conventional manufacturing techniques such as depositing one or more metal layers on the substrate <NUM> by any of a number of techniques known in semiconductor fabrication industry and etching them by any of a number of techniques known in the semiconductor fabrication industry to create the two distinct metallizations, i.e., the top ground plane <NUM> and the patch <NUM>.

A feed line <NUM> may be etched on the opposite side of the substrate <NUM> or could be etched on a second substrate <NUM> disposed below the first substrate <NUM> and bonded thereto. Feed line <NUM> is coupled to a drive signal (not shown). In the illustrated example, feedline <NUM> is directly coupled to patch <NUM> by a feedline via (vertical interconnect access) <NUM>'. In other examples, via <NUM>' could also be omitted so that feed line <NUM> capacitively drives a signal on patch <NUM>. The feed line of a patch antenna may be coupled directly to the patch in order to directly drive (or receive) the signal. However, a patch antenna also may be exited using a proximity coupled feed line. Particularly, the feed line, whether it is a microstrip or a stripline, may be electrically separated from patch <NUM> by a dielectric material, including air, and may drive (or receive) the waves on the patch capacitively.

In the illustrated example, another dielectric substrate <NUM> is disposed below feed line <NUM>. Feed line <NUM> alternately may be deposited on the top surface of the second substrate <NUM>, rather than the bottom surface of the first substrate <NUM>. A bottom ground plane <NUM> is deposited on the bottom of the second substrate <NUM>. Side walls <NUM> through the substrates <NUM> and <NUM> conductively connect the top ground plane <NUM> to the bottom ground plane <NUM>. Side walls <NUM> may be implemented using plated through vias, for example. Note that feed line <NUM> alternately could also be deposited below bottom ground plane <NUM> for better isolating it from patch <NUM>. For more than one antenna polarization, more then one feed line and/or feed points may be provided to drive patch <NUM>.

In the illustrated example, vias <NUM> electrically couple the top and bottom ground planes <NUM> and <NUM> to each other and thus form a shielded cavity around the patch <NUM>. Thus, vias <NUM> may also be regarded as vertically extending side walls of the cavity laterally surrounding patch <NUM>. This helps to minimize coupling between adjacent patch antenna elements in an array of patch antenna elements. Particularly, patch antennas elements of this type may be arranged in arrays of hundreds or even thousands of patch antennas elements. More particularly, multiple patch antennas elements may be fabricated on large substrates, such as substrates <NUM> and <NUM>, that contain multiple patch antenna elements. The fields surrounding the vias help isolate the patch antenna elements from each other.

As previously noted, patch antennas of this type tend to have relatively narrow bandwidth and, therefore, have somewhat limited applications. Within limits, the bandwidth of the antenna can be increased by increasing the volume of the antenna. The volume generally can be understood as the space between the two ground planes <NUM>, <NUM> and the side walls <NUM>, generally called the cavity of the antenna. For this reason, the antenna structure of <FIG> is also sometimes referred to as "cavity backed patch antenna". The bandwidth of a cavity backed patch antenna can be increased by decreasing the substrate's <NUM>, <NUM> permittivity and/or by increasing the distance between the patch <NUM> and the bottom ground plane <NUM>, i.e., by increasing the vertical dimension of the antenna. The bandwidth also can be increased by increasing the horizontal dimension of the antenna, but this is undesirable in an antenna array environment for several reasons, most notably because it would increase the spacing between the elements which directly impacts the performance of an antenna array (like steering capability, grating lobes,. However, varying these distances can affect the bandwidth only within a limited range. Furthermore, it is desirable to reduce the size and weight of electronic components, particularly electronic components in telecommunication devices, such as mobile terminals, for example.

Another known technique to increase the frequency bandwidth is to add an additional or parasitic patch above the first patch <NUM>, resulting in a so-called "stacked patch antenna". A perspective view of a simple stacked patch antenna <NUM> is shown in <FIG>. While <FIG> shows the antenna with substrate layers, <FIG> shows the metal layers of antenna <NUM> without any substrate layers. Note that stacked patch antenna <NUM> may also be implemented as cavity backed stacked patch antenna, similar to the cavity structure described with respect to <FIG>.

For instance, a second (parasitic) patch <NUM> can be placed above the first patch <NUM> and separated therefrom by a dielectric material (for example, a dielectric substrate) having a permittivity similar to air. The second patch <NUM> can have approximately similar dimensions as first patch <NUM>. A signal to be transmitted can be input to the antenna through feed line <NUM>, which then can drive both patches <NUM>, <NUM> simultaneously. The second patch <NUM> parasitically couples to the drive signal by parasitically capacitively coupling to the first patch <NUM>. The additional resonance provided by the second patch can increase the frequency bandwidth of the antenna. It can also enhance its gain. However, when a second linear polarization is introduced (e.g., by a dual-polarized patch antenna) the antenna loses a tuning parameter and thus loses bandwidth.

The present disclosure proposes to bring a tuning parameter back by capacitive coupling of the cavity to a patch and thus achieving a higher bandwidth than without the coupling effect. Turning now to <FIG>, it is illustrated an enhanced patch antenna design according to an example of the present disclosure, which can provide an increased bandwidth compared to the examples described above.

<FIG> is a side view of a patch antenna element <NUM> according to an example. It comprises a substrate <NUM>, a patch <NUM> disposed on the substrate <NUM>, and a ground plane <NUM> disposed on the substrate <NUM> below the patch <NUM>. The skilled person having benefit from the present disclosure will appreciate that patch <NUM> can be of many shapes, including circular, triangular, and rectangular shapes. In this example, ground plane <NUM> horizontally extends beyond patch <NUM> (i.e., has a larger horizontal extension) and conductively connects to vertically extending electrically conductive side walls <NUM> laterally surrounding patch <NUM>. Side walls <NUM> comprise or conductively connect to a conductive planar arrangement in form of protrusions or projections <NUM> horizontally extending from the side walls <NUM> toward the patch <NUM>. Thus, electrically conductive protrusions <NUM> extend inwardly from side walls <NUM> to patch <NUM>.

The skilled person having benefit from the present disclosure will appreciate that patch antenna element <NUM> can be manufactured with an adequate manufacturing method. An example flowchart of a corresponding manufacturing method <NUM> is illustrated in <FIG>.

Method <NUM> includes disposing <NUM> an antenna ground plane <NUM> on a substrate <NUM>, wherein the ground plane horizontally extends beyond an area of a patch <NUM>. Method <NUM> further includes disposing <NUM> vertically extending side walls <NUM> on the ground plane <NUM>, wherein the side walls laterally surround the area of the patch. Method <NUM> further includes forming <NUM> a conductive planar arrangement in form of protrusions <NUM> which horizontally extend from the side walls toward the patch <NUM>, and disposing <NUM> the patch <NUM> on the substrate <NUM> above the ground plane <NUM> such that the patch, the ground plane, the side walls, and the protrusions circumscribe a volume V between the patch and the ground plane. Antenna element <NUM> may be created by conventional semiconductor manufacturing techniques such as depositing one or more metal layers on one or more substrate layers <NUM>, <NUM> by any of a number of techniques known in Printed Circuit Board (PCB)/ semiconductor fabrication industry and etching them by any of a number of techniques known in the semiconductor fabrication industry.

Turning back to <FIG>, a horizontal distance d between protrusions <NUM> and patch <NUM> may be smaller than a horizontal distance between side walls <NUM> and patch <NUM>. Or, to put it differently, a horizontal extension h of the protrusions <NUM> may be larger than a horizontal extension or width hSW of the side walls <NUM> extending between the protrusions <NUM> and ground plane <NUM>, i.e. h ≥ hSW. Side walls <NUM> may connect to protrusions <NUM> at a horizontally outer end of protrusions <NUM>, the outer end facing away from patch <NUM>. Thereby, the horizontally inner end of protrusions <NUM> faces patch <NUM>. The distance d is measured between the horizontally inner end of protrusions <NUM> and the horizontally outer end of patch <NUM>. In some examples, protrusions <NUM> can form a peripheral protruding frame at least partially surrounding patch <NUM>.

Protrusions <NUM> reaching close to patch <NUM> increase the capacitive coupling between patch <NUM> and the surrounding cavity formed by protrusions <NUM>, side walls <NUM>, and ground plane <NUM>. This capacitive coupling between protrusions <NUM> and patch <NUM> can yield an additional tuning parameter which can be used to enhance the bandwidth of patch antenna element <NUM> with respect to conventional designs. The protrusions <NUM> also help to streamline radiating electric field lines in the horizontal direction. A stronger horizontal electric field means more "voltage" over the radiation resistance and this in turn can lead to more radiated power and to a larger bandwidth.

Similar to top ground plane <NUM> of <FIG>, protrusions <NUM> can be formed by a metallic frame structure peripherally surrounding patch <NUM>. This protruding frame structure may also be regarded as an upper ground plane, since it is short circuited with bottom ground plane <NUM> via side walls <NUM>. However, in contrast to the conventional patch antenna element <NUM> illustrated in <FIG>, the horizontal or lateral gap between protrusions <NUM> and patch <NUM> is considerably smaller in <FIG>. In other words, protrusions <NUM> reach closer to patch <NUM> compared to the conventional design of <FIG>. That is, the capacitive coupling can be implemented by a closely spaced annular or peripheral ring around patch <NUM> that is connected to ground. Patch <NUM>, ground plane <NUM>, side walls <NUM>, and protrusions <NUM> may all be formed of one or more metal layers.

In the illustrated example of <FIG>, protrusions <NUM> extend horizontally toward the patch <NUM> from an upper end of side walls <NUM>. In this example, protrusions <NUM> may thus also be considered as a top ground plane. In general, a horizontal extension h of the protrusions <NUM> may be equal to or smaller than λ/<NUM>, i.e. <NUM> < h ≤ λ/<NUM>, wherein h ≥ hSW. The protrusions could also be larger than λ/<NUM>, but when the antenna is used in an array a good configuration is ≤ λ/<NUM>. Edges of the patch <NUM> and of the protrusions <NUM> facing each other are separated by a gap G having width d. According to examples of the present disclosure, the width d of the gap can be smaller than λ/<NUM>. According to the invention, it has been found that d ≤ λ/<NUM> leads to good bandwidth performance of patch antenna element <NUM>. Here, λ denotes the wavelength (in free space) of the Radio Frequency (RF) signal to be emitted or received.

In some examples, protrusions <NUM> and patch <NUM> can be implemented in the same metal layer of a layer stack. Patch <NUM> and protrusions <NUM> may be created by conventional PCB/ semiconductor manufacturing techniques such as depositing one or more metal layers on the substrate <NUM> by any of a number of techniques known in semiconductor fabrication industry and etching them by any of a number of techniques known in the semiconductor fabrication industry to create the two distinct metallizations, i.e., protrusions <NUM> and patch <NUM>.

In the illustrated example, ground plane <NUM>, side walls <NUM>, and protrusions <NUM> circumscribe a volume V or a cavity between patch <NUM> and ground plane <NUM>. The volume V may comprise dielectric substrate material <NUM>, for example. Dielectric substrate material <NUM> can extend underneath the protrusions <NUM>, such that the volume or area <NUM> directly underneath the protrusions <NUM> also comprises dielectric substrate material <NUM>. As has been explained above, side walls <NUM>, which may be formed by vias, and ground plane <NUM> form a shielded cavity around the patch <NUM>, which helps to minimize coupling between adjacent patch antenna elements in an array of patch antenna elements.

The skilled person having benefit from the present disclosure will appreciate that patch antenna element <NUM> will further comprise at least one feedline (not shown) which can be coupled (e.g. by an ohmic contact) to the patch <NUM> in various ways. It may be directly coupled to the patch <NUM> via at least one feedpoint. In other examples, the feedline and patch <NUM> may be capacitively coupled. In the first case, the at least one feedline may be guided to the at least one feedpoint of the patch <NUM> through the ground plane <NUM>. In examples related to multi-polarized patch antennas, patch antenna element <NUM> may optionally comprise a first feedline coupled to patch <NUM> via a first feedpoint configured for a first antenna polarization and a second feedline coupled to patch <NUM> via a second feedpoint configured for a second antenna polarization.

As shown in <FIG>, the side walls <NUM> of <FIG> could also be omitted, leading to an example patch antenna element <NUM>' without cavity but merely with a conductive planar arrangement or frame structure <NUM> above ground plane <NUM>, wherein the conductive planar arrangement <NUM> at least partially laterally surrounds patch <NUM>. Edges of the patch <NUM> and of the conductive planar arrangement <NUM> facing each other are separated by gap G having width d. According to examples of the present disclosure, the width d gap G can be smaller than λ/<NUM>.

According to the invention, it has been found that d ≤ λ/<NUM> leads to good bandwidth performance of patch antenna element <NUM>'. A horizontal extension h of the conductive planar arrangement <NUM> may be equal to or smaller than λ/<NUM>, i.e. <NUM> < h ≤ λ/<NUM>, wherein h ≥ hSW. However, horizontal extension h of the conductive planar arrangement <NUM> could also be larger than λ/<NUM>.

The skilled person having benefit from the present disclosure will appreciate that patch antenna element <NUM>' can be manufactured with an adequate manufacturing method. An example flowchart of a corresponding manufacturing method <NUM>' is illustrated in <FIG>.

Method <NUM>' includes disposing <NUM> an antenna ground plane <NUM> on a substrate <NUM>, wherein the ground plane horizontally extends beyond an area of a patch <NUM>. Method <NUM>' further includes disposing <NUM> the patch <NUM> on the substrate <NUM> above the ground plane <NUM>, and forming or disposing <NUM> a conductive planar arrangement or frame structure <NUM> on the substrate <NUM> above the ground plane <NUM>, wherein the conductive planar arrangement or frame structure <NUM> at least partially laterally surrounds the patch <NUM>. Antenna element <NUM>' may be created by conventional semiconductor manufacturing techniques such as depositing one or more metal layers on one or more substrate layers <NUM>, <NUM> by any of a number of techniques known in Printed Circuit Board (PCB)/ semiconductor fabrication industry and etching them by any of a number of techniques known in the semiconductor fabrication industry.

<FIG> shows a further example of a patch antenna element <NUM> according to the present disclosure.

In addition to patch antenna element <NUM> of <FIG>, patch antenna element <NUM> comprises a second parasitic patch <NUM> disposed above the first patch <NUM> to form a cavity backed stacked patch antenna. Parasitic patch <NUM> is separated from the first patch <NUM> by dielectric substrate material <NUM> disposed between parasitic patch <NUM> and the first patch <NUM> for capacitive coupling between parasitic patch <NUM> and patch <NUM>. In the illustrated example, side walls <NUM> extend up to parasitic patch <NUM> in order to isolate the patch antenna element <NUM> from adjacent ones. Thus, here, protrusions <NUM> do not extend horizontally toward the patch <NUM> from an upper end of the side walls but from a portion of the side walls <NUM> in essentially the same vertical height as the first patch <NUM>. The skilled person having benefit from the present disclosure will appreciate that the side walls <NUM> could also end in the height of the first patch <NUM>, similar to <FIG>.

As shown in <FIG>, the side walls <NUM> of <FIG> could also be omitted, leading to an example patch antenna element <NUM>' without cavity but merely with a conductive planar arrangement or frame structure <NUM> at least partially laterally surrounding patch <NUM> vis-à-vis the radiating edges of patch <NUM>. Edges of the patch <NUM> and of the conductive planar arrangement <NUM> facing each other are separated by gap G having width d. According to examples of the present disclosure, the width d gap G can be smaller than λ/<NUM> or even smaller than λ/<NUM>. A horizontal extension h of the conductive planar arrangement <NUM> may be equal to or smaller than λ/<NUM>, i.e. <NUM> < h ≤ λ/<NUM>, wherein h ≥ hSW. However, horizontal extension h of the conductive planar arrangement 36could also be larger than λ/<NUM>.

<FIG> and <FIG> show further examples of the present disclosure.

In the example of <FIG>, side walls <NUM> comprise or conductively connect to protrusions <NUM> and <NUM>' horizontally extending toward patch <NUM> and parasitic patch <NUM>, respectively. Protrusions <NUM>' related to parasitic patch <NUM> can be formed by a metallic frame structure peripherally surrounding parasitic patch <NUM>. In the illustrated example, protrusions <NUM>' extend horizontally toward the parasitic patch <NUM> from an upper end of side walls <NUM>. Edges of the parasitic patch <NUM> and the protrusions <NUM>' facing each other are separated by a gap. According to examples of the present disclosure, a width d' of the gap is smaller than λ/<NUM>.

According to the invention, it has been found that d < λ/<NUM> leads to good performance of patch antenna element <NUM>. Note that widths d and d' can be different from each other in some examples. For example, protrusions <NUM>' and parasitic patch <NUM> can be implemented in the same metal layer of a layer stack. Parasitic patch <NUM> and corresponding protrusions <NUM>' may be created by conventional PCB/ semiconductor manufacturing techniques such as depositing one or more metal layers on the substrate <NUM>, <NUM>, <NUM> by any of a number of techniques known in semiconductor fabrication industry and etching them by any of a number of techniques known in the PCB/ semiconductor fabrication industry to create the distinct metallizations.

As shown in <FIG>, the side walls <NUM> of <FIG> could also be omitted, leading to an example patch antenna element <NUM>' without cavity but merely with a first conductive planar arrangement or frame structure <NUM> at least partially laterally surrounding patch <NUM> vis-à-vis the radiating edges of patch <NUM> and a second conductive planar arrangement or frame structure <NUM>' at least partially laterally surrounding parasitic patch <NUM> vis-à-vis the radiating edges of parasitic patch <NUM>.

In the example of <FIG>, side walls <NUM> only comprise or conductively connect to protrusions <NUM>' horizontally extending toward parasitic patch <NUM>. The protrusions <NUM> of the previous examples are omitted here. Due to the protrusions <NUM>' related to parasitic patch <NUM> still a better bandwidth of patch antenna element <NUM> may be achieved compared to conventional solutions.

As shown in <FIG>, the side walls <NUM> of <FIG> could also be omitted, leading to an example patch antenna element <NUM>' without cavity but merely with a conductive planar arrangement or frame structure <NUM>' at least partially laterally surrounding parasitic patch <NUM> vis-à-vis the radiating edges of parasitic patch <NUM>.

The skilled person having benefit from the present disclosure will appreciate that yet further examples are possible. For example, protrusions may be located below or above patch <NUM> or parasitic patch <NUM>. That is to say, patch and related protrusions do not necessarily have to be implemented in the same metal layer. Examples also allow for an implementation in different metal layers, leading to a different vertical position of patch and related protrusions.

<FIG> and <FIG> provide a comparison between a conventional cavity backed stacked patch antenna <NUM>, which is similar to the example discussed with respect to <FIG>, and an enhanced cavity backed stacked patch antenna <NUM> according to an example of the present disclosure.

The enlarged view of <FIG> shows a substrate <NUM> which can comprise a plurality of substrate layers. A ground metal layer <NUM> is formed on substrate <NUM> and separated from a feed line <NUM> by substrate material. Above feedline <NUM> antenna ground plane <NUM> is deposited. Electrically conductive sidewalls <NUM> electrically couple the top and bottom ground planes <NUM> and <NUM> to each other and thus form a shielded cavity around patch <NUM>. Further dielectric layers <NUM> and a parasitic patch <NUM> are bonded on top of patch <NUM>. Due to the larger gap (here: in the mm range) between top ground plane <NUM> and patch <NUM> there is only a relatively weak capacitive coupling between top ground plane <NUM> and patch <NUM> in the conventional device <NUM>.

In the device <NUM> illustrated in <FIG>, top ground plane <NUM> additionally comprises protrusion portions <NUM> extending inwardly toward patch <NUM>, thus leading to a considerably smaller gap between protrusion portions <NUM> and patch <NUM>. In the illustrated example, the protrusion portions <NUM> are only implemented in the top metal layer of a metal layer stack forming the side walls <NUM>. The gap between protrusion portions <NUM> and patch <NUM> only has a horizontal width of <NUM> compared to a horizontal extension of patch <NUM> in the mm range. This smaller gap leads to higher capacitive coupling between protrusion portions <NUM> and patch <NUM> in the device <NUM>. Thus, the ground metal <NUM> is strongly coupled to the adjacent patch <NUM>. This coupling can take place on all four sides of the patch <NUM> in some embodiments, and can thus enable a broadband matching of the antenna.

A perspective view the stacked patch antenna <NUM> of <FIG> is shown in <FIG>. While <FIG> shows the antenna <NUM> with substrate layers, <FIG> shows antenna <NUM> without substrate layers.

A comparison of <FIG>, B and 11A, B shows a possible improvement between a conventional stacked patch antenna design without improved metal cavity surrounding and a stacked patch antenna design with metal cavity surrounding according to an example of the present disclosure. As can be seen from both figures, a significant antenna bandwidth improvement can be achieved with metal cavity surrounding and protrusions. In the illustrated examples, the antenna bandwidth (for example, where the antenna reflection is less than - 10dB) has been improved from <NUM>,<NUM> for the conventional case to <NUM>,<NUM>, which is a substantial increase in bandwidth. <FIG> depicts the radiation efficiency and total efficiency of both conventional and enhanced antenna structures. It can be seen that the increase in bandwidth of the enhanced design does not originate from a decrease in radiation efficiency. In fact a slight increase in radiation efficiency can be recognized for the enhanced metal cavity backed stacked patch antenna (EMCBSPA).

<FIG> and <FIG> illustrate the influence of a horizontal thickness of the sidewalls hSW relative to the horizontal extension of the protrusions hP, given the same vertical and horizontal extensions of the patch antenna element hPA and the same minimum gap width d between sidewalls and patch.

It can be seen from <FIG> that the bandwidth of the antenna decreases with decreasing ratio hP/hSW (in the example Prototype Sim_23 the protrusions completely vanish, thus hP/hSW = <NUM>). This is because the effective volume of the cavity circumscribed by ground plane side walls and protrusions decreases with decreasing ratio hP/hSW. This means that the ratio hP/hSW should be chosen as large as possible (given a predetermined fixed horizontal extension of the patch antenna element hPA and a predetermined fixed gap width d (e.g., d = λ/<NUM>) between protrusions <NUM> and patch <NUM>). Thus, in some examples the ratio hP/hSW may be chosen larger than <NUM> (i.e., hP > hSW) or even larger than <NUM> (i.e., hP > <NUM>hSW).

The proposed capacitive coupling of the metal cavity to the main and/or parasitic patch can bring back a tuning parameter which can be used to enhance the bandwidth. The proposed metal cavity can ensure a good metal density on every layer (> <NUM>%) which may be crucial for the lamination process. The higher metallization density may on top of that be very helpful for heat dissipation generated by an Radio Frequency Integrated Circuit (RFIC) which can be flip-chip mounted to the other side of the antenna. The proposed metal cavity can attenuate the coupling between neighboring elements in an antenna array due to the fact that the metal walls damp the propagation of surface waves in the dielectric substrate. An example of an antenna array <NUM> comprising a plurality (here: four) of enhanced cavity backed patch antenna elements according to the present disclosure is shown <FIG>.

<FIG> is a more detailed block diagram of an example of a device, e.g. a telecommunication device, in which enhanced cavity backed patch antenna elements according to example implementations can be implemented. Device <NUM> can represent a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, wearable computing device, or other telecommunication device. It will be understood that certain of the components are shown generally, and not all components of such a device are shown in device <NUM>.

Device <NUM> includes processor <NUM>, which performs the primary processing operations of device <NUM>. Processor <NUM> can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting device <NUM> to another device. The processing operations can also include operations related to audio I/O and/or display I/O.

In one embodiment, device <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into device <NUM>, or connected to device <NUM>. In one embodiment, a user interacts with device <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device. Display subsystem <NUM> includes display interface <NUM>, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface <NUM> includes logic separate from processor <NUM> to perform at least some processing related to the display. In one embodiment, display subsystem <NUM> includes a touchscreen device that provides both output and input to a user. In one embodiment, display subsystem <NUM> includes a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately <NUM> PPI (pixels per inch) or greater, and can include formats such as full HD (e.g., 1080p), retina displays, <NUM> (ultra high definition or UHD), or others.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> can operate to manage hardware that is part of audio subsystem <NUM> and/or display subsystem <NUM>. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to device <NUM> through which a user might interact with the system. For example, devices that can be attached to device <NUM> might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> and/or display subsystem <NUM>. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device <NUM>. Additionally, audio output can be provided instead of or in addition to display output. In another example, if display subsystem includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on device <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one embodiment, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS), or other hardware that can be included in device <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features). In one embodiment, device <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation.

Memory subsystem <NUM> includes memory device(s) <NUM> for storing information in device <NUM>. Memory subsystem <NUM> can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system <NUM>. In one embodiment, memory subsystem <NUM> includes memory controller <NUM> (which could also be considered part of the control of system <NUM>, and could potentially be considered part of processor <NUM>). Memory controller <NUM> includes a scheduler to generate and issue commands to memory device <NUM>.

Connectivity <NUM> includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable device <NUM> to communicate with external devices. The external device could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity <NUM> can include multiple different types of connectivity. To generalize, device <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, LTE (long term evolution - also referred to as "<NUM>"), or other cellular service standards. Wireless connectivity <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth), local area networks (such as WiFi), and/or wide area networks (such as WiMax), or other wireless communication, such as NFC. Wireless communication refers to transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs through a solid communication medium. Cellular connectivity <NUM> and/or wireless connectivity <NUM> can implement example patch antennas of the present disclosure.

Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that device <NUM> could both be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. Device <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device <NUM>. Additionally, a docking connector can allow device <NUM> to connect to certain peripherals that allow device <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, device <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other type.

The following examples pertain to further embodiments:.

The skilled person having benefit from the present disclosure will appreciate that the various examples described herein can be implemented individually or in combination.

Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art.

Functions of various elements shown in the figures, including any functional blocks labeled as "means", "means for providing a sensor signal", "means for generating a transmit signal. ", etc., may be implemented in the form of dedicated hardware, such as "a signal provider", "a signal processing unit", "a processor", "a controller", etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term "processor" or "controller" is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage.

Claim 1:
A patch antenna element (<NUM>; <NUM>; <NUM>; <NUM>; <NUM>) comprising:
a substrate (<NUM>; <NUM>);
a first patch (<NUM>) disposed on the substrate;
a second patch (<NUM>) disposed above the first patch (<NUM>);
a ground plane (<NUM>) disposed on the substrate below the first patch (<NUM>), the ground plane horizontally extending beyond the first patch (<NUM>); and
conductive vertically extending sidewalls (<NUM>);
wherein edges of the first patch (<NUM>) or second patch (<NUM>) and the conductive vertical side walls (<NUM>) facing each other are separated by a gap (G),
wherein
a horizontal width (d, d') of the gap (G) is less then λ/<NUM>, wherein λ denotes a wavelength of a radio frequency signal to be transmitted or received via the patch antenna element.