Patent Description:
The term "cell-free massive MIMO" [Ref. <NUM>] has been used to refer to a massive Multiple-Input Multiple-Output (MIMO) system where some or all of the transmitting and receiving antennas for a base station are geographically distributed, apart from the base station. Each of the transmitting and receiving points may be referred to as an "antenna point" or "antenna processing unit," with the abbreviation "APU" being used herein.

<FIG> provides a conceptual view of a cell-free massive MIMO deployment. As seen in the figure, each of several user equipments (UEs), such as the UE labeled UE <NUM>, has an associated bubble of coverage, representing the area around the UE from which the UE can be reached by transmissions from an APU. Each UE may be surrounded by one or several serving APUs, all of which may be attached to the same central processing unit (CPU), which is responsible for processing the data received from and transmitted by each APU. The UE thus experiences no cell boundaries.

<FIG> provides another view of an example deployment. In this scenario, multiple APUs are deployed around the perimeter of a room, which might be a manufacturing floor or a conference room, for example. Each APU is connected to the CPU via a "strip," or "stripe. " More particularly, the CPU is connected to two such stripes, each stripe comprising a serial concatenation of several (<NUM>, in the illustrated example) APUs. As a general matter, the CPU can target a UE anywhere in the room by controlling one or several APUS that are closest to the UE to transmit signals to and receive signals from the UE.

It will be appreciated that the distribution of base station antennas into APUs as shown in <FIG> and <FIG> can provide for shorter distances between the UE antenna and the base station antennas, in many scenarios. This will be an enabler for the use of higher carrier frequencies, and thereby higher modulation/information bandwidths, both of which are key expectations for <NUM> networks.

Prior art document <CIT> (<NUM>-<NUM>), describes methods and devices for radio frequency (RF) loopback for transceivers. Prior art document <CIT> (<NUM>-<NUM>-<NUM>), describes that reversibility in the directivity in the event of transmission/reception through a multi-antenna system is well suitably compensated for by executing self-calibration. Prior art document <CIT>), describes aspects of a waveguide system for determining an event. Prior art document <CIT> (<NUM>-<NUM>-<NUM>), describes aspects of a repeater having a first coupler to extract downstream channel signals from a first guided electromagnetic waves bound to a transmission guided wave communication system.

One approach to linking a CPU to APUs in a distributed transmission like those described generally above is to interconnect the CPU and APUs using dielectric waveguides that carry information to be transmitted to and received from user equipments (UEs) via radio-frequency (RF) signals, rather than digital signals. A key advantage of linking APUs with CPUs using dielectric waveguides is that a signal to be transmitted by a given APU can be conveyed as an already modulated RF carrier signal from the CPU to the APU, via one or more dielectric waveguides linking the CPU to the APU of interest. This means that no upconversion is needed at the APU - the APU need only route the RF signal to the appropriate antenna or antennas, while providing appropriate amplification and, in some cases, performing analog beamforming. Similarly, an RF signal received by an APU from a UE need not be downconverted at the APU. Instead, it can be amplified and then sent to the CPU in RF form, via one or more dielectric waveguides linking the APU to the CPU.

According to the techniques disclosed herein, the amplitude and phase/delay response of the dielectric waveguides, which is frequency dependent, is measured using an RF test signal that is transmitted by the CPU through at least a first dielectric waveguide connecting the CPU to the first APU in a stripe and then looped back from the first APU or a subsequent APU to the CPU, via a second dielectric waveguide connecting the CPU to the first APU in the stripe.

In some embodiments, this looping back at the APU may be performed by looping the RF test signal from one dielectric waveguide in the APU to another over the air, utilizing multiple antennas in the APU. In some of these embodiments, the RF test signal may be received by the APU via a first dielectric waveguide interface and then transmitted by the APU using an antenna (or antennas) of a first polarization. The same APU in these embodiments may then receive the RF test signal using an antenna (or antennas) of a second polarization, and then send the received RF test signal back towards the CPU via a second dielectric waveguide interface.

Other methods, as well as apparatus corresponding to and configured to carry out the methods summarized above and other techniques are described in further detail below.

There are several possible approaches for implementing the interconnections between the CPU and the APUs that it controls. One approach is to implement the interconnections between the CPUs and the APUs as a high-speed digital interface, e.g., such as a high-speed Ethernet connection. With this approach, information to be transmitted by a given APUs is sent from the CPU to the APU as digital baseband information. This digital baseband information is then up-converted to a radiofrequency (RF) signal in the APU, for transmission over the air. In the other direction, RF signals received from a UE are downconverted in the APU and converted to digital form before being sent over the digital link to the CPU, for further processing.

Another approach is to implement each link, or "hop," along the stripes shown in <FIG> as a dielectric waveguide that carries a high-frequency RF signal (e.g., a millimeter-wave signal). As a general matter, this term may include any sort of dielectric waveguide, which would include such things as conventional RF waveguides, which are metallic pipes and in which the dielectric substance within the pipe is often simply air. However, more cost-effective solutions have been developed for short- and medium-range applications; these solutions may comprise an inexpensive plastic dielectric that is metallized, e.g., so as to form a "pipe" surrounding the dielectric material or so as to form two parallel plates separated by the dielectric material. These inexpensive dielectric waveguides may provide suitable performance over links that are several meters, or even dozens of meters, long. <FIG> illustrates examples of waveguides with rectangular and circular cross sections.

A key advantage of linking APUs with CPUs using dielectric waveguides is that a signal to be transmitted by a given APU can be conveyed as an already modulated RF carrier signal from the CPU to the APU, via one or more dielectric waveguides linking the CPU to the APU of interest. This means that no upconversion is needed at the APU - the APU need only route the RF signal to the appropriate antenna or antennas, while providing appropriate amplification and, in some cases, performing analog beamforming. Similarly, an RF signal received by an APU from a UE need not be downconverted at the APU. Instead, it can be amplified and then sent to the CPU in RF form, via one or more dielectric waveguides linking the APU to the CPU.

In systems utilizing this dielectric waveguide approach, control information, e.g., signals indicating which APU a given RF signal is targeted, indicating beamforming that should be applied to the RF signal when it is transmitted, indicating which APU should send RF signals received for a particular time interval to the CPU, etc., may be sent to the APUs and received from the APUs over a digital channel. This digital channel may be conveyed using any of a variety of physical channel implementations, e.g., by superimposing a digital signal on the conductors of a dielectric waveguide, using any of a wide variety of possible signaling schemes, or by providing a separate electrical link between the CPU and the APUs, for carrying digital control information. It will be appreciated that the information bandwidth of these control signals is far lower than what would be needed to convey digital baseband representations of the signals transmitted and received by the APUs; thus, the physical implementation of the digital links in these dielectric waveguide-based systems can be much simpler than their digital interface-based counterparts.

The techniques described herein are focused on the second approach described above, i.e., on systems where APUs are connected to one another and/or to a CPU via one or more dielectric waveguides.

<FIG> is a block diagram of one embodiment of a wireless communication network <NUM> ("network <NUM>") that includes a dielectric waveguide-based distributed radio system configured to provide one or more types of communications services to User Equipments (UEs) <NUM>, according to some embodiments of the presently disclosed invention. For example, the network <NUM> operates as an access network, providing access to one or more external networks (<NUM>), such as the Internet.

While <FIG> depicts five UEs <NUM>-<NUM> through <NUM>-<NUM>, no limitation attends the depiction, as the number of UEs <NUM> connected to the network <NUM> varies over time. As with the UEs <NUM>, <FIG> and other ones of the accompanying figures may depict elements that are the same or at least broadly similar for purposes of discussion using suffixed reference numbers. However, this specification refers to suffixes only when necessary for clarity. Thus, the reference number "<NUM>" without suffixing may be used to refer to a given UE in singular form, or to given UEs in plural form. The same holds for other drawing reference numbers depicted with suffixing in any of the figures.

The term "UE" encompasses essentially any type of wireless communication apparatus that is configured to make use of the network <NUM>-i.e., to communicate via wireless attachment to the network <NUM>. Example types or categories of UEs include smartphones, feature phones, laptops, tablets, or other personal computing devices. Other examples include Machine Type Communication (MTC) devices or Internet-of-Things (IoT) devices, such as sensors and controllers. The UEs <NUM> served by the network <NUM> may be of the same type or a mix of various types and the mix may change with time. One or more UEs <NUM> served by the network <NUM> may be embedded, e.g., in a vehicle, and one or more may be stationary. For example, the network <NUM> may be an indoor deployment targeting UEs <NUM> within a building or may be outdoors in an urban area with foot traffic and vehicle traffic.

The network <NUM> in an example embodiment is configured according to Third Generation Partnership Project (3GPP) specifications. In at least one embodiment, the network <NUM> is a Fifth Generation (<NUM>) New Radio (NR) network, according to the corresponding 3GPP specifications. See the specifications referred to as 3GPP Release <NUM> and newer. However, the architecture of the network <NUM> has wider applicability than <NUM> NR deployments and <NUM> NR stands only as one example.

Different "parts" of the network <NUM> include a Radio Access Network (RAN) part <NUM>, also referred to as the RAN <NUM>, and a Core Network (CN) part <NUM>, also referred to as the CN <NUM>. While not necessarily germane to radio operations of interest herein, the CN <NUM> provides authentication, mobility-management, and external-network interfacing functions, in support of providing communication services to the UEs <NUM>, while the RAN <NUM> provides the air interface(s) by which the UEs <NUM> are "connected" to the network <NUM>.

Example details for the RAN <NUM> includes a central processing unit (CPU) <NUM> and one or more antenna processing units (APUs) <NUM>, e.g., APUs <NUM>-<NUM> through <NUM>-<NUM>. A characteristic arrangement contemplated herein is that a CPU <NUM> and one or more APUs <NUM> form a "chain" <NUM> of serially interconnected or interlinked entities. In <FIG>, the CPU <NUM> anchors two distinct chains, a first chain <NUM>-<NUM> that includes the APUs <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in series, and a second chain <NUM>-<NUM> that includes the APUs <NUM>-<NUM> and <NUM>-<NUM> in series. Another CPU might anchor only a single chain, or more than two chains.

The entities constituting each chain <NUM> are interconnected via dielectric waveguide (DWG) links <NUM>. For example, for the chain <NUM>-<NUM>, the CPU <NUM> couples to the APU <NUM>-<NUM> via a first DWG link <NUM>-<NUM>, the APU <NUM>-<NUM> couples to the APU <NUM>-<NUM> via a second DWG link <NUM>-<NUM>, and the APU <NUM>-<NUM> couples to the APU <NUM>-<NUM> via a third DWG link <NUM>-<NUM>. For the chain <NUM>-<NUM>, the CPU <NUM> couples to the APU <NUM>-<NUM> via a first DWG link <NUM>-<NUM>, and the APU <NUM>-<NUM> couples to the APU <NUM>-<NUM> via a second DWG link <NUM>-<NUM>.

Each chain <NUM> has a directional sense, with the direction going away from the CPU <NUM> being referred to as the "downstream" direction, and with the direction going towards the CPU <NUM> being referred to as the "upstream" direction. Using this nomenclature, the CPU <NUM> generates "outbound" radio carrier signals and propagates them into the chain <NUM> in the downstream direction, for over-the-air (OTA) transmission by one or more of the APUs <NUM> in the chain <NUM>. Conversely, radio carrier signals received via OTA reception by given ones of the APUs <NUM> are propagated in the chain <NUM> in the upstream direction, for conveyance to the CPU <NUM> for processing-e.g., down-conversion and demodulation.

Saying that a radio carrier signal is "propagated" in the chain <NUM> refers to DWG-conveyance of the radio carrier signal over one or more successive "hops" or "links" in the chain <NUM>. Each DWG link <NUM> in the chain constitutes one serial hop or link. Radio carrier signals propagated in the chain <NUM> may also be referred to as "guided" radio carrier signals or "distributed" radio carrier signals to emphasize that they are conveyed via DWGs. With this in mind, one way to understand operation of the chain <NUM> is that the CPU <NUM> generates outbound radio carrier signals, which are then propagated downstream in the chain <NUM>, as far as needed, for OTA transmission by one or more of the APUs <NUM> in the chain <NUM>. In the opposite direction, radio carrier signals received by given APUs <NUM> via OTA reception are propagated upstream in the chain <NUM> to the CPU <NUM>.

Consider an example case where the APU <NUM>-<NUM> in the chain <NUM>-<NUM> operates as a serving base station for the UE <NUM>-<NUM> and the CPU <NUM> generates a radio carrier signal conveying user traffic for the UE <NUM>-<NUM>. The CPU <NUM> has a DWG interface that couples it to one end of the DWG link <NUM>-<NUM> and it uses that interface to propagate the generated radio carrier signal into the DWG link <NUM>-<NUM> as an outbound radio carrier signal targeting the UE <NUM>-<NUM>. In turn, the APU <NUM>-<NUM> includes an "upstream" DWG interface that couples it to the other end of the DWG <NUM>-<NUM>, and it receives the outbound radio carrier signal via its upstream DWG interface. Because the outbound radio carrier signal targets a UE <NUM> that is served by the APU <NUM>-<NUM>, the APU <NUM>-<NUM> performs an OTA transmission of the radio outbound carrier signal.

Consider a similar example, but where the outbound radio carrier signal targets the UE <NUM>-<NUM>, which is served by the APU <NUM>-<NUM>. In this case, the APU <NUM>-<NUM> propagates the outbound radio carrier signal to the next hop in the chain <NUM>-<NUM>, which is the DWG link <NUM>-<NUM> that couples the APU <NUM>-<NUM> to the APU <NUM>-<NUM>. In turn, the APU <NUM>-<NUM> propagates the outbound radio carrier signal to the next hop in the chain <NUM>-<NUM>, which is the DWG link <NUM>-<NUM> that couples the APU <NUM>-<NUM> to the APU <NUM>-<NUM>.

Now consider the inbound case, where and given APU <NUM> within a chain <NUM> receives an OTA transmission from a UE <NUM> that it serves. That is, the given APU <NUM> receives an uplink radio carrier signal from the UE <NUM>. The given APU <NUM> couples the received uplink radio carrier signal into the DWG link <NUM> on its upstream side - facing the CPU <NUM> - for propagation in the chain <NUM> in the upstream direction as an inbound radio carrier signal for the CPU <NUM>. Any intervening APUs <NUM> in the upstream direction between the given APU <NUM> and the CPU <NUM> perform respective next-hop propagations of the inbound radio carrier signal towards the CPU <NUM>.

As such, each APU <NUM> can transmit and receive via its DWG interfaces, for propagation of radio carrier signals within the chain <NUM>-i.e., waveguide conveyance in the downstream or upstream direction of the chain <NUM>. Further, each APU <NUM> includes or is associated with an antenna array <NUM>, for OTA transmission of radio carrier signals, referred to as downlink (DL) transmission, and OTA reception of radio carrier signals, referred to as uplink (UL) reception.

All APU operations may be managed and controlled by the CPU <NUM>, e.g. by the CPU <NUM> distributing control signaling in the chain <NUM> for the included APUs <NUM>. In one or more embodiments, each APU <NUM> operates in TDD fashion, such that it performs OTA reception mutually exclusive from OTA transmission and, with respect to one DWG to which it is coupled, it performs DWG reception mutually exclusive from DWG transmission.

Each DWG link <NUM> comprises at least one DWG-that is, the term "DWG link" as used herein refers to at least one dielectric waveguide. In at least one embodiment, each DWG link <NUM> comprises a parallel pair of DWGs, with each DWG in the parallel pair being dedicated to a different radio-carrier-signal polarization. Relating this example arrangement to <FIG>, the DWG link <NUM>-<NUM> is an upstream link with respect to the APU <NUM>-<NUM> and it includes a parallel pair of DWGs, and the DWG link <NUM>-<NUM> is a downstream link with respect to the APU <NUM>-<NUM> and it includes a parallel pair of DWGs. Of course, with respect to the APU <NUM>-<NUM>, the DWG link <NUM>-<NUM> is an upstream link and the DWG link <NUM>-<NUM> is a downstream link for the APU <NUM>-<NUM>.

Using two or more parallel DWGs in each DWG link <NUM> allows separate radio carrier signals to propagate simultaneously over the DWG link <NUM>, e.g., for different polarizations and/or greater signal capacity in the chain <NUM>. For example, in <FIG>, consider the case where each DWG link <NUM> in the chain <NUM>-<NUM> includes a single DWG for each polarization that is in use. That means that one series set of DWGs is available in the entire chain <NUM>-<NUM> for use in transmitting or receiving radio carrier signals of the involved polarization, at least in a TDD implementation.

In at least one arrangement, the DWG links <NUM> within a chain <NUM> comprise <NUM> x N parallel DWGs, where the APUs <NUM> in the chain <NUM> are interleaved and every N:th APU <NUM> is connected to the same DWG pair. Also, such arrangements would gain a capacity increase and increased robustness by terminating the chain <NUM> with a CPU <NUM> at each end. For example, one of the terminating CPUs <NUM> could take over for the other one, if needed, using the same set of series-connected DWGs, or the DWG links <NUM> in the chain <NUM> could have respective sets of series-connected DWGs for each of the CPUs <NUM>, such that one of the CPUs <NUM> acts as a master CPU on one of the sets of series-connected DWGs while the other CPU <NUM> acts as a master CPU on the other one of the sets of series-connected DWGs. Of course, the APUs <NUM> would be configured to support such operation.

With TDD operation of the CPU <NUM>, APUs <NUM>, and DGW links <NUM> in one chain <NUM>-<NUM>, conveying radio carrier signals in the downlink direction of the chain <NUM>-<NUM> is mutually exclusive from conveying them in the upstream direction. As such, all of the UEs <NUM> served by the chain <NUM>-<NUM> "share" the radio-carrier-signal bandwidth in time, with only one UE <NUM> being served at a time. To change this, the chain <NUM>-<NUM> can include more than one DWG in each DWG link <NUM>, for each polarization in use, such that a first series set of DWGs in the chain <NUM>-<NUM> can be used to serve a given UE <NUM> at a given time instant, while a second series set of DWGs in the chain <NUM>-<NUM> in parallel with the first set can be used to serve another given UE <NUM> at the same time.

However, whether each of the DWG links <NUM> that form the series sets of DWGs individually comprise single DWGs or two or more DWGs in parallel, the DWG-based connection arrangement offers distinct advantages. For example, using digital interfaces for the serial interconnections in the chain <NUM> would raise serious issues with respect to power consumption and complexity of the serial interconnections and the APUs <NUM>, particularly when targeting very high bit rates for the traffic exchanged with the UEs <NUM> served by the network <NUM>. At a minimum, the use of digital interfaces would require each APU <NUM> to include corresponding analog-to-digital converters and digital to analog converters.

Further, as noted, the APUs <NUM> as contemplated herein do not perform any modulation, demodulation, or frequency-shifting, meaning that the radio carrier signals they transmit OTA are the same ones they received from the CPU <NUM> via downstream propagation in the chain <NUM>, subject, of course, to any transmit beamforming applied by the APU <NUM>. Similarly, and APU <NUM> may perform reception beamforming but, besides that, the OTA-received radio carrier signal incoming to the APU <NUM> is the same carrier radio signal that the APU <NUM> propagates in the upstream direction as an inbound radio signal for the CPU <NUM>.

As a further advantageous simplification used in one or more embodiments of the APUs <NUM>, the DWG interfaces included in the APUs <NUM> operate in TDD fashion with respect to each DWG included in a corresponding DWG link <NUM>-<NUM>. That is, with respect to a single DWG, the DWG interface transmits and receives on a mutually exclusive basis. This arrangement reduces complexity, e.g., the need for diplexers and other frequency-multiplexing circuitry. And, as noted, the APUs <NUM> do not perform frequency-conversion or shifting for the radio carrier signals they handle.

As seen in <FIG>, the distributed radio system consist of several antennas processing units (APU) <NUM>, which are connected to a single central processing unit (CPU) <NUM>, using serial links <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, etc. More particularly, each APU <NUM> is connected to at least one neighboring APU <NUM> and/or to CPU <NUM> via a pair of dielectric waveguides <NUM> that carries the RF signal. Two dielectric waveguides <NUM> may be used for each link so that an APU can be provided (or provide) different RF signals for each of two antenna polarizations. Of course, more than two dielectric waveguides may be used to link neighboring units, in some embodiments.

At each end of each dielectric waveguide, the RF signal received from or transmitted into the dielectric waveguide is converted to or from an electrical signal with a dielectric waveguide interface antenna. These antennas, which may in some cases be very simple conductive elements, launch the RF signals into the dielectric waveguides and pickup RF signals from the dielectric waveguides. The length of each dielectric waveguide <NUM> is set by the deployment scenario and is therefore not a fixed length.

<FIG> depicts an APU <NUM> in an example embodiment. The APU <NUM> includes two sides in a functional sense, labeled in the diagram as SIDE <NUM> and SIDE <NUM>. One is the upstream side facing towards the CPU <NUM> controlling the chain <NUM> in which the APU <NUM> operates and the other side is the downstream side facing away from the CPU <NUM>.

The APU <NUM> includes "A" elements for a first radio-carrier-signal polarization and "B" elements for a second radio-carrier-signal polarization-e.g., horizontal and vertical polarizations. These may be referred to as "Part A" and "Part B" in the discussion that follows. Correspondingly, the antenna array <NUM> comprises a small antenna matrix for each polarization. Only the A matrix is visible in the diagram. Each antenna matrix provides beamforming gain and thus improve the link budget between the APU <NUM> and the UEs <NUM> that it serves, along with improves the interference situation in implementations where multiple chains <NUM> use the same radio carrier frequencies. Example matrix dimensions are <NUM> x <NUM> for <NUM> radio carrier signals, with the antenna elements <NUM> spaced at lambda/<NUM> (<NUM>).

The example APU <NUM> further includes antenna circuitry <NUM> that interfaces with the antenna array <NUM>, a dielectric waveguide interface <NUM>, and control circuitry <NUM> that may exchange control signaling on the upstream side and on the downstream side of the APU <NUM>. For example, the CPU <NUM> may output control signaling for the APUs <NUM> in the chain <NUM> and each APU <NUM> in the chain may transfer some or all such signaling onto the next APU <NUM> in the chain. The signaling may be common to the A and B parts of the APU <NUM> or may be separate for the A and B parts, e.g., coordinated but separate signaling for A and B radio-carrier-signal polarizations handled by the APU <NUM>. <FIG> illustrates such a case, where <NUM>-1A denotes upstream-side control signaling associated with the A part of the APU <NUM>, <NUM>-1B denotes upstream-side control signaling associated with the B part of the APU <NUM>, <NUM>-2A denotes downstream-side control signaling associated with the A part of the APU <NUM>, and <NUM>-2B denotes downstream-side control signaling associated with the B part of the APU <NUM>. Of course, this example not limiting and other control signaling arrangements are contemplated.

In similar A/B fashion, the DWG interface <NUM> of the APU <NUM> connects to two DWGs in each direction. That is, on SIDE <NUM> of the APU <NUM>, the DWG interface <NUM> provides DWG coupling for two DWGs constituting the SIDE-<NUM> DWG link <NUM>-<NUM>. These two SIDE-<NUM> DWGs are denoted as <NUM>-1A and <NUM>-1B, corresponding to the A and B parts of the APU <NUM>. Likewise, the DWG interface <NUM> provides DWG coupling for two DWGs <NUM> constituting the SIDE-<NUM> DWG link <NUM>-<NUM>. These two SIDE-<NUM> DWGs are denoted as <NUM>-2A and <NUM>-2B, corresponding to the A and B parts of the APU <NUM>.

The DWG <NUM>-1A on SIDE <NUM> "maps" to the DWG <NUM>-2A on SIDE <NUM>, meaning that in relay operation, the APU <NUM> couples radio carrier signals incoming to the APU <NUM> from the DWG <NUM>-1A over to the DWG <NUM>-2A, and vice versa. The same cross-side mapping applies for the DWGs <NUM>-1B and <NUM>-2B. In at least one embodiment, the <NUM>-1A/<NUM>-2A pairing of DWGs handles a first radio-carrier-signal polarization, such as horizontal polarization, and the <NUM>-1B/<NUM>-2B pairing of DWGs handles a second radio-carrier-signal polarization, such as vertical polarization. With TDD operation, only one DWG on either side of the APU <NUM> is needed per polarization.

Assuming that SIDE <NUM> is the upstream side of the APU <NUM>, in downlink (DL) operation, also referred to as outbound operation, the DWGs <NUM>-1A and <NUM>-1B carry corresponding outbound radio carrier signals of "A" and "B" polarization, originated from the CPU <NUM> and propagated in the chain <NUM> towards the APU <NUM>. If the APU <NUM> is operating as a relay station, its DWG interface <NUM> couples these outbound radio signals over to SIDE <NUM> of the APU <NUM>, into the DWGs <NUM>-2A and <NUM>-2B, for the next APU <NUM> in the chain <NUM>. Conversely, in base-station or transceiver mode, the DWG interface <NUM> of the APU <NUM> couples the outbound radio carrier signals incoming on DWGs <NUM>-1A and <NUM>-1B into the antenna circuitry <NUM>, for OTA transmission from the antenna array <NUM> (the A and B antenna matrixes in <FIG>).

Assuming, again, that SIDE <NUM> is the upstream side of the APU <NUM>, in uplink (UL) operation, also referred to as inbound operation, relay-station operation of the APU <NUM> involves the APU <NUM> receiving inbound radio carrier signals on its downstream side (SIDE <NUM>), i.e., on the DWGs <NUM>-2A and <NUM>-2B, where these signals were received via OTA reception by another APU <NUM> that is downstream in the chain <NUM>. The APU <NUM> couples these inbound signals into the SIDE-<NUM> DWGs <NUM>-1A and <NUM>-1B, for propagation towards the CPU <NUM>. For base-station mode UL operation, the APU <NUM> receives an UL radio carrier signal from a UE <NUM> and couples it into its SIDE <NUM> DWG interface, for propagation towards the CPU <NUM> as an inbound radio carrier signal.

Another point worth emphasizing is that the A/B segregations shown in <FIG> aid discussion, but they are not meant to suggest limitations on how an APU <NUM> may be implemented with respect to multiple polarizations. At least some aspects may be integrated.

Other example elements illustrated in the APU <NUM> of <FIG> include a signaling interface <NUM> of the control circuitry <NUM>, which may include two respective control interfaces <NUM>, with the interface <NUM>-<NUM> for control-signaling connectivity on the upstream side of the APU <NUM> and the interface <NUM>-<NUM> for control-signaling connectivity on the downstream side of the APU <NUM>. For example, the CPU <NUM> generates control signaling to control the APUs <NUM> included in a chain <NUM>, such as TDD-related control signaling that determines the relay-station and base-station operations of individual APUs <NUM> in the chain <NUM>. Such signaling may flow via serial control-signaling links between the CPU <NUM> and the successive APUs <NUM> in the chain <NUM>, with the APU <NUM> closest to the CPU <NUM> receiving control signaling directly from the CPU <NUM> and passing all or some of it along to the next APU <NUM>, and so on.

To this end, the control circuitry <NUM> in one or more embodiments comprises one or more microprocessors, Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), or Application Specific Integrated Circuits (ASICs), or any mix thereof. The control circuitry <NUM> may include or be associated with memory or other computer-readable media, and may operate according to the execution of stored computer program instructions.

In at least one embodiment, the DWGs <NUM> comprising the DWG links <NUM> have a conductive exterior <NUM> that provides an electrical connection for exchanging control signaling between the CPU <NUM> and the adjacent APU <NUM>, and between adjacent APUs <NUM>. The conductive exterior <NUM> comprises, for example a metallic coating or a conductive sheathing. In other embodiments, dedicated wired connections independent of the DWG links <NUM> electrically interconnects the CPU <NUM> and the APUs <NUM>. In either case, the control signaling includes, for example, TDD control signaling and mode control signaling, according to which the CPU <NUM> determines which APUs <NUM> transmit or receive OTA radio carrier signals at what times. Thus, the control signaling provides for operation of the APUs <NUM> as a distributed antenna system, where the CPU <NUM> schedules the transmission and/or reception of user traffic from respective UEs <NUM> served by the chain <NUM>, via respective ones of the APUs <NUM> in the chain <NUM>.

Each APU <NUM> may also include or be associated with a power management unit (PMU) <NUM>. The PMU <NUM> provides operating power for the antenna circuitry <NUM>, the DWG interface <NUM>, and the control circuitry <NUM>, for example. In at least some embodiments, the PMU <NUM> is controllable by the CPU <NUM> via the control signaling. In addition to the conductive exteriors <NUM> of the DWGs in the DWG links <NUM> carrying the control signaling, the conductive exteriors <NUM> also may be used to supply operating power, e.g. DC voltage down the chain <NUM> of APUs <NUM>.

In a Power over Ethernet (POE) example, a <NUM> VDC power signal is carried via the conductive coatings <NUM> included in the respective DWG links <NUM>. However, lower operating voltages may be used, e.g., to facilitate full monolithic integration of the circuitry comprising each APU <NUM>. To some extent, the voltage drops incurred on the successive interconnections used to carry the control signaling down the chain <NUM> of APUs <NUM> may dictate the voltage level of the DC power signal and the PMU <NUM> of each APU <NUM> may include DC/DC converters, as needed, to provide the particular operating voltages needed within the APU <NUM>.

While carrying the control signaling over the power feed may be advantageous in terms of reduced complexity and parts count, the arrangement should be understood as a non-limiting example for the control-signaling interconnections. More broadly, the control signaling arrangement may be implemented as a parallel, low-frequency serial peripheral interface (SPI), with the CPU <NUM> outputting control signaling for respective ones of the APUs <NUM> via the SPI.

Each APU <NUM> has, for example, a unique identifier that allows the CPU <NUM> to identify which APU <NUM> is targeted by particular control signaling. Application Specific Integrated Circuits (ASICs) or other integrated circuitry used within each APU <NUM> may, for example, be fused with a unique identifier that fixes the APU's identity. Dynamic or configurable identities also may be used in one or more embodiments. An APU <NUM> that receives control signaling not targeted to it would pass it along the next control-signaling hop in the chain <NUM>, in the downstream direction. Likewise, upstream control signaling would pass from APU <NUM> to APU <NUM> in the chain <NUM>, as needed, to reach the CPU <NUM>.

As noted, the CPU <NUM> uses the control signaling to, among other things, control the state of each APU <NUM> in the chain <NUM>. Here, the possible states may be relay mode, base-station mode, and standby mode, as set under control of the CPU <NUM>.

<FIG> illustrates an example arrangement for the CPU <NUM> in one or more embodiments. The CPU <NUM> includes DWG interfaces <NUM>, including receiving and transmitting circuitry <NUM> and <NUM>, for coupling into the DWGs that comprise its DWG link <NUM> into the first APU <NUM> of a chain <NUM> of APUs <NUM> controlled by the CPU <NUM>. In at least one embodiment, the DWG interface(s) <NUM> of the CPU <NUM> use antennas <NUM> to transmit outbound radio carrier signals into the associated DWG link <NUM> and to receive inbound radio carrier signals from the associated DWG link <NUM>. The antennas <NUM> may be placed for lateral feeding into the associated DWG link <NUM>, and the same arrangement may be implemented in each of the APUs <NUM>, for coupling with their respective upstream and downstream DWG links <NUM>.

The CPU <NUM> also includes processing circuitry <NUM>, including baseband radio processing circuitry <NUM> for baseband processing of outbound and inbound signals corresponding to the outbound and inbound radio carrier signals. The CPU <NUM> further includes control circuitry <NUM> configured for controlling operation of the CPU <NUM> and for controlling one or more chains <NUM> of APUs <NUM> that are coupled to the CPU <NUM>. To that end, the control circuitry <NUM> is associated with one or more control-signaling interfaces <NUM>, e.g., SPI circuitry. The control circuitry <NUM> or the processing circuitry <NUM> at large also may be associated with one or more network interfaces <NUM>, e.g., that support backhaul connections for carrying user traffic and related network-control signaling between the CPU <NUM> and one or more supporting nodes in the CN <NUM>.

The processing circuitry <NUM> in one or more embodiments includes or is associated with storage <NUM>, e.g., for storing configuration data <NUM> associated with the operation of the CPU <NUM> and/or one or more computer programs ("CP" in the diagram) comprising computer program instructions the execution of which by one or more microprocessors or other types of digital processors configure such processors as said processing circuitry <NUM>. That is, the processing circuitry <NUM> may be fixed circuitry or programmed circuitry and, in at least one embodiment, the processing circuitry <NUM> is at least partly realized by one or more microprocessors being specially adapted according to their execution of computer program instructions stored in the storage <NUM>.

Correspondingly, the storage <NUM> provides for at least temporary storage of the computer program(s) and also may provide working memory for program execution. Broadly, the storage <NUM> comprises one or more types of computer-readable media, with non-limiting examples including any one or more of SRAM, DRAM, NVRAM, FLASH, EEPROM, and Solid State Disk (SSD).

The CPU <NUM> also includes radiofrequency circuitry <NUM> that is associated with the baseband radio processing circuitry <NUM> and with the DWG interfaces <NUM>. In cooperation with the baseband radio processing circuitry <NUM>, the CPU <NUM> uses the radiofrequency circuitry <NUM> to generate outbound radio carrier signals for output via the DWG interface(s) <NUM>. Likewise, the CPU <NUM> uses the radiofrequency circuitry <NUM> to process inbound radio carrier signals received via the DWG interface(s) <NUM>. In this regard, the CPU <NUM> can be understood as providing all modulation and frequency up-conversion processing for outbound radio carrier signals conveyed in the chain <NUM> of APUs <NUM>, and providing all demodulation and frequency down-conversion processing for inbound radio carrier signals conveyed in the chain <NUM> of APUs <NUM>.

<FIG> is a block diagram illustrating more details of part A of APU <NUM>. Again, it should be understood that example APU <NUM> comprises a substantially identical part B, which supports a different antenna polarization. <FIG> focuses on an example implementation of the DWG interface <NUM> and the antenna circuitry <NUM>. The antenna circuitry <NUM> includes first radiofrequency circuitry <NUM> and the DWG interface <NUM> includes second radiofrequency circuitry <NUM>.

In an example case, the antenna array <NUM> includes sixteen antenna elements for transmission and/or reception beamforming, and the first radiofrequency circuitry <NUM> includes a corresponding block <NUM> of radiofrequency circuitry per antenna element of the antenna array <NUM>. Each block <NUM> includes a switch <NUM>, a power amplifier (PA) <NUM>, a low noise amplifier (LNA) <NUM>, a switch <NUM>, a beamforming circuit element <NUM>, and a splitter/combiner (S/C) <NUM>.

The second radiofrequency circuitry <NUM> comprises respective DWG coupling circuits <NUM>-<NUM> and <NUM>-<NUM>. Each DWG coupling circuit <NUM> provides for transmit/receive coupling via an associated antenna <NUM> into a DWG <NUM>. To the extent that the APU <NUM> supports more than one DWG <NUM> per DWG link <NUM>, it will have a DWG coupling circuit <NUM> per DWG <NUM>. Going back momentarily to <FIG>, the depicted APU <NUM> would include two DWG coupling circuits <NUM> on SIDE <NUM>, one for the SIDE-<NUM> A connection and one for the SIDE-<NUM> B connection, and two DWG coupling circuits <NUM> on SIDE <NUM>, one for the SIDE-<NUM> A connection and one for the SIDE-<NUM> B connection.

Further, as seen in <FIG>, each DWG coupling circuit <NUM> on one side of the APU <NUM> is paired with-coupled to-a corresponding DWG coupling circuit <NUM> on the other side of the APU <NUM>. That is, each DWG coupling circuit <NUM> on the upstream side of the APU <NUM> has a corresponding DWG coupling circuit <NUM> on the downstream side of the APU <NUM>. These complementary pairings, the upstream/downstream pairings, provide for the coupling of radio carrier signals from an upstream DWG <NUM> into a corresponding downstream DWG <NUM>-i.e., next-hop conveyance. In the diagram, transfer circuitry <NUM> provides such coupling between the DWG coupling circuit <NUM>-<NUM> and the DWG coupling circuit <NUM>-<NUM>.

For relay operation of an outbound radio signal and assuming that SIDE <NUM> is the upstream side of the APU <NUM> and that SIDE <NUM> is the downstream side, an outbound radio carrier signal appears on the DWG <NUM>-<NUM> and the switch <NUM> of the DWG coupling circuit <NUM>-<NUM> (upstream coupler) is set for receiving, such that the outbound radio carrier signal radiates from the upstream DWG <NUM>-<NUM> and is coupled to the input of the LNA <NUM> of the upstream coupler. The LNA <NUM> of the upstream coupler outputs the outbound radio carrier signal with amplification and applies it to an S/C <NUM> of the transfer circuitry <NUM>. In turn, the S/C <NUM> applies the outbound radio carrier signal to the input of a PA <NUM> of the DWG coupling circuit <NUM>-<NUM> (downstream coupler). The PA <NUM> outputs the outbound radio carrier signal with power amplification, and a switch <NUM> of the downstream coupler is set for transmission, meaning that the outbound radio carrier signal is launched via the antenna <NUM> of the downstream coupler into the downstream DWG <NUM>-<NUM>.

For relay operation of an inbound radio signal and assuming that SIDE <NUM> is the upstream side of the APU <NUM> and that SIDE <NUM> is the downstream side, an inbound radio carrier signal appears on the DWG <NUM>-<NUM> and the switch <NUM> of the downstream coupler is set for receiving, such that the inbound radio carrier signal radiates from the downstream DWG <NUM>-<NUM> and is coupled to the input of the LNA <NUM> of the downstream coupler. The LNA <NUM> of the downstream coupler outputs the inbound radio carrier signal with amplification and applies it to an S/C <NUM> of the transfer circuitry <NUM>. In turn, the S/C <NUM> applies the outbound radio carrier signal to the input of a PA <NUM> of the upstream coupler. The PA <NUM> of the upstream coupler outputs the inbound radio carrier signal with power amplification, and the switch <NUM> of the upstream coupler is set for transmission, meaning that the inbound radio carrier signal is launched via the antenna <NUM> of the upstream coupler into the upstream DWG <NUM>-<NUM>.

For base-station operation with respect to an outbound radio carrier signal received at the APU <NUM> via the upstream coupler, the S/C <NUM> of the transfer circuitry <NUM> applies outbound radio carrier signal to a SW <NUM> that couples it into an S/C <NUM> of the antenna circuitry <NUM>. The S/C <NUM> and S/Cs <NUM> split/distribute the outbound radio signal into the respective per-antenna blocks <NUM>. In embodiments where the APU <NUM> performs transmit beamforming, the split radio carrier signal into each of the antenna blocks <NUM> is weighted by the beamforming element <NUM> and the switches <NUM> and <NUM> are set for transmission, meaning that the split and weighted radio carrier signal passes to the input of the PA <NUM>, for power amplification and OTA transmission from the associated antenna element.

For base-station operation with respect to an OTA radio carrier signal received at the APU <NUM> via its antenna array <NUM>, the switches <NUM> and <NUM> of each antenna block <NUM> are set for receive, meaning that an antenna-received radio carrier signal appears at the input of the LNA <NUM> in each block <NUM>, which provides low-noise amplification for the antenna-received radio carrier signal and applies it to the beamforming element <NUM>. In embodiments of the APU <NUM> that perform receive beamforming, the beamforming element <NUM> applies a weighting to the radio carrier signal output from the LNA <NUM> and provides it to a respective one of the S/Cs <NUM>, which combine the radio carrier signals incoming from each of the antenna blocks <NUM>. Correspondingly, the S/C <NUM> forms a combined radio carrier signal, e.g., a combination of the weighted radio carrier signals output from the respective beamforming elements <NUM> of the antenna blocks <NUM> and couples the combined radio carrier signal into the switch <NUM>, which is set for inbound base-station operation and, therefore, couples it into the S/C <NUM>.

In turn, the S/C <NUM> couples the combined radio carrier signal to the PA <NUM> of the upstream coupler, which provides power amplification for it and applies it to the switch <NUM> of the upstream coupler. The switch <NUM> is configured for transmission, meaning that the combined radio carrier signal from the PA <NUM> of the upstream coupler is launched into the upstream DWG <NUM>-<NUM>, as an inbound radio carrier signal, for propagation in the chain <NUM> towards the CPU <NUM>.

It will be understood that the selective operation of the SWs <NUM>, <NUM>, <NUM>, and <NUM>, as well as other modally-controlled elements of the first and second radiofrequency circuitry <NUM> and <NUM> of the APU <NUM> are controlled within the APU <NUM> by the control circuitry <NUM> of the APU <NUM>, in dependence on the operational state of the APU <NUM>. In turn, the control circuitry <NUM> of the APU <NUM> controls the operational state of the APU <NUM> in dependence on the control signaling targeted to it by the CPU <NUM>. In this respect, the various SWs and S/Cs within the radio frequency circuitry <NUM> and <NUM> can be considered as part of the control circuitry <NUM>.

Similarly, the beamforming solutions used by the APU <NUM> for transmit and/or receive antenna beamforming-i.e., the dynamically configured sets of antenna weights collectively applied by the beamforming elements <NUM> of the antenna blocks <NUM>-may be determined by the CPU <NUM> and conveyed to the APU <NUM> via the control signaling. As such, the control circuitry <NUM> of the APU <NUM> includes or interfaces to the beamforming elements <NUM>, to set the per-antenna weights applied to the radio carrier signals incoming from the antenna array <NUM> or outgoing to the antenna array <NUM>.

As seen in <FIG>, the same or similar RF-circuit building blocks are used to implement the antenna circuitry <NUM> and the DWG interface <NUM>. Notably, the elimination of frequency-conversion blocks and mixed-mode circuits from the radio-carrier-signal paths within the APU <NUM> relaxes the requirements on the integrated-circuit process choices available for implementation of these parts of the APU <NUM>. As a further advantage, the absence of filters from the radio-carrier-signal paths within the APUS <NUM> enables full monolithic integration of the circuit elements comprising the antenna circuitry <NUM> and the DWG interface <NUM>.

Some embodiments of an APU <NUM> may include a loopback switch (SW) <NUM> that connects parts A and B at the point shown in <FIG>, i.e., at the point between dielectric waveguide interface circuitry <NUM> and antenna circuitry <NUM>. This loopback switch <NUM> provides for a loopback path that connects the dielectric waveguide interface circuitry <NUM> in the two parts of the APU <NUM>, making it possible to pass an RF signal from a dielectric waveguide <NUM> connected to part A of APU <NUM> to a dielectric waveguide <NUM> connected to part B of APU <NUM>, and vice versa, without passing through any of the antenna circuitry <NUM> in either part. The significance and usefulness of this will be explained further, below.

One problem with using a dielectric wave guide as interface between the APUs <NUM> in a system like that illustrated in <FIG> is that each of the dielectric waveguides has an amplitude and phase/delay response that is frequency dependent. This means that passing RF signals with a wide bandwidth through each link between a CPU and APU or between two APUs introduces a frequency-dependent attenuation of the RF signal, which increases with increasing length of the dielectric waveguide, and that accumulates for signals that are forwarded through two or more dielectric waveguides. One approach to this problem, as discussed in <CIT> [Ref. <NUM>], is to divide the RF signal into sub-bands that have narrow enough bandwidths that the phase/delay and amplitude ripple is reasonably constant within each sub-band. This technique, however, requires the use of up- and down-conversion circuitry in each of the APUs, which increases the cost and complexity of the APUs. The embodiments described herein provide a more cost-efficient solution to this problem. With these embodiments, the need for up- and down-conversion circuitry in the APUs can be avoided; only the CPU need include up- and down-conversion circuitry.

According to the techniques disclosed herein, the amplitude and phase/delay response of the dielectric waveguides, which is frequency dependent, is measured using an RF test signal that is transmitted by the CPU <NUM> through at least a first dielectric waveguide <NUM> connecting the CPU <NUM> to the first APU <NUM> in a stripe and then looped back from the first APU <NUM> or a subsequent APU <NUM> to the CPU <NUM>, via a second dielectric waveguide <NUM> connecting the CPU <NUM> to the first APU in the stripe.

In some embodiments, this looping back at the APU <NUM> may be performed by looping the RF test signal from one dielectric waveguide in the APU <NUM> to another over the air, utilizing multiple antennas in the APU <NUM>. As discussed above, an APU <NUM> may be equipped with dual-polarized antennas. In these embodiments, the RF test signal may be received by the APU <NUM> via a first dielectric waveguide interface and then transmitted by the APU <NUM> using an antenna (or antennas) of a first polarization. The same APU <NUM> in these embodiments may then receive the RF test signal using an antenna (or antennas) of a second polarization, and then send the received RF test signal back towards the CPU <NUM> via a second dielectric waveguide interface.

This is shown in <FIG>, which illustrates an example APU <NUM>, comprising parts A and B, with parts A and B having different antenna polarizations. The RF test signal is input to the dielectric waveguide <NUM> on the left-hand side (CPU-facing side) of APU <NUM> part A, and is then forwarded by the waveguide interface circuitry <NUM> of APU <NUM> part A to the the antenna circuitry <NUM> of APU <NUM> part A, where it is transmitted over the air. The transmitted RF test signal is received by antenna circuitry <NUM> of APU <NUM> part B, and forwarded to the dielectric waveguide interface circuitry <NUM> of APU <NUM> part B, which then transmits it back towards the CPU, via the dielectric waveguide <NUM> on the left-hand (CPU-facing) side of APU <NUM> part B. A simplified view of this loopback path is shown in <FIG>, which shows the RF test signal being looped back through the horizontal-polarization side of APU <NUM> to the vertical-polarization side, and then sent back towards the CPU.

An alternative to transmitting the RF test signal over the air is to provide APU <NUM> with a dedicated loopback switch <NUM>, as shown in <FIG>. With this approach, the antenna circuitry <NUM> in both APU <NUM> part A and B is not used. Rather, the RF test signal is input to the dielectric waveguide <NUM> on the left-hand side (CPU-facing side) of APU <NUM> part A, and is then forwarded by the waveguide interface circuitry <NUM> of APU <NUM> part A directly to the waveguide interface circuitry <NUM> of APU <NUM> part B, using loopback switch <NUM>. The dielectric waveguide interface circuitry <NUM> of APU <NUM> part B then transmits it back towards the CPU, via the dielectric waveguide <NUM> on the left-hand (CPU-facing) side of APU <NUM> part B.

The RF test signal has a bandwidth comparable to the RF signals that will be transmitted to and received from UEs served by the APUs <NUM>, so that the amplitude, phase, and delay response of the dielectric waveguides <NUM> can be estimated by the CPU <NUM> across the same frequency bandwidth utilized by UE RF signals, or at several discrete frequencies spanning this bandwidth.

The total phase/delay and amplitude response can then be estimated for the loop that comprises the two parallel wave guides - this phase/delay and amplitude response may be represented in the frequency domain as Hloop(s). The phase/amplitude response from the antenna coupling or switch can be characterized separately and removed from the response to derive a frequency response Hloop(s) that corresponds to the response of only the dielectric waveguides in the loop. The phase/delay and amplitude response HWG(s) for a single direction (outbound to the APU, or inbound from the APU to the CPU) is estimated by splitting the frequency response into two equal parts, based on the assumption that the two dielectric waveguides for a given link/hop have the same frequency response. This is a reasonable assumption in many cases, e.g., for dielectric waveguide pairs that are manufactured together, as a single component. This splitting of the two-way frequency response into a one-way frequency response HWG(s) is a simple operation when it is done in the frequency domain: <MAT> <MAT>.

The calibration technique described above can be done separately for each APU in a series of APUs. When it is performed for an APU that is beyond the first APU in the series, i.e., the APU closest to the CPU, the APUs between the CPU and the APU that is looping back the RF test signal are instructed, via control signaling from the CPU, to forward the RF test signal towards the loopback APU and to forward the looped-back RF test signal back towards the CPU.

The one-way frequency response for each APU so obtained can be used to determine compensation parameters, e.g., amplitude, phase, and/or delay compensation parameters, to correct for the frequency-dependent frequency response of the one-way path through the dielectric waveguides to a particular APU. The CPU may derive a frequency-dependent compensation function, in some embodiments, or a set of compensation parameters corresponding to several frequencies across the RF bandwidth of the RF test signal. These compensation functions or parameters are stored in the CPU In operation mode, RF signals transmitted to or received from a given APU can then be equalized, using the corresponding compensation parameters or function, to remove the amplitude and delay effects from the dielectric wave guide.

<FIG> is a block diagram illustrating functional elements of CPU <NUM>, as may be used during the calibration and compensation operations described above. A waveform defined in the frequency domain, by the waveform generator (WFG) block, is converted to time domain with an IFFT. After conversion to analog via a digital-to-analog converter (DAC), the signal is up-converted, using a mixer, amplified with a power amplifier (PA), and transmitted over the waveguide to the APU. The RF test signal sent via the dielectric waveguide is looped back, in the illustrated case using the loopback switch between the dielectric waveguide interface circuits in the APU. The APU transmits the looped-back RF test signal over the dielectric waveguide to the CPU, where the signal, after amplification by a low-noise amplifier (LNA), is downconverted with a mixer and digitized with an analog-to-digital converter (ADC). After conversion to the frequency domain, with an FFT, the baseband waveform obtained from the looped-back RF test signal can be compared to the waveform used to generate the originally transmitted RF test signal, using the "Diff" block shown in the figure. This "diff" block may comprise digital signal processing circuitry, in various embodiments.

<FIG> illustrates the setup when the first APU in a series of APUs is calibrated. For other APUs, the same principles apply, but all APUs between the CPU and the APU being calibrated will be set to repeat mode, so that the RF test signal is forwarded to the APU being calibrated and back again. The signal is repeated in the direction from CPU in one polarization and in the other polarization towards the CPU.

<FIG> illustrates essentially the same setup shown in <FIG>, except that the looping back of the RF test signal is performed over the air, as was described above in connection with <FIG> and <FIG>. The signal processing and control operations performed by the CPU are the same as discussed above.

In the description above, it has been described that the antenna in the APU is dual polarized. The techniques will also work if two antennas with same polarization are used. The use of dual-polarized antennas, however, will provide higher isolation between the two antennas in the APU, which will increase the likelihood for that the looped back signal will not compress the receiving LNA. Additionally, the description above assumes that each APU uses two dielectric waveguides in each direction of the stick/strip, one for each polarization. The techniques may also be used, of course, in implementations in which three or more dielectric waveguides are used in each direction.

<FIG> illustrates an example method of determining calibration parameters to correct for frequency responses of one or more dielectric waveguides coupling a control unit to a first antenna node or to a series of antenna nodes including the first antenna node. The illustrated method, which may be performed in a CPU, begins with transmitting, via a first dielectric waveguide coupling the control unit to the first antenna node, a radiofrequency (RF) test signal having a signal bandwidth covering a bandwidth of interest. This is shown at block <NUM>. The method further comprises receiving, via a second dielectric waveguide coupling the control unit to the first antenna node, a looped-back version of the transmitted RF test signal, as shown at block <NUM>. As shown at block <NUM>, the method further includes estimating a first one-way frequency response corresponding to the first (or second) dielectric waveguide, based on the RF test signal and the received loop-back version of the transmitted RF test signal.

In some embodiments or instances, this first one-way frequency response corresponding to the first dielectric waveguide represents an estimated frequency response for the first dielectric waveguide alone, i.e., when the RF test signal is looped back from the APU closest to the CPU in a serial chain of multiple APUs. The method may comprise sending a a control signal to this first antenna node, prior to transmitting the RF test signal, the control signal instructing the first antenna node to loop back the RF test signal. This is shown at block <NUM>.

In some embodiments, determining the first one-way frequency response corresponding to the first dielectric waveguide comprises determining a two-way frequency response based on the RF test signal and the received loop-back version of the transmitted RF test signal, adjusting the two-way frequency response to account for an estimated frequency response of a loop-back path in the first antenna node, and calculating the first one-way frequency response from the adjusted two-way frequency response based on an assumption that frequency responses corresponding to the first and second dielectric waveguides are equal. Mathematical details corresponding to this approach were provided in the detailed discussion above. In some of these embodiments, the estimated frequency response of the loop-back path in the first antenna node accounts for over-the-air coupling between at least a first antenna in the first antenna node, from which the RF test signal is transmitted over the air, and at least a second antenna in the first antenna node, at which the RF test signal is received after transmission over the air. These antennas may have first and second polarizations, respectively, the first and second polarizations being at least approximately orthogonal. In other embodiments, the estimated frequency response of the loop-back path in the first antenna node accounts for an estimated frequency response of a switched path coupling the first dielectric waveguide to the second dielectric waveguide, through the first antenna node.

In some embodiments, the method further comprises calculating an amplitude correction parameter and/or a phase correction parameter for each of two or more frequencies or frequency ranges within the bandwidth of interest, based on the first one-way frequency response. This is shown at block <NUM> of <FIG>. These parameters can be referred to as equalization, or "EQ," parameters. The method may further comprise, as shown at block <NUM>, applying the calculated amplitude correction parameters and/or phase correction parameters to RF signals subsequently sent to the first antenna node, via the first and/or second dielectric waveguide, for transmission by the first antenna node, and/or applying the calculated amplitude correction parameters and/or phase correction parameters to RF signals received from the first antenna node, via the first and/or second dielectric waveguide.

It was noted above that some embodiments or instances of the method illustrated in <FIG> may obtain a first one-way frequency response that corresponds to the first dielectric waveguide alone, i.e., to only the dielectric waveguide connecting the CPU to the closest APU. In other embodiments or instances, the APU looping back the RF test signal may be any of one or more APUs beyond that first APU in the serial chain. In these embodiments or instances, the first one-way frequency response corresponding to the first dielectric waveguide may instead represent an estimated frequency response for a series of two or more dielectric waveguides, the series comprising the first dielectric waveguide and one more additional waveguides between the first antenna node and each of one or more additional antenna nodes coupled in series with first antenna node, via respective ones of the one or more additional waveguides. Again, the method further comprises sending a control signal to this additional node at the end of said series, prior to transmitting the RF test signal, the control signal instructing the additional node at the end of said series to loop back the RF test signal.

As with the previously discussed embodiments, in those embodiments in which the RF test signal is being looped back from the additional antenna node (rather than the first antenna node in the series), estimating the first one-way frequency response corresponding to the first dielectric waveguide may comprise determining a two-way frequency response based on the RF test signal and the received loop-back version of the transmitted RF test signal, adjusting the two-way frequency response to account for a frequency response of a loop-back path in the additional antenna node from which the transmitted RF test signal is looped back, and calculating the first one-way frequency response from the adjusted two-way frequency response based on an assumption that frequency responses corresponding to the first and second dielectric waveguides are equal. Once again, the estimated frequency response of the loop-back path in the additional antenna node may account for over-the-air coupling between at least a first antenna in the additional antenna node, from which the RF test signal is transmitted over the air, and at least a second antenna in the additional antenna node, at which the RF test signal is received after transmission over the air, or may account for an estimated frequency response of a switched loopback path through the additional node.

As with the previously discussed examples, the method in these further embodiments may further comprise calculating an amplitude correction parameter and/or a phase correction parameters for each of two or more frequencies or frequency ranges within the bandwidth of interest, based on the first one-way frequency response, and applying the calculated amplitude correction parameters and/or phase correction parameters to RF signals subsequently sent to the additional antenna node from which the transmitted RF test signal is looped back, via the first and/or second dielectric waveguide, for transmission by the additional antenna node from which the transmitted RF test signal is looped back, and/or applying the calculated amplitude correction parameters and/or phase correction parameters to RF signals received from the additional antenna node from which the transmitted RF test signal is looped back, via the first and/or second dielectric waveguide.

In some embodiments, the steps shown in <FIG> may correspond to a first calibration that produces a first one-way frequency response corresponding to the first dielectric waveguide that represents an estimated frequency response for the first dielectric waveguide alone. As suggested above, the technique may be repeated for further nodes in the chain. In some of these embodiments, then, some or all of the steps of <FIG> are repeated. Thus, for example, the method may comprise re-transmitting the RF test signal via the first dielectric waveguide coupling the control unit to the first antenna node, i.e., repeating the step shown at block <NUM> of <FIG>, and receiving, via the second dielectric waveguide coupling the control unit to the first antenna node, a looped-back version of the retransmitted RF test signal, i.e., repeating the step shown at block <NUM> of <FIG>. In this case, however, the looped-back version is looped back from a further antenna node in the chain. Thus, when the step shown in block <NUM> is repeated, this amounts to estimating a second one-way frequency response corresponding to the first (or second) dielectric waveguide, based on the retransmitted RF test signal and the received loop-back version of the retransmitted RF test signal, the second one-way frequency response representing a frequency response for a series of two or more dielectric waveguides, the series comprising the first dielectric waveguide or the second dielectric waveguide and one more additional waveguides between the first antenna node and each of one or more additional antenna nodes coupled in series with first antenna node, via respective ones of the one or more additional waveguides.

<FIG> is a process flow diagram providing another illustration of an example method carried out by a CPU, according to some of the techniques described herein. The method begins with entering a "calibration mode. " This may be done upon system installation, for example, prior to use of the distributed transmission system, or may be carried out periodically or on demand, to ensure that the system remains well calibrated.

The method begins, as shown at block <NUM>, with an initialization step. Here, RF traffic to and from the APUs, if any, is halted, and a count variable X is set to zero. Next, the count variable is incremented to <NUM>. As shown at block <NUM>, APU #X is set into loopback mode, i.e., by sending a control signal or command to the APU. In the first iteration of the loop, APU #X is APU #<NUM>, i.e., the closest APU to the CPU in the serial chain of APUs. Of course, a CPU may be connected to more than one serial chain of APUs, in which case the method described here may be repeated for each of these chains.

As shown at block <NUM>, the CPU then transmits the RF test signal to APU #X, via a first waveguide coupling the CPU to APU#<NUM>. For this first iteration, the RF test signal is looped back by APU #<NUM>; in subsequent iterations the RF test signal is forwarded by APUs into the chain until it reaches APU #X, where it is looped back.

As shown at block <NUM>, the CPU receives the looped-back RF test signal via a second waveguide coupling the CPU to APU #<NUM>, and calculates frequency-dependent amplitude, phase, and delay responses. These are one-way responses, corresponding to either the outbound path, i.e., the one or more dielectric waveguides linking the CPU to APU #X as the RF test signal propagates to APU #X, or the inbound path, i.e., the one or more dielectric waveguides through which the looped-back RF test signal returns to the CPU. For many installations/applications, it can be reasonably assumed that the outbound and inbound responses are effectively equal; thus, the one-way response can be calculated accordingly.

As shown at block <NUM>, the calculated frequency-dependent amplitude, phase, and delay responses are used to determine and/or update equalization parameters for use when subsequently sending RF signals to and receiving RF signals from APU #X. These are stored for later use. Similarly, parameters for controlling a power amplifier (PA) driver gain and/or bias, for use when sending RF signals to APU #X, may be calculated. In some cases, these parameters may include parameters sent to APU #X for its use in controlling PA drivers when forwarding RF signals to a next APU or when sending signals towards the CPU.

The steps discussed above are repeated, for each APU in the chain, with each APU successively being instructed to loopback the RF test signal. When the paths for all the APUs have been calibrated, the system may begin (or resume) normal operation, as shown at block <NUM>.

<FIG> illustrates an example method carried out by a first antenna node coupled to an upstream antenna node or to a control unit via first and second dielectric waveguides and coupled to a downstream antenna node via third and fourth dielectric waveguides. This antenna node comprises (a) first radiofrequency (RF) circuitry and corresponding one or more antennas for selectively transmitting RF signals received via the first dielectric waveguide or receiving RF signals via the one or more antennas and coupling the received RF signals to the first dielectric waveguide, and (b) second RF circuitry and corresponding one or more antennas for selectively transmitting RF signals received via the second dielectric waveguide or receiving RF signals via the one or more antennas and coupling the received RF signals to the second dielectric waveguide. This first antenna node further comprises (c) third RF circuitry for selectively forwarding RF signals received via the first and second dielectric waveguides to the third and fourth dielectric waveguides or forwarding RF signals received via the third and fourth dielectric waveguides to the first and second dielectric waveguides. The example method comprises receiving, from the control unit or the upstream antenna node, a signal instructing the first antenna node to loopback an RF test signal, as shown at block <NUM>. The method further comprises, in response to the signal, looping back an RF test signal received via the first dielectric waveguide to the second dielectric waveguide. This is shown at block <NUM>.

In some embodiments, this looping back of the RF test signal comprises transmitting the RF test signal over the air, using the first RF circuitry and one or antennas corresponding to the first RF circuitry, and receiving the transmitted RF test signal, using the second RF circuitry and one or antennas corresponding to the second circuitry. In other embodiments, this looping back the RF test signal comprises routing the RF test signal from the first dielectric waveguide to the second dielectric waveguide via a loopback switch coupling the first dielectric waveguide to the second dielectric waveguide.

In some embodiments or instances, the method may further comprise receiving, from the control unit or the upstream antenna node, a second signal, the second signal instructing the first antenna node to repeat an RF test signal for a downstream antenna node. This is shown at block <NUM> of <FIG>. In these embodiments or instances, the method further comprises, in response to the second signal, forwarding RF signals received via the first dielectric waveguide to the third dielectric waveguide and forwarding RF signals received via the fourth waveguide to the second dielectric waveguide. It will be appreciated that this amounts to forwarding outbound RF signals in the outbound direction, i.e., to the next APU in the chain, and forwarding RF signals received from the next APU in the chain in an outbound direction, i.e., towards the CPU.

It will be appreciated that embodiments of the inventive concepts described herein include apparatuses that are adapted to carry out the methods and techniques described above. These apparatuses may take the form of a control node or CPU <NUM>, like that illustrated in <FIG>, and an antenna node or APU <NUM>, like that illustrated in <FIG>.

Thus, for example, an example control node <NUM> for determining calibration parameters to correct for frequency responses of one or more dielectric waveguides coupling the control node to a first antenna node or to a series of antenna nodes including the first antenna node may comprise first and second dielectric waveguide interfaces, each being configured to selectively transmit and receive radiofrequency, RF, signals via a respective dielectric waveguide, to and from a first antenna node. In <FIG>, these dielectric waveguide interfaces are shown combined as DWG interfaces <NUM>.

Control node <NUM> in these examples further comprise first RF circuitry operatively coupled to the first dielectric waveguide interface and configured to selectively transmit RF signals via the first dielectric waveguide interface or receive RF signals via the first dielectric waveguide interface, and second RF circuitry operatively coupled to the second dielectric waveguide interface and configured to selectively transmit RF signals via the second dielectric waveguide interface or receive RF signals via the first dielectric waveguide interface. The control node <NUM> further comprises baseband circuitry and upconversion circuitry configured to generate RF signals from baseband signals. In <FIG>, the baseband and RF circuitries are shown combined as baseband/radio processing circuitry <NUM>.

Control node <NUM> further comprises processing circuitry, illustrated as control circuitry <NUM> in <FIG>. This processing circuitry is operatively coupled to and configured to control the first and second RF circuitry, baseband circuitry, and upconversion circuitry to carry out one or more of the calibration methods described herein. Thus, the processing circuitry may control the CPU to transmit, via the first dielectric waveguide an RF test signal having a signal bandwidth covering a bandwidth of interest, to receive, via the second dielectric waveguide interface, a looped-back version of the transmitted RF test signal, and to estimate a first one-way frequency response corresponding to the first (or second) dielectric waveguide interface, based on the RF test signal and the received loop-back version of the transmitted RF test signal. The processing circuitry may be further configured to carry out any of the additional steps and/or variant techniques described herein, e.g., as described in connection with <FIG>.

Similarly, embodiments may include an antenna node, or APU, adapted to and/or configured to carry out one or more of the techniques described herein. An example is illustrated in <FIG>, where APU <NUM> comprises first and second dielectric waveguide interfaces, each being configured to selectively transmit and RF signals via a respective dielectric waveguide, to and from an upstream antenna node or control unit. In <FIG>, these first and second dielectric waveguide interfaces are in Part A and Part B, respectively, of the illustrated APU <NUM>, and face to the left (on Side <NUM>); these parts may correspond to first and second antenna polarizations, in some embodiments. APU <NUM> further comprises third and fourth dielectric waveguide interfaces, each being configured to selectively transmit and receive RF signals via a respective dielectric waveguide, to and from a downstream antenna node; these dielectric waveguide interfaces are oriented to the right in <FIG>, and are shown in <FIG> as combined with the rightward facing dielectric waveguide interfaces, as dielectric waveguide interfaces <NUM>.

APU <NUM> further comprises first RF circuitry and corresponding one or more first antennas configured to selectively transmit, over the air, RF signals received via the first dielectric waveguide interface or to receive RF signals via the one or more first antennas and couple the received RF signals to the first dielectric waveguide interfaces. Similarly, APU <NUM> comprises second RF circuitry and corresponding one or more second antennas configured to selectively transmit, over the air, RF signals received via the second dielectric waveguide interface or to receive RF signals via the one or more second antennas and couple the received RF signals to the second dielectric waveguide interface, as well as third RF circuitry configured to selectively (a) forward RF signals received via the first and second dielectric waveguide interfaces to the third and fourth dielectric waveguide interfaces respectively, and (b) forward RF signals received via the third and fourth dielectric waveguide interfaces to the first and second dielectric waveguide interfaces, respectively. In <FIG>, the first and second RF circuitry are shown as combined in antenna circuitry <NUM>, while the third RF circuitry forms part of the dielectric waveguide interface circuitry <NUM> shown in the figure. Further details of the RF and switching circuitry that may make up all of this RF circuitry are shown in <FIG>.

APU <NUM> comprises switching circuitry configured to, responsive to a control signal instructing the antenna node to loopback an RF test signal, loop back an RF test signal received via the first dielectric waveguide interface to the second dielectric waveguide interface. This switching circuitry may take various configurations, in different embodiments. In some embodiments, this switching circuitry forms from the dielectric waveguide interface circuitry to one or more transmitting antennas and then back again from one or more receiving antennas. Thus, the switching circuitry in an embodiment like that shown in <FIG> may comprise SW <NUM>, switch/combiner (S/C) <NUM>, S/C <NUM>, SW <NUM>, and SW <NUM>, in Part A of the APU <NUM>, e.g., to provide for transmission of the RF test signal over one or more horizontally polarized antennas. The switching circuitry in these embodiments will comprise the same switches on Part B, but oriented to route a signal received via one or more antennas on the Part B side of APU <NUM> to the dielectric waveguide interface circuitry and back towards the CPU.

APU <NUM> and variations thereof may be configured to carry out any of the APU-related methods and techniques described herein, including those described above in connection with <FIG>.

Claim 1:
A method of determining calibration parameters to correct for frequency responses of one or more dielectric waveguides coupling a control unit to a first antenna node or to a series of antenna nodes including the first antenna node, the method comprising:
transmitting (<NUM>), via a first dielectric waveguide coupling the control unit to the first antenna node, a radiofrequency, RF, test signal having a signal bandwidth covering a bandwidth of interest;
receiving (<NUM>), via a second dielectric waveguide coupling the control unit to the first antenna node, a looped-back version of the transmitted RF test signal; and
estimating (<NUM>) a first one-way frequency response corresponding to the first dielectric waveguide, based on the RF test signal and the received loop-back version of the transmitted RF test signal, said first one-way frequency response representing an estimated frequency response for the first dielectric waveguide alone,
wherein estimating the first one-way frequency response corresponding to the first dielectric waveguide comprises determining a two-way frequency response based on the RF test signal and the received loop-back version of the transmitted RF test signal, adjusting the two-way frequency response to account for an estimated frequency response of a loop-back path in the first antenna node, and calculating the first one-way frequency response from the adjusted two-way frequency response based on an assumption that frequency responses corresponding to the first and second dielectric waveguides are equal.