Patent Description:
As the information society advances, various demands for display apparatuses for displaying images have increased. Moreover, display apparatuses have become thinner and lighter, and thus, the usage thereof has expanded.

Techniques to decrease a peripheral area, a so-called dead space, have been developed in order to increase a size of a display area in a display apparatus.

<CIT> discloses an organic light emitting diode display device having a display area and a non-display area around the display area. The conductive wire includes a lower layer disposed adjacent to the substrate, an upper layer disposed over the lower layer, and an intermediate layer between the upper layer and the lower layer. Both sides of the upper layer may overlap the upper surface of the lower layer. The propagation time of moisture permeation along the edge of the conductive wire is delayed and the possibility of damage to the conductive wire is reduced, thus improving the lifespan and reliability of the display panel and preventing the possibility of image quality defects.

<CIT> discloses a display device having improved reliability including a substrate, a display area, and a peripheral area outside the display area. The reliability of the display device is improved by preventing propagation of cracks.

<CIT> discloses a display unit and a method for fabricating the same a wiring layer in a semiconductor layer on a substrate, and a first electrically conductive layer in a terminal section, where the first electrically conductive layer is made of a material same as a material of the wiring layer, formed as a continuous film.

According to the present invention, a display apparatus has a reduced dead space and display a high-quality image. However, the scope of the present invention is not limited to this effect as described above.

The present invention is defined by the features of the independent claims directed to a display apparatus and a method of manufacturing a display apparatus. Additional aspects are disclosed in the dependent claims and will be set forth in part in the description which follows and, in part, will be apparent from the description or may be learned by practice of the embodiments of the present invention.

In one or more embodiments, the conductive pattern may extend in a first direction, and the conductive pattern may include protrusion patterns protruding in a second direction crossing the first direction.

In one or more embodiments, the display apparatus may further include a dam portion and a bank in the peripheral area, wherein the adhesion area is between the dam portion and the bank.

The display apparatus according to the present invention further includes a first connection pattern in the display area, a first organic insulating layer on the first connection pattern, a second connection pattern on the first organic insulating layer, a second organic insulating layer on the second connection pattern, a third connection pattern on the second organic insulating layer, and a third organic insulating layer on the third connection pattern.

In the present invention, the conductive pattern is at a same layer as the first connection pattern, the second connection pattern, or the third connection pattern.

In the present invention, the conductive pattern is at a same layer as the first connection pattern.

In one or more embodiments, the third conductive layer and the cover layer may include a same material as each other.

In one or more embodiments, the second connection pattern may include a fourth layer, a fifth layer, and a sixth layer that are sequentially stacked, and the cover layer may include a same material as the fourth layer.

In one or more embodiments, the removing of the portion of the protection layer may include forming a second organic insulating layer on the second connection pattern, forming a third pattern material on the second organic insulating layer and the protection layer, forming a third connection pattern by etching the third pattern material on the second organic insulating layer and removing the third pattern material on the protection layer, the second protection layer of the protection layer, and a portion of the first protection layer of the protection layer, forming a third organic insulating layer on the third connection pattern, forming a fourth pattern material on the third organic insulating layer and the first protection layer, and forming a pixel electrode by etching the fourth pattern material on the third organic insulating layer and removing the fourth pattern material on the first protection layer and remaining portions of the first protection layer.

In one or more embodiments, the cover layer and the second protection layer may include the same material as each other, and the cover layer and the first protection layer may include different materials from each other.

In one or more embodiments, the method may further include, after removing the portion of the protection layer, forming a first inorganic encapsulation layer and a second inorganic encapsulation layer on the cover layer.

In one or more embodiments, the first inorganic encapsulation layer in the adhesion area may directly contact the cover layer and the second inorganic encapsulation layer.

In one or more embodiments, the method may further include a dam portion and a bank in the peripheral area, wherein the adhesion area is between the dam portion and the bank.

The above and other aspects, features, and/or principles of various embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:.

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present invention. Throughout the present invention, the expression "at least one of a, b or c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

While the present invention is capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. Effects and characteristics of the present invention, and realized methods thereof will become apparent by referring to the drawings and embodiments described in detail below. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present invention may not be described. However, the present invention is not limited to the embodiments disclosed hereinafter and may be realized in various forms.

It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

As used herein, the singular expressions "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "include," "including," "comprises" and/or "comprising" used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region, or element is referred to as being formed "on," "connected to," or "coupled to" another layer, area, or element, it can be directly or indirectly formed on, connected to, or coupled to the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. For example, sizes and thicknesses of the elements in the drawings are indicated for convenience of explanation, and thus, the invention is not necessarily limited to the illustrations of the drawings.

In this specification, the expression "A and/or B" may indicate A, B, or A and B. Also, in this specification, the expression "at least one of A and B" may indicate A, B, or A and B.

In embodiments described hereinafter, "lines extending in a first direction or a second direction" denotes not only the lines extending as a linear shape, but also the lines extending in the first direction or the second direction as a zig-zag shape or a circular shape.

In the embodiments hereinafter, the expression "planar" indicates a shape when an object is seen downwardly, and the expression "cross-sectional" indicates a shape when an object, which is vertically taken, is seen from the lateral perspective. In the embodiments below, when a part is referred to as "overlapping," the part may be "planarly" or "cross-sectionally" overlapping.

Spatially relative terms, such as "beneath," "below," "lower," "under," "above," "upper," and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

As used herein, the term "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention. " As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

Also, when the descriptions are given by referring to the drawings, the same elements or the corresponding elements will be referred to by using the same reference numerals.

<FIG> is a schematic plan view of a display apparatus according to one or more embodiments. A plan view, as used in the present specification, may correspond to a state in which the device or portion of the device is viewed in a z-direction.

Referring to <FIG>, the display apparatus may include a display panel <NUM>. The display apparatus may refer to all types of display apparatuses that include the display panel <NUM> described in more detail below. For example, the display apparatus may include various products, such as a smartphone, a tablet, a laptop, a television, or an advertising board.

The display panel <NUM> includes a display area DA and a peripheral area PA outside the display area DA. The display area DA is configured to display an image, and a plurality of pixels P may be arranged in the display area DA. From a direction approximately perpendicular to the display panel <NUM> (e.g., in a plan view), the display area DA may have various shapes including a circular shape, an oval shape, a polygonal shape, and/or any other suitable shape (e.g., a predetermined shape). <FIG> illustrates that the display area DA may approximately have a square shape. However, the present invention is not limited thereto. For example, the display area DA may approximately have a round-edged square shape.

The peripheral area PA is arranged outside the display area DA. The peripheral area PA may completely surround (or may be around) the display area DA. The peripheral area PA is configured to not display an image, and driving circuits, lines, etc. configured to drive the pixels P in the display area DA may be arranged in the peripheral area PA.

According to one or more embodiments, at least a portion of the peripheral area PA, the portion being at a lower portion of the display area DA, may be bent. When the display panel <NUM> is bent, the peripheral area PA, which is a non-display area, may not be visible, when viewing the display apparatus, or even when the peripheral area PA is visible, a visible area thereof may be minimized.

A shape of the display panel <NUM> described above may be substantially the same as a shape of the substrate <NUM>. It is to be understood that the substrate <NUM> includes the display area DA and the peripheral area PA. Hereinafter, for convenience, it is described that the substrate <NUM> may include the display area DA and the peripheral area PA.

The pixel P may be arranged in the display area DA and may emit red, green, and/or blue light. For example, the pixel P may emit a desirable color (e.g., a predetermined color) of light by using a light-emitting diode configured to emit light. The light-emitting diode may include an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot light-emitting diode. Hereinafter, for convenience of explanation, it is described that the light-emitting diode may correspond to an organic light-emitting diode.

The light-emitting diode may be connected to transistors that are connected to signal lines or a voltage line configured to control on/off and brightness of the light-emitting diode. Regarding this aspect, <FIG> illustrates the signal lines connected to the transistors, such as a scan line SL, an emission control line EL, a data line DL, and the voltage line, such as a driving voltage line PL. In the peripheral area PA, a common voltage supply line <NUM>, a driving voltage supply line <NUM>, a first driving circuit <NUM>, a second driving circuit <NUM>, and a data driving circuit <NUM> may be arranged.

The common voltage supply line <NUM> may be arranged in the peripheral area PA. The common voltage supply line <NUM> may include a first common voltage supply line <NUM>, a second common voltage supply line <NUM>, and a body portion <NUM>. The first common voltage supply line <NUM> and the second common voltage supply line <NUM> may be arranged adjacent to a first edge E1 of the display area DA. The first common voltage supply line <NUM> and the second common voltage supply line <NUM> may extend in a first direction (for example, a y direction). Also, the first common voltage supply line <NUM> and the second common voltage supply line <NUM> may be arranged apart from each other in a second direction (for example, an x direction) crossing the first direction (for example, the y direction). The first common voltage supply line <NUM> and the second common voltage supply line <NUM> may be arranged at both sides of the first edge E1 of the display area DA, respectively (e.g., the first common voltage supply line <NUM> may be at one side of the first edge E1 and the second common voltage supply line <NUM> may be at the other side of the first edge E1). However, the present invention is not limited thereto. The common voltage supply line <NUM> may further include a third common voltage supply line arranged between the first common voltage supply line <NUM> and the second common voltage supply line <NUM>. When the common voltage supply line <NUM> includes the third common voltage supply line arranged between the first common voltage supply line <NUM> and the second common voltage supply line <NUM>, the common voltage supply line <NUM> may further reduce a current density when applying currents and may further suppress (or reduce) heating, compared to when the common voltage supply line <NUM> includes only the first common voltage supply line <NUM> and the second common voltage supply line <NUM>.

The first common voltage supply line <NUM> and the second common voltage supply line <NUM> may be connected with each other via the body portion <NUM> extending along a second edge E2, a third edge E3, and a fourth edge E4 of the display area DA. According to one or more embodiments, the first common voltage supply line <NUM>, the second common voltage supply line <NUM>, and the body portion <NUM> may be integrally formed.

According to one or more embodiments, the driving voltage supply line <NUM> may include a first driving voltage supply line <NUM>, a second driving voltage supply line <NUM>, and a third driving voltage supply line <NUM>. The first driving voltage supply line <NUM> and the second driving voltage supply line <NUM> may extend in the first direction (for example, the y direction), and the third driving voltage supply line <NUM> may extend in the second direction (for example, the x direction). For example, the third driving voltage supply line <NUM> may be arranged along the first edge E1 of the display area DA. According to one or more embodiments, the first driving voltage supply line <NUM>, the second driving voltage supply line <NUM>, and the third driving voltage supply line <NUM> may be integrally formed. However, the present invention is not limited thereto.

The driving voltage supply line <NUM> may be arranged in the peripheral area PA and may be electrically connected to the driving voltage line PL crossing the display area DA in the first direction (for example, the y direction). That is, the third driving voltage supply line <NUM> may be electrically connected to the driving voltage line PL crossing the display area DA in the first direction (for example, the y direction).

The first driving circuit <NUM> and the second driving circuit <NUM> may be arranged in the peripheral area PA and may be electrically connected to the scan lines SL and/or the emission control line EL. According to one or more embodiments, some of the scan lines SL may be electrically connected to the first driving circuit <NUM>, and the others may be electrically connected to the second driving circuit <NUM>. The first driving circuit <NUM> and the second driving circuit <NUM> may be configured to generate a scan signal, and the generated scan signal may be transmitted to the transistor electrically connected to the light-emitting diode through the scan lines SL. According to one or more embodiments, any one of the first and second driving circuits <NUM> and <NUM> may include an emission control driving circuit. For example, as illustrated in <FIG>, the first driving circuit <NUM> may include an emission control driving circuit and may be configured to transmit an emission control signal to the transistor electrically connected to the light-emitting diode through the emission control line EL. <FIG> illustrates that the emission control driving circuit is arranged at one side of the display area DA. However, the emission control driving circuit may be arranged at both sides of the display area DA.

The data driving circuit <NUM> may be arranged in the peripheral area PA at a lower side of the display area DA. The data driving circuit <NUM> may be configured to transmit a data signal to the transistor electrically connected to the light-emitting diode through the data line DL.

A first pad portion TD1 may be arranged at a side of the substrate <NUM>, for example, at an end of the peripheral area PA. A printed circuit board <NUM> may be coupled on (or to) the first pad portion TD1. The printed circuit board <NUM> may include a second pad portion TD2 electrically connected to the first pad portion TD1. A controller <NUM> may be arranged on the printed circuit board <NUM>. Control signals of the controller <NUM> may be supplied to each of the first and second driving circuits <NUM> and <NUM>, the data driving circuit <NUM>, the driving voltage supply line <NUM>, and the common voltage supply line <NUM> through the first and second pad portions TD1 and TD2.

<FIG> is a schematic plan view of a portion of a display apparatus according to one or more embodiments of the present invention. The embodiments illustrated in <FIG> differ from the embodiments illustrated in <FIG> in that the display panel <NUM> may further include an opening area OA and a middle area MA, in addition to the display area DA and the peripheral area PA outside the display area DA. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the display panel <NUM> includes the display area DA and the peripheral area PA outside the display area DA. Also, the display panel <NUM> may further include the opening area OA and the middle area MA.

According to one or more embodiments, the display area DA may at least partially surround (or be around) the opening area OA. The middle area MA may be between the display area DA and the opening area OA. In a plan view, the middle area MA may be closed-loop shaped, completely surrounding (or around) the opening area OA.

The opening area OA may be at an inner side of the display area DA. According to one or more embodiments, the opening area OA may be arranged at an upper right side of the display area DA as illustrated in <FIG>. In one or more embodiments, the opening area OA may be arranged at an upper left side or an upper middle side of the display area DA. Like this, the opening area OA may be arranged in various manners. <FIG> illustrates that one opening area OA is arranged. However, the present invention is not limited thereto. For example, a plurality of opening areas OA may be arranged.

Also, in one or more embodiments, a component may be arranged below the opening area OA. The component may include an electronic element. For example, the component may include an electronic element using light or sound. For example, the electronic element may include a sensor configured to use light, such as an infrared sensor, a camera configured to receive light and capture an image, a sensor configured to measure a distance or recognize a fingerprint, etc. by outputting and sensing light or sound, a small lamp configured to output light, a speaker configured to output sound, etc. The electronic element using light may use pieces of light of various wavelength ranges, such as visible rays, infrared rays, ultraviolet rays, etc. The opening area OA may correspond to an area through which light and/or sound output from the component to the outside or proceeding from the outside toward the electronic element is transmitted.

<FIG> is a schematic equivalent circuit diagram of a pixel circuit PC electrically connected to a light-emitting diode corresponding to a pixel of a display apparatus according to one or more embodiments of the present invention.

The pixel circuit PC may include a plurality of thin-film transistors T1 through T7 and a storage capacitor Cst as illustrated in <FIG>. The plurality of thin-film transistors T1 through T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL, and DL, a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL. At least one of these lines described above, for example, the driving voltage line PL, may be shared by adjacent pixel circuits PC.

According to one or more embodiments, the plurality of thin-film transistors T1 through T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7. However, the present invention is not limited thereto.

An organic light-emitting diode OLED may include a pixel electrode and an opposite electrode. Through the emission control transistor T6, the pixel electrode of the organic light-emitting diode OLED may be connected to the driving transistor T1 and receive a driving current, and the opposite electrode of the organic light-emitting diode OLED may receive a common voltage ELVSS. The organic light-emitting diode OLED may generate the light having a brightness according to the driving current.

One or more of the plurality of thin-film transistors T1 through T7 may be provided as n-channel metal-oxide semiconductor field-effect transistors (MOSFETs) (NMOS), and the others may be provided as p-channel MOSFETs (PMOS). For example, the compensation transistor T3 and the first initialization transistor T4 from among the plurality of thin-film transistors T1 through T7 may be provided as NMOS transistors, and the others may be provided as PMOS transistors. In one or more embodiments, the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 from among the plurality of thin-film transistors T1 through T7 may be provided as NMOS transistors, and the others may be provided as PMOS transistors. In one or more embodiments, all of the plurality of thin-film transistors T1 through T7 may be provided as NMOS transistors or PMOS transistors. The plurality of thin-film transistors T1 through T7 may include amorphous silicon or polysilicon. The NMOS thin-film transistors may include oxide semiconductors. Hereinafter, for convenience, a case in which the compensation transistor T3 and the first initialization transistor T4 are NMOS transistors including oxide semiconductors, and the others are PMOS transistors is described.

The signal lines may include a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line SLn, an emission control line EL, and a data line DL. However, the present invention is not limited thereto. Also, the first scan line SL1 may be configured to transmit a first scan signal Sn. The second scan line SL2 may be configured to transmit a second scan signal Sn'. The previous scan line SLp may be configured to transmit a previous scan signal Sn-<NUM> to the first initialization transistor T4. The next scan line SLn may be configured to transmit a next scan signal Sn+<NUM> to the second initialization transistor T7. The emission control line EL may be configured to transmit an emission control signal En to the operation control transistor T5 and the emission control transistor T6. The data line DL may be configured to transmit a data signal Dm.

The driving voltage line PL may be configured to transmit a driving voltage ELVDD to the driving transistor T1, the first initialization voltage line VL1 may be configured to transmit a first initialization voltage Vint1 for initializing the driving transistor T1, and the second initialization voltage line VL2 may be configured to transmit a second initialization voltage Vint2 for initializing the pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode of the driving transistor T1 may be connected to the storage capacitor Cst via a second node N2. Also, any one of a source area and a drain area of the driving transistor T1 may be connected to the driving voltage line PL through the operation control transistor T5 via a first node N1, and the other may be electrically connected to the pixel electrode of the organic light-emitting diode OLED through the emission control transistor T6 via a third node N3. The driving transistor T1 may be configured to receive the data signal Dm according to a switching operation of the switching transistor T2 and to supply the driving current to the organic light-emitting diode OLED. That is, according to a voltage applied to the second node N2, the voltage varying according to the data signal Dm, the driving transistor T1 may be configured to control the amount of currents flowing from the first node N1 electrically connected to the driving voltage line PL to the organic light-emitting diode OLED.

A switching gate electrode of the switching transistor T2 may be connected to the first scan line SL1 configured to transmit the first scan signal Sn. Either a source area or a drain area of the switching transistor T2 may be connected to the data line DL, and the other may be connected to the driving transistor T1 via the first node N1 and may be connected to the driving voltage line PL through the operation control transistor T5. The switching transistor T2 may be configured to transmit the data signal Dm from the data line DL to the first node N1, according to a voltage applied to the first scan line SL1. That is, the switching transistor T2 may be turned on in response to the first scan signal Sn received through the first scan line SL1 and may be configured to perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving transistor T1 via the first node N1.

A compensation gate electrode of the compensation transistor T3 may be connected to the second scan line SL2. A source area or a drain area of the compensation transistor T3 may be connected to the pixel electrode of the organic light-emitting diode OLED through the emission control transistor T6 via the third node N3. The other of the source area and the drain area of the compensation transistor T3 may be connected to a first capacitor electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 via the second node N2. The compensation transistor T3 may be turned on in response to the second scan signal Sn' received through the second scan line SL2 and may diode-connect the driving transistor T1.

A first initialization gate electrode of the first initialization transistor T4 may be connected to the previous scan line SLp. A source area or a drain area of the first initialization transistor T4 may be connected to the first initialization voltage line VL1. The other of the source area and the drain area of the first initialization transistor T4 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst, the driving gate electrode of the driving transistor T1, etc. via the second node N2. The first initialization transistor T4 may be configured to apply the first initialization voltage Vint1 from the first initialization voltage line VL1 to the second node N2, according to a voltage applied to the previous scan line SLp. That is, the first initialization transistor T4 may be turned on in response to the previous scan signal Sn-<NUM> received through the previous scan line SLp and may be configured to perform an initialization operation of initializing a voltage of the driving gate electrode of the driving transistor T1 by transmitting the initialization voltage Vint1 to the driving gate electrode of the driving transistor T1.

An operation control gate electrode of the operation control transistor T5 may be connected to the emission control line EL, and a source area or a drain area of the operation control transistor T5 may be connected to the driving voltage line PL and the other may be connected to the driving transistor T1 and the switching transistor T2 via the first node N1.

An emission control gate electrode of the emission control transistor T6 may be connected to the emission control line EL, and a source area or a drain area of the emission control transistor T6 may be connected to the driving transistor T1 and the compensation transistor T3 via the third node N3, and the other may be electrically connected to the pixel electrode of the organic light-emitting diode OLED.

The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on in response to the emission control signal En received through the emission control line EL so that the driving voltage ELVDD may be transmitted to the organic light-emitting diode OLED, and the driving current may flow in the organic light-emitting diode OLED.

A second initialization gate electrode of the second initialization transistor T7 may be connected to the next scan line SLn, and a source area or a drain area of the second initialization transistor T7 may be connected to the pixel electrode of the organic light-emitting diode OLED, and the other may be connected to the second initialization voltage line VL2 and may receive the second initialization voltage Vint2. The second initialization transistor T7 may be turned on in response to the next scan signal Sn+<NUM> received through the next scan line SLn and may be configured to initialize the pixel electrode of the organic light-emitting diode OLED. The next scan line SLn may be the same as the first scan line SL1. In this case, by transmitting the same electrical signals to the corresponding scan line SL with a time interval between the electrical signals, the corresponding scan line may be configured to function as the first scan line SL1 and the next scan line SLn. That is, the next scan line SLn may be the first scan line SL1 of a different pixel circuit, which is adjacent to the pixel circuit PC illustrated in <FIG> and is connected to the same data line DL as the pixel circuit PC.

The storage capacitor Cst may include the first capacitor electrode CE1 and the second capacitor electrode CE2. The first capacitor electrode CE1 of the storage capacitor Cst may be connected to the driving gate electrode of the driving transistor T1 via the second node N2, and the second capacitor electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may be configured to store a charge corresponding to a difference between a driving gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD.

A detailed operation of the pixel circuit PC and the organic light-emitting diode OLED, according to one or more embodiments of the present invention, is described in more detail below.

During an initialization period, when the previous scan signal Sn-<NUM> is supplied through the previous scan line SLp, the first initialization transistor T4 may be turned on in response to the previous scan signal Sn-<NUM>, and the driving transistor T1 may be initialized via the first initialization voltage Vint1 supplied from the first initialization voltage line VL1.

During a data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2, the switching transistor T2 and the compensation transistor T3 may be turned on in response to the first scan signal Sn and the second scan signal Sn'. Here, the driving transistor T1 may be diode-connected by the compensation transistor T3 that is turned on and may be biased in a forward direction. Then, a compensation voltage Dm+Vth (Vth has a negative (-) value) obtained by subtracting a threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied from the data line DL may be applied to the driving gate electrode of the driving transistor T1. The driving voltage ELVDD and the compensation voltage Dm+Vth may be applied to both ends of the storage capacitor Cst, and a charge corresponding to a difference between the voltages of both ends of the storage capacitor Cst may be stored in the storage capacitor Cst.

During an emission period, the operation control transistor T5 and the emission control transistor T6 may be turned on in response to the emission control signal En supplied from the emission control line EL. A driving current according to a voltage difference between a voltage of the driving gate electrode of the driving transistor T1 and the driving voltage ELVDD may occur, and the driving current may be supplied to the organic light-emitting diode OLED through the emission control transistor T6.

As described above, one or more of the plurality of thin-film transistors T1 through T7 may include oxide semiconductors. For example, the compensation transistor T3 and the first initialization transistor T4 may include oxide semiconductors. However, the present invention is not limited thereto.

Polysilicon is highly reliable, and thus, the flow of currents for which precision is desired may controlled by polysilicon. Thus, the driving transistor T1 directly affecting brightness of a display apparatus may include a semiconductor layer including polysilicon that is highly reliable, to realize a display apparatus having high resolution. An oxide semiconductor may have a high carrier mobility and a low leakage current, and thus, even when a driving time is increased, a voltage drop may be insignificant. That is, in the case of an oxide semiconductor, even during low frequency driving, a color change of an image due to a voltage drop may be insignificant. Accordingly, low frequency driving may be possible. Thus, the compensation transistor T3 and the first initialization transistor T4 may include the oxide semiconductor, to realize a display apparatus in which leakage currents are prevented (or substantially prevented) and power consumption is reduced.

However, the oxide semiconductor is sensitive to light, and thus, the amount of currents may be changed, etc., due to external light. Thus, a metal layer may be arranged below the oxide semiconductor to absorb or reflect the light from the outside. Accordingly, as illustrated in <FIG>, a gate electrode may be arranged both above and below an oxide semiconductor layer of each of the compensation transistor T3 and the first initialization transistor T4 that include the oxide semiconductor. That is, from a direction (for example, a z axis direction) perpendicular to an upper surface of the substrate <NUM>, a metal layer arranged below the oxide semiconductor may overlap the oxide semiconductor.

<FIG> is a schematic cross-sectional view of a light-emitting diode of a display apparatus and a pixel circuit PC electrically connected to the light-emitting diode, according to one or more embodiments of the present invention.

Referring to <FIG>, an organic light-emitting diode OLED may be arranged in the display area DA, wherein the organic light-emitting diode OLED may be electrically connected to the pixel circuit PC arranged between the substrate <NUM> and the organic light-emitting diode OLED in a direction (for example, a z axis direction) that is perpendicular to the substrate <NUM>.

The substrate <NUM> may include glass materials or polymer resins. According to one or more embodiments, the substrate <NUM> may have a stack structure in which a base layer including polymer resins and a barrier layer including an inorganic insulating material, such as silicon oxide or silicon nitride, are alternately stacked. For example, the substrate <NUM> may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d that are sequentially stacked. The first base layer 100a and the second base layer 100c may include polymer resins, and the first barrier layer 100b and the second barrier layer 100d may include an inorganic insulating material. The polymer resins may include polyether sulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and/or cellulose acetate propionate.

A buffer layer <NUM> may be arranged on the substrate <NUM>. The buffer layer <NUM> may reduce or prevent the penetration of impurities, moisture, and/or external substances from below the substrate <NUM>. The buffer layer <NUM> may include an inorganic material, such as silicon oxide (SiOx), silicon oxynitride (SiON), and/or silicon nitride (SiNx), and may include a single layer or multiple layers including the inorganic material(s) described above.

As described above with reference to <FIG>, the pixel circuit PC may include a plurality of transistors and a storage capacitor. With respect to this configuration, <FIG> illustrates the driving transistor T1, the compensation transistor T3, and the storage capacitor Cst.

The driving transistor T1 may include a semiconductor layer (hereinafter, referred to as a driving semiconductor layer A1) on the buffer layer <NUM> and a driving gate electrode GE1 overlapping a channel area C1 of the driving semiconductor layer A1. The driving semiconductor layer A1 may include a silicon-based semiconductor material, for example, polysilicon. The driving semiconductor layer A1 may include the channel area C1 and a first area B1 and a second area D1 arranged at opposing sides of the channel area C1, respectively. The first area B1 and the second area D1 may include more highly concentrated impurities than the channel area C1, and one of the first area B1 and the second area D1 may correspond to a source area, and the other may correspond to a drain area.

A first gate insulating layer <NUM> may be arranged between the driving semiconductor layer A1 and the driving gate electrode GE1. The first gate insulating layer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, and may include a single layer or multiple layers including the inorganic insulating material(s) described above.

The driving gate electrode GE1 may include a conductive material including Mo, Al, Cu, Ti, and/or other suitable material(s), and may include a single layer or multiple layers including the conductive material(s) described above.

The storage capacitor Cst may include the first capacitor electrode CE1 and the second capacitor electrode CE2 overlapping each other. According to one or more embodiments, the first capacitor electrode CE1 of the storage capacitor Cst may include the driving gate electrode GE1. In other words, the driving gate electrode GE1 may include the first capacitor electrode CE1 of the storage capacitor Cst. For example, the driving gate electrode GE1 and the first capacitor electrode CE1 may be integrally formed.

A first interlayer insulating layer <NUM> may be arranged between the first capacitor electrode CE1 and the second capacitor electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, and may include a single layer or multiple layers including the inorganic insulating material(s) described above.

The second capacitor electrode CE2 of the storage capacitor Cst may include a low resistance conductive material, such as Mo, Al, Cu, and/or Ti, and may include a single layer or multiple layers including the material(s) described above.

A second interlayer insulating layer <NUM> may be arranged on the storage capacitor Cst. The second interlayer insulating layer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, and may include a single layer or multiple layers including the inorganic insulating material(s) described above.

A semiconductor layer (hereinafter, referred to as a compensation semiconductor layer A3) of the compensation transistor T3 may be arranged on the second interlayer insulating layer <NUM>. The compensation semiconductor layer A3 may include an oxide-based semiconductor material. For example, the compensation semiconductor layer A3 may include a Zn oxide-based material, for example, a Zn oxide, an In-Zn oxide, a Ga-In-Zn oxide, and/or other suitable material(s). In one or more embodiments, the compensation semiconductor layer A3 may include a semiconductor including In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), and/or In-Ga-Sn-Zn-O (IGTZO), in which a metal, such as In, Ga, or Sn, is included in ZnO.

The compensation semiconductor layer A3 may include a channel area C3, and a third area B3 and a fourth area D3 arranged at respective sides of the channel area C3. One of the third area B3 and the fourth area D3 may correspond to a source area, and the other may correspond to a drain area.

The compensation transistor T3 may include a compensation gate electrode GE3 overlapping the channel area C3 of the compensation semiconductor layer A3. The compensation gate electrode GE3 may have a dual gate structure including a lower gate electrode G3A arranged below the compensation semiconductor layer A3 and an upper gate electrode G3B arranged above the channel area C3.

The lower gate electrode G3A may be arranged on the same layer (for example, the first interlayer insulating layer <NUM>) as the second capacitor electrode CE2 of the storage capacitor Cst. The lower gate electrode G3A may include the same material as the second capacitor electrode CE2 of the storage capacitor Cst.

The upper gate electrode G3B may be arranged on the compensation semiconductor layer A3 with a second gate insulating layer <NUM> therebetween. The second gate insulating layer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, and may include a single layer or multiple layers including the inorganic insulating material(s) described above.

A third interlayer insulating layer <NUM> may be arranged on the upper gate electrode G3B. The third interlayer insulating layer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, and may include a single layer or multiple layers including the inorganic insulating material(s) described above.

The driving transistor T1 and the compensation transistor T3 may be electrically connected to each other through a first connection pattern <NUM>. The first connection pattern <NUM> may be arranged on the third interlayer insulating layer <NUM>. A side of the first connection pattern <NUM> may be connected to the driving gate electrode GE1 of the driving transistor T1, and the other side of the first connection pattern <NUM> may be connected to the compensation semiconductor layer A3 of the compensation transistor T3. However, the present invention is not limited thereto. The first connection pattern <NUM> may denote a line or a conductive layer arranged on the third interlayer insulating layer <NUM>.

The first connection pattern <NUM> may include Al, Cu, and/or Ti and includes multiple layers including the material(s) described above. For example, the first connection pattern <NUM> may have a triple-layered structure of a Ti layer/an Al layer/a Ti layer. This aspect is described in more detail with reference to <FIG>.

A first organic insulating layer <NUM> may be arranged on the first connection pattern <NUM>. The first organic insulating layer <NUM> may include an organic insulating material. The organic insulating material may include acryl, benzocyclobutene (BCB), polyimide, and/or hexamethyldisiloxane (HMDSO).

A second connection pattern <NUM> may be arranged on the first organic insulating layer <NUM>. The second connection pattern <NUM> may include Al, Cu, and/or Ti and may include a single layer or multiple layers including the material(s) described above. For example, the second connection pattern <NUM> may have a triple-layered structure of a Ti layer/an Al layer/a Ti layer. This aspect is to be described in more detail with reference to <FIG>.

A second organic insulating layer <NUM> may be arranged on the second connection pattern <NUM>. The second organic insulating layer <NUM> may include an organic insulating material, such as acryl, BCB, polyimide, and/or HMDSO.

A third connection pattern <NUM> and a data line DL may be arranged on the second organic insulating layer <NUM>. However, the present invention is not limited thereto. The data line DL may be arranged on the third interlayer insulating layer <NUM> or the first organic insulating layer <NUM>. The third connection pattern <NUM> and the data line DL may include Al, Cu, and/or Ti and may include a single layer or multiple layers including the material(s) described above. For example, the third connection pattern <NUM> and the data line DL may have a triple-layered structure of a Ti layer/an Al layer/a Ti layer. This aspect is described in more detail with reference to <FIG>.

A third organic insulating layer <NUM> may be arranged on the third connection pattern <NUM> and the data line DL. The third organic insulating layer <NUM> may include an organic insulating material, such as acryl, BCB, polyimide, and/or HMDSO.

<FIG> illustrates the first organic insulating layer <NUM>, the second organic insulating layer <NUM>, and the third organic insulating layer <NUM>. However, the present invention is not limited thereto. For example, at least one of the first through third organic insulating layers <NUM> through <NUM> may be omitted.

The organic light-emitting diode OLED may be arranged on the third organic insulating layer <NUM>. The organic light-emitting diode OLED may include a pixel electrode <NUM>, an intermediate layer <NUM>, and an opposite electrode <NUM>.

The pixel electrode <NUM> may be arranged on the third organic insulating layer <NUM>. The pixel electrode <NUM> may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and/or a compound thereof. In one or more embodiments, the pixel electrode <NUM> may further include a conductive oxide layer above and/or below the reflective layer described above. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), and/or aluminum zinc oxide (AZO). According to one or more embodiments, the pixel electrode <NUM> may have a tripled-layered structure of ITO/Ag/ITO layers.

A pixel-defining layer <NUM> may be arranged on the pixel electrode <NUM>. An opening may be defined in the pixel-defining layer <NUM> to expose at least a portion of the pixel electrode <NUM>. A central portion of the pixel electrode <NUM> may be exposed by the opening defined in the pixel-defining layer <NUM>.

The pixel-defining layer <NUM> may include an organic insulating material. In one or more embodiments, the pixel-defining layer <NUM> may include an inorganic insulating material, such as SiNX, SiON, and/or SiOx. In one or more embodiments, the pixel-defining layer <NUM> may include an organic insulating material and an inorganic insulating material. In one or more embodiments, the pixel-defining layer <NUM> may include a light-shielding material and may be provided as a black color. The light-shielding material may include a resin or paste including carbon black, a carbon nano-tube, and/or a black dye, a metal particle, such as Ni, Al, Mo, and/or an alloy thereof, a metal oxide particle (for example, chromium oxide), a metal nitride particle (for example, chromium nitride), and/or other suitable particle(s). When the pixel-defining layer <NUM> includes a light-shielding material, reflection of external light due to metal structures arranged below the pixel-defining layer <NUM> may be reduced.

A spacer <NUM> may be arranged on the pixel-defining layer <NUM>. The spacer <NUM> may include an organic insulating material, such as polyimide. In one or more embodiments, the spacer <NUM> may include an inorganic insulating material, such as SiOX, SiNX, and/or SiON, or an organic insulating material and an inorganic insulating material.

According to one or more embodiments, the spacer <NUM> may include the same material as the pixel-defining layer <NUM>. In this case, the pixel-defining layer <NUM> and the spacer <NUM> may be formed together by a mask process using a half-tone mask, and/or other suitable process. According to one or more embodiments, the spacer <NUM> and the pixel-defining layer <NUM> may include different materials from each other.

The intermediate layer <NUM> may be arranged on the pixel electrode <NUM>. The intermediate layer <NUM> may include a first functional layer 222a, an emission layer 222b, and a second functional layer 222c that are sequentially stacked. The first functional layer 222a and the second functional layer 222c may be commonly referred to as a functional layer.

The emission layer 222b may be arranged in the opening defined in the pixel-defining layer <NUM>. The emission layer 222b may include a high molecular-weight organic material or a low molecular-weight organic material emitting a light of a desired or specified color.

The first functional layer 222a may be arranged between the pixel electrode <NUM> and the emission layer 222b, and the second functional layer 222c may be arranged between the emission layer 222b and the opposite electrode <NUM>. However, the present invention is not limited thereto. At least one of the first functional layer 222a and/or the second functional layer 222c may be omitted.

The first functional layer 222a may include, for example, a hole transport layer (HTL), or an HTL and a hole injection layer (HIL). The second functional layer 222c may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer 222a and/or the second functional layer 222c may be a common layer formed to entirely cover the substrate <NUM>.

The opposite electrode <NUM> may include a conductive material having a low work function. For example, the opposite electrode <NUM> may include a transparent (or transflective) layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and/or an alloy thereof. In one or more embodiments, the opposite electrode <NUM> may further include a layer, such as an ITO, IZO, ZnO, and/or In<NUM>O<NUM> layer, on the transparent (or transflective) layer including the material(s) described above.

The organic light-emitting diode <NUM> may be covered by an encapsulation layer <NUM>. The encapsulation layer <NUM> may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. According to one or more embodiments, the encapsulation layer <NUM> may include a first inorganic encapsulation layer <NUM>, a second inorganic encapsulation layer <NUM>, and an organic encapsulation layer <NUM>. The organic encapsulation layer <NUM> may be arranged between the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM>.

The first and second inorganic encapsulation layers <NUM> and <NUM> may include one or more inorganic materials from among aluminum oxide (Al<NUM>O<NUM>), titanium oxide (TiO), tantalum oxide (Ta<NUM>O<NUM>), hafnium oxide (HfO<NUM>), ZnO, SiOX, SiNX, and/or SiON. The first and second inorganic encapsulation layers <NUM> and <NUM> may include a single layer or multiple layers including the material(s) described above. The organic encapsulation layer <NUM> may include a polymer-based material. The polymer-based material may include acryl-based resins, epoxy-based resins, polyimide, polyethylene, and/or other suitable materials. According to one or more embodiments, the organic encapsulation layer <NUM> may include acrylate.

<FIG>, <FIG>, and <FIG> are schematic cross-sectional views of portions of a display apparatus according to one or more embodiments of the present invention. In detail, <FIG>, <FIG>, and <FIG> correspond to enlargements of region C, region D, and region E of <FIG>, respectively. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the first connection pattern <NUM> may be arranged on the third interlayer insulating layer <NUM>. The first connection pattern <NUM> includes a first layer <NUM>, a second layer <NUM>, and a third layer <NUM> that are sequentially stacked. Each of the first through third layers <NUM> through <NUM> may include at least one of Al, Cu, and/or Ti. For example, the first layer <NUM> and the third layer <NUM> may include Ti, and the second layer <NUM> may include Al. However, the present invention is not limited thereto.

Referring to <FIG>, the second connection pattern <NUM> may be arranged on the first organic insulating layer <NUM>. The second connection pattern <NUM> may include a fourth layer <NUM>, a fifth layer <NUM>, and a sixth layer <NUM> that are sequentially stacked. Each of the fourth through sixth layers <NUM> through <NUM> may include at least one of Al, Cu, and/or Ti. For example, the fourth layer <NUM> and the sixth layer <NUM> may include Ti, and the fifth layer <NUM> may include Al. However, the present invention is not limited thereto.

Referring to <FIG>, the third connection pattern <NUM> may be arranged on the second organic insulating layer <NUM>. The third connection pattern <NUM> may include a seventh layer <NUM>, an eighth layer <NUM>, and a ninth layer <NUM> that are sequentially stacked. Each of the seventh through ninth layers <NUM> through <NUM> may include at least one of Al, Cu, and/or Ti. For example, the seventh layer <NUM> and the ninth layer <NUM> may include Ti, and the eighth layer <NUM> may include Al. However, the present invention is not limited thereto.

<FIG> is a schematic plan view of a portion of a display apparatus according to one or more embodiments of the present invention. In detail, <FIG> corresponds to an enlargement of region A of <FIG>. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the driving voltage supply line <NUM> may be arranged in the peripheral area PA of the display panel <NUM>. Also, a first dam portion <NUM>, a second dam portion <NUM>, and a bank <NUM> may be arranged in the peripheral area PA of the display panel <NUM>.

As described above with reference to <FIG>, the driving voltage supply line <NUM> may include the first driving voltage supply line <NUM>, the second driving voltage supply line <NUM> (see, e.g., <FIG>), and the third driving voltage supply line <NUM>.

When forming the encapsulation layer <NUM> (see, e.g., <FIG>), in detail, the organic encapsulation layer <NUM> (see, e.g., <FIG>), it is required to apply a material for forming an organic encapsulation layer within a suitable area (e.g., a predetermined area). To this end, as illustrated in <FIG>, the first dam portion <NUM> may be arranged in the peripheral area PA. The first dam portion <NUM> may be arranged to surround (or be around) the display area DA (see, e.g., <FIG>). That is, the first dam portion <NUM> may be arranged along a circumference of the display area DA.

The second dam portion <NUM> may further be arranged outside the first dam portion <NUM>. The second dam portion <NUM> may be arranged to surround (or be around) the first dam portion <NUM>. That is, the second dam portion <NUM> may be arranged along a circumference of the first dam portion <NUM>. Also, because the first dam portion <NUM> may be arranged along the circumference of the display area DA, it may be understood that the second dam portion <NUM> may also be arranged along the circumference of the display area DA.

Because the first dam portion <NUM> and/or the second dam portion <NUM> may be arranged along the circumference of the display area DA, the material for forming an organic encapsulation layer may be prevented (or substantially prevented) from being diffused toward an edge of the substrate <NUM> (see, e.g., <FIG>), a location for forming the organic encapsulation layer <NUM> may be defined, and formation of an edge tail of the organic encapsulation layer <NUM> may be prevented (or substantially prevented).

The bank <NUM> may further be arranged outside the second dam portion <NUM>. The bank <NUM> may at least partially surround (or be around) the second dam portion <NUM>. The bank <NUM> may support masks which are used in a manufacturing process of the display panel <NUM> to form the intermediate layer <NUM> (see, e.g., <FIG>) and/or the opposite electrode <NUM> (see, e.g., <FIG>) of the organic light-emitting diode OLED (see, e.g., <FIG>), and by doing so, may prevent or minimize damage to previously formed components, the damage being caused by the masks.

According to one or more embodiments, an end of the organic encapsulation layer <NUM> may be arranged between the display area DA and the first dam portion <NUM>. In one or more embodiments, an end of the organic encapsulation layer <NUM> may be arranged on the first dam portion <NUM>.

According to one or more embodiments, the first inorganic encapsulation layer <NUM> (see, e.g., <FIG>) and the second inorganic encapsulation layer <NUM> (see, e.g., <FIG>) of the encapsulation layer <NUM> may extend toward the bank <NUM>. Ends of the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may be arranged between the second dam portion <NUM> and the bank <NUM>. In one or more embodiments, ends of the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may be arranged on the bank <NUM>.

The peripheral area PA includes an adhesion area AA. The adhesion area AA may be arranged between the second dam portion <NUM> and the bank <NUM>. For example, the adhesion area AA including only inorganic insulating materials may be defined between the second dam portion <NUM> and the bank <NUM>. Here, that the adhesion area AA includes only inorganic insulating materials may denote that an organic insulating material may not be arranged in the adhesion area AA. That is, an inorganic insulating layer and/or a conductive pattern may be arranged in the adhesion area AA. In the adhesion area AA, the first inorganic encapsulation layer <NUM> directly contacts the second inorganic encapsulation layer <NUM> and another inorganic layer may be below the first inorganic encapsulation layer <NUM>, for example, the third interlayer insulating layer <NUM> (see, e.g., <FIG>), and thus, an adhesive force of the encapsulation layer <NUM> may be improved to relatively more effectively prevent or minimize the penetration of external moisture and oxygen.

A conductive pattern <NUM> is arranged in the adhesion area AA. Here, the conductive pattern <NUM> may a portion of the first driving voltage supply line <NUM>. For example, at least a portion of the first driving voltage supply line <NUM> may overlap the adhesion area AA, and the portion of the first driving voltage supply line <NUM>, the portion overlapping the adhesion area AA, may correspond to the conductive pattern <NUM>.

According to one or more embodiments, the conductive pattern <NUM> may extend in a first direction (for example, a y direction). Also, the conductive pattern <NUM> may include protrusion patterns PP protruding in a second direction (for example, an x direction) crossing the first direction (for example, the y direction). That is, the portion of the first driving voltage supply line <NUM>, the portion overlapping the adhesion area AA, may include the protrusion patterns PP protruding in the second direction (for example, the x direction). The protrusion patterns PP may be formed at an edge of the conductive pattern <NUM> (for example, the first driving voltage supply line <NUM>) and may outwardly protrude on an x-y plane.

The edge of the conductive pattern <NUM> (for example, the first driving voltage supply line <NUM>) may be a movement path of external moisture and oxygen. When a length of the edge of the conductive pattern <NUM> (for example, the first driving voltage supply line <NUM>) increases, the movement path of external moisture and oxygen may increase. Accordingly, the organic light-emitting diode OLED (<FIG>) arranged in the display area DA may be protected (or substantially protected) from external moisture and oxygen.

According to one or more embodiments, because the protrusion patterns PP may be provided at the edge of the conductive pattern <NUM> (for example, the first driving voltage supply line <NUM>), the length of the edge of the conductive pattern <NUM> (for example, the first driving voltage supply line <NUM>) may be increased. Thus, transmission of external moisture and oxygen to the display area DA may be prevented or minimized, and as a result, damage to (or contamination of) the organic light-emitting diode OLED may be prevented or minimized.

<FIG> is a schematic cross-sectional view of a portion of a display apparatus according to one or more embodiments. In detail, <FIG> is a cross-sectional view of the display apparatus of <FIG>, taken along the line I-I'. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> and <FIG> denote the same elements of <FIG> and <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the substrate <NUM> may be arranged in the adhesion area AA. As described above, the substrate <NUM> may include the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d.

The buffer layer <NUM>, the first gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM>, the second gate insulating layer <NUM>, and the third interlayer insulating layer <NUM> may be sequentially arranged on the substrate <NUM>. All of the buffer layer <NUM>, the first gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM>, the second gate insulating layer <NUM>, and the third interlayer insulating layer <NUM> may include inorganic insulating materials.

The conductive pattern <NUM> may be arranged on the third interlayer insulating layer <NUM>. As described above, the conductive pattern <NUM> may be a portion of the first driving voltage supply line <NUM>. The conductive pattern <NUM> includes a first conductive layer <NUM>, a second conductive layer <NUM>, and a third conductive layer <NUM> that are sequentially stacked. Each of the first through third conductive layers <NUM> through <NUM> may include at least one of Al, Cu, and/or Ti. For example, the first conductive layer <NUM> and the third conductive layer <NUM> may include Ti, and the second conductive layer <NUM> may include Al. However, the present invention is not limited thereto.

According to one or more embodiments, the conductive pattern <NUM> may be arranged on (or at) the same layer as at least one of the first connection pattern <NUM> (see, e.g., <FIG>), the second connection pattern <NUM> (see, e.g., <FIG>), and/or the third connection pattern <NUM> (see, e.g., <FIG>) described above with reference to <FIG>. For example, the conductive pattern <NUM> are arranged on (or at) the same layer as the first connection pattern <NUM>. The first through third conductive layers <NUM> through <NUM> of the conductive pattern <NUM> are arranged on (or at) the same layer by including the same material as the first layer <NUM>, the second layer <NUM>, and the third layer <NUM> of the first connection pattern <NUM>, respectively.

According to one or more embodiments, a cover layer <NUM> is arranged on the conductive pattern <NUM>. The cover layer <NUM> does include at least one of Al, Cu, and/or Ti. For example, the cover layer <NUM> may include Ti. The cover layer <NUM> may include the same material as the first conductive layer <NUM> or the third conductive layer <NUM> of the conductive pattern <NUM>. In one or more embodiments, the cover layer <NUM> may include the same material as the fourth layer <NUM> of the second connection pattern <NUM> described above with reference to <FIG>.

The cover layer <NUM> covers a side surface <NUM> of the conductive pattern <NUM> and at least a portion of an upper surface 110u of the conductive pattern <NUM>. In detail, the cover layer <NUM> covers a side surface <NUM> of the first conductive layer <NUM>, a side surface <NUM> of the second conductive layer <NUM>, a side surface <NUM> of the third conductive layer <NUM>, and at least a portion of an upper surface 115u of the third conductive layer <NUM>.

When, in a process of manufacturing the display apparatus, the side surface <NUM> of the second conductive layer <NUM> is exposed, an undercut may occur in the side surface <NUM> of the second conductive layer <NUM>, which may generate an opening, and the opening may become a movement path of external moisture and oxygen.

The cover layer <NUM> covers the side surface <NUM> of the first conductive layer <NUM>, the side surface <NUM> of the second conductive layer <NUM>, the side surface <NUM> of the third conductive layer <NUM>, and at least the portion of the upper surface 115u of the third conductive layer <NUM>, and thus, occurrence of an undercut in the side surface <NUM> of the second conductive layer <NUM> due to exposure may be prevented or minimized. Thus, damage to (or contamination of) the organic light-emitting diode OLED (<FIG>) arranged in the display area DA, caused by external moisture and oxygen, may be prevented or minimized.

According to one or more embodiments, the encapsulation layer <NUM> may be arranged on the cover layer <NUM> and the third interlayer insulating layer <NUM>. In detail, the first inorganic encapsulation layer <NUM> may be arranged on the cover layer <NUM> and the third interlayer insulating layer <NUM>. The first inorganic encapsulation layer <NUM> is directly arranged on the cover layer <NUM> and may be arranged on the third interlayer insulating layer <NUM>.

The second inorganic encapsulation layer <NUM> is arranged on the first inorganic encapsulation layer <NUM>. The second inorganic encapsulation layer <NUM> is directly arranged on the first inorganic encapsulation layer <NUM>. The first inorganic encapsulation layer is directly arranged on the cover layer <NUM> and may be arranged on the third interlayer insulating layer <NUM>, and the second inorganic encapsulation layer <NUM> isdirectly arranged on the first inorganic encapsulation layer <NUM>, and thus, an adhesive force of the encapsulation layer <NUM> may be increased, and thus, the penetration of external moisture and oxygen may be relatively more effectively prevented or minimized.

The first driving voltage supply line <NUM> is described with reference to <FIG> and <FIG>. However, the second driving voltage supply line <NUM>, the first common voltage supply line <NUM>, and the second common voltage supply line <NUM> may have the same or substantially the same structure. For example, the protrusion patterns PP may be included in each of the second driving voltage supply line <NUM>, the first common voltage supply line <NUM>, and the second common voltage supply line <NUM> overlapping the adhesion area AA, and the cover layer <NUM> may be included in each of the second driving voltage supply line <NUM>, the first common voltage supply line <NUM>, and the second common voltage supply line <NUM> overlapping the adhesion area AA.

<FIG> is a schematic plan view of a portion of a display apparatus according to one or more embodiments of the present invention. In detail, <FIG> corresponds to an enlargement of region B of <FIG>. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the display panel <NUM> may include the display area DA, the opening area OA, and the middle area MA. Here, the display area DA may at least partially surround (or be around) the opening area OA. The middle area MA may be between the display area DA and the opening area OA.

According to one or more embodiments, grooves GV may be arranged (or defined) in the middle area MA. The grooves GV may include a first groove GV1, a second groove GV2, and a third groove GV3. Here, each of the first groove GV1, the second groove GV2, and the third groove GV3 may be arranged (or defined) along a circumference of the opening area OA.

<FIG> illustrates that three grooves GV may be arranged (or defined) in the middle area MA. However, the present invention is not limited thereto. Only one groove GV, two grooves GV, or four or more grooves GV may be arranged (or defined) in the middle area MA. Like this, various numbers of grooves GV may be arranged in the middle area MA.

<FIG> is a schematic cross-sectional view of a portion of a display apparatus according to one or more embodiments of the present invention. In detail, <FIG> is a cross-sectional view of the display apparatus of <FIG>, taken along the line II-II'. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, the substrate <NUM> may be arranged in the middle area MA. As described above, the substrate <NUM> may include the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d.

The buffer layer <NUM>, the first gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM>, the second gate insulating layer <NUM>, and the third interlayer insulating layer <NUM> may be sequentially arranged on the substrate <NUM>. An opening may be defined in the first gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM>, the second gate insulating layer <NUM>, and the third interlayer insulating layer <NUM> to correspond to the opening area OA.

Also, the first organic insulating layer <NUM> may be arranged on the third interlayer insulating layer <NUM>, the second organic insulating layer <NUM> may be arranged on the first organic insulating layer <NUM>, and the third organic insulating layer <NUM> may be arranged on the second organic insulating layer <NUM>. The pixel-defining layer <NUM> may be arranged on the third organic insulating layer <NUM>. The intermediate layer <NUM> and the opposite electrode <NUM> may be arranged on the pixel-defining layer <NUM>. For example, the first functional layer 222a, the second functional layer 222c, and the opposite electrode <NUM> may be arranged on the pixel-defining layer <NUM>.

According to one or more embodiments, the groove GV and a third dam portion <NUM> may be arranged in the middle area MA. The grooves GV may include the first groove GV1, the second groove GV2, and the third groove GV3. <FIG> illustrates that three grooves GV may be arranged in the middle area MA. However, the present invention is not limited thereto. Only one groove GV may be arranged in the middle area MA. In one or more embodiments, two grooves GV or four or more grooves GV may be arranged in the middle area MA. Like this, various modifications are possible.

According to one or more embodiments, the first groove GV1 may be arranged (or defined) between the display area DA (see, e.g., <FIG>) and the third dam portion <NUM>. However, the present invention is not limited thereto. For example, the first groove GV1 may be arranged (or defined) between the third dam portion <NUM> and the opening area OA. The second groove GV2 and the third groove GV3 may be arranged (or defined) between the third dam portion <NUM> and the opening area OA.

The organic material layer, for example, the first functional layer 222a and/or the second functional layer 222c, included in the intermediate layer <NUM> may be disconnected (or insulated) via the groove GV. The middle area MA may be understood as a groove area or a disconnected area (or an insulated area) of the organic material layer.

The groove GV may be formed in the substrate <NUM>. For example, the groove GV may be formed by removing at least a portion of the second base layer 100c, the second barrier layer 100d, and the buffer layer <NUM>. Thus, a bottom surface of the groove GV may be co-planar with an upper surface of the second base layer 100c. However, the present invention is not limited thereto. For example, the groove GV may be formed in layers arranged between the substrate <NUM> and the pixel electrode <NUM> (see, e.g., <FIG>). Here, the layers may include a first sub-layer and a second sub-layer.

According to one or more embodiments, the groove GV may have an undercut structure (or an undercut section). After the groove GV is formed, the intermediate layer <NUM> may be formed. Thus, at least one organic material layer of the intermediate layer <NUM> may be disconnected or insulated by the groove GV. For example, the first functional layer 222a and/or the second functional layer 222c may be disconnected or insulated by the groove GV. Also, the opposite electrode <NUM> may also be disconnected or insulated by the groove GV. The first functional layer 222a, the second functional layer 222c, and/or at least a portion of the opposite electrode <NUM> may be arranged in the groove GV. That is, the first functional layer 222a, the second functional layer 222c, and/or at least a portion of the opposite electrode <NUM> may be arranged on the bottom surface of the groove GV.

According to one or more embodiments, the third dam portion <NUM> may include a plurality of sub-layers 211a, 212a, 215a, and 217a stacked on the buffer layer <NUM>. The plurality of sub-layers 211a, 212a, 215a, and 217a may correspond to a portion of the first organic insulating layer <NUM>, a portion of the second organic insulating layer <NUM>, a portion of the pixel-defining layer <NUM>, and a portion of the spacer <NUM> (see, e.g., <FIG>), respectively. In this case, a height from the substrate <NUM> to an upper surface of the third dam portion <NUM> may be less than a height from the substrate <NUM> to an upper surface of the spacer <NUM> (see, e.g., <FIG>) in the display area DA (see, e.g., <FIG>). However, the present invention is not limited thereto. The height from the substrate <NUM> to the upper surface of the third dam portion <NUM> may be equal to or greater than the height from the substrate <NUM> to the upper surface of the spacer <NUM> (see, e.g., <FIG>) in the display area DA (see, e.g., <FIG>).

<FIG> illustrates that one dam portion (for example, the third dam portion <NUM>) may be arranged in the middle area MA. However, the present invention is not limited thereto. Two or more dam portions may be arranged in the middle area MA.

According to one or more embodiments, the encapsulation layer <NUM> may be arranged on the opposite electrode <NUM>. The encapsulation layer <NUM> may include the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM>. The first inorganic encapsulation layer <NUM> may have a relatively superior step coverage, and thus, may be continually formed to cover an inner surface of the groove GV. The first inorganic encapsulation layer <NUM> may cover the first functional layer 222a, the second functional layer 222c, and/or the opposite electrode <NUM> arranged on the bottom surface of the groove GV and insulated from each other.

The organic encapsulation layer <NUM> may be arranged between the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM>, and an end of the organic encapsulation layer <NUM> may be arranged adjacent to a side of the third dam portion <NUM>. The organic encapsulation layer <NUM> may be arranged in an inner space of a groove GV which is adjacent to the display area DA from among the grooves GV. That is, the first groove GV1 may be filled with the organic encapsulation layer <NUM>.

The second inorganic encapsulation layer <NUM> may have a relatively superior step coverage, similarly to the first inorganic encapsulation layer <NUM>. Thus, the second inorganic encapsulation layer <NUM> may be continually formed along an inner surface of a groove GV which is not covered by the organic encapsulation layer <NUM> from among the grooves GV.

<FIG> is a schematic plan view of a portion of a display apparatus according to one or more embodiments of the present invention. The embodiment of <FIG> is different from the embodiment of <FIG> in that openings OP may be defined in the middle area MA. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

According to one or more embodiments, the openings OP may be arranged (or defined) in the middle area MA. The openings OP may include a first opening OP1 and a second opening OP2. Here, each of the first and second openings OP1 and OP2 may be arranged along a circumference of the opening area OA.

<FIG> illustrates that two openings OP may be arranged (or defined) in the middle area MA. However, the present invention is not limited thereto. Only one opening OP may be arranged (or defined) or three or more openings OP may be arranged (or defined) in the middle area MA. Like this, various numbers of openings OP may be arranged (or defined) in the middle area MA.

<FIG> is a schematic cross-sectional view of a portion of a display apparatus according to one or more embodiments of the present invention. In detail, <FIG> is a cross-sectional view of the display apparatus of <FIG>, taken along the line III-III'. In <FIG>, reference numerals that are the same as the reference numerals in <FIG> denote the same elements of <FIG>, and thus, their descriptions are not repeated.

Referring to <FIG>, according to one or more embodiments, the intermediate layer <NUM> may be arranged in the middle area MA. The intermediate layer <NUM> may be arranged in the display area DA (see, e.g., <FIG>), and at least a portion of the intermediate layer <NUM> may extend from the display area DA to the middle area MA. The intermediate layer <NUM> may include the first functional layer 222a and the second functional layer 222c.

According to one or more embodiments, the intermediate layer <NUM> may be disconnected (or insulated) in the middle area MA. In detail, the first and second functional layers 222a and 222c may be disconnected (or insulated) in the middle area MA. The openings OP may be defined in the first and second functional layers 222a and 222c arranged in the middle area MA.

According to one or more embodiments, the openings OP and a fourth dam portion <NUM> may be defined (or arranged) in the middle area MA. The openings OP may include the first opening OP1 and the second opening OP2. <FIG> illustrates that two openings OP may be defined (or arranged) in the middle area MA. However, the present invention is not limited thereto. Only one opening OP may be defined (or arranged) in the middle area MA. In one or more embodiments, three or more openings OP may be defined (or arranged) in the middle area MA. Like this, various modifications are possible.

According to one or more embodiments, the first opening OP1 may be arranged (or defined) between the display area DA (see, e.g., <FIG>) and the fourth dam portion <NUM>. However, the present invention is not limited thereto. For example, the first opening OP1 may be defined (or arranged) between the fourth dam portion <NUM> and the opening area OA. The second opening OP2 may be defined (or arranged) between the fourth dam portion <NUM> and the opening area OA.

According to one or more embodiments, the fourth dam portion <NUM> may include the plurality of sub-layers 211a, 212a, 215a, and 217a. The plurality of sub-layers 211a, 212a, 215a, and 217a may correspond to a portion of the first organic insulating layer <NUM>, a portion of the second organic insulating layer <NUM>, a portion of the pixel-defining layer <NUM>, and a portion of the spacer <NUM> (see, e.g., <FIG>), respectively. <FIG> illustrates that one dam portion (for example, the fourth dam portion <NUM>) may be arranged in the middle area MA. However, the present invention is not limited thereto. Two or more dam portions may be arranged in the middle area MA.

According to one or more embodiments, at least one opening OP may be defined in the first functional layer 222a and the second functional layer 222c, and thus, the penetration (or diffusion) of oxygen or moisture around the opening area OA into the organic light-emitting diodes OLED of the display area DA may be prevented or minimized.

According to one or more embodiments, the opposite electrode <NUM> may be arranged in the middle area MA. The opposite electrode <NUM> may be arranged in the display area DA (see, e.g., <FIG>), and at least a portion of the opposite electrode <NUM> may extend from the display area DA to the middle area MA.

According to one or more embodiments, the opposite electrode <NUM> may be disconnected in the middle area MA. The opposite electrode <NUM> arranged in the middle area MA may include a hole <NUM> corresponding to the opening area OA. The hole <NUM> defined in the opposite electrode <NUM> may be in the middle area MA.

An area of the hole <NUM> defined in the opposite electrode <NUM> may be greater than an area of the opening area OA. When the area of the hole <NUM> defined in the opposite electrode <NUM> is greater than the area of the opening area OA, the penetration (or diffusion) of oxygen or moisture around the opening area OA into the organic light-emitting diode OLED (see, e.g., <FIG>) of the display area DA may be prevented or minimized.

The encapsulation layer <NUM> may be arranged in the middle area MA. The encapsulation layer <NUM> may be arranged in the display area DA, and at least a portion of the encapsulation layer <NUM> may extend from the display area DA to the middle area MA. According to one or more embodiments, the encapsulation layer <NUM> may include the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM> that are sequentially stacked. Each of the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM> may extend from the display area DA to the middle area MA.

The organic encapsulation layer <NUM> may be formed by applying a monomer and curing the same, and flowing of the monomer for forming the organic encapsulation layer <NUM> may be controlled by the fourth dam portion <NUM>. That is, the fourth dam portion <NUM> may be arranged in the middle area MA, to prevent or minimize the flowing of the monomer for forming the organic encapsulation layer <NUM> toward the opening area OA. For example, an end of the organic encapsulation layer <NUM> may be arranged at a side of the fourth dam portion <NUM>.

Because an end of the organic encapsulation layer <NUM> may be arranged at a side of the fourth dam portion <NUM>, the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may directly contact each other on an upper surface of the fourth dam portion <NUM>.

The encapsulation layer <NUM> may overlap at least one opening OP defined in the intermediate layer <NUM>. The first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM> of the encapsulation layer <NUM> may overlap the first opening OP1 defined in the intermediate layer <NUM>.

<FIG> are schematic cross-sectional views for describing a method of manufacturing a display apparatus, according to one or more embodiments of the present invention.

Hereinafter, the method of manufacturing a display apparatus is sequentially described with reference to <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, the method of manufacturing a display apparatus includes: forming a first pattern material <NUM> in the display area DA and the adhesion area AA; forming the first connection pattern <NUM> by etching the first pattern material <NUM> in the display area DA and forming the conductive pattern <NUM> by etching the first pattern material <NUM> in the adhesion area AA; forming the first organic insulating layer <NUM> on the first connection pattern <NUM>; forming a second pattern material <NUM> on the first organic insulating layer <NUM> and the conductive pattern <NUM>; forming the second connection pattern <NUM> by etching the second pattern material <NUM> on the first organic insulating layer <NUM> and forming a protection layer <NUM> by etching the second pattern material <NUM> on the conductive pattern <NUM>; and etching a portion of the protection layer <NUM>.

First, referring to <FIG>, an operation of forming the first pattern material <NUM> in the display area DA and the adhesion area AA is performed.

The substrate <NUM> includes the display area DA and the adhesion area AA. The buffer layer <NUM> may be formed on the substrate <NUM> in the display area DA and on the substrate <NUM> in the adhesion area AA.

The driving semiconductor layer A1 of the driving transistor T1 may be formed on the buffer layer <NUM> in the display area DA. The driving semiconductor layer A1 may include the channel area C1 and the first area B1 and the second area D1 arranged at respective sides of the channel area C1.

The first gate insulating layer <NUM> may be formed on the driving semiconductor layer A1 in the display area DA and on the buffer layer <NUM> in the adhesion area AA. The driving gate electrode GE1 may be formed on the first gate insulating layer <NUM> in the display area DA. The first interlayer insulating layer <NUM> may be formed on the driving gate electrode GE1 in the display area DA and on the first gate insulating layer <NUM> in the adhesion area AA.

The second capacitor electrode CE2 may be formed on the first interlayer insulating layer <NUM> in the display area DA. The second interlayer insulating layer <NUM> may be formed on the second capacitor electrode CE2 in the display area DA and on the first interlayer insulating layer <NUM> in the adhesion area AA.

The compensation semiconductor layer A3 of the compensation transistor T3 may be formed on the second interlayer insulating layer <NUM> in the display area DA. The second gate insulating layer <NUM> may be formed on the compensation semiconductor layer A3 in the display area DA and on the second interlayer insulating layer <NUM> in the adhesion area AA.

The upper gate electrode G3B may be formed on the second gate insulating layer <NUM> in the display area DA. The third interlayer insulating layer <NUM> may be formed on the upper gate electrode G3B in the display area DA and on the second gate insulating layer <NUM> in the adhesion area AA.

According to one or more embodiments, the first pattern material <NUM> may be formed in the display area DA and the adhesion area AA. In detail, the first pattern material <NUM> may be formed on the third interlayer insulating layer <NUM> in the display area DA and the adhesion area AA. The first pattern material <NUM> is generally formed both in the display area DA and the adhesion area AA.

According to one or more embodiments, the first pattern material <NUM> may include a first material 1200M1, a second material 1200M2, and a third material 1200M3. However, the present invention is not limited thereto. The first pattern material <NUM> may include only one material. In one or more embodiments, the first pattern material <NUM> may include two materials. Like this, various modifications are possible.

The first material 1200M1, the second material 1200M2, and the third material 1200M3 may be sequentially formed on the third interlayer insulating layer <NUM>. Each of the first through third materials 1200M1 through 1200M3 may include at least one of Al, Cu, and/or Ti. For example, the first material 1200M1 and the third material 1200M3 may include Ti, and the second material 1200M2 may include Al. However, the present invention is not limited thereto.

Referring to <FIG>, an operation of forming the first connection pattern <NUM> by etching the first pattern material <NUM> in the display area DA and forming the conductive pattern <NUM> by etching the first pattern material <NUM> in the adhesion area AA is performed.

According to one or more embodiments, the first connection pattern <NUM> may be formed by etching the first pattern material <NUM> in the display area DA. Here, the first pattern material <NUM> may be etched by using a dry etching method. However, the present invention is not limited thereto. The first pattern material <NUM> may be etched by using a wet etching method.

Also, during the etching of the first pattern material <NUM> in the display area DA, the first pattern material <NUM> in the adhesion area AA is also be etched concurrently. Thus, the first connection pattern <NUM> is formed by etching the first pattern material <NUM> in the display area DA, and the conductive pattern <NUM> is formed by etching the first pattern material <NUM> in the adhesion area AA.

Because the first pattern material <NUM> may include the first material 1200M1, the second material 1200M2, and the third material 1200M3, the first connection pattern <NUM> formed by etching the first pattern material <NUM> includes the first layer <NUM>, the second layer <NUM>, and the third layer <NUM>. The first layer <NUM> and the third layer <NUM> may include Ti, and the second layer <NUM> may include Al. However, the present invention is not limited thereto.

Because the first pattern material <NUM> may include the first material 1200M1, the second material 1200M2, and the third material 1200M3, the conductive pattern <NUM> formed by etching the first pattern material <NUM> may include the first conductive layer <NUM>, the second conductive layer <NUM>, and the third conductive layer <NUM>. The first conductive layer <NUM> and the third conductive layer <NUM> may include Ti, and the second conductive layer <NUM> may include Al. However, the present invention is not limited thereto.

Because the first layer <NUM> and the first conductive layer <NUM> may be formed by etching the first material 1200M1, the first layer <NUM> and the first conductive layer <NUM> may include the same material as each other. Also, because the second layer <NUM> and the second conductive layer <NUM> may be formed by etching the second material 1200M2, the second layer <NUM> and the second conductive layer <NUM> may include the same material as each other. Because the third layer <NUM> and the third conductive layer <NUM> may be formed by etching the third material 1200M3, the third layer <NUM> and the third conductive layer <NUM> may include the same material as each other.

Referring to <FIG>, an operation of forming the first organic insulating layer <NUM> on the first connection pattern <NUM> may be performed. In detail, the first organic insulating layer <NUM> may be formed on the first connection pattern <NUM> in the display area DA.

Referring to <FIG>, an operation of forming the second pattern material <NUM> on the first organic insulating layer <NUM> and the conductive pattern <NUM> may be performed. According to one or more embodiments, the second pattern material <NUM> may be formed in the display area DA and the adhesion area AA. In detail, the second pattern material <NUM> may be formed on the first organic insulating layer <NUM> in the display area DA and on the conductive pattern <NUM> in the adhesion area AA. The second pattern material <NUM> may be generally formed both in the display area DA and the adhesion area AA.

According to one or more embodiments, the second pattern material <NUM> may include a fourth material 1300M1, a fifth material 1300M2, and a sixth material 1300M3. However, the present invention is not limited thereto. The second pattern material <NUM> may include only one material. In one or more embodiments, the second pattern material <NUM> may include two materials. Like this, various modifications are possible.

The fourth material 1300M1, the fifth material 1300M2, and the sixth material 1300M3 may be sequentially formed on each of the first organic insulating layer <NUM> and the conductive pattern <NUM>. Each of the fourth material 1300M1, the fifth material 1300M2, and the sixth material 1300M3 may include one of Al, Cu, and/or Ti. For example, the fourth material 1300M1 and the sixth material 1300M3 may include Ti, and the fifth material 1300M2 may include Al. However, the present invention is not limited thereto.

Referring to <FIG>, an operation of forming the second connection pattern <NUM> by etching the second pattern material <NUM> on the first organic insulating layer <NUM> and forming the protection layer <NUM> by etching the second pattern material <NUM> on the conductive pattern <NUM> is performed.

According to one or more embodiments, the second connection pattern <NUM> may be formed by etching the second pattern material <NUM> in the display area DA. Here, the second pattern material <NUM> may be etched by using a dry etching method. However, the present invention is not limited thereto. The second pattern material <NUM> may be etched by using a wet etching method.

Also, while the second pattern material <NUM> in the display area DA is etched, the second pattern material <NUM> in the adhesion area AA may also be etched concurrently. Thus, the second connection pattern <NUM> may be formed by etching the second pattern material <NUM> in the display area DA, and the protection layer <NUM> may be formed by etching the second pattern material <NUM> in the adhesion area AA.

Because the second pattern material <NUM> may include the fourth through sixth materials 1300M1 through 1300M3, the second connection pattern <NUM> formed by etching the second pattern material <NUM> may include the fourth layer <NUM>, the fifth layer <NUM>, and the sixth layer <NUM>. The fourth layer <NUM> and the sixth layer <NUM> may include Ti, and the fifth layer <NUM> may include Al. However, the present invention is not limited thereto.

Because the second pattern material <NUM> may include the fourth through sixth materials 1300M1 through 1300M3, the protection layer <NUM> formed by etching the second pattern material <NUM> may include the cover layer <NUM>, a first protection layer <NUM>, which may also be termed as a first sub-protection layer <NUM>, and a second protection layer <NUM>, which may also be termed as a second sub-protection layer <NUM>. The cover layer <NUM>, the first protection layer <NUM>, and the second protection layer <NUM> of the protection layer <NUM> may be sequentially stacked in a thickness direction (for example, a z direction) of the substrate <NUM>. The cover layer <NUM> and the second protection layer <NUM> may include Ti, and the first protection layer <NUM> may include Al. However, the present invention is not limited thereto.

According to one or more embodiments, the protection layer <NUM> may cover the side surface <NUM> and at least a portion of the upper surface 110u of the conductive pattern <NUM>. The cover layer <NUM> of the protection layer <NUM> may cover the side surface <NUM> of the conductive pattern <NUM> and at least a portion of the upper surface 110u of the conductive pattern <NUM>. In detail, the cover layer <NUM> covers the side surface <NUM> of the first conductive layer <NUM>, the side surface <NUM> of the second conductive layer <NUM>, the side surface <NUM> of the third conductive layer <NUM>, and at least a portion of the upper surface 115u of the third conductive layer <NUM>.

Because the cover layer <NUM> of the protection layer <NUM> may cover the side surface <NUM> and at least the portion of the upper surface 110u of the conductive pattern <NUM>, occurrence of an undercut in the conductive pattern <NUM>, for example, the side surface <NUM> of the second conductive layer <NUM>, in subsequent processes may be prevented or minimized. Accordingly, the organic light-emitting diode OLED (see, e.g., <FIG>) arranged in the display area DA may be protected (or substantially protected) from external moisture and oxygen.

Referring to <FIG>, an operation of forming the second organic insulating layer <NUM> on the second connection pattern <NUM> is performed. In detail, the second organic insulating layer <NUM> may be formed on the second connection pattern <NUM> in the display area DA.

Referring to <FIG>, an operation of forming a third pattern material <NUM> on the second organic insulating layer <NUM> and the protection layer <NUM> may be performed. According to one or more embodiments, the third pattern material <NUM> may be formed in the display area DA and the adhesion area AA. In detail, the third pattern material <NUM> may be formed on the second organic insulating layer <NUM> in the display area DA and on the protection layer <NUM> in the adhesion area AA. The third pattern material <NUM> may be generally formed both in the display area DA and the adhesion area AA.

According to one or more embodiments, the third pattern material <NUM> may include a seventh material 1400M1, an eighth material 1400M2, and a ninth material 1400M3. However, the present invention is not limited thereto. The third pattern material <NUM> may include only one material. In one or more embodiments, the third pattern material <NUM> may include two materials. Like this, various modifications are possible.

The seventh material 1400M1, the eighth material 1400M2, and the ninth material 1400M3 may be sequentially formed on each of the second organic insulating layer <NUM> and the protection layer <NUM>. Each of the seventh through ninth materials 1400M1 through 1400M3 may include one of Al, Cu, and/or Ti. For example, the seventh material 1400M1 and the ninth material 1400M3 may include Ti, and the eighth material 1400M2 may include Al. However, the present invention is not limited thereto.

Referring to <FIG>, an operation of forming the third connection pattern <NUM> by etching the third pattern material <NUM> on the second organic insulating layer <NUM> and removing the third pattern material <NUM> on the protection layer <NUM>, the second protection layer <NUM>, and a portion of the first protection layer <NUM> may be performed.

According to one or more embodiments, the third connection pattern <NUM> may be formed by etching the third pattern material <NUM> in the display area DA. Here, the third pattern material <NUM> may be etched by dry etching. However, the present invention is not limited thereto. The third pattern material <NUM> may also be etched by wet etching.

Also, while the third pattern material <NUM> in the display area DA is etched, the third pattern material <NUM> in the adhesion area AA, the second protection layer <NUM>, and a portion of the first protection layer <NUM> may be removed together. Thus, the third connection pattern <NUM> may be formed by etching the third pattern material <NUM> in the display area DA, and the third pattern material <NUM> in the adhesion area AA, the second protection layer <NUM>, and a portion of the first protection layer <NUM> may be removed.

Because the third pattern material <NUM> may include the seventh through ninth materials 1400M1 through 1400M3, the third connection pattern <NUM> formed by etching the third pattern material <NUM> may include the seventh layer <NUM>, the eighth layer <NUM>, and the ninth layer <NUM>. The seventh layer <NUM> and the ninth layer <NUM> may include Ti, and the eighth layer <NUM> may include Al. However, the present invention is not limited thereto.

According to one or more embodiments, the third pattern material <NUM> in the adhesion area AA may be completely removed. Also, the second protection layer <NUM> arranged below the third pattern material <NUM> may also be completely removed. However, only a portion of the first protection layer <NUM> arranged below the second protection layer <NUM> may be removed. Thus, the cover layer <NUM> and remaining portions of the first protection layer <NUM> may be arranged on the conductive pattern <NUM>.

Referring to <FIG>, an operation of forming the third organic insulating layer <NUM> on the third connection pattern <NUM> may be performed. In detail, the third organic insulating layer <NUM> may be formed on the third connection pattern <NUM> in the display area DA.

Referring to <FIG>, an operation of forming a fourth pattern material <NUM> on the third organic insulating layer <NUM> and the first protection layer <NUM> may be performed. According to one or more embodiments, the fourth pattern material <NUM> may be formed in the display area DA and the adhesion area AA. In detail, the fourth pattern material <NUM> may be formed on the third organic insulating layer <NUM> in the display area DA and on the first protection layer <NUM> in the adhesion area AA. Here, the fourth pattern material <NUM> may be formed on the first protection layer <NUM>, a portion of which is removed.

The fourth pattern material <NUM> may be generally formed both in the display area DA and the adhesion area AA.

According to one or more embodiments, the fourth pattern material <NUM> may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and/or a compound thereof. In one or more embodiments, the fourth pattern material <NUM> may further include a conductive oxide layer above and/or below the reflective layer described above. The conductive oxide layer may include ITO, IZO, ZnO, In<NUM>O<NUM>, IGO, and/or AZO. According to one or more embodiments, the fourth pattern material <NUM> may have a structure in which a conductive oxide layer, a reflective layer, and a conductive oxide layer are stacked. For example, the fourth pattern material <NUM> may have a triple-layered structure of ITO/Ag/ITO layers. However, the present invention is not limited thereto.

Referring to <FIG>, an operation of forming the pixel electrode <NUM> by etching the fourth pattern material <NUM> on the third organic insulating layer <NUM> and removing the fourth pattern material <NUM> on the first protection layer <NUM> and the remaining portions of the first protection layer <NUM> may be performed.

According to one or more embodiments, the pixel electrode <NUM> may be formed by etching the fourth pattern material <NUM> in the display area DA. Here, the fourth pattern material <NUM> may be etched by wet etching. However, the present invention is not limited thereto. The fourth pattern material <NUM> may be etched by dry etching.

Also, while the fourth pattern material <NUM> in the display area DA is etched, the fourth pattern material <NUM> in the adhesion area AA and the remaining portions of the first protection layer <NUM> may be removed together. Thus, the pixel electrode <NUM> may be formed by etching the fourth pattern material <NUM> in the display area DA, and the fourth pattern material <NUM> in the adhesion area AA and the remaining portions of the first protection layer <NUM> may be removed.

According to one or more embodiments, because the remaining portions of the first protection layer <NUM> may be removed, only the cover layer <NUM> of the protection layer <NUM> may be arranged on the conductive pattern <NUM>. The cover layer <NUM> may cover the side surface <NUM> of the conductive pattern <NUM> and at least a portion of the upper surface 110u of the conductive pattern <NUM>. In detail, the cover layer <NUM> covers the side surface <NUM> of the first conductive layer <NUM>, the side surface <NUM> of the second conductive layer <NUM>, the side surface <NUM> of the third conductive layer <NUM>, and at least a portion of the upper surface 115u of the third conductive layer <NUM>.

As illustrated in <FIG>, after removing a portion of the protection layer <NUM>, an operation of forming the first inorganic encapsulation layer <NUM> (see, e.g., <FIG>) and the second inorganic encapsulation layer <NUM> (see, e.g., <FIG>) on the cover layer <NUM> may further be performed.

In detail, after removing a portion of the protection layer <NUM>, the pixel-defining layer <NUM> (see, e.g., <FIG>) may be formed on the pixel electrode <NUM> in the display area DA. Also, the intermediate layer <NUM> (see, e.g., <FIG>) and the opposite electrode <NUM> (see, e.g., <FIG>) may be sequentially formed on the pixel-defining layer <NUM> and the pixel electrode <NUM> in the display area DA.

Thereafter, the encapsulation layer <NUM> (see, e.g., <FIG> and <FIG>) may be formed on the opposite electrode <NUM> in the display area DA and on the cover layer <NUM> in the adhesion area AA. In detail, the first inorganic encapsulation layer <NUM> may be formed on the opposite electrode <NUM> in the display area DA and on the cover layer <NUM> in the adhesion area AA. Thereafter, the organic encapsulation layer <NUM> may be formed on the first inorganic encapsulation layer <NUM> in the display area DA. Thereafter, the second inorganic encapsulation layer <NUM> may be formed on the organic encapsulation layer <NUM> in the display area DA and on the first inorganic encapsulation layer <NUM> in the adhesion area AA.

Thus, the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may be formed on the cover layer <NUM> in the adhesion area AA. The first inorganic encapsulation layer <NUM> in the adhesion area AA may directly contact the cover layer <NUM> and the second inorganic encapsulation layer <NUM>.

As described above, according to the one or more of the embodiments of the present invention, a display apparatus, in which a peripheral area at a bottom portion of the display apparatus may be minimized, may be realized. However, the scope of the present invention is not limited by this effect.

Claim 1:
A display apparatus comprising:
a substrate (<NUM>) including a display area (DA) and a peripheral area (PA) outside the display area (DA), the peripheral area (PA) including an adhesion area (AA);
a conductive pattern (<NUM>) in the adhesion area (AA);
a cover layer (<NUM>) covering at least a portion of an upper surface (110u) of the conductive pattern (<NUM>) and a side surface (<NUM>) of the conductive pattern (<NUM>); and
an encapsulation layer (<NUM>) in the display area (DA) and the peripheral area (PA), the encapsulation layer (<NUM>) comprising a first inorganic encapsulation layer (<NUM>), an organic encapsulation layer (<NUM>), and a second inorganic encapsulation layer (<NUM>),
wherein the first inorganic encapsulation layer (<NUM>) directly contacts the cover layer (<NUM>) and the second inorganic encapsulation layer (<NUM>) in the adhesion area (AA),
characterized in that
the conductive pattern (<NUM>) comprises a first conductive layer (<NUM>), a second conductive layer (<NUM>), and a third conductive layer (<NUM>) that are sequentially stacked,
wherein the cover layer (<NUM>) covers a side surface (<NUM>) of the first conductive layer (<NUM>), a side surface (<NUM>) of the second conductive layer (<NUM>), a side surface (<NUM>) of the third conductive layer (<NUM>), and at least a portion of an upper surface (115u) of the third conductive layer (<NUM>),
wherein a first connection pattern (<NUM>) is located in the display area (DA), the first connection pattern (<NUM>) comprises a first layer (<NUM>), a second layer (<NUM>), and a third layer (<NUM>) that are sequentially stacked, and
the first conductive layer (<NUM>), the second conductive layer (<NUM>), and the third conductive layer (<NUM>) are at same layers and comprise same materials as the first layer (<NUM>), the second layer (<NUM>), and the third layer (<NUM>), respectively, and
wherein the cover layer (<NUM>) includes at least one of aluminum, copper, and/or titanium.