Patent Description:
The present application relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.

A dynamic random access memory (DRAM) is a semiconductor memory in which data can be written and read at high speed and randomly, and is widely used in data storage devices or apparatuses.

The dynamic random access memory consists of a plurality of repeat memory units, each of the plurality of memory units generally include a capacitor structure and a transistor, and a gate electrode of the transistor is connected to a word line, a drain electrode of the transistor is connected to a bit line, and a source electrode of the transistor is connected to the capacitor structure; and a voltage signal on the word line can control turn-on or turn-off of the transistor, thereby reading data information stored in the capacitor structure by means of the bit line, or writing data information into the capacitor structure by means of the bit line for storage.

With the increasing integration of the dynamic random access memory, a width of the word line becomes smaller, and further, a structure size of the transistor becomes smaller, easily generating gate induced drain leakage (GIDL) and reducing performance of a semiconductor structure. Related technology is known from <CIT>, <CIT>, <CIT> and <CIT>.

In the method for manufacturing the semiconductor structure and the semiconductor structure provided by embodiments of the present application, by means of a deposition process, the thickness of the first oxide portion covering the side walls of each of the trench structures is greater than the thickness of the second oxide portion covering the bottom wall of each of the trench structures; and by means of nitriding treatment, the concentration of nitrogen ions in the first oxide portion is less than the concentration of nitrogen ions in the second oxide portion, so that a dielectric constant of the first oxide portion is less than a dielectric constant of the second oxide portion. Such an arrangement can ensure that the semiconductor structure generates small gate induced drain leakage at a junction between the gate structure and a source electrode and a junction between the gate structure and a drain electrode, and can also improve turn-on current of the semiconductor structure, thereby improving sensitivity of the semiconductor structure.

In addition to the technical problems solved by the embodiments of the present application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of the technical solutions, other technical problems that can be solved by the method for manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present application, other technical features included in the technical solutions, and beneficial effects brought about by the technical features will be further described in detail in the detailed description of the embodiments.

With continuous reduction of size of a semiconductor structure, a line width and a trench size of the semiconductor structure become smaller, and a thickness of oxide layer formed on side walls and a bottom wall of the trench is reduced. Due to the reduction of the thickness of the oxide layer, for the semiconductor structure, signal resolution is weakened, storage speed is slow, and gate induced drain leakage is easily generated.

With regard to the described technical problems, the embodiments of the present application provide a method for manufacturing a semiconductor structure, and a semiconductor structure. By means of a deposition process, a thickness of a first oxide portion covering side walls of a trench structure is greater than a thickness of a second oxide portion covering a bottom wall of the trench structure; and by means of nitriding treatment, a concentration of nitrogen ions in the first oxide portion is less than a concentration of nitrogen ions in the second oxide portion, so that a dielectric constant of the first oxide portion is less than a dielectric constant of the second oxide portion. Such an arrangement can ensure that the semiconductor structure generates small gate induced drain leakage at a junction between a gate structure and a source electrode and a junction between the gate structure and a drain electrode, thereby improving sensitivity of the semiconductor structure.

In order to make described objectives, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the embodiments to be described are only a part rather than all of the embodiments of the present application.

<FIG> is a flowchart of the method for manufacturing the semiconductor structure provided by the embodiments of the present application. <FIG> are schematic diagrams of various stages of the method for manufacturing the semiconductor structure. The method for manufacturing the semiconductor structure will be described in detail below with reference to <FIG>.

The semiconductor structure is not limited in the embodiments, and the semiconductor structure is introduced below by taking a dynamic random access memory (DRAM) as an example, but the embodiments are not limited thereto, and the semiconductor structure in the embodiments are also other structures.

As shown in <FIG>, the embodiments of the present application provide the method for manufacturing the semiconductor structure, including the following steps:
Step S100: a substrate is provided, the substrate including trench structures distributed at intervals.

As shown in <FIG>, the semiconductor structure includes the substrate <NUM>. The substrate <NUM> serves as a supporting component of a memory and is used for supporting other components provided thereon. The substrate <NUM> is made of a semiconductor material, and the semiconductor material is one or more of silicon, germanium, silicon-germanium compound and silicon-carbide compound.

The trench structures <NUM> are provided at intervals in the substrate <NUM>, the trench structures <NUM> are used for exposing a part of the active region, and a gate structure is provided in each of the trench structures <NUM>, so as to achieve the electrical connection between the gate structure and the active region.

Specifically, a photoresist layer is formed on the substrate <NUM>, and the photoresist layer is patterned by means of exposure, development or etching, so as to form openings provided at intervals in the photoresist layer.

After the openings are formed, the substrate <NUM> exposed in the openings is removed by an etching liquid or an etching gas, so as to form the trench structures <NUM> provided at intervals in the substrate <NUM>.

Step S200: a source region and a drain region are formed respectively on both sides of each of the trench structures.

Exemplarily, a mask is provided, the mask is used to shield the trench structures <NUM>, so as to expose regions located at both sides of each of the trench structures <NUM>, and ions are doped into the regions located at both sides of each of the trench structures <NUM> by an ion implantation process, for example, doped ions are arsenic ions or boron ions, so as to form a source region <NUM> and a drain region <NUM> of the semiconductor structure.

Step S300: an oxide layer is formed, the oxide layer including a first oxide portion and a second oxide portion, and the first oxide portion covers side walls of each of the trench structures, the second oxide portion covers a bottom wall of each of the trench structures, and a thickness of the second oxide portion is less than a thickness of the first oxide portion.

Exemplarily, as shown in <FIG>, a silicon oxide layer is formed on the side walls and the bottom wall of each of the trench structures <NUM> and a top surface of the substrate <NUM> by an atomic layer deposition process, and the silicon oxide layer covering the side walls of the substrate <NUM> forms the first oxide portion <NUM>, and the silicon oxide layer covering the bottom wall of the substrate <NUM> forms the second oxide portion <NUM>, and the thickness of the first oxide portion <NUM> is greater than the thickness of the second oxide portion <NUM>.

Specifically, taking orientation shown in <FIG> as an example, in the direction perpendicular to the substrate, the thickness of the first oxide portion <NUM> gradually decreases from top to bottom, and the thickness of the second oxide portion <NUM> gradually decreases from top to bottom; in order to ensure accuracy of the thickness of the first oxide portion <NUM> and the thickness of the second oxide portion <NUM>, in the embodiments, an average thickness of the thickness of the first oxide portion <NUM> and an average thickness of the second oxide portion <NUM> are used as the standard for measuring a thickness of the oxide layer, that is, the average thickness of the first oxide portion <NUM> is greater than the average thickness of the second oxide portion <NUM>.

It should be noted that, in the embodiments, thickness difference between the first oxide portion <NUM> and the second oxide portion <NUM> is achieved by controlling process parameters in the atomic layer deposition process, for example, adjusting reaction temperature in the atomic layer deposition process so that the reaction temperature in the atomic layer deposition process is between <NUM> and <NUM>; and for another example, adjusting ratio of hexachlorodisilane (HCDS), O2 and H2 in the reaction gas, so as to ensure that the thickness of the first oxide portion <NUM> is greater than the thickness of the second oxide portion <NUM>.

In the embodiments, by making the thickness of the second oxide portion less than the thickness of the first oxide portion, it is equivalent to reducing the thickness of the oxide layer between a bottom-gate structure and the substrate; when a certain voltage is applied to the gate structure, electrons and minority carriers generated by the gate structure can be quickly transferred to the source region or the drain region, so as to improve turn-on current of the semiconductor structure and sensitivity of the semiconductor structure.

In addition, if the thickness of the oxide layer at the junction between the gate structure and the source electrode and the junction between the gate structure and the drain electrode are too small, the risk of the gate induced drain leakage generated by the semiconductor structure will be increased. Therefore, in the embodiments, ratio of the thickness of the second oxide portion <NUM> to the thickness of the first oxide portion <NUM> is limited, so that the ratio of the thickness of the second oxide portion <NUM> to the thickness of the first oxide portion <NUM> is <NUM>%-<NUM>%, and thus on the premise of improving the turn-on current of the semiconductor structure and the sensitivity of the semiconductor structure, the risk of the gate induced drain leakage generated by the semiconductor structure can also be prevented.

In order to ensure stability of the semiconductor structure, in the embodiments of the present application, high temperature treatment is performed on the first oxide portion <NUM> and the second oxide portion <NUM>, so as to increase compactness of the first oxide portion <NUM> and compactness of the second oxide portion <NUM>.

Exemplarily, the high temperature treatment is performed on the first oxide portion <NUM> and the second oxide portion <NUM> by a thermal annealing process, so as to increase the compactness of the first oxide portion <NUM> and the compactness of the second oxide portion <NUM>. Compared with the technical solution in the related art that only an atomic layer deposition process is used to form an oxide layer on the side walls and the bottom walls of each of the trench structures <NUM>, the embodiments can increase the compactness of the oxide layer <NUM> by performing a thermal annealing treatment on the oxide layer, so that the thickness of the oxide layer <NUM> is between <NUM> and <NUM>, and it can be ensured that the semiconductor structure is not easily broken down under a certain voltage, thereby improving performance of the semiconductor structure.

In the process of performing the thermal annealing treatment on the first oxide portion <NUM> and the second oxide portion <NUM>, a reaction temperature in the thermal annealing treatment can be limited, for example, the reaction temperature in the thermal annealing treatment is <NUM>-<NUM>. If the reaction temperature in the thermal annealing treatment is lower than <NUM>, it is difficult to ensure the compactness of the first oxide portion and the compactness of the second oxide portion, and if the reaction temperature in the thermal annealing treatment is higher than <NUM>, production cost and heat load effect of the semiconductor structure will be increased. Therefore, in the embodiments, the reaction temperature in the thermal annealing treatment process is specifically limited, so as to ensure the compactness of the oxide layer, and reduce the production cost of the semiconductor structure.

Step <NUM>: the oxide layer is nitrided, so that a concentration of nitrogen ions in the first oxide portion is less than a concentration of nitrogen ions in the second oxide portion.

Taking orientation shown in <FIG> as an example, the concentration of the nitrogen ions in the first oxide portion <NUM> gradually decreases from top to bottom, and the concentration of the nitrogen ions in the second oxide portion <NUM> gradually decreases from top to bottom. In order to ensure accuracy of the concentration of the nitrogen ions in the first oxide portion <NUM> and the concentration of the nitrogen ions in the second oxide portion <NUM>, in the embodiments, an average concentration of the nitrogen ions in the first oxide portion <NUM> and an average concentration of the nitrogen ions in the second oxide portion <NUM> are used as a measurement standard, that is, the average concentration of the nitrogen ions in the first oxide portion <NUM> is less than the average concentration of the nitrogen ions in the second oxide portion <NUM>.

In order to reduce the gate induced drain leakage of the semiconductor structure, in the embodiments, the oxide layer <NUM> is nitrided, for example, as shown in <FIG>, ammonia gas or nitrogen gas is introduced to the trench structures <NUM> at <NUM>-<NUM>, and then the ammonia gas or the nitrogen gas is used to form plasma by plasma treatment technology, so that a surface of the oxide layer <NUM> can be nitrided to substances similar to silicon oxynitride so as to increase dielectric constant of the oxide layer <NUM>, and the concentration of nitrogen ions in the first oxide portion is less than the concentration of nitrogen ions in the second oxide portion, and then there is a relatively large difference between the dielectric constant of the first oxide portion and the dielectric constant of the second oxide portion, and in this way, the gate induced drain leakage generated at the junction between the gate structure and the source electrode and the junction between the gate structure and the drain electrode can be relatively small, and the turn-on current of the semiconductor structure can also be improved, the sensitivity of the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

It should be noted that, the plasma treatment technology in the embodiments includes a capacitive coupling plasma treatment technology or an inductive coupling plasma treatment technology.

Further, as the gate induced drain leakage is mainly formed at an interface between the gate structure and the drain electrode, the embodiment also limits a ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM>. By making the concentration of nitrogen ions in the first oxide portion <NUM> less than the concentration of nitrogen ions in the second oxide portion <NUM>, the gate induced drain leakage is reduced, and the performance of the semiconductor structure is improved.

Specifically, if the ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM> is less than <NUM>, the concentration of nitrogen ions in the first oxide portion <NUM> will be reduced, and the dielectric constant of the first oxide portion will be greatly reduced. Although generation of the gate induced drain leakage will be reduced, the turn-on current of the semiconductor structure will also be greatly reduced under the same voltage. If the ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM> is greater than <NUM>, the generation of the gate induced drain leakage will be increased, and the performance of the semiconductor structure will be affected.

Therefore, in the embodiments, by setting the ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM> to between <NUM> and <NUM>, the gate induced drain leakage of the semiconductor structure can be reduced, and the turn-on current of the semiconductor structure can also be ensured.

In some embodiments, after the oxide layer is nitrided and before the gate structure is formed in each of the trench structures, the method for manufacturing a semiconductor structure further includes:
As shown in <FIG>, according to an embodiment not forming part of, but useful to understand the present invention, an initial barrier layer <NUM> is formed on the oxide layer <NUM>, that is, the initial barrier layer <NUM> is formed on the oxide layer <NUM> by an atomic layer deposition process. The initial barrier layer <NUM> can prevent conductive material of the gate structure from penetrating into the substrate <NUM>, thereby ensuring conductive performance of the gate structure and further improving yield of the semiconductor structure.

Exemplarily, material of the initial barrier layer <NUM> includes conductive material such as titanium nitride, and the titanium nitride has conductivity while preventing permeation between the conductive material in the gate structure and the substrate, thereby ensuring the performance of the semiconductor structure.

When forming the initial barrier layer, a chemical vapor deposition process is generally used to react titanium chloride with the ammonia gas to form the titanium nitride; however, in the process of forming the titanium nitride, chloride ions tend to remain in the titanium nitride; therefore, it is necessary to nitride the initial barrier layer <NUM>, so as to remove the chloride ions remaining in the initial barrier layer <NUM>.

Exemplarily, as shown in <FIG>, according to an embodiment not forming part of, but useful to understand the present invention, the ammonia gas or the nitrogen gas is supplied to a surface of the initial barrier layer <NUM> at <NUM>-<NUM>, and then the ammonia gas or the nitrogen gas is formed into plasma by the plasma treatment technology; and the plasma reacts with residual chloride ions, and the residual chloride ions in the titanium nitride are substituted by the nitrogen ions, so as to achieve the purpose of eliminating the residual chloride ions and improving conductivity of the initial barrier layer.

In the embodiments, a concentration of plasma formed on the surface of the initial barrier layer <NUM> is different. For example, a ratio of a concentration of plasma on the initial barrier layer <NUM> located on the side walls of each of the trench structures <NUM> to a concentration of plasma on the initial barrier layer <NUM> located on the bottom wall of each of the trench structures <NUM> is greater than <NUM>, such that concentration of the residual chloride ions can be removed well, thereby improving the conductivity of the initial conductive layer.

It should be noted that the plasma treatment technology includes capacitive coupling plasma treatment technology or inductive coupling plasma treatment technology.

Step S500: the gate structure is formed in each of the trench structures.

As shown in <FIG>, specifically, by a physical deposition process or a chemical vapor deposition process, conductive material is deposited into each of the trench structures <NUM>, so as to form the initial conductive layer <NUM> in each of the trench structures <NUM>, and the initial conductive layer <NUM> covers the surface of the initial barrier layer <NUM>, and material of the initial conductive layer <NUM> includes the conductive material such as tungsten.

After the initial conductive layer <NUM> is formed, a chemical mechanical polishing process is used to flatten the initial conductive layer <NUM>, so that a top surface of the initial conductive layer <NUM> is flush with a top surface of the initial barrier layer <NUM>, and a structure as shown in <FIG> is formed.

Then, by a wet etching process, a portion of the initial barrier layer <NUM> and a portion of the initial conductive layer <NUM> are removed, that is, the initial barrier layer <NUM> located on the substrate <NUM> is removed, and a portion of the initial barrier layer <NUM> and a portion of the initial conductive layer <NUM> located in each of the trench structures <NUM> are removed, a remaining initial barrier layer <NUM> forms a barrier layer <NUM>, and a remaining initial conductive layer <NUM> forms the gate structure <NUM>, and a structure thereof is as shown in <FIG>.

An upper surface of the barrier layer <NUM> is flush with an upper surface of the gate structure <NUM>, and the upper surface of the gate structure <NUM> is lower than an upper surface of the substrate <NUM>, so that the trench structures are formed between the gate structure <NUM> and the upper surface of the substrate <NUM>, so as to subsequently form a gate protection layer in each of the trench structures.

In some embodiments, not forming part of, but useful to understand the present invention, after forming the gate structure in each of the trench structures, the method for manufacturing the semiconductor structure further includes: a gate protection layer is formed, the gate protection layer covering the surface of the substrate and filling each of the trench structures.

As shown in <FIG>, insulating material is deposited into each of the trench structures <NUM> by an atomic layer deposition process or a chemical vapor deposition process, so as to form the gate protection layer <NUM> on the surface of the gate structure <NUM>, the gate protection layer <NUM> extending to the surface of the substrate <NUM> outside each of the trench structures <NUM>, and material of the gate protection layer <NUM> includes the insulating material such as silicon nitride. In the embodiments, by the arrangement of the gate protection layer <NUM>, insulation arrangement between the gate structure <NUM> and other conductive structures arranged on the substrate <NUM> can be realized.

In the process of etching the initial barrier layer <NUM> and the initial conductive layer <NUM> and transferring the semiconductor structure from an etching machine to a deposition machine, metal tungsten on the surface of the gate structure <NUM> is oxidized into tungsten oxide. Therefore, in the embodiments, after forming the gate structure in each of the trench structures and before forming the gate protection layer, hydrogen gas or ammonia gas is introduced to the surface of the gate structure <NUM>, and the gate structure <NUM> is plasma-treated at <NUM>-<NUM>, so as to improve the conductivity of the gate structure <NUM>.

Exemplarily, at <NUM>-<NUM>, the ammonia gas or the hydrogen gas is introduced to the surface of the gate structure <NUM>, and then the ammonia gas or the hydrogen gas is formed into plasma by plasma treatment technology. The plasma reacts with the tungsten oxide, and reduces the tungsten oxide on the surface of the gate structure <NUM> to tungsten, so as to improve the conductivity of the gate structure and reduce resistance of the gate structure, thereby improving the turning-on current of the gate structure.

The embodiments of the present application further provide a semiconductor structure. As shown in <FIG>, the semiconductor structure includes a substrate <NUM>, an oxide layer <NUM> and a gate structure <NUM>, and trench structures <NUM> are provided in the substrate <NUM>, the number of the trench structures <NUM> is multiple, and the trench structures <NUM> are provided at intervals in the substrate <NUM>.

The oxide layer <NUM> is provided in the trench structures <NUM>, and the oxide layer <NUM> includes a first oxide portion <NUM> and a second oxide portion <NUM>, and the first oxide portion <NUM> covers side walls of each of the trench structures <NUM>, and the second oxide portion <NUM> covers a bottom wall of each of the trench structures <NUM>.

A thickness of the second oxide portion <NUM> is less than a thickness of the first oxide portion <NUM>, which is used for increasing turn-on current of the semiconductor structure and improving sensitivity of the semiconductor structure.

A concentration of nitrogen ions in the first oxide portion <NUM> is less than a concentration of nitrogen ions in the second oxide portion <NUM>, to better reduce gate induced drain leakage, thereby improving performance of the semiconductor structure.

The gate structure <NUM> is provided in each of the trench structures <NUM>, and a top surface of the gate structure <NUM> is lower than a top surface of the substrate <NUM>.

In order to prevent conductive material in the gate structure <NUM> from diffusing into the substrate <NUM>, a barrier layer <NUM> is further provided between the oxide layer <NUM> and the gate structure <NUM>. By the arrangement of the barrier layer <NUM>, permeation between the conductive material in the gate structure and the substrate is prevented, and the barrier layer <NUM> also has conductivity, ensuring the performance of the semiconductor structure.

In the embodiments, not forming part of, but useful to understand the present invention, material of the barrier layer <NUM> includes conductive material such as titanium nitride, and material of the gate structure <NUM> includes conductive material such as metal tungsten.

In the semiconductor structure provided by the embodiments, by making the thickness of the second oxide portion be less than the thickness of the first oxide portion, and in combination with the fact that the concentration of nitrogen ions in the first oxide portion is less than that of the second oxide portion, dielectric constant of the first oxide portion is less than dielectric constant of the second oxide portion. Such an arrangement can ensure that the semiconductor structure generates small gate induced drain leakage at a junction between the gate structure and a source electrode and a junction between the gate structure and a drain electrode, and can also improve the turn-on current of the semiconductor structure, thereby improving the sensitivity of the semiconductor structure.

Further, the embodiments also limits the concentration of nitrogen ions in the first oxide portion and the concentration of nitrogen ions in the second oxide portion; if the ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM> is less than <NUM>, the concentration of nitrogen ions in the first oxide portion <NUM> will be reduced, and the dielectric constant of the first oxide portion will be greatly reduced; although the generation of the gate induced drain leakage will be reduced, the turn-on current of the semiconductor structure will also be greatly reduced under the same voltage; and if the ratio of the concentration of nitrogen ions in the first oxide portion <NUM> to the concentration of nitrogen ions in the second oxide portion <NUM> is greater than <NUM>, the generation of the gate induced drain leakage will be increased, and the performance of the semiconductor structure will be affected.

Therefore, in the embodiments, by setting the ratio of the concentration of nitrogen ions in the first oxide portion to the concentration of nitrogen ions in the second oxide portion to between <NUM> and <NUM>, the gate induced drain leakage can be reduced, and the turn-on current of the semiconductor structure can also be ensured.

In some embodiments, not forming part of, but useful to understand the present invention, the semiconductor structure provided by the embodiments further includes a gate protection layer <NUM>. The gate protection layer <NUM> is provided on a surface of the barrier layer <NUM> and the gate structure <NUM>, and fills each of the trench structures <NUM>. In the embodiments, by providing the gate protection layer <NUM>, insulation between the gate structure <NUM> and other conductive structures provided on the substrate <NUM> can be achieved.

The embodiments or implementations in this description are described in a progressive manner, each of the embodiments emphasizes the differences from one another, and same and similar parts of the various embodiments can make reference to one another.

Reference throughout this description to "an embodiment", "some embodiments", "an exemplary embodiment, "an example", "a specific example", "or some examples" means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application.

Thus, expressions of the terms above are not necessarily referring to the same embodiment or example of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

Claim 1:
A method for manufacturing a semiconductor structure, comprising:
providing a substrate (<NUM>), the substrate(<NUM>) comprising trench structures(<NUM>) distributed at intervals;
forming a source region (<NUM>) and a drain region(<NUM>) respectively on both sides of each of the trench structures(<NUM>);
forming an oxide layer(<NUM>), the oxide layer(<NUM>) comprising a first oxide portion(<NUM>) and a second oxide portion(<NUM>), wherein the first oxide portion(<NUM>) covers side walls of each of the trench structures(<NUM>), the second oxide portion(<NUM>) covers a bottom wall of each of the trench structures(<NUM>), and a thickness of the second oxide portion(<NUM>) is less than a thickness of the first oxide portion(<NUM>);
nitriding the oxide layer (<NUM>), so that a concentration of nitrogen ions in the first oxide portion(<NUM>) is less than a concentration of nitrogen ions in the second oxide portion(<NUM>);
forming a gate structure (<NUM>) in each of the trench structures(<NUM>);
wherein a ratio of the concentration of the nitrogen ions in the first oxide portion (<NUM>) to the concentration of the nitrogen ions in the second oxide portion(<NUM>) is between <NUM> and <NUM>.