Patent Description:
The technology of the disclosure relates generally to voltage level shifting of signals from one voltage domain to a different voltage domain, and more particularly to half-voltage level shifter (HVLS) circuits for shifting signals from one voltage domain to a different voltage domain.

Processor-based systems have access to a power supply that provides voltage to circuit components therein for powering operations. Particular components within a processor-based system may operate using less voltage than other components during certain operation modes. For example, a processor may use less voltage to operate during idle modes. On the other hand, memory may require a certain minimum voltage to retain data, regardless of the processor's mode of operation. In this regard, rather than providing a single voltage supply to supply a higher voltage to all components in a processor-based system, a plurality of supply voltages at different voltage levels may be made available to components of the processor-based system. Components, such as logic circuits, that can operate at a lower voltage are powered by a lower voltage in a first voltage domain. Components, such as memory, that may be required to operate at a higher voltage for data retention for example, are powered by a higher voltage in a second voltage domain. In this manner, power is conserved as opposed to providing a single higher voltage to all components.

To provide for signals from components in one voltage domain operating from a first voltage supply to be compatibly received and processed by components operating from a second voltage supply in another voltage domain, and vice versa, voltage level shifter (VLS) circuits are employed. <FIG> illustrates an exemplary electronic system <NUM> that includes multiple voltage domains, which are shown as a first voltage domain <NUM>(<NUM>) and a second voltage domain <NUM>(<NUM>). The first voltage domain <NUM>(<NUM>) and the second voltage domain <NUM>(<NUM>) are supplied with voltages of different voltage levels by first and second voltage supplies. VLS circuits <NUM>(<NUM>)-<NUM>(N) are provided that are configured to shift respective input signals <NUM>(<NUM>)-<NUM>(N) in the first voltage domain <NUM>(<NUM>) to respective output signals <NUM>(<NUM>)-<NUM>(N) in the second voltage domain <NUM>(<NUM>). For example, the electronic system <NUM> may include logic circuits in the first voltage domain <NUM>(<NUM>) designed to operate at lower voltage levels of <NUM> Volts (V) for example, and memory circuits in the second voltage domain <NUM>(<NUM>) designed to operate at higher voltage levels of <NUM> Volts (V) for example. In this scenario, the VLS circuits <NUM>(<NUM>)-<NUM>(N) illustrated in <FIG> would be low-to-high VLS circuits that are configured to shift the input signals <NUM>(<NUM>)-<NUM>(N) from the lower, first voltage domain <NUM>(<NUM>) of <NUM> V to the respective output signals <NUM>(<NUM>)-<NUM>(N) in the higher, second voltage domain <NUM>(<NUM>) of <NUM> V. In other words, if an input signal <NUM>(<NUM>)-<NUM>(N) has a logic `<NUM>'/high value, meaning its voltage is approximately <NUM> V from being supplied by power in the lower, first voltage domain <NUM>(<NUM>), the corresponding output signal <NUM>(<NUM>)-<NUM>(N) will be shifted to remain a logic `<NUM>'/high value, but with a voltage of approximately <NUM> V of the higher, second voltage domain <NUM>(<NUM>).

Memory systems may also be provided in dual voltage domains to further conserve power. For example, memory arrays that include memory bit cells that may require higher voltages for data retention are provided in a higher voltage domain. Circuits that support memory access to the memory array(s), such as decoders, driver circuits, and sense amplifiers for example, may be provided in a lower voltage domain. Thus, these dual voltage domain memory systems include VLS circuits to voltage level shift signals between the memory access circuits and the memory arrays. For example, these memory systems may employ VLS circuits in wordline decoders to generate word line signals to the memory array(s) in the higher voltage domain. Since a conventional memory system includes memory array(s) that include a large number of memory rows having corresponding word lines, a corresponding large number of HVLS circuits would be required to voltage level shift decoded wordline signals generated by the wordline decoders to the higher voltage domain, thus critically affecting the overall power/performance/area (PPA) of the memory circuit. <CIT> discloses a dynamic level shifter circuit and ring oscillator. <CIT> describes a type of dynamic level shifter.

Aspects of the present disclosure involve voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase. The VLS circuits may be half- voltage level shifter (HVLS) circuits as an example. A VLS circuit includes a pre-charge circuit configured to pre-charge an output node in a pre-charge phase in response to a pre-charge control signal. The VLS circuit also includes a pull-up circuit (e.g., a P-type (P) metal oxide semiconductor (MOS) (PMOS)-based circuit) and a pull-down circuit (e.g., an N-type (N) MOS (NMOS)-based circuit) that are configured to pull-up and pulldown the pre-charge phase of the output node, respectively, based on a logic voltage level of an input signal in an evaluation phase to generate a voltage level shifted output signal on the output node in a higher voltage domain. To mitigate or avoid contention between the pre-charge circuit and the pull-down circuit in response to the pre-charge phase, the input signal is pre-conditioned based on the pre-condition control signal such that the pull-down circuit is not activated by the input signal in response to the pre-charge phase. For example, if the input signal were not pre-conditioned, the pull-down circuit may be required to include additional circuitry or components that are responsive to the pre-condition control signal, such as an additional stacked transistor, to deactivate the pull-down circuit during the pre-charge phase. However, providing an additional stacked transistor in the pull-down circuit may decrease the drive strength of the pulldown circuit. This may cause contention issues with the pull-up circuit during the evaluation phase unless the pull-up circuit is weakened and/or the pull-down circuit is strengthened with larger sized transistors, which can cause additional power consumption and area in an undesired manner. Avoiding reducing the strength of the pull-down circuit can also allow the VLS circuit to operate over a wider range of voltages between the lower and higher voltage domains.

In this regard, the invention is defined by the apparatus of claim <NUM> in that, a voltage level shifter, circuit, comprises a pre-conditioning circuit. The pre-conditioning circuit is configured to receive an input signal in a first voltage domain. The pre-conditioning circuit is also configured to generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on the input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase. The VLS circuit further comprises a pre-charge circuit coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain. The pre-charge circuit is configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase. The VLS circuit further comprises a pull-up circuit coupled to the first supply rail and the output node. The pull-up circuit is configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal, CTRL1, and the pre-charge control signal, CTRLh, having a voltage level of a discharge logical high state indicating an evaluation phase. The VLS circuit further comprises a pull-down circuit coupled to the input node and the second supply rail. The pull-down circuit is configured to decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase. The pull-down circuit is further configured to couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRL1, and the pre-charge control signal, CTRLH, having a voltage level of a discharge logical high state indicating the evaluation phase.

The invention is defined by independent method claim <NUM> in that, a method of voltage level shifting an input signal from a lower voltage domain to a higher voltage domain is provided. The method comprises receiving an input signal in a first voltage domain. The method also comprises generating a pre-conditioned input signal on an input node in the first voltage domain at a voltage level indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase. The method also comprises coupling a first supply rail to an output node in response to a pre-charge control signal indicating the pre-charge phase. The method also comprises coupling the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal CTRL1, and the pre-charge control signal, CTRLh, having a voltage level of a discharge logic state indicating an evaluation phase. The method also comprises decoupling a second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase. The method also comprises coupling the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRLh, and the pre-charge control signal, CTRLH, having a voltage level of a discharge logical high state indicating the evaluation phase.

Aspects of the present disclosure involve voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase. The VLS circuits may be half-voltage level shifter (HVLS) circuits as an example. A VLS circuit includes a pre-charge circuit configured to pre-charge an output node in a pre-charge phase in response to a pre-charge control signal. The VLS circuit also includes a pull-up circuit (e.g., a P-type (P) metal oxide semiconductor (MOS) (PMOS)-based circuit) and a pull-down circuit (e.g., an N-type (N) MOS (NMOS)-based circuit) that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, based on a logic voltage level of an input signal in an evaluation phase to generate a voltage level shifted output signal on the output node in a higher voltage domain. To mitigate or avoid contention between the pre-charge circuit and the pull-down circuit in response to the pre-charge phase, the input signal is pre-conditioned based on a pre-condition control signal such that the pull-down circuit is not activated by the input signal in response to the pre-charge phase. For example, if the input signal were not pre-conditioned, the pull-down circuit may be required to include additional circuitry or components that are responsive to the pre-condition control signal, such as an additional stacked transistor, to deactivate the pull-down circuit during the pre-charge phase. However, providing an additional stacked transistor in the pull-down circuit may decrease the drive strength of the pull-down circuit. This may cause contention issues with the pull-up circuit during the evaluation phase unless the pull-up circuit is weakened and/or the pull-down circuit is strengthened with larger sized transistors, which can cause additional power consumption and area in an undesired manner. Avoiding reducing the strength of the pull-down circuit can also allow the VLS circuit to operate over a wider range of voltages between the lower and higher voltage domains.

Before discussing VLS circuits that employ a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase starting at <FIG>, a VLS circuit that does not employ a pre-conditioning circuit is first discussed with regard to <FIG>.

<FIG> is a schematic diagram of an exemplary VLS circuit <NUM> provided in the form of a HVLS circuit <NUM>. The HVLS circuit <NUM> is configured to receive an input signal IN on an input node <NUM> in a lower voltage domain VDL and voltage level shift the input signal IN into an output signal OUTB on an output node 206B in a higher voltage domain VDH. For example, a voltage level of a supply voltage supplying power in the lower voltage domain VDL may be <NUM> Volts (V), while a voltage level of a supply voltage supplying power in the higher voltage domain VDH may be <NUM> V. As shown in <FIG>, the HVLS circuit <NUM> is powered by higher supply voltage VDD-H received from a first, positive supply rail 208P in the higher voltage domain VDH to be able to generate the output signal OUTB in the higher voltage domain VDH. The output signal OUTB is a complement voltage logic state from the input signal IN, but the HVLS circuit <NUM> can include an inverter circuit <NUM> that inverts the output signal OUTB to output signal OUT on an output node <NUM> having the same logic state as the input signal IN. For example, using the supply voltage example above, if the input signal IN were <NUM> V, meaning a logic high or '<NUM>' state in the lower voltage domain VDL, the HVLS circuit <NUM> will generate the output signal OUT at approximately <NUM> V as a logic high or '<NUM>' state in the higher voltage domain VDH.

The HVLS circuit <NUM> is a dynamic voltage level shifter circuit meaning that the output signal OUTB is generated on the output node 206B in an evaluation phase after pre-charging of the output node 206B in a pre-charge phase. In this regard, the HVLS circuit <NUM> includes a pre-charge circuit <NUM> coupled to the output node 206B and the positive supply rail 208P. The pre-charge circuit <NUM> is a PMOS transistor M0. The pre-charge circuit <NUM> is configured to couple the positive supply rail 208P to the output node 206B to pre-charge the output node 206B to the higher supply voltage VDD-H in response to a pre-charge control signal CTRL indicating a pre-charge state. For example, the pre-charge control signal CTRL may be a clock signal wherein the pre-charge state is indicated by a logic low / '<NUM>' value. By the pre-charge circuit <NUM> pre-charging the output node 206B, this is what is meant by "half-voltage" level shifter. If the logic state of the input signal IN is a low logic state, the output node 206B is already pre-charged to the high logic state. Thus, in an evaluation phase when the pre-charge control signal CTRL is in a high logic state, a pull-up circuit 214U only has to pull-up the voltage level at the output node <NUM> to the higher supply voltage VDD-H in the evaluation phase from the pre-charged voltage level at the output node 206B during the pre-charge phase to generate the voltage level shifted output signal OUTB at the higher voltage domain VDH. However, if the logic state of the input signal IN is a high logic state during an evaluation phase, a pull-down circuit 214D pulls the output node 206B down to a second, negative supply rail 208N to generate the voltage level shifted output signal OUTB in a logic low state in the higher voltage domain VDH.

The HVLS circuit <NUM> also includes an NMOS transistor M1 that is provided as an optional keeper circuit. The NMOS transistor M1 keeps the output node OUTB in a low logic state if the input signal IN is in a low logic state on a next evaluation phase, so that the pre-charge circuit <NUM> does not pre-charge the output node OUTB in the next evaluation phase.

With continuing reference to <FIG>, to prevent or mitigate the pull-down circuit 214D being active and pulling down the output node 206B to the negative supply rail 208N in contention with the pre-charge circuit <NUM> pre-charging the output node 206B in the higher supply voltage VDD-H in the pre-charge phase, the pull-down circuit 214D includes stacked NMOS transistors M2 and M3. NMOS transistor M2 is turned off by the pre-charge control signal CTRL in the pre-charge state, which as discussed above causes the pre-charge circuit <NUM> to be activated to pre-charge the output node 206B to the higher supply voltage VDD-H- The pull-down circuit 214D also includes NMOS transistor M3 that pulls the output node 206B down to the negative supply rail 208N in response to the logic state of the input signal IN being a high logic state during the evaluation phase. The pull-up circuit 214U includes PMOS transistor M4 that is configured to be activated in response to the input signal IN being in a low logic state to pull-up the output node 206B to generate the output signal OUTB in a high logic state in the evaluation phase. Because the PMOS transistor M4 is in the higher voltage domain VDH and the input signal IN is the lower voltage domain VDL, due to this voltage difference, the PMOS transistor M4 may not completely turn off in response to the input signal IN being in a high logic state. Thus, this can cause contention between the pull-up circuit 214U and the pull-down circuit 214D, because the NMOS transistor M3 must overcome the pull-up PMOS transistor M4 to drive the output node 206B lower in response to the input signal IN being in a logic high state. Thus, PMOS transistor M5 is provided in the pull-up circuit 214U and controlled by the output signal OUT on the output node <NUM> to turn off the PMOS transistor M5 and prevent a crow-bar condition between the positive supply rail 208P and the negative supply rail 208N because of the contention between the NMOS transistor M3 and the PMOS transistor M4.

The critical margin that affects the functionality of the HVLS circuit <NUM> is the ratio of the pull-down strength of the pull-down circuit 214D through NMOS transistors M2 and M3 to the pull-up strength of the pull-up circuit 214U through PMOS transistors M4 and M5. The pull-down strength must be higher than the pull-up strength. At an extreme voltage difference between the lower and higher voltage domains VDL and VDH, the pull-down path to the negative supply rail 208N is weakened relative to the pull up path to the positive supply rail 208P, thereby affecting the voltage range where the HVLS circuit <NUM> works reliably. To improve the operating voltage range of the HVLS circuit <NUM>, the drive strength of the pull-down NMOS transistors M2 and M3 is increased by the size of the pull-down NMOS transistors M2 and M3 and providing such with gates having lower threshold voltages Vt relative to the pull-up PMOS transistors M4 and M5. In some cases, the pull-up circuit 214U may be further stacked to reduce its drive strength. Another circuit may be provided to temporarily weaken the pull-up circuit 214U using a timed signal to assist the pull-down circuit 214D in overpowering the pull-up path of the pull-up circuit 214U to the positive supply rail 208P. However, all of these techniques negatively affect the power/performance/area (PPA) of the HVLS circuit <NUM> in an undesired manner.

<FIG> is a schematic diagram of an exemplary VLS circuit <NUM> also provided in the form of a HVLS circuit <NUM>. The HVLS circuit <NUM> is also configured to receive an input signal IN on a node <NUM> in a first, lower voltage domain VDL, and voltage level shift the input signal IN into an output signal OUTB on an output node 306B in a second, higher voltage domain VDH. As will be discussed in more detail below, unlike the HVLS circuit <NUM> in <FIG>, the HVLS circuit <NUM> in <FIG> includes a pre-conditioning circuit <NUM> in this example. However, the pre-conditioning circuit <NUM> could also be provided as a separate circuit outside of the HVLS circuit <NUM>, including in a different circuit block for example. The pre-conditioning circuit <NUM> avoids or mitigates contention between a pre-charge circuit <NUM> and a pull-down circuit 314D without the need to provide a stacked transistor arrangement in the pull-down circuit 314D, unlike, for example, the pull-down circuit 214D in the HVLS circuit <NUM> in <FIG>.

In this example, the pre-conditioning circuit <NUM> is provided in the form of an AND-based logic circuit <NUM>, which in this non-limiting example is an AND gate <NUM>. The pre-conditioning circuit <NUM> is configured to receive the input signal IN and a pre-condition control signal CTRLL in the lower voltage domain VDL. The pre-conditioning circuit <NUM> is configured to generate a pre-conditioned input signal INc in the lower voltage domain VDL in response to a pre-charge state of the pre-condition control signal CTRLL. In a pre-charge state, a pre-charge control signal CTRLH in the higher voltage domain VDH is in a charge logic state, which is a lower voltage or '<NUM>' logic state in this example. In this example, the pre-charge control signal CTRLH follows the logic state of the pre-condition control signal CTRLL. For example, the pre-charge control signal CTRLH may be the pre-condition control signal CTRLL shifted to or otherwise available in the higher voltage domain VDH. When the pre-charge control signal CTRLH is in a charge logic state, the pre-charge circuit <NUM> is turned on to couple a positive supply rail 308P to the output node 306B. However, when the pre-charge control signal CTRLH is in a charge logic state, the pre-conditioning circuit <NUM> forces the pre-conditioned input signal INC to the charge logic state regardless of the logic state of the input signal IN, which turns off the NMOS transistor M3 in the pull-down circuit 314D to decouple a negative supply rail 308N (e.g., which may be coupled to ground) from the output node 306B. In this manner, the pre-conditioning circuit <NUM> mitigates or avoids contention between the pre-charge circuit <NUM> and the pull-down circuit 314D during the pre-charge phase of the HVLS circuit <NUM>.

For example, this avoids the need to provide a stacked NMOS transistor arrangement or additional transistor in the pull-down circuit 314D, unlike in the pull-down circuit 214D in the HVLS circuit <NUM> in <FIG> for example, to decouple the output node 306B from the negative supply rail 308N during a pre-charge phase. In this example, the pull-down circuit 314D only includes one (<NUM>) NMOS transistor, which is NMOS transistor M3. Thus, as an example, the HVLS circuit <NUM> is capable of operating at more extreme voltage differences between the lower and higher voltage domains VDH and VDL, because of the ratio of the pull-down strength of the pull-down circuit 314D through NMOS transistor M3 to the pull-up strength of a pull-up circuit 314U through PMOS transistors M4 and M5. The absence of an additional NMOS transistor in the pull-down circuit 314D does not further weaken the pull-down path to the negative supply rail 308N relative to the pull up path to the positive supply rail 308P such that the drive strength of the pull-down circuit 314D must be increased and/or providing the gate G of the NMOS transistor M3 with lower threshold voltage Vt relative to pull-up PMOS transistors M4 and M5.

With continuing reference to <FIG>, the HVLS circuit <NUM> can be provided in an integrated circuit (IC) <NUM> that may, for example, be provided in a system-on-a-chip (SoC) <NUM> with an integrated processor and memory systems. The HVLS circuit <NUM> is powered by a higher supply voltage VDD-H received from the first, positive supply rail 308P in the higher voltage domain VDH to be able to generate the output signal OUTB in the higher voltage domain VDH. For example, a voltage level of a supply voltage supplying power in the lower voltage domain VDL may be <NUM> Volts (V), while a voltage level of a supply voltage supplying power in the higher voltage domain VDH may be <NUM> V. The output signal OUTB is a complement voltage logic state from the pre-conditioned input signal INC, but the HVLS circuit <NUM> can include an inverter circuit <NUM> that inverts the output signal OUTB to output signal OUT on output node <NUM> having the same logic state as the input signal IN and the pre-conditioned input signal INC. For example, using the supply voltage example above, if the input signal IN were <NUM> V, meaning a logic high or '<NUM>' state in the lower voltage domain VDL, the HVLS circuit <NUM> will generate the output signal OUT at approximately <NUM> V as a logic high or '<NUM>' state in the higher voltage domain VDH.

The HVLS circuit <NUM> is a dynamic voltage level shifter circuit meaning that the output signal OUTB is generated on the output node 306B in an evaluation phase after pre-charging of the output node 306B in a pre-charge phase. In this regard, the HVLS circuit <NUM> includes a pre-charge circuit <NUM> coupled the output node 306B and the positive supply rail 308P. The pre-charge circuit <NUM> is a PMOS logic circuit <NUM> in this example, which is PMOS transistor M0 in this example. The pre-charge circuit <NUM> is configured to couple the positive supply rail 308P to the output node 306B to pre-charge the output node 306B to the higher supply voltage VDD-H in response to the pre-charge control signal CTRLH indicating a pre-charge state. For example, the pre-charge control signal CTRLH may be a clock signal wherein the pre-charge state is indicated by a logic low / '<NUM>' value. By the pre-charge circuit <NUM> pre-charging the output node 306B, this is what is meant by a "half-voltage" level shifter. If the logic state of the input signal IN is a low logic state, the output node 306B is already pre-charged to the high logic state. Thus, in an evaluation phase when the pre-charge control signal CTRLH is in a high logic state, the pull-up circuit 314U only has to pull-up the voltage level at the output node <NUM> to the higher supply voltage VDD-H in the evaluation phase from the pre-charged voltage level at the output node 306B during the pre-charge phase to generate the voltage level shifted output signal OUTB at the higher voltage domain VDH. However, if the logic state of the input signal IN is a high logic state during an evaluation phase from the pre-charged voltage level at the output node 306B during the pre-charge phase to generate the voltage level shifted output signal OUTB at the higher voltage domain VDH-However, if the logic state of the input signal IN is a high logic state during an evaluation phase, the pull-down circuit 314D pulls the output node 306B down to the second, negative supply rail 308N to generate the voltage level shifted output signal OUTB in a logic high state in the higher voltage domain VDH.

With continuing reference to <FIG>, when the pre-charge control signal CTRLH and the pre-condition control signal CTRLL is in a discharge logic state, which is a higher voltage level or logic T state in this example, the HVLS circuit <NUM> is in an evaluation phase. In this manner, with the pre-conditioning circuit <NUM> being an AND gate <NUM> in this example, the pre-conditioning circuit <NUM> passes the actual logic state of the input signal IN as the pre-conditioned input signal INc to the pull-up circuit 314U and the pull-down circuit 314D. In this manner, depending on the logic state of the preconditioned input signal INc, the pull-up circuit 314U will pull up the output node <NUM> to the higher voltage level VDD-H of the positive supply rail 308P or the pull-down circuit 314D will pull down the output node 306B to the lower voltage level VDD-L of the negative supply rail 308N to generate the output signal OUTB in the higher voltage domain VDH- If the logic state of the pre-conditioned input signal INc is in the charge logic state in the evaluation phase, which is a lower voltage level or logic ' <NUM> ' state in example, the PMOS transistor M4 of the pull-up circuit 314U will be turned on to couple to the positive supply rail 308P to the output node 306B, and the NMOS transistor M3 of the pull-down circuit 314D will be turned off to decouple the negative supply rail 308N from the output node 306B. On the other hand, if the logic state of the pre-conditioned input signal INc is in the discharge logic state in the evaluation phase, which is a higher voltage level or logic '<NUM>' state in example, the PMOS transistor M4 of the pull-up circuit 314U will be turned off to decouple the positive supply rail 308P from the output node 306B, and the NMOS transistor M3 of the pull-down circuit 314D will be turned on to couple the negative supply rail 308N to the output node 306B.

With continuing reference to <FIG>, the pull-down circuit 314D in this example includes an NMOS logic circuit <NUM> which is the NMOS transistor M3 in this example. A gate G of the NMOS transistor M3 is coupled to a pre-conditioned input node <NUM> that carries the pre-conditioned input signal INc generated by the preconditioning circuit <NUM>. A first, source electrode S of the NMOS transistor M3 is coupled to the negative supply rail 308N. A second, drain electrode D of the NMOS transistor M3 is coupled to the output node 306B. By the gate G of the NMOS transistor M3 being coupled to the pre-conditioned input node <NUM>, the pre-conditioned input signal INC being in a discharge logic state will turn on the NMOS transistor M3 in an evaluation phase to pull-down and couple the output node 306B to the negative supply rail 308N to generate the voltage level shifted output signal OUTB in the higher voltage domain VDH. As discussed above, if the HVLS circuit <NUM> is in a pre-charge phase where the pre-charge control signal CTRLH is in a charge logic state to turn on the pre-charge circuit <NUM> to couple the output node 306B to the higher supply voltage VDD-H of the positive supply rail 308P, the pre-conditioned input signal INC will turn off the NMOS transistor M3 regardless of the logic state of the input signal IN.

With continuing reference to <FIG>, the pull-up circuit 314U in this example includes a PMOS logic circuit <NUM> provided in the form of a stacked PMOS transistor circuit. The PMOS logic circuit <NUM> includes the PMOS transistor M4 and the PMOS transistor M5 coupled together in a stacked arrangement in this example. A gate G of the PMOS transistor M4 is coupled to the pre-conditioned input node <NUM> that carries the pre-conditioned input signal INC generated by the pre-conditioning circuit <NUM>. A first, source electrode S of the PMOS transistor M4 is coupled to a second, drain electrode D of the second PMOS transistor M5 in the pull-up circuit 314U. A gate G of the PMOS transistor M5 is coupled to the output node <NUM>. A first, source electrode S of the PMOS transistor M5 is coupled to the positive supply rail 308P. By the gate G of the PMOS transistor M4 being coupled to the pre-conditioned input node <NUM>, the pre-conditioned input signal INC being in a charge logic state will turn on the PMOS transistor M4 in an evaluation phase to pull-up and couple the output node 306B to the positive supply rail 308P to generate the voltage level shifted output signal OUTB in the higher voltage domain VDH. The gate G of the PMOS transistor M5 is controlled by the output signal OUT on the output node <NUM> to turn off the PMOS transistor M5 and prevent a crow-bar condition between the positive supply rail 308P and the negative supply rail 308N because of the contention between the NMOS transistor M3 and the PMOS transistor M4.

The HVLS circuit <NUM> also includes an optional keeper circuit <NUM>, which is an NMOS logic circuit <NUM> in this example. The NMOS logic circuit <NUM> in this example is an NMOS transistor M1. A gate G of the NMOS transistor M1 is coupled to the output node <NUM>. A first, source electrode S of the NMOS transistor M1 is coupled to the negative supply rail 308N. A second, drain electrode D of the NMOS transistor M1 is coupled to the output node 306B. The NMOS transistor M1 is configured to "keep" or maintain the coupling of the output node 306B to the negative supply rail 308N to keep the output node 306B in the discharge logic state if the input signal IN is in a discharge logic state on the next evaluation phase, so that the pre-charge circuit <NUM> does not pre-charge the output node OUTB in the next evaluation phase. The discharge logic state is maintained on the output node 306B until the next evaluation phase in which the input signal IN, and thus the output node 306B, are in the charge logic state.

<FIG> is a flowchart illustrating an exemplary process <NUM> of the HVLS circuit <NUM> in <FIG> pre-conditioning the input signal IN in response to the pre-charge phase to avoid contention between the pull-down circuit 314D and the pre-charge circuit <NUM>. In this regard, as illustrated in <FIG>, the process <NUM> includes the pre-conditioning circuit <NUM> receiving the input signal IN in the first, lower voltage domain VDL (block <NUM>). The process <NUM> also includes the pre-conditioning circuit <NUM> generating the pre-conditioned input signal INc on the node <NUM> in the first, lower voltage domain VDL at a voltage level indicating a charge logic state, in response to the pre-condition control signal CTRLL having a voltage level of a charge logic state indicating a pre-charge phase (block <NUM>). The process <NUM> also includes coupling the first, positive supply rail 308P to the output node OUTB in response to the pre-charge control signal CTRLH indicating the pre-charge phase (block <NUM>). The process <NUM> also includes coupling the first, positive supply rail 308P to the output node OUTB in response to the pre-conditioned input signal INc having a voltage level of a charge logic state, and in response to the pre-condition control signal CTRLL having a voltage level of a discharge logic state indicating an evaluation phase (block <NUM>). The process <NUM> also includes decoupling the second, negative supply rail 308N from the output node 306B in response to the pre-condition control signal CTRLL indicating the pre-charge phase (block <NUM>). The process <NUM> also includes coupling the second, negative supply rail 308N to the output node OUTB in response to the pre-conditioned input signal INC having a voltage level of a discharge logic state, and in response to the pre-condition control signal CTRLL indicating the evaluation phase (block <NUM>).

Other variations of the HVLS circuit <NUM> in <FIG> can be provided that are also configured to pre-condition an input signal IN in a lower voltage domain VDL in response to the pre-charge phase to avoid contention between a pull-down circuit and a pre-charge circuit in a higher voltage domain VDH. In this regard, <FIG> is a schematic diagram of another exemplary VLS circuit <NUM> also provided in the form of a HVLS circuit <NUM>. The HVLS circuit <NUM> can be provided in an IC <NUM> that may, for example, be provided in a SoC <NUM> with an integrated processor and memory systems. The HVLS circuit <NUM> in <FIG> includes some common components with the HVLS circuit <NUM> in <FIG>, which are shown with common element numbers between <FIG> and <FIG>. Thus, these common components will not be re-described.

The HVLS circuit <NUM> in <FIG> includes an optional keeper circuit <NUM> that is similar to the keeper circuit <NUM> in the HVLS circuit <NUM> in <FIG>. The keeper circuit <NUM> is an NMOS logic circuit <NUM>. In addition to the NMOS transistor M1 being coupled to the output node OUTB, the NMOS logic circuit <NUM> includes an additional second NMOS transistor M6. The source electrode S of the NMOS transistor M1 is coupled to a first, drain electrode D of the NMOS transistor M6. A second, source electrode S of the NMOS transistor M6 is coupled to the negative supply rail 308N. The gate G of the NMOS transistor M6 is coupled to the pre-charge control signal CTRLH. Thus, the NMOS transistor M6 is turned on when the pre-charge control signal CTRLH is in the discharge logic state in this example indicating the evaluation phase, to "keep" or maintain a coupling of the output node 306B to the negative supply rail 308N to keep the output node 306B in the discharge logic state. The output node 306B is maintained coupled to the negative supply rail 308N through the input signal IN subsequently being in a charge state until the pre-charge control signal CTRLH indicates the pre-charge phase causing the pre-charge circuit <NUM> to pre-charge the output node 306B.

<FIG> is a schematic diagram of another exemplary VLS circuit <NUM> also provided in the form of a HVLS circuit <NUM>. The HVLS circuit <NUM> can be provided in an IC <NUM> that may for example, be provided in a SoC <NUM> with an integrated processor and memory systems. The HVLS circuit <NUM> in <FIG> includes some common components with the HVLS circuit <NUM> in <FIG>, which are shown with common element numbers between <FIG> and <FIG>. Thus, these common components will not be re-described.

The HVLS circuit <NUM> in <FIG> includes an optional clamp circuit <NUM> that is similar to the keeper circuit <NUM> in the HVLS circuit <NUM> in <FIG>. The clamp circuit <NUM> is provided as an NMOS logic circuit <NUM> in this example. The NMOS logic circuit <NUM> includes an NMOS transistor M7. The clamp circuit <NUM>, and more particularly the gate G of the NMOS transistor M7, is coupled to a clamp control signal CLAMP. The clamp circuit <NUM>, and more particularly the source electrode S of the NMOS transistor M7, is coupled to the negative supply rail 308N. The clamp circuit <NUM>, and more particularly the drain electrode D of the NMOS transistor M7, is coupled to the input node <NUM>. The clamp circuit <NUM> is configured to pull down the input node <NUM> to the negative supply rail 308N, or alternatively the node <NUM>, in response to the clamp control signal CLAMP indicating a clamp state, which is a high voltage level or '<NUM>' logic state in this example. In this manner, the pull-down circuit 314D will not be turned on or switch as long as the clamp control signal CLAMP is asserted having the clamp state. For example, the clamp control signal CLAMP may be asserted by the clamp state when it is desired to collapse the node <NUM>, such as when it is desired to put the HVLS circuit <NUM> in an idle or collapsed power mode to conserve power. The clamp control signal CLAMP being asserted by the clamp state prevents the output node 306B from being driven to different states. When it is desired to no longer clamp the HVLS circuit <NUM>, the clamp control signal CLAMP can be driven to a non-clamping state, which is a low voltage level or '<NUM>' logic level in this example.

<FIG> is a schematic diagram of another exemplary VLS circuit <NUM> also provided in the form of a HVLS circuit <NUM>. The HVLS circuit <NUM> can be provided in an IC <NUM> that may for example, be provided in a SoC <NUM> with an integrated processor and memory systems. The HVLS circuit <NUM> includes both the clamp circuit <NUM> in the HVLS circuit <NUM> in <FIG> and the keeper circuit <NUM> in the HVLS circuit <NUM> in <FIG>. The common components between the HVLS circuit <NUM> in <FIG> and the HVLS circuits <NUM>, <NUM> in <FIG> and <FIG> are shown with common element numbers between <FIG>, <FIG>, and <FIG>, which have been described above. Thus, these common components and their functionality do not need to be re-described.

In another aspect, a VLS circuit can be provided that employs a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase to prevent or mitigate contention between a pre-charge circuit and a pull-down circuit. These VLS circuit can include, for example, any of the HVLS circuits <NUM>, <NUM>, <NUM>, <NUM> in <FIG> and <FIG>, or any portion of any components provided therein. Note that these components can be provided in either NMOS or PMOS logic. These VLS circuits can include a means for receiving an input signal in a first voltage domain. These VLS circuits can also include a means for generating a pre-conditioned input signal in the first voltage domain at a voltage level on an input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase. These VLS circuits can also include a means for coupling a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain to an output node in response to a pre-charge control signal indicating the pre-charge phase. These VLS circuits can also include a pull-up means for coupling the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal having a voltage level of a discharge logic state indicating an evaluation phase. These VLS circuits can also include a pull-down means that includes a means for decoupling the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase, and a means for coupling the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal indicating the evaluation phase. The pull-up means in these VLS circuits can also include a means for decoupling the first supply rail from the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal indicating the evaluation phase. The pull-down means in these VLS circuits can also include a means for decoupling the second supply rail from the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal indicating the evaluation phase.

Further, the VLS circuits described above can be included in any circuit or system that has multiple voltage domains and needs to shift signals in a lower voltage domain to a higher voltage domain, or vice versa. In this regard, <FIG> is a schematic diagram of an exemplary multiple voltage domain memory system <NUM> ("memory system <NUM>") that includes a lower voltage domain VDL and a higher voltage domain VDH. The memory system <NUM> includes a memory array <NUM> provided in the higher voltage domain VDH for data retention. The memory array <NUM> includes a plurality of memory bit cells <NUM>(<NUM>)(<NUM>)-<NUM>(M)(N) organized in rows and columns, where 'M' indicates the memory row and 'N' indicates the memory column. Each of the memory bit cells <NUM>(<NUM>)(<NUM>)-<NUM>(M)(N) is configured to store data. To access the memory bit cells <NUM>(<NUM>)(<NUM>)-<NUM>(M)(N) during a memory access operation (i.e., a read or write operation), a word line decoder <NUM> is provided. The word line decoder <NUM> includes an address input interface <NUM> configured to receive a memory address associated with a memory row in the memory array <NUM> to be addressed. The address input interface <NUM> is in the lower voltage domain VDL in this example.

The word line decoder <NUM> also includes a word line decoder circuit <NUM> in the lower voltage domain VDL configured to receive the memory address and decode the memory address into a decoded word comprising a plurality of word line bit signals <NUM>(<NUM>)-<NUM>(M). Because the word line bit signals <NUM>(<NUM>)-<NUM>(M) are in the lower voltage domain VDL and the memory array <NUM> is in the higher voltage domain VDH, a plurality of VLS circuits <NUM>(<NUM>)-<NUM>(M) are each coupled to a word line <NUM>(<NUM>)-<NUM>(M) among the plurality of word lines bits <NUM>(<NUM>)-<NUM>(M). Note that the VLS circuits <NUM>(<NUM>)-<NUM>(M) are shown outside of the word line decoder <NUM>, but the VLS circuits <NUM>(<NUM>)-<NUM>(M) can be provided within the word line decoder <NUM>. Further note that the pre-conditioning circuits <NUM> described above that are shown as part of the VLS circuits <NUM>, <NUM>, <NUM>, and <NUM> can be provided separately from the VLS circuits <NUM>(<NUM>)-<NUM>(M) and also as part of the word line decoder <NUM>. The VLS circuits <NUM>(<NUM>)-<NUM>(M) can include HVLS circuits that are configured to condition the word lines bits <NUM>(<NUM>)-<NUM>(M) in the lower voltage domain VDL to avoid contention between a pull-down circuit and a pre-charge circuit. For example, the VLS circuits <NUM>(<NUM>)-<NUM>(M) can include any of the HVLS circuits <NUM>, <NUM>, <NUM>, <NUM> in <FIG> and <FIG> described above as examples, which have already been described and thus do not need to be re-described here. The VLS circuits <NUM>(<NUM>)-<NUM>(M) are configured to generate output word lines <NUM>(<NUM>)-<NUM>(M) which are voltage level shifted signals of the respective word line bit signals <NUM>(<NUM>)-<NUM>(M). Note that only one word line bit signal <NUM>(<NUM>)-<NUM>(M) may be active at one time as the "hot" word line to select the row of memory bit cells <NUM>(<NUM>)()-<NUM>(M)() according to the decoded memory address. The active output word line <NUM>(<NUM>)-<NUM>(M) is asserted in the memory array <NUM> to activate the memory bit cells <NUM>(<NUM>)()-<NUM>(M)() in the selected row.

In a read operation, sense amplifiers <NUM> sense the data of the activated row of memory bit cells <NUM>(<NUM>)()-<NUM>(M)() to provide read data <NUM> to a column decoder <NUM>. The column decoder <NUM> includes a column decoder circuit <NUM> that is controlled by a column address <NUM>. If the column decoder circuit <NUM> is in the lower voltage domain VDL, VLS circuits <NUM>(<NUM>)-<NUM>(N) can be provided to voltage level shift the read data <NUM> from the higher voltage domain VDH to the lower voltage domain VDL to provide the read data <NUM> in the lower voltage domain VDL to another circuit.

VLS circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase to prevent or mitigate contention between a pre-charge circuit and a pull-down circuit, including but not limited to the HVLS circuits <NUM>, <NUM>, <NUM>, <NUM> in <FIG> and <FIG>, respectively, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that can include circuits that include VLS circuits <NUM> employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase to prevent or mitigate contention between a pre-charge circuit and a pull-down circuit, including but not limited to the HVLS circuits <NUM>, <NUM>, <NUM>, <NUM> in <FIG> and <FIG>. For example, the processor-based system <NUM> includes one or more memory systems <NUM> provided in a higher voltage domain and/or split between multiple voltage domains, wherein the memory systems <NUM> can employ VLS circuits <NUM> employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase to prevent or mitigate contention between a pre-charge circuit and a pull-down circuit. These VLS circuits <NUM> can include but are not limited to the HVLS circuits <NUM>, <NUM>, <NUM>, <NUM> in <FIG> and <FIG>, as non-limiting examples.

In this example, the processor-based system <NUM> is provided in an IC <NUM>. The IC <NUM> may be included in or provided as a SoC <NUM>. The processor-based system <NUM> includes a CPU or processor <NUM> that includes one or more processor cores <NUM>(<NUM>)-<NUM>(N). The CPU <NUM> may have a cache memory <NUM> coupled to the processor cores <NUM>(<NUM>)-<NUM>(N) for rapid access to temporarily stored data. The cache memory <NUM> may include the VLS circuits <NUM> employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase to prevent or mitigate contention between a pre-charge circuit and a pull-down circuit. The CPU <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric. For example, the CPU <NUM> can communicate bus transaction requests to the memory systems <NUM> as an example of a slave device.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the memory systems <NUM>, and one or more input devices <NUM>. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The other devices can also include one or more output devices <NUM>, and one or more network interface devices <NUM>. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired.

The other devices can also include one or more display controllers <NUM> as examples. The CPU <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The master devices and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

A processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

Claim 1:
A voltage level shifter, VLS, circuit, comprising:
a pre-conditioning circuit (<NUM>) configured to:
receive an input signal in a first voltage domain; and
generate a pre-conditioned input signal on an input node (<NUM>) in the first voltage domain at a voltage level on the input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase;
a pre-charge circuit (<NUM>) coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain, the pre-charge circuit configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase;
a pull-up circuit (314U) coupled to the first supply rail (308P) and the output node, the pull-up circuit configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal, CTRLL, and the pre-charge control signal, CTRLH, having a voltage level of a discharge logical high state indicating an evaluation phase; and
a pull-down circuit (314D) coupled to the input node (<NUM>) and the second supply rail (308N), the pull-down circuit configured to:
decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and
couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRLL, and the pre-charge control signal, CTRLH, having a voltage level of a discharge logical high state indicating the evaluation phase.