Patent Description:
The invention relates to a display device comprising a thin film transistor in which a gate electrode has a thickness step profile.

<CIT> describes that an image display device has an image display section including an insulating substrate having a matrix of pixels formed on an inner surface thereof and a liquid crystal layer sandwiched between the insulating substrate and a substrate opposing the insulating substrate. The image display device includes signal lines, driver circuits for driving the matrix of pixels via the signal lines, voltage amplifiers formed by polycrystalline semiconductor TFTs and each coupled between one of the signal lines and a corresponding one of the driver circuits. The signal lines, the driver circuits and the voltage amplifiers are formed on a surface of the insulating substrate on a side thereof facing the liquid crystal layer. A channel, a source and a drain of the polycrystalline semiconductor TFTs each are formed of a polycrystalline semiconductor film. A gate insulating film and a gate electrode are superposed on the polycrystalline semiconductor film in the order named. The polycrystalline semiconductor TFTs are provided with a second region of the channel having a threshold voltage higher than a threshold voltage of a first region of the channel on a drain side thereof.

<CIT> describes, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region that are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by impurities, such as inert-gas, metals, Group III elements, Group IV elements and Group V elements, introduced to a predetermined region in this channel region, or by defects generated due to the introduction of these impurities. The disclosure thus provides an arrangement restraining bipolar transistor type behavior to stabilize saturation current and to provide a TFT that can improve reliability.

<CIT> describes that a thin film transistor includes an active layer including a channel portion; a gate electrode spaced apart from the active layer and overlapping at least a part of the active layer; and source and drain electrodes connected with the active layer and spaced apart from each other, wherein the channel portion includes, a first boundary portion connected with one of the source and drain electrodes; a second boundary portion connected with the other one of the source and drain electrodes; and a main channel portion interposed between the first boundary portion and the second boundary portion, and wherein at least a part of the second boundary portion has a thickness smaller than a thickness of the main channel portion.

<CIT> describes that formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

<CIT> describes PROBLEM TO BE SOLVED: To prevent degradation in characteristics of elements such as increase in parasitic capacitor, reduction in breakdown voltage, etc. SOLUTION: Exposure is performed by using a reticle <NUM> having solid pattern on the drain region D side and a plurality of linear slots on the source region S side, and a resist pattern <NUM> of two levels with low source region side and high drain region side is formed on a polycrystalline silicon film <NUM>. The polycrystalline silicon film <NUM> is then etched through the use of the resist pattern <NUM> as a mask to form a gate electrode <NUM> having the same two levels as the resist pattern <NUM>. Subsequently, ion implantation is performed to form a diffusion layer of low impurity density. Side walls 22a, 22b with different widths on the source and drain sides are formed. Another ion implantation is performed to form a diffusion layer of high impurity density.

Since a thin film transistor can be fabricated on a glass substrate or a plastic substrate, the thin film transistor is widely used as a switching device of a display device such as a liquid crystal display device or an organic light emitting device.

The thin film transistor may be categorized into an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor thin film transistor in which an oxide semiconductor is used as an active layer, based on a material constituting the active layer.

Among thin film transistors, since the oxide semiconductor thin film transistor (TFT) may have high mobility and have a large resistance change in accordance with an oxygen content, there is an advantage in that desired properties may be easily obtained. Further, since an oxide constituting an active layer may be grown at a relatively low temperature during a process of fabricating the oxide semiconductor thin film transistor, the fabricating cost of the oxide semiconductor thin film transistor is reduced. In view of the properties of oxide, since an oxide semiconductor is transparent, it is favorable to embody a transparent display device.

A display panel constituting a display device is generally fabricated using one large mother substrate. For example, after a plurality of display panels are fabricated using one large mother substrate, the mother substrate is cut to form each display panel.

In the process of fabricating a display panel using a large-sized mother substrate, large-sized deposition equipment may be used to form a plurality of thin film transistors. When elements are fabricated from the large-area mother substrate, a process deviation may occur for each area. As a result, a performance deviation may occur in elements formed in each area, for example, thin film transistors. When a performance deviation occurs, the thin film transistor formed in a partial area may have a problem in reliability, such as a threshold voltage significantly changed over time of use.

Therefore, when a display panel is fabricated using a large-sized mother substrate, it is required to reduce a performance deviation of the thin film transistor and minimize or avoid deterioration in reliability of the thin film transistor.

The present disclosure has been made in view of the above problems and it is an object of the present disclosure to minimize a performance deviation of a thin film transistor when a display panel is fabricated using a large-sized mother substrate.

It is another object of the present disclosure to provide a thin film transistor of which reliability is not deteriorated over time even though the thin film transistor is fabricated on a large-sized mother substrate.

It is still another object of the present disclosure to provide a thin film transistor comprising a gate electrode having a thickness step profile.

It is further still another object of the present disclosure to provide a display device comprising the above thin film transistor.

In addition to the objects of the present disclosure as mentioned above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

In accordance with claim <NUM> of the invention, the above and other objects can be accomplished by the provision of a display device comprising a substrate, and a plurality of thin film transistors on the substrate, wherein each of the plurality of thin film transistors includes an active layer having a channel portion and a gate electrode spaced apart from the active layer, the substrate includes a first area, the gate electrode of the thin film transistor disposed in the first area includes a first part that at least partially overlaps the channel portion of the active layer, and a second part having a thickness smaller than a thickness of the first part and at least partially overlapping the channel portion of the active layer, and light transmittance of the second part is greater than that of the first part.

The substrate may further include a second area distinguished from the first area, and the gate electrode of the thin film transistor disposed in the second area may have the same height as a height of the first part without a thickness difference.

The substrate further includes a third area distinguished from the first area and the second area, a gate electrode of the thin film transistor disposed in the third area includes a first part that at least partially overlaps the channel portion of the active layer, and a second part having a thickness smaller than the first part and at least partially overlapping the channel portion of the active layer, and the second part of the gate electrode included in the thin film transistor disposed in the third area has a smaller area or a larger thickness than that of the second part of the gate electrode included in the thin film transistor disposeo in the first area.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In a case where 'comprise', 'have', and 'include' described in the present specification are used, another part may be added unless 'only~' is used. The terms of a singular form may include plural forms unless referred to the contrary.

In describing a position relationship, for example, when the position relationship is described as 'upon~', 'above~', 'below~', and 'next to~', one or more portions may be arranged between two other portions unless 'just' or 'direct' is used.

Spatially relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein to easily describe a relationship of one element or elements to another element or elements as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device illustrated in the figure is reversed, the device described to be arranged "below", or "beneath" another device may be arranged "above" another device. Therefore, an exemplary term "below or beneath" may include "below or beneath" and "above" orientations. Likewise, an exemplary term "above" or "on" may include "above" and "below or beneath" orientations.

In describing a temporal relationship, for example, when the temporal order is described as "after," "subsequent," "next," and "before," a case which is not continuous may be included, unless "just" or "direct" is used.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to partition one element from another.

The term "at least one" should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" denotes the combination of all items proposed from one or more of the first item, the second item, and the third item as well as one or more of the first item, the second item, or the third item.

In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

In the embodiments of the present disclosure, a source electrode and a drain electrode are distinguished from each other, for convenience of description. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode in any one embodiment of the present disclosure may be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be the source electrode in another embodiment of the present disclosure.

In some embodiments of the present disclosure, for convenience of description, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, a source region may be a source electrode, and a drain region may be a drain electrode. Also, a source region may be a drain electrode, and a drain region may be a source electrode.

<FIG> is a plan view illustrating a thin film transistor according to one embodiment of the present disclosure, and <FIG> is a cross-sectional view taken along line I-I' of <FIG>.

The thin film transistor <NUM> according to one embodiment of the present disclosure includes an active layer <NUM>, and a gate electrode <NUM> at least partially overlapped with the active layer <NUM>. Referring to <FIG>, the gate electrode <NUM> has a thickness step profile.

Referring to <FIG>, the thin film transistor <NUM> according to one embodiment of the present disclosure is disposed on a substrate <NUM>.

Glass or plastic may be used as the substrate <NUM>. A transparent plastic, e.g., polyimide, having a flexible property may be used as the plastic. When the polyimide is used as the substrate <NUM>, a heat-resistant polyimide capable of enduring a high temperature may be used considering that a high temperature deposition process is performed on the substrate <NUM>.

A buffer layer <NUM> may be disposed on the substrate <NUM>. The buffer layer <NUM> may include at least one of a silicon oxide, a silicon nitride or a metal-based oxide. The buffer layer <NUM> may protect the active layer <NUM> by blocking oxygen (O<NUM>) or moisture (H<NUM>O) permeated from the substrate <NUM>. Further, an upper surface of the substrate <NUM> may be uniform by the buffer layer <NUM>.

Referring to <FIG>, the active layer <NUM> is disposed on the buffer layer <NUM>.

The active layer <NUM> includes a semiconductor material. According to one embodiment of the present disclosure, the active layer <NUM> may include an oxide semiconductor material.

According to one embodiment of the present disclosure, the active layer <NUM> includes a channel portion 130n, a first connection portion 130a and a second connection portion 130b. The first connection portion 130a is in contact with a side of the channel portion 130n, and the second connection portion 130b is in contact with the other side of the channel portion 130n.

The first connection portion 130a and the second connection portion 130b may be formed by selective conductorization for the active layer <NUM>. Providing conductivity to a selected part of active layer <NUM> is referred to as a selective conductorization. Selective conductorization can be performed by doping, plasma treatment, or the like. The first connection portion 130a and the second connection portion 130b are referred to as "conductorization portions". According to one embodiment of the present disclosure, the first connection portion 130a of the active layer <NUM> may be a source area, and the second connection portion 130b may be a drain area, but one embodiment of the present disclosure is not limited thereto, and the first connection portion 130a may be a drain area and the second connection portion 130b may be a source area.

According to one embodiment of the present disclosure, the active layer <NUM> may include at least one of an IGZO(InGaZnO)-based oxide semiconductor material, a GZO(GaZnO)-based oxide semiconductor material, an IGO(InGaO)-based oxide semiconductor material, an IGZTO(InGaZnSnO)-based oxide semiconductor material, a GZTO(GaZnSnO)-based oxide semiconductor material, an IZO(InZnO)-based oxide semiconductor material, an ITZO(InSnZnO)-based oxide semiconductor material, a FIZO(FelnZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO(SilnZnO)-based oxide semiconductor material or a ZnON(Zn-Oxynitride)-based oxide semiconductor material, but one embodiment of the present disclosure is not limited thereto, and the active layer <NUM> may be formed by another oxide semiconductor material known in the art.

Although <FIG> illustrates that the active layer <NUM> is formed of one layer, one embodiment of the present disclosure is not limited thereto. The active layer <NUM> may have a single layered structure, or may have a multi-layered structure.

A gate insulating layer <NUM> is disposed on the active layer <NUM>. The gate insulating layer <NUM> protects the channel portion 130n.

The gate insulating layer <NUM> may include at least one of a silicon oxide, a silicon nitride or a metal-based oxide. The gate insulating layer <NUM> may have a single layered structure, or may have a multi-layered structure.

Referring to <FIG>, the gate insulating layer <NUM> may have a patterned structure. In the process of patterning the gate insulating layer <NUM>, the active layer <NUM> may be selectively conductorized so that the first connection portion 130a and the second connection portion 130b may be formed, but one embodiment of the present disclosure is not limited thereto. The gate insulating layer <NUM> may be disposed on an entire surface of the substrate <NUM> without being patterned (see <FIG>).

The gate electrode <NUM> is disposed on the gate insulating layer <NUM>. The gate electrode <NUM> overlaps the channel portion 130n of the active layer <NUM>.

The gate electrode <NUM> may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd) or titanium (Ti). The gate electrode <NUM> may have a multi-layered structure that includes at least two conductive layers having their respective physical properties different from each other.

In more detail, the gate electrode <NUM> may include at least one of molybdenum (Mo) or titanium (Ti).

According to one embodiment of the present disclosure, the gate insulating layer <NUM> may be patterned by an etching process using the gate electrode <NUM> as a mask. In this process, the active layer <NUM> may be selectively conductorized to form the first connection portion 130a and the second connection portion 130b. In more detail, according to one embodiment of the present disclosure, an area of the active layer <NUM>, which overlaps the gate electrode <NUM>, is not conductorized, and thus may become the channel portion 130n having semiconductor characteristics, an area of the active layer, which does not overlap the gate electrode <NUM>, is conductorized, and thus may become the first connection portion 130a and the second connection portion 130b.

According to one embodiment of the present disclosure, the gate electrode <NUM> includes a first part <NUM> and a second part <NUM>. Referring to <FIG>, the first part <NUM> at least partially overlaps the channel portion 130n. The second part <NUM> has a thickness smaller than a thickness of the first part <NUM>, and at least partially overlaps the channel portion 130n.

Due to a thickness difference between the first part <NUM> and the second part <NUM>, the gate electrode <NUM> may have a thickness step profile. In one embodiment of the present disclosure, the thickness step profile of the gate electrode <NUM> means that one gate electrode <NUM> includes a portion having different thicknesses without having the same thickness.

Referring to <FIG>, the first part <NUM> may be disposed on one side of the gate electrode <NUM>, and the second part <NUM> may be disposed on the other side of the gate electrode <NUM>, but one embodiment of the present disclosure is not limited thereto. The arrangement type of the first part <NUM> and the second part <NUM> may vary as needed.

Referring to <FIG>, the second part <NUM> may have a rectangular plane, but one embodiment of the present disclosure is not limited thereto, and the second part <NUM> may have various planar shapes. For example, the second part <NUM> may have a circular shape, an oval shape, a semi-circular shape, a semi-oval shape, or a polygonal plane, or may have an irregular planar shape.

According to one embodiment of the present disclosure, light transmittance of the second part <NUM> is greater than light transmittance of the first part <NUM>. According to one embodiment of the present disclosure, light transmittance refers to average light transmittance in the range of <NUM> to <NUM>. The light transmittance may be measured by a spectrophotometer in accordance with the known method. For example, a product of KONICA MINOLTA may be used as the spectrophotometer.

According to one embodiment of the present disclosure, the first part <NUM> does not have light transmissive characteristics or is substantially free of light transmissive characteristics, and only the second part <NUM> may have light transmissive characteristics. In more detail, the first part <NUM> of the gate electrode <NUM> may be made to prevent light from being transmitted therethrough in the same manner as the gate electrode that is conventionally known, and the second part <NUM> may be made to transmit light therethrough.

When the second part <NUM> has light transmissive characteristics, light may be transmitted through the second part <NUM> to selectively irradiate light to the channel portion 130n. When light is selectively irradiated to the channel portion 130n, an electron trap generated on an interface between the channel portion 130n and the gate insulating layer <NUM> may be resolved, that is to say the electron trap may be alleviated.

When the active layer <NUM> is formed of an oxide semiconductor, an electron trap may be generated on the interface between the channel portion 130n of the active layer <NUM> and the gate insulating layer <NUM>. When the electron trap is generated, mobility of the thin film transistor <NUM> may be deteriorated, and a threshold voltage of the thin film transistor <NUM> may vary due to the electron trap.

In addition, the electron trap may be non-uniform depending on the use time of the thin film transistor <NUM>. In this case, the threshold voltage of the thin film transistor <NUM> may be unstable. As a result, since reliability of the thin film transistor <NUM> may be deteriorated, it is required to resolve the electron trap to improve reliability of the thin film transistor <NUM>.

According to one embodiment of the present disclosure, light may be transmitted through the second part <NUM> of the gate electrode <NUM>, and the electron trap of the active layer may be resolved by the transmitted light.

For example, when the thin film transistor <NUM> according to one embodiment of the present disclosure is used for the display device, light emitted from the display device may be irradiated to the channel portion 130n by passing through the second part <NUM> of the gate electrode <NUM>. When the light is irradiated to the channel portion 130n, the electron trap generated on the interface between the channel portion 130n and the gate insulating layer <NUM> may be resolved. When the electron trap of the channel portion 130n is resolved, instability of the threshold voltage of the thin film transistor <NUM> may be removed.

In order to resolve the electron trap by light transmission, according to one embodiment of the present disclosure, the second part <NUM> may have light transmittance of <NUM>% to <NUM>%. In more detail, the second part <NUM> may have average light transmittance of <NUM>% to <NUM>% in the range of <NUM> to <NUM>. The light transmittance may be measured by a spectrophotometer, for example, a spectrophotometer from KONICA MINOLTA.

When the light transmittance of the second part <NUM> is less than <NUM>%, an electron trap removal effect by the light transmission may not be sufficiently exhibited. When the light transmittance of the second part <NUM> exceeds <NUM>%, intensity of the light passing through the second part <NUM> may be greater than necessary, so that the channel portion 130n may be damaged, and the thickness of the second part <NUM> may be too thin to achieve light transmittance of more than <NUM>%, whereby film stability of the second part <NUM> may be deteriorated. According to one embodiment of the present disclosure, the second part <NUM> may have light transmittance of <NUM>% to <NUM>%, and may have light transmittance of <NUM>% to <NUM>%.

The thickness of the first part <NUM> and the thickness of the second part <NUM> may vary depending on the material constituting the gate electrode <NUM>. According to one embodiment of the present disclosure, the first part <NUM> and the second part <NUM> may be made of the same material, for example, a metal or a metal alloy.

According to one embodiment of the present disclosure, in order to avoid light transmission through the first part <NUM>, the first part <NUM> may have a thickness of <NUM> or more. When the first part <NUM> is made of a metal or a metal alloy and the thickness of the first part <NUM> is greater than or equal to <NUM>, light may be almost or completely blocked by the first part <NUM>. When the thickness of the first part <NUM> is greater than or equal to <NUM>, the first part <NUM> may have light transmittance close to zero (<NUM>).

According to one embodiment of the present disclosure, the gate electrode <NUM> may have a thickness of <NUM> or less. Therefore, according to one embodiment of the present disclosure, the first part <NUM> may have a thickness of <NUM> to <NUM>. In more detail, the first part <NUM> may have a thickness of <NUM> to <NUM>. Alternatively, the first part <NUM> may have a thickness of <NUM> to <NUM>, may have a thickness of <NUM> to <NUM>, or may have a thickness of <NUM> to <NUM>.

The second part <NUM> may have a thickness of <NUM>% to <NUM>% relative to the thickness of the first part <NUM> to have predetermined light transmittance. When the thickness of the second part <NUM> exceeds <NUM>% of the thickness of the first part <NUM>, a light transmissive effect through the second part <NUM> may hardly occur. On the other hand, when the thickness of the second part <NUM> is less than <NUM>% of the thickness of the first part <NUM>, film stability of the second part <NUM> may be deteriorated.

According to one embodiment of the present disclosure, the second part <NUM> may have a thickness of <NUM> to <NUM> to have light transmittance. The second part <NUM> may be made of a metal or a metal alloy, and light may be transmitted through the second part <NUM> when the thickness of the second part <NUM> is <NUM> to <NUM>. When light is transmitted through the second part <NUM>, the channel portion 130n may be selectively exposed to light.

When the thickness of the second part <NUM> is less than <NUM>, intensity of the light passing through the second part <NUM> may be more increased than necessary, film stability of the gate electrode <NUM> may be deteriorated, and an electric field effect by the gate electrode <NUM> may not be sufficiently expressed. When the thickness of the second part <NUM> exceeds <NUM>, light transmittance may be deteriorated, whereby the light transmissive effect may not be expressed. The thickness of the second part <NUM> may vary depending on the type of the material used as the gate electrode <NUM>, and may be set in consideration of optical characteristics of the material used as the gate electrode <NUM>.

According to one embodiment of the present disclosure, the thickness of the second part <NUM> may range from <NUM> to <NUM>, may range from <NUM> to <NUM>, or may range from <NUM> to <NUM>.

An area of the second part <NUM> may vary depending on light transmittance of the second part <NUM> and the degree of electron trap generated in the thin film transistor <NUM>.

According to one embodiment of the present disclosure, a ratio of an area occupied by the second part <NUM> to a total area where the channel portion 130n and the gate electrode <NUM> overlap each other, based on a plan view, may range from <NUM>% to <NUM>%. Therefore, light transmission may be performed for the area of <NUM>% to <NUM>% of the area of the channel portion 130n.

Based on the plan view, when the area occupied by the second part <NUM> in the entire area where the channel portion 130n and the gate electrode <NUM> overlap each other is less than <NUM>%, the electron trap removal effect by light transmission may not be sufficiently exhibited. On the other hand, when the area occupied by the second part <NUM> in the entire area where the channel portion 130n and the gate electrode <NUM> overlap each other exceeds <NUM>%, a light irradiation area of the channel portion 130n is increased so that carriers may be more increased than necessary, whereby the threshold voltage of the thin film transistor <NUM> may be shifted in a negative (-) direction. In more detail, the area occupied by the second part <NUM> in the entire area where the channel portion 130n and the gate electrode <NUM> overlap each other may range from <NUM>% to <NUM>%, or may range from <NUM>% to <NUM>%.

The detailed area occupied by the second part <NUM> may vary depending on light transmittance of the second part <NUM>. According to one embodiment of the present disclosure, the area of the second part <NUM> may be determined in consideration of light transmittance of the second part <NUM>.

According to one embodiment of the present disclosure, the gate electrode <NUM> has an area transmittance coefficient (ATC) calculated by Equation <NUM> below. According to one embodiment of the present disclosure, the area transmittance coefficient (ATC) defines a relation between the area occupied by the second part <NUM> overlapped with the channel portion 130n and light transmittance of the second part <NUM>.

In the Equation <NUM>, T is light transmittance of the second part <NUM>, and is represented by %. In this case, light transmittance refers to average light transmittance measured in the range of <NUM> to <NUM>.

In the Equation <NUM>, A is an area ratio of the second part <NUM>, and is calculated in Equation <NUM> below.

In the Equation <NUM>, the area of the second part <NUM> that overlaps the channel portion 130n corresponds to an area of the channel portion 130n, which overlaps the second part <NUM>. The area of the gate electrode <NUM> that overlaps the channel portion 130n corresponds to the area of the channel portion 130n.

For example, when light transmittance of the second part <NUM> is <NUM>% and the ratio of the area of the second part <NUM> that overlaps the channel portion 130n to the area of the gate electrode <NUM> that overlaps the channel portion 130n is <NUM>, the area transmittance coefficient (ATC) of the gate electrode <NUM> is as follows<MAT>.

According to one embodiment of the present disclosure, the gate electrode <NUM> may have an area transmittance coefficient (ATC) of <NUM>% to <NUM>%.

When the area transmittance coefficient (ATC) of the gate electrode <NUM> is less than <NUM>%, the amount of light transmitted through the second part <NUM> of the gate electrode <NUM> is reduced, and as a result, the electron trap removal effect by light transmission may not be sufficiently exhibited. On the other hand, when the area transmittance coefficient (ATC) of the gate electrode <NUM> exceeds <NUM>%, the amount of light transmitted through the second part <NUM> of the gate electrode <NUM> increases, and as a result, the channel portion 130n may be damaged or the threshold voltage of the thin film transistor <NUM> may be shifted in the negative (-) direction due to excessive light irradiation to the channel portion 130n.

According to one embodiment of the present disclosure, the gate electrode <NUM> may have an area transmittance coefficient (ATC) of <NUM>% to <NUM>%, or may have an area transmittance coefficient (ATC) of <NUM>% to <NUM>%.

Referring to <FIG>, an interlayer insulating layer <NUM> may be disposed on the gate electrode <NUM>. The interlayer insulating layer <NUM> may be made of an organic or inorganic insulating material. The interlayer insulating layer <NUM> may be formed of a composite layer of an organic layer and an inorganic layer.

According to one embodiment of the present disclosure, the thin film transistor <NUM> may include a first electrode <NUM> and a second electrode <NUM>, which are disposed on the interlayer insulating layer <NUM>. The first electrode <NUM> may serve as a source electrode, and the second electrode <NUM> may serve as a drain electrode, but one embodiment of the present disclosure is not limited thereto. The first electrode <NUM> may serve as a drain electrode, and the second electrode <NUM> may serve as a source electrode. In addition, the first connection portion 130a and the second connection portion 130b may serve as a source electrode and a drain electrode, respectively, and the first electrode <NUM> and the second electrode <NUM> may serve as connection electrodes between elements.

Referring to <FIG>, the first electrode <NUM> and the second electrode <NUM> may be connected to the active layer <NUM> through contact holes CH1 and CH2, respectively. In detail, the first electrode <NUM> may be in contact with the first connection portion 130a through the contact hole CH1. The second electrode <NUM> may be spaced apart from the first electrode <NUM> to contact the second connection portion 130b through the contact hole CH2.

<FIG> is a plan view illustrating a thin film transistor <NUM> according to another embodiment of the present disclosure. Hereinafter, the description of the elements that are already described will be omitted to avoid redundancy.

Referring to <FIG>, the second part <NUM> of the gate electrode <NUM> may have a trapezoidal flat plane. The second part <NUM> may be disposed on one side of the gate electrode <NUM>. The second part <NUM> may be disposed in a direction of the second connection portion 130b that is in contact with the second electrode <NUM> serving as a drain electrode. That is to say that the longest side of the trapezoidal shaped plane of the second part may be disposed towards the second connection portion 130b that is in contact with the second electrode <NUM>.

However, another embodiment of the present disclosure is not limited to <FIG>. For example, the second part <NUM> may be disposed in a direction of the first connection portion 130a that is in contact with the first electrode <NUM> serving as a source electrode. Also, as already described above, the second part <NUM> may have a circular shape, an oval shape, a semi-circular shape, a semi-oval shape, or a polygonal plane, or may have various planar shapes in addition to the shape shown in the drawing.

<FIG> is a plan view illustrating a thin film transistor <NUM> according to another embodiment of the present disclosure.

Referring to <FIG>, the second part <NUM> of the gate electrode <NUM> may have a semi-circular shape. A planar shape of the second part <NUM> in which a diameter portion of a semi-circle is directed toward an edge portion of the gate electrode <NUM> is shown in <FIG>, but another embodiment of the present disclosure is not limited thereto. The diameter portion of the semi-circle may be disposed toward a center portion of the gate electrode <NUM>.

<FIG> is a plan view illustrating a thin film transistor <NUM> according to still another embodiment of the present disclosure, and <FIG> is a cross-sectional view taken along line II-II' of <FIG>.

Referring to <FIG>, the second part <NUM> may be positioned at the center of the gate electrode <NUM> based on a plan view. In detail, the second part <NUM> may overlap the channel portion 130n, and the first part <NUM> may be disposed to surround the second part <NUM>.

Referring to <FIG>, based on the cross-sectional view, the first part <NUM> more protruded than the second part <NUM> may be disposed on both sides of the second part <NUM>.

<FIG> is a plan view illustrating a thin film transistor <NUM> according to further still another embodiment of the present disclosure.

Referring to <FIG>, the second part <NUM> overlaps the channel portion 130n, and may have a circular or oval plane. The first part <NUM> may be disposed to surround the second part <NUM> of a circular or oval shape.

<FIG> is a cross-sectional view illustrating a thin film transistor <NUM> according to further still another embodiment of the present disclosure.

Referring to <FIG>, a light shielding layer <NUM> may be disposed on the substrate <NUM>. The light shielding layer <NUM> may be made of a material having light shielding characteristics. The light shielding layer <NUM> shields light incident from the outside to protect the active layer <NUM>.

Referring to <FIG>, the buffer layer <NUM> may be disposed on the light shielding layer <NUM>. Although not shown in <FIG>, a lower buffer layer may be disposed between the substrate <NUM> and the light shielding layer <NUM>.

Referring to <FIG>, the light shielding layer <NUM> may be connected to the first electrode <NUM> through a contact hole formed in the buffer layer <NUM> and the interlayer insulating layer <NUM>, but further still another embodiment of the present disclosure is not limited thereto. The light shielding layer <NUM> may be connected to the first electrode <NUM>, or may be connected to another line or ground portion. The light shielding layer <NUM> may be in a floating state without being connected to another line as the case may be.

In the thin film transistors <NUM>, <NUM>, <NUM>, <NUM> and <NUM> shown in <FIG>, <FIG>, <FIG> and <FIG>, the light shielding layer <NUM> may be disposed on the substrate <NUM>, and the buffer layer <NUM> may be disposed on the light shielding layer <NUM>.

The thin film transistor <NUM> of <FIG> includes a gate insulating layer <NUM> that is not patterned. As shown in <FIG> and <FIG>, the gate insulating layer <NUM> may be patterned to correspond to the gate electrode <NUM>, but as shown in <FIG>, the gate insulating layer <NUM> may not be patterned.

When the gate insulating layer <NUM> is not patterned, the active layer <NUM> may be selectively conductorized by selective ion doping, selective hydrogen injection or selective ultraviolet irradiation, so that the first connection portion 130a and the second connection portion 130b may be formed. In addition, contact holes CH1 and CH2 passing through the gate insulating layer <NUM> may be formed.

According to further still another embodiment of the present disclosure, the active layer <NUM> of the thin film transistor <NUM> may have a multi-layered structure. Referring to <FIG>, the active layer <NUM> may include a first oxide semiconductor layer <NUM> and a second oxide semiconductor layer <NUM> on the first oxide semiconductor layer <NUM>.

The first oxide semiconductor layer <NUM> may support the second oxide semiconductor layer <NUM>. Therefore, the first oxide semiconductor layer <NUM> may be referred to as a "support layer". The channel portion 130n may be mainly formed in the second oxide semiconductor layer <NUM>. Therefore, the second oxide semiconductor layers <NUM> may be referred to as a "channel layer", but one embodiment of the present disclosure is not limited thereto, and the channel portion 130n may be also formed on the first oxide semiconductor layer <NUM>.

A structure in which the active layer <NUM> includes a first oxide semiconductor layer <NUM> and a second oxide semiconductor layer <NUM> is referred to as a bi-layer structure.

In the thin film transistor <NUM> of <FIG>, the active layer <NUM> further includes a third oxide semiconductor layer <NUM> on the second oxide semiconductor layer <NUM>, in comparison with the thin film transistor <NUM> of <FIG>.

Referring to <FIG>, the active layer <NUM> includes a first oxide semiconductor layer <NUM>, a second oxide semiconductor layer <NUM>, and a third oxide semiconductor layer <NUM>, but further still another embodiment of the present disclosure is not limited thereto, and the active layer may further include another semiconductor layer. With three oxide semiconductor layers, the middle layer is protected from damage during manufacture in both directions, for example the bottom oxide semiconductor layer protects the middle semiconductor layer from gases during manufacture, and the top oxide semiconductor layer protects the middle semiconductor layer from etchant or gases during manufacture.

<FIG> is a graph illustrating light transmittance of a metal and an alloy based on a thickness and a wavelength.

In <FIG>, "LT1" denotes light transmittance according to a wavelength of a molybdenum titanium alloy (MoTi) having a thickness of <NUM>, "LT2" denotes light transmittance according to a wavelength of molybdenum (Mo) having a thickness of <NUM>, and "LT3" denotes light transmittance according to a wavelength of a molybdenum titanium alloy (MoTi) having a thickness of <NUM>.

Referring to <FIG>, it is noted that light transmittance varies depending on a type of a metal, a type of an alloy and a thickness of the metal or alloy.

According to one embodiment of the present disclosure, the thickness of the second part <NUM> of the gate electrode <NUM> may be determined depending on the type of the metal or alloy and the degree of deterioration of reliability of the thin film transistor by the electron trap.

<FIG> is a plan view illustrating a mother panel <NUM> according to another embodiment of the present disclosure.

According to one embodiment of the present disclosure, one panel having a plurality of display panels is referred to as a mother panel. A display panel constituting a display device is generally fabricated in one large mother substrate. When a plurality of display panels are fabricated in one large mother substrate, the mother panel may be formed. The mother panel is cut to form each display panel.

In a fabricating process of a display panel using a large-sized mother substrate, a plurality of thin film transistors are formed on the mother substrate. In order to form a large number of thin film transistors on the large-sized mother substrate, a large-sized deposition apparatus is used, and a process such as exposure and etching is performed for a large area. As a result, a process deviation may be generated for each area of the mother substrate. Due to this process deviation, the degree of electron trap may vary for each thin film transistor.

<FIG> illustrates an embodiment of the case that one mother panel <NUM> includes six display panels Panel <NUM>, Panel <NUM>, Panel <NUM>, Panel <NUM>, Panel <NUM> and Panel <NUM>. In <FIG>, an area represented by "①" refers to a first area having low reliability of an element, an area represented by "②" refers to a second area having high reliability of an element, and an area represented by "③" refers to a third area having middle-level reliability of an element.

According to another embodiment of the present disclosure, the degree of reliability may be determined based on the density of the electron trap generated in the thin film transistor. An area having a high density of the electron trap may be classified into a first area (area ①) having low reliability, an area having a low density of the electron trap may be classified into a second area (area ②) having high reliability, and an area having a middle-level density of the electron trap may be classified into a third area (area ③) having middle-level reliability.

Since a problem of the electron trap in the thin film transistor occurs in the first area (area ①) having low reliability, the second part <NUM> may be formed in the gate electrode <NUM>. As the electron trap becomes serious, the area of the second part <NUM> may be larger or the second part <NUM> may be formed to be thin.

In the second area (area ②) having high reliability, since the problem of the electron trap in the thin film transistor is not large, the second part <NUM> may not be formed in the gate electrode <NUM>.

In the third area (area ③) having middle-level reliability, the problem of the electron trap occurs in the thin film transistor but the degree of the electron trap is not large. Therefore, the second part <NUM> may be formed in the gate electrode <NUM> to have a small area, or the second part <NUM> may be formed to be thick.

<FIG> is a result of PBTS measurement of a thin film transistor, and <FIG> is a cross-sectional view illustrating a thin film transistor according to a reference example.

In detail, <FIG> is a result of PBTS measurement of thin film transistors disposed in the first area (area ①) of the mother panel <NUM> shown in <FIG>. "Embodiment <NUM>" in <FIG> shows the result of the PBTS measurement for the thin film transistor <NUM> having the structure of <FIG>. In the graph represented by the Embodiment <NUM>, light is transmitted through the second part <NUM> of the gate electrode <NUM>, so that PBTS is measured under the condition that light is irradiated to a portion of the channel portion 130n.

"Reference Example" in <FIG> shows the result of PBTS measured for the thin film transistor according to the Reference Example. As shown in <FIG>, the thin film transistor according to the Reference Example has a structure similar to that of <FIG>, and does not include the second part <NUM> of the gate electrode <NUM>. The thickness of the gate electrode <NUM> is the same as that of the first part <NUM> of <FIG>.

PBTS (Positive Bias Temperature Stress) refers to stress under the condition that a positive(+) bias voltage and a constant temperature are applied.

According to one embodiment of the present disclosure, the PBTS for the thin film transistor may be evaluated by measuring a variation ΔVth of the threshold voltage of the thin film transistor under the condition that a positive(+) bias voltage and a constant temperature are applied. The PBTS for the thin film transistor may be expressed as a variation ΔVth of the threshold voltage of the thin film transistor under the PBTS condition.

<FIG> is a graph illustrating a variation of the threshold voltage of the thin film transistor based on the time (seconds, sec) in a state that temperature stress of <NUM> and a positive (+) bias voltage are applied to the thin film transistor according to the Embodiment <NUM> and the Reference Example, which is formed in the first area (area ①) of the mother panel <NUM>.

In the thin film transistor according to the Embodiment <NUM>, light is transmitted through the second part <NUM> of the gate electrode <NUM>, whereby the light is irradiated to a portion of the channel portion 130n. On the other hand, in the thin film transistor according to the Reference Example, no external light is irradiated to the channel portion 130n.

Referring to <FIG>, in the thin film transistor according to the Embodiment <NUM>, which includes the gate electrode <NUM> having the second part <NUM>, it is noted that the threshold voltage Vth is not changed significantly over time even though the thin film transistor is formed in the first area (area ①) having low reliability among the areas of the mother panel <NUM>.

On the other hand, in the thin film transistor according to the Reference Example, it is noted that the threshold voltage Vth is changed over time. Referring to <FIG>, when the thin film transistor is formed in the first area (area ①) having low reliability, the threshold voltage Vth of the thin film transistor is changed over time, so that reliability of the thin film transistor is deteriorated.

On the other hand, it is noted that the thin film transistor according to one embodiment of the present disclosure has excellent driving stability under the condition of PBTS even though it has been formed in the first area (area ①) having low reliability.

In the thin film transistor that includes an active layer <NUM> made of an oxide semiconductor, when the electron trap occurs on the interface between the channel portion 130n of the active layer <NUM> and the gate insulating layer <NUM>, mobility of the thin film transistor <NUM> may be deteriorated so that the threshold voltage may be changed. As shown in the Reference Example of <FIG>, when the threshold voltage is changed, it is evaluated that reliability of the thin film transistor is not good.

In the thin film transistor according to the Embodiment <NUM>, light is transmitted through the second part <NUM> of the gate electrode <NUM>, and the electron trap may be resolved by the transmitted light. As a result, the thin film transistor according to the Embodiment <NUM> may maintain the threshold voltage Vth to be almost constant as shown in <FIG> even though it is used for a long period of time under the worst stress condition.

Another embodiment of the present disclosure provides a mother panel <NUM> that may be divided into a plurality of display panels by cutting.

The mother panel <NUM> according to another embodiment of the present disclosure may include at least one of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

In detail, the mother panel <NUM> may include a mother substrate having one or more display panels Panel <NUM>, Panel <NUM>, Panel <NUM>, Panel <NUM>, Panel <NUM> and Panel <NUM> and a plurality of thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> disposed on the mother substrate.

The mother substrate includes a first area (area ①) and a second area (area ②), which are distinguished from each other. The first area of the mother substrate corresponds to an area (area ①) having low reliability of an element, and the second area corresponds to an area (area ②) having high reliability of an element. The first area (area ①) of the mother substrate corresponds to the first area of the mother panel <NUM>, and the second area (area ②) of the mother substrate corresponds to the second area of the mother panel <NUM>.

Each of the plurality of thin film transistors disposed on the mother substrate includes an active layer <NUM> and a gate electrode <NUM>. The active layer <NUM> includes a channel portion 130n.

The gate electrode <NUM> of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> disposed in the first area (area ①) having low reliability of the element may include a first part <NUM> and a second part <NUM>. The first part <NUM> at least partially overlaps the channel portion 130n of the active layer <NUM>. The second part <NUM> has a thickness smaller than that of the first part <NUM>, and at least partially overlaps the channel portion 130n of the active layer <NUM>. In addition, light transmittance of the second part <NUM> is greater than that of the first part <NUM>.

The gate electrode <NUM> of the thin film transistor disposed in the second area (area ②) having high reliability of the element may not include the second part <NUM>. The gate electrode <NUM> of the thin film transistor disposed in the second area (area ②) may have the same thickness as that of the first part <NUM>. For example, the thin film transistor disposed in the second area (area ②) may have the structure shown in <FIG>.

For example, the gate electrode <NUM> of the thin film transistor disposed in the second area (area ②) of the mother substrate may have the same thickness as that of the first part <NUM> of the gate electrode <NUM> of the thin film transistor disposed in the second area without a thickness step profile. In more detail, the entire gate electrode <NUM> of the thin film transistor disposed in the second area of the mother substrate may have the same thickness as that of the first part <NUM>.

According to another embodiment of the present disclosure, the mother substrate includes a third area (area ③) distinguished from the first area (area ①) and the second area (area ②). The third area (area ③) of the mother substrate corresponds to an area (area ③) having middle-level reliability. The third area (area ③) of the mother substrate corresponds to a third area of the mother panel <NUM>.

Since the thin film transistor included in the third area (area ③) has middle-level reliability, the area of the second part <NUM> may be reduced as compared with the thin film transistor included in the first area (area ①).

In detail, the gate electrode <NUM> of the thin film transistor disposed in the third area (area ③) includes a first part <NUM> and a second part <NUM>. The first part <NUM> overlaps at least a portion of the channel portion 130n of the active layer <NUM>. The second part <NUM> has a thickness smaller than that of the first part <NUM>, and at least partially overlaps the channel portion 130n of the active layer <NUM>. The gate electrode <NUM> of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> disposed in the third area (area ③) of the mother substrate includes a first part <NUM> and a second part <NUM>.

The area of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) is smaller than the area of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①). Alternatively, the thickness of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) is greater than the thickness of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

For example, the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) may have a smaller area or a larger thickness as compared with the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

Hereinafter, the display devices according to another embodiment of the present disclosure will be described. The display devices according to another embodiment of the present disclosure may include the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. The display device may comprise an LED, OLED, LCD, PDP, microLED, or a miniLED display device.

<FIG> is a schematic view illustrating a display device <NUM> according to further still another embodiment of the present disclosure.

As shown in <FIG>, the display device <NUM> according to further still another embodiment of the present disclosure includes a display panel <NUM>, a gate driver <NUM>, a data driver <NUM> and a controller <NUM>.

Gate lines GL and data lines DL are disposed in the display panel <NUM> and pixels P are disposed in intersection areas of the gate lines GL and the data lines DL. An image is displayed by driving of the pixels P.

The controller <NUM> controls the gate driver <NUM> and the data driver <NUM>.

The controller <NUM> outputs a gate control signal GCS for controlling the gate driver <NUM> and a data control signal DCS for controlling the data driver <NUM> by using a signal supplied from an external system (not shown). Also, the controller <NUM> samples input image data input from the external system, realigns the sampled data and supplies the realigned digital image data RGB to the data driver <NUM>.

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst and a gate clock GCLK. Also, control signals for controlling a shift register may be included in the gate control signal GCS.

The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL.

The data driver <NUM> supplies a data voltage to the data lines DL of the display panel <NUM>. In detail, the data driver <NUM> converts the image data RGB input from the controller <NUM> into an analog data voltage and supplies the data voltage to the data lines DL.

The gate driver <NUM> may include a shift register <NUM>.

The shift register <NUM> sequentially supplies gate pulses to the gate lines GL for one frame by using the start signal and the gate clock, which are transmitted from the controller <NUM>. In this case, one frame means a time period when one image is output through the display panel <NUM>. The gate pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) disposed in the pixel P.

Also, the shift register <NUM> supplies a gate-off signal capable of turning off a switching element, to the gate line GL for the other period of one frame, at which the gate pulse is not supplied. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

According to one embodiment of the present disclosure, the gate driver <NUM> may be packaged on the display panel <NUM>. In this way, a structure in which the gate driver <NUM> is directly packaged on the display panel <NUM> will be referred to as a Gate In Panel (GIP) structure.

The gate driver <NUM> may include a plurality of thin film transistors. The plurality of thin film transistors included in the gate driver <NUM> may be disposed in the shift register <NUM>.

According to one embodiment of the present disclosure, each of the plurality of thin film transistors disposed in the gate driver <NUM> includes an active layer <NUM> and a gate electrode <NUM>. The active layer <NUM> includes a channel portion 130n. The gate electrode <NUM> of the thin film transistor disposed in the gate driver <NUM> may include a second part <NUM> or not. The thin film transistor disposed in the gate driver <NUM> may have the same structure as that of each of the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, or may have the structure shown in <FIG>.

For example, the gate electrode <NUM> of the thin film transistor disposed in the gate driver <NUM> may have a second part <NUM>, or may have the same thickness as that of the first part <NUM> of the gate electrode of the thin film transistor disposed in the pixel driving circuit without thickness step profile.

<FIG> is a circuit diagram illustrating any one pixel P of <FIG>, <FIG> is a plan view illustrating a pixel P of <FIG>, and <FIG> is a cross-sectional view taken along line III-III' of <FIG>.

The circuit diagram of <FIG> is an equivalent circuit diagram for the pixel P of the display device <NUM> that includes an organic light emitting diode (OLED) as a display element <NUM>. The pixel P includes a display element <NUM> and a pixel driving circuit PDC for driving the display element <NUM>.

According to further still another embodiment of the present disclosure, the display device <NUM> includes a plurality of pixels P having a pixel driving circuit PDC. The pixel driving circuit PDC includes a first thin film transistor TR1 and a second thin film transistor TR2. At least one of the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> may be used as at least one of the first thin film transistor TR1 or the second thin film transistor TR2.

According to further still another embodiment of the present disclosure, the first thin film transistor TR1 is a driving transistor, and the second thin film transistor TR2 is a switching transistor.

The second thin film transistor TR2 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls applying of the data voltage Vdata.

A driving power line PL provides a driving voltage Vdd to the display element <NUM>, and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode (OLED) that is the display element <NUM>.

When the second thin film transistor TR2 is turned on by the scan signal SS applied from the gate driver <NUM> through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to a gate electrode G2 of the first thin film transistor TR1 connected with the display element <NUM>. The data voltage Vdata is charged in a storage capacitor C1 formed between the gate electrode G2 and a source electrode S2 of the first thin film transistor TR1.

The amount of a current supplied to the organic light emitting diode (OLED), which is the display element <NUM>, through the first thin film transistor TR1 is controlled in accordance with the data voltage Vdata, whereby a gray scale of light emitted from the display element <NUM> may be controlled.

Referring to <FIG> and <FIG>, the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the substrate <NUM>.

The substrate <NUM> may be made of glass or plastic. Plastic having a flexible property, for example, polyimide (PI) may be used as the substrate <NUM>.

Light shielding layers <NUM> and <NUM> are disposed on the substrate <NUM>. The light shielding layers <NUM> and <NUM> may shield light incident from the outside to protect the active layers A1 and A2.

A buffer layer <NUM> is disposed on the light shielding layers <NUM> and <NUM>. The buffer layer <NUM> is made of an insulating material, and protects the active layers A1 and A2 from external water or oxygen.

The active layer A1 of the fist thin film transistor TR1 and the active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer <NUM>. The active layers A1 and A2 may include, for example, an oxide semiconductor material. The active layers A1 and A2 may be made of an oxide semiconductor layer made of an oxide semiconductor material. The active layers A1 and A2 may have a multi-layered structure.

A gate insulating layer <NUM> is disposed on the active layers A1 and A2.

A gate electrode G1 of the first thin film transistor TR1 and a gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer <NUM>.

Both of the gate electrodes G1 and G2 may include a first part <NUM> and a second part <NUM>. The first part <NUM> at least partially overlaps the channel portions of the active layers A1 and A2. The second part <NUM> has a thickness smaller than a thickness of the first part <NUM>, and at least partially overlaps the channel portions of the active layers A1 and A2. Due to the thickness difference between the first part <NUM> and the second part <NUM>, the gate electrodes G1 and G2 may have a thickness step profile.

Light transmittance of the second part <NUM> is greater than that of the first part <NUM>.

Also, a gate line GL may be disposed on the gate insulating layer <NUM>. The gate electrode G2 of the second thin film transistor TR2 may be extended from the gate line GL, but one embodiment of the present disclosure is not limited thereto, and a portion of the gate line GL may be the gate electrode G2 of the second thin film transistor TR2.

Referring to <FIG> and <FIG>, a first capacitor electrode C11 of the storage capacitor C1 is disposed in the same layer as the gate electrodes G1 and G2. The first capacitor electrode C11 may be connected to the gate electrode G1 of the first thin film transistor TR1. The first capacitor electrode C11 may be integrally formed with the gate electrode G1 of the first thin film transistor TR1.

An interlayer insulating layer <NUM> is disposed on the gate electrodes G1 and G2, the gate line GL and the first capacitor electrode C11. The interlayer insulating layer <NUM> may be made of an organic or inorganic insulating material.

A source electrode S1 and a drain electrode D1 of the first thin film transistor TR1 and a source electrode S2 and a drain electrode D2 of the second thin film transistor TR2 are disposed on the interlayer insulating layer <NUM>. The data line DL, the driving power line PL, and a second capacitor electrode C12 of the storage capacitor C1 may be disposed on the interlayer insulating layer <NUM>.

A portion of the driving power line PL may be extended to become the drain electrode D1 of the first thin film transistor TR1. The drain electrode D1 of the first thin film transistor TR1 is connected to the active layer A1 through a contact hole H1.

The source electrode S1 of the first thin film transistor TR1 may be connected to the active layer A1 through a contact hole H2, and may be connected to the light shielding layer <NUM> through another contact hole H3.

The source electrode S1 of the first thin film transistor TR1 and the second capacitor electrode C12 are connected to each other. The source electrode S1 of the first thin film transistor TR1 and the second capacitor electrode C12 may be integrally formed.

A portion of the data line DL may be extended to become the source electrode S2 of the second thin film transistor TR2. The source electrode S2 of the second thin film transistor TR2 may be connected to the active layer A2 through a contact hole H4.

A drain electrode D2 of the second thin film transistor TR2 may be connected to the active layer A2 through a contact hole H5, may be connected to the light shielding layer <NUM> through another contact hole H6, and may be connected to the first capacitor electrode C11 through another contact hole H7.

A planarization layer <NUM> is disposed on the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1, the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2, the data line DL, the driving power line PL, and the second capacitor electrode C12.

The planarization layer <NUM> is made of an insulating layer, planarizes upper portions of the first thin film transistor TR1 and the second thin film transistor TR2, and protects the first thin film transistor TR1 and the second thin film transistor TR2.

A first pixel electrode <NUM> of the display element <NUM> is disposed on the planarization layer <NUM>. The first pixel electrode <NUM> is in contact with the second capacitor electrode C12 through a contact hole H8 formed in the planarization layer <NUM>. As a result, the first pixel electrode <NUM> may be connected to the source electrode S1 of the first thin film transistor TR1.

A bank layer <NUM> is disposed at an edge of the first pixel electrode <NUM>. The bank layer <NUM> defines a light emission area of the display element <NUM>.

An organic light emitting layer <NUM> is disposed on the first pixel electrode <NUM>, and a second pixel electrode <NUM> is disposed on the organic light emitting layer <NUM>. Therefore, the display element <NUM> is completed. The display element <NUM> shown in <FIG> and <FIG> is an organic light emitting diode OLED. Therefore, the display device <NUM> according to further still another embodiment of the present disclosure is an organic light emitting display device.

<FIG> is a circuit diagram illustrating any one pixel P of a display device <NUM> according to further still another embodiment of the present disclosure.

<FIG> is an equivalent circuit diagram illustrating a pixel P of an organic light emitting display device.

The pixel P of the display device <NUM> shown in <FIG> includes an organic light emitting diode (OLED) that is a display element <NUM> and a pixel driving circuit PDC for driving the display element <NUM>. The display element <NUM> is connected with the pixel driving circuit PDC.

In the pixel P, signal lines DL, GL, PL, RL and SCL for supplying a signal to the pixel driving circuit PDC are disposed.

The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving the pixel is supplied to the driving power line PL, a reference voltage Vref is supplied to a reference line RL and a sensing control signal SCS is supplied to a sensing control line SCL.

The pixel driving circuit PDC includes, for example, a second thin film transistor TR2 (switching transistor) connected with the gate line GL and the data line DL, a first thin film transistor TR1 (driving transistor) for controlling a magnitude of a current output to the display element <NUM> in accordance with the data voltage Vdata transmitted through the second thin film transistor TR2, and a third thin film transistor TR3 (reference transistor) for sensing characteristics of the first thin film transistor TR1.

A storage capacitor C1 is positioned between the gate electrode of the first thin film transistor TR1 and the display element <NUM>.

The second thin film transistor TR2 is turned on by the scan signal SS supplied to the gate line GL to transmit the data voltage Vdata, which is supplied to the data line DL, to the gate electrode of the first thin film transistor TR1.

The third thin film transistor TR3 is connected to a first node n1 between the first thin film transistor TR1 and the display element <NUM> and the reference line RL, and thus is turned on or off by the sensing control signal SCS and senses characteristics of the first thin film transistor TR1, which is a driving transistor, for a sensing period.

A second node n2 connected with the gate electrode of the first thin film transistor TR1 is connected with the second thin film transistor TR2. The storage capacitor C1 is formed between the second node n2 and the first node n1.

When the second thin film transistor TR2 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the first thin film transistor TR1. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the first thin film transistor TR1.

When the first thin film transistor TR1 is turned on, the current is supplied to the display element <NUM> through the first thin film transistor TR1 in accordance with the driving voltage Vdd for driving the pixel, whereby light is output from the display element <NUM>.

<FIG> is a circuit diagram illustrating any one pixel of a display device <NUM> according to further still another embodiment of the present disclosure.

The pixel driving circuit PDC includes thin film transistors TR1, TR2, TR3 and TR4.

In the pixel P, signal lines DL, EL, GL, PL, SCL and RL for supplying a driving signal to the pixel driving circuit PDC are disposed.

In comparison with the pixel P of <FIG>, the pixel P of <FIG> further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL.

Also, the pixel driving circuit PDC of <FIG> further includes a fourth thin film transistor TR4 that is an emission control transistor for controlling a light emission timing of the first thin film transistor TR1, in comparison with the pixel driving circuit PDC of <FIG>.

The third thin film transistor TR3 is connected to the reference line RL, and thus is turned on or off by the sensing control signal SCS and senses characteristics of the first thin film transistor TR1, which is a driving transistor, for a sensing period.

The fourth thin film transistor TR4 transfers the driving voltage Vdd to the first thin film transistor TR1 in accordance with the emission control signal EM or shields the driving voltage Vdd. When the fourth thin film transistor TR4 is turned on, a current is supplied to the first thin film transistor TR1, whereby light is output from the display element <NUM>.

The pixel driving circuit PDC according to further still another embodiment of the present disclosure may be formed in various structures in addition to the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

The display device <NUM> of <FIG> is a liquid crystal display device. The pixel P of the display device <NUM> shown in <FIG> includes a pixel driving unit PDC and a liquid crystal capacitor Clc connected to the pixel driving unit PDC. The liquid crystal capacitor Clc corresponds to a display element.

The pixel driving circuit PDC includes a thin film transistor TR connected to the gate line GL and the data line DL, a pixel electrode <NUM> connected to the thin film transistor TR, a common electrode <NUM> facing the pixel electrode <NUM>, and a storage capacitor Cst connected between the thin film transistor TR and the common electrode <NUM>. The liquid crystal capacitor Clc is connected between the thin film transistor TR and the common electrode <NUM> in parallel with the storage capacitor Cst.

The liquid crystal capacitor Clc charges a differential voltage between the data signal supplied to the pixel electrode through the thin film transistor TR and a common voltage Vcom supplied to the common electrode <NUM>, and controls the light-transmissive amount by driving a liquid crystal in accordance with the charged voltage. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

The display device <NUM> according to further still another embodiment of the present disclosure may include at least one of the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>.

Referring to <FIG>, the display device <NUM> may include a substrate <NUM>, a gate driver <NUM>, a data driver <NUM> and a controller <NUM>.

The gate lines GL and the data lines DL may be disposed on the substrate <NUM>, and the pixel P may be disposed in the intersection areas of the gate lines GL and the data lines DL to constitute a display panel (not shown, see "<NUM>" of <FIG>). A plurality of pixels P may be disposed on the substrate <NUM>. The pixel P may include a display element <NUM> and a thin film transistor for driving the display element <NUM>. According to further still another embodiment of the present disclosure, an area of the substrate <NUM>, in which the pixels P are disposed, may be referred to as a display portion. The display panel of the display device <NUM> according to further still another embodiment of the present disclosure may correspond to the panel <NUM> shown in <FIG>, for example.

Referring to <FIG>, the gate driver <NUM> may be disposed on the substrate <NUM>. The gate driver <NUM> may include a plurality of thin film transistors.

The display device <NUM> according to further still another embodiment of the present disclosure may include a substrate <NUM> and a plurality of thin film transistors on the substrate <NUM>.

As already described above, each of the plurality of thin film transistors includes an active layer <NUM> having a channel portion 130n and a gate electrode <NUM> spaced apart from the active layer <NUM>.

The substrate <NUM> includes a first area (area ①). The first area (area ①) of the substrate <NUM> may correspond to a first area having low reliability in the mother panel <NUM> of <FIG>.

A thin film transistor is disposed in the first area (area ①) of the substrate <NUM>. At least one of the above-described thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> may be applied to the thin film transistor disposed in the first area (area ①) of the substrate <NUM>.

In detail, the gate electrode <NUM> of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> disposed in the first area (area ①) of the substrate <NUM> includes a first part <NUM> that at least partially overlaps the channel portion 130n of the active layer <NUM>, and a second part <NUM> having a thickness smaller than a thickness of the first part <NUM>. The second part <NUM> at least partially overlaps the channel portion 130n of the active layer <NUM>. In addition, light transmittance of the second part <NUM> is greater than light transmittance of the first part <NUM>. Hereinafter, a detailed description of the structure of the thin film transistor will be omitted to avoid redundancy.

According to further still another embodiment of the present disclosure, at least a portion of the gate driver <NUM> may be positioned in the first area (area ①) of the substrate <NUM>, and at least a portion of the thin film transistor included in the gate driver <NUM> may be disposed in the first area (area ①). Therefore, the gate driver <NUM> may include at least one of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

A portion of the plurality of pixels P disposed on the substrate <NUM> may be disposed in the first area (area ①) of the substrate <NUM>. Therefore, at least a portion of the pixels P may include at least one of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

Referring to <FIG>, the substrate <NUM> may include a second area (area ②) that is distinguished from the first area (area ①). The second area (area ②) of the substrate <NUM> may correspond to a second area having high reliability in the mother panel <NUM> of <FIG>.

The gate electrode of the thin film transistor disposed in the second area (area ②) may have the same height as that of the first part <NUM> without a thickness difference. For example, a thin film transistor having the structure shown in <FIG> may be applied to the thin film transistor disposed in the second area (area ②).

According to further still another embodiment of the present disclosure, at least a portion of the gate driver <NUM> may be included in the second area (area ②) of the substrate <NUM>. Therefore, a portion of the gate driver <NUM> may include a thin film transistor having the structure shown in <FIG>.

A portion of the plurality of pixels P disposed on the substrate <NUM> may be disposed in the second area (area ) of the substrate <NUM>. Therefore, at least a portion of the pixels P may include a thin film transistor having the structure shown in <FIG>.

The substrate <NUM> also includes a third area (area ③) that is distinguished from the first area (area ①) and the second area (area ②). The third area (area ③) of the substrate <NUM> may correspond to a third area having middle-level reliability in the mother panel <NUM> of <FIG>.

The gate electrode of the thin film transistor disposed in the third area (area ③) includes a first part <NUM> that at least partially overlaps the channel portion 130n of the active layer <NUM>, and a second part <NUM> having a thickness smaller than a thickness of the first part <NUM>. The second part <NUM> at least partially overlaps the channel portion 130n of the active layer <NUM>. In addition, light transmittance of the second part <NUM> may be greater than light transmittance of the first part <NUM>.

The area of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) may be smaller than that of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

The thickness of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) may be greater than a thickness of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

The second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the third area (area ③) has a smaller area or a larger thickness than that of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

According to further still another embodiment of the present disclosure, at least a portion of the gate driver <NUM> may be included in the third area (area ③) of the substrate <NUM>. Therefore, the gate driver <NUM> may include at least one of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

In the thin film transistor disposed in the third area (area ③) among the thin film transistors of the gate driver <NUM>, the second part <NUM> of the gate electrode <NUM> may have a smaller area or a larger thickness than that of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

A portion of the plurality of pixels P disposed on the substrate <NUM> may be disposed in a third area (area ③) of the substrate <NUM>. Therefore, at least a portion of the pixels P may include at least one of the thin film transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>.

In the thin film transistor of the pixel P disposed in the third area (area ③), the second part <NUM> of the gate electrode <NUM> may have a smaller area or a larger thickness than that of the second part <NUM> of the gate electrode <NUM> included in the thin film transistor disposed in the first area (area ①).

According to the present disclosure, the following advantageous effects may be obtained.

The thin film transistor according to one embodiment of the present disclosure includes a gate electrode having a first part having a relatively large thickness and a second part having a relatively small thickness. According to one embodiment of the present disclosure, light is transmitted through the second part of the gate electrode and the electron trap of the active layer is resolved by the transmitted light, whereby reliability of the thin film transistor may be prevented from being deteriorated.

According to one embodiment of the present disclosure, light is transmitted through the second part of the gate electrode having a small thickness, and the transmitted light is irradiated to the interface between the active layer and the gate insulating layer, whereby the electron trap on the interface between the active layer and the gate insulating layer may be resolved. As a result, the threshold voltage of the thin film transistor may be prevented from being changed.

In detail, according to one embodiment of the present disclosure, the variation of the threshold voltage of the thin film transistor may be avoided or minimized under the condition of positive(+) bias temperature stress (PBTS) in which a positive(+) bias voltage and a constant temperature are applied.

The display device according to one embodiment of the present disclosure may include the above-described thin film transistor, thereby preventing display quality from being deteriorated over time to maintain excellent display quality.

Claim 1:
A display device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising:
a substrate (<NUM>); and
a plurality of thin film transistors (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> ,<NUM>, <NUM>) on the substrate,
wherein each of the plurality of thin film transistors includes an active layer (<NUM>, A1, A2) having a channel portion (130n) and a gate electrode (<NUM>, G1, G2) spaced apart from the active layer,
the substrate includes a first area,
the gate electrode of the thin film transistor disposed in the first area includes:
a first part (<NUM>) that at least partially overlaps the channel portion of the active layer; and
a second part (<NUM>) having a thickness smaller than that of the first part and at least partially overlapping the channel portion of the active layer, and
light transmittance of the second part is greater than that of the first part,
wherein the substrate further includes a third area distinguished from the first area,
a gate electrode of the thin film transistor disposed in the third area includes:
a first part that at least partially overlaps the channel portion of the active layer; and
a second part having a thickness smaller than the first part and at least partially overlapping the channel portion of the active layer, and
the second part of the gate electrode included in the thin film transistor disposed in the third area has a smaller area or a larger thickness than that of the second part of the gate electrode included in the thin film transistor disposed in the first area.