Patent Description:
A video is a set of static pictures (or "frames") capturing the visual information. To reduce the storage memory and the transmission bandwidth, a video can be compressed before storage or transmission and decompressed before display. The compression process is usually referred to as encoding and the decompression process is usually referred to as decoding. There are various video coding formats which use standardized video coding technologies, most commonly based on prediction, transform, quantization, entropy coding and in-loop filtering. The video coding standards, such as the High Efficiency Video Coding (HEVC/H. <NUM>) standard, the Versatile Video Coding (VVC/H. <NUM>) standard AVS standards, specifying the specific video coding formats, are developed by standardization organizations. With more and more advanced video coding technologies being adopted in the video standards, the coding efficiency of the new video coding standards get higher and higher.

<CIT> relates to a method of video processing which includes determining, for a conversion between a current block of a video and a coded representation of the video, whether a syntax element indicating usage of a skip mode for an intra-block copy (IBC) coding model is included in the coded representation according to a rule that specifies that signaling of the syntax element is based on a dimension of the current block and/or a maximum allowed dimension for a block that is coded using the IBD coding model.

<CIT> relates to a video signal decoding device which includes a processor characterized by determining a result value that indicates the direction for dividing the current transform block on the basis of preset conditions, dividing the current transform block into a plurality of transform blocks on the basis of the result value, and decoding a video signal by using the plurality of transform blocks, wherein the preset conditions include a condition pertaining to a color component of the current transform block.

<NPL>, relates to Draft <NUM> of an ITU-T Recommendation and ISO/IEC International Standard entitled Versatile Video Coding, developed by a joint collaborative team of ITU-T and ISO/IEC experts known as the Joint Video Experts Team (JVET).

According to aspects, there are provided a method of encoding, a method of decoding, an apparatus for encoding, an apparatus for decoding, and a computer-readable medium as set forth in the appended claims. Other features will be apparent from the dependent claims, and the description which follows.

Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying figures. Various features shown in the figures are not drawn to scale.

The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims. Particular aspects of the present disclosure are described in greater detail below. The terms and definitions provided herein control, if in conflict with terms and/or definitions incorporated by reference.

The Joint Video Experts Team (JVET) of the ITU-T Video Coding Expert Group (ITU-T VCEG) and the ISO/IEC Moving Picture Expert Group (ISO/IEC MPEG) is currently developing the Versatile Video Coding (VVC/H. <NUM>) standard. The VVC standard is aimed at doubling the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC/H. <NUM>) standard. In other words, VVC's goal is to achieve the same subjective quality as HEVC/H. <NUM> using half the bandwidth.

In order to achieve the same subjective quality as HEVC/H. <NUM> using half the bandwidth, the JVET has been developing technologies beyond HEVC using the joint exploration model (JEM) reference software. As coding technologies were incorporated into the JEM, the JEM achieved substantially higher coding performance than HEVC.

The VVC standard has been developed recent, and continues to include more coding technologies that provide better compression performance. VVC is based on the same hybrid video coding system that has been used in modern video compression standards such as HEVC, H. <NUM>/AVC, MPEG2, H. <NUM>, etc..

A video is a set of static pictures (or "frames") arranged in a temporal sequence to store visual information. A video capture device (e.g., a camera) can be used to capture and store those pictures in a temporal sequence, and a video playback device (e.g., a television, a computer, a smartphone, a tablet computer, a video player, or any end-user terminal with a function of display) can be used to display such pictures in the temporal sequence. Also, in some applications, a video capturing device can transmit the captured video to the video playback device (e.g., a computer with a monitor) in real-time, such as for surveillance, conferencing, or live broadcasting.

For reducing the storage space and the transmission bandwidth needed by such applications, the video can be compressed before storage and transmission and decompressed before the display. The compression and decompression can be implemented by software executed by a processor (e.g., a processor of a generic computer) or specialized hardware. The module for compression is generally referred to as an "encoder," and the module for decompression is generally referred to as a "decoder. " The encoder and decoder can be collectively referred to as a "codec. " The encoder and decoder can be implemented as any of a variety of suitable hardware, software, or a combination thereof. For example, the hardware implementation of the encoder and decoder can include circuitry, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combinations thereof. The software implementation of the encoder and decoder can include program codes, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process fixed in a computer-readable medium. Video compression and decompression can be implemented by various algorithms or standards, such as MPEG- <NUM>, MPEG-<NUM>, MPEG-<NUM>, H. 26x series, or the like. In some applications, the codec can decompress the video from a first coding standard and re-compress the decompressed video using a second coding standard, in which case the codec can be referred to as a "transcoder.

The video encoding process can identify and keep useful information that can be used to reconstruct a picture and disregard unimportant information for the reconstruction. If the disregarded, unimportant information cannot be fully reconstructed, such an encoding process can be referred to as "lossy. " Otherwise, it can be referred to as "lossless. " Most encoding processes are lossy, which is a tradeoff to reduce the needed storage space and the transmission bandwidth.

The useful information of a picture being encoded (referred to as a "current picture") include changes with respect to a reference picture (e.g., a picture previously encoded and reconstructed). Such changes can include position changes, luminosity changes, or color changes of the pixels, among which the position changes are mostly concerned. Position changes of a group of pixels that represent an object can reflect the motion of the object between the reference picture and the current picture.

A picture coded without referencing another picture (i.e., it is its own reference picture) is referred to as an "I-picture. " A picture coded using a previous picture as a reference picture is referred to as a "P-picture. " A picture coded using both a previous picture and a future picture as reference pictures (i.e., the reference is "bi-directional") is referred to as a "B-picture.

<FIG> illustrates structures of an example video sequence <NUM>, according to some embodiments of the present disclosure. Video sequence <NUM> can be a live video or a video having been captured and archived. Video <NUM> can be a real-life video, a computer-generated video (e.g., computer game video), or a combination thereof (e.g., a real-life video with augmented-reality effects). Video sequence <NUM> can be inputted from a video capture device (e.g., a camera), a video archive (e.g., a video file stored in a storage device) containing previously captured video, or a video feed interface (e.g., a video broadcast transceiver) to receive video from a video content provider.

As shown in <FIG>, video sequence <NUM> can include a series of pictures arranged temporally along a timeline, including pictures <NUM>, <NUM>, <NUM>, and <NUM>. Pictures <NUM>-<NUM> are continuous, and there are more pictures between pictures <NUM> and <NUM>. In <FIG>, picture <NUM> is an I-picture, the reference picture of which is picture <NUM> itself. Picture <NUM> is a P-picture, the reference picture of which is picture <NUM>, as indicated by the arrow. Picture <NUM> is a B-picture, the reference pictures of which are pictures <NUM> and <NUM>, as indicated by the arrows. In some embodiments, the reference picture of a picture (e.g., picture <NUM>) can be not immediately preceding or following the picture. For example, the reference picture of picture <NUM> can be a picture preceding picture <NUM>. It should be noted that the reference pictures of pictures <NUM>-<NUM> are only examples, and the present disclosure does not limit embodiments of the reference pictures as the examples shown in <FIG>.

Typically, video codecs do not encode or decode an entire picture at one time due to the computing complexity of such tasks. Rather, they can split the picture into basic segments, and encode or decode the picture segment by segment. Such basic segments are referred to as basic processing units ("BPUs") in the present disclosure. For example, structure <NUM> in <FIG> shows an example structure of a picture of video sequence <NUM> (e.g., any of pictures <NUM>-<NUM>). In structure <NUM>, a picture is divided into <NUM>×<NUM> basic processing units, the boundaries of which are shown as dash lines. In some embodiments, the basic processing units can be referred to as "macroblocks" in some video coding standards (e.g., MPEG family, H. <NUM>, or H. <NUM>/AVC), or as "coding tree units" ("CTUs") in some other video coding standards (e.g., H. <NUM>/HEVC or H. <NUM>/VVC). The basic processing units can have variable sizes in a picture, such as <NUM>×<NUM>, <NUM>×<NUM>, <NUM>×<NUM>, <NUM>×<NUM>, <NUM>×<NUM>, <NUM>×<NUM>, or any arbitrary shape and size of pixels. The sizes and shapes of the basic processing units can be selected for a picture based on the balance of coding efficiency and levels of details to be kept in the basic processing unit.

The basic processing units can be logical units, which can include a group of different types of video data stored in a computer memory (e.g., in a video frame buffer). For example, a basic processing unit of a color picture can include a luma component (Y) representing achromatic brightness information, one or more chroma components (e.g., Cb and Cr) representing color information, and associated syntax elements, in which the luma and chroma components can have the same size of the basic processing unit. The luma and chroma components can be referred to as "coding tree blocks" ("CTBs") in some video coding standards (e.g., H. <NUM>/HEVC or H. <NUM>/VVC). Any operation performed to a basic processing unit can be repeatedly performed to each of its luma and chroma components.

Video coding has multiple stages of operations, examples of which are shown in <FIG> and <FIG>. For each stage, the size of the basic processing units can still be too large for processing, and thus can be further divided into segments referred to as "basic processing sub-units" in the present disclosure. In some embodiments, the basic processing sub-units can be referred to as "blocks" in some video coding standards (e.g., MPEG family, H. <NUM>, or H. <NUM>/AVC), or as "coding units" ("CUs") in some other video coding standards (e.g., H. <NUM>/HEVC or H. <NUM>/VVC). A basic processing sub-unit can have the same or smaller size than the basic processing unit. Similar to the basic processing units, basic processing sub-units are also logical units, which can include a group of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in a computer memory (e.g., in a video frame buffer). Any operation performed to a basic processing sub-unit can be repeatedly performed to each of its luma and chroma components. It should be noted that such division can be performed to further levels depending on processing needs. It should also be noted that different stages can divide the basic processing units using different schemes.

For example, at a mode decision stage (an example of which is shown in <FIG>), the encoder can decide what prediction mode (e.g., intra-picture prediction or inter--picture prediction) to use for a basic processing unit, which can be too large to make such a decision. The encoder can split the basic processing unit into multiple basic processing sub-units (e.g., CUs as in H. <NUM>/HEVC or H. <NUM>/VVC), and decide a prediction type for each individual basic processing sub-unit.

For another example, at a prediction stage (an example of which is shown in <FIG>), the encoder can perform prediction operation at the level of basic processing sub-units (e.g., CUs). However, in some cases, a basic processing sub-unit can still be too large to process. The encoder can further split the basic processing sub-unit into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H. <NUM>/HEVC or H. <NUM>/VVC), at the level of which the prediction operation can be performed.

For another example, at a transform stage (an example of which is shown in <FIG>), the encoder can perform a transform operation for residual basic processing sub-units (e.g., CUs). However, in some cases, a basic processing sub-unit can still be too large to process. The encoder can further split the basic processing sub-unit into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H. <NUM>/HEVC or H. <NUM>/VVC), at the level of which the transform operation can be performed. It should be noted that the division schemes of the same basic processing sub-unit can be different at the prediction stage and the transform stage. For example, in H. <NUM>/HEVC or H. <NUM>/VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

In structure <NUM> of <FIG>, basic processing unit <NUM> is further divided into <NUM>×<NUM> basic processing sub-units, the boundaries of which are shown as dotted lines. Different basic processing units of the same picture can be divided into basic processing sub-units in different schemes.

In some implementations, to provide the capability of parallel processing and error resilience to video encoding and decoding, a picture can be divided into regions for processing, such that, for a region of the picture, the encoding or decoding process can depend on no information from any other region of the picture. In other words, each region of the picture can be processed independently. By doing so, the codec can process different regions of a picture in parallel, thus increasing the coding efficiency. Also, when data of a region is corrupted in the processing or lost in network transmission, the codec can correctly encode or decode other regions of the same picture without reliance on the corrupted or lost data, thus providing the capability of error resilience. In some video coding standards, a picture can be divided into different types of regions. For example, H. <NUM>/HEVC and H. <NUM>/VVC provide two types of regions: "slices" and "tiles. " It should also be noted that different pictures of video sequence <NUM> can have different partition schemes for dividing a picture into regions.

For example, in <FIG>, structure <NUM> is divided into three regions <NUM>, <NUM>, and <NUM>, the boundaries of which are shown as solid lines inside structure <NUM>. Region <NUM> includes four basic processing units. Each of regions <NUM> and <NUM> includes six basic processing units. It should be noted that the basic processing units, basic processing sub-units, and regions of structure <NUM> in <FIG> are only examples, and the present disclosure does not limit embodiments thereof.

<FIG> illustrates a schematic diagram of an exemplary encoder <NUM> in a hybrid video coding system, according to some embodiments of the present disclosure. Video encoder <NUM> may perform intra- or inter-coding of blocks within video frames, including video blocks, or partitions or sub-partitions of video blocks. Intra-coding may rely on spatial prediction to reduce or remove spatial redundancy in video within a given video frame. Inter-coding may rely on temporal prediction to reduce or remove temporal redundancy in video within adjacent frames of a video sequence. Intra modes may refer to a number of spatial based compression modes. Inter modes (such as uni-prediction or bi-prediction) may refer to a number of temporal-based compression modes.

Referring to <FIG>, input video signal <NUM> may be processed block by block. For example, the video block unit may be a <NUM>×<NUM> pixel block (e.g., a macroblock (MB)). The size of the video block units may vary, depending on the coding techniques used, and the required accuracy and efficiency. In HEVC, extended block sizes (e.g., a coding tree unit (CTU)) may be used to compress video signals of resolution, e.g., 1080p and beyond. In HEVC, a CTU may include up to 64x64 luma samples corresponding chroma samples, and associated syntax elements. In VVC, the size of a CTU may be further increased to include 128x128 luma samples, corresponding chroma samples, and associated syntax elements. A CTU can be further divided into coding units (CUs) using, for example, quad-tree, binary tree, or ternary tree. A CU may be further partitioned into prediction units (PUs), for which separate prediction methods may be applied. Each input video block may be processed by using spatial prediction unit <NUM> or temporal prediction unit <NUM>.

Spatial prediction unit <NUM> performs spatial prediction (e.g., intra prediction) to the current block/CU using information on the same picture/slice containing the current block. Spatial prediction may use pixels from the already coded neighboring blocks in the same video picture frame/slice to predict the current video block. Spatial prediction may reduce spatial redundancy inherent in the video signal.

Temporal prediction unit <NUM>. performs temporal prediction (e.g., inter prediction) to the current block using information from picture(s)/slice(s) different from the picture/slice containing the current block. Temporal prediction for a video block may be signaled by one or more motion vectors. In unit-directional temporal prediction, only one motion vector indicating one reference picture is used to generate the prediction signal for the current block. On the other hand, in bi-directional temporal prediction, two motion vectors, each indicating a respective reference picture, can be used to generate the prediction signal for the current block. The motion vectors may indicate the amount and the direction of motion between the current block and one or more associated block(s) in the reference frames. If multiple reference pictures are supported, one or more reference picture indices may be sent for a video block. The one or more reference indices may be used to identify from which reference picture(s) in the reference picture store or decoded picture buffer (DPB) <NUM>, the temporal prediction signal may come.

Mode decision and encoder control unit <NUM> in the encoder may choose the prediction mode, for example, based on rate-distortion optimization. Based on the determined prediction mode, the prediction block can be obtained. The prediction block may be subtracted from the current video block at adder <NUM>. The prediction residual may be transformed by transformation unit <NUM> and quantized by quantization unit <NUM>. The quantized residual coefficients may be inverse quantized at inverse quantization unit <NUM><NUM> and inverse transformed at inverse transform unit <NUM> to form the reconstructed residual. The reconstructed residual may be added to the prediction block at adder <NUM> to form the reconstructed video block. The reconstructed video block before loop. -filtering may be used to provide reference samples for intra prediction.

The reconstructed video block may go through loop filtering at loop filter <NUM>. For example, loop filtering such as deblocking filter, sample adaptive offset (SAO), and adaptive loop filter (ALF) may be applied. The reconstructed block after loop filtering may be stored in reference picture store <NUM> and can be used to provide inter prediction reference samples for coding other video blocks. To form the output video bitstream <NUM>, coding mode (e.g., inter or intra), prediction mode information, motion information, and quantized residual coefficients may be sent to the entropy coding unit <NUM> to further reduce the bit rate, before the data are compressed and packed to form bitstream <NUM>.

<FIG> illustrates a schematic diagram of an exemplary decoder <NUM> in a hybrid video coding system, according to some embodiments of the present disclosure. Referring to <FIG>, a video bitstream <NUM> may be unpacked or entropy decoded at entropy decoding unit <NUM>. The coding mode information can be used to determine whether the spatial prediction unit <NUM> or the temporal prediction unit <NUM> is to be selected. The prediction mode information can be sent to the corresponding prediction unit to generate the prediction block. For example, motion compensated prediction may be applied by the temporal prediction unit <NUM>. to form the temporal prediction block.

The residual coefficients may be sent to inverse quantization unit <NUM> and inverse transform unit <NUM> to obtain the reconstructed residual. The prediction block and the reconstructed residual can be added together at <NUM> to form the reconstructed block before loop filtering. The reconstructed block may then go through loop filtering at loop filer <NUM>. For example, loop filtering such as deblocking filter, SAO, and ALF may be applied. The reconstructed block after loop filtering can then be stored in reference picture store <NUM>. The reconstructed data in the reference picture store <NUM> may be used to obtain decoded video <NUM>, or used to predict future video blocks. Decoded video <NUM> may be displayed on a display device, such as a TV, a PC, a smartphone, or a tablet to be viewed by the end-users.

<FIG> is a block diagram of an exemplary apparatus <NUM> for encoding or decoding a video, according to some embodiments of the present disclosure. As shown in <FIG>, apparatus <NUM> can include processor <NUM>. When processor <NUM> executes instructions described herein, apparatus <NUM> can become a specialized machine for video encoding or decoding. Processor <NUM> can be any type of circuitry capable of manipulating or processing information. For example, processor <NUM> can include any combination of any number of a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), a neural processing unit ("NPU"), a microcontroller unit ("MCU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor <NUM> can also be a set of processors grouped as a single logical component. For example, as shown in <FIG>, processor <NUM> can include multiple processors, including processor 402a, processor 402b, and processor 402n.

Apparatus <NUM> can also include memory <NUM> configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in <FIG>, the stored data can include program instructions (e.g., program instructions for implementing the stages in <FIG> or <FIG>) and data for processing. Processor <NUM> can access the program instructions and data for processing (e.g., via bus <NUM>), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory <NUM> can include a high-speed random-access storage device or a non-volatile storage device. In some embodiments, memory <NUM> can include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory <NUM> can also be a group of memories (not shown in <FIG>) grouped as a single logical component.

Bus <NUM> can be a communication device that transfers data between components inside apparatus <NUM>, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

For ease of explanation without causing ambiguity, processor <NUM> and other data processing circuits are collectively referred to as a "data processing circuit" in the present disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of apparatus <NUM>.

Apparatus <NUM> can further include network interface <NUM> to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface <NUM> can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication ("NFC") adapter, a cellular network chip, or the like.

In some embodiments, optionally, apparatus <NUM> can further include peripheral interface <NUM> to provide a connection to one or more peripheral devices. As shown in <FIG>, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), or the like.

It should be noted that video codecs can be implemented as any combination of any software or hardware modules in apparatus <NUM>. For example, some or all stages of encoder <NUM> of <FIG> or decoder <NUM> of <FIG> can be implemented as one or more software modules of apparatus <NUM>, such as program instructions that can be loaded into memory <NUM>. For another example, some or all stages of encoder <NUM> of <FIG> or decoder <NUM> of <FIG> can be implemented as one or more hardware modules of apparatus <NUM>, such as a specialized data processing circuit (e.g., an FPGA, an ASIC, an NPU, or the like).

In the quantization and inverse quantization functional blocks (e.g., quantization unit <NUM> and inverse quantization unit <NUM> of <FIG>, inverse quantization unit <NUM> of <FIG>), a quantization parameter (QP) is used to determine the amount of quantization (and inverse quantization) applied to the prediction residuals. Initial QP values used for coding of a picture or slice may be signaled at the high level, for example, using syntax element init_qp_minus26 in the Picture Parameter Set (PPS) and using syntax element slice_qp_delta in the slice header. Further, the QP values may be adapted at the local level for each CU using delta QP values sent at the granularity of quantization groups.

In VVC, sub-block transform (SBT) is used for an inter-predicted coding unit (CU). In this transform mode, only a sub-part of the residual block is coded for the CU. When inter-predicted CU with syntax element cu_cbf is equal to <NUM>, syntax element cu_sbt_flag can be signaled to indicate whether the whole residual block or a sub-part of the residual block is coded. In the former case, inter multiple transform selected (MTS) information is further parsed to determine the transform type of the CU. In the latter case, a part of the residual block is coded with inferred adaptive transform and the other part of the residual block is zeroed out.

When SBT is used for an inter-predicted CU, SBT type and SBT position information are signaled in the bitstream. There are two SBT types and two SBT positions, as illustrated in <FIG>. For SBT-V (or SBT-H), the transform unit (TU) width (or height) can be equal to half of the CU width (or height) or <NUM>/<NUM> of the CU width (or height), resulting in <NUM>:<NUM> split or <NUM>:<NUM>/<NUM>:<NUM> split. The <NUM>:<NUM> split is like a binary tree (BT) split while the <NUM>:<NUM>/<NUM>:<NUM> split is like an asymmetric binary tree (ABT) split. In ABT splitting, only the small region contains the non-zero residual. If one dimension of a CU is <NUM> in luma samples, the <NUM>:<NUM>/<NUM>:<NUM> split along that dimension is disallowed. There are at most <NUM> SBT modes for a CU.

The Sequence Parameter Set (SPS) level syntax can use syntax element sps_sbt_enabled_flag to specify whether SBT is enabled or disabled. When syntax element sps_sbt_enabled_flag is equal to <NUM>, it signals that SBT for inter-predicted CUs is disabled for the entire video sequence that refers to this SPS. When syntax element sps_sbt_enabled_flag is equal to <NUM>, it signals that SBT for inter-predicted CU is enabled for the entire video sequence that refers to this SPS.

Moreover, when sps_sbt_enabled_flag is equal to <NUM>, another SPS syntax element sps_sbt_max_size_64_flag can be used to specify the maximum CU width and height for which SBT is allowed. When syntax element sps_sbt_max_size_64_flag is equal to <NUM>, it signals that the maximum CU width and height for allowing SBT is <NUM> luma samples. When syntax element sps_sbt_max_size_64_flag is equal to <NUM>, it signals that the maximum CU width and height for allowing SBT is <NUM> luma samples. The variable MaxSbtSize that can specify the maximum allowed CU size for SBT is computed based on the following Equation <NUM>: <MAT> where MaxTbSizeY is the maximum allowed transform block (TB) size and can be derived from another SPS level syntax element, sps_max_luma_transform_size_64_flag, according to the following Equation <NUM>: <MAT>.

As described above, MaxSbtSize derivation depends on the two syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_max_size_64_flag. If the value of syntax element sps_max_luma_transform_size_64_flag = <NUM>, MaxSbtSize is always <NUM>, regardless of the value of syntax element sps_sbt_max_size_64_flag. Therefore, it is not required to signal syntax element sps_sbt_max_size <NUM> flag when syntax element sps_max_luma_transform_size_64_flag is zero. Such syntax redundancy in VVC increases signaling overhead unnecessarily.

To improve the video coding efficiency, according to some disclosed embodiments, syntax element sps_sbt_max_size_64_flag is signaled only when both syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are <NUM>. <FIG> illustrates an exemplary Table <NUM>, according to some embodiments of the present disclosure. Table <NUM> shows an exemplary SPS syntax table of some embodiments. As shown in Table <NUM> (emphases shown in italics), syntax element sps_sbt_max_size_64_flag is signaled only if both syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are <NUM>. If syntax element sps_max_luma_transform_size_64_flag is <NUM>, syntax element sps_sbt_max_size_64_flag can be inferred to be zero-meaning that the maximum CU width and height that allow SBT are <NUM> (in units of luma samples).

<FIG> illustrates a flowchart of an exemplary video processing method <NUM>, according to some embodiments of the present disclosure. In some embodiments, method <NUM> can be performed by an encoder (e.g., encoder <NUM> of <FIG>), decoder (e.g., decoder <NUM> of <FIG>) or one or more software or hardware components of an apparatus (e.g., apparatus <NUM> of <FIG>). For example, a processor (e.g., processor <NUM> of <FIG>) can perform method <NUM>. In some embodiments, method <NUM> can be implemented by a computer program product, embodied in a computer-readable medium, including computer-executable instructions, such as program code, executed by computers (e.g., apparatus <NUM> of <FIG>).

At step <NUM>, method <NUM> can include determining whether a sub-block transform (SBT) is enabled in a Sequence Parameter Set (SPS) of a video sequence. In some embodiments, a flag (e.g., syntax element sps_sbt_enabled_flag as shown in Table <NUM> of <FIG>) can be signaled in the SPS indicating whether the SBT is enabled. For example, syntax element sps_sbt_enabled_flag being equal to <NUM> can specify that SBT for inter-predicted CUs is disabled for the whole video sequence that refers to the SPS. And syntax element sps_sbt_enabled_flag equal to <NUM> can specify that SBT for inter-predicted CUs is enabled for the whole video sequence that refers to the SPS.

At step <NUM>, method <NUM> can include determining a value of a first flag in the SPS indicating a maximum transform block (TB) size that allows the SBT. The first flag can be set to a first vale or a second value. For example, the first value is <NUM> and the second value is <NUM>. The maximum TB size can be <NUM>, <NUM>, or the like. In some embodiments, method <NUM> can also include in response to the maximum TB size being <NUM>, setting the value of the first flag to be the first value, and in response to the maximum TB size being <NUM>, setting the value of the first flag to be the second value. In some embodiments, the first flag can be syntax element sps_max_luma_transform_size_64_flag in Table <NUM> of <FIG>.

At step <NUM>, method <NUM> can include in response to the SBT being enabled and the value of the first flag being equal to a first value, signaling a second flag indicating a maximum coding unit (CU) size that allows the SBT. The second flag is not signaled in response to the SBT being disenabled or the value of the first flag being equal to a second value. For example, the second flag can be syntax element sps_sbt_max_size_64_flag as shown in Table <NUM> of <FIG>. The syntax element sps_sbt_max_size_64_flag is signaled only when both syntax elements sps_max_luma_transform_size_64_flag and sps_sbt_enabled_flag are <NUM>.

In some embodiments, method <NUM> can also include signaling a third flag (e.g., syntax element sps_sbt_enabled_flag as shown in Table <NUM> of <FIG>) in the SPS indicating whether the SBT is enabled and signaling the first flag (e.g., syntax element sps_max_luma_transform_size_64_flag in Table <NUM> of <FIG>) in the SPS.

In some embodiments, the maximum CU size can be <NUM> or <NUM>. A maximum CU width or height that allows SBT can be determined based on a smaller one of the maximum TB size and the maximum CU size (e.g., according to Equation <NUM>).

In some disclosed embodiments, syntax element sps_sbt_max_size_64_flag is not signaled at all. In that case, maximum allowed CU width and height of SBT directly depends on the syntax element sps_max_luma_transform_size_64_flag. If syntax element sps_max_luma_transform_size_64_flag is equal to <NUM>, the maximum CU width and height for allowing SBT are <NUM> luma samples. If syntax element sps_max_luma_transform_size_64_flag is equal to <NUM>, the maximum CU width and height for allowing SBT are <NUM> luma samples. In other words, MaxSbtSize is set equal to MaxTbSizeY. <FIG> illustrates an exemplary Table <NUM>, according to some embodiments of the present disclosure. Table <NUM> shows an exemplary SPS syntax implementing these embodiments. As shown in Table <NUM>, syntax element sps_sbt_max_size_64_flag is not signaled and is deleted from the syntax. <FIG> illustrates an exemplary Table <NUM>, according to some embodiments of the present disclosure. Table <NUM> (emphases shown in italics) shows an exemplary coding unit (CU) syntax table that directly uses MaxTbSizeY to set the maximum CU width and height. MaxTbSizeY is computed based on the following Equation <NUM>: <MAT>.

<FIG> illustrates a flowchart of another exemplary video processing method <NUM>, according to some embodiments of the present disclosure. In some embodiments, method <NUM> can be performed by an encoder (e.g., encoder <NUM> of <FIG>), decoder (e.g., decoder <NUM> of <FIG>) or one or more software or hardware components of an apparatus (e.g., apparatus <NUM> of <FIG>). For example, a processor (e.g., processor <NUM> of <FIG>) can perform method <NUM>. In some embodiments, method <NUM> can be implemented by a computer program product, embodied in a computer-readable medium, including computer-executable instructions, such as program code, executed by computers (e.g., apparatus <NUM> of <FIG>).

At step <NUM>, method <NUM> includes signaling a first flag in a Sequence Parameter Set (SPS) of a video sequence indicating whether a sub-block transform (SBT) is enabled. In some embodiments, the first flag can be syntax element sps_sbt_enabled_flag as shown in Table <NUM> of <FIG>. For example, syntax element sps_sbt_enabled_flag being equal to <NUM> can specify that SBT for inter-predicted CUs is disabled for the whole video sequence that refers to the SPS. And syntax element sps_sbt_enabled_flag equal to <NUM> can specify that SBT for inter-predicted CUs is enabled for the whole video sequence that refers to the SPS.

At step <NUM>, method <NUM> can include signaling a second flag indicating a maximum transform block (TB) size that allows the SBT. The second flag can be set to a first vale or a second value. For example, the first value is <NUM> and the second value is <NUM>. The maximum TB size can be <NUM>, <NUM>, or the like. In some embodiments, method <NUM> can also include in response to the maximum TB size being <NUM>, setting a value of the second flag to be <NUM>, and in response to the maximum TB size being <NUM>, setting a value of the second flag to be <NUM>. In some embodiments, the first flag can be syntax element sps_max_luma_transform_size_64 flag in Table <NUM> of <FIG>.

A maximum CU size that allows the SBT can be determined directly based on the maximum TB size in response to the first flag indicating that the SBT is enabled. For example, the maximum CU size is determined to be equal to the maximum TB size. The maximum CU size can include a maximum CU width and a maximum CU height.

In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and the instructions may be executed by a device (such as the disclosed encoder and decoder), for performing the above-described methods. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM or any other flash memory, NVRAM, a cache, a register, any other memory chip or cartridge, and networked versions of the same. The device may include one or more processors (CPUs), an input/output interface, a network interface, and/or a memory.

It should be noted that, the relational terms herein such as "first" and "second" are used only to differentiate an entity or operation from another entity or operation, and do not require or imply any actual relationship or sequence between these entities or operations. Moreover, the words "comprising," "having," "containing," and "including," and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items.

As used herein, unless specifically stated otherwise, the term "or" encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

It is appreciated that the above described embodiments can be implemented by hardware, or software (program codes), or a combination of hardware and software. If implemented by software, it may be stored in the above-described computer-readable media. The software, when executed by the processor can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, or software, or a combination of hardware and software. One of ordinary skill in the art will also understand that multiple ones of the above described modules/units may be combined as one module/unit, and each of the above described modules/units may be further divided into a plurality of sub-modules/sub-units.

In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.

Claim 1:
A method (<NUM>) of encoding a video sequence into a bitstream, the method comprising:
signaling (<NUM>), in a Sequence Parameter Set, SPS, encoded in a bitstream (<NUM>, <NUM>), a first flag indicating whether a sub-block transform, SBT, is enabled; and
signaling (<NUM>), in the SPS encoded in the bitstream, a second flag indicating a maximum transform size for luma samples,
characterized in that
when the first flag indicates that the SBT is enabled:
a maximum coding unit, CU, size that allows the SBT is set to <NUM> in response to the second flag indicating the maximum transform size for luma samples is <NUM>; and
a maximum coding unit, CU, size that allows the SBT is set to <NUM> in response to the second flag indicating the maximum transform size for luma samples is <NUM>.