Patent Description:
<CIT> discloses the application of tumor treating fields (TTFields) in stopping the proliferation of and destroying living cells that proliferate rapidly (e.g., cancer cells) by choosing the rate at which the field is switched between various directions.

<CIT> discloses the selective destruction of rapidly-dividing cells in a localized area, and particularly the selective destruction of dividing cells without destroying nearby non-dividing cells by applying an electric field with specific characteristics to a target area in a living patient.

This application describes a variety of approaches for generating high voltage sinusoidal signals whose output voltage can be adjusted rapidly, without introducing high-frequency artifacts (e.g., voltage spikes) on the output. When these approaches are used, stronger electric fields can be applied to the tumor for a higher percentage of time, which can increase the efficacy of the TTFields therapy.

One aspect of the invention is directed to an apparatus according to clam <NUM>.

When using the prior art approaches to generate high voltage sinusoidal signals in connection with TTFields therapy, high-frequency artifacts (e.g., voltage spikes) may appear on the output under specific conditions (e.g., in response to a command to change the output voltage, or when the direction of the TTFields is switched). And because those high-frequency artifacts can create an unpleasant sensation in the person being treated with TTFields therapy, the output voltage amplitude was typically ramped-up slowly to prevent those high-frequency artifacts (and the resulting unpleasant sensations) from occurring. But using a slow ramp-up has a downside: the output voltage is not always as high as it could be, which means that the electric field being applied to the tumor is not always as strong as it could be. And when the electric field is not as strong as it could be, the efficacy of treatment can be reduced. The embodiments described herein can advantageously increase the output voltage amplitude much more rapidly, without introducing high-frequency artifacts. These embodiments can therefore prevent unpleasant sensations from occurring without incurring an associated decrease in efficacy of treatment.

The embodiments described herein are useful in connection with generating TTFields, as described in <CIT>. The embodiments described herein build upon the architecture described in <CIT>. Notably, the embodiments described herein enable the voltage of the sinusoidal signals (which are applied to the TTFields transducer arrays) to be adjusted more rapidly, without the risk of introducing high-frequency artifacts (e.g., voltage spikes) on the output. The embodiments described herein also enable the sinusoidal signals to be switched on and off to full power instantaneously, without the risk of introducing high-frequency artifacts on the output.

Note that when generating a high-voltage signal for TTFields delivery, the exact shape of the signal is known at every moment (pure sine wave at a known frequency) and it is only the amplitude of the output signal that changes over time, based on external inputs (e.g., control based on the skin temperature of the patient),.

The embodiments described herein generate high voltage sinusoidal signals by generating a specific pulse train that, when filtered using a specific low pass filter, will result in a low distortion sine wave of the desired amplitude and frequency.

<FIG> is a block diagram of a first example of a sinusoid generator that generates a sinusoid at a pre-set frequency f, with a controllable amplitude. Ultimately, the amplitude of the output sinusoid will be proportional to the output of the DC power source <NUM>, which is preferably a controlled DC-DC converter.

In the illustrated example, the DC to DC converter <NUM> is configured to multiply an analog voltage-control input signal by <NUM>, so when a <NUM> V voltage-control signal is applied the output will be <NUM> V, and when a <NUM> V voltage-control signal is applied the output will be <NUM> V, with proportional control therebetween. The output of the DC-DC converter <NUM> can therefore take any value between <NUM> and <NUM> V, depending on the voltage (e.g., <NUM>-<NUM> V) that is applied to the analog voltage-control input. A controller <NUM> controls the output voltage of the DC-DC converter <NUM> by writing a control word to a digital-to-analog converter (DAC) <NUM>. The DAC <NUM> then generates an analog voltage that is proportional to the control word, and this analog voltage is applied to the voltage-control input of the DC-DC converter <NUM>.

The output of the DC-DC converter <NUM> is routed to the power switcher <NUM>. The power switcher <NUM> has a control input, and depending on the state of the control input, it will route the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in either direction. More specifically, when a first control signal is applied to the control input, the power switcher <NUM> will apply the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in a first direction. When a second control signal is applied to the control input, the power switcher <NUM> will apply the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in a second direction that is opposite to the first direction. When neither the first control signal nor the second control signal is applied to the control input, the power switcher <NUM> will remain off, in which case power from the DC-DC converter <NUM> is not routed to the primary of the transformer <NUM>.

<FIG> includes a block diagram of one preferred approach for implementing the power switcher <NUM> using a set of four electronically controlled switches <NUM>-<NUM> connected to the primary of the transformer <NUM> in an H-bridge configuration. These switches <NUM>-<NUM> open and close in response to signals that are applied to a control input <NUM>. A wide variety of technologies may be used for implementing these switches, as will be appreciated by persons skilled in the relevant arts. For example, the switches <NUM>-<NUM> may be implemented using MOSFET transistors (e.g., BSC109N10NS3 manufactured by Infineon) along with appropriate logic to switch them on and off in response to a control signal. In order to apply the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in the first direction, only switches <NUM> and <NUM> should be closed. In order to apply the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in the opposite direction, only switches <NUM> and <NUM> should be closed. When all four of these switches <NUM>-<NUM> are off, no power is routed into the primary of the transformer <NUM>.

Transformer <NUM> is preferably a step-up transformer with a step-up ratio between <NUM>:<NUM> and <NUM>:<NUM>. In some preferred examples transformer <NUM> is a step-up transformer with a step-up ratio of <NUM>:<NUM>. For example, when a transformer with a <NUM>:<NUM> step-up ratio is used in combination with a DC-DC converter <NUM> that can output up to <NUM> V, the resulting voltage at the secondary of the transformer <NUM> can go as high as <NUM> V.

Returning to <FIG>, the controller <NUM> applies control signals to the control input of the power switcher <NUM> in a time-choreographed sequence in order to construct an oversampled version of a sine wave that is sampled six times per cycle using evenly spaced samples. More specifically, <FIG> depicts a sine wave <NUM> and an oversampled version of that sine wave <NUM> that is sampled at <NUM>°, <NUM>°, <NUM>°, <NUM>°, <NUM>°, <NUM>°, and <NUM>°. Looking at this oversampled version <NUM>, it becomes apparent that it contains only three voltage levels: a positive voltage +V between <NUM>° and <NUM>°, a negative voltage -V between <NUM>° and <NUM>°, and zero volts between <NUM>° and <NUM>° and also between <NUM>° and <NUM>°. Note that the zero Volt level exists because we have chosen the sampling times such that one of the sampling points occurs at <NUM>° and another one of the sampling points occurs at <NUM>°, where the sine function equals zero. This choice advantageously reduces the number of voltage levels that must be generated to construct the oversampled version <NUM> of the sine wave. It also advantageously reduces the number of switching events, which minimizes losses that are incurred during the switching process.

As a result, an oversampled version of a sinusoid at a pre-set frequency f can be constructed at the output of the transformer <NUM> by continuously repeating the following four steps: (a) applying the first control signal to the control input <NUM> for a duration of T/<NUM>, which corresponds to the <NUM>-<NUM>° segment of waveform <NUM> in <FIG>; then (b) waiting for a duration of T/<NUM>, which corresponds to the <NUM>-<NUM>° segment of waveform <NUM>; then (c) applying the second control signal to the control input <NUM> for a duration of T/<NUM>, which corresponds to the <NUM>-<NUM>° segment of waveform <NUM>; and then (d) waiting for a duration of T/<NUM>, which corresponds to the <NUM>-<NUM>° segment of waveform <NUM>. Note that T is the reciprocal of the pre-set frequency f.

The controller <NUM> is responsible for generating these control signals in this sequence. The controller <NUM> may be implemented using a wide variety of approaches that will be apparent to persons skilled in the relevant arts including but not limited to a microcontroller or microprocessor that has been programmed to perform the functions described herein. The controller <NUM> may also be implemented using a microcontroller or microprocessor combined with a hardwired sequencer, the latter of which may be implemented using, for example, a state machine or a counter.

The output of the secondary of the transformer <NUM> is routed to an output filter <NUM> that has a cut-off frequency between 2f and 4f. The output filter <NUM> passes the pre-set frequency f and attenuates frequencies above the cutoff frequency.

Note that when the oversampled version of the sine wave (<NUM> in <FIG>) is converted to the frequency domain, all of the even harmonics will be zero as a result of the fact that waveform <NUM> being symmetric. In addition, because sampling is performed <NUM> times per period, the third harmonic of waveform <NUM> will also be zero.

Many filter designs have inherent instabilities at their cutoff frequencies. But because the third harmonic component of the oversampled waveform <NUM> is zero, the lowest harmonic that will have any significant power will be the fifth harmonic. If the output filter <NUM> is designed so that its cutoff frequency coincides with the third harmonic, the oversampled waveform <NUM> will not be affected by the instabilities in the vicinity of the cutoff frequency, because the waveform contains no power at 3f. It is therefore most preferable to design the output filter <NUM> with its cutoff frequency at 3f, in which case (a) the fundamental component will be far enough below the cutoff frequency so as not to activate the instabilities and (b) the fifth harmonic will be far enough above the cutoff frequency so as not to activate the instabilities.

To further reduce the higher order harmonics, the output filter <NUM> is preferably designed so that the transfer function of the output filter has a zero located at the fifth harmonic. This may be accomplished, for example, by selecting the components within the output filter <NUM> to implement an elliptic low pass filter or a Chebyshev-<NUM> low pass filter. Ordinarily, elliptic filters and Chebyshev-<NUM> filters are not suitable for filtering square waves into sine waves because they have significant ripple in the stop band. As a result, if an incoming signal happens to contain a frequency component that coincides with a crest within that ripple, that component would not be filtered out from the incoming signal. The <FIG> example avoids this situation by generating the oversampled waveform <NUM> at a pre-set frequency, which means that the frequency of the fifth harmonic will be known in advance. By selecting the components within the output filter <NUM> so that its transfer function has a zero at the fifth harmonic, we ensure that the fifth harmonic will never coincide with a crest within the ripple in the stop band.

To reduce the higher harmonics even further, the output filter <NUM> may be designed so that its transfer function has an additional zero located at the seventh harmonic. Here again, because the frequency of the seventh harmonic will be known in advance, the components within the output filter <NUM> can be selected so that its transfer function has a zero at the seventh harmonic.

Designing the output filter <NUM> with zeros at the fifth and seventh harmonics reduces the attenuation at other frequencies located between the harmonics, which would ordinarily be very undesirable. However, because the frequency of the oversampled waveform <NUM> is pre-set in advance and because it only contains signals centered around the odd harmonics (starting with the fifth harmonic), this design will actually decrease the overall distortion of the output signal in the <FIG> example.

When the output filter <NUM> is designed with zeros at the fifth and seventh harmonics, the initial harmonic that will contain any significant power will be the ninth harmonic. But because the power in the ninth harmonic of the oversampled waveform <NUM> (in <FIG>) is relatively low to begin with, and because the ninth harmonic is 6f above the cutoff frequency, the power in the ninth harmonic (and all higher harmonics) at the output <NUM> of the output filter <NUM> will be low enough to produce an excellent sine wave.

<FIG> depicts a suitable architecture for implementing the output filter <NUM> with the cutoff frequency and the zeros at the locations indicated above. Preferably, the output filter <NUM> is a multi-stage low pass LC filter. In this case, the first stage of the output filter <NUM> comprises inductor <NUM> and capacitor <NUM>, and the subsequent stages are represented by block <NUM>. In some examples, the filter <NUM> is a fourth order LC low pass filter. In some examples, the filter <NUM> is a dual M-type element low pass filter.

When the electrical characteristics of transformer <NUM> are modelled, the leakage inductance of the transformer appears in series with the secondary of transformer <NUM>. As a result, this leakage inductance must be accounted for when calculating the inductance of the first inductor <NUM> in the first stage of the output filter <NUM>. In some examples, a transformer <NUM> with a leakage inductance that is large enough to supply all of the inductance that is needed for the first inductor <NUM> is selected. In this case, the first inductor <NUM> can be eliminated entirely from the output filter <NUM> and replaced with a wire. For example, if the calculated desired value for the first inductor in the output filter is <NUM>µH and the leakage inductance of the transformer <NUM> is <NUM>µH, the first inductor <NUM> of the output filter can be eliminated entirely.

In alternative examples, the leakage inductance of the transformer <NUM> accounts for at least half of the inductance of the first stage of the low pass LC filter. In these examples, we start with the calculated value for the first inductor <NUM> and reduce that value by the leakage inductance of the transformer <NUM>. For example, if the calculated value for the first inductor in the first stage of the output filter is <NUM>µH and the leakage inductance of the transformer <NUM> is <NUM>µH, a <NUM>µH inductor should be used as the first inductor <NUM> of the output filter (because <NUM>µH - <NUM>µH = <NUM>µH).

<FIG> is a schematic diagram of an example of the output filter <NUM> in which the inductance of the transformer <NUM> provides all of the inductance that is needed to serve as the first inductor for the first stage of the output filter. The transformer in <FIG> is a Zolotov TRM085, which has the following characteristics: a turn ratio of <NUM>:<NUM>; an inductance of <NUM> mH in the primary (at <NUM>); an inductance of <NUM> mH in the secondary (at <NUM>); and a leakage inductance between <NUM> and <NUM>µH (at <NUM>). The capacitors C33, C35, C36, C42, C43, and C44 are all <NUM> pF capacitors. C40 is a <NUM> nF capacitor. C41 is a <NUM> pF capacitor. The inductor L5-L8 are all <NUM>µH inductors. The values of these components were selected to position the zeros of the filter at the fifth harmonic and the seventh harmonic when the operating frequency is <NUM>.

An alternative design for implementing an output filter <NUM> with an operating frequency of <NUM> can be realized by starting with the schematic of <FIG> and (a) adding an additional <NUM> nF capacitor in parallel with C40; and (b) swapping in <NUM> pF capacitors in place of the <NUM> pF capacitors C33, C35, C36, C42, C43, and C44. These components were selected to position the zeros of the filter at the fifth harmonic and the seventh harmonic when the operating frequency is <NUM>.

The output impedance of the output filter <NUM> is preferably as close as possible to <NUM> ohms. In alternative examples, the output impedance of the output filter <NUM> is between <NUM> and <NUM> ohms. Using an output impedance in this range is appropriate because the current and voltage of the output signal <NUM> can change depending on the load that is presented (i.e., the patient and the transducer arrays in the context of TTFields treatments). But because the output impedance is between <NUM> and <NUM> ohms, even if there is a short circuit on the exit, the current will not surge to dangerous values. In addition, if the impedance of the load suddenly increases (e.g., if an electrode becomes partially disconnected from a patient), then the drop in current will be a lot less significant. This is very useful as a safety feature in the context of TTFields treatment.

The controller <NUM> controls the amplitude of the output signal <NUM> by adjusting the control signal that is applied to the voltage control input of the DC-DC converter <NUM>. In the illustrated example, this is accomplished by having the controller <NUM> write a control word to the DAC <NUM>. The DAC <NUM> responds by outputting an analog voltage, which serves as the control signal that is applied to the voltage-control input of the DC-DC converter <NUM>. Assume, for example, that the output of the DAC <NUM> starts at <NUM> V, that the DC-DC converter is outputting <NUM> VDC, and that the transformer <NUM> has a step-up ratio of <NUM>:<NUM>. Under these conditions, the pulses at the output of the secondary of the transformer <NUM> will be <NUM> V. When the controller <NUM> writes a new control word to the DAC <NUM> that causes the output of the DAC <NUM> to increase to <NUM> V. The DC-DC converter <NUM> will respond to the new signal that is being applied to its voltage-control input by increasing its output voltage to <NUM> V DC, which (after passing through the step up transformer <NUM>) will cause the pulses at the output of the secondary of the transformer <NUM> to increase to <NUM> V.

Preferably, the voltage and/or current of the output signal <NUM> are monitored by a voltage sense circuit <NUM> and/or a current sense circuit <NUM>. The output of these circuits <NUM>, <NUM> is preferably fed back to the controller <NUM>, and the controller <NUM> is preferably configured so that when and error condition is detected at the output <NUM> (e.g., overvoltage, overcurrent, severe voltage drop, etc.), the controller <NUM> will shut down the power switcher <NUM> by inhibiting the generation of both the first control signal and the second control signal that are applied to the control input <NUM> of the power switcher <NUM>. Optionally, shut down of the power switcher <NUM> may also be triggered by an over-temperature condition at the load by including appropriate temperature sensors and routing a signal back from those temperature sensors to the controller <NUM>.

Note that in the illustrated example, a single controller <NUM> is used to implement all the control functions and sequencing functions described herein. But in alternative examples, a programmable controller <NUM> may be combined with a hardwired sequencer to perform those two functions, respectively.

In some examples, the output of the current sense circuit <NUM> and or the voltage sense circuit <NUM> is fed back to the controller <NUM>. In these examples, the controller can adjust the voltage at the output of the DC-DC converter <NUM> by writing appropriate control words to the DAC <NUM> in order to adjust the current or voltage of the output signal <NUM> to a desired level. For example, when the controller <NUM> is set to adjust the current to a particular level and the output of the current sense circuit <NUM> indicate that the current is too low, the controller can increase the voltage at the output of the DAC <NUM>, which will cause an increase in amplitude at the output signal <NUM>. Similarly, if the output of the current sense circuit <NUM> indicate that the current is too high, the controller can decrease the voltage at the output of the DAC <NUM>, which will cause a corresponding decrease in amplitude at the output signal <NUM>.

In alternative examples, the transformer <NUM> (shown in <FIG> and <FIG>) can be omitted, in which case the two conductors at the output of the power switcher <NUM> are hooked up directly to the two conductors at the input of the output filter <NUM>. In these examples, current flows directly from the output of the power switcher <NUM> to the input of the output filter <NUM> with no intervening transformer. But these alternative examples are less preferred, especially in situations when isolation is desirable and in situations where a high voltage output is desirable. In addition, these alternative examples cannot rely on the leakage inductance of the transformer to provide some or all of the inductance needed for the first stage of the filter.

Note that the design of the <FIG> example relies on advance knowledge of the incoming signal, and the intentional construction of both the signal and the output filter <NUM> so that the most significant harmonics are either inherently zero (e.g., the even harmonics and the third harmonic) or zeroed out by the output filter <NUM> (e.g., the fifth and seventh harmonics). This helps provide a very clean high voltage output signal at the desired frequency, with very high efficiency.

The <FIG> example uses a single DC-DC converter <NUM>, and implements six equally-spaced sampling points per cycle. In alternative examples, the number of sampling points may be increased to N=<NUM>+4n, where n is a positive integer. When n=<NUM>, we have the situation described above in connection with <FIG>. When n=<NUM>, we have the situation described below in connection with <FIG>, which uses two DC-DC converters. Other examples may be implemented for n > <NUM> following the same framework using additional DC-DC converters and even more samples (following the rule that N=<NUM>+4n).

<FIG> is a block diagram of a second example of a sinusoid generator that generates a sinusoid at a pre-set frequency f, with controllable amplitude, in which n=<NUM>. As a result, there are two DC-DC converters <NUM>, 50B and (following the formula N=<NUM>+4n) <NUM> samples per cycle are used. Note that in the <FIG> example, components with similar reference numbers operate in a manner similar to the description above in connection with the <FIG> example.

<FIG> depicts a sine wave <NUM> and an oversampled version of that sine wave <NUM> that is sampled <NUM> times per cycle (i.e., at <NUM>°, <NUM>°, <NUM>°,. <NUM>°, and <NUM>°). Looking at this oversampled version <NUM>, it becomes apparent that it contains only five voltage levels: a low positive voltage +V1, a higher positive voltage +V2, a low negative voltage -V1, a higher negative voltage -V2, and zero volts (between <NUM>° and <NUM>° and also between <NUM>° and <NUM>°). Here again, the zero Volt level exists because we have chosen the sampling times such that one of the sampling points occurs at <NUM>° and another one of the sampling points occurs at <NUM>°, where the sine function equals zero. This choice advantageously reduces the number of voltage levels that must be generated to construct the oversampled version <NUM> of the sine wave to two levels (i.e., V1 and V2).

As a result, a controller 40B can be used to control the generation of an oversampled version of a sine wave that is sampled N times per cycle using evenly spaced samples that include a sampling point at <NUM>°, where N=<NUM>+4n, by setting the output voltages of the DC power sources to levels that are present on the oversampled version of the sine wave, and then sequencing the control signal through the 2n states and the additional off state, so that each of the DC power sources is applied to the primary of the transformer in each direction at appropriate times in a sequence so as to generate the oversampled version of the sine wave.

When n=<NUM> (as it is in the <FIG> example), an oversampled version of a sinusoid at a pre-set frequency f can be constructed at the output of the transformer <NUM> by continuously repeating the following eight steps: applying V1 to the primary of the transformer <NUM> in the first direction between <NUM>° and <NUM>°; applying V2 in the first direction between <NUM>° and <NUM>°; applying V1 in the first direction between <NUM>° and <NUM>°; remaining off between <NUM>° and <NUM>°; applying V1 in the second direction between <NUM>° and <NUM>°; applying V2 in the second direction between <NUM>° and <NUM>°; applying V1 in the second direction between <NUM>° and <NUM>°; and remaining off between <NUM>° and <NUM>°. Note that in order for the resulting waveform to properly track an oversampled version of a sinusoid (<NUM> in <FIG>), the ratio between V1 and V2 must remain constant. More specifically, the ratio V2/V1 must equal sin(<NUM>°) / sin(<NUM>°), which comes to <NUM>.

The controller 40B is responsible for generating control signals that cause the power switcher 60B to apply these voltages to the transformer <NUM> in the sequence identified above. The controller 40B is similar to the controller <NUM> in the <FIG> example, except that it sequences through <NUM> states per cycle instead of six states per cycle.

Referring now to <FIG>, the power switch 60B has a control input <NUM>, and the power switch is configured to either (a) apply the output of a selected one of the DC power sources to the primary of the transformer <NUM> in a selected direction in response to 2n states of a control signal that is applied to the control input <NUM> or (b) remain off in response to an additional state of the control signal.

<FIG> is a block diagram of one preferred approach for implementing the power switcher 60B. This power switcher is similar to the power switcher <NUM> of the <FIG> example, except that it contains additional switches <NUM>-<NUM> for switching the output of the second DC-DC converter across the transformer <NUM> in either direction. More specifically, this power switcher 60B uses a set of six electronically controlled switches <NUM>-<NUM> connected to the primary of the transformer <NUM> as depicted in <FIG>. These switches <NUM>-<NUM> (which are similar to the corresponding switches in the <FIG> example) open and close in response to signals that are applied to a control input <NUM>. In order to route the output of the first DC-DC converter <NUM> to the primary of the transformer <NUM> in the first direction, only switches <NUM> and <NUM> should be closed. In order to route the output of the first DC-DC converter <NUM> to the primary of the transformer <NUM> in the opposite direction (i.e., with an opposite polarity), only switches <NUM> and <NUM> should be closed. In order to route the output of the second DC-DC converter 50B to the primary of the transformer <NUM> in the first direction, only switches <NUM> and <NUM> should be closed. In order to route the output of the second DC-DC converter 50B to the primary of the transformer <NUM> in the opposite direction (i.e., with an opposite polarity), only switches <NUM> and <NUM> should be closed. When all six of these switches <NUM>-<NUM> are off, no power is routed into the primary of the transformer <NUM>.

Returning to <FIG>, an output filter 80B is connected to the secondary of the transformer <NUM>, and the output filter passes the pre-set frequency f and attenuates frequencies above a cut-off frequency. The output filter 80B is similar to the output filter <NUM> in the <FIG> example, except the location of the zeros in the transfer function of the output filter 80B must be adjusted to account for the different frequency content of the oversampled waveform <NUM> (shown in <FIG>). More specifically, the output filter 80B should have a transfer function with a zero at a frequency where a harmonic of the pre-set frequency f is expected to contain power.

For example, because the waveform <NUM> has <NUM> samples per cycle, the initial harmonic that we would expect to appear will be the ninth harmonic. Accordingly, a transfer function with a zero at the ninth harmonic would be useful when this waveform <NUM> is being used. The cut off frequency of the filter should also be adjusted accordingly, based on the set of harmonics that are expected to appear (which can be calculated in advance by taking the Fourier transform of the waveform that is being used).

Optionally, the transfer function of the output filter 80B can also be designed to have a zero at the next frequency where a harmonic of the pre-set frequency f is expected to contain power. In the case of the waveform <NUM>, this would be the eleventh harmonic.

The controller 40B controls an amplitude of the sinusoid at the output 100B of the output filter 80B by adjusting the output voltages of the DC power sources <NUM>, 50B via their voltage-control inputs, while maintaining a fixed ratio between the output voltages of each of the DC power sources. In the illustrated example, this is accomplished by writing appropriate control words to DAC <NUM> and DAC 42B, taking care to maintain the required ratio of sin(<NUM>°) / sin(<NUM>°) as described above. In alternative examples, the second DAC 42B can be eliminated, and replaced by a <NUM>. 618x hardware multiplier that is inserted between the output of DAC <NUM> and the voltage control input to the second DC-DC converter 50B.

In alternative examples, the transformer <NUM> can be omitted from the <FIG> example, in which case the two conductors at the output of the power switcher 60B are hooked up directly to the two conductors at the input of the output filter 80B. In these examples, current flows directly from the output of the power switcher 60B to the input of the output filter 80B with no intervening transformer. But these embodiments are less preferred for the same reasons discussed above in connection with <FIG>.

Note that the system descried above is suitable for generating high voltage signals of any shape, as long as the pulse train that will result in these signals can be determined before use either through calculations or experiments, and the filters are designed accordingly.

When the output signal generated by the system is applied to electrodes to generate TTFields (as described in <CIT>) changes in the load associated with the body of the patient and the transducer arrays can change the output signal due to interactions with the output filter. This means that any changes to this load (e.g., lifting of a disk off a patient's body, short circuiting etc.) immediately influence the output signal, which is constantly monitored. Hence, it is possible for the device to respond very quickly to these changes (e.g., by shutting down the power switcher <NUM> in response to the detection of a short circuit or overload condition).

Notably, in the examples described above, the exact shape of the desired output signal is known in advance at every moment because we are generating a sine wave at a known frequency. It is only the amplitude of the output signal that changes over time based on the controller responding to external inputs (e.g., current measurements or temperature measurements). The examples described above can advantageously be used to generate very clean narrow band limited signals in the frequency range of <NUM>-<NUM>, with very low losses and very low sensitivity to the external load to which the signal generator is connected.

In alternative examples, the system can be used to generate a sinusoid at any desired frequency within a pre-set range by building the filter using a component with a tunable reactance (e.g. a tunable capacitance or a tunable inductance). In these examples, the reactance of the tunable components is set to imbue the filter with the desired transfer function characteristics. Then, an appropriate oversampled sinusoid is generated and fed into the filter as discussed above in connection with <FIG> and <FIG>.

In other alternative examples, the system can be used to generate a finite number of pre-defined signals at a plurality of different pre-set frequencies. These examples can be implemented by saving the characteristics of the pulse trains for each of the pre-defined signals in a look up table, and providing a bank of filters that can be selectively switched in to the signal path so as to provide the filtering characteristics necessary to generate the desired one of the pre-defined signals. When using the system to generate one of the pre-defined signals, the characteristics of the required pulse train are retrieved from memory and the appropriate filter (i.e., the one that matches this pulse train) is switched in to the signal path.

In other alternative examples, composite signals that contain a small number of discrete frequencies (e.g., between two and five frequencies) can be generated by generating an oversampled version of the composite signal, and passing the oversampled version of the composite signal through an appropriate filter.

In the <FIG> and <FIG> examples described above, depending on the construction of the DC-DC converters <NUM>/50B, the possibility exists that high-frequency artifacts (e.g., spikes) may appear on the output <NUM>/100B when the output voltage of those DC-DC converters changes (e.g., when the controller <NUM>/40B writes a new control word to the DAC <NUM>/42B). And because high-frequency artifacts can create an unpleasant sensation in the person being treated with TTFields therapy, it is preferable to take steps to prevent such high-frequency artifacts.

One suitable approach that prevents high-frequency artifacts from appearing on the output <NUM>/100B is to deliberately slow down the response time of the DC-DC converters <NUM>/50B (e.g., by adding a sufficiently large capacitor across the output of each DC-DC converter). But while this approach is effective, it has two drawbacks: first, additional components must be included in the circuit. And second, slowing down the response time of the system will prevent the output voltage from changing rapidly in situations when rapid changes may be desirable.

<FIG> depict an alternative approach for preventing high-frequency artifacts from appearing on the output <NUM>/100B without deliberately slowing down the response time of the DC-DC converters <NUM>/50B.

More specifically, <FIG> depicts the same waveform <NUM> described above in connection with <FIG> (which appears at the output of the power switcher <NUM> in <FIG>) and the sinusoidal output waveform <NUM> (which appears at the output <NUM> of the output filter <NUM> in <FIG>) under steady-state conditions (e.g., when the voltage at the output of the DC-DC converter <NUM> in <FIG> is held at a constant <NUM> VDC, which means that the controller <NUM> in <FIG> is not updating the contents of the DAC <NUM>). In this steady-state situation, the output waveform <NUM> will operate as described above in connection with <FIG>, and will not include any high frequency artifacts.

<FIG> shows how things change when a DC-DC converter with a rapid response time is used, and the output of the DC-DC converter <NUM> (shown in <FIG>) changes from <NUM> VDC to <NUM> VDC. As explained above in connection with <FIG>, the controller <NUM> could initiate this change by updating the contents of the DAC <NUM> at time t9. Prior to this time t9, the output waveform <NUM> will be identical to the output waveform <NUM> in the <FIG> example. But as soon as the controller <NUM> updates the contents of the DAC <NUM> at time t9, because the output of the DAC <NUM> is applied to the voltage-control input of the DC-DC converter <NUM>, the output voltage of the DC-DC converter will rapidly begin to change (e.g., from <NUM> V to <NUM> V in the illustrated example). And because the power switch <NUM> is set to actively source current from the DC-DC converter <NUM> into the transformer <NUM> at that instant t9, the rapid change in current will travel through the transformer <NUM> and into the output filter <NUM>, which will add a high-frequency artifact <NUM> to the output <NUM>. (Note that the dashed line <NUM> represents a continuation of the original sinusoid that existed prior to t9, and the dashed line <NUM> represents a clean sinusoid at twice the original amplitude.

A similar situation exists when the design of the DC-DC converter is such that spikes and/or instabilities can appear on the output of the DC-DC converter in response to changes on the DC-DC converter's voltage-control input (regardless of the response time of the DC-DC converter). More specifically, if the power switch <NUM> is set to actively source current from the DC-DC converter <NUM> into the transformer <NUM> at the instant the voltage-control input of the DC-DC converter changes, any spikes on the output of the DC-DC converter will travel through the transformer <NUM> and into the output filter <NUM>, which will add high-frequency artifacts <NUM> to the output <NUM>.

Under certain circumstances, high-frequency artifacts could be added to the output <NUM> if the output voltage of the DC-DC converter changes during an interval of time when the power switch <NUM> is set to actively source current from a DC-DC converter <NUM>/50B into the transformer <NUM>. If, on the other hand, the output of the DC-DC converter is changed during an interval of time when the power switch <NUM> is not actively sourcing current from a DC-DC converter <NUM>/50B into the transformer <NUM>, high-frequency artifacts will not appear at the output <NUM>. The controller <NUM>/40B in the FIG. <NUM>/<NUM> examples can take advantage of this dichotomy to prevent high-frequency artifacts from appearing on the output <NUM>/100B. More specifically, the controller <NUM>/40B does this by ensuring that the output of the DC-DC converter <NUM>/50B is only changed during intervals when the power switcher <NUM>/60B is not actively sourcing current from a DC-DC converter.

In the context of the <FIG> example described above, the controller <NUM> accomplishes this by preventing adjustments of the voltage-control input of the DC-DC converter <NUM> from occurring when either (a) the first control signal is being applied to the control input of the power switcher <NUM> (i.e., when the power switcher <NUM> is routing the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in one direction) or (b) the second control signal is being applied to the control input of the power switcher <NUM> (i.e., when the power switcher <NUM> is routing the output of the DC-DC converter <NUM> to the primary of the transformer <NUM> in the opposite direction). When neither the first control signal nor the second control signal is being applied to the control input, the power switcher <NUM> will remain off, in which case the controller <NUM> can make adjustments to the voltage-control input of the DC-DC converter <NUM> without introducing a high-frequency artifact on the output <NUM>.

<FIG> shows how things unfold in the context of the <FIG> example when the output of the DC-DC converter <NUM> changes from <NUM> VDC to <NUM> VDC during a time <NUM> when the power switch <NUM> is not actively sourcing current from the DC-DC converter. Prior to this time t10, the output of the DC-DC converter <NUM> will be at a first level (e.g., <NUM> V in the illustrated example), and the output waveform <NUM> will be identical to the output waveform <NUM> in the <FIG> example. The controller <NUM> updates the contents of the DAC <NUM> at time t10, when the power switch <NUM> is not actively sourcing current from the DC-DC converter <NUM> into the transformer <NUM>. The output voltage of the DC-DC converter <NUM> will rapidly begin to change (e.g., from <NUM> V to <NUM> V in the illustrated example) and will stabilize before the power switch <NUM> begins to route current into the transformer <NUM> at t11. Because the output of the DC-DC converter <NUM> has already stabilized when the power switch <NUM> begins to route current into the transformer <NUM> at t11, the waveform that will enter the output filter after t11 will be an oversampled sine wave with a different amplitude (e.g., <NUM> V). And as explained above in connection with <FIG>, when an oversampled sine wave is provided to the output filter <NUM>, the resulting output <NUM> will be a very clean sinusoid.

Similarly, in the context of the <FIG> example described above, the controller 40B prevents high-frequency artifacts from appearing on the output 100B by ensuring that the output of any given DC-DC converter <NUM>/50B is only changed during intervals when the power switch <NUM> is not actively sourcing current from the given DC-DC converter. The controller 40B accomplishes this by not adjusting the output voltage of any DC power source while its output is being routed to the output terminals of the power switcher <NUM>.

<FIG> is a block diagram of a third example of a sinusoid generator that generates a sinusoid at a pre-set frequency f, with controllable amplitude. Components with similar reference numbers operate in a manner similar to the corresponding components described above in connection with <FIG>.

This example uses two DC-DC converters <NUM>, <NUM>. Each of these DC-DC converters is configured to multiply an analog voltage-control input signal by a fixed number (e.g., <NUM>). In this example, when a <NUM> V voltage-control signal is applied the output will be <NUM> V, and when a <NUM> V voltage-control signal is applied the output will be <NUM> V, with proportional control therebetween. The output of the DC-DC converters <NUM>, <NUM> can therefore take any value between <NUM> and <NUM> V, depending on the voltage (e.g., <NUM>-<NUM> V) that is applied to the analog voltage-control input. The controller 40C controls the output voltage of the DC-DC converters <NUM>, <NUM> by writing control words to the DACs <NUM>, 42B. The DACs then generate analog voltages that are proportional to the control words, and these analog voltages are applied to the voltage-control inputs of the DC-DC converters <NUM>, <NUM>.

The controller 40C is responsible for generating control signals that cause the power switcher 60B to apply these voltages to the transformer <NUM> in the sequence described below.

<FIG> is a block diagram of one preferred approach for implementing the power switcher 60B. This power switcher is identical to the power switcher 60B of the <FIG> example. More specifically, this power switcher 60B uses a set of six electronically controlled switches <NUM>-<NUM> connected to the primary of the transformer <NUM> as depicted in <FIG>. These switches <NUM>-<NUM> open and close in response to signals that are applied to a control input <NUM>.

In order to route the output of the first DC-DC converter <NUM> to the primary of the transformer <NUM> in the first direction, only switches <NUM> and <NUM> should be closed. The power switcher 60B is configured so that this occurs in response to a first state of the control input. In order to route the output of the first DC-DC converter <NUM> to the primary of the transformer <NUM> in the opposite direction (i.e., with an opposite polarity), only switches <NUM> and <NUM> should be closed. The power switcher 60B is configured so that this occurs in response to a second state of the control input.

In order to route the output of the second DC-DC converter <NUM> to the primary of the transformer <NUM> in the first direction, only switches <NUM> and <NUM> should be closed. The power switcher 60B is configured so that this occurs in response to a third state of the control input. In order to route the output of the second DC-DC converter <NUM> to the primary of the transformer <NUM> in the opposite direction (i.e., with an opposite polarity), only switches <NUM> and <NUM> should be closed. The power switcher 60B is configured so that this occurs in response to a fourth state of the control input. When all six of these switches <NUM>-<NUM> are off, no power is routed into the primary of the transformer <NUM>. The power switcher 60B is configured so that this occurs in response to a fifth state of the control input (also referred to herein as an additional state).

The controller 40C has the ability to operate in either a first mode or a second mode. In the first mode, the controller 40C generates an output waveform 100C powered exclusively from the first DC-DC converter <NUM> by setting the control input of the power switcher 60B to the first and second states in an alternating sequence while holding the first voltage-control input constant. In some preferred examples, a waveform similar to the waveform <NUM> in <FIG> can be generated by (a) placing the control input in the first state for a duration of T/<NUM>, then (b) waiting for a duration of T/<NUM>, then (c) placing the control input in the second state for a duration of T/<NUM>, and then (d) waiting for a duration of T/<NUM>, then continuously repeating the sequence (a), (b), (c), and (d). The amplitude of this waveform will depend only on the output voltage of the DC-DC converter <NUM>, Filtering of this waveform by the output filter <NUM> (which is identical to the output filter <NUM> in the <FIG> example) will result in a clean sinusoid (as explained above in connection with <FIG>).

In the second mode, the controller 40C generates an output waveform 100C powered exclusively from the second DC-DC converter <NUM> by setting the control input of the power switcher 60B to the third and fourth states in an alternating sequence while holding the second voltage-control input constant. In some preferred examples, a waveform similar to the waveform <NUM> in <FIG> can be generated by (e) placing the control input in the third state for a duration of T/<NUM>, then (f) waiting for a duration of T/<NUM>, then (g) placing the control input in the fourth state for a duration of T/<NUM>, and then (h) waiting for a duration of T/<NUM>, then continuously repeating the sequence (e), (f), (g), and (h). The amplitude of this waveform will depend only on the output voltage of the DC-DC converter <NUM>, Filtering of this waveform by the output filter <NUM> will result in a clean sinusoid.

<FIG> illustrates how the <FIG> example facilitates rapid changes to the voltage of the output signal 100C by switching between the first and second modes. Trace <NUM> is the output voltage of the first DC-DC converter <NUM>, trace <NUM> is the output voltage of the second DC-DC converter <NUM>, and trace <NUM> is the output signal. <FIG> begins at t0, with the controller 40C operating in the first mode. In this mode, the output waveform <NUM> is powered exclusively from the first DC-DC converter <NUM> (which is set to <NUM> V in the illustrated example). The controller 40C controls generation of the output waveform <NUM> by setting the control input of the power switcher 60B to the first and second states in an alternating sequence (with wait times interspersed at appropriate times) while holding the first voltage-control input constant, as described above.

While still operating in the first mode, the controller 40C determines in advance what the output voltage will be when it eventually switches into the second mode. The controller 40C then issues a command at time t1, which causes the output voltage of the second DC-DC converter <NUM> to move to the desired level. In the illustrated example, the desired level for the second DC-DC converter <NUM> is <NUM> V. Notably, the reaction time of the second DC-DC converter can be very slow because the second DC-DC converter is not being used at this time.

Preferably after the output of the second DC-DC converter <NUM> has settled to the desired level, the controller 40C switches into the second mode. This transition from the first mode to the second mode occurs at a time when the power switcher 60B is in the fifth state and is not routing current to the transformer <NUM>. In the second mode, the output waveform <NUM> is powered exclusively from the second DC-DC converter <NUM> (which is set to <NUM> V in the illustrated example). The controller 40C controls generation of the output waveform <NUM> by setting the control input of the power switcher 60B to the third and fourth states in an alternating sequence (with wait times interspersed at appropriate times) while holding the second voltage-control input constant, as described above. Preferably, the command that initiates the change in voltage of the second DC-DC converter <NUM> (i.e., t1 in <FIG>) occurs far enough in advance (e.g., at least <NUM>) before the controller 40C switches into the second mode (i.e., t2 in <FIG>) to allow the output of the second DC-DC converter <NUM> to settle at the desired level, so that when the second mode begins at t2 the output waveform <NUM> will immediately go to the desired level.

A similar process occurs when transitioning from the second mode back to the first mode. More specifically, while still operating in the second mode, the controller 40C determines in advance what the output voltage will be when it eventually switches into the first mode. The controller 40C then issues a command at time t3, which causes the output voltage of the first DC-DC converter <NUM> to move to the desired level. In the illustrated example, the new desired level for the first DC-DC converter <NUM> is <NUM> V. Notably, the reaction time of the first DC-DC converter can be very slow because the first DC-DC converter is not being used at this time.

Preferably after the output of the first DC-DC converter <NUM> has settled to the desired level, the controller 40C switches into the first mode. This transition from the second mode to the first mode occurs at a time when the power switcher 60B is in the fifth state and is not routing current to the transformer <NUM>. In the first mode, the output waveform <NUM> is powered exclusively from the first DC-DC converter <NUM> (which is set to <NUM> V in the illustrated example). The controller 40C controls generation of the output waveform <NUM> by setting the control input of the power switcher 60B to the first and second states in an alternating sequence (with wait times interspersed at appropriate times) while holding the first voltage-control input constant, as described above. Preferably, the command that initiates the change in voltage of the first DC-DC converter <NUM> (i.e., t3 in <FIG>) occurs far enough in advance (e.g., at least <NUM>) before the controller 40C switches into the first mode (i.e., t4 in <FIG>) to allow the output of the first DC-DC converter <NUM> to settle at the desired level, so that when the first mode begins at t4 the output waveform <NUM> will immediately go to the desired level.

In alternative examples, the transformer <NUM> can be omitted from the <FIG> example, in which case the two conductors at the output of the power switcher 60B are hooked up directly to the two conductors at the input of the output filter <NUM>. In these embodiments, current flows directly from the output of the power switcher 60B to the input of the output filter <NUM> with no intervening transformer. But these examples are less preferred for the same reasons discussed above in connection with <FIG>.

TTFields therapy involves inducing an electric field (e.g., at <NUM>) through a target body part in order to treat a tumor in that body part. Experiments have shown, that the efficacy of TTFields increases when the direction of the TTFields changes during the course of treatment. For example, in the Optune® prior art system, the direction of the TTFields changes every <NUM>. But in alternative embodiments, the direction can change at a different rate (e.g., between <NUM> and <NUM>).

<FIG> is a block diagram of the original Optune® prior art system for applying TTFields to a person's head (or other body part) in two different directions. This is accomplished using one pair of transducer arrays 25A, 25P positioned on the front and back of the head (i.e., anterior and posterior; and another pair of transducer arrays <NUM>, 25R positioned on the left and right sides of the person's head. More specifically, when an AC voltage is applied between transducer arrays <NUM> and 25R, an electric field that primarily runs in a left-to-right (LR) direction will be induced in the subject's head. And when an AC voltage is applied between transducer arrays 25A and 25P, an electric field that primarily runs in a anterior-to-posterior (AP) direction will be induced in the subject's head. TTFields may also be applied to other parts of the body (e.g., pancreas, lungs, etc.) by positioning transducer arrays of the subject' skin in front/back of the relevant body part and right/left of the relevant body part.

In the <FIG> example, a single AC voltage generator <NUM> is used to drive both transducer array pairs (i.e., <NUM>/R and 25A/P). This is accomplished by routing the output of the AC voltage generator <NUM> into a switch <NUM>. Depending on the state of the control signal, the switch <NUM> will either route the signal from the AC voltage generator <NUM> across one pair of transducer arrays (i.e. <NUM>/R) or the other pair of transducer arrays (i.e. 25A/P).

<FIG> is a timing diagram that shows the sequencing between the two directions LR and AP that was used in the original Optune®. In this approach, the switch <NUM> would (a) route the output of the AC voltage generator <NUM> to the left and right transducer arrays (<NUM>/R) for one second, then (b) route the output of the AC voltage generator <NUM> to the anterior and posterior transducer arrays (25A/P) for one second, and then repeat steps (a) and (b) in an alternating sequence. A short duration of time (e.g., <NUM>-<NUM>) during which the output of the AC voltage generator <NUM> was not routed to either pair of transducer arrays (<NUM>/R, 25A/P) was interposed between each step (indicated by the label OFF).

One issue that was addressed during the design of the original Optune® is explained in connection with <FIG>. More specifically, if the switch <NUM> switched from the OFF state to either the LR state or the AP state (trace <NUM>) while the instantaneous output voltage <NUM> generated by the AC voltage generator <NUM> was substantial (e.g., > <NUM> V), the output waveform would resemble trace <NUM>, which includes a spike <NUM>. Because such a spike <NUM> could cause the subject to experience an uncomfortable sensation, the original Optune® was designed to prevent such spikes from occurring. More specifically, this was accomplished by ramping down the output voltage of the AC voltage generator <NUM> from its steady-state value to zero V during the <NUM> interval that preceded each OFF state, then ramping the output voltage back up to its steady-state value during the <NUM> interval that followed each OFF state, as depicted in <FIG>, trace <NUM>. The ramp rate was about <NUM> V/ms, which was sufficiently slow to avoid spikes that might be noticeable to a patient.

The resulting waveform at the output of the AC voltage generator <NUM> resembled the waveform depicted in <FIG> (except that the actual frequency of the sinusoid generated by the AC voltage generator <NUM> would be orders of magnitude higher than the depicted sinusoid). Note that the scale of the x-axis in <FIG> is magnified <NUM>× with respect to <FIG>, in order to show additional detail. And this solution worked quite well in the context of the original Optune®, because the system operated at its peak output voltage <NUM>% of the time, and only <NUM>% of the time was spent either ramping up the voltage, ramping down the voltage, or with the voltage switched off.

Let us now examine what would happen if a similar approach is used, but the interval that the AC voltage is applied to either the LR or AP transducer arrays is reduced from <NUM> to <NUM>. If the same <NUM> V/ms ramp-down and ramp-up approach described above in connection with <FIG> is used at this new timescale, the output voltage of the AC voltage generator <NUM> would follow trace <NUM> in <FIG>. And as a result, the waveform at the output of the AC voltage generator <NUM> would resemble the waveform depicted in <FIG> (except that, once again, the actual frequency of the sinusoid generated by the AC voltage generator <NUM> would be orders of magnitude higher than the depicted sinusoid). Note that the scale of the x-axis in <FIG> is magnified <NUM>× with respect to <FIG>, in order to show additional detail.

But this solution is less than ideal because the peak output voltage would only be applied to the transducer arrays <NUM>% of the time, which means that the maximum electric field would only be applied to the subject <NUM>% of the time. Thus, unlike the prior art situation depicted in <FIG>/B (in which the output voltage was ramped up/down to ensure patient comfort, and the ramping only reduced the percentage of time spent at the peak voltage by a small amount), using the same ramping slope when the switching time is shortened to <NUM> will reduce the percentage of time spent at the peak voltage by a very significant amount (as depicted in <FIG> A/B). Moreover, the situation would be even worse if the interval that the AC voltage is applied to either the LR or AP transducer arrays is reduced below <NUM>, in which case the peak voltage (and corresponding peak field strength) would never be reached.

The <FIG> embodiment uses a different approach for avoiding spikes that resemble the spike <NUM> depicted in <FIG>. More specifically, the <FIG> embodiment has an AC voltage generator <NUM> and a switch <NUM>, and synchronization between those two functional blocks is relied on to avoid spikes, as described below in connection with <FIG>. In some preferred embodiments, the AC voltage generator <NUM> in <FIG> is implemented using the approaches described above in connection with <FIG>. The switch <NUM> is configured to either (a) route the output of the AC voltage generator <NUM> to the left and right transducer arrays (<NUM>/R) in response to a first state of its control input; (b) route the output of the AC voltage generator <NUM> to the anterior and posterior transducer arrays (25A/P) in response to a second state of its control input; or (c) remain off in response to a third state of its control input. The switch <NUM> may be implemented using any of a variety of approaches that will be apparent to persons skilled in the relevant arts, including but not limited to field effect transistors, solid-state relays, etc..

In the illustrated embodiment, synchronization between the AC voltage generator <NUM> and the switch <NUM> is implemented using a synchronization controller <NUM> that is programmed to send control signals to the AC voltage generator <NUM> and/or the switch <NUM>, to orchestrate those components so that the signals described below are generated with the time relationships described below. A variety of alternative approaches for synchronizing the AC voltage generator <NUM> and the switch <NUM> may be used. For example, synchronization may be achieved by allowing the AC voltage generator <NUM> to run freely and adjusting the switching time of the switch <NUM> (as described below in connection with <FIG>). Alternatively, synchronization may be achieved by allowing the switch <NUM> to switch automatically, and turning off the AC voltage generator <NUM> prior to each switching event (as described below in connection with <FIG>). Yet another alternative for achieving synchronization is to control the timing of both the AC voltage generator <NUM> and the switch <NUM>.

<FIG> is a timing diagram that shows the sequencing between the two directions LR and AP for the <FIG> embodiment. In this embodiment, the switch <NUM> (a) routes the output of the AC voltage generator <NUM> to the left and right transducer arrays (<NUM>/R) for a duration T, then (b) routes the output of the AC voltage generator <NUM> to the anterior and posterior transducer arrays (25A/P) for a duration T, and then repeat steps (a) and (b) in an alternating sequence. A short duration of time (e.g., <NUM>-<NUM>) during which the output of the AC voltage generator <NUM> is not routed to either pair of transducer arrays is interposed between each step (indicated by the label OFF). This may be choreographed by repeatedly adjusting a control input of the switch <NUM> to cycle through the LR mode, the AP mode, and the OFF mode in the following repeating sequence (<NUM>) LR mode, (<NUM>) OFF mode, (<NUM>) AP mode, and (<NUM>) OFF mode.

In this embodiment, the duration T can be much shorter than <NUM>, because the output voltage of the voltage generator <NUM> is not ramped up and down slowly (as it was in the prior art embodiment described above in connection with <FIG>). Instead, the output of the AC voltage generator <NUM> either stays at its full value constantly (as described below in connection with <FIG>) or jumps to its full value immediately after the switch <NUM> switches states (as described below in connection with <FIG>). In either case, the signal that is applied to the transducer arrays 25A/P, <NUM>/R will be at its full value the vast majority of the time (e.g., > <NUM>% or > <NUM>% of the time). And keeping the TTFields stronger for a larger percentage of time can advantageously improve the efficacy of the TTFields treatment. In some embodiments, the duration T is greater than <NUM>. In some embodiments, the duration T is between <NUM> and <NUM>. In some embodiments, the duration T is between <NUM> and <NUM>. Notably, in contrast to the situation described above in connection with <FIG>/B, the system operates at its full output voltage for a large percentage of time regardless of how short the duration of T is.

<FIG> depicts a first approach for achieving synchronization between the AC voltage generator <NUM> and the switch <NUM> that operates by controlling timing of transitions of the switch <NUM> from the OFF state to either the LR state or the AP state (indicated by trace <NUM>) so that the transitions coincide with windows of time during which the instantaneous magnitude of the output of the AC voltage generator is small enough so that jumping from the OFF state to the small voltage will not cause the subject who is being treated to experience a perceptible sensation.

The voltage threshold that results in perception may vary from person to person, and may also depend on which portions of the body make contact with the transducer arrays. For example, on various portions of the body, jumps from the OFF state to either 1V, <NUM>. 5V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, or <NUM> V will not be perceptible. So to prevent the switching from causing a perceptible sensation, transitions from the OFF state to either the LR state or the AP state should be timed to coincide with windows of time during which the instantaneous output magnitude of the AC voltage generator is less than or equal to those thresholds. In this approach, the output voltage of the AC voltage generator <NUM> can remain at its full steady-state value <NUM>% of the time, as depicted by trace <NUM>. In some preferred embodiments, the transitions occur when the instantaneous output of the AC voltage generator is less than <NUM> V in magnitude.

Assume, for example, that the threshold of perceptibility for a given subject is <NUM> V, and that the output of the AC voltage generator <NUM> is <NUM> V pk-pk (which means that the instantaneous output value of the AC voltage generator <NUM> will range between +<NUM> and -<NUM> V). The instantaneous output of the AC voltage generator will be less than <NUM> V in magnitude for the first <NUM>° of each <NUM>° cycle, for the middle <NUM>° of each cycle, and for the last <NUM>° of each cycle. By restricting the switching of the switch <NUM> from the OFF state to either the LR state or the AP state to these specific windows of time, the signal <NUM> that is applied to the transducer arrays (<NUM>/R or 25A/P) will never have any spikes that are larger than <NUM> V in magnitude, which means that they will not be perceptible to the subject. Note that when the AC voltage generator is operating at <NUM>, <NUM>° corresponds to <NUM>, and this window is sufficiently long to facilitate synchronization by aligning the switching of the switch <NUM> to the specific windows of time identified in this paragraph.

In some preferred embodiments, the switching of the switch <NUM> from the OFF state to either the LR state or the AP state is restricted to those windows of time in which the instantaneous output of the AC voltage generator is less than <NUM> V in magnitude). Assuming the same <NUM> V pk-pk output voltage, the instantaneous output of the AC voltage generator will be less than <NUM> V in magnitude in the first <NUM>° of each cycle, in the middle <NUM>° of each cycle, and in the last <NUM>° of each cycle. By restricting the switching of the switch <NUM> from the OFF state to either the LR state or the AP state to these specific windows of time, the signal <NUM> that is applied to the transducer arrays (<NUM>/R or 25A/P) will never have any spikes that are larger than <NUM> V in magnitude. As would be appreciated by those skilled in the art, timing of switch <NUM> can be similarly adjusted for other threshold values.

In the example illustrated in <FIG>, the output voltage of the AC voltage generator <NUM> remains at its full steady-state value <NUM>% of the time, as depicted by trace <NUM>. In this situation, the signal <NUM> that is applied to the transducer arrays (<NUM>/R or 25A/P) jumps instantly to its full steady-state output voltage as soon as it is turned on. The signal that is applied to the transducer arrays 25A,P, 25LIR will therefore be at its full value almost all the time. And as noted above, keeping the TTFields stronger for a larger percentage of time can advantageously improve the efficacy of the TTFields treatment. Note, however, that the output voltage of the AC voltage generator <NUM> during the very beginning of the LR or AP state is not critical, and in alternative embodiments it is acceptable if the AC voltage generator's output voltage dips to some extent. But the output of the AC voltage generator <NUM> should preferably reach at least <NUM>% of the AC voltage generator's steady-state output voltage within <NUM> after the electronic switch switches from the OFF state to either the LR state or the AP state. In some preferred embodiments, this occurs within <NUM>. And in some preferred embodiments, this occurs within <NUM>.

A similar synchronization of the switching of the switch <NUM> to the low-magnitude portions (i.e., less than or equal to 1V, <NUM>. 5V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, or <NUM> V in magnitude) of the AC voltage generator's output sinusoid is preferably implemented when the switch <NUM> switches from either the LR state or the AP state back to the OFF state.

<FIG> depicts a second approach for achieving synchronization between the AC voltage generator <NUM> and the switch <NUM> in <FIG>. This approach operates by reducing the instantaneous output voltage of the AC voltage generator <NUM> to less than <NUM> V in magnitude prior to switching of the switch <NUM> from the OFF state to either the LR state or the AP state, in order to prevent spikes from appearing on the conductors that lead to the transducer arrays 25LIR and 25A/P when the switch <NUM> switches states. In some preferred embodiments, the instantaneous output voltage of the AC voltage generator <NUM> is reduced to less than <NUM> V (e.g., to <NUM> V) in magnitude prior to switching of the switch <NUM>.

Reducing the output voltage of the AC voltage generator <NUM> to <NUM> V is easy to accomplish when any of the embodiments described above in connection with <FIG> and <NUM>-<NUM> are used as the AC voltage generator. For example, when the <FIG> and <FIG> AC voltage generator is used, its output can be set to zero by ensuring that neither the first control signal nor the second control signal is applied to the control input of the power switcher <NUM>, which means that all the switches (i.e., switches <NUM>-<NUM>) in the power switcher <NUM> will remain off. Similarly, when the <FIG> and <FIG> AC voltage generator is used, its output can be set to zero by sending a control signal to the power switcher 60B that causes all the switches (i.e., switches <NUM>-<NUM>) in the power switcher 60B to switch off.

In <FIG>, the upper trace <NUM> depicts the output of the AC voltage generator <NUM>; the middle trace <NUM> depicts the state of the switch <NUM>; and the lower trace <NUM> depicts one of the outputs (LR or AP) of the switch <NUM>. Assume that the switch <NUM> starts in the OFF state, and that at t20 the switch <NUM> will be set to route the output of the AC voltage generator <NUM> to either the LR pair of transducer arrays <NUM>/R or the AP pair of transducer arrays 25A/P. At some time prior to t20, control signals are sent to the AC voltage generator <NUM> to reduce the output voltage of the AC voltage generator <NUM> to zero. Because the output of the AC voltage generator <NUM> is <NUM> V when the switch <NUM> is switched at t20, a spike will not appear on the conductors that lead to the transducer arrays 25LIR and 25A/P at that time.

A short interval of time (e.g., <<NUM>) later, at t21, the synchronization controller <NUM> (see <FIG>) begins sending control signals to the AC voltage generator <NUM> (e.g., as described above in connection with <FIG> and <FIG>), which causes the AC voltage generator <NUM> to begin generating the sinusoid <NUM>. Due to the construction of the AC voltage generator (e.g., as described above in connection with <FIG> and <FIG>), and in particular the output filter <NUM>/80B in the <FIG> embodiments, the AC voltage generator <NUM> will not introduce any spikes on the output <NUM> at t21, so no spikes will propagate to the output <NUM>. And because the switch <NUM> is already settled into its current state, the switch <NUM> will not introduce any spikes on the output <NUM> (which is fed to the transducer arrays 25LIR or 25A/P) at t21.

Notably, as depicted in <FIG>, the output voltage <NUM> of the AC voltage generator <NUM> preferably jumps immediately to its full steady-state output voltage, with no ramp-up period. The signal that is applied to the transducer arrays 25A/P, 25LIR will therefore be at its full value almost all the time. And as noted above, keeping the TTFields stronger for a larger percentage of time can advantageously improve the efficacy of the TTFields treatment. <FIG> depicts the immediate jump to the full steady-state output voltage on a longer timescale, and this figure stands in sharp contrast to the prior art configuration depicted in <FIG>. Note, however, that the output voltage of the AC voltage generator <NUM> during the very beginning of the LR or AP state is not critical, and in alternative embodiments it is acceptable if the AC voltage generator's output voltage does not jump immediately to its full steady-state voltage. But the output of the AC voltage generator <NUM> should preferably reach at least <NUM>% of the AC voltage generator's steady-state output voltage within <NUM> after the electronic switch switches from the OFF state to either the LR state or the AP state. In some preferred embodiments, this occurs within <NUM>. And in some preferred embodiments, this occurs within <NUM>.

<FIG> also depicts an exemplary approach for synchronizing the AC voltage generator <NUM> and the switch <NUM> when the time arrives to switch from either the LR state or the AP state to the OFF state. At time t22, the AC voltage generator <NUM> is generating a sinusoid at its full steady-state output voltage, and the switch <NUM> remains set to route the output of the AC voltage generator <NUM> to either the LR pair of transducer arrays 25LIR or the AP pair of transducer arrays 25A/P. At time t23, the controller stops generating the signals (described above in connection with <FIG> and <FIG>) to the power switcher <NUM>/60B, which causes the output of the AC voltage generator <NUM> to drop to 0V. And due to the construction of the AC voltage generator described above, no spikes will appear on the output <NUM> at t23, which means that no spikes will appear on the output <NUM> of the switch <NUM>. A short interval of time later (e.g., <<NUM>), at t24, the switch <NUM> is set to the OFF state. And because the output of the AC voltage generator <NUM> is <NUM> V at t24, no spikes will be introduced onto the conductors that run between the switch <NUM> and the transducer arrays <NUM> at t24.

In the embodiments described above in connection with <FIG> and <FIG>, the switch <NUM> (a) routes the output of the AC voltage generator <NUM> to the left and right transducer arrays (<NUM>/R) for a duration T, then (b) routes the output of the AC voltage generator <NUM> to the anterior and posterior transducer arrays (25A/P) for a duration T, and then repeat steps (a) and (b) in an alternating sequence. A short duration of time (e.g., <NUM>-<NUM>) during which the output of the AC voltage generator <NUM> is not routed to either pair of transducer arrays is interposed between each step. This is choreographed by repeatedly adjusting a control input of the switch <NUM> to cycle through the LR mode, the AP mode, and the OFF mode in the following repeating sequence (<NUM>) LR mode, (<NUM>) OFF mode, (<NUM>) AP mode, and (<NUM>) OFF mode.

In a variation of these embodiments, the OFF mode (i.e., the short duration of time during which the output of the AC voltage generator <NUM> is not routed to either pair of transducer arrays) is omitted. With this variation, the switch <NUM> (a) routes the output of the AC voltage generator <NUM> to the left and right transducer arrays (<NUM>/R) for a duration T, then (b) routes the output of the AC voltage generator <NUM> to the anterior and posterior transducer arrays (25A/P) for a duration T, and then repeat steps (a) and (b) in a two-step alternating sequence. This is choreographed by repeatedly adjusting a control input of the switch <NUM> to cycle through the LR mode and the AP mode in the following repeating sequence (<NUM>) LR mode, (<NUM>) AP mode.

In this variation where the OFF mode is omitted, the duration T can also be much shorter than <NUM> for the same reasons as described above. And here again, in contrast to the situation described above in connection with <FIG>/B, the system operates at its full output voltage for a large percentage of time (e.g., <NUM>% of the time) regardless of how short the duration of Tis.

Transitions of the switch <NUM> from the LR state to the AP state and from the AP state to the LR state are timed so that the transitions coincide with windows of time during which the instantaneous magnitude of the output of the AC voltage generator is small enough so as not to cause the subject who is being treated to experience a perceptible sensation. More specifically, transitions between the LR and AP states should be timed to coincide with windows of time during which the instantaneous output magnitude of the AC voltage generator is less than or equal to the same thresholds noted above in the <FIG> embodiments that include the OFF state (e.g., in the first <NUM>° of each cycle, in the middle <NUM>° of each cycle, and in the last <NUM>° of each cycle).

<FIG> depicts an example of timing that synchronizes transitions of the switch <NUM> (shown in <FIG>) between the LR and AP states (indicated by trace <NUM> in <FIG>) with the output (indicated by trace <NUM>) of the AC voltage generator <NUM> (shown in <FIG>) so that the transitions between the LR and AP states coincide with windows of time during which the instantaneous magnitude of the output of the AC voltage generator <NUM> (trace <NUM>) is close to zero (e.g., < <NUM> V or < <NUM> V).

The embodiments described above in connection with <FIG> advantageously make it possible to drive the transducer arrays at full power for a much larger percentage of the time than was possible in the prior art systems, without fear of introducing voltage spikes that could create an unpleasant sensation in the person being treated. And driving the transducer arrays at full power can advantageously increase the efficacy of treatment using TTFields.

Finally, although the embodiments described above in connection with <FIG> discuss switching the AC voltage between a first pair of transducer arrays positioned anterior/posterior of the relevant body part and a second pair of transducer arrays positioned front/back of the relevant body part, this approach can be extended to more than two pairs of transducer arrays. For example, the third pair of transducer arrays may be positioned above/below the relevant body part, in which case the AC voltage would be switched between the first, second, and third pairs of transducer arrays in a repeating sequence in a manner that is similar to the switching described above in connection with <FIG>.

Claim 1:
An apparatus for generating AC electrical signals for application to a first pair of electrodes (<NUM>/R) and a second pair of electrodes (25A/P), the apparatus comprising:
an AC voltage generator (<NUM>) having an output;
an electronic switch (<NUM>) having an input that receives the output of the AC voltage generator (<NUM>), a first power output, and a second power output, wherein the electronic switch (<NUM>) is configured to operate in a first mode that routes the output of the AC voltage generator (<NUM>) to the first power output, and a second mode that routes the output of the AC voltage generator (<NUM>) to the second power output, and the electronic switch (<NUM>) is further configured to cycle through a repeating sequence that includes the first mode and the second mode; and
a controller (<NUM>) configured to synchronize the operation of the AC voltage generator (<NUM>) and the electronic switch (<NUM>), wherein, within <NUM> after the electronic switch (<NUM>) switches to either the first mode or the second mode, the output voltage of the AC voltage generator (<NUM>) is at least <NUM>% of the steady-state output voltage of the AC voltage generator (<NUM>);
characterized in that switching of the electronic switch (<NUM>) to either the first mode or the second mode is restricted to windows of time that correspond to the first <NUM>°, the middle <NUM>°, and the last <NUM>° of each <NUM>° cycle of the AC voltage generator (<NUM>).