Patent Description:
Memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. In many servers and mobile devices, NAND flash memory (a type of non-volatile storage technology) is widely used as the primary non-volatile storage device due to its high storage density and relatively low access latency. Three-dimensional (3D) NAND flash memory is developed to further increase storage density and reduce manufacturing costs. However, as smaller device size provides the benefit of significantly improved storage capacity, it is becoming increasingly challenging to efficiently and timely read and write data in memory devices.

<CIT> describes a shared non-volatile memory ("NVM") system using a distributed flash translation layer ("FTL") scheme capable of facilitating data storage between multiple hosts and NVM devices. <CIT> describes multi-device storage systems and methods provide disaggregated read/write operations. <CIT> describes a media controller that processes requests including a logical address and address range.

The present disclosure includes a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request contains a logical address of the data. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage devices. The method also includes identifying an on-die SRAM storage of a flash memory die containing logical-to-physical (L2P) information and searching the L2P information to obtain a physical address of the data that corresponds to the logical address. The method further includes retrieving the data from a flash memory array of the flash memory die using the physical address.

The present disclosure also includes a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data and the flash memory controller includes a controller storage. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage. The method also includes searching the controller storage for logical-to-physical (L2P) information. In response to the L2P information being in the controller storage: the method includes obtaining a physical address of the data using the L2P information and retrieving the data from the plurality of flash memory dies using the physical address. In response to the L2P information not being in the controller storage, the method includes identifying an on-die SRAM storage device of a flash memory die containing the L2P information and searching the L2P information to obtain a physical address that corresponds to the logical address. The method further includes retrieving the data from a flash memory array of the flash memory die using the physical address.

The present disclosure further includes a flash memory system having a plurality of flash memory dies. Each flash memory die includes one or more NAND memory arrays and one or more on-die SRAM storage devices. The flash memory system also includes a flash memory controller including a controller storage and one or more processors. Upon executing instructions, the one or more processors are configured to receive a read request for data stored in the plurality of flash memory dies, wherein the read request comprises a logical address of the data. The one or more processors are further configured to identify an on-die SRAM storage containing logical-to-physical (L2P) information, the on-die SRAM storage device formed on a flash memory die of the plurality of flash memory dies. The one or more processors further configured to search the L2P information to obtain a physical address of the data that corresponds to the logical address. The flash memory controller is also configured to retrieve the data from a NAND memory array of the flash memory die using the physical address.

It is noted that, in accordance with the common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of illustration and discussion.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure being covered by the claims. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

The substrate comprises a top surface and a bottom surface. The top surface of the substrate is where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate.

A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

As used herein, the term "3D NAND memory device" (referred to herein as "memory device") refers to a semiconductor device with vertically-oriented strings of 3D NAND memory cell transistors (referred to herein as "memory strings," such as NAND strings or 3D NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate.

A solid-state drive ("SSD") is a storage device capable of recording data. For example, SSD devices can use non-volatile memory components to store and retrieve data. User or device interfaces allow other systems to access the storage capacities of SSD devices. To store data persistently, various types of non-volatile memories such as flash-based memory may be used. 3D NAND memory devices are a type of non-volatile memory devices that are developed to increase data storage capacity. Flash memory devices can be fabricated with several different types of integrated circuit technologies such as NOR or NAND logic gates with floating-gates. Depending on the application, flash memory devices can be arranged in arrays and configured to be accessed as a block, a page, a word, and/or a byte. Each page can contain <NUM>N bytes, where N is an integer, and typical page sizes can be, for example, <NUM>,<NUM> bytes (<NUM> kb), <NUM>,<NUM> bytes (<NUM> kb), <NUM>,<NUM> bytes (<NUM> kb) or more per page. Pages can be arranged in blocks. For example, a block can contain <NUM>, <NUM>, or more pages. The read and write operations for NAND memory devices are performed on a page-by-page basis while an erase operation can be performed on a block-by-block basis.

A hard disk is addressed linearly by logical address (e.g., logical block address) while NAND devices address memory storage by physical address (e.g., page number). Therefore, flash memory devices usually allocate a portion of the controller circuitry to maintain a record of mappings of each logical block address to the current page number where data is stored. This record mapping can be managed by a flash translation layer (FTL) that can provide a logical-to-physical (L2P) table for mapping the two addresses. The FTL can be implemented using an allocated portion of flash memory controller circuitry and controlling software. To retrieve a specific piece of data, a host device can provide a logical address of the target data and the flash memory controller can utilize L2P mapping tables to identify a physical page address of the target data in the non-volatile memory device and retrieve the stored data.

Several approaches can be used for storing and maintaining L2P mapping tables. One such approach is single-level direct L2P mapping. Under such mapping scheme, the mapping table includes an entry for each page and a summary page for metadata at the end of each block that contains logical block address information. The L2P mapping table can be stored in a memory device within the flash memory controller. For example, the L2P mapping table can be stored in a static random access memory (SRAM) device Single-level direct L2P mapping can contain the mapping information for the entire flash memory devices. Therefore, the single-level direct page mapping scheme requires a large amount of storage space (in the order of <NUM>-<NUM> MB per GB of user storage) to store the L2P mapping table, which can be challenging for high capacity flash storage memory devices.

Another approach for storing and maintaining L2P mapping tables is the multi-level mapping schemes. For example, multi-level mapping schemes can group together a number of adjacent logical blocks and can include a page global directory for each grouped blocks. The page global directories can be stored in a memory device (e.g., SRAM) within the flash memory controller for quick access. The mapping scheme also includes page middle directories and page tables that are stored and maintained in pages located at a memory cell level in the spare areas of the NAND memory devices. Page tables contain physical block numbers and physical page numbers of the data.

A flash translation layer ("FTL") can be located in the flash memory control module for translating a logical address to a physical address. Under the single-level direct L2P mapping, FTL can read and scan the L2P mapping table stored within the flash memory controller. Under the multi-level mapping scheme, the FTL would read the page global directory stored in the flash memory controller and access the spare memory cells of the NAND memory devices for the page middle directories and the page tables in order to retrieve the requested data address. The FTL can be a module stored in a static random-access memory (SRAM) or a dynamic random-access memory (DRAM) in the flash memory controller module. Accessing speed to the SRAM within the flash memory and spare memory cells of the NAND memory devices can be different. For example, the read latency of SRAM within the flash memory controller module can be in the order of a few microseconds, whereas the read latency from the cell level of the NAND memory devices can be an order of magnitude greater, for example, a few tens of microseconds.

With increasing storage capacity in memory devices, such as 3D NAND memories, the size of L2P tables has become immensely large and requires a substantial amount of storage space for access operation such as storing L2P tables and buffering data. Particularly, in mobile devices that do not contain DRAM storage, implementing single-level direct L2P tables in the flash memory controller SRAM storage can result in larger device size and higher manufacturing costs. On the other hand, implementing multi-level mapping scheme by storing components of L2P tables at flash memory controller and at the spare memory cells of the non-volatile memory devices can result in long latency and a decline in device performance.

To address the above shortcomings, embodiments described herein are directed to systems and methods for reducing latency in flash memory systems without expanding device footprint. More particularly, this disclosure is directed to caching L2P tables in SRAM storage that are located on the same die as the NAND flash memory arrays, i.e., on-die SRAM. For example, page middle directory and page tables can be stored in on-die SRAM for quick access by the flash memory controller. The methods can include program codes and/or algorithms that implement an indicate flag for providing the location of the L2P table that include address information for the target data. For example, the indicate flag can display a first status indicating that the target L2P table is stored in the on-die SRAM storage or a second status indicating that it is stored in the SRAM of the flash memory controller. As the flash memory system can include more than one flash memory dies, the indicate flag can also indicate which flash memory die contains the on-die SRAM that stores the target L2P table. In addition, the method can also include swapping L2P tables between various on-die SRAMs and the flash memory controller SRAM. Structures and components described in the present application can be implemented on hardware, firmware, software, or any combinations thereof. Methods and systems described in the present disclosure can reduce the read latency of 3D NAND flash memory devices by more than <NUM>%.

<FIG> illustrates a block diagram of a flash memory system <NUM>, in accordance to some embodiments. Flash memory system <NUM> can include a flash memory controller <NUM> and an array of flash memory dies <NUM>. Flash memory controller <NUM> communicates with a host controller <NUM> through an interface <NUM>. The host controller <NUM> is operable to request flash memory controller to perform read, program, and erase operations of the flash memory dies <NUM> by sending commands and/or data through the interface <NUM>. Flash memory controller <NUM> can be configured to retrieve data from one or more flash memory dies <NUM> (e.g., an array of flash memory devices) and send the data to host controller <NUM> via data bus. The retrieved dated can be transmitted by host controller <NUM> to host computers or other system components, not illustrated. The array of flash memory devices can include one or more arrays of NAND flash memory, as introduced below as elements <NUM>.

Host controller <NUM> sends data to be stored at flash memory dies <NUM> or retrieves data by instructing flash memory controller <NUM> to read data from flash memory dies <NUM>. Host controller <NUM> can handle I/O requests received from a host computer (not illustrated in <FIG>), ensure data integrity and efficient storage, and manage flash memory dies <NUM>. Interface <NUM> can provide data and control communication between flash memory controller <NUM> and the flash memory dies <NUM> via data bus.

Flash memory controller <NUM> can include an encoder/decoder unit <NUM>, a control logic <NUM>, a controller storage <NUM>, a flash translation layer (FTL) <NUM>, and a page buffer <NUM>. Other suitable components can be included in flash memory controller <NUM> and are not illustrated or described herein for simplicity. In some embodiments, FTL <NUM> can further include storage areas (e.g., SRAM) for storing L2P mapping information or any other suitable information.

Encoder/decoder unit <NUM> can provide encoding and decoding data processed by flash memory controller <NUM>. Encoder/decoder unit <NUM> can also generate and store error correction codes (ECC) and metadata for memory management. Encoder/decoder unit <NUM> can be used for detecting and correcting errors in the stored data.

Control logic <NUM> can be any suitable integrated circuitry (e.g., one or more processors) configured to receive instructions from host controller <NUM> and perform read, program, erase operations-as well understood by persons of ordinary skill in the art (POSA)-of flash memory dies <NUM> by transmitting commands and/or data with flash memory dies <NUM> through interface <NUM>. For example, control logic <NUM> receive requests for flash media access, such as read or write operations, from one or more external devices through host controller <NUM>. Control logic <NUM> can be further configured to communicate with and control other components of flash memory controller <NUM>. For example, control logic <NUM> can instruct FTL to scan internal memory storage for mapping information and send/receive address-mapping information from FTL. Control logic <NUM> can further communicate with encoder/decoder unit <NUM>, page buffer <NUM>, and other suitable components of flash memory controller <NUM>.

Controller storage <NUM> can be used to store commands for the operation of control logic <NUM>. In some embodiments, controller storage <NUM> can be a storage media for storing mapping information. For example, controller storage <NUM> can include single-level direct L2P mapping tables for a sector of the flash memory dies <NUM>. In some embodiments, controller storage <NUM> can include page global directory information for the flash memory dies <NUM>. The page global directory information can be stored in a random access memory device (RAM) and used as a pseudo-cache to provide fast lookup of mapping data. Page global directories are well understood by a POSA and are not described in detail herein for simplicity. In some embodiments, controller storage <NUM> can include software codes, commands, computer logic, firmware, any suitable information. In some embodiments, controller storage <NUM> can be an SRAM device.

Flash translation layer (FTL) <NUM> can be configured to provide L2P mapping table for converting logical addresses to physical addresses. Requests for accessing flash media received by control logic <NUM> can include one or more logical block address where user data should be read or written. FTL <NUM> can be configured to translate the logical block address of the desired data into a physical address by scanning through various L2P tables. For example, FTL <NUM> can generate L2P mapping information and send such information to storage media located in flash memory controller <NUM>, such as controller storage <NUM>. FTL <NUM> can also send the mapping information to storage media located on flash memory dies <NUM>, such as on-die SRAM or memory cells. FTL <NUM> can also search abovementioned storage media for L2P information upon requests by flash memory controller <NUM>.

Page buffer <NUM> can include one or more register circuitry for storing sections of data. For example, under a two-pass programming scheme page buffer <NUM> can store data such as lower page data, middle page data, and upper page data. Data transfers between host controller <NUM> and array of flash memory dies <NUM> can be temporarily stored in page buffer <NUM>. The structure and functions of page buffer <NUM> is well understood by a POSA and are not described in detail herein for simplicity.

Flash memory dies <NUM> can be configured to store user data and include circuitry components for communicating with flash memory controller <NUM> and for storing L2P mapping information. In some embodiments, each flash memory die <NUM> can include data cache <NUM>, on-die SRAM <NUM>, and arrays of NAND flash memory array <NUM>. Flash memory die <NUM> can be a memory chip (package), a memory die, or any portion of a memory die. In some embodiments, each flash memory die <NUM> can include one or more on-die SRAM <NUM> or one or more NAND flash memory arrays <NUM>. The additional on-die SRAM <NUM> and NAND flash memory arrays <NUM> are not illustrated in <FIG> for simplicity.

Data cache <NUM> can be configured to temporarily store data that is transmitted between flash memory controller <NUM> and NAND flash memory array <NUM>. For example, during a read operation for accessing stored user data from NAND flash memory array <NUM>, data cache <NUM> can be configured to temporarily store the retrieved data prior to sending the retrieved data to flash memory controller <NUM>.

On-die SRAM <NUM> can be configured to store L2P mapping information for quick access by flash memory controller <NUM>. For example, under the multi-level mapping schemes, L2P mapping information, such as page middle directories and page tables, can be stored in the on-die SRAM <NUM> and accessed by FTL <NUM> of flash memory controller <NUM> through interface <NUM>. Since reading data from SRAM storage media can be orders of magnitude faster than reading data from NAND flash memory cells, compared to storing L2P information in spare memory cells of NAND flash memory arrays, storing such information in an on-die SRAM <NUM> can provide the benefit of, among other things, lower data read latency. In some embodiments, on-die SRAM <NUM> can be any other suitable memory devices having greater speed than NAND flash memory cells. In some embodiments, media storage such as dynamic RAM (DRAM) can be implemented in flash memory die <NUM> to perform similar functions as on-die SRAM <NUM>.

NAND flash memory array <NUM> can include one or more memory planes, each of which can include a plurality of memory blocks. Identical and concurrent operations can take place at each memory plane. The memory block, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Each memory block can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. For simplicity, the memory blocks are also referred to as "memory array" or "array. " The memory array is the core area in a memory device, performing storage functions.

<FIG> is a schematic circuit diagram illustrating flash memory cell arrangements, according to some embodiments of the present disclosure. NAND flash memory arrays <NUM> can include an array of flash memory cells <NUM> that are deployed in array arrangement as shown by <FIG>. NAND flash memory arrays <NUM> can be 3D NAND flash memory arrays that include a stack of gate electrodes arranged over a substrate, with semiconductor channels through and intersecting word lines, into the substrate. The bottom/lower gate electrodes function as bottom/lower selective gates. The top/upper gate electrodes function as top/upper selective gates. The word lines/gate electrodes between the top/upper selective gate electrodes and the bottom/lower gate electrodes function as word lines. The intersection of a word line and a semiconductor channel forms a memory cell. The top/upper selective gates are connected to word lines for row selection, and the bottom/lower selective gates are connected to bit lines for column selection. Examples of 3D NAND flash memory devices and methods for forming the same can be found in <CIT>, titled "Memory Device and Forming Method Thereof".

Each of the NAND flash memory cells <NUM> indicates one or more bit values stored therein. Specifically, each NAND flash memory cell <NUM> can include a transistor with a floating gate that stores charge. NAND flash memory cells <NUM> are coupled in form of multiple series strings <NUM>, wherein drains of the memory cells are each coupled to a source of another NAND flash memory cell <NUM>. NAND flash memory arrays <NUM> can include word lines WL0-WLN. Each of the word lines WL0-WLN can be connected to control gates of each NAND flash memory cell <NUM> of a row of NAND flash memory array <NUM> and utilized to bias the control gates of the NAND flash memory cells <NUM> in the row. NAND flash memory arrays <NUM> also includes bit lines BL0-BLK. Each of the bit lines BL0-BLK is coupled to a series string <NUM> and coupled to data cache <NUM>. Sensing circuitry (not shown, but apparent to POSA) can be controlled by control logic <NUM> to detect the states of each NAND flash memory cells <NUM> by sensing voltage or current on a particular bit line of bit lines BL0-BLK.

Other suitable circuitry components can be included in the schematic circuit diagram of <FIG> and are not illustrated for simplicity. For example, selection gates, sensing circuitry, address decoders, driving circuits, other supporting logic/circuits, and any suitable circuitry components can be included and are omitted here for sake of brevity.

<FIG> is a flow chart illustrating an operation of a flash memory system implementing an on-die SRAM for reducing data read latency, according to some embodiments of the present disclosure. It should be understood that the method <NUM> are not exhaustive and that other operation steps can be performed as well before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of method <NUM> can be omitted or other operation steps can be included, which are not described here for simplicity. In some embodiments, operation steps of method <NUM> can be performed in a different order and/or vary. Method <NUM> can be performed using flash memory devices and circuitry described in <FIG> and <FIG>.

Method <NUM> starts at operation step <NUM>, where a host controller initiates a user data read request, according to some embodiments of the present disclosure. Referring to <FIG>, host controller <NUM> may initiate a user data request command to flash memory controller <NUM> through interface <NUM> requesting a specific piece of user data that is stored in flash memory array <NUM>. In some embodiments, the request command may contain one or more logical addresses of the requested user data.

Method <NUM> continues with operation step <NUM>, where the flash memory controller scans and searches L2P table in the media storage (e.g., SRAM) of the flash memory controller, according to some embodiments of the present disclosure. Referring to <FIG>, flash memory controller <NUM> can be configured to receive the user data request from host controller and instruct FTL <NUM> to search controller storage <NUM> of flash memory controller <NUM> to determine if controller storage <NUM> contains the mapping information of the requested user data. In some embodiments, controller storage <NUM> can include a single-level direct L2P mapping of a selection of user data. For example, to reduce read latency, the storage media of flash memory controller <NUM> can contain single-level direct L2P mapping information for user data that is frequently accessed by the user. In some embodiments, the storage media of flash memory controller <NUM> can also contain a sector of L2P mapping information. For example, under a multi-level mapping scheme, controller storage <NUM> can include page global directories and FTL <NUM> can be configured to search the page global directories.

Method <NUM> continues with operation step <NUM>, where the FTL is configured to determine if the L2P data is stored in the controller media storage, according to some embodiments of the present disclosure. In some embodiments, the user data request initiated by host controller can contain logical address information of the requested data. Referring to <FIG>, FTL <NUM> can be configured to determine if the L2P address information corresponding to the logical address information is stored in the controller media storage or in the flash memory dies.

If the FTL determines that the L2P address information is stored in the flash controller storage, method <NUM> continues with operation step <NUM>, where the FTL reads a sector of L2P information from the flash controller storage, according to some embodiments of the present disclosure. Referring to <FIG>, FTL <NUM> can be configured to search contents of controller storage <NUM> to identify the sector of L2P mapping data that corresponds to the logical address information received from host controller <NUM>. Method <NUM> continues with operation step <NUM>, where the physical address is retrieved based on the reading of the L2P data. Under a single-level direct L2P mapping scheme, FTL <NUM> can look up the physical address in the L2P mapping table to obtain corresponding physical address of the logical address received from host controller <NUM>.

Method <NUM> continues to operation step <NUM>, where control logic <NUM> of flash memory controller <NUM> retrieves user data from NAND flash memory array <NUM> based on the physical address of the user data. Then method <NUM> continues with operation step <NUM>, where flash memory controller transmits data to host controller. For example, flash memory controller <NUM> receives user data from flash memory dies <NUM> and temporarily stores the user data in page buffer <NUM> before transmitting the user data to host controller <NUM> through interface <NUM>.

On the other hand, if the FTL determines that L2P address information is not stored in the flash controller storage at operation step <NUM>, method <NUM> continues with operation step <NUM>, where an indicate flag is checked to determine where the L2P address information is stored. For example, a first status (e.g., status <NUM>) of the indicate flag can inform flash memory controller <NUM> that the corresponding L2P address information is stored at the spare cells in one die of the flash memory dies <NUM>. The indicate flag can be a string of bits that provide information, such as identifying which die of the flash memory die the L2P address information is stored. For example, the indicate flag can be one or more bits of information stored in controller storage <NUM>. The indicate flag can also include the block information whether the L2P mapping information is stored in NAND flash memory array <NUM> or on-die SRAM <NUM>. If the L2P address information is stored at the spare cells of the NAND flash memory array <NUM>, method <NUM> continues with operation step <NUM>, where FTL <NUM> can be configured to retrieve the physical address from L2P data stored in the spare cells of NAND flash memory array <NUM>. The indicate flag can include information that directs flash memory controller <NUM> to a specific die that contains the L2P data.

Alternatively, a second status (e.g., status <NUM>) of the indicate flag can inform flash memory controller <NUM> that the corresponding L2P address information is stored in the on-die SRAM. The indicate flag can also be configured to include the identification of on-die SRAM, such as the die number on which the on-die SRAM is located. The indicate flag can further include identification of a sector of the on-die SRAM on which the relevant portion of L2P mapping information is stored. In such scenario, method <NUM> continues with operation step <NUM>, where the FTL can be configured to sweep a sector of L2P mapping data from the on-die SRAM onto the controller storage, according to some embodiments of the present disclosure. Based on information provided by the indicate flag, the FTL can identify a sector of a specific on-die SRAM of flash memory dies <NUM> and sweep the sector of L2P mapping data from on-die SRAM <NUM> to controller storage <NUM>. In some embodiments, sweeping the sector of L2P mapping data includes transmitting the sector of the L2P mapping data from on-die SRAM <NUM> to flash memory controller <NUM> and storing the sector of L2P mapping data in controller storage <NUM>. Method <NUM> continues with operation <NUM>, where the FTL updates the indicate flag, according to some embodiments of the present disclosure. Referring to <FIG>, FTL <NUM> can update the indicate flag to include information of the sector of L2P mapping data that is currently stored in controller storage <NUM>. The stored information can be available for subsequent read requests. Method <NUM> continues with operation <NUM>, where physical address can be retrieved from the L2P data, according to some embodiments of the present disclosure. FTL <NUM> can be configured to scan and read the L2P data that has been swept onto controller storage <NUM> and obtain the physical address that corresponds to the logical address provided by host controller <NUM>. The indicate flag can include one or more additional suitable status.

Method <NUM> then continues with operation step <NUM>, where data is read from the memory cells, according to some embodiments of the present disclosure. Based on the physical address obtained by FTL <NUM>, control logic <NUM> of flash memory controller <NUM> retrieves user data from NAND flash memory array <NUM> based on the physical address of the user data.

Method <NUM> then continues with operation step <NUM>, where flash memory controller transmits data to host controller. For example, flash memory controller <NUM> receives user data from flash memory dies and transmits the user data to host controller <NUM> through interface <NUM>.

Various embodiments of the present disclosure are directed to systems and methods for reducing latency in flash memory systems without expanding device footprint. For example, flash memory dies can include SRAM storage that are located on the same die as the NAND flash memory arrays. The methods can include program codes and/or algorithms that implement one or more indicate flags for providing the location of the L2P table that include address-mapping information for the target data. For example, the indicate flag can display a first status indicating that the target L2P table is stored in the on-die SRAM storage or a second status indicating that it is stored in the SRAM of the flash memory controller.

In some embodiments, a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request contains a logical address of the data. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage devices. The method also includes identifying an on-die SRAM storage of a flash memory die containing logical-to-physical (L2P) information and searching the L2P information to obtain a physical address of the data that corresponds to the logical address. The method further includes retrieving the data from a flash memory array of the flash memory die using the physical address.

In some embodiments, a method for reading data from a flash memory includes receiving, by a flash memory controller, a read request for data stored in a plurality of flash memory dies. The read request includes a logical address of the data and the flash memory controller includes a controller storage. Each flash memory die of the plurality of flash memory dies includes one or more flash memory arrays and one or more on-die static random access memory (SRAM) storage. The method also includes searching the controller storage for logical-to-physical (L2P) information. In response to the L2P information being in the controller storage: the method includes obtaining a physical address of the data using the L2P information and retrieving the data from the plurality of flash memory dies using the physical address. In response to the L2P information not being in the controller storage, the method includes identifying an on-die SRAM storage device of a flash memory die containing the L2P information and searching the L2P information to obtain a physical address that corresponds to the logical address. The method further includes retrieving the data from a flash memory array of the flash memory die using the physical address. In some embodiments, a flash memory system includes a plurality of flash memory dies. Each flash memory die includes one or more NAND memory arrays and one or more on-die SRAM storage devices. The flash memory system also includes a flash memory controller including a controller storage and one or more processors. Upon executing instructions, the one or more processors are configured to receive a read request for data stored in the plurality of flash memory dies, wherein the read request comprises a logical address of the data. The one or more processors are further configured to identify an on-die SRAM storage containing logical-to-physical (L2P) information, the on-die SRAM storage device formed on a flash memory die of the plurality of flash memory dies. The one or more processors further configured to search the L2P information to obtain a physical address of the data that corresponds to the logical address. The flash memory controller is also configured to retrieve the data from a NAND memory array of the flash memory die using the physical address.

Claim 1:
A method for reading data from a flash memory, comprising:
receiving, by a flash memory controller (<NUM>), a read request for data stored in a plurality of flash memory dies (<NUM>), wherein
- each flash memory die of the plurality of flash memory dies (<NUM>) comprises one or more flash memory arrays (<NUM>) and one or more on-die static random access memory (SRAM) storage devices (<NUM>) located on the same die as the flash memory arrays (<NUM>),
- one of the one or more on-die static random access memory (SRAM) storage devices (<NUM>) containing logical-to-physical (L2P) information, and
- the read request comprises a logical address of the data;
identifying the on-die static random access memory (SRAM) storage device (<NUM>) that contains the logical-to-physical (L2P) information, said on-die static random access memory (SRAM) storage device (<NUM>) being formed on one of the plurality of flash memory dies (<NUM>);
searching the logical-to-physical (L2P) information to obtain a physical address of the data that corresponds to the logical address; and
retrieving the data from a flash memory array (<NUM>) of the flash memory die using the physical address.