Patent Description:
Moreover the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

Example fluidic dies may include fluid actuators (e.g., for ejecting and recirculating fluid), where the fluid actuators may include thermal resistor based actuators, piezoelectric membrane based actuators, electrostatic membrane actuators, mechanical/impact driven membrane actuators, magneto-strictive drive actuators, or other suitable devices that may cause displacement of fluid in response to electrical actuation. Fluidic dies described herein may include a plurality of fluid actuators, which may be referred to as an array of fluid actuators. An actuation event may refer to singular or concurrent actuation of fluid actuators of the fluidic die to cause fluid displacement. An example of an actuation event is a fluid firing event whereby fluid is jetted through a nozzle.

In example fluidic dies, the array of fluid actuators may be arranged in sets of fluid actuators, where each such set of fluid actuators may be referred to as a "primitive" or a "firing primitive. " The number of fluid actuators in a primitive may be referred to as a size of the primitive. In some examples, the set of fluid actuators of each primitive are addressable using a same set of actuation addresses, with each fluid actuator of a primitive corresponding to a different actuation address of the set of actuation addresses, with the addresses being communicated via an address bus. In some examples, during an actuation event, in each primitive, the fluid actuator corresponding to the address on the address bus will actuate (e.g., fire) in response to a fire signal (also referred to as a fire pulse) based on a state of the select data (e.g., a select bit state) corresponding to the primitive (sometimes also referred to as nozzle data or primitive data).

In some cases, electrical and fluidic operating constraints of a fluidic die may limit the number of fluid actuators of which can be actuated concurrently during an actuation event. Primitives facilitate selecting subsets of fluid actuators that may be concurrently actuated for a given actuation event to conform to such operating constraints.

By way of example, if a fluidic die includes four primitives, with each primitive having eight fluid actuators (with each fluid actuator corresponding to a different address of a set of addresses <NUM> to <NUM>, for example), and where electrical and fluidic constraints limit actuation to one fluid actuator per primitive, a total of four fluid actuators (one from each primitive) may be concurrently actuated for a given actuation event. For example, for a first actuation event, the respective fluid actuator of each primitive corresponding to address "<NUM>" may be actuated. For a second actuation event, the respective fluid actuator of each primitive corresponding to address "<NUM>" may be actuated. As will be appreciated, such example is provided merely for illustration purposes, where fluidic dies contemplated herein may comprise more or fewer fluid actuators per primitive and more or fewer primitives per die.

Example fluidic dies may include fluid chambers, orifices, and/or other features which may be defined by surfaces fabricated in a substrate of the fluidic die by etching, microfabrication (e.g., photolithography), micromachining processes, or other suitable processes or combinations thereof. Some example substrates may include silicon based substrates, glass based substrates, gallium arsenide based substrates, and/or other such suitable types of substrates for microfabricated devices and structures. As used herein, fluid chambers may include ejection chambers in fluidic communication with nozzle orifices from which fluid may be ejected, and fluidic channels through which fluid may be conveyed. In some examples, fluidic channels may be microfluidic channels where, as used herein, a microfluidic channel may correspond to a channel of sufficiently small size (e.g., of nanometer sized scale, micrometer sized scale, millimeter sized scale, etc.) to facilitate conveyance of small volumes of fluid (e.g., picoliter scale, nanoliter scale, microliter scale, milliliter scale, etc.).

In some examples, a fluid actuator may be arranged as part of a nozzle where, in addition to the fluid actuator, the nozzle includes an ejection chamber in fluidic communication with a nozzle orifice. The fluid actuator is positioned relative to the fluid chamber such that actuation of the fluid actuator causes displacement of fluid within the fluid chamber that may cause ejection of a fluid drop from the fluid chamber via the nozzle orifice. Accordingly, a fluid actuator arranged as part of a nozzle may sometimes be referred to as a fluid ejector or an ejecting actuator.

In some examples, a fluid actuator may be arranged as part of a pump where, in addition to the fluidic actuator, the pump includes a fluidic channel. The fluidic actuator is positioned relative to a fluidic channel such that actuation of the fluid actuator generates fluid displacement in the fluid channel (e.g., a microfluidic channel) to convey fluid within the fluidic die, such as between a fluid supply and a nozzle, for instance. An example of fluid displacement/pumping within a die may sometimes be referred to as microrecirculation. A fluid actuator arranged to convey fluid within a fluidic channel may sometimes be referred to as a non-ejecting or microrecirculation actuator.

In one example nozzle, the fluid actuator may comprise a thermal actuator, where actuation of the fluid actuator (sometimes referred to as "firing") heats the fluid to form a gaseous drive bubble within the fluid chamber that may cause a fluid drop to be ejected from the nozzle orifice. As described above, fluid actuators may be arranged in arrays (such as columns), where the actuators may be implemented as fluid ejectors and/or pumps, with selective operation of fluid ejectors causing fluid drop ejection and selective operation of pumps causing fluid displacement within the fluidic die. In some examples, the array of fluid actuators may be arranged into primitives.

Some fluidic dies receive data in the form of data packets, sometimes referred to as fire pulse groups or as fire pulse group data packets. In some examples, such data packets may include configuration data and select data. In some examples, configuration data includes data for configuring on-die functions, such as address bits representing an address of fluid actuators to be actuated as part of a firing operation, fire pulse data for configuring fire pulse characteristics, and thermal data for configuring thermal operations such as heating and sensing. In some examples, the data packets are configured with head and tail portions including the configuration data, and a body portion including the select (primitive) data. In example fluidic dies, in response to receiving a data packet, on-die control circuitry employs address decoders/drivers to provide the address on an address line, activation logic to activate selected fluid actuators (e.g., based on the address, select data, and a fire pulse), and configuration logic to configure operations of on-die functions, such as fire pulse configuration, crack sensing and thermal operations based on configuration data and a mode signal, for instance.

In addition to fluid actuators, some example fluidic dies include on-die memory (e.g., non-volatile memory (NVM)) to communicate information (e.g., memory bits) with external devices, such as a printer, to assist in controlling operation of the fluidic, including operation of fluid actuators and other devices (e.g., heaters, crack sensors) for regulating fluid ejection. In examples, such information may include thermal behavior, offsets, region information, a color map, fluid levels, and a number of nozzles, for example.

Memories typically include overhead circuitry (e.g., address, decode, read, and write modes, etc.) which are costly to implement and consume relatively large amounts of silicon area on a die. However, since similar circuitry is employed in selecting, actuating, and transferring data to an array of fluid actuators, some example fluidic dies multipurpose portions of the control circuitry for selecting and transferring data to fluid actuators (including portions of a high speed data path, for example) to also select memory elements of a memory array.

To further save space and reduce complexity associated with multi-bus architectures, some example fluidic dies employ a single lane analog bus which is communicatively connected in parallel with the memory elements to read and write information to/from the memory elements over the shared single lane analog bus (which is also sometimes referred to as a sense bus). In some examples, the single-lane bus is able to read/write to memory elements individually or to different combinations of memory elements in parallel. Additionally, some example fluidic dies include devices such as crack sensors, temperature sensors, and heating elements that may also be connected to the signal-lane analog bus for sensing and control.

In example fluidic dies having on-die memories, in addition to communicating select data to select fluid actuators for actuation as part of a fluid actuation operation, data packets may communicate select data to select memory elements which are to be accessed as part of a memory access operation (e.g., read/write operations). To differentiate between different operating modes, such as between a fluid actuation mode and a memory access mode, example fluidic dies may employ different operating protocols for different modes of operation. For example, a fluid die may employ one protocol sequence of operating signals, such as data (e.g., data packets) received via data pads (DATA), a clock signal received which clock pad (CLK), a mode signal received via a mode pad (MODE), and a fire signal received a fire pad (FIRE), to identify fluid actuator operation, and another sequence of such signals to identify memory access operations (e.g., read and write).

In example fluidic dies, on-die memory elements may be one-time-programmable (OTP) elements. During manufacture, information may be written to the memory elements late in the manufacturing process, including after a fluidic die may have been arranged as a part of a printhead or pen. If the memory is found to be defective (e.g., to have one or more failed bits that will not program properly), the fluidic die may not function properly, such that the fluidic die, printhead, and pen are also defective. Additionally, even though the overhead circuitry of the memory may be shared with fluid actuator selection and activation circuitry, the inclusion of on-die memory elements consumes silicone area and increases dimensions of the fluidic die.

The present disclosure, as will be described in greater detail herein, provides a print component, such as a printhead or a print pen, for example, including a fluidic die having an array of fluid actuators. The fluidic die is coupled to a number of input/output (I/O) terminals communicating operating signals for controlling the operation of the fluidic die, including ejection operations of the fluidic actuators, the I/O terminals including an analog sense terminal. The print component includes a memory die, separate from the fluidic die, coupled to the I/O terminals, the memory die to store memory values associated with the print component, such as manufacturing data, thermal behavior, offsets, region information, a color map, a number of nozzles, and fluid type, for example. According to one example, in response to observing operating signals on I/O terminals representing a memory access sequence of the stored memory values, the memory die provides an analog signal on the sense terminal based on the stored memory values corresponding to the memory access sequence.

As will be described in greater detail herein, in one example, the memory die replaces or substitutes for a defective memory array on the fluidic die, thereby enabling the fluidic die, and a print component employing the fluidic die, such as a print pen, for example, to remain operational. In another example, the memory die can be employed instead of a memory array on the fluidic die, thereby enabling the fluidic die and a printhead employing the fluidic die to be made smaller. In another example, the fluidic die can be employed to supplement a memory array on the fluidic die (e.g., to expand the memory capacity).

<FIG> is a block and schematic diagram generally illustrating a memory circuit <NUM>, according to one example of the present disclosure, for a print component, such as a print component <NUM>. Memory circuit <NUM> includes a control circuit <NUM>, and a memory component <NUM> storing a number of memory values <NUM> associated with operation of print component <NUM>. Memory component <NUM> may comprise any suitable storage element, including any number of non-volatile memories (NVM), such as EPROM, EEPROM, flash, NV RAM, fuse, for example. In one example, memory values <NUM> may be values stored as a lookup table, where such lookup table may be an array of indexing data, with each memory value having a corresponding address or index. In examples, each memory value <NUM> represents a data bit having a bit state of "<NUM>" or "<NUM>", or an analog value (e.g., a voltage or a current) corresponding to a "<NUM>" and "<NUM>". In examples, memory circuit <NUM> is a die.

Memory circuit <NUM> includes a number of input/output (I/O) pads <NUM> to connect to a plurality of signal paths <NUM> which communicate operating signals to print component <NUM>. In one example, the plurality of I/O pads <NUM> includes a CLK Pad <NUM>, a DATA Pad <NUM>, a FIRE Pad <NUM>, a MODE Pad <NUM>, and an Analog Pad <NUM>, which will be described in greater detail below. In examples, control circuit <NUM> monitors the operating signals conveyed to print component <NUM> via I/O pads <NUM>. In one example, upon observing a sequence of operating signals representing a memory read (e.g., a "read" protocol), control circuit <NUM> provides an analog electrical signal to Analog Pad <NUM> to provide an analog electrical value at Analog Pad <NUM> representing the stored memory values <NUM> selected by the memory read. In examples, the analog electrical signal provided to Analog Pad <NUM> may be one of an analog voltage signal and an analog current signal, and the analog electrical signal may be one of a voltage level and a current level. In examples, Analog Pad <NUM> may be an analog sense pad connected to an analog sense circuit, and is sometimes referred to herein as SENSE pad <NUM>.

In one example, upon observing a sequence of operating signals representing a memory write (a "write" protocol), control circuit <NUM> adjusts the values of the stored memory values.

<FIG> is a block and schematic diagram generally illustrating memory die <NUM>, according to one example, for a print component <NUM>, where print component <NUM> can be a print pen, a print cartridge, a print head, or may include a number of printheads. In examples, the print component <NUM> may be removable and replaceable in a printing system. The print component may be a refillable device, and may include a tank, chamber, or container for fluid, such as ink. The print component may include a replaceable container for fluid.

In one example, print component <NUM> includes a fluid ejection circuit <NUM>, a memory circuit <NUM>, and a number of input/output (I/O) pads <NUM>. Fluid ejection circuit ejection circuit <NUM> includes an array <NUM> of fluid actuators <NUM>. In examples, fluid actuators <NUM> may be arranged to form a number of primitives, with each primitive having a number of fluid actuators <NUM>. A portion of fluid actuators <NUM> may be arranged as part of a nozzle for fluid ejection, and another portion arranged as part of a pump for fluid circulation. In one example, fluidic ejection circuit <NUM> comprises a die.

In one example, I/O pads <NUM> of memory circuit <NUM> include CLK Pad <NUM>, DATA Pad <NUM>, FIRE Pad <NUM>, MODE Pad <NUM>, and Analog Pad <NUM> which connect to a plurality of signal paths which convey a number of digital and analog operating signals for operating fluidic ejection circuit <NUM> between print component <NUM> and a separate device, such as a printer <NUM>. CLK pad <NUM> may convey a clock signal, DATA pad <NUM> may convey data including configuration data and selection data, including in the form of fire pulse group (FPG) data packets, FIRE pad may communicate a fire signal, such as a fire pulse, to initiate an operation of fluidic ejection circuit <NUM> (such as, for example, operation of selected fluid actuators <NUM>), MODE pad <NUM> may indicate different modes of operation of fluidic ejection circuit <NUM>, and SENSE pad <NUM> may convey analog electrical signals for sensing and operation of sensing elements fluidic ejection circuit <NUM> (such as, for example, crack sensors, thermal sensors, heaters) and memory elements of fluidic ejection circuit <NUM>, such as will be described in greater detail below.

In one example, memory values <NUM> of memory component <NUM> of memory circuit <NUM> are memory values associated with print component <NUM>, including memory values associated with the operation of fluid ejection circuit <NUM>, such as a number of a nozzles, ink levels, operating temperatures, manufacturing information, for example. In examples, similar to that described above, upon observing a sequence of operating signals representing a memory read (e.g., a "read" protocol), control circuit <NUM> provides an analog electrical signal to Analog Pad <NUM> to provide an analog electrical value at Analog Pad <NUM> representing the stored memory values <NUM> selected by the memory read.

In an example where fluid ejection circuit <NUM> is implemented as a fluidic die, by disposing memory circuit <NUM> separately from fluidic ejection circuit <NUM>, such fluidic die can be made with smaller dimensions, such that a printhead including a fluidic die <NUM> may have smaller dimensions.

In one example, fluidic ejection circuit <NUM> may include a memory array <NUM> including a number of memory elements <NUM> storing memory values associated with the operation of print component <NUM> and fluidic ejection circuit <NUM>. In one case, where memory array <NUM> includes defective memory elements <NUM>, memory circuit <NUM> may serve as a substitute memory (a replacement memory) for memory array <NUM>, with stored memory values <NUM> replacing values stored by memory elements <NUM>. In another case, memory circuit <NUM> may supplement memory array <NUM> (increase the storage capacity associated with fluidic ejection circuitry <NUM>). In one example, as will be described in greater detail below, such as when being employed to replace or substitute for a defective on-die memory array <NUM>, memory circuit <NUM> may be connected to print component <NUM> via an overlay wiring substrate (e.g., a flexible overlay) which includes pads that overlay and contact the number of I/O pads <NUM>.

<FIG> is a block and schematic diagram generally illustrating memory circuit <NUM> connected to a print component <NUM> including fluid ejection circuit <NUM> having a memory array <NUM>, and a memory circuit <NUM> (e.g., a memory die), according to one example of the present disclosure. In one case, as will be described in greater detail below, memory circuit <NUM> replaces memory array <NUM> of fluidic ejection circuit <NUM>, such as when memory array <NUM> is defective, for example.

Fluidic ejection circuit <NUM> includes array <NUM> of fluidic actuators <NUM>, and an array <NUM> of memory elements <NUM>. In one example, the array <NUM> of fluid actuators <NUM> and the array <NUM> of memory elements <NUM> are each arrayed to form a column, with each column arranged into groups referred to as primitives, with each primitive P<NUM> to PM including a number of fluid actuators, indicated as fluid actuators F<NUM> to FN, and a number of memory elements, indicated as memory elements M<NUM> to MN. Each primitive P0 to PM employs a same set of addresses, illustrated as addresses A0 to AN. In one example, each fluid actuator <NUM> has a corresponding memory element <NUM> addressable by the same address, such as fluid actuator F<NUM> and memory element M<NUM> of primitive P<NUM> each corresponding to address A<NUM>.

In one example, each fluid actuator <NUM> may have more than one corresponding memory element <NUM>, such as two corresponding memory elements <NUM>, as indicated by the dashed memory elements <NUM>, where the array <NUM> of memory elements is arranged to form two columns of memory elements <NUM>, such as columns <NUM><NUM> and <NUM><NUM>, with each additional memory element sharing the corresponding address. In other examples, each fluid actuator <NUM> may have more than two corresponding memory elements <NUM>, where each additional memory element <NUM> is arranged as part of an additional column of memory elements <NUM> of memory array <NUM>. According to one example, as will be described in greater detail below, where more than one column of memory elements <NUM> are employed such that more than one memory element <NUM> shares a same address, each column of memory elements <NUM> may be separately addressed (or accessed) using column bits in a fire pulse group data packet to identify a column to be accessed.

In one example, fluidic ejection circuit <NUM> may include a number of sensors <NUM>, illustrated as sensors S<NUM> to SX, to sense a state of fluidic ejection circuit <NUM>, such as temperature sensors and crack sensors, for example. In one example, as will be described in greater detail below, memory elements <NUM> and sensors <NUM> may be selectively coupled to sense pad <NUM>, such as via a sense line <NUM>, for access, such as by printer <NUM>. In one example, communication of information to printer <NUM>, such as measurements of cracks and temperatures in regions of fluidic ejection circuit <NUM>, and information stored by memory elements <NUM> (e.g., thermal behavior, offsets, color mapping, number of nozzles, etc.), enables computation and adjustment of instructions for operation of fluidic ejection circuit <NUM> (including fluid ejection) according to detected conditions.

In one example, fluidic ejection circuit <NUM> includes control circuit <NUM> to control the operation of the array <NUM> of fluid actuators <NUM>, the array <NUM> of memory elements <NUM>, and sensors <NUM>. In one example, control circuit <NUM> includes an address decoder/driver <NUM>, activation/selection logic <NUM>, a configuration register <NUM>, a memory configuration register <NUM>, and write circuitry <NUM>, with address decoder/driver <NUM> and activation/selection logic <NUM> being shared to control access to the array <NUM> of fluid actuators <NUM> and the array <NUM> of memory elements <NUM>.

In one example, during a fluid actuation event, control logic <NUM> receives a fire pulse group (FPG) data packet via data pad <NUM>, such as from printer <NUM>. In one case, the FPG data packet has a head portion including configuration data, such as address data, and a body portion including actuator select data, each select data bit having a select state (e.g., a "<NUM>" or a "<NUM>") and each select data bit corresponding to a different one of the primitives P<NUM> to PM. Address decoder/driver <NUM> decodes and provides the address corresponding data packet address data, such as on an address bus, for example. In one example, in response to receiving a fire pulse via fire pad <NUM> (such as from printer <NUM>), in each primitive P0 to PM, activation logic <NUM> fires (actuates) the fluid actuator corresponding to the address provided by address decoder/driver <NUM> when the corresponding select bit is set (e.g., has state of "<NUM>").

Similarly, according to examples, during a memory access operation, control logic <NUM> receives a fire pulse group (FPG) data packet via data pad <NUM>, such as from printer <NUM>. However, rather than including actuator select data, during a memory access operation, the body portion of the FPG data packet includes memory select data, with each select data bit having a select state (e.g., "<NUM>" or "<NUM>") and corresponding and corresponding to a different one of the primitives P0 to PM. In one example, in response to receiving a fire pulse via fire pad <NUM>, in each primitive P0 to PM, activation logic <NUM> fires connects the memory element <NUM> corresponding to the address provided by address decoder/driver <NUM> to sense line <NUM> when the corresponding select bit is set (e.g., has state of "<NUM>").

In a case where the memory access operation is a "read" operation, an analog response of the memory element <NUM> (or elements <NUM>) connected to sense line <NUM> to an analog sense signal (e.g., a sense current signal or a sense voltage signal) provided on sense line <NUM>, such as by printer <NUM> via sense pad <NUM>, is indicative of a state of the memory element <NUM> (or elements). In a case where the memory access operation is a "write" operation, memory elements <NUM> connected to sense line <NUM> may be programmed to a set state (e.g., to a "<NUM>" from a "<NUM>") by an analog program signal provided on sense line <NUM>, such as by printer <NUM> via sense pad <NUM>, or by a write circuit <NUM> integral with fluidic ejection circuit <NUM>.

During a read operation, a single memory element <NUM> may be connected to sense line <NUM> and be read, or a combination (or subset) of memory elements <NUM> may be connected in parallel to sense line <NUM> and be read simultaneously based on an expected analog response to an analog sense signal. In examples, each memory element <NUM> may have known electrical characteristics when in a programmed state (e.g., set to a value of "<NUM>") and an unprogrammed state (e.g., having a value of "<NUM>"). For example, in one case, memory elements <NUM> may be floating gate metal-oxide semiconductor field-effect transistors (MOSTFETs) having a relatively high resistance when unprogrammed, and a relatively lower resistance when programmed. Such electrical properties enable known responses to known sense signals to be indicative of a memory state of the memory element <NUM> (or elements), during a read operation.

For example, if a fixed sense current is applied to sense line <NUM>, a voltage response may be measured that is indicative of a memory state of a selected memory element <NUM>, or memory elements <NUM>. When more than one memory element <NUM> is connected in parallel to sense line <NUM>, each additional memory element reduces the resistance, which reduces a sense voltage response at sense pad <NUM> by a predictable amount. As such, information (e.g., program state) may be determined about the combination of selected memory elements <NUM> based on the measured sense voltage. In examples, a current source internal to fluidic ejection circuit <NUM> may be used to apply the sense current. In other examples, a current source external to fluidic ejection circuit <NUM> (e.g., printer <NUM> via sense pad <NUM>) may be used.

In a corresponding way, if a fixed sense voltage is applied a current response may be measured that is indicative of a memory state of a selected memory element <NUM> (or memory elements <NUM>). When more than one memory element <NUM> is connected in parallel to sense line <NUM>, each additional memory element <NUM> reduces the resistance, which increases a sense current at sense pad <NUM> by a predictable amount. As such, information (e.g., program state) may be determined about the combination of selected memory elements <NUM> based on the measured sense current. In examples, a voltage source internal to fluidic ejection circuit <NUM> may be used to apply the sense voltage. In other examples, a voltage source external to fluidic ejection circuit <NUM> (e.g., printer <NUM> via sense pad <NUM>) may be used.

In one case, to enable fluidic ejection circuit <NUM> to identify a memory access operation so that information is not inadvertently written to memory array <NUM> during other operations, such as a fluid actuation operation, a unique memory access protocol is used which includes a specific sequence of operating signals received via I/O pads <NUM>. In one example, the memory access protocol begins with DATA pad <NUM> being raised (e.g., raised to a relatively higher voltage). With DATA pad <NUM> still being raised, MODE pad <NUM> is raised (e.g., a mode signal on MODE pad <NUM> is raised). With the DATA pad <NUM> and Mode pad <NUM> raised, control logic <NUM> recognizes that an access of configuration register <NUM> is to occur. A number of data bits are then shifted into configuration register <NUM> from DATA pad <NUM> with a clock signal on CLK pad <NUM>. In one example, configuration register <NUM> holds a number of bits, such as <NUM> bits, for example. In other examples, configuration register <NUM> may include more than or few than <NUM> bits. In one example, one of the bits in control register <NUM> is a memory access bit.

A FPG data packet is then received via DATA pad <NUM>, with the select bits in the body portion of the data packs representing memory element <NUM> select bits. In one example, the FPG data packet further includes a configuration bit (e.g., in a head or tail portion of the data packet) that, when set, indicates that the FPG is a memory access FPG. When control logic <NUM> recognizes that both the memory enable bit in configuration register <NUM> and the memory access configuration data bit in the received FPG packet are "set", control logic <NUM> enables memory configuration registration (MCR) <NUM> to receive data via Data pad <NUM> in a fashion similar to which configuration register <NUM> received data bits (as described above). According to one example, upon recognizing that both the memory enable bit in configuration register <NUM> and the memory access configuration data bit in the received FPG packet are "set", a number of data bits are shifted into memory configuration register <NUM> from DATA pad <NUM>, including a column enable bit to enable a column <NUM> of memory bits to be accessed, and a read/write enable bit indicating whether the memory access is a read or a write access (e.g., a "<NUM>" indicating a memory read and a "<NUM>" indicating a memory write). In one example, where fluidic ejection circuit <NUM> has a memory array <NUM> having more than one column of memory elements <NUM>, such as columns <NUM><NUM> and <NUM><NUM>, configuration data of the FPG data packet communicating the memory select data includes column selection bits to identify which column <NUM> of data elements is being accessed. The column enable bit of memory configuration register <NUM> and the column selection bit of the FPG data packet together enable the selected column <NUM> to be accessed for a memory operation.

After loading data into memory configuration register <NUM>, the fire pulse on FIRE pad <NUM> is raised, and each memory element <NUM> corresponding to the address represented in the header of the FPG and having a corresponding memory select bit in the body portion of the FPG which is set (e.g., having a value of "<NUM>") is connected to sense bus <NUM> for a read or a write access, as indicated by the state of the read/write bit of the memory configuration register.

In one example, a read operation of a crack sensor <NUM> of fluid ejection circuit <NUM> has a protocol similar to that of a read operation of memory elements <NUM>. Data pad <NUM> is raised, followed by the mode signal on MODE pad <NUM> being raised. A number of data bits are then shifted into configuration registration <NUM>. However, in lieu of a configuration data bit corresponding to a read operation of a memory element <NUM> being set in configuration register <NUM>, a configuration data bit corresponding to a read operation of a crack sensor <NUM> is set. After data has been shifted into configuration register <NUM>, a FPG is received by control logic <NUM>, where all data bits of the body portion of the FPG have a non-select value (e.g. a value of "<NUM>"). The fire pulse signal on FIRE pad <NUM> is then raised, and the crack sensor <NUM> is connected to sense line <NUM>. An analog response of crack sensor <NUM> to an analog sense signal on sense line <NUM> is indicative of whether crack sensor <NUM> is detecting a crack (e.g., an analog voltage sense signal produces an analog response current signal, and an analog current sense signal produces an analog response voltage signal).

In one example, a read operation of a thermal sensor <NUM> is carried out during a fluid ejection operation. In one case, a configuration data bit corresponding to a particular thermal sensor is set in a head or tail portion of the FPG data packet, while the body portion of the FPG includes actuator select data bits, one for each primitive P<NUM> to PM, and having a state indicative of which fluid actuators <NUM> are to be actuated. When the fire pulse signal on FIRE pad <NUM> is raised, the selected fluid actuators <NUM> are fired, and the selected thermal sensor (e.g., a thermal diode) is connected to sense line <NUM>. An analog sense signal applied to the selected thermal sensor via sense line <NUM> results in an analog response signal on sense line <NUM> indicative of the temperature of the thermal sensor.

In one example, where memory array <NUM> of fluidic ejection circuit <NUM> may include defective memory elements <NUM> storing incorrect memory values, memory circuit <NUM> may be connected in parallel with fluidic ejection circuitry <NUM> to I/O terminals <NUM> with the memory values <NUM> of memory component <NUM> to serve as a replacement memory for memory array <NUM> and to store correct memory values. In one example, control circuit <NUM> monitors the operating signals received via I/O pads <NUM>. In one case, upon recognizing a memory access sequence, such as described above, control circuit <NUM> checks the status of the read/write bit provided to memory configuration register <NUM> via DATA pad <NUM>.

In one example, where the memory access is a "write" operation, control circuit <NUM> checks the state of the memory select bits in the body portion of the FPG received via DATA pad <NUM> to determine which memory elements <NUM> are indicated as being programmed (e.g., have corresponding select bit which is set (e.g., has a value of "<NUM>"). Control circuit <NUM> then updates the corresponding memory values <NUM> of memory component <NUM> to reflect any changes in memory values <NUM> due to the write operation.

In one example, where the memory access is a "read" operation, control circuit <NUM> checks the state of the memory select bits in the body portion of the FPG received via DATA pad <NUM> to determine which memory elements <NUM> are indicated as being programmed. Control circuit <NUM> then checks the corresponding memory values <NUM> in memory component <NUM> and determines the type of analog sense signal present SENSE pad <NUM>. In one example, in response to the detected analog sense signal, and based on the memory values to be read, control circuit <NUM> drives an analog response signal on sense line <NUM> and SENSE pad <NUM> indicative of the values of memory values <NUM>.

For example, in a case where an analog sense current is provided on sense line <NUM> via SENSE pad <NUM>, such as by printer <NUM>, and a single memory value is being read, control circuit provides an analog voltage response on sense line <NUM> which is indicative of the value of the signal memory value being read. For example, if a single memory value is being read, the analog voltage response provided on sense line <NUM> by control circuit <NUM> may be a relatively high voltage for an unprogrammed memory value, and may be a relatively lower voltage for a programed memory value. In one example, control circuit <NUM> provides the analog voltage response on sense line <NUM> having a value equal to an expected response in view of the known characteristics of memory elements <NUM>, the number of memory elements <NUM> being read in parallel, and the analog sense signal.

By monitoring operating signals on I/O pads <NUM> to identify memory access operation (e.g., read/write operations) in order to maintain and update memory values <NUM>, and to provide expected analog response signals on sense line <NUM> in response to memory read operations, memory circuit <NUM> is indistinguishable from memory array <NUM> of fluidic ejection circuit <NUM> to a device accessing print component <NUM>, such as printer <NUM>.

<FIG> is a block and schematic diagram illustrating memory circuit <NUM> connected to print component <NUM>, according to one example. In the example of <FIG>, print component <NUM> includes a number of fluid ejection circuits <NUM>, illustrated as fluidic ejection circuits <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM>, each including an array of fluid actuators <NUM>, illustrated as actuator arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, and <NUM>, and each including a memory array <NUM>, illustrated as memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM>. In one example, each fluidic ejection circuit <NUM> comprises a separate fluidic ejection die, with each die providing a different color ink. For example, fluidic ejection die <NUM><NUM> may be a cyan die, fluidic ejection die <NUM><NUM> may be a magenta die, fluidic ejection die <NUM><NUM> may be a yellow die, and fluidic ejection die <NUM> may be a black die. In example, fluidic ejection dies <NUM><NUM>, <NUM><NUM> and <NUM><NUM> are arranged as part of a color print pen <NUM>, and fluid ejection die <NUM> is arranged as a part of a monochromatic print pen <NUM>.

In one example, each fluidic ejection die <NUM><NUM> to <NUM><NUM> receives data from a corresponding one of data pads <NUM><NUM> to <NUM>, and each share CLK Pad <NUM>, FIRE pad <NUM>, MODE pad <NUM>, and SENSE pad <NUM>. In examples, each of the memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> may be separately accessed during a memory access operation. In other examples, any combination of memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> may be simultaneously accessed during a memory access operation. For example, memory elements from each of the memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> may be simultaneously accessed (e.g., a read operation) via sense line <NUM>, such as by printer <NUM>.

Memory circuit <NUM> is connected to CLK pad <NUM>, FIRE pad <NUM>, MODE pad <NUM>, and SENSE pad <NUM>, and is connected to each of data pads <NUM><NUM> to <NUM><NUM> so as to be connected in parallel with each of the fluidic ejection dies <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM>. In examples, memory circuit <NUM> may serve as a replacement memory for any combination of memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM>. For example, in one case, memory circuit <NUM> may serve as a replacement memory for memory array <NUM><NUM>, whereas in another example, memory circuit <NUM> may serve as a replacement for each of the memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM>.

In one example, memory circuit <NUM> may serve as supplemental memory for a fluidic ejection circuit <NUM>. In such case, for memory access operations, memory elements <NUM> of the fluidic ejection circuit <NUM> and memory values <NUM> of memory circuit <NUM> may be separately identified using column selection bits in the configuration data of FPG data packets communicating memory select data. For example, fluidic ejection circuit <NUM> of monochromatic print pen <NUM> may include a memory array <NUM><NUM> having a number of columns of memory elements <NUM>, such as three columns, for instance. In such case, the columns of memory elements of fluidic ejection circuit <NUM> may be identified by column selection bits of configuration data of the FPG data packet as columns <NUM>-<NUM>, and additional columns of memory values <NUM> of memory component <NUM> acting as supplemental memory may be identified as additional columns beginning with column <NUM>.

In one example, similar to that described above with respect to <FIG>, memory circuit <NUM> monitors operating signals on the number I/O pads <NUM> to detect a memory access sequence for any of the memory arrays <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> for which memory circuit <NUM> serves as a replacement memory.

In one example, when memory circuit <NUM> serves as a replacement memory for less than all of the fluidic ejection dies <NUM><NUM>, <NUM><NUM>, <NUM><NUM> and <NUM><NUM> of print component <NUM>, memory elements <NUM> of fluidic ejection dies <NUM> for which memory circuit <NUM> does not serve as a replacement memory are unable to read in parallel with memory elements of fluidic ejection dies <NUM> for which memory circuit serves as a replacement memory.

<FIG> is a block and schematic diagram generally illustrating memory circuit <NUM> connected to print component <NUM>, according to one example, where portions of print component <NUM> are also shown. As will be described in greater detail below, according to the example of <FIG>, memory circuit <NUM> is connected in parallel with fluidic ejection device <NUM> to SENSE pad <NUM> during memory access operations. In example, according to the illustration of <FIG>, memory circuit <NUM> may serve as a replacement memory for the array <NUM> of memory elements <NUM> of fluidic ejection circuit <NUM> (where one or more memory elements <NUM> may be defective).

In one example, activation logic <NUM> of fluid ejection circuit <NUM> includes a read enable switch <NUM>, a column activation switch <NUM> controlled via an AND-gate <NUM>, and a memory element select switch <NUM> controlled via an AND-gate <NUM>. According to one example, as described above, during a read operation, fluidic ejection circuit <NUM> receives a fire pulse group including configuration data (e.g., in a head and/or tail portion), and memory select data (e.g., in a body portion). In one example, the configuration data includes a column select bit and address data. The column select bit indicates a particular column of memory elements <NUM> being accessed when memory array <NUM> includes more than one column of memory elements, such as columns <NUM><NUM> and <NUM><NUM> in <FIG>. The address data is decoded by address decoder <NUM> and provided to activation circuit <NUM>. In one example, the select data includes a number of memory select bits, where each select data bit corresponds to a different primitive (P<NUM> to PM) of the column of memory elements <NUM>, where a select bit which is set (e.g., has a value of "<NUM>") enables memory elements <NUM> of the column <NUM> to be accessed for reading (or writing).

Additionally, as part of the read operation protocol, memory configuration register <NUM> is loaded with a column enable bit and a read enable bit. The read enable bit of memory configuration register <NUM> turns on read enable switch <NUM>. When FIRE is raised, the column enable bit of configuration register <NUM> together with the column select bit of the configuration data of the fire pulse group cause AND-gate <NUM> to turn on column activation switch <NUM> for the selected column, and the select data and address (via address decoder <NUM>) of the fire pulse group, and FIRE signal together cause AND-gate <NUM> to turn on memory element select switch <NUM>, thereby connecting memory element <NUM> to sense line <NUM>. It is noted that, in some examples, a column select bit may not be included as part of the fire pulse group configuration data when fluidic ejection circuit <NUM> includes a single column of memory elements.

Once connected to sense line <NUM>, memory element <NUM> provides an analog output signal in response to an analog sense signal on sense line <NUM>, where a value of the analog output signal depends on a program state of memory element (where such program state may be defective). In one example, as described above, memory element <NUM> may have a relatively higher electrical resistance when having a non-programmed state (e.g., a value of "<NUM>") than when having a programmed state (e.g., a value of "<NUM>"). Accordingly, when the analog sense signal is a fixed analog current (a so-called "forced current mode"), an analog output voltage provided by memory element <NUM> will have a relatively higher voltage level when memory element <NUM> has a non-programmed state, and a relatively lower voltage level when memory element <NUM> has a programmed state. Likewise, when the analog sense signal is a fixed voltage (a so-called "forced voltage mode"), an analog output current provided by memory element <NUM> will have a relatively lower current level when memory element <NUM> has a non-programmed state, and a relatively higher current level when memory element <NUM> has a programmed state.

It is noted that during a write operation, read enable switch <NUM> is maintained in an open position to disconnect memory element <NUM> from sense line <NUM>, while column enable switch <NUM> and memory element select switch <NUM> are closed. The write enable bit of memory configuration register connects voltage regulator <NUM> to memory element <NUM> to apply a program voltage thereto.

Control circuit <NUM> of memory circuit <NUM>, according to one example, includes control logic <NUM>, a first voltage-controlled current source <NUM> operating as a current supply to a node <NUM>, and a second voltage controlled current source operating as a current sink from node <NUM>, with node <NUM> being connected to sense line <NUM> at second SENSE pad <NUM><NUM> via a control line <NUM>. In the example of <FIG>, during a memory access operation, memory circuit <NUM> is connected to sense line <NUM> in parallel with fluidic ejection circuit <NUM> at second SENSE pad <NUM><NUM>.

In one example, memory circuit <NUM> is connected in parallel with fluid ejection circuit <NUM> to I/O pads <NUM> via an overlay wiring substrate <NUM>, which is described in greater detail below (e.g., see <FIG>). In one example, wiring substrate <NUM> includes a pair of I/O pads for each signal path, with the signal path routed through overlay wiring substrate <NUM> to print component <NUM> from the first I/O pad of the pair to the second I/O pad of the pair. For example, wiring substrate <NUM> includes a pair of CLK pads <NUM> and <NUM><NUM>, a pair of DATA Pads <NUM> and <NUM><NUM>, a pair of FIRE Pads <NUM> and <NUM><NUM>, a pair of MODE Pads <NUM> and <NUM><NUM>, and a pair of SENSE Pads <NUM> and <NUM><NUM>. In one example, in each case, the first pad of the pair of pads connects to the incoming signal line, and the second pad of the pair of pads connects the outgoing signal line to print component <NUM>.

In one example, overlay wiring substrate <NUM> further includes a sense resistor <NUM> connected in series with sense line <NUM>, where control logic <NUM> monitors a voltage on high and low side terminals <NUM> and <NUM> of sense resistor <NUM>. In other examples, sense resistor <NUM> may be arranged as part of control circuit <NUM> (e.g., see <FIG>).

Although illustrated as being connected to the signal paths and print component <NUM> via wiring substrate <NUM>, any number of other implementations may be employed to provide such connection. For instance, in one example, the functionality of wiring substrate <NUM> may integrated within memory circuit <NUM>.

Memory component <NUM> includes a number of memory values <NUM>. In one example, each memory value <NUM> corresponds to a different one of the memory elements <NUM> of fluidic ejection circuit <NUM>. However, whereas one or more memory elements <NUM> of fluidic ejection circuit <NUM> may be defective and store incorrect values, each of the memory values <NUM> of memory component <NUM> represents a correct memory value. It is noted that in examples, memory component <NUM> may include memory values <NUM> in addition to memory values <NUM> corresponding to memory elements <NUM>.

In one example, control circuit <NUM> monitors the operating signals being communicated to fluidic ejection circuit <NUM> on I/O pads <NUM>, such as from printer <NUM>. In one example, upon detecting operating signals representing a memory access sequence indicative of a read operation of memory element <NUM>, control logic <NUM> monitors the voltage on high-side terminal <NUM> (or low-side terminal <NUM>) of sense resistor <NUM> to determine whether the read operation is being performed in a forced current mode or a forced voltage mode. If a forced current mode is being employed, the voltage level on high-side terminal <NUM> will rise (e.g., a linear rise) for a time period following FIRE pad <NUM> being raised as sense line <NUM> charges. If a forced voltage mode is being employed, the voltage on high-side terminal <NUM> will remain relatively steady at the fixed voltage level of the input sense signal.

In one example, upon detecting a read operation, control logic <NUM> reads the memory value <NUM> corresponding to the memory element <NUM> identified as being accessed by the read operation. Based on the memory value <NUM>, control logic <NUM> is able to determine an expected output response voltage level that should be present on SENSE pad <NUM> during a forced current mode read operation, and an expected output response current level that should be present on SENSE pad <NUM> during forced voltage mode read operation via a feedback loop formed with sense resistor <NUM>.

Since memory circuit <NUM> is connected in parallel with fluidic ejection circuit <NUM> to sense line <NUM>, during a read operation, in response to the analog sense signal being forced on sense line <NUM>, an analog output response signal (e.g., a voltage or a current) from memory element <NUM> is present at second SENSE pad <NUM><NUM>. In one example, control logic <NUM> adjusts the voltage controlled current sources <NUM> and <NUM> to provide current to second SENSE pad <NUM><NUM> or to draw current from second sense pad <NUM><NUM> so that the combination of the output response from memory element <NUM> of fluidic ejection circuit <NUM> and the output response of control circuit <NUM> at second SENSE Pad <NUM> produces the expected analog output response level (voltage or current) at SENSE pad <NUM>.

In one example, when in forced current mode, control logic <NUM> monitors the voltage at high-side terminal <NUM> of sense resistor <NUM> and adjusts voltage controlled current sources <NUM> and <NUM> to adjust an amount of current provided to second SENSE pad <NUM><NUM> (either providing current to second SENSE pad <NUM><NUM> or drawing current from second SENSE pad <NUM><NUM>) so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response voltage level at SENSE pad <NUM>.

Similarly, in one example, when in forced voltage mode, control logic monitors the voltage across sensor resistor <NUM> via high-side and low-side terminals <NUM> and <NUM> to determine the output response current level at SENSE pad <NUM>. Control circuit <NUM> then adjusts voltage controlled current sources <NUM> and <NUM> to adjust the amount of current provided to second SENSE pad <NUM><NUM> (either providing current to second SENSE pad <NUM><NUM> or drawing current from second SENSE pad <NUM><NUM>) so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response current level at SENSE pad <NUM>.

By controlling voltage-controlled current sources <NUM> and <NUM> to provide an expected analog output response value at SENSE pad <NUM> based on the correct memory values for fluidic ejection circuit <NUM> as stored as memory values <NUM> by memory component <NUM>, memory circuit <NUM> is able to replace a defective memory array <NUM> on fluidic ejection circuit <NUM> so that print component <NUM> is able to remain operational, thereby reducing the number of defective print components during manufacturing. Additionally, by connecting memory circuit <NUM> in parallel with fluidic ejection circuit to I/O pads <NUM>, sensors <NUM> of fluidic ejection circuit <NUM> remain accessible at all times for monitoring via SENSE pad <NUM>, such as by printer <NUM>.

<FIG> is a cross-sectional view illustrating portions of an overlay wiring substrate <NUM> for connecting memory circuit <NUM> to I/O terminals <NUM>. In particular, <FIG> represents a cross-sectional view extending through SENSE pad <NUM> of <FIG>, where memory circuit <NUM> is coupled in parallel with fluidic ejection circuit <NUM> to sense pad <NUM>. In one example, overlay wiring substrate <NUM> includes a flexible substrate <NUM> having a first surface <NUM> and an opposing second surface <NUM>. Memory circuit <NUM> and SENSE pad <NUM> are disposed on first surface <NUM>, with a conductive trace representing sense line <NUM> connecting SENSE pad <NUM> to memory circuit <NUM>. In one example, as illustrated, sense resistor <NUM> in disposed in series with sense line <NUM> between SENSE pad <NUM> and memory circuit <NUM>. In one example, a conductive via <NUM> extends from sense line <NUM> at first surface <NUM> through flexible substrate <NUM> to second SENSE pad <NUM><NUM> on second surface <NUM>.

Print component <NUM> includes a substrate <NUM> on which fluidic ejection circuit <NUM> is mounted, and includes a SENSE pad <NUM><NUM> coupled to fluidic ejection circuit <NUM> by a sense line <NUM><NUM>. When flexible wiring substrate <NUM> is coupled to print component <NUM>, as indicated by the directional arrow <NUM>, second SENSE pad <NUM><NUM> aligns with SENSE pad <NUM><NUM> to connect sense line <NUM> to SENSE pad <NUM><NUM> between sense resistor <NUM> and memory circuit <NUM>.

<FIG> is a block diagram generally illustrating a cross-sectional view of overlay wiring substrate <NUM> showing connections of I/O pads <NUM> other than SENSE pad <NUM>, for example, such as MODE pad <NUM>, for instance. As illustrated, MODE pad <NUM> is disposed on top surface <NUM> of substrate <NUM>. A via <NUM> extends through substrate <NUM> to connect first MODE pad <NUM> to second MODE pad <NUM><NUM> on second surface <NUM>. When flexible wiring substrate <NUM> is coupled to print component <NUM>, MODE pad <NUM><NUM> aligns with MODE pad <NUM><NUM> to connect MODE pad <NUM> to fluidic ejection circuit <NUM>.

<FIG> is a block and schematic diagram generally illustrating memory circuit <NUM>, according to one example. Portions of print component <NUM> are also generally illustrated. The example of <FIG> is similar to that of <FIG>, where memory circuit <NUM> is connected in parallel with fluidic ejection device <NUM> to SENSE pad <NUM> during memory access operations. However, in the example of <FIG>, control circuit <NUM> of memory circuit <NUM> includes an op-amp <NUM> and a controllable voltage source <NUM> in lieu of voltage-controlled current sources <NUM> and <NUM>.

A first input of op-amp <NUM> is connected to a reference potential (e.g., ground) via controllable voltage source <NUM>. A second input and an output of op-amp <NUM> are connected to node <NUM>, with node <NUM> being connected to SENSE pad <NUM><NUM> via line <NUM>.

In one example, during a memory read operation, when in forced current mode, control logic <NUM> monitors the voltage at high-side terminal <NUM> of sense resistor <NUM> and adjusts the output voltage of op-amp <NUM> by adjusting the voltage level of controllable voltage source <NUM> (where the output voltage approximately follows that of controllable voltage source <NUM>), so as to adjust an amount of current provided to second SENSE pad <NUM><NUM> (either providing current to second SENSE pad <NUM><NUM> or drawing current from second SENSE pad <NUM><NUM>) so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response voltage level at SENSE pad <NUM>.

Similarly, in one example, when in forced voltage mode, control logic monitors the voltage across sensor resistor <NUM> via high-side and low-side terminals <NUM> and <NUM> to determine the output response current level at SENSE pad <NUM>. Control circuit <NUM> then adjusts the output voltage of op-amp <NUM> by adjusting the voltage level of controllable voltage source <NUM> (where the output voltage approximately follows that of controllable voltage source <NUM>), so as to adjust the amount of current provided to second SENSE pad <NUM><NUM> (either providing current to second SENSE pad <NUM><NUM> or drawing current from second SENSE pad <NUM><NUM>) so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response current level at SENSE pad <NUM>.

<FIG> is a block and schematic diagram of memory circuit <NUM> for print component <NUM>, according to one example. The example of <FIG> is similar to that of <FIG>, where memory circuit <NUM> is connected in parallel with fluidic ejection device <NUM> to SENSE pad <NUM> during memory access operations. However, in the example of <FIG>, control circuit <NUM> of memory circuit <NUM> includes a number of resistors <NUM>-<NUM> which may be connected to form an adjustable voltage divider between voltage source VCC and a reference voltage (e.g., ground) in lieu of voltage-controlled current sources <NUM> and <NUM>.

In example, a source resistor <NUM> is connected between voltage source VCC and node <NUM>. Sink resistors <NUM>-<NUM> are connected in parallel with one another between node <NUM> and a reference voltage (e.g., ground) via respective switches <NUM>-<NUM>. It is noted that a number of resistors different from that illustrated in <FIG> may be employed by control circuit <NUM>.

In one example, during a memory read operation, when in forced current mode, control logic <NUM> monitors the voltage at high-side terminal <NUM> of sense resistor <NUM> and adjusts the number of sink resistors <NUM>-<NUM> which are connected between node <NUM> and ground via control of switches <NUM>-<NUM> to adjust an amount of current provided to second SENSE pad <NUM><NUM> so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response voltage level at SENSE pad <NUM>.

Similarly, in one example, when in forced voltage mode, control logic monitors the voltage across sensor resistor <NUM> via high-side and low-side terminals <NUM> and <NUM> to determine the output response current level at SENSE pad <NUM>. Control circuit <NUM> then adjusts the number of sink resistors <NUM>-<NUM> which are connected between node <NUM> and ground via control of switches <NUM>-<NUM> to adjust the amount of current provided to second SENSE pad <NUM><NUM> (either providing current to second SENSE pad <NUM><NUM> or drawing current from second SENSE pad <NUM><NUM>) so that the combined response of memory circuit <NUM> and fluidic ejection circuit <NUM> provides the expected output response current level at SENSE pad <NUM>.

<FIG> is a block and schematic diagram generally illustrating memory circuit <NUM>, according to one example. Memory circuit <NUM> includes a plurality of I/O pads <NUM>, including an analog pad <NUM> , to connect to a plurality of signal paths <NUM> communicating operating signals to print component <NUM>. In one example, a controllable selector <NUM> is connected in-line with one of the signal paths <NUM> via the I/O pads <NUM>, with the controllable selector <NUM> controllable to open the corresponding signal line to the print component <NUM> (to interrupt or break the connection to print component <NUM>). In one example, in response to a sequence of operating signals received by I/O pads <NUM> representing a memory read, control circuit <NUM> opens controllable selector <NUM> to break the signal path to print component <NUM> to block a memory read of print component <NUM>, and provides an analog signal to analog pad <NUM> to provide an analog electrical value at analog pad <NUM> representing stored memory values <NUM> selected by the memory read. By breaking the signal path during a memory read, print component <NUM> is unable to provide an analog signal to analog pad <NUM> during memory read operations. In examples, print component <NUM> is enabled to provide an analog signal pad <NUM> during non-memory read functions which access analog pad <NUM>, such as a read of an analog component. In examples, such analog component may be a sense circuit (e.g., a thermal sensor).

<FIG> is a block and schematic diagram illustrating memory circuit <NUM>, according to one example of the present disclosure, where controllable selector <NUM> is a controllable switch <NUM>. In the example of <FIG>, I/O pads <NUM> include a first analog pad <NUM> and a second analog pad <NUM><NUM> connected to an analog signal line <NUM>, where controllable switch <NUM> is connect between analog pads <NUM> and <NUM><NUM> so as to be connected in-line with analog signal line <NUM>. In one example, as illustrated, control circuit <NUM> further includes a second controllable switch <NUM> connected to first analog pad <NUM>. The example of <FIG> is similar to that of <FIG>, except controllable selector switches <NUM> and <NUM> enable control circuit <NUM> to selectively couple and decouple memory circuit <NUM> and fluidic ejection circuit <NUM> from select line <NUM> such that, in one example, memory circuit <NUM> is not coupled in parallel with fluidic ejection circuit <NUM> during a memory access operation. Additionally, according to one example, sense resistor <NUM> along with high-side and low-side terminals <NUM> and <NUM> are disposed within memory circuit <NUM>.

In one example, when control logic <NUM> identifies a non-memory access operation, control logic opens controllable selector switch <NUM> to disconnect voltage-controlled current sources <NUM> and <NUM> from sense line <NUM>, and close selector switch <NUM> to connect fluid ejection circuit <NUM> to sense line <NUM>, to enable monitoring of sensors <NUM> (see <FIG>), such as by printer <NUM>, without potential for interference in output signals of sensors <NUM> by control circuit <NUM>.

In one example, when control logic <NUM> identifies a memory access operation, control logic may close selector switch <NUM> to connect node <NUM> and voltage-controlled current sources <NUM> and <NUM> to sense line <NUM>, and open selector switch <NUM> to disconnect fluidic ejection circuit <NUM> from sense line <NUM>, so that fluidic ejection circuit <NUM> is no longer connected in parallel with control circuit <NUM> to second SENSE pad <NUM><NUM>, so that fluidic ejection circuit <NUM> is blocked from responding to a memory read operation. Control circuit <NUM> can then adjust voltage controlled current sources <NUM> and <NUM> to provide the expected analog voltage response at SENSE pad <NUM>, as described above with respect to <FIG>, but without the contribution of an analog output response signal from fluidic ejection circuit <NUM>. By disconnecting fluidic ejection circuit <NUM> from sense line <NUM> during memory access operations, potential contamination from defective memory elements <NUM> in the analog output response signal at SENSE pad <NUM> can be eliminated.

In other examples, controllable selector switch <NUM> may be connected in a similar fashion so as to be in-line with a fire signal path via FIRE pad, such that a fire signal is blocked from fluidic ejection circuit <NUM> during a memory read operation so that fluidic ejection circuit <NUM> is unable to respond to such memory read operation. In another example, controllable selector <NUM> may be a multiplexer coupled in-line with sense line <NUM> (or analog path <NUM>), where the control circuit <NUM> operates the multiplexer operates to disconnect sense line <NUM> from fluidic ejection circuit <NUM> during a memory read, and otherwise operates to connect sense line <NUM> to fluid ejection circuit <NUM>, such as during non-memory read operations which access analog sense pad <NUM> and sense line <NUM>.

It is noted that the configurations of control circuit <NUM> described by <FIG> and <FIG>, and any number of other suitable control configurations, may be employed in the example print component <NUM> of <FIG>.

<FIG> is a cross-sectional view illustrating portions of overlay wiring substrate <NUM> for connecting memory circuit <NUM> to I/O terminals <NUM> as illustrated by <FIG>, according to one example. In particular, <FIG> represents a cross-sectional view extending through SENSE pad <NUM>. In one example, memory circuit <NUM> and SENSE pad <NUM> are disposed on first surface <NUM> of flexible substrate <NUM>, with a conductive trace representing sense line <NUM> connecting SENSE pad <NUM> to memory circuit <NUM>. According to one example, sense resistor <NUM> and selector switches <NUM> and <NUM> are disposed internally to memory circuit <NUM>. A conductive via <NUM> extends through flexible substrate <NUM>, with memory circuit <NUM> being electrically connected to a SENSE pad <NUM><NUM> on second surface <NUM> of flexible substrate <NUM> with conductive traces <NUM><NUM> and <NUM><NUM> (representing portions of sense line <NUM>) by way of via <NUM>. When flexible wiring substrate <NUM> is coupled to print component <NUM>, as indicated by arrow <NUM>, sense pad <NUM><NUM> aligns with sense pad <NUM><NUM> such that SENSE pad <NUM> is coupled to fluidic ejection circuit <NUM> via selector switch <NUM> in memory circuit <NUM>.

<FIG> is a block and schematic diagram generally illustrating memory circuit <NUM>, according to one example. Memory circuit <NUM> includes a plurality of I/O pads <NUM>, including first and second analog pads <NUM> and <NUM>, indicated at <NUM> and <NUM><NUM>, to connect a plurality of signal paths <NUM> to print component <NUM>, including an analog signal path <NUM> connected to Analog Pads <NUM> and <NUM><NUM>. In one example, the first analog pad <NUM> is electrically isolated from the second analog pad <NUM><NUM> to break the analog signal path to print component <NUM>. In response to a sequence of operating signals on I/O pads <NUM> representing a memory read, control circuit <NUM> provides an analog signal to first analog pad <NUM> to provide an analog electrical value at first analog pad <NUM> representing stored memory values <NUM> selected by the memory read.

By breaking the analog signal path <NUM> during a memory read, print component <NUM> is disconnected from analog signal path <NUM> during memory read operations. As will be described in greater detail below, in addition to providing memory values <NUM> corresponding to memory elements of print component <NUM>, memory values <NUM> may represent values for other functions that access print component <NUM> via analog signal path <NUM>, such sensor read commands (e.g., to read thermal sensors).

<FIG> is a block and schematic diagram of memory circuit <NUM>, according to one example, and generally illustrating portions of print component <NUM>. The example of <FIG> is similar to that of <FIG>, but rather than including a selector switch (e.g., selector switch <NUM>) to selectively control connection of fluidic ejection circuit <NUM> to sense line <NUM>, fluidic ejection circuit <NUM> is physically decoupled from sense line <NUM>. In one example, with reference to <FIG> below, overlay wiring substrate <NUM> is arranged to connect memory circuit <NUM> to select line <NUM> and to connect memory circuit <NUM> to I/O pads <NUM>-<NUM> in parallel with fluidic ejection circuit <NUM>, while disconnecting fluidic ejection circuit <NUM> from SENSE pad <NUM>.

In one example, upon identifying a memory access operation of fluidic ejection circuit <NUM> on I/O pads <NUM>, control logic operates as described by <FIG> and <FIG> above to update memory values <NUM> in view of write operations, and to provide expected analog output responses at SENSE pad <NUM> in view of read commands.

However, as described earlier, SENSE pad <NUM>, via sense line <NUM>, is also employed to read sensors <NUM> (see <FIG>), such as thermal sensors and crack sensors, for example. Such sensors are read in a fashion similar to that of memory elements <NUM> of fluid ejection circuit <NUM>, where an analog sense signal is applied to a sensor and an analog response signal is indicative of a sensed temperature in the case of a temperature sensor, and indicative of a presence or absence of a crack in the case of a crack sensor. In one example, in the case of a temperature sensor, an analog output signal representative of a sensed temperature within a designated operating temperature range is indicative of proper operation of fluidic ejection circuit <NUM>, while a sensed temperature outside of the designated operating temperature range may indicate improper operation of fluidic ejection circuit <NUM> (e.g., overheating). Similarly, in the case of a crack sensor, an analog signal representative of sensed a resistance below a designated threshold value may indicate the absence of a crack in fluidic ejection circuit <NUM>, while a sensed resistance above the designated threshold value may indicate the presence of a crack in fluidic ejection circuit <NUM>.

In view of the above, in one example, in addition to memory component <NUM> including memory values <NUM> corresponding to memory elements <NUM> of fluidic ejection circuit <NUM>, memory component <NUM> includes a memory value <NUM> corresponding to each of the sensors <NUM> of fluidic ejection circuit <NUM>. In one example, the memory value <NUM> represents a value of an analog output signal to be provided by control circuit <NUM> at SENSE pad <NUM> in response to a read operation of the sensor <NUM> corresponding to the memory value <NUM> being recognized on I/O pads <NUM> by memory circuit <NUM>. In one example, control logic <NUM> controls voltage controlled current sources <NUM> and <NUM> to provide an analog output signal at SENSE pad <NUM> as indicated by the corresponding memory value <NUM>.

In view of the above, as described above, with SENSE pad <NUM> physically decoupled from fluidic ejection circuit <NUM>, memory circuit <NUM> emulates analog output signal responses for memory elements <NUM> and sensors <NUM> of fluidic ejection circuit <NUM> based on memory values <NUM> stored by memory component <NUM>. According to one example, memory circuit <NUM> of <FIG> may be mounted to print component <NUM> via flexible wiring substrate <NUM> to replace defective memory elements <NUM> and defective sensors <NUM> to maintain operation of print component <NUM>.

In one example, memory circuit <NUM> of <FIG> may be temporarily mounted to print component <NUM> via flexible wiring substrate <NUM> and serve as a diagnostic circuit for testing a response to an external circuit, such as printer <NUM>, to simulated conditions on fluidic ejection circuit <NUM>. For example, memory values <NUM> corresponding to sensors <NUM> comprising temperature sensors may have values corresponding to temperature values outside of a desired operating temperature value range to test the response of printer <NUM> to such conditions. In other examples, memory values corresponding to sensors <NUM> comprising crack sensors may have values corresponding to a resistance value above a threshold value indicative of a presence of a crack to test the response of printer <NUM> to such conditions. Any number of other conditions may be simulated by memory circuit <NUM>, thereby enabling a response of printer <NUM> to simulated operating conditions to be tested without access to fluidic ejection circuit <NUM> via sense line <NUM>. In one example, after diagnostic has been completed, memory circuit <NUM> and flexible wiring circuit <NUM> may be removed from print component <NUM>.

<FIG> is a cross-sectional view illustrating portions of overlay wiring substrate <NUM> for connecting memory circuit <NUM> to I/O terminals <NUM> as illustrated by <FIG>, according to one example. In particular, <FIG> represents a cross-sectional view extending through SENSE pad <NUM>. In one example, memory circuit <NUM> and SENSE pad <NUM> are disposed on first surface <NUM> of flexible substrate <NUM>, with a conductive trace representing sense line <NUM> connecting SENSE pad <NUM> to memory circuit <NUM>. A second SENSE pad <NUM><NUM> is disposed on second surface <NUM> of substrate <NUM>, and is electrically isolated from SENSE pad <NUM>, sense line <NUM>, and memory circuit <NUM>. A SENSE pad <NUM><NUM> is disposed on print component substrate <NUM> and is connected by conductive trace <NUM><NUM> to fluidic ejection circuit <NUM>. When flexible wiring substrate <NUM> is mounted to print component <NUM> (as indicated by direction arrow <NUM>), SENSE pad <NUM><NUM> aligns with and contacts SENSE pad <NUM><NUM>. Since SENSE pad <NUM><NUM> is electrically isolated form SENSE pad <NUM>, no electrical contact is made between SENSE pad <NUM> and underlying pad <NUM><NUM>, such that the connection between fluidic ejection circuit <NUM> and SENSE pad <NUM> is broken.

<FIG> is a block diagram illustrating one example of a fluid ejection system <NUM>. Fluid ejection system <NUM> includes a fluid ejection assembly, such as printhead assembly <NUM>, and a fluid supply assembly, such as ink supply assembly <NUM>. In the illustrated example, fluid ejection system <NUM> also includes a service station assembly <NUM>, a carriage assembly <NUM>, a print media transport assembly <NUM>, and an electronic controller <NUM>. While the following description provides examples of systems and assemblies for fluid handling with regard to ink, the disclosed systems and assemblies are also applicable to the handling of fluids other than ink.

Printhead assembly <NUM> includes at least one printhead <NUM> which ejects drops of ink or fluid through a plurality of orifices or nozzles <NUM>, where printhead <NUM> may be implemented, in one example, as fluidic ejection circuit <NUM>, with fluid actuators (FAs) <NUM> implemented as nozzles <NUM>, as previously described herein by <FIG>, for instance. In one example, the drops are directed toward a medium, such as print media <NUM>, so as to print onto print media <NUM>. In one example, print media <NUM> includes any type of suitable sheet material, such as paper, card stock, transparencies, Mylar, fabric, and the like. In another example, print media <NUM> includes media for three-dimensional (3D) printing, such as a powder bed, or media for bioprinting and/or drug discovery testing, such as a reservoir or container. In one example, nozzles <NUM> are arranged in at least one column or array such that properly sequenced ejection of ink from nozzles <NUM> causes characters, symbols, and/or other graphics or images to be printed upon print media <NUM> as printhead assembly <NUM> and print media <NUM> are moved relative to each other.

Ink supply assembly <NUM> supplies ink to printhead assembly <NUM> and includes a reservoir <NUM> for storing ink. As such, in one example, ink flows from reservoir <NUM> to printhead assembly <NUM>. In one example, printhead assembly <NUM> and ink supply assembly <NUM> are housed together in an inkjet or fluid-jet print cartridge or pen. In another example, ink supply assembly <NUM> is separate from printhead assembly <NUM> and supplies ink to printhead assembly <NUM> through an interface connection <NUM>, such as a supply tube and/or valve.

Carriage assembly <NUM> positions printhead assembly <NUM> relative to print media transport assembly <NUM>, and print media transport assembly <NUM> positions print media <NUM> relative to printhead assembly <NUM>. Thus, a print zone <NUM> is defined adjacent to nozzles <NUM> in an area between printhead assembly <NUM> and print media <NUM>. In one example, printhead assembly <NUM> is a scanning type printhead assembly such that carriage assembly <NUM> moves printhead assembly <NUM> relative to print media transport assembly <NUM>. In another example, printhead assembly <NUM> is a non-scanning type printhead assembly such that carriage assembly <NUM> fixes printhead assembly <NUM> at a prescribed position relative to print media transport assembly <NUM>.

Service station assembly <NUM> provides for spitting, wiping, capping, and/or priming of printhead assembly <NUM> to maintain the functionality of printhead assembly <NUM> and, more specifically, nozzles <NUM>. For example, service station assembly <NUM> may include a rubber blade or wiper which is periodically passed over printhead assembly <NUM> to wipe and clean nozzles <NUM> of excess ink. In addition, service station assembly <NUM> may include a cap that covers printhead assembly <NUM> to protect nozzles <NUM> from drying out during periods of non-use. In addition, service station assembly <NUM> may include a spittoon into which printhead assembly <NUM> ejects ink during spits to ensure that reservoir <NUM> maintains an appropriate level of pressure and fluidity, and to ensure that nozzles <NUM> do not clog or weep. Functions of service station assembly <NUM> may include relative motion between service station assembly <NUM> and printhead assembly <NUM>.

Electronic controller <NUM> communicates with printhead assembly <NUM> through a communication path <NUM>, service station assembly <NUM> through a communication path <NUM>, carriage assembly <NUM> through a communication path <NUM>, and print media transport assembly <NUM> through a communication path <NUM>. In one example, when printhead assembly <NUM> is mounted in carriage assembly <NUM>, electronic controller <NUM> and printhead assembly <NUM> may communicate via carriage assembly <NUM> through a communication path <NUM>. Electronic controller <NUM> may also communicate with ink supply assembly <NUM> such that, in one implementation, a new (or used) ink supply may be detected.

Electronic controller <NUM> receives data <NUM> from a host system, such as a computer, and may include memory for temporarily storing data <NUM>. Data <NUM> may be sent to fluid ejection system <NUM> along an electronic, infrared, optical or other information transfer path. Data <NUM> represent, for example, a document and/or file to be printed. As such, data <NUM> form a print job for fluid ejection system <NUM> and includes at least one print job command and/or command parameter.

In one example, electronic controller <NUM> provides control of printhead assembly <NUM> including timing control for ejection of ink drops from nozzles <NUM>. As such, electronic controller <NUM> defines a pattern of ejected ink drops which form characters, symbols, and/or other graphics or images on print media <NUM>. Timing control and, therefore, the pattern of ejected ink drops, is determined by the print job commands and/or command parameters. In one example, logic and drive circuitry forming a portion of electronic controller <NUM> is located on printhead assembly <NUM>. In another example, logic and drive circuitry forming a portion of electronic controller <NUM> is located off printhead assembly <NUM>. In another example, logic and drive circuitry forming a portion of electronic controller <NUM> is located off printhead assembly <NUM>. In one example, electronic controller <NUM> may provide operating signals via I/O pads <NUM> to print component <NUM>, such as illustrated by <FIG>.

Claim 1:
A print component comprising:
a plurality of I/O pads (<NUM>), including an analog pad (<NUM>), to communicate operating signals for operating the print component;
a fluidic ejection circuit (<NUM>) coupled to the I/O pads (<NUM>) including:
an array (<NUM>) of fluid actuators (<NUM>); and
an array (<NUM>) of memory elements (<NUM>), each memory element (<NUM>) to store a data bit having a bit value representing information associated with the print component; and
a memory circuit (<NUM>) including:
a memory component (<NUM>) to store memory values (<NUM>) associated with the print component, each memory value (<NUM>) of at least a portion of the memory values (<NUM>) of the memory component (<NUM>) corresponding to a different one of the memory elements (<NUM>); and characterized by:
a control circuit (<NUM>) to, in response to identifying a sequence of operating signals representing a memory read of selected memory elements (<NUM>), provide a first analog signal on the analog pad (<NUM>) in parallel with a second analog signal from the fluid ejection circuit (<NUM>) representing bit values of the selected memory elements (<NUM>) to provide an analog electrical value on the analog pad (<NUM>) representing stored memory values (<NUM>) corresponding to the selected memory elements (<NUM>).