Patent Description:
Existing public-key digital signature algorithms such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve Digital Signature Algorithm (ECDSA) are anticipated not to be secure against brute-force attacks based on algorithms such as Shor's algorithm using quantum computers. As a result, there are efforts underway in the cryptography research community and in various standards bodies to define new standards for algorithms that are secure against quantum computers.

Accordingly, techniques to implement low latency post-quantum signature verification for fast secure-boot operations may find utility, e.g., in computer-based communication systems and methods.

<NPL> relates to a hardware-software co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor.

<CIT> relates to a processor including a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm.

<NPL> relates to an investigation of the use of the XMSS scheme targeting Internet-of-Thing constrained devices.

Described herein are exemplary systems and methods to implement accelerators for post-quantum cryptography secure hash-based signature algorithms. In the following description, numerous specific details are set forth to provide a thorough understanding of various examples. However, it will be understood by those skilled in the art that the various examples may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the examples.

As described briefly above, existing public-key digital signature algorithms such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve Digital Signature Algorithm (ECDSA) are anticipated not to be secure against brute-force attacks based on algorithms such as Shor's algorithm using quantum computers. The eXtended Merkle signature scheme (XMSS) and/or an eXtended Merkle many time signature scheme (XMSS-MT) are hash-based signature schemes that can protect against attacks by quantum computers. As used herein, the term XMSS shall refer to both the XMSS scheme and the XMSS-MT scheme.

An XMSS signature process implements a hash-based signature scheme using a one-time signature scheme such as a Winternitz one-time signature (WOTS) or a derivative there of (e.g., WOTS+) in combination with a secure hash algorithm (SHA) such as SHA2-<NUM> as the primary underlying hash function. In some examples the XMSS signature/verification scheme may also use one or more of SHA2-<NUM>, SHA3-SHAKE-<NUM> or SHA3-SHAKE-<NUM> as secure hash functions. XMSS-specific hash functions include a Pseudo-Random Function (PRF), a chain hash (F), a tree hash (H) and message hash function (Hmsg). As used herein, the term WOTS shall refer to the WOTS signature scheme and or a derivative scheme such as WOTS+.

The Leighton/Micali signature (LMS) scheme is another hash-based signature scheme that uses Leighton/Micali one-time signatures (LM-OTS) as the one-time signature building block. LMS signatures are based on a SHA2-<NUM> hash function.

An XMSS signature process comprises three major operations. The first major operation receives an input message (M) and a private key (sk) and utilizes a one-time signature algorithm (e.g., WOTS+) to generate a message representative (M') that encodes a public key (pk). In a <NUM>-bit post quantum security implementation the input message M is subjected to a hash function and then divided into <NUM> message components (n bytes each), each of which are subjected to a hash chain function to generate the a corresponding <NUM> components of the digital signature. Each chain function invokes a series of underlying secure hash algorithms (SHA).

The second major operation is an L-Tree computation, which combines WOTS+ (or WOTS) public key components (n-bytes each) and produces a single n-byte value. For example, in the <NUM>-bit post-quantum security there are <NUM> public key components, each of which invokes an underlying secure hash algorithm (SHA) that is performed on an input block.

The third major operation is a tree-hash operation, which constructs a Merkle tree. In an XMSS verification, an authentication path that is provided as part of the signature and the output of L-tree operation is processed by a tree-hash operation to generate the root node of the Merkle tree, which should correspond to the XMSS public key. For XMSS verification with <NUM>-bit post-quantum security, traversing the Merkle tree comprises executing secure hash operations. In an XMSS verification, the output of the Tree-hash operation is compared with the known public key. If they match then the signature is accepted. By contrast, if they do not match then the signature is rejected.

The XMSS signature process is computationally expensive. An XMSS signature process invokes hundreds, or even thousands, of cycles of hash computations. Subject matter described herein addresses these and other issues by providing systems and methods to implement accelerators for post-quantum cryptography secure XMSS and LMS hash-based signing and verification.

Post-Quantum Cryptography (also referred to as "quantum-proof", "quantum-safe", "quantum-resistant", or simply "PQC") takes a futuristic and realistic approach to cryptography. It prepares those responsible for cryptography as well as end-users to know the cryptography is outdated; rather, it needs to evolve to be able to successfully address the evolving computing devices into quantum computing and post-quantum computing.

It is well-understood that cryptography allows for protection of data that is communicated online between individuals and entities and stored using various networks. This communication of data can range from sending and receiving of emails, purchasing of goods or services online, accessing banking or other personal information using websites, etc..

Conventional cryptography and its typical factoring and calculating of difficult mathematical scenarios may not matter when dealing with quantum computing. These mathematical problems, such as discrete logarithm, integer factorization, and elliptic-curve discrete logarithm, etc., are not capable of withstanding an attack from a powerful quantum computer. Although any post-quantum cryptography could be built on the current cryptography, the novel approach would need to be intelligent, fast, and precise enough to resist and defeat any attacks by quantum computers.

Today's PQC is mostly focused on the following approaches: <NUM>) hash-based cryptography based on Merkle's hash tree public-key signature system of <NUM>, which is built upon a one-message-signature idea of Lamport and Diffie; <NUM>) code-based cryptography, such as McEliece's hidden-Goppa-code public-key encryption system; <NUM>) lattice-based cryptography based on Hoffstein-Pipher-Silverman public-key-encryption system of <NUM>; <NUM>) multivariate-quadratic equations cryptography based on Patarin's HFE public-key-signature system of <NUM> that is further based on the Matumoto-Imai proposal; <NUM>) supersingular elliptical curve isogeny cryptography that relies on supersingular elliptic curves and supersingular isogeny graphs; and <NUM>) symmetric key quantum resistance.

<FIG> illustrate a one-time hash-based signatures scheme and a multi-time hash-based signatures scheme, respectively. As aforesaid, hash-based cryptography is based on cryptographic systems like Lamport signatures, Merkle Signatures, extended Merkle signature scheme (XMSS), and SPHINCs scheme, etc. With the advent of quantum computing and in anticipation of its growth, there have been concerns about various challenges that quantum computing could pose and what could be done to counter such challenges using the area of cryptography.

One area that is being explored to counter quantum computing challenges is hash-based signatures (HBS) since these schemes have been around for a long while and possess the necessarily basic ingredients to counter the quantum counting and post-quantum computing challenges. HBS schemes are regarded as fast signature algorithms working with fast platform secured-boot, which is regarded as the most resistant to quantum and post-quantum computing attacks.

For example, as illustrated with respect to <FIG>, a scheme of HBS is shown that uses Merkle trees along with a one-time signature (OTS) scheme <NUM>, such as using a private key to sign a message and a corresponding public key to verify the OTS message, where a private key only signs a single message.

Similarly, as illustrated with respect to <FIG>, another HBS scheme is shown, where this one relates to multi-time signatures (MTS) scheme <NUM>, where a private key can sign multiple messages.

<FIG> and <FIG> illustrate a one-time signature scheme and a multi-time signature scheme, respectively. Continuing with HBS-based OTS scheme <NUM> of <FIG> and MTS scheme <NUM> of <FIG>, <FIG> illustrates Winternitz OTS scheme <NUM>, which was offered by Robert Winternitz of Stanford Mathematics Department publishing as hw(x) as opposed to h(x)|h(y), while <FIG> illustrates XMSS MTS scheme <NUM>, respectively.

For example, WOTS scheme <NUM> of <FIG> provides for hashing and parsing of messages into M, with <NUM> integers between [<NUM>, <NUM>, <NUM>,. , <NUM>], such as private key, sk, <NUM>, signature, s, <NUM>, and public key, pk, <NUM>, with each having <NUM> components of <NUM> bytes each.

<FIG> illustrates XMSS MTS scheme <NUM> that allows for a combination of WOTS scheme <NUM> of <FIG> and XMSS scheme <NUM> having XMSS Merkle tree. As discussed previously with respect to <FIG>, WOTs scheme <NUM> is based on a one-time public key, pk, <NUM>, having <NUM> components of <NUM> bytes each, that is then put through L-Tree compression algorithm <NUM> to offer WOTS compressed pk <NUM> to take a place in the XMSS Merkle tree of XMSS scheme <NUM>. It is contemplated that XMSS signature verification may include computing WOTS verification and checking to determine whether a reconstructed root node matches the XMSS public key, such as root node = XMSS public key.

<FIG> is a schematic illustration of a high-level architecture of a secure environment <NUM> that includes a first device <NUM> and a second device <NUM>, in accordance with some examples. Referring to <FIG>, each of the first device <NUM> and the second device <NUM> may be embodied as any type of computing device capable of performing the functions described herein. For example, in some embodiments, each of the first device <NUM> and the second device <NUM> may be embodied as a laptop computer, tablet computer, notebook, netbook, Ultrabook™, a smartphone, cellular phone, wearable computing device, personal digital assistant, mobile Internet device, desktop computer, router, server, workstation, and/or any other computing/communication device.

First device <NUM> includes one or more processor(s) <NUM> and a memory <NUM> to store a private key <NUM>. The processor(s) <NUM> may be embodied as any type of processor capable of performing the functions described herein. For example, the processor(s) <NUM> may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. Similarly, the memory <NUM> may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory <NUM> may store various data and software used during operation of the first device <NUM> such as operating systems, applications, programs, libraries, and drivers. The memory <NUM> is communicatively coupled to the processor(s) <NUM>. In some examples the private key <NUM> may reside in a secure memory that may be part memory <NUM> or may be separate from memory <NUM>.

First device <NUM> further comprises authentication logic <NUM> which includes memory <NUM>, signature logic, and verification logic <NUM>. Hash logic <NUM> is configured to hash (i.e., to apply a hash function to) a message (M) to generate a hash value (m') of the message M. Hash functions may include, but are not limited to, a secure hash function, e.g., secure hash algorithms SHA2-<NUM> and/or SHA3-<NUM>, etc. SHA2-<NUM> may comply and/or be compatible with Federal Information Processing Standards (FIPS) Publication <NUM>-<NUM>, titled: "Secure Hash Standard (SHS)", published by National Institute of Standards and Technology (NIST) in March <NUM>, and/or later and/or related versions of this standard. SHA3-<NUM> may comply and/or be compatible with FIPS Publication <NUM>, titled: "<NPL>, and/or later and/or related versions of this standard.

Signature logic <NUM> may be configured to generate a signature to be transmitted, i.e., a transmitted signature and/or to verify a signature. In instances in which the first device <NUM> is the signing device, the transmitted signature may include a number, L, of transmitted signature elements with each transmitted signature element corresponding to a respective message element. For example, for each message element, mi, signature logic <NUM> may be configured to perform a selected signature operation on each private key element, ski of the private key, sk, a respective number of times related to a value of each message element, mi included in the message representative m'. For example, signature logic <NUM> may be configured to apply a selected hash function to a corresponding private key element, ski, mi times. In another example, signature logic <NUM> may be configured to apply a selected chain function (that contains a hash function) to a corresponding private key element, ski, mi times. The selected signature operations may, thus, correspond to a selected hash-based signature scheme.

Hash-based signature schemes may include, but are not limited to, a Winternitz (W) one time signature (OTS) scheme, an enhanced Winternitz OTS scheme (e.g., WOTS+), a Merkle many time signature scheme, an extended Merkle signature scheme (XMSS) and/or an extended Merkle multiple tree signature scheme (XMSS-MT), etc. Hash functions may include, but are not limited to SHA2-<NUM> and/or SHA3-<NUM>, etc. For example, XMSS and/or XMSS-MT may comply or be compatible with one or more Internet Engineering Task Force (IETF. ) informational draft Internet notes, e.g., draft draft-irtf-cfrg-xmss-hash-based-signatures-<NUM>, titled "<NPL>. and/or later and/or related versions of this informational draft, such as draft draft-irtf-cfrg-xmss-hash-based-signatures-<NUM>, released June <NUM>.

Winternitz OTS is configured to generate a signature and to verify a received signature utilizing a hash function. Winternitz OTS is further configured to use the private key and, thus, each private key element, ski, one time. For example, Winternitz OTS may be configured to apply a hash function to each private key element, mi or N-mi times to generate a signature and to apply the hash function to each received message element N-mi' or mi' times to generate a corresponding verification signature element. The Merkle many time signature scheme is a hash-based signature scheme that utilizes an OTS and may use a public key more than one time. For example, the Merkle signature scheme may utilize Winternitz OTS as the one-time signature scheme. WOTS+ is configured to utilize a family of hash functions and a chain function.

XMSS, WOTS+ and XMSS-MT are examples of hash-based signature schemes that utilize chain functions. Each chain function is configured to encapsulate a number of calls to a hash function and may further perform additional operations. The number of calls to the hash function included in the chain function may be fixed. Chain functions may improve security of an associated hash-based signature scheme. Hash-based signature balancing, as described herein, may similarly balance chain function operations.

Cryptography logic <NUM> is configured to perform various cryptographic and/or security functions on behalf of the signing device <NUM>. In some embodiments, the cryptography logic <NUM> may be embodied as a cryptographic engine, an independent security co-processor of the signing device <NUM>, a cryptographic accelerator incorporated into the processor(s) <NUM>, or a standalone software/firmware. In some embodiments, the cryptography logic <NUM> may generate and/or utilize various cryptographic keys (e.g., symmetric/asymmetric cryptographic keys) to facilitate encryption, decryption, signing, and/or signature verification. Additionally, in some embodiments, the cryptography logic <NUM> may facilitate to establish a secure connection with remote devices over communication link. It should further be appreciated that, in some embodiments, the cryptography module <NUM> and/or another module of the first device <NUM> may establish a trusted execution environment or secure enclave within which a portion of the data described herein may be stored and/or a number of the functions described herein may be performed.

After the signature is generated as described above, the message, M, and signature may then be sent by first device <NUM>, e.g., via communication logic <NUM>, to second device <NUM> via network communication link <NUM>. In an embodiment, the message, M, may not be encrypted prior to transmission. In another embodiment, the message, M, may be encrypted prior to transmission. For example, the message, M, may be encrypted by cryptography logic <NUM> to produce an encrypted message.

Second device <NUM> may also include one or more processors <NUM> and a memory <NUM> to store a public key <NUM>. As described above, the processor(s) <NUM> may be embodied as any type of processor capable of performing the functions described herein. For example, the processor(s) <NUM> may be embodied as a single or multi-core processor(s), digital signal processor, microcontroller, or other processor or processing/controlling circuit. Similarly, the memory <NUM> may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory <NUM> may store various data and software used during operation of the second device <NUM> such as operating systems, applications, programs, libraries, and drivers. The memory <NUM> is communicatively coupled to the processor(s) <NUM>.

In some examples the public key <NUM> may be provided to verifier device <NUM> in a previous exchange. The public key, pk, is configured to contain a number L of public key elements, i.e., pk=[pk1,. The public key <NUM> may be stored, for example, to memory <NUM>.

Second device <NUM> further comprises authentication logic <NUM> which includes hash logic <NUM>, signature logic, and verification logic <NUM>. As described above, hash logic <NUM> is configured to hash (i.e., to apply a hash function to) a message (M) to generate a hash message (m'). Hash functions may include, but are not limited to, a secure hash function, e.g., secure hash algorithms SHA2-<NUM> and/or SHA3-<NUM>, etc. SHA2-<NUM> may comply and/or be compatible with Federal Information Processing Standards (FIPS) Publication <NUM>-<NUM>, titled: "<NPL>, and/or later and/or related versions of this standard. SHA3-<NUM> may comply and/or be compatible with FIPS Publication <NUM>, titled: "<NPL>, and/or later and/or related versions of this standard.

In instances in which the second device is the verifying device, authentication logic <NUM> is configured to generate a verification signature based, at least in part, on the signature received from the first device and based, at least in part, on the received message representative (m'). For example, authentication logic <NUM> may configured to perform the same signature operations, i.e., apply the same hash function or chain function as applied by hash logic <NUM> of authentication logic <NUM>, to each received message element a number, N-mi' (or mi'), times to yield a verification message element. Whether a verification signature, i.e., each of the L verification message elements, corresponds to a corresponding public key element, pki, may then be determined. For example, verification logic <NUM> may be configured to compare each verification message element to the corresponding public key element, pki. If each of the verification message element matches the corresponding public key element, pki, then the verification corresponds to success. In other words, if all of the verification message elements match the public key elements, pk1,. , pkL, then the verification corresponds to success. If any verification message element does not match the corresponding public key element, pki, then the verification corresponds to failure.

As described in greater detail below, in some examples the authentication logic <NUM> of the first device <NUM> includes one or more accelerators <NUM> that cooperate with the hash logic <NUM>, signature logic <NUM> and/or verification logic <NUM> to accelerate authentication operations. Similarly, in some examples the authentication logic <NUM> of the second device <NUM> includes one or more accelerators <NUM> that cooperate with the hash logic <NUM>, signature logic <NUM> and/or verification logic <NUM> to accelerate authentication operations. Examples of accelerators are described in the following paragraphs and with reference to the accompanying drawings.

The various modules of the environment <NUM> may be embodied as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of the environment <NUM> may form a portion of, or otherwise be established by, the processor(s) <NUM> of first device <NUM> or processor(s) <NUM> of second device <NUM>, or other hardware components of the devices As such, in some embodiments, one or more of the modules of the environment <NUM> may be embodied as circuitry or collection of electrical devices (e.g., an authentication circuitry, a cryptography circuitry, a communication circuitry, a signature circuitry, and/or a verification circuitry). Additionally, in some embodiments, one or more of the illustrative modules may form a portion of another module and/or one or more of the illustrative modules may be independent of one another.

<FIG> is a schematic illustration of a Merkle tree structure illustrating signing operations, in accordance with some examples. Referring to <FIG>, an XMSS signing operation requires the construction of a Merkle tree 400A using the local public key from each leaf WOTS node <NUM> to generate a global public key (PK) <NUM>. In some examples the authentication path and the root node value can be computed off-line such that these operations do not limit performance. Each WOTS node <NUM> has a unique secret key, "sk" which is used to sign a message only once. The XMSS signature consists of a signature generated for the input message and an authentication path of intermediate tree nodes to construct the root of the Merkle tree.

<FIG> is a schematic illustration of a Merkle tree structure 400B during verification, in accordance with some examples. During verification, the input message and signature are used to compute the local public key 420B of the WOTS node, which is further used to compute the tree root value using the authentication path. A successful verification will match the computed tree root value to the public key PK shared by the signing entity. The WOTS and L-Tree operations constitute on average <NUM>% and <NUM>% of XMSS sign/verify latency respectively, thus defining the overall performance of the authentication system. Described herein are various pre-computation techniques which may be implemented to speed-up WOTS and L-Tree operations, thereby improving XMSS performance. The techniques are applicable to the other hash options and scale well for both software and hardware implementations.

<FIG> is a schematic illustration of a compute blocks in an architecture <NUM> to implement a signature algorithm, in accordance with some examples. Referring to <FIG>, the WOTS+ operation involves <NUM> parallel chains of <NUM> SHA2-<NUM> HASH functions, each with the secret key sk[<NUM>:<NUM>] as input. Each HASH operation in the chain consists of <NUM> pseudo-random functions (PRF) using SHA2-<NUM> to generate a bitmask and a key. The bitmask is XOR-ed with the previous hash and concatenated with the key as input message to a 3rd SHA2-<NUM> hash operation. The <NUM>×<NUM>-byte WOTS public key pk[<NUM>:<NUM>] is generated by hashing secret key sk across the <NUM> hash chains.

<FIG> is a schematic illustration of a compute blocks in an architecture 600A to implement signature generation in a signature algorithm, in accordance with some examples. As illustrated in <FIG>, for message signing, the input message is hashed and pre-processed to compute a <NUM>×<NUM>-bit value, which is used as an index to choose an intermediate hash value in each chain.

<FIG> is a schematic illustration of a compute blocks in an architecture 600B to implement signature verification in a verification algorithm, in accordance with some examples. Referring to <FIG>, during verification, the message is again hashed to compute the signature indices and compute the remaining HASH operations in each chain to compute the WOTS public key pk. This value and the authentication path are used to compute the root of the Merkle tree and compare with the shared public key PK to verify the message.

As described briefly above, the XMSS hash-based signature scheme is a post-quantum signature verification algorithm that can protect secure-boot against quantum computers. XMSS signature verification consists of three major steps.

The first major step is onetime (WOTS+) public key generation. This step takes a message representation vector and XMSS signature components as inputs and computes the corresponding onetime WOTS+ public key components (n-bytes each). It comprises execution of the chain function for each signature/public key component, where the chain function in verification includes eight (<NUM>) iterations of three (<NUM>) SHAKE operations on three (<NUM>) n-bit input blocks (Opcode + KEY + M).

The second major step is the L-Tree computation, which combines WOTS+ (or WOTS) public key components (n-byte each) and produces a single n-byte value. For a <NUM>-bit post-quantum security there are <NUM> public key components. Each hash operation is performed on 4n-byte input block, which translates to <NUM> SHAKE operations.

The third major step is the tree-hash operation, which is the Merkle tree construction step. In an XMSS verification, an authentication path that is provided as part of the signature and the output of L-tree operation are processed by the tree-hash operation to generate the root node of the Merkle tree, which is supposed to correspond to the XMSS public key. For XMSS verification with <NUM>-bit post-quantum security, each level of the Merkle tree consists of one hash operation with 4n-bit (4x256-bit) input. The SHAKE function is capable to capture all <NUM>-bit inputs as one block. Therefore, for a XMSS scheme with <NUM> Merkle tree depth would have ten (<NUM>) SHAKE functions for computing the root node in Tree-hash. In the final step of XMSS verification, the output of the Tree-hash operation is matched with the known public key. If they are equal then the signature is accepted. If they are not equal the signature is rejected.

The signature verification operation in XMSS requires approximately <NUM> cycles of hash computations. Approximately <NUM>% of the hash operations are performed on three <NUM>-byte inputs to the XMSS operation, referred to herein as (Opcode, KEY and M). In one example, the SHA3 (SHAKE*) algorithm has a large input block size that fits the set of inputs (Opcode + KEY + M) within one input block, as opposed to two input blocks in the SHA2 algorithm. Additionally, the SHA3 algorithm utilizes <NUM> rounds which is <NUM>. 7x fewer than the SHA2 algorithm. However, in some examples the SHA3 is slower than the SHA2 algorithm in software because the SHA3 round function is based on <NUM>-bit operations on a <NUM>-bit variable, while the SHA2 algorithm is based on <NUM>-bit operations on a <NUM>-bit variable.

It will be recognized that bit operations in SHA3 round function are independent to each other and can be computed in parallel in hardware. Described herein is a SHAKE hardware engine that computes all <NUM> bit-operations in parallel within a single SHA3-round of execution. Further, the SHAKE hardware engine implements a unified datapath for eight SHA3 rounds within one clock period (e.g., @<NUM>). The resulting SHAKE hardware engine has a latency of <NUM> cycles for computing a hash on the inputs comprising (Opcode + KEY + M). Additionally, the hardware engine pipelines three sub-operations (data fetch from memory, SHAKE operation and Data restore into memory). As a result of these design features, the SHAKE hardware engine provides a low latency XMSS HW Engine that can compute an XMSS verification operation in as few as <NUM>,<NUM> cycles, which corresponds to <NUM> microseconds at a <NUM> clock speed.

<FIG> is a schematic illustration of compute blocks in an architecture of an XMSS hardware accelerator <NUM> to implement low latency post-quantum signature verification for fast secure-boot operations, in accordance with some examples. Referring to <FIG>, in some examples a XMSS hardware accelerator <NUM> may comprise a computer readable memory block (or register file) <NUM> which may be used to store XMSS inputs and intermediate results for the XMSS operations, an XMSS verification manager <NUM>, a WOTS+ (or WOTS) public key generation manager logic <NUM>, an L-Tree computation logic <NUM>, a tree-hash operations logic <NUM>, and a chain function logic <NUM>, which are coupled to a low-latency SHAKE hardware engine <NUM> via an interface <NUM>. When the hardware accelerator <NUM> is initialized for an XMSS verify operation it switches to a protected mode and completes the execution atomically and ignores all external reads & writes during the execution.

<FIG> is a schematic illustration of compute blocks in an architecture to implement low latency post-quantum signature verification for fast secure-boot operations, in accordance with some examples. <FIG> illustrates compute blocks of a unified SHAKE hardware engine <NUM> as depicted in <FIG>. Referring to <FIG>, in some examples the SHAKE hash algorithm has a <NUM>-bit state variable which is processed through <NUM> round functions each of them comprising five steps (θ, ρ, π, χ and <IMG>). The SHAKE hardware engine <NUM> comprises an input multiplexer <NUM> and output multiplexer <NUM> which enable specific sets of input/output bits based on the mode of operation. The SHAKE hardware engine <NUM> executes all <NUM> SHA3 rounds iteratively and generates a digest output <NUM>.

During execution in a SHAKE128 hash operating mode, the SHAKE hardware engine <NUM> configures with <NUM>-bit state, <NUM>-bit input block and <NUM>-bit output. All inputs for each WOTS chain function, the hashes involved in an L-tree computation and the hash operations for a Merkle tree root node computation are fit within one input block of SHAKE128. When the unified SHAKE hardware engine <NUM> receives a start pulse it captures the input from msg port <NUM> and starts SHAKE128 execution. One round of SHA3 is computed in one clock cycle by the SHAKE hardware engine <NUM>. After one round it updates the <NUM>-bit state register <NUM>. In the following clock cycle the SHAKE hardware engine <NUM> computes the next round operation on the updated state value, and so on for subsequent cycles. After <NUM> such iterations the state register <NUM> does not update and the <NUM>-bit digest is generated through the digest out port <NUM>. To generate a <NUM>-bit output, after generating first <NUM>-bit output, the SHAKE hardware engine <NUM> executes for another <NUM> SHA3 rounds with input zero (i.e., a Squeeze) and generates the second <NUM>-bit output of the <NUM>-bits.

In some examples the SHAKE hardware engine <NUM> may execute in a SHAKE <NUM> mode. During execution in a SHAKE256 has operating mode the SHAKE hardware engine <NUM> is configured with <NUM>-bit state, a <NUM>-bit input, and a <NUM>-bit output. In SHAKE256 mode the SHAKE hardware engine <NUM> can generate one <NUM>-bit output after <NUM> rounds. Therefore, similar to the SHAKE128 mode, it computes the first <NUM> bits in a first <NUM> rounds then performs one extra squeeze for generating the second <NUM>-bit output for computing <NUM>-bit output for XMSS operations.

<FIG> is a flowchart illustrating operations in a method to implement low latency post-quantum signature verification for fast secure-boot operations, in accordance with some examples. More particularly, <FIG> illustrates operations which may be implemented by a host process in a method to implement low latency post-quantum signature verification for fast secure-boot operations. In some examples the operations depicted in <FIG> may be implemented by a processor, e.g., one or more of the processors <NUM> in first device or the processor(s) in the second device <NUM>. Referring to <FIG>, at operation <NUM> an XMSS operation is received. If, at operation <NUM>, the XMSS hardware accelerator <NUM> is asserting an IP_Busy status then control remains at operation <NUM> and the host process continues to monitor the status of the XMSS hardware accelerator <NUM>.

By contrast, if at operation <NUM> the XMSS hardware accelerator <NUM> is not asserting an IP_Busy status then control passes to operation <NUM> and the host process writes the XMSS inputs to the XMSS hardware accelerator <NUM>. At operation <NUM> the host process applies a start pulse to the XMSS hardware accelerator <NUM>.

At operation <NUM> the host process monitors the status of the XMSS hardware accelerator <NUM> to determine whether the XMSS hardware accelerator <NUM> has completed its operations. If, at operation <NUM>, the XMSS hardware accelerator <NUM> has not completed its operations then the host process continues to poll the XMSS hardware accelerator <NUM>. By contrast, if at operation <NUM> the XMSS hardware accelerator <NUM> has completed its operations then control passes to operation <NUM> and the host process reads the results of the XMSS hardware accelerator <NUM>.

At operation <NUM> the host process compares the computed root node read from the XMSS hardware accelerator <NUM> in operation <NUM> with the known public key. If, at operation <NUM>, the computed root node does not match the known public key then control passes to operation <NUM> and the signature is rejected (i.e., not verified). By contrast, if at operation <NUM>, the computed root node matches the known public key then control passes to operation <NUM> and the signature is accepted (i.e., verified).

<FIG> is a flowchart illustrating operations in a method to implement low latency post-quantum signature verification for fast secure-boot operations, in accordance with some examples. More particularly, <FIG> illustrates operations which may be implemented by XMSS hardware accelerator <NUM>. Referring to <FIG>, at operation <NUM> the XMSS hardware accelerator <NUM> asserts an IP_Busy status and at operation <NUM> the XMSS hardware accelerator <NUM> switches to a protected mode in which it ignores external read/write operations and invokes the XMSS operation state machine to execute XMSS operations.

At operation <NUM> the WOTS+ public key generation logic <NUM> is invoked to implement one-time signature operations repeatedly until they one-time signature operations are finished. The WOTS+ public key generation logic <NUM> invokes the chain function logic <NUM> to perform chain functions at operation <NUM> and also invokes the SHAKE hardware engine <NUM> to perform the SHAKE hash functions at operation <NUM>. At operation <NUM> a chain function logic <NUM> is invoked to implement chain function operations until the chain function operations are completed, and at operation <NUM> the SHAKE hardware engine <NUM> is activated to perform SHAKE hash functions.

When the SHAKE hardware engine <NUM> completes the hash function at operation <NUM>, control passes to operation <NUM> and the XMSS accelerator <NUM> invokes the L-Tree computation logic <NUM> to perform an L-Tree computation. The L-Tree computation logic <NUM> invokes the SHAKE hardware engine <NUM> to perform SHAKE hash functions at operation <NUM>.

When the SHAKE hardware engine <NUM> completes the hash function at operation <NUM>, control passes to operation <NUM> and the XMSS accelerator <NUM> invokes the Tree-hash operations logic <NUM> to perform an L-Tree computation. The Tree-hash computation logic <NUM> invokes the SHAKE hardware engine to perform SHAKE hash functions at operation <NUM>.

When the SHAKE hardware engine <NUM> completes the hash function at operation <NUM>, control passes to operation <NUM> and the XMSS accelerator <NUM> sets a done flag and releases the IP_Busy status such that when the host process polls the XMSS accelerator <NUM> at operation <NUM> the host process receives an indication that the XMSS accelerator <NUM> is finished and the host process can read the results at operation <NUM>.

<FIG> illustrates an embodiment of an exemplary computing architecture that may be suitable for implementing various embodiments as previously described. In various embodiments, the computing architecture <NUM> may comprise or be implemented as part of an electronic device. In some embodiments, the computing architecture <NUM> may be representative, for example of a computer system that implements one or more components of the operating environments described above. In some embodiments, computing architecture <NUM> may be representative of one or more portions or components of a DNN training system that implement one or more techniques described herein.

As used in this application, the terms "system" and "component" and "module" are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary computing architecture <NUM>. For example, a component can be, but is not limited to being, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and/or magnetic storage medium), an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution, and a component can be localized on one computer and/or distributed between two or more computers. Further, components may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the unidirectional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

As shown in <FIG>, the computing architecture <NUM> includes one or more processors <NUM> and one or more graphics processors <NUM>, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors <NUM> or processor cores <NUM>. In on embodiment, the system <NUM> is a processing platform incorporated within a system-on-a-chip (SoC or SOC) integrated circuit for use in mobile, handheld, or embedded devices.

An embodiment of system <NUM> can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system <NUM> is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system <NUM> can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system <NUM> is a television or set top box device having one or more processors <NUM> and a graphical interface generated by one or more graphics processors <NUM>.

In some embodiments, one or more processor(s) <NUM> are coupled with one or more interface bus(es) <NUM> to transmit communication signals such as address, data, or control signals between processor <NUM> and other components in the system. The interface bus <NUM>, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In one embodiment the processor(s) <NUM> include an integrated memory controller <NUM> and a platform controller hub <NUM>. The memory controller <NUM> facilitates communication between a memory device and other components of the system <NUM>, while the platform controller hub (PCH) <NUM> provides connections to I/O devices via a local I/O bus.

Memory device <NUM> can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device <NUM> can operate as system memory for the system <NUM>, to store data <NUM> and instructions <NUM> for use when the one or more processors <NUM> executes an application or process. Memory controller hub <NUM> also couples with an optional external graphics processor <NUM>, which may communicate with the one or more graphics processors <NUM> in processors <NUM> to perform graphics and media operations. In some embodiments a display device <NUM> can connect to the processor(s) <NUM>. The display device <NUM> can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment the display device <NUM> can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub <NUM> enables peripherals to connect to memory device <NUM> and processor <NUM> via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller <NUM>, a network controller <NUM>, a firmware interface <NUM>, a wireless transceiver <NUM>, touch sensors <NUM>, a data storage device <NUM> (e.g., hard disk drive, flash memory, etc.). The data storage device <NUM> can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The touch sensors <NUM> can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver <NUM> can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a <NUM>, <NUM>, or Long Term Evolution (LTE) transceiver. The firmware interface <NUM> enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller <NUM> can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus <NUM>. The audio controller <NUM>, in one embodiment, is a multi-channel high definition audio controller. In one embodiment the system <NUM> includes an optional legacy I/O controller <NUM> for coupling legacy (e.g., Personal System <NUM> (PS/<NUM>)) devices to the system. The platform controller hub <NUM> can also connect to one or more Universal Serial Bus (USB) controllers <NUM> connect input devices, such as keyboard and mouse <NUM> combinations, a camera <NUM>, or other USB input devices.

The following pertains to further examples.

Example <NUM> is an apparatus, comprising a computer readable memory;an XMSS verification manager logic to manage XMSS verification functions; a one-time signature and public key generator logic; chain function logic to implement chain function algorithms; a low latency SHA3 hardware engine; and a register bank communicatively coupled to the XMSS verification manager logic.

In Example <NUM>, the subject matter of Example <NUM> can optionally include logic to receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and apply the set of XMSS inputs to an XMSS verification manager logic.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include comprising logic to assert a busy signal on a communication bus; and switch to a protected mode in which external read/write operations are disregarded.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include logic to apply a one-time signature function process to the set of XMSS inputs; and invoke the chain function logic to apply a chain function to facilitate the one-time signature function.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include an arrangement wherein the SHA3 hardware engine is capable to perform a SHAKE-<NUM> function or to perform a SHAKE-<NUM> operation.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include an arrangement wherein the SHA3 hardware engine comprises a <NUM> bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a <NUM> bit message input.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include an arrangement wherein the SHA3 hardware engine comprises logic to perform a first set of <NUM> SHA3 rounds using the first set of inputs; and generate a first <NUM> bit output.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include an arrangement perform a second set of <NUM> SHA3 rounds using no inputs; and generate a second <NUM> bit output.

In Example <NUM>, the subject matter of any one of Examples <NUM>-<NUM> can optionally include an arrangement wherein the SHA3 hardware engine comprises logic to perform a second set of <NUM> SHA3 rounds using no inputs; and generate a second <NUM> bit output.

Example <NUM> is an electronic device, comprising a processor; and a hardware accelerator for an authentication logic, the hardware accelerator comprising a computer readable memory; an XMSS verification manager logic to manage XMSS verification functions; a one-time signature and public key generator logic; a chain function logic to implement chain function algorithms; a low latency SHA3 hardware engine; and a register bank communicatively coupled to the XMSS verification manager logic.

The above Detailed Description includes references to the accompanying drawings, which form a part of the Detailed Description. The drawings show, by way of illustration, specific embodiments that may be practiced. " Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

" In addition "a set of" includes one or more elements. In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein. " Also, in the following claims, the terms "including" and "comprising" are open-ended; that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," "third," etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.

The terms "logic instructions" as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and examples are not limited in this respect.

The terms "computer readable medium" as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and examples are not limited in this respect.

The term "logic" as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and examples are not limited in this respect.

Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.

In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular examples, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.

Reference in the specification to "one example" or "some examples" means that a particular feature, structure, or characteristic described in connection with the example is included in at least an implementation. The appearances of the phrase "in one example" in various places in the specification may or may not be all referring to the same example.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein as embodiments may feature a subset of said features. Further, embodiments may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the embodiments disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claim 1:
An apparatus (<NUM>), comprising:
a computer readable memory (<NUM>);
an XMSS verification manager (<NUM>) logic to manage XMSS verification functions;
a one-time signature and public key generator logic (<NUM>);
a chain function logic (<NUM>) to implement chain function algorithms;
a low latency SHA3 hardware engine (<NUM>); and
a register bank (<NUM>) communicatively coupled to the XMSS verification manager logic,
wherein the SHA3 hardware engine (<NUM>) comprises a <NUM> bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a <NUM> bit message input.