Patent Description:
For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor devices. The drive to scale-down features in ICs such as microelectronic packages, while optimizing the performance of each device, however is not without issue.

One main issue involves the thermal management of such packages. For example, thermal management of microelectronic packages is becoming extremely important as the power requirements and the number of dies of the microelectronic packages steadily increase. These microelectronic packages typically include stacked dies which includes high power and high density bottom dies. Typically, the performance of these microelectronic packages is limited by the hotspots of the edges of the bottom dies. This leads to other issues as the high power density of the bottom die edges are covered with low thermal conductivity mold materials.

As such, existing packaging solutions may implement high thermal conductivity mold materials over the bottom die edges, attempt to increase the performance of the system cooling solutions, or reduce the thicknesses of the top dies and/or the mold layers. Such existing packaging solutions, however, may substantially increase packaging costs, time, and uncertainty such as leading to other unexpected issues. Furthermore, reducing the top die thicknesses may slightly reduce the hotspot temperature, but the reduction of the top die thickness does not remove (or mitigate) the actual hotspots generated by the edges of the bottom dies.

<CIT> discloses a semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

Embodiments described herein illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar features. Furthermore, some conventional details have been omitted so as not to obscure from the inventive concepts described herein.

Described herein are semiconductor packages with thermally conductive slugs and/or active silicon dies and methods of forming such semiconductor packages. The semiconductor packages described below and methods of forming such semiconductor packages may include an integrated heat spreader (IHS), a thermal interface material (TIM), a plurality of top dies, a plurality of bottom dies, a plurality of thermally conductive slugs, and a package substrate. Additionally, in these embodiments, the semiconductor packages described herein may include an IHS with a plurality of pedestals and/or an active die (e.g., a bridge die, an active silicon die, etc.).

In these embodiments, the semiconductor package may drill/laser a plurality of trenches into the encapsulation layer that surrounds (or embeds) the bottom dies. The trenches may be positioned (or located) over the edges of the bottom dies. Accordingly, in some embodiments, the trenches may expose the top surfaces of the top edges of the bottom dies, and subsequently the thermally conductive slugs may be disposed into the drilled trenches and directly over the exposed top surfaces of the bottom dies, where the thermally conductive slugs may thereby be positioned directly on the top surfaces of the top edges of the bottom dies and the package substrate. Furthermore, in these embodiments, the active die may be disposed into one of the trenches with the thermally conductive slugs, and the active die may be positioned directly over the exposed top surfaces of both of the bottom dies, where the active die may be a bridge (or a bridge die) that may communicatively couple the stacks of bottom dies and top dies to each other. In some alternative embodiments, the pedestals of the IHS may be disposed into the drilled trenches and directly over the exposed top surfaces of the bottom dies, where the pedestals of the IHS may thereby be positioned directly on the top surfaces of the top edges of the bottom dies.

The embodiments described herein provide improvements to existing packaging solutions by substantially increasing the thermal design power (TDP) capabilities of the semiconductor packages described herein. Additionally, these embodiments also enable removing the hotspots generated by the high power and high density bottom dies, which thereby allow the overall temperature of the semiconductor package to be significantly reduced without needing to reduce the thickness (or z-height) of the top dies. The embodiments described herein also improve the packaging solutions by implementing the trenches with a single drilling process (or the like) at no additional costs, where the trenches may be disposed (or filled) with the thermally conductive slugs (or the like). Accordingly, in these embodiments, the thermal resistance from the top edges of the bottom dies to the IHS is significantly reduced due to the highly thermal conductive materials (e.g., copper, silicon, and/or the like) of the thermally conductive slugs, the active die, and/or the pedestals of the IHS.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as microelectromechanical systems (MEMS) based electrical systems, gyroscopes, advanced driving assistance systems (ADAS), <NUM> communication systems, cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments, the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices, including semiconductor packages with IHSs, IHSs with pedestals, top dies, bottom dies, thermally conductive slugs, active dies (or bridge dies), and package substrates with embedded bridge dies.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present embodiments, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As used herein the terms "top," "bottom," "upper," "lower," "lowermost," and "uppermost" when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration. Thus, an element described as an "uppermost element" or a "top element" in a device may instead form the "lowermost element" or "bottom element" in the device when the device is inverted. Similarly, an element described as the "lowermost element" or "bottom element" in the device may instead form the "uppermost element" or "top element" in the device when the device is inverted.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the semiconductor package <NUM> may include an IHS <NUM>, a plurality of top dies 110a-b, a plurality of bottom dies 121a-b, a TIM <NUM>, a plurality of thermally conductive slugs 141a-b, an encapsulation layer <NUM>, and a package substrate <NUM>, according to one embodiment. In one embodiment, the bottom dies 121a-b (or first dies) may be disposed and coupled onto the top surface of the package substrate <NUM> with an adhesive layer <NUM> (or the like). For one embodiment, the top dies <NUM>10a-b (or the second dies) may be respectively disposed and coupled onto the bottom dies 121a-b.

In some embodiments, the bottom dies 121a-b may include a plurality of interconnects <NUM> that couple the package substrate <NUM> to the respective top dies <NUM>10a-b. In these embodiments, the interconnects <NUM> may be through silicon vias (TSVs), through glass vias (TGVs), and/or the like. In some embodiments, as described above, the semiconductor package <NUM> may include a plurality of trenches <NUM> (or cavities) disposed into the encapsulation layer <NUM> and surrounding the thermally conductive slugs 141a-b. In an embodiment, the thermally conductive slugs 141a-b may be positioned directly on the top surface of the bottom dies 121a-b. Likewise, in these embodiments, the thermally conductive slugs 141a-b may be positioned adjacent to the top dies <NUM>10a-b and separated by the encapsulation layer <NUM>.

In particular, as shown in <FIG>, the thermally conductive slugs 141a-b may be positioned directly on the top surfaces of the top outer edges of the bottom dies 121a-b to remove the formation of hotspots on these top outer edges of the bottom dies 121a-b. For some embodiments, the thermally conductive slugs 141a-b may be directly and thermally coupled to the top outer edges of the bottom dies 121a-b, the TIM <NUM>, and the IHS <NUM>. In an embodiment, the IHS <NUM> may be disposed over the top dies 110a-b, where the IHS <NUM> may be coupled to the top dies 110a-b with the TIM <NUM>. For one embodiment, the IHS <NUM> may be a heatsink or the like, where the heatsink may be a single shared heatsink or two separated heatsinks.

In an embodiment, a bridge <NUM> may be disposed in the package substrate <NUM>, and the bridge <NUM> may communicatively couple the bottom die 121a to the bottom die 121b. In an embodiment, the bridge <NUM> may comprise electrical routings (or interconnect structures) that may communicatively couple the bottom die 121a to the bottom die 121b. In an embodiment, the bridge <NUM> may be a silicon bridge, a glass bridge, or a bridge made of any other substrate material that is suitable for forming bridges. In some embodiments, the bridge <NUM> may be referred to as an embedded multi-die interconnect bridge (EMIB). For additional embodiments, the bridge <NUM> may include a plurality of TSVs that may be used to communicatively couple the bottom dies 121a-b.

For one embodiment, the encapsulation layer <NUM> may be disposed over the bottom dies 121a-b, where the encapsulation layer <NUM> also surrounds the top dies 110a-b and the thermally conductive slugs 141a-b. Additionally, as shown in <FIG>, the encapsulation layer <NUM> may be disposed in between the top dies 110a-b, where the encapsulation layer <NUM> may be disposed between the top surfaces of the bottom dies 121a-b and the bottom surface of the TIM <NUM>. For one embodiment, the encapsulation layer <NUM> may be planarized as the top surface of the encapsulation layer <NUM> may be substantially coplanar to the top surfaces of the top dies <NUM>10a-b.

Note that, according to some embodiment, the semiconductor package <NUM> is merely one example of an embodiment of a semiconductor packaged system. That is, the semiconductor package <NUM> is not limited to the illustrated semiconductor packaged system, and thus may be designed/formed with fewer, alternate, or additional packaging components and/or with different interconnecting structures. For example, while one IHS <NUM>, one TIM <NUM>, two thermally conductive slugs 141a, one thermally conductive slug 141b, two bottom dies 121a-b, two sets of top dies <NUM>10a-b, and one package substrate <NUM> with one bridge <NUM> are illustrated, it is to be appreciated that the semiconductor package <NUM> may include any number of IHSs <NUM>, TIMs <NUM>, thermally conductive slugs 141a-b, bottom dies 121a-b, sets of top dies 110a-b, and package substrates <NUM> with bridges <NUM>.

For one embodiment, the semiconductor package <NUM> may include a ball grid array (BGA) package, a land grid array (LGA) package, and/or a pin grid array (PGA) package. In other embodiments, one or more of the bottom dies 121a-b, the top dies 110a-b, and/or the package substrate <NUM> may be coupled via solder balls (or the like) that may be implemented as solder bumps/joints formed from respective microbumps. A solder ball (or joint) formed by soldering of a microbump according to an embodiment may itself be referred to as a "bump" and/or a "microbump. " Additionally, for other embodiments, one or more of the top dies <NUM>10a-b, the bottom dies 121a-b, and the package substrate <NUM> may be coupled using an anisotropic conductive film (ACF) or the like.

The package substrate <NUM> may include a variety of electronic structures formed thereon or therein. In certain embodiments, the package substrate <NUM> may be an organic substrate made up of one or more layers of polymer base materials or ceramic base materials, with conducting regions for transmitting signals. For some embodiments, the package substrate <NUM> may include, but is not limited to, a package, a substrate, a printed circuit board (PCB), and a motherboard. In one embodiment, the package substrate <NUM> is a PCB. For one embodiment, the PCB is made of an FR-<NUM> glass epoxy base with thin copper foil laminated on both sides. For certain embodiments, a multilayer PCB can be used, with pre-preg and copper foil used to make additional layers. For example, the multilayer PCB may include one or more dielectric layers, where the dielectric layers may be a photosensitive dielectric layer. For one embodiment, the PCB may also include one or more conductive layers, which may further include copper (or metallic) traces, lines, pads, vias, holes, and/or planes.

For one embodiment, the bottom dies 121a-b and the top dies 110a-b may be comprised, but are not limited to, a semiconductor die, an electronic device (e.g., a wireless device), an integrated circuit (IC), a central processing unit (CPU), a graphic processing unit (GPU), a microprocessor, a platform controller hub (PCH), a memory (e.g., a high bandwidth memory (HBM)), and/or a field-programmable gate array (FPGA). Additionally, in other embodiments, the bottom dies 121a-b may be comprised of one or more materials, including glass, crystal, diamond, low thermal conductive materials, high thermal conductive materials (e.g., gallium nitride (GaN) or the like), silicon, glass-based materials, and/or silicon-based materials (e.g., silicon carbide (SiC) or the like). As described above, in some embodiments, the top dies 110a-b may be a plurality of chiplet dies. While, in another embodiment, the top dies 110a and/or the top dies 110b may be a single monolithic die instead of multiple chiplet dies. The bottom dies 121a-b and the top dies 110a-b may be formed from a material such as silicon and have circuitry thereon that is to be coupled to the package substrate <NUM> and/or each other. Although some embodiments are not limited in this regard, the package substrate <NUM> may in turn be coupled to another body, for example, a computer motherboard (or the like).

For one embodiment, the bottom dies 121a may have a thickness that is substantially equal to a thickness of the bottom dies 121b. For one embodiment, the bottom dies 121a-b may have a thickness of approximately <NUM> or less. In some embodiments, the top dies 110a may have a thickness that is substantially equal to a thickness of the top dies 110b. For one embodiment, the top dies 110a-b may have a thickness of approximately <NUM> to <NUM>. In some embodiments, the top dies 110a-b may have a thickness that is substantially equal or different from a thickness of bottom dies 121a-b. For one embodiment, the top dies 110a-b may have a top surface that is substantially coplanar to a top surface of the encapsulation layer <NUM>. Note that, in some embodiments, the thickness of the TIM <NUM> disposed over the top dies 110a may be substantially equal to or different from the thickness of the TIM <NUM> that is disposed over the top dies 110b. For one embodiment, the TIM <NUM> may have a thickness of approximately <NUM> to <NUM>.

One or more connections between the package substrate <NUM>, the top dies 110a-b, and the bottom dies 121a-b may include one or more interconnect structures and underfill layers if desired. In some embodiments, these interconnect structures (or connections) may variously comprise an alloy of nickel, palladium, and tin (and, in some embodiments, copper). For one embodiment, the underfill layers may be one or more polymer materials that are injected between the respective components. Alternatively, the underfill layers may be molded underfills (MUF) or the like.

In one embodiment, the encapsulation layer <NUM> may fully and/or partially surround the outer sidewalls of the top die 110a-b and/or the thermally conductive slugs 141a-b. For example, in one embodiment, the encapsulation layer <NUM> may fully surround the thermally conductive slug 141b, whereas the encapsulation layer <NUM> may be disposed between the outer sidewalls of the top dies <NUM> and the thermally conductive slugs 141a. Note that, in alternate embodiments, the encapsulation layer <NUM> may be implemented to partially or fully surround the bottom dies 121a-b. In some embodiments the encapsulation layer <NUM> may include one or more encapsulation materials such as a mold material, an underfill material, a filler material, any similar materials, and/or any combination thereof.

Additionally, as described above, the thermally conductive slugs 141a-b may be disposed directly on the top outer edges of the bottom dies 121a-b. Furthermore, in these embodiments, one of the thermally conductive slugs 141a may be respectively positioned on one of the bottom dies 121a-b and the package substrate <NUM> (e.g., as shown with the two thermally conductive slugs 141a on the left and right), and the thermally conductive slug 141b is directly positioned on both of the bottom dies 121a-b (e.g., as shown with the one thermally conductive slug 141b in the middle). As such, in these embodiments, as shown in <FIG>, the thermally conductive slugs 141a-b may have the same widths or different widths based on the desired packaging design.

According to some embodiments, the thermally conductive slugs 141a-b may be comprised of copper or the like. Likewise, in some embodiments, the thermally conductive slugs 141a-b may be comprised of one or more highly thermal conductive materials, such as, but not limited to, copper, silver, boron nitride, graphene, and/or the like. For example, in these embodiments, the thermally conductive slugs 141a-b may have a high thermal conductivity of approximately <NUM> W/mK or greater.

In some embodiments, the thermally conductive slugs 141a-b may have one or more thicknesses, where the thermally conductive slugs 141a may have a first thickness, and the thermally conductive slug 141b may have a second thickness. For example, the first thickness of the thermally conductive slugs 141a may be greater than the second thickness of the thermally conductive slug 141b, where the first thickness of the thermally conductive slugs 141a may be defined from the top surface of the package substrate <NUM> to the bottom surface of the TIM <NUM>, and where the second thickness of the thermally conductive slug 141b may be defined from the top surfaces of the bottom dies 121a-b to the bottom surface of the TIM <NUM>.

In these embodiments, the first thickness of the thermally conductive slugs 141a may be approximately <NUM> to <NUM>. In another embodiment, the first thickness of the thermally conductive slugs 141a may be approximately <NUM> or less. In some embodiments, the second thickness of the thermally conductive slug 141b may be approximately <NUM> to <NUM>. In another embodiment, the second thickness of the thermally conductive slugs 141b may be approximately <NUM> or less.

Moreover, as shown in <FIG>, the thermally conductive slugs 141a may be shaped as thermally conductive block regions with pedestals (or legs). In these embodiments, the thermally conductive slugs 141a may have two different thicknesses, where the thermally conductive block regions of the thermally conductive slugs 141a may be directly disposed and coupled onto the top outer edges of the bottom dies 121a-b, and where the pedestals of the thermally conductive slugs 141a may be directly disposed and coupled onto the top surface of the package substrate <NUM>. That is, in these embodiments, the thermally conductive block regions of the thermally conductive slugs 141a may have a thickness that is substantially equal to the second thickness of the thermally conductive slug 141b (e.g., a thickness of approximately <NUM> to <NUM>), while the thermally conductive pedestals of the thermally conductive slugs 141a may have a thickness that is substantially equal to the first thickness of the thermally conductive slug 141a (e.g., a thickness of approximately <NUM> to <NUM>). Note that, as shown in <FIG>, a slight gap may be implemented between the pedestals of the thermally conductive slugs 141a and the outer sidewalls of the bottom dies 121a-b. Additionally, in some embodiments, the thermally conductive block regions of the thermally conductive slugs 141a, the thermally conductive slug 141b, and/or the trenches <NUM> may have one or more sidewalls that are shaped as tapered sidewalls and/or substantially vertical sidewalls.

Furthermore, the TIM <NUM> may be directly disposed and coupled onto the top surfaces of the top dies <NUM>10a-b, the encapsulation layer <NUM>, and/or the thermally conductive slugs 141a-b, where the TIM <NUM> may be positioned between the top surfaces of the top dies 110a-b and the bottom surface of the IHS <NUM>. In one embodiment, the TIM <NUM> may be a solder TIM (STIM) such as an indium STIM or the like. In other embodiments, the TIM <NUM> may include one or more highly thermal conductivity materials such as a metallic TIM, a STIM, a polymer TIM (PTIM), and/or any similar highly thermal conductive material(s). The TIM <NUM> may be two split/separated TIMs or one single/shared TIM based on the desired packaging design.

In one embodiment, the IHS <NUM> may be disposed over the TIM <NUM>, the top dies 110a-b, the bottom dies 121a-b, and the package substrate <NUM>. The IHS <NUM> may be manufactured (or shaped) to include a lid and/or a plurality of legs (or pedestals), where the lid of the IHS <NUM> may be directly disposed on the top surface of the TIM <NUM>, and the legs of the IHS <NUM> may be directly disposed on the top surface of the package substrate <NUM>. In some embodiments, the IHS <NUM> may be a heatsink, a heat spreader, a heat exchanger, a manifold, a cold plate, and/or any similar thermal solution (or device) that may be used to help transfer the heat from the electrical components of the semiconductor package <NUM> to the ambient environment (or an additional heat spreader). In some embodiments, the IHS <NUM> may be a shared heatsink disposed over both the top dies 110a-b, or the IHS <NUM> may be a split heatsink separated into two separate heatsinks individually disposed over the top dies 110a only and the top dies 110b only.

Note that the semiconductor package <NUM> of <FIG> may include fewer or additional packaging components based on the desired packaging design.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the semiconductor package <NUM> may be substantially similar to the semiconductor package <NUM> described above in <FIG>, with the exception that an active die <NUM> may be disposed on the top inner edges of both of the bottom dies 121a-b, and that the active die <NUM> may thus replace the thermally conductive slug 141b and the bridge <NUM> of <FIG>. That is, whereas the bridge <NUM> is embedded within the package substrate <NUM> of <FIG>, the active die <NUM> may be disposed and coupled onto the top inner edges of both of the bottom dies 121a-b, where the active die <NUM> may be implemented to communicatively couple the stack of the top dies 110a and bottom die 121a to the stack of the top dies 110b and bottom die 121b without requiring an embedded bridge in the package substrate <NUM>, according to some embodiments.

In these embodiments, the active die <NUM> may be an active silicon die or the like. As shown in <FIG>, the active die <NUM> may be surrounded (or embedded) with the encapsulation layer <NUM>, the TIM <NUM>, and the bottom dies 121a-b, where the active die <NUM> may be directly positioned between the top dies 110a and the top dies 110b. In one embodiment, the active die <NUM> may have a top surface that is substantially coplanar to the top surfaces of the top dies 110a-b, where the active dies <NUM> may have a thickness that is substantially equal to the thickness of the top dies <NUM>10a-b (e.g., the thickness may be approximately <NUM> to <NUM>). Moreover, in some embodiments, the active die <NUM> may have a width of approximately <NUM> to <NUM>. While, in another embodiment, the active die <NUM> may have a width of approximately <NUM> or less.

In particular, for these embodiments, the active die <NUM> may be a bridge (or a bridge die). For one embodiment, the active die <NUM> may comprise electrical routings (or interconnect structures) that may communicatively couple the bottom die 121a to the bottom die 121b. In an embodiment, the active die <NUM> may be a silicon bridge, a glass bridge, or a bridge made of any other substrate material that is suitable for forming bridges. In some embodiments, the active die <NUM> may be referred to as an EMIB. For additional embodiments, the active die <NUM> may include a plurality of TSVs that may be used to communicatively couple the bottom dies 121a-b and/or the top dies 110a-b.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the semiconductor package <NUM> may be substantially similar to the semiconductor package <NUM> described above in <FIG>, with the exception that the IHS <NUM> may include a plurality of pedestals 120a-b, and that the pedestals 120a-b of the IHS <NUM> may replace the thermally conductive slugs 140a-b of <FIG>. That is, whereas the thermally conductive slugs 141a-b are disposed and coupled onto the top surfaces of the bottom dies 121a-b of <FIG>, the pedestals 120a-b of the IHS <NUM> may be disposed and directly coupled onto the top surfaces of the bottom dies 121a-b, where the pedestals 120a-b may be part of the IHS <NUM> and/or directly coupled onto the bottom surface of the IHS <NUM>, according to some embodiments.

In these embodiments, the pedestals 120a-b may be implemented as a plurality of legs on the IHS <NUM>, where the pedestals 120a-b may be comprised of the same thermally conductive material as the IHS <NUM>. As shown in <FIG>, the pedestals 120a-b may be surrounded (or embedded) with the encapsulation layer <NUM>, the TIM <NUM>, and the bottom dies 121a-b, where the pedestals 120a-b may be directly positioned between the top surfaces of the bottom dies 121a-b and the bottom surface of the IHS <NUM>. In one embodiment, the pedestals 120a-b of the IHS <NUM> may have a thickness of approximately <NUM> to <NUM>. While, in another embodiment, the pedestals 120a-b of the IHS <NUM> may have a thickness of approximately <NUM> or less. In these embodiments, the pedestals 120a-b of the IHS <NUM> may have a thickness that is greater than (or greater than or equal to) a thickness of the top dies 110a-b.

Moreover, in some embodiments, the pedestal 120b (or a second pedestal) may have a width of approximately <NUM> to <NUM>. While, in another embodiment, the pedestal 120b may have a width of approximately <NUM> or less. In these embodiments, the pedestal 120b may have a width that is greater than a width of the pedestals 120a (or a plurality of first pedestals). In some embodiments, the pedestals 120a-b may have one or more sidewalls that are shaped as tapered sidewalls and/or substantially vertical sidewalls. In an alternative embodiment, the pedestal 120b may be replaced with an active die similar to the active die <NUM> described above in <FIG>.

<FIG> are cross-sectional illustrations of a semiconductor package <NUM>, in accordance with some embodiments. For some embodiments, as shown in <FIG>, the semiconductor package <NUM> may include an IHS <NUM>, a TIM <NUM>, an encapsulation layer <NUM>, a plurality of trenches <NUM>, a plurality of thermally conductive slugs 241a-b, a plurality of top dies 210a-b, a plurality of bottom dies 221a-b, a plurality of interconnects <NUM>, an adhesive layer <NUM>, a bridge <NUM>, and a package substrate <NUM>. In these embodiments, the semiconductor package <NUM> of <FIG> with the thermally conductive slugs 241a-b may be substantially similar to the semiconductor package <NUM> with the thermally conductive slugs 141a-b described above in <FIG>.

Likewise, the components of the semiconductor package <NUM> may be substantially similar to the components of the semiconductor package <NUM> described above in <FIG>. Accordingly, the IHS <NUM>, the TIM <NUM>, the encapsulation layer <NUM>, the trenches <NUM>, the top dies 210a-b, the bottom dies 221a-b, the interconnects <NUM>, the adhesive layer <NUM>, the bridge <NUM>, and the package substrate <NUM> may be substantially similar to the IHS <NUM>, the TIM <NUM>, the encapsulation layer <NUM>, the trenches <NUM>, the top dies <NUM>10a-b, the bottom dies 121a-b, the interconnects <NUM>, the adhesive layer <NUM>, the bridge <NUM>, and the package substrate <NUM> described above in <FIG>.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the semiconductor package <NUM> may include the top dies 210a-b and bottom dies 221a-b respectively stacked on the package substrate <NUM>, where the bottom dies 221a-b may be coupled to the package substrate <NUM> with the adhesive layer <NUM>. The encapsulation layer <NUM> may be disposed over the top surface of the bottom dies 221a-b and surrounds the top dies 210a-b, where the encapsulation layer <NUM> may be particularly disposed on the top outer edges of the bottom dies 221a-b. In some embodiments, the top surface of the encapsulation layer <NUM> may be planarized with a polishing/grinding process (or the like) and may thus be substantially coplanar to the top surface of the top dies 210a-b.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the semiconductor package <NUM> may implement the trenches <NUM> into the encapsulation layer <NUM>, where the trenches <NUM> may expose the top surface of the bottom dies 221a-b. In an embodiment, the trenches <NUM> may be implemented with a drilling process, a laser process, or the like, where the drilled/lasered trenches may have tapered sidewalls or substantially vertical sidewalls. As described above, the trenches <NUM> may provide openings over the top edges of the bottom dies 221a-b.

Referring now to <FIG>, a cross-sectional illustration of a semiconductor package <NUM> is shown, in accordance with an embodiment. For some embodiments, the thermally conductive slugs 241a-b may be disposed (or deposited/plated) into the trenches <NUM> with a plating process (or the like) to implement the thermally conductive slugs 241a-b directly on the top edges of the respective bottom dies 221a-b. In these embodiments, the TIM <NUM> may then be disposed over the thermally conductive slugs 241a-b, the encapsulation layer <NUM>, and the top dies 210a-b. Lastly, as shown in <FIG>, the IHS <NUM> may be disposed over the TIM <NUM> and the package substrate <NUM>, where the thermally conductive slugs 241a-b may thus create a low thermal resistance path from the top edges of the bottom dies 221a-b to the TIM <NUM> and the IHS <NUM> - and thus substantially improve the TDP of the semiconductor package <NUM>. Furthermore, in alternative embodiments, the semiconductor package <NUM> may be implemented with an active die (e.g., the active die <NUM> of <FIG>) and/or one or more pedestals with the IHS <NUM> (e.g., the pedestals 120a-b of <FIG>).

<FIG> is an illustration of a schematic block diagram illustrating a computer system <NUM> that utilizes a device package <NUM> (or a semiconductor package) with an IHS, a TIM, a plurality of top dies, a plurality of bottom dies, a plurality of thermally conductive slugs, a plurality of pedestals of an IHS, an active die, and/or a package substrate, according to one embodiment. <FIG> illustrates an example of computing device <NUM>. Computing device <NUM> houses a motherboard <NUM>. Motherboard <NUM> may include a number of components, including but not limited to processor <NUM>, device package <NUM> (or semiconductor package), and at least one communication chip <NUM>. Processor <NUM> is physically and electrically coupled to motherboard <NUM>. For some embodiments, at least one communication chip <NUM> is also physically and electrically coupled to motherboard <NUM>. For other embodiments, at least one communication chip <NUM> is part of processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

At least one communication chip <NUM> enables wireless communications for the transfer of data to and from computing device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. At least one communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. Computing device <NUM> may include a plurality of communication chips <NUM>.

Processor <NUM> of computing device <NUM> includes an integrated circuit die packaged within processor <NUM>. Device package <NUM> may be a semiconductor package that may include, but is not limited to, a substrate, a package substrate, and/or a PCB. In one embodiment, device package <NUM> may be substantially similar to the semiconductor packages <NUM>-<NUM> and <NUM> of <FIG> and <FIG> described herein. Device package <NUM> may include the thermally conductive slugs (and/or the active die, the pedestals of the IHS, etc.) directly disposed and coupled onto the top surfaces of the bottom dies and/or the package substrate as described herein (e.g., as illustrated and described above with the thermally conductive slugs, the active die, and/or the pedestals of the IHS of <FIG> and <FIG>) - or any other components from the figures described herein.

Note that device package <NUM> may be a single component/device, a subset of components, and/or an entire system, as the materials, features, and components may be limited to device package <NUM> and/or any other component of the computing device <NUM> that may need the thermally conductive slugs (and/or the active die, the pedestals of the IHS, etc.) as described herein (e.g., the motherboard <NUM>, the processor <NUM>, and/or any other component of the computing device <NUM> that may need the embodiments of the semiconductor packages described herein).

For certain embodiments, the integrated circuit die may be packaged with one or more devices on a package substrate that includes a thermally stable RFIC and antenna for use with wireless communications and the device package, as described herein, to reduce the z-height of the computing device. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

At least one communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. For some embodiments, the integrated circuit die of the communication chip <NUM> may be packaged with one or more devices on a package substrate that includes one or more device packages, as described herein.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

The following examples pertain to further embodiments:
Example <NUM> is a semiconductor package, comprising: a first bottom die and a second bottom die on a package substrate, wherein the first bottom die is adjacent to the second bottom die; a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die; a plurality of thermally conductive slugs on the first bottom die and the second bottom die, wherein the plurality of thermally conductive slugs are comprised of a high thermal conductive material, and wherein the plurality of thermally conductive slugs include a plurality of first thermally conductive slugs and a second thermally conductive slug; an encapsulation layer over the first and second bottom dies, wherein the encapsulation layer surrounds the plurality of first top dies, the plurality of second top dies, and the second thermally conductive slug; and a TIM over the plurality of first top dies, the plurality of second top dies, the plurality of thermally conductive slugs, and the encapsulation layer.

In example <NUM>, the subject matter of example <NUM> can optionally include that the plurality of first thermally conductive slugs are positioned directly on a top surface of the package substrate, wherein the plurality of first thermally conductive slugs are also positioned directly on an outer edge of a top surface of the first bottom die and an outer edge of a top surface of the second bottom die, and wherein the second thermally conductive slug is positioned directly on an inner edge of the top surface of the first bottom die and an inner edge of the top surface of the second bottom die.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of thermally conductive slugs have top surfaces that are substantially coplanar to a top surface of the encapsulation layer and a top surface of the plurality of first and second top dies.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the high thermal conductive material of the plurality of thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of first thermally conductive slugs have a first thickness that is greater than a second thickness of the second thermally conductive slug.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the second thickness of the second thermally conductive slug is substantially equal to a thickness of the plurality of first and second top dies.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the top surface of the first bottom die is substantially coplanar to the top surface of the second bottom die, wherein the plurality of first thermally conductive slugs are shaped as a plurality of thermally conductive block regions with a plurality of pedestals, wherein the plurality of thermally conductive block regions of the plurality of first thermally conductive slugs have a third thickness that is substantially equal to the second thickness of the second thermally conductive slug, wherein the first thickness of the plurality of first thermally conductive slugs is greater than the third thickness of the plurality of first thermally conductive slugs, wherein the thermally conductive block regions of the plurality of first thermally conductive slugs are coupled directly on the outer edges of the top surfaces of the first and second bottom dies, wherein the plurality of pedestals of the plurality of first thermally conductive slugs are coupled directly on the top surface of the package substrate, wherein the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and wherein the plurality of first thermally conductive slugs are separated from the plurality of respective first and second top dies by the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include a bridge in the package substrate, wherein the bridge communicatively couples the first bottom die to the second bottom die, wherein the first and second bottom dies include a plurality of interconnects, and wherein the plurality of interconnects of the first and second bottom dies communicatively couple the package substrate to the plurality of respective first and second top dies; an adhesive layer couples the package substrate to the first and second bottom dies; and an IHS over the TIM, the plurality of thermally conductive slugs, and the package substrate, wherein the plurality of thermally conductive slugs thermally couple the top surfaces of the first and second bottom dies to the IHS, and wherein the TIM is positioned between a bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of thermally conductive slugs, and the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of pedestals of the plurality of first thermally conductive slugs are separated from the respective first and second bottom dies by a slight gap, and wherein the plurality of thermally conductive slugs have tapered sidewalls or substantially vertical sidewalls.

Example <NUM> is a semiconductor package, comprising: a first bottom die and a second bottom die on a package substrate, wherein the first bottom die is adjacent to the second bottom die; a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die; a plurality of thermally conductive slugs on the first bottom die and the second bottom die, wherein the plurality of thermally conductive slugs are comprised of a high thermal conductive material; an active die on the first bottom die and the second bottom die, wherein the active die communicatively couples the first bottom die to the second bottom die; an encapsulation layer over the first and second bottom dies, wherein the encapsulation layer surrounds the plurality of first top dies, the plurality of second top dies, and the active die; and a TIM over the plurality of first top dies, the plurality of second top dies, the plurality of thermally conductive slugs, the active die, and the encapsulation layer.

In example <NUM>, the subject matter of example <NUM> can optionally include that the plurality of thermally conductive slugs are positioned directly on a top surface of the package substrate, wherein the plurality of thermally conductive slugs are also positioned directly on an outer edge of a top surface of the first bottom die and an outer edge of a top surface of the second bottom die, and wherein the active die is positioned directly on an inner edge of the top surface of the first bottom die and an inner edge of the top surface of the second bottom die.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of thermally conductive slugs have top surfaces that are substantially coplanar to a top surface of the encapsulation layer and a top surface of the plurality of first and second top dies, and wherein the active die has a top surface that is substantially coplanar to the top surfaces of the plurality of thermally conductive slugs, the plurality of first and second top dies, and the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the high thermal conductive material of the plurality of thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene, and wherein the active die is an active silicon die or an EMIB die.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of thermally conductive slugs have a first thickness that is greater than a second thickness of the active die.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the second thickness of the active die is substantially equal to a thickness of the plurality of first and second top dies.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the top surface of the first bottom die is substantially coplanar to the top surface of the second bottom die, wherein the plurality of thermally conductive slugs are shaped as a plurality of thermally conductive block regions with a plurality of pedestals, wherein the plurality of thermally conductive block regions of the plurality of thermally conductive slugs have a third thickness that is substantially equal to the second thickness of the active die, wherein the first thickness of the plurality of thermally conductive slugs is greater than the third thickness of the plurality of thermally conductive slugs, wherein the thermally conductive block regions of the plurality of thermally conductive slugs are coupled directly on the outer edges of the top surfaces of the first and second bottom dies, wherein the plurality of pedestals of the plurality of thermally conductive slugs are coupled directly on the top surface of the package substrate, wherein the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and wherein the plurality of thermally conductive slugs are separated from the plurality of respective first and second top dies by the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that a plurality of interconnects in the first and second bottom dies, wherein the plurality of interconnects of the first and second bottom dies communicatively couple the package substrate to the plurality of respective first and second top dies; an adhesive layer couples the package substrate to the first and second bottom dies; and an IHS over the TIM, the plurality of thermally conductive slugs, the active die, and the package substrate, wherein the plurality of thermally conductive slugs thermally couple the top surfaces of the first and second bottom dies to the IHS, and wherein the TIM is positioned between a bottom surface of the IHS and the top surfaces of the first and second top dies, the plurality of thermally conductive slugs, the active die, and the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the plurality of pedestals of the plurality of thermally conductive slugs are separated from the respective first and second bottom dies by a slight gap, and wherein the plurality of thermally conductive slugs have tapered sidewalls or substantially vertical sidewalls.

Example <NUM> is a semiconductor package, comprising: a first bottom die and a second bottom die on a package substrate, wherein the first bottom die is adjacent to the second bottom die, wherein the package substrate includes a bridge that communicatively couples the first bottom die to the second bottom die; a plurality of first top dies on the first bottom die, and a plurality of second top dies on the second bottom die; an encapsulation layer over the first and second bottom dies; a TIM over the plurality of first top dies, the plurality of second top dies, and the encapsulation layer; and an IHS with a plurality of pedestals over the TIM, the first and second bottom dies, and the package substrate, wherein the plurality of pedestals of the IHS are on the first bottom die and the second bottom die, wherein the plurality of pedestals of the IHS are comprised of a high thermal conductive material, wherein the pedestals of the IHS include a plurality of first pedestals and a second pedestal, and wherein the encapsulation layer surrounds the plurality of first top dies, the plurality of second top dies, and the pedestals of the IHS.

In example <NUM>, the subject matter of example <NUM> can optionally include that the plurality of first pedestals are positioned directly on an outer edge of a top surface of the first bottom die and an outer edge of a top surface of the second bottom die, and wherein the second pedestal is positioned directly on an inner edge of the top surface of the first bottom die and an inner edge of the top surface of the second bottom die.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the encapsulation layer has a top surface that is substantially coplanar to a top surface of the plurality of first and second top dies, wherein the pedestals of the IHS have a thickness that is greater than a thickness of the plurality of first and second top dies, and wherein the plurality of first pedestals have a first width that is greater than a second width of the second pedestal.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the high thermal conductive material of the pedestals of the IHS is comprised of copper, silver, boron nitride, or graphene, wherein the first and second bottom dies include a plurality of interconnects, wherein the plurality of interconnects of the first and second bottom dies communicatively couple the package substrate to the plurality of respective first and second top dies, wherein the package substrate is coupled to the first and second bottom dies with an adhesive layer, wherein the plurality of pedestals of the IHS are thermally coupled to the top surfaces of the first and second bottom dies, and wherein the TIM is positioned between a bottom surface of the IHS and the top surfaces of the first and second top dies and the encapsulation layer.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the second pedestal of the IHS is surrounded by the encapsulation layer and the TIM.

In example <NUM>, the subject matter of examples <NUM>-<NUM> can optionally include that the top surface of the first bottom die is substantially coplanar to the top surface of the second bottom die, wherein the encapsulation layer is directly on the top surfaces of the first and second bottom dies, and wherein the plurality of first pedestals of the IHS are separated from the plurality of respective first and second top dies by the encapsulation layer.

Claim 1:
A semiconductor package (<NUM>), comprising:
a first bottom die (121a) and a second bottom die (121b) on a package substrate (<NUM>), wherein the first bottom die is adjacent to the second bottom die;
a plurality of first top dies (<NUM>10a) on the first bottom die, and a plurality of second top dies (110b) on the second bottom die;
a plurality of thermally conductive slugs (141a,b) on the first bottom die and the second bottom die, wherein the plurality of thermally conductive slugs are comprised of a high thermal conductive material, and wherein the plurality of thermally conductive slugs include a plurality of first thermally conductive slugs (141a) and a second thermally conductive slug (141b), wherein the second thermally conductive slug is directly positioned on the first bottom die and the second bottom die;
an encapsulation layer (<NUM>) over the first and second bottom dies, wherein the encapsulation layer surrounds the plurality of first top dies, the plurality of second top dies, and the second thermally conductive slug; and
a thermal interface material (<NUM>), TIM, over the plurality of first top dies, the plurality of second top dies, the plurality of thermally conductive slugs, and the encapsulation layer.