Patent Description:
A storage device may refer to a nonvolatile medium that retains stored data even when power is turned off. The storage device may be used to store original data of various software such as an operating system and applications. The storage device is widely used as an essential component in various electronic devices.

With the expansion of fields where the storage device is used, various distinct characteristics (or features) may be required or desired by the storage device. For example, in a specific application field, a distinct characteristic that a storage device off-loads a load of a host device may be required or desired. Alternatively, in another specific application field, there may be a need or desire to implement a storage device with low costs without a complicated function.

<CIT> discloses systems and methods for memory reads.

Example embodiments of the present disclosure provide a storage device decreasing a read latency in a copy operation associated with a zoned storage space and an operating method of the storage device.

According to an example embodiment, a storage device includes a nonvolatile memory device, and a controller configured to partition a storage space of the nonvolatile memory device into a plurality of zones and access the storage space. Each of the plurality of zones corresponds to consecutive physical addresses of the nonvolatile memory device, and the controller is configured to map the consecutive physical addresses of each of the plurality of zones onto consecutive logical addresses. In response to a copy command being received from an external host device, the controller is configured to start a copy operation for copying data of a first zone of the plurality of zones to a second zone of the plurality of zones and sends first read commands and first write commands to the nonvolatile memory device. In response to a suspend command being received from the external host device before the copy operation is completed, the controller is configured to suspend the copy operation, store progress status information about the copy operation, and send a suspend response to the external host device.

According to an example embodiment, a storage device includes a nonvolatile memory device, and a controller configured to partition a storage space of the nonvolatile memory device into a plurality of zones, and access the storage space. Each of the plurality of zones corresponds to consecutive physical addresses of the nonvolatile memory device, and the controller is configured to map the consecutive physical addresses of each of the plurality of zones onto consecutive logical addresses. In response to a first UFS protocol information unit (UPIU) being received from an external host device, the controller is configured to start a copy operation for copying data of a first zone of the plurality of zones to a second zone of the plurality of zones and send first read commands and first write commands to the nonvolatile memory device. In response to a second UPIU being received from the external host device before the copy operation is completed, the controller is configured to suspend the copy operation, store progress status information about the copy operation, and send a response UPIU to the external host device.

According to an example embodiment, an operating method of a storage device which includes a nonvolatile memory device and a controller includes receiving, at the controller, a copy command from an external host device, starting, at the controller, a copy operation for copying data of a first zone of a plurality of zones mapped onto a storage space of the nonvolatile memory device to a second zone of the plurality of zones to send first read commands and first write commands to the nonvolatile memory device, receiving, at the controller, a suspend command from the external host device, suspending, at the controller, the copy operation in response to the suspend command and sending a suspend response to the external host device, receiving, at the controller, a second read command from the external host device, reading, at the controller, data from the nonvolatile memory device in response to the second read command and sending a read response including the read data to the external host device, and resuming, at the controller, the suspended copy operation.

The above and other objects and features of the present disclosure will become apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

Below, example embodiments of the present disclosure may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the example embodiments. Below, the term "and/or" is interpreted as including any one of items listed with regard to the term, or a combination of some of the listed items.

<FIG> is a block diagram illustrating a host-storage system <NUM> according to some example embodiments of the present disclosure.

Referring to <FIG>, the host-storage system <NUM> may include a host <NUM> and a storage device <NUM>. Also, the storage device <NUM> may include a storage controller <NUM> and a nonvolatile memory (NVM) <NUM>. Also, according to some example embodiments of the present disclosure, the host <NUM> may include a host controller <NUM> and a host memory <NUM>. The host memory <NUM> may function as a buffer memory for temporarily storing data to be transmitted to the storage device <NUM> or data transmitted from the storage device <NUM>.

The storage device <NUM> may include storage mediums for storing data depending on a request from the host <NUM>. As an example, the storage device <NUM> may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. In the case where the storage device <NUM> is an SSD, the storage device <NUM> may be a device complying with the non-volatile memory express (NVMe) standard. In the case where the storage device <NUM> is an embedded memory or an external memory, the storage device <NUM> may be a device complying with the universal flash storage (UFS) or embedded multi-media card (eMMC) standard. Each of the host <NUM> and the storage device <NUM> may generate a packet complying with a standard protocol applied thereto and may send the generated packet.

When the nonvolatile memory <NUM> of the storage device <NUM> includes a flash memory, the flash memory may include a two-dimensional (2D) NAND flash memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. As another example, the storage device <NUM> may be implemented with various kinds of different nonvolatile memories. For example, the storage device <NUM> may include a magnetic RAM (MRAM), a spin-transfer torque MRAM (STT-MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), or at least one of various kinds of different memories.

According to some example embodiments, the host controller <NUM> and the host memory <NUM> may be implemented with separate semiconductor chips. Alternatively, in some example embodiments, the host controller <NUM> and the host memory <NUM> may be implemented in the same semiconductor chip. As an example, the host controller <NUM> may be one of a plurality of modules included in an application processor; in this case, the application processor may be implemented with a system on chip (SoC). Also, the host memory <NUM> may be an embedded memory included in the application processor or may be a nonvolatile memory or a memory module disposed outside the application processor.

The host controller <NUM> may manage an operation of storing data (e.g., write data) of a buffer region of the host memory <NUM> in the nonvolatile memory <NUM> or storing data (e.g., read data) of the nonvolatile memory <NUM> in the buffer region.

The storage controller <NUM> may include a host interface (I/F) <NUM>, a memory interface (I/F) <NUM>, and a central processing unit (CPU) <NUM>. Also, the storage controller (STRG CTRL) <NUM> may further include a flash translation layer (FTL) <NUM>, a packet manager (PCK MNG) <NUM>, a buffer memory (BUF MEM) <NUM>, an error correction code (ECC) engine (ECC ENG)<NUM>, and an advanced encryption standard (AES) engine (AES ENG) <NUM>. The storage controller <NUM> may further include a working memory (not illustrated) onto which the flash translation layer <NUM> is loaded, and data write and read operations of the nonvolatile memory <NUM> may be controlled as the CPU <NUM> executes the flash translation layer <NUM>.

The host interface <NUM> may exchange packets with the host <NUM>. The packet that is transferred from the host <NUM> to the host interface <NUM> may include a command or data to be written in the nonvolatile memory <NUM>, and the packet that is transferred from the host interface <NUM> to the host <NUM> may include a response to the command or data read from the nonvolatile memory <NUM>. The memory interface <NUM> may provide the nonvolatile memory <NUM> with data to be written in the nonvolatile memory <NUM>, or may receive data read from the nonvolatile memory <NUM>. The memory interface <NUM> may be implemented to comply with the standard such as Toggle or ONFI (Open NAND Flash Interface).

The flash translation layer <NUM> may perform various functions such as an address mapping and wear-leveling. The address mapping operation refers to an operation of translating a logical address received from the host <NUM> into a physical address to be used to store data in the nonvolatile memory <NUM>. The wear-leveling that is a technology for allowing blocks in the nonvolatile memory <NUM> to be used uniformly such that excessive degradation of a specific block is prevented (or hindered) may be implemented, for example, through a firmware technology for balancing erase counts of physical blocks.

The packet manager <NUM> may generate a packet complying with a protocol of an interface agreed with the host <NUM> or may parse various kinds of information from the packet received from the host <NUM>. Also, the buffer memory <NUM> may temporarily store data to be written in the nonvolatile memory <NUM> or data read from the nonvolatile memory <NUM>. The buffer memory <NUM> may be a component provided within the storage controller <NUM>; however, it may be possible to dispose the buffer memory <NUM> outside the storage controller <NUM>.

The ECC engine <NUM> may perform an error detection and correction function on data read from the nonvolatile memory <NUM>. In detail, the ECC engine <NUM> may generate parity bits for write data to be stored in the nonvolatile memory <NUM>, and the parity bits thus generated may be stored in the nonvolatile memory <NUM> together with the write data. When data are read from the nonvolatile memory <NUM>, the ECC engine <NUM> may correct an error of the read data by using parity bits read from the nonvolatile memory <NUM> together with the read data and may output the error-corrected read data.

The AES engine <NUM> may perform at least one of an encryption operation and a decryption operation on data input to the storage controller <NUM> by using a symmetric-key algorithm.

In some example embodiments, the storage device <NUM> may be a zoned device. A storage space of the storage device <NUM> may be partitioned into a plurality of zones. The storage device <NUM> may support only a sequential write operation in each of the plurality of zones. In each of the plurality of zones of the storage device <NUM>, a random write operation may be inhibited. The storage device <NUM> may be implemented based on various standards such as ZNS (Zoned NameSpace), and ZBD (Zoned Block Device).

<FIG> illustrates an example in which a storage space of the storage device <NUM> is partitioned into zones.

Referring to <FIG> and <FIG>, a storage space of the storage device <NUM> may be partitioned into first to m-th zones Z1 to Zm. A storage space of the first zone Z1 may correspond to <NUM>-th to 1n-th logical block addresses LBA11 to LBA1n. A storage space of the second zone Z2 may correspond to <NUM>-th to 2n-th logical block addresses LBA21 to LBA2n. A storage space of the m-th zone Zm may correspond to m1-th to mn-th logical block addresses LBAm1 to LBAmn.

Logical block addresses of each zone may be consecutive. Consecutive logical block addresses of each zone may correspond to consecutive physical block addresses of the nonvolatile memory <NUM>. In each zone, the storage device <NUM> may support a sequential write operation and may not support a random write operation.

The host <NUM> may receive information about the first to m-th zones Z1 to Zm of the storage device <NUM> from the storage device <NUM>. The host <NUM> may open one or more zones of the first to m-th zones Z1 to Zm. The host <NUM> may make a request of the storage device <NUM> for the sequential write operation with regard to the opened zones. The host <NUM> may make a request of the storage device <NUM> for the random or sequential read operation with regard to the first to m-th zones Z1 to Zm.

The host <NUM> may access the storage space of the storage device <NUM> based on logical block addresses. However, an operation in which the host <NUM> erases, invalidates, or discards data of the storage device <NUM> in units of logical block address may be inhibited. The host <NUM> may be permitted to erase, invalidate, or discard data of the storage device <NUM> in units of zone. The host <NUM> may erase, invalidate, or discard the whole data stored in each of the first to m-th zones Z1 to Zm by respectively initializing the first to m-th zones Z1 to Zm.

Because a zone is managed by the host <NUM>, an operation in which the storage controller <NUM> of the storage device <NUM> copies, invalidates, or erases data stored in the nonvolatile memory <NUM> automatically (or internally), for example, through a background operation may be inhibited. Because a zone is managed by the host <NUM>, a mapping table managed by the storage controller <NUM> of the storage device <NUM>, for example, a mapping table of logical block addresses and physical block addresses may be simplified. For example, because the mapping table stores mapping information corresponding to the number of first to m-th zones Z1 to Zm, the size of the mapping table may decrease.

As the size of the mapping table decreases, the size of a buffer memory (e.g., <NUM>) for loading the mapping table may decrease. Accordingly, the host-storage system <NUM> may be implemented at high speed and with low costs in an environment in which a sequential write operation is mainly performed.

<FIG> illustrates an example in which a write operation is performed in the host-storage system <NUM>.

Referring to <FIG> and <FIG>, in operation S110, the host <NUM> may send a write command to the storage controller <NUM>. For example, the write command may include a logical block address or a write pointer. The write pointer may include information about a location of each zone, at which next data will be written.

In operation S120, the storage controller <NUM> may perform an address mapping operation. For example, when the logical block address is included in the write command, the flash translation layer <NUM> of the storage controller <NUM> may translate the logical block address into a physical block address. When the write pointer is included in the write command, the flash translation layer <NUM> of the storage controller <NUM> may translate the write pointer into a physical block address. When the logical block address or the write pointer is not included in the write command, the flash translation layer <NUM> of the storage controller <NUM> may identify a physical block address corresponding to a location of a current write pointer of a zone corresponding to the write command.

In operation S130, the storage controller <NUM> may send the write command including the physical block address to the nonvolatile memory <NUM>. In some example embodiments, the write command in operation S110 and the write command in operation S130 may be expressed by the same term but may be different from each other.

For example, the write command in operation S110 may correspond to an interface between the host <NUM> and the storage controller <NUM>. The write command in operation S110 may be based on a communication protocol such as NVMe (Non Volatile Memory express), UFS (Universal Flash Storage), PCIe (Peripheral Component Interconnect express), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), or SAS (Serial Attached SCSI). For example, the write command in operation S110 may be based on a communication protocol that depends on logical buffering of the storage controller <NUM> such as queuing or write back.

The write command in operation S130 may be based on an interface protocol such as Toggle NAND or ONFI (Open NAND Flash Interface). For example, the write command in operation S130 may be based on a communication protocol supporting only write through, unlike the communication protocol requiring the logical buffering such as queuing or write back.

Below, unless explicitly differently mentioned, a command between the host <NUM> and the storage controller <NUM> and a command between the storage controller <NUM> and the nonvolatile memory <NUM> are interpreted as being distinguished from each other.

The nonvolatile memory <NUM> may perform the write operation in response to the write command in operation S130. When the write operation is completed, the storage controller <NUM> may send a write response to the host <NUM>. For example, in the case where the logical block address or the write pointer is not included in the write command in operation S110, the storage controller <NUM> may notify the host <NUM> of a location where data are written, by returning a logical block address or a write pointer through the write response.

<FIG> illustrates an example of a process in which a copy operation is performed in the host-storage system <NUM>.

Referring to <FIG> and <FIG>, in operation S210, the host <NUM> may send a copy command to the storage controller <NUM>. For example, the copy command may include logical block addresses or a logical block address range of a source zone, and logical block addresses, a logical block address range, or a write pointer of a target zone.

In operation S220, the storage controller <NUM> may perform an address mapping operation. The address mapping operation may be performed as described with reference to operation S120. Afterwards, the storage device <NUM> may start the copy operation. For example, the storage controller <NUM> may copy data of the source zone to the target zone by sending the read command for the source zone to the nonvolatile memory <NUM> (in operation S230) and sending the write command for the target zone to the nonvolatile memory <NUM> (in operation S240). When the copy operation is completed, in operation S250, the storage controller <NUM> may send a copy response to the host <NUM>.

In some example embodiments, the size of data associated with the copy operation for which the host <NUM> makes a request of the storage controller <NUM> may be larger than the size by which a data access to the nonvolatile memory <NUM> is performed (e.g., by which data are written in or read from the nonvolatile memory <NUM>). The storage controller <NUM> may send two or more read commands and two or more write commands to the nonvolatile memory <NUM>.

For example, the storage controller <NUM> may send two or more read commands to the nonvolatile memory <NUM> and may store data read from the nonvolatile memory <NUM>. Afterwards, the storage controller <NUM> may perform the copy operation by sending two or more write commands to the nonvolatile memory <NUM>. As another example, the storage controller <NUM> may repeatedly perform the process, in which a portion of data is copied by sequentially sending the read command and the write command to the nonvolatile memory <NUM>, two or more times. When the whole data is completely copied, the storage controller <NUM> may send the copy response to the host <NUM>.

The storage device <NUM> may be a zoned device. An operation in which the storage controller <NUM> copies or invalidates data of the nonvolatile memory <NUM> internally or automatically, for example, through the background operation may be inhibited. That is, an operation in which the storage controller <NUM> performs the garbage collection operation as the background operation may be inhibited. Accordingly, the host <NUM> may have to support the garbage collection operation of the storage device <NUM>. The host <NUM> may perform garbage collection on the storage device <NUM> by using the copy command. An action may be performed automatically if no outside command is needed for the action to be taken.

<FIG> illustrates an example in which a garbage collection operation is performed by using a copy command.

Referring to <FIG> and <FIG>, 1st D1, 2nd data D2, 3rd data D3, 4th data D4, 5th data D5, 6th data D6, 7th data D7, 8th data D8, and 9th data D9 may be stored in the first zone Z1. 10th data D10, 11the data D11, 12th data D12, 13th data D13, 14th data D14, 15th data D15, 16th data D16, 17th data D17, and 18th data D18 may be stored in the second zone Z2.

The host <NUM> may copy valid data present in the first zone Z1 and the second zone Z2 to the third zone Z3. For example, the host <NUM> may write the 1st data D1, the 2nd data D2, the 3rd data D3, the 5th data D5, and the 6th data D6 in the third zone Z3 by using the copy command. Afterwards, the host <NUM> may write the 12th data D12, the 13th data D13, the 15th data D15, and the 17th data D17 in the third zone Z3 by using the copy command.

When the garbage collection operation is completed, the host <NUM> may initialize the first zone Z1 and the second zone Z2 and may set the first zone Z1 and the second zone Z2 to an empty zone. That is, the garbage collection operation may be performed.

While the garbage collection operation, that is, the copy operation is performed, a read operation for data being copied may be requested by the host <NUM>. For example, while the host <NUM> copies the 1st data D1 of the first zone Z1 to the third zone Z3, a read operation for specific data of the 1st data D1 may be requested by the host <NUM>.

However, the read operation for the corresponding data may be delayed until the copy operation for data associated with the read request is completed. After the copy operation is completed, the host <NUM> may send the read command for the data associated with the read request to the storage controller <NUM>. This may cause a significant increase in the read latency.

Because the size of data to be copied by the copy command for garbage collection is larger than the size of data to be copied by a conventional copy command, the read latency may significantly increase in the garbage collection operation. In the case where the read operation is urgently requested, the increase in the read latency may cause a critical error in the host-storage system <NUM>.

<FIG> illustrates an example of a process in which a copy operation is suspended and resumed in the host-storage system <NUM>.

Referring to <FIG> and <FIG>, in operation S310, the host <NUM> is adapted to send the copy command to the storage controller <NUM>, for example, may send the copy command for garbage collection to the storage controller <NUM>. Operation S310 may be performed to be identical to operation S210.

In operation S320, address mapping is adapted to be performed. Operation S320 may be performed to be identical to operation S220. The storage device <NUM> is adapted to start the copy operation. In operation S330, the storage controller <NUM> is adapted to send the read command to the nonvolatile memory <NUM>. In operation S340, the storage controller <NUM> is adapted to send the write command to the nonvolatile memory <NUM>. Operation S330 and operation S340 may be performed to be identical to operation S230 and operation S240.

When a read operation for data being copied is requested, in operation S350, the host <NUM> is adapted to send a suspend command to the storage controller <NUM>. The suspend command may include information about the copy command targeted for suspend, for example, logical block addresses, a logical block address range, a logical block address, or a write pointer of the source zone or the target zone.

The storage controller <NUM> is adapted to suspend the copy operation and may store the progress status information of the copy operation. For example, the storage controller <NUM> may store a logical block address of data lastly written in the target zone from among data of the source zone (or a next logical block address of the lastly stored data). The storage controller <NUM> may maintain or discard data that are read through the read command but are not yet written in the target zone, for example, may maintain or discard data being buffered.

In operation S360, the storage controller <NUM> is adapted to send a suspend response to the host <NUM>. For example, the suspend response may include the progress status information of the copy operation.

In operation S370, the host <NUM> is adapted to send the read command to the storage controller <NUM>. The read command may include a logical block address(es) corresponding to the data being copied. In operation S380, the storage controller <NUM> may perform address mapping. Operation S360 may be performed to be identical to operation S220.

In operation S390, the storage controller <NUM> is adapted to send the read command to the nonvolatile memory <NUM> to read the data. In some example embodiments, in the case where the read-requested data are being buffered in the storage controller <NUM>, operation S390 may be omitted. In operation S400, the storage controller <NUM> is adapted to send a read response including the read data to the host <NUM>.

After sending the read response, the storage controller <NUM> may automatically resume the suspended copy operation. In operation S420, the storage controller <NUM> may send the read command to the nonvolatile memory <NUM>. In operation S430, the storage controller <NUM> may send the write command to the nonvolatile memory <NUM>. Operation S420 and operation S430 may be performed to be identical to operation S230 and operation S240.

When the copy operation is completed, in operation S440, the storage controller <NUM> may send the copy response to the host <NUM>.

As described above, the storage device <NUM> is adapted to suspend the copy operation in response to the suspend command and may automatically resume the suspended copy operation after processing one read command. Accordingly, the read latency may be prevented (or hindered) from increasing due to the copy operation.

In some example embodiments, the suspend command may include information about the number of read commands. The storage device <NUM> may automatically resume the suspended copy operation after processing the read command as much as the number of times defined by the suspend command.

As another example embodiment, the host <NUM> may provide the storage device <NUM> with information of the number of read commands at an arbitrary time. The storage device <NUM> may automatically resume the suspended copy operation after processing the read command as much as the number of times defined at an arbitrary time.

In some example embodiments, the operating method of <FIG> may be associated with an automatic resume mode. The host <NUM> may determine whether to enable the automatic resume mode of the storage device <NUM>. When the automatic resume mode is enabled, the storage device <NUM> is adapted to automatically resume the suspended copy operation, which is described with reference to <FIG>.

<FIG> illustrates another example of a process in which a copy operation is suspended and resumed in the host-storage system <NUM>.

Referring to <FIG> and <FIG>, in operation S510, the host <NUM> is adapted to send the copy command to the storage controller <NUM>, for example, may send the copy command for garbage collection to the storage controller <NUM>. Operation S510 may be performed to be identical to operation S310.

In operation S520, address mapping is adapted to be performed. Operation S520 may be performed to be identical to operation S320. The storage device <NUM> is adapted to start the copy operation. In operation S530, the storage controller <NUM> is adapted to send the read command to the nonvolatile memory <NUM>. In operation S540, the storage controller <NUM> is adapted to send the write command to the nonvolatile memory <NUM>. Operation S530 and operation S540 may be performed to be identical to operation S330 and operation S340.

When a read operation for data being copied is requested, in operation S550, the host <NUM> is adapted to send the suspend command to the storage controller <NUM>. The storage controller <NUM> is adapted to suspend the copy operation and may store the progress status information of the copy operation. In operation S560, the storage controller <NUM> is adapted to send the suspend response to the host <NUM>. Operation S550 and operation S560 may be performed to be identical to operation S350 and operation S360.

In operation S570, the host <NUM> is adapted to send the read command to the storage controller <NUM>. The read command may include a logical block address(es) corresponding to the data being copied. In operation S580, the storage controller <NUM> may perform address mapping. In operation S590, the storage controller <NUM> may send the read command to the nonvolatile memory <NUM>. In operation S600, the storage controller <NUM> is adapted to send the read response including the read data to the host <NUM>. Operation S570, operation S580, operation S590, and operation S600 may be performed to be identical to operation S370, operation S380, operation S390, and operation S400.

Unlike the description given with reference to <FIG>, the storage controller <NUM> may not automatically resume the suspended copy operation. The host <NUM> may perform an additional read operation through operation S610, operation S620, operation S630, and operation S640. Operation S610, operation S620, operation S630, and operation S640 may be performed to be identical to operation S370, operation S380, operation S390, and operation S400.

When a necessary read operation(s) is completed, in operation S650, the host <NUM> may send a resume command to the storage controller <NUM>. The resume command may include information about the copy command targeted for resume, for example, logical block addresses, a logical block address range, a logical block address, or a write pointer of the source zone or the target zone.

The storage controller <NUM> is adapted to resume the suspended copy operation in response to the resume command. In operation S670, the storage controller <NUM> may send the read command to the nonvolatile memory <NUM>. In operation S680, the storage controller <NUM> may send the write command to the nonvolatile memory <NUM>. Operation S670 and operation S680 may be performed to be identical to operation S330 and operation S340.

When the copy operation is completed, in operation S690, the storage controller <NUM> may send the copy response to the host <NUM>.

As described above, the storage device <NUM> is adapted to suspend the copy operation in response to the suspend command and resume the suspended copy operation in response to the resume command. Accordingly, the read latency may be prevented (or hindered) from increasing due to the copy operation.

In some example embodiments, the operating method of <FIG> may be associated with a host control mode. The host <NUM> may determine whether to enable the host control mode of the storage device <NUM>. When the host control mode is enabled, the storage device <NUM> may resume the suspended copy operation under control of the host <NUM>, which is described with reference to <FIG>.

In some example embodiments, the storage device <NUM> may support the automatic resume mode of <FIG> and the host control mode of <FIG>. The host <NUM> may enable one of the automatic resume mode and the host control mode of the storage device <NUM> or may disable both the automatic resume mode and the host control mode.

<FIG> is a diagram for describing a UFS system <NUM> according to some example embodiments of the present disclosure.

The UFS system <NUM> that is a system complying with the UFS standard announced by the JEDEC (Joint Electron Device Engineering Council) may include a UFS host <NUM>, a UFS device <NUM>, and a UFS interface <NUM>. The description given with reference to <FIG> with regard to the host-storage system <NUM> may be applied to the UFS system <NUM> of <FIG> without conflicting with the following description to be given with reference to <FIG>.

Referring to <FIG>, the UFS host <NUM> and the UFS device <NUM> may be interconnected through the UFS interface <NUM>. In the case where the host <NUM> of <FIG> is an application processor, the UFS host <NUM> may be implemented as a part of the application processor. The UFS host controller <NUM> and the host memory <NUM> may respectively correspond to the host controller <NUM> and the host memory <NUM> of <FIG>. The UFS device <NUM> may correspond to the storage device <NUM> of <FIG>, and the UFS device controller <NUM> and the nonvolatile memory <NUM> may respectively correspond to the storage controller <NUM> and the nonvolatile memory <NUM> of <FIG>.

<FIG> is a diagram of a UFS system <NUM> according to some example embodiments. The UFS system <NUM> may be a system conforming to a UFS standard announced by Joint Electron Device Engineering Council (JEDEC) and include a UFS host <NUM>, a UFS device <NUM>, and a UFS interface <NUM>. The above description of the host-storage system <NUM> of <FIG> may also be applied to the UFS system <NUM> of <FIG> within a range that does not conflict with the following description of <FIG>.

Referring to <FIG>, the UFS host <NUM> may be connected to the UFS device <NUM> through the UFS interface <NUM>. When the host <NUM> of <FIG> is an AP, the UFS host <NUM> may be implemented as a portion of the AP. The UFS host controller <NUM> and the host memory <NUM> may respectively correspond to the controller <NUM> of the main processor <NUM> and the memories 1200a and 1200b of <FIG>. The UFS device <NUM> may correspond to the storage device 1300a and 1300b of <FIG>, and a UFS device controller <NUM> and an NVM <NUM> may respectively correspond to the controllers <NUM> and the nonvolatile memory <NUM> of <FIG>.

The UFS host <NUM> may include a UFS host controller <NUM>, an application <NUM>, a UFS driver <NUM>, a host memory <NUM>, and a UFS interconnect (UIC) layer <NUM>. The UFS device <NUM> may include the UFS device controller <NUM>, the NVM <NUM>, a storage interface <NUM>, a device memory <NUM>, a UIC layer <NUM>, and a regulator <NUM>. The NVM <NUM> may include a plurality of memory units <NUM>. Although each of the memory units <NUM> may include a V-NAND flash memory having a 1D structure or a 3D structure, each of the memory units <NUM> may include another kind of NVM, such as PRAM and/or RRAM. The UFS device controller <NUM> may be connected to the NVM <NUM> through the storage interface <NUM>. The storage interface <NUM> may be configured to comply with a standard protocol, such as Toggle or ONFI.

The application <NUM> may refer to a program that wants to communicate with the UFS device <NUM> to use functions of the UFS device <NUM>. The application <NUM> may transmit input-output requests (IORs) to the UFS driver <NUM> for input/output (I/O) operations on the UFS device <NUM>. The IORs may refer to a data read request, a data storage (or write) request, and/or a data erase (or discard) request, without being limited thereto.

The UFS driver <NUM> may manage the UFS host controller <NUM> through a UFS-host controller interface (UFS-HCI). The UFS driver <NUM> may convert the IOR generated by the application <NUM> into a UFS command defined by the UFS standard and transmit the UFS command to the UFS host controller <NUM>. One IOR may be converted into a plurality of UFS commands. Although the UFS command may basically be defined by an SCSI standard, the UFS command may be a command dedicated to the UFS standard.

The UFS host controller <NUM> may transmit the UFS command converted by the UFS driver <NUM> to the UIC layer <NUM> of the UFS device <NUM> through the UIC layer <NUM> and the UFS interface <NUM>. During the transmission of the UFS command, a UFS host register <NUM> of the UFS host controller <NUM> may serve as a command queue (CQ).

The UIC layer <NUM> on the side of the UFS host <NUM> may include a mobile industry processor interface (MIPI) M-PHY <NUM> and an MIPI UniPro <NUM>, and the UIC layer <NUM> on the side of the UFS device <NUM> may also include an MIPI M-PHY <NUM> and an MIPI UniPro <NUM>.

The UFS interface <NUM> may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n for the UFS device <NUM>, a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

A frequency of a reference clock signal REF_CLK provided from the UFS host <NUM> to the UFS device <NUM> may be one of <NUM>, <NUM>, <NUM>, and <NUM>, without being limited thereto. The UFS host <NUM> may change the frequency of the reference clock signal REF_CLK during an operation, that is, during data transmission/receiving operations between the UFS host <NUM> and the UFS device <NUM>. The UFS device <NUM> may generate cock signals having various frequencies from the reference clock signal REF_CLK provided from the UFS host <NUM>, by using a phase-locked loop (PLL). Also, the UFS host <NUM> may set a data rate between the UFS host <NUM> and the UFS device <NUM> by using the frequency of the reference clock signal REF_CLK. That is, the data rate may be determined depending on the frequency of the reference clock signal REF_CLK.

The UFS interface <NUM> may support a plurality of lanes, each of (or alternatively, at least one of) which may be implemented as a pair of differential lines. For example, the UFS interface <NUM> may include at least one receiving lane and at least one transmission lane. In <FIG>, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C may constitute a receiving lane, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C may constitute a transmission lane. Although one transmission lane and one receiving lane are illustrated in <FIG>, the number of transmission lanes and the number of receiving lanes may be changed.

The receiving lane and the transmission lane may transmit data based on a serial communication scheme. Full-duplex communications between the UFS host <NUM> and the UFS device <NUM> may be enabled due to a structure in which the receiving lane is separated from the transmission lane. That is, while receiving data from the UFS host <NUM> through the receiving lane, the UFS device <NUM> may transmit data to the UFS host <NUM> through the transmission lane. In addition, control data (e.g., a command) from the UFS host <NUM> to the UFS device <NUM> and user data to be stored in or read from the NVM <NUM> of the UFS device <NUM> by the UFS host <NUM> may be transmitted through the same lane. Accordingly, between the UFS host <NUM> and the UFS device <NUM>, there may be no need to further provide a separate lane for data transmission in addition to a pair of receiving lanes and a pair of transmission lanes.

The UFS device controller <NUM> of the UFS device <NUM> may control all operations of the UFS device <NUM>. The UFS device controller <NUM> may manage the NVM <NUM> by using a logical unit (LU) <NUM>, which is a logical data storage unit. The number of LUs <NUM> may be <NUM>, without being limited thereto. The UFS device controller <NUM> may include an FTL and convert a logical data address (e.g., a logical block address (LBA)) received from the UFS host <NUM> into a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. A logical block configured to store user data in the UFS system <NUM> may have a size in a predetermined (or alternatively, a desired) range. For example, a minimum size of the logical block may be set to <NUM> Kbyte.

When a command from the UFS host <NUM> is applied through the UIC layer <NUM> to the UFS device <NUM>, the UFS device controller <NUM> may perform an operation in response to the command and transmit a completion response to the UFS host <NUM> when the operation is completed.

As an example, when the UFS host <NUM> intends to store user data in the UFS device <NUM>, the UFS host <NUM> may transmit a data storage command to the UFS device <NUM>. When a response (a 'ready-to-transfer' response) indicating that the UFS host <NUM> is ready to receive user data (ready-to-transfer) is received from the UFS device <NUM>, the UFS host <NUM> may transmit user data to the UFS device <NUM>. The UFS device controller <NUM> may temporarily store the received user data in the device memory <NUM> and store the user data, which is temporarily stored in the device memory <NUM>, at a selected position of the NVM <NUM> based on the address mapping information of the FTL.

As another example, when the UFS host <NUM> intends to read the user data stored in the UFS device <NUM>, the UFS host <NUM> may transmit a data read command to the UFS device <NUM>. The UFS device controller <NUM>, which has received the command, may read the user data from the NVM <NUM> based on the data read command and temporarily store the read user data in the device memory <NUM>. During the read operation, the UFS device controller <NUM> may detect and correct an error in the read user data by using an ECC engine (not shown) embedded therein. More specifically, the ECC engine may generate parity bits for write data to be written to the NVM <NUM>, and the generated parity bits may be stored in the NVM <NUM> along with the write data. During the reading of data from the NVM <NUM>, the ECC engine may correct an error in read data by using the parity bits read from the NVM <NUM> along with the read data, and output error-corrected read data.

In addition, the UFS device controller <NUM> may transmit user data, which is temporarily stored in the device memory <NUM>, to the UFS host <NUM>. In addition, the UFS device controller <NUM> may further include an AES engine (not shown). The AES engine may perform at least of an encryption operation and a decryption operation on data transmitted to the UFS device controller <NUM> by using a symmetric-key algorithm.

The UFS host <NUM> may sequentially store commands, which are to be transmitted to the UFS device <NUM>, in the UFS host register <NUM>, which may serve as a common queue, and sequentially transmit the commands to the UFS device <NUM>. In this case, even while a previously transmitted command is still being processed by the UFS device <NUM>, that is, even before receiving a notification that the previously transmitted command has been processed by the UFS device <NUM>, the UFS host <NUM> may transmit a next command, which is on standby in the CQ, to the UFS device <NUM>. Thus, the UFS device <NUM> may also receive a next command from the UFS host <NUM> during the processing of the previously transmitted command. A maximum number (or queue depth) of commands that may be stored in the CQ may be, for example, <NUM>. Also, the CQ may be implemented as a circular queue in which a start and an end of a command line stored in a queue are indicated by a head pointer and a tail pointer.

Each of (or alternatively, at least one of) the plurality of memory units <NUM> may include a memory cell array (not shown) and a control circuit (not shown) configured to control an operation of the memory cell array. The memory cell array may include a 1D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. Although each of (or alternatively, at least one of) the memory cells is a single-level cell (SLC) configured to store <NUM>-bit information, each of (or alternatively, at least one of) the memory cells may be a cell configured to store information of <NUM> bit or more, such as a multi-level cell (MLC), a triple-level cell (TLC), and a quadruple-level cell (QLC). The 3D memory cell array may include a vertical NAND string in which at least one memory cell is vertically oriented and located on another memory cell.

Voltages VCC, VCCQ, and VCCQ2 may be applied as power supply voltages to the UFS device <NUM>. The voltage VCC may be a main power supply voltage for the UFS device <NUM> and be in a range of <NUM> V to <NUM> V. The voltage VCCQ may be a power supply voltage for supplying a low voltage mainly to the UFS device controller <NUM> and be in a range of <NUM> V to <NUM> V. The voltage VCCQ2 may be a power supply voltage for supplying a voltage, which is lower than the voltage VCC and higher than the voltage VCCQ, mainly to an I/O interface, such as the MIPI M-PHY <NUM>, and be in a range of <NUM> V to <NUM> V. The power supply voltages may be supplied through the regulator <NUM> to respective components of the UFS device <NUM>. The regulator <NUM> may be implemented as a set of unit regulators respectively connected to different ones of the power supply voltages described above.

The UFS device <NUM> may be a zoned device. The UFS host <NUM> may perform the copy operation by sending the copy command to the UFS device <NUM>. The UFS host <NUM> may perform garbage collection on the UFS device <NUM> by using the copy operation. The UFS host <NUM> may send the suspend command for the copy operation to the UFS device <NUM>. The UFS device <NUM> may operate in the automatic resume mode and/or the host control mode.

<FIG> illustrates an example of a process in which the UFS system <NUM> of <FIG> operates in the automatic resume mode. To reduce the duplicated description, the command transfer between the UFS device controller <NUM> and the nonvolatile memory <NUM>, which is performed to be identical to that of <FIG>, is omitted.

Referring to <FIG> and <FIG>, in operation S910, the UFS host <NUM> may send a copy UPIU (UFS (Universal Flash Storage) Protocol Information Unit) to the UFS device <NUM>, for example, may send the copy UPIU for garbage collection to the UFS device <NUM>. For example, the copy UPIU may include logical block addresses or a logical block address range of a source zone, and logical block addresses, a logical block address range, a logical block address, or a write pointer of a target zone. The copy UPIU may include a command UPIU or a query request UPIU and may request the UFS device <NUM> to start the copy operation.

In operation S920, the UFS device <NUM> is adapted to perform the copy operation. The UFS device controller <NUM> of the UFS device <NUM> is adapted to perform address mapping and send the read command and the write command to the nonvolatile memory <NUM>.

In operation S930, the UFS host <NUM> is adapted to send a suspend UPIU to the UFS device <NUM>. The suspend UPIU may include information about the copy UPIU targeted for suspend, for example, logical block addresses, a logical block address range, a logical block address, or a write pointer of the source zone or the target zone. The suspend UPIU may include a command UPIU, a query request UPIU, or a task management UPIU, and may request the UFS device <NUM> to suspend the copy operation.

In operation S940, the UFS device <NUM> is adapted to send a response UPIU to the suspend UPIU to the UFS host <NUM>.

In operation S950, the UFS host <NUM> is adapted to send a command UPIU to the UFS device <NUM>. The command UPIU is adapted to include the read command associated with a portion of data, which is targeted for the copy operation.

In operation S960, the UFS device <NUM> is adapted to send a data in UPIU including the read data to the UFS host <NUM>. For example, the UFS device <NUM> may send two or more data in UPIUs to the UFS host <NUM>.

As the output of the data requested by the UFS host <NUM> is completed, in operation S970, the UFS device <NUM> is adapted to send the response UPIU to the command UPIU to the UFS host <NUM>.

As the response UPIU to the command UPIU is transferred, in operation S980, the UFS device <NUM> may automatically resume the suspended copy operation. When the copy operation is completed, the UFS device <NUM> may send the response UPIU to the copy UPIU to the UFS host <NUM>.

In some example embodiments, as the UFS host <NUM> sends the command UPIU as much as a given count and the UFS device <NUM> sends the response UPIU to the command UPIU to the UFS host <NUM> as much as the given count, the UFS device <NUM> may automatically resume the suspended copy operation. The given count may be included in the suspend UPIU or may be determined in advance by the UFS host <NUM>. The UFS host <NUM> may set the given count by using the query request UPIU.

<FIG> illustrates an example of a process in which the UFS system <NUM> of <FIG> operates in the host control mode. To reduce the duplicated description, the command transfer between the UFS device controller <NUM> and the nonvolatile memory <NUM>, which is performed to be identical to that of <FIG>, is omitted.

Referring to <FIG> and <FIG>, in operation S1010, the UFS host <NUM> may send the copy UPIU to the UFS device <NUM>, for example, may send the copy UPIU for garbage collection to the UFS device <NUM>. Operation S1010 may be performed to be identical to operation S910.

In operation S1020, the UFS device <NUM> may start the copy operation. Operation S1020 may be performed to be identical to operation S920.

In operation S1030, the UFS host <NUM> may send the suspend UPIU to the UFS device <NUM>. In operation S1040, the UFS device <NUM> may send the response UPIU to the suspend UPIU to the UFS host <NUM>. Operation S1030 and operation S1040 may be performed to be identical to operation S930 and operation S940.

In operation S1050, the UFS host <NUM> may send the command UPIU to the UFS device <NUM>. In operation S1060, the UFS device <NUM> may send at least one data in UPIU including the read data to the UFS host <NUM>. As the output of the data requested by the UFS host <NUM> is completed, in operation S1070, the UFS device <NUM> may send the response UPIU to the command UPIU to the UFS host <NUM>. Operation S1050, operation S1060, and operation S1070 may be performed to be identical to operation S950, operation S960, and operation S970.

In operation S1080, the UFS host <NUM> may send the command UPIU to the UFS device <NUM>. In operation S1090, the UFS device <NUM> may send at least one data in UPIU including the read data to the UFS host <NUM>. As the output of the data requested by the UFS host <NUM> is completed, in operation S1100, the UFS device <NUM> may send the response UPIU to the command UPIU to the UFS host <NUM>. Operation S1080, operation S1090, and operation S1100 may be performed to be identical to operation S950, operation S960, and operation S970.

In operation S1110, the UFS host <NUM> may send a resume UPIU to the UFS device <NUM>. The resume UPIU may include information about the copy UPIU targeted for resume, for example, logical block addresses, a logical block address range, a logical block address, or a write pointer of the source zone or the target zone. The resume UPIU may include a command UPIU, a query request UPIU, or a task management UPIU, and may request the UFS device <NUM> to resume the suspended copy operation.

<FIG> is a block diagram illustrating a storage device <NUM> according to some example embodiments of the present disclosure.

Referring to <FIG>, a storage device <NUM> may include a memory device <NUM> and a memory controller <NUM>. The memory device <NUM> may correspond to the nonvolatile memory <NUM> of <FIG> or the nonvolatile memory <NUM> of <FIG>. The memory controller <NUM> may correspond to the storage controller <NUM><NUM> of <FIG> or the UFS device controller <NUM> of <FIG>.

<FIG> is a block diagram of a memory system <NUM> according to some example embodiments. Referring to <FIG>, the memory system <NUM> may include a memory device <NUM> and a memory controller <NUM>. The memory system <NUM> may support a plurality of channels CH1 to CHm, and the memory device <NUM> may be connected to the memory controller <NUM> through the plurality of channels CH1 to CHm. For example, the memory system <NUM> may be implemented as a storage device, such as an SSD.

The memory device <NUM> may include a plurality of NVM devices NVM11 to NVMmn. Each of (or alternatively, at least one of) the NVM devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a way corresponding thereto. For instance, the NVM devices NVM11 to NVM1n may be connected to a first channel CH1 through ways W11 to W1n, and the NVM devices NVM21 to NVM2n may be connected to a second channel CH2 through ways W21 to W2n. In some example embodiments, each of the NVM devices NVM11 to NVMmn may be implemented as an arbitrary memory unit that may operate according to an individual command from the memory controller <NUM>. For example, each of the NVM devices NVM11 to NVMmn may be implemented as a chip or a die, but the example embodiments are not limited thereto.

The memory controller <NUM> may transmit and receive signals to and from the memory device <NUM> through the plurality of channels CH1 to CHm. For example, the memory controller <NUM> may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device <NUM> through the channels CH1 to CHm or receive the data DATAa to DATAm from the memory device <NUM>.

The memory controller <NUM> may select one of the NVM devices NVM11 to NVMmn, which is connected to each of (or alternatively, at least one of) the channels CH1 to CHm, by using a corresponding one of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller <NUM> may select the NVM device NVM11 from the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller <NUM> may transmit the command CMDa, the address ADDRa, and the data DATAa to the selected NVM device NVM11 through the first channel CH1 or receive the data DATAa from the selected NVM device NVM11.

The memory controller <NUM> may transmit and receive signals to and from the memory device <NUM> in parallel through different channels. For example, the memory controller <NUM> may transmit a command CMDb to the memory device <NUM> through the second channel CH2 while transmitting a command CMDa to the memory device <NUM> through the first channel CH1. For example, the memory controller <NUM> may receive data DATAb from the memory device <NUM> through the second channel CH2 while receiving data DATAa from the memory device <NUM> through the first channel CH1.

The memory controller <NUM> may control all operations of the memory device <NUM>. The memory controller <NUM> may transmit a signal to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For instance, the memory controller <NUM> may transmit the command CMDa and the address ADDRa to the first channel CH1 and control one selected from the NVM devices NVM11 to NVM1n.

Each of (or alternatively, at least one of) the NVM devices NVM11 to NVMmn may operate via the control of the memory controller <NUM>. For example, the NVM device NVM11 may program the data DATAa based on the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the NVM device NVM21 may read the data DATAb based on the command CMDb and the address ADDb provided to the second channel CH2 and transmit the read data DATAb to the memory controller <NUM>.

Although <FIG> illustrates an example in which the memory device <NUM> communicates with the memory controller <NUM> through m channels and includes n NVM devices corresponding to each of the channels, the number of channels and the number of NVM devices connected to one channel may be variously changed.

The storage device <NUM> may be a zoned device. The memory controller <NUM> may start the copy operation with respect to data stored in the memory device <NUM> in response to the copy command of the host. The memory controller <NUM> may suspend the copy operation in response to the suspend command of the host. The memory controller <NUM> may resume the suspended copy operation based on the automatic resume mode or the host control mode.

The memory controller <NUM> may map two or more zones onto each of the plurality of nonvolatile memory devices (or sub-devices) NVM11 to NVMmn. The nonvolatile memory devices may include nonvolatile memory therein. Logical address of a plurality of zones may be fixed, but physical addresses of the plurality of zones may be changed by the memory controller <NUM>. For example, a nonvolatile memory or a channel onto which a plurality of zones are mapped may be changed by the memory controller <NUM>.

When the host opens a specific zone of the plurality of zones, the memory controller <NUM> may map physical addresses onto the corresponding zone. For example, when a target zone is newly opened by the copy command of the host, the memory controller <NUM> may map physical addresses of a different channel from a channel of the source zone onto the target zone. That is, the copy operation may be performed in nonvolatile memories of different channels. Accordingly, a speed of the copy operation may be improved.

<FIG> is a block diagram illustrating a nonvolatile memory <NUM> according to some example embodiments of the present disclosure.

Referring to <FIG>, the nonvolatile memory <NUM> includes a memory cell array <NUM>, a row decoder block <NUM>, a page buffer block <NUM>, a pass/fail check block (PFC) <NUM>, a data input and output block <NUM>, a buffer block <NUM>, and a control logic block <NUM>.

The memory cell array <NUM> includes a plurality of memory blocks BLK1 to BLKz. Each of (or alternatively, at least one of) the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of (or alternatively, at least one of) the memory blocks BLK1 to BLKz may be connected with the row decoder block <NUM> through at least one ground selection line GSL, word lines WL, and at least one string selection line SSL. Some of the word lines WL may be used as dummy word lines. Each of (or alternatively, at least one of) the memory blocks BLK1 to BLKz may be connected with the page buffer block <NUM> through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be connected in common with the plurality of bit lines BL.

In some example embodiments, each of (or alternatively, at least one of) the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. Memory cells belonging to each of (or alternatively, at least one of) the memory blocks BLK1 to BLKz may be erased at the same time. As another example, each of (or alternatively, at least one of) the memory blocks BLK1 to BLKz may be divided into a plurality of sub-blocks. Each of (or alternatively, at least one of) the plurality of sub-blocks may correspond to a unit of the erase operation.

The row decoder block <NUM> is connected with the memory cell array <NUM> through the ground selection lines GSL, the word lines WL, and the string selection lines SSL. The row decoder block <NUM> operates under control of the control logic block <NUM>.

The row decoder block <NUM> may decode a row address RA received from the buffer block <NUM> and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address.

The page buffer block <NUM> is connected with the memory cell array <NUM> through the plurality of bit lines BL. The page buffer block <NUM> is connected with the data input and output block <NUM> through a plurality of data lines DL. The page buffer block <NUM> operates under control of the control logic block <NUM>.

In a program operation, the page buffer block <NUM> may store data to be written in memory cells. The page buffer block <NUM> may apply voltages to the plurality of bit lines BL based on the stored data. In a read operation or in a verify read operation that is performed in the program operation or the erase operation, the page buffer block <NUM> may sense voltages of the bit lines BL and may store a sensing result.

In the verify read operation associated with the program operation or the erase operation, the pass/fail check block <NUM> may verify the sensing result of the page buffer block <NUM>. For example, in the verify read operation associated with the program operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to on-cells that are not programmed to a target threshold voltage or more.

In the verify read operation associated with the erase operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to off-cells that are not erased to a target threshold voltage or less. When a counting result is greater than or equal to a threshold value, the pass/fail check block <NUM> may output a signal indicating a fail to the control logic block <NUM>. When the counting result is smaller than the threshold value, the pass/fail check block <NUM> may output a signal indicating a pass to the control logic block <NUM>. Depending on a verification result of the pass/fail check block <NUM>, a program loop of the program operation may be further performed, or an erase loop of the erase operation may be further performed.

The data input and output block <NUM> is connected with the page buffer block <NUM> through the plurality of data lines DL. The data input and output block <NUM> may receive a column address CA from the buffer block <NUM>. The data input and output block <NUM> may output data read by the page buffer block <NUM> to the buffer block <NUM> depending on the column address CA. The data input and output block <NUM> may provide data received from the buffer block <NUM> to the page buffer block <NUM>, based on the column address CA.

Through first signal lines SIGL1, the buffer block <NUM> may receive a command CMD and an address ADDR from an external device and may exchange data "DATA" with the external device. The buffer block <NUM> may operate under control of the control logic block <NUM>. The buffer block <NUM> may provide the command CMD to the control logic block <NUM>. The buffer block <NUM> may provide the row address RA of the address ADDR to the row decoder block <NUM> and may provide the column address CA of the address ADDR to the data input and output block <NUM>. The buffer block <NUM> may exchange the data "DATA" with the data input and output block <NUM>.

The control logic block <NUM> may exchange a control signal CTRL with the external device through second signal lines SIGL2. The control logic block <NUM> may allow the buffer block <NUM> to route the command CMD, the address ADDR, and the data "DATA". The control logic block <NUM> may decode the command CMD received from the buffer block <NUM> and may control the nonvolatile memory <NUM> based on the decoded command.

In some embodiments, the nonvolatile memory <NUM> may be manufactured in a bonding manner. The memory cell array <NUM> may be manufactured at a first wafer, and the row decoder block <NUM>, the page buffer block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be manufactured at a second wafer. The nonvolatile memory <NUM> may be implemented by coupling the first wafer and the second wafer such that an upper surface of the first wafer and an upper surface of the second wafer face each other.

As another example, the nonvolatile memory <NUM> may be manufactured in a cell over peri (COP) manner. A peripheral circuit including the row decoder block <NUM>, the page buffer block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be implemented on a substrate. The memory cell array <NUM> may be implemented over the peripheral circuit. The peripheral circuit and the memory cell array <NUM> may be connected by using through vias.

<FIG> illustrates an example in which logical addresses of zones and physical addresses of the nonvolatile memory <NUM> are mapped.

Referring to <FIG> and <FIG>, a mapping table MT may include items of a logical block address LBA, a physical block address PBA, and a write pointer WP. One representative logical block address (e.g., a start address or an end address) among logical block addresses of each zone may be recorded in the mapping table MT as the logical block address LBA.

First to z-th zones Z1 to Zz may be respectively mapped onto first to z-th memory blocks BLK1 to BLKz (or supper blocks each including two or more memory blocks capable of being accessible in parallel). A representative physical address (e.g., a start address or an end address) of each memory block may be recorded in the mapping table MT as the physical block address PBA.

The write pointer WP may indicate a location of next data to be written in each zone. A first write pointer WP1 may be recorded in the first zone Z1, and a second write pointer WP2 may be recorded in the second zone Z2. When data are written in each zone, the corresponding write pointer may be updated. A write pointer may be allocated only for opened zones. The number of zones that are opened at the same time may be limited.

<FIG> is a diagram of a system <NUM> to which a storage device is applied, according to some example embodiments. The system <NUM> of <FIG> may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device. However, the system <NUM> of <FIG> is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring to <FIG>, the system <NUM> may include a main processor <NUM>, memories (e.g., 2200a and 2200b), and storage devices (e.g., 2300a and 2300b). In addition, the system <NUM> may include at least one of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control all operations of the system <NUM>, more specifically, operations of other components included in the system <NUM>. The main processor <NUM> may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor <NUM> may include at least one CPU core <NUM> and further include a controller <NUM> configured to control the memories 2200a and 2200b and/or the storage devices 2300a and 2300b. In some example embodiments, the main processor <NUM> may further include an accelerator <NUM>, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor <NUM>.

The memories 2200a and 2200b may be used as main memory devices of the system <NUM>. Although each of the memories 2200a and 2200b may include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of (or alternatively, at least one of) the memories 2200a and 2200b may include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories 2200a and 2200b may be implemented in the same package as the main processor <NUM>.

The storage devices 2300a and 2300b may serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have larger storage capacity than the memories 2200a and 2200b. The storage devices 2300a and 2300b may respectively include storage controllers (STRG CTRL) 2310a and 2310b and NVM (Non-Volatile Memory) 2320a and 2320b configured to store data via the control of the storage controllers 2310a and 2310b. Although the NVMs 2320a and 2320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 2320a and 2320b may include other types of NVMs, such as PRAM and/or RRAM.

The storage devices 2300a and 2300b may be physically separated from the main processor <NUM> and included in the system <NUM> or implemented in the same package as the main processor <NUM>. In addition, the storage devices 2300a and 2300b may have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system <NUM> through an interface, such as the connecting interface <NUM> that will be described below. The storage devices 2300a and 2300b may be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device <NUM> may capture still images or moving images. The image capturing device <NUM> may include a camera, a camcorder, and/or a webcam.

The user input device <NUM> may receive various types of data input by a user of the system <NUM> and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may detect various types of physical quantities, which may be obtained from the outside of the system <NUM>, and convert the detected physical quantities into electric signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device <NUM> may transmit and receive signals between other devices outside the system <NUM> according to various communication protocols. The communication device <NUM> may include an antenna, a transceiver, and/or a modem.

The power supplying device <NUM> may appropriately convert power supplied from a battery (not shown) embedded in the system <NUM> and/or an external power source, and supply the converted power to each of (or alternatively, at least one of) components of the system <NUM>.

The connecting interface <NUM> may provide connection between the system <NUM> and an external device, which is connected to the system <NUM> and capable of transmitting and receiving data to and from the system <NUM>. The connecting interface <NUM> may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE <NUM>, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

The storage devices 2300a and 2300b may correspond to the storage device <NUM> described with reference to <FIG>, the UFS device <NUM> described with reference to <FIG>, or the storage device <NUM> described with reference to <FIG>. The main processor <NUM> may correspond to the host <NUM> described with reference to <FIG> or the UFS host <NUM> described with reference to <FIG>.

In the above example embodiments, components according to the present disclosure are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the example embodiments. For example, the terms "first", "second", "third", etc. do not involve an order or a numerical meaning of any form.

In the above example embodiments, components according to example embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

According to the present disclosure, a copy operation of a zoned storage space may be suspended and resumed. Accordingly, a storage device in which a read latency decreases in a copy operation and an operating method of the storage device are provided.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry including storage controller <NUM>, host controller <NUM>, UFS host controller <NUM>, UFS device controller <NUM>, memory controller <NUM> control logic block <NUM>, the controller, <NUM>, accelerator <NUM>, CPU core <NUM>,more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc..

Processor(s), controller(s), and/or processing circuitry may be configured to perform actions or steps by being specifically programmed to perform those action or steps (such as with an FPGA or ASIC) or may be configured to perform actions or steps by executing instructions received from a memory, or a combination thereof.

Claim 1:
A storage device (<NUM>) comprising:
a nonvolatile memory device (<NUM>); and
a controller (<NUM>) configured to
partition a storage space of the nonvolatile memory device (<NUM>) into a plurality of zones (Z1, Z2, Zm), and
access the storage space,
wherein each of the plurality of zones (Z1, Z2, Zm) corresponds to consecutive physical addresses of the nonvolatile memory device (<NUM>),
wherein the controller (<NUM>) is configured to map the consecutive physical addresses of each of the plurality of zones (Z1, Z2, Zm) onto consecutive logical addresses,
wherein, in response to a copy command being received from an external host device (<NUM>), the controller (<NUM>) is configured to start a copy operation for copying data of a first zone (Z1) of the plurality of zones (Z1, Z2, Zm) to a second zone (Z2) of the plurality of zones (Z1, Z2, Zm) and send first read commands and first write commands to the nonvolatile memory device (<NUM>),
wherein, in response to a suspend command being received from the external host device (<NUM>) before the copy operation is completed, the controller (<NUM>) is configured to suspend the copy operation, store progress status information about the copy operation, and send a suspend response to the external host device (<NUM>), and
wherein, in response to a second read command being received from the external host device (<NUM>), the controller (<NUM>) is configured to send a third read command to the nonvolatile memory device (<NUM>) to perform a read operation, send a read response including data read by the read operation to the external host device (<NUM>), and resume the suspended copy operation.