Patent Description:
The introduction of copper metallization brings new challenges in the die-to-package interaction as compared to standard aluminum metallization. Increased die bow/warpage and higher residual stress within the die after the soldering process are two examples of challenges exasperated by incorporating copper into die and packaging technologies. Die bow/warpage and residual stress may dramatically influence the die and clip attach processes, leading to formation of voids in the solder and a tilted die with respect to the lead frame or other substrate to which the die is attached.

The formation of voids within the conductive connection, for example between the die and die attach substrate or between the die and clip, can hinder electrical and thermal properties of the packaged device to such an extent that early failure may occur. Moreover, package devices with such voids cannot always be screened.

If a die is titled with respect to the substrate to which it is attached, an unusually small amount of solder may be present under one corner or edge of the die as compared to the other corners/edges. The unusually small amount of solder may degrade during temperature cycling, leading to early failure of the device.

<CIT> discloses a semiconductor device that includes a semiconductor body, a plurality of contact pads formed on a surface of the semiconductor body, a passivation layer formed on the surface between the contact pads, and a stress buffer layer formed on the passivation layer, wherein the stress buffer is patterned to expose the contact pads. Further, the semiconductor device includes a layer stack that is formed on the stress buffer layer and the contact pads. The layer stack includes an adhesion layer, a barrier layer, a seed layer and a metal layer.

<CIT> discloses a semiconductor die with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of a device integrated in the die. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling.

<CIT> discloses a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. The semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material. A Young's modulus of the material of the stress relaxation portion is lower than a Young's modulus of the material of the emitter electrode.

<CIT> discloses a method of forming a stress relieved film stack. The method comprises forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about <NUM> after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

<CIT> discloses a method to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an integrated circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

More robust techniques which reduce die bow/warpage and higher residual stress within a die of a power semiconductor device in a semiconductor package are needed.

One embodiment of the present invention relates to a semiconductor package according to claim <NUM>.

In an embodiment, the stress relieving layer or layer stack may comprise a material selected from the group consisting of a polymer, an imide, an alloy of aluminum and copper, an oxide, a nitride, silicon nitride, oxynitride, a nitride-based ceramic, and SiCOH.

Separately or in combination, the metal layer or layer stack may be an uppermost metal layer of the semiconductor device. Part of the stress relieving layer or layer stack may be free of openings or have a large opening to provide a generally planar surface topography over which the metal layer or layer stack may comprise one or more contact pads.

Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may be arranged in a regular pattern so that the patterned surface topography of the stress relieving layer or layer stack may have a regular pattern.

Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may be arranged in a checkerboard pattern, a honeycomb pattern or in stripes so that the patterned surface topography of the stress relieving layer or layer stack may have a checkerboard pattern, a honeycomb pattern or a striped pattern, respectively.

Separately or in combination, the stress relieving layer or layer stack may have a corrugated profile with alternating ridges and grooves in a cross-section through any row of the plurality of openings.

Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may comprise an arrangement of regularly-spaced openings of the same or substantially same shape. For example, the shape of the regularly-spaced openings may be selected from the group consisting of square, rectangular, hexagonal, ellipsoidal, and polygonal.

Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may comprise rows of regularly spaced openings of the same shape.

Separately or in combination, the stress relieving layer or layer stack may cover between <NUM>% and <NUM>% of an entire main surface of the semiconductor body over which the stress relieving layer or layer stack is disposed. For example, the stress relieving layer or layer stack may cover the entire main surface of the semiconductor body over which the stress relieving layer or layer stack is disposed.

Separately or in combination, the plurality of openings may be formed in the stress relieving layer or layer stack over a first part of the semiconductor body, and the stress relieving layer or layer stack may be free of openings or have a large opening over a second part of the semiconductor body adjacent the first part to provide a generally planar surface topography. For example, the first part of the semiconductor body may be a central part of the semiconductor body and the second part of the semiconductor body may be a periphery region of the semiconductor body which laterally surrounds the central part.

Separately or in combination, the metal layer or layer stack may comprise: a barrier metal layer covering a top main surface of the stress relieving layer or layer stack and sidewalls of the openings in the stress relieving layer or layer stack; and a copper layer covering the barrier metal layer.

Separately or in combination, in a same row of the openings in the stress relieving layer or layer stack, a spacing between adjacent ones of the openings may be approximately equal to a width of the openings.

Separately or in combination, the stress relieving layer or layer stack may be formed on an AlCu layer, and the metal layer or layer stack may be in electrical contact with the AlCu layer through the plurality of openings or through a large opening in the stress relieving layer or layer stack.

Separately or in combination, the stress relieving layer or layer stack may comprise a doped region and/or polysilicon at a rear main surface of the semiconductor body which is structured with recesses and the metal layer or layer stack may comprise a barrier layer covering the structured rear main surface of the semiconductor body and a copper layer formed on the barrier layer and filling the recesses in the structured rear main surface of the semiconductor body.

Another embodiment of the present invention relates to a method according to claim <NUM>.

In an embodiment, part of the stress relieving layer or layer stack may be free of openings or have a larger opening to provide a generally planar surface topography over which the metal layer or layer stack may comprise a contact pad, and the metal connector may be attached to the contact pad.

The features of the various illustrated embodiments may be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows. The embodiments of the figures show partial aspects, but not all of the features of an embodiment of the present invention, which is defined by the appended claims.

Embodiments described herein provide a stress relieving layer or layer stack disposed over at least part of a semiconductor body, for counteracting stress imparted by a metal layer or layer stack disposed above the stress relieving layer or layer stack. The stress relieving layer or layer stack has a plurality of openings which yield a patterned surface topography. The patterned surface topography for the stress relieving layer or layer stack is transferred to the surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack absorbs at least some of the stress imparted by the metal layer or layer stack during temperature cycling and/or residual stress stored within the metal layer or layer stack, reducing the likelihood of die bow/warpage and high mechanical stress.

<FIG> illustrates a cross-sectional view of part of a semiconductor device <NUM>. The semiconductor device <NUM> includes a semiconductor body <NUM>. The semiconductor body <NUM> may be part of a semiconductor wafer prior to die singulation, or may be part of a semiconductor die (chip) post die singulation. In either case, one or more passive and/or active devices may be formed in the semiconductor body <NUM>. A power device such as an insulated gate bipolar transistor (IGBT), power metal-oxide-semiconductor field effect transistor (MOSFET), high-electron mobility transistor (HEMT), power diode, half-bridge, full-bridge, etc. is formed in the semiconductor body <NUM>. In addition, a logic device such as a processor, ASIC (application-specific integrated-circuit), memory, controller, etc. may be formed in the semiconductor body <NUM>. In addition, a sensor such as a Hall sensor, microelectromechanical systems (MEMS), etc. may be formed in the semiconductor body <NUM>. Still other types of passive and/or active devices may be formed in the semiconductor body <NUM>. The device(s) formed in the semiconductor body <NUM> are not shown in <FIG> for ease of illustration, but may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc..

A stress relieving layer (i.e. a single stress relieving layer) or layer stack (i.e. more than one stress relieving layer stacked one above the other) <NUM> is disposed over at least part of the semiconductor body <NUM>. That is, the stress relieving layer or layer stack <NUM> covers all or only a portion of the semiconductor body <NUM>. For example, the stress relieving layer or layer stack <NUM> may cover between <NUM>% and <NUM>% of the entire main surface <NUM> of the semiconductor body <NUM> over which the stress relieving layer or layer stack <NUM> is disposed. In one embodiment, the stress relieving layer or layer stack <NUM> may cover the entire main surface <NUM> of the semiconductor body <NUM> over which the stress relieving layer or layer stack <NUM> is disposed.

The stress relieving layer or layer stack <NUM> has a plurality of openings <NUM> which yield a patterned surface topography for the stress relieving layer or layer stack <NUM>. That is, the surface <NUM> of the stress relieving layer or layer stack <NUM> facing away from the semiconductor body <NUM> has a patterned shape which is defined by the number, spacing, shape and dimensions of the openings <NUM> formed in the stress relieving layer or layer stack <NUM>. The openings <NUM> in the stress relieving layer or layer stack <NUM> may be arranged in a regular or irregular pattern so that the patterned surface topography of the stress relieving layer or layer stack <NUM> has a corresponding regular or irregular pattern, respectively. The openings <NUM> may be formed by a standard etch process such as masking and wet or dry etching of the stress relieving layer or layer stack <NUM>, by laser drilling of the stress relieving layer or layer stack <NUM>, by patterned deposition of the stress relieving layer or layer stack <NUM>, etc..

A metal layer (i.e. a single metal layer) or layer stack (i.e. more than one metal layer stacked one above the other) <NUM> is formed on the stress relieving layer or layer stack <NUM> and occupies the openings <NUM> in the stress relieving layer or layer stack <NUM>. The metal layer or layer stack <NUM> may partly or completely fill the openings <NUM> in the stress relieving layer or layer stack <NUM>. Any commonly used metal(s) or metal stack in the semiconductor industry may be used.

The patterned surface topography of the stress relieving layer or layer stack <NUM> is transferred to the surface <NUM> of the metal layer or layer stack <NUM> facing away from the semiconductor body <NUM>. Accordingly, the surface <NUM> of the metal layer or layer stack <NUM> facing away from the semiconductor body <NUM> has the same or substantially same patterned shape as the surface <NUM> of the stress relieving layer or layer stack <NUM> facing away from the semiconductor body <NUM>. While the metal layer or layer stack <NUM> and the stress relieving layer or layer stack <NUM> have the same or substantially same general shape / structure / contour, the relative dimensions may differ. For example, the vertical sidewalls <NUM> of the openings <NUM> in the stress relieving layer or layer stack <NUM> may be covered with slightly more or slightly less material than the horizontal parts <NUM>, and the thickness of the metal layer or layer stack <NUM> along the sidewalls <NUM> of the openings <NUM> may be different than the thickness of the metal layer or layer stack <NUM> at the bottom <NUM> of the openings <NUM> and on the horizontal parts <NUM> of the stress relieving layer or layer stack <NUM>. Also, the surface <NUM> of the metal layer or layer stack <NUM> with the patterned topography is not planarized. Hence, the metal layer or layer stack <NUM> retains the patterned surface topography transferred from the stress relieving layer or layer stack <NUM>. The metal layer or layer stack <NUM> may be a thick layer such that the patterned surface topography transferred from the stress relieving layer or layer stack <NUM> may be barely visible.

The stress relieving layer or layer stack <NUM> also has a different elastic modulus (e.g. Young's modulus) than the metal layer or layer stack <NUM> over a temperature range, which may or may not be the full (entire) operating range of the semiconductor device <NUM>. In one embodiment, the stress relieving layer or layer stack <NUM> has a smaller elastic modulus than the metal layer or layer stack <NUM> over the temperature range of interest. For example, the stress relieving layer or layer stack <NUM> may comprise one or more of a stable or dissolvable polymer, an imide, an alloy of aluminum and copper, and an oxide. The stress relieving layer or layer stack <NUM> absorbs at least some of the stress imparted by the metal layer or layer stack <NUM> during temperature cycling and/or residual stress stored within the metal layer or layer stack <NUM>, reducing the likelihood of die bow/warpage and high mechanical stress.

In another embodiment, the stress relieving layer or layer stack <NUM> has a higher elastic modulus than the metal layer or layer stack <NUM> over the temperature range of interest. For example, the stress relieving layer or layer stack <NUM> may comprise one or more of a tungsten-based alloy, e.g., with titanium or nitride, nickel or a nickel-based alloy, e.g., with vanadium or phosphorus, doped silicon and/or polysilicon. In the case of doped silicon, the rear main surface <NUM> of the semiconductor body <NUM> may be doped with phosphorus, then structured, e.g., by etching, and then filled, e.g., with copper. The stress relieving layer or layer stack <NUM> may compensate some of the stress imparted by the metal layer or layer stack <NUM> during temperature cycling and/or residual stress in a way to reduce the likelihood of die bow/warpage and high mechanical stress.

The metal layer or layer stack <NUM> and the corresponding stress relieving layer or layer stack <NUM> may be applied over either side of the semiconductor body <NUM>. That is, the metal layer or layer stack <NUM> and the corresponding stress relieving layer or layer stack <NUM> may be applied over the front main surface <NUM> of the semiconductor body <NUM>, over the rear main surface <NUM> of the semiconductor body <NUM>, or over both main surfaces <NUM>, <NUM>.

The metal layer or layer stack <NUM> with the same or substantially same patterned surface topography as the stress relieving layer or layer stack <NUM> may be the uppermost (final) metallization of the semiconductor device <NUM>. In this case, the metal layer or layer stack <NUM> provides one or more points of external electrical contact for the device(s) formed in the semiconductor body <NUM>. For example, the metal layer or layer stack <NUM> may include a gate pad, a source pad and/or drain pad in the case of a power transistor device such as an IGBT, bipolar transistor, HEMT, MEMS, etc. The metal layer or layer stack <NUM> may include an anode pad and/or a cathode pad in the case of a power diode device. The metal layer or layer stack <NUM> may include a substantial number of pads in the case of a logic device.

The metal layer or layer stack <NUM> with the same or substantially same patterned surface topography as the stress relieving layer or layer stack <NUM> instead may be the lowermost (first) metallization closest to the semiconductor body <NUM>. In this case, an additional layer or layer stack <NUM> such as an oxide or one or more additional metal layers or layer stacks may be provided above the metal layer or layer stack <NUM>. The number and composition of layers disposed above the metal layer or layer stack <NUM> may vary for different areas of the semiconductor device <NUM> independent of the metal layer or layer stack <NUM> and stress relieving layer or layer stack <NUM>. The metal layer or layer stack <NUM> with the same or substantially same patterned surface topography as the stress relieving layer or layer stack <NUM> instead may be an intermediary metallization. In this case, one or more additional metal layers or layer stacks are formed above the intermediary metal layer or layer stack and one or more additional metal layers or layer stacks are formed below the intermediary metal layer or layer stack, with an interlayer dielectric separating the different metallization layers.

<FIG> shows the metal layer or layer stack <NUM> as either the uppermost (final) metallization or as an intermediary metallization. In this case, one or more additional metallization layers may be provided between the metal layer or layer stack <NUM> and the semiconductor body <NUM>, and additional layer(s) may be disposed between the intermediary metallization and the semiconductor substrate as indicated by the vertical dotted line.

For example, one of the additional layer or layer stack <NUM> may be an additional metallization such as a wiring layer on which the stress relieving layer or layer stack <NUM> is formed. The metal layer or layer stack <NUM> with the same or substantially same patterned surface topography as the stress relieving layer or layer stack <NUM> may be in electrical contact with the additional metallization layer through the openings <NUM> in the stress relieving layer or layer stack <NUM>. In one embodiment, the openings <NUM> in the stress relieving layer or layer stack <NUM> are arranged independent of the layout of the additional metallization layer <NUM>. That is, while the openings <NUM> in the stress relieving layer or layer stack <NUM> enable electrical contact between the two metallization layers <NUM>, <NUM> separated by the stress relieving layer or layer stack <NUM>, the layout of the openings <NUM> is designed so that the stress relieving layer or layer stack <NUM> absorbs at least some of the stress imparted by the overlying metal layer or layer stack <NUM> during temperature cycling and/or residual stress stored within the metal layer or layer stack <NUM>.

<FIG> illustrates a perspective view of the stress relieving layer or layer stack <NUM> and the metal layer or layer stack <NUM> with the same or substantially same patterned surface topography, according to an embodiment. <FIG> illustrates a perspective view of the stress relieving layer or layer stack <NUM> without the metal layer or layer stack <NUM>. According to this embodiment, the stress relieving layer or layer stack <NUM> has rows <NUM> of regularly-spaced openings <NUM> of the same or substantially same shape. The shape of the regularly-spaced openings <NUM> may be square, rectangular, hexagonal, ellipsoidal, polygonal, etc. While the openings <NUM> in the stress relieving layer or layer stack <NUM> are shown as being arranged in a regular pattern in <FIG> and <FIG>, the pattern instead may be irregular. In either case, the patterned surface topography of the stress relieving layer or layer stack <NUM> is transferred to the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM> so that the metal layer or layer stack <NUM> has the same or substantially same patterned surface topography as the stress relieving layer or layer stack <NUM>.

<FIG> illustrates a plan view of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. <FIG> illustrates a cross-sectional view of the structure taken through the line labeled A-A' in <FIG>. <FIG> illustrates a cross-sectional view of the structure taken through the line labeled B-B' in <FIG>. As described above, the metal layer or layer stack <NUM> may be the uppermost (final) metallization, lowermost (first) metallization or an intermediary metallization.

The cross-sectional in <FIG> transects through a row of the openings <NUM> in the stress relieving layer or layer stack <NUM>, whereas the cross-sectional in <FIG> transects through the structure between adjacent rows <NUM>. According to this embodiment, the stress relieving layer or layer stack <NUM> covers the entire main surface <NUM> of the semiconductor body <NUM> over which the stress relieving layer or layer stack <NUM> is disposed. As shown in <FIG> and <FIG>, the surface topography of the metal layer or layer stack <NUM> follows the surface topography of the stress relieving layer or layer stack <NUM>. That is, the surface <NUM> of the metal layer or layer stack <NUM> facing away from the semiconductor body <NUM> has the same or substantially same patterned shape as the surface <NUM> of the stress relieving layer or layer stack <NUM> facing away from the semiconductor body <NUM>.

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the metal layer or layer stack <NUM> is the uppermost (final) metal layer of the semiconductor device <NUM>. The stress relieving layer or layer stack <NUM> is out of view in <FIG>. However, part of the stress relieving layer or layer stack <NUM> is free of openings and has a generally planar surface topography. The generally planar surface topography is transferred to the metal layer or layer stack <NUM>. The metal layer or layer stack <NUM> may include one or more contact pads <NUM> disposed over the part of the stress relieving layer or layer stack <NUM> which is free of openings, e.g. in the case of a current or temperature sensor routed in the planar part of the metal layer or layer stack <NUM>. That is, the one or more contact pads <NUM> are formed in a part <NUM> of the metal layer or layer stack <NUM> that has a generally planar surface topography. In another embodiment, part of the stress relieving layer or layer stack <NUM> has a large opening to provide a generally planar surface topography over which the one or more contact pads <NUM> are formed, e.g. to contact a metal layer disposed below the stress relieving layer or layer stack <NUM>. In either case, each contact pad <NUM> has a relatively top planar surface. External electric connections can be made to the one or more contact pads <NUM>, e.g., by way of bond wires, metal ribbons, metal clips, solder, etc. The remainder of the metal layer or layer stack <NUM> has a nonplanar surface topography which mimics the nonplanar surface topography of the underlying stress relieving layer or layer stack <NUM>. The exploded view in <FIG> enlarges the border between the planar and nonplanar surface topographies of the metal layer or layer stack <NUM>.

The metal layer or layer stack <NUM> may include one or more bridge areas <NUM> for electrically connecting neighboring regions of the metal layer or layer stack <NUM> without connecting the metal layer or layer stack <NUM> to an underlying conductive structure such as a metal or polysilicon line. The underlying conductive structure may be a source finger, gate finger, etc. routed under the metal layer or layer stack <NUM>. The stress relieving layer or layer stack <NUM> is present under each bridge area <NUM>, as descried herein, and acts as a bridge mechanism for connecting neighboring regions of the metal layer or layer stack <NUM> while also isolating the metal layer or layer stack <NUM> from an underlying conductive structure e.g. in the case of a gate finger, a source finger, a metal connection of a sensor such as a current or temperature, etc..

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the openings <NUM> in the stress relieving layer or layer stack <NUM> are arranged in a checkerboard pattern so that the patterned surface topography of the stress relieving layer or layer stack <NUM> has a checkerboard pattern which is transferred to the metal layer or layer stack <NUM>. The spacing (Sp) between adjacent ones of the openings <NUM> in the same row <NUM> of openings <NUM> in the stress relieving layer or layer stack <NUM> may be approximately equal to the width (W) of the openings <NUM>. Other spacings and widths are contemplated. The spacing (Sp) and the width (W) may be different, and may differ between rows of openings <NUM> in the stress relieving layer or layer stack <NUM>. The openings <NUM> in the stress relieving layer or layer stack <NUM> are not visible in <FIG>.

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the openings <NUM> in the stress relieving layer or layer stack <NUM> are arranged in a honeycomb pattern so that the patterned surface topography of the stress relieving layer or layer stack <NUM> has a honeycomb pattern which is transferred to the metal layer or layer stack <NUM>. The spacing (Sp) between adjacent ones of the openings <NUM> in the same row <NUM> of openings <NUM> in the stress relieving layer or layer stack <NUM> may be approximately equal to the width (W) of the openings <NUM>. Other spacings and widths are contemplated. The spacing (Sp) and the width (W) may be different, and may differ between rows of openings <NUM> in the stress relieving layer or layer stack <NUM>. The openings <NUM> in the stress relieving layer or layer stack <NUM> are not visible in <FIG>.

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the metal layer or layer stack <NUM> covers at least <NUM>% of the semiconductor body <NUM> and is segmented into separate sections <NUM>, <NUM>, <NUM>. Some of the sections <NUM>, <NUM>, <NUM> may include contact pads <NUM>, and/or some or all the sections <NUM>, <NUM>, <NUM> may form contact pads by themselves. In each case, each section <NUM>, <NUM>, <NUM> of the metal layer or layer stack <NUM> has the same or substantially same patterned shape as the portion of the surface of the stress relieving layer or layer stack <NUM> underlying that section <NUM>, <NUM>, <NUM>. The separate sections <NUM>, <NUM>, <NUM> may be electrically connected by to each other by bridge areas, e.g., as previously described herein in connection with <FIG>.

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. The embodiment shown in <FIG> is similar to the one shown in <FIG>. Different, however, the metal layer or layer stack <NUM> covers less than <NUM>%, e.g. between about <NUM>% to <NUM>%, of the semiconductor body <NUM>.

<FIG> illustrates a plan view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the stress relieving layer or layer stack <NUM> has a corrugated profile with alternating ridges <NUM> and grooves <NUM> in a transverse cross-section through any row of the plurality of openings <NUM>. The metal layer or layer stack <NUM> has the same or substantially same corrugated profile as the stress relieving layer or layer stack <NUM>.

<FIG> illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. According to this embodiment, the metal layer or layer stack <NUM> includes a barrier metal layer <NUM> such as WTi, Ta, TaN, TiN, Ti, W, TiW, etc. covering the top main surface <NUM> of the stress relieving layer or layer stack <NUM> and sidewalls <NUM> of the openings <NUM> in the stress relieving layer or layer stack <NUM>. The metal layer or layer stack <NUM> includes a copper layer <NUM> covering the barrier metal layer <NUM>. The barrier metal layer <NUM> and copper layer <NUM> may be formed using any common copper metallurgy process such as physical or chemical deposition, electroplating, etc. In some cases, the barrier metal layer <NUM> may be omitted if the base metal composition of the metal layer or layer stack <NUM> is less likely to diffuse, e.g., in the case of Cu-Ge alloys such as epitaxial CusGe. The material on which the stress relieving layer or layer stack <NUM> is formed may be the semiconductor body <NUM>, another layer or layer stack <NUM>, e.g., such as another Cu layer, an AICu layer, etc., or an insulating layer, e.g., such as oxide, nitride, silicon nitride, oxynitride, nitride-based ceramics, SiCOH, etc..

<FIG> illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. The exploded view in <FIG> enlarges part of the illustrated semiconductor device. According to this embodiment, the stress relieving layer or layer stack <NUM> comprises imide and covers the entire main surface <NUM> of the semiconductor body <NUM> over which the stress relieving layer or layer stack <NUM> is disposed. The overlying metal layer or layer stack <NUM> includes a barrier metal layer <NUM> such as WTi, Ta, TaN, TiN, etc. covering the top main surface <NUM> of the stress relieving layer or layer stack <NUM> and sidewalls <NUM> of the openings <NUM> in the stress relieving layer or layer stack <NUM>. The overlying metal layer or layer stack <NUM> includes a copper layer <NUM> covering the barrier metal layer <NUM>. The barrier metal layer <NUM> and copper layer <NUM> may be formed using any common copper metallurgy process such as physical or chemical deposition, electroplating, etc. The overlying metal layer or layer stack <NUM> is in electrical contact with an underlying metal layer or layer stack <NUM> through the openings <NUM> in the stress relieving layer or layer <NUM>. In one embodiment, the underlying metal layer or layer stack <NUM> includes an AICu layer <NUM> on which the stress relieving layer or layer <NUM> is formed and a barrier layer <NUM> such as W, TiW, etc. under the AICu layer. The barrier layer <NUM> is separated from the semiconductor body <NUM> by a dielectric layer <NUM>, e.g., such as borophosphosilicate glass (BPSG). The dielectric layer <NUM> may have grooves which allow for electrical contact to the semiconductor body <NUM>.

The plurality of openings <NUM> in the stress relieving layer or layer stack <NUM> may be arranged in a regular or irregular pattern so that the patterned surface topography of the stress relieving layer or layer stack <NUM> has a corresponding regular or irregular pattern, respectively. <FIG> illustrates an embodiment in which the spacing (Sp) between adjacent ones of the openings <NUM> in the same row of openings <NUM> in the stress relieving layer or layer stack <NUM> is approximately equal to the width (W) of the openings <NUM>. For example, the spacing (Sp) and the width (W) may be approximately <NUM> (microns). Other spacings and widths are contemplated, and the <NUM> example given above is purely illustrative and should not be considered limiting. The spacing (Sp) and the width (W) parameters may be different, and may differ across rows of openings <NUM> in the stress relieving layer or layer stack <NUM>.

The height or thickness (H) of the stress relieving layer or layer stack <NUM> may be in a range of about <NUM> to <NUM>, for example. The inventors have discovered that increasing the height / thickness (H) of an imide-based stress relieving layer or layer stack having a patterned surface topography as described herein from about <NUM> to <NUM> increases bow/warpage at lower temperatures below about <NUM> C, whereas the bow/warpage remains mostly unchanged for higher temperatures above about <NUM> C. The height / thickness (H) of the stress relieving layer or layer stack <NUM> instead may be less than <NUM> or greater than <NUM>. The inventors have also discovered that the bow/warpage change (slope) around <NUM> is flatter for dies with an imide-based stress relieving layer or layer stack having a patterned surface topography as described herein, compared with dies having zero coverage by such a patterned imide-based stress relieving layer or layer stack. This is particularly important as the solidification of solder happens around this temperature, leading to a more stable die attach process with respect to process variation of the die processing.

<FIG> illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack <NUM> formed on the stress relieving layer or layer stack <NUM>. The embodiment shown in <FIG> is similar to the one shown in <FIG>. Different, however, the plurality of openings <NUM> in the stress relieving layer or layer stack <NUM> are formed over a first part <NUM> of the semiconductor body <NUM> and a large opening is formed in the stress relieving layer or layer stack <NUM> over a second part <NUM> of the semiconductor body <NUM> adjacent the first part <NUM> to provide a generally planar surface topography. The metal layer or layer stack <NUM> contacts the underlying additional layer or layer stack <NUM> through the large opening. The inventors have discovered that partial coverage of a die with a stress relieving layer or layer stack having a patterned surface topography as described herein (e.g. about <NUM>% coverage or the inner part of the die) is still beneficial in terms of bow/warpage reduction, but not to the same extent as full coverage. The same also applies for placement of the patterned surface topography on the outer half (periphery) of the die.

In one embodiment, the first part <NUM> of the semiconductor body <NUM> is a central part of the semiconductor body <NUM> and the second part <NUM> is a periphery region of the semiconductor body <NUM> which is located along at least one side of the central part or which laterally surrounds the central part in its entirety. The semiconductor device formed in the semiconductor body <NUM> is disposed in the central part of the semiconductor body <NUM>, which may be considered the active region of the semiconductor body <NUM>. The active region of the semiconductor body <NUM> is the region of the semiconductor body <NUM> that includes the constituent parts of the device. For example, the active region may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc..

<FIG> illustrates a cross-sectional view of a semiconductor package <NUM> that includes the semiconductor device <NUM> shown in <FIG>. The semiconductor body <NUM> of the device <NUM> is attached to a standard substrate <NUM> such as a printed circuit board (PCB), lead frame, etc. The semiconductor package <NUM> also includes a metal connector <NUM> such as a clip attached at one end to the metal layer or layer stack <NUM> of the semiconductor device <NUM>. The opposite end of the metal connector <NUM> is attached to the substrate <NUM>, e.g., to a metal trace of a PCB, to a lead of a lead frame, etc. The metal connector <NUM> may be joined to the metal layer or layer stack <NUM> by solder <NUM>. The inventors have discovered that using a metal layer or layer stack having a patterned surface topography as described herein localizes and distributes solder voids in the 'dimpled' or 'depressed' regions <NUM> of the metal layer or layer stack <NUM>.

In one embodiment, part of the stress relieving layer or layer stack <NUM> may be free of openings or have a large opening to provide a generally planar surface topography. The metal layer or layer stack <NUM> may have a contact pad disposed over the generally planar surface topography, e.g., as described previously herein in connection with <FIG>, <FIG> and <FIG>. The metal connector <NUM> may be attached to the contact pad in this case. Still other metal connector attachment configurations are contemplated and within the scope of the embodiments described herein.

While the embodiments previously described herein describe the surface <NUM> of the metal layer or layer stack <NUM> with the patterned topography as being non-planarized, the surface <NUM> instead may be subjected to a planarization process such as chemical-mechanical polishing (CMP). <FIG> illustrates a corresponding a semiconductor device <NUM>. As shown in <FIG>, the top surface <NUM> of the metal layer or layer stack <NUM> is generally planar. Adequate stress relief is provided by the stress relieving layer or layer stack <NUM> since the openings <NUM> in the stress relieving layer or layer stack <NUM> are filled with metal. In some cases, the top surface <NUM> of the stress relieving layer or layer stack <NUM> may be partly visible after planarization of the metal layer or layer stack <NUM>, e.g. as shown in <FIG>. The metal layer or layer stack <NUM> may be recessed below the top surface <NUM> of the stress relieving layer or layer stack <NUM> depending on the type of planarization process employed or by design.

<FIG> illustrates a partial cross-sectional view of an embodiment in which a copper layer <NUM> and a barrier metal layer <NUM> are formed on the rear main surface <NUM> of the semiconductor body <NUM> to form a back-side metallization stack. According to this embodiment, the stress relieving layer or layer stack <NUM> has a higher elastic modulus than the back-side metallization stack <NUM>/<NUM> over the temperature range of interest. For example, the stress relieving layer or layer stack <NUM> may comprise doped silicon and/or polysilicon. In the case of doped silicon, the rear main surface <NUM> of the semiconductor body <NUM> may be doped with phosphorus, then structured, e.g., by etching, so that the rear main surface <NUM> of the semiconductor body <NUM> has recesses. The rear main surface <NUM> of the semiconductor body <NUM> is then covered by the barrier metal layer <NUM> and the recesses are then filled with the copper layer <NUM>. The stress relieving layer or layer stack <NUM> may compensate some of the stress imparted by the back-side metallization stack <NUM>/<NUM> during temperature cycling and/or residual stress in a way to reduce the likelihood of die bow/warpage and high mechanical stress, as previously described herein.

Spatially relative terms such as "under", "below", "lower", "over", "upper" and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first", "second", and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

Claim 1:
A semiconductor package comprising a power semiconductor device attached to a substrate (<NUM>) and a metal clip (<NUM>) attached at one end to a metal layer stack (<NUM>) of the power semiconductor device and at an opposite end to the substrate (<NUM>),
the power semiconductor device, comprising:
a semiconductor body (<NUM>);
a stress relieving layer or layer stack (<NUM>) disposed over at least part of the semiconductor body (<NUM>), the stress relieving layer or layer stack (<NUM>) comprising a plurality of openings (<NUM>) which yield a patterned surface topography for the stress relieving layer or layer stack (<NUM>);
the metal layer stack (<NUM>) formed on the stress relieving layer or layer stack (<NUM>) and occupying the plurality of openings (<NUM>) in the stress relieving layer or layer stack (<NUM>); and
a wiring layer (<NUM>) on which the stress relieving layer or layer stack (<NUM>) is formed,
wherein the metal layer stack (<NUM>) is in electrical contact with the wiring layer (<NUM>) through the plurality of openings (<NUM>) in the stress relieving layer or layer stack (<NUM>),
wherein the patterned surface topography of the stress relieving layer or layer stack (<NUM>) is transferred to a surface of the metal layer or layer stack (<NUM>) facing away from the semiconductor body (<NUM>) and the metal clip (<NUM>) is joined to the metal layer stack (<NUM>) by solder,
wherein the stress relieving layer or layer stack (<NUM>) has a different elastic modulus than the metal layer or layer stack (<NUM>) over a temperature range,
wherein the wiring layer (<NUM>) is arranged on a dielectric layer (<NUM>) that is directly formed on the semiconductor body (<NUM>) and comprises grooves which allow for electrical contact to the semiconductor body (<NUM>), and
wherein the metal layer stack (<NUM>) comprises a copper layer (<NUM>) and a barrier layer (<NUM>) separated from the semiconductor body (<NUM>) by the dielectric layer (<NUM>).