Patent Description:
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a semiconductor structure and a formation method thereof.

A Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones, tablet computers, or the like, due to its advantages, such as a small size, high integration, a fast transmission speed, or the like.

An existing dynamic random access memory includes bitlines and capacitor contact windows arranged alternately with the bitlines. However, when the bitlines and the capacitor contact windows are formed, a structure anomaly is easy to occur and a device yield is low due to the influence of a manufacturing process.

It is to be noted that the information disclosed in the above background section is intended only to enhance the understanding of the background of the present disclosure and therefore can include information that does not form the prior art known to those of ordinary skill in the art. Related technologies are known from <CIT>.

It should be understood that the general description above and the detailed description in the following are merely exemplary and illustrative, and cannot limit the present disclosure.

The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain principles of the present disclosure. Obviously, the accompanying drawings described below are merely some embodiments of the present disclosure. Those of ordinary skill in the art can also obtain other accompanying drawings according to the described accompanying drawings without creative efforts.

In the drawings, <NUM>: substrate; <NUM>: bitline structure; <NUM>: capacitor contact structure; <NUM>: air gap structure; <NUM>: substrate; <NUM>: bitline formation region; <NUM>: capacitor contact structure formation region; <NUM>: sacrificial layer; <NUM>: trench; <NUM>: through hole; <NUM>: first gap; <NUM>: second gap; <NUM>: insulating layer; <NUM>: bitline structure; <NUM>: first conductive layer; <NUM>: second conductive layer; <NUM>: passivation layer; <NUM>: capacitor contact structure; <NUM>: dielectric layer; <NUM>: substrate; <NUM>: bitline formation region; <NUM>: capacitor contact structure formation region; <NUM>: sacrificial layer; <NUM>: trench; <NUM>: through hole; <NUM>: first sacrificial structure; <NUM>: second sacrificial structure; <NUM>: first gap; <NUM>: filling layer; <NUM>: dielectric layer; <NUM>: insulating layer; <NUM>: bitline structure; <NUM>: first conductive layer; <NUM>: second conductive layer; <NUM>: passivation layer; <NUM>: capacitor contact structure.

Exemplary implementations are now described more comprehensively with reference to the accompanying drawings. However, the exemplary implementations may be implemented in various forms, and are not understood as being limited to the implementations described herein. Conversely, the exemplary implementations are provided to make the descriptions of the present disclosure more comprehensive and complete, and to completely convey the idea of the exemplary implementations to those skilled in the art. Identical reference numerals in the drawings represent identical or similar structures, and therefore, detailed descriptions thereof are omitted.

Relative terms, such as "upper" or "lower", as used in this specification, are directed to describe a relative relationship between one component and another component illustrated in the drawings, but these terms are used in this specification for convenience only, for example, according to the direction of the examples as shown in the drawings. It should be appreciated that if a device in the drawings is flipped upside down, the component indicated as being "upper" would become the component being "lower". When a structure is "on" another structure, it is possible to indicate that the structure is integrally formed on the another structure, or the structure is "directly" arranged on the another structure, or the structure is "indirectly" formed on the another structure through a further structure.

The terms "one", "a/an", "the" and "said" are intended to express the presence of one or more elements/components/or the like. The terms "include/comprise" and "have" are intended to be an open inclusion, and mean there may be additional elements/components/or the like other than the listed elements/components/or the like. The terms "first", "second", and "third" are meant to indication, but not to limit numbers of objects to which they modify.

In a related art, as shown in <FIG>, a semiconductor device mainly includes a plurality of bitline structures <NUM> and capacitor contact windows <NUM> configured to form capacitor contact structures that are alternately distributed and formed on a substrate <NUM>. During the manufacturing, the bitline structures <NUM> are required to be formed on the substrate <NUM> first and then a capacitor contact structure is formed between two adjacent bitline structures <NUM>. In addition, in order to reduce parasitic capacitance of the device, an air gap structure <NUM> is generally formed on a sidewall of each bitline structure <NUM>. However, the design of the air gap structure <NUM> weakens protection strength between the bitline structure <NUM> and the capacitor contact structure. Moreover, since the bitline structure <NUM> and the capacitor contact structure are formed in different periods, exposure deviation between layers is easy to occur, so that the capacitor contact structure is prone to misalignment, which easily causes damages to the air gap structure <NUM> when the capacitor contact window <NUM> is formed, thereby leading to a structure anomaly and a low device yield.

A first implementation of the present disclosure provides a semiconductor structure formation method. As shown in <FIG>, the formation method may include the following steps.

In step S110, a substrate is provided, and a sacrificial layer is formed on the substrate.

In step S120, the sacrificial layer is patterned to form trenches and through holes distributed side by side in the sacrificial layer.

In step S130, insulating layers covering a sidewall of the trench and a sidewall of the through hole are formed.

In step S140, a conductive layer and a passivation layer are sequentially formed in the trench and the through hole to form a bitline structure in the trench.

In step S150, the passivation layer in the through hole is removed to form a capacitor contact structure in the through hole.

A second implementation of the present disclosure provides a semiconductor structure formation method. As shown in <FIG>, the formation method may include the following steps.

In step S210, a substrate is provided, and a sacrificial layer is formed on the substrate.

In step S220, the sacrificial layer is patterned to form first sacrificial structures and second sacrificial structures distributed side by side.

In step S230, insulating layers covering a sidewall of the first sacrificial structure and a sidewall of the second sacrificial structure are formed.

In step S240, the first sacrificial structure is removed to form a trench, and the second sacrificial structure is removed to form a through hole.

In step S250, a conductive layer and a passivation layer are sequentially formed in the trench and the through hole to form a bitline structure in the trench.

In step S260, the passivation layer in the through hole is removed to form a capacitor contact structure.

In the semiconductor device, the semiconductor structure and the formation method thereof according to the embodiments of the present disclosure, two sides of the bitline structure and the capacitor contact structure can be insulated through the insulating layers to prevent the contact of the bitline structure and the capacitor contact structure with other structures and reduce a risk of short circuit. In addition, the capacitor contact structure and the bitline structure are formed simultaneously using a same manufacturing process, so as to prevent the misalignment of the capacitor contact structure caused by separate manufacturing of the capacitor contact structure and the bitline structure. Moreover, during the manufacturing, the bitline structure is formed in the trench, and the capacitor contact structure is formed in the through hole; that is, their positions are predefined; therefore, the capacitor contact structure formed may not deviate, thereby preventing the structure anomaly and improving the device yield.

Each step in the semiconductor structure formation method according to the first implementation of the present disclosure is described in detail below.

As shown in <FIG>, in step S110, a substrate is provided, and a sacrificial layer is formed on the substrate.

As shown in <FIG> and <FIG>, the substrate <NUM> may be of a plate structure, and a bitline formation region <NUM> and a formation region <NUM> of capacitor contact structures <NUM> may be predefined on the substrate <NUM>. The substrate <NUM> may be a rectangular, circular, oval, polygonal or irregular pattern, and may be made of silicon or other semiconductor materials. The shape and material of the substrate <NUM> are not specially limited.

A sacrificial layer <NUM> is formed on a surface of the substrate <NUM>. The sacrificial layer <NUM> may be a film formed on the substrate <NUM> or a coating formed on substrate <NUM>. For example, it may be a photoresist or a hard mask and may be made of silicon oxide, or the like, which are not specially limited herein. A thickness of the sacrificial layer <NUM> may be the same as that of the required bitline structure. In one implementation, the thickness may range from <NUM> to <NUM>. For example, the thickness may be <NUM>, <NUM>, <NUM> or <NUM>, and certainly, may also be other values, which are not listed herein. The sacrificial layer <NUM> may be formed on the substrate <NUM> by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or the like. Certainly, the sacrificial layer <NUM> may also be formed on the substrate <NUM> by using other processes, and a forming process of the sacrificial layer <NUM> is not specially limited herein.

As shown in <FIG>, in step S120, the sacrificial layer is patterned to form trenches and through holes distributed side by side in the sacrificial layer.

As shown in <FIG>, the sacrificial layer <NUM> is patterned by photolithography according to the predefined bitline formation region <NUM> and formation region <NUM> of capacitor contact structures <NUM>, so as to form trenches <NUM> and through holes <NUM> distributed side by side in the sacrificial layer <NUM>. The trench <NUM> may be connected at two ends in a direction perpendicular to the substrate <NUM>, may be strip-like in a direction parallel to the substrate <NUM>, and may extend along the direction parallel to the substrate <NUM>. The through hole <NUM> may be a circular hole, rectangular hole or irregular hole structure, which is not specially limited herein.

A plurality of through holes <NUM> may be provided. The plurality of through holes <NUM> may be arranged in a row and spaced along an extension direction of the trench <NUM>. In one implementation, each trench <NUM> may form a group with each column of through holes <NUM>, a plurality of groups of trenches <NUM> and through holes <NUM> distributed side by side may be formed, and columns formed by the trenches <NUM> and the through holes <NUM> in two adjacent groups are alternately distributed. That is, the through holes <NUM> are distributed on two sides of the trench <NUM> and may be spaced along an extension direction of the trench.

For example, a mask material layer may be formed on one side of the sacrificial layer <NUM> away from the substrate <NUM> by chemical vapor deposition, vacuum evaporation, atomic layer deposition or other means. The mask material layer may be of a multi-layer or monolayer structure, and may be made of at least one of a polymer, SiO<NUM>, SiN, poly and SiCN, and certainly, may also be made of other materials, which are not listed herein.

A photoresist layer may be formed on a surface of the mask material layer facing away from the sacrificial layer <NUM> by spin coating or other means. The photoresist layer may be made of a positive photoresist or a negative photoresist, which is not specially limited herein.

The photoresist layer may be exposed by using a photomask. A pattern of the photomask may match a pattern required by the sacrificial layer <NUM>. Then, the exposed photoresist layer may be developed to form a plurality of development regions. The mask material layer may be exposed from each development region, and a pattern of the development region may be the same as the pattern required by the sacrificial layer <NUM>. A size of each development region may match required sizes of the trench <NUM> and the through hole <NUM>.

The mask material layer may be etched in the development region by using a plasma etching process. The sacrificial layer <NUM> may be exposed from an etch region, so as to form a required mask pattern on the mask material layer. After completion of the etching process, the photoresist layer may be removed by cleaning with a cleaning solution or by a process such as ashing, or the like, so that the mask material layer is no longer covered with the photoresist layer, and a formed mask layer is exposed to obtain a hard mask structure.

The sacrificial layer <NUM> may be isotropically etched according to the mask pattern. For example, the sacrificial layer <NUM> may be etched in the development region of the mask pattern by a dry etching process, the substrate <NUM> is used as an etch stop layer, and the trenches <NUM> and the through holes <NUM> distributed side by side are formed in the sacrificial layer <NUM>. <FIG> shows a structure after completion of step S120 in the first implementation of the formation method according to the present disclosure.

As shown in <FIG>, in step S130, insulating layers covering a sidewall of the trench and a sidewall of the through hole are formed.

As shown in <FIG>, conformal insulating layers <NUM> are formed on a sidewall of the through hole <NUM> and a sidewall of the trench <NUM>, and the insulating layer <NUM> located on two sidewalls of the trench <NUM> may be spread over the two sidewalls of the trench <NUM>. When the trench <NUM> is strip-like, the insulating layer <NUM> located on the two sidewalls of the trench <NUM> may be arranged oppositely. The insulating layer <NUM> located on the sidewall of the through hole <NUM> may be spread over hole walls of the through hole <NUM>. That is, when the through hole <NUM> is a circular hole, the insulating layer <NUM> located on the sidewall of the through hole <NUM> may have a circular cross section in the direction parallel to the substrate <NUM>; when the through hole <NUM> is a rectangular hole, the insulating layer <NUM> located on the sidewall of the through hole <NUM> may have a rectangular cross section in the direction parallel to the substrate <NUM>. A thickness of the insulating layer <NUM> may range from <NUM> to <NUM>, and certainly, may also be in other ranges, which is not specially limited herein.

It is to be noted that the insulating layer <NUM> located on the sidewall of the trench <NUM> may be separated from the insulating layer <NUM> located on the sidewall of the through hole <NUM> through the sacrificial layer <NUM>. One side of the insulating layer <NUM> close to the substrate <NUM> may be in a contact connection with the substrate <NUM>, and one side thereof facing away from the substrate <NUM> may be flush with the surface of the sacrificial layer <NUM> facing away from the substrate <NUM>.

The insulating layer <NUM> may be a film formed on the sidewall of the through hole <NUM> and the sidewall of the trench <NUM> or a film layer formed on the sidewall of the through hole <NUM> and the sidewall of the trench <NUM>, which is not specially limited herein. The insulating layer <NUM> may be formed on the sidewall of the through hole <NUM> and the sidewall of the trench <NUM> by using a chemical vapor deposition process, and certainly, the insulating layer <NUM> may also be formed by using other processes, which is not specially limited herein.

It is to be noted that an etching ratio of a material of the sacrificial layer <NUM> to a material of the insulating layer <NUM> may be high. For example, the etching ratio of the material of the sacrificial layer <NUM> to the material of the insulating layer <NUM> may be greater than <NUM>:<NUM>. For example, the insulating layer <NUM> may be made of Si<NUM>N<NUM> or SiCN, and certainly, may also be made of other insulating materials, which are not listed one by one herein.

As shown in <FIG>, in step S140, a conductive layer and a passivation layer are sequentially formed in the trench and the through hole to form a bitline structure in the trench.

As shown in <FIG> and <FIG>, a bitline structure <NUM> may be formed in the trench <NUM>, the capacitor contact structure <NUM> is formed in the through hole <NUM> at the same time, and then the bitline structure <NUM> may be in a contact connection with a source or drain in the substrate <NUM> and the capacitor contact structure <NUM> may be in a contact connection with a capacitor, so as to store charges collected by the capacitor through the capacitor contact structure <NUM>.

It is to be noted that, when a plurality of through holes <NUM> are provided, the capacitor contact structure <NUM> may be formed in each through hole <NUM>. Each capacitor contact structure <NUM> may have a capacitor corresponding thereto. The charges may be stored simultaneously through a plurality of capacitor contact structures <NUM>, to improve storage capability of a DRAM. When a plurality of trenches <NUM> are provided, the bitline structure <NUM> may be formed in each trench <NUM>.

The conductive layer may be of a monolayer or multi-layer structure, and may be made of a conductor or semiconductor material, which may be, for example, polysilicon, silicon-germanium (SiGe), tungsten, titanium, cobalt, or the like, or compositions thereof, and certainly, may also be other conductive materials. For example, it may also be a metal silicide and compositions of different metal silicides. A number of film layers and the material of the conductive layer are not specially limited herein.

The conductive layer and the passivation layer <NUM> may be sequentially formed in the trench <NUM> and the through hole <NUM> by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or the like. Certainly, the conductive layer and the passivation layer <NUM> may also be formed in other manners, which are not listed one by one herein.

In one implementation, as shown in <FIG>, the step of sequentially forming a conductive layer and a passivation layer <NUM> in the trench <NUM> and the through hole <NUM> may include steps S1401 to S1403.

In step S1401, a first conductive layer is formed on a surface of the substrate exposed by the trench and the through hole.

As shown in <FIG>, the first conductive layer <NUM> may be a film formed on the surface of the substrate <NUM> and may be made of polysilicon. The first conductive layer <NUM> may be simultaneously formed, by atomic layer deposition, on the surface of the substrate <NUM> exposed by the trench <NUM> and the through hole <NUM>. The first conductive layer <NUM> may be in a contact connection with the substrate <NUM>, and a surface thereof facing away from the substrate <NUM> may be lower than one end of the insulating layer <NUM> facing away from the substrate <NUM>.

In step S1402, a second conductive layer is formed on a surface of the first conductive layer facing away from the substrate, a top surface of the second conductive layer being lower than that of the sacrificial layer.

As shown in <FIG>, the second conductive layer <NUM> may be a film formed on one side of the first conductive layer <NUM> facing away from the substrate <NUM> and may be made of tungsten. The second conductive layer <NUM> may be simultaneously formed, by vacuum evaporation or magnetron sputtering, on the side of the first conductive layer <NUM> facing away from the substrate <NUM>. The second conductive layer <NUM> may be in a contact connection with the first conductive layer <NUM>, and a surface thereof facing away from the first conductive layer <NUM> may be lower than the end of the insulating layer <NUM> facing away from the substrate <NUM>.

In step S1403, the passivation layer is formed on a surface of the second conductive layer facing away from the substrate, a top surface of the passivation layer being flush with that of the sacrificial layer <NUM>.

As shown in <FIG>, the passivation layer <NUM> may be a film formed on one side of the second conductive layer <NUM> facing away from the first conductive layer <NUM>, may be configured to protect a surface of the conductive layer, and may be made of silicon nitride. In order to facilitate the process, the passivation layer <NUM> may be simultaneously formed, by chemical vapor deposition or physical vapor deposition, on the side of the second conductive layer <NUM> facing away from the first conductive layer <NUM>, and then the bitline structure <NUM> may be formed in the trench <NUM>. It is to be noted that a surface of the passivation layer <NUM> facing away from the second conductive layer <NUM> may be flush with the top surface of the sacrificial layer <NUM>.

As shown in <FIG>, in step S150, the passivation layer in the through hole is removed to form a capacitor contact structure in the through hole.

As shown in <FIG>, the passivation layer <NUM> located in the through hole <NUM> may be removed to form the capacitor contact structure <NUM> in the through hole <NUM>; that is, the capacitor contact structure <NUM> may include a conductive layer formed on the substrate <NUM>. For example, the passivation layer <NUM> located in the through hole <NUM> may be removed by an anisotropic etching process, to form the capacitor contact structure <NUM> in each through hole <NUM>.

In one implementation of the present disclosure, the formation method according to the present disclosure may further include steps S160 and S170, as shown in <FIG>.

In step S160, the sacrificial layer is removed to form an isolation gap after the passivation layer is formed.

As shown in <FIG>, after the passivation layer <NUM> is formed, the sacrificial layer <NUM> may be removed by a wet etching process to form the isolation gap. The isolation gap may include a first gap <NUM> between two adjacent capacitor contact structures <NUM> in a same column and a second gap <NUM> between the bitline structure <NUM> and the capacitor contact structure <NUM> adjacent thereto.

For example, wet etching may be performed using an acid solution which may be hydrofluoric acid. For example, it may be buffered hydrofluoric acid (BHF), hydrofluoric acid at a concentration of <NUM>%, or dilute hydrofluoric acid (DHF). In use, a formulation ratio of the acid solution to deionized water may be set according to a specific material of the sacrificial layer <NUM>. A proportion and concentration of the etching solution are not specifically limited herein. By taking the first implementation of the present disclosure as an example, a structure after completion of step S160 is shown in <FIG>.

In step S170, a dielectric layer covering the isolation gap is formed.

As shown in <FIG> and <FIG>, the isolation gap may be filled with a dielectric layer. The dielectric layer may be made of a material with a low dielectric constant, which may effectively reduce parasitic capacitance between the bitline structures <NUM> and reduce power consumption of the device. For example, it may be a silicon oxide material. In one implementation, the dielectric layer may fill each isolation gap. In another implementation, the second gap <NUM> may be rapidly sealed during the deposition of the dielectric layer to form an air gap. Since a dielectric constant of the air is less than that of silicon oxide, the formation of the air gap can reduce the parasitic capacitance of the device. For example, a deposition rate of a dielectric layer <NUM> covering the isolation gap may be controlled to deposit the dielectric layer <NUM>, so as to rapidly seal the second gap <NUM> and form an air gap. Moreover, in order to prevent cracks between the bitline structures <NUM> in subsequent packaging and practical application and ensure device stability, a top surface of the air gap should not exceed that of the bitline structure <NUM>.

It is to be noted that the air gap may also be formed in a dielectric layer between two adjacent capacitor contact structures <NUM> while the second gap <NUM> is rapidly sealed, so as to further reduce the parasitic capacitance.

As shown in <FIG>, the substrate <NUM> may be of a plate structure, and a bitline formation region <NUM> and a formation region <NUM> of capacitor contact structures <NUM> may be predefined on the substrate <NUM>. The substrate <NUM> may be a rectangular, circular, oval, polygonal or irregular pattern, and may be made of silicon or other semiconductor materials. The shape and material of the substrate <NUM> are not specially limited.

As shown in <FIG>, a sacrificial layer <NUM> is formed on a surface of the substrate <NUM>. The sacrificial layer <NUM> may be a film formed on the substrate <NUM> or a coating formed on substrate <NUM>, and may be made of silicon oxide, which are not specially limited herein. The sacrificial layer <NUM> may be formed on the substrate <NUM> by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or the like. Certainly, the sacrificial layer <NUM> may also be formed on the substrate <NUM> by using other processes, and a forming process of the sacrificial layer <NUM> is not specially limited herein.

As shown in <FIG> and <FIG>, the sacrificial layer <NUM> is patterned by photolithography according to the predefined bitline formation region <NUM> and formation region <NUM> of capacitor contact structures <NUM>, so as to form first sacrificial structures <NUM> and second sacrificial structures <NUM> distributed side by side in the sacrificial layer <NUM>. The first sacrificial structure <NUM> may be strip-like in a direction parallel to the substrate <NUM>, and may extend along the direction parallel to the substrate <NUM>. The second sacrificial structure <NUM> may be a circular, rectangular or irregular column structure, which is not specially limited herein.

As shown in <FIG>, a plurality of second sacrificial structures <NUM> is provided. The plurality of second sacrificial structures <NUM> may be arranged in a column and may be spaced along an extension direction of the first sacrificial structure <NUM>. In one implementation, each first sacrificial structure <NUM> may form a group with each column of second sacrificial structures <NUM>, a plurality of groups of first sacrificial structures <NUM> and second sacrificial structures <NUM> distributed side by side may be formed, and columns formed by the first sacrificial structures <NUM> and the second sacrificial structures <NUM> in two adjacent groups are alternately distributed. That is, the second sacrificial structures <NUM> are distributed on two sides of the first sacrificial structure <NUM> and may be spaced along an extension direction of the first sacrificial structure <NUM>.

The photoresist layer may be exposed by using a photomask. A pattern of the photomask may match a pattern required by the sacrificial layer <NUM>. Then, the exposed photoresist layer may be developed to form a plurality of development regions. The mask material layer may be exposed from each development region, and a pattern of the development region may be the same as the pattern required by the sacrificial layer <NUM>. A size of each development region may match a required size of a region other than the first sacrificial structure <NUM> and the second sacrificial structure <NUM>.

The sacrificial layer <NUM> may be isotropically etched according to the mask pattern. For example, the sacrificial layer <NUM> may be etched in the development region of the mask pattern by a dry etching process, the substrate <NUM> is used as an etch stop layer, and the first sacrificial structures <NUM> and the second sacrificial structures <NUM> distributed side by side are formed in the sacrificial layer <NUM>. <FIG> shows a structure after completion of step S220 in the second implementation of the formation method according to the present disclosure.

As shown in <FIG> and <FIG>, conformal insulating layers <NUM> may be formed on a sidewall of the first sacrificial structure <NUM> and a sidewall of the second sacrificial structure <NUM>, and the insulating layer <NUM> located on two sidewalls of the first sacrificial structure <NUM> may be spread over the two sidewalls of the first sacrificial structure <NUM>. When the first sacrificial structure <NUM> is strip-like, the insulating layer <NUM> located on the two sidewalls of the first sacrificial structure <NUM> may be arranged oppositely. The insulating layer <NUM> located on the sidewall of the second sacrificial structure <NUM> may be spread over hole walls of the second sacrificial structure <NUM>. That is, when the second sacrificial structure <NUM> is a circular column, the insulating layer <NUM> located on the sidewall of the second sacrificial structure <NUM> may have a circular cross section in the direction parallel to the substrate <NUM>; when the second sacrificial structure <NUM> is a rectangular column, the insulating layer <NUM> located on the sidewall of the second sacrificial structure <NUM> may have a rectangular cross section in the direction parallel to the substrate <NUM>.

It is to be noted that, the insulating layer <NUM> located on the sidewall of the first sacrificial structure <NUM> may be in a contact connection with the insulating layer <NUM> located on the sidewall of the second sacrificial structure <NUM>; moreover, one side of the insulating layer <NUM> close to the substrate <NUM> may be in a contact connection with the substrate <NUM>, and one side thereof facing away from the substrate <NUM> may be flush with a surface of the sacrificial layer <NUM> facing away from the substrate <NUM>.

The insulating layer <NUM> may be a film formed on the sidewall of the second sacrificial structure <NUM> and the sidewall of the first sacrificial structure <NUM> or a film layer formed on the sidewall of the second sacrificial structure <NUM> and the sidewall of the first sacrificial structure <NUM>, which is not specially limited herein. The insulating layer <NUM> may be formed on the sidewall of the second sacrificial structure <NUM> and the sidewall of the first sacrificial structure <NUM> by using a chemical vapor deposition process, and certainly, the insulating layer <NUM> may also be formed by using other processes, which is not specially limited herein.

In one implementation of the present disclosure, an isolation gap may be provided between the first sacrificial structure <NUM> and the second sacrificial structure <NUM>. The isolation gap may include a first gap <NUM> between two adjacent capacitor contact structures <NUM> in a same column and a second gap (not shown in the drawings) between the bitline structure <NUM> and the capacitor contact structure <NUM>. In one implementation, after the insulating layers <NUM> covering the sidewall of the first sacrificial structure <NUM> and the sidewall of the second sacrificial structure <NUM> are formed, the second gap may be an air gap between the insulating layer <NUM> located on a sidewall of the bitline structure <NUM> and the insulating layer <NUM> located on a sidewall of the capacitor contact structure <NUM>.

The formation method according to the present disclosure may further include depositing a filling layer <NUM> in the isolation gap, as shown in <FIG> and <FIG>. The filling layer <NUM> may be removed after the bitline structure <NUM> and the capacitor contact structure <NUM> are formed, so as to prevent filling of the isolation gap with a conductive material during the formation of the bitline structure <NUM> and the capacitor contact structure <NUM>. The filling layer <NUM> may be made of a material with a small density to facilitate subsequent removal. The filling layer <NUM> may be formed in the isolation gap by chemical vapor deposition or physical vapor deposition. Certainly, the filling layer <NUM> may also be formed in other manners. The formation manner of the filling layer <NUM> is not specifically limited herein.

As shown in <FIG>, after the insulating layer <NUM> is formed, by using a wet etching process, the first sacrificial structure <NUM> may be removed to form a trench <NUM> and the second sacrificial structure <NUM> is removed at the same time to form a through hole <NUM>. For example, wet etching may be performed using an acid solution which may be hydrofluoric acid. For example, it may be buffered hydrofluoric acid (BHF), hydrofluoric acid at a concentration of <NUM>%, or dilute hydrofluoric acid (DHF). In use, a formulation ratio of the acid solution to deionized water may be set according to specific materials of the first sacrificial structure <NUM> and the second sacrificial structure <NUM>. A proportion and concentration of the etching solution are not specifically limited herein. A structure after completion of step S240 is shown in <FIG>.

As shown in <FIG>, a bitline structure <NUM> may be formed in the trench <NUM>, the capacitor contact structure <NUM> is formed in the through hole <NUM> at the same time, and then the bitline structure <NUM> may be in a contact connection with a source or drain in the substrate <NUM> and the capacitor contact structure <NUM> may be in a contact connection with a capacitor, so as to store charges collected by the capacitor through the capacitor contact structure <NUM>.

It is to be noted that, when a plurality of second contact structures are provided, a plurality of through holes <NUM> are also provided, and the capacitor contact structure <NUM> may be formed in each through hole <NUM>. Each capacitor contact structure <NUM> may have a capacitor corresponding thereto. The charges may be stored simultaneously through a plurality of capacitor contact structures <NUM>, to improve storage capability of a DRAM. When a plurality of first contact structures are provided, a plurality of trenches <NUM> are also provided, and the bitline structure <NUM> may be formed in each trench <NUM>, so as to lead out the device electrically.

In one implementation, as shown in <FIG>, the step of sequentially forming a conductive layer and a passivation layer <NUM> in the trench <NUM> and the through hole <NUM> may include steps S2501 to S2503.

In step S2501, a first conductive layer is formed on a surface of the substrate exposed by the trench and the through hole.

In step S2502, a second conductive layer is formed on a surface of the first conductive layer facing away from the substrate, a top surface of the second conductive layer being lower than that of the sacrificial layer.

In step S2503, the passivation layer is formed on a surface of the second conductive layer facing away from the substrate, a top surface of the passivation layer being flush with that of the sacrificial layer.

In one implementation of the present disclosure, subsequent to the step of forming a conductive layer and a passivation layer <NUM> in the trench <NUM> and the through hole <NUM>, the formation method according to the present disclosure may further include the following steps.

In step S270, the filling layer is removed to expose the isolation gap.

As shown in <FIG>, the filling layer <NUM> filling the isolation gap may be removed by using a wet etching process. For example, the filling layer <NUM> may be removed by acid-etching the filling layer <NUM> with an acid solution. The acid solution may selectively etch the filling layer <NUM>, which may not cause damages or destructions to other film layer structures.

In step S280, a deposition rate is controlled to form a dielectric layer covering the isolation gap, so as to rapidly seal the second gap and form an air gap, a top surface of the air gap not exceeding that of the bitline structure.

As shown in <FIG>, the isolation gap may be filled with a dielectric layer. The dielectric layer may be made of a material with a low dielectric constant, which may effectively reduce parasitic capacitance between the bitline structures <NUM> and reduce power consumption of the device. For example, it may be a silicon oxide material. In one implementation, the dielectric layer may fill each isolation gap. In another implementation, the second gap may be rapidly sealed during the deposition of the dielectric layer to form an air gap. Since a dielectric constant of the air is less than that of silicon oxide, the formation of the air gap can reduce the parasitic capacitance of the device. For example, a deposition rate of a dielectric layer <NUM> covering the isolation gap may be controlled to deposit the dielectric layer <NUM>, so as to rapidly seal the second gap and form an air gap. Moreover, in order to prevent cracks between the bitline structures <NUM> in subsequent packaging and practical application and ensure device stability, a top surface of the air gap should not exceed that of the bitline structure <NUM>.

It is to be noted that the air gap may also be formed in a dielectric layer between two adjacent capacitor contact structures <NUM> while the second gap is rapidly sealed, so as to further reduce the parasitic capacitance.

An implementation of the present disclosure further provides a semiconductor structure. The semiconductor structure may be formed with the semiconductor structure formation method in any one of the above implementations. The semiconductor structure and beneficial effects may be obtained with reference to the semiconductor structure formation method in any one of the above implementations, which are not described in detail herein.

An implementation of the present disclosure further provides a semiconductor device. The semiconductor device may include the semiconductor structure in any one of the above implementations and a capacitor in a contact connection with the capacitor contact structure <NUM> in the semiconductor structure. Charges collected in the capacitor may be stored through the capacitor contact structure <NUM>. The semiconductor device and beneficial effects may be obtained with reference to the semiconductor structure formation method in the above implementation, which are not described in detail herein. According to the invention, it is a Dynamic Random Access Memory (DRAM).

After considering the specification and practicing the invention disclosed herein, those skilled in the art would easily conceive of other implementations of the present disclosure.

Claim 1:
A method for forming a DRAM structure, comprising:
(S110) providing a substrate (<NUM>),
forming a sacrificial layer (<NUM>) on the substrate;
patterning (S120) the sacrificial layer to form trenches (<NUM>) and through holes (<NUM>) distributed side by side in the sacrificial layer;
forming (S130) insulating layers (<NUM>) covering a sidewall of the trenches and a sidewall of the through holes;
sequentially forming (S140) a conductive layer and a passivation layer (<NUM>) in the trenches and the through holes to form a bitline structure (<NUM>) in the trenches; and
removing (S150) the passivation layer (<NUM>) in the through holes to form a capacitor contact structure (<NUM>) in the through holes.