Patent Description:
In recent years, with the rapid progress of down-scaling of semiconductor elements due to the development of electronic technique, there is a demand for higher integration and lower power consumption of semiconductor chips. An interval between circuit components such as wirings is gradually decreasing, which may increase resistance between the wiring and the via. Research for limiting an increase of resistance between the wiring and the via is being conducted to improve the reliability of the semiconductor device. <CIT> describes a semiconductor device having a buried conductive line, with a portion buried in an active region, and an insulating isolating film in a side surface of the buried conductive line.

Aspects of the present disclosure provide a semiconductor device in which a plug conductive film included in the via is brought into direct contact with the wiring to reduce the resistance between the via and the wiring.

However, aspects of the present disclosure are not restricted to the one set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an aspect of the present disclosure, a semiconductor device includes a first film including a first side and a second side opposite to each other; a second film including a third side and a fourth side opposite each other, the third side of the second film being in contact with the second side of the first film, the second film and the first film defining parts of a trench, the trench including a first sub-trench and a second sub-trench below the first sub-trench, the first sub-trench having a first width and extending from the fourth side of the second film toward the first film, the second sub-trench below the first sub-trench having a second width, the second width being smaller than the first width; a plug conductive film extending from the first side of the first film to penetrate a bottom face of the trench, an uppermost face of the plug conducive film being inside the trench; a via including an insulating liner between the plug conductive film and the first film; and a wiring in the trench. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film in the trench is in contact with the wiring, and an upper face of the insulating liner is exposed by a bottom face of the second sub-trench.

According to an example embodiment of the present disclosure, a semiconductor device may include a first film including a first side and a second side opposite each other; a second film including a third side and a fourth side opposite each other, the third side of the second film being in contact with the second side of the first film; a wiring including a first portion and a second portion, the first portion having a first width and extending from the fourth side of the second film toward the first film, the second portion below the first portion and having a second width, and the second width being smaller than the first width; and a plug conductive film extending from the first side of the first film to penetrate a bottom face of the wiring, an uppermost face of the plug conductive film and a part of side walls of the plug conductive film being in contact with the wiring; and a via including an insulating liner between the plug conductive film and the first film. The insulating liner may be in contact with the second portion of the wiring. The wiring may further include a third portion below the second portion, the third portion having a third width smaller than the second width. The via may further include a barrier conductive film between the plug conductive film and the insulating liner, the barrier conductive film being in contact with the third portion.

According to an example embodiment of the present disclosure, a semiconductor device may include a substrate including a first side and a second side opposite each other; an active pattern on the first side of the substrate; a source/drain region in contact with the active pattern; a frontside wiring structure on the first side of the substrate, the frontside wiring structure extending in a first direction and being electrically connected to the source/drain region; a through contact via electrically connected to the source/drain region, the through contact via spaced apart from a side of the source/drain region; a buried wiring in the substrate and electrically connected to the through contact via; and a backside wiring structure electrically connected to the buried wiring, the backside wiring structure on the second side of the substrate. The buried wiring may include a first portion and a second portion below the first portion. The first portion may extend from the second side of the substrate toward the first side, and the first portion may have a first width. The second portion may have a second width. The second width may be smaller than the first width. The through contact via may include a plug conductive film and an insulating liner. The plug conductive film may penetrate through an upper face of the second portion. A lowermost face of the plug conductive film and a part of a side wall of the plug conductive film may be in contact with the buried wiring. The insulating liner may extend along the side wall of the plug conductive film.

The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings, in which:.

<FIG> is a diagram for explaining a semiconductor device according to some example embodiments. <FIG> and <FIG> are enlarged views of a portion A of <FIG>.

Referring to <FIG>, a semiconductor device according to some example embodiments may include a first film <NUM>, a second film <NUM>, a via <NUM>, and a wiring <NUM>.

The first film <NUM> may include a first side 10a and a second side 10b that are opposite to each other. In some example embodiments, the first film <NUM> may be a semiconductor substrate. For example, the first film <NUM> may be bulk silicon or silicon-on-insulator (SOI). The first film <NUM> may be a silicon substrate, or may include, but is not limited to, other materials, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. In some example embodiments, the first film <NUM> may include an insulating material. For example, the first film <NUM> may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

The second film <NUM> may be placed on the second side 10b of the first film <NUM>. The second film <NUM> may include a third side 20a and a fourth side 20b that are opposite to each other. The third side 20a of the second film <NUM> may be in contact with the second side 10b of the first film <NUM>. The second film <NUM> may include an insulating material. For example, the second film <NUM> may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

In the following description, an upper face, an uppermost face, an upper side, a lower face, a lowermost face, and a lower part are based on a direction facing from the first film <NUM> to the second film <NUM> or a direction facing from the via <NUM> to the wiring <NUM>, for example, a third direction DR3. A first direction DR1 and a second direction DR2 may intersect each other in a direction parallel to the first side 10a of the first film <NUM>. The third direction DR3 may intersect the first and second directions DR1 and DR2.

The first film <NUM> and the second film <NUM> may define parts of a trench t1. The trench t1 may be placed inside the second film <NUM> and the first film <NUM>. The trench t1 may extend from the fourth side 20b of the second film <NUM> toward the first film <NUM>. The trench t1 may penetrate the second film <NUM>, and a bottom face of the trench t1 may be placed in the first film <NUM>. The bottom face of the trench t1 may be placed below the third side 20a of the second film <NUM>. The bottom face of the trench t1 may have a step.

A width of the trench t1 in the first direction DR1 may decrease toward the first film <NUM>.

In some example embodiments, the trench t1 may include a first sub-trench t11, a second sub-trench t12, and a third sub-trench t13.

The first sub-trench t11 may have a first width W1. The second sub-trench t12 may be placed below the first sub-trench t11. The second sub-trench t12 may be formed on a bottom face t11bs of the first sub-trench t11. The second sub-trench t12 may have a second width W2 that is smaller than the first width W1. The third sub-trench t13 may be placed below the second sub-trench t12. The third sub-trench t13 may be formed on a bottom face t12bs of the second sub-trench t12. The third sub-trench t13 may have a third width W3 that is smaller than the second width W2. The bottom face t11bs of the first sub-trench t11 may be placed below the third side 20a of the second film <NUM>, the bottom face t12bs of the second sub-trench t12 may be placed below the bottom face t11bs of the second first sub-trench t11, and the bottom face t13bs of the third sub-trench t13 may be placed below the bottom face t12bs of the second sub-trench t12. The first to third widths W1, W2 and W3 may each mean widths of each of the bottom faces t11bs, t12bs and t13bs of the first to third sub-trench t11, t12 and t13 in the first direction DR1.

The via <NUM> may be placed in the first film <NUM>. The via <NUM> may extend from the first side 10a of first film <NUM> toward the second film <NUM>. An upper face of the via <NUM> may have a step.

In some example embodiments, the via <NUM> may include an insulating liner <NUM>, a first barrier conductive film <NUM>, and a first plug conductive film <NUM>.

The first plug conductive film <NUM> may extend from the first side 10a of the first film <NUM> to penetrate the bottom face of the trench t1. The first plug conductive film <NUM> may penetrate the bottom face t13bs of the third sub-trench t13. The upper face <NUM> of the first plug conductive film <NUM> may be placed above the bottom face t13bs of the third sub-trench t13 and the bottom face t12bs of the second sub-trench t12. The upper face <NUM> of the first plug conductive film <NUM> and a part of the side wall 36sw of the first plug conductive film <NUM> may be placed inside the trench t1. The upper face <NUM> of the first plug conductive film <NUM> and a part of the side wall 36sw of the first plug conductive film <NUM> may be exposed by the trench t1. The upper face <NUM> of the first plug conductive film <NUM> may be the uppermost face of the first plug conductive film <NUM>.

The width of the first plug conductive film <NUM> in the first direction DR1 may decrease toward the second film <NUM>.

In some example embodiments, the first plug conductive film <NUM> may include a seam <NUM> therein. The seam <NUM> may extend in the third direction DR3.

The first plug conductive film <NUM> may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

The first barrier conductive film <NUM> may be placed between the first plug conductive film <NUM> and the insulating liner <NUM>. The first barrier conductive film <NUM> may extend from the first side 10a of the first film <NUM> along at least a part of the side wall 36sw of the first plug conductive film <NUM>. The upper face <NUM> of the first barrier conductive film <NUM> may be placed below the upper face <NUM> of the first plug conductive film <NUM> and the upper face <NUM> of the insulating liner <NUM>. The upper face <NUM> of the first barrier conductive film <NUM> may be exposed by the bottom face t13bs of the third sub-trench t13.

The first barrier conductive film <NUM> may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh) and two-dimensional materials (2D materials).

The insulating liner <NUM> may be placed between the first plug conductive film <NUM> and the first film <NUM>. The insulating liner <NUM> may be placed on at least a part of the side walls of the barrier conductive film <NUM>. The insulating liner <NUM> extends from the first side 10a of the first film <NUM>, and the upper face <NUM> of the insulating liner <NUM> may be placed below the upper face <NUM> of the first plug conductive film <NUM>. The upper face <NUM> of the insulating liner <NUM> may be exposed by the bottom face t12bs of the second sub-trench t12.

The insulating liner <NUM> may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride or combinations thereof.

The wiring <NUM> extends from the fourth side 20b of the second film <NUM> toward the first film <NUM>, and a bottom face thereof may be placed inside the first film <NUM>. The wiring <NUM> may be placed inside the trench t1. The wiring <NUM> may fill at least a part of the trench t1. The width of the wiring <NUM> in the first direction DR1 may decrease toward the first film <NUM>.

In some example embodiments, the wiring <NUM> may have a single conductive film structure. The wiring <NUM> may include a second plug conductive film <NUM>. The second plug conductive film <NUM> may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

In some example embodiments, the wiring <NUM> may not include an insulating liner. In some example embodiments, the wiring <NUM> may further include an insulating liner (not shown in <FIG>). The insulating liner may extend along the side walls of the second plug conductive film <NUM>. The insulating liner may include an insulating material for electrically isolating the second plug conductive film <NUM> from the first and second films <NUM> and <NUM>.

Referring to <FIG>, in some example embodiments, the wiring <NUM> may fill the trench t1. Therefore, the wiring <NUM> may include a first portion <NUM>, a second portion <NUM> below the first portion <NUM> and having a width smaller than the first portion <NUM>, and a third portion <NUM> below the second portion <NUM> and having a width smaller than the second portion <NUM>. For example, the first portion <NUM> may have a first width W1, the second portion <NUM> may have a second width W2, and the third portion <NUM> may have a third width W3. A lower face of the wiring <NUM> may have a step.

The wiring <NUM> may be in contact with the upper face <NUM> of the first plug conductive film <NUM> and at least a part of the side wall 36sw of the first plug conductive film <NUM>. The wiring <NUM> may be in contact with the upper face <NUM> and the side walls 36sw of the first plug conductive film <NUM> exposed by the trench t1. That is, the first plug conductive film <NUM> may penetrate through the bottom face 43bs of the third portion <NUM> of the wiring <NUM>, and the upper part of the first plug conductive film <NUM> may be placed inside the wiring <NUM> and be in contact with the wiring <NUM>. Accordingly, the via <NUM> may be electrically connected to the wiring <NUM>.

The wiring <NUM> may fill the trench t1 to come into contact with the upper face <NUM> of the insulating liner <NUM> and the upper face <NUM> of the first barrier conductive film <NUM>.

Referring to <FIG>, in some example embodiments, the wiring <NUM> may fill a part of the trench t1. A void 20v may be formed between the wiring <NUM> and the first barrier conductive film <NUM>. The void 20v may be formed when the wiring <NUM> does not completely fill the trench t1 in the process of forming the wiring <NUM>. The shape and placement of the void 20v are not limited to those shown in <FIG>, and may vary.

For example, the wiring <NUM> may include a first portion <NUM>, and a second portion <NUM> having a smaller width than the first portion <NUM> below the first portion <NUM>. The void 20v may be formed between the second portion <NUM> of the wiring <NUM> and the first barrier conductive film <NUM>.

In the semiconductor device according to some example embodiments, since the wiring <NUM> is in direct contact with the first plug conductive film <NUM> of the via <NUM>, an interfacial resistance may be reduced, as compared with a case where the first barrier conductive film <NUM> is placed between the wiring <NUM> and the first plug conductive film <NUM>, and the wiring <NUM> is in contact with the first barrier conductive film <NUM>. In addition, since the wiring <NUM> is in contact with the upper face <NUM> and a part of the side wall 36sw of the first plug conductive film <NUM>, a contact area between the wiring <NUM> and the first plug conductive film <NUM> increases, and the interfacial resistance may decrease.

<FIG> is a diagram for explaining a semiconductor device according to some example embodiments. For convenience of explanation, points that are different from those explained using <FIG> will be mainly explained.

Referring to <FIG>, in the semiconductor device according to some example embodiments, the wiring <NUM> may have multiple conductive film structures. The wiring <NUM> may include a second barrier conductive film <NUM> and a second plug conductive film <NUM>.

The second barrier conductive film <NUM> may extend along the side walls and bottom face of the trench t1. The second barrier conductive film <NUM> may extend along bottom faces t11bs, t12bs and t13bs of each of the first to third sub-trench t11, t12 and t13. The second barrier conductive film <NUM> may be in contact with the upper face <NUM> of the insulating liner <NUM> and the upper face <NUM> of the first barrier conductive film <NUM>. For example, the second barrier conductive film <NUM> may fill the second sub-trench t12 and the third sub-trench t13, and may be in contact with the upper face <NUM> of the first plug conductive film <NUM>. Alternatively, unlike this, the upper face <NUM> of the first plug conductive film <NUM> may be placed inside the second plug conductive film <NUM>, and the upper face <NUM> of the first plug conductive film <NUM> may be in contact with the second plug conductive film <NUM>.

The second barrier conductive film <NUM> may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh) and two-dimensional materials (2D materials).

The second plug conductive film <NUM> may be placed on the second barrier conductive film <NUM>. The second plug conductive film <NUM> may fill the trench t1 on the second barrier conductive film <NUM>.

<FIG> is a diagram for explaining a semiconductor device according to some example embodiments. <FIG> are enlarged views of a portion B of <FIG>.

Referring to <FIG>, in some example embodiments, the via <NUM> may include an insulating liner <NUM> and a first plug conductive film <NUM>.

The first plug conductive film <NUM> may include a first portion <NUM>, and a second portion <NUM> placed below the first portion <NUM>. An upper face <NUM> of the first portion <NUM> may be the upper face <NUM> of the first plug conductive film <NUM>. The first portion <NUM> may have a fourth width W4. The fourth width W4 may be smaller than the second width W2. The second portion <NUM> may have a fifth width W5 larger than the fourth width W4. The fifth width W5 may be smaller than the second width W2. The fourth width W4 may be a width of the upper face of the first portion <NUM> in the first direction DR1, and the fifth width W5 may be a width of the upper face of the second portion <NUM> in the first direction DR1. The fourth and fifth widths W4 and W5 may each be widths of the first and second portions <NUM> and <NUM> in the first direction DR1 at a boundary between the first and second portions <NUM> and <NUM>. That is, the first portion <NUM> and the second portion <NUM> may have a step at the boundary.

In some example embodiments, a grain size of the first portion <NUM> may be different from the grain size of the second portion <NUM>. The grain size of the first portion <NUM> may be smaller than the grain size of the second portion <NUM>. This may be attributed to the manufacturing process of the first plug conductive film <NUM>.

In some example embodiments, the first portion <NUM> may include the same material as the second portion <NUM>. In some example embodiments, the first portion <NUM> may include a different material from the second portion <NUM>.

The insulating liner <NUM> may extend along at least a part of the side walls 361sw and 362sw of the first plug conductive film <NUM>. The insulating liner <NUM> may be in contact with the first plug conductive film <NUM>. The insulating liner <NUM> may extend along at least a part of the side wall 362sw of the second portion <NUM>.

In the semiconductor devices according to some example embodiments, the trench t1 may include a first sub-trench t11 and a second sub-trench t12. The first portion <NUM> may penetrate the bottom face t12bs of the second sub-trench t12. The upper face <NUM> of the first portion <NUM> and the side walls 361sw of the first portion <NUM> may be exposed by the trench t1. The upper face <NUM> of the insulating liner <NUM> may be exposed by the second sub-trench t12.

Referring to <FIG>, in some example embodiments, the wiring <NUM> fills the trench t1, and may include a first portion <NUM>, and a second portion <NUM> having a width smaller than the first portion <NUM> below the first portion <NUM>. The first plug conductive film <NUM> may penetrate through the second portion <NUM>.

The wiring <NUM> may be in contact with the upper face <NUM> of the first portion <NUM> of the first plug conductive film <NUM> and the side wall 361sw of the first portion <NUM> of the first plug conductive film <NUM>. The wiring <NUM> may be in contact with the upper face <NUM> of the second portion <NUM> of the first plug conductive film <NUM>. The wiring <NUM> may be in contact with the upper face <NUM> of the insulating liner <NUM>.

Referring to <FIG>, in some example embodiments, the wiring <NUM> may be in contact with the upper face <NUM> of the first portion <NUM> and a part of the side walls 361sw of the first portion <NUM>. A void 40v may be formed between the wiring <NUM> and the insulating liner <NUM>. The shape and placement of the void 40v are not limited to those shown in <FIG>, and may vary.

Referring to <FIG> and <FIG>, unlike <FIG>, in some example embodiments, the bottom face t12bs of the second sub-trench t12 may be placed below an interface between the first portion <NUM> and the second portion <NUM>. That is, a part of the side wall 362sw of the second portion <NUM> may be further exposed by the trench t1.

The wiring <NUM> may be in contact with the upper face <NUM> of the first portion <NUM>, the side walls 361sw of the first portion <NUM>, the upper face <NUM> of the second portion <NUM>, and a part of the side walls 362sw of the second portion <NUM>. The wiring <NUM> may be in contact with the upper face <NUM> of the insulating liner <NUM>.

Referring to <FIG>, in some example embodiments, the void 40v may be formed between the wiring <NUM> and the insulating liner <NUM>. The shape and placement of the void 40v are not limited to those shown in <FIG>, and may vary.

Referring to <FIG>, in some example embodiments, the first plug conductive film <NUM> may not include a seam inside. Referring to <FIG>, in some example embodiments, the first portion <NUM> may include a seam <NUM> inside, but the second portion <NUM> may not include a seam inside.

Referring to <FIG>, in the semiconductor device according to some example embodiments, the wiring <NUM> may have multiple conductive film structures. The wiring <NUM> may include a second barrier conductive film <NUM> and a second plug conductive film <NUM>. The second barrier conductive film <NUM> may extend along bottom faces t11bs and t12bs of each of the first and second sub-trench t11 and t12. The second barrier conductive film <NUM> may be in contact with the upper face <NUM> of the insulating liner <NUM> and the upper face <NUM> of the first barrier conductive film <NUM>. For example, the second barrier conductive film <NUM> may fill the second sub-trench t12, and may be in contact with the upper face <NUM> of the first plug conductive film <NUM>. Alternatively, unlike this, the upper face <NUM> of the first plug conductive film <NUM> may be placed inside the second plug conductive film <NUM>, and the upper face <NUM> of the first plug conductive film <NUM> may be in contact with the second plug conductive film <NUM>.

<FIG> are intermediate operation diagrams for describing a method of manufacturing the semiconductor device according to some example embodiments.

Referring to <FIG>, a second film <NUM> including a third side 20a and a fourth side 20b may be provided. A first film <NUM> including a first side 10a and a second side 10b may be provided on the third side 20a of the second film <NUM>. The first film <NUM> may be placed on the third side 20a of the second film <NUM>.

A trench 10t may be formed inside the first film <NUM>. The trench 10t may extend from the first side 10a of the first film <NUM> toward the second side 10b and penetrate through the first film <NUM>. For example, the bottom face of the trench 10t may be placed inside the second film <NUM>.

An insulating liner <NUM> extending along the side walls and bottom face of the trench 10t may be formed. A first barrier conductive film <NUM> extending along the insulating liner <NUM> may be formed on the insulating liner <NUM>. The insulating liner <NUM> and the first barrier conductive film <NUM> may be conformally formed. A first plug conductive film <NUM> may be formed on the first barrier conductive film <NUM>. The first plug conductive film <NUM> may fill the trench 10t that remains after the insulating liner <NUM> and the first barrier conductive film <NUM> are formed. The first plug conductive film <NUM> may include a seam <NUM> inside.

Referring to <FIG>, a first sub-trench t11 may be formed in the second film <NUM>. The first sub-trench t11 may extend from the fourth side 20b of the second film <NUM> toward the third side 20a. The first sub-trench t11 may expose at least a part of the via <NUM>. That is, the via <NUM> may have a shape penetrating through the bottom face of the first sub-trench t11. The insulating liner <NUM> of the via <NUM> may be exposed by the first sub-trench t11.

Alternatively, in a case where the second film <NUM> is a substrate, the substrate may be removed and an insulating material may be applied. The second film <NUM> including the insulating material may be formed, accordingly. Next, the above-described first sub-trench t11 may be formed.

Referring to <FIG>, the insulating liner <NUM> exposed by the first sub-trench t11 may be removed. The insulating liner <NUM> may be removed by a dry etching process or a wet etching process.

The upper face of the insulating liner <NUM> may be placed below the bottom face of the first sub-trench t11. Accordingly, the second sub-trench t12 may be formed under the first sub-trench t11. That is, the via <NUM> may have a shape penetrating through the bottom face of the second sub-trench t12. The first barrier conductive film <NUM> and the insulating liner <NUM> of the via <NUM> may be exposed by the first and second sub-trench t11 and t12.

Referring to <FIG>, the first barrier conductive film <NUM> exposed by the first and second sub-trench t11 and t12 may be removed. The first barrier conductive film <NUM> may be removed by a dry etching process or a wet etching process.

The upper face of the first barrier conductive film <NUM> may be placed below the bottom face of the second sub-trench t12. Accordingly, the third sub-trench t13 may be formed under the second sub-trench t12, and the trench t1 including the first to third sub-trench t11, t12 and t13 may be formed. That is, the via <NUM> may have a shape penetrating through the bottom face of the third sub-trench t13. The upper face of the via <NUM> may be exposed by the trench t1.

Next, referring to <FIG>, a wiring <NUM> that fills the trench t1 may be formed. The wiring <NUM> may be formed by a selective bottom up metal fill manner, on the basis of the first plug conductive film <NUM> exposed by the trench t1. Alternatively, referring to <FIG>, after forming the second barrier conductive film <NUM>, a second plug conductive film <NUM> may be formed on the second barrier conductive film <NUM>.

Alternatively, after forming an insulating liner that extends along the side walls and bottom face of trench t1, the lower face of the insulating liner may be removed to expose the upper face of the via <NUM>. Subsequently, the second plug conductive film <NUM> that fills the trench t1 that remains after the insulating liner is formed, or the second barrier conductive film <NUM> and the second plug conductive film <NUM> may be formed. The wiring <NUM> including an insulating liner may be formed, accordingly.

<FIG> are intermediate operation diagrams for explaining a method of manufacturing the semiconductor device according to some example embodiments. <FIG> is an intermediate step diagram for explaining steps after <FIG>.

Referring to <FIG> and <FIG>, a part of the first barrier conductive film <NUM> and a part of the first plug conductive film <NUM> may be removed. This may be performed by an etch-back process. The first portion <NUM> of the first plug conductive film <NUM> may remain.

At this time, all the seams <NUM> in the first plug conductive films <NUM> may be removed. Alternatively, the seam <NUM> may remain inside the first portion <NUM>.

Referring to <FIG>, a second portion <NUM> of the first plug conductive film <NUM> may be formed on the first portion <NUM> of the first plug conductive film <NUM>. The second portion <NUM> may be formed by an optional bottom-up metal fill manner, on the basis of the first portion <NUM>. The second portion <NUM> may be formed without the barrier conductive film, and the grain size of the second portion <NUM> may be greater than the grain size of the first portion <NUM>. As a result, the first plug conductive film <NUM> which has a larger volume, a relatively larger grain size, no seam inside, and a low resistance may be formed, as compared to a case where the barrier conductive film is present.

Referring to <FIG>, a first sub-trench t11 may be formed in the second film <NUM>. The first sub-trench t11 may extend from the fourth side 20b of the second film <NUM> toward the third side 20a and expose the insulating liner <NUM> of the via <NUM>.

The insulating liner <NUM> exposed by the first sub-trench t11 may then be removed. The insulating liner <NUM> may be removed by a dry etching process or a wet etching process. Accordingly, the second sub-trench t12 may be formed under the first sub-trench t11. The upper face of the via <NUM> may be exposed by the trench t1.

Next, referring to <FIG>, the wiring <NUM> that fills the trench t1 may be formed. The wiring <NUM> may be formed by a selective bottom-up metal fill manner, on the basis of the first plug conductive film <NUM> exposed by the trench t1. Alternatively, referring to <FIG>, after forming the second barrier conductive film <NUM>, the second plug conductive film <NUM> may be formed on the second barrier conductive film <NUM>.

Alternatively, after forming an insulating liner that extends along the side walls and bottom face of the trench t1, the lower face of the insulating liner may be removed to expose the upper face of the via <NUM>. Subsequently, the second plug conductive film <NUM> that fills the trench t1 that remains after forming the insulating liner, or the second barrier conductive film <NUM> and the second plug conductive film <NUM> may be formed. The wiring <NUM> including the insulating liner may be formed, accordingly.

<FIG> is a layout diagram for explaining a semiconductor device according to some example embodiments. <FIG> and <FIG> are schematic cross-sectional views taken along A-A of <FIG>. <FIG> is a schematic cross-sectional view taken along B-B of <FIG>. <FIG> is a schematic cross-sectional view taken along C-C of <FIG>.

Referring to <FIG>, a semiconductor device according to some example embodiments includes a first substrate <NUM>, an active pattern AP, a field insulating film <NUM>, a gate structure GS, a gate spacer <NUM>, a gate capping pattern <NUM>, a source/drain region <NUM>, an interlayer insulating film <NUM>, a frontside wiring structure FS, a through contact via <NUM>, a buried wiring <NUM>, and a backside wiring structure BS. The source/drain region <NUM> may be referred to as a source/drain structure <NUM>.

The first substrate <NUM> may be a semiconductor substrate. For example, the first substrate <NUM> may be bulk silicon or silicon-on-insulator (SOI).

The first substrate <NUM> may include a first side 100a and a second side 100b that are opposite to each other. An active pattern AP may be placed on the first side 100a of the first substrate <NUM>. In this specification, the first side 100a of the first substrate <NUM> on which the active pattern AP is placed may also be called a front side. Also, the second side 100b of the first substrate <NUM> opposite to the first side 100a may also be called a back side.

The active pattern AP may be formed on the first side 100a of the first substrate <NUM>. The active pattern AP may extend along a second direction DR2 parallel to the first side 100a. Also, the plurality of active patterns AP may extend side by side in the second direction DR2.

In some example embodiments, the active pattern AP may include first to third bridge patterns <NUM> to <NUM> which are sequentially stacked on the first substrate <NUM>, spaced apart from each other and each extend in the second direction DR2. This active pattern AP may be used as a channel region of a multi-bridge-channel field-effect transistor (MBCFET)® (registered trademark) including a multi-bridge channel. The number of bridge patterns included in the active pattern AP is an example only, and is not limited to that shown.

In some example embodiments, the active pattern AP may further include a fin pattern <NUM>. The fin pattern <NUM> may protrude from the first side 100a of the first substrate <NUM> and extend in the second direction DR2. The first to third bridge patterns <NUM> to <NUM> may be sequentially stacked on the upper face of the fin pattern <NUM>.

The field insulating film <NUM> may be formed on the first side 100a of the first substrate <NUM>. The field insulating film <NUM> may surround at least a part of the side faces of the active pattern AP. In some example embodiments, the field insulating film <NUM> may include a concave upper face. For example, a height of the upper face of the field insulating film <NUM> on the basis of the first side 100a of the first substrate <NUM> may decrease and then remain constant, as it goes away from the fin pattern <NUM>. Although the upper part of the fin pattern <NUM> is only shown to protrude from the upper face of the field insulating film <NUM>, this is an example only. As another example, the upper face of the fin pattern <NUM> may be coplanar with the upper face of the field insulating film <NUM>.

The field insulating film <NUM> may include, for example, but is not limited to, at least one of silicon oxide (SiO<NUM>), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN) or combinations thereof.

A gate structure GS may be formed on the active pattern AP and the field insulating film <NUM>. The gate structure GS may intersect the active pattern AP. For example, the gate structure GS may extend in the first direction DR1 parallel to the first side 100a and intersecting the second direction DR2.

In some example embodiments, at least a part of the active pattern AP may extend in the second direction DR2 and penetrate through the gate structure GS. For example, the first to third bridge patterns <NUM> to <NUM> may each extend in the second direction DR2 and penetrate through the gate structure GS. The gate structure GS may surround periphery of each of the first to third bridge patterns <NUM> to <NUM>.

The gate structure GS may include a gate dielectric film <NUM> and a gate electrode <NUM>. The gate dielectric film <NUM> and the gate electrode <NUM> may be sequentially stacked on the active pattern AP.

The gate dielectric film <NUM> may be stacked on the active pattern AP. For example, the gate dielectric film <NUM> may extend along the upper face and side faces of the active pattern AP and the upper face of the field insulating film <NUM>. Also, the gate dielectric film <NUM> may surround the periphery of at least a part of the active pattern AP. For example, the gate dielectric film <NUM> may extend along the periphery of each of the first to third bridge patterns <NUM> to <NUM>.

The gate dielectric film <NUM> may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride or a high dielectric constant material having a higher dielectric constant than silicon oxide.

A semiconductor device according to some example embodiments may include a NC (Negative Capacitance) FET using a negative capacitor. For example, the gate dielectric film <NUM> may include a ferroelectric material film having ferroelectric properties, and a paraelectric material film having paraelectric properties.

A gate electrode <NUM> may be stacked on the gate dielectric film <NUM>. That is, the gate dielectric film <NUM> may be interposed between the active pattern AP and the gate electrode <NUM>. The gate dielectric film <NUM> may be interposed between the field insulating film <NUM> and the gate electrode <NUM>.

Although the gate electrode <NUM> is only shown as a single film, this is merely an example, and it goes without saying that the gate electrode <NUM> may be formed by stacking a plurality of conductive layers. For example, the gate electrode <NUM> may include a work function adjusting film that adjusts the work function, and a filling conductive film that fills a space formed by the work function adjusting film. The work function adjusting film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

A gate spacer <NUM> may be formed on the first substrate <NUM> and the field insulating film <NUM>. Also, the gate spacer <NUM> may extend along the side faces of the gate electrode <NUM>. In some example embodiments, a part of the gate dielectric film <NUM> may be interposed between the gate electrode <NUM> and the gate spacer <NUM>. For example, the gate dielectric film <NUM> may further extend along the inner face of the gate spacer <NUM>.

The gate spacer <NUM> may include an insulating material, for example, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

The gate capping pattern <NUM> may be formed on the gate structure GS. The gate capping pattern <NUM> may extend along the upper face of the gate structure GS. Although the upper face of the gate capping pattern <NUM> is only shown as being coplanar with the upper face of the gate spacer <NUM>, this is an example only. As another example, the gate capping pattern <NUM> may cover the upper face of the gate spacer <NUM>.

The gate capping pattern <NUM> may include an insulating material, for example, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

The source/drain region <NUM> may be formed on at least one side face (e.g., both side faces) of the gate structure GS. Additionally, the source/drain regions <NUM> may be connected to the active pattern AP. For example, the upper face of the fin pattern <NUM> may be connected to the source/drain region <NUM>. Also, the first to third bridge patterns <NUM> to <NUM> may each penetrate the gate structure GS and the gate spacer <NUM>, and be connected to the source/drain region <NUM>. The source/drain region <NUM> may be electrically isolated from the gate electrode <NUM> by the gate dielectric film <NUM> and/or the gate spacers <NUM>. Such a source/drain region <NUM> may be provided as a source or a drain of a field effect transistor including the active pattern AP and the gate structure GS.

In some example embodiments, the source/drain region <NUM> may include an epitaxial layer. For example, the source/drain region <NUM> may be an epitaxial pattern formed by an epitaxial growth process.

The interlayer insulating film <NUM> may be formed to fill the space on the outer face of the gate spacer <NUM>. For example, the interlayer insulating film <NUM> may cover the field insulating film <NUM> and the source/drain region <NUM>. The interlayer insulating film <NUM> may cover the upper face of the gate spacer <NUM> and the upper face of the gate capping pattern <NUM>.

The interlayer insulating film <NUM> may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a low dielectric constant material having a dielectric constant smaller than silicon oxide.

The frontside wiring structure FS may be placed on the first side 100a of the first substrate <NUM>. For example, the frontside wiring structure FS may be formed on the upper face of the interlayer insulating film <NUM>. The frontside wiring structure FS may include a front inter-wiring insulating film <NUM>, a plurality of frontside wiring patterns FM1 to FM4, and a plurality of frontside via patterns FV1 to FV4. The frontside wiring patterns FM1 to FM4 may be sequentially stacked on the interlayer insulating film <NUM>. The frontside via patterns FV1 to FV4 may be sequentially stacked on the interlayer insulating film <NUM>. The frontside via patterns FV1 to FV4 may connect the frontside wiring patterns FM1 to FM4 to each other. The frontside wiring patterns FM1 to FM4 and the frontside via patterns FV1 to FV4 may be formed inside the front inter-wiring insulating film <NUM>. The frontside wiring patterns FM1 to FM4 and the frontside via patterns FV1 to FV4 may be insulated from each other by the front inter-wiring insulating film <NUM>, respectively. The number of layers, the number, the placement and the like of the front inter-wiring insulating film <NUM>, the frontside wiring patterns FM1 to FM4, and the frontside via patterns FV1 to FV4 are merely examples, and are not limited to those shown in the drawings.

In some example embodiments, the width of each of the frontside via patterns FV1 to FV4 may decrease toward the first side 100a of the first substrate <NUM>.

The frontside wiring structure FS may provide a signal line and/or a power line for various electronic elements (e.g., the field effect transistor including the active pattern AP and the gate structure GS) formed on the first side 100a of the first substrate <NUM>. For example, the source/drain contact CA may be formed on the source/drain region <NUM>. The source/drain contact CA may penetrate through the interlayer insulating film <NUM> and be connected to the source/drain region <NUM>. A first frontside via pattern FV1 of the frontside wiring structure FS may be connected to the source/drain contact CA. The frontside wiring structure FS may be electrically connected to the source/drain region <NUM>, accordingly. The silicide film <NUM> may be placed between the source/drain region <NUM> and the source/drain contact CA.

The frontside wiring patterns FM1 to FM4 and the frontside via patterns FV1 to FV4 may each include a barrier conductive film and a filling conductive film.

In some example embodiments, the width of each source/drain contact CA may decrease toward the first side 100a of the first substrate <NUM>.

The backside wiring structure BS may be placed on the second side 100b of the first substrate <NUM>. The backside wiring structure BS may include a backside inter-wiring insulating film <NUM>, a plurality of backside wiring patterns BM1 to BM3, and a plurality of backside via patterns BV1 to BV3. The backside wiring patterns BM1 to BM3 may be sequentially stacked on the second side 100b of the first substrate <NUM>. The backside via patterns BV1 to BV3 may be sequentially stacked on the second side 100b of the first substrate <NUM>. The backside via patterns BV1 to BV3 may connect the backside wiring patterns BM1 to BM3 to each other. The backside wiring patterns BM1 to BM3 and the backside via patterns BV1 to BV3 may be formed inside the backside inter-wiring insulating film <NUM>. The backside wiring patterns BM1 to BM3 and the backside via patterns BV1 to BV3 may be insulated from each other by the backside inter-wiring insulating film <NUM>. The number of layers, number, placement and the like of the backside inter-wiring insulating film <NUM>, the backside wiring patterns BM1 to BM3, and the backside via patterns BV1 to BV3 are merely examples, and are not limited to that shown.

In some example embodiments, the width of each of the backside via patterns BV1 to BV3 may decrease toward the second side 100b of the first substrate <NUM>.

In some example embodiments, the backside wiring structure BS may provide a power delivery network (PDN) for various electronic elements (e.g., a field effect transistor including the active pattern AP and gate structure GS) formed on the first side 100a of the first substrate <NUM>. For example, the backside wiring structure BS may be electrically connected to the buried pattern PR. A power supply voltage (for example, a source voltage VSS or a drain voltage VDD) supplied from the outside may be transferred to the uppermost wiring (for example, a third backside wiring pattern BM3) of the backside wiring structure BS, and may be provided to the source/drain region <NUM> through the buried pattern PR, the through contact via <NUM> and the source/drain contact CA.

In some example embodiments, the buried pattern PR may extend in the second direction DR2 from a planar point of view. Such a buried pattern PR may be provided as a power rail for various electronic elements (e.g., the field effect transistor including the active pattern AP and the gate structure GS) formed on the first side 100a of the first substrate <NUM>.

Although it is not specifically shown, the backside wiring patterns BM1 to BM3 and the backside via patterns BV1 to BV3 may each include a barrier conductive film and a filling conductive film.

The through contact via <NUM> may extend in the third direction DR3 and penetrate the interlayer insulating film <NUM> and the field insulating film <NUM>. The through contact via <NUM> may be electrically connected to various electronic elements (e.g., the field effect transistors including the active patterns AP and the gate structures GS) formed on the first side 100a of the first substrate <NUM>.

In some example embodiments, the through contact via <NUM> may be electrically connected to the source/drain contact CA. For example, the through contact via <NUM> may be in contact with the source/drain contact CA. The through contact via <NUM> may be in contact with, for example, the upper face of the source/drain contact CA in the third direction DR3.

In some example embodiments, the width of the through contact via <NUM> may gradually decrease in the third direction DR3 from the frontside wiring structure FS to the backside wiring structure BS.

The buried wiring <NUM> may be formed inside the first substrate <NUM>. The buried wiring <NUM> may be connected to the through contact via <NUM>. For example, the upper face of the buried wiring <NUM> may be connected to the lower part of the through contact via <NUM> penetrating the first side 100a of the first substrate <NUM>. Accordingly, the buried wiring <NUM> may be electrically connected to various electronic elements (e.g., the field effect transistor including the active pattern AP and the gate structure GS) formed on the first side 100a of the first substrate <NUM>. As an example, the buried wiring <NUM> may be electrically connected to the source/drain region <NUM>.

In some example embodiments, the width of the buried wiring <NUM> may gradually increase in the third direction DR3 from the first side 100a of the first substrate <NUM> to the second side 100b of the first substrate <NUM>.

Referring to <FIG>, the through contact via <NUM> may include an insulating liner <NUM>, a first barrier conductive film <NUM> and a first plug conductive film <NUM>. The first plug conductive film <NUM> may include a seam <NUM> inside. The through contact via <NUM>, the buried wiring <NUM>, and the first substrate <NUM> may correspond to any one via, wiring, and second film among the via <NUM>, the wiring <NUM>, and the second film <NUM> described using <FIG>. The insulating liner <NUM>, the first barrier conductive film <NUM> and the first plug conductive film <NUM> may correspond to any one insulating liner, first barrier conductive film and first plug conductive film among the insulating liner <NUM>, the first barrier conductive film <NUM> and the first plug conductive film <NUM> described using <FIG>. Although the via <NUM> and the wiring <NUM> of <FIG> are shown as the through contact via <NUM> and the buried wiring <NUM> in <FIG>, the embodiment is not limited thereto.

Referring to <FIG>, the through contact via <NUM> may include an insulating liner <NUM> and a first plug conductive film <NUM>. The through contact via <NUM>, the buried wiring <NUM>, and the first substrate <NUM> may correspond to any one via, wiring and second film among the via <NUM>, the wiring <NUM>, and the second film <NUM> described using <FIG>. The insulating liner <NUM> and the first plug conductive film <NUM> may correspond to any one of insulating liner and first plug conductive film among the insulating liner <NUM> and the first plug conductive film <NUM> described using <FIG>. Although the via <NUM> and the wiring <NUM> of <FIG> are shown as the through contact via <NUM> and the buried wiring <NUM> in <FIG>, the embodiment is not limited thereto. The plug conductive film <NUM> may include a first portion <NUM>, and a second portion <NUM> placed below the first portion <NUM>.

<FIG> and <FIG> are diagrams for explaining a semiconductor device according to some example embodiments. <FIG> and <FIG> are schematic cross-sectional views taken along B-B of <FIG>.

Referring to <FIG>, in the semiconductor device according to some example embodiments, inner spacers <NUM> may be further placed on the side faces of the gate electrode <NUM>. The inner spacers <NUM> may be formed on side faces of the gate electrode <NUM> between the first to third bridge patterns <NUM> to <NUM>. Also, the inner spacers <NUM> may be formed on the side faces of the gate electrode <NUM> between the fin pattern <NUM> and the first bridge pattern <NUM>. The gate electrode <NUM> may be electrically isolated from the source/drain region <NUM> by the gate dielectric film <NUM>, the gate spacer <NUM> and/or the inner spacers <NUM>.

The inner spacers <NUM> may include the same material as the gate spacers <NUM> or may include different material from the gate spacers <NUM>.

Referring to <FIG>, in the semiconductor device according to some example embodiments, the outer walls of the source/drain region <NUM> may have a wavy shape.

<FIG> and <FIG> are diagrams for explaining the semiconductor device according to some example embodiments. <FIG> is a schematic cross-sectional view taken along B-B of <FIG>. <FIG> is a schematic cross-sectional view taken along C-C of <FIG>. For convenience of explanation, points different from those explained using <FIG> will be mainly explained.

Referring to <FIG> and <FIG>, in the semiconductor device according to some example embodiments, the active pattern AP does not include a bridge pattern. The active pattern AP may be a fin-shaped pattern protruding upward from the upper face of the field insulating film <NUM>.

<FIG> is a layout diagram for explaining a semiconductor device according to some example embodiments. <FIG> and <FIG> are schematic cross-sectional views taken along line D-D of <FIG>.

Referring to <FIG>, in the semiconductor device according to some example embodiments, the through contact via <NUM> may be electrically connected to the frontside wiring structure FS. For example, the through contact via <NUM> may be in contact with the frontside wiring pattern FM1.

Referring to <FIG>, the through contact via <NUM> may include an insulating liner <NUM>, a first barrier conductive film <NUM>, and a first plug conductive film <NUM>. The first plug conductive film <NUM> may include a seam <NUM> inside. The through contact via <NUM>, the buried wiring <NUM>, and the first substrate <NUM> may correspond to any one via, wiring and second film among the via <NUM>, the wiring <NUM>, and the second film <NUM> described using <FIG>. The insulating liner <NUM>, the first barrier conductive film <NUM> and the first plug conductive film <NUM> may correspond to any one insulating liner, first barrier conductive film and first plug conductive film among the insulating liner <NUM>, the first barrier conductive film <NUM> and the first plug conductive film <NUM> described using <FIG>. Although the via <NUM> and the wiring <NUM> of <FIG> are shown as the through contact via <NUM> and the buried wiring <NUM> in <FIG>, the embodiment is not limited thereto.

Claim 1:
A semiconductor device comprising:
a first film (<NUM>) including a first side (10a) and a second side (10b) opposite to each other;
a second film (<NUM>) including a third side (20a) and a fourth side (20b) opposite each other, the third side of the second film being in contact with the second side of the first film,
the second film and the first film defining parts of a trench (t1),
the trench including a first sub-trench (t11) and a second sub-trench (t12) below the first sub-trench,
the first sub-trench having a first width (W1) and extending from the fourth side of the second film toward the first film,
the second sub-trench below the first sub-trench having a second width (W2), the second width being smaller than the first width;
a plug conductive film (<NUM>) extending from the first side of the first film to penetrate a bottom face of the trench, an uppermost face (<NUM>) of the plug conductive film being inside the trench;
a via (<NUM>) including an insulating liner (<NUM>) between the plug conductive film and the first film; and
a wiring (<NUM>) in the trench, wherein
the uppermost face of the plug conductive film and at least a part of a side wall (36sw) of the plug conductive film in the trench are in contact with the wiring, and
an upper face (<NUM>) of the insulating liner is exposed by a bottom face (t12bs) of the second sub-trench.