Patent Description:
Substrates for power electronics are different than printed circuit boards used for low power microelectronics. The power electronics substrate both provides the interconnections to form an electrical circuit and cool the components. Power electronic substrates carry higher currents and provide a higher voltage isolation (up to several thousand volts), as compared to microelectronic counterparts, and operate over a wide temperature range (e.g., up to <NUM>).

Direct bonded copper (DBC), also known as direct copper bonded (DCB) substrates, have very good thermal conductivity, and are thus suitable for power modules. DCBs are composed of a ceramic tile with a sheet of copper bonded to one or both sides of the ceramic tile. Insulated metal substrates (IMS) are also used for power modules and consist of a metal baseplate covered by a thin layer of dielectric and a layer of copper. IMS are single-sided substrates.

A problem that exists for power substrates having DCB layers is known as DCB warpage. DCB warpage occurs when there is a mismatch of the coefficient of thermal expansion (CTE) of the components being soldered onto the DCB surface. This warpage may also occur on single-sided IMS substrates.

<CIT> refers to an electronic apparatus comprising a substrate and a conductor layer having a first sub-conductor layer and second sub-conductor layer provided in the substrate, where an electronic device is provided in the first conductor layer.

<CIT> refers to a connector for connecting electrodes of a semiconductor device, having a metal plate with vertical and horizontal grooves formed at its front side which overlap with vertical and horizontal peaks provided at back side.

<CIT> refers to a semiconductor device having a perpendicular guide section which is formed corresponding to the thickness of the electronic component such that the chip lead slides perpendicularly.

An exemplary embodiment of a power substrate assembly in accordance with the present disclosure may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first surface connected to a ceramic tile. The chip is soldered onto the first surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.

A power substrate assembly designed to reduce power substrate warpage is disclosed herein. The power substrate has a ceramic tile sandwiched between two DCB surfaces, or alternatively a ceramic tile adjacent a single DCB surface. The power substrate assembly features a clip and a trimetal to avoid power substrate warpage. The trimetal has a button array and the clip has a cavity array, where the button array is designed to mate with the cavity array. In contrast to prior art designs, the arrangement mitigates the likelihood of warpage to the power substrate. Modifications are made to the ceramic tile to further improve resistance to DCB warpage of the power substrate.

For the sake of convenience and clarity, terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", "lateral", "transverse", "radial", "inner", "outer", "left", and "right" may be used herein to describe the relative placement and orientation of the features and components, each with respect to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. Said terminology is not intended to be limiting and includes the words specifically mentioned, derivatives therein, and words of similar import.

As used herein, power substrates refer variously to direct bonded copper (DBC), also known as direct copper bonded (DCB) substrates and insulated metal substrates (IMS). The principles shown and described herein may refer to either of these types of substrates. For simplicity, these substrates are referred to as power substrates.

<FIG> are representative drawings of a power substrate assembly <NUM> experiencing warpage, according to the prior art. <FIG> is a perspective view and <FIG> is a side view of the power substrate assembly <NUM>. The power substrate assembly <NUM> features a power chip <NUM> (hereinafter, "chip <NUM>") that is soldered to a power substrate <NUM>, where the power substrate <NUM> consists of a first surface <NUM> and a second surface <NUM>, with a ceramic tile <NUM> sandwiched therebetween. The first surface <NUM> and the second surface <NUM> may be direct copper bonded (DCB) substrates. The substrate assembly <NUM> may alternatively have a single surface <NUM>, thus making the power substrate an insulated metal substrate (IMS). The power substrate assembly <NUM> also features a clip <NUM> and a trimetal <NUM>, where the trimetal <NUM> connects the chip <NUM> to the clip <NUM>. Solder 106a, 106b, and 106c (collectively, "solder <NUM>") are used to make connections between parts, with solder 1206a connecting the clip <NUM> to the trimetal <NUM>, solder 106b connecting the chip <NUM> to the power substrate <NUM>, and solder 106c connecting the clip <NUM> to the power substrate <NUM>.

In <FIG>, a DCB warpage line <NUM> shows how the power substrate <NUM> bends over the lifetime of the power substrate assembly <NUM>. Though perhaps more pronounced for illustrative purposes, the DCB warpage line <NUM> makes it possible to imagine the effects such a bending of the power substrate <NUM> could compromise one or more of the solders <NUM>, particularly those connecting directly to the power substrate <NUM> (e.g., solder 106b and 106c).

<FIG> are representative drawings of a power substrate assembly <NUM>, according to exemplary embodiments. <FIG> is a perspective view and <FIG> is a side view of the power substrate assembly <NUM>, while <FIG> is a perspective view of the clip <NUM>, <FIG> is a side view of the trimetal <NUM>, and <FIG> is a perspective view of the trimetal <NUM>. The power substrate assembly <NUM> enables some components to be coupled together without the use of solder, in exemplary embodiments.

The trimetal <NUM> consists of a trapezoid structure <NUM>, a clip portion <NUM>, and a base <NUM>. The trapezoid structure <NUM> sits atop the base <NUM> and is sandwiched between the base <NUM> and the clip <NUM>. In a non-limiting example, the base <NUM> is a rounded rectangular shape, that fits atop a power chip <NUM> (hereinafter, "chip <NUM>") within the diameter of the chip <NUM>. In exemplary embodiments, the trimetal <NUM> consists of a button array <NUM> for coupling with the clip <NUM>. In this example, there are two rows of buttons <NUM> in the button array <NUM>, though this is not meant to be limiting. As shown in <FIG>, the buttons <NUM> of the button array <NUM> are disposed on a bottom surface of the clip portion <NUM> of the trimetal <NUM>.

The clip <NUM> consists of a base <NUM> and a foot <NUM>, where the base is substantially parallel to the power substrate <NUM> and the foot <NUM> is for connection to the power substrate <NUM> using solder 206b, while the chip <NUM> is connected to the power substrate <NUM> using solder 206a (collectively, "solder <NUM>"). In exemplary embodiments, the solder 206a is either solder or silver (Ag) sintering while the solder 206b is solder.

In exemplary embodiments, the clip <NUM> further includes a cavity array <NUM>, the cavity array having multiple cavities <NUM>. In this example, there are two rows of cavities <NUM> forming the cavity array <NUM>, though this is not meant to be limiting. The cavity array <NUM> is disposed on a top surface of the base <NUM> of the clip <NUM>. In exemplary embodiments, the base <NUM> of the clip <NUM> is designed to fit into the clip portion <NUM> of the trimetal <NUM>. Further, the cavity array <NUM> of the clip <NUM> is sized to receive the button array <NUM> of the trimetal <NUM> such that each individual button <NUM> of the button array <NUM> fits into respective cavities <NUM> of the cavity array <NUM>. Alternatively, the clip <NUM> could feature a button array while the trimetal <NUM> features a cavity array.

In exemplary embodiments, the trapezoid structure <NUM> of the trimetal <NUM> is sized to be a height, h, based on the configuration of the clip <NUM>, so that, when the base <NUM> of the clip <NUM> is positioned into the clip portion <NUM> of the trimetal <NUM>, the foot <NUM> of the clip <NUM> sits on the power substrate <NUM>. For the power substrate assembly <NUM>, no solder is used to connect the clip <NUM> to the trimetal <NUM>. Instead, the button array <NUM> of the trimetal <NUM> fits into the cavity array <NUM> of the clip <NUM>. Thus, in exemplary embodiments, even if the power substrate <NUM> experiences warpage, the clip <NUM> will remain coupled to the trimetal <NUM>.

The power substrate assembly <NUM> thus features a power substrate <NUM> having a first DCB surface <NUM> connected to a ceramic tile <NUM>, a chip <NUM> soldered onto the first DCB surface <NUM>, a clip <NUM> to be attached to the power substrate <NUM>, and a trimetal <NUM> to connect the chip <NUM> to the clip <NUM>. The clip <NUM> has a foot <NUM> at one end that is soldered to the power substrate <NUM> and a recessed area at the other end of the clip <NUM>. The recessed area may be a cavity array <NUM> featuring one or more cavities <NUM>. The trimetal <NUM> connects the chip <NUM> to the clip <NUM> and has a base <NUM> to be soldered to the chip <NUM>, a trapezoid structure <NUM> seated atop the base <NUM>, and a clip portion <NUM> on top of the trapezoid structure <NUM>, the clip portion <NUM> having a projecting area. The projecting area may be a button array <NUM> featuring one or more buttons <NUM>. The buttons <NUM> and the cavities <NUM> are arranged so that each button <NUM> fits snugly into each respective cavity <NUM>. The recessed area of the clip <NUM> fits into the projecting area of the trimetal <NUM>.

Table <NUM> provides a comparison between the materials used in power substrates versus using the power substrate assembly <NUM> disclosed herein. K88 is a leadframe manufacturer that uses copper and alloys to make the lead terminals both strong and flexible, resulting in a springlike quality to the leads. Rthjc is the impedance from junction to case (outside surface of package). In exemplary embodiments, the clip <NUM> for the above-described power substrate assembly <NUM> is impregnated with a material to make the clip springier yet maintain hardness. Where lead frames typically have a hardness vector (HV) of <NUM> to <NUM>, in exemplary embodiments, the clip <NUM> of the power substrate assembly <NUM> has a HV of between <NUM> and <NUM>. Further, in exemplary embodiments, where prior art power substrates typically used Aluminum Oxide (Al<NUM>O<NUM>), Aluminum Nitride (AlN), or Zirconia Toughened Alumina (ZTA), the power substrate assembly <NUM> utilizes ceramic made of Si<NUM>N<NUM> (Silicon Nitride) for better performance rather than AlN. Further, by using a pressure contact clip (e.g., clip <NUM>) rather than a soldered clip in the power substrate assembly <NUM>, the clip has a self-cleaning capability, that is, the clip <NUM> self-cleans the surface to maintain a good connection to the tri-metal <NUM>, in exemplary embodiments.

In exemplary embodiments, the ceramic tile used for the power substrate assembly <NUM> is modified from prior art power assemblies to enhance the strength of the power substrate. Table <NUM> provides characteristic data about the ceramic tile. In exemplary embodiments, thermal conductivity, bending strength, and fracture toughness are all considered when selecting the ceramic tile for the power substrate assembly <NUM>. In exemplary embodiments, the ceramic tiles are made using Silicon Nitride (Si<NUM>N<NUM>), with a favorable combination to thermal conductivity, bending strength, and toughness, as compared to standard Al<NUM>O<NUM>, AlN, or ZTA.

Claim 1:
A substrate assembly comprising:
a power substrate comprising a first direct copper bonded (DCB) surface coupled to a ceramic tile;
a chip soldered onto the first DCB surface;
a clip attached to the power substrate, the clip comprising:
a foot coupled to the power substrate, wherein the foot is disposed at a first end of the clip; and
a recessed area disposed at a second end of the clip, the second end being opposite the first end; and
a trimetal comprising:
a base soldered to the chip;
a trapezoid structure disposed atop the base; and
a clip portion disposed atop the trapezoid structure, the clip portion further
comprising a projecting area;
wherein the recessed area of the clip fits into the projecting area of the trimetal.