Patent Description:
Low power devices, in particular low power battery or super-capacitor operated devices, require a measurement and monitoring of the supply voltage. Conventional measurement of the battery or super-capacitor voltage produces a quiescent current that may discharge the battery or super-capacitor. Document <CIT> describes a measurement apparatus. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance. Document <CIT> discusses an analog to digital converter ("ADC") that can be used in a system with an internal or external CPU or in an ASIC. The ADC includes a band gap reference (BGR) circuit whose output is internally coupled to an analog input of the ADC; and a positive analog supply voltage (AVDD) and a positive analog reference voltage (REFP) operationally coupled to a same voltage supply; wherein a BGR value is used by a CPU as a calibration constant for determining an AVDD value, a REFP value, and a Bit Weight value. Document <CIT> describes a system and method for measuring voltage of individual cells connected in series includes a single flying capacitor. The capacitor stores the charge of one of the cells such that an analog-to-digital converter (ADC) connected to the capacitor may process an accurate representation of the voltage of the cell being measured. A plurality of switches electrically connects and disconnects the cells from the capacitor. A controller is in communication with the ADC and the switches for sequencing the switches and recording the voltage measurements of each cell. At least one precision voltage reference device is included to provide the ADC a reference voltage to provide self-calibration. Document <CIT> discusses a calibration device for a mobile terminal and an ADC module thereof, the ADC module being disposed inside a baseband chip. The calibration device includes a bandgap voltage reference inside the mobile terminal platform for generating a reference voltage; the device further includes a circuit for connecting the bandgap voltage reference, the circuit being connected with the ADC module for providing the reference voltage generated by the bandgap voltage reference to the ADC module. The prior art uses a bandgap voltage reference inside a mobile terminal platform to provide voltage to an ADC module, which, during the ADC module calibration, does not require an external reference voltage source to perform the ADC calibration, and therefore greatly reduces calibration errors and improves calibration efficiency. Document <CIT> describes highly accurate, self-calibrating data processors and methods for calibrating the same use internal analog references with negligible time and temperature drifts. A first input reference signal set generated by any accurate, precision analog reference is applied to a data processor. The corresponding output response is compared to the theoretical ideal output response to determine the data processor's initial gain and offset errors. This information can be stored in non-volatile memory, re-called, and used to compensate for the data processor's initial gain and offset errors during actual use of the data processor. Subsequent errors due to time and temperature drifting can be determined by comparing the output responses to a second input reference signal set which is generated by the internal analog reference. The subsequent errors can be combined with the initial errors to compensate for system errors within the data processor. Document <CIT> discusses a method of calibrating a circuit that includes coupling a first reference voltage to a first input of the circuit, coupling a programmable reference voltage to a reference node of a digital-to-analog converter (DAC), such that the gain of the DAC is dependent on an input value at the reference node. The method further includes providing a first predetermined input code to the DAC, summing an output of the DAC with the first reference voltage to produce a summed output, comparing the summed output to a threshold, and adjusting the programmable reference voltage until the summed output is within a predetermined range of the threshold.

Further enhancements are discussed in the dependent claims.

Embodiments of the present disclosure include a voltage measurement circuit that includes a sensor configured to measure a bandgap/reference voltage, a capacitive voltage divider (CVD), an analog-to-digital converter (ADC), and a control circuit configured to: measure, with the ADC, a bandgap/reference voltage and determining a first code value of the bandgap voltage, charge a first capacitor to a voltage to be measured and determine, with the ADC, a second code value of voltage of the first capacitor, charge a second capacitor to a second known voltage and determine, with the ADC, a third code value of voltage of the second capacitor, and determine the voltage to be measured by applying the first, second, and third code values.

In combination with any of the above embodiments, a computer, electronic device, system, or apparatus may include such a voltage measurement circuit. In combination with any of the above embodiments, a method may be performed. A method for measuring a voltage using a CVD and an analog-to-digital converter includes the steps of measuring a bandgap/reference voltage and determining a first code value of the bandgap/reference voltage, charging a first capacitor to a voltage to be measured and determining a second code value of voltage of the first capacitor, charging a second capacitor to a second known voltage and determining a third code value of voltage of the second capacitor, and determining the voltage to be measured by applying the first, second, and third code values.

In combination with any of the above embodiments, the voltage to be measured is further determining by applying a factor to convert the code values. In combination with any of the above embodiments, the factor is based upon a bit size of an analog to digital converter that is to determine the code values. In combination with any of the above embodiments, the first capacitor and the second capacitor are a same capacitor. In combination with any of the above embodiments, performing analog to digital conversion to find the voltage to be measured produces no quiescent current. In combination with any of the above embodiments, the voltage to be measured is further determined by dividing the value of the battery or super-capacitor measurement by the value of the bandgap/reference and by the known voltage.

<FIG> illustrates an example of a system <NUM> for measuring a voltage, in accordance with embodiments of the present disclosure. In one embodiment, system <NUM> may be configured to measure a battery or super-capacitor voltage. In another embodiment, system <NUM> may be configured to measure a voltage without quiescent current. In yet another embodiment, system <NUM> may be configured to adjust a battery or super-capacitor voltage measurement by performing another measurement of bandgap voltage. System <NUM> may be implemented in any suitable device that has a voltage or battery or super-capacitor voltage that is to be measured, such as a microcontroller, computer, mobile device, wearable, or integrated circuit.

System <NUM> is configured to measure a voltage such as vbat <NUM>. Vbat <NUM> may include the voltage of a battery, super-capacitor, or other power source of a device. Vbat <NUM> may include the voltage at the positive terminal of such a battery or super-capacitor or other power source. Vbat <NUM> may include the voltage of a back-up source of power for the device. Measuring vbat <NUM> directly might not provide entirely accurate readings due to parasitic influences from other portions of the device. Specifically, measuring vbat <NUM> might require use of a voltage divider and such a voltage divider may cause various side-effects.

Accordingly, system <NUM> measures vbat <NUM> in conjunction with other voltages of the device, such as a bandgap voltage from the device on which system <NUM> resides so that a measurement for vbat <NUM> can be adjusted for the parasitic influence. The bandgap voltage may represent a fixed value of the system and, as such, a code value of an analog to digital converter for the bandgap voltage can be used to adjust the measurement of vbat <NUM>. Instead of the bandgap voltage, another known reference voltage may be used. System <NUM> measures another voltage vdd3 <NUM>. Vdd3 <NUM> may include voltage from another power supply of the same device, such as a positive supply rail. Vdd3 <NUM> may represent positive supply voltage from a field-effect transistor (FET)-based power supply. Vdd3 <NUM> may be implemented by any known voltage. Vbat <NUM> may, directly or indirectly, provide power to vdd3 <NUM>. Each of vdd3 <NUM> and vbat <NUM> may be pins of the same integrated circuit device.

In a further embodiment, system <NUM> may include a switch <NUM> that may optionally switch between measurement of vdd3 <NUM> and vbat <NUM>. Switch <NUM> may be controlled by control and calculation circuitry (CCC) <NUM>. Switch <NUM> may be implemented in any suitable manner, such as by switching or routing circuitry. Switch <NUM> may control access to a sensor such a voltage sensor <NUM>, labeled "Vbatmon" in <FIG>. Sensor <NUM> may be implemented in any suitable manner. In one embodiment, sensor <NUM> may route a voltage sense node from one of vdd3 <NUM> or vbat <NUM> to an analog to digital converter (ADC) <NUM>. ADC <NUM> may be implemented in any suitable manner to generate a digital value from an analog value. ADC <NUM> may output its value to CCC <NUM>. Although a single instance of switch <NUM>, sensor <NUM>, and ADC <NUM>, system <NUM> may be implemented with any suitable number and combination of these elements. For example, a switch may be omitted while multiple sensors <NUM> are each respectively connected to vbat <NUM> and vdd3 <NUM>, and furthermore each respectively connected to ADCs <NUM>, which are each in turn connected to CCC <NUM>.

CCC <NUM> may be configured to control operation of system <NUM> to correctly calculate, measure, and monitor voltage such as those from vbat <NUM>. CCC <NUM> may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, digital logic, instructions of execution in a processor, or any suitable combination thereof.

Vbat <NUM> may include a smaller or larger voltage range than vdd3 <NUM>, and as such one of vbat <NUM> or vdd3 <NUM> may be adjusted according to the available range of ADC <NUM>. In one embodiment, vdd3 <NUM> may include voltages in the range of <NUM>. 71V to <NUM>. In another embodiment, vbat <NUM> may include voltages in the range of <NUM>. 0V to <NUM>. In such embodiments, as the full scale of ADC <NUM> is defined by vdd3 <NUM> (with the wider voltage than vbat <NUM>), then vbat <NUM> could have its scale increased with a higher, larger scale. In order to achieve a larger scale to match, for example, that of vdd3 <NUM> (or any other range causing ADC <NUM> to be implemented with a wider range), system <NUM> may include any suitable mechanism. For example, system <NUM> may include a resistive divider to cause the voltage of vbat <NUM> to be divided in half. The actual value of vbat <NUM> would be later compensated for such a correction by, for example, multiplying by two. Another example of such system could be to add an additional capacitor along with parasitic capacitor <NUM> on ADC <NUM> input so further attenuate the signal.

However, system <NUM> may be implemented in a device with tight power requirements. For example, system <NUM> may be implemented in a device that includes a sleep or hibernation mode in which the total budget is 800nA. A resistive divider, even though configured to duty-cycle and turn once in ten minutes, can consume <NUM>-50nA. Thus, the problems of the resistive divider may be addressed. Some solutions might use a larger resister in the resistive divider to address these problems. However, using a larger resister in the resistive divider to address these problems may further cause issues with a necessary larger area on die for the semiconductor device. Furthermore, longer time might be required to settle capacitors of ADC <NUM>. In addition, this may cause additional shoot-through current. Some solutions might use a PMOS as resistor to address these problems, as a PMOS requires less area on die than other resistors. However, using a PMOS as a resister might require a longer settling time. Furthermore, the diode and transistor current consumption may burn quiescent current at a rate of, for example, <NUM>-5uA at full-charge and -500nA at low-charge, or <NUM>-10uA at higher voltages (such as above <NUM>. The algorithm to measure the absolute vbat <NUM> in such cases may include first determining bandgap/reference voltage of a device upon which system <NUM> resides. The bandgap/reference voltage may be measured by ADC <NUM> while CCC <NUM> detaches Vbatmon <NUM> and the left-hand of the circuit. A code value produced by ADC <NUM> corresponding to the bandgap/reference voltage mat be designated as Cx. The actual voltage represented by Cx (or other code values produced by CCC <NUM>) may be determined through, for example, normalization according to the accuracy and range of ADC <NUM>. For example, with a given range of <NUM>,<NUM> values (when ADC <NUM> is a twelve-bit converter), the code output of ADC <NUM> for measuring the bandgap/reference voltage (saved as Cx) might correspond to <NUM> volts in an example circuit. In other circuits, the bandgap/reference voltage may be different. A battery or super-capacitor measurement of vbat <NUM> may be designated, in terms of a code output of ADC <NUM>, as Cy. Thus, in other systems such as those that use resistive dividers that fail to take into account the code values of vdd3 <NUM>, the actual (as opposed to measured) value of vbat <NUM> may be given as (VBAT = <NUM>*<NUM>/Cx*Cy).

According to various embodiments, instead of a resistive divider which has a shoot-through current, a charge-sharing from a capacitor is used to measure the battery or super-capacitor voltage. In one embodiment, system <NUM> may include a capacitor, such as Cbat <NUM> connected in series between switch <NUM> and ground. Such a Cbat <NUM> may be used to counteract a shoot-through current that may occur in system <NUM>. However, inclusion of Cbat <NUM> may require calculations to determine that absolute vbat <NUM>. Such calculations may be performed by CCC <NUM> to adjust measurements otherwise made by ADC <NUM>.

The adjustments needed to determine the absolute value of vbat <NUM> may arise from the fact that sensor <NUM> is placed at a shared channel of ADC <NUM> which includes a variable parasitic <NUM>. The value of the parasitic <NUM>, in terms of capacitance, is an attenuation factor that is dependent upon system parasitics and process variations, which may vary from device to device. Thus, in some embodiments, parasitic <NUM> cannot be determined in advance and accounted-for.

The attenuated voltage due to parasitic <NUM> may be given by CVBAT/(CVBAT+CPAR+CADC). However, as discussed above, the parasitic capacitance due to parasitic <NUM> might not be known. Thus, it is impossible to calculate the absolute value of vbat <NUM> with this formula.

When using two capacitors the following equations should be considered: <MAT> <MAT> <MAT>.

In the claimed invention, system <NUM> performs three voltage measurements, one of a bandgap/reference, a second to capacitor charged with vdd3 <NUM>, and a third of a capacitor charged with vbat <NUM>. The code value of the measured voltage of the capacitor charged with vdd3 <NUM> may be designated as Cz. System <NUM> thus solves problems associated with the impossibility of calculating the absolute value of vbat <NUM> as described above when using other methods. In another, further embodiment, system <NUM> may thus eliminate quiescent current. In yet another embodiment, system <NUM> may add a step to the battery or super-capacitor voltage measurement. The measurements and calculations may be directed by, for example, CCC <NUM>.

In one embodiment, the actual value of vbat <NUM> may be defined by <NUM> * (<NUM>N) *Cy / (Cz * Cx), where N is the resolution of ADC <NUM>.

In the claimed invention, the known bandgap/reference voltage of a system including ADC <NUM> is measured and its code value assigned to the value of Cx. Furthermore, the number of bits of ADC <NUM> may be defined by N and may be, for example, twelve, leading to the factor of <NUM>,<NUM>. The factor of <NUM> may arise from the known (as opposed to measured) bandgap/reference voltage value of, for example, <NUM>.

In another embodiment, the voltage of vbat <NUM> may be measured by or at sensor <NUM> when switch <NUM> is switched to vbat <NUM>. The code value of the measured voltage of vbat <NUM> is assigned to the value of Cy. The measurement of vbat <NUM> is made when Cbat <NUM> is charged with voltage from vbat <NUM>.

In yet another embodiment, the voltage of vdd3 <NUM> may be measured by or at sensor <NUM> when switch <NUM> is switched to vdd3 <NUM>. The code vale of the measured voltage of vdd3 <NUM> is assigned to the value of Cz. The measurement of vdd3 <NUM> is made when Cbat <NUM> is charged with voltage from vdd3 <NUM>. As discussed above, any known reference voltage may be used for vdd3 <NUM>.

The calculation of the actual voltage of the battery or super-capacitor, given by <NUM> * (<NUM>N) *Cy / (Cz * Cx), may be performed by, for example, CCC <NUM>. The calculation may be performed through any suitable adder, multiplier, or divisor circuits or instructions. The result of the calculation may be stored in memory, a register, or other suitable destination.

<FIG> is an illustration of an example of a circuit for providing a resistive divider to divide battery or super-capacitor voltage according to the range required by an ADC. The divider may be accomplished by a transistor network. However, as discussed above, this may cause a quiescent current of <NUM>-10uA at higher voltages (><NUM>. Thus, in embodiments of the claimed invention, the system <NUM> of <FIG> is used instead, wherein a capacitor is used between the battery or super-capacitor voltage and ground, and the voltage of the battery or super-capacitor is measured and adjusted.

<FIG> illustrates an example of a method <NUM> for measuring a voltage, in accordance with embodiments of the present disclosure.

At <NUM>, a battery or super-capacitor to be measured may be switched so as to be applied to a capacitor. At <NUM>, the capacitor may be charged by the battery or super-capacitor. At <NUM>, the voltage across the capacitor, representing the voltage of the battery or super-capacitor, is measured. This measurement, in terms of a code value, is defined as Cy.

At <NUM>, a known voltage may be switched to as to be applied to the capacitor. At <NUM>, the capacitor may be charged by the battery or super-capacitor. At <NUM>, the voltage across the capacitor representing the known voltage, is measured. This measurement, in terms of a code value, is defined as Cz.

At <NUM>, a bandgap/reference voltage is measured with respect to a system on which the ADC making the measurements resides. This measurement, in terms of a code value, is defined as Cx.

At <NUM>, the real, or actual, battery or super-capacitor voltage may be calculated and compensated for parasitic capacitance. The real battery or super-capacitor voltage may be defined as <NUM> * <NUM> * Cy / (Cx * Cz). The factor of <NUM> may be the known bandgap/reference voltage value. The factor of <NUM>,<NUM> may be derived from the size of an ADC performing the measurements of method <NUM>. Thus, these factors may vary for different hardware. Method <NUM> may be optionally repeated or may terminate.

Method <NUM> may be implemented by any suitable mechanism, such as by system <NUM> and the elements of <FIG>. In particular, method <NUM> may be operated by CCC <NUM>. Method <NUM> may optionally repeat or terminate at any suitable point. Moreover, although a certain number of steps are illustrated to implement method <NUM>, the steps of method <NUM> may be optionally repeated, performed in parallel or recursively with one another, omitted, or otherwise modified as needed, the resulting modified method not necessarily forming part of the claimed subject-matter.

Claim 1:
A capacitive voltage divider (CVD) method for measuring a voltage using a capacitor (<NUM>) and an analog-to-digital converter (ADC) (<NUM>) comprising a sample and hold capacitor, comprising the steps of:
measuring a bandgap or reference voltage by the ADC (<NUM>) and determining a first code value of the bandgap or reference voltage;
charging the capacitor (<NUM>) to a voltage to be measured and coupling the charged capacitor (<NUM>) in parallel with the sample and
hold capacitor of the ADC (<NUM>) to share a sampled charge to perform a first CVD measurement thereby determining a second code value; and
charging the capacitor (<NUM>) to a known second voltage and coupling the charged capacitor (<NUM>) in parallel with the sample and hold capacitor of the ADC (<NUM>) to share a sampled charge to perform a second CVD measurement thereby determining a third code value; characterized in
determining the voltage to be measured by calculating Vbg * <NUM>N * Cy / (Cz*Cx), wherein Vbg represents the bandgap or reference voltage, N represents the number of bits of the ADC (<NUM>), Cx represents the first code value, Cy represents the second code value, and Cz represents the third code value, and wherein the second voltage defines the full scale of the ADC (<NUM>).