Patent Description:
A semiconductor memory device may include memory cells arranged in rows and columns. When activating or accessing a specific row of the memory cells, a voltage change may occur at the memory cells in the specific row. The voltage change may cause stress to memory cells in a row adjacent to the specific row. This stress may cause data stored in the adjacent row to be lost or changed.

Document <CIT> discloses an apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The controller is configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller performs a second read operation using a second read reference voltage. The controller identifies a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller performs a third read operation on aggressor cells of the victim cell. The controller performs a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells.

From <CIT> it is known a memory area protected from row hammer attacks by placing an extra sacrificial row at the top and the bottom of the memory addresses defining the area to be protected. The sacrificial rows of memory are written with a known bit pattern that may be read periodically to detect any row hammer attacks that may be in progress.

Embodiments of the present disclosure provide a method and a semiconductor memory device capable of compensating for or suppressing a stress coming from concentrated activation of memory cells in a specific row.

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one of skill in the art may implement embodiments of the invention. The term "and/or" as used hereinafter is intended to include any one of items listed with regard to the term, or a combination of some of the listed items.

<FIG> illustrates a memory system <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, the memory system <NUM> may include a semiconductor memory device <NUM> and a memory controller <NUM>.

The semiconductor memory device <NUM> may include at least one of various memories such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), and a resistive RAM (RRAM).

The semiconductor memory device <NUM> may be implemented with a memory module including two or more memory packages. For example, the memory module may be implemented based on a dual in-line memory module (DIMM). As another example, the semiconductor memory device <NUM> may be implemented with an embedded memory that is directly mounted on a board of an electronic device.

The memory controller <NUM> may access the semiconductor memory device <NUM> depending on a request of an external host device (e.g., a central processing unit or an application processor). For example, the memory controller <NUM> may provide the semiconductor memory device <NUM> with a command CMD, an address ADDR, a first control signal CS1, and a clock signal CK. The memory controller <NUM> may receive a second control signal CS2 from the semiconductor memory device <NUM>.

The memory controller <NUM> may exchange a data signal DQ and a data strobe signal DQS with the semiconductor memory device <NUM>, based on the command CMD, the address ADDR, the first control signal CS1, the clock signal CK, and the second control signal CS2. The data strobe signal DQS may be a toggle signal indicating a timing to latch the data signal DQ.

<FIG> illustrates memory cell arrays 110a and 110b and a sense amplifier <NUM> according to an embodiment of the present disclosure. The memory cell arrays 110a and 110b may be included in the semiconductor memory device <NUM>. An example in which the memory cell arrays 110a and 110b are included in the semiconductor memory device <NUM> implemented with a DRAM is illustrated as an embodiment. However, the present disclosure is not limited to the example in which the memory cell arrays 110a and 110b are included in the semiconductor memory device <NUM> implemented with a DRAM.

Referring to <FIG>, the memory cell array 110a may include memory cells MCa arranged in rows and columns, and the memory cell array 110b may include memory cells MCb arranged in rows and columns. The rows of the memory cells MCa may be connected with word lines WL1a and WL2a. The rows of the memory cells MCb may be connected with word lines WL1b and WL2b. The columns of the memory cells MCa may be connected with bit lines BL1a, BL2a, and BL3a. The columns of the memory cells MCb may be connected with bit lines BL1b, BL2b, and BL3b. In an embodiment, a row may be understood as having the same meaning as a word line or a meaning similar thereto. While <NUM> word lines, <NUM> bit lines, and <NUM> memory cells are illustrated in <FIG>, the number of word lines, the number of bit lines, and the number of memory cells are not limited thereto.

The memory cell arrays 110a and 110b may be implemented with a pair. The word lines WL1a and WL2a may be paired with the word lines WL1b and WL2b, respectively. For example, when the word line WL1a is activated, the paired word line WL1b may also be activated together. Likewise, the bit lines BL1a, BL2a, and BL3a may be paired with the bit lines BL1b, BL2b, and BL3b respectively. Paired bit lines may be driven in association with each other.

In another example, the memory cell arrays 110a and 110B are not paired. Hereinafter, based on the context, the terms "word line" and "bit line" may refer to a pair of lines implemented as a pair or one line not implemented as a pair. Also, depending on the context, the terms "row" and "column" may refer to a pair of rows implemented as a pair, a pair of columns implemented as a pair, a row not implemented as a pair, and a column not implemented as a pair. Likewise, depending on the context, the term "memory cell" may refer to a pair of memory cells or one memory cell not implemented as a pair.

The memory cell MCa connected with a specific word line WL2a and a specific bit line BL1a of the memory cell array 110a may store a data bit complementary to that of the memory cell MCb connected with a specific word line WL2b and a specific bit line BL1b of the memory cell array 110a. That is, one data bit may be complementarily stored in a pair of memory cells MCa and MCb.

Each of the memory cells MCa and MCb may include a selection element SE and a capacitance element CE. The selection element SE may operate in response to a voltage of a corresponding word line of the word lines WL1a, WL1b, WL2a, and WL2b. When the corresponding word line (or a voltage of the word line) is activated, the selection element SE may be turned on to electrically connect the capacitance element CE with a corresponding bit line of the bit lines BL1a, BL1b, BL2a, and BL2b. When the corresponding word line (or a voltage of the word line) is deactivated, the selection element SE may be turned off to electrically disconnect the capacitance element CE from the corresponding bit line.

The capacitance element CE may be connected between the selection element SE and a common node to which a common voltage VC is applied. The capacitance element CE may be implemented with a capacitor. The capacitance element CE may store a data bit by storing a voltage transferred from the corresponding bit line through the selection element SE. In an embodiment, the common voltage VC may be a power supply voltage, a ground voltage, or a voltage having a level between the power supply voltage and the ground voltage (e.g., a level corresponding to half the level of the power supply voltage).

When a specific word line (e.g., WL2a and WL2b) is activated, data bits stored in the memory cells MCa and MCb connected with the specific word lines WL2a and WL2b may be read. In this case, a voltage change may occur at the capacitance elements CE of the memory cells MCa and MCb of the activated word lines WL2a and WL2b.

When the activated word lines WL2a and WL2b are deactivated, the data bits may be written in the memory cells MCa and MCb connected with the specific word lines WL2a and WL2b. In this case, a voltage change may occur at the capacitance elements CE of the memory cells MCa and MCb of the activated word lines WL2a and WL2b.

The voltage change occurring at the capacitance elements CE of the memory cells MCa and MCb of the activated word lines WL2a and WL2b may cause a voltage change at the capacitance elements CE of the memory cells MCa and MCb of adjacent neighbor word lines (e.g., WL1a and/or WL1b) due to coupling. The voltage change due to the coupling may act as a stress on the memory cells MCa and MCb of an adjacent row (e.g., WL1a and/or WL1b, or third word lines (not illustrated) adjacent to WL2a and WL2b), and thus may cause an error in data bits. For example, a third row of memory cells MCa connected to a third word line may be located in 110a below the second row of memory cells MCa connected to word line WL2a, and a third row memory cells MCb connected to a third word line may be located in 110b below the second row of memory cells MCb connected to word line WL2b.

When a frequent or concentrated activation is made with respect to the specific word lines WL2a and WL2b, a stress applied to adjacent neighbor word lines (e.g., WL1a and/or WL1b, or the third word lines (not illustrated)) may increase, and thus, the probability that an error occurs may increase.

In an embodiment, a row that causes a stress or an error factor may be referred to as an "aggressor row". In an embodiment, a row that is affected by a stress or an error factor may be referred to as a "victim row".

<FIG> illustrates an example in which the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) operates for the purpose of preventing an error in data bits. Referring to <FIG>, <FIG>, and <FIG>, in a first state S1, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may operate in a normal mode. In the normal mode, the memory controller <NUM> may transmit a refresh command to the semiconductor memory device <NUM> periodically.

The semiconductor memory device <NUM> may perform a refresh operation in response to the refresh command. In the refresh operation, data bits may be read from memory cells in a specific row, and the read data bits may be again written therein. As such, the stress (or error factor) accumulated in the memory cells in the specific row may be removed.

In an embodiment, after charges corresponding to a data bit are stored in the capacitance element CE, over time, charges may be leaked out from the capacitance element CE or may be introduced into the capacitance element CE. The charge leakage or introduction may act as a stress on a data bit stored in the capacitance element CE and may be accumulated as an error factor. As charges are again charged (or discharged) to or from the capacitance element CE through the refresh operation, the accumulated stress or error factor may be removed.

In an embodiment, when the memory controller <NUM> does not access the semiconductor memory device <NUM> in the normal mode, the memory controller <NUM> may transmit a self-refresh command to the semiconductor memory device <NUM>. In response to the self-refresh command, the semiconductor memory device <NUM> may periodically perform the refresh operation without receiving the refresh command from the memory controller <NUM>.

In response to that the concentrated activation CA occurs at a specific row, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may enter a second state S2. In the second state S2, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may perform policy-based determination. A policy may be determined during initialization of the memory system <NUM> by an external host device or the memory controller <NUM>.

In the case where the policy of the concentrated activation CA is set to a first policy P1, in response to that the concentrated activation CA occurs at a specific row, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may enter a third state S3. In the third state S3, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may perform the refresh operation with respect to a victim row.

For example, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may remove the stress or error factor accumulated by the concentrated activation CA by performing the refresh operation with respect to the victim row. When the refresh operation is completed (CPT), the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may return to the first state S1.

In the case where the policy of the concentrated activation CA is set to a second policy P2, in response to that the concentrated activation CA occurs at a specific row, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may enter a fourth state S4. In the fourth state S4, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may perform a flip operation with respect to an aggressor row.

For example, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may compensate for or suppress the stress or error factor coming from the concentrated activation CA by flipping data bits of memory cells in an aggressor row where the concentrated activation CA occurs.

For example, when data bit "<NUM>" is stored in a specific memory cell in an aggressor row where the cells concentrated activation CA occurs, memory cells in an adjacent neighbor row may be affected by the following stress or error factor: a voltage of the capacitance element CE increases to the power supply voltage. For example, in the case where data bit "<NUM>" stored in a specific memory cell in an aggressor row where the cells concentrated activation CA occurs is inverted into data bit "<NUM>", memory cells in an adjacent neighbor row may be affected by the following stress or error factor: a voltage of the capacitance element CE decreases to the ground voltage.

As a data bit of a specific memory cell in an aggressor row where the concentrated activation CA occurs is flipped, the stress or error factor before the flip operation and the stress or error factor after the flip operation may be canceled out. That is, the stress or error factor due to the concentrated activation CA may be compensated for or suppressed.

The policy of the concentrated activation CA may be set to both the first policy P1 and the second policy P2. In this case, the memory system <NUM> (e.g., the semiconductor memory device <NUM> or the memory controller <NUM>) may perform both the flip operation associated with an aggressor row where the concentrated activation CA occurs and the refresh operation associated with a victim row.

<FIG> illustrates the semiconductor memory device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the semiconductor memory device <NUM> may include first to fourth bank groups BG1 to BG4. The first to fourth bank groups BG1 to BG4 may have the same structures and may operate in the same manner.

Each of the first to fourth bank groups BG1 to BG4 may include first to fourth banks B1 to B4. The first to fourth banks B1 to B4 may have the same structures and may operate in the same manner.

Each of the first to fourth banks B1 to B4 may include the memory cell array <NUM> and the sense amplifier <NUM>. The memory cell array <NUM> may include the memory cell arrays 110a and 110b described with reference to <FIG>. The sense amplifier <NUM> may be connected with columns of memory cells of the memory cell array <NUM> through bit lines BL.

The semiconductor memory device <NUM> may further include an address register <NUM>, a row decoder <NUM> (e.g., a decoder circuit), a column decoder <NUM> (e.g., decoder circuit), first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM>, a global gating circuit <NUM>, a buffer circuit <NUM>, and control logic <NUM> (e.g., a logic circuit).

The address register <NUM> may receive the address ADDR from the memory controller <NUM> through first pads PAD1. The address ADDR may include a bank group address, a bank address, a row address, and a column address. The address register <NUM> may transfer the bank group address, the bank address, and the row address to the row decoder <NUM>. The address register <NUM> may transfer the bank group address, the bank address, and the column address to the column decoder <NUM>.

The address register <NUM> may include a counter (CNT) <NUM>. The counter <NUM> may count up (e.g., increment) or down (e.g., decrement) the row address or the column address and may internally generate row addresses or column addresses increasing or decreasing sequentially.

The row decoder <NUM> may receive the bank group address, the bank address, and the row address from the address register <NUM>. The row decoder <NUM> may select one of the first to fourth bank groups BG1 to BG4, based on the bank group address. The row decoder <NUM> may select one of the first to fourth banks B1 to B4 in the selected bank group, based on the bank address. The row decoder <NUM> may select one word line (or a pair of word lines) of word lines of the selected bank in the selected bank group, for example, one row (or a pair of rows) of rows of memory cells, based on the row address.

The row decoder <NUM> may activate the selected row by applying a voltage for turning on the selection element SE to the selected row of the selected bank in the selected bank group. After the selected word line is activated, an access to data bits of the memory cells in the selected row may be permitted.

The row decoder <NUM> may deactivate the selected row by applying a voltage for turning off the selection element SE to the selected row of the selected bank in the selected bank group. After the selected row is deactivated, the activation of any other row may be permitted.

The column decoder <NUM> may receive the bank group address, the bank address, and the column address from the address register <NUM>. The column decoder <NUM> may generate first selection signals SEL1, based on the bank group address. The column decoder <NUM> may provide the first selection signals SEL1 to the global gating circuit <NUM>.

The column decoder <NUM> may generate second selection signals SEL2, based on the bank address and the column address. The column decoder <NUM> may provide the second selection signals SEL2 to the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM>.

The first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM> may correspond to the first to fourth bank groups BG1, BG2, BG3, and BG4, respectively. The first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM> may be connected with the first to fourth bank groups BG1, BG2, BG3, and BG4 through first input and output lines IO1.

The first input and output lines IO1 may include first to fourth bank group lines connected with the first to fourth bank groups BG1, BG2, BG3, and BG4. For example, the first bank group lines may include first to fourth bank lines connected with the first to fourth banks B1, B2, B3, and B4, and the second bank group lines may include first to fourth bank lines connected with the first to fourth banks B1, B2, B3, and B4. Likewise, the third bank group lines may include first to fourth bank lines connected with the first to fourth banks B1, B2, B3, and B4, and the fourth bank group lines may include first to fourth bank lines connected with the first to fourth banks B1, B2, B3, and B4. The first to fourth bank group lines of the first input and output lines IO1 are illustrated in <FIG> as an example.

Each of the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM> may select one of banks belonging to the corresponding one of the first to fourth bank groups BG1, BG2, BG3, and BG4. For example, the first local gating circuit <NUM> may be connected with the first to fourth banks of the first bank group BG1 through the first to fourth bank lines of the first bank group lines included in the first input and output lines IO1.

The first local gating circuit <NUM> may select ones of the first to fourth bank lines (e.g., may select one bank) in response to corresponding selection signals of the second selection signals SEL2. The first local gating circuit <NUM> may electrically connect the selected bank lines (or bank) with corresponding lines of second input and output lines IO2 (e.g., with global lines to be described later).

Likewise, in the second to fourth bank groups BG2, BG3, and BG4, like the first local gating circuit <NUM>, each of the second to fourth local gating circuits <NUM>, <NUM>, and <NUM> may select one bank and may electrically connect the selected bank with corresponding lines of the second input and output lines IO2 (e.g., with global lines to be described later).

The global gating circuit <NUM> may be connected with the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM> through the second input and output lines IO2. The second input and output lines IO2 may include first to fourth global lines connected with the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM>. The first to fourth global lines of the second input and output lines IO2 are illustrated in <FIG> as an example.

The global gating circuit <NUM> may select ones of the first to fourth bank lines (e.g., may select one bank group) in response to the first selection signals SEL1. The global gating circuit <NUM> may electrically connect the selected global lines (or a selected bank of a selected bank group) with third input and output lines IO3.

The buffer circuit <NUM> may be electrically connected with the third input and output lines IO3. The buffer circuit <NUM> may be connected with the memory controller <NUM> through second pads PAD2. The buffer circuit <NUM> may exchange the data signal DQ and the data strobe signal DQS with the memory controller <NUM> through the second pads PAD2.

The buffer circuit <NUM> may transmit the data signal DQ (i.e., data bits), which is received from the memory controller <NUM> through the second pads PAD2 in synchronization with the data strobe signal DQS, to the sense amplifier <NUM> of the selected bank in the selected bank group through the global gating circuit <NUM> and the selected local gating circuit of the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM>.

The buffer circuit <NUM> may output data bits, which are transferred from the sense amplifier <NUM> of the selected bank in the selected bank group through the selected local gating circuit of the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM> and the global gating circuit <NUM>, to the memory controller <NUM> through the second pads PAD2.

The buffer circuit <NUM> may include a flip circuit (FC) <NUM>. The flip circuit <NUM> may receive a flip signal FS from the control logic <NUM>. In response to the flip signal FS, the flip circuit <NUM> may selectively flip the data bits transferred through the buffer circuit <NUM>. For example, in response to that the flip signal FS has a first value, the flip circuit <NUM> does not flip the data bits transferred through the buffer circuit <NUM>. In response to that the flip signal FS has a second value, the flip circuit <NUM> inverts the data bits transferred through the buffer circuit <NUM>. For example, data bits to be written to the memory cell array <NUM> when the flip signal FS has the second value are inverted to generate inverted data, and the inverted data is then written to the memory cell array <NUM>.

The control logic <NUM> may receive the command CMD, the first control signal CS1, and the clock signal CK from the memory controller <NUM> through third pads PAD3. The control logic <NUM> may receive the address ADDR from the memory controller <NUM> through the first pads PAD1. The control logic <NUM> may receive the second control signal CS2 from the memory controller <NUM> through fourth pads PAD4.

As a portion of an algorithm for preventing an error of data bits stored in the memory cells MCa and MCb, the control logic <NUM> may enter the first state S1. In the first state S1, in response to that a refresh command is received as the command CMD, the control logic <NUM> may allow the counter <NUM> to generate a row address internally. Under control of the control logic <NUM>, the semiconductor memory device <NUM> may perform the refresh operation based on a row address generated by the counter <NUM>.

The control logic <NUM> may monitor the command CMD and the address ADDR. By monitoring the command CMD and the address ADDR, the control logic <NUM> may determine (or detect) whether a concentrated activation CA occurs at a specific row. For example, in response to that an active command and a row address are received, the control logic <NUM> may store the row address. The control logic <NUM> may detect the concentrated activation CA by counting the number of times that the active command is received with regard to a specific row address. For example, if the active command for a specific row is received a number of times that exceeds a threshold number, then it may be determined that the concentrated activation CA has occurred.

As another example, the control logic <NUM> may count the number of times that a specific row is activated, by counting the number of times that the active command is received with regard to a specific row address, during a given time window (e.g., a time period). The control logic <NUM> may detect the concentrated activation CA by counting the number of times that a specific row is activated. For example, if the specific row is activated a number of times during the given time window that exceeds a threshold number, then it may be determined that the concentrated activation CA has occurred.

In response to that the concentrated activation CA occurs at a specific row, the control logic <NUM> may enter the second state S2. In the second state S2, the control logic <NUM> may determine one of the first policy P1 or the second policy P2.

When the first policy P1 is applied to the semiconductor memory device <NUM>, under control of the control logic <NUM>, the semiconductor memory device <NUM> may perform the refresh operation with respect to neighbor rows adjacent to an aggressor row, that is, victim rows. When the second policy P2 is applied to the semiconductor memory device <NUM>, under control of the control logic <NUM>, the semiconductor memory device <NUM> may flip data bits of memory cells in the aggressor row.

For example, the control logic <NUM> may set the flip signal FS to a second level. The control logic <NUM> may allow the counter <NUM> to generate column addresses increasing sequentially. The flip circuit <NUM> of the buffer circuit <NUM> may receive data bits of memory cells connected with the activated row of the selected bank in the selected bank group, based on the column addresses generated by the counter <NUM>. The flip circuit <NUM> may flip the received data bits, and the flipped data bits may be written, for example, overwritten on the data bits of the memory cells connected with the activated row of the selected bank in the selected bank group.

<FIG> illustrates an example of the sense amplifiers <NUM> and the local gating circuit <NUM> corresponding to one bank group (e.g., BG1) of the semiconductor memory device <NUM> of <FIG>. Referring to <FIG> and <FIG>, each of the sense amplifiers <NUM> may include a plurality of bit line sense amplifiers SA. Each of the plurality of bit line sense amplifiers SA may be connected with a corresponding bit line pair of bit line pairs BLa and BLb.

Voltages of a pair of bit lines may be controlled complementarily (e.g., during a given time period, one voltage level may be a high level, and the other voltage level may be a low level). As each of the plurality of bit line sense amplifiers SA amplifies a difference of voltages of a corresponding pair of bit lines, the plurality of bit line sense amplifiers SA may sense data bits stored in memory cells of an activated row.

Each bit line sense amplifier SA may amplify a difference of a pair of bit lines so as to be output to a corresponding pair of input and output lines of the first input and output lines IO1 (herein and below, used as a meaning of lines corresponding to the first bank group BG1 from among the first input and output lines IO1). Voltages of a pair of input and output lines may be controlled complementarily (e.g., during a given time period, one voltage level may be a high level, and the other voltage level may be a low level).

An example in which one bank includes <NUM> bit line sense amplifiers SA is illustrated in <FIG>. However, the number of bit line sense amplifiers SA included in one bank is not limited.

The local gating circuit <NUM> may include column selection transistors CST, internal input and output lines IIO, and a switch circuit SC. The column selection transistors CST may be connected between the first input and output lines IO1 and the internal input and output lines IIO. The column selection transistors CST may select bank lines to be electrically connected with the internal input and output lines IIO, from among the first to fourth bank lines corresponding to the first to fourth banks B1 to B4 of the first bank group BG1.

For example, the column selection transistors CST connected with a first column selection line CSL1 may be activated (e.g., turned on) in response to that an active voltage is applied to the first column selection line CSL1. In this case, bank lines associated with the first column selection line CSL1 from among the first bank lines belonging to the first bank group lines of the first input and output lines IO1 may be electrically connected with the internal input and output lines IIO.

Likewise, in response to that the first column selection line CSL1 is activated, bank lines associated with the first column selection line CSL1 from among the second to fourth bank lines belonging to the first bank group lines may be electrically connected with the internal input and output lines IIO.

The column selection transistors CST connected with a second column selection line CSL2 may be activated (e.g., turned on) in response to that the active voltage is applied to the second column selection line CSL2. In this case, bank lines associated with the second column selection line CSL2 from among the first bank lines belonging to the first bank group lines of the first input and output lines IO1 may be electrically connected with the internal input and output lines IIO.

Likewise, in response to that the second column selection line CSL2 is activated, bank lines associated with the second column selection line CSL2 from among the second to fourth bank lines belonging to the first bank group lines may be electrically connected with the internal input and output lines IIO. That is, internal input and output line pairs, the number of which corresponds to the number of column selection lines CSL1 and CSL2, may be connected with the local gating circuit <NUM>.

An example in which two column selection lines CSL1 and CSL2 are provided for each bank is illustrated in <FIG>. However, the number of column selection lines provided for each bank is not limited. Also, an example in which the first column selection line CSL1 and the second column selection line CSL2 are provided in common to banks belonging to one bank group is illustrated in <FIG>. However, column selection lines may be independently provided for each of banks belonging to the same bank group. In contrast, the first column selection line CSL1 and the second column selection line CSL2 may be provided in common to the banks B1, B2, B3, and B4 of the four bank groups BG1, BG2, BG3, and BG4.

The switch circuit SC may operate in response to a bank selection signal BS. In response to the bank selection signal BS, the switch circuit SC may select pairs of lines corresponding to one bank from among the pairs of internal input and output lines IIO. The switch circuit SC may electrically connect the selected pairs of lines with pairs of second input and output lines IO2 (herein and below, used as a meaning of lines corresponding to the first bank group BG1 from among the second input and output lines IO2).

Voltages of a pair of input and output lines of the pairs of second input and output lines IO2 may be controlled complementarily (e.g., during a given time period, one voltage level may be a high level, and the other voltage level may be a low level). Two pairs of second input and output lines IO2 are illustrated in <FIG> as an example, but the number of pairs of second input and output lines IO2 is not limited. The number of pairs of second input and output lines IO2 may correspond to the number of column selection lines CSL1 and CSL2.

In an embodiment, the switch circuit SC may function as a multiplexer electrically connecting the internal input and output lines IIO with the second input and output lines IO2 or a demultiplexer electrically connecting the second input and output lines IO2 with the internal input and output lines IIO.

In an embodiment, the switch circuit SC may operate as a sense amplifier. For example, the switch circuit SC may sense and amplify signals of lines corresponding to the selected bank from among the internal input and output lines IIO so as to be transferred to the second input and output lines IO2. The switch circuit SC may sense and amplify signals of the second input and output lines IO2 so as to be transferred to the lines corresponding to the selected bank from among the internal input and output lines IIO. The switch circuit SC may be also referred to as a "local sense amplifier".

In an embodiment, the first column selection line CSL1, the second column selection line CSL2, and the bank selection signal BS may be included in the second selection signals SEL2.

In the semiconductor memory device <NUM> of <FIG>, the global gating circuit <NUM> may be implemented to be similar to the switch circuit SC. In response to the first selection signals SEL1, the global gating circuit <NUM> may electrically connect pairs of lines corresponding to one bank group from among the pairs of second input and output lines IO2 with pairs of third input and output lines IO3. The global gating circuit <NUM> may function as a multiplexer or a demultiplexer. Thus, additional description associated with the global gating circuit <NUM> will be omitted to avoid redundancy.

Voltages of a pair of input and output lines of the pairs of third input and output lines IO3 may be controlled complementarily (e.g., during a given time period, one voltage level may be a high level, and the other voltage level may be a low level). In an embodiment, the number of pairs of third input and output lines IO3 is not limited. The number of pairs of third input and output lines IO3 may correspond to the number of column selection lines CSL1 and CSL2 or the number of second pads PAD2 for transferring the data signals DQ.

<FIG> illustrates an example of the buffer circuit <NUM> of the semiconductor memory device <NUM> of <FIG>. Referring to <FIG> and <FIG>, the buffer circuit <NUM> may include first to fourth buffers <NUM>, <NUM>, <NUM>, and <NUM>. An example in which the buffer circuit <NUM> includes <NUM> buffers <NUM>, <NUM>, <NUM>, and <NUM> is illustrated in <FIG>, but the number of buffers included in the buffer circuit <NUM> is not limited. For example, the number of buffers <NUM>, <NUM>, <NUM>, and <NUM> may correspond to the number of column selection lines CSL1 and CSL2 (refer to <FIG>) or the number of second pads PAD2 for transferring the data signals DQ. In an embodiment, components of the buffer circuit <NUM>, which are associated with the data strobe signal DQS, are omitted in <FIG>.

Each of the first to fourth buffers <NUM>, <NUM>, <NUM>, and <NUM> may include an input and output sense amplifier IOSA, a write driver WD, a first flip circuit FC1, and a second flip circuit FC2. The first flip circuit FC1 and the second flip circuit FC2 may be included in the flip circuit (FC) <NUM> of <FIG>.

The input and output sense amplifier IOSA may be connected with a corresponding pair of lines of the pairs of third input and output lines IO3. The input and output sense amplifier IOSA may amplify a voltage difference of the corresponding pair of lines to generate an amplification result and may output a data bit having one of a first bit value and a second bit value based on the amplification result.

The first flip circuit FC1 may receive an output bit signal of the input and output sense amplifier IOSA and an inverted bit signal of the output bit signal. The first flip circuit FC1 may output the output bit signal of the input and output sense amplifier IOSA and the inverted bit signal in response to a first flip signal FS1. An output of the first flip circuit FC1 may be transferred to a corresponding pad of the second pads PAD2. The first flip signal FS1 may be included in the flip signal FS of <FIG>.

The second flip circuit FC2 may receive a bit signal transferred through the corresponding pad of the second pads PAD2 and an inverted bit signal of the received bit signal. The second flip circuit FC2 may output the bit signal received through the corresponding pad of the second pads PAD2 and the inverted bit signal in response to a second flip signal FS2. An output of the second flip circuit FC2 may be transferred to the write driver WD. The second flip signal FS2 may be included in the flip signal FS of <FIG>.

The write driver WD may receive the output of the second flip circuit FC2. The write driver WD may output signals (e.g., complementary signals) that correspond to the receive signal, for example, signals having a bit value of the received bit signal and an inverted bit value of the received bit signal. A pair of output lines of the write driver WD may be connected with a corresponding pair of lines of the pairs of third input and output lines IO3.

In a read operation, the input and output sense amplifier IOSA may receive signals (e.g., complementary bit signals) corresponding to a data bit stored in the corresponding bit line sense amplifier SA and may sense and amplify the received signals so as to be output as an output bit signal. The first flip circuit FC1 may output the output bit signal or the inverted bit signal to the corresponding pad of the second pads PAD2 in response to the first flip signal FS1. For example, in response to the first flip signal FS1, the first flip circuit FC1 may selectively invert the data bit stored in the bit line sense amplifier SA so as to be output to the corresponding pad of the second pads PAD2. For example, the first flip circuit FC1 may include an inverter to invert the data bit.

In a write operation, the second flip circuit FC2 may receive a bit signal transferred through the corresponding pad of the second pads PAD2 and an inverted bit signal of the received bit signal. The second flip circuit FC2 may output the output bit signal or the inverted bit signal to the write driver WD in response to the second flip circuit FC2. For example, in response to the second flip signal FS2, the second flip circuit FC2 may selectively invert the received bit signal so as to be output to the write driver WD. For example, the second flip circuit FC2 may include an inverter to invert the bit signal.

In the flip operation, the first flip signal FS1 and the second flip signal FS2 may have different levels. That is, one of the first flip circuit FC1 and the second flip circuit FC2 may output a signal of a positive input, and the other thereof may output a signal of a negative input. That is, a data bit stored in the bit line sense amplifier SA may be inverted by one of the first flip circuit FC1 and the second flip circuit FC2. The write driver WD may write (e.g., overwrite) the inverted data bit in the bit line sense amplifier SA.

<FIG> illustrates an example of an operating method of the semiconductor memory device <NUM> of <FIG> according to an embodiment of the disclosure. In an embodiment, an example of a method for flipping data bits of an aggressor row based on the second policy P2 is illustrated in <FIG>. Referring to <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S110, the control logic <NUM> receives an active command as the command CMD. Also, the control logic <NUM> and the address register <NUM> may receive a bank group address, a bank address, and a row address as the address ADDR.

In response to the active command, in operation S120, the row decoder <NUM> selects a row of the memory cell array <NUM> such that a word line of the selected row is activated. The row decoder <NUM> may select a bank group based on the bank group address, may select one of banks of the selected bank group based on the bank address, and may select one of rows of the selected bank such that a word line of the selected row is activated. For example, the row decoder <NUM> may apply a voltage for turning on the selection element SE to the selected word line. The sense amplifier <NUM> of the selected bank in the selected bank group may sense and store (or latch) data bits stored in memory cells of the selected row.

The column decoder <NUM> may generate the first selection signals SEL1 based on the bank group address and may generate some (e.g., the bank selection signal BS) of the second selection signals SEL2 based on the bank address. Based on some of the first selection signals SEL1 and the second selection signals SEL2, pairs of internal input and output lines IIO corresponding to the selected bank of the selected bank group may be electrically connected with the pairs of third input and output lines IO3.

After the data bits of the memory cell of the selected rows are stored in the sense amplifier <NUM>, access (e.g., write or read access) to the data bits stored in the sense amplifier <NUM> may be permitted. The activation of the selected row may be completed within a time defined by the standard of the semiconductor memory device <NUM>.

In operation S130, the control logic <NUM> determines whether the activation associated with the selected row is concentrated. For example, the control logic <NUM> may determine whether the concentrated activation occurs at the selected row. When the concentrated activation does not occur at the selected row, the semiconductor memory device <NUM> may terminate the procedure without performing the process of compensating for or suppressing the stress or error due to the concentrated activation. Afterwards, the semiconductor memory device <NUM> may wait for the command CMD and the address ADDR of the memory controller <NUM>. For example, the error may be a change to data stored in a row adjacent to the selected row where the concentrated activation occurs.

When the concentrated activation occurs at the selected row, the semiconductor memory device <NUM> performs the process of compensating for or suppressing the stress or error due to the concentrated activation. For example, the semiconductor memory device <NUM> may perform operation S140, operation S150, and operation S160.

In operation S140, the semiconductor memory device <NUM> activates a column selection line (e.g., CSL) under control of the control logic <NUM>. For example, the counter <NUM> may generate a column address. The column decoder <NUM> may activate a column selection line corresponding to the column address generated by the counter <NUM> from among column selection lines.

In response to determining that the column selection line is activated, some of bit lines of the selected bank in the selected bank group, that is, some of columns of memory cells may be electrically connected with the buffer circuit <NUM>.

In operation S150, data associated with the selected word line and the activated column selection line are flipped. The input and output sense amplifier IOSA of the buffer circuit <NUM> may determine a data bit stored in the corresponding bit line sense amplifier SA. The control logic <NUM> may flip the data bit by using one of the first flip circuit FC1 and the second flip circuit FC2 of the buffer circuit <NUM>. The write driver WD may write (e.g., overwrite) the flipped data bit in the corresponding bit line sense amplifier SA.

In operation S160, the control logic <NUM> determines whether the activated column selection line is the last column selection line. For example, the control logic <NUM> may determine whether all the column selection lines of the activated row are selected, that is, whether data bits of all memory cells are flipped. When the activated column selection line is not the last column selection line, the counter <NUM> may count up (or increment) the current column address to generate a next column address. In operation S140 to operation S160, the semiconductor memory device <NUM> may flip (or invert) data bits of memory cells associated with the next column selection line.

When the activated column selection line is the last column selection line, the control logic <NUM> may store a row address of a row where the flip operation is performed, that is, the activated row. When the flip operation is once performed with respect to a specific row, the control logic <NUM> may store a row address of the specific row. When the flip operation is again once performed with respect to the specific row, the control logic <NUM> may clear or delete the row address. Depending on whether a row address is stored, the control logic <NUM> may selectively activate the first flip signal FS1 and/or the second flip signal FS2 in the write operation or the read operation.

As another example, when the activated column selection line is the last column selection line, the control logic <NUM> may store a flag bit (e.g., flip or inversion information) in storage (e.g., a memory cell or a register) having a correlation with the activated row. When the flip operation is once performed with respect to a specific row, the control logic <NUM> may store the flag bit of a first value. When the flip operation is again once performed with respect to the specific row, the control logic <NUM> may store the flag bit of a second value. The first value is different from the second value. Depending on whether the flag bit indicates one of the first value and the second value, the control logic <NUM> may selectively activate the first flip signal FS1 and/or the second flip signal FS2 in the write operation or the read operation.

In an embodiment, the control logic <NUM> may store the flag bit in an internal register or storage. For example, a flag bit for each of the rows that is either set to the first value or cleared to the second value may be stored in the internal register. As another example, the control logic <NUM> may store the flag bit in some of the memory cells of the memory cell array <NUM>. For example, the control logic <NUM> may store the flag bit of a corresponding row in at least one of memory cells belonging to each row.

As another example, the row decoder <NUM> may include storage elements, which respectively correspond to the word lines WL, such as registers or latches. The row decoder <NUM> may store the flag bit in a storage element corresponding to each row.

After processing information indicating that the flip operation is performed, the semiconductor memory device <NUM> may terminate the process of compensating for or suppressing the stress or error due to the concentrated activation.

In an embodiment, operation S140 to operation S160 may be performed immediately after a selected row is activated. As another example, operation S140 to operation S160 may be performed when a selected row is deactivated. For example, in response to determining that a command (e.g., a precharge command) for deactivating the activated row is received from the memory controller <NUM>, the semiconductor memory device <NUM> may perform operation S140 to operation S160 and may deactivate the activated row.

<FIG> illustrates an example of a process in which the control logic <NUM> determines whether the concentrated activation occurs at an activated row. Referring to <FIG>, <FIG>, and <FIG>, in operation S210, the control logic <NUM> detects activation of a specific row. For example, in response to determining that the active command is received as the command CMD and a bank group address, a bank address, and a row address are received as the address ADDR, the control logic <NUM> may detect activation of a row corresponding to the bank group address, the bank address, and the row address.

In operation S220, the control logic <NUM> increases a count and/or a frequency of the activation. For example, when the number of rows adjacent to an activated row is "<NUM>", the control logic <NUM> may manage one count and/or one frequency, with regard to the activated row. When the number of rows adjacent to an activated row is "<NUM>", the control logic <NUM> may manage two counts and/or two frequencies corresponding to two neighbor rows, with regard to the activated row. A counter for calculating a count and/or a frequency may be included in the control logic <NUM>.

For example, the count may indicate the number of times that a currently selected row is activated and then deactivated after the refresh operation is performed with respect to a neighbor row or the neighbor row is activated and then deactivated. For example, the count may indicate the number of times that the active command is received as the command CMD and an address of a currently activated row is received as the address ADDR, after the refresh operation is performed with respect to a neighbor row or the neighbor row is activated and then deactivated.

The frequency may indicate the number of times that a currently selected row is activated and then deactivated during a given time window after the refresh operation is performed with respect to a neighbor row or the neighbor row is activated and then deactivated. For example, the frequency may correspond to the count that increases during the given time window. The given time window may correspond to a period from a past point in time preceding a point in time (e.g., a current point in time), at which a currently selected row is activated, as much as a given time period, to a current point in time.

In operation S230, the control logic <NUM> determines whether the count and/or the frequency reaches a first threshold value VTH1. When the count and/or the frequency does not reach the first threshold value VTH1, the control logic <NUM> determines that the concentrated activation does not occur at the activated row. Afterwards, the control logic <NUM> may terminate the algorithm for determining the concentrated activation in association with the flip operation.

When it is determined in operation S230 that the count and/or the frequency reaches the first threshold value VTH1, in operation S240, the control logic <NUM> determines that the concentrated activation occurs at the activated row. After determining that the concentrated activation occurs at the activated row, the control logic <NUM> may initialize the count and/or the frequency.

In an embodiment, in response to determining that the refresh operation or activation is performed with respect to a specific row, the control logic <NUM> may initialize a count and/or a frequency of a neighbor row adjacent to the specific row.

As described above, in the fourth state S4 according to the first policy P2 of <FIG>, the control logic <NUM> may determine the occurrence of concentrated activation by comparing a count and/or a frequency of the activation associated with the activated row with the first threshold value VTH1 and may selectively flip data bits of memory cells in an aggressor row based on a determination result.

As in the above description, in the third state S3 according to the second policy P1 of <FIG>, the control logic <NUM> may determine the occurrence of concentrated activation by comparing a count and/or a frequency of the activated row with a threshold value equal to or different from the first threshold value VTH1 and may selectively perform the refresh operation with respect to data bits of memory cells in a victim row based on a determination result. For example, the refresh operation may include reading the data bits from the victim row and writing the read bits to the victim row.

<FIG> illustrates an example of a process in which the semiconductor memory device <NUM> determines the concentrated activation in association with the flip operation and the refresh operation. Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, the control logic <NUM> of the semiconductor memory device <NUM> may perform the flip operation for an aggressor row and the refresh operation for a victim row together depending on the first policy P1 and the second policy P2.

In operation S310, the control logic <NUM> detects activation of a row. Operation <NUM> may be performed to be identical to operation S210.

In operation S320, the control logic <NUM> increases a first count and/or a first frequency and a second count and/or a second frequency of the activation. The first count and/or the first frequency may be used in association with the flip operation. The second count and/or the second frequency may be used in association with the refresh operation. Operation S320 may be performed similarly to operation S220. A counter for calculating the first count and/or the first frequency and the second count and/or the second frequency may be included in the control logic <NUM>.

In operation S330, the control logic <NUM> compares the first count and/or the first frequency with the first threshold value VTH1. When the first count and/or the first frequency does not reach the first threshold value VTH1, the control logic <NUM> may omit operation S340 and may perform operation S350. When the first count and/or the first frequency reaches the first threshold value VTH1, the control logic <NUM> performs operation S340. Operation S330 may be performed similarly to operation S230.

In operation S340, the control logic <NUM> determines whether the concentrated activation of a first step occurs at an activated row. When the concentrated activation of the first step is determined, the semiconductor memory device <NUM> may perform the flip operation. After the concentrated activation of the first step is determined, the control logic <NUM> may initialize the first count and/or the first frequency. Operation S340 may be performed similarly to operation S240.

In operation S350, the control logic <NUM> compares the second count and/or the second frequency with a second threshold value VTH2. The second threshold value VTH2 may be greater than the first threshold value VTH1. When the second count and/or the second frequency does not reach the second threshold value VTH2, the control logic <NUM> may omit operation S360 and may terminate the algorithm for determining the concentrated activation. When the second count and/or the second frequency reaches the second threshold value VTH2, the control logic <NUM> performs operation S360.

In operation S360, the control logic <NUM> determines whether the concentrated activation of a second step occurs at the activated row. When the concentrated activation of the second step is determined, the semiconductor memory device <NUM> may perform the refresh operation. After the concentrated activation of the second step is determined, the control logic <NUM> may initialize the first count and/or the first frequency and the second count and/or the second frequency.

In an embodiment, the second threshold value VTH2 is greater than the first threshold value VTH1. The semiconductor memory device <NUM> may determine the concentrated activation of the first step in response to that the number of times or the frequency of activation reaches the first threshold value VTH1. The semiconductor memory device <NUM> may compensate for or suppress the accumulation of stress or error by performing the flip operation in response to determining that the concentrated activation of the first step occurs.

The semiconductor memory device <NUM> may determine the concentrated activation of the second step in response to that the number of times or the frequency of activation reaches the second threshold value VTH2. The semiconductor memory device <NUM> may overall remove the influence of stress or error by performing the refresh operation in response to determining that the concentrated activation of the second step occurs.

The stress or error that occurs between the refresh operations may be compensated for or suppressed by the flip operations. Accordingly, compared to the case where the refresh operation of a victim row is performed based on the first policy P1 of <FIG>, in the case where both the refresh operation and the flip operation are performed based on the first policy P1 and the second policy P2 of <FIG>, a reference (e.g., the second threshold value VTH2) for determining the concentrated activation associated with the refresh operation may be set to a greater value.

In an embodiment, when a specific row is continuously activated, the flip operation and the refresh operation may be alternately performed in association with the specific row. When the first count and/or the first frequency reaches the first threshold value VTH1 and the second count and/or the second frequency also reaches the second threshold value VTH2, the flip operation and the refresh operation may be performed (or reserved) in association with the specific row. As another example, when the first count and/or the first frequency reaches the first threshold value VTH1 and the second count and/or the second frequency also reaches the second threshold value VTH2, the flip operation may be omitted, and only the refresh operation may be performed.

<FIG> illustrates an example of a process in which the semiconductor memory device <NUM> adjusts a reference value (e.g., the first threshold value VTH1) for determining concentrated activation. Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S410, the control logic <NUM> detects the concentrated activation based on the first threshold value VTH1 as described with reference to <FIG>.

In operation S420, the control logic <NUM> increases a concentration count in response to detecting the concentrated activation. In operation S430, the control logic <NUM> determines whether the concentration count reaches a third threshold value VTH3. When the concentration count does not reach the third threshold value VTH3, the control logic <NUM> may not perform (or may omit) operation S440 and may terminate the algorithm for adjusting a reference value.

When the concentration count reaches the third threshold value VTH3, in operation S440, the control logic <NUM> decreases the first threshold value VTH1. That is, in response to that the concentrated activation continuously occurs at a specific row (as much as the third threshold value VTH3), the semiconductor memory device <NUM> may decrease the first threshold value VTH1 that is used as a determination reference for determining the concentrated activation (or performing the flip operation). The control logic <NUM> may initialize the concentration count in response to that the concentrated activation continuously occurs at the specific row (as much as the third threshold value VTH3).

In an embodiment, the control logic <NUM> may stepwise decrease the first threshold value VTH1. That is, when the concentration count reaches the third threshold value VTH3, the control logic <NUM> may decrease the first threshold value VTH1. When the concentration count again reaches the third threshold value VTH3, the control logic <NUM> may further decrease the first threshold value VTH1.

In an embodiment, in the case where the number of neighbor rows adjacent to the specific row is <NUM>, the control logic <NUM> may manage two concentration counts with regard to the specific row. When the refresh operation or activation is performed with respect to the specific row, the control logic <NUM> may initialize the first threshold value VTH1 and the concentration count of a neighbor row adjacent to the specific row.

<FIG> illustrates an example of a process in which the semiconductor memory device <NUM> performs the write operation when performing the flip operation with respect to an aggressor row based on the second policy P2 of <FIG>. Referring to <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S510, the semiconductor memory device <NUM> receives a write command as the command CMD and receives write data as the data signals DQ.

In an embodiment, the write command and the write data may be received after a specific row is activated. The write command and the write data may be received together with a column address as the address ADDR.

In operation S520, the control logic <NUM> determines whether flip information of the activated row indicates a flip. When the flip information of the activated row indicates a flip, data bits stored in the sense amplifier <NUM> may be in a flip state. In operation S530, the control logic <NUM> flips (or inverts) the write data and stores the flipped write data. The control logic <NUM> may control the second flip signal FS2 such that the second flip circuits FC2 of the buffer circuit <NUM> output inverted bit signals. That is, the semiconductor memory device <NUM> may flip the write data and may store (e.g., overwrite) the flipped data on data bits corresponding to the column address from among the data bits of the sense amplifier <NUM>.

When the flip information of the activated row does not indicate a flip, the data bits stored in the sense amplifier <NUM> may be in a normal state, not the flip state. In operation S540, the control logic <NUM> stores the write data without performing the flip. The control logic <NUM> may control the second flip signal FS2 such that the second flip circuits FC2 of the buffer circuit <NUM> output bit signals. That is, the semiconductor memory device <NUM> may store (e.g., overwrite) the write data on the data bits corresponding to the column address from among the data bits of the sense amplifier <NUM> (without the flip operation).

The data stored in the sense amplifier <NUM> may be written in memory cells when the activated row is deactivated. That is, the semiconductor memory device <NUM> may selectively invert write data based on flip information and may write (e.g., overwrite) the write data (or the inverted write data) in memory cells.

<FIG> illustrates an example of a process in which the semiconductor memory device <NUM> performs a read operation when performing the flip operation with respect to an aggressor row based on the second policy P2 of <FIG>. Referring to <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S610, the semiconductor memory device <NUM> receives a read command as the command CMD. In an embodiment, the read command may be received after a specific row is activated. The read command may be received together with a column address as the address ADDR.

In operation S620, the control logic <NUM> determines whether flip information of the activated row indicates a flip. When the flip information of the activated row indicates a flip, data bits stored in the sense amplifier <NUM> may be in a flip state. In operation S630, the read data bits are flipped (or inverted) and output. The control logic <NUM> may control the first flip signal FS1 such that the first flip circuits FC1 of the buffer circuit <NUM> output inverted bit signals. That is, the semiconductor memory device <NUM> may flip data bits corresponding to the column address from among the data bits stored in the sense amplifier <NUM> and may output the flipped data bits as the data signals DQ.

When the flip information of the activated row does not indicate a flip, the data bits stored in the sense amplifier <NUM> may be in a normal state, not the flip state. In operation S640, the read data bits are output without being flipped or inverted. The control logic <NUM> may control the first flip signal FS1 such that the first flip circuits FC1 of the buffer circuit <NUM> output bit signals. That is, the semiconductor memory device <NUM> may output the data bits corresponding to the column address from among the data bits stored in the sense amplifier <NUM> as the data signals DQ.

That is, the semiconductor memory device <NUM> may selectively invert read data based on flip information so as to be output as the data signals DQ.

<FIG> illustrates a semiconductor memory device 100a according to an embodiment of the present disclosure Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, the semiconductor memory device 100a may include the first to fourth bank groups BG1 to BG4. Each of the first to fourth bank groups BG1 to BG4 may include the first to fourth banks B1 to B4. Each of the first to fourth banks B1 to B4 may include the memory cell array <NUM> and the sense amplifier <NUM>.

The semiconductor memory device <NUM> may further include the address register <NUM>, the row decoder <NUM>, the column decoder <NUM>, the first to fourth local gating circuits <NUM>, <NUM>, <NUM>, and <NUM>, the global gating circuit <NUM>, the buffer circuit <NUM>, and the control logic <NUM>.

A configuration and an operation of the semiconductor memory device 100a may be identical to those of the semiconductor memory device <NUM> of <FIG> except that a flip circuit (FC) <NUM> is provided in the sense amplifier <NUM>. Thus, additional description will be omitted to avoid redundancy. In each of the first to fourth banks B1 to B4 of the first to fourth bank groups BG1 to BG4, the sense amplifier <NUM> may include the flip circuit <NUM>.

<FIG> illustrates an example of an operating method of the semiconductor memory device 100a of <FIG>. In an embodiment, an example of a method for flipping data bits of an aggressor row based on the second policy P2 is illustrated in <FIG>. Referring to <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S710, the control logic <NUM> receives an active command as the command CMD. Also, the control logic <NUM> and the address register <NUM> may receive a bank group address, a bank address, and a row address as the address ADDR.

In response to the active command, in operation S720, the row decoder <NUM> selects one of the rows of the memory array cell <NUM> such that a word line of the selected row is activated. The row decoder <NUM> may select a bank group based on the bank group address, may select one of banks of the selected bank group based on the bank address, and may select one of rows of the selected bank such that a word line of the selected row is activated.

In operation S730, the control logic <NUM> determines whether the activation associated with the selected row is concentrated. For example, the control logic <NUM> may determine whether the concentrated activation occurs at the selected row. When the concentrated activation does not occur at the selected row, the semiconductor memory device <NUM> may terminate the procedure without performing the process of compensating for or suppressing the stress or error due to the concentrated activation. Afterwards, the semiconductor memory device <NUM> may wait for the command CMD and the address ADDR of the memory controller <NUM>.

When the concentrated activation occurs at the selected row, the semiconductor memory device <NUM> may perform the process of compensating for or suppressing the stress or error due to the concentrated activation. For example, the semiconductor memory device <NUM> may perform operation S740. Operation S710, operation S720, and operation S730 may be identical to operation S110, operation S120, and operation S130.

When the concentrated activation occurs at the selected row, in operation S740, the control logic <NUM> may flip data bits. The control logic <NUM> may flip data bits by using one of the first flip circuit FC1 and the second flip circuit FC2 of the sense amplifier <NUM>. The control logic <NUM> may store flip information of the activated row.

Comparing the semiconductor memory device <NUM> of <FIG> and the semiconductor memory device 100a of <FIG>, the semiconductor memory device 100a of <FIG> may include the first flip circuit FC1 and the second flip circuit FC2 for each of pairs of bit line sense amplifiers or pairs of column selection transistors CST. Accordingly, all data bits stored in the sense amplifier <NUM> may be flipped at the same time.

In an embodiment, the semiconductor memory device <NUM> may be modified such that the first flip circuit FC1 and the second flip circuit FC2 are provided for each of pairs of internal input and output lines IIO or for each of pairs of second input and output lines IO2.

<FIG> illustrates an example of an operating method of the memory system <NUM>. Referring to <FIG> and <FIG>, in operation S810, the memory controller <NUM> transmits an active command ACT and a row address RA to the semiconductor memory device <NUM>. In operation S820, the semiconductor memory device <NUM> activates a row corresponding to the row address RA.

In operation S830, the memory controller <NUM> determines whether the concentrated activation CA occurs. For example, the memory controller <NUM> may determine whether the concentrated activation CA occurs, based on the method described with reference to <FIG> and <FIG>. When the concentrated activation CA does not occur, the memory controller <NUM> may terminate the process of compensating for or suppressing the stress or error due to the concentrated activation CA.

When the concentrated activation CA occurs, in operation S840, the memory controller <NUM> transmits a flip command FLIP to the semiconductor memory device <NUM>. In operation S850, in response to the flip command FLIP, the semiconductor memory device <NUM> flips data bits of the activated row.

Compared to the method of <FIG> or <FIG>, the determination of the concentrated activation CA may be performed by the memory controller <NUM>. Flip information may be managed by the semiconductor memory device <NUM>. As described with reference to <FIG> and <FIG>, the semiconductor memory device <NUM> may selectively invert data bits based on the flip information and may perform the write operation or the read operation.

As another example, the flip information may also be managed by the memory controller <NUM>. The semiconductor memory device <NUM> may perform the flip operation in response to the flip command FLIP and may not flip data bits in the write operation or the read operation. The memory controller <NUM> may flip write data based on the flip information so as to be transmitted to the semiconductor memory device <NUM> or may flip data transferred from the semiconductor memory device <NUM> based on the flip information.

<FIG> illustrates an example of an electronic device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, the electronic device <NUM> may include a main processor <NUM>, a touch panel <NUM>, a touch driver integrated circuit (TDI) <NUM>, a display panel <NUM>, a display driver integrated circuit (DDI) <NUM>, a system memory <NUM>, a storage device <NUM>, an audio processor <NUM>, a communication block <NUM>, an image processor <NUM>, and a user interface <NUM>. In an embodiment, the electronic device <NUM> may be one of various electronic devices such as a personal computer, a laptop computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, and a wearable device.

The main processor <NUM> may control overall operations of the electronic device <NUM>. The main processor <NUM> may control/manage operations of the components of the electronic device <NUM>. The main processor <NUM> may perform various operations for the purpose of operating the electronic device <NUM>. The touch panel <NUM> may be configured to sense a touch input from a user under control of the touch driver integrated circuit <NUM>. The display panel <NUM> may be configured to display image information under control of the display driver integrated circuit <NUM>.

The system memory <NUM> may store data that are used in an operation of the electronic device <NUM>. For example, the system memory <NUM> may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and/or a nonvolatile memory such as a phase change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

The storage device <NUM> may store data regardless of whether a power is supplied. For example, the storage device <NUM> may include at least one of various nonvolatile memories such as a flash memory, a PRAM, an MRAM, a ReRAM, and a FRAM. For example, the storage device <NUM> may include an embedded memory and/or a removable memory of the electronic device <NUM>.

The audio processor <NUM> may process an audio signal by using an audio signal processor <NUM>. The audio processor <NUM> may receive an audio input through a microphone <NUM> or may provide an audio output through a speaker <NUM>. The communication block <NUM> may exchange signals with an external device/system through an antenna <NUM>. A transceiver <NUM> and a modulator/demodulator (MODEM) <NUM> of the communication block <NUM> may process signals exchanged with the external device/system in compliance with at least one of various wireless communication protocols: long term evolution (LTE), worldwide interoperability for microwave access (WiMax), global system for mobile communication (GSM), code division multiple access (CDMA), Bluetooth, near field communication (NFC), wireless fidelity (Wi-Fi), and radio frequency identification (RFID).

The image processor <NUM> may receive a light through a lens <NUM>. An image device <NUM> and an image signal processor (ISP) <NUM> included in the image processor <NUM> may generate image information about an external object, based on a received light. The user interface <NUM> may include an interface capable of exchange information with a user, except for the touch panel <NUM>, the display panel <NUM>, the audio processor <NUM>, and the image processor <NUM>. The user interface <NUM> may include a keyboard, a mouse, a printer, a projector, various sensors, a human body communication device, etc..

The electronic device <NUM> may further include a power management IC (PMIC) <NUM>, a battery <NUM>, and a power connector <NUM>. The power management IC <NUM> may generate an internal power from a power supplied from the battery <NUM> or a power supplied from the power connector <NUM>, and may provide the internal power to the main processor <NUM>, the touch panel <NUM>, the touch driver integrated circuit (TDI) <NUM>, the display panel <NUM>, the display driver integrated circuit (DDI) <NUM>, the system memory <NUM>, the storage device <NUM>, the audio processor <NUM>, the communication block <NUM>, the image processor <NUM>, and the user interface <NUM>.

The electronic device <NUM> may include the semiconductor memory device <NUM> or the memory system <NUM> described with reference to <FIG>. For example, the semiconductor memory device <NUM> or the memory system <NUM> of the present disclosure may be implemented with the system memory <NUM>. As another example, the semiconductor memory device <NUM> or the memory system <NUM> may be implemented with a memory of the touch driver integrated circuit <NUM>, the display driver integrated circuit <NUM>, the storage device <NUM>, the audio signal processor <NUM>, the MODEM <NUM>, the image signal processor <NUM>, and/or the user interface <NUM>.

In the above embodiments, components according to the present disclosure are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. need not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

According to the present disclosure, in response to that memory cells of a specific row are intensively activated, data bits stored in the memory cells of the specific row may be flipped. Accordingly, a method and a semiconductor memory device capable of compensating for or suppressing a stress coming from concentrated activation of memory cells in the specific row, and an operating method of a memory controller including the same are provided.

Claim 1:
A method for accessing memory cells arranged in rows and columns, the method comprising:
in response to receiving (S710) an active command, activating (S720) a specific row of the rows of the memory cells; and
flipping (S740) data bits stored in memory cells of the specific row in response to determining (S730) that a concentrated activation occurs at the specific row, and
wherein the flipping (S740) of the data bits stored in the memory cells of the specific row in response to determining (S730) that the concentrated activation occurs at the specific row comprises:
flipping the data bits stored in the memory cells of the specific row in response to determining (S230) that a number of times that the specific row is activated or a frequency at which the specific row is activated reaches a threshold value (VTH1).