Patent Description:
Some central processor unit (CPU) cores utilize speculative execution to avoid pipeline stalls and achieve better performance, which allows execution to continue without having to wait for the architectural resolution of a branch target. Branch prediction technology utilizes a digital circuit that guesses which way a branch will go before the branch instruction is executed. Correct predictions/guesses improve the flow in the instruction pipeline.

In general, there are two kind of branch predictions: branch prediction for conditional branches, which are understood as a prediction for the branch as "taken" vs. "not-taken"; and branch target prediction for unconditional branches, including both direct and indirect branches. Indirect branch prediction is an important part of the overall branch prediction, because an indirect branch typically involves higher latency in its target resolution, especially for a memory indirect branch the target of which needs to be fetched from a specific memory location. A branch prediction unit (BPU) supports speculative execution by providing a predicted target to the front-end (FE) of a CPU based on the branch instruction pointer (IP), branch type, and the control flow history (also referred as branch history) prior to the prediction point.

<CIT> relates to concurrent branch prediction for multiple branch-type instructions. For example, a processing unit includes a set of instruction group branch prediction arrays and concurrently branch predicts for branch-type instructions of an instruction group in accordance with branch prediction information in the set of instruction group branch prediction arrays.

<CIT> relates to branch prediction. For example, a processor comprises a branch predictor to generate, in association with a program loop, a frozen history vector comprising a snapshot of a branch history vector, track a current iteration of the program loop, and provide a prediction for a branch instruction associated with the program loop, the prediction based on the frozen history vector and the current iteration of the program loop.

<CIT> relates to trace prediction during parallel processing. For example, a method for trace prediction includes using trace prediction to predict a trace specifying branch decisions. When a branch misprediction is detected, trace prediction is terminated and prediction is continued using branch prediction.

The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:.

Embodiments discussed herein variously provide techniques and mechanisms for determining an execution of instructions based on a prediction of a taken branch. In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a processor or other circuitry suitable to execute instructions.

Some embodiments advantageously provide technology for a multi-offset predictor (MOP). In some embodiments, "offset" refers in this context to a relative location in a cache line. Modern superscalar processors achieve higher performance by extracting more instruction level parallelism (ILP) from the workloads. To facilitate this, superscalar processors employ ever growing Out-of-Order (OOO) instructions windows to identify more and more independent instructions. To support such wide and deep machines, the Front-End of the processor needs to provide a very high sustained instruction bandwidth to the OOO.

A major limiter of Front-End bandwidth is the Branch Prediction Unit (BPU). For example, one type of conventional BPU uses a Program Counter (PC) and Branch History (Stew) to predict each branch in a given cache-line, and then determine the first taken branch out of all the branches. After that, the BPU discards all instructions following the first taken branch. In the next cycle, the BPU operation restarts from the target of the branch instruction. Accordingly, every taken branch causes a BPU re-steering event which involves discarding unused fetched bytes and a cycle change. This limits the overall bandwidth of the Front-End and the performance of the processor.

To solve the above problem, some embodiments variously facilitate operation of a MOP which enables a very high sustained BPU bandwidth. Various embodiments of the MOP utilize the PC and Stew (e.g., a current program state), and identify a predicted next N taken branches, and their respective targets, in the program flow. In one such embodiment, the MOP directly jumps, in a next cycle, to the target of the predicted Nth taken branch.

Where a conventional predictor predicts each branch in a cache-line and then picks the first taken branch amongst them (if any), embodiments of the MOP directly produce the relative positions of some next N taken branches from the current PC and the targets of the next N taken branches. This is a major micro-architectural benefit of some embodiments. Additionally, in contrast to a conventional predictor which is re-steered after every taken branch, some embodiments of the MOP are re-steered only after N taken branches, effectively making a bandwidth of the MOP N times that of a conventional predictor. Accordingly, some embodiments provide a much higher BPU bandwidth using a very simple microarchitecture and low storage.

Some predictors utilize Path-based Next Trace prediction (PNT), where a Next-Trace predictor predicts units of traces. Compared to a conventional branch predictor which predicts every branch, the PNT predictor predicts an entire trace in one shot. The PNT predictor records sequences of traces as the path history of the program and uses the recorded sequence to predict the next trace.

Decoded stream buffer (DSB) simple-stream (DSS) technology identifies stable code regions in which the control flow is always constant. Such control flows are generally a result of always-taken or always-not-taken branches in the program. For such code regions, DSS records the DSB pointers to all micro-ops belonging to this region. Next time the same code region is encountered, DSS provides all the pointers to the DSB from where a stream of micro-ops is read out and supplied to the next pipeline stages. The main BPU is not consulted during this time. Accordingly, DSS can supply a stream of instructions spanning multiple taken branches in a single cycle without any BPU re-steering operation, opportunistically increasing the Front-End bandwidth.

Some high confidence multiple branch offset (HCoMB) predictors are trace predictors which predict N taken branches per cycle (e.g., where N is an integer greater than <NUM>). However, a HCoMB predictor is usually an opportunistic predictor which predicts only in those cases when it has sufficient confidence for all N predictions in the trace. When such a HCoMB predictor does not have sufficient confidence, predictions are instead given by a main branch prediction unit (BPU). Thus, a HCoMB predictor has a low coverage of taken branches. Often, HCoMB prediction can avail of N predicted branches only when there is high confidence on all the N predictions in a trace. If any of the predictions has low confidence, then prediction of the trace by the HCoMB does not occur.

The PNT predictor only supports a limited trace size (e.g., <NUM> instructions) or a limited number of branches (taken or not-taken), which is too small and not suitable to support the bandwidth requirements of very wide, deep OOO cores. In contrast, embodiments of the MOP provide information on the next N taken branches, which constitute an arbitrarily very long trace if the N taken branches are far apart. Also, the PNT predictor does not check if the branches are taken or not-taken. If a certain program region has many consecutive not-taken branches, the PNT predictor will break the entire region into multiple traces of six (<NUM>) branches each and take multiple cycles to predict this entire region. In contrast, embodiments of the MOP accommodate taken branches (rather than not-taken branches) because not-taken branches do not change the natural control flow of a program and hence, do not need prediction. By implicitly predicting not-taken branches, a MOP prediction spans a much larger code region than that covered by a single PNT prediction. Therefore, MOP prediction can provide a much higher throughput at much lower storage than the PNT predictor.

DSS relies on the DSB implementation. It only records DSB pointers whereas the actual micro-ops must be supplied by the DSB itself. Therefore, DSS requires inclusivity in the DSB. If the micro-ops are not present in DSB, DSS cannot give out a stream-prediction. Embodiments of the MOP do not have any dependency on the DSB. A MOP works as a standalone branch predictor. In terms of branch stability versus prediction stability, DSS relies very much on the stability of a given branch (e.g., DSS only works when branches are always-taken or always-not-taken). If a branch has inconsistent behavior, DSS cannot reliably handle it. Embodiments of the MOP, on the other hand, rely on prediction stability which means an MOP also works very well with branches that change behavior over time if the change can be accurately predicted. For example, embodiments of the MOP incorporate the branch history (Stew) in its prediction to work better with branches that change behavior over time. The branch history allows embodiments of the MOP to distinguish between each taken or not-taken instance of the same branch and therefore, accurately predict each instance separately. This contrast between branch stability and prediction stability gives embodiments of the MOP a superior coverage and performance over DSS.

Some embodiments of a MOP predict multiple taken branches per cycle and, for example, jump to the target of the last predicted taken branch. Given the current PC and Stew, some embodiments of the MOP generate pointers to the next N branches which are predicted to be taken. Using these pointers, the PC of the taken branch and its target are accurately identified and thus, an entire control flow is constructed from a current point until the Nth taken branch. In one such embodiment, any of the N branch predictions which is determined to be of low confidence is sent to another prediction unit, which performs its own branch prediction, for the same branch instruction, in addition to the low confidence branch prediction. If the additional branch prediction is determined to be inconsistent with the low confidence branch prediction, the prediction unit generates a signal to flush or otherwise clear at least some execution state of an execution pipeline which would otherwise execute instructions based on the N branch predictions. Advantageously, some embodiments provide a mechanism to enhance the bandwidth of the front end (FE) of the processor, which is a critical limitation when scaling the depth-width of processor cores. Further, some embodiments are highly area efficient and leverage existing hardware structures in the front end for most of the work. Thus, some embodiments provide a simple way to support an important requirement of a wide variety of processors.

In various embodiments, a MOP prediction is not dependent on the confidence associated with the predictions. For example, if a trace is present in the MOP table, it can be predicted irrespective of the confidence of the individual predictions in that trace. Thus, MOP provides multiple predictions per cycle even when the confidence of individual predictions is low. Therefore, MOP has a much higher prediction coverage than the HCoMB predictor and hence, offers higher performance as well.

Although some embodiments are not limited in this regard, an MOP supports operation with a buffer - referred to herein as a verification queue (VQ) - which is not present, for example, in existing HCoMB predictors. In one such embodiment, any branch prediction which is not of a high confidence prediction type is buffered in a verification queue, and subsequently dequeued to an additional prediction unit for validation. If a mismatch is detected between the respective predictions by the MOP and the additional prediction unit, a front end clear (or other such signal) is issued. This feature allows an additional prediction unit to run in the background and not affect the front end bandwidth.

<FIG> shows features of a processor <NUM> to execute instructions based on branch predictions according to an embodiment. Processor <NUM> illustrates one example of an embodiment wherein circuitry provides functionality to selectively clear a state of an execution pipeline based on an invalidity of a branch prediction. In an embodiment, an evaluation of the branch prediction (the evaluation to detect for the invalidity) is performed based on a low confidence classification of the branch prediction. Alternatively or in addition, the branch prediction is one of multiple branch predictions which are each provided, or otherwise indicated, to the execution pipeline - e.g., wherein the multiple branch predictions are determined in a single cycle of a sequence of prediction cycles.

As shown in <FIG>, processor <NUM> comprises a front end unit <NUM> and circuitry <NUM> coupled to front end unit <NUM>, where circuitry <NUM> is configured to provide a multi-offset predictor (MOP). For example, circuitry <NUM> is configured to access an entry, in a multiple-taken-branch (MTB) prediction table, which corresponds to a conditional branch instruction, and to provide or otherwise indicate to an execution pipeline some N successive branch predictions (where N is an integer greater than <NUM>) that are expected to stem from that conditional branch instruction. For example, circuitry <NUM> is configured to generate tag information for a conditional branch instruction - e.g., based on a last taken branch and a branch history - and to identify an entry in the MTB table based on the generated tag information.

In some embodiments, circuitry <NUM> is configured to predict N taken branches per cycle and then jump to the target of the last predicted taken branch. In some embodiments, circuitry <NUM> is further configured to generate pointers to the next N branches which are predicted to be taken based on a current PC and branch history (stew). In some embodiments, circuitry <NUM> is further configured to identify the PC of the taken branch and its target based on the generated pointers. For example, circuitry <NUM> is configured to construct an entire execution control flow from a current point until the Nth taken branch based on the generated pointers.

In some embodiments, circuitry <NUM> is further configured to write to, read from, and/or otherwise access a registry (e.g., implemented with a MTB table, with a separate trace table, and/or with one or more other suitable data structures) of confidence metrics which each correspond to a respective branch prediction. In one such embodiment, circuitry <NUM> is further configured to evaluate one such confidence metric to determine whether (or not) - according to some predetermined criteria - a corresponding branch prediction is of a "low confidence" type or a "high confidence" type. For example, circuitry <NUM> is configured to compare a confidence metric to a predetermined value representing a threshold minimum confidence level.

In various embodiments, circuitry <NUM> is further configured to provide or otherwise indicate a low confidence prediction to another prediction unit, which is to subject said low confidence prediction to further evaluation. For example, the other prediction unit is to determine whether the low confidence prediction is valid according to (e.g., is consistent with) some additional prediction criteria.

Embodiments of front end unit <NUM> and/or circuitry <NUM> are incorporated in a processor including, for example, the core <NUM> (in <FIG>), the cores 902A-N (in <FIG>, <FIG>), the processor <NUM> (in <FIG>), the co-processor <NUM> (in <FIG>), the processor <NUM> (in <FIG>), the processor/coprocessor <NUM> (in <FIG>), the coprocessor <NUM> (in <FIG>), the coprocessor <NUM> (in <FIG>), and/or the processors <NUM>, <NUM> (in <FIG>). In particular, embodiments of circuitry <NUM> are incorporated in the front end unit <NUM> (in <FIG>).

<FIG> shows features of a processor <NUM> to provide branch prediction information according to an embodiment. Processor <NUM> provides functionality such as that of processor <NUM>, for example. As shown in <FIG>, processor <NUM> comprises a front end unit <NUM> to decode one or more instructions, and an execution pipeline <NUM> communicatively coupled to front end unit <NUM> to execute the decoded one or more instructions.

Front end unit <NUM> includes a prediction unit <NUM> to selectively provide branch prediction functionality for one or one or more instructions, and a multi-offset predictor (MOP) <NUM> communicatively coupled to the prediction unit <NUM>, the MOP <NUM> including circuitry to predict multiple taken branches per cycle and then (for example) jump to the target of the last predicted taken branch.

In various embodiments, circuitry of MOP <NUM> (e.g., including some or all of circuitry <NUM>) generates multiple branch predictions in a single cycle of a sequence of prediction cycles - e.g., wherein a duration of the cycle is equal to that of a single cycle of a clock signal which regulates operations of processor <NUM>. Functionality of MOP <NUM> is adapted, for example, from conventional techniques and mechanisms to generate multiple branch predictions in a single cycle. The details of such conventional techniques and mechanisms are not limiting on some embodiments, and are not detailed herein to avoid obscuring certain features of said embodiments.

In some embodiments, circuitry of MOP <NUM> (or alternatively, circuitry coupled to MOP <NUM>) is configured to access a registry of confidence metrics which each correspond to a respective one of the N branch predictions. In one such embodiment, the circuitry is further configured to determine, based on confidence metrics, whether respective confidences in the branch prediction are variously greater than, or less than, a threshold confidence level.

In the example embodiment shown, MOP <NUM> detects an instance of N branch predictions - e.g., wherein MOP <NUM> identifies or otherwise detects, in a single cycle, N branch predictions which each correspond to a respective branch instruction in a software program. The N branch predictions have a relative order, with respect to each other, in an execution sequence of the software program. For example, one or more of the N branch predictions are each predicated on a respective earlier one of the N branch predictions in the sequence. Based on the detected instance, MOP <NUM> provides to execution pipeline <NUM> one or more indications of the N branch predictions - e.g., via the illustrative signal <NUM> shown. For example, for one or more of the N branch predictions, signal <NUM> identifies (e.g., includes) or otherwise indicates an expected next instruction to be performed after said branch prediction. Additionally or alternatively, for some or all of the N branch predictions, signal <NUM> explicitly identifies said branch prediction.

In some embodiments, circuitry of MOP <NUM> (or alternatively, circuitry coupled to MOP <NUM>) is further configured to provide or otherwise indicate to prediction unit <NUM> - e.g., via signal <NUM> - any of the N branch predictions which are determined to be of a low confidence type. Circuitry of prediction unit <NUM> is configured to determine, for any such low confidence prediction, whether the prediction is consistent with an additional branch prediction which prediction unit <NUM> performs independently, using additional prediction criteria, for the corresponding branch instruction. The low confidence prediction is determined to be "valid" where it is found to be consistent with the additional prediction performed by prediction unit <NUM>, and "invalid" where the two branch predictions are inconsistent with each other. Where a low confidence branch prediction is determined to be invalid, prediction unit <NUM> provides an indication - e.g., via the illustrative signal <NUM> shown - that at least some state of execution pipeline <NUM> is to be cleared. Based on signal <NUM>, some or all of the current execution state of execution pipeline <NUM> is flushed - e.g., to facilitate subsequent operations to recover from an invalid branch prediction.

<FIG> shows features of a method <NUM> to operate a processor based on branch prediction information according to an embodiment. The method <NUM> illustrates one example of an embodiment which facilitates an execution of one or more instructions based on the detection of a sequence of predicted taken branches, wherein at least one such predicted taken branch is selectively provided, based on a corresponding confidence metric, to determine whether such execution should be stopped, cleared and/or otherwise interrupted. Operations such as those of method <NUM> are performed, for example, with processor <NUM> or processor <NUM>.

As shown in <FIG>, method <NUM> comprises (at <NUM>) detecting an instance of N branch predictions comprising a first branch prediction, wherein N is an integer greater than one. For example, the detecting at <NUM> comprises an MOP of the processor identifying each of the N branch predictions in a first cycle of a sequence of branch prediction cycles. In an embodiment, one or more of the N branch predictions are each based on a respective other one of the N branch predictions - e.g., wherein the N branch predictions each correspond to a different respective branch instruction of an expected execution flow of a software process.

Method <NUM> further comprises operations <NUM> which are performed based on the instance which is detected at <NUM>. In an embodiment, operations <NUM> comprise (at <NUM>) indicating each of the N branch predictions to an execution pipeline. For example, the indicating at <NUM> comprises, for one or more of the N branch instructions, specifying or otherwise indicating to the execution pipeline a respective next instruction which is expected after a corresponding branch instruction for which the branch prediction was made. In one such embodiment, the indicating at <NUM> comprises providing an indication of at least a next expected instruction after the Nth branch instruction in an expected execution flow.

In some embodiments, the indicating at <NUM> comprises, or is otherwise based on, selecting an indication of one of the N branch predictions over an indication of a different prediction other than any of the N branch predictions. By way of illustration and not limitation, a processor performing method <NUM> further comprises line predictor, and a multiplexer and/or other suitable circuitry to select between the line predictor, and the MOP which performs the detecting at <NUM>. Such selection is based, for example, on a hit resulting from a search of a trace table or other suitable registry of confidence metrics for the N branch predictions. By contrast, in an alternative scenario wherein the search fails to result in the hit, a prediction from the line predictor is instead provided to the execution pipeline.

Operations <NUM> further comprise (at <NUM>) identifying a confidence metric which corresponds to the first branch prediction, and (at <NUM>) determining, based on the confidence metric, whether to send the first branch prediction to a prediction unit of the processor. For example, the MOP includes, is coupled to, or is otherwise configured to operate with, a registry of confidence metrics each for a different respective branch prediction. In one such embodiment, entries of the registry each correspond to a different respective set of N branch predictions - e.g., wherein a given one such entry comprises N confidence metrics each for a different respective one of the N branch predictions.

Although some embodiments are not limited in this regard, method <NUM> further comprises operations <NUM> which are performed in a circumstance wherein - based on the determining at <NUM> - the first branch prediction is sent to the prediction unit. In one such embodiment, operations <NUM> comprise (at <NUM>) performing an evaluation, with the prediction unit, to determine a validity condition of the first branch prediction.

For example, the first branch prediction corresponds to a first branch instruction - e.g., wherein the first branch prediction is based on a PC value which identifies the first branch instruction. In one such embodiment, determining the validity condition at <NUM> comprises the prediction unit generating a second branch prediction based on the first branch instruction (e.g., based on the same PC value), and determining whether the first branch prediction is consistent with the second branch prediction. The first branch prediction is considered valid where it is determined to be consistent with the second branch prediction, or (alternatively) is considered invalid where it is instead determined to be inconsistent with the second branch prediction.

In an embodiment, operations <NUM> further comprise (at <NUM>) determining, based on the validity condition, whether to provide a signal to clear a state of the execution pipeline. For example, some or all execution state of the execution pipeline is cleared where the first branch prediction is determined to be invalid - e.g., by flushing the respective execution state for any instruction currently being processed by the execution pipeline. By contrast, such clearing of the execution pipeline is to be avoided, or at least delayed, where the first branch prediction is determined to be valid.

In some embodiments, method <NUM> further comprises additional operations (not shown) which are performed in the circumstance wherein the first branch prediction is sent to the prediction unit. For example, in some embodiments, the processor performing method <NUM> provides functionality to buffer a given prediction prior to an evaluation of said prediction by the prediction unit. In one such embodiment, method <NUM> further comprises debuffering that given prediction (e.g., one other than the first branch prediction) from the buffer, and then sending the prediction to the prediction unit. Method <NUM> further comprises (for example) determining that said buffer is currently empty and, based on such a determination, communicating the first branch prediction to the prediction unit via a path which bypasses the buffer.

Additionally or alternatively, such additional operations of method <NUM> comprise detecting a condition wherein a utilization of such a buffer is above a threshold level, and - based on the condition - generating a second signal to reduce an operational rate of the execution pipeline. In one such embodiment, detecting the condition comprises detecting that the buffer is currently full, wherein the second signal is to at least temporarily stop an execution of instructions by the execution pipeline. In some embodiments, after generating this second signal, method <NUM> further detects a current availability of space at the buffer, wherein - based on the availability - a third signal is provided to increase the operational rate of the execution pipeline.

In an alternative embodiment, the detected condition comprises a total number of predictions enqueued to the buffer currently being greater than a threshold number, while also being less than a maximum number of predictions which the buffer is able to accommodate. In such an embodiment, based on the second signal, the execution pipeline transitions from a first positive rate of instruction execution to a second positive rate of instruction execution (which is less than the first positive rate). Subsequently, in some embodiments, method <NUM> detects that the total number of predictions enqueued to the buffer is currently less than the threshold number. Based on such detecting, method <NUM> generates a third signal to increase the operational rate of the execution pipeline.

In various embodiments, method <NUM> additionally comprises operations to variously update one or more confidence metrics which each correspond to a different respective branch prediction. In one such embodiment, method <NUM> detects whether the first branch prediction had a successful outcome or, alternatively, an unsuccessful outcome. For example, a branch prediction has a successful outcome where the first branch prediction correctly indicates the branch which was actually taken by a subsequent execution of a corresponding branch instruction. Additionally or alternatively, the branch prediction has a successful outcome where it passes a validity test such as one performed at <NUM>.

In various embodiments, method <NUM> updates a value of a confidence metric (the updating based on the successful outcome of the first branch prediction) to indicate an increased confidence in the first branch prediction. Alternatively, where an unsuccessful outcome of the first branch prediction is detected, method <NUM> updates such a value to indicate a decreased confidence in the first branch prediction - for example, wherein the value is decremented by some predetermined number or, alternatively, is reset to some baseline value (e.g., zero).

<FIG> shows a timing diagram <NUM> illustrating branch predictions which are performed during a single cycle according to an embodiment. In various embodiments, timing diagram <NUM> illustrates operations by one of processors <NUM>, <NUM> - e.g., wherein method <NUM> includes or is otherwise based on such operations. As shown in <FIG>, a software program comprises a fetched instruction stream which is broken into multiple traces comprising N taken branches each, wherein N is an integer - in this example, four (<NUM>) - which is greater than one (<NUM>).

Some embodiments of a MOP snoop the instruction stream, and record the taken branches - e.g., in a N-entry buffer. When the buffer is full, the sequence of N taken branches, referred to herein collectively as a trace, are registered in an entry of a table (referred to herein as a "trace table") or other suitable registration resource. The entry is identified using index information, such as a hash value which is calculated based on a PC associated with one of the taken branches (e.g., a PC for a branch instruction, or for a target instruction), and/or based on a branch history of the program up to the point of one of the N taken branches. After a trace is registered, the buffer is cleared to accommodate training for a next trace in the instruction stream.

In various embodiments, a trace entry registers the N branch predictions and, for each such branch prediction, a different respective confidence metric which indicates a confidence in that branch prediction. For example, a confidence metric for a given branch prediction is set to some baseline value when a trace is initially registered. As one or more later instances of the same N branch predictions are subsequently detected, that confidence metric is variously increased, decreased, reset, or otherwise changed - e.g., according to the corresponding branch prediction having an outcome which was successful, or unsuccessful.

<FIG> shows features of a registered trace <NUM>, which provides branch prediction information according to an embodiment. In various embodiments, trace <NUM> is used by one of processor <NUM> or processor <NUM> - e.g., wherein one or more operations of method <NUM> are determine and/or use trace <NUM>. <FIG> is an illustrative diagram of an example format of a trace table entry. To facilitate a prediction lookup, some embodiments of a MOP comprise, are coupled to, or otherwise operate with a single set-associative table which stores all information required to identify a branch prediction. In one such embodiment, each entry in the trace table holds data regarding a respective one (<NUM>) trace in the program. An example MOP table entry appears as shown in <FIG>.

As shown in <FIG>, trace <NUM> comprises a tag field to store an index value which facilitates a search for the entry in the trace table. In some embodiments, trace <NUM> further comprises a utility field to store a value which indicates a current number of search "hits" - i.e., a number of times that the entry has been the subject of a trace table search. Trace <NUM> further comprises confidence metrics (Conf <NUM>, Conf <NUM>) each to indicate a respective level of confidence in a respective one of the N branch predictions - in this example, two (<NUM>) predictions - which are represented by trace <NUM>. Trace <NUM> further comprises offset fields (Offset <NUM>, Offset <NUM>) each to provide a respective value which indicates an offset location, in an instruction cache, for a cached instruction which corresponds to a respective one of the N branch predictions. Trace <NUM> further comprises branch type fields (Branch type <NUM>, Branch type <NUM>) each to indicate, for a corresponding one of the N branch predictions, a respective branch type of a branch instruction for which the branch prediction is made. Trace <NUM> further comprises target fields (Target <NUM>, Target <NUM>) which are each to indicate a respective location of a next instruction which is expected to be targeted by a corresponding predicted branch.

<FIG> shows features of a processor <NUM> to evaluate branch predictions based on confidence information according to an embodiment. The processor <NUM> illustrates one example of an embodiment wherein N branch predictions are indicated to an execution pipeline, wherein one or more of the N branch predictions are also subject to being selected for validity testing to determine whether state of the execution pipeline is to be cleared. In various embodiments, processor <NUM> provides functionality such as that of processor <NUM> or processor <NUM> - e.g., wherein one or more operations of method <NUM> are performed with processor <NUM>.

To illustrate certain features of various embodiments, methods <NUM>, <NUM>, <NUM> - shown in <FIG>, <FIG> (respectively) - are variously described herein with reference to operations by the example processor <NUM>. However, in other embodiments, one or more operations of method <NUM>, <NUM>, or <NUM> are performed with any of various other suitable devices which provide functionality described herein.

As shown in <FIG>, processor <NUM> comprises a MOP <NUM>, a prediction unit <NUM>, execution pipeline circuitry <NUM>, and a controller <NUM> which facilitates the indicating of branch predictions to execution pipeline circuitry <NUM> (and, under certain circumstances, to prediction unit <NUM>). In an embodiment, MOP <NUM> comprises application specific integrated circuitry, and/or any of various other suitable integrated circuits, which provides functionality to identify each of N branch predictions in a single branch prediction cycle. For example, processor <NUM> includes some or all of the features of MOP <NUM> - e.g., wherein prediction unit <NUM> and execution pipeline circuitry <NUM> correspond functionally to prediction unit <NUM>, and execution pipeline <NUM> (respectively).

MOP <NUM> provides to controller <NUM> a signal <NUM> which specifies or otherwise indicates the detected instance of the N branch predictions. Controller <NUM> is coupled to a trace table <NUM> or other suitable registry resource, entries of which - such as the illustrative entries 432a,. , 432x shown - each comprise a trace of a different respective N branch predictions. For example, a given entry of table <NUM> comprises some or all of the features of trace <NUM>. In the example embodiment shown, one entry 432a of table <NUM> is indexed by a tag value Ta, and comprises confidence metric values Ca1,. , CaN each for a first N branch predictions. By contrast, another entry 432x of table <NUM> is indexed by a tag value Tx, and comprises other confidence metric values Cx1,. , CxN each for a second N branch predictions. However, the number and/or contents of entries 432a,. , 432x are merely illustrative, and not limiting on some embodiments. Although MOP <NUM> is shown as being distinct from controller <NUM> and table <NUM>, in various other embodiments, controller <NUM> and/or table <NUM> are integrated in MOP <NUM>.

In an embodiment, controller <NUM> calculates or otherwise determines a tag value (or other suitable index) based on an indication of the N branch predictions which is communicated via signal <NUM>. In one such embodiment, the tag value is generated with a hash calculation which is based on a PC value for a branch instruction, or (for example) for an instruction which is a target of a predicted branch. With the tag value, controller <NUM> performs a search of table <NUM> to identify which (if any) of entries 432a,. , 432x corresponds to the N branch predictions which were indicated by MOP <NUM> via signal <NUM>. Where such a search results in a hit of one of the entries 432a,. , 432x, controller <NUM> accesses the entry in question to determine (for example) the respective confidence metrics for some or all of the N branch predictions.

Based on a search of table <NUM> which results in a hit, controller <NUM> specifies or otherwise indicates the registered N branch predictions (using the illustrative signal <NUM>, for example) to execution pipeline circuitry <NUM>, which - in turn - prepares to execute one or more instructions based on the N branch predictions. Furthermore, controller <NUM> evaluates some or all of the respective confidence metrics for the N branch predictions, to determine whether any such branch prediction should also be subjected to validity testing (i.e., to determine, based on an additional branch prediction, whether the branch prediction in question is to be considered valid, or invalid). In some embodiments, a determination that a branch prediction is invalid results in processor <NUM> clearing some or all execution state of execution pipeline circuitry <NUM>.

By way of illustration and not limitation, controller <NUM> performs an evaluation to determine whether a given branch prediction is considered to be of a low confidence type. For example, controller <NUM> compares a given confidence metric to a predetermined value representing a threshold minimum level of confidence. The threshold value is provided, for example, as a priori information by a manufacturer, distributer, administrator, test unit, or other agent. In an illustrative scenario according to some embodiments, a confidence metric is equal to an integer value in a range of possible integer values (e.g., a range from <NUM> to <NUM>), wherein the threshold minimum confidence level is, for example, at a middle of the range (e.g., equal to <NUM>). However, some embodiments use any of various other ranges, threshold levels and/or other techniques to represent and evaluate confidence information. Moreover, some embodiments are not limited with respect to a particular threshold confidence level, or to a particular basis on which, and/or source from which the threshold confidence level is provided to controller <NUM>.

Where a given one of the N branch predictions is determined to be of low confidence, controller <NUM> outputs a signal <NUM> which is to provide, or otherwise identify, the low confidence branch prediction to prediction unit <NUM>. Responsive to controller <NUM>, prediction unit <NUM> performs a validation test for the low confidence branch prediction - e.g., by generating another branch prediction based on the same branch instruction for which the low confidence branch prediction was made by MOP <NUM>. Where a low confidence prediction is determined to be invalid, prediction unit <NUM> generates a signal <NUM> to clear some or all of the execution state of execution pipeline circuitry <NUM>.

In various embodiments, branch predictions by prediction unit <NUM> tend to be more complex and/or otherwise more reliable than those branch predictions by MOP <NUM>. By way of illustration and not limitation, prediction unit <NUM>, as compared to MOP <NUM>, employs a more sophisticated branch prediction algorithm which is able to more accurately determine an outcome of a given branch instruction's execution. Additionally or alternatively, prediction unit <NUM>, as compared to MOP <NUM>, employs a larger number and/or size of one or more branch prediction tables (BTBs), for example.

In some embodiments, controller <NUM> is further coupled to receive one or more signals (e.g., including the illustrative signal <NUM> shown) which indicates whether a given branch prediction had a successful outcome. Signal <NUM> is provided by execution pipeline circuitry <NUM>, for example (or by prediction unit <NUM>, in another embodiment). A branch prediction is successful where, for example, it is determined by prediction unit <NUM> to be valid and, in some embodiment, where the branch prediction correctly indicates the branch which was actually taken by a subsequent execution of a corresponding branch instruction. By contrast, such a branch prediction is unsuccessful where it is instead determined to be invalid and/or incorrect. Based on the successful (or alternatively, unsuccessful) outcome of a given branch prediction - as indicated by signal <NUM> - controller <NUM> updates a corresponding confidence metric at table <NUM> to indicate an increased (or alternatively, decreased) confidence in that branch prediction.

Although some embodiments are not limited in this regard, processor <NUM> further comprises additional circuitry to selectively provide one or more predictions to prediction unit <NUM> and execution pipeline circuitry <NUM>, where (for example) a search of table <NUM> results in a miss. For example, processor <NUM> further comprises another line predictor <NUM> and selection logic (e.g., comprising the illustrative multiplexer circuits <NUM>, <NUM>) which facilitates selection between indicating a branch prediction - if any - which has been identified by controller <NUM>, and indicating a line prediction which has been identified by line predictor <NUM>.

In the example embodiment shown, multiplexer circuits <NUM>, <NUM> are variously coupled to receive, from controller <NUM>, a control signal <NUM> which indicates whether a search of table <NUM> has resulted in a hit (or alternatively, in a miss). Where a search hit is indicated by control signal <NUM>, multiplexer circuit <NUM> provides - as an output signal <NUM> - the one or more indications of the N branch predictions which were communicated by controller <NUM> via signal <NUM>. Furthermore, the search hit results in multiplexer circuit <NUM> providing as an output signal <NUM> the indication of a low confidence branch prediction (if any) which was communicated by controller <NUM> via signal <NUM>. By contrast, where a search miss is indicated by control signal <NUM>, multiplexer circuit <NUM> and multiplexer circuit <NUM> each provide - via the respective output signals <NUM>, <NUM> - a different indication of a line prediction which line predictor <NUM> communicates to multiplexer circuits <NUM>, <NUM> via signal <NUM>.

<FIG> shows features of a method <NUM> to operate a processor according to an embodiment. Method <NUM> illustrates one example of an embodiment wherein a multi-offset predictor (MOP) provides predictions each to an execution pipeline, which is subject to being cleared at least in part based on a determination that one such prediction is invalid. In an embodiment, the determination is performed based on the detection of a low confidence in a branch prediction. Operations such as those of method <NUM> are performed, for example, with one of processors <NUM>, <NUM>, <NUM>, <NUM> - e.g., wherein method <NUM> includes or is otherwise based on some or all such operations.

As shown in <FIG>, method <NUM> comprises (at <NUM>) detecting, in one cycle, an instance of N branch predictions. Method <NUM> further comprises performing an evaluation (at <NUM>) to determine whether the N branch predictions detected at <NUM> are currently registered (e.g., in a trace table or other suitable resource). For example, the evaluation performed at <NUM> includes or is otherwise based on the determining of a tag value, or other suitable index, with which a trace table (for example) is to be searched - e.g., wherein the tag value is calculated based on the branch instructions for which the N branch predictions are made.

Where it is determined at <NUM> that the N branch predictions are not registered, method <NUM> (at <NUM>) registers the N branch predictions - e.g., by storing to a trace table a trace which, for example, includes respective confidence metrics for each of the N branch predictions. In one such embodiment, some or all of the respective confidence metrics are each initially set to some baseline (e.g., default) value indicating a lowest confidence level in a range of possible confidence levels. As described herein, such confidence metrics are subject to being variously updated over time, where one or more other instances of the N branch predictions are subsequently detected.

Furthermore, where the N branch predictions are not registered, method <NUM> successively indicates N line predictions (at <NUM>) both to execution pipeline circuitry and to a prediction unit - e.g., in lieu of indicating any of the N branch predictions to either of the execution pipeline circuitry or the prediction unit. After sending the N line predictions at <NUM>, method <NUM> performs a next instance of the detecting at <NUM>.

Where it is instead determined at <NUM> that the N branch predictions are registered, method <NUM> performs operations to indicate the N branch predictions to the execution pipeline circuitry, and to provide a low confidence branch prediction (if any) for evaluation to determine whether or not said low confidence branch prediction is invalid. By way of illustration and not limitation, method <NUM> (at <NUM>) identifies a next one of the N branch prediction to be processed - e.g., starting with an earliest of the N branch predictions in the software program sequence. Method <NUM> then indicates this next branch prediction (at <NUM>) to the execution pipeline circuitry - e.g., by providing or otherwise identifying to the execution pipeline circuitry a next instruction which is expected to be after (and based on) a respective branch instruction for which the prediction is made.

Method <NUM> further performs an evaluation (at <NUM>) to determine whether, according to some predetermined criteria, the branch prediction most recently identified at <NUM> is a low confidence prediction. Where it is determined at <NUM> that there is insufficient confidence in the branch prediction, method <NUM> (at <NUM>) specifies or otherwise indicates the branch predication to the prediction unit (such as one of prediction units <NUM>, <NUM>, for example). Where it is instead determined at <NUM> that there is sufficient confidence in the branch prediction, method <NUM> (at <NUM>) specifies or otherwise indicates the line predication (e.g., in lieu of the branch prediction) to the prediction unit.

Method <NUM> further comprises performing an evaluation (at <NUM>) to determine whether there is any remaining branch prediction of the N branch predictions which were most recently detected at <NUM>. Where it is determined at <NUM> that there is at least one such remaining branch prediction, method <NUM> performs a next instance of the identifying at <NUM>. Where it is instead determined at <NUM> that there is no such remaining branch prediction, method <NUM> performs a next instance of the detecting at <NUM>.

<FIG> shows features of a method <NUM>, according to an embodiment, to determine confidence information which facilitates the selective evaluation of whether a given branch prediction is invalid. In one embodiment, such a selective evaluation results in a state of an execution pipeline being cleared. Operations such as those of method <NUM> are performed, for example, with one of processors <NUM>, <NUM>, <NUM>, <NUM> - e.g., wherein method <NUM> or method <NUM> includes or is otherwise based on some or all such operations.

As shown in <FIG>, method <NUM> comprises (at <NUM>) detecting an outcome of a registered branch prediction. In an embodiment, the detecting at <NUM> comprises controller <NUM>, or other suitable circuit logic, receiving or otherwise detecting a signal (such as the illustrative signal <NUM>) which specifies or otherwise indicates whether the execution of a branch instruction resulted in an outcome which was indicated by a corresponding branch prediction.

Method <NUM> further comprises (at <NUM>) accessing a confidence metric which corresponds to the registered branch prediction. For example, the accessing at <NUM> comprises controller <NUM> identifying the prediction as being one of a recently detected N branch predictions, and searching table <NUM> - using a tag which corresponds to said N branch predictions - for a respective one of the entries 432a,. In an embodiment, the respective entry includes a confidence metric corresponding to the branch prediction.

Method <NUM> performs an evaluation (at <NUM>) to determine, based on the outcome detected at <NUM>, whether the branch prediction was correct. Where it is determined at <NUM> that the branch prediction was correct, method <NUM> (at <NUM>) updates the corresponding confidence metric - in the entry accessed at <NUM> - to indicate an increased confidence in said branch prediction. By way of illustration and not limitation, a value of the confidence metric is incremented by one or otherwise increased - e.g., unless the value already indicates some maximum possible level of confidence. After the updating at <NUM>, method <NUM> performs a next instance of the detecting at <NUM>.

Where it is instead determined at <NUM> that the branch prediction was incorrect, method <NUM> (at <NUM>) updates the corresponding confidence metric to indicate a decreased confidence in said branch prediction. For example, a value of the confidence metric is reset to a baseline value (e.g., zero) or otherwise decremented. After the updating at <NUM>, method <NUM> performs a next instance of the detecting at <NUM>.

<FIG> shows features of a method <NUM>, according to an embodiment, to selectively clear state of an execution pipeline based on whether a given prediction is valid. Operations such as those of method <NUM> are performed, for example, with one of processors prediction unit <NUM>, prediction unit <NUM> or other suitable circuit logic - e.g., wherein method <NUM> and/or method <NUM> include or are otherwise performed based on some or all such operations.

As shown in <FIG>, method <NUM> comprises (at <NUM>) receiving a prediction which comprises one of a low confidence branch prediction or a line prediction. For example, the receiving at <NUM> comprises prediction unit <NUM> receiving signal <NUM> from multiplexer circuit <NUM>, wherein - based on control signal <NUM> - signal <NUM> indicates a selected one of a line prediction indicated by signal <NUM>, or a branch prediction indicated by signal <NUM>.

Method <NUM> further comprises (at <NUM>) determining a validity state corresponding to the prediction. In an embodiment, determining the validity state comprises determining whether - according to some criteria - the prediction is to be considered valid or, alternatively, invalid. For example, such determining comprises performing another prediction regarding the same instruction for which the prediction received at <NUM> was made - e.g., using a different prediction basis than that used for the received prediction.

Method <NUM> further comprises performing an evaluation (at <NUM>) to determine whether the received prediction is valid. In various embodiments, the received prediction is determined to be valid where it is identified as being the same (i.e., predicting the same outcome) as the other prediction performed at <NUM>. By contrast, the received prediction is determined to be invalid where it is instead identified as being different than (i.e., predicting the different outcome) said other prediction.

Where it is determined at <NUM> that the prediction is invalid, method <NUM> (at <NUM>) provides a signal - such as the illustrative signal <NUM> from prediction unit <NUM> - to clear some or all of the execution state of execution pipeline circuitry <NUM>. Where it is instead determined at <NUM> that the prediction is valid, method <NUM> performs a next instance of the receiving at <NUM> - e.g., without signaling that the execution state is to be cleared.

<FIG> shows features of a processor <NUM> to selectively clear an execution pipeline based on an invalidation of a branch prediction according to an embodiment. The processor <NUM> illustrates an embodiment wherein a buffer (in this example, a verification queue, or "VQ") is coupled to regulate a provisioning of predictions to a prediction unit for validity testing. In various embodiments, processor <NUM> provides functionality of one of processors <NUM>, <NUM>, <NUM> - e.g., wherein operations of one of methods <NUM>, <NUM>, <NUM>, <NUM> are performed with processor <NUM>.

To illustrate certain features of various embodiments, methods <NUM>, <NUM> - shown in <FIG> (respectively) - are variously described herein with reference to operations by the example processor <NUM>. However, in other embodiments, one or more operations of methods <NUM>, <NUM> are performed with any of various other suitable devices which provide functionality described herein.

As shown in <FIG>, processor <NUM> comprises a MOP <NUM>, a controller <NUM>, a table <NUM>, a prediction unit <NUM>, an execution pipeline circuitry <NUM>, a line predictor <NUM>, and multiplexer circuits <NUM>, <NUM> which - for example - correspond functionally to MOP <NUM>, controller <NUM>, table <NUM>, prediction unit <NUM>, execution pipeline circuitry <NUM>, line predictor <NUM>, and multiplexer circuits <NUM>, <NUM> (respectively). For example, table <NUM> comprises entries 532a,. , 532x, which correspond functionally to entries 432a,. , 432x, in an embodiment. Signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM> - variously communicated with MOP <NUM>, controller <NUM>, line predictor <NUM>, and multiplexer circuits <NUM>, <NUM> - correspond functionally to signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (respectively). Furthermore, signals <NUM>, <NUM>, <NUM> - variously communicated with multiplexer circuits <NUM>, <NUM>, prediction unit <NUM>, and execution pipeline circuitry <NUM> - correspond functionally to signals <NUM>, <NUM>, <NUM> (respectively).

In the example embodiment shown, processor <NUM> further comprises a verification queue (VQ) <NUM> - which is coupled between prediction unit <NUM> and multiplexer circuitry <NUM> - and a monitor/selector unit <NUM> which (for example) selectively determines whether or not an indication of a given branch prediction is to be enqueued or otherwise buffered to VQ <NUM>. A given prediction which is buffered to VQ <NUM> is subsequently debuffered for communication to prediction unit <NUM> via signal <NUM>.

In an embodiment, monitor/selector unit <NUM> is coupled to receive an output signal <NUM> from multiplexer circuitry <NUM>, wherein signal <NUM> indicates one of a low confidence branch prediction by MOP <NUM>, or a line prediction by line predictor <NUM>. Monitor/selector unit <NUM> is further coupled to monitor information (e.g., communicated by the illustrative signal <NUM> shown) which indicates whether VQ <NUM> is currently empty. Where signal <NUM> indicates that no predictions are currently enqueued by VQ <NUM>, monitor/selector unit <NUM> sends the indication - which was provided by signal <NUM> - in an output signal <NUM> for buffering to VQ <NUM>. Otherwise, monitor/selector unit <NUM> sends the indication, in an output signal <NUM> to prediction unit <NUM>, via a path which bypasses VQ <NUM>.

Additionally or alternatively, monitor/selector unit <NUM> detects - e.g., based on signal <NUM> - whether VQ <NUM> is currently full or otherwise above some threshold number of enqueued predictions. Where signal <NUM> indicates that a number of currently predictions enqueued by VQ <NUM> is below such a threshold number, monitor/selector unit <NUM> generates one or more signals (e.g., comprising the illustrative control signal <NUM> shown) to stop, stall or otherwise reduce a rate of one or more operations by execution pipeline circuitry <NUM>. In some embodiments, controller <NUM> is further coupled to receive one or more signals (not shown) which indicate whether an outcome of a given branch prediction was successful - e.g., wherein controller <NUM> updates a corresponding confidence metric based on the outcome.

<FIG> shows features of a method <NUM> to selectively buffer predictions which are to be validated by a prediction unit according to an embodiment. Operations such as those of method <NUM> are performed, for example, with one of processors <NUM>, <NUM>, <NUM> - e.g., wherein method <NUM>, method <NUM> and/or method <NUM> include or are otherwise performed based on some or all such operations.

As shown in <FIG>, method <NUM> comprises (at <NUM>) receiving a prediction which comprises one of a low confidence branch prediction or a line prediction. For example, the receiving at <NUM> comprises monitor/selector unit <NUM> receiving signal <NUM> from multiplexer circuitry <NUM>, wherein - based on control signal <NUM> - signal <NUM> indicates a selected one of a line prediction indicated by signal <NUM>, or a branch prediction indicated by signal <NUM>. Method <NUM> further comprises performing an evaluation (at <NUM>) to determine whether a queue - referred to herein as a verification queue (VQ) - currently empty. In an embodiment the VQ - such as VQ <NUM> - is provided to buffer predictions that have yet to be classified (e.g., according to method <NUM>, for example) as being valid or invalid.

Where it is determined at <NUM> that the VQ is empty, method <NUM> (at <NUM>) sends the prediction to the prediction unit via a path which bypasses the VQ. After sending the prediction at <NUM>, method <NUM> performs a next instance of the receiving at <NUM>. Where it is instead determined at <NUM> that the VQ is not empty, method <NUM> (at <NUM>) buffers the prediction to the VQ - e.g., wherein the prediction is to be subsequently dequeued for processing by the prediction unit. After the buffering at <NUM>, method <NUM> performs a next instance of the receiving at <NUM>.

<FIG> shows features of a method <NUM>, according to an embodiment, to selectively control an execution pipeline based on an ability of one or more predictions to be received for evaluation by a prediction unit. Operations such as those of method <NUM> are performed, for example, with one of processors <NUM>, <NUM>, <NUM> - e.g., wherein one of methods <NUM>, <NUM>, <NUM>, <NUM> includes or is otherwise performed based on some or all such operations.

As shown in <FIG>, method <NUM> comprises performing an evaluation (at <NUM>) to determine whether a current number of predictions buffered at a verification queue (VQ) is above some predetermined threshold number. For example, the performing at <NUM> comprises or is otherwise based on monitor/selector unit <NUM> receiving a signal (such as the illustrative signal <NUM> shown) which identifies a number of predictions currently enqueued by VQ <NUM>. In some embodiments, the evaluation is performed at <NUM> based on the sending of a prediction at <NUM> of method <NUM> (for example).

Where it is determined at <NUM> that the VQ is not currently above the threshold number of predictions, method <NUM> performs a next instance of the evaluation at <NUM> - i.e., without signaling that operations of execution pipeline circuitry (such as that of execution pipeline <NUM>) are to be stopped or otherwise stalled. Where it is instead determined at <NUM> that the VQ is above the threshold number, method <NUM> (at <NUM>) sends a signal to stall an execution of one or more instructions by the execution pipeline circuitry. For example, method <NUM> stops or otherwise slows instruction execution while buffered predictions are successively processed by the prediction unit - e.g., until either the number of buffered predictions falls below the high threshold, or an invalid prediction results in a state of the execution pipeline being cleared. After the sending at <NUM>, method <NUM> performs a next instance of the evaluation at <NUM>.

In some embodiments, the evaluation at <NUM> comprises determining whether the VQ is full - e.g., wherein the signal sent at <NUM> is to stop all instruction execution by the execution pipeline circuitry. In an alternative embodiment, the evaluation at <NUM> comprises determining whether the VQ is at or above a threshold level which still allows for the VQ to enqueue one or more additional predictions. In one such embodiment, the signal sent at <NUM> is to provide a lower rate at which instructions are executed by the execution pipeline circuitry.

The figures described herein detail exemplary architectures and systems to implement embodiments of the above. In some embodiments, one or more hardware components and/or instructions described herein are emulated as detailed below, or implemented as software modules.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units <NUM>/<NUM> and a shared L2 cache unit <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core, along with its connection to the on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to embodiments of the invention. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> and vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core is stored in its L2 cache subset <NUM> and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset <NUM> and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is <NUM>-bits wide per direction.

<FIG> is an expanded view of part of the processor core in <FIG> according to embodiments of the invention. <FIG> includes an L1 data cache 806A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> is a <NUM>-wide vector processing unit (VPU) (see the <NUM>-wide ALU <NUM>), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 822A-B, and replication with replication unit <NUM> on the memory input. Write mask registers <NUM> allow predicating resulting vector writes.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 902A, a system agent <NUM>, a set of one or more bus controller units <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 902A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 902A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 902A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 902A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes respective one or more levels of caches 904A-N within cores 902A-N, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit <NUM> interconnects the special purpose logic <NUM>, the set of shared cache units <NUM>, and the system agent unit <NUM>/integrated memory controller unit(s) <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 902A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 902A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 902A-N and the special purpose logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

There can be a variety of differences between the processors <NUM>, <NUM> in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller unit's point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interconnect <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM> and an interconnect <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> in order to avoid obscuring other aspects of <FIG>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 902A-N and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using an x86 compiler <NUM> to generate x86 binary code <NUM> that may be natively executed by a processor with at least one x86 instruction set core <NUM>. The processor with at least one x86 instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler <NUM> represents a compiler that is operable to generate x86 binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one x86 instruction set core <NUM> (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter <NUM> is used to convert the x86 binary code <NUM> into code that may be natively executed by the processor without an x86 instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code <NUM>.

Techniques and architectures for executing instructions based on branch predictions are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

Claim 1:
A processor (<NUM>) comprising:
first prediction circuitry (<NUM>) to detect an instance of N branch predictions which comprise a first branch prediction, wherein N is an integer greater than one, wherein the first prediction circuitry (<NUM>) to detect the instance comprises the first prediction circuitry (<NUM>) to identify each of the N branch predictions in a first cycle of a sequence of branch prediction cycles, wherein one or more of the N branch predictions are each based on a respective other one of the N branch predictions;
controller circuitry (<NUM>) coupled to the first prediction circuitry (<NUM>), wherein based on the instance, the controller circuitry (<NUM>) is to:
indicate each of the N branch predictions to an execution pipeline (<NUM>); and
based on a confidence metric which corresponds to the first branch prediction, determine whether to send the first branch prediction to a prediction unit (<NUM>); and
second prediction circuitry coupled to the controller circuitry (<NUM>), wherein, where the first branch prediction is sent to the prediction unit (<NUM>), the second prediction circuitry is to:
perform an evaluation of a validity condition of the first branch prediction; and
determine, based on the validity condition, whether to provide a signal to clear a state of the execution pipeline (<NUM>).