Patent Description:
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random-access memory (RAM), read only memory (ROM), DRAM, synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Advancing memory technology has realized improvements for many of these metrics, however, as improvements in processing speed are developed, memory bandwidth can become a bottleneck to overall system performance improvements.

<CIT> generally relates to methods, systems, and devices for communicating data with stacked memory dies. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

<CIT> generally relates to an apparatus and method for storing information, including using an integrated circuit including a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. To store information, the on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer.

In a first aspect, a storage system is provided according to claim <NUM>.

Features of the disclosure introduced above are further described below in the context of an exemplary array (e.g., <FIG>). Specific examples are then described for various examples or aspects of systems (e.g., <FIG>).

<FIG> illustrates an example of a memory die <NUM> in accordance with various aspects disclosed herein. Memory die <NUM> may also be referred to as an electronic memory apparatus, a memory array, an array of memory cells, or a deck of memory cells, in some examples. The memory die <NUM> may include memory cells <NUM> that are programmable to store different states. Memory cells <NUM> may be arranged in one or more banks of memory cells that may be independently accessible. Each memory cell <NUM> may be programmable to store two states, denoted as a logic <NUM> and a logic <NUM>. In some cases, memory cell <NUM> may be configured to store more than two logic states.

In some examples, a memory cell <NUM> may store a charge representative of the programmable states in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may use such a design, and the capacitor employed may include a dielectric material with linear or para-electric electric polarization properties as the insulator. FeRAM architectures may also employ such a design. In some examples, a memory cell <NUM> may store a representation of the programmable states in a cross-coupled inverter configuration. Static RAM (SRAM) architectures may use such a design.

Operations such as reading and writing may be performed on memory cells <NUM> by activating access line <NUM> and digit line <NUM>. Access lines <NUM> may also be known as word lines <NUM>, and bit lines <NUM> may also be known digit lines <NUM>. References to word lines and bit lines, or their analogues, are interchangeable without loss of understanding or operation. Activating a word line <NUM> or a digit line <NUM> may include applying a voltage to the respective line.

According to the example of <FIG>, each row of memory cells <NUM> may be connected to a single word line <NUM>, and each column of memory cells <NUM> may be connected to a single digit line <NUM>. By activating one word line <NUM> and one digit line <NUM> (e.g., applying a voltage to the word line <NUM> or digit line <NUM>), a single memory cell <NUM> may be accessed at their intersection. Accessing the memory cell <NUM> may include reading or writing the memory cell <NUM>. The intersection of a word line <NUM> and digit line <NUM> may be referred to as an address of a memory cell. Additionally or alternatively, for example, each row of memory cells <NUM> may be arranged in one or more banks of memory cells.

In some architectures, the logic storing device of a cell, e.g., a capacitor, flip-flop, may be electrically isolated from the digit line by a selection component (not shown). The word line <NUM> may be connected to and may control the selection component. For example, the selection component may be a transistor and the word line <NUM> may be connected to the gate of the transistor. Activating the word line <NUM> may result in an electrical connection or closed circuit between the capacitor of a memory cell <NUM> and its corresponding digit line <NUM>. The digit line may then be accessed to either read or write the memory cell <NUM>.

Accessing memory cells <NUM> may be controlled through a row decoder <NUM> and a column decoder <NUM>. For example, a row decoder <NUM> may receive a row address from the memory controller <NUM> and activate the appropriate word line <NUM> based on the received row address. Similarly, a column decoder <NUM> may receive a column address from the memory controller <NUM> and activate the appropriate digit line <NUM>. Row decoder <NUM> and column decoder <NUM> may receive a row address and a column address, respectively, for a memory cell located within one specific bank of memory cells. Additionally or alternatively, each bank of memory cells may be in electronic communication with a separate row decoder <NUM> and column decoder <NUM>. For example, memory die <NUM> may include multiple word lines <NUM>, labeled WL_1 through WL_M, and multiple digit lines <NUM>, labeled DL_1 through DL_N, where M and N depend on the array size. Thus, by activating a word line <NUM> and a digit line <NUM>, e.g., WL_2 and DL_3, the memory cell <NUM> at their intersection may be accessed.

Upon accessing a memory cell <NUM>, the cell may be read, or sensed, by sense component <NUM> to determine the stored state of the memory cell <NUM>. For example, after accessing the memory cell <NUM>, the capacitor of memory cell <NUM> may discharge onto its corresponding digit line <NUM>. Discharging the capacitor may in some cases result from biasing, or applying a voltage, to the capacitor. The discharging may cause a change in the voltage of the digit line <NUM>, which sense component <NUM> may compare to a reference voltage (not shown) to determine the stored state of the memory cell <NUM>. For example, if digit line <NUM> has a higher voltage than the reference voltage, then sense component <NUM> may determine that the stored state in memory cell <NUM> was a logic <NUM> and vice versa. Sense component <NUM> may include various transistors or amplifiers to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell <NUM> may then be output through column decoder <NUM> as output <NUM>. In some cases, sense component <NUM> may be part of a column decoder <NUM> or row decoder <NUM>. Or, sense component <NUM> may be connected to or in electronic communication with column decoder <NUM> or row decoder <NUM>.

A memory cell <NUM> may be set, or written, by similarly activating the relevant word line <NUM> and digit line <NUM>-e.g., a logic value may be stored in the memory cell <NUM>. Column decoder <NUM> or row decoder <NUM> may accept data, for example input/output <NUM>, to be written to the memory cells <NUM>. A memory cell <NUM> may be written by applying a voltage across the capacitor.

The memory controller <NUM> may control the operation (e.g., read, write, rewrite, refresh, discharge, etc.) of memory cells <NUM> through the various components, for example, row decoder <NUM>, column decoder <NUM>, and sense component <NUM>. Memory controller <NUM> may be a component of memory die <NUM> or may be external to memory die <NUM> in various examples. In some cases, one or more of the row decoder <NUM>, column decoder <NUM>, and sense component <NUM> may be co-located with the memory controller <NUM>. Memory controller <NUM> may generate row and column address signals to activate the desired word line <NUM> and digit line <NUM>. The memory controller <NUM> may activate the desired word line <NUM> and digit line <NUM> of a specific bank of memory cells via at least one channel traversing the memory die <NUM>. Memory controller <NUM> may also generate and control various voltages or currents used during the operation of memory die <NUM>. For example, it may apply discharge voltages to a word line <NUM> or digit line <NUM> after accessing one or more memory cells <NUM>. Memory controller <NUM> may be coupled to memory cells <NUM> via channels <NUM>. Channels <NUM> are illustrated in <FIG> as logical connections with row decoder <NUM> and column decoder <NUM>, but those skilled in the art will recognize that other configurations may be employed. As described herein, memory controller <NUM> may exchange data (e.g., from a read or write operation) with cells <NUM> multiple times per clock cycle.

The memory controller <NUM> may also be configured to communicate commands, data, and other information with a host device (not shown). The memory controller <NUM> may use a modulation scheme to modulate signals communicated between the memory array and the host device. An I/O interface may be configured based on what type of modulation scheme is selected. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die <NUM>. Furthermore, one, multiple, or all memory cells <NUM> within memory die <NUM> may be accessed simultaneously or concurrently; for example, multiple or all cells of memory die <NUM> may be accessed simultaneously or concurrently during a reset operation in which all memory cells <NUM>, or a group of memory cells <NUM>, are set to a single logic state.

<FIG> illustrates an apparatus or system <NUM> that supports channel routing for a memory device in accordance with various examples disclosed herein. The system <NUM> may include a host device <NUM> and a plurality of stacks <NUM>. In conventional systems, the plurality of stacks can include stacked memory die of the same type, such as DRAM memory die. In certain examples, the stacks can include a mix of capacitive based memory devices such as DRAM forming a main memory array, and a faster access memory architecture, for example, a cross-linked inverter memory such a SRAM, which commonly includes four to six transistors per cell, for a second portion of the memory array. In place of DRAM, another storage technology may be used. The present inventor has recognized that bandwidth improvements can be realized if the host has direct access to a second, faster, deterministic type of memory, such as SRAM memory, in addition to the main memory array. Other forms of memory may be used as alternatives to SRAM. In some examples, Ferroelectric RAM (FeRAM) may be utilized in combination with the DRAM; or in other examples non-volatile DRAM devices (such as NVDIMM) combining DRAM and flash memory to provide a non-volatile memory may be used. The greatest benefits to the described systems, at least in terms of speed, will be experienced with a reduced access time memory technology, in combination with the DRAM (or other main memory array storage technology).

The host device <NUM> may be an example of a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), or a system on a chip (SoC). In some cases, the host device <NUM> may be a separate component from the memory device such that the host device <NUM> may be manufactured separately from the memory device. The host device <NUM> may be external to the stacks <NUM> (e.g., a laptop, server, personal computing device, smartphone, personal computer). In the system <NUM>, the stacks of memory die <NUM> may be configured to store data for the host device <NUM>. The described techniques enable direct communication with either the main memory array or the SRAM, as further described below.

The host device <NUM> may exchange information with the stacks of memory die <NUM> using signals communicated over signal paths. A signal path may be a path that a message or transmission may take from a transmitting component to a receiving component. In some cases, a signal path may be a conductor coupled with at least two components, where the conductor may selectively allow electrons to flow between the at least two components. The signal path may be formed in a wireless medium as in the case for wireless communications (e.g., radio frequency (RF) or optical). The signal paths may at least partially include a first substrate, such as an organic substrate of the memory device, and/or a second substrate, such as a package substrate (e.g., a second organic substrate) that may be coupled with at least one, if not both, of the stacks <NUM> and the host device <NUM>. In some cases, the stacks <NUM> may function as a slave-type device to the host device <NUM>, which may function as a master-type device.

In some applications, the system <NUM> may benefit from a high-speed connection between the host device <NUM> and the memory devices <NUM>. As such, some stacks <NUM> support applications, processes, host devices, or processors that have multiple terabytes per second (TB/s) bandwidth needs. Satisfying such a bandwidth constraint within an acceptable energy budget may pose challenges in certain contexts.

The memory dies <NUM> of the stacks <NUM> may be configured to work with multiple types of communication mediums <NUM> (e.g., substrates such as organic substrates and/or high-density interposers such as silicon interposers). The host device <NUM> may, in some cases, be configured with an interface or ball-out comprising a design (e.g., a matrix or pattern) of terminals.

In some cases, a buffer layer may be positioned between the memory dies <NUM> and the communication medium <NUM>. The buffer layer may be configured to drive (e.g., redrive) signals to and from the memory dies <NUM>. In some cases, the stacks <NUM> of memory dies <NUM> may be bufferless meaning that either no buffer layer is present or that a base layer does not include re-drivers, among other components. In certain examples of bufferless memory, a routing layer or logic die <NUM> may be positioned between the memory die <NUM>, or stack of memory die <NUM> and the communication medium <NUM>. In certain examples, the logic die <NUM> can form a lower layer of a memory die <NUM>. In certain examples, a bufferless memory stack <NUM> can include a lower most memory die <NUM> having a logic die layer <NUM>.

<FIG> illustrates generally an example storage system <NUM> including a host device <NUM> that can request and receive information from a storage system <NUM> according to the present subject matter. The host device <NUM> may be, but is not limited to, a CPU, graphics processing unit (GPU), accelerated processing unit (GPU), digital signal processor (DSP), field-programmable gate array (FPGA), application specific integrated circuit (ASIC) and any other component of a larger system that communicates with the storage system <NUM>. In some embodiments, the device <NUM> may be multiple devices accessing the same storage system <NUM>. The storage system <NUM> can include a logic die <NUM> integrated with a memory stack <NUM>, such as a stack of dynamic random-access memory (DRAM) devices.

The logic die <NUM> can include a host interface <NUM> connected to a stacked DRAM control <NUM> and prefetch and cache logic <NUM>. The stacked DRAM control <NUM> is connected to and interfaces with the memory stack <NUM>. The prefetch and cache logic <NUM> can be connected with a prefetcher, prefetch buffers and a cache array <NUM>. The prefetcher may be a hardware prefetcher. The prefetch buffers and cache array <NUM> may be, but is not limited to, an SRAM array, any other memory array technology, or a register.

The host interface <NUM> can include a command decoder <NUM> and interface registers <NUM>. The host interface <NUM>, and more specifically, the command decoder <NUM> can receive all incoming memory requests to the memory stack <NUM> from the device <NUM>. The requests can be sent to the prefetch and cache logic <NUM>, (for example, next-line, stride, and the like). The prefetch and cache logic <NUM> can monitor the incoming memory requests. Prefetched data can be placed into the prefetch buffers and cache array <NUM>. The prefetch and cache logic <NUM> can also check any incoming memory requests against the data in the prefetch buffers and cache array <NUM>. Any hits can be served directly from the prefetch buffers and cache array <NUM> without going to the stacked DRAM control <NUM>. This can reduce service latencies for these requests, as well as reduce contention in the stacked DRAM control <NUM> of any remaining requests, (i.e., those that do not hit in the prefetch buffers and cache array <NUM>).

The prefetcher may encompass any prefetching algorithm/method or combination of algorithms/methods. Due to the row-buffer-based organization of most memory technologies, (for example, DRAM), prefetch algorithms that exploit spatial locality, (for example, next-line, small strides and the like), have relatively low overheads because the prefetch requests will (likely) hit in the memory's row buffer(s). Implementations may issue prefetch requests for large blocks of data, (i.e., more than one 64B cache line's worth of data), such as prefetching an entire row buffer, half of a row buffer, or other granularities.

The prefetch buffers and cache array <NUM> may be implemented as a directmapped, set-associative, to a fully-associative cache-like structure. In an embodiment, the prefetch buffers and cache array <NUM> may be used to service only read requests, (i.e., writes cause invalidations of prefetch buffer entries, or a write-through policy must be used). In another embodiment, the prefetch buffers and cache array <NUM> may employ replacement policies such as Least Recently Used (LRU), Least Frequency Used (LFU), or First In First Out (FIFO). If the prefetch unit generates requests for data sizes larger than a cache line, (as described hereinabove), the prefetch buffers and cache array <NUM> may also need to be organized with a correspondingly wider data block size. In some embodiments, sub-blocking may be used.

While described herein as being employed in a memory organization consisting of one logic chip and one or more memory chips, there are other physical manifestations. Although described as a vertical stack of a logic die with one or more memory chips, another embodiment may place some or all of the logic on a separate chip horizontally on an interposer or packaged together in a multi-chip module (MCM). More than one logic chip may be included in the overall stack or system.

In certain examples, the host interface <NUM> can directly access a portion of the buffers and cache array <NUM> or can directly access a separate instance of SRAM-type memory <NUM>. In such examples, the command decoder <NUM> is responsive to a command truth table that includes commands that extend beyond accessing and servicing the DRAM memory stack <NUM>. More specifically, the command decoder <NUM> can be responsive to commands for directly accessing SRAM-type storage located <NUM> on the logic die <NUM>. As used herein, SRAM-type memory includes memory that has less latency than the DRAM memory of the storage system. In such memory, information can be accessed with less latency than information stored at the stacked memory <NUM>. In certain examples, directly accessing an instance of, for example, SRAM <NUM> at the logic die <NUM>, information can be accessed with less latency than information available at the prefetch buffers or cache array <NUM> via the prefetch and cache logic <NUM>.

<FIG> illustrate generally an example truth table extension of existing high bandwidth memory protocols to allow access to a second type of random-access memory within a stack of random-access memory dies. Such stacks can be used in high bandwidth memory packages. In certain examples, systems adapted to operate with a memory stack including a mix of DRAM and faster SRAM can also work with conventional memory stack systems that include a homogeneous stack of memory die. The present inventor has recognized that unused states of existing interface protocols can be exploited to allow for a memory controller to specifically command and control the faster memory so as to improve overall storage system bandwidth. In certain examples, each channel can provide independent access to an area of memory of the memory stack. In certain examples, each channel can act independent of another channel. Each channel can include an independent command and data interface. In certain examples, each command and data interface can include a number signals or terminations including data (DQ[ND:<NUM>), column command/address (C[Nc:<NUM>]) and row command/address (R[NR:<NUM>]) among others, where ND, NC and NR can be the maximum signal address of the respective group or bus of signals or terminations. In certain examples, specific operations of a stack of memory die can be initiated by properly setting the respective signals of the row command/address and column command/address while receiving a clock signal. Conventional operations of DRAM stacks use the first few signals (R[<NUM>:<NUM>] of the row command/address signals and the first few signal (C[<NUM>:<NUM>]) of the column command/address signals to initiate various operations of the stack of DRAM devices. In certain examples, the channels couple an interface of the memory controller with a device interface and device control circuitry of one or more of the memory die in the stack.

In certain examples, where the stack of memory die includes one or more SRAM arrays, the memory controller can access the SRAM arrays using an extension of the conventional row and column command truth tables, such as the row and column truth tables provided in JEDEC Standard No. 235B. <FIG> illustrates generally an example row command truth table extension. <FIG> illustrates generally a column truth table extension. In certain examples, unlike conventional methods, the row and column command/address signals can work in tandem to initiate individual operations to access the one or more SRAM arrays within the stack of memory die.

As an example, upon receiving a rising clock signal and additional signals on the row command/address where R0-R2 are logic "high" (H), "low" (L), H, respectively, the memory device controller of an SRAM device can recognize that the memory controller is requesting access to the SRAM device. The remaining row command/address signals, as well as the column command/address signals, can provide additional information to confirm the SRAM access request, provide address information, and specific command information such as whether the request is a read request, write request and whether or not the request is to use a buffer for the data. Referring to <FIG>, signals or terminations R3-R5 on the riding edge of the clock signal, and R0, R4 and R5 on the falling edge of the clock signal can provide a portion of the SRAM address (A10-A15) for the requested SRAM access. The "D" at R6 on the falling edge of the clock (CLK) stands for "Do Not Care" and indicates the logic level is not relevant for the illustrated example. Referring to FIG. 3B, signals of the column command/address interface of the same channel, including C3-C7 on the rising edge of the clock, and C1 and C3-C6 on the falling edge of the clock signal can provide the rest of the SRAM address (A0-A9) for the requested SRAM access. On the rising edge of the clock signal, C0 and C1 can verify that the command address information provided to the memory controller is a SRAM access request when C0 is set "low" and C1 is set "high". Also, on the rising edge, the state of C2 can indicate whether the access is a "read" access or a "write" access. SID0 and SID1 can indicate a stack identification of the device for the SRAM access command.

Existing stacked DRAM devices can operate in a number of modes. Some modes have been added as the stacked DRAM technology has evolved. In certain examples, one such mode of operation is generally referred to a pseudo channel mode. Pseudo channel mode can divide a channel into two individual sub channels or pseudo channels. Both pseudo channels can operate semi-independently. The pseudo channels can share the channel's row command/address bus and column command/address bus, however, each pseudo channel can execute and decode commands individually. Command/address signal BA4 can be used to direct a SRAM access command to one of the two pseudo channels. In certain examples, the command information can include a parity bit (PAR) that can be used to insure the command information on ether the row command/address interface or the column command address interface did not get corrupted before being received by the memory controller.

In certain examples, SRAM and DRAM access commands can be isolated from the external bus connecting the host with the host interface. In such examples, a memory access command does not provide read data to the external bus or receive write data from the external bus, but instead, uses an internal buffer, such as a prefetch buffer or similar register to capture data read from SRAM or Stacked DRAM and to provide data for an SRAM write or a stacked DRAM write command. In such examples, column command address signal C8, on a falling edge of the clock signal, can provide a binary state to indicate whether the internal buffer or the external bus is to be used as the data target of a memory access command. In certain examples, a column command/address bit, such as the C8 bit can be used, on the falling edge of the clock signal (CLK) to indicate to the memory controller or the command decoder of the host interface, the data location to use for the direct SRAM or stacked DRAM access command. In a first state, the C8 bit can indicate the memory controller can use the external data bus as the data location for the memory access command. In a second state, the C8 bit can indicate that the memory controller can use an internal buffer as the data location for the memory access command.

<FIG> illustrate generally an example truth table extension of existing high bandwidth memory protocols to allow access to a second type of random-access memory within a stack of random-access memory die. Such stacks can be used in high bandwidth memory packages. The example of <FIG> allow for a larger capacity SRAM than can be addressed by the example of <FIG>.

As an example, upon receiving a rising clock signal and additional signals on the row command/address where R0-R2 are logic "high" (H), "low" (L), H, respectively, the memory device controller of an SRAM device can recognize that the memory controller is requesting access to the SRAM device. The remaining row command/address signals, as well as the column command/address signals, can provide additional information to confirm the SRAM access request, provide address information, and specific command information such as whether the request is a read request, write request and whether or not the request is to use a buffer for the data. Referring to <FIG>, signals or terminations R3-R5 on the riding edge of the clock signal, and R0, R4 and R5 on the falling edge of the clock signal can provide a portion of the SRAM address (A12-A20) for the requested SRAM access. Referring to FIG. 3B, signals of the column command/address interface of the same channel, including C3-C7 on the rising edge of the clock, and C1 and C3-C6 on the falling edge of the clock signal can provide the rest of the SRAM address (A0-A11) for the requested SRAM access. On the rising edge of the clock signal, C0 and C1 can verify that the command address information provided to the memory controller is a SRAM access request when C0 is set "low" and C1 is set "high". Also, on the rising edge, the state of C2 can indicate whether the access is a "read" access or a "write" access.

Existing stacked DRAM die can operate in a number of modes. Some modes have been added as the stacked DRAM technology has evolved. In certain examples, one such mode of operation is generally referred to a pseudo channel mode. Pseudo channel mode can divide a channel into two individual sub channels or pseudo channels. Both pseudo channels can operate semi-independently. The pseudo channels can share the channel's row command/address bus and column command/address bus however, each pseudo channel can execute and decode commands individually. Command/address signal BA4 can be used to direct a SRAM access command to one of the two pseudo channels. In certain examples, the command information can include a parity bit (PAR) that can be used to insure the command information on ether the row command/address interface or the column command address interface did not get corrupted before being received by the memory controller.

<FIG> illustrates generally a flowchart of an example method <NUM> for operating a storage system including a stack of first memory. In certain examples, the storage system can include a logic die, a memory controller, a first interface and a second interface. The logic die can receive and decode requests received from the host via the first interface. The logic die can initiate data access of the storage system via the memory controller of the stack of first memory, via a cache, via a second memory of the logic die, or combinations thereof. In some examples, the first memory can include DRAM die coupled to the memory controller via the second interface. In some examples, the second memory can be SRAM memory. The logic die includes the memory controller. In certain examples, the memory controller can reside as a separate controller on each of the memory die of the stack of memory die. At <NUM>, first memory operations of the first memory can be initiated and executed using only a first command/address bus of the first interface to identify the first memory operations. In certain examples, the first command address bus can be the row command address bus associated with, for example, high bandwidth memory devices. In some examples, the first memory operations do not include read operations or write operation. In some examples, the first memory operations include pre-charge operations, refresh operations, power down operations or combinations thereof.

At <NUM>, second memory operations of the first memory can be initiated and executed using only a second command/address bus of the first interface to identify the second memory access operation. In certain examples, the second command address bus can be the column command/address bus associated with, for example, high bandwidth memory devices. In some examples, the second memory operations include read operations or write operations. At <NUM>, a third memory access operation, of the second memory, such as an SRAM array of the logic die, can be initiated or executed using both the first command/address bus and the second command address bus to identify the third memory operation. In certain examples, the first memory can be a capacitive based random-access memory device such as a DRAM and the second memory can be SRAM. Having direct access to faster SRAM-type memory in a stacked DRAM storage system can provide opportunities for improved bandwidth of the storage system compared to conventional stacked DRAM memory or storage systems.

In certain examples, in addition to providing new commands for directly accessing, for example, SRAM device within a storage system including a stack of DRAM memory devices, and without violating standards for implementing stacked DRAM high bandwidth storage systems, the present subject matter can also allow internal data movement between the DRAM memory and the SRAM memory using a buffer of the logic die and the extended command truth table, instead of requiring the information to be transferred via the host interface bus. Such internal transfer commands can be implemented by setting a bit of the second command/address bus to a particular state on a second transition of a clock of the second command/address bus. In some examples, the bit to allow movement between memory and a buffer can be the C8 bit of the column command/address bus associated with high bandwidth memory devices.

In certain examples, modification of the command truth table for a stack of random access memory (RAM) as disclosed herein can allow direct access to a different type of RAM within a logic die of the stack, such as an SRAM memory in a stacked DRAM storage system and can provide specific commands to directly access and utilize the benefits of the SRAM. Such commands can allow for the ability of a memory controller to read or write the SRAM using the external data bus, read and write the SRAM using a buffer internal to the storage system, read and write the DRAM using the external bus, and read and write the DRAM using the buffer. In certain examples, commands that use the buffer as the data location do not affect the data bus of the channel (e.g., the external data bus) associated with the memory addressed in the command/operation and can allow the data bus to be used for other operations.

In certain examples, a storage system according to the present subject matter can provide an increase in bandwidth for high bandwidth memory without passing the stress of the bandwidth increase to for example, the performance limited conventional memory of a conventional high bandwidth device. In some examples, the bandwidth increase can be achieved without modification of the pinout of the existing high bandwidth memory package.

<FIG> illustrates generally a diagram of a system <NUM> including a device <NUM> that supports a storage system including stacked DRAM in accordance with aspects disclosed herein. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including memory controller <NUM>, memory cells <NUM>, basic input/output system (BIOS) component <NUM>, processor <NUM>, I/O controller <NUM>, peripheral components <NUM>, memory chip <NUM>, system memory controller <NUM>, encoder <NUM>, decoder <NUM>, and multiplexer <NUM>. These components may be in electronic communication via one or more busses (e.g., bus <NUM>). Bus <NUM>, for example, may have a bus width of <NUM> data lines ("DQ" lines). Bus <NUM> may be in electronic communication with <NUM> banks of memory cells.

Memory controller <NUM> or <NUM> may operate one or more memory cells as described herein. Specifically, memory controller may be configured to support flexible multi-channel memory. In some cases, memory controller <NUM> or <NUM> may operate a row decoder, column decoder, or both, as described with reference to <FIG>. Memory controller <NUM> or <NUM> may be in electronic communication with a host and may be configured to transfer data during each of a rising edge and a falling edge of a clock signal of the memory controller <NUM> or <NUM>.

Memory cells <NUM> may store information (i.e., in the form of a logical state) as described herein. Memory cells <NUM> may represent, for example, memory cells <NUM> described with reference to <FIG>. Memory cells <NUM> may be in electronic communication with memory controller <NUM> or <NUM>, and memory cells <NUM> and memory controller <NUM> or <NUM> may be located on a chip <NUM>, which may be one or several planar memory devices as described herein. Chip <NUM> may, for example, be managed by system memory controller <NUM> or <NUM>.

Memory cells <NUM> may represent a first array of memory cells with a plurality of regions coupled to a substrate. Each region of the plurality of regions may include a plurality of banks of memory cells and a plurality of channels traversing the first array of memory cells. At least one of the plurality of channels may be coupled to at least one region. Memory controller <NUM> or <NUM> may be configured to transfer data between the coupled region and the memory controller <NUM> or <NUM>.

BIOS component <NUM> be a software component that includes BIOS operated as firmware, which may initialize and run various hardware components. BIOS component <NUM> may also manage data flow between a processor and various other components, e.g., peripheral components, input/output control component, etc. BIOS component <NUM> may include a program or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a digital signal processor (DSP), a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller <NUM> or <NUM>. In other cases, a memory controller <NUM> or <NUM> may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting flexible multi-channel memory).

I/O controller <NUM> may utilize an operating system such as iOS®, ANDROID®, MS-DOS®, MS-WINDOWS®, OS/<NUM>®, UNIX®, LINUX®, or another known operating system. A user may interact with device <NUM> via I/O controller <NUM> or via hardware components controlled by I/O controller <NUM>.

Peripheral components <NUM> may include any input or output device, or an interface for such devices. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input <NUM> may represent a device or signal external to device <NUM> that provides input to device <NUM> or its components. This may include a user interface or an interface with or between other devices. In some cases, input <NUM> may be managed by I/O controller <NUM>, and may interact with device <NUM> via a peripheral component <NUM>.

Output <NUM> may also represent a device or signal external to device <NUM> configured to receive output from device <NUM> or any of its components. Examples of output <NUM> may include a graphics display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output <NUM> may be a peripheral element that interfaces with device <NUM> via peripheral component(s) <NUM>. Output <NUM> may be managed by I/O controller <NUM>.

System memory controller <NUM> or <NUM> may be in electronic communication with a first array of memory cells (e.g., memory cells <NUM>). A host may be a component or device that controls or directs operations for a device of which memory controller <NUM> or <NUM> and corresponding memory array are a part. A host may be a component of a computer, mobile device, or the like. Or device <NUM> may be referred to as a host. In some examples, system memory controller <NUM> or <NUM> is a GPU.

Encoder <NUM> may represent a device or signal external to device <NUM> that provides performs error correction encoding on data to be stored to device <NUM> or its components. Encoder <NUM> may write the encoded data to the at least one selected memory via the at least one channel and may also encode data via error correction coding.

Decoder <NUM> may represent a device or signal external to device <NUM> that sequences command signals and addressing signals to device <NUM> or its components. In some examples, memory controller <NUM> or <NUM> may be co-located within decoder <NUM>.

Multiplexer <NUM> may represent a device or signal external to device <NUM> that multiplexes data to device <NUM> or its components. Multiplexer <NUM> may multiplex the data to be transmitted to the encoder <NUM> and de-multiplex data received from the encoder <NUM>. A multiplexer <NUM> may be in electronic communication with the decoder <NUM>. In some examples, multiplexer <NUM> may be in electronic communication with a controller, such as system memory controller <NUM> or <NUM>.

The components of device <NUM> may include circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein. Device <NUM> may be a computer, a server, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a wearable electronic device, a personal electronic device, or the like. Or device <NUM> may be a portion or aspect of such a device. In some examples, device <NUM> is an aspect of a computer with high reliability, mission critical, or low latency constraints or parameters, such as a vehicle (e.g., an autonomous automobile, airplane, a spacecraft, or the like). Device <NUM> may be or include logic for artificial intelligence (AI), augmented reality (AR), or virtual reality (VR) applications.

In one example, a memory device may include an array of memory cells with a plurality of regions that may each may include a plurality of banks of memory cells, and a plurality of channels traversing the array of memory cells. Each of the channels may be coupled with a region of the array of memory cells and may be configured to communicate signals between the plurality of banks of memory cells in the region with a host device.

In some examples, the memory device may further include I/O areas extending across the array of memory cells, the I/O areas occupying an area of the array of memory cells that may be devoid of memory cells. In some examples of the memory device, the I/O areas may include TSVs configured to couple the array of memory cells with a power node or a ground node.

In some examples, the memory device may further include a plurality of channel interfaces distributed in the array of memory cells. In some examples of the memory device, the plurality of channel interfaces may be bump-outs. In some examples of the memory device, a channel interface of the plurality of channel interfaces may be positioned in each quadrant of the array of memory cells.

In some examples, the memory device may further include a plurality of signal paths extending between memory cells of the region and a channel interface associated with the region. In some examples of the memory device, the channel interface may be positioned in the array of memory cells to minimize a length of the signal paths.

In some examples, the memory device may further include a second array of memory cells stacked on top of the array of memory cells. In some examples of the memory device, the second array of memory cells may have regions that may each include a plurality of banks of memory cells. In some examples, the memory device may further include a second plurality of channels traversing the second array of memory cells. In some examples of the memory device, each of the channels of the second plurality of channels may be coupled with a second region of the second array of memory cells and may be configured to communicate signals between the plurality of banks of memory cells in the second region with the host device.

In some examples, the memory device may further include TSVs extending through the array of memory cells to couple the second array of memory cells with the second plurality of channels. In some examples of the memory device, a channel may establish a point-to-point connection between the region and the host device. In some examples of the memory device, each channel may include four or eight data pins. In some examples of the memory device, the region of the array of memory cells may include eight or more banks of memory cells.

In some examples, the memory device may further include an interface configured for bidirectional communication with the host device. In some examples of the memory device, the interface may be configured to communicate signals modulated using at least one of a NRZ modulation scheme or a PAM4 scheme, or both.

In one example, a memory device may include an array of memory cells with regions that each include a plurality of banks of memory cells, I/O areas extending across the array of memory cells, the I/O areas may include a plurality of terminals configured to route signals to and from the array of memory cells, and a plurality of channels positioned in the I/O areas of the array of memory cells, each of the channels may be coupled with a region of the array of memory cells and may be configured to communicate signals between the plurality of banks of memory cells in the region with a host device.

In some examples, the memory device may further include a plurality of channel interfaces positioned in the I/O areas of the array of memory cells, signal paths couple the regions with the plurality of channel interfaces. In some examples of the memory device, the I/O areas may include TSVs configured to couple a second array of memory cells stacked on top of the array of memory cells with a channel interface.

In some examples of the memory device, a channel interface of the region may be positioned within an I/O area that bisects the region serviced by the channel interface. In some examples of the memory device, the I/O areas may include TSVs configured to couple the array of memory cells with a power node or a ground node. In some examples of the memory device, the I/O areas may occupy an area of the array of memory cells that may be devoid of memory cells. In some examples of the memory device, the array of memory cells may be bisected by two I/O areas. In some examples of the memory device, the array of memory cells may be bisected by four I/O areas.

In one example, a system may include a host device, a memory device including a memory die with a plurality of regions that may each include a plurality of banks of memory cells, and a plurality of channels configured to communicatively couple the host device and the memory device, each of the channels may be coupled with a region of the memory die and may be configured to communicate signals between the plurality of banks of memory cells in the region with the host device.

In some examples, the system may include an interface configured for bidirectional communication with the host device. In some examples of the system, the interface may be configured to communicate signals modulated using at least one of a NRZ modulation scheme or a PAM4 scheme, or both. In some examples of the system, the host device may be an example of a GPU. In some examples of the system, the memory device may be positioned in a same package as the host device.

In one example, a memory device may include an array of memory cells with a plurality of regions that each include a plurality of banks of memory cells, and a plurality of channels traversing the array of memory cells, each of the channels may be coupled to at least one region of the array of memory cells and each channel may include two or more data pins and one or more command/address pin.

In some examples of the memory device, each channel may include two data pins. In some examples of the memory device, each channel may include one command/address pin. In some examples of the memory device, each region of the array may include four banks of memory cells. In some examples of the memory device, each channel may include four data pins. In some examples of the memory device, each channel may include two command/address pins. In some examples of the memory device, each region of the array may include eight banks of memory cells. In some examples of the memory device, each bank of memory cells may be contiguous with a channel.

In some examples of the memory device, a first set of banks of each plurality may be contiguous with a channel and a second set of banks of each plurality may be contiguous with another bank and non-contiguous with a channel. In some examples, the memory device may include <NUM> data pins and configured with a ratio of two, four, or eight data pins per channel.

In some examples, the memory device may include one, two, three, four, or six command/address pins per channel. In some examples, the memory device may include <NUM> data pins and configured with a ratio of two, four, or eight data pins per channel. In some examples, the memory device may include one, two, three, four, or six command/address pins per channel. In some examples of the memory device, the array may include a plurality of memory dice that each may include a plurality of channels.

In some examples of the memory device, each memory die of the plurality may be coupled with a different channel of the plurality of channels. In some examples, the memory device may include a buffer layer coupled with array. In some examples, the memory device may include an organic substrate underlying the array.

In some examples of the memory device, the array may be configured for a pin rate of <NUM>, <NUM>, <NUM>, or <NUM> Gbps. In some examples, the memory device may include an interface configured for bidirectional communication with a host device. In some examples of the memory device, the interface may be configured for at least one of a binary modulation signaling or pulse-amplitude modulation, or both.

In one example, a system may include at least one memory die that may include a plurality of regions that each may include a plurality of banks of memory cells, one or more channels associated with each memory die, each of the channels may be coupled to at least one region of the die of memory cells and each channel may include two or more data pins, and an organic substrate that underlies the memory die.

In some examples, the system may include a host device, and an interface configured for bidirectional communication with the host device, the interface supports at least one of a NRZ signaling or a PAM4, or both. In some examples of the system, the host device may include a GPU.

In some examples, the system may include a plurality of memory arrays that each may include <NUM> or <NUM> data pins and configured with a ratio of two, four, or eight data pins per channel. In some examples, the system may include a buffer layer positioned between the at least one memory die and the organic substrate.

As may be used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The may be used herein, the term "electronic communication" and "coupled" refer to a relationship between components that support electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

The term "layer" used herein refers to a stratum or sheet of a geometrical structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover some or all of a surface. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration. Those skilled in the art will, however, recognize that the layers are three-dimensional in nature.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

The term "isolated" refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. In some examples, the substrate may be an organic build up substrate formed from materials such as ABF or BT. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A transistor or transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

Claim 1:
A storage system (<NUM>, <NUM>) comprising:
a stack (<NUM>, <NUM>) of first memory die (<NUM>, <NUM>) configured to store data; and
a logic die (<NUM>, <NUM>) including an interface circuit (<NUM>) configured to receive multiple memory requests from an external host (<NUM>, <NUM>) using a first command bus, a second command bus, and a data bus, and a controller (<NUM>) configured to interface with the stack (<NUM>, <NUM>) of first memory die (<NUM>, <NUM>) to store and retrieve the data from the stack (<NUM>, <NUM>) of first memory die (<NUM>, <NUM>);
the storage device being characterized in that
the logic die (<NUM>, <NUM>) includes a second memory having a faster access time than devices of the stack (<NUM>, <NUM>) of first memory die (<NUM>, <NUM>); and
wherein the interface circuit (<NUM>) is configured to directly access the second memory in response to a first memory request of the multiple of memory requests,
wherein multiple selected bits of the first command bus are configured to provide at least a first command identifier upon a first transition of a clock signal of the first command bus, based on the state of each of the multiple selected bits; and
wherein the controller (<NUM>) is configured to directly access the second memory device in response to the first command identifier.