Patent Description:
Wireless communication devices and technologies are becoming ever more prevalent. Wireless communication devices generally transmit and receive communication signals. A communication signal is typically processed by a variety of different components and circuits. In some modern communication systems, a communication beam may be formed and steered in one or more directions. One type of beam steering system uses what is referred to as phased array, or phased array antenna system. A phased array may use a number of different elements and antennas where each element may process a transmit and/or receive signal that is offset in phase by some amount, leading to different elements of a phased array system processing slightly phase-shifted versions of a transmit and/or a receive signal. A phased array system may produce narrow, steerable, high power communication beams. A phased array antenna system may also form part of a massive multiple-input, multiple-output (MIMO) system. Attention is drawn to <CIT> describing a transformer-based antenna switching network which includes a transformer having a secondary winding that extends between a first terminal and a second terminal. The first terminal couples to ground through a first switch and connects to a first antenna. The second terminal couples to ground through a second switch and connects to a second antenna. Further attention is drawn to <CIT> describing a signal processing circuit which reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path. Attention is also drawn to a paper by<NPL>. A <NUM>-GHz transmitter (TX) and receiver (RX) front-ends in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers is presented in this paper. In order to mitigate undesired electromagnetic coupling through LC resonators in TX/RX and avoid severe metal density issue in highly scaled CMOS technology, Ka-band RF circuit design strategy using transmission line is studied. To improve the TX output power level, a power amplifier (PA) with <NUM>-way power splitter/combiner and transmission line for impedance transforming is introduced. The proposed TX and RX front-ends is designed and fabricated in a <NUM> CMOS technology. The measured TX output power is <NUM> dBm. The RX achieves a conversion gain of <NUM> dB. The TX occupies <NUM> <NUM> and consumes <NUM> mW. The RX occupies <NUM> <NUM> and consumes 72mW. Further attention is drawn to <CIT> describing a variable gain amplifier which includes a differential transistor pair including a first and second transistor. A variable resistor for setting a gain is connected between electrodes the transistor pair. A first variable capacitor is connected to an electrode of the first transistor, and a second variable capacitor is connected to an electrode of the second transistor. Corresponding to the gain setting set by adjusting the variable resistor, capacitance values of the variable capacitors can be adjusted to provide improved frequency characteristics of the variable gain amplifier. Attention is further drawn to <CIT> describing a system for split-frequency amplification, preferably including: one or more primary-band amplification stages, one or more secondary-band amplification stages, one or more band-splitting filters, and/or one or more signal couplers. An analog canceller including one or more split-frequency amplifiers. A mixer including one or more split-frequency amplifiers. A voltage-controlled oscillator including one or more split-frequency amplifiers. A method for split-frequency amplification, preferably including: receiving an input signal, separating the input signal into signal portions, and/or amplifying the signal portions, and optionally including combining the amplified signal portions and/or providing one or more output signals.

Further embodiments of the invention are described in the dependent claims.

Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein.

In the figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as "102a" or "102b", the letter character designations may differentiate two like parts or elements present in the same figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.

In a communication system that uses a phased array antenna system, it may be desirable to standardize the number of phased array elements which can be coupled to antennas in the phased array, support multiple power output configurations using a single radio frequency integrated circuit (RFIC), and/or support multiple device types, such as a user equipment (UE) and a customer premises equipment (CPE) using a single RFIC module. It may also be desirable to eliminate a power combiner between an RFIC and an antenna or an antenna array.

It is desirable to lower the cost of a communication device without compromising key performance indicators (KPIs). Further, it may be desirable to utilize a single chip or design across multiple devices and/or tiers of devices. Designs for different devices or tiers, however, may not always offer consistent advantages or benefits. For example, a premium tier communication device may use antennas to perform power combining, but a mid-tier communication device may use conductive power combining, for example such that fewer antennas are required, in order to reduce the overall size of the device. However, conductive power combining may degrade the transmit efficiency and the receive performance (such as the receiver noise figure (NF)) of the phased array element in some designs.

Therefore, it would be desirable to have a phased array element that can provide multiple power levels and that can be incorporated into a millimeter wave integrated circuit (mmWIC), for example such that consistent phased array elements may be implemented and/or different module sizes or number of antennas can be utilized across different communication devices. For example, a phased array element and antenna module incorporating the element can be configured to support both a high power (HP) mode for a mid-tier communication device and support a low power (LP) mode for a premium-tier communication device.

<FIG> is a diagram showing a wireless device <NUM> communicating with a wireless communication system <NUM>. The wireless communication system <NUM> may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, a <NUM> NR (new radio) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, <FIG> shows wireless communication system <NUM> including two base stations <NUM> and <NUM> and one system controller <NUM>. In general, a wireless communication system may include any number of base stations and any set of network entities.

The wireless device <NUM> may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device <NUM> may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, a device configured to connect to one or more other devices (for example through the internet of things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device <NUM> may communicate with wireless communication system <NUM>. Wireless device <NUM> may also receive signals from broadcast stations (e.g., a broadcast station <NUM>) and/or signals from satellites (e.g., a satellite <NUM> in one or more global navigation satellite systems (GNSS), etc). Wireless device <NUM> may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, <NUM>, <NUM>, etc..

The wireless communication system <NUM> may also include a wireless device <NUM>. In an exemplary embodiment, the wireless device <NUM> may be a wireless access point, or another wireless communication device that comprises, or comprises part of a wireless local area network (WLAN). In an exemplary embodiment, the wireless device <NUM> may be referred to as a customer premises equipment (CPE), which may be in communication with a base station <NUM> and a wireless device <NUM>, or other devices in the wireless communication system <NUM>. In some embodiments, the CPE may be configured to communicate with the wireless device <NUM> using WAN signaling and to interface with the base station <NUM> based on such communication instead of the wireless device <NUM> directly communicating with the base station <NUM>. In exemplary embodiments where the wireless device <NUM> is configured to communicate using WLAN signaling, a WLAN signal may include WiFi, or other communication signals.

Wireless device <NUM> may support carrier aggregation, for example as described in one or more LTE or <NUM> standards. In some embodiments, a single stream of data is transmitted over multiple carriers using carrier aggregation, for example as opposed to separate carriers being used for respective data streams. Wireless device <NUM> may be able to operate in a variety of communication bands including, for example, those communication bands used by LTE, WiFi, <NUM> or other communication bands, over a wide range of frequencies. Wireless device <NUM> may also be capable of communicating directly with other wireless devices without communicating through a network.

In general, carrier aggregation (CA) may be categorized into two types - intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.

<FIG> is a block diagram showing a wireless device <NUM> in which the exemplary techniques of the present disclosure may be implemented. The wireless device <NUM> may, for example, be an embodiment of the wireless device <NUM> illustrated in <FIG>.

<FIG> shows an example of a transceiver <NUM> having a transmitter <NUM> and a receiver <NUM>. In general, the conditioning of the signals in the transmitter <NUM> and the receiver <NUM> may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. These circuit blocks may be arranged differently from the configuration shown in <FIG>. Furthermore, other circuit blocks not shown in <FIG> may also be used to condition the signals in the transmitter <NUM> and receiver <NUM>. Unless otherwise noted, any signal in <FIG>, or any other figure in the drawings, may be either single-ended or differential. Some circuit blocks in <FIG> may also be omitted.

In the example shown in <FIG>, wireless device <NUM> generally comprises the transceiver <NUM> and a data processor <NUM>. The data processor <NUM> may include a processor <NUM> operatively coupled to a memory <NUM>. The memory <NUM> may be configured to store data and program codes shown generally using reference numeral <NUM>, and may generally comprise analog and/or digital processing components. The transceiver <NUM> includes a transmitter <NUM> and a receiver <NUM> that support bi-directional communication. In general, wireless device <NUM> may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver <NUM> may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc..

A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown in <FIG>, transmitter <NUM> and receiver <NUM> are implemented with the direct-conversion architecture.

In the transmit path, the data processor <NUM> processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter <NUM>. In an exemplary embodiment, the data processor <NUM> includes digital-to-analog-converters (DAC's) 214a and 214b for converting digital signals generated by the data processor <NUM> into the I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs 214a and 214b are included in the transceiver <NUM> and the data processor <NUM> provides data (e.g., for I and Q) to the transceiver <NUM> digitally.

Within the transmitter <NUM>, lowpass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from lowpass filters 232a and 232b, respectively, and provide I and Q baseband signals. An upconverter <NUM> having upconversion mixers 241a and 241b upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator <NUM> and provides an upconverted signal. A filter <NUM> filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) <NUM> amplifies the signal from filter <NUM> to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch <NUM> and transmitted via an antenna <NUM>. While examples discussed herein utilize I and Q signals, those of skill in the art will understand that components of the transceiver may be configured to utilize polar modulation.

In the receive path, antenna <NUM> receives communication signals and provides a received RF signal, which is routed through duplexer or switch <NUM> and provided to a low noise amplifier (LNA) <NUM>. The duplexer <NUM> is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA <NUM> and filtered by a filter <NUM> to obtain a desired RF input signal. Downconversion mixers 261a and 261b in a downconverter <NUM> mix the output of filter <NUM> with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator <NUM> to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by lowpass filters 264a and 264b to obtain I and Q analog input signals, which are provided to data processor <NUM>. In the exemplary embodiment shown, the data processor <NUM> includes analog-to-digital-converters (ADC's) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor <NUM>. In some embodiments, the ADCs 216a and 216b are included in the transceiver <NUM> and provide data to the data processor <NUM> digitally.

In <FIG>, TX LO signal generator <NUM> generates the I and Q TX LO signals used for frequency upconversion, while RX LO signal generator <NUM> generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase locked loop (PLL) <NUM> receives timing information from data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator <NUM>. Similarly, a PLL <NUM> receives timing information from data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator <NUM>.

In an exemplary embodiment, the RX PLL <NUM>, the TX PLL <NUM>, the RX LO signal generator <NUM>, and the TX LO signal generator <NUM> may alternatively be combined into a single LO generator circuit <NUM>, which may include common or shared LO signal generator circuitry to provide the TX LO signals and the RX LO signals. Alternatively, separate LO generator circuits may be used to generate the TX LO signals and the RX LO signals.

Wireless device <NUM> may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. Those of skill in the art will understand, however, that aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.

Certain components of the transceiver <NUM> are functionally illustrated in <FIG>, and the configuration illustrated therein may or may not be representative of a physical device configuration in certain implementations. For example, as described above, transceiver <NUM> may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver <NUM> is implemented on a substrate or board such as a printed circuit board (PCB) having various modules, chips, and/or components. For example, the power amplifier <NUM>, the filter <NUM>, and the duplexer <NUM> may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver <NUM> may be implemented in a single transceiver chip.

The power amplifier <NUM> may comprise one or more stages comprising, for example, driver stages, power amplifier stages, or other components, that can be configured to amplify a communication signal on one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier <NUM> can be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and can be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

In an exemplary embodiment in a super-heterodyne architecture, the filter <NUM>, PA <NUM>, LNA <NUM> and filter <NUM> may be implemented separately from other components in the transmitter <NUM> and receiver <NUM>, and may be implemented on a millimeter wave integrated circuit. An example super-heterodyne architecture is illustrated in <FIG>.

<FIG> is a block diagram showing a wireless device in which the exemplary techniques of the present disclosure may be implemented. Certain components, for example which may be indicated by identical reference numerals, of the wireless device 200a in <FIG> may be configured similarly to those in the wireless device <NUM> shown in <FIG> and the description of identically numbered items in <FIG> will not be repeated.

The wireless device 200a is an example of a heterodyne (or superheterodyne) architecture in which the upconverter <NUM> and the downconverter <NUM> are configured to process a communication signal between baseband and an intermediate frequency (IF). For example, the upconverter <NUM> may be configured to provide an IF signal to an upconverter <NUM>. In an exemplary embodiment, the upconverter <NUM> may comprise summing function <NUM> and upconversion mixer <NUM>. The summing function <NUM> combines the I and the Q outputs of the upconverter <NUM> and provides a non-quadrature signal to the mixer <NUM>. The non-quadrature signal may be single ended or differential. The mixer <NUM> is configured to receive the IF signal from the upconverter <NUM> and TX RF LO signals from a TX RF LO signal generator <NUM>, and provide an upconverted RF signal to phase shift circuitry <NUM>. While PLL <NUM> is illustrated in <FIG> as being shared by the signal generators <NUM>, <NUM>, a respective PLL for each signal generator may be implemented.

In an exemplary embodiment, components in the phase shift circuitry <NUM> may comprise one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor <NUM> over connection <NUM> and operate the adjustable or variable phased array elements based on the received control signals.

In an exemplary embodiment, the phase shift circuitry <NUM> comprises phase shifters <NUM> and phased array elements <NUM>. Although three phase shifters <NUM> and three phased array elements <NUM> are shown for ease of illustration, the phase shift circuitry <NUM> may comprise more or fewer phase shifters <NUM> and phased array elements <NUM>.

Each phase shifter <NUM> may be configured to receive the RF transmit signal from the upconverter <NUM>, alter the phase by an amount, and provide the RF signal to a respective phased array element <NUM>. Each phased array element <NUM> may comprise transmit and receive circuitry including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifters <NUM> may be incorporated within respective phased array elements <NUM>.

The output of the phase shift circuitry <NUM> is provided to an antenna array <NUM>. In an exemplary embodiment, the antenna array <NUM> comprises a number of antennas that typically correspond to the number of phase shifters <NUM> and phased array elements <NUM>, for example such that each antenna element is coupled to a respective phased array element <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> and the antenna array <NUM> may be referred to as a phased array.

In a receive direction, an output of the phase shift circuitry <NUM> is provided to a downconverter <NUM>. In an exemplary embodiment, the downconverter <NUM> may comprise an I/Q generation function <NUM> and a downconversion mixer <NUM>. In an exemplary embodiment, the mixer <NUM> downconverts the receive RF signal provided by the phase shift circuitry <NUM> to an IF signal according to RX RF LO signals provided by an RX RF LO signal generator <NUM>. The I/Q generation function <NUM> receives the IF signal from the mixer <NUM> and generates I and Q signals for the downconverter <NUM>, which downconverts the IF signals to baseband, as described above. While PLL <NUM> is illustrated in <FIG> as being shared by the signal generators <NUM>, <NUM>, a respective PLL for each signal generator may be implemented.

In some embodiments, the upconverter <NUM>, downconverter <NUM>, and the phase shift circuitry <NUM> are implemented on a common IC. In some embodiments, the summing function <NUM> and the I/Q generation function <NUM> are implemented separate from the mixers <NUM> and <NUM> such that the mixers <NUM>, <NUM> and the phase shift circuitry <NUM> are implemented on the common IC, but the summing function <NUM> and I/Q generation function <NUM> are not (e.g., the summing function <NUM> and I/Q generation function <NUM> are implemented in another IC coupled to the IC having the mixers <NUM>, <NUM>). In some embodiments, the LO signal generators <NUM>, <NUM> are included in the common IC. In some embodiments in which phase shift circuitry is implemented on a common IC with <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>, the common IC and the antenna array <NUM> are included in a module, which may be coupled to other components of the transceiver <NUM> via a connector. In some embodiments, the phase shift circuitry <NUM>, for example, a chip on which the phase shift circuitry <NUM> is implemented, is coupled to the antenna array <NUM> by an interconnect. For example, components of the antenna array <NUM> may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuitry <NUM> via a flexible printed circuit.

In some embodiments, both the architecture illustrated in <FIG> and the architecture illustrated in <FIG> are implemented in the same device. For example, a wireless device <NUM> or <NUM> may be configured to communicate with signals having a frequency below about <NUM> using the architecture illustrated in <FIG> and to communicate with signals having a frequency above about <NUM> using the architecture illustrated in <FIG>. In devices in which both architectures are implemented, one or more components of <FIG> and <FIG> that are identically numbered may be shared between the two architectures. For example, both signals that have been downconverted directly to baseband from RF and signals that have been downconverted from RF to baseband via an IF stage may be filtered by the same baseband filter <NUM>. In other embodiments, a first version of the filter <NUM> is included in the portion of the device which implements the architecture of <FIG> and a second version of the filter <NUM> is included in the portion of the device which implements the architecture of <FIG>.

<FIG> is a block diagram <NUM> showing in greater detail an embodiment of some of the components of <FIG>. In an exemplary embodiment, the upconverter <NUM> provides an RF transmit signal to the phase shift circuitry <NUM> and the downconverter <NUM> receives an RF receive signal from the phase shift circuitry <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> comprises an RF variable gain amplifier <NUM>, a splitter/combiner <NUM>, the phase shifters <NUM> and the phased array elements <NUM>. In an exemplary embodiment, the phase shift circuitry <NUM> may be implemented on a millimeter-wave integrated circuit (mmWIC). In some such embodiments, the upconverter <NUM> and/or the downconverter <NUM> (or just the mixers <NUM>, <NUM>) are also implemented on the mmWIC. In an exemplary embodiment, the RF VGA <NUM> may comprise a TX VGA <NUM> and an RX VGA <NUM>. In some embodiments, the TX VGA <NUM> and the RX VGA <NUM> may be implemented independently. In other embodiments, the VGA <NUM> is bidirectional. In an exemplary embodiment, the splitter/combiner <NUM> may be an example of a power distribution network and a power combining network. In some embodiments, the splitter/combiner <NUM> may be implemented as a single component or as a separate signal splitter and signal combiner. The phase shifters <NUM> are coupled to respective phased array elements <NUM>. Each respective phased array element <NUM> is coupled to a respective antenna element in the antenna array <NUM>. In an exemplary embodiment, phase shifters <NUM> and the phased array elements <NUM> receive control signals from the data processor <NUM> over connection <NUM>. The exemplary embodiment shown in <FIG> comprises a 1x4 array having four phase shifters <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n, four phased array elements <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n, and four antennas <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-n. However, a 1x4 phased array is shown for example only, and other configurations, such as 1x2, 1x6, 1x8, 2x3, 2x4, or other configurations are possible.

<FIG> is a block diagram of a phased array element <NUM> in accordance with an exemplary embodiment of the disclosure. In an exemplary embodiment, the phased array element <NUM> is an example of a single element that may be implemented in a phased array on a millimeter wave integrated circuit (mmWIC). The phased array element <NUM> may be an example of any of the phased array elements <NUM> from <FIG>, <FIG>.

In an exemplary embodiment, the phased array element <NUM> may comprise a transmit portion <NUM> and a receive portion <NUM>. In an exemplary embodiment, the transmit portion <NUM> may comprise a phase shifter <NUM>, a variable gain amplifier <NUM>, a variable capacitance <NUM>, one or more amplifier paths with exemplary amplifier path <NUM> and amplifier path <NUM> being shown for example, and a magnetic circuit <NUM>.

The phase shifter <NUM> may receive a transmit signal over connection <NUM> from a signal splitter, such as the splitter/combiner <NUM> of <FIG>. In an exemplary embodiment, the signal on connection <NUM> may be a radio frequency (RF) signal provided by a mixer circuit. In an exemplary embodiment, the phase shifter <NUM> may receive a control signal over connection <NUM> that controls the phase of the transmit signal provided over connection <NUM> to the VGA <NUM>. In an exemplary embodiment, the phase shifter <NUM> changes the phase of the signal on connection <NUM> by an amount that may be between <NUM> degrees and <NUM> degrees based on the control signal provided over connection <NUM>.

The exemplary embodiment shown in <FIG> is an example of the phase shifter being included in the phased array element <NUM> (<FIG>), and the phase shifter <NUM> is an exemplary embodiment of the phase shifter <NUM> (<FIG>).

The variable gain amplifier <NUM> may comprise one or more stages, with additional stages shown in dotted line. For example, at millimeter wave frequencies, multiple stages of a VGA may be used to generate the desired gain control and power control. In an exemplary embodiment, the VGA <NUM> may receive a control signal over connection <NUM> that controls the gain and power of the transmit signal provided over connection <NUM> to the amplifier path <NUM> and the amplifier path <NUM>.

In an exemplary embodiment, the amplifier path <NUM> may comprise a switch <NUM>, a driver amplifier <NUM>, and a power amplifier <NUM>. In an exemplary embodiment, the amplifier path <NUM> may comprise a switch <NUM>, a driver amplifier <NUM>, and a power amplifier <NUM>. In an exemplary embodiment, the switches <NUM> and <NUM> may receive a control signal over connection <NUM> that controls whether one or both of the amplifier path <NUM> and the amplifier path <NUM> are connected to the transmit signal on connection <NUM>.

In an exemplary embodiment, the magnetic circuit <NUM> comprises a transformer <NUM> and a transformer <NUM>. In an exemplary embodiment, the transformer <NUM> comprises a primary winding <NUM>, a secondary winding <NUM> and a tertiary winding <NUM>. In an exemplary embodiment, the transformer <NUM> comprises a primary winding <NUM>, a secondary winding <NUM> and a tertiary winding <NUM>.

In an exemplary embodiment, the secondary winding <NUM> of the transformer <NUM> and the secondary winding <NUM> of the transformer <NUM> are coupled together by a transformer segment <NUM>. In an exemplary embodiment, the transformer segment <NUM> may be selectively coupled to a system ground through a switch <NUM>. In an exemplary embodiment, the transformer segment <NUM> may be referred to as a common transformer segment because it forms part of the secondary winding <NUM> and the secondary winding <NUM>. In an exemplary embodiment, the switch <NUM> may receive a control signal over connection <NUM>. The secondary winding <NUM> of the transformer <NUM> may also be coupled to system ground over connection <NUM>. The secondary winding <NUM> of the transformer <NUM> may provide an output to an antenna element over connection <NUM>.

In an exemplary embodiment, the power amplifier <NUM> is coupled to the primary winding <NUM> and the power amplifier <NUM> is coupled to the primary winding <NUM>.

In an exemplary embodiment, the tertiary winding <NUM> of the first transformer <NUM> may be coupled to an AC ground over connection <NUM> and may be coupled to an impedance <NUM> over connection <NUM>.

In an exemplary embodiment, the receive portion <NUM> may comprise a low noise amplifier (LNA) <NUM>, which in an exemplary embodiment may be a two-stage LNA comprising LNA stage <NUM> and LNA stage <NUM>.

An output of the LNA <NUM> may be provided over connection <NUM> to a phase shifter <NUM>. The phase shifter <NUM> may provide a receive signal over connection <NUM> to a signal combiner, such as the splitter/combiner <NUM> of <FIG>. In an exemplary embodiment, the signal on connection <NUM> may be an RF signal provided to a mixer circuit. In an exemplary embodiment, the phase shifter <NUM> may receive a control signal over connection <NUM> that controls the phase of the receive signal provided over connection <NUM>.

In an exemplary embodiment, the tertiary winding <NUM> of the second transformer <NUM> may be coupled to an AC ground over connection <NUM> and may be coupled the LNA <NUM> over connection <NUM>. In an exemplary embodiment, the connection <NUM> may also provide a DC bias signal to bias the LNA stage <NUM> and to bias the LNA stage <NUM>.

In an exemplary embodiment, in a high power (HP) transmit (TX) mode, which is also referred to herein as a power combining mode, the switch <NUM> (S1) is conductive (i.e., is ON), the switch <NUM> (S2) is conductive (ON) and the switch <NUM> (S3) is non-conductive (i.e., is OFF). This configuration allows the power output of the power amplifier <NUM> and the power amplifier <NUM> to be combined at the secondary winding <NUM> and the secondary winding <NUM>, with the combined power being delivered to the connection <NUM> for transfer to an antenna element (not shown).

In an exemplary embodiment, the power amplifier <NUM> and the power amplifier <NUM> can be the same size or can be different sizes, and can have the same or different bias configuration, resulting in the same or different power levels. In an exemplary embodiment, the bias and size of the power amplifier <NUM> and power amplifier <NUM> can also be arranged so as to create a main and an auxiliary or peaking amplifier structure, respectively, for example to increase efficiency at power back-off. Similarly, the driver amplifier <NUM> and the driver amplifier <NUM> can be the same size or can be different sizes, and can have the same or different bias configuration, resulting in the same or different power levels.

In an exemplary embodiment, in a low power (LP) transmit (TX) mode, the switch <NUM> (S1) is non-conductive (i.e., is OFF), the switch <NUM> (S2) is conductive (ON) and the switch <NUM> (S3) is conductive (i.e., is ON). This configuration allows only a single amplifier path (amplifier path <NUM> in this example) to provide an output to the connection <NUM> for transfer to an antenna element (not shown). In the exemplary embodiment shown in <FIG>, the amplifier path <NUM> is enabled in TX LP mode because both the amplifier path <NUM> and the LNA <NUM> are coupled to the tertiary winding <NUM> of the second transformer <NUM>.

In an exemplary embodiment, the switchable control of the amplifier path <NUM> and the amplifier path <NUM> allows the phased array element <NUM> to provide a power output that may be increased by approximately 3dB compared to a phased array element having only a single amplifier path without compromising the power efficiency at back off power levels. Using one of the power amplifiers <NUM> and <NUM> to generate the desired power in LP mode, and using two power amplifiers <NUM> and <NUM> to generate the desired power (for example, approximately 3dB higher power than in LP mode) in HP mode instead of a single larger power amplifier allows efficient low power mode operation. For example, a larger power amplifier (for example, a single large power amplifier) operating in LP mode may suffer from inefficiency at the power backoff used for LP mode because the single large power amplifier may be operating at approximately 3dB more back off than its peak efficiency point. Moreover, the dual amplifier path architecture of the phased array element <NUM> increases the circuit area incrementally (e.g., by only approximately ~<NUM>% in some embodiments) compared to a phased array element having a single amplifier path because some of the other signal path components (e.g., the phase shifter, splitter/combiner, mixer, LO and IF circuitry) are shared. In an exemplary embodiment, the approximate 3dB higher power when the two power amplifiers <NUM> and <NUM> are active may be somewhat lower than 3dB due to losses resulting from power combining. For example, the combined power output when the two power amplifiers <NUM> and <NUM> are active may be, for example, approximately <NUM>. 5dB to approximately 3dB.

In an exemplary embodiment, in a receive (RX) mode, regardless of whether the transmit portion is in HP mode or LP mode, the switch <NUM> (S3) is conductive (ON), thus allowing only a single power amplifier (PA <NUM>) to influence the impedance at the input to the LNA <NUM> on connection <NUM>. When the switch <NUM> is conductive (ON), the secondary winding <NUM> of the transformer <NUM> is grounded to system ground such that no effect of any component in the amplifier path <NUM> appears on connection <NUM>. In this manner, the receive portion <NUM> maintains noise figure (NF) performance even with the arrangement that allows an approximate <NUM>. 5dB to approximate 3dB higher power to be provided by the dual amplifier paths <NUM> and <NUM> because the switch <NUM> (S3) can be non-conductive (OFF) when both amplifier paths <NUM> and <NUM> are providing power; and because the switch <NUM> (S3) can be conductive (ON) when one amplifier path (for example, amplifier path <NUM>) is providing power, and can be conductive (ON) when the receive portion <NUM> is enabled, thereby removing the loading of the power amplifier <NUM> from the input to the LNA <NUM> in RX mode. For example, because the transmit portion <NUM> and the receive portion <NUM> share the connection <NUM> to the antenna they naturally load each other, and if a higher power to be provided by the transmit portion <NUM> is desired, it may be necessary to increase the size of a power amplifier coupled to the antenna, which may increase the loading presented to the LNA <NUM> and degrade the noise figure (NF). By implementing the power amplifiers <NUM> and <NUM> and making the switch <NUM> (S3) conductive in RX mode, the LNA <NUM> will be exposed only to loading from the power amplifier <NUM>, thereby allowing the LNA <NUM> to maintain a higher NF than if exposed to both the loading of the power amplifier <NUM> and the power amplifier <NUM> or a single larger power amplifier.

In an exemplary embodiment, the impedance <NUM> acts as a termination impedance in TX HP mode, for example so that it is possible to use the same circuit architecture for the transformer <NUM> and for the transformer <NUM> for design re-use purposes and/or for balancing. Otherwise, the termination impedance <NUM> can be omitted leaving the connection <NUM> as an open circuit/floating winding, so that in TX HP mode, the connection <NUM> remains as high impedance and does not degrade the quality factor (Q) of the transformer <NUM> by generating eddy currents in the tertiary winding <NUM>. Alternatively, the transformer <NUM> can be implemented without the tertiary winding <NUM>.

In an exemplary embodiment, the phased array element <NUM> is depicted as performing a voltage combining operation; however, the phased array element <NUM> may also be configured for current combining, as will be described below.

In an exemplary embodiment, the variable capacitance <NUM> (C_match) maintains the frequency response at node <NUM> for two or more different transmit modes of operation. (i.e., HP mode where switch <NUM> and switch <NUM> are both ON, and LP mode where switch <NUM> is OFF and switch <NUM> is ON). In an exemplary embodiment, the variable capacitance <NUM> may be coupled to a control signal over connection <NUM> and may be adjusted to different values depending on whether one amplifier path (<NUM> or <NUM>) or both amplifier paths <NUM> and <NUM> are enabled and providing signal amplification.

In an exemplary embodiment, a single phase shifter <NUM> is used to drive both amplifier path <NUM> and amplifier path <NUM>. Thus, both power combining (HP) mode and the LP mode may use a single transmit phase shifter per phase array element. In an exemplary embodiment, a single output is provided to the antenna over connection <NUM>.

<FIG> is a block diagram of a millimeter wave (mmW) RF module <NUM> having a 1x8 phased array in accordance with an exemplary embodiment of the disclosure. Although the RF module <NUM> is illustrated and described as including a 1x8 phased array, other array configurations for the RF module <NUM> are possible. As used herein, the terms "module" and "RF module" refer to a hardware configuration that incorporates some or all of the RF components on a single substrate or structure, for example such that all components are included in a common package.

In an exemplary embodiment, the RF module <NUM> may comprise a millimeter wave integrated circuit (mmWIC) <NUM> (also referred to as a radio frequency integrated circuit (RFIC)), an antenna array <NUM>, a power management integrated circuit (PMIC) <NUM>, and a connector <NUM>.

In an exemplary embodiment, the mmWIC <NUM> may include a plurality of phased array elements, such as the phased array element <NUM> described in <FIG>. In the 1X8 phased array example shown in <FIG>, there are eight (<NUM>) phased array elements 300a, 300b, 300c, 300d, 300e, 300f, <NUM> and <NUM>. In some embodiments, the mmWIC <NUM> is coupled to a substrate and one or more of the antennas 300a-<NUM> is implemented on a surface and/or on one or more internal layers of the substrate in the module <NUM>.

In an exemplary embodiment, the mmWIC <NUM> may include the local oscillator generator circuit <NUM> and <NUM> (<FIG>), the upconverter <NUM> and the downconverter <NUM>. The upconverter <NUM> may be coupled to a signal connection <NUM>, which may be coupled to the splitter/combiner <NUM> (<FIG>), and the downconverter <NUM> may be coupled to a signal connection <NUM>, which may also be coupled to the splitter/combiner <NUM> (<FIG>) or to another combiner. For clarity of illustration, the signal connection <NUM> is shown with bold lines and the signal connection <NUM> is shown with non-bold lines. In an exemplary embodiment in a super-heterodyne architecture, the upconverter <NUM> may be configured to receive an output of the upconverter <NUM> (<FIG>) and the downconverter <NUM> may be configured to provide an output to the downconverter <NUM> (<FIG>). In a direct-conversion architecture, the LO generator circuit <NUM>/<NUM> may be implemented as described in <FIG> using the LO generator circuit <NUM>, the upconverter <NUM> may be implemented as described in <FIG> using the upconverter <NUM>, and the downconverter <NUM> may be implemented as described in <FIG> using the downconverter <NUM>.

In an exemplary embodiment, the phased array elements 300a through <NUM> are similar to the phased array element <NUM> of <FIG>. Further, the phased array element 300b is similar to the phased array element 300a, except that the phased array element 300b is a "mirror image" of the phased array element 300a. The phased array elements 300c, 300e and <NUM> may be similar to the phased array element 300a; and the phased array elements 300d, 300f and <NUM> may be similar to the phased array element 300b. Details of the phased array elements 300c, 300d, 300e, 300f, <NUM> and <NUM> are omitted for clarity of illustration.

In an exemplary embodiment, the phased array element 300a provides an output to an antenna <NUM> and the phased array element 300b provides an output to an antenna <NUM>. Similarly, the phased array element 300c provides an output to an antenna <NUM> and the phased array element 300d provides an output to an antenna <NUM>; the phased array element 300e provides an output to an antenna <NUM> and the phased array element 300f provides an output to an antenna <NUM>; and the phased array element <NUM> provides an output to an antenna <NUM> and the phased array element <NUM> provides an output to an antenna <NUM>.

In an exemplary embodiment, the PMIC module <NUM> provides and controls the power used by the components on the RF module <NUM> and the connector <NUM> couples the RF module <NUM> to other components in a communication device.

In an exemplary embodiment, fewer than all of the phased array elements within the mmWIC <NUM> may be coupled to an antenna element. For example, in a situation where TX HP mode may be used in a smaller module, for example a 1X4 phased array, then one or more of the total number of phased array elements on the mmWIC <NUM> may remain unconnected from an antenna element because fewer than all of the phased array elements on the mmWIC <NUM> can provide sufficient output power level for a particular application. For example, although the mmWIC <NUM> shown in <FIG> includes eight phased array elements 300a through <NUM>, in an application where a 1X4 phased array may be implemented, only phased array elements 300a, 300b, 300c and 300d may be coupled to respective antennas <NUM>, <NUM>, <NUM> and <NUM>. In such an implementation, as shown in <FIG>, the phased array elements 300e, 300f, <NUM> and <NUM> are shown as having dotted line connection to respective antennas <NUM>, <NUM>, <NUM> and <NUM> to indicate that the phased array elements 300e, 300f, <NUM> and <NUM> are not connected to respective antennas.

In an exemplary embodiment, a 1X4 phased array may be used for a UE and a 1X8 phased array may be used for a customer premises equipment (CPE). In this manner, the RF module <NUM> may be implemented in multiple applications, such as in a UE and in a CPE. Further, the same mmWIC <NUM> may be used in these various applications (e.g., in applications in which different numbers of antennas are coupled to the mmWIC <NUM>). Alternatively, all phased array elements may be coupled to respective antennas. In some embodiments in which fewer than all of the phased array elements <NUM> are coupled to an antenna element, at least one of the phased array elements which is coupled to an antenna operates in the HP mode. In some embodiments in which all of the phased array elements <NUM> are coupled to respective antennas, all of the phased array elements operate in the LP mode in certain scenarios, for example at least when transmitting from all of the antennas. For example, the phased array element 300a is shown with the switch 302a being conductive and the phased array element 300b is shown with the switch 302b being conductive, indicating that the phased array elements 300a and 300b are in LP TX mode.

<FIG> is a block diagram of a millimeter wave (mmW) RF module <NUM> having a 1x4 phased array in accordance with an exemplary embodiment of the disclosure. Although the RF module <NUM> is illustrated and described as a 1X4 phased array, other configurations for the RF module <NUM> are possible. Description of components which are numbered identical to components in <FIG> will not be repeated.

In an exemplary embodiment, the mmWIC <NUM> may include a plurality of phased array elements, such as the phased array element <NUM> described in <FIG>. In the 1X4 phased array example shown in <FIG>, there are four (<NUM>) phased array elements 300a, 300b, 300c and 300d.

In an exemplary embodiment, the phased array element 300a provides an output to an antenna element <NUM> and the phased array element 300b provides an output to an antenna element <NUM>. Similarly, the phased array element 300c provides an output to an antenna element <NUM> and the phased array element 300d provides an output to an antenna element <NUM>.

In an exemplary embodiment where TX HP mode may be used in a smaller module, the 1X4 phased array shown in <FIG> may be implemented. In an exemplary embodiment, the 1X4 phased array shown in <FIG> may be used for a UE and a 1X8 phased array may be used for a customer premises equipment (CPE). For example, the phased array element 300a is shown with the switch 302a being non-conductive and the phased array element 300b is shown with the switch 302b being non-conductive, indicating that the phased array elements 300a and 300b are in HP TX mode in the embodiments shown in <FIG>. In some such embodiments, the phased array elements 300d-<NUM> (<FIG>) are included in the mmWIC <NUM>, but are not connected to an antenna. In some of these embodiments, the mmWIC <NUM> may include all of the components which are included in the mmWIC <NUM>, but the two mmWICs may be configured differently (for example, certain connections such as the switches <NUM>, <NUM>, and/or <NUM> may be set differently) and coupled to a different number of antennas.

The configurations shown in <FIG> and <FIG> are examples only. Each of the phased array elements may operate in any of HP TX mode, LP TX mode and RX mode. Further all of these components may be included in a device without being packaged in a module. For example, the phased array elements could be coupled to a separate substrate on which the antennas are implemented instead of being coupled together with the antennas in a module.

<FIG> is a block diagram of a phased array element <NUM> configured in a HP TX mode in accordance with an exemplary embodiment of the disclosure. The phased array element <NUM> may be an example configuration of the phased array element <NUM>. The phased array element <NUM> illustrates that in a high power (HP) transmit (TX) mode, which is also referred to herein as a power combining mode, the switch <NUM> (S1) is conductive (i.e., is ON), the switch <NUM> (S2) is conductive (ON) and the switch <NUM> (S3) is non-conductive (i.e., is OFF). This configuration allows the power output of the power amplifier <NUM> and the power amplifier <NUM> to be combined and be delivered to the connection <NUM> for transfer to an antenna element (not shown). The LNA stage <NUM>, the LNA stage <NUM> and the phase shifter <NUM> are shown in phantom line to indicate that they are inactive in this mode.

<FIG> is a block diagram of a phased array element <NUM> configured in a LP TX mode in accordance with an exemplary embodiment of the disclosure. The phased array element <NUM> illustrates that in a low power (LP) transmit (TX) mode, the switch <NUM> (S1) is non-conductive (i.e., is OFF), the switch <NUM> (S2) is conductive (ON) and the switch <NUM> (S3) is conductive (i.e., is ON). The driver amplifier <NUM>, power amplifier <NUM>, transformer <NUM>, LNA stage <NUM>, the LNA stage <NUM> and the phase shifter <NUM> are shown in phantom line to indicate that they are inactive in this mode. This configuration allows only a single power amplifier (<NUM> in this example) to provide an output to the connection <NUM> for transfer to an antenna element (not shown).

<FIG> is a block diagram of a phased array element <NUM> configured in a RX mode in accordance with an exemplary embodiment of the disclosure. The phased array element <NUM> illustrates that in a receive (RX) mode, regardless of whether the transmit portion operates in HP mode or LP mode, the switches <NUM> and <NUM> are non-conductive (OFF), and the switch <NUM> (S3) is conductive (ON), thus allowing only a single power amplifier (PA <NUM>) to influence the impedance at the input to the LNA <NUM> on connection <NUM>. When the switch <NUM> is conductive (ON), the secondary winding <NUM> of the transformer <NUM> is grounded to system ground such that no effect of any component in the amplifier path <NUM> appears on connection <NUM>. In this RX mode, the driver amplifier <NUM>, power amplifier <NUM>, transformer <NUM>, driver amplifier <NUM>, and power amplifier <NUM>, and portions of transformer <NUM> are shown in phantom line to indicate that they are inactive in this mode. The transformer <NUM> is partially inactive in that it may be implemented as a tri-coil which is coupling the antenna on connection <NUM> to the LNA <NUM> in receive (RX) mode via secondary winding <NUM> and tertiary winding <NUM>, which act as a transformer for the receive (RX) mode In some embodiments, components which are described as being inactive (e.g., the LNA <NUM>, amplifiers in the transmit paths <NUM>, <NUM>, phase shifter <NUM>, etc.) may be disabled by coupling the component to a particular voltage (e.g., a certain bias or a ground).

<FIG> is a block diagram of a phased array element <NUM> in accordance with an exemplary embodiment of the disclosure. The phased array element <NUM> differs from the phased array element <NUM> shown in <FIG> in that the secondary windings <NUM> and <NUM> of the transformers <NUM> and <NUM>, respectively, are coupled in parallel. A switch <NUM> is located between transformer segment <NUM> and a transformer segment <NUM>, for example between respective connections <NUM> and <NUM>. In an exemplary embodiment, when the switch <NUM> is conductive, the transformer segment <NUM> and the transformer segment <NUM> may form a common transformer segment. The output connection <NUM> is also coupled to the connection <NUM>. The exemplary embodiment of the phased array element <NUM> shown in <FIG> performs similar functionality but uses current combining as opposed to voltage combining to combine the output of the amplifier path <NUM> with the output of the amplifier path <NUM>. In the phased array element <NUM>, the power amplifier <NUM> and the power amplifier <NUM> can be the same size or can be different sizes and can also have the same or different biases. The transformer <NUM> and the transformer <NUM> can also be similarly fabricated or can be optimized to different values. As described above with respect to <FIG>, the embodiment of the phased array element <NUM> can also be configured such that the power amplifier <NUM> acts as the main amplifier (for example, class-AB bias), while the power amplifier <NUM> acts as peaking/auxiliary amplifier (for example, class-C bias) or vice versa. Further, an optional inductor <NUM>, shown in dotted line, can be located across the switch <NUM> to improve the off isolation of the switch <NUM>, thus lowering the loading of the power amplifier <NUM> presented to the power amplifier <NUM> in LP TX mode as well as lowering the loading presented to the LNA <NUM> in RX mode.

In some embodiments, more than two amplifier paths are included in the phased array element <NUM>. For example, a third amplifier path may be selectively coupled to the VGA <NUM> in parallel with the paths <NUM>, <NUM>. Outputs of the third amplifier path may be coupled to a third transformer, which may be switchable coupled to the connection <NUM>, for example to selectively enable the third amplifier path to contribute to a signal output to the antenna on the output connection <NUM>.

<FIG> is a block diagram of a phased array element <NUM> in accordance with an exemplary embodiment of the disclosure. The phased array element <NUM> differs from the phased array element <NUM> shown in <FIG> in that the outputs of the power amplifier <NUM> and power amplifier <NUM> in the phased array element <NUM> are provided to respective bump transitions <NUM> and <NUM>. A bump transition refers to a connection that connects an integrated circuit (IC) package to a die, connecting a die-side bump (i.e., PA output pin) to a package ball in a ball grid array (BGA) IC package. This bump transition connection from the bump to the BGA ball can be customized in terms of inductance (L) and capacitance (C) to provide certain desired impedance at mm-wave frequencies for optimizing PA/LNA performance.

While bump transitions are not illustrated in the previous figures, they may be included (e.g., between the phased array elements and the antennas in <FIG> and <FIG>, or at the "To ANT" arrow in <FIG>, <FIG>, <FIG>, <FIG> and <FIG>. In some embodiments shown in <FIG>, <FIG>, <FIG>, <FIG> and <FIG>, there may be one bump transition per element, in contrast to the two bump transitions per element shown in <FIG>.

In this exemplary embodiment, an LNA <NUM> includes an LNA stage <NUM> that is coupled to connection <NUM> over connection <NUM>, and an LNA stage <NUM> that is coupled to connection <NUM> over connection <NUM>. The LNA stage <NUM> and the LNA stage <NUM> provide output to another LNA stage <NUM>.

In the exemplary embodiment shown in <FIG>, each amplifier path <NUM> and <NUM> has a separate output to a separate bump transition <NUM> and <NUM>, respectively. In this exemplary embodiment, each amplifier path can be separately enabled via switches <NUM> and <NUM>, and can also be configured to provide different power output levels, for example, a low power (LP) output via the bump transition <NUM> and a high power (HP) output via the bump transition <NUM>. In the exemplary embodiment shown in <FIG>, the power amplifier <NUM> may be implemented using a larger size device than the power amplifier <NUM>. For example, in an exemplary embodiment, a phased array element may be configured where the power amplifier <NUM> may be designed to have approximately 3dB higher power than the power amplifier <NUM>. However, due to operating losses, the power amplifier <NUM> may have an approximate <NUM>. 5dB to approximate 3dB higher power than the power amplifier <NUM>. Such a phased array may be optimized to deliver higher power so that fewer phased array elements <NUM> having the power amplifier <NUM> larger than the power amplifier <NUM> can be used to deliver an equivalent effective isotropic radiated power (EIRP) than a phased array having the power amplifier <NUM> configured similarly to the power amplifier <NUM>. For example, if the power amplifier <NUM> is designed to have approximately 3dB higher power than the power amplifier <NUM>, then a phased array size for phased array elements <NUM> having the power amplifier <NUM> with higher power than the power amplifier <NUM> may be 1X6 instead of 1X8 for a phased array element in which the power amplifier <NUM> is the same as the power amplifier <NUM>. This arrangement may sacrifice some efficiency because a larger phased array is generally more current efficient than a smaller phased array because gain is realized by spatial power combining. However, in some applications the size of the phased array may be more important than current efficiency due to cost reasons. In an exemplary embodiment, the LNA <NUM> can be separately optimized for the best noise figure for HP and LP TX mode. The architecture shown in <FIG> does not present any additional loading or loss because the switch <NUM> (<FIG>) or the switch <NUM> (<FIG>) is omitted.

In an exemplary embodiment, two transmit paths per phased array element are shown in <FIG>; however, there could be three (<NUM>) or more transmit paths (each coupled to a respective bump transition) to provide different power levels and/or accommodate different numbers of antennas. Similarly, a receive path could be coupled to each transmit path/bump transition such that three or more receive paths (e.g., including respective amplifiers outputting to the amplifier <NUM> or the phase shifter <NUM>) are implemented.

In the exemplary embodiments described herein with respect to <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG>, not all of the phased array elements in an integrated circuit (IC) need to be configured the same. For example, it may be desirable to have a low power (LP) path in every element, but if a high power (HP) path will typically be used when there are fewer antennas, then an HP path may be omitted in some of the phased array elements.

In an exemplary embodiment in which the phased array element <NUM> is connected to antennas, a number of the bump transitions may remain unconnected. For example, a manufacturer may choose which ones to use depending on what type of device is being implemented.

In some embodiments, regardless of how many paths are implemented in each phased array element, only a single TX phase shifter may be used and all of the RX paths may converge to a single RX phase shifter.

<FIG> and <FIG> are block diagrams collectively illustrating an exemplary embodiment of a millimeter wave (mmW) RF module in accordance with an exemplary embodiment of the disclosure.

<FIG> shows a side view of a millimeter wave (mmW) RF module <NUM>. The RF module <NUM> may be an example of the RF module <NUM> shown in <FIG>. In an exemplary embodiment, the RF module <NUM> may comprise a 1x8 phased array fabricated on a substrate <NUM>.

In an exemplary embodiment, the RF module <NUM> may comprise a mmWIC <NUM>, a PMIC <NUM>, a connector <NUM> and a plurality of antennas <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> fabricated on a substrate <NUM>.

<FIG> is a top perspective view of the RF module <NUM> showing the mmWIC <NUM>, a PMIC <NUM>, a connector <NUM> and a plurality of antennas <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> on the substrate <NUM>.

<FIG> is a bottom perspective view of the RF module <NUM> showing the antennas <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> on the substrate <NUM>.

<FIG> shows an alternative embodiment of a millimeter wave (mmW) RF module <NUM>. The RF module <NUM> may be similar to the RF module <NUM> shown in <FIG>, but is arranged as a 1x6 array. In an exemplary embodiment, the RF module <NUM> may comprise a 1x6 phased array fabricated on a substrate <NUM>.

In an exemplary embodiment, the RF module <NUM> may comprise a plurality of antennas <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> fabricated on the substrate <NUM>.

In an exemplary embodiment, every phase array element associated with each antenna <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> on the RF module <NUM> may be configured for an HP mode that delivers an approximately <NUM>. 5dB to 3dB higher power than in LP mode. In an exemplary embodiment, the mmWIC <NUM> may be used with the 1x6 array in the module <NUM>, and configured to operate in an HP mode as described. When the mmWIC <NUM> is used with the 1x8 configuration shown in <FIG>, in contrast, the mmWIC <NUM> may be configured to operate in the LP mode.

For example, a premium-tier communication device may provide the highest key performance indicators (KPIs) with the lowest possible current consumption, but the amount of circuit area consumed and cost may be less important comparatively. In a mid-tier communication device, it may be desirable to compromise current efficiency in pursuit of low circuit area and low cost. In terms of circuit area, the area refers to the area of the mmWIC and the area consumed by the mmWIC on the printed circuit board in the communication device. To reduce the module size in a mid-tier communication device, it would be desirable to have fewer phased array elements and antennas, but reducing the number of phased array elements and antennas without changing (increasing) the per element power may come at the expense of EIRP, which may not be acceptable in some situations/devices, as lower EIRP may reduce the cell coverage. Therefore, in a mid-tier communication device, the per phased array element power may be increased so that fewer antennas (which correspond to a smaller RF module) can be used while maintaining the same EIRP provided by a larger number of phased array elements where the per element power is not increased. In some such embodiments, the same mmWIC can be used in both the premium and mid tier devices because the area required may be dictated by the number of antennas. As can be seen in <FIG>, the area consumed by the mmWIC <NUM> is smaller than the area required for either <NUM> or <NUM> antennas and thus it may be sufficient to use the mmWIC for a module including either <NUM> or <NUM> (or another number, such as <NUM>) antennas. In other embodiments, a different mmWIC (for example, including less phased array elements) may be used for different module configurations. Regarding efficiency, building larger phased arrays for the same EIRP may be more current efficient compared to smaller phased arrays having higher per element power (such that a largely equivalent EIRP is achieved). This is because in an MxN phased array the TX mode power, EIRP, increases with the square of the number of elements (M×N)<NUM>, where MxN is the number of antennas). The EIRP increases with the square of the number of elements and provides the best efficiency in larger phased arrays. For example, MxN times per element DC /battery current expended results in (M×N)<NUM> radiated power (EIRP) increase. Having the ability to increase the per element power in the RF module without substantially compromising the efficiency for the lower power mode allows building RF modules having different sizes, while also providing substantially similar EIRP. For example, if the per element power can be increased by, for example, approximately <NUM>. 5dB (i.e., <NUM>. 78x) then the size of the phased array can be reduced from 1x8 to <NUM>×<NUM> (i.e., 8x8=6x6*<NUM>) to achieve a substantially equivalent EIRP. Although, such a 1x6 phased array may have lower receive sensitivity (RX EIS (Effective Isotropic Sensitivity)) than a 1x8 phased array, in almost all practical networks, coverage/cell size is limited by EIRP and not by EIS.

<FIG> is a flow chart <NUM> describing an example of the operation of a method for signal amplification. The blocks in the method <NUM> can be performed in or out of the order shown, and in some embodiments, can be performed at least in part in parallel.

In block <NUM>, a communication signal may be selectively amplified. For example, the phased array element <NUM> in <FIG> may amplify a communication signal using one or both of the first amplifier path <NUM> and the second amplifier path <NUM>, or the phased array element <NUM> of <FIG> may amplify a communication signal using the first amplifier path <NUM> or the second amplifier path <NUM>.

In block <NUM>, the amplified communication signal may be selectively combined for transmission in some embodiments. For example, in a HP TX mode, the output of the first amplifier path <NUM> and the output of the second amplifier path <NUM> in <FIG> may be combined by the transformer segment <NUM> while the switch <NUM> is non-conductive (OFF), so that the output of both the first amplifier path <NUM> and the output of the second amplifier path <NUM> are provided over connection <NUM> to an antenna element. In other embodiments, for example in the LP mode or when using the configuration in <FIG>, combination of the amplified signals is omitted.

In block <NUM>, a frequency response for one of the plurality of power levels is selectively maintained. For example, the variable capacitor <NUM> may be set or adjusted so that the frequency response of the phased array element <NUM> or <NUM> is maintained in a LP TX mode or in a HP TX mode.

<FIG> is a functional block diagram of an apparatus for signal amplification. The apparatus <NUM> comprises means <NUM> for selectively amplifying a communication signal. In certain embodiments, the means <NUM> for selectively amplifying a communication signal can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for selectively amplifying a communication signal may comprise the first amplifier path <NUM> and the second amplifier path <NUM>, and in some embodiments the switches <NUM>, <NUM>.

The apparatus <NUM> may also comprise means <NUM> for selectively combining the amplified communication signal for transmission. In certain embodiments, the means <NUM> for selectively combining the amplified communication signal for transmission can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an exemplary embodiment, the means <NUM> for selectively combining the amplified communication signal for transmission may comprise the circuit <NUM>.

The apparatus <NUM> also comprises means <NUM> for selectively maintaining a frequency response for each of the plurality of power levels. In certain examples, the means <NUM> for selectively maintaining a frequency response for each of the plurality of power levels can be configured to perform one or more of the functions described in operation block <NUM> of method <NUM> (<FIG>). In an example, the means <NUM> for selectively maintaining a frequency response for each of the plurality of power levels may comprise the variable capacitor <NUM>. For example, the variable capacitor <NUM> may be set or selectively adjusted so that the frequency response of the phased array element <NUM> is maintained in a LP TX mode or in a HP TX mode.

The circuit architecture described herein described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc..

An apparatus implementing the circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc..

Claim 1:
A phased array element (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a transmit portion (<NUM>) having a plurality of amplifier paths (<NUM>, <NUM>), each amplifier path having a driver amplifier (<NUM>, <NUM>) and a power amplifier (<NUM>, <NUM>);
a first transformer (<NUM>) coupled to the power amplifier (<NUM>) of a first amplifier path (<NUM>) of the plurality of amplifier paths and a second transformer (<NUM>) coupled to the power amplifier (<NUM>) of a second amplifier path (<NUM>) of the plurality of amplifier paths, a secondary winding (<NUM>, <NUM>) of each of the first transformer and the second transformer coupled together by a common transformer segment (<NUM>);
a transmit phase shifter (<NUM>) switchably coupled to the plurality of amplifier paths;
a receive portion (<NUM>) coupled to the second transformer, the receive portion having a receive path having a low noise amplifier, LNA (<NUM>); and
a receive phase shifter (<NUM>) coupled to the LNA;
wherein the first amplifier path is disabled, the second amplifier path is enabled and coupled to an antenna element, and the common transformer segment is coupled to a system ground; or
wherein both the first amplifier path and the second amplifier path are enabled and the common transformer segment is configured to combine the power of the first amplifier path and the second amplifier path.