Patent Description:
Embodiments presented in this disclosure generally relate the fabrication of a quantum dot layer, especially for producing a laser.

The cost of production and the physical properties of lasers are directly influenced by the materials and methods used in producing those lasers. The choices made in the production methods and construction materials not only affect the yield for a given batch of lasers, but affect the size that batches may be. As a result, lasers are often produced on specialized equipment and in smaller batches than other electrical or optical components. Additionally, due to material differences in the laser from the other components, special techniques and materials are often used to integrate the lasers with other electrical or optical components to create a final assembly, which the other components do not require to integrate with one another, further adding to the costs of production. <CIT> is directed to a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

Presented in this disclosure is a method according to claim <NUM>.

A wafer may be provided, comprising a silicon substrate, a base layer of a predetermined thickness of a III-V semiconductor material bonded with the silicon substrate, and at least one layer grown on the base layer to form a plurality of quantum dot lasers.

Also, there may be provided a laser that comprises a silicon substrate having an upper side and an underside opposite to the upper side, a III-V semiconductor material layer, bonded with the upper side of the silicon substrate, a quantum dot layer included in one or more layers grown from the III-V semiconductor material layer at a predetermined height relative to the upper side of the silicon substrate, and wherein the underside of the silicon substrate includes a plurality of assembly features defined on the silicon substrate as a wafer-level feature.

Also, there may be provided an apparatus, comprising a silicon substrate, a quantum dot laser comprising: a base layer of a III-V semiconductor material, bonded with the silicon substrate and at least one layer grown epitaxially from the base layer, wherein the at least one layer comprises a quantum dot layer, and a photonic element, fabricated on the silicon substrate and including a waveguide optically aligned with the quantum dot layer.

Additionally, there may be provided a method of forming a photonic apparatus comprising bonding a sheet of a III-V semiconductor material with a substrate, forming a base layer of the III-V semiconductor material with a predetermined thickness by removing excess III-V semiconductor material bonded with the substrate, and after removing the excess III-V semiconductor material, epitaxially growing a quantum dot layer above the base layer, wherein the quantum dot layer is arranged at a predetermined height relative to the substrate, and fabricating a photonic element on the substrate, wherein a waveguide of the photonic element is optically aligned with the quantum dot layer according to the predetermined height.

Furthermore, a method of forming a photonic apparatus may be provided, comprising growing, from a base layer bonded to a silicon substrate, at least one layer comprising a quantum dot layer, fabricating a first photonic element to the silicon substrate in optical alignment with the quantum dot layer to form a laser submount, and using the silicon substrate as a reference surface, mounting the laser submount to a dielectric layer of an integrated circuit including a second photonic element.

A method of creating a laser may comprise bonding a III-V semiconductor material with a silicon substrate, removing excess III-V semiconductor material bonded with the substrate to leave a III-V semiconductor material base layer of a predetermined thickness bonded with the substrate, and after removing the excess III-V semiconductor material, epitaxially growing at least one layer on the III-V semiconductor material base layer, the at least one layer comprising a quantum dot layer.

A laser may comprise a silicon substrate having an upper surface with a base layer bonded with the upper surface of the silicon substrate, the base layer comprising a III-V semiconductor material and one or more layers grown on the base layer, the one or more layers comprising: a matrix layer, grown from the base layer, comprising a lattice-matched III-V semiconductor material to the III-V semiconductor material, a quantum dot layer, grown within the matrix layer; and a contact layer, grown from the matrix layer, comprising the III-V semiconductor material, wherein the contact layer is separated from the base layer by the matrix layer.

A laser may comprise a quantum dot layer positioned with a predefined height above an upper surface of a silicon substrate, a base layer of a III-V semiconductor material, the base layer bonded with the upper surface of the silicon substrate, and a cladding layer of a lattice-matched III-V semiconductor material that is grown from the base layer, wherein the quantum dot layer is included in a waveguide of the cladding layer.

Silicon (Si) photonic applications often use Quantum Well (QW) based lasers that are based on small-size (e.g., <NUM> diameter and less) indium phosphide (InP) substrates. These InP-based QW lasers often have limited operating temperature ranges, greater back-reflection sensitivity, and limited gain bandwidth when compared to Quantum Dot (QD) lasers. Additionally, InP substrates tend to be more brittle and are less thermally conductive than Si substrates, leading to the use of smaller-sized substrates and worse heat-sinking performance for components that are InP-based. Additionally, the differences in coefficients of thermal expansion between InP and Si makes strain management during production and later use challenging.

Most efforts to date to integrate QW or QD lasers onto Si Photonic platforms bond lasers grown on InP or Gallium-Arsenide (GaAs) substrates to a Si substrate. Efforts to directly grow QD lasers onto Si photonics platforms have not been cost effective, due in part to the use of larger wafers (e.g., <NUM>-<NUM>) having a small ratio of III-V semiconductor material to wafer area, and laser yield losses also resulting in the loss of Si photonic dies.

Instead, as is discussed herein in greater detail with regard to the Figures, growing QD lasers on a thin film of III-V semiconductor material bonded with a Si substrate, provides lasers that have superior physical properties, greater ease of manufacture, and/or greater production yields than InP-based QW lasers or QW/QD lasers grown from Si substrates.

<FIG> illustrate various views of an exemplary fabrication process of QD laser assemblies using a thin film of III-V semiconductor material bonded with a Si substrate, according to one or more embodiments herein. <FIG> illustrates a first state of fabrication <NUM>, in which a wafer <NUM> is bonded with a sheet <NUM> that is made of a III-V semiconductor material. As is shown in <FIG>, the sheet <NUM> may be bonded directly to the wafer <NUM>, however, in an optional first state of fabrication <NUM> shown in <FIG>, an intermediate layer <NUM> is disposed between the wafer <NUM> and the sheet <NUM> and operates to bond the wafer <NUM> and the sheet <NUM> together.

The wafer <NUM> comprises a Si substrate from which various optical and electrical components may be grown or eutectically bonded. In some embodiments, the Si substrate of the wafer <NUM> is a bulk Si substrate in which one or more features or materials for the optically active device to be produced (e.g., a laser, detector, modulator, absorber) have been pre-processed. In various embodiments, the diameter of the wafer <NUM> may range between about <NUM> millimeters (mm) and about <NUM>, and its thickness may range between about <NUM> and about <NUM>, but the dimensions of the wafer <NUM> may be changed to account for new diameters and thicknesses desired in Si fabrication industries.

The sheet <NUM> may be bonded directly (per <FIG>) with the wafer <NUM>, or may be bonded indirectly (per <FIG> and <FIG>) with the wafer <NUM>. The diameter of the sheet <NUM> may be based on the diameter of the wafer <NUM> (e.g., within +/- <NUM>% of the wafer diameter), but the thickness of the sheet <NUM> may vary independently of the thickness of the wafer <NUM> (i.e., either thicker or thinner than the wafer <NUM>). In some embodiments, the diameter of the sheet <NUM> is independent from the diameter of the wafer <NUM>; for example, several small sheets <NUM> may be bonded with a wafer <NUM> having a much larger diameter (e.g., several <NUM> sheets <NUM> bonded with a <NUM> wafer <NUM>). Various methods of bonding the sheet <NUM> with the wafer <NUM> may be used, which will be familiar to those of ordinary skill in the art, and that may differ based on the particular III-V semiconductor material that comprises the sheet <NUM> and whether an intermediate layer <NUM> is used. Various III-V semiconductor materials are used in different embodiments to comprise the sheet <NUM>, which include a material selected from the Boron group (i.e., a group III material: Boron, Aluminum, Gallium, Indium, Thallium) and a material selected from the Nitrogen group (i.e., a group V material: Nitrogen, Phosphorus, Arsenic, Antimony, Bismuth), such as, for example: Boron-Nitride (BN), Gallium-Nitride (GaN), Gallium-Arsenide (GaAs), and Indium-Phosphide (InP).

In some embodiments, the intermediate layer <NUM> (when used) may be sized with a diameter that substantially matches (e.g., +/- <NUM>%) the diameter of the wafer <NUM>. In some embodiments, the thickness of the intermediate layer <NUM> may vary between about <NUM> nanometers (nm) and about <NUM>. Various materials for an intermediate layer <NUM> may be used in different embodiments, such as, for example, a dielectric such as silicon dioxide (SiO<NUM>), a polymer, a metal, or a semiconductor. One of ordinary skill in the art will be familiar with suitable materials that may be used as an intermediate layer <NUM>.

Additionally, any of the III-V semiconductor material, the material of the intermediate layer <NUM>, and the wafer <NUM> may be doped with various other materials to affect their physical and/or electrical properties. For example, Si, C, Zn, Ge, Sn, Cd, S, Se, Te, Be, Mg, and other impurities may be used to dope the III-V semiconductor material for use as an electron emitter or electron collector when used in a semiconductor component. The III-V semiconductor material used in the sheet <NUM> is doped prior to bonding with the wafer <NUM>. In another example, B and P may be used as dopants for the wafer <NUM>.

<FIG> illustrates a second state of fabrication <NUM> advancing from the first state of fabrication <NUM>, in which the sheet <NUM> has been directly bonded to the wafer <NUM>. <FIG> illustrates an optional second state of fabrication <NUM> advancing from the optional first state of fabrication <NUM>, in which the sheet <NUM> has been bonded indirectly with the wafer <NUM> via the intermediate layer <NUM>.

<FIG> illustrates a third state of fabrication <NUM>, advancing from either the second state of fabrication <NUM> or the optional second state of fabrication <NUM>, in which the sheet <NUM> is separated from the wafer <NUM> to produce a base layer <NUM> of a thin film of the III-V semiconductor material that is bonded with the wafer <NUM> and excess material <NUM> that has been removed from the wafer <NUM>. The base layer <NUM> comprises a predetermined thickness of the selected III-V semiconductor material, such as, for example, a base layer <NUM> that is between about <NUM> and about <NUM> thick. In embodiments that use an intermediate layer <NUM>, the intermediate layer <NUM> is included within the base layer <NUM>. The excess material <NUM> comprises the material of the sheet <NUM> that is not left bonded with the wafer <NUM> once separated. In different embodiments, the excess material <NUM> of the sheet <NUM> is removed from the wafer <NUM> using chemical means, mechanical means, or a combination thereof, such as, for example, the SMART CUT® process described in <CIT>. Once the excess material <NUM> has been separated from the wafer <NUM>, it may then be re-processed and recycled to produce a new sheet <NUM> that is then used to bond with additional wafers <NUM>.

<FIG> illustrates a fourth state of fabrication <NUM> advancing from the third state of fabrication <NUM>, in which epitaxial growth processes <NUM> are applied to the base layer <NUM>. In various embodiments, various additional layers of a QD laser are grown from the base layer <NUM> via epitaxial growth processes <NUM> known to a person of ordinary skill in the art. Some non-limiting examples of epitaxial growth processes <NUM> include Chemical Vapor Deposition (CVD), Metal-Organic CVD (MOCVD), Molecular Beam Epitaxy (MBE), Vapor-Phase Epitaxy (VPE), Liquid-Phase Epitaxy (LPE), Solid-Phase Epitaxy (SPE), Hydride Vapor Phase Epitaxy, etc..

<FIG> illustrates a fifth state of fabrication <NUM> advancing from the fourth state of fabrication <NUM>, in which several layers grown from the base layer <NUM> are shown as strata in cross-section. As will be appreciated, the individual and relative heights/thicknesses of the strata and their associated layers shown in the fifth state of fabrication <NUM> are provided as non-limiting examples; one of ordinary skill in the art will be able to adjust the heights/thicknesses of the layers to fabricate a QD laser to meet the needs of individual applications. As shown in detail <NUM>, a matrix layer <NUM>, a waveguide layer <NUM>, a quantum dot layer <NUM>, and a contact layer <NUM> have been grown from the base layer <NUM>. In cross section (see also <FIG>), the wafer <NUM> defines a silicon stratum <NUM>, the base layer <NUM> defines a first III-V semiconductor material stratum <NUM>, the matrix layer <NUM> defines a first cladding stratum <NUM> and a second cladding stratum <NUM>, the waveguide layer <NUM> defines a first waveguide stratum <NUM> and a second waveguide stratum <NUM>, the quantum dot layer <NUM> defines a quantum dot stratum <NUM>, and the contact layer <NUM> defines a second III-V semiconductor material stratum <NUM>.

The matrix layer <NUM>, also referred to as a cladding layer, comprises a lattice-matched material to the III-V semiconductor material that is used for the base layer <NUM>. For example, AlGaAs may be used for the matrix layer <NUM> when GaAs is used for the base layer <NUM>. Other example lattice-matched materials include, but are not limited to: InGaP with GaAs and AlGaInAs, AllnAs, InGaAs, GaAsSb, InGaAsP with InP. One of ordinary skill in the art will be able to select a lattice-matched material for use with the selected III-V semiconductor material for the base layer <NUM>.

In some embodiments, the matrix layer <NUM> comprises one layer epitaxially grown around the waveguide layer <NUM> and the quantum dot layer <NUM>. In other embodiments, the matrix layer <NUM> comprises two layers; one grown from the base layer <NUM> and one grown from the second waveguide stratum <NUM> of the waveguide layer <NUM>.

The waveguide layer <NUM> comprises a III-V semiconductor material that is grown to surround the quantum dot layer <NUM> and provides a structured gain medium in which the light produced by the quantum dot layer <NUM> is amplified and directed outward from the quantum dot layer <NUM> in one or more directions. In several embodiments, the III-V semiconductor material that comprises the waveguide layer <NUM> is the same as the III-V semiconductor material of the base layer <NUM>, but may also be made of different III-V semiconductor materials (e.g., AlGaAs when GaAs used for the base layer <NUM>) or doped with different (or no) dopants than the base layer <NUM>. In some embodiments, the waveguide layer <NUM> comprises one layer epitaxially grown around the quantum dot layer <NUM>. In other embodiments, the waveguide layer <NUM> comprises two layers; one grown from the first stratum <NUM> of the matrix layer <NUM> and one grown from the quantum dot layer <NUM>.

The quantum dot layer <NUM> includes a plurality of quantum dots that, when stimulated by an applied electrical current, emit photons. Quantum dots are nanostructures that exhibit various properties, such as light generation, based on quantum mechanical effects. Quantum Wells are two-dimensional structures formed by a thin layer of a first material surrounded by wider-bandgap material and that only allow electronic capture in one dimension (allowing planar two-dimensional movement). In contrast, Quantum Dots act as zero-dimensional entities that are embedded in the waveguide layer <NUM>, which enables three-dimensional capture of excited electrons (not allowing movement), The Quantum Dots are surrounded by the waveguide layer <NUM> and are made of materials that have narrower bandgaps than the material of the waveguide layer <NUM>. As will be appreciated, the precise size, shape, and material of the quantum dots will affect the color produced by the laser.

The contact layer <NUM> is made from a III-V semiconductor material, which in some (but not all) embodiments is the same III-V semiconductor material used in the base layer <NUM>, but is doped differently than the base layer <NUM> to form an opposing semiconductor material. When the base layer <NUM> is p-doped, the contact layer <NUM> is n-doped and vice versa. The contact layer <NUM> forms the most distal layer from the wafer <NUM>, and along with the base layer <NUM> surrounds the quantum dot layer <NUM>, the waveguide layer <NUM>, and the matrix layer <NUM>. When sufficient voltage is applied across the contact layer <NUM> and the base layer <NUM>, a current will flow through the quantum dot layer <NUM> and produce a laser beam.

As will be appreciated, various additional processes may be applied to etch the layers into a desired shape or profile, add one or more photonic elements, and/or process the QD laser, which are discussed in greater detail elsewhere in the present disclosure. Similarly, various wafer processes may be performed on the wafer <NUM> prior to or after bonding and/or growing the layers, such as, for example, the inclusion of through-silicon vias (TSV), alignment features, dicing the wafer <NUM> into individual components, etc., which are discussed in greater detail elsewhere in the present disclosure.

<FIG> illustrates a flow chart outlining general operations in an example method <NUM> to produce a QD laser assembly, according to one or more embodiments disclosed herein. Method <NUM> begins with OPERATION <NUM>, where a III-V semiconductor material is bonded with a Si substrate. In some embodiments, the III-V semiconductor material is bonded directly to the Si substrate, while in other embodiments an intermediate bonding layer is used between the III-V semiconductor material and the Si substrate, such as in <FIG> and <FIG> respectively.

Method <NUM> proceeds to OPERATION <NUM>, where excess III-V semiconductor material is removed from the substrate to leave a thin film of III-V semiconductor material bonded with the Si substrate, such as is shown in <FIG>. In various embodiments, the thin film is doped with a first dopant material for use as an anode or as a cathode in a semiconductor device.

After the excess III-V semiconductor material is removed, at least one layer is epitaxially grown on the thin film of III-V semiconductor material at OPERATION <NUM>, such as is shown in <FIG>. The at least one layer includes a layer of quantum dots, and may also include layers of a material that is lattice matched with the III-V semiconductor material of the thin film, layers of a III-V semiconductor material that form a waveguide for the quantum dots, and a second layer of a III-V semiconductor material doped with a second dopant material for use as a cathode (when the thin film is an anode) or as an anode (when the thin film is a cathode).

At OPERATION <NUM>, the layers are etched to produce a predetermined profile or shape for the laser being fabricated. Etching to remove material from the grown layers may be done using chemical means, mechanical means, or a combination thereof according to various embodiments. Various steps of etching are illustrated and discussed in greater detail in regards to <FIG>.

In some embodiments, etching is also applied to the Si substrate to produce various assembly features, although the Si substrate may be etched separately from the layers; either before or after the layers are etched. One example of an assembly feature is a through-silicon via (TSV), which defines a through-hole in the Si substrate and through which an electric contact is run the underside of the Si substrate to one or more layers grown on the top side of the Si substrate. A second example of an assembly feature is an alignment feature defined on the underside of the Si substrate, which allows for integrated circuit masks to be applied consistently to the to the Si substrate in relation to the layers on the opposite side, and for the mechanical positioning or manipulation of the component, among other benefits.

Metallization occurs at OPERATION <NUM>, where electrical contacts made from a metallic conductor (e.g., gold, silver, copper, platinum) are attached to the Si substrate and various layers of the laser so that a current will flow between the contacts through the QD layer to produce a laser beam when an appropriate voltage is applied to the electrical contacts. <FIG> illustrate example electrical contacts positioned relative to the example layers, and the related discussion covers the metallization process in greater detail.

Proceeding to OPERATION <NUM>, the layers of the laser assembly are passivated to protect them from corrosion, stray voltages, stray contaminants, and/or to avoid or distribute mechanical stresses. In various embodiments, a layer of Silicon Dioxide (SiO<NUM>) is applied to the layers for passivation. The passivation coating may be grown from the Si substrate and layers, deposited thereon, or a combination of initial growth and subsequent deposition may be used.

At least one photonic element is fabricated onto the substrate of the assembly at OPERATION <NUM> using various standard etching, deposition, lithography, etc. steps. In various embodiments, the photonic element fabricated onto the Si substrate may be any one of the example photonic elements <NUM> illustrated in <FIG>, or another photonic element known to one of ordinary skill in the art. How an individual photonic element is fabricated onto the Si substrate may vary in different embodiments based on the materials of the photonic element, the size/shape of the photonic element, and its intended use profile. One of ordinary skill in the art will be familiar with various schemes for fabricating a photonic element onto a Si substrate.

The Si substrate is diced into individual components at OPERATION <NUM>. As will be appreciated, several components are fabricated on one substrate (e.g., a wafer <NUM>) that are separated from one another to produce several individual copies of the component (e.g., dies). Dicing may be done via a mechanical saw or laser cutting, and may involve several machines to separate the dies from one another or leftover portions of the substrate.

Various tests may be performed at the wafer level prior to dicing the wafer <NUM> into the individual dies. Example tests include, but are not limited to: device burn-in, wavelength characterization, light-current-voltage characterization, threshold measurements, wafer maps, photoluminescence, process monitoring, physical dimensions, etc..

Proceeding to OPERATION <NUM>, individual dies, including the laser and any photonic elements bonded with one Si substrate may be mounted to another integrated circuit. Examples of other integrated circuits, and various schemes of mounting the assembly thereto are discussed in greater detail in regard to <FIG>.

<FIG> illustrate various views of an individual die of a QD laser produced according to one or more embodiments disclosed herein.

<FIG> illustrates a top-frontal isometric cutaway view <NUM> of the internal layering of a QD laser submount <NUM>. The QD laser submount <NUM> is a discrete semiconductor component, which may include one or more pre-fabricated optical components (e.g., photonic elements <NUM>) that are co-bonded with the substrate for use as part of a larger photonic circuit (discussed in greater detail in regards to <FIG>) or as a discrete lasing component.

As illustrated, a first TSV 320a and a second TSV 320b (collectively or generically, TSV <NUM>) extend from a bottom surface <NUM> of the substrate <NUM> to an upper surface <NUM> of the substrate <NUM>. The dielectric <NUM> and the semiconductor layers <NUM> of the QD laser are bonded to the upper surface <NUM>. In some embodiments, the TSVs <NUM> also extend through the dielectric <NUM>. In some embodiments, the dielectric <NUM> comprises a silicon oxynitride (SiON) material, although other material(s) are also possible. As will be appreciated, the semiconductor layers <NUM> include the base layer <NUM>, the matrix layer <NUM>, the waveguide layer <NUM>, the QD layer <NUM>, and the contact layer <NUM>. In some embodiments, the QD layer <NUM> within the semiconductor layers <NUM> relative to the upper surface <NUM> of the substrate <NUM> is formed at a predefined height so that the QD layer <NUM> can be aligned with any optical components that are bonded with the substrate <NUM> and/or that the QD laser submount <NUM> is mated with by using the upper surface <NUM> as a reference surface for the optical components.

A first electrical lead 330a and a second electrical lead 330b (collectively or generically, electrical leads <NUM>) extend, respectively, from the first TSV 320a and the second TSV 320b to various layers of the semiconductor layers <NUM>. The electrical leads <NUM> are held within the dielectric <NUM> used to passivate the QD semiconductor layers <NUM>, and make contact with various layers of the semiconductor layers <NUM> (e.g., base layer <NUM>, matrix layer <NUM>, contact layer <NUM>) to form a voltage pathway running through the QD layer <NUM> thereof. As illustrated, the electrical leads <NUM> extend electrical communication to the semiconductor layers <NUM> from contacts made outside of the substrate <NUM> via pads 360a-d (collectively, pads <NUM>) that provide areas onto which wires or other components may be soldered, brazed, welded or otherwise affixed to the pads <NUM>. Although four pads 360a-d are illustrated, with two pads 360a-b under the substrate <NUM> and two pads 360c-d above the semiconductor layers <NUM>, more or fewer pads <NUM> may be used in other embodiments.

<FIG> illustrates a top-lateral isometric view <NUM> of the QD laser submount <NUM> with a photonic element <NUM> shown fabricated in the upper surface <NUM> (covered in <FIG> by the photonic element <NUM> and the semiconductor layers <NUM>) of the substrate <NUM> and optically aligned with the QD layer <NUM>. Although one photonic element <NUM> is shown fabricated on the substrate <NUM>, more or fewer photonic elements <NUM> may be fabricated on the substrate <NUM> to mate with the QD layer <NUM> in other embodiments. For example, a QD laser submount <NUM> may be completed without a photonic element <NUM>. In another example, a photonic element <NUM> may be fabricated either side of the semiconductor layer <NUM> and optically aligned with the QD layer <NUM>. Various examples of photonic elements <NUM> are discussed in greater detail in regard to <FIG>.

The photonic element <NUM> is aligned so that any waveguides defined in the photonic element <NUM> will be optically aligned with the QD layer <NUM> according to the predetermined height relative to the substrate at which the QD layer <NUM> is grown. In various embodiments, the photonic element <NUM> is fabricated directly on the substrate <NUM>, or indirectly on the substrate <NUM> (e.g., via the intermediate layer <NUM>). Additionally, in some embodiments the photonic element <NUM> is also encased in the dielectric <NUM>, while in other embodiments, the photonic element <NUM> is outside of the dielectric <NUM>.

<FIG> illustrates a bottom-lateral isometric view <NUM> of the QD laser submount <NUM> with various assembly features shown on the bottom surface <NUM> of the substrate <NUM>. The assembly features are constructed on the wafer <NUM> prior to dicing the wafer <NUM> into individual dies, but each assembly feature is associated with one die. As shown on the die illustrated in <FIG>, three pads <NUM> (associated with TSV <NUM>) are shown, three raised alignment features <NUM> are shown (raised relative to the bottom surface <NUM>), and two etched alignment features <NUM> are shown (etched into the bottom surface <NUM>). The alignment features <NUM> include, but are not limited to: fiducial markers for optical imaging systems (e.g., sets of two to three alignment dots in known positions), mechanical stops, metalized marks, poke-yoke features (e.g., go/no-go features for later assembly), epoxy slots, and other identifying features such as crosshairs, QR codes, and component callouts/labels.

<FIG> illustrate various frontal cut-away views to highlight the different layers and strata of a QD laser in various stages of fabrication, according to one or more embodiments disclosed herein.

<FIG> illustrates a view <NUM> of the stratified layers of a QD laser prior to etching. As illustrated, from bottom to top, a silicon stratum <NUM> is bonded with a first III-V semiconductor material stratum <NUM>, from which a first cladding stratum <NUM>, a first waveguide stratum <NUM>, a quantum dot stratum <NUM>, a second waveguide stratum <NUM>, a second cladding stratum <NUM>, and a second III-V semiconductor material stratum <NUM> are epitaxially grown. As will be appreciated, the relative heights of the individual strata may vary in different embodiments. The quantum dot stratum <NUM> is positioned at a predetermined height relative to an upper surface <NUM> of the silicon stratum <NUM> to allow for alignment with pre-made photonic elements <NUM> that are fabricated on the upper surface <NUM> of the surface stratum <NUM>.

<FIG> illustrates a view <NUM> of one example of an etched QD laser. Etching removes material from one or more layers of the semiconductors of the QD laser to produce a tiered set of layers according to a predefined shape or profile for the semiconductor components of the QD laser. In some embodiments, such as the example illustrated in <FIG>, the contact layer <NUM>, waveguide layer <NUM>, QD layer <NUM>, and matrix layer <NUM> are etched, although more or fewer layers may be etched in other embodiments. As shown in <FIG>, the first III-V semiconductor material stratum <NUM> has a wider cross-section that the "higher" strata, which allows for electrical leads <NUM> to make contact with the first III-V semiconductor material stratum <NUM>, the first cladding stratum <NUM>, and/or the contact stratum <NUM>, and to be insulated from the other strata to which they are not to make contact with.

<FIG> illustrates a view <NUM> of one example of the etched QD laser that has been passivated. A dielectric <NUM>, such as SiO<NUM> or SiON, is applied to the etched layers to protect those layers from corrosion, physical damage, electrically insulate the layers, and/or to provide a desired shape for the QD laser. The dielectric <NUM> may be applied in one or more stages in various embodiments.

<FIG> illustrates a view <NUM> of one example of the etched and passivated QD laser that has been metalized. Metallization may be achieved via evaporation or sputtering processes so as to add TSVs <NUM>, electrical leads <NUM> and pads <NUM> for the QD laser. The electrical leads <NUM> may pass through the dielectric <NUM> and terminate in one or more pads <NUM>. The pads <NUM> are positioned on one or more of the bottom surface <NUM> of the silicon stratum <NUM>, above an upper side of the dielectric <NUM>, or on top of the second III-V stratum <NUM> so that other components can be physically attached to and/or electrically connected to the QD laser. As shown, the electrical leads <NUM> are out of the beam path of the laser produced by QD layer <NUM>.

<FIG> illustrate various example photonic elements <NUM> integrated with the QD laser assemblies constructed according to the present disclosure. In each of the illustrated examples of <FIG>, the example photonic elements <NUM> are integrated in a QD laser submount <NUM> with the substrate <NUM> and the semiconductor layers <NUM> of the QD laser. The photonic element <NUM> is fabricated on the substrate <NUM> and mated to the semiconductor layers <NUM>. Any waveguides internal to the photonic element <NUM> are aligned with the waveguide layer <NUM> and the quantum dot layer <NUM> of the semiconductor layers <NUM>. In various embodiments, different surface treatments are applied to the face of the photonic element <NUM> mated to the semiconductor layers <NUM> to affect the reflectivity of the face of the photonic element <NUM>.

<FIG> shows a mode converter photonic element <NUM> as an example photonic element <NUM> that spreads the propagating frequency of the laser beam. <FIG> shows a wavelength combiner/splitter photonic element <NUM> as an example photonic element <NUM>, which combines or splits the laser beam based on its wavelengths. <FIG> shows a feedback photonic element <NUM> as an example photonic element <NUM>, (such as a distributed Bragg reflector), which produces various stopbands in the photonic element <NUM> to regulate the wavelengths of the laser beam that are emitted from the QD laser submount <NUM>.

<FIG> shows a multi-photonic setup, including two photonic elements 540a-b as example photonic elements <NUM>. In various embodiments, each of the two photonic elements 540a-b may be any of the photonic elements <NUM>, <NUM>, <NUM> described in relation to <FIG>, although other photonic elements <NUM> are envisioned and the current disclosure is not limited to the examples shown in <FIG>. Each of the two photonic elements 540a-b may be the same type of photonic element <NUM>, <NUM>, <NUM>, or the first photonic element 540a may be a different type (e.g., a combiner/splitter photonic element <NUM>) than the second photonic element 540b (e.g., a feedback photonic element <NUM>). Additionally, in some embodiments, at least one face of the second photonic element 540b is given a highly reflective surface, to act as a reflector for the laser beam.

<FIG> illustrate various mounting schemes for a QD laser with a larger photonic integrated circuit (PIC) <NUM>, according to one or more embodiments disclosed herein. The PIC <NUM> in each of <FIG>includes a PIC substrate <NUM> with which a first PIC photonic element 620a (generally, PIC photonic element <NUM>) is fabricated optically aligned with the QD layer <NUM> of a mounted QD laser submount <NUM>. A second PIC photonic element 620b is fabricated on the PIC substrate <NUM> opposite to the first PIC photonic element 620a relative to the mounted QD laser submount <NUM>. In some embodiments, the second PIC photonic element 620b is a reflector that directs the beam generated by the mounted QD laser submount <NUM> back to the first PIC photonic element 620a. In other embodiments, the second PIC photonic element 620b directs an externally generated beam into the QD layer <NUM> for amplification or detection. In yet other embodiments, the second PIC photonic element 620b may be omitted if the QD laser submount <NUM> incorporates a second photonic element <NUM> that is a reflector.

In various embodiments, two separate PIC photonic elements <NUM> are fabricated a predetermined distance from one another on the PIC substrate <NUM> to define a pocket in which the QD laser submount <NUM> is to be mounted. In other embodiments, a single PIC photonic element <NUM> is bonded with the PIC substrate <NUM> and is etched to produce the pocket and thereby differentiate the first PIC photonic element 620a from the second PIC photonic element 620b.

The height of the PIC photonic elements <NUM> is defined so that the waveguide layer <NUM> and QD layer <NUM> of a mounted QD laser submount <NUM> will be aligned with PIC waveguides <NUM> defined in the PIC photonic elements <NUM>. Although one PIC waveguide <NUM> is illustrated in <FIG>, various PIC waveguides <NUM> may be included within the PIC photonic elements <NUM>. In various embodiments the submount <NUM> is optically coupled to the PIC <NUM> using various approaches and coupling elements, including, but not limited to: mode converters, edge-coupling, evanescent coupling, gratings, turning mirrors, etc..

<FIG> illustrates a first mounting scheme <NUM> in which the QD laser submount <NUM> is mounted in place within the pocket of the PIC <NUM> with an epoxy <NUM> (including various glues, cements, and adhesives) between the shoulders of the substrate <NUM> of the QD laser submount <NUM> and the PIC photonic elements <NUM>. Wires <NUM> are then bonded to pads <NUM> defined on the bottom surface <NUM> (facing upward in <FIG>) of the substrate <NUM> to establish electrical connections to the QD laser submount <NUM>. In the illustrated configuration of <FIG>, the face of the first PIC photonic element 620a coupled with the QD laser submount <NUM> includes an anti-reflective surface treatment, whereas the second PIC photonic element 620b includes a highly-reflective surface treatment on the face coupled with the QD laser submount <NUM>. In various embodiments, the surface treatments applied to the PIC photonic elements <NUM> is between about <NUM> micrometers (µm) and about <NUM> thick, which is significantly thinner than the surface treatments used in InP QW laser PICs.

<FIG> illustrates a second mounting scheme <NUM> in which the QD laser submount <NUM> is mounted in place within the pocket of the PIC <NUM> via solder collapse between the top side of the QD laser submount <NUM> and the upper surface of the PIC substrate <NUM>. When using the second mounting scheme <NUM>, the QD laser submount <NUM> may omit TSVs <NUM> and metallization on the bottom surface <NUM> of the substrate <NUM>, as the electrical connections to the QD laser submount <NUM> are made through the solder <NUM> and metallization of the PIC substrate <NUM>, such as through one or more PIC TSV <NUM> and/or PIC Pad <NUM>. In the illustrated configuration of <FIG>, the face of the first PIC photonic element 620a coupled with the QD laser submount <NUM> includes an anti-reflective surface treatment, whereas the second PIC photonic element 620b includes a highly-reflective surface treatment on the face coupled with the QD laser submount <NUM>.

<FIG> illustrates a third mounting scheme <NUM> in which the QD laser submount <NUM> operates as a semiconductor optical amplifier (SOA) between two PIC photonic elements <NUM>. In the illustrated configuration of <FIG>, the face of the first PIC photonic element 620a coupled with the QD laser submount <NUM> and the face of the second PIC photonic element 620b coupled with the QD laser submount <NUM> both include an anti-reflective surface treatment and a PIC waveguide <NUM>. In other embodiments, one face of the second photonic element 370b or the second PIC photonic element 620b is made highly reflective, thus forming a reflective semiconductor optical amplifier (RSOA).

<FIG> & <FIG> illustrate wafer-level views of the QD lasers fabricated according to the present disclosure. <FIG> illustrates a top-view <NUM> of a populated wafer <NUM>, and <FIG> illustrates a bottom-view <NUM> of the populated wafer <NUM>. The top-view <NUM> shows a plurality of QD laser submounts <NUM> (with integrated photonic elements <NUM>) as individual dies on the populated wafer <NUM>. The bottom-view <NUM> shows a plurality of assembly features (e.g., TSV <NUM> and alignment features <NUM>) that are associated with the individual dies of the QD submounts <NUM> on the opposing side of the populated wafer <NUM>.

As will be appreciated, the populated wafer <NUM> will be diced into individual dies for use as QD laser submounts <NUM>. Prior to dicing the populated wafer <NUM> however, various tests may be performed on the individual dies on the populated wafer <NUM> to determine whether the dies have been properly fabricated. Such tests include, but are not limited to: device burn-in, wavelength characterization, light-current-voltage characterization, threshold measurements, wafer maps, photoluminescence, process monitoring, physical dimensions, etc..

Embodiments of the present disclosure are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments presented in this disclosure.

These computer program instructions may also be stored in a computer readable storage medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable storage medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some other implementations, the functions noted in the block may occur out of the order noted in the figures.

Claim 1:
A method, comprising:
bonding (<NUM>) a III-V semiconductor material (<NUM>) with a wafer (<NUM>) comprising a silicon substrate, wherein the III-V semiconductor material is doped prior to being bonded with the wafer;
removing (<NUM>) excess III-V semiconductor material bonded with the silicon substrate to leave a III-V semiconductor material base layer (<NUM>) of a predetermined thickness bonded with the silicon substrate; and
after removing the excess III-V semiconductor material, epitaxially growing (<NUM>) at least one layer on the III-V semiconductor material base layer, the at least one layer comprising a quantum dot layer (<NUM>).