Patent Description:
This section introduces aspects that may help facilitate a better understanding of the disclosure.

In computing, information theory, and coding theory, an error-correction code (ECC) is a code according to which a data signal conforms to specific rules of construction so that departures from these rules in the corresponding received data signal can typically be automatically detected and corrected. A main feature of an ECC is that the sender encodes messages with redundant information, which then allows the receiver to correct up to a fixed number of errors per message without retransmission. Various error-correction codes are widely used, e.g., in telecommunications and data storage. <CIT> discloses a memory device with enhanced error correction. <CIT> discloses low complexity error correction. <CIT> discloses stopping and/or reducing oscillations in low density parity check (LDPC) decoding.

Disclosed herein are embodiments of a low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about <NUM>%.

According to an example embodiment, provided is an apparatus, comprising an optical data receiver to receive a channel-impaired data stream encoded via an LDPC code, the optical data receiver including a digital LDPC decoder comprising: (i) a pre-processor connected to receive a first sequence of LLR values representing measurements of the channel-impaired data stream, the pre-processor being configured to flip nonzero sign bits of the LLR values of the first sequence to transform the first sequence into a corresponding second LLR sequence; and (ii) an electronic decoder connected to perform iterative LDPC decoding of the second LLR sequence in response to a set of bias information corresponding to the sign-bit flips, the set of bias information being applied in the electronic decoder to change a corresponding set of parity-check conditions of the LDPC code.

According to another example embodiment, provided is a communication method, comprising the steps of: generating a first sequence of LLR values by performing, in an optical data receiver, measurements of a channel-impaired data stream encoded via an LDPC code; flipping nonzero sign bits of the LLR values of the first sequence to transform the first sequence into a corresponding second LLR sequence; and performing iterative LDPC decoding of the second LLR sequence using a set of bias information corresponding to the sign-bit flips, the set of bias information being applied to change a corresponding set of parity-check conditions of the LDPC code.

Other aspects, features, and benefits of various disclosed embodiments will become more fully apparent, by way of example, from the following detailed description and the accompanying drawings, in which:.

A representative systematic forward-error-correction (FEC) code is used to convert an input bit sequence into an expanded bit sequence (e.g., an FEC codeword) by appending to the input bit sequence a corresponding set of parity bits. Some well-performing FEC codes are low-density parity-check (LDPC) codes. LDPC codes are linear block codes that have parity check matrices with a relatively small number of nonzero elements in each row and column. An LDPC decoder may use soft information during decoding, which information can be generated by a soft information detector, e.g., relying on a soft-output algorithm. LDPC coding is known to persons of ordinary skill in the error-correction arts and is briefly reviewed, e.g., in International Patent Application Publication No. <CIT>.

<FIG> shows a block diagram of a communication system <NUM> in which example embodiments may be practiced. System <NUM> comprises a transmit branch <NUM>, a receive branch <NUM>, and a communication channel <NUM>. In different embodiments, channel <NUM> may be, e.g., a wireline, wireless, or fiber-optic channel.

In an example embodiment, transmit branch <NUM> comprises a data source (e.g., input port) <NUM>, an LDPC encoder <NUM>, and a data transmitter <NUM>. In operation, data source <NUM> may provide a set of bits <NUM>, often referred to as an original information word, to LDPC encoder <NUM>. LDPC encoder <NUM> encodes information word <NUM> using the operative LDPC code to generate a corresponding codeword <NUM>. Codeword <NUM> is then supplied to data transmitter <NUM>, which converts the supplied codeword into a corresponding output data signal <NUM> suitable for application or transmission to the physical channel <NUM>. Data transmitter <NUM> then applies output data signal <NUM> to channel <NUM>.

In an example embodiment, receive branch <NUM> comprises a data receiver <NUM>, an LDPC decoder <NUM>, and a data sink (e.g., output port) <NUM>. In operation, data receiver <NUM> receives an input data signal <NUM> from channel <NUM>. Input data signal <NUM> typically differs from the corresponding output data signal <NUM> applied or transmitted to channel <NUM> by transmit branch <NUM>, e.g., due to the presence of noise and other linear and/or nonlinear signal distortions imposed by the channel, e.g., chromatic and polarization dispersion and nonlinear optical distortion. Data receiver <NUM> may perform measurements on input data signal <NUM>, e.g., as known in the art, to generate a corresponding set of log-likelihood-ratio (LLR) values <NUM> and then supply the LLR values to LDPC decoder <NUM>.

In an example implementation, an LLR value comprises: (i) a sign bit that represents the best guess (e.g., hard decision) regarding the bit value encoded in the corresponding portion of data signal <NUM>; and (ii) one or more magnitude bits that represent the confidence in the hard decision. For example, data receiver <NUM> may output each LLR value as a five-bit value, wherein the most-significant bit (MSB) is the sign bit and the four least-significant bits (LSBs) are the confidence bits. For example, a five-bit LLR value of <NUM> indicates a hard decision of <NUM> with the minimum confidence, while a five-bit LLR value of <NUM> indicates a hard decision of <NUM> with the maximum confidence. Intermediate values (e.g., between <NUM> and <NUM>) of confidence bits represent intermediate confidence levels. Similarly, a five-bit LLR value of <NUM> indicates a hard decision of <NUM> with the minimum confidence, while a five-bit LLR value of <NUM> indicates a hard decision of <NUM> with the maximum confidence. Other implementations and interpretations of LLR values may also be used in some embodiments.

LDPC decoder <NUM> performs iterative decoding on a sequence of LLR values <NUM> to recover the corresponding original information word <NUM>, which is then directed to data sink <NUM>. More specifically, the decoding processing performed in LDPC decoder <NUM> is directed at converting an LLR sequence <NUM> into a corresponding valid codeword of the operative LDPC code. A valid codeword is characterized in that all of its parity checks defined by the code's parity-check matrix are satisfied, e.g., produce zeros. In a conventional implementation, such decoding processing may include the following example steps. First, parity checks defined by the parity-check matrix are calculated. If all parity checks are satisfied, then the decoding processing is terminated, and the LDPC decoder outputs the codeword that satisfied the parity checks. If some of the parity checks are not satisfied, then the decoder typically operates to try to converge to a valid codeword of the LDPC code using an iterative process, e.g., based on a message-passing or belief-propagation algorithm. After each iteration, the decoder recalculates the parity checks and, depending on the result, may either output a valid codeword or proceed to perform another iteration. In different embodiments, different iteration-stoppage criteria may be used to end iterations.

Some embodiments of system <NUM> may benefit from a receive branch <NUM> having reduced power consumption therein. For example, in some implementations of receive branch <NUM> of an optical communication system <NUM>, LDPC decoder <NUM> may consume approximately <NUM>% of the power needed to run the corresponding digital signal processor (DSP) of the optical data receiver. Accordingly, power-efficient implementations of LDPC decoder <NUM> may especially be desirable for optical communications systems.

These and possibly other related problems in the state of the art can beneficially be addressed using at least some embodiments of LDPC decoder <NUM> described in more detail below in reference to <FIG>. More specifically, according to an example embodiment, LDPC decoder <NUM> may include a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform the received LLR sequences <NUM> into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to LLR sequence <NUM>, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code.

The inventors' computer simulations indicate that an example embodiment of LDPC decoder <NUM> operating in this manner may be able to beneficially reduce the power consumption therein by about <NUM>%. Since the addition of pre- and post-processors may represent a substantially insignificant increase in the circuit complexity of the LDPC decoder, such power-consumption reduction may advantageously be achieved substantially without an overall cost increase for the corresponding DSP and/or receive branch <NUM>.

<FIG> shows a block diagram of LDPC decoder <NUM> according to an embodiment. As shown, LDPC decoder <NUM> comprises a pre-processor <NUM>, a core decoder <NUM>, and a post-processor <NUM> interconnected as indicated in <FIG>. The stream of LLR values <NUM> and the stream of information words <NUM> are also schematically shown in <FIG> to better illustrate the relationship between the circuits of <FIG>.

The inventors believe that the average toggling rate during the decoding processing of an LLR sequence <NUM> in a conventional LDPC decoder may depend on the specific value of the bit-word defined by the sign bits of the sequence. That is, for some specific values of such sign bit-words, the observed average toggling rate may be significantly lower than for some other values of such sign bit-words. One of such specific values may be the null (i.e., all-zero) sign bit-word. Other examples of such specific values may be implementation- and/or code-specific, but may typically be identified, e.g., using appropriate computer simulations. Herein, sign bit-words characterized by a reduced toggling rate during decoding processing of the corresponding LLR sequences <NUM> are referred to as "lower-toggle" sign bit-words.

Herein, the term "toggling rate" refers to the relative rate at which a logic element switches compared to its input. For example, during the decoding processing of an LLR sequence <NUM> (input), some or all of the sign and confidence bits stored in the variable nodes (logic elements) of the decoder may toggle during iterations. A person of ordinary skill in the art will readily understand that, in hardware, a bit-value flip typically involves a voltage change in the corresponding memory cell, which draws electrical current and, as such, consumes electrical power. Thus, reduction in the toggling rate may produce a corresponding reduction in the power consumption.

The architecture of LDPC decoder <NUM> shown in <FIG> beneficially exploits the above-indicated features of the LDPC-decoding processing by steering the decoder towards the decoding paths associated with one or more of the lower-toggle sign bit-words. As a result, the effective toggling rate is typically reduced, thereby beneficially reducing the power consumption in LDPC decoder <NUM>.

Pre-processor <NUM> operates to transform any received LLR sequence <NUM> into a corresponding LLR sequence <NUM>, the sign bits of which form a selected one of the lower-toggle sign bit-words. LLR sequence <NUM> is then supplied to core decoder <NUM> together with a set <NUM> of the corresponding bias information. In an example embodiment, bias information <NUM> is constructed to inform core decoder <NUM> about the parity checks affected by the LLR-sequence transformation performed by pre-processor <NUM>. Pre-processor <NUM> also generates a sign-inversion vector <NUM> corresponding to the LLR-sequence transformation performed therein and supplies this sign-inversion vector to post-processor <NUM>. In an example embodiment, sign-inversion vector <NUM> is constructed to inform post-processor <NUM> about the LLR-sequence positions at which the sign-bit flips have been performed by pre-processor <NUM> during the LLR transformation.

Core decoder <NUM> operates to perform iterative decoding processing of LLR sequence <NUM> using the corresponding bias information <NUM>. In <FIG>, a processing loop <NUM> schematically indicates decoding iterations performed by core decoder <NUM>. After each iteration <NUM>, core decoder <NUM> recalculates biased parity checks and, depending on the result, may either output a corresponding biased codeword <NUM> or proceed to perform another iteration <NUM>. Herein, the term "biased parity checks" refers to a set of parity-check conditions, wherein some of the conditions are altered based on bias information <NUM>. The term "biased codeword" similarly refers to a valid codeword of the operative LDPC code, wherein some of the bits are flipped due to the use of biased parity-check conditions instead of the true parity-check conditions of the code. Example embodiments of the decoding processing performed in core decoder <NUM> are described in more detail below in reference to <FIG> and <FIG>.

Post-processor <NUM> operates to flip the bits of biased codeword <NUM> at positions indicated by sign-inversion vector <NUM>, thereby transforming the biased codeword into a corresponding valid codeword of the operative LDPC code. Post-processor <NUM> then uses this valid codeword to recover, in a conventional manner, the corresponding original information word <NUM>.

<FIG> shows a flowchart of a processing method <NUM> that can be implemented using LDPC decoder <NUM> of <FIG> according to an embodiment. For illustration purposes and without any implied limitations, method <NUM> is described in reference to the null lower-toggle bit-word.

At step <NUM>, pre-processor <NUM> receives a next LLR sequence <NUM> from receiver <NUM>. The received LLR sequence <NUM> has N LLRs, where N is the codeword length of the operative LDPC code. In an example embodiment, the number N can be, e.g., in the range between about <NUM><NUM> and about <NUM><NUM>. Each LLR has a sign bit and n confidence bits, where the number n can be, e.g., in the range between seven and ten. In alternative embodiments, other codeword lengths and/or LLR sizes can be used. Example power savings may depend on the choice of these parameters.

At step <NUM>, pre-processor <NUM> operates to transform LLR sequence <NUM> received at step <NUM> into a corresponding LLR sequence <NUM>, wherein the sign bits form the null bit-word.

At step <NUM>, pre-processor <NUM> generates bias information <NUM> and sign-inversion vector <NUM> corresponding to the transformation of step <NUM>.

At step <NUM>, core decoder <NUM> performs a next decoding iteration <NUM> for the LLR sequence <NUM> of step <NUM> using the bias information <NUM> of step <NUM>. In the first instance of step <NUM>, core decoder <NUM> performs the initial decoding iteration.

Step <NUM> is used to control the exit from the iteration loop <NUM>. More specifically, if the iteration stoppage criteria are not satisfied, then the processing of method <NUM> is looped back for another instance of step <NUM>. Otherwise, the processing of method <NUM> is directed to step <NUM>. In some embodiments of step <NUM>, conventional iteration-stoppage criteria known to persons of ordinary skill in the LDPC coding/decoding arts may be used.

At step <NUM>, post-processor <NUM> recovers the original information word <NUM> corresponding to the LLR sequence <NUM> of step <NUM> based on the biased codeword <NUM> generated during the last instance of step <NUM> and the sign-inversion vector <NUM> of step <NUM>. Step <NUM> may typically include the sub-steps of (i) converting the biased codeword <NUM> into a corresponding valid codeword of the LDPC code and (ii) recovering the original information word <NUM> from the valid codeword.

Step <NUM> is used to control the termination of method <NUM>. More specifically, if there is another LLR sequence <NUM> in the decoding queue, then the processing of method <NUM> is directed back to step <NUM>. Otherwise, the processing of method <NUM> is terminated.

<FIG> shows a simplified bipartite graph <NUM> representing a message-passing decoding algorithm that can be implemented in core decoder <NUM> according to an embodiment. For illustration purposes and without any implied limitations, graph <NUM> is shown as having five channel nodes <NUM><NUM>-<NUM><NUM>, five variable nodes labeled <NUM><NUM>-<NUM><NUM>, and four check nodes labeled <NUM><NUM>-<NUM><NUM>. In general, the full bipartite graph for an LDPC decoder has N variable nodes and (N-r) check nodes, where N is the codeword length of the LDPC code, and r is the length of the corresponding information word, e.g., <NUM>, <FIG>. Connected variable nodes <NUM> and check nodes <NUM> can exchange messages during iterative decoding. The connections through which such messages are passed between the nodes are typically referred to as the "edges" of the graph. The positions of the edges between the nodes are determined by the nonzero elements of the code's parity-check matrix. In an example embodiment, the parity-check matrix may have (N-r) rows and N columns. If the parity-check matrix has a nonzero element located in the i-th column and j-th row, then the corresponding bipartite graph has an edge connecting the i-th variable node and the j-th check node. The bipartite graph does not typically have edges corresponding to any zero elements of the parity-check matrix.

The variable nodes are initialized, by the channel nodes, using LLR sequence <NUM>. As an example, <FIG> shows LLRs <NUM><NUM>-<NUM><NUM> of the LLR sequence <NUM> as being applied to channel nodes <NUM><NUM>-<NUM><NUM>, respectively. During iterative decoding processing, the LLR values stored in the variable nodes are recomputed based on the messages exchanged, through the edges of the graph, by the corresponding variable and check nodes.

Each of the check nodes operates to compute, modulo two, the sum of the inputs applied thereto by the connected nodes (also see <FIG>). In a conventional implementation of the LDPC decoder, the check nodes may only receive inputs from the connected variable nodes, which causes each of the check nodes to compute the corresponding one of the parity checks of the LDPC code. In contrast, in core decoder <NUM>, each of check nodes <NUM> is also connected to receive an input from a respective one of bias nodes <NUM>. In an example embodiment, there is the same number of check and bias nodes, i.e., (N-r) of each. As such, <FIG> illustratively shows four bias nodes <NUM>, labeled <NUM><NUM>-<NUM><NUM>, each of which is connected to provide a corresponding additional input to a respective one of check nodes <NUM><NUM>-<NUM><NUM>. Each of these additional inputs is fixed for each LLR sequence <NUM> that is being processed and does not change during iterative decoding thereof. More specifically, each of bias nodes <NUM> is loaded with a respective bias value computed based on the bias information <NUM> provided by pre-processor <NUM>. As such, <FIG> illustratively shows bias nodes <NUM><NUM>-<NUM><NUM> as providing inputs <NUM><NUM>-<NUM><NUM> to check nodes <NUM><NUM>-<NUM><NUM>, respectively. As a result, check nodes <NUM><NUM>-<NUM><NUM> operate to compute the corresponding biased parity checks for each iteration <NUM>, as already indicated above. A person of ordinary skill in the art will readily understand that different LLR sequences <NUM> may typically result in different respective sets of inputs <NUM><NUM>-<NUM><NUM>.

In an example embodiment, core decoder <NUM> may operate in substantially the same manner as a conventional LDPC decoder to exchange messages, by way of the edges of graph <NUM>, between the connected variable nodes <NUM> and check nodes <NUM>. However, the processing performed by at least some of the check nodes <NUM> may be different from that of the check nodes in a conventional LDPC decoder, e.g., due to the use of inputs <NUM><NUM>-<NUM><NUM>, e.g., as described in more detail below in reference to <FIG>.

<FIG> provide pseudocode examples that can be used to program LDPC decoder <NUM> according to an embodiment. More specifically, <FIG> provides the nomenclature and various definitions relevant to the pseudocodes of <FIG> provide pseudocode examples for programming pre-processor <NUM>, core decoder <NUM>, and post-processor <NUM>, respectively. The pseudocode of <FIG> generally corresponds to steps <NUM>-<NUM> of method <NUM>. The pseudocode of <FIG> generally corresponds to step <NUM> of method <NUM>. The pseudocode of <FIG> generally corresponds to step <NUM> of method <NUM>.

Referring to <FIG>, lines <NUM>-<NUM> cause pre-processor <NUM> to flip the sign bits of any negative LLR values present in the received LLR sequence <NUM>. Lines <NUM>-<NUM> cause pre-processor <NUM> to set to zero the initial values of the messages. Line <NUM> sets the initial component values of bias vector <NUM> to be all zeros. Lines <NUM>-<NUM> cause pre-processor <NUM> to adjust the bias vector <NUM> and compute the sign-inversion vector <NUM> to reflect the sign-bit flips performed at lines <NUM>-<NUM>.

Referring to <FIG>, lines <NUM>-<NUM> represent a single iteration <NUM> performed by core decoder <NUM>. Depending on the decisions taken at step <NUM> of method <NUM>, the processing represented by lines <NUM>-<NUM> may be repeated one or more times. Lines <NUM>-<NUM> cause core decoder <NUM> to compute messages from variable nodes <NUM> to check nodes <NUM>. Lines <NUM>-<NUM> cause core decoder <NUM> to compute messages from check nodes <NUM> to variable nodes <NUM>. Lines <NUM>-<NUM> cause core decoder <NUM> to update the LLR values in the variable nodes <NUM> based on the messages. Therein, line <NUM> makes the hard decision for the potential readout.

Referring to <FIG>, lines <NUM>-<NUM> cause post-processor <NUM> to adjust the hard decision corresponding to line <NUM> (<FIG>) based on the sign-inversion vector <NUM>.

<FIG> shows a block diagram of an optical data transmitter that can be used to implement transmit branch <NUM> of system <NUM> (<FIG>) according to an example not falling under the scope of the claimed invention. In this embodiment, communication channel <NUM> is a fiber-optic channel.

Transmitter <NUM> comprises a DSP <NUM> connected to data source <NUM>. DSP <NUM> comprises LDPC encoder <NUM> (not explicitly shown in <FIG>). In operation, DSP <NUM> processes an input data stream supplied by data source <NUM> to generate digital signals <NUM><NUM>-<NUM><NUM>. In an example embodiment, DSP <NUM> may perform, inter alia, one or more of the following: (i) encode the input data stream using a suitable code, e.g., including an LDPC code; (ii) parse the resulting encoded data stream into a sequence of bit-words; (iii) for each bit-word, determine a corresponding constellation symbol of the operative QAM constellation; (iv) generate a digital drive signal carrying the constellation symbol. For example, in each modulation time slot, signals <NUM><NUM> and <NUM><NUM> may carry digital values that represent the I component and Q component, respectively, of a QAM constellation symbol intended for transmission using a first (e.g., X) polarization of light. Signals <NUM><NUM> and <NUM><NUM> may similarly carry digital values that represent the I and Q components, respectively, of a QAM constellation symbol intended for transmission using a second (e.g., Y) polarization of light.

A front-end circuit <NUM> of transmitter <NUM> is an electrical-to-optical (E/O) converter that operates to transform digital signals <NUM><NUM>-<NUM><NUM> into a corresponding modulated optical output signal <NUM>. More specifically, drive circuits <NUM><NUM> and <NUM><NUM> transform digital signals <NUM><NUM> and <NUM><NUM>, as known in the pertinent art, into electrical analog drive signals IX and QX, respectively. Drive signals IX and QX are then used, in a conventional manner, to drive an optical I-Q modulator <NUM>X. In response to drive signals IX and QX, optical I-Q modulator <NUM>X operates to modulate an X-polarized beam <NUM>X of light supplied thereto by a laser source <NUM> as indicated in <FIG>, thereby generating a modulated optical signal <NUM>X.

The output wavelength of laser source <NUM> is wavelength λ<NUM>. The optical output power of laser source <NUM> can be set and/or changed in response to a control signal <NUM>.

Drive circuits <NUM><NUM> and <NUM><NUM> similarly transform digital signals <NUM><NUM> and <NUM><NUM> into electrical analog drive signals IY and QY, respectively. In response to drive signals IY and QY, an optical I-Q modulator <NUM>Y operates to modulate a Y-polarized beam <NUM>Y of light supplied by laser source <NUM> as indicated in <FIG>, thereby generating a modulated optical signal <NUM>Y. A polarization beam combiner (PBC) <NUM> operates to combine modulated optical signals <NUM>X and <NUM>Y, thereby generating the optical output signal <NUM>, said optical output signal being a polarization-division-multiplexed (PDM) signal. Optical output signal <NUM> may then be directed for transmission to optical fiber <NUM>.

<FIG> shows a block diagram of an optical data receiver that can be used to implement receive branch <NUM> of system <NUM> (<FIG>) according to an embodiment. The shown optical data receiver <NUM> is compatible with optical data transmitter <NUM> of <FIG>.

A front-end circuit <NUM> of receiver <NUM> is an optical-to-electrical (O/E) converter comprising an optical hybrid <NUM>, light detectors <NUM><NUM>-<NUM><NUM>, analog-to-digital converters (ADCs) <NUM><NUM>-<NUM><NUM>, and an optical local-oscillator (OLO) source <NUM>. Optical hybrid <NUM> has (i) two input ports labeled S and R and (ii) four output ports labeled <NUM> through <NUM>. Input port S receives optical signal <NUM> from optical fiber <NUM>. Input port R receives an OLO signal <NUM> generated by OLO source (e.g., laser) <NUM>. OLO signal <NUM> has an optical-carrier wavelength (frequency) that is sufficiently close to that of signal <NUM> to enable coherent (e.g., intradyne) detection of the latter optical signal.

In an example embodiment, optical hybrid <NUM> operates to mix optical signal <NUM> and OLO signal <NUM> to generate different mixed (e.g., by interference) optical signals (not explicitly shown in <FIG>). Light detectors <NUM><NUM>-<NUM><NUM> then convert the mixed optical signals into four electrical signals <NUM><NUM>-<NUM><NUM> that are indicative of complex values corresponding to two orthogonal-polarization components of optical signal <NUM>. For example, electrical signals <NUM><NUM> and <NUM><NUM> may be indicative of an analog I signal and an analog Q signal, respectively, or linearly independent mixtures thereof corresponding to a first (e.g., horizontal, h) polarization component of optical signal <NUM>. Electrical signals <NUM><NUM> and <NUM><NUM> may similarly be indicative of an analog I signal and an analog Q signal, respectively, or linearly independent mixtures thereof corresponding to a second (e.g., vertical, v) polarization component of optical signal <NUM>.

Each of electrical signals <NUM><NUM>-<NUM><NUM> is converted into digital form in a corresponding one of ADCs <NUM><NUM>-<NUM><NUM>. Optionally, each of electrical signals <NUM><NUM>-<NUM><NUM> may be low-pass filtered and amplified in a corresponding electrical amplifier (not explicitly shown) prior to the resulting signal being converted into digital form. Digital signals <NUM><NUM>-<NUM><NUM> produced by ADCs <NUM><NUM>-<NUM><NUM>, respectively, are then processed by a DSP <NUM>. DSP <NUM> comprises LDPC decoder <NUM> (not explicitly shown in <FIG>).

In an example embodiment, DSP <NUM> may perform, inter alia, one or more of the following: (i) signal processing directed at dispersion compensation; (ii) signal processing directed at compensation of nonlinear distortions; (iii) electronic compensation for polarization rotation and polarization de-multiplexing; (iv) compensation of frequency offset between OLO <NUM> and laser source <NUM>; (v) error correction based on LDPC-encoding performed at DSP <NUM>; (vi) mapping of a set of complex values conveyed by digital signals <NUM><NUM>-<NUM><NUM> onto the operative QAM constellations to determine a corresponding constellation symbol thereof, etc. An output data stream of DSP <NUM> is applied to data sink <NUM>.

According to an example embodiment disclosed above, e.g., in the summary section and/or in reference to any one or any combination of some or all of <FIG>, provided is an apparatus, comprising an optical data receiver (e.g., <NUM>, <FIG>) to receive a channel-impaired data stream (e.g., <NUM>, <FIG>) encoded via a low-density parity-check, LDPC, code, the optical data receiver including a digital LDPC decoder (e.g., <NUM>, <FIG>) comprising: (i) a pre-processor (e.g., <NUM>, <FIG>) connected to receive a first sequence of log-likelihood-ratio, LLR, values (e.g., <NUM>, <FIG>) representing measurements of the channel-impaired data stream, the pre-processor being configured to flip (e.g., <NUM>, <FIG>) nonzero sign bits of the LLR values of the first sequence to transform the first sequence into a corresponding second LLR sequence (e.g., <NUM>, <FIG>); and (ii) an electronic decoder (e.g., <NUM>, <FIG>) connected to perform iterative LDPC decoding (e.g., <NUM>-<NUM>, <FIG>) of the second LLR sequence in response to a set of bias information (e.g., <NUM>, <FIG>) corresponding to the sign-bit flips, the set of bias information being applied in the electronic decoder to change a corresponding set of parity-check conditions of the LDPC code.

In some embodiments of the above apparatus, the digital LDPC decoder further comprises a post-processor (e.g., <NUM>, <FIG>) configured to obtain (e.g., <NUM>-<NUM>, <FIG>) a codeword of the LDPC code corresponding to the first sequence by flipping bits of a hard decision at bit positions corresponding to positions of the sign-bit flips in the first sequence, the hard decision being taken upon stoppage of the iterative LDPC decoding (e.g., "Yes" at <NUM>, <FIG>).

In some embodiments of any of the above apparatus, the digital LDPC decoder is configured to recover (e.g., <NUM>, <FIG>), based on the codeword, a corresponding information word encoded in the channel-impaired data stream.

In some embodiments of any of the above apparatus, the digital LDPC decoder is configured to perform the iterative LDPC decoding by updating messages for variable nodes (e.g., <NUM>, <FIG>) and check nodes (e.g., <NUM>, <FIG>) thereof.

In some embodiments of any of the above apparatus, the set of bias information (e.g., <NUM><NUM>-<NUM><NUM>, <FIG>) is applied to a corresponding set of the check nodes to change the parity-check conditions computed thereat.

In some embodiments of any of the above apparatus, individual ones of the variable nodes are initialized using respective LLR values (e.g., <NUM><NUM>-<NUM><NUM>, <FIG>) of the second LLR sequence.

In some embodiments of any of the above apparatus, the optical data receiver comprises one or more photodiodes (e.g., <NUM><NUM>-<NUM><NUM>, <FIG>) to receive the channel-impaired data stream.

According to another example embodiment disclosed above, e.g., in the summary section and/or in reference to any one or any combination of some or all of <FIG> and <FIG>, provided is a communication method, comprising the steps of: generating a first sequence of log-likelihood-ratio, LLR, values (e.g., <NUM>, <FIG>) by performing, in an optical data receiver (e.g., <NUM>, <FIG>), measurements of a channel-impaired data stream (e.g., <NUM>, <FIG>) encoded via a low-density parity-check, LDPC, code; flipping (e.g., <NUM>, <FIG>) nonzero sign bits of the LLR values of the first sequence to transform the first sequence into a corresponding second LLR sequence (e.g., <NUM>, <FIG>); and performing iterative LDPC decoding (e.g., <NUM>-<NUM>, <FIG>) of the second LLR sequence using a set of bias information (e.g., <NUM>, <FIG>) corresponding to the sign-bit flips, the set of bias information being applied (e.g., to <NUM>, <FIG>) to change a corresponding set of parity-check conditions of the LDPC code.

In some embodiments of the above method, the method further comprises obtaining (e.g., <NUM>-<NUM>, <FIG>) a codeword of the LDPC code corresponding to the first sequence by flipping bits of a hard decision at bit positions corresponding to positions of the sign-bit flips in the first sequence, the hard decision being taken upon stoppage of the iterative LDPC decoding (e.g., "Yes" at <NUM>, <FIG>).

In some embodiments of any of the above methods, the method further comprises recovering (e.g., <NUM>, <FIG>), based on the codeword, a corresponding information word encoded in the channel-impaired data stream.

In some embodiments of any of the above methods, the performing comprises passing messages between variable nodes (e.g., <NUM>, <FIG>) and check nodes (e.g., <NUM>, <FIG>) of an LDPC decoder.

In some embodiments of any of the above methods, the performing further comprises applying the set of bias information (e.g., <NUM><NUM>-<NUM><NUM>, <FIG>) to a corresponding set of the check nodes to change the parity-check conditions computed thereat.

In some embodiments of any of the above methods, individual ones of the variable nodes are initialized using respective LLR values (e.g., <NUM><NUM>-<NUM><NUM>, <FIG>) of the second LLR sequence.

While this disclosure includes references to illustrative embodiments, this specification is not intended to be construed in a limiting sense. Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the scope of protection, which is defined by the claims.

It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure may be made by those skilled in the art without departing from the scope as expressed in the following claims.

Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Unless otherwise specified herein, the use of the ordinal adjectives "first," "second," "third," etc., to refer to an object of a plurality of like objects merely indicates that different instances of such like objects are being referred to, and is not intended to imply that the like objects so referred-to have to be in a corresponding order or sequence, either temporally, spatially, in ranking, or in any other manner.

Unless otherwise specified herein, in addition to its plain meaning, the conjunction "if" may also or alternatively be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting," which construal may depend on the corresponding specific context. For example, the phrase "if it is determined" or "if [a stated condition] is detected" may be construed to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event].

Also for purposes of this description, the terms "couple," "coupling," "coupled," "connect," "connecting," or "connected" refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms "directly coupled," "directly connected," etc., imply the absence of such additional elements.

The described embodiments are to be considered in all respects as only illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of the claims are to be embraced within their scope.

A person of ordinary skill in the art would readily recognize that steps of various above-described methods can be performed by programmed computers. Herein, some embodiments are intended to cover program storage devices, e.g., digital data storage media, which are machine or computer readable and encode machine-executable or computer-executable programs of instructions where said instructions perform some or all of the steps of methods described herein. The program storage devices may be, e.g., digital memories, magnetic storage media such as a magnetic disks or tapes, hard drives, or optically readable digital data storage media. The embodiments are also intended to cover computers programmed to perform said steps of methods described herein.

It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

The functions of the various elements shown in the figures, including any functional blocks labeled as "processors" and/or "controllers," may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. Moreover, explicit use of the term "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage.

As used in this application, the term "circuitry" may refer to one or more or all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry); (b) combinations of hardware circuits and software, such as (as applicable): (i) a combination of analog and/or digital hardware circuit(s) with software/firmware and (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions); and (c) hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g., firmware) for operation, but the software may not be present when it is not needed for operation. " This definition of circuitry applies to all uses of this term in this application, including in any claims.

It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.

Claim 1:
An apparatus for a communications system, comprising an optical data receiver (<NUM>) to receive a channel-impaired data stream (<NUM>) encoded via a low-density parity-check, LDPC, code, the optical data receiver including a digital LDPC decoder (<NUM>) comprising:
a pre-processor (<NUM>) connected to receive a first sequence of log-likelihood-ratio, LLR, values (<NUM>) representing measurements of the channel-impaired data stream, the pre-processor being configured to flip (<NUM>) nonzero sign bits of the LLR values of the first sequence to transform the first sequence into a corresponding second LLR sequence (<NUM>); and
an electronic decoder (<NUM>) connected to perform iterative LDPC decoding (<NUM>-<NUM>) of the second LLR sequence in response to a set of bias information (<NUM>) corresponding to the sign-bit flips, the set of bias information being applied in the electronic decoder to change a corresponding set of parity-check conditions of the LDPC code.