Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Exemplary, <CIT> discloses a semiconductor device with a peripheral circuit region and a first memory region that are side by side on a substrate and with a second memory region that is on the peripheral circuit region and the first memory region, <CIT> discloses an integrated circuit memory device, including a memory circuit and a peripheral circuit, which are implemented in different layers of a stacked structure and which include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit, <CIT> discloses an NAND memory with a silicon substrate, a plurality of peripheral devices, a plurality of NAND strings formed above the peripheral devices, a monocrystal silicon layer formed above the multiple NAND strings, and one or more first interconnection layers formed between the multiple peripheral devices and the multiple NAND strings, wherein the monocrystal silicon layer and the multiple NAND strings are in contact connection, and <CIT> discloses a 3D memory device with arrays of storage cells including CMOS circuitry and control circuitry to access the storage cells.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein.

In one example, a 3D memory device according to the invention is disclosed in claim <NUM> and includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

In another example, a method for forming a 3D memory device according to the invention is disclosed in claim <NUM> and includes forming a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts, forming a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts, and bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

In still another example, the method for operating a 3D memory device according to the invention is disclosed in claim <NUM>, the device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

In conventional 3D memory devices, the periphery circuits that are formed outside of memory array devices on the same plane can occupy a large area of the device chip, thereby leading to poor array efficiency, large die size, and high cost. Also, the thermal budget associated with processing the memory array device limits the peripheral circuit performance requirement, making it difficult to achieve high input/output (I/O) speed of the 3D memory device. Moreover, in memory technology, operations based on caching and/or buffering program data often require additional memory space. The conventional 3D memory architecture makes it difficult for certain operations that requires additional memory space to be implemented.

For example, cache program operations are commonly used in a solid-state drive of a memory device to improve the performance (e.g., speed) of sequential programming. In a cache program operation, program data are sequentially written into memory cells while cached/buffered into a cache to allow faster programming. Due to considerations such as volume and cost, cache spaces are often not formed in memory packages such as an embedded multi-media card (eMMC) o universal flash storage (UFS). Cache program operations are often not enabled in such memory packages. As a result, high-speed sequential programming in these memory packages can be limited. In another example, a memory device can use a considerable amount of resources (e.g., data buffers and data buses) to buffer and transmitting program data. This can slow down other operations (e.g., buffering and/or transmitting data for other operations). The overall performance of the memory device can be limited.

Various embodiments in accordance with the present disclosure provide a 3D memory device having an on-chip static random-access memory (SRAM) with improved I/O speed, throughput, and memory density. On-die SRAM cells are formed on the same chip with peripheral circuits of the 3D memory device. The SRAM cells can locate in the area that is not occupied by the peripheral circuits (e.g., the spare space neighboring peripheral circuits) and thus, do not need extra space to be formed. The on-die SRAM can enable high-speed read and write operations on the memory cells of the 3D memory device. In an embodiment, the on-die SRAM is used as a cache for a cache program operation. In another embodiment, the on-die SRAM is used as a data buffer for coarse and fine programming of the memory cells, releasing buffering space in the main buffer of the system. The on-die SRAM can thus enable high-speed sequentially programming in the 3D memory device and allow more space to be released in the main buffer for other operations.

<FIG> illustrates a schematic view of a cross-section of an exemplary 3D memory device <NUM> with an SRAM, according to some embodiments. 3D memory device <NUM> represents an example of a non-monolithic 3D memory device. The term "non-monolithic" means that the components of 3D memory device <NUM> (e.g., peripheral circuit/SRAM and 3D NAND memory) can be formed separately on different substrates and then joined to form a 3D memory device. 3D memory device <NUM> can include a first semiconductor structure <NUM> including peripheral circuits and an array of SRAM cells. Both peripheral circuits and the SRAM cell array can be implemented with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) to achieve high speed. In some embodiments, the peripheral circuits and SRAM cell array in first semiconductor structure <NUM> use complementary metal-oxide-semiconductor (CMOS) technology.

In some embodiments, the peripheral circuits include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>. For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). An SRAM is integrated on the same die of logic circuits (e.g., the peripheral circuits), allowing wider bus and higher operation speed. The memory controller of the SRAM can be embedded as part of the peripheral circuits. In some embodiments, each SRAM cell includes a plurality of transistors for string a bit of data as a positive of negative electrical charge as well as one or more transistors that control access to it. In one example, each SRAM cell has six transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)),for example, four transistors for storing a bit of data and two transistors for controlling access to the data.

3D memory device <NUM> can also include a second semiconductor structure <NUM> including an array of 3D NAND memory strings. That is, second semiconductor structure <NUM> can be a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. In some embodiments, depending on the NAND technology (e.g., the number of levels/tiers in the memory stack), a 3D NAND memory string typically consists of <NUM> to <NUM> NAND memory cells. 3D NAND memory strings can be organized into pages which are then organized into blocks in which each 3D NAND memory string is connected to a separate line called a bit line (BL). All cells with the same position in the 3D NAND memory string can be connected through the control gates by a word line (WL). In some embodiments, a plane contains a certain number of blocks that are connected through the same bit line. Second semiconductor structure <NUM> can include one or more planes, and the peripheral circuits that are needed to perform all the read/ write/ erase operations can be included in first semiconductor structure <NUM>.

As shown in <FIG>, 3D memory device <NUM> further includes a bonding interface <NUM> vertically between first semiconductor structure <NUM> and second semiconductor structure <NUM>. As described below in detail, first and second semiconductor structures <NUM> and <NUM> can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of first and second semiconductor structures <NUM> and <NUM> does not limit the processes of fabricating another one of first and second semiconductor structures <NUM> and <NUM>. Moreover, a large number of interconnects (e.g., bonding contacts via hybrid bonding) can be formed through bonding interface <NUM> to make direct, short electrical connections between first semiconductor structure <NUM> and second semiconductor structure <NUM>, as opposed to the long-distance chip-to-chip data bus on the circuit board, thereby eliminating chip interface delay and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the array of 3D NAND memory strings in second semiconductor structure <NUM> and the array of SRAM cells in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts via hybrid bonding) across bonding interface <NUM>. Furthermore, by vertically integrating first and second semiconductor structures <NUM> and <NUM>, the chip size can be reduced, and the memory cell density can be increased.

It is understood that the relative positions of stacked first and second semiconductor structures <NUM> and <NUM> are not limited. <FIG> illustrates a schematic view of a cross-section of another exemplary 3D memory device <NUM> with an SRAM, according to some embodiments. Different from 3D memory device <NUM> in <FIG> in which second semiconductor structure <NUM> including the array of 3D NAND memory strings is above first semiconductor structure <NUM> including the peripheral circuits and the array of SRAM cells, in 3D memory device <NUM> in <FIG>, first semiconductor structure <NUM> including the peripheral circuits and the array of SRAM cells is above second semiconductor structure <NUM> including the array of 3D NAND memory strings. Nevertheless, bonding interface <NUM> is formed vertically between first and second semiconductor structures <NUM> and <NUM> in 3D memory device <NUM> as well as first and second semiconductor structures <NUM> and <NUM> are joined vertically through bonding (e.g., hybrid bonding) according to some embodiments. Data transfer between the array of 3D NAND memory strings in second semiconductor structure <NUM> and the array of SRAM cells in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts via hybrid bonding) across bonding interface <NUM>.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having a peripheral circuit and an SRAM, according to some embodiments. Semiconductor structure <NUM> may be one example of first semiconductor structure <NUM>. Semiconductor structure <NUM> can include peripheral circuits for controlling and sensing a 3D NAND memory, including word line drivers <NUM>, page buffers <NUM>, and any other suitable circuits. Semiconductor structure <NUM> can further include SRAM <NUM> on the same die as the peripheral circuits and fabricated using the same logic process as the peripheral circuits. <FIG> shows an exemplary layout of the peripheral circuits (e.g., word line drivers <NUM>, page buffers <NUM>) and SRAM <NUM> in which peripheral circuits (e.g., word line drivers <NUM>, page buffers <NUM>) and SRAM <NUM> are formed in different regions on the same plane. For example, SRAM <NUM> may be formed outside of the peripheral circuits (e.g., word line drivers <NUM>, page buffers <NUM>). It is understood that the layout of semiconductor structure <NUM> is not limited to the exemplary layout in <FIG>. In some embodiments, the peripheral circuit (e.g., word line drivers <NUM> and page buffers <NUM>) and SRAM <NUM> are formed in non-overlapping regions of the same plane. In some embodiments not forming part of the claimed invention, on a plane, SRAM <NUM> is formed in space that is not used for the formation of the peripheral circuit. In some embodiments forming part of the claimed invention, the peripheral circuit (e.g., word line drivers <NUM> and page buffers <NUM>) and SRAM <NUM> (e.g., the array of SRAM cells) are stacked one over another, i.e., on different planes. For example, SRAM <NUM> (e.g., the array of SRAM cells) is formed above or below the peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>) to further reduce the chip size.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM> with an SRAM, according to some embodiments. As one example of 3D memory device <NUM> described above with respect to <FIG>, 3D memory device <NUM> is a non-monolithic 3D memory device including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are joined at a bonding interface <NUM> therebetween. As shown in <FIG>, first semiconductor structure <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of 3D memory device <NUM> can include a device layer <NUM> above substrate <NUM>. It is noted that x and y axes are added in <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM>. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

In some embodiments, device layer <NUM> includes a peripheral circuit <NUM> on substrate <NUM> and an array of SRAM cells <NUM> on substrate <NUM> and outside of peripheral circuit <NUM>. In some embodiments, peripheral circuit <NUM> includes a plurality of peripheral transistors <NUM> forming any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM> including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference. Peripheral transistors <NUM> can be formed "on" substrate <NUM>, in which the entirety or part of peripheral transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of peripheral transistors <NUM>) can be formed in substrate <NUM> as well.

In some embodiments, each SRAM cell <NUM> includes a plurality of SRAM transistors <NUM> (e.g., MOSFETs). In some embodiments, SRAM cell <NUM> is a 6T cell that consists of four MOSFETs for storing <NUM> bit of data and two MOSFETs for controlling access to the data. It is understood that SRAM cell <NUM> may be of any suitable configuration, such as more or fewer than six transistors (e.g., more or fewer transistors per bit). In some embodiments, SRAM transistors <NUM> are formed "on" substrate <NUM>, in which the entirety or part of SRAM transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of SRAM transistors <NUM>) can be formed in substrate <NUM> as well. As shown in <FIG>, SRAM transistors <NUM> and peripheral transistors <NUM> can be formed in different regions on the same plane, e.g., on substrate <NUM>. That is, SRAM transistors <NUM> can be formed outside of the region in which peripheral circuit <NUM> is formed on substrate <NUM>. In some embodiments, the two access MOSFETs (e.g., MOSFETs that control access of data) are controlled by a word line, and the four storage MOSFETs (e.g., MOSFETs that store the bit of data) are coupled to bit lines and controlled by the two access MOSFETs. For ease of illustration, <FIG> only depicts a limited number of SRAM transistors <NUM> and the connection of SRAM transistors <NUM> to bit lines <NUM>. An electrode contact <NUM> may be connected to electrodes of MOSFETs and a common plate <NUM>, e.g., a common ground. It is understood that the configuration in <FIG>, e.g., the layout of SRAM transistors and the connection between SRAM transistors <NUM> and bit lines <NUM>, do not reflect the actual layout and electrical connection between SRAM transistors and other components (e.g., word lines, bit lines, and ground).

In some embodiments, first semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from peripheral circuit <NUM> and array of SRAM cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and via contacts can form. That is, interconnect layer <NUM> can include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown in <FIG>, first semiconductor structure <NUM> of 3D memory device <NUM> can further include a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM> (including peripheral circuit <NUM> and array of SRAM cells <NUM>). Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can also include a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

As described above, second semiconductor structure <NUM> can be bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. In some embodiments, bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> includes a NAND Flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Each 3D NAND memory string <NUM> extends vertically through a plurality of pairs each including a conductor layer <NUM> and a dielectric layer <NUM>, according to some embodiments. The stacked and interleaved conductor layers <NUM> and dielectric layer <NUM> are also referred to herein as a memory stack <NUM>. Interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> alternate in the vertical direction, according to some embodiments. In other words, except for the ones at the top or bottom of memory stack <NUM>, each conductor layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductor layers <NUM> on both sides. Conductor layers <NUM> can each have the same thickness or different thicknesses. Similarly, dielectric layers <NUM> can each have the same thickness or different thicknesses. Conductor layers <NUM> can include conductor materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, each 3D NAND memory string <NUM> is a "charge trap" type of NAND memory string including a semiconductor channel <NUM> and a memory film <NUM>. In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite dielectric layer including a tunneling layer, a storage layer (also known as "charge trap/storage layer"), and a blocking layer. Each 3D NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). Semiconductor channel <NUM>, the tunneling layer, the storage layer, and the blocking layer of memory film <NUM> are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the blocking layer can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In another example, the blocking layer can include a high-k dielectric layer, such as an aluminum oxide (Al<NUM>O<NUM>) layer, a hafnium oxide (HfO<NUM>) layer, a tantalum oxide (Ta<NUM>O<NUM>) layer, etc..

In some embodiments, 3D NAND memory strings <NUM> further include a plurality of control gates (each being part of a word line). Each conductor layer <NUM> in memory stack <NUM> can act as a control gate for each memory cell of 3D NAND memory string <NUM>. In some embodiments, each 3D NAND memory string <NUM> includes two plugs <NUM> and <NUM> at a respective end in the vertical direction. Plug <NUM> can include a semiconductor material, such as single-crystal silicon, that is epitaxially grown from a semiconductor layer <NUM>. Plug <NUM> can function as the channel controlled by a source select gate of 3D NAND memory string <NUM>. Plug <NUM> can be at the upper end of 3D NAND memory string <NUM> and in contact with semiconductor channel <NUM>. As used herein, the "upper end" of a component (e.g., 3D NAND memory string <NUM>) is the end father away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., 3D NAND memory string <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Another Plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductor materials (e.g., metals). In some embodiments, plug <NUM> includes an opening filled with titanium/titanium nitride (Ti/TiN as a barrier layer) and tungsten (as a conductor). By covering the upper end of 3D NAND memory string <NUM> during the fabrication of 3D memory device <NUM>, plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in 3D NAND memory string <NUM>, such as silicon oxide and silicon nitride. In some embodiments, plug <NUM> functions as the drain of 3D NAND memory string <NUM>.

In some embodiments, first semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above memory stack <NUM> and 3D NAND memory strings <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which memory stack <NUM> and 3D NAND memory strings <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon from which plugs <NUM> can be epitaxially grown. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., functioning as an array common source for 3D NAND memory strings <NUM>, not shown). Isolation regions (not shown) can extend across the entire thickness or part of the thickness of semiconductor layer <NUM> to electrically isolate the doped regions. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and semiconductor layer <NUM>.

It is understood that 3D NAND memory strings <NUM> are not limited to the "charge trap" type of 3D NAND memory strings and may be "floating gate" type of 3D NAND memory strings in other embodiments. Semiconductor layer <NUM> may include polysilicon as the source plate of the "floating gate" type of 3D NAND memory strings.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. The pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between 3D memory device <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, array of SRAM cells <NUM> can be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, peripheral circuit <NUM>, array of SRAM cells <NUM>, and array of 3D NAND memory strings <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of another exemplary 3D memory device <NUM> with an SRAM, according to some embodiments. Similar to 3D memory device <NUM> described above in <FIG>, 3D memory device <NUM> represents an example of a non-monolithic 3D memory device in which a first semiconductor structure <NUM> including 3D NAND memory strings and a second semiconductor structure <NUM> including peripheral circuits and SRAM cells are formed separately and bonded in a face-to-face manner at a bonding interface <NUM>. Different from 3D memory device <NUM> described above in <FIG> in which first semiconductor structure <NUM> including peripheral circuits and SRAM cells is below second semiconductor structure <NUM> including 3D NAND memory strings, 3D memory device <NUM> in <FIG> includes second semiconductor structure <NUM> including peripheral circuits and SRAM cells disposed above first semiconductor structure <NUM> including 3D NAND memory strings. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both 3D memory devices <NUM> and <NUM> may not be repeated below.

First semiconductor structure <NUM> of 3D memory device <NUM> can include a substrate <NUM> and a memory stack <NUM> including interleaved conductor layers <NUM> and dielectric layers <NUM> above substrate <NUM>. In some embodiments, an array of 3D NAND memory strings <NUM> each extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> above substrate <NUM>. Each 3D NAND memory string <NUM> can include a semiconductor channel <NUM> and a memory film <NUM>. Each 3D NAND memory string <NUM> further includes two plugs <NUM> and <NUM> at its lower end and upper end, respectively. 3D NAND memory strings <NUM> can be "charge trap" type of 3D NAND memory strings or "floating gate" type of 3D NAND memory strings. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and substrate <NUM>.

In some embodiments, first semiconductor structure <NUM> of 3D memory device <NUM> also includes an interconnect layer <NUM> above memory stack <NUM> and 3D NAND memory strings <NUM> to transfer electrical signals to and from 3D NAND memory strings <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, first semiconductor structure <NUM> of 3D memory device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and memory stack <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> includes another bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>. In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> also includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts.

Second semiconductor structure <NUM> of 3D memory device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, device layer <NUM> includes a peripheral circuit <NUM> above interconnect layer <NUM> and bonding layer <NUM> and an array of SRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of peripheral circuit <NUM>. In some embodiments, peripheral circuit <NUM> includes a plurality of peripheral transistors <NUM> forming any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM> including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference. Peripheral transistors <NUM> can be formed "on" a semiconductor layer <NUM>, in which the entirety or part of peripheral transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of peripheral transistors <NUM>) can be formed in semiconductor layer <NUM> as well.

In some embodiments, each SRAM cell <NUM> includes a plurality of SRAM transistors <NUM> (e.g., MOSFETs). In some embodiments, SRAM cell <NUM> is a 6T cell that consists of four MOSFETs for storing <NUM> bit of data and two MOSFETs for controlling access to the data. It is understood that SRAM cell <NUM> may be of any suitable configuration, such as more or fewer than six transistors (e.g., more or fewer transistors per bit). In some embodiments, SRAM transistors <NUM> are formed "on" semiconductor layer <NUM>, in which the entirety or part of SRAM transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of SRAM transistors <NUM>) can be formed in semiconductor layer <NUM> as well. As shown in <FIG>, SRAM transistors <NUM> and peripheral transistors <NUM> can be formed in different regions on the same plane, e.g., on semiconductor layer <NUM>. That is, SRAM transistors <NUM> can be formed outside of the region in which peripheral circuit <NUM> is formed on semiconductor layer <NUM>. In some embodiments, the two access MOSFETs (e.g., MOSFETs that control access of data) are controlled by a word line, and the four storage MOSFETs (e.g., MOSFETs that store the bit of data) are coupled to bit lines and controlled by the two access MOSFETs. For ease of illustration, <FIG> only depicts a limited number of SRAM transistors <NUM> and the connection of SRAM transistors <NUM> to bit lines <NUM>. An electrode contact <NUM> may be connected to electrodes of MOSFETs and a common plate <NUM>, e.g., a common ground. It is understood that the configuration in <FIG>, e.g., the layout of SRAM transistors and the connection between SRAM transistors <NUM> and bit lines <NUM>, do not reflect the actual layout and electrical connection between SRAM transistors and other components (e.g., word lines, bit lines, and ground).

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which peripheral transistors <NUM> and SRAM transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between 3D memory device <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, array of SRAM cells <NUM> can be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, peripheral circuit <NUM>, array of SRAM cells <NUM>, and array of 3D NAND memory strings <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having a peripheral circuit and an SRAM, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having 3D NAND memory strings, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary 3D memory device with an SRAM, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for forming a 3D memory device with an SRAM, according to some embodiments. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory device <NUM> depicted in <FIG> and 3D memory device <NUM> depicted in <FIG>. <FIG> and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

As depicted in <FIG>, a first semiconductor structure including a peripheral circuit, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts is formed. As depicted in <FIG> and <FIG>, a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts is formed. As depicted in <FIG> and <FIG>, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which the peripheral circuit and the array of SRAM cells are formed on a first substrate. The first substrate can be a silicon substrate. In some embodiments, to form the peripheral circuit and the array of SRAM cells, a plurality of transistors are formed on the first substrate. As illustrated in <FIG>, a plurality of transistors (e.g., peripheral transistors <NUM> and SRAM transistors <NUM>) are formed on a silicon substrate <NUM>. Transistors <NUM> and <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors <NUM> and <NUM>. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition.

As illustrated in <FIG>, bit lines <NUM> and common plates <NUM> are formed as well for connecting SRAM transistors <NUM>. A device layer <NUM> including a peripheral circuit (having peripheral transistors <NUM>) and an array of SRAM cells (each having a plurality of SRAM transistors <NUM>) is thereby formed.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first interconnect layer is formed above the peripheral circuit and the array of SRAM cells. The first interconnect layer can include a first plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above device layer <NUM> including the peripheral circuit (having peripheral transistors <NUM>) and the array of SRAM cells (each having SRAM transistor <NUM>). Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with device layer <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first bonding layer is formed above the first interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack is formed above a second substrate. The second substrate can be a silicon substrate. As illustrated in <FIG>, interleaved sacrificial layers (not shown) and dielectric layers <NUM> are formed above a silicon substrate <NUM>. The interleaved sacrificial layers and dielectric layers <NUM> can form a dielectric stack (not shown). In some embodiments, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer <NUM> includes a layer of silicon oxide. The interleaved sacrificial layers and dielectric layers <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a memory stack <NUM> can be formed by a gate replacement process, e.g., replacing the sacrificial layers with conductor layers <NUM> using wet/dry etch of the sacrificial layers selective to dielectric layers <NUM> and filling the resulting recesses with conductor layers <NUM>. As a result, memory stack <NUM> can include interleaved conductor layers <NUM> and dielectric layers <NUM>. In some embodiments, each conductor layer <NUM> includes a metal layer, such as a layer of tungsten. It is understood that memory stack <NUM> may be formed by alternatingly depositing conductor layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without the gate replacement process in other embodiments. In some embodiments, a pad oxide layer including silicon oxide is formed between memory stack <NUM> and silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the array of 3D NAND memory strings extending vertically through the memory stack are formed. As illustrated in <FIG>, 3D NAND memory strings <NUM> are formed above silicon substrate <NUM>, each of which extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> include forming a channel hole through memory stack <NUM> and into silicon substrate <NUM> using dry etching/and or wet etching, such as deep reactive-ion etching (DRIE), followed by epitaxially growing a plug <NUM> in the lower portion of the channel hole from silicon substrate <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> also include subsequently filling the channel hole with a plurality of layers, such as a memory film <NUM> (e.g., a tunneling layer, a storage layer, and a blocking layer) and a semiconductor layer <NUM>, using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> further include forming another plug <NUM> in the upper portion of the channel hole by etching a recess at the upper end of 3D NAND memory string <NUM>, followed by filling the recess with a semiconductor material using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of 3D NAND memory strings. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above memory stack <NUM> and array of 3D NAND memory strings <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with 3D NAND memory strings <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at the bonding interface. The bonding can be hybrid bonding. In some embodiments, the first substrate on which the peripheral circuit and SRAM cells are formed (e.g., the first semiconductor structure) is disposed above the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) after the bonding. In some embodiments, the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) is disposed above the first substrate on which the peripheral circuit and SRAM cells are formed (e.g., the first semiconductor structure) after the bonding.

As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., 3D NAND memory strings <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., the peripheral circuit and SRAM cells therein) can be electrically connected to 3D NAND memory strings <NUM>. It is understood that in the bonded device, 3D NAND memory strings <NUM> may be either above or below device layer <NUM> (e.g., the peripheral circuit and SRAM cells therein). Nevertheless, bonding interface <NUM> can be formed between 3D NAND memory strings <NUM> and device layer <NUM> (e.g., the peripheral circuit and SRAM cells therein) after the bonding as illustrated in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate or the second substrate is thinned to form a semiconductor layer. In some embodiments, the first substrate of the first semiconductor structure, which is above the second substrate of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second substrate of the second semiconductor structure, which is above the first substrate of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer.

As illustrated in <FIG>, the substrate on top of the bonded 3D memory device (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. The thickness of the thinned substrate can be between about <NUM> and about <NUM>, such as between <NUM> and <NUM>, or between about <NUM> and about <NUM>, such as between <NUM> and <NUM>. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate on top of the bonded 3D memory device, another semiconductor layer may be formed by thinning silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. Pad contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

<FIG> illustrates a schematic block diagram of an exemplary system <NUM> having a 3D memory device with an on-die SRAM, according to some embodiments. <FIG> illustrates a schematic block diagram of system <NUM> having a 3D memory device with an on-die SRAM as a cache, according to some embodiments. <FIG> illustrates a schematic block diagram of system <NUM> having a 3D memory device with an on-die SRAM as a data buffer, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for operating a 3D memory device with an on-die SRAM as a cache, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for operating a 3D memory device with an on-die SRAM as a data buffer, according to some embodiments. Examples of the systems illustrated in <FIG> and <FIG> are described together with <FIG> and <FIG>, respectively. It is understood that the operations shown in methods <NUM> and <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

<FIG> illustrates a system <NUM> having an SRAM used as a cache or a data buffer, according to some embodiments. System <NUM> may have a host <NUM>, an I/O <NUM>, an SRAM <NUM>, a page buffer <NUM>, and a 3D NAND memory <NUM>. In some embodiments, SRAM <NUM> is formed on the same chip with page buffer <NUM> and 3D NAND memory <NUM>, as described above in detail. In some embodiments, SRAM <NUM>, page buffer <NUM>, and 3D NAND memory <NUM> form a 3D memory device <NUM>. SRAM <NUM> can be referred to as an on-die SRAM or an on-NAND SRAM. Data, e.g., program data and control instructions, may be transmitted bidirectionally between host <NUM> and I/O <NUM>, between I/O <NUM> and SRAM <NUM>, between SRAM <NUM> and page buffer <NUM>, and between 3D NAND memory <NUM> and page buffer <NUM>. Data transmission <NUM> between host <NUM> and page buffer <NUM> may be enabled or disabled, depending on the functions of SRAM <NUM>. For example, when SRAM <NUM> functions as a cache in 3D memory device <NUM>, data transmission <NUM> can be bi-directional data transmission between host <NUM> and page buffer <NUM>; when SRAM <NUM> functions as a data buffer in 3D memory device <NUM>, data transmission <NUM> may be disabled. That is, when SRAM <NUM> functions as a cache, data transmission <NUM> allows 3D memory device <NUM> to program 3D NAND memory <NUM> using program data from host <NUM> and host <NUM> to extract program data from page buffer <NUM> at the same time; when SRAM <NUM> functions as a data buffer, 3D memory device <NUM> sequentially buffers program data from host <NUM> in SRAM <NUM> and program the buffered program data into 3D NAND memory <NUM>.

Host <NUM> can be any suitable devices that generate the data, such as one or more processors. In some embodiments, host <NUM> includes a central processing unit (CPU), a graphics processor (e.g., graphics processing unit (GPU)), an application processor (AP), a general processor (e.g., APU, accelerated processing unit; GPGPU, general-purpose computing on GPU), or any other suitable processor. Input/output circuit <NUM> can be a high-speed, high-throughput input/output circuit as part of the peripheral circuits. In some embodiments, host <NUM> includes a system controller (e.g., a controller that controls various operations of system <NUM>) and/or a memory controller (e.g., a controller that controls various operations of 3D memory device <NUM>). Any suitable type of data generated by a host <NUM> is transferred to SRAM <NUM> of 3D memory device <NUM> through I/O <NUM>. Host <NUM> and 3D memory device <NUM> can be part of any suitable apparatus, for example, a virtual reality (VR)/augmented reality (AR) device (e.g., VR headset, etc.), handheld device (e.g., dumb or smart phone, tablet, etc.), wearable device (e.g., eyeglasses, wrist watch, etc.), automobile control station, gaming console, television set, laptop computer, desktop computer, netbook computer, media center, set-top box, global positioning system (GPS), printer, or any other suitable device.

In some embodiments, SRAM <NUM> includes a plurality of SRAM cells, arranged in an array or an arbitrary pattern. Details of SRAM cells can be found in the description of <FIG> and thus, are not repeated herein. SRAM <NUM> may be connected to page buffer <NUM>, which includes a plurality of buffering sections connected to respective pages in 3D NAND memory <NUM>.

SRAM <NUM> may be employed as a high-speed on-die cache of 3D memory device <NUM> to improve sequential programming. <FIG> illustrates system <NUM> in which SRAM <NUM> functions as a high-speed on-die cache. For ease of depiction, I/O <NUM> is omitted in <FIG>. In some embodiments, data is programmed into 3D NAND memory <NUM> in pages, and SRAM <NUM> is illustrated as a plurality of cache units <NUM> (i.e., <NUM>-<NUM>,. , <NUM>-K), each being configured to cache program data for programming a page in 3D NAND memory <NUM>. 3D NAND memory <NUM> may be depicted as a plurality of planes <NUM> (i.e., <NUM>-<NUM>,. , <NUM>-M), each represents memory cells formed by a word line and intersecting memory strings. A plane <NUM> may include a plurality of pages of memory cells. K and M may each be a positive integer and may or may not be the same as each other. In operation, the plurality of cache units <NUM> can cache program data of the same batch into page buffer <NUM> at the same time. Cache units <NUM> further inputs cached program data into page buffer <NUM>, which then inputs the cached program data into respective pages in planes <NUM>. In some embodiments, host <NUM> sequentially (e.g., one batch immediately after another batch) transmits batches of program data, e.g., (N-<NUM>)th, (N-<NUM>)th, (N-<NUM>)th, Nth, (N+<NUM>)th, and (N+<NUM>)th, into SRAM <NUM> and/or page buffer <NUM>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which 3D memory device <NUM> receives control instructions, from host <NUM>, to condition 3D memory device <NUM> for a cache program operation. In some embodiments, 3D memory device <NUM> follows the control instructions to initialize SRAM cells of SRAM <NUM>, e.g., erase data in/empty SRAM cells so SRAM <NUM> is ready to receive program data.

At operation <NUM>, 3D memory device <NUM> programs an (N-<NUM>)th batch of program data into respective pages. At the same time, 3D memory device <NUM> caches an Nth batch of program data in a respective space (e.g., cache unit) in SRAM <NUM> and check the status of an (N-<NUM>)th batch of program data. SRAM <NUM> can cache a plurality of batches of program data. In some embodiments, SRAM caches at most three batches of program data, e.g., as (N-<NUM>)th, (N-<NUM>)th, and Nth batches of program data shown in <FIG>. Each batch of program data (e.g., (N-<NUM>)th batch, (N-<NUM>)th batch, and Nth batch) may include program data for one or more pages in respective planes. For example, each batch of program data may include program data for K pages and the program data for each page can be cached in a respective cache unit (e.g., <NUM>-<NUM>,. , <NUM>-K). The cached batch of program data may be a backup copy of the respective program data and can be programmed into 3D NAND memory <NUM> if necessary, e.g., the programming of respective program data to 3D NAND memory <NUM> fails. Details are described below.

In some embodiments, checking the status of (N-<NUM>)th batch of program data, programming (N-<NUM>)th batch of program data, and caching Nth batch of program data, are performed at the same time or in a same time span. For example, these operations may start and complete at about the same time or may have overlapping operation times. In some embodiments, when 3D memory device <NUM> is programming (N-<NUM>)th batch of program data from page buffer <NUM> into 3D NAND memory <NUM>, 3D memory device <NUM> is caching Nth batch of program data from host <NUM> and checking the status of (N-<NUM>)th batch of program data. 3D memory device <NUM> may program (N-<NUM>)th batch of program data by transmitting a copy of (N-<NUM>)th batch of program data from page buffer <NUM>. The copy of (N-<NUM>)th batch of program data may be formed by buffering (N-<NUM>)th batch of program data (e.g., before the caching of Nth batch of program data) from host <NUM> or by buffering the backup copy of (N-<NUM>)th batch of program data from SRAM <NUM>. In some embodiments, 3D memory device <NUM> programs (N-<NUM>)th batch of program data by loading the copy of (N-<NUM>)th batch of program data from page buffer <NUM> to 3D NAND memory <NUM> when caching Nth batch of program data into SRAM <NUM> from host <NUM>. The copy of (N-<NUM>)th batch of program data may be formed by buffering (N-<NUM>)th batch of program data through data transmission <NUM> from host <NUM>, e.g., before the programming starts. In some embodiments, the backup copy of (N-<NUM>)th batch of program data is cached in SRAM <NUM> when 3D memory device <NUM> is checking the status of an (N-<NUM>)th batch of program data. In some embodiments, (N-<NUM>)th batch of program data is cached from host <NUM> into SRAM <NUM> to form a backup copy of the (N-<NUM>)th batch of program data when (N-<NUM>)th batch of program data is being programmed into respective pages in 3D NAND memory <NUM>.

In some embodiments, the checking of the status of the (N-<NUM>)th batch of program data includes determining whether the programming of (N-<NUM>)th batch of program data was successful. In some embodiments, if the programming of (N-<NUM>)th batch of program data failed, 3D memory device <NUM> retrieves a backup copy of (N-<NUM>)th batch of program data from SRAM <NUM>, buffers the backup copy of (N-<NUM>)th batch of program data in page buffer <NUM>, and programs the backup copy of the (N-<NUM>)th batch of program data into respective pages in 3D NAND memory <NUM>. In some embodiments, SRAM <NUM> maintains the backup copy of (N-<NUM>)th batch of program data when checking the status of programming of (N-<NUM>)th batch of program data and removes the backup copy of (N-<NUM>)th batch of program data when the programming of (N-<NUM>)th batch of program is successful. SRAM <NUM> may then have space for caching another batch (e.g., (N+<NUM>)th batch of program data) of program data.

Nth batch of program data may be cached into SRAM <NUM> to form a backup copy of Nth batch of program data when (N-<NUM>)th batch of program data is being programmed into 3D NAND memory <NUM>. The backup copy of Nth batch of program data in SRAM <NUM> may be maintained until it is determined the programming of Nth batch of program data into 3D NAND memory <NUM> is successful. In some embodiments, host <NUM> reads out Nth batch of program data from SRAM <NUM> for further processing and/or storage, e.g., before Nth batch of program data is deleted from SRAM <NUM>. For example, host <NUM> can store the read-out Nth batch of program data at another location. In some embodiments, host <NUM> deletes a copy of the Nth batch of program data from the host after Nth batch of program data is cached into SRAM <NUM>. In some embodiments, 3D memory device <NUM> checks the status of (N-<NUM>)th batch of program data when Nth batch of program data is being programmed into respective pages in 3D NAND memory <NUM>. Meanwhile, 3D memory device <NUM> may cache an (N+<NUM>)th batch of program data in respective space in SRAM <NUM>. In some embodiments, host <NUM> reads out program data from page buffer <NUM> for further processing.

In some embodiments, 3D memory device <NUM> sequentially repeats the operation <NUM> for subsequent batches of program data. At operation <NUM>, 3D memory device <NUM> programs Nth batch of program data into respective pages. At this operation, 3D memory device <NUM> also caches (N+<NUM>)th batch of program data in a respective space in SRAM <NUM> and check the status of (N-<NUM>)th batch of program data. At operation <NUM>, 3D memory device <NUM> programs (N+<NUM>)th batch of program data into respective pages. At this operation, 3D memory device <NUM> also caches (N+<NUM>)th batch of program data in a respective space in SRAM <NUM> and check the status of Nth batch of program data.

In some embodiments, 3D memory device <NUM> may sequentially cache a plurality of batches of program data and program the cached program data into 3D NAND memory <NUM>. For example, 3D memory device <NUM> may sequentially cache a backup copy of (N-<NUM>)th batch of program data, a backup copy of (N-<NUM>)th batch of program data, and a backup copy of Nth batch of program data into SRAM <NUM>. 3D memory device <NUM> may then sequentially program the backup copies of (N-<NUM>)th batch of program data, (N-<NUM>)th batch of program data, and Nth batch of program data into respective pages of 3D NAND memory <NUM> through page buffer <NUM>. In some embodiments, 3D memory device <NUM> checks the status of (N-<NUM>)th batch of program data after it has been programmed. If the programming was successful, 3D memory device <NUM> may delete the backup copy of (N-<NUM>)th batch of program data from SRAM <NUM>; if the programming failed, 3D memory device <NUM> may re-program 3D NAND memory <NUM> (e.g., repeatedly if necessary) using the backup copy of (N-<NUM>)th batch of program data until the status is successful. SRAM <NUM> may then have space for caching next the next batch of program data (e.g., (N+<NUM>)th batch of program data). In some embodiments, host <NUM> deletes copies of (N-<NUM>)th batch of program data, (N-<NUM>)th batch of program data, and Nth batch of program data after these batches of program data are cached in SRAM <NUM>.

3D NAND memory <NUM> may include a multi-level cell (MLC) NAND memory device, in which a number of the plurality of pages corresponds to a number of bits stored in a memory cell. In some embodiments, 3D NAND memory <NUM> includes a triple-level cell (TLC) NAND memory device packed in a RAM-less application environment, such as an eMMC or a UFS. In an example, to cache three batches of program data for a TLC NAND memory device with <NUM> planes, SRAM <NUM> has at least <NUM> kB of storage space.

SRAM <NUM> may also be employed as an on-die data buffer of 3D memory device <NUM>. <FIG> illustrates system <NUM> in which SRAM <NUM> functions as an on-die data buffer. For ease of depiction, I/O <NUM> is omitted in <FIG>. In some embodiments, program data is programmed into 3D NAND memory <NUM> in pages, and SRAM <NUM> is illustrated as a plurality of data buffer units <NUM> (i.e., <NUM>-<NUM>,. , <NUM>-L), each being configured to buffer program data for programming a page in 3D NAND memory <NUM>. 3D NAND memory <NUM> may be depicted as a plurality of planes <NUM> (i.e., <NUM>-<NUM>,. , <NUM>-M). M and L may each be a positive integer and may or may not be the same as each other. In operation, the plurality of data buffer units <NUM> can provide storage space to buffer program data before it is transmitted into page buffer <NUM>. This allows program data stored in host <NUM> and to be programmed into 3D NAND memory <NUM> to be stored on the same chip as 3D memory device <NUM>, releasing the main cache/buffer in host <NUM> for storing this program data. SRAM <NUM> also reduce bandwidth in data buses (e.g., between 3D memory device <NUM> and host <NUM>) for transmitting this program data during a programming operation. Instead, data transmission and processing can be performed in 3D memory device <NUM>. Resources in host <NUM> that are used to store, process, and transmit the program data can be used for other purposes/operations. As shown in <FIG>, 3D memory device <NUM> receives program data corresponding to different word lines from host <NUM>. The program data corresponding to word lines is depicted as WL0,. The program data can be transmitted from host <NUM> to SRAM <NUM> sequentially, in groups, or in an arbitrary pattern, before it is buffered into page buffer <NUM>. The depiction of program data WL0,. , WLP in 9B in each data buffer unit <NUM> is merely for illustrating the program data for programming a page and do not indicate sequentially operation of program data.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which 3D memory device <NUM> receives control instructions, from host <NUM>, to condition 3D memory device <NUM> for a first pass program and a second pass program on memory cells of a page in 3D NAND memory <NUM>. In some embodiments, 3D memory device <NUM> follows the control instructions to initialize SRAM cells of SRAM <NUM>, e.g., erase data in/empty SRAM cells so SRAM <NUM> is ready to receive program data.

At operation <NUM>, 3D memory device <NUM> buffers first program data for the first pass program and second program data for the second pass program in SRAM <NUM>. In some embodiments, a word line corresponds to its respective program data that includes the first program data and the second program data for programming the memory cells formed by the word line and intersecting memory strings. That is, for example, WL0 refers to first program data and second program data for programming memory cells formed by WL0 (i.e., word line <NUM> and intersecting memory cells). In some embodiments, the amount of program data buffered in SRAM <NUM> is determined based on the storage capacity of SRAM <NUM>. Thus, program data corresponding to WL0,. , WLP may represent a portion or the entirety of the program data to be programmed in 3D NAND memory <NUM>. In some embodiments, the first pass program is a coarse program and the second pass program is a fine program.

The first program data and the second program data for programming memory cells formed by one or more word lines can be buffered into SRAM <NUM> at any suitable order before it is loaded in page buffer <NUM> for programming. For example, the first and second program data for programming memory cells formed by a first word line and a second word line can be buffered from host <NUM> at the same time (e.g., before performing the first pass program using the first program data), or be buffered separately (e.g., the second program data can be buffered after the first pass program is completed). In various embodiments of the present disclosure, the first and second program data is each buffered in SRAM <NUM> before it is transmitted into page buffer <NUM>. In some embodiments, first and second program data for programming memory cells in all planes of 3D NAND memory <NUM> is buffered and stored SRAM <NUM> before being loaded into page buffer <NUM>.

At operation <NUM>, 3D memory device <NUM> sequentially performs the first pass program using the first program data on memory cells formed by a first word line and a second word line. 3D memory device <NUM> may retrieve the buffered first program data from SRAM <NUM> and transmit it to page buffer <NUM> before it is programmed to respective memory cells in 3D NAND memory <NUM>. The memory cells formed by or corresponding to a word line, as described in the present disclosure, refer to the memory cells formed by the word line and memory strings intersecting the word line. In some embodiments, the memory cells are programmed in pages, e.g., the first pass program may be performed on all memory cells formed by the memory strings and the first word line before it is performed on the memory cells formed by the memory strings and the second word line.

The memory cells being programmed may be MLCs. For example, each memory cell being programmed may be a quad-level cell (QLC) that has four threshold voltage states (e.g., lower page data (LP), middle page data (MP), upper page data (UP), and extra page data (XP)) for storing <NUM><NUM> bits of data. The first program data and the second program data for programming each memory cell may be configured to program the memory cell to desired threshold voltage states. Table I illustrates an exemplary page map for QLCs in a page to be programmed. Table I illustrates the order the memory cells are programmed respectively in the first pass program and the second pass program. In TABLE I, string <NUM> - string <NUM> refer to the six memory strings intersecting with the word lines, which are denoted using "WL#".

In some embodiments, TABLE I shows an order a pass program (e.g., first or second pass program) is performed. For example, 3D memory device <NUM> can sequentially program the four threshold voltage states (i.e., LP, MP, UP, and XP) into each memory cell and sequentially program the memory cells formed by memory string <NUM> to memory string <NUM> and a word line (e.g., word line <NUM>, <NUM>, <NUM>, or <NUM>). After the memory cells in each page formed by the memory strings and one word line is programmed, 3D memory device <NUM> proceeds to program the memory cells formed by the memory strings and the next word line. In this operation, the first pass program is sequentially performed on the memory cells formed by string0 to string0 with the first and second word lines (e.g., WL0 and WL1) according to the order provided in Table I.

At operation <NUM>, 3D memory device <NUM> retrieves the second program data from SRAM <NUM> and performs the second pass program on memory cells formed by the first word line using the second program data when the first pass program is completed. In some embodiments, when the first pass program, performed on the memory cells formed by the first and second word lines and all the memory strings (e.g., string0 to string5), is completed, 3D memory device <NUM> starts performing the second pass program automatically, e.g., without receiving permission from host <NUM>. TABLE II illustrates an exemplary order memory cells in the page are programmed with a first pass program (e.g., a coarse program, shown as "1st" in Table II) and a second pass program (e.g., a fine program, shown as "2nd" in TABLE II).

As shown in TABLE II, 3D memory device <NUM> may sequentially perform the first pass program on memory cells formed by string0 to string5 with the first and second word lines (e.g., WL0 and WL1, as described in Operation <NUM>) before sequentially performing the second pass program on memory cells formed by string0 to string5 with the first word line. In some embodiments, data (e.g., program data and/or control instructions) for performing first and second pass programs is transmitted in 3D memory device <NUM> without occupying data buses in host <NUM> and between host <NUM> and 3D memory device <NUM>. In some embodiments, the order shown in Table II is predetermined before the first and the second pass programs are performed. 3D memory device <NUM> may repeat the operations described above for memory cells formed by other word lines, e.g., memory cells corresponding to WL2 and WL3, until the programming of memory cells is completed.

3D NAND memory <NUM> may include a multi-level cell (MLC) NAND memory device, in which a number of the plurality of pages corresponds to a number of bits stored in a memory cell. In an example, to buffer first and second program data for memory cells formed by two word lines in a QLC NAND memory device with <NUM> planes, SRAM <NUM> has at least <NUM> MB of storage space.

In some embodiments according to claim <NUM>, a 3D memory device includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

In some embodiments not forming part of the claimed invention, the first semiconductor structure includes a substrate, the peripheral circuit on the substrate, the array of SRAM cells on the substrate and non-overlapping with the peripheral circuit, and the first bonding layer above the peripheral circuit and the array of SRAM cells.

In some embodiments, the second semiconductor structure includes the second bonding layer above the first bonding layer, a memory stack above the second bonding layer, the array of 3D NAND memory strings extending vertically through the memory stack, and a semiconductor layer above and in contact with the array of 3D NAND memory strings.

In some embodiments, the 3D memory device further includes a pad-out interconnect layer above the semiconductor layer.

In some embodiments, the semiconductor layer includes at least one of polysilicon or single-crystal silicon.

In some embodiments, the second semiconductor structure includes a substrate, a memory stack above the substrate, the array of 3D NAND memory strings extending vertically through the memory stack, and the second bonding layer above the memory stack and the array of 3D NAND memory strings.

In some embodiments not forming part of the claimed invention, the first semiconductor structure includes the first bonding layer above the second bonding layer, the peripheral circuit above the first bonding layer, the array of SRAM cells above the first bonding layer and non-overlapping with the peripheral circuit, and a semiconductor layer above and in contact with the peripheral circuit and the array of SRAM cells.

In some embodiments according to the claimed invention, the peripheral circuit and the array of SRAM cells are stacked one over another.

In some embodiments, each SRAM cell includes a plurality of transistors.

In some embodiments, the first semiconductor structure includes a first interconnect layer vertically between the first bonding layer and the array of SRAM cells, and the second semiconductor structure includes a second interconnect layer vertically between the second bonding layer and the array of 3D NAND memory strings.

In some embodiments, the array of SRAM cells are electrically connected to the array of 3D NAND memory strings through the first and second interconnect layers and the first and second bonding contacts.

In some embodiments, the 3D memory device is packaged in at least one of an eMMC or a UFS.

In some embodiments according to claim <NUM>, a method for forming a 3D memory device includes forming a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts, forming a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts, and bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

In some embodiments, forming the first semiconductor structure includes forming the peripheral circuit and the array of SRAM cells on a first substrate, forming a first interconnect layer above the peripheral circuit and the array of SRAM cells, and forming the first bonding layer above the first interconnect layer.

In some embodiments, forming the peripheral circuit and the array of SRAM cells includes forming a plurality of transistors on the first substrate.

In some embodiments, forming the second semiconductor structure includes forming a memory stack above a second substrate, forming the array of 3D NAND memory strings extending vertically through the memory stack, forming a second interconnect layer above the array of 3D NAND memory strings, and forming the second bonding layer above the second interconnect layer.

In some embodiments, the second semiconductor structure is above the first semiconductor structure after the bonding.

In some embodiments, the method further includes thinning the second substrate to form a semiconductor layer after the bonding and forming a pad-out interconnect layer above the semiconductor layer.

In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding.

In some embodiments, the method further includes thinning the first substrate to form a semiconductor layer after the bonding and forming a pad-out interconnect layer above the semiconductor layer.

In some embodiments, the bonding includes hybrid bonding.

In some embodiments according to claim <NUM>, the method for operating a 3D memory device having an input/output circuit, an array of on-die SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of on-die SRAM cells, storing the data in the array of on-die SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of on-die SRAM cells.

In some embodiments, the method further includes transferring the data between the array of 3D NAND memory strings and the array of on-die SRAM cells through a plurality of bonding contacts.

In some embodiments, the method further includes transferring data from the array of on-die SRAM cells through the input/output circuit.

In some embodiments, storing the data in the array of on-die SRAM cells and programming the data into the array of 3D NAND memory strings are performed at a same time.

In some embodiments, storing the data in the array of on-die SRAM cells and programming the data into the array of 3D NAND memory strings are performed sequentially.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional 3D memory device (<NUM>; <NUM>), comprising:
a first semiconductor structure (<NUM>; <NUM>) comprising a peripheral circuit (<NUM>; <NUM>), an array of static random-access memory SRAM cells (<NUM>; <NUM>), a first bonding layer (<NUM>; <NUM>) comprising a plurality of first bonding contacts (<NUM>; <NUM>);
a second semiconductor structure (<NUM>; <NUM>) comprising a substrate (<NUM>; <NUM>; <NUM>), a memory stack (<NUM>; <NUM>) having an array of 3D NAND memory strings (<NUM>; <NUM>) extending vertically through the memory stack (<NUM>; <NUM>), and a second bonding layer (<NUM>; <NUM>) comprising a plurality of second bonding contacts (<NUM>; <NUM>); and
a bonding interface (<NUM>; <NUM>) between the first bonding layer (<NUM>; <NUM>) and the second bonding layer (<NUM>) and vertically between the first semiconductor structure (<NUM>; <NUM>) and the second semiconductor structure (<NUM>; <NUM>), wherein the first bonding contacts (<NUM>; <NUM>) are in contact with the second bonding contacts (<NUM>; <NUM>) at the bonding interface (<NUM>; <NUM>);
characterized in that
the second semiconductor structure (<NUM>; <NUM>) is formed such that the memory stack (<NUM>; <NUM>) having the array of 3D NAND memory strings (<NUM>; <NUM>) is arranged vertically between the second bonding layer (<NUM>; <NUM>) and the substrate (<NUM>; <NUM>; <NUM>) of the second semiconductor structure (<NUM>; <NUM>), wherein the peripheral circuit (<NUM>; <NUM>) and the array of SRAM cells (<NUM>; <NUM>) are stacked one over another.