Patent Description:
For some devices it is highly desirable to have a flat die. For example, sensing devices, such as focal plane arrays, can include die that can have sensors and/or circuitry. Conventional techniques for attempting to achieve flat die, e.g., to remove bow in the die, may include the use of glass beads in an epoxy bondline to control thickness. Weights can be used to flatten the device after epoxy application. However, some known techniques to remove bow in a die may put an assembly, such as focal planes, at risk, such as due to weight contact with optical surface. Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit are known from <CIT>. Therein disclosed is a sensor chip assembly comprising an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector. Also disclosed is a method of manufacturing a sensor chip assembly, the method comprising providing a radiation-shielding wafer including plurality of through wafer vias (TWVs), providing a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), fabricating a first wafer level bonding structure on a first surface of the CMOS ROIC, fabricating a second wafer level bonding structure on a second surface of the radiation-shielding wafer, and forming a first direct oxide bond between the first wafer level bonding structure and the second wafer level bonding structure to electrically and physically couple to the radiation-shielding wafer and the CMOS ROIC. <CIT> discloses a method of accommodating CTE mismatch in a Focal Plane Array (FPA) having a readout integrated circuit (ROIC) substrate with a first coefficient of thermal expansion (CTE) and a detector array with a second CTE. The method comprises printing an ROIC on a first wafer and thinning said first wafer to a first thickness after said printing. The method further comprises selecting a second wafer of a third thickness, selecting as a shim layer a material having a second thickness and a specified CTE, bonding the first wafer, second wafer, and shim layer together simultaneously to form a balanced wafer stack having a specified composite average CTE, wherein the composite average CTE is determined by the relative thicknesses of the wafers and the shim layer, and also by the composition of the shim layer, and wherein the shim layer is disposed between the wafers. The method further comprises dicing the wafer stack into individual dies, wherein each die contains one ROIC and hybridizing the individual dies by attaching the detector array to the ROIC of a die.

In accordance with the present invention, there is provided a method and integrated circuit assembly as defined by claims <NUM> and <NUM>.

Embodiments of the invention provide methods and apparatus for processing a wafer using oxide deposited for bonding a shim at the wafer level at room temperature at atmosphere, for example. Embodiments can include bow compensation to reduce bow in the die. Integrating bonding oxide deposition into a sensor chip assembly (SCA) process flow reduces the likelihood of damaging a delicate front side of the imager, for example.

In embodiments, an oxide layer for shim attachment is applied before thinning to prevent damage to the wafer surface. It will be appreciated that a wafer providing a photodetector should have a polished and defect-free surface to enhance detector performance. Embodiments can include ion implantation and annealing to bond multiple wafers using oxide-to-oxide bonding for production of silicon-based imaging arrays. According to the claimed invention, a first wafer is provided as a detector wafer bonded to a second wafer provided as a ROIC (read out integrated circuit) wafer. According to the claimed invention, the first wafer is bonded to the second wafer with an oxide layer. This is a particular kind of DBH bonding to attach the first and second wafers. In embodiments, DBH bonding refers to using direct bond hybridization to form a covalent bonding between wafers.

After the first and second wafers are bonded, oxide is deposited to the backside of the ROIC wafer prior to detector thinning. Oxide is deposited to the backside of the ROIC wafer after which a shim is bonded to the SCA. In embodiments, the shim is bonded to the assembly using low temperature, e.g., room temperature, lower than the DBH temperatures used to bond the first and second wafers. The illustrative steps enable assembly of a CTE (coefficient of thermal expansion) engineered structure for focal plane array (FPA) detectors, for example. In addition, wafer bow can be modified to promote die flatness in the final assembly. Also, the bonded wafers increase rigidity to allow post bond processing of thin outside wafers. Further, thin film deposition for oxide, for example, can improve SCA/die Z-height control/flatness over adhesives. In embodiments, bonding oxide is deposited by PECVD or PVD have high uniformity (<NUM> ±500Å), whereas epoxy has a large variation (e.g., <NUM>-<NUM>±50000Å) across a <NUM> wafer.

It will be appreciated that increasing a flatness of an optical surface is desirable to increase performance, resolution, and the like, of a sensing device, such as a device in a FPA. By decreasing bow in the die, the optical plane of the sensor is flattened for enhanced sensor performance.

With use of the above illustrative processing, an example process allows for standard wafer thicknesses to enable standard wafer processing equipment (e.g., no handling <NUM>-<NUM> thick wafers).

The method of the claimed invention comprises: deploying a circuit assembly having a first wafer bonded to a second wafer with an oxide layer, wherein the first wafer comprises a detector and the second wafer comprises a read out integrated circuit (ROIC) wherein a first surface of the first wafer is bonded to a first surface of the second wafer; creating a bonding oxide on a second surface of the second wafer; thinning the first wafer after depositing the bonding oxide; annealing the circuit assembly; applying a coating over at least a portion of the first wafer after annealing the circuit assembly; polishing the bonding oxide on the second surface of the second wafer after applying the coating over at least the portion of the first wafer; securing a shim to the polished bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly; and removing the coating after securing the shim.

A method can further include one or more of the following features: the circuit assembly comprises a sensor circuit assembly with interconnection embedded in the bond interface, the circuit assembly provides a sensor for a focal plane array, the circuit assembly does not comprise epoxy, applying photoresist material to the first wafer prior to bonding the shim, applying a non-photosensitive material to the first wafer prior to bonding the shim, removing the photoresist material prior to annealing the circuit assembly, removing the non-photosensitive material prior to annealing the circuit assembly, the bonding oxide bonding oxide has a uniformity of about <NUM> ±500Å, and/or the shim comprises a material selected from the group consisting of Silicon, AlN, and sapphire.

According to the claimed invention an integrated circuit assembly comprises:
a circuit assembly having a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer, wherein the first wafer comprises a detector and the second wafer comprises a read out integrated circuit (ROIC); a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished; and a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.

An assembly can further include one or more of the following features: the circuit assembly comprises a sensor circuit assembly with interconnection embedded in the bond interface, and/or the circuit assembly does not comprise epoxy.

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following description of the drawings in which:.

<FIG> shows example process steps for providing an assembly having a shim in which bonding oxide deposition is integrated into the process for minimizing damage to a front side of the assembly, such as an imager forming part of a focal plane array (FPA). The assembly can include an oxide-bonded shim to reduce bow in the sensor and flatten an optical plane for enhanced sensor performance.

In step <NUM> of <FIG> and referring to <FIG>, a first wafer <NUM> is bonded to a second wafer <NUM> with a bonding oxide layer <NUM> to form an assembly <NUM>, which can be provided as a sensor chip assembly (SCA). In embodiments, DBH bonding can be used to attach the first and second wafers <NUM>, <NUM> with integrated interconnection layer for electrical connections using embedded metal posts and high temperature annealing in a manner well known in the art.

In embodiments, the first wafer <NUM> corresponds to a detector and the second wafer <NUM> corresponds to a read out integrated circuit (ROIC). As is known in the art, a ROIC refers to an integrated circuit configured to read data from certain types of detectors, such as infrared sensors. In general, the ROIC accumulates photocurrent from pixels for transferring the respective pixel signals onto output taps for readout. The pixels can form a focal plane array to detect a variety of signals.

It is understood that the first and second wafers can be provided with any suitable functionality and features to meet the needs of a particular embodiment. It is understood that a SCA having a first wafer provided as a detector and a second wafer provided as a ROIC is one particular embodiment that should not be construed as limiting with respect to the functionality of the wafers in an assembly. The assembly can have varying thicknesses depending upon the application. An illustrative thickness is about <NUM>.

In step <NUM>, and referring to <FIG>, a bonding oxide <NUM> for later attachment of a shim is deposited onto the second wafer <NUM> of the assembly <NUM>. In embodiments, the assembly <NUM> is flipped prior to application of the bonding oxide <NUM> using ion implantation and annealing. The bonding oxide <NUM> has a thickness selected to achieve certain tuning of wafer bow/flatness characteristics. It will be appreciated that in many applications, such as FPAs, it is desirable to minimize bow of the detectors and/or complete hybrid focal plane structure.

In step <NUM>, referring to <FIG>, the first wafer <NUM> is processed so that a thickness <NUM> of the first wafer <NUM> is reduced to a desired level, such as about <NUM>. For an illustrative visible hybrid CMOS imager the range is about <NUM> - <NUM>, depending on the required spectral response in the near infrared spectrum.

In embodiments, the bonding oxide layer <NUM> to later attach a shim is applied prior thinning the first wafer <NUM>. With this arrangement, the likelihood of damage to the first wafer <NUM> (i.e., the detector) is reduced as compared with conventional processing techniques in which an attachment mechanism is applied to second wafer <NUM> (i.e., the ROIC) after wafer thinning (backgrind and CMP) so that the assembly <NUM> must be flipped and possibly damaged. In the conventional process, the bonding oxide is applied after the SCA completion. This requires the fragile imaging surface of the top device to be place face down in onto chucks and handled with vacuum tooling which can scratch the surface, causing optical defects or circuit damage.

In step <NUM>, referring to <FIG>, the assembly <NUM> is subject to implant and laser anneal to form layer <NUM> for the first wafer <NUM>. This process is used to apply a conductive layer to the backside surface after hybrid processing has completed, where thermal anneal temperatures (><NUM>) cannot be tolerated.

In optional step <NUM>, referring to <FIG>, a coating <NUM>, such as an optical anti-reflective coating (ARC) is applied to the assembly. In embodiments, the coating <NUM> has a first portion 120a covering a first region of the detector layer of the first wafer <NUM> and a second portion 120b covering a second region of the detector layer. Any damage to the multi-layer ARC films will result in reduced optical performance of the sensor.

In step <NUM>, referring to <FIG>, the assembly <NUM> is etched to singulate the detector wafer into individual die <NUM> of the second wafer <NUM> to form multiple detectors <NUM>, <NUM> on respective die.

In step <NUM>, referring to <FIG>, a photoresist coating <NUM> is applied to the assembly <NUM> to protect the detectors <NUM>, <NUM>. The coated assembly <NUM> can be baked to cure the photoresist material, as needed.

In step <NUM>, referring to <FIG>, the bonding oxide layer <NUM> that was applied to second wafer <NUM> for bonding a shim is polished, such as by CMP (chemical mechanical planarization) polishing to produce a surface roughness acceptable for fusion bonding. In embodiments, the assembly <NUM> is flipped for polishing.

In step <NUM>, referring to <FIG>, a shim <NUM> is applied to the oxide layer <NUM> on the surface of the second wafer <NUM>. In embodiments, the shim <NUM> can be bonded at or about room temperature. In one embodiment, the shim <NUM> is manually applied to the assembly <NUM>. In other embodiments, suitable machines are used to attach the shim <NUM>. It will be appreciated that the annealing temperature for oxide activation of layer <NUM> should be less that the annealing temperature used during annealing to DBH bond the first and second wafers <NUM> and <NUM> of the assembly <NUM> in step <NUM>. For example, the interconnection DBH bond can occur at <NUM>, whereas the shim bond can occur at <NUM>, so the shim bond will not affect the interconnection.

In embodiments, the shim <NUM> can comprise silicon with a thickness and rigidity to achieve a desired reduction in wafer bow. Examples of shim materials include Silicon(<NUM>-<NUM>), AlN (<NUM>-<NUM>), and sapphire (<NUM>-<NUM>).

In step <NUM>, referring to <FIG>, the photoresist material <NUM> can be removed from the assembly <NUM> which can then be annealed in step <NUM>. In embodiments, annealing of the assembly <NUM> is performed at a temperature in the order of <NUM> degrees. The anneal converts the weak van der Waal bond to a very strong covalent bond to increase the wafer bond strength, rendering the bond permanent.

In embodiments, by using the shim, pre-existing bow in the die is significantly reduced or eliminated resulting in an ultra-flat optical surface. In addition, the use of bonding oxide for securing the shim to the assembly generates minimal, if any, voids, which may be an issue in epoxy-based shim processing. Application epoxy is generally challenging to deliver thin, uniform layers without voided regions due to the thick viscosity and deposition methods. Any voids in the layer will become a bond void after wafer bonding, leading to poor thermal and mechanical properties.

It is understood that embodiments of the invention are applicable to a wide range of devices having die for which flatness is desirable, such as SCAs and FPAs. A sensor chip assembly (SCA) or focal plane array (FPA) refers to an image sensing device having an array of light-sensing pixels at the focal plane of a lens. FPAs may be useful for imaging applications, such as taking pictures or videos, as well as non-imaging applications. Example applications include spectrometry, LIDAR, guidance systems, inspection, wavefront sensing, infrared astronomy, manufacturing inspection, thermal imaging for firefighting, medical imaging, and infrared phenomenology. Some FPAs operate by detecting photons at particular wavelengths and generating an electrical charge, voltage, or resistance in relation to the number of photons detected at each pixel. This charge, voltage, or resistance is then measured, digitized, and used to construct an image of the object, scene, or phenomenon that emitted the photons.

In illustrative embodiments, a die can have an example bow of +/- <NUM> microns prior to processing and an example bow of about <NUM> microns after processing with an example range of about ±5µms. In an illustrative embodiment, a die having a pre-processing bow of about <NUM> microns and a post-processing bow of about <NUM> microns provides a <NUM>% reduction in bow. An example shim will have a bow of less than about <NUM> microns.

Claim 1:
A method, comprising:
deploying a circuit assembly having a first wafer (<NUM>) bonded to a second wafer (<NUM>) with an oxide layer (<NUM>), wherein the first wafer (<NUM>) comprises a detector and the second wafer (<NUM>) comprises a read out integrated circuit, ROIC, wherein a first surface of the first wafer (<NUM>) is bonded to a first surface of the second wafer (<NUM>);
creating a bonding oxide (<NUM>) on a second surface of the second wafer (<NUM>);
thinning the first wafer (<NUM>) after depositing the bonding oxide (<NUM>);
annealing the circuit assembly;
applying a coating (<NUM>) over at least a portion of the first wafer (<NUM>) after annealing the circuit assembly;
polishing the bonding oxide (<NUM>) on the second surface of the second wafer (<NUM>) after applying the coating (<NUM>) over at least the portion of the first wafer (<NUM>):
securing a shim (<NUM>) to the polished bonding oxide (<NUM>) on the second surface of the second wafer (<NUM>) to reduce bow of the circuit assembly; and
removing the coating (<NUM>) after securing the shim (<NUM>).