Patent Description:
Oxide semiconductor devices including a transparent semiconductor material having a wide bandgap of <NUM> eV or greater have been studied for many years. The oxide semiconductor devices are mass-produced as driving devices for large-area OLED TVs.

As the degree of device integration of semiconductor devices increases, the devices are required or desired to be smaller. In the case of a transistor, as a size thereof is reduced, a channel length may decrease. A decrease in the channel length of the transistor may cause or may exacerbate a short channel effect that results in a shift of a threshold voltage. Document <CIT> discloses a transistor in which changes in threshold voltage caused by a reduction on the physical size of said transistor are prevented.

Provided are transistors having improved operation reliability.

However, problems to be solved are not limited to the above disclosure. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, and/or may be learned by practice of various example embodiments.

According to a claimed embodiment, a transistor as defined by claim <NUM> includes an oxide semiconductor layer; a source electrode and a drain electrode on the oxide semiconductor layer and spaced apart from each other; a gate electrode spaced apart from the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; and a graphene layer between the gate electrode and the gate insulating layer and doped with a metal.

The metal doped in the graphene layer may be different from a metal included in the oxide semiconductor layer.

The metal doped into the graphene layer may include at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), thallium (TI), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W).

The metal may be doped in an amount of <NUM> at% or more and <NUM> at% or less with respect to a total amount of the graphene layer.

A work function of the graphene layer may be <NUM> eV or more and <NUM> eV or less.

A threshold voltage of the transistor may be a positive value when a current flowing from the drain electrode to the source electrode is <NUM>-<NUM>A/micron.

A thickness of the graphene layer may be less than a thickness of the gate electrode.

The thickness of the graphene layer may be <NUM> or less.

The oxide semiconductor layer may include at least one of In, Zn, Sn, Ga, and Hf.

The graphene layer may be in contact with two or more surfaces of the gate electrode.

The graphene layer may be in contact with a lower surface of the gate electrode and a side surface of the gate electrode.

The gate insulating layer may at least partially cover two or more surfaces of the gate electrode.

The gate insulating layer may at least partially cover a lower surface of the gate electrode and a side surface of the gate electrode.

The gate insulating layer may be in contact with at least one of the source electrode and the drain electrode.

At least one of the source electrode and the drain electrode may include a stepped shape.

At least one of the source electrode and the drain electrode may include a first region having a first thickness and a second region having a second thickness less than the first thickness, wherein the second region may be closer to the gate electrode than the first region.

The source electrode, the drain electrode, and the gate insulating layer may be on a same surface of the oxide semiconductor layer.

The source electrode and the drain electrode may be on a first surface of the oxide semiconductor layer, and the gate insulating layer may be on a second surface, different from the first surface of the oxide semiconductor layer.

The gate insulating layer may include a first gate insulating layer in contact with a first surface of the oxide semiconductor layer and a second gate insulating layer in contact with a second surface, different from the first surface of the oxide semiconductor layer. The gate electrode may include a first gate electrode on the first gate insulating layer and a second gate electrode on the second gate insulating layer. The graphene layer may include a first graphene layer between the first gate insulating layer and the first gate electrodes and a second graphene layer between the second gate insulating layer and the second gate electrode.

The source electrode, the oxide semiconductor layer, and the drain electrode may be sequentially arranged in one direction.

The gate insulating layer may entirely surround a side surface of the oxide semiconductor layer.

Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, example embodiments are merely described below, by referring to the figures, to explain aspects.

Example embodiments are described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals refer to like components, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. The embodiments described herein are merely examples, and various modifications may be made from these embodiments.

When it is described that a certain component is "above" or "on" another component, the certain component may be directly above another component, or a third component may be interposed therebetween. The singular expressions include plural expressions unless the context clearly dictates otherwise. When a part "includes" a component, it may indicate that the part does not exclude another component but may further include another component, unless otherwise stated. The use of the terms "a" and "an" and "the" and similar referents may cover both the singular and the plural.

<FIG> is a diagram illustrating a transistor <NUM> according to various example embodiments. Referring to <FIG>, the transistor <NUM> may be disposed on or in a substrate SUB. The transistor <NUM> may include an oxide semiconductor layer <NUM>, a source electrode <NUM> and a drain electrode <NUM> disposed on the oxide semiconductor layer <NUM> and spaced apart from each other, a gate electrode <NUM> disposed to be spaced apart from the oxide semiconductor layer <NUM>, and a gate insulating layer <NUM> disposed between the oxide semiconductor layer <NUM> and the gate electrode <NUM>.

The substrate SUB may be provided in a flat plate shape extending along one surface thereof. The substrate SUB may include a material for forming a device, and a material having good or excellent mechanical strength and/or dimensional stability may be selected. The material of the substrate SUB may include, but is not limited to, a glass plate, a metal plate, a ceramic plate, or plastic (a polycarbonate resin, a polyester resin, an epoxy resin, a silicone resin, a fluorine resin, etc.).

A first interlayer insulating layer (e.g., a first interlayer dielectric (ILD1)) may be disposed on the substrate SUB. The oxide semiconductor layer <NUM> may be disposed on the first interlayer insulating layer ILD1. As an example, the oxide semiconductor layer <NUM> may be provided in the form of an ultra-thin film. For example, a thickness of the oxide semiconductor layer <NUM> may be <NUM> or less. The oxide semiconductor layer <NUM> according to an example may include metal elements of group <NUM>, <NUM> and <NUM> such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf), and oxides of materials selected from one or combinations thereof. For example, the oxide semiconductor layer <NUM> may be formed of a Zn oxide-based material, such as one or more of Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like. As an example, the oxide semiconductor layer <NUM> may be provided as a single-layer or as a multi-layer structure.

The source electrode <NUM> and the drain electrode <NUM> may be disposed on the oxide semiconductor layer <NUM> and spaced apart from each other. The source electrode <NUM> and the drain electrode <NUM> may be disposed on the same surface of the oxide semiconductor layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> may include an electrically conductive material. For example, the source electrode <NUM> and the drain electrode <NUM> may include a metal and/or a metal compound, and may include the same, or different materials.

The gate electrode <NUM> may be disposed between the source electrode <NUM> and the drain electrode <NUM> on the oxide semiconductor layer <NUM>. The gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> may be disposed on the same surface of the oxide semiconductor layer <NUM>. According to some example embodiments, the gate electrode <NUM> may include an electrically conductive material. For example, the gate electrode <NUM> may include a metal and/or a metal compound.

The gate insulating layer <NUM> may be disposed between the oxide semiconductor layer <NUM> and the gate electrode <NUM> to electrically disconnect the oxide semiconductor layer <NUM> and the gate electrode <NUM>. For example, the gate insulating layer <NUM> may include a ferroelectric material. As an example, the ferroelectric material may include at least one of an oxide ferroelectric material, a polymer ferroelectric material, a fluoride ferroelectric material such as BaMgF4 (BMF), and/or a ferroelectric material semiconductor.

The transistor <NUM> including the oxide semiconductor layer <NUM> has a wide bandgap of <NUM> eV or greater. In addition, the transistor <NUM> including the oxide semiconductor layer <NUM> may reduce an OFF-current, have a low subthreshold swing (SS), and/or have a high ON/OFF ratio.

When such a transistor <NUM> is applied as a driving element of an electronic device, for example, a display device, a short-channel effect due to scaling down may exist or be pronounced, varying performance. Typically, a length of the transistor <NUM> may be reduced, so it may be difficult to control a threshold voltage. In general, in the process of forming other components of the transistor <NUM> after the oxide semiconductor layer <NUM> is formed, a conductivity of the oxide semiconductor layer <NUM> may increase due to the influence of a process such as plasma damage and/or an increase in the hydrogen (H) concentration. As a result, a threshold voltage of the transistor <NUM> may be reduced. Alternatively or additionally, when he transistor <NUM> is driven in a high temperature, high voltage state, the threshold voltage may be shifted to a negative value due to migration of hydrogen.

The transistor <NUM> according to various example embodiments includes a graphene layer <NUM> doped with, and/or having incorporated therein, a metal between the gate insulating layer <NUM> and the gate electrode <NUM>. The metal may be interstitially within the graphene, and/or may be substitutional within the graphene; example embodiments are not limited thereto.

The metal doped in the graphene layer <NUM> may be different from a metal included in the oxide semiconductor layer <NUM>. For example, the metal doped in the graphene layer <NUM> may include at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), thallium (TI), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W). The metal may be doped in an amount of about <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or less, or <NUM> at% or less with respect to a total amount of the metal-doped graphene layer <NUM> A thickness of the graphene layer <NUM> may be less than a thickness of the gate electrode <NUM>. The thickness of the graphene layer <NUM> may be about <NUM> or less.

The metal-doped graphene layer <NUM> may increase a work function to increase the threshold voltage of the transistor <NUM>. An ideal threshold voltage VT of the transistor <NUM> may be expressed as in Equation <NUM> below.

Here, Φms = Φm - Φs represents a difference between a work function Φm of the gate electrode <NUM> and a work function Φs of the oxide semiconductor layer <NUM>, Ci represents capacitance of the gate insulating layer <NUM>, Qi represents the amount of charges in the gate insulating layer <NUM>, Qd represents the amount of deflation charges in the gate insulating layer <NUM>, and Φf represents a Fermi level of the oxide semiconductor layer <NUM>.

According to Equation <NUM>, in general, the threshold voltage VT of the transistor <NUM> may increase when Ci is large, for example, when one or more of the gate insulating layer <NUM> is high-k, the thickness of the gate insulating layer <NUM> is small, or the work function of the gate electrode <NUM> is large.

In general, W or TiN may be used for the gate electrode <NUM>. A work function of W or TiN may be about <NUM> to <NUM> eV. Meanwhile, an undoped graphene layer may have a work function of about <NUM> eV, which is greater than that of a metal. If the graphene layer is doped with or has incorporated therein a metal, the grapheme layer may have a higher work function. For example, a graphene layer doped with Ru has a work function of <NUM> to <NUM> eV, and thus may have a higher work function of about <NUM> eV than a gate electrode including a metal material. Therefore, when the metal-doped graphene layer <NUM> having a high work function is disposed between the gate insulating layer <NUM> and the gate electrode <NUM>, the metal-doped graphene layer <NUM> may serve as the gate electrode <NUM>, thereby increasing the threshold voltage of the transistor <NUM>.

Alternatively or additionally, the graphene layer <NUM> may prevent or reduce the amount of or impact from material diffusion between the layers. Hydrogen is a dopant of an oxide semiconductor, and when the content of hydrogen in the oxide semiconductor layer <NUM> increases, the threshold voltage of the oxide semiconductor layer <NUM> decreases. During a thin film deposition and/or a heat treatment process of the transistor <NUM>, hydrogen may be introduced into the oxide semiconductor layer <NUM>, and during high-temperature driving of the transistor <NUM>, hydrogen may be introduced into the oxide semiconductor layer <NUM> due to bias stress. The introduced hydrogen lowers the threshold voltage of the oxide semiconductor layer <NUM>. For example, in order to increase thermal stability and reliability of device driving, it is necessary or desirable to prevent or reduce hydrogen from diffusing into the oxide semiconductor layer <NUM>. Because carbon atoms of graphene have a small bonding length and are bound by strong covalent bonds, the carbon atoms may act as a diffusion barrier that effectively prevents or reduces material diffusion. Accordingly, by forming the graphene layer <NUM> on the gate insulating layer <NUM>, hydrogen diffusing from the gate electrode <NUM> may be or at least partially be properly blocked, thereby improving the reliability of the threshold voltage control.

For example, the metal-doped transistor <NUM> according to various example embodiments has a large work function, so that the metal-doped transistor <NUM> may serve as a barrier to prevent or reduce material diffusion, while serving as the gate electrode <NUM>, thereby improving the reliability of driving of the transistor.

The metal-doped graphene layer <NUM> may be in contact with two or more surfaces of the gate electrode <NUM>. For example, the metal-doped graphene layer <NUM> may be in contact with a lower surface and side surfaces of the gate electrode <NUM>. The metal-doped graphene layer <NUM> may effectively prevent or reduce the material of the gate electrode <NUM> from diffusing to the outside.

The gate insulating layer <NUM> may also cover two or more surfaces of the gate electrode <NUM>. For example, the gate insulating layer <NUM> may be disposed on the lower surface and side surfaces of the gate electrode <NUM>. The gate insulating layer <NUM> may insulate the gate electrode <NUM> from the oxide semiconductor layer <NUM> as well as insulate the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM>. Thus, a length or a channel length of the oxide semiconductor layer <NUM> may be reduced.

The source electrode <NUM> and the drain electrode <NUM> may include a stepped shape. For example, the source electrode <NUM> may include a first source electrode <NUM> having a first thickness and a second source electrode <NUM> having a second thickness less than the first thickness, and the second source electrode <NUM> may be disposed closer to the gate electrode <NUM> than the first source electrode <NUM>. The source electrode <NUM> having a stepped shape may reduce formation of parasitic capacitance between the gate electrode <NUM> and the source electrode <NUM>, while securing or helping to secure a contact area with the oxide semiconductor layer <NUM>.

The drain electrode <NUM> may have a symmetrical structure with the source electrode <NUM> with respect to the gate electrode <NUM>. For example, the drain electrode <NUM> may include a first drain electrode <NUM> having a first thickness and a second drain electrode <NUM> having a second thickness less than the first thickness, and the second drain electrode <NUM> may be disposed closer to the gate electrode <NUM> than the first drain electrode <NUM>. The drain electrode <NUM> having a stepped shape may reduce formation of a parasitic capacitance between the gate electrode <NUM> and the source electrode <NUM>, while securing a contact area with the oxide semiconductor layer <NUM>.

Alternatively or additionally, at least one of the source electrode <NUM> and the drain electrode <NUM> may be in contact with even the gate insulating layer <NUM>. Thus, the transistor <NUM> may be integrated, while reducing the length of the oxide semiconductor layer <NUM>.

A second interlayer insulating layer ILD2 may fill a gap between the gate insulating layer <NUM> and the source electrode <NUM> and between the gate insulating layer <NUM> and the drain electrode <NUM>. The second interlayer insulating layer ILD2 may electrically disconnect the oxide semiconductor layer <NUM>, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> from each other. As an example, the second interlayer insulating layer ILD2 may be in contact with the first interlayer insulating layer ILD1, and bury the oxide semiconductor layer <NUM>, the gate insulating layer <NUM>, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM>.

<FIG> is results of measuring a work function of each material according to various example embodiments. Referring to <FIG>, a work function of a material including TiN and Wwas about <NUM> eV or more and <NUM> eV or less, and a work function of graphene was about <NUM> eV or more and <NUM> eV or less. A work function of the graphene layer doped with a metalloid (e.g., As) and a non-metal (e.g., P) was about <NUM> eV or more and <NUM> eV or less. A work function of a graphene layer doped with a metal, for example, Ru, was about <NUM> eV or more and <NUM> eV or less.

When a graphene layer is added to the gate electrode, it may be expected that the work function increases. In particular, when a metal-doped graphene layer is added to the gate electrode, it may be expected that a work function exceeds <NUM> eV. A work function of the metal-doped graphene layer according to various example embodiments may be <NUM> eV or more and <NUM> eV or less. Alternatively, a work function of the metal-doped graphene layer according to various example embodiments is <NUM> eV or more and <NUM> eV or less.

<FIG> is results of measuring current-voltage (IV) characteristics of the transistor <NUM> according to various example embodiments. Example is IV characteristics of a transistor including a metal-doped graphene layer, and Comparative Example is IV characteristics of a transistor not including a metal-doped graphene layer. It can be seen that, when a current IDS flowing from the drain electrode <NUM> to the source electrode <NUM> is <NUM>-<NUM> A/µm or <NUM>-<NUM> A/micron, a threshold voltage of Example is a positive voltage, whereas a threshold voltage of Comparative Example is a negative voltage. Therefore, it can be seen that the threshold voltage may be maintained at a positive value even when the drain current is <NUM>-<NUM> A/µm by adding the metal-doped graphene layer <NUM> to the gate electrode <NUM>.

The metal-doped graphene layer may be applied to various types of transistors.

<FIG> is a diagram illustrating a transistor 10a having a top gate structure according to various example embodiments. Comparing <FIG> with <FIG>, a source electrode 120a and a drain electrode 130a of the transistor 10a of <FIG> disposed to be spaced apart from each other on an oxide semiconductor layer 110a. In addition, a gate insulating layer 150a, a metal-doped graphene layer 160a, and a gate electrode 140a may be sequentially stacked on the oxide semiconductor layer 110a. The metal-doped graphene layer 160a may be disposed only on a lower surface of the gate electrode 140a, and the source electrode 120a and the drain electrode 130a may be disposed to be spaced apart from the gate insulating layer 150a. A length (e.g., a channel length) of the oxide semiconductor layer 110a of the transistor 10a of <FIG> may be longer than that of the transistor <NUM> of <FIG>.

A metal doped in the graphene layer 160a may be different from a metal included in the oxide semiconductor layer 110a. For example, the metal doped into the graphene layer 160a may include at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), thallium (TI), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W), and the oxide semiconductor layer 110a may be an oxide including at least one of In, Zn, Sn, Ga, and Hf. The metal may be doped in an amount of <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or less, or <NUM> at% or less with respect to a total amount of the graphene layer 160a, and a thickness of the doped graphene layer 160a is less than a thickness of the gate electrode 140a. For example, the thickness of the graphene layer 160a may be about <NUM> or less.

<FIG> is a diagram illustrating a transistor 10b having a bottom gate structure according to various example embodiments. Comparing <FIG> with <FIG>, a source electrode 120b and a drain electrode 130b of the transistor 10b of <FIG> may be disposed to be spaced apart from each other on an upper surface of an oxide semiconductor layer 110b, and a gate electrode 140b may be disposed on a lower surface of the oxide semiconductor layer 110b. A gate insulating layer 150b may be disposed between the oxide semiconductor layer 110b and the gate electrode 140b. A metal-doped graphene layer 160b may be disposed between the gate insulating layer 150b and the gate electrode 140b. The metal-doped graphene layer 160b may also be disposed on a side surface of the gate electrode 140b, as well as between the gate insulating layer 150b and the gate electrode 140b. Characteristics of each component have been described above, and thus, a detailed description thereof is omitted.

<FIG> is a diagram illustrating a transistor 10c having a double gate structure according to various example embodiments. Comparing <FIG> with <FIG>, a gate insulating layer 150c may include a first gate insulating layer <NUM> disposed on an upper surface of an oxide semiconductor layer 110c and a second gate insulating layer <NUM> disposed on a lower surface of the oxide semiconductor layer <NUM>. A gate electrode 140c may include a first gate electrode <NUM> disposed on an upper surface of the first gate insulating layer <NUM> and a second gate electrode <NUM> disposed on a lower surface of the second gate insulating layer <NUM>. In addition, a graphene layer 160c may include a first graphene layer <NUM> disposed between the first gate insulating layer <NUM> and the first gate electrode <NUM> and a second graphene layer <NUM> disposed between the second gate insulating layer <NUM> and the second gate electrode <NUM>. The first and second graphene layers <NUM> and <NUM> may be doped with a metal.

The metal doped in the graphene layer 160c may be different from a metal included in the oxide semiconductor layer 110c. For example, the metal doped in the graphene layer 160c may include at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), thallium (Ti), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W), and the oxide semiconductor layer 110c may be an oxide including at least one of In, Zn, Sn, Ga, and Hf. The metal may be doped in an amount of <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or less, or <NUM> at% or less with respect to a total amount of the graphene layer 160c, and a thickness of the metal-doped graphene layer 160c is less than a thickness of the gate electrode 140c. For example, the thickness of the graphene layer 160c may be about <NUM> or less.

<FIG> is a diagram illustrating a transistor 10d having a vertical channel structure according to various example embodiments. Referring to <FIG>, an oxide semiconductor layer 110d may have a structure extending in a thickness direction of the substrate SUB. A source electrode 120d may be disposed on an upper surface of the oxide semiconductor layer 110d, and a drain electrode 130d may be disposed on a lower surface of the oxide semiconductor layer 110d. However, various example embodiments are not limited thereto. The drain electrode 130d may be disposed on the upper surface of the oxide semiconductor layer 110d and the source electrode 120d may be disposed on the lower surface of the oxide semiconductor layer 110d. A gate insulating layer 150d and a gate electrode 140d may be disposed on a side surface of the oxide semiconductor layer 110d. In addition, the metal-doped graphene layer 160d may be disposed between the gate insulating layer 150d and the gate electrode 140d. The metal-doped graphene layer 160d may cover two or more surfaces of the gate electrode <NUM>.

<FIG> is a diagram illustrating a transistor 10e having a gate-all-around structure according to various example embodiments. Referring to <FIG>, an oxide semiconductor layer 110e may have a structure extending in a thickness direction of the substrate SUB. A source electrode 120e may be disposed on an upper surface of the oxide semiconductor layer 110e and a drain electrode 130e may be disposed on a lower surface of the oxide semiconductor layer 110e. However, various example embodiments are not limited thereto. The drain electrode 130e may be disposed on an upper surface of the oxide semiconductor layer 110e and the drain electrode 130e may be disposed on a lower surface of the oxide semiconductor layer 110e.

A gate insulating layer 150e covering the entire side surface of the oxide semiconductor layer 110e and a gate electrode 140e covering the side surface of the gate insulating layer <NUM> may be further disposed. Also, the metal-doped graphene layer 160e may be disposed between the gate insulating layer 150e and the gate electrode 140e. The metal-doped graphene layer 160e may be disposed not only on the side surface of the gate electrode 140e but also on the upper and lower surfaces of the gate electrode 140e.

So far, the source electrode and the drain electrode in contact with one surface of the oxide semiconductor layer have been described. However, various example embodiments are not limited thereto. The source electrode and the drain electrode may be in contact with a plurality of surfaces of the oxide semiconductor layer to integrate the transistor.

<FIG> is a diagram illustrating a transistor 10f according to another embodiment. Referring to <FIG>, the transistor 10f according to an example may include a substrate SUB, an oxide semiconductor layer 110f disposed on the substrate SUB, a source electrode 120f in contact with three or more surfaces of the oxide semiconductor layer 110f, a drain region 130f in contact with three or more surfaces of the oxide semiconductor layer 110f, a gate electrode 140f apart from the oxide semiconductor layer, and a gate insulating layer 150f disposed between the oxide semiconductor layer 110f and the gate electrode 140f.

The source electrode 120f may be disposed to contact three or more surfaces of the oxide semiconductor layer 110f. As an example, the source electrode 120f may include a first contact portion <NUM> in contact with the oxide semiconductor layer 110f and a first conductive plug <NUM> in contact with the first contact portion <NUM> and extending in one direction.

The first contact portion <NUM> may be disposed between the oxide semiconductor layer 110f and the first conductive plug <NUM> and may be in contact with the oxide semiconductor layer 110f on three or more surfaces. As described above, as a thickness h of the oxide semiconductor layer 110f decreases to an ultra-thin film, a thickness of an effective channel formed by a gate field may substantially be equal to a thickness of the physical oxide semiconductor layer 110f. A difference in charge concentration between a lower surface and an upper surface of the oxide semiconductor layer 110f is also reduced, so that a contact area in which the entire area of the oxide semiconductor layer 110f is in contact with the source electrode 120f and the drain region 130f may be formed.

As an example, when the oxide semiconductor layer 110f is provided in the form of a thin film extending along one plane, the first contact portion <NUM> may include a first lower contact layer <NUM>-<NUM> surrounding a portion of the lower surface of the oxide semiconductor layer 110f, a first upper contact layer <NUM>-<NUM> surrounding a portion of the upper surface of the oxide semiconductor layer 110f, and a first side contact layer <NUM>-<NUM> surrounding one side surface of the oxide semiconductor layer 110f. The first lower contact layer <NUM>-<NUM> may be disposed to face the substrate SUB. The first upper contact layer <NUM>-<NUM> may be disposed to face the first lower contact layer <NUM>-<NUM> with the oxide semiconductor layer 110f interposed therebetween. As an example, the first upper contact layer <NUM>-<NUM> may be provided to contact one end of the first conductive plug <NUM>. The first side contact layer <NUM>-<NUM> may be disposed between the first lower contact layer <NUM>-<NUM> and the first upper contact layer <NUM>-<NUM> to connect the first lower contact layer <NUM>-<NUM> to the first upper contact layer <NUM>-<NUM>.

Like the source electrode 120f, the drain electrode 130f may also contact three or more surfaces of the oxide semiconductor layer 110f. As an example, the drain electrode 130f may include a second contact portion <NUM> in contact with the oxide semiconductor layer 110f and a second conductive plug <NUM> in contact with the second contact portion <NUM> and extending in one direction.

The second contact portion <NUM> may be disposed between the oxide semiconductor layer 110f and the second conductive plug <NUM> and may contact the oxide semiconductor layer 110f on three or more surfaces. As described above, as the thickness of the oxide semiconductor layer 110f decreases to an ultra-thin film, a thickness of an effective channel formed by a gate field may substantially be equal to the thickness of the physical oxide semiconductor layer 110f. A difference in charge concentration between a lower surface and an upper surface of the oxide semiconductor layer 110f is also reduced, so that a contact area in which the lower surface and the upper surface of the oxide semiconductor layer 110f are in contact with the drain electrode 130f and the drain region 130f may be formed.

As an example, when the oxide semiconductor layer 110f is provided in the form of a thin film extending along one plane, the second contact portion <NUM> may include a second lower contact layer <NUM>-<NUM> surrounding a portion of the lower surface of the oxide semiconductor layer 110f, a second upper contact layer <NUM>-<NUM> surrounding a portion of the upper surface of the oxide semiconductor layer 110f, and a second side contact layer <NUM>-<NUM> surrounding one side of the oxide semiconductor layer 110f. The second lower contact layer <NUM>-<NUM> may be disposed to face the substrate SUB. The second upper contact layer <NUM>-<NUM> may be disposed to face the second lower contact layer <NUM>-<NUM> with the oxide semiconductor layer 110f interposed therebetween. As an example, the second upper contact layer <NUM>-<NUM> may be provided to contact one end of the second conductive plug <NUM>. The second side contact layer <NUM>-<NUM> may be disposed between the second lower contact layer <NUM>-<NUM> and the second upper contact layer <NUM>-<NUM> to connect the second lower contact layer <NUM>-<NUM> to the second upper contact layer <NUM>-<NUM>.

The transistor 10f includes a metal-doped graphene layer 160f between the gate electrode 140f and the gate insulating layer 150f.

A metal doped in the graphene layer 160f may be different from a metal included in the oxide semiconductor layer 110f. For example, the metal doped in the graphene layer 160f may include at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), thallium (Ti), platinum (Pt), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W), and the oxide semiconductor layer 110f may be an oxide including at least one of In, Zn, Sn, Ga, and Hf. The metal may be doped in an amount of <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or more, <NUM> at% or less, or <NUM> at% or less with respect to a total amount of the graphene layer 160f, and a thickness of the doped graphene layer 160f is less than a thickness of the gate electrode 140f. For example, the thickness of the graphene layer 160f may be about <NUM> or less.

<FIG> shows a memory device <NUM> using the aforementioned transistor as a switching element and including a data storage element connected to the switching element. In an example, the transistor <NUM> of <FIG>, among the transistors described above, may be used as a switching element.

Referring to <FIG>, the memory device <NUM> includes a data storage element <NUM> on the interlayer insulating layer ILD. The data storage element <NUM> may cover the entire upper surface of the drain electrode <NUM> and may be in direct contact with the upper surface. The data storage element <NUM> may include a capacitor, a ferroelectric capacitor, and a magnetic tunnel junction (MTJ) cell. The memory device <NUM> may be a volatile memory device, such as DRAM, or a nonvolatile memory device, such as FRAM, MRAM, ReRAM, or the like, depending on the data storage element <NUM>.

<FIG> illustrates a memory device <NUM> in which a plurality of memory cells MC1 of <FIG> are vertically stacked.

Referring to <FIG>, a memory logic layer <NUM> controlling an operation of the memory device <NUM> is disposed on a substrate <NUM>, and a memory cell array <NUM> is provided on the memory logic layer <NUM>. The memory cell array <NUM> includes a plurality of vertically stacked memory cells MC1. In an example, the memory cell MC1 may be the memory device <NUM> of <FIG>.

In the above, the transistor including a metal-doped graphene layer has been illustrated and described, but various example embodiments are not limited to the specific exemplary embodiments described above, and may be variously modified by those skilled in the art to which the present invention pertains without departing from the scope of the present invention as claimed in the claims.

According to various example embodiments, a threshold voltage of a transistor may be increased by adding a graphene layer doped with a metal having a large work function.

The metal-doped graphene layer may serve as a barrier to improve the reliability of driving of the transistor.

However, the effect of various example embodiments are not limited to the above disclosure.

Claim 1:
A transistor comprising:
an oxide semiconductor (<NUM>) layer;
a source electrode (<NUM>) and a drain electrode (<NUM>) spaced apart from each other on the oxide semiconductor layer;
a gate electrode (<NUM>) spaced apart from the oxide semiconductor layer;
a gate insulating layer (<NUM>) between the oxide semiconductor layer and the gate electrode; and
characterised by a graphene layer (<NUM>) between the gate electrode and the gate insulating layer and doped with a metal.