Patent Description:
Along with the increasing demand on display devices, the quantity of circuitries and lines in a display panel increase too, so a pad bending technique is adopted for an upper bezel or a lower bezel of the display panel. For the pad bending technique, a part of a circuit board (which may be a flexible circuit board) of the display device is folded toward a back surface of the display panel, and a heat dissipation film is attached to a surface of the circuit board folded to the back surface of the display panel, so as to reduce heat generated during the operation of the circuits. In order to increase alignment accuracy for folding and attachment accuracy for the heat dissipation film, it is necessary to identify an alignment mark in the display panel to perform alignment. In the related art, in the case of not increasing a width of the bezel, there is no technical scheme for implementing the alignment mark accurately for a four-surface-folding display panel.

<CIT> relates to a display device with alignment marks.

<CIT> relates to a display device capable of reducing or minimizing a crack in the bending area, and a manufacturing method thereof.

<CIT> relates to a display device in which a dummy pattern overlaps a signal line being spaced farthest from a display area.

A main object of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.

The present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.

Along with the increasing demand on display devices, the quantity of circuitries and lines in a display panel increase too, so a pad bending technique is adopted for an upper bezel or a lower bezel of the display panel. For the pad bending technique, a part of a circuit board (which may be a flexible circuit board) of the display device is folded toward a back surface of the display panel, and a heat dissipation film is attached to a surface of the circuit board folded to the back surface of the display panel, so as to reduce heat generated during the operation of the circuits. In order to increase alignment accuracy for folding and attachment accuracy for the heat dissipation film, it is necessary to identify alignment marks in the display panel to implement an alignment. During the implementation, the alignment marks may include an alignment mark for folding the circuit board and/or an alignment mark for attaching the heat dissipation film. The alignment marks may be identified by an alignment camera, so as to determine positions. Definition of an image identified by the alignment camera through focusing is associated with consistency of object distances, so the alignment marks need to be placed at a flat region where the display panel is provided with a flat surface.

When the display panel is a four-surface-folding display panel, an upper surface and a lower surface of the display panel are each a flat surface, and an upper side surface of the display panel, a lower side surface of the display panel, a left side surface of the display panel and a right side surface of the display panel are each a curved side surface, so a size of the flat region is relatively small.

<FIG> are top views of a four-surface-folding display panel, after a circuit board has been folded and before the four side surfaces of the four-surface-folding display panel have been folded.

In <FIG>, the sign <NUM> represents an outer edge of the display panel, and the sign <NUM> represents an active area boundary which surrounds an Active Area (AA) of the display panel. A peripheral region of the display panel is a region of the display panel other than the active area.

In <FIG>, the sign <NUM> represents the outer edge of the display panel, the sign <NUM>-<NUM> represents a left curved region of the display panel, the sign <NUM>-<NUM> represents a lower curved region of the display panel, the sign <NUM>-<NUM> represents an upper curved region of the display panel, and the sign <NUM>-<NUM> represents a right curved region of the display panel.

In <FIG>, the sign L1 represents a first dashed line, and a region on the left of the display panel surrounded by the first dashed line L1 and the outer edge of the display panel is the left curved region <NUM>-<NUM> of the display panel. The sign L2 represents a second dashed line, and a region at a lower side of the display panel surrounded by the second dashed line L2 and the outer edge of the display panel is the lower curved region <NUM>-<NUM> of the display panel. The sign L3 represents a third dashed line, and a region at an upper side of the display panel surrounded by the third dashed line L3 and the outer edge of the display panel is the upper curved region <NUM>-<NUM> of the display panel. The sign L4 represents a fourth dashed line, and a region on the right of the display panel surrounded by the fourth dashed line L4 and the outer edge of the display panel is the right curved region <NUM>-<NUM> of the display panel. A flat region in the peripheral region of the display panel may be a region in the peripheral region of the display panel not covered by the right curved region <NUM>-<NUM>, the lower curved region <NUM>-<NUM>, the upper curved region <NUM>-<NUM> and the right curved region <NUM>-<NUM>.

In <FIG>, the sign <NUM> represents a first flat region included in the flat region of the display panel, the sign <NUM> represents a second flat region included in the flat region of the display panel, the sign <NUM> represents a third flat region included in the flat region of the display panel, and the sign <NUM> represents a fourth flat region included in the flat region of the display panel. In other words, in the four-side-folding display panel whose four side surfaces are folded, the flat region may be located at an upper left side, a lower left side, an upper right side and a lower right side in proximity to the active area.

In <FIG>, the first flat region <NUM> is a flat region located at a lower left side of the display panel, the second flat region <NUM> is a flat region located at a lower right side of the display panel, the third flat region <NUM> is a flat region located at an upper left side of the display panel, and the forth flat region <NUM> is a flat region located at an upper right side of the display panel.

The first flat region <NUM> is arranged proximate to a lower left rounded corner of the active area boundary <NUM>, the second flat region <NUM> is arranged proximate to a lower right rounded corner of the active area boundary <NUM>, the third flat region <NUM> is arranged proximate to an upper left rounded corner of the active area boundary <NUM>, and the fourth flat region <NUM> is arranged proximate to an upper right rounded corner of the active area boundary <NUM>.

In at least one embodiment of the present disclosure, an orthogonal projection of the left side surface of the display panel onto a first plane may overlap an orthogonal projection of the left curved region <NUM>-<NUM> onto the first plane, an orthogonal projection of the lower side surface of the display panel onto the first plane may overlap an orthogonal projection of the lower curved region <NUM>-<NUM> onto the first plane, an orthogonal projection of the upper side surface of the display panel onto the first plane may overlap an orthogonal projection of the upper curved region <NUM>-<NUM> onto the first plane, and an orthogonal projection of the right side surface of the display panel onto the first plane may overlap an orthogonal projection of the right curved region <NUM>-<NUM> onto the first plane. The first plane may be parallel to the lower surface of the display panel.

As shown in <FIG>, the lower left corner of the active area boundary <NUM> may be a portion between a first intersection point P1 and a second intersection point P2 on the active area boundary <NUM>. The first intersection point P1 may be a point where the first dashed line L1 intersects a lower left portion of the active area boundary <NUM>, and the second intersection point P2 may be a point where the second dashed line L2 intersects the lower left portion of the active area boundary <NUM>.

As shown in <FIG>, the lower right rounded corner of the active area boundary <NUM> may be a portion between a third intersection point P3 and a fourth intersection point P4 on the active area boundary <NUM>. The third intersection point P3 may be a point where the second dashed line L2 intersects a lower right portion of the active area boundary <NUM>, and the fourth intersection point P4 may be a point where the fourth dashed line L4 intersects the lower left portion of the active area boundary <NUM>.

As shown in <FIG>, the upper left rounded corner of the active area boundary <NUM> may be a portion between a fifth intersection point P5 and a sixth intersection point P6 on the active area boundary <NUM>. The fifth intersection point P5 may be a point where the first dashed line L1 intersects an upper left portion of the active area boundary <NUM>, and the sixth intersection point P6 may be a point where the third dashed line L3 intersects the upper left portion of the active area boundary <NUM>.

As shown in <FIG>, the upper right rounded corner of the active area boundary <NUM> may be a portion between a seventh intersection point P7 and an eighth intersection point P8 on the active area boundary <NUM>. The seventh intersection point P7 may be a point where the third dashed line L3 intersects an upper right portion of the active area boundary <NUM>, and the eighth intersection point P8 may be a point where the fourth dashed line L4 intersects the upper left portion of the active area boundary <NUM>.

<FIG> is a top view of the four-surface-folding display panel before a circuit board has been folded. In <FIG>, the sign <NUM> represents the circuit board. The circuit board <NUM> may be a flexible circuit board. During the manufacture of the four-surface-folding display panel, it is necessary to fold the circuit board <NUM> to a back surface of the display panel.

In the embodiments of the present disclosure, when the circuit board <NUM> is folded to the back surface of the display panel, a heat dissipation film may be attached to each of the back surface and the four side surfaces of the display panel for heat dissipation.

In at least one embodiment of the present disclosure, when the circuit board <NUM> is arranged at a lower side of the display panel and it is necessary to fold the circuit board <NUM> to the back surface of the display panel, alignment marks are arranged at the first flat region <NUM> and/or the second flat region <NUM>, so as to perform the alignment for the folding and the alignment for the attachment of the heat dissipation film. Moreover, when the circuit board <NUM> is arranged at the lower side of the display panel, because the heat dissipation film also needs to be attached to the upper side surface of the display panel, the alignment marks can also be arranged at the third flat region <NUM> and/or the fourth flat region <NUM>, so as to perform the alignment for the attachment of the heat dissipation film.

During the implementation, when the circuit board <NUM> is arranged at the lower side of the display panel, an alignment mark for folding may also be arranged on the circuit board. The alignment for folding may be performed in accordance with the alignment mark for folding on the circuit board in conjunction with the alignment marks at the first flat region <NUM> and/or the second flat region <NUM>.

In at least one embodiment of the present disclosure, when the circuit board <NUM> is arranged at an upper side of the display panel and it is necessary to fold the circuit board <NUM> to the back surface of the display panel, the alignment marks are arranged at the third flat region <NUM> and/or the fourth flat region <NUM>, so as to perform the alignment for folding and the alignment for the attachment of the heat dissipation film. Moreover, when the circuit board <NUM> is arranged at the upper side of the display panel, because the heat dissipation film also needs to be attached to the lower side surface of the display panel, the alignment marks are also arranged at the first flat region <NUM> and/or the second flat region <NUM>, so as to perform the alignment for the attachment of the heat dissipation film.

During the implementation, when the circuit board <NUM> is arranged at the upper side of the display panel, an alignment mark for folding may also be arranged on the circuit board. The alignment for folding may be performed in accordance with the alignment mark for folding on the circuit board in conjunction with the alignment marks at the third flat region <NUM> and/or the fourth flat region <NUM>.

A fan-out region is arranged at the peripheral region of the display panel and a driving circuitry region and a signal line region may be arranged sequentially at the peripheral region of the display panel in a direction away from the active area. The fan-out region is a region where a connection line between a source driver and a data line in the active area is located, and a direct current voltage signal line may be arranged in the fan-out region.

The direct current voltage signal line may include a high voltage signal line and/or a low voltage signal line. The high voltage signal line may be used to provide a high voltage signal VDD, and the low voltage signal line may be used to provide a low voltage signal VSS.

A connection line between a gate line and a gate driver can also be arranged in the fan-out region. A signal line may be arranged within the signal line region, and it may include a direct current voltage signal line. When the signal line includes the direct current voltage signal line, the signal line may include a high voltage signal line and/or a low voltage signal line. The low voltage signal line may be used to provide a low voltage signal VSS, and the high voltage signal line may be used to provide a high voltage signal VDD.

The driving circuitry region may include a driving circuitry region and a dummy driving circuitry region. A driving circuitry including a plurality of levels of shift register units may be arranged within the driving circuitry region. The driving circuitry may include a gate driving circuitry for providing a gate driving signal to a plurality of rows of pixel circuitries in the active area.

In a possible embodiment of the present disclosure, the driving circuitry may also include a light-emission control circuitry for providing a respective light-emission control signal to each of the plurality of rows of pixel circuitries in the active area.

A dummy driving circuitry may be arranged within the dummy driving circuitry region, and it may include at least one level of dummy shift register unit. The dummy shift register unit may not be coupled to the pixel circuitries in the active area, and it may be reserved merely to ensure etching uniformity and layout reasonability. A signal line in the dummy shift register unit may receive a signal at a fixed voltage, so as to reduce the influence on the driving circuitry at the driving circuitry region caused by signal jump.

According to the claimed invention, a fist metal layer is arranged on a base and an anode layer may be sequentially arranged on the base at the fan-out region. The connection line between the data line and the source driver is arranged on the first metal layer. In addition, the anode layer may also be provided with a plurality of openings at a region of the fan-out region other than an alignment mark region, and each opening may be provided for gas release of an organic film layer.

During the implementation, the first metal layer may include a gate metal layer and/or a source/drain metal layer. The gate metal layer may include, but not limited to, a first gate metal layer and a second gate metal layer.

Within the fan-out region, the connection line between the data line and the source driver may be arranged on the first gate metal layer and/or the second gate metal layer, or on the source/drain metal layer.

Within the fan-out region, the connection line between the gate line and the gate driver may be arranged on the first gate metal layer and/or the second gate metal layer, or on the source/drain metal layer.

Within the fan-out region, the direct current voltage signal line may be arranged on the first gate metal layer and/or the second gate metal layer, or on the source/drain metal layer.

In at least one embodiment of the present disclosure, a semiconductor layer, a second metal layer and the anode layer may be arranged sequentially on the base within the signal line region. When the anode layer is arranged on the second metal layer within the signal line region, it is able for a cathode of a light-emitting element at the active area to be lapped onto the low voltage signal line (an area of the anode layer covering the second metal layer is determined by a lapping condition of the low voltage signal line and the cathode).

In a possible embodiment of the present disclosure, the second metal layer may include, but not limited to, a source/drain metal layer and/or a gate metal layer.

During the implementation, the second metal layer may include a signal line, and the signal line may be a direct current voltage signal line. When the signal line includes the direct current voltage signal line, the signal line may include a high voltage signal line and/or a low voltage signal line. The low voltage signal line may be used to provide a low voltage signal VSS, and the high voltage signal line may be used to provide a high voltage signal VDD.

In addition, the anode layer may be provided with a plurality of openings at a region of the signal line region other than the alignment mark region for gas release of an organic film layer.

<FIG> is a schematic view showing the division of regions at the lower left rounded corner of the display panel in <FIG>. In <FIG>, the sign <NUM> represents the active area, the sign <NUM> represents fan-out region, the sign <NUM> represents the driving circuitry region, the sign <NUM> represents the signal line region, the sign <NUM> represents the outer edge of the display panel, and the sign <NUM> represents the active area boundary.

According to the claimed invention, the flat region includes a part of the fan-out region, and/or a part of the signal line region. When the flat region includes a part of the fan-out region, the part of the fan-out region may be flat, and when the flat region includes a part of the signal line region, the part of the signal line region may be flat.

During the implementation, a signal line having a certain width may be arranged at the flat signal line region, and a direct current voltage signal may be applied to the signal line. The direct current voltage signal may be a high voltage signal or a low voltage signal.

When the signal line has a certain width, it is able to reduce a resistance of the signal line, thereby to reduce a voltage drop of the direct current voltage signal across the signal line. In a possible embodiment of the present disclosure, the flat region may further include at least a part of the dummy driving circuitry region. When the flat region includes at least a part of the dummy driving circuitry region, the at least a part of the dummy driving circuitry region may be a flat dummy driving circuitry region.

The display panel according to the claimed invention includes an alignment mark region arranged within a flat region of a peripheral region of the display panel. The peripheral region is a region of the display panel other than an active area. An alignment mark pattern is arranged at the alignment mark region, and/or at least one film layer at the alignment mark region is hollowed out.

According to the claimed invention, the display panel includes the alignment mark region, and the alignment mark pattern is arranged at the alignment mark region or at least one film layer within the alignment mark region is hollowed out. Because at least one film layer within the alignment mark region is hollowed out, light transmittance at the alignment mark region may be greater than that at the peripheral region. As a result, it is able to perform the alignment accurately.

In at least one embodiment of the present disclosure, the film layer may be, but not limited to, a metal layer.

During the implementation, the display panel may be provided with a flat surface at the flat region.

In a possible embodiment of the present disclosure, the display panel may include an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface. The first side surface, the second side surface, the third side surface and the fourth side surface may be curved side surfaces, an orthogonal projection of the first side surface onto a first plane may not overlap an orthogonal projection of the flat region onto the first plane, an orthogonal projection of the second side surface onto the first plane may not overlap the orthogonal projection of the flat region onto the first plane, an orthogonal projection of the third side surface onto the first plane may not overlap the orthogonal projection of the flat region onto the first plane, an orthogonal projection of the fourth side surface onto the first plane may not overlap the orthogonal projection of the flat region onto the first plane, and the first plane may be parallel to the lower surface.

In at least one embodiment of the present disclosure, the display panel may be a four-side-folding display panel. <FIG> is a top view of the four-side-folding display panel. The first side surface may be, but not limited to, the left side surface in <FIG>, the second side surface may be, but not limited to, the lower side surface in <FIG>, the third side surface may be, but not limited to, the upper side surface in <FIG>, and the fourth side surface may be, but not limited to, the right side surface in <FIG>.

In a possible embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the lower side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and a lower left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, and/or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and a lower right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

During the implementation, the predetermined distance may be set according to the practical need. For example, the predetermined distance may be, but not limited to, greater than or equal to <NUM> and smaller than or equal to <NUM>.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the lower side of the display panel, the alignment mark region may be arranged proximate to the lower left rounded corner of the active area boundary, and/or proximate to the lower right rounded corner of the active area boundary.

As shown in <FIG>, when the alignment mark region <NUM> is arranged proximate to the lower left rounded corner of the active area boundary <NUM>, the maximum distance between the orthogonal projection of the alignment mark region <NUM> onto the first plane and the lower left rounded corner of the active area boundary <NUM> may be a maximum distance between any point on a boundary of the orthogonal projection of the alignment mark region <NUM> onto the first plane and any point on the lower left rounded corner of the active area boundary <NUM>. In <FIG>, the alignment mark region <NUM> may be of, but not limited to, an L-like shape.

In at least one embodiment of the present disclosure, when the alignment mark region is arranged proximate to the lower right rounded corner of the active area boundary, the maximum distance between the orthogonal projection of the alignment mark region onto the first plane and the lower right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may refer to a maximum distance between any point on the boundary of the alignment mark region onto the first plane and any point on the lower right rounded corner of the active area boundary.

In another possible embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the upper side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and an upper left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, and/or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and an upper right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, when the alignment mark region is arranged proximate to the upper left rounded corner of the active area boundary, the maximum distance between the orthogonal projection of the alignment mark region onto the first plane and the upper left rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may refer to a maximum distance between any point on a boundary of the orthogonal projection of the alignment mark region onto the first plane and any point on the upper left rounded corner of the active area boundary.

In at least one embodiment of the present disclosure, when the alignment mark region is arranged proximate to the upper right rounded corner of the active area boundary, the maximum distance between the orthogonal projection of the alignment mark region onto the first plane and the upper right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may refer to a maximum distance between any point on the boundary of the orthogonal projection of the alignment mark region onto the first plane and any point on the upper right rounded corner of the active area boundary.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the upper side of the display panel, the alignment mark region may be arranged proximate to the upper left rounded corner of the active area boundary, and/or proximate to the upper right rounded corner of the active area boundary.

In at least one embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the lower side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and an upper left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and an upper right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the lower side of the display panel, the alignment mark region may be arranged proximate to the upper left rounded corner of the active area boundary, and/or proximate to the upper right rounded corner of the active area boundary.

In at least one embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the upper side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and a lower left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and a lower right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the upper side of the display panel, the alignment mark region may be arranged proximate to the lower left rounded corner of the active area boundary, and/or proximate to the lower right rounded corner of the active area boundary. In a possible embodiment of the present disclosure, the flat region may include a flat fan-out region, and the alignment mark region may be included in the flat fan-out region. The display panel may include a first metal layer on the base at the flat fan-out region, the first metal layer at the alignment mark region may be hollowed out, and the first metal layer may include a first metal pattern surrounding the alignment mark region at the flat fan-out region.

In at least one embodiment of the present disclosure, the first metal layer may include a plurality of metal connection lines arranged parallel to each other at the flat fan-out region. The metal connection line may be used for connecting the data line and the source driver, or connecting the gate line and the gate driver.

The first metal layer may also include a direct current voltage signal line having a certain width at the flat fan-out region, and the direct current voltage signal line may be a high voltage signal line or a low voltage signal line. When the direct current voltage signal line has a certain width, it is able to reduce a resistance of the direct current voltage signal line, thereby to reduce a voltage drop of a direct current voltage signal across the direct current voltage signal line.

In a possible embodiment of the present disclosure, the first metal layer may include, but not limited to, a gate metal layer and/or a source/drain metal layer, and the gate metal layer may include, but not limited to, a first gate metal layer and a second gate metal layer.

According to the claimed invention, the alignment mark region is included in the flat fan-out region. The first metal layer is hollowed out at the alignment mark region, so as to form a fan-out opening. In addition, the first metal pattern in the first metal layer surrounds the alignment mark region, so that light transmittance of the flat fan-out region other than the alignment mark region is relatively low and light transmittance of the alignment mark region is relatively high, thereby to form a contrast between bright field and a dark field and facilitate the identification of the alignment mark. In addition, it is unnecessary to provide the alignment mark in a separate space, so it is able to reduce a width of a bezel of the display panel and perform the alignment accurately.

According to the claimed invention, the first metal pattern includes a connection line between the data line and the source driver, or a connection line between the gate line and the gate driver, and the first metal pattern may include a direct current voltage signal line, e.g., a high voltage signal line and/or a low voltage signal line.

During the implementation, the first metal layer may include a gate metal layer. The gate metal layer may include a first gate metal layer and a second gate metal layer that are arranged sequentially on the base and hollowed out at the alignment mark region. A first insulation layer may be arranged between the first gate metal layer and the second gate metal layer. The first insulation layer is transparent, so the first gate insulation layer may not be hollowed out at the alignment mark region.

Within an identification range of an alignment camera, due to dense lines at the fan-out region, when the alignment mark region is included in the flat fan-out region, the bright field and the dark field may be formed at the alignment mark region and the peripheral region respectively, resulting in an obvious contrast between the bright field and the dark field, so as to facilitate the identification.

In a possible embodiment of the present disclosure, the display panel may further include a semiconductor layer arranged between the base and the first metal layer at the flat fan-out region, the semiconductor layer may be hollowed out at a region of the flat fan-out region other than the alignment mark region, and the semiconductor layer may include an alignment mark pattern at the alignment mark region.

In the related art, no semiconductor layer may be arranged at the flat fan-out region. However, In at least one embodiment of the present disclosure, the semiconductor layer may be arranged between the base and the first metal layer at the flat fan-out region, and hollowed out at a region of the flat fan-out region other than the alignment mark region, i.e., not hollowed out at the alignment mark region, such that the semiconductor layer may include the alignment mark region. In this regard, it is able for the alignment camera to capture the alignment mark pattern in the semiconductor layer, thereby to perform the alignment accurately.

During the implementation, the display panel may further include an anode layer arranged at a surface of the first metal layer distal to the base at the alignment mark region, the anode layer may be not provided with any opening at the alignment mark region, and the anode layer may be provided with a plurality of openings arranged at intervals at a region other than the alignment mark region.

In at least one embodiment of the present disclosure, at the region of the display panel other than the alignment mark region, the anode layer may be provided with the plurality of openings (the adjacent openings may be spaced apart from each other at a certain distance) for the gas release of the organic film layer. When the anode layer is not provided with any opening at the alignment mark region, it is able for the alignment camera to conveniently identify the alignment mark region.

In a possible embodiment of the present disclosure, an edge of the orthogonal projection of the alignment mark region onto the base may be of, but not limited to, a polygonal, L-like or T-like shape.

<FIG>, <FIG> are top views of the semiconductor layer, the first gate metal layer, the second gate metal layer and the anode layer sequentially arranged on the base at at least a part of the flat fan-out region. In <FIG>, <FIG>, a hexagonal region <NUM> is the alignment mark region.

In the embodiments corresponding to <FIG>, <FIG>, the first metal layer may include a gate metal layer, and the gate metal layer may include a first gate metal layer and a second gate metal layer.

As shown in <FIG>, the semiconductor layer may be hollowed out at a region of the flat fan-out region other than the alignment mark region <NUM>, so that the semiconductor layer includes the alignment mark pattern <NUM> at the alignment mark region.

As shown in <FIG>, a first gate metal pattern <NUM> of the first gate metal layer may surround the alignment mark region <NUM>, and the first gate metal layer may be hollowed out at the alignment mark region <NUM>.

As shown in <FIG>, a second gate metal pattern <NUM> of the second gate metal layer may surround the alignment mark region <NUM>, and the second gate metal layer may be hollowed out at the alignment mark region <NUM>.

As shown in <FIG>, the anode layer may not be provided with any opening at the alignment mark region <NUM>, so that the alignment camera may identify the alignment mark region <NUM>. The anode layer may be provided with a plurality of openings 4dl at a region of the flat fan-out region other than the alignment mark region <NUM> (the adjacent openings 4dl may be spaced apart from each other at a certain distance). The anode layer may be hollowed out to form the opening 4dl for the gas release of the organic film layer.

In at least one embodiment of the present disclosure, a shape of the edge of the orthogonal projection of the alignment mark region <NUM> onto the base may be set according to the practical need. For example, the edge may be of a polygonal, L-like or T-like shape.

During the implementation, at the flat fan-out region, a second insulation layer may be arranged between the semiconductor layer and the first gate metal layer, a first insulation layer may be arranged between the first gate metal layer and the second gate metal layer, and a third insulation layer may be arranged between the second gate metal layer and the anode layer. The first insulation layer, the second insulation layer and the third insulation layer each has relatively high light transmittance, so they are not necessarily hollowed out at the alignment mark region.

During the implementation, the first insulation layer, the second insulation layer and the third insulation layer may be made of, but not limited to, silicon oxide or silicon nitride.

In another possible embodiment of the present disclosure, the flat region may include a flat signal line region, the alignment mark region may be included in the flat signal line region, the display panel may include a semiconductor layer arranged on the base at the alignment mark region, and the semiconductor layer may include an alignment mark pattern.

In at least one embodiment of the present disclosure, the flat region may include the flat signal line region, and the alignment mark pattern may be arranged at the alignment mark region included in the flat signal line region. The display panel may include the semiconductor layer arranged on the base at the alignment mark region included in the flat signal line region, and the semiconductor layer may include the alignment mark pattern.

In a possible embodiment of the present disclosure, an orthogonal projection of the alignment mark pattern onto the base may be of an L-like, T-like or polygonal shape.

During the implementation, when the alignment mark region is included in the flat signal line region, the display panel includes the semiconductor layer on the base at the alignment mark region and the semiconductor layer includes the alignment mark pattern, the display panel may further include a source/drain metal layer arranged at a surface of the semiconductor layer distal to the base, and the source/drain metal layer may include a low voltage signal line.

In addition, at the flat signal line region, the display panel may further include an anode layer arranged at a surface of the source/drain metal layer distal to the semiconductor layer. When the anode layer is arranged on the source/drain metal layer, it is able for a cathode of a light-emitting element at the active area to be lapped onto the low voltage signal line (an area of the anode layer covering the source/drain metal layer is determined by a lapping condition of the low voltage signal line and the cathode). The semiconductor layer under the source/drain metal layer may be provided with the alignment mark pattern, so as to enable the alignment camera to accurately acquire the alignment mark pattern from the back surface of the display panel. Through this scheme, it is able to prevent the layout of the other circuitries for the back plate from being adversely affected without increasing a width of a bezel, and enable the alignment camera to accurately acquire the alignment mark pattern for the alignment.

<FIG> and <FIG> are top views of the semiconductor layer, the source/drain metal layer and the anode layer sequentially arranged on the base at at least a part of the flat signal line region.

As shown in <FIG>, the semiconductor layer includes the alignment mark pattern <NUM> at the alignment mark region included in the flat signal line region.

As shown in <FIG>, the sign <NUM> represents a low voltage signal line in the source/drain metal layer at at least a part of the flat signal line region.

As shown in <FIG>, the sign <NUM> represents the anode layer arranged on the source/drain metal layer at at least a part of the flat signal line region.

<FIG> is a schematic view showing layers acquired after the layers in <FIG> are superimposed one on another, and <FIG> is a schematic view showing layers after the layers in <FIG> and <FIG> are superimposed one on another.

During the implementation, the flat region may include a flat signal line region, and the alignment mark region may be included in the flat signal line region. The display panel may include a second metal layer arranged on the base at the flat signal line region, and the second metal layer may be hollowed out at the alignment mark region.

In at least one embodiment of the present disclosure, the alignment mark region may be included in the flat signal line region, and the display panel may include the second metal layer at the flat signal line region. The second metal layer may be hollowed out at the alignment mark region, so as to form a light-transmissible alignment mark. Light transmittance of the alignment mark region is greater than that of the peripheral region, so as to perform the alignment accurately.

In a possible embodiment of the present disclosure, the second gate metal layer may include, but not limited to, a source/drain metal layer and/or a gate metal layer.

During the implementation, the second gate metal layer may include a signal line, and the signal line may include a direct current voltage signal line. When the signal line includes the direct current voltage signal line, the signal line may include, but not limited to, a low voltage signal line and/or a high voltage signal line.

In at least one embodiment of the present disclosure, when the second metal layer includes the source/drain metal layer and the source/drain metal layer includes the low voltage signal line, the display panel may further include an anode layer arranged at a surface of the source/drain metal layer distal to the base at the flat signal line region. When the anode layer covers the source/drain metal layer, it is able for a cathode of a light-emitting element at the active area to be lapped onto the low voltage signal line (an area of the anode layer covering the source/drain metal layer is determined by a lapping condition of the low voltage signal line and the cathode).

In a possible embodiment of the present disclosure, an edge of an orthogonal projection of the alignment mark region onto the base may be of an L-like, T-like or polygonal shape.

<FIG> shows at least a part of a source/drain metal pattern of the source/drain metal layer at the flat signal line region. As shown in <FIG>, the flat signal line region includes the alignment mark region <NUM>, and the source/drain metal layer is hollowed out at the alignment mark region <NUM>, so as to form a light-transmissible alignment mark. Light transmittance of the alignment mark region <NUM> may be greater than that of the peripheral region, so as to perform the alignment accurately.

In the embodiment of <FIG>, an edge of the orthogonal projection of the alignment mark region <NUM> onto the base may be, but not limited to, an L-like shape.

In another possible embodiment of the present disclosure, the flat region may include a flat dummy driving circuitry region, and the alignment mark region may be included in the flat dummy driving circuitry region. The display panel may include a semiconductor layer, a third metal layer and a fourth metal layer arranged sequentially on the base at the alignment mark region. The third metal layer and the fourth metal layer may be hollowed out at the alignment mark region. Preferably, the semiconductor layer may also be hollowed out at the alignment mark region.

In a possible embodiment of the present disclosure, the third metal layer may include, but not limited to, a gate metal layer, and the fourth metal layer may include, but not limited to, a source/drain metal layer.

During the implementation, the alignment mark region may be included in the flat dummy driving circuitry region. Except the alignment mark region, dense lines are provided at the peripheral region adjacent to the alignment mark region, and these lines are nontransparent to visible light. In a certain backlight source condition, these lines may be black in a field of view of the alignment camera. However, no line is arranged at the alignment mark region, and almost all the backlight light may pass through the alignment mark region and enter the alignment camera, i.e., there is a sharp contrast between the alignment mark region and the peripheral region. In this regard, it is able for the alignment camera to identify the alignment mark region.

During the implementation, the display panel may further include an anode layer arranged at a surface of the fourth metal layer distal to the second metal layer at the alignment mark region. The anode layer may not be provided with any opening at the alignment mark region, so as to enable the alignment camera to identify the alignment mark region. The anode layer may be provided with a plurality of openings at intervals at a region other than the alignment mark region.

In a possible embodiment of the present disclosure, an edge of an orthogonal projection of the alignment mark region onto the base may be of a polygonal, L-like or T-like shape.

In at least one embodiment of the present disclosure, the third metal layer may include a gate metal layer, and the gate metal layer may include a first gate metal layer and a second gate metal layer sequentially arranged on a surface of the semiconductor layer distal to the base.

<FIG> shows a part of the driving circuitry region, a part of the fan-out region <NUM> and a part of the signal line region <NUM>.

As shown in <FIG>, the flat region may include a flat dummy driving circuitry region <NUM>, the alignment mark region <NUM> may be included in the flat dummy driving circuitry region <NUM>, and the flat dummy driving circuitry region <NUM> may be included in the driving circuitry region. Apart from the flat dummy driving circuitry region <NUM>, the driving circuitry region may further include a first driving circuitry region <NUM> and a second driving circuitry region <NUM>, and the flat dummy driving circuitry region <NUM> may include the alignment mark region <NUM>.

At the alignment mark region <NUM>, the display panel may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a source/drain metal layer and an anode layer arranged sequentially on the base.

At least one level of dummy shift register unit may be arranged at a region of the flat dummy driving circuitry region <NUM> other than the alignment mark region <NUM>, and a driving circuitry including a plurality of levels of shift register units may be arranged at the first driving circuitry region <NUM> and the second driving circuitry region <NUM>.

At the alignment mark region <NUM>, the semiconductor layer, the gate metal layer and the source/drain metal layer may be hollowed out, so that light transmittance of the alignment mark region <NUM> is far greater than light transmittance of a region of the driving circuitry region adjacent to the alignment mark region <NUM>, so as to enable the alignment camera to accurately identify the alignment mark region. In addition, it is unnecessary to provide the alignment mark in a separate space, so it is able to reduce a width of a bezel of the display panel and perform the alignment accurately.

At the alignment mark region <NUM>, the anode layer may not be provided with any opening, so as to enable the alignment camera to identify the alignment mark region <NUM>.

At the driving circuitry region other than the alignment mark region <NUM>, the anode layer may be provided with a plurality of openings for the gas release of the organic film layer.

In the embodiments as shown in <FIG>, and <FIG>, the third gate metal layer may include a gate metal layer, the gate metal layer may include a first gate metal layer and a second gate metal layer, and the fourth metal layer may include a source/drain metal layer.

As shown in <FIG>, the edge of the orthogonal projection of the alignment mark region <NUM> onto the base may be of, but not limited to, an L-like shape. During the implementation, the edge of the orthogonal projection of the alignment mark region <NUM> onto the base may also be of any other shape.

<FIG> is a top view of an active pattern <NUM> of the semiconductor layer arranged on the base at the flat dummy driving circuitry region according to an embodiment, <FIG> is a top view of a first gate metal pattern <NUM> of the first gate metal layer arranged above the semiconductor layer at the flat dummy driving circuitry region according to an embodiment, <FIG> is a schematic view showing a pattern acquired after the patterns in <FIG> are superimposed one on another at the flat dummy driving circuitry region, <FIG> is a schematic view showing a pattern acquired after a second gate metal pattern <NUM> of the second gate metal layer is added at the flat dummy driving circuitry region on the basis of <FIG> is a schematic view showing a plurality of via-holes HO after the formation of the semiconductor layer, the first gate metal layer and the second gate metal layer sequentially at the flat dummy driving circuitry region, and <FIG> is a schematic view showing the source/drain metal layer SO at the flat dummy driving circuitry region after the formation of the plurality of via-holes HO. As shown in <FIG>, at the alignment mark region <NUM>, the first gate metal layer, the second gate metal layer, the semiconductor layer and the source/drain metal layer may be hollowed out. <FIG> is a schematic view showing an anode layer <NUM> on the source/drain metal layer at the flat dummy driving circuitry region. The anode layer <NUM> may not be provided with any opening at the alignment mark region <NUM>, so as to enable the alignment camera to identify the alignment mark region <NUM>. The anode layer <NUM> may be provided with a plurality of openings 9g1 at a region other than the alignment mark region <NUM>.

In <FIG>, a region surrounded by a dashed line represents the alignment mark region <NUM>. The edge of the orthogonal projection of the alignment mark region <NUM> onto the base may be of, but not limited to, an L-like shape.

During the implementation, at the flat dummy driving circuitry region, a second insulation layer may be arranged between the semiconductor layer and the first gate metal layer, a first insulation layer may be arranged between the first gate metal layer and the second gate metal layer, a fourth insulation layer may be arranged between the second gate metal layer and the source/drain metal layer, and a fifth insulation layer may be arranged between the source/drain metal layer and the anode layer. Because light transmittance of the first insulation layer, light transmittance of the second insulation layer, light transmittance of the fourth insulation layer and light transmittance of the fifth insulation layer are relatively high, the first insulation layer, the second insulation layer, the fourth insulation layer and the fifth insulation layer may not be hollowed out at the alignment mark region.

In at least one embodiment of the present disclosure, the first insulation layer, the second insulation layer, the fourth insulation layer and the fifth insulation layer may each be made of, but not limited to, silicon oxide or silicon nitride.

The present disclosure further provides in some embodiments a method for manufacturing a display panel, which includes providing an alignment mark region within a flat region of a peripheral region of the display panel. An alignment mark pattern may be arranged at the alignment mark region, and/or at least one film layer within the alignment mark region may be hollowed out. The peripheral region may be a region of the display panel other than an active area.

According to the method in at least one embodiment of the present disclosure, the alignment mark region may be formed at the flat region of the peripheral region of the display panel. The alignment mark pattern may be arranged at the alignment mark region, or at least one film layer within the alignment mark region may be hollowed out. Because at least one film layer within the alignment mark region is hollowed out, light transmittance of the alignment mark region may be greater than that of the peripheral region. As a result, it is able to perform the alignment accurately.

In at least one embodiment of the present disclosure, the peripheral region may be a region adjacent to the alignment mark region.

In a possible embodiment of the present disclosure, the film layer may include a metal layer, i.e., at least one metal layer may be hollowed out at the alignment mark region.

In a possible embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the lower side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and a lower left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and a lower right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the upper side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and an upper left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and an upper right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the lower side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and an upper left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, and/or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and an upper right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the lower side of the display panel, the alignment mark region may be arranged adjacent to the upper left rounded corner of the active area boundary, and/or adjacent to the upper right rounded corner of the active area boundary.

In at least one embodiment of the present disclosure, the first side surface may be the left side surface, the second side surface may be the lower side surface, the third side surface may be the upper side surface, and the fourth side surface may be the right side surface. The display panel may further include a circuit board arranged at the lower surface and at the upper side of the display panel. A maximum distance between an orthogonal projection of the alignment mark region onto the first plane and a lower left rounded corner of an orthogonal projection of an active area boundary of the display panel onto the first plane may be smaller than a predetermined distance, and/or a maximum distance between the orthogonal projection of the alignment mark region onto the first plane and a lower right rounded corner of the orthogonal projection of the active area boundary of the display panel onto the first plane may be smaller than the predetermined distance.

In at least one embodiment of the present disclosure, when the circuit board is arranged at the upper side of the display panel, the alignment mark region may be arranged adjacent to the lower left rounded corner of the active area boundary, and/or adjacent to the lower right rounded corner of the active area boundary.

In a possible embodiment of the present disclosure, the flat region may include a flat fan-out region, and the alignment mark region may be included in the flat fan-out region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include forming a first metal layer on a surface of a base at the flat fan-out region, patterning the first metal layer to form a first metal pattern, and enabling the first metal layer at the alignment mark region to be hollowed out. The first metal pattern may surround the alignment mark region.

During the implementation, the alignment mark region may be included in the flat fan-out region. The first metal layer may be hollowed out at the alignment mark region to form a fan-out opening, so that light transmittance of the flat fan-out region other than the alignment mark region is relatively low and light transmittance of the alignment mark region is relatively high, thereby to form a contrast between a bright field and a dark field and facilitate the identification of the alignment mark. In addition, it is unnecessary to provide the alignment mark in a separate space, so it is able to reduce a width of a bezel of the display panel and perform the alignment accurately.

In a possible embodiment of the present disclosure, the first metal layer may include, but not limited to, a gate metal layer and/or a source/drain metal layer, and the gate metal layer may include, but not limited, a first gate metal layer and a second gate metal layer.

In another possible embodiment of the present disclosure, the flat region may include a flat fan-out region, and the alignment mark region may be included in the flat fan-out region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include: within the flat fan-out region, forming a semiconductor layer on a base, and patterning the semiconductor layer to enable the semiconductor layer to be hollowed out at a region of the flat fan-out region other than the alignment mark region; and forming a first metal layer at a surface of the semiconductor layer distal to the base, and patterning the first metal layer to form a first metal pattern and enable the first metal layer at the alignment mark region to be hollowed out. The first metal pattern may surround the alignment mark region.

In the related art, no semiconductor layer may be arranged at the flat fan-out region. In contrast, in at least one embodiment of the present disclosure, the semiconductor layer may be arranged between the base and the first metal layer at the flat fan-out region, and hollowed out at a region of the flat fan-out region other than the alignment mark region, i.e., not hollowed out at the alignment mark region, such that the semiconductor layer may include the alignment mark pattern. In this regard, it is able for the alignment camera to capture the alignment mark pattern in the semiconductor layer, thereby to perform the alignment accurately.

In yet another possible embodiment of the present disclosure, the flat region may include a flat signal line region, and the alignment mark region may be included in the flat signal line region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include: within the flat signal line region, forming a semiconductor layer arranged on the base, and patterning the semiconductor layer to form an alignment mark pattern arranged at the alignment mark region.

In at least one embodiment of the present disclosure, the flat region may include the flat signal line region, and the alignment mark pattern may be arranged at the alignment mark region included in the flat signal line region. At the alignment mark region included in the flat signal line region, the display panel may include the semiconductor layer arranged on the base, and the semiconductor layer may include the alignment mark pattern.

In still yet another possible embodiment of the present disclosure, the flat region may include a flat signal line region, and the alignment mark region may be included in the flat signal line region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include forming a second metal layer on a surface of the base at the flat signal line region, and enabling the second metal layer to be hollowed out at the alignment mark region.

In at least one embodiment of the present disclosure, the flat region may include the flat signal line region, and the alignment mark region may be included in the flat signal line region. At the alignment mark region, the second metal layer may be hollowed out to form a light-transmissible alignment mark. Light transmittance of the alignment mark region may be greater than that of the peripheral region, so it is able to perform the alignment accurately.

During the implementation, in at least one embodiment of the present disclosure, the method may further include patterning the second metal layer to form a signal line.

In a possible embodiment of the present disclosure, the signal line may include a direct current voltage signal line. When the signal line includes the direct current voltage signal line, the signal line may include a low voltage signal line and/or a high voltage signal line.

In still yet another possible embodiment of the present disclosure, the flat region may include a flat dummy driving circuitry region, and the alignment mark region may be included in the flat dummy driving circuitry region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include: forming a semiconductor layer on the base at the flat dummy driving circuitry region, and patterning the semiconductor layer to form an active pattern; forming a third metal layer at a surface of the semiconductor layer distal to the base, patterning the third metal layer to form a third metal pattern, and enabling the third metal layer to be hollowed out at the alignment mark region; and forming a fourth metal layer at a surface of the third metal layer distal to the semiconductor layer, patterning the fourth metal layer to form a fourth metal pattern, and enabling the fourth metal layer to be hollowed out at the alignment mark region.

In still yet another possible embodiment of the present disclosure, the flat region may include a flat dummy driving circuitry region, and the alignment mark region may be included in the flat dummy driving circuitry region. The providing the alignment mark region within the flat region of the peripheral region of the display panel may include: forming a semiconductor layer on the base at the flat dummy driving circuitry region, patterning the semiconductor layer to form an active pattern, and enabling the semiconductor layer to be hollowed out at the alignment mark region; forming a third metal layer at a surface of the semiconductor layer distal to the base, patterning the third metal layer to form a third metal pattern, and enabling the first metal layer to be hollowed out at the alignment mark region; and forming a fourth metal layer at a surface of the third metal layer distal to the semiconductor layer, patterning the fourth metal layer to form a fourth metal pattern, and enabling the fourth metal layer to be hollowed out at the alignment mark region.

The present disclosure further provides in some embodiments a display device including the above-mentioned display panel.

In the embodiments of the present disclosure, the display device may be any product or member having a display function, e.g., mobile phone, tablet computer, television, display, notebook computer, digital photo frame or navigator.

Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as "first" and "second" used in the present disclosure are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as "one" or "one of" are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as "comprising" or "including" intends to indicate that an element or object before the word contains an element or object or equivalents thereof listed after the word, without excluding any other element or object. Such words as "connect/connected to" or "couple/coupled to" may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as "on", "under", "left" and "right" are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.

It should be appreciated that, in the case that such an element as layer, film, region or substrate is arranged "on" or "under" another element, it may be directly arranged "on" or "under" the other element, or an intermediate element may be arranged therebetween.

In the above description, the features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

Claim 1:
A display panel, comprising an alignment mark region (<NUM>, <NUM>) arranged within a flat region (<NUM>, <NUM>, <NUM>, <NUM>) of a peripheral region of the display panel,
wherein the peripheral region is a region of the display panel other than an active area of the display panel; and
an alignment mark pattern (<NUM>, <NUM>) is arranged within the alignment mark region (<NUM>, <NUM>), and/or at least one film layer within the alignment mark region (<NUM>, <NUM>) is hollowed out such that light transmittance at the alignment mark region is greater than light transmittance at the peripheral region enabling to perform an alignment,
wherein the flat region (<NUM>, <NUM>, <NUM>, <NUM>) comprises a flat fan-out region, the fan-out region being a region where connection lines between a source driver and a data line in the active area or between a gate line and a gate driver are located;
wherein, within the flat fan-out region, the display panel comprises a first metal layer arranged on a base; and
characterized in that the alignment mark region (<NUM>, <NUM>) is comprised in the flat fan-out region;
within the alignment mark region (<NUM>, <NUM>), the first metal layer is hollowed out;
within the flat fan-out region, the first metal layer comprises a first metal pattern surrounding the alignment mark region (<NUM>, <NUM>);
the first metal pattern is a pattern formed by connection lines in the flat fan-out area.