Patent Description:
Capacitors are components of primary importance in integrated circuits. In order to meet different requirements of circuit applications, various types of capacitors have been proposed, each with characteristics of their own. On account of the limited capacitance per unit area, capacitors generally occupy a considerable area within the integrated circuit to which they belong. Selecting a type of capacitor over another is thus a fundamental aspect in the design of integrated circuits.

Known in the art are basically three types of capacitors, namely, metal-oxide-semiconductor (MOS) capacitors, metal-insulating-metal (MIM) capacitors, and metal-oxide-metal (MOM) capacitors. Of these, owing to their thin gate-oxide structure, MOS capacitors have the highest value of density of capacitance per unit area. However, they suffer from considerable disadvantages, such as an accentuated not-linearity, a high temperature coefficient, and a low breakdown voltage, which render them not suitable for all circuit applications. MIM and MOM capacitors overcome the disadvantages of MOS capacitors; however, the densities of capacitance of said MIM and MOM capacitors are considerably lower as compared to MOS capacitors. Consequently, the use of MIM and MOM capacitors entails a higher consumption of area.

As a consequence of what has been discussed above, in many applications it is preferable to use discrete capacitors external to the integrated circuit (e.g., SMD capacitors).

Patent document <CIT> relates to semiconductor structures, and particularly to an embedded dynamic random access memory (eDRAM) employing a deep trench capacitor and formed in a hybrid orientation substrate, and methods of manufacturing the same.

Patent document <CIT> discloses methods of forming passive elements under a device layer.

Patent document <CIT> relates to electrical circuits, and more particularly, to embodiments of buried decoupling capacitors, circuits, devices and systems including such capacitors, and methods of fabrication.

Non-patent literature by<NPL>, relates to a three-dimensional Buried-Trench (BT) memory cell.

However, the above-listed issues are not overcome. There is thus felt the need for capacitors that enable the critical aspects of capacitors of a known type to be overcome and at the same time enable a saving of area.

The aim of the present invention is thus to provide a semiconductor die with buried capacitor, and a method of manufacturing the semiconductor die that are alternative to those of the prior art and that enable the drawbacks of the prior art to be overcome.

According to the present invention, a semiconductor die with buried capacitor and a method of manufacturing the semiconductor die are provided, as defined in the annexed claims.

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

<FIG> is a schematic lateral sectional view, in a triaxial system X, Y, Z, of a portion of a die, or chip, <NUM> that houses an integrated semiconductor device, in particular including a capacitor <NUM>. The view of <FIG> is a cross-sectional view taken along the line of section I-I of <FIG>. The capacitor <NUM> is of an integrated type, or embedded, in the die <NUM>.

The die <NUM> comprises a semiconductor substrate <NUM>, made, for example, of silicon, having a first conductivity (e.g., of a P type) and having a top surface 2a opposite, along Z, to a bottom surface 2b. By way of example, the semiconductor substrate <NUM> is doped with a concentration of P dopant species comprised between <NUM><NUM> and <NUM><NUM> at. In the context of the present invention, the die <NUM> is provided, on the top surface 2a of the substrate <NUM>, with one or more epitaxial layers <NUM>, which are also of semiconductor material. The semiconductor material may be for example silicon, and have the first conductivity, for an overall thickness, along Z, for example comprised between <NUM> and <NUM>.

The die <NUM> further comprises a buried conductive region <NUM> extending in the substrate <NUM> (and possibly, in part, in the epitaxial layer <NUM>), of doped polysilicon or of metal material or a metal alloy. Examples of materials that may be used include, but not are limited to, Ru, Pt, Ir, Pd, Ag, Au, W, Cu, Co, Fe, Ni, Mo, Ta, Ti, Al, doped Si, doped Ge, etc..

According to the embodiment illustrated in <FIG>, the buried conductive region <NUM> is electrically insulated from substrate <NUM>, and from the epitaxial layer <NUM>, by a layer of dielectric material <NUM>, made, for example, of silicon oxide. According to one aspect of the present invention, the layer of dielectric material <NUM> is made of a material with high dielectric constant k (known in the art as "high-k material"). Materials that may be used include, but not are limited to, Al<NUM>O<NUM>, TiO<NUM>, GeO<NUM>, Si<NUM>N<NUM>, La<NUM>O<NUM>, etc..

In an embodiment provided by way of example of the present invention, the buried cavity <NUM> has, in top plan view in the plane XY, a shape chosen from among circular, oval, quadrangular, or generically polygonal, with a diameter comprised approximately between <NUM> and <NUM> and a base area comprised between <NUM><NUM> and <NUM><NUM>. Alternatively, in a way not illustrated in the figure, it is likewise possible to form a plurality of membranes adjacent to one another, to form a suspended surface with total base area (sum of the areas of the adjacent membranes) of several square millimetres, according to the need. The extension hc of the buried cavity <NUM> in the direction Z is comprised approximately between <NUM> and <NUM>. The layer of dielectric material <NUM> has a substantially uniform thickness hI; for example, it may be an atomic monolayer or may be formed by thousands of atomic monolayers arranged on top of one another. The buried conductive region <NUM> has, in top plan view in the plane XY, a shape and size defined by the buried cavity <NUM> and by the layer of dielectric material <NUM>.

The buried conductive region <NUM> is formed, according to one aspect of the present disclosure, in a buried cavity <NUM> in the semiconductor substrate <NUM>. The walls of the buried cavity <NUM> are completely covered by the dielectric <NUM>, and extending over the dielectric layer <NUM>, inside the buried cavity <NUM>, is the buried conductive region <NUM>. The buried conductive region <NUM> may fill the buried cavity <NUM> completely and uniformly (<FIG>) or else only partially (<FIG>), to define a hollow region <NUM> inside the buried conductive region <NUM> that is completely surrounded by the buried conductive region <NUM>. The embodiment of <FIG> enables a better dissipation of heat as compared to the embodiment of <FIG>.

The presence or otherwise of one or more cavities internal to the buried conductive region <NUM> may likewise depend upon the filling method used.

The buried conductive region <NUM> is connected to the top surface of the epitaxial layer 6a by one or more electrical paths <NUM>, which have a main extension along Z. The electrical paths <NUM> are provided in trenches <NUM> that extend starting from the buried conductive region <NUM>, through part of the semiconductor substrate <NUM> and through the entire thickness of the epitaxial layer <NUM>, towards the top surface 6a of the epitaxial layer <NUM>. The electrical paths <NUM> are made of conductive material, for example polysilicon or metal, in particular of the same material as the one used for forming the buried conductive region <NUM> (as will be described more fully in what follows; according to one embodiment, they may be formed simultaneously with the buried conductive region <NUM>).

Further an insulating layer, formed as prolongation of the dielectric <NUM>, extends on the inner walls of the trenches <NUM> to insulate the electrical paths <NUM> electrically from the substrate <NUM> and from the epitaxial layer <NUM>. In the embodiment of <FIG> and <FIG>, as described in greater detail in what follows, the insulating layers internal to the trenches <NUM> are made in the same manufacturing step as the dielectric <NUM> and are consequently identified by the same reference number.

In order to prevent any possible undesired contamination of the epitaxial layer <NUM> and of the substrate <NUM> by the filling metal material of the buried cavity <NUM> and of the trenches <NUM>, it is possible to carry out, prior to the step of formation of the dielectric <NUM>, a step of formation of a barrier layer (not illustrated in the figures) designed to prevent diffusion of metal ions within the epitaxial layer <NUM> and the substrate <NUM>.

The electrical paths <NUM> are electrically connected to conductive paths <NUM>, which extend on the top surface 6a of the epitaxial layer <NUM>. The conductive paths <NUM> are further electrically insulated from the epitaxial layer <NUM> by interposition of a dielectric or insulating layer <NUM>. In an embodiment, the dielectric layer <NUM> extends on the top surface 6a as a prolongation of the dielectric <NUM>, whereas the conductive paths <NUM> extend on the dielectric layer <NUM> as a prolongation of the buried conductive region <NUM>.

The die <NUM> further comprises a pre-metal dielectric (PMD) layer <NUM> made, for example, of silicon oxide, which extends over the top surface 6a of the epitaxial layer <NUM>.

The pre-metal dielectric layer <NUM> may, for example, be made of silicon oxide and have a thickness chosen according to the need, for example comprised approximately between <NUM> and <NUM>.

For electrical access to one or more conductive paths <NUM>, one or more conductive trenches <NUM> extend through the pre-metal dielectric layer <NUM>, until the one or more conductive paths <NUM> are electrically contacted.

Extending on a bottom surface 2b of the substrate <NUM>, opposite to the top surface 2a of the substrate <NUM>, is a back electrical-contact region <NUM>, made, for example, of conductive material, such as a metal.

In use, the buried conductive region <NUM> has the function of first plate of the capacitor <NUM>, which may be biased at a working voltage VP by the conductive trench <NUM>, the conductive path <NUM> coupled thereto, and the corresponding electrical path <NUM>. The substrate <NUM> forms a second plate of the capacitor <NUM>, which may be biased at a respective working voltage by the back electrical contact <NUM>. In the example of <FIG> and <FIG>, the working voltage applied on the back electrical contact <NUM> is the ground voltage GND.

The dielectric <NUM> that extends between the buried conductive region <NUM> and the substrate <NUM> forms a dielectric of the capacitor <NUM> arranged between the first and second plates.

Capacitor <NUM> is therefore a planar capacitor whose plates lie on a respective plane parallel to the XY plane, i.e. parallel to the plane of main extension of substrate <NUM>. In other words, the first plate of the capacitor, the second plate of the capacitor and the dielectric interposed are arranged one above the other (overlapped) along the Z-axis which is orthogonal to the top and bottom surfaces 2a, 2b of substrate <NUM>, and to the top surface 6a of epitaxial layer <NUM>.

According to the present invention, the epitaxial layer <NUM> houses, in a region <NUM>', one or more electronic components, in particular designed and coupled to one another to form an electronic circuit <NUM>. The region <NUM>' is a region that extends over the cavity <NUM> (i.e., the region <NUM>' and the cavity <NUM> are superimposed on one another in top plan view). The electronic components that form the electronic circuit <NUM> may include active components such as transistors (e.g., MOS transistors, DMOS transistors, VDMOS transistors, trench-MOS transistors, bipolar transistors, etc.), or else passive components such as resistors and/or diodes, or in general any other electronic component. Electrical-connection paths <NUM> (only one of which is illustrated in the figures) form respective electrical paths for supplying/picking up electrical signals to/from the electronic circuit <NUM>. The region that houses the electronic circuit <NUM> is an active region of the die <NUM>, in which phenomena of transport and conduction of electric charge take place. Due to the configuration of capacitor <NUM> of planar type, the space devoted to house the electronic cuircuit <NUM> is maximized and optimized.

<FIG> illustrate in top plan view in the plane XY, limitedly to the elements of interest, respective layouts of the die <NUM> of <FIG> and <FIG>.

With reference to <FIG>, a plurality of trenches <NUM> are present (here, two, but the number may be any), coupled to respective conductive paths <NUM>, each of which is adapted to provide a point of electrical access for biasing the buried conductive region <NUM>. The region <NUM>' that houses the electronic circuit <NUM> extends, in this example, between the trenches <NUM>.

With reference to <FIG>, a single trench <NUM>, which is U-shaped, is present. Likewise, a conductive path <NUM> extends in a position corresponding to the trench <NUM> and substantially follows the shape thereof in plan view, as does the conductive trench <NUM>. This embodiment presents the advantage of providing a greater area of electrical contact for biasing the buried conductive region <NUM>, consequently reducing the series resistance. The region <NUM>' that houses the electronic circuit <NUM> is, in this example, partially surrounded by the trench <NUM>.

In an embodiment not illustrated, two U-shaped trenches <NUM> may be present, which are specular to one another with respect to an axis parallel to the direction X.

In a further embodiment, which is not shown either, there may be present one or more trenches that have a substantially rectangular shape, with a main extension along the axis X and/or along the axis Y.

<FIG> illustrates a further embodiment in which a plurality of trenches <NUM> are present, which partially surround the electronic circuit <NUM>.

<FIG> shows the die <NUM> in a further embodiment that is not part of the present invention. Here, the back electrical contact <NUM> is not present, and a conductive via <NUM> extends through the pre-metal dielectric layer <NUM> until the epitaxial layer <NUM>, and via the latter the substrate <NUM>, is reached and electrically contacted at its top surface 6a, at a distance from the conductive paths <NUM>. In a way similar to what has been described previously, the buried conductive region <NUM> forms a first plate of the capacitor <NUM>, the dielectric <NUM> forms a dielectric arranged between the plates of the capacitor <NUM>, and the substrate <NUM> forms a second plate of the capacitor <NUM>.

<FIG> is a schematic lateral-sectional view, in the triaxial system X, Y, Z, of a portion of a die <NUM>, in particular integrating a capacitor <NUM>, according to a further embodiment of the present invention.

In a way similar to what has been described with reference to <FIG> and <FIG> (the same reference numbers identify elements that are in common) the die <NUM> comprises a semiconductor substrate <NUM> extending on which is an epitaxial layer <NUM>, both being, for example, of an N type; likewise extending in the substrate <NUM> is a buried cavity <NUM>. Extending in the buried cavity <NUM>, and in particular on the internal wall of the buried cavity <NUM>, is an insulating region <NUM>, made, for example, of silicon oxide.

Extending on the insulating region <NUM>, inside the buried cavity <NUM>, is a first conductive region <NUM>, made, for example, of doped polysilicon, or else of metal or a metal alloy. Examples of materials that may be used include, but are not limited to, Ru, Pt, Ir, Pd, Ag, Au, W, Cu, Co, Fe, Ni, Mo, Ta, Ti, Al, doped Si, doped Ge, etc. The first conductive region <NUM> is completely insulated from the substrate <NUM> by the insulating region <NUM>.

Extending on the first conductive region <NUM>, in the buried cavity <NUM>, is a dielectric region <NUM>, in particular a dielectric with a high dielectric constant k (known in the art as "high-k material"). Materials that may be used include, but not are limited to, Al<NUM>O<NUM>, TiO<NUM>, GeO<NUM>, Si<NUM>N<NUM>, La<NUM>O<NUM>, etc. SiO<NUM> may alternatively be used.

Finally, extending on the dielectric region <NUM> is a second conductive region <NUM>, made, for example, of doped polysilicon, metal, or a metal alloy. The materials referred to previously for the first conductive region <NUM> may be used also in this case. The second conductive region <NUM> is completely insulated from the first conductive region <NUM> by the dielectric region <NUM>. In other words, the dielectric region <NUM> is arranged between the first and second conductive regions <NUM>, <NUM>.

In the embodiment of <FIG>, the second conductive region <NUM> delimits within it a hollow portion <NUM>'. In a different embodiment (not illustrated), the second conductive region <NUM> may fill the hollow portion <NUM>' completely, the latter thus not being present.

The first and second conductive regions <NUM>, <NUM> are electrically accessible by respective first and second electrical paths <NUM>, <NUM>, which extend, substantially in the direction Z, in trenches <NUM> formed through the epitaxial layer <NUM> and in part through the semiconductor substrate <NUM>. The first and second electrical paths <NUM>, <NUM> are made, for example, of doped polysilicon, or metal material, in particular of the same material as the one used for formation of the first and second conductive regions <NUM>, <NUM>. Further, it may be noted that the insulating region <NUM> extends through the trenches <NUM>, in contact with the inner walls of the trenches <NUM>, between the substrate <NUM>/epitaxial layer <NUM> and the first electrical path <NUM>, so as to insulate electrically the first electrical contact <NUM> from the substrate <NUM>/epitaxial layer <NUM>. Likewise, also the dielectric region <NUM> extends through the trenches <NUM>, between the first electrical path <NUM> and the second electrical path <NUM>, for electrically insulating the first electrical path <NUM> from the second electrical path <NUM>. In this way, the first and second conductive regions <NUM>, <NUM> are electrically accessible independently of one another.

In order to prevent any possible undesired contamination of the epitaxial layer <NUM> and of the substrate <NUM> by the filling metal material of the buried cavity <NUM> and of the trenches <NUM>, it is possible to carry out, prior to the step of formation of the insulating region <NUM>, a step of formation of a barrier layer (not illustrated in the figures) designed to prevent diffusion of metal ions within the epitaxial layer <NUM> and the substrate <NUM>.

The first and second electrical paths <NUM>, <NUM> are electrically coupled to respective first and second conductive paths <NUM>, <NUM> that extend above the epitaxial layer <NUM>, insulated from the latter by an insulating layer <NUM>, which extends as a prolongation of the portion of the insulating region <NUM> inside the trenches <NUM> (this is, according to one aspect of the present invention, a single layer formed in a same manufacturing step; according to an alternative aspect, the insulating layer <NUM> could be formed in a different manufacturing step).

The die <NUM> further comprises a pre-metal dielectric (PMD) layer <NUM>, made, for example, of silicon oxide, which extends on the top surface 6a of the epitaxial layer <NUM>, coating the first and second conductive paths <NUM>, <NUM>.

The pre-metal dielectric layer <NUM> may, for example, be made of silicon oxide and have a thickness chosen according to the need, for example comprised between <NUM> and <NUM>.

Finally, first and second conductive trenches <NUM>, <NUM> extend through the pre-metal dielectric layer <NUM> until they electrically contact the first and second conductive paths <NUM>, <NUM>, respectively.

In a way similar to what has been described with reference to <FIG>, according to the present invention, the epitaxial layer <NUM> houses, in a region <NUM>', one or more electronic components, in particular designed and coupled to one another to form an electronic circuit <NUM>. The region <NUM>' is a region that extends over the cavity <NUM> (i.e., the region <NUM>' and the cavity <NUM> are superimposed on one another in top plan view). The electronic components that form the electronic circuit <NUM> may include active components such as transistors (e.g., MOS transistors, DMOS transistors, VDMOS transistors, trench-MOS transistors, bipolar transistors, etc.), or else passive components such as resistors and/or diodes, or in general any other electronic component. Electrical-connection paths <NUM> (just one of which is illustrated in the figures) form respective electrical paths for supplying/picking up electrical signals to/from the electronic circuit <NUM>. The region that houses the electronic circuit <NUM> is an active region of the die <NUM>, occurring in which are phenomena of transport and conduction of electric charge.

In use, the first conductive region <NUM> has the function of first plate of the capacitor <NUM>, which may be biased at a working voltage V<NUM> by the first conductive trench <NUM>, the first conductive path <NUM> coupled thereto, and the first electrical contact <NUM>. The second conductive region <NUM> has the function of second plate of the capacitor <NUM>, which may be biased at a respective working voltage V<NUM> by the second conductive trench <NUM>, the second conductive path <NUM> coupled thereto, and the second electrical contact <NUM>. The dielectric region <NUM> arranged between the first and second conductive regions <NUM>, <NUM> performs the function of dielectric arranged between the plates of the capacitor thus formed.

<FIG> show, in the same lateral sectional view as that of <FIG>, steps of processing of a semiconductor wafer <NUM> that lead to formation of the die <NUM>.

With reference to <FIG>, the semiconductor substrate <NUM> made, for example, of doped silicon, is provided as described previously.

Then (<FIG>), steps of formation of the buried cavity (designated by the reference number <NUM> in <FIG>) are carried out, for example according to the method of creation of buried cavities described in <CIT>, filed in the name of the present applicant.

For this purpose (<FIG>), an etch mask <NUM> is formed on the surface 2a of the substrate <NUM>, made, for example, of silicon oxide. Alternatively, the mask may be a photolithographic mask, of photoresist. The mask <NUM> is defined so as to provide a plurality of openings <NUM>' in the region where the buried cavity <NUM> is to be formed.

<FIG> shows, in top plan view in the plane XY, the portion of the photolithographic mask <NUM> including the openings <NUM>'. In this example, the openings <NUM>' have, by way of example, a quadrangular shape, for example a square shape with side lB comprised between <NUM> and <NUM>, and form an array of openings in which each opening <NUM>' is arranged at a distance lD from an immediately adjacent opening comprised between <NUM> and <NUM>.

It is, however, evident that the openings <NUM>' may have a shape and/or spatial arrangement different from the one illustrated in <FIG> (for example, they may be circular or generically polygonal).

Next (<FIG>), an etching step is carried out, for example dry RIE, for selective removal of portions of the substrate <NUM> exposed through the openings <NUM>' of the mask <NUM>. During etching, portions of the semiconductor substrate <NUM> not protected by the mask <NUM> are removed, and etching proceeds until a desired depth, for example comprised between <NUM> and <NUM>, is reached (depth along Z measured starting from the surface 2a).

Then, the etch mask <NUM> is removed. Trenches <NUM> are thus formed in the substrate <NUM>.

In one embodiment, each trench <NUM> has a square shape, in top plan view in the plane XY, with side a of a value substantially defined by the openings <NUM>' of the etch mask <NUM>, comprised between <NUM> and <NUM>, and a depth, measured along Z starting from the surface 2a of the substrate <NUM>, of a value comprised between <NUM> and <NUM>. Each trench <NUM> is separated from another adjacent trench <NUM>, along X, by walls or columns <NUM> of a thickness c comprised between <NUM> and <NUM>.

According to what is described with reference to <FIG>, the trenches <NUM> that, in subsequent steps, will concur in formation of a buried cavity, are provided exclusively in the substrate <NUM>. In this case, also the buried cavity <NUM> will be formed substantially in the substrate <NUM>. In the case where the buried cavity were to be formed at a height, along Z, greater than the thickness of the substrate <NUM>, it is possible to carry out, prior to the step of <FIG>, an epitaxial growth (in a way not illustrated in the figure).

With reference to <FIG>, an epitaxial growth is carried out in deoxidizing environment (typically, in an atmosphere having a high hydrogen concentration, preferably using trichlorosilane - SiHCl<NUM>). Consequently, an epitaxial layer <NUM>, here having the first conductivity, grows on the silicon columns <NUM> and closes the trenches <NUM> at the top, trapping in the trenches <NUM> the gas present in the epitaxial-growth reactor (here, hydrogen molecules - H<NUM>). The thickness of the epitaxial layer <NUM> is made of some microns, for example between <NUM> and <NUM>.

An annealing step is then carried out, for example for <NUM> at <NUM>. The annealing step causes (<FIG>) migration of the silicon atoms, which tend to move into the position of lower energy, in a per se known manner, as, for example, discussed in the paper by <NPL>.

Consequently, in the area of the trenches <NUM> where the silicon columns <NUM> are close to one another, the silicon atoms migrate completely and form the buried cavity <NUM>, closed at the top by the epitaxial layer <NUM>. Preferably, the previous annealing step is carried out in H<NUM> atmosphere so as to prevent the hydrogen present in the trenches <NUM> from escaping through the epitaxial layer <NUM> outwards and so as to increase the concentration of hydrogen present in the buried cavity <NUM> in the case where the hydrogen trapped during the step of epitaxial growth were not sufficient. Alternatively, annealing may be carried out in a nitrogen environment.

Formation of a buried cavity <NUM> may likewise be carried out according to other processes of a known type, for example, as described in the scientific paper by <NPL>. The method described in the aforementioned scientific paper by Tsutomu Sato, et al. specify some parameters useful for setting the depth at which the buried cavity is formed.

According to a further embodiment, the buried cavity <NUM> may likewise be formed according to the process described in the paper by <NPL>.

Irrespective of the embodiment chosen for the formation of the buried cavity <NUM>, process steps, in themselves known, are then carried out as illustrated in <FIG>, for the formation of one or more electronic components integrated in the epitaxial layer <NUM>, which form the aforementioned electronic circuit <NUM>. The electronic circuit <NUM> is created at portions of the epitaxial layer <NUM> that extend above the buried cavity <NUM>. The steps of formation of the electronic circuit <NUM> may include steps of deposition of semiconductor material, implantations of dopant species, lithographic and etching steps, etc..

Then (<FIG>), a step is carried out of formation and photolithographic definition of an etch mask <NUM>, having openings <NUM>' corresponding to regions where the trenches <NUM> that reach the buried cavity <NUM>, thus arranging it in communication with the external environment, are to be formed. The etch mask <NUM> protects, in this step and in the subsequent steps, the underlying electronic circuit <NUM>.

By way of example, the openings <NUM>' of the etch mask <NUM> extend, in view in the plane XY, so as to implement one of the embodiments of <FIG>, or another embodiment provided by the present disclosure. In view in the plane XZ, the openings <NUM>' extend, along Z, above the cavity <NUM>.

Further, according to a further aspect of the present disclosure, the size of the openings <NUM>' may be selected so that the aspect ratio of the trenches <NUM> (ratio between the depth of the trenches <NUM> and their maximum width) is equal to <NUM> or higher than <NUM>, for example comprised between <NUM> and <NUM>.

In detail, the trenches <NUM> are provided by wet or dry etching of the wafer <NUM> (represented schematically, in <FIG>, by arrows <NUM>), for selective removal of exposed portions of the epitaxial layer <NUM>, until the buried cavity <NUM> is reached. The trenches <NUM> are formed in peripheral regions of the buried cavity <NUM>, at a sufficient distance from the electronic circuit <NUM> so as not to jeopardise operation or structural integrity thereof. The epitaxial layer <NUM> (here of monocrystalline silicon) may be removed by an etching chemistry with a base of sulphur hexafluoride (SF<NUM>) and octafluorocyclobutane (C<NUM>F<NUM>). Other etching chemistries may be used, according to the need.

The etch mask <NUM> may then be removed from the wafer <NUM>.

Next (<FIG>), a step of at least partial filling of the buried cavity <NUM> is carried out to provide a plate <NUM> of the capacitor <NUM> and the dielectric <NUM>, according to one of the embodiments of <FIG>, <FIG>, and <FIG>. A similar procedure is carried out to provide the capacitor <NUM> of <FIG>.

For this purpose, according to one aspect of the present disclosure, the wafer <NUM> is arranged in a deposition reactor, in particular a reactor configured to carry out atomic-layer deposition (ALD), and ALD of dielectric material, for example Al<NUM>O<NUM>, TiO<NUM>, GeO<NUM>, Si<NUM>N<NUM>, La<NUM>O<NUM>, is carried out to form the dielectric layer <NUM> described previously. The ALD technique enables a uniform deposition of the dielectric inside the cavity <NUM> and along the walls of the trenches <NUM>. The deposition parameters envisage a temperature comprised between <NUM> and <NUM>.

As an alternative to the ALD step, it is possible to form the dielectric layer <NUM> by a step of thermal growth of silicon oxide.

Then, a step is carried out of deposition, for example by CVD, of polysilicon (in this example, with a doping of an N type) or of metal material such as tungsten (W) or titanium (Ti) or copper (Cu), to form the buried conductive region <NUM>. By adjusting the deposition parameters, in particular by selecting a temperature comprised between <NUM> and <NUM>, the present applicant has found that the conductive material chosen penetrates into the trenches <NUM> and deposits on the side walls, top wall, and bottom wall of the buried cavity <NUM>, to form a filling layer that coats the inner walls of the buried cavity <NUM> completely. At the same time, the conductive material coats the walls of the trenches <NUM>, to form an electrical path in contact with the buried conductive region in the cavity <NUM>. The process of deposition of conductive material continues until the trenches <NUM> are completely filled.

The dielectric layer <NUM> has likewise the function of protective barrier against diffusion of conductive species (in particular metal) of the buried conductive region <NUM> within the substrate <NUM> and the epitaxial layer <NUM>.

With the previous steps, respective dielectric and conductive layers are formed on the top surface 6a of the epitaxial layer <NUM>. A subsequent step of photolithographic definition of said layers at the top surface 6a of the epitaxial layer <NUM> enables formation of the conductive paths <NUM> and of the underlying dielectric layer <NUM> of <FIG>.

The step previously described of deposition of the buried conductive region <NUM> by CVD may be replaced, or integrated, with a step of deposition by ALD technique, which may be used for covering more complex geometries, such as possible corners of the buried cavity and/or for deposition of metal materials with high conductivity (aluminium, copper, etc.).

Next (<FIG>), the pre-metal dielectric (PMD) layer <NUM> is formed, for example by depositing silicon oxide, on the front of the wafer <NUM>, i.e., on the epitaxial layer <NUM> and on the conductive paths <NUM>. The pre-metal dielectric layer <NUM> is selectively removed, by known lithographic and etching steps, to form one or more trenches <NUM> (just one of which is illustrated in the figure), which, once filled with conductive material, form the respective electrical paths <NUM> previously described for electrical contact of specific portions of the electronic circuit <NUM>. Simultaneously, one or more further trenches <NUM> are formed, which, once filled with conductive material, will form the conductive trenches <NUM> of <FIG>. Likewise, in this step, also the conductive trench <NUM> of <FIG> may simultaneously be formed.

Filling of the trenches <NUM> and <NUM> is carried out, for example, by CVD, depositing metal material, in particular tungsten, aluminium, or copper.

Likewise, the back contact <NUM> is formed according to the embodiments of <FIG> and <FIG>.

The steps for the production of the capacitor <NUM> of <FIG> are similar to those described previously, with the appropriate variants for filling of the buried cavity <NUM>. In detail, after the step of <FIG>, a series of steps of thermal oxidation and/or CVD/ALD are carried out to form in succession the insulating region <NUM>, the first conductive region <NUM>, the dielectric <NUM>, and the second conductive region <NUM>. Then, the steps described with reference to <FIG> and <FIG> are carried out.

From what has been described above, the advantages of the invention illustrated, in the various embodiments, are evident.

For instance, the manufacturing process described envisages formation of a buried cavity in a monolithic semiconductor body, without the need to carry out bonding operations. The structural stability is thus improved, and the manufacturing costs are reduced. Further, the semiconductor body <NUM>, which would otherwise have an exclusive function of structural support, is exploited actively.

Further, the value of density of capacitance per unit area of the embedded capacitor according to the various embodiments of the present invention is high, in particular higher than the typical value of MIM capacitors (e.g., approximately twice, i.e., <NUM> pF/mm<NUM>).

Finally, it is evident that modifications and variations may be made to the invention described, without departing from the scope of the present disclosure, as defined in the annexed claims.

For instance, the first conductivity may be of an N type, and the second conductivity may be of a P type.

Claim 1:
A semiconductor die (<NUM>; <NUM>) comprising:
- a semiconductor body (<NUM>, <NUM>), formed by a substrate (<NUM>) and an epitaxial layer (<NUM>) provided on the substrate (<NUM>), having a front side (6a) and a back side (2b), and housing an electronic circuit (<NUM>) in the epitaxial layer (<NUM>) ;
- a buried region (<NUM>) in the substrate (<NUM>) between the electronic circuit (<NUM>) and the back side (2b), including a first layer of conductive material (<NUM>) and a dielectric layer (<NUM>) extending between the first layer of conductive material (<NUM>) and the substrate (<NUM>);
- first and second trenches (<NUM>) extending at a distance from one another;
- a first conductive path (<NUM>) extending along a direction (<NUM>) within said first and second trenches (<NUM>), through the epitaxial layer (<NUM>) and part of the substrate (<NUM>) and between the buried region (<NUM>) and the front side (6a), forming a first path for electrical access to the first layer of conductive material (<NUM>);
wherein said first layer of conductive material (<NUM>) forms a first plate of a capacitor (<NUM>) buried in the substrate (<NUM>),
wherein the buried region (<NUM>) further comprises a second layer of conductive material (<NUM>), between the dielectric layer (<NUM>) and the substrate (<NUM>), which forms a second plate of said capacitor (<NUM>), the dielectric layer (<NUM>) being the dielectric of said capacitor (<NUM>) arranged between the first and second plates of said capacitor (<NUM>),
the semiconductor die (<NUM>; <NUM>) further comprising a second conductive path (<NUM>) extending along said direction (<NUM>) in said first and second trenches (<NUM>) through the epitaxial layer (<NUM>) and part of the substrate (<NUM>) and between the buried region (<NUM>) and the front side (6a), forming a second path for electrical access to the second layer of conductive material (<NUM>),
said electronic circuit being arranged in a region (<NUM>') of the semiconductor body (<NUM>, <NUM>) between the first and the second trench (<NUM>) and being superimposed, in a top plan view, to the buried region (<NUM>).