Patent Description:
Reference is made to <FIG> showing a circuit diagram of a power metal oxide semiconductor field effect transistor (MOSFET) device <NUM>. The power MOSFET <NUM> includes a gate G, a source S and a drain D. In this example, the power MOSFET <NUM> is an n-channel device, and thus the source S and drain D are formed by n-type doped semiconductor regions and the channel (and body B) is formed by a p-type doped semiconductor region. The body B is electrically tied to the source S. A body diode D1 of the MOSFET <NUM> is formed by a p-n junction with an anode formed by the p-type doped region of the body B and a cathode formed by the n-type region of the drain D.

In a switching circuit application, the body diode D1 is in reverse mode when the power MOSFET <NUM> is gate controlled to be conducting. When the power MOSFET <NUM> is subsequently turned off, the body diode D1, in its anti-parallel circuit configuration, will be switched on in forward mode. The body diode D1 may, for example, have a forward voltage drop (Vf) of about <NUM>. This forward voltage drop, however, is too high to support industry demand for faster switching speeds and higher efficiency.

<CIT> describes a semiconductor device, e.g. part of motor vehicle alternator, which has P-plus doped layer and N-plus doped layer filled with P-doped polysilicon, and etched trenches provided at N-doped section in region of base and/or between P-doped layers.

There is accordingly a need in the art to address the foregoing problem.

The present invention relates to an integrated circuit according to claim <NUM>.

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:.

Reference is made to <FIG> showing a circuit diagram of a power metal oxide semiconductor field effect transistor (MOSFET) device <NUM> with an embedded rectifying diode D2. The power MOSFET <NUM> includes a gate G, a source S and a drain D. In this example, the power MOSFET <NUM> is an n-channel device, and thus the source S and drain D are formed by n-type doped semiconductor regions and the channel (and body B) is formed by a p-type doped semiconductor region. The body B is electrically tied to the source S. A body diode D1 of the MOSFET <NUM> is formed by a p-n junction with an anode formed by the p-type doped region of the body B and a cathode formed by the n-type region of the drain D. An additional rectifying diode D2 is electrically coupled in parallel with body diode D1 between the body B (source S) and drain D. The rectifying diode D2 has a forward voltage drop VfD2 that is less than the forward voltage drop VfD1 of the body diode D1. As a result, there is an improvement in switching speed and efficiency with respect to the MOSFET <NUM> of <FIG>. The value of the forward voltage drop VfD2 is process tunable in a manner described herein.

In a preferred implementation, the power MOSFET <NUM> is fabricated as a monolithic integrated circuit device with the rectifying diode D2 embedded in the structure of the field effect transistor having the body diode D1. In other words, the MOSFET <NUM> and diode D2 share a common semiconductor substrate. Furthermore, as will be described in more detail herein, the transistor and rectifying diode devices may share certain structures in common.

<FIG> shows a first cross-section of the power MOSFET <NUM> fabricated as a vertical conduction transistor. A semiconductor substrate <NUM> (for example, silicon) that is n-type doped includes a back surface. A first metal layer <NUM> at the back surface of the substrate <NUM> provides the drain electrode for the transistor <NUM>. An n-type doped epitaxial layer <NUM>, for example made of silicon, is formed from the upper surface of the substrate <NUM>. The epitaxial layer <NUM> is more lightly doped than the semiconductor substrate <NUM> and forms an n-type drift region <NUM> for the drain of the transistor. A more heavily n-type doped region <NUM> at the front surface of the epitaxial layer <NUM> provides the source region of the transistor <NUM>. The bottom of the n-type doped region <NUM> is spaced from the front surface of the epitaxial layer <NUM> to a depth t4 (where the depth t4 is about <NUM>, for example in a range of <NUM> to <NUM>). A p-type doped region <NUM> buried in the epitaxial layer <NUM>, between the doped region for the source and the n-type drift region <NUM>, provides the body region of the transistor <NUM>. The bottom of the p-type doped region <NUM> is spaced from the front surface of the epitaxial layer <NUM> to a depth t2 (where the depth t2 is about <NUM>, for example in a range of <NUM> to <NUM>). Trenches <NUM> are formed in the epitaxial layer <NUM> on either side of the n-type drift region <NUM>. The trenches <NUM> extend from the front surface of the epitaxial layer <NUM> completely through the regions <NUM> and <NUM> to a depth that is deeper than the bottom of the buried p-type doped region <NUM>, but without reaching the top of the n-type doped substrate <NUM>. The trenches are filled with an insulating material <NUM> (such as a dielectric material in the form of an oxide). A field plate electrode <NUM> is located within each trench <NUM>. The field plate electrode <NUM> may, for example, be made of a polysilicon material deposited within a sub-trench <NUM> (formed in (or by) the insulation material <NUM>) and insulated from the epitaxial layer <NUM> by the insulation material <NUM>. A gate electrode <NUM> is also located within each trench <NUM> on opposite sides of the field plate electrode <NUM>. Each gate electrode <NUM> may, for example, be made of a polysilicon material deposited within a sub-trench. The gate electrode <NUM> is insulated from the field plate electrode <NUM> by an interposed (i.e., inter-poly) oxide layer 42a. The gate electrode <NUM> is further insulated from the semiconductor regions <NUM>, <NUM> and <NUM> (of the epitaxial layer <NUM>) by a gate oxide layer 42b having a thickness t1 (where the thickness t1 is about 750Å, for example in a range of 675Å to 825Å). The thicknesses of the inter-poly oxide layer 42a and the gate oxide layer 42b will typically be different, with the thickness t1 being thinner. The gate electrodes <NUM> extend from the front surface of the epitaxial layer <NUM> to a depth t3 (where depth t3 is greater than depth t2; where the depth t3 is about <NUM>, for example in a range of <NUM> to <NUM>) and have a width w in the plane of the cross-section (where the width w is about <NUM>, for example in a range of <NUM> to <NUM>). A more heavily p-type doped region <NUM> is buried within the buried p-type doped region <NUM> at a position between two adjacent trenches <NUM> to provide a contact to the p-type doped region <NUM>. An insulating layer <NUM> extends over the top surface of the epitaxial layer <NUM> (it will be noted that the layer <NUM> may be fabricated of a stack of insulating layers). A first opening <NUM> extends through the insulating layer <NUM> at a position aligned with the more heavily p-type doped region <NUM>. The first opening <NUM> further extends through the more heavily n-type doped region <NUM> at the front surface of the epitaxial layer (and may, depending on the location of the heavily p-type doped region <NUM>, further extend partially through the p-type doped region <NUM> for the body of the transistor). The first opening <NUM> is filled with a metal material forming a portion <NUM> of the source S electrode of the transistor. It will be noted that the metal material of portion <NUM> is in physical and electrical contact directly with both the more heavily n-type doped region <NUM> forming the source region and the heavily p-type doped region <NUM> forming the contact to the p-type doped region <NUM> for the body of the transistor. A second metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the source S electrode for the transistor.

A TEM image of the <FIG> cross-section is shown in <FIG>.

<FIG> shows a second cross-section of the power MOSFET <NUM>. The second cross-section of <FIG> is made in a plane parallel to, but offset from, the plane of the first cross-section of <FIG>. Like reference numbers refer to same component parts. The offset between the cross-sections of <FIG> is in the direction orthogonal to the parallel planes of those cross-sections (i.e., in a direction into/out of the page of the drawing illustration). A second opening <NUM> extends through the insulating layer <NUM> at a position aligned with each gate electrode <NUM>. The second opening <NUM> is filled with a metal material forming a portion <NUM> of the gate electrode of the transistor. It will be noted that the metal of portion <NUM> is in electrical contact with the polysilicon material of the gate electrode <NUM>. A third metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the gate G electrode for the transistor.

<FIG> shows a third cross-section of the power MOSFET <NUM>. The third cross-section of <FIG> is made in a plane parallel to, but offset from, the planes of the first and second cross-sections of <FIG>, respectively. Like reference numbers refer to same component parts. The offsets between the cross-sections of <FIG> and <FIG> is in the direction orthogonal to the parallel planes of those cross-sections (i.e., in a direction into/out of the page of the drawing illustration). A third opening <NUM> extends through the insulating layer <NUM> at a position aligned with each field plate electrode <NUM>. The third opening <NUM> is filled with a metal material forming a further portion <NUM> of the source S electrode of the transistor. It will be noted that the metal of portion <NUM> is in electrical contact with the polysilicon material of the field plate electrode <NUM>. The second metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the source S electrode for the transistor.

<FIG> shows a first cross-section of a monolithic rectifying diode which is embedded with the power MOSFET <NUM> of <FIG>. Like reference numbers refer to same component parts. The structure of the rectifying diode may share in common with the structure of the power MOSFET <NUM> the following parts: substrate <NUM> (here forming a cathode region of the diode D2), first metal layer <NUM> (here providing the cathode electrode), lightly doped epitaxial layer <NUM> with n-type drift region <NUM>, trenches <NUM>, insulation material <NUM>, field plate electrode <NUM>, sub-trench <NUM>, and insulating layer <NUM>. A more heavily n-type doped region <NUM>' at the front surface of the epitaxial layer <NUM> provides a source region. The bottom of the n-type doped region <NUM>' is spaced from the front surface of the epitaxial layer <NUM> to a depth t4' (where the depth t4' is about <NUM>, for example in a range of <NUM> to <NUM>). A p-type doped region <NUM>' buried in the epitaxial layer <NUM>, between the doped region for the source and the n-type drift region <NUM>, provides a body region. The doping concentration level of the p-type dopant for region <NUM>' is selected in connection with tuning the forward voltage drop VfD2 of the diode D2. The bottom of the p-type doped region <NUM>' is spaced from the front surface of the epitaxial layer <NUM> to a depth t2' (where the depth t2' is less than the depth t2; where the depth t2' is about <NUM>, for example in a range of <NUM> to <NUM>). The depth t2'of the p-type doped region <NUM>', which defines the channel length, is selected in connection with tuning the forward voltage drop VfD2 of the diode D2. The trenches <NUM> extend completely through regions <NUM>' and <NUM>' and terminate within the epitaxial layer <NUM>. A gate electrode <NUM>' is also located within each trench <NUM> on opposite sides of the field plate electrode <NUM>. Each gate electrode <NUM>' may, for example, be made of a polysilicon material. The gate electrode <NUM>' is insulated from the field plate electrode <NUM> by an interposed (i.e., inter-poly) oxide layer 42a'. The gate electrode is further insulated from the semiconductor regions <NUM>', <NUM>' and <NUM> (of the epitaxial layer <NUM>) by a gate oxide layer 42b' having a thickness t1' (where the thickness t1' is less than the thickness t1; where the thickness t1' is about 50Å, for example in a range of 40Å to 60Å). The thickness t1'of the gate oxide layer 42b' is selected in connection with tuning the forward voltage drop VfD2 of the diode D2. The gate electrodes <NUM>' extend from the front surface of the epitaxial layer <NUM> to a depth t3' (where the depth t3' is greater than depth t2', and wherein the depth t3' is less than the depth t3; where the depth t3' is about <NUM>, for example in a range of <NUM> to <NUM>) and have a width w' in the plane of the cross-section (where the width w is less than the width w'; where the width w' is about <NUM>, for example in a range of <NUM> to <NUM>). A more heavily p-type doped region <NUM>' is buried within the buried p-type doped region <NUM>' at a position between two adjacent trenches <NUM> to provide a contact for the body region. A fourth opening <NUM> extends through the insulating layer <NUM> at a position aligned with the more heavily p-type doped region <NUM>'. The fourth opening <NUM> further extends through the more heavily n-type doped region <NUM>' at the front surface of the epitaxial layer (and may, depending on the location of the heavily p-type doped region <NUM>', further extend partially through the p-type doped region <NUM>' for the body of the transistor). The fourth opening <NUM> is filled with a metal material forming a portion <NUM> of the anode A electrode of the rectifying diode D2. It will be noted that the metal material of portion <NUM> is in physical and electrical contact directly with both the more heavily n-type doped region <NUM>' forming the source region and the heavily p-type doped region <NUM>' forming the contact to the p-type doped region <NUM>' for the body. A fourth metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the anode A electrode. The fourth metal layer <NUM> is electrically connected (shorted) to the second metal layer <NUM> (and in an embodiment, the layers <NUM> and <NUM> may comprise a same metal layer). It will be noted that the metal layer <NUM> is also present and forms a portion of the cathode C electrode.

In an embodiment, the first cross-section of <FIG> is made in a plane parallel to, but offset from, the planes of the first, second and third cross-sections of <FIG> and <FIG> for the power MOSFET <NUM>. The offsets between the cross-sections of <FIG>, <FIG> is in the direction orthogonal to the parallel planes of those cross-sections (i.e., in a direction into/out of the page of the drawing illustration).

<FIG> shows a second cross-section of the rectifying diode. The second cross-section of <FIG> is made in a plane parallel to, but offset from, the plane of the first cross-section of <FIG>. Like reference numbers refer to same component parts. The offset between the cross-sections of <FIG> is in the direction orthogonal to the parallel planes of those cross-sections (i.e., in a direction into/out of the page of the drawing illustration). A fifth opening <NUM> extends through the insulating layer <NUM> at a position aligned with each gate electrode <NUM>'. The fifth opening <NUM> is filled with a metal material forming a portion <NUM> of the anode electrode. It will be noted that the metal of portion <NUM> is in electrical contact with the polysilicon material of the gate electrode <NUM>'. The fourth metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the anode A electrode.

<FIG> shows a third cross-section of the rectifying diode. The third cross-section of <FIG> is made in a plane parallel to, but offset from, the planes of the first and second cross-sections of <FIG>, respectively. Like reference numbers refer to same component parts. The offsets between the cross-sections of <FIG> and <FIG> is in the direction orthogonal to the parallel planes of those cross-sections (i.e., in a direction into/out of the page of the drawing illustration). A sixth opening <NUM> extends through the insulating layer <NUM> at a position aligned with each field plate electrode <NUM>. The sixth opening <NUM> is filled with a metal material forming a portion <NUM> of the anode A electrode. It will be noted that the metal of portion <NUM> is in electrical contact with the polysilicon material of the field plate electrode <NUM>. The fourth metal layer <NUM> at the top surface of the insulating layer <NUM> provides a further portion of the anode A electrode.

Reference is now made to <FIG> which shows a top (plan) view of a layout for the monolithic integrated circuit of the power metal oxide semiconductor field effect transistor (MOSFET) device <NUM> with an embedded rectifying diode D2. The plan view is illustrated at a level of the upper surface of the epitaxial layer <NUM> corresponding to the regions <NUM> and <NUM>'. The relative position of regions <NUM> and <NUM>' is shown by dotted lines as these regions are buried below the regions <NUM> and <NUM>'. Regions <NUM> and <NUM>' are not shown, but generally have a same plan layout as the regions <NUM> and <NUM>'. The electrode portions <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are shown, it being understood that the number of included portions and their positions is shown by way of example only and that in embodiments there will likely be a plurality of each portion provided. Furthermore, the illustration of just a pair of trenches is by way of example only and in a preferred implementation the layout of will include a plurality of pairs of trenches arranged parallel to each other (for example, to the left and right of the pair shown in the illustration). In this example, the trench <NUM> and its field plate electrode <NUM> are shared structures between the MOSFET <NUM> at the top and the diode D2 at the bottom. In an alternative implementation, the MOSFET <NUM> and diode D2 may instead have separate trench <NUM> and field plate electrode <NUM> structures.

Reference is now made to <FIG> which shows a top (plan) view of a layout for the monolithic integrated circuit of the power metal oxide semiconductor field effect transistor (MOSFET) device <NUM> with an embedded rectifying diode. The plan view is illustrated at a level of the upper surface of the epitaxial layer <NUM> corresponding to the regions <NUM> and <NUM>'. In this layout the structures for the MOSFET device <NUM> with the embedded rectifying diode D2 are arranged side-by-side (as opposed to the aligned layout as shown in <FIG>). It will be understood that the layout for the embedded rectifying diode D2 as shown on the left of the layout for the MOSFET device <NUM> in <FIG> could be replicated on the right of the layout for the MOSFET device <NUM>. Additionally, as noted above in connection with the layout of <FIG>, the illustration of just a pair of trenches is by way of example only and in a preferred implementation the layout of each of the MOSFET device <NUM> and the embedded rectifying diode D2 will include a plurality of pairs of trenches.

The plan views of <FIG> are examples only of layout configurations. The illustrations are not drawn to scale. Furthermore, the illustrations do not show the layout for a complete monolithic device. The layout structures as illustrated may be replicated a plurality of times and arranged in a tiled or cell manner as is well-known to those skilled in the art.

<FIG> show process steps for the fabrication of the gates <NUM>, <NUM>' and gate oxide layers <NUM>, <NUM>' for the MOSFET device <NUM> with the embedded rectifying diode D2. It will be noted that the left side in each of <FIG> shows a location where the MOSFET device <NUM> (with D1) is being fabricated and the right side in each of <FIG> shows a location where the embedded rectifying diode D2 is being fabricated. The steps of <FIG> are illustrative only and do not show all structures or all individual process steps. The drawings are not presented to scale.

In <FIG>, standard fabrication processes well known to those skilled in the art have already been performed to produce the trenches <NUM>, insulating material <NUM>, sub-trenches <NUM> and field plate electrodes <NUM>. As an example of such a process: the trenches <NUM> are produced in the epitaxial layer <NUM> by an etch process; a conformal insulating material layer is deposited to line each trench and define the sub-trench <NUM>; a polysilicon material is then deposited to fill each sub-trench; a polishing operation is performed to remove excess polysilicon material and define the field plate electrode <NUM>.

In <FIG>, a mask <NUM> is provided over the location where the MOSFET device <NUM> is being fabricated. An etch is then performed to remove a portion of the insulating material <NUM> at an upper part of the trench in location where the embedded rectifying diode D2 is being fabricated. The etch here is performed to the depth t3'.

In <FIG>, a thermal oxidation is performed to grow the gate oxide 42b' with a thickness t1' on the surface of the epitaxial layer <NUM> (at regions <NUM>', <NUM>' and <NUM>) which is exposed as a result of the etch in <FIG>. By controlling the parameters of the thermal oxidation, the thickness t1' can be selected in connection with tuning the forward voltage drop VfD2 of the diode D2. It will be noted that this thermal oxidation step will further produce the inter-poly oxide layer 42a'.

In <FIG>, polysilicon material is deposited to fill the opening and form the gate <NUM>'.

In <FIG>, a mask <NUM> is provided over the location where the embedded rectifying diode D2 is being fabricated. An etch is then performed to remove a portion of the insulating material <NUM> at an upper part of the trench in location where the MOSFET device <NUM> is being fabricated. The etch here is performed to the depth t3.

In <FIG>, a thermal oxidation is performed to grow the gate oxide 42b with a thickness t1 on the surface of the epitaxial layer <NUM> (at regions <NUM>, <NUM> and <NUM>) which is exposed as a result of the etch in <FIG>. It will be noted that this thermal oxidation step will further produce the inter-poly oxide layer 42a.

In <FIG>, polysilicon material is deposited to fill the opening and form the gate <NUM>.

The fabrication process continues with the use of well-known masking and dopant implantation steps to form the regions <NUM> and <NUM> for the transistor <NUM> (left side) and the regions <NUM>' and <NUM>' for the rectifying diode D2 (right side). The result is shown in <FIG>. By controlling the parameters of the implantation process, the thickness t2' and the dopant concentration in region <NUM>' can be selected in connection with tuning the forward voltage drop VfD2 of the diode D2.

Claim 1:
An integrated circuit, comprising:
a semiconductor layer (<NUM>) doped with a dopant of a first-type;
a MOSFET device (<NUM>), comprising:
a first trench (<NUM>) in said semiconductor layer;
a first region (<NUM>) of the semiconductor layer doped with the dopant of the first-type at a top surface of the semiconductor layer;
a third region (<NUM>) of the semiconductor layer doped with a dopant of a second-type opposite the first-type and positioned between the first region and a first drift region (<NUM>) formed by the semiconductor layer; and
a first gate (<NUM>) located within the first trench and separated from the first region and third region by a first gate oxide layer (42b) having a first thickness (t1);
a diode device (D2), comprising:
a second trench (<NUM>) in said semiconductor layer;
a second region (<NUM>') of the semiconductor layer doped with the dopant of the first-type at the top surface of the semiconductor layer, wherein the first and second regions are separated from each other;
a fourth region (<NUM>') doped with the dopant of the second-type and positioned between the second region and a second drift region (<NUM>) formed by the semiconductor layer; and
a second gate (<NUM>') located within the second trench and separated from the second region and fourth region by a second gate oxide layer (42b') having a second thickness (t1') that is less than the first thickness;
wherein the diode device is electrically connected in parallel with a body diode (D1) of the MOSFET device;
wherein the diode device (D2) is configured to have a forward voltage drop (VfD2) that is less than the forward voltage drop (VfD1) of the body diode (D1); and
wherein a gate electrode (<NUM>) for the MOSFET device is electrically connected to the first gate; and an anode electrode (<NUM>) of the diode device is electrically connected to the second gate.