Patent Description:
Nonvolatile memories are utilized for storing data including during times when the memory is not powered.

<CIT> describes a method and apparatus for managing data in a memory, such as a flash memory array. In particular, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

<CIT> describes systems and methods for data retention manager in a solid state storage system utilizing temperature measurement mechanisms. Background data scanning can provide an efficient way to monitor data health and can be used to determine whether data refreshing is needed or to prevent data retention from degrading beyond error correction capabilities. In particular, data scanning may be performed as a background process regularly, for example, every month. Furthermore, a numerical integral method is used for taking account the system temperature by using the acceleration factor for data retention.

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.

The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.

As disclosed herein, a temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuity for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.

In some embodiments, reading nonvolatile memory cells to determine a retention error rate that correlates to a particular temperature exposure profile may provide for a system that can monitor temperature exposure without having to be powered.

<FIG> is a temperature disclosure detection system <NUM> according to one embodiment of the present invention. System <NUM> includes an array of nonvolatile memory cells <NUM> that are arranged in rows and columns. In the embodiment shown, array <NUM> includes <NUM> subarray portions of cells (cell groups <NUM>-<NUM>) where each subarray portion has cells with a different temperature dependent data retention error rate profile (A-E). A cells temperature dependent data retention error rate profile is based on physical aspects of the cell which define the cell's propensity to retain a stored data state over a range of exposed temperatures.

System <NUM> includes wordline driver circuitry <NUM> which includes a decoder <NUM> and a plurality of wordline drivers each connected to a wordline (WLS A-WLS E) of a row of array <NUM>. Circuitry <NUM> asserts a wordline to a row of array <NUM> to access memory cells of the row for a memory read or write operation. In the embodiment shown, wordlines WLS A are for accessing cells of a row in the sub array portion of cell group <NUM>, wordlines WLS B are for accessing cells of a row in the sub array portion of cell group <NUM>, wordlines WLS C are for accessing cells of a row in the sub array portion of cell group <NUM>, wordlines WLS D are for accessing cells of a row in the sub array portion of cell group <NUM>, and wordlines WLS E are for accessing cells of a row in the sub array portion of cell group <NUM>. Decoder <NUM> receives a portion of a memory address (ADDRESS) from determination circuitry <NUM> and activates the wordline driver of circuitry <NUM> corresponding to the received address to assert the wordline of the cells of the address.

System <NUM> includes column mux and write circuitry <NUM> for writing data to cells of array <NUM> for memory operations. Circuitry <NUM> receives a portion of an address (ADDRESS) from determination circuitry <NUM> where a decoder of circuitry <NUM> controls column multiplexers of circuitry <NUM> to direct the columns of the cells of an address to the write circuitry of circuitry <NUM> to be written to during a memory operation. In the embodiment shown, the column multiplexers of circuitry <NUM> also direct the columns of the cells of an address to the sense amplifiers <NUM> for reading data of those cells during a read operation.

In the embodiment shown, system <NUM> includes an M number of sense amplifiers <NUM> for reading M number of cells during a data read operation. There are M number of N-to-<NUM> column multiplexers in circuitry <NUM> for redirecting the columns to the sense amplifiers and write circuitry during read and write operations. M may be any number such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> etc. N may be of one of a number such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> etc. Also, circuitry <NUM> may include termination circuitry for terminating the unselected columns during a read or write operation. In some embodiments, circuitry <NUM> would not include column multiplexers where every column would include its own sense amplifier. In one embodiment, array <NUM> has <NUM> rows were each group of cells <NUM>-<NUM> is located in <NUM> rows of array <NUM> which row having <NUM> cells, however the number rows and/or cells may be different in different embodiments.

In some embodiments, the specific circuitry implemented for circuitry <NUM>, sense amplifiers <NUM>, and circuitry <NUM> would depend upon the type of nonvolatile memory cells of array <NUM>. In other embodiments, each group of cells <NUM>-<NUM> be located in a separate array with each array having a corresponding wordline driver circuity, column mux and write circuitry, and sense amplifiers. In some embodiments, the cells of the different groups would be located in different columns where the different cell groups would share the same wordlines.

In the embodiment shown, determination circuitry <NUM> generates the ADDRESS values, memory operation commands (e.g., W/R), and write data (DATA IN) for performing a read or write memory operation. Circuitry <NUM> also receives the read data (DATA OUT) from the sense amplifiers (<NUM>) during a memory read operation. In the embodiment shown, circuity <NUM> includes a memory (tables <NUM>) for storing data that correlates data retention error rates determined from the memory reads of each cell group with temperature exposure profiles of the cells groups. In some embodiments where only one data state is written (e.g., all <NUM>) during a programing operation, DATA IN lines would not be located between circuitry <NUM> and circuitry <NUM>. In such an embodiment, the write circuitry would be configured to place the cells in the single data state based on the write signal during a programming operation.

In some embodiments, circuitry <NUM> may include a processor core for performing the write operations, read operations, and for determining the temperature exposure information based on the read values. In other embodiments, circuitry <NUM> may include discrete circuitry (e.g., counters, comparators, adders, shifters) for performing at least some of the operations. In still other embodiments, circuity <NUM> may include a combination of both processor cores and discrete circuitry. Also, in some embodiments, determination circuitry may include circuitry that performs other operations for a system that includes system <NUM> such as a system controller. In some embodiments, circuitry <NUM> may include a processor core for performing the memory operations and a separate processor core for determining the temperature exposure information. In some embodiments, the different processor cores (or discrete circuitry) may be located on different integrated circuits or in different component housings.

In the embodiment shown, system <NUM> includes a transceiver <NUM> for communicating wirelessly with a controller (e.g., controller <NUM> in <FIG>) for receiving commands to provide temperature exposure information and to program the system. Transceiver <NUM> also provides the temperature exposure information wirelessly to the controller. In other embodiments, system <NUM> would include I/O circuitry for receiving and providing data by a wired connection with a controller.

Examples of nonvolatile memory types cells utilized in system <NUM> include MRAM, ReRAM, FeRAM, flash, or phase change memories. In some embodiments, all of the memory cells of system <NUM> would be the same memory cell type. However, systems of other embodiments may include cells of more than one memory cell type. In some embodiments, memory cell types that have a temperature dependent data retention error rate profile where data retention varies widely with temperature exposure may be better suited for use in a temperature exposure detection monitoring system.

In some embodiments, system <NUM> may include memory cells characterized as bi-stable memory cells. With bi-stable memory cells, the cell generally resides at one of two stable memory states. For example, with some MRAM cells, the cell will be stable in either one memory state or another memory state, depending upon the magnetic polarization of the ferromagnetic free layer of the magnetic tunnel junction of the MRAM cell. See <FIG> and its corresponding description. Another type of bi-stable nonvolatile memory cell is an FeRAM memory cell.

In some embodiments, using data retention error rates as measured by memory reads to determine temperature exposure information may advantageously be useful for bi-stable nonvolatile memory cell types in that a specific degree of temperature exposure of the material of a specific memory cell cannot be easily measured due to the bi-state nature of the cell. In some embodiments, utilizing bi-stable cells over other types of memory cells may allow for a data retention error rate determination to be made by a less complicated process in that it may be performed digitally in a more simplified manner.

<FIG> is a block diagram of an MRAM memory cell <NUM> according to one embodiment of the present invention that may be implemented in array <NUM> of system <NUM>. Cell <NUM> includes a magnetic tunnel junction (MTJ) <NUM> and includes a select transistor <NUM> whose gate is connected to a wordline. When asserted, the wordline makes transistor <NUM> conductive to provide a path between the bit line of the column and the source line of the column through MTJ <NUM>. Depending upon the storage state of MTJ <NUM>, MTJ <NUM> either provides a higher resistance indicating one memory state or a lower resistance indicating a second state.

<FIG> also shows a block diagram of MTJ <NUM>. In the embodiment shown, MTJ <NUM> has several layers located between bottom electrode <NUM> and top electrode <NUM>. In one embodiment, MTJ <NUM> is located in the interconnect portion of an integrated circuit between two metal layers where bottom electrode <NUM> is a portion of a metal interconnect in a lower metal layer and electrode <NUM> is a portion of a metal interconnect in an upper metal layer.

In one embodiment, the stack of layers of MTJ <NUM> are formed by the sequential deposition and patterning during the formation of the interconnect portion of an integrated circuit. In one embodiment, each of the layers are patterned to have a cylindrical shape but may have other shapes in other embodiments. Located on bottom electrode <NUM> is a seed layer <NUM> which is deposited for the formation of an antiferromagnetic material layer <NUM>, which in one embodiment is of a synthetic antiferromagnetic material. A transition layer <NUM> is located on layer <NUM>. A ferromagnetic pinned layer <NUM>, which in the embodiment shown is made of CoFeB, is located on layer <NUM>. A tunnel layer <NUM>, which in the embodiment shown in made of MgO, is located on pinned layer <NUM>. A ferromagnetic free layer <NUM>, which in the embodiment shown is made of a CoFeB based ferromagnetic material, is located on tunnel layer <NUM>. Layer <NUM> of MgO is located on free layer <NUM>, and spacer layer <NUM> is located between layer <NUM> and electrode <NUM>. Other embodiments may include MTJs of other configurations and/or made of other materials. For example, in some embodiments, the free layer and/or pin layer may include FeB and Ta. In some embodiments, the free layer and/or pinned layer may be a composite layer of different materials.

In some embodiments, the magnetic polarization direction of the pinned layer <NUM> is fixed. The magnetic polarization direction of free layer <NUM> can be set to either a direction parallel to the magnetic polarization direction of the pinned layer <NUM> for a low resistive state or a direction anti parallel to the magnetic polarization direction of pinned layer <NUM> for a high resistive state. This type of MRAM cell is considered bi-stable in that there are only two detectable stable magnetic polarization directions of the free layer <NUM> with respect to the fixed layer <NUM> (parallel and antiparallel). In some embodiments, the magnetic polarization direction of free layer <NUM> is set by providing a current at a sufficient magnitude through MTJ <NUM>, where the direction of the current flow through MTJ <NUM> sets the magnetic polarization direction of the free layer <NUM> to the desired direction to store the desired value. MJTs of other embodiments may be written to or read from in other ways. In some embodiments, the magnetic polarization direction of the pinned layer is fixed in the plane of the MTJ. In other embodiments, the magnetic polarization direction of the pinned layer is fixed perpendicular to the plane of the MTJ.

The temperature dependent data retention error rate profile of an MTJ (the propensity of the cell to retain its programmed magnetic state and therefore its programmed data over a range of temperatures) may depend upon several factors of an MTJ. For example, differences in the thickness of the ferromagnetic layers <NUM> and <NUM> and differences in the lateral cross-sectional area of the ferromagnetic layers <NUM> and <NUM> may affect the thermal stability and therefore the temperature range in which the free layer <NUM> is able to retain its programmed magnetic polarization direction. For example, a cell with a thinner free layer may make the cell more likely to retain its programmed state at a particular temperature than a similar cell with a thicker free layer. In other embodiments, the cells of the different cell groups (<NUM>-<NUM>) could be made with different lateral cross-sectional areas of the MTJs to provide for a different temperature dependent data retention error profile for each group. For example, cells with a greater lateral cross-sectional area of the MTJ would be more likely to retain its programmed state at a particular temperature than a similar cell with smaller lateral cross-sectional area. In some embodiments, the lateral cross-sectional area of an MTJ or layer of an MTJ is the cross-sectional area of the MTJ or layer in a plane that is generally parallel with the interfacial areas between the layers of the MTJ. In the embodiment of <FIG>, the lateral cross-sectional area of MTJ <NUM> is the area of the MTJ in a plane defined from left to right and into and out of the page, relative to the view of MTJ cell <NUM> in <FIG>. In other embodiments, the number of MgO layers of an MTJ may affect thermal stability of the cell.

<FIG> is a chart showing a correlation between temperature exposure and data retention error rates for groups of cells according to one embodiment of the present invention. As shown in <FIG>, each of the five cell groups (<NUM>-<NUM>) (labeled CELLS A- CELLS E) have a different temperature dependent data retention error rate profile which provides for different data retention error rates when exposed to the same temperatures for the same period of time. As shown in <FIG>, the memory cells of group A have the high susceptibility to changing data states after being exposed at a particular temperature (are the least thermally stable) whereas the cells of group E have the lowest susceptibility to changing data states (are the most thermally stable).

In one embodiment, the MJTs of the cells of group E would have the largest lateral cross-sectional area and the MJTs of the cells of group A would have the smallest lateral cross-sectional area. The lateral cross-sectional areas of the MJTs of the cells of groups D, C, and B would be located in between. In another embodiment, the free layer of the cells of group E would be the thinnest and the free layer of the cells of group A would be the thickest.

As shown in the graph of <FIG>, as the cells are exposed to higher temperatures, the data retention error rate rise. Accordingly, by measuring the data retention error rate by performing data reads of programmed data stored in the cells, an indication can made as to the temperatures that the cells were exposed to.

In some embodiments, the correlation between temperature exposure and data retention error is strongest for data retention error rates within a certain range. In the embodiment shown in <FIG>, that range is between the HIGH VALID RATE (approximately <NUM> percent error rate) and the LOW VALID RATE (approximately <NUM> percent error rate). Accordingly, in some embodiments of a system with multiple cell groups, the system may determine temperature exposure from the error rate of the cell group or cell groups that fall in the valid error range. As shown in the graph of <FIG>, for exposure temperatures between <NUM> and <NUM> degrees C, a system will use the error rate of the cells of group A to determine temperature exposure. For temperatures between <NUM> and <NUM> degrees C, the system will use the error rate of the cells of group B to determine temperature exposure. For temperatures between <NUM> and <NUM> C, the system will use the cells of group C to determine temperature exposure. For temperatures between <NUM> and <NUM> degrees C, the system will use the cells of group D to determine temperature exposure. For temperatures between <NUM> and <NUM> degrees C, the system will use the cells of group E to determine temperature exposure.

In some embodiments, a system may use more than one group of cells to determine temperature exposure. For example, if two groups were to have an error rate within a valid error range, then the temperature exposure indicated by both groups would be averaged to obtain resultant temperature exposure data. In some embodiments, all the cells of the temperature exposure detection system have the same temperature dependent data retention error rate profile wherein temperature exposure data would be determined from just one curve.

<FIG> is a chart showing the relationship between data retention error rates of nonvolatile memory cells and temperature exposure and how those rates change based on the time after programming. In some embodiments, the longer data is stored in a memory cell, the greater the probability the data will flip states. As shown in the embodiment of <FIG>, this increase in data retention error rates holds across all temperatures. Accordingly, a temperature exposure detection system may take into account the time from last programming in order to determine temperature exposure based on measured data retention error rates.

In some embodiments, temperature exposure information may be indicative of the highest temperature that a system is exposed to. In other embodiments, temperature exposure information may indicate a cumulative amount of time of exposure at elevated temperatures. The amount of time that memory cells need to be exposed at a certain temperature for data retention error rates to rise may be a factor in what the temperature exposure information is indicative of. In some embodiments, the cells of cell group A (<NUM>) may be more indicative of a peak temperature in that they are more susceptible to switching where the cells of group E (<NUM>) may be more indicative of a cumulative exposure to extreme temperatures.

With some items being monitored, a short momentary exposure to a very high temperature may not be as harmful as a prolonged exposure at lower temperatures. In some embodiments, it may be desirable to closely match the temperature dependent data retention error rate profiles of the cells of a system with the harmful temperature exposure profile of the products being monitored at least for the valid ranges of data retention error rates.

<FIG> sets forth a calibration routine for setting data retention error rate/ temperature exposure correlation information for a temperature exposure detection system according to one embodiment of the present invention. During the routine, the system is exposed to a range of temperatures, where the data retention error rates are determined after exposure to each temperature by a read of the nonvolatile memory cells of the system.

At operation <NUM>, the test temperature (TESTTEMP) is set to the lowest temperature of the test range. In operation <NUM>, the memory cells of the system are programmed to a predefined set of values, which in one embodiment is all <NUM>, but in other embodiments may be all <NUM> or a pattern of <NUM> and <NUM>. In operation <NUM>, the cells are exposed to the TESTTEMP temperature for a predetermined period of time. Afterwards, the cells are read to determine the data retention error rate for each cell group. In one embodiment, the system reads all the cells of the array and compares the read values to the predefined values (e.g., all <NUM>'s) written in operation <NUM>. The number of incorrect read bits of a cell group is divided by the total number of bits of the cell group to determine an error rate percentage for the cell group at that temperature. In operation <NUM>, if not all of the temperatures of the range have been tested, TESTTEMP is increased to the next temperature in the range in operation <NUM> and operations <NUM>, <NUM> and <NUM> are performed again until all temperatures in the range have been tested. In operation <NUM>, the test results are used to generate data retention error rates/temperature exposure correlation data for storing in a memory (e.g., tables <NUM>) of a temperature exposure determination system.

In some embodiments, routine <NUM> would be performed after manufacturing and prior to sale of the system. In some embodiments, routine <NUM> would be performed on a small subset of manufactured systems where the resultant correlation data would be programmed into the memories of the other manufactured systems. In still other embodiments, initial correlation data would be programmed into the memory (e.g., tables <NUM>) of a system. Afterwards, the system would be calibrated at one temperature, where the measured results at the one temperature would be used to adjust the initial correlation data programmed in the memory. In some embodiments (e.g., that utilize MRAM cells), initial correlation data may be obtained from switching models, where a thermal stability factor of the cells is extracted by extrapolation of off-state conditions, i.e., zero magnetic field, zero current and ambient temperature. In other embodiments, a system may be calibrated in other ways.

<FIG> is a flow chart of a routine <NUM> for determining temperature exposure by a temperature exposure detection system (e.g., <NUM>) as per one embodiment of the present invention. In operation <NUM>, system <NUM> receives a command (e.g., via RF receiver <NUM>) to provide temperature exposure information. In operation <NUM>, determination circuitry <NUM> preforms a read on all of the cells of array <NUM> and determines the data retention error rate for each cell group (<NUM>-<NUM>). In operation <NUM>, determination circuitry <NUM> determines which cell group or groups of cell groups (<NUM>-<NUM>) has a data retention error rate within a valid range (e.g., <NUM>-<NUM>% in <FIG>). In operation <NUM>, determination circuitry <NUM> determines the temperature exposure information from the data retention error rate of the cell group(s) with data in the valid range. In operation <NUM>, the temperature exposure information is provided to the requestor (e.g., controller <NUM> in <FIG>) e.g., via RF receiver <NUM>. In other embodiments, a temperature exposure monitoring system may determine and provide temperature exposure in other ways.

<FIG> is a block diagram showing temperature exposure detection system <NUM> being attached to an item <NUM> being monitored. Item <NUM> can be any product for which it is desirable to determine what temperatures the item has been exposed to. For example, item <NUM> can be batteries, food, beverages, plastics, medicines, vaccines, chemical substances, or electronic equipment or components. For some products, it may be desirable to determine temperatures that an item was exposed to prior to the sale of the item e.g., as when an item is sitting in a warehouse or during transit. Such information can be used in determining whether warranty or product usage conditions were complied with. In other embodiments, the information may be used to determine the conditions that raw materials where subject to for determining whether to alter manufacturing processes. In other embodiments, such information can be used to determine whether a product is nearing end of life or should be replaced.

In one embodiment, system <NUM> is implemented in a tag that is attached to the item or package container. In other embodiments, system <NUM> may be part of the electronics of item <NUM>. In still other embodiments, system <NUM> would be integrated with the package container such as enclosed within a liquid container.

Controller <NUM> is used to program system <NUM> to begin monitoring temperature exposure, to request temperature exposure information regarding the item, and to reset system <NUM> to begin monitoring for a second period. In the embodiment shown, controller <NUM> exchanges information with system <NUM> wirelessly, although in other embodiments, that information may be exchanged via a wired communication link (not shown). Controller <NUM> may be a portable device such as a handheld inventory scanner, laptop, or cell phone or it may a stationary device such as a scanner, manufacturing tool, or desktop computer. In some embodiments, different devices may be used to program, read, and reset system <NUM>. In some embodiments, the some of the determination operations may be performed by controller <NUM>. In some embodiments, the different nonvolatile memory cell groups may be located in different integrated circuits of a temperature exposure detection system.

In some embodiments, because system <NUM> utilizes nonvolatile memory cells to determine temperature exposure of an item, system <NUM> can monitor temperature exposure even when not powered up. Accordingly, such a system can monitor temperature for items when they are not powered or for items that are not configured to be powered (e.g., food, liquids). Also, because the memory cells are reprogrammable, a system can be reused to monitor multiple items. For example, system <NUM> can be incorporated into a barrel and can be reset to monitor temperature each time the barrel is filled.

Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

In one embodiment, a temperature exposure detection system includes a plurality of nonvolatile memory cells, read circuitry for reading the plurality of nonvolatile memory cells, and determination circuity that determines a data retention error rate of the plurality of nonvolatile memory cells based on a read of the plurality of nonvolatile memory cells and determines temperature exposure of the system based on the determined data retention error rate of at least some of the plurality of nonvolatile memory cells.

Claim 1:
A temperature exposure detection system (<NUM>) comprising:
a plurality of nonvolatile memory cells (<NUM>);
read circuitry (<NUM>) for reading the plurality of nonvolatile memory cells (<NUM>);
characterized in that the system (<NUM>) further comprises determination circuity (<NUM>) that is configured to determine a data retention error rate of the plurality of nonvolatile memory cells (<NUM>) based on a read of the plurality of nonvolatile memory cells (<NUM>) and is configured to determine temperature exposure of the system (<NUM>) based on the determined data retention error rate of at least some of the plurality of nonvolatile memory cells (<NUM>).