Patent Description:
A computing device may include multiple subsystems that communicate with one another via high-speed data communication interfaces or links. The communicating subsystems may be included within the same integrated circuit chip or in different chips. A "system-on-a-chip" or "SoC" is an example of one such chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as central processing units ("CPU"s), graphics processing units ("GPU"s), digital signal processors ("DSP"s), and neural processing units ("NPU"s). An SoC may include other subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity. An SoC may be coupled to one or more memory chips via a data communication link. High-speed, synchronous types of memory, such as double data-rate synchronous dynamic random access memory ("DDR-SDRAM") require precise timing between data and clock signals to maintain reliability. Noise and other environmental stressors may adversely affect these signals.

A data eye is a representation of the data signal on a communication link in the form of a voltage versus time plot, such as may be produced by a high-speed oscilloscope. The term data eye refers to the shape of the characteristic opening or region in which minimal data signal transitions occur. Communication link stability is maximized when the clock edge is aligned with the center of the data eye. Noise and other environmental stressors may distort the data eye. For this reason, techniques have been developed by which a data link is periodically trained to re-align the clock edge with the center of the data eye. Data link training may not result in improved performance if the eye has become severely distorted. Also, data link training is not generally used to determine whether a data link has become so impaired that other actions, such as maintenance, may need to be taken to avert failures. Attention is drawn to document <CIT>. It describes an analyzer for monitoring a configuration of a wired network medium that is used for communication between multiple devices. The configuration change includes an additional device tapping to the medium for eavesdropping, or the substituting one of the devices. The analyzer is connected to the medium for receiving, storing, and analyzing waveforms of the physical-layer signals propagated over the medium. The analysis includes comparing the received signals to reference signals, and notifying upon detecting a difference according to pre-set criteria. The analysis may be time or frequency-domain based, and may use a feed-forward Artificial Neural Network (ANN). The wired network may be an automotive or in-vehicle network, PAN, LAN, MAN, or WAN, may use balanced or unbalanced signaling, and may be configured as point-to- point or multi-point topology. The analyzer may be connected at an end of the medium, and may be integrated with one of the devices.

In accordance with the present invention, a method and a system, as set forth in the independent claims is provided. Embodiments of the invention are defined in the dependent claims,
Systems, methods, computer program products, and other embodiments are disclosed for detecting and otherwise maintaining reliability of a data communication link in a computing device.

" The word "illustrative" may be used herein synonymously with "exemplary.

As shown in <FIG>, in an illustrative or exemplary embodiment, a computing device <NUM> may include a processor subsystem <NUM> and a memory subsystem <NUM> coupled together via a bidirectional data communication link <NUM>. The data communication link <NUM> may comprise any number of signal lines, configured to convey data signals, clock signals, etc. The systems, methods and computer program products described in this disclosure may be employed to evaluate and otherwise maintain the reliability of the data communication link <NUM>. It should be understood that although in the exemplary embodiments described in this disclosure the data communication link <NUM> is between a processor subsystem <NUM> and a memory subsystem <NUM> and configured to convey memory traffic, in other embodiments such a data communication link may be between any other types of computing device subsystems and may be configured to communicate (i.e., transmit and receive) any other type of data traffic. For example, in such other embodiments the data communication link may be a Peripheral Component Interconnect express ("PCIe") bus, a Universal Serial Bus ("USB"), or any other type of interface or data communication link that is not inconsistent with the principles described in this disclosure. In the exemplary embodiment shown in <FIG>, the data communication link may be between separate chips, such as between an SoC that includes a first subsystem (e.g., the processor subsystem <NUM>) and a chip that includes a second subsystem (e.g., the memory subsystem <NUM>). In other embodiments (not shown), the data communication link may be between first and second subsystems (e.g., the processor subsystem <NUM> and the memory subsystem <NUM>) included within the same chip. In still other embodiments (not shown), the data communication link may be between chiplets.

In the exemplary embodiment shown in <FIG>, the memory subsystem <NUM> may comprise, for example, a double data-rate synchronous dynamic random access memory ("DDR-SDRAM") chip. The processor subsystem <NUM> may comprise, for example, a system-on-a-chip ("SoC"). The processor subsystem <NUM> may include a controllable communication link interface <NUM> that can be configured to adjust aspects of operation of the data communication link <NUM> that affect link quality, such as relative timing between clock and data signals being conveyed on the data communication link <NUM>.

An application task <NUM> may execute on a processor (not separately shown) of the processor subsystem <NUM>. The application task <NUM> (i.e., processor structures as configured by software in execution) may be any task, process, thread, etc., that communicates a data stream via the data communication link <NUM> with the memory subsystem <NUM>. In the exemplary embodiment shown in <FIG>, the data stream comprises memory traffic (i.e., write transactions, read transactions, etc.). The memory traffic is communicated via the communication link interface <NUM>.

A convolutional neural network ("CNN")-based controller <NUM> also may execute on a processor (not separately shown) of the processor subsystem <NUM>. The CNN-based controller <NUM> is coupled to the communication link interface <NUM>. Through the communication link interface <NUM>, the CNN-based controller <NUM> may monitor the data stream being communicated between the application task <NUM> and the memory subsystem <NUM>. The CNN-based controller <NUM> may also be configured to control aspects of the controllable communication link interface <NUM>, such as relative timing between clock and data signals being conveyed on the data communication link <NUM>. The CNN-based controller <NUM> may further be configured to initiate write and read transactions with the memory subsystem <NUM>.

As shown in <FIG>, a data eye <NUM> is defined or characterized by transitions of a data signal <NUM>. Within the data eye <NUM>, i.e., bounded by successive transitions of the data signal <NUM>, the bit value may be high ("<NUM>") or low ("<NUM>"). A data stream may consist of many successive bits, transmitted at a bit rate of the data communication link <NUM> (<FIG>), and the data eye <NUM> may represent a composite of such successive bits. To properly sample or capture data transmitted on a signal line (i.e., one bit) of the data communication link <NUM> (<FIG>), the edge <NUM> of the clock signal (RX Clock) must be properly aligned in time with the data eye <NUM>, such as, for example, in the center of the data eye <NUM> at a time <NUM>, where the data eye <NUM> spans an interval between a time <NUM> and a time <NUM>. The term "clock-data timing" is used in this disclosure to refer to the time at which the edge <NUM> of the clock signal occurs within the data eye, i.e., in the interval between time <NUM> and time <NUM>. In a manner described below, the clock-data timing may be adjusted or set to any value in the range of time <NUM> to time <NUM> by delaying either the clock signal or the data signal with respect to the other, so that the edge <NUM> occurs earlier or later in time with respect to the data eye <NUM>, as conceptually indicated by the arrows in <FIG>. The communication link interface <NUM> (<FIG>) may be controllable to adjust this clock-data timing.

In <FIG>, an oscilloscope image <NUM> shows a data eye in a two-dimensional ("<NUM>-D") space defined by a time axis and an amplitude or voltage ("V") axis. As well understood by one of ordinary skill in the art, the image <NUM> may be obtained by repetitively sampling a single data (bit) line of the data communication link <NUM> (<FIG>) synchronously with the bit rate. In contrast with the conceptual depiction of the data eye <NUM> (<FIG>), in which the data signal <NUM> is depicted by well-defined lines, the data eye in the image <NUM> is further characterized by variations or fluctuations in the oscilloscope signal trace over many successive bits. In the image <NUM>, a region is white where the signal trace occurs more frequently and black where the signal trace occurs less frequently. While the image <NUM> is rendered in <FIG> in monochrome for clarity, similar data eye images are commonly rendered in color, with different colors representing different frequencies or densities of signal trace occurrence. Regardless of how a signal trace may be rendered, a region in which the signal trace occurs less frequently than in the surrounding regions may define the data eye, i.e., a region in which the bit value is most stable. Nevertheless, it may be noted that the frequency or density of occurrence of the signal trace follows somewhat of a gradient, with a minimum at the center of the data eye and generally increasing with distance from the center. A large data eye, i.e., a central region in which the signal trace frequency is low over a large, well-defined region, indicates that the data value is stable over a large region. Such a data eye may be referred to as a higher-quality data eye. A higher-quality data eye yields more accurate data value samples using a clock signal (not shown in <FIG>) because the clock edge more frequently occurs during a time when the data value is stable. A data eye that is smaller or less symmetrical generally yields less accurate data value sampling using a clock signal and may be referred to as a lower-quality data eye relative to the aforementioned higher-quality data eye. One of ordinary skill in the art is readily capable of judging data eye quality among two or more data eyes and of ranking the data eyes in quality relative to each other. Unless otherwise stated, the terms "higher" quality and "lower" quality are used in this disclosure to describe data eyes in a data set relative to each other and not relative to other criteria.

In <FIG>, an oscilloscope image <NUM> shows a data eye that is lower quality than the data eye shown in the oscilloscope image <NUM> (<FIG>). Such a lower-quality data eye may occur when a data line experiences electromagnetic noise or other environmental stressors. The data eye in the image <NUM> is therefore less conducive to accurate sampling using a clock signal.

As shown in <FIG>, a <NUM>-D array <NUM> represents an example of a data eye formed using information that quantitatively characterizes how well the data eye is likely to yield accurate data value sampling using a clock signal (not shown). The array <NUM> may also be referred to as a "functional" data eye to distinguish it from a traditional, oscilloscope-generated data eye (image) of the type described above with regard to <FIG>.

The data points that the array <NUM> comprises are indexed by clock-data timing on the horizontal axis and reference voltage ("Vref") on the vertical axis. The reference voltage is a threshold that determines whether a data capture buffer (not shown) samples or captures a value of "<NUM>" or "<NUM>. " That is, a value of "<NUM>" is captured when the data signal voltage is above the reference voltage when the clock edge occurs, and a value of "<NUM>" is captured when the data signal voltage is below the reference voltage when the clock edge occurs. The value or number at each point in the array <NUM> is indicative of the stability of the data signal. (The numerical values and their pattern shown in <FIG> are intended only as examples. ) For example, the value represents a count of the number of times that a sampled bit value failed to match an expected bit value. In the example shown in <FIG>, a value of zero represents a point of maximum data stability and therefore a point within the region defining the data eye. The data eye may generally be defined by a pattern in which a large, contiguous region of data points having low values, such as zero, is surrounded by data points having higher values, generally increasing with distance from a center of the data eye. (Values in the array <NUM> represented by a hash symbol ("#") represent numerical values greater than a threshold and may be omitted from the data eye analysis described herein.

It is known in the art to form a functional data eye (e.g., the array <NUM>) by operating a data communication link while sweeping both the reference voltage and clock-data timing over their respective ranges. For example, the clock-data timing may be initialized to a predetermined minimum (e.g., one end of the range described above with regard to <FIG>) and then incremented in steps until a predetermined maximum (e.g., the other end of the range) is reached. At each step of the clock-data timing, the reference voltage may similarly be initialized to a predetermined minimum and then incremented in steps until a predetermined maximum is reached. When the maximum reference voltage is reached, the clock-data timing may again be incremented. Under operating conditions of each unique combination of clock-data timing and reference voltage, sampled data may be compared with expected data. For example, a test data value may be written to a memory and then read back from the memory over a data communication link. A mis-match between a bit that was written and a bit that was read back may be attributed to diminished signal quality, under a presumption that the memory system is otherwise operating properly (which, as understood by one of ordinary skill in the art, can be analyzed in other ways not related to the present disclosure). Sampled data is compared with expected data in this manner a number of times under operating conditions of each unique combination of clock-data timing and reference voltage. Each time such a mis-match or failure is detected, the count is incremented. Any number of arrays <NUM> may be formed in this manner. The arrays <NUM> may be displayed (e.g., rendered in the graphical manner depicted in <FIG>) for visual inspection by engineers or other persons. It is known for such persons to judge data eye quality using such functional data eyes.

As shown in <FIG>, an SoC <NUM> may communicate with a memory chip <NUM> via a data communication link <NUM>. The SoC <NUM> may include a CPU <NUM> (also sometimes referred to as an application processor), a memory controller <NUM>, a power manager or controller <NUM>, and other elements (not shown for purposes of clarity). The CPU <NUM>, the memory controller <NUM>, and the memory chip <NUM> may examples of the processor subsystem <NUM>, the interface <NUM>, and the memory subsystem <NUM>, respectively, described above with regard to <FIG>. An internal data communication bus <NUM> may couple the CPU <NUM> with the memory controller <NUM> and power controller <NUM>. Although the power controller <NUM> is included in the SoC <NUM> in the illustrated embodiment, in other embodiments such a power manager or controller may be a separate chip. Although the power controller <NUM> may serve a number of functions, including controlling a number of different power supply rails provided to different subsystems, for purposes of the present disclosure it is sufficient to note that the power controller <NUM> provides the reference voltage (i.e., Vref) to the memory controller <NUM>, and that the power controller <NUM> may adjust the reference voltage in response to instructions provided by the CPU <NUM>.

As the data communication link <NUM> is external to the SoC, such as, for example, on a printed circuit board or flex circuit (not shown), it is more susceptible to the adverse effects of noise than, for example, the internal data communication bus <NUM>. The memory chip <NUM> may be a high-speed synchronous type, such as, for example DDR-SDRAM. Accordingly, the data communication link <NUM> may comprise a number of data signal lines ("DQ_0"-"DQ_N") that convey data signals, and a clock signal (also referred to as data strobe) line ("DQS") that conveys a clock signal. Each data signal line corresponds to one bit of a data word that may be written to or read back from the memory chip <NUM>.

The memory controller <NUM> may include memory control logic <NUM>, data buffers <NUM>, and a clock delay control ("CDC") circuit or controller <NUM>. Although not shown for purposes of clarity, the CDC controller <NUM> may receive a system clock signal, which may be the same frequency as the clock signal under which the CPU <NUM> operates. The CDC controller <NUM> provides a controllable delay that, in the illustrated embodiment, delays the system clock signal or a data strobe signal ("DQS") relative to the data signals by an amount determined by the memory control logic <NUM> or by instructions provided to the memory controller <NUM> by the CPU <NUM>. The delayed clock signal may be referred to as a receive data capture clock ("RX_CLK") signal. In other embodiments, a similar delay controller (not shown) may delay the data signals relative to a clock signal. The term "clock-data timing" refers to the delay or amount by which the clock signal leads or lags a data signal regardless of whether the controller delays the clock signal relative to the data signal or delays the data signal relative to the clock signal. The clock-data timing may sometimes be referred to as "CDC" for brevity.

The data buffers <NUM> temporarily store or buffer data values that are the subject of write or read transactions initiated by the CPU <NUM>. For example, the data buffers <NUM> may be triggered by an edge of the data capture clock to capture a data value provided by the memory chip <NUM> in response to a read transaction. If the edge of the data capture clock always occurs at a time when a data signal has an amplitude substantially greater than or substantially less than the reference voltage, then the data buffers <NUM> will capture the correct data values. However, if the edge of the data capture clock occurs at a time when a data signal has an amplitude approximately equal to the reference voltage (as represented by a distorted data eye), then the data buffers <NUM> may capture erroneous data values. The more distorted the data eye, the higher the probability of the data buffers <NUM> capturing erroneous data values. As described above, the clock-data timing may be adjusted by the CPU <NUM> via the memory controller <NUM>. The reference voltage similarly may be adjusted by the CPU <NUM> via the power controller <NUM>.

As conceptually illustrated in <FIG>, a method <NUM> involves employing a convolutional neural network ("CNN") <NUM> to analyze the above-described <NUM>-D array <NUM> (<FIG>). The CNN <NUM> outputs a score <NUM> that indicates the stability of the data eye (signal) corresponding to the <NUM>-D array <NUM>. The score may be within a numerical range, such as, for example, <NUM> to <NUM>. Unlike in the conventional method of persons judging data eye quality based on functional data eyes, the CNN <NUM> of the present disclosure need not be explicitly provided with patterns or features identified as being relevant to data eye quality. Rather, through neural network training, the CNN <NUM> learns to identify such relevant features.

As shown in <FIG>, a CNN-based controller <NUM> may include a control system <NUM> and a CNN <NUM>. The CNN-based controller <NUM> may be an example of the CNN-based controller <NUM> (<FIG>), and the CNN <NUM> may be an example of the CNN <NUM> (<FIG>). The control system <NUM> and CNN <NUM> may execute on one or more processors, such as, for example, the CPU <NUM> described above with regard to <FIG>, or any processor of the processor subsystem <NUM> described above with regard to <FIG>, etc. The control system <NUM> may include a functional data eye collector <NUM> and a result evaluator <NUM>.

The functional data eye collector <NUM> may collect functional data eyes <NUM> as described above with regard to <FIG>. Accordingly, the functional data eye collector <NUM> may communicate information with, for example, the memory controller <NUM> described above with regard to <FIG>. For example, the functional data eye collector <NUM> may send clock-data timing and reference voltage instructions to the memory controller <NUM>, which may respond by adjusting the clock-data timing and reference voltage. The functional data eye collector <NUM> may also initiate memory transactions (e.g., write and read transactions) to which the memory controller <NUM> may respond by writing data values to or reading data values from the memory chip <NUM>.

The functional data eye collector <NUM> may provide a functional data eye <NUM> as a gray-scale image input to the CNN <NUM>. The CNN <NUM> may be trained and otherwise configured in the manner described below to recognize features in the functional data eye <NUM> that are relevant to data eye quality, in a manner analogous to that in which conventional neural networks recognize relevant features in photographic images. The CNN <NUM> may generate a score for the data eye <NUM> on, for example, a scale of <NUM> to <NUM>, as described above with regard to <FIG>. The result evaluator <NUM> may receive the score from the CNN <NUM>. Based on the score, the result evaluator <NUM> may initiate an action. For example, the result evaluator <NUM> may issue a human-perceptible alert, such as a message recommending to have the computing device undergo maintenance procedures by service personnel. Alternatively, or in addition, the result evaluator <NUM> may initiate a fail-over, involving switching from an active subsystem to an alternate or back-up subsystem. For example, the result evaluator <NUM> may switch a data stream from being communicated between the memory subsystem <NUM> (<FIG>) and the processor subsystem <NUM> to being communicated between the memory subsystem <NUM> and an alternate subsystem (not shown).

In the following description of the architecture of the CNN <NUM>, a well-known symbology is used to describe the order of the layers. In accordance with this symbology, the arrow symbol "→" points from a layer that outputs information to a layer that receives that information as its input. The layer that outputs information also may be described as preceding or before the layer that receives the information as its input, and the layer that receives the information as its input may be referred to as following or after the layer that outputs the information.

The CNN <NUM> may have the following architecture, for example: INPUT→CONV0(<NUM>×<NUM>×<NUM>)→BATCHNORM→CONV1(<NUM>×<NUM>×<NUM>)→ BATCHNORM→CONV2(<NUM>×<NUM>×<NUM>)→BATCHNORM→FLATTEN→ DENSE(<NUM>)(Dropout0. <NUM>)→DENSE(<NUM>)(Dropout0. <NUM>)→DENSE(<NUM>)→OUTPUT.

The input layer ("INPUT") represents the above-described <NUM>-D array of data points. Three convolutional layers may follow the input layer. As well understood by one of ordinary skill in the art, a convolutional layer extracts features from a source image. The first convolutional layer ("CONV0") may comprise <NUM> filters, each 3x3 in size. The second convolutional layer ("CONV1") may comprise <NUM> filters, each 3x3 in size. The third convolutional layer ("CONV2") may comprise <NUM> filters, each 3x3 in size. As in a conventional neural network that is configured to recognize or classify spatial features, the first, second and third convolutional layers of the CNN <NUM> are configured during training (described below) to extract features from the <NUM>-D array of data points (i.e., the source image) that are characteristic of data eyes.

A first batch normalization layer ("BATCHNORM") may be included between the first and second convolutional layers; a second batch normalization layer may be included between the second and third convolutional layers; and a third batch normalization layer may be included after the third convolutional layer. Batch normalization ensures that the received input has a mean of zero and a standard deviation of one. To increase stability of a neural network, batch normalization normalizes the output of a previous activation layer by subtracting the batch mean and dividing by the batch standard deviation. A flattening layer ("FLATTEN") may be provided following the third batch normalization layer. Flattening transforms a <NUM>-D matrix of features into a vector that can be fed into a fully connected neural network classifier.

Three dense layers ("DENSE"), also sometimes referred to as fully connected layers, may follow the above-described convolutional, batch normalization and flattening layers. The dense layers successively interpret or classify the features. "Fully connected" means that the dense layer feeds all outputs from the layer that precedes the dense layer to all neurons of that dense layer, and each neuron of that dense layer provides one output to the layer that follows the dense layer. The first, second and third dense layers in this example have <NUM>, <NUM> and <NUM> neurons, respectively.

The dense layers include an activation function. In the exemplary embodiment the activation function may be the hyperbolic tangent activation function ("Tanh").

The additional of the "Dropout" function to the dense layers randomly selects neurons to be ignored during the training phase. They are randomly "dropped out. " Thus, the contribution of dropped-out neurons to the activation of downstream neurons is temporally removed on the forward pass, and any weight updates are not applied to the neuron on the backward pass. In this example, each neuron in each of the first and second dense layers is assigned a <NUM> percent probability of being dropped out on each weight update cycle. The output layer classifies the result in the form of a score ranging from <NUM> to <NUM>.

The foregoing architecture description enables one of ordinary skill in the art to implement the CNN <NUM> using, for example, any of a number of commercially available neural network development software packages. Such commercially available software packages commonly include application program interface ("API") functions that correspond to the above-described convolutional, batch normalization, flattening and dense layers. Accordingly, details of the manner in which these layers, the activation function, and other aspects of the CNN <NUM> may operate are not described herein.

As understood by one of ordinary skill in the art, a CNN must be trained before it can be used to classify images or otherwise identify features relevant to image classification. Similarly, a CNN structured as described above with regard to <FIG> must be trained before it can be used in the methods for maintaining the reliability of a data communication link described herein. Nevertheless, for purposes of continuity with the descriptions above regarding how the CNN-based controller <NUM> may be used, exemplary methods for maintaining the reliability of a data communication link are described first, with reference to <FIG> and <FIG>. Then, exemplary training methods are described (<FIG>).

An exemplary method <NUM> for maintaining the reliability of a data communication link is shown in flow diagram form in <FIG>. As indicated by block <NUM>, a <NUM>-D array of data points representing a data eye on the data communication link is collected. As indicated by block <NUM>, a CNN determines a score of the array. As indicated by block <NUM>, the determined score is compared with a threshold. An action is then initiated based on the result of comparing the determined score with the threshold. For example, as indicated by block <NUM> the action may be initiated if it is determined (block <NUM>) that the score is less than the threshold. Examples of actions include issuing an alert, switching to an alternate subsystem (i.e., fail-over), etc. Different actions may be initiated depending on the score.

Collecting the array in accordance with block <NUM> includes monitoring a data stream on the data communication link, as indicated by block <NUM>. The data stream comprises transmitted values, such as data values written to a memory, and received values, such as data values read back from the memory. The data stream is monitored to detect data mis-matches or other failure indications. As described above with regard to <FIG>, a mis-match between a data value that was written to the memory and a corresponding data value that was read back from the memory is counted as a failure and recorded in the array.

Collecting the array in accordance with block <NUM> includes varying (e.g., incrementing in steps) the reference voltage and clock-data timing while monitoring the transmitted and received data values for failures at each unique combination of reference voltage and clock-data timing, as indicated by block <NUM>. For each unique combination of reference voltage and clock-data timing, the number of times a received data value (e.g., read back from memory) does not match a transmitted data value (e.g., written to memory) is counted, as indicated by block <NUM>. The array is formed from the failure counts, as indicated by block <NUM>.

Another exemplary method <NUM> for maintaining the reliability of a data communication link is shown in flow diagram form in <FIG>. The method <NUM> may be an example of the above-described method <NUM>. The method <NUM> may be performed at intervals, such as periodically during the operation of a computing device. The method <NUM> may be performed, for example, during intervals of inactivity or low activity of the data communication link. The method <NUM> may be performed at such intervals while a computing device is otherwise being used for its ordinary or "mission-mode" purposes by a user (e.g., using an autonomous vehicle, drone, etc.). The method <NUM> may be performed under the control of, for example, the above-described CNN-based controller <NUM> (<FIG>) or <NUM> (<FIG>). The data communication link to which the method <NUM> relates may be, for example, the data communication link <NUM> described above with regard to <FIG> or the data communication link described above with regard to <FIG>.

As indicated by block <NUM>, a <NUM>-D array of data points representing a data eye on the data communication link may be collected. As indicated by block <NUM>, collecting the array in accordance with block <NUM> may include initializing the array (e.g., all data points set to zero) and initializing interface-controllable aspects of the data communication link. For example, the clock-data timing and reference voltage may be set to minimum values within their respective ranges. The array may be similar to the array <NUM> described above with regard to <FIG>. As indicated by blocks <NUM> and <NUM>, respectively, collecting the array of data points in accordance with block <NUM> may also include writing a data value to a memory location via the data communication link (under conditions determined by the interface settings for clock-data timing and reference voltage) and reading back a corresponding data value from the memory location via the data communication link (under conditions determined by the interface settings for clock-data timing and reference voltage). As indicated by block <NUM>, collecting the array of data points in accordance with block <NUM> may further include comparing the data value that was written to the memory location with the corresponding data value that was read from the memory location. As each data value may comprise multiple bits, the data values may be compared on a bit-wise basis. The comparison (block <NUM>) may indicate for each bit position whether the comparison (test) result was a failure (i.e., the data bit value that was read back did not match the data bit value that was written) or a pass (i.e., the data bit value that was read back matched the data bit value that was written). If the comparison (block <NUM>) indicates a failure, then the value in the array (i.e., count of the number of failures) is incremented by one, as indicated by block <NUM>. If the comparison (block <NUM>) indicates a pass, then the value in the array is not incremented. Regardless of the comparison result, the test steps described above with regard to block <NUM>-<NUM> may be repeated until it is determined (block <NUM>) that a predetermined number of repetitions or iterations has been reached. That is, for each data point in the array, a predetermined number of tests are performed.

As indicated by block <NUM>, it is determined whether all data points in the array have been obtained. If it is determined (block <NUM>) that all data points in the array have not yet been obtained (i.e., the clock-data timing and reference voltage values have not been swept or varied through the entireties of their respective predetermined ranges from respective minimum values to respective maximum values), then the clock-data timing and/or the reference voltage is incremented, as indicated by block <NUM>. For purposes of clarity, the method <NUM> does not show a nested loop flow structure in which, for example, clock-data timing is incremented in an outer loop and the reference voltage is incremented in an inner loop. Rather, block <NUM> is intended to indicate setting the clock-data timing and reference voltage combination to the next unique combination. Following block <NUM>, the method <NUM> may continue forming the array, beginning as described above with regard to block <NUM>. When it is determined (block <NUM>) that all data points in the array have been obtained, then the method <NUM> may continue in the following manner with regard to block <NUM> (<FIG>).

As indicated by block <NUM>, a CNN may be used to determine a score of the array. The CNN may be, for example, the CNN <NUM> described above with regard to <FIG>. The CNN may be configured to parse the array in a manner similar to which a conventional CNN may be configured to parse a single-channel <NUM>-D gray-scale input image. As a corresponding array may be formed for each data bit signal line of the data communication interface, the CNN may determine a corresponding score for each such array. As indicated by block <NUM>, each determined score may be compared with a threshold. An action may then be initiated based on the result of comparing the determined scores with the threshold. For example, as indicated by block <NUM> the action may be initiated if it is determined (block <NUM>) that any score is less than the threshold. Examples of actions include issuing an alert, switching to an alternate subsystem (i.e., fail-over), etc. Different actions may be initiated depending on the score. Block <NUM> indicates that a delay or time interval may elapse before the method <NUM> is repeated.

The method <NUM> thus may be performed periodically, interspersed with mission-mode operation of the computing device. In the manner described above, the stability of the data communication link may be periodically analyzed during mission-mode operation of the computing device, and an action may be initiated if the link becomes unstable.

As noted above, before the above-described method <NUM> (<FIG>) or <NUM> (<FIG>) is performed, the CNN must be trained. The CNN may be trained by first collecting a training data set comprising a large number of the above-described <NUM>-D arrays of data points. The number of arrays may be, for example, on the order of tens, hundreds, or even thousands. The arrays in the training data set may be collected in the manner described above. Persons experienced in judging the quality of data eyes may then visually inspect a displayed (i.e., graphical) representation of each array in the training data set and assign each array a score that correlates with the person's judgment of the eye quality. For example, each array may be assigned a score in a range from <NUM> to <NUM>, where <NUM> indicates a data eye that the person judges least likely to be accurately sampled (i.e., lowest quality), and <NUM> indicates a data eye that the person judges most likely to be accurately sampled (i.e., highest quality).

Training involves inputting each array in the training data set to the CNN, and back-propagating the resulting model error through the CNN to adjust the node weights in a way that reduces the model error. The "model error" refers to the difference between the CNN-determined score (i.e., the score that the CNN determines in response to an array in the training data set) and the assigned score (i.e., the score that was assigned to that array by a person as described above). Neural networks are commonly trained using an optimization process that requires a loss function to calculate the model error. A neural network development software package of the type described above may include an API feature that enables a loss function to be selected. In the exemplary embodiment described herein, the loss function may be Mean Squared Error ("MSE"). While the MSE loss function is in itself a conventional or well-known neural network loss function, the basic MSE function may be modified in one or more ways in accordance with the present disclosure. For example, instead of a conventional symmetric MSE function, the MSE may be skewed so that a higher MSE multiplier is applied to the base MSE loss when a CNN-determined score deviates from the corresponding assigned score by a greater amount, while a lower MSE multiplier may be applied to the base MSE loss when a CNN-determined score deviates from the corresponding assigned score by a lesser amount. In other words, the MSE loss function may be weighted to apply a higher loss to determined scores higher than corresponding assigned scores by a certain amount and a lower loss to determined scores lower than corresponding assigned scores by the amount. This modified loss function is described in further detail below.

An exemplary method <NUM> for training the CNN is shown in flow diagram form in <FIG>. The first several steps relate to obtaining a training data set comprising a number of <NUM>-D arrays of the type described above. As these steps are similar to the steps described above with regard to <FIG>, they are described only briefly. As indicated by block <NUM>, a <NUM>-D array and the data communication link control settings may be initialized. As indicated by blocks <NUM> and <NUM>, respectively, a data value may be written to a memory location via the data communication link, and a corresponding data value may be read back from the memory location via the data communication link. As indicated by block <NUM>, the data value that was written to the memory location may be compared with the corresponding data value that was read from the memory location. The result of the comparison may indicate either a pass or a failure, as indicated by block <NUM>. If the result of the comparison indicates a failure, then the value in the array (i.e., count of the number of failures) is incremented, as indicated by block <NUM>. If the result of the comparison indicates a pass, then the value in the array is not incremented. Regardless of the comparison result, the steps described above with regard to block <NUM>-<NUM> may be repeated until it is determined (block <NUM>) that enough tests have been performed to provide a data point in the array.

As indicated by block <NUM>, it is determined whether all data points in an array have been obtained. If it is determined (block <NUM>) that all data points in the array have not yet been obtained, then the combination of clock-data timing and reference voltage is set to the next unique combination so as to correspond to the next data point in the array, as indicated by block <NUM>. Following block <NUM>, the method <NUM> may continue forming the array, beginning as described above with regard to block <NUM>. When it is determined (block <NUM>) that all data points in the array have been obtained, then the method <NUM> may proceed with obtaining another array, until a predetermined number of arrays have been obtained for the training data set, as indicated by block <NUM>.

Continuing on <FIG>, the method <NUM> may include displaying a graphical representation or image of each array in the training data set, as indicated by block <NUM>. As indicated by block <NUM>, the method <NUM> may further include assigning a score to each array, based on a person's judgment of the quality of the functional eye depicted in the corresponding displayed image. For example, each array may be assigned a score in a range from <NUM> to <NUM>, where <NUM> indicates a data eye that the person judges least likely to be accurately sampled (i.e., lowest quality), and <NUM> indicates a data eye that the person judges most likely to be accurately sampled (i.e., highest quality).

As indicated by block <NUM>, each array in the training data set may be provided as input to the CNN. In response to each array, the CNN determines a score and a model error. A modified MSE loss function may be applied to the error.

As shown in <FIG>, a calculated base MSE loss may be modified by applying a multiplier value. The MSE loss function or equation that determines the calculated base MSE loss is well known and therefore not shown in <FIG>. In <FIG>, the horizontal axis <NUM> represents the result of applying the model error to the calculated base MSE loss produced by the MSE equation. That is, the calculated base MSE loss may fall anywhere along the horizontal axis <NUM>. This calculated base MSE loss is the basic loss or penalty that conventionally (i.e., in the absence of modification by a multiplier value as described herein), would be applied to the model error before back-propagating the error through the CNN. The vertical axis <NUM> represents the extent to which the calculated base MSE result may be modified by a multiplier value. That is, the vertical axis represents a multiplier value by which the calculated base MSE loss may be multiplied before back-propagating the resulting modified MSE loss. A calculated base MSE loss may be either "optimistic," meaning that the CNN-determined score is higher than the person-assigned score, or "pessimistic," meaning that the CNN-determined score is lower than the person-assigned score. Calculated base MSE losses along the horizontal axis <NUM> to the left of the vertical axis <NUM> are pessimistic, and calculated MSE losses along the horizontal axis <NUM> to the right of the vertical axis <NUM> are optimistic.

The MSE loss modification or multiplier function shown in <FIG> uses two windows: an inner window ranging between the CNN-determined score being <NUM>% more pessimistic than the person-assigned score and <NUM>% more optimistic than the person-assigned score, and an outer window ranging between the CNN-determined score being <NUM>% more pessimistic than the person-assigned and <NUM>% more optimistic than the person-assigned score. The MSE loss multiplier function most heavily penalizes deviations between the CNN-determined score and the person-determined score that are outside the outer window, less heavily penalizes deviations between the CNN-determined score and the person-determined score that are between the outer window and the inner window, and least heavily penalizes deviations between the CNN-determined score and the person-determined score that are within the inner window. The modified MSE loss function may also more heavily penalize optimistic deviations than pessimistic deviations of the same magnitude, so as to avoid false positives.

For example, if the CNN-determined score is more than <NUM>% lower than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN. If the CNN-determined score is more than <NUM>% higher than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN. If the CNN-determined score is <NUM>%-<NUM>% lower than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN. If the CNN-determined score is <NUM>%-<NUM>% higher than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN. If the CNN-determined score is less than <NUM>% lower than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN. If the CNN-determined score is less than <NUM>% higher than the assigned score, a multiplier of <NUM> may be applied to the base MSE before back-propagating the error through the CNN.

Threshold criteria may be established for evaluating the accuracy of the trained CNN and thus to evaluate whether further training may be beneficial. For example, the above-described <NUM>% window may be considered a threshold. That is, a CNN-determined score may be considered a pass if it is within <NUM>% of the person-assigned score. The accuracy of the CNN may be quantified as the percentage of passing scores. An accuracy below a threshold, such as, for example, <NUM>%, may indicate that further training may be beneficial. Nevertheless, it should be understood that the threshold criteria described above are only examples, and may be different in other embodiments.

As described above with regard to block <NUM> (<FIG>) and <NUM> (<FIG>), one example of an action that may be initiated in response to a determination that a communication link has become unstable is to switch from an active subsystem to an alternate or back-up subsystem. Switching from one subsystem to an alternate subsystem in response to detection of a failure is sometimes referred to as "fail-over. " Fail-over or fail-safe features may be useful in computing devices used in controlling mission-critical or safety-critical systems, such as autonomous vehicles (e.g., automobiles, drones, etc.), industrial automation, medical devices, etc..

As illustrated in <FIG>, a computing device <NUM> may include a first processor subsystem 102A that is similar to the processor subsystem <NUM> described above with regard to <FIG>, and a second processor subsystem 102B that is similar to the first processor subsystem 102A. A first data communication link 106A couples the first processor subsystem 102A to a memory subsystem <NUM>. A second data communication link 106B couples the second processor subsystem 102B to the memory subsystem <NUM>. Although depicted in a conceptual manner in <FIG>, the first and second data communication links 106A and 106B may be physically distinct or independent from each other.

An application task <NUM> and a first CNN-based controller 112A may execute on one or more processors (not separately shown) of the first processor subsystem 102A and may have access to the data communication link 106A via a first interface 108A. If the first CNN-based controller 112A, operating in the manner described above, determines that the first data communication link 106A has become unstable, the first CNN-based controller 112A may initiate switching the second processor subsystem 102B in place of the first processor subsystem 102A. This switching may include migrating the application task <NUM> from the first processor subsystem 102A to the second processor subsystem 102B. The application task <NUM> thus continues executing on the second processor system 102B and may continue directing data transactions to the memory subsystem <NUM> but via the second data communication link 106B instead of the first data communication link 106A. The switching may also include a second CNN-based controller 112B beginning to execute on the second processor system 102B. The second CNN-based controller 112B may be similar to the first CNN-based controller 112A and may begin monitoring the second data communication link 106B.

As illustrated in <FIG>, exemplary embodiments of systems and methods for maintaining the reliability of a data communication link may be provided in a portable computing device ("PCD") <NUM>, such as a smartphone. The PCD <NUM> may be an example of the computing device <NUM> more generally described above (<FIG>). Nevertheless, portability is only an exemplary, relative characteristic of a computing device in accordance with the present disclosure. It is contemplated that in some embodiments a computing device in accordance with the present disclosure may be portable, while in other embodiments a computing device in accordance with the present disclosure may be less portable and included in mission-critical or safety critical equipment, such as autonomous vehicles, drones, industrial automation, etc..

The PCD <NUM> may include an SoC <NUM>. The SoC <NUM> may include a CPU <NUM>, a GPU <NUM>, a DSP <NUM>, an analog signal processor <NUM>, or other processors. The CPU <NUM> may include multiple cores, such as a first core 1304A, a second core 1304B, etc., through an Nth core 1304N. In some embodiments, the above-described controller <NUM> (<FIG>) may comprise a functional portion of the CPU <NUM> or other processor of the PCD <NUM>.

A display controller <NUM> and a touch-screen controller <NUM> may be coupled to the CPU <NUM>. A touchscreen display <NUM> external to the SoC <NUM> may be coupled to the display controller <NUM> and the touch-screen controller <NUM>. The PCD <NUM> may further include a video decoder <NUM> coupled to the CPU <NUM>. A video amplifier <NUM> may be coupled to the video decoder <NUM> and the touchscreen display <NUM>. A video port <NUM> may be coupled to the video amplifier <NUM>. A universal serial bus ("USB") controller <NUM> may also be coupled to CPU <NUM>, and a USB port <NUM> may be coupled to the USB controller <NUM>. A subscriber identity module ("SIM") card <NUM> may also be coupled to the CPU <NUM>.

Claim 1:
A method (<NUM>) for maintaining reliability of a data communication link (<NUM>) in a computing device, comprising:
collecting (<NUM>), by a control system (<NUM>), a two-dimensional array (<NUM>) of data points representing a data eye (<NUM>) on the data communication link;
determining (<NUM>), by a convolutional neural network, a score of the two-dimensional array of data points;
comparing (<NUM>), by the control system, the determined score with a threshold; and
initiating (<NUM>), by the control system, an action based on a result of comparing the determined score with the threshold, characterized in that collecting the two-dimensional array of data points comprises:
monitoring (<NUM>), by the control system, a data stream comprising a plurality of transmitted data values and a corresponding plurality of received data values on the data communication link;
varying (<NUM>), by the control system, while monitoring the plurality of transmitted data values and corresponding plurality of received data values, a reference voltage and a clock-data time delay of the data communication link relative to one another to provide a plurality of combinations of different reference voltages and different clock-data time delays;
counting (<NUM>), by the control system, a number of times a received data value does not match a corresponding transmitted data value under conditions of each combination of reference voltage and clock-data time delay; and
forming, by the control system, the two-dimensional array of data points (<NUM>), each data point corresponding to the number of times a received data value does not match a corresponding transmitted data value, each data point positioned in the array at a unique combination of reference voltage and clock-data time delay.