Patent Description:
Multitier arrangements of integrated devices, and methods of forming sense/access lines.

Efforts are being directed toward forming multitier arrangements of integrated devices. For instance, a tier comprising memory may be formed over a tier comprising drivers, sense amplifiers, etc. It may be desired to form sense/access lines (e.g., bitlines) which are coupled with memory devices of the upper tier, and which are also coupled with components of the lower tier through interconnects that extend through the upper tier. It would be desirable to develop structures specifically configured to be suitable for such applications, and to develop methods of forming such structures. A device and a method of the prior art are described in <CIT>.

The invention relates to an arrangement according to claim <NUM> and a method according to claim <NUM>.

Some embodiments include multitier architectures in which a memory tier is over a tier comprising CMOS circuitry, and in which components of the memory tier are electrically coupled with the CMOS circuitry through conductive interconnects. In some embodiments, sense/access lines (e.g., bitlines) may extend across the memory cells and the conductive interconnects, and may have different compositional configurations over the memory cells than over the conductive interconnects. In some applications, regions of the sense/access lines which are over and directly against the conductive interconnects will have lower resistance (i.e., higher conductivity) than regions which are over and directly against electrodes of the memory cells. Some embodiments include methods of forming multitier architectures. Example embodiments are described with reference to <FIG>.

Referring to <FIG>, an assembly <NUM> shows an example configuration for coupling a bitline (<NUM>) to memory cells (<NUM>) and a conductive interconnect (<NUM>).

The assembly <NUM> includes a memory array <NUM>, which comprises the memory cells <NUM>. The memory cells <NUM> are supported by wordlines (access lines) <NUM>. The illustrated memory cells <NUM> may be representative of a large number of substantially identical memory cells within the memory array <NUM>; and in some embodiments the memory array <NUM> may comprise hundreds, thousands, millions, hundreds of millions, etc., of the memory cells. The term "substantially identical" means identical to within reasonable tolerances of fabrication and measurement. The illustrated wordlines <NUM> may be representative of a large number of substantially identical wordlines within the memory array.

The wordlines <NUM> comprise conductive material <NUM>. The conductive material <NUM> may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material <NUM> may comprise one or more metals and/or metal-containing compositions; and may, for example, comprise tungsten over tantalum nitride.

Each of the memory cells <NUM> comprises a bottom electrode <NUM>, a top electrode <NUM>, and a programmable material <NUM> between the top and bottom electrodes. The electrodes <NUM> and <NUM> comprise conductive electrode materials <NUM> and <NUM>, respectively. The electrode materials <NUM> and <NUM> may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The electrode materials <NUM> and <NUM> may be the same composition as one another, or may be of different compositions relative to one another. In some example embodiments, the electrode materials <NUM> and <NUM> may comprise, consist essentially of, or consist of one or more of TiSiN (titanium silicon nitride), TiAlN (titanium aluminum nitride), TiN (titanium nitride), WN (tungsten nitride), Ti (titanium), C (carbon) and W (tungsten); where the formulas indicate the components within the listed substances, rather than designating specific stoichiometries of such components.

The bottom electrodes <NUM> are electrically coupled with the wordlines <NUM>, and in the shown embodiment are directly against the wordlines.

The programmable material <NUM> may comprise any suitable composition(s). In some embodiments, the programmable material <NUM> may be an ovonic memory material, and specifically may be a chalcogenide. For instance, the programmable material <NUM> may comprise one or more of germanium (Ge), antimony (Sb), tellurium (Te) and indium (In). In specific embodiments, the programmable material <NUM> may, for example, comprise, consist essentially of, or consist of GeSbTe or InGeTe, where the formulas indicate the components within the listed substances, rather than designating specific stoichiometries of such components. In some embodiments, the memory cells may comprise programmable material configured to be utilized in self-selecting devices; for example, a chalcogenide material may act both as a storage element and as a select device. The chalcogenide may be utilized alone in the self-selecting device, or may be utilized in combination with another composition. Example self-selecting PCM devices (with PCM devices being devices comprising phase change material) are described in <CIT>. ) and<CIT> as the assignee.

The memory cells <NUM> are example memory cells which may be utilized in a memory array. In other embodiments, the memory cells may have other configurations. For instance, <FIG> shows a memory cell 12a having another example configuration. The memory cell includes the electrodes <NUM> and <NUM>, and further includes a third electrode <NUM>. In some embodiments, the electrodes <NUM>, <NUM> and <NUM> may be referred to as a bottom electrode, a middle electrode, and a top electrode, respectively. The electrode <NUM> comprises electrode material <NUM>. Such electrode material may comprise any of the compositions described above relative to the electrode materials <NUM> and <NUM>; and may be the same composition as one or both of the electrode materials <NUM> and <NUM>, or may be compositionally different than at least one of the electrode materials <NUM> and <NUM>.

The ovonic material <NUM> may be referred to as a first ovonic material between the upper electrode <NUM> and the middle electrode <NUM>. A second ovonic material <NUM> is between the lower electrode <NUM> and the middle electrode <NUM>. The second ovonic material <NUM> may be incorporated into an ovonic threshold switch (OTS) of a select device <NUM>. The memory cell 12a may thus comprise the programmable material <NUM> in combination with the select device <NUM>, rather than being in a self-selecting configuration.

The ovonic material <NUM> may comprise any suitable composition(s), and in some embodiments may comprise one or more of the compositions described above as being suitable for the programmable material <NUM>.

Referring again to <FIG>, the wordlines <NUM> may be considered to extend in and out of the page relative to the cross-sectional view. Insulative material <NUM> is between the wordlines, and spaces the wordlines from one another. The insulative material <NUM> also isolates neighboring memory cells <NUM> from one another. The insulative material <NUM> may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

The cross-sectional view of <FIG> shows the memory cells <NUM> arranged to form a first set <NUM> and a second set <NUM>. A coupling region <NUM> is between the first and second sets (<NUM>, <NUM>) of the memory cells.

An insulative material <NUM> extends across the coupling region <NUM>. The insulative material <NUM> may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, consist of silicon dioxide. The insulative material <NUM> may be referred to as an intervening insulative material in some of the applications described herein.

The conductive interconnect <NUM> is within the coupling region <NUM>. The conductive interconnect comprises conductive material <NUM>. The conductive material <NUM> may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The conductive interconnect <NUM> may extend entirely through a tier (i.e., deck, level, etc.) comprising the memory array <NUM>. The conductive interconnect <NUM> may comprise multiple compositions, and may comprise different compositions at various locations throughout the tier. The illustrated portion of the conductive interconnect <NUM> may comprise, consist essentially of, or consist of tungsten in some example embodiments.

The memory cells <NUM> have upper surfaces <NUM> along the upper electrodes <NUM>, and the interconnect <NUM> has an upper surface <NUM>. The illustrated upper surfaces <NUM> are planar. In other embodiments, the upper surfaces <NUM> may have other suitable configurations. The illustrated upper surface <NUM> is dome-shaped. In other embodiments, the upper surface <NUM> may be planar, or may have any other suitable shape.

The bitline (digit line, sense line) <NUM> extends across the first and second sets (<NUM>, <NUM>) of the memory cells <NUM>, and across the conductive interconnect <NUM>; and is electrically coupled with the memory cells <NUM> and the conductive interconnect <NUM>. The bitline comprises a first region <NUM> and a second region <NUM>, with such regions being compositionally different than one another. The composition of the first region <NUM> may be referred to as a first composition, and the composition of the second region <NUM> may be referred to as a second composition.

In the illustrated embodiment, the first region <NUM> comprises two materials <NUM> and <NUM>, and the second region <NUM> only comprises the material <NUM>. In other embodiments, the regions <NUM> and <NUM> may comprise different numbers of materials than are shown in the example embodiment of <FIG>. The illustrated materials <NUM> and <NUM> may be referred to as first and second materials, respectively. In some embodiments, the materials <NUM> and <NUM> may be considered to correspond to first and second layers, respectively; or to a lower layer and an upper layer, respectively.

The first material <NUM> directly contacts the upper surfaces <NUM> of the memory cells. The first material <NUM> does not extend to over the upper surface <NUM> of the conductive interconnect <NUM>, and instead the second material <NUM> directly contacts the upper surface <NUM>.

The conductive interconnect <NUM> has sidewall surfaces <NUM>; and in the illustrated embodiment the first material <NUM> directly contacts such sidewall surfaces. In other embodiments, it may be only the conductive material <NUM> which directly contacts any surfaces of the conductive interconnect <NUM>.

In some embodiments, the material <NUM> may have higher resistivity (i.e., lower conductivity) than the material <NUM>. The combined materials <NUM> and <NUM> may be suitable for utilization as a bitline electrically coupled with the memory cells <NUM>, but it may be desired for the electrical connection to the conductive interconnect <NUM> to only utilize the low-resistivity (high-conductivity) material <NUM>; with the terms "low-resistivity" and "high-conductivity" meaning that the material <NUM> has lower resistivity (lower resistance) and corresponding higher conductivity (higher conductance) than the material <NUM>, rather than meaning low-resistivity or high-conductivity in an absolute sense. The direct coupling of the interconnect <NUM> to the low-resistivity material <NUM> may enable enhanced transfer of signals from the bitline <NUM> to the conductive interconnect <NUM>, which may improve speed and reliability relative to configurations in which the interconnect <NUM> couples to higher-resistivity material.

The conductive materials <NUM> and <NUM> may comprise any suitable composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the first conductive material <NUM> comprises, consists essentially of, or consists of one or more of C (carbon), WSiN (tungsten silicon nitride), WN (tungsten nitride) and TiN (titanium nitride), where the formulas indicate components rather than indicating specific stoichiometries; and the second conductive material <NUM> comprises, consists essentially of, or consists of one or more of Ta (tantalum), Pt (platinum), Cu (copper), W (tungsten) and Pd (palladium).

In some embodiments, the first region <NUM> of the bitline <NUM> may be considered to comprise two or more materials (e.g., the materials <NUM> and <NUM>), and the second region <NUM> of the bitline may be considered to include a subset of the materials of the first region (e.g., comprises only the material <NUM> in the illustrated embodiment).

In some embodiments, the first material <NUM> may comprise a first metal (e.g., tungsten or titanium) in combination with one or more nonmetallic elements (e.g., one or more of silicon, nitrogen, carbon, etc.); and the second material <NUM> may consist of a second metal (e.g., one or more of Ta, Pt, Cu, W and Pd). The second metal of the material <NUM> may be the same as the first metal of the material <NUM>, or may be different than the first metal of the material <NUM>. In some specific applications, the first material <NUM> may consist of WSiN (where the chemical formula indicates constituents rather than a specific stoichiometry), and the second material <NUM> may consist of W.

<FIG> shows a top view of the assembly <NUM>. The view of <FIG> is not to scale relative to the view of <FIG>, and utilizes a different diagrammatic representation of the assembly <NUM> than is utilized in <FIG>. Regardless, the cross-section of <FIG> may be understood to be generally along the line <NUM>-<NUM> of <FIG>.

The coupling region <NUM> comprises a plurality of the conductive interconnects <NUM>. The conductive interconnects are arranged along a row, with such row extending along a direction which would be in and out of the page relative to the plane of the cross-section of <FIG>. The conductive interconnects may be circular-shaped in top-down view (as shown), or may have any other suitable shapes, including, for example, square shapes, rectangular shapes, elliptical shapes, etc..

It is to be understood that even though the cross-section of <FIG> only comprises one of the conductive interconnects <NUM> within the illustrated portion of the coupling region <NUM>, in other embodiments there may be multiple conductive interconnects formed along the cross-section of <FIG>. Accordingly, even though <FIG> shows a single row of the interconnects <NUM> within the coupling region <NUM>, in other embodiments there may be multiple rows of such interconnects arranged in a matrix or other suitable configuration. Also, it is to be understood that the illustrated interconnects <NUM> of <FIG> may be representative of a large number of substantially identical interconnects formed within the coupling region <NUM>. For instance, in some embodiments there may be hundreds, thousands, millions, hundreds of thousands, etc., of the conductive interconnects <NUM> formed within the coupling region <NUM>.

<FIG> shows that a plurality of the bitlines <NUM> extend across the memory array <NUM> and the coupling region <NUM>. Each of the bitlines extends across one of the illustrated conductive interconnects <NUM>. The conductive interconnects <NUM> are shown in dashed-line view in <FIG> to indicate that they are under the bitlines <NUM>. The illustrated bitlines <NUM> may be representative of a large number of substantially identical bitlines associated with the memory array <NUM>. For instance, in some embodiments there may be hundreds, thousands, millions, hundreds of thousands, etc., of the bitlines <NUM> associated with the memory array.

The description of <FIG> indicates that the wordlines <NUM> are under the memory cells <NUM>, and that the bitlines <NUM> are over the memory cells. In other applications, the relative orientation of the wordlines and bitlines may be reversed so that the bitlines are under the memory cells and the wordlines are over the memory cells. The terms "access/sense line," "bitline/wordline," "wordline/bitline" and "sense/access line" may be utilized herein to generically refer to bitlines and wordlines in contexts in which an indicated structure may be either a wordline or a bitline.

The conductive interconnects <NUM> of <FIG> and <FIG> may be utilized to enable circuitry from one tier to be electrically coupled with circuitry of another tier within a multitier stack. For instance, <FIG> shows a multitier stack <NUM> having two tiers <NUM> and <NUM> in a vertical stack. The vertically-stacked arrangement of <FIG> may extend upwardly to include additional tiers. The tiers <NUM> and <NUM> may be considered to be examples of levels that are stacked one atop the other. The levels may be within different semiconductor dies (wafers), or may be within the same semiconductor die. The bottom tier <NUM> may include control circuitry and/or sensing circuitry (e.g., may include wordline drivers, sense amplifiers, etc.; and may include CMOS circuitry, as shown). The upper tier <NUM> may include a memory array, such as, for example, the memory array <NUM> of <FIG> and <FIG>; and may be referred to as a memory tier.

The conductive interconnect <NUM> of <FIG> is illustrated as enabling electrical coupling of circuitry associated with the tier <NUM> to circuitry associated with the tier <NUM>, with such electrical coupling being diagrammatically shown utilizing a dashed arrow <NUM>. In an example embodiment, a sense/access line <NUM> associated with the memory array <NUM> is electrically coupled with circuitry of the tier <NUM> through the conductive interconnect <NUM>. For instance, a bitline associated with the memory array within the tier <NUM> may be coupled with a sense amplifier within the tier <NUM> through the connection <NUM>. As another example, a wordline associated with memory array within the tier <NUM> may be coupled with a wordline driver within the tier <NUM> through the connection <NUM>.

The memory array <NUM> of <FIG> and <FIG> comprises a first series of sense/access lines <NUM> extending along a first direction (in and out of the page relative to the cross-section of <FIG>), and a second series of sense/access lines <NUM> extending along a second direction (along a plane of the cross-section of <FIG>), with the second direction being orthogonal to the first direction. <FIG> shows another diagrammatic top view of the assembly <NUM> of <FIG> and <FIG>; and shows the wordlines <NUM> arranged as a first series of sense/access lines under the memory cells <NUM>, and the bitlines <NUM> arranged as a second series of sense/access lines over the memory cells <NUM>. The memory cells <NUM> are not visible in <FIG>, but are to be understood as being at cross-points where the sense/access lines <NUM> cross the sense/access lines <NUM> (with a dashed arrow diagrammatically illustrating an example cross-point location of a memory cell <NUM>).

The memory array <NUM> of <FIG> and <FIG> may have any suitable configuration. <FIG> schematically illustrates an example configuration of the memory array <NUM>. Such configuration includes the memory cells <NUM> at cross-points where wordlines (WL1-WL4) pass the bitlines (BL1-BL6). Each of the memory cells is uniquely addressed through a combination of one of the wordlines and one of the bitlines.

The configuration of <FIG> and <FIG> may be formed with any suitable processing. Example processing is described with reference to <FIG>.

Referring to <FIG>, a capping material <NUM> is over the first and second sets (<NUM>, <NUM>) of the memory cells <NUM>. The capping material <NUM> may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon nitride. The insulative material <NUM> is provided over the capping material <NUM> and across the coupling region <NUM>. In some embodiments, the insulative material <NUM> may be considered to extend across an intervening region between the sets <NUM>, <NUM> of memory cells <NUM>; with such intervening region corresponding to the coupling region <NUM>. The memory cells <NUM> of <FIG> may be replaced with other memory cells (e.g., memory cells having the configuration of the memory cell 12a of <FIG>) in other embodiments.

Referring to <FIG>, the assembly <NUM> is shown after formation of the conductive interconnect <NUM> within the coupling region <NUM>; and after one or more polishing processes have been utilized to expose the upper surfaces <NUM> of the memory cells <NUM>, and the upper surface <NUM> of the conductive interconnect <NUM>.

The conductive interconnect <NUM> may be formed with any suitable processing. For instance, in some example embodiments a via may be formed to extend through the materials within the coupling region <NUM>, and then suitable conductive material(s) may be provided within the via to form the conductive interconnect <NUM>.

The upper surface <NUM> of the conductive interconnect <NUM> projects above an upper surface <NUM> of the polished material <NUM>. Such may be a natural consequence of polishing (e.g., chemical-mechanical polishing, CMP) due to the relative hardness of the conductive material <NUM> as compared to the silicon dioxide <NUM>. The upper surface <NUM> of the conductive interconnect <NUM> is above the upper surface <NUM> of the insulative material <NUM> by a height H. Such height may be at least about 10Å, at least about 20Å, at least about 50Å, etc..

<FIG> shows a top view of the assembly <NUM> at the processing stage of <FIG> utilizing a diagrammatic illustration analogous to that of <FIG>. The view of <FIG> shows that the conductive interconnect <NUM> of <FIG> may be one of many substantially identical conductive interconnects, with others of the conductive interconnect being formed out of the plane of the cross-section of <FIG>.

Referring to <FIG>, the conductive material <NUM> is formed along an upper surface of the assembly <NUM>. The conductive material <NUM> extends across the memory cells <NUM>, and across the conductive interconnect <NUM>; and directly contacts the upper surfaces <NUM> of the memory cells <NUM>, and the upper surface <NUM> of the conductive interconnect <NUM>.

Referring to <FIG>, the conductive material <NUM> is removed from over the upper surface <NUM> of the conductive interconnect <NUM>, while leaving portions of the conductive material <NUM> remaining over the memory cells <NUM> of the first and second sets <NUM> and <NUM>. The conductive material <NUM> may be removed from over the surface <NUM> with any suitable processing; and in some embodiments is removed with a polishing process (e.g., CMP).

Referring to <FIG>, the conductive material <NUM> is formed over the conductive material <NUM>, and the conductive materials <NUM> and <NUM> are together patterned into a bitline <NUM>. The assembly <NUM> of <FIG> comprises the configuration described above with reference to <FIG>. <FIG> shows a top view of the assembly <NUM> at the processing stage of <FIG> utilizing a diagrammatic illustration analogous to that of <FIG>. The view of <FIG> shows that the bitline <NUM> is one of many substantially identical bitlines which may be fabricated utilizing the processing of <FIG>.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term "integrated circuit" meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

The terms "dielectric" and "insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "insulative" (or "electrically insulative") in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The terms "electrically connected" and "electrically coupled" may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being "on", "adjacent" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on", "directly adjacent" or "directly against" another structure, there are no intervening structures present. The terms "directly under", "directly over", etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as "extending vertically" to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an arrangement having a first tier which includes a first set of memory cells on one side of a coupling region, and a second set of memory cells on an opposing side of the coupling region. A first series of sense/access lines are under the memory cells of the first and second sets, and are electrically connected with the memory cells of the first and second sets. A conductive interconnect is within the coupling region of the memory tier. A sense/access line of a second series extends across the memory cells of the first and second sets, and across the conductive interconnect. The sense/access line of the second series has a first region of a first composition, and has a second region of a second composition. The first region is over the memory cells of the first and second series, and is electrically connected with the memory cells of the first and second series. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. A second tier is vertically offset from the first tier. The second tier includes circuitry which is coupled with the conductive interconnect.

Some embodiments include an arrangement having a memory tier which includes a first set of memory cells on one side of a coupling region, and a second set of memory cells on an opposing side of the coupling region. A first series of sense/access lines are under the memory cells of the first and second sets, and are electrically connected with the memory cells of the first and second sets. A conductive interconnect is within the coupling region of the memory tier. A sense/access line of a second series extends across the memory cells of the first and second sets, and across the conductive interconnect. The sense/access line of the second series has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells of the first and second series and is electrically connected with the memory cells of the first and second series. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier. The additional tier includes CMOS circuitry which is coupled with the conductive interconnect.

Claim 1:
An arrangement, comprising:
a first tier (<NUM>) including a first set (<NUM>) of memory cells (<NUM>) on one side of a coupling region (<NUM>), and a second set (<NUM>) of memory cells (<NUM>) on an opposing side of the coupling region (<NUM>);
a first series of sense/access lines (<NUM>) under the memory cells (<NUM>) of the first and second sets (<NUM>, <NUM>), and electrically connected with the memory cells (<NUM>) of the first and second sets (<NUM>, <NUM>);
a conductive interconnect (<NUM>) within the coupling region (<NUM>) of the first tier;
a sense/access line (<NUM>) of a second series extending across the memory cells (<NUM>) of the first and second sets (<NUM>, <NUM>), and across the conductive interconnect (<NUM>); the sense/access line (<NUM>) of the second series having a first region (<NUM>) comprising a first composition (<NUM>), and having a second region (<NUM>) comprising a second composition (<NUM>) which is different than the first composition (<NUM>); the first region (<NUM>) being over the memory cells (<NUM>) of the first and second sets and being electrically connected with the memory cells (<NUM>) of the first and second sets;
the second region (<NUM>) being over the conductive interconnect (<NUM>) and being electrically coupled with the conductive interconnect (<NUM>) with the first composition (<NUM>) being absent from over at least a portion of the conductive interconnect (<NUM>) with the second composition (<NUM>) being in direct physical contact with an upper surface (<NUM>) of the conductive interconnect (<NUM>); and
a second tier (<NUM>) vertically offset from the first tier; the second tier comprising circuitry which is coupled with the conductive interconnect.