Patent Description:
This disclosure relates generally to bit cells, and more specifically, but not exclusively, to charge sharing compute in memory (CIM) bit cells.

As computing systems become more complex, the computing systems process larger amounts of data during operation. This leads to challenges involving the retrieval and storage of data in storage devices. For example, computing systems use multiple layers of computational nodes, where deeper layers perform computations based on results of computations performed by higher layers. These computations sometimes may rely on the computation of dot-products and absolute difference of vectors, typically computed with multiply and accumulate (MAC) operations performed on the parameters, input data and weights. Because these complex computing system operations may include many such data elements, these data elements are typically stored in a memory separate from processing elements that perform the MAC operations.

The computation of operations within a processor is typically orders of magnitude faster than the transfer of data between the processor and memory resources used to store the data. Placing all the data closer to the processor in caches is prohibitively expensive for the great majority of practical systems due to the need for large data capacities of close proximity caches. Thus, the transfer of data when the data is stored in a memory separate from processing elements becomes a major bottleneck for computing system computations. As the data sets increase in size, the time and power/energy a computing system uses for moving data between separately located memory and processing elements can end up being multiples of the time and power used to actually perform the computations. Thus, there exists the need for computing systems that reduce or avoid transferring data for use in a computing operation.

Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional approaches including the methods, system and apparatus provided hereby.

Attention is drawn to <CIT> describing compute-in memory circuits and techniques. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

Attention is further drawn to <CIT> describing multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.

Further attention is drawn to <CIT> describing a write assist driver circuit that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower.

The following aspects of this summary are for illustrative purposes only.

The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.

In one aspect, a bit cell circuit comprises: a bit cell coupled to a system voltage and a ground; a first signal line coupled to the bit cell; a second signal line coupled to the bit cell; a third signal line coupled to the bit cell; a fourth signal line coupled to the bit cell; a read transistor coupled to a first read signal line, an output of the bit cell, and a first read bit line; and a capacitor coupled to the bit cell output and the system voltage.

In another aspect, a bit cell circuit comprises: a bit cell coupled to a system voltage and a ground; a first signal line coupled to the bit cell; a second signal line coupled to the bit cell; a third signal line coupled to the bit cell; a fourth signal line coupled to the bit cell; a read transistor coupled to a first read signal line, an output of the bit cell, and the ground; and a capacitor coupled to the bit cell output and the read bit line.

In still another aspect, a bit cell circuit comprises: a bit cell coupled to a system voltage and a ground; a first signal line coupled to the bit cell; a second signal line coupled to the bit cell; a third signal line coupled to the bit cell; a fourth signal line coupled to the bit cell; a read transistor coupled to a first read signal line, an output of the bit cell, and a write bit line bar; a write bit line coupled to third signal line and the fourth signal line; and a capacitor coupled to the bit cell output and the read bit line.

In still another aspect, a method for operating a bit cell circuit comprises: resetting the bit cell circuit to an initial state; applying a first voltage signal to a first signal line; applying a second voltage signal to a second signal line; coupling a first read bit line to an output of the bit cell circuit; and sampling a voltage level of the first read bit line.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure, and in which:.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

The exemplary methods, apparatus, and systems disclosed herein mitigate shortcomings of the conventional methods, apparatus, and systems, as well as other previously unidentified needs. For example, a charge sharing Compute In Memory (CIM) (also known as In Memory Compute or Process In Memory) may comprise a complement of an exclusive OR (XNOR) CIM bit cell with an internal capacitor between the XNOR output node and a system voltage. In another example, a charge sharing (also known as switch capacitance based or more generally charge based) CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. In such examples, a CIM circuit may eliminate the need for a dedicated write port for the XNOR bit cell, use the transmission gate for an XNOR CIM bit cell to generate a definite voltage at an internal capacitor that avoids a floating node, and is a smaller cell than conventional XNOR bit cells that uses only <NUM> signal line vertical pins and <NUM> horizontal (read bit line (RBL) & read word line (RWL)) pins. In still another example, a charge sharing CIM may comprise an XNOR CIM bit cell with an internal capacitor between XNOR and read bit line with a separate write bit line and write bit line bar. In this example, a CIM circuit may eliminate SRAM write port BL and BLB and not use 6T SRAM, use a separate write bit line (WBL) and write bit line bar (WBLB - the complement of the write bit line) and write word lines (WWLs) to generate a definite voltage at an internal capacitor that avoids a floating node, and is a smaller cell than conventional XNOR CIM bit cells that uses only <NUM> signal line pins and <NUM> (WBL) horizontal pin, <NUM> (RBL & WBLB) vertical pins.

The exemplary CIM circuits described herein both reduce energy for data movement and increase an effective memory bandwidth for data consumed in computing systems. The exemplary CIM circuits can perform operations such as dot-product and absolute difference of vectors locally stored within an array of memory cells (e.g., bit cells) without having to send data to a host processor. The exemplary CIM circuits may perform MAC operations within a CIM circuit to enable a higher throughput for dot-product operations or weight matrices while still providing higher performance and lower energy compared to continually moving data from memory for inputs in computations by a host processor. The exemplary CIM circuits may include a local memory processor to perform processing to return a computation result instead of merely returning raw or unprocessed data. In some examples, a processor in the CIM circuit computes a MAC value based on a charge or current from selected bit cells of a column of a memory array, the memory array also included in the CIM circuit. It will be noted that the abbreviation "MAC" can refer to multiply-accumulate, multiplication/accumulation, or multiplier accumulator, in general referring to an operation that includes the multiplication of two values, and the accumulation of a sequence of multiplications.

According to some examples, use of a CIM circuit reduces the amount of data that is typically transferred between system memory and compute resources. The reduction in data movement accelerates the execution of algorithms that may be memory bandwidth limited if not for the use of a CIM circuit. The reduction in data movement also reduces overall energy consumption associated with data movement within the computing device. In some examples, processing elements of a CIM circuit may compute a MAC value via use of current summing for one or more columns of bit cells of an array included in the CIM circuit. For these examples, current summing may include doing the following: <NUM>) multiple bit cell pass gates (PGs) simultaneously pulling down a precharged bit line of a column having accessed bit cells; and <NUM>) interpret the final bit line voltage as an analog output value.

There are many useful applications for CIM bit cell arrays including, but not limited to, computer artificial intelligence (AI) that use machine learning such as deep learning techniques. With deep learning, a computing system organized as a neural network computes a statistical likelihood of a match of input data with prior computed data. A neural network refers to a plurality of interconnected processing nodes that enable the analysis of data to compare an input to "trained" data. Trained data refers to computational analysis of properties of known data to develop models to use to compare input data. An example of an application of AI and data training is found in object recognition, where a system analyzes the properties of many (e.g., thousands or more) of images to determine patterns that can be used to perform statistical analysis to identify an input object such as a person's face. Such neural networks may compute "weights" to perform computations on new data (an input data "word") with multiple layers of computational nodes that rely on the MAC operations performed on the input data and weights. For example, CIM bit cell arrays may be used as hardware accelerators for neural networks (e.g., neural processing unit (NPU)).

It should be noted that the terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are "connected" or "coupled" together via the intermediate element. It should also be understood that "coupled" or "connected" as used herein mean electrically coupled or electrically connected unless stated otherwise.

It should be noted that the terms "system voltage" and "ground" refer to voltage states of a circuit. In a circuit coupled to an operating power supply of <NUM> volts, for example, the system voltage (<NUM> volts to <NUM> volts) indicates a "high" logic state while the ground (<NUM> volts to <NUM> volts) indicates a "low" logic state. With regard to system voltage, it should be understood that system voltage as used herein refers to the operating voltage of the bit cell or memory array (sometimes referred to a nominal voltage that a device or system was designed to operate at). For example, a memory bit cell may reside in a system with a processor wherein the memory bit cell has a system voltage (operating voltage) of <NUM> volts while the processor has a system voltage (operating voltage) of <NUM> volts. In this example, it is well understood in the art that the processor signals are voltage reduced when applied to the memory bit cell from a system voltage of <NUM> volts to a system voltage of <NUM> volts. Thus, the system voltage as used herein applies to the system or operating voltage of the memory array or bit cell unless otherwise stated.

<FIG> illustrates an exemplary CIM bit cell array. As shown in <FIG>, a CIM bit cell array <NUM> may include a plurality of bit cells W11-Wnm arranged in an array, a first activation input X1, a second activation input X2, an nth activation input Xn, a first output Y1, a second output Y2, and an mth output Ym. The first activation input X1 is coupled to a first signal line (word line - WL1), the second activation input X2 is coupled to a second signal line (word line - WL2), the nth activation input Xn is coupled to an nth signal line (word line - WLn). The first output Y1 is coupled to a first bit line (BL1) and an analog to digital converter (ADC), the second output Y2 is coupled to a second bit line (BL2) and an ADC, and an mth output Ym is coupled to a mth bit line (BLm) and an ADC.

Each of the bit cells W1 <NUM>-Wnm stores a value corresponding to a weight. An activation signal (Activation (Xn)) is driven by a voltage pulse on respective wordlines (WLn) and multiplication happens at each bit cell (W11-Wnm) and the results are output to the bit lines (BLm). Each bit line (BL1, BL2, BLm) sums up each bit cells' output (each bit cell's output adds voltage to the respective bit line) and passes the result to respective ADC and the ADC converts each BL result to a digital value in accordance with <MAT> The multiplication occurs as a result of a vector-matrix operation. For example, data may be stored in the cell array <NUM> in a column major format such that the most significant bit (MSB) is the topmost first signal line (WL1) and the least significant bit (LSB) is the bottommost nth signal line (WLn) while the rightmost column is the most significant column and the leftmost column is the least significant column. In artificial neural networks, for instance, the matrix elements W11-Wnm correspond to weights, or synapses, between neuron. Each bit cell W11-Wnm may store a value (one or zero) corresponding to a data word for a particular signal line (WL1-Wln). By activating a particular combination of signal lines, a vector-matrix multiplication operation may be performed. Each activated bit cell W11-Wnm that stores a logical "one" will contribute some voltage level (e.g., if the bit cell voltage is <NUM> volt, the bit cell may contribute less than <NUM> volt, such as <NUM> or <NUM> millivolts) to the activated bit cell's respective bit line (BL1-BLm). Each activated bit cell W11-Wnm that stores a logical "zero" will not contribute any voltage potential to the activated bit cell's respective bit line (BL1-BLm). The ADC for each bit line (BL1-BLm) will convert the analog voltage level on the bit line to a digital value as an output of the vector-matrix multiplication operation.

<FIG> illustrates exemplary CIM memory types. As shown in <FIG>, many different types of memory are candidates for a CIM bit cell array. <FIG> illustrates the benefits and drawbacks of four main types of bit cells: Flash memory, phase change memory (PCM), resistive random access memory (RRAM), and charge sharing static random access memory (CS-SRAM). As shown, the storage mechanism for each type of memory is indicated: charge stored in a floating gate (Flash), a GST (GeSbTe - germanium-antimony-tellurium) phase change (PCM), resistance switch of a TMO (transition metal oxide - RRAM), and a CMOS latch. As indicated in the "Accumulation" row, the first three memory types are shown as current accumulation and the fourth is shown as charge accumulation. However, it should be understood that a CS-SRAM may be configured as a charge or current accumulator (See <FIG>, for example). As indicated in the "Process limitation" row, the CS-SRAM has no process limitations on node size and very high MAC energy efficiency along with good parameters in other categories. In addition, as indicated in <FIG>, the CS-SRAM configured as a charge accumulator will scale well in terms of the number of nodes in addition to the lack of process limitations on the size of each node. Thus, with no process limitations on the size of a node as well as the MAC energy efficiency, and multi-bit support without the need for a multi-level layout, the CS-SRAM offers the better performance of the different illustrated memory types.

<FIG> illustrates an exemplary SRAM CIM memory types. As indicated in <FIG>, the CS-SRAM memory type offers benefits over other possible memory types for use in CIM arrays. As shown in <FIG>, an SRAM may be configured as a CIM bit cell array with current accumulation on the bit line or charge accumulation on the bit line. For the current accumulation configuration, the bit cells with a logical "one" contribute current to the respective bit lines and this current is read as the output for that bit line of the array. As indicated in the Sensitivity to process, voltage and temperature (PVT) variation row, the current accumulation configuration is more sensitive to PVT variations that may cause delays in the signal timing under different conditions. For the current accumulation configuration, these variation sources include PVT, Threshold Voltage Mismatch (VtMM), ADC offset, and noise. In contrast, the charge accumulation configuration is subject only to capacitance mismatch between bit cells, ADC offset, and noise variation sources. As indicated in the Energy efficiency and linearity row, the charge accumulation configuration shows better performance than the current accumulation configuration. In addition, the number of nodes or size of the array scales well for the charge accumulation configuration but not for the current accumulation configuration as indicated in the Process node scalability row. Furthermore, the current accumulation configuration has additional challenges such keeping the accumulated current small and critical timing issues while the charge accumulation configuration may have challenges only with data retention. Thus, as can be seen in <FIG>, an SRAM configured to use charge accumulation provides better performance across the various categories (i.e., a CS-SRAM) making an CS-SRAM a good candidate for a CIM bit cell array.

<FIG> illustrates a XNOR bit cell with an internal capacitor between the bit cell and a system voltage in accordance with the invention. As shown in <FIG>, a bit cell circuit <NUM> includes a bit cell <NUM> coupled to a system voltage <NUM> (a logical "one" of <NUM> volts to <NUM> volts, for example) and a ground <NUM> (a logical "zero" of <NUM> volts to <NUM> volts, for example). The bit cell circuit <NUM> also includes a first signal line <NUM> (pre-charge word line 1P, PCWL1P) coupled to the bit cell <NUM>, a second signal line <NUM> (pre-charge word line 2P, PCWL2P) coupled to the bit cell <NUM>, a third signal line <NUM> (pre-charge word line 1N, PCWL1N) coupled to the bit cell <NUM>, a fourth signal line <NUM> (pre-charge word line 2N, PCWL2N) coupled to the bit cell <NUM>, a read transistor <NUM> coupled to a first read word line <NUM>, an output <NUM> of the bit cell <NUM>, a first read bit line <NUM>, and a capacitor <NUM> coupled to the bit cell output <NUM> and the system voltage <NUM>.

As shown in <FIG>, the bit cell <NUM> includes a first transistor <NUM> coupled to the first signal line <NUM>, a second transistor <NUM> coupled to the second signal line <NUM>, a third transistor <NUM> coupled to the third signal line <NUM>, and a fourth transistor <NUM> coupled to the fourth signal line <NUM>. These four transistors are configured to operate as transmission pass gates for the bit cell <NUM>. As is well understood in the art, a transmission pass gate is analog gate similar to a relay that can conduct in both directions or block by a control signal. As shown in <FIG>, the first transistor <NUM> and the second transistor <NUM> pass a strong "<NUM>" but poor "<NUM>", and the third transistor <NUM> and the fourth transistor <NUM> passes a strong "<NUM>" but poor "<NUM>. " As shown in <FIG>, the first transistor <NUM> is a P type transistor, the second transistor <NUM> is a P type transistor, the third transistor <NUM> is an N type transistor, and a fourth transistor <NUM> is an N type transistor.

As shown in <FIG>, the bit cell <NUM> includes a fifth transistor <NUM> (P type), a sixth transistor <NUM> (P type), a seventh transistor <NUM> (N type), and an eighth transistor <NUM> (N type). The bit cell circuit <NUM> is configured as a XNOR logic device with a truth table <NUM> with a first internal node (N1) <NUM> and a second internal node (N2) <NUM>. The bit cell <NUM> may be an SRAM memory cell. Alternatively, the transistors <NUM>-<NUM> may be illustrated as two cross-coupled inverters (See <FIG>, for example). This simple loop creates a bi-stable circuit with a stable state (a logical "<NUM>" or a logical "<NUM>") that does not change over time as is well known in the art.

To read the contents of the bit cell <NUM>, the transistors <NUM>-<NUM> must be turned on/enabled and when the transistors <NUM>-<NUM> receive voltage to their gates from their respective signal lines (i.e., first signal line <NUM>, second signal line <NUM>, third signal line <NUM>, and fourth signal line <NUM>), the transistors <NUM>-<NUM> become conductive and so the value stored get transmitted to the read bit line <NUM>. If the bit cell <NUM> stores a logical "<NUM>", the bit cell output <NUM> will contribute a voltage level to the read bit line <NUM>. If the bit cell <NUM> stores a logical "<NUM>", the bit cell output <NUM> will not contribute a voltage level to the read bit line <NUM>. When multiple bit cells <NUM> are configured in an array (See <FIG>, for example), the read bit line <NUM> will accumulate a voltage contribution from each bit cell <NUM> that stored a logical "<NUM>" and read that accumulated voltage level as an output of the array.

<FIG> illustrates a XNOR bit cell with an internal capacitor between the bit cell and a read bit line in accordance with the invention. As shown in <FIG>, a bit cell circuit <NUM> includes similar elements as the bit cell circuit <NUM> with the exception that the capacitor <NUM> is coupled between the bit cell output <NUM> and the first read bit line <NUM> and the read transistor <NUM> is coupled to the bit cell <NUM>, the first read word line <NUM>. In this configuration within a CIM bit cell array, the first read word line <NUM> on the selected column is turned on to discharge any voltage remaining on internal capacitor <NUM>, P channel transmission gate on left <NUM> or right <NUM> is turned on depends on data <NUM> or <NUM> and desired data state is written into the bit cell <NUM>. In some examples, a write assist may be used to minimize the cell size. This may include an over drive of the first read word line <NUM>, a lower system voltage <NUM>, over driving of the nch PCWL <NUM> or <NUM>. In addition, the capacitor <NUM> may be used for write assistance by first read bit line <NUM> with a first read bit line <NUM> pulse to aid the write operation.

<FIG> illustrates a XNOR CIM bit cell with an internal capacitor between the bit cell and a read bit line and separate write bit line in accordance with the invention. As shown in <FIG>, a bit cell circuit <NUM> includes a bit cell <NUM> coupled to a system voltage <NUM> and a ground <NUM>. The bit cell circuit <NUM> also includes a first signal line <NUM> coupled to the bit cell <NUM>, a second signal line <NUM> coupled to the bit cell <NUM>, a first write signal line <NUM> coupled to the bit cell <NUM>, a fourth write signal line <NUM> coupled to the bit cell <NUM>, a read transistor <NUM> coupled to a first read signal line <NUM>, an output <NUM> of the bit cell <NUM>, a first read bit line <NUM>, and a capacitor <NUM> coupled to the bit cell output <NUM> and the first read bit line <NUM>. The bit cell circuit <NUM> may also include a write bit line <NUM> and a write bit line bar <NUM>. As shown in <FIG>, the bit cell <NUM> includes a first inverter <NUM> cross coupled to a second inverter <NUM>, a first transistor <NUM> coupled to a first signal line <NUM>, a second transistor <NUM> coupled to the second signal line <NUM>, a third transistor <NUM> coupled to the third signal line <NUM>, and a fourth transistor <NUM> coupled to the fourth signal line <NUM>. As shown in <FIG>, the first transistor <NUM> is a P type transistor, the second transistor <NUM> is a P type transistor, the third transistor <NUM> is an N type transistor, and a fourth transistor <NUM> is an N type transistor.

<FIG> illustrates an exemplary charge sharing CIM bit cell array with an internal capacitor between the bit cell and a system voltage in accordance with some examples of the disclosure. As shown in <FIG>, a bit cell circuit <NUM> may include a first bit cell <NUM> (e.g., bit cell <NUM>), a second bit cell <NUM> (e.g., bit cell <NUM>), and a third bit cell <NUM> (e.g., bit cell <NUM>) arranged in an array. The outputs from each bit cell <NUM>-<NUM> may be read on the first read bit line <NUM>, then summed and converted to a digital signal by a first ADC <NUM>. As shown, a popcount accumulation may include charge sharing across the first read bit line <NUM> and the first ADC <NUM> readout of the first read bit line <NUM> voltage level. In addition, both transmission gates of each bit cell may be turned off to reduce leakage in a standby mode. In this configuration within a CIM bit cell array, the CIM bit cell rows may be read simultaneously and written one row at a time (instead of one row at a time in typical SRAM). For example, one row is defined by PCWL1P to PCWL1N, and a second row is defined by PCWL2P to PCWL2N, etc..

<FIG> illustrates an exemplary charge sharing CIM bit cell array with an internal capacitor between the bit cell and a read bit line in accordance with some examples of the disclosure. As shown in <FIG>, a bit cell circuit <NUM> may include a first bit cell <NUM> (e.g., bit cell <NUM>), a second bit cell <NUM> (e.g., bit cell <NUM>), and a third bit cell <NUM> (e.g., bit cell <NUM>) arranged in an array. The outputs from each bit cell <NUM>-<NUM> may be read on the first read bit line <NUM>, then summed and converted to a digital signal by a first ADC <NUM>. In addition, a reset switch <NUM> coupled to the ground <NUM> may be included to reset the bit cell circuit <NUM>. As shown, another way to implement a MAC operation may include resetting the first read bit line <NUM> and each cell node to ground while the transmission gates remain off. The activation input drives PCWL N/P respectively in a XNOR operation and the bit cell output becomes either the system voltage or ground as a result while the first read bit line <NUM> voltage will be readout by the first ADC <NUM>.

As shown in <FIG>, a timing diagram <NUM> illustrates a CIM cycle <NUM> of the bit cell circuit <NUM>. In an initial reset phase <NUM>, the reset switch <NUM> is activated to reset the read bit line <NUM> to an initial state (e.g., ground) with the read word line <NUM> transitioning to a logical high (i.e., activate or turn on) and read bit line <NUM> transitioning to a logical low (i.e., coupled to ground) as shown. This is followed by a MAC operation phase <NUM>. As shown in the example timing diagraph <NUM>, a first signal line <NUM> (i.e., PCWL1P) is turned on to transition to a logical low state and a second signal line <NUM> (i.e., PCWL1N) is turned on to transition to a logical high state. After the first signal line <NUM> and the second signal line <NUM> are turned on, the output <NUM> of the bit cell <NUM> is coupled to the read bit line <NUM> (shown as a logical "<NUM>") to increase the voltage level on the read bit line <NUM>. The first ADC <NUM> may then be sampled to read the value of the MAC operation. The voltage signals applied to the signal lines, such as the first signal line <NUM> and the second signal line <NUM> in this example, may be configured to correspond to an input state of that signal line to generate a bit cell output in accordance with the MAC operation desired. See, for example, the truth table of <FIG> where the combination of voltage signals of a logical "<NUM>" or "<NUM>" result in an XNOR output of the bit cell.

With regard to sampling a voltage at the ADC, this refers to an instantaneous voltage reading or signal value at the ADC. An ADC converts a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal. The conversion involves quantization of the input, so it necessarily introduces a small amount of error or noise. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input, limiting the allowable bandwidth of the input signal. The performance of an ADC is primarily characterized by its bandwidth and signal-to-noise ratio (SNR). The bandwidth of an ADC is characterized primarily by its sampling rate. The SNR of an ADC is influenced by many factors, including the resolution, linearity and accuracy (how well the quantization levels match the true analog signal), aliasing and jitter. ADCs are chosen to match the bandwidth and required SNR of the signal to be digitized. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then per the Nyquist-Shannon sampling theorem, perfect reconstruction is possible. The presence of quantization error limits the SNR of even an ideal ADC. However, if the SNR of the ADC exceeds that of the input signal, its effects may be neglected resulting in an essentially perfect digital representation of the analog input signal.

The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying band limited signal can be sampled (in other words, the instantaneous signal values at intervals of time T, the sampling time, are measured and potentially stored) and then the original signal can be reproduced from the discrete-time values by an interpolation formula. The accuracy in this procedure is dictated by the combined effect of sampling and quantization. In the limit of high ADC quantizer resolution, the Shannon-Nyquist sampling theorem implies that a faithful reproduction of the original signal is only possible if the sampling rate is higher than twice the highest frequency of the signal. For a finite quantizer resolution, sampling rates lower than twice the highest frequency usually lead to the optimal digital representation. Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task-in most cases by using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.

<FIG> illustrates a partial method for operating a bit cell circuit in accordance with the invention. As shown in <FIG>, the partial method <NUM> begins in block <NUM> with resetting the bit cell circuit to an initial state. The partial method <NUM> continues in block <NUM> with applying a first voltage signal to a first signal line. The partial method <NUM> continues in block <NUM> with applying a second voltage signal to a second signal line. The partial method <NUM> continues in block <NUM> with coupling a first read bit line to an output of the bit cell circuit. The partial method <NUM> concludes in block <NUM> with sampling a voltage level of the first read bit line.

<FIG> illustrates an exemplary mobile device in accordance with some examples of the disclosure. Referring now to <FIG>, a block diagram of a mobile device that is configured according to exemplary aspects is depicted and generally designated <NUM>. In some aspects, mobile device <NUM> may be configured as a wireless communication device. As shown, mobile device <NUM> includes processor <NUM>, which may be configured to implement the methods described herein in some aspects. Processor <NUM> is shown to comprise instruction pipeline <NUM>, buffer processing unit (BPU) <NUM>, branch instruction queue (BIQ) <NUM>, and throttler <NUM> as is well known in the art. Other well-known details (e.g., counters, entries, confidence fields, weighted sum, comparator, etc.) of these blocks have been omitted from this view of processor <NUM> for the sake of clarity.

Processor <NUM> may be communicatively coupled to memory <NUM> over a link, which may be a die-to-die or chip-to-chip link. Mobile device <NUM> also include display <NUM> and display controller <NUM>, with display controller <NUM> coupled to processor <NUM> and to display <NUM>.

In some aspects, <FIG> may include coder/decoder (CODEC) <NUM> (e.g., an audio and/or voice CODEC) coupled to processor <NUM>; speaker <NUM> and microphone <NUM> coupled to CODEC <NUM>; and wireless controller <NUM> (which may include a modem) coupled to wireless antenna <NUM> and to processor <NUM>.

In a particular aspect, where one or more of the above-mentioned blocks are present, processor <NUM>, display controller <NUM>, memory <NUM>, CODEC <NUM>, and wireless controller <NUM> can be included in a system-in-package or system-on-chip device <NUM>. Input device <NUM> (e.g., physical or virtual keyboard), power supply <NUM> (e.g., battery), display <NUM>, input device <NUM>, speaker <NUM>, microphone <NUM>, wireless antenna <NUM>, and power supply <NUM> may be external to system-on-chip device <NUM> and may be coupled to a component of system-on-chip device <NUM>, such as an interface or a controller.

It should be noted that although <FIG> depicts a mobile device, processor <NUM> and memory <NUM> may also be integrated into a set top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communications device, a mobile phone, or other similar devices.

<FIG> illustrates various electronic devices that may be integrated with any of the aforementioned integrated device, semiconductor device, integrated circuit, die, interposer, package or package-on-package (PoP) in accordance with some examples of the disclosure. For example, a mobile phone device <NUM>, a laptop computer device <NUM>, and a fixed location terminal device <NUM> may include an integrated device <NUM> as described herein. The integrated device <NUM> may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, package-on-package devices described herein. The devices <NUM>, <NUM>, <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also feature the integrated device <NUM> including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

It will be appreciated that various aspects disclosed herein can be described as functional equivalents to the structures, materials and/or devices described and/or recognized by those skilled in the art. It should furthermore be noted that methods, systems, and apparatus disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective actions of this method. For example, in one aspect, an apparatus may comprise a semiconductor means (see, e.g., <NUM> in <FIG>), a means for encapsulating, or an encapsulant means (see, e.g., <NUM> in <FIG>), disposed around the semiconductor means, wherein a backside surface of the semiconductor means is exposed. Such an apparatus may further include a means for conducting (e.g., conductive layer <NUM>) coupled to the semiconductor means, the means for conducting comprising a plurality of conductive pillar bumps, wherein a bump density of the plurality of conductive pillar bumps is greater than <NUM>%. The means for encapsulating, or encapsulant means, may be further disposed between the plurality of conductive bumps using a MUF process. It will be appreciated that the aforementioned aspects are merely provided as examples and the various aspects claimed are not limited to the specific references and/or illustrations cited as examples.

One or more of the components, processes, features, and/or functions illustrated in <FIG> may be rearranged and/or combined into a single component, process, feature or function or incorporated in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted that <FIG> and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, <FIG> and its corresponding description may be used to manufacture, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.

" Any details described herein as "exemplary" is not to be construed as advantageous over other examples. Likewise, the term "examples" does not mean that all examples include the discussed feature, advantage or mode of operation. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.

The terminology used herein is for the purpose of describing particular examples and is not intended to be limiting of examples of the disclosure. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, integers, actions, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, actions, operations, elements, components, and/or groups thereof.

Any reference herein to an element using a designation such as "first," "second," and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements can comprise one or more elements.

Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques.

The methods, sequences and/or algorithms described in connection with the examples disclosed herein may be incorporated directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art including non-transitory types of memory or storage mediums.

Although some aspects have been described in connection with a device, it goes without saying that these aspects also constitute a description of the corresponding method, and so a block or a component of a device should also be understood as a corresponding method action or as a feature of a method action. Analogously thereto, aspects described in connection with or as a method action also constitute a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method actions can be performed by a hardware apparatus (or using a hardware apparatus), such as, for example, a microprocessor, a programmable computer or an electronic circuit. In some examples, some or a plurality of the most important method actions can be performed by such an apparatus.

In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples have more features than are explicitly mentioned in the respective claim. Rather, the disclosure may include fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that-although a dependent claim can refer in the claims to a specific combination with one or a plurality of claims-other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.

Furthermore, in some examples, an individual action can be subdivided into a plurality of sub-actions or contain a plurality of sub-actions. Such sub-actions can be contained in the disclosure of the individual action and be part of the disclosure of the individual action.

Claim 1:
A XNOR compute in memory, CIM, bit cell circuit (<NUM>) comprising:
a static random access memory, SRAM, bit cell (<NUM>) coupled to a system voltage (<NUM>) and a ground (<NUM>);
a first signal line (<NUM>) coupled to the SRAM bit cell;
a second signal line (<NUM>) coupled to the SRAM bit cell;
a third signal line (<NUM>) coupled to the SRAM bit cell;
a fourth signal line (<NUM>) coupled to the SRAM bit cell;
a read transistor (<NUM>) coupled to a first read signal line, an output (<NUM>) of the SRAM bit cell, and a first read bit line;
a capacitor (<NUM>) coupled to the SRAM bit cell output and the system voltage;
wherein the SRAM bit cell comprises a first transistor (<NUM>) coupled to the first signal line (<NUM>), a second transistor (<NUM>) coupled to the second signal line (<NUM>), a third transistor (<NUM>) coupled to the third signal line (<NUM>), and a fourth transistor (<NUM>) coupled to the fourth signal line (<NUM>);
wherein the SRAM bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latch function on a data bit; and
wherein the first transistor is a P type transistor, the second transistor is a P type transistor, the third transistor is an N type transistor, and a fourth transistor is an N type transistor.