Patent Description:
Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences.

In many instances, the functions may be enabled by having circuits on different dies or chips communicate with one another. For example, a processor chip may communicate with a memory chip or a sensor chip. Various standards and protocols have been developed to assist in such communication. One popular standard for low-speed communication is the serial peripheral interface (SPI) specification. SPI is widely adopted. Accordingly, improvements to SPI may provide disproportionate impact across a computing device.

An article on inter-integrated circuits (I<NUM>C) on Wikipedia, available online, https://en. org/w/index. php?title=I%C2%B2C&oldid=<NUM>, discloses synchronous, multi-master, multi-slave, packet switched, single-ended communication busses.

An article on serial peripheral interface (SPI) on Wikipedia, available online, https://en. org/w/index. php?title=SeriaI_PeripheraI_Interface&oldid=<NUM><NUM>, discloses synchronous serial communication interface specifications used for short-distance communication, primarily in embedded systems.

Aspects disclosed in the detailed description include systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin. In particular, exemplary aspects contemplate eliminating the chip select pin for host (also referred to as master)-to-single device (also referred to as slave) communication links. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may signal a start or stop condition using the clock line, and the device may send an acknowledgment of the host's signaling through the device-to-host line. Once acknowledgment is made, the host may then signal on the host-to-device line using a protocol such as SPI. Such arrangement obviates the need for a dedicated chip select pin, which may save space on the chip and help reduce the complexity of line routing between chips.

In this regard in one aspect, an integrated circuit (IC) is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to couple to a clock line on an associated bus. The bus interface also includes an input pin configured to couple to an input line on the associated bus. The bus interface also includes an output pin configured to couple to an output line on the associated bus. The IC also includes a control circuit. The control circuit is configured to detect a change on the clock pin. The control circuit is also configured to send an acknowledgment (ACK) on the output pin that the change was detected. The control circuit is also configured to, after sending the ACK, detect a subsequent change on the clock pin. The control circuit is also configured to send a second ACK on the output pin.

In another aspect, an IC is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to couple to a clock line on an associated bus. The bus interface also includes an input pin configured to couple to an input line on the associated bus. The bus interface also includes an output pin configured to couple to an output line on the associated bus. The IC also includes a control circuit. The control circuit is configured to hold a clock signal on the clock pin at a logical high. The control circuit is also configured to change the clock signal to a logical low. The control circuit is also configured to receive an ACK on the input pin that the change was detected. The control circuit is also configured to, after receiving the ACK, change the clock signal to the logical high. The control circuit is also configured to receive a second ACK on the input pin.

In another aspect, a method for controlling an SPI bus is disclosed. The method includes detecting a change on a clock pin. The method also includes sending an ACK on an output pin that the change was detected. The method also includes, after sending the ACK, detecting a subsequent change on the clock pin. The method also includes sending a second ACK on the output pin.

In another aspect, a method for controlling an SPI bus is disclosed. The method includes holding a clock signal on a clock pin at a logical high. The method also includes changing the clock signal to a logical low. The method also includes receiving an ACK on an input pin that the change was detected. The method also includes, after receiving the ACK, changing the clock signal to the logical high. The method also includes receiving a second ACK on the input pin.

Aspects disclosed in the detailed description include systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin. In particular, exemplary aspects, contemplate eliminating the chip select pin for host (also referred to as master)-to-single device (also referred to as slave) communication links. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may signal a start or stop condition using the clock line and the device may send an acknowledgment of the host's signaling through the device-to-host line. Once acknowledgment is made, the host may then signal on the host-to-device line using a protocol such as SPI. Such arrangement obviates the need for a dedicated chip select pin, which may save space on the chip and help reduce the complexity of line routing between chips.

Before addressing exemplary aspects of the present disclosure, a brief overview of a chip-to-multiple chip system that uses an SPI link is provided in <FIG> and <FIG>, and a chip-to-chip system that uses an SPI link is provided in <FIG> to provide context for the subsequent discussion. <FIG> provides a signaling diagram for a conventional SPI link and a discussion of exemplary aspects of the present disclosure begins below with reference to <FIG>.

In this regard, <FIG> is a block diagram of a conventional chip-to-multiple chip system <NUM> that uses an SPI link <NUM> to communicate between chips. As used herein, a chip is an integrated circuit (IC) or monolithic IC that has a set of electronic circuits on one small piece of semiconductor material such as silicon. It should be appreciated that a plurality of chips may be stacked to form a system in a package (SiP) that may be a number of ICs enclosed in one or more chip carrier packages that may be stacked using package-on-package. The SiP performs all or most of the functions of an electronic system, and is typically used inside a mobile phone, digital music player, etc. Dies containing ICs may be stacked vertically on a substrate. The dies are internally connected by fine wires that are bonded to the package. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together. A SiP is like a system on a chip (SoC) but less tightly integrated and not on a single semiconductor die.

With continued reference to <FIG> a first chip <NUM> may be a host IC. Historically, a host IC might be referred to as a master IC and such terminology may be used interchangeably herein. The first chip <NUM> is coupled through the SPI link <NUM> to a plurality of second chips <NUM>(<NUM>)-<NUM>(N), where as illustrated, N=<NUM>. The second chips <NUM>(<NUM>)-<NUM>(<NUM>) may be referred to as device chips or slave chips. The SPI link <NUM> includes a clock line (SCLK) <NUM>, a master out, slave in (MOSI) line <NUM>, a master in, slave out (MISO) line <NUM>, and a slave select (SS) line <NUM>. The slave select line <NUM> is also commonly referred to as a chip select (CS) line. In <FIG>, the second chips <NUM>(<NUM>)-<NUM>(<NUM>) are arranged in a daisy chain, where the MISO of the second chip <NUM>(<NUM>) connects to the MOSI of the second chip <NUM>(<NUM>). The MISO of the second chip <NUM>(<NUM>) connects to the MOSI of the second chip <NUM>(<NUM>), and the MISO of the second chip <NUM>(<NUM>) connects to the MISO of the first chip <NUM>.

In contrast, the second chips may be independently arranged as better illustrated by the chip-to-multiple chip system <NUM>' illustrated in <FIG>. The second chips <NUM>(<NUM>)-<NUM>(N) are the same, but the SPI link <NUM>' has additional slave select lines <NUM>(<NUM>)-<NUM>(N) that individually couple the first chip <NUM>' to the second chips <NUM>(<NUM>)-<NUM>(N). Likewise, instead of daisy chaining the second chips <NUM>(<NUM>)-<NUM>(N), the MOSI line <NUM> couples the first chip <NUM>' to each of the second chips <NUM>(<NUM>)-<NUM>(N), and the MISO line <NUM> likewise couples each of the second chips <NUM>(<NUM>)-<NUM>(N) to the first chip <NUM>'.

While the chip-to-multiple chip systems <NUM> and <NUM>' are defined and used in some instances within a computing device, more commonly SPI may be used to connect just a single pair of chips as better illustrated by system <NUM>" in <FIG>. The system <NUM>" includes a first chip <NUM> and just a single second chip <NUM>. The SPI link <NUM> contains the lines <NUM>, <NUM>, <NUM>, and <NUM> previously discussed, but has no need for daisy chaining or extra chip select lines.

<FIG> illustrates a signal diagram <NUM> for a typical SPI link <NUM>. Apart from designating which second chip <NUM>(<NUM>)-<NUM>(N) is being enabled or selected, the CS line <NUM> also indicates a valid transaction phase by asserting a logical low during the active transaction. The falling edge <NUM> indicates a start of transaction and a rising edge <NUM> indicates an end of transaction. During the valid transaction window <NUM>, the clock line <NUM> provides a clock signal <NUM>. Outside the valid transaction window <NUM>, the clock line <NUM> is held at a logical high. The first chip <NUM> may send a command <NUM> on the MOSI line <NUM> in the valid transaction window <NUM>, which causes the second chip <NUM> to send responsive data <NUM> on the MISO line <NUM>.

It should be appreciated that SPI is a low-speed (typically below <NUM> megahertz (MHz) and more commonly below <NUM> with throughput ranges around <NUM> megabits per second (Mbps) to <NUM> Mbps), synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. Thus, while exemplary aspects of the present disclosure focus on SPI as an exemplary aspect, other synchronous serial communication systems that employ full duplex communication and include a slave or chip select lines may also benefit from the present disclosure.

The SPI specification has proven useful since its introduction in the mid-<NUM>. However, more modern computing devices may have a central application processor or modem that has numerous associated sensor chips or affiliated chips which are not amenable to daisy chain or independent control on a multiple slave bus. Thus, each of these sensor or affiliated chips may have its own SPI link with the corresponding four lanes or lines therewithin. Each line requires its own pin or bump on each of the chips, which adds to the cost and complexity of both chips. Likewise, routing many lines between an application and a plurality of affiliated chips can be challenging.

Exemplary aspects of the present disclosure allow the elimination of the chip select line and the corresponding chip select pin from both ends of an SPI link. Where a chip, such as a SoC or other chip, has multiple SPI master circuits, elimination of the chip select line and pin allows for multiplicative space and cost savings. Exemplary aspects of the present disclosure not only eliminate the chip select lines and pins, but also preserve the valid transaction indication function of the chip select line by introducing a signaling sequence between the host and the device using the remaining lines. In particular, the host signals the start of a new transaction by manipulating the clock line of the SPI link and receiving an acknowledgment from the device of the MISO line. Similarly, the end of a transaction is signaled by the host using the clock line and an acknowledgment is received on the MISO line.

An exemplary system <NUM> is illustrated in <FIG>. The system <NUM> includes a host (or master) chip <NUM> coupled to a device (or slave) chip <NUM> by a modified SPI link <NUM>. The modified SPI link <NUM> has a clock (SCLK) line <NUM>, a MISO line <NUM>, and a MOSI line <NUM>, but does not have a slave or chip select line. The host chip <NUM> may include a clock <NUM> and a control circuit <NUM> as well as a bus interface <NUM> (sometimes referred to as a host bus interface). Similarly, the device chip <NUM> may include an internal clock <NUM> and a control circuit <NUM> as well as a bus interface <NUM> (sometimes referred to as a device bus interface to differentiate it from the host bus interface). It should be appreciated that the bus interfaces <NUM>, <NUM> may include pins or bumps (although as used herein, the term "pin" is defined to include bumps). In particular, the host bus interface <NUM> may include a clock pin 318A, an input pin 318B (corresponding to the MISO line <NUM>), and an output pin 318C (corresponding to the MOSI line <NUM>). Similarly, the device bus interface <NUM> may include a clock pin 324A, an output pin 324B (corresponding to the MISO line <NUM>), and an input pin 324C (corresponding to the MOSI line <NUM>).

In an exemplary aspect, the host chip <NUM> and the device chip <NUM> may initially be connected and perform a handshake-based two-way synchronization. Handshake synchronization is well understood in the art, but may be summarized as a request and acknowledgement mechanism to guarantee a sampling of correct data into a destination clock domain irrespective of clock ratio between the source (e.g., the host chip <NUM> and clock <NUM>) and the destination clock (e.g., the device chip <NUM> and internal clock <NUM>). There may be other ways to synchronize the host chip <NUM> and the device chip <NUM>, and such are within the scope of the present disclosure.

Relevant to the synchronization process is that the device chip <NUM>, and particularly the control circuit <NUM>, may understand the ratio between the clocks <NUM>, <NUM> and know or determine that sampling across N (i.e., some predetermined value) clock cycles of the internal clock <NUM> is required to reliably detect a change in state in the clock signal at the clock pin 324A and confirm that the change in state is being maintained. This ability is relevant for a transaction start sequence as explained in greater detail below with reference to <FIG>.

In this regard, <FIG> illustrates a transaction start sequence process <NUM> that includes a few preliminary steps including the system <NUM> entering an idle state (block <NUM>) and the host chip <NUM> driving the clock signal on the clock line <NUM> to a logical low (block <NUM>). The device chip <NUM> holds the MISO line <NUM> at a last state known to the host chip <NUM> (block <NUM>). Note that in an initial start up, the host chip <NUM> knows that the MISO line <NUM> starts at a logical low, so even if this particular idle state has no preceding active state, the host chip <NUM> may still know the expected state of the MISO line <NUM>.

With continued reference to <FIG>, the host chip <NUM> determines to exit the idle state (block <NUM>). The exit from the idle state may be caused by a need to sample a sensor, a need to access data within the device chip <NUM>, or the like. The host chip <NUM> asserts the clock signal on the clock line <NUM> to a logical high (block <NUM>). The device chip <NUM> samples the clock signal at the clock pin 324A for a predetermined number of clock cycles of the internal clock <NUM> to detect and confirm the change on the clock pin 324A (block <NUM>). Note that this predetermined number may be programmable and may be a function of the ratios of the clock frequencies of the clocks <NUM>, <NUM> and may be set during the handshake synchronization process. The device chip <NUM> sends an acknowledgment (ACK) by inverting the MISO line <NUM> for a predetermined number of clock cycles (of the internal clock <NUM>) (block <NUM>). The host chip <NUM> detects the ACK by sampling the MISO line <NUM> and deasserts the clock signal (block <NUM>).

With continued reference to <FIG>, the device chip <NUM> samples the clock signal for a predetermined number of clock cycles of the internal clock <NUM> to detect and confirm the change on the clock pin 324A. The device chip <NUM> enters the transaction phase (block <NUM>) and sends a second ACK by inverting the MISO line <NUM> (block <NUM>). The host chip <NUM> detects the second ACK and enters the transaction phase with corresponding operation of the clock signal on the clock line <NUM> (block <NUM>).

By using a transaction start sequence such as that shown in process <NUM>, the transaction start function of the now missing chip select pin may be preserved. Thus, even though the chip select pin is omitted, the device chip <NUM> may be instructed to enter the transaction state.

The process <NUM> corresponds to a signaling diagram <NUM> illustrated in <FIG>. A first line <NUM> corresponds to a state of the host chip <NUM>, where the host chip <NUM> starts in an idle state <NUM>, enters a start state <NUM> and then enters a transaction state <NUM>. The host chip <NUM> controls the clock line <NUM> shown at line <NUM> and the MOSI line <NUM> shown at line <NUM> while the device chip <NUM> controls the MISO line <NUM> shown at line <NUM>. The device chip <NUM> sees the host chip <NUM> assert the clock signal on the clock line <NUM> at time <NUM> (corresponding to block <NUM>). While the clock is asserted, the device chip <NUM> is sampling the clock signal to detect and confirm the assertion. The device chip <NUM> then inverts the MISO line <NUM> (both from low to high and high to low shown) at time <NUM> to provide the first ACK (corresponding to block <NUM>). The host chip <NUM> detects this first ACK and deasserts the clock line at time <NUM> (corresponding to block <NUM>). The device chip <NUM> detects and confirms this change of state in the clock line and sends the second ACK at time <NUM> by inverting the MISO line <NUM> (corresponding to block <NUM>). As shown in line <NUM> which has the state of the device chip <NUM>, the device chip <NUM> starts in an idle state <NUM>, and enters a start state <NUM> at time <NUM> by sending the first ACK. The start state <NUM> ends at time <NUM> by sending the second ACK, and the device chip <NUM> enters a transaction state <NUM>. In the transaction state <NUM>, the host chip <NUM> may send a command <NUM> on the MOSI line <NUM>, which causes the device chip <NUM> to sends data <NUM> on the MISO line <NUM>.

Similarly, the present disclosure provides a stop transaction sequence to preserve the stop transaction function of the omitted chip select pin. This process <NUM> is illustrated in <FIG>. The process <NUM> starts with the host chip <NUM> determining that an end of the transaction has occurred and detects the last MISO state (block <NUM>). Note that the detection of the last MISO state is relevant to block <NUM> described above. The host chip <NUM> then holds the clock signal at a logical high (block <NUM>). The device chip <NUM> samples the clock signal for a predetermined number of clock cycles of the internal clock <NUM> to detect and confirm the change to the logical high (block <NUM>). The device chip <NUM> sends a stop ACK by inverting the MISO line (block <NUM>). The host chip <NUM> receives the stop ACK and deasserts the clock signal (block <NUM>). The device chip <NUM> samples the clock for a predetermined number of clock cycles of the internal clock <NUM> to detect and confirm the logical low of the clock signal (block <NUM>) and sends a second stop ACK by inverting the MISO line back to its original "last state" and enters an idle state (block <NUM>). The host chip <NUM> receives the second stop ACK and enters the idle state (block <NUM>).

<FIG> provides a signaling diagram <NUM> of the stop sequence. The host chip <NUM> starts in a transaction state <NUM> with the clock signal active (<NUM>) on clock line <NUM> (shown by line <NUM>). Likewise, data <NUM> is being sent on the MISO line <NUM> (indicated by line <NUM>). The MOSI line <NUM> (indicated by line <NUM>) is quiescent while the data <NUM> is being delivered. As the host chip <NUM> reaches the end of the transaction state <NUM>, the host chip <NUM> drives the clock line <NUM> to a logical high <NUM> to enter a stop transaction state <NUM>. The device chip <NUM>, which was in a transaction state <NUM> initially holds the MISO line <NUM> at the last state (generally at <NUM>) while the device chip <NUM> samples the clock line <NUM> at the clock pin 324A for a sufficient number of clock cycles from the internal clock <NUM> to determine and confirm the extended logical high and then inverts the MISO line <NUM> (generally at <NUM>) to provide a stop ACK to the host chip <NUM> and enters a stop state <NUM>. On receipt of the stop ACK, the host chip <NUM> drives the clock line <NUM> to a logical low at <NUM>. The device chip <NUM> sends a second stop ACK by inverting the MISO line <NUM> again (generally at <NUM>) and enters an idle state <NUM>. On receipt of the second stop ACK, the host chip <NUM> also enters an idle state <NUM>.

While there are myriad ways that the bus interfaces <NUM>, <NUM> and control circuits <NUM>, <NUM> may be implemented, <FIG> and <FIG> provide two illustrative block diagrams showing how they may be implemented in the host chip <NUM> and device chip <NUM>, respectively. In this regard, <FIG> illustrates a circuit <NUM> for the host chip <NUM> and <FIG> illustrates a circuit <NUM> for the device chip <NUM>.

With reference to <FIG>, the circuit <NUM> may have a state machine <NUM> that transitions between an idle state <NUM>, a start state <NUM>, a transaction state <NUM> and a stop state <NUM>. When the state machine <NUM> enters the start state <NUM>, a signal is sent to an OR gate <NUM>, which sends a request to a two-way handshake-based synchronizer circuit <NUM>. The OR gate <NUM> also receives a signal when the state machine <NUM> enters the stop state <NUM>. The synchronizer circuit <NUM> receives a clock signal from the clock <NUM> and generates a request signal to a multiplexer <NUM> that controls the signal on the clock line <NUM>. The multiplexer <NUM> also receives a clock signal from a host finite state machine (FSM) <NUM>. A multiplexer <NUM> is similarly coupled to the MISO line <NUM> and an AND gate <NUM> is coupled to the MOSI line <NUM>. The signal from the MISO line <NUM> is provided to the host FSM <NUM> and the synchronizer circuit <NUM>, which indicates that the various ACKs were received form the device chip <NUM>.

With reference to <FIG>, the circuit <NUM> may have a state machine <NUM> that transitions between an idle state <NUM>, a start state <NUM>, a transaction state <NUM>, and a stop state <NUM>. The clock signal from the clock line <NUM> is provided to a start/stop detector circuit <NUM> that uses the local clock <NUM> to test the clock signal for "N" cycles to determine if the clock signal is being held at a logical high or logical low. That is, if each sample in the N cycles of the local clock <NUM> is the same, the device chip <NUM> infers that the clock signal is being held at a level. The start/stop detector circuit <NUM> may then output a detected signal <NUM> to the state machine <NUM>. The clock signal is also supplied to a multiplexer <NUM> that outputs a one or a zero depending on the state. The zero is output to a device FSM <NUM>, while the one is output to a two-way handshake-based synchronizer circuit <NUM>. The synchronizer circuit <NUM> also receives a signal from the local clock <NUM> and outputs an ACK to a multiplexer <NUM> as well as ACK Edge1 and ACK_Edge2 signals. The device FSM <NUM> is also coupled to the multiplexer <NUM> to control the MISO line <NUM>. The MOSI line <NUM> is coupled to an AND gate <NUM>, which provides a signal to the device FSM <NUM>.

The systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> is a system-level block diagram of an exemplary mobile terminal <NUM> such as a smart phone, mobile computing device tablet, or the like. While a mobile terminal s is particularly contemplated as being capable of benefiting from exemplary aspects of the present disclosure, it should be appreciated that the present disclosure may be useful in any system having an SPI bus.

With continued reference to <FIG>, the mobile terminal <NUM> includes an application processor <NUM> (sometimes referred to as a host) that communicates with a mass storage element <NUM> through a universal flash storage (UFS) bus <NUM>. The application processor <NUM> may further be connected to a display <NUM> through a display serial interface (DSI) bus <NUM> and a camera <NUM> through a camera serial interface (CSI) bus <NUM>. Various audio elements such as a microphone <NUM>, a speaker <NUM>, and an audio codec <NUM> may be coupled to the application processor <NUM> through a serial low-power interchip multimedia bus (SLIMbus) <NUM>. Additionally, the audio elements may communicate with each other through a SOUNDWIRE bus <NUM>. A modem <NUM> may also be coupled to the SLIMbus <NUM> and/or the SOUNDWIRE bus <NUM>. The modem <NUM> may further be connected to the application processor <NUM> through a peripheral component interconnect (PCI) or PCI express (PCIe) bus <NUM> and/or a system power management interface (SPMI) bus <NUM>.

With continued reference to <FIG>, the SPMI bus <NUM> may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) <NUM>, a power management integrated circuit (PMIC) <NUM>, a companion IC (sometimes referred to as a bridge chip) <NUM>, and a radio frequency IC (RFIC) <NUM>. It should be appreciated that separate PCI buses <NUM> and <NUM> may also couple the application processor <NUM> to the companion IC <NUM> and the WLAN IC <NUM>. The application processor <NUM> may further be connected to sensors <NUM> through a sensor bus <NUM>, which may be an SPI bus. The modem <NUM> and the RFIC <NUM> may communicate using a bus <NUM>.

With continued reference to <FIG>, the RFIC <NUM> may couple to one or more RFFE elements, such as an antenna tuner <NUM>, a switch <NUM>, and a power amplifier <NUM> through a radio frequency front end (RFFE) bus <NUM>. Additionally, the RFIC <NUM> may couple to an envelope tracking power supply (ETPS) <NUM> through a bus <NUM>, and the ETPS <NUM> may communicate with the power amplifier <NUM>. Collectively, the RFFE elements, including the RFIC <NUM>, may be considered an RFFE system <NUM>. It should be appreciated that the RFFE bus <NUM> may be formed from a clock line and a data line (not illustrated).

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion.

Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

Claim 1:
An integrated circuit, IC, comprising:
a bus interface comprising:
a clock pin configured to couple to a clock line on an associated bus;
an input pin configured to couple to an input line on the associated bus; and
an output pin configured to couple to an output line on the associated bus;
an internal clock coupled to a control circuit; and
the control circuit configured to detect a start command by being configured to:
detect a change on the clock pin by detecting a transition from a logical low to a logical high on the clock pin that lasts a predetermined number of clock cycles of the internal clock;
in response, send a first start acknowledgment, ACK, on the output pin that the change was detected;
after sending the first start ACK, detect a subsequent change on the clock pin; and
in response, send a second start ACK on the output pin.