Patent Description:
<CIT> discloses a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same wherein the capacitor may include a first conductive layer a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

<CIT> discloses a semiconductor device includes a lower electrode; an upper electrode disposed to be spaced apart from the lower electrode; and a dielectric layer disposed between the lower electrode and the upper electrode, and including a first metal oxide region, a second metal oxide region, and a third metal oxide region.

<CIT> discloses a capacitor which has the lower electrode having a structure in which the first conductive layer containing a first metal, the second conductive layer that is formed on the first conductive layer and made of the metal oxide of the second metal different from the first metal, and the third conductive layer that is formed on the second conductive layer and made of the third metal different from the first metal are formed sequentially; the dielectric layer formed on the lower electrode; and the upper electrode formed on the capacitor dielectric layer.

Further prior art is in: <NPL>; and in <NPL>.

As electronics technology advances, semiconductor devices may be rapidly downscaled, and thus, patterns configuring electronic devices may be miniaturized. Based thereon, it may be desirable to reduce leakage current in capacitors having a fine size and to maintain desired electrical characteristics.

The inventive concept provides an integrated circuit device including a capacitor structure, which may decrease a leakage current.

According to a partial aspect of the inventive concept, there is provided an integrated circuit device including a transistor on a substrate and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode including a first conductive material having a first work function, a dielectric layer on the first electrode, the dielectric layer including a first metal, a second electrode on the first electrode with the dielectric layer therebetween, the second electrode including a second conductive material having a second work function that is less than the first work function, and an interfacial layer between the dielectric layer and the second electrode, where the interfacial layer increases an electrical energy barrier between the second electrode and the dielectric layer relative to that of a direct interface therebetween.

According to another aspect of the inventive concept, there is provided an integrated circuit device including a transistor on a substrate and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode including a first conductive material having a first work function, a dielectric layer on the first electrode, the dielectric layer including first metal oxide including a first metal, a second electrode on the first electrode with the dielectric layer therebetween, the second electrode including a second conductive material having a second work function that is less than the first work function, and an interfacial layer between the dielectric layer and the second electrode, wherein the interfacial layer includes an insulating interfacial layer including a second metal, and a valence of the second metal of the insulating interfacial layer is less than a valence of the first metal of the dielectric layer.

According to another partial aspect of the inventive concept, there is provided an integrated circuit device including a word line in a word line trench extending in a first direction in a substrate, a contact structure on the substrate and electrically connected to the word line, and a capacitor structure on the contact structure and electrically connected to the contact structure, wherein the capacitor structure includes a first electrode including a first conductive material having a first work function, a dielectric layer on the first electrode, the dielectric layer including a first metal oxide including a first metal, a second electrode on the first electrode with the dielectric layer therebetween and including a second conductive material having a second work function that is less than the first work function, and an interfacial layer between the dielectric layer and the second electrode, the first metal comprises zirconium (Zr), hafnium (Hf), titanium (Ti), or tantalum (Ta), the interfacial layer includes an insulating interfacial layer including a second metal, a valence of the second metal being less than a valence of the first metal of the dielectric layer and a first conductive interfacial layer including a third metal, an electronegativity of the third metal being greater than an electronegativity of the first metal of the dielectric layer, the insulating interfacial layer and the first conductive interfacial layer are stacked in a vertical direction perpendicular to a surface of the second electrode, between the dielectric layer and the second electrode, wherein the interfacial layer is increases an electrical energy barrier between the second electrode and the dielectric layer relative to that of a direct interface therebetween.

Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements in the drawings, and their repeated descriptions are omitted. The terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated elements, but do not preclude the presence of additional elements.

<FIG> is a cross-sectional view illustrating a capacitor structure <NUM> of an integrated circuit device according to embodiments.

Referring to <FIG>, the integrated circuit device according to embodiments may include a capacitor structure <NUM> formed on a substrate.

The substrate may include a semiconductor, such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiC, GaAs, InAs, and InP. The substrate may include structures which each include a semiconductor substrate and at least one conductive region or at least one insulation layer formed on the semiconductor substrate. The conductive region may include, for example, an impurity-doped well or an impurity-doped structure. In embodiments, the substrate may have various device isolation structures such as a shallow trench isolation (STI) structure.

The capacitor structure <NUM> may be disposed on the substrate and may be electrically connected to a transistor formed on and/or in the substrate. The capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, an interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1. The first direction D1 may be defined as a direction vertical or normal to one surface of the second electrode <NUM> facing the dielectric layer <NUM>, and a second direction D2 may be defined as a direction parallel to the one surface of the second electrode <NUM> facing the dielectric layer <NUM>. The terms "first," "second," "third," etc., may be used herein merely to distinguish one element, layer, direction, etc., from another. Elements referred to herein as "connected to" may be electrically and/or physically connected.

The first electrode <NUM> and the second electrode <NUM> may face each other with the dielectric layer <NUM> and the interfacial layer <NUM> therebetween. In embodiments, the first electrode <NUM> and the second electrode <NUM> may be respectively referred to as a lower electrode and an upper electrode.

Each of the first electrode <NUM> and the second electrode <NUM> may include a metal-containing film or doped polysilicon. Each of the first electrode <NUM> and the second electrode <NUM> may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal oxynitride film, or a combination thereof. In embodiments, each of the first electrode <NUM> and the second electrode <NUM> may include metal such as titanium (Ti), niobium (Nb), cobalt (Co), tin (Sn), ruthenium (Ru), or tungsten (W), nitride including the metal, or oxide including the metal. In embodiments, each of the first electrode <NUM> and the second electrode <NUM> may include NbN, TiN, TaN, CoN, SnO<NUM>, or a combination thereof. In embodiments, each of the first electrode <NUM> and the second electrode <NUM> may include TaN, TiAlN, TaAlN, W, Ru, RuO<NUM>, SrRuO<NUM>, Ir, IrO<NUM>, Pt, PtO, SRO(SrRuO<NUM>), BSRO((Ba,Sr)RuO<NUM>), CRO(CaRuO<NUM>), LSCO((La,Sr)CoO<NUM>), or a combination thereof. However, a material of the first electrode <NUM> and a material of the second electrode <NUM> are not limited to the embodiments described above. In some embodiments, each of the first electrode <NUM> and the second electrode <NUM> may include a single layer or a multi-layer structure.

In some embodiments, the first electrode <NUM> may include a first conductive material having a first work function, and the second electrode <NUM> may include a second conductive material having a second work function which is less than the first work function. The first conductive material may differ from the second conductive material. In embodiments, the first work function may be determined to be a value which is greater than a predetermined reference work function, and the second work function may be determined to be a value which is less than the reference work function. In embodiments, the reference work function may be one value selected from among about <NUM> eV to about <NUM> eV, one value selected from among <NUM> eV to <NUM> eV, or one value selected from among <NUM> eV to <NUM> eV. In embodiments, the first conductive material of the first electrode <NUM> may include precious metal (for example, platinum (Pt), iridium (Ir), etc.), and the second conductive material of the second electrode <NUM> may include Ti, tantalum (Ta), Nb, or W.

The dielectric layer <NUM> may include a high-k dielectric film. The term "high-k dielectric film" described herein may be defined as a dielectric film having a dielectric constant which is higher than that of a silicon oxide film. In embodiments, the dielectric layer <NUM> may include first metal oxide including first metal. The first metal may include at least one material selected from among hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), titanium (Ti), strontium (Sr), and barium (Ba). In embodiments, the first metal oxide included in the dielectric layer <NUM> may include HfO<NUM>, ZrO<NUM>, Al<NUM>O<NUM>, La<NUM>O<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, SrTiO<NUM>, BaSrTiO<NUM>, Nb<NUM>O<NUM>, CeO<NUM>, or a combination thereof, but is not limited thereto. The dielectric layer <NUM> may have a single-layer structure including one high-k dielectric film, or may have a multi-layer structure including a plurality of high-k dielectric films.

The interfacial layer <NUM> may be disposed between the dielectric layer <NUM> and the second electrode <NUM>. The interfacial layer <NUM> may be inserted between the dielectric layer <NUM> and the second electrode <NUM>, and may be configured to increase an electrical energy barrier between the dielectric layer <NUM> and the second electrode <NUM>. The interfacial layer <NUM> may include an insulating interfacial film, a conductive interfacial film, or a combination thereof. For example, a thickness of the interfacial layer <NUM> may be within a range of about <NUM>Å to about <NUM>Å, <NUM>Å to <NUM>Å, <NUM>Å to <NUM>Å, <NUM>Å to <NUM>Å, <NUM>Å to <NUM>Å, or <NUM>Å to <NUM>Å in the first direction D1.

<FIG> is a cross-sectional view illustrating a capacitor structure <NUM>' of an integrated circuit device according to a comparative example. <FIG> is an energy band diagram of the capacitor structure <NUM>' of <FIG>. <FIG> is a graph showing the I-V characteristic representing a behavior of a leakage current with respect to an applied voltage, in the capacitor structure <NUM>' of <FIG>.

Referring to <FIG>, the capacitor structure <NUM>' according to the comparative example may include a first electrode <NUM>, a second dielectric layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1. The capacitor structure <NUM>' according to the comparative example may not include the interfacial layer, and the second electrode <NUM> may contact the dielectric layer <NUM>.

The first electrode <NUM> may include a first conductive material having a first work function Φ1, and the second electrode <NUM> may include a second conductive material having a second work function Φ2. The first work function Φ1 may correspond to a difference between a vacuum energy level E0 and a fermi level of the first conductive material, and the second work function Φ2 may correspond to a difference between the vacuum energy level E0 and the fermi level of the first conductive material. Because the first work function Φ1 is greater than the second work function Φ2, a first electrical energy barrier Φ3 formed between the first electrode <NUM> and the dielectric layer <NUM> may be greater than a second electrical energy barrier Φ4 formed between the second electrode <NUM> and the dielectric layer <NUM>. When the second electrical energy barrier Φ4 formed between the second electrode <NUM> and the dielectric layer <NUM> is less than the first electrical energy barrier Φ3 formed between the first electrode <NUM> and the dielectric layer <NUM>, a higher leakage current may occur in the second electrode <NUM> where an electrical energy barrier is relatively small, while an external voltage is being applied to the capacitor structure <NUM>'. In this case, as shown in <FIG>, the I-V characteristic representing a behavior of a leakage current based on an external voltage applied to the capacitor structure <NUM>' may be asymmetrical. That is, a leakage current when a voltage having a positive value (i.e., a voltage which is higher than <NUM> V) is applied to the capacitor structure <NUM>' and a leakage current when a voltage having a negative value (i.e., a voltage which is lower than <NUM> V) is applied to the capacitor structure <NUM>' may be asymmetrically shown. When the I-V characteristic is asymmetrical, a higher leakage current may occur in one direction of application of the external voltage to the capacitor structure <NUM>', and the amount of electric charge lost in the capacitor structure <NUM>' may increase, causing a problem where the reliability of the capacitor structure <NUM>' is reduced.

<FIG> is a graph showing the I-V characteristic representing a behavior of a leakage current with respect to an applied voltage in a capacitor structure according to embodiments.

Referring to <FIG> and <FIG>, the interfacial layer <NUM> may be inserted between the dielectric layer <NUM> and the second electrode <NUM>, and an electrical energy barrier between the dielectric layer <NUM> and the second electrode <NUM> may be increased by the interfacial layer <NUM>. In embodiments, the electrical energy barrier formed between the dielectric layer <NUM> and the second electrode <NUM> may be increased to a level which is substantially the same as (i.e., the same as or similar to) a first electrical energy barrier (Φ3 of <FIG>) formed between the first electrode <NUM> and the dielectric layer <NUM>, based on the interfacial layer <NUM>. That is, the interfacial layer <NUM> is configured to increase the electrical energy barrier between the second electrode <NUM> and the dielectric layer <NUM> so as to be substantially the same as an electrical energy barrier between the first electrode <NUM> and the dielectric layer <NUM>. In embodiments, the interfacial layer <NUM> inserted between the dielectric layer <NUM> and the second electrode <NUM> may act based on a p-type doping effect, and thus, an electrical energy barrier between the dielectric layer <NUM> and the second electrode <NUM> may be increased. In embodiments, the electrical energy barrier between the dielectric layer <NUM> and the second electrode <NUM> may be increased based on polarization formed by the interfacial layer <NUM> inserted between the dielectric layer <NUM> and the second electrode <NUM>. As shown in <FIG>, in the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions, as the electrical energy barrier between the dielectric layer <NUM> and the second electrode <NUM> is increased by the interfacial layer <NUM>, the I-V characteristic representing a behavior of a leakage current based on an external voltage applied to the capacitor structure <NUM> may be symmetrical or may have substantial symmetry (also referred to herein as substantially symmetrical, which need not have exact symmetry). When the capacitor structure <NUM> has a symmetrical I-V characteristic, a leakage current based on an external voltage applied to the capacitor structure <NUM> may symmetrically occur in both directions of the external voltage, and in this case, the loss of an electric charge from the capacitor structure <NUM> may be reduced or prevented, thereby improving the reliability of the capacitor structure <NUM>.

<FIG> is a cross-sectional view illustrating a capacitor structure <NUM> of an integrated circuit device according to embodiments. <FIG> is a diagram showing an energy band diagram with respect to an applied voltage, in the capacitor structure <NUM> of <FIG>.

Referring to <FIG> and <FIG>, the capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, an insulating interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1.

The insulating interfacial layer <NUM> may include an insulation material including a second metal, which may be different than the first metal of the dielectric layer <NUM>. In embodiments, the insulating interfacial layer <NUM> may include a metal oxide including the second metal.

In embodiments, a valence of the second metal included in the insulating interfacial layer <NUM> may be less than that of the first metal included in the dielectric layer <NUM>. In embodiments, when the first metal included in the dielectric layer <NUM> has a valence of +<NUM> or more, the second metal included in the insulating interfacial layer <NUM> may have a valence of +<NUM> or less. In embodiments, when the first metal included in the dielectric layer <NUM> has a valence of +<NUM> or more, the second metal included in the insulating interfacial layer <NUM> may have a valence of +<NUM> or less. In embodiments, the first metal included in the dielectric layer <NUM> may be selected from among Zr, Hf, Ti, and Ta, and the second metal included in the insulating interfacial layer <NUM> may be selected from rare-earth metals (for example, lanthanum (La) and yttrium (Yt)). In embodiments, the dielectric layer <NUM> may include HfO<NUM>, ZrO<NUM>, TiO<NUM>, Ta<NUM>O<NUM>, or a combination thereof, and the insulating interfacial layer <NUM> may include La<NUM>O<NUM>, Y<NUM>O<NUM>, or a combination thereof.

In embodiments, a thickness of the insulating interfacial layer <NUM> in the first direction D1 may be <NUM>Å or less. In embodiments, a thickness of the insulating interfacial layer <NUM> in the first direction D1 may be within a range of <NUM>Å to <NUM>Å.

When the insulating interfacial layer <NUM> inserted between the second electrode <NUM> and the dielectric layer <NUM> includes the second metal having a valence which is less than that of the first metal included in the dielectric layer <NUM>, the insulating interfacial layer <NUM> may act based on the p-type doping effect, and thus, an electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased. Accordingly, the electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> maybe increased by the insulating interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG> and <FIG>, the capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, a first conductive interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1.

The first conductive interfacial layer <NUM> may include a conductive material including third metal. In embodiments, the first conductive interfacial layer <NUM> may include a third metal, conductive nitride including the third metal, conductive oxide including the third metal, conductive oxynitride including the third metal, or a combination thereof.

In embodiments, an electronegativity of the third metal included in the first conductive interfacial layer <NUM> may be greater than that of the first metal included in the dielectric layer <NUM>. In embodiments, an electronegativity of the third metal may be determined to be a value which is greater than predetermined reference electronegativity, and an electronegativity of the first metal may be determined to be a value which is less than the reference electronegativity. An electronegativity of the first metal, an electronegativity of the third metal, and the reference electronegativity may be defined by a Pauling electronegativity criterion. In embodiments, the reference electronegativity may be one value selected from among <NUM> to <NUM>, one value selected from among <NUM> to <NUM>, one value selected from among <NUM> to <NUM>, or one value selected from among <NUM> to <NUM>. The first metal included in the dielectric layer <NUM> may be selected from among Zr, Hf, Ti, Ta, Sr, barium (Ba), and Al, and the third metal included in the first conductive interfacial layer <NUM> may be selected from among chromium (Cr), molybdenum (Mo), W, Ru, Co, Ir, nickel (Ni), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and Sn.

In embodiments, a thickness of the first conductive interfacial layer <NUM> in the first direction D1 may be <NUM>Å or less. In embodiments, a thickness of the first conductive interfacial layer <NUM> in the first direction D1 may be within a range of <NUM>Å to <NUM>Å.

When the first conductive interfacial layer <NUM> inserted between the second electrode <NUM> and the dielectric layer <NUM> includes third metal having electronegativity which is greater than that of the first metal included in the dielectric layer <NUM>, an electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by polarization formed by the first conductive interfacial layer <NUM>. Accordingly, the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG>, the capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, a second conductive interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1.

The second conductive interfacial layer <NUM> may include a conductive material including a fourth metal. In embodiments, the second conductive interfacial layer <NUM> may include a second metal oxide including the fourth metal.

In embodiments, an oxygen chemical potential of the second metal oxide included in the second conductive interfacial layer <NUM> may be greater than that of first metal oxide included in the dielectric layer <NUM>. In embodiments, the first metal oxide of the dielectric layer <NUM> may include HfO<NUM>, ZrO<NUM>, Al<NUM>O<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, SrTiO<NUM>, BaSrTiO<NUM>, or a combination thereof, and the second metal oxide of the second conductive interfacial layer <NUM> may include Mo oxide, W oxide, Ru oxide, Ir oxide, Pt oxide, Sn oxide, or a combination thereof.

In embodiments, a thickness of the second conductive interfacial layer <NUM> in the first direction D1 may be <NUM>Å or less. In embodiments, a thickness of the second conductive interfacial layer <NUM> in the first direction D1 may be within a range of <NUM>Å to <NUM>Å.

When an oxygen chemical potential of second metal oxide included in the second conductive interfacial layer <NUM> inserted between the second electrode <NUM> and the dielectric layer <NUM> is greater than that of the first metal oxide included in the dielectric layer <NUM>, an electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by polarization formed by the second conductive interfacial layer <NUM>. Accordingly, the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG>, the capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, an interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1, and the interfacial layer <NUM> may include a first interfacial layer <NUM> and a second interfacial layer <NUM>, which are stacked in the first direction D1. The first interfacial layer <NUM> may contact the dielectric layer <NUM>, and the second interfacial layer <NUM> may contact the second electrode <NUM>.

The first interfacial layer <NUM> may correspond to one of the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and the second conductive interfacial layer <NUM> described above with reference to <FIG>. The second interfacial layer <NUM> may correspond to one of the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and the second conductive interfacial layer <NUM> described above with reference to <FIG>.

<FIG> is a diagram showing an energy band diagram with respect to an applied voltage, in a capacitor structure <NUM> according to embodiments.

Referring to <FIG> and <FIG>, in the capacitor structure <NUM>, a first interfacial layer <NUM> may correspond to the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and a second interfacial layer <NUM> may correspond to one of the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG> and the second conductive interfacial layer <NUM> described above with reference to <FIG>. An electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by the first interfacial layer <NUM> and the second interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG> and <FIG>, in the capacitor structure <NUM>, a first interfacial layer <NUM> may correspond to one of the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG> and the second conductive interfacial layer <NUM> described above with reference to <FIG>, and a second interfacial layer <NUM> may correspond to the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>. An electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by the first interfacial layer <NUM> and the second interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG> and <FIG>, in the capacitor structure <NUM>, one of a first interfacial layer <NUM> and a second interfacial layer <NUM> may correspond to one of the first conductive interfacial layers <NUM> described above with reference to <FIG> and <FIG>, and other one of the first interfacial layer <NUM> and the second interfacial layer <NUM> may correspond to the second conductive interfacial layer <NUM> described above with reference to <FIG>. An electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by the first interfacial layer <NUM> and the second interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG>, the capacitor structure <NUM> may include a first electrode <NUM>, a dielectric layer <NUM>, an interfacial layer <NUM>, and a second electrode <NUM>, which are sequentially stacked in a first direction D1, and the interfacial layer <NUM> may include a first interfacial layer <NUM>, a second interfacial layer <NUM>, and a third interfacial layer <NUM>, which are stacked in the first direction D1. The first interfacial layer <NUM> may contact the dielectric layer <NUM>, the third interfacial layer <NUM> may contact the second electrode <NUM>, and the second interfacial layer <NUM> may be disposed between the first interfacial layer <NUM> and the third interfacial layer <NUM>.

The first interfacial layer <NUM> may correspond to one of the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and the second conductive interfacial layer <NUM> described above with reference to <FIG>. The second interfacial layer <NUM> may correspond to one of the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and the second conductive interfacial layer <NUM> described above with reference to <FIG>. The third interfacial layer <NUM> may correspond to one of the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and the second conductive interfacial layer <NUM> described above with reference to <FIG>.

Referring to <FIG> and <FIG>, in the capacitor structure <NUM>, each of a first interfacial layer <NUM> and a third interfacial layer <NUM> may correspond to the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>, and a second interfacial layer <NUM> may correspond to one of the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG> and the second conductive interfacial layer <NUM> described above with reference to <FIG>. An electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by the based on the interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

Referring to <FIG> and <FIG>, in the capacitor structure <NUM>, each of a first interfacial layer <NUM> and a third interfacial layer <NUM> may correspond to one of the first conductive interfacial layer <NUM> described above with reference to <FIG> and <FIG> and the second conductive interfacial layer <NUM> described above with reference to <FIG>, and a second interfacial layer <NUM> may correspond to the insulating interfacial layer <NUM> described above with reference to <FIG> and <FIG>. An electrical energy barrier formed between the second electrode <NUM> and the dielectric layer <NUM> may be increased by the interfacial layer <NUM>, and the capacitor structure <NUM> including the first and second electrodes <NUM> and <NUM> having different work functions may have a symmetrical I-V characteristic.

<FIG> is a layout view illustrating an integrated circuit device <NUM> according to embodiments. <FIG> is a cross-sectional view taken along line B1-B1' of <FIG>.

Referring to <FIG> and <FIG>, the integrated circuit device <NUM> may include a capacitor structure CSA on a buried channel array transistor (BCAT) structure.

A substrate <NUM> may include an active region AC defined by a device isolation layer <NUM>. In some embodiments, the substrate <NUM> may include a Si wafer.

In some embodiments, the device isolation layer <NUM> may have an STI structure. For example, the device isolation layer <NUM> may include an insulation material which is filled into a device isolation trench 212T formed in the substrate <NUM>. The insulation material may include fluoride silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma enhanced deposition of tetra-ethyl-ortho-silicate (PE-TEOS), or tonen silazene (TOSZ), but is not limited thereto.

The active region AC may have a relatively long island shape having a short axis and a long axis. As illustrated, the long axis of the active region AC may be arranged in a D3 direction parallel to an upper surface of the substrate <NUM>. In some embodiments, the active region AC may have a first conductive type. The first conductive type may be a p-type (or an n-type).

The substrate <NUM> may include a word line trench 220T which extends in an X direction. The word line trench 220T may intersect with the active region AC and may be formed by a certain depth from the upper surface of the substrate <NUM>. A portion of the word line trench 220T may extend to an inner portion of the device isolation portion <NUM>, and a portion of the word line trench 220T formed in the device isolation layer <NUM> may include a bottom surface disposed at a level which is lower than a portion of the word line trench 220T formed in the active region AC.

A first source/drain region 216A and a second source/drain region 216B may be disposed at an upper portion of the active region AC disposed at both or opposing sides of the word line trench 220T. The first source/drain region 216A and the second source/drain region 216B may each be an impurity region doped with impurities having a second conductive type which differs from the first conductive type. The second conductive type may be n-type (or p-type).

A word line WL may be formed in the word line trench 220T. The word line WL may include a gate insulation layer <NUM>, a gate electrode <NUM>, and a gate capping layer <NUM>, which are sequentially formed on an inner wall of the word line trench 220T.

The gate insulation layer <NUM> may be conformally formed on the inner wall of the word line trench 220T to have a certain thickness. The gate insulation layer <NUM> may include at least one material selected from among silicon oxide, silicon nitride, silicon oxynitride, oxide/nitride/oxide (ONO), and a high-k dielectric material having a dielectric constant which is greater than that of silicon oxide. For example, the gate insulation layer <NUM> may have a dielectric constant of about <NUM> to about <NUM>. In some embodiments, the gate insulation layer <NUM> may include HfO<NUM>, Al<NUM>O<NUM>, HfAlO<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, or a combination thereof, but is not limited thereto.

The gate electrode <NUM> may be formed up to a certain height from a bottom portion of the word line trench 220T to fill the word line trench 220T, on the gate insulation layer <NUM>. The gate electrode <NUM> may include a work function adjustment layer (not shown) which is disposed on the gate insulation layer <NUM> and a buried metal layer (not shown) which fills the bottom portion of the word line trench 220T, on the work function adjustment layer. For example, the work function adjustment layer may include at least one of metal such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, and TaSiCN, metal nitride, and metal carbide, and the buried metal layer may include at least one of W, WN, TiN, and TaN.

The gate capping layer <NUM> may fill a residual portion of the word line trench 220T, on the gate electrode <NUM>. For example, the gate capping layer <NUM> may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

A bit line BL extending in a Y direction vertical to an X direction may be formed on the first source/drain region 216A. The bit line BL may include a bit line contact <NUM>, a bit line conductive layer <NUM>, and a bit line capping layer <NUM>, which are sequentially stacked on the substrate <NUM>. For example, the bit line contact <NUM> may include polysilicon, and the bit line conductive layer <NUM> may include metal. The bit line capping layer <NUM> may include an insulation material such as silicon oxynitride or silicon nitride. In the drawing, a bottom surface of the bit line contact <NUM> is illustrated as having the same level as an upper surface of the substrate <NUM>, but is not limited thereto and may be formed at a level which is lower than the upper surface of the substrate <NUM>.

Optionally, a bit line middle layer (not shown) may be disposed between the bit line contact <NUM> and the bit line conductive layer <NUM>. The bit line middle layer may include metal silicide such as tungsten silicide or metal nitride such as tungsten nitride. A bit line spacer (not shown) may be further formed on a sidewall of the bit line BL. The bit line spacer may include a single-layer or multi-layer structure which includes an insulation material such as silicon oxide, silicon oxynitride, or silicon nitride. Also, the bit line spacer may further include an air spacer (not shown).

A first interlayer insulation layer <NUM> may be formed on the substrate <NUM>, and the bit line contact <NUM> may pass through the first interlayer insulation layer <NUM> and may be connected to the first source/drain region 216A. The bit line conductive layer <NUM> and the bit line capping layer <NUM> may be disposed on the first interlayer insulation layer <NUM>. A second interlayer insulation layer <NUM> may cover a sidewall of the bit line conductive layer <NUM> and a side surface and an upper surface of the bit line capping layer <NUM>, on the first interlayer insulation layer <NUM>.

A contact structure <NUM> may be disposed on the second source/drain region 216B. The first and second interlayer insulation layers <NUM> and <NUM> may surround a sidewall of the contact structure <NUM>. In some embodiments, the contact structure <NUM> may include a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown), which are sequentially stacked on the substrate <NUM>, and a barrier layer (not shown) which surrounds a side surface and a bottom surface of the upper contact pattern. In some embodiments, the lower contact pattern may include polysilicon, and the upper contact pattern may include a metal material. The barrier layer may include a metal nitride having conductivity, that is, a conductive metal nitride.

The capacitor structure CSA may be formed on the second interlayer insulation layer <NUM>. The capacitor structure CSA may correspond to one of the capacitor structures <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above with reference to <FIG> and <FIG>. An etch stop layer <NUM> including an opening portion 250T may be formed on the second interlayer insulation <NUM>, and a bottom portion of the lower electrode <NUM> may be disposed in the opening portion 250T of the etch stop layer <NUM>.

The capacitor structure CSA may include the lower electrode <NUM> electrically connected to the contact structure <NUM>, a dielectric layer <NUM> on the lower electrode <NUM>, the upper electrode <NUM> on the dielectric layer <NUM>, and an interfacial layer <NUM> disposed between the dielectric layer <NUM> and the upper electrode <NUM>. The lower electrode <NUM> may be formed in a pillar shape which extends in a Z direction on the contact structure <NUM>, and the dielectric layer <NUM> may conformally extend along an upper surface and a sidewall of the lower electrode <NUM>. The upper electrode <NUM> may be disposed on the dielectric layer <NUM>. The interfacial layer <NUM> may correspond to one of the interfacial layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above with reference to <FIG> and <FIG>. In <FIG>, it is illustrated that a work function of a conductive material included in the upper electrode <NUM> is less than that of a conductive material included in the lower electrode <NUM> and the interfacial layer <NUM> is inserted between the upper electrode <NUM> and the dielectric layer <NUM>. However, according to embodiments, the work function of the conductive material included in the lower electrode <NUM> may be less than that of the conductive material included in the upper electrode <NUM>, and in this case, the upper electrode <NUM> may directly contact the dielectric layer <NUM> and the interfacial layer <NUM> may be disposed between the lower electrode <NUM> and the dielectric layer <NUM>. As used herein, when elements or layers have a "direct interface," "directly contact," or are "directly on" one another, no intervening elements or layers are present.

In the drawings, it is illustrated that the capacitor structure CSA is repeatedly arranged in the X direction and the Y direction on the contact structure <NUM> which is repeatedly arranged in the X direction and the Y direction. However, in further embodiments, unlike the illustration, the capacitor structure CSA may be arranged in a hexagonal shape such as a honeycomb pattern, on the contact structure <NUM> which is repeatedly arranged in the X direction and the Y direction, and in this case, a landing pad (not shown) may be formed between the contact structure <NUM> and the capacitor structure CSA.

According to embodiments, an electrical energy barrier between the dielectric layer <NUM> and an electrode having a relatively low work function may be increased by the interfacial layer <NUM> inserted between the dielectric layer <NUM> and an electrode having a relatively low work function, and thus, the capacitor structure CSA may have a symmetrical I-V characteristic. Accordingly, the reliability of the capacitor structure CSA and the reliability of the integrated circuit device <NUM> including the capacitor CSA may be improved.

<FIG> is a layout view illustrating an integrated circuit device <NUM> according to embodiments. <FIG> is a cross-sectional view taken along line B2-B2' of <FIG>.

Referring to <FIG> and <FIG>, the integrated circuit device <NUM> may include a capacitor structure CSB on a vertical channel transistor (VCT) structure.

A lower insulation layer <NUM> may be disposed on a substrate <NUM>, and a plurality of first conductive lines <NUM> may be spaced apart from one another in an X direction and may extend in a Y direction, on the lower insulation layer <NUM>. A plurality of first insulation patterns <NUM> may be disposed on the lower insulation layer <NUM> to fill a space between the plurality of first conductive lines <NUM>. The plurality of first conductive lines <NUM> may correspond to a bit line BL of the integrated circuit device <NUM>.

In some embodiments, the plurality of first conductive lines <NUM> may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines <NUM> may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, but are not limited thereto. The plurality of first conductive lines <NUM> may include a single-layer or multi-layer structure of the material. In some embodiments, the plurality of first conductive lines <NUM> may include a two-dimensional (2D) semiconductor material, and for example, the 2D semiconductor material may include graphene, carbon nanotube, or a combination thereof.

The channel layer <NUM> may be arranged in an island shape where channel layers <NUM> are spaced apart from each other in the X direction and the Y direction, on the plurality of first conductive lines <NUM>. The channel layer <NUM> may have a channel width in the X direction and a channel height in a Z direction, and the channel height may be greater than the channel width. A bottom portion of the channel layer <NUM> may function as a first source/drain region (not shown), an upper portion of the channel layer <NUM> may function as a second source/drain region (not shown), and a portion of the channel layer <NUM> between the first and second source/drain regions may function as a channel region (not shown). A VCT may represent a structure where a channel length of the channel layer <NUM> extends in the Z direction from the substrate <NUM>.

In some embodiments, the channel layer <NUM> may include an oxide semiconductor, and for example, the oxide semiconductor may include InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, or a combination thereof. The channel layer <NUM> may include a single-layer or multi-layer structure of the oxide semiconductor. In some embodiments, the channel layer <NUM> may have band gap energy which is greater than that of silicon. The channel layer <NUM> may be poly-crystal or amorphous, but is not limited thereto. In some embodiments, the channel layer <NUM> may include a 2D semiconductor material, and for example, the 2D semiconductor material may include graphene, carbon nanotube, or a combination thereof.

In some embodiments, the gate electrode <NUM> may surround a sidewall of the channel layer <NUM> and may extend in the X direction. In the drawing, the gate electrode <NUM> may be a gate electrode of a gate-all-around type which surrounds a whole sidewall of the channel layer <NUM>. The gate electrode <NUM> may correspond to a word line WL of the integrated circuit device <NUM>.

In other embodiments, the gate electrode <NUM> may be a gate electrode of a dual gate type, and for example, may include a first sub gate electrode (not shown) which faces a first sidewall of the channel layer <NUM> and a second sub gate electrode (not shown) which faces a second sidewall, which is opposite to the first sidewall, of the channel layer <NUM>.

In some other embodiments, the gate electrode <NUM> may be a gate electrode of a single gate type which covers only the first sidewall of the channel layer <NUM> and extends in the X direction.

The gate electrode <NUM> may include doped polysilicon, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode <NUM> may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

The gate insulation layer <NUM> may surround the sidewall of the channel layer <NUM> and may be disposed between the channel layer <NUM> and the gate electrode <NUM>. In some embodiments, the gate insulation layer <NUM> may include silicon oxide, silicon oxynitride, a high-k dielectric film having a dielectric constant which is greater than that of silicon oxide, or a combination thereof. The high-k dielectric film may include metal oxide or metal oxynitride. For example, the high-k dielectric film included in the gate insulation layer <NUM> may include HfO<NUM>, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO<NUM>, Al<NUM>O<NUM>, or a combination thereof, but is not limited thereto.

A first buried insulation layer <NUM> surrounding a lower sidewall of the channel layer <NUM> may be disposed on the plurality of first insulation patterns <NUM>, and a second buried insulation layer <NUM> which surrounds the lower sidewall of the channel layer <NUM> and covers the gate electrode <NUM> may be disposed on the first buried insulation layer <NUM>.

A capacitor contact <NUM> may be disposed on the channel layer <NUM>. The capacitor contact <NUM> may be disposed to vertically overlap the channel layer <NUM> and may be arranged in a matrix form which is arranged from adjacent capacitor contacts in the X direction and the Y direction. The capacitor contact <NUM> may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, but is not limited thereto. The upper insulation layer <NUM> may surround a sidewall of the capacitor contact <NUM>, on the second buried insulation layer <NUM>.

The etch stop layer <NUM> may be disposed on the upper insulation layer <NUM>, and a capacitor structure CSB may be disposed on the etch stop layer <NUM>. The capacitor structure CSB may correspond to one of the capacitor structures <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above with reference to <FIG> and <FIG>. The capacitor structure CSB may include a lower electrode <NUM>, a dielectric layer <NUM>, an upper electrode <NUM>, and an interfacial layer <NUM>. The lower electrode <NUM> may be electrically connected to the capacitor contact <NUM>, the dielectric layer <NUM> may cover the lower electrode <NUM>, and the upper electrode <NUM> may cover the lower electrode <NUM>, on the dielectric layer <NUM>. A supporting member <NUM> may be disposed on a sidewall of the lower electrode <NUM>. The interfacial layer <NUM> may be disposed between the upper electrode <NUM> and the dielectric layer <NUM>. The interfacial layer <NUM> may correspond to one of the interfacial layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above with reference to <FIG> and <FIG>. In <FIG>, it is illustrated that a work function of a conductive material included in the upper electrode <NUM> is less than that of a conductive material included in the lower electrode <NUM> and the interfacial layer <NUM> is inserted between the upper electrode <NUM> and the dielectric layer <NUM>. However, according to embodiments, the work function of the conductive material included in the lower electrode <NUM> may be less than that of the conductive material included in the upper electrode <NUM>, and in this case, the upper electrode <NUM> may directly contact the dielectric layer <NUM> and the interfacial layer <NUM> may be disposed between the lower electrode <NUM> and the dielectric layer <NUM>.

Claim 1:
An integrated circuit device (<NUM>, <NUM>) comprising:
a transistor on a substrate (<NUM>, <NUM>); and
a capacitor structure (<NUM>-<NUM>) electrically connected to the transistor, wherein
the capacitor structure (<NUM>-<NUM>) comprises:
a first electrode (<NUM>) including a first conductive material having a first work function;
a dielectric layer (<NUM>, <NUM>) on the first electrode (<NUM>), the dielectric layer (<NUM>, <NUM>) including a first metal;
a second electrode (<NUM>) on the first electrode (<NUM>) with the dielectric layer (<NUM>, <NUM>) therebetween, the second electrode (<NUM>) including a second conductive material having a second work function that is less than the first work function; and
an interfacial layer (<NUM>-<NUM>, <NUM>, <NUM>, <NUM>) between the dielectric layer (<NUM>, <NUM>) and the second electrode (<NUM>), wherein the interfacial layer (<NUM>-<NUM>, <NUM>, <NUM>, <NUM>) increases an electrical energy barrier between the second electrode (<NUM>) and the dielectric layer (<NUM>, <NUM>) relative to that of a direct interface therebetween,
wherein the interfacial layer (<NUM>-<NUM>, <NUM>, <NUM>, <NUM>) comprises an insulating interfacial layer (<NUM>) including a second metal, and a valence of the second metal of the insulating interfacial layer (<NUM>) is less than a valence of the first metal of the dielectric layer (<NUM>, <NUM>),
wherein a thickness of the insulating interfacial layer (<NUM>) is about <NUM>Å or less in a vertical direction perpendicular to a surface of the second electrode (<NUM>) facing the dielectric layer (<NUM>, <NUM>), and the electrical energy barrier between the second electrode (<NUM>) and the dielectric layer (<NUM>, <NUM>) is substantially the same as an electrical energy barrier between the first electrode (<NUM>) and the dielectric layer (<NUM>, <NUM>).