Patent Description:
Line drivers are used in electronics to transmit signals through transmission lines. Types of line drivers include voltage mode drivers and current mode drivers.

<CIT> discloses an N-bit analog to digital converter which includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

<CIT> describes a low voltage differential signaling ("LVDS") line driver includes a pre-emphasis circuit to increase the drive capability of the LVDS line driver. A current source provides a first drive current to a current steering circuit. The pre-emphasis circuit includes a second current source, a current sourcing circuit coupled to the second current source and the current steering circuit and a current sinking circuit coupled to the second current source and the current steering circuit. In this way, first and second drive currents are provided to during the switching of the signal states of an input signal, so that more drive current is supplied to the output of the LVDS line driver circuit. Thus, the time it takes for the current steering circuit to switch the drive current between the first and second directions is decreased.

The present invention is defined by the attached independent claims. Other preferred embodiments may be found in the dependent claims. The present application discloses a circuit comprising:a first transistor having a control terminal and a first output terminal;a second transistor having a second output terminal coupled to the first output terminal;a driving stage connected to the control terminal, the driving stage comprising a first driver having a first speed and a second driver having a second speed slower than the first speed,wherein the control terminal is a first control terminal and the driving stage is a first driving stage, and further comprising:a third transistor having a third output terminal and a second control terminal;a fourth transistor having a fourth output terminal coupled to the third output terminal; and a second driving stage connected to the second control terminal, the second driving stage comprising a third driver having a third speed and a fourth driver having a fourth speed slower than the third speed.

Voltage mode drivers have the advantage of consuming less power, compared to some other types of line drivers. Accordingly, voltage mode drivers are used to drive transmission lines in a variety of applications. However, the inventor has appreciated a challenge in the design of voltage mode drivers that has arisen as the size of integrated transistors decreases (e.g., at smaller transistor fabrication "nodes"). In particular, smaller transistors may be less able to handle the voltage stresses needed to drive the required voltages on a transmission line. Applying a voltage to the transistors greater than that which they are designed to withstand risks damage to the transistors and/or may cause unacceptably high leakage current. However, smaller fabrication nodes provide the opportunity to drive electronic circuits at higher data rates. Accordingly, as the demand for bandwidth increases, circuit designers have an incentive to migrate to smaller fabrication nodes.

<FIG> shows an example of a voltage mode driver <NUM>. Voltage mode driver <NUM> includes transistors M<NUM>, M<NUM>, M<NUM> and M<NUM> and four resistors R. Resistor Rout represents the impedance of the transmission line driven by the voltage mode driver <NUM>. The voltage used to drive a signal through a transmission line is often specified by a standard. A transmission line voltage level specified according to a standard will be referred to herein as the "line level. " As an example, a standard may specify a line level of 1V peak-to-peak (1Vpp). To supply a line level of 1Vpp, the voltage mode driver <NUM> needs to have the capability of producing a voltage of 1V across Rout. To do so, the supply voltage of the voltage mode driver <NUM> needs to be at least 1V. However, fabrication nodes are decreasing in size to the point where the transistors are no longer capable of withstanding a supply voltage of 1V. As an example, a manufacturer may specify that the maximum voltage that can be supplied to a transistors fabricated using a <NUM>-fabrication node is <NUM>. As another example, a manufacturer may specify that the maximum voltage that can be supplied to a circuit fabricated using a <NUM>-fabrication node is <NUM>. Providing a voltage to the transistor (e.g., across the gate and source of a MOSFET) higher than the maximum specified by the manufacturer risks causing damage to the transistors and/or high leakage current. Reducing the supply voltage may not be an acceptable solution, as reducing the supply voltage of voltage mode driver <NUM> does not allow supplying a signal of 1Vpp.

<FIG> illustrates applying a supply voltage of <NUM>. 75V to voltage mode driver <NUM>. In this example, the resistance of resistors R is 50Ω and Rout has an impedance of 100Ω. Transistors M<NUM> and M<NUM> are PMOS transistors, and M<NUM> and M<NUM> are NMOS transistors. The drain of each transistor is coupled to a terminal of Rout through a resistor R. The sources of transistors M<NUM> and M<NUM> are provided with a <NUM>. 75V supply voltage, which is equal to the maximum supply voltage specified by the manufacturer, and the sources of transistors M<NUM> and M<NUM> are grounded. If the gates of transistors M<NUM> and M<NUM> are driven with zero voltage and transistors M<NUM> and M<NUM> are driven with <NUM>. 75V, the voltages appearing at the terminals of Rout are equal to <NUM>. 5625V and <NUM>. 1875V respectively. In this case, the voltage difference at the terminals of Rout is <NUM>. 5625V-<NUM>. 1875V=<NUM>. In case of driving a signal of opposite polarity, the voltage across the terminals of Rout are equal to <NUM>. 1875V and <NUM>. 5625V respectively. In this case, the voltage difference at the terminals of Rout is <NUM>. 1875V-<NUM>. 5625V =-<NUM>. Toggling between -<NUM>. 375V and <NUM>. 375V, Rout exhibits a <NUM>.

The present inventor has developed circuits and associated techniques that allow supplying the desired line voltage while keeping the voltage of the transistors(s) within their voltage limits. In some embodiments, the supply voltage can exceed the voltage limits of the transistors. To allow the transistors to withstand the supply voltage, a control signal is applied to a control terminal of a transistor through parallel control paths (e.g., fast and slow control paths) that respond to the control signal with different speeds. The way in which the parallel control paths allow the transistors to withstand the voltage will be described with reference to <FIG>.

<FIG> is a block diagram illustrating a line driver <NUM> with parallel control paths of different speeds, according to some embodiments. Line driver <NUM> includes transistors M<NUM>, M<NUM>, M<NUM> and M<NUM>, resistors R<NUM>, R<NUM>, R<NUM> and R<NUM>, drivers D<NUM>, D<NUM>, D<NUM>', D<NUM>', D<NUM> and D<NUM> and capacitors C<NUM> and C<NUM>. Driver D<NUM>' serves as slow control path <NUM>, and driver D<NUM> and capacitor C<NUM> serve as fast control path <NUM>. In some embodiments, transistor M<NUM> and M<NUM> are PMOS transistors, and M<NUM> and M<NUM> are NMOS transistors. However, the present invention is not limited to MOS transistors, and any other suitable type of transistor may be used, including bipolar junction transistors (BJT), heterojunction bipolar transistor (HBT), junction field effect transistor (JFET ), etc. The transistors of line driver <NUM> may be fabricated using any suitable fabrication node, such as less than or equal to <NUM>, less than equal to <NUM>, less than equal to <NUM>, less than equal to <NUM>, less than equal to <NUM>, less than equal to <NUM>, less than equal to <NUM> or less than equal to <NUM>.

Transistors M<NUM> and M<NUM> may be coupled to supply voltage VLL, for example, through the respective source terminals, while transistors M<NUM> and M<NUM> may be coupled to supply voltage VHH, through the respective source terminals, for example. In some embodiments, the drain of transistor M<NUM> may be coupled to the output terminal labeled Vout+ through resistor R<NUM>, and the drain of transistor M<NUM> may be coupled to Vout+ through resistor R<NUM>. In some embodiments, the drain of transistor M<NUM> may be coupled to the output terminal labeled Vout- through resistor R<NUM>, and the drain of transistor M<NUM> may be coupled to Vout- through resistor R<NUM>. Output terminals Vout+ and Vout- may be coupled to respective conductors of a transmission line. Examples of a transmission line that may be driven by the line driver <NUM> include the wires of a twinax cable, or a pair of metal traces disposed on a printed circuit board, by way of example and not limitation. In some embodiments, the transmission line may exhibit a impedance equal to 50Ω, 75Ω, 80Ω or 100Ω. However, transmission lines exhibiting any other suitable resistance may be coupled to line driver <NUM>.

Each driver may receive an input signal, and in response, may place the corresponding transistor in a on or off state. An "on state" is referred to herein to either indicate an NMOS transistor having a gate/source voltage VGS greater than or equal to the threshold voltage, or a PMOS transistor having a source/gate voltage VSG greater than or equal to the absolute value of the threshold voltage. Contrarily, an "off state" is referred to herein to either indicate an NMOS transistor having a gate/source voltage VGS less than the threshold voltage or a PMOS transistor having a source/gate voltage VSG less than the absolute value of the threshold voltage.

The gate of transistor M<NUM> may be coupled to the output of driver D<NUM>, through capacitor C<NUM>, and to the output of driver D<NUM>', and the gate of transistor M<NUM> may be coupled to the output of driver D<NUM>, through capacitor C<NUM>, and to the output of driver D<NUM>'. The gate of transistor M<NUM> may be coupled to the output of driver D<NUM> and the gate of transistor M<NUM> may be coupled to the output of driver D4. Drivers D<NUM>, D<NUM>' and D<NUM> may be configured to receive input signal Vin-, and drivers D<NUM>, D<NUM>' and D<NUM> may be configured to receive input signal Vin+. Input signals Vin+ and Vin- may toggle between VLL and VH. Input signals Vin+ and Vin- may represent a differential signal in some embodiments. Drivers D<NUM> and D<NUM> may be configured to receive voltage supplies VH and VLL, while drivers D<NUM>' and D<NUM>' may be configured to receive voltage supplies VHH and VL.

In some embodiments, fast control path <NUM> may have a first speed, and fast control path <NUM> may have a second speed, less than the first speed. For example, fast control path <NUM> may be configured to track signals that vary at a frequency up to <NUM>, and slow control path <NUM> may be configured to track signals that vary at a frequency up to <NUM>.

In some embodiments, the line driver <NUM> may be configured to receive a supply voltage greater that the maximum voltage for the particular fabrication node utilized. As an example, line driver <NUM> may be fabricated using a fabrication node such that only voltages no greater than <NUM>. 75V can be withstood. Nevertheless, the line driver <NUM> may receive a 1V supply voltage, and may drive transmission lines with a 1Vpp. As will be described further below, the use of a fast control path and a slow control path to drive the signals allows the line driver to withstand the voltage in excess.

By way of example and not limitation, Vin- may exhibit a succession of logic <NUM>, represented by the voltage VH, and <NUM>, represented by the voltage VLL, as illustrated in <FIG>. In response to receiving Vin-, driver D<NUM> may output signal VA, illustrated in <FIG>. Driver D<NUM> may be configured to output a signal that tracks Vin-. Accordingly, signal VA may exhibit a succession of logic <NUM>, represented by the voltage VH, and <NUM>, represented by the voltage VLL, that tracks the succession provided by Vin-. Having a lower speed, driver D<NUM>' may not be fast enough to track Vin-, and may output a signal VB that varies at a slower rate with respect to VA, as shown in <FIG>, which illustrates a non-limiting example of signal VB.

In some embodiments, to provide a slower speed, driver D<NUM>' may comprise transistor(s) having a gate dielectric layer that is thicker than the gate dielectric layer used in driver D<NUM>. Having a thicker gate dielectric, the transistor(s) of driver D<NUM>' may be configured to withstand voltages greater than VH-VLL. <FIG> are schematic diagrams illustrating two MOSFET transistors having different gate dielectric thicknesses. Transistor <NUM> of <FIG>, may be used within driver D<NUM> while transistor <NUM> of <FIG> may be used within driver D<NUM>'.

Transistor <NUM> may comprise substrate <NUM>, source doped well <NUM>, drain doped well <NUM>, gate dielectric <NUM>, source terminal <NUM>, gate terminal <NUM> and drain terminal <NUM>. Substrate <NUM> may be a common substrate shared by a plurality of transistors of the type of transistor <NUM>. Source terminal <NUM> may be disposed in correspondence with source doped well <NUM> and drain terminal <NUM> may be disposed in correspondence with drain doped well <NUM>. Gate dielectric <NUM> may be disposed between gate terminal <NUM> and substrate <NUM>. Gate dielectric <NUM> may comprise silicon oxide in some embodiments. Gate dielectric <NUM> may have a thickness TD, which may be between <NUM> and <NUM> in some embodiments.

Transistor <NUM> may comprise substrate <NUM>, source doped well <NUM>, drain doped well <NUM>, gate dielectric <NUM>, source terminal <NUM>, gate terminal <NUM> and drain terminal <NUM>. Substrate <NUM> may be a common substrate shared by a plurality of transistors of the type of transistor <NUM>. Source terminal <NUM> may be disposed in correspondence with source doped well <NUM> and drain terminal <NUM> may be disposed in correspondence with drain doped well <NUM>. Gate dielectric <NUM> may be disposed between gate terminal <NUM> and substrate <NUM>. Gate dielectric <NUM> may comprise silicon oxide in some embodiments. Gate dielectric <NUM> may have a thickness TD', which may be between <NUM> and <NUM> in some embodiments.

In some embodiments, transistor <NUM> may be used within driver D<NUM> and transistor <NUM> may be used within driver D<NUM>'. In such embodiments, the thickness TD of dielectric <NUM> may be lower than the thickness TD' of dielectric <NUM>. For example, TD may be at least two times lower than TD', at least three times lower than TD', at least five times lower than TD', at least ten times lower than TD', or at least twenty times lower than TD'.

Referring back to <FIG>, the capacitor C<NUM> may be used to retain the charge provided by driver D<NUM>', while providing a path for signal VA. Capacitor C<NUM> may also block the direct current (DC) component of signal VA. Accordingly, signal VC may have a DC component provided by driver D<NUM>' and time-varying frequency components provided by driver D<NUM>.

By combining a fast signal VA, toggling between VLL and VH, and a slowly varying signal VB, the resulting signal VC may track VA while toggling between VL and VHH. <FIG> illustrates a non-limiting example of VC in response to Vin-. As illustrated, capacitor C<NUM>, used in combination with drivers D<NUM> and D<NUM>', may effectively operate as a level shifter receiving VLL and VH as inputs, and providing VL and VHH as outputs.

When VC is equal to VL, the source/gate voltage of transistor M<NUM> may be equal VHH-VC =VHH-VL. Since VHH-VL is within the rating range of the transistor, transistor M<NUM> may operate without experiencing stress.

By way of example and not limitation, VLL=<NUM>, VL=<NUM>. 25V, VH=<NUM>. 75V and VHH=1V, and Vin+ and Vin- may toggle between VLL, representing a logic <NUM>, and <NUM>. 75V, representing a logic <NUM>. According to such example, the transistors M<NUM>-M<NUM> of line driver <NUM> may be configured to withstand voltages between the gate and the source, having an absolute value equal to or less than <NUM>. When Vin- is equal to <NUM>, VA may be equal to <NUM> and VC may be equal to <NUM>. Accordingly, the source/gate voltage of transistor M<NUM> is equal to 1V-<NUM>. In this case the source/gate voltage of transistor M<NUM> is within the rating range of the transistor, and transistor M<NUM> may operate without experiencing stress. Fast control path and a slow control path act as a level shifter, shifting a <NUM> logic from <NUM> to <NUM>. 25V, thus maintain the source/gate voltage of transistor M<NUM> below <NUM>.

When Vin- is equal to <NUM>. 75V, VA may be equal to <NUM> and VC may be equal to 1V. Accordingly, the source/gate voltage of transistor M<NUM> is equal to 1V-1V=<NUM>. In this case the source/gate voltage of transistor M<NUM> may cause transistor M1 to be in an off state without experiencing current leakage. Fast control path and a slow control path act as a level shifter, shifting a <NUM> logic from <NUM> to 1V, thus maintain the source/gate voltage of transistor M<NUM> to <NUM>.

Drivers D<NUM>, and D<NUM>' and capacitor C<NUM> may receive signal Vin+ and may be configured to operate in the same manner as described in connection with drivers D<NUM>, and D<NUM>' and capacitor C<NUM>.

Line driver <NUM> may exhibit one of two possible states. The first state occurs when Vin- is equal to a logic <NUM> and Vin+ is equal to a logic <NUM>. In such a circumstance, the gate of transistor M<NUM> my receive a voltage equal to VL, thus placing transistor M<NUM> in an on state. The gate of transistor M<NUM> my receive a voltage equal to VHH, thus placing transistor M<NUM> in an off state. The gate of transistor M<NUM> my receive a voltage equal to VLL, thus placing transistor M<NUM> in an off state. The gate of transistor M<NUM> my receive a voltage equal to VH, thus placing transistor M<NUM> in an on state. Since M<NUM> and M<NUM> are in an on state, a current may flow through transistor M<NUM>, resistor R<NUM>, resistor Rout, resistor R<NUM> and transistor M<NUM>. In some embodiments, resistors R<NUM> and R<NUM> may exhibit equal resistances, and such resistance may be equal to half of the resistance associated with Rout. In such embodiments, the output voltage Vout+- Vout- may be equal to (VHH-VLL)/<NUM>. Referring back to the non-limiting example provided above, Vout+- Vout- =<NUM>.

The second state occurs when Vin- is equal to a logic <NUM> and Vin+ is equal to a logic <NUM>. In such a circumstance, the gate of transistor M<NUM> my receive a voltage equal to VHH, thus placing transistor M<NUM> in an off state. The gate of transistor M<NUM> my receive a voltage equal to VL, thus placing transistor M<NUM> in an on state. The gate of transistor M<NUM> my receive a voltage equal to VH, thus placing transistor M<NUM> in an on state. The gate of transistor M<NUM> my receive a voltage equal to VLL, thus placing transistor M<NUM> in an off state. Since M<NUM> and M<NUM> are in an on state, a current may flow through transistor M<NUM>, resistor R<NUM>, resistor Rout, resistor R<NUM> and transistor M<NUM>. In some embodiments, resistors R<NUM> and R<NUM> may exhibit equal resistances, and such resistance may be equal to half of the resistance associated with Rout. In such embodiments, the output voltage Vout+- Vout- may be equal to -(VHH-VLL)/<NUM>. Referring back to the non-limiting example provided above, Vout+- Vout- =-(<NUM>. 25V)=-<NUM>. 5V, thus providing a 1Vpp as desired.

In some circumstances, it may be desirable to implement drivers D<NUM>' and D<NUM>' without resorting to transistors having different gate dielectric thicknesses. For example, some fabrication processes may provide process design kits (PDK) having only one type of transistor, such that all the transistors have the same gate dielectric thickness.

In some embodiments, driver D<NUM>' (and/or D<NUM>') may be implemented using a latch circuit. <FIG> illustrates an exemplary latch circuit, according to some embodiments. Latch circuit <NUM> may comprise transistors M<NUM>, M<NUM>, M<NUM>, M<NUM>, M<NUM> and M<NUM>. In some embodiments, the transistors may be PMOS transistors. However, other types of transistors may be used. The drain terminals of transistors M<NUM> and M<NUM> may be coupled to a voltage supply VLL, such as a ground terminal. The source terminals of transistors M<NUM> and M<NUM> may be coupled to the drain terminals of transistors M<NUM> and M<NUM> respectively. The source terminals of transistors M<NUM> and M<NUM> may be coupled to a supply voltage VHH. The gate terminals of transistor M<NUM> and M<NUM> may be coupled to the source terminals of transistors M<NUM> and M<NUM> respectively. In some embodiments, the drain terminal of transistor M<NUM> may be coupled to the drain terminal of transistor M<NUM>, and the drain terminal of transistor M<NUM> may be coupled to the drain terminal of transistor M<NUM>. The gate terminals of transistors M<NUM> and M<NUM> may be coupled together. The source terminals of transistors M<NUM> and M<NUM> may be coupled to a supply voltage VHH.

The gate terminal of transistor M<NUM> may be driven by signal Vin- through driver D<NUM>. The gate terminal of transistor M<NUM> may be driven by an inverted version of signal Vin- through inverter driver D<NUM>. When Vin- switches from a logic <NUM> to a logic <NUM>, transistor M<NUM> may switch to an off state, and transistor M<NUM> may switch to an on state. As a current flows through transistors M<NUM> and M<NUM>, the voltage at the drain terminal of transistor M<NUM> may charge the capacitance associated with the gate terminal of transistor M<NUM>. Consequently the voltage VB may slowly increase. Contrarily, when Vin- switches from a logic <NUM> to a logic <NUM>, transistor M<NUM> may switch to an on state, and transistor M<NUM> may switch to an off state. As a current flows through transistor M<NUM> and M<NUM>, the voltage at the drain terminal of transistor M<NUM> may charge the capacitance associated with the gate terminal of transistor M<NUM>. At the same time, the capacitance associated with the gate terminal of transistor M<NUM> may discharge. Consequently the voltage VB may slowly decay. In some embodiments, latch circuit <NUM> may be configured to provide a voltage VB equal to the moving average of signal Vin-.

In some embodiments, a line driver of the type described herein may be used in a digital-to-analog converter (DAC). The DAC may comprise a plurality of cells. For example, the DAC may comprise one cell for each bit of a digital word to be converted. <FIG> is a block diagram illustrating an exemplary DAC, according to some embodiments. DAC <NUM> may comprise a plurality of line drivers LD<NUM>, LD<NUM>. One or more such line drivers may be implemented using line driver <NUM>. Each line driver may be configured to receive a corresponding digital signal, which may be represented by a series of bits b<NUM>, b<NUM>. Each line driver may be configured to drive resistor Rout, which may represent the resistance of a transmission line. In some embodiments, a resistive ladder may be used to perform the digital-to-analog conversion. For example, for each line driver, the resistors R<NUM>, R<NUM>, R<NUM> and R<NUM> may be configured to provide an output having a desired weight. Alternatively, or additionally, a transistor ladder may be used. For example, for each line driver, the size of transistors M<NUM>, M<NUM>, M<NUM> and M<NUM>, such as the width and/or length of the drain and/or source, may be configured to provide a weighted output.

The embodiments described herein may be used to drive transmission lines with peak-to-peak voltages greater than the maximum voltage that a transistor can withstand for a given fabrication node. Thanks to such line drivers, designers of electronic circuits may have the freedom to choose fabrication nodes that can provide a data rate sufficient for the specific application. For example, the embodiments described herein may be used to drive transmission lines at data rates exceeding 20Gbit/s, 25Gbit/s, 30Gbit/s, 35Gbit/s, 40Gbit/s, 45Gbit/s, 50Gbit/s, 55Gbit/s or 60Gbit/s.

Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Use of ordinal terms such as "first", "second", "third", etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Claim 1:
A circuit (<NUM>) comprising:
a first transistor (M1) having a control terminal and a first output terminal;
a second transistor (M3) having a second output terminal coupled to the first output terminal;
a driving stage connected to the control terminal, the driving stage comprising a first driver (D1) having a first speed and a second driver (D1') having a second speed slower than the first speed,
wherein the control terminal is a first control terminal and the driving stage is a first driving stage, and characterised by: further comprising:
a third transistor (M2) having a third output terminal and a second control terminal;
a fourth transistor (M4) having a fourth output terminal coupled to the third output terminal; and
a second driving stage connected to the second control terminal, the second driving stage comprising a third driver (D2) having a third speed and a fourth driver (D2') having a fourth speed slower than the third speed.