Patent Description:
Semiconductor devices, in particular power semiconductor devices, may comprise electrical interconnections which need to be able to carry a large electrical current and/or withstand a high voltage. This requirement for example affects an interconnection between a load electrode of a power semiconductor die and a substrate like e.g. a leadframe, a direct copper bond (DCB), a direct aluminum bond (DAB), an active metal brazing (AMB), etc. One possible interconnection technique comprises sintering the semiconductor die to the substrate using a dedicated sintering metal layer. The specific material for the sintering metal layer may for example be chosen based on its high electrical and thermal conductivity, low processing temperature, high reliability, low cost, etc. Manufacturing of such an interconnection comprising a sintering metal layer may comprise depositing a stack of different metals on the semiconductor substrate beneath the sintering metal layer. The metal layers of this stack may for example be configured as diffusion barrier layer, inter-adhesion layer, etc. Furthermore, the metal stack may need to be patterned in order to define metallization areas on the chip. This patterning process should not be too time consuming in order to save costs, but it should also produce clean sidewall profiles and avoid undercuts in the patterned metal stack which otherwise could pose reliability risks due to their potential for trapping humidity. Improved methods for fabricating semiconductor devices as well as improved semiconductor devices may help with solving these and other problems.

<CIT> discloses an example of a method for fabricating a semiconductor device. The method comprises depositing a barrier layer on a substrate; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and forming a photoresist layer over the separation layer. The conductive layer may comprise sublayers. The barrier layer and the separation layer may be wet etched and the conductive layer may be dry etched.

The problem on which the invention is based is solved by the features of the independent claims. Further advantageous examples are described in the dependent claims.

Various aspects pertain to a method for fabricating a semiconductor device, the method comprising: depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.

Various aspects pertain to a semiconductor device, comprising: a semiconductor substrate, a TiW layer arranged on the semiconductor substrate, a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.

The accompanying drawings illustrate examples and together with the description serve to explain principles of the disclosure. Other examples and many of the intended advantages of the disclosure will be readily appreciated as they become better understood by reference to the following detailed description. Identical reference numerals designate corresponding similar parts.

In the following detailed description, directional terminology, such as "top", "bottom", "left", "right", "upper", "lower" etc., is used with reference to the orientation of the Figure(s) being described. Because components of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only.

In addition, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically noted otherwise or unless technically restricted. Also, the term "exemplary" is merely meant as an example, rather than the best or optimal.

The examples of a semiconductor device may comprise various types of semiconductor chips or circuits incorporated in the semiconductor chips, among them AC/DC or DC/DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, power integrated circuits, chips with integrated passives, etc..

The semiconductor chip(s) can be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, GaN, or from any other semiconductor material, and, furthermore, may contain one or more of inorganic and organic materials that are not semiconductors, such as for example insulators, plastics or metals.

The semiconductor chips may have contact pads (or electrodes) which allow electrical contact to be made with the integrated circuits included in the semiconductor chips. The electrodes may be arranged all at only one main face of the semiconductor chips or at both main faces of the semiconductor chips. They may include one or more electrode metal layers which are applied to the semiconductor material of the semiconductor chips. The electrode metal layers may be manufactured with any desired geometric shape and any desired material composition.

The notation XY refers to an alloy of X including at least Y as a further component. In particular, it may refer to an alloy of X including Y as a sole residual component (i.e. a closed composition). That is, in the second case, the notation XY means that the alloy XY has a composition consisting of X (of the percentage in weight of X) and Y (of the percentage in weight of Y), the balance being only inevitable elements. The notation XYZ. has an analogous meaning, i.e. an "open composition" or a "closed composition" with X, Y, Z. forming the sole constituents of the alloy (except inevitable elements).

<FIG> shows an exemplary semiconductor device <NUM> comprising a semiconductor substrate <NUM>, a TiW layer <NUM>, a Ti layer <NUM>, a Ni alloy layer <NUM>, and an Ag layer <NUM>.

The Ni alloy layer <NUM> may comprise an alloy of nickel and another suitable element. NiV, NiSi and NiN are examples of suitable alloys, though it is contemplated that other nickel alloys might also be suitable. For simplicity, an embodiment utilizing a NiV layer will be described from this point forward.

The TiW layer <NUM> is arranged on the semiconductor substrate <NUM>, e.g. on a first main side <NUM>. The Ti layer <NUM> is arranged on the TiW layer <NUM>, in particular directly on the TiW layer <NUM>. The NiV layer <NUM> is arranged on the Ti layer <NUM>, in particular directly on the Ti layer <NUM>. The Ag layer <NUM> is arranged on the NiV layer <NUM>, in particular directly on the NiV layer <NUM>.

The TiW layer <NUM>, the Ti layer <NUM>, the NiV layer <NUM>, and the Ag layer <NUM> comprise respective side faces <NUM>, <NUM>, <NUM>, <NUM> which may be arranged at an angle with respect to the first main side <NUM> of the semiconductor substrate. For example, one or more of the side faces <NUM>, <NUM>, <NUM>, <NUM> may be arranged essentially perpendicular with respect to the first main side <NUM>.

The side faces <NUM> of the Ag layer <NUM> and the side faces <NUM> of the NiV layer <NUM> are fabricated by a wet etching process. In other words, the side faces <NUM>, <NUM> comprise a surface structure and/or a microstructure that is fabricated by a wet etching process. The side faces <NUM> of the Ti layer <NUM> and the side faces <NUM> of the TiW layer <NUM> are fabricated by a dry etching process. In other words, the side faces <NUM>, <NUM> comprise a surface structure and/or a microstructure that is fabricated by a dry etching process.

The semiconductor substrate <NUM> may for example comprise a semiconductor wafer, a semiconductor panel, or a singulated semiconductor die. The semiconductor substrate <NUM> may have any suitable thickness measured perpendicular to the first main side <NUM>.

According to an example, the semiconductor device <NUM> comprises a dielectric layer arranged between the semiconductor substrate <NUM> and the TiW layer <NUM>. The dielectric layer may for example comprise or consist of a polymer, e.g. an imide. The TiW layer <NUM> may be arranged at least partially directly on the dielectric layer.

The TiW layer <NUM> may comprise Ti and W or it may completely consist of Ti and W, except for unavoidable contaminants. The TiW layer <NUM> may comprise any suitable ratio of Ti to W. Likewise, the Ti layer <NUM> may comprise or consist of Ti, except for unavoidable contaminants. The NiV layer <NUM> may comprise or consist of Ni and V in any suitable ratio and it may comprise unavoidable contaminants. The Ag layer <NUM> may comprise or consist of Ag and it may also comprise unavoidable contaminants.

The layers <NUM>, <NUM>, <NUM>, and <NUM> may have any suitable thickness measured perpendicular to the first main side <NUM>. According to an example, the TiW layer <NUM> has a thickness in the range of <NUM> to <NUM>, e.g. about <NUM>. The Ti layer <NUM> may for example have a thickness in the range of <NUM> to <NUM>, e.g. about <NUM>. The NiV layer <NUM> may for example have a thickness in the range of <NUM> to <NUM>, e.g. about <NUM>. The Ag layer <NUM> may for example have a thickness in the range of <NUM> to <NUM>, e.g. about <NUM>.

The Ag layer <NUM> may be configured as a sinter layer, meaning that the semiconductor device <NUM> may be electrically and mechanically coupled to a substrate by sintering the Ag layer <NUM> to the substrate. The Ag layer <NUM> may essentially be comprised of an Ag film deposited on the NiV layer <NUM>. The Ag layer <NUM> may comprise voids between individual Ag particles, wherein during sintering the semiconductor device <NUM> to a substrate, these voids shrink.

According to an example, all respective side faces <NUM>, <NUM>, <NUM>, <NUM> are essentially coplanar (i.e. all side faces <NUM>, <NUM>, <NUM>, <NUM> on the left side in <FIG> are essentially coplanar and all side faces <NUM>, <NUM>, <NUM>, <NUM> on the right side in <FIG> are essentially coplanar). According to another example, one or more of the side faces <NUM>, <NUM>, <NUM>, <NUM> are not coplanar with the others. For example, the side faces <NUM>, <NUM> of the TiW layer <NUM> and the Ti layer <NUM> may be coplanar or almost coplanar with each other but not coplanar with the side faces <NUM>, <NUM> of the NiV layer <NUM> and the Ag layer <NUM>.

The metal layers <NUM>, <NUM>, <NUM>, and <NUM> may be part of a layer stack <NUM>. The layer stack <NUM> may have a center line <NUM> which is arranged perpendicular to the first main side <NUM> and which is also arranged essentially at the middle of each of the layers <NUM>, <NUM>, <NUM>, <NUM> or at least at the middle of the majority of the layers <NUM>, <NUM>, <NUM>, <NUM>.

According to an example, one or more of the side faces <NUM>, <NUM>, <NUM>, <NUM> are recessed towards the center line <NUM> with respect to the other side faces. In particular, an upper one of the side faces <NUM>, <NUM>, <NUM>, <NUM> (as seen from above the Ag layer <NUM>) may be recessed with respect to a lower one of the side faces <NUM>, <NUM>, <NUM>, <NUM>. For example, the side faces <NUM> of the NiV layer <NUM> may be recessed towards the center line <NUM> with respect to the side faces <NUM> of the Ti layer <NUM>.

According to an example, the layer stack <NUM> is free of any undercut between the layers <NUM>, <NUM>, <NUM>, and <NUM>. In other words, no side face of a lower one of the layers <NUM>, <NUM>, <NUM>, <NUM> is recessed towards the center line <NUM> with respect to a respective side face of an upper one of the layers <NUM>, <NUM>, <NUM>, <NUM>. This means that the TiW layer <NUM> has at least the same lateral extension (measured perpendicular to the center line <NUM>) from the center line <NUM> as the Ti layer <NUM>; the Ti layer <NUM> has at least the same lateral extension from the center line <NUM> as the NiV layer <NUM>; the NiV layer <NUM> has at least the same lateral extension from the center line <NUM> as the Ag layer <NUM>.

As mentioned above, the TiW layer <NUM> and Ti layer <NUM> are patterned by dry etching, whereas the NiV layer <NUM> and the Ag layer <NUM> are patterned by wet etching. One advantage of this two-step etching scheme may be that different metal materials may exhibit different etching rates which may make it difficult or impossible to obtain a smooth side face profile (in particular a side face profile free of any undercuts) in only one single etching process. By using a wet etching process for patterning the upper layers (NiV layer <NUM> and Ag layer <NUM>) and using a subsequent dry etching process for patterning the lower layers (TiW layer <NUM> and Ti layer <NUM>) however an optimal side face profile free of any undercuts can be obtained.

<FIG> shows a semiconductor device <NUM> which may be similar to or identical with the semiconductor device <NUM>. In the semiconductor device <NUM>, the NiV layer <NUM> and the Ag layer <NUM> are recessed towards the center line <NUM> with respect to the TiW layer <NUM> and the Ti layer <NUM>. This offset between the NiV layer <NUM> and Ag layer <NUM> on the one hand and the TiW layer <NUM> and Ti layer <NUM> on the other hand may for example be due to the fact that two different etching processes were used to pattern the layers <NUM>, <NUM> and <NUM>, <NUM>. As mentioned further above, the NiV layer <NUM> and Ag layer <NUM> may e.g. be patterned with a wet etching process and the TiW layer <NUM> and Ti layer <NUM> may be patterned with a dry etching process.

According to an example, the offset between the NiV layer <NUM> and Ag layer <NUM> on the one hand and the TiW layer <NUM> and Ti layer <NUM> on the other hand has a length l of 1pm or more, or <NUM> or more, or 3pm or more, or 4pm or more, or <NUM> or more.

According to an example, the semiconductor device <NUM> comprises a further offset between the TiW layer <NUM> and the Ti layer and/or a further offset between the NiV layer <NUM> and the Ag layer <NUM>. The further offsets may have a shorter length than the length l of the offset between the Ti layer <NUM> and the NiV layer <NUM> shown in <FIG>. For example, the further offsets may have a length of 1pm or less, or <NUM> or less, or <NUM> or less.

According to an example, an exposed part of an upper side <NUM> of the Ti layer <NUM> may have a microstructure essentially fabricated by a wet etching process. The exposed part of the upper side <NUM> is that part of the upper side <NUM> that is not covered by the NiV layer <NUM>. The microstructure of the exposed part of the upper side <NUM> may be formed while wet etching the NiV layer <NUM> and Ag layer <NUM>.

<FIG> shows a semiconductor device <NUM> according to the present invention. In the semiconductor device <NUM>, the side faces <NUM> of the NiV layer <NUM> are arranged at an angle α<NUM> with respect to the first main side <NUM>, wherein the angle α<NUM> is smaller than <NUM>°. Furthermore, the side faces <NUM> of the Ag layer <NUM> are arranged at an angle α<NUM> with respect to the first main side <NUM>, wherein the angle α<NUM> is also smaller than <NUM>°. The side faces <NUM>, <NUM> of the TiW layer <NUM> and Ti layer <NUM> on the other hand are arranged perpendicular with respect to the first main side <NUM>.

The side faces <NUM>, <NUM> of the NiV layer <NUM> and Ag layer <NUM> being sloped and the side faces <NUM>, <NUM> of the TiW layer <NUM> and Ti layer <NUM> being vertical may be due to the different etching techniques used to pattern the layers <NUM>, <NUM> and <NUM>, <NUM>. A wet etching process is an isotropic patterning process which may produce sloped side faces, whereas dry etching is an anisotropic patterning process which may produce vertical or almost vertical side faces.

The angles α<NUM> and α<NUM> need not necessarily be identical. However, it is also possible that they are identical or almost identical. The angles α<NUM> and α<NUM> may have any value, dependent on the specific etching parameters used, e.g. <NUM>° or less, or <NUM>° or less, or <NUM>° or less, or <NUM>° or less.

According to an example, there is an offset between the side faces <NUM> and <NUM>, e.g. a small offset of no more than <NUM> or no more than 1pm, or no more than <NUM>. However, it is also possible that the side faces <NUM> and <NUM> are essentially coplanar. Furthermore, the side faces <NUM>, <NUM> need not necessarily be planar and may e.g. have a bent shape.

<FIG> show the semiconductor device <NUM> in various stages of fabrication, according to an exemplary method for fabricating semiconductor devices. A similar method may be used to fabricate the semiconductor devices <NUM> and <NUM>.

As shown in <FIG>, the semiconductor substrate <NUM> is provided. This may comprise arranging the semiconductor substrate <NUM> on a temporary carrier, e.g. a tape. According to an example, a dielectric layer like an imide layer (not shown in <FIG>) may be deposited on the first main side <NUM>. The dielectric layer may be patterned in order to provide an electrical contact to e.g. transistor structures of the semiconductor substrate <NUM>. According to an example, the first main side <NUM> is a backside of the semiconductor substrate <NUM> and according to another example, it is a front side of the semiconductor substrate <NUM>.

As shown in <FIG>, the layer stack <NUM> is deposited on the first main side <NUM> of the semiconductor substrate <NUM>. The individual layers <NUM>, <NUM>, <NUM>, and <NUM> of the layer stack <NUM> may e.g. be deposited in individual, subsequent processes.

One or more of the layers <NUM>, <NUM>, and <NUM> may e.g. be deposited using a sputtering process, an electroplating process, a vapor deposition process, or any other suitable deposition technique. The Ag layer <NUM> may e.g. be deposited using a spraying process, a cold plasma assisted deposition process, or any other suitable deposition technique.

The layer stack <NUM> may be deposited such that it completely covers the first main side <NUM> of the semiconductor substrate <NUM> or it may be deposited such that it covers the first main side <NUM> only partially (e.g. by using an appropriate mask).

As shown in <FIG>, a photoresist layer <NUM> is deposited on the Ag layer <NUM>. The photoresist layer <NUM> may be applied such that it completely covers the Ag layer <NUM>. Any suitable type of photoresist may be used, e.g. IX335.

As shown in <FIG>, the photoresist layer <NUM> may be patterned using any suitable photolithography technique.

As shown in <FIG>, a wet etching process is used to etch the Ag layer <NUM> and the NiV layer <NUM>. The wet etching chemistry <NUM> may be chosen such that the Ag layer <NUM> and NiV layer <NUM> are readily etched, whereas the Ti layer <NUM> and TiW layer <NUM> are not readily etched. According to an example, the wet etching chemistry <NUM> comprises a solution comprising phosphoric acid, acetic acid and nitric acid. One exemplary wet etching solution comprises <NUM>% phosphoric acid, <NUM>% nitric acid, <NUM>% acetic acid and <NUM>% water.

The wet etching process may essentially be an isotropic patterning process. Therefore, the Ag layer <NUM> and/or NiV layer <NUM> may form an undercut under the photoresist layer <NUM>.

As shown in <FIG>, a dry etching process is used to etch the Ti layer <NUM> and TiW layer <NUM>. Dry etching may e.g. be done with an etching gas <NUM> comprising chlorine and fluorine (e.g. Cl<NUM> and SF<NUM>). The dry etching process may e.g. comprise reactive ion etching or any other suitable technique. In particular, particles of the etching gas <NUM> may be accelerated towards the first main side <NUM>, thereby anisotropically etching the Ti layer <NUM> and TiW layer <NUM>. Since the Ag layer <NUM> and NiV layer <NUM> are covered by the photoresist layer <NUM>, no dry etching is performed on these layers, according to an example.

The same photoresist layer <NUM> may be used for both the wet etching process shown in <FIG> and the dry etching process shown in <FIG>. However, it is also possible that the photoresist <NUM> is removed after the wet etching process and new photoresist <NUM> is applied in a further photolithography process, prior to the dry etching process.

According to an example, the dry etching process is performed within <NUM> hours or less of the wet etching process, or within <NUM> hours or less, or within <NUM> hour or less.

According to an example, the dry etching process is stopped once the dielectric layer beneath the TiW layer <NUM> is reached. This may e.g. be determined by spectrographically checking for particles of the dielectric layer (e.g. imides in the case that the dielectric layer is an imide layer) are alternatively for particles of the semiconductor substrate <NUM> in the exhaust gas of the etching chamber. The etching apparatus may be equipped with a spectrometer for this purpose. The etching process may be stopped automatically once the particles of the dielectric layer or the semiconductor substrate <NUM> are detected by the spectrometer.

According to a further non-claimed method for fabricating a semiconductor device, the wet etching process as described with respect to <FIG> is used for etching the Ag layer <NUM>, the NiV layer <NUM>, and also the Ti layer <NUM>. The dry etching process as described with respect to <FIG> is only used for etching the TiW layer <NUM>. In this case, tight control of the etching times may be necessary in order to obtain satisfying etching results.

According to yet another non-claimed method for fabricating a semiconductor device, the TiW layer <NUM> and Ti layer <NUM> are deposited on the semiconductor substrate <NUM> as described with respect to <FIG>. Consequently, photoresist <NUM> is deposited on the Ti layer <NUM>, a lithography process is performed and the TiW layer <NUM> and Ti layer <NUM> are dry etched. The Ti layer <NUM> may be striped, e.g. by using hydrofluoric acid, in order to preserve a clean TiW surface (avoid contact of TiW with photoresist). Afterwards, a new Ti layer <NUM>, the NiV layer <NUM> and the Ag layer <NUM> may be deposited and patterned by wet etching.

<FIG> is a flow chart of a method <NUM> for fabricating a semiconductor device in accordance with the present invention. The method <NUM> is used for fabricating the semiconductor devices <NUM>.

The method <NUM> comprises at <NUM> an act of depositing a TiW layer on a semiconductor substrate, at <NUM> an act of depositing a Ti layer on the TiW layer, at <NUM> an act of depositing a Ni alloy layer on the Ti layer, at <NUM> an act of depositing an Ag layer on the Ni alloy layer, at <NUM> an act of at least partially covering the Ag layer with photoresist, at <NUM> an act of wet etching the Ag layer and the Ni alloy layer, and at <NUM> an act of dry etching the Ti layer and the TiW layer.

The wet etching at <NUM> may for example be done using a solution comprising phosphoric acid, acetic acid and nitric acid. The dry etching at <NUM> may for example be done using an etching gas comprising chlorine and fluorine.

Claim 1:
A method for fabricating a semiconductor device, the method comprising:
depositing a TiW layer (<NUM>) on a main side (<NUM>) of a semiconductor substrate (<NUM>),
depositing a Ti layer (<NUM>) on the TiW layer,
depositing a Ni alloy layer (<NUM>) on the Ti layer,
depositing an Ag layer (<NUM>) on the Ni alloy layer,
at least partially covering the Ag layer with photoresist (<NUM>),
wet etching the Ag layer and the Ni alloy layer so that the Ag layer and the Ni alloy layer comprise side faces (<NUM>, <NUM>) which are arranged at an angle (α1, α2) smaller than <NUM>° with respect to the main side, and
dry etching the Ti layer and the TiW layer so that the Ti layer and the TiW layer comprise side faces (<NUM>, <NUM>) which are perpendicular to the main side.