Patent Description:
Some types of transistor devices, such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistor) include an internal diode, which is often referred to as body diode, between a first load node (drain node) and a second load node (source node) of the transistor. In many types of electronic circuits MOSFETs are operated in such a way that the respective body diode is forward biased for a certain time period, so as to conduct a current.

Forward biasing the body diode is associated with the generation of a charge carrier plasma that includes first type and second type (p and n) charge carriers inside the body diode. When the body diode is reverse biased, so that the body diode blocks, this charge carrier plasma is removed and an output capacitance of the transistor device is charged. Removing the charge carrier plasma and charging the output capacitance is associated with a current, which may also be referred to as charging current. This charging current is associated with losses, which are sometimes referred to as reverse recovery losses. Basically, the higher the voltage across a current path in which the charging current flows, the higher the losses associated with removing the charge carrier plasma from the body diode and the charging the output capacitance.

<CIT> discloses a half-bridge circuit with a high-side switch and a low-side switch that each include several transistors connected in parallel. A freewheeling circuit is connected in parallel to each of the high-side switch and low-side switch. Each of the freewheeling circuits includes a series circuit with a diode and a MOSFET connected in series with the diode. Each of the diodes can be activated or deactivated by activating or deactivating the MOSFET connected in series thereto.

There is a need to reduce losses in an electronic circuit that includes a transistor device, in particular a superjunction transistor device.

One embodiment relates to an electronic circuit according to claim <NUM>.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

<FIG> shows one example of an electronic circuit that includes a transistor device <NUM>, a drive circuit <NUM> configured to drive the transistor device <NUM>, and a biasing circuit <NUM>. The transistor device <NUM> includes a drive input that is configured to receive a drive voltage Vgs1 and a load path D-S between a first load node D and a second load node S. In the example illustrated in <FIG>, the drive input configured to receive the drive voltage Vgs1 includes a control node G and the second load node S. This, however, is only an example. According to another example (not illustrated) the drive input may include the control node G and a further control node (which is sometimes referred to as Kelvin source).

According to one example, the transistor device is a MOSFET. In this case, the first load node D is a drain node, the second load node S is a source node, and the control node G is a gate node of the MOSFET. The drive input may be formed by the gate node G and the source node S. In the following, although the transistor device <NUM> is not restricted to be implemented as a MOSFET, the terms drain node D, source node S, and gate node G will be used to denote the first and second load nodes and the control node, respectively, of the transistor device <NUM>.

The transistor device includes an internal diode (which is also referred to as body diode in the following) between the drain node D and the source node S of the transistor device. For the purpose of illustration in <FIG>, this internal diode is represented by the circuit symbol of a diode connected between the drain node D and the source node S of the transistor device <NUM>. Furthermore, the transistor device includes an internal output capacitance, which includes a capacitance between the drain node D and the source node S (which is usually referred to as drain-source capacitance) and a capacitance between the gate node G and the drain node D (which is usually be referred to as gate-drain capacitance). This output capacitance is represented by the circuit symbol of a capacitor connected between the drain node D and the source node S of the transistor device <NUM> (for the ease of illustration, this capacitor symbol is omitted in the remainder of the drawings).

The transistor device <NUM> can be operated in different operating states, wherein these operating states are dependent on a voltage level of the drive voltage Vgs1 and a polarity of a load path voltage (drain-source voltage) Vds, which is a voltage between the drain node D and the source node S.

An operating state of the transistor device in which the drain-source voltage has a polarity that reverse biases the body diode is referred to as forwarding biased state of the transistor device <NUM>. In the forward biased state, the transistor device <NUM> (i) conducts a current when the transistor device is in the on-state, wherein this operating state is also referred to as forward conducting state; or (ii) blocks when the transistor device is in the off-state, wherein this operating state is referred to as forward blocking state in the following. The output capacitance of the transistor <NUM> is charged when the transistor device is in the forward blocking state and the drain-source voltage Vds increases.

In the electronic circuit illustrated in <FIG>, the drive voltage Vgs1 is generated by the drive circuit <NUM> based on a supply voltage Vsup received by the drive circuit <NUM> and dependent on an input signal Sin1. According to one example, the drive circuit <NUM> is configured to generate the drive voltage Vgs1 such that the drive voltage Vgs1 essentially equals the supply voltage Vsup, so that the transistor device <NUM> switches on, when the input signal Sin1 indicates that it is desired to switch on the transistor device <NUM>. Furthermore, the drive circuit is configured to generate the drive voltage Vgs <NUM> such that the drive voltage Vgs1 and is essentially zero, so that the transistor device <NUM> switches off, when the input signal Sin1 indicates that it is desired to switch off the transistor device <NUM>.

According to one example, the drive circuit <NUM> receives the supply voltage Vsup between a first supply node <NUM> and a second supply node <NUM>, wherein the second supply node <NUM> is also referred to as drive circuit ground node (or briefly as ground node) in the following. Further, the drive circuit <NUM> provides the drive voltage Vgs1 at an output node <NUM>. According to one example, the supply voltage Vsup and the drive voltage Vgs1 are both referenced to the ground node <NUM>, so that the drive voltage Vgs1 is available between the output node <NUM> and the ground node <NUM> of the drive circuit <NUM>.

According to one example, the supply voltage Vsup is between <NUM> V and <NUM> V, in particular between <NUM> V and <NUM> V.

This bias circuit <NUM> is connected in parallel with the load path D-S of the transistor device <NUM> and is configured to apply a bias voltage Vbias to the load path D-S of the transistor device <NUM>. In the example illustrated in <FIG>, the biasing circuit <NUM> includes a bias voltage circuit <NUM> that provides the bias voltage Vbias, an electronic switch <NUM>, and a rectifier element <NUM>. The bias voltage circuit <NUM> provides the bias voltage Vbias at an output <NUM>, <NUM>. The output <NUM>, <NUM> of the bias voltage circuit <NUM>, the electronic switch <NUM> and the rectifier element <NUM> are connected in series, wherein the bias voltage Vbias is applied to the load path D-S of the transistor device <NUM> when the electronic switch <NUM> is switched on. The electronic switch <NUM> switches on or off dependent on a drive signal S31 received at an input of the electronic switch <NUM>. An example for driving this electronic switch <NUM> is explained in detail herein further below.

According to one example, the rectifier element <NUM> is a diode. According to one example, the diode is a silicon carbide (SiC) based diode. The transistor device is a silicon-based transistor device, for example.

A polarity of the bias voltage Vbias is such that the bias voltage Vbias reverse biases the body diode of the transistor device <NUM> and charges the output capacitance when the transistor device <NUM> is in the off-state. Applying the bias voltage Vbias to the load path D-S of the transistor device <NUM> has the effect that a charge carrier plasma is removed from the transistor device <NUM>, when before applying the bias voltage Vbias the body diode was forward biased. Moreover, applying the bias voltage Vbias has the effect that the output capacitance of the transistor device <NUM> between the drain node D and the source node S is charged. This is explained in detail herein further below.

According to one example, as illustrated in <FIG>, the bias voltage Vbias is based on the supply voltage Vsup. That is, the bias voltage circuit <NUM> receives the supply voltage Vsup at an input <NUM>, <NUM> and generates the bias voltage Vbias based on the supply voltage Vsup at the output <NUM>, <NUM>. Examples of the bias voltage source <NUM> are explained herein further below.

By using the supply voltage Vsup to generate the bias voltage Vbias only one external voltage source for both driving the transistor device <NUM> and biasing the load path D-S of the transistor device <NUM> is required.

Referring to <FIG> and <FIG>, a circuit path that includes the load path D-S of the transistor device <NUM> and the bias circuit <NUM> includes at least one inductor that is connected in series with the load path D-S of the transistor device <NUM>, the rectifier element <NUM>, and the electronic switch <NUM>. The at least one inductor may include one inductor <NUM> in the bias circuit <NUM>, as illustrated in <FIG>. According to another example, the at least one inductor includes several inductors <NUM>-<NUM> at different positions of the circuit path including the bias circuit <NUM> and the load path D-S of the transistor device <NUM>. The at least one inductor <NUM>, <NUM>-<NUM> can be implemented as a discrete device added to the circuit path. Alternatively, the at least one inductor can be formed by wires that connect the individual devices in the bias circuit <NUM> and/or that connect the bias circuit <NUM> to the drain and source node D, S of the transistor device <NUM>. The wires may be implemented in such a way that the circuit path of the bias circuit <NUM> and the transistor device <NUM> includes a desired inductance. According to one example, the inductance provided by the at least one inductor <NUM>, <NUM>-<NUM> is between <NUM> nanohenries (nH) and <NUM> nH, in particular between <NUM> nH and <NUM> nH.

The at least one inductor <NUM>, <NUM>-<NUM> has a boost effect in such a way that after switching on the electronic switch <NUM> the load path voltage Vds of the transistor device <NUM> may increase to a voltage level that is higher than a voltage level of the bias voltage Vbias. This is explained in the following.

When the electronic switch <NUM> switches on and the bias voltage Vbias is applied between the drain node D and the source node S of the transistor device <NUM> the output capacitance of the transistor device <NUM> is charged to a certain extent. Charging the output capacitance is associated with a charging current , wherein this charging current decreases as the output capacitance charges and the load path voltage Vds of the transistor device <NUM> increases. The at least one inductor <NUM>, <NUM>-<NUM>, however, counteracts such decrease of the charging current by increasing the load path voltage Vds to a voltage level higher than the bias voltage Vbias. This has the effect that the output capacitance of the transistor device <NUM> is charged further.

According to one example, the inductance of the at least one inductor <NUM>, <NUM>-<NUM> is selected such that the voltage level the load path voltage Vds reaches, after switching on the electronic switch <NUM>, is at least to <NUM> times, at least <NUM> times, at least <NUM> times, or at least <NUM> times the voltage level of the bias voltage Vbias. In the example in which the bias voltage Vbias equals the supply voltage Vsup, the at least one inductor <NUM>, <NUM>-<NUM> has the effect that the voltage Vds applied to the load path D-S is at least <NUM> times, at least <NUM> times, at least <NUM> times, or at least <NUM> times the voltage level of the supply voltage Vbias.

It should be noted that in a MOSFET, such as a superjunction MOSFET, the output capacitance is highly non-linear and is dependent on the voltage level of the load path voltage Vds that is applied to the load path D-S of the transistor device <NUM> when the transistor device <NUM> is in the off-state. "Non-linear" in this connection means that the output capacitance decreases as the load path voltage Vds increases. In a superjunction MOSFET, there is a range of the load path voltage Vds within which the output capacitance decreases for several orders of magnitude as the load path voltage Vds increases. This voltage range may range over several volts. A voltage level at an upper end of this voltage range is referred to as depletion voltage in the following. A significant portion, such as between <NUM>% and <NUM>%, of an overall charge that can be stored in the output capacitance is already stored when the load path voltage Vds reaches the depletion voltage. It may therefore be desirable to design the bias circuit <NUM> such that the voltage level of the drain source-voltage Vds generated by the bias circuit <NUM> essentially equals the depletion voltage of the transistor device <NUM>. The depletion voltage of the transistor device <NUM> is explained in detail herein further below.

Referring to the above, the drain-source voltage Vds generated by the bias circuit <NUM> is defined by the bias voltage Vbias and the optional at least one inductor <NUM>, <NUM>-<NUM>. Referring to the above, when using the at least one inductor <NUM>, <NUM>-<NUM>, the bias voltage Vbias can be lower than the drain-source voltage that is desired to be applied to the load path D-S. In particular, when using the at least one inductor <NUM>, <NUM>-<NUM>, the bias voltage Vbias can be lower than the depletion voltage of the transistor device <NUM>.

According to one example, the bias voltage Vbias is selected from between 12V and 25V.

According to one example, illustrated in <FIG>, the bias voltage Vbias equals the supply voltage Vsup. In this case, the bias voltage circuit <NUM> simply includes two connectors that connect the supply voltage Vsup to the bias circuit <NUM>. According to one example, when the bias voltage Vbias is generated such it essentially equals the supply voltage Vsup, the circuit path with the biasing circuit <NUM> and the load path D-S includes the at least one inductor <NUM>, <NUM>-<NUM> explained with reference to <FIG> and <FIG>.

According to another example, the bias voltage circuit <NUM> is configured to generate the bias voltage Vbias based on the supply voltage Vsup such that the bias voltage Vbias is higher than the supply voltage Vsup. One example of a bias voltage circuit <NUM> that is configured to generate the bias voltage Vbias such that it is higher than the supply voltage Vsup is illustrated in <FIG>.

The bias voltage circuit <NUM> illustrated in <FIG> is a charge pump circuit that is configured to provide the bias voltage Vbias at an output capacitor <NUM> connected between output nodes <NUM>, <NUM> of the bias voltage circuit <NUM>. The charge pump circuit illustrated in <FIG> includes an integrated drive circuit <NUM> that receives the supply voltage Vsup between a first supply input VCC and a second supply input GND. According to one example, this drive circuit <NUM> is an integrated drive circuit of the type 1EDN8511B available from Infineon Technologies AG, Munich.

The drive circuit <NUM> further includes an output OUT and is configured to either connect the first supply input VCC or the second supply input GND to the output OUT, so that a voltage between the output OUT and the second supply node GN either equals the supply voltage Vsup or is zero. A capacitor <NUM> connected between the first supply input VCC and the second supply input GND is optional and serves to stabilize the supply voltage received by the drive circuit <NUM>. A second input node <NUM> and the second output node <NUM> of the bias voltage circuit are connected and connected to the second supply node of the integrated circuit <NUM>. The supply voltage Vsup and the bias voltage Vbias are therefore referenced to the same circuit node.

The output OUT of the drive circuit <NUM> is connected to a first circuit node of a charge pump capacitor <NUM>. A second circuit node of the charge pump capacitor <NUM> is connected to the first input node <NUM> via a first rectifier element <NUM>. The first rectifier element is a diode, for example. The first rectifier element <NUM> is connected between the first input node <NUM> and the second circuit node of the charge pump capacitor <NUM> such that the first charge pump capacitor <NUM> can be charged to the supply voltage Vsup via the first rectifier element <NUM> when the first circuit node of the charge pump capacitor <NUM> is connected to the second supply node GND via the drive circuit <NUM>.

When the first charge pump capacitor <NUM> has been charged and the drive circuit <NUM> connects the output OUT and, therefore, the first circuit node of the charge pump capacitor <NUM> to the first supply input VCC, the first charge pump capacitor <NUM> is discharged via a second rectifier element <NUM>, which is connected between the second circuit node of the charge pump capacitor <NUM> and the output capacitor <NUM>. The drive circuit <NUM> is configured to periodically connect the output OUT (i) to the second supply node GND, so that the charge pump capacitor <NUM> is charged, and (ii) the first supply input VCC, so that the charge pump capacitor <NUM> is discharged and the output capacitor <NUM> is charged. In this charge pump circuit, the output capacitor <NUM> (over several periods of the charge pumping process) is charged such that the bias voltage Vbias essentially equals twice the supply voltage Vsup.

The drive circuit <NUM> further includes a first drive input IN+ that is connected to the first input node <NUM> of the bias voltage circuit <NUM>, and a second drive input IN- that is connected to the output OUT of the integrated drive circuit <NUM> via a feedback circuit <NUM>, <NUM>. The feedback circuit <NUM>, <NUM> includes an RC circuit with a resistor <NUM> and a capacitor <NUM>, wherein the capacitor is connected between the second drive input IN- and the second supply input GND. In this configuration, the drive circuit <NUM> is configured to connect the output OUT to the second supply input GND, in order to charge the charge pump capacitor <NUM>, whenever a voltage between the second drive input IN- and the second supply input GND is higher than a predefined first voltage threshold. Further, the drive circuit <NUM> is configured to connect the first supply input VCC to the output OUT, in order to discharge the charge pump capacitor <NUM>, whenever the voltage at the second drive input IN- is below a predefined second voltage threshold. When the output OUT of the drive circuit <NUM> is connected to the first supply input VCC, the voltage at the second drive input IN- increases because the capacitor <NUM> is charged until the voltage reaches the predefined first threshold. When the voltage reaches the predefined threshold, the voltage at the output OUT goes low so that the capacitor <NUM> is again discharged. In this way, the voltage at the output OUT periodically changes between the supply voltage Vsup and zero, wherein a duration of one period is defined by the RC circuit. A difference between the first and second threshold, which defines a hysteresis of the switching operation, is between <NUM>. 5V and 2V, such as between 1V and <NUM>. 5V, for example.

<FIG> illustrates one example of the electronic circuit in greater detail. It should be noted that the bias voltage circuit <NUM> may be implemented in accordance with any of the examples explained herein before. Further, the biasing circuit <NUM> may include at least one inductor. Such inductor, however, is not illustrated in <FIG>.

In the example illustrated in <FIG>, the electronic switch <NUM> of the biasing circuit <NUM> is implemented as a transistor device. More specifically, in this example, the electronic switch <NUM> is implemented as a MOSFET, in particular an n-type enhancement MOSFET. This MOSFET includes an integrated body diode (not illustrated). The electronic switch <NUM> is connected in series with the rectifier element <NUM> such that the body diode of the MOSFET and the rectifier element <NUM> are connected in series in a back-to-back configuration.

According to one example, the MOSFET forming the electronic switch <NUM> is a low voltage MOSFET with a voltage blocking capability that is lower than the voltage blocking capability of the transistor device <NUM>. According to one example, the low voltage MOSFET has a voltage blocking of less than 120V or even less than 100V. The low voltage MOSFET may be implemented as a silicon based non-superjunction device.

Referring to <FIG>, the electronic circuit further includes a drive circuit <NUM> that is configured to drive the electronic switch <NUM> by generating the drive signal S31 received by the electronic switch <NUM>. In this example, the drive signal S31 is a drive voltage Vgs2 received between a gate node G and a source node S of the MOSFET forming the electronic switch <NUM>. In the following, the drive circuit <NUM> configured to drive the electronic switch <NUM> is also referred to as second drive circuit, and the drive circuit <NUM> configured to drive the transistor device <NUM> is also referred to as first drive circuit <NUM>.

According to one example, the second drive circuit <NUM> has a first supply input <NUM> that is connected to the first supply input <NUM> of the first drive circuit <NUM>, and a second supply input <NUM> connected to the source node of the MOSFET forming the electronic switch <NUM>. This source node S is connected to the second supply node <NUM> of the first drive circuit <NUM> via the diode <NUM> and the load path of the transistor device <NUM>. In this way, the second drive circuit <NUM> receives the supply voltage Vsup between the first and second supply node <NUM>, <NUM> each time the transistor device <NUM> is in the on-state. The drive circuit <NUM> may include a bootstrap circuit with a capacitor <NUM> and a diode <NUM> connected between the first and second supply nodes <NUM>, <NUM>. In this bootstrap circuit, the capacitor <NUM> is charged to a voltage level that essentially equals the supply voltage Vsup when the transistor device <NUM> is in the on-state.

According to one example, the second drive circuit <NUM> is configured to generate the second drive voltage Vgs2 such that the second drive voltage Vgs2 essentially equals the voltage provided by the bootstrap capacitor <NUM> when the second input signal Sin2 has a signal level that indicates that it is desired to switch on the electronic switch <NUM>, and is configured to generate the second drive voltage Vgs2 such that the second drive voltage Vgs2 is essentially zero when the second input signal Sin2 has a signal level that indicates that it is desired to switch off the electronic switch <NUM>. According to one example, the second drive voltage Vgs2 is available between an output node <NUM> and the second supply node <NUM> of the second drive circuit <NUM>.

According to one example illustrated in <FIG>, the first drive circuit <NUM> and the second drive circuit <NUM> include a common integrated drive circuit <NUM> which receives both the first input signal Sin1 and the second input signal Sin2, and which is configured to generate both the first drive voltage Vgs1 received by the transistor device <NUM>, and the second drive voltage Vgs2 received by the electronic circuit <NUM>. In the following, the drive circuit that drives both the transistor device <NUM> and the electronic switch <NUM> is referred to as common drive circuit <NUM>, <NUM> in the following. According to one example, this integrated drive circuit <NUM> included in the common drive circuit is an integrated circuit of the type 2EDF7275F, available from Infineon Technologies AG, Munich. In this type of integrated drive circuit <NUM> input nodes INB, INA that receive the first and second input signals Sin1, Sin2 and output nodes OUTB, OUTA at which the first and second drive voltages Vgs1, Vgs2 are available are galvanically isolated from each other.

Referring to <FIG>, the integrated drive circuit <NUM> includes a first supply input VDDB and the second supply input GNDB, wherein the supply voltage Vsup is received between these two supply inputs VDDB, GNDB. Optionally, a capacitor <NUM> that stabilizes the supply voltage received between these supply inputs VDDB, GNDB is connected between these supply inputs VDDB, GNDB. The first drive voltage Vgs1 is available between the first output node OUTB and the second supply node GNDB. Optionally, a resistor <NUM> is connected between the second output node OUTB and the gate node G of the transistor device <NUM>, wherein this resistor <NUM> serves to limit a gate current of the transistor device <NUM>.

The integrated drive circuit <NUM> is configured to generate the first drive voltage Vgs1 such that the first drive voltage Vgs1 essentially equals the supply voltage Vsup when the first input signal Sin1 indicates that it is desired to switch on the transistor device <NUM>. Further, the integrated drive circuit <NUM> is configured to generate the first drive voltage Vgs1 such that the first drive voltage Vgs1 is essentially zero when the second input signal Sin1 indicates that it is desired to switch off the transistor device <NUM>. According to one example, the first input signal Sin1 is a voltage between the first input node INB and an input reference node GNDI.

Referring to <FIG>, the integrated drive circuit <NUM> further includes a third supply input VDDA and the fourth supply input GNDA, wherein the bootstrap capacitor <NUM> is connected between the third and fourth supply inputs VDDA, VDDB and the bootstrap diode <NUM> is connected between the third supply input VDDA and the circuit node <NUM>, <NUM> at which the supply voltage Vsup is available.

The integrated drive circuit <NUM> is configured to generate the second drive voltage Vgs2 such that a voltage level of the second drive voltage Vgs2 essentially equals the voltage provided by the bootstrap capacitor <NUM> when the second input signal Sin2 indicates that it is desired to switch on the electronic switch <NUM>. Further, the integrated drive circuit <NUM> is configured to generate the second drive voltage Vgs2 such that the voltage level of the second drive voltage Vgs2 is essentially zero when the second input signal Sin2 indicates that it is desired to switch off the electronic switch <NUM>. According to one example, the second input signal Sin2 is a voltage between the second input node INA and the reference node GNDI.

The bias voltage circuit <NUM> is not illustrated in detail in <FIG>. This bias voltage circuit <NUM> may be implemented in accordance with any of the examples explained herein before. It should be noted in this regard that an output capacitor <NUM> which provides the bias voltage Vbias may also be used in a bias voltage circuit <NUM> of the type shown in <FIG>, which generates the bias voltage Vbias such that it essentially equals the supply voltage Vsup. The output capacitor <NUM> may include several sub-capacitors connected in parallel as illustrated in <FIG>.

According to one example illustrated in <FIG>, the electronic circuit further includes a further transistor device 1a which has a load path D-S connected in series with the transistor device <NUM>. In the following, the transistor device <NUM> is also referred to as first transistor device <NUM>, and the further transistor device 1a is also referred to as second transistor device 1a. The second transistor device 1a can be a transistor device of the same type as the first transistor device <NUM> or can be a transistor device of a different type. Just for the purpose of illustration, the circuit symbol of the second transistor device 1a illustrated in <FIG> is the circuit symbol of an n-type MOSFET. This, however, is only an example. The second transistor device 1a is not restricted to be implemented as an n-type MOSFET.

The first transistor device <NUM> and the second transistor device 1a, which have their load paths D-S connected in series, form a half-bridge. One way of operating this half-bridge is explained in the following.

For the purpose of illustration it is assumed that the half-bridge is connected to a voltage source providing a load supply voltage Vsupz, so that the load supply voltage Vsupz is received by the series circuit including the load paths of the first transistor device <NUM> and the second transistor device 1a. Further, for the purpose of illustration it is assumed that an inductive load Z is connected in parallel with the load path D-S of the first transistor device <NUM> and is driven by the half-bridge. This inductive load Z can be any type of inductive load, such as a motor winding, a magnetic valve, an inductor in a switched mode power supply (SMPS), or the like. The inductive load Z includes at least one inductor. In addition to the inductor, the inductive load may include any kind of additional electronic devices.

According to one example, the second transistor device 1a is operated in a PWM (pulse-width modulated) fashion. That is, the second transistor device 1a is alternatingly switched on and off. This is illustrated in <FIG> which schematically illustrates the drive voltage Vgs1a received by the second transistor device 1a. Just for the purpose of illustration, in <FIG>, a high signal level of the drive voltage Vgs1a represents a signal level that switches on the second transistor device 1a, and a low signal level of the drive voltage Vgs1a represents a signal level that switches off the second transistor device 1a. When the second transistor device 1a is switched on (is in an on-state), a load voltage Vz, which is a voltage across the inductive load Z, essentially equals the load supply voltage Vsupz. For the purpose of illustration it is assumed that a load current Iz flows through the inductive load Z when the second transistor device 1a is switched on.

When the second transistor device 1a switches off, the load current Iz continues to flow, forced by the inductive load Z. In this operating state, the first transistor device <NUM> acts as a freewheeling element that takes over the load current Iz. In order to reduce conduction losses, the first transistor device <NUM> may be switched on during those time periods in which the second transistor device 1a is switched off. The drive voltage Vgs1 received by the first transistor device <NUM> is also schematically illustrated in <FIG>, wherein a high signal level of the drive voltage Vgs1 represents an on-state and a low signal level of the drive voltage Vgs1 represents an off-state of the first transistor device <NUM>.

In order to avoid a cross current, there may be a first dead time Td1 between a time instance at which the second transistor device Vgs1a switches off, and a time instance at which the first transistor device Vgs1 switches on. Further, there may be a second dead time Td2 between a time instance at which the first transistor device <NUM> switches off and the second transistor device 1a switches on. During those dead times Td1, Td2 the load current Iz flows through the body diode of the first transistor device <NUM>.

In a conventional half-bridge circuit, that is, a half-bridge circuit in which the first transistor device <NUM> does not have a biasing circuit <NUM> connected thereto, the load supply voltage Vsupz is applied to the load path D-S of the first transistor device <NUM> at the end of the second dead time Td2, wherein the load supply voltage Vsupz reverse biases the body diode and charges the output capacitance of the first transistor device <NUM>. Referring to the above, charging the output capacitance is associated with a charging current and, therefore with losses. These losses are dependent on a voltage across a current path in which the charging current flows. In a conventional half-bridge circuit, this current path includes the load paths of the first and second transistor device <NUM>, 1a, and the voltage across this current path is the load supply voltage Vsupz. Dependent on the specific type of application, this load path voltage Vsupz is between <NUM> V and several <NUM> V, such as between <NUM> V and <NUM> V for example.

The biasing circuit <NUM> helps to significantly reduce these losses. According to one example, the electronic switch <NUM> in the biasing circuit <NUM> is operated such that it switches on during the second dead time Td2. When the electronic switch <NUM> is switched on, the bias voltage Vbias is applied to the load path D-S of the first transistor device <NUM>, wherein the bias voltage Vbias removes the charge carrier plasma from the first transistor device <NUM> and charges the output capacitance. According to one example, the bias voltage Vbias (or the voltage generated based on the bias voltage Vbias) is significantly lower than the load supply voltage Vsupz, so that removing the charge carrier plasma and charging the junction capacitance using the biasing circuit <NUM> is associated with significantly lower losses than in a conventional half-bridge circuit. According to one example, the bias voltage Vbias is less than <NUM>% of the load supply voltage Vsupz.

Voltage blocking capabilities of the first and second transistor device <NUM>, 1a are adapted to the load supply voltage Vsupz, wherein the voltage blocking capability of each of the first and second transistor device <NUM>, 1a at least equals the load supply voltage Vsupz. Thus, according to one example, the bias voltage Vbias is less than <NUM>%, or even less than <NUM>% of a voltage blocking capability of the first transistor device <NUM>.

<FIG> illustrates one example of an half-bridge circuit of the type shown in <FIG>, wherein both the first transistor device <NUM> and the second transistor device 1a have a respective biasing circuit <NUM>, 3a connected thereto. In the following, the biasing circuit <NUM> connected to the first transistor device <NUM> is referred to as first biasing circuit, and the biasing circuit 3a connected to the second transistor device 1a is referred to as second biasing circuit in the following. Each of the first and second biasing circuits <NUM>, 3a illustrated in <FIG> is implemented in accordance with the examples illustrated in <FIG> and <FIG> and includes a respective electronic switch <NUM>, 31a.

Furthermore, the half-bridge circuit includes a drive circuit arrangement DRVC that is configured to drive the first transistor device <NUM> and the electronic switch <NUM> in the first biasing circuit <NUM> based on a first half-bridge input signal Sin and drive the second transistor device 1a and the electronic switch 31a in the second biasing circuit 3a based on a second half-bridge input signal Sina.

Referring to <FIG>, the drive circuit arrangement DRVC includes a first drive circuit <NUM> configured to drive the first transistor device <NUM>, a second drive circuit <NUM> configured to drive the electronic switch <NUM> in the first biasing circuit <NUM>, a third drive circuit 2a configured to drive the second transistor device 1a, and a fourth drive circuit 7a configured to drive the electronic switch 31a in the second biasing circuit 3a. More specifically, the first drive circuit <NUM> is configured to receive the first input signal Sin1 at an input <NUM>, <NUM> and generate the first drive voltage Vgs1 received by the first transistor device <NUM> based on the first input signal Sin1; the second drive circuit <NUM> is configured to receive the second input signal Sin2 at an input <NUM>, <NUM> and generate the second drive voltage Vgs2 received by the electronic switch <NUM> in the first biasing circuit <NUM> based on the second input signal Sin2; the third drive circuit 2a is configured to receive a third input signal Sin1a at an input 24a, 25a and generate the drive voltage Vgs1a (which is referred to as third drive voltage in the following) received by the second transistor device 1a based on the third input signal Sin1a; and the fourth drive circuit 7a is configured to receive a fourth input signal Sin2a at an input 76a, 77a and generate a drive voltage Vgs2a (which is referred to as fourth drive voltage in the following) received by the electronic switch 31a in the second biasing circuit 3a based on the fourth input signal Sin2a. According to one example, each of the first to fourth input signal Sin1, Sin2, Sin1a, Sin2a is a voltage received at the input of the respective drive circuit <NUM>, <NUM>, 2a, 7a.

In <FIG>, corresponding parts have like reference numbers, wherein lowercase letter "a" has been added to the reference numbers of those circuit parts associated with the second transistor device 1a and the second biasing circuit 3a.

In the electronic according to <FIG>, the bias voltage Vbias may be generated in accordance with any of the examples explained herein before, wherein the bias voltage circuit <NUM> is not illustrated in <FIG>. This bias voltage Vbias is used by the first biasing circuit <NUM> to bias the load path D-S of the first transistor device <NUM>. That is, the bias voltage Vbias is received by the series circuit including the first electronic switch <NUM> and the diode of the first biasing circuit <NUM> and the first transistor device <NUM>.

According to one example, an internal bias voltage of the second biasing circuit 3a may be generated based on the bias voltage generated in the second biasing circuit <NUM>. For this, the second biasing circuit 3a may include a bootstrap circuit with a bootstrap diode <NUM> and at least one capacitor 46a, wherein this bootstrap circuit is connected in parallel with the output capacitor <NUM> of the bias voltage source via the first transistor device <NUM>, so that the (at least) one capacitor 46a of the bootstrap circuit is charged each time the first transistor device <NUM> is switched on. A voltage level of the internal biasing voltage that is available across the bootstrap capacitor <NUM> essentially equals a voltage level of the bias voltage Vbias generated by the bias voltage circuit <NUM> of the first biasing circuit <NUM>. This internal biasing voltage is available in the second biasing circuit 3a even in those time periods in which the first transistor device <NUM> is in the off-state.

The drive circuit arrangement DRVC electronic circuit is configured to receive the supply voltage Vsup between a first supply node <NUM> and a second supply node <NUM> and is configured to generate internal supply voltages of the drive circuits <NUM>, <NUM>, 2a, 7a based on the supply voltage Vsup. As explained above, the first drive circuit <NUM> may receive the supply voltage Vsup between the first and second supply nodes <NUM>, <NUM>.

The second drive circuit <NUM> may include a bootstrap circuit with a capacitor <NUM> and a diode <NUM> connected between the first and second supply nodes <NUM>, <NUM> of the second drive circuit <NUM>. These circuit elements <NUM>, <NUM> are explicitly illustrated in <FIG>, while other circuit elements of the second drive circuit <NUM> are represented by a circuit block. The first supply node <NUM> of the second drive circuit <NUM> is connected to the first supply node <NUM> of the drive circuit arrangement DRVC, and the second supply node <NUM> of the second drive circuit <NUM> is coupled to the second supply node <NUM> of the drive circuit arrangement DRVC via the diode <NUM> of the first biasing circuit <NUM> and the first transistor device <NUM>. In this arrangement, the capacitor <NUM> of the bootstrap circuit <NUM>, <NUM> is charged via the diode <NUM> to a voltage level that essentially equals the voltage level of the supply voltage Vsup whenever the first transistor device <NUM> is in the on-state, so that a voltage level of an internal supply voltage of the second drive circuit <NUM> essentially equals the voltage level of the supply voltage Vsup. This internal supply voltage, however, is not referenced to a fixed potential.

Similarly to the second drive circuit <NUM>, the third drive circuit 2a may include a bootstrap circuit with a capacitor 26a and a diode 27a connected between the first and second supply nodes 21a and 23a of the third drive circuit 2a. The first supply node 21a of the third drive circuit 2a is connected to the first supply node <NUM> of the drive circuit arrangement DRVC, and the second supply node 23a of the third drive circuit 2a is coupled to the second supply node <NUM> of the drive circuit arrangement DRVC via the first transistor device <NUM>. In this arrangement, the capacitor 26a of the bootstrap circuit 26a, 27a is charged via the diode 27a to a voltage level that essentially equals the voltage level of the supply voltage Vsup whenever the first transistor device <NUM> is in the on-state, so that a voltage level of an internal supply voltage of the third drive circuit 2a essentially equals the voltage level of the supply voltage Vsup. This internal supply voltage, however, is not referenced to a fixed potential.

Referring to <FIG>, the fourth drive circuit 7a may include a bootstrap circuit with a capacitor 74a and a diode 75a connected between the first and second supply nodes 71a, 73a of the fourth drive circuit 7a. The first supply node 71a of the fourth drive circuit 7a is connected to the bootstrap capacitor 26a of the third drive circuit and the second supply node 73a of the fourth drive circuit 7a is coupled to the second supply node 23a of the third drive circuit 2a via the diode 32a of the second biasing circuit 3a and the second transistor device 1a. In this arrangement, the capacitor 74a of the bootstrap circuit 74a, 75a of the fourth drive circuit 7a is charged by the bootstrap capacitor <NUM> of the third drive circuit 2a whenever the second transistor device 1a is in the on-state.

Referring to the above, in the half-bridge circuit shown in <FIG>, the first transistor device <NUM> switches on and off dependent on the input signal Sin1 received by the first drive circuit <NUM>, and the electronic switch <NUM> of the first biasing circuit <NUM> switches on and off dependent on the second input signal Sin2 received by the second drive circuit <NUM>. Equivalently, the second transistor device 1a switches on or off dependent on the third input signal Sin1a received by the third drive circuit 2a, and the electronic switch 31a of the second biasing circuit 3a switches on or off dependent on the fourth input signal Sin2a received by the fourth drive circuit 7a. The input signals Sin1, Sin2a are dependent on the first half-bridge input signal Sin, and the input signals Sin1a, Sin2 are dependent on the second half-bridge input signal Sina.

The half-bridge input signals Sin, Sina govern the operation of the half-bridge circuit. According to one example, the first and second half-bridge signals Sin, Sina are PWM signals. The first half-bridge signal Sin governs switching on or off the first transistor device <NUM> and the electronic switch 31a in the second biasing circuit 3a. That is, the first input signal Sin1 and the fourth input signal Sin2a are generated based on the first half-bridge signal Sin. The second half-bridge signal Sina governs switching on or off the second transistor device 1a and the electronic switch <NUM> in the first biasing circuit <NUM>. That is, the third input signal Sin1a and the second input signal Sin2 are generated based on the second half-bridge signal Sina. According to one example, the first and second half-bridge input signals Sin, Sina are generated such that at most one of these signals Sin, Sina has an on-level at the same time.

<FIG> shows signal diagrams that illustrate one example of operating the half-bridge circuit shown in <FIG>. More specifically, <FIG> schematically illustrates signal diagrams of the first and second half-bridge signals Sin, Sina and the first to fourth drive voltages Vgs <NUM>, Vgs2, Vgs1a, Vgs2a. Just for the purpose of illustration, it is assumed, that a high signal level illustrated in <FIG> represents an on-level of the respective half-bridge input signal or the respective drive voltage and that a low signal level represents an off-level of the respective half-bridge input signal or the respective drive voltage.

Referring to <FIG>, in the half-bridge circuit shown in <FIG>, the electronic switch <NUM> in the first biasing circuit <NUM> is switched on for a certain time period before the second transistor device 1a switches on, and the electronic switch 31a in the second biasing circuit 3a is switched on for a certain time period before the first transistor device <NUM> is switched on. This is achieved by driving the first and second transistor devices <NUM>, 1a and the electronic switches <NUM>, 31a in the first and second biasing circuit <NUM>,3a dependent on the first and second half-bridge signal Sin, Sina as follows:.

Referring to <FIG>, the time period during which the electronic switch 31a of the second biasing circuit 3a, governed by the fourth drive signal Vgs2a, is switched on may overlap with the time period during which the first transistor device <NUM>, governed by the first drive signal Vgs1, is switched on. That is, the first transistor device <NUM> may switch on when the electronic switch 31a of the second biasing circuit 3a is still in the on-state. Equivalently, the time period during which the electronic switch <NUM> of the first biasing circuit <NUM>, governed by the second drive signal Vgs2, is switched on may overlap with the time period during which the second transistor device 1a, governed by the third drive signal Vgs1a, is switched on. That is, the second transistor device 1a may switch on when the electronic switch <NUM> of the first biasing circuit <NUM> is still in the on-state.

Referring to <FIG>, there may be a third delay time Tdel3 between a time instance at which the first half-bridge signal Sin changes from the on-level to the off-level and the time instance at which the first drive signal Vgs1 changes from the on-level to the off-level. Equivalently, there may be a fourth delay time Tdel4 between a time instance at which the second half-bridge signal Sina changes from the on-level to the off-level and the time instance at which the third drive signal Vgs1a changes from the on-level to the off-level. According to one example, the second delay time Tdel2 at least approximately equals the first delay time Tdel1, and the fourth delay time Tdel4 at least approximately equals the third delay time Tdel3. The third and fourth delay times Tdel3, Tdel <NUM> may be longer than the first and second delay times Tdel1, Tdel2.

According to one example, the switching behavior illustrated in <FIG> is achieved by passive filters PF1 - PF4 which are connected between signal inputs that are configured to receive the first and second half-bridge input signals Sin, Sina and the inputs of the drive circuits <NUM>, <NUM>, 2a, 7a. In the following, the signal input configured to receive the first half-bridge signal Sin is referred to as first half-bridge signal input, and the signal input configured to receive the second half-bridge signal Sina is referred to as second half-bridge signal input. The passive filters PF1 - PF4 include a first filter PF1 connected between the first half-bridge signal input and the input <NUM>, <NUM> of the first drive circuit <NUM>; a second filter PF2 connected between the second half-bridge signal input and the input <NUM>, <NUM> of the second drive circuit <NUM>; a third filter PF3 connected between the second half-bridge signal input and the input 24a, 25a of the third drive circuit 2a; and a fourth filter PF4 connected between the first half-bridge signal input and the input 76a, 77a of the fourth drive circuit 7a.

According to one example, each of the first and third passive filter PF1, PF3 includes an RC element with a resistor <NUM>, 85a and a capacitor <NUM>, 86a, wherein the capacitor <NUM>, 86a is connected in series with the resistor <NUM>, 85a and is connected between a first input node <NUM>, 24a, and a second input node <NUM>, 25a of the respective one of the first drive circuit <NUM> and the third drive circuit 2a. According to one example, the first half-bridge signal Sin is a voltage that is referenced to the second input node <NUM> of the first drive circuit <NUM> and the second half-bridge signal Sina is a voltage that is referenced to the second input node 25a of the third drive circuit 2a.

According to one example, each of the first and third drive circuits <NUM>, 2a is configured to generate an on-level of the respective drive voltage Vgs1, Vgs1a when the respective input signal Sin1, Sin1a (which is the voltage between the respective first and second input nodes <NUM>, <NUM>, 24a, 25a) is higher than a respective first voltage threshold, and to generate an off-level of the respective drive voltage Vgs1, Vgs1a when the respective input signal Sin1, Sin1a is lower than a respective second voltage threshold. The first and second voltage thresholds can be identical or can be different (to achieve a hysteresis in the switching behavior). Due to the RC elements there is a delay time between a time instance at which the respective half-bridge signal Sin, Sina changes from the off-level to the on-level and a time instance at which the input signal Sin1, Sin1a of the respective first or third drive circuit <NUM>, 2a reaches the respective first voltage threshold. That is, the first delay time Tdel1 is defined by the RC element <NUM>, <NUM> in the first passive filter, and the second delay time Tdel2 is defined by the RC element 85a, 86a in the third passive filter. Each RC element has an RC time constant (which is given by the capacitance of the respective capacitor multiplied with the resistance of the respective resistor), wherein the greater the RC time constant, the greater the delay time. Thus, the first and second delay times Tdel1, Tdel2 can be adjusted by suitably adjusting the RC time constants of the RC elements <NUM>, <NUM> and 85a, 86a.

According to one example, each of the second and fourth passive filter PF2, PF4 includes a CR element with a capacitor <NUM>, 83a and a resistor <NUM>, 84a, wherein the resistor <NUM>, 84a is connected in series with the capacitor <NUM>, 83a , and wherein the resistor <NUM>, 84a is connected between a first input node <NUM>, 76a, and a second input node <NUM>, 77a of the respective one of the second drive circuit <NUM> and the fourth drive circuit 7a. According to one example, the first half-bridge signal Sin is a voltage that is referenced to the second input node 77a of the fourth drive circuit 7a, and the second half-bridge signal Sina is a voltage that is referenced to the second input node <NUM> of the second drive circuit <NUM>. It should be noted that the second input nodes <NUM>, 25a, <NUM>, 77a of the drive circuits <NUM>, 2a, <NUM>, 7a may be connected to a common input ground node and the first and second half-bridge input signals Sin, Sina may be referenced to this common input ground node. The drive circuits <NUM>, 2a, <NUM>, 7a may include an internal potential barrier, such as a transformer, so that the drive voltages Vgs1, Vgs1a, Vgs2, Vgs2a may be referenced to circuit nodes different from the common input ground node.

According to one example, each of the second and fourth drive circuits <NUM>, 7a is configured to generate an on-level of the respective drive voltage Vgs2, Vgs2a when the respective input signal Sin2, Sin2a (which is the voltage between the respective first and second input nodes <NUM>, <NUM>, 76a, 77a) is higher than a respective third voltage threshold, and to generate an off-level of the respective drive voltage Vgs2, Vgs2a when the respective input signal Sin1, Sin1a is lower than a respective fourth voltage threshold. The third and fourth voltage thresholds can be identical or can be different (to achieve a hysteresis in the switching behavior).

Referring to <FIG>, whenever the signal level of the first half-bridge signal Sin changes from the off-level to the on-level, the drive voltage Vgs2a of the electronic switch 31a in the second biasing circuit 3a has an on-level for a first time period Tp1, which is referred to as first pulse period in the following. Equivalently, whenever the signal level of the second half-bridge signal Sina changes from the off-level to the on-level, the drive voltage Vgs2 of the electronic switch <NUM> in the first biasing circuit <NUM> has an on-level for a second time period Tp2, which is referred to as second pulse period in the following. These first and second pulse periods Tp1, Tp2 can be adjusted by suitably adjusting the resistances and capacitances of the resistors <NUM>, <NUM> and the capacitances, respectively, in the CR elements of the passive filters connected to the inputs <NUM>, <NUM>, 76a, 77a of the second and fourth drive circuits <NUM>, 7a.

Each of the second and fourth drive circuits <NUM>, 7a (as well as the first and third drive circuits <NUM>, 2a) includes in internal input capacitance (not shown) between the respective input nodes <NUM>, <NUM>, 76a, 77a. The input capacitance of the second drive circuit <NUM> is charged via the capacitor <NUM> of the respective CR element <NUM>, <NUM> when a rising edge of the second half-bridge input signal Sina occurs, wherein the electronic switch <NUM> of the first biasing circuit <NUM> switches on when the input capacitance has been charged such that input signal (input voltage) Sin2 is higher than the third voltage threshold explained above. For the ease of illustration, an inevitable delay time between the rising edge of the second half-bridge input signal Sina and a corresponding rising edge of the drive voltage Vgs2 is not illustrated in <FIG>. The input capacitance of the second drive circuit <NUM> is discharged via the resistor <NUM> of the CR element <NUM>, <NUM>, wherein the electronic switch <NUM> switches off when the input capacitance has been discharged such that input signal (input voltage) Sin2 falls below the fourth voltage threshold. Equivalently, the input capacitance of the fourth drive circuit 7a is charged via the capacitor 83a of the respective CR element 83a, 84a when a rising edge of the first half-bridge input signal Sin occurs, wherein the electronic switch 31a of the second biasing circuit 3a switches on when the input capacitance has been charged such that input signal (input voltage) Sin2a is higher than the third voltage threshold explained above. For the ease of illustration, an inevitable delay time between the rising edge of the first half-bridge input signal Sin and a corresponding rising edge of the drive voltage Vgs2a is not illustrated in <FIG>. The input capacitance of the fourth drive circuit 7a is discharged via the resistor 84a of the CR element 83a, 84a, wherein the electronic switch 31a switches off when the input capacitance has been discharged such that input signal (input voltage) Sin2a falls below the fourth voltage threshold. Thus, the first and second pulse periods Tp1, Tp2 can be adjusted by suitably adjusting the resistance of the resistor <NUM>, 84a in the respective CR element <NUM>, <NUM>, 83a, 84a.

In an electronic circuit of the type shown in <FIG>, the first drive circuit <NUM> and the second drive circuit <NUM> may be implemented using one common drive circuit of the type shown in <FIG> and the second drive circuit 2a and the fourth drive circuit 7a may be implemented using another integrated circuit of the type shown in <FIG>. This is illustrated in <FIG>.

The electronic circuit according to <FIG> includes a first common drive circuit <NUM> - <NUM> for driving the first transistor device <NUM> and the electronic switch <NUM> in the first biasing circuit <NUM> and a second common drive circuit 2a - 7a for driving the second transistor device 1a and the electronic switch 31a in the second biasing circuit 3a. Each of the first common drive circuit <NUM> - <NUM> and the second common drive circuits 2a - 7a is implemented in accordance with the example illustrated in <FIG> and includes a respective integrated drive circuit <NUM>, 27a, wherein the integrated circuit <NUM> in the first common drive circuit <NUM> - <NUM> is referred to as first integrated drive circuit in the following and the integrated circuit 27a in the second common drive circuit 2a - 7a is referred to as second integrated drive circuit in the following.

Referring to <FIG>, the first integrated drive circuit <NUM> - <NUM>, which drives the first transistor device <NUM> and the electronic switch <NUM> in the first biasing circuit <NUM>, receives the first input signal Sin1 and the second input signal Sin2 from the respective passive filter <NUM>, <NUM>, <NUM>, <NUM>, wherein these input signals Sin1, Sin2 are referenced to the same input ground node. The second integrated drive circuit 2a - 7a, which drives the second transistor device <NUM> and the electronic switch 31a in the second biasing circuit 3a, receives the first input signal Sin1a and the second input signal Sin2a from the respective passive filter 83a, 84a, 85a, 86a, wherein these input signals Sin1a, Sin2a are referenced to the same input ground node.

<FIG> schematically illustrates one example of the first transistor device <NUM>. More specifically, <FIG> illustrates a vertical cross sectional view of one section of a semiconductor body <NUM> in which the first transistor device <NUM> is integrated. The semiconductor body <NUM> may include a conventional semiconductor material such as, for example, silicon (Si) or silicon carbide (SiC).

The first transistor device illustrated in <FIG> is a superjunction transistor device. It should be noted that the first transistor device is not restricted to be implemented in accordance with the example illustrated in <FIG>. However, <FIG> may help to better understand the operating principle of the first transistor device and, in particular, charging the output capacitance of the first transistor device <NUM> when the transistor device is in the off-state and forward biased so that the output capacitance is charged.

Referring to <FIG>, in the semiconductor body <NUM>, the first transistor device <NUM> includes a drift region <NUM> with a plurality of first regions <NUM> of a first doping type (conductivity type) and a plurality of second regions <NUM> of a second doping type (conductivity type) complementary to the first doping type. The first regions <NUM> and the second regions <NUM> are arranged alternately in at least one horizontal direction x of the semiconductor body <NUM>, and a pn-junction is formed between each first region <NUM> and a corresponding adjoining second region <NUM>. A pitch p of the semiconductor structure with the first and second semiconductor regions <NUM>, <NUM> is given by a center distance between two neighboring first semiconductor regions <NUM> or a center distance between two neighboring second semiconductor regions <NUM>.

Referring to <FIG>, the first regions <NUM> are connected to the drain node D of the transistor device <NUM>, and the second regions <NUM> are connected to the source node S of the transistor device <NUM>. A connection between the second regions <NUM> and the source node S is only schematically illustrated in <FIG>. Examples of how these connections can be implemented are explained with reference to examples herein further below. The first regions <NUM> are connected to the drain node D via a drain region <NUM> of the first doping type. The drain region <NUM> may adjoin the first regions <NUM>. This, however, is not shown in <FIG>. Optionally, as shown in <FIG>, a buffer region <NUM> of the first doping type is arranged between the drain region <NUM> and the first regions <NUM>. The buffer region <NUM> has the first doping type, which is the doping type of the drift regions <NUM> and the drain region <NUM>. According to one example, a doping concentration of the buffer region <NUM> is lower than a doping concentration of the drain region <NUM>. The doping concentration of the drain region <NUM> is selected from a range of between 1E17 (=<NUM><NUM>) cm-<NUM> and 1E20 cm-<NUM>, for example, and the doping concentration of the buffer region <NUM> is selected from a range of between 1E14 cm-<NUM> and 1E17 cm-<NUM>, for example.

Referring to <FIG>, the first transistor device <NUM> further includes a control structure <NUM> connected between the source node S and the first regions <NUM>. The control structure <NUM> is at least partially integrated in the semiconductor body <NUM>. Examples of how the control structure <NUM> may be implemented are explained with reference to examples herein further below. The control structure <NUM> furthermore includes the gate node G and is configured to control a conducting channel between the source node S and the first regions <NUM> dependent on the first drive voltage Vgs1 received between the gate node G and the source node S. In the example shown in <FIG>, this function of the control structure <NUM> is represented by a switch connected between the source node S and the first regions <NUM>. Furthermore, the control structure <NUM> includes a pn-junction between the first regions <NUM> and the source node S. In the example shown in <FIG>, this pn-junction is represented by a bipolar diode connected between the first regions <NUM> and the source node S. This diode represents the body diode or is part of the body diode of the transistor device <NUM>.

The transistor device has a current flow direction, which is a direction in which a current may flow between the source node S and the drain node D inside the semiconductor body. In the example shown in <FIG>, the current flow direction is a vertical direction z of the semiconductor body <NUM>. The vertical direction z is a direction perpendicular to a first surface (not shown in <FIG>) and a second surface <NUM>, which is formed by the drain region <NUM>, of the semiconductor body <NUM>. <FIG> shows a vertical cross sectional view of the drift region <NUM>, the drain region <NUM>, and the optional buffer region <NUM>. The "vertical cross sectional view" is a sectional view in a section plane perpendicular to the first surface and the second surface <NUM> and parallel to the vertical direction z. Section planes perpendicular to the vertical section plane shown in <FIG> are referred to as horizontal section planes in the following.

<FIG> shows one example of the control structure <NUM> in a greater detail. Besides the control structure <NUM>, portions of the drift region <NUM> adjoining the control structure <NUM> are shown in <FIG>. In the example shown in <FIG> the control structure <NUM> includes a plurality of control cells <NUM>, which may also be referred to as transistor cells. Each of these control cells <NUM> includes a body region <NUM> of the second doping type, a source region <NUM> of the first doping type, a gate electrode <NUM>, and a gate dielectric <NUM>. The gate dielectric <NUM> dielectrically insulates that gate electrode <NUM> from the body region <NUM>. The body region <NUM> of each control cell <NUM> separates the respective source region <NUM> of the control cell <NUM> from at least one of the plurality of first regions <NUM>. The source region <NUM> and the body region <NUM> of each of the plurality of control cells <NUM> is electrically connected to the source node S. "Electrically connected" in this context means ohmically connected. That is, there is no rectifying junction between the source node S and the source region <NUM> and the body region <NUM>. Electrical connections between the source node S and the source region <NUM> and the body region <NUM> of the individual control cells <NUM> are only schematically illustrated in <FIG>. The gate electrode <NUM> of each control cell <NUM> is electrically connected to the gate node G.

Referring to the above, the body region <NUM> of each control cell <NUM> adjoins at least one first region <NUM>. As the body region <NUM> is of the second doping type and the first region <NUM> is of the first doping type there is a pn-junction between the body region <NUM> of each control cell <NUM> and the at least one first region <NUM>. These pn-junctions form the pn-junction of the control structure <NUM> that is represented by the bipolar diode in the equivalent circuit diagram of the control structure <NUM> shown in <FIG>.

In the example shown in <FIG>, the gate electrode <NUM> of each control structure <NUM> is a planar electrode arranged on top of the first surface <NUM> of the semiconductor body <NUM> and dielectrically insulated from the semiconductor body <NUM> by the gate dielectric <NUM>. In this example, sections of the first regions <NUM>, adjacent the individual body regions <NUM>, extend to the first surface <NUM>.

<FIG> shows a control structure <NUM> according to another example. The control structure <NUM> shown in <FIG> is different from the control structure <NUM> shown in <FIG> in that the gate electrode <NUM> of each control cell <NUM> is a trench electrode. This gate electrode <NUM> is arranged in a trench that extends from the first surface <NUM> into the semiconductor body <NUM>. Like in the example shown in <FIG>, a gate dielectric <NUM> dielectrically insulates the gate electrode <NUM> from the respective body region <NUM>. The body region <NUM> and the source region <NUM> of each control cell <NUM> are electrically connected to the source node S. Further, the body region <NUM> adjoins at least one first region <NUM> and forms a pn-junction with the respective first region <NUM>.

In the examples shown in <FIG>, the control structures <NUM> each include one gate electrode <NUM>, wherein the gate electrode <NUM> of each control cell <NUM> is configured to control a conducting channel between the source region <NUM> of the respective control cell <NUM> and one first region <NUM>, so that each control cell <NUM> is associated with one first region <NUM>. Further, as shown in <FIG>, the body region <NUM> of each control cell <NUM> adjoins at least one second region <NUM>, so that the at least one second region <NUM> is electrically connected to the source node S via the body region <NUM> of the control cell <NUM>. Just for the purpose of illustration, in the examples shown in <FIG> and <FIG>, the body region <NUM> of each control cell <NUM> adjoins one second region <NUM> so that each control cell <NUM> is associated with one second region. Furthermore, in the examples, shown in <FIG> and <FIG>, the source regions <NUM> of two (or more) neighboring control cells <NUM> are formed by one doped region of the first doping type, the body regions <NUM> of two (or more) neighboring control cells <NUM> are formed by one doped region of the second doping type, and the gate electrodes <NUM> of two (or more) control cells <NUM> are formed by one electrode. The gate electrodes <NUM> may include doped polysilicon, a metal, or the like. According to one example, a doping concentration of the source regions <NUM> is selected from a range of between 1E18 cm-<NUM> and 1E210 cm-<NUM>, and a doping concentration of the body regions <NUM> is selected from a range of between 1E16 cm-<NUM> and 5E18 cm-<NUM>.

<FIG> shows a perspective sectional view of the drift region <NUM> according to one example. In this example, the first regions <NUM> and the second regions <NUM> are elongated in one lateral direction of the semiconductor body <NUM>. Just for the purpose of illustration, this lateral direction is a second lateral direction y perpendicular to the first lateral direction x. "Elongated" means that a length of the first and second regions <NUM>, <NUM> is significantly greater than a width. The "length" is a dimension in one direction, which may be referred to as longitudinal direction, and the "width" is a dimension in a direction perpendicular to the longitudinal direction. In the example shown in <FIG>, the length is the dimension in the second lateral direction y of the semiconductor body <NUM>, and the width is the dimension in the first lateral direction x of the semiconductor body <NUM>. According to one example, "significantly greater" means that a ratio between the length and the width is greater than <NUM>, greater than <NUM>, or even greater than <NUM>.

Associating one control cell <NUM> of the plurality of control cells with one first region <NUM> and one second region <NUM>, as illustrated in <FIG> and <FIG>, is only an example. The implementation and the arrangement of the control cells <NUM> of the control structure <NUM> are widely independent of the specific implementation and arrangement of the first regions <NUM> and the second regions <NUM>.

One example illustrating that the implementation and arrangement of the control structure <NUM> are widely independent of the implementation and arrangement of the first and second regions <NUM>, <NUM> is shown in <FIG>. In this example, the first regions <NUM> and the second regions <NUM> are elongated in the second lateral direction y of the semiconductor body <NUM>, while the source regions <NUM>, the body regions <NUM>, and the gate electrodes <NUM> of the individual control cells <NUM> of the control structure <NUM> are elongated in the first lateral direction x perpendicular to the second lateral direction y. In this example, the body region <NUM> of one control cell <NUM> adjoins a plurality of first regions <NUM> and second regions <NUM>.

The functionality of a transistor device of the type explained herein above is explained below. The transistor device can be operated in a forward biased state and a reverse biased state. Whether the device is in the forward biased state or the reverse biased state is dependent on a polarity of the load path voltage (drain-source voltage) Vds. In the reverse biased state the polarity of the drain-source voltage Vds is such that the pn-junctions between the body regions <NUM> and the first regions <NUM> of the drift region <NUM> are forward biased, so that in this operation state the transistor device conducts a current independent of an operation state of the control structure <NUM>. In this operating state, that is, when the transistor device is reverse biased, the body diode is forward biased.

In the forward biased state of the transistor device, the polarity of the drain-source voltage Vds such that the pn-junctions between the body regions <NUM> and the first regions <NUM> are reverse biased. In this forward biased state, the transistor device can be operated in an on-state or an off-state by the control structure <NUM>. In the on-state, the control structure <NUM> generates a conducting channel between the source node S and the first regions <NUM>, and in the off-state this conducting channel is interrupted. More specifically, referring to <FIG>, in the on-state there are conducting channels in the body regions <NUM> between the source regions <NUM> and the first regions <NUM> controlled by the gate electrodes <NUM>. In the off-state, these conducting channels are interrupted. The gate electrodes <NUM> are controlled by a gate-source voltage VGS, which is a voltage between the gate node G and the source node S.

The transistor device can be implemented as an n-type transistor device or as a p-type transistor device. In an n-type transistor device, the first doping type, which is the doping type of the first regions <NUM>, the source regions <NUM>, the drain region <NUM> and the optional buffer region <NUM> is an n-type and the second doping type, which is the doping type of the second regions <NUM> and the body regions <NUM>, is a p-type. In a p-type transistor device, the doping types of the device regions mentioned before are complementary to the doping types of the respective device regions in an n-type transistor device. An n-type transistor device, for example, is in the forward biased state when the drain-source voltage Vds is a positive voltage. Furthermore, an n-type enhancement (normally-off) transistor device is in the on-state when the drive voltage (gate-source voltage) Vgs1 is positive and higher than a threshold voltage of the transistor device <NUM>.

Referring to <FIG>, and <FIG>, in the transistor device <NUM>, the second regions <NUM> are coupled to the source node S. These second regions <NUM>, which are sometimes referred to as compensation regions, may directly by connected to the source node S (not illustrated), or may be connected to the source node S via the body regions <NUM>) as illustrated. In this case, each of the second regions <NUM> adjoins at least one of the body regions <NUM>, wherein the body regions <NUM> are connected to the source node S (as schematically illustrated in <FIG>, and <FIG>). Between the first regions <NUM> and the second regions <NUM> pn-junctions are formed. Thus, the first and second regions <NUM>, <NUM> form a junction capacitance, wherein this junction capacitance forms a significant portion of the output capacitance of the transistor device <NUM>.

When the transistor device is in the off-state and forward biased the pn-junctions between the first and second regions <NUM>, <NUM> are reverse biased, so that depletion regions (space charge regions) expand in the first and second regions. This is equivalent to charging the junction capacitance formed by the first and second regions <NUM>, <NUM>.

<FIG> illustrates one example of an output capacitance Coss of a superjunction transistor device on a logarithmic scale. As can be seen from <FIG>, the output capacitance is highly dependent on the drain-source voltage Vds (which is also illustrated on a logarithmic scale) in such a way that the output capacitance Coss decreases as the drain-source voltage Vds increases. More specifically, the output capacitance Coss rapidly decreases when the drain-source voltage Vds reaches a certain voltage level Vdep, which is referred to as depletion voltage in the following. The output capacitance Coss may decrease for about <NUM> orders of magnitude, or more, when the drain-source voltage Vds reaches the depletion voltage Vdep.

In the superjunction transistor device, the first and second regions <NUM>, <NUM> are implemented such that they can completely be depleted of charge carriers, when the pn junctions between the first and second regions <NUM>, <NUM> are reverse biased. A doping concentrations of the first and second regions <NUM>, <NUM> is between 1E15 cm-<NUM> and
1E17 cm-<NUM>, for example, and the pitch p is such that the voltages across these pn junctions are below the breakdown voltage when the first and second regions <NUM>, <NUM> are completely depleted. The depletion voltage Vdep is the voltage level of the drain-source voltage Vds that is required to completely deplete the first and second regions <NUM>, <NUM>. This depletion voltage Vdep is much lower than the voltage blocking capability of the transistor device. The superjunction transistor <NUM> can be implemented such that depletion voltage Vdep is less than 30V, or even less than 25V, while the voltage blocking capability is several <NUM> volts (V), such as 600V or 800V.

When the drain-source voltage Vds has reached the depletion voltage Vdep the output capacitance Coss has been mainly charged. That is, for example, between <NUM>% and <NUM>% of an overall charge that can be stored in the output capacitance Coss have been stored when the drain source voltage Vds reaches the depletion voltage Vdep. Thus, according to one example, in the electronic circuit explained before, the voltage applied by the bias circuit <NUM> to the load path of the transistor device <NUM> is at least <NUM>%, at least <NUM>% or at least <NUM>% of the depletion voltage Vdep. This "voltage applied to the load path of the transistor device <NUM>" is either the bias voltage Vbias or the boosted bias voltage (when the at least one inductor is used). According to one example, the bias voltage is between <NUM>% and <NUM>% of the depletion voltage Vdep.

In a superjunction transistor device, the depletion voltage Vdep decrease as the pitch p decreases, wherein the lower the depletion voltage Vdep, the lower the bias voltage that is required. According to one example, the superjunction transistor device <NUM> is implemented such that the pitch p is lower than <NUM> micrometers (µm), lower than <NUM>, or even lower than <NUM>. The pitch of the transistor device may vary. Thus, according to one example, pitch p as used herein denotes the average pitch.

Referring to the above, each of the biasing circuits <NUM>, 3a includes a diode <NUM>, 32a in addition to the respective electronic switch <NUM>, 31a. The diode <NUM>, 32a is connected in series with the respective electronic switch <NUM>, 31a and the respective transistor device <NUM>, 1a in such a way that it blocks when the load path voltage of the respective transistor device <NUM>, 1a becomes higher than the bias voltage, so that the diode <NUM>, 32a protects the electronic switch <NUM>, 31a against overvoltages. Furthermore, when the respective electronic switch <NUM>, 31a is switched on and the load path voltage of the respective transistor device <NUM>, 1a is lower than the bias voltage Vbias, the current from the respective biasing circuit <NUM>, 3a into the respective transistor device <NUM>, 1a (that removes the charge carrier plasma and charges the output capacitance) flows through the diode <NUM>, 32a.

According to one example, the diode is made of a wide-bandgap (WBG) semiconductor material. According to one example, the WBG semiconductor material is silicon carbide (SiC). According to one example, the diode <NUM>, 32a is a Schottky diode, which offers lower conduction losses than a pn-diode.

One example of a diode is illustrated in <FIG>. More specifically, <FIG> schematically illustrates a vertical cross sectional view of a diode. The diode includes a semiconductor body <NUM> that includes a wide-bandgap semiconductor material, such as SiC. The semiconductor body <NUM> includes a first surface <NUM>, a second surface <NUM> opposite the first surface <NUM>, an n-type base region <NUM>, and an n-type emitter region <NUM> adjoining the base region <NUM> and adjoining the second surface <NUM> of the semiconductor body <NUM>. The diode further includes a Schottky metal <NUM> on top of the first surface <NUM>. The base region <NUM> extends to the first surface <NUM> and adjoins the Schottky metal <NUM>, so that one or more Schottky contacts are formed between the Schottky metal <NUM> and the base region <NUM>. The Schottky metal <NUM> forms an anode node A or is connected to an anode node A of the diode. The n-type emitter <NUM> forms a cathode node K or is connected to a cathode node K of the diode.

The diode illustrated in <FIG> is configured to conduct a current when a positive voltage is applied between the anode A and the cathode K. Furthermore, the diode is configured to block when a negative voltage is applied between the anode A and the cathode K.

Additionally, the diode may include one or more p-type emitter regions <NUM> that adjoin the n-type base region <NUM> and the Schottky metal <NUM>. A diode of this type includes a Schottky diode in parallel with a pn diode, wherein the Schottky diode includes the one or more Schottky contacts between the Schottky metal <NUM> and the base region <NUM> and the pn diode includes the pn junctions between the p-type emitter regions <NUM> and the base region. The pn-diode is inactive as long as the voltage between the anode A and the cathode K is below a forward voltage of the pn junction.

The p-type emitter regions <NUM> and those sections of the n-type base region <NUM> that adjoin the Schottky metal <NUM> form JFETs (Junction Field-Effect Transistors) that help to prevent high leakage currents at the Schottky contact when the diode is in a blocking state.

The pn diode may become active, when a current between the anode A and the cathode K becomes high enough for the voltage between the anode A and the base region <NUM> to reach the forward voltage of the pn junctions between the p-type emitter regions <NUM> and the base region <NUM>. Operating the diode in an operating mode in which the pn-diode is active, however, is not desirable, because this may cause degradation of the WBG semiconductor body <NUM>.

In the following "maximum Schottky current" denotes the maximum current that can flow through the diode in the Schottky mode. The "Schottky mode" is an operating mode in which the voltage between the anode A and the base region <NUM> is below the forward voltage of the pn-junction. This maximum Schottky current is dependent on this specific design of the Schottky diode and, in particular, the size of the semiconductor body <NUM>.

Diodes of the type shown in <FIG> are commercially available. Usually, the maximum Schottky current can be seen from the data sheet of the respective device. Examples of such diodes include the following diodes available from Infineon Technologies AG, Munich: IDDD04G65C6, IDDD06G65C6, IDDD08G65C6, IDDD10G65C6, IDDD12G65C6, IDDD16G65C6, IDDD20G65C6. Each of these diodes has a voltage blocking capability of 650V and a current rating of between 4A and 20A, dependent on the type.

Claim 1:
An electronic circuit, comprising:
a half-bridge with a first transistor device (<NUM>) and a second transistor device (1a);
a first biasing circuit (<NUM>) connected in parallel with a load path of the first transistor device (<NUM>) and comprising a first electronic switch (<NUM>);
a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and
a drive circuit arrangement (DRVC) configured to
receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina),
drive the first transistor device (<NUM>) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and
drive the second transistor device (1a) and the first electronic switch (<NUM>) based on the second half-bridge input signal (Sina),
wherein the drive circuit arrangement (DRVC) comprises:
a first drive circuit (<NUM>) configured to drive the first transistor device (<NUM>) based on a first input signal (Sin1),
a second drive circuit (<NUM>) configured to drive the first electronic switch (<NUM>) based on a second input signal (Sin2),
a third drive circuit (2a) configured to drive the second transistor device (1a) based on a third input signal (Sin3), and
a fourth drive circuit configured to drive the second electronic switch (31a) based on a fourth input signal (Sin4),
characterized in that
each of the first input signal (Sin1) and the fourth input signal (Sin4) is dependent on the first half-bridge input signal (Sin), and
in that each of the second input signal (Sin2) and the third input signal (Sin3) is dependent on the second half-bridge input signal (Sina).