Patent Description:
The JTAG interface is a well-known interface established by the Joint Test Action Group (JTAG). The JTAG interface is incorporated into IEEE <NUM> (referred to herein as the "JTAG standard"), which is a standard defining boundary scan test logic for integrated circuits (ICs). The JTAG interface provides a <NUM>-pin interface that uses serial data shifting to perform a multitude of test and debug functions on devices. The JTAG standard includes various rules that define how a JTAG controller should operate, such as the IDCODE register is <NUM>-bits and the BYPASS instruction inserts a one register delay on the shift chain. The standard further specifies that the JTAG controller operates in two phases. First, the instruction phase, where an instruction is serially shifted into the controller. Second, the data phase, where data associated with the active instruction is shifted into the selected JTAG data register. The data register length varies by instruction, but the instruction register length should remain constant.

The JTAG standard also includes methods for chaining multiple JTAG controllers together. One technique includes daisy chaining each JTAG controller across multiple devices so that the output of one is coupled to the input of the next, where the JTAG input is on the first device and the JTAG output is on the last device. This technique allows for creation of one long serial shift chain on a circuit board having multiple devices. The daisy chain technique was developed for connecting multiple chips on a board. Consider, however, a multi-die integrated circuit (IC) package having multiple devices with JTAG controllers coupled in daisy chain fashion as described above. From the outside, the JTAG network in the IC package is designed to appear coupled in daisy chain fashion as described above. From the outside, the JTAG network in the IC package is designed to appear as a single JTAG controller to the user. To accomplish this and maintain compliance with the JTAG standard, some sacrifices are necessary that affect JTAG performance. For example, as noted above, the BYPASS instruction requires that only a single delay be set between the data input and the data output. However, the data input is to the first device in the chain and the data output is from the last device in the chain. To comply with the JTAG standard, the multi-die IC package must include a long wire that routes through all die therein from first to last. Such a long wire limits the maximum frequency at which the JTAG interface can operate for a multi-die package.

<CIT> describes integrated circuits including a first input interconnect, a second input interconnect, an output interconnect, a shift register, a select register, a test access port (TAP) controller, and select register decode circuitry. The TAP controller is coupled to the first input interconnect and the select register, and the TAP controller is configured to shift a select value provided on the first input interconnect into the select register. The select register decode circuitry is configured to control, based on the select value, which of a plurality of test data output signals are provided to the output interconnect, where the plurality of test data output signals includes a first test data output signal and a second test data output signal. The first test data output signal is provided by the shift register, and the second test data output signal is received from a second integrated circuit on the second input interconnect.

<CIT> describes apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one example, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one example, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one example, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

<CIT> describes a test system having a package containing a number of die. There is a JTAG controller for each of the die. There is also master/slave selector input for each of the JTAG controllers. A boundary scan register link connects at least two of the die.

Techniques for implementing a JTAG device chain in a multi-die integrated circuit are described. In an example, an integrated circuit (IC) package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS) is described. The IC package includes: a master integrated circuit (IC) die including a master Joint Test Action Group (JTAG) controller and a master wrapper circuit coupled to the master JTAG controller; a slave IC die including a slave JTAG controller and a slave wrapper circuit coupled to the slave JTAG controller; a forwarding path coupling an output of the master wrapper circuit to a first input of the slave wrapper circuit; and a master return path coupling a first output of the slave wrapper circuit to an input of the master wrapper circuit; wherein the master wrapper circuit couples the TDI of the TAP to a TDI of the master JTAG controller, and selectively couples, in response to a first control signal, the TDO of the TAP to either the master return path or a TDO of the master JTAG controller.

In another example, an integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select multi-die IC package; a master return path coupled to the first input; and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.

In another example, a method of testing a multi-die integrated circuit (IC) package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), the multi-die IC package further including a master IC die and a slave IC die, is described. The method includes: coupling, by a master wrapper circuit in the master IC die, in response to a first control signal output by a first control circuit in the master IC die, the TDO of the TAP to a master return path from the slave IC die to the master IC die; receiving an instruction at a master JTAG controller in the master IC die through the TDI of the TAP, and at a slave JTAG controller in the slave IC die through a forwarding path from the master IC die to the slave IC die; determining, by the first control circuit, that the instruction requires data to be routed only through the master IC die and changing state of the first control signal; and coupling, by the master wrapper circuit, in response to the first control signal output by the first control circuit, the TDO of the TAP to a TDO of the master JTAG controller.

These and other aspects may be understood with reference to the following detailed description.

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with an example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described. In this respect, the invention is defined by the appended claims.

Techniques for implementing a JTAG device chain in a multi-die integrated circuit are described. In examples, the JTAG controllers on master and slave IC die in the package are daisy chained together through the package (e.g., through an interposer). The primary JTAG interface, the four-signal interface exposed to the user, is only active on the master IC die. The serial shift chain starts in the master and propagates to the first slave. The connection from master to slave is implemented using a JTAG interface that connects through the package (e.g., through the interposer). This connection continues from slave to slave until the last slave. The package configures the last slave to loop the chain to a master return path. The master return path is used to drive the JTAG data back to the master die in order to send it out the TDO of the JTAG interface of the package. In examples, the return path on each die has a rebuffering element to improve performance of the JTAG interface. These and further aspects of the disclosed techniques can be understood with reference to the description of the drawings.

<FIG> is a block diagram depicting a multi-die integrated circuit (IC) device <NUM> according to an example. The multi-die IC device <NUM> includes a master IC die <NUM> and at least one slave IC die <NUM>-<NUM>. <NUM>-n, where n is an integer greater than zero (collectively slave dies <NUM>). The master IC die <NUM> and the slave IC die(s) <NUM> are collectively referred to as IC dies <NUM>. The master IC die <NUM> and the slave IC die(s) <NUM> are disposed in a multi-die IC package <NUM>. In examples, the IC dies <NUM> are disposed side-by-side on an interposer (sometimes referred to as a <NUM>. 5D package). In other examples, the IC dies are disposed in a three-dimensional stack, one on top of another (referred to as a 3D package). The coupling of master IC die <NUM> with the slave IC die(s) <NUM> described herein does not presume any specific structure of the IC dies <NUM> within the multi-die IC package <NUM>. <FIG> described below show two example structures of the multi-die IC package <NUM> in which the techniques described herein for connecting JTAG devices can be employed.

The multi-die IC package <NUM> includes a test access port (TAP) <NUM> comprising a test data input (TDI), a test data output (TDO), a test mode select (TMS), and a test clock (TCK). The TDI, TDO, TMS, and TCK of the TAP <NUM> comprise external contacts of the multi-die IC package <NUM> and are accessible by an external tester. Each of the master IC die <NUM> and the slave IC die(s) <NUM> include a JTAG controller <NUM> and a wrapper circuit <NUM> coupled to the JTAG controller <NUM>. The TMS and the TCK of the TAP <NUM> are coupled to a TMS and a TCK, respectively, of each JTAG controller in the IC dies <NUM>. Together with control logic, the wrapper circuit <NUM> in each IC die <NUM> configures the IC die <NUM> as either a master or a slave. In the example, the master IC die <NUM> is configured as a master. Together with control logic, the wrapper circuit <NUM> in each IC die <NUM> configures the IC die <NUM> to route JTAG input to the same die or to a next die in the chain. In the example, the master IC die <NUM> is configured in the master configuration, and each slave IC die <NUM> is configured in the slave configuration.

In the master configuration, within the master IC die <NUM>, the wrapper circuit <NUM> couples the TDI to the JTAG controller <NUM>. The master IC die <NUM> dynamically operates in either the same die configuration or the next die configuration depending on the JTAG instruction. In the same die configuration, the wrapper circuit <NUM> in the master IC die <NUM> couples the TDO of the JTAG controller <NUM> to the TDO of the TAP <NUM>. Thus, in the same die configuration, JTAG data only propagates through the master IC die <NUM> during the data phase. During the instruction phase, data propagates through all IC die <NUM> regardless of same/next die configuration. In the next die configuration, the wrapper circuit <NUM> in the master die <NUM> couples the TDO of the JTAG controller <NUM> to a forwarding path <NUM> that serially couples each slave IC die <NUM> to the master IC die <NUM>. Thus, in the next die configuration, JTAG data propagates from the master IC die <NUM> to the slave IC die <NUM>-<NUM>.

In the slave configuration, the wrapper circuit <NUM> in each slave IC die <NUM> couples the forwarding path <NUM> to the TDI of its respective JTAG controller <NUM>. Further, each slave IC die <NUM> operates in the next die configuration. In the next die configuration, the wrapper circuit <NUM> in each slave IC die <NUM> couples the TDO of its respective JTAG controller <NUM> to the forwarding path <NUM>. Thus, JTAG data propagates from the master IC die <NUM> serially through each slave IC die <NUM> until being consumed by the slave IC die <NUM>-n.

A master return path <NUM> serially couples each slave IC die <NUM> to the master IC die <NUM>. The multi-die IC package <NUM> is configured to couple the forwarding path <NUM> to the master return path <NUM> after the slave IC die <NUM>-n. In the next die configuration, the wrapper circuits <NUM> in the slave IC dies <NUM> function to form the master return path <NUM> to the master IC die <NUM>. In the next die configuration, the wrapper circuit <NUM> in the master IC die <NUM> couples the master return path <NUM> to the TDO of the TAP <NUM>. This allows JTAG data to be shifted in through the TDI of the TAP <NUM> to each IC die <NUM> and back out through the TDO of the TAP <NUM>. As discussed below, the master IC die <NUM> can be configured in the same die configuration in cases where the instruction requirements dictate only the master IC die <NUM> be connected to the TAP <NUM> (e.g., for BYPASS or IDCODE instructions). The master IC die <NUM> can be configured in the next die configuration in cases where the instruction requirements dictate all IC die <NUM> be connected to the TAP <NUM> (e.g., for EXTEST and SAMPLE/PRELOAD instructions).

<FIG> is a block diagram depicting different signal interfaces of an IC die <NUM> according to an example. The IC die <NUM> includes an interface <NUM> comprising four contacts EXT_TDI, EXT_TDO, EXT_TCK, and EXT_TMS respectively designated by contacts <NUM>-<NUM> through <NUM>-<NUM>. The contacts <NUM>-<NUM> and <NUM>-<NUM> of the interface <NUM> are coupled to the TCK and TMS of the TAP <NUM>, respectively (e.g., EXT_TCK receives TCK and EXT_TMS receives TMS). If the IC die <NUM> is a master, the contacts <NUM>-<NUM> and <NUM>-<NUM> of the interface <NUM> are coupled to the TDI and TDO of the TAP <NUM>, respectively (e.g., EXT_TDI receives TDI and EXT_TDO supplies TDO). If the IC die <NUM> is a slave, the contacts <NUM>-<NUM> and <NUM>-<NUM> are unconnected (e.g., high-impedance).

The IC die <NUM> includes an interface <NUM> comprising four contacts INT_TDO, INT_TDI, INT_TDO_MR_OUT, and INT_TDO_MR_IN respectively designated by contacts <NUM>-<NUM> through <NUM>-<NUM>. The interface <NUM> is not exposed outside the multi-die IC package <NUM>. Rather, the interface <NUM> is only coupled to routing disposed inside the multi-die IC package <NUM>.

The JTAG controller <NUM> includes an interface <NUM> comprising JTAG_TDI, JTAG_TDO, JTAG_TCK, and JTAG_TMS respectively designated by contacts <NUM>-<NUM> through <NUM>-<NUM>. The wrapper circuit <NUM> in the IC die <NUM> (shown in <FIG>) couples EXT_TCK and EXT_TMS to JTAG_TCK and JTAG_TMS, respectively. That is, the clock and mode select signals pass through the wrapper circuit <NUM> to the JTAG controller <NUM>. The wrapper circuit <NUM> selectively couples JTAG_TDI and JTAG_TDO to the interface <NUM> and the interface <NUM> depending on the master/slave and same/next configurations.

<FIG> is a block diagram depicting JTAG circuitry <NUM> according to an example. The JTAG circuitry <NUM> includes a wrapper circuit <NUM>, a JTAG controller <NUM>, a control circuit <NUM>, and a master return circuit <NUM>. EXT_TDI, EXT_TDO, INT_TDI, INT_TDO, and INT_TDO_MR_OUT are each coupled to the wrapper circuit <NUM>. The wrapper circuit <NUM> passes EXT_TCK and EXT_TMS to the JTAG controller <NUM>. The JTAG controller <NUM> is coupled to a boundary scan register (BSCAN <NUM>) in the IC die <NUM>. The wrapper circuit <NUM> receives control signals <NUM> from the control circuit <NUM>. The wrapper circuit <NUM> is further coupled to the master return circuit <NUM>. The master return circuit <NUM> provides an interface between INT_TDO_MR_IN and the wrapper circuit <NUM>. The wrapper circuit <NUM> includes multiplexing logic, as described further below, that is controlled by the control circuit <NUM>.

<FIG> is a block diagram depicting a wrapper circuit <NUM> as coupled to a JTAG controller <NUM>, a master return circuit <NUM>, and a control circuit <NUM> according to an example. The wrapper circuit <NUM> includes multiplexers <NUM> and <NUM>, demultiplexers <NUM> and <NUM>. The multiplexer <NUM> includes a first input ("<NUM>" input) coupled to EXT_TDI, a second input ("<NUM>" input) coupled to INT_TDI, and an output coupled to JTAG_TDI of the JTAG controller <NUM>. The demultiplexer <NUM> includes an input coupled to JTAG_TDO of the JTAG controller <NUM>, a first output ("<NUM>" output) coupled to INT_TDO, and a second output ("<NUM>" output) coupled to a second input ("<NUM>" input) of the multiplexer <NUM>. The multiplexer <NUM> includes a first input ("<NUM>" input) coupled to an output of the master return circuit <NUM>, the second input described above, and an output coupled to an input of the demultiplexer <NUM>. The demultiplexer <NUM> includes a first output ("<NUM>" output) coupled to EXT_TDO and a second output ("<NUM>" output) coupled to INT_TDO_MR_OUT.

In an example, the master return circuit <NUM> includes a flip-flop <NUM> and a falling-edge flip-flop <NUM>. As used herein, a "falling-edge" flip-flop loads data at the input on each falling edge of the applied clock signal, as opposed to each leading edge of the clock signal. A falling-edge flip-flop is indicated in the drawings by a bubble at the clock port. An input (D) of the flip-flop <NUM> is coupled to INT_TDO_MR_IN. An output (Q) of the flip-flop is coupled to an input (D) of the falling-edge flip-flop <NUM>. An output (Q) of the falling-edge flip-flop <NUM> is coupled to the first input (<NUM>) of the multiplexer <NUM>. The clock ports of the flip-flop <NUM> and the falling-edge flip-flop <NUM> are coupled to EXT_TCK.

The control circuit <NUM> includes an input <NUM> coupled to an output of the JTAG controller <NUM>. The control circuit <NUM> generates control signals <NUM>-<NUM> and <NUM>-<NUM>, referred to as slave and same, respectively. The control signal <NUM>-<NUM> is coupled to control ports of the multiplexer <NUM> and the demultiplexer <NUM>. The control signal <NUM>-<NUM> is coupled to control ports of the demultiplexer <NUM> and the multiplexer <NUM>.

<FIG> is a block diagram depicting a JTAG controller <NUM> according to an example. The BSCAN register <NUM> is shown for clarity and is not part of the JTAG controller <NUM>, but rather distributed throughout the input/outputs of the IC die <NUM>. The JTAG controller <NUM> includes a TAP controller <NUM>, instruction logic <NUM>, a device ID register <NUM>, a bypass register <NUM>, other register(s) <NUM>, a demultiplexer <NUM>, a multiplexer <NUM>, and a multiplexer <NUM>. The instruction logic <NUM> includes instruction register <NUM> and instruction decoder <NUM>. The device ID register <NUM>, a bypass register <NUM>, and other register(s) <NUM> together with the BSCAN register <NUM> comprise data logic <NUM>.

JTAG_TDI is coupled to an input of the demultiplexer <NUM>. Outputs of the demultiplexer <NUM> are coupled to inputs of the BSCAN register <NUM>, the other register(s) <NUM>, the bypass register <NUM>, the device ID register <NUM>, and the instruction register <NUM>. Outputs of the BSCAN register <NUM>, the other register(s) <NUM>, the bypass register <NUM>, and the device ID register <NUM> are coupled to inputs of the multiplexer <NUM>. An output of the multiplexer <NUM> is coupled to a first input of the multiplexer <NUM>. A first output of the instruction register <NUM> is coupled to a second input of the multiplexer <NUM>. A second output of the instruction register <NUM> is coupled to an input of the instruction decoder <NUM>. An output of the multiplexer <NUM> is coupled to the JTAG_TDO.

A first output of the instruction decoder <NUM> is coupled to a control input of the multiplexer <NUM>. A second output of the instruction decoder <NUM> is coupled to a first input <NUM>-<NUM> of the control circuit <NUM>. Inputs of the TAP controller <NUM> are coupled to JTAG_TCK and JTAG_TMS. A first output of the TAP controller <NUM> is coupled to an input <NUM>-<NUM> of the control circuit <NUM>. A second output of the TAP controller <NUM> is coupled to the instruction logic <NUM>. A third output of the TAP controller <NUM> is coupled to the data logic <NUM>. A fourth output of the TAP controller <NUM> is coupled to a control input of the demultiplexer <NUM>.

In operation, the TAP controller <NUM> implements a state machine having a plurality of states that control setting and retrieving information from a selected register. Transitions between states of the TAP controller <NUM> are controlled by the JTAG_TMS signal sampled according to the JTAG_TCK signal. The demultiplexer <NUM> selectively couples the JTAG_TDI to an input of one of the registers, and the multiplexer <NUM> selectively couples an output of one of the data registers to an input of the multiplexer <NUM>. The multiplexer <NUM> then selects either an output of one of the data registers or the output of the instruction register <NUM>. The TAP controller <NUM> controls the demultiplexer <NUM> and the multiplexer <NUM> based on the phase (instruction phase or data phase). The instruction decoder <NUM> controls the multiplexer <NUM> based on the current instruction. The states of the TAP controller <NUM> are described in detail in the IEEE <NUM> standard and are well-known. In particular, the TAP controller <NUM> includes a shift data state, which controls when data is shifted into one of the data registers. Serial data transfers occur when the shift data state is in an active logic state (e.g., active logic low according to IEEE <NUM>). The bypass register <NUM> is typically a <NUM>-bit register that allows information on the JTAG bus intended for another device to bypass the JTAG controller of a prior device. The device ID register <NUM> can store an identifier for the device. The structure of the JTAG controller <NUM> shown in <FIG> is just one example structure. Those skilled in the art will appreciate that the techniques described herein can be employed with JTAG controllers having other structures.

<FIG> is a block diagram depicting the master IC die <NUM> coupled to the slave IC die <NUM>-<NUM> according to an example. In the example of <FIG>, the slave IC die(s) <NUM> include only the slave IC die <NUM>-<NUM>. The master IC die <NUM> includes a master wrapper circuit <NUM> and a master JTAG controller <NUM>. The slave IC die <NUM>-<NUM> includes a slave wrapper circuit <NUM> and a slave JTAG controller <NUM>. In <FIG>, reference characters having the suffix "M" are associated with the master IC die <NUM>, and reference characters having the suffix "S" are associated with the slave IC die <NUM>.

With reference to <FIG>, the master IC die <NUM> is configured as a master. The control circuit <NUM> in master IC die <NUM> sets the slave signal to select "<NUM>" so that multiplexer <NUM> selects EXT_TDI (<NUM>-<NUM>) and demultiplexer <NUM> selects EXT_TDO (<NUM>-<NUM>). The multi-die IC package <NUM> includes routing <NUM>-<NUM> that couples EXT_TDI to TDI of the TAP <NUM>, and routing <NUM>-<NUM> that couples EXT_TDO to TDO of the TAP <NUM>. As discussed above, TMS and TCK of the TAP <NUM> is coupled to EXT_TMS and EXT_TCK of each IC die <NUM> and are omitted from <FIG> for clarity. Since the control circuit <NUM> sets the signal slave to logic "<NUM>", the master wrapper circuit <NUM> couples EXT_TDI to JTAG_TDI of the master JTAG controller <NUM>. INT_TDI (<NUM>-<NUM>) and INT_TDO_MR_OUT (<NUM>-<NUM>) of the master IC die <NUM> are unconnected within multi-die IC package <NUM> (e.g., high-impedance).

The multi-die IC package <NUM> includes routing <NUM>-<NUM> that couples INT_TDO (<NUM>-<NUM>) of the master IC die <NUM> to INT_TDI (<NUM>-<NUM>) of the slave IC die <NUM>-<NUM>. The slave IC die <NUM>-<NUM> is configured as a slave. The control circuit <NUM> in slave IC die <NUM>-<NUM> sets the slave signal to select "<NUM>" so that multiplexer <NUM> selects INT_TDI and demultiplexer <NUM> selects INT_TDO_MR_OUT. EXT_TDI (<NUM>-<NUM>) and EXT_TDO (<NUM>-<NUM>) of slave IC die <NUM>-<NUM> are unconnected within multi-die IC package <NUM> (e.g., high-impedance). The multi-die IC package <NUM> includes routing <NUM>-<NUM> that couples INT_TDO (<NUM>-<NUM>) of the slave IC die <NUM>-<NUM> to INT_TDO_MR_IN (<NUM>-<NUM>) of the slave IC die <NUM>-<NUM>. That is, the multi-die IC package <NUM> couples the forwarding path <NUM> to the master return path <NUM> after the slave IC die <NUM>-<NUM> (since the slave IC die <NUM>-<NUM> is the last slave in the chain).

Since slave IC die <NUM>-<NUM> is configured as a slave, the control circuit <NUM> sets the signal "same" to select "<NUM>" so that the demultiplexer <NUM> couples JTAG_TDO of the slave JTAG controller <NUM> to INT_TDO (<NUM>-<NUM>) and the multiplexer <NUM> couples the output (Q) of the falling-edge flip-flop <NUM> to the demultiplexer <NUM>. Since the control circuit <NUM> sets the signal slave to logic "<NUM>", the demultiplexer <NUM> selects INT_TDO_MR_OUT (<NUM>-<NUM>). Thus, the master return circuit <NUM> of the master return path <NUM> is coupled to INT_TDO_MR_OUT (<NUM>-<NUM>) of the slave IC die <NUM>-<NUM>.

The multi-die IC package <NUM> includes routing <NUM>-<NUM> that couples INT_TDO_MR_OUT (<NUM>-<NUM>) of the slave IC die <NUM>-<NUM> to INT_TDO_MR_IN (<NUM>-<NUM>) of the master IC die <NUM>. This connects the master return circuit <NUM> of the master IC die <NUM> to the master return path <NUM>. The control circuit <NUM> in the master IC die <NUM> sets the state of the signal "same" dynamically according to the instruction loaded to instruction register <NUM> in the master JTAG controller <NUM>. If the instruction is of a type that requires JTAG data to only be shifted through the master IC die <NUM>, the control circuit <NUM> sets the signal "same" to logic "<NUM>" (e.g., BYPASS, IDCODE). If the instruction is of a type that requires JTAG data to be shifted through both the master IC die <NUM> and the slave IC die <NUM>-<NUM>, the control circuit <NUM> sets the signal "same" to logic "<NUM>" (e.g., EXTEST, SAMPLE/PRELOAD).

When the signal "same" is set to logic "<NUM>", the demultiplexer <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to INT_TDO (<NUM>-<NUM>) of the master IC die <NUM>. Also, the multiplexer <NUM> couples the output (Q) of the falling-edge flip-flop <NUM> to the input of the demultiplexer <NUM>. As the master IC die <NUM> is configured as a master, the demultiplexer <NUM> couples the output of the multiplexer <NUM> to EXT_TDO (<NUM>-<NUM>), which is coupled to TDO of the TAP <NUM> by the routing <NUM>-<NUM>. Thus, when the signal "same" is set to logic "<NUM>", the master wrapper circuit <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to the forwarding path <NUM> and couples the master return path <NUM> to EXT_TDO of the master IC die <NUM>.

When the signal "same" is set to logic "<NUM>", the demultiplexer <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to the input ("<NUM>") of the multiplexer <NUM>. That is, the JTAG_TDO of the master JTAG controller <NUM> is disconnected from INT_TDO (<NUM>-<NUM>) and the forwarding path <NUM>. The multiplexer <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to the input of the demultiplexer <NUM>, which in the master IC die <NUM> is selecting EXT_TDO (<NUM>-<NUM>). Thus, when the signal "same" is set to logic "<NUM>", the master wrapper circuit <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to EXT_TDO (<NUM>-<NUM>), which in turn is coupled to TDO of the TAP <NUM>. In such case, the master IC die <NUM> is disconnected from the forwarding path <NUM> and the master return path <NUM>.

Table <NUM> shows a truth table for the control circuit <NUM> in an IC die <NUM>.

In summary, if the IC die <NUM> is configured as a slave, then the signal "slave" is set to logic "<NUM>" (true) and the signal "same" is set to logic "<NUM>" (false) regardless of the instruction type. Thus, a slave IC die <NUM> is always configured to couple the JTAG_TDO of its JTAG controller <NUM> to the forwarding path <NUM> and its master return circuit <NUM> to the master return path <NUM>. If the IC die <NUM> is configured as a master, then its control circuit <NUM> performs dynamic routing to EXT_TDO based on the type of instruction. If the instruction is the type indicating the same die (e.g., JTAG data only for master IC die <NUM>), then the control circuit <NUM> sets the signal "same" to logic "<NUM>" (true). Otherwise, the control circuit <NUM> sets the signal "same" to logic "<NUM>" (false).

The control circuit <NUM> receives information of the type of instruction from the instruction decoder <NUM>. Based on the result of the instruction decoder <NUM>, the control circuit <NUM> sets the state of the signal "same" to route the JTAG data as required (either only in the master or to the entire chain). Instruction data is routed to all IC die <NUM> on the chain. Thus, control circuit <NUM> in the master IC die <NUM> initially sets the signal "same" to logic "<NUM>" (false). Once the instruction is decoded, the control circuit <NUM> in the master IC die <NUM> can change the state of the signal "same" to be "<NUM>" (true) (e.g., for a BYPASS instruction). After the instruction is executed, the control circuit <NUM> in the master IC die <NUM> resets the signal "same" to logic "<NUM>" (false) for the next instruction. The control circuit <NUM> can reset the signal "same" to logic "<NUM>" (false) based on output from the TAP controller <NUM>, which indicates the previous instruction has been completed.

In the examples described, the control circuit <NUM> is external to the JTAG controller <NUM>. In other examples, a portion of the control circuit <NUM> can be incorporated into the JTAG controller <NUM>. For example, the functionality of the control circuit <NUM> with respect to the signal "same" can be implemented in the instruction decoder <NUM>. In such case, the JTAG controller <NUM> can output the signal "same" for use by the wrapper circuit <NUM>. The IC die <NUM> in the multi-die IC package <NUM> are disposed in a fixed configuration with respect to which die is the master and which die is/are the slave(s). In such case, the signal "slave" is a fixed value for the master IC die <NUM> and each slave IC die <NUM>. In examples, the signal "slave" can be generated by a nonvolatile memory element (e.g., e-fuse or the like).

<FIG> illustrates a side-view of a multi-die IC package <NUM> according to an example. The multi-die IC package <NUM> includes a substrate <NUM> (e.g., an interposer or package substrate) having a plurality of contacts <NUM> on one side, and one or more layers of routing <NUM> on the opposite side. The substrate <NUM> includes vias <NUM> that couple the contacts <NUM> to the routing <NUM>. IC die <NUM> are attached to the substrate <NUM> in electrical communication with the routing <NUM> through contacts <NUM>. In the example, the multi-die IC package <NUM> includes a master IC die <NUM> and a slave IC die <NUM>-<NUM>. The routing <NUM> and <NUM> shown in <FIG> is implemented in the routing <NUM> of the substrate <NUM>. The contacts <NUM> include contacts for the interface <NUM> and the interface <NUM> of each IC die <NUM>. As noted above, some contacts of the interface <NUM> or the interface <NUM> can be unconnected depending on the master/slave configuration of the IC die <NUM>. The contacts <NUM> include contacts for the TAP <NUM>.

<FIG> illustrates a side-view of a multi-die IC package <NUM> according to another example. In this example, the multi-die IC package <NUM> includes a substrate <NUM> (e.g., an interposer or package substrate) having a plurality of contacts <NUM> on one side, and one or more layers of routing <NUM> on the opposite side. The substrate <NUM> includes vias <NUM> that couple the contacts <NUM> to the routing <NUM>. An IC die <NUM> (e.g., the master IC die <NUM>) is attached to the substrate <NUM> in electrical communication with the routing <NUM> through contacts <NUM>. The master IC die <NUM> includes layers of routing <NUM> electrically coupled to the contacts <NUM> through vias <NUM>. Another IC die <NUM> (e.g., the slave IC die <NUM>-<NUM>) is mounted on top of the master IC die <NUM>. The slave IC die <NUM>-<NUM> includes layers of routing <NUM> facing the routing <NUM> of the master IC die <NUM>. This is referred to as an "active-on-active" configuration. The routing <NUM> is electrically connected to the routing <NUM> by contacts <NUM>. The routing <NUM> shown in <FIG> can be implemented using the routing <NUM>, the contacts <NUM>, and the routing <NUM>. The routing <NUM> shown in <FIG> can be implemented using the contacts <NUM>, the vias <NUM>, and the routing <NUM>. The contacts <NUM> include contacts for the TAP <NUM>.

<FIG> is a block diagram depicting an IC test system <NUM> according to an example. The IC test system <NUM> includes a tester <NUM> having a hardware platform <NUM> and a software platform <NUM>. As shown, the hardware platform <NUM> includes conventional components of a computing device, such as one or more central processing units (CPUs) <NUM>, system memory (e.g., random access memory (RAM) <NUM>), storage <NUM>, and a JTAG interface <NUM>. The CPUs <NUM> are configured to execute instructions, for example, executable instructions that perform one or more operations described herein, which may be stored in the RAM <NUM>. The storage <NUM> can store files, such as one or more boundary scan description language (BSDL) files <NUM>. The JTAG interface <NUM> is coupled to the multi-die IC device <NUM>. The software platform <NUM> includes an operating system (OS) <NUM>, a test program generator <NUM>, and a test program executive <NUM>. The OS <NUM> can be any operating system known in the art. The test program generator <NUM> accepts computer aided design (CAD) data as input in the form of a netlist, bill of materials, schematic, layout information, and the like or any combination thereof. The test program generator <NUM> uses the CAD data to generate test patterns for fault detection and isolation using JTAG. The test program executive <NUM> interfaces with the multi-die IC device <NUM>, executes the tests, and compares the results to expected values. The test program generator <NUM> and/or the test program executive <NUM> can consume the BSDL files <NUM>. A BSDL file <NUM> describes the boundary scan behavior of the device, including what JTAG standards are supported, signal mapping and package information, available instructions and which registers those instructions access, the type of boundary scan cell available for each signal, and the like.

As described above, the shift instruction register state (e.g., loading an instruction) is treated as a "next die" instruction (e.g., the signal "same" is logic "<NUM>" or false). This maintains a constant instruction register length for the multi-die IC package <NUM>. In the instruction phase, the flip-flops on the master return path <NUM> used for retiming must be accounted for when specifying the instruction. Within a single IC die <NUM>, the instruction register can be <NUM>-bits in length, for example. Since the multi-die IC package <NUM> includes multiple IC die <NUM>, the instruction register length increases by <NUM> bits for each added IC die <NUM> (<NUM> instruction bits and <NUM> return path bit) plus one additional bit for the return flip-flop in the master return circuit. The instruction register order for a master IC die <NUM> and one slave IC die <NUM>-<NUM> is: TDI -> <NUM>-bit (master instruction register) -> <NUM>-bit (slave instruction register) -> <NUM>-bit (slave return flop) -> <NUM>-bit (master return flop) -> TDO. The total instruction register length in this example is <NUM> bits.

The JTAG instruction decodes are extended to account for the extra bits. For example, the IDCODE instruction for just one IC die is <NUM>'h09 (<NUM>'b001001). In the notation, the first number (e.g., <NUM>) indicates the number of bits, the next letter (e.g., h or b) indicates hexadecimal or binary, and remaining portion indicates the value. The IDCODE instruction for the multi-die IC package <NUM> having one master IC die <NUM> and one slave IC die <NUM> is <NUM>'h927, where the instruction is formatted as follows:.

Since the IDCODE instruction is a "same" die instruction, the code loaded into the slave instruction register does not matter, as the data will never shift through the slave IC die <NUM>. It is described as <NUM>'h09 by way of example but could in practice be any value. The instruction register length for a multi-die IC package <NUM> is described in a BSDL file <NUM> for the device.

<FIG> are flow diagrams depicting a method of testing a multi-die IC package <NUM> according to an example. <FIG> shows a method <NUM> for operating the master IC die <NUM> during the testing. <FIG> shows a method for operating a slave IC die <NUM> during the testing.

The method <NUM> begins at step <NUM>, where the master IC die <NUM> configures itself as a master. The master wrapper circuit <NUM> in the master IC die <NUM> couples the TDI of the TAP <NUM> (through EXT_TDI) to the JTAG_TDI of the master JTAG controller <NUM> (<NUM>). The master wrapper circuit <NUM> couples the TDO of the TAP <NUM> (through EXT_TDO) to itself(<NUM>). The step <NUM> (including <NUM> and <NUM>) can be performed upon powering up the master IC die <NUM> and remain static throughout operation of the master IC die <NUM>.

At step <NUM>, the control circuit <NUM> in the master IC die <NUM> configures the master wrapper circuit <NUM> to propagate JTAG data to the next die (e.g., the signal "same" is set to logic "<NUM>" in the master IC die <NUM>). The JTAG_TDO of the master JTAG controller <NUM> is coupled to the forwarding path <NUM> (<NUM>). The master return path <NUM> is coupled to the TDO of the TAP <NUM> (through the master wrapper circuit <NUM> and EXT_TDO) (<NUM>). At step <NUM>, the JTAG controllers <NUM> in the multi-die IC package <NUM> receive the instruction formatted as described above.

At step <NUM>, the control circuit <NUM> in the master IC die <NUM> determines if the instruction is for same die or all dies. If the instruction is for all dies, the method <NUM> proceeds to step <NUM>, where the control circuit <NUM> maintains the state of the signal "same" (as logic "<NUM>" or false) and the configuration of the master wrapper circuit <NUM> stays the same (connecting the forwarding path <NUM> and the master return path <NUM>). If the instruction is for the same die, the method <NUM> proceeds to step <NUM>. At step <NUM>, the control circuit <NUM> in the master IC die <NUM> sets the signal "same" to logic "<NUM>" (true) to disable propagation of JTAG data to the next die. The master wrapper circuit <NUM> couples the JTAG_TDO of the master JTAG controller <NUM> to the TDO of the TAP <NUM>, disconnecting the forwarding path <NUM> and the master return path <NUM> (<NUM>). At step <NUM>, a tester loads/reads data to/from the JTAG controller(s) in the multi-die IC package <NUM>.

Referring to <FIG>, the method <NUM> begins at step <NUM>. At step <NUM>, the slave IC die <NUM> configures itself as a slave. The JTAG_TDI of the slave JTAG controller <NUM> is coupled to a previous master/slave on the forwarding path <NUM> (<NUM>). The slave wrapper circuit <NUM> couples itself to the next master/slave on the master return path <NUM> (<NUM>). The step <NUM> (including <NUM> and <NUM>) can be performed upon powering up the slave IC die <NUM> and remain static throughout operation of the slave IC die <NUM>.

At step <NUM>, the control circuit <NUM> in the slave IC die <NUM> configures the slave wrapper circuit <NUM> to propagate to the next die. The control circuit <NUM> in the slave IC die <NUM> sets the signal "same" to "<NUM>" (false). The slave wrapper circuit <NUM> couples the JTAG_TDO of the slave JTAG controller <NUM> to the forwarding path <NUM> (<NUM>). The slave wrapper circuit <NUM> couples the master return circuit <NUM> to the master return circuit of the next master/slave (<NUM>).

The JTAG circuitry <NUM> shown in <FIG> can be used in a programmable device, such as that shown in <FIG> below.

<FIG> is a block diagram depicting a programmable device <NUM> according to an example. The programmable device <NUM> includes a plurality of programmable integrated circuits (ICs) <NUM>, e.g., programmable ICs 1A, 1B, 1C, and 1D. In an example, each programmable IC <NUM> is an IC die disposed on an interposer <NUM>. Each programmable IC <NUM> comprises a super logic region (SLR) <NUM> of the programmable device <NUM>, e.g., SLRs 53A, 53B, 53C, and 53D. The programmable ICs <NUM> are interconnected through conductors on the interposer <NUM> (referred to as super long lines (SLLs) <NUM>). The JTAG circuitry <NUM> can be disposed in each programmable IC <NUM>, where one of the programmable IC <NUM> is configured as master and the remaining programmable IC <NUM> is/are configured as slave(s).

<FIG> is a block diagram depicting a programmable IC <NUM> according to an example. The programmable IC <NUM> can be used to implement one of the programmable ICs 1A-1D in the programmable device <NUM>. The programmable IC <NUM> includes programmable logic (PL) <NUM> (also referred to as a programmable fabric), configuration logic <NUM>, and configuration memory <NUM>. The programmable IC <NUM> can be coupled to external circuits, such as nonvolatile memory <NUM>, DRAM <NUM>, and other circuits <NUM>. The PL <NUM> includes logic cells <NUM>, support circuits <NUM>, and programmable interconnect <NUM>. The logic cells <NUM> include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits <NUM> include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits <NUM> can be interconnected using the programmable interconnect <NUM>. Information for programming the logic cells <NUM>, for setting parameters of the support circuits <NUM>, and for programming the programmable interconnect <NUM> is stored in the configuration memory <NUM> by the configuration logic <NUM>. The configuration logic <NUM> can obtain the configuration data from the nonvolatile memory <NUM> or any other source (e.g., the DRAM <NUM> or from the other circuits <NUM>). In some examples, the programmable IC <NUM> includes a processing system (PS) <NUM>. The PS <NUM> can include microprocessor(s), memory, support circuits, IO circuits, and the like. In some examples, the programmable IC <NUM> includes a network-on-chip (NOC) <NUM> and data processing engine (DPE) array <NUM>. The NOC <NUM> is configured to provide for communication between subsystems of the programmable IC <NUM>, such as between the PS <NUM>, the PL <NUM>, and the DPE array <NUM>. The DPE array <NUM> can include an array of DPE's configured to perform data processing, such as an array of vector processors. The programmable IC <NUM> can include a BSCAN register <NUM> coupled to the JTAG circuitry <NUM>, described above.

<FIG> illustrates a field programmable gate array (FPGA) implementation of the programmable IC <NUM> that includes the PL <NUM>. The PL <NUM> shown in <FIG> can be used in any example of the programmable devices described herein. The PL <NUM> includes a large number of different programmable tiles including configurable logic blocks ("CLBs") <NUM>, random access memory blocks ("BRAMs") <NUM>, input/output blocks ("IOBs") <NUM>, configuration and clocking logic ("CONFIG/CLOCKS") <NUM>, digital signal processing blocks ("DSPs") <NUM>, specialized input/output blocks ("I/O") <NUM> (e.g., configuration ports and clock ports), and other programmable logic <NUM> such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. In examples, the programmable IC <NUM> can include a BSCAN register <NUM> coupled to the JTAG circuitry <NUM>, described above.

In some PLs, each programmable tile can include at least one programmable interconnect element ("INT") <NUM> having connections to input and output terminals <NUM> of a programmable logic element within the same tile, as shown by examples included at the top of <FIG>. Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments <NUM>) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments <NUM>) can span one or more logic blocks. The programmable interconnect elements <NUM> taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated PL.

In an example implementation, a CLB <NUM> can include a configurable logic element ("CLE") <NUM> that can be programmed to implement user logic plus a single programmable interconnect element ("INT") <NUM>. A BRAM <NUM> can include a BRAM logic element ("BRL") <NUM> in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile <NUM> can include a DSP logic element ("DSPL") <NUM> in addition to an appropriate number of programmable interconnect elements. An IOB <NUM> can include, for example, two instances of an input/output logic element ("IOL") <NUM> in addition to one instance of the programmable interconnect element <NUM>. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element <NUM> typically are not confined to the area of the input/output logic element <NUM>.

In the pictured example, a horizontal area near the center of the die (shown in Fig. 3D) is used for configuration, clock, and other control logic. Vertical columns <NUM> extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the PL.

Some PLs utilizing the architecture illustrated in <FIG> include additional logic blocks that disrupt the regular columnar structure making up a large part of the PL. The additional logic blocks can be programmable blocks and/or dedicated logic.

Claim 1:
An integrated circuit, IC, package (<NUM>) having a test access port (<NUM>), TAP, comprising a test data input, TDI, test data output, TDO, test clock, TCK, and test mode select, TMS, the IC package comprising:
a master IC die (<NUM>) including a master Joint Test Action Group, JTAG, controller (<NUM>) and a master wrapper circuit (<NUM>) coupled to the master JTAG controller, the master wrapper circuit comprising a first demultiplexer (<NUM>) having an input coupled to a TDO of the master JTAG controller, and a first output coupled to an output (<NUM>-<NUM>) of the master wrapper circuit;
a slave IC die (<NUM>) including a slave JTAG controller (<NUM>) and a slave wrapper circuit (<NUM>) coupled to the slave JTAG controller;
a forwarding path (<NUM>) coupling the output of the master wrapper circuit to a first input (<NUM>-<NUM>) of the slave wrapper circuit; and
a master return path (<NUM>) coupling a first output (<NUM>-<NUM>) of the slave wrapper circuit to an input (<NUM>-<NUM>) of the master wrapper circuit; and
wherein the master wrapper circuit couples the TDI of the TAP to a TDI of the master JTAG controller, and selectively couples, based on a first control signal (<NUM>-<NUM>), the TDO of the TAP to either the master return path or the TDO of the master JTAG controller.