Patent Description:
Spin Transfer Torque (STT) MRAM is an example MRAM implementation with potential advantages, however, current STT-MRAM technologies use a high current to reorient the magnetization of the MTJ during a write operation.

According to embodiments of the present invention, a device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.

According to embodiments of the present invention, in a method of operating a device comprising a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer, and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layer are disposed below the free layer, the method includes applying a voltage across the pair of magneto-electric controlling layers, the voltage enhancing a magnetization of one of the magneto-electric controlling layers and reducing a magnetization in the other magneto-electric controlling layer, and controlling a magnetic field formed through the free layer; and inducing, by the magnetic field, a change in direction of a magnetization of the free layer, which changes a resistance in the MTJ memory element.

According to embodiments of the present invention, in a method of manufacturing a device includes providing a front-end-of-line (FEOL) substrate with bottom connections to an active circuit; forming a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy; forming a first and a second magnetoelectric controlling contacts electrically connected to the pair of magneto-electric controlling layers and the bottom connections; forming a read line on the pair of magneto-electric controlling layers; forming an Magnetic Tunnel Junction (MTJ) stack comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer on the read line; forming a top contact on the reference layer; and forming a bit line contact on the read line. Examples of prior art documents are <CIT> and <CIT>.

As used herein, "facilitating" an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by instructions executing on a remote processor, by sending appropriate data or commands to cause or aid the action to be performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.

One or more embodiments of the invention or elements thereof can be implemented in the form of a computer program product including a computer readable storage medium with computer usable program code for performing the method steps indicated. Furthermore, one or more embodiments of the invention or elements thereof can be implemented in the form of a system (or apparatus) including a memory, and at least one processor that is coupled to the memory and operative to perform exemplary method steps. Yet further, in another aspect, one or more embodiments of the invention or elements thereof can be implemented in the form of means for carrying out one or more of the method steps described herein; the means can include (i) hardware mod-ule(s), (ii) software module(s) stored in a computer readable storage medium (or multiple such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii); any of (i)-(iii) implement the specific techniques set forth herein.

Techniques of the present invention can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. For example, one or more embodiments may provide for:.

These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

Preferred embodiments of the present invention will be described below in more detail, with reference to the accompanying drawings:.

Single-phase Magneto-Electric (ME) materials are typically comprised of magnetic oxides including some heavy metals that can act as insulators and transducers between magnetic and electric systems. An electric field applied to an MR material will generate changes in the magnetization of the MR material. Similarly, a changing magnetic field applied to an electric dipole will be induced an electric polarization in the material. Since the ME materials are insulators, there is no current induced in a film in case of applying a voltage (no power consumption).

Working principles of ME-controlled magnetization change in a magnetic free layer (FL) can be relied on a controllable element of the ME layer. By applying different voltages (i.e., electric fields) into this ME layer, the magnetization of the ME layer can be changed, and thereby the magnetic field sensed by the magnetic FL can be changed and magnetic dipoles will be aligned to the applied magnetic field.

In a device including an ME layer and a FL separated by another non-magnetic layer, a magnetization of the ME layer is in-plane. By increasing of the voltage applied to the ME layer, a magnetization change can be induced in the ME layer. That change of magnetization in the ME layer can induce an increasing amount of the magnetic field on the FL and therefore, more domain will be aligned in a direction of the magnetic field on the FL and so the magnetic density in the FL will be changed (i.e., increased) by the voltage.

According to embodiments of the present invention and referring to <FIG>, a device <NUM> includes a Magnetic Tunnel Junction (MTJ) memory element <NUM> comprising a reference layer <NUM> (RL) and a free layer <NUM>, separated by a magnetic tunneling layer <NUM>. The device <NUM> includes magneto-electric (ME) controlling layers <NUM>. The device <NUM> includes a first ME layer <NUM> and a second ME layer <NUM>, which have in-plane uniaxial anisotropy in two different directions.

According to embodiments of the present invention, a net magnetization on the free layer <NUM> is zero. By applying a voltage (VW) in each direction (in-plane to ME layers) across a first ME controlling contact <NUM> and a second ME controlling contact <NUM>, the magnetization is enhanced in one of the first ME layer <NUM> and the second ME layer <NUM> that has a magnetization in the direction of the voltage VW, and reduces a magnetization in the other ME controlling layer. According to some aspects, a direction of magnetization of the second ME layer <NUM> may be parallel to a direct of magnetization of the reference layer <NUM>.

According to some aspects, the directions of magnetization of the first ME layer <NUM> and the second ME layer <NUM> are in-plane, and that the directions are opposite one another. Moreover, it should be understood that uniaxial anisotropy refers to a first ME layer having a preferred direction magnetization in one direction (e.g., to the right side of <FIG>) and a second ME layer having a preferred direction magnetization to an opposite direction (e.g., to the left side of <FIG>).

According to some embodiments, based on the voltage VW, the magnetic field seen by the free layer <NUM> can be changed both in its direction and intensity. Thus, according to one or more embodiments, the magnetic field can be employed to induce changes in domains of the free layer <NUM> to achieve variable magnetization and induce different resistances in the MTJ memory element <NUM> having the reference layer <NUM>, free layer <NUM>, and the magnetic tunneling layer <NUM>. According to some embodiments, different states (i.e., resistance) in the MTJ memory element <NUM> can be detected by a reading voltage (VR) on the MTJ memory element.

According to some embodiments, the MTJ memory element <NUM> is disposed on a read line <NUM> and under a top contact <NUM>.

The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the nonirradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.

There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as "etching". For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean <NUM> (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.

Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.

It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.

According to some embodiments, a pair of ME layers are used to write different states on the FL of the MTJ memory element. According to one or more embodiments, a net magnetization of the ME layers on the FL can be zero. According to at least one embodiment, the ME layers have in-plane uniaxial anisotropy magnetization in opposite directions, wherein a voltage applied on the ME layers can be controlled to induce a non-zero magnetization on the FL, and to move the magnetic dipoles in the FL in a direction according to the voltage. The voltage applied on the ME layers can be used to induce different magnetizations on the FL and different resistances for the MTJ memory element. It should be understood that MTJ resistance is dependent on an orientation of MTJ magnetization with the parallel and antiparallel states. The switching of the FL, which switches between the parallel and antiparallel states, can be controlled by adjusting a magnetic field generated by the ME layers.

According to some embodiments, the ME layers consume no power in writing data to the MTJ memory element. According to some aspects, the ME layers consume no power because the ME materials are dielectric and applying voltages does not generate current. For example, according to some embodiments, in a write operation, by applying a voltage, the magnetization of both ME layers enhances in one or other direction and applies some non-zero net magnetization in the FL in one or other in-plane direction.

By comparison, a conventional STT-RAM consumes power during the application of a current through an MTJ to write a state. According to some embodiments, for a read of the MTJ memory element, a state of resistance on the analogue (i.e., multi-state) MTJ memory element (e.g., the read line) can be detected.

<FIG> shows a method <NUM> of forming a magnetic domain based device with magnetoelectric layers, a write line, and a decoupled read path according to one or more embodiments of the present invention. According to some embodiments of the present invention and referring to <FIG>, the method <NUM> of forming a magnetic domain based device with magnetoelectric layers, a write line, and a decoupled read path includes providing a front-end-of-line (FEOL) substrate with bottom connections to an active circuit at step <NUM>. According to some embodiments, the method includes depositing two ME layers with opposite uniaxial anisotropy at step <NUM>. According to some embodiments, the method includes patterning the ME layers, e.g., by Ion Beam Etching (IBE), and forming the first and the second ME controlling contacts on the sides of the ME layers and in contact with the bottom connections at step <NUM>. According to example embodiments, a first conductive layer is deposited and patterned at step <NUM>. The first conductive layer can be formed of, for example, Ruthenium (Ru). According to some embodiments, the first conductive layer is patterned to form a read line. According to at least one aspect, an MTJ stack is deposited and patterned, e.g., by IBE, at step <NUM>. According to some embodiments, the MTJ stack includes a FL, tunnel barrier, and a RL. According to at least one embodiment, a top dielectric is deposited and planarized, e.g., by chemical-mechanical polish (CMP), at step <NUM>. According to some embodiments, the top dielectric is patterned, e.g., by reactive ion etch (RIE), to form a first opening exposing a top of the RL and a second opening exposing a top of the first conductive layer at step <NUM>. According to one or more embodiments, the first and the second openings are filled (e.g., by a metallization and a planarization, for example, by CMP) forming a top contact and a bit line contact, respectively, at step <NUM>.

According to some embodiments and referring to <FIG>, of forming a magnetic domain based device with magnetoelectric layers, a write line, and a decoupled read path according to one or more embodiments of the present invention. According to some embodiments of the present invention and referring to <FIG>, a front-end-of-line (FEOL) substrate <NUM> includes bottom connections <NUM>, <NUM>, to an active circuit (not shown). As shown in <FIG>, a first ME layer <NUM> and a second ME layer <NUM> with opposite uniaxial anisotropy are deposited on the substrate <NUM>. According to some embodiments of the present invention and referring to <FIG>, the first ME layer <NUM> and the second ME layer <NUM> are patterned, e.g., by IBE, and the first ME controlling contact <NUM> and the second ME controlling contact <NUM> are formed on the sides of the ME layers and in contact with the bottom connections <NUM>, <NUM>. According to some embodiments of the present invention and referring to <FIG>, a first conductive layer is deposited and patterned forming a read line <NUM>. The read line can be formed of, for example, Ruthenium (Ru). According to some embodiments of the present invention and referring to <FIG>, an MTJ stack is deposited and patterned, e.g., by IBE, wherein the MTJ stack includes a free layer <NUM>, a magnetic tunneling layer <NUM>, and a reference layer <NUM>. According to some embodiments of the present invention and referring to <FIG>, a top dielectric <NUM> is deposited over the device and planarized, e.g., by CMP. According to some embodiments, the top dielectric <NUM> is patterned, e.g., by reactive ion etch (RIE), to form a first opening <NUM> exposing a top of the reference layer <NUM> and a second opening <NUM> exposing a top of the read line <NUM>. According to some embodiments of the present invention and referring to <FIG>, the first and the second openings are filled, e.g., by a metallization and CMP, forming a top contact <NUM> and a bit line contact <NUM>.

According to some aspects, the bottom connections <NUM>, <NUM> are connected to respective word lines <NUM>, <NUM>. According to at least one embodiment, the word lines <NUM>, <NUM> can be used to write data to the device by controlling the voltage across the first ME layer <NUM> and the second ME layer <NUM>, and the bit line contact <NUM> can be used to read data from free layer <NUM>, by measuring a voltage between the top contact <NUM> and the bit line contact <NUM> of the device. For example, the word lines <NUM>, <NUM> can apply a signal to a gate, thereby driving a voltage to the bottom connections <NUM>, <NUM> and the first ME layer <NUM> and the second ME layer <NUM>. According to some aspects, the word lines <NUM>, <NUM> can be used to write data to the device by simultaneously controlling the voltage across the first ME layer <NUM> and the second ME layer <NUM>.

According to some embodiments, the read line <NUM> is decoupled from the top contact <NUM>.

<FIG> is method <NUM> of operating the magnetic domain based device of <FIG> according to one or more embodiments of the present invention. According to some embodiments, the method <NUM> of operating the magnetic domain based device comprises applying a voltage across the pair of magneto-electric controlling layers at step <NUM>, the voltage enhancing a magnetization of one of the magneto-electric controlling layers and reducing a magnetization in the other magneto-electric controlling layer, and controlling a magnetic field formed through the free layer, and inducing, by the magnetic field, a change in a direction of magnetization of the free layer at step <NUM>, which changes a resistance in the MTJ memory element. According to some embodiments, the application of the voltage across the pair of magneto-electric controlling layers controls a direction and an intensity of the magnetic field formed through the free layer. According to some embodiments, the method includes detecting the resistance in the MTJ memory element by a reading a voltage on the MTJ memory element at step <NUM>.

According to embodiments of the present invention, a device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer <NUM>, a free layer <NUM>, and a magnetic tunneling layer <NUM> between the reference layer and the free layer; and a pair of magneto-electric controlling layers <NUM>, <NUM>, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.

According to embodiments of the present invention, in a method <NUM> of operating a device comprising a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer, and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer, the method includes applying a voltage across the pair of magneto-electric controlling layers at step <NUM>, the voltage enhancing a magnetization of one of the magneto-electric controlling layers and reducing a magnetization in the other magneto-electric controlling layer, and controlling a magnetic field formed through the free layer; and inducing, by the magnetic field, a change in direction of a magnetization of the free layer at step <NUM>, which changes a resistance in the MTJ memory element.

According to embodiments of the present invention, in a method <NUM> of manufacturing a device includes providing a front-end-of-line (FEOL) substrate with bottom connections to an active circuit at step <NUM>; forming a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy at steps <NUM>-<NUM>; forming a first and a second magneto-electric controlling contacts electrically connected to the pair of magnetoelectric controlling layers and the bottom connections at step <NUM>; forming a read line on the pair of magnetoelectric controlling layers at step <NUM>; forming an Magnetic Tunnel Junction (MTJ) stack comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer on the read line at step <NUM>; forming a top contact on the reference layer at step <NUM>; and forming a bit line contact on the read line at step <NUM>.

As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates other-wise.

Claim 1:
A device comprising:
a Magnetic Tunnel Junction (MTJ) memory element comprising,
a reference layer,
a free layer, and
a magnetic tunneling layer between the reference layer and the free layer; and characterized by the device having
a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.