Patent Description:
This document pertains generally, but not by way of limitation, to integrated circuits and communication systems, and particularly, but not by way of limitation to digital predistortion for non-linear components, such as power amplifiers.

Communications over wired media, such as coaxial cable and over wireless media, such as RF transmission, often use a power amplifier (PA) in a transmitter to produce a signal for transmission over the medium. The PA circuit may include a PA with a nonlinear gain characteristic, such as gain compression, that occurs at higher power output levels. The nonlinear gain characteristic can lead to signal distortion at the higher power levels. Digital predistortion (DPD) is used to compensate for amplifier nonlinearities. A DPD circuit applies predistortion to the amplifier input signal. The predistortion is determined using an inverse model of the amplifier's transfer characteristic, including distortion terms. A goal of the predistortion is to reduce distortion in the transmitted signal due to the PA gain nonlinearity.

<CIT> relates to a high-frequency signal predistortion device and nonlinear distortion correcting device for a power amplifier.

<CIT>, <CIT> and <CIT> all relate to the use of tilt equalizers with DPD circuits.

Various examples described herein are directed to systems and methods implementing multi-component DPD where one DPD generates a pre-distorted signal that is provided to multiple PAs. For example, there are many contexts in which it is desirable to provide the same input signal to multiple PAs. One example is in cable television and related cable communications where the same input signal (e.g., representing different television channel signals or other signals) may be transmitted to different customers across different coaxial and/or fiber trunk lines. Another example is in mobile telephony. Some mobile telephony technologies, such as <NUM>th Generation (<NUM>) wireless systems, utilize electromagnetic beamforming that involves transmitting the same input signal from different antennas at different power levels and phases.

Because different PAs have different nonlinearities, a DPD trained for the transfer characteristic of one PA may not produce acceptable results when used with another PA (e.g., another PA having different nonlinearities). Accordingly, in a situation where multiple PAs receive a common input signal, it may be desirable to have a dedicated, trained DPD for each PA. Such an arrangement, however, may be expensive to build and resource-intensive to train.

The examples described herein address this and other problems by providing an adaption arrangement for a single DPD circuit that trains the DPD circuit to provide a pre-distorted signal that is suitable for use with multiple PAs. The multiple PAs may be arranged in parallel, with each PA receiving the pre-distorted signal generated by the DPD circuit.

An adaption circuit generates predistortion parameters for the DPD circuit to configure the DPD circuit to generate the pre-distorted signal for the multiple PAs. The adaption circuit receives the pre-distorted signal from the DPD circuit and feedback signals from the multiple PAs. From the pre-distorted signal and the feedback signals, the adaption circuit generates predistortion correlation data based on basis matrices and error vectors generated using the various feedback signals from the PAs.

The adaption circuit may sequentially sample feedback signals of the PAs. For each PA, the adaption circuit generates a basis matrix Y and error vector εgmpn. For example, a first basis matrix Y<NUM> and first error vector εgmp<NUM> are generated from a first feedback signal from a first PA and a corresponding portion of the pre-distorted signal. The first basis matrix Y<NUM> and first error vector εgmp<NUM> are used to generate and/or update predistortion correlation data. A second basis matrix Y<NUM> and second error vector εgmp2 are generated using a second feedback signal from the second PA. The second basis matrix Y<NUM> and the second error vector εgmp2 are then used to update the predistortion correlation data. The predistortion correlation data may be updated in this manner, for example, until all PAs have been sampled and used to make a corresponding update to the predistortion correlation data. The adaption circuit may use the updated predistortion correlation data to generate predistortion parameters θ̂k for the DPD circuit. The DPD circuit utilizes the predistortion parameters θ̂k to generate the pre-distorted signal that is provided to the multiple PAs.

<FIG> is a diagram showing one example of an environment <NUM> for implementing multi-component digital predistortion. The environment <NUM> includes a DPD circuit <NUM> and a plurality of power amplifiers 104A, 104B, 104C, 104N. Although four power amplifiers 104A, 104B, 104C, 104N are shown, the environment <NUM> may include any suitable number of power amplifiers, for example, any suitable number greater than one. According to the environment <NUM>, the DPD circuit <NUM> generates a pre-distorted signal v. The pre-distorted signal v is provided to a digital-to-analog converter (DAC) <NUM>. The DAC <NUM> generates an analog pre-distorted signal v. The analog pre-distorted signal v is provided to the PAs 104A, 104B, 104C, 104N, which generate respective output signals, for example, for wired or wireless transmission. <FIG> also shows an optional digital upconverter (DUC) <NUM>. The DUC <NUM> receives one or more baseband input signals, and up-converts them to an IF or RF carrier frequency. The DUC <NUM> provides an upconverted input signal to the DPD circuit <NUM>. In examples where the DUC <NUM> is present, the input signal provided to the DPD circuit <NUM> may be the up-converted input signal generated by the DUC <NUM>.

In the example of <FIG>, the outputs of the respective PAs 104A, 104B, 104C, 104N are provided to a feedback switching circuit <NUM> that selectively provides feedback signals yn from the various PAs 104A, 104B, 104C, 104N to a feedback analog-to-digital converter (ADC) <NUM>. For example, the feedback switching circuit <NUM> may have a first position forming a first signal path in which a feedback signal y<NUM> of the power amplifier 104A is provided to the feedback ADC <NUM>, a second position forming a second signal path in which a feedback signal y<NUM> of the power amplifier 104B is provided to the feedback ADC <NUM>, a third position forming a third signal path in which a feedback signal y<NUM> of the power amplifier 104C is provided to the feedback ADC <NUM>, and so on. The feedback ADC <NUM> provides a digital feedback signal yn to a capture buffer <NUM>. The digital feedback signal yn is a digital version of the feedback signal yn provided to the feedback ADC <NUM> by the feedback switching circuit <NUM>. It will be appreciated that other feedback circuitry arrangements may be used. For example, although one feedback ADC <NUM> is shown in <FIG>, some examples may use more than one feedback ADC <NUM>.

The capture buffer <NUM> may also receive the digital pre-distorted signal v from the output of the DPD circuit <NUM>. Although one capture buffer <NUM> is shown, in some examples, separate capture buffers may be included with one buffer to receive the feedback signal yn and another buffer to capture the pre-distorted signal v. A time alignment circuit <NUM> is configured to match or time align values of the feedback signal yn to corresponding values of the pre-distorted signal v. For example, the time alignment circuit <NUM> may match values of the pre-distorted signal v to values of the feedback signal yn that were generated therefrom. Sets of time-aligned values of the pre-distorted signal v and the feedback signal yn are provided to the adaption circuit <NUM>.

The adaption circuit <NUM> generates predistortion parameters θ̂k for the DPD circuit <NUM> from the feedback signal yn and pre-distorted signal v. In some examples, the predistortion parameters θ̂k include a set of coefficients that may be used by the DPD circuit <NUM> to implement a polynomial approximation of the inverse model of the PAs 104A, 104B, 104C, 104N. For example, the coefficients may be used as coefficients for taps of a digital filter that implements all or part of the DPD circuit <NUM>. Also, in some examples, the predistortion parameters θ̂k include a lookup table (LUT) that is applied by the DPD circuit <NUM> to generate the pre-distorted signal v.

<FIG> is a flowchart showing one example of a process flow <NUM> that may be executed in the environment <NUM> to train the DPD circuit <NUM>. At operation <NUM>, the feedback switching circuit is configured to provide a feedback signal from a first power amplifier 104A, 104B, 104C, 104N to the capture buffer <NUM> (e.g., via the feedback ADC <NUM>). This description will assume that the feedback signal y<NUM> from the PA 104A is provided first, however, any suitable PA 104A, 104B, 104C, 104N may be selected first. At operation <NUM>, the capture buffer <NUM> captures values of the feedback signal y<NUM> and corresponding values of the pre-distorted signal v. The feedback signal y<NUM> may be taken at the output of the DPD circuit <NUM> as shown in <FIG> or in, some examples, may be taken from the input of the DPD circuit <NUM> in a direct adaption arrangement.

At operation <NUM>, the adaption circuit <NUM> generates and/or updates predistortion correlation data. For example, the adaption circuit <NUM> may utilize the feedback signal y<NUM> and the corresponding values of the pre-distorted signal v to generate a basis matrix Y<NUM> and an error vector εgmp1. The basis matrix Y<NUM> describes features of the DPD circuit <NUM> chosen to reflect the dynamic composition of the inverse PA behavior, such as; past and present linear terms and past and present nonlinear terms. The error vector εgmp1 is an indication of the error between the estimated inverse PA response and the actual DPD output v. and the corresponding values of the pre-distorted signal v.

The adaption circuit <NUM> uses the basis matrix Y<NUM> and an error vector εgmp1 to generate predistortion correlation data. The predistortion correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryε. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y<NUM>. In some examples, the autocorrelation vector Ryy is given by Equation [<NUM>] below: <MAT> In Equation [<NUM>], an inner product is taken between the autocorrelation matrix (in this example Y<NUM>) and the Hermitian transpose of the autocorrelation matrix (indicated by the operator "H"). The result of the inner product is added to a previous iteration of the autocorrelation matrix Ryy. When the operation <NUM> is executed for the first time, the previous version of the autocorrelation matrix Ryy may be set to the null matrix (e.g., a matrix of zeros). In some examples, the autocorrelation matrix is a square matrix having an order based on the number of features in the basis matrix Y. For example, if the basis matrix Y has twenty features, then the autocorrelation matrix Ryy may be a <NUM> x <NUM> matrix.

The cross-correlation vector ryε indicates a correlation between the basis matrix Y and the error vector εgmp. In some examples, the cross-correlation vector ryε is given by Equation [<NUM>] below: <MAT> According to Equation [<NUM>], an inner product is taken between the Hermitian transpose of the basis matrix Y and the error vector εgmp. The result is added to a previous iteration of the cross-correlation vector ryε. When the operation <NUM> is executed for the first time, the previous iteration of the cross-correlation vector ryε
may be set to the null vector. The result of the operation <NUM> may be generated and/or updated predistortion correlation data including, for example, a value for the autocorrelation matrix Ryy and a value for the cross-correlation vector or ryε.

At operation <NUM>, it is determined whether there are any additional PAs 104A, 104B, 104C, 104N to be sampled. For example, it may be determined if any PAs 104A, 104B, 104C, 104N have not yet been sampled for the current execution of the process flow <NUM>. If there are any additional PAs 104A, 104B, 104C, 104N to be sampled, the feedback switching circuit <NUM> is configured to provide a feedback signal from a next power amplifier 104A, 104B, 104C, 104N to the capture buffer <NUM> (e.g., via the feedback ADC <NUM>). At operation <NUM>, the capture buffer <NUM> captures values of the feedback signal yn from the next PA 104A, 104B, 104C, 104N and corresponding values of the pre-distorted signal v.

Returning to operation <NUM>, the adaption circuit <NUM> generates updated predistortion correlation data. For example, the adaption circuit <NUM> may utilize Equations [<NUM>] and [<NUM>] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryε, where the previous versions of Ryy and ryε are as determined the previous time that the operation <NUM> was executed.

If at operation <NUM> it is determined that all PAs 104A, 104B, 104C, 104N have been sampled at operation <NUM> and corresponding updates to the predistortion correlation data made at operation <NUM>, then operation <NUM> may follow. At operation <NUM>, the adaption circuit <NUM> utilizes a linear solver to generate predistortion parameters θ̂k for the DPD circuit <NUM> using the updated predistortion correlation data. Equation [<NUM>] below provides an example that may be implemented by the adaption circuit <NUM> to generate the predistortion parameters θ̂k: <MAT> In Equation [<NUM>], θk-<NUM> is the previous iteration of the predistortion parameters. The value µ is a real scaler that may be chosen to trade off noise immunity against the adaption rate (e.g., the rate at which the DPD circuit <NUM> is updated). The term λ is a scaler that is a regularization factor that may be chosen to improve the numerical conditioning of the calculations and minimize over fitting. I is the identity matrix of appropriate dimension.

At operation <NUM>, the adaption circuit <NUM> determines whether the solution attempted at operation <NUM> has converged. If there is no convergence, the adaption circuit <NUM> may return to operation <NUM> to re-sample the PAs 104A, 104B, 104C, 104N before re-attempting to solve for the predistortion parameters θk. If the solution does converge, then the predistortion parameters θ̂k are provided to the DPD circuit and the environment proceeds with use of the PAs 104A, 104B, 104C, 104N at operation <NUM>.

In some examples, the techniques described herein can be applied to arrangements where the transmission medium exhibits frequency-dependent attenuation. One example of such a medium is coaxial cable. Cable exhibits a high-frequency roll-off characteristic in which higher frequencies are attenuated at higher levels than lower frequencies. In some examples, cables exhibit about <NUM> dB of signal amplitude reduction per <NUM> of frequency, such as at frequencies above <NUM>. To compensate for this, a tilt filter is added, for example, after a digital-to-analog converter (DAC). The tilt filter applies an "uptilt" frequency characteristic to the pre-distorted signal. The tilt frequency characteristic amplifies higher frequency portions of the signal that are attenuated by the cable so as to reduce frequency-dependent distortions at the signal destination. In some examples, the tilt frequency characteristic increases in gain by frequency according to a tilt slope, with the signal amplitude increasing as frequency increases.

When a tilt filter is used, for example, in a cable implementation, the DPD circuit may also include a tilt reference filter and a tilt equalizer circuit. The tilt reference filter (positioned to operate on the input signal prior to predistortion) and the tilt equalizer circuit (positioned to operate on the pre-distorted signal) place a tilt characteristic onto the pre-distorted signal, for example, prior to the tilt filter. The tilt characteristic attenuates higher frequency portions of the signal. In some examples, the inverse tilt characteristic decreases in gain by frequency according to a tilt slope, which may be the inverse of the tilt slope up the tilt filter.

The example illustrated by <FIG> and <FIG> shows an indirect learning algorithm where the training error εgmp is the difference between the actual output of the DPD circuit <NUM> and the inverse model of the PAs 104A, 104B, 104C, 104N. In other examples arrangement a direct approach is used where the training error εgmp is the difference between the input to the DPD circuit <NUM> and the observed output. In various examples, a direct or indirect learning algorithm may be used with the other examples described herein, as appropriate. <FIG> is a diagram showing one example of an environment <NUM> including a DPD circuit <NUM> for driving multiple PAs 304A, 304B, 304C 304N for transmitting over cable media 334A, 334B, 334C, 334N. In the environment <NUM>, a tilt filter circuit <NUM> applies tilt filter characteristics to the respective PAs 304A, 304B, 304C, 304N. In the example of <FIG>, a first stage tilt filter <NUM> provides a first stage tilt filter characteristic common to all of the PAs 304A, 304B, 304C, 304N. Second stage tilt filters 326A, 326B, 326C, 326N receive the output of the first stage tilt filter <NUM> and apply second stage tilt filter characteristics that are, for example, selected to correspond to the frequency-dependent attenuation characteristics of the respective cable media 334A, 334B, 334C, 334N. Different arrangements can be used. In some examples, the first stage tilt filter <NUM> is omitted. In other examples, additional stages may be used. The tilt filter circuit <NUM>, in some examples, is implemented utilizing analog components to achieve the desired characteristic.

In the example of <FIG>, the environment <NUM> also includes a tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM>. The tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM> place a tilt characteristic onto the pre-distorted signal v to compensate for the effect of the tilt filter circuit <NUM>. For example, the tilt filter circuit <NUM> imposes a linear distortion to the signal provided to the respective PAs 304A, 304B, 304C, 304N. The tilt reference filter circuit <NUM>, positioned between the optional DUC <NUM> and the DPD circuit <NUM> corrects for this linear distortion, for example, by attempting to replicate it in the digital domain. The tilt equalizer circuit <NUM>, positioned between the DPD circuit <NUM> and the DAC <NUM>, may be the inverse of the tilt reference filter circuit <NUM>. In some examples, the tilt reference filter <NUM> and tilt equalizer circuit <NUM> are implemented using one or more digital signal processors (DSPs) or other suitable hardware arrangement, such as the architecture <NUM> described herein below.

As with the DPD circuit <NUM> itself, it is desirable in some examples to train the tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM> to match the nonlinearities of the respective output processing paths to the respective PAs 304A, 304B, 304C, 304N. Accordingly, training the tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM> to operate with multiple output processing paths can present issues similar to those encountered when training the DPD circuit <NUM> to operate with multiple PAs 304A, 304B, 304C, 304N.

The example arrangement of <FIG> shows an example way to address the training of the tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM> for use with multiple output processing paths to multiple PAs 304A, 304B, 304C, 304N. For example, a feedback switching circuit <NUM> is configured to selectively sample feedback signals yn from the PAs 304A, 304B, 304C, 304N. A feedback ADC <NUM>, capture buffers 314A, 314B and time alignment circuit <NUM> may work in a manner similar to feedback ADC <NUM>, capture buffer <NUM>, and time alignment circuit <NUM> to provide time-aligned signals to an adaption circuit <NUM>. The adaptation circuit <NUM> may comprise a PA inverse model <NUM> for generating predistortion parameters θ̂k, a tilt equalizer model <NUM> for generating tilt equalizer parameters θ̂equk for the tilt equalizer circuit <NUM> and a tilt reference model <NUM> for generating tilt reference parameters. In some examples, the adaption circuit <NUM> is implemented using a processor arrangement, for example, similar to the architecture <NUM> described herein below. Time alignment circuit <NUM> and buffer circuits 314A, 314B may also be implemented using all or a portion of an arrangement similar to the architecture <NUM>. In some examples, the time alignment <NUM> and buffer circuits 314A, 314B can be implemented utilizing one or more shift registers or other suitable components.

<FIG> is a diagram showing one example of the environment <NUM> of <FIG> configured to generate predistortion parameters θ̂k. The example arrangement of <FIG> shows the PA inverse model <NUM> including a feature generation circuit <NUM> to generate basis matrix Y and an inverse model error circuit <NUM> to generate error vector εgmp, for example, as described herein. In the arrangement shown in <FIG>, the DPD circuit <NUM> may be trained according to the process flow <NUM> described herein. For example, the feature generation circuit <NUM> may generate basis matrix Y based on the respective feedback signals from the PAs 304A, 304B, 304C, 304N and the pre-distorted signal v. The inverse model error circuit <NUM> may generate error vectors εgmp based on the estimated inverse model of the measured output of each of the PAs 304A, 304B, 304C, 304N and the pre-distorted signal v. The correlation engine <NUM> may generate correlation data, for example, according to Equations [<NUM>] and [<NUM>] above. A linear solver circuit <NUM> may be configured to generate the predistortion parameters θ̂k, for example, according to Equation [<NUM>] described above.

<FIG> is a diagram showing one example of the environment <NUM> of <FIG> configured to generate tilt reference parameters θ̂ref for the tilt reference filter circuit <NUM>. The example arrangement of <FIG> shows the tilt reference model <NUM> including a feature generation circuit <NUM> to generate basis matrix Y and an inverse model error circuit <NUM> to generate error vectors εref. <FIG> is a flowchart showing one example of a process flow <NUM> that may be executed in the environment, for example, in the arrangement shown in <FIG>, to generate tilt reference parameters reference parameters θ̂ref.

At operation <NUM>, the PAs 304A, 304B, 304C, 304N are biased in a linear mode with the DPD circuit <NUM> turned off. Biasing the PAs 304A, 304B, 304C, 304N in linear mode may include biasing the PAs 304A, 304B, 304C, 304N such that nonlinearities of the PAs 304A, 304B, 304C, 304N do not affect or minimally affect the outputs of the PAs 304A, 304B, 304C, 304N. Turning off the DPD circuit <NUM> may include, for example, bypassing the DPD circuit <NUM>, removing power to the DPD circuit <NUM> and/or otherwise removing it from the circuit. This is illustrated in <FIG> by the absence of the DPD circuit <NUM>. As shown, the output of the tilt reference filter circuit <NUM> is provided directly to the tilt equalizer circuit <NUM>.

At operation <NUM>, the feedback switching circuit <NUM> is configured to provide a feedback signal y<NUM> from a first power amplifier 304A, 304B, 304C, 304N to the capture buffer 314B (e.g., via the feedback ADC <NUM>). This description will assume that the feedback signal y<NUM> from the PA 304A is provided first, however, as described herein any suitable PA 304A, 304B, 304C, 304N may be selected first. At operation <NUM>, the capture buffers 314A, 314B capture values of the feedback signal y<NUM> and corresponding values of the tilt reference filter circuit <NUM>. For example, values of the feedback signal y<NUM> may be captured at the capture buffer 314B and values of the output of the tilt reference filter circuit <NUM> may be captured at the capture buffer 314A. In some examples, the adaption circuit <NUM> can be arranged to perform indirect adaption for the tilt reference filter circuit <NUM>. For example, the adaption circuit <NUM> may be configured to capture feedback from an input to the tilt reference filter <NUM> (e.g., instead of or in addition to capturing feedback from the output as shown in <FIG>).

At operation <NUM>, the adaption circuit <NUM> generates and/or updates tilt reference correlation data. For example, the adaption circuit <NUM> may utilize the feedback signal y<NUM> and the corresponding values of the output of the tilt reference filter circuit <NUM> to generate a basis matrix Y<NUM> and an error vector εref1. The basis matrix Y<NUM> describes features of the DPD circuit <NUM> to minimize the error between the feedback signal y<NUM> and the corresponding values of the tilt reference filter circuit <NUM> output. The error vector εref1 is an indication of the error between the feedback signal y<NUM> and the corresponding values of the output of the tilt reference filter circuit <NUM>.

The adaption circuit <NUM> uses the basis matrix Y<NUM> and an error vector εref1 to generate tilt reference correlation data. The tilt reference correlation data can be generated, for example, by the correlation engine <NUM>. The tilt reference correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryε. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y<NUM>. In some examples, the autocorrelation vector Ryy is given by Equation [<NUM>] above. The cross-correlation vector ryε indicates a correlation between the basis matrix Y and the error vector εref, for example, as given by Equation [<NUM>] above.

At operation <NUM>, it is determined whether there are any additional PAs 304A, 304B, 304C, 304N to be sampled. For example, it may be determined if any PAs 304A, 304B, 304C, 304N have not yet been sampled for the current execution of the process flow <NUM>. If there are any additional PAs 304A, 304B, 304C, 304N to be sampled, the feedback switching circuit <NUM> is configured at operation <NUM> to provide a feedback signal from a next power amplifier 304A, 304B, 304C, 304N to the capture buffer 314B (e.g., via the feedback ADC <NUM>). At operation <NUM>, the capture buffer 314B captures values of the feedback signal yn from the next PA 304A, 304B, 304C, 304N and corresponding values of the output of the tilt reference filter circuit <NUM>.

Returning to operation <NUM>, the adaption circuit <NUM> generates updated tilt reference correlation data. For example, the adaption circuit <NUM> may utilize Equations [<NUM>] and [<NUM>] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryε, where the previous versions of Ryy and ryε are as determined the previous time that the operation <NUM> was executed.

If, at operation <NUM> it is determined that all PAs 304A, 304B, 304C, 304N have been sampled at operation <NUM> and corresponding updates to the tilt reference correlation data made at operation <NUM>, then operation <NUM> may follow. At operation <NUM>, the adaption circuit <NUM> utilizes the linear solver <NUM> to generate tilt reference parameters θ̂ref for the tilt reference filter circuit <NUM> using the updated tilt reference correlation data, for example, by optimizing Equation [<NUM>] below provides an example that may be implemented by the adaption circuit <NUM> to generate the tilt reference parameters θ̂ref: <MAT> In Equation [<NUM>], θ̂ref-<NUM> is the previous iteration of the tilt reference parameters. The values µ and λ may be as described with respect to Equation [<NUM>] above.

At operation <NUM>, the adaption circuit <NUM> determines whether the solution attempted at operation <NUM> has converged. If there is no convergence, the adaption circuit <NUM> may return to operation <NUM> to re-sample the PAs 304A, 304B, 304C, 304N before re-attempting to solve for the tilt reference parameters θ̂ref. If the solution does converge, then the tilt reference parameters θ̂ref are provided to the tilt reference filter circuit <NUM>. The DPD circuit <NUM> may be reactivated and the environment may proceed with use of the PAs 304A, 304B, 304C, 304N at operation <NUM>.

<FIG> is a diagram showing one example of the environment <NUM> of <FIG> configured to generate tilt equalizer parameters θ̂equ for the tilt equalizer circuit <NUM>. The example arrangement of <FIG> shows the tilt equalizer model <NUM> including a feature generation circuit <NUM> to generate a basis matrix Y and an inverse model error circuit <NUM> to generate error vectors εequ. <FIG> is a flowchart showing one example of a process flow <NUM> that may be executed in the environment, for example, in the arrangement shown in <FIG>, to generate tilt equalizer parameters, θ̂equ.

At operation <NUM>, the PAs 304A, 304B, 304C, 304N are biased in a linear mode with the DPD circuit <NUM> turned off. At operation <NUM>, the feedback switching circuit <NUM> is configured to provide a feedback signal y<NUM> from a first power amplifier 304A, 304B, 304C, 304N to the capture buffer 314B (e.g., via the feedback ADC <NUM>). This description will assume that the feedback signal y<NUM> from the PA 304A is provided first; however, as described herein any suitable PA 304A, 304B, 304C, 304N may be selected first. At operation <NUM>, the capture buffers 314A, 314B capture values of the feedback signal y<NUM> and corresponding values of the tilt equalizer circuit <NUM> input. For example, values of the feedback signal y<NUM> may be captured at the capture buffer 314B and values of the output from the tilt equalizer circuit <NUM> may be captured at the capture buffer 314A. In some examples, the adaption circuit <NUM> can be arranged to perform indirect adaption for the tilt equalizer circuit <NUM>. For example, the adaption circuit <NUM> may be configured to capture feedback from an input to the tilt equalizer circuit <NUM> (e.g., instead of or in addition to capturing feedback from the output as shown in <FIG>).

At operation <NUM>, the adaption circuit <NUM> generates and/or updates tilt equalizer correlation data. For example, the adaption circuit <NUM> may utilize the feedback signal y<NUM> and the corresponding values of the output of the tilt equalizer circuit <NUM> to generate a basis matrix Y<NUM> and an error vector εequ1. The basis matrix Y<NUM> describes (linear) features to minimize the error between the feedback signal y<NUM> and the corresponding values of the output of the tilt equalizer circuit <NUM>. The error vector εequ1 is an indication of the error between the feedback signal y<NUM> and the corresponding values of the output of the tilt equalizer circuit <NUM>. In some examples, the basis matrix Y<NUM> for generating the tilt equalizer circuit <NUM> and tilt reference circuit <NUM> parameters include linear terms while the basis matrix Y<NUM> for generating DPD circuit <NUM> parameters may include linear and/or non-linear terms.

The adaption circuit <NUM> uses the basis matrix Y<NUM> and an error vector εequ1 to generate tilt equalizer correlation data. The tilt equalizer correlation data can be generated, for example, by the correlation engine <NUM>. The tilt equalizer correlation data may include an autocorrelation matrix Ryy and a cross-correlation vector ryε, as described herein. The autocorrelation matrix Ryy indicates a correlation between the various features of the basis matrix Y<NUM>. In some examples, the autocorrelation vector Ryy is given by Equation [<NUM>] above. The cross-correlation vector ryε indicates a correlation between the basis matrix Y and the error vector εequ. In some examples, the cross-correlation vector ryε is given by Equation [<NUM>] above.

At operation <NUM>, it is determined whether there are any additional PAs 304A, 304B, 304C, 304N to be sampled. For example, it may be determined if any PAs 304A, 304B, 304C, 304N have not yet been sampled for the current execution of the process flow <NUM>. If there are any additional PAs 304A, 304B, 304C, 304N to be sampled, the feedback switching circuit <NUM> is configured at operation <NUM> to provide a feedback signal from a next power amplifier 304A, 304B, 304C, 304N to the capture buffer 314B (e.g., via the feedback ADC <NUM>). At operation <NUM>, the capture buffer 314B captures values of the feedback signal yn from the next PA 304A, 304B, 304C, 304N and corresponding values of the input to the tilt equalizer circuit <NUM>.

Returning to operation <NUM>, the adaption circuit <NUM> generates updated equalizer correlation data. For example, the adaption circuit <NUM> may utilize Equations [<NUM>] and [<NUM>] above to generate an updated autocorrelation matrix Ryy and an updated cross-correlation vector ryε, where the previous versions of Ryy and ryε are as determined the previous time that the operation <NUM> was executed.

If at operation <NUM> it is determined that all PAs 304A, 304B, 304C, 304N have been sampled at operation <NUM> and corresponding updates to the tilt equalizer correlation data made at operation <NUM>, then operation <NUM> may follow. At operation <NUM>, the adaption circuit <NUM> utilizes the linear solver <NUM> to generate tilt equalizer parameters θ̂equ for the tilt equalizer circuit <NUM> using the updated tilt equalizer correlation data, for example, by optimizing Equation [<NUM>] below provides an example that may be implemented by the adaption circuit <NUM> to generate the tilt equalizer parameters θ̂equ: <MAT> In Equation [<NUM>], θ̂equ-<NUM> is the previous iteration of the tilt equalizer parameters. The values µ and λ may be as described with respect to Equation [<NUM>] above.

At operation <NUM>, the adaption circuit <NUM> determines whether the solution attempted at operation <NUM> has converged. If there is no convergence, the adaption circuit <NUM> may return to operation <NUM> to re-sample the PAs 304A, 304B, 304C, 304N before re-attempting to solve for the tilt equalizer parameters θ̂equ. If the solution does converge, then the tilt equalizer parameters θ̂equ are provided to the tilt equalizer circuit <NUM>. The DPD circuit <NUM> may be reactivated and the environment may proceed with use of the PAs 304A, 304B, 304C, 304N at operation <NUM>. In some examples, the tilt equalizer circuit <NUM> and tilt reference filter circuit <NUM> are trained independently of the DPD circuit <NUM>. For example, the tilt reference filter parameters θ̂equ and tilt reference parameters θ̂ref may be determined first, for example, as illustrated and described with respect to <FIG>. After the tilt reference filter circuit <NUM> and tilt equalizer circuit <NUM> are trained, the DPD circuit <NUM> may be trained, for example, as described herein.

<FIG> shows four plots <NUM>, <NUM>, <NUM>, <NUM> illustrating outputs of four PAs in the arrangement of the PAs 304A, 304B, 304C, 304N, with components trained as described with respect to <FIG>. Plot <NUM> shows signal strength in decibels (dB) versus frequency for a first PA, such as PA 304A. Plot <NUM> shows signal strength in dB versus frequency for a second PA, such as PA 304B. Plot <NUM> shows signal strength in dB versus frequency for a third PA, such as PA 304C. Plot <NUM> shows signal strength in dB versus frequency for a fourth PA, such as PA 304N. The plots <NUM>, <NUM>, <NUM>, <NUM> show tilt provided by the tilt circuit <NUM> as the displayed signals are higher at higher frequency to compensate for the higher attenuation of the cable media 334A, 334B, 334C, 334N at higher frequencies. Also, as shown, the outputs are substantially similar despite being driven by a single DPD circuit <NUM>.

<FIG> is a diagram showing one example of an environment <NUM> including an array <NUM> of PAs and an array DPD circuit <NUM>. In the environment <NUM> a single input signal (e.g., processed by the optional DUC <NUM>) is provided to the array DPD circuit <NUM>. The array DPD circuit <NUM> generates a pre-distorted signal v. A DAC <NUM> converts the pre-distorted signal v to an analog pre-distorted signal v. A mixer <NUM> and mixer array <NUM> mix the pre-distorted signal v with an array of values for a given downtilt angle θ and a horizontal scan angle ϕ to modify the amplitude and phase of the pre-distorted signal v. The mixer <NUM> may be or include a frequency translation mixer that takes a lower-centered frequency signal (e.g., IF, such as about <NUM>) and coverts it to a higher-centered frequency signal (e.g., about <NUM>). The result of the mixer <NUM> and mixer array <NUM> may be a set of amplitude-modified and phase-shifted pre-distorted signals v, with each distinct signal being shifted by a phase and amplitude to bring about a transmission beam <NUM> of a desired shape and direction. The phase-shifted and amplitude-modified pre-distorted signals are provided to PAs of a PA array <NUM>. The PAs of the PA array amplify their respective received signals, which are provided to separate antennas of an antenna array <NUM>. The phase shifting and amplitude modifying of the inputs to the PAs of the PA array result in a beam <NUM> having the desired downtilt angle θ and horizontal scan angle ϕ.

In the arrangement of <FIG>, the array DPD circuit <NUM> may be trained in a manner similar to that described herein with respect to <FIG> and <FIG>. For example, a feedback switching circuit <NUM> is configured to sequentially provide feedback signals yn from the PAs of the PA array <NUM> to an adaption circuit <NUM> via a, mixer <NUM>, and feedback ADC <NUM>. The mixer <NUM>, for example, man down-convert the feedback signals yn, for example, as the inverse of the mixer <NUM>.

The adaption circuit <NUM> may receive the feedback signals yn and the digital pre-distorted signal v from the output of the array DPD circuit <NUM>. The adaption circuit <NUM> may perform time alignment to match or time align values of the feedback signal yn to corresponding values of the pre-distorted signal v. The adaption circuit <NUM> generates predistortion parameters θ̂k for the array DPD circuit <NUM> from the feedback signal yn and pre-distorted signal v, for example, as described herein with respect to <FIG>.

<FIG> is a block diagram illustrating a computing device hardware architecture <NUM>, within which a set or sequence of instructions can be executed to cause a machine to perform examples of any one of the methodologies discussed herein. For example, the architecture <NUM> may describe one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or similar hardware that may be used, in some examples, to implement any of the circuits described herein. For example, the DPD circuit <NUM>, adaption circuit <NUM> may be implemented using all or portions of a hardware architecture such as the architecture <NUM>. The capture buffer <NUM> and time alignment circuit <NUM>, in some examples, may also be implemented using all or portions of a hardware architecture such as the architecture <NUM>.

The architecture <NUM> may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the architecture <NUM> may operate in the capacity of either a server or a client machine in server-client network environments, or it may act as a peer machine in peer-to-peer (or distributed) network environments. The architecture <NUM> can be implemented in an embedded system, a personal computer (PC), a tablet PC, a hybrid tablet, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, a network switch, a network bridge, or any machine capable of executing instructions (sequential or otherwise) that specify operations to be taken by that machine.

The example architecture <NUM> includes a processor unit <NUM> comprising at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both, processor cores, compute nodes). The architecture <NUM> may further comprise a main memory <NUM> and a static memory <NUM>, which communicate with each other via a link <NUM> (e.g., a bus). The architecture <NUM> can further include a video display unit <NUM>, an input device <NUM> (e.g., a keyboard), and a UI navigation device <NUM> (e.g., a mouse). In some examples, the video display unit <NUM>, input device <NUM>, and UI navigation device <NUM> are incorporated into a touchscreen display. The architecture <NUM> may additionally include a storage device <NUM> (e.g., a drive unit), a signal generation device <NUM> (e.g., a speaker), a network interface device <NUM>, and one or more sensors (not shown), such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor.

In some examples, the processor unit <NUM> or another suitable hardware component may support a hardware interrupt. In response to a hardware interrupt, the processor unit <NUM> may pause its processing and execute an ISR, for example, as described herein.

The storage device <NUM> includes a machine-readable medium <NUM> on which is stored one or more sets of data structures and instructions <NUM> (e.g., software) embodying or used by any one or more of the methodologies or functions described herein. The instructions <NUM> can also reside, completely or at least partially, within the main memory <NUM>, within the static memory <NUM>, and/or within the processor unit <NUM> during execution thereof by the architecture <NUM>, with the main memory <NUM>, the static memory <NUM>, and the processor unit <NUM> also constituting machine-readable media.

The various memories (i.e., <NUM>, <NUM>, and/or memory of the processor unit(s) <NUM>) and/or the storage device <NUM> may store one or more sets of instructions and data structures (e.g., the instructions <NUM>) embodying or used by any one or more of the methodologies or functions described herein. These instructions, when executed by the processor unit(s) <NUM>, cause various operations to implement the disclosed examples.

As used herein, the terms "machine-storage medium," "device-storage medium," and "computer-storage medium" (referred to collectively as "machine-storage medium") mean the same thing and may be used interchangeably. The terms refer to a single or multiple storage devices and/or media (e.g., a centralized or distributed database, and/or associated caches and servers) that store executable instructions and/or data, as well as cloud-based storage systems or storage networks that include multiple storage apparatus or devices. The terms shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media, including memory internal or external to processors. Specific examples of machine-storage media, computer-storage media, and/or device-storage media include non-volatile memory, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), field-programmable gate array (FPGA), and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The terms "machine-storage media," "computer-storage media," and "device-storage media" specifically exclude carrier waves, modulated data signals, and other such media, at least some of which are covered under the term "signal medium" discussed below.

The term "signal medium" or "transmission medium" shall be taken to include any form of modulated data signal, carrier wave, and so forth.

The instructions <NUM> can further be transmitted or received over a communications network <NUM> using a transmission medium via the network interface device <NUM> using any one of a number of well-known transfer protocols (e.g., Hypertext Transfer Protocol (HTTP)). Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, mobile telephone networks, plain old telephone service (POTS) networks, and wireless data networks (e.g., Wi-Fi, <NUM>, <NUM> Long-Term Evolution (LTE)/LTE-A, <NUM>, or WiMAX networks).

Geometric terms, such as "parallel", "perpendicular", "round", or "square", are not intended to require absolute mathematical precision, unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as "round" or "generally round," a component that is not precisely circular (e.g., one that is slightly oblong or is a many-sided polygon) is still encompassed by this description.

The term "circuit" can include a dedicated hardware circuit, a general-purpose microprocessor, digital signal processor, or other processor circuit, and may be structurally configured from a general purpose circuit to a specialized circuit such as using firmware or software.

Any one or more of the techniques (e.g., methodologies) discussed herein may be performed on a machine. In various embodiments, the machine may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine may act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine.

Examples, as described herein, may include, or may operate by, logic or a number of components, or mechanisms. Circuit sets are a collection of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuit set membership may be flexible over time and underlying hardware variability. Circuit sets include members that may, alone or in combination, perform specified operations when operating. In an example, hardware of the circuit set may be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuit set may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions can enable embedded hardware (e.g., the execution units or a loading mechanism) to create members of the circuit set in hardware via the variable connections to carry out portions of the specific operation when in operation. Accordingly, the computer readable medium is communicatively coupled to the other components of the circuit set member when the device is operating. In an example, any of the physical components may be used in more than one member of more than one circuit set. For example, under operation, execution units may be used in a first circuit of a first circuit set at one point in time and reused by a second circuit in the first circuit set, or by a third circuit in a second circuit set at a different time.

Particular implementations of the systems and methods described herein may involve use of a machine (e.g., computer system) that may include a hardware processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory and a static memory, some or all of which may communicate with each other via an interlink (e.g., bus). The machine may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, the display unit, input device and UI navigation device may be a touch screen display. The machine may additionally include a storage device (e.g., drive unit), a signal generation device (e.g., a speaker), a network interface device, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

The storage device may include a machine readable medium on which is stored one or more sets of data structures or instructions (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions may also reside, completely or at least partially, within the main memory, within static memory, or within the hardware processor during execution thereof by the machine. In an example, one or any combination of the hardware processor, the main memory, the static memory, or the storage device may constitute machine readable media.

While the machine readable medium can include a single medium, the term "machine readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions.

The term "machine readable medium" may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Nonlimiting machine readable medium examples may include solid-state memories, and optical and magnetic media. In an example, a massed machine readable medium comprises a machine readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals. Specific examples of massed machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions may further be transmitted or received over a communications network using a transmission medium via the network interface device utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) <NUM> family of standards known as Wi-Fi®, IEEE <NUM> family of standards known as WiMax®), IEEE <NUM>. <NUM> family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network. In an example, the network interface device may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

Claim 1:
A system for operating a plurality of power amplifiers, the system comprising:
a predistortion circuit (<NUM>) configured to pre-distort an input signal according to a predistortion configuration to generate a pre-distorted signal for the plurality of power amplifiers (304A, 304B, 304C, 304N);
a tilt equalizer circuit (<NUM>) electrically coupled to the predistortion circuit (<NUM>) to apply a frequency characteristic to the pre-distorted signal according to a tilt equalizer configuration, thereby generating a tilt equalizer output signal;
a tilt filter (<NUM>) configured to generate respective input signals of the plurality of power amplifiers by applying tilt frequency characteristics to the tilt equalizer output signal; and
an adaption circuit (<NUM>), configured to perform operations comprising:
receiving a first feedback signal from a first power amplifier of the plurality of power amplifiers;
generating predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers;
receiving a first feedback signal from a second power amplifier of the plurality of power amplifiers;
updating the predistortion correlation data to generate updated predistortion correlation data, the updating using the first feedback signal from the second power amplifier;
generating the predistortion configuration using the updated predistortion correlation data;
receiving a second feedback signal from the first power amplifier, the second feedback signal from the first power amplifier taken while the first power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated;
generating tilt equalizer correlation data describing a correlation between the plurality of power amplifiers and a tilt equalizer input signal using the second feedback signal of the first power amplifier;
receiving a second feedback signal from the second power amplifier, the second feedback signal from the second power amplifier taken while the second power amplifier is biased to operate in a linear mode and while the predistortion circuit is deactivated;
updating the tilt equalizer correlation data to generate updated tilt equalizer correlation data, the updating using the second feedback signal of the second power amplifier; and
generating the tilt equalizer configuration for the tilt equalizer circuit using the updated tilt equalizer correlation data.