Patent Description:
The present disclosure, in various embodiments, relates generally to semiconductor device design and fabrication. More particularly, the present disclosure relates to design and fabrication of memory devices having three-dimensionally arranged memory cells.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. In contrast to volatile memory devices, nonvolatile memory devices, such as flash memory devices, retain stored data even when power is removed. Therefore, nonvolatile memory devices, such as flash memory devices, are widely used in memory cards and in electronic devices. Due to rapidly growing digital information technology, there are demands to continuingly increase the memory density of the flash memory devices while maintaining, if not reducing, the size of the devices.

Three dimensional (3D)-NAND flash memory devices have been investigated for increasing the memory density. The 3D-NAND architecture includes a stack of memory cells having a plurality of charge storage structures (e.g., floating gates, charge traps or the like), a stack of alternating control gates and dielectric materials, and charge blocking materials disposed between the charge storage structures (mostly referred to by example as floating gates hereinafter) and the adjacent control gates. An oxide material, such as silicon oxide, is conventionally used as the dielectric material. The charge blocking material may be an inter-poly dielectric (IPD) material, such as oxide-nitride-oxide (ONO) material.

<FIG> shows a semiconductor structure <NUM> that may be further processed to form a 3D-NAND flash memory device. The semiconductor structure <NUM> includes a stack <NUM> of alternating control gates <NUM> and dielectric materials <NUM> over a material <NUM> to be used as control gate of a select device, such as a select gate source (SGS) or a select gate drain (SGD), a plurality of floating gates <NUM>, a charge blocking material (<NUM>, <NUM>, <NUM>) positioned between the floating gates <NUM> and adjacent control gates <NUM>, and a channel material <NUM> extending through the stack <NUM>, the control gate material <NUM>, a dielectric material <NUM>, and a portion of a source <NUM>. The source <NUM> could be formed in and/or on a substrate (not shown), such as a semiconductor substrate comprising monocrystalline silicon. Optionally, the semiconductor structure <NUM> may include an etch stop material <NUM>. Although not depicted here, in other embodiments, the depicted material <NUM> may form or be part of a bit line (e.g., instead of a source). The control gates <NUM> each has a height of L<NUM>. The floating gates <NUM> each has a height of L<NUM>. Due to the presence of the charge blocking material (<NUM>, <NUM>, <NUM>) around the discrete floating gate <NUM>, the height L<NUM> of each discrete floating gate <NUM> is approximately half the height L<NUM> of an adjacent control gate. For example, the height of the floating gate in the direction of current flow (e.g., in a pillar of a string of the memory cells) may be approximately <NUM> compared to the height of an adjacent control gate, which is approximately <NUM>. In addition, the floating gate is not aligned with the adjacent control gate.

During use and operation, a charge may get trapped on portions of the IPD material, such as on portions of the IPD material that are horizontally disposed between a floating gate and adjacent dielectric material. When the IPD material is an ONO material, the charge may get trapped in the horizontal nitride portions of the IPD material that are not between the control gates and the floating gates. Trapped charge can migrate along the IPD material, such as through program, erase or temperature cycling. The presence of the IPD material creates a direct path for programming/ erasing into the nitride material of the IPD material and degrades cell program-erase cycling. Such charge trapping or movement can alter the threshold voltage (Vt) of the memory cells or degrade incremental step pulse programming (ISPP) relative to memory cells that do not have such charge trapping in the nitride. Charge trap jeopardizes the controllability of the channel characteristics and the reliability of the 3D-NAND flash memory device.

To minimize charge trap in the horizontal IPD portions, it is desirable to reduce the amount of the horizontal IPD portions, such as by increasing the height of a floating gate relative to the height of an adjacent control gate. In addition to reducing the undesirable charge trap, increasing the height of floating gate in the direction of current flow through the channel may offer a higher degree of channel conductance modulation (e.g., a higher on/off ratio), a reduced cell noise (e.g., a larger floating gate), and a reliability gain. The attempts to increase the height of floating gates to about the same as that of adjacent control gates require the addition of numerous deposition/dry/wet etch steps, resulting in a complex and rather costly fabrication process. Furthermore, these additional deposition/dry/wet etch steps often associate with an undesirable increase in the critical dimension.

Therefore, it would be beneficial to have a fabrication process for forming the floating gates having a height approximately the same as the height of adjacent control gates that utilizes relatively few additional acts and without jeopardizing other properties and performances of the fabricated structure.

<CIT> describes, in a nonvolatile semiconductor memory device, a stacked body provided on a silicon substrate by alternately stacking pluralities of isolation dielectric films and electrode films. A through-hole is formed in the stacked body to extend in the stacking direction, and a memory film is formed by stacking a block layer, a charge layer and a tunnel layer in this order at an inner face of the through-hole, and thereby a silicon pillar is buried in the through-hole.

<CIT> describes a memory cell in a semiconductor integrated circuit provided with: a semiconductor pillar that serves as a channel; a floating gate that circumferentially covers the semiconductor pillar via a tunnel insulation layer on the outer circumference of the semiconductor pillar; and a control gate that circumferentially covers the semiconductor pillar via an insulating layer on the outer circumference of the semiconductor pillar, and that circumferentially covers the floating gate via an insulating layer on the outer circumference of the floating gate.

<CIT> describes a nonvolatile semiconductor memory device including: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface.

A method of fabricating a semiconductor structure according to the invention is presented in claim <NUM>, a semiconductor structure according to the invention is presented in claim <NUM>. Embodiments of the invention are presented in the dependent claims.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that embodiments of the present disclosure may be practiced without employing these specific details. Indeed, the embodiments of the present disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry.

In addition, the description provided herein does not form a complete process flow for forming a semiconductor device structure, and the semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the present disclosure are described in detail below. Additional acts to form the complete semiconductor device may be performed by conventional fabrication techniques. Also the drawings accompanying the application are for illustrative purposes only, and are thus not necessarily drawn to scale. Elements common between figures may retain the same numerical designation. Furthermore, while the materials described and illustrated herein may be formed as layers, the materials are not limited thereto and may be formed in other three-dimensional configurations.

As used herein, any relational terms, such as "first," "second" and "third," or "top," "middle" and "bottom," are used for clarity and convenience in understanding the present disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation or order. It is understood that, although the terms "first," "second," "top," "middle" and "bottom" are used herein to describe various elements, these elements should not be limited by these terms.

As used herein, the terms "horizontal" and "lateral" are defined as a plane parallel to the plane or surface of a wafer or substrate, regardless of the actual orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal plane as defined above. The term "height" is defined as a dimension of the structure in a direction perpendicular to the horizontal plane as defined above.

As used herein, the term "substantially," in reference to a given parameter, property or condition, means to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances.

As used herein, the term "critical dimension" means and includes a dimension of a feature within design tolerances in order to achieve the desired performance of the device and to maintain the performance consistency of the device. This dimension may be obtained on a device structure as a result of different combinations of fabrication processes, which may include, but are not limited to, photolithography, etch (dry/wet), diffusion, or deposition acts.

<FIG> are cross-sectional views of various stages of forming a plurality of floating gates for 3D-NAND flash memory device according to one embodiment of the present disclosure.

<FIG> shows a semiconductor structure <NUM> including a source <NUM>, a source oxide material <NUM>, a material <NUM> to be used as a control gate of a select device (e.g., SGS), optionally an etch stop material <NUM>, and a stack <NUM> of alternating oxide materials <NUM> and control gates <NUM> (of memory cells). The oxide material <NUM> may include multiple portions having different densities, which are indicated in <FIG> by reference numerals 105a, 105b, 105c. While the oxide portions 105a, 105b, 105c are shown in <FIG> as distinct, this does not necessarily imply that the oxide portions 105a, 105b, 105c are formed from different materials. Rather, the oxide portions 105a, 105b, 105c may be formed from the same material, but differing in density. By way of example, the oxide material <NUM> may include a top oxide portion 105c, a middle oxide portion 105b, and a bottom oxide portion 105a, wherein the densities of the top and bottom oxide portions 105c, 105a are substantially the same as each other but lower than the density of the middle oxide portion 105b. While the oxide material <NUM> is illustrated as including three portions having different densities, the oxide material <NUM> may include fewer portions or more portions, as will be described in more detail. The source <NUM> may be formed from doped polysilicon, tungsten silicide (WSix), or other conventional materials for sources. The etch stop material <NUM> may be aluminum oxide or other conventional etch stop material selected so that the materials of the stack <NUM> may be selectively removed without removing other materials of the semiconductor structure <NUM>.

As used herein, the term "substrate" means and includes a base material or construction upon which additional materials are formed. The substrate may be, for example, a semiconductor substrate, a base semiconductor material on a supporting structure, a metal electrode or a semiconductor substrate having one or more materials, structures or regions formed thereon. The substrate may be a conventional silicon substrate, or other bulk substrate comprising a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si<NUM>-xGex, where x is, for example, a mole fraction between <NUM> and <NUM>), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a "substrate" in the following description, previous process acts may have been conducted to form materials, regions, or junctions in the base semiconductor structure or foundation. In one embodiment, the substrate is a silicon-containing material, such as a silicon substrate. The substrate may be doped or undoped. In one embodiment, the substrate may be p-doped polysilicon.

As shown in <FIG>, the semiconductor structure <NUM> may include films of the respective materials. The source <NUM>, source oxide material <NUM>, control gate material <NUM>, etch stop material <NUM>, and control gate materials <NUM> may be formed by conventional techniques, which are not described in detail herein.

The different portions of the oxide material <NUM> may be formed on the etch stop material <NUM> by adjusting process conditions during the formation of the material. In one embodiment, the oxide material <NUM> may be formed using a plasma enhanced-chemical vapor deposition (PECVD) process. Each portion may be formed to a desired thickness before forming another portion. The oxide portions 105a, 105b, 105c may be of sufficiently different densities that the portions may be selectively removed when subjected to a suitable etch chemistry. The density (measured in g/cm<NUM> unit) of each oxide portion may be determined using X-ray reflectometry (XRR), which is a conventional technique and, therefore, is not described in detail herein. In some embodiments, a density of one oxide portion may be from about six times (6x) lower to about two times (2x) higher than the density of an adjacent oxide portion(s), i.e., an oxide portion may be from about six times less dense to about two times more dense in relation to the adjacent oxide portion(s). However, it is understood that the differences in densities of oxide portions may be varied, depending on specific integration schemes of the semiconductor structure.

Various process parameters may be adjusted while forming the oxide material <NUM> that includes oxide portions of different densities. Non-limiting examples of such processing parameters include an amount of RF power/energy applied and RF frequency during a deposition process. By way of non-limiting example, the density of each of the oxide portions may be tailored by varying the frequency and power applied during the formation of the oxide portion. A high frequency (HF) may be a RF frequency of from about <NUM> to about <NUM>, and a low frequency (LF) may be a RF frequency of from about <NUM> to about <NUM>. A high frequency (HF) power may be a RF power of about <NUM> Watts to about <NUM> Watts, and a low frequency (LF) power may be a RF power of from about <NUM> Watts to about <NUM> Watts. In some embodiments, the high frequency (HF) may be RF frequency of about <NUM>. In some embodiments, the low frequency (LF) may be RF frequency of about <NUM>.

If an oxide portion is formed using high power/low frequency, more surface impingement of ions may occur and consequently a high density of the oxide portion may be produced. Conversely, if low power/low frequency is used, less surface impingement of ions may occur and consequently a relatively lower density portion of the oxide material may be produced.

Additional processing parameters that may be adjusted include, but are not limited to, deposition time, types and ratios of component gases, pressure, flow rates of the component gases, temperature, or post-deposition treatment, etc. While these processing parameters may have a smaller effect on the density of the oxide material compared to adjusting at least one of the RF power and frequency, the density of the oxide material may be further tailored by adjusting one or more of these parameters. For instance, a longer deposition time may produce the oxide portion having a higher density compared to a shorter deposition time. Several processing parameters may be controlled to obtain the oxide material that includes at least two oxide portions of different densities. In some embodiments, the processing parameters may be programmed such that the desired density of oxide material is achieved.

The density of deposited oxide material may, optionally, be modified by post-deposition treatment. By way of non-limiting example, the post-deposition treatment may include subjecting the oxide material <NUM> to a mixed frequency of high frequency (HF) and low frequency (LF) plasma treatment. The mixed frequency plasma treatment may densify the top oxide portion 105c. The desired depth of densification of the oxide material <NUM> may be dependent on several factors including, but not limited to, the RF power employed during the post-deposition treatment, the duration of the post-deposition treatment, or both.

In some embodiments, the oxide material having at least two oxide portions of different densities may be achieved by adjusting the RF power during the deposition and applying a post-deposition treatment using a mixed frequency plasma treatment. In some embodiments, the oxide material having at least two oxide portions of different densities may be obtained by forming the oxide material at a RF power from about <NUM> Watts to about <NUM> Watts, and applying a postdeposition treatment from about two seconds to about <NUM> seconds using a mixed frequency plasma treatment having a high frequency/lower frequency power (HF/LF) combination from about <NUM>/<NUM> Watts to <NUM>/<NUM> Watts.

In some embodiments, the oxide material having at least two oxide portions of different densities may be achieved by depositing the oxide material using high frequency (HF), and then subjecting the oxide material to a high frequency (HF) plasma treatment. In some embodiments, this may be achieved by depositing the oxide material using high frequency (HF), and then subjecting the oxide material to a mixed frequency of high frequency (HF) and low frequency (LF) plasma treatment. In some embodiments, this may be achieved by depositing the oxide material using a mixed frequency of high frequency (HF) and low frequency (LF), and then subjecting the oxide material to a high frequency (HF) plasma treatment. In some embodiments, this may be achieved by depositing the oxide material using a mixed frequency of high frequency (HF) and low frequency (LF), and then subjecting the oxide material to a mixed frequency of high frequency (HF) and low frequency (LF) plasma treatment.

In some embodiments, the oxide material may be deposited using tetraethyl orthosilicate (TEOS) and oxygen. In some embodiments, the oxide material may be deposited using silane and oxygen. In one embodiment, the oxide material may be silicon oxide.

In some embodiments, the formation of oxide material having at least two oxide portions of different densities may be conducted in one reaction chamber. In these in-situ deposition embodiments, the processing parameters may be adjusted to form one oxide portion and then adjusted for the formation of another oxide portion having a different density.

Alternatively, in some embodiments the formation of oxide material having at least two oxide portions of different densities may be conducted in more than one reaction chamber. By way of non-limited example, one oxide portion of the oxide material may be formed in a first reaction chamber, and then another oxide portion of different density may be formed in a second reaction chamber.

The control gate material <NUM> may be formed over the oxide material <NUM> by any conventional method and, therefore, is not described in detail herein. The control gate material may be of any known conductive materials. Non-limiting examples of such conductive materials may include n-doped polysilicon, p-doped polysilicon, or undoped polysilicon. In one embodiment, the control gate material may be n-doped polysilicon. The formation of the oxide materials <NUM> and control gate materials <NUM> may be repeated to create the stack <NUM> of alternating oxide materials <NUM> and control gates <NUM>.

Referring to <FIG>, the semiconductor structure <NUM> of <FIG> is subjected to a single etch process or multiple etch processes to create an opening <NUM> through the stack <NUM> of alternating oxide materials <NUM> and control gate materials <NUM> that stops in the etch stop material <NUM>. By way of example, the stack <NUM> may be etched using an anisotropic dry etch process. A surface of the control gate material <NUM> may be exposed following the etch process. The opening <NUM> may be formed using any conventional etch chemistry (i.e., a reactive ion etch), and therefore is not described in detail herein. Although the structure <NUM> of <FIG> shows only one opening <NUM>, it is understood that the semiconductor structure <NUM> may include more than one opening.

As shown in <FIG>, a portion of the control gate materials <NUM> in the stack <NUM> is selectively removed relative to adjacent oxide materials <NUM> to create control gate recesses <NUM> having a height of L<NUM>, where the upper and lower boundaries of the control gate recesses <NUM> are defined by sidewalls of the adjacent oxide materials <NUM>. The height L<NUM> of the control gate recesses <NUM> is substantially the same as the thickness of the adjacent control gate materials <NUM>. The control gate recesses <NUM> is formed by laterally removing portions of the control gate materials <NUM>. In some embodiments, the control gate recesses <NUM> may be formed by wet etching the semiconductor structure <NUM> using a solution of tetramethylammonium hydroxide (TMAH).

As shown in <FIG>, a portion of the oxide materials <NUM> in the stack <NUM> is removed to increase the height of the control gate recesses <NUM>. Portions of the oxide materials <NUM> adjacent to the control gate recesses <NUM> may be removed using any conventional wet etch chemistry for an oxide material. In some embodiments, the portions of the oxide materials may be removed by etching with an etchant selected from the group consisting of hydrogen fluoride (HF) solution, and buffered oxide etch (BOE) solution comprising HF and NH<NUM>F. Since the oxide material <NUM> has oxide portions of different densities, the oxide portions may be removed at different rates when exposed to an etch chemistry. By way of example, a portion of the top and bottom oxide portions 105c, 105a may be removed without removing a portion of the middle oxide portion 105b. The top and bottom oxide portions 105c, 105a above and below the control gate recesses <NUM> may be removed by the etch chemistry, while portions of the top and bottom oxide portions 105c, 105a above and below the control gate materials <NUM> may remain.

As shown in <FIG>, the top and bottom oxide portions 105a, 105c may be removed such that the resulting control gate recesses <NUM> has a height of L<NUM>, which is greater than the original height L<NUM> of the control gate recesses <NUM>. The amount of oxide material <NUM> removed, the height L<NUM> of the control gate recesses <NUM>, and the profile of the control gate recesses <NUM> may be controlled by various factors including, but not limited to, the densities of each oxide portion of the oxide material <NUM>, the thickness of each oxide portion in the oxide material <NUM>, or the etching types and conditions. The heights and profiles of the control gate recesses <NUM> may be dependent on the densities of each oxide portion in the oxide material <NUM>, as shown and discussed in more detail with reference to <FIG>.

<FIG> are enlarged views of the area labeled "W" in <FIG>. In <FIG>, the oxide material <NUM> includes the top oxide portion 105c, the middle oxide portion 105b, and the bottom oxide portion 105a, wherein the densities of the top and bottom oxide portions 105c, 105a are substantially the same, and the density of the middle oxide portion 105b is higher than that of the top and bottom oxide portions 105c, 105a. The top oxide portion 105c of one oxide material <NUM> and the bottom oxide portion 105a of another oxide material <NUM> define the boundaries of each control gate recess <NUM>. Since the top and bottom oxide portions 105c, 105a adjacent the control gate recess <NUM> have about the same density, portions of these materials are removed at substantially the same rate while other exposed materials, including middle oxide portion 105b, are removed at a substantially slower rate. Therefore, the amounts of removal in the vertical direction for the top and bottom oxide portions 105c, 105a are substantially the same. However, portions of the top and bottom oxide portions 105c, 105a overlying or underlying the control gate material <NUM> may remain in place, in addition to middle oxide portion 105b. While portions of the oxide material <NUM> may also be removed in the horizontal direction, which leads to a loss in critical dimension (CD), the loss in CD may be compensated for by appropriately selecting the initial CD of the opening <NUM>. Thus, horizontal etching of the oxide material <NUM> of the structure in <FIG> may occur with less effect on the CD than the horizontal etching of the oxide material <NUM> of the structure in <FIG>. It is desirable to minimize the loss of critical dimension to comply with design rules/requirements and, therefore, ensure that the desired device performance is achieved.

Therefore, the dimension, height and profile of the control gate recess <NUM> may be controlled by appropriate selection of the type and density of oxide portions (e.g., 105a, 105b, 105c) in the oxide material <NUM>, the thickness of each oxide portion, the etching conditions, and other various known factors.

While <FIG> have been described and illustrated above as including top oxide portion 105a, middle oxide portion 105b, and bottom oxide portion 105c, where the top and bottom oxide portions 105a and 105b have lower densities than the middle oxide portion 105b, other configurations and other relative densities of the oxide portions may be used depending on the intended use of the semiconductor structure <NUM>. In other embodiments and as explained in more detail below, the oxide material <NUM> may include a single oxide portion or two oxide portions having different densities.

In <FIG>, which is an example useful for understanding the invention, the oxide material <NUM> includes a substantially uniform oxide material with substantially the same density across the height of the oxide material <NUM>, which provides the semiconductor structure of <FIG> after further processing steps. During the wet etch process of <FIG>, a portion of the oxide material <NUM> may be removed in a horizontal direction (shown as arrow "H") and in a vertical direction (shown as arrow "V") such that the height L<NUM> of the control gate recess <NUM> is greater than the height L<NUM>. As the oxide material <NUM> in the stack <NUM> is made of an oxide material having a single density, the amount of removal in the vertical and horizontal directions is substantially the same.

In <FIG>, the oxide material <NUM> includes an oxide portion 105a over an oxide portion 105d, wherein the oxide portion 105a has a lower density than the oxide portion 105d. The oxide portion 105d of the oxide material <NUM> is in direct contact to the upper boundary of the adjacent control gate <NUM>, while the oxide portion 105a is in direct contact to the lower boundary of the adjacent control gate <NUM>. Since the oxide portion 105a has a lower density than the oxide portion 105d, the oxide portion 105a may be removed at a faster rate than the oxide portion 105d when exposed to the same etch chemistry. Thus, the amount of etching in the vertical direction for the oxide portions 105a, 105d adjacent the control gate recesses <NUM> are not the same when exposed to the same etch chemistry. As shown, the etching of the oxide portion 105a in the vertical direction is faster than the etching of the oxide portion 105d in the vertical direction due to the different densities of the oxide portion 105a, 105d.

In <FIG>, the oxide material <NUM> includes an oxide portion 105d over an oxide portion 105a, wherein the oxide portion 105a has a lower density than the oxide portion 105d. The oxide portion 105a of the oxide material <NUM> is in direct contact to the upper boundary of the adjacent control gate <NUM>, while the oxide portion 105d is in direct contact to the lower boundary of adjacent control gate <NUM>. Since the oxide portion 105a has a lower density than the oxide portion 105d, the oxide portion 105a is removed at a faster rate than the oxide portion105d when exposed to the same etch chemistry. Thus, the amount of etching in the vertical direction for the oxide portions 105a, 105d adjacent the control gate recesses <NUM> are not the same when exposed to the same etch chemistry. As shown, the etching of the oxide portion 105a in the vertical direction is faster than the etching of the oxide portion 105d in the vertical direction due to the different densities of the oxide portion 105a, 105d.

In some embodiments, the oxide material <NUM> may include the top oxide portion 105c, the middle oxide portion 105b and the bottom oxide portion 105a, wherein the densities of the top and bottom oxide portions 105c, 105a are substantially the same, and the densities of the top and bottom oxide portions 105c, 105a are up to about six times lower (i.e., 6x less dense) than the density of the middle oxide portion 105b.

In some embodiments, the oxide material <NUM> may include a top oxide portion 105c, middle oxide portion 105b and bottom oxide portion 105a, wherein the density of the top oxide portion 105c is from about six times lower (i.e., 6x less dense) to about two times higher (i.e., 2x more dense) than the density of the middle oxide portion 105b, and the density of the bottom oxide portion 105a is from about six times lower (i.e., 6x less dense) to about two times higher (i.e., 2x more dense) than the density of the middle oxide portion 105b. The densities of the top portion 105c and the bottom portion 105a may or may not be the same as each other.

Referring now to <FIG>, the charge blocking material, such as inter-poly dielectric (IPD) material, is formed on the exposed surface of the control gate recesses <NUM> and the sidewalls and floor of the opening <NUM> of the semiconductor structure <NUM> to provide the semiconductor structure of <FIG>. In one embodiment of the present disclosure, the charge blocking material is an inter-poly dielectric (IPD) material that includes dielectric materials <NUM>, <NUM> and <NUM>. In one embodiment, the charge blocking material is an inter-poly dielectric (IPD) material consists of oxide <NUM><NUM>-nitride <NUM>-oxide <NUM> (ONO) materials.

In <FIG>, a first dielectric material <NUM>, such as an oxide material, may be selectively formed on the sidewalls of the control gate material <NUM>. By way of non-limiting examples, the first dielectric material <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials.

In some embodiments, the first dielectric material <NUM> may be silicon oxide. Any convention method for forming a dielectric material may be used. By way of non-limiting example, the dielectric material may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. To selectively form the first dielectric material <NUM>, the first dielectric material <NUM> may be grown on the control gate material <NUM>. In one embodiment, the first dielectric material <NUM> may be grown on the exposed surface of control gate material <NUM> through an In Situ Steam Generation (ISSG) process, physical vapor deposition (PVD), furnace growth (diffusion), or combinations thereof.

In <FIG>, a second dielectric material <NUM> such as a nitride material is formed substantially conformally on the exposed surfaces of the oxide material <NUM>, the first dielectric material <NUM> in the control gate recesses <NUM>, the etch stop material <NUM> and the exposed surface of the control gate material <NUM>. In some embodiments, the second dielectric material <NUM> is silicon nitride. Any conventional method for forming the nitride material may be used and, therefore, is not described in detail herein.

A third dielectric material <NUM> may be formed substantially conformally over the second dielectric material <NUM>, providing the semiconductor structure <NUM> of <FIG>. Any conventional method for forming the third dielectric material <NUM> may be used, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. The third dielectric material <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials. In some embodiments, the third dielectric material <NUM> is silicon oxide. The first and third dielectric materials <NUM>, <NUM> may be independently selected so that the same or different oxide materials are used. Depending on the materials selected, the inter-poly dielectric (IPD) material may include an oxide-nitride-oxide (ONO) material of the first dielectric oxide material <NUM>-the second dielectric nitride material <NUM>-the first dielectric oxide material <NUM> on at least the area proximate the control gate recesses <NUM> on the sidewalls of the opening <NUM>. The IPD material (<NUM>, <NUM>, <NUM>) may occupy the area in the control gate recesses <NUM> such that the height L<NUM> of the resulting control gate recesses is substantially equal to the height L<NUM> of the adjacent control gate material <NUM>.

Referring to <FIG>, floating gate material <NUM> may be formed in the control gate recesses <NUM> adjacent to the third dielectric material <NUM> to substantially fill the remaining volume of the control gate recesses <NUM>. The floating gate material <NUM> may be separated from the adjacent control gate material <NUM> by the IPD material (<NUM>, <NUM>, <NUM>). Thus, the semiconductor structure <NUM> includes floating gates <NUM> that are discrete and isolated from one another and from the control gates <NUM> by IPD material (<NUM>, <NUM>, <NUM>). By way of non-limiting example, the floating gate material <NUM> may include silicon, germanium, or silicon germanium. In one embodiment, the floating gate material <NUM> is polysilicon, such as n-doped polysilicon, p-doped polysilicon, or undoped polysilicon. The control gate material <NUM> and the floating gate material <NUM> may be independently selected so that the same or different materials are used. In one embodiment, the control gate material <NUM> and the floating gate material <NUM> are polysilicon. Any conventional method for forming the floating gate material <NUM> may be used and, therefore, is not described in detail herein.

After substantially filling the control gate recesses <NUM>, any excess floating gate material <NUM> may be removed using vapor ammonia, a mixture of ammonium fluoride and nitric acid (NH<NUM>F/HNO<NUM>), an ozone or hydrofluoric acid (HF) mix or cycle, a mixture of hydrofluoric acid and nitric acid (HF/HNO<NUM>), or a tetramethyl ammonium hydroxide (TMAH) process. The process used to remove any excess floating gate material <NUM> may be a function of the doping of the floating gate material <NUM>. For example, if the floating gate material <NUM> is an n-doped polysilicon, the TMAH process may be used to remove the excess floating gate material <NUM>. A vertical, exposed surface of the floating gate material <NUM> is substantially coplanar with a vertical, exposed surface of the third dielectric material <NUM>. As shown in <FIG>, the height L<NUM> of floating gate <NUM> is substantially the same as the height L<NUM> of control gate material <NUM>.

Referring to <FIG>, the depth of the opening <NUM> may then be increased such that the opening <NUM> extends through the control gate material <NUM> and into at least a portion of the source oxide material <NUM>. The depth of the opening <NUM> may be increased by etching the control gate material <NUM> and the source oxide material <NUM> by conventional techniques, which are not described in detail herein.

In some embodiments as shown in <FIG>, a tunnel dielectric material <NUM> (hereinafter sometimes referred to as "tunnel oxide material" by example) may be formed on the exposed surfaces of the floating gates <NUM> and the control gate material <NUM>. In some embodiments, the tunnel oxide material <NUM> may be silicon oxide. Any conventional method for forming a tunnel oxide material may be used. To selectively form the tunnel dielectric material <NUM>, the tunnel oxide material <NUM> may be grown on the exposed surfaces of the floating gates <NUM> and the control gate material <NUM>.

In some embodiments, a liner material, such as a polysilicon liner, may be formed on the exposed surface of the opening <NUM>, such as on the sidewalls of the opening <NUM>. For example, as shown in <FIG>, a liner material <NUM> may be formed on the exposed surfaces of the third dielectric material <NUM> and the tunnel oxide material <NUM>, and the exposed sidewalls of source oxide material <NUM>. The liner material <NUM> may protect oxide materials from downstream process acts.

Referring to <FIG>, the depth of the opening <NUM> may be extended through the source oxide material <NUM> to allow electrical contact to the source <NUM>. As shown in the embodiment of <FIG>, the remaining thickness of the source oxide material <NUM> and at least a portion of the source <NUM> may be removed such that the opening <NUM> extends through the stack <NUM>, the etch stop material <NUM>, the control gate material <NUM>, the source oxide material <NUM> and at least a portion of the source <NUM>. Any conventional method for removing the source oxide material <NUM> and at least a portion of the source <NUM> may be used and, therefore, is not described in detail herein.

In <FIG>, a channel material <NUM> may be formed to substantially fill the opening <NUM> of the semiconductor structure <NUM>. By way of non-limiting example, the channel material <NUM> may be conductively doped polysilicon. Any conventional method for forming the channel material <NUM> may be used and, therefore, is not described in detail herein.

In some embodiments, the semiconductor structure <NUM> of <FIG> may be subjected to a cleaning process prior to substantially filling the opening <NUM> with the channel material <NUM>. Any conventional method for cleaning process may be used and, therefore, is not described in detail herein.

As described herein, one or more embodiments of the present disclosure may enable an increased height of a floating gate to be formed, without jeopardizing the critical dimensions and without the addition of complex acts to the process. By modifying the process to form the floating gates and control gates at the same height, the floating gates and control gates may be aligned.

Although various embodiments herein have described using an oxide material having portions of different densities as a dielectric material, it is understood that other dielectric materials may be used. The dielectric material may be any insulative material that can be formed by a PECVD process in which processing parameters, such as power and frequency, are adjustable and result in portions of the insulative material having different densities. By way of non-limiting examples, the dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating material.

A semiconductor structure may include a stack of alternating oxide materials and control gates, each of the oxide materials comprising at least two oxide portions of different densities; charge storage structures (e.g., floating gates or charge traps) laterally adjacent to the control gates; a charge block material between each of the charge storage structures and the laterally adjacent control gates; and a pillar extending through the stack of alternating oxide materials and control gates.

A semiconductor structure may include a stack of alternating dielectric materials and control gates, the dielectric material comprising a top portion, a middle portion and a bottom portion, the top and bottom portions having lower densities than the middle portion; a charge storage structure having a height substantially the same as the height of an adjacent control gate; a charge block material between the charge storage structure and the adjacent control gate; and a channel material extending through the stack of alternating oxide materials and control gates.

<FIG> are cross-sectional views of some stages of forming a plurality of floating gates for 3D-NAND flash memory device according to one embodiment of the present disclosure, wherein the alternating dielectric materials of the stack may include at least two portions of different materials having different rates of removal when exposed to a single etch chemistry (i.e., the same etch chemistry). The different materials in the alternating dielectric materials may have substantially the same density or different densities.

<FIG> shows a semiconductor structure <NUM>' including a source <NUM>', a source oxide material <NUM>', a material <NUM>' to be used as a control gate of a select device (e.g., SGS), optionally an etch stop material <NUM>', a stack <NUM>' of alternating dielectric materials <NUM>' and control gates <NUM>' (of memory cells), and an opening <NUM>' extending through the stack <NUM>'. The dielectric material <NUM>' may include at least two portions of different materials having different rates of removal when exposed to the same etch chemistry. The different materials in the dielectric material may or may not have same density. Non-limiting examples of the materials suitable for the different portions of the alternating dielectric material may include an oxide-based material, a nitride-based material, an oxynitride-based material, or combinations thereof.

In some embodiments, each of the dielectric materials of the stack may include at least a first material portion and a second material portion, wherein the first material portion has an etch rate at least about two times greater than that of the second material portion when exposed to same etch chemistry. However, it is understood that the differences in removal rates of dielectric material portions may be varied, depending on specific integration schemes of the semiconductor structure.

By way of non-limiting example, as shown in <FIG>, the dielectric material <NUM>' may include a top material portion 105c', a middle material portion 105b', and a bottom material portion105a', wherein when exposed to the same etch chemistry, the top material portion 105c' has substantially the same rate of removal as the bottom material portion 105a' and a higher rate of removal than that of the middle material portion 105b'. As a non-limiting example, the top and bottom material portions (105c' and 105a') of the dielectric material <NUM>' may include silicon oxide (SiOx) material, and the middle material portion 105b' may include silicon nitride (SiNy) material. As another non-limiting example, the top and bottom material portions (105c' and 105a') of the dielectric material <NUM>' may include silicon oxide (SiOx) material and the middle material portion 105b' may include silicon oxynitride (SiOxNy) material.

Although the structure <NUM>' of <FIG> shows only one opening <NUM>', it is understood that the semiconductor structure <NUM>' may include more than one opening. Furthermore, while the dielectric material <NUM>' is illustrated in <FIG> as including three portions, it is understood that the dielectric material <NUM>' may include fewer than three material portions or more than three material portions.

As shown in <FIG>, portions of the control gate materials <NUM>' and portions of the dielectric materials <NUM>' in the stack <NUM>' may be removed to create control gate recesses <NUM>', where the upper and lower boundaries of the control gate recesses <NUM>' are defined by sidewalls of the adjacent dielectric materials <NUM>'. By way of non-limiting example, as shown in <FIG>, the top and bottom material portions (105c', 105a') of the dielectric materials <NUM>' may be removed without substantially removing a portion of the middle material portion 105b' to provide such that the control gate recesses <NUM>' having a height of L<NUM>, which is greater than the height L<NUM> of the adjacent control gate <NUM>'. As a non-limiting example, when the top and bottom material portions (105c' and 105a') of the dielectric material <NUM>' is composed of silicon oxide (SiOx) material and the middle material portion 105b' is composed of silicon nitride (SiNy) material, the silicon oxide (SiOx) material of the top and bottom material portions (105c' and 105a') may be removed at a faster rate than the silicon nitride (SiNy) material of the middle material portion 105b' by etching with an etchant selected from the group consisting of hydrogen fluoride (HF) solution, and buffered oxide etch (BOE) solution comprising HF and NH<NUM>F.

Therefore, the dimension, height and profile of the control gate recess <NUM>' may be controlled by appropriate selection of materials for each of the dielectric portions (e.g., 105a', 105b', 105c') in the dielectric material <NUM>', the thickness of each material portion, the etching conditions, and other various known factors.

Referring to <FIG>, a charge blocking trap structure (<NUM>'-<NUM>'-<NUM>'), such as inter-poly dielectric (IPD) material, may be formed on the exposed surface of the control gate recesses <NUM>' to occupy the area in the control gate recesses <NUM>' such that the height L<NUM> of the resulting control gate recesses is substantially equal to the height L<NUM> of the adjacent control gate material <NUM>'. The floating gate material <NUM>' may then be formed in the control gate recesses to substantially fill the remaining volume of the control gate recesses.

In some embodiments as shown in <FIG>, a tunnel dielectric material <NUM>' may be formed on the exposed surfaces of the floating gates <NUM>' and the control gate material <NUM>'. A liner material <NUM>' may be formed on the exposed surface of the opening <NUM>', and a channel material <NUM>' may be formed to substantially fill the opening <NUM>'.

A semiconductor structure may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates and having substantially the same height as the respective laterally adjacent control gate, a charge block material between each of the charge storage structures and the respective laterally adjacent control gate, and a pillar extending through the stack of alternating dielectric materials and control gates, wherein each of the dielectric materials of the stack comprises at least two portions of different materials having different rates of removal when exposed to the same etch chemistry.

The semiconductor structure (<NUM> of <FIG>, <NUM>' of <FIG>) maybe subjected to further processing for production of a semiconductor device. In one embodiment, the semiconductor structure (<NUM>, <NUM>') may be further processed by conventional techniques to form a semiconductor device, such as a 3D-NAND flash memory device. However, while the embodiments are described in connection with 3D-NAND flash memory devices, the disclosure is not so limited. The disclosure is applicable to other semiconductor structures and memory devices which may employ charge storage structures.

<FIG> illustrate some embodiments of forming a semiconductor structure (<NUM>, <NUM>') having charge storage structures (<NUM>, <NUM>') for a 3D-NAND device, and do not necessarily limit the number of alternating oxide materials (<NUM>, <NUM>') and control gate materials (<NUM>, <NUM>') in the stack (<NUM>, <NUM>'). In addition, the locations, numbers, and shapes of the charge storage structures (<NUM>, <NUM>'), or the profile and shape of the channel material (<NUM>, <NUM>') are not limited to the illustrated embodiments.

A method of forming a semiconductor structure can include utilizing an oxide material having at least two oxide portions of different densities, in combination with an optimized wet etching process for such oxide material to increase the height of charge storage structures formed between the oxide materials, to sculpt the profile of charge storage structures to the predetermined structure, or both.

One such method modifies the deposition process of oxide material and adds a wet etching step of the oxide material prior to formation of charge blocking material in the control gate recesses. Such a method may allow for an increased height of a charge storage structure without jeopardizing the critical dimensions and without complex additional steps.

Claim 1:
A method of fabricating a semiconductor structure, the method comprising:
forming a stack (<NUM>) of alternating dielectric materials (<NUM>) and control gate materials (<NUM>), each of the dielectric materials of the stack comprising at least two portions of materials formulated to have different rates of removal when exposed to the same etch chemistry and having different densities;
forming an opening (<NUM>) through the stack (<NUM>) of alternating dielectric materials (<NUM>) and control gate materials (<NUM>);
removing a portion of the control gate materials (<NUM>) to form control gate recesses (<NUM>) adjacent the control gate materials;
removing portions of the dielectric materials (<NUM>) adjacent the control gate recesses (<NUM>) to increase a height of the control gate recesses (<NUM>);
forming a charge blocking material (<NUM>, <NUM>, <NUM>) adjacent exposed surfaces of the control gate materials (<NUM>);
thereafter filling the control gate recesses with a charge storage material; and
removing excess portions of the charge storage material within the opening (<NUM>) to form discrete charge storage structures (<NUM>), wherein a vertical, exposed surface of the discrete charge storage structures (<NUM>) is coplanar with a vertical, exposed surface of a dielectric material (<NUM>) of the charge blocking material (<NUM>, <NUM>, <NUM>), and wherein a height (L<NUM>) of each of the discrete charge storage structures (<NUM>) is the same as a height (L<NUM>) of the adjacent control gate materials (<NUM>).