Patent Description:
<CIT> provides an integrated circuit includes a delay circuit and first and second interface circuits.

It is therefore an objective of the present invention to provide a system, which can achieve synchronization of data signals and the strobe signal under low power consumption and low latency, to solve the above-mentioned problems.

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to. The terms "couple" and "couples" are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

<FIG> shows a system <NUM> according to one embodiment of the present invention. As shown in <FIG>, the system <NUM> comprises two dies <NUM> and <NUM> connected to each other, wherein the die <NUM> serves as a transmitter to transmit a plurality of data signals DAT[n:<NUM>] and strobe signals STB and STBN to the die <NUM> serving as the receiver. The die <NUM> comprises a main data path and a main strobe path, wherein the main data path of the die <NUM> comprises a delay circuit such as a digital control delay line (DCDL) <NUM>, a clock tree synthesizer <NUM>, a plurality of serializer <NUM> and a plurality of transmitter input/output circuits (TXIO) <NUM>. The main strobe path of the die <NUM> comprises a delay circuit such as a DCDL <NUM>, two serializers <NUM> and <NUM>, and two TXIO <NUM> and <NUM>. In addition, the die <NUM> comprises a main data path and a main strobe path, wherein the main data path of the die <NUM> comprises a plurality of receiver input/output circuits (RXIO) <NUM> and a plurality of sampling circuits <NUM>. The main strobe path of the die <NUM> comprises a RXIO <NUM>, a strobe generator <NUM> and a clock tree synthesizer <NUM>. In this embodiment, the system <NUM> is a cross-chip system comprises a plurality of dies within a package (e.g., three-dimensional integrated circuit, 3D IC), however, this feature is not a limitation of the present invention. In other embodiments, the transmitter of the die <NUM> and the receiver of the die <NUM> may be integrated into a single die.

In the operation of the main data path of the die <NUM>, the DCDL <NUM> receives a reference clock signal CK_DAT to generate a delayed clock signal, and the clock tree synthesizer <NUM> receives the delayed clock signal to generate a plurality of clock signals CK_DAT' to the serializers <NUM>, respectively. The serializers <NUM> uses the clock signals CK_DAT' to sample a plurality of input signals Din to generate the data signals DAT[n:<NUM>] to the die <NUM> via the TXIO <NUM>. In the operation of the main strobe path of the die <NUM>, the DCDL <NUM> receives a reference clock signal CK_STB to generate a delayed clock signal CK_STB' , and the serializers <NUM> and <NUM> receives the delayed clock signal CK_STB' to generate the strobe signals STB and STBN (differential signals) to the die <NUM> via the TXIO <NUM> and <NUM>.

In the operation of the main strobe path of the die <NUM>, the RXIO <NUM> receives the strobe signals STB and STBN to generate a signal to the strobe signal generator <NUM> to generate a strobe signal, for the clock tree synthesizer <NUM> to generate a plurality of strobe signals STB' to the sampling circuits <NUM>, respectively. In the operation of the main data path of the die <NUM>, the RXIO <NUM> receives the data signals DAT[n:<NUM>], for the sampling circuits <NUM> to use the strobe signals STB' to sample the data signals DAT[n:<NUM>] to generate sampled signals, respectively.

In the conventional art, the main data path and the main strobe path of the die <NUM> are designed to have similar delay amount, that is the conventional art may add an additional clock tree synthesized between the DCDL <NUM> and the serializer <NUM>/<NUM>, so that the reference clock signal CK_DAT and the reference clock signal CK_STB are delayed with the same or similar delay amount. Similarly, the main data path and the main strobe path of the die <NUM> are also designed to have similar delay amount, that is the conventional art may add an additional delay circuit between the RXIO <NUM> and the sampling circuits <NUM>, so that the data signals DAT [n:<NUM>] and the received strobe signal are delayed with the same or similar delay amount. Therefore, because the conventional art uses a physical balance circuit to align the data signals and the strobe signals, the conventional art will increase data and strobe latency and lower the performance, and the power consumption is increased.

To solve the above problems of the conventional art, the die <NUM> and the die <NUM> are designed to have minimum intrinsic timing utilization to lower the data and strobe latency. Specifically, the main data path and the main strobe path within the die <NUM> have the unbalanced architecture, for example, the main strobe path does not have the clock tree synthesizer to lower the strobe latency. Therefore, in this embodiment, the phase of each of the data signals DAT[n:<NUM>] lags the phase of the strobe signals STB and STBN. Similarly, the main data path and the main strobe path within the die <NUM> may also have the unbalanced architecture, for example, the main data path of the die <NUM> does not have the clock tree synthesizer to lower the data latency.

In the embodiment shown in <FIG>, the die <NUM> and the die <NUM> are designed to have the unbalanced architecture to lower the data latency and the strobe latency, however, the unalined strobe signal or the misaligned strobe signal may cause the sampling circuits <NUM> to generate incorrect sampled signals. Therefore, the system <NUM> is further designed to have a deskew circuit <NUM> to generate control signals Vc_DAT and Vc_STB to control the delay amount of the DCDLs <NUM> and <NUM>, respectively, to make the data signals DAT[n:<NUM>] and the strobe signals STB' inputted into the sampling circuits <NUM> have the suitable phases. Specifically, referring to <FIG> which shows a timing diagram of the signals CK_DAT, CK_DAT', DAT, CK_STB, CK_STB', STB' according to one embodiment of the present invention. As shown in <FIG>, assuming that delay amount of the DCDL <NUM>, the clock tree synthesizer <NUM>, the DCDL <NUM> and the clock tree synthesizer <NUM> (with the strobe signal generator <NUM>) are DAT_DL, TX_CTS, STB_DL and RX_CTS, respectively, the total delay of the main data path of the die <NUM> is a summation of DAT_DL, TX_CTS and a driver delay (i.e. the delay caused by the serializers <NUM> and TXIO <NUM>), the total delay of the main strobe path of the die <NUM> is a summation of STB_DL and a driver delay (i.e. the delay caused by the serializers <NUM>, <NUM> and TXIO <NUM>, <NUM>), the total delay of the main data path of the die <NUM> is the delay caused by the RXIO <NUM>, and the total delay of the main strobe path of the die is a summation of RX_CTS and the delay caused by the RXIO <NUM>. Therefore, the deskew circuit <NUM> is configured to control the DCDLs <NUM> and <NUM> so that a rising edge of the strobe signal STB' is at the center of the data signal DAT, that is the DCDLs <NUM> and <NUM> are controlled to satisfy the following equation:<MAT> wherein the symbol "UI" is an unit interval of the clock signal (i.e., half of the clock cycle), and it is assumed that the clock signals used in the main data path and the main strobe path have substantially the same frequency.

<FIG> is a diagram illustrating the deskew circuit <NUM> according to one embodiment of the present invention. As shown in <FIG>, the deskew circuit <NUM> comprises a first circuit <NUM> and a second circuit <NUM>, wherein the first circuit <NUM> is within the die <NUM>, and the second circuit <NUM> is within the die <NUM>. The first circuit <NUM> comprises a control circuit <NUM>, a data path and a strobe path, wherein the data path of the first circuit comprises a DCDL <NUM>, a clock tree synthesizer <NUM>, a DCDL <NUM>, a clock tree synthesizer <NUM>, a serializer <NUM> and a TXIO <NUM>; and the strobe path of the first circuit <NUM> comprises a two DCDLs <NUM> and <NUM>, two serializers <NUM> and <NUM>, and two TXIO <NUM> and <NUM>. The second circuit <NUM> comprises a data path and a strobe path, wherein the data path of the second circuit <NUM> comprises a RXIO <NUM> and a phase detector <NUM>; and the strobe path of the second circuit <NUM> comprises a RXIO <NUM>, a strobe signal generator <NUM>, a clock tree synthesizer <NUM>, the strobe signal generator <NUM> and a clock tree synthesizer <NUM>.

In this embodiment, the data path of the first circuit <NUM> of the deskew circuit <NUM> is designed to have the DCDL <NUM>, the clock tree synthesizer <NUM>, the DCDL <NUM> and the clock tree synthesizer <NUM> so that its delay amount is twice that of the main data path of the die <NUM>. Specifically, each of the DCDL <NUM> and the DCDL <NUM> can be controlled by the control signal Vc_DAT, so that the DCDL <NUM>, the DCDL <NUM> and the DCDL <NUM> have the same delay amount; and the delay amount of each of the clock tree synthesizers <NUM> and <NUM> is equal to the delay amount of the clock tree synthesizer <NUM>. Similarly, the strobe path of the first circuit <NUM> of the deskew circuit <NUM> is designed to have the DCDL <NUM> and the DCDL <NUM> so that its delay amount is twice that of the main strobe path of the die <NUM>. Specifically, each of the DCDL <NUM> and the DCDL <NUM> can be controlled by the control signal Vc_STB, so that the DCDL <NUM>, the DCDL <NUM> and the DCDL <NUM> have the same delay amount. In addition, the strobe path of the second circuit <NUM> of the deskew circuit <NUM> is designed to have the strobe signal generator <NUM>, the clock tree synthesizer <NUM>, the strobe signal generator <NUM> and the clock tree synthesizer <NUM> so that its delay amount is twice that of the main strobe path of the die <NUM>. Specifically, the strobe signal generators <NUM>, <NUM> and <NUM> have the same delay amount, and the delay amount of each of the clock tree synthesizers <NUM> and <NUM> is equal to the delay amount of the clock tree synthesizer <NUM>.

In the operation of the data path of the first circuit <NUM> of the deskew circuit <NUM>, the reference clock signal CK_DAT passes throughs the DCDL <NUM>, the clock tree synthesizer <NUM>, the DCDL <NUM> and the clock tree synthesizer <NUM> to generate a delayed clock signal, and the serializers <NUM> uses the delayed clock signal to sample the input signal such as Din to generate the data signal DS_DAT to the die <NUM> via the TXIO <NUM>. In the operation of the strobe path of the first circuit <NUM> of the deskew circuit <NUM>, the reference clock signal CK_STB passes through the DCDL <NUM> and the DCDL <NUM> to generate a delayed clock signal, and the serializers <NUM> and <NUM> receives the delayed clock signal to generate the strobe signals DS_STB and DS_STBN (differential signals) to the die <NUM> via the TXIO <NUM> and <NUM>.

In the operation of the strobe path of the second circuit <NUM> of the deskew circuit <NUM>, the RXIO <NUM> receives the strobe signals DS_STB and DS_STBN to generate a signal, and this signal passes through the strobe signal generator <NUM>, the clock tree synthesizer <NUM>, the strobe signal generator <NUM> and the clock tree synthesizer <NUM> to generate a strobe signal DS_STB'. In the operation of the data path of the second circuit <NUM> of the deskew circuit <NUM>, the RXIO <NUM> receives the data signal DS_DAT, and the phase detector <NUM> compares phases of the data signal DS_DAT and the strobe signal DS_STB' to generate a phase detection result DS_PD to the control circuit <NUM> to align the data signal DS_DAT and the strobe signal DS_STB'. For example, when the phase detection result DS_PD indicates that the phase of the data signal DS_DAT lags the phase of the strobe signal DS_STB', the control circuit <NUM> generates the control signal Vc_DAT to reduce the delay mount of the DCDL <NUM>/<NUM>, and/or generates the control signal Vc_STB to increase the delay amount of the DCDL <NUM>/<NUM>. In addition, when the phase detection result DS_PD indicates that the phase of the data signal DS_DAT leads the phase of the strobe signal DS_STB', the control circuit <NUM> generates the control signal Vc_DAT to increase the delay mount of the DCDL <NUM>/<NUM>, and/or generates the control signal Vc_STB to reduce the delay amount of the DCDL <NUM>/<NUM>.

By using the control circuit <NUM> of the deskew circuit <NUM> to refer to the phase detection result DS_PD to align the data signal DS_DAT and the strobe signal DS_STB', the main data path and the main strobe path of the die <NUM> and the die <NUM> can be automatically controlled so that the rising edge of the strobe signal STB' is at the center of the data signal DAT, for the sampling circuit <NUM> to output the correct sampled signal. Specifically, referring to <FIG> which shows a timing diagram of the signals CK, STB, STB', DS_DAT, DS_STB and DS_STB' according to one embodiment of the present invention. As shown in <FIG>, the deskew circuit <NUM> is configured to control the DCDLs <NUM>, <NUM>, <NUM> and <NUM> to align the data signal DS_DAT and the strobe signal DS_STB', that is the DCDLs <NUM>, <NUM>, <NUM> and <NUM> are controlled to satisfy the following equation:<MAT> wherein the symbol DL is equal to a difference between the delay amount of the DCDL <NUM> and the delay amount of the DCDL <NUM>, that is DL = (STB_DL - DAT_DL). In addition, since equation (<NUM>) is satisfied, the equation (<NUM>) is satisfied.

Claim 1:
A system (<NUM>), comprising:
a transmitter (<NUM>), comprising a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals (DAT [n:<NUM>]), the first main strobe path is configured to generate a first strobe signal (STB, STBN), the first main data path comprises a first delay circuit (<NUM>), the first main strobe path comprises a second delay circuit (<NUM>), and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced so that the first strobe signal (STB, STBN) and the plurality of data signals (DAT[n:<NUM>]) are not aligned; and
a receiver (<NUM>), comprising a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal (STB, STBN) to generate a plurality of second strobe signals (STB'), and the second main data path is configured to receive the plurality of data signals (DAT [n: <NUM>]), and uses the plurality of second strobe signals (STB') to sample the plurality of data signals (DAT[n:<NUM>]) to generate a plurality of sampled signals, respectively;
a deskew circuit (<NUM>), configured to generate a first control signal (Vc_DAT) and a second control signal (Vc_STB) to control delay amount of the first delay circuit (<NUM>) and the second delay circuit (<NUM>), respectively;
characterized in that the first main data path comprises:
the first delay circuit (<NUM>), configured to receive a first reference clock signal (CK_DAT) to generate a delayed first reference clock signal;
a clock tree synthesizer (<NUM>), configured to receive the delayed first reference clock signal to generate a plurality of first clock signals (CK_DAT'); and
a plurality of first serializers (<NUM>), configured to use the plurality of first clock signals (CK_DAT') to sample input signals (Din) to generate the plurality of data signals (DAT [n:<NUM>]); and
the first main strobe path comprises:
the second delay circuit (<NUM>), configured to receive a second reference clock signal (CK_STB) to generate a second clock signal (CK_STB');
a second serializer (<NUM>), configured to receive the second clock signal (CK_STB') to generate the first strobe signal (STB, STBN) .