Patent Description:
Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, photodetectors, modulators, and optical power splitters, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip.

Document <CIT> shows a structure, comprising a substrate, a first waveguide core on the substrate, the first waveguide core comprised of silicon nitride, and an active layer positioned proximate to a section of the first waveguide core. The active layer is comprised of a phase change material having a first state with a first refractive index and a second state with a second refractive index.

In document <CIT>, a spot-size converter is described. The spot-size converter comprises a first substrate, a first core that is provided on the first substrate and is extended from a first end configured to input/output light toward a second end, a second core that is formed by a plurality of cores, and formed at a position to be evanescent-coupled to the first core in a lamination direction, and moreover extended along a direction from the first end toward the second end, and a third core that has a taper unit whose cross section increases along the direction from the first end toward the second end, and that is formed at a position to be evanescent-coupled to the second core in the lamination direction, and moreover extended along the direction from the first end toward the second end.

Improved waveguide structures and methods of fabricating a waveguide structure are needed.

In an embodiment of the invention, a structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material. The first material is a silicon and the second material is silicon nitride.

In another embodiment of the invention, a method includes forming a first waveguide core and a second waveguide core that comprise a first material, and forming a third waveguide core that comprises a second material different in composition from the first material. The third waveguide core is positioned adjacent to the first waveguide core and the second waveguide core, the third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first material is a silicon and the second material is silicon nitride.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

With reference to <FIG> and in accordance with embodiments of the invention, a waveguide structure <NUM> includes a waveguide cores <NUM>, <NUM> that are positioned over a dielectric layer <NUM>. The waveguide cores <NUM>, <NUM> may be comprised of a high refractive-index material. The waveguide cores <NUM>, <NUM> are comprised of a semiconductor material, such as single-crystal silicon patterned by lithography and etching processes from a device layer of a silicon-on-insulator substrate in an embodiment. The silicon-on-insulator substrate further includes a buried insulator layer comprised of a dielectric material, such as silicon dioxide, that may provide the dielectric layer <NUM> and a handle substrate <NUM> comprised of a semiconductor material, such as single-crystal silicon, beneath the buried insulator layer.

The waveguide cores <NUM>, <NUM> may be located in a region of a monolithic photonics chip. A field-effect transistor, diagrammatically indicated by reference numeral <NUM>, may be located in a different region of the monolithic photonics chip. The field-effect transistor <NUM> may be formed using the same semiconductor layer used to form the waveguide cores <NUM>, <NUM>. Alternatively, the waveguide cores <NUM>, <NUM> may be located in a region of a standalone photonics chip.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, a dielectric layer <NUM> is formed over the waveguide cores <NUM>, <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide, that is deposited and then polished to remove topography. The thickness of the dielectric layer <NUM> may be greater than the thickness of the waveguide cores <NUM>, <NUM> such that the waveguide cores <NUM>, <NUM> are embedded in the dielectric layer <NUM>. A dielectric layer <NUM> is formed that extends across the field-effect transistor <NUM> and that deposits on the dielectric layer <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon nitride, and may be conformally deposited.

A dielectric layer <NUM> of a contact level may be formed by middle-of-line processing. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide, and may include contacts that are connected to the field-effect transistor <NUM>.

A trench <NUM> may be patterned that extends through the dielectric layers <NUM>, <NUM>, <NUM> to the dielectric layer <NUM>. In an embodiment, the trench <NUM> may extend fully through the dielectric layers <NUM>, <NUM>, <NUM> to the dielectric layer <NUM>. The waveguide core <NUM> is laterally spaced from the waveguide core <NUM> such that the trench <NUM> does not overlap with either of the waveguide cores <NUM>, <NUM>. A thickness of the dielectric material of the dielectric layer <NUM> is positioned between each of the waveguide cores <NUM>, <NUM> and a sidewall <NUM> surrounding the trench <NUM>.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, a dielectric layer <NUM> may be deposited inside the trench <NUM>. The dielectric layer <NUM>, which is comprised of a dielectric material, includes a divot that may be filled by an etch mask <NUM>, such as a photoresist. In an embodiment, the dielectric layer <NUM> may be comprised of silicon nitride.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, a waveguide core <NUM> is formed the trench <NUM> from the dielectric layer <NUM> by an etching process. The portion of the dielectric layer <NUM> that is masked by the etch mask <NUM> provides the waveguide core <NUM> following the etching process. After patterning the waveguide core <NUM>, the etch mask <NUM> may be removed.

The waveguide core <NUM> is positioned adjacent to the waveguide core <NUM>, and the waveguide core <NUM> is also positioned adjacent to the waveguide core <NUM>. The waveguide core <NUM> is positioned laterally between the waveguide core <NUM> and the waveguide core <NUM>. The waveguide core <NUM> is laterally spaced from the waveguide core <NUM> by a slot <NUM>, and the waveguide core <NUM> is laterally spaced from the waveguide core <NUM> by a slot <NUM>. The slot <NUM> may have a width dimension measured between the nearest sidewalls of the waveguide core <NUM> and the waveguide core <NUM>, the slot <NUM> may have a width dimension measured between the nearest sidewalls of the waveguide core <NUM> and the waveguide core <NUM>, and the width dimensions may range in value from <NUM> nanometers to <NUM> microns. In an embodiment, the waveguide core <NUM> may be symmetrically positioned between the waveguide core <NUM> and the waveguide core <NUM> such that the slots <NUM>, <NUM> have equal or substantially equal width dimensions.

The waveguide core <NUM> has a bottom surface <NUM> that may be in direct contact with the dielectric layer <NUM>, and the waveguide core <NUM> has a bottom surface <NUM> that may be in direct contact with the dielectric layer <NUM>. The waveguide core <NUM> has a bottom surface <NUM> that may also be in direct contact with the dielectric layer <NUM>. The waveguide cores <NUM>, <NUM> and the waveguide core <NUM> may be considered to be arranged at the same level of the waveguide structure <NUM> because the respective bottom surfaces <NUM>, <NUM>, <NUM> may all be in direct contact with the same planar surface of the dielectric layer <NUM>. As a result of the common reference plane defined by the dielectric layer <NUM>, the bottom surfaces <NUM>, <NUM>, <NUM> may be coplanar.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, a dielectric layer <NUM> may be subsequently deposited and planarized to refill the open space remaining in the trench <NUM>, after the formation of the waveguide core <NUM>, with dielectric material. In an embodiment, the dielectric material of the dielectric layer <NUM> may be comprised of silicon dioxide. Each of the slots <NUM>, <NUM> is filled in part by the dielectric material of the dielectric layer <NUM> and in part by the dielectric material of the dielectric layer <NUM>. The dielectric materials of the dielectric layers <NUM>, <NUM>, which may be the same dielectric material, may differ in composition from the materials of the waveguide cores <NUM>, <NUM>, <NUM>. In an embodiment, the dielectric material filling the slots <NUM>, <NUM> has a lower refractive index than the materials of the waveguide cores <NUM>, <NUM>, <NUM>.

A back-end-of-line stack <NUM> may be formed by back-end-of-line processing over the dielectric layers <NUM>, <NUM>. The back-end-of-line stack <NUM> may include one or more interlayer dielectric layers each comprised of a dielectric material, such as silicon dioxide or silicon nitride. The back-end-of-line stack <NUM> may also include metal lines, vias, and contacts that are connected to the field-effect transistor <NUM>.

The waveguide structure <NUM> is heterogeneous in that the waveguide cores <NUM>, <NUM> are comprised of a different material than the waveguide core <NUM>. According to the claimed invention, the waveguide cores <NUM>, <NUM> are comprised of silicon, and the waveguide core <NUM> is comprised of silicon nitride. The waveguide structure <NUM> includes multiple waveguide cores <NUM>, <NUM>, <NUM> with lateral positioning and multiple slots laterally between the waveguide cores <NUM>, <NUM>, <NUM> of alternating composition. In the representative embodiment, the waveguide structure <NUM> including the waveguide cores <NUM>, <NUM>, <NUM> has a dual-slot configuration. In alternative embodiments, the number of waveguide cores of alternating composition and the number slots may be greater than included in the representative embodiment. In alternative not according to the claimed invention, the alternating materials may be extended to include other combinations of alternating materials, such as silicon oxynitride and silicon nitride, silicon and silicon oxynitride, etc., as well as other material systems such as III-V compound semiconductor material systems and polymer material systems.

The heterogeneous, multiple-slot waveguide structure <NUM> may support well-confined photonic modes and can serve as a building block for functional optical components. The heterogeneous, multiple-slot waveguide structure <NUM> may exhibit a significantly reduced power ratio inside the waveguide cores <NUM>, <NUM> for improved power handling. The addition of the waveguide core <NUM> and the slots <NUM>, <NUM> may, in combination, reduce the power density of the waveguide structure <NUM>, which may increase the nonlinear threshold. The selection of silicon nitride as a material for the waveguide core <NUM> may be effective to increase the power handling and reduce the thermal sensitivity of the waveguide structure <NUM>.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and in accordance with alternative embodiments of the invention, the waveguide structure <NUM> may be modified to add another waveguide core <NUM> that is positioned on the dielectric layer <NUM> adjacent to the waveguide core <NUM>. The waveguide core <NUM> may be comprised of the same material as the waveguide core <NUM>. In an embodiment, the waveguide core <NUM> may be comprised of silicon nitride. The waveguide core <NUM> may be formed by patteming a trench similar to the trench <NUM> and then by patterning the dielectric layer <NUM> deposited in this additional trench.

The waveguide core <NUM> is positioned laterally between the waveguide core <NUM> and the waveguide core <NUM>. The waveguide core <NUM> is laterally spaced from the waveguide core <NUM> by a slot <NUM> that is filled in part by the dielectric material of the dielectric layer <NUM> and in part by the dielectric material of the dielectric layer <NUM>. The slot <NUM> may have a width dimension measured between the nearest sidewalls of the waveguide core <NUM> and the waveguide core <NUM>, and the width dimension may range in value from <NUM> nanometers to <NUM> microns. The waveguide core <NUM> has a bottom surface <NUM> that may also be in direct contact with the dielectric layer <NUM>. The waveguide cores <NUM>, <NUM> and the waveguide cores <NUM>, <NUM> may be considered to be arranged at the same level of the waveguide structure <NUM> because the respective bottom surfaces <NUM>, <NUM>, <NUM>, <NUM> may be in direct contact with the same planar surface of the dielectric layer <NUM>. As a result of the common reference plane defined by the dielectric layer <NUM>, the bottom surfaces <NUM>, <NUM>, <NUM>, <NUM> may be coplanar.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and in accordance with alternative embodiments not according to the claimed invention, the waveguide structure <NUM> may be modified to eliminate the waveguide core <NUM> such that the waveguide core <NUM> and the waveguide cores <NUM>, <NUM> remain. The waveguide structure <NUM> includes slots <NUM>, <NUM>, and the materials of the waveguide cores <NUM>, <NUM>, <NUM> alternate laterally.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/- <NUM>% of the stated value(s).

References herein to terms such as "vertical", "horizontal", etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

A feature "connected" or "coupled" to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or with another feature if intervening features are absent. A feature may be "indirectly connected" or "indirectly coupled" to or with another feature if at least one intervening feature is present. A feature "on" or "contacting" another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be "directly on" or in "direct contact" with another feature if intervening features are absent. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present. Different features "overlap" if a feature extends over, and covers a part of, another feature.

Claim 1:
A structure (<NUM>), comprising:
a first waveguide core (<NUM>);
a second waveguide core (<NUM>); and
a third waveguide core (<NUM>) adjacent to the first waveguide core (<NUM>) and the second waveguide core (<NUM>), the third waveguide core (<NUM>) laterally separated from the first waveguide core (<NUM>) by a first slot (<NUM>), the third waveguide core (<NUM>) laterally separated from the second waveguide core (<NUM>) by a second slot (<NUM>),
wherein the first waveguide core (<NUM>) and the second waveguide core (<NUM>) comprise a first material, and the third waveguide core (<NUM>) comprises a second material that is different in composition from the first material,
characterized in that
the first material is silicon and the second material is silicon nitride.