Patent Description:
With rapid development of wireless communications technologies, a radio frequency integrated circuit (radio frequency integrated circuit, RFIC) becomes increasingly important. The radio frequency integrated circuit may be an integrated circuit operating within a frequency range of <NUM> megahertz (MHz) to <NUM> gigahertz (GHz). With arrival of latest fifth-generation mobile communications, a signal frequency greatly increases. This brings faster communication experience to people, and also brings greater challenges and opportunities to the radio frequency integrated circuit.

In the integrated circuit, a plurality of layers of electronic components are connected through metal wires to form a complete logic circuit. Based on a chemical mechanical polishing (chemical mechanical polishing, CMP) process, molding quality of each layer of metal wire in the integrated circuit is closely related to a metal arrangement area of a bottom metal layer of the metal wire. If the metal arrangement area of the bottom metal layer of the metal wire is insufficient, a yield of the metal wire is poor, and a line is likely to be short-circuited.

To resolve this problem, a common practice is to add a dummy metal (dummy metal) to a bottom metal of the metal wire to increase the metal arrangement area. However, when the metal wire serves as an inductor device, the dummy metal under the inductor device affects performance of the inductor device, thereby resulting in poor performance of the inductor device.

<CIT> discloses a dummy metal filling structure including multiple dummy metal layers, wherein each dummy metal layer includes a plurality of dummy metals, and the dummy metal in each dummy metal layer is the same as the phase. The dummy metals in the adjacent dummy metal layers are arranged crosswise, so that the dummy metals are distributed more uniformly, and the influence of the dummy metals on the performance of the integrated circuit is reduced.

<CIT> discloses a semiconductor device with a SOI substrate including a semiconductor substrate, a BOX layer on the semiconductor substrate, and a semiconductor layer on the BOX layer, a multilayer wiring formed over a main surface of the SOI substrate, and an inductor comprised of the multilayer wiring.

<CIT> discloses a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view.

<CIT> discloses a partial metal fill within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.

An inductor wiring architecture is disclosed as recited in claim <NUM>. An integrated circuit is disclosed as recited in claim <NUM>. A communication device is disclosed as recited in claim <NUM>.

In the inductor device wiring architecture, adverse effects on performance of an inductor device can be reduced, and a product yield can be increased.

According to a first aspect, an embodiment of this application provides an inductor device wiring architecture. The inductor device wiring architecture may be applied to an integrated circuit. The inductor device wiring architecture includes an inductor device and a plurality of dummy metals located under the inductor device. The plurality of dummy metals are arranged in a plurality of metal layers. Each of the plurality of metal layers corresponds to some of the plurality of dummy metals. Arrangement areas of dummy metals corresponding to at least three adjacent metal layers of the plurality of metal layers progressively increase in a direction away from the inductor device. In other words, arrangement areas of dummy metals corresponding to at least three adjacent metal layers located under the inductor device progressively increase.

In this embodiment, the arrangement areas of the dummy metals corresponding to the at least three adjacent metal layers of the plurality of metal layers under the inductor device progressively increase in the direction away from the inductor device. In this case, an arrangement area of dummy metals corresponding to a metal layer close to the inductor device is smaller, and an arrangement area of dummy metals corresponding to a metal layer away from the inductor device is larger. To be specific, during arrangement, the plurality of dummy metals located under the inductor device are kept away from the inductor device as far as possible, fewer dummy metals are in a region close to the inductor device, and more dummy metals are in a region away from the inductor device, thereby reducing adverse effects of the dummy metals on performance of the inductor device, or even eliminating impact on performance of the inductor device. In addition, each metal layer under the inductor device has a relatively sufficient metal arrangement area. This can meet a processing requirement of chemical mechanical polishing, thereby improving processing quality, and achieving a higher product yield of the inductor device wiring architecture and the integrated circuit in which the inductor device wiring architecture is used.

In an optional embodiment, a space under the inductor device includes a space in which a wiring region of the inductor device is projected along a vertical direction of a metal layer in which the inductor device is located. The wiring region of the inductor device includes at least a region surrounded by an outer edge of an outermost wire of the inductor device.

In an optional embodiment, the plurality of dummy metals are arranged in a stepped shape. To be specific, in the plurality of metal layers under the inductor device, a dummy metal corresponding to a lower metal layer extends out relative to a dummy metal corresponding to an upper metal layer to form a stepped shape.

In this embodiment, because the plurality of dummy metals under the inductor device are arranged in the stepped shape, the plurality of dummy metals can effectively improve metal arrangement under the inductor device, so that higher manufacturing precision of the inductor device is high during chemical mechanical polishing, and a product yield of the inductor device wiring architecture and the integrated circuit in which the inductor device wiring architecture is used is higher. In addition, the plurality of dummy metals can be arranged not in a region close to the inductor device, but arranged in a region away from the inductor device as far as possible, thereby reducing adverse effects of the dummy metals on performance of the inductor device, and improving performance of the inductor device.

The inductor device wiring architecture may further include a plurality of dummy metals arranged in a same layer as that of the inductor device. Some dummy metals arranged in the same layer as that of the inductor device may be jointly arranged in a stepped shape with the plurality of dummy metals located under the inductor device. In this case, the dummy metals arranged in the same layer as that of the inductor device have less impact on performance of the inductor device, processing quality of the inductor device is higher, and a product yield of the inductor device wiring architecture is higher.

In an optional embodiment, the plurality of dummy metals under the inductor device present a continuous stepped shape. This helps further improve processing quality of the inductor device wiring architecture, and the plurality of dummy metals have less impact on performance of the inductor device.

In an optional embodiment, an arrangement area of dummy metals corresponding to an ith metal layer under the inductor device is the same as an arrangement area of dummy metals corresponding to an (i - <NUM>)th metal layer, the ith metal layer is located on a side, of the (i - <NUM>)th metal layer, that is away from the inductor device, and i is an integer greater than or equal to <NUM>.

In this embodiment, when the inductor device wiring architecture roughly meets an arrangement rule of transitioning from a sparse arrangement to a dense arrangement, two metal layers corresponding to dummy metals with a same arrangement area are included under the inductor device, so that arrangement flexibility of the plurality of dummy metals in the inductor device wiring architecture is higher, and arrangement manners are more diversified.

The inductor device wiring architecture may include one group of two metal layers corresponding to dummy metals with a same arrangement area, or may include more than two (including two) groups of two metal layers corresponding to dummy metals with a same arrangement area. Alternatively, the inductor device wiring architecture may include more than three (including three) metal layers corresponding to dummy metals with a same arrangement area.

In an optional embodiment, a plurality of dummy metals corresponding to the ith metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals is an ith spacing; a plurality of dummy metals corresponding to the (i - <NUM>)th metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals is an (i - <NUM>)th spacing; and the (i - <NUM>)th spacing is less than the ith spacing. In this case, although metal arrangement areas of the ith metal layer do not progressively increase, the plurality of dummy metals corresponding to the ith metal layer have a larger arrangement range and a more uniform arrangement. This effectively improves processing quality of the metal layer, and achieves a higher product yield of the inductor device wiring architecture.

In an optional embodiment, an arrangement area of dummy metals corresponding to a jth metal layer under the inductor device is smaller than an arrangement area of dummy metals corresponding to a (j - <NUM>)th metal layer, the jth metal layer is located on a side, of the (j - <NUM>)th metal layer, that is away from the inductor device, and j is an integer greater than or equal to <NUM>.

In this implementation, when the inductor device wiring architecture roughly meets an arrangement rule of transitioning from a sparse arrangement to a dense arrangement, two metal layers corresponding to dummy metals are included under the inductor device, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer, so that arrangement flexibility of the plurality of dummy metals in the inductor device wiring architecture is higher, and arrangement manners are more diversified.

The inductor device wiring architecture may include one group of two metal layers corresponding to dummy metals, or may include more than two (including two) groups of two metal layers corresponding to dummy metals, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer. Alternatively, the inductor device wiring architecture may include more than three (including three) metal layers corresponding to dummy metals, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer.

In an optional embodiment, a plurality of dummy metals corresponding to the jth metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals is a jth spacing; a plurality of dummy metals corresponding to the (j - <NUM>)th metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals is a (j - <NUM>)th spacing; and the (j - <NUM>)th spacing is less than the jth spacing. In this case, the plurality of dummy metals corresponding to the jth metal layer with a smaller metal arrangement area have a larger arrangement range and a more uniform arrangement. This effectively improves processing quality of the metal layer, and achieves a higher product yield of the inductor device wiring architecture.

In an optional embodiment, under the inductor device, each metal layer (a metal layer of the plurality of metal layers) corresponds to a plurality of dummy metals, and dummy metals corresponding to each metal layer are arranged in a staggered manner with dummy metals corresponding to an adjacent metal layer. In this case, the plurality of dummy metals under the inductor device are arranged more regularly, thereby helping reduce design costs and production costs of the inductor device wiring architecture.

In an optional embodiment, under the inductor device, each metal layer (a metal layer of the plurality of metal layers) has a plurality of dummy metals, and dummy metals corresponding to each metal layer are arranged in alignment with dummy metals corresponding to an adjacent metal layer. In this case, the plurality of dummy metals under the inductor device are arranged more regularly, thereby helping reduce design costs and production costs of the inductor device wiring architecture.

In an optional embodiment, under the inductor device, each metal layer (a metal layer of the plurality of metal layers) corresponds to a plurality of dummy metals, dummy metals corresponding to one or more metal layers are arranged in a staggered manner with dummy metals corresponding to an adjacent metal layer, and dummy metals corresponding to one or more metal layers are arranged in alignment with dummy metals corresponding to an adjacent metal layer.

In this case, under the inductor device in the inductor device wiring architecture, some dummy metals are arranged in alignment, and some dummy metals are arranged in a staggered manner. This enriches arrangement manners of the plurality of dummy metals, and makes arrangement manners of the inductor device wiring architecture more diversified.

In an optional embodiment, the inductor device is an inductor with two ports or a transformer with four ports. The inductor with two ports includes but is not limited to a helical inductor, a differential inductor, and the like. In this application, the inductor device may have a plurality of implementation structures, and the inductor device wiring architecture has a wider application scope.

In an optional embodiment, the inductor device is arranged in one metal layer; or the inductor device includes an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers. The upper inductor and the lower inductor may be connected by using a conductive material, so that the inductor device serves as a multilayer metal serial inductor. In this application, the inductor device may have a plurality of implementation structures, and the inductor device wiring architecture has a wider application scope.

According to a second aspect, an embodiment of this application further provides an integrated circuit, including the inductor device wiring architecture according to any one of the foregoing implementations. Because the inductor device wiring architecture has lower costs and has a little adverse effect on performance of an inductor device, the integrated circuit has low costs and high performance.

According to a third aspect, an embodiment of this application further provides a communications device, including the foregoing integrated circuit.

An embodiment of this application provides a communications device. The communications device may be a wireless fidelity (wireless fidelity, Wi-Fi) device, a Bluetooth (bluetooth) device, an infrared device, a global positioning system (global positioning system, GPS) device, a near-field communication (near-field communication, NFC) device, a mobile communications device, a router, a photoelectric device, a base station, a microwave device, or the like.

The communications device includes an integrated circuit (integrated circuit, IC). For example, the communications device includes a high frequency integrated circuit (high frequency integrated circuit, HFIC). The high frequency integrated circuit is an integrated circuit whose operating frequency is greater than <NUM> megahertz (MHz). For example, the high frequency integrated circuit may be a radio frequency integrated circuit (radio frequency integrated circuit, RFIC). The radio frequency integrated circuit may operate within a range of <NUM> megahertz to <NUM> gigahertz (GHz) to implement a specific radio frequency function.

In an embodiment, the integrated circuit includes an inductor device wiring architecture. The inductor device wiring architecture includes an inductor device. The inductor device is one of most important devices of the integrated circuit. The inductor device is connected to devices such as a resistor, a capacitor, a metal-oxide-semiconductor field-effect transistor (metal-oxide-semiconductor field-effect Transistor, MOSFET), a bipolar junction transistor (bipolar junction transistor, BJT), and a diode by using a special circuit structure to jointly form the integrated circuit. The integrated circuit has functions of control, calculation, memorization, and the like.

The integrated circuit may include one or more circuit modules. The circuit module may include but is not limited to one or more of a voltage control oscillator (Voltage Control Oscillator, VCO) module, a low-noise amplifier (Low-noise Amplifier, LNA) module, a frequency mixer (mixer) module, a trans-impedance amplifier (trans-impedance amplifier, TIA) module, a variable gain amplifier (variable gain amplifier, VGA) module, or a driver (driver) module. Inductor devices are widely used in these circuit modules.

<FIG> is a schematic structural diagram of an integrated circuit <NUM> according to an embodiment of this application.

In an embodiment, the integrated circuit <NUM> includes a substrate <NUM>, and a plurality of metal layers <NUM> and a plurality of insulation layers <NUM> that are formed on the substrate <NUM>. At least one insulation layer <NUM> is disposed between any two adjacent metal layers <NUM>. A silicon material, a glass material, or a ceramic material may be used for the substrate <NUM>. A material of the metal layer <NUM> may include one or more of copper, aluminum, silver, nickel, gold, titanium, indium, tungsten, or an alloy thereof. A material of the insulation layer <NUM> may include one or more of an electrical-insulating polymer, electrical-insulating ceramic, or a dielectric material.

The metal layer <NUM> is a patterned metal layer. The patterned metal layer may be molded in a plurality of manners. Examples are as follows.

In an implementation, a method for manufacturing the patterned metal layer includes: first, forming a groove on an insulation substrate based on a layout of the patterned metal layer; then, performing metal deposition (metal deposition) on the insulation substrate, so that a metallic material fills the groove and spills out of the groove; and next, removing, through chemical mechanical polishing (chemical-mechanical polishing, CMP), a metallic material spilled out of the groove. In this case, a metallic material remaining in the groove jointly forms the patterned metal layer.

In another implementation, a method for manufacturing the patterned metal layer includes: first, performing deposition to form a metal film; then, depositing photoresistance on the metal film; next, performing exposure, photolithography (photolithography), and etching (etching) processing by using a mask (mask) to pattern the metal film; and finally, performing planarization processing on a patterned metal film to form the patterned metal layer. The planarization processing is usually performed through chemical mechanical polishing.

Therefore, in the molding steps of the patterned metal layer, chemical mechanical polishing processing usually needs to be performed in the last step. However, a completion degree of the chemical mechanical polishing processing usually depends on a metal arrangement area of a to-be-processed metal layer and a metal arrangement area of a bottom metal layer of the to-be-processed metal layer. If the metal arrangement area is insufficient, a phenomenon of insufficient polishing is likely to occur, thereby resulting in a very low product yield of the patterned metal layer.

In an embodiment, the integrated circuit <NUM> includes an inductor device wiring architecture <NUM>. The inductor device wiring architecture <NUM> is a part of the integrated circuit <NUM>. The inductor device wiring architecture <NUM> includes some metal layers <NUM> and some insulation layers <NUM>. The inductor device wiring architecture <NUM> is molded synchronously with other parts of the integrated circuit <NUM> during manufacturing of the integrated circuit <NUM>. A specific quantity of layers of the inductor device wiring architecture <NUM> may be less than or equal to a quantity of layers of the integrated circuit <NUM>.

In an embodiment, the inductor device wiring architecture <NUM> includes an inductor device and a plurality of dummy metals (dummy metals) located under the inductor device. A plurality of metal layers may be laminated in the inductor device wiring architecture <NUM>. The metal layers of the inductor device wiring architecture <NUM> are some of the corresponding metal layers <NUM>, and the metal layers of the inductor device wiring architecture <NUM> are also patterned metal layers. The inductor device is arranged in a top metal layer of the inductor device wiring architecture <NUM>. The plurality of dummy metals under the inductor device are arranged in a plurality of metal layers under the inductor device. Each of the plurality of metal layers located under the inductor device corresponds to some of the plurality of dummy metals located under the inductor device. Arrangement areas of dummy metals corresponding to at least two of the plurality of metal layers under the inductor device progressively increase in a direction away from the inductor device. In this case, an arrangement area of dummy metals corresponding to a metal layer close to the inductor device is smaller, and an arrangement area of dummy metals corresponding to a metal layer away from the inductor device is larger. To be specific, during arrangement, the plurality of dummy metals located under the inductor device are kept away from (keep put from) the inductor device as far as possible, fewer dummy metals are in a region close to the inductor device, and more dummy metals are in a region away from the inductor device, thereby reducing adverse effects of the dummy metals on performance of the inductor device, or even eliminating impact on performance of the inductor device. In addition, each metal layer under the inductor device has a relatively sufficient metal arrangement area. This can meet a processing requirement of chemical mechanical polishing, thereby improving processing quality, and achieving a higher product yield of the inductor device wiring architecture <NUM> and the integrated circuit in which the inductor device wiring architecture <NUM> is used.

The following provides descriptions by using specific embodiments.

Refer to both <FIG> and <FIG>. <FIG> is a top view of the inductor device wiring architecture <NUM> shown in <FIG> according to a first embodiment, and <FIG> is a schematic cross-sectional view of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> that is cut along a line A-A. To illustrate the structure in <FIG> more clearly, a quantity of dummy metals <NUM> in each metal layer <NUM> in <FIG> is slightly reduced, but an overall arrangement rule remains unchanged.

The inductor device wiring architecture <NUM> includes an inductor device <NUM> and a plurality of dummy metals <NUM> located under the inductor device <NUM>. In this application, "under" is merely a direction shown with reference to the accompanying drawings. Therefore, a directional term is used for describing and understanding this application, but not to indicate or imply that an indicated apparatus or element shall have a specific direction or be constructed and operated in a specific direction, and therefore cannot be construed as a limitation on this application. For example, in the integrated circuit <NUM> in both <FIG> and <FIG>, the inductor device <NUM> may be arranged in a top metal layer <NUM> of the integrated circuit <NUM>. A space under the inductor device <NUM> is a space on a side, of the inductor device <NUM>, that faces the substrate <NUM> of the integrated circuit <NUM>. To be specific, a structure or a component located under the inductor device <NUM> is located between the inductor device <NUM> and the substrate <NUM>.

The space under the inductor device <NUM> includes a space under a wiring region of the inductor device <NUM> (as indicated by a dashed-line box on a periphery of the inductor device <NUM> in <FIG>). To be specific, the space under the inductor device <NUM> includes a space in which the wiring region of the inductor device <NUM> is projected along a vertical direction of a plane on which the inductor device <NUM> is located. The wiring region of the inductor device <NUM> covers the entire inductor device <NUM>. The wiring region of the inductor device <NUM> includes at least a region surrounded by an outer edge of an outermost wire of the inductor device <NUM>. In actual use, the "vertical direction" described above is not limited to a direction that has an included angle of exactly <NUM>° with the plane on which the inductor device <NUM> is located, but may be alternatively a direction close to <NUM>°. The plurality of dummy metals <NUM> under the inductor device <NUM> are located in the space under the inductor device <NUM>.

The inductor device wiring architecture <NUM> includes a plurality of laminated metal layers <NUM>. The metal layers <NUM> are some of the corresponding metal layers <NUM> of the integrated circuit <NUM>. The plurality of dummy metals <NUM> under the inductor device <NUM> are arranged in a plurality of metal layers <NUM> under the inductor device <NUM>. Each of the plurality of metal layers <NUM> under the inductor device <NUM> includes a plurality of corresponding dummy metals <NUM>, to increase a metal arrangement area of the metal layer <NUM>. The plurality of metal layers <NUM> under the inductor device <NUM> are a bottom structure of the inductor device <NUM>.

In this embodiment, the plurality of dummy metals <NUM> corresponding to the metal layer <NUM> under the inductor device <NUM> are spaced from each other. In another embodiment, two or more dummy metals <NUM> may be alternatively combined into a continuous dummy metal with a larger area. For example, a plurality of discontinuous dummy metals <NUM> in the embodiment shown in <FIG> may be combined into a continuous dummy metal.

Dummy metals <NUM> located in two adjacent metal layers <NUM> may be connected by using a conductive material in a via, or may not be connected.

In this embodiment, the inductor device <NUM> is located in a first metal layer <NUM>. Because the inductor device <NUM> is disposed in the first metal layer <NUM>, the first metal layer <NUM> can be processed to obtain a larger thickness, thereby reducing a resistance and increasing a quality factor Q. A second metal layer <NUM> to a fifth metal layer <NUM> are arranged under the inductor device <NUM>. The second metal layer <NUM> to the fifth metal layer <NUM> are a bottom structure of the inductor device <NUM>. The plurality of dummy metals <NUM> under the inductor device <NUM> are arranged in the second metal layer <NUM>, the third metal layer <NUM>, the fourth metal layer <NUM>, and the fifth metal layer <NUM>.

The inductor device wiring architecture <NUM> further includes a plurality of dummy metals <NUM> arranged in a metal layer <NUM> in which the inductor device <NUM> is located. For example, in this embodiment, the first metal layer <NUM> further includes a plurality of dummy metals <NUM>, and the plurality of dummy metals <NUM> are disposed around the inductor device <NUM> and are disposed away from the inductor device <NUM>. When the inductor device <NUM> surrounds a middle space with a larger area, a dummy metal <NUM> may also be arranged in the middle space.

Arrangement areas of dummy metals corresponding to at least two metal layers <NUM> located under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM> (for example, a Z direction shown in <FIG>). An arrangement area of dummy metals corresponding to a metal layer <NUM> is a total arrangement area of dummy metals <NUM> that are in the metal layer <NUM> and that are located under the inductor device <NUM>. A metal layer <NUM> with a larger arrangement area of dummy metals <NUM> has a larger metal arrangement proportion. In this case, among the plurality of dummy metals <NUM> located under the inductor device <NUM>, fewer dummy metals <NUM> are arranged in a region close to the inductor device <NUM>, and more dummy metals <NUM> are arranged in a region away from the inductor device <NUM>, thereby reducing adverse effects on performance of the inductor device <NUM>. In addition, because arrangement areas of the dummy metals <NUM> corresponding to the metal layers <NUM> under the inductor device <NUM> tend to progressively increase, arrangement areas of the metal layers <NUM> under the inductor device <NUM> roughly present a progressively increasing trend based on the arrangement areas of the dummy metals <NUM> (to be specific, the metal layers <NUM> roughly present a trend from a sparse arrangement to a dense arrangement from the top down). Therefore, each metal layer <NUM> of the inductor device wiring architecture <NUM> has a relatively sufficient metal arrangement area to meet a processing requirement of chemical mechanical polishing, so that the first metal layer <NUM> is well flattened, and the inductor device <NUM> has a few metal residues and high processing quality. Therefore, a short circuit risk of a circuit is reduced, and a product yield of the inductor device wiring architecture <NUM> and the integrated circuit <NUM> in which the inductor device wiring architecture <NUM> is used is higher. In short, in the inductor device wiring architecture <NUM>, a metal arrangement area of each metal layer <NUM> can be increased while adverse effects of the dummy metals <NUM> on inductor device performance of the inductor device <NUM> are reduced. This increases a product yield.

The plurality of dummy metals <NUM> located under the inductor device <NUM> are arranged in a stepped shape. To be specific, in the plurality of metal layers <NUM> located under the inductor device <NUM>, a dummy metal <NUM> corresponding to a lower metal layer <NUM> extends out relative to a dummy metal <NUM> corresponding to an upper metal layer <NUM> to form a stepped shape. For example, in <FIG>, a dummy metal <NUM> corresponding to the third metal layer <NUM> extends out relative to a dummy metal <NUM> corresponding to the second metal layer <NUM> to form a stepped shape.

In <FIG>, dummy metals <NUM> located in different metal layers <NUM> in the inductor device wiring architecture <NUM> are filled with different patterns for differentiation. The inductor device <NUM> and the dummy metal <NUM> in the first metal layer <NUM> are filled with a black pattern, the dummy metal <NUM> in the second metal layer <NUM> is filled with slashes, and the dummy metal <NUM> in the third metal layer <NUM> is not filled with a pattern (that is, has a white background color). In this embodiment, the dummy metals <NUM> in the plurality of metal layers <NUM> are arranged in alignment. In this case, a dummy metal <NUM> in a bottom structure is blocked by a dummy metal <NUM> in a top structure. For example, some dummy metals <NUM> in the second metal layer <NUM> are blocked by dummy metals <NUM> in the first metal layer <NUM>. Some dummy metals <NUM> in the second metal layer <NUM> extend out relative to dummy metals <NUM> in the first metal layer <NUM>, and the dummy metals <NUM> that relatively extend out are exposed.

In this embodiment, because the plurality of dummy metals <NUM> located under the inductor device <NUM> are arranged in the stepped shape, the plurality of dummy metals <NUM> can effectively improve metal arrangement under the inductor device <NUM>, so that higher manufacturing precision of the inductor device <NUM> is high during chemical mechanical polishing, and a product yield of the inductor device wiring architecture <NUM> and the integrated circuit <NUM> in which the inductor device wiring architecture <NUM> is used is higher. In addition, the plurality of dummy metals <NUM> located under the inductor device <NUM> can be arranged not in a region close to the inductor device <NUM>, but arranged in a region away from the inductor device <NUM> as far as possible, thereby reducing adverse effects of the dummy metals <NUM> on inductor device performance of the inductor device <NUM>, and improving performance of the inductor device <NUM>.

Some dummy metals <NUM> arranged in the metal layer <NUM> in which the inductor device <NUM> is located and the dummy metals <NUM> arranged under the inductor device <NUM> may also be arranged in a stepped shape. For example, in <FIG>, a dummy metal <NUM> corresponding to the second metal layer <NUM> extends out relative to a dummy metal <NUM> corresponding to the first metal layer <NUM> to form a stepped shape.

As shown in <FIG>, some of the plurality of dummy metals <NUM> in the first metal layer <NUM> are disposed around the inductor device <NUM>, and some of the plurality of dummy metals <NUM> in the first metal layer <NUM> are arranged in the middle space surrounded by the inductor device <NUM>. A spacing S1 is formed between the inductor device <NUM> and a dummy metal <NUM> closest to the inductor device <NUM> among the dummy metals <NUM> located in the middle space of the inductor device <NUM>. A spacing S2 is formed between two adjacent dummy metals <NUM> located in the middle space of the inductor device <NUM>. S1 is greater than S2. In this case, the dummy metals <NUM> in the first metal layer <NUM> have smaller impact on performance of the inductor device <NUM>, and the inductor device <NUM> has higher inductance performance. Similarly, a spacing between the inductor device <NUM> and some dummy metals <NUM> located on a periphery of the inductor device <NUM> is greater than a spacing between two adjacent dummy metals <NUM> located on the periphery of the inductor device <NUM>.

In this embodiment, the plurality of dummy metals <NUM> in the first metal layer <NUM> may be arranged at equal spacings or unequal spacings. This is not strictly limited in this application. In this application, a "spacing" between two adjacent dummy metals <NUM> is a spacing between two dummy metals <NUM> located on a same side of the inductor device <NUM>.

In this embodiment, the dummy metals <NUM> in the first metal layer <NUM> are arranged roughly in an array (no dummy metal <NUM> is arranged in some regions of the array), and spacings between every two adjacent dummy metals <NUM> are roughly the same. In another embodiment, the dummy metals <NUM> in the first metal layer <NUM> may be alternatively arranged in another manner, for example, arranged roughly in a diffused annular shape or randomly arranged in a scattered manner.

A plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> are kept away from the inductor device <NUM> as far as possible. For example, a dummy metal <NUM> in the second metal layer <NUM> is arranged not directly under a wire of the inductor device <NUM>, to increase a metal arrangement area of the second metal layer <NUM> as much as possible, so that a product yield of the inductor device wiring architecture <NUM> is increased, and there is less impact on performance of the inductor device <NUM>. In the second metal layer <NUM>, a spacing S4 between two dummy metals <NUM> close to a space directly under a wire of the inductor device <NUM> is greater than or equal to a gap S5 between two adjacent dummy metals <NUM>.

In this embodiment, some dummy metals <NUM> corresponding to the second metal layer <NUM> extend out relative to dummy metals <NUM> in the first metal layer <NUM>, and a plurality of dummy metals <NUM> that are in the first metal layer <NUM> and the second metal layer <NUM> and that are close to the inductor device <NUM> are arranged roughly in a stepped shape.

In this embodiment, for designs of a structure and a size of the dummy metal <NUM> in the second metal layer <NUM>, refer to the dummy metal <NUM> in the first metal layer <NUM>. For example, S5 is equal to S2. In another embodiment, designs of a structure and a size of the dummy metal <NUM> in the second metal layer <NUM> may be alternatively different from those of the dummy metal in the first metal layer <NUM>.

S1 may range from <NUM> micron (µm) to <NUM> microns. S1 may be set based on a range of an electromagnetic field generated by the inductor device <NUM>. S2 may range from <NUM> micron to <NUM> microns. A width of the wire of the inductor device <NUM> is W1. W1 may range from <NUM> micron to <NUM> microns. A width of the dummy metal <NUM> is W2. W2 may range from <NUM> micron to <NUM> microns. In a thickness direction (namely, the Z direction) of the inductor device wiring architecture <NUM>, a thickness of the dummy metal <NUM> is T1. T1 may range from <NUM> micron to <NUM> microns. A copper or aluminum material may be used for the dummy metal <NUM>. A copper or aluminum material may be used for the inductor device <NUM>. A material of the inductor device <NUM> is the same as a material of the dummy metal <NUM> in the first metal layer <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> is larger than an arrangement area of the dummy metals <NUM> corresponding to the second metal layer <NUM>. Some dummy metals <NUM> corresponding to the third metal layer <NUM> extend out relative to dummy metals <NUM> corresponding to the second metal layer <NUM>. In this embodiment, a plurality of dummy metals <NUM> in the first metal layer <NUM>, the second metal layer <NUM>, and the third metal layer <NUM> are arranged in a stepped shape.

A dummy metal <NUM> in the third metal layer <NUM> is located directly under a wire of the inductor device <NUM>, and a spacing between the dummy metal <NUM> and the wire of the inductor device <NUM> is S3. S3 may range from <NUM> micron to <NUM> microns. S3 may be designed based on a range of an electromagnetic field of the inductor device <NUM>.

For designs of a structure and a size of the dummy metal <NUM> in the third metal layer <NUM>, refer to the dummy metal <NUM> in the first metal layer <NUM>. In another embodiment, designs of a structure and a size of the dummy metal <NUM> in the third metal layer <NUM> may be alternatively different from those of the dummy metal in the first metal layer <NUM>.

In this embodiment, the inductor device wiring architecture <NUM> further includes a plurality of dielectric layers <NUM>. The dielectric layers <NUM> are a part of the corresponding insulation layers <NUM>. A dielectric layer <NUM> is disposed between every two adjacent metal layers <NUM>. When a gap is formed between dummy metals <NUM> in a metal layer <NUM>, the gap is filled with an insulation material to form an insulation part. The insulation part is connected to the dielectric layer <NUM>.

The dielectric layers <NUM> in the inductor device wiring architecture <NUM> may have a same thickness. For example, as shown in <FIG>, the thickness of the dielectric layer <NUM> is T2. T2 may range from <NUM> micron to <NUM> microns.

As shown in <FIG> and <FIG>, in this embodiment, the plurality of dummy metals <NUM> under the inductor device <NUM> are mainly arranged in a stepped shape. In another embodiment, when a processing requirement and a performance requirement are met, the plurality of dummy metals <NUM> under the inductor device <NUM> may be alternatively arranged in another manner.

As shown in <FIG> and <FIG>, in this embodiment, the plurality of dummy metals <NUM> under the inductor device <NUM> have a roughly same shape and size. In another embodiment, the plurality of dummy metals <NUM> under the inductor device <NUM> may alternatively have different shapes and different sizes. Similarly, a plurality of dummy metals <NUM> disposed in a same layer as that of the inductor device <NUM> and the plurality of dummy metals <NUM> under the inductor device <NUM> may have a roughly same shape and size, or may have different shapes and different sizes.

As shown in <FIG>, in this embodiment, the plurality of dummy metals <NUM> under the inductor device <NUM> are in a square shape. In another embodiment, the plurality of dummy metals <NUM> under the inductor device <NUM> may be alternatively in a strip shape, a triangular shape, a circular shape, an elliptical shape, a polygonal shape, a special shape, or the like. A shape and a size of the dummy metal <NUM> are not strictly limited in this application.

In an embodiment, the inductor device wiring architecture <NUM> further includes a polycrystalline silicon (polycrystalline silicon) layer (not shown in the figure) located under the plurality of metal layers <NUM>. The polycrystalline silicon layer includes a plurality of polycrystalline silicons that serve as gates of PN junctions (a P-type semiconductor and an N-type semiconductor are fabricated on one semiconductor substrate, and a space charge region referred to as a PN junction (PN junction), is formed at a junction interface of the semiconductors) of the integrated circuit <NUM>. An arrangement of the plurality of polycrystalline silicons also needs to meet a processing requirement of chemical mechanical polishing to flatten the plurality of metal layers <NUM>. For an arrangement rule of the plurality of polycrystalline silicons, refer to the foregoing arrangement rule of the plurality of dummy metals <NUM>. For example, when the polycrystalline silicon layer is closer to the inductor device <NUM>, the polycrystalline silicons in the polycrystalline silicon layer tend to be arranged away from the inductor device <NUM>. Specifically, an arrangement area of the polycrystalline silicons in the polycrystalline silicon layer and the arrangement area of the dummy metals <NUM> corresponding to the metal layers <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>. The plurality of polycrystalline silicons and the plurality of dummy metals <NUM> located under the inductor device <NUM> may be jointly arranged in a stepped shape.

Further, in this application, when the plurality of dummy metals <NUM> under the inductor device <NUM> in the inductor device wiring architecture <NUM> meet an arrangement rule of transitioning from a sparse arrangement to a dense arrangement in a direction away from the inductor device <NUM>, there may be a plurality of arrangement manners. Examples are as follows.

In an arrangement manner, under the inductor device <NUM>, each metal layer <NUM> corresponds to a plurality of dummy metals <NUM>, and dummy metals <NUM> corresponding to each metal layer <NUM> are arranged in a staggered manner with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. In other words, a dummy metal <NUM> under the inductor device <NUM> and a dummy metal <NUM> located above or under the dummy metal <NUM> have a location relationship of being roughly staggered with each other. In this case, the plurality of dummy metals <NUM> located under the inductor device <NUM> are arranged more regularly, thereby helping reduce design costs and production costs.

In another arrangement manner, under the inductor device <NUM>, each metal layer <NUM> corresponds to a plurality of dummy metals <NUM>, and dummy metals <NUM> corresponding to each metal layer <NUM> are arranged in alignment with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. In other words, a dummy metal <NUM> under the inductor device <NUM> and a dummy metal <NUM> above or under the dummy metal <NUM> have a location relationship of roughly facing each other. In this case, the plurality of dummy metals <NUM> located under the inductor device <NUM> are arranged more regularly, thereby helping reduce design costs and production costs.

In still another arrangement manner, under the inductor device <NUM>, each metal layer <NUM> corresponds to a plurality of dummy metals <NUM>, dummy metals <NUM> corresponding to one or more metal layers <NUM> are arranged in a staggered manner with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>, and dummy metals <NUM> corresponding to one or more metal layers <NUM> are arranged in alignment with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. In this case, under the inductor device <NUM> in the inductor device wiring architecture <NUM>, some dummy metals <NUM> are arranged in alignment, and some dummy metals <NUM> are arranged in a staggered manner. This enriches arrangement manners of the dummy metals <NUM>, and makes arrangement manners of the inductor device wiring architecture <NUM> more diversified.

In the first embodiment shown in <FIG> and <FIG>, under the inductor device <NUM>, dummy metals <NUM> corresponding to each metal layer <NUM> are arranged in alignment with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. For example, dummy metals <NUM> corresponding to the second metal layer <NUM> to the fifth metal layer <NUM> are arranged in alignment. In an embodiment, sizes of the plurality of dummy metals <NUM> under the inductor device <NUM> are the same, and spacings between every two adjacent dummy metals <NUM> corresponding to each metal layer <NUM> are the same, for example, S5 = S2.

Refer to both <FIG> and <FIG>. <FIG> is a top view of the inductor device wiring architecture <NUM> shown in <FIG> according to a second embodiment, and <FIG> is a schematic cross-sectional view of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> that is cut along a line B-B. To illustrate the structure in <FIG> more clearly, a quantity of dummy metals <NUM> in each metal layer <NUM> in <FIG> is slightly reduced, but an overall arrangement rule remains unchanged. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the second embodiment, under the inductor device <NUM>, dummy metals <NUM> corresponding to each metal layer <NUM> are arranged in a staggered manner with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. In this case, a layer structure under the inductor device <NUM> has a more uniform metal arrangement area, thereby helping improve processing precision of the inductor device <NUM>, and achieving a higher product yield of the inductor device wiring architecture <NUM>.

In this embodiment, the inductor device wiring architecture <NUM> includes a first metal layer <NUM>, a second metal layer <NUM>, a third metal layer <NUM>, a fourth metal layer <NUM>, and a fifth metal layer <NUM>. Dummy metals <NUM> corresponding to the second metal layer <NUM>, the third metal layer <NUM>, the fourth metal layer <NUM>, and the fifth metal layer <NUM> under the inductor device <NUM> are arranged in a staggered manner. Some dummy metals <NUM> in the first metal layer <NUM> in which the inductor device <NUM> is located are arranged in a staggered manner with the dummy metals <NUM> corresponding to the metal layers (<NUM>, <NUM>, <NUM>, and <NUM>) under the inductor device <NUM>.

<FIG> is a schematic diagram of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> according to a third embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the third embodiment, the inductor device wiring architecture <NUM> includes a first metal layer <NUM> in which the inductor device <NUM> is located and a plurality of metal layers (a second metal layer <NUM> to a ninth metal layer <NUM>) located under the inductor device <NUM>. Arrangement areas of dummy metals <NUM> corresponding to the second metal layer <NUM> to the sixth metal layer <NUM> progressively increase in a Z direction away from the inductor device <NUM>.

Under the inductor device <NUM>, dummy metals <NUM> corresponding to one or more metal layers <NUM> are arranged in a staggered manner with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>, and dummy metals <NUM> corresponding to one or more metal layers <NUM> are arranged in alignment with dummy metals <NUM> corresponding to an adjacent metal layer <NUM>. For example, dummy metals <NUM> corresponding to the second metal layer <NUM>, dummy metals <NUM> corresponding to the third metal layer <NUM>, and dummy metals <NUM> corresponding to the fourth metal layer <NUM> are arranged in alignment. In the fourth metal layer <NUM>, the fifth metal layer <NUM>, the sixth metal layer <NUM>, the seventh metal layer <NUM>, the eighth metal layer <NUM>, and the ninth metal layer <NUM>, dummy metals <NUM> corresponding to two adjacent metal layers <NUM> are arranged in a staggered manner. In this case, the plurality of dummy metals <NUM> located under the inductor device <NUM> in the inductor device wiring architecture <NUM> are arranged in a more diversified manner.

Some dummy metals <NUM> in the first metal layer <NUM> are arranged in a staggered manner with dummy metals <NUM> corresponding to the second metal layer <NUM>. In another embodiment, some dummy metals <NUM> in the first metal layer <NUM> are arranged in alignment with dummy metals <NUM> corresponding to the second metal layer <NUM>. An arrangement manner of the dummy metals <NUM> in the plurality of metal layers <NUM> in the inductor device wiring architecture <NUM> is not strictly limited in this application.

Further, in this application, there are a plurality of implementations of a relationship between arrangement areas of the dummy metals <NUM> corresponding to the plurality of metal layers <NUM> under the inductor device <NUM>. Examples are as follows.

In an implementation, in the plurality of metal layers <NUM> under the inductor device <NUM>, arrangement areas of dummy metals <NUM> corresponding to at least three adjacent metal layers <NUM> progressively increase in the Z direction away from the inductor device <NUM>. In this case, the plurality of dummy metals <NUM> under the inductor device <NUM> present a continuous stepped shape. This helps further improve processing quality of the inductor device wiring architecture <NUM>, and the plurality of dummy metals <NUM> under the inductor device <NUM> have less impact on performance of the inductor device <NUM>.

In another implementation, an arrangement area of dummy metals <NUM> corresponding to an ith metal layer under the inductor device <NUM> is the same as an arrangement area of dummy metals <NUM> corresponding to an (i - <NUM>)th metal layer. The ith metal layer is located on a side, of the (i - <NUM>)th metal layer, that is away from the inductor device <NUM>. In other words, the ith metal layer is located under the (i - <NUM>)th metal layer. i is an integer greater than or equal to <NUM>.

In this implementation, when the inductor device wiring architecture <NUM> roughly meets an arrangement rule of transitioning from a sparse arrangement to a dense arrangement, two metal layers <NUM> corresponding to dummy metals <NUM> with a same arrangement area are included under the inductor device <NUM>, so that arrangement flexibility of the plurality of dummy metals <NUM> under the inductor device <NUM> in the inductor device wiring architecture <NUM> is higher, and arrangement manners are more diversified. The inductor device wiring architecture <NUM> may include one group of two metal layers <NUM> corresponding to dummy metals <NUM> with a same arrangement area, or may include more than two (including two) groups of two metal layers <NUM> corresponding to dummy metals <NUM> with a same arrangement area. Alternatively, the inductor device wiring architecture <NUM> may include more than three (including three) metal layers <NUM> corresponding to dummy metals <NUM> with a same arrangement area.

A plurality of dummy metals <NUM> corresponding to the ith metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is an ith spacing. A plurality of dummy metals <NUM> corresponding to the (i - <NUM>)th metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is an (i - <NUM>)th spacing. The (i - <NUM>)th spacing is less than or equal to the ith spacing. When the (i - <NUM>)th spacing is less than the ith spacing, although arrangement areas of the dummy metals <NUM> corresponding to the ith metal layer do not progressively increase, the plurality of dummy metals <NUM> in the ith metal layer have a larger arrangement range and a more uniform arrangement. This effectively improves processing quality of the metal layer <NUM>, and achieves a higher product yield of the inductor device wiring architecture <NUM>. Certainly, in another embodiment, an arrangement manner and an arrangement spacing of the plurality of dummy metals <NUM> corresponding to the ith metal layer and the (i - <NUM>)th metal layer may be alternatively different from those in the foregoing solution, and may be set as required.

In still another implementation, an arrangement area of dummy metals <NUM> corresponding to a jth metal layer under the inductor device <NUM> is smaller than an arrangement area of dummy metals <NUM> corresponding to a (j - <NUM>)th metal layer. The jth metal layer is located on a side, of the (j - <NUM>)th metal layer, that is away from the inductor device <NUM>. In other words, the jth metal layer is located under the (j - <NUM>)th metal layer. j is an integer greater than or equal to <NUM>.

In this implementation, when the inductor device wiring architecture <NUM> roughly meets an arrangement rule of transitioning from a sparse arrangement to a dense arrangement, two metal layers <NUM> corresponding to dummy metals <NUM> are included under the inductor device <NUM>, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer, so that arrangement flexibility of the plurality of dummy metals <NUM> under the inductor device <NUM> in the inductor device wiring architecture <NUM> is higher, and arrangement manners are more diversified. The inductor device wiring architecture <NUM> may include one group of two metal layers <NUM> corresponding to dummy metals <NUM>, or may include more than two (including two) groups of two metal layers <NUM> corresponding to dummy metals <NUM>, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer. Alternatively, the inductor device wiring architecture <NUM> may include more than three (including three) metal layers <NUM> corresponding to dummy metals <NUM>, where an arrangement area of an upper metal layer is smaller than an arrangement area of a lower metal layer.

A plurality of dummy metals <NUM> corresponding to the jth metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a jth spacing. A plurality of dummy metals <NUM> corresponding to the (j - <NUM>)th metal layer are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a (j - <NUM>)th spacing. The (j - <NUM>)th spacing is less than or equal to the jth spacing. When the (j - <NUM>)th spacing is less than the jth spacing, the plurality of dummy metals <NUM> corresponding to the jth metal layer that corresponds to dummy metals <NUM> with a smaller arrangement area have a larger arrangement range and a more uniform arrangement. This effectively improves processing quality of the metal layer <NUM>, and achieves a higher product yield of the inductor device wiring architecture <NUM>. Certainly, in another embodiment, an arrangement manner and an arrangement spacing of the plurality of dummy metals <NUM> corresponding to the jth metal layer and the (j - <NUM>)th metal layer may be alternatively different from those in the foregoing solution, and may be set as required.

In other words, when arrangement areas of dummy metals <NUM> corresponding to at least two of the plurality of metal layers <NUM> under the inductor device <NUM> progressively increase in the direction away from the inductor device <NUM>, an arrangement area of dummy metals <NUM> corresponding to one or more metal layers <NUM> and an arrangement area of dummy metals <NUM> corresponding to an adjacent metal layer <NUM> may be the same or progressively decrease (in the Z direction away from the inductor device <NUM>). In this case, a higher product yield can also be achieved for the inductor device wiring architecture <NUM>.

The foregoing three implementations may be used independently or in combination.

Refer to <FIG>. In the first embodiment, the inductor device <NUM> is arranged in the first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to the second metal layer <NUM> and the third metal layer <NUM> under the inductor device <NUM> progressively increase in the direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>). An arrangement area of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is the same as the arrangement area of the dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>). In other words, an arrangement area of dummy metals <NUM> corresponding to an ith metal layer under the inductor device <NUM> is the same as an arrangement area of dummy metals <NUM> corresponding to an (i - <NUM>)th metal layer. The ith metal layer is located on a side, of the (i - <NUM>)th metal layer, that is away from the inductor device <NUM>. i is an integer greater than or equal to <NUM>.

A plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a third spacing. A plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a second spacing. The second spacing is equal to the third spacing. A plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a fourth spacing. The fourth spacing is equal to the third spacing.

The arrangement area of the dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>), the arrangement area of the dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>), and the arrangement area of the dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) are the same. In other words, more than three (including three) metal layers <NUM> under the inductor device <NUM> correspond to dummy metals <NUM> with a same arrangement area.

Refer to <FIG>. In the second embodiment, the inductor device <NUM> is arranged in the first metal layer <NUM>. The second metal layer <NUM> is disposed adjacent to the third metal layer <NUM> and the fourth metal layer <NUM> under the inductor device <NUM>. In addition, arrangement areas of dummy metals <NUM> corresponding to the second metal layer <NUM>, the third metal layer <NUM>, and the fourth metal layer <NUM> progressively increase in the Z direction away from the inductor device <NUM>. In other words, in the plurality of metal layers <NUM> under the inductor device <NUM>, arrangement areas of dummy metals <NUM> corresponding to at least three adjacent metal layers <NUM> progressively increase in the Z direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>). A plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a fourth spacing. A plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a third spacing. The third spacing is equal to the fourth spacing.

Refer to <FIG>. In the third embodiment, the inductor device <NUM> is arranged in the first metal layer <NUM>. The second metal layer <NUM> is disposed adjacent to the third metal layer <NUM>, the fourth metal layer <NUM>, the fifth metal layer <NUM>, and the sixth metal layer <NUM> under the inductor device <NUM>. In addition, arrangement areas of dummy metals <NUM> corresponding to the second metal layer <NUM> to the sixth metal layer <NUM> progressively increase in the direction away from the inductor device <NUM>.

Arrangement areas of dummy metals <NUM> corresponding to the sixth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), the seventh metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), the eighth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), and the ninth metal layer <NUM> (that is, an <NUM>th metal layer under the inductor device <NUM>) are the same. In this case, more than three (including three) metal layers <NUM> under the inductor device <NUM> correspond to dummy metals <NUM> with a same arrangement area.

In the sixth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>), the seventh metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>), the eighth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>), and the ninth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>), each metal layer <NUM> corresponds to a plurality of dummy metals <NUM>, and an arrangement spacing between two adjacent dummy metals <NUM> remains the same in different metal layers <NUM>. In another embodiment, an arrangement spacing between two adjacent dummy metals <NUM> may alternatively vary in different metal layers <NUM>.

<FIG> is a schematic structural diagram of the inductor device wiring architecture <NUM> shown in <FIG> according to a fourth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the fourth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a third metal layer <NUM> and a fourth metal layer <NUM> under the inductor device <NUM> progressively increase in a Z direction away from the inductor device <NUM>.

A second metal layer <NUM> and the fourth metal layer <NUM> are spaced from each other. Arrangement areas of dummy metals <NUM> corresponding to the second metal layer <NUM> and the fourth metal layer <NUM> progressively increase in the Z direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>). An arrangement area of dummy metals <NUM> corresponding to a fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>). In this case, two or more groups of two metal layers <NUM> corresponding to dummy metals <NUM> with a same arrangement area may be included under the inductor device <NUM>.

An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) is a second spacing S7. An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, the <NUM>st metal layer under the inductor device <NUM>) is a first spacing S6. The first spacing S6 is equal to the second spacing S7.

An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) is a fourth spacing. An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) is a third spacing. The third spacing is equal to the fourth spacing. The third spacing may be equal to or not equal to the second spacing.

<FIG> is a schematic structural diagram of the inductor device wiring architecture <NUM> shown in <FIG> according to a fifth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the fifth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a third metal layer <NUM> and a fourth metal layer <NUM> under the inductor device <NUM> progressively increase in a Z direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>). An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) is a second spacing S7. An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, the <NUM>st metal layer under the inductor device <NUM>) is a first spacing S6. The first spacing S6 is less than the second spacing S7.

An arrangement area of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>). A plurality of dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a fourth spacing. A plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a third spacing. The third spacing is equal to the fourth spacing.

<FIG> is a schematic diagram of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> according to a sixth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the sixth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a second metal layer <NUM> and a third metal layer <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a fourth metal layer <NUM>, a fifth metal layer <NUM>, and a sixth metal layer <NUM> progressively increase in the direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>). Arrangement areas of dummy metals <NUM> corresponding to the sixth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), a seventh metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), an eighth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), and a ninth metal layer <NUM> (that is, an <NUM>th metal layer under the inductor device <NUM>) are the same.

<FIG> is a schematic structural diagram of the inductor device wiring architecture <NUM> shown in <FIG> according to a seventh embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the seventh embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a third metal layer <NUM> and a fourth metal layer <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to a second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>). An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) is a second spacing S7. An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, the <NUM>st metal layer under the inductor device <NUM>) is a first spacing S6. The first spacing S6 is equal to the second spacing S7.

An arrangement area of dummy metals <NUM> corresponding to a fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>). An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) is equal to an arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>).

<FIG> is a schematic structural diagram of the inductor device wiring architecture <NUM> shown in <FIG> according to an eighth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the eighth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a third metal layer <NUM> and a fourth metal layer <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to a second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>).

An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) is a second spacing S7. An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, the <NUM>st metal layer under the inductor device <NUM>) is a first spacing S6. The first spacing S6 is less than the second spacing S7.

An arrangement area of dummy metals <NUM> corresponding to a fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>).

An arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) is equal to an arrangement spacing between two adjacent dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>).

<FIG> is a schematic diagram of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> according to a ninth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the ninth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a third metal layer <NUM> and a fourth metal layer <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a fifth metal layer <NUM> and a sixth metal layer <NUM> progressively increase in the direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to a second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>). An arrangement area of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>).

A plurality of dummy metals <NUM> in a plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a second spacing. A plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a first spacing. The first spacing is equal to the second spacing.

A plurality of dummy metals <NUM> corresponding to the fifth metal layer <NUM> (that is, the <NUM>th metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a fourth spacing. A plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a third spacing. The third spacing is equal to the fourth spacing.

Arrangement areas of dummy metals <NUM> corresponding to the sixth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), a seventh metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), an eighth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), and a ninth metal layer <NUM> (that is, an <NUM>th metal layer under the inductor device <NUM>) are the same.

<FIG> is a schematic diagram of a partial structure of the inductor device wiring architecture <NUM> shown in <FIG> according to a tenth embodiment. Most technical content in this embodiment is the same as that in the foregoing embodiments, and is not described in detail again.

In the tenth embodiment, the inductor device <NUM> is arranged in a first metal layer <NUM>. Arrangement areas of dummy metals <NUM> corresponding to a second metal layer <NUM> and a third metal layer <NUM> under the inductor device <NUM> progressively increase in a direction away from the inductor device <NUM>. A fourth metal layer <NUM> is disposed adjacent to a fifth metal layer <NUM>, and a sixth metal layer <NUM>. In addition, arrangement areas of dummy metals <NUM> corresponding to the fourth metal layer <NUM>, the fifth metal layer <NUM>, and the sixth metal layer <NUM> progressively increase in the direction away from the inductor device <NUM>.

An arrangement area of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, a <NUM>st metal layer under the inductor device <NUM>) is the same as an arrangement area of dummy metals <NUM> corresponding to the first metal layer <NUM> (that is, a metal layer in which the inductor device <NUM> is located). An arrangement spacing between two adjacent dummy metals in a plurality of dummy metals <NUM> corresponding to the second metal layer <NUM> (that is, the <NUM>st metal layer under the inductor device <NUM>) is greater than an arrangement spacing between two adjacent dummy metals in a plurality of dummy metals <NUM> corresponding to the first metal layer <NUM> (that is, the metal layer in which the inductor device <NUM> is located).

An arrangement area of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, a <NUM>rd metal layer under the inductor device <NUM>) is smaller than an arrangement area of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, a <NUM>nd metal layer under the inductor device <NUM>). A plurality of dummy metals <NUM> corresponding to the fourth metal layer <NUM> (that is, the <NUM>rd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a third spacing. A plurality of dummy metals <NUM> corresponding to the third metal layer <NUM> (that is, the <NUM>nd metal layer under the inductor device <NUM>) are arranged at equal spacings, and an arrangement spacing between two adjacent dummy metals <NUM> is a second spacing. The second spacing is less than the third spacing.

Arrangement areas of dummy metals <NUM> corresponding to the sixth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), a seventh metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), an eighth metal layer <NUM> (that is, a <NUM>th metal layer under the inductor device <NUM>), and a ninth metal layer <NUM> (that is, an <NUM>th metal layer under the inductor device <NUM>) are the same. In this application, the first embodiment to the tenth embodiment schematically describe an arrangement relationship of the plurality of dummy metals <NUM> under the inductor device <NUM>, but do not strictly limit the arrangement relationship of the plurality of dummy metals <NUM> under the inductor device <NUM> (for example, a relationship between arrangement spacings in a single metal layer <NUM> and an arrangement spacing between a plurality of metal layers <NUM>). For example, in the first embodiment to the tenth embodiment, the plurality of dummy metals <NUM> in the metal layers <NUM> under the inductor device <NUM> may be alternatively arranged randomly or according to another arrangement rule.

Further, in this application, the inductor device <NUM> may have a plurality of implementation structures. For example, the inductor device <NUM> may be an inductor with two ports or a transformer (transformer) with four ports. The inductor device <NUM> may be arranged in one metal layer; or the inductor device <NUM> may include an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers.

In an implementation structure, as shown in <FIG>, the inductor device <NUM> in the inductor device wiring architecture <NUM> is an inductor with two ports.

<FIG> shows an implementation structure of the inductor device <NUM> in the inductor device wiring architecture <NUM> shown in <FIG>. <FIG> is a top view of a metal layer in which the inductor device <NUM> of the inductor device wiring architecture <NUM> is located.

In another implementation structure, the inductor device <NUM> in the inductor device wiring architecture <NUM> is a helical inductor with two ports. The helical inductor is arranged in one metal layer. <NUM>° is formed between the two ports <NUM> of the helical inductor. A main structure of the helical inductor is arranged in one metal layer. The metal layer in which the inductor device <NUM> is located further includes a plurality of dummy metals <NUM>. Some dummy metals <NUM> are arranged around a periphery of the helical inductor. Some dummy metals <NUM> are arranged in a middle space surrounded by the helical inductor. In <FIG>, a wiring region of the inductor device <NUM> is schematically indicated by a dashed-line box on a periphery of the inductor device <NUM>.

<FIG> shows another implementation structure of the inductor device <NUM> in the inductor device wiring architecture <NUM> shown in <FIG>. <FIG> is a top view of a metal layer in which the inductor device <NUM> of the inductor device wiring architecture <NUM> is located.

In still another implementation structure, the inductor device <NUM> in the inductor device wiring architecture <NUM> is a helical inductor with two ports. <NUM>° is formed between the two ports <NUM> of the helical inductor. A main structure of the helical inductor is arranged in one metal layer. The metal layer in which the inductor device <NUM> is located further includes a plurality of dummy metals <NUM>. Some dummy metals <NUM> are arranged around a periphery of the helical inductor. Some dummy metals <NUM> are arranged in a middle space surrounded by the helical inductor. In <FIG>, a wiring region of the inductor device <NUM> is schematically indicated by a dashed-line box on a periphery of the inductor device <NUM>.

<FIG> shows still another implementation structure of the inductor device <NUM> in the inductor device wiring architecture <NUM> shown in <FIG>. <FIG> is a top view of a metal layer in which the inductor device <NUM> of the inductor device wiring architecture <NUM> is located.

In still another implementation structure, the inductor device <NUM> in the inductor device wiring architecture <NUM> is a differential inductor with two ports. A main structure of the differential inductor is arranged in one metal layer. The metal layer in which the inductor device <NUM> is located further includes a plurality of dummy metals <NUM>. Some dummy metals <NUM> are arranged around a periphery of the differential inductor. Some dummy metals <NUM> are arranged in a middle space surrounded by the differential inductor. In <FIG>, a wiring region of the inductor device <NUM> is schematically indicated by a dashed-line box on a periphery of the inductor device <NUM>.

In still another implementation structure, the inductor device <NUM> in the inductor device wiring architecture <NUM> is a square inductor with two ports. A main structure of the square inductor is arranged in one metal layer. The metal layer in which the inductor device <NUM> is located further includes a plurality of dummy metals <NUM>. Some dummy metals <NUM> are arranged around a periphery of the square inductor. Some dummy metals <NUM> are arranged in a middle space surrounded by the square inductor. In <FIG>, a wiring region of the inductor device <NUM> is schematically indicated by a dashed-line box on a periphery of the inductor device <NUM>.

In this implementation structure, the square inductor is a differential inductor. In another implementation structure, the square inductor may be alternatively another inductor. In another implementation structure, the inductor may alternatively be an inductor in another shape, for example, a circular shape or a polygonal shape. This is not strictly limited in this application.

In still another implementation structure, the inductor device <NUM> in the inductor device wiring architecture <NUM> is a transformer with four ports. The transformer includes two coils that are intertwined. Each coil has two ports <NUM>. A main structure of the transformer is arranged in one metal layer. The metal layer in which the inductor device <NUM> is located further includes a plurality of dummy metals <NUM>. Some dummy metals <NUM> are arranged around a periphery of the transformer. Some dummy metals <NUM> are arranged in a middle space surrounded by the transformer. In <FIG>, a wiring region of the inductor device <NUM> is schematically indicated by a dashed-line box on a periphery of the inductor device <NUM>.

<FIG> shows still another implementation structure of the inductor device <NUM> in the inductor device wiring architecture <NUM> shown in <FIG>. <FIG> is a schematic three-dimensional structural diagram of the inductor device <NUM>.

In still another implementation structure, the inductor device <NUM> may include an upper inductor <NUM> and a lower inductor <NUM>. The upper inductor <NUM> and the lower inductor <NUM> are arranged in two adjacent metal layers. The upper inductor <NUM> and the lower inductor <NUM> may be connected by using a conductive material <NUM> in a via, so that the inductor device <NUM> serves as a multilayer metal serial (serial) inductor.

In this implementation structure, the wiring region of the inductor device <NUM> includes a region surrounded by an outer edge of an outermost wire of the upper inductor <NUM> and a region surrounded by an outer edge of an outermost wire of the lower inductor <NUM>.

It can be understood that the plurality of implementation structures of the inductor device <NUM> are all used in the inductor device wiring architecture <NUM> shown in the first embodiment to the tenth embodiment.

Claim 1:
An inductor device wiring architecture (<NUM>), comprising:
an inductor device (<NUM>) and a plurality of dummy metals (<NUM>) located under the inductor device (<NUM>), wherein
the plurality of dummy metals (<NUM>) are arranged in a plurality of metal layers (<NUM>), each of the plurality of metal layers (<NUM>) corresponds to some of the plurality of dummy metals (<NUM>), characterised in that arrangement areas of dummy metals (<NUM>) corresponding to at least three adjacent metal layers of the plurality of metal layers (<NUM>) progressively increase in a direction away from the inductor device.