Patent Description:
In general, a display apparatus includes a display area in which an image is displayed, and a peripheral area. Electronic devices such as integrated circuits may be located in the peripheral area to generate or transmit electrical signals to the display area.

As the resolution of images displayed in the display area increases, the number of lines for transmitting electrical signals to the display area increases, and the number of pads that correspond to these lines and to which bumps of electronic devices are connected also increases.

However, as the number of pads and the number of lines connected thereto increase, the area of the peripheral area outside the display area is generally increased.

<CIT> discloses a display apparatus with a substrate and pads disposed in a peripheral area outside a display area on the substrate. Adjacent connection pad portions are disposed on the same layer and only an outermost pad is disposed on a lower layer. <CIT> discloses a display apparatus with pad portions and auxiliary pads. Further reference is made to <CIT>.

Display apparatus constructed according to embodiments of the invention are capable of displaying a high-resolution image while having a reduced peripheral area. The present invention is defined by the features of the independent claims. The dependent claims describe preferred embodiments.

A display apparatus according to an embodiment of the present invention includes a substrate including a display area and a peripheral area outside the display area, a first pad disposed on a first layer in the peripheral area, a second pad disposed adjacently to the first pad in a first direction in the peripheral area, the second pad being disposed on a second layer different from the first layer, a third pad disposed adjacently to the first pad in a second direction in the peripheral area, the third pad being disposed on the second layer, a fourth pad disposed adjacently to the third pad in the second direction in the peripheral area such that the third pad is interposed between the first pad and the fourth pad, the fourth pad being disposed on the first layer; a first connection line disposed on the first layer and connected to the first pad, a second connection line disposed on the second layer and connected to the second pad, a third connection line disposed on the second layer, connected to the third pad, and disposed between the first connection line and the second connection line, and a fourth connection line disposed on the first layer and connected to the fourth pad, and disposed between the second connection line and the third connection line, wherein the second layer covers the first pad, the fourth pad, the first connection line, and the fourth connection line.

The first connection line and the first pad may include the same layer structure, the second connection line and the second pad may include the same layer structure, and the third connection line and the third pad may include the same layer structure.

The first, second, and third connection lines may extend in a direction towards the display area.

The first connection line may be electrically connected to a first data line over the display area, the second connection line may be electrically connected to a second data line over the display area, and the third connection line may be electrically connected to a third data line over the display area.

The third data line may be disposed between the first data line and the second data line.

The display apparatus may further include a first test line disposed on the first layer and connected to the first pad, a second test line disposed on the second layer and connected to the second pad, and a third test line disposed on the second layer, connected to the third pad, and disposed between the first test line and the second test line.

The second layer may cover the first test line.

The first test line and the first pad may include the same layer structure, the second test line and the second pad may include the same layer structure, and the third test line and the third pad may include the same layer structure.

The first, second, and third test lines may extend in a direction away from the display area.

Each of the first, second, and third test lines may be electrically connected to a corresponding test transistor, respectively.

The display apparatus may further include bridge lines electrically connecting the first, second, and third test lines to corresponding test transistors, respectively.

The bridge lines may be disposed on a third layer covering the second test line and the third test line.

A distance between an edge of the first pad in a direction to the second pad and an edge of the second pad in a direction to the first pad may be about <NUM> to about <NUM>.

A width of the first pad in a direction to the second pad may be about <NUM> to about <NUM>.

A width of each of the first to third connection lines may be about <NUM> to about <NUM>.

The display apparatus may further include a third layer covering the second pad and the third pad, a first auxiliary pad disposed on the third layer, overlapping the first pad in a plan view, and electrically connected to the first pad, a second auxiliary pad disposed on the third layer, overlapping the second pad in a plan view, and electrically connected to the second pad, and a third auxiliary pad disposed on the third layer, overlapping the third pad in a plan view, and electrically connected to the third pad.

The first auxiliary pad may overlap the third connection line in a plan view.

A display apparatus according to another embodiment of the invention includes a substrate including a display area and a peripheral area outside the display area, a plurality of pads disposed on a first layer in the peripheral area and arranged substantially in parallel with each other in a first direction, a plurality of auxiliary pads disposed on a second layer different from the first layer in the peripheral area, arranged substantially in parallel with each other in the first direction, and interposed between the plurality of pads, connection lines disposed on the first layer and connected to the pads, and auxiliary connection lines disposed on the second layer and connected to the auxiliary pads.

The pads and the auxiliary pads are alternately arranged in the first direction.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the inventive concepts.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to be understood as providing features of varying detail of some ways in which the inventive concepts may be implemented in practice.

When an embodiment may be implemented differently, a specific process order may be performed differently from the described order.

Thus, the term "below" can encompass both an orientation of above and below.

Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing.

<FIG> is a schematic plan view of a portion of a display apparatus according to an embodiment, <FIG> is an enlarged plan view of portion A of <FIG> according to an embodiment, <FIG> is a schematic cross-sectional view taken along line III-III of the display apparatus of <FIG> according to an embodiment, and <FIG> is a schematic cross-sectional view taken along line IV-IV of the display apparatus of <FIG> according to an embodiment. <FIG> is a schematic cross-sectional view of a portion of a display area of <FIG> according to an embodiment.

Referring to <FIG>, the display apparatus according to the illustrated embodiment has a display area DA in which a plurality of pixels are located, and a peripheral area PA located outside the display area DA. A substrate <NUM> included in the display apparatus has the display area DA and the peripheral area PA. The peripheral area PA includes a pad area PDA to which various electronic devices, printed circuit boards, and the like are electrically bonded. The pad area PDA includes a test circuit part TC that may be used to test whether images are correctly displayed in the display area DA.

<FIG> exemplarily shows a substrate or the like during a manufacturing process. In a final display apparatus or an electronic apparatus such as a smartphone including the display apparatus, a portion of the substrate <NUM> or the like may be bent so as to minimize the area of the peripheral area PA that may be recognized by a user. For example, when the peripheral area PA includes a bending area, the bending area may be located between the pad area PDA and the display area DA. In this case, the substrate <NUM> may be bent in the bending area so that at least a part of the pad area PDA is located to overlap the display area DA. In this case, a bending direction is set so that the pad area PDA does not cover the display area DA, but the pad area PDA is located behind the display area DA. In this manner, a user may recognize that the display area DA occupies most of the display apparatus.

The substrate <NUM> may be flexible or bendable. For example, the substrate <NUM> may include a polymer resin, such as polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. However, the inventive concepts are not limited thereto. For example, in some embodiments, the substrate <NUM> may have a multiple layer structure that includes two layers each including the above-described polymer resin, and a barrier layer arranged between the two layers and including an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). Furthermore, when the substrate <NUM> is not bent, the substrate <NUM> may include glass or the like.

A thin-film transistor <NUM> is disposed on the substrate <NUM>, as shown in <FIG>. The thin-film transistor <NUM> may include a semiconductor layer <NUM>, a gate electrode <NUM>, a source electrode 215a, and a drain electrode 215b. The semiconductor layer <NUM> may include amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or an organic semiconductor material.

The thin-film transistor <NUM> includes the gate electrode <NUM>. The gate electrode <NUM> may include metal such as molybdenum or aluminum, and may have a single layer or a multiple layer structure. When the gate electrode <NUM> has a multiple layer structure, the gate electrode <NUM> may have a three-layer structure of molybdenum/aluminum/molybdenum. In order to secure an electrical insulation between the gate electrode <NUM> and the semiconductor layer <NUM>, a first gate insulating layer <NUM> may be between the gate electrode <NUM> and the semiconductor layer <NUM>. The first gate insulating layer <NUM> may include an inorganic material, such as silicon oxide, silicon nitride, and/or silicon oxynitride.

The gate electrode <NUM> may be covered by the second gate insulating layer <NUM>, as shown in <FIG>. In some embodiments, the gate electrode <NUM> may be disposed on the second gate insulating layer <NUM>, rather than being disposed between the first gate insulating layer <NUM> and the second gate insulating layer <NUM>. Hereinafter, the gate electrode <NUM> will exemplarily be described as being disposed between the first gate insulating layer <NUM> and the second gate insulating layer <NUM>. The second gate insulating layer <NUM> may also include an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

An interlayer insulating layer <NUM> may be arranged above the gate electrode <NUM> and the second gate insulating layer <NUM>. The interlayer insulating layer <NUM> may include an inorganic material, such as silicon oxide, silicon nitride, and/or silicon oxynitride. The source electrode 215a and the drain electrode 215b of the thin-film transistor <NUM> may be arranged on the interlayer insulating layer <NUM>. The source electrode 215a and the drain electrode 215b may include metal, such as titanium, copper, or aluminum, and may have a single layer structure or a multiple layer structure. When the source electrode 215a and the drain electrode 215b have a multiple layer structure, the source electrode 215a and the drain electrode 215b may have a three-layer structure of titanium/aluminum/titanium.

Insulating layers including an inorganic material, such as the first gate insulating layer <NUM>, the second gate insulating layer <NUM>, and the interlayer insulating layer <NUM>, may be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD).

A buffer layer <NUM> may be between the thin-film transistor <NUM> and the substrate <NUM>. The buffer layer <NUM> may include an inorganic material, such as silicon oxide, silicon nitride, and/or silicon oxynitride. The buffer layer <NUM> may increase flatness of the upper surface of the substrate <NUM>, and/or may prevent or reduce the permeation of impurities from the substrate <NUM> or the like to the semiconductor layer <NUM> of the thin-film transistor <NUM>.

The display apparatus according to the illustrated embodiment includes a plurality of pads in the pad area PDA, as shown in <FIG>. In particular, the display apparatus according to the illustrated embodiment includes a first pad PD1, a second pad PD2, and a third pad PD3 in the pad area PDA. The first pad PD1 and the second pad PD2 are disposed on a different layer. For example, the first pad PD1 may be disposed on the first gate insulating layer <NUM>, which may be referred to as a first layer, as shown in <FIG>, and the second pad PD2 and the third pad PD3 may be disposed on the second gate insulating layer <NUM>, which may be referred to as a second layer, as shown in <FIG> and <FIG>. The second pad PD2 is located adjacent to the first pad PD1. More particularly, the second pad PD2 is located in a first direction (-x direction) from the first pad PD1. The third pad PD3 is also located adjacent to the first pad PD1. More particularly, the third pad PD3 is located in a second direction (-y direction) from the first pad PD1.

The display apparatus according to the illustrated embodiment may include a plurality of pads in addition to the first to third pads PD1 to PD3. <FIG> illustrates that a fourth pad PD4 is located in the second direction (approximately -y direction) from the third pad PD3, which is in accordance with an embodiment of the present invention, and a fifth pad PD5 is located in the second direction (approximately -y direction) from the fourth pad PD4, and a sixth pad PD6 is located in the second direction (approximately -y direction) from the fifth pad PD5. The fourth pad PD4 and the sixth pad PD6 are disposed on the first gate insulating layer <NUM> or the first layer as the first pad PD1. The fifth pad PD5 is disposed on the second gate insulating layer <NUM> or the second layer as the third pad PD3.

As shown <FIG> and <FIG>, a plurality of pads including the first pad PD1 are arranged substantially in parallel in the first direction (-x direction). Similarly, a plurality of additional pads including the second pad PD2 are arranged substantially in parallel in the first direction (-x direction). As such, the additional pads may be disposed between the pads. In this case, the pads including the first pad PD1 are disposed on the first gate insulating layer <NUM> or the first layer, and the additional pads including the second pad PD2 are disposed on the second gate insulating layer <NUM> or the second layer. In this manner, the pads and the additional pads are alternately arranged in the first direction (-x direction).

A first connection line CL1 is connected to the first pad PD1, a second connection line CL2 is connected to the second pad PD2, and a third connection line CL3 is connected to the third pad PD3. As the first pad PD1 is disposed on the first gate insulating layer <NUM> or the first layer, the first connection line CL1 is also disposed on the first gate insulating layer <NUM> or the first layer. As the second pad PD2 is disposed on the second gate insulating layer <NUM> or the second layer, the second connection line CL2 is also disposed on the second gate insulating layer <NUM> or the second layer. As the third pad PD3 is disposed on the second gate insulating layer <NUM> or the second layer, the third connection line CL3 is also disposed on the second gate insulating layer <NUM> or the second layer, as shown in <FIG>. In this case, the third connection line CL3 passes between the first connection line CL1 and the second connection line CL2, as shown in <FIG>.

A fourth connection line CL4 is connected to the fourth pad PD4, a fifth connection line CL5 is connected to the fifth pad PD5, and a sixth connection line CL6 is connected to the sixth pad PD6. As the fourth pad PD4 and the sixth pad PD6 are disposed on the first gate insulating layer <NUM> or the first layer, the fourth connection line CL4 and the sixth connection line CL6 are also disposed on the first gate insulating layer <NUM> or the first layer. Because the fifth pad PD5 is disposed on the second gate insulating layer <NUM> or the second layer, the fifth connection line CL5 is also disposed on the second gate insulating layer <NUM> or the second layer.

As described above, when the pads including the first pad PD1 are arranged substantially in parallel in the first direction (-x direction) and the additional pads including the second pad PD2 are arranged substantially in parallel in the first direction (-x direction), the connection lines connected to the pads, including the first connection line CL1, are disposed on the first gate insulating layer <NUM> or the first layer, and additional connection lines connected to the additional pads, including the second connection line CL2, are disposed on the second gate insulating layer <NUM> or the second layer.

As the resolution of image displayed in the display area DA increases, the number of connection lines for transmitting electrical signals to the display area DA is generally increased. Also, the number of pads that correspond to the connection lines and to which bumps of an electronic device are connected is also generally increased. However, in the display apparatus according to the illustrated embodiment, even when the number of connection lines and the number of pads are increased, the area of the peripheral area PA may be minimized. More particularly, a distance between the adjacent connection lines may be significantly narrowed by arranging the adjacent connection lines on different layers from each other. As such, even when the number of connection lines are increased, the connection lines may be located within a narrow area while being the connection lines are prevented from being short-circuited to each other.

In particular, as illustrated in <FIG>, the third connection line CL3, the fourth connection line CL4, the fifth connection line CL5, and the sixth connection line CL6 are sequentially located in the first direction (-x direction). The third connection line CL3 and the fifth connection line CL5 are disposed on the second gate insulating layer <NUM> or the second layer, and the fourth connection line CL4 and the sixth connection line CL6 are disposed on the first gate insulating layer <NUM> or the first layer. In this manner, since adjacent connection lines are disposed on different layers from each other, the adjacent connection lines may not be electrically short-circuited even when the distance between the adjacent connection lines decreases. As such, the total area of the peripheral area PA may be reduced.

The inventive concepts are not limited to the relationship between the connection lines. For example, as illustrated in <FIG>, the first pad PD1 is located on a layer different from the third connection line CL3 adjacent thereto. In particular, the first pad PD1 is disposed on the first gate insulating layer <NUM> or the first layer. The third connection line CL3 that is most adjacent to the first pad PD1 is disposed on the second gate insulating layer <NUM> or the second layer, and is located in the first direction (-x direction) from the first pad PD1. In this manner, even when the distance between the first pad PD1 and the third connection line CL3 decreases, the probability of occurrence of a short-circuit therebetween is very low, and thus, the area of the peripheral area PA may be significantly reduced.

To this end, the second gate insulating layer <NUM> or the second layer may cover the first pad PD1, the fourth connection line CL4, and the sixth connection line CL6, which are disposed on the first gate insulating layer <NUM> or the first layer. As such, the third connection line CL3, the fifth connection line CL5, and the second pad PD2, which are disposed on the second gate insulating layer <NUM> or the second layer, and the first pad PD1, the fourth connection line CL4, and the sixth connection line CL6, which are located below the second gate insulating layer <NUM>, may be reliably electrically insulated.

As illustrated in <FIG>, the first pad PD1, the third pad PD3, the fourth pad PD4, the fifth pad PD5, and the sixth pad PD6 are sequentially arranged in the second direction (approximately -y direction), and the adjacent pads are disposed on different layers from each other. In particular, the first pad PD1, the fourth pad PD4, and the sixth pad PD6 are disposed on the first gate insulating layer <NUM> or the first layer, and the third pad PD3 and the fifth pad PD5 are disposed on the second gate insulating layer <NUM> or the second layer. This location relationship may also be applied to the second pad PD2 and pads located in the second direction (approximately -y direction) from the second pad PD2. For example, the seventh pad PD7 that is adjacently located to the second pad PD2 in the second direction (approximately -y direction) may be disposed on a layer different from a layer on which the second pad PD2 is located. More particular, unlike the second pad PD2 disposed on the second gate insulating layer <NUM> or the second layer, the seventh pad PD7 may be disposed on the first gate insulating layer <NUM> or the first layer. In this manner, as illustrated in <FIG>, the seventh connection line CL7 connected to the seventh pad PD7 is disposed on the first gate insulating layer <NUM> and is disposed on a layer different from a layer on which the adjacent second pad PD2 is located.

As illustrated in <FIG> and <FIG>, even the pads are sequentially arranged in the first direction (-x direction), the adjacent pads are disposed on different layers from each other. More particularly, the first pad PD1 is disposed on the first gate insulating layer <NUM> that is the first layer, and the second pad PD2 is disposed on the second gate insulating layer <NUM> that is the second layer. Similarly, the seventh pad PD7 is disposed on the first gate insulating layer <NUM> that is the first layer, and the third pad PD3 is disposed on the second gate insulating layer <NUM> that is the second layer.

Each connection line may have substantially the same layer structure as that of the connected pad. This is because each connection line may be simultaneously formed using the same material as that of the connected pad. For example, the first connection line CL1 may have substantially the same layer structure as that of the first pad PD1, the second connection line CL2 may have substantially the same layer structure as that of the second pad PD2, and the third connection line CL3 may have substantially the same layer structure as that of the third pad PD3. For example, the first to third connection lines CL1 to CL3 may each include metal such as molybdenum or aluminum, and may have a single layer or a multiple layer structure. When the first to third connection lines CL1 to CL <NUM> have a multiple layer structure, the gate electrode <NUM> may have a three-layer structure of molybdenum/aluminum/molybdenum.

As illustrated in <FIG>, the first to third connection lines CL1 to CL <NUM> may extend in a direction towards the display area DA (approximately +y direction). The first to third connection lines CL1 to CL <NUM> may be electrically connected to the corresponding data lines DL. For example, the first connection line CL1 may be electrically connected to a first data line DL1 of the display area DA, the second connection line CL2 may be electrically connected to a second data line DL2 of the display area DA, and the third connection line CL3 may be electrically connected to a third data line DL3 of the display area DA. In this case, the third data line DL3 may be located between the first data line DL1 and the second data line DL2.

As described above, the first connection line CL1 is disposed on the first gate insulating layer <NUM> that is the first layer, and the second connection line CL2 and the third connection line CL3 are disposed on the second gate insulating layer <NUM> that is the second layer. As such, when the first to third data lines DL1 to DL3 are disposed on a layer other than the first gate insulating layer <NUM> or the second gate insulating layer <NUM>, the first to third data lines DL1 to DL3 may be connected to the first to third connection lines CL1 to CL3 via contact holes.

For example, as illustrated in <FIG>, when the interlayer insulating layer <NUM>, which may be referred to as a third layer, covers the second connection line CL2 and the third connection line CL3, the first to third data lines DL1 to DL3 may be disposed on the interlayer insulating layer <NUM>. The first to third data lines DL1 to DL3 are electrically connected to the first to third connection lines CL1 to CL3 via contact holes formed in the interlayer insulating layer <NUM>. The first to third data lines DL1 to DL3 may be simultaneously formed using the same material as that of the source electrode 215a (see <FIG>) and the drain electrode 215b (see <FIG>). As such, the first to third data lines DL1 to DL3 may have substantially the same layer structures as those of the source electrode 215a and the drain electrode 215b. For example, the first to third data lines DL1 to DL3 may each include metal, such as titanium, copper, or aluminum, and may have a single layer structure or a multiple layer structure. When the first to third data lines DL1 to DL3 have a multiple layer structure, the first to third data lines DL1 to DL3 may have a three-layer structure of titanium/aluminum/titanium.

As illustrated in <FIG> and <FIG>, auxiliary pads may be disposed on the pads, respectively. These auxiliary pads may be referred to as a fourth layer and are disposed on the interlayer insulating layer <NUM> covering the second pad PD2, the third pad PD3, and the seventh pad PD7. Contact holes may be formed in the interlayer insulating layer <NUM> and/or the second gate insulating layer <NUM>, so that the auxiliary pads disposed on the interlayer insulating layer <NUM> may be in contact with the corresponding pads.

More particularly, a first auxiliary pad APD1 is disposed on the interlayer insulating layer <NUM> so as to overlap the first pad PD1 when viewed from a direction perpendicular to the substrate <NUM>. The first auxiliary pad APD1 is electrically connected to the first pad PD1 via the contact holes formed in the interlayer insulating layer <NUM> and the second gate insulating layer <NUM>. A second auxiliary pad APD2 is disposed on the interlayer insulating layer <NUM> so as to overlap the second pad PD2 when viewed from a direction perpendicular to the substrate <NUM>. The second auxiliary pad APD2 is electrically connected to the second pad PD2 via the contact hole formed in the interlayer insulating layer <NUM>. A third auxiliary pad APD3 is disposed on the interlayer insulating layer <NUM> so as to overlap the third pad PD3 when viewed from a direction perpendicular to the substrate <NUM>. The third auxiliary pad APD3 is electrically connected to the third pad PD3 via the contact hole formed in the interlayer insulating layer <NUM>. A seventh auxiliary pad APD7 is disposed on the interlayer insulating layer <NUM> so as to overlap the seventh pad PD7 when viewed from a direction perpendicular to the substrate <NUM>. The seventh auxiliary pad APD7 is electrically connected to the seventh pad PD7 via the contact holes formed in the interlayer insulating layer <NUM> and the second gate insulating layer <NUM>.

The auxiliary pads may be simultaneously formed using the same material as that of the source electrode 215a (see <FIG>) and the drain electrode 215b (see <FIG>). As such, the first auxiliary pad APD1, the second auxiliary pad APD2, the third auxiliary pad APD3, and the seventh auxiliary pad APD7 may have substantially the same layer structures as those of the source electrode 215a and the drain electrode 215b. For example, the first auxiliary pad APD1, the second auxiliary pad APD2, the third auxiliary pad APD3, and the seventh auxiliary pad APD7 may each include metal, such as titanium, copper, or aluminum, and may have a single layer structure or a multiple layer structure. When the first auxiliary pad APD1, the second auxiliary pad APD2, the third auxiliary pad APD3, and the seventh auxiliary pad APD7 have a multiple layer structure, the first auxiliary pad APD1, the second auxiliary pad APD2, the third auxiliary pad APD3, and the seventh auxiliary pad APD7 may have a three-layer structure of titanium/aluminum/titanium.

When viewed from a direction perpendicular to the substrate <NUM>, these auxiliary pads may overlap a portion of the connection lines located therebelow. <FIG> exemplarily illustrates that, when viewed from a direction perpendicular to the substrate <NUM>, the first auxiliary pad APD1 overlaps the third connection line CL3, and the second auxiliary pad APD2 overlaps the sixth connection line CL6 and/or the seventh connection line CL7. <FIG> exemplarily illustrates that, when viewed from a direction perpendicular to the substrate <NUM>, the third auxiliary pad APD3 overlaps the fourth connection line CL4. As such, when viewed from a direction perpendicular to the substrate <NUM>, each of the auxiliary pads may overlap a portion of the connection line that is most adjacent to the corresponding pad located therebelow. In particular, as the distance between the pad and the connection line that is most adjacent to the pad decreases to implement a high-resolution display apparatus, the degree of overlap between the auxiliary pads and the connection lines therebelow may be increased.

Bumps of an electronic device, such as an integrated circuit (IC), may be electrically connected to the auxiliary pads, as illustrated in <FIG> and <FIG>. To this end, an anisotropic conductive film ACF may be disposed between the auxiliary pads and the bumps. The anisotropic conductive film ACF includes an adhesive member AD and conductive balls CB. Because the adhesive member AD has adhesive force, the electronic device such as the IC is bonded to the auxiliary pads or the like on the substrate <NUM>. In this case, the conductive balls CB are disposed between the bumps BP1, BP2, BP3, and BP7 of the electronic device such as the IC and the auxiliary pads, so that the bumps BP1, BP2, BP3, and BP7 are electrically connected to the corresponding auxiliary pads, respectively. Bumps BP1, BP2, BP3, and BP7 may be defined as protrusions arranged on one surface, in particular on the bottom surface, of the integrated circuit (IC). The bumps and the IC between the bumps, in particular the bottom surface of the IC between the bumps, may be in contact with the anisotropic conductive film ACF. As shown in <FIG> the distance between neighboring bumps, e. between BP1 and BP2, and the distance sp between neighboring pads, e. between PD1 and PD2, may be the same. The bumps BP1, BP2, BP3, and BP7 may be located directly above the pads PD1, PD2, PD3, and PD7 and the auxiliary pads APD1, APD2, APD3, and APD7 in the third direction (z-direction) with the anisotropic conductive film ACF therebetween. In this case, the distance in the third direction (z-direction) between the bumps BP1, BP2, BP3, and BP7 and the interlayer insulating layer <NUM> is smaller than the distance between the bottom surface of the IC and the insulating layer <NUM>. Each ball CB may only electrically connected to one bump BP1, BP2, BP3, or BP7 and one auxiliary pad APD1, APD2, APD3, or APD7. The electrically connected bump and auxiliary pad may be located in the same plane in the third direction (z-direction).

As described above with reference to <FIG> and <FIG>, the adjacent pads among the pads that are sequentially arranged in the first direction (-x direction) are disposed on different layers from each other. In this case, the pads may include corresponding auxiliary pads disposed on the interlayer insulating layer <NUM> that is the third layer. As such, the bumps of the electronic device such as the IC are located above the auxiliary pads located at a substantially constant height from the substrate <NUM>, and thus, the electronic device such as the IC may be stably disposed on the substrate <NUM>.

The width of each of the connection lines, such as the third connection line CL3, may be about <NUM> to about <NUM>. When the width of each of the connection lines is less than <NUM>, the connection lines may be disconnected during a manufacturing process, and when the width of each of the connection line is greater than <NUM>, a high-resolution image may not be implemented. A space between the adjacent connection lines or a space between the pad and the most adjacent connection line may be about <NUM> to about <NUM>. The space between the adjacent connection lines refers to, for example, a distance between the edge of the fifth connection line CL5 in a direction to the fourth connection line CL4 and the edge of the fourth connection line CL4 in a direction to the fifth connection line CL5, when viewed from a direction perpendicular to the substrate <NUM>. The space between the pad and the most adjacent connection line refers to, for example, a distance between the edge of the first pad PD1 in a direction to the third connection line CL3 and the edge of the third connection line CL3 in a direction to the first pad PD1, when viewed from a direction perpendicular to the substrate <NUM>. When the space between the adjacent connection lines or the space between the pad and the most adjacent connection line is less than <NUM>, the magnitude of a parasitic capacitance generated between the adjacent connection lines increases rapidly, and when the space is greater than <NUM>, a high-resolution image may not be implemented.

Accordingly, a distance sp between the edge of the first pad PD1 in a direction to the second pad PD2 and the edge of the second pad PD2 in a direction to the first pad PD1 may be about <NUM> to about <NUM>. This is because there may be <NUM> connection lines between the first pad PD1 and the second pad PD2 along the first direction (-x direction) as shown in <FIG>, thus forming a minimum value of the distance sp of <NUM> (= <NUM> x <NUM> + <NUM> x <NUM>), and a maximum value of the distance sp of <NUM> (= <NUM> x <NUM> + <NUM> x <NUM>).

The width wd of the pads in the first direction (-x direction) may be about <NUM> to about <NUM>. When the resolution in the display area DA is <NUM> PPI, the pitch p of the pads in the first direction (-x direction) is about <NUM>. In order to implement such a high-resolution display apparatus, the distance sp between the edge of the first pad PD1 in a direction to the second pad PD2 and the edge of the second pad PD2 in a direction to the first pad PD1 may be about <NUM> to about <NUM>. This is because when the display apparatus is a high-resolution display apparatus, the maximum value of the distance sp is limited to <NUM>, which is less than <NUM>. When the distance sp is <NUM>, the width of the pads is <NUM> (= <NUM> - <NUM>) derived from the difference between the pitch p of the pads and the distance sp. When the distance sp is <NUM>, the width of the pads is <NUM> (= <NUM> - <NUM>). Accordingly, when the resolution in the display area DA is <NUM> PPI, the width wd of the pads is about <NUM> to about <NUM>. For similar reasons, when the resolution in the display area DA is <NUM> PPI, the pitch p of the pads in the first direction (-x direction) is about <NUM> and the distance sp is about <NUM> to about <NUM>, and thus, the width wd of the pads is about <NUM> to about <NUM>. When the resolution in the display area DA is <NUM> PPI, the pitch p of the pads in the first direction (-x direction) is about <NUM> and the distance sp is about <NUM> to about <NUM>, and thus, the width wd of the pads is about <NUM> to about <NUM>. Accordingly, the width of the pads is about <NUM> to about <NUM>.

Signals applied to the pads are transmitted to the data lines through the connection lines, so that the pixels in the display area DA emit light having luminance corresponding to the signals. A display element is located in the display area DA. For example, as illustrated in <FIG>, an organic light-emitting device <NUM> may be located in the display area DA. The organic light-emitting device <NUM> may be disposed on a planarization layer <NUM> covering the source electrode 215a and the drain electrode 215b. The planarization layer <NUM> may planarize substantially the entire upper portion of the thin-film transistor <NUM>. The planarization layer <NUM> may include, for example, an organic material such as acryl, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). <FIG> exemplarily illustrates that the planarization layer <NUM> has a single layer, but the inventive concepts are not limited thereto. For example, in another embodiment, the planarization layer <NUM> may have multiple layers. When the display element is the organic light-emitting device <NUM>, the display element may include a pixel electrode <NUM>, an opposite electrode <NUM>, and an intermediate layer <NUM> located therebetween and including an emission layer.

As illustrated in <FIG>, the pixel electrode <NUM> may be in contact with one of the source electrode 215a and the drain electrode 215b via an opening formed in the planarization layer <NUM> or the like, and may be electrically connected to the thin-film transistor <NUM>. The pixel electrode <NUM> includes a light-transmitting conductive layer including a light-transmitting conductive oxide, such as ITO, In<NUM>O<NUM> or IZO, and a reflective layer including a metal, such as Al or Ag. For example, the pixel electrode <NUM> may have a three-layer structure of ITO/Ag/ITO.

A pixel defining layer <NUM> may be arranged above the planarization layer <NUM>. The pixel defining layer <NUM> may include an opening corresponding to each sub-pixel, that is, an opening exposing a central portion of at least the pixel electrode <NUM>, thereby defining a pixel. Also, as illustrated in <FIG>, the pixel defining layer <NUM> increases a distance between the edge of the pixel electrode <NUM> and the opposite electrode <NUM> above the pixel electrode <NUM>, thereby preventing arcs or the like from occurring at the edge of the pixel electrode <NUM>. The pixel defining layer <NUM> may include, for example, an organic material, such as polyimide or hexamethyldisiloxane (HMDSO).

The intermediate layer <NUM> of the organic light-emitting device <NUM> may include a low molecular weight material or a high molecular weight material. When the intermediate layer <NUM> includes a low molecular weight material, the intermediate layer <NUM> may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or multiple structure. The intermediate layer <NUM> may be formed by vacuum deposition. When the intermediate layer <NUM> includes a high molecular weight material, the intermediate layer <NUM> may have a structure including an HTL and an EML. In this case, the HTL may include poly(<NUM>,<NUM>-ethylenedioxythiophene) (PEDOT), and the EML may include a high molecular weight material such as a poly-phenylenevinylene (PPV)-based polymer and a polyfluorene-based polymer. The intermediate layer <NUM> may be formed by screen printing, inkjet printing, or laser induced thermal image (LITI). However, the inventive concepts are not limited thereto, and may have various structures. For example, in some embodiments, the intermediate layer <NUM> may include an integrated layer throughout the pixel electrodes <NUM>, or may include layers patterned to correspond to the pixel electrodes <NUM>.

The opposite electrode <NUM> may be arranged above the display area DA and cover the display area DA. In particular, the opposite electrode <NUM> may be integrally formed with respect to the organic light-emitting devices <NUM> and may correspond to the pixel electrodes <NUM>. The opposite electrode <NUM> may include a light-transmitting conductive layer such as ITO, In<NUM>O<NUM>, or IZO, and may also include a semi-transmissive layer including metal such as Al or Ag. For example, the opposite electrode <NUM> may include a semi-transmissive layer including Mg/Ag.

Because the organic light-emitting device <NUM> may be easily damaged by external moisture or oxygen, an encapsulation layer may cover the organic light-emitting device to protect the organic light-emitting device <NUM>. The encapsulation layer may cover the display area DA and extend to at least a portion of the peripheral area PA. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

As illustrated in <FIG>, a first test line TL1 is connected to the first pad PD1, a second test line TL2 is connected to the second pad PD2, and a third test line TL3 is connected to the third pad PD3. As the first pad PD1 is disposed on the first gate insulating layer <NUM> that is the first layer, the first test line TL1 may also be disposed on the first gate insulating layer <NUM> that is the first layer, as illustrated in <FIG>. As the second pad PD2 is disposed on the second gate insulating layer <NUM> that is the second layer, the second test line TL2 may also be disposed on the second gate insulating layer <NUM> that is the second layer, as illustrated in <FIG>. In addition, as the third pad PD3 is disposed on the second gate insulating layer <NUM> that is the second layer, the third test line TL3 may also be disposed on the second gate insulating layer <NUM> that is the second layer. In this case, the third test line TL3 is disposed between the first test line TL1 and the second test line TL2, as illustrated in <FIG>.

A fourth test line TL4 is connected to the fourth pad PD4, a fifth test line TL5 is connected to the fifth pad PD5, and a sixth test line TL6 is connected to the sixth pad PD6. As the fourth pad PD4 and the sixth pad PD6 are disposed on the first gate insulating layer <NUM> that is the first layer, the fourth test line TL4 and the sixth test line TL6 may also be disposed on the first gate insulating layer <NUM> that is the first layer. In addition, as the fifth pad PD5 is disposed on the second gate insulating layer <NUM> that is the second layer, the fifth test line TL5 may also be disposed on the second gate insulating layer <NUM> that is the second layer.

Each of the test lines extends in a direction away from the display area DA (approximately -y direction) and is electrically connected to a corresponding test transistor. This will be described in more detail later below.

As the resolution of image displayed in the display area DA increases, the number of connection lines for transmitting electrical signals to the display area DA may be increased. As such, the number of test lines corresponding to the connection lines may also be generally increased. However, in the display apparatus according to the illustrated embodiment, the area of the peripheral area PA may be minimized even when the number of test lines increases. More particularly, a distance between the adjacent test lines may be significantly narrowed by arranging the adjacent test lines on different layers from each other. In this manner, even when the number of test lines may be increased, the test lines may be located within a narrow area while being prevented from being short-circuited with each other.

In particular, as illustrated in <FIG>, the first test line TL1, the third test line TL3, the fourth test line TL4, the fifth test line TL5, and the sixth test line TL6 are sequentially arranged in the first direction (-x direction). The third test line TL3 and the fifth test line TL5 are disposed on the second gate insulating layer <NUM> that is the second layer, and the first test line TL1, the fourth test line TL4, and the sixth test line TL6 are disposed on the first gate insulating layer <NUM> that is the first layer. Since the adjacent test lines are disposed on different layers from each other, the adjacent test lines may not be electrically short-circuited even when the distance between the adjacent test lines decreases. In this manner, the total area of the peripheral area PA may be reduced.

This configuration is not limited to the relationship between the test lines. In particular, as illustrated in <FIG>, the third pad PD3 is located in a layer different from the first test line TL1 that is located adjacent thereto. In addition, the third pad PD3 is disposed on the second gate insulating layer <NUM> that is the second layer, and is located in a direction (+x direction) opposite to the first direction from the third pad PD3. The first test line TL1 that is most adjacent to the third pad PD3 is disposed on the first gate insulating layer <NUM> that is the first layer. As such, even when the distance between the third pad PD3 and the first test line TL1 may be decreased, the probability of occurrence of a short-circuit therebetween becomes very low, and thus, the area of the peripheral area PA may be significantly reduced.

As illustrated in <FIG>, the second gate insulating layer <NUM> that is the second layer may cover the first test line TL1 disposed on the first gate insulating layer <NUM> that is the first layer. As such, the third pad PD3 or the like, which is disposed on the second gate insulating layer <NUM> that is the second layer, and the first test line TL1 or the like, which is located below the second gate insulating layer <NUM>, may be reliably electrically insulated.

Each test line may have substantially the same layer structure as that of the connected pad. This is because each test line may be simultaneously formed using the same material as that of the connected pad. For example, the first test line TL1 may have substantially the same layer structure as that of the first pad PD1, the second test line TL2 may have substantially the same layer structure as that of the second pad PD2, and the third test line TL3 may have substantially the same layer structure as that of the third pad PD3. For example, the first to third test lines TL1 to TL3 may each include metal such as molybdenum or aluminum, and may have a single layer or a multiple layer structure. When the first to third test lines TL1 to TL3 have a multiple layer structure, the gate electrode <NUM> may have a three-layer structure of molybdenum/aluminum/molybdenum.

As illustrated in <FIG>, the first to third test lines TL1 to TL3 may extend in a direction (approximately -y direction) opposite to the direction of the display area DA, and may be electrically connected to the test circuit part TC. <FIG> is a schematic circuit diagram of a test circuit located in the test circuit part TC of <FIG> according to an embodiment.

As illustrated in <FIG>, gate electrodes of test thin-film transistors TT are electrically connected to each other by a test gate line TGL. As such, when an electrical signal is applied to the test gate line TGL, the test thin-film transistors TT are simultaneously turned on. An electrical signal from a first test signal line TSL1 is transmitted to the corresponding data lines through the test lines TL2, TL6, TL3, and TL1, and the pads and the connection lines connected thereto. Accordingly, the pixels in the display area DA, which are electrically connected to the data lines, may emit light. In the manner, whether the pixels in the display area DA are defective may be tested. Similarly, an electrical signal from a second test signal line TSL2 is transmitted to the corresponding data lines through the test lines TL5 and TL4, and the pads and the connection lines connected thereto. Accordingly, the pixels in the display area DA, which are electrically connected to the data lines, may emit light. In this manner, whether the pixels in the display area DA are defective may be tested. In some embodiments, the first test signal line TSL1 and the second test signal line TSL2 may be integrally formed with each other.

<FIG> is a schematic plan view of a portion of the test circuit part TC of <FIG> according to an embodiment. <FIG> is a schematic cross-sectional view taken along line VIII-VIII of the display apparatus of <FIG> according to an embodiment, <FIG> is a schematic cross-sectional view taken along line IX-IX of the display apparatus of <FIG> according to an embodiment, and <FIG> is a schematic cross-sectional view taken along line X-X of the display apparatus of <FIG> according to an embodiment.

As illustrated in <FIG>, the first to sixth test lines TL1 to TL6 are arranged on the first gate insulating layer <NUM> or the second gate insulating layer <NUM>. As illustrated in <FIG>, the first to sixth test lines TL1 to TL6 are electrically connected to one end of the semiconductor layer SC of the test thin-film transistor TT through first bridge lines BR1.

The first bridge line BR1 may function as a drain electrode of the test thin-film transistor TT. The first bridge line BR1 may be disposed on the interlayer insulating layer <NUM> that is the third layer covering the second test line TL2, the third test line TL3, and the fifth test line TL5. The first bridge line BR1 may be simultaneously formed using the same material as that of the source electrode 215a and the drain electrode 215b described above with reference to <FIG>. In particular, the first bridge line BR1 may have substantially the same layer structure as that of the auxiliary pad described above with reference to <FIG> and <FIG>.

The other end of each of the semiconductor layers SC of some test thin-film transistors TT may be directly connected to the first test signal line TSL1. For example, as illustrated in <FIG>, the other end of the semiconductor layer SC having one end electrically connected to the first test line TL1 may be connected to the first test signal line TSL1 via a contact hole. The first test signal line TSL1 may be disposed on the interlayer insulating layer <NUM> that is the third layer, and may be simultaneously formed using the same material as that of the source electrode 215a and the drain electrode 215b described above with reference to <FIG>. As such, the first test signal line TSL1 may have substantially the same layer structure as that of the auxiliary pad described above with reference to <FIG> and <FIG>.

The other end of each of the semiconductor layers SC of some test thin-film transistors TT may be electrically connected to the second test signal line TSL2 through a second bridge line BR2 and a third bridge line BR3. For example, as illustrated in <FIG>, the other end of the semiconductor layer SC having one end electrically connected to the fifth test line TL5 may be electrically connected to the second bridge line BR2 disposed on the interlayer insulating layer <NUM> that is the third layer via a contact hole. The second bridge line BR2 may be connected to the third bridge line BR3 located below the interlayer insulating layer <NUM> via a contact hole. The third bridge line BR3 may pass under the first test signal line TSL1 and extend under the second test signal line TSL2. The second test signal line TSL2 may be connected to the third bridge line BR3 via a contact hole formed in the interlayer insulating layer <NUM> or the like.

The second bridge line BR2 and the second test signal line TSL2 may be disposed on the interlayer insulating layer <NUM> that is the third layer, and may be simultaneously formed using the same material as that of the source electrode 215a and the drain electrode 215b described above with reference to <FIG>. As such, the second bridge line BR2 and the second test signal line TSL2 may have substantially the same layer structure as that of the auxiliary pad described above with reference to <FIG> and <FIG>. As illustrated in <FIG>, the third bridge line BR3 may be disposed on the second gate insulating layer <NUM>. In this case, the third bridge line BR3 may include the same material as that of the fifth test line TL5 and may have substantially the same layer structure as that of the fifth test line TL5. However, the inventive concepts are not limited thereto. For example, in some embodiments, the third bridge line BR3 may be disposed between the first gate insulating layer <NUM> and the second gate insulating layer <NUM>, and may be connected to the second test signal line TSL2 via contact holes formed in the second gate insulating layer <NUM> and the interlayer insulating layer <NUM>. In this case, the third bridge line BR3 may include the same material as that of the first pad PD1 (see <FIG>) and may have substantially the same layer structure as that of the first pad PD1.

The test gate line TGL extends in the first direction (-x direction) to pass over the semiconductor layers SC of the test thin-film transistors TT. In the test gate line TGL, portions overlapping the semiconductor layers SC of the test thin-film transistors TT may function as the gate electrodes of the test thin-film transistors TT. As the test gate line TGL is disposed on the first gate insulating layer <NUM>, the test gate line TGL may also include the same material as that of the first pad PD1 disposed on the first gate insulating layer <NUM> and may have substantially the same layer structure as that of the first pad PD <NUM>.

As described above with reference to <FIG>, the first test line TL1, the second test line TL2, the third test line TL3, the fourth test line TL4, the fifth test line TL5, and the sixth test line TL6 are sequentially located in the first direction (-x direction). As illustrated in <FIG>, the second test line TL2, the third test line TL3, and the fifth test line TL5 are disposed on the second gate insulating layer <NUM> that is the second layer, and the first test line TL1, the fourth test line TL4, and the sixth test line TL6 are disposed on the first gate insulating layer <NUM> that is the first layer. As such, since the adjacent test lines are disposed on different layers from each other, the adjacent test lines may not be electrically short-circuited even when the distance between the adjacent test lines decreases. In this manner, the total area of the peripheral area PA may be reduced while the display apparatus is capable of displaying the high-resolution image.

In general, the test for defects of the display elements in the display area DA using the test thin-film transistor TT is performed during the manufacturing process. When the manufacture of a display apparatus is completed, the test thin-film transistors TT are turned off. For example, when the test thin-film transistors TT are p-type thin-film transistors, the test thin-film transistors TT are turned off by applying a VGH bias voltage (positive bias voltage) to the test gate line TGL. In this manner, signals from the electronic device such as the IC may be applied to the data lines through the pads and the connection lines.

Claim 1:
A display apparatus comprising:
a substrate (<NUM>) comprising a display area (DA) and a peripheral area (PA) outside the display area (DA);
a first pad (PD1) disposed on a first layer in the peripheral area (PA);
a second pad (PD2) disposed adjacently to the first pad (PD1) in a first direction in the peripheral area (PA), the second pad (PD2) being disposed on a second layer different from the first layer;
a third pad (PD3) disposed adjacently to the first pad (PD1) in a second direction in the peripheral area (PA), the third pad (PD3) being disposed on the second layer;
a fourth pad (PD4) disposed adjacently to the third pad (PD3) in the second direction in the peripheral area (PA) such that the third pad (PD3) is interposed between the first pad (PD1) and the fourth pad (PD4), the fourth pad (PD4) being disposed on the first layer;
a first connection line (CL1) disposed on the first layer and connected to the first pad (PD1);
a second connection line (CL2) disposed on the second layer and connected to the second pad (PD2);
a third connection line (CL3) disposed on the second layer and connected to the third pad (PD3), and disposed between the first connection line (CL1) and the second connection line (CL2); and
a fourth connection line (CL4) disposed on the first layer and connected to the fourth pad (PD4), and disposed between the second connection line (CL2) and the third connection line (CL3),
wherein the second layer covers the first pad (PD1), the fourth pad (PD4), the first connection line (CL1), and the fourth connection line (CL4).