Patent Description:
Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, , planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

<CIT> discloses a method for manufacturing a 3D NAND memory device, the memory device including a plurality of channel structures extending through a memory cell stack, a plurality of source lines, and a plurality of vias coupled to the plurality of source lines.

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

Claim <NUM> defines a three-dimensional memory device according to the invention and claim <NUM> defines a method for forming a three-dimensional memory device accoording to the invention.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

In some 3D memory devices, the periphery circuits and memory array are stacked to save wafer area and increase memory cell density. For example, direct bonding technologies have been proposed to fabricate some 3D NAND memory devices (e.g., having <NUM>-layers or more) by joining peripheral device and memory array on different substrates in a face-to-face manner. The memory array substrate is then thinned for forming through-silicon vertical interconnect access (VIA), known as "TSV" therethrough to vertical interconnections and pad-out on the backside of the thinned substrate with wire bonding pads. However, as only wire bonding pads and TSVs are formed on the backside of the thinned substrate (i.e., the top surface of the bonded 3D memory device), a substantial amount of area on the backside of the thinned substrate is wasted.

Various embodiments in accordance with the present disclosure provide 3D memory devices with backside interconnect structure to better utilize the backside area and optimize the metal routings. Some or all of the source lines, source select gate (SSG) lines, and power lines can be moved from the front side of the memory array substrate (i.e., in the middle of the bonded 3D memory device) to the backside of the memory array substrate (i.e., on the top surface of the bonded 3D memory device) as the "backside interconnect structures. " In some embodiments, the backside source lines allow source contacts to be formed on the backside of the memory array substrate as well, which can avoid leakage current and parasitic capacitance between the word lines and source contacts on the front side through the memory stack. The various backside interconnect structures can be arranged in different layouts, such as a mesh (e.g., comb-like shape) or parallel straight lines, to optimize the metal routings and reduce the overall resistance based on different memory array structures to further improve the electrical performance of the 3D memory devices.

<FIG> illustrates a plan view of a cross-section of an exemplary 3D memory device <NUM> having a center staircase region, according to some embodiments of the present disclosure. As shown in <FIG>, the memory stack of 3D memory device <NUM> includes two core array regions 106A and 106B having channel structures <NUM> therein and a staircase region <NUM> between core array regions 106A and 106B in a first lateral direction in the plan view. It is noted that x and y axes are included in <FIG> to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. 3D memory device <NUM> includes center staircase region <NUM> laterally separating the memory stack in the x-direction (e.g., the word line direction) into two parts: a first core array region 106A and a second core array region 106B, each of which includes an array of channel structures <NUM>, according to some embodiments.

3D memory device <NUM> also includes parallel insulating structures <NUM> (e.g., gate line slits (GLSs)) in the y-direction (e.g., the bit line direction) each extending laterally in the x-direction to separate core array regions 106A and <NUM> and arrays of channel structures <NUM> therein into blocks <NUM>, according to some embodiments. 3D memory device <NUM> can further include parallel drain select gate (DSG) cuts <NUM> (sometimes known as top select gate (TSG) cuts) in the y-direction in block <NUM> to further separate block <NUM> into fingers. It is understood that the layout of the staircase region and core array regions is not limited to the example of <FIG> and may include any other suitable layouts, such as having side staircase regions at the edges of the memory stack in other examples.

The cross-section of 3D memory device <NUM> is on the front side of 3D memory device <NUM> on which channel structures <NUM> are formed. In some embodiments, 3D memory device <NUM> is flipped upside down and bonded to another semiconductor device, such as a peripheral device having peripheral circuits for facilitating the operations of 3D memory device <NUM>. Thus, the backside of 3D memory device <NUM> can become the top surface of the bonded device, which can be used for pad-out. As described below in detail, the area on the backside of 3D memory device <NUM> (i.e., the top surface of the bonded device) can be utilized to form, besides bonding pads, various backside interconnect structures in various layouts to optimize the metal routings and reduce the overall resistance as well as reduce leakage current and parasitic capacitance on the front side of 3D memory device <NUM>.

<FIG> illustrates a plan view of a cross-section of an exemplary 3D memory device <NUM> with backside interconnect structures, according to some embodiments of the present disclosure. 3D memory device <NUM> may be one example of 3D memory device <NUM> after flip-chip bonding, and <FIG> shows one example of the backside of 3D memory device <NUM> after flip-chip bonding. As shown in <FIG>, the memory stack of 3D memory device <NUM> includes two core array regions 206A and 206B having channel structures therein (not shown) and a staircase region <NUM> between core array regions 206A and 206B in the x-direction (e.g., the word line direction) in the plan view, according to some embodiments. In some embodiments, 3D memory device <NUM> further includes a peripheral region <NUM> outside of core array region 206A or 206B of the memory stack in the plan view. In the y-direction (e.g., the bit line direction), <FIG> shows backside interconnect structures in one block <NUM> of 3D memory device <NUM>, which may be repeated in any suitable number of times in multiple blocks.

According to the invention, 3D memory device <NUM> includes a source line mesh <NUM> in the plan view. As shown in <FIG>, source line mesh <NUM> has a comb-like shape, according to some embodiments. For example, source line mesh <NUM> may include a shaft source line <NUM> extending laterally in the y-direction (e.g., the bit line direction) in one of core array regions 206A and 206B. Source line mesh <NUM> may also include a plurality of parallel tooth source lines <NUM> each extending laterally from shaft source line <NUM> in one core array region 206A in the x-direction (e.g., the word line direction) through staircase region <NUM> to another core array region 206B. In some embodiments, source line mesh <NUM> is in core array regions 206A and 206B and staircase region <NUM>, for example, extending in the x-direction across core array regions 206A and 206B and staircase region <NUM>, but not in peripheral region <NUM>.

3D memory device <NUM> also includes backside source contacts <NUM> (e.g., in the form of VIA contacts) in core array regions 206A and 206B, but not in staircase region <NUM> or peripheral region <NUM>. For example, backside source contacts <NUM> may be evenly distributed in core array region 206A or 206B. In some embodiments, backside source contacts <NUM> are distributed below and in contact with source line mesh <NUM>. For example, backside source contacts <NUM> may be evenly distributed below and in contact with source line mesh <NUM> in core array region 206A or 206B. That is, the distances between adjacent backside source contacts <NUM> (e.g., in the x-direction and/or the y-direction) are the same in core array region 206A or 206B. In some embodiments, backside source contacts <NUM> are distributed below and in contact with tooth source lines <NUM> of source line mesh <NUM>, but not shaft source line <NUM> of source line mesh <NUM>. It is understood that in some examples, backside source contacts <NUM> in the form of VIA contacts may be replaced by one or more source wall-shaped contacts, i.e., interconnect lines.

3D memory device <NUM> can further include a plurality of sets of contacts <NUM>, <NUM> and <NUM>, such as through-silicon contacts (TSCs). In some embodiments, contacts <NUM> are distributed below and in contact with source line mesh <NUM> in staircase region <NUM> and part of core array regions 206A and 206B. As contacts <NUM> may be TSCs extending through the silicon substrate, contacts <NUM> are distributed below and in contact with the peripheral portion of source line mesh <NUM> (including the part in staircase region <NUM>) to avoid overlapping with the channel structures in the center portion of source line mesh <NUM> in core array regions 206A and 206B, according to some embodiments. For example, as shown in <FIG>, contacts <NUM> may be distributed below and in contact with shaft source line <NUM> and the outermost tooth source lines <NUM> of source line mesh <NUM> in core array regions 206A and 206B. Contacts <NUM> may also be distributed below and in contact with each tooth source line <NUM> of source line mesh <NUM> in staircase region <NUM>.

As described below in detail, each backside source contact <NUM> can be electrically connected to the common source (e.g., array common source (ASC)) of NAND memory strings in block <NUM>, and source line mesh <NUM> electrically connects each backside source contact <NUM> and is in turn, electrically connected to the common source of NAND memory strings in block <NUM>. Similarly, each contact <NUM> can be electrically connected to the peripheral circuits of 3D memory device <NUM>, and source line mesh <NUM> electrically connects each contact <NUM> and is in turn, electrically connected to the peripheral circuits of 3D memory device <NUM>. As a result, the peripheral circuits can be electrically connected to the common source of NAND memory strings in block <NUM> to control and/or sense the common source through the metal routing including contacts <NUM>, source line mesh <NUM>, and backside source contacts <NUM> on the backside of 3D memory device <NUM>. The layout of contacts <NUM>, source line mesh <NUM>, and backside source contacts <NUM>, for example, the comb-like shape of source line mesh <NUM> and multiple distributed contacts <NUM> and backside source contacts <NUM>, can reduce the overall resistance of the metal routing.

According to the invention, 3D memory device <NUM> includes another backside interconnect structure - a power line mesh <NUM> in the plan view. As shown in <FIG>, power line mesh <NUM> has a comb-like shape, according to some embodiments. For example, power line mesh <NUM> may include a shaft power line <NUM> extending laterally in the y-direction (e.g., the bit line direction) in peripheral region <NUM>. Power line mesh <NUM> can also include a plurality of parallel tooth power lines <NUM> each extending laterally from shaft power line <NUM> in peripheral region <NUM> in the x-direction (e.g., the word line direction) through one core array region 206B, staircase region <NUM>, to another core array region 206A. In some embodiments, power line mesh <NUM> is in peripheral region <NUM>, core array regions 206A and 206B, and staircase region <NUM>, for example, extending in the x-direction from peripheral region <NUM> across core array regions 206A and 206B and staircase region <NUM>. In some embodiments, tooth power lines <NUM> are interleaved with tooth source lines <NUM> in the y-direction.

According to the invention, contacts <NUM> are distributed below and in contact with power line mesh <NUM> in staircase region <NUM> and peripheral region <NUM>, but not in core array regions 206A and 206B. As contacts <NUM> may be TSCs extending through the silicon substrate, contacts <NUM> are not in core array regions 206A and 206B to avoid overlapping with the channel structures in core array regions 206A and 206B, according to some embodiments. For example, as shown in <FIG>, contacts <NUM> may be distributed below and in contact with shaft power line <NUM> in peripheral region <NUM> and parts of tooth power lines <NUM> in staircase region <NUM>. It is understood that in some examples, contacts <NUM> may be distributed in either peripheral region <NUM> or staircase region <NUM>, but not both. That is, according to the invention, contacts <NUM> are distributed in at least one of staircase region <NUM> or peripheral region <NUM> outside of the memory array in the plan view.

Each contact <NUM> can be electrically connected to the power line of the peripheral circuits of 3D memory device <NUM>, and power line mesh <NUM> electrically connects each contact <NUM> and is in turn, electrically connected to the power line of the peripheral circuits of 3D memory device <NUM>. A power supply can be electrically connected to power line mesh <NUM> through bonding pads (not shown) to provide power to 3D memory device <NUM> through the metal routing including contacts <NUM> and power line mesh <NUM> on the backside of 3D memory device <NUM>. The bonding pads can be part of the backside interconnect structures and electrically connected to power line mesh <NUM> through contacts <NUM>. The layout of contacts <NUM> and power line mesh <NUM>, for example, the comb-like shape of power line mesh <NUM> and multiple distributed contacts <NUM>, can reduce the overall resistance of the metal routing.

In some embodiments, 3D memory device <NUM> includes still another backside interconnect structure - a plurality of SSG lines <NUM> in the plan view. Each SSG line <NUM> can extend in the x-direction (e.g., the word line direction) across two core array regions 206A and 206B and staircase region <NUM>. In some embodiments, SSG lines <NUM> are evenly distributed in parallel in the y-direction (e.g., the bit line direction) in the plan view. SSG lines <NUM>, tooth power line <NUM>, and tooth source line <NUM> can be in parallel. As shown in <FIG>, each SSG line <NUM> can be sandwiched between two tooth power lines <NUM> in the y-direction. It is understood that the arrangement of SSG lines <NUM>, tooth power line <NUM>, and tooth source line <NUM> may vary in other examples. For example, SSG lines <NUM>, tooth power line <NUM>, and tooth source line <NUM> may be interleaved with one another in the y-direction.

In some embodiments, contacts <NUM> are distributed below and in contact with SSG lines <NUM> in core array regions 206A and 206B in the plan view, but not in staircase region <NUM> and peripheral region <NUM>. For example, as shown in <FIG>, at least one contact <NUM> in core array region 206A and at least one contact <NUM> in core array region 206B are below and in contact with each SSG line <NUM>. The SSG in the memory stack of 3D memory device <NUM> may be cut off in staircase region <NUM>, becoming two disconnected parts in core array regions 206A and 206B, respectively. Each contact <NUM> can be electrically connected to one part of the SSG of 3D memory device <NUM> in respective core array region 206A or 206B. By extending over staircase region <NUM> between two core array regions 206A and 206B in the x-direction and electrically connecting contacts <NUM> in each core array region 206A or 206B, SSG lines <NUM> can thus electrically connect the two disconnected parts of the SSG in core array regions 206A and 206B. That is, the two disconnected parts of the SSG in core array regions 206A and 206B can be "bridged" across staircase region <NUM> by the metal routing including SSG lines <NUM> and contacts <NUM> on the backside of 3D memory device <NUM>. The layout of contacts <NUM> and SSG lines <NUM>, for example, the multiple parallel SSG lines <NUM> and multiple distributed contacts <NUM>, can reduce the overall resistance of the metal routing.

It is understood that the backside interconnect structures are not limited to the example in <FIG> and may include any other suitable layouts depending on the design of the 3D memory device, such as the specification (e.g., voltage and resistance) of the electrical performance. It is also understood that additional backside interconnect structures may be disposed on the same surface as source line mesh <NUM>, power line mesh <NUM>, and SSG lines <NUM> as shown in <FIG>. For example, bonding pads (not shown) for wire bonding may be disposed on the backside of 3D memory device <NUM> as well, such as in peripheral region <NUM>.

<FIG> illustrates a plan view of a cross-section of another exemplary 3D memory device <NUM> with backside interconnect structures, according to some embodiments of the present disclosure. 3D memory device <NUM> may be substantially the same as 3D memory device <NUM> in <FIG> except that 3D memory device <NUM> does not include SSG lines <NUM> and contacts <NUM> in <FIG>. <FIG> illustrates a plan view of a cross-section of still another exemplary 3D memory device <NUM> with backside interconnect structures, according to some examples not forming part of the invention. 3D memory device <NUM> may be substantially the same as 3D memory device <NUM> in <FIG> except that 3D memory device <NUM> does not include SSG lines <NUM>, power line mesh <NUM>, and contacts <NUM> and <NUM> in <FIG>. Moreover, by removing power line mesh <NUM>, source line mesh <NUM> in 3D memory device <NUM> can have two parallel shaft source lines <NUM> in core array regions 206A and 206B, respectively.

<FIG> illustrates a side view of a cross-section of an exemplary 3D memory device <NUM> with backside interconnect structures, according to some embodiments of the present disclosure. 3D memory device <NUM> may be one example of 3D memory devices <NUM>, <NUM>, and <NUM> in <FIG> may illustrate plan views of the cross-sections in the AA plane of 3D memory device <NUM> in <FIG>, i.e., the backside of 3D memory device <NUM>. In some embodiments, 3D memory device <NUM> is a bonded chip including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are jointed at a bonding interface <NUM> therebetween, according to some embodiments. As shown in <FIG>, first semiconductor structure <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of 3D memory device <NUM> can include peripheral circuits <NUM> on substrate <NUM>. It is noted that x-, y-, and z- axes are included in <FIG> to illustrate the spatial relationships of the components in 3D memory device <NUM>. Substrate <NUM> includes two lateral surfaces extending laterally in the x-y plane: a front surface on the front side of the wafer, and a back surface on the backside opposite to the front side of the wafer. The x- and y-directions are two orthogonal directions in the wafer plane: x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to both the x- and y- axes. As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some embodiments, peripheral circuit <NUM> is configured to control and sense the 3D memory device <NUM>. Peripheral circuit <NUM> can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device <NUM> including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits <NUM> can include transistors formed "on" substrate <NUM>, in which the entirety or part of the transistors are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate <NUM> as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments. It is understood that in some examples, peripheral circuit <NUM> may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM). In some embodiments, peripheral circuits <NUM> include one or more power lines to provide power (e.g., voltages) to peripheral circuits <NUM>.

In some embodiments, first semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer (not shown) above peripheral circuits <NUM> to transfer electrical signals to and from peripheral circuits <NUM>. The interconnect layer can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and VIA contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown in <FIG>, first semiconductor structure <NUM> of 3D memory device <NUM> can further include a bonding layer <NUM> at bonding interface <NUM> and above the interconnect layer and peripheral circuits <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can also include a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding. Bonding contacts <NUM> are in contact with bonding contacts <NUM> at bonding interface <NUM>, according to some embodiments.

As described below in detail, second semiconductor structure <NUM> can be bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. In some embodiments, bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer (not shown) above bonding layer <NUM> to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can include an array of channel structures <NUM> functioning as the array of NAND memory strings. As shown in <FIG>, each channel structure <NUM> can extend vertically through a plurality of pairs each including a conductive layer <NUM> and a dielectric layer <NUM>. The interleaved conductive layers <NUM> and dielectric layers <NUM> are part of a memory stack <NUM>. The number of the pairs of conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or more) determines the number of memory cells in 3D memory device <NUM>. It is understood that in some examples, memory stack <NUM> may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers <NUM> and dielectric layers <NUM> in each memory deck can be the same or different.

Memory stack <NUM> can include a plurality of interleaved conductive layers <NUM> and dielectric layers <NUM>. Conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductive layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductive layers <NUM> on both sides. Conductive layers <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer <NUM> can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer <NUM> can extend laterally as a word line, ending at one or more staircase structures of memory stack <NUM>. In some embodiments, the uppermost condcutive layer <NUM> functions as the SSG for controlling the source of the NAND memory string. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can also include a first semiconductor layer <NUM> above memory stack <NUM> and a second semiconductor layer <NUM> above and in contact with first semiconductor layer <NUM>. The dopant types in each semiconductor layer <NUM> and <NUM> may vary in different examples. Semiconductor layers <NUM> and <NUM> may be viewed as a single smeicondutor layer when semiconductor layers <NUM> and <NUM> have the same type of dopants. It is understood that the number of semiconductor layers may be different in other examples and is not limited to the example shown in <FIG>.

In some embodiments, each channel structure <NUM> includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel <NUM>) and a composite dielectric layer (e.g., as a memory film <NUM>). In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of channel structure <NUM> can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel <NUM>, the tunneling layer, storage layer, and blocking layer of memory film <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film <NUM> can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure <NUM> further includes a channel plug <NUM> in the bottom portion (e.g., at the lower end) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the z-direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the z-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Channel plug <NUM> can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug <NUM> functions as the drain of the NAND memory string.

As shown in <FIG>, each channel structure <NUM> can extend vertically through interleaved conductive layers <NUM> and dielectric layers <NUM> of memory stack <NUM> and first semiconductor layer <NUM>. In some embodiments, first semiconductor layer <NUM> surrounds part of channel structure <NUM> and is in contact with semiconductor channel <NUM> including polysilicon. That is, memory film <NUM> is disconnected at part of channel structure <NUM> that abuts first semiconductor layer <NUM>, exposing semiconductor channel <NUM> to be in contact with the surrounding first semiconductor layer <NUM>, according to some embodiments. In some embodiments, each channel structure <NUM> can extend vertically further into second semiconductor layer <NUM>. It is understood that the structure of the top portion of channel structure <NUM> and its relative position with respect to semiconductor layer <NUM> and <NUM> are not limited to the example in <FIG> and may vary in other examples.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can further include insulating structures <NUM> each extending vertically through interleaved conductive layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. Each insulating structure <NUM> can also extend laterally to separate channel structures <NUM> into a plurality of blocks. That is, memory stack <NUM> can be divided into a plurality of memory blocks by insulating structures <NUM>, such that the array of channel structures <NUM> can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure <NUM> does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers <NUM> (including word lines), according to some embodiments. In some embodiments, each insulating structure <NUM> includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure <NUM> may be filled with silicon oxide.

Instead of having front side source contacts, 3D memory device <NUM> can include backside source contacts <NUM> above memory stack <NUM> and in contact with second semiconductor layer <NUM>. Backside source contact <NUM> may be one example of backside source contact <NUM> in <FIG>. Source contact <NUM> and memory stack <NUM> (and insulating structure <NUM> therethrough) can be disposed on opposites sides of semiconductor layer <NUM> (a thinned substrate) and thus, viewed as a "backside" source contact. In some embodiments, source contact <NUM> extends further into second semiconductor layer <NUM> and is electrically connected to semiconductor channel <NUM> of channel structure <NUM> through semiconductor layers <NUM> and <NUM>. It is understood that the depth that source contact <NUM> extends into second semiconductor layer <NUM> may vary in different examples. In some embodiments in which second semiconductor layer <NUM> is an N-well, source contact <NUM> is also known as a backside "N-well pick up. " Source contacts <NUM> can include any suitable types of contacts. In some embodiments, source contacts <NUM> include a VIA contact (e.g., as backside source contact <NUM> in <FIG>). In some embodiments, source contacts <NUM> include a wall-shaped contact extending laterally. Source contact <NUM> can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown in <FIG>, memory device <NUM> can further include a BEOL backside3D interconnect layer <NUM> above and in contact with source contact <NUM> for pad-out, e.g., transferring electrical signals between 3D memory device <NUM> and external circuits. Backside interconnect layer <NUM> may also include the examples of backside interconnect structures described above in <FIG>. In some embodiments, backside interconnect layer <NUM> includes one or more ILD layers <NUM> on second semiconductor layer <NUM> and a redistribution layer <NUM> on ILD layers <NUM>. The upper end of source contact <NUM> is flush with the top surface of ILD layers <NUM> and the bottom surface of redistribution layer <NUM>, and source contact <NUM> extends vertically through ILD layers <NUM> into second semiconductor layer <NUM>, according to some embodiments. ILD layers <NUM> in backside interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Redistribution layer <NUM> in backside interconnect layer <NUM> can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer <NUM> includes Al. Although not shown in <FIG>, it is understood that redistribution layer <NUM> can be patterned to form various types of backside interconnect structures described herein, such as source line mesh <NUM>, power line mesh <NUM>, and SSG lines <NUM> in <FIG>. In one example, source contacts <NUM> may be below and in contact with source line mesh <NUM> in redistribution layer <NUM>. In some embodiments, backside interconnect layer <NUM> further includes a passivation layer <NUM> as the outmost layer for passivation and protection of 3D memory device <NUM>. Part of redistribution layer <NUM> can be exposed from passivation layer <NUM> as bonding pads <NUM>. That is, backside interconnect layer <NUM> of 3D memory device <NUM> can also include bonding pads <NUM> for wire bonding and/or bonding with an interposer. Although not shown in <FIG>, bonding pads <NUM> may be part of the backside interconnect structures as well in some examples.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> further includes contacts <NUM> and <NUM> through second semiconductor layer <NUM>. As second semiconductor layer <NUM> may be a thinned substrate, contacts <NUM> and <NUM> are TSCs, according to some embodiments. Contact <NUM> may be one example of contact <NUM> or <NUM> in <FIG> and <FIG>. In some embodiments, contact <NUM> extends through second semiconductor layer <NUM> and ILD layers <NUM> to be in contact with redistribution layer <NUM> (e.g., including source line mesh <NUM> and power line mesh <NUM>). For example, the source of NAND memory string may be electrically connected to contact <NUM> (e.g., as contact <NUM> in <FIG>) through semiconductor layers <NUM> and <NUM>, source contact <NUM>, and redistribution layer <NUM> (e.g., having source line mesh <NUM> in <FIG>). That is, contacts <NUM> (either as contacts <NUM> or <NUM>) can be below and in contact with source line mesh <NUM> or power line mesh <NUM>, respectively, in redistribution layer <NUM>. Although not shown in <FIG>, as one example of contact <NUM> in <FIG>, 3D memory device <NUM> may also include contacts (e.g., one example of contacts <NUM> in <FIG>) extending further into memory stack <NUM> to be in contact with one of conductive layers <NUM> (i.e., the SSG) of memory stack <NUM>. The contacts (e.g., as contacts <NUM> in <FIG>) can be below and in contact with SSG lines <NUM> in redistribution layer <NUM>.

In some embodiments, contact <NUM> extends through second semiconductor layer <NUM> and ILD layers <NUM> to be in contact with bonding pad <NUM>. Contacts <NUM> and <NUM> each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact <NUM> further includes a spacer (e.g., a dielectric layer) to electrically insulate contact <NUM> from second semiconductor layer <NUM>.

In some embodiments, 3D memory device <NUM> further includes peripheral contacts <NUM> and <NUM> each extending vertically to second semiconductor layer <NUM> outside of memory stack <NUM>. Each peripheral contact <NUM> or <NUM> can have a depth greater than the depth of memory stack <NUM> to extend vertically from bonding layer <NUM> to second semiconductor layer <NUM> in a peripheral region corresponding to, for example, peripheral region <NUM> and staircase region <NUM> in <FIG> or the peripheral regions of core array regions 206A and 206B in which contacts <NUM> are disposed. In some embodiments, peripheral contact <NUM> is below and in contact with contact <NUM>, such that source line mesh <NUM> or power line mesh <NUM> is electrically connected to peripheral circuit <NUM> in first semiconductor structure <NUM>. In one example, the source of NAND memory string may be electrically connected to the part of peripheral circuit <NUM> for controlling/sensing the source of NAND memory string through redistribution layer <NUM> (e.g., including source line mesh <NUM>), contact <NUM> (e.g., as contact <NUM>), and peripheral contact <NUM>. In another example, the power supply may be electrically connected to the power line of peripheral circuit <NUM> to provide power to 3D memory device <NUM> through redistribution layer <NUM> (e.g., including power line mesh <NUM>), contact <NUM> (e.g., as contact <NUM>), and peripheral contact <NUM> In some embodiments, peripheral contact <NUM> is below and in contact with contact <NUM>, such that peripheral circuit <NUM> in first semiconductor structure <NUM> is electrically connected to bonding pad <NUM> for pad-out through at least contact <NUM> and peripheral contact <NUM>. Peripheral contacts <NUM> and <NUM> each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown in <FIG>, 3D memory device <NUM> also includes a variety of local contacts (also known as "C1") as part of the interconnect structure, which are in contact with a structure in memory stack <NUM> directly. In some embodiments, the local contacts include channel local contacts <NUM> each below and in contact with the lower end of a respective channel structure <NUM>. Each channel local contact <NUM> can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts <NUM> each below and in contact with a respective conductive layer <NUM> (including a word line) at the staircase structure of memory stack <NUM> for word line fan-out. Local contacts, such as channel local contacts <NUM> and word line local contacts <NUM>, can be electrically connected to peripheral circuits <NUM> of first semiconductor structure <NUM> through at least bonding layers <NUM> and <NUM>. Local contacts, such as channel local contacts <NUM> and word line local contacts <NUM>, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

<FIG> illustrates a plan view of a cross-section of yet another exemplary 3D memory device <NUM> with backside interconnect structures, according to some examples not forming part of the invention. 3D memory device <NUM> may be one example of 3D memory device <NUM> after flip-chip bonding, and <FIG> shows one example of the backside of 3D memory device <NUM> after flip-chip bonding. As shown in <FIG>, the memory stack of 3D memory device <NUM> includes two core array regions 406A and 406B having channel structures <NUM> therein and a staircase region <NUM> between core array regions 406A and 406B in the x-direction (e.g., the word line direction) in the plan view, according to some embodiments. In the y-direction (e.g., the bit line direction), <FIG> shows backside interconnect structures in one block <NUM> of 3D memory device <NUM>, which may be repeated in any suitable number of times in multiple blocks.

In some embodiments, 3D memory device <NUM> includes a source line mesh <NUM> in the plan view. In some embodiments, source line mesh <NUM> is in core array regions 406A and 406B and staircase region <NUM>. As shown in <FIG>, source line mesh <NUM> includes a plurality of parallel source lines <NUM> each extending laterally in the x-direction (e.g., the word line direction) across staircase region <NUM> and core array regions 406A and 406B in the plan view, similar to tooth source lines <NUM> of source line mesh <NUM> in <FIG>, according to some embodiments. Different from source line mesh <NUM> having a single shaft source line <NUM> in <FIG> and <FIG>, source line mesh <NUM> may also include a plurality of parallel source lines <NUM> each extending laterally in the y-direction (e.g., the bit line direction) in the plan view. Parallel source lines <NUM> can be disposed in core array regions 406A and 406B and in staircase region <NUM>, as shown in <FIG>. It is understood that in some examples, source lines <NUM> may not be disposed in staircase region <NUM>, but only in core array regions 406A and 406B.

3D memory device <NUM> can also include backside source contacts <NUM> (e.g., in the form of VIA contacts) in core array regions 406A and 406B, but not in staircase region <NUM>. For example, backside source contacts <NUM> may be evenly distributed in core array region 406A or 406B. As shown in <FIG>, each channel structure <NUM> is below and aligned laterally with a respective one of backside source contacts <NUM>, according to some embodiments. That is, each channel structure <NUM> can be overlapped with a respective backside source contact <NUM> directly on top of channel structure <NUM>, thereby reducing the resistance between the source of the NAND memory string and backside source contact <NUM>. In some embodiments, since channel structures <NUM> are arranged in an array having rows and columns, backside source contacts are also arranged in an array having rows and columns. Each source line <NUM> or <NUM> can be in contact with each of backside source contacts <NUM> in a row or a column in the array in the plan view. In some embodiments, each source line <NUM> extending in the y-direction can be in contact with each of backside source contacts <NUM> in a column. It is understood that in some examples, each source line <NUM> extending in the x-direction may be in contact with each of backside source contacts <NUM> in a row. In some embodiments, each source line <NUM> or <NUM> is in contact with each of backside source contacts <NUM> in two adjacent rows or columns in the array in the plan view. For example, as shown in <FIG>, each source line <NUM> extending in the y-direction may be in contact with each of backside source contacts <NUM> in two adjacent columns. Although not shown, similarly, each source line <NUM> extending in the x-direction may be in contact with each of backside source contacts <NUM> in two adjacent rows in other examples.

3D memory device <NUM> can further include contacts <NUM>, such as TSCs. In some embodiments, contacts <NUM> are distributed below and in contact with source line mesh <NUM> in staircase region <NUM> and part of core array regions 406A and 406B. As contacts <NUM> may be TSCs extending through the silicon substrate, contacts <NUM> are distributed below and in contact with the peripheral portion of source line mesh <NUM> (including the part in staircase region <NUM>) to avoid overlapping with channel structures <NUM> in the center portion of source line mesh <NUM> in core array regions 406A and 406B, according to some embodiments. For example, as shown in <FIG>, contacts <NUM> may be distributed below and in contact with outermost source lines <NUM> and <NUM> in core array regions 406A and 406B. Contacts <NUM> may also be distributed below and in contact with source line <NUM> in staircase region <NUM>.

As described below in detail, each backside source contact <NUM> can be electrically connected to the source of a respective NAND memory strings, and source line mesh <NUM> electrically connects each backside source contact <NUM> and is in turn, electrically connected to the sources of the NAND memory strings. Similarly, each contact <NUM> can be electrically connected the peripheral circuits of 3D memory device <NUM>, and source line mesh <NUM> electrically connects each contact <NUM> and is in turn, electrically connected to the peripheral circuits of 3D memory device <NUM>. As a result, the peripheral circuits can be electrically connected to the sources of the NAND memory strings to control and/or sense the sources through the metal routing including contacts <NUM>, source line mesh <NUM>, and backside source contacts <NUM> on the backside of 3D memory device <NUM>. Compared with the examples in <FIG>, the layout of contacts <NUM>, source line mesh <NUM>, and backside source contacts <NUM>, for example, the array of backside source contacts <NUM> corresponding to the array of channel structures <NUM>, and source lines <NUM> each contacting backside source contacts <NUM> in two adjacent columns in core array regions 406A and 406B, can further reduce the overall resistance of the metal routing.

<FIG> illustrates a side view of a cross-section of another exemplary 3D memory device <NUM> with backside interconnect structures, according to some embodiments of the present disclosure. 3D memory device <NUM> may be one example of 3D memory device <NUM> in <FIG>. 3D memory <NUM> is similar to 3D memory device <NUM> in <FIG> except for the arrangement of source contacts <NUM>. As shown in <FIG>, each channel structure <NUM> is below and aligned laterally (e.g., in both x- and y-directions) with a respective source contact <NUM> (e.g., one example of backside source contact <NUM> in <FIG>), which is in contact with semiconductor layer <NUM>. It is understood that the details of other same structures in both 3D memory devices <NUM> and <NUM> are not repeated for ease of description.

<FIG> illustrate a fabrication process for forming an exemplary 3D memory device with backside interconnect structures, according to some embodiments of the present disclosure. <FIG> illustrates a flowchart of a method <NUM> for forming an exemplary 3D memory device with backside interconnect structures, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory devices <NUM>, <NUM>, <NUM>, and <NUM> depicted in <FIG> and <FIG>. <FIG> and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in <FIG>, peripheral circuits <NUM> having a plurality of transistors are formed on a first silicon substrate <NUM> using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of channel structures each extending vertically through a memory stack are formed on a front side of a second substrate. In some embodiments, the memory stack includes two core array regions having the channel structures and a staircase region between the two core array regions in a first lateral direction in a plan view. As illustrated in <FIG>, an array of channel structures <NUM> each extending vertically through a memory stack are formed on the front side of a second silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the channel structures are above the peripheral circuit. The bonding can include hybrid bonding. As illustrated in <FIG>, second silicon substrate <NUM> and components formed thereon (e.g., channel structures <NUM>) are flipped upside down and bonded with first silicon substrate <NUM> and components formed thereon (e.g., peripheral circuits <NUM>) facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> between silicon substrates <NUM> and <NUM>, according to some embodiments.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the second substrate is thinned. The thinning is performed from the backside of the second substrate. As illustrated in <FIG>, second silicon substrate <NUM> (shown in <FIG>) is thinned from the backside to become a semiconductor layer <NUM> (i.e., the thinned second silicon substrate <NUM>) using CMP, grinding, dry etching, and/or wet etching.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of contacts are formed through the thinned second substrate, and a plurality of source contacts are formed in contact with the thinned second substrate. The contacts and source contacts are formed from the backside of the thinned second substrate. In some embodiments, each of the channel structures is below and aligned laterally with a respective one of the source contacts. In some embodiments, the source contacts are arranged in an array having rows and columns. As illustrated in <FIG>, backside source contacts <NUM> are formed from the backside of semiconductor layer <NUM> and in contact with semiconductor layer <NUM>. In some embodiments, each channel structure <NUM> is below and aligned laterally with a respective backside source contact <NUM>. A plurality of TSCs <NUM>, <NUM>, and <NUM> can be formed from the backside of semiconductor layer <NUM> through semiconductor layer <NUM>. In some embodiments, TSCs <NUM> extend further into the memory stack to be in contact with the SSG in the memory stack.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a source line mesh is formed on the backside of the thinned second substrate, such that the source line mesh is above and in contact with the plurality of source contacts and a first set of the plurality of contacts. In some embodiments, the source line mesh includes a plurality of parallel source lines each extending laterally in the plan view. In some embodiments, source line mesh is above and in contact with each of the source contacts. In some embodiments, each of the source lines is in contact with each of the source contacts in a row or a column in the array in the plan view. In some embodiments, each of the source lines is in contact with each of the source contacts in two adjacent rows or columns in the array in the plan view. As illustrated in <FIG>, a source line mesh <NUM> is formed on the backside of semiconductor layer <NUM>, such that source line mesh <NUM> is above and in contact with backside source contracts <NUM> as well as TSCs <NUM>. The layout of source line mesh <NUM>, backside source contacts <NUM>, and TSCs <NUM> may vary in different examples, for example, as in the examples shown in <FIG> and <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of SSG lines are formed on the backside of the thinned second substrate, such that the SSG lines are above and in contact with a second set of the plurality of contacts. In some embodiments, each of the SSG lines extends in the first lateral direction across the two core array regions and the staircase region, and the second set of the contacts are distributed in the core array regions in the plan view. In some embodiments, the SSG lines are evenly distributed in parallel in a second lateral direction perpendicular to the first lateral direction in the plan view. As illustrated in <FIG>, SSG lines <NUM> are formed on the backside of semiconductor layer <NUM>, such that SSG lines <NUM> are above and in contact with TSCs <NUM>. The layout of SSG lines <NUM> and TSCs <NUM> may vary in different examples, for example, as in the example shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a power line mesh is formed on the backside of the thinned second substrate, such that the power line mesh is above and in contact with a third set of the plurality of contacts. In some embodiments, the third set of the contacts are distributed in at least one of the staircase region or a peripheral region outside of the memory array in the plan view. As illustrated in <FIG>, a power line mesh <NUM> is formed on the backside of semiconductor layer <NUM>, such that power line mesh <NUM> is above and in contact with TSCs <NUM>. The layout of power line mesh <NUM> and TSCs <NUM> may vary in different examples, for example, as in the example shown in <FIG> and <FIG>. It is understood that although operations <NUM>, <NUM>, and <NUM> are described above as three sequential operations, operations <NUM>, <NUM>, and <NUM> may be performed in the same fabrication processes. For example, one or more of source line mesh <NUM>, power line mesh <NUM>, and SSG lines <NUM> may be patterned and formed in the same fabrication processes.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional, 3D, memory device (<NUM>), comprising:
a substrate;
a memory stack comprising interleaved conductive layers and dielectric layers above the substrate;
a plurality of channel structures each extending vertically through the memory stack;
a semiconductor layer above and in contact with the plurality of channel structures;
a plurality of source contacts (<NUM>) above the memory stack and in contact with the semiconductor layer; and
a backside interconnect layer above the semiconductor layer comprising a source line mesh (<NUM>) in a plan view, wherein the plurality of source contacts (<NUM>) are distributed below and in contact with the source line mesh (<NUM>), characterised in that the three-dimensional memory device further comprises a plurality of contacts (<NUM>) through the semiconductor layer, wherein
a first set (<NUM>) of the plurality of contacts are distributed below and in contact with the source line mesh (<NUM>);
wherein the memory stack comprises two core array regions (206A, 206B) having the channel structures and a staircase region (<NUM>) between the two core array regions (206A, 206B) in a first lateral direction in the plan view; and
wherein the backside interconnect layer further comprises a power line mesh (<NUM>) in the plan view, and a third set (<NUM>) of the plurality of contacts are distributed below and in contact with the power line mesh (<NUM>), wherein the third set (<NUM>) of the contacts are distributed in at least one of the staircase region (<NUM>) or a peripheral region (<NUM>) outside of the memory array in the plan view.