Patent Description:
<CIT> describes a dielectric wafer which has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode. <CIT> describes a capacitor structure, comprising a substrate, a TSV, a dielectric layer and a doped region. The substrate includes a first surface and a second surface, which are disposed oppositely to each other. The TSV penetrates through the first surface and the second surface. The dielectric layer is disposed in the substrate and encompasses the TSV. The doped region is disposed between the dielectric layer and the substrate.

<CIT> describes a carrier for a semiconductor component having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

<CIT> describes a device comprising a substrate, an integrated circuit interconnection part arranged above a first face of the substrate, at least one capacitor passing through said substrate having a first electrode having a first contact face electrically coupled to a first electrically conductive zone disposed above a second face of the substrate and a second electrode electrically coupled to said interconnection part, at least one electrically conductive connection passing through the substrate having on the one hand a first contact face electrically coupled to a second electrically conductive zone disposed above said second face of the substrate and on the other hand a part electrically coupled to said interconnection part, said two first contact faces being located in the same plane.

The invention is set forth in the independent claims. Embodiments of the invention are described in the dependent claims.

According to an embodiment of the invention an integrated circuit includes a capacitor, the integrated circuit comprising a semiconductor layer; a first through-body via, TBV, disposed within a first through-hole formed in a semiconductor layer, the first through-hole extending through the semiconductor layer from a first surface thereof to a second surface thereof; an isolation layer disposed in the first through-hole between a first dielectric layer and the semiconductor layer and conformal to a sidewall of the first trough-hole; the first dielectric layer disposed between the first TBV and the isolation layer; wherein a second electrode of the capacitor is provided by a conductive layer disposed between the isolation layer and the first dielectric layer; a second TBV disposed within a second through-hole formed in the semiconductor layer adjacent to the first TBV, wherein the second TBV is electrically connected with the first TBV and electrically isolated from the semiconductor layer by an isolation layer disposed in the second through-hole on the semiconductor layer and conformal to a sidewall of the second trough-hole, a first electrode of the capacitor is provided by the first TBV, and an electrical connection to the first electrode of the capacitor and an electrical connection to the second electrode of the capacitor are provided on the front side or the back side of the integrated circuit by a contact with the second TBV and the conductive layer, respectively, wherein the first trough-hole and the second trough-hole have the shape of a conical frustum.

According to an embodiment of the invention the semiconductor layer is either a bulk substrate in which the first TBV is disposed and the bulk substrate is doped to provide the low-resistance portion that provides the second electrode of the capacitor or the semiconductor layer is a bulk layer of a multilayer substrate in which the first TBV is disposed; and the multilayer substrate is doped to provide the low-resistance portion that provides the second electrode of the capacitor, wherein the multilayer substrate is a semiconductor-on-insulator, SOI, structure; and the semiconductor layer is the semiconductor layer of the SOI structure or the semiconductor layer is a bulk substrate in which the first TBV is disposed; and the second electrode of the capacitor is provided by the conductive layer or the semiconductor layer is a bulk layer of a multilayer substrate in which the first TBV is disposed; and the second electrode of the capacitor is provided by the conductive layer, wherein the multilayer substrate is a semiconductor-on-insulator, SOI, structure; and the semiconductor layer is the semiconductor layer of the SOI structure. According to an embodiment of the invention at least one of: the integrated circuit further comprises a p+ tap portion formed in the semiconductor layer, and a metal interconnect disposed over the first or second surface of the semiconductor layer and electrically connected with the second TBV and the p+ tap portion.

According to an embodiment of the invention the integrated circuit is configured to serve as a battery that is able to at least one of: charge itself using energy harvested from an external source; discharge itself by emitting a high-Voltage pulse; and recharge itself after discharge.

According to an embodiment of the invention the integrated circuit has a front side and a back side; the first electrode is accessible by a first front side contact aligned with the first TBV; and the second electrode is accessible by a second front side contact aligned with the second TBV.

According to an embodiment of the invention the second through-hole extends through the semiconductor layer from a first surface thereof to a second surface thereof, wherein either the first dielectric layer is disposed between the second TBV and the semiconductor layer and is conformal to a sidewall of the second through-hole or the integrated circuit includes a metal interconnect disposed over the first or second surface of the semiconductor layer and electrically connected with the second TBV, wherein the second through-hole lands on the metal interconnect.

According to an embodiment of the invention, the first dielectric layer has a thickness in the range of about <NUM>-<NUM> and includes at least one of hafnium oxide and polyimide.

According to an embodiment of the invention, the first TBV has a width in the range of about <NUM>-<NUM>.

According to an embodiment of the invention, the first TBV has a length in the range of about <NUM>-<NUM>.

According to an embodiment of the invention, the first TBV has a length-to-Width aspect ratio of <NUM>:<NUM> or greater.

According to an embodiment of the invention, the first TBV is of at least one of cylindrical and conical frustum shape.

According to an embodiment of the invention, the integrated circuit further includes at least one of a p-well, an n-well, and a deep n-well formed in the semiconductor layer.

According to an embodiment of the invention, a method of forming an integrated circuit including a capacitor comprises: forming a first through-body via, TBV, in a first through-hole in a semiconductor layer, the first through-hole extending through the semiconductor layer from a first surface thereof to a second surface thereof; forming an isolation layer in the first through-hole between a first dielectric layer and the semiconductor layer and conformal to a sidewall of the first trough-hole; forming the first dielectric layer between the first TBV and the isolation layer; providing a second electrode of the capacitor by forming a conductive layer between the isolation layer and the first dielectric layer; forming a second TBV within a second through-hole formed in the semiconductor layer adjacent to the first TBV, wherein the second TBV is electrically connected with the first TBV and electrically isolated from the semiconductor layer by an isolation layer disposed in the second through-hole on the semiconductor layer and conformal to a sidewall of the second trough-hole, wherein a first electrode of the capacitor is provided by the first TBV; and providing an electrical connection to the first electrode of the capacitor and an electrical connection to the second electrode of the capacitor on the front side or the back side of the integrated circuit by a contact with the second TBV and the conductive layer, respectively, wherein the first trough-hole and the second trough-hole have the shape of a conical frustum.

According to an embodiment of the invention, the semiconductor layer is a bulk substrate in which the first TBV is disposed, and the bulk substrate is doped to provide the low-resistance portion that provides the second electrode of the capacitor;.

According to an embodiment of the invention, the multilayer substrate is a semiconductor-on-insulator, SOI, structure; and the semiconductor layer (<NUM>) is the semiconductor layer of the SOI structure.

According to an embodiment of the invention, the first dielectric layer is conformal to a sidewall of the first through-hole; the method further comprises: forming an isolation layer within the first through-hole between the first dielectric layer and the semiconductor layer and conformal to a sidewall of the first through-hole, wherein:.

According to an embodiment of the invention, the method further comprises forming a p+ tap portion in the semiconductor layer, and forming a metal interconnect over the first or second surface of the semiconductor layer and electrically connected with the second TBV and the p+ tap portion.

According to an embodiment of the invention, the integrated circuit has a front side and a back side; the first electrode is accessible by a first front side contact aligned with the first TBV; and the second electrode is accessible by a second front side contact aligned with the second TBV.

According to an embodiment of the invention, the second through-hole extends through the semiconductor layer from a first surface thereof to a second surface thereof and the method includes forming a metal interconnect over the first or second surface of the semiconductor layer and electrically connected with the second TBV, wherein the first through-hole lands on the metal interconnect.

According to an embodiment of the invention, the method further comprises forming a second dielectric layer over the first or second surface of the semiconductor layer, wherein: the second dielectric layer has a thickness in the range of about <NUM>-<NUM>; and the first through-hole lands on the second dielectric layer.

According to an embodiment of the invention, the method further comprises that the first dielectric layer has a thickness in the range of about <NUM>-<NUM> and includes at least one of hafnium oxide and polyimide.

According to an embodiment of the invention, the method further comprises that the first TBV has a width in the range of about <NUM>-<NUM>.

According to an embodiment of the invention, the method further comprises that the first TBV has a length in the range of about <NUM>-<NUM>.

According to an embodiment of the invention, the method further comprises that the first TBV has a length-to-width aspect ratio of <NUM> : <NUM> or greater.

According to an embodiment of the invention, the method further comprises that the first TBV is of at least one of cylindrical and conical frustum shape.

According to an embodiment of the invention, the method further comprises forming at least one of a p-Well, an n-well, and a deep n-well in the semiconductor layer.

The following are examples not forming part of the invention:
According to an example an integrated circuit includes a capacitor, the integrated circuit including: a silicon layer; a first copper through-body Via (TBV) disposed within the silicon layer and providing a first electrode of the capacitor; and a first dielectric layer disposed between the first copper TBV and the silicon layer; wherein a second electrode of the capacitor is provided by either: a low-resistance portion of the silicon layer proximate the first copper TBV; or a conductive layer disposed between the silicon layer and the first copper TBV.

According to an example the silicon layer is a bulk substrate in which the first copper TBV is disposed; and the bulk substrate is doped to provide the low-resistance portion that provides the second electrode of the capacitor.

According to an example the silicon layer is a bulk layer of a multilayer substrate in which the first copper TBV is disposed; and the multilayer substrate is doped to provide the low-resistance portion that provides the second electrode of the capacitor, and (<NUM>)the multilayer substrate is a semiconductor-on-insulator (SOI) structure; and the silicon layer is the semiconductor layer of the SOI structure.

According to an example the silicon layer is a bulk substrate in which the first copper TBV is disposed; and the second electrode of the capacitor is provided by the conductive layer.

According to an example the silicon layer is a bulk layer of a multilayer substrate in Which the first copper TBV is disposed; and the second electrode of the capacitor is provided by the conductive layer and the multilayer substrate is a semiconductor-on-insulator (SOI) structure; and the silicon layer is the semiconductor layer of the SOI structure.

According to an example the first TBV is disposed Within a first through-hole formed in the silicon layer, the first through-hole extending through the silicon layer from a first surface thereof to a second surface thereof and at least one of the first dielectric layer is conformal to a sidewall of the first through-hole, the integrated circuit further includes a metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the first copper TBV, wherein the first through-hole lands on the metal interconnect, the integrated circuit further includes a metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the conductive layer, wherein the first through-hole lands on the metal interconnect, the integrated circuit further includes an isolation layer disposed within the first through-hole between the first dielectric layer and the silicon layer and conformal to a sidewall of the first through-hole, wherein: the conductive layer is disposed within the first through-hole between the first dielectric layer and the isolation layer and conformal to the isolation layer; and the first dielectric layer is conformal to the conductive layer, the integrated circuit further includes a second dielectric layer disposed over the first or second surface of the silicon layer, wherein: the second dielectric layer has a thickness in the range of about <NUM>-<NUM>; and the first through-hole lands on the second dielectric layer, the integrated circuit further includes: a first metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the conductive layer; and a second metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the first TBV, wherein the second metal interconnect is electrically insulated from the conductive layer.

According to an example the integrated circuit further includes a second copper TBV disposed within the silicon layer adjacent to the first copper TBV and at least one of the integrated circuit further includes: a p+ tap portion formed in the silicon layer; and a metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the second copper TBV and the p+ tap portion, the second copper TBV is electrically connected with the first copper TBV and electrically isolated from the silicon layer; and the second electrode of the capacitor is provided by the conductive layer, the integrated circuit has a front side and a back side; the first electrode is accessible by a first front side contact aligned with the first copper TBV; and the second electrode is accessible by a second front side contact aligned with the second copper TBV, the second copper TBV is disposed within a second through-hole formed in the silicon layer, the second through-hole extending through the silicon layer from a first surface thereof to a second surface thereof, wherein either the first dielectric layer is disposed between the second copper TBV and the silicon layer and is conformal to a sidewall of the second through-hole and or the integrated circuit includes a metal interconnect disposed over the first or second surface of the silicon layer and electrically connected with the second copper TBV, wherein the second through-hole lands on the metal interconnect.

According to an example the first dielectric layer has a thickness in the range of about <NUM>-<NUM> and includes at least one of hafnium oxide (HfOz) and polyimide.

According to an example the silicon layer is p-doped silicon having a resistivity in the range of about <NUM>-<NUM>Ω cm.

According to an example the integrated circuit further includes at least one of a p-well, an n-well, and a deep n-well formed in the semiconductor layer and further includes at least one of: a p-type metal-oxide-semiconductor (PMOS) device; and an n-type metal-oxide-semiconductor (NMOS) device.

According to an example the integrated circuit is configured to serve as a battery that is able to at least one of: charge itself using energy harvested from an external source; discharge itself by emitting a high-voltage pulse; and recharge itself after discharge.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines, right angles, etc., and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV serves as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer serves as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer in which the TBV is formed serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer comprises a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) are provided just along the sidewalls local to the TBV, for example, by doping the semiconductor material in those selected location(s). In accordance with some other embodiments, rather than utilizing a low-resistivity semiconductor material for one of the electrodes, the second electrode of the TBV capacitor can be realized by providing a conductive layer between the semiconductor layer and the dielectric layer, resulting in a metal-insulator-metal (MIM)-type of capacitive structure. In some such cases, a dual-TBV capacitor configuration is provided, wherein one of a pair of neighboring TBVs is a part of the MIM-type capacitive structure and provides front side access to the cathode, and the other TBV of the pair is electrically connected with the conductive material of the first TBV and provides front side access to the anode of the capacitor. Back side access is available as well, in some such embodiments. Numerous configurations and variations, as well as forming methods, will be apparent in light of this disclosure.

The capacitors and batteries of modern electronics typically involve off-chip elements that occupy significant real estate or on-chip elements that can provide only very small capacitance. Modern off-chip capacitors are generally too large in size for use in compact mobile computing devices, such as smartphones. Furthermore, although through-silicon vias (TSVs) can be connected with front-end circuits and used to pass signals between stacked dies, it is normally desirable to minimize their capacitance, which otherwise would introduce significant signal delay.

Thus, and in accordance with some embodiments of the present disclosure, techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may be configured to serve as one of the conductor bodies of a TBV capacitor (e.g., anode), and the dielectric layer may be configured to serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer may be formed from a low-resistivity material and thus may serve as the other of the conductor bodies of the TBV capacitor (e.g., cathode). In some cases, the low-resistivity material may be, for example, one or more doped areas of a bulk substrate (e.g., dopant provided along sidewalls of a TBV). In other cases, the low-resistivity material may be doped regions of a semiconductor layer of a semiconductor-on-insulator (SOI) structure or some other substrate layer in which the TBV is formed. In still other embodiments, use of such low-resistivity semiconductor substrate regions can be avoided, for instance, by providing a conductive layer between the substrate and the dielectric layer to serve as the other of the conductor bodies of the TBV capacitor (e.g., cathode), providing a metal-insulator-metal (MIM)-type of capacitive structure, of which the TBV is a component. Various configurations can be implemented to provide either front side or back side access to the cathode and anode of a TBV capacitor provided as described herein, as will be appreciated in light of this disclosure.

As will be further appreciated in light of this disclosure, the three-dimensional geometry of high-aspect ratio TBV capacitors configured as described herein may provide a conductive surface area that is much larger than that offered by traditional metal-insulator-metal (MIM) capacitors and other typical two-dimensional on-chip capacitors, in accordance with some embodiments. When formed by interfacing a TBV with surrounding low-resistivity semiconductor material through a dielectric layer of sufficiently high dielectric constant (κ) and sufficiently low thickness, the resulting TBV capacitor(s) can contribute very large on-chip capacitance. For instance, in some cases, a TBV capacitor configured as described herein may provide capacitance that is greater (e.g., about <NUM>×, about <NUM>×, about <NUM>× or greater) than that of a typical MIM capacitor. In accordance with some embodiments, the amount of on-chip capacitance provided can be tuned, as desired for a given target application or end-use, by increasing the thickness of the surrounding semiconductor layer (e.g., doped substrate region), reducing the thickness of the dielectric layer, forming the dielectric layer from a dielectric material of higher dielectric constant (κ), stacking multiple chips together, or a combination of any of these.

In accordance with some embodiments, the disclosed techniques can be used, for example, for monolithic on-chip integration of high-capacitance components and may be generally compatible with existing complementary metal-oxide-semiconductor (CMOS) fabrication processes. In some instances, the disclosed techniques can be used to provide low-cost NAND and system-on-chip (SoC) integration of on-chip capacitance. In some cases, on-chip TBV-based capacitance may be provided for use in storing electricity in a battery design. In some instances, such an on-chip battery can be configured to store energy harvested, for example, from solar energy, thermal energy, or any other suitable source. In some other cases, on-chip TBV-based capacitance may be provided for use in generating and discharging a high-voltage pulse in a charge-pump circuit design. In some instances, on-chip TBV-based capacitance provided as described herein can be recharged after discharge (e.g., when used in a battery mode). In some cases, the disclosed techniques can be used, for example, to reduce signal delay, to reduce total bill of materials (BoM) cost, or both, as compared to existing off-chip approaches. Numerous suitable uses and applications will be apparent in light of this disclosure.

In accordance with some embodiments, use of techniques disclosed herein may be detected, for example, by visual or other inspection, such as by cross-sectional scanning electron microscopy (SEM) or any other suitable microscopy technique, as will be apparent in light of this disclosure, of a given integrated circuit or other device having a through-body-via (TBV) capacitor configured as described herein.

<FIG> illustrate an integrated circuit (IC) fabrication process flow, in accordance with an embodiment of the present disclosure. The process may begin as in <FIG>, which is a cross-sectional view of an integrated circuit (IC) <NUM>, in accordance with an embodiment of the present disclosure. The semiconductor layer <NUM> of IC <NUM> can be formed from any suitable semiconductor material(s), such as, for example, silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide, a III-V compound semiconductor such as gallium arsenide, indium arsenide, indium phosphide, gallium nitride, or indium gallium arsenide, or a combination of any thereof, among others. In an example case, semiconductor layer <NUM> may be p-doped silicon. Semiconductor layer <NUM> can be configured as any one, or combination, of a bulk semiconductor substrate, a semiconductor-on-insulator (e.g., silicon-on-insulator, or SOI) structure, a semiconductor wafer, or a multi-layered structure, for example.

In accordance with some embodiments, semiconductor layer <NUM> may be formed from a low-resistivity material, which can be accomplished, for example, by maximizing or otherwise increasing dopant concentration, allowing semiconductor layer <NUM> to serve as a metal-like electrode for TBV capacitor <NUM> (discussed below with reference to <FIG>). For instance, in some example cases, semiconductor layer <NUM> may be formed from a material having a resistivity in the range of about <NUM>-<NUM>Ω·cm (e.g., ± <NUM>%). Note that the doping scheme can be throughout the bulk semiconductor substrate or layer <NUM>, or it can be selectively provisioned along the sidewalls local to the TBV <NUM> so as to provide one electrode of the TBV capacitor <NUM>. To such ends, any suitable dopant(s), dopant concentration(s), and doping process(es) may be used, as will be apparent in light of this disclosure. In other instances, such as those discussed below with respect to <FIG> and <FIG>, for example, a semiconductor layer <NUM> of any resistivity may be used; for instance, in some embodiments, semiconductor layer <NUM> may be formed from a material having a resistivity greater than about <NUM>Ω·cm (e.g., greater than about <NUM>Ω·cm, greater than about <NUM>Ω·cm).

The dimensions of semiconductor layer <NUM> can be customized, as desired for a given target application or end-use. As will be appreciated in light of this disclosure, it may be desirable to ensure that semiconductor layer <NUM> is of sufficient thickness, for example, to permit formation of one or more TBV capacitors <NUM> of sufficient dimensions to provide the amount of TBV capacitance desired for a given target application or end-use.

In accordance with some embodiments, semiconductor layer <NUM> may have undergone complementary metal-oxide-semiconductor (CMOS) processing. For instance, in some cases, a p-well (PW) <NUM> with one or more n+ and p+ doped regions may be formed in semiconductor layer <NUM>. In some such cases, the p-well <NUM> may be disposed within a deep n-well (DNW) <NUM>, which may provide electrical isolation between semiconductor layer <NUM> and other circuit component(s) of IC <NUM>. In some cases, an n-well (NW) <NUM> with one or more n+ and p+ doped regions may be formed in semiconductor layer <NUM>. In some instances, semiconductor layer <NUM> may have one or more p+ taps formed therein. In some instances, additional ion implantation may be provided to increase dopant concentration, for example, at the sidewalls of a given opening <NUM> (discussed below with reference to <FIG>), so as to provide a given desired degree of low-resistivity. Doping of a given p-well <NUM>, n-well <NUM>, deep n-well <NUM>, or other portion of semiconductor layer <NUM> may be provided as typically done, and the dopant type and concentration can be customized, as desired for a given target application or end-use.

In accordance with some embodiments, front-end transistor device(s) may be formed over semiconductor layer <NUM>. To that end, gate(s) can be provided over a given p-well <NUM> (optionally with deep n-well <NUM>) or n-well <NUM>, as typically done. A given gate can be formed from any suitable gate material, such as an electrically conductive metal or polysilicon (poly-Si), and the gate dimensions can be customized, as desired for a given target application or end-use. In addition, drain (D), source (S), and base (B) connections can be provided for a given p-type metal-oxide-semiconductor (PMOS) device or n-type metal-oxide-semiconductor (NMOS) device of IC <NUM> (e.g., as can be seen with respect to <FIG>). When optionally included, deep n-well <NUM> may serve to isolate the NMOS device (or other circuit components) of IC <NUM> from the surrounding semiconductor layer <NUM>, which, as previously noted, may be p-doped Si in some cases.

In accordance with some embodiments, conductive line(s) <NUM> may be formed over semiconductor layer <NUM>. A given conductive line <NUM> may be configured, for example, as an interconnect or other typical frontend routing, among others. A given conductive line <NUM> can be formed from any suitable electrically conductive material, such as, for example, copper, aluminum, nickel, cobalt, or a combination of any thereof, among others. Conductive line(s) <NUM> can be formed over IC <NUM>, for example, using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination of any thereof, among others. Furthermore, the dimensions of a given conductive line <NUM> can be customized, as desired for a given target application or end-use.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming an opening <NUM> in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. A given opening <NUM> can be formed using any suitable patterning technique, as will be apparent in light of this disclosure. For example, a given opening <NUM> may be formed using a directional dry etching process such as, for example, reactive-ion etching (RIE), ion beam etching, plasma etching, laser ablation, or a combination thereof, among others. The etch chemistry can be customized, as desired, and in some instances may be one compatible with pulsed or time-multiplexed (e.g., Bosch process) etching. In some cases, a given opening <NUM> may extend through the entire thickness of semiconductor layer <NUM> (e.g., be configured as a through-hole passing from a first surface of semiconductor layer <NUM> to a second surface thereof).

As can be seen with respect to <FIG>, a given opening <NUM> may be formed, for example, from the back side of semiconductor layer <NUM> so as to land, in part or in whole, on an underlying conductive line <NUM> formed over the front side of semiconductor layer <NUM>, in accordance with some embodiments. Thus, in a sense, such an opening <NUM> and underlying conductive line <NUM> may serve as a so-called catch-cup, with that conductive line <NUM> routing the TBV <NUM> (see <FIG>) from the catch-cup to other circuit component(s).

As discussed herein, a given opening <NUM> may be configured to host, at least in part, a dielectric layer <NUM> and a TBV <NUM> (e.g., as discussed below with reference to <FIG>), in accordance with some embodiments. Also, as discussed herein, a given opening <NUM> alternatively (or additionally) may be configured to host, at least in part, an isolation liner layer <NUM> and a conductive layer <NUM> (e.g., as discussed below with reference to <FIG> and 5C-5D), in accordance with some embodiments. As will be appreciated, isolation liner layer <NUM> may serve, for example, to electrically isolate the material of conductive layer <NUM> (e.g., formed in an opening <NUM>) from the surrounding semiconductor layer <NUM>, as well as prevent diffusion of the material of conductive layer <NUM> into that semiconductor layer <NUM>. As will be further appreciated, such an isolation liner layer <NUM> may not be needed, for instance, when semiconductor layer <NUM> (e.g., one or more doped regions along the sidewall of opening <NUM>) provides an electrode for the TBV capacitor <NUM> (e.g., as can be seen generally with respect to <FIG>, <FIG>, and <FIG>).

The dimensions and geometry of a given opening <NUM> can be customized, as desired for a given target application or end-use. In some instances, a given opening <NUM> may have a width/diameter in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In some cases, a given opening <NUM> may have a substantially uniform width/diameter along its length, whereas in some other cases, a given opening <NUM> may have a non-uniform or otherwise varying width/diameter along its length (e.g., a first portion of opening <NUM> may have a width/diameter within a first range, whereas a second portion thereof may have a width/diameter within a second, different range). In some instances, a given opening <NUM> may have a length in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In some example cases, a given opening <NUM> may have a length-to-width aspect ratio (AR) of <NUM>:<NUM> or less, <NUM>:<NUM> or less, <NUM>:<NUM> or less, or <NUM>:<NUM> or less. In some other example cases, a given opening <NUM> may have a length-to-width AR of <NUM>:<NUM> or greater, <NUM>:<NUM> or greater, <NUM>:<NUM> or greater, or <NUM>:<NUM> or greater. As a result of the etch technique(s) utilized, a given opening <NUM> may exhibit an isotropic or anisotropic profile. In some instances, a given opening <NUM> may be generally cylindrical in shape (e.g., with sidewalls that are substantially vertically straight). In the invention such as that generally shown in <FIG>, a given opening <NUM> has the shape of a conical frustum (e.g., with sidewalls that taper). In a more general sense, the profile of a given opening <NUM> can be tuned based on the etch process and recipe utilized in its formation, as desired for a given target application or end-use.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a dielectric layer <NUM> in opening <NUM>, in accordance with an embodiment of the present disclosure. Dielectric layer <NUM> can be formed from any of a wide range of dielectric material(s), including, for example, silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, and a high-κ dielectric material such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some cases, an annealing process may be carried out on the dielectric layer <NUM> to improve its quality, for instance, when a high-κ material is used. In still other embodiments, dielectric layer <NUM> can be implemented with a polymer (or blend of polymers) such as polyimide. In still other embodiments, dielectric layer <NUM> can be implemented with a combination of any the various dielectric materials provided in this paragraph, among others. As will be appreciated in light of this disclosure, the use of high-κ dielectric materials (e.g., having a dielectric constant κ greater than or equal to that of SiO<NUM>) may help to maximize TBV capacitance. Dielectric layer <NUM> can be formed over IC <NUM>, for example, using an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a combination of any thereof, among others.

Furthermore, the dimensions of dielectric layer <NUM> can be customized, as desired for a given target application or end-use. In some cases, dielectric layer <NUM> may have a thickness in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In a more general sense, the thickness of the dielectric material should be sufficient to electrically isolate the electrodes of the TBV capacitor (e.g., outer and inner electrodes; top and bottom electrodes) from one another so as to avoid short-circuiting of the TBV capacitor in a given application. In some instances, dielectric layer <NUM> may have a substantially uniform thickness over the topography provided by a given opening <NUM>, whereas in some other instances, dielectric layer <NUM> may have a non-uniform or otherwise varying thickness over such topography (e.g., a first portion of dielectric layer <NUM> may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range). In some instances, dielectric layer <NUM> may be substantially conformal to the underlying topography provided by a given opening <NUM>. In a more general sense, and in accordance with an embodiment, the thickness(es) of dielectric layer <NUM> can be tuned to provide the amount of TBV capacitance desired for a given target application or end-use.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a through-body via (TBV) <NUM> in opening <NUM>, in accordance with an embodiment of the present disclosure. A given TBV <NUM> can be formed from any suitable electrically conductive material(s), such as any of those example materials discussed above, for instance, with respect to conductive line(s) <NUM>, in accordance with some embodiments. A given TBV <NUM> can be formed, for example, using an electroplating process, an electroless deposition process, or a combination of any thereof, among others. In some instances, a seed layer optionally may be formed over dielectric layer <NUM> prior to bulk filling with the TBV <NUM> material.

The dimensions and geometry of a given TBV <NUM> can be customized, as desired for a given target application or end-use, and as will be appreciated in light of this disclosure, may be of any of the example dimensions and geometries discussed above, for instance, with respect to a given opening <NUM> hosting such TBV <NUM>, in accordance with some embodiments. In some example cases, a given TBV <NUM> may have a width/diameter in the range of about <NUM>-<NUM> and a length in the range of about <NUM>-<NUM>. In some example cases, a given TBV <NUM> may have a length-to-width aspect ratio (AR) of <NUM>:<NUM> or less, <NUM>:<NUM> or less, <NUM>:<NUM> or less, or <NUM>:<NUM> or less. In some other example cases, a given TBV <NUM> may have a length-to-width AR of <NUM>:<NUM> or greater, <NUM>:<NUM> or greater, <NUM>:<NUM> or greater, or <NUM>:<NUM> or greater.

In accordance with an embodiment, the combination of the bulk TBV <NUM>, surrounding doped or otherwise low-resistance semiconductor layer <NUM>, and intervening dielectric layer <NUM> sandwiched there between provides a TBV capacitor <NUM>, as can be seen, for instance, from the enlarged view enclosed by the dashed circle in <FIG>. As will be appreciated in light of this disclosure, and in accordance with some embodiments, an array of such TBV capacitors <NUM> can be formed in semiconductor layer <NUM> to provide the amount of TBV capacitance desired for a given target application or end-use.

<FIG> illustrate an integrated circuit (IC) fabrication process flow, in accordance with another embodiment of the present disclosure. The process may begin as in <FIG>, which is a cross-sectional view of an integrated circuit (IC) <NUM>, in accordance with an embodiment of the present disclosure. As can be seen here, the semiconductor layer <NUM> of IC <NUM> may have undergone CMOS processing, as discussed above. As can be seen further, IC <NUM> may include a dielectric layer <NUM> formed over semiconductor layer <NUM> (e.g., over a back side thereof), in accordance with some embodiments. In some instances, dielectric layer <NUM> may be configured to serve as an etch stop layer. Dielectric layer <NUM> can be formed from any of the example materials discussed above, for instance, with respect to dielectric layer <NUM>, in accordance with some embodiments. Dielectric layer <NUM> can be formed over IC <NUM>, for example, using a physical vapor deposition (PVD) process such as sputter deposition, a chemical vapor deposition (CVD) process such as plasma-enhanced CVD (PECVD), or a combination of any thereof, among others.

Furthermore, the dimensions of dielectric layer <NUM> can be customized, as desired for a given target application or end-use. In some cases, dielectric layer <NUM> may have a thickness in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In some instances, dielectric layer <NUM> may have a substantially uniform thickness over the topography provided by semiconductor layer <NUM>, whereas in some other instances, dielectric layer <NUM> may have a non-uniform or otherwise varying thickness over such topography (e.g., a first portion of dielectric layer <NUM> may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range). In some instances, dielectric layer <NUM> may be substantially conformal to the underlying topography provided by semiconductor layer <NUM>.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming an opening <NUM> in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. As can be seen with respect to <FIG>, a given opening <NUM> may be formed, for example, from the front side of semiconductor layer <NUM> so as to land on dielectric layer <NUM> formed over the back side of semiconductor layer <NUM>, in accordance with some embodiments.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a dielectric layer <NUM> in opening <NUM>, and as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a through-body via (TBV) <NUM> in opening <NUM>, in accordance with some embodiments of the present disclosure. Additional CMOS backend processing may be performed, for example, to connect TBV <NUM> to other circuit component(s).

<FIG> illustrate an integrated circuit (IC) fabrication process flow, in accordance with another embodiment of the present disclosure. The process may begin as in <FIG>, which is a cross-sectional view of an IC <NUM>, in accordance with an embodiment of the present disclosure. As can be seen here, the semiconductor layer <NUM> of IC <NUM> may be formed as a semiconductor-on-insulator or so-called SOI structure (e.g., silicon-on-insulator, or other SOI structure) having an insulator layer <NUM> buried therein. Insulator layer <NUM> may be formed using any suitable process, such as, for example, an ion beam implantation process with subsequent high-temperature annealing. In an example case, semiconductor layer <NUM> may undergo implantation of oxygen ions (O+) that are subsequently converted to produce the buried insulator layer <NUM>. Thus, if semiconductor layer <NUM> is silicon, for example, then the buried insulator layer <NUM> may be SiO<NUM>. In addition, the semiconductor layer <NUM> of IC <NUM> may have undergone CMOS processing, as discussed above. The isolation provided by the semiconductor-on-insulator configuration may be confined only to the front-end circuit(s) of IC <NUM>, ensuring that the p+ tap bias on a given TBV <NUM> (discussed below with reference to <FIG>) does not impact (or otherwise negligibly impacts) those front-end circuit(s). As will be further noted, unlike the semiconductor layers <NUM> discussed above with respect to <FIG> and <FIG>, the semiconductor layer <NUM> of <FIG> does not include a deep n-well (DNW) <NUM>.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming opening(s) <NUM> in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. As can be seen with respect to <FIG>, a given opening <NUM> may be formed, for example, from the back side of semiconductor layer <NUM> so as to land, in part or in whole, on an underlying conductive line <NUM> formed over the front side of semiconductor layer <NUM>, in accordance with some embodiments. In so doing, a given opening <NUM> may pass through the thickness of insulator layer <NUM>, as well as any remaining front side semiconductor layer <NUM> material (e.g., the active layer in which one or more CMOS devices may be formed). Thus, in a sense, such an opening <NUM> and underlying conductive line <NUM> may serve as a so-called catch-cup, with that conductive line <NUM> routing the TBV <NUM> (see <FIG>) from the catch-cup to other circuit component(s).

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a dielectric layer <NUM> in each opening <NUM>, and as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a through-body via (TBV) <NUM> in each opening <NUM>, in accordance with some embodiments of the present disclosure. Additional CMOS backend processing may be performed, for example, to connect TBV <NUM> to other circuit component(s). As can be seen, a p+ tap on the back side of semiconductor layer <NUM> may be electrically contacted with one of the TBVs <NUM> by a metal line <NUM>. Metal line <NUM> can be formed from any of the example electrically conductive materials discussed above, for instance, with respect to conductive line(s) <NUM>, in accordance with some embodiments. In a sense, providing the p+ tap contact via metal line <NUM> sacrifices one TBV <NUM> out of the array thereof.

<FIG> illustrate an integrated circuit (IC) fabrication process flow, in accordance with another embodiment of the present disclosure. As can be seen, the embodiment effectively provides a dual-TBV capacitor configuration, wherein one of a pair of neighboring TBVs is a part of a MIM-type structure and provides front side access to the cathode (or anode) of the capacitor, and the other TBV is electrically connected to an upper portion of the first TBV and provides front side access to the anode (or cathode) of the capacitor. Back side access is available as well, in some such embodiments.

The process may begin as in <FIG>, which is a cross-sectional view of an integrated circuit (IC) <NUM>, in accordance with an embodiment of the present disclosure. As will be noted, as compared to the IC <NUM> in <FIG>, for example, the IC <NUM> here in <FIG> does not utilize a low-resistivity semiconductor layer <NUM> or a deep n-well (DNW) <NUM>, semiconductor-on-insulator isolation, or one or more p+ taps. The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming opening(s) <NUM> in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. As can be seen with respect to <FIG>, a given opening <NUM> may be formed, for example, from the back side of semiconductor layer <NUM> so as to land, in part or in whole, on an underlying conductive line <NUM> formed over the front side of semiconductor layer <NUM>, in accordance with some embodiments. Thus, in a sense, such an opening <NUM> and underlying conductive line <NUM> may serve as a so-called catch-cup, with that conductive line <NUM> routing the TBV <NUM> (see <FIG>) from the catch-cup to other circuit component(s).

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming an isolation liner layer <NUM> there over, in accordance with an embodiment of the present disclosure. Isolation liner layer <NUM> can be formed with any number of suitable diffusion barrier materials, such as, for example, tantalum, tantalum nitride, titanium nitride, tungsten, tungsten nitride, hafnium, niobium, vanadium, and zirconium, or a combination of any thereof, among others, in accordance with some embodiments. Likewise, any of the various materials discussed above with respect to dielectric layer <NUM> could be used for isolation liner layer <NUM>. Furthermore, the dimensions of isolation liner layer <NUM> can be customized, as desired for a given target application or end-use. In some example cases, isolation liner layer <NUM> may have a thickness in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In some instances, isolation liner layer <NUM> may have a substantially uniform thickness over the topography provided by a given opening <NUM> (or other portion of IC <NUM>), whereas in some other instances, isolation liner layer <NUM> may have a non-uniform or otherwise varying thickness over such topography (e.g., a first portion of isolation liner layer <NUM> may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range). In some instances, isolation liner layer <NUM> may be substantially conformal to the underlying topography provided by a given opening <NUM> (or other portion of IC <NUM>). In a more general sense, and in accordance with an embodiment, the thickness(es) of isolation liner layer <NUM> can be tuned to provide the amount of TBV capacitance desired for a given target application or end-use.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a conductive layer <NUM> over isolation liner layer <NUM> in an opening <NUM> of IC <NUM>, in accordance with an embodiment of the present disclosure. Conductive layer <NUM> provides the outer electrode of the TBV capacitor <NUM> and can be formed with any of the example materials and techniques discussed above, for instance, with respect to conductive line(s) <NUM>, in accordance with some embodiments. In some cases, conductive layer <NUM> may be formed, in part or in whole, from an electrically conductive ceramic, such as, for example, titanium nitride. Furthermore, the dimensions of conductive layer <NUM> can be customized, as desired for a given target application or end-use. In some example cases, conductive layer <NUM> may have a thickness in the range of about <NUM>-<NUM> (e.g., about <NUM>-<NUM>, about <NUM>-<NUM>, about <NUM>-<NUM>, or any other sub-range in the range of about <NUM>-<NUM>). In some instances, conductive layer <NUM> may have a substantially uniform thickness over the topography provided by isolation liner layer <NUM> in a given opening <NUM> (or other portion of IC <NUM>), whereas in some other instances, conductive layer <NUM> may have a non-uniform or otherwise varying thickness over such topography (e.g., a first portion of conductive layer <NUM> may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range). In some instances, conductive layer <NUM> may be substantially conformal to the underlying topography provided by isolation liner layer <NUM> in a given opening <NUM> (or other portion of IC <NUM>). In a more general sense, and in accordance with an embodiment, the thickness(es) of conductive layer <NUM> can be tuned to provide the amount of TBV capacitance desired for a given target application or end-use. Conductive layer <NUM> may be configured to serve, in accordance with an embodiment, as a cathode for the TBV capacitor <NUM> (see <FIG>).

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a dielectric layer <NUM> over conductive layer <NUM> in an opening <NUM> of IC <NUM>, in accordance with an embodiment of the present disclosure. In some instances, dielectric layer <NUM> may have a substantially uniform thickness over the topography provided by conductive layer <NUM> in a given opening <NUM>, whereas in some other instances, dielectric layer <NUM> may have a non-uniform or otherwise varying thickness over such topography (e.g., a first portion of dielectric layer <NUM> may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range). In some instances, dielectric layer <NUM> may be substantially conformal to the underlying topography provided by conductive layer <NUM> in a given opening <NUM>. In a more general sense, and in accordance with an embodiment, the thickness(es) of dielectric layer <NUM> can be tuned to provide the amount of TBV capacitance desired for a given target application or end-use.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming a through-body via (TBV) <NUM> in each of the two openings <NUM>, in accordance with the invention.

As can be seen, the example TBV capacitor <NUM> structure illustrated in <FIG> is configured, in a general sense, like a metal-insulator-metal (MIM) structure, with the TBVs <NUM> (e.g., the TBV <NUM> on the right and the TBV <NUM> on the left are electrically connected with one another) serving as the anode, and the conductive layer <NUM> on the left serving as the cathode. Electrical connection to the cathode and anode can be provided on the front side or back side (or both) of IC <NUM>, as desired for a given target application or end-use. Similar to the case discussed above with respect to <FIG>, only one TBV <NUM> (e.g., the TBV <NUM> on the right) may be needed to route the anode signal from the back side to the front side of IC <NUM>.

<FIG> illustrate an integrated circuit (IC) fabrication process flow, in accordance with another embodiment of the present disclosure. As will be appreciated in light of this disclosure, the process flow of <FIG> is similar to that discussed above with respect to <FIG>, but with TBV processing from the front side of IC <NUM>, similar to that discussed above with respect to <FIG>. The process may begin as in <FIG>, which is a cross-sectional view of an IC <NUM>, in accordance with an embodiment of the present disclosure. As can be seen, IC <NUM> here may include a semiconductor layer <NUM> and dielectric layer <NUM> configured substantially similar to the IC <NUM> described above with respect to <FIG>.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming an opening <NUM> in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. As with <FIG> discussed above, a given opening <NUM> may be formed, for example, from the front side of semiconductor layer <NUM> so as to land on dielectric layer <NUM> formed over the back side of semiconductor layer <NUM>, in accordance with some embodiments.

The process may continue as in <FIG>, which is a cross-sectional view of the IC <NUM> of <FIG> after forming an isolation liner layer <NUM> there over, as well as a p-well (PW) <NUM> and an n-well (NW) <NUM> (e.g., with one or more n+ and p+ doped regions) in semiconductor layer <NUM>, in accordance with an embodiment of the present disclosure. Formation of isolation liner layer <NUM> may involve, in some cases, deposition thereof over IC <NUM> followed by one or more patterning processes, which may be performed as typically done. Patterning may clear away a portion of isolation liner layer <NUM> so that a p-well <NUM>, an n-well <NUM>, etc., may be formed in semiconductor layer <NUM>, in accordance with some embodiments. As can be seen, as compared with the IC <NUM> of <FIG>, the IC <NUM> here may be formed without the one or more p+ taps or deep n-well (DNW) <NUM>, in accordance with an embodiment.

The process may continue as in <FIG>, which are cross-sectional views of the IC <NUM> of <FIG> after forming, respectively, a conductive layer <NUM> over isolation liner layer <NUM> in an opening <NUM> (<FIG>), a dielectric layer <NUM> over conductive layer <NUM> in opening <NUM> (<FIG>), and a TBV <NUM> in opening <NUM> (<FIG>), in accordance with some embodiments of the present disclosure. In accordance with an embodiment, the combination of the bulk TBV <NUM>, surrounding semiconductor layer <NUM>, and intervening dielectric layer <NUM> sandwiched there between may provide a TBV capacitor <NUM>, as can be seen, for instance, from the enlarged view enclosed by the dashed circle in <FIG>. As will be appreciated in light of this disclosure, and in accordance with some embodiments, an array of such TBV capacitors <NUM> can be formed in semiconductor layer <NUM> to provide the amount of TBV capacitance desired for a given target application or end-use.

The process may continue as in <FIG>, which is a top-down view of the IC <NUM> of <FIG> after patterning with metal lines <NUM> and <NUM>, in accordance with an embodiment of the present disclosure. As can be seen, additional front side patterning, for example, with a metal line <NUM> (e.g., metal interconnect) may provide an electrical connection for the anode (e.g., TBV <NUM>), whereas a metal line <NUM> (e.g., metal interconnect) may provide a separate electrical connection for the concentric cathode (e.g., conductive layer <NUM>). As will be appreciated in light of this disclosure, metal lines <NUM> and <NUM> can be formed with any of the example materials, techniques, and dimensions discussed above, for instance, with respect to conductive line(s) <NUM>, in accordance with some embodiments. As will be further appreciated, one or more electrically insulating layers may be provided, for instance, between metal line <NUM> and underlying conductive layer <NUM> so as to avoid electrically shorting TBV capacitor <NUM> in electrically connecting metal line <NUM> with TBV <NUM>, in accordance with some embodiments. Any suitable dielectric or other electrically insulating material may be used to that end.

Any of the various techniques discussed herein, for example, with respect to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> can be used, in part or in whole, to form one or more TBV capacitors <NUM>. <FIG> is a scanning electron microscope (SEM) image illustrating several TBV capacitors <NUM> configured in accordance with an embodiment of the present disclosure. In some instances, an array of TBV capacitors <NUM> may be formed, the array having a given degree of regularity (or irregularity), as desired for a given target application or end-use. Numerous configurations and variations will be apparent in light of this disclosure.

In accordance with an example embodiment, a TBV capacitor <NUM> configured as described herein with a dielectric layer <NUM> formed, for instance, from hafnium oxide (or other material having a dielectric constant of <NUM> or higher) may provide about <NUM> pF (e.g., ± <NUM>%) of capacitance. If the TBV <NUM> of that TBV capacitor <NUM> occupies an area of about <NUM> × <NUM> (e.g., such as is suggested by current JEDEC standard specifications relating to through-body vias), then that TBV capacitor <NUM> may have an areal capacitance density of about <NUM> fF/µm<NUM> (e.g., ± <NUM>%), in accordance with an example embodiment. As will be appreciated in light of this disclosure, this may be more than a <NUM>× increase in on-chip capacitance density as compared to a typical MIM capacitor. As will be further appreciated, further scaling may further improve on-chip capacitance density, in some cases. If more than <NUM>,<NUM> TBVs <NUM> (e.g., each occupying an area of about <NUM> × <NUM>) can fit in a <NUM><NUM> chip, then an array of TBV capacitors <NUM> formed therefrom may provide more capacitance than a typical <NUM>µF off-chip capacitor, in accordance with an example embodiment.

<FIG> illustrates a computing system <NUM> implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. As can be seen, the computing system <NUM> houses a motherboard <NUM>. The motherboard <NUM> may include a number of components, including, but not limited to, a processor <NUM> and at least one communication chip <NUM>, each of which can be physically and electrically coupled to the motherboard <NUM>, or otherwise integrated therein. As will be appreciated, the motherboard <NUM> may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system <NUM>, etc. Depending on its applications, computing system <NUM> may include one or more other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system <NUM> may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip <NUM> can be part of or otherwise integrated into the processor <NUM>).

The communication chip <NUM> enables wireless communications for the transfer of data to and from the computing system <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The computing system <NUM> may include a plurality of communication chips <NUM>.

The processor <NUM> of the computing system <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also may include an integrated circuit die packaged within the communication chip <NUM>. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor <NUM> (e.g., where functionality of any chips <NUM> is integrated into processor <NUM>, rather than having separate communication chips). Further note that processor <NUM> may be a chip set having such wireless capability. In short, any number of processor <NUM> and/or communication chips <NUM> can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

Claim 1:
An integrated circuit including a capacitor, the integrated circuit comprising:
a semiconductor layer (<NUM>);
a first through-body via, TBV (<NUM>), disposed within a first through-hole formed in a semiconductor layer (<NUM>), the first through-hole extending through the semiconductor layer from a first surface thereof to a second surface thereof;
an isolation layer (<NUM>) disposed in the first through-hole between a first dielectric layer (<NUM>) and the semiconductor layer (<NUM>) and conformal to a sidewall of the first trough-hole;
the first dielectric layer (<NUM>) disposed between the first TBV (<NUM>) and the isolation layer (<NUM>);
wherein a second electrode of the capacitor is provided by a conductive layer (<NUM>) disposed between the isolation layer (<NUM>) and the first dielectric layer (<NUM>);
a second TBV (<NUM>) disposed within a second through-hole formed in the semiconductor layer (<NUM>) adjacent to the first TBV (<NUM>), wherein
the second TBV (<NUM>) is electrically connected with the first TBV (<NUM>) and electrically isolated from the semiconductor layer (<NUM>) by an isolation layer (<NUM>) disposed in the second through-hole on the semiconductor layer (<NUM>) and conformal to a sidewall of the second trough-hole,
a first electrode of the capacitor is provided by the first TBV (<NUM>), and an electrical connection to the first electrode of the capacitor and an electrical connection to the second electrode of the capacitor are provided on the front side or the back side of the integrated circuit by a contact with the second TBV (<NUM>) and the conductive layer (<NUM>) respectively, wherein the first trough-hole and the second trough-hole have the shape of a conical frustum.