Patent Description:
Computer systems may include any number of components, such as a central processing unit (CPU), memory, chipsets, and/or many other devices coupled together by a computer bus. The computer bus may transfer data between devices or components inside a computer, as well as between computers. The computer bus may implement one or more communication protocols.

<CIT> relates to systems and devices including protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.

<CIT> relates to systems and devices including a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY includes a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer directs data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY includes a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer directs data to the first set or the second set of ECC encoders based on the selected interconnect protocol.

The present invention is defined by the independent claim <NUM>.

Computing systems may implement various communication protocols. For example, a communication link between a transmitter and a receiver may implement a compute express link (CXL) protocol, an ultra path interconnect (UPI) protocol, and so forth. The receiver may receive data units (e.g., packets, flits, etc.) via the link, and may process the received data units. Such processing may include performing correction processing (e.g., forward error correction (FEC)) to correct errors that may occur in transmission. However, such error correction may introduce latency into the processing of the received data unit. As used herein, the term "high latency processing mode" may refer to processing of received data by performing error correction. To reduce such latency, some communication protocols may provide bypass formats or other mechanisms that allow processing to occur without error correction. As used herein, the term "low latency processing mode" may refer to processing of received data without performing error correction. However, in the event of a bit error, the receiver may be forced to switch from the low latency processing mode to the high low latency processing mode. Further, under heavy traffic load, the frequency of bit errors may cause the receiver to spend the majority of operating time in the high latency processing mode. Accordingly, in such situations, the receiver may not benefit from the low latency provided by the bypass formats. By way of example, if a bit error rate (BER) is 1e-<NUM>, a bit error is expected every <NUM>-<NUM> flits. The skip ordered set (SOS) insertion frequency for a x16 link may be every <NUM>-<NUM> flits. As such, it may not be effective to rely on SOS insertion to switch over from the high latency mode to the low latency mode. Further, if an error occurs every <NUM> flits, and we assume that an error on average happens <NUM> flits after the link switches modes, then the system may spend <NUM> flits out of a possible <NUM> flits (e.g., <NUM>% of the time) in the high latency mode.

Further, some communication links may implement receiver replay buffers. For example, if an uncorrectable error is detected and the receiver has sufficient space in its replay buffer, it can choose to do a selective NAK only for the data element in error, while storing data for the subsequent flits in the replay buffer. Once the erroneous flit is replayed, the receiver can read out the subsequent flits from the replay buffer. In this manner, the replay buffer may minimize the chance of a full sequence number replay in order to save overall link bandwidth. However, if the receiver spends a substantial amount of time writing into and reading out of the replay buffer, it may incur additional cost of the latency associated with passing through the replay buffer.

Some embodiments described herein may allow a receiver to switch over to the low latency operating mode deterministically. For example, some embodiments may provide include a mechanism for a receiver to send a hint signal to cause a transmitter to insert no-operation (NOP) message when the receiver is in the high latency operating mode. The NOP message may allow the receiver to switch over to the low latency operating mode. Further, some embodiments described herein may provide a mechanism for the transmitter to monitor replay characteristics and adjust the number of transmitted NOP messages, and thereby improve utilization of link throughput and reduce the chances of a full replay.

Referring now to <FIG>, shown is a block diagram of an example system <NUM> in accordance with one or more embodiments. The system <NUM> may include a transmitter (TX) circuit <NUM> transmitting data units (e.g., flits) to a receiver (RX) circuit <NUM> via a link. In some embodiments, the transmitter circuit <NUM> may include a response circuit <NUM>, and the receiver circuit <NUM> may include a hint circuit <NUM>. The transmitter circuit <NUM>, the receiver circuit <NUM>, the response circuit <NUM>, and the hint circuit <NUM> may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), firmware, or a combination thereof.

In some embodiments, the receiver circuit <NUM> may include two paths for processing received data, namely a high latency path <NUM> and a low latency path <NUM>. As shown in <FIG>, the high latency path <NUM> may include performing error correction on the processed data using an error correction circuit (ECC) <NUM>. As such, using the high latency path <NUM> may incur a higher latency that using the low latency path <NUM> that does not include performing error correction. The receiver circuit <NUM> may selectively operate in one of two processing modes, namely the high latency processing mode when using the high latency path <NUM>, and the low latency processing mode when using the low latency path <NUM>.

In some embodiments, the hint circuit <NUM> may generate a hint message ("Hint") based on operating characteristics of the receiver circuit <NUM>, and may transmit the hint message to the transmitter circuit <NUM>. The hint message may be a signal or data element indicating that the receiver circuit <NUM> is ready to switch from the high latency processing mode to the low latency processing mode. For example, the hint message may comprise a special bit that is set in a flit header. In another example, the hint message may comprise sending a specialized flit that is only used as a hint message. In yet another example, the hint message may comprise an overloaded acknowledgement-signal (ACK) or a negative-acknowledgement signal (NACK) with a <NUM> value, which may provide better bit and bandwidth efficiency than the other examples described above.

In some embodiments, the hint circuit <NUM> may generate and transmit the hint message when certain conditions are met in the receiver circuit <NUM>. For example, the hint message may be transmitted when the receiver circuit <NUM> is operating in a normal flit exchange phase, is currently operating in the high latency operating mode (e.g., is currently processing received flits in the high latency path <NUM>), and no hint message has been sent in a recent period of a defined length (e.g., the last <NUM> flits, the last <NUM> flits, and so forth). The length of the recent period may be a configurable setting of the system <NUM>.

In some embodiments, the response circuit <NUM> may receive or detect the hint message, and may cause a response message to be transmitted to the receiver circuit <NUM>. The response message may include one NOP flit or a set of multiple consecutive NOP flits, and may be inserted in the data stream transmitted to the receiver circuit <NUM> via the link. The number of NOP flits included in the response message may be a configurable setting of the system <NUM>.

In some embodiments, the NOP flits in the response message may cause the high latency path <NUM> to be "drained" of pending work (i.e., to complete all pending work). In this manner, receiving the response message may allow the receiver circuit <NUM> to switch from the high latency path <NUM> to the low latency path <NUM>. In some embodiments, the bandwidth loss caused by one NOP flit may be less that the latency savings associated with using the low latency path <NUM>. Accordingly, the hint circuit <NUM> and response circuit <NUM> may provide significant latency savings in high link utilization scenarios. In some embodiments, the hint circuit <NUM> and/or the response circuit <NUM> may be selectively disabled to operate the system <NUM> in a conventional mode if desired in some applications (e.g., if link utilization is prioritized over latency for a given application).

Referring now to <FIG>, shown is a flow diagram of a method <NUM>, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., transmitter circuit <NUM>, receiver circuit <NUM>, response circuit <NUM>, and/or hint circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include receiving data by a receiver. Decision block <NUM> may include determining whether the receiver is currently using a high latency operating mode. If not, the method <NUM> may return to block <NUM>. Otherwise, if it is determined that the receiver is currently using a high latency operating mode, then the method <NUM> may continue at decision block <NUM>, including determining whether the receiver has sent a hint message in a recent period. If so, the method <NUM> may return to block <NUM>. Otherwise, if it is determined that the receiver has not sent a hint message in a recent period, then the method <NUM> may continue at block <NUM>, including transmitting a hint message to a transmitter. For example, referring to <FIG>, the hint circuit <NUM> may transmit a hint message in response to determining that the receiver circuit <NUM> is operating in the high latency operating mode (e.g., is currently processing received flits in the high latency path <NUM>) and has not sent any hint message in a recent period (e.g., in the last two hundred flits).

Referring again to <FIG>, decision block <NUM> may include determining whether the transmitter has sent a response message in a recent period. If so, then no action is taken by the transmitter in response to the hint message. Otherwise, if it is determined that the transmitter has not sent a response message in a recent period, then the method <NUM> may continue at block <NUM>, including transmitting a response message to the receiver. In some embodiments, the response message may include a set of one or more multiple consecutive NOP flits. For example, referring to <FIG>, the response circuit <NUM> may receive the hint message from the hint circuit <NUM>, and in response may cause a response message to be transmitted to the receiver circuit <NUM>. The response message may include one or more NOP flits, and may be inserted in the data stream transmitted to the receiver circuit <NUM> via the link.

Referring again to <FIG>, block <NUM> may include the receiver draining the high latency path using the NOP message. Block <NUM> may include the receiver switching from the high latency path to the low latency path. After block <NUM>, the method <NUM> may be completed. For example, referring to <FIG>, receiving and/or processing the response message may cause the receiver circuit <NUM> to not schedule any new work, and therefore may allow the high latency path <NUM> to be drained of its pending work. Once the high latency path <NUM> is drained, the receiver circuit <NUM> may switch from the high latency path <NUM> to the low latency path <NUM>.

Referring now to <FIG>, shown is a block diagram of an example system <NUM> in accordance with one or more embodiments. In some embodiments, the system <NUM> may correspond generally to all or a part of the system <NUM> (shown in <FIG>). However, in other embodiments, the system <NUM> may be distinct or separate from the system <NUM>.

As shown, the system <NUM> may include a transmitter circuit <NUM> that transmits data units (e.g., flit, packet, block, etc.) to a receiver circuit <NUM> via a link. In some embodiments, the receiver circuit <NUM> may include a replay circuit <NUM>, an error detection circuit <NUM>, an error correction circuit <NUM>, and a receiver (RX) replay buffer <NUM>. Further, the transmitter circuit <NUM> may include a latency circuit <NUM>, a look-up table <NUM>, a replay tracker <NUM>, and a transmitter (TX) replay buffer <NUM>.

In one or more embodiments, the TX replay buffer <NUM> may store a data unit before it is transmitted, and may retain the stored data unit until it has been positively acknowledged by the receiver circuit <NUM>. Once an acknowledgement arrives from the receiver circuit <NUM> for that data unit, it can be removed from the TX replay buffer <NUM>. However, if the data unit is not acknowledged, then that data unit and any data units transmitted after it are retransmitted or "replayed" out of the TX replay buffer <NUM>. The RX replay buffer <NUM> may store received data units, and the error detection circuit <NUM> may detect errors in the received data units. For example, incoming communications may be error correction coded (ECC), and the error detection circuit <NUM> may perform error checking (e.g., a cyclic redundancy checksum (CRC) process).

In some embodiments, if the error detection circuit <NUM> detects an error in a received data element, the error correction circuit <NUM> may attempt to correct the error (e.g., using a forward error correction (FEC) process). Further, if the detected error cannot be corrected, the replay circuit <NUM> may determine whether the RX replay buffer <NUM> has sufficient available space for a replay process. If it is determined that the RX replay buffer <NUM> has sufficient available space, the replay circuit <NUM> may transmit a replay signal to the transmitter <NUM>. The replay signal may identify a particular data unit that had an uncorrectable error, and therefore needs to be replayed by re-transmitting the erroneous data unit and the following data units to the receiver circuit <NUM>. In some examples, the replay signal may be a selective negative-acknowledgement signal (NACK) of the erroneous data unit.

In some embodiments, the latency circuit <NUM> may receive the replay signal, and in response may determine an occupancy metric for the TX replay buffer <NUM>. For example, assume that the replay signal identifies an erroneous flit having a sequence number X. Assume further, that the set of flits that follow the erroneous flit are identified by sequence number that increase consecutively. Thus, as illustrated in <FIG>, the TX replay buffer <NUM> may store a set of flits having sequence numbers X to Y, and the RX replay buffer <NUM> may store a set of flits having sequence numbers X+<NUM> to Y. Accordingly, in this example, (Y-X) flits will have to be removed from the RX replay buffer <NUM> in order for it to become empty.

In some embodiments, the latency circuit <NUM> may determine an occupancy metric equal to the drain time (DT) to empty the RX replay buffer <NUM> using only skip ordered sets (SOS). For example, assume that each SOS drains <NUM> flits, that a SOS is inserted every <NUM> flits, and that each flit takes 2ns to drain from the RX replay buffer <NUM>. In this example, the drain time DT is equal to ((Y-X)*<NUM>*<NUM>)*<NUM> ns, and indicates the time needed to empty the RX replay buffer <NUM> if using only on SOSs. Depending on the value of the occupancy metric (e.g., drain time DT), a replay operation may result in one of the following three possible outcomes. In a first outcome, if the next replay happens on average before the drain time is up, then the receiver is perpetually using the RX replay buffer <NUM>, thereby incurring a latency penalty, and likely resulting in a full sequence replay once the RX replay buffer <NUM> fills up. In a second possible outcome, if the next replay on average requires a period longer than DT but less than (<NUM>*T), then the RX replay buffer <NUM> will empty. However, the receiver may spend more than <NUM>% of the time reading out of the RX replay buffer <NUM>. In a third possible outcome, it may be possible to extend the ranges to (<NUM>*T) to (<NUM>*T) for <NUM>% of the time reading out of the RX replay buffer <NUM>.

In one or more embodiments, the replay tracker <NUM> may include hardware (e.g., circuitry) and/or software logic to track statistics associated with data transmitted from the transmitter circuit <NUM> to the receiver circuit <NUM>. For example, the replay tracker <NUM> may calculate or otherwise determine the average number of received data units between successive replay signals (AvgR) sent by the replay circuit <NUM>. In some examples, the average number AvgR may be computed as an average number of flits received between successive replay signals, and may be computed across a time period defined by a given number of consecutive replay signals (e.g., <NUM> replay signals, <NUM> replay signals, and so forth).

In one or more embodiments, the latency circuit <NUM> may use the occupancy metric (e.g., drain time DT) and the average number AvgR to identify a particular entry of the look-up table <NUM>. In some embodiments, the look-up table <NUM> may include multiple entries that each indicate a different rate or number of NOP messages to be inserted into the data transmitted to the receiver circuit <NUM> (also referred to as an "NOP insertion rate"). The latency circuit <NUM> may then insert NOP messages (e.g., NOP flits) into the transmitted data according to the determined NOP insertion rate.

Referring now to <FIG>, shown is an example operation <NUM> for identifying a particular entry of the look-up table <NUM>. As shown in <FIG>, the example look-up table <NUM> may include multiple entries, with each entry including an index value <NUM> and an NOP insertion value <NUM>. The index value <NUM> may be a fraction or a multiple of the average number AvgR (i.e., the average number of received data units between successive replay signals). Further, the index value <NUM> may indicate one or more range boundaries (e.g., upper bound, lower bound, or both) for a range associated with the entry. For example, as shown in <FIG>, the index value <NUM> of the first entry may define an associated first range having a lower bound at the average number AvgR. In another example, the index value <NUM> of the second entry may define an associated second range having a lower bound equal to the average number AvgR divided by two, and having an upper bound equal to the average number AvgR. In yet another example, the index value <NUM> of the third entry may define an associated third range having a lower bound equal to the average number AvgR divided by four, and having an upper bound equal to the average number AvgR divided by two.

In some embodiments, the latency circuit <NUM> may calculate the drain time DT as described above, and may match <NUM> the calculated DT to a range associated with a particular entry of the look-up table <NUM> (e.g., by matching <NUM> to the third range associated with the third entry). Further, the latency circuit <NUM> may determine the NOP insertion rate by reading the NOP insertion value <NUM> of the matching entry. The latency circuit <NUM> may then insert NOP messages (e.g., NOP flits) into the data transmitted to the receiver circuit <NUM> according to the determined NOP insertion rate. For example, if DT matches the third entry of the look-up table <NUM> having an NOP insertion value <NUM> of <NUM>, then the latency circuit <NUM> may insert at least <NUM> NOP flits for every <NUM> flits that are transmitted. The latency circuit <NUM> may continue this insertion until the earliest of receiving the next selective replay signal, or when the sequence number Y has been de-allocated from the TX retry buffer <NUM>. Further, if a full sequence replay command is received (indicating that the RX replay buffer <NUM> is full or has lost tracking), then the transmitter circuit <NUM> may continue performing the replay process, and/or may use a higher NOP insertion rate until an ACK for the sequence number Y is received.

It is noted that, while <FIG> illustrates one technique for determining the NOP insertion rate using the look-up table <NUM>, embodiments are not limited in this regard. For example, it is contemplated that the NOP insertion rate may be calculated using a formula or algorithm that uses the average number AvgR and/or any occupancy metric as input parameters. In another example, it is contemplated that the entry of the look-up table <NUM> may be selected using other techniques (e.g., by matching to a closest index value).

Referring now to <FIG>, shown is a flow diagram of a method <NUM>, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., transmitter circuit <NUM>, receiver circuit <NUM>, replay circuit <NUM>, and latency circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include receiving a data unit (e.g., a flit) by a receiver. Decision block <NUM> may include determining whether an uncorrectable error has been detected in the received data unit. If not, the method <NUM> may return to block <NUM>. Otherwise, if it is determined that an uncorrectable error has been detected in the received data unit, then the method <NUM> may continue at decision block <NUM>, including determining whether a receiver replay buffer has sufficient space for a replay process. If not, the method <NUM> may return to block <NUM>. Otherwise, if it is determined that the receiver replay buffer has sufficient space, then the method <NUM> may continue at block <NUM>, including transmitting a replay signal to a transmitter. For example, referring to <FIG>, the error detection circuit <NUM> may detect an error in a received flit. The replay circuit <NUM> may determine that the RX replay buffer <NUM> has sufficient available space for a replay process, and may then transmit a replay signal to the transmitter <NUM>.

Referring again to <FIG>, block <NUM> may include determining a drain time based on an occupancy metric of the transmitter replay buffer. Block <NUM> may include determining an average number of data units that have been transmitted to the receiver. Block <NUM> may include determining an NOP insertion rate based on the drain time (determined at block <NUM>) and the average number of data units (determined at block <NUM>). For example, referring to <FIG>, the latency circuit <NUM> may calculate a drain time (DT) based on a current occupancy of the TX replay buffer <NUM>. Further, the latency circuit <NUM> may access or read the replay tracker <NUM> to determine the average number of received data units between successive replay signals (AvgR) sent by the replay circuit <NUM>. The latency circuit <NUM> may then determine an NOP insertion rate based on the drain time DT and the average number AvgR (e.g., by matching <NUM> the drain time to a particular entry of the look-up table <NUM>, as shown in <FIG>).

Referring again to <FIG>, block <NUM> may include transmitting NOP messages to the receiver circuit <NUM> according to the NOP insertion rate (determined at block <NUM>). Block <NUM> may include draining the receiver replay buffer using the NOP messages received from the transmitter. After block <NUM>, the method <NUM> may be completed. For example, referring to <FIG>, the latency circuit <NUM> may insert NOP messages (e.g., NOP flits) into the data transmitted to the receiver circuit <NUM> according to the determined NOP insertion rate. Receiving and/or processing the NOP messages may allow the RX replay buffer <NUM> to be drained.

Embodiments may be implemented in a variety of other computing platforms. Referring now to <FIG>, shown is a block diagram of a system in accordance with another embodiment. As shown in <FIG>, a system <NUM> may be any type of computing device, and in one embodiment may be a server system such as an edge platform. In the embodiment of <FIG>, system <NUM> includes multiple CPUs 610a,b that in turn couple to respective system memories 620a,b which in embodiments may be implemented as double data rate (DDR) memory. Note that CPUs <NUM> may couple together via an interconnect system <NUM>, which in an embodiment can be an optical interconnect that communicates with optical circuitry (which may be included in or coupled to CPUs <NUM>).

To enable coherent accelerator devices and/or smart adapter devices to couple to CPUs <NUM> by way of potentially multiple communication protocols, a plurality of interconnects 630a1-b2 may be present. In an embodiment, each interconnect <NUM> may be a given instance of a Compute Express Link (CXL) interconnect.

In the embodiment shown, respective CPUs <NUM> couple to corresponding field programmable gate arrays (FPGAs)/accelerator devices 650a,b (which may include graphics processing units (GPUs), in one embodiment. In addition CPUs <NUM> also couple to smart network interface circuit (NIC) devices <NUM> a,b. In turn, smart NIC devices 660a,b couple to switches 680a,b that in turn couple to a pooled memory 690a,b such as a persistent memory.

Referring now to <FIG>, shown is a block diagram of a system in accordance with another embodiment such as an edge platform. As shown in <FIG>, multiprocessor system <NUM> includes a first processor <NUM> and a second processor <NUM> coupled via an interconnect <NUM>, which in an embodiment can be an optical interconnect that communicates with optical circuitry (which may be included in or coupled to processors <NUM>). As shown in <FIG>, each of processors <NUM> and <NUM> may be many core processors including representative first and second processor cores (i.e., processor cores 774a and 774b and processor cores 784a and 784b).

In the embodiment of <FIG>, processors <NUM> and <NUM> further include point-to point interconnects <NUM> and <NUM>, which couple via interconnects <NUM> and <NUM> (which may be CXL buses) to switches <NUM> and <NUM>. In turn, switches <NUM>, <NUM> couple to pooled memories <NUM> and <NUM>.

Still referring to <FIG>, first processor <NUM> further includes a memory controller hub (MCH) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, second processor <NUM> includes a MCH <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MCH's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor <NUM> and second processor <NUM> may be coupled to a chipset <NUM> via P-P interconnects <NUM> and <NUM>, respectively. As shown in <FIG>, chipset <NUM> includes P-P interfaces <NUM> and <NUM>.

Furthermore, chipset <NUM> includes an interface <NUM> to couple chipset <NUM> with a high performance graphics engine <NUM>, by a P-P interconnect <NUM>. As shown in <FIG>, various input/output (I/O) devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. Various devices may be coupled to second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication devices <NUM> and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to second bus <NUM>.

Referring now to <FIG>, shown is a flow diagram of a method <NUM> performed by a receiver, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., receiver circuit <NUM>, and hint circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include determining, by a receiver circuit, whether the receiver circuit is operating in a high latency processing mode. Block <NUM> may include, in response to a determination that the receiver circuit is operating in the high latency processing mode, the receiver circuit transmitting a hint signal to a transmitter circuit.

Block <NUM> may include receiving, by the receiver circuit, a response message from the transmitter circuit. Block <NUM> may include processing, by the receiver circuit, the response message to reduce a current workload of the receiver circuit. Block <NUM> may include, in response to a reduction of the current workload of the receiver circuit, switching the receiver circuit from operating in the high latency processing mode to operating in a low latency processing mode.

For example, referring to <FIG>, the hint circuit <NUM> of the receiver circuit <NUM> may transmit a hint message in response to determining that the receiver circuit <NUM> is operating in the high latency operating mode and has not sent any hint message in a recent period. The receiver circuit <NUM> may receive a response message that was transmitted by the response circuit <NUM> in response to the hint message from the hint circuit <NUM>. Receiving and/or processing the response message may cause the receiver circuit <NUM> to not schedule any new work, and may therefore allow the high latency path <NUM> to be drained of its pending work.

Referring now to <FIG>, shown is a flow diagram of a method <NUM> performed by a transmitter circuit, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., transmitter circuit <NUM>, and response circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include receiving, by a transmitter circuit, a hint signal from a receiver circuit, the hint signal to indicate that the receiver circuit is operating in a high latency processing mode. Block <NUM> may include, in response to a receipt of the hint signal from the receiver circuit, the transmitter circuit transmitting a response message to the receiver circuit.

For example, referring to <FIG>, the response circuit <NUM> may receive from the hint circuit <NUM> a hint message indicating that the receiver circuit is operating in a high latency processing mode. In response to the hint message, the response circuit <NUM> may transmit a response message to be transmitted to the receiver circuit <NUM>.

Referring now to <FIG>, shown is a flow diagram of a method <NUM> performed by a transmitter circuit, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., transmitter circuit <NUM> and latency circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include receiving, by a transmitter circuit, a replay signal indicating that a receiver circuit has detected an error in a data transmission from the transmitter circuit to the receiver circuit. Block <NUM> may include, in response to a receipt of the replay signal, the transmitter circuit determining an occupancy of a replay buffer associated with the data transmission.

Block <NUM> may include determining, by the transmitter circuit, an average number of data units associated with the data transmission. Block <NUM> may include transmitting, by the transmitter circuit to the receiver circuit, a set of one or more no-operation messages based on the determined occupancy of the replay buffer and the determined average number of data units.

For example, referring to <FIG>, the latency circuit <NUM> of the transmitter circuit <NUM> may receive a replay signal from a replay circuit <NUM> of the receiver circuit <NUM>. The latency circuit <NUM> may calculate a drain time (DT) based on a current occupancy of the transmitter replay buffer <NUM>, and may determine the average number of received data units between successive replay signals (AvgR) sent by the replay circuit <NUM>. The latency circuit <NUM> may then determine an NOP insertion rate based on the drain time DT and the average number AvgR. Further, the latency circuit <NUM> may insert NOP messages (e.g., NOP flits) into the data transmitted to the receiver circuit <NUM> according to the determined NOP insertion rate.

Referring now to <FIG>, shown is a flow diagram of a method <NUM> performed by a receiver circuit, in accordance with one or more embodiments. In various embodiments, the method <NUM> may be performed by processing logic (e.g., transmitter circuit <NUM>, and replay circuit <NUM> shown in <FIG>) that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software and/or firmware (e.g., instructions run on a processing device), or a combination thereof. In firmware or software embodiments, the method <NUM> may be implemented by computer executed instructions stored in a non-transitory machine-readable medium, such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method.

Block <NUM> may include detecting, by a receiver circuit, an uncorrectable error in a data unit received from a transmitter circuit. Block <NUM> may include determining, by the receiver circuit, whether a replay buffer has sufficient available space. Block <NUM> may include, in response to a detection of the uncorrectable error and a determination that the replay buffer has sufficient available space, the receiver circuit transmitting a replay signal for the received data unit to the transmitter circuit.

For example, referring to <FIG>, the error detection circuit <NUM> of the receiver circuit <NUM> may detect an error in a received flit. The replay circuit <NUM> of the receiver circuit <NUM> may determine that the receiver replay buffer <NUM> has sufficient available space for a replay process, and may then transmit a replay signal to the transmitter <NUM>. The latency circuit <NUM> may then determine an NOP insertion rate (e.g., using method <NUM> shown in <FIG>), and may transmit NOP messages to the receiver circuit <NUM> according to the determined NOP insertion rate.

Referring now to <FIG>, shown is a storage medium <NUM> storing executable instructions <NUM>. In some embodiments, the storage medium <NUM> may be a non-transitory machine-readable medium, such as an optical medium, a semiconductor, a magnetic storage device, and so forth. The executable instructions <NUM> may be executable by a processing device. Further, the executable instructions <NUM> may be used by at least one machine to fabricate at least one integrated circuit to perform one or more of the methods and/or operations shown in <FIG>.

Note that, while <FIG> illustrate various example implementations, other variations are possible. For example, the examples shown in <FIG> are provided for the sake of illustration, and are not intended to limit any embodiments. Specifically, while embodiments may be shown in simplified form for the sake of clarity, embodiments may include any number and/or arrangement of components. For example, it is contemplated that some embodiments may include any number of components in addition to those shown, and that different arrangement of the components shown may occur in certain implementations. Furthermore, it is contemplated that specifics in the examples shown in <FIG> may be used anywhere in one or more embodiments.

Understand that various combinations of the above examples are possible. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Claim 1:
An apparatus comprising:
a receiver circuit (<NUM>) configured to:
in response to a determination that the receiver circuit (<NUM>) is in a high latency processing mode, transmit a hint signal to a transmitter circuit (<NUM>), the hint signal to indicate to the transmitter circuit (<NUM>) that the receiver circuit (<NUM>) is operating in the high latency processing mode;
receive a response message from the transmitter circuit (<NUM>);
process data units received from the transmitter circuit (<NUM>) using the response message to complete work pending at the receiver circuit (<NUM>); and
switch the receiver circuit (<NUM>) from the high latency processing mode to a low latency processing mode,
wherein the receiver circuit (<NUM>) is further configured to:
identify a number of data units received from the transmitter circuit (<NUM>) since a previous hint signal was transmitted by the receiver circuit (<NUM>) to the transmitter circuit (<NUM>);
compare the number of data units to a threshold value; and
transmit the hint signal in response to a determination that the number of data units exceeds the threshold value.