Patent Description:
Currently, stacked integrated circuit (IC) package assemblies may include package-on-package (PoP) configurations in which first and second packages are stacked together, one on the other, with electrical connections between them. For example, the first package may include a processor and the second package may include a memory component. Incidental electrical coupling, such as crosstalk and electromagnetic interference (EMI), may occur as signals are transmitted between the packages.

<CIT> describes a package-on-package (PoP). The top package in the PoP comprises a ground plane. The ground plane is situated in the PoP between the die embedded in the top package and the die embedded in the bottom package.

<CIT> describes a package that includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.

More particularly, <CIT> discloses a stacked package assembly comprising:.

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made. Aspects of the invention are as set out in the appended independent claims and optional features in the dependent claims.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.

In various embodiments, the phrase "a first layer formed on a second layer" may mean that the first layer is formed over the second layer, and at least a part of the first layer may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other layers between the first layer and the second layer) with at least a part of the second layer.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature," may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

<FIG> schematically illustrates a cross-section side view of an example stacked integrated circuit (IC) package assembly (hereinafter "package assembly <NUM>"), in accordance with some embodiments. The package assembly <NUM> includes a first package <NUM> and a second package <NUM> that are stacked together, one on the other. First package <NUM> may be referred to as a base package and includes one or more dies <NUM> (e.g., only one shown), and second package <NUM> may be referred to as a top package and includes one or more dies <NUM> (e.g., two dies shown). One or more dies <NUM> include one or more logic dies such as, for example, a processor, CPU, or ASIC, and one or more dies <NUM> may include one or more memory dies such as, for example, low power double data rate memory. Dies <NUM> may be constructed to perform other functions in other embodiments.

In the example of package assembly <NUM>, first package <NUM> may include multiple layers, such as layers L1-<NUM>, L1-<NUM>, L1-<NUM>, L1-<NUM>, L1-<NUM>, or more or fewer layers, which may include arrangements of insulative and conductive materials. Second package <NUM> may include multiple layers, such as layers L2-<NUM>, L2-<NUM>, or more or fewer layers, which may include arrangements of insulative and conductive materials. Multiple electrical couplings <NUM> provide electrical connection between first package <NUM> and second package <NUM>, and multiple electrical couplings <NUM> may provide electrical connection between package assembly <NUM> and other devices, such as through connection to a printed circuit board, for example. Electrical couplings <NUM> and <NUM> may each include a ball grid array integrated circuit package, or any other suitable type of integrated circuit coupling or packaging.

Package assembly <NUM> also includes a conductive voltage reference plane <NUM> that is embedded in the first die package <NUM>. Voltage reference plane <NUM> is in proximity to and generally parallel to the second package <NUM>. In the example of package assembly <NUM>, voltage reference plane <NUM> may be embedded in a dielectric <NUM> at layer L1-<NUM> of first package <NUM> in proximity to second package <NUM>. Voltage reference plane <NUM> has applied to it one or more reference or shielding voltages.

<FIG> is a sectional top view of first package <NUM> illustrating voltage reference plane <NUM>, which extends substantially across first package <NUM> and includes a major aperture <NUM> for one or more dies <NUM>. The one or more dies <NUM> extend at least partly through major aperture <NUM>. Voltage reference plane <NUM> may further include one or more minor apertures <NUM> through which one or more electrical connections or vias <NUM> may pass through voltage reference plane <NUM> in electrical isolation from it.

Voltage reference plane <NUM> may include one or more portions or sub-planes <NUM> that are co-planar with and electrically isolated from each other. In the example of <FIG>, voltage reference plane <NUM> may include four sub-planes 130A-130D that may be arranged in a rectangular (e.g., square) array. It will be appreciated that voltage reference plane <NUM> may include more, fewer, or no sub-planes, and that any sub-planes may be configured and arranged in any manner. Voltage reference plane <NUM> includes one or more electrical connections to one or more reference voltages, such as a source voltage Vss, in one embodiment.

Voltage reference plane <NUM> may provide embedded shielding at layer L1-<NUM> of first package <NUM> that may mitigate incidental electrical coupling, such as crosstalk and electromagnetic interference (EMI), as signals are transmitted between packages <NUM> and <NUM> through electrical couplings <NUM> and electrical connections <NUM>. In embodiments, voltage reference plane <NUM> may provide increased signal-to-ground ratios in signals transmitted between packages <NUM> and <NUM>, may provide or allow increased density of interconnections between packages <NUM> and <NUM> of package assembly <NUM>, and may provide improved signal quality through vertical and horizontal voltage (e.g., ground) referencing without increasing the number of layers in or stacked (z-axis) height of the package assembly. The voltage reference plane <NUM> may also provide high data-rate scalability through robust noise shielding and voltage (e.g., ground) referencing and may provide a reduced package foot-print by reduction in number of reference voltage (e.g., Vss) interconnects.

The dies <NUM> and/or <NUM> may represent or include discrete products made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like used in connection with forming complementary metal-oxide semiconductor (CMOS) devices. In some embodiments, the dies <NUM> and/or <NUM> may be, include, or be a part of a processor, memory, system on a chip (SoC) or application-specific IC (ASIC). In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of the dies <NUM> and/or <NUM>.

<FIG> schematically illustrate various stages of fabrication of an example stacked IC package assembly <NUM> (<FIG>, hereinafter "package assembly <NUM>") that includes integrated circuit packages <NUM>, <NUM> (<FIG>) that are stacked together, in accordance with some embodiments. <FIG> schematically illustrate various stages of fabrication of an example first package <NUM> of package assembly <NUM>, in reference to a two-sided fabrication technique. In other embodiments first package <NUM> could be fabricated in a one-sided fabrication technique. The package assembly <NUM>, packages <NUM>, <NUM>, and their components, including dies, may comport with embodiments described in connection with package assembly <NUM>, packages <NUM>, <NUM>, and their components, including dies, and vice versa.

<FIG> depicts a core material <NUM> with applied or laminated layers <NUM>, <NUM> which may be of a metal such as, for example, copper, and may function as a fabrication carrier <NUM> to facilitate handling of first packages <NUM> during fabrication.

<FIG> depicts a pair of first packages <NUM> subsequent to coupling contact carriers <NUM> to fabrication carrier <NUM>. Contact carriers <NUM> and fabrication carrier <NUM> may be coupled using any suitable technique and may form die attachment recesses or cavities <NUM> and may provide contact pads <NUM>, such as ball grid array pads, for example.

<FIG> depicts dies <NUM> mounted in die attachment recesses or cavities <NUM> as first packages <NUM>.

<FIG> depicts first packages <NUM> subsequent to application or lamination of embedding or encapsulating dielectric layers <NUM>.

<FIG> depicts first packages <NUM> in which dielectric layers <NUM> may be exposed for etching with respect to a reference voltage plane etch mask or pattern <NUM>, an embodiment of which is shown in plan in <FIG>. Etching of dielectric layers <NUM> may be done in any suitable manner including photolithography, plasma, UV, or laser etching, etc., according to mask or pattern <NUM>.

<FIG> depicts first packages <NUM>, in which each includes reference voltage plane <NUM>, an embodiment of which may be shown in <FIG> and may include sub-plane 229A-229D. Reference voltage plane <NUM> may be formed in any suitable manner such as an electroplating process, which may include electroless or electrolytic processing.

<FIG> depicts first packages <NUM>, which may include formation of one or more package assembly via paths <NUM>, to contact pads <NUM>, for example, and one or more reference voltage plane vias <NUM>. Via paths <NUM> and recesses for vias <NUM> may be formed in any suitable manner such as dielectric lamination in combination with an etching process such as UV or CO2 laser etching. <FIG> depicts a sectional top view of a first package <NUM> of <FIG>.

<FIG> depicts first packages <NUM> with electrical connections <NUM> made between package assembly vias <NUM> and reference voltage plane vias <NUM> through which to apply one or more reference voltages to reference voltage planes <NUM>, for example, or to provide other electrical connections. In embodiments formation of electrical connections <NUM> may be semi-additive and may employ an electroplating process. The one or more reference voltages may include a source voltage Vss.

<FIG> depicts first packages <NUM>, which may include multiple additional layers such as, for example, layers L1-<NUM> through L1-<NUM>, which may be formed with successive dielectrics <NUM>, metal layers <NUM>, and vias or micro-vias.

<FIG> depicts first packages <NUM>, which may include solder resist layers <NUM> and solder resist openings <NUM> to solder contact pads <NUM>. Solder resist layers <NUM> and solder resist openings <NUM> may be formed in a build-up process of solder resist film lamination, photolithography, and etching.

<FIG> depicts singulation and panel separation of first packages <NUM>, which may include sawing or other separating or cutting along separation lines <NUM>.

<FIG> depicts a singulated and panel-separated first package <NUM>.

<FIG> depicts first package after removal of fabrication carrier <NUM>, which may be removed by an etching process or peeling removal and may provide access to one or more package assembly contact pads <NUM>.

<FIG> depicts formation of conductive attachments <NUM>, such as solder balls, to solder contact pads <NUM>. In embodiments, conductive attachments <NUM> may be formed by a solder ball placement and reflow process and may be for connection to a ball grid array integrated circuit package or another suitable package.

<FIG> depicts a first package <NUM> and second package <NUM> stacked together as stacked package assembly <NUM> with package assembly connections <NUM>, which may include a surface mounting technology. In embodiments, the stacked package assembly <NUM> may include a package-on-package (POP) device.

<FIG> schematically illustrates a flow diagram for a method <NUM> of fabricating a stacked IC package assembly, in accordance with some embodiments. The method <NUM> may comport with techniques and/or configurations described in connection with <FIG> and vice versa.

At <NUM>, the method <NUM> may include providing a fabrication carrier (e.g., fabrication carrier <NUM> of <FIG>) to facilitate handling of a first package (e.g., packages <NUM> of <FIG>) during fabrication. At <NUM>, the method <NUM> may include coupling a contact carrier to the fabrication carrier (e.g., contact carrier <NUM> coupled to fabrication carrier <NUM> of <FIG>). In embodiments, the contact carrier may include a recess or cavity (e.g., cavity <NUM> of <FIG>). At <NUM>, the method <NUM> may include coupling a first die (e.g., die <NUM> of <FIG>) to the fabrication carrier. In embodiments, the die may be coupled in a recess of the contact carrier (e.g., die <NUM> in recess <NUM> of <FIG>).

At <NUM>, the method <NUM> may include depositing a die encapsulant or embedding material (e.g., dielectric material <NUM> of <FIG>) in the cavity. In some embodiments, depositing the die encapsulant material in the cavity may be performed by applying a laminate layer (e.g., dielectric material <NUM> of <FIG>) on the fabrication carrier and hot pressing the laminate layer to couple the laminate layer with the fabrication carrier and substantially fill the cavity with the laminate layer.

At <NUM>, the method <NUM> may include exposing the laminate layer for etching with respect to a reference voltage plane etch mask or pattern (e.g., reference voltage plane etch mask or pattern <NUM> of <FIG>). Exposing the laminate layer for etching may be done in any suitable manner including photolithography, plasma, UV, or laser etching, etc..

At <NUM>, the method <NUM> includes forming a conductive reference voltage plane (e.g., reference voltage plane <NUM> of <FIG>). The reference voltage plane may be formed in any suitable manner such as an electroplating process, which may include electroless or electrolytic processing.

At <NUM>, the method <NUM> may include forming one or more vias through the reference voltage plane (e.g., one or more package assembly vias <NUM> and/or one or more reference voltage plane vias <NUM> of <FIG>). In embodiments, the one or more vias may provide electrical couplings through the reference voltage plane and may be formed in any suitable manner such as dielectric lamination in combination with an etching process such as UV or CO2 laser etching.

At <NUM>, the method <NUM> includes forming electrical connections through which to provide one or more reference voltages to the reference voltage plane (e.g. electrical connection <NUM> of <FIG>). At <NUM>, the method <NUM> includes formation of one or more additional layers of the first package (e.g., <FIG>).

At <NUM>, the method <NUM> includes coupling the first package with a second package as a stacked IC package assembly (e.g., stacked package assembly <NUM> of <FIG>).

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order-dependent. For example, actions of the method <NUM> may be performed in another suitable order than depicted.

Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software. <FIG> schematically illustrates a computing device <NUM> that may include a stacked IC package assembly as described herein, in accordance with some embodiments. The computing device <NUM> may house a board such as motherboard <NUM>. The motherboard <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> may be physically and electrically coupled to the motherboard <NUM>. In some implementations, the at least one communication chip <NUM> may also be physically and electrically coupled to the motherboard <NUM>. In further implementations, the communication chip <NUM> may be part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The processor <NUM> of the computing device <NUM> may be packaged in a stacked IC package assembly with a memory, as described herein, and/or other components may be packaged together in a stacked IC package assembly with a memory, as described herein.

The communication chip <NUM> may enable wireless communications for the transfer of data to and from the computing device <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments.

Claim 1:
A stacked package assembly (<NUM>) comprising:
a first die package (<NUM>) and a second die package (<NUM>) stacked one upon the other with plural interconnections (<NUM>) between them, wherein the first die package (<NUM>) comprises a first embedded logic die (<NUM>) and wherein the second die package (<NUM>) comprises a second embedded die (<NUM>); and
a voltage reference plane (<NUM>) embedded in the first die package (<NUM>) and in proximity and parallel to the second die package (<NUM>), wherein the voltage reference plane (<NUM>) comprises an aperture (<NUM>) through which the embedded logic die (<NUM>) at least partly extends and wherein the voltage reference plane (<NUM>) substantially encompasses the first die package (<NUM>).