Patent Description:
Semiconductor memory device such as a low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM) is widely used in mobile devices, such as mobile phones, portable computers, and the like. The LPDDR SDRAM is a highspeed synchronous SDRAM device internally configured with <NUM> channel, and may support multiple bank architectures to provide optimal access methods for varied system configurations. Furthermore, the burst length determined by data prefetch size depends on which bank architecture is used.

<CIT> and <CIT> disclose electronic systems comprising a memory device, comprising a plurality of bank groups, wherein each of the bank groups comprises a plurality of memory banks, and a controller coupled to the memory device and configured to access the memory device with a data rate. Data of the memory device can be accessed according to short and long burst commands, wherein the short burst commands correspond to a short burst length and the long burst commands correspond to a long burst length that is twice the short burst length. Further, <CIT> discloses that a controller coupled to a memory device and configured to access the memory device with a data rate comprises a request queue configured to store a plurality of requests.

As operating systems (OS) become larger to support multitasking, the memory devices of the electronic systems (e.g., the mobile devices) need to efficiently operate at higher speed.

An electronic system and a method according to the invention are defined in the independent claims. The dependent claims define preferred embodiments thereof.

The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense.

<FIG> shows an electronic system <NUM> according to some embodiments of the invention. The electronic system <NUM> may be a mobile device, such as a mobile phone, a portable computer (e.g., a lap top computer, a tablet computer), a wearable device, and the like. The electronic system <NUM> includes a processor <NUM>, a controller <NUM> and a memory device <NUM>. The processor <NUM> is coupled to the controller <NUM> through an interconnect (e.g., a bus) <NUM>, and the controller <NUM> is coupled to the memory device <NUM> through an interconnect (e.g., a bus) <NUM>. The processor <NUM> is a requester in the electronic system <NUM> that needs to access data in the memory device <NUM> for performing various applications. In order to simplify the description, only the processor <NUM> is described as the requester in the electronic system <NUM>, and other requesters (e.g., central processing unit (CPU), digital signal processor (DSP), graphic processing unit (GPU), etc.) that need to access the memory device <NUM> in the electronic system <NUM> will be omitted. The memory device <NUM> is a low power memory device that consumes less power for the electronic system <NUM>. For example, the memory device <NUM> may be a low-power double data rate synchronous dynamic random access memory (LPDDR SDRAM).

Preferably, the memory device <NUM> may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a Rambus dynamic random access memory (RDRAM), and so on. Preferably, the electronic system <NUM> includes a plurality of memory devices <NUM>, and the controller <NUM> is configured to control data exchange between the processor <NUM> (or various requesters) and the plurality of memory devices <NUM>.

<FIG> shows a block diagram of the controller <NUM> and the memory device <NUM> of <FIG> according to some embodiments of the invention. The controller <NUM> includes a request queue <NUM>, and the request queue <NUM> is configured to store the requests REQ1 through REQn from the processor <NUM> or other requesters (not shown) of the electronic system <NUM>. Preferably, the requests REQ1 through REQn are provided by the same requester. Alternatively preferably, the requests REQ1 through REQn are provided by multiple requesters. In response to the requests REQ1 through REQn, the controller <NUM> is configured to access the memory device <NUM> with a data rate through the interconnect <NUM>. The memory device <NUM> includes multiple bank groups BG0 through BG3. Each of the bank groups BG0 through BG3 includes multiple memory banks <NUM>, e.g., <NUM> memory banks. According to the requests REQ1 through REQn queued in the request queue <NUM>, the controller <NUM> is configured to dynamically control the burst length corresponding to the data and commands, so as to access the memory device <NUM> efficiently.

It should be noted that the number of bank groups and the number of memory banks shown in <FIG> are only an example, and the invention should not be limited thereto.

The interconnect <NUM> includes multiple transmission lines for transfer the command/address CA, the clock CK, the data DQ, and the data clock WCK. In order to simplify the description, <FIG> shows only a portion of the signals in the interconnect <NUM>. The controller <NUM> is configured to provide the clock CK, the command/address CA and the data clock WCK to the memory device <NUM> through unidirectional transmission lines in the interconnect <NUM>. Preferably, the frequency of the data clock WCK is twice that of the clock CK. Furthermore, the controller <NUM> is configured to provide the data DQ to the memory device <NUM> during write operations and receive the data DQ from the memory device <NUM> during read operations through bidirectional transmission lines in the interconnect <NUM>. The command/address CA includes the command information corresponding to read or write operation, burst length and so on, and the address information corresponding to row address, column address, bank group and so on. The clock CK is configured to sample (or capture) the command/address CA for the memory device <NUM>. Preferably, the clock CK is a pair of differential signals. The data clock WCK is used for capturing the data DQ during the write operations and outputting the data DQ during the read operations on the memory device <NUM>. Preferably, the data clock WCK is a pair of differential signals.

<FIG> shows a method <NUM> for dynamically controlling burst length of commands to access the memory device <NUM> according to some embodiments of the invention. When accessing the memory device <NUM> by the controller <NUM>, the burst length of the memory device <NUM> is set (or programmed) by the access command (e.g., the read/write command) from the controller <NUM>.

First, in step S210, the controller <NUM> is configured to obtain the requests REQ1 through REQn queued in the request queue <NUM>. Preferably, the requests REQ1 through REQn are issued by the same requester (e.g., the processor <NUM> in <FIG>). Alternatively preferably, the requests REQ1 through REQn are issued by two or more requesters (not shown). Next, in step S220, the controller <NUM> is configured to determine whether the memory device <NUM> is operating at a high data rate, i.e., the data rate of the memory device <NUM> is greater than a specific data rate (e.g., 4800Nbps). If the memory device <NUM> is operating at a low data rate, e.g., the data rate of the memory device <NUM> is less than or equal to the specific data rate, the controller <NUM> is configured to schedule data and commands in a first burst mode (step S230), so as to issue the long burst commands (e.g., read/write command) to access data (e.g., read/write data) with a long burst length BLyin response to the requests REQ1 through REQn.

In the first burst mode, in response to one request, the corresponding data is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK, and the corresponding command is issued to the memory device <NUM> on successive clock cycles of the clock CK. Furthermore, the clock cycles of the data clock WCK is determined according to the long burst length BLy. For example, the clock cycles of the data clock WCK is equal to the long burst length BLy. The operation of the first burst mode is described in <FIG> below.

In flowchart of the method <NUM>, if the memory device <NUM> is operating at a high data rate (step S220), i.e., the data rate of the memory device <NUM> is greater than the specific data rate, the controller <NUM> is configured to determine whether the requests REQ1 through REQn correspond to different bank groups. i.e., multiple bank groups are accessed in response to the requests REQ1 through REQn (step S240).

If the requests REQ1 through REQn correspond to at least two bank groups (step S240), the controller <NUM> is configured to schedule data and commands in a second burst mode (step S250), so as to interleave two long burst commands to access data (e.g., read/write data) with a short burst length BLx in response to two of the requests REQ1 through REQn corresponding to the different bank groups.

In the second burst mode, in response to one request, the corresponding data is divided (or split) into two portions and separately transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK, and the corresponding command is transferred to the memory device <NUM> on successive clock cycles of the clock CK along with the portion of the divided data transferred first. Furthermore, the clock cycles of the data clock WCK corresponding to each portion of the divided data is determined according to the short burst length BLx. For example, the clock cycles of the data clock WCK corresponding to each portion of the divided data is equal to the short burst length BLx. A portion of the data corresponding to another request of another bank group is inserted between two portions of the divided data. The operation of the second burst mode is described in <FIG> below.

In flowchart of the method <NUM>, if the requests REQ1 through REQn correspond to the same bank group (step S240), the controller <NUM> is configured to schedule data and commands in a third burst mode (step S260), so as to reorganize a long burst command as two short burst commands in response to the requests REQ1 through REQn, and then issue the two short burst commands to access data (e.g., read/write data) with the short burst length BLx.

In the third burst mode, in response to one request, the corresponding data is divided (or split) into two portions and separately transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK, and the corresponding short burst command is transferred to the memory device <NUM> on successive clock cycles of the clock CK along with each portion of the divided data. Furthermore, the clock cycles of the data clock WCK corresponding to each portion of the divided data is determined according to the short burst length BLx. For example, the clock cycles of the data clock WCK corresponding to each portion of the divided data is equal to the short burst length BLx. In the third burst mode, no data corresponding to another queued request in the request queue <NUM> is inserted between the portions of the divided data. The operation of the third burst mode is described in <FIG> below.

<FIG> shows a diagram illustrating the signals of the interconnect <NUM> in the first burst mode according to some embodiments of the invention. It is assumed that the controller <NUM> is configured to perform read/write operation in response to the request REQ1 of <FIG>. When operating in the first burst mode, the controller <NUM> is configured to access the data of the memory device <NUM> with the long burst length BLy according to the read/write (RD/WR) command <NUM> in response to the request REQ1. Furthermore, the read/write command <NUM> is a long burst command, and the burst length of the memory device <NUM> is set by the read/write command <NUM>. In the time interval tBLy, the read/write command <NUM> corresponding to the request REQ1 is issued to initiate a burst read/write operation for the memory device <NUM>, and the data <NUM> is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK. Furthermore, the clock cycles of the data clock WCK in the time interval tBLy is determined according to the long burst length BLy. Preferably, the clock cycles of the data clock WCK is <NUM>, and the data <NUM> is <NUM> bytes of data in the data DQ.

<FIG> shows a diagram illustrating the signals of the interconnect <NUM> in the second burst mode according to some embodiments of the invention. It is assumed that the controller <NUM> is configured to perform read/write operations in response to the requests REQ1 and REQ2 in <FIG>, and the requests REQ1 and REQ2 correspond to the bank groups BG0 and BG1 of <FIG>, respectively. When operating in the second burst mode, the controller <NUM> is configured to access the data of the memory device <NUM> with the short burst length BLx according to the read/write (RD/WR) commands <NUM> and <NUM> in response to the requests REQ1 and REQ2. The read/write commands <NUM> and <NUM> are the long burst commands. Moreover, the long burst length BLy is twice the short burst length BLx, i.e., BLy= <NUM>* BLx.

In <FIG>, the burst length of the memory device <NUM> is set by the read/write commands <NUM> and <NUM>. First, the read/write command <NUM> corresponding to the request REQ1 is issued to initiate a burst read/write operation for the bank group BG0 of the memory device <NUM>, and the portion of data 251_1 of the bank group BG0 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx. In other words, the portion of data 251_1 is transferred simultaneously with the read/write command <NUM>. Furthermore, the clock cycles of the data clock WCK in the time interval tBLx is determined according to the short burst length BLx. Preferably, the clock cycles of the data clock WCK is <NUM>. Seamlessly, the read/write command <NUM> corresponding to the request REQ2 is issued to initiate a burst read/write operation for the bank group BG1 of the memory device <NUM>, and the portion of data 253_1 of the bank group BG1 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx. In other words, the portion of data 253_1 is transferred simultaneously with the read/write command <NUM>. Seamlessly, in response to the read/write command <NUM>, the remainder of data 251_2 of the bank group BG0 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx. Seamlessly, in response to the read/write command <NUM>, the remainder of data 253_2 of the bank group BG1 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx. In such embodiments, in response to each of the requests REQ1 and REQ2, the controller <NUM> is configured to only issue a single command (i.e., the long burst command <NUM> or <NUM>) to the memory device <NUM>, although multiple portions of data are sent separately. In other words, while the remainder of data 251_2 and the remainder of data 253_2 are transferred, no command is issued by the controller <NUM>.

In <FIG>, the data of the bank group BG0 and the data of the bank group BG1 of the memory device <NUM> are transferred alternately, i.e., the data of the bank groups BG0 and BG1 are interleaved in the data DQ. In such embodiment, the data of the bank group BG0 is <NUM> bytes of data in the data DQ, and is divided into the first portion of data 251_1 and the second portion of data 251_2. Similarly, the data of the bank group BG1 is <NUM> bytes of data in the data DQ, and is divided into the first portion of data 253_1 and the second portion of data 253_2. Furthermore, the controller <NUM> is configured to control the data 251_1, 253_1, 251_2 and 253_2 are seamlessly transferred in sequence. Thus, the data bus efficiency of the data DQ is optimized when the read/write commands of different bank groups interleaved.

<FIG> shows a diagram illustrating the signals of the interconnect <NUM> in the third burst mode according to some embodiments of the invention. It is assumed that the controller <NUM> is configured to perform read/write operations in response to the request REQ2 in <FIG>, and the requests REQ1 through REQn correspond to the same bank group BG2 of <FIG>. When operating in the third burst mode, the controller <NUM> is configured to access the data of the memory device <NUM> with the short burst length BLx according to the read/write (RD/WR) commands 265_1 and 265_2 in response to the request REQ2. Furthermore, the read/write commands 265_1 and 265_2 are the short burst commands.

In <FIG>, the burst length of the memory device <NUM> is set by the read/write command <NUM>. First, the read/write command 265_1 corresponding to the request REQ2 is issued to initiate a burst read/write operation for the bank group BG2 of the memory device <NUM>, and the first portion of data 261_1 of the bank group BG2 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx. Next, when a column-to-column or command-to-command delay time tCCD is reached, the read/write command 265_2 corresponding to the same request REQ2 is issued to initiate a burst read/write operation for the bank group BG2 of the memory device <NUM>, and the second portion of data 261_2 of the bank group BG2 is transferred to or from the memory device <NUM> on successive clock cycles of the data clock WCK in the time interval tBLx.

The read/write commands 265_1 and 265_2 are reorganized to sequential addresses of the bank group BG2. The clock cycles of the data clock WCK in the time interval tBLx is determined according to the short burst length BLx. Preferably, the clock cycles of the data clock WCK is <NUM>. In the third burst mode, in response to the request REQ2, the controller <NUM> is configured to separate one long burst command into two short burst commands (e.g., the read/write commands 265_1 and 265_2), and then continuously issue the two short burst commands to the memory device <NUM>. In general, the delay time tCCD can be understood as the timing between consecutive access commands.

In <FIG>, the data of the bank group BG2 in the memory device <NUM> is transferred separately. In such embodiment, the data of the bank group BG2 is <NUM> bytes of data in the data DQ, and is divided into the first portion of data 261_1 and the second portion of data 261_2. Furthermore, the controller <NUM> is configured to transferred the data 261_1 and 251_2 in sequence according to the column-to-column or command-to-command delay time tCCD.

Claim 1:
An electronic system (<NUM>), comprising:
a memory device (<NUM>), comprising a plurality of bank groups (BG_0 - BG3), wherein each of the bank groups (BG_0 - BG3) comprises a plurality of memory banks (<NUM>); and
a controller (<NUM>) coupled to the memory device (<NUM>) and configured to access the memory device (<NUM>) with a data rate, and comprising:
a request queue (<NUM>) configured to store a plurality of requests (REQ1 - REQn),
wherein the controller (<NUM>) is configured to:
determine whether the requests (REQ1 - REQn) correspond to different bank groups (BG0-BG_3);
in response to the requests (REQ1 - REQn) corresponding to different bank groups (BG0-BG_3), access data of the memory device (<NUM>) according to a plurality of long burst commands corresponding to the requests (REQ1 - REQn); and
in response to the requests (REQ1 - REQn) corresponding to a same bank group (BG0-BG_3), access data of the memory device (<NUM>) according to a plurality of short burst commands corresponding to the requests (REQ1 - REQn);
wherein the short burst commands correspond to a short burst length, and the long burst commands correspond to a long burst length that is twice the short burst length.