Patent Description:
A computing device (e.g., a laptop, a mobile phone, etc.) may perform various functions, such as telephony, wireless data access, and camera/video function, etc. Such computing device may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing circuits, user interface components, storage and other peripheral components that communicate through a serial communication bus. In one example, the serial communication bus may be operated in accordance with Inter-Integrated Circuit protocols, which may also be referred to as I2C protocols or I<NUM>C protocols. The I2C protocols are operable on a serial, single-ended bus used for connecting low-speed peripherals to a processor. In some examples, a serial communication bus may employ a multi-master protocol in which one or more devices can serve as a master and a slave for different messages transmitted on the serial communication bus. Data may be serialized and transmitted in a data signal carried on a Serial Data (SDA) line (SDA), in accordance with timing provided in a clock signal carried on a Serial Clock (SCL) Line. In some examples, the serial communication bus may be operated in accordance with I3C protocols defined by the Mobile Industry Processor Interface (MIPI) Alliance. The I3C protocol can increase available bandwidth on the serial communication bus through higher transmitter clock rates, by encoding data in symbols defining signaling state of two or more wires, and/or through other encoding techniques including double data rate transmissions (where data is clocked using rising and falling edges of a transmitted clock signal). Certain aspects of the I3C protocol are derived from corresponding aspects of the I2C protocol, and the I2C and I3C protocols can coexist on the same serial communication bus (e.g., on the SDA line and the SCL line).

In the past, some have tried to specify a protocol for peer-to-peer communication (direct communication between slave devices; also known as "device to device" or D2D). Some of these efforts proved inefficient, and an improved direct communication scheme between the slave devices is needed.

Attentions is drawn to the document <CIT> which describes communication systems and communication control methods. In one example, a slave device belonging to a group of devices to which arbitration is applicable sequentially transmits a start bit and a first address including a first bit having a value different from a corresponding first bit of predetermined pattern data. A master device sequentially transmits the start bit and the predetermined pattern data. The master device arbitrates the master device and the first slave device based on the value of the first bit.

In accordance with the present invention an apparatus, as set forth in claim <NUM>, is provided. Embodiments of the invention are claimed in the dependent claims.

As used herein, the term "coupled to" in the various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term "coupled to" may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" indicate having an electric current flowing between the elements A and B. In some examples, the term "electrically connected" may indicate having an electric current flowing between the elements A and B.

The terms "first," "second," "third," etc. are employed for ease of reference and may not carry substantive meanings. Likewise, names for components/modules may be adopted for ease of reference and might not limit the components/modules. For example, such non-limiting names may include "IBI handling" module, "IBI detection" module, "processing unit interrupt control" module, and/or "IBI response" module. Modules and components presented in the disclosure may be implemented in hardware, software, or a combination of hardware and software.

The term "bus system" may provide that elements coupled to the "bus system" may exchange information therebetween, directly or indirectly. In such fashion, the "bus system" may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc..

In the disclosure, the serial communication protocol may include, for example, an I3C specification. Examples of the I3C specification may include a MIPI Alliance I3C specification (e.g., the host controller being configured to operate the I3C link meeting all requirements of the MIPI I3C specification). In some examples, the I3C specification may include specifications from any standard-setting organization using part or all of an I3C link (e.g., an SCL line and an SDA line) and/or Common Command Codes provided by the MIPI Alliance I3C specification. A serial communication bus may be a link that operates in accordance with the serial communication protocol.

A direct communication scheme (e.g., peer-to-peer communication between slave devices) over a serial communication bus would improve performance of the system and reduce power consumption, since steps having a master device acting as an intermediary are eliminated. Methods and apparatuses in the disclosure are directed to an efficient, improved direct communication scheme. In one aspect of the disclosure, a master device may use an always-on module of handle the direct communication between slave devices. In such fashion, a master-slave module of the master device may enter into a low-power mode to conserve power. Such scheme might be particularly beneficial for use cases having long idle periods between the master device and the slave device. In this aspect, the specific scheme for the direct communication would not matter. For example, based on this aspect of the disclosure, the master device (e.g., the always-on module) and slave device may engage in a direct communication scheme specified by an I3C specification.

The direct communication is triggered by an existing, known interrupt followed by a direct communication address. The master device would recognize the direct communication address as such and proceed with the direct communication among the slave devices. Information including the direct communication address and a predetermined, fixed number of clocks (e.g., a data length) may be stored within the master device and/or the slave devices. In some examples, the direct communication address might not be part of an I3C specification. For example, the direct communication address might be agreed upon between master device and the slave device via Private Contracts.

In such fashion, the master device may recognize the direct communication address as triggering a direct communication and provide a number of clocks (e.g., clock pulses) based on the stored information. The requesting slave device may provide a number of data based on the stored information. According, information on the data length of the direct communication needs not to be exchanged in the disclosed direct communication scheme, further improving system performance and reducing power needed for operating the direct communication.

<FIG> illustrates components of an apparatus <NUM> with serial communication, in accordance with certain aspects of the disclosure. The apparatus <NUM> may, for example, be one of a computing system (e.g., servers, datacenters, desktop computers, mobile computing device such as laptops, cell phones, vehicles, etc.), Internet of Things device, and virtual reality or augmented reality system. The apparatus <NUM> includes a master <NUM> (e.g., master device), a serial communication bus (e.g., I3C link <NUM>), and a plurality of slaves <NUM>-<NUM> to <NUM>-N (e.g., slave devices). The plurality of slaves <NUM>-<NUM> to <NUM>-N includes a first slave <NUM>-<NUM> and a second slave <NUM>-<NUM>. The master <NUM> may be, for example, an application processor that performs various functions (e.g., telephony, wireless data access, audio/video function, etc.) and communicates with the plurality of slaves <NUM>-<NUM> to <NUM>-N via the I3C link <NUM>. The I3C link <NUM> includes a Serial Clock (SCL) line <NUM> and a Serial Data (SDA) line <NUM>.

The master <NUM> includes at least one processing unit (one or more) <NUM>-<NUM> to <NUM>-M, a host controller <NUM>, and a bus system <NUM>. The bus system <NUM> may be one or more buses and may directly or indirectly connect the at least one processing unit <NUM>-<NUM> to <NUM>-M to the host controller <NUM>. In one example, the host controller <NUM> may be configured to communicate with the first slave <NUM>-<NUM> and with the second slave <NUM>-<NUM> via a serial communication bus (e.g., the I3C link <NUM>) in accordance with a serial communication protocol.

The host controller <NUM> includes an always-on module <NUM>, a master-slave module <NUM>, and a bus system <NUM> coupling the always-on module <NUM> and the master-slave module <NUM>. The master-slave module <NUM> is configured to operate communications (of the master <NUM>) with the first slave <NUM>-<NUM> and (of the master <NUM>) with the second slave <NUM>-<NUM> via a serial communication bus (e.g., the I3C link <NUM>) in accordance with the serial communication protocol (e.g., an I3C specification), using at least one master-slave address. For example, the master-slave module <NUM> may be configured service a slave-to-master in-band interrupt (IBI) request. The master-slave module <NUM> may recognize the IBI request and wake up the at least one processing unit <NUM>-<NUM> to <NUM>-M accordingly. The master-slave module <NUM> may further the configured to control reading and writing (e.g., data exchanges) between the master <NUM> and the first slave <NUM>-<NUM> and between the master <NUM> and the second slave <NUM>-<NUM>, using the at least one master-slave address.

The at least one master-slave address is part of a serial communication protocol. For example, the at least one master-slave address may be part of an I3C specification for communications between a master and a slave. Such communication may include an exchange of data and/or an interrupt request/handling between the master (e.g., the master <NUM> of <FIG>) and the slave (e.g., one of the plurality of slaves <NUM>-<NUM> to <NUM>-N of <FIG>). For example, the I3C specification provides that such master-slave address may be a Static Address for legacy I2C device or a dynamically assigned Dynamic Address, for the master or the slave.

Moreover, the master-slave module <NUM> may be further configured to be in a low-power mode (e.g., sleep or power-down mode) while the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> are in a direct communication. For example, the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> may be in direct communication by outputting and receiving data on a serial communication bus (e.g., the I3C link <NUM>), without having to receive the data from the master <NUM>.

The an always-on module <NUM> may be configured to stay powered-on while the master-slave module <NUM> is in the low-power mode. In some examples, the always-on module <NUM> may be designed for the dedicated functions presented herein and therefore, may be small in size and efficient in power consumption. The term "always-on" may refer to that the module remains powered-on (e.g., having power supplied thereto and receiving power) while the master-slave module <NUM> is in the low-power mode. The always-on module <NUM> may be configured to detect the direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> and/or to facilitate the direct communication, while the master-slave module <NUM> is in the low-power mode. In such fashion, the master-slave module <NUM> needs not exit the low-power mode for the direct communication, and power consumption may be reduced. In some examples, the functions of the always-on module <NUM> and the master-slave module <NUM> may not be exclusive. For example, some functions of the always-on module <NUM> may be duplicated in the master-slave module <NUM> (but powered down in the low-power mode). Further details on the always-on module <NUM> is presented with <FIG>.

The at least one processing unit <NUM>-<NUM> to <NUM>-M may be, for example, central processing units (CPUs). In some examples, the at least one processing unit <NUM>-<NUM> to <NUM>-M may be functional unit or units for performing various functions (e.g., telephony, wireless data access, audio/video function, etc.). For example, in a mobile device, the at least one processing unit <NUM>-<NUM> to <NUM>-M may include a modem, an image signal processor, and/or multimedia modules. The plurality of slaves <NUM>-<NUM> to <NUM>-N may be, for example, various sensors. For example, the plurality of slaves <NUM>-<NUM> to <NUM>-N may include a fingerprint sensor, a capacitive touch sensor, gyroscope, accelerometer, magnetometer and/or a camera, etc..

A further example of the host controller <NUM> communicating with the first slave <NUM>-<NUM> in accordance with a serial communication protocol (e.g., an I3C specification) is presented infra. In one example, the master-slave module <NUM> may be in the low-power mode and may be powered down. The always-on module <NUM> may remain powered-on. The first slave <NUM>-<NUM> may issue an IBI request on a serial communication link (e.g., the I3C link <NUM>) by pulling the SDA line <NUM> line Low or logic <NUM>. The host controller <NUM> may, via the always-on module <NUM>, detect the IBI request on the SDA line <NUM> and respond to the IBI request. For example, the host controller <NUM> may respond to the detected IBI request by clocking the SCL line <NUM> to receive information of the IBI request from the requesting first slave <NUM>-<NUM>. The information of the IBI request may indicate to which of the at least one processing unit <NUM>-<NUM> to <NUM>-M the IBI request is directed.

The host controller <NUM> (e.g., the always-on module <NUM>) may service the IBI request by waking up the master-slave module <NUM>, via the bus system <NUM>. The master-slave module <NUM> may determine from the information of the IBI request to which of the at least one processing unit <NUM>-<NUM> to <NUM>-M the IBI request is directed and wake up the at least one processing unit <NUM>-<NUM> to <NUM>-M, via the bus system <NUM>. However, in a case of a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, the host controller <NUM> (e.g., the always-on module <NUM>) may not need service the IBI request (e.g., need to wake up the master-slave module <NUM>). In such fashion, the master-slave module <NUM> may remain in the low-power mode, and power consumption is reduced.

<FIG> illustrates an always-on module <NUM> of the host controller of <FIG>, in accordance with certain aspects of the disclosure. <FIG> includes the always-on module <NUM> coupled to a bus system <NUM> and the I3C link <NUM> of <FIG> (e.g., an instance of a serial communication bus). The bus system <NUM> may be an instance of the bus system <NUM> of <FIG>.

In some examples, all operations of the always-on module <NUM> presented herein may be performed while the master-slave module <NUM> is in a low-power mode. The always-on module <NUM> may include some or all of an SDA generator <NUM>, an SDA generator <NUM>, an always-on control <NUM>, a bus system <NUM>, and/or an SDA analyzer <NUM>. The bus system <NUM> couples an always-on control <NUM>, the SDA generator <NUM>, the always-on control <NUM>, and the SDA analyzer <NUM>. The SCL generator <NUM> may be configured to operate (e.g., to drive or to leave open) the SCL line <NUM>. The SDA generator <NUM> may be configured to operate (e.g., to drive or to leave open) the SDA line <NUM>. The SDA analyzer <NUM> may be configured to determine states on the SDA line <NUM> and/or to detect an IBI request on the serial communication bus (e.g., the I3C link <NUM>). The always-on control <NUM> may be configured to control operations of the SDA analyzer <NUM>, the SCL generator <NUM>, and/or the SDA generator <NUM> to, for example, detect and respond to the IBI request detected on the serial communication bus (e.g., the I3C link <NUM>), in accordance with a serial communication protocol (e.g., an I3C specification).

The always-on control <NUM> may be further configured to service the IBI request detected (e.g., to complete the IBI request; e.g., waking up the master-slave module <NUM> of <FIG>, via the bus system <NUM> and the bus system <NUM>). Further, the always-on control <NUM> may be configured to control operations of the SDA analyzer <NUM>, the SCL generator <NUM>, and/or the SDA generator <NUM> to, for example, detect a direct communication request and to facilitate a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> (<FIG>).

The always-on control <NUM> may further include a memory-m <NUM>. The memory-m <NUM> may be a volatile memory or a non-volatile memory, among others. The memory-m <NUM> may be configured to store, as a Table <NUM>, at least one master-slave address <NUM>-<NUM>, at least one direct communication address <NUM>-<NUM>, and/or information associated with the at least one direct communication address <NUM>-<NUM>. The at least one master-slave address <NUM>-<NUM> may be part of a serial communication protocol. For example, the at least one master-slave address <NUM>-<NUM> may be part of an I3C specification for communication between a master and a slave. Such communications may include data changes and/or an interrupt request/handling between the master (e.g., the master <NUM> of <FIG>) and the slave (e.g., one of the plurality of slaves <NUM>-<NUM> to <NUM>-N of <FIG>). For example, the I3C specification provides that such master-slave address may be a Static Address for legacy I2C device or a dynamically assigned Dynamic Address, for the master or the slave.

The at least one direct communication address <NUM>-<NUM> may indicate an address of a target slave of the direct communication. In some examples, the at least one master-slave address <NUM>-<NUM> is different from the at least one direct communication address <NUM>-<NUM>. For example, the at least one master-slave address <NUM>-<NUM> and the at least one direct communication address <NUM>-<NUM> are mutually exclusive. In some examples, the at least one direct communication address <NUM>-<NUM> might not be part of a serial communication protocol such as the I3C specification. In such fashion, a detection of the at least one direct communication address <NUM>-<NUM> would indicate a direct communication request.

The information associated with the at least one direct communication address <NUM>-<NUM> may include information for the always-on control <NUM> to facilitate the direct communication between slaves (e.g., the plurality of slaves <NUM>-<NUM> to <NUM>-N of <FIG>). For example, the information associated with the at least one direct communication address <NUM>-<NUM> may include a predetermined data length (and therefore, of a predetermined number of clocks) associated with each of the at least one direct communication address <NUM>-<NUM>. In some example, being predetermined refers to that the number was determined before the direct communication request was initiated. The at least one direct communication address <NUM>-<NUM> and the information associated with the at least one direct communication address <NUM>-<NUM> may be entered by software or by private agreements between the master <NUM> and the plurality of slaves <NUM>-<NUM> to <NUM>-N prior to the request for the direct communication.

<FIG> illustrates operations of the host controller (the always-on module <NUM>) of <FIG> and <FIG>, in accordance with certain aspects of the disclosure. Referring to <FIG>, the apparatus <NUM> is configured for a direct communication among the plurality of slaves <NUM>-<NUM> to <NUM>-N, via a serial communication bus. The direct communication may include data exchanges among the plurality of slaves <NUM>-<NUM> to <NUM>-N, without the master <NUM> receiving and/or outputting the data. For example, a first slave <NUM>-<NUM> may request a direct communication with a second slave <NUM>-<NUM>, and output data onto the serial communication bus (e.g., the I3C link <NUM>). The destination second slave <NUM>-<NUM> may receive the data outputted by the first slave <NUM>-<NUM> from the serial communication bus directly, the data not being received or outputted by the master <NUM>.

At <NUM>, the master-slave module <NUM> of <FIG> enters into a low-power mode (e.g., sleep mode; power down) to save power. The always-on module <NUM> of <FIG> remains powered on and in operation. The subsequent operations <NUM>, <NUM>, <NUM>, and <NUM> may all be performed while the master-slave module <NUM> is at the low-power mode. At <NUM>, the host controller, via the always-on module <NUM> (see <FIG>), detects an interrupt request in accordance with a serial communication protocol (while the master-slave module <NUM> of <FIG> is in the low-power mode). The interrupt request may be, for example, an in-band interrupt (IBI) request in accordance with the serial communication protocol. The serial communication protocol may be an I3C specification or other specifications incorporating the I3C specification. The host controller (e.g., the always-on module <NUM>) may be configured to detect the interrupt request in accordance with a serial communication protocol and the request for the direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, on the serial communication bus (e.g., the I3C link <NUM> having the SCL line <NUM> and the SDA line <NUM>; see <FIG>)(while the master-slave module <NUM> of <FIG> is in the low-power mode). Referring to <FIG>, for example, the SDA analyzer <NUM> may detect the IBI request on the SDA line <NUM> by detecting the SDA line <NUM> transitioning from a High (e.g., logic <NUM>) to a Low (e.g., a logic <NUM>), in accordance with an I3C specification. The SDA analyzer <NUM> may issue an IBI request detect onto the bus system <NUM> to notify the always-on control <NUM>.

At <NUM>, the host controller, via the always-on module <NUM>, reads in the request for the direct communication (while the master-slave module <NUM> of <FIG> is in the low-power mode). For example, in response to the IBI request detect (provided on the bus system <NUM>), the always-on control <NUM> may direct, via the bus system <NUM>, the SCL generator <NUM> to clock the SCL line <NUM> nine times to read in the information following the IBI request accordance with the I3C specification for handling the IBI request. For example, in the case of an IBI request in according to the I3C specification, the nine clock pulses may include <NUM> clocks to read in a Device Address (<NUM> bits), one clock to read in an RnW bit, and one clock for the ACK (acknowledge) bit. The always-on control <NUM> may be configured to direct, via the bus system <NUM>, the SDA generator <NUM> to provide the ACK bit onto the serial communication bus. According to the I3C specification, the <NUM>-bit Device Address is an address of a slave (e.g., one of the plurality of slaves <NUM>-<NUM> to <NUM>-N) requesting the IBI. The <NUM>-bit Device Address is an example of a master-slave address, as the Device Address would be used for master-slave communication (e.g., the IBI request, read/write between the master <NUM> and the plurality of slaves <NUM>-<NUM> to <NUM>-N). According to the I3C specification, the Device Address may be a Static Address for legacy I2C device or may be a dynamically assigned Dynamic Address for I3C.

In a case of a direct communication request, the information read in by the host controller, via the always-on module <NUM>, may be a request for the direct communication. For example, in response to detecting the interrupt request (e.g., the IBI request), the host controller (e.g., the always-on module <NUM>) may be configured to read in the request for the direct communication in response to detecting the interrupt request, in accordance of with the serial communication protocol for the interrupt request. The request for the direct communication may be an address or a code indicating a direct communication request.

In the example, the serial communication bus includes an I3C link <NUM> (which includes the SCL line <NUM> and the SDA line <NUM>; see <FIG>). The serial communication protocol includes an I3C protocol. The interrupt request includes an in-band interrupt (IBI) request. In some examples, the always-on module <NUM> may be configured to read in a Mandatory Data Byte (MDB) in accordance with an I3C specification for the IBI request. The MDB may include a device-to-device Common Command Code (CCC) that indicates a request for the direct communication.

In some examples, a different direct communication scheme is provided. The host controller (e.g., the always-on module <NUM>) is configured to clock the I3C link <NUM> nine times to read in the request for the direct communication in response to detecting the interrupt request and immediately following the interrupt request (while the master-slave module <NUM> of <FIG> is in the low-power mode). The request for the direct communication includes the at least one direct communication address <NUM>-<NUM> (e.g., the address of the destination second slave), which is <NUM> bits.

In a case of the first slave <NUM>-<NUM> requesting the direct communication with the second slave <NUM>-N, the request for the direct communication (e.g., the <NUM>-bit read in following the IBI request read in by the always-on module <NUM>) might not be part of the serial communication protocol. For example, the first slave <NUM>-<NUM> may provide on the serial communication bus a direct communication address of the destination second slave <NUM>-<NUM> as the request for the direct communication (instead IBI request information as provided by the I3C specification), following the IBI request. The direct communication address might not be part of the I3C specification. For example, the direct communication address is not part of the master-slave address (e.g., the Static Address or the Dynamic Address) specified by the I3C specification. In other words, the direct communication address is not part of the serial communication protocol.

From the perspective of the first slave <NUM>-<NUM>, to request the direct communication with another slave, the requesting first slave <NUM>-<NUM> may be configured to provide, to the master <NUM>, an interrupt request (e.g., an IBI request) in accordance with the serial communication protocol (e.g., an I3C specification) and a request for a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, on the serial communication bus. The host controller <NUM> (e.g., the always-on module <NUM>) is configured to detect the interrupt request in accordance with the serial communication protocol and the request for a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, on the serial communication bus (while the master-slave module <NUM> of <FIG> is in the low-power mode).

The request for the direct communication does not include the at least one master-slave address. The request for the direct communication may include an address of the second slave <NUM>-<NUM> and not an address of the first slave <NUM>-<NUM>, in a case the first slave <NUM>-<NUM> is requesting the direct communication to the second slave <NUM>-<NUM>. In some examples, the request for the direct communication is not part of the serial communication protocol (e.g., not part of an I3C specification). For example, the address of the second slave <NUM>-<NUM> provided by the requesting first slave <NUM>-<NUM> might not be specified by the serial communication protocol.

At <NUM>, the host controller, via the always-on module <NUM>, detects the request for the direct communication (while the master-slave module <NUM> of <FIG> is in the low-power mode). To determine whether the interrupt request is for a direct communication among the plurality of slaves <NUM>-<NUM> to <NUM>-N (see <FIG>), in some examples, the host controller (e.g., the always-on module <NUM> of <FIG>) may be configured to detect the device-to-device CCC in the MDB of the IBI request, the device-to-device CCC indicating a direct communication request.

In some examples, the host controller (e.g., the always-on module <NUM>) may be configured to store at least one direct communication address <NUM>-<NUM> and to determine whether the request for the direct communication indicates (e.g., includes or expresses in certain ways) the at least one direct communication address <NUM>-<NUM>. For example, the memory-m <NUM> may be configured to store Table <NUM>, including at least one master-slave address <NUM>-<NUM>, at least one direct communication address <NUM>-<NUM>, and information associated with the at least one direct communication address <NUM>-<NUM>. The Table <NUM> may store, for each of the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, a corresponding at least one master-slave address <NUM>-<NUM>, an at least one direct communication address <NUM>-<NUM>, and a number of clocks associated with the direct communication address (i.e., the information associated with the at least one direct communication address <NUM>-<NUM>).

As illustrated in <FIG>, the master-slave address for the first slave <NUM>-<NUM> is one; the master-slave address for the second slave <NUM>-<NUM> is two; the direct communication address for the first slave <NUM>-<NUM> is three; and the direct communication address for the second slave <NUM>-<NUM> is four. In some examples, the first slave <NUM>-<NUM> provides onto the serial communication bus the identification including an address of the second slave <NUM>-<NUM> and not an address of the first slave <NUM>-<NUM>, in a case the first slave <NUM>-<NUM> is requesting the direct communication to the second slave <NUM>-<NUM>. For example, the request for the direct communication may include the address of the destination second slave <NUM>-<NUM> (address is four in the example) only and excludes the address of the requesting first slave <NUM>-<NUM> (address is three in the example). The at least one direct communication address <NUM>-<NUM> includes the (direct communication) address of the second slave <NUM>-<NUM> (four in the example).

In some examples, the host controller (e.g., the always-on control <NUM>) may be configured to match the request for the direct communication (e.g., the address four of the destination second slave <NUM>-<NUM>) with the Table <NUM> to determine whether the request (for the direct communication) indicates the at least one direct communication address <NUM>-<NUM>. Since the address of the destination second slave <NUM>-<NUM> (address is four in the example) matches the at least one direct communication address <NUM>-<NUM>, the always-on control <NUM> may recognize that the request having the address of four is a request for direct communication and the destination of the direct communication is the second slave <NUM>-<NUM>. By using the address of the destination slave for direct communication request (and/or that the address is not part of the direct communication protocol), no additional transaction to provide the destination address are needed, and the cost in terms of power and time to request the direct communication among the plurality of slaves <NUM>-<NUM> to <NUM>-N is reduced.

In some examples, the host controller (e.g., the always-on control <NUM>) may be configured to determine whether the request for the direct communication is part of the serial communication protocol, based on the information stored in the memory-m <NUM>. For example, the always-on control <NUM> may match the request (e.g., the address four of the destination second slave <NUM>-<NUM>) with the at least one master-slave address <NUM>-<NUM> or the at least one direct communication address <NUM>-<NUM>. For example, the request for the direct communication (e.g., the address four of the destination second slave <NUM>-<NUM>) might not indicate the at least one master-slave address <NUM>-<NUM> (the at least one master-slave address <NUM>-<NUM> being part of the I3C specification). Such case may indicate to the always-on control <NUM> that request is a direct communication request. In a case that the request (e.g., the address four of the destination second slave <NUM>-<NUM>) matches the at least one direct communication address <NUM>-<NUM>, the always-on control <NUM> may likewise recognize the identification is a direct communication request.

At <NUM>, the host controller services the interrupt request in accordance with the serial interface protocol. At <NUM>, the host controller wakes up the master-slave module <NUM> (see <FIG>) to service the interrupt request. In a case that the interrupt request is part of the serial communication protocol (e.g., the request for the direct communication matches the at least one master-slave address <NUM>-<NUM> or does not match the at least one direct communication address <NUM>-<NUM>), the host controller may service the interrupt request (e.g., an IBI request in accordance with the I3C specification). Referring to <FIG>, the always-on module <NUM> may be configured to wake up the master-slave module <NUM> from the low-power mode via the bus system <NUM>. The always-on module <NUM> may be further configured to provide the read-in information (e.g., IBI information in this case) to the master-slave module <NUM> via the bus system <NUM>.

The master-slave module <NUM> may be configured to service the IBI request in accordance with IBI-handling procedures of the I3C specification. For example, the master-slave module <NUM> may be configured to wake up one of the at least one processing unit <NUM>-<NUM> to <NUM>-M based on the IBI information, the one of the at least one processing unit <NUM>-<NUM> to <NUM>-M being a target of the IBI request.

At <NUM>, the host controller, via the always-on module <NUM>, clocks the communication bus a number of times for the direct communication (while the master-slave module <NUM> of <FIG> is in the low-power mode). The host controller (e.g., the always-on control <NUM> of the always-on module <NUM>) may be further configured to bypass servicing the interrupt request in accordance with the serial communication protocol, in response to the request for the direct communication indicating the at least one direct communication address <NUM>-<NUM>. For example, host controller, via the always-on control <NUM>, may be configured to bypass servicing the IBI request in accordance of an I3C specification, in response to the request direct communication indicating the at least one direct communication address <NUM>-<NUM> (e.g., matching the at least one direct communication address <NUM>-<NUM>). In some examples, the host controller (e.g., the always-on control <NUM>) may be configured to bypass service the interrupt request (the interrupt request being in accordance with the serial communication protocol) in response to the identification being not part of the serial communication protocol (e.g., the identification does not match the at least one master-slave address <NUM>-<NUM>).

Further, the host controller (e.g., always-on control <NUM> of the always-on module <NUM>) may be configured to store information associated with the at least one direct communication address <NUM>-<NUM> and to clock the serial communication bus a number of times based on the information associated with the at least one direct communication address <NUM>-<NUM> for the direct communication (while the master-slave module <NUM> of <FIG> is in the low-power mode). Referring to <FIG>, the memory-m <NUM> is configured to store the information associated with the at least one direct communication address <NUM>-<NUM> in the form of the number of clocks. For example, each of the number of clocks is associated with a corresponding at least one direct communication address <NUM>-<NUM>. In such fashion, a data length of a direct communication to each of the slaves is stored in the form of number of clocks. In a case of a direct communication to the second slave <NUM>-<NUM>, the number of clocks is twelve in <FIG>. Thus, in this example, the always-on control <NUM> may be configured to instruct the SCL generator <NUM> to clock the SCL line <NUM> twelve times for the first slave <NUM>-<NUM> to provide data directly to the second slave <NUM>-<NUM> on the SDA line <NUM> (while the master-slave module <NUM> of <FIG> is in the low-power mode). In such fashion, the number of times to clock the serial communication bus for the direct communication may be predetermined (e.g., determined before the request for the direct communication).

<FIG> illustrates a first slave <NUM>-<NUM> and a second slave <NUM>-<NUM> of the apparatus of <FIG> configured for direct communication, in accordance with certain aspects of the disclosure. <FIG> includes the first slave (e.g., a slave device) <NUM>-<NUM> and the second slave <NUM>-<NUM>. The first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> are coupled to a serial communication bus (e.g., the I3C link <NUM> including the SCL line <NUM> and the SDA line <NUM> of <FIG>) and coupled via the serial communication bus to a master. The first slave <NUM>-<NUM> may be an instance of the first slave <NUM>-<NUM> of <FIG>. The second slave <NUM>-<NUM> may be an instance of the second slave <NUM>-<NUM> of <FIG>.

The first slave <NUM>-<NUM> may be configured to communicate with the master (e.g., the master <NUM> of <FIG>) via the serial communication bus (e.g., the I3C link <NUM> having the SCL line <NUM> and the SDA line <NUM>) using at least one master-slave address, in accordance with a serial communication protocol (e.g., an I3C specification). The first slave <NUM>-<NUM> may be further configured to be in a direct communication with a second slave (e.g., the second slave <NUM>-<NUM>) via the serial communication bus. The first slave <NUM>-<NUM> may include some or all of a PHY <NUM>-<NUM> and a memory memory-s1 <NUM>-<NUM>. The PHY <NUM>-<NUM> may be configured to operate and/or to detect states on the serial communication bus (e.g., the I3C link <NUM> having the SCL line <NUM> and the SDA line <NUM>).

The memory-s1 <NUM>-<NUM> may be a volatile memory or non-volatile memory. The memory-s1 <NUM>-<NUM> may store information of a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>. For example, the memory-s1 <NUM>-<NUM> may store a Table <NUM>-<NUM> including at least one master-slave address <NUM>-<NUM>, at least one direct communication address <NUM>-<NUM>, and/or information associated with the at least one direct communication address <NUM>-<NUM> (e.g. a number of clocks or data length).

The at least one master-slave address <NUM>-<NUM> may be part of the serial communication protocol, such as an I3C specification. For example, an I3C specification may provide at least one Static Address for legacy I2C support and dynamic assigned at least one Dynamic Address as the at least one master-slave address <NUM>-<NUM>. The at least one master-slave address <NUM>-<NUM> may be used for communications between the master (e.g., the master <NUM> of <FIG>) and one among the plurality of slaves (e.g., the first slave <NUM>-<NUM> or the second slave <NUM>-<NUM>), in accordance with the I3C specification.

The at least one direct communication address <NUM>-<NUM> may be used to indicate a direct communication request. In some examples, the at least one direct communication address <NUM>-<NUM> might not be part of the serial communication protocol. For example, the at least one master-slave address <NUM>-<NUM> and the at least one direct communication address <NUM>-<NUM> may be different (e.g., mutually exclusive). In some examples, the at least one direct communication address may include an address of a source slave and/or an address of a destination slave for the direct communication. In some examples, the at least one direct communication address may exclude the address of a source slave.

The second slave <NUM>-<NUM> includes some or all of a PHY <NUM>-<NUM> and a memory memory-s2 <NUM>-<NUM>. The PHY <NUM>-<NUM> may be configured to operate and/or to detect states on the serial communication bus (e.g., the I3C link <NUM> having the SCL line <NUM> and the SDA line <NUM>). The memory-s2 <NUM>-<NUM> may be a volatile memory or non-volatile memory. The memory-s2 <NUM>-<NUM> may store information of a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>. For example, in similar fashion as the Table <NUM>-<NUM>, the memory-s2 <NUM>-<NUM> may store a Table <NUM>-<NUM> including at least one master-slave address <NUM>-<NUM>, at least one direct communication address <NUM>-<NUM>, and/or information associated with the at least one direct communication address <NUM>-<NUM> (e.g. a number of clocks or data length).

The first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> may be further configured for a direct communication therebetween. The direct communication may include, for example, the first slave <NUM>-<NUM> transmit data directly to the second slave <NUM>-<NUM> via the serial communication bus. The master <NUM> (see <FIG>) might not receive the data from the first slave <NUM>-<NUM> and then provide the data to the second slave <NUM>-<NUM>.

To facilitate the direct communication, the first slave <NUM>-<NUM> may be configured to provide, to the master <NUM>, an interrupt request (e.g., an in-band interrupt or IBI request) in accordance with the serial communication protocol (e.g., an I3C specification). The interrupt request may trigger at the master <NUM> an inquiry for the direct communication. The first slave <NUM>-<NUM> may be further configured to provide, to the master <NUM>, a request for a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, on the serial communication bus (e.g., the I3C link <NUM>). The request for the direct communication may be different from the at least one master-slave address of the serial communication protocol (e.g., an I3C specification).

For example, the request for the direct communication may indicate (e.g., include or express in certain ways) the at least one direct communication address <NUM>-<NUM>. The at least one direct communication address <NUM>-<NUM> may be different (e.g., mutually exclusive) with all of the master-slave addresses of the serial communication protocol (e.g., an I3C specification). For example, the at least one master-slave address may include Dynamic Addresses provided by an I3C specification (and used for communication between a master and a slave), and the request for the direct communication does not include any of the at least one master-slave address. In such fashion, the request for the direct communication (e.g., the at least one direct communication address <NUM>-<NUM>) is not part of the serial communication protocol.

<FIG> illustrates direct communication waveforms on a serial communication bus, in accordance with certain aspects of the disclosure. Initially (before T0), the I3C link <NUM> is in a Bus Available State (e.g., both the SCL line <NUM> and the SDA line <NUM> are High). For example, the at least one processing unit <NUM>-<NUM> to <NUM>-M and/or the master-slave module <NUM> (see <FIG>) may be in the low-power mode. The master <NUM> may stay in the low-power mode in such fashion through the direct communication cycles without having to wake up. For example, the master <NUM> (see <FIG>) may be in the low-power mode from before T0 to after T5.

At T0, the first slave <NUM>-<NUM> (see <FIG>) signals an interrupt request (e.g., an IBI request) to the master <NUM> on the I3C link <NUM>. The first slave <NUM>-<NUM> may be configured to provide the interrupt request on the serial communication bus by directing the PHY <NUM>-<NUM> (see <FIG>) to pull the SDA line <NUM> Low. The master <NUM>, via the host controller (e.g., the SDA analyzer <NUM> of the always-on module <NUM>; see <FIG>) may detect that the SDA line <NUM> is pulled Low and recognize the interrupt request. The SDA analyzer <NUM> may issue an IBI detect signal to the always-on control <NUM>, via the bus system <NUM> (see <FIG>).

At T1, the master <NUM> (via the always-on module <NUM> of the host controller) reads in a request for a direct communication <NUM> in response to detecting the interrupt request, in accordance with the serial communication protocol for the interrupt request. For example, in response to receiving the IBI detect signal from the SDA analyzer <NUM>, the always-on control <NUM> may be configured to direct the SCL generator <NUM> to pull the SCL line <NUM> Low to complete a START Condition.

The always-on module <NUM> of the host controller may be configured to read in information immediately following (e.g., no intervening data exchanges on the SDA line <NUM>) the interrupt request. In a case of a slave requesting an IBI request, the information read in would include a master-slave address (e.g., a Dynamic Address) of the requesting slave, in accordance with the I3C specification for the IBI request. In a case of a slave requesting a direct communication, the information read in immediately following detecting the IBI request would be the request for the direct communication <NUM>.

The always-on control <NUM> may be configured to direct the SCL generator <NUM> to clock the SCL line <NUM> nine times to read in the IBI request information or the request for the direct communication <NUM>, in response to detecting the interrupt request (immediately following the interrupt request). The nine clocks account for <NUM> bits of the request for the direct communication <NUM> (e.g., the at least one direct communication address <NUM>-<NUM> of <FIG>), one bit for RnW (read or write), and one bit for ACK to signal acceptance of the direct communication request by the host controller.

The <NUM>-bit request for the direct communication <NUM> may indicate (e.g., include or express in certain ways) at least one direct communication address <NUM>-<NUM>. The first slave <NUM>-<NUM> may be configured to read from the memory-s1 <NUM>-<NUM> information of the direct communication (e.g., the Table <NUM>-<NUM>). For example, the memory-s1 <NUM>-<NUM> may be configured to store at least one direct-communication address <NUM>-<NUM>. The at least one direct communication address <NUM>-<NUM> may be used to indicate to the master <NUM> a direct communication request. In some examples, the at least one direct communication address <NUM>-<NUM> might not be part of the serial communication protocol (e.g., not part of an I3C specification).

For example, the first slave <NUM>-<NUM> requesting the direct communication to the second slave <NUM>-<NUM> may be configured to provide the request for the direct communication <NUM> immediately following (e.g., no intervening data exchanges on the SDA line <NUM>) the interrupt request at T0. The requesting first slave <NUM>-<NUM> may be configured to, based on the memory-s1 <NUM>-<NUM>, provide the at least one direct communication address <NUM>-<NUM> of the destination second slave <NUM>-<NUM> (in the example of <FIG>, the address is four). The first slave <NUM>-<NUM> may be configured to provide, via the PHY <NUM>-<NUM>, the address four onto the I3C link <NUM> as the request for the direct communication <NUM>.

Accordingly, the request for the direct communication <NUM> may include an address of the destination second slave <NUM>-<NUM> and not an address of the requesting first slave <NUM>, the first slave <NUM>-<NUM> being requesting the direct communication to the second slave <NUM>-<NUM>. For example, the master <NUM> does not need additional steps to acquire the address of the destination slave. In such fashion, information needed for the direct communication is reduced, and performance and power consumption are improved.

Referring to <FIG>, the second slave <NUM>-<NUM> may include some or all of the PHY <NUM>-<NUM> and the memory-s2 <NUM>-<NUM>, similar to the first slave <NUM>-<NUM>. The PHY <NUM>-<NUM> may be configured to operate and to detect states on the serial communication bus (e.g., the I3C link <NUM>). The memory-s2 <NUM>-<NUM> may be configured to store, as a Table <NUM>-<NUM>, at least one master-slave address <NUM>-<NUM> for communication under a serial communication protocol (e.g., an I3C specification). The memory-s2 <NUM>-<NUM> may be further configured to store, as the Table <NUM>-<NUM>, direct communication information including at least one direct communication address <NUM>-<NUM> and/or information associated with the at least one direct communication address <NUM>-<NUM>.

The second slave <NUM>-<NUM> may be configured to detect on the serial communication bus the request for the direct communication <NUM>. For example, the PHY <NUM>-<NUM> of the second slave <NUM>-<NUM> may be configured to detect states on the I3C link <NUM> and read in the request for the direct communication <NUM> (e.g., the at least one direct communication address <NUM>-<NUM> provided by the first slave <NUM>-<NUM>). In the example, the provided at least one direct communication address <NUM>-<NUM> is four.

The second slave <NUM>-<NUM> may be further configured to determine, based on direct communication information stored in the memory-s2 <NUM>-<NUM> and the received request for the direct communication <NUM>, that the second slave <NUM>-<NUM> is the destination device of the direct communication request. For example, the second slave <NUM>-<NUM> may be configured to match the request for the direct communication <NUM> (e.g., the at least one direct communication address <NUM>-<NUM>) with the at least one master-slave address <NUM>-<NUM> stored in the memory-s2 <NUM>-<NUM>. In the example, the at least one direct communication address <NUM>-<NUM> is four and matches the at least one direct communication address <NUM>-<NUM>, indicating that the second slave <NUM>-<NUM> is the destination device.

At T3, the master <NUM> (via a host controller) clocks the serial communication bus a number of times based on information associated with the at least one direct communication address for the direct communication. The master <NUM> contributes to the direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> by clocking the SCL line <NUM> of the I3C link <NUM>. The host controller may be configured, via the SDA analyzer <NUM>, to read in the request for the direct communication <NUM>. The always-on control <NUM> may read in the request for the direct communication <NUM> via the bus system <NUM> and determine whether the request for the direct communication <NUM> indicates the at least one direct communication address.

For example, based on the memory-m <NUM>, the always-on control <NUM> may be configured to determine that the request for the direct communication <NUM> (e.g., the received at least one direct communication address <NUM>-<NUM> of four) is different (e.g., mutually exclusive) from the at least one master-slave address <NUM>-<NUM>. The always-on control <NUM> may thus be configured to determine that the request for the direct communication <NUM> is not part of the serial communication protocol (e.g., an I3C specification) of which the at least one master-slave address <NUM>-<NUM> is a part.

In some examples, the always-on control <NUM> may be configured to determine that the request for the direct communication <NUM> indicates (e.g., includes or expresses in certain ways) the at least one direct communication address <NUM>-<NUM>, based on the memory-m <NUM>. In the example, the always-on control <NUM> may be configured to find that the received at least one direct communication address <NUM>-<NUM> (e.g., four) matches the at least one direct communication address <NUM>-<NUM> stored in the memory-m <NUM>. In such fashion, the host controller (via the always-on control <NUM>) may be configured to determine that the interrupt request detected at T0 is indeed a direct communication request, and not an IBI request in accordance with the I3C specification. The host controller (via the always-on control <NUM>) may be configured to bypass servicing the IBI request in accordance with the I3C specification, in response to the request for the direct communication <NUM> indicating (e.g., including or expressing in certain ways) the at least one direct communication address <NUM>-<NUM> stored in the memory-m <NUM>.

The host controller, via the always-on module <NUM>, may be configured to clock the serial communication bus (e.g., the I3C link <NUM>) a number of times based on the information associated with the at least one direct communication address <NUM>-<NUM>, stored in the memory-m <NUM>. In the example, the received at least one direct communication address <NUM>-<NUM> is four, indicating that target of the direct communication is the second slave <NUM>-<NUM>. The always-on control <NUM> may be configured to determine that the corresponding information associated with the at least one direct communication address <NUM>-<NUM> is twelve clocks. The information associated with the at least one direct communication address <NUM>-<NUM> may express information in terms of the number of clocks or a data length of the direct communication, for example.

The always-on control <NUM> may be configured to instruct the SCL generator <NUM> to clock the I3C link <NUM> twelve times, based on the information associated with the at least one direct communication address <NUM>-<NUM> for the direct communication. In such fashion, the host controller (e.g. the always-on module <NUM>) may be configured to provide a predetermined number of clocks onto the serial communication bus for the direct communication. The predetermined number of clocks may be, for example, provided onto the memory-m <NUM> via private agreements between the master <NUM> and the plurality of slaves <NUM>-<NUM> to <NUM>-N (see <FIG>) or via software before the request for the direct communication <NUM>.

The first slave <NUM>-<NUM> and the second slave <NUM>-<NUM> may utilize the clocking provided by the master <NUM> for the direct communication. The first slave <NUM>-<NUM> may be configured to provide a number of data on the serial communication bus based on the information associated with the at least one direct communication address <NUM>-<NUM> stored within the first slave <NUM>-<NUM>. In the Table <NUM>-<NUM>, the information associated with the at least one direct communication address <NUM>-<NUM> corresponding to the destination second slave <NUM>-<NUM> is twelve. The information associated with the at least one direct communication address <NUM>-<NUM> may express the information in terms of a number of clocks or data length, etc. The first slave <NUM>-<NUM> may be configured to provide <NUM> bits of direct communication data <NUM>, via the PHY <NUM>-<NUM>, onto the I3C link.

The second slave <NUM>-<NUM> may be configured to receive the direct communication data <NUM> from the serial communication bus directly from the first slave <NUM>-<NUM>. The direct communication data <NUM> are not received or provided by the master <NUM>. The second slave <NUM> may be configured to determine that itself is indeed the destination of the request for the direct communication <NUM>, based on based on the Table <NUM>-<NUM> stored in the memory-s2 <NUM>-<NUM>. For example, the second slave <NUM> may be configured to determine the request for the direct communication <NUM> indicates (e.g., includes or expresses in certain ways) at least one direct communication address <NUM>-<NUM> stored in the in the memory-s2 <NUM>-<NUM>. In the example, the received request for the direct communication <NUM> includes the at least one direct communication address <NUM>-<NUM>, which is four. The second slave <NUM>-<NUM> may be configured to recognize that itself is the destination of the request for the direct communication <NUM>, because the at least one direct communication address <NUM>-<NUM> of four is associated with the second slave <NUM>-<NUM> in the Table <NUM>-<NUM>.

The second slave <NUM> may be further configured to determine a number of clocks or a data length associated with the at least one direct communication address <NUM>-<NUM> received on the serial communication bus (e.g., the I3C link <NUM>). For example, the second slave <NUM> may be configured to, based on the Table <NUM>-<NUM> stored in the memory-s2 <NUM>-<NUM>, determine the information associated with the at least one direct communication address <NUM>-<NUM>. In the example, the received request for the direct communication <NUM> includes the at least one direct communication address <NUM>-<NUM>, which is four. The corresponding information associated with the at least one direct communication address <NUM>-<NUM> is twelve. Accordingly, the second slave <NUM> may be further configured to receive the direct communication data <NUM> (<NUM> bits) based on the corresponding information associated with the at least one direct communication address <NUM>-<NUM>.

As presented above, the master <NUM>, the first slave <NUM>-<NUM>, and the second slave <NUM>-<NUM> may be configured to engage in a direct communication (between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>). Each of the master <NUM>, the first slave <NUM>-<NUM>, and the second slave <NUM>-<NUM> may be configured to store at least one master-slave address (e.g., respectively <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) in accordance with the serial communication protocol (e.g., the I3C specification). Each of the master <NUM>, the first slave <NUM>-<NUM>, and the second slave <NUM>-<NUM> may be configured to store at least one direct communication address (e.g., respectively <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) to identify an interrupt request as a direct communication address. The at least one direct communication address (e.g., <NUM>-<NUM>, <NUM>-<NUM>, or <NUM>-<NUM>) may be different (e.g., exclusive) from the at least one direct communication address (e.g., <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) and may not be part of the serial communication protocol (e.g., not part of the I3C specification). Each of the master <NUM>, the first slave <NUM>-<NUM>, and the second slave <NUM>-<NUM> may be further configured to store information associated with the at least one direct communication address (e.g., respectively, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>). Based on the information associated with the at least one direct communication address <NUM>-<NUM>, the master <NUM> (via the always-on module <NUM>) may be configured to clock a serial communication bus a number of times, while a master-slave module <NUM> is in a low-power mode. Based on the information associated with the at least one direct communication address <NUM>-<NUM>, the first slave <NUM>-<NUM> may be configured to provide a predetermine number of (direct communication) data on the serial communication bus. Based on the information associated with the at least one direct communication address <NUM>-<NUM>, the second slave <NUM>-<NUM> may be configured to receive a predetermine number of data on the serial communication bus. Being predetermined may refer to setting the values prior to the request for the direct communication <NUM>.

At T4, after the direct communication data <NUM> are transferred, the SCL line <NUM> is pulled High. AT T5, the SDA line <NUM> is pulled High to complete a STOP condition. For example, referring to <FIG>, the always-on control <NUM> may direct the SCL generator <NUM> and/or the SDA generator <NUM> to pull the SCL line <NUM> and/or the SDA line <NUM> High, in a case that the direct communication is completed. Upon STOP, the I3C link <NUM> enters a Bus Free Condition (a predecessor of the Bus Available Condition), and the I3C link <NUM> is relinquished.

<FIG> illustrates a method for operating direct communication on a direct communication bus, in accordance with certain aspects of the disclosure. The operations of <FIG> may be implemented by, for example, the apparatus/host controller/slaves presented with <FIG>, <FIG>, and <FIG>. The arrows indicate certain relationships among the operations, but not necessarily sequential relationships.

At <NUM>, a host controller communicates with a first slave and with a second slave via a serial communication bus, in accordance with a serial communication protocol. In some examples, the host controller (e.g., the master-slave module <NUM>) communicates with the first slave <NUM>-<NUM> and with the second slave <NUM>-<NUM> via the I3C link <NUM> (an instance of the serial communication bus), in accordance with an I3C specification (an instance of the serial communication protocol). Such communications may include in-band (IBI) interrupts and data exchanges between the host controller (which is part of a master, such as the master <NUM> of <FIG>) and the first slave <NUM>-<NUM> or with the second slave <NUM>-<NUM>, using master-slave addresses in accordance with the I3C specification. The communication may be conducted using master-slave addresses, including Static Addresses and/or Dynamic Addresses provided by the I3C specification.

The master-slave module <NUM> operates communications (of the master <NUM>) with the first slave <NUM>-<NUM> and (of the master <NUM>) with the second slave <NUM>-<NUM> via a serial communication bus (e.g., the I3C link <NUM>) in accordance with the serial communication protocol (e.g., an I3C specification), using at least one master-slave address. For example, the master-slave module <NUM> may service a slave-to-master in-band interrupt (IBI) request using the master-slave address. The master-slave module <NUM> may recognize the IBI request and wake up the at least one processing unit <NUM>-<NUM> to <NUM>-M accordingly. The master-slave module <NUM> may further control reading and writing (e.g., data exchanges) between the master <NUM> and the first slave <NUM>-<NUM> and between the master <NUM> and the second slave <NUM>-<NUM>, using the at least one master-slave address.

At <NUM>, a low-power mode is entered by the master-slave module. For example, the master-slave module <NUM> enters into a sleep mode or is powered down to reduce power consumption. At <NUM>, a direct communication is entered by the first slave and the second slave, while the master-slave module is in the low-power. For example, referring to <FIG>, the always-on module <NUM> remains powered on while the master-slave module <NUM> is in the low-power mode. The always-on module <NUM> detects and facilitates a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>.

At <NUM>, the serial communication bus is clocked by the always-on module for the direct communication. For example, referring to <FIG> and while the master-slave module <NUM> is in the low-power mode, the host controller (e.g., the always-on control <NUM>) determines, based on the information associated with the at least one direct communication <NUM>-<NUM> and the received request for the direct communication <NUM> (see <FIG>)(e.g., the information associated with the at least one direct communication <NUM>-<NUM> is selected based on the received request for the direct communication <NUM>). The host controller (e.g., the always-on control <NUM>) operates the SCL generator <NUM> to clock the SCL line <NUM> the number of times for the direct communication between the salves. In some examples, the serial communication bus is clocked a number of times by the host controller (e.g., the always-on module <NUM>; see <FIG>), based on the information associated with the at least one direct communication address <NUM>-<NUM> (see <FIG>) for the direct communication, while the master-slave module <NUM> of <FIG> is in a low-power mode.

At <NUM>, an interrupt request in accordance with the serial communication protocol and a request for the direct communication between the first slave and the second slave are detected by the always-on module, while the master-slave module is in the low-power mode, on the serial communication bus. In some examples, while the master-slave module <NUM> is in the low-power mode, the host controller (e.g., the always-on module <NUM> of <FIG>) detects an IBI request in accordance of the I3C specification (an instance of an interrupt request in accordance with the serial communication protocol). The always-on module <NUM> of <FIG> further reads in, while the master-slave module <NUM> of FIG is in a low-power mode, an Mandator Data Byte (MDB) in response to detecting an IBI request. The always-on module <NUM> of <FIG> may recognize that the MDB includes device to device Common Command Code that indicates the direct communication request, while the master-slave module <NUM> is in the low-power mode.

In some examples, while the master-slave module <NUM> is in the low-power mode, the host controller (e.g., the always-on module <NUM> of <FIG>) detects the IBI request in accordance of the I3C specification (an instance of an interrupt request in accordance with the serial communication protocol). The host controller (e.g., the always-on module <NUM> of <FIG>) further detects a request for a direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>, on the I3C link <NUM>. For example, the always-on module <NUM> of <FIG>, using the SDA analyzer <NUM>, detects the request for the direct communication <NUM> (see <FIG>). The request for the direct communication <NUM> does not include the master-slave address.

At <NUM>, the request for the direct communication is read in by always-on module while the master-slave module is in the low-power mode, in response to detecting the interrupt request. In some examples, the host controller (e.g., the always-on module <NUM> of <FIG>) reads in, while the master-slave module <NUM> of FIG is in a low-power mode, an Mandator Data Byte in response to detecting an IBI request.

In some examples, referring to <FIG> and while the master-slave module <NUM> is in the low-power mode, the host controller (e.g., the always-on control <NUM>) reads in the request for the direct communication <NUM> on the I3C link <NUM> (the SDA line <NUM>), in response to the SDA analyzer <NUM> detecting an IBI request. Referring to <FIG>, the host controller (e.g., the always-on control <NUM>) detects the IBI request at T0 and in response, (immediately or without intervening operations) reads in the request for the direct communication <NUM> starting at T1 (while the master-slave module <NUM> is in a low-power mode).

<FIG> illustrates another method for operating direct communication on a direct communication bus, in accordance with certain aspects of the disclosure. The operations of <FIG> may be implemented by, for example, the apparatus/host controller/slaves presented with <FIG>, <FIG>, and <FIG>. The arrows indicate certain relationships among the operations, but not necessarily sequential relationships.

At <NUM>, a first slave communicates with a master via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. For example, referring to <FIG>, the first slave <NUM>-<NUM> communicates with the master <NUM> via the I3C link <NUM> (an instance of the serial communication bus) using at least one master-slave address, in accordance with an I3C specification (an instance of the serial communication protocol). Such communications may include, for example, an IBI request initiated by the first slave <NUM>-<NUM> (and serviced by the master <NUM>) and/or data changes therebetween. The at least one master-slave address may be, for example, Static Address and/or Dynamic Address specified by the I3C specification.

At <NUM>, the first slave communicates directly with a second slave via the serial communication bus. For example, referring to <FIG>, the first slave <NUM>-<NUM> communicates directly (e.g., in a direct communication) with a second slave <NUM>-<NUM>. The first slave <NUM>-<NUM> provides direct communication data onto the serial communication bus (e.g. the I3C link <NUM>) and received by the second slave <NUM>-<NUM>. The directly communication data are not received and/or not provided by the master <NUM>.

At <NUM>, an interrupt request in accordance with the serial communication protocol and a request for the direct communication between the first slave and the second slave are provided by the first slave to the master, on the serial communication bus. The request for the direct communication is different from the at least one master-slave address. Referring to <FIG>, at T0, the first slave <NUM>-<NUM> pulls the SDA line <NUM> Low to signal an IBI request (an instance of the interrupt request), in accordance with an I3C specification (an instance of the serial communication protocol). Referring to <FIG>, the first slave <NUM>-<NUM> may, via the PHY <NUM>-<NUM>, pulls the SDA line <NUM> Low.

Referring to <FIG>, after T1, the first slave <NUM>-<NUM> provides onto the SDA line <NUM> (the I3C link <NUM>) the <NUM>-bit request for the direct communication <NUM> (for direct communication between the first slave <NUM>-<NUM> and the second slave <NUM>-<NUM>). Referring to <FIG>, the first slave <NUM>-<NUM> (via the PHY <NUM>-<NUM>) provides onto the SDA line <NUM> at least one direct communication address <NUM>-<NUM> (from the memory-s1 <NUM>-<NUM>), as the request for the direct communication <NUM>. The request for the direct communication <NUM> is different from the at least one master-slave address. For example, the request for the direct communication <NUM> is not part of the I3C specification and/or is not used in master-slave communications.

At <NUM>, at least one direct communication address is stored in a memory. The request for the direct communication indicates the at least one direct communication address. For example, referring to <FIG>, the first slave <NUM>-<NUM> includes a memory-s1 <NUM>-<NUM>. The memory-s1 <NUM>-<NUM> stores the at least one direct communication address <NUM>-<NUM>. The first slave <NUM>-<NUM>, via the PHY <NUM>-<NUM>, provides onto the I3C link <NUM> the at least one direct communication address <NUM>-<NUM> as the request for the direct communication <NUM>. The request for the direct communication <NUM> thus indicates (e.g., includes or expresses in certain ways) the at least one direct communication address <NUM>-<NUM>. In some examples, the request for the direct communication <NUM> includes an address of the second slave <NUM>-<NUM> (e.g., four in the Table <NUM>-<NUM>) and not an address of the first slave <NUM>-<NUM> (e.g., not three in the Table <NUM>-<NUM>, the first slave <NUM>-<NUM> being requesting the direct communication to the second slave <NUM>-<NUM>.

At <NUM>, the request for the direct communication is provided by the first slave on the serial communication bus immediately following the interrupt request. Referring to <FIG>, the first slave <NUM>-<NUM> provides the request for the direct communication <NUM> on the I3C link <NUM> (an instance of the serial communication bus) immediately following the IBI request at T0. For example, there are no intervening data changes between the IBI request at T0 and the request for the direct communication <NUM>.

At <NUM>, the at least one direct communication address is provided by the first slave as the request for the direct communication immediately following the interrupt request. The at least one direct communication address is <NUM> bits. In some examples, the serial communication bus includes, for example, an I3C link <NUM>. The serial communication protocol includes an I3C protocol (e.g., an I3C specification). The interrupt request includes an in-band interrupt (IBI) request (see <FIG> at T0). Referring to <FIG>, the first slave <NUM>-<NUM> provides the at least one direct communication address <NUM>-<NUM> as the request for the direct communication <NUM> immediately following the interrupt request (e.g., the IBI request at T0). Referring to <FIG>, the at least one direct communication address <NUM>-<NUM> (stored in the memory-s1 <NUM>-<NUM>) is <NUM> bits.

At <NUM>, information associated with the at least one direct communication address is stored in a memory. Referring to <FIG>, the first slave <NUM>-<NUM> includes a memory-s1 <NUM>-<NUM>. The memory-s1 <NUM>-<NUM> stores the information associated with the at least one direct communication address <NUM>-<NUM>. At <NUM>, a number of data is provided by the first slave on the serial communication bus based on the information associated with the at least one direct communication address. Referring to <FIG>, at T3, the first slave <NUM>-<NUM> provides a number of data onto the I3C link <NUM> based on the information associated with the at least one direct communication address <NUM>-<NUM>. Referring to <FIG>, the first slave <NUM>-<NUM> determines, from the memory-s1 <NUM>-<NUM>, the information associated with the at least one direct communication address <NUM>-<NUM> associated with the destination second slave <NUM>-<NUM> is twelve. The first slave <NUM>-<NUM>, via the PHY <NUM>-<NUM>, provides <NUM>-bit direct communication data onto the I3C link <NUM> (see <FIG> at T3). The host controller (via the always-on module <NUM>) provides the clocking on the I3C link <NUM>.

Claim 1:
An apparatus (<NUM>), comprising:
a master (<NUM>) comprising a host controller (<NUM>),
the host controller being configured to communicate with a plurality of slaves comprising a first slave (<NUM>-<NUM>) and a second slave (<NUM>-<NUM>) via a serial communication bus using at least a first and second master-slave address, in accordance with a serial communication protocol,
wherein the host controller is configured to detect an interrupt request in accordance with the serial communication protocol and a request for a direct communication between the first slave and the second slave, on the serial communication bus, wherein the request for the direct communication does not include the at least first and second master-slave address.