Patent Description:
The field of the invention relates, generally, to nuclear magnetic resonance (NMR) equipment, and in particular to managing output impedance and/or power levels in such equipment.

Nuclear magnetic resonance (NMR) is a well-known analytic technique that has been used in a number of fields, such as spectroscopy, bio-sensing and medical imaging. In general, an NMR device includes transceiver circuits to transmit signals to a test sample and receive echo signals therefrom. For example, with reference to <FIG>, the basic components a conventional NMR system <NUM> include an NMR coil <NUM> surrounding a sample <NUM> being analyzed, a magnet <NUM> for generating a static magnetic field B<NUM> across the sample <NUM> and the coil <NUM>, a duplexer <NUM> coupled to the NMR coil <NUM>, and a controller <NUM> for controlling operation of the various components. Typically, the duplexer <NUM> includes a transmitter (Tx) portion for delivering RF signals to the NMR coil <NUM> and a receiver (Rx) portion for receiving echo signals from the sample <NUM> vis the NMR coil <NUM>.

NMR coil <NUM> and transceiver <NUM> are commonly known as an "NMR probe," which operates with large electromagnets or superconducting permanent magnets in conventional NMR systems. The NMR probe is typically included in an environment having a <NUM>Ω impedance because of a long interconnection required between the probe and NMR instrument.

The RF signals delivered by the duplexer <NUM> originate with an RF frequency source <NUM> and a pulse sequence generator <NUM>. A modulator circuit <NUM> modulates the RF signal from the RF frequency source <NUM> in accordance with the pulse sequence supplied by the pulse sequence generator <NUM>. The modulated RF signal is amplified by a power amplifier <NUM>.

During NMR measurements, the modulated RF signal having a Larmor frequency ω<NUM> is delivered to the coil <NUM> via the duplexer <NUM>; the coil <NUM> generates an RF magnetic field B<NUM> (which is typically orthogonal to the static magnetic field B<NUM>) that resonantly excites nuclei spins within the sample <NUM>. After a time duration, Δt, the RF excitation signal is stopped and the controller <NUM> causes the duplexer <NUM> to receive the echo signals from the sample <NUM>. Upon stopping the RF excitation, the nuclear spins within the sample <NUM> precess around the B<NUM>-axis at the Larmor frequency ω<NUM>. The nuclear spins slowly lose phase coherence via spin-spin interactions, which manifest themselves in a macroscopic average as an exponential relaxation or damping signal in the precession of the net magnetic moment. This NMR signal relaxation can be detected by the coil <NUM>. Because the spin-spin interactions are peculiar to the material of the sample <NUM> being tested, the characteristic time, commonly referred to as T<NUM>, of the relaxation signal is material specific.

The duplexer <NUM> directs the received echo signals, representing the signal output of the NMR probe, to an amplification block including a pre-amplifier (e.g., a low-noise amplifier <NUM>) and a programmable gain amplifier <NUM>. The signal is ultimately converted to digital form by an analog-to-digital converter (ADC) <NUM> for processing. But the frequency of the "raw" NMR signal received by the pre-amplifier <NUM> is too high for the ADC <NUM>, and is therefore "down-converted" through comparison with the signal supplied by the RF frequency source <NUM>. A mixer <NUM> combines the amplified NMR signal, which oscillates at the Larmor frequency, with the reference signal from the RF frequency source to generate a new signal that oscillates at a lower "relative Larmor frequency. " Following filtering by a low-pass filter <NUM>, the signal varies slowly enough to be handled by the ADC <NUM> but nonetheless retains the essential frequency characteristics of the received echo signals.

Thus, by measuring the Larmor frequency ω<NUM> described above (e.g., for spectroscopy) and characteristic time T<NUM> (e.g., for relaxometry), NMR techniques can be used as an analytic tool in a number of fields, including but not limited to chemical composition analysis, medical imaging, and bio-sensing.

Significant efforts have been devoted to miniaturizing traditional NMR systems. For example, the entire NMR electronics, including the power amplifier (PA) <NUM>, may be integrated on a single semiconductor device. The numerous advantages of miniaturization include low cost, portability, and the fact that a micro-coil tightly surrounding a small sample increases the signal quality. In addition, reducing the size of the magnet <NUM> allows use of a much smaller power to excite (or polarize) the sample <NUM> than in a conventional system.

<FIG> depicts a traditional class-D PA <NUM> implemented in a miniaturized NMR system; the input signal VS to the PA <NUM> is typically a square-wave signal having low and high amplitudes between the ground (VSSPA) and the PA source voltage (VDDPA). The input signal is used to close and open switches <NUM>, <NUM> in an alternating fashion for connecting an output load <NUM> to either VDDPA or VSSPA. The power transferred to the load <NUM> depends on the output impedance of the amplifier <NUM>, the input signal amplitude VS, and the load impedance RL. In a single-ended PA as depicted in <FIG>, the delivered power can be represented as: <MAT> When the duty cycle of the input switching bipolar square-wave signal is not <NUM>%, the total average power at the fundamental frequency supplied by the PA can be computed as: <MAT> where DUTYCYCLE is the positive duty cycle of the waveform expressed as a decimal fraction in the range from <NUM> to <NUM>. Thus, the total average power is a direct function of the supply voltage VDDPA, the duty cycle of the input square-wave signals, the output impedance of the PA, and the impedance of the load RL.

The traditional class-D PA typically delivers a power ranging from watts to kilowatts. The power may be adjusted by changing the supply voltage VDDPA while maintaining the duty cycle of the switching waveform at <NUM>% (DUTYCYCLE = <NUM>) corresponding to the maximum total average power of the fundamental. In addition, the output impedance ROUT and load impedance RL are generally kept constant so as to ensure impedance matching between the PA and the load resistor <NUM>.

Recent developments in class-D amplifier technology have been exploited to integrate the PA on a semiconductor device and generate excitation signals suitable for NMR measurements, particularly in low-field time-domain NMR relaxometry. Controlling the available power of the integrated class-D PA via adjustment of the supply voltage, VDDPA, however, is not desirable. This is because such adjustment ordinarily requires implementation of an additional power domain and associated pin(s) dedicated exclusively to the PA output drivers; this introduces extra system complexity.

Alternatively, the total available power may be adjusted via changing the duty cycle of the PA switching waveform as shown in <FIG> and Eq. (<NUM>). In this case a duty cycle control block is inserted between RF signal source <NUM> and modulator <NUM> in <FIG>.

Efforts have been made to use analog duty-cycle-control circuits to adjust the duty cycle of the input signals to an integrated PA. Conventional approaches, however, tend to suffer from a high degree of variability and poor control of accuracy when environmental conditions, such as a manufacturing process, supply voltage and operating temperature (PVT) vary. Accordingly, there is a need for an approach that reliably and accurately controls the total available power of the PA by adjusting the duty cycle of the switching input signals. The approach should desirably account for effects resulting from various environmental conditions (e.g., PVT), thereby ensuring repeatably stable power levels during NMR measurements.

In addition, the traditional class-D PA typically has a somewhat limited bandwidth (usually much less than <NUM>). To make NMR measurements, the PA, however, requires a wide bandwidth (e.g., between <NUM> and <NUM>). Further, because the output impedance of the traditional class-D amplifier is fixed, the available power setting is also fixed for the fixed power-supply voltage VDDPA. In other words, the power and output impedance of the amplifier are not separable. Because of this constraint, it is difficult to adjust the power available from the amplifier in order to optimize the excitation parameters (such as magnetization flipping angles and NMR excitation pulse spacing) of an NMR measurement. Another challenge of implementing the traditional class-D amplifer in NMR applications is that it is hard to achieve impedance matching (compared to classic audio or power applications) for optimizing the power delivery (as shown by Eq. (<NUM>) above) and maintain PA power levels with accuracy and consistency for repeatable NMR measurements.

Various strategies to address these difficulties have been proposed, generally involving the use of discrete components for the PA and assuming the ON resistance of the switches <NUM>, <NUM> to be negligible. This allows the output impedance of the PA to be set by an external precision resistor. When integrating the PA and other NMR electronics on a single semiconductor device - resulting in an integrated "switch-mode" power amplifier - the switch devices <NUM>, <NUM> are typically implemented using MOSFETs whose gates are controlled by an input RF signal having a square wave form with an amplitude of VDDPA VSSPA.

In a typical NMR application, the PA drives a <NUM>Ω load impedance. This means that for the case of a differential class-D PA, each PA driver has an output impedance of <NUM>Ω for an optimal, reflection-free power delivery to the load. The ON resistance of the MOS device, however, varies with manufacturing processes, supply voltage and temperature. In addition, the highly nonlinear behavior for large voltages across the device makes it extremely challenging to implement a basic MOSFET switch having a constant ON resistance of <NUM>Ω.

Accordingly, there is a need for an approach that reduces the variability of the output impedance of an integrated switch-mode power amplifier in order to maintain consistent power levels repeatably during NMR measurements.

<CIT> relates to a transmitter with class E amplifier. <CIT> relates to a clock synchronisation delay circuit. <CIT> relates to an integrated circuit including a digitally-controlled power generation stage comprising a plurality of selectable switching devices capable of adjusting an envelope of the radio frequency carrier, and a pulse width modulator generator arranged to generate a pulse width modulator control signal. The pulse width modulator generator inputs the control signal to a subset of the plurality of the selectable switching devices to adjust the envelope radio frequency carrier output from the digitally-controlled power generation stage.

In accordance with the invention there is provided: circuitry for adjusting a duty cycle of an RF carrier input signal to a power amplifier, as recited by claim <NUM>; and an NMR apparatus as recited by claim <NUM>.

Also disclosed herein, but not claimed, is an approach for reducing variability in the output impedance of an integrated switch-mode power amplifier by splitting the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.

In an implementation of circuity for reducing variability in the output impedance, a replica circuit of a class-D PA-driver sensor is utilized to monitor the output impedance of the matched replica switch devices; a software (and/or hardware) implemented state-machine algorithm may then be utilized to automatically adjust the output impedance of the PA to achieve a target value set by a pair of externally matched precision resistors. Implementation of the resistor on-chip may advantageously eliminate the need for an external resistor component and, at the same time, reduce voltage swings across the MOSFET switch device, thereby increasing the linearity thereof.

The present invention generally relates to an approach for accurately setting a duty cycle of PA switching waveforms, and may be implemented using an all-digital PVT sensor circuit. In various implementations, the all-digital PVT sensor circuit measures a pulse width of a periodic reference signal using digital delay line, and subsequently, implements an off-chip digital calculation to program the digital delay line to delay this periodic reference signal so that, when the delayed periodic reference signal is combined with the original (undelayed) reference via a logical AND operation, the resulting signal conforms to a desired duty cycle. In one implementation, the PA is a class-D PA, which may have a single-ended configuration or a differential configuration having two single-ended structures operating in opposite phases.

Also disclosed herein, but not claimed, is circuitry for reducing variability of an output impedance of an integrated switch-mode PA. The circuitry may comprise a PA driver; a pre-driver for facilitating activation and deactivation of the PA driver; and a passive resistor coupled to the PA driver so as to split the output impedance between the PA driver and the passive resistor. The PA driver may comprise or consist of a PMOS device and an NMOS device. Typically, the on-chip passive resistor has an impedance that substantially does not depend on temperature or voltage.

The circuitry reducing variability of an output impedance may further comprise a calibration circuit for calibrating an ON resistance of the PA driver so as to provide stable output power levels. The calibration circuit may comprise a replica circuit of the PA driver and a load resistor, and may further comprise an on-chip voltage divider for generating a reference voltage. The calibration circuit may further comprise a comparator for comparing the reference voltage with an output voltage of the replica circuit and the load resistor. The passive resistor may be on-chip or off-chip.

Also disclosed herein, but not claimed, is an NMR apparatus comprising an NMR coil configured to enclose a sample, an integrated switch-mode PA coupled to the NMR coil, and circuitry for reducing variability of an output impedance of the PA. The circuitry may include (i) a PA driver, (ii) a pre-driver for facilitating activation and deactivation of the PA driver; and (iii) an on-chip passive resistor coupled to the PA driver for splitting the output impedance between the PA driver and the passive resistor. The circuitry may include one or more of the features described above.

Also disclosed herein, but not claimed, is a method of reducing variability of an output impedance of an integrated switch-mode PA. The method may comprise providing a PA driver having at least one MOS device; providing a pre-driver for facilitating activation and deactivation of the PA driver; and adjusting the number of stripes of the MOS device(s) so to provide a desired impedance.

The invention pertains to circuitry for adjusting a duty cycle of an RF carrier input signal to a PA as defined in claim <NUM>.

In various embodiments, the circuitry further comprises a processor having a register for bypassing the digital delay line. Each one of the delay elements may comprise one input and three outputs. For example, a first one of the outputs may be coupled to an input of a successive delay element; a second one of the outputs to an input of a multiplexer; and a third one of the outputs to an input of the time-to-digital converter.

In accordance with the invention, the circuitry further comprises a processor configured to determine the number of the delay elements required for generating the desired duty cycle based on a measurement of the time-to-digital converter. The processor may be implemented on a chip integrating the digital delay line and time-to-digital converter, or off a chip integrating the digital delay line and time-to-digital converter; in the latter case, the circuitry may further comprise a communication module for allowing signal communication between the processor and the chip.

Another aspect of the invention relates to an NMR apparatus comprising an NMR coil configured to enclose a sample; an integrated switch-mode PA coupled to the NMR coil; and circuitry for adjusting a duty cycle of an input signal to a power amplifier (PA) as described above.

In general, as used herein, the term "substantially" means ±<NUM>%, and in some embodiments, ±<NUM>%. In addition, reference throughout this specification to "one example," "an example," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present technology. Thus, the occurrences of the phrases "in one example," "in an example," "one embodiment," or "an embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, routines, steps, or characteristics may be combined in any suitable manner in one or more examples of the technology. The headings provided herein are for convenience only and are not intended to limit or interpret the scope or meaning of the claimed technology.

Also, the drawings are not necessarily to scale, with an emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:.

Refer first to <FIG>, which depicts an exemplary differential class-D PA interface <NUM> coupled to an NMR probe <NUM>. The PA is implemented as a part of a CMOS (Complementary Metal Oxide Semiconductor) application-specific integrated circuit (ASIC) chip. The NMR probe <NUM> includes a coil <NUM> and capacitors CM_P, CM_M, CT. Capacitor CT in combination with inductance of coil <NUM> creates a parallel resonant circuit <NUM>. Capacitor CM_P and CM_M provide a matching network that transforms the impedance of parallel resonant circuit <NUM> to the passive differential impedance RT at the excitation frequency at the output of the PA. The PA <NUM> is implemented as a discrete chip or a part of a larger application specific integrated circuit (ASIC) including a pair of pre-drivers <NUM>, <NUM>, each coupled to output driver P-type and N-type MOSFET devices <NUM>, <NUM>, which are connected in series with an on-chip resistor <NUM> having a resistance RD and function as the PA circuit. The pre-drivers <NUM>, <NUM> receive, respectively, the pulse sequence, its inverse and the carrier signal, and include logical NAND and NOR gates. In a typical switched-mode power amplifier, the sizes of the PMOS device <NUM> and NMOS device <NUM> are chosen to produce a desired PA output power for operation at a target frequency. A fundamental tradeoff exists between the amount of power provided by such PA and its bandwidth due to the parasitic capacitances of devices <NUM>, <NUM>, which reduce the PA bandwidth as their sizes are increased to boost output PA power and vice versa.

In CMOS manufacturing process, ON resistances (RON) - i.e., the resistance across the drain/source path of the MOSFET with the gate terminal configured to operate the MOSFET in a strong inversion linear regime - is a function of many parameters, such as supply voltage, operating temperature, variations in manufacturing parameters including lithography, chemical etching, and electron mobility (among others). As a result, a switching-mode power amplifier using MOSFET devices <NUM>, <NUM> as switches in the in configuration shown in <FIG> will exhibit a large variation of up to <NUM>% in both output power and bandwidth due to variation in the MOSFET ON resistance from one instance of circuit <NUM> to another and over the full range of environmental conditions. To minimize this variation a calibration approach, as further described below, is utilized to adjust the ON resistance of the PMOS device <NUM> and NMOS device <NUM> and keep it at a constant value suited to the particular application.

Because the devices <NUM>, <NUM> are each connected in series with the resistor <NUM>, the target ON resistance of devices <NUM>, <NUM> is RON Ω so as to provide a combined differential PA output impedance of RT = <NUM> × (RON + RD). In a typical NMR instrument, NMR probe <NUM> presents a passive <NUM>Ω load to the PA that is expected to have an output impedance of the same value. This promotes optimal power delivery from the PA to probe <NUM> and avoids electrical reflections that can damage the PA. Without loss of generality, other interface impedance values can be chosen; for example, smaller interface impedance values will result in larger power delivery by the PA. In this case, the value of resistor <NUM> is reduced and the values of matching capacitors CM_P, CM_M are adjusted appropriately to satisfy the power-matching condition and the lower interface impedance.

<FIG> illustrates a circuit for adjusting the ON resistance by changing the total width of the output MOSFET devices <NUM>, <NUM> driving the output of the PA. In one example, PA output devices are configured as a parallel connection of plurality of MOSFET devices ("stripes") each having a width equal to the total desired width of the MOSFET device divided by the chosen number of parallel devices. Without loss of generality, in the example shown in <FIG>, the number of parallel MOSFET devices is indicated as NSTRIPES. In some examples, the number of stripes in PMOSFET devices can differ from the number of stripes in NMOSFET devices to accommodate different variabilities of P-type and N-type MOSFETs. Unlike the conventional class-D PA illustrated in <FIG>, the gate terminals of the output MOSFETS shown in <FIG> can be individually controlled using the illustrated stripe-selection logic circuits <NUM>, <NUM>. In particular, the desired number of stripes is selected by driving HI the appropriate number of bits in the digital control signals SELECT_P_STRIPES and SELECT_N_STRIPES, which are digital signals of width NSTRIPES bits. The value of NSTRIPES is chosen in such that when all stripes of the output MOSFET device are selected, the ON resistance of the MOSFET device is less than the target RON value for the worst-case manufacturing variation, resulting in lowest ON resistance of the typical MOSFET in the chosen manufacturing process, lowest desired operating temperature and highest operating power supply voltage.

The resistance RD of the on-chip resistors <NUM> typically does not depend significantly on temperature and voltage, but may vary in a range of ±<NUM>% as a result of the manufacturing process variations. Thus, total single-ended output impedance of the PA, RON + RD, may vary in the range of ±<NUM>%; this necessitates a calibration approach to provide stable PA output power levels to ensure consistency and repeatability during NMR measurements.

<FIG> illustrates a calibration circuit <NUM>. The calibration circuit <NUM> utilizes sensors integrated on the same chip as the PA circuit <NUM> to accurately measure a DC ON resistance of the switch MOSFET devices of the PA. In various examples, the ON resistance is measured using a PA driver replica circuit <NUM> having PMOSFET and NMOSFET switches <NUM>, <NUM> with on-chip resistors RD and loaded with external resistors <NUM>, <NUM>, respectively; each of the resistors <NUM>, <NUM> has an impedance of RCAL precisely. Devices <NUM>, <NUM> have identical total width and length and have the same number of stripes (NSTRIPES) as devices <NUM>, <NUM> shown in <FIG>. In various examples, the calibration approach implements an on-chip voltage reference <NUM> for generating a reference voltage and a comparator <NUM> for comparing the reference voltage with the output voltage of the sense PMOSFET or NMOSFET <NUM>, <NUM> generated by a resistive divider from VDDPA to VSSPA. The resistive dividers may be formed by the resistors <NUM>, <NUM>, which have a precise impedance of RCAL, resistors RD connected in series with the drain terminal of the PMOSFET and NMOSFET sensors of the calibration circuit, and the ON resistance of the MOSFET devices <NUM>, <NUM>.

In various examples, a decision value of the comparator <NUM> is stored in one of a bank of control registers <NUM>, which are accessible to a digital interface <NUM>. (All of these components may reside on the ASIC <NUM> shown in <FIG>. ) In addition, a finite state machine may be utilized to adjust the corresponding ON resistance of the replica half driver <NUM> until the output voltage of the sense PMOSFET or NMOSFET crosses a threshold voltage corresponding to a target value of the ON resistance. For the PMOSFET sensor circuit, the comparator threshold voltage is chosen to be (<NUM>/<NUM>) × VDDPA where VDDPA is the PA supply voltage. For the NMOSFET sensor circuit, comparator threshold voltage is chosen to be (<NUM>/<NUM>) × VDDPA. The finite state machine may be implemented on or outside the chip <NUM> in hardware and/or software. In some examples, the threshold voltages can be generated internally on the chip using the resistive divider string formed by three identical resistors connected in series from VDDPA to VSSPA. Given the generated threshold voltages, the comparator output will change when the following condition is met for either one of the MOSFET sensors: RON + RD = (RCAL/<NUM>).

In various examples, the PA half-replica impedance sensor <NUM> is controlled by two control registers (e.g., CENSN and CENSP in a Model WG1000 provided by WaveGuide Corporation). Writing logic <NUM> to either one of these registers may enable one or both sense devices <NUM>, <NUM>. In addition, two registers (e.g., CDSN and CDSP) may be used to drive the gates of the MOS sensor devices <NUM>, <NUM> to an appropriate value required for the calibration approach. In some examples, a register (e.g., SELCALREF) is used to select which one of the sense PMOSFET and NMOSFET devices and which reference voltages are connected to the inputs of the decision comparator <NUM>. For example, writing logic <NUM> may select the output from the sense PMOS <NUM> and (<NUM>/<NUM>) × VDDPA reference voltage, whereas writing logic <NUM> may select the output from the sense NMOS <NUM> and (<NUM>/<NUM>) × VDDPA reference voltage.

<FIG> illustrates a representative flow chart <NUM> illustrating operation of the calibration circuit <NUM> for calibrating a PA output impedance. In an example, the output impedance of the PA is calibrated, before each NMR experiment, during the so called "recycle delay" or after the chip is powered up. While no specific algorithm update rate is specified for the steps of the flow chart <NUM>, it is expected that a minimal progression time interval in the finite state machine is determined based on the settling time constants of capacitors in a low-pass filter that are used to remove high-frequency noise at the inputs of the decision comparator <NUM> arising during switching between different comparison thresholds.

With reference to <FIG>, <FIG> and <FIG>, in a first step <NUM>, the circuit <NUM> is enabled. The NMOSFET leg <NUM> of the circuit <NUM> is disabled and the comparator reference <NUM> is set to (<NUM>/<NUM>) × VDDPA reference voltage (step <NUM>). At this point, no stripes of the PMOSFET sense circuit <NUM> are selected (step <NUM>). If the output of the comparator <NUM> is low, additional stripe is enabled in the PMOSFET sense circuit <NUM> (step <NUM>). If the output of the comparator <NUM> is high and the procedure <NUM> has just been entered, an error condition exists where either target RON value of the PMOSFET device is too large and cannot be achieved by selecting even single stripe of the calibration sensor PMOSFET <NUM> or comparator threshold value was chosen incorrectly for the target RON value; otherwise, the current number of stripes is written the register bank <NUM> (step <NUM>). At this point the PMOSFET leg <NUM> of the circuit <NUM> is disabled and the NMOSFET leg <NUM> is enabled, and the comparator reference <NUM> is set to (<NUM>/<NUM>) × VDDPA reference voltage (step <NUM>). All <NUM> stripes of the NMOS sense circuit are selected (step <NUM>). If the output of the comparator <NUM> is now low, the number of stripes selected for the NMOS sense circuit is progressively decremented until the comparator output is high (step <NUM>). Once again, if the comparator output is high and the procedure <NUM> has just been entered, an error condition exists where either target RON value of the NMOSFET device is too small (i.e., cannot be achieved by selecting all stripes of the calibration sense NMOSFET <NUM>) or the comparator threshold value was chosen incorrectly for the target RON value; otherwise, the current number of stripes is written the register bank <NUM> (step <NUM>) and the procedure ends. The target value of the ON resistances having thus been established and set, the NMR circuit is ready for operation.

The calibration method <NUM> may be implemented in the controller <NUM>. Controller <NUM> may be implemented in hardware, software or a combination of the two. For implementations in which the functions of the controller are provided as one or more software programs, the programs may be written in any of a number of high level languages such as PYTHON, PASCAL, JAVA, C, C++, C#, BASIC, various scripting languages, and/or HTML. Additionally, the software can be implemented in an assembly language directed to the microprocessor resident on a target computer; for example, the software may be implemented in Intel 80x86 assembly language if it is configured to run on an IBM PC or PC clone. The software may be embodied on an article of manufacture including, but not limited to, a floppy disk, a jump drive, a hard disk, an optical disk, a magnetic tape, a PROM, an EPROM, EEPROM, field-programmable gate array, or CD-ROM. Implementations using hardware circuitry may be implemented using, for example, one or more FPGA, CPLD or ASIC processors. Controller <NUM> may be implemented in hardware, software or a combination of the two. For implementations in which the functions are provided as one or more software programs, the programs may be written in any of a number of high level languages such as PYTHON, PASCAL, JAVA, C, C++, C#, BASIC, various scripting languages, and/or HTML. Additionally, the software can be implemented in an assembly language directed to the microprocessor resident on a target computer; for example, the software may be implemented in Intel 80x86 assembly language if it is configured to run on an IBM PC or PC clone. The software may be embodied on an article of manufacture including, but not limited to, a floppy disk, a jump drive, a hard disk, an optical disk, a magnetic tape, a PROM, an EPROM, EEPROM, field-programmable gate array, or CD-ROM. Implementations using hardware circuitry may be implemented using, for example, one or more FPGA, CPLD or ASIC processors.

Approaches described herein may be particularly suitable for implementation in a low-field NMR system where multiple transceivers are integrated on the same semiconductor substrate such that multiple simultaneous NMR measurements can be performed at once. A single replica half circuit described above may be used to independently calibrate all on-chip PAs without the need for providing numerous external resistors to match the impedance of each individual PA.

In addition, approaches described herein may be suitable for implementation in a low-field NMR system where an NMR coil is integrated on the same silicon substrate as the NMR transceiver, or on a separate silicon substrate but is encapsulated in the same package. In this situation, the calibration techniques described herein may provide precise and robust power delivery to the NMR coil without directly accessing and configuring the interface between the PA and NMR coil.

An additional benefit is that this technique may also allow class-D PAs to be used with NMR probes having a significantly lower impedance. The ability to precisely control the output impedance at lower absolute impedance values is important because the same absolute variations of PA output impedance may result in larger relative variations of the delivered output power. In micro-NMR, it is desirable to shift from a <NUM>Ω system to a lower-impedance system so as to increase the total available PA and delivered power for the same supply voltage VDDPA.

In various embodiments, with reference to <FIG> and <FIG>, duty-cycle-control (DCC) circuitry <NUM> may be implemented to reliably and accurately set a duty cycle of PA switching waveforms so as to control the total available power of the PA. The DCC circuitry <NUM> includes two main components: a time-to-digital converter logic (TDC LOGIC) block <NUM> and a digital delay line (DDL) <NUM>. Together, block <NUM> and DDL <NUM> form a time-to-digital converter (TDC). DDL <NUM> includes N digital-delay elements <NUM> connected in series, where the output of each delay element is connected to the input of the next delay element and is also connected to one of the inputs of the TDC LOGIC block <NUM>. The total number of delay elements N and the delay Td through each individual delay element <NUM> of the DDL are chosen to ensure that under all PVT conditions, DDL will provide an accurate measurement of <NUM>/<NUM> of the TX carrier period (in units of Td) with the resolution required for a desired accuracy of duty-cycle programming. The TDC is a sensor that measures the number of delay elements <NUM> in the DDL <NUM> required to delay the rising edge of the input TX carrier signal TXRF_IN with a <NUM>% duty cycle by <NUM>/<NUM> of the period of the TX carrier signal (which corresponds to the output of the RF frequency source <NUM> shown in <FIG> and labeled TXRF_IN in <FIG>).

This number of delay elements, designated as DNUMTXCK, represents the measurement of <NUM>/<NUM> of the TX_carrier period in units of Td and is used to compute the required number of delay-line elements <NUM> for generating a DCC_OUT (indicated as TXRF_OUT signal in <FIG>) signal with a specific duty cycle as a fraction of DNUMTXCK. This signal is provided to the modulator <NUM> as the duty-cycle-controlled RF frequency source. The value of DNUMTXCK is always less than or equal to the total number of delay elements N.

With reference to <FIG> and <FIG>, programming the duty cycle of the DCC_OUT signal involves two sequential operations as shown in <FIG>. First, the TDC circuit comprising the DDL <NUM> and the TDC LOGIC block <NUM> measures the TX carrier period, expressed as the closest integer number DNUMTXCK, of the delays Td required to span exactly <NUM>/<NUM> of the TX carrier clock period. And second, the target duty cycle of DCC_OUT is programmed by selecting the required number of delays Td - i.e., DNUMDCC - in the DDL <NUM> to represent the desired duty cycle of the signal DCC_OUT after the delayed signal DELAYED_REF is combined with signal UNDELAYED_REF via a logical AND operation as shown in <FIG>.

In various embodiments, in order to reduce the length of the DDL <NUM> and the TDC LOGIC block <NUM> required to measure the period of the TX carrier signal, the DCC circuitry <NUM> uses an input clock pulse having a duration of exactly <NUM>/<NUM> of the period of TXRF_IN. This clock pulse corresponds to a <NUM>% duty cycle of the TXRF_IN signal and can be generated by performing logic operations on the quadrature phases of the input clock TXRF_IN. In particular, quadrature components TX_CLK0, TX_CLK90, TX_CLK180 and TX_CLK270 of the clock signal TXRF_IN are generated by block TX_CKGEN (as shown in <FIG>) placed at the output of the RF frequency source <NUM>. The quadrature components TX_CK0, TX_CK90, TX_CK180 and TX_CK270 are then provided to a <NUM>% duty cycle generator (DCG) <NUM> that generates <NUM>% duty cycle waveforms of the quadrature phases of the input signal TXRF_IN. Multiplexer <NUM> is then used to select between the quadrature phases of TXRF_IN that have a <NUM>% and a <NUM>% duty cycle.

The DCC circuitry <NUM> may have a HIGH-power mode and a LOW-power mode corresponding to the <NUM>% and <NUM>% duty cycle of the output signal DCC_OUT. These modes are accessible via an internal configuration and/or control registers <NUM>. Specifically, when an internal register corresponding to the multiplexer <NUM> select signal SDCC is written HI, a low-power mode is enabled by selecting one of the quadrature components of the signal TXRF_IN with the <NUM>% duty cycle to propagate through to the input of the modulator <NUM>. Alternatively, when signal SDCC is driven LOW, one of the <NUM>% duty cycle quadrature components of signal RF_CLKIN will propagate to the input of the modulator <NUM>.

A second multiplexer <NUM> is employed during the first operation of the duty cycle programming. It is used to select a single <NUM>% duty cycle clock pulse of the RF_CLKIN signal with quadrature phase <NUM> degrees to perform TDC measurements. The signals and sequence of logic operations during the first operation (TDC measurement) are shown in <FIG>. Prior to the TDC measurement signals SEL_DCC_CK, DCC_MEASURE, DCC_MEASURE_START, DCC_CK_IN, DCC_CAPTURE - also labeled CONTROL SIGNALS in <FIG> - are driven LOW by resetting all associated configuration registers that are used to control these signals via a digital interface. To initiate TDC measurement, signal SEL_DCC_CK is driven HIGH by writing to the associated control register to select DCC_CKIN input of the multiplexer <NUM> to propagate to the DDL <NUM> and TDC LOGIC <NUM>. When the signal DCC_MEASURE is asserted HIGH by writing corresponding internal register, duty cycle control/pulse generation block <NUM> drives HIGH the signal DCC_MEASURE START on the second detected rising edge of the signal CK_PH0_DC25. The rising edge of the signal DCC_MEASURE START then enables propagation of the signal CK_PH0_DC25 to the output DCC_CK_IN of the block <NUM> to the DLL <NUM> and TDC LOGIC BLOCK <NUM>. Consequently, the DCC_CAPTRUE signal is driven HIGH on the third detected rising edge of the signal CK_PH0_DC25 to capture TDC measurement results, TDCOUT, in capture registers <NUM> (see <FIG>) as a digital word DELLENGTH of length M bits, where M is equal or less than the length N of the DDL. At this point, the signal SEL_DCC_CK is driven LOW by writing the corresponding control register in block <NUM>. This disables DCC pulse generation block <NUM> and completes first operation in the DCC programming sequence. It should be noted that the timing between steps in the sequence of operations may not be critical and thus may be set based on application requirements.

The signal DELLENGTH is a temperature-encoded measurement of exactly <NUM>/<NUM> of the TXRF_IN carrier period with the number of non-zero least-significant bits corresponding to the number DNUMTXCK. In some embodiments, the DCC circuitry <NUM> may be bypassed by writing <NUM> into a DCC _BPS_SELECT register of block <NUM> and selecting bypassing input to the multiplexer <NUM>. The DCC_BPS_SELECT register may have a default state set as <NUM>.

Block <NUM> communicates with the interface block <NUM>, which implements an off-chip communications protocol and the physical layer. The interface block <NUM>, in turn, communicates with the processor block <NUM>. The processor block <NUM> includes a conventional central processing unit, memory, and control registers, and may be implemented on a chip integrating various parts of the DCC circuitry <NUM> or off the chip as an external device.

In the second operation of duty cycle programming sequence, the lower M bits of the TDC <NUM> output TDCOUT are written into the register block <NUM> as signal DELLENGTH, and are forwarded to the processor block <NUM> via the interface <NUM>. The processor block <NUM> is a priori provided with information about the desired duty cycle value (DCTARGET), which it stores in an internal memory device. Based on that stored value and the information provided by signal DELLLENGTH, the processor block <NUM> computes the required number of delay elements to generate signal DELAYED_REF. This signal, in turn, is used to generate the output signal DCC_OUT with the target duty cycle by performing logic AND operation on the signals DELAYED_REF and UNDELAYED _REF. The required number of delay elements is binary-encoded and written to the register block <NUM> as the signal SELDELAY of length S via interface <NUM>. The multiplexer <NUM> then decodes binary signal SELDELAY and selects the output of the appropriate delay line element to generate signal DELAYED_REF. The output DCC_OUT of the multiplexer <NUM> is TXRF_OUT, the carrier signal of the DCC controller <NUM> with the target duty cycle value. The DCC controller <NUM> produces the TXRF_OUT carrier signal with duty cycle that is greater than zero and less than or equal to <NUM>%. For applications where lower jitter and low phase noise are required, a "clean" <NUM>% or <NUM>% duty cycle waveform is obtained by bypassing DDL and AND gate <NUM> by writing <NUM> in register DCC _BPS_SELECT as shown in <FIG>.

In various embodiments, for a target duty cycle having a value between <NUM>% and <NUM>%, signal SDCC is driven HIGH to select one of the <NUM>% duty cycle quadrature phases to propagate to the output of the multiplexer <NUM>, DDL <NUM>, multiplexer <NUM> and AND gate <NUM>. The number DNUMDCC of required selected delay elements of DDL for the DCTARGET value is expressed as: <MAT> For a target duty cycle having a value between <NUM>% and <NUM>%, the signal DCC is driven LOW to select one of the <NUM>% duty cycle quadrature phases to propagate to the output of the multiplexer <NUM>, DDL <NUM>, multiplexer <NUM> and AND gate <NUM>. The corresponding computation for number DNUMDCC is expressed as: <MAT>.

<FIG> illustrates the TDC <NUM> and support circuitry in greater detail. Each delay element <NUM> in the DDL <NUM> may have one input and two outputs; delays from the input to any of the outputs may be matched. In one embodiment, one of the outputs is connected to the input of the successive delay element in the DDL chain <NUM> and to one of the inputs of the multiplexer <NUM> that is used to select one of the DLL outputs to generate a TX carrier signal having a desired duty cycle. The second output is directed to a D input of one of a chain of TDC flip-flops <NUM> that collectively provide the lower <NUM> bits of the output of the TDC <NUM>. The flip-flops <NUM> are clocked on the rising edge of the signal CLKREFB that itself is an inverted copy of the signal UNDELAYED _REF. As such, each input of each of the flip-flops <NUM> is captured on the falling edge of signal UNDELAYED _REF. As the signal UNDELAYED_REF propagates through delay elements <NUM>, it reaches the condition where a setup HIGH time violation will occur at some flip-flop, where all downstream flip-flops capturing outputs of delay elements <NUM> will capture logic value LOW and all upstream flip-flops flop will capture logic value HI. The captured logic values in all flip-flops <NUM> then form the digtal signal TDCOUT of length N.

The minimally supported duty cycle may depend on the period of the TX carrier; that period, however, is generally limited by the shortest controlled pulse width for any operating condition. This limit is set by a mismatch in the signal paths of two PA drivers as well as any variation in propagation delays for the pull-up and pull-down drivers that reduce the accuracy of the DCC circuitry <NUM>. This limitation thus results in reduced control over the range of the duty cycle at a lower TX carrier frequency. Accordingly, while the duty cycle control is optimal for the NMR application (or any suitable application), implementing this feature may result in either reduced accuracy in determining the desired duty cycle of the TX carrier at higher frequencies or a reduced control range of the duty cycle at lower frequencies. This can be mitigated by choosing a smaller unit delay Td and/or a larger number of DDL delay elements N.

In various embodiments, a smaller amount of power may be required for excitation of a sample at a lower TX carrier frequency. The availability of the low-power mode with a <NUM>% duty cycle and below the control range may address this requirement. At a higher frequency, more power is required and a TX carrier having a <NUM>% duty cycle is used almost exclusively.

In sum, various embodiments of the present invention provide an all-digital, on-chip duty-cycle control mechanism for accurately setting the duty cycle of PA switching waveforms; this ensures power control with predictable accuracy.

The central processing unit of the processor block <NUM> may be a general-purpose processor and, in some embodiments, may be implemented in the controller <NUM>. Alternatively, the central processing unit of the processor block <NUM> may utilize any of a wide variety of other technologies including special-purpose hardware, a microcomputer, minicomputer, mainframe computer, programmed microprocessor, microcontroller, peripheral integrated circuit element, a CSIC (customer-specific integrated circuit), ASIC (application-specific integrated circuit), a logic circuit, a digital signal processor, a programmable logic device such as an FPGA (field-programmable gate array), PLD (programmable logic device), PLA (programmable logic array), RFID processor, smart chip, or any other device or arrangement of devices that is capable of implementing the steps of the processes of the invention.

Claim 1:
Circuitry (<NUM>) for adjusting a duty cycle of an RF carrier input signal to a power amplifier (PA), the circuitry comprising:
a time-to-digital converter comprising a digital delay line (<NUM>) and a time-to-digital converter logic block (<NUM>), the digital delay line (<NUM>) for receiving the input signal and comprising a plurality of digital delay elements (<NUM>) connected in series, wherein the time-to-digital converter is configured to measure the period of the input signal expressed as a number of the digital delay elements;
circuitry (<NUM>, <NUM>) for selecting a number of delay elements of the digital delay line required to generate an output signal with a desired duty cycle, and for generating the output signal by combining the input signal with a delayed input signal via a logical AND operation, wherein the delayed input signal is generated by the selected number of delay elements; and
a processor having a control register (<NUM>) for enabling a HIGH-power mode or a LOW-power mode of the circuitry, wherein the control register is configured to select the HIGH-power mode if the desired duty cycle has a value between <NUM>% and <NUM>% and the LOW-power mode if the desired duty cycle has a value between <NUM>% and <NUM>%.