Patent Description:
A mobile handset device is generally a small form factor device among other small form factor devices, such as tablet devices. Due to the small configuration of such devices, using the device space economically is of particular interests. In this regard, it may be desirable to convert an audio path (e.g., to a headset or speakers) on a mobile handset device from a <NUM>-millimeter (mm) jack to a Universal Serial Bus (USB) version C (USB-C) port connector, as the USB-C port connector is more versatile (e.g., transmits audio, exchanges USB data, exchanges battery charger data, etc.).

Because of the additional functionality of providing audio over USB-C, the differential transmission data lines DP/DN associated with the host USB-C circuit are loaded with many components, such as switching devices coupling the differential transmission lines DP/DN to audio circuitry, USB application processor (AP), battery charger circuit, electrostatic discharge (ESD) devices, traces, flex connectors, and other circuitry.

<CIT> is disclosing an USB signal transmission circuit.

The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

The invention is as defined in the independent claims <NUM> and <NUM>. Preferred embodiments are according to the dependent claims.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations.

, In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

<FIG> illustrates a schematic/block diagram of an example Universal Serial Bus (USB) host data communication circuit <NUM> in accordance with an aspect of the disclosure. The USB host data communication circuit <NUM> may be integrated into any type of host electronic device, such as a mobile handset device, tablet device, laptop computer, desktop computer, wearable device (e.g., a smart watch, health monitoring device, human activity monitoring device, etc.), Internet of Things (IoT) device, etc..

The USB host data communication circuit <NUM> is referred to as a "host" because it is capable of providing audio to a client device (e.g., a headset, speakers, etc.), and exchanging USB and battery charger data with a client device (e.g., a USB client device, battery charger, etc.). A USB version C (USB-C) compliant circuit serves to exemplify the concepts described herein, but it shall be understood that other versions of USB or other types of data transmission protocols may employ the concepts described herein.

The USB host data communication circuit <NUM> includes a USB-C data switch <NUM>, a USB application processor (AP) <NUM>, a charger circuit <NUM>, an overvoltage protection (OVP) circuit <NUM>, and a USB-C host connector (plug) <NUM>. The USB-C switch <NUM> operates as a multiplexer/demultiplexer to distribute different types of data (e.g., audio, USB, battery charger) to and from USB differential transmission lines DP/DN. The USB-C data switch <NUM> may include at least a portion of an audio circuit, such as a stereo pair of audio amplifiers <NUM>-L (left (L) channel) and <NUM>-R (right (R) channel) coupled in series with associated off-board inductors LL and LR, and a pair of switching devices SWAL and SWAR, respectively. The USB-C data switch <NUM> further includes USB differential data transmission lines DN/DP coupled to the pair of switching devices SWAL and SWAR, respectively.

The USB-C data switch <NUM> further includes a pair of switching devices SWDP and SWDN coupled to the USB differential data transmission lines DP/DN, respectively. In one example, the switching devices SWDP and SWDN may each be implemented as singlepole-triple-throw (SPTT) switches, where the poles (labeled as "p") of the switching devices SWDP and SWDN are coupled to the USB differential data transmission lines DP/DN, respectively. The switching devices SWDP and SWDN may also include first throws (labeled as "<NUM>") coupled to differential data ports DPAP/DNAP of the USB application processor <NUM>, respectively. The switching devices SWDP and SWDN may also include second throws (labeled as "<NUM>"), which may be floating to configure the switching devices in open states. Additionally, the switching devices SWDP and SWDN may include third throws (labeled as "<NUM>") coupled to differential data ports DPC and DNC of the charger circuit <NUM>, respectively.

Alternatively, it shall be understood that separate switching devices may electrically couple the DPAP/DNAP and DPC and DNC data ports of the USB application processor <NUM> and the charger circuit <NUM> to the USB differential data transmission lines DP/DN, respectively. The USB-C data switch <NUM> may further include a control circuit <NUM> configured to control the states of the switching devices SWAL, SWAR, SWDP and SWDN based on a mode signal, as described in more detail further herein. The USB differential data transmission lines DP/DN of the USB-C data switch <NUM> is coupled to the (offboard) overvoltage protection (OVP) circuit <NUM>, which, in turn, is differentially coupled to electrical contacts of the USB-C host connector (plug) <NUM>.

In operation, if the mode signal indicates USB data communication mode, the control circuit <NUM> configures the switching devices SWDP and SWDN to electrically couple the first throws "<NUM>" to the poles "p", and configures the switching devices SWAL and SWAR in open states. In this configuration, a USB differential data signal may be communicated between the differential data ports DPAP/DPAN of the USB application processor <NUM> and the USB differential transmission lines DP/DN for communication with a client device connected to the USB-C host connector <NUM>. Also, in this configuration, the charger circuit <NUM> is electrically isolated from the USB differential data transmission lines DP/DN. Similarly, the switching devices SWAL and SWAR in open states electrically isolates the audio circuitry from the USB differential data transmission lines DP/DN.

If the mode signal indicates audio transmission mode, the control circuit <NUM> configures the switching devices SWDP and SWDN to electrically couple the second throws "<NUM>" to the poles "p", and configures the switching devices SWAL and SWAR in closed states. In this configuration, stereo audio signals generated by the stereo audio amplifiers <NUM>-R and <NUM>-L are applied to the USB differential transmission lines DP/DN via the inductors LR and LL and switching devices SWAL and SWAR for transmission to a client device connected to the USB-C host connector <NUM>. Also, in this configuration, the USB application processor <NUM> and the charger circuit <NUM> are electrically isolated from the USB differential data transmission lines DP/DN.

If the mode signal indicates charger data communication mode, the control circuit <NUM> configures the switching devices SWDP and SWDN to electrically couple the third throws "<NUM>" to the poles "p", and configures the switching devices SWAL and SWAR in open states. In this configuration, battery charger data may be communicated between the charger circuit <NUM> and the USB differential transmission lines DP/DN for communication with a client device connected to the USB-C host connector <NUM>. Also, in this configuration, the USB application processor <NUM> and the audio circuit (amplifiers <NUM>-L/R and inductors LL/LR) are electrically isolated from the USB differential data transmission lines DP/DN.

Due to the communication of audio and charger data, in addition to the USB differential data signal, there is a significant number of components coupled to the USB differential data transmission lines DP/DN. For example, the audio switching devices SWAL and SWAR are coupled to the USB differential data transmission lines DN/DP, which introduces significant parasitic capacitance to the transmission lines DN/DP due to their relatively large size to provide audio signal linearity. Additionally, the switching devices SWDP and SWDN including electrostatic discharge (ESD) devices (not shown) coupled to those switching devices SWDP and SWDN further provide significant parasitic capacitance to the transmission lines DP/DN. Also, there are flex connectors and traces that route the signals between the USB-C data switch <NUM> and the USB-C host connector <NUM> that further adds significant parasitic capacitance to the transmission lines DP/DN.

<FIG> illustrates a schematic diagram of an example Universal Serial Bus (USB) data transmission system <NUM> in accordance with another aspect of the disclosure. The USB data transmission system <NUM> may represent a simplified model for the transmission of USB differential data from a USB application processor of a host device to a client device connected to a USB-C host port connector.

In particular, the USB data transmission system <NUM> includes a USB differential data signal driver <NUM>, a USB-C data switch circuit <NUM> representing parasitic capacitance as discussed above, a USB-C host connector (plug) <NUM>, and a client device <NUM> connected to the USB-C host connector <NUM>.

The USB differential data signal driver <NUM> includes a current source <NUM>, a first field effect transistor (FET) M1 (e.g., a p-channel metal oxide semiconductor (PMOS) FET), and a driver load resistor RDP coupled in series between an upper voltage rail VDD and a lower voltage rail (e.g., ground). The USB differential data signal driver <NUM> further includes a second FET M2 (e.g., a PMOS FET) coupled in series with the current source <NUM> and a second driver load resistor RDN between the upper voltage rail VDD and the lower voltage rail (e.g., ground). The first and second FETs M1 and M2 are configured to receive an input USB differential data signal VINN/VINP, which may be generated internally within a USB application processor. The USB differential data signal driver <NUM> is configured to generate an output USB differential data signal VOUP/VOUN at the drains of the first and second FETs M1 and M2, respectively. The drains of the first and second FETs M1 and M2 may serve as the differential data ports of a USB application processor.

The drains of FETs M1 and M2 (e.g., the differential output of the USB differential data signal driver) are coupled to USB differential transmission lines DP/DN of a USB host circuit. The USB-C data switch circuit <NUM>, representing the parasitic capacitance of the components coupled to the USB differential transmission lines DP/DN, include shunt parasitic capacitors CPARP and CPARN coupled between the USB differential transmission lines DP/DN and the lower voltage rail (e.g., ground), respectively. The USB differential transmission lines DP/DN is electrically coupled to DP/DN contacts of the USB-C host connector (plug) <NUM>. As discussed, the client device <NUM>, being connected to the USB-C host connector (plug) <NUM>, is electrically coupled to the DP/DN contacts of the USB-C host connector (plug) <NUM>, as represented by the client load resistors RLP and RLN being coupled between the DP/DN contacts and the lower voltage rail (e.g., ground), respectively.

<FIG> illustrates a graph of an insertion loss S21 in decibels (dB) versus frequency associated with the data transmission of the USB data transmission system <NUM> in accordance with another aspect of the disclosure. The horizontal axis represents frequency extending from <NUM> mega Hertz (MHz) at the left-end of the graph to two (<NUM>) giga Hertz (GHz) at the right-end of the graph. The vertical axis represents insertion loss from 0dB at the top-end of the graph to -6dB at the bottom-end of the graph.

As the graph illustrates, the insertion loss S21 below <NUM> is relatively low, e.g., being about <NUM>. 2dB or less. However, above <NUM>, the insertion loss S21 increases significantly, e.g., being about <NUM>. 1dB at <NUM>. The increase in the insertion loss S21 above <NUM> is generally caused by parasitic capacitance due to the many components coupled to the USB differential transmission lines DP/DN, as represented by the shunt capacitors CPARP and CPARN of the USB-C data switch circuit <NUM>. The increase in the insertion loss S21 with frequency hinders the rate at which data may be transmitted between the USB host device driver <NUM> and the client device <NUM>. Thus, there is a need to reduce the insertion loss S21 at higher frequencies (e.g., above <NUM>) so that higher data rates may be achieved.

A first order estimation of the insertion loss S21 or voltage Vout across the client device <NUM> may be represented by the following equation: <MAT> where Idrv is the current generated by the current source <NUM>, Gterm is the average conductance of the driver load resistors RDP and RDN, and sCpar is the susceptance associated with the parasitic capacitance or the average capacitance of the capacitors CPARP and CPARN. As the parameter "s" increases with frequency, the output voltage Vout across the client device <NUM> decreases, which is also a measure of the insertion loss S21.

<FIG> illustrates a schematic/block diagram of another example Universal Serial Bus (USB) host data communication circuit <NUM> in accordance with the invention as defined in the claims. The USB host data communication circuit <NUM> is basically the same as the USB host data communication circuit <NUM> previously discussed in detail, but includes an equalizer to reduce the insertion loss S21 at higher frequencies (e.g., above <NUM>), and optionally to reduce the insertion loss at lower frequencies (e.g., below <NUM>). In essence, the equalizer applies negative capacitance to the USB differential transmission lines DP/DN to substantially cancel out the parasitic capacitance associated with the many components coupled to the transmission lines DP/DN, as previously discussed. Optionally, the equalizer may apply negative conductance to the USB differential transmission lines DP/DN to reduce the conductance in the denominator of equation <NUM>.

As mentioned, the USB host data communication circuit <NUM> includes the same components as the USB host data communication circuit <NUM> previously discussed. In USB host data communication circuit <NUM>, the same components or elements are either identified with the same reference labels, and the same reference numbers but with the most significant digit being a "<NUM>" instead of a "<NUM>". The same components or elements have been previously described in detail with reference to the description of the USB host data communication circuit <NUM>.

In addition, the USB-C data switch <NUM> further includes an integrated equalizer <NUM> coupled to the USB differential data transmission lines DP/DN. As discussed, the equalizer <NUM> is configured to reduce the insertion loss S21 at higher frequencies (e.g., above <NUM>), and optionally to reduce the insertion loss S21 at lower frequencies (e.g., below <NUM>). In this regard, the equalizer <NUM> is configured to apply negative capacitance to the USB differential transmission lines DP/DN to substantially cancel or reduce the parasitic capacitance Cpar associated with the components coupled to the transmission lines DP/DN, as previously discussed. Optionally, the equalizer <NUM> may be configured to apply negative conductance to the differential transmission lines DP/DN to reduce the conductance Gterm due to the driver load resistors RDP/RDN. The equalizer <NUM> may be regarded as a shunt equalizer coupled between the USB differential data transmission lines DP/DN and DC and/or AC ground.

<FIG> illustrates a schematic diagram of an equalizer <NUM> in accordance with the invention as defined in claim <NUM>. The equalizer <NUM> is a detailed implementation of the equalizer <NUM> of the USB-C data switch <NUM>.

In particular, the equalizer <NUM> includes a first current source <NUM>-N coupled in series with a first FET M3 (e.g., a PMOS FET) between an upper voltage rail VDD and the negative one (DN) of the USB differential data transmission lines DP/DN. The upper voltage rail VDD may serve as an AC ground. The equalizer <NUM> further includes a second current source <NUM>-P coupled in series with a second FET M4 (e.g., a PMOS FET) between the upper voltage rail VDD and the positive one (DP) of the USB differential data transmission lines DP/DN. The first FET M3 includes a gate coupled to the positive one (DP) of the USB differential data transmission lines DP/DN. The second FET M4 includes a gate coupled to the negative one (DN) of the USB differential data transmission lines DP/DN.

The equalizer <NUM> further includes a capacitor Ceq coupled between a first node n1 between the first current source <NUM>-N and the first FET M3, and a second node n2 between the second current source <NUM>-P and the second FET M4. Optionally, the equalizer <NUM> may include a resistor Req coupled between the first node n1 and the second node n2. So that the negative capacitance and optionally the negative conductance may be configured, including the frequency response (pole(s) and zero(s)) of the equalizer <NUM>, the current sources <NUM>-N and <NUM>-P may be implemented as variable current sources, the capacitor Ceq may be implemented as a variable capacitor, and the optional resistor Req may be implemented as a variable resistor.

A first order estimation of the insertion loss S21 or voltage Vout across the client device <NUM> with the equalizer <NUM> or <NUM> (without the optional resistor Req) may be represented by the following equation: <MAT> where Ceq is the capacitance of the capacitor Ceq. Thus, by properly configuring the capacitance Ceq to be substantially equal to the parasitic capacitance Cpar, the expression sCpar-sCeq may be made substantially equal to zero (<NUM>); thereby, cancelling the frequency dependency of the insertion loss S21 or output voltage Vout for at least a desired frequency range.

A first order estimation of the insertion loss S21 or voltage Vout across the client device <NUM> with the equalizer <NUM> or <NUM> (including the optional resistor Req) may be represented by the following equation: <MAT> where Geq is the conductance of the resistor Req. Thus, by properly configuring the resistance Req, the expression 2Gterm-Geq may be made smaller to achieve a particular insertion loss S21 at lower frequencies (e.g., below <NUM>).

<FIG> illustrates a comparison graph of frequency responses of data communication of the USB host data communication system <NUM> with and without the equalizer <NUM> or <NUM> in accordance with another aspect of the disclosure. The vertical axis of the graph represents insertion loss S21 between a USB data signal driver and a client device using the USB host data transmission circuit <NUM> with or without the integrated equalizer <NUM> or <NUM>. The horizontal axis represents frequency from <NUM> to <NUM>. The solid line represents the insertion loss S21 without the equalization provided by the equalizer <NUM> or <NUM>. The dashed line represents the insertion loss S21 with a less aggressive equalization provided by the integrated equalizer <NUM> or <NUM>. The dot-dashed line represents the insertion loss S21 with a more aggressive equalization provided by the integrated equalizer <NUM> or <NUM>.

As the graph illustrates, without equalization provided by the integrated equalizer <NUM> or <NUM>, the insertion loss S21 rolls off above <NUM>. With the less aggressive equalization provided by the integrated equalizer <NUM> or <NUM>, the insertion loss S21 is relatively flat all the way to <NUM>, and then begins to roll off above that frequency. With the more aggressive equalization provided by the integrated equalizer <NUM> or <NUM>, the insertion loss S21 is relatively flat to <NUM>, then decreases to a peak at about <NUM>, and then begins to roll off above that frequency. Thus, as the insertion loss S21 is significantly reduced at frequencies above <NUM> with the integrated equalizer <NUM> or <NUM>, higher data transmission rates between a USB host device and a client device may be achieved.

<FIG> illustrates a schematic diagram of another equalizer <NUM> in accordance with the invention as defined in claim <NUM>. The equalizer <NUM> is a detailed implementation of the equalizer <NUM> of the USB-C data switch <NUM>. In equalizer <NUM>, the FETs M3 and M4 provide direct current (DC) and alternating current (AC) to the USB differential data transmission lines DP/DN. As a result, the equalizer <NUM> may affect a common mode voltage associated with the USB differential data transmission lines DP/DN. As discussed further herein, the equalizer <NUM> does not affect the common mode voltage associated with the USB differential data transmission lines DP/DN.

More specifically, the equalizer <NUM> includes a first resistor RN, a first FET M5 (e.g., an NMOS FET), and a current source <NUM> coupled in series between an upper voltage rail VDD1 and a lower voltage rail (e.g., ground). The upper voltage rail VDD1 may serve as an AC ground. The equalizer <NUM> further includes a second resistor RP and a second FET M6 (e.g., an NMOS FET).

Additionally, the equalizer <NUM> includes a first capacitor Ceqp coupled between a first node n1 between the first resistor RN and the first FET M5, and a positive one (DP) of the USB differential data transmission lines DP/DN. The equalizer <NUM> also includes a second capacitor Ceqn coupled between a second node n2 between the second resistor RP and the second FET M6, and a negative one (DN) of USB differential data transmission lines DP/DN.

The equalizer <NUM> further includes a third capacitor CINN coupled between the negative one (DN) of the USB differential data transmission lines DP/DN and a gate of the first FET M5. Further, the equalizer <NUM> includes a fourth capacitor CINP coupled between the positive one (DP) of the USB differential data transmission lines DP/DN and a gate of the second FET M6.

The equalizer <NUM> also includes a gate bias voltage source <NUM> configured to generate a gate bias voltage Vbias. Additionally, the equalizer <NUM> includes a third resistor RINN coupled between the gate bias voltage source <NUM> and the gate of the first FET M5. Similarly, the equalizer <NUM> includes a fourth resistor RINP coupled between the gate bias voltage source <NUM> and the gate of the second FET M6.

In operation, when the USB data transmission lines DP/DN transition to logic high/low, the logic low signal on the DN line is AC coupled to the gate of FET M5; thereby, turning off FET M5. Thus, a high frequency current path exists between the upper voltage rail VDD1 and the positive one (DP) of the USB differential data transmission lines DP/DN via the resistor RN and the capacitor Ceqp. Thus, the low voltage on the positive transmission (DP) due to the relatively high insertion loss S21 at high frequencies is boosted by the high frequency current flowing to the positive one (DP) of the USB differential data transmission lines DP/DN.

Similarly, when the USB data transmission lines DP/DN transition to logic low/high, the logic low signal on the DP line is AC coupled to the gate of FET M6; thereby, turning off FET M6. Thus, a high frequency current path exists between the upper voltage rail VDD1 and the negative one (DN) of the USB differential data transmission lines DP/DN via the resistor RP and the capacitor Ceqn. Thus, the low voltage on the negative transmission (DN) due to the relatively high insertion loss S21 at high frequencies is boosted by the high frequency current flowing applied to the negative one (DN) of the USB differential data transmission lines DP/DN.

As the equalizer <NUM> is AC (not DC) coupled to the USB differential data transmission lines DP/DN, the equalizer <NUM> does not affect the common mode voltage associated with the USB differential data transmission lines DP/DN. The capacitors Ceqp and Ceqn may be implemented as variable capacitors, and the current source <NUM> may also be implemented as a variable current source. This allows the negative capacitance and frequency response (pole(s) and zero(s)) of the equalizer <NUM> to be set to achieve the desired high frequency insertion loss S21 compensation.

<FIG> illustrates a schematic diagram of yet another example equalizer <NUM> in accordance with another aspect of the disclosure. The equalizer <NUM> includes the equalizer <NUM> previously discussed, but further includes a negative capacitance equalizer <NUM> to increase the bandwidth of the equalizer <NUM>. That is, due to internal parasitic capacitance in the equalizer <NUM>, the insertion loss S21 compensation provided by the equalizer <NUM> may be bandwidth limited. Thus, the negative capacitance equalizer <NUM> provides negative capacitance to the equalizer <NUM> to substantially cancel or reduce the internal parasitic capacitance of the equalizer <NUM>. As the equalizer <NUM> has been discussed in detail above, the following focusses on the description of the negative capacitance equalizer <NUM>.

In particular, the negative capacitance equalizer <NUM> includes a second current source <NUM>-N coupled in series with a third FET M7 (e.g., a PMOS FET) between an upper voltage rail VDD2 and the first node n1 of the equalizer <NUM>. The upper voltage rail VDD2 may be the same as or different than the upper voltage rail VDD1. The upper voltage rail VDD2 may serve as an AC ground. The negative capacitance equalizer <NUM> further includes a third current source <NUM>-P coupled in series with a fourth FET M8 (e.g., a PMOS FET) between the upper voltage rail VDD2 and the second node n2 of the equalizer <NUM>. The third FET M7 includes a third gate coupled to the second node n2 of the equalizer <NUM>. The fourth FET M7 includes a fourth gate coupled to the first node n1 of the equalizer <NUM>. The negative capacitance equalizer <NUM> also includes a capacitor Ceq2 coupled between a third node n3 between the current source <NUM>-N and the third FET M7, and a fourth node n4 between the current source <NUM>-P and the fourth FET M8.

In operation, when the USB data transmission lines DP/DN transition to logic high/low, the logic low signal on the DN line is AC coupled to the gate of FET M7; thereby, turning on FET M7. Thus, a high frequency current path exists between the current source <NUM>-P and the positive one (DP) of the USB differential data transmission lines DP/DN via the capacitor Ceq2 and FET M7. Thus, the low voltage on the positive transmission line (DP) due to the relatively high insertion loss S21 at high frequencies is boosted by the high frequency current flowing to the positive one (DP) of the USB differential data transmission lines DP/DN.

Similarly, when the USB data transmission lines DP/DN transition to logic low/high, the logic low signal on the DP line is AC coupled to the gate of FET M8; thereby, turning on FET M8. Thus, a high frequency current path exists between the current source <NUM>-N and the negative one (DN) of the USB differential data transmission lines DP/DN via the capacitor Ceq2 and FET M8. Thus, the low voltage on the negative transmission (DN) due to the relatively high insertion loss S21 at high frequencies is boosted by the frequency current flowing to the negative one (DN) of the USB differential data transmission lines DP/DN. The capacitor Ceq2 may be implemented as a variable capacitor, and the current sources <NUM>-N and <NUM>-P may also be implemented as variable current sources. This allows the negative capacitance and frequency response (pole(s) and zero(s)) of the negative capacitance equalizer <NUM> to widen the bandwidth of the equalizer <NUM> as desired.

<FIG> illustrates a flow diagram of an example method <NUM> of communicating Universal Serial Bus (USB) data between a host device and a client device in accordance with another aspect of the disclosure. The method <NUM> includes receiving a Universal Serial Bus (USB) differential data signal to USB differential data transmission lines (block <NUM>). Examples of means for receiving a Universal Serial Bus (USB) differential data signal to USB differential data transmission lines include any of the switching devices SWDP and SWDN or the connection to the OVP circuit <NUM> and/or USB host connector <NUM>.

The method <NUM> further includes equalizing the USB differential data signal (block <NUM>). Examples of means for equalizing the USB differential data signal include any of the equalizers described herein. Additionally, the method <NUM> includes routing the equalized USB differential data signal between an application processor and a USB host connector (block <NUM>). Examples of means for routing the equalized USB differential data signal between an application processor and a USB host connector include the USB differential data transmission lines as described herein.

<FIG> illustrates a block diagram of an example wireless communication device <NUM> in accordance with another aspect of the disclosure. The wireless communication device <NUM> may be implemented as any type of wireless communication device, such as mobile handset device, tablet device, laptop computer, desktop computer, wearable device (e.g., a smart watch, health monitoring device, human activity monitoring device, etc.), Internet of Things (IoT) device, etc..

The wireless communication device <NUM> includes an integrated circuit (IC) <NUM>, which may be implemented as a system on chip (SOC). The SOC <NUM> may include one or more signal processing cores <NUM> coupled to an audio codec <NUM> and a USB application processor <NUM>. The one or more signal processing cores <NUM> may be configured to generate and/or process a baseband (BB) signal. The audio codec <NUM> may be configured to generate stereo analog audio signals AUD-L and AUD-R based on audio data received from the one or more signal processing cores <NUM>. The USB application processor <NUM> is configured to generate a USB differential data signal VOUN/VOUP based on data received from the one or more signal processing cores <NUM>, and/or process the USB differential data signal VOUN/VOUP received from a client device connected to a USB-C host connector (plug) <NUM>.

The wireless communication device <NUM> further includes a USB data switch with integrated equalizer <NUM>, which may be implemented as per USB-C data switch <NUM> including any of the integrated equalizers <NUM>, <NUM>, <NUM>, and <NUM>. The USB-C data switch with integrated equalizer <NUM> is differentially coupled to the USB application processor <NUM> to receive and/or provide the USB differential data signal VOUN/VOUP therefrom and/or thereto. The USB-C host data switch with integrated equalizer <NUM> is coupled to the audio codec <NUM> to receive the stereo analog audio signals AUD-L and AUD-R. The USB host transmission circuit <NUM> may be coupled to a charger circuit <NUM> to receive and/or provide charger data therefrom and/or thereto. The USB-C data switch with integrated equalizer <NUM> includes at least a portion of the USB differential transmission lines DP/DN, which is coupled to an overvoltage protection (OVP) circuit <NUM> and electrical contacts of a USB-C host connector (plug) <NUM>.

A client device may be plugged into the USB-C host connector (plug) <NUM>. If a mode signal indicates USB data communication, the USB-C data switch with integrated equalizer <NUM> may route the USB differential data signal VOUN/VOUP, which is equalized by the integrated equalizer, to the client device or the USB application processor <NUM>. If the mode signal indicates stereo audio transmission, the USB-C data switch with integrated equalizer <NUM> may route the stereo analog audio signals AUD-L and AUD-P to the client device via the USB differential data transmission lines DN/DP, OVP circuit <NUM>, and the USB-C host connector <NUM>. And, if the mode signal indicates charger data communication, the USB host transmission circuit <NUM> may route the charger data signals to the client device or charger circuit <NUM>.

Claim 1:
An apparatus (<NUM>), comprising:
a first pair of switching devices configured to selectively couple an application processor (<NUM>) to Universal Serial Bus, USB, differential data transmission lines (DN/DP);
a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and
an equalizer (<NUM>, <NUM>) including differential terminals coupled to the USB differential data transmission lines, respectively, characterized in that the equalizer (<NUM>) comprises:
a first current source (<NUM>-N);
a first field effect transistor, FET, (M3) coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines;
a second current source (<NUM>-P);
a second FET (M4) coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and
a capacitor (Ceq) coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET.