Patent Description:
<CIT> discloses methods and systems for implementing a user-personalized wake policy which may enable learning of actual user behavior over daily, weekly, and/or monthly time scales. Based on actual usage patterns of a user of an information handling system, the user-personalized wake policy may automatically wake the information handling system in advance of when the user is predicted to desire to use the information handling system. Other actions, such as network data updates, may be automatically performed by the user-personalized wake policy in advance of the user-personalized wake times.

<CIT> discloses a power path controller included in a system-on-chip (SoC). The power path controller is coupled to a first power source and a second power source. The power path controller includes a first switch located between the first power source and a memory core included in the SoC, a second switch located between the second power source and the memory core, a comparator configured to compare a first power supply voltage supplied from the first power source with a second power supply voltage supplied from the second power source, and a switch controller configured to selectively activate the first switch or the second switch according to a comparison result of the comparator.

<CIT> relates to power management via coordination and selective operation of timer-related tasks. A method of coordinating tasks of a mobile computing device may include initializing a timer associated with one or more tasks and a state condition. The state condition may depend on a device state of the mobile computing device and/or a component state of a mobile computing device component. An expiration of the timer is detected. Upon detecting the expiration, a determination is made whether the state condition is satisfied based on whether the mobile computing device is in the device state and/or the mobile computing device component is in the component state. Based at least in part on the determination that the state condition is satisfied, performance of the one or more tasks associated with the timer can be initiated.

<CIT> relates to monitoring a portable electronic device to detect an occurrence of a power event. A command can be sent to a data storage device to initiate a maintenance procedure on the data storage device. In a particular embodiment, a method includes monitoring a portable electronic device to detect an occurrence of a power event. The method also includes selectively sending a command to a data storage device to initiate a maintenance procedure on the data storage device when the occurrence of the power event is detected.

Advantageous embodiments are described by the dependent claims. Embodiments not falling under the scope of the claims should be understood as examples useful for understanding the invention.

A detailed description of systems and methods consistent with embodiments of the present disclosure is provided below. In addition, while numerous specific details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed herein, some embodiments can be practiced without some or all of these details. Moreover, for the purpose of clarity, certain technical material that is known in the related art has not been described in detail in order to avoid unnecessarily obscuring the disclosure.

In an example useful for understanding the invention, techniques, apparatus and methods are disclosed that enable a power delivery system of a computing system which is on alternating current (AC) power to limit software administrative tasks to a system-controlled and tunable broadcast window. In an example useful for understanding the invention, maintenance is restricted until the computing system broadcasts a notification, and legacy software and devices that do not understand these notifications can be told the AC power is not present nominally, and then be notified of AC power presence during maintenance intervals.

For example, while operating on AC power, the system will broadcast a notification to the operating system (OS), applications and/or drivers to regulate requests to the system for the performance of administrative tasks. Administrative tasks can include tasks such as file maintenance, virus scanning, and software updates.

In some embodiments, the system notifies the OS, drivers and software of a defined window for the execution of administrative tasks. In one embodiment, the system suppresses requests from drivers and overlaying software for processing time by reporting that the system is operating on battery power until within the maintenance window, even when the system is operating on AC power. Components unable to process the broadcast identifying the maintenance window withhold requests for system services until being notified that the system is on AC power. By using a maintenance window, a system employing SOix sleep state can achieve a core C6 power state, followed by a platform C10 power state more consistently.

It should be recognized that while specific C-states and RT-states are mentioned, they are presented as an example of a system process. For example, system hardware can pick a state dynamically at any time, even without waking OS up. The system can be in a C2-C10 state depending on what is occurring. In another example, devices do not have to transition back to RTD0 on every C0 maintenance window start. The devices can be brought up as needed. For example, a majority of devices outside of comms and storage may not be needed for maintenance.

Two types of sleeping state models can be supported in modern OSes. A first sleeping state model is Sx. Sx involves notifying applications and drivers, and then powering off the bulk of the hardware with the memory left in self-refresh. Sx use can result in long latency transitions (which can be on the order of seconds) as the system basic input/output system (BIOS) performs pre-OS execution to ready the system for a handoff to the OS. A second sleeping state model is SOix. In SOix, the OS dynamically places devices in lower power states (which may, in turn, be powered off the system BIOS and hardware known as runtime D3 device power state (RTD3) from runtime D0 (RTD0)), and then places threads and/or cores in a low-power C state from a high power C state such as a normal operating state (C0). This low-power C state can map to a core C6, which, in turn, enters a platform C10 state (assuming the devices are inactive and allow for such a state). In this state, the system on a chip (SoC) is capable of achieving low power levels and can allow the system to wake faster than using an Sx-based approach (e.g., under <NUM> for SOix versus over <NUM> second for Sx).

In some computer system designs, low-power states are power-optimized in battery-powered configurations. For energy-efficient desktop computer systems, these capabilities can be used in AC power configurations. In order to achieve a low-power floor, software maintenance activities, such as file system maintenance, virus scanning, and software updates, are deferred in modern-day OSes to when a machine is connected to AC power. Stringent energy regulations are putting pressure on achieving a dramatic reduction in AC power consumption on desktop computing systems (e.g., reducing long idle screen off power from <NUM>-25W to under 10W at the wall). To meet such regulations and/or low-power objectives, a system can ensure that the idle floor is properly testable and clear of maintenance activity, and that the overall net average power consumption across a day in the life of the system is also similarly energy constrained and tunable. A mechanism to trigger software maintenance and updates that will occur within bounded specified and broadcast maintenance intervals can help achieve this objective.

Throughout this disclosure, a hyphenated form of a reference numeral refers to a specific instance of an element, and the unhyphenated form of the reference numeral refers to the element generically or collectively. Thus, widget <NUM>-<NUM> refers to an instance of a widget class, which may be referred to collectively as widgets <NUM>, and any one of which may be referred to generically as a widget <NUM>.

<FIG> is an example illustration of system maintenance activity <NUM> and idling <NUM> with respect to system power state changes <NUM>, <NUM> in a computing system. The computing system is on battery power during the battery-powered time periods <NUM> and on AC power during the AC-powered time period <NUM>. System activity is at a low state <NUM> during the battery-powered time periods <NUM>. System activity varies between high activity <NUM> and low activity <NUM> during the AC-powered time period <NUM>, which can be due to deferred maintenance.

During the times of low activity <NUM>, the system can use an SOix model in which the OS can dynamically place devices in low-power states (which may in turn be powered off by the system BIOS and RTD3). The system can then place the threads/cores in a lowest power C state. This can map to a core C6 power state. When the cores are at a C6 power state, the platform (assuming the devices are inactive and allow for such a state) can enter a platform C10 power state. In this C10 state, the SoC is capable of achieving low power levels, while allowing the system to wake much faster than an Sx-based approach (e.g., less than <NUM> for SOix versus greater than <NUM> second for Sx in some cases).

In the embodiment shown, while the system is AC powered, maintenance activity can run at any time and with unlimited bounds. These unlimited bounds result in an idle power penalty because this activity is unaligned and unbounded.

While the system is on battery power, the system can emphasize achieving a low-power floor. To achieve a low-power floor, software maintenance activities such as file system maintenance, virus scanning, and software updates may be deferred in modern-day OSes, such as a standby mode, to when the system is connected to AC power.

<FIG> is an illustration of system maintenance activity and idling with respect to a system-tunable maintenance window <NUM> in a computing system on AC power. In the embodiment shown, the SoC is restricted to an idle state <NUM> for maintenance activities except during the configurable maintenance window <NUM>. During the maintenance window <NUM>, the SoC is available to exit a low-power state and become active to perform maintenance functions. The maintenance window <NUM> is broadcast to the system by a notification interface.

In some embodiments, an OS application programming interface (API) allows software and devices to register to the notification interface and be notified when they can perform background updates, maintenance or additional processing. The notification interface can be tunable by the end-user, information technology (IT) department, or system manufacturer. The tuning parameters can include: maintenance window triggers on specific time; maintenance window triggers on network events; maintenance interval durations (time); and maintenance interval cycles (such as a percent load parameter).

An OS can include one or more interfaces. In an embodiment, an interface for software and/or drivers indicates the presence of a notification interface. In another embodiment, an interface for software and/or drivers provides registration for notification. In one embodiment, an interface for the platform enables programming activity window parameters and/or registry entries. In some embodiments, the interface can provide a callback notification mechanism on activity window start/stop.

In the embodiment shown, maintenance activity is restricted until the system broadcasts a notification. Software and devices compliant with the maintenance window notification perform maintenance activity during the broadcast maintenance window. Legacy software and devices that do not understand these broadcast messages are told that AC power is not present during the period outside the maintenance window, and are notified of AC power presence during maintenance intervals.

Energy regulations can place pressure to achieve a reduction in AC power consumption on desktop computing systems. In some embodiments, ensuring that the idle floor is properly testable and clear of maintenance activity can aid in achieving the reduction. By limiting maintenance operations to the maintenance window, an overall net average power consumption across a day in the life of the computing system can be further energy-constrained. For example, a computing system is idle <NUM> until the system triggers software maintenance and updates that will occur within a bounded, specified and broadcast maintenance interval <NUM>. Once the maintenance interval <NUM> ends, the system may return to idle <NUM>.

<FIG> illustrates a method of standby power savings. The method can be accomplished by systems including the systems shown in <FIG>, including a power control unit <NUM> and an operating system interface <NUM>. In block <NUM>, the system selects a maintenance window for maintenance activities of the computing system. In block <NUM>, the system detects an idle state of the computing system outside of a maintenance window. In block <NUM>, the system transitions devices of the computing system to a low-power device state. In block <NUM>, the system transitions a CPU of the computing system to a low-power C state. In block, <NUM>, the system transitions the computing system to a low-power platform state. In block <NUM>, the system restricts maintenance activities from occurring until within a maintenance window. In block <NUM>, the system registers one or more systems or components for notification of the maintenance window through an API. In block <NUM>, the system notifies the one or more systems (also known as registered components) of the maintenance window.

<FIG> illustrates a multicore processor used in conjunction with at least one embodiment. In at least one embodiment, a processor <NUM> includes a core region <NUM> and an uncore <NUM>. In some embodiments, the core region <NUM> includes multiple processing cores <NUM>, but disclosed functionality may be applicable to single-core processors in a multiprocessor system. In some embodiments, the processor <NUM> includes a first processing core <NUM>-<NUM>, a second processing core <NUM>-<NUM>, and so forth through an n-th processing core <NUM>-n.

In some examples, the processing cores <NUM> include sub-elements or clusters that provide different aspects of overall functionality. In some embodiments, the processing cores <NUM> include a front end <NUM>, an execution pipeline <NUM>, and a core periphery <NUM>. The core periphery <NUM> can include a first level (L1) data cache <NUM>, a C6 storage <NUM> and an advanced programmable interrupt controller (APIC) <NUM>. In at least one embodiment, the front end <NUM> is operable to fetch instructions from an instruction cache (not depicted) and schedule the fetched instructions for execution. In some embodiments, the execution pipeline <NUM> decodes and performs various mathematical, logical, memory access and flow control instructions in conjunction with a register file (not depicted) and the L1 data cache <NUM>. Thus, in some embodiments, the front end <NUM> may be responsible for ensuring that a steady stream of instructions is fed to the execution pipeline <NUM> while the execution pipeline <NUM> may be responsible for executing instructions and processing the results. In some embodiments, the execution pipeline <NUM> may include two or more arithmetic pipelines in parallel, two or more memory access or load/store pipelines in parallel, and two or more flow control or branch pipelines. In at least one embodiment, the execution pipelines <NUM> may further include one or more floating point pipelines. In some embodiments, the execution pipelines <NUM> may include register and logical resources for executing instructions out of order, executing instructions speculatively, or both. A hyperthread core is a core that is capable of execution of two or more instructions in parallel. Each execution pipeline of a core is called a hyperthread. A hyperthread can be exposed to an OS as a logical core.

The core periphery <NUM> can include logic that supports the front end <NUM> and the execution pipeline <NUM>, including managing storage and interrupts. The core periphery <NUM> can include the L1 data cache <NUM>, the C6 storage <NUM> and the APIC <NUM>. The C6 storage <NUM> can store a context (or state) of the processing core <NUM> when the processing core <NUM> transitions into a low-power state (such as a C6 state). A peripheral controller (e.g., the APIC <NUM>) can manage interrupts for the processing core <NUM>, including identifying which interrupts apply to the associated processing core <NUM> and managing an APIC ID which can be used to identify an associated core.

During execution of memory access instructions, the execution pipeline <NUM> may attempt to execute the instructions by accessing a copy of the applicable memory address residing in the lowest-level cache memory of a cache memory subsystem that may include two or more cache memories arranged in a hierarchical configuration. A cache memory subsystem may include the L1 data caches <NUM> and a last level cache (LLC) <NUM> in the uncore <NUM>. Other elements of the cache memory subsystem may include a per-core instruction cache (not depicted) that operates in conjunction with the front end <NUM> and one or more per-core intermediate caches (not depicted). The cache memory subsystem for the processor <NUM> may include L1 data and instruction caches per core, an intermediate or L2 cache memory per core that includes both instructions and data, and the LLC <NUM>, which includes instructions and data and is shared among multiple processing cores <NUM>. In some embodiments, if a memory access instruction misses in the L1 data cache <NUM>, execution of the applicable program or thread may stall or slow while the cache memory subsystem accesses the various cache memories until a copy of the applicable memory address is found.

The processor <NUM>, the first processing core <NUM>-<NUM>, the second processing core <NUM>-<NUM> and the processing core <NUM>-n may communicate via a crossbar <NUM>, which may support data queuing, point-to-point protocols and multicore interfacing. Other embodiments of the processor <NUM> may employ a shared bus interconnect (not depicted) or direct core-to-core interconnections and protocols. In at least one embodiment, the crossbar <NUM> serves as an uncore controller that interconnects the processing cores <NUM> with the LLC <NUM>. The uncore <NUM> may include a cache controller <NUM> to implement a cache coherency policy and, in conjunction with a memory controller (not depicted), maintain coherency between a system memory (not depicted) and the various cache memories.

A power control unit (PCU) <NUM> may include a placement controller <NUM>. The placement controller <NUM> can monitor workloads of the processing cores <NUM> and determine which work can be moved to a different processing core <NUM> to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as "stressing" a core). Efficiency can be increased by combining multiple threads upon a single hyperthreading core, which saves power of a multicore overhead. Efficiency can be increased by placing threads on cores that are physically separated to enable a larger spread of heat on the processor die. Efficiency can be increased by spreading heat by moving threads from physical processor to physical processor in sequence to heat different parts of a processor die. Efficiency can be increased by using cores with failed arithmetic units when instructions will not use the arithmetic units, and/or migrating threads between cores when the instructions will use the failed arithmetic units. Efficiency can be increased by performing load balancing for lifetime use management and/or thermal management.

As a core is used and/or used to perform a large workload, the efficiency of the core decreases. The efficiency decrease can be due to a larger operating voltage and/or a larger thermal output. A lifetime use of cores can be managed, and workloads transitioned between cores to spread the lifetime usage of cores. The processor can report a lower core count than is actually available on the processor. The workload can be spread among cores to increase the overall lifetime and efficiency of the cores beyond what would be possible without the extra unreported cores. Threads can be transitioned off a core to sequester the core. The sequestered core can be tested and/or performance characteristics of the core can be determined. In one embodiment, core sequestering can be used in conjunction with virtual machine manager solutions. In other embodiments, a sequestered core can be used to support other dedicated-purpose, hidden execution arrangements.

The hardware PCU <NUM> can decide thread placement among the core and hyperthread resources available. Logical processors can be enumerated to the OS. However, the number of logical processors can be less than a number of physical cores and/or hyperthreads that exist in the processor (i.e., there can be more processor resources than are enumerated to the OS). The OS places work on the logical processors visible to it, and the processor (e.g., the PCU <NUM>) may at a later time migrate a thread to a different resource. For example, the PCU <NUM> can initiate a sequence that saves the core's context, restores the context to a different core, and redirects a local APIC ID of the previous core to the new core. This migration can occur at the core or thread level. Alternatively, the hardware can provide migration hints to the OS through an operating system interface <NUM>, and the OS can move the work from one core or thread to another.

The core region <NUM> includes, in addition to the processing cores <NUM>, voltage regulator/clock generator (VRCG) circuits <NUM> for each processing core <NUM>. In conjunction with per-core supply voltage signals and clock frequency signals generated by the PCU <NUM> and provided to each processing core <NUM>, the VRCG circuits <NUM> support per-core power states by applying a power state indicated by the applicable supply voltage signal and clock frequency signal to the applicable processing core <NUM>, as well as to the uncore <NUM>.

The PCU <NUM> may be further operable to select processing cores <NUM> for execution of specific threads and to migrate a thread and its corresponding performance objective or context information from a first core (e.g., the first processing core <NUM>-<NUM>) to a second core (e.g., the second processing core <NUM>-<NUM>), when the performance characteristics of the second processing core <NUM>-<NUM> make the second processing core <NUM>-<NUM> better suited to achieve a desired efficiency objective than the first processing core <NUM>-<NUM>.

The processor <NUM> may include a hybrid assortment of cores including, in addition to the processing cores <NUM>, graphics cores and other types of core logic. In these hybrid core embodiments, the PCU <NUM> determines an optimal or desirable power state, not only for the processing cores <NUM>, but also for these other types of core elements in the core region <NUM>. Similarly, the processor <NUM> may include a VRCG circuit <NUM>-u that provides the power state for the uncore <NUM> and, in this embodiment, the PCU <NUM> may determine the optimal or preferred power states for the uncore <NUM>. The processor <NUM> may support individualized power states for each processing core <NUM>, any other types of cores in the core region <NUM>, and the uncore <NUM>. Other examples may support one power state for the entire core region <NUM> and one power state for the uncore <NUM>.

The PCU <NUM> can also include the operating system interface <NUM>. The PCU <NUM> can provide recommendations for work placement or migration to an OS through the operating system interface <NUM>. The OS can then perform the thread migration between cores. For example, an OS may not have enough information to recognize that two logical processors are actually associated with one hyperthread core. The PCU <NUM> can recommend to the OS that two threads be consolidated on the two logical processors, which can eliminate multicore overhead.

Embodiments may be implemented in many different platforms. <FIG> illustrates a computer system <NUM> used in conjunction with at least one embodiment. In an example, a processor, memory, and input/output devices of a processor system are interconnected by a number of point-to-point (P-P) interfaces, as will be described in further detail. However, the processor system may employ different bus architectures, such as a front side bus, a multi-drop bus, and/or another implementation. Although a processor is shown in <FIG> for descriptive clarity, a different number of processors may be employed using elements of the illustrated architecture.

In an example, the system <NUM> is a point-to-point interconnect system and includes a processor <NUM>. While in some examples the system <NUM> may include a single processor, in other embodiments the system <NUM> may support multiple processors. The processor <NUM> may be a multicore processor including the first processing core <NUM>-<NUM> and the second processing core <NUM>-<NUM>. It is noted that other elements of the processor <NUM> besides the processing cores <NUM> may be referred to as the uncore <NUM>, while the processing cores <NUM> may also be referred to as the core region <NUM>. A varying number of cores may be present in a particular processor. The processing cores <NUM> may comprise a number of sub-elements (not shown in <FIG>), also referred to as clusters, that provide different aspects of overall functionality. The processing cores <NUM> may each include a memory cluster (not shown in <FIG>) that may comprise one or more levels of cache memory. Other clusters (not shown in <FIG>) in the processing cores <NUM> may include a front-end cluster and an execution pipeline cluster. The processing cores <NUM> may include an L1 data cache (not shown in <FIG>). The uncore <NUM> may include a crossbar <NUM>, an LLC <NUM>, a memory controller (MC) <NUM>, a PCU <NUM> and a P-P interface <NUM>. The PCU <NUM> may be used to select a specific core based on the individual characteristics of each core on the die and the specifications of the task.

In examples, the processing cores <NUM> within the processor <NUM> are not equipped with direct means of communicating with each other, but rather communicate via the crossbar <NUM>, which may include intelligent functionality such as cache control, data queuing, P-P protocols, and multicore interfacing. The crossbar <NUM> may thus represent an intelligent uncore controller that interconnects the processing cores <NUM> with the MC <NUM>, the LLC <NUM>, and the P-P interface <NUM>, among other elements. In particular, to improve performance in such an architecture, cache controller functionality within the crossbar <NUM> may enable selective caching of data within a cache hierarchy including the LLC <NUM> and one or more caches present in the processing cores <NUM>. In an example, the crossbar <NUM> is referred to as a global queue.

The LLC <NUM> may be coupled to a pair of the processing cores <NUM>, respectively. The LLC <NUM> may be shared by the first processing core <NUM>-<NUM> and the second processing core <NUM>-<NUM>. The LLC <NUM> may be fully shared such that any single one of the processing cores <NUM> may fill or access the full storage capacity of the LLC <NUM>. Additionally, the MC <NUM> may provide for direct access by the processor <NUM> to a memory <NUM> via a memory interface <NUM>. The memory <NUM> may be a double-data rate (DDR) type dynamic random-access memory (DRAM), while the memory interface <NUM> and the MC <NUM> comply with a DDR interface specification. The memory <NUM> may represent a bank of memory interfaces (or slots) that may be populated with corresponding memory circuits for a desired DRAM capacity.

The processor <NUM> may also communicate with other elements of the system <NUM>, such as a near hub <NUM> and a far hub <NUM>, which are also collectively referred to as a chipset that supports the processor <NUM>. The P-P interface <NUM> may be used by the processor <NUM> to communicate with the near hub <NUM> via an interconnect link <NUM>. In certain examples, the P-P interfaces <NUM>, <NUM> and the interconnect link <NUM> are implemented using Intel® QuickPath Interconnect architecture. The near hub <NUM> may include an interface <NUM> to couple the near hub <NUM> with a first bus <NUM>, which may support high-performance I/O with corresponding bus devices, such as graphics <NUM> and/or other bus devices. The graphics <NUM> may represent a high-performance graphics engine that outputs to a display device (not shown in <FIG>). In an example, the first bus <NUM> is a Peripheral Component Interconnect (PCI) bus, such as a PCI Express (PCIe) bus and/or another computer expansion bus. The near hub <NUM> may also be coupled to the far hub <NUM> at an interface <NUM> via an interconnect link <NUM>. The interface <NUM> may be referred to as a south bridge. The far hub <NUM> may provide I/O interconnections for various computer system peripheral devices and interfaces, and may provide backward compatibility with legacy computer system peripheral devices and interfaces. Thus, in an example, the far hub <NUM> provides a network interface <NUM> and an audio I/O <NUM>, as well as interfaces to a second bus <NUM>, a third bus <NUM>, and a fourth bus <NUM>, as will be described in further detail.

The second bus <NUM> may support expanded functionality for the system <NUM> with I/O devices <NUM> and a touchscreen controller <NUM>, and may be a PCI-type computer bus. The third bus <NUM> may be a peripheral bus for end-user consumer devices, represented by desktop devices <NUM> and communication devices <NUM>, which may include various types of keyboards, computer mice, communication devices, data storage devices, bus expansion devices, etc. The third bus <NUM> may represent a Universal Serial Bus (USB) or similar peripheral interconnect bus. The fourth bus <NUM> may represent a computer interface bus for connecting mass storage devices, such as hard disk drives, optical drives, and disk arrays, which are generically represented by a persistent storage <NUM> that may be accessible by the processor <NUM>.

The system <NUM> may incorporate various features that facilitate a handheld or tablet type of operation and other features that facilitate laptop or desktop operation. In addition, in some embodiments, the system <NUM> includes features that cooperate to aggressively conserve power while simultaneously reducing latency associated with traditional power conservation performance objectives.

The system <NUM> may include an operating system <NUM> that may be entirely or partially stored in the persistent storage <NUM>. The operating system <NUM> may include various modules, APIs, and the like that expose to varying degrees various hardware and software features of the system <NUM>. In at least one example, the system <NUM> includes a sensor application programming interface (API) <NUM>, a resume module <NUM>, a connect module <NUM>, and a touchscreen user interface <NUM>. The system <NUM> may further include various hardware/firmware features including the capacitive or resistive touchscreen controller <NUM> and a second source of persistent storage such as a solid state drive (SSD) <NUM>.

The sensor API <NUM> may provide application program access to one or more sensors (not depicted) that may be included in the system <NUM>. Sensors that the system <NUM> might have in some embodiments include an accelerometer, a global positioning system (GPS) device, a gyrometer, an inclinometer, and a light sensor. The resume module <NUM> may be implemented as software that, when executed, performs operations for reducing latency when transitioning the system <NUM> from a power conservation performance objective to an operating performance objective. The resume module <NUM> may work in conjunction with the SSD <NUM> to reduce the amount of SSD storage used when the system <NUM> enters a power conservation mode. The resume module <NUM> may flush standby and temporary memory pages before transitioning to a sleep mode. By reducing the amount of system memory space that the system <NUM> uses to preserve upon entering a low-power state, the resume module <NUM> beneficially reduces the amount of time used to perform the transition from the low-power state to an operating performance objective. The connect module <NUM> may include software instructions that, when executed, perform complementary functions for conserving power while reducing the amount of latency or delay associated with traditional "wake-up" sequences. The connect module <NUM> may periodically update certain "dynamic" applications including email and social network applications, so that, when the system <NUM> wakes from a low-power mode, the applications that are often most likely to refresh are up-to-date. In an example, the touchscreen user interface <NUM> supports the touchscreen controller <NUM> that enables user input via touchscreens traditionally reserved for handheld applications. The inclusion of touchscreen support in conjunction with support for the communication devices <NUM> enables the system <NUM> to provide features traditionally found in dedicated tablet devices as well as features found in dedicated laptop and desktop systems.

<FIG> illustrates a representation for simulation, emulation, and fabrication of a design implementing the disclosed techniques. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language which basically provides a computerized model of how the designed hardware is expected to perform. A hardware model <NUM> may be stored in a storage medium <NUM> such as a computer memory so that the hardware model <NUM> may be simulated using simulation software <NUM> that applies a particular test suite to the hardware model <NUM> to determine if it indeed functions as intended. In some examples, the simulation software <NUM> is not recorded, captured or contained in the storage medium <NUM>.

Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. This model may be similarly simulated, sometimes by dedicated hardware simulators that form the model using programmable logic. This type of simulation, taken a degree further, may be an emulation technique. In any case, reconfigurable hardware is another embodiment that may involve a tangible machine-readable medium storing a model employing the disclosed techniques.

Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. Again, this data representing the integrated circuit embodies the techniques disclosed in that the circuitry or logic in the data can be simulated or fabricated to perform these techniques.

In any representation of the design, the data may be stored in any form of a tangible machine-readable medium. In some examples, an optical or electrical wave <NUM> modulated or otherwise generated to transmit such information, a memory <NUM>, or a magnetic or optical storage <NUM> such as a disc may be the tangible machine-readable medium. Any of these media may "carry" the design information. The term "carry" (e.g., a tangible machine-readable medium carrying information) thus covers information stored on a storage device or information encoded or modulated into or onto a carrier wave. The set of bits describing the design or the particular part of the design is (when embodied in a machine-readable medium such as a carrier or storage medium) an article that may be sold in and of itself or used by others for further design or fabrication.

The following example embodiments pertain to further embodiments.

Example embodiment <NUM> is a system for managing maintenance activities on system on a chip, SoC. The system comprises legal devices and a processor. The processor is configured to restrict maintenance activities from occurring during a low-power state when not in a maintenance window. The system is also configured to generate a maintenance window notification, and when a maintenance activity occurs during the maintenance window, transition the SoC to an active state and perform the maintenance activity. The system further comprises a notification interface configured to receive registrations for maintenance window notifications, wherein the notification interface is configured to periodically trigger the maintenance window based on a period or periodically trigger the maintenance window based on a percentage of time for the maintenance window. During the maintenance window, the SoC is available to exit a low-power state and become active to perform maintenance functions, and the SoC is restricted to an idle state for maintenance activities except during the maintenance window, wherein to restrict the maintenance activities from occurring further comprises to communicate to the legacy devices that alternating current, AC, is not present when outside of maintenance window, and wherein to generate the maintenance window notification further comprises communicating to the legacy devices that AC is present when inside of the maintenance window.

In Example embodiment <NUM>, the system of Example embodiment <NUM> further comprises a graphics interface and a central processing unit, CPU, interface, both interfaces configured to provide power state information through an application programming interface, API.

In Example embodiment <NUM>, the system of Example embodiment <NUM> further comprises an operating system interface, the operating system interface configured to provide power state information.

Example embodiment <NUM> is a method of performing power management operations of a system on a chip, SoC. The method comprises restricting maintenance activities from occurring during a low-power state when not in a maintenance window. The method also comprises generating a maintenance window notification, and when a maintenance activity occurs during the maintenance window, transitioning the SoC to an active state and performing the maintenance activity. The method further comprises receiving registrations for maintenance window notifications, and periodically triggering the maintenance window based on a period or periodically triggering the maintenance window based on a percentage of time for the maintenance window, wherein, during the maintenance window, the SoC is available to exit a low-power state and become active to perform maintenance functions and the SoC is restricted to an idle state for maintenance activities except during the maintenance window, wherein restricting the maintenance activities from occurring comprises communicating to legacy devices that alternating current, AC, is not present when outside of the maintenance window, and generating the maintenance window notification further comprises communicating to the legacy devices that AC is present when inside of the maintenance window.

In Example embodiment <NUM>, the method of Example embodiment <NUM> further comprises setting a maintenance window duration.

In Example embodiment <NUM>, the method of Example embodiment <NUM> further comprises setting a maintenance window load, the load representing a percentage of time in which to allow maintenance windows.

Example embodiment <NUM> is a machine readable medium including code, when executed, to cause a machine to perform the method of any of Example embodiments <NUM>-<NUM>.

Embodiments and implementations of the systems and methods described herein may include various operations, which may be embodied in machine-executable instructions to be executed by a computer system. A computer system may include one or more general-purpose or special-purpose computers (or other electronic devices). The computer system may include hardware components that include specific logic for performing the operations or may include a combination of hardware, software, and/or firmware.

Computer systems and the computers in a computer system may be connected via a network. Suitable networks for configuration and/or use as described herein include one or more local area networks, wide area networks, metropolitan area networks, and/or Internet or IP networks, such as the World Wide Web, a private Internet, a secure Internet, a value-added network, a virtual private network, an extranet, an intranet, or even stand-alone machines which communicate with other machines by physical transport of media. In particular, a suitable network may be formed from parts or entireties of two or more other networks, including networks using disparate hardware and network communication technologies.

One suitable network includes a server and one or more clients; other suitable networks may contain other combinations of servers, clients, and/or peer-to-peer nodes, and a given computer system may function both as a client and as a server. Each network includes at least two computers or computer systems, such as the server and/or clients. A computer system may include a workstation, laptop computer, disconnectable mobile computer, server, mainframe, cluster, so-called "network computer" or "thin client," tablet, smart phone, personal digital assistant or other hand-held computing device, "smart" consumer electronics device or appliance, medical device, or a combination thereof.

Suitable networks may include communications or networking software, such as the software available from Novell®, Microsoft®, and other vendors, and may operate using TCP/IP, SPX, IPX, and other protocols over twisted pair, coaxial, or optical fiber cables, telephone lines, radio waves, satellites, microwave relays, modulated AC power lines, physical media transfer, and/or other data transmission "wires" known to those of skill in the art. The network may encompass smaller networks and/or be connectable to other networks through a gateway or similar mechanism.

Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, magnetic or optical cards, solid-state memory devices, a nontransitory computer-readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and nonvolatile memory and/or storage elements may be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or other medium for storing electronic data. One or more programs that may implement or utilize the various techniques described herein may use an API, reusable controls, and the like. Such programs may be implemented in a high-level procedural or an object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

Each computer system includes one or more processors and/or memory; computer systems may also include various input devices and/or output devices. The processor may include a general purpose device, such as an Intel®, AMD®, or other "off-the-shelf" microprocessor. The processor may include a special purpose processing device, such as ASIC, SoC, SiP, FPGA, PAL, PLA, FPLA, PLD, or other customized or programmable device. The memory may include static RAM, dynamic RAM, flash memory, one or more flip-flops, ROM, CD-ROM, DVD, disk, tape, or magnetic, optical, or other computer storage medium. The input device(s) may include a keyboard, mouse, touch screen, light pen, tablet, microphone, sensor, or other hardware with accompanying firmware and/or software. The output device(s) may include a monitor or other display, printer, speech or text synthesizer, switch, signal line, or other hardware with accompanying firmware and/or software.

It should be understood that many of the functional units described in this specification may be implemented as one or more components, which is a term used to more particularly emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom very large scale integration (VLSI) circuits or gate arrays, or off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

Components may also be implemented in software for execution by various types of processors. An identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, a procedure, or a function. Nevertheless, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations that, when joined logically together, comprise the component and achieve the stated purpose for the component.

Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within components, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. The components may be passive or active, including agents operable to perform desired functions.

Several aspects of the embodiments described will be illustrated as software modules or components. As used herein, a software module or component may include any type of computer instruction or computer-executable code located within a memory device. A software module may, for instance, include one or more physical or logical blocks of computer instructions, which may be organized as a routine, program, object, component, data structure, etc., that perform one or more tasks or implement particular data types. It is appreciated that a software module may be implemented in hardware and/or firmware instead of or in addition to software. One or more of the functional modules described herein may be separated into sub-modules and/or combined into a single or smaller number of modules.

In certain embodiments, a particular software module may include disparate instructions stored in different locations of a memory device, different memory devices, or different computers, which together implement the described functionality of the module. Indeed, a module may include a single instruction or many instructions, and may be distributed over several different code segments, among different programs, and across several memory devices. Some embodiments may be practiced in a distributed computing environment where tasks are performed by a remote processing device linked through a communications network. In a distributed computing environment, software modules may be located in local and/or remote memory storage devices. In addition, data being tied or rendered together in a database record may be resident in the same memory device, or across several memory devices, and may be linked together in fields of a record in a database across a network.

Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, appearances of the phrase "in an example" in various places throughout this specification are not necessarily referring to the same embodiment.

Claim 1:
A system (<NUM>) for managing maintenance activities (<NUM>) on system on a chip, SoC, the system (<NUM>) comprising:
legacy devices;
a processor (<NUM>, <NUM>) configured to:
restrict maintenance activities (<NUM>) from occurring during a low-power state when not in a maintenance window (<NUM>);
generate a maintenance window notification; and
when a maintenance activity occurs during the maintenance window (<NUM>),
transition the SoC to an active state; and
perform the maintenance activity,
wherein the system further comprises a notification interface configured to receive registrations for maintenance window notifications, wherein the notification interface is configured to periodically trigger the maintenance window (<NUM>) based on a period or periodically trigger the maintenance window (<NUM>) based on a percentage of time for the maintenance window (<NUM>),
wherein, during the maintenance window (<NUM>), the SoC is available to exit a low-power state and become active to perform maintenance functions, and the SoC is restricted to an idle state (<NUM>) for maintenance activities except during the maintenance window (<NUM>),
wherein to restrict the maintenance activities (<NUM>) from occurring further comprises to communicate to the legacy devices that alternating current, AC, is not present when outside of maintenance window (<NUM>), and
wherein to generate the maintenance window notification further comprises communicating to the legacy devices that AC is present when inside of the maintenance window (<NUM>).