Patent Description:
Aspects of the present disclosure relate generally to amplifiers, and more particularly, to sense amplifiers.

Sense amplifiers are used in a wide range of applications including memories, analog-to-digital converters, and data samplers in high-speed serializer/deserializer (SerDes). In the case of a data sampler, a sense amplifier may include a regeneration circuit that provides the sense amplifier with regenerative feedback to quickly resolve incoming data bits in the data sampler. It is desirable to increase the regenerative gain of the regeneration circuit to increase the speed and sensitivity of the sense amplifier.

Attention is drawn to <CIT> relating to an apparatus for comparing differential input signal inputs. The apparatus comprises a CMOS sense amplifier with a first input terminal, a second input terminal, a first output terminal, and a second output terminal, a first output circuit with a first load capacitance, a second output circuit with as a second load capacitance and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier. Further attention is drawn to <CIT> relating to a comparator circuit having a sense amplifier with a differential pair, a voltage excursion limiter, and a switch. The differential pair receives two analog input signals. Its differential outputs operate at a common mode voltage approximately half the supply voltage. The voltage limiter is coupled with one of the differential pair outputs. A capacitor stores comparison results. The switch energizes the differential pair and the voltage excursion limiter during a first phase of a clock, and de-energizes them during a second phase of the clock. During this phase, the comparator provides the stored comparison result to an amplifier with positive feedback.

Additional attention is drawn to <CIT> relating to a comparator comprising a differential input stage comprising a first n-type transistor and a second n-type transistor, an output stage coupled to the differential input stage, a clock transistor coupled to the differential input stage and a pre-charge apparatus connected in parallel with the clock transistor.

Attention is also drawn to <CIT> relating to a comparator circuit including a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch circuit in synchronization with a clock signal, and an equalizing transistor that equalizes the output signals when the latch circuit is inactive. The equalizing transistor is switched on and off by a control signal generated from the clock signal by the control signal generating circuit.

Further attention is drawn to <CIT> relating to a differential latch circuit which places little capacitance on the clock line. The differential latch circuit utilizes differential data signals, and thus, has two data lines. The transfer portion of the latch receives the differential data signals and passes them to the storage portion responsive to a control signal. The storage portion stores and outputs the differential data signals. Each data line in the transfer portion comprises a single transistor pass gate for selectively passing one of the differential data signals responsive to the control signal, which is coupled to the gate terminals of both pass gates.

The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

A first aspect relates to a regeneration circuit. The regeneration circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regeneration circuit also includes a first transistor coupled to the input of the second inverting circuit, wherein a gate of the first transistor is configured to receive a first input signal, and a second transistor coupled to the input of the first inverting circuit, wherein a gate of the second transistor is configured to receive a second input signal. The regeneration circuit further includes a first switch coupled between the first transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal, and a second switch coupled between the second transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.

A second aspect relates to a sense amplifier. The sense amplifier includes an input circuit and a regeneration circuit. The input circuit includes a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, and a drain of the first transistor is coupled to a first output of the input circuit, and a second transistor, wherein a gate of the second transistor is configured to receive a second input signal, and a drain of the second transistor is coupled to a second output of the input circuit. The regeneration circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regeneration circuit also includes a third transistor coupled to the input of the second inverting circuit, wherein a gate of the third transistor is coupled to the second output of the input circuit, and a fourth transistor coupled to the input of the first inverting circuit, wherein a gate of the fourth transistor is coupled to the first output of the input circuit. The regeneration circuit also includes a first switch coupled between the third transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal, and a second switch coupled between the fourth transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.

A third aspect relates to a method of operating a regeneration circuit of a sense amplifier. The regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, and a second transistor coupled to the input of the first inverting circuit. The method includes, in a reset phase, decoupling the output of the first inverting circuit from the first transistor, and decoupling the output of the second inverting circuit from the second transistor. The method also includes, in a sensing phase, coupling the output of the first inverting circuit to the first transistor, and coupling the output of the second inverting circuit to the second transistor.

<FIG> shows an example of a sense amplifier <NUM> according to certain aspects of the present disclosure. The sense amplifier <NUM> may be used, for example, in a data sampler to sample and resolve incoming data bits. The sense amplifier <NUM> includes an input circuit <NUM> and a regeneration circuit <NUM>. The input circuit <NUM> may also be referred to as an input stage and the regeneration circuit <NUM> may also be referred to as a regeneration stage.

The input circuit <NUM> includes a first input transistor <NUM>, a second input transistor <NUM>, a first switch <NUM>, a second switch <NUM>, and a third switch <NUM>. The second switch <NUM> is coupled between a supply rail <NUM> and the first input transistor <NUM>, and the third switch <NUM> is coupled between the supply rail <NUM> and the second input transistor <NUM>. The first input transistor <NUM> is coupled between the second switch <NUM> and node <NUM>, and the second input transistor <NUM> is coupled between the third switch <NUM> and node <NUM>. The first switch <NUM> is coupled between node <NUM> and a ground <NUM>.

In the example shown in <FIG>, the first input transistor <NUM> is implemented with a first n-type field effect transistor (NFET) and the second input transistor <NUM> is implemented with a second NFET. In this example, the second switch <NUM> is coupled between the supply rail <NUM> and the drain of the first input transistor <NUM>, and the first switch <NUM> is coupled between the source of the first input transistor <NUM> and the ground <NUM>. Also, the third switch <NUM> is coupled between the supply rail <NUM> and the drain of the second input transistor <NUM>, and the first switch <NUM> is coupled between the source of the second input transistor <NUM> and the ground <NUM>. It is to be appreciated that the first input transistor <NUM> and the second input transistor <NUM> are not limited to NFETs and may be implemented with other types of transistors.

The input circuit <NUM> is configured to receive a differential input signal (e.g., differential data signal) that includes a first input voltage (labeled "INP") and a second input voltage (labeled "INN"). The first input voltage INP is input to a first input <NUM> of the input circuit <NUM> and the second input voltage INN is input to a second input <NUM> of the input circuit <NUM>, in which the first input <NUM> is coupled to the gate of the first input transistor <NUM> and the second input <NUM> is coupled to the gate of the second input transistor <NUM>. The differential input signal may have a small differential voltage (i.e., a small difference between the first input voltage INP and the second input voltage INN) in which the polarity of the differential voltage represents a bit value. As discussed further below, the sense amplifier <NUM> is configured to convert the small differential input voltage into a large differential output voltage to resolve the bit value.

The first switch <NUM> has a control input <NUM> driven by a first timing signal, the second switch <NUM> has a control input <NUM> driven by the first timing signal, and the third switch <NUM> has a control input <NUM> driven by the first timing signal. In one example, the first switch <NUM> is configured to turn on when the first timing signal is high and turn off when the first timing signal is low, and each one of the second switch <NUM> and the third switch <NUM> is configured to turn on when the first timing signal is low and turn off when the first timing signal is high. In the example shown in <FIG>, the first timing signal is a clock signal (labeled "CLK"). As used herein, a "clock signal" is a periodic signal that oscillates between a high logic state and a low logic state. In certain aspects, a high logic state (i.e., logic state of one) may correspond to a voltage approximately equal to a supply voltage VCC and a low logic state (i.e., logic state of zero) may correspond to a voltage approximately equal to ground.

As used herein, a "control input" of a switch is an input that controls the on/off state of the switch based on a signal (e.g., a voltage of the signal) at the control input. For an example where a switch is implemented with a transistor, the control input is located at the gate of the transistor.

The input circuit <NUM> has a first output <NUM> located at a node between the second switch <NUM> and the first input transistor <NUM>, and a second output <NUM> located at a node between the third switch <NUM> and the second input transistor <NUM>. The voltage at the first output <NUM> (labeled "DINT") and the voltage at the second output <NUM> (labeled "NDINT") are output to the regeneration circuit <NUM>, as discussed further below. In the example in <FIG>, the first output <NUM> is coupled to the drain of the first input transistor <NUM>, and the second output <NUM> is coupled to the drain of the second input transistor <NUM>.

The regeneration circuit <NUM> includes a first input transistor <NUM>, a second input transistor <NUM>, a switch <NUM>, a first inverting circuit <NUM>, and a second inverting circuit <NUM>. As discussed further below, the first inverting circuit <NUM> and the second inverting circuit <NUM> are cross coupled to provide regenerative feedback. As used herein, an "inverting circuit" is a circuit configured to invert a logic state (i.e., logic level or logic value) at an input of the inverting circuit and output the inverted logic state at an output of the inverting circuit. The logic state may be represented by a voltage in which a low voltage (e.g., approximately ground) may represent a logic state of zero and a high voltage (e.g., approximately a supply voltage) may represent a logic state of one. In certain aspects, an inverting circuit has a threshold voltage in which the output of the inverting circuit transitions from low to high when the voltage at the input of the inverting circuit falls below the threshold voltage, and the output of the inverting circuit transitions from high to low when the voltage at the input of the inverting circuit rises above the threshold voltage. An inverting circuit may also be referred to as an inverter, an inverting circuit, or another term.

The regeneration circuit <NUM> has a first input <NUM> coupled to the second output <NUM> of the input circuit <NUM>, and a second input <NUM> coupled to the first output <NUM> of the input circuit <NUM>. Thus, the first input <NUM> receives the voltage NDINT from the input circuit <NUM> and the second input <NUM> receives the voltage DINT from the input circuit <NUM>. In this regard, the voltage NDINT may be considered a first input signal to the regeneration circuit <NUM> and the voltage DINT may be considered a second input signal to the regeneration circuit <NUM>.

The first inverting circuit <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. The second inverting circuit <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. To cross couple the first inverting circuit <NUM> and the second inverting circuit <NUM>, the input <NUM> of the first inverting circuit <NUM> is coupled to the output <NUM> of the second inverting circuit <NUM>, and the input <NUM> of the second inverting circuit <NUM> is coupled to the output <NUM> of the first inverting circuit <NUM>. The cross coupling of the first inverting circuit <NUM> and the second inverting circuit <NUM> provide the regeneration circuit <NUM> with regenerative feedback. The regenerative feedback allows the regeneration circuit <NUM> to achieve regeneration for quicky resolving the values of data bits, as discussed further below.

The first supply terminal <NUM> of the first inverting circuit <NUM> and the first supply terminal <NUM> of the second inverting circuit <NUM> are coupled to a supply node <NUM>. The second supply terminal <NUM> of the first inverting circuit <NUM> and the second supply terminal <NUM> of the second inverting circuit <NUM> are coupled to the ground <NUM>. In this example, a first output <NUM> of the regeneration circuit <NUM> is coupled to the output <NUM> of the second inverting circuit <NUM>, and a second output <NUM> of the regeneration circuit <NUM> is coupled to the output <NUM> of the first inverting circuit <NUM>.

The first input transistor <NUM> is coupled between the output <NUM> of the first inverting circuit <NUM> and the ground <NUM>. The gate of the first input transistor <NUM> is coupled to the first input <NUM> of the regeneration circuit <NUM>. Thus, the gate of the first input transistor <NUM> is configured to receive the voltage NDINT (i.e., the first input signal to the regeneration circuit <NUM>). In one example, the first input transistor <NUM> is configured to turn on when the voltage NDINT is above a threshold voltage of the first input transistor <NUM> and turn off when the voltage NDINT is below the threshold voltage of the first input transistor <NUM>. In the example shown in <FIG>, the first input transistor <NUM> is implemented with an NFET, in which the drain of the first input transistor <NUM> is coupled to the output <NUM> of the first inverting circuit <NUM> and the source of the first input transistor <NUM> is coupled to the ground <NUM>. However, it is to be appreciated that the first input transistor <NUM> may be implemented with another type of transistor.

The second input transistor <NUM> is coupled between the output <NUM> of the second inverting circuit <NUM> and the ground <NUM>. The gate of the second input transistor <NUM> is coupled to the second input <NUM> of the regeneration circuit <NUM>. Thus, the gate of the second input transistor <NUM> is configured to receive the voltage DINT (i.e., the second input signal to the regeneration circuit <NUM>). In one example, the second input transistor <NUM> is configured to turn on when the voltage DINT is above a threshold voltage of the second input transistor <NUM> and turn off when the voltage DINT is below the threshold voltage of the second input transistor <NUM>. In the example shown in <FIG>, the second input transistor <NUM> is implemented with an NFET, in which the drain of the second input transistor <NUM> is coupled to the output <NUM> of the second inverting circuit <NUM> and the source of the second input transistor <NUM> is coupled to the ground <NUM>. However, it is to be appreciated that the second input transistor <NUM> may be implemented with another type of transistor.

The switch <NUM> is coupled between the supply rail <NUM> and the supply node <NUM>. The switch <NUM> has a control input <NUM> driven by a second timing signal. In one example, the second timing signal is a complement of the first timing signal. For the example in which the first timing signal is a clock signal CLK, the second timing signal may be a complementary clock signal (labeled "CLKb"), which may be generated by inverting the clock signal CLK with an inverting circuit (not shown). In one example, the switch <NUM> is configured to turn on when the second timing signal is low (e.g., first timing signal is high) and turn off when the second timing signal is high (e.g., first timing signal is low).

<FIG> shows an example in which the switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the gate of the PFET <NUM> is coupled to the control input <NUM>, and the drain of the PFET <NUM> is coupled to the supply node <NUM>.

Exemplary operations of the sense amplifier <NUM> will now be discussed according to certain aspects.

When the first timing signal (e.g., the clock signal CLK) is low, the sense amplifier <NUM> is in a reset phase. In the reset phase, the first switch <NUM> in the input circuit <NUM> is turned off. As a result, the first switch <NUM> decouples the first input transistor <NUM> and the second input transistor <NUM> from the ground <NUM>. The second switch <NUM> and the third switch <NUM> are turned on. As a result, the second switch <NUM> couples the first output <NUM> to the supply rail <NUM> and the third switch <NUM> couples the second output <NUM> to the supply rail <NUM>. This causes the first output <NUM> to be pulled up to VCC (i.e., the supply voltage on the supply rail <NUM>) and the second output <NUM> to be pulled up to VCC. Thus, the voltage NDINT input to the gate of the first input transistor <NUM> of the regeneration circuit <NUM> and the voltage DINT input to the gate of the second input transistor <NUM> of the regeneration circuit <NUM> are both pulled up to VCC.

In the reset phase, the switch <NUM> in the regeneration circuit <NUM> is turned off since the second timing signal is the complement of the first timing signal and is therefore high when the first timing signal is low. As a result, the switch <NUM> decouples the first supply terminal <NUM> of the first inverting circuit <NUM> from the supply rail <NUM> and decouples the first supply terminal <NUM> of the second inverting circuit <NUM> from the supply rail <NUM>. This disables current flow from the supply rail <NUM> to the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM>.

In the reset phase, the first input transistor <NUM> and the second input transistor <NUM> of the regeneration circuit <NUM> are both turned on since the voltage DINT and the voltage NDINT are both pulled up to the supply voltage VCC (assuming VCC is greater than the threshold voltage of the first input transistor <NUM> and the threshold voltage of the second input transistor <NUM>). As a result, the first input transistor <NUM> pulls the output <NUM> of the first inverting circuit <NUM> to ground and pulls the input <NUM> of the second inverting circuit <NUM> to ground, and the second input transistor <NUM> pulls the output <NUM> of the second inverting circuit <NUM> to ground and pulls the input <NUM> of the first inverting circuit <NUM> to ground.

When the first timing signal (e.g., the clock signal CLK) transitions from low to high, the sense amplifier <NUM> enters a sensing phase in which the input circuit <NUM> senses the differential input signal (e.g., differential data signal) at the inputs <NUM> and <NUM> of the input circuit <NUM>. <FIG> shows an example of the voltages DINT and NDINT during the sensing phase for the case where the input voltage INP is higher than the input voltage INN, which may represent a bit value of one. In this example, the first timing signal (e.g., the clock signal CLK) transitions from low to high at time T1. Also, in this example, the first input transistor <NUM> and the second input transistor <NUM> have the same threshold voltage <NUM>, which is shown in <FIG>.

At time T1, the first switch <NUM> turns on, and the second switch <NUM> and the third switch <NUM> turn off. This allows the first input transistor <NUM> to pull down the voltage DINT at the first output <NUM> based on the input voltage INP driving the first input transistor <NUM>, and the second input transistor <NUM> to pull down the voltage NDINT at the second output <NUM> based on the input voltage INN driving the second input transistor <NUM>. In this example, the voltage DINT at the first output <NUM> is pulled down at a faster rate than the voltage NDINT at the second output <NUM>. This is because the first input transistor <NUM> is driven by a higher voltage than the second input transistor <NUM> in this example (i.e., INP > INN).

At time T2, the voltage DINT falls below the threshold voltage <NUM>, which turns off the second input transistor <NUM> of the regeneration circuit <NUM>. The first input transistor <NUM> of the regeneration circuit <NUM> is still turned on at time T2 since the voltage NDINT is still above the threshold voltage at time T2. At time T2, the regeneration circuit <NUM> transitions from the sensing phase to a decision phase in which the turning off of the second input transistor <NUM> triggers the regenerative feedback of the regeneration circuit <NUM>, which is provided by the cross coupling of the inverting circuits <NUM> and <NUM>, as discussed above. In this example, the regenerative feedback pulls up the first output <NUM> and pulls down the second output <NUM>. An example of this is illustrated in <FIG>, which shows an example of the output voltage OUTP at the first output <NUM> and the output voltage OUTN at the second output <NUM>. As shown in <FIG>, the regenerative feedback pulls up the first output <NUM> and pulls down the second output <NUM> resulting in a large differential output voltage at the outputs <NUM> and <NUM> of the regeneration circuit <NUM> representing the resolved bit value. In this example, the output voltage OUTP is higher than the output voltage OUTN, which may represent a bit decision of one.

At time T3, the first timing signal transitions from high back to low, causing the sense amplifier <NUM> to return to the reset phase and each of the output voltages OUTP and OUTN to return to the reset voltage of approximately zero volts (i.e., ground). Just before time T3, a latch (not shown) coupled to the outputs <NUM> and <NUM> of the regeneration circuit <NUM> may latch the resolved bit value. The latch may include a set-reset (S-R) latch or another type of latch.

The sensing phase and the decision phase are discussed above for the case where the input voltage INP is higher than the input voltage INN. For the case where the input voltage INN is higher than the input voltage INP, the voltage NDINT at the second output <NUM> of the input circuit <NUM> falls below the threshold voltage <NUM> before the voltage DINT at the first output <NUM> of the input circuit <NUM> during the sensing phase, causing the first input transistor <NUM> to turn off before the second input transistor <NUM>. When this occurs, the sense amplifier <NUM> transitions from the sensing phase to the decision phase in which the turning off of the first input transistor <NUM> triggers the regenerative feedback of the regeneration circuit <NUM>. As discussed above, the regenerative feedback is provided by the cross coupling of the inverting circuits <NUM> and <NUM>. In this case, the regenerative feedback pulls up the second output <NUM> and pulls down the first output <NUM>, resulting in a large differential output voltage in which the output voltage OUTN is higher than the output voltage OUTP, which may represent a bit decision of zero.

In the above example, the first switch <NUM> is turned on, the second switch <NUM> and the third switch <NUM> are turned off, and the switch <NUM> is turned on during the sensing phase and the decision phase. The sense amplifier <NUM> enters the decision phase when one of the voltages DINT and NDINT falls below the threshold voltage <NUM> of the input transistors <NUM> and <NUM>, which triggers the regenerative feedback of the regeneration circuit <NUM> to resolve a bit value (i.e., make a bit decision), as discussed above.

The cross coupling of the inverting circuits <NUM> and <NUM> provides regenerative gain when the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> are coupled to the supply rail <NUM> through the switch <NUM>. The inverting circuits <NUM> and <NUM> may draw a large current from the supply rail <NUM> through the switch <NUM> during the sensing phase, causing a large current-resistance (IR) voltage drop to appear across the switch <NUM>. The large IR voltage drop reduces the supply voltage (labeled "Vp") at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM>. An example of this is illustrated in <FIG>, which shows an example of the supply voltage VCC at the supply rail <NUM> and the supply voltage Vp at the supply node <NUM>, which is coupled to the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM>. As shown in <FIG>, at the start of the decision phase at time T2, the supply voltage Vp at the supply node <NUM> may be substantially lower (e.g., over <NUM> percent lower) than the supply voltage VCC at the supply rail <NUM> due to the IR voltage drop across the switch <NUM>. The lower supply voltage Vp may substantially reduce the regenerative gain provided by the cross-coupled inverting circuits <NUM> and <NUM>, which substantially slows down the speed with which the regeneration circuit <NUM> can render a bit decision and reduces the sensitivity of the sense amplifier <NUM>.

To address the above, aspects of the present disclosure provide a regeneration circuit including a first switch coupled between the first input transistor <NUM> and the output <NUM> of the first inverting circuit <NUM>, and a second switch coupled between the second input transistor <NUM> and the output <NUM> of the second inverting circuit <NUM>. As discussed further below, the first and second switches increase the regenerative gain of the cross-coupled inverting circuits <NUM> and <NUM> during the decision phase by eliminating the need for the switch <NUM> and thus eliminating the reduction in the supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> caused by the IR voltage drop across the switch <NUM>. In addition, the first switch is located outside the current path between the input <NUM> of the second inverting circuit <NUM> and the first input transistor <NUM>, and the second switch is located outside the current path between the input <NUM> of the first inverting circuit <NUM> and the second input transistor <NUM>. As discussed further below, this feature substantially reduces the current flow through the first switch and the second switch during the sensing phase and the decision phase, which substantially reduces degradation in the performance of the regeneration circuit <NUM> caused by the presence of the first switch and the second switch.

<FIG> shows the regeneration circuit <NUM> according to the invention. The regeneration circuit <NUM> may be coupled to the exemplary input circuit <NUM> shown in <FIG>. The regeneration circuit <NUM> includes the first inverting circuit <NUM>, the second inverting circuit <NUM>, the first input transistor <NUM>, and the second input transistor <NUM> discussed above.

The input <NUM> of the second inverting circuit <NUM> is coupled to the first input transistor <NUM>, and the input <NUM> of the first inverting circuit <NUM> is coupled to the second input transistor <NUM>. In certain aspects, the input <NUM> of the second inverting circuit <NUM> is directly coupled to the first input transistor <NUM> via first metal routing <NUM>, and the input <NUM> of the first inverting circuit <NUM> is directly coupled to the second input transistor <NUM> via second metal routing <NUM>. The first metal routing <NUM> and the second metal routing <NUM> may each include one or more metal layers on a chip, and one or more metal interconnect structures (e.g., vias) coupling the one or more metal layers. As used herein, the term "directly coupled" refers to coupling between two devices with no intervening device (e.g., a switch).

For the example where the first input transistor <NUM> is implemented with an NFET, the drain of the first input transistor <NUM> is coupled (e.g., directly coupled via the first metal routing <NUM>) to the input <NUM> of the second inverting circuit <NUM>, the gate of the first input transistor <NUM> is coupled to the first input <NUM> of the regeneration circuit <NUM>, and the source of the first input transistor <NUM> is coupled to the ground <NUM>. For the example where the second input transistor <NUM> is implemented with an NFET, the drain of the second input transistor <NUM> is coupled (e.g., directly coupled via the second metal routing <NUM>) to the input <NUM> of the first inverting circuit <NUM>, the gate of the second input transistor <NUM> is coupled to the second input <NUM> of the regeneration circuit <NUM>, and the source of the second input transistor <NUM> is coupled to the ground <NUM>. However, it is to be appreciated that the first input transistor <NUM> and the second input transistor <NUM> are not limited to this example and that each of the first input transistor <NUM> and the second input transistor <NUM> may be implemented with a PFET or another type of transistor.

In this example, the first supply terminal <NUM> of the first inverting circuit <NUM> and the first supply terminal <NUM> of the second inverting circuit <NUM> are coupled to the supply rail <NUM>. In certain aspects, the first supply terminal <NUM> of the first inverting circuit <NUM> and the first supply terminal <NUM> of the second inverting circuit <NUM> are directly coupled (e.g., via metal routing) to the supply rail <NUM>, in which the switch <NUM> shown in <FIG> and <FIG> is omitted. The direct coupling substantially increases the supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> compared with the regeneration circuit <NUM> in <FIG> and <FIG> by eliminating the reduction in the supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> due to the IR voltage drop across the switch <NUM>. The second supply terminal <NUM> of the first inverting circuit <NUM> and the second supply terminal <NUM> of the second inverting circuit <NUM> are coupled to the ground <NUM>.

The regeneration circuit <NUM> also includes a first switch <NUM> and a second switch <NUM>. The first switch <NUM> is coupled between the first input transistor <NUM> and the output <NUM> of the first inverting circuit <NUM>, and the second switch <NUM> is coupled between the second input transistor <NUM> and the output <NUM> of the second inverting circuit <NUM>. For the example where each of the input transistors <NUM> and <NUM> is implemented with an NFET, the first switch <NUM> is coupled between the drain of the first input transistor <NUM> and the output <NUM> of the first inverting circuit <NUM>, and the second switch <NUM> is coupled between the drain of the second input transistor <NUM> and the output <NUM> of the second inverting circuit <NUM>.

In <FIG>, the first switch <NUM> has a control input <NUM> driven by a timing signal (e.g., the clock signal CLK), and the second switch <NUM> has a control input <NUM> driven by the timing signal. The timing signal may be the same timing signal used to control the switches <NUM>, <NUM> and <NUM> in the exemplary input circuit <NUM> shown in <FIG> or another timing signal. In certain aspects, the first switch <NUM> and the second switch <NUM> are configured to turn off when the timing signal is in a first logic state (e.g., low) and turn on when the timing signal is in a second logic state (e.g., high). As discussed further below, the timing signal is in the first logic state during the reset phase and in the second logic state during the sensing phase and the decision phase. Thus, the first switch <NUM> and the second switch <NUM> are turned off during the reset phase and turned on during the sensing phase and the decision phase.

Exemplary operations of the exemplary regeneration circuit <NUM> shown in <FIG> will now be discussed according to certain aspects of the present disclosure.

When the timing signal (e.g., the clock signal CLK) is in the first logic state (e.g., low), the regeneration circuit <NUM> is in the reset phase. In the reset phase, the timing signal turns off the first switch <NUM> and the second switch <NUM>. Turning off the first switch <NUM> decouples the input <NUM> of the second inverting circuit <NUM> from the output <NUM> of the first inverting circuit <NUM>, which breaks the regenerative feedback path between the input <NUM> of the second inverting circuit <NUM> and the output <NUM> of the first inverting circuit <NUM>. Turning off the second switch <NUM> decouples the input <NUM> of the first inverting circuit <NUM> from the output <NUM> of the second inverting circuit <NUM>, which breaks the regenerative feedback path between the input <NUM> of the first inverting circuit <NUM> and the output <NUM> of the second inverting circuit <NUM>.

By breaking the regenerative feedback paths during the reset phase, the first switch <NUM> and the second switch <NUM> disable the regenerative feedback of the regeneration circuit <NUM> during the reset phase. In contrast, the regenerative feedback is disabled during the reset phase in <FIG> and <FIG> by turning off the switch <NUM>, which decouples the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> from the supply rail <NUM> and therefore cuts off power from the supply rail <NUM> to the inverting circuits <NUM> and <NUM>. Thus, the first switch <NUM> and the second switch <NUM> allow the timing signal to disable the regenerative feedback of the regeneration circuit <NUM> during the reset phase without the switch <NUM> in <FIG> and <FIG>. This eliminates the need for the switch <NUM>, which allows the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> to be directly coupled to the supply rail <NUM>. As discussed further below, the first switch <NUM> and the second switch <NUM> may also disable current flow from the supply rail <NUM> to the ground <NUM> during the reset phase.

As discussed above, the voltage NDINT at the first input <NUM> of the regeneration circuit <NUM> and the voltage DINT at the second input <NUM> of the regeneration circuit <NUM> are pulled up to VCC by the input circuit <NUM> during the reset phase. As a result, the voltage NDINT is above the threshold voltage of the first input transistor <NUM>, and the voltage DINT is above the threshold voltage of the second input transistor <NUM> (assuming VCC is above the threshold voltage of each of the first input transistor <NUM> and the second input transistor <NUM>). This causes the first input transistor <NUM> to turn on and pull down the input <NUM> of the second inverting circuit <NUM> to the ground <NUM>, and the second input transistor <NUM> to turn on and pull down the input <NUM> of the first inverting circuit <NUM> to the ground <NUM>.

When the timing signal (e.g., the clock signal CLK) transitions from the first logic state (e.g., low) to the second logic state (e.g., high), the regeneration circuit <NUM> enters the sensing phase and the timing signal turns on the first switch <NUM> and the second switch <NUM>. Turning on the first switch <NUM> couples the input <NUM> of the second inverting circuit <NUM> to the output <NUM> of the first inverting circuit <NUM> through the first switch <NUM>, and turning on the second switch <NUM> couples the input <NUM> of the first inverting circuit <NUM> to the output <NUM> of the second inverting circuit <NUM> through the second switch <NUM>. As a result, the first inverting circuit <NUM> and the second inverting circuit <NUM> are cross coupled through the switches <NUM> and <NUM>. This enables the regenerative feedback of the regeneration circuit <NUM> in the sensing phase. The regenerative feedback allows the regeneration circuit <NUM> to achieve regeneration.

As discussed above, the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> may be directly coupled to the supply rail <NUM>, which substantially increases the supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> compared with the example shown in <FIG> and <FIG> in which the IR voltage drop across the switch <NUM> substantially reduces the supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM>. The increased supply voltage at the first supply terminals <NUM> and <NUM> of the inverting circuits <NUM> and <NUM> increases the regenerative gain of the regeneration circuit <NUM>, which increases the speed with which the regeneration circuit <NUM> can render a bit decision and increases the sensitivity of the sense amplifier <NUM>.

As discussed above, during the sensing phase, the input circuit <NUM> pulls down the voltage NDINT at the first input <NUM> of the regeneration circuit <NUM> and pulls down the voltage DINT at the second input <NUM> of the regeneration circuit <NUM> at different rates depending on the polarity of the differential signal (e.g., differential data signal) input to the input circuit <NUM>. The regeneration circuit <NUM> transitions from the sensing phase to the decision phase when one of the voltages NDINT and DINT falls below the threshold voltage <NUM> of the first input transistor <NUM> and the second input transistor <NUM>, which triggers the regenerative feedback of the regeneration circuit <NUM> to make a bit decision. As discussed above, the regeneration feedback is enabled by the cross coupling of the inverting circuits <NUM> and <NUM> through the switches <NUM> and <NUM> (which are both turned on). The regenerative feedback causes the regeneration circuit <NUM> to pull one of the outputs <NUM> and <NUM> high and pull the other one of the outputs <NUM> and <NUM> low to resolve the bit value depending on which of the voltages NDINT and DINT falls below the threshold voltage <NUM> first, as discussed above.

The presence of the first switch <NUM> and the second switch <NUM> may potentially cause a large voltage offset at the outputs <NUM> and <NUM> of the regeneration circuit <NUM>, which degrades the performance of the regeneration circuit <NUM> and may need to be calibrated out. The large voltage offset may be caused by a difference in the IR voltage drop across the first switch <NUM> and the IR voltage drop across the second switch <NUM> during the sensing phase and decision phase, which is amplified by the regenerative gain of the regeneration circuit <NUM>. The difference in the IR voltage drops across the switches <NUM> and <NUM> may be due to, for example, mismatches in the first switch <NUM> and the second switch <NUM>. The voltage offset caused by the difference in the IR voltage drops across the switches <NUM> and <NUM> can be substantially reduced by substantially reducing the IR voltage drops across the switches <NUM> and <NUM>, as discussed further below.

As shown in <FIG>, the first switch <NUM> is located outside the current path between the input <NUM> of the second inverting circuit <NUM> and the first input transistor <NUM>. This is because the first switch <NUM> is coupled between the first input transistor <NUM> and the output <NUM> of the first inverting circuit <NUM>. As a result, the current flowing between the input <NUM> of the second inverting circuit <NUM> and the first input transistor <NUM> during the sensing phase and the decision phase does not flow through the first switch <NUM>, which substantially reduces the IR voltage drop across the first switch <NUM>.

Similarly, the second switch <NUM> is located outside the current path between the input <NUM> of the first inverting circuit <NUM> and the second input transistor <NUM>. This is because the second switch <NUM> is coupled between the second input transistor <NUM> and the output <NUM> of the second inverting circuit <NUM>. As a result, the current flowing between the input <NUM> of the first inverting circuit <NUM> and the second input transistor <NUM> during the sensing phase and the decision phase does not flow through the second switch <NUM>, which substantially reduces the IR voltage drop across the second switch <NUM>.

Thus, locating the first switch <NUM> outside the current path between the input <NUM> of the second inverting circuit <NUM> and the first input transistor <NUM> and locating the second switch <NUM> outside the current path between the input <NUM> of the first inverting circuit <NUM> and the second input transistor <NUM> substantially reduce the current flow through the first switch <NUM> and the current flow through the second switch <NUM> during the sensing and decision phases. The reduced current flows through the first switch <NUM> and the second switch <NUM> substantially reduce the IR voltage drops across the first switch <NUM> and the second switch <NUM>. The substantially reduced IR voltage drops across the first switch <NUM> and the second switch <NUM> substantially reduces the impact of the IR voltage drops on the voltage offset of the regeneration circuit <NUM>, resulting in a substantially smaller voltage offset due to the difference in the IR voltage drops.

<FIG> shows an example in which the first switch <NUM> is implemented with a first NFET <NUM>, and the second switch <NUM> is implemented with a second NFET <NUM>. In this example, one of the source and the drain of the first NFET <NUM> is coupled to the first input transistor <NUM> (e.g., the drain of the first input transistor <NUM>), the other one of the source and the drain of the first NFET <NUM> is coupled to the output <NUM> of the first inverting circuit <NUM>, and the gate of the first NFET <NUM> is coupled to the control input <NUM> to receive the timing signal (e.g., the clock signal CLK). One of the source and the drain of the second NFET <NUM> is coupled to the second input transistor <NUM> (e.g., the drain of the second input transistor <NUM>), the other one of the source and the drain of the second NFET <NUM> is coupled to the output <NUM> of the second inverting circuit <NUM>, and the gate of the second NFET <NUM> is coupled to the control input <NUM> to receive the timing signal (e.g., the clock signal CLK).

In this example, the first switch <NUM> and the second switch <NUM> are turned off when the timing signal is low and are turned on when the timing signal is high. Thus, in this example, the regeneration circuit <NUM> is in the reset phase when the timing signal is low, and in the sensing phase and the decision phase when the timing signal is high.

It is to be appreciated that the first switch <NUM> and the second switch <NUM> are not limited to the exemplary implementation shown in <FIG>, and that each of the first switch <NUM> and the second switch <NUM> may be implemented with another type of transistor, a transmission gate, or another type of switch. For example, <FIG> shows an example in which the first switch <NUM> also includes a first PFET <NUM> coupled in parallel with the first NFET <NUM>. In this example, the first NFET <NUM> and the first PFET <NUM> form a transmission gate (e.g., complementary metal oxide semiconductor (CMOS) transmission gate) in which the gate of the first PFET <NUM> is driven by the complement of the timing signal (e.g., complementary clock signal CLKb). Also, in this example, the second switch <NUM> also includes a second PFET <NUM> coupled in parallel with the second NFET <NUM>. In this example, the second NFET <NUM> and the second PFET <NUM> form a transmission gate in which the gate of the second PFET <NUM> is driven by the complement of the timing signal (e.g., complementary clock signal CLKb). In some implementations, the NFETs <NUM> and <NUM> may be omitted from the switches <NUM> and <NUM> with the first PFET <NUM> coupled between the first input transistor <NUM> (e.g., drain of the first input transistor <NUM>) and the output <NUM> of the first inverting circuit <NUM> and the second PFET <NUM> coupled between the second input transistor <NUM> (e.g., drain of the second input transistor <NUM>) and the output <NUM> of the second inverting circuit <NUM>.

<FIG> shows an exemplary implementation of the first inverting circuit <NUM> and the second inverting circuit <NUM> according to certain aspects. In this example, the first inverting circuit <NUM> includes a first switch <NUM> and a second switch <NUM>. The first switch <NUM> is coupled between the output <NUM> and the second supply terminal <NUM> of the first inverting circuit <NUM>, and the second switch <NUM> is coupled between the output <NUM> and the first supply terminal <NUM> of the first inverting circuit <NUM>. A control input <NUM> of the first switch <NUM> and a control input <NUM> of the second switch <NUM> are coupled to the input <NUM> of the first inverting circuit <NUM>.

In operation, the first switch <NUM> is configured to turn on and the second switch <NUM> is configured to turn off when the voltage at the input <NUM> is high (e.g., approximately VCC). In this case, the first switch <NUM> pulls the output <NUM> low. The first switch <NUM> is configured to turn off and the second switch <NUM> is configured to turn on when the voltage at the input <NUM> is low (e.g., approximately ground). In this case, second switch <NUM> pulls the output <NUM> high. Each of the switches <NUM> and <NUM> may be implemented with one or more transistors, a transmission gate, or another type of switch.

In this example, the second inverting circuit <NUM> includes a first switch <NUM> and a second switch <NUM>. The first switch <NUM> is coupled between the output <NUM> and the second supply terminal <NUM> of the second inverting circuit <NUM>, and the second switch <NUM> is coupled between the output <NUM> and the first supply terminal <NUM> of the second inverting circuit <NUM>. A control input <NUM> of the first switch <NUM> and a control input <NUM> of the second switch <NUM> are coupled to the input <NUM> of the second inverting circuit <NUM>.

In operation, the first switch <NUM> is configured to turn on and the second switch <NUM> is configured to turn off when the voltage at the input <NUM> is high (e.g., approximately VCC). In this case, the first switch <NUM> pulls the output <NUM> low. The first switch <NUM> is configured to turn off and the second switch <NUM> is configured to turn on when the voltage at the input <NUM> is low (i.e., approximately ground). In this case, second switch <NUM> pulls the output <NUM> high. Each of the switches <NUM> and <NUM> may be implemented with one or more transistors, a transmission gate, or another type of switch.

<FIG> shows an exemplary implementation of the first switch <NUM> and the second switch <NUM> in the first inverting circuit <NUM>. In this example, the first switch <NUM> includes an NFET <NUM> and the second switch <NUM> includes a PFET <NUM>. The drain of the NFET <NUM> is coupled to the output <NUM>, the gate of the NFET <NUM> is coupled to the control input <NUM>, and the source of the NFET <NUM> is coupled to the second supply terminal <NUM>. The source of the PFET <NUM> is coupled to the first supply terminal <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM>, and the gate of the PFET <NUM> is coupled to the control input <NUM>.

<FIG> also shows an exemplary implementation of the first switch <NUM> and the second switch <NUM> in the second inverting circuit <NUM>. In this example, the first switch <NUM> includes an NFET <NUM> and the second switch <NUM> includes a PFET <NUM>. The drain of the NFET <NUM> is coupled to the output <NUM>, the gate of the NFET <NUM> is coupled to the control input <NUM>, and the source of the NFET <NUM> is coupled to the second supply terminal <NUM>. The source of the PFET <NUM> is coupled to the first supply terminal <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM>, and the gate of the PFET <NUM> is coupled to the control input <NUM>.

In the examples shown in <FIG> and <FIG>, the first switch <NUM> and the second switch <NUM> disable current paths from the supply rail <NUM> to the ground <NUM> during the reset phase. An example of this is illustrated in <FIG>, which indicates each of the devices in the regeneration circuit <NUM> that is turned off during the reset phase with an "X". As shown in <FIG>, the first switch <NUM> and the second switch <NUM> are turned off. Also, the first switch <NUM> (e.g., NFET <NUM>) in the first inverting circuit <NUM> is turned off. This is because the second input transistor <NUM> pulls the input <NUM> of the first inverting circuit <NUM> to the ground <NUM> during the reset phase, which turns off the first switch <NUM>. The first switch <NUM> (e.g., NFET <NUM>) in the second inverting circuit <NUM> is also turned off. This is because the first input transistor <NUM> pulls the input <NUM> of the second inverting circuit <NUM> to the ground <NUM> during the reset phase, which turns off the first switch <NUM>.

The turning off of the first switch <NUM> and the first switch <NUM> in the first inverting circuit <NUM> prevents current flow from the first supply terminal <NUM> of the first inverting circuit <NUM> to the ground <NUM>, and the turning off of the second switch <NUM> and the first switch <NUM> in the second inverting circuit <NUM> prevents current flow from the first supply terminal <NUM> of the second inverting circuit <NUM> to the ground <NUM>. As a result, the first switch <NUM> and the second switch <NUM> disable current flow from the supply rail <NUM> to the ground <NUM> during the reset phase, which reduces power consumption of the regeneration circuit <NUM> during the reset phase. In contrast, in the example shown in <FIG> and <FIG>, current flow from the supply rail <NUM> to the ground <NUM> is disabled during the reset phase by turning off the switch <NUM>, which decouples the inverting circuits <NUM> and <NUM> from the supply rail <NUM>.

It is to be appreciated that the inverting circuits <NUM> and <NUM> are not limited to the exemplary implementations shown in <FIG> and <FIG>. Accordingly, it is to be appreciated that each of the inverting circuits <NUM> and <NUM> may be implemented with any one of a variety of circuits configured to invert a logic state (i.e., logic level or logic value), and is therefore not limited to a particular implementation.

<FIG> shows an example in which the regeneration circuit <NUM> further includes a first pull-up transistor <NUM> and a second pull-up transistor <NUM> according to certain aspects of the present disclosure. As discussed further below, the first pull-up transistor <NUM> and the second pull-up transistor <NUM> boost the regenerative gain of the regeneration circuit <NUM>.

In the example in <FIG>, the first pull-up transistor <NUM> is implemented with a first PFET and the second pull-up transistor <NUM> is implemented with a second PFET. In this example, the source of the first pull-up transistor <NUM> is coupled to the supply rail <NUM>, the drain of the first pull-up transistor <NUM> is coupled to the input <NUM> of the first inverting circuit <NUM>, and the gate of the first pull-up transistor <NUM> is coupled to the output <NUM> of the first inverting circuit <NUM>. The source of the second pull-up transistor <NUM> is coupled to the supply rail <NUM>, the drain of the second pull-up transistor <NUM> is coupled to the input <NUM> of the second inverting circuit <NUM>, and the gate of the second pull-up transistor <NUM> is coupled to the output <NUM> of the second inverting circuit <NUM>.

When the voltage DINT falls faster than the voltage NDINT during the sensing phase (e.g., INP > INN at the inputs <NUM> and <NUM> of the input circuit <NUM>), the second input transistor <NUM> turns off before the first input transistor <NUM>. This triggers the regenerative feedback of the regeneration circuit <NUM> to pull up the first output <NUM> and pull down the second output <NUM>. The pulling down of the second output <NUM> turns on the first pull-up transistor <NUM> since the gate of the first pull-up transistor <NUM> is coupled to the second output <NUM> through the first switch <NUM>. When the first pull-up transistor <NUM> turns on, the first pull-up transistor <NUM> pulls up the input <NUM> of the first inverting circuit <NUM> to the supply voltage VCC on the supply rail <NUM>, which helps drive the output <NUM> of the first inverting circuit <NUM> low. Since the output <NUM> of the first inverting circuit <NUM> is coupled to the second output <NUM> through the first switch <NUM>, driving the output <NUM> of the first inverting circuit <NUM> low helps pull down the second output <NUM> and hence boost the regenerative gain of the regeneration circuit <NUM>.

When the voltage NDINT falls faster than the voltage DINT during the sensing phase (e.g., INN > INP at the inputs <NUM> and <NUM> of the input circuit <NUM>), the first input transistor <NUM> turns off before the second input transistor <NUM>. This triggers the regenerative feedback of the regeneration circuit <NUM> to pull up the second output <NUM> and pull down the first output <NUM>. The pulling down of the first output <NUM> turns on the second pull-up transistor <NUM> since the gate of the second pull-up transistor <NUM> is coupled to the first output <NUM> through the second switch <NUM>. When the second pull-up transistor <NUM> turns on, the second pull-up transistor <NUM> pulls up the input <NUM> of the second inverting circuit <NUM> to the supply voltage VCC on the supply rail <NUM>, which helps drive the output <NUM> of the second inverting circuit <NUM> low. Since the output <NUM> of the second inverting circuit <NUM> is coupled to the first output <NUM> through the second switch <NUM>, driving the output <NUM> of the second inverting circuit <NUM> low helps pull down the first output <NUM> and hence boost the regenerative gain of the regeneration circuit <NUM>.

Thus, the first pull-up transistor <NUM> and the second pull-up transistor <NUM> boost the regenerative gain of the regeneration circuit <NUM>. The first pull-up transistor <NUM> boosts the regenerative gain for the case where the voltage DINT falls faster than the voltage NDINT during the sensing phase (e.g., INP > INN at the inputs <NUM> and <NUM> of the input circuit <NUM>) by pulling up the input <NUM> of the first inverting circuit <NUM> to the supply voltage VCC. The second pull-up transistor <NUM> boosts the regenerative gain for the case where the voltage NDINT falls faster than the voltage DINT during the sensing phase (e.g., INN > INP at the inputs <NUM> and <NUM> of the input circuit <NUM>) by pulling up the input <NUM> of the second inverting circuit <NUM> to the supply voltage VCC.

<FIG> shows an exemplary implementation of the first switch <NUM>, the second switch <NUM>, and the third switch <NUM> in the input circuit <NUM> of the sense amplifier <NUM> according to certain aspects. Note that details of the regeneration circuit <NUM> are not shown in <FIG> for ease of illustration. As shown in <FIG>, the first output <NUM> of the input circuit <NUM> is coupled to the second input <NUM> of the regeneration circuit <NUM>, and the second output <NUM> of the input circuit <NUM> is coupled to the first input <NUM> of the regeneration circuit <NUM>. The regeneration circuit <NUM> may be implemented with any one of the exemplary implementations shown in <FIG>.

In the example in <FIG>, the first switch <NUM> is implemented with an NFET <NUM> in which the drain of the NFET <NUM> is coupled to the sources of the input transistors <NUM> and <NUM>, the gate of the NFET <NUM> is coupled to the control input <NUM>, and the source of the NFET <NUM> is coupled to the ground. The second switch <NUM> is implemented with a first PFET <NUM> in which the source of the first PFET <NUM> is coupled to the supply rail <NUM>, the gate of the first PFET <NUM> is coupled to the control input <NUM>, and the drain of the first PFET <NUM> is coupled to the drain of the first input transistor <NUM>. The third switch <NUM> is implemented with a second PFET <NUM> in which the source of the second PFET <NUM> is coupled to the supply rail <NUM>, the gate of the second PFET <NUM> is coupled to the control input <NUM>, and the drain of the second PFET <NUM> is coupled to the drain of the second input transistor <NUM>.

The first switch <NUM>, the second switch <NUM>, and the third switch <NUM> in the input circuit <NUM> may be driven by the same timing signal (e.g., the clock signal CLK) as the first switch <NUM> and the second switch <NUM> in the regeneration circuit <NUM>. In this example, the first switch <NUM> is turned off, and the second switch <NUM> and the third switch <NUM> are turned on when the timing signal is low. The first switch <NUM> is turned on, and the second switch <NUM> and the third switch <NUM> are turned off when the timing signal is high. In this example, the timing signal is low during the reset phase and is high during the sensing phase and the decision phase.

<FIG> shows an example of a system <NUM> in which aspects of the present disclosure may be used. In this example, the system <NUM> includes a first chip <NUM> and a second chip <NUM> in which SerDes may be used for communication between the first chip <NUM> and the second chip <NUM>. The first chip <NUM> includes a serializer <NUM>, a driver <NUM>, a first output pin <NUM>, and a second output pin <NUM>. The second chip <NUM> includes a first receive pin <NUM>, a second receive pin <NUM>, a receiver <NUM>, the sense amplifier <NUM>, a latch <NUM>, and a deserializer <NUM>.

In this example, the first chip <NUM> and the second chip <NUM> are coupled via a differential serial link including a first line <NUM> and a second line <NUM>. The first line <NUM> is coupled between the first output pin <NUM> and the first receive pin <NUM>, and the second line <NUM> is coupled between the second output pin <NUM> and the second receive pin <NUM>. Each line <NUM> and <NUM> may be implemented with a metal line on a substrate (e.g., a printed circuit board), a wire, etc..

On the first chip <NUM>, the serializer <NUM> is configured to receive parallel data streams (e.g., from a processor on the first chip <NUM>) and convert the parallel data streams into a serial data stream, which is output at an output <NUM> of the serializer <NUM>. The driver <NUM> has an input <NUM> coupled to the output <NUM> of the serializer <NUM>, a first output <NUM> coupled to the first output pin <NUM>, and a second output <NUM> coupled to the second output pin <NUM>. The driver <NUM> is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive the lines <NUM> and <NUM> of the differential seral link with the differential data signal to transmit the differential signal to the second chip <NUM>. It is to be appreciated that the first chip <NUM> may include additional components not shown in <FIG> (e.g., impedance matching network coupled to the output pins <NUM> and <NUM>, a pre-driver coupled between the serializer <NUM> and the driver <NUM>, etc.).

On the second chip <NUM>, the receiver <NUM> has a first input <NUM> coupled to the first receive pin <NUM>, a second input <NUM> coupled to the second receive pin <NUM>, a first output <NUM> coupled to the first input <NUM> of the sense amplifier <NUM>, and a second output <NUM> coupled to the second input <NUM> of the sense amplifier <NUM>. The receiver <NUM> may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip <NUM> and the second chip <NUM>). The sense amplifier <NUM> receives the differential signal from the receiver <NUM> and makes bit decisions based on the differential signal, as discussed above.

In the example in <FIG>, the first output <NUM> of the sense amplifier <NUM> is coupled to a first input <NUM> of the latch <NUM>, and the second output <NUM> of the sense amplifier <NUM> is coupled to a second input <NUM> of the latch <NUM>. The latch <NUM> has an output <NUM> coupled to an input <NUM> of the deserializer <NUM>. The latch <NUM> is configured to latch bit decisions from the sense amplifier <NUM> and output the corresponding bits to the deserializer <NUM>. The deserializer <NUM> is configured to convert the bits into parallel data streams, which may be output to one or more components (not shown) on the second chip <NUM> for further processing. It is to be appreciated that the second chip <NUM> may include additional components not shown in <FIG> (e.g., impedance matching network coupled to the receive pins <NUM> and <NUM>, a clock recovery circuit, etc.).

In the example in <FIG>, the second chip <NUM> also includes a timing signal circuit <NUM> configured to generate the timing signal (e.g., clock signal CLK) for the sense amplifier <NUM> and output the timing signal at output <NUM>. The output <NUM> may be coupled to the control inputs of the switches <NUM>, <NUM> and <NUM> in the input circuit <NUM> and the control inputs of the switches <NUM> and <NUM> in the regeneration circuit <NUM> of the sense amplifier <NUM>.

In certain aspects, the timing signal circuit <NUM> may recover the timing signal (e.g., clock signal CLK) based on the bit decisions of the sense amplifier <NUM> using clock data recovery. The input <NUM> of the timing signal circuit <NUM> may be coupled to the output of the latch <NUM> (shown in the example in <FIG>) or may be coupled to one or both outputs <NUM> and <NUM> of the sense amplifier <NUM> to receive the bit decisions.

In certain aspects, the timing signal circuit <NUM> may include a clock generator which may include a phase locked loop (PLL), a delay locked loop (DLL), an oscillator, or any combination thereof to generate the timing signal (e.g., clock signal CLK). It is to be appreciated that the timing signal circuit <NUM> may be implemented using various types of clock generators.

In the example in <FIG>, the first input <NUM> of the latch <NUM> is coupled to the first output <NUM> and hence the drain of the second input transistor <NUM>, and the second input <NUM> of the latch <NUM> is coupled to the second output <NUM> and hence the drain of the first input transistor <NUM>. However, it is to be appreciated that the present disclosure is not limited to this example. In another example, the first input <NUM> of the latch <NUM> may be coupled to the output <NUM> of the second inverting circuit <NUM>, and the second input <NUM> of the latch <NUM> may be coupled to the output <NUM> of the first inverting circuit <NUM>.

<FIG> illustrates a method <NUM> of operating a regeneration circuit of a sense amplifier according to certain aspects. The regeneration circuit (e.g., regeneration circuit <NUM>) includes a first inverting circuit (e.g., first inverting circuit <NUM>) having an input (e.g., input <NUM>) and an output (e.g., output <NUM>), a second inverting circuit (e.g., second inverting circuit <NUM>) having an input (e.g., input <NUM>) and an output (e.g., output <NUM>), a first transistor (e.g., first input transistor <NUM>) coupled to the input of the second inverting circuit, and a second transistor (e.g., second input transistor <NUM>) coupled to the input of the first inverting circuit.

At block <NUM>, in a reset phase, the output of the first inverting circuit is decoupled from the first transistor. For example, the output of the first inverting circuit may be decoupled from the first transistor by turning off the first switch <NUM>.

At block <NUM>, in the reset phase, the output of the second inverting circuit is decoupled from the second transistor. For example, the output of the second inverting circuit may be decoupled from the second transistor by turning off the second switch <NUM>.

At block <NUM>, in a sensing phase, the output of the first inverting circuit is coupled to the first transistor. For example, the output of the first inverting circuit may be coupled to the first transistor by turning on the first switch <NUM>.

At block <NUM>, in the sensing phase, the output of the second inverting circuit is coupled to the second transistor. For example, the output of the second inverting circuit may be coupled to the second transistor by turning on the second switch <NUM>.

In certain aspects, the method <NUM> may also include driving a gate of the first transistor with a first input signal (e.g., voltage NDINT) and driving a gate of the second transistor with a second input signal (e.g., voltage DINT). The first input signal and the second input signal may be generated by the input circuit <NUM> based on a data signal (e.g., a differential data signal) input to the input circuit <NUM>.

In certain aspects, in the reset phase, the first input signal is above a threshold voltage of the first transistor, and the second input signal is above a threshold voltage of the second transistor. In one example, the threshold voltage of the first transistor may be approximately the same as the threshold voltage of the second transistor.

In certain aspects, in the sensing phase, the first input signal is above the threshold voltage of the first transistor, and the second input signal is above the threshold voltage of the second transistor. In certain aspects, in the sensing phase, the first input signal (e.g., voltage NDINT) falls (i.e., decreases) at a first rate and the second input signal (e.g., voltage DINT) falls (i.e., decreases) at a second rate, wherein the first rate and the second rate are different (e.g., based on the polarity of the data signal input to the input circuit <NUM>).

The method <NUM> may also include transitioning from the sensing phase to a decision phase when the first input signal falls below the threshold voltage of the first transistor or the second input signal falls below the threshold voltage of the second transistor. The method <NUM> may also include, in the decision phase, resolving a bit value based on the first input signal and the second input signal. For example, resolving the bit value may include resolving to a first bit value if the first input signal falls below the threshold voltage of the first transistor before the second input signal falls below the threshold voltage of the second transistor, and resolving to a second bit value if the second input signal falls below the threshold voltage of the second transistor before the first input signal falls below the threshold voltage of the first transistor. The first bit value may be a one and the second bit value may be a zero, or vice versa. In certain aspects, in the decision phase, the output of the first inverting circuit is coupled to the first transistor and the output of the second inverting circuit is coupled to the second transistor, which cross couples the first inverting circuit and the second inverting circuit. This is because the first transistor is coupled to the input of the second inverting circuit and the second transistor is coupled to the input of the first inverting circuit. The cross coupling of the first inverting circuit and the second inverting circuit provides regenerative feedback, which facilitates resolving the bit value.

It is to be appreciated that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, the input circuit <NUM> may also be referred to as a sensing circuit or another term. The regeneration circuit <NUM> may also be referred to as a decision circuit, a cross-coupled latch, or another term. An inverting circuit may also be referred to as an inverter, or another term. A logic state may also be referred to as a logic level, a logic value, or another term.

Any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

The term "approximately", as used herein with respect to a stated value or a property, is intended to indicate being within <NUM>% of the stated value or property.

Claim 1:
A regeneration circuit (<NUM>) for a sense amplifier, comprising:
a first inverting circuit (<NUM>) having an input (<NUM>) and an output (<NUM>);
a second inverting circuit (<NUM>) having an input (<NUM>) and an output (<NUM>);
a first transistor (<NUM>) coupled to the input of the second inverting circuit via a first node (<NUM>), wherein a gate (<NUM>) of the first transistor is configured to receive a first input signal (NDINT);
a second transistor (<NUM>) coupled to the input of the first inverting circuit via a second node (<NUM>), wherein a gate (<NUM>) of the second transistor is configured to receive a second input signal (DINT);
a first switch (<NUM>) coupled between the first transistor via the first node and the output of the first inverting circuit, wherein a control input (<NUM>) of the first switch is configured to receive a timing signal (CLK), and the first switch is configured to decouple the output of the first inverting circuit from the input of the second inverting circuit when the timing signal turns off the first switch;
a second switch (<NUM>) coupled between the second transistor via the second node and the output of the second inverting circuit, wherein a control input (<NUM>) of the second switch is configured to receive the timing signal, and the second switch is configured to decouple the output of the second inverting circuit from the input of the first inverting circuit when the timing signal turns off the second switch.