Patent Description:
A system on-chip (SoC) includes a plurality of subsystems implemented in a single integrated circuit. In some cases, one subsystem of the SoC is configured to provide data to another subsystem of the SoC. It can be difficult to manage such communication efficiently.

<FIG> illustrates an example of an integrated circuit <NUM>. The integrated circuit <NUM> is an SoC. The integrated circuit <NUM> includes a first subsystem <NUM> and a second subsystem <NUM>. The first subsystem <NUM> is configured to output data to the second subsystem <NUM>. The first subsystem <NUM> operates on a first clock signal CLK1. The second subsystem <NUM> operates on a second clock signal CLK2. The first and second clock signals are mesochronous. Mesochronous clock signals have a same frequency and a constant, unknown, phase difference.

There are various complications that affect the timing of communication between the first and second subsystems <NUM> and <NUM>. For example, there may be certain delays in processing and transmitting data from the first subsystem102 and certain other delays in processing and receiving data in the second subsystem <NUM>. Additionally, the first and second clock signal have a same frequency and are out of phase with each other to an unknown degree. These factors make it difficult to reliably transmit data from the first subsystem <NUM> in accordance with the first clock signal CLK1 and to receive data at the second subsystem on a desired cycle of the second clock signal. If this is not managed properly, then there can be delays and even failures in data reception by the second subsystem <NUM>.

One possible solution to ensure safe transmission of data from the first subsystem <NUM> to the second subsystem <NUM> is to couple a first-in first-out (FIFO) buffer <NUM> between the first and second subsystems <NUM> and <NUM>. The FIFO buffer <NUM> receives the first clock signal CLK1 from the first subsystem <NUM> and the second clock signal CLK2 from the second subsystem <NUM>. The FIFO buffer <NUM> utilizes the first clock signal CLK1 to manage reception of data from the first subsystem <NUM>. The FIFO <NUM> utilizes the second clock signal CLK2 to manage outputting data to the second subsystem <NUM>.

While this solution ensures safe transmission of data between the first subsystem <NUM> and the second subsystem <NUM>, there are some drawbacks. For example, the FIFO <NUM> consumes a relatively large amount of area on the integrated circuit. Furthermore, the FIFO <NUM> consumes a significant amount of power.

All of the subject matter discussed in the Background section is not necessarily prior art and should not be assumed to be prior art merely as a result of its discussion in the Background section. Along these lines, any recognition of problems in the prior art discussed in the Background section or associated with such subject matter should not be treated as prior art unless expressly stated to be prior art. Instead, the discussion of any subject matter in the Background section should be treated as part of the inventor's approach to the particular problem, which, in and of itself, may also be inventive.

<CIT> discloses a method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. <CIT> Al discloses a method and a system for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. <CIT> Al discloses a system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain.

Embodiments of the present invention provide a system on-chip with subsystems that can communicate with each other without intervening circuits, aside from signal lines, conductive plugs, and other passive electrical connectors. This is accomplished by detecting a phase of a clock signal of a receiving subsystem and generating a clock signal for a transmitting subsystem based on the phase of the clock signal of the receiving subsystem. The phase of the transmitting clock signal relative to the receiving clock signal is selected to ensure that the receiving subsystem can properly process data from the transmitting subsystem within a desired cycle of the receiving clock signal.

Embodiments of the present disclosure help ensure that data can be transmitted from the receiving subsystem to the transmitting subsystem without dropping clock cycles at the receiving subsystem. Because the phase of the transmitting subsystem is known and controlled relative to the phase of the receiving clock signal, interfacial circuitry between the transmitting and receiving subsystems, such as a FIFO, can be eliminated. The result is effective and efficient communication between two subsystems with low hardware overhead.

In one embodiment, a method according to claim <NUM> is provided.

In one embodiment, an integrated circuit according to claim <NUM> is provided.

Reference will now be made by way of example only to the accompanying drawings. In the drawings, identical reference numbers identify similar elements or acts. In some drawings, however, different reference numbers may be used to indicate the same or similar elements. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be enlarged and positioned to improve drawing legibility.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuitry associated with integrated circuits have not been shown or described in detail, to avoid unnecessarily obscuring descriptions of the embodiments.

Unless the context requires otherwise, throughout the specification and claims which follow, the word "comprise" and variations thereof, such as, "comprises" and "comprising" are to be construed in an open, inclusive sense, that is as "including, but not limited to. " Further, the terms "first," "second," and similar indicators of sequence are to be construed as interchangeable unless the context clearly dictates otherwise.

As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its broadest sense, that is as meaning "and/or" unless the content clearly dictates otherwise.

<FIG> is a schematic diagram of an integrated circuit <NUM>, according to one embodiment. The integrated circuit <NUM> includes a first subsystem <NUM> and a second subsystem <NUM>. The first subsystem <NUM> transmits data to the second subsystem <NUM>. As will be set forth in more detail below, the first subsystem <NUM> determines a phase of a receiving clock signal of a second subsystem and generates a transmitting clock signal of the first subsystem <NUM> with a selected phase relative to the phase of the transmitting clock signal.

The integrated circuit <NUM> is a system-on-a-chip (SoC). Accordingly, the integrated circuit <NUM> can include various subsystems such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), microprocessors, memory, memory controllers, bus controllers, digital signal processors, low-voltage differential signaling (LVDS), wireless receivers, wireless transmitters, and other types of subsystems. Some of the subsystems provide data to other subsystems. Embodiments of the present invention help ensure that data can be transmitted effectively and efficiently from one subsystem to another. While <FIG> illustrates only a first subsystem <NUM> and a second subsystem <NUM>, in practice, the integrated circuit <NUM> may include a large number of subsystems such as those described above, or others.

The first subsystem <NUM> includes a first clock generator <NUM>. The first clock generator <NUM> generates a first clock signal CLK1. The first clock signal CLK1 can correspond to a transmitting clock signal. The first clock generator <NUM> receives a global clock signal of the integrated circuit <NUM>. The first clock generator <NUM> may generate the first clock signal CLK1 based, at least in part, on the global clock signal CLKS.

The first clock generator <NUM> may include one or more frequency dividers, phase locked loops, or other circuitry that can be utilized to generate the first clock signal CLK1 based on the global clock signal CLKS. Alternatively, or additionally, the first clock generator <NUM> can include one or more voltage control oscillators, current control oscillators, ring oscillators, or other types of oscillators that can generate a clock signal. The first clock signal CLK1 has a lower frequency than the global clock signal CLKS. For example, the global clock signal CLKS has a frequency at least four times as large as the first clock signal CLK1.

The first clock signal CLK1 may be the clock signal on which the basic functions of the first subsystem <NUM> are performed. The block diagram of <FIG> only illustrates aspects of the first subsystem that are related to transmission of data to the second subsystem <NUM>. In practice, the first subsystem <NUM> includes other circuitry associated with a primary function of the first subsystem. In an example in which the first subsystem <NUM> is an ADC, the first subsystem <NUM> would include circuitry that converts analog signals to digital signals under control of the first clock signal. For simplicity, such circuitry is not shown in <FIG>. In practice, the clock generator <NUM> may generate a plurality of clock signals to be utilized by various components of the first subsystem <NUM> not illustrated herein.

The second subsystem <NUM> includes a second clock generator <NUM>. The second clock signal CLK2 can correspond to a receiving clock signal. The second clock generator <NUM> receives the global clock signal of the integrated circuit <NUM>. The second clock generator <NUM> may generate the second clock signal CLK2 based, at least in part, on the global clock signal CLKS.

The second clock generator <NUM> may include one or more frequency dividers, phase locked loops, or other circuitry that can be utilized to generate the second clock signal CLK2 based on the global clock signal CLKS. Alternatively, or additionally, the second clock generator <NUM> can include one or more voltage control oscillators, current control oscillators, ring oscillators, or other types of oscillators that can generate a clock signal. The second clock signal CLK2 has a lower frequency than the global clock signal CLKS. For example, the global clock signal CLKS has a frequency at least four times as large as the second clock signal CLK2.

The second clock signal CLK2 may be the clock signal on which the basic functions of the second subsystem <NUM> are performed. The block diagram of <FIG> only illustrates aspects of the second subsystem that are related to receiving of data from the first subsystem <NUM>. In practice, the second subsystem <NUM> includes other circuitry associated with a primary function of the second subsystem <NUM>. In practice, the clock generator <NUM> may generate a plurality of clock signals to be utilized by various components of the second subsystem <NUM> not illustrated herein.

In one embodiment, the first clock signal CLK1 and the second clock signal CLK2 have the same frequency. However, the first and second clock signals CLK1 and CLK2 are out of phase with each other. Initially, the phase difference between the first clock signal CLK1 and the second clock signal CLK2 may be unknown. Accordingly, the first clock signal CLK1 and the second clock signal CLK2 are mesochronous because they have a same frequency and constant phase difference. The magnitude of the phase difference affects how data is transmitted from the first subsystem <NUM> and received by the second subsystem <NUM>. If no action is taken based on the phase difference, then it is possible that clock cycles will be wasted between transmitting and receiving data due to delays associated with transmitting and receiving data. Furthermore, data received may be corrupted. As will be set forth in more detail below, the first subsystem <NUM> detects the phase of the second clock signal CLK2 and adjusts or generates the first clock signal CLK1 with a phase selected based on the phase of the second clock signal CLK2.

The first subsystem includes an edge detector <NUM>. The first subsystem <NUM> receives the second clock signal CLK2 from the second subsystem <NUM>. The second clock signal CLK2 is provided to the edge detector <NUM>. The edge detector <NUM> detects an edge of the second clock signal CLK2. In one embodiment, the edge detector <NUM> detects the first rising edge of the second clock signal CLK2. Alternatively, the edge detector <NUM> can detect the first falling edge of the second clock signal CLK2, or both the first rising edge and the first falling edge of the second clock signal CLK2.

The edge detector <NUM> also receives the global clock signal CLKS. The edge detector <NUM> detects the edge of the second clock signal CLK2 based, in part, on the global clock signal CLKS. The edge detector <NUM> outputs a signal EDGE indicating that the first edge of the second clock signal CLK2 has been detected. The edge detector <NUM> passes the signal EDGE to the clock generator <NUM>.

The clock generator <NUM> receives the signal EDGE from the edge detector <NUM>. The signal EDGE indicates the timing of the first edge of the second clock signal CLK2. The edge of the second clock signal CLK2 indicates the phase of the second clock signal CLK2.

The clock generator <NUM> generates the first clock signal CLK1 with a selected phase relative to the second clock signal CLK2. The phase of the first clock signal CLK1 relative to the second clock signal CLK2 is selected to ensure that the second subsystem <NUM> can receive data transmitted from the first subsystem <NUM> to the second subsystem <NUM> without losing any clock cycles or corrupting the data.

In one embodiment, the global clock signal CLKS has a much higher frequency than the first and second clock signal CLK1 and CLK2. The clock generator <NUM> generates the first clock signal CLK1 by dividing the frequency of the global clock signal with a frequency divider. The second clock generator <NUM> generates the second clock signal CLK2 by dividing the frequency of the global clock signal with a frequency divider having a same division ratio as the frequency divider utilized by the clock generator <NUM> to generate the clock signal CLK1.

After the clock generator <NUM> receives the signal EDGE, the clock generator <NUM> generates the clock signal CLK1 by waiting a selected number of clock cycles of the much higher frequency global clock signal CLKS before generating the rising edge of the first clock signal CLK1. In one example, it is desirable for the first clock signal CLK1 to have a rising edge that occurs half a clock cycle after the rising edge of the second clock signal CLK2. In an example in which the frequency of the global clock cycle CLKS is <NUM> times higher than the frequency of the first and second clock signals CLK1 and CLK2, the clock generator <NUM> may be configured to generate the rising edge of the first clock signal CLK1 two cycles of the global clock signal CLKS after receiving the signal EDGE. In this example, the signal EDGE is known to have a delay of two cycles of the global clock signal CLKS relative to the rising edge of the second clock signal CLK2. Accordingly, the rising edge of CLK1 happens four cycles of the global clock signal CLKS after the rising edge of the second clock signal CLK2. This ensures that there will not be a set up failure at the second subsystem <NUM> when receiving data from the first subsystem <NUM>. Other phase differences and other methods of generating the selected phase difference between the first and second clock signal CLK1 and CLK2 can be utilized without departing from the scope of the present invention.

The first subsystem <NUM> includes data transmission circuitry <NUM>. The data transmission circuitry <NUM> outputs data to the second subsystem <NUM>. In an example in which the first subsystem is an ADC, the data transmission circuitry <NUM> receives the digital data converted from analog signals and provides the digital data to the second subsystem <NUM>.

The data transmission circuitry <NUM> includes a plurality of logic circuits that receive data of the first subsystem <NUM> and output the data to the second subsystem <NUM>. There is delay associated with the logic circuits of the data transmission circuitry <NUM>.

In one example, the data transmission circuitry <NUM> includes flip-flops that each include a clock terminal, a data input terminal, and a data output terminal. The data received at the input terminal will typically be provided to the output terminal upon the next rising edge of the clock signal received at the input terminal. However, there is a setup delay associated with the flip-flop. When data arrives at the input terminal of the flip-flop, there is a small setup time for the data to be fully received by the input terminal. If the rising edge of the clock signal occurs after data has arrived at the input terminal, but before the set up time has elapsed, then that data will not be passed to the output terminal of the flip-flop until the next rising edge of the clock signal. Accordingly, the setup time associated with the data input terminal is a source of signal transmission delay. Furthermore, there is an additional delay associated with passing data from the input terminal to the output terminal after the rising edge of the clock signal.

The second subsystem <NUM> includes data receiving circuitry <NUM>. The data receiving circuitry <NUM> receives data from the data transmission circuitry <NUM> of the first subsystem <NUM>. The data receiving circuitry <NUM> also includes logic circuits that receive and process the data from the data transmission circuitry <NUM> of the first subsystem <NUM>. There are delays associated with the logic circuits of the data receiving circuitry <NUM>.

In one example, the logic circuits of the data receiving circuitry <NUM> include a plurality of flip-flops. As described previously in relation to flip-flops of the data transmission circuitry <NUM>, there are delays associated with receiving data at input terminals of the flip-flops of the data receiving circuitry. In particular, the setup delay described previously is also a factor in the flip-flops of the data transmission circuitry <NUM>. If the rising edge of the second clock signal is received at the clock terminal of the flip-flop after data arrives at the input terminal of the flip-flop but before the set up time associated with the data input terminal has elapsed, then the data value will not be passed to the flip-flop until the next rising edge of the clock signal. Accordingly, an entire clock signal can be lost if the clock signals that control the flip-flops of both the data transmission circuitry <NUM> and the data receiving circuitry <NUM> are not carefully managed.

Returning to the data transmission circuitry, <NUM> of the first subsystem <NUM>, data is provided to the data transmission circuitry <NUM> in accordance with the first clock signal CLK1. Digital data is passed to the data transmission circuitry <NUM> in accordance with the first clock signal. This means that data will arrive at the input terminals of the flip-flops of the data transmission circuitry <NUM> in accordance with the rising edge of the first clock signal.

However, the clock signal that is provided to the flip-flops of the data receiving circuitry <NUM> is the second clock signal CLK2. Thus, data arrives at the input terminals of the flip-flops of the data receiving circuitry <NUM> based on the rising edge of the first clock signal CLK1, but data is passed from the input terminals of the flip-flops of the data receiving circuitry <NUM> to the output terminals of the flip-flops based on the second clock signal CLK2. Due to the delays associated with the data transmission circuitry <NUM> and the data receiving circuitry <NUM> as described above, if the rising edge of the second clock signal CLK2 occurs too close to the rising edge of the first clock signal CLK1, the data will not be received and processed at the data receiving circuitry <NUM> within the same cycle of the second clock signal CLK2, assuming that the flip-flops of the data receiving circuitry <NUM> are managed by the rising edge of the second clock signal.

Advantageously, the first subsystem <NUM> generates the first clock signal CLK1 with a known phase difference relative to the second clock signal CLK2 as described above. In particular, the edge detector <NUM> detects the rising edge of the second clock signal CLK2 and generates the signal EDGE. The clock generator <NUM> receives the signal EDGE and generates the edge of the first clock signal CLK1 with a selected phase difference relative to the second clock signal CLK2 based on the signal EDGE and the known delay between the signal EDGE and the edge of the second clock signal CLK2. The phase difference of the first clock signal CLK1 relative to the second clock signal CLK2 is selected to ensure that there is no set up failure at the data receiving circuitry <NUM> when data arrives at the input terminals of the data receiving circuitry <NUM>.

<FIG> is a timing diagram illustrating the global clock signal CLKS, the second clock signal CLK2, and the first clock signal CLK1. In <FIG>, the first and second clock signal CLK1 and CLK2 have a same frequency. The global clock signal CLKS has a frequency that is much higher than the frequency of the first and second clock signal CLK1 and CLK2.

In one example, the edge detector <NUM> of the first subsystem <NUM> receives the second clock signal CLK2 and detects the rising edge of the second clock signal CLK2. The edge detector <NUM> generates the signal EDGE indicating the timing of the rising edge of the second clock signal CLK2. Due to the inherent delays in the edge detector <NUM>, EDGE may go high one or two cycles of the global clock signal CLKS after the rising edge of the edge detector <NUM>. The clock generator <NUM> takes into account this known delay associated with the signal EDGE. The clock generator <NUM> counts an additional number of cycles of the global clock signal CLKS and then generates the rising edge of the first clock signal CLK1. In the example of <FIG>, the rising edge of the clock signal CLK1 occurs half a clock cycle after the rising edge of the second clock signal CLK2. This may ensure that there are no setup failures at the data receiving circuitry <NUM> of the second subsystem <NUM>.

In one embodiment, may be beneficial to generate the rising edge of the clock signal CLK1 to occur cycles of the global clock signal CLKS after the rising edge of the second clock signal CLK2. This results in the rising edge of the second clock signal CLK2 occurring nearly a half clock cycle after the rising edge of the first clock signal CLK1. This may provide a very large timing window and may ensure that no setup failures will occur at the data receiving circuitry <NUM>. Various other phase differences can be selected based on known characteristics of first and second subsystems <NUM> and <NUM>. Furthermore, other components of the methods can be utilized to ensure the selected phase difference between CLK1 and CLK2 in accordance with principles of the present invention without departing from the scope of the present invention.

<FIG> is a schematic diagram of a first subsystem <NUM> of an integrated circuit, according to one embodiment. The first subsystem <NUM> of <FIG> is one example of a first subsystem <NUM> of <FIG>. The first subsystem <NUM> includes the clock generator <NUM>, the edge detector <NUM>, and the data transmission circuitry <NUM>.

The edge detector includes a plurality of flip-flops <NUM>, <NUM>, <NUM>, and <NUM> all connected in series. In particular, the data output of the flip-flop <NUM> is connected to the data input of the flip-flop <NUM>. The data output of the flip-flop <NUM> is connected to the data input of the flip-flop <NUM>. The data output of the flip-flop <NUM> is connected to the data input of the flip-flop <NUM>. The global clock signal CLKS is provided to the clock input terminals CLK of the flip-flops <NUM>, <NUM>, <NUM>, and <NUM>. The reset terminals R of the flip-flops <NUM>, <NUM>, <NUM>, and <NUM> each receive a reset signal RESET. The data input terminal of the flip-flop <NUM> receives the second clock signal CLK2 from the second subsystem <NUM>. The edge detector <NUM> includes an inverter <NUM> and an AND gate <NUM>. The input of the inverter <NUM> is coupled to the output of the flip-flop <NUM>. The output of the inverter <NUM> is coupled to a first input terminal of the AND gate <NUM>. The output of the flip-flop <NUM> is provided to a second input terminal of the AND gate <NUM>. The edge detector <NUM> includes a flip-flop <NUM>. Reset terminal R of the flip-flop <NUM> receives the reset signal RESET. The clock input terminal CLK of the flip-flop <NUM> receives the output of the AND gate <NUM>. The data input terminal of the flip-flop <NUM> receives a high data value of <NUM>. The output of the flip-flop <NUM> corresponds to the output of the edge detector <NUM>. Accordingly, the output of the flip-flop <NUM> is the signal EDGE.

When the first subsystem <NUM> is to generate a first clock signal CLK1 with a selected phase relative to the second clock signal CLK2, the reset signal RESET gets asserted (high to low), causing the data output terminals of the flip-flops <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> to go low. Reset then gets deasserted (low to high). The data input terminal of the flip-flop <NUM> receives the second clock signal CLK2. The data input terminal of the flip-flop <NUM> receives the rising edge of the clock signal CLK2. The rising edge is provided to the data output terminal of the flip-flop <NUM> at the next rising edge of the much higher frequency global clock signal CLKS. Accordingly, the rising edge of the global clock signal CLK2 is provided to the data input terminal of the flip-flop <NUM> after the first rising edge of the global clock signal CLKS.

After the second rising edge of the global clock signal CLKS, the rising edge of the clock signal CLK2 is passed to the output of the flip-flop <NUM>. The rising edge of the clock signal CLK2 is also passed to the second input of the AND gate <NUM>. At this point, the output of the inverter <NUM> is also high because the output of the flip-flop <NUM> is low upon receiving the reset signal RESET. Accordingly, the output of the AND gate <NUM> goes high when the rising edge of the second clock signal CLK2 is passed to the output of the flip-flop <NUM>. Because the output of the AND gate <NUM> is coupled to the clock input terminal CLK of the flip-flop <NUM>, the output of the flip-flop <NUM> goes high when the output of the AND gate <NUM> goes high. Accordingly, the signal EDGE goes high, indicating the presence of the rising edge of the second clock signal CLK2. In this example, there is a delay of two or three cycles of the global clock signal CLKS between the rising edge of CLK2 and the rising edge of EDGE.

The clock generator <NUM> receives the global clock signal CLKS and the edge signal EDGE. The clock generator <NUM> includes a counter <NUM> and the clock divider <NUM>. The counter <NUM> counts the cycles of the global clock signal CLKS. After the signal EDGE goes high, the clock generator <NUM> delays a selected number of cycles of the global clock signal CLKS before causing the rising edge of the first clock signal CLK1. The number of cycles can be selected to ensure a desired phase difference between the first clock signal CLK1 and the second clock signal CLK2. The clock generator <NUM> can take into account the known delay associated with the edge detector <NUM>. As described previously, the clock generator <NUM> may include a clock divider <NUM>. The clock divider <NUM> generates the clock signal CLK1 by dividing the frequency of the global clock signal CLKS.

The data transmission circuitry <NUM> includes a plurality of flip-flops <NUM>. The flip-flops each include a data input terminal D, a data output terminal Q, and a clock input terminal CLK. The data input terminal D receives data from primary circuitry (not shown) of the subsystem <NUM>. In an example in which the subsystem <NUM> is an analog-to-digital converter, the data input terminals D receive data from the analog-to-digital conversion circuitry.

The clock input terminal CLK of each flip-flop receives the first clock signal CLK1. For each flip-flop <NUM>, whatever data value is present at D will be provided to the output terminal Q when CLK1 goes high, subject to set up delays as described previously. The data output terminals Q are connected to the data input terminals of flip-flops of the data receiving circuitry <NUM> of the second subsystem <NUM>. The clock input terminals of the flip-flops of the data receiving circuitry <NUM> each receive the second clock signal CLK2. Because CLK1 is generated with a selected phase difference relative to the clock signal CLK2, there is sufficient time between the rising edge of the first clock signal CLK1 and the rising edge of the second clock signal CLK2 to ensure that there are no setup errors at the flip-flops of the data receiving circuitry <NUM> of the second subsystem <NUM>.

<FIG> is a schematic diagram of a first subsystem <NUM>, according to one embodiment. The first subsystem <NUM> of <FIG> is substantially similar to the first subsystem <NUM> of <FIG> , except that the subsystem <NUM> of <FIG> includes flip-flops <NUM>. The flip-flops <NUM> may be called shadow flip-flops. The data input terminal D of each flip-flop <NUM> receives data from a data output terminal Q of a corresponding flip-flop <NUM>. The flip-flops <NUM> each receive the second clock signal CLK2 on the clock input terminal CLK.

<FIG> is a schematic diagram of an ADC <NUM>, in accordance with some embodiments. The ADC <NUM> may be one example of a first subsystem <NUM> of <FIG>. The ADC <NUM> includes an edge detector <NUM> and a clock generator <NUM>. The edge detector <NUM> and the clock generator <NUM> may function substantially as described in relation to <FIG>. The clock generator <NUM> includes multiple frequency dividers <NUM>. Accordingly, the clock generator <NUM> generates a plurality of clock signals each having different frequencies.

The ADC <NUM> includes a CIC Filter (CIC) <NUM>, a finite impulse response (FIR) filter <NUM>, a FIR filter <NUM>, a DC filter <NUM>, and data output circuitry <NUM>. The signal path of the ADC flows from the CIC <NUM> to the FIR filter <NUM>, to the FIR filter <NUM>, the DC filter <NUM>, to the data output circuitry <NUM>.

The clock generator generates the first clock signal CLK1 as described previously and provides the first clock signal CLK1 to the DC filter <NUM> and to the data output circuitry <NUM>. The clock generator <NUM> generates the clock signal CLK three and provides the clock signal CLK three to the (CIC) <NUM>. The clock signal CLK three may have the same frequency as the global clock signal CLKS. The clock generator <NUM> generates the clock signal CLK4 and provides the clock signal CLK4 to the FIR filter <NUM>. The clock signal CLK four may have a lower frequency than the clock signal CLK three. The clock generator <NUM> generates the clock signal CLK5 and provides the clock signal CLK5 to the FIR filter <NUM>. The clock signal CLK five may have a lower frequency than the clock signal CLK4 and the higher for the clock signal CLK1. Accordingly, the clock generator <NUM> can generate a plurality of clock signals to provide to various components of the ADC <NUM>. Other configurations of an ADC can be utilized without departing from the scope of the present invention.

<FIG> is a flow diagram of a method <NUM>, according to one embodiment. The method <NUM> can utilize systems, components, and processes described in relation to <FIG>. At <NUM>, the method <NUM> includes generating a first clock signal with a first subsystem of an integrated circuit. At <NUM>, the method <NUM> includes receiving the first clock signal with a second subsystem of the integrated circuit. At <NUM>, the method <NUM> includes detecting, with the second subsystem, an edge of the first clock signal. At <NUM>, the method <NUM> includes generating, with the second subsystem, a second clock signal with a phase relative to the second clock signal based on the edge. At <NUM>, the method <NUM> includes outputting data from the second subsystem to the first subsystem based on the second clock signal.

Claim 1:
A method, comprising:
generating a second clock signal (CLK2) with a second subsystem (<NUM>) of an integrated circuit;
receiving the second clock signal (CLK2) with a first subsystem (<NUM>) of the integrated circuit;
detecting, with the first subsystem (<NUM>), an edge of the second clock signal (CLK2);
generating, with the first subsystem (<NUM>), a first clock signal (CLK1) with a phase relative to the second clock signal based on the detected edge of the second clock signal (CLK2); and
outputting data from the first subsystem (<NUM>) to the second subsystem (<NUM>) based on the first clock signal (CLK1),
the phase of the first clock signal (CLK1) relative to the second clock signal (CLK2) being selected to ensure that the second subsystem (<NUM>) can properly process data from the first subsystem (<NUM>) within a desired cycle of the second clock signal (CLK2).