Patent Description:
According to the invention as defined in the claims, a signal driver circuit, comprising: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.

In an example embodiment, the first subset is a set of un-delayed voltage-modulated amplifiers and the second subset is a set of delayed voltage-modulated amplifiers; and the de-emphasis levels are set based on a ratio of the set of un-delayed voltage-modulated amplifiers to the set of delayed voltage-modulated amplifiers.

In another example embodiment, the de-emphasis levels include a first de-emphasis level and a second de-emphasis level.

In another example embodiment, the de-emphasis controller is configured to switch-on all of the voltage-modulated amplifiers for the first de-emphasis level.

In another example embodiment, a voltage ripple at the output of the signal driver circuit decreases as the switched-on voltage-modulated amplifiers in the second subset increases.

In another example embodiment, a de-emphasis of the input of the signal driver circuit increases as the switched-on voltage-modulated amplifiers in the second subset increases.

In another example embodiment, further comprising a set of de-emphasis dummy loads coupled between the regulated voltage output and a reference potential; and wherein each de-emphasis dummy load in the set of de-emphasis dummy loads is configured to draw a de-emphasis dummy load current from the regulated voltage output of the LDO if the de-emphasis dummy load is switched-on.

In another example embodiment, the set of voltage-modulated amplifiers are configured to draw a first current; the set of de-emphasis dummy loads are configured to draw a second current; and a summation of the first current and the second current is substantially a constant current.

In another example embodiment, the set of de-emphasis dummy loads are coupled to receive the input signal.

In another example embodiment, the de-emphasis controller is configured to switch-off all of the de-emphasis dummy loads for the first de-emphasis level.

In another example embodiment, the de-emphasis controller is configured to switch-on at least one of the de-emphasis dummy loads for the second de-emphasis level.

In another example embodiment, the LDO is a capless LDO.

In another example embodiment, the signal driver circuit is completely embodied in a single integrated circuit.

In another example embodiment, the signal driver circuit is an e-USB transmit signal driver circuit.

In another example embodiment, the input signal is a differential input signal; and the output signal is a differential output signal.

In another example embodiment, further comprising a start-up dummy load coupled between the regulated voltage output and a reference potential; wherein the start-up dummy load is coupled to receive the input signal and configured to draw a start-up dummy load current from the regulated voltage output of the LDO; and wherein the dummy load current equals a first current when the input signal is in a first state and equals a second current when the input signal is in a second state.

In another example embodiment, the dummy load includes a NOR gate, a switch, and a dummy impedance; the output of the signal driver circuit is configured to be coupled to a load termination impedance (R_Term); and the dummy impedance is equal to twice the termination impedance (R_Term).

In another example embodiment, the voltage mode line driver is configured to draw a voltage-mode line driver current; and a summation of the voltage mode line driver current and the start-up dummy load current is substantially a constant current.

The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The Figures and Detailed Description that follow also exemplify various example embodiments.

Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

Minimizing ripple, logic-conversion, signal-interfacing, etc. all refer to ensuring glitch-free electrical compatibility between one or more electrical circuits, modules, or systems. In the discussion herein, circuits are discussed for minimizing ripple in an eUSB or USB high-speed transmit (TX) driver that can cause signal level errors (e.g. bit errors); however, the concepts and examples discussed applied to a wide variety of such signal driver circuits. Just one example application employing such circuits is now presented for Universal Serial Bus (USB) repeaters.

USB (e.g. v2. <NUM>) has been one of the most successful wired interfaces in the past <NUM> years, and almost all SoCs today are equipped with a USB <NUM> interface. USB standards evolution kept the original <NUM>-V I/O USB <NUM> interface intact for backward compatibility, helping enable wider adoption and a larger ecosystem while also preserving device interoperability. However, as process nodes approach more advanced node (e.g. <NUM>), the manufacturing cost to maintain USB <NUM><NUM>. 3V I/O signaling has grown exponentially.

Embedded USB2 (eUSB2) is a supplement specification to the USB <NUM> specification that addresses issues related to interface controller integration with advanced system-on-chip (SoC) process nodes by enabling USB <NUM> interfaces to operate at I/O voltages of 1V or <NUM>. 2V instead of <NUM>. eUSB2 can enable smaller, more power-efficient SoCs, in turn enabling process nodes to continue to scale while increasing performance in applications such as smartphones, tablets and notebooks. In some examples, designers integrate the eUSB2 interface at a device level while leveraging and reusing the USB <NUM> interface at a system level. eUSB2 can support onboard inter-device connectivity through direct connections as well as exposed connector interfaces through an eUSB2-to-USB <NUM> repeater for performing level shifting.

The following Table presents some differences between USB <NUM> and eUSB2:.

<FIG> represents examples <NUM> of two eUSB to USB configurations <NUM>, <NUM> requiring level-shifting.

The first configuration <NUM> includes a system on a chip (SoC) having two eUSB embedded interfaces (as shown). The chip <NUM> is configured to be coupled to an external eUSB device <NUM> and to a legacy USB2 device <NUM>. An eUSB2 repeater <NUM> is necessary to convert a differential eUSB signal (eD+/eD-) to a differential USB signal (D+/D-). The eUSB2 repeater <NUM> in some examples is on a same PC board as the chip <NUM>, while the eUSB <NUM> and USB <NUM> devices are coupled via cabling.

The second configuration <NUM> is substantially similar to the first configuration <NUM>, except now an SoC <NUM> includes two USB2 embedded interfaces (as shown).

<FIG> represents an example bi-directional eUSB repeater <NUM>. This example repeater follows the first configuration <NUM> example in <FIG>, but in another example embodiment could follow the second configuration <NUM> in <FIG>.

The repeater <NUM> includes a transmit datapath <NUM>, a receive datapath <NUM>, an eUSB2 port <NUM>, a datapath switch matrix <NUM>, a USB2 port <NUM>, and a controller <NUM>. The repeater <NUM> is configured to be coupled to differential eUSB signals (eD+/eD-) <NUM> in a low voltage domain, and differential USB signals (D+/D-) <NUM> in a high voltage domain. Power supplies VDD <NUM>. 8V, VDD <NUM> V and a mode control <NUM> signal are also shown.

The transmit and receive datapaths <NUM>, <NUM> are substantially similar and include: a first stage <NUM>, a datapath switch <NUM>, and a transmit (TX) line-driver <NUM>.

The first stage <NUM> includes, equalizer, gain circuits and slicer. The slicer circuit makes a (non-linear) hard decision and makes the data signal either high or low, which avoids propagation of amplitude noise and allows regeneration of pre-emphasis.

The equalizer circuit in various example embodiments is a continuous time linear equalizer (CTLE) (i.e. a feed forward equalizer (FFE)) for removing most intersymbol interference (ISI), due to input and termination resistors (R_Term). R_Term can be different for different standards ( e.g. for an USB2 to an eUSB repeater, input R_Term = 45Ω, output R_Term = 40Ω).

The repeater <NUM> also includes a low drop-out voltage regulator (LDO) <NUM> which provides power to the TX line-driver <NUM>, because USB2 is in <NUM>. 3V domain and while most of the platforms have <NUM>. 8V available, <NUM>. 2V source needs to be generated internally from <NUM>. 8V supply by the LDO <NUM>, and not from the <NUM>. 3V supply for lower power consumption. In case USB2 to eUSB repeater <NUM> shown, the eUSB side will need to use a <NUM>. 8V to <NUM>. 2V LDO <NUM> for low-speed (LS) applications, and a <NUM>. 2V and <NUM>. 4V LDO for high-speed (HS) applications.

Traditional LDOs are coupled to an external capacitor and are simple to design and provide good regulated output, but are area consuming due to the off-chip external capacitor which also needs a dedicated pin from the LDO. Due to the external capacitor, such LDOs will provide a solid <NUM>. 4V output, since the external capacitor holds the required charge to keep the LDO's output voltage stable even while the LDO output current changes significantly. The external capacitor however acts as a fixed load and is thus always current consuming and not preferable (e.g. load current is ~<NUM>. 5mA and IL needs to be ~10mA to do the job, the extra ~10mA current is not preferably in a low-current application.

Capless LDOs <NUM> in contrast are attractive due to their small area and removing need of off-chip capacitor. However, sourcing the mA range signal bit currents needed by the voltage-mode line-driver <NUM> causes a collapse of the capless LDO's <NUM> output voltage due to the capless LDO's 222small/zero value capacitor. Since it will take some time for the capless LDO <NUM> to adjust signal bit changes (i.e. the capless LDO is not fast enough to be ready to deliver a required (<NUM>. 5mA) load ( <NUM>. 4V/4R_Term, R_Term=40Ω) and output voltage swing may be up to 240mV, depending on the LDO design and value of the integrated capacitor), a few signal bits may be corrupted at startup which can violate the USB2/eUSB standard.

Additionally, switching de-emphasis levels (i.e. in the first stage <NUM>) of the USB2/eUSB repeater can result in excessive output voltage ripple due to the capless LDO's <NUM> load current sourcing limitations (i.e. de-emphasis loading changes periodically in nanosecond range and a capless LDO may not be able to track the changing load fast enough which means quality of output signal will drop). This voltage ripple will be seen at output of voltage mode driver and can affect a quality of the line-driver's <NUM> output voltage, especially in high-speed applications.

As power efficiency becomes increasingly critical in computing devices, there is a need for IO technology to be optimized for startup, active and idle power scenarios. <NUM> technology, originally optimized for external device interconnect, is primed to be enhanced for inter-chip interconnect such that the link power can be further optimized.

<FIG> represents another example <NUM> of the datapath <NUM> (e.g. the USB2 to eUSB signal conversion) in the repeater <NUM>.

<FIG> represents an example <NUM> of the LDO <NUM> and the line-driver <NUM> in the repeater <NUM>. In this example <NUM>, a capless LDO <NUM> (i.e. no external capacitor) is coupled to a voltage-mode line driver <NUM>, which is itself coupled to a communications channel <NUM> that is coupled to a receiving device <NUM>, as shown.

As background, current-mode drivers use Norton-equivalent parallel terminations, which makes controlling output impedance for signal integrity considerations (e.g. min. reflections) rather straightforward. In contrast, voltage-mode drivers use Thevenin-equivalent series termination, which uses potentially ½ to ¼ of the current as a current-mode driver for a given output voltage swing. Thus an ideal voltage-mode driver is not only able to interface signals with a differential receiver (RX) termination, but can do so with a potential 4x reduction in TX driver power. Voltage-mode driver implementation depends on a TX driver's output swing requirements, and can be configured as either Low-Swing or High-Swing. For a low-swing application (<<NUM>-500mVpp) an all NMOS driver may be used, while for high-swing applications CMOS driver may be used.

The capless LDO <NUM> is designed on-chip to reduce a cost of the device, and therefore, the LDO <NUM> is very low speed with gain-bandwidth at the level of <NUM> or even lower also in order to reduce power consumption. When the voltage-mode line driver <NUM> is disabled, both ip and im are low and the MOS switches in the transmitter are off and the transmitter draws no current from the LDO <NUM>.

During the startup, either the differential input signals ip or im toggle from low to high and S1 and S2, or S3 and S4 are enabled and the transmitter starts to draw a high current from the LDO <NUM>.

The current can be calculated as I_transmitter= V_LDO/(<NUM>*R_Term). The resistance of these switches, S1,S2,S3 and S4, is not included in this calculation for simplicity. The current can be very high, for example, V_LDO =<NUM>. 4V, R_Term=<NUM> Ohms, then the current I_LDO = <NUM>. Since the transmitter is designed to be very high speed to transmit high-speed signal with <NUM> UI equal to 2nS or even less, the transition of current drawn from the LDO <NUM> from 0mA to <NUM>. 5mA can be as fast as 1nS or even faster. This causes a voltage ripple on the LDO output during transmitter startup because of the on-chip low speed LDO results in the output of the LDO <NUM> V_LDO experiencing a very large voltage drop.

<FIG> represents an example timing diagram <NUM> for the capless LDO <NUM> supplied line-driver <NUM>. The example timing diagram <NUM> shows I_LDO <NUM> and V_LDO <NUM> output by the capless LDO <NUM>, as well as differential input signals (Im <NUM> and Ip <NUM>) received by the voltage-mode line driver <NUM> and one differential output signal <NUM> (tx_dr_out) generated by the voltage-mode line driver <NUM>. A second differential output signal from the voltage-mode line driver <NUM> is similarly affected.

Corrupted bits <NUM> from the voltage-mode line driver <NUM> due to the very large voltage drop (see V_LDO waveform) of the LDO <NUM> at startup are also shown. While in some applications corruption of the first bit is allowed, corruption of multiple bits is not typically allowed.

Now discussed are circuits that when added to a capless LDO in a voltage-modulated high-speed TX driver, for example, reduce bit corruption and voltage ripple both at start-up and while in continuous operation. While these circuits are discussed in an eUSB application (e.g. 480Mbps/<NUM>), they are equally applicable to any voltage mode line-driver. These circuits can be used with any capless LDO having a fast changing load. With these circuits, there is no need for an external capacitor (e.g. CLDO) and an extra pin to connect thereto.

While these circuits are good for any eUSB2. <NUM> transmitter/repeater which is in <NUM>. 2V domain while chip supply is in higher voltage domain, they are also applicable to any application which needs a fast changing current.

<FIG> represents a first example <NUM> a signal driver circuit <NUM>. The example <NUM> includes a capless LDO <NUM>, a start-up dummy load <NUM>, and a voltage mode line driver <NUM>. The signal driver circuit is coupled to a communications channel <NUM> that is itself coupled to a receiving device <NUM>. The receiving device <NUM> has a differential termination impedance of <NUM>*R_Term.

The start-up dummy load <NUM> is configured to receive differential input signals (Im and Ip) which are also received by the voltage mode line driver <NUM> as shown. The start-up dummy load <NUM> is coupled between the LDO's <NUM> regulated voltage output (V_LDO) and a reference potential <NUM>.

Generally, the start-up dummy load <NUM> is coupled to receive the differential input signals and draw a first current (first start-up dummy load current (I_dummy)) from the regulated voltage output of the LDO <NUM> when the input signal is in a first state (e.g. no input signal) and draw a second current (second start-up dummy load current (I_dummy)) from the regulated voltage output of the LDO <NUM> when the input signal is in a second state (e.g. either one of Ip or Im asserted in this example embodiment).

The start-up dummy load <NUM> includes a NOR gate, a switch (S5) and an impedance (<NUM>*R_Term). The total load current of the I_LDO = I_dummy + I_transmitter, where I_transmitter is drawn by the voltage mode line driver <NUM>. The start-up dummy load <NUM> impedance is equal to twice the receiving device <NUM> termination impedance (i.e. <NUM>*<NUM>*R_Term = <NUM>*R_Term).

After the signal driver circuit <NUM> warms up, but before differential input signal transmission has started, both ip and im are at a logic "low", and the output of the NOR gate is at a logic "high". Therefore, switch S5 is on, and the drawn start-up dummy current I_dummy from LDO = V_LDO/(<NUM>*R_Term). And the transmitter current I_transmitter = 0mA as described earlier. Therefore, LDO = I_dummy + I_transmitter = V_LDO/(<NUM>*R_Term) + <NUM> = V_LDO/(<NUM>*R_Term).

After differential input signal transmission has started, either ip or im toggles from low to high and S1 and S2 or S3 and S4 are periodically enabled and the voltage mode line driver <NUM> starts to draw a of I_transmitter = V_LDO/(<NUM>*R_Term). Also during the transient of startup, the output of the NOR gate toggles to logic "low", and S5 is turned off. And I_dummy =0mA. Therefore, LDO = I_dummy + I_transmitter = 0mA + V LDO/(<NUM>*R_Term)= V_LDO/(<NUM>*R_Term).

Thus the total LDO <NUM> load current (I_LDO) is substantially un-changed at V_LDO/(<NUM>*R_Term), thereby minimizing any ripple voltage at the LDO's <NUM> output. In other words a summation of the voltage mode line driver <NUM> current (I_transmitter) and the start-up dummy load <NUM> current (I_dummy) is substantially a constant current thus minimizing bit corruption at start-up.

<FIG> represents an example timing diagram <NUM> for the first example <NUM> the signal driver circuit <NUM>. The example timing diagram <NUM> shows: I_LDO <NUM>, V_LDO <NUM>, differential input signals (Im <NUM> and Ip <NUM>), one differential output signal <NUM> (tx_dr_out), start-up dummy load current (I_dummy) <NUM>, voltage-mode line driver current (I_transmitter) <NUM>, and an enable dummy circuit signal (En_dummy) <NUM>.

Thus using the first example <NUM> the signal driver circuit <NUM> the differential input signals (Im <NUM> and Ip <NUM>) are, at the output of the voltage-mode line driver <NUM>, clean bits <NUM> and not corrupted.

Now discussed are circuits for reducing output voltage ripple due to a capless LDO's load current sourcing limitations while switching de-emphasis levels as introduced above. De-emphasis (DE) loading can change within nano-seconds and a capless LDO may not be able to track the changing load fast enough which means quality of output signal will drop. The circuits now discussed maintain output signal quality even as a de-emphasis level is switched.

<FIG> represents a circuit <NUM> with a signal driver circuit <NUM> according to the invention as defined in the claims. The circuit <NUM> shows a signal driver circuit <NUM> coupled to receive differential input signals (Im and Ip), amplify those signals and generate differential output signals (om and op) which are then transmitted over a differential communications channel to a receiving device <NUM> having R_Term termination impedances.

The signal driver circuit <NUM> includes a capless LDO <NUM>, a dummy load <NUM>, and a programmable de-emphasis circuit <NUM>. The dummy load <NUM> includes a NOR gate, switch (S0), impedance (<NUM>*R_Term), and draws a first dummy load current (I_dummy_1) when the switch is activated. The dummy load <NUM> receives the differential input signals (Im and Ip) and operates substantially as discussed in <FIG>.

The programmable de-emphasis circuit <NUM> includes a set of un_delayed (N_UD) voltage-mode line driver cells <NUM>, a set of delayed (N_D) voltage-mode line driver cells <NUM>, an emphasis delay <NUM>, a set of buffers, a de-emphasis(DE) level controller <NUM> that generates a DE_1 level select signal <NUM>, and a DE level switch (S1) that sinks a second dummy load current (I_dummy_2). The programmable de-emphasis circuit <NUM> sinks a voltage-mode line driver current (I_transmitter), and also receives the differential input signals (Im and Ip) at various circuit locations as shown. To support different output swing levels, LDO output voltage can be programmable.

The following Table shows an example set of four DE Levels (<NUM>, <NUM>, <NUM>, <NUM>). For each DE Level a prespecified number of delayed voltage-mode driver cells are activated in the set of un_delayed (N_UD) voltage-mode line driver cells <NUM>, and a prespecified number of un_delayed voltage-mode driver cells are activated in the set of delayed (N_D) voltage-mode line driver cells <NUM>.

In <FIG> and the discussion to follow there are only two DE Levels (<NUM> and <NUM>). Level_0 is completely un_delayed and corresponds to the circuit in <FIG>. Level_1 is now discussed.

Refer to <FIG>, de-Emphasis (DE) (dB) = <NUM> * log(Vs / Vd) = <NUM> * log((<NUM> + α) / (<NUM>-α)) , where: a number of un_delayed_cells (N_UD) is normalized to <NUM>, and a number of delay_cells is normalized to α.

<FIG> represents a simplified version <NUM> of a second example <NUM> of the signal driver circuit <NUM>. The simplified version <NUM> shows only one un_delayed (real number will be N_UD) voltage-mode line driver cell (i.e. R_N and S_N) and one delayed (real number will be N_D) voltage-mode line driver cell (i.e. R_N and S_D). Both cells are controlled by the de-emphasis (DE) level controller <NUM>.

<FIG> represents an example timing diagram <NUM> for the second example <NUM> of the signal driver circuit <NUM> and shows how de-emphasis works. As is seen in the TX-output (e.g. differential output signals (om and op)) will have two levels, Vs and Vd where Vs represents DE Level_0 and Vd represents DE Level_1. The emphasis delay <NUM> sets a duration of each de-emphasis level equal to <NUM> UI (unit interval).

An example set of calculations and operating parameters are now discussed. In other example embodiments and/or applications these calculations and operating parameters may be different. RON of switches (S1, S_N, S_D) will be considered zero to simplify the discussion below.

For R_Term = 40Ω (i.e. differential R_Term = 80Ω), ratio of delayed and un_delayed cells is chosen to provide a required de-emphasis level. Considering R_N = <NUM>Ω, NT = <NUM> (see Table), NT = N_UD + N_D, R_Term = <NUM>Ω (eUSB single ended termination resistor), RU = R_Term * NT = 40Ω * <NUM> = 2000Ω, RD = RU / N_D, R_UD = RU / N_UD.

When only un-delayed cells are in place, then: R_Out = R_N / N_UD = R_Term * NT / N_UD and Vout = Vd. When all cells are in place, then R_Out = R_N / N_UD ∥ R_N / N_D = R_N / (N_UD + N_D) ∥ R_N / NT = R_Term, and Vout = Vs.

When only un-delayed cells are in place, then IT = V_LDO / ( R_UD + R_Term) = V_LDO / (RU / N_UD + R_Term). IT when all delayed and un-delayed cells are in place is IT = V_LDO / (R_UD∥RD + R_Term) = V_LDO / (R_Term + R_Term).

When only un-delayed cells are in place, then R_Out will be higher ( >R_Term), means equal impedance is higher, means less LDO current is needed, IT is smaller, swing is smaller (Vd). When all delayed and un-delayed cells are in place, R_Out is smaller (= R_Term), means IT is larger, swing is larger ( Vs).

Difference between two currents will be: Delta (IT) = V_LDO / ( Term + R_Term) - V_LDO / ( Term + Term * NT / N_UD) = (V_LDO / R _Term) / (<NUM> / <NUM>- <NUM> / (<NUM> + NT / N_UD)) = V_LDO / (<NUM> * R_Term * (NT - N_UD / NT + N_UD)) = V_LDO / (<NUM> * R_Term * N_D / (NT + N_UD) = V_LDO / (<NUM> * R_Term * N_D / (N_D + N_UD + N_UD) = V_LDO / (<NUM> * R_Term * N_D / (N_D + <NUM> * N_UD).

This means that when delayed cells are not in place, the extra current should be switched off to ground to have a fix LDO current during all the time that the voltage-mode line driver cells <NUM>, <NUM> are operating.

An equivalent resistor to ground in the I_dummy_2 and S1 path is R_DE (i.e. Req). Req = R_DE = <NUM> * R_Term * N_D / (N_D + <NUM> * N_UD) = <NUM> * R_Term / (<NUM> + <NUM> * N_UD / N_D). The current path with Req will be enabled when the delayed cell is switched off. This will keep the LDO output current constant during the transmission with DE.

A timing of the differential input signals (Im and Ip) to differential output signals (om and op) conversion is set by the im_UD, ip_UD, im_D and ip_D signal from the emphasis delay <NUM> are sent to two XOR gates to detect the delay of ip and in, respectively, and an OR gate to, in conduction with the de-emphasis (DE) level controller <NUM>, enable the second dummy load current (I_dummy_2).

<FIG> represents an example timing diagram <NUM> for the second example <NUM> of the signal driver circuit <NUM> for DE Level-<NUM> (e.g. without the compensation of I_dummy_2). As can be seen a voltage ripple <NUM> on V_LDO is 421mV - 389mV ~32mV which can affect differential output signals (om and op) signal quality.

<FIG> represents an example timing diagram <NUM> for the second example <NUM> of the signal driver circuit <NUM> for DE Level-<NUM> (e.g. with the compensation of I_dummy _2). Here the second dummy load current (I_dummy_2) deemphasis dummy current is selectively added and balances the transmitter current (I_transmitter). As a result a voltage ripple <NUM> on the V_LDO is reduced (i.e. <NUM>. 8mV - <NUM>. 3mV ~<NUM>. 5mV), which is almost ¼ of the Level_0 voltage ripple <NUM>.

<FIG> represents a third example <NUM> a signal driver circuit. In this example <NUM> there are three DE Levels (<NUM>, <NUM> (DE_1) and <NUM> (DE_2)) as shown. Otherwise the operation of the third example <NUM> is substantially a scaled version of the second example <NUM> of the signal driver circuit.

Various instructions and/or operational steps discussed in the above Figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while some example sets of instructions/steps have been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description.

In some example embodiments these instructions/steps are implemented as functional and software instructions. In other embodiments, the instructions can be implemented either using logic gates, application specific chips, firmware, as well as other hardware forms.

When the instructions are embodied as a set of executable instructions in a non-transitory computer-readable or computer-usable media which are effected on a computer or machine programmed with and controlled by said executable instructions. Said instructions are loaded for execution on a processor (such as one or more CPUs). Said processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. Said computer-readable or computer-usable storage medium or media is (are) considered to be part of an article (or article of manufacture). The non-transitory machine or computer-usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and/or other transitory mediums.

Thus, the detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description.

Claim 1:
A signal driver circuit (<NUM>), comprising:
an input configured to receive an input signal (im, ip);
an output configured to transmit an output signal (om, op);
a low drop-out voltage regulator, LDO (<NUM>), having a regulated voltage output (V_LDO);
a set of voltage-modulated amplifiers (<NUM>, <NUM>) having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal;
wherein each voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit;
a de-emphasis controller (<NUM>), including a set of de-emphasis levels;
wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers (<NUM>) and switch-off a second subset of the set of voltage-modulated amplifiers (<NUM>) based on the de-emphasis levels.