Patent Description:
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. <CIT> relates to a spin orbit torque MRAM and manufacture thereof. <CIT> relates to a method for forming storage node contact in semiconductor device using nitride-based hard mask.

According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps as defined by the subject matter of the independent claim.

<FIG> illustrate a method for fabricating a MRAM device according to an embodiment of the present invention.

Referring to <FIG> illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown in <FIG>, a substrate <NUM> made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region <NUM> and a logic region <NUM> are defined on the substrate <NUM>.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer <NUM> could also be formed on top of the substrate <NUM>. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate <NUM>, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer <NUM> could be formed on the substrate <NUM> to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer <NUM> to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, metal interconnect structures <NUM>, <NUM> are sequentially formed on the ILD layer <NUM> on the MRAM region <NUM> and the logic region <NUM> to electrically connect the aforementioned contact plugs, in which the metal interconnect structure <NUM> includes an inter-metal dielectric (IMD) layer <NUM> and metal interconnections <NUM> embedded in the IMD layer <NUM>, and the metal interconnect structure <NUM> includes a stop layer <NUM>, an IMD layer <NUM>, and metal interconnections <NUM> embedded in the stop layer <NUM> and the IMD layer <NUM>.

In this embodiment, each of the metal interconnections <NUM> from the metal interconnect structure <NUM> preferably includes a trench conductor and the metal interconnection <NUM> from the metal interconnect structure <NUM> on the MRAM region <NUM> includes a via conductor. Preferably, each of the metal interconnections <NUM>, <NUM> from the metal interconnect structures <NUM>, <NUM> could be embedded within the IMD layers <NUM>, <NUM> and/or stop layer <NUM> according to a single damascene process or dual damascene process. For instance, each of the metal interconnections <NUM>, <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers <NUM> in the metal interconnections <NUM> are preferably made of copper, the metal layer <NUM> in the metal interconnections <NUM> is made of tungsten, the IMD layers <NUM>, <NUM> are preferably made of silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer <NUM> is preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof.

Next, a bottom electrode <NUM>, a MTJ stack <NUM> or stack structure, a top electrode <NUM>, a spin orbit torque (SOT) layer <NUM>, and a hard mask <NUM> are formed on the metal interconnect structure <NUM>. In this embodiment, the formation of the MTJ stack <NUM> could be accomplished by sequentially depositing a pinned layer, a barrier layer, and a free layer on the bottom electrode <NUM>. In this embodiment, the bottom electrode <NUM> and the top electrode <NUM> are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Alternatively, the pinned layer could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field. Preferably, the first SOT layer <NUM> is serving as a channel for the MRAM device as the first SOT layer <NUM> could include metals such as tantalum (Ta), tungsten (W), platinum (Pt), or hafnium (Hf) and/or topological insulators such as bismuth selenide (BixSe<NUM>-x). The hard mask <NUM> preferably includes conductive material or metals such as ruthenium (Ru), but not limited thereto.

Next, as shown in <FIG>, one or more etching process could be conducted to by using a patterned mask (not shown) as mask to remove part of the hard mask <NUM>, part of the SOT layer <NUM>, part of the top electrode <NUM>, part of the MTJ stack <NUM>, part of the bottom electrode <NUM>, and part of the IMD layer <NUM> to form a MTJ <NUM> on the MRAM region <NUM>, and the patterned mask is removed thereafter. It should be noted that a reactive ion etching (RIE) process or an ion beam etching (IBE) process could be conducted at this stage to remove the top electrode <NUM>, MTJ stack <NUM>, bottom electrode <NUM>, and the IMD layer <NUM> in this embodiment for forming the MTJ <NUM>. Due to the characteristics of the IBE process, the top surface of the remaining IMD layer <NUM> is slightly lower than the top surface of the metal interconnections <NUM> after the IBE process and the top surface of the IMD layer <NUM> also reveals a curve or an arc. It should also be noted that as the IBE process is conducted to remove part of the IMD layer <NUM>, part of the metal interconnection <NUM> could be removed at the same time to form inclined sidewalls on the surface of the metal interconnection <NUM> immediately adjacent to the MTJ <NUM>.

Next, a cap layer <NUM> is formed on the MTJ <NUM> while covering the surface of the IMD layer <NUM> on the MRAM region <NUM> and the logic region <NUM>. In this embodiment, the cap layer <NUM> preferably includes silicon nitride, but could also include other dielectric material including but not limited to for example silicon oxide, silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

Next, as shown in <FIG>, an etching process is conducted without using any patterned mask such as patterned resist to remove part of the cap layer <NUM> for forming a spacer <NUM> around or adjacent to sidewalls of the MTJ <NUM>, the SOT layer <NUM>, and the hard mask <NUM>, in which the spacer <NUM> preferably includes a L-shape in a cross-section view. Next, a deposition process such as an atomic layer deposition (ALD) process is conducted to form an IMD layer <NUM> on the hard mask <NUM>, the spacer <NUM>, and the IMD layer <NUM>, and then a planarizing process such as a chemical mechanical polishing (CMP) or etching back process is conducted to remove part of the IMD layer <NUM> so that the top surface of the remaining IMD layer <NUM> is even with the top surface of the hard mask <NUM>. Next, another hard mask <NUM> is formed on the IMD layer <NUM> to cover the hard mask <NUM> and the spacer <NUM>, in which the hard mask <NUM> is preferably made of metal nitride such as TiN, but not limited thereto.

Next, as shown in <FIG>, a semiconductor layer <NUM> and another hard mask <NUM> is formed on the hard mask <NUM>. Preferably, the semiconductor layer <NUM> includes silicon such as polysilicon or amorphous silicon and the hard mask <NUM> includes a dielectric layer such as silicon nitride, but not limited thereto.

Next, as shown in <FIG>, a patterned mask (not shown) such as a patterned resist is formed on the hard mask <NUM>, an etching process is conducted by using the patterned mask as mask to remove part of the hard mask <NUM> for exposing the top surface of the semiconductor layer <NUM>, and the patterned mask is removed thereafter.

Next, as shown in <FIG>, a dry etching process is conducted by using the patterned hard mask <NUM> as mask to pattern the semiconductor layer <NUM> and stop on the surface of the hard mask <NUM>.

Next, as shown in <FIG>, a wet etching process is conducted by using the hard mask <NUM> again to remove part of the hard mask <NUM> for exposing the top surface of the IMD layer <NUM> as the sidewall of the hard mask <NUM> is aligned with sidewalls of the semiconductor layer <NUM> and hard mask <NUM>. Preferably, the wet etching process conducted at this stage could be accomplished by etchant such as standard clean SC2 for removing the hard mask <NUM>, but not limited thereto.

Next, as shown in <FIG>, a wet etching process is conducted to remove hard mask <NUM> completely and exposing the top surface of the semiconductor layer <NUM>. Preferably, the wet etching process conducted at this stage could be accomplished by using phosphoric acid (H<NUM>PO<NUM>) to completely remove the hard mask <NUM> made of SiN and exposing the surface of the semiconductor layer <NUM>.

Next, as shown in <FIG>, another wet etching process is conducted to remove the semiconductor layer <NUM>, in which the wet etching process could be accomplished by using tetramethyl ammonium hydroxide (TMAH) to completely remove the semiconductor layer <NUM> made of polysilicon and expose the top surface of the hard mask <NUM>.

Next, as shown in <FIG>, another IMD layer <NUM> is formed on the hard mask <NUM> and the IMD layer <NUM>. In this embodiment, each of the IMD layer <NUM> and IMD layer <NUM> preferably includes an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). Next, a planarizing process such as chemical mechanical polishing (CMP) process or etching back process is conducted to remove part of the IMD layer <NUM> while the top surface of the remaining IMD layer <NUM> is still higher than the top surface of the hard mask <NUM>.

Next, a pattern transfer process is conducted by using a patterned mask (not shown) to remove part of the IMD layer <NUM>, part of the IMD layer <NUM>, part of the IMD layer <NUM>, and part of the stop layer <NUM> on the MRAM region <NUM> and logic region <NUM> to form contact holes (not shown) exposing the metal interconnections <NUM> underneath and conductive materials are deposited into the contact hole afterwards. For instance, a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) could be deposited into the contact holes, and a planarizing process such as CMP could be conducted to remove part of the conductive materials including the aforementioned barrier layer and metal layer to form metal interconnections <NUM> in the contact holes electrically connecting the metal interconnections <NUM>.

Next, as shown in <FIG>, a stop layer <NUM> is formed on the MRAM region <NUM> and logic region <NUM> to cover the IMD layer <NUM> and metal interconnections <NUM>, an IMD layer <NUM> is formed on the stop layer <NUM>, and one or more photo-etching process is conducted to remove part of the IMD layer <NUM>, part of the stop layer <NUM>, and part of the IMD layer <NUM> on the MRAM region <NUM> and logic region <NUM> to form contact holes (not shown). Next, conductive materials are deposited into each of the contact holes and a planarizing process such as CMP is conducted to form metal interconnections <NUM> connecting the MTJ <NUM> and metal interconnections <NUM> underneath, in which the metal interconnections <NUM> on the MRAM region <NUM> directly contacts the hard mask <NUM> underneath while the metal interconnections <NUM> on the logic region <NUM> directly contacts the metal interconnections <NUM> on the lower level.

In this embodiment, the stop layers <NUM> and <NUM> could be made of same or different materials, in which the two layers <NUM>, <NUM> could all include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof. Similar to the metal interconnections formed previously, each of the metal interconnections <NUM> could be formed in the IMD layer <NUM> through a single damascene or dual damascene process. For instance, each of the metal interconnections <NUM> could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Claim 1:
A method for fabricating a semiconductor device, comprising:
forming a magnetic tunneling junction, MTJ, (<NUM>) on a substrate (<NUM>);
forming a spin orbit torque, SOT, layer (<NUM>) on the MTJ (<NUM>);
forming a spacer (<NUM>) adjacent to the MTJ (<NUM>) and the SOT layer (<NUM>);
forming an inter-metal dielectric, IMD, layer (<NUM>) around the MTJ (<NUM>) and the SOT layer (<NUM>) and around the spacer (<NUM>);
wherein the method is characterized by:
forming a first hard mask (<NUM>) on the IMD layer (<NUM>);
forming a semiconductor layer (<NUM>) on the first hard mask (<NUM>);
forming a second hard mask (<NUM>) on the semiconductor layer (<NUM>), wherein the second hard mask (<NUM>) comprises a dielectric layer;
patterning the semiconductor layer (<NUM>);
using the second hard mask (<NUM>) to pattern the first hard mask (<NUM>);
removing the second hard mask (<NUM>); and
removing the semiconductor layer (<NUM>).