Patent Description:
A gate driver is an integrated circuit configured to convert a low power switching signal, such as from a microcontroller, into a high current signal suitable for driving a high-power switching device, such as a power metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In other words, the gate driver can be an interface between a low-power domain and a high-power domain and may include electrical isolation to separate the power domains. It is often necessary to monitor the condition of the high-power switching device for safety and reliability. For example, an overcurrent condition can cause damage to the switching device and/or to its coupled devices (e.g., capacitors). Further, the over current condition could result in a safety concern to a user because of the high-power levels of an over current. Accordingly, the gate driver may be further configured to sense conditions of the high-power switching device and report these conditions to the microcontroller. As a result, the gate driver may be configured to communicate with the microcontroller.

<CIT> discloses verification of a gate driver protection logic that may receive through a link a test trigger signal and a disable signal.

<CIT> discloses test system circuits and methods in which a check start signals starts a test routine.

<CIT> discloses an electronic apparatus with switching elements. Specific information may be superimposed on a gate signal.

It is the object of the invention to provide high-power switching system, a gate driver and a testing method allowing a small-built implementation.

This object is accomplished by the features of the independent claims.

A high-power switching system has the features of claim <NUM>.

A gate driver has the features of claim <NUM>.

A method for testing a fault detector circuit has the features of claim <NUM>.

The foregoing illustrative summary, as well as other exemplary objectives and/or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.

The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

The present disclosure describes a gate driver that includes circuitry and protocols necessary for communicating with a microcontroller (i.e., controller) regarding functions other than switching (i.e., auxiliary functions). These auxiliary functions can include functions related to sensing and responding to a fault condition and may include (i) disabling an output of the driver (e.g., in response to a sensed fault condition), (ii) resetting a state of a fault detector (e.g., after a fault condition has ended), and (iii) testing a fault detector (e.g., to ensure it is operable). The disclosed circuits and methods may advantageously simplify the complexity of the communication with the microcontroller by combining these functions at a single input/output pin of the gate driver. In other words, the disclosed gate driver includes a multi-function pin.

<FIG> is a schematic block diagram of a high-power switching system including a gate driver according to a first possible implementation of the present disclosure. The system <NUM> includes a controller (e.g., microcontroller <NUM>) that controls a switching device <NUM> via a gate driver <NUM>. The gate driver <NUM> is coupled at an output to a controlling terminal (e.g., gate terminal) of the switching device <NUM>. The switching device can be any high-power switching device, including (but not limited to) a power MOSFET or an IGBT. The gate driver <NUM> is configured to provide an output signal (OUT) to change the switch condition (i.e., ON, OFF) of the switching device <NUM> according to an input signal (IN) from the microcontroller <NUM>. For example, the input signal may be a pulse width modulation (PWM) signal that can turn the switching device ON and OFF according to the modulation, such as in a switching power converter. For example, the switching device may have a high-side (HS) or a low-side (LS) switch included in a synchronous buck (or boost) converter. Further, the gate driver may control a plurality of switching devices, such as in a multiphase (i.e., multichannel) switching power supply. In these implementations it may be necessary to enable/disable the output of the gate driver. For example, in a light load condition a phase including the switching device <NUM> may be disabled to conserve power. Accordingly, the gate driver may receive an enable signal (EN) from the microcontroller <NUM> to enable (or disable) its output.

The input signal (IN) to the gate driver <NUM> may be in a low power domain that spans from a low-power, lower-rail voltage (e.g., low-power ground (GND1) to a low-power, upper-rail voltage (i.e., VDD1), while the output signal (OUT) from the gate driver <NUM> may be in a high-power domain that spans from a high-power lower rail voltage (e.g., high power ground (GND2) to a high-power, upper-rail voltage (i.e., VDD2).

In some implementations, crosstalk from the high-power domain to the low-power domains can impair function or cause damage to the low power circuitry. According, for these implementations the gate driver may include electrical isolation <NUM> between a high-power side and a low-power side. The electrical isolation may be implemented with a transformer or capacitor. The present disclosure can be applied to gate drivers with, or without, the electrical isolation <NUM>.

As mentioned, the gate driver <NUM> may be configured to perform functions that are auxiliary to its primary function of switching. For example, the gate driver may be configured with a fault protection function. A fault can be an over current condition created by a low impedance (e.g., short circuit) in the switching device. Alternatively, the over current condition may be created by a load coupled to the switching device. For example, a high current drawn by the load (e.g., when the load is shorted) may create the over current condition. Fault (i.e., over current) protection can be implemented in a variety of ways. <FIG> illustrates a possible implementation of a gate driver configured to determine over current by a desaturation of the switching device. <FIG> illustrates a possible implementation of a gate driver configured to determine over current based on a current sensed in a sense resistor coupled to the switching device.

<FIG> illustrates overcurrent protection implemented by sensing desaturation of the switching device <NUM>. Sensing desaturation can include measuring a collector-emitter voltage (VCE) of the switching device (e.g., IGBT) using a detection circuit <NUM>. The detection circuit <NUM> can include a diode (D) so that the measurement of VCE occurs when the switching device <NUM> is in the ON condition. The detection circuit <NUM> can further include a capacitor (C) that is charged to VCE while the switching device is in the ON condition. A time constant of the capacitor charging may help to filter changes to VCE during normal switching.

The switching device operates as an ON/OFF switch to conduct/block current to a load when it is in saturation mode. The saturation mode may depend on a collector-emitter voltage of the switching device. For example, a collector-emitter voltage (VCE) can be a few volts (e.g., <NUM>≤ VCE ≤ <NUM>) when the IGBT is in saturation mode. When the load is short-circuited, the current conducted by the IGBT increase thereby increasing the collector-emitter voltage (VCE) pushing the IGBT out of saturation mode. In other words, a high collector-emitter voltage (VCE) may indicate that the IGBT has become desaturated and is conducting a high current. The voltage on the capacitor (C) of the detection circuit <NUM> can be referred to as the desaturation signal (i.e., DESAT). The desaturation signal (DESAT) can be compared to a threshold (e.g., <NUM> ≤ VDESAT_THR ≤ <NUM>) and when the threshold is exceeded then the controller may change the state of a fault signal (i.e., FLT) transmitted to the microcontroller <NUM>. In response, the microcontroller <NUM> may change the state of the enable signal (EN) transmitted to the gate driver <NUM>. Switching operation is not resumed until a reset signal (i.e., RST) is received at the gate driver <NUM>. The reset signal (RST) may reset the fault signal (FLT) state back to no-fault. The reset signal (RST) may further re-engage the detection circuit to monitor the desaturation signal.

<FIG> is a schematic block diagram of a high-power switching system including a gate driver according to a second possible implementation of the present disclosure in which current sensing is used for overcurrent protection. In this implementation, a sense resistor (RSHUNT) is coupled in series (e.g., between an emitter terminal and a ground) with a switching device <NUM> to sense the current flowing through the switching device as a current sense (CS) signal (i.e., voltage). In a possible implementation a filter <NUM> (e.g., low-pass filter) is coupled between the sense resistor (RSHUNT) and the gate driver <NUM>.

Some applications (e.g., automotive) require checking the capability of the gate driver's over current protection (i.e., fault monitoring) periodically. For the implementation shown in <FIG>, the microcontroller may transmit a desaturation-check signal (DSCHK) to the gate driver <NUM>. The desaturation-check signal can mimic a fault condition in the circuitry of the gate driver so that the gate driver transmits a fault signal (FLT) indicating a fault. Accordingly, the microcontroller may transmit a DSCHK signal and monitor the FLT signal to see if the fault monitoring circuitry is working properly. For the implementation shown in <FIG>, the microcontroller may transmit a current-sense-check signal (CSCHK) to the gate driver <NUM>. The CS-check signal can mimic a fault condition in the circuitry of the gate driver so that the gate driver transmits a fault signal (FLT) indicating a fault. Accordingly, the microcontroller may transmit a CSCHK signal and monitor the FLT signal to see if the fault monitoring circuitry is working properly.

The high-power switching systems shown in <FIG> and <FIG> illustrate the auxiliary signals (FLT, RST, EN, (DSHK or CSCHK)) communicated between the microcontroller <NUM> and the gate driver <NUM>. These signals may be binary signals that are either in a HIGH state (e.g., approximately VDD1) or a LOW state (e.g., approximately GND1) to indicate a condition of the signal. A condition may exist for a HIGH signal and may not exist for a LOW signal or vice versa. Accordingly, inverse signals may be defined as well. For example, a fault-bar signal (FLTb) may be the logical inverse of the FLT signal, and a reset-bar signal (RSTb) may be the logical inverse of the RST signal. The microcontroller <NUM> may be configured to interpret signals or their inverse counterparts.

The gate drivers of <FIG>, <FIG> may include a pin (i.e., channel) to communicate each auxiliary signal, but it may be advantageous from a size, cost, and complexity standpoint to minimize the number of pins (i.e., channels) necessary for communicating the auxiliary signals. Accordingly, the present disclosure describes a gate driver configured to effectively combine the reset (RST), enable (EN), and fault check signals (i.e., DSCHK, CSCHK) into a single multifunction signal (MFP). By combining the signals, only one pin (i.e., multi-function pin) is used (e.g., is necessary) for receiving these signals from the microcontroller, thereby reducing the cost and complexity of the gate driver.

The present disclosure describes a multifunction signal that is switched between a HIGH level and a LOW level (i.e., modulated) in order to (i) enable/disable the gate driver, (ii) reset a fault condition in the gate driver, and (iii) activate a fault test (i.e., DESAT test, CS test). Accordingly, the present disclosure further describes a gate driver that includes circuitry (e.g., logic) configured to interpret the auxiliary signals from the multifunction signal (MFP). For example, the gate driver may include circuitry (e.g., logic) to generate a reset signal (RST) from the multifunction signal (MFP). Further, the gate driver may include circuitry to generate a desaturation check signal (DSCHK) or current-sense check signal (CSCHK) from the multifunction signal (MFP).

<FIG> is a schematic block diagram of a gate driver according to a first possible implementation of the present disclosure. The gate driver includes gate driver circuit <NUM> coupled to an input pin <NUM> and configured to receive an input signal (IN). The IN signal can be a digital signal with HIGH/LOW levels corresponding to desired ON/OFF switch states. The IN signal may be input to a first comparator <NUM> with hysteresis to remove switching noise. The output of the first comparator <NUM> may be coupled to logic (e.g., AND gate <NUM>). The AND gate <NUM> is further configured to receive a multifunction signal (MFP) from the output of a second comparator <NUM> with hysteresis. The second comparator <NUM> is configured to receive the multifunction signal from an MFP pin <NUM> of the gate driver <NUM>.

The AND gate <NUM> is configured to output a HIGH signal when the IN signal and the MFP signal are HIGH and to output a LOW signal otherwise. In other words, the MFP signal may function as an enable signal because the input signal (IN) can pass the AND gate <NUM> when the MFP signal is HIGH and not pass the AND gate <NUM> when the MFP signal is LOW. The output of the AND gate <NUM> is coupled to an amplifier <NUM> that is configured to convert the low-power input signal (IN) to a high-power output signal (OUT). The output of the amplifier <NUM> is coupled to an output pin <NUM> of the gate driver <NUM>, which can be coupled to a controlling terminal of a high-power switching device.

The gate driver <NUM> is configured to monitor a desaturation signal (DESAT) at a desaturation pin <NUM>. As discussed, the DESAT signal can be a voltage of an externally coupled capacitor (C), which can indicate if the switching device is in a saturation mode. The gate is configured to measure the DESAT signal while the switching device is ON. Accordingly, the gate driver includes a DESAT discharge transistor (i.e., discharge transistor <NUM>) that is coupled between the DESAT pin and a ground (e.g., GND2). A controlling terminal (e.g., gate terminal) of the discharge transistor <NUM> is coupled to logic (e.g., NOR gate) that is configured to ground the DESAT pin <NUM> when the switching device is OFF (i.e., the input signal is LOW). As shown, the logic may be implemented as a NOR gate <NUM> that receives the IN signal while the gate driver is enabled and further receives a desaturation check signal (DSCHK). The DSCHK signal can be LOW in normal conditions and can be HIGH during a test of the desaturation circuitry. In other words, unless the gate driver is (i) disabled or (ii) performing a desaturation test, the state of the discharge transistor corresponds to the input signal. For example, while the IN signal is HIGH (i.e., the switching device is ON), the discharge transistor <NUM> is OFF, and while the IN signal is LOW (i.e., the switching device is OFF), the discharge transistor <NUM> is ON.

The discharge transistor <NUM> may be coupled to the input of a fault detector circuit (i.e., fault detector <NUM>) and its ON/OFF state may enable/disable operation of the fault detector <NUM>. When enabled (i.e., discharge transistor <NUM> is OFF), the fault detector <NUM> may be configured to receive the DESAT signal and to output a fault signal (FAULT) when the DESAT signal satisfies a criterion. For example, the fault detector <NUM> may compare the DESAT signal (i.e., Vc) to a threshold (VDESAT-THR) and make the FAULT signal HIGH when the DESAT signal exceeds the threshold, otherwise the FAULT signal is LOW. Accordingly, the fault detector <NUM> may include a comparator <NUM> with the DESAT signal (Vc) at a non-inverting terminal and a threshold voltage (VDESAT-THR) at an inverting terminal of the comparator <NUM>. The threshold voltage may be generated by a voltage source <NUM> coupled to the inverting terminal of the comparator <NUM>.

The fault detector <NUM> may further include a current source (IDESAT) that is coupled between an upper rail voltage (e.g., VDD) and the DESAT pin <NUM>. The current source (IDESAT) is configured to charge the capacitor (C), which is coupled externally to the DESAT pin <NUM> during a DESAT test. The capacitor (C) can also be coupled to a collector terminal of an IGBT (not shown) so that the current source will help charge the capacitor (C) to the collector-emitter voltage (VCE) of the IGBT when it is ON. When the DESAT test is over and the IGBT is OFF, charge on the capacitor (C) (i.e., voltage (Vc)) may be drained (i.e., decreased) by the discharge transistor <NUM>.

The output of the fault detector <NUM> can be a fault signal (FAULT) that is HIGH when a fault (e.g., high current condition) is detected and is LOW when no fault (e.g., normal current condition) is detected. The fault signal (FAULT) is coupled to a fault communication circuit <NUM> that includes a latch (e.g., SR latch). The latch <NUM> can be configured to hold the FAULT signal HIGH until it is reset by a reset signal (RST). The output of the latch <NUM> can be coupled to a fault-bar pin via an output transistor <NUM>.

When a fault is detected, the FAULT signal may be latched HIGH by the latch <NUM> to switch an output transistor <NUM> ON to couple a fault-bar pin <NUM> to a ground (e.g., GND). When the latch <NUM> is reset to LOW, the output transistor <NUM> is switched OFF and the fault-bar pin <NUM> is pulled up to an upper rail voltage (e.g., VDD1) by a pull-up resistor <NUM>. Accordingly, a fault-bar signal (FLTb) is an inverted version of the fault signal (FAULT) that is held LOW by a latch <NUM> until it is cleared by a reset signal.

While the gate driver is configured to provide continuous DESAT protection, the disclosed gate driver can also be configured in a test mode to perform a DESAT test. In a DESAT test, the DESAT signal is forced to satisfy the fault criterion. At the same time the FLTb signal can be monitored. If the FLTb signal responds properly to the fault, then the DESAT functionality is verified (i.e., the DESAT test passes). For example, a proper response to the fault, can be the FLTb signal transitioning to a LOW level, where it is held by the latch. If the FLTb signal does not respond properly to the fault (e.g., the FLTb signal does not transition to a latched LOW state), then the DESAT functionality is not verified (i.e., the DESAT test fails).

The gate driver <NUM> includes activation logic <NUM> (e.g., DSCHK activation logic) that can interpret the MFP signal in the context of other signals, such as the input signal (IN) and the fault signal (FAULT), to configure the gate driver according to multiple functions. The multiple functions can include (i) disabling the output signal, (ii) starting a DESAT test (e.g., to generate a fault condition), and resetting the fault condition (e.g., to resume normal operation).

The multiple functions may correspond to multiple states (i.e., conditions) of the gate driver. For example, while the output is disabled, the gate driver may be said to be in a disabled condition (i.e., disabled state). While a DESAT test is being performed, the gate driver may be said to be in a test condition (i.e., test state). While a fault is detected, the gate driver may be said to be in a fault condition (i.e., fault state). The gate driver may be in a normal condition (i.e., normal state) when it is not in a disabled state, a test state, and a fault state.

<FIG> is a schematic block diagram of a gate driver according to a second possible implementation of the present disclosure. The gate driver includes a fault communication circuit <NUM> and a gate driver circuit <NUM> as in <FIG>, but includes a fault detector circuit (i.e., fault detector <NUM>) based on a sensed current signal (CS) rather than a DESAT signal. As before the output of the fault detector <NUM> can be a fault signal (FAULT) that is high when a fault (e.g., high current condition is detected and LOW when no fault (e.g., normal current condition) is detected. In a normal mode, a current sense pin <NUM> is coupled by a first switch <NUM> to a positive input of a comparator <NUM>, while an upper supply voltage (VDD) is decoupled by a second switch <NUM> from the positive input of the comparator <NUM>. The comparator <NUM> is configured to compare the voltage (i.e., the CS signal) to a current-sense threshold (VCS-THR) coupled to a negative terminal of the comparator. When the CS signal exceeds the current-sense threshold (VCS-THR), the fault detector <NUM> is configured to trigger the fault state in the gate driver.

The gate driver further includes activation logic <NUM> (i.e., CSCHK activation logic) that is configured to interpret MFP signals in the context of other signals, such as the input signal (IN) and the fault signal (FAULT), to configure the gate driver according to multiple functions. The multiple functions can include (i) disabling the output signal, (ii) starting a CS test (e.g., to generate a fault condition), and resetting the fault condition (e.g., to resume normal operation).

In a CS test the fault logic may configure the first switch <NUM> to decouple the CS pin <NUM> from the positive input of the comparator <NUM> and the second switch <NUM> to couple the upper rail voltage (VDD) to the positive input of the comparator <NUM> in order to trigger a fault condition (i.e., FAULT = HIGH). The activation logic <NUM> is further configured to deactivate the CS test (i.e., reset the fault condition) after the test has concluded by coupling the CS pin to the positive input of the comparator <NUM> via the first switch <NUM> and decoupling the upper rail voltage (VDD) from the positive input of the comparator <NUM> via the second switch <NUM>. An inverter <NUM> can be included so that the switches may be controlled in complementary fashion.

<FIG> are graphs of signals illustrating functions controlled by a multifunction signal (MFP) according to a possible implementation of the present disclosure. In the graphs <NUM>, the signals are aligned in time and alternate between HIGH levels and LOW levels to indicate conditions and alter operation of the gate driver. The graphs include a DSCHK signal, but it should be understood that a CSCHK signal could behave similarly.

During a first period <NUM>, the gate driver is in normal operation (i.e., in a normal state). Here, the MFP signal is HIGH to enable the output so that the OUT signal follows (i.e., matches) the IN signal. Further, in normal operation, the FLTb signal is HIGH indicating that no fault (i.e., high current) is detected and the DSCHK signal is LOW indicating that a DESAT test is not underway.

During a second period <NUM>, the output of the gate driver is disabled (i.e., the gate driver is in a disabled state). Here, the MFP signal is LOW to disable the output. When the output is disabled, the OUT signal is LOW despite HIGH levels of IN signal. Here the output was disabled for a reason other than a fault or a DESAT test because during the second period, the FLTb signal is HIGH indicating that no fault condition and the DSCHK signal is LOW indicating that a DESAT test is not underway.

During a third period <NUM>, the normal operation (i.e., the normal state) of the gate driver is restored because the MFP signal is HIGH to enable the output so that the OUT signal again follows (i.e., matches) the IN signal. Further, in normal operation, the FLTb signal is HIGH indicating that no fault (i.e., high current) is detected and the DSCHK signal is LOW indicating that a DESAT test is not underway.

At a first time <NUM>, the FLTb signal transitions LOW indicating that a fault is detected. The LOW FLTb signal disables the output. Accordingly, during a fourth period <NUM>, the gate driver is disabled, and the gate driver is in fault operation (i.e., in a fault state). Here, the output is disabled by the FLTb signal being LOW despite the MFP signal being HIGH. Also note, that the HIGH output signal (OUT) may be turned off slowly when being disabled to prevent voltage spikes (e.g., due to back EMF). In other words, the output may be disabled according to a soft turn off <NUM> (i.e., STO). The amplifier <NUM> of the gate driver <NUM> shown in <FIG> can be configured to reduce the OUT signal according to a soft turn off (i.e., soft shutdown) profile.

At a second time <NUM>, the MFP signal is transitioned LOW so that both the FLTb and the MFP signal are LOW. If this condition is held for more than a minimum reset period (TRST_MIN) then the FLTb signal is reset to a HIGH level indicating no fault condition. Additionally, the MFP signal can be reset to a HIGH level to enable the output so that a normal condition is restored during a fifth period <NUM>.

During the fifth period <NUM> the input signal (IN) may be turned off and the MFP signal may be pulsed (i.e., toggled) for a number of consecutive pulses to begin a DESAT test. During a sixth period <NUM> the gate driver is in a DESAT test operation (i.e., DESAT test state) a DSCHK signal is transition HIGH to disable the discharge transistor <NUM> so that the external capacitor (C) can be charged for the test.

<FIG> illustrates a state diagram that summarizes the states and the transitions between states, such as described with the signals of <FIG>. The gate driver can operate in a normal state <NUM> (i.e., normal mode) in which the output signal follows the input signal. The normal state <NUM> may be the most common operating state of the gate driver. Operation in states other than the normal state may be temporary and may ultimately result in a return to the normal state.

The gate driver can also operate in a disabled state <NUM> (i.e., disabled mode) in which the output is held LOW. The gate driver may transition from the normal state <NUM> to the disabled state <NUM> and from the disabled state <NUM> to the normal state <NUM> according to a level of the MFP signal. The gate driver can operate in a disabled state even when there is no fault detected.

The gate driver can also operate in a fault state <NUM> (i.e., fault mode) in which the output is held LOW. The gate driver may transition from the normal state <NUM> to the fault state <NUM> according to a level of the FTLb signal. In the fault mode, the FLTb signal is latched at a LOW level. The gate driver may transition from the fault state <NUM> to the normal state <NUM> when the MFP signal is held LOW for a period greater than or equal to a threshold (TRST-MIN).

The gate driver can also operate in a DESAT test state <NUM> (i.e., DESAT test mode, DSCHK mode) in which the DSCHK signal is held HIGH. The gate driver may transition from the normal state <NUM> to the DESAT test state <NUM> after the MFP signal is pulsed (e.g., HIGH/LOW/HIGH) for a number of times (e.g., <NUM> times). In the DESAT test state <NUM>, the voltage at the DESAT pin can be charged until it exceeds a threshold (VDESAT-THR), thereby changing the FLTb level. The gate driver may transition from the DESAT test state <NUM> to the fault state <NUM> according to the FLTb level. As before, the gate driver may transition from the fault state <NUM> to the normal state <NUM> when the MFP signal is held LOW for a period greater than or equal to a threshold (TRST-MIN).

As shown in <FIG> and <FIG>, the gate driver <NUM> further includes activation logic <NUM> to generate the DSCHK signal or CSCHK signal (i.e., DSCHK/CSCHK singal). <FIG> is a schematic block diagram of an activation logic circuit according to a possible implementation of the present disclosure. The activation logic <NUM> is configured to control a level of a desaturation check signal (DSCHK) or a current sense check signal (CSCHK). In particular the activation logic is configured to make the DSCHK/CSCHK signal HIGH when the MFP signal is pulsed (i.e., toggled) for a number of cycles. A HIGH DSCHK/CSCHK signal can configure the gate driver in a DESAT test state to charge the external capacitor (C) or a CS test state to couple the upper rail voltage to the input of the comparator.

The activation logic <NUM> includes a shift register <NUM>. The input of the shift register <NUM> can be coupled to a HIGH signal (i.e., VDD) and the output of the shift register is the DSCHK/CSCHK signal. The shift register includes a plurality of flip-flops (e.g., D-type flip-flops) coupled in series. The MFP signal may be coupled to a clock input of each of the flip flops so as the MFP signal is pulsed, the HIGH signal shifts to the output of the shift register. For example, if four flip flops are implemented then the MFP signal can be pulsed four times for the HIGH signal (VDD) to reach the output. The activation logic may include a low pass filter <NUM> coupled between the MFP signal and the shift register <NUM>. The low pass filter <NUM> may remove spurious signals from the MFP signal that could cause shift errors in the shift register <NUM>.

The DSCHK/CSCHK signal may be deactivated (i.e., made LOW) by clearing the shift register <NUM>. The shift registered may be cleared in several conditions. Accordingly, the activation logic includes a logic gate (e.g., NOR gate <NUM>) configured to clear the flip-flops of the shift register.

The NOR gate <NUM> is configured to receive a reset signal (RST), the input signal (IN), and the fault signal (FAULT). The NOR gate is configured to clear the shift register <NUM> if the RST signal is LOW, the IN signal is HIGH, or the FAULT signal is HIGH.

As mentioned previously, the DSHK signal may be deactivated (i.e., the DESAT test ended) by holding the MFP signal LOW for a period that is greater than a threshold (e.g., TRST-MIN). The gate driver <NUM> includes a low pass filter <NUM> that is configured to receive the MFP signal and output the RST signal. A delay associated with the low pass filter <NUM> may help to create the threshold (TRST-MIN) that is satisfied for the RST to change states and clear the shift register <NUM>.

<FIG> illustrates terminating a DSCHK mode (i.e., DESAT test state) by holding the MFP signal low for a period (TRST-MIN). While shown for the DSCHK mode, it may be understood that a CSCHK mode could operate similarly. At a first time <NUM>, the DSCHK signal is transitioned HIGH as a result of the MFP signal pulsing for a number of pulses determined by the shift register (e.g., <NUM> pulses). The gate driver enters the DSCHK mode, and the external capacitor is charged, thereby raising the DESAT signal. If the DESAT signal is allowed to rise above a threshold (e.g., VDESAT-THR), then the FAULT signal will transition HIGH moving the gated driver out of the DSCHK mode and into the FAULT mode. Here, however, the MFP signal is held low for a period (TRST-MIN) before a fault occurs. Accordingly at a second time <NUM>, the shift register is cleared so that the DSCHK signal is transitioned LOW and the gate driver returns to the NORMAL state. In the NORMAL state, the charge on the capacitor (i.e., DESAT signal) is drained by the discharge transistor <NUM> when the IN signal is low, as is the case shown here.

<FIG> illustrates a DSCHK mode (i.e., DESAT test state) that is prevented when the IN signal is HIGH. While shown for the DSCHK mode, it may be understood that a CSCHK mode could operate similarly. At a first time <NUM>, the MFP signal is toggled to begin a DESAT test (i.e., make DSCHK HIGH). At a second <NUM>, however, the IN signal is transition HIGH. This clears the shift register and as a result DSCHK is held LOW. In other words, the HIGH IN signal prevents the gate driver from entering the DESAT test state and remains in NORMAL mode. In normal mode the OUT signal follows the IN signal but is disabled when the MFP signal is pulsed LOW. When the OUT signal is held HIGH by the IN signal the DESAT signal charges and eventually at a third time <NUM>, a fault condition is reached, making the FAULT signal HIGH. In other words, at the third time <NUM> the gate driver enters the FAULT state. Here, the output is shut down (e.g., according to a soft turn off (STO) profile <NUM>. For example, the FAULT signal may trigger the amplifier <NUM> to perform a soft shutdown (SSD) of its output (see <FIG>). The gate driver remains in the fault state (i.e., FLTb is LOW) until it is returned to a NORMAL state at a fourth time <NUM> by holding the MFP signal LOW for a period.

<FIG> is a method for controlling a gate driver to test its faut detector circuit. The method <NUM> includes configuring <NUM> the gate driver for normal operation (i.e., OUT signal at OUT pin follows IN signal at IN pin). The method <NUM> further includes receiving <NUM> a series of pulses at a multifunction pin of the gate driver. The gate driver can receive the pulses until a first criterion <NUM> is satisfied. The first criterion may be receiving a number of consecutive pulses while the IN signal is LOW. If the first criterion is not satisfied, then the gate driver may be configured to reset <NUM> a pulse counter (e.g., shift register) and return to normal operation <NUM>. When the first criterion is satisfied, however, the method <NUM> further includes configuring <NUM> the gate driver to charge an external capacitor, which generates an increasing DESAT voltage. The DESAT voltage can continue to increase until it satisfies a second criterion <NUM>. The second criterion <NUM> may be the DESAT voltage exceeding a threshold. When the second criterion is satisfied, the method <NUM> further includes configuring <NUM> the gate driver for fault operation (i.e., FAULT state). In fault operation, the gate driver may be configured to discharge the external capacitor and transmit a fault signal (FLTb) to a fault pin of the gate driver. The fault operation can continue until an MFP signal is received <NUM> that satisfies a third criterion <NUM>. The third criterion <NUM> can be that the MFP signal at the multifunction pin is held LOW for a period longer than a threshold time. When the third criterion <NUM> is satisfied, the method <NUM> includes clearing <NUM> the fault and returning the gate driver to normal operation <NUM> (i.e., NORMAL state).

<FIG> illustrates signals of the gate driver during a test of its fault sensing capabilities, such as described for the method illustrated in <FIG>. While shown for the DSCHK mode, it may be understood that a CSCHK mode could operate similarly. At a first time <NUM>, a series of <NUM> consecutive pulses in the MFP signal is received at the gate driver while the IN signal is LOW, thus satisfying the first criterion of the method described above. Accordingly, the gate driver is configured to charge an external capacitor, which increases a DESAT signal. At a second time <NUM>, the DESAT signal exceeds a threshold, thus satisfying the second criterion of the method described above. Accordingly, the gate driver is configured to generate a fault (FAULT) which clears the DESAT signal and latches a fault signal (FLTb) at a fault pin of the gate driver LOW. At a third time <NUM>, the MFP signal is held LOW for a period, thus satisfying the third criterion of the method described above. Accordingly, the gate driver is configured to reset the fault signal (FLTb), which ends the test.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. The scope of protection is defined in the appended independent claims and preferred embodiments are defined in the dependent claims. The implementations described herein can include various combinations and/or subcombinations of the functions, components and/or features of the different implementations described.

It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.

Claim 1:
A high-power switching system comprising:
a switching device (<NUM>);
a gate driver (<NUM>, <NUM>, <NUM>) having an input pin (<NUM>) and a fault pin (<NUM>) and a single multifunctional pin (<NUM>) for a multifunctional signal; and
a controller (<NUM>) configured to:
transmit an input signal to said input pin (<NUM>) of the gate driver to control operation of the switching device, and
receive a fault signal from the fault pin (<NUM>) of the gate driver to monitor a fault in the switching device, wherein
the controller (<NUM>) is further configured to transmit said multifunction signal to said single multifunctional pin (<NUM>) of the gate driver to control operation of the gate driver; wherein the gate driver is configured by the multifunction signal to:
• disable an output of the gate driver; and
• activate a fault test to test a fault detector circuit of the gate driver;
characterized in that
the gate driver is further configured by the multifunction signal to clear the fault signal of a fault detected by the fault detector circuit of the gate driver when the multifunction signal is held LOW for a period greater than a threshold to clear the fault signal.