Patent Description:
The present disclosure relates to the technical field of storage devices, and in particular, to a method for manufacturing a memory.

With the continuous development of a semiconductor technology and a storage technology, an electronic device is continuously developing towards miniaturization and integration. A Dynamic Random Access Memory (DRAM) is widely applied in various electronic devices because of its relatively high storage density and relatively rapid read-write speed.

The DRAM may generally include a substrate, the substrate is provided with a plurality of active areas, a plurality of bit lines disposed at intervals are disposed on the substrate, and the active area of each row makes contact with a bit line. An isolation layer is also disposed on the substrate and the bit line, the isolation layer is provided with a plurality of through holes, the plurality of through holes and the active areas are in one-to-one correspondence, each of the through holes exposes an active area, and the bit line is not exposed in the through hole. In related arts, during manufacturing of a memory, after the through holes are formed, the substrate is usually etched along the through holes, so as to form grooves, the groove and the through hole are filled with a conducting wire, and thus a capacitor is electrically connected with the active area by the conducting wire.

However, in a process of forming the grooves, the isolation layer outside the bit line is easy to etch through, which results in that the conducting wire filled in the groove is conducted with the bit line, thereby causing failure of the memory and the relatively low yield of the memory.

Related arts can be found in <CIT> and <CIT>.

The embodiments of the present disclosure provide a method for manufacturing a memory, which may include: a substrate is provided, the substrate may include a plurality of active areas disposed at intervals, and the active area may include a first contact area and second contact areas; a plurality of bit lines disposed at intervals are formed on the substrate, and each of the bit lines is connected to at least one first contact area; first isolation layers are formed on the bit lines, and a first trench extending along a first direction is formed between the two adjacent first isolation layers; the bottom of the first trench is etched along the first trench to form a second trench, the bottom of the second trench is located in the substrate, and the second contact area is exposed in the second trench; a first conductive layer is formed in the first trench and the second trench; part of the first conductive layer is removed to form a plurality of first through holes, the first conductive layer is separated into a plurality of conducting wires by the plurality of first through holes, and each of the conducting wires is connected to a respective second contact area; and a second isolation layer is formed in the first through hole.

The method for manufacturing the memory provided by the embodiments of the present disclosure has the following advantages.

The method for manufacturing the memory provided by the embodiments of the present disclosure may include: a substrate is provided at first, the substrate may include a plurality of active areas disposed at intervals, and the active area may include a first contact area and second contact areas; a plurality of bit lines disposed at intervals are formed on the substrate, and each of the bit lines is connected to at least one first contact area; first isolation layers are formed on the bit line, and a first trench extending along a first direction is formed between the two adjacent first isolation layers; the bottom of the first trench is etched along the first trench to form a second trench, the bottom of the second trench is located in the substrate, and the second contact area is exposed in the second trench; a first conductive layer is formed in the first trench and the second trench; part of the first conductive layer is removed to form a plurality of first through holes, the first conductive layer is separated into a plurality of conducting wires by the plurality of first through holes, and each of the conducting wires is connected to a second contact area; and a second isolation layer is formed in the first through hole. As the first isolation layer is formed at first, the first trench is formed in the first isolation layer, furthermore, the bottom of the first trench is etched to form the second trench, the depth-to-width ratio of the second trench is reduced, so that the loading effect of the second trench is reduced, and meanwhile, the second trench and the first trench are aligned well, thereby improving the yield of the memory. As the first conductive layer is formed in the first trench and the second trench, the filling difficulty is relatively low, so as to improve the yield of the memory. As part of the first conductive layer is removed to form the plurality of first through holes in the first conductive layer, the retained first conductive layer forms the conducting wire, and the second isolation layer is formed in the first through hole. Compared with the prior art that an area formed by the first isolation layer and the second isolation layer in an encircling manner is also required to be etched so as to fill the conducting wire, in the embodiments of the present disclosure, etching is not required again after the second isolation layer is formed, so that the risk of damage to the first isolation layer by etching is reduced, the through etching possibility of the first isolation layer is reduced, and the yield of the memory is further improved.

In a related technology, during manufacturing of a memory, a plurality of bit lines and a first isolation layer covering the various bit lines are usually formed on a substrate at first; the substrate may include a plurality of active areas disposed at intervals, the active area may include a first contact area and second contact areas, each bit line is connected to at least one first contact area, and the first isolation layer between two adjacent bit lines forms a first trench; an intermediate layer is deposited in the first trench, and fully fills in the first trench; the intermediate layer is etched to form a first through hole, the retained intermediate layer forms a plurality of columnar structures disposed at intervals, and each of the columnar structures corresponds to a second contact area; a second isolation layer is deposited in the first through hole; the retained intermediate layer is removed to form a second through hole; the substrate is etched along the second through hole, so as to form a groove, and the groove exposes the second contact area; and a conducting wire is filled in the groove and the second through hole.

In the above manufacturing process, when the substrate is etched along the second through holes, the first isolation layer outside the bit line is easy to etch through, which results in that the conducting wire is conducted with the bit line, thereby causing failure of the memory and the relatively low yield of the memory. Moreover, the intermediate layer is removed by etching twice, the removing process is complex, and residue of the intermediate layer also causes the relatively low yield of the memory.

In order to solve the technical problem of the relatively low yield of the memory, the embodiments of the present disclosure provide a method for manufacturing a memory, at first, the bottom of a first trench is etched along the first trench formed in a first isolation layer to form a second trench, the bottom of which is located in a substrate, the second trench exposes an active area of the substrate, and then a first conductive layer is formed in the first trench and the second trench, so as to reduce the filling difficulty of the first conductive layer; a first through hole is formed in the first conductive layer, the retained first conductive layer forms a conducting wire, a second isolation layer is filled in the first through hole, etching is not required again after the second isolation layer is formed, so that the through etching possibility of the first isolation layer is reduced, and the yield of the memory is improved.

In order to make the above objectives, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in combination with the drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are not all embodiments but merely part of embodiments of the present disclosure. On the basis of the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skilled in the art without creative work shall fall within the scope of protection of the present disclosure.

Referring to <FIG>, the present disclosure provides a method for manufacturing a memory, which specifically includes the following steps.

At S101, a substrate is provided, the substrate includes a plurality of active areas disposed at intervals, and the active area includes a first contact area and second contact areas.

Referring to <FIG>, an active area <NUM> is disposed in the substrate <NUM>. Referring to <FIG>, the active area <NUM> is not exposed to the surface of the substrate <NUM>. There is a plurality of active areas <NUM>, which are disposed at intervals. Exemplarily, a Shallow Trench Isolation (STI) structure <NUM> is disposed among the plurality of active areas <NUM>, and silicon oxide (SiO<NUM>) is disposed in the STI structure <NUM>, so that the plurality of active areas <NUM> are isolated from each other.

The plurality of active areas <NUM> may be disposed in an array. Each of the active areas <NUM> include a first contact area <NUM> and second contact areas <NUM>, and the first contact area <NUM> and the second contact areas <NUM> are connected adjacently. The first contact area <NUM> is connected to a bit line <NUM>, and the second contact area <NUM> is connected to a capacitor, for example, the second contact area <NUM> is connected to the capacitor through a conducting wire and a capacitive contact pad in sequence.

In a possible example, as illustrated in <FIG>, the first contact area <NUM> is located in the center of the active area <NUM>, the second contact areas <NUM> are located at two sides of the active area <NUM>, that is, the second contact areas <NUM> are located at both sides of the first contact area <NUM> respectively, and the material of the active area <NUM> may include silicon (Si).

At S102, a plurality of bit lines disposed at intervals are formed on the substrate, and each of the bit lines is connected to at least one first contact area.

Referring to <FIG>, the plurality of bit lines <NUM> disposed at intervals are formed on the substrate <NUM>, a bit line contact window may be formed in the substrate <NUM>, the first contact area <NUM> of the active area <NUM> is exposed in the bit line contact window, and each of the bit lines <NUM> is connected to at least one first contact area <NUM> through the bit line contact window. Each of the bit lines <NUM> is connected to the first contact areas <NUM> of the plurality of active areas <NUM> in the same row, that is, the first contact areas <NUM> of the plurality of active areas <NUM> in the same row may be connected to the same bit line <NUM>, and each of the first contact areas <NUM> is only connected to a bit line <NUM>.

It is to be understood that, there is a certain angle between an orthographic projection of the bit line <NUM> on the substrate <NUM> and an orthographic projection of the active area <NUM> on the substrate <NUM>, that is, the two orthographic projections are not parallel. Exemplarily, in the orientation as illustrated in <FIG>, the bit line <NUM> is vertically arranged, the plurality of bit lines <NUM> are parallel to each other, the active area <NUM> is disposed to be inclined, and the plurality of active areas <NUM> are parallel to each other. The same bit line <NUM> may pass through the plurality of active areas <NUM>.

As illustrated in <FIG>, the bit line <NUM> may include a second conductive layer <NUM>, a third conductive layer <NUM> and a fourth conductive layer <NUM>, which are stacked in sequence, and the fourth conductive layer <NUM> is located on the substrate <NUM>, and is electrically connected with the active area <NUM> of the substrate <NUM>.

Exemplarily, the material of the second conductive layer <NUM> may include polycrystalline silicon, the material of the third conductive layer <NUM> may include titanium nitride (TiN), and the material of the fourth conductive layer <NUM> may include tungsten (W).

At S103, first isolation layers are formed on the bit line, and a first trench extending along a first direction is formed between two adjacent first isolation layers.

Also referring to <FIG>, after the bit lines <NUM> are formed, the first isolation layer <NUM> is formed on the bit lines <NUM>, and the first isolation layer <NUM> covers the bit lines <NUM>. It is to be understood that, the first isolation layer <NUM> is formed on an upper surface and a side surface of each of the bit lines <NUM>, and the material of the first isolation layer <NUM> may be an insulating material, such as silicon nitride (Si<NUM>N<NUM>), so as to perform protection and electric isolation on the bit lines <NUM>.

The first trench <NUM> is formed between two adjacent first isolation layers <NUM>, that is, two side walls of the first trench <NUM> are the first isolation layers <NUM>. As illustrated in <FIG>, the first trench <NUM> extends along a first direction, and it is to be understood that, the extending direction of the first trench <NUM> is the same as the extending direction of the bit line <NUM>.

In a possible example, as illustrated in <FIG> and <FIG>, a plurality of first sacrificial layers <NUM> may also be disposed in the first isolation layer <NUM>, and in a section vertical to the bit line <NUM> as illustrated in <FIG>, both sides of each of the bit lines <NUM> are provided with a first sacrificial layer <NUM>. The first sacrificial layer <NUM> extends along a first direction, that is, the extending direction of the first sacrificial layer <NUM> is the same as the extending direction of the bit line <NUM>.

The material of the first sacrificial layer <NUM> may include an oxide, such as SiO<NUM>. It is to be understood that, along the direction from the bit line <NUM> to the first trench <NUM>, a Nitride, an Oxide and a Nitride (NON) are sequentially formed outside the bit line <NUM>.

In some possible examples, referring to <FIG>, the first isolation layer <NUM> may be formed through the following steps.

A first nitride layer <NUM> is formed on a side wall and a top surface of the bit line <NUM>. For example, as illustrated in <FIG>, a second preset conductive layer, a third preset conductive layer, a fourth preset conductive layer and a first preset nitride layer are sequentially formed on the substrate <NUM>, the second preset conductive layer, the third preset conductive layer, the fourth preset conductive layer and the first preset nitride layer are etched, so as to form the second conductive layer <NUM>, the third conductive layer <NUM>, the fourth conductive layer <NUM> and the first nitride layer <NUM> as illustrated in <FIG>, and the second conductive layer <NUM>, the third conductive layer <NUM> and the fourth conductive layer <NUM> form the bit line <NUM>.

After the first nitride layer <NUM> is formed, the first sacrificial layer <NUM> and a second nitride layer <NUM> are formed, as illustrated in <FIG>, the formed first sacrificial layer <NUM> is located at two sides of the bit line <NUM> and the first nitride layer <NUM>, and the second nitride layer <NUM> covers the first sacrificial layer <NUM>, the first nitride layer <NUM> and the bit line <NUM>.

At S104, the bottom of the first trench is etched along the first trench to form a second trench, the bottom of the second trench is located in the substrate, and the second contact area is exposed in the second trench.

Referring to <FIG>, the bottom of the first trench <NUM> is etched along the first trench <NUM>, so as to form the second trench <NUM>, and the bottom of the second trench <NUM> is located in the substrate <NUM> as illustrated in <FIG>. The depth of the second trench <NUM> is relatively small, so that the loading effect is reduced, and thus the second trench <NUM> is conveniently formed. Meanwhile, the alignment problem of a through hole and an overlay mark in the active area <NUM> in a related technology may also be avoided.

Referring to <FIG>, the second contact area <NUM> is exposed in the second trench <NUM>, the active area <NUM> as illustrated in <FIG> has a partial solid line and a partial dotted line, the solid line shows the second contact area <NUM> exposed in the second trench <NUM>, and the dotted line shows the first contact area <NUM> shielded by the first isolation layer <NUM>, or the first contact area <NUM> shielded by the first isolation layer <NUM> and part of the second contact area <NUM>.

The first trench <NUM> exposes the substrate <NUM>, when the bottom of the first trench <NUM> is etched along the first trench <NUM>, the substrate <NUM> is etched, the second trench <NUM> is formed in the substrate <NUM>, and the second trench <NUM> exposes the second contact area <NUM> of the active area <NUM>.

In another possible example, the first isolation layer <NUM> covers the bit line <NUM> and the substrate <NUM>, that is, the first isolation layer <NUM> is exposed in the first trench <NUM>, when the bottom of the first trench <NUM> is etched along the first trench <NUM>, the first isolation layer <NUM> and the substrate <NUM> are etched, so as to form the second trench <NUM>, as illustrated in <FIG>, the bottom of the first isolation layer <NUM> is located in the substrate <NUM>, and the second trench <NUM> exposes the second contact area <NUM> of the active area <NUM>.

In the above examples, referring to <FIG>, the first sacrificial layer <NUM> is also disposed in the first isolation layer <NUM>, when the first isolation layer <NUM> and the substrate <NUM> are etched along the first trench <NUM>, part of the first isolation layer <NUM> is also removed, so that the first sacrificial layer <NUM> is exposed to the surface, away from the substrate <NUM>, of the first isolation layer <NUM>, and thus, the first sacrificial layer <NUM> is conveniently removed subsequently, thereby forming first air gaps. As illustrated in <FIG>, part of an area above the first isolation layer <NUM> is removed, so that the first sacrificial layer <NUM> is exposed to the upper surface of the first isolation layer <NUM>.

At S105, a first conductive layer <NUM> is formed in the first trench <NUM> and the second trench <NUM>.

Referring to <FIG>, the first conductive layer <NUM> is deposited in the first trenches <NUM> and the second trenches <NUM>, and for example, a polycrystalline silicon layer is deposited. After the first conductive layer <NUM> is formed, as illustrated in <FIG>, the first conductive layer <NUM> covers part of the second contact area <NUM> of the active area <NUM>, so that a conducting wire is subsequently formed and is electrically connected with the active area <NUM>.

When the first conductive layer <NUM> is formed, the filling space of the first trench <NUM> and the second trench <NUM> is relatively large, the filling difficulty is relatively low, the filling quality is better, a void and/or a seam generated in the first conductive layer <NUM> because of uneven filling is reduced, and the forming quality of the first conductive layer <NUM> is improved.

The first conductive layer <NUM> is formed in the first trench <NUM> and the second trench <NUM> through a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process and other processes.

At S106, part of the first conductive layer is removed to form a plurality of first through holes, the first conductive layer is separated into a plurality of conducting wires by the plurality of first through holes, and each of the conducting wires is connected to the second contact area.

The first conductive layer <NUM> is etched, so as to remove part of the first conductive layer <NUM>, the retained first conductive layer <NUM> and the first isolation layer <NUM> form the plurality of first through holes in an encircling manner, and the plurality of first through holes may be formed by a single etching.

The first conductive layer <NUM> is separated into the plurality of conducting wires by the plurality of first through holes, that is, the retained first conductive layer <NUM> forms a plurality of conducting wires disposed at intervals, each of the conducting wires is connected to a second contact area <NUM>, so as to be electrically connected with the active area <NUM>. Exemplarily, an active area <NUM> may be connected to two conducting wires, and an active area <NUM> may also be only connected to a conducting wire.

At S107, a second isolation layer is formed in the first through hole.

The second isolation layer may be formed through a deposition process, and the material of the second isolation layer may be an insulating material, such as Si3N4, so as to perform electric isolation on the conducting wire together with the first isolation layer <NUM>. That is, various conducting wires are separated by the first isolation layer <NUM> and the second isolation layer, so as to prevent two adjacent conducting wires from being conducted, and thus normal operation of the memory is ensured.

After the second isolation layer is formed, an area formed by the first isolation layer <NUM> and the second isolation layer in an encircling manner is not required to be etched, so that the risk of damage to the first isolation layer <NUM> by etching is reduced, the through etching possibility of the first isolation layer <NUM> is reduced, thus, the conducting wire is prevented from being conducted with the bit line <NUM>, and the yield of the memory is improved.

The method for manufacturing the memory provided by the embodiments of the present disclosure may include: a substrate <NUM> is provided at first, the substrate <NUM> may include a plurality of active areas <NUM> disposed at intervals, and the active area <NUM> may include a first contact area <NUM> and a second contact area112; a plurality of bit lines <NUM> disposed at intervals are formed on the substrate <NUM>, and each of the bit lines <NUM> is connected to at least one first contact area <NUM>; first isolation layers <NUM> are formed on the bit line <NUM>, and a first trench <NUM> extending along a first direction is formed between the two adjacent first isolation layers <NUM>; the bottom of the first trench <NUM> is etched along the first trench <NUM> to form a second trench <NUM>, the bottom of the second trench <NUM> is located in the substrate <NUM>, and the second contact area <NUM> is exposed in the second trench <NUM>; a first conductive layer <NUM> is formed in the first trench <NUM> and the second trench <NUM>; a plurality of first through holes <NUM> are formed in the first conductive layer <NUM>, the first conductive layer <NUM> is separated into a plurality of conducting wires <NUM> by the plurality of first through holes <NUM>, and each of the conducting wires <NUM> is connected to a second contact area <NUM>; and a second isolation layer <NUM> is formed in the first through hole <NUM>. As the first isolation layer <NUM> is formed at first, the first trench <NUM> is formed in the first isolation layer <NUM>, furthermore, the bottom of the first trench <NUM> is etched to form the second trench <NUM>, the depth-to-width ratio of the second trench <NUM> is reduced, so that the loading effect of the second trench <NUM> is reduced, and meanwhile, the second trench <NUM> and the first trench <NUM> are aligned well, thereby improving the yield of the memory. As the first conductive layer <NUM> is formed in the first trench <NUM> and the second trench <NUM>, the filling difficulty is relatively low. As part of the first conductive layer <NUM> is removed to form the plurality of first through holes <NUM> in the first conductive layer <NUM>, the retained first conductive layer <NUM> forms the conducting wire <NUM>, and the second isolation layer <NUM> is formed in the first through hole <NUM>. Compared with the prior art that an area formed by the first isolation layer <NUM> and the second isolation layer <NUM> in an encircling manner is also required to be etched after the second isolation layer <NUM> is formed so as to fill the conducting wire <NUM>, in the embodiments of the present disclosure, etching is not required again after the second isolation layer <NUM> is formed, so that the risk of damage to the first isolation layer <NUM> by etching is reduced, the through etching possibility of the first isolation layer <NUM> is reduced, and the yield of the memory is further improved.

It is to be noted that, referring to <FIG>, after the step of forming the first conductive layer in the first trench and the second trench, the method for manufacturing the memory may further include the following operations.

Part of the first conductive layer is removed to form third trenches extending along a first direction. Exemplarily, referring to <FIG> and <FIG>, part of the first conductive layer <NUM> on the first trench <NUM> is removed, so as to form the third trench <NUM>, that is, the third trench <NUM> is a part of the first trench <NUM>. As illustrated in <FIG>, a side wall of the third trench <NUM> is the first isolation layer <NUM>, the bottom of the third trench <NUM> is the first conductive layer <NUM>, and the bottom of the third trench <NUM> may be located above the bit line <NUM>.

After the third trenches <NUM> are formed, an intermediate layer <NUM> is formed in the third trenches <NUM> and on the first isolation layer <NUM>, and the intermediate layer <NUM> is filled in the third trenches <NUM> and covers the first conductive layer <NUM>. Referring to <FIG> and <FIG>, an upper part of the first trench <NUM> fills the intermediate layer <NUM>, and a lower part of the first trench <NUM> fills the first conductive layer <NUM>.

It is to be understood that, after the first conductive layer <NUM> is etched back to form the third trenches <NUM>, the intermediate layer <NUM> is formed in the third trenches <NUM>, on one hand, the height of the first conductive layer <NUM> is reduced, when the first conductive layer <NUM> is etched subsequently, the etching depth of the first conductive layer <NUM> is reduced, so that a by-product while etching is reduced, and thus the contour of the etched first conductive layer <NUM> is better. On the other hand, a selection ratio of the first conductive layer <NUM> to the first isolation layer <NUM> is difficult to increase, through arrangement of the intermediate layer <NUM>, a selection ratio of the intermediate layer <NUM> to the first isolation layer <NUM> is relatively high, and the first isolation layer <NUM> is less etched when the intermediate layer <NUM> is etched subsequently. Moreover, through arrangement of the intermediate layer <NUM>, diffusion of the first conductive layer <NUM> may also be stopped.

In some possible examples, referring to <FIG>, the intermediate layer <NUM> may be Spin on Dielectrics (SOD), and after a liquid insulating dielectric is spun, high-temperature processing is executed, so that the liquid insulating dielectric is solidified, thereby forming the intermediate layer <NUM>. The intermediate layer <NUM> may be an oxide, such as SiOz. After the intermediate layer <NUM> is formed, the intermediate layer <NUM> covers the first isolation layer <NUM> and the first conductive layer <NUM>, a side, departing from the first conductive layer <NUM>, of the intermediate layer <NUM> is flattened, as illustrated in <FIG>, and an upper surface of the intermediate layer <NUM> is flattened.

After flattening, the upper surface of the intermediate layer <NUM> exposes the first isolation layer <NUM> and the first conductive layer <NUM>. The intermediate layer <NUM> may be flattened through Chemical Mechanical Polishing (CMP). Certainly, a flattening mode is not limited, and for example, flattening may also be executed through a multi-layer photoresist process.

The implementation and various implementations below are described in detail by taking the intermediate layer <NUM> formed in the third trench <NUM> as an example. Referring to <FIG>, the operation of removing part of the first conductive layer to form the plurality of first through holes may include the following steps.

At S1061, part of the intermediate layer and part of the first isolation layer are removed to form fourth trenches extending along a second direction, and the first conductive layer and the first isolation layer are exposed in the fourth trench.

Referring to <FIG> and <FIG>, the intermediate layer <NUM> and the first isolation layer <NUM> are etched, so as to form the fourth trenches <NUM>, the fourth trenches <NUM> extend along the second direction, the second direction may be perpendicular to the first direction, and, as illustrated in <FIG>, the fourth trenches <NUM> are horizontally arranged, It is to be understood that, part of a side wall of the fourth trench <NUM> is the first isolation layer <NUM>, part of a side wall of the fourth trench <NUM> is the intermediate layer <NUM>, and the intermediate layer <NUM> and the first isolation layer <NUM> are alternate.

In a possible example, as illustrated in <FIG>, when part of the intermediate layer <NUM> and part of the first isolation layer <NUM> are removed, part of the first conductive layer <NUM> is also removed, so that the bottom of the fourth trench <NUM> is located in the first conductive layer <NUM>. Through the above arrangement, on one hand, the third trench <NUM> is easily formed, on the other hand, the height of the first conductive layer <NUM> is further reduced, so that the depth when the first conductive layer <NUM> is subsequently etched is reduced. As illustrated in <FIG>, the bottom of the fourth trench <NUM> is located above the bit line <NUM>, that is, the bit line <NUM> is not exposed in the fourth trench <NUM>, so that the bit line <NUM> is prevented from being damaged.

At S1062, the first conductive layer located at the bottom of the fourth trench is removed to form the plurality of first through holes.

Also referring to <FIG> and <FIG>, after the fourth trenches <NUM> are formed, the bottom of the fourth trench <NUM> is the first isolation layer <NUM> and the first conductive layer <NUM> that are alternate, that is, the fourth trench <NUM> exposes the first isolation layer <NUM> and the first conductive layer <NUM>.

As illustrated in <FIG>, the first conductive layer <NUM> exposed in the fourth trench <NUM> is removed by etching to form the plurality of first through holes <NUM>, and retain the first conductive layer <NUM> below the intermediate layer <NUM>, the retained first conductive layer <NUM> forms the plurality of conducting wires <NUM> disposed at intervals, and each of the conducting wires <NUM> makes contact with a second contact area <NUM>.

It is to be noted that, referring to <FIG> and <FIG>, the step of forming the second isolation layer <NUM> in the first through hole <NUM> may include: the second isolation layer <NUM> is deposited in the first through hole <NUM> and the fourth trench <NUM>, and the second isolation layer <NUM> is filled in the first through hole <NUM> and the fourth trench <NUM>. As illustrated in <FIG> and <FIG>, various conducting wires <NUM> are electrically isolated by the second isolation layer <NUM> and the first isolation layer <NUM>.

It is to be noted that, referring to <FIG>, after the step of forming the second isolation layer <NUM> in the first through holees <NUM>, the method for manufacturing the memory may further include: the intermediate layer <NUM> is removed to expose the conducting wires <NUM>. Exemplarily, the intermediate layer <NUM> is removed through wet etching till the conducting wire <NUM> is exposed. As illustrated in <FIG>, the intermediate layer is removed, so as to form a second through hole <NUM>, and the conducting wire <NUM> is exposed in the second through hole <NUM>.

When the first sacrificial layer <NUM> is disposed in the first isolation layer <NUM>, the first sacrificial layer <NUM> is also removed while the intermediate layer <NUM> is removed, so that a first air gap is formed. For example, the first sacrificial layer <NUM> is removed through steam etching. The material of the first sacrificial layer <NUM> may be the same as the material of the intermediate layer <NUM>, so that the first sacrificial layer <NUM> is conveniently removed by prolonging the etching time. The first sacrificial layer <NUM> may also be removed by etching through a high selection ratio while the first sacrificial layer <NUM> is etched, so that etching to other materials is reduced.

It is to be noted that, before the step of forming the second isolation layer <NUM> in the first through hole <NUM>, the method for manufacturing the memory may further include: a second sacrificial layer is formed on a side surface of the conducting wire <NUM>. The material of the second sacrificial layer may include an oxide, and for example, the second sacrificial layer is a SiO2 layer. The second sacrificial layer may be formed on each of two opposite side surfaces exposed by the conducting wire <NUM>.

When the second sacrificial layer is formed on the side surface of the conducting wire <NUM>, the second sacrificial layer is also removed while the intermediate layer <NUM> is removed, so that second air gaps are formed at both sides of the conducting wire <NUM>. For example, the second sacrificial layer is removed by steam etching through a high selection ratio.

In a possible example, the intermediate layer <NUM>, the first sacrificial layer <NUM> and the second sacrificial layer are removed by a single etching, so that the etching time is reduced. For example, the intermediate layer <NUM>, the first sacrificial layer <NUM> and the second sacrificial layer are same in material, so that etching is executed conveniently.

When the first sacrificial layer <NUM> is etched to form the first air gaps and/or the second sacrificial layer is etched to form the second air gaps, a peripheral circuit area on the substrate <NUM> is also etched usually, the peripheral circuit area may generally include an insulating layer and a protection layer, the material of the insulating layer is an oxide, and the material of the protection layer is a nitride. Because the first isolation layer <NUM> and/or the second isolation layer <NUM> may not be etched when the first sacrificial layer <NUM> is etched and/or the second sacrificial layer is etched, the protection layer of the peripheral circuit area may not be damaged, so that failure of a peripheral circuit due to through etching of the insulating layer of the peripheral circuit area is avoided.

Various embodiments or implementations in the specification are described in a progressive way, each of the embodiments focuses on the differences from other embodiments, and same and similar parts among various embodiments may be referred to each other.

It is to be understood by those skilled in the art that, in the disclosure of the present disclosure, orientation or position relationships indicated by terms "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are orientation or position relationships illustrated in the drawings, are adopted not to indicate or imply that indicated systems or components must be in specific orientations or structured and operated in specific orientations but only to conveniently describe the present disclosure and simplify descriptions and thus should not be understood as limits to the present disclosure.

In description of the specification, description of referring terms such as "one implementation", "some implementations", "a schematic implementation", "a demonstration", "a specific demonstration", or "some demonstrations" refers to specific features, structures, materials or features described in combination with the implementations or demonstrations involved in at least one implementation or demonstration of the present disclosure. In the specification, schematic description on the above terms not always refers to same embodiment modes or demonstrations. Moreover, the described specific features, structures, materials or features may be combined in any one or more implementations or demonstrations in a proper manner.

Claim 1:
A method for manufacturing a memory, comprising:
providing a substrate (<NUM>), the substrate (<NUM>) comprising a plurality of active areas (<NUM>) disposed at intervals, and each active area (<NUM>) comprising a first contact area (<NUM>) and second contact areas (<NUM>);
forming a plurality of bit lines (<NUM>) disposed at intervals on the substrate (<NUM>), each of the bit lines (<NUM>) being connected to at least one first contact area (<NUM>);
forming first isolation layers (<NUM>) on the respective bit lines (<NUM>), and forming a first trench (<NUM>) extending along a first direction between two adjacent first isolation layers (<NUM>);
etching the bottom of the first trench (<NUM>) along the first trench (<NUM>) to form a second trench (<NUM>), wherein the bottom of the second trench (<NUM>) is located in the substrate, and the second contact area (<NUM>) is exposed in the second trench (<NUM>); and
forming a first conductive layer (<NUM>) in the first trench (<NUM>) and the second trench (<NUM>); followed by removing part of the first conductive layer (<NUM>) to form third trenches (<NUM>) extending along a first direction; and
forming an intermediate layer (<NUM>) in the third trenches (<NUM>) and on the first isolation layer (<NUM>), the intermediate layer (<NUM>) being filled in the third trenches (<NUM>) and covering the first conductive layer (<NUM>); followed by
removing part of the first conductive layer (<NUM>) and part of the intermediate layer (<NUM>) to form a plurality of first through holes (<NUM>), wherein the first conductive layer (<NUM>) is separated into a plurality of conducting wires (<NUM>) by the plurality of first through holes (<NUM>), and each of the conducting wires (<NUM>) is connected to a respective second contact area (<NUM>); and
forming a second isolation layer (<NUM>) in the first through hole (<NUM>).