Patent Description:
A DAC such as a Capacitive DAC (CDAC) demands for a constant load impedance at its output over the instantaneous output bandwidth, i.e. the frequency range within which the output signal can be synthesized. Moreover, the load impedance presented to the DAC (e.g. a CDAC) should have a low value for optimum power transfer. For example, for a differentially implemented DAC, a full-scale single tone output power at the load may be calculated as follows: <MAT>.

POUT denotes the maximum single-tone output power (obtained with a full-scale sine wave) that is delivered by the DAC to a load exhibiting an impedance RL. VSUPPLY denotes the supply voltage of the DAC.

For a more complex output signal of the DAC (e.g. a broadband signal characterized by a Peak-to-Average-Ratio, PAR, of more than two), the output power at the load may be calculated as follows: <MAT>.

The PAR of DAC output signal x may be defined as follows: <MAT>.

xPEAK denotes the maximum value of the DAC output signal x, whereas xRMS denotes the Root Mean Square (RMS) value of the DAC output signal x.

It can be seen from mathematical expressions (<NUM>) and (<NUM>) that the maximum DAC output power increases for decreasing load impedances RL coupled to the output of the DAC. Further, it can be seen that the load impedances should be lowered for a lower supply voltage in order to maintain a given output power level.

For example, a CDAC is inherently a pure AC DAC with a very low output impedance at Radio Frequency (RF) frequencies (when looking back from the load into the CDAC) since the series capacitors in the CDAC cells block DC currents. As described above in connection with mathematical expressions (<NUM>) and (<NUM>), the CDAC output power may be maximized by minimizing the load impedance directly connected to the CDAC. However, typically a predefined output impedance such as <NUM>Ω (Ohm) is desired at the output of the CDAC in order to facilitate the interfacing with standard RF components (e.g. a filter, a mixer, a power amplifier or an antenna) of the transmit chain.

Documents <CIT>, <CIT> and <CIT> propose DAC architectures including a respective transformer for adjusting a load resistance.

Document "High Speed System Applications", by Analog Devices, discloses a high speed differential CMOS DAC coupled to an external transmission line transformer.

There may be a desire for an improved DAC architecture.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, and alternatives falling within the scope of the disclosure. Same or like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an "or", this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is "at least one of A and B" or "A and/or B". The same applies, mutatis mutandis, for combinations of more than two elements.

Whenever a singular form such as "a", "an" and "the" is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality. It will be further understood that the terms "comprises", "comprising", "includes" and/or "including", when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof.

<FIG> illustrates an example of a DAC <NUM> that may allow to maximize the DAC output power delivered to an external load and to prevent stability problems of active RF components interfacing with the DAC output (e.g. a mixer or a RF power amplifier).

The DAC <NUM> comprises a first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N configured to generate a first analog signal <NUM>. Further, the DAC <NUM> comprises a second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N configured to generate a second analog signal <NUM>. The first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N as well as the DAC cells <NUM>-<NUM>,. , <NUM>-N may be any number N ≥ <NUM> of DAC cells, respectively (e.g. related to a desired resolution of the DAC). The first analog signal <NUM> and the second analog signal <NUM> form a differential signal pair. In other words, the DAC <NUM> is implemented as a differential DAC.

For illustrative purposes only, the DAC cells <NUM>-<NUM> and <NUM>-<NUM> are illustrated in detail. The DAC cells <NUM>-<NUM> and <NUM>-<NUM> may be understood to be exemplary for one or more other DAC cells of the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N and the second plurality of DAC cells <NUM>-<NUM>,. Although the proposed DAC architecture is described below with respect to the plurality of first DAC cells <NUM>-<NUM>,. , <NUM>-N and the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N, it is to be noted that the proposed DAC architecture may as well be used for a DAC comprising only one first DAC cell and only one second DAC cell.

The DAC cells <NUM>-<NUM> and <NUM>-<NUM> comprise respective capacitive elements <NUM>, <NUM> configured to generate respective analog cell output signals <NUM>, <NUM> based on respective drive signals <NUM>, <NUM>. For example, the capacitive elements <NUM>, <NUM> may be on-chip capacitors (e.g. implemented within metal layers or by trenches within a semiconductor substrate). However, the capacitive elements <NUM>, <NUM> may also be any other suitable means for providing a capacitance. The capacitive elements <NUM>, <NUM> may, e.g., exhibit a capacitance ranging from a few picofarad to a few attofarad.

Further, the DAC cells <NUM>-<NUM> and <NUM>-<NUM> comprise driver circuits <NUM>, <NUM> (e.g. inverter circuits, buffer circuits or logic circuits) configured to generate the drive signals <NUM>, <NUM> for the capacitive element <NUM>, <NUM>. In the example of <FIG>, the driver circuits <NUM>, <NUM> are implemented as buffer circuits. The driver circuits <NUM>, <NUM> are supplied with a converter reference voltage VSUPPLY (e.g. <NUM> V) as provided by a voltage source <NUM> (e.g. a voltage regulator). For example, the converter reference voltage VSUPPLY may be a supply voltage for the DAC <NUM>. The driver circuit <NUM> is configured to receive a first digital signal <NUM> representing digital data, and to output signal values corresponding to those of the first digital signal <NUM> in order to generate the drive signal <NUM>. Similarly, the driver circuit <NUM> is configured to receive a second digital signal <NUM> representing inverted digital data, and to output signal values corresponding to those of the second digital signal <NUM> in order to generate the drive signal <NUM>. Since the data represented by the first and second digital signals <NUM> and <NUM> are inverted with respect to each other, the resulting analog cell output signals of the DAC cells <NUM>-<NUM> and <NUM>-<NUM> are inverted with respect to each other.

The first analog signal is based on the analog cell output signals of the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N, whereas the second analog signal is based on the analog cell output signals of the second plurality of DAC cells <NUM>-<NUM>,. For example, the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N may be coupled to a first common node so that their analog cell output signals sum up to the first analog signal. Similarly, the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N may be coupled to a second common node so that their analog cell output signals sum up to the second analog signal. Since the analog cell output signals of the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N are inverted with respect to the analog cell output signals of the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N, the first analog signal <NUM> and the second analog signal <NUM> form a differential signal pair.

However, it is to be noted that the implementation of the DAC cells <NUM>-<NUM> and <NUM>-<NUM> as illustrated in <FIG> is merely exemplary. The DAC cells of the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N and the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N may in some examples be implemented different from what is illustrated in <FIG> (e.g. comprises more, less or other components and/or receive more, less or different signals). For example, the DAC cell <NUM>-<NUM> may receive a modulated oscillation signal instead of the first digital signal <NUM>. In other examples, the DAC cell <NUM>-<NUM> may implemented like one of the DAC cells described below in connection with <FIG>.

The first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N and the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N may be understood as a DAC core <NUM> since they provide the core functionality of the DAC <NUM>.

The DAC <NUM> additionally comprises a transmission line transformer <NUM>. A transmission line transformer may, in general, be understood as a RF transformer consisting of matched transmission lines exhibiting equal length and characteristic impedance (e.g. the transmission lines are wound around one or more cores made up of magnetic material). The transmission lines are coupled to each other in a predetermined manner defining the impedance transformation ratio of the transmission line transformer.

The transmission line transformer <NUM> comprises a first input node <NUM> coupled to the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N, and a second input node <NUM> coupled to the second plurality of DAC cells <NUM>-<NUM>,. Further, the transmission line transformer comprises a first output node <NUM> and a second output node <NUM>. The transmission line transformer <NUM> is configured to present a first impedance at the first and second input nodes <NUM>, <NUM> and to present a second impedance at the first and second output nodes <NUM>, <NUM>.

In the example of <FIG>, the first output node <NUM> of the transmission line transformer <NUM> is coupled to an output node <NUM> of the DAC <NUM>. The second output node <NUM> of the transmission line transformer <NUM> is coupled to another output node <NUM> of the DAC <NUM>. The output nodes <NUM>, <NUM> of the transmission line transformer <NUM> and the output nodes <NUM>, <NUM> of the DAC <NUM> are illustrated as separate elements in <FIG>. However, according to examples of the proposed technique, the output nodes <NUM>, <NUM> of the transmission line transformer <NUM> and the output nodes <NUM>, <NUM> of the DAC <NUM> may be identical. Terms such as "an output node of the transmission line transformer is coupled to an output node of the DAC" used within the present disclosure are meant to cover both cases.

A load <NUM> is coupled to the output nodes <NUM>, <NUM> of the DAC <NUM>. In the example of <FIG>, the load <NUM> is illustrated as a resistor since any load presents an impedance to the DAC <NUM>. For example, the load <NUM> may be a mixer for up-mixing the first analog signal <NUM> and/or the second analog signal <NUM>, a Power Amplifier (PA) for amplifying the first analog signal <NUM> and/or the second analog signal <NUM>, a filter for filtering the first analog signal <NUM> and/or the second analog signal <NUM>, or an antenna for radiating the first analog signal <NUM> and/or the second analog signal <NUM> to the environment.

The transmission line transformer <NUM> forces the current at the two input nodes <NUM> and <NUM> to be equal (and in opposite phase), as well as the current at the two output nodes <NUM> and <NUM>. Because the impedance levels at the input and output nodes are different, the voltages at input and output nodes are different (an ideal transformer is transparent for power if losses are neglected).

The transmission line transformer <NUM> exhibits a very broad frequency response so that the transmission line transformer <NUM> is a suitable very broadband matching network enabling impedance transformation from the DAC core <NUM> (i.e. the first and second DAC cells) to the load <NUM> coupled to the DAC <NUM>. The transmission line transformer <NUM> may allow to present different impedances to the DAC core <NUM> and the load <NUM> at a very broad frequency response. For example, the first impedance presented at the first and second input nodes <NUM>, <NUM> may be lower than the second impedance present at the first and second output nodes <NUM>, <NUM>. That is, a low first impedance may be presented to the DAC core <NUM> in order to maximize the output power of the DAC <NUM>, whereas a predefined second impedance may be presented to the load <NUM>.

In general, a ratio of the first impedance to the second impedance may be N:M, wherein N and M are real numbers with N < M. For example, a ratio of the first impedance to the second impedance may be <NUM>:<NUM>, <NUM>:<NUM>, <NUM>:<NUM>, <NUM>:<NUM>, <NUM>:<NUM>, etc. In some examples, the first impedance may, hence, be at least four times lower than the second impedance.

The first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N is capable of generating the first analog signal <NUM> with a minimum signal frequency of less than a first frequency value and a maximum signal frequency of more than a second frequency value. The second frequency value may, e.g., be at least two, three, five, ten, or twenty times the first frequency value. For example, the first frequency value may between (in the order of) <NUM> and <NUM>, and the second frequency value may be <NUM> or more (e.g. about <NUM>).

Since the transmission line transformer <NUM> acts as a very wide bandwidth output matching network, the DAC <NUM> may, hence, allow direct RF synthesis for applications demanding a very wide output bandwidth. For example, Software-Defined-Radio (SDR) applications such as <NUM>th Generation New Radio (<NUM> NR) demand a very wide output bandwidth in the range of about <NUM> to more than <NUM>. In other words, SDR applications may cover more than a decade of signal bandwidth (i.e. the upper frequency limit of the used frequency range is more than ten times higher the lower limit). Since the transmission line transformer <NUM> exhibits a very broad frequency response with a suitable impedance transformation, the DAC <NUM> is capable of sub <NUM> operation at the low end as well as of <NUM> to <NUM> operation at the high end.

Since the transmission line transformer <NUM> is a very broadband matching network with suitable impedance transformation, the DAC <NUM> may be implemented as a fully integrated RF-CDAC for very wideband direct RF synthesis in an SDR application. For example, the DAC <NUM> may be used in a transmitter of a <NUM> NR base station or a <NUM> NR mobile device for direct synthesis of an RF output signal.

In some examples, the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N (and optionally the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N) and the transmission line transformer <NUM> may be integrated in a same semiconductor die (e.g. flip-chip package die; not illustrated in <FIG>). In other words, the DAC core <NUM> and the transmission line transformer <NUM> may be integrated on-chip. The compactness of the DAC <NUM> may allow to integrate several RF-DACs on a single semiconductor die (chip) such that a transmitter array (e.g. for <NUM> NR beamforming applications) may be provided.

Alternatively, the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N (and optionally the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N) may be integrated in a semiconductor die of a semiconductor package and the transmission line transformer <NUM> may be formed on a Printed Circuit Board (PCB) holding the semiconductor package.

In the example of <FIG>, the load <NUM> is coupled to both output nodes <NUM>, <NUM> of the transmission line transformer <NUM> (e.g. via the output nodes <NUM>, <NUM> of the DAC <NUM>). In alternative examples, the load <NUM> (e.g. an antenna) may be coupled to only one of the output nodes <NUM>, <NUM> of the transmission line transformer <NUM>, whereas the other one of output nodes <NUM>, <NUM> of the transmission line transformer <NUM> is coupled to ground. For example, the second output node <NUM> may be coupled to ground. The ground connection of the second output node <NUM> may be done on-chip, leading to only one output pin, or, alternatively, in package (still only one output pin for the packaged chip), or on the PCB (two output pins, only one used for signal transfer).

In the above description of <FIG>, it is generally referred to a transmission line transformer. In the following, two DACs are described with reference to <FIG> and <FIG> using a Guanella-type transmission line transformer. The Guanella-type transmission line transformer is an example for a transmission line transformer that may allow a broadband frequency response with a relatively wide range of impedance ratios.

<FIG> illustrates an exemplary DAC <NUM> using a Guanella-type transmission line transformer <NUM> with an impedance ratio of <NUM>:<NUM>. That is, the first impedance that is presented to the DAC core <NUM> is four times lower than the second impedance presented to the load <NUM>. Other than that, the DAC <NUM> is identical to DAC <NUM> illustrated in <FIG>. The DAC <NUM> uses the Guanella-type transmission line transformer <NUM> as broadband matching network so that an integrated RF-CDAC may be provided.

The Guanella-type transmission line transformer <NUM> with intertwined inductor structures may be (easily) integrated on chip so that the first plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N, the second plurality of DAC cells <NUM>-<NUM>,. , <NUM>-N and the Guanella-type transmission line transformer <NUM> may be integrated in a same semiconductor die. For example, the output side (indicated by output nodes <NUM> and <NUM>) of the Guanella-type transmission line transformer <NUM> may be coupled to the load <NUM> via a semiconductor package holding the semiconductor die.

The two coupled inductor pairs <NUM>, <NUM> of the Guanella-type transmission line transformer <NUM> form pairs of coupled transmission lines. In order to achieve the <NUM>:<NUM> impedance ratio, the pairs of coupled transmission lines are respectively coupled in parallel on the input side (indicated by input nodes <NUM> and <NUM>) and in series on the output side.

For example, if an impedance of the load <NUM> is <NUM>Ω, the Guanella-type transmission line transformer <NUM> presents a (differential) impedance of <NUM>Ω to the DAC core <NUM>. For example, for an integrated RF-CDAC in <NUM> V silicon technology, the Guanella-type transmission line transformer <NUM> with impedance ratio of <NUM>:<NUM> may be a good compromise between achievable output power and bandwidth (e.g. for very high bandwidth applications such as <NUM> NR).

<FIG> illustrates another exemplary DAC <NUM> using a Guanella-type transmission line transformer <NUM> with an impedance ratio of <NUM>:<NUM>. That is, the first impedance that is presented to the DAC core <NUM> is nine times lower than the second impedance presented to the load <NUM>. Other than that, the DAC <NUM> is identical to DACs <NUM> and <NUM> described above.

Compared to the Guanella-type transmission line transformer <NUM> of DAC <NUM>, the Guanella-type transmission line transformer <NUM> used three coupled inductor pairs <NUM>, <NUM> and <NUM> instead of only two pairs. Since three inductor pairs are now effectively coupled in parallel on the input side (indicated by input nodes <NUM> and <NUM>), the Guanella-type transmission line transformer <NUM> provides a higher impedance ratio compared to the Guanella-type transmission line transformer <NUM> of DAC <NUM>.

Accordingly, the Guanella-type transmission line transformer <NUM> may present a lower impedance value to the DAC core <NUM> than the Guanella-type transmission line transformer <NUM> of DAC <NUM>. As a consequence, the DAC <NUM> may exhibit a higher output power than the DAC <NUM>.

Compared to DAC <NUM>, the parallel coupling of three coupled inductor pairs <NUM>, <NUM> and <NUM> instead of only two pairs shifts the lower cutoff frequency of the Guanella-type transmission line transformer upwards for the same inductance L of the inductors and the same capacitance CDAC of the CDAC. Therefore, DAC <NUM> is more suitable for applications demanding for lower frequency synthesis (e.g. less than <NUM> for on-chip implementations).

Using four pairs of coupled inductor pairs (i.e. four transmission line systems) in parallel provides a Guanella-type transmission line transformer with an impedance ratio of <NUM>:<NUM>. This may allow still higher output power for the trade-off of reduced bandwidth (in particular towards lower frequencies for the same capacitance CDAC of the CDAC).

In the examples of <FIG> and <FIG>, the transmission line transformer is implemented as Guanella-type transmission line transformer. However, the proposed architecture is not limited to Guanella-type transmission line transformers. In general any transmission line transformer may be used. For example, Ruthroff-type transmission line transformers may be used instead of the Guanella-type transmission line transformers <NUM>, <NUM> in the above described DACs <NUM>, <NUM>.

A first example of a Ruthroff-type transmission line transformer <NUM> with an impedance ratio of <NUM>:<NUM> is illustrated in <FIG>. Unlike the Guanella-type transmission line transformers, the Ruthroff-type transmission line transformer <NUM> exhibits a direct connection from the input to the output. The transmission lines of the Ruthroff-type transmission line transformer <NUM> are coiled forming chokes so that the transmission lines are raised by a voltage equal to the input, resulting in a voltage twice the input and, hence, a <NUM>:<NUM> impedance ratio. The characteristic impedance of the transmission line may, e.g., be equal to one-half of the load impedance RL. This structure is also known as a "bootstrap". Compared to the Ruthroff-type transmission line transformer <NUM>, the Guanella-type transmission line transformer <NUM> exhibits a wider frequency response (i.e. a higher bandwidth).

An extension of the Ruthroff-type transmission line transformer <NUM> is illustrated in <FIG> illustrates another Ruthroff-type transmission line transformer <NUM> with an impedance ratio of <NUM>:<NUM>. The Ruthroff-type transmission line transformer <NUM> uses three inductors with one of the inductors connected to the input impedance.

Still another Ruthroff-type transmission line transformer <NUM> with an impedance ratio of <NUM>:<NUM> is illustrated in <FIG>. In order to achieve the impedance ratio of <NUM>:<NUM>, five inductors are used.

By decreasing the impedance ratio, a bandwidth of the Ruthroff-type transmission line transformers may be increased.

As indicated by means of the above examples, transmission line transformers with different impedance transformation ratios may be used to optimize the DAC (e.g. a CDAC) output bandwidth vs. the DAC output power trade-off for specific applications.

An example of an implementation using a DAC according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a radio base station <NUM> (e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising a DAC <NUM> as proposed.

The DAC <NUM> is part of a transmitter <NUM>. The transmitter <NUM> additionally comprises digital circuitry <NUM> (e.g. a Digital Signal Processor, DSP) configured to supply digital data as input to the DAC <NUM>. For example, the digital circuitry <NUM> may be configured to generate the digital data based on data to be wirelessly transmitted.

Further, the base station <NUM> comprises at least one antenna element <NUM> coupled to the DAC <NUM> for radiating one or more RF transmit signals that are based on the DAC output to the environment. For example, the DAC <NUM> may be coupled to the antenna element <NUM> via one or more intermediate elements such as a filter, an up-converter (mixer) or a PA.

Additionally, the base station <NUM> comprises a receiver <NUM> configured to receive a RF receive signal from the antenna element <NUM> or another antenna element (not illustrated) of the base station <NUM>.

To this end, a base station supporting direct RF synthesis at a very wide output bandwidth may be provided.

The base station <NUM> may comprise further elements such as, e.g., a baseband processor, an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit (CPU) cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I<NUM>C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/ MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the baseband processor may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using a DAC according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a mobile device <NUM> (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising a DAC <NUM> as proposed.

The DAC <NUM> is part of a transmitter <NUM>. The transmitter <NUM> additionally comprises digital circuitry <NUM> (e.g. a DSP) configured to supply digital data as input to the DAC <NUM>. For example, the digital circuitry <NUM> may be configured to generate the digital data based on data to be wirelessly transmitted.

Further, the mobile device <NUM> comprises at least one antenna element <NUM> coupled to the DAC <NUM> for radiating one or more RF transmit signals that are based on the DAC output to the environment. For example, the DAC <NUM> may be coupled to the antenna element <NUM> via one or more intermediate elements such as a filter, an up-converter (mixer) or a PA.

Additionally, the mobile device <NUM> comprises a receiver <NUM> configured to receive a RF receive signal from the antenna element <NUM> or another antenna element (not illustrated) of the mobile device <NUM>.

To this end, a mobile device supporting direct RF synthesis at a very wide output bandwidth may be provided.

The mobile device <NUM> may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I<NUM>C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The wireless communication circuits using digital-to-analog conversion according to the proposed architecture or one or more of the examples described above may be configured to operate according to one of the 3GPP-standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a <NUM> NR, a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM), an Enhanced Data rates for GSM Evolution (EDGE) network, or a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuits may be configured to operate according to mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WI-MAX) network IEEE <NUM> or Wireless Local Area Network (WLAN) IEEE <NUM>, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc..

The examples described herein may be summarized as follows:
An example relates to a DAC comprising a first plurality of DAC cells configured to generate a first analog signal. The DAC further comprises a second plurality of DAC cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Additionally, the DAC comprises a transmission line transformer comprising a first input node coupled to the first plurality of DAC cells, a second input node coupled to the second plurality of DAC cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

In some examples, the transmission line transformer is a Guanella-type transmission line transformer.

According to some examples, the transmission line transformer is a Ruthroff-type transmission line transformer.

In some examples, the first impedance is lower than the second impedance.

According to some examples, the first impedance is at least four times lower than the second impedance.

In some examples, the first plurality of DAC cells is capable of generating the first analog signal with a minimum signal frequency of less than a first frequency value and a maximum signal frequency of more than a second frequency value. The second frequency value is at least five times the first frequency value.

According to some examples, the first frequency value is between <NUM> and <NUM>, and wherein the second frequency value is <NUM> or more.

In some examples, at least one of the first plurality of DAC cells comprises a capacitive element configured to generate an analog cell output signal based on a drive signal, and a driver circuit configured to generate the drive signal for the capacitive element. The first analog signal is based on the analog cell output signal.

According to some examples, the first output node of the transmission line transformer is coupled to an output node of the DAC.

In some examples, the transmission line transformer further comprises a second output node coupled to another output node of the DAC.

According to some examples, the transmission line transformer further comprises a second output node coupled to ground.

In some examples, the first plurality of DAC cells and the transmission line transformer are integrated in a same semiconductor die.

Another example relates to a transmitter comprising a DAC according to any of the examples and digital circuitry configured to supply digital data as input to the DAC.

In some examples, the digital circuitry is configured to generate the digital data based on data to be wirelessly transmitted.

A further example relates to a mobile device comprising a transmitter according to any of the examples and at least one antenna element coupled to the DAC.

According to some examples, the mobile device further comprises a receiver configured to receive a radio frequency receive signal from the antenna element.

A still further example relates to a base station comprising a transmitter according to any of the examples and at least one antenna element coupled to the DAC.

In some examples, the base station further comprises a receiver configured to receive a radio frequency receive signal from the antenna element.

Functions of various elements shown in the figures, including any functional blocks labeled as "means", "means for providing a signal", "means for generating a signal. ", etc., may be implemented in the form of dedicated hardware, such as "a signal provider", "a signal processing unit", "a processor", "a controller", etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term "processor" or "controller" is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage.

It is to be understood that the disclosure of multiple acts, processes, operations, steps or functions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

Claim 1:
A digital-to-analog converter (<NUM>), comprising:
a first plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N) configured to generate a first analog signal (<NUM>);
a second plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N) configured to generate a second analog signal (<NUM>), wherein the first analog signal (<NUM>) and the second analog signal (<NUM>) form a differential signal pair, and wherein the first plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N) and the second plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N) form a digital-to-analog converter core (<NUM>) of the digital-to-analog converter (<NUM>); and
a transmission line transformer (<NUM>) comprising a first input node (<NUM>) coupled to the first plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N), a second input node (<NUM>) coupled to the second plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N), a first output node (<NUM>) coupled to an output node (<NUM>) of the digital-to-analog converter (<NUM>), and a second output node (<NUM>) coupled to another output node (<NUM>) of the digital-to-analog converter (<NUM>), wherein the transmission line transformer is a matching network configured to present a first impedance at the first and second input nodes (<NUM>, <NUM>) and to present a second impedance at the first output node (<NUM>) for impedance transformation from the digital-to-analog converter core (<NUM>) to an external load (<NUM>) coupled to the output node (<NUM>) and the other output node of the digital-to-analog converter (<NUM>),
wherein the first plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N), the second plurality of digital-to-analog converter cells (<NUM>-<NUM>, ..., <NUM>-N) and the transmission line transformer (<NUM>) are integrated in a same semiconductor die.