Patent Description:
Wireless networks provide communication between nodes without the cost and complexity of routing cables. Wireless nodes can be distributed in remote or otherwise hard-to-reach locations. These nodes can include one more local power sources configured to provide power for the node, for example. To conserve power, low power communication schemes have been developed to limit power consumption due to data communication.

<CIT> relates to a method and apparatus for providing multi-user parallel channel access (MU-PCA) and/or single-user parallel channel access (SU-PCA) using transmit and/or receive with symmetrical bandwidth, in the downlink (DL), uplink (UL), or combined DL and UL.

<CIT> relates to architectures, systems, methods, and computer program products for real-time object locating and position determination using frequency channel diversity for transmitting and receiving position determination signals including bursts of location signals.

<CIT> relates to a method of, in a physical layer of a communication stack of a wireless communication device, receiving a first radio frequency (RF) signal, converting the first RF signal to a first digital data signal, and passing the first digital data signal to a higher communication stack layer.

It is desirable to increase throughput and capacity in low power wireless networks. For example, in conventional time synchronized channel hopping(TSCH) implemented networks, only one frequency channel is used to transmit data during each timeslot. Therefore, throughput is limited by only allowing one node to wirelessly transmit at a time. The present inventors have realized, among other things, that scheduling multiple wireless nodes to communicate during a single timeslot can increase throughput and capacity while still providing a low power communication scheme.

The present invention provides a system as defined by claim <NUM> and method as defined by the claim <NUM>.

A low power wireless system is disclosed herein that employs wireless communication on multiple channels simultaneously. For example, the system may employ time synchronized channel hopping (TSCH) with multiple scheduled communications per timeslot. In an example, the wireless system is a wireless battery monitoring system for a vehicle. Each wireless node can be positioned to sense a characteristic of one or more battery cells, such as a current through the cells or a voltage across the cells, for example. A wireless node, such as a network manager, for example, can employ one or more wideband radios, multiple narrowband radios, or a combination thereof to receive communication on multiple channels simultaneously. The wireless node can transmit acknowledgement packets (ACKs) to each node that provided the simultaneous communication. The ACKs can be simultaneous using a wideband radio or multiple narrowband radios, or can be staggered using a single narrowband radio, for example.

<FIG> is a diagram illustrating a system <NUM> for a vehicle <NUM> that employs simultaneous multi-channel communication between wireless nodes. The vehicle <NUM> may include network managers 104a and 104b, wireless nodes 106a-<NUM>, an electronic control unit (ECU) <NUM>, and a battery pack <NUM> that includes battery modules 112a-<NUM>. Each battery module 112a-<NUM> can include several battery cells. In one example, each module 112a-<NUM> includes <NUM> battery cells. In other embodiments, each module 112a-<NUM> can include any number of battery cells. While illustrated as a wireless battery monitoring system, the system <NUM> can be used for monitoring any component of a vehicle or other apparatus within which a low-power wireless system is desired.

The wireless nodes 106a-<NUM> can be wireless sensors, for example, configured to sense operational characteristics of the battery cells of each of the battery modules 112a-<NUM>, including, but not limited to, a voltage across or current through a respective battery module 112a-<NUM>. The network managers 104a and 104b can collect the sensed data from the wireless nodes 106a-<NUM>, for example, and provide the data to a host application running on the ECU <NUM> or other system through a wired or wireless connection. The host application can use the data to monitor the health of, and provide control for, the battery pack <NUM>. The wireless nodes 106a-<NUM> and network managers 104a and 104b can be configured using a mesh network topology, a star topology, a multi-hop topology, or any other wireless network configuration.

In an example, the ECU <NUM> is configured to execute a host application for the battery monitoring system. While described in this example as hosted by the ECU <NUM>, the host application can be executed by any other computing system. For example, the host application can be executed by one of the managers 104a and/or 104b. The ECU <NUM> can include, for example, software, hardware, and combinations of hardware and software configured to execute several functions related to control of the battery monitoring system. The ECU <NUM> can include controllers or processors such as any one or more of a microprocessor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or equivalent discrete or integrated logic circuitry. The ECU <NUM> can also include storage devices, including short-term and/or long-term memory that can be volatile and/or non-volatile. Examples of non-volatile storage elements include magnetic hard discs, optical discs, floppy discs, flash memories, or forms of electrically programmable memories (EPROM) or electrically erasable and programmable (EEPROM) memories. Examples of volatile memories include random access memories (RAM), dynamic random access memories (DRAM), static random access memories (SRAM), and other forms of volatile memories known in the art.

In one example, the network managers 104a and 104b may be configured to communicate with the wireless nodes 106a-<NUM> using time synchronized channel hopping (TSCH). <FIG> is a chart illustrating an example TSCH schedule 200a for a wireless network that includes multi-channel communication for each timeslot. A gateway, network manager, or other wireless node can include a wideband radio, multiple narrowband radios, or a combination thereof, for example, to permit simultaneous communication with two or more other nodes on two or more respective channels. The network can schedule communication between the nodes so that each node knows when, and at what frequency, to transmit. While illustrated in <FIG> as permitting two wireless nodes to communicate with another wireless node simultaneously, other examples can allow any number (N) of wireless nodes to communicate simultaneously with another wireless node device. While discussed as implemented using a TSCH scheme, the network can be implemented using any other low power wireless communication scheme in which nodes are scheduled to communicate during a respective timeslot.

For the TSCH schedule <NUM>, a timeslot (TS) is defined. This can be any amount of time, such as <NUM>, to allow for a wireless node (nodes 106a-<NUM>, for example) to transmit a communication to another node (nodes 104a and 104b, for example) and receive an acknowledgement (ACK) from the node. Each network node is allocated one or more predefined timeslots within a defined slotframe (SF). Thus, as seen in <FIG>, eight transmissions occur during the first SF, allowing each of the eight nodes 106a-<NUM> of <FIG>, for example, to communicate with the managers 104a and/or 104b. Each TS can be static or dynamic, for example, to accommodate systems that may communicate at multiple data rates. In the example illustrated in <FIG>, each TS includes a data communication <NUM> from a first node and a simultaneous data communication <NUM> from a second node.

Each communication <NUM> and <NUM> includes a data transmission <NUM> and an ACK <NUM>. In the example illustrated in <FIG>, the ACKs <NUM> are communicated simultaneously for each TS. Thus, the ACK <NUM> for the communication <NUM> is sent at the same time as the ACK <NUM> for communication <NUM>. This can be accomplished by the network manager 104a or 104b, for example, using a wideband radio transmitter or multiple narrowband radio transmitters, for example. By transmitting the ACKs <NUM> simultaneously, each TS can be as short as a single data transmission and ACK. While illustrated in <FIG> as being sent on the same channel as the respective data transmission <NUM>, in other examples, the respective ACK <NUM> can be transmitted on a different channel than the data transmission <NUM>.

<FIG> is a chart illustrating another example TSCH schedule 200b that includes staggered acknowledgements for each TS. For each TS, a wireless node, such as a network manager 104a and/or 104b, for example, can be configured to receive data transmissions <NUM> and <NUM> simultaneously. The wireless node can then provide staggered ACKs, transmitted during subsequent time periods for the respective TS. For example, the wireless node can provide an ACK <NUM> for the data transmission <NUM>, followed by an ACK <NUM> for the data transmission <NUM>. The length of each TS can be set accordingly to allow for the staggered ACKs <NUM> and <NUM>. While illustrated as two simultaneous transmission and two respective ACKs, any number of simultaneous transmissions and respective ACKs can be scheduled providing the TS is sized appropriately. While illustrated in <FIG> as transmitted on separate channels, in other examples, the ACKs <NUM> and <NUM> can be transmitted on the same channel, which may be the same channel as the data transmission <NUM>, the data transmission <NUM>, or a different channel.

The schedule 200b can be used by networks in which it may be desirable to have wireless nodes capable of receiving multiple transmissions simultaneously, but only capable of transmitting on a single channel at a time. This can increase capacity while minimizing power consumption for the wireless nodes that have to transmit the ACKs in that the wireless nodes can include a single, low power narrowband radio transmitter.

<FIG> is a block diagram illustrating an example transceiver circuit <NUM> for a wireless node capable of multi-channel transmission and reception using a single antenna <NUM>. The transceiver circuit <NUM> includes digital signal processing circuits 304a and 304b, a wideband radio receiver circuit <NUM>, and a wideband radio transmitter circuit <NUM>. A control and memory circuit <NUM> can be connected to provide data to the digital signal processor 304b and receive data from the digital signal processor 304a. The data can be provided and received as a baseband signal, such as through a stream of data bits.

The wideband radio receiver circuit <NUM> is configured to receive transmissions through the antenna <NUM>. These transmissions can include data from multiple wireless nodes simultaneously on separate channel frequencies. The wideband radio receiver circuit <NUM> may be configured to receive a wideband signal through the antenna <NUM> and convert the signal into a digital signal for the digital signal processor 304a. In an example, the wideband receiver circuit <NUM> can be configured to convert the received signal into wideband digital in-phase and quadrature (IQ) signals.

The digital signal processor 304a may be configured to generate baseband signals from the received wideband digital signals. For example, the digital signal processor 304a can receive wideband IQ signals, and convert the wideband IQ signals into separate baseband signals for each transmission received. In an example, the control and memory circuit <NUM> may provide control to the digital signal processor 304a indicating which frequency channels are used for a current timeslot. The digital signal processor 304a may use the channel information to extract the baseband signals from the wideband digital signals. The baseband signals can then be provided to the control and memory circuit <NUM>.

In the example illustrated in <FIG>, the transceiver circuit <NUM> can transmit ACKs simultaneously for the received data transmissions. The control and memory circuit <NUM> can provide the acknowledgement baseband signals along with transmission channel information, for example, to the digital signal processor 304b. The digital signal processor 304b can modulate the digital ACK data on multiple carriers for respective transmission frequency channels and combine the multiple carriers into a digital wideband signal, for example. In an example, the digital wideband signal can be a digital IQ signal.

The wideband radio transmitter circuit <NUM> may convert the digital wideband signal into an analog wideband signal. In an example, the wideband transmitter circuit <NUM> can then shift and combine the wideband analog IQ signals to generate an output signal that includes the data for multiple ACKs. The output signal can then be transmitted through the antenna <NUM>. This way, a wireless node that includes the transceiver circuit <NUM> can receive multiple data transmissions simultaneously and provide multiple ACKs simultaneously and can therefore implement a transmission schedule such as that illustrated in <FIG>, for example.

The control and memory circuit <NUM> can include one or more application-specific or general-purpose processor circuits. Such circuits can include system-on-chip (SoC) realization or such circuits can be field-programmable. The control and memory circuit <NUM> can also include one or more volatile or non-volatile memories. For example, the control and memory circuit <NUM> can include one or more non-volatile memories including read-only memories (ROMs), flash memories, solid state drives, or any other non-volatile memory, and one or more volatile memories including, for example, static or dynamic random-access memories (RAM). The control and memory circuit <NUM> can implement network management and a protocol stack, for example, for a network within which a respective wireless node belongs.

<FIG> is a diagram illustrating an example digital signal processor 400a for a receiver circuit of a wireless node, such as the digital signal processor 304a illustrated in <FIG>. The digital signal processor 400a includes interface <NUM>, demodulation circuits 404a-404n, and digital downconverter circuits 406a-406n. The digital signal processor 400a receives a digital signal <NUM>, for example, from a radio receiver circuit. The digital signal <NUM> may be a wideband digital signal, such as a wideband digital IQ signal, for example. The digital signal processor 400a outputs a signal <NUM> that can include, for example, digital baseband information. The digital signal processor 400a can include additional or alternative components to achieve any additional or alternative desirable behavior.

The digital signal <NUM> can be received by respective digital downconverter circuits 406a-406n. The number of digital downconverters 406a-406n can be selected based on how many channels a respective wireless node may desire to receive simultaneous communication. In another example, the digital signal processor circuit 400a can include as many digital downconverters 406a-406n as there are communication channels for the network such that the digital signal processor circuit 400a does not need to know which channels are currently being used.

Each digital downconverter circuit 406a-406n can include respective mixers and respective oscillators. The oscillators can be digital local oscillators (DLO) or numerically controlled oscillators (NCO), for example, tuned to a frequency indicative of, or otherwise corresponding to, a respective channel. The frequency/channel can be programmable, for example, by a respective control circuit of the respective wireless node, such that the digital signal processor 400a can handle communication on different channels for each timeslot of a TSCH schedule, for example. The demodulation circuits 404a-404n can then be used to demodulate the signals to recover the original data of the data transmissions, which can be provided to the control and memory circuit through the interface <NUM>.

<FIG> is a diagram illustrating an example digital signal processor 400b for a transmitter circuit of a wireless node, such as the digital signal processor 304b illustrated in <FIG>. The digital signal processor 400b includes interface <NUM>, modulation circuits 422a-422n, digital upconverter circuits 424a-424n, and adder <NUM>. The digital signal processor 400b receives baseband information <NUM> from a control circuit, for example, for transmission. The digital signal processor 400b outputs a digital signal <NUM> to a radio transmitter circuit, for example. The digital signal <NUM> may be a wideband digital signal, such as a wideband digital IQ signal, for example. The digital signal processor 400b can include additional or alternative components to achieve any additional or alternative desirable behavior.

The digital data <NUM> from the control circuit can be modulated by respective modulation circuits 422a-422n. The modulation circuits 422a-422n can be configured to modulate the digital data <NUM> using any desirable modulation scheme. In an example, the modulation circuits 422a-422n are configured to modulate respective data onto respective carriers for simultaneous transmission. The modulated data may be provided to a respective digital upconverter circuit 424a-424n. The number of digital upconverters 424a-424n can be selected based on how many channels a respective wireless node may desire to transmit simultaneous communication. The digital upconverters 424a-424n may receive control signals from a control and memory circuit, for example, indicative of respective frequency channels for the data communications.

Each digital upconverter circuit 424a-424n can include respective mixers and respective oscillators. The oscillators can be digital local oscillators (DLO) or numerically controlled oscillators (NCO), for example, tuned to a frequency indicative of, or otherwise corresponding to, a respective channel. The frequency/channel can be programmable, for example, by a respective control circuit of the respective wireless node, such that the digital signal processor 400a can handle communication on different channels for each timeslot of a TSCH schedule, for example. The adder <NUM> can then be used to sum the signals from each digital upconverter circuit 424a-424n to provide a digital wideband IQ signal <NUM> as output, for example, to a respective wideband radio transmitter circuit.

<FIG> are diagrams illustrating example radio receiver and transmitter circuits, respectively. <FIG> is a diagram illustrating an example radio receiver circuit 500a, such as the radio receiver circuit <NUM> of <FIG>. The radio receiver circuit 500a includes analog-to-digital converters (ADCs) 502a and 502b, filters 504a and 504b, phase shift circuit <NUM>, and filter and amplifier circuit <NUM>. The radio receiver circuit 500a receives a signal <NUM> through an antenna. The signal <NUM> may be a wideband signal, for example. The filter and amplifier circuit <NUM> can include a low noise amplifier (LNA), for example and one or more filters to condition the received signal <NUM>.

The phase shift circuit <NUM> may be configured to shift the received signal <NUM> into analog quadrature and in-phase (IQ) signals. The ADCs 502a and 502b are configured to convert the analog IQ signals into digital IQ data for a respective digital signal processing circuit, such as the digital signal processing circuit 400a illustrating in <FIG>. The radio receiver circuit 500a can include additional or alternative components to achieve any additional or alternative desirable behavior.

<FIG> is a diagram illustrating an example radio transmitter circuit 500b, such as the radio transmitter circuit <NUM> of <FIG>. The radio transmitter circuit 500b includes digital-to-analog converters (DACs) 522a and 522b, filters 524a and 524b, phase shift circuit <NUM>, and filter and amplifier circuit <NUM>. The radio transmitter circuit 500a may receive a signal <NUM> from a digital signal processing circuit, for example, such as the digital signal processor 400b illustrated in <FIG>. The signal <NUM> may be a digital wideband signal, for example, such as digital wideband IQ signals. The filter and amplifier circuit <NUM> can include a power amplifier (PA), for example, and various filters to condition the signal <NUM> for transmission through an antenna.

The DACs may be configured to convert the digital signal <NUM> into an analog signal, such as a wideband analog IQ signal. The phase shift circuit <NUM> may be configured to shift the analog IQ signals into phase and sum the in-phase signals to generate the output signal <NUM>. The output signal <NUM> is amplified and conditioned by the filter and amplifier circuit <NUM> for transmission through an antenna, for example. The radio transmitter circuit 500b can include additional or alternative components to achieve any additional or alternative desirable behavior.

<FIG> are block diagrams illustrating example transceiver circuits for use by wireless nodes implementing the transmission schedules of <FIG> and <FIG>. <FIG> is a block diagram illustrating an example transceiver circuit 600a for a wireless node capable of single-channel transmission and multi-channel reception using a single antenna <NUM>. The transceiver circuit 600a includes a digital signal processing circuit <NUM>, a wideband radio receiver circuit <NUM>, and a narrowband radio transmitter circuit <NUM>. A control and memory circuit <NUM> can be connected to provide data to the narrowband radio transmitter circuit <NUM> and receive data from the digital signal processor <NUM>. The data can be provided and received as a baseband signal, such as through a stream of data bits. The control and memory circuit <NUM> may be similar to the control and memory circuit <NUM> illustrated in <FIG>.

The wideband radio receiver circuit <NUM> is configured to receive transmissions through the antenna <NUM>. These transmissions can include data from multiple wireless nodes simultaneously on separate channel frequencies. The wideband radio receiver circuit <NUM> may be configured similar to the radio receiver circuit 500a to receive a wideband signal through the antenna <NUM> and convert the signal into a digital signal for the digital signal processor <NUM>. In an example, the wideband receiver circuit <NUM> can be configured to convert the received signal into wideband digital in-phase and quadrature (IQ) signals.

The digital signal processor <NUM> may be configured similar to the digital signal processor 400a to generate baseband signals from the received wideband digital signals. For example, the digital signal processor <NUM> can receive wideband IQ signals, and convert the wideband IQ signals into separate baseband signals for each transmission received. In an example, the control and memory circuit <NUM> may provide control to the digital signal processor <NUM> indicating which frequency channels are used for a current timeslot. The digital signal processor <NUM> may use the channel information to extract the baseband signals from the wideband digital signals. The baseband signals can then be provided to the control and memory circuit <NUM>.

In the example illustrated in <FIG>, the transceiver circuit 600a can transmit ACKs one at a time for the received data transmissions, such as is illustrated in <FIG>. The control and memory circuit <NUM> can provide the acknowledgement data bit stream to the narrowband radio transmitter circuit <NUM>. The narrowband radio transmitter circuit <NUM> can be implemented similarly to the radio transmitter circuit 500b, but may include a modulation circuit. The narrowband radio transmitter circuit <NUM> may modulate the data bit stream to generate a narrowband IQ signal, for example, which can be conditioned and transmitted through the common antenna <NUM>. This way, a wireless node that includes the transceiver circuit 600a can receive multiple data transmissions simultaneously and provide staggered ACKs and can therefore implement a transmission schedule such as that illustrated in <FIG>, for example.

<FIG> is a block diagram illustrating an example transceiver circuit 600b for a wireless node capable of multi-channel transmission and reception using multiple antennas 622a and 622b. The transceiver circuit 600b includes narrowband radio receiver circuits 624a and 624b, and narrowband radio transmitter circuits 626a and 626b. A control and memory circuit <NUM> can be connected to provide data to the narrowband radio transmitter circuits 626a and 626b, and receive data from the narrowband radio receiver circuits 624a and 624b. The data can be provided and received as a baseband signal, such as through a stream of data bits. The control and memory circuit <NUM> may be similar to the control and memory circuit <NUM> illustrated in <FIG>.

The narrowband radio receiver circuits 624a and 624b are configured to receive transmissions through the respective antennas 622a and 622b. These transmissions can include data from separate nodes simultaneously on separate channel frequencies. For example, the narrowband radio receiver circuit 624a may be configured to receive data communication through the antenna 622a on a first channel frequency and the narrowband radio receiver circuit 624b may be configured to receive data communication through the antenna 622b on a second channel frequency to allow simultaneous data reception.

In the example illustrated in <FIG>, the transceiver circuit 600b can transmit ACKs simultaneously, such as is illustrated in <FIG>. The control and memory circuit <NUM> can provide the acknowledgement data bit streams to the respective narrowband radio transmitter circuits 626a and 626b. The narrowband radio transmitter circuit 626a can modulate the data bit stream for the first ACK to generate a narrowband IQ signal, for example, which can be conditioned and transmitted through the common antenna 622a, and the narrowband radio transmitter circuit 626b can modulate the data bit stream for the second ACK to generate a narrowband IQ signal, for example, which can be conditioned and transmitted through the common antenna 622b. This way, a wireless node that includes the transceiver circuit 600b can receive multiple data transmissions simultaneously and provide multiple ACKs simultaneously and can therefore implement a transmission schedule such as that illustrated in <FIG>, for example.

<FIG> is a block diagram illustrating an example transceiver circuit 600c for a wireless node capable of multi-channel transmission and reception using multiple antennas 642a and 642b. The transceiver circuit 600c includes digital signal processing circuits 644a and 644b, wideband radio receiver circuits 646a and 646b, and wideband radio transmitter circuits 648a and 648b. A control and memory circuit <NUM> can be connected to provide data to the digital signal processing circuit 644b, and receive data from the digital signal processing circuit 644b. The data can be provided and received as a baseband signal, such as through a stream of data bits. The control and memory circuit <NUM> may be similar to the control and memory circuit <NUM> illustrated in <FIG>.

The wideband data reception and transmission can be similar to that illustrated and described for <FIG>. In the example illustrated in <FIG>, the control and memory circuit <NUM> can employ antenna diversity to redundantly receive the same data and select the best signal for a respective frequency channel. Thus, a wireless node employing the transceiver circuit 600c can employ a schedule such as the schedule 200a illustrated in <FIG>, and can increase the reliability of the system by employing antenna diversity.

The above description includes references to the accompanying drawings, which form a part of the detailed description.

Claim 1:
A system for increasing capacity and throughput in a wireless network, the system comprising:
a plurality of wireless nodes (104a-104b, 106a-<NUM>) configured to communicate wirelessly with one another on respective frequency channels according to a schedule, wherein the schedule comprises pre-defined timeslots, wherein the plurality of wireless nodes (104a-104b, 106a-<NUM>) comprise a plurality of transmitting wireless nodes (106a-<NUM>) for generating transmissions and at least one receiving wireless node (104a-104b), the at least one receiving wireless node (104a-104b) comprising a receiver circuit (<NUM>) configured to receive the transmissions from the plurality of transmitting wireless nodes (106a-<NUM>) and a transmitter circuit (<NUM>) configured to generate acknowledgment packets (<NUM>) for the plurality of transmitting wireless nodes upon receipt of the transmissions (<NUM>);
wherein during a pre-defined timeslot of the schedule:
first and second transmitting wireless nodes (106a-<NUM>) are configured to generate transmissions (<NUM>) for a first receiving wireless node (104a-104b);
the receiver circuit (<NUM>) of the first receiving wireless node (104a-104b) is configured to receive the transmissions (<NUM>) from the first and the second transmitting wireless nodes (106a-<NUM>) simultaneously and on separate frequency channels; and
the transmitter circuit (<NUM>) of the first receiving wireless node (104a-104b) is configured to generate and transmit acknowledgement packets (<NUM>) to the first and the second transmitting wireless nodes (106a-<NUM>),
characterized in that
the acknowledgment packets (<NUM>, <NUM>) are transmitted to the first and the second transmitting wireless nodes (106a-<NUM>) in subsequent time periods of the respective pre-defined timeslot; and
the system being further characterized in that the transmitter circuit (<NUM>) of the first receiving wireless node (104a-104b) is configured to transmit on a single channel at a time.