Patent Description:
Currently, embedded spin-transfer torque (STT) MRAM (eMRAM) is considered a practical replacement for eFlash memory owing to its application and ease of use. Typical problems associated with eFlash, such as endurance and power consumption difficulties (at <NUM> and lower-process), can be avoided with STT-MRAM's seamless inclusion with CMOS, and its voltage schemes. STT-MRAM can be integrated with as few as three additional masks, while eFlash typically requires six to eight additional masks. eMRAM may also simplify hardware and software designs, improve energy efficiency, enhance form factor, and reduce costs of IoT devices simultaneously. However, due to eMRAM's data retention requirements, a high Eb (i.e., the energy barrier between P and AP stable states of the magnetic tunnel junction cell) is needed to preserve data reliability. This may cause undesirably long write times that may particularly affect high speed applications.

MRAM architectures with voltage-controledd magentic anisotropy controlled MTJs similar to those of the present invention are disclosed in <CIT>, <CIT>, <NPL>, <NPL>, and <NPL>.

Shortcomings of the prior art are overcome and additional advantages are provided through the provision of a memory device that includes a plurality of MTJ pillars, each MTJ pillar is located below a top electrode and above a bottom electrode for forming an MRAM array, the bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, the top electrode is disposed above each MTJ pillar and surrounded by a second dielectric spacer, a bottom metal plate is disposed on opposing sides of the bottom electrode between a first dielectric layer and a second dielectric layer, the bottom metal plate is electrically separated from the bottom electrode by the first dielectric spacer, and a top metal plate on opposing sides of the top electrode between a third dielectric layer and a fourth dielectric layer, the top metal plate is electrically separated from the top electrode by the second dielectric spacer, the top metal plate and the bottom metal plate generating an external electric field to each MTJ pillar for creating a voltage-controlled magnetic anisotropy effect. The top metal plate and the bottom metal plate are each electrically connected to metal contacts. A bias voltage is applied on the top metal plate and the bottom metal plate to generate the external electric field and reduce Eb.

Another embodiment of the present disclosure provides a memory device that includes a first MRAM array including a first MTJ pillar located below a first top electrode and above a first bottom electrode, the first bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, the first top electrode is disposed above the first MTJ pillar and surrounded by a second dielectric spacer, a bottom metal plate on opposing sides of the first bottom electrode between a first dielectric layer and a second dielectric layer, the bottom metal plate is electrically separated from the first bottom electrode by the first dielectric spacer, a top metal plate on opposing sides of the first top electrode between a third dielectric layer and a fourth dielectric layer, the top metal plate is electrically separated from the first top electrode by the second dielectric spacer, the top metal plate and the bottom metal plate locally generating an external electric field to the first MTJ pillar for creating a voltage-controlled magnetic anisotropy effect, and a second MRAM array including a second MTJ pillar located below a second top electrode and above a second bottom electrode, the second bottom electrode is disposed above the substrate and surrounded by the first dielectric spacer, the second top electrode is disposed above the second MTJ pillar and surrounded by the second dielectric spacer. The top metal plate and the bottom metal plate are each electrically connected to metal contacts. A bias voltage is applied on the top metal plate and the bottom metal plate to generate the external electric field and reduce Eb.

Another embodiment of the present disclosure provides a method of forming a memory device that includes forming a first MRAM array on a substrate, the first MRAM array including a first MTJ pillar located below a first top electrode and above a first bottom electrode, the first bottom electrode is disposed above the substrate and surrounded by a first dielectric spacer, the first top electrode is disposed above the first MTJ pillar and surrounded by a second dielectric spacer, a bottom metal plate on opposing sides of the first bottom electrode between a first dielectric layer and a second dielectric layer, the bottom metal plate is electrically separated from the first bottom electrode by the first dielectric spacer, and a top metal plate on opposing sides of the first top electrode between a third dielectric layer and a fourth dielectric layer, the top metal plate is electrically separated from the first top electrode by the second dielectric spacer, the top metal plate and the bottom metal plate locally generating an external electric field to the first MTJ pillar for creating a voltage-controlled magnetic anisotropy effect. The top metal plate and the bottom metal plate are each electrically connected to metal contacts.

The method further includes applying a bias voltage on the top metal plate and the bottom metal plate to generate the external electric field locally for reducing Eb, sending a write current pulse through the first MRAM array using the top electrode and the bottom electrode, and removing the applied bias voltage from the top metal plate and the bottom metal plate to remove the external electric field locally and increase the Eb.

The method further includes forming a second MRAM array on the substrate that includes a second MTJ pillar located below a second top electrode and above a second bottom electrode, the second bottom electrode being disposed above the substrate and surrounded by the first dielectric spacer, the second top electrode being disposed above the second MTJ pillar and surrounded by the second dielectric spacer.

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as "above", "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

STT-MRAM devices are two terminal devices similar to conventional MRAM devices, except that the write current paths pass through the magnetic layers of each memory element. The free layer is set via the spin transfer torque from the spin-polarized current passing through the reference magnetic layer. In an STT-MRAM device, the spin of the electrons is flipped using a spin-polarized current. This effect can be achieved in a magnetic tunnel junction (MTJ) or a spin-valve. The spin-polarized current is created by passing a current through a thin magnetic layer, and then directed into a thinner magnetic layer which transfers the angular momentum to the thin layer which changes its spin. In general, the reference magnetic layer has unchangeable magnetization direction, while the magnetization direction can be changed in the free layer. Therefore, the magnetic field determines the electrical properties of the MTJ. For applications, the conductance difference resulting from the variations of the magnetic field in the ferromagnetic layers is employed. The magnetization orientations (mz) of the two ferromagnetic layers are related to a level of the MTJ resistance: low-resistance (RP) at a parallel state and high-resistance (RAP) at an anti-parallel state. These two stable states of the MTJ can be used to represent logic <NUM> or logic <NUM>.

In STT-MRAMs, the STT effect allows switching the MTJ state by a bidirectional current I when the current is bigger than a critical current Ic0. It improves the scalability of the circuit with MTJs allowing a denser layout and a simpler design due the use of the same line to write and read the MTJ state. However, a drawback of scaling down using STT is that the thermal stability factor (D) scales down linearly with the area and the increase in retention failures due to thermal instability results in unreliable operations. Thus, a high Eb (Eb being the energy barrier between the P and AP stable states of the MTJ cell) is needed to preserve data reliability. This may cause undesirably long write times that may particularly affect high write speed applications since the switching current of STT is inversely proportional to the write pulse width.

Therefore, embodiments of the present disclosure provide an embedded STT-MRAM (eMRAM) memory device, and a method of making the same, in which an external electric field is introduced to the MTJ cell for eFlash replacement. The external electric field utilizes a voltage-controlled magnetic anisotropy (VCMA) effect to reduce the energy barrier (Eb) between AP and P states in the MTJ cell, thus improving the overall MTJ speed. Efficient energy consumption and reduced area can be achieved in the present embodiments by using a voltage-controlled MTJ with an electric field (or a voltage). With the VCMA effect, the electric field is used to switch the MTJ state which occurs by an accumulation of electron charges induced by the electric field changing the occupation of atomic orbitals at the interface. This and the spin-orbit interaction can lead to a change of magnetic anisotropy. Accordingly, embodiments of the present disclosure provides a lower Eb at which the critical current Ic0 can be reduced and the overall MTJ speed can be improved.

More specifically, embodiments of the present disclosure use a top metal plate and a bottom metal plate electrically isolated from the top and bottom electrodes of the MTJ by dielectric materials to introduce the external electric field, thereby generating the VCMA effect on the memory device.

Embodiments by which top and bottom metal plates can be used to generate the VCMA effect and introduce the external electric field to the MTJ cell of the memory device is described in detailed below by referring to the accompanying drawings in <FIG>.

Referring now to <FIG>, a cross-sectional view of a memory device <NUM> at an intermediate step during a back-end-of-the-line (BEOL) integration process is shown, according to an embodiment of the present disclosure. At this step of the manufacturing process the memory device <NUM> includes a simplistically depicted substrate <NUM> containing one or more metal-oxide-semiconductor field-effect transistors (not shown). In this embodiment, the memory device <NUM> can be an embedded STT-MRAM (eMRAM) device.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X is shown after forming a bottom metal plate <NUM>, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>.

In this embodiment, prior to forming the bottom metal plate <NUM>, a first dielectric layer <NUM> is deposited on the memory device <NUM> above the substrate <NUM>. The first dielectric layer <NUM> may include, for example, a low-k dielectric material having a dielectric constant, k, in the range of approximately <NUM> to approximately <NUM>, which may be deposited directly above the substrate <NUM> by any suitable deposition process such as, for example, chemical vapor deposition (CVD). A thickness of the first dielectric layer <NUM> may vary from approximately <NUM> to approximately <NUM> and ranges there between. In an exemplary embodiment, the first dielectric layer <NUM> may have a thickness varying between <NUM> and <NUM>.

After depositing the first dielectric layer <NUM>, the bottom metal plate <NUM> is formed in the memory device <NUM>. The bottom metal plate <NUM> is made of a first conductive material. According to an embodiment, the first conductive material forming the bottom metal plate <NUM> may include metals such as tungsten, tungsten carbide, copper, titanium, titanium nitride, and the like. In some embodiments, the bottom metal plate <NUM> may consist of a multilayer stack including one or more layers of metals.

In an exemplary embodiment, the bottom metal plate <NUM> may have a (vertical) thickness varying from approximately <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application.

With continued reference to <FIG>, a patterning process is conducted on the bottom metal plate <NUM>, as illustrated in <FIG>. The process of patterning the bottom metal plate <NUM> consists of steps well-known in the art, which generally include forming a pattern on a photoresist layer (not shown) that is transferred to a hardmask and used to pattern the underlying bottom metal plate <NUM> via any suitable etching technique. In an exemplary embodiment, an ion beam etch (IBE) or reactive ion etch (RIE) technique may be used to pattern the bottom metal plate <NUM>. As depicted in <FIG>, a first plurality of trenches <NUM> are formed in the bottom metal plate <NUM> after completing the patterning process.

After patterning the bottom metal plate <NUM>, a second dielectric layer <NUM> is formed on the memory device <NUM> above the bottom metal plate <NUM>, as depicted in <FIG>. The second dielectric layer <NUM> may include similar materials and may be formed in analogous ways as the first dielectric layer <NUM> (<FIG>) previously described. A thickness of the second dielectric layer <NUM> may vary from approximately <NUM> to approximately <NUM> and ranges there between, , although other thicknesses above or below this range may be used as desired for a particular application.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> after forming first via openings <NUM> is shown, according to an embodiment of the present disclosure. The first via openings <NUM> are formed to electrically connect the memory device <NUM> to subsequently formed conductive structures.

As known by those skilled in the art, the process of forming the first via openings <NUM> in the memory device <NUM> includes depositing a photoresist layer (not shown) above the second dielectric layer <NUM>, exposing a pattern on the photoresist layer, and transferring the exposed pattern to the underlying first dielectric layer <NUM>, bottom metal plate <NUM> and second dielectric layer <NUM> to form the first via openings <NUM>, as depicted in the figure. After transferring the pattern and forming the first via openings <NUM>, the photoresist layer can be removed using any photoresist striping method known in the art including, for example, plasma ashing.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X is shown after forming first dielectric spacers <NUM> and bottom electrode <NUM>, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>.

The first dielectric spacers are formed within the first via openings <NUM> (<FIG>). The first dielectric spacers <NUM> may be made from an insulator material such as an oxide, nitride, oxynitride, silicon carbon oxynitride, silicon boron oxynitride, low-k dielectric, or any combination thereof. Standard deposition and etching techniques may be used to form the first dielectric spacers <NUM>. As known by those skilled in the art, the deposited insulator material is removed from all horizontal surfaces of the memory device <NUM> using, for example, an anisotropic etch. According to an embodiment, a (horizontal) thickness of the first dielectric spacers <NUM> may vary between approximately <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application.

With continued reference to <FIG>, after forming the first dielectric spacers <NUM>, the bottom electrode <NUM> may be deposited on the memory device <NUM> using standard deposition methods. The conductive material forming the bottom electrode <NUM> is deposited on a remaining space within the first dielectric spacers <NUM>. Exemplary deposition processes that can be used to form the bottom electrode <NUM> may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and the like. The bottom electrode <NUM> is formed above the electrically conductive structures (not shown) in the substrate <NUM> substantially filling a space between the first dielectric spacers <NUM>, as depicted in the figure. In an exemplary embodiment, the bottom electrode <NUM> may be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or any combination thereof.

After forming the bottom electrode <NUM>, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove excess (overfill) portions of the conductive material forming the bottom electrode <NUM> from the memory device <NUM>. After the planarization process, top surfaces of the bottom electrode <NUM> and the second dielectric layer <NUM> are substantially coplanar.

As depicted in the figures, the first dielectric spacers <NUM> surround the bottom electrode <NUM>. Thus, the first dielectric spacers <NUM> electrically separate the bottom electrode <NUM> from the bottom metal plate <NUM>. Similarly, the first dielectric layer <NUM> electrically separates the bottom metal plate <NUM> from the substrate <NUM>, while the second dielectric layer <NUM> electrically separates the bottom metal plate <NUM> from subsequently formed conductive structures.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X after depositing an MRAM stack <NUM> is shown, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>.

According to an embodiment, the MRAM stack <NUM> is formed above the bottom electrode <NUM>. The MRAM stack <NUM> may include an MTJ pillar consisting of, at least, a magnetic reference layer <NUM>, a tunnel barrier layer <NUM>, and a magnetic free layer <NUM>. The MRAM stack <NUM> may further include a conductive hardmask layer <NUM> located above the MTJ pillar and a patterning hardmask layer <NUM> located above the conductive hardmask layer <NUM>, as depicted in <FIG>. It should be noted that other MTJ configurations are possible for the MTJ pillar of the MRAM stack <NUM> such as, for example, the magnetic free layer <NUM> being located at the bottom of the MTJ pillar and the magnetic reference layer <NUM> being at the top of the MTJ pillar. The various material layers of the MRAM stack <NUM> can be formed by utilizing one or more deposition processes such as, for example, plating, sputtering, plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

The magnetic reference layer <NUM> has a fixed magnetization. The magnetic reference layer <NUM> may be composed of a metal or metal alloy (or a stack thereof) that includes one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for the formation of the magnetic reference layer <NUM> may include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified by the above. In another embodiment, the magnetic reference layer <NUM> may be a multilayer arrangement having (<NUM>) a high spin polarization region formed from a metal and/or metal alloy using the metals mentioned above, and (<NUM>) a region constructed of a material or materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that may be used include a metal such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. The strong PMA region may also include alloys that exhibit strong PMA, with exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and/or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed.

The tunnel barrier layer <NUM> is composed of an insulator material and is formed at such a thickness as to provide an appropriate tunneling resistance. Exemplary materials for the tunnel barrier layer <NUM> may include magnesium oxide, aluminum oxide, and titanium oxide, or materials of higher electrical tunnel conductance, such as semiconductors or low-bandgap insulators.

The magnetic free layer <NUM> may be composed of a magnetic material (or a stack of magnetic materials) with a magnetization that can be changed in orientation relative to the magnetization orientation of the magnetic reference layer <NUM>. Exemplary magnetic materials for the magnetic free layer <NUM> include alloys and/or multilayers of cobalt, iron, alloys of cobalt-iron, nickel, alloys of nickel-iron, and alloys of cobalt-iron-boron.

It should be noted that some elements and/or features of the memory device <NUM> are illustrated in the figures but not described in detail in order to avoid unnecessarily obscuring the presented embodiments.

With continued reference to <FIG>, the conductive hardmask layer <NUM> includes a metallic hardmask typically required to protect the MRAM stack <NUM> during subsequent etching steps. In an exemplary embodiment, the conductive hardmask layer <NUM> may be composed of metals such as TaN, TaAlN, WN, and TiN.

According to an embodiment, the patterning hardmask layer <NUM> located above the conductive hardmask layer <NUM> can be made of a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, and the like), multiple layers of dielectric materials, and/or an organic planarization layer (OPL). The conductive hardmask layer <NUM> and the patterning hardmask layer <NUM> can be formed by any suitable deposition method known in the art. It should be noted that the conductive hardmask layer <NUM> is not sacrificial, while the patterning hardmask layer <NUM> is sacrificial, in that the patterning hardmask layer <NUM> will be removed after completion of the patterning process.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X is shown after patterning of the MRAM stack <NUM>, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>. As can be observed in the figures, the patterned MRAM stack <NUM> is disposed above the bottom electrode <NUM> in a way such that a top surface of the bottom electrode <NUM> contacts a central portion of a bottom surface of the MRAM stack <NUM>.

The process of patterning the MRAM stack <NUM> consists of steps well-known in the art, which generally include forming a pattern on a photoresist layer (not shown) that is transferred to the patterning hardmask layer <NUM> and used to pattern the underlying MTJ pillar and conductive hardmask layer <NUM> via any suitable etching technique. In an exemplary embodiment, an ion beam etch (IBE) technique may be used to pattern the MRAM stack <NUM>. After patterning the MRAM stack <NUM>, recesses <NUM> are formed in the memory device <NUM>. The recesses <NUM> extend through a first (top) portion of the second dielectric layer <NUM>. As depicted in <FIG>, a second portion of the second dielectric layer <NUM> remains above the bottom metal plate <NUM> between the patterned MRAM structures. In this embodiment, the patterning hardmask layer <NUM> is removed after patterning the MRAM stack <NUM> using any suitable etching technique.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> after forming second dielectric spacers <NUM> and depositing a third dielectric layer <NUM> is shown, according to an embodiment of the present disclosure.

According to an embodiment, the second dielectric spacers <NUM> are formed within the recesses <NUM> (<FIG>) followed by the deposition of the third dielectric layer <NUM>. The third dielectric layer <NUM> substantially fills a remaining space within the recesses <NUM> (<FIG>) and extends over a top surface of the conductive hardmask layer <NUM>, as shown in the figure. The third dielectric layer <NUM> electrically separates the conductive hardmask layer <NUM> and underlying MTJ layers from subsequently formed electrically conductive structures.

In an exemplary embodiment, the second dielectric spacers <NUM> are made of the same or similar materials and formed in analogous ways as the first dielectric spacers <NUM> described above with reference to <FIG>. Similarly, the third dielectric layer <NUM> is made of similar materials and form in analogous ways as the first and second dielectric layers <NUM>, <NUM> described above with reference to <FIG>. In some embodiments, after forming the third dielectric layer <NUM>, a planarization process can be conducted on the memory device <NUM>.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X is shown after deposition and patterning of a top metal plate <NUM>, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>. The top metal plate <NUM> is formed above the third dielectric layer <NUM>, as depicted in <FIG>. The top metal plate <NUM> is made of a second conductive material similar to the first conductive material forming the bottom metal plate <NUM> described above with reference to <FIG>.

In an exemplary embodiment, the top metal plate <NUM> may have a (vertical) thickness varying from <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application.

According to an embodiment, a patterning process is conducted on the top metal plate <NUM>, as illustrated in <FIG>. The process of patterning the top metal plate <NUM> consists of steps well-known in the art, which generally include forming a pattern on a photoresist layer (not shown) that is transferred to a hardmask (not shown) and used to pattern the underlying top metal plate <NUM> via any suitable etching technique. In an exemplary embodiment, an ion beam etch (IBE) or reactive ion etch (RIE) technique may be used to pattern the top metal plate <NUM>. As depicted in <FIG>, a second plurality of trenches <NUM> are formed in the top metal plate <NUM> after completing the patterning process.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> is shown after depositing a fourth dielectric layer <NUM> and forming second via openings <NUM>, according to an embodiment of the present disclosure.

After patterning the top metal plate <NUM>, a fourth dielectric layer <NUM> is formed on the memory device <NUM> above the top metal plate <NUM>. In an embodiment, the fourth dielectric layer <NUM> substantially fills the second plurality of trenches <NUM> shown in <FIG>. The fourth dielectric layer <NUM> may include similar materials and may be formed in analogous ways as the first, second and third dielectric layers <NUM>, <NUM> and <NUM> previously described. As known by those skilled in the art, the process of forming the second via openings <NUM> in the memory device <NUM> includes depositing a photoresist layer (not shown) above the second dielectric layer <NUM>, exposing a pattern on the photoresist layer, and transferring the exposed pattern to the underlying fourth dielectric layer <NUM>, top metal plate <NUM> and third dielectric layer <NUM> to form the second via openings <NUM>, as depicted in the figure. After transferring the pattern and forming the second via openings <NUM>, the photoresist layer can be removed using any photoresist striping method known in the art including, for example, plasma ashing. As shown in <FIG>, the second via openings <NUM> expose a top surface of the conductive hardmask layer <NUM>.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X is shown after forming third dielectric spacers <NUM> and top electrode <NUM>, according to an embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>.

Similar to the first dielectric spacers <NUM> (<FIG>), the third dielectric spacers <NUM> are formed within the second via openings <NUM> (<FIG>) using methods well-known in the art. After forming the third dielectric spacers <NUM>, the top electrode <NUM> is formed in a remaining space within the second via openings <NUM> (<FIG>). The third dielectric spacers <NUM> may be formed using similar techniques and materials as in the first dielectric spacers <NUM> (<FIG>). As known by those skilled in the art, the deposited insulator material forming the third dielectric spacers <NUM> can be removed from all horizontal surfaces of the memory device <NUM> using, for example, an anisotropic etch.

According to an embodiment, a (horizontal) thickness of the third dielectric spacers <NUM> may vary between approximately <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application.

Similar to the bottom electrode <NUM> (<FIG>), the top electrode <NUM> may be deposited on the memory device <NUM> using standard deposition methods. For example, a chemical vapor deposition (CVD) process can be used to form the top electrode <NUM>. In an embodiment, the top electrode <NUM> may be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or any combination thereof.

As illustrated in <FIG>, the third dielectric spacers <NUM> surround the top electrode <NUM>. Thus, the third dielectric spacers <NUM> electrically separate the top electrode <NUM> from the top metal plate <NUM>.

At this step of the manufacturing process, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove excess (overfill) portions of the conductive material forming the top electrode <NUM> from the memory device <NUM>.

Thus, by forming the top metal plate <NUM> and the bottom metal plate <NUM> in isolation from the top and bottom electrodes <NUM>, <NUM> of the MRAM array, an external electric field is introduced to the MTJ cell of the MRAM, thereby generating the VCMA effect on the memory device <NUM> for reducing the energy barrier (Eb) between AP and P states of the MTJ cell and improving the overall MTJ speed.

It should be noted that the top metal plate <NUM> and the bottom metal plate <NUM> are each electrically connected to (independent) metal contacts (not shown). In some embodiments, the metal contacts may include external metal contacts located outside of the MRAM array. In other embodiments, the metal contacts can be located within the MRAM array region. As may be known by those skilled in the art, when the top metal plate <NUM> and the bottom metal plate <NUM> are not connected to the metal contacts (not shown), they would not be functional and the electric field cannot be generated between the top metal plate <NUM> and the bottom metal plate <NUM>.

Accordingly, embodiments of the present disclosure provide a sequence of operations for a write function that includes: <NUM>) applying a bias voltage on the top metal plate <NUM> and the bottom metal plate <NUM> to generate an external electric field locally for reducing Eb; <NUM>) sending a write current pulse through the MRAM junction using the top electrode <NUM> and the bottom electrode <NUM>; and <NUM>) removing the applied bias voltage from the top metal plate <NUM> and the bottom metal plate <NUM> to remove the external electric field locally and increase Eb back for enhanced magnetic state stability and increased retention time.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> across line X-X after contact metallization is shown, according to another embodiment of the present disclosure. In this embodiment, <FIG> is a top-down view of the memory device <NUM>.

Specifically, <FIG>, depict a region of the memory device <NUM> in which the top metal plate <NUM> and the bottom metal plate <NUM> are not integrated in the MRAM array. Thus, additionally or alternatively, the memory device <NUM> may have one or more MRAM arrays including the top metal plate <NUM> and the bottom metal plate <NUM>, for example, for eFLASH replacement (as described above), while other MRAM arrays on the same chip may not include the top metal plate <NUM> and the bottom metal plate <NUM>.

Claim 1:
A memory device, comprising:
a plurality of MTJ pillars, each MTJ pillar located below a top electrode and above a bottom electrode comprising an MRAM array, the bottom electrode being disposed above a substrate and surrounded by a first dielectric spacer, the top electrode being disposed above each MTJ pillar and surrounded by a second dielectric spacer;
a bottom metal plate on opposing sides of the bottom electrode between a first dielectric layer and a second dielectric layer, the bottom metal plate being electrically separated from the bottom electrode by the first dielectric spacer; and
a top metal plate on opposing sides of the top electrode between a third dielectric layer and a fourth dielectric layer, the top metal plate being electrically separated from the top electrode by the second dielectric spacer, the top metal plate and the bottom metal plate generating an external electric field to each MTJ pillar for creating a voltage-controlled magnetic anisotropy effect.