Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM), among others.

Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

Memory can be part of a memory system used in computing devices. Memory systems can include volatile, such as DRAM, for example, and/or non-volatile memory, such as Flash memory, FeRAM, or RRAM, for example.

Patent document <CIT> forms part of the relevant background art and discloses a semiconductor integrated circuit device. Patent document <CIT> also forms part of the relevant background art and discloses a semiconductor memory array.

The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can include an array of memory cells and a controller coupled to the array configured to sense a first memory cell based upon a first input associated with the memory cell and a second input and a third input associated with a second memory cell.

In one or more embodiments of the present disclosure, a memory cell can be sensed by applying a signal corresponding to a voltage potential of the memory cell and signals corresponding to complementary voltage potentials of another memory cell to sensing circuitry associated with the memory cell. The another memory cell can be a memory cell that is programmed using two complementary voltage potentials that are stored in different storage elements, such as capacitors of the memory cell (e.g., a two access device/two storage element memory cell such as a two transistor two capacitor (2T2C) memory cell). The sensing circuitry is configured to average the two complementary voltage potentials and compare that average to the voltage potential of the memory cell that is being sensed. The average of the voltage potentials can be the reference voltage for sensing memory cells.

In one or more embodiments of the present disclosure, a first memory cell can be sensed by applying, to sensing circuitry associated with the first memory cell, a signal corresponding to a voltage potential of the first memory cell, a second signal corresponding to a voltage potential of the second memory cell, and a third signal corresponding to a voltage potential of the third memory cell. The second and third voltage potentials are complementary where one of the voltage potentials corresponds to a first data state and the other voltage potential corresponds to a second data state (e.g., two 1T1C memory cells that are operated to obtain one bit of data). The sensing circuitry is configured to average the second and third voltage potentials and compare that average to the voltage potential of the first memory cell that is being sensed. The average of the second and third voltage potentials can be a reference voltage for sensing the first memory cell.

The memory cells that store the voltage potentials that are averaged and used by the sensing circuitry as a reference voltage to sense a particular memory cell can be located within a particular distance of the particular memory cell. For example, the memory cells that store the voltage potentials used as a reference voltage by the sensing circuitry can be coupled to sensing circuitry associated with a group of memory cells, where the group of memory cells include a number of adjacent memory cells. The group of memory cells can include <NUM>, <NUM>, <NUM>, <NUM>,. , etc. memory cells that use voltage potentials, as a reference voltage, from a memory cell (or memory cells) that is adjacent to the group of memory cells.

Sensing memory cells in a group of memory cells using a reference voltage from a memory cell (or memory cells) that is adjacent to the group of memory cells can reduce the effects of temperature and/or memory cell structure variations during sensing operation. Also, sensing memory cells in a group of memory cells using a reference voltage from a memory cell (or memory cells) that is adjacent to the group of memory cells can reduce the time of a sensing operation. For example, a sensing operation can be completed before saturation of the voltage potential associated with a memory cell that is being sensed because changes in magnitude of the reference voltage is proportional to changes in magnitude of the voltage potential associated with the memory cell that is being sensed during a sensing operation. Therefore, the voltage potential of the memory cell that is being sensed can be compared to the reference voltage prior to saturation of the voltage potential associated with the memory cell that is being sensed.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

As used herein, "a number of" something can refer to one or more of such things. For example, a number of memory devices can refer to one or more of memory devices. Additionally, designators such as "N", as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.

As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

<FIG> is a block diagram of an apparatus in the form of a computing system <NUM> including a memory device <NUM> which includes a memory array <NUM> in accordance with a number of embodiments of the present disclosure. As used herein, a memory device <NUM>, controller <NUM>, memory array <NUM>, sensing circuitry <NUM>, and/or wear leveling <NUM>, among other components might also be separately considered an "apparatus.

System <NUM> in <FIG> includes a host <NUM> coupled (e.g., connected) to the memory device <NUM>. Host <NUM> may be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host <NUM> may include a system motherboard and/or backplane and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system <NUM> may include separate integrated circuits or both the host <NUM> and the memory device <NUM> may be on the same integrated circuit. The system <NUM> may be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the examples shown in <FIG> illustrates a system having a Von Neumann architecture, embodiments of the present disclosure may be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system <NUM> has been simplified to focus on features with particular relevance to the present disclosure. The memory array <NUM> may be a 2D array, a 3D array, a FeRAM, a NAND flash array, and/or NOR flash array, among other types of non-volatile memory arrays. The array <NUM> may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although a single array <NUM> is shown in <FIG>, embodiments are not so limited. For instance, memory device <NUM> may include a number of arrays <NUM> (e.g., a number of banks of NAND flash cells, etc.).

The memory device <NUM> may include address circuitry <NUM> to latch address signals provided over a data bus <NUM> (e.g., an I/O bus connected to the host <NUM>) by I/O circuitry <NUM> (e.g., provided to external ALU circuitry via local I/O lines and global I/O lines). As used herein, external ALU circuitry may enable input of data to and/or output of data from a bank (e.g., from and/or to the controller <NUM> and/or host <NUM>) via a bus (e.g., data bus <NUM>).

The channel controller <NUM> may include a logic component to allocate a plurality of locations (e.g., controllers for subarrays) in the arrays of each respective bank to store bank commands, application instructions (e.g., for sequences of operations), and arguments (PIM commands) for various banks associated with operations for each of a plurality of memory devices <NUM>. The channel controller <NUM> may dispatch commands (e.g., PIM commands) to the plurality of memory devices <NUM> to store those program instructions within a given bank (e.g. bank <NUM> in <FIG>) of a memory device <NUM>. In some embodiments, the channel controller <NUM> can be located in the host <NUM>.

Address signals are received through address circuitry <NUM> and decoded by a row decoder <NUM> and a column decoder <NUM> to access the memory array <NUM>. Data may be sensed (read) from memory array <NUM> by sensing voltage and/or current changes on sense lines (digit lines) using a number of sense amplifiers, as described herein, of the sensing circuitry <NUM>. A sense amplifier may read and latch a page (e.g., a row) of data from the memory array <NUM>. Additional compute circuitry, as described herein, may be coupled to the sensing circuitry <NUM> and may be used in combination with the sense amplifiers to sense, store (e.g., cache and/or buffer), perform compute functions (e.g., operations), and/or move data. The I/O circuitry <NUM> may be used for bidirectional data communication with host <NUM> over the data bus <NUM> (e.g., a <NUM> bit wide data bus). The write circuitry <NUM> may be used to write data to the memory array <NUM>.

Controller <NUM> may decode signals (e.g., commands) provided by control bus <NUM> from the host <NUM>. These signals may include chip enable signals, write enable signals, and/or address latch signals that may be used to control operations performed on the memory array <NUM>, including data sense, data store, data movement (e.g., copying, transferring, and/or transporting data values), data write, and/or data erase operations, among other operations. In various embodiments, the controller <NUM> may be responsible for executing instructions from the host <NUM> and/or accessing the memory array <NUM>. The controller <NUM> may be a state machine, a sequencer, or some other type of controller. The controller <NUM> may control sensing data (e.g., reading data) in a row of an array (e.g., memory array <NUM>) and execute microcode instructions to perform operations such as compute operations (e.g., AND, OR, NOR, XOR, add, subtract, multiply, divide, etc.). The controller <NUM> may include wear leveling logic <NUM>. The controller <NUM> may communicate with the wear leveling logic <NUM> to move data as a wear leveling operation between rows and/or between sections to prevent data loss.

Examples of the sensing circuitry <NUM> are described further below (e.g., in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>). For instance, in some embodiments, the sensing circuitry <NUM> may include a number of sense amplifiers. In some embodiments, the sensing circuitry <NUM> may include the number of sense amplifiers and a corresponding number of compute components, which may serve as an accumulator and may be used to perform operations in each subarray (e.g., on data associated with complementary sense lines) in addition to the in data path compute operations described herein.

In some embodiments, the sensing circuitry <NUM> may be used to perform operations using data stored by memory array <NUM> as inputs and participate in movement of the data for copy, transfer, transport, writing, logic, and/or storage operations to a different location in the memory array <NUM> and/or in logic stripes.

<FIG> is a block diagram of a plurality of sections, e.g., sections <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>, of a bank <NUM> of a memory device (e.g. memory device <NUM> in <FIG>) in a computing system (e.g. computing system <NUM> in <FIG>) in accordance with a number of embodiments of the present disclosure. By way of illustration, <FIG> shows a bank section <NUM> of the bank <NUM> of the memory device. For example, bank section <NUM> can represent an example bank section of a number of bank sections of the bank <NUM> of the memory device, e.g., bank section <NUM>, bank section <NUM>,. , bank section M-<NUM> (not shown). As shown in <FIG>, a bank section <NUM> can include a plurality of memory columns <NUM> shown horizontally as X, e.g., <NUM>, <NUM>, or <NUM>,<NUM> columns, among various possibilities, in an example bank section. Additionally, the bank section <NUM> may be divided into section <NUM>, section <NUM>,. , and section N-<NUM>, e.g., <NUM>, <NUM>, or <NUM> sections, among various possibilities, shown at <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>, respectively, that are separated by amplification regions configured to be coupled to a data path. As such, the sections <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> can each have amplification regions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> that correspond to sensing component stripe <NUM>, sensing component stripe <NUM>,. , and sensing component stripe N-<NUM>, respectively.

Each column <NUM>, e.g., single or each pair of sense or digit lines, is configured to be coupled to sensing circuitry (e.g. sensing circuitry <NUM> in <FIG>). As such, each column <NUM> in a section <NUM> can be coupled individually to a sense amplifier that contributes to a sensing component stripe <NUM> for that section. For example, as shown in <FIG>, the bank section <NUM> can include sensing component stripe <NUM>, sensing component stripe <NUM>,. , sensing component stripe N-<NUM> that each have sensing circuitry with sense amplifiers that can, in various embodiments, be used as registers, cache and/or data buffering and that are coupled to each column <NUM> in the sections <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>.

Each of the sections <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM> can include a plurality of rows <NUM> shown vertically as Y, e.g., each section may include <NUM>, <NUM>, <NUM> rows, among various possibilities, in an example bank. Embodiments are not limited to the example horizontal and vertical orientation of columns and rows described herein or the example numbers thereof. Each of the plurality of rows <NUM> can include a single memory cell selectably coupled to each sense line. Each of the complementary memory cells of the pair can be coupled to one of a respective pair of sense lines at a position of the sense lines on the row. As such, the number of memory cells in a row can correspond to the number of sense lines that intersect that row.

As shown in <FIG>, portions of the sensing circuitry, e.g., sense amplifiers, compute components, etc., can be separated between a number of sensing component stripes <NUM> that are each physically associated with a section of memory cells <NUM> in the bank section <NUM>. The sense amplifiers may sense data values stored by memory cells of the sections and/or the sense amplifiers may sense residual voltages on the sense lines as a reference voltage for determination of a sensed data value.

In some embodiments, the sense amplifiers may at least temporarily store, e.g., cache, sensed data values. The compute components described herein in connection with the sense amplifiers may, in some embodiments, perform compute operations on the cached data values in the plurality of sensing component stripes <NUM>.

As shown in <FIG>, the bank section <NUM> can be associated with controller <NUM>. The controller <NUM> shown in <FIG> can, in various embodiments, represent at least a portion of the functionality embodied by and contained in the controller <NUM> shown in and described in connection with <FIG>. The controller <NUM> can direct, e.g., control, input of commands and data <NUM> to the bank section <NUM> and/or output, e.g., movement, of data from the bank section <NUM>.

The bank section <NUM> can include a data bus, e.g., a <NUM> bit wide data bus which can correspond to the data bus <NUM>. Each data bus for each bank of sections, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N-<NUM>, can be referred to as a portion of a data bus that contributes to formation of a combined data bus, e.g., for a plurality of banks and/or memory devices. As such, in some embodiments, eight <NUM> bit wide data bus portions for eight banks can contribute to a <NUM> bit wide combined data bus. However, embodiments are not limited to a particular data bus. Alternatively or in addition, each bank can individually use the entirety of the <NUM> bit wide combined data bus, although one bank at a time. Various combinations of using the data bus portions also may be utilized. For example, one bank may use four data bus portions at the same time as four other banks each use one of the remaining four data bus portions, among other possibilities.

In order to appreciate the performance of operations described herein, a discussion of an apparatus for implementing such techniques follows. For example, such an apparatus may be a memory device having a controller <NUM>, that is on chip with a memory array (e.g. memory array <NUM> in <FIG>) and/or sensing circuitry (e.g. sensing circuitry <NUM> in <FIG>).

<FIG> is a schematic diagram illustrating sections and groups of memory cells in a bank of a memory device in accordance with a number of embodiments of the present disclosure. <FIG> includes sections, e.g., section <NUM> at <NUM>-<NUM>, section <NUM> at <NUM>-<NUM>, section <NUM> at <NUM>-<NUM>, section N-<NUM> at <NUM>-N-<NUM> etc., in a bank of a memory device. Each of the sections includes memory cells coupled to Y rows of access lines <NUM>-<NUM>,. , <NUM>-Y and T columns <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-T of digit lines. Memory cells, indicated by dots in <FIG>, are located at the intersections of the access lines <NUM>-<NUM>,. , <NUM>-Y and digit lines <NUM>-<NUM>,. Each group of memory cells can include a number of one access device/one storage element memory cells (e.g., one transistor two capacitor (1T1C) memory cells) coupled to a first number of digit lines and a number of two access device/two storage element memory cells (e.g., two transistor two capacitor (2T2C) memory cells) coupled to two digit lines. Also, each group of memory cells can include a first number of one access device/one storage element memory cells coupled to a first number of digit lines and a second number of one access device/one storage element memory cells coupled to two digit lines, where the second number of one access device/one storage element memory cells are sensed together to obtain one bit of data.

In <FIG>, group <NUM>-<NUM> includes one access device/one storage element memory cells coupled to three digit lines (e.g., digit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) and two access device/two storage element memory cells coupled to two <NUM> digit lines (e.g., digit lines <NUM>-<NUM> and <NUM>-<NUM>). Groups of digit lines <NUM>-<NUM>,. , <NUM>-T are sensed using the voltage potential stored on the two access device/two storage element memory cells in the group (e.g. the memory cells coupled to digit lines <NUM>-<NUM> and <NUM>-<NUM> in group <NUM>-<NUM>, digit lines <NUM>-<NUM> and <NUM>-<NUM> in group <NUM>-<NUM>, and digit lines <NUM>-X-<NUM> and <NUM>-X in group <NUM>-T). Digit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> coupled to 1T1C memory cells can each be associated with a sense amp and digit lines <NUM>-<NUM> and <NUM>-<NUM> coupled to two access device/two storage element memory cells can be associated with a common sense amp. The one access device/one storage element memory cells can be sense based upon the voltage potential stored in the memory cell and the voltage potential stored in a two access device/two storage element memory cell on a common access line in the group of memory cells.

<FIG> is a schematic diagram illustrating a group of memory cells in accordance with a number of embodiments of the present disclosure. In <FIG>, group <NUM> of memory cells includes memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> and respective access lines <NUM>-<NUM>,. , <NUM>-<NUM>, memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> and respective access lines <NUM>-<NUM>,. , <NUM>-<NUM>, memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> and respective access lines <NUM>-<NUM>,. , <NUM>-<NUM>. Memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM>, memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM>, and memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> can be 1T1C memory cells. Group <NUM> of memory cells also includes memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit lines <NUM>-<NUM> and <NUM>-<NUM> and respective access lines <NUM>-<NUM>,. , <NUM>-<NUM>. Memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> can be 2T2C memory cells.

Memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> are coupled to sense amp <NUM>-<NUM>, memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> are couple to sense amp <NUM>-<NUM>, and memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit line <NUM>-<NUM> are coupled to sense amp <NUM>-<NUM>. Memory cells <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-<NUM> coupled to digit lines <NUM>-<NUM> and <NUM>-<NUM> are coupled each of the sense amps in group <NUM> (e.g., sense amps, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>).

Voltage potentials stored in the memory cells corresponding to a data state can be sensed by the sense amp to determine a data state of a memory cells. In a number of embodiments, a data state of a memory cell can be sensed by inputting a signal corresponding to the voltage potential stored in the memory cell into a sense amp. The signal corresponding to the voltage potential can be compared to voltage potentials of a two access device/two storage element memory cell that is coupled to the sense amp to determine the data state of the memory cell. For example, sensing memory cell <NUM>-<NUM>-<NUM> can include inputting a signal corresponding to the voltage potential stored memory cell <NUM>-<NUM>-<NUM> in input <NUM>-<NUM>-<NUM> of sense amp <NUM>-<NUM>, inputting a signal corresponding to the voltage potential stored memory cell <NUM>-<NUM>-<NUM> in input <NUM>-<NUM>-<NUM> of sense amp <NUM>-<NUM>, inputting a signal corresponding to the voltage potential stored on a first capacitor of memory cell <NUM>-<NUM>-<NUM> in input <NUM> of sense amp <NUM>-<NUM>, and inputting a signal corresponding to the voltage potential stored on a second capacitor of memory cell <NUM>-<NUM>-<NUM> in input <NUM> of sense amp <NUM>-<NUM>. Memory cell <NUM>-<NUM>-<NUM> is a two access device/two storage element memory cell that stores complementary voltage potentials (e.g., one capacitor stores a voltage potential corresponding to a first data state and the other capacitor stores a voltage potential corresponding to a second data state; or vice versa). Memory cell <NUM>-<NUM>-<NUM> can provide a reference voltage for sensing memory cell <NUM>-<NUM>-<NUM> in sense amp <NUM>-<NUM>. Sense amp <NUM>-<NUM> can be configured to average inputs <NUM> and <NUM>, which are inputs from complementary voltage potentials. The average of inputs <NUM> and <NUM> can be used as a reference voltage by sense amp <NUM>-<NUM> for determining a data state of memory cell <NUM>-<NUM>-<NUM>. Inputs <NUM>-<NUM>-<NUM> and <NUM>-<NUM> are compared to inputs <NUM> and <NUM> in sense amp <NUM>-<NUM> to determine a data state of memory cells <NUM>-<NUM>-<NUM>. If inputs <NUM>-<NUM>-<NUM> and <NUM>-<NUM> are less than an average of inputs <NUM> and <NUM>, the memory cell is sensed to be at a first data state. If inputs <NUM>-<NUM>-<NUM> and <NUM>-<NUM> are greater than an average of inputs <NUM> and <NUM>, the memory cell is sensed to be at second data state.

A data state of memory cell <NUM>-<NUM> is determined by inputting a signal corresponding to the voltage potential stored on a first capacitor of memory cell <NUM>-<NUM>-<NUM> in inputs <NUM> of sense amp <NUM>-<NUM> and inputting a signal corresponding to the voltage potential stored on a second capacitor of memory cell <NUM>-<NUM>-<NUM> in inputs <NUM> of sense amp <NUM>-<NUM>. If inputs <NUM> are less than inputs <NUM>, the memory cell is sensed to be at a first data state. If inputs <NUM> are greater than inputs <NUM>, the memory cell is sensed to be at second data state.

Group <NUM> of memory cells can be configured to store and sense, on a given row of memory cells, <NUM> bits of data in memory cells that are coupled <NUM> digit lines. In a number of embodiments, groups of memory cells can be configured to store and sense, on a given row of memory cells, <NUM> less bit of data than the number of digit lines coupled to the memory cells in the group.

<FIG> illustrates a sense amp used to sense a memory cell in accordance with a number of embodiments of the present disclosure. In <FIG>, sense amp <NUM> is configured to sense one access device/one storage element memory cells. Sense amp <NUM> can receive inputs <NUM>-<NUM> and <NUM>-<NUM> that correspond to a voltage potential stored on a one access device/one storage element memory cell. Input <NUM>-<NUM> is coupled to a gate of transistor <NUM>-<NUM> and input <NUM>-<NUM> is coupled to a gate of transistor <NUM>-<NUM>. Sense amp <NUM> can receive complementary inputs from a two access device/two storage element memory cell that can be used as a reference for determining a data state of the memory cell. Sense amp <NUM> can receive input <NUM> that corresponds to a voltage potential stored on a first storage element of a two access device/two storage element memory cell and input <NUM> that corresponds to a voltage potential stored on a second storage element of a two access device/two storage element memory cell. Input <NUM> is coupled to a gate of transistor <NUM>-<NUM> and input <NUM> is coupled to a gate of transistor <NUM>-<NUM>. A source drain region of transistors <NUM>-<NUM> and <NUM>-<NUM> is coupled to a first side of cross coupled latch and a source drain region of transistors <NUM>-<NUM> and <NUM>-<NUM> is coupled to a second side of a cross coupled latch. The cross coupled latch includes NMOS transistors <NUM>-<NUM> and <NUM>-<NUM> and PMOS transistors <NUM>-<NUM> and <NUM>-<NUM>. Sense amp <NUM> can latch a signal that corresponds to a data value in response to inputs <NUM>-<NUM> and <NUM>-<NUM> from the memory cell being sensed and inputs <NUM> and <NUM> from a memory cell providing a reference signal.

<FIG> illustrates a sense amp used to sense a memory cell in accordance with a number of embodiments of the present disclosure. In <FIG>, sense amp <NUM> is configured to sense one access device/one storage element memory cell. Sense amp <NUM> can receive inputs <NUM>-<NUM> and <NUM>-<NUM> that correspond to a voltage potential stored on a one access device/one storage element memory cell. Input <NUM>-<NUM> is coupled to a gate of transistor <NUM>-<NUM> and input <NUM>-<NUM> is coupled to a gate of transistor <NUM>-<NUM>. Sense amp <NUM> can receive complementary inputs from a two access device/two storage element memory cell that can be used as a reference for determining a data state of the memory cell. Sense amp <NUM> can receive input <NUM> that corresponds to a voltage potential stored on a first capacitor of a two access device/two storage element memory cell and input <NUM> that corresponds to a voltage potential stored on a second capacitor of a two access device/two storage element memory cell. Input <NUM> is coupled to a gate of transistor <NUM>-<NUM> and input <NUM> is coupled to a gate of transistor <NUM>-<NUM>. A source drain region of transistors <NUM>-<NUM> and <NUM>-<NUM> is coupled to a first side of cross coupled latch and a source drain region of transistors <NUM>-<NUM> and <NUM>-<NUM> is coupled to a second side of a cross coupled latch. The cross coupled latch includes NMOS transistors <NUM>-<NUM> and <NUM>-<NUM> and PMOS transistors <NUM>-<NUM> and <NUM>-<NUM>. Sense amp <NUM> can latch a signal that corresponds to a data value in response to inputs <NUM>-<NUM> and <NUM>-<NUM> from the memory cell being sensed and inputs <NUM> and <NUM> from a memory cell providing a reference signal.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claim 1:
An apparatus, comprising:
an array of memory cells (<NUM>); and
a controller (<NUM>, <NUM>) coupled to the array configured to:
sense a first memory cell (<NUM>-<NUM>-<NUM>... <NUM>-<NUM>-<NUM>) using a first sense amp (<NUM>-<NUM>), wherein the first memory cell is coupled to a first digit line (<NUM>-<NUM>) and a first access line (<NUM>-<NUM>) and the first sense amp is coupled to the first digit line,
wherein the first sense amp is configured to sense the first memory cell based upon a first input (<NUM>-<NUM>-<NUM>-<NUM>...<NUM>-<NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM> ... <NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM>... <NUM>-<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) associated with the first memory cell and a second input (<NUM>-<NUM>-<NUM>-<NUM>... <NUM>-<NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM> ... <NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM>...<NUM>-<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and a third input (<NUM>-<NUM>-<NUM>-<NUM>...<NUM>-<NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM> ... <NUM>-<NUM>, <NUM>, <NUM>, <NUM>-<NUM>... <NUM>-<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) associated with a second memory cell (<NUM>-<NUM>-<NUM>... <NUM>-<NUM>-<NUM>)
wherein the second memory cell is coupled to a second digit line (<NUM>-<NUM>), a third digit line (<NUM>-<NUM>), and the first access line,
wherein the first input is received by a gate of a first transistor (<NUM>-<NUM>) of the first sense amp and a gate of a second transistor (<NUM>-<NUM>) of the first sense amp via the first digit line, the second input is received by a gate of a third transistor (<NUM>-<NUM>) of the first sense amp via the second digit line, and the third input is received by a gate of a fourth transistor (<NUM>-<NUM>) via the third digit line,
wherein a source drain region of the first transistor and a source drain region of the second transistor is coupled to a source drain region of a fifth transistor (<NUM>-<NUM>),
wherein a source drain region of the third transistor and a source drain region of the fourth transistor is coupled to a source drain region of a sixth transistor (<NUM>-<NUM>), and
wherein the first sense amp includes a cross coupled latch comprising the fifth transistor and the sixth transistor forming a first pair of transistors and a seventh transistor (<NUM>-<NUM>) and an eighth transistor (<NUM>-<NUM>) forming a second pair of transistors.