Patent Description:
A typical FSK/MSK (Frequency Shift Keying / Minimum Shift Keying) I/Q receiver achieves a very good performance at relatively low power consumption. Especially a properly designed digital part has already very low power consumpation which can be further reduced by introduction of smaller process technologies. However, the analog components represent the major power consumption in the receiver and will not benefit from future smaller process technology.

Conventional FSK/MSK I/Q receivers typically require that a complex-valued analog signal is generated from the received real-valued analog input signal in order to recover from the real-valued analog input signal complex-valued information which was originally generated at the transmitter side. For processing the complex-valued analog signal two (analog and digital) processing branches (receive channels) are required.

Work of the presently named inventor(s), to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.

<CIT> discloses a baseband integrated circuit that is configured to: perform division between a first component of a baseband signal modulated by a minimum shift keying scheme and the first component of a predetermined first synchronization word signal; select the division result corresponding to a frequency offset from among a plurality of division results; interpolate the selected division result; and approximate the interpdated division result by a sine wave, and estimate the frequency offset based on an approximated sine wave.

<CIT> discloses a front-end system for a radio device comprising a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator, and characterized in that, said converter further comprises a quantizer arranged for quantizing said baseband signal into a digital signal, and wherein the signal generator is configured for generating, based on said digital signal, said local oscillator signal such that it is synchronized with the radio frequency signal.

It is an object to provide a receiver and a receiving method, especially for frequency modulated signals, having a reduced overall (and especially analog) power consumption. Preferably, the BLE (Bluetooth Low Energy) <NUM> standard specification shall be fulfilled.

It is a further object to provide a corresponding computer program for implementing the single channel receiving method.

According to an aspect there is provided a single channel receiver as defined in claim <NUM>.

According to a further aspect there is provided a single channel receiving method as defined in claim <NUM>.

According to still further aspects a computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method is provided.

It shall be understood that the disclosed method and the disclosed computer program have similar and/or identical further embodiments as the claimed receiver and as defined in the dependent claims and/or disclosed herein.

The present disclosure particularly relates to a single channel receiver for binary frequency shift keying modulation which exploits special properties of the modulation. The complex-valued information which was originally generated at the transmitter side and which is contained in the (real-valued) analog receiver input signal is shifted only, or substantially only, to the real part (or (substantially) only to the imaginary part), so that an intermediate real-valued analog signal containing sufficient information to recover the full bit information in the real (or imaginary) part can be obtained. This is accomplished by mixing the received RF signal to a certain offset frequency. Thus, the complex-valued information contained in the analog receiver input signal can be recovered at the receiver in one single channel. By use of such a single channel approach, i.e., by use of only one receive channel instead of two receive channels as used in conventional FSK/MSK I/Q receivers, the desired power reduction can be achieved due to the reduced number of analog components. The disclosed single channel receiver operates on purely real-valued signals.

The disclosed single channel receiver is a coherent receiver. Phase and/or frequency effects present in the received signal are tracked and compensated by applying a phase tracking loop. It estimates phase errors based on zero-crossing detection. The obtained phase errors may in one embodiment be fed to a loop filter, which obtains the corresponding phase and/or frequency error to be corrected. The phase and/or frequency correction signal may be fed to the oscillator to adjust the mixer phase and frequency correspondingly to compensate the phase- and/or frequency error.

Additionally, synchronization of the transmitter and receiver sample timing is preferred. Especially for reception of long packets, an additional sample timing offset tracking is desired. This is accomplished in an embodiment by a decision directed sample timing tracking loop (also called timing error loop herein), which is based on estimating signal shape distortions related to sample timing offset.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, <FIG> shows a schematic diagram of a first embodiment of a single channel receiver <NUM> (SC RX) according to the present disclosure. It comprises an input terminal <NUM> for receiving an analog input signal <NUM>, in this embodiment an amplifier, e.g. a low noise amplifier (LNA), for amplifying the input signal. A mixer <NUM> down-mixes the (amplified) analog input signal <NUM> by use of a phase- and/or frequency-corrected oscillator frequency signal <NUM> and shifts the complex-valued information contained in the (amplified) analog input signal <NUM> only, or substantially only, to the real part (or, alternatively, to the imaginary part) to obtain an intermediate real-valued analog signal <NUM>. That is, by shifting all the complex-valued information contained in the analog input signal <NUM> to the real (or imaginary) part, all relevant information (the full differential information) is contained in a single component (in the real part or the imaginary part) and can be recovered using a real-valued intermediate analog signal. In contrast, conventional solutions generate a complex-valued intermediate analog signal in order to recover the complex-valued information contained in the analog input signal.

Referring back to <FIG>, an optional analog front end (FE) <NUM> may include for example one or several filter stages and gain stages to properly adjust the intermediate analog signal <NUM> for the analog-to-digital converter (ADC) <NUM>. The ADC <NUM> converts the (adjusted) intermediate analog signal <NUM> into an intermediate digital signal <NUM>. A demodulator <NUM>, preferably a single-channel demodulator (SC DMOD), demodulates the intermediate digital signal <NUM> into a digital output signal <NUM>.

A phase tracking loop <NUM>, in this embodiment comprising a zero-crossing detector (ZCDET) <NUM> and a loop filter (hLoop) <NUM>, detects zero-crossings in the intermediate digital signal <NUM> to obtain phase error information <NUM> representing a phase error in the intermediate digital signal. Finally, a local oscillator (LO) <NUM> generates the phase- and/or frequency-corrected oscillator frequency signal <NUM> by use of the phase error information.

In this embodiment, after the LNA <NUM>, the analog input signal <NUM> is mixed down to a very low intermediate frequency by the single channel RF mixer <NUM>, which shifts all information to the real axis in a signal constellation diagram. After the ADC <NUM>, the intermediate digital signal <NUM> is fed to the single channel demodulator <NUM>, which outputs the final bit decisions as digital output signal <NUM>. Within the single channel demodulator <NUM> a suitable signal (a digital representation of the analog input signal) is fed back via the phase tracking loop <NUM> to the local oscillator <NUM>. For example, the single channel demodulator <NUM> may reduce the frequency of the intermediate digital signal <NUM> in two stages, from an ADC rate at the output of the ADC <NUM> to a signal processing rate after a first stage and to a symbol rate after a second stage. In this case, the intermediate digital signal <NUM> (at ADC rate), or the (processed) intermediate digital signal after the first stage (at signal processing rate), or even the (further processed) intermediate digital signal at symbol rate (which may correspond to the digital output signal <NUM>; but resolution may be rather coarse if a signal at symbol rate is used could be used). In the example of <FIG>, the intermediate digital signal <NUM> at ADC rate is used.

The phase tracking thus adjusts the oscillator's phase in such a way that any detected phase and frequency deviations are de-rotated, e.g. phase offset, frequency drift, etc., so that any phase and frequency errors are tried to be corrected on average. The oscillator phase and frequency is controlled by the phase tracking loop <NUM>, using the estimated phase error as the correcting variable signal.

The disclosed single channel receiver uses a similar architecture as a typical FSK/MSK I/Q receiver to achieve a comparable sensitivity and adjacent channel rejection (ACR) performance. The power reduction is achieved by a single channel approach, i.e. only using one receive channel instead of two. It operates on purely real valued signals.

For single channel reception a coherent receiver concept is used. Therefore, it may be necessary to track the carrier phase and carrier frequency constantly during the whole packet reception. Since a real-valued signal does not have any direct phase information, a new phase error tracking concept is used according to the present disclosure.

In an embodiment, the transmitter and receiver sampling clock offset may be tracked at the receiver as well to guarantee correct reception for long packets. Current I/Q based receivers use an ad-hoc feedback scheme for MSK type modulations, which requires complex signal information. In contrast, an embodiment of the disclosed single channel receiver may use a new approach for timing error tracking.

As mentioned above, to enable single channel reception, the information on symbol rate is shifted fully to one axis in a constellation diagram, i.e. the complex-valued information of the (amplified) analog input signal <NUM> is shifted (substantially) only to the real or imaginary part to obtain the intermediate real-valued analog signal <NUM>. This may be accomplished by an offset mixer scheme as illustrated in <FIG> showing a diagram illustrating the function of the mixer <NUM>.

<FIG> shows the constellation diagram of a received analog input signal at the input of the mixer <NUM>. It also shows the possible signal state transitions for the positive<IMG> constellation point as an example. The binary FSK performs a -<NUM> shift for logic <NUM> and +<NUM> for logic <NUM>, i.e. ∓ π/<NUM> phase rotation on symbol rate. This also means that the signal information rotates between real (I) and imaginary (Q) axis.

<FIG> shows the constellation diagram mixer output and all possible signal transitions. The mixer <NUM> performs a ±<NUM> shift (<FIG> shows a -<NUM> shift), thus the output signal either rotates by ∓π (i.e. double the phase) per symbol or it does not change in phase. As can be seen, the information at the mixer output is shifted to the real axis (I) and consequently can be received using only one single real valued channel. This assumes an already phase synchronized signal, since the initial phase shall start on the real axis in this example.

In an embodiment, after selecting the real part of the mixer output, the signal may be filtered and down converted by several stages, to guarantee a certain frequency selectivity of the system. For instance, at first it may be filtered by an <NUM>-times oversampled IIR filter, representing the overall analog frontend filter characteristic. In the following the signal may be <NUM>-times down-converted to ADC rate of <NUM>. Afterwards, the signal may be filtered by first single channel FIR channel filter on <NUM> rate, down-converted to signal processing rate (<NUM>) and filtered by the second FIR channel filter. Finally, the signal may be down-converted to symbol rate (<NUM>), hard decided and differentially decoded. The differential decoder is provided since the signal at mixer output contains the differential information of the original bit sequence.

Since a coherent receiver concept is used for single channel reception, phase and frequency are tracked constantly during the duration of packet reception. In an embodiment the phase tracking algorithm is based on the location of zero-crossings between consecutive symbols, relative to the sample timing grid. The concept of ZCDET is illustrated in <FIG> showing diagrams illustrating the detection of phase error information by zero-crossing detection. In an exemplary implementation a proportional integral (PI) filter may be used as loop filter, but in general any type of loop control filter may be applied, e.g. adaptive filter concepts or model predictive control (MPC) concepts, etc..

A loop filter is controlling the compensation based on an error measurement. In the simplest case it is just a factor, which defines the phase error correction speed. If frequency error also shall be tracked, a parallel integral branch with its own control factor may be included as well. There are generally many different types of loop filters which may be applied according to the present disclosure.

The single channel receiver operates only on real-valued signals, i.e. no direct phase information is available. The zero-crossing detector <NUM> acts as a phase error detector by detecting the zero-crossings in the intermediate digital signal <NUM> or an oversampled version thereof. It estimates the phase error of two consecutive symbols S1 and S2 (which have a zero-crossing between each other), based on the timing shift of the zero-crossing from the middle timing between the two consecutive symbols. The phase error is zero if the zero-crossing is exactly in the middle timing position between the two consecutive symbols S1 and S2, as shown in the constellations depicted in <FIG> and the corresponding zero-crossing timing depicted in <FIG>. If the zero-crossing deviates to the previous symbol there is a value unequal to zero outputted which is proportional to the corresponding phase offset present in the signal, as shown in the constellations with phase offset of <NUM>° depicted in <FIG> and zero-crossing timing in such a case depicted in <FIG>. If the zero-crossing deviates to the next symbol a value unequal to zero is outputted with opposite sign, which again is proportional to the phase error.

The amount of the deviation of the zero-crossing from the middle position may be determined by evaluating the relation between the amplitudes of the two consecutive symbols. Without loss of generality the assumption for an ideal symbol transition is that at previous symbol timing the amplitude has the value +x and the amplitude at the next symbol timing has the value -x. By comparing and normalizing the actual amplitude values to the expected value x, a timing offset value is obtained which is proportional to the phase error.

In other words, the absolute zero-crossing offset from its optimal symmetric <NUM>° phase offset position can be estimated based on amplitude differences of consecutive samples. The zero-crossing detector <NUM> detects a zero-crossing between samples at time instance n-<NUM> and n-<NUM>, if samples n-<NUM> and n-<NUM> have opposite sign than samples at n-<NUM> and n, where n is the sample index of the current sample (e.g. <NUM> rate). Based on the amplitude difference between sample n-<NUM> and n-<NUM>, the zero-crossing between these <NUM> samples is estimated in terms of fraction of symbol period. The sample timing grid is used as additional information, to obtain the offset direction, i.e. positive or negative phase offset.

A PI-filter may be used as loop filter to control the phase error compensation. It may comprise a proportional (P) and an integral (I) branch, which respectively can correct a constant phase and frequency error ideally to zero. For any higher order effect (e.g. frequency drift) a PI-filter is not optimal, since it can never correct the error ideally to zero. P- and I-gain may be designed in advance and then set as fixed constant system gains for simulations.

<FIG> shows a schematic diagram of a second embodiment of a single channel receiver2 according to the present disclosure. In this embodiment an additional timing tracking loop <NUM> is provided that is configured to detect signal shape distortions in the digital output signal <NUM> to obtain timing error information representing a sample timing error in the digital output signal <NUM>.

After the ADC <NUM>, the intermediated digital signal <NUM> is decimated in two stages from some ADC rate to some signal processing rate and finally to the symbol rate. Suppression of aliasing and further out-of-band interferers is accomplished in both decimation stages by the digital filters <NUM> (hD1) and <NUM> (hD2), respectively, each followed by a respective down-sampling stage <NUM> and <NUM>, respectively. Finally, the bits are detected in a hard decision detector <NUM> and differentially decoded by a differential decoder <NUM>. The differential decoder <NUM> is preferably provided due to the applied offset mixer concept. The phase tracking feedback <NUM>' is shown after the first digital filter <NUM> and the first down-sampling stage <NUM>, but the feedback may also be taken at any other suitable point in the single channel demodulator <NUM>.

For single channel reception of long packets in particular long BLE packets, a timing error caused by clock frequency offset results in significant performance degradation as sampling timing error increases towards the end of a packet. Since zero-crossing timing is already used for phase error detection, another indicator is used for sampling offset. In a single channel architecture, the amplitude information of received signal is used to estimate the direction of timing offset, which algorithm may herein be called Decision-Directed Phase Error Detection (DDPED) This phase error detection algorithm is used for timing error detection in this embodiment. Hence, in this embodiment the sample timing offset is additionally be tracked with a separate timing tracking algorithm. This decision directed algorithm is based on measuring (or estimating) signal shape distortions related to sample timing offset. The sample timing offset is estimated in a DDPED detector <NUM> and compensated in a (fractional) down-sampling stage <NUM> from ADC rate to signal processing rate. The sample timing compensation may, however, also be done in the second down-sampling stage <NUM>. A delay circuit <NUM> may be provided to compensate a delay of the elements <NUM> to <NUM>.

<FIG> shows diagrams illustrating the detection of timing error information used in an embodiment according to the present disclosure. <FIG> particularly show the input signal <NUM> (<FIG> in a constellation diagram and <FIG> over time)when there is no phase offset, i.e. the input signal <NUM> is a synchronized signal. In this case the expected ratio of the average amplitudes of area A and area B are identical. <FIG> show the input signal <NUM> (<FIG> in a constellation diagram and <FIG> over time)when there is a phase offset of -<NUM> degrees. In this case the expected ratio of the average amplitude of area A is larger than that of area B. If the phase offset is in the positive direction, the ratio of area A and area B are reversed, i.e. positive or negative direction of phase offset can be estimated. The timing for measuring amplitude in area A or B may be determined by the transmitted bit sequence. Therefore the decoded bit output of the demodulator <NUM> is fed to DDPED detector <NUM> as shown in <FIG>, which is the reason why the algorithm is called "decision-directed".

The reason why zero-crossing detection (ZCDET) is used for carrier phase error detection and decision-directed phase error detection (DDPED) is used for timing error detection is because of the detectors' reliabilities and required response time. Although DDPED is a direct measure for carrier phase offset, the algorithm may be susceptible of noise and may require a longer averaging window, i.e. it may not be suitable for carrier phase correction because carrier phase correction requires very fast response time and relatively high accuracy. On the other hand, sample timing offset increases very slowly even when there is a maximum <NUM> ppm clock frequency offset between the transmitter and the receiver, which justifies the use of the DDPED algorithm for timing error correction.

<FIG> shows diagrams illustrating a synchronized signal and a signal with phase offset As shown in <FIG>, with the absence of sample timing error (<FIG>), a phase offset results in a zero-crossing timing offset, i.e. the ZCDET algorithm can be used for phase error detection. With a zero sample timing error (<FIG>), a phase offset results in both zero-crossing timing offset and amplitude imbalance. In this case, the ZCDET algorithm quickly corrects the phase error and the DDPED algorithm will not play any role because its response time is much slower than the ZCDET algorithm.

<FIG> shows diagrams illustrating the effect of the compensation of phase errors and timing errors. As shown in <FIG>, when there is no phase error (<FIG>) but there is sampling error (sample timing error) on the received signal, ZCDET reacts on the zero-crossing timing and tries to correct it. As a result, ZCDET produces a residual phase error due to timing error. Then DDPED slowly corrects the residual phase error by correcting timing offset (<FIG>).

After some period of time, both carrier phase error and sample timing error are removed as depicted in <FIG>. This dual loop structure works for cases with existence of both carrier phase error and sample timing error, i.e. by additionally applying timing offset correction by DDPED, both carrier phase error and sample timing error can be corrected.

With the disclosed concept a reduction of the number of analog components (and thereby a reduction of the overall power consumption) can be achieved compared to a typical I/Q receiver architecture.

Thus, the foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. As will be understood by those skilled in the art, the present disclosure may be embodied in other specific forms. Accordingly, the disclosure of the present disclosure is intended to be illustrative, but not limiting of the scope of the disclosure, as well as other claims.

Further, such a software may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Claim 1:
Single channel receiver comprising:
- an input terminal (<NUM>) configured to receive an analog input signal,
- an RF mixer (<NUM>) configured to down-mix the analog input signal to an intermediate frequency by use of a phase- and/or frequency-corrected oscillator frequency signal and to shift complex-valued information contained in the analog input signal only to the real part or only to the imaginary part to obtain an intermediate real-valued analog signal,
- an analog-to-digital-converter (<NUM>) configured to convert the intermediate analog signal into an intermediate digital signal,
- a demodulator (<NUM>) configured to demodulate the intermediate digital signal into a digital output signal,
- a phase tracking loop (<NUM>) configured to detect zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, wherein the phase tracking loop comprises a zero-crossing detector (<NUM>) configured to detect the timing of zero-crossings between two consecutive symbols of the intermediate digital signal, and
- an oscillator (<NUM>) configured to generate the phase- and/or frequency-corrected oscillator frequency signal by use of the phase error information.