Patent Description:
Many communication standards outline a series of stressed test scenarios to determine if a device under test (DUT) passes all performance tests with a specified margin for conformance. Test and measurement instruments having a signal source, such as, for example, arbitrary waveform or function generators and bit error rate testers (BERTs), may be used to generate waveforms for stress testing to measure a performance margin of a DUT in response to the received signals.

Communication standards can require jitter impairments to be added to the desired data waveform that come in many forms, including, but not limited to, random, bounded/unbounded, sinusoidal, high/low frequency jitter, clock wander, etc. Given this, a test and measurement instrument having a signal source should have the ability to insert jitter impairments with the attributes specified by given communication standards. However, conventional test and measurement instruments often do not have a large enough baud rate range and/or flexible enough impairment generation capabilities to cover multiple standards effectively.

Embodiments of the disclosure address these and other deficiencies of the prior art. range and/or flexible enough impairment generation capabilities to cover multiple standards effectively.

Embodiments of the disclosure address these and other deficiencies of the prior art.

Document <CIT> relates to an Arbitrary Waveform Generator that has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files.

Document <CIT> relates to a device and method for generation of Intersymbol interference (ISI) effects on serial data by direct digital synthesis.

Aspects, features and advantages of embodiments of the present disclosure will become apparent from the following description of embodiments in reference to the appended drawings in which:.

Further embodiments are defined in the corresponding dependent claims. Furthermore, the description and drawings present additional examples, aspects, and non-claimed embodiments for the better understanding of the claimed invention.

Embodiments of the disclosure can add impairments to a desired data waveform to be synthesized, such as non-linearity, jitter, noise, crosstalk, intersymbol interference (ISI), channel frequency response, etc., to determine the margins required for the receiver DUT to properly record the desired data waveform, with an acceptable bit error rate (BER), based on the impaired data waveform. Embodiments of the disclosure can add the impairments, such as jitter or spread spectrum clocking, to the desired data waveform using either a digital signal processing (DSP) or analog means by modulating a signal source DAC sample clock in real-time, as will be discussed in more detail below.

Embodiments disclosed herein can be implemented either in real-time DSP hardware, such as a field programmable gate array (FPGA) or Application Specific Integrated Circuits (ASICs) or by pre-computation, if replication/interpolation of a waveform is done in advance and loaded to a waveform pattern memory in the signal source that is used to generate the real-time output waveform at the DAC sample rate.

<FIG> is a block diagram of a test and measurement instrument <NUM> having a waveform synthesizer according to some embodiments of the disclosure. An input waveform <NUM>, x[n], is a digital representation of the desired output waveform symbol values to be generated, which may be sampled at the baud rate of the waveform to be synthesized (Fs, symbol). The input waveform <NUM> can be received at waveform synthesizer <NUM>, which synthesizes the waveform, y[m], according to the sample rate (Fs, DAC) of a DAC <NUM>.

The synthesized waveform, y[m], is received at the DAC <NUM> and converted to an analog signal. The DAC <NUM> also may receive a reference clock <NUM> from another component of the test and measurement instrument. In some embodiments, after the synthesized waveform is converted to an analog signal through the DAC <NUM>, the analog waveform may be filtered by an analog low-pass filter, which can be used to remove signal content above the first Nyquist zone of the DAC <NUM> output. This may remove the zero-order hold effects of traditional DACs in the higher Nyquist zones, which causes sin(πf)/(πf) replication of the waveform spectrum in the first Nyquist zones across the higher Nyquist zones. The analog waveform may be output to a port, which may be connected through a cable to a device under test.

In embodiments or situations where the DAC <NUM> sample rate (Fs, DAC) is an integer multiple of the waveform baud rate (Fs, symbol), the analog low-pass filter may be removed or bypassed, and the output from the DAC <NUM> may be sent directly to the port since the zero-order hold response of the DAC <NUM> is coherent to the waveform that is being synthesized and can reinforce the desired symbol transitions in the output waveform for waveform signaling methods where symbol values are held constant across the entire symbol period, such as non-return to zero (NRZ) and pulse amplitude modulation (PAM).

An impairment <NUM> is sent to the waveform synthesizer <NUM>, which is added to the synthesized waveform, y[m], prior to being sent to the DAC <NUM>. The impairment <NUM>, as mentioned above, may be used to test a DUT connected to the port. That is, the DUT receives the impaired waveform and can be tested to determine if the DUT adequately recovers the intended data waveform (x[n]). The impairment <NUM> may be jitter, spread spectrum clocking (SSC) impairments, and/or other timing or phase impairments, as will be discussed in more detail below. The impairment <NUM> comes from an impairment generator <NUM>, which may be a memory that stores a number of different impairments required by testing standards or a processor that can generate the impairments either based on testing standards stored in the memory or an impairment received from a user input.

In some embodiments, the impairment generator <NUM> may receive an input signal provided by a user (not shown). The input signal may be used by the impairment generator <NUM> to generate the impairment <NUM>. In some embodiments, the impairment <NUM> is the received input signal, while in other embodiments, the impairment <NUM> is generated using the input signal.

The waveform synthesizer <NUM> may synthesize the waveform in a number of different ways, including, but not limited to, fractional replication and linear edge interpolation, fractional replication and zero insertion at edge, fractional replication with a data sample replication to a highly oversampled rate followed by a fractional decimation filter, fractional replication with pre-computed look up tables for edge value interpolation, etc..

Using a direct linear interpolation approach as an example, where the DAC input samples, y[m], may be computed from the input waveform <NUM>, x[n], using equations (<NUM>), (<NUM>), and <NUM>):
<MAT>
<MAT>
<MAT>.

Where <MAT>. That is, r is the ratio of the DAC <NUM> output sample rate and the input waveform <NUM> baud rate. Per the equations above, the value of µ[m] will dynamically vary for each DAC <NUM> sample period to achieve the desired fractional resampling rate between the waveform baud rate (Fs,Symbol) and the DAC <NUM> output sample rate (Fs,DAC). Thus, the variable µ[m] will reflect the placement of the symbol edge transitions, with sub-sample resolution relative to the DAC <NUM> output sample rate, for when a transition occurs between successive x[n] and x[n+<NUM>] input symbols. An edge in the waveform y[m] only occurs when x[n+<NUM>] is not equal to x[n]. Changing the value of µ[m] from its nominal value computed in equation (<NUM>) will translate to shifting the edge transition earlier or later in time relative to the nominally resampled output data waveform. This modulation of the edge location in the output waveform amounts to phase modulation or jitter insertion, which is shown in equation (<NUM>) for µ́[m] :
<MAT>.

Where jit[n] corresponds to a jitter phase modulation amount for a given symbol transition and ssc[n] corresponds to the phase modulation for a given symbol transition to emulate spread spectrum clocking (SSC) in the output waveform. Other timing and phase impairments may be added to equation (<NUM>) in a similar fashion.

Phase modulation due to jitter, SSC, and/or other timing or phase impairments can cause the symbol transition edges to move to a different DAC <NUM> output sample period relative to the sample period where the transition would normally occur before adding in the phase modulation. As such, a correction of an output symbol transition location may be beneficial, as shown in equations (<NUM>) and (<NUM>):
<MAT>
<MAT>.

Where e[m] determines the integer input sample index correction value to adjust the input samples <NUM> used in the linear interpolation process to handle cases where the jitter, SSC, and/or other phase modulation cause µ́[m] to be less than zero or greater than or equal to one, i.e., wrap between successive input sample periods.

The resulting equation for the waveform y[m], with the input sample index correction is shown in equation (<NUM>):
<MAT>.

<FIG> illustrates another example embodiment for modifying a synthesized waveform y[m] with jitter, SSC, and/or other timing or phase impairments. A waveform synthesizer <NUM> may include, for example, a waveform symbol clock generator <NUM> and a waveform synthesis interpolator <NUM>. The waveform symbol clock generator <NUM> also receives the DAC reference clock <NUM> from another component of the test and measurement instrument <NUM>, as well as an impairment <NUM>. The impairment may come, for example, from the impairment generator <NUM>.

The waveform symbol clock generator <NUM> outputs symbol transition events and symbol transition sub-sample phases to the waveform synthesis interpolator <NUM> which also receives the input signal <NUM>, x[n]. The waveform synthesis edge interpolator <NUM> outputs a digital signal, y[m], to be converted to an analog signal through DAC <NUM>. The embodiment of <FIG> may also include an analog filter to filter the analog signal before being output to a port, similar to <FIG>.

The waveform symbol clock generator <NUM> outputs symbol transition events and symbol transition sub-sample phases based on the DAC reference clock <NUM> and the impairment <NUM>. That is, the symbol transition events and symbol transition sub-sample phases may be modified based on the impairment <NUM>. The waveform synthesis interpolator <NUM> can translate the input waveform <NUM>, x[n], at the baud rate, to an output waveform, y[m], at the DAC <NUM> sample rate by using a DSP fractional interpolation and/or replication operation. The symbol transition time phase modulation can include both integer and fractional sample period phase modulation components, relative to the DAC <NUM> sample period. Thus, the phase modulation range can extend multiple DAC <NUM> sample periods relative to the normal symbol transition times before jitter, SSC, and/or other timing or phase impairments have been applied.

The embodiments of <FIG> and <FIG>, advance or delay the timing of transitions between symbol values in the baud-rate input waveform to apply phase modulation through DSP manipulation of the output waveform, y[m], values. <FIG>, on the other hand, is an example embodiment for an analog operation for inserting an impairment into a generated waveform.

Similar to <FIG> and <FIG>, an input waveform <NUM> is received at a waveform synthesizer <NUM> and output to a DAC <NUM>. The output of the DAC <NUM> may be further filtered through an analog filter prior to being output to a port, which may be connected to a device under test.

The waveform synthesizer <NUM> includes a waveform generator <NUM>, which may generate an output waveform, y[m], at the DAC <NUM> sample rate using any of the above-discussed operations, such as, but not limited to, fractional replication and linear edge interpolation, fractional replication and zero insertion at edge, fractional replication with a data sample replication to a highly oversampled rate followed by a fractional or integer decimation filter, fractional replication with pre-computed look up tables for edge value interpolation, etc..

The waveform synthesizer <NUM> receives an impairment <NUM> from an impairment generator <NUM>, which, in this example embodiment, outputs a digital codeword that specifies the amount of phase modulation for jitter, SSC, and/or other timing or phase impairments to be inserted for a given output sample. The digital codeword may come, for example, from jitter, SSC, and/or other timing or phase impairments generation operations which create the type of jitter, SSC, and/or other timing or phase impairments as dictated by a desired test. For example, if a user wants to perform a sinusoidal jitter tolerance test, then the impairment generator <NUM> may be a numerically controlled oscillator (NCO). As mentioned above, in some embodiments, a memory may store a number of different types of jitter or SSC that are required for different tests, and the impairment generator <NUM> may generate these codewords based on a type of test selected by a user. In other embodiments, a user may enter the specific type of impairment to be used through a user interface of the test and measurement instrument and the impairment generator <NUM> outputs the digital codeword based on this information. The codewords output by the impairment generator <NUM> may be updated for each symbol period of the input waveform <NUM>.

The digital codeword is sent to an analog phase adjuster <NUM>, which may be, for example, a phase interpolator (PI) or analog delay lines (ADL). A buffer <NUM>, such as a first in, first out buffer <NUM> shown in <FIG>, receives an output from the analog phase adjuster <NUM> and the waveform generator <NUM>. The buffer <NUM> allows the waveform generator <NUM> to run at a fixed clock rate. The buffer <NUM> can also handle situations where the phase modulation wraps between successive sample periods, as the jitter, SSC, and/or other timing or phase impairments phase modulation can result in scenarios where the next input sample value is mapped to a DAC <NUM> symbol value one sample period sooner or later than would otherwise occur with no phase modulation added. The output from the analog phase adjuster <NUM> is also sent to the DAC <NUM> as a jittered clock signal, rather than receiving a fixed-rate reference clock signal, as shown in <FIG> and <FIG>.

Flow control may be used to throttle the input data to the buffer <NUM> when the buffer <NUM> is near full and hold off the start of output waveform generation by DAC <NUM> until the buffer <NUM> has accumulated a sufficient buffer of valid samples to accommodate dynamic changes in the sample period in DAC <NUM>. Throttling the input data to the buffer <NUM> can regulate the dynamic changes in the DAC <NUM> output sample rate for cases where the digital feed path <NUM> feeding the DAC <NUM> needs to be implemented with a fixed rate clock, as opposed to a continuously varying clock rate that changes in lockstep with the phase modulated DAC <NUM> effective output sample rate. In such a case, the digital data path <NUM> feeding the buffer <NUM> can operate faster than the highest possible instantaneous DAC <NUM> output sample rate.

If a phase interpolator is used for the analog phase adjuster <NUM>, the analog phase adjuster <NUM> can rotate up to one output sample period in range (relative to DAC <NUM>) and rollover glitch free. If analog delay lines are used for the analog phase adjuster <NUM>, a full output sample period range can also be supported, but will do so with the concatenation of analog delay elements, i.e., chains of inverters, passive delay lines, etc..

<FIG> illustrates an example test and measurement instrument <NUM> with a waveform synthesizer <NUM> and a DAC <NUM>. The waveform synthesizer <NUM> may be any of the waveform synthesizers <NUM>, <NUM>, and <NUM> discussed above. The test and measurement instrument <NUM>, may be, for example, an arbitrary waveform generator, arbitrary function generator, bit error rate tester (BERT) or any test and measurement instrument that outputs a signal source.

The test and measurement instrument <NUM> includes one or more ports <NUM> which may be any electrical or optical signaling medium. Ports <NUM> may include receivers, transmitters, and/or transceivers, as well as potentially electrical-to-optical and/or optical-to-electrical converters. The ports <NUM> are coupled with the waveform synthesizer <NUM> through the DAC <NUM>. The waveform synthesizer <NUM> is connected to one or more processors <NUM>. Although only one processor <NUM> is shown in <FIG> for ease of illustration, as will be understood by one skilled in the art, multiple processors <NUM> of varying types may be used in combination, rather than a single processor <NUM>. In some embodiments, the waveform synthesizer <NUM> may be part of the one or more processors <NUM>.

The one or more processors <NUM> may be configured to execute instructions from memory <NUM> and may perform any methods and/or associated steps indicated by such instructions. Memory <NUM> may be implemented as processor cache, random access memory (RAM), read only memory (ROM), solid state memory, hard disk drive(s), or any other memory type. Memory <NUM> acts as a medium for storing data, computer program products, and other instructions. For example, the one or more processors <NUM> may output a digital signal to the Waveform synthesizer <NUM> that is to be output as an analog signal, such as described above, to a device under test through ports <NUM>.

User inputs <NUM> are coupled to the one or more processors <NUM>. User inputs <NUM> may include a keyboard, mouse, trackball, touchscreen, and/or any other controls employable by a user to with a GUI on the display <NUM>. The display <NUM> may be a digital screen, a cathode ray tube based display, or any other monitor to display waveforms, measurements, and other data to a user. While the components of test instrument <NUM> are depicted as being integrated within test and measurement instrument <NUM>, it will be appreciated by a person of ordinary skill in the art that any of these components can be external to test instrument <NUM> and can be coupled to test instrument <NUM> in any conventional manner (e.g., wired and/or wireless communication media and/or mechanisms). For example, in some embodiments, the display <NUM> may be remote from the test and measurement instrument <NUM>.

Aspects of the disclosure may operate on particularly created hardware, firmware, digital signal processors, or on a specially programmed computer including a processor operating according to programmed instructions. The terms controller or processor as used herein are intended to include microprocessors, microcomputers, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and dedicated hardware controllers. One or more aspects of the disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules, executed by one or more computers (including monitoring modules), or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer executable instructions may be stored on a computer readable storage medium such as a hard disk, optical disk, removable storage media, solid state memory, Random Access Memory (RAM), etc. As will be appreciated by one of skill in the art, the functionality of the program modules may be combined or distributed as desired in various aspects. In addition, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGA, and the like. Particular data structures may be used to more effectively implement one or more aspects of the disclosure, and such data structures are contemplated within the scope of computer executable instructions and computer-usable data described herein.

The disclosed aspects may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more or computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. Computer-readable media, as discussed herein, means any media that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may comprise computer storage media and communication media.

Computer storage media means any medium that can be used to store computer-readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Video Disc (DVD), or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals per se and transitory forms of signal transmission.

Communication media means any media that can be used for the communication of computer-readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber-optic cables, air, or any other media suitable for the communication of electrical, optical, Radio Frequency (RF), infrared, acoustic or other types of signals.

The previously described versions of the disclosed subject matter have many advantages that were either described or would be apparent to a person of ordinary skill. Even so, these advantages or features are not required in all versions of the disclosed apparatus, systems, or methods.

Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features.

Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

Claim 1:
A test and measurement device having a signal source, comprising:
an impairment generator (<NUM>) configured to output an impairment (<NUM>);
a waveform synthesizer (<NUM>) configured to:
receive an input digital signal (<NUM>) to be synthesized,
receive the impairment (<NUM>), and
synthesize a synthesized digital signal based on the input digital signal and the impairment; and
a fixed sample rate digital-to-analog converter (<NUM>) configured to receive a reference clock signal (<NUM>) and the synthesized digital signal and output an analog signal;
characterised in that the waveform synthesizer (<NUM>) includes:
a waveform symbol clock generator (<NUM>) configured to receive the impairment (<NUM>) and the reference clock signal (<NUM>) and output a transition event signal based on the impairment and the reference clock signal; and
a waveform synthesis interpolator (<NUM>) configured to receive the transition event signal and the input signal (<NUM>) and output the synthesized digital signal at the fixed sample rate of the digital-to-analog converter (<NUM>).