Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits in computing systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processing resource can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logical operations on data (e.g., one or more operands). For example, functional unit circuitry may be used to perform arithmetic operations such as addition, subtraction, multiplication, and division on operands via a number of logical operations.

A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and data may also be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Data movement between and within arrays and/or subarrays of various memory devices, can affect processing time and/or power consumption.

<CIT> describes DRAM cache with on-demand reload. <CIT> describes a semiconductor memory device. <CIT> describes apparatuses and methods for logic/memory devices. <CIT> describes using storage cells to perform computation.

The invention is defined by the features of independent claims.

The present disclosure includes apparatuses and methods related to logical operations using a logical operation component. An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processing-in-memory (PIM) device, in which a processing resource may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). A PIM device may reduce time in processing and may also conserve power. Data movement between and within arrays and/or subarrays of various memory devices, such as PIM devices, can affect processing time and/or power consumption.

Dynamic random-access memory (DRAM) may be provided as part of a computing system to store data associated with the computing system. In some approaches, DRAM may comprise multiple one transistor, one capacitor (1T1C) memory cells, which may be coupled together to form a memory array. In 1T1C DRAM environments, binary data information may be stored in the capacitor in the form of an electric charge. Once a 1T1C memory cell has been read (e.g., once a read operation has been performed using data stored in the 1T1C memory cell), the electric charge corresponding to the binary data information stored in the capacitor may discharge (e.g., leak, become depleted, etc.) thereby destroying the binary data information that was stored in the capacitor. This phenomenon may be referred to as a "destructive read" or "destructive memory cell read.

In contrast, DRAM memory cells having three transistors (3T) may preserve the binary data information (e.g., may preserve the charge stored therein) subsequent to performance of a read operation. This may allow for multiple word lines (e.g., read row lines, write row lines, etc.) to be fired without the need to refresh the memory cells or re-write data to the memory cells subsequent to performance of a read operation. This may reduce power consumption of a memory device since the memory cells do not need to be rewritten or refreshed in comparison to conventional 1T1C DRAM memory cells, and may reduce an amount of time (e.g., a read-to-read delay) required between performance of read operations in comparison to conventional 1T1C DRAM memory cells.

In some approaches, performing logical operations between binary data (e.g., operands) stored in memory cells and binary data stored in an accumulator may need to be inverted (e.g., using a latch in addition to a sense amplifier latch) prior to performance of a logical operation. For example, in some approaches, data would be transferred to a first latch to be inverted, and the inverted data stored in the first latch may have been used as an operand in a logical operation between the inverted operands and operands stored in an accumulator.

Further, in some approaches, performing logical operations between binary data (e.g., operands) stored in memory cells and binary data stored in an accumulator may require multiple latches per column because binary data may need to be transferred multiple times prior to execution of a logical operation. For example, data stored in memory cells may be transferred to a first latch, then data may be transferred to a second latch in two discrete operations prior to performance of a logical operation using the data values.

In contrast, embodiments disclosed herein allow for logical operations to be performed between binary data (e.g., operands) stored in the memory cells without using an additional latch to perform the inversion. For example, a 3T memory cell may be controlled to invert the data stored therein without the need for an additional latch. In some embodiments, the inverted data associated with the 3T memory cell may then be used as an operand for a logical operation.

Further, in some embodiments, logical operations may be performed between binary data stored in sense amplifiers without performing multiple operations to transfer the data from memory cells to the sense amplifiers. For example, in some embodiments, data values may be concurrently transferred from memory cells to multiple sense amplifiers. Subsequent to transfer of the data, logical operations may be performed using the data values stored in the sense amplifiers. In some embodiments, performance of the logical operation may be facilitated through the use of a logical operation component, which may be configured to cause performance of a logical operation such as an XOR logical operation between the data values stored in the sense amplifiers.

Some embodiments herein may allow for logical operations such as NOR logical operations and/or NAND logical operations to be performed using two sense amplifiers with different reference voltages. For example, a pair of sense amplifiers having different reference voltages (e.g., trip points) can be operated to perform a NOR operation or a NAND operation depending on which sense amplifier of the pair of sense amplifiers is enabled. As described in more detail herein, a logical operation component coupled to the pair of sense amplifiers can be operated such that the sensing circuitry outputs a XOR of the data values stored in the sense amplifiers, which can correspond to a XOR operation between data values stored in a pair of cells sensed by the sense amplifiers.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, designators such as "n, "N," etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. As used herein, "a number of" a particular thing refers to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays). A "plurality of" is intended to refer to more than one of such things.

As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

<FIG> is a block diagram of an apparatus in the form of a computing system <NUM> including a memory device <NUM> in accordance with a number of embodiments of the present disclosure. As used herein, a memory device <NUM>, controller <NUM>, channel controller <NUM>, memory array <NUM>, and/or sensing circuitry <NUM> might also be separately considered an "apparatus.

System <NUM> includes a host <NUM> coupled (e.g., connected) to memory device <NUM>, which includes a memory array <NUM>. Host <NUM> can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host <NUM> can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system <NUM> can include separate integrated circuits or both the host <NUM> and the memory device <NUM> can be on the same integrated circuit. The system <NUM> can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in <FIG> illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system <NUM> has been simplified to focus on features with particular relevance to the present disclosure. The memory array <NUM> can be a DRAM array (e.g., a 3T DRAM array), SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array <NUM> can comprise memory cells arranged in rows coupled by word lines, which may be referred to herein as row lines, access lines, or select lines, and columns coupled by digit lines, which may be referred to herein as data lines or sense lines. Although a single array <NUM> is shown in <FIG>, embodiments are not so limited. For instance, memory device <NUM> may include a number of arrays <NUM> (e.g., a number of banks of DRAM cells, NAND flash cells, etc.). In some embodiments, the memory array may include the sensing circuitry <NUM> in addition to the memory cells arranged in rows coupled by word lines and columns coupled by digit lines.

The memory device <NUM> includes address circuitry <NUM> to latch address signals for data provided over a data bus <NUM> (e.g., an I/O bus) through I/O circuitry <NUM>. Status and/or exception information can be provided from the controller <NUM> on the memory device <NUM> to a channel controller <NUM>, through a high speed interface (HSI) including an out-of-band bus <NUM>, which in turn can be provided from the channel controller <NUM> to the host <NUM>. Address signals are received through address circuitry <NUM> and decoded by a row decoder <NUM> and a column decoder <NUM> to access the memory array <NUM>. Data can be read from memory array <NUM> by sensing voltage and/or current changes on the digit lines using sensing circuitry <NUM>. The sensing circuitry <NUM> can read and latch a page (e.g., row) of data from the memory array <NUM>. The I/O circuitry <NUM> can be used for bi-directional data communication with host <NUM> over the data bus <NUM>. The write circuitry <NUM> can be used to write data to the memory array <NUM>.

Controller <NUM> (e.g., memory controller) decodes signals provided by control bus <NUM> from the host <NUM>. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array <NUM>, including data read, data write, and data erase operations. In various embodiments, the controller <NUM> is responsible for executing instructions from the host <NUM> and sequencing access to the array <NUM>. The controller <NUM> can be a state machine, sequencer, or some other type of controller, and include hardware and/or firmware (e.g., microcode instructions) in the form of an application specific integrated circuit (ASIC), field programmable gate array, etc. The controller <NUM> can control, for example, performance of logical operations between operands stored in the memory array <NUM>.

As described further below, in a number of embodiments, the sensing circuitry <NUM> and/or the array <NUM> can comprise one or more sense amplifiers and/or a logical operation component. The sense amplifier(s) can be used in the performance of logical operations. For example, the sense amplifiers and/or the logical operation component may be used to perform logical operations such as XOR, NOR, NAND, etc. logical operation between operands stored in the sense amplifier(s). Embodiments are not so limited, however, and in some embodiments, the sense amplifiers may be configured to latch data values corresponding to NOR and/or NAND operations based on the reference voltages (e.g., trip points) of the sense amplifiers.

For example, as described herein, a first sense amplifier may be configured to latch a data value corresponding to a NOR of a data value stored in a memory array coupled to the first sense amplifier, while a second sense amplifier may be configured to latch a data value corresponding to a NAND of a data value stored in the memory array coupled to the second sense amplifier. The data values latched in the first sense amplifier and/or the second sense amplifier may be transferred back the memory array. In some embodiments, the data values latched in the first and second sense amplifiers may be used as operands by a logical operation component to output a XOR.

In a number of embodiments, the sensing circuitry <NUM> can be used to perform logical operations using data stored in array <NUM> as inputs and/or store the results of the logical operations back to the array <NUM> without transferring data via a digit line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry <NUM> rather than (or in association with) being performed by processing resources external to the sensing circuitry (e.g., by a processing resource associated with host <NUM> and/or other processing circuitry, such as ALU circuitry, located on device <NUM> (e.g., on controller <NUM> or elsewhere)). Stated alternatively, various logical operations may be performed using, and within, the sensing circuitry <NUM> without transferring data or commands to or from the host <NUM>.

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry <NUM> is configured to perform logical operations on data stored in memory array <NUM> and store the result back to the memory array <NUM> without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry <NUM>. The sensing circuitry <NUM> can be formed on pitch with the memory cells of the array.

In a number of embodiments, circuitry external to array <NUM> and sensing circuitry <NUM> is not needed to perform compute functions as the sensing circuitry <NUM> can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry <NUM> may be used to complement and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry <NUM> may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host <NUM>). For instance, host <NUM> and/or sensing circuitry <NUM> may be limited to performing only certain logical operations and/or a certain number of logical operations.

Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to performing logical operations using sensing circuitry (e.g., <NUM>) without enabling column decode lines of the array. Whether or not local I/O lines are used in association with performing logical operations via sensing circuitry <NUM>, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array <NUM> (e.g., to an external register).

<FIG> is a schematic drawing illustrating a portion of a memory array in accordance with a number of embodiments of the present disclosure. <FIG> illustrates one memory cell <NUM>, which can be one of a number of memory cells corresponding to memory array <NUM> shown in <FIG>. In the example shown in <FIG>, the memory cell <NUM> is a 3T DRAM memory cell. In this example, the memory cell <NUM> comprises three transistors <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. The memory cell <NUM> may be operated to store a data value (e.g., a stored charge at node <NUM>). In some embodiments, a charge associated with the data value may be stored at node <NUM> using the parasitic capacitance generated between transistor <NUM>-<NUM> and transistor <NUM>-<NUM>. Embodiments are not so limited; however, and the memory cell <NUM> may optionally include a discrete capacitor <NUM> to store the data value.

The memory cell <NUM> includes two word lines <NUM>-<NUM>/<NUM>-<NUM> (e.g., row lines) and two digit lines <NUM>-<NUM>/<NUM>-<NUM> (e.g., bit lines). Word line <NUM>-<NUM> may be referred to herein as a read row line, and the word line <NUM>-<NUM> may be referred to herein as a write row line. Digit line <NUM>-<NUM> may be referred to herein as a write digit line, and digit line <NUM>-<NUM> may be referred to herein as a read digit line. The word lines <NUM>-<NUM>/<NUM>-<NUM> and the digit lines <NUM>-<NUM>/<NUM>-<NUM> may be enabled and/or disabled in conjunction with reading and writing data to the node <NUM> of the memory cell <NUM>.

As shown in <FIG>, the transistors <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are coupled to the word lines <NUM>-<NUM>/<NUM>-<NUM> and digit lines <NUM>-<NUM>/<NUM>-<NUM>. In association with performing a write operation, the write row line <NUM>-<NUM> may be enabled, and data may be placed on the write digit line <NUM>-<NUM>, thereby causing the data to be stored at node <NUM>. Similarly, in association with performing a read operation, the read row line <NUM>-<NUM> may be enabled and the data may be transferred out of the node <NUM> via the read digit line <NUM>-<NUM>. In some embodiments, the data value read out of the memory cell <NUM> as part of a read operation may be inverted in comparison to the data value written to the memory cell <NUM> as part of the write operation. For example, if a value of "<NUM>" is written to the memory cell <NUM>, a value of "<NUM>" may be read out of the memory cell <NUM>. Conversely, if a value of "<NUM>" is written to the memory cell <NUM>, a value of "<NUM>" may be read out of the memory cell <NUM>.

For example, memory cell <NUM> can be coupled to different digit lines <NUM>-<NUM>/<NUM>-<NUM> and word lines <NUM>-<NUM>/<NUM>-<NUM>. For instance, in this example, a first source/drain region of transistor <NUM>-<NUM> is coupled to digit line <NUM>-<NUM>, a second source/drain region of transistor <NUM>-<NUM> is coupled to node <NUM>, and a gate of transistor <NUM>-<NUM> is coupled to word line <NUM>-<NUM>. A first source/drain region of transistor <NUM>-<NUM> is coupled to digit line <NUM>-<NUM>, a second source/drain region of transistor <NUM>-<NUM> is coupled to a first source/drain region of transistor <NUM>-<NUM>, and a gate of transistor <NUM>-<NUM> is coupled to word line <NUM>-<NUM>.

In some embodiments, the data value stored at node <NUM> of the memory cell <NUM> may be used as an operand for performance of a logical operation. For example, a data value stored at node <NUM> of the memory cell <NUM> may be used as an operand to perform a logical operation with a data value stored at node <NUM> of a different memory cell, as described in more detail in association with <FIG>. For example, the data value stored at node <NUM> of the memory cell <NUM> may be transferred to a sense amplifier and subsequently used as an operand to perform a logical operation with a data value stored at node <NUM> of a different memory cell and transferred to a different sense amplifier. In some embodiments, the logical operation may comprise an XOR operation; however, embodiments are not so limited, and various logical operations such as ANDs, ORs, XORs, NANDs, etc. operations may be performed in the manner described herein.

In some embodiments, the memory cell <NUM> may be controlled to store a data value at node <NUM> subsequent to performance of a read operation. For example, the memory cell <NUM> may be controlled such that read operations are non-destructive. This may allow for multiple rows (e.g., read rows) to be fired without refreshing or re-writing data to the memory cell <NUM>, which may allow for improved performance and reduced power consumption in comparison with previous approaches that utilize destructive read cells such as 1T1C memory cells.

Although schematically represented in a planar orientation, the transistors <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM> may be arranged in a vertical orientation (e.g., extending upward out of the page or downward into the page in <FIG>). In some embodiments, the transistors <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM> of the memory cell <NUM> may be formed such that the transistors <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM> are contained within an area defined by the digit lines <NUM>-<NUM>/<NUM>-<NUM>. For example, the transistors <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM> of the memory cell <NUM> may be formed on pitch with digit lines <NUM>-<NUM>/<NUM>-<NUM> of the memory cell <NUM>. In some embodiments, the memory cell <NUM> may be formed such that the transistors <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM> of the memory cell <NUM> are disposed within an area that equal to or less than an area used by a conventional 1T1C DRAM memory cell.

<FIG> is another schematic drawing illustrating a portion of a memory array <NUM> in accordance with a number of embodiments of the present disclosure. As shown in <FIG>, the memory array <NUM> comprises a plurality of memory cells <NUM>. For clarity, only one memory cell <NUM> is labeled in <FIG>; however, each set of three transistors illustrated in <FIG> represents one of a plurality of memory cells <NUM> associated with the memory array <NUM>.

A plurality of memory cells <NUM> are coupled to a plurality of digit lines <NUM> and row lines <NUM>. For example, a first memory cell <NUM> is coupled to digit lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., write digit0 line <NUM>-<NUM><NUM> and read digit0 line <NUM>-<NUM><NUM>) and row lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., read row0 line <NUM>-<NUM><NUM> and write row0 line <NUM>-<NUM><NUM>). Similarly, a second memory cell is coupled to digit lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., write digit1 line <NUM>-<NUM><NUM> and read digit1 line <NUM>-<NUM><NUM>) and word lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., read row0 line <NUM>-<NUM><NUM> and write row0 line <NUM>-<NUM><NUM>), a third memory cell is coupled to digit lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., write digit0 line <NUM>-<NUM><NUM> and read digit0 line <NUM>-<NUM><NUM>) and word lines <NUM>-<NUM><NUM>/<NUM>-<NUM><NUM> (e.g., read row1 line <NUM>-<NUM><NUM> and write row1 line <NUM>-<NUM><NUM>, etc..

In some embodiments, if one or more memory cells <NUM> coupled to a particular digit line <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N (e.g., if one or more memory cells in a particular column of memory cells) contains a high voltage (e.g., a logical value of "<NUM>"), the associated digit line <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N will be driven to a ground reference potential. For example, if memory cell <NUM> (or any other memory cell in the column of memory cells coupled to digit line <NUM>-<NUM><NUM>) contains a high voltage, digit line <NUM>-<NUM><NUM> will be driven to a ground reference potential.

As described in more detail in association with <FIG>, herein, a sense amplifier (e.g., sense amplifier <NUM> illustrated in <FIG>) is coupled to respective pairs of digit lines <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N and <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N. The sense amplifier may sense a low voltage (e.g., a logical value of "<NUM>") if one or more of the memory cells coupled to a same pair of digit lines205-<NUM><NUM>,. , <NUM>-<NUM>N and <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N that are also coupled to the sense amplifier contains a high voltage (e.g., a logical value of "<NUM>"). Conversely, the sense amplifier may sense a high voltage (e.g., a logical value of "<NUM>") if one or more of the memory cells coupled to a same pair of digit lines205-<NUM><NUM>,. , <NUM>-<NUM>N and <NUM>-<NUM><NUM>,. , <NUM>-<NUM>N that are also coupled to the sense amplifier contains a low voltage (e.g., a logical value of "<NUM>"). That is, in some embodiments, the sense amplifier may sense a particular value (e.g., a "<NUM>" or a "<NUM>") based on the value stored in the memory cell that is coupled thereto.

As mentioned above, because a read operation using the memory cell <NUM> described in <FIG> and <FIG> may be non-destructive, the memory cell <NUM> may still contain the original data value (e.g., the same high or low voltage) that was stored therein prior to performance of the read operation and/or performance of the logical operation, while the sense amplifier may contain a result of the logical operation after performance of the logical operation. In some embodiments, the data value (e.g., the logical value of "<NUM>" or "<NUM>") stored in the sense amplifier subsequent to performance of the logical operation may be written back to any memory cell <NUM> (or row of memory cells) in the memory array <NUM>, as described in more detail in association with <FIG>, herein.

<FIG> is a block diagram of sensing circuitry in accordance with a number of embodiments of the present disclosure. As shown in <FIG>, the sensing circuitry <NUM> may include a first sense amplifier (SENSE AMP1) <NUM>, a second sense amplifier (SENSE AMP2) <NUM>, and a logical operation component <NUM>. As shown in <FIG>, the logical operation component <NUM> is an exclusive or (XOR) logical operation component. For example, the logical operation component <NUM> may be configured to cause performance of an XOR <NUM> logical operation between an operand (e.g., a data value or charge corresponding to a logical "<NUM>" or "<NUM>") stored in the first sense amplifier <NUM> and an operand stored in the second sense amplifier <NUM>. In some examples, as described in more detail in connection with <FIG>, herein, the first sense amplifier <NUM> may have a reference voltage (e.g., a trip point) associated therewith that causes a logical NOR of the data value to be stored in the first sense amplifier <NUM>, while the second sense amplifier <NUM> may have a reference voltage associated therewith that causes a logical NAND of the data value to be stored in the second sense amplifier <NUM>. The logical operation component <NUM> is described in more detail in connection with <FIG>, herein.

As used herein, a "component" is an electrical circuit (e.g., circuitry), hardware device (e.g., one or more processing resources and/or one or more memory resources), logic device, application-specific integrated circuit, field-programmable gate array, or combinations thereof, to perform one or more tasks or functions. A "logical operation component" is a component configured to cause performance of a logical operation, such as a XOR logical operation.

The first sense amplifier <NUM> and may be coupled to the logical operation component <NUM>, and the second sense amplifier <NUM> may be coupled to the logical operation component <NUM>. In some embodiments, the second sense amplifier <NUM> may be coupled to the logical operation component <NUM> via an inverter <NUM>. The inverter <NUM> may, in some embodiments, function as a NOT gate. When the logical operation component <NUM> is invoked, performance of a XOR logical operation between an operand stored in the first sense amplifier <NUM> and an operand stored in the second sense amplifier <NUM> may be facilitated.

As discussed in further detail in connection with <FIG>, herein, in some embodiments, the sensing circuitry <NUM> may be configured to store a data value corresponding to a logical NOR of a data value stored in a memory cell (e.g., memory cell <NUM> illustrated in <FIG>, herein) to be stored in the first sense amplifier <NUM>, and/or the sensing circuitry <NUM> may be configured to store a data value corresponding to a logical NAND of a data value stored in a memory cell to be stored in the second sense amplifier <NUM>. For example, if the data value stored in the first sense amplifier <NUM> is not passed through the logical operation component <NUM>, the sensing circuitry <NUM> may be configured to output a data value corresponding to a NOR <NUM> logical operation from the first sense amplifier <NUM>. Similarly, if the data value stored in the second sense amplifier <NUM> is not passed through the logical operation component <NUM>, the sensing circuitry <NUM> may be configured to output a data value corresponding to a NAND <NUM> logical operation from the second sense amplifier <NUM>. In some embodiments, the data value corresponding to the NOR logical operation <NUM>, the XOR logical operation <NUM>, and/or the NAND logical operation <NUM> may be read from the first sense amplifier <NUM> and/or the second amplifier <NUM> by enabling a column select line (e.g., Column Select transistor <NUM> illustrated in <FIG>, herein).

<FIG> is a graph illustrating the behavior of a plurality of digit lines responsive to activation of row lines associated with sensing circuitry in accordance with a number of embodiments of the present disclosure. The graph illustrated in <FIG> may correspond to a voltage sensing scheme associated with sensing circuitry (e.g., sensing circuitry <NUM> illustrated in <FIG>, herein). The upper horizontal curve shown in <FIG> corresponds to a voltage magnitude of Vcc, while the lower horizontal curve shown in <FIG> corresponds to a voltage magnitude associated with a ground reference potential (Gnd).

As shown in <FIG>, one or more sense amplifiers (e.g., SENSE AMP1 and/or SENSE AMP2 illustrated in <FIG>, herein) may be activated. The sense amplifier(s) may have a reference voltage (e.g., a trip point) somewhere between a pair of rail voltages (e.g., a supply voltage Vcc and applied to the read digit line <NUM> and the diagonal curve(s) illustrated in <FIG>.

For example, upon activation (e.g., upon enabling) of a first sense amplifier (e.g., SENSE AMP1 illustrated in <FIG>, herein), the first sense amplifier may have a reference voltage somewhere in between Vcc and the diagonal curve corresponding to a voltage associated with the first sense amplifier (e.g., the SENSE AMP1 Reference Voltage shown in <FIG>). Similarly, upon activation of a second sense amplifier (e.g., SENSE AMP2 illustrated in <FIG>, herein), the second sense amplifier may have a reference voltage somewhere in between Vcc and the diagonal curve corresponding to a voltage associated with the second sense amplifier (e.g., the SENSE AMP2 Reference Voltage shown in <FIG>).

In some embodiments, the first sense amplifier and the second sense amplifier may each have a different reference voltage (e.g., trip point). The reference voltage may refer to a voltage at which at least one memory cell associated with the sense amplifier is conducting. For example, the first sense amplifier may be configured to have a reference voltage corresponding to a first voltage and the second sense amplifier may be configured to have a reference voltage corresponding to a second voltage. The first voltage may have a greater magnitude than the second voltage, or vice versa.

<FIG> illustrates an example in which two row lines are activated. When two row lines are activated, there may be three different cases for how the digit lines (e.g., digit lines <NUM>-<NUM> and <NUM>-<NUM> illustrated in <FIG>, herein) respond. The first case corresponds to a case in which both memory cells coupled to the row lines contain a logical value of "<NUM>" (as shown at "<NUM>,<NUM> in cells"). In this case, the read digit line (e.g., read digit lines <NUM>-<NUM> illustrated in <FIG>, herein) stay at a precharged level of Vcc. For example, in the first case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), neither of the sense amplifiers are "tripped" corresponding to the memory cells coupled to the row lines contain logical values of "<NUM>.

The second case corresponds to a case in which one of the memory cells contains a logical value of "<NUM>" and the other memory cell contains a logical value of "<NUM>" (as shown at "<NUM>,<NUM> in cells or <NUM>,<NUM> in cells). In this case the read digit line may discharge from Vcc to the ground reference potential as shown by the curve <NUM>. For example, in the second case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), one of the sense amplifiers is "tripped" corresponding to one of the memory cells coupled to the row lines containing a logical value of "<NUM>," while another memory cell coupled to the row lines contains a logical value of "<NUM>.

In the second case, the data value latched by the first sense amplifier in response to the sense amplifier being tripped may correspond to a logical NOR (or NAND) of the data value stored in the corresponding memory cell. Similarly, the data value latched by the second sense amplifier may correspond to a logical NAND (or NOR) of the data value stored in the corresponding memory cell. Whether the data value latched by the respective sense amplifier corresponds to a logical NOR or a logical NAND corresponds to the reference voltage associated with the sense amplifier that is tripped.

For example, as shown in <FIG>, the SENSE AMP1 Reference Voltage is higher than a voltage corresponding a voltage on the READ DIGIT LINE at a time corresponding to the SENSE AMP DECIDE curve, which may result in the first sense amplifier latching a data value corresponding to a logical NOR of a data value stored in the memory cell corresponding to the first sense amplifier. In contrast, the SENSE AMP2 Reference Voltage is lower than a voltage corresponding a voltage on the READ DIGIT LINE at a time corresponding to the SENSE AMP DECIDE curve, which may result in the second sense amplifier latching a data value corresponding to a logical NAND of a data value stored in the memory cell corresponding to the second sense amplifier.

The third case corresponds to a case in which both memory cells contain a logical value of "<NUM>" (as shown at "<NUM>,<NUM> in cells"). In this case, the read digit line may discharge from Vcc to the ground reference potential as shown by the curve <NUM>. For example, in the third case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), both of the sense amplifiers are "tripped" responsive to the memory cells coupled to the row lines containing a logical value of "<NUM>. " In some embodiments, the rate of discharge exhibited by the curve <NUM> may be twice the rate of discharge exhibited by the curve <NUM>. For example, in the case corresponding to the curve <NUM>, there may be twice as much current in the memory cells as there is in the case corresponding to the curve <NUM>.

In some embodiments, a reference voltage for the first sense amplifier may be set to a particular value (as shown at "SENSE AMP1 Reference Voltage"), and/or a reference voltage for the second sense amplifier may be set to a different particular value (as shown at "SENSE AMP2 Reference Voltage"). Embodiments are not limited to the case shown in <FIG> in which there are two sense amplifiers, however, and in some embodiments, a single sense amplifier may be used. In examples in which a single sense amplifier is used, the sense amplifier may be sensed twice to correspond to the two particular sense amplifier reference voltage levels illustrated in <FIG>.

For example, a first reference voltage may be set for a single sense amplifier and a data value may be latched by the sense amplifier. In some embodiments, the data value latched by the sense amplifier using the first reference voltage may correspond to a logical NOR of a data value stored in the memory cell corresponding to the sense amplifier. Subsequently, a second reference voltage may be set for the sense amplifier. A data value latched by the sense amplifier using the second reference voltage may correspond to a logical NAND of a data value stored in the memory cell corresponding to the sense amplifier. The data value corresponding to the logical NOR and/or the data value corresponding to the logical NAND may be transferred to a storage location for use in a subsequent logical operation (e.g., in performance of a XOR logical operation using the data value corresponding to the NOR and the data value corresponding to the NAND as operands for the XOR logical operation).

<FIG> is a schematic diagram illustrating sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure. <FIG> illustrates a first sense amplifier <NUM> (e.g., SENSE AMP1), a second sense amplifier <NUM> (e.g., SENSE AMP2), and a logical operation component <NUM>. <FIG> illustrates one sensing component <NUM> which can be one of a number of sensing components corresponding to sensing circuitry <NUM> shown in <FIG>. The sensing component <NUM> may be coupled to a memory array <NUM>, via the digit line <NUM>-<NUM> (e.g., read digit line <NUM>-<NUM>) and the digit line <NUM>-<NUM> (e.g., write digit line <NUM>-<NUM>).

The read digit line <NUM>-<NUM> may be coupled to a first source/drain region of a transistor <NUM>-<NUM> (e.g., Precharge1 transistor <NUM>-<NUM>). A second source/drain region of the transistor <NUM>-<NUM> may be coupled to a voltage source configured to provide Vcc/<NUM> to the second source/drain region of the transistor <NUM>-<NUM>. The write digit line <NUM>-<NUM> may be coupled to a first source/drain region of a transistor <NUM>-<NUM> (e.g., Precharge2 transistor <NUM>-<NUM>). A second source/drain region of the transistor <NUM>-<NUM> may be coupled to a voltage source configured to provide Vcc to the second source/drain region of the transistor <NUM>-<NUM>.

As described in more detail below, the read digit line <NUM>-<NUM> and the write digit line <NUM>-<NUM> may be coupled to the sensing circuitry <NUM>, a Column Select transistor <NUM>, and/or a Local input/output (I/O) line. The Column Select transistor <NUM> may be controlled to select various columns of the memory array <NUM> to, for example, allow data values to be transferred between the memory array <NUM> and the sensing circuitry <NUM> and/or to circuitry external to the memory array <NUM>. In some embodiments, the Local I/O line may be controlled to transfer data values from the memory array <NUM> and/or sensing circuitry <NUM> to circuitry external to the memory array <NUM>.

The sense amplifiers <NUM> and <NUM> can be operated to determine a data value (e.g., logic state) stored in a selected memory cell of the memory array <NUM>. The sense amplifiers <NUM> and <NUM> can each include a cross-coupled latch <NUM>-<NUM>/<NUM>-<NUM> (e.g., gates of a pair of transistors, such as n-channel transistors that are cross coupled with the gates of another pair of transistors, such as p-channel transistors); however, embodiments are not limited to this example.

The cross-coupled latch <NUM>-<NUM> of SENSE AMP1 <NUM> may be coupled to a Read Enable1 transistor <NUM>-<NUM>, which may be coupled to the read digit line <NUM>-<NUM> and a Write Enable1 transistor <NUM>-<NUM>, which may be coupled to the write digit line <NUM>-<NUM>. Similarly, the cross-coupled latch <NUM>-<NUM> of SENSE AMP2 <NUM> may be coupled to a Read Enable2 transistor <NUM>-<NUM>, which may be coupled to the read digit line <NUM>-<NUM> and a Write Enable2 transistor <NUM>-<NUM>, which may be coupled to the write digit line <NUM>-<NUM>.

The sensing circuitry <NUM> may further include a Reference Enable1 transistor <NUM>-<NUM>, which may be coupled to the cross-coupled latch <NUM>-<NUM> at a first source/drain region of the transistor <NUM>-<NUM>. In some embodiments, a second source/drain region of the transistor <NUM>-<NUM> may be coupled to a reference potential (e.g., a ground reference potential). Similarly, the sensing circuitry <NUM> may further include a Reference Enable2 transistor <NUM>-<NUM>, which may be coupled to the cross-coupled latch <NUM>-<NUM> at a first source/drain region of the transistor <NUM>-<NUM>. In some embodiments, a second source/drain region of the transistor <NUM>-<NUM> may be coupled to a reference potential (e.g., a ground reference potential).

In some embodiments, an XOR logical operation as described above in connection with <FIG> and below in connection with <FIG> may be performed between data values stored in the memory array <NUM> by precharging the ACT1 (active pull-up) node of the cross-coupled latch <NUM>-<NUM> of SENSE AMP1 <NUM> and precharging the ACT2 node of the cross-coupled latch <NUM>-<NUM> of the SENSE AMP2 <NUM>, and/or precharging the RNL1 (activation) node of the cross-coupled latch <NUM>-<NUM> of SENSE AMP1 <NUM> and precharging the RNL2 node of the cross-coupled latch <NUM>-<NUM> of the SENSE AMP2 <NUM>. In some embodiments, the ACT1 node, the ACT2 node, the RNL1 node, and/or the RNL2 node may be precharged to Vcc/<NUM> prior to performance of the logical operation.

Subsequent to, or concurrently with precharging the ACT1 node, the ACT2 node, the RNL1 node, and/or the RNL2 node, the Precharge1 transistor <NUM>-<NUM> may be enabled to precharge the read digit line <NUM>-<NUM> to Vcc/<NUM>. In some embodiments, the Read Enable1 transistor <NUM>-<NUM> and the Read Enable2 transistor <NUM>-<NUM> may be enabled such that the charge on the digit line <NUM>-<NUM> may pass through the Read Enable1 transistor <NUM>-<NUM> and the Read Enable2 transistor <NUM>-<NUM>. Subsequently, the Reference Enable1 transistor <NUM>-<NUM> and the Reference Enable2 transistor <NUM>-<NUM> may be enabled.

A plurality of rows (e.g., rows <NUM>-<NUM>/<NUM>-<NUM> illustrated in <FIG>, herein) may be subsequently activated (e.g., opened). In some embodiments, two rows, such as write row0 <NUM>-<NUM><NUM> and write row1 <NUM>-<NUM><NUM> may be activated. The rows <NUM>-<NUM>/<NUM>-<NUM> may be activated to allow a data value stored in a memory cell (e.g., memory cell <NUM> illustrated in <FIG>) to be transferred to the sense amplifiers <NUM>/<NUM> (e.g., SENSE AMP1 and/or SENSE AMP2).

In some embodiments, the data values stored in memory cells coupled to the rows (e.g., rows <NUM>-<NUM>/<NUM>-<NUM>) may be sensed by the SENSE AMP1 and/or the SENSE AMP2. For example, a signal may develop on the SENSE AMP1 and/or the SENSE AMP2 in response to activation of the rows. Once the signal has developed on the SENSE AMP1 and/or the SENSE AMP2, the Reference Enable1 transistor <NUM>-<NUM> and the Reference Enable2 transistor <NUM>-<NUM> may be disabled, and/or the Read Enable1 transistor <NUM>-<NUM> and the Read Enable2 transistor <NUM>-<NUM> may be disabled.

The ACT1 node the ACT2 node, the RNL1 node, and/or the RNL2 node may subsequently be enabled (e.g., fired) to sense a state corresponding to the read digit line <NUM>-<NUM>. For example, the ACT1 node the ACT2 node, the RNL1 node, and/or the RNL2 node may subsequently be enabled to sense the data values present on the read digit line <NUM>-<NUM> in the SENSE AMP1 <NUM> and/or the SENSE AMP2 <NUM>.

In some embodiments, once the data values are sensed by the SENSE AMP1 and/or the SENSE AMP2, the rows may be deactivated (e.g., closed). In some embodiments, the write digit line <NUM>-<NUM> may be precharged to Vcc. For example, the Precharge2 transistor <NUM>-<NUM> may be enabled to precharge the write digit line <NUM>-<NUM> to Vcc. Subsequently, a row different than the rows previously activated may be activated. For example, write rowN <NUM>-<NUM>N may be activated (e.g., opened).

The XOR Enable transistor <NUM> may be subsequently enabled to transfer a result of the XOR logical operation between the data value sense by SENSE AMP1 and the SENSE AMP2 to the row different than the rows previously activated (e.g., to write rowN <NUM>-<NUM>N). In some embodiments, the result of the XOR logical operation may be stored in a memory cell coupled to the write row (e.g., to a memory cell coupled to write rowN <NUM>-<NUM>N). After the result of the XOR logical operation has been transferred to the write row that is different than the rows previously activated, the write row that is different than the rows previously activated may be disabled (e.g., closed).

In some embodiments, the result of the XOR logical operation may be read out of the sensing circuitry <NUM> via the Column Select line and/or via the Local I/O line. As described above, the data value sensed by the SENSE AMP1 may be read out of the sensing circuitry the write row that is different than the rows previously activated, the Column Select line and/or via the Local I/O line. As described above in connection with <FIG>, the resulting data value read out of the SENSE AMP1 may correspond to a data value having a NOR logical operation applied thereto or performed thereon. Similarly, the data value sensed by the SENSE AMP2 may be read out of the sensing circuitry the write row that is different than the rows previously activated, the Column Select line and/or via the Local I/O line. As described above in connection with <FIG>, the resulting data value read out of the SENSE AMP2 may correspond to a data value having a NAND logical operation applied thereto or performed thereon.

<FIG> is a schematic diagram illustrating a portion of a memory array including sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure. <FIG> shows a number of sense amplifiers <NUM>/<NUM> coupled to respective digit lines <NUM> and <NUM>. The sense amplifiers <NUM>/<NUM> shown in <FIG> can correspond to sensing circuitry <NUM> shown in <FIG>, sense amplifiers <NUM>/<NUM> shown in <FIG> and/or sense amplifiers <NUM>/<NUM> shown in <FIG>.

Although not explicitly shown, memory cells, such as those described in <FIG>, are coupled to the respective digit lines <NUM>-<NUM> and <NUM>-<NUM> The cells of the memory array <NUM> can be arranged in rows coupled by word lines and columns coupled by pairs of digit lines, etc. The individual digit lines corresponding to each pair of respective digit lines can also be referred to as data lines. Although only five pairs of digit lines <NUM>-<NUM>/<NUM>-<NUM> (e.g., five columns) are shown in <FIG>, embodiments of the present disclosure are not so limited.

A data value present on a digit line <NUM> can be loaded into the corresponding sense amplifier <NUM> and/or sense amplifier <NUM>. For example, as described in connection with <FIG>, data values present on the digit lines <NUM>-<NUM> may be sensed by the sense amplifier <NUM> and/or the sense amplifier <NUM>.

Each column may be coupled to memory cells <NUM>, which can be coupled to a Column Select transistor <NUM> (e.g., a column decode line) that can be activated to transfer data values from corresponding sense amplifiers <NUM>/<NUM> to a control component external to the array such as an external processing resource (e.g., host processor and/or other functional unit circuitry). The column decode line can be coupled to a column decoder. In a number of embodiments, the data values may be transferred to the sense amplifiers <NUM>/<NUM> and/or transferred out of the sense amplifiers <NUM>/<NUM> without transferring data to a control component and/or a processing resource external to the array (e.g., without transferring data from the memory device to a host such as host <NUM> illustrated in <FIG>), for instance. In some embodiments, a logical operation may be performed using operands stored in the sense amplifiers <NUM>/<NUM> without encumbering a host such as host <NUM> shown in <FIG>. As used herein, the term "encumbering" refers to utilizing processing resources and/or transferring commands and/or data. For example, a logical operation may be performed using operands stored in the sense amplifiers <NUM>/<NUM> without utilizing processing resources and/or transferring commands and/or data from the memory device to the host.

As used herein, transferring data, which may also be referred to as moving data or shifting data is an inclusive term that can include, for example, copying data from a source location to a destination location and/or moving data from a source location to a destination location without necessarily maintaining a copy of the data at the source location (e.g., at the sense amplifier <NUM> and/or at the sense amplifier <NUM>).

Logical operation components <NUM> may be coupled to the digit lines <NUM>-<NUM>/<NUM>-<NUM> and/or to the sense amplifiers <NUM>/<NUM>. The logical operation components <NUM> may be analogous to the logical operation component <NUM> illustrated in <FIG> and/or logical operation component <NUM> illustrated in <FIG>, herein.

In some embodiments, the logical operation component <NUM> may be configured to cause performance of a logical operation (e.g., a XOR logical operation) between data values (e.g., operands) stored in the sense amplifier <NUM> and the sense amplifier <NUM>. Performance of said logical operations may be carried out using the logical operation component <NUM> by enabling and/or disabling various transistors that comprise the logical operation component <NUM>, as shown and described in connection with <FIG>, herein.

The result of a logical operation performed by use of the logical operation component <NUM> may be transferred via the Local I/O line from the memory array <NUM> and/or sensing circuitry (e.g., sensing circuitry <NUM> shown in <FIG>) to circuitry external to the memory array. Embodiments are not so limited, however, and the result of the logical operation may be transferred via activation of the Column Select transistors <NUM> from the memory array and/or sensing circuitry to circuitry external to the memory array.

<FIG> is a logic table illustrating selectable logical operation results implementable in accordance with a number of embodiments of the present disclosure. In <FIG>, each column corresponds to a data value associated with a particular component or portion of a memory array (e.g., memory array <NUM> illustrated in <FIG>) and/or a particular component or portion of the sensing circuitry (e.g., sensing circuitry <NUM> illustrated in <FIG>).

The first column corresponds to a data value associated with a first row <NUM>-<NUM><NUM> of the memory array (e.g., ROW <NUM>). The second column corresponds to a data value associated with a first row <NUM>-<NUM><NUM> of the memory array (e.g., ROW <NUM>). The third column corresponds to a first sense amplifier <NUM> of the sensing circuitry, while the fourth column corresponds to a second sense amplifier <NUM> of the sensing circuitry. In the third and fourth columns, the data values correspond to data values output by the first sense amplifier and the second sense amplifier, respectively. For example, as described above in connection with <FIG>, a data value output by the first sense amplifier <NUM> may correspond to performance of a NOR logical operation <NUM> by the first sense amplifier, and a data value output by the second sense amplifier <NUM> may correspond to performance of a NAND logical operation <NUM> by the first sense amplifier. The fifth column corresponds to a result of a XOR logical operation <NUM> performed by a logical operation component (e.g., logical operation component <NUM> illustrated in <FIG>) using a data value stored in the first sense amplifier <NUM> and a data value stored in the second sense amplifier <NUM>.

In the second row of the logic table illustrated in <FIG> (e.g., the first row of the logic table containing numbers), ROW <NUM> and ROW <NUM> may each include a logical value of "<NUM>. " In this case, the first sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NOR operation <NUM>. The second sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NAND operation <NUM>. If the logical operation component is invoked to cause performance of a XOR logical operation <NUM> between an operand stored in the first sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>") and an operand stored in the second sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>"), the result will have a logical value of "<NUM>," as shown in <FIG>.

In the third row of the logic table illustrated in <FIG> (e.g., the second row of the logic table containing numbers), ROW <NUM> may include a logical value of "<NUM>" and ROW <NUM> may include a logical value of "<NUM>. " In this case, the first sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NOR operation <NUM>. The second sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NAND operation <NUM>. If the logical operation component is invoked to cause performance of a XOR logical operation <NUM> between an operand stored in the first sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>") and an operand stored in the second sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>"), the result will have a logical value of "<NUM>," as shown in <FIG>.

In the fourth row of the logic table illustrated in <FIG> (e.g., the third row of the logic table containing numbers), ROW <NUM> may include a logical value of "<NUM>" and ROW <NUM> may include a logical value of "<NUM>. " In this case, the first sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NOR operation <NUM>. The second sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NAND operation <NUM>. If the logical operation component is invoked to cause performance of a XOR logical operation <NUM> between an operand stored in the first sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>") and an operand stored in the second sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>"), the result will have a logical value of "<NUM>," as shown in <FIG>.

In the fifth row of the logic table illustrated in <FIG> (e.g., the fourth row of the logic table containing numbers), ROW <NUM> and ROW <NUM> may each include a logical value of "<NUM>. " In this case, the first sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NOR operation <NUM>. The second sense amplifier <NUM> may be configured to store and/or output a logical value of "<NUM>," corresponding to performance of a logical NAND operation <NUM>. If the logical operation component is invoked to cause performance of a XOR logical operation <NUM> between an operand stored in the first sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>") and an operand stored in the second sense amplifier <NUM> (e.g., a data value with a logical value of "<NUM>"), the result will have a logical value of "<NUM>," as shown in <FIG>.

<FIG> is a flow diagram <NUM> for performing logical operations using sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure. In some embodiments, the logical operation may be a XOR logical operation, as described in connection with <FIG>, <FIG>, and <FIG>, herein. Performance of the logical operation may include operating sense amplifiers at different reference voltages and/or enabling a XOR Enable transistor (e.g., XOR Enable transistor <NUM> illustrated in <FIG>). The logical operation may be performed between data values stored in one or more memory cells and/or between data values stored in the first sense amplifier and the second sense amplifier.

At block <NUM>, a digit line (e.g., read digit line <NUM>-<NUM> illustrated in <FIG>) may be precharged to Vcc/<NUM>. In some embodiments, prior to precharging the digit line, an ACT1 (active pull-up) node of a first sense amplifier (e.g., SENSE AMP1 <NUM> illustrated in <FIG>), an ACT2 node of a second sense amplifier (e.g., SENSE AMP2 <NUM> illustrated in <FIG>), and/or an RNL1 (activation) node of the first sense amplifier and an RNL2 node of the second sense amplifier may be precharged to Vcc/<NUM>.

At block <NUM>, a read enable transistor and a reference enable transistor may be activated (e.g., opened). In some embodiments, the read enable transistor may correspond to Read Enable1 transistor <NUM>-<NUM> and/or Read Enable2 transistor <NUM>-<NUM> illustrated in <FIG>. The read enable transistor(s) may be enabled such that the charge on the digit line may pass through the read enable transistor(s). Subsequently, the reference enable transistor(s), which may correspond to Reference Enable1 transistor <NUM>-<NUM> and the Reference Enable2 transistor <NUM>-<NUM> illustrated in <FIG>, may be enabled.

At block <NUM>, one or more rows of a memory array (e.g., memory array <NUM> illustrates in <FIG>) may be activated. In some embodiments, two rows, such as write row0 <NUM>-<NUM><NUM> and write row1 <NUM>-<NUM><NUM>, illustrated in <FIG>, may be activated. The rows may be activated to allow a data value stored in a memory cell (e.g., memory cell <NUM> illustrated in <FIG>) to be transferred to the first sense amplifier and the second sense amplifier. In some embodiments, the data values stored in memory cells coupled to the rows may be sensed by the first sense amplifier and/or the second sense amplifier. For example, a signal may develop on the first sense amplifier and/or the second sense amplifier in response to activation of the rows. Subsequently, in some embodiments, the read enable transistor(s) and the reference enable transistor(s) may be disabled, as described in connection with <FIG>, herein.

At block <NUM>, the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may be activated (e.g., fired). In some embodiments, activating the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may allow a state corresponding to the digit line to be sensed by the first sense amplifier and/or the second sense amplifier. For example, activating the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may allow for a data value present on the digit line to be sensed by the first sense amplifier and/or the second sense amplifier.

In some embodiments, once the data values are sensed by the first sense amplifier and/or the second sense amplifier, the rows may be deactivated (e.g., closed). In some embodiments, the write digit line (e.g., write digit line <NUM>-<NUM> illustrated in <FIG>) may be precharged to Vcc. For example, a precharge transistor such as Precharge2 transistor <NUM>-<NUM> shown in <FIG> may be enabled to precharge the write digit line to Vcc. Subsequently, a row different than the rows previously activated may be activated, as described in connection with <FIG>.

Once the logical operation has been performed, a result of the XOR logical operation may be transferred to a row different than the rows previously activated (e.g., to write rowN <NUM>-<NUM>N shown in <FIG>). In some embodiments, the result of the XOR logical operation may be stored in a memory cell coupled to the write row (e.g., to a memory cell coupled to write rowN <NUM>-<NUM>N illustrated in <FIG>). After the result of the XOR logical operation has been transferred to the write row that is different than the rows previously activated, the write row that is different than the rows previously activated may be disabled (e.g., closed).

In some embodiments, the result of the XOR logical operation may be read out of the sensing circuitry via a Column Select line and/or via a Local I/O line, as described in connection with <FIG> and <FIG>, herein. As described above in connection with <FIG>, a resulting data value read out of the first sense amp (in the absence of performance of the XOR logical operation) may correspond to a data value having a NOR logical operation applied thereto or performed thereon. In some embodiments, resulting data value read out of the second sense amp (in the absence of performance of the XOR logical operation) may correspond to a data value having a NAND logical operation applied thereto or performed thereon.

Operations to perform a logical XOR operation in accordance with the disclosure can be summarized as follows:.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claim 1:
An apparatus, comprising:
an array of three-transistor, 3T, memory cells (<NUM>, <NUM>, <NUM>, <NUM>) including a first 3T memory cell and a second 3T memory cell, wherein a first transistor of the first 3T memory cell is coupled to a read digit line (<NUM>-<NUM>) and a first transistor of the second 3T memory cell is coupled to the read digit line (<NUM>-<NUM>);
said array of 3T memory cells coupled to sensing circuitry (<NUM>, <NUM>, <NUM>) including a first sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>), a second sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>), and a logical operation component (<NUM>, <NUM>, <NUM>), wherein:
the first sense amplifier and the second sense amplifier are coupled to the same read digit line (<NUM>-<NUM>),
the first sense amplifier and the second sense amplifier each have a respective enable signal the first sense amplifier and the second sense amplifier each have a different reference voltage, and
the sensing circuitry (<NUM>, <NUM>, <NUM>) is controlled to:
activate two read rows lines concurrently by coupling the first 3T memory cell and the second 3T memory cell to the read digit line (<NUM>-<NUM>);
sense, via the first sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>), a data value of the read digit line (<NUM>-<NUM>) as part of performance of a first logical operation
concurrently sense, via the second sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>), a data value of the read digit line (<NUM>-<NUM>) as part of performance of a second logical operation; and
operate the logical operation component (<NUM>, <NUM>, <NUM>) to output a result of a third logical operation based on the data value stored in the first sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>) and the data value stored in the second sense amplifier (<NUM>, <NUM>, <NUM>, <NUM>).