Patent Description:
Functional circuits such as logic gates and buffers typically use CMOS output driver circuits and dependent on the nature of the circuit connected to the output, the output drivers can drive variable capacitive loads. The output driver is designed to drive the external capacitance with specific rise/fall times, dependent on the application, of the external circuit. Unwanted voltage spike events can occur on the signal outputs of such electronic integrated circuits. These unwanted events, also known as bumps, can have a magnitude that is less than a supply voltage of the electronic integrated circuit. A bump may be defined as an unwanted voltage or signal on the output of an electronic circuit, such as a logic circuit.

If the external capacitance connected to the output of the electronic circuit is a certain value (farads) and a parasitic capacitance of the output driver circuit between supply and output capacitance is a fraction of the external capacitance then a certain fraction of the supply voltage may appear as a bump, on the output of the driver when supply ramps up.

As the rate of change of the electronic circuit supply voltage (typically designated as VCC) over time, known as the ramp rate, increases, high frequency coupling effects may arise leading to the unwanted bumps and disturb the signal integrity.

Looking at a generalised data transfer system as illustrated in <FIG>, data is received at an input of a first circuit, SystemA. The output of the first circuit is connected to the input of a second circuit, SystemB, and the second circuit provides a data output for connection to further circuitry (not illustrated). During operation the second circuit may be powered up and ready to receive data from the first circuit but the first circuit may not be ready to transfer data to the second circuit. In this situation, if there are any bumps, or unwanted voltages or signals generated by the output driver of the first circuit, they will be transferred to the second circuit. If the amplitude of the bump is greater than an input threshold voltage of the second circuit the bump will be processed by the second circuit which may lead to an erroneous and unwanted signal at the output of the second circuit.

Currently the effects of the bumps can be reduced by synchronising the turn on of the electronic circuit supply voltage with the turn on of the second circuit. However, synchronisation requires an additional timing signal between the two circuits which prevents switch on of the second circuit until the bump has passed.

Prior art documents <CIT>, <CIT> and <CIT> are disclosing optical filters for electronic circuits that are known in the art.

Various example embodiments are directed to issues such as those addressed above and/or others which may become apparent from the following disclosure concerning minimising high frequency supply coupling to the output load of electronic circuits and in particular, minimising the generation of undesired voltage spikes or bumps on the output of such electronic circuits.

In certain example embodiments, aspects of the present disclosure involve attenuation of undesired voltage spikes or bumps on output pad(s) or pin(s) of an electronic circuit. According to an embodiment there is provided a filter circuit for an output stage of electronic circuit, the filter comprising: a capacitor connected between a supply voltage and a first transistor wherein the first transistor is arranged as a diode connected transistor; a second transistor connected to the first transistor such that the first and second transistors are arranged as a current mirror; wherein the capacitor is connected to the first and second transistors and configured and arranged such that during operation the first transistor, the second transistor and the capacitor operate as a high pass filter.

The capacitor may be connected to a source and gate of the first transistor, and a gate of the second transistor. The first transistor may act as the impedance of the high pass filter and the gate source capacitances of the first and second transistors and the capacitor are the capacitance of the high pass filter. The impedance of the first filter transistor may be the gate-source impedance of the first transistor.

The capacitor and the first transistor may be configured an arranged to detect a change in the supply voltage. The capacitance of the capacitor is greater than the combined capacitance of the first transistor and the second transistor. The second transistor is arranged to be connected to the output stage and wherein the output stage is a CMOS driver.

The second transistor may be connected to a further circuit, wherein the further circuit has a capacitive and resistive load.

The filter circuit of the claimed invention further comprises an enable circuit, to switchably operate the filter circuit, wherein the enable circuit comprises a third transistor connected to the source of the first transistor and a supply voltage detection circuit connected to a gate of the third transistor.

According to embodiments there is also provided an output stage of an electronic circuit comprising the filter circuit according to embodiments.

According to embodiments there is also provided logic circuit comprising the output stage.

So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:.

A filter circuit <NUM> in accordance with an example, not falling within the scope of the claimed invention, is illustrated in the circuit diagram of <FIG>. The filter circuit <NUM> may comprise a first filter transistor <NUM>, a second filter transistor <NUM> and a filter capacitor <NUM>. A supply voltage VCC <NUM> is connected in series with the filter capacitor <NUM> and a first terminal of the first filter transistor <NUM>. A second terminal of the first filter transistor <NUM> is connected to ground <NUM>. The first filter transistor <NUM> is arranged as a diode connected transistor, whereby the first terminal of the of the first filter transistor <NUM> is connected to the gate terminal thereof. The first filter transistor <NUM> and second filter transistor <NUM> are connected to form a current mirror.

The arrangement of the filter capacitor <NUM> and first and second transistors <NUM>, <NUM> as a current mirror, may be switched between a series arrangement of capacitors illustrated in <FIG>, and a high-pass filter, illustrated in <FIG>. Before the supply voltage VCC <NUM> reaches the threshold voltage of the first and second filter transistors <NUM>, <NUM>, the filter circuit <NUM> acts as a series of capacitances, namely the filter capacitor <NUM> and the sum of the gate-source capacitances Cgs of the first and second filter transistors <NUM>, <NUM>, as shown in <FIG>. However, when the supply voltage VCC <NUM> reaches the threshold voltage of the first and second filter transistors <NUM> (the voltage at node <NUM> being equal), the first filter transistor <NUM> switches on and thus provides an impedance, <NUM>/gm (where gm is the transconductance of the first filter transistor <NUM>) in parallel with the sum of the gate-source capacitances Cgs of the first and second filter transistors <NUM>, <NUM>. The high pass filter of <FIG> may then attenuate an unwanted bump event, such that the magnitude of the bump at an output <NUM> of the filter circuit is reduced when compared to the bump which occurred during the rise time of the supply voltage VCC <NUM>.

In more detail, as the supply voltage VCC <NUM> rises and before the first filter transistor <NUM> turns on, the voltage at the node <NUM> of first terminal and gate of the first filter transistor <NUM> increases linearly based on the ratio of first filter transistor <NUM> capacitance and filter capacitor <NUM> (as shown in <FIG>). After the first filter transistor <NUM> turns on, and during supply voltage VCC <NUM> ramp up, node <NUM> holds the voltage that is already coupled when first filter transistor <NUM> is off. During the remaining ramp up cycle the second transistor <NUM> turns on and draws current from the output driver (illustrated as output driver stage <NUM> of circuit <NUM> in <FIG>) and no current flows to the external capacitor of the external circuit at output <NUM> of the driver circuit.

As mentioned above, the filter capacitor <NUM> and the first filter transistor <NUM> are arranged to operate as a high pass filter. Specifically, when the first filter transistor <NUM> turns on, the diode connected transistor arrangement with the second filter transistor <NUM> offers the impedance of <NUM>/gm, which is the drain source impedance of the first filter transistor, in parallel with the combined capacitance of the first filter transistor <NUM> and second filter transistor <NUM>. Since this arrangement acts as a high pass filter it keeps a constant voltage at node <NUM> during the remaining supply ramp up cycle. The gate of the first filter transistor <NUM> is connected to the gate of the second filter transistor <NUM>.

A first terminal of the second filter transistor <NUM> is arranged as the output <NUM> of the bump filter circuit <NUM>. A second terminal of the second filter transistor <NUM> is connected to ground <NUM>.

In applications, as discussed in more detail below with reference to <FIG>, the output <NUM> of the bump filter <NUM> is typically connected to the output driver stage (not illustrated in <FIG>) of a functional circuit, such as a logic circuit as illustrated. Therefore, because the voltage is constant at node <NUM>, the current is constant though node <NUM> and the drain source current through the second filter transistor <NUM> is equal to the drain source current through the first filter transistor <NUM>.

The first and second filter transistors <NUM>, <NUM> are typically operated in saturation mode. The first filter transistor <NUM> is in saturation because the drain source voltage Vds will be greater that the difference between the gate source voltage V<NUM>s and the threshold voltage V1h of the first filter transistor <NUM>. The second filter transistor <NUM> also turns on in saturation because there is voltage already coupled to the output through the driver. Therefore, when first filter transistor <NUM> turns on, the second filter transistor <NUM> also turns on in saturation. Assuming that 100mV is present on the output capacitance of the output <NUM> of the driver circuit due to coupling through the driver, when supply ramps up and V1h is 600mV, if voltage on node <NUM> goes above 600mV, second filter transistor <NUM> turns on in saturation because the drain source voltage Vds is 100mV.

The filter circuit <NUM> operates only when the supply voltage <NUM> turns on and is ramping up. As discussed in more detail below, the supply voltage <NUM> will increase to a maximum over time. When the supply voltage <NUM> turns on and ramps up, the filter circuit <NUM> turns on and prevents any voltage coupling to the external capacitor by turning on bump filter circuit <NUM>. Any bump that is coupled through parasitic capacitance of the driver circuit is therefore filtered by the filter circuit <NUM>. In addition, through the use of the high pass filter mentioned above, the filter circuit <NUM> operates to remove certain frequencies where high frequency coupling effects arise. That is the filter circuit <NUM> removes bumps which are equal to or higher than a predetermined frequency.

As the amplitude of the bump reduces with reduction in supply voltage ramp rate <NUM>, the voltage on node <NUM> also reduces with the reduction in ramp rate so that the amount of current drawn from the output <NUM> reduces with the corresponding reduction in frequency. The high pass filter feature of the filter counteracts the low pass behaviour of a bump event.

As the supply voltage rises, the voltage at the node <NUM> of first terminal and gate of the first filter transistor <NUM> will rise correspondingly. As the voltage at the node <NUM> increases and then reaches the threshold voltages, Vth of the first filter transistor <NUM> and second filter transistor <NUM>. It should be noted that the threshold voltages of the first filter transistor <NUM> and the second filter transistor <NUM> are equal. At the threshold voltage Vth, the first filter transistor <NUM> and the second filter transistor <NUM> will consequently be turned on and the second filter transistor <NUM> discharges the voltage coupled to the output <NUM> and prevents further incremental change in the voltage on the output <NUM>.

Assuming that the supply voltage VCC <NUM> increases from 0V to <NUM>. 7V and that a bump event of <NUM>. 1Vis coupled to the output <NUM>. As the supply voltage VCC <NUM> increases further, the first filter transistor <NUM> turns on and provides low impedance path to ground by turning on the second filter transistor <NUM>. The voltage on the node <NUM> stops increasing and maintains low impedance path to ground until supply voltage VCC <NUM> reaches its maximum value.

The filter capacitor <NUM> and the first filter transistor <NUM> are selected based on the maximum ramp rate of the supply voltage VCC <NUM>. When supply voltage VCC <NUM> increases from 0V to <NUM>. 8V, the first filter transistor <NUM> and the filter capacitor <NUM> are selected such that the voltage on the node <NUM> reaches the threshold voltage <NUM>. 7V of first and second filter transistors <NUM>, <NUM>. Based on the desired attenuated magnitude of the bump event, the specific value of the filter capacitance and the capacitances of the first and second filter transistors <NUM>, <NUM> selected such that the specific capacitance value (farad) of the filter capacitor <NUM> is larger than the combined gate-source capacitance the first and second filter transistor <NUM>, <NUM>.

In one example, non-limiting, application the maximum supply voltage <NUM> ramp rate from 0V to VCC may be <NUM>. The external load capacitance may be 5pF -and the external load resistance may be 1MΩ and a typical bump event amplitude (assuming no filter) will be approximately 700mV. For a bump filter circuit <NUM> according to embodiments, where the filter capacitor <NUM> is <NUM>. 8pF, and the ratio of the capacitance of the first filter transistor <NUM> and the filter capacitor <NUM> is as low as possible so that switching on of the first filter transistor <NUM> synchronises with the occurrence of the bump. This arrangement may result in a bump of amplitude of approximately 100mV.

A filter circuit <NUM> in accordance with an embodiment of the claimed invention is illustrated in the circuit diagram of <FIG>. As with the arrangement of <FIG>, discussed above, the bump filter circuit <NUM> may comprise a first filter transistor <NUM>, a second filter transistor <NUM> and a filter capacitor <NUM>. A supply voltage <NUM> is connected in series with the filter capacitor <NUM>, a filter resistor <NUM> and a first terminal of the first filter transistor <NUM>. A second terminal of the first filter transistor <NUM> is connected to ground <NUM>. The first filter transistor <NUM> is arranged as a diode connected transistor, whereby the first terminal of the of the first filter transistor <NUM> is connected to the gate terminal thereof. The filter capacitor <NUM> and the first filter transistor <NUM> are arranged as a high pass filter. The gate of the first filter transistor <NUM> is connected to the gate of the second filter transistor <NUM>. A first terminal of the second filter transistor <NUM> is arranged as the output <NUM> of the bump filter circuit <NUM>. A second terminal of the second filter transistor <NUM> is connected to ground <NUM>.

The filter resistor <NUM> is arranged to handle electrostatic discharge (ESD) events. When an ESD event occurs, the filter capacitor <NUM> provides a low impedance path which can create currents that may damage either the filter circuit <NUM> itself or the circuit connected to the output <NUM>. By including the filter resistor <NUM> the current is limited during ESD event. Specifically, the filter resistor <NUM> limits high frequency ESD events passed by the filter capacitor <NUM>, whilst also ensuring that the voltage drop is kept to a minimum. In this regard the voltage drop across the filter resistor <NUM> should be less than the voltage drop across the first filter transistor <NUM> such that the majority of the voltage drop occurs across the first filter transistor <NUM>. Typically, the filter resistor <NUM> may be approximately a 2KΩ resistor. Similar to the arrangement of <FIG>, for the filter <NUM> of <FIG>, the filter capacitor <NUM> and the first filter transistor <NUM> are selected based on the maximum ramp rate of the supply voltage <NUM> and the specific capacitance value (farads) of the filter capacitor <NUM> is larger than the combined gate-source capacitance of each of the first filter transistor <NUM> and the second filter transistor <NUM>.

In the arrangement of <FIG>, the filter circuit <NUM> also comprises an enable control circuit which comprises an enable transistor <NUM> and a power supply detector <NUM>. A first terminal of the enable transistor <NUM> is connected to the first terminal of the first filter transistor <NUM> at node <NUM>. A gate terminal of the enable transistor <NUM> is connected to the output of a power supply detector <NUM>, and the power supply detector <NUM> is connected to the supply voltage <NUM>. Enable transistor <NUM> is selected such that the gate source leakage current is low and any excess voltage coupling during ramp-up of the supply voltage <NUM> is avoided.

When the supply voltage VCC <NUM> reaches a maximum (or in other words a valid voltage level) such as <NUM> Volts, a disable signal is generated by the power supply detector <NUM> which disables the filter <NUM> circuit. The filter <NUM> is disabled by switching on the enable transistor <NUM> and thus by-passing the first filter transistor <NUM> and second filter transistor <NUM>, because any current generated by the supply voltage <NUM> will flow through the filter capacitor <NUM> and filter resistor <NUM> to ground <NUM>. In this way when the gate voltage, indicated by Supply_good, of the enable transistor <NUM> is greater than the threshold voltage of the enable transistor <NUM>, the filter <NUM> is disabled. Therefore, the Supply_good signal is generated only when supply voltage is stable and there is no chance of a bump event.

The filter capacitor <NUM>, the filter resistor <NUM> and the first filter transistor <NUM> are used to detect a change in supply voltage <NUM>. Before the power supply detect circuit <NUM> is turned on, the filter circuit <NUM> is turned on and attenuates the bump voltage. When the Supply_good signal is asserted the bump filter actively draws the excess current from the output driver <NUM> (see <FIG>). The second filter transistor <NUM> then removes the voltage that is coupled to the output due to high frequency effects on the supply voltage as it powers up. As the supply voltage <NUM> switches on it will take a finite period of time (see <FIG>) to reach a maximum or valid voltage level, this finite period of time is known as the rise time. When the supply voltage reaches the threshold voltage Vth of the first and second filter transistor <NUM>, <NUM> the transistors <NUM>, <NUM> will turn on and remove the bump event that would have otherwise been coupled to the output <NUM>, due to the rising supply voltage <NUM>, by actively drawing current and preventing from appearing at the output <NUM>.

The second filter transistor <NUM> will not switch on until the threshold voltage is reached and the attenuated bump, as discussed above, is observed at the output <NUM>.

With reference to the arrangements of <FIG> and <FIG>, the first terminal and second terminal of the first filter transistor <NUM>, <NUM> and enable transistor <NUM> may be, respectively, drain terminals and source terminals. Likewise, the first terminal and second terminal of the second filter transistor <NUM>, <NUM> and enable transistor <NUM> may be, respectively, a drain terminal and a source terminal. The first filter transistor <NUM>, <NUM> and the second filter transistor <NUM>, <NUM> may be NFET or NMOS transistors. In addition, from the above discussion, the skilled person will see that the control circuit of <FIG> may likewise be used with the bump filter circuit of <FIG> by connecting the first terminal of the enable transistor <NUM> to node <NUM>.

The bump filter circuit <NUM>, <NUM> according to embodiments can therefore detect the change in supply voltage and attenuate the any high frequency voltage bumps that may occur.

<FIG> illustrates a bump filter <NUM> according to embodiments connected to an output driver stage <NUM> of a circuit <NUM>. The circuitry <NUM>, may provide the functionality such as Level-shifting, NOR, NANO, XOR, AND, NOT, XNOR and OR is connected to the CMOS output driver stage <NUM>.

Whilst the embodiment of <FIG> relates to logic functionality, the skilled person will see that the present disclosure is also relevant for any circuit having CMOS driver the output stage. For example the filter <NUM>, <NUM> according to embodiments may also be applicable to high speed <NUM> circuits such as high speed serializer and deserializer and high speed clock drivers.

The filter may be arranged according to the embodiments of <FIG> or <FIG> such that the output <NUM>, <NUM> is connected to the output <NUM> of the driver circuit. As illustrated in <FIG>, the resistor and the capacitor connected to the output merely represent the load resistance and capacitance of the external circuit of the output driver stage <NUM>.

In terms of operation <FIG> illustrate various plots of voltage versus time, comparing circuits with and without a filter <NUM>, <NUM> according to embodiments. <FIG>shows how the supply voltage <NUM>,<NUM> increases over time from a minimum, for example O volts, to a maximum (or valid voltage level), for example <NUM> volts. In the situation where no filter circuit is used (as indicated by the solid line in <FIG>), a bump event will appear on the output <NUM> of the output driver stage. However, in the situation where a bump filter <NUM>, <NUM> according to embodiments is used (as indicated by the dotted line in <FIG>) the amplitude of the bump event is attenuated as described above.

In the plots of <FIG>the supply voltage <NUM>, <NUM> is zero at time To. At time T1, the supply voltage <NUM>, <NUM> switches on and rises to a maximum or valid voltage level at T3. From T1 to T2, the voltage at node <NUM>, <NUM> increases to the threshold voltage Vth of the first and second filter transistors <NUM>, <NUM>, <NUM>, <NUM>, based on the capacitance ratio of device capacitances of the first and second filter transistors <NUM>, <NUM>, <NUM>, <NUM> and the filter capacitor <NUM>. From T2 to T3, the filter circuit according to embodiments acts as a high pass filter and attenuates the bump such that a bump of reduced magnitude (as indicated by the dotted line in <FIG>) appears at the output <NUM>, <NUM> of the filter circuit <NUM>, <NUM>.

<FIG>shows an enable signal generated by the power supply detect circuit to disable the filter circuit. The signal is enabled at T3 after the supply voltage <NUM> become stables. <FIG> is the voltage on node <NUM>, <NUM> increases and reaches above the threshold voltage. This ensures that filter circuit turns on provided that the supply voltage is ramping up by enabling the first and second filter transistors <NUM> and <NUM>.

<FIG> is a plot of bump amplitude versus voltage supply ramp rate on the output of output driver stage with and without the filter circuit according to embodiments. As can be shown the magnitude of bump is reduced, in particular for ramp rates from <NUM> to <NUM>.

<FIG> is a plot bump amplitude versus load capacitance at the output <NUM> of the driver circuit <NUM> with and without the filter circuit according to embodiments. The amplitude of the bump is clearly reduced over the range of load capacitances from <NUM> to 20pF.

Whilst the foregoing examples illustrate embodiments with respect to logic circuits, the embodiments are not limited thus. The skilled person will appreciate that embodiments also relate to analog and mixed signal circuits having drivers to drive capacitive loads on the output of said drivers.

Particular and preferred aspects of the invention are set out in the accompanying independent claims.

Claim 1:
A filter circuit for an output stage of electronic circuit, the filter circuit comprising:
a capacitor connected between a supply voltage terminal and a first transistor wherein the first transistor is arranged as a diode connected transistor;
a second transistor connected to the first transistor such that the first and second transistors are arranged as a current mirror;
wherein the capacitor is connected to the first and second transistors and configured and arranged such that during operation the first transistor, the second transistor and the capacitor operate as a high pass filter;
characterized in that,
the filter circuit further comprises an enable circuit, to switchably operate the filter circuit, wherein the enable circuit comprises a third transistor connected to the source of the first transistor and a supply voltage detection circuit connected to a gate of the third transistor.