Patent Description:
Artificial neural networks (hereinafter, neural network) have become increasingly important in artificial intelligence applications and modern computing in general. An example neural network is shown in <FIG>. Neural network <NUM> receives input values corresponding to features to be recognized. The input values are multiplied by weights (represented by edges <NUM>) and added together (e.g., summed) in nodes <NUM>. An activation function is applied to the result in the nodes <NUM> to generate an output value. Values are combined across multiple nodes and layers of nodes to produce network output values corresponding to a result.

Such systems "learn" to perform tasks by considering examples, generally without being programmed with task-specific rules. Initially, the weights may be untrained. During a training phase, input values for corresponding known results are processed by the network, and the difference (or error) between the network output values is compared to known values. The weights may be adjusted based on the error using a process known as backpropagation, where computations flow in the reverse direction (e.g., from the output to the input). Training may involve successively adjusting weights across many input samples and corresponding known network output values. This is often referred to as the training phase. Once trained, the system may receive inputs and produce meaningful results (e.g., classification or recognition). This is often referred to as the inference phase.

As the popularity of neural networks has increased, so to has the complexity of problems neural networks are being used to solve. As the complexity of the problems increases, the size and computational complexity of the networks has increased. One common and very time-consuming operation in a neural network is normalization. For example, as activations and weights are multiplied and summed across nodes of a network, it is common to normalize the results. Softmax is an example of one such normalization function. Softmax may be used as the last activation function of a neural network to normalize the output of a network to a probability distribution over predicted output classes, for example. However, normalization functions often require complex numerical calculations that can slow down the network. The disclosure presented herein provides digital circuits and processing techniques that may be used in normalization functions (and other applications) more efficiently.

Various embodiments, examples, and advantages are described in the detailed description below.

<CIT> describes a method for performing a power of two estimation on a floating-point number within a data processing system. The floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. In order to estimate the power of two of the floating-point number, the mantissa is partitioned into an integer part and a fraction part, based on the value of the exponent bits. A floating-point result is formed by assigning the integer part of the floating-point number as an unbiased exponent of the floating-point result, and by converting the fraction part of the floating-point number via a table lookup to become a fraction part of the floating-point result.

<NPL> addresses the problem of cost-efficient inference for Soft-max, a popular non-linear function in DNNs. There is provided a hardware-aware linear approximation framework by algorithm and hardware co-optimization, with the goal of minimizing the cost in terms of area and energy, without incurring significant loss in application accuracy. This is achieved by simultaneously reducing the operand bit-width and approximating cost-intensive operations in Softmax (e.g. exponential and division) with cost-effective operations (e.g. addition and bit shifts). A hardware unit for an approximation approach, to estimate the area and energy Consumption, is designed. In addition, there is provided a training method to further save area and energy cost. It reduces area cost by 13x and energy consumption by 2x with <NUM>-bit operand width, compared to baseline at <NUM>-bit for VOC2007 dataset in Faster R-CNN. <NPL> describes a simplified hardware implementation of a CNN softmax layer is proposed. Initially the softmax activation function is analyzed in terms of required accuracy and certain optimizations are proposed. Subsequently the proposed hardware architecture is evaluated in terms of the introduced approximation error. Finally the proposed circuits are synthesized in a <NUM>-nm <NUM> V CMOS standard-cell library using Synopsys Design Compiler. Comparisons reveal significant reduction up to <NUM>% and <NUM>% for certain cases, in terms of area x delay product over prior art. Area savings are achieved with no performance penalty.

Various embodiments of the present disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings.

In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. Such examples and details are not to be construed as unduly limiting the elements of the claims or the claimed subject matter as a whole. It will be evident to one skilled in the art, based on the language of the different claims, that the claimed subject matter may include some or all of the features in these examples, alone or in combination, and may further include modifications and equivalents of the features and techniques described herein.

Features and advantages of the present disclosure include a digital circuit that receives input values (e.g., floating point) and produces output values corresponding to an approximate value of a power of two (<NUM>) (e.g., <NUM>, <NUM>,. ) raised to a power of the input value x (e.g., <NUM>x, <NUM>x, etc.. As described in more detail below, the Softmax function may be approximated using such functions. Advantageously, such functions may be implemented in combinational digital logic, which may be able to generate outputs without waiting for multiple clock cycles, for example. Accordingly, some example embodiments may be able to generate outputs based only on a present input, in contrast to sequential logic, in which the output depends not only on the present input but also on the prior inputs (e.g., data is stored). This may result in faster, lower latency systems which may implement many approximations of the Softmax function, for example.

<FIG> illustrates a digital circuit <NUM> according to an embodiment. Circuit <NUM> receives an input value <NUM> in a floating point representation. Input value (Xi) <NUM> comprises an input exponent (ex), input mantissa (mx), and an input sign bit (sx) represented as digital bits. Digital circuit <NUM> comprises combinational logic <NUM> which receives the digital bits representing an input mantissa mx and digital bits representing an input exponent ex and generates a plurality of output mantissas and plurality of output exponents <NUM> corresponding to an approximate value of a power of two (<NUM>) raised to a power of the input value. In one example embodiment, combinational logic <NUM> generates a plurality of shifted versions of the input mantissa, where the input mantissa is shifted based on the input exponent to produce the output mantissas and output exponents. Advantageously, separate output mantissas and output exponents may be generated across four quadrants, for example, when the input value is positive and negative and when the input exponent is above and below a first value.

Digital circuit <NUM> further includes selection circuits <NUM>. Selection circuits <NUM> are configured to receive the output mantissas and output exponents <NUM> and produce one final output mantissa <NUM> and one final output exponent <NUM>. Accordingly, embodiments of the present disclosure may include two or more selection circuits, such as multiplexers, in selection circuits <NUM>, for example. Selection circuits <NUM> may include selection control inputs coupled to the input exponent and an input sign bit of the input value (Xi). As illustrated here and in further embodiments below, features of the present disclosure include selecting one of the output mantissas as the final output mantissa <NUM> and selecting one of the output exponents as the final output exponent <NUM> based on the input exponent and the input sign bit. Since digital circuit <NUM> implements an approximate value of a power of two (<NUM>) raised to a power of the input value (e.g., Nx, N = <NUM>, <NUM>, <NUM>, <NUM>,. ), the output sign bit is constant value <NUM>, and may be hardwired at <NUM>, for example. Thus, the output value (Yi) <NUM> generated by digital circuit <NUM> may also be a floating point value comprising an exponent (ey), mantissa (my), and a sign bit (sy). Advantageously, in some embodiments, streams of input values (Xi) may be converted to output values (Yi) very quickly (e.g., on each clock cycle) for efficient computation of an approximation of the Softmax function, for example.

<FIG> illustrates a digital circuit according to another embodiment. Features and advantages of the present disclosure include shifting the mantissa of the input value based on the exponent to produce output mantissas and output exponents, which may then be selected based on the input exponent and input sign bit. In this example, digital circuit <NUM> receives input values <NUM> comprising an input sign bit, input exponent, and input mantissa and produce an output value <NUM> approximately equal to a power of two (<NUM>) raise to the power of the input (e.g., <NUM>x, <NUM>x) comprising an output sign bit, output exponent, and output mantissa. Digital circuit <NUM> includes combinational logic <NUM>, which in this example includes shifter circuits <NUM>. A plurality of shifter circuits may receive in the input mantissa and input exponent, for example. Features and advantages of the present disclosure include shifting the input mantissa <NUM> based on the input exponent <NUM> to produce a plurality of output manitssas <NUM> and output exponents <NUM>, which are coupled to selection circuits <NUM> and <NUM> for selection one output mantissa/exponent pair as the final outputs based on the input sign bit <NUM> and input exponent <NUM>. The shifter circuits may produce left and right shifted versions of the input mantissa. For example, a right shifter circuit may include a first input coupled to the input mantissa <NUM> through a logic circuit configured to add the input mantissa to a constant and a shift input coupled to the input exponent <NUM> through a logic circuit configured to negate the input exponent. Additionally, a first left shifter circuit may include a first input coupled to receive the input mantissa <NUM> and a shift input coupled to the input exponent <NUM>, for example. A right shifted version of the input mantissa may be used to form a first output mantissa and a second output mantissa, and lower bits of a left shifted version of the input mantissa may be used to form a third output mantissa and a fourth output mantissa. Further, upper bits of a left shifted version of the input mantissa may be used to form a first output exponent and a second output exponent. Further examples and illustrations of these techniques are provided below.

In some example embodiments, the shifter circuits are barrel shifter circuits, which is a digital circuit that can shift a data word by a specified number of bits using combinational logic (e.g., without the use of any sequential logic and associated delays from storing data over time). Barrel shifters may be advantageous in applications where it is desirable to obtain a result on a single clock cycle, for example.

Each output mantissa <NUM> may have an associated output exponent <NUM>, for example, corresponding to a particular pair of values for the input exponent <NUM> and input sign bit <NUM> (e.g., <NUM> sets of tuples for sx greater than or less than <NUM>, and ex greater than or less than <NUM> or -<NUM>). Selection circuits <NUM> and <NUM> are controlled by the input exponent <NUM> and input sign bit <NUM>. Accordingly, a final output mantissa <NUM> and final output exponent <NUM> may be selected from the plurality of output mantissas <NUM> and output exponents <NUM> based on the input exponent <NUM> and input sign bit <NUM>.

Accordingly, selection circuits <NUM> may produce different output mantissas, and selection circuits <NUM> may produce different output exponents, based on the input sign bit and input exponent. First, selection circuits <NUM> and <NUM> may produce a final output mantissa comprising a shifted version of a sum of the input mantissa and a constant and an output exponent having a zero value (<NUM>) when the input sign bit is positive and the input exponent is less than a first value (e.g., <NUM> or -<NUM>). Second, selection circuits <NUM> and <NUM> may produce a final output mantissa comprising a modulus of another shifted version of the input mantissa and a final output exponent having a digital value of one (<NUM>) shifted based on the input exponent added to an integer division of the shifted version of the input mantissa when the input sign bit is positive and the input exponent is greater than the first value. Third, selection circuits <NUM> and <NUM> may produce a final output mantissa comprising the first shifted version of the sum of the input mantissa and a constant, subtracted from a second constant, and a final output exponent having negative one (-<NUM>) value when the input sign bit is negative and the input exponent is less than the first value. Finally, selection circuits <NUM> and <NUM> may produce a final output mantissa comprising a modulus of the second shifted version of the input mantissa, subtracted from the second constant, and a negation of the second output exponent minus one (<NUM>) when the input sign bit is negative and the input exponent is greater than the first value. Various example implementations and further illustrations of the above techniques are provided below.

<FIG> illustrates an example digital circuit <NUM> for generating approximations of <NUM>x according to another embodiment. Digital circuit <NUM> includes right shifter circuit <NUM>, left shifter circuit <NUM>, and left shifter circuit <NUM>. Input mantissa <NUM> is coupled to an adder circuit <NUM>. Adder circuit <NUM> further receives a constant value (N) <NUM> and outputs a sum of the input mantissa and a constant (N). For example, for an input mantissa that can take on values between <NUM> and <NUM> (mx, <NUM> ≤ mx < <NUM>), constant N may be equal to <NUM>. In various embodiments, adder <NUM> may be replaced with OR logic to implement (e.g., <NUM> OR mx), for example, as illustrated in further examples below. The output of adder <NUM> is coupled to an input of right shifter <NUM>. A shift input of right shifter <NUM>, which controls the shift operation, is coupled to input exponent <NUM> thought a negation circuit (-x) <NUM>, which receives the input exponent (ex) and produces a negative of the input exponent (-ex). For example, right shifter circuit <NUM> may produce a right shifted version of the input mantissa <NUM> having values between <NUM> and <NUM> as follows: <MAT>.

The above right shifter version of the input mantissa is a first output mantissa <NUM> for a value of <NUM>x for cases where the input sign bit is +<NUM> and the input exponent is less than zero (<NUM>).

Input mantissa <NUM> is also coupled to an input of left shifter <NUM>. A shift input of left shifter <NUM> is coupled to input exponent <NUM>. Accordingly, left shifter <NUM> produces a left shifted version of the input mantissa. Lower bits of the left shifted version of the input mantissa form a modulus function. In this example, lower bits of the left shifted version of the input mantissa correspond to a second output mantissa <NUM> for a value of <NUM>x when the input sign bit is +<NUM> and the input exponent is greater than or equal to zero (<NUM>) as follows: <MAT>.

In this example, first and second output mantissas <NUM>-<NUM> are coupled to multiplexer (Mux) <NUM>. An output of Mux <NUM> is coupled to an input of Mux <NUM>, and an output of Mux <NUM> produces the final output mantissa. Muxes <NUM> and <NUM> have selection control signals, Select <NUM> and Select <NUM>, based on the values of the input sign bit <NUM> and input exponent <NUM> to select one of output manitssas <NUM>-<NUM>.

The right and left shifted versions of the input mantissas may be subtracted from a constant (M) to form additional output mantissas. In this example, the output of Mux <NUM> is coupled to constant subtraction logic circuit <NUM> (M-x), which subtracts the output of Mux <NUM> from a constant value (e.g., <NUM> for a mantissa having values between <NUM>-<NUM>). Accordingly, the output of subtraction circuit may be either: <MAT> or <MAT>.

These alternative outputs form third and fourth output mantissas for a value of <NUM>x when the input sign bit is -<NUM> and the input exponent is positive or negative. Either output mantissa may be selected as the final output mantissas by Mux <NUM>.

A plurality of output exponents may also be generated from shifter circuits. In various embodiments, output exponents may be produced from adding upper bits of the left shifted input mantissa to a value of two (<NUM>) raised to a power of the input exponent (<NUM>ex). In this example, digital circuit <NUM> further includes left shifter circuit <NUM> having input coupled to a value of one (<NUM>) (e.g., a binary value of <NUM> or a bit value of <NUM>) and a shift input coupled to the input exponent <NUM>, where left shifting <NUM> by the input exponent results in <NUM>ex. The upper bits from left shifter <NUM> form an integer divide function (DIV). Thus, the outputs of shifter <NUM> and shifter <NUM> may be added in adder <NUM> to produce an output exponent <NUM> as follows: <MAT>.

The output of adder <NUM> is further coupled through a negation circuit (-<NUM>-x) <NUM> to produce another output exponent <NUM> as follows: <MAT>.

Finally, output exponent <NUM> is couple to a first input of Mux <NUM>, output exponent <NUM> is coupled to a second input of Mux <NUM>. Values of zero (<NUM>) <NUM> and negative one (-<NUM>) <NUM> are coupled to other inputs of Mux <NUM>. The final output mantissas and exponents for <NUM>x may selected as follows:.

Accordingly, digital circuit <NUM> further includes control logic <NUM> configured to receive the input exponent and the input sign bit and generate control signals (Select <NUM>, Select <NUM>) to a mantissa selection circuit (e.g., Muxes <NUM> and <NUM>) and exponent selection circuit (e.g., Mux <NUM>). Selection control signals Select <NUM> and Select <NUM> configure the multiplexers such that the output of Mux <NUM> is coupled to an output of the right shifter circuit <NUM> and an output of the Mux <NUM> is coupled to a zero (<NUM>) value <NUM> when the input sign bit is positive and the input exponent is less than <NUM>. Additionally, selection control signals Select <NUM> and Select <NUM> configure the multiplexers such that the output of Mux <NUM> is coupled to lower bits of the left shifter circuit <NUM> and an output of the exponent selection circuit is coupled a sum of upper bits of the left shifter circuit <NUM> and a value of two (<NUM>) raised to a power corresponding to the input exponent when the input sign bit is positive and the input exponent is greater than or equal to <NUM>. Next, selection control signals Select <NUM> and Select <NUM> configure the multiplexers such that the output of Mux <NUM> is coupled to an output of the right shifter circuit <NUM> through a constant subtraction logic circuit <NUM> and an output of the multiplexer <NUM> is coupled to a constant negative one (-<NUM>) value when the input sign bit is positive and the input exponent is less than <NUM>. Finally, selection control signals Select <NUM> and Select <NUM> configure the multiplexers such that the output of Mux <NUM> is coupled to lower bits of the left shifter circuit through the constant subtraction logic circuit <NUM> and an output of the multiplexer <NUM> is coupled a negative of a sum of upper bits of left shifter circuit <NUM> and a value of two (<NUM>) raised to a power corresponding to the input exponent when the input sign bit is negative and the input exponent is greater than the first value.

Muxes <NUM>, <NUM> and <NUM> are examples of selection circuits, and the other circuits in <FIG> are one example combinational logic mechanisms for receiving first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value and generating a plurality of output mantissas and plurality of output exponents.

<FIG> illustrates an example digital circuit 500A for generating approximations of <NUM>x according to another embodiment. As illustrated in this example, the above-described techniques may be used to also implement a digital circuit for generating approximations of <NUM>x. For approximations of <NUM>x, the mantissa is shifted based on the input exponent added to a constant (e.g., ex+<NUM>). Thus, digital circuit 500A further includes a +<NUM> adder circuit, which adds the value of <NUM> to the input exponent. In this example, the adder between the input mantissa and shifter <NUM> is replace with OR logic as mentioned above. The following table illustrates the behavior of digital circuit 500A:.

Muxes <NUM>, <NUM> and <NUM> are examples of selection circuits, and the other circuits in <FIG> are additional example combinational logic mechanisms for receiving first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value and generating a plurality of output mantissas and plurality of output exponents.

<FIG> illustrates another example digital circuit 500B for generating approximations of <NUM>x according to another embodiment. In this example, Mux <NUM> is removed and Mux <NUM> has one input coupled to the input mantissa and another input coupled to the input mantissa through OR logic <NUM>. In this example, shifter <NUM> is a bidirectional shifter, where the direction of the shift (left/right) is set by the shift polarity input (here, the input sign bit). For the shift polarity input s, shifting is (s==<NUM>: no shifting; S><NUM>: shift s positions left; S<<NUM>: shift s positions right). The behavior of digital circuit 500B is the same shown in Table <NUM> above. Removing adder circuit (+<NUM>) <NUM> results in the same behavior as illustrated in Table <NUM> above.

Muxes <NUM>, <NUM> and <NUM> are further examples of selection circuits, and the other circuits in <FIG> are additional example combinational logic mechanisms for receiving first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value and generating a plurality of output mantissas and plurality of output exponents.

<FIG> illustrates a normalization system <NUM> according to an embodiment. In this example, an input vector is received by approximation circuit <NUM> for determining Ax, where A is a power of two (<NUM>). Circuit <NUM> may be implemented using one of the techniques above. Circuit <NUM> generates values of Ax, which may be used to determine a normalization function such as an approximation of the Softmax function. For example, values of Ax may be stored in buffer <NUM>. The values may be added together in summation circuit <NUM>. Divider circuit <NUM> may access values in buffer <NUM> and the summed value ∑Ax to produce normalized values: Ax/∑Ax. The normalized values may, for example, be coupled to a matrix multiplication circuit <NUM>. In some embodiments, the normalized values are used to process neural network data, for example.

The following illustrate how the above circuit behavior may approximate a Softmax function. The softmax function is defined as: <MAT>.

A function that is "similar" to exi in Softmax, may have the following properties: easy to compute in floating point, strictly monotonous, and quickly growing. In this example, bfloat16 is used as an example, but is extendible to fp32 and bfloat. A bfloat16 number is defined as: <MAT>.

Where sx the sign of x (e.g., sx = +<NUM> or sx = -<NUM>), ex the exponent of x (e.g., -<NUM> ≤ ex <= <NUM>), and mx the mantissa of x (e.g., <NUM> ≤ mx < <NUM>). When calculating <NUM>ex in bfloat16, the result is <NUM> for ex < -<NUM> and infinity for ex > <NUM> - so check can be performed at the boundaries - but no need to implement for large exponents. Also, for IEEE FP numbers, there is an exponent offset.

Softmax can be approximated using powers of <NUM>. For example, Softmax<NUM> may be defined as follows: <MAT>.

It may be noted that Softmax(x) = Softmax2(log2(e)*x) = Softmax2(<NUM>*x). In other words, to get a better approximation, one can multiply x by <NUM> before invoking the circuitry that approximates <NUM>x.

Next, an approximation of <NUM>xi may be as follows: <MAT>.

Approximating <MAT> with <MAT>. Then: <MAT>.

There are four cases for different values of the sign bit and input exponent:.

Case A: sx = +<NUM> and ex < <NUM> (e.g., small positive numbers): <MAT> <MAT>.

Case B: sx = +<NUM> and ex ≥ <NUM> (e.g., large positive numbers): <MAT> <MAT>.

Note that the implementation is very simple, since this is shifting and "bit-picking" with -<NUM> ≤ ex <= <NUM>. (e.g., mx is left-shifted: the lower <NUM> bits are used in the mantissa and the upper bits are used in the exponent as mentioned above).

Case C: sx = -<NUM> and ex < <NUM> (e.g., small negative numbers): <MAT> <MAT>.

Case D: sx = -<NUM> and ex ≥ <NUM> (e.g., large negative numbers): <MAT>.

The following illustrates Softmax approximated using powers of <NUM>. For example, Softmax<NUM> may be defined as follows: <MAT>.

Case A: sx = +<NUM> and ex < -<NUM> (e.g., small positive numbers): <MAT>.

Case B: sx = +<NUM> and ex ≥ -<NUM> (e.g., large positive numbers): <MAT>.

Again, the implementations comprise shifting and "bit-picking" with -<NUM> ≤ ex <= <NUM>. (e.g., mx is left-shifted: the lower <NUM> bits may be used in the mantissa and the upper bits are used in the exponent).

Case C: sx = -<NUM> and ex < -<NUM> (e.g., small negative numbers): <MAT>.

Case D: sx = -<NUM> and ex ≥ -<NUM> (e.g., large negative numbers): <MAT>.

<FIG> illustrates a method <NUM> according to an embodiment. At <NUM>, first digital bits and second digital bits are received in a digital circuit. The first digital bits represent a mantissa of an input value, and the second digital bits represent an exponent of the input value. The input value may be in a floating point format, for example, and further include a sign bit. At <NUM>, a plurality of output mantissas and plurality of output exponents are generated. The output mantissas and output exponents correspond to approximate values of a power of two (<NUM>) raised to a power of the input value x (e.g., <NUM>x, <NUM>x,. At <NUM>, one of the plurality of output mantissas and one of the plurality of output exponents are selected based on the input exponent and the input sign bit. Accordingly, the method <NUM> generates digital values (e.g., in a floating point format) corresponding to an approximation of <NUM>x, <NUM>x, etc., which may be used to approximate a Softmax function in a neural network, for example. The circuits for outputting digital values approximating a power of <NUM> raised to a power of an input value may also be used in other applications.

<FIG> illustrates a neural network processing system according to some embodiments. In various embodiments, neural networks according to the present disclosure may be implemented and trained in a hardware environment comprising one or more neural network processors. A neural network processor may refer to various graphics processing units (GPU) (e.g., a GPU for processing neural networks produced by Nvidia Corp®), field programmable gate arrays (FPGA) (e.g., FPGAs for processing neural networks produced by Xilinx®), or a variety of application specific integrated circuits (ASICs) or neural network processors comprising hardware architectures optimized for neural network computations, for example. In this example environment, one or more servers <NUM>, which may comprise architectures illustrated in Fig. <NUM> above, may be coupled to a plurality of controllers <NUM>(<NUM>)-<NUM>(M) over a communication network <NUM> (e.g. switches, routers, etc.). Controllers <NUM>(<NUM>)-<NUM>(M) may also comprise architectures illustrated in Fig. <NUM> above. Each controller <NUM>(<NUM>)-<NUM>(M) may be coupled to one or more NN processors, such as processors <NUM>(<NUM>)-<NUM>(N) and <NUM>(<NUM>)-<NUM>(N), for example. NN processors <NUM>(<NUM>)-<NUM>(N) and <NUM>(<NUM>)-<NUM>(N) may include a variety of configurations of functional processing blocks and memory optimized for neural network processing, such as training or inference. NN processors in <FIG> may include digital circuits described herein for normalizing values (e.g., an approximation of the Softmax function). The NN processors are optimized for neural network computations. Server <NUM> may configure controllers <NUM> with NN models as well as input data to the models, which may be loaded and executed by NN processors <NUM>(<NUM>)-<NUM>(N) and <NUM>(<NUM>)-<NUM>(N) in parallel, for example. Models may include layers and associated weights as described above, for example. NN processors may load the models and apply the inputs to produce output results. NN processors may also implement training algorithms, for example. Digital circuits described herein may be used in both training and inference, for example.

In various embodiments, the present disclosure includes systems, methods, and apparatuses for generating approximated values that may be used for normalization. The following examples may be used alone or in various combinations.

In one embodiment, the present disclosure includes a digital circuit comprising: combinational logic receiving first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value, the combinational logic generating a plurality of output mantissas and plurality of output exponents corresponding to an approximate value of a power of two (<NUM>) raised to a power of the input value when the input value is positive and negative and when the input exponent is above and below a first value; and two or more selection circuits configured to receive the plurality of output mantissas and the plurality of output exponents, the selection circuits comprising selection control inputs coupled to the input exponent and an input sign bit of the input value to select one of the plurality of output mantissas and one of the plurality of output exponents.

In another embodiment, the present disclosure includes a method for generating normalized values comprising: receiving, in combinational logic comprising one or more shifter circuits, first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value; generating, in the combinational logic, a plurality of output mantissas and plurality of output exponents corresponding to an approximate value of a power of two (<NUM>) raised to a power of the input value when the input value is positive and negative and when the input exponent is above and below a first value; and selecting, by two or more selection circuits configured to receive the plurality of output mantissas and the plurality of output exponents, one of the plurality of output mantissas and one of the plurality of output exponents based on the input exponent and an input sign bit of the input value.

In another embodiment, the present disclosure includes digital circuit comprising: combinational logic means for receiving first digital bits representing an input mantissa of an input value and second digital bits representing an input exponent of the input value, the combinational logic means generating a plurality of output mantissas and plurality of output exponents corresponding to an approximate value of a power of two (<NUM>) raised to a power of the input value when the input value is positive and negative and when the input exponent is above and below a first value; and selection circuit means for receiving the plurality of output mantissas and the plurality of output exponents and selecting one of the plurality of output mantissas and one of the plurality of output exponents based on the input exponent and an input sign bit of the input value.

In one embodiment, the combinational logic generates a plurality of shifted versions of the input mantissa based on the input exponent to produce the plurality of output mantissas and the plurality of output exponents.

In one embodiment, the two or more selection circuits produce: a first output mantissa comprising a sum of a first shifted version of the input mantissa and a first constant and a first output exponent having a zero value when the input sign bit is positive and the input exponent is less than a first value; a second output mantissa comprising a modulus of a second shifted version of the input mantissa and a second output exponent having a digital value of one (<NUM>) shifted based on the input exponent added to an integer division of the second shifted version of the input mantissa when the input sign bit is positive and the input exponent is greater than the first value; a third output mantissa comprising the sum of the first shifted version of the input mantissa the first constant, subtracted from a second constant, and a third output exponent having negative one (-<NUM>) value when the input sign bit is negative and the input exponent is less than the first value; and a fourth output mantissa comprising a modulus of the second shifted version of the input mantissa, subtracted from the second constant, and a negation of the second output exponent minus one (<NUM>) when the input sign bit is negative and the input exponent is greater than the first value.

In one embodiment, the combinational logic comprises one or more shifter circuits having an input coupled to the input mantissa and a shift input coupled to the input exponent, wherein the one or more shifter circuits produce left and right shifted versions of the input mantissa.

In one embodiment, a right shifted version of the input mantissa is used to form a first output mantissa and a second output mantissa, and wherein lower bits of a left shifted version of the input mantissa are used to form a third output mantissa and a fourth output mantissa.

In one embodiment, the right shifted version of the input mantissa is subtracted from a constant to form the second output mantissa.

In one embodiment, the left shifted version of the input mantissa is subtracted from a constant to form the fourth output mantissa.

In one embodiment, upper bits of a left shifted version of the input mantissa is used to form a first output exponent and a second output exponent.

In one embodiment, the upper bits of the left shifted version of the input mantissa is added to a value generated based on the input exponent to form the first output exponent and the second output exponent.

In one embodiment, the value generated based on the input exponent comprises a bit left shifted based on the input exponent.

In one embodiment, said added upper bits of the left shifted version of the input mantissa and the value generated based on the input exponent are negated to produce the second output exponent.

In one embodiment, the one or more shifter circuits comprise barrel shifter circuits.

In one embodiment, the one or more shifter circuits comprise: a right shifter circuit having a first input coupled to the input mantissa through a logic circuit configured to add the input mantissa to a constant and a shift input coupled to the input exponent through a logic circuit configured to negate the input exponent; and a first left shifter circuit having a first input coupled to receive the input mantissa and a shift input coupled to the input exponent.

In one embodiment, the one or more shifter circuits further comprise a second left shifter circuit having a first input coupled to receive a digital value of one (<NUM>) and a shift input coupled to the input exponent, wherein an output of the first left shifter circuit and the second left shifter circuit are added together.

In one embodiment, the two or more selection circuits comprise a first multiplexer having a first input coupled to an output of the right shifter circuit and a second input coupled to lower bits of the first left shifter circuit.

In one embodiment, the two or more selection circuits further comprise a second multiplexer having a first input coupled an output of the first multiplexer and a second input coupled to the output of the first multiplexer through a logic circuit configured to subtract a value on an input of the logic circuit from a constant.

In one embodiment, the two or more selection circuits comprise a multiplexer, the multiplexer comprising: a first input coupled to a sum of upper bits of the first left shifter circuit and a value of two (<NUM>) raised to a power corresponding to the exponent; a second input coupled to a negative version of the sum; a third input coupled to a zero (<NUM>) value; and a fourth input coupled to a negative one (-<NUM>) value; and an output producing a final output exponent.

In one embodiment, the digital circuit further comprises control logic configure to receive the input exponent and the input sign bit and generate control signals to at least a mantissa selection circuit and an exponent selection circuit, wherein: an output of the mantissa selection circuit is coupled to an output of the right shifter circuit and an output of the exponent selection circuit is coupled to a zero (<NUM>) value when the input sign bit is positive and the input exponent is less than a first value; an output of the mantissa selection circuit is coupled to lower bits of the left shifter circuit and an output of the exponent selection circuit is coupled a sum of upper bits of the first left shifter circuit and a value of two (<NUM>) raised to a power corresponding to the input exponent when the input sign bit is positive and the input exponent is greater than the first value; an output of the mantissa selection circuit is coupled to an output of the right shifter circuit through a constant subtraction logic circuit and an output of the exponent selection circuit is coupled to a constant negative one (-<NUM>) value when the input sign bit is positive and the input exponent is less than a first value; an output of the mantissa selection circuit is coupled to lower bits of the left shifter circuit through the constant subtraction logic circuit and an output of the exponent selection circuit is coupled a negative of a sum of upper bits of the first left shifter circuit and a value of two (<NUM>) raised to a power corresponding to the input exponent when the input sign bit is negative and the input exponent is greater than the first value.

Claim 1:
A digital circuit comprising:
combinational logic (<NUM>) receiving first digital bits (<NUM>) representing an input mantissa of an input value and second digital bits representing an input exponent of the input value, the combinational logic (<NUM>) generating a plurality of output mantissas and plurality of output exponents (<NUM>) corresponding to an approximate value of a power of two raised to a power of the input value when the input value is positive and negative and when the input exponent is above and below a first value; and
two or more selection circuits (<NUM>) configured to receive the plurality of output mantissas and the plurality of output exponents (<NUM>), the selection circuits (<NUM>) comprising selection control inputs coupled to the input exponent and an input sign bit of the input value to select one of the plurality of output mantissas and one of the plurality of output exponents.