Patent Description:
Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, <CIT> discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published <CIT> discloses a CMOS inverter also based upon similar strained silicon technology.

<CIT>discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

<CIT> discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

<CIT> discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, <CIT>discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

<CIT>discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO<NUM>/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

An article entitled "<NPL> discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a <NUM> thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to <NPL>) further discusses the light emitting SAS structures of Tsu.

Published International Application <CIT>, discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.

Published Great <CIT> discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc, can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

<CIT>is directed towards methods and structures for forming semiconductor FinFET devices that include providing an APT layer formed beneath a semiconductor fin.

<CIT> is directed towards a semiconductor device comprising a dopant blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers including a plurality og stacked base semiconductor monolayers and at least one non-semiconductor monolayer.

Despite the advantages provided by such structures, further developments may be desirable for integrating advanced semiconductor materials in various semiconductor devices.

A method for making a semiconductor device includes forming a plurality of fins on a substrate. The fins are formed by forming a plurality of spaced apart lower semiconductor fin portions extending vertically upward from the substrate, and forming at least one respective superlattice punch-through stop layer on each of the lower fin portions. Each superlattice punch-through stop layer includes a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A respective upper semiconductor fin portion is formed above each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom. The method also includes forming source and drain regions at opposing ends of the fins, and forming a gate overlying the fins. Forming the at least one respective superlattice punch-through stop layer includes forming a respective plurality of vertically stacked superlattice punch-through stop layers on each of the lower fin portions with a respective bulk semiconductor layer between each of the superlattice punch-through stop layers. The bulk semiconductor layers have opposite conductivity types defining an embedded junction therebetween.

The method may also include forming an insulating layer on the substrate surrounding the lower semiconductor fin portions.

By way of example, forming the plurality of fins may further include forming a superlattice layer on the substrate, epitaxially growing a bulk semiconductor layer on the superlattice layer, and etching a plurality of spaced apart trenches extending through the bulk semiconductor layer, the superlattice layer, and into the substrate to define the respective lower semiconductor fin portions, superlattice punch-through stop layers, and upper semiconductor fin portions. The method may further include performing a thermal anneal after forming the plurality of fins.

Each base semiconductor portion may comprise silicon, germanium, etc. The at least one non-semiconductor monolayer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example. Furthermore, the gate may include an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer. Moreover, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the non-semiconductor layer therebetween.

A related semiconductor device includes a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins includes a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through stop layer on the lower fin portion. The superlattice punch-through stop layer includes a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin also includes an upper semiconductor fin portion above the at least one superlattice punch-through stop layer and extending vertically upward therefrom. The semiconductor device also includes source and drain regions at opposing ends of the fins, and a gate overlying the fins. The at least one respective superlattice punch-through stop layer comprises a respective plurality of vertically stacked superlattice punch-through stop layers on each of the lower fin portions with a respective bulk semiconductor layer between each of the superlattice punch-through stop layers. The bulk semiconductor layers have opposite conductivity types defining an embedded junction therebetween. The invention relates to a method and apparatus as set forth in the claims. It will be understood that aspects of the disclosure falling within the scope of the claims are part of the invention whereas aspects of the disclosure falling outside the scope of the claims are not part of the invention.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

The present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level. Further, the invention relates to the identification, creation, and use of improved materials for use in semiconductor devices.

Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", <MAT> and <MAT> for electrons and holes respectively, defined as: <MAT> for electrons and: <MAT> for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B. ), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicants theorize without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, the Applicants have identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to <FIG> and <FIG>, the materials or structures are in the form of a superlattice <NUM> whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice <NUM> includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of <FIG>.

Each group of layers 45a-45n of the superlattice <NUM> illustratively includes a plurality of stacked base semiconductor monolayers <NUM> defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer <NUM> thereon. The energy band-modifying layers <NUM> are indicated by stippling in <FIG> for clarity of illustration.

The energy band-modifying layer <NUM> illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within a crystal lattice of adjacent base semiconductor portions" it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer <NUM> therebetween, as seen in <FIG>. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a-46n through atomic layer deposition techniques so that not all (i.e., less than full or <NUM>% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers <NUM> of semiconductor material are deposited on or over a non-semiconductor monolayer <NUM>, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

More than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicants theorize without wishing to be bound thereto that energy band-modifying layers <NUM> and adjacent base semiconductor portions 46a-46n cause the superlattice <NUM> to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers <NUM> may also cause the superlattice <NUM> to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice <NUM>. These properties may thus advantageously allow the superlattice <NUM> to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice <NUM> may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. As a result of the band engineering, the superlattice <NUM> may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice <NUM> also illustratively includes a cap layer <NUM> on an upper layer group 45n. The cap layer <NUM> may comprise a plurality of base semiconductor monolayers <NUM>. The cap layer <NUM> may have between <NUM> to <NUM> monolayers of the base semiconductor, and, more preferably between <NUM> to <NUM> monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer <NUM> may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other examples, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer <NUM> provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or <NUM>% coverage). For example, with particular reference to the atomic diagram of <FIG>, a <NUM>/<NUM> repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

With different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice <NUM> in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicants wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The <NUM>/<NUM> repeating structure shown in <FIG> and <FIG>, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is <NUM> and for the <NUM>/<NUM> SiO superlattice in the X direction it is <NUM> resulting in a ratio of <NUM>. Similarly, the calculation for holes yields values of <NUM> for bulk silicon and <NUM> for the <NUM>/<NUM> Si/O superlattice resulting in a ratio of <NUM>.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the <NUM>/<NUM> Si/O example of the superlattice <NUM> may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice <NUM> may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to <FIG>, another example of a superlattice <NUM>' that can be used with the invention and having different properties is now described. In this example, a repeating pattern of <NUM>/<NUM>/<NUM>/<NUM> is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice <NUM>'. The energy band-modifying layers <NUM>' may each include a single monolayer. For such a superlattice <NUM>' including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of <FIG> not specifically mentioned are similar to those discussed above with reference to <FIG> and need no further discussion herein.

All of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other examples, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other examples, all of the base semiconductor portions may be a different number of monolayers thick.

In <FIG>, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction. " However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

<FIG> shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> shown in <FIG> (represented by dotted lines). The directions refer to the unit cell of the <NUM>/<NUM> Si/O structure and not to the conventional unit cell of Si, although the (<NUM>) direction in the figure does correspond to the (<NUM>) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (<NUM>) and (<NUM>) directions in the figure correspond to the (<NUM>) and (-<NUM>) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the <NUM>/<NUM> Si/O structure.

It can be seen that the conduction band minimum for the <NUM>/<NUM> Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (<NUM>) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the <NUM>/<NUM> Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

<FIG> shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (<NUM>) direction.

<FIG> shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure of the superlattice <NUM>' of <FIG> (dotted lines). Due to the symmetry of the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure, the calculated band structures in the (<NUM>) and (<NUM>) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (<NUM>) stacking direction. Note that in the <NUM>/<NUM>/<NUM>/<NUM> Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the <NUM>/<NUM>/<NUM>/<NUM> superlattice <NUM>' should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Using the above-described measures, one can select materials having improved band structures for specific purposes. Referring more particularly to <FIG>, a first example not forming part of the present invention would be a superlattice material layer <NUM> in a vertical.

semiconductor device <NUM>, such as a FINFET, in which the superlattice material layer is used for dopant blocking within each semiconductor fin <NUM>. More particularly, it may generally be desirable to dope a bottom portion <NUM> of a fin <NUM> to help reduce leakage (a P-type dopant is used in the illustrated NMOS example, but an N-type dopant may be used for a PMOS device, as will be discussed further below). However, it may also be desirable to have an upper channel portion <NUM> of the fin <NUM> remain undoped, but it may be difficult to prevent dopant creep from the bottom of the fin <NUM> into the upper channel portion of the fin. The superlattice layer <NUM> may advantageously provide a self-aligned punch-through stop layer for preventing dopant from the lower portion <NUM> of the fin <NUM> from creeping into the upper undoped portion <NUM> of the fin, in addition to the leakage reduction properties of the superlattice itself, as described above. The upper (undoped) portion <NUM> of each fin <NUM> may advantageously be epitaxially grown on top of a respective superlattice layer <NUM>, as also described above.

The fins <NUM> are formed on a substrate <NUM> (e.g., silicon substrate), and a source and drain regions <NUM>, <NUM> are formed at opposing ends of the fins <NUM> (see <FIG>). An insulating layer <NUM> (e.g., SiO<NUM>) is formed over the fins <NUM> and source and drain regions <NUM>, <NUM>. Moreover, a gate <NUM> is formed overlying the fins <NUM> and the insulating layer <NUM>.

An embodiment of the present invention is shown in <FIG>, in which a vertical device <NUM>' includes a "quasi-BOX" structure below the upper channel portion <NUM>', in which a series of vertically spaced-apart superlattice layers <NUM>' have regions or layers <NUM>', <NUM>' of a bulk semiconductor (e.g., Si) stacked therebetween and with alternating dopant types. In the illustrated example, the stack includes a bottom superlattice layer <NUM>' on the Si substrate <NUM>', an N-type Si layer <NUM>' on the bottom superlattice layer, an intermediate superlattice layer on the N-type Si layer, a P-type Si layer <NUM>' on the intermediate superlattice layer, and an upper superlattice layer on the P-type Si layer. The Si channel <NUM>' may advantageously be grown on top of the upper superlattice layer <NUM>', as noted above. However, in some embodiments the channel may reside partially or completely in the upper superlattice layer <NUM>', if desired. This quasi-BOX structure may conceptually be considered to perform a similar function to a buried oxide (BOX) layer, but here the quasi-BOX stack provides an added benefit of an embedded P-N junction to provide further isolation of the channel region, as will be appreciated by those skilled in the art.

In accordance with a further example not forming part of the present invention and as described with reference to <FIG>, a "quasi-planar" semiconductor device <NUM>" is similar to the FINFET example described above with respect to <FIG>, but with a shorter and wider profile for the fins. This example may be advantageous in certain implementations, as it may help relax fin patterning requirements, for example.

An example method for making a CMOS version of the semiconductor device <NUM> will now be described with reference to <FIG>. Beginning at Block <NUM>, a blanket superlattice layer <NUM> may be formed on a silicon substrate <NUM>, followed by an epitaxial silicon growth above the superlattice layer (<FIG>, (i)). Deep punch-through stop implants (e.g., N-type for PMOS, P-type for NMOS) may then be performed at Block <NUM> (<FIG>, (ii)), followed by a fin <NUM> patterning/isolation processing module, at Block <NUM> (<FIG>, (iii)). Gate <NUM> and source/drain <NUM>, <NUM> processing may then be performed using typical steps for FINFET processing, for example, at Blocks <NUM>-<NUM> (<FIG>, (iv)).

Claim 1:
A method for making a semiconductor device (<NUM>, <NUM>', <NUM>") comprising:
forming a plurality of fins (<NUM>) on a substrate (<NUM>) by
forming a plurality of spaced apart lower semiconductor fin portions (<NUM>, <NUM>', <NUM>") extending vertically upward from the substrate,
forming at least one respective superlattice punch-through stop layer (<NUM>, <NUM>', <NUM>") on each of the lower semiconductor fin portions, each superlattice punch-through stop layer including a plurality of stacked groups of layers (45a-45n, 45a'-45n'), each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers (<NUM>, <NUM>') defining a base semiconductor portion and at least one non-semiconductor monolayer (<NUM>, <NUM>') constrained within a crystal lattice of adjacent base semiconductor portions, and
forming a respective upper semiconductor fin portion (<NUM>, <NUM>', <NUM>") on each of the at least one superlattice punch-through stop layers and extending vertically upward therefrom;
forming source and drain regions (<NUM>, <NUM>) at opposing ends of the plurality of fins (<NUM>); and
forming a gate (<NUM>) overlying the plurality of fins (<NUM>);
characterized in that forming the at least one respective superlattice punch-through stop layer comprises forming a respective plurality of vertically stacked superlattice punch-through stop layers (<NUM>') on each of the lower semiconductor fin portions with a respective bulk semiconductor layer (<NUM>', <NUM>') between each of the superlattice punch-through stop layers, the bulk semiconductor layers having opposite conductivity types defining an embedded junction therebetween.