Patent Description:
In an attempt to meet workload demands, some examples increase different types of processing units or elements (e.g., multiply-and-accumulate (MAC) units) to increase processing power. The processing units may nonetheless suffer from degraded performance due to blocking caused by high latency data fetch and/or memory access operations. Thus, merely scaling compute power may not yield performance gains. Indeed, including idle processing units may be detrimental to the overall power/energy of the system since idling processing units may increase the leakage component, increase hardware costs and a size of an overall package.

Turning now to <FIG>, a multi-buffered memory access process <NUM> is illustrated that provides a flexible schedule based approach of data movements to reduce overall memory circuitry and latency of memory fetches. The process <NUM> may move data from lower levels of memory, such as storage <NUM>, to higher levels of a memory hierarchy such as register file <NUM> (e.g., a hardware register) having dedicated write portions 104a, 106a and read portions 104b, 106b. The register file <NUM> may include a number of data banks, including the zero double buffer bank <NUM> and the N double buffer bank <NUM>. The register file <NUM> may include shared read-write circuitry to store data and reduce blocking of the processor <NUM> due to memory accesses, while also reducing an overall size of the register file <NUM>.

The process <NUM> may include writing data from storage <NUM> into write portions 104a, 106a according to one or more first clock cycles of a first clock signal <NUM> of the first clock <NUM>. The register file <NUM> may be a local storage (e.g., memory device) of a processor <NUM> (e.g., on-chip registers) and may be allocated close to compute processing elements 120a-120n. The register file <NUM> may be accessed more frequently than distant, higher levels of memory hierarchy such as storage <NUM> (e.g., compute-near-Memory) which may be a static random-access memory (SRAM) and/or dynamic random access memory (DRAM). Thus, some embodiments include register files <NUM> that are close to processing elements 120a-120n to enable reuse of data to bypass higher latency memory fetches.

The process <NUM> may include transferring data into read portions 104b, 106b according to a second clock signal (e.g., a pulse) of the second clock <NUM>, <NUM>. Each clock cycle of the second clock signal may correspond (e.g., may be as long as) several cycles of the first clock signal. In some embodiments, the second clock <NUM> may be omitted and the second clock signal may be a modified version of the first clock signal. The second clock signal is different from the first clock signal to avoid overwriting data in the read portions 104b, 106b that is not yet read by the processor <NUM>. After the data in the read portions 104b, 106b is read by the processor <NUM>, new data may be transferred (e.g., according to the second clock signal) from the write portions 104a, 106a to overwrite the data in the read portions 104b, 106b and be stored in the read portions 104b, 106b. In some embodiments, the second clock signal is timed to cause transfer of data from the write portions 104a, 106a to the read portions 104b, 106b between read operations of the read portions 104b, 106b by the processor <NUM>, and write operations of data from storage <NUM> to the write portion 104a, 106a. The data may be transferred from the write portions 104a, 106a to the read portions 104b, 106b in one cycle of the second clock signal.

Process <NUM> may further read data from read portions 104b, 106b, according to one or more second clock cycles of the first clock signal following (e.g., immediately subsequent to) the transfer based on the second clock signal <NUM>. For example, the processor <NUM> may read the data stored in read portions 104b, 106b to execute operations based on the data with the PE 120a-120n. In some embodiments, the processor <NUM> may only be able to access the read portions 104b, 106b and not the write portions 104a, 106a. Further, data from the storage <NUM> may only be directly written into the write portions 104a, 106a and not the read portions 104b, 106b. Doing so may be reduce the circuity for accessing the zero double buffer bank <NUM> and the N double buffer bank <NUM> since duplicative circuitry may be eliminated. Thus, the write portions 104a, 106a may be dedicated to write operations from the storage <NUM>, while the read portion 104b, 106b may be dedicated to read operations from the processor <NUM>.

For example, the write portions 104a, 106a may receive data that is external to the register file <NUM> and from elements external to the register file <NUM>. The write portions 104a, 106a may not be read by elements external to the register file <NUM>. The read portions 104b, 106b may be read by elements external to the register file <NUM>, but may not be written to by elements external to the register file <NUM>. Data may be transferred internally within the register file <NUM> from the write portions 104a, 106a to the read portions 104b, 106b, but as noted, external elements may have limited interactions with the write portions 104a, 106a to bypass reading the write portions 104a, 106a, and bypass writing to the read portions 104b, 106b.

During consecutive clock cycles of the first clock signal of first clock <NUM>, data may be written into the write portions 104a, 106a, and read from read portions 104b, 106b. Data may be transferred from the write portions 104a, 106a to the read portions 104b, 106b between portions of the clock cycles (e.g., between phases) of the first clock <NUM> to avoid data errors such as overwriting. For example, data may be written into the write portions 104a, 106a during one or more first clock cycles of the first clock signal. During subsequent clock cycles, the loaded data may be transferred from the write portions 104a, 106a to the read portions 104b, 106b based on the second clock signal. During one or more subsequent clock cycles of the first clock signal after the second clock signal has transferred data from the write portions 104a, 106a to the read portions 104b, 106b, the processor <NUM> may read data from the read portions 104b, 106b.

Such operations may repeat over the first and second clock signals. For example, in one or more first clock cycles of the first clock signal, first data may be read from the read portions 104b, 106b (that may have been stored in one or more previous clock cycles of the first clock signal) and second data may be stored in the write portions 104a, 106a from the storage <NUM>. The second data may be transferred from the write portions 104a, 106a to the read portions 104b, 106b according to the second clock signal and to overwrite the first data after the first data is read from the read portions 104b, 106b. In some embodiments, the read of the first data from the read portions 104b, 106b and write of the second data in the write portions 104a, 106a may occur concurrently to avoid overwriting errors.

Thereafter, in one or more second clock cycles of the first clock signal, the second data may be read from the read portions 104b, 106b (that were stored in the one or more first clock cycles) and third data may be stored in the write portions 104a, 106a. The third data may be transferred from the write portions 104a, 106a to the read portions 104b, 106b according to the second clock signal and to overwrite the second data. In some embodiments, the read of the second data from the read portions 104b, 106b and write of the third data may in the write portions 104a, 106a may occur concurrently. Such a process <NUM> may continue for a plurality of consecutive clock cycles of the first clock signal and the second clock signal.

By including dedicated write portions 104a, 106a, and dedicated read portions 104a, 104b, the register file <NUM> may be an area-efficient, multi-buffered (e.g., double-buffered) memory with shared read/write circuits to reduce area (e.g., by over <NUM>% or more) over other implementations while reducing waiting by the PEs 120a-120n for memory fetches. Thus, some embodiments enhance throughput at a reduced memory size by sharing the read and write circuitry between the first (e.g., active) register file and a buffered (e.g., shadow) register file to reduce memory size.

In some embodiments, more than one register file <NUM> may be provided. For example, a plurality of register files <NUM> may be included depending on the application. For example, if a deep neural network is implemented, first register file may be dedicated to input features (IF), a second register file may be dedicated to filters (FL) a third register file may be dedicated to output features (OF) register (e.g., for calculations that are determined based on the FL and the IF). If the register file <NUM> is modified to be an OF register, the above process <NUM> may be reversed so that the processor <NUM> may write to dedicated write portions, data may be transferred from the write portions to read portions and then transferred to another storage from the read portions.

Thus, some embodiments may maintain high throughput performance at a reduced cost and size by avoiding duplicative hardware overheads implemented by other designs (e.g., a ping-pong double-buffered register file implementations). In some embodiments, the PEs 120a-120n may include deep neural network (DNN) accelerators and/or arithmetic logic units (ALU), graphics accelerators, artificial intelligence accelerators, etc. Some embodiments may be implemented in conjunction with high performance microprocessors, graphics, and other application specific hardware accelerators.

For example, in a higher performance microprocessor, a double-buffered register file such as register file <NUM> may be an instance of one set of register files being read by the ALU and another set of register files are written to by the ALU in order to achieve computational overlaps for enhancing performance. The process <NUM> may be implemented in high performance general purpose computing processes, graphics processes, and/or other hardware accelerator processes. Some embodiments may be applicable to artificial intelligence applications such as imaging, video, and speech recognition.

<FIG> shows a method <NUM> of accessing multi-buffered registers. The method <NUM> may generally be implemented with the embodiments described herein, for example, the process <NUM> (<FIG>), already discussed. In an embodiment, the method <NUM> is implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

For example, computer program code to carry out operations shown in the method <NUM> may be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state-setting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and/or other structural components that are native to hardware (e.g., host processor, central processing unit/CPU, microcontroller, etc.).

Illustrated processing block <NUM> includes identifying a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. Illustrated processing block <NUM> writes data to the first portion of the plurality of registers. Illustrated processing block <NUM> transfers the data from the first portion to the second portion. In some embodiments, the method <NUM> includes transferring the data in response to a transfer clock pulse being identified. In some embodiments, the method <NUM> further includes writing the data to the first portion during one or more first clock cycles prior to the transfer clock pulse being identified. In some embodiments, the method <NUM> further includes reading the data in the first portion during one or more second clock cycles after the transfer clock pulse is identified.

In some embodiments, the plurality of registers includes a first register associated with input features associated with a neural network, a second register associated with filters associated with the neural network, and a third register associated with output features associated with the neural network. In some embodiments, the method <NUM> further includes in each of a plurality of consecutive clock cycles, retrieving data from a memory and storing the retrieved data in the first portion. Furthermore, some embodiments of the method <NUM> include in each of a plurality of consecutive clock cycles, reading data from the second portion. In some embodiments, the method <NUM> further includes controlling read and write operations to the first and second portions based on a first clock signal and transferring data between the first and second portions based on a second clock signal that is different from the first clock signal.

<FIG> illustrates a double-buffer register file architecture <NUM> with shared read and write circuitry. <FIG> illustrates timing diagrams <NUM> of accesses and transfers of data in the architecture <NUM>. Architecture <NUM> may be associated with a machine learning model such as a DNN and/or CNN. First clock <NUM> may generate the first clock signal <NUM> while a second clock <NUM> may generate the transfer clock signal <NUM>.

As illustrated in <FIG>, the architecture <NUM> includes an input features register file <NUM>, filter register file <NUM> and output features register file <NUM>. The input features register file <NUM> includes first double buffer bank <NUM>-N double buffer bank <NUM>. The write portions 304a, 306a may each include one write port in some embodiments, and the read portions 304b, 306b may each include a plurality of read ports (e.g., <NUM> or more) in some embodiments.

The filter register file <NUM> includes first double buffer bank <NUM>-N double buffer bank <NUM>. Write portions 310a, 312a may each include one write port in some embodiments, and the read portions 310b, 312b may each include one read port in some embodiments.

The output features register file <NUM> includes first double buffer bank <NUM>-N double buffer bank <NUM>. Write portions 316a, 318a may each include one write port in some embodiments, and the read portions 316b, 318b may each include one read port in some embodiments.

Access circuit <NUM> may control write accesses to the input features register file <NUM>, filter register file <NUM> and output features register file <NUM>. In some embodiments, the access circuit <NUM> may be a part of the input features register file <NUM>, filter register file <NUM> and output features register file <NUM>. Furthermore, while the access circuit <NUM> is shown schematically as one component, it will be understood that other implementations may be possible. For example, each of the input features register file <NUM>, filter register file <NUM> and output features register file <NUM> may include different logic that controls write operations and read operations as described herein and similar to the access circuit <NUM>. The access circuit <NUM> may include hardware, such as configurable logic and/or fixed-functionality hardware logic.

Access circuit <NUM> may store data from storage <NUM> (e.g., solid state drive, hard disk drive, SRAM, DRAM, etc.) into the write portions 304a, 306a, 310a, 312a and in accordance with a first clock signal <NUM> (<FIG>) from the first clock <NUM>. The access circuit <NUM> may store data computed by processor <NUM> into the write portions 316a, 318a and in accordance with the first clock signal <NUM>. The first clock signal <NUM> may correspond to access cycles <NUM> of timing diagram <NUM> (<FIG>). The upper graph of access cycles <NUM> corresponds to actions (e.g., writes into) associated with the write portions 304a, 306a, 310a, 312a, 316a, 318a and the lower graph of access cycles <NUM> corresponds to actions (e.g., reads from) associated with the read portions 304b, 306b, 310b, 312b, 316b, 318b. Further, transfers may occur between read and writes. In the example of access cycles <NUM>, the write actives are denoted with a "WA," the read actives are denoted with a "RA," and transfers are denoted with a "T. " Multiple reads and writes may occur during each read active and write active respectively. Further, multiple transfers may occur during each transfer. The access circuit <NUM> may include configurable logic and/or fixed-functionality logic hardware.

Further, the access circuit <NUM> may control read accesses to the input features register file <NUM>, filter register file <NUM> and output features register file <NUM>. For example, access circuit <NUM> may read data out of the read portions 304b, 304b, 310b, 312b in accordance with the first clock signal <NUM> from the first clock <NUM> to provide the data to the processor <NUM>. The access circuit <NUM> may read data computed by processor <NUM> and stored in the read portions 316b, 318b to store the data to the storage <NUM> and in accordance with the first clock signal <NUM>.

In some embodiments and as described above, the transfer circuit <NUM> may transfer data from the write portions 304a, 306a, 310a, 312a, 316a, 318a to the read portions 304b, 304b, 310b, 312b, 316b, 318b in accordance with a transfer clock signal of the second clock <NUM> during transfer cycles. The transfer clock signal <NUM> may correspond to transfer cycles of timing diagram <NUM> (<FIG>).

Some embodiments may replace duplicative read-write circuitry that may otherwise be present in each of the two instances of a double-buffer register file with a single write and single read circuitry to control accesses. For instance, the access circuit <NUM> may include a single write and single read circuitry that is common to the first double buffer bank <NUM> to access read portion 304b and write portion 304a. Notably, at least part of the write circuitry may not be needed for the read portion 304b since components external to the input features register file <NUM> do not write to the read portion 304b. Rather, data is transferred internally from the write portion 304a to the read portion 304b. Further, read circuitry may not be needed for the write portion 304a since the write portion 304a is not read by components external to the input features register file <NUM>. Similarly, the access circuit <NUM> may include a single write and single read circuitry that is common to the N double buffer bank <NUM> to access the read portion 306b and write portion 306a. The access circuit <NUM> may similarly include single read write circuitry for the first-N double buffer banks <NUM>-<NUM> and the first-N double buffer banks <NUM>-<NUM>.

In some embodiments, the write circuitry of the access circuit <NUM> only accesses the write portions 304a, 306a, 310a, 312a, 316a, 318a (e.g., active register file bit-cells). Furthermore, in some embodiments the read circuitry of the access circuit <NUM> is only allowed to access read portions 304b, 306b, 310b, 312b, 316b, 318b (e.g., shadow register file bit-cell).

For example, in access cycles <NUM>, during first clock cycles from T<NUM>-T<NUM>, first data may be written into write portions 304a, 306a, 310a, 312a from storage <NUM>. Since this is the first clock cycles, the read portions 304b, 306b, 310b, 312b, 316b, 318b do not yet contain data, and thus no data is yet passed to the processor <NUM>. After the first data has been loaded into the write portions 304a, 306a, 310a, 312a, a transfer pulse of transfer clock signal <NUM> may trigger a transfer from time T<NUM>-T<NUM> to move the first data from the write portions 304a, 306a, 310a, 312a to the read portions 304b, 306b, 310b, 312b. In some embodiments, time T<NUM>-T<NUM> may overlap with the first clock cycles by avoiding overwriting data that has not yet been read by the processor <NUM> or transferred to storage <NUM>.

Thereafter, from time T<NUM>-T<NUM> during second clock cycles of the first clock signal <NUM> from time T<NUM>-T<NUM>, the first data may be read from the read portions 304b, 306b, 310b, 312b by the processor <NUM>. Furthermore, from time T<NUM>-T<NUM>, second data may be written into the write portions 304a, 306a, 310a, 312a from storage <NUM>. The processor <NUM> may now being to execute operations based on the first data. After the second data has been loaded into the write portions 304a, 306a, 310a, 312a and the processor <NUM> has read the first data from the read portions 304b, 306b, 310b, 312b, a transfer pulse may trigger a transfer from time T<NUM>-T<NUM> to move the second data from the write portions 304a, 306a, 310a, 312a to the read portions 304b, 306b, 310b, 312b. In some embodiments, time T<NUM>-T<NUM> may overlap with the second clock cycles by avoiding overwriting data that has not yet been read by the processor <NUM> or transferred to storage <NUM>.

Thereafter, from time T<NUM>-T<NUM> during third clock cycles of the first clock signal <NUM>, the second data may be read from the read portions 304b, 306b, 310b, 312b by the processor <NUM>. Furthermore, from time T<NUM>-T<NUM>, third data may be written into the write portions 304a, 306a, 310a, 312a from storage <NUM>. The processor <NUM> may have completed operations based on the first data and stores the output in the write portions 316a, 318a during the third clock cycles. After the third data and output have been loaded into the write portions 304a, 306a, 310a, 312a, 316a, 318a and the processor <NUM> has read the second data from the from the read portions 304b, 306b, 310b, 312b, a transfer pulse may trigger a transfer from time T<NUM>-T<NUM> to move the third data from the write portions 304a, 306a, 310a, 312a to the read portions 304b, 306b, 310b, 312b, and the output from the write portion 316a, 318a to the read portions 316b, 318b. In some embodiments, the time T<NUM>-T<NUM> may overlap with the third clock cycles by avoiding overwriting data that has not yet been read by the processor <NUM> or transferred to storage <NUM>.

The above process may repeat again starting at time T<NUM> and similar to the above. For example, the read portions 316b, 318b may be read to identify the output and store the output in the storage <NUM>. In some embodiments, the transfer cycles of the transfer clock signal <NUM> correspond to a clock pulse that triggers the copy of the write portions 304a, 306a, 310a, 312a, 316a, 318a (e.g., active register file bit-cells) to read portions 304b, 306b, 310b, 312b, 316b, 318b (e.g., shadow register file bit-cell). The write portions 304a, 306a, 310a, 312a, 316a, 318a may operate solely in the write phase, while the read portions 304b, 306b, 310b, 312b, 316b, 318b operate solely in the read phase with a pulse of a trigger clock, such as transfer clock signal <NUM>, between the two phases that causes copying of contents from the write portions 304a, 306a, 310a, 312a, 316a, 318a into the read portions 304b, 306b, 310b, 312b, 316b, 318b.

<FIG> illustrates an example of a double-buffered register file architecture <NUM> with shared read/write circuits. As illustrated, a first integrated clock gate <NUM> may be provided to generate a first clock signal associated with a write portion 416a of the multi-buffered memory cell <NUM>. The write enable signal may be provided to the D input of the latch of the first integrated clock gate <NUM> and the clock signal may be provided to the clock input of the latch of first integrated clock gate <NUM>.

A write decoder <NUM> may receive an input of a write address from a latch <NUM> at a timing corresponding to the first clock signal. The write decoder <NUM> may provide an output to the write wordline driver <NUM>, which provides an output to the clock input of the write portion 416a. The write data may be transmitted to the multi-buffered memory cell through a mini-delay buffer <NUM> and a latch <NUM>.

A second integrated clock gate <NUM> may provide a second clock signal to the clock input of a read portion 416b of the multi-buffered memory cell <NUM>. The data may be transferred from the write portion 416a to the read portion 416b based on a timing of the second clock signal. A read decoder <NUM> and read path <NUM> may provide read data from the read portion 416b. In some embodiments, more than one multi-buffered memory cell <NUM> may utilize the read path <NUM>, and hence more than one AND logic gate may be provided in the read path <NUM>. It is to be noted that the illustrated logic gates show examples of exemplary paths for the various illustrated blocks, such as write decoder <NUM>, read decoder <NUM> and read path <NUM>. In some embodiments the logic pins associated with signals S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM> may be connected to other gate outputs (e.g., other memory cells) which are not shown for clarity to simplify the discussion. The other gate outputs may generate signals S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>.

For example, the logic pins in the first AND-OR-Invert (AOI) gate in the read path <NUM> may be connected to two memory cells, and/or two read wordlines (from read decoder) that produce signals S<NUM>, S<NUM>. The next NAND gate may receive inputs from two AOI gates, one of which is unillustrated and generates signal S<NUM>. The last NOR gate may receive inputs from two NAND gates, one of which is unillustrated and produced signal S<NUM>. If the register file has more entries, the read decoder <NUM> and read path <NUM> logic may be modified to increase logic depth.

Furthermore, in some embodiments an exposed state node may need to use relative placement so that the exposed state node may be placed next to the first AOI gate of the read path <NUM>, which corresponds to one or more of a plurality of the multi-buffered memory cells <NUM>, may utilize the read path <NUM>. The read decoder <NUM> may feed into each AND gate of the read path <NUM> to control the output of the correct multi-buffered memory cell of the multi-buffered memory cells <NUM>.

In some embodiments, some of the components of <FIG> may be duplicated. Some embodiments of <FIG> include a double-buffered, quad-latch based memory circuit as the multi-buffered memory cell <NUM>, where the double-buffered memory cell contains two latches that correspond to read portion 416b and write portion 416a (e.g., a shadow latch for writing and an active latch for reading). Double-buffered memories may be constructed using quad-latches exposed state node quad latch standard cells.

<FIG> illustrates memory cell <NUM>-N memory cell <NUM> that may correspond to double-buffered latches. For example, if the memory cells <NUM>-N memory cells <NUM> are double buffered quad bit latches, there may be four memory cells total (e.g., N=<NUM>). As illustrated a first latch 502a may couple with a second latch 502b. The memory cells <NUM>-N memory cells <NUM> may be readily substituted for the multi-buffered memory cell <NUM> (<FIG>).

Turning now to <FIG>, a performance-enhanced double-buffered memory computing system <NUM> is shown. The system <NUM> may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television/TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), etc., or any combination thereof. In the illustrated example, the system <NUM> includes a host processor <NUM> (e.g., CPU) having an integrated memory controller (IMC) <NUM> that is coupled to a system memory <NUM>. The host processor <NUM> includes processing elements including PE<NUM>-PEn 152a-152n that may execute operations based on data on the registers <NUM> (e.g., hardware registers). The registers <NUM> may implement a multi-buffer architecture as described herein to include read portions dedicated to providing data to PE<NUM>-PEn 152a-152n, FPGA <NUM>, graphics processor <NUM> and/or AI accelerator <NUM>. The registers <NUM> may further include write portions to store data from one or more of a cache <NUM>, system memory <NUM>, cache of the graphics processor <NUM> or cache of the FPGA <NUM>. The access circuitry <NUM> may control read and writes to the registers <NUM> in accordance with a clock signal from a read/write clock <NUM>. The registers <NUM> may move data from the write portions to the read portions in accordance with a transfer clock signal of transfer clock <NUM> as described herein.

The illustrated system <NUM> also includes an input output (IO) module <NUM> implemented together with the host processor <NUM> and a graphics processor <NUM> (e.g., GPU) on a semiconductor die <NUM> as a system on chip (SoC). The illustrated IO module <NUM> communicates with, for example, a display <NUM> (e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), a network controller <NUM> (e.g., wired and/or wireless), and mass storage <NUM> (e.g., hard disk drive/HDD, optical disk, solid state drive/SSD, flash memory). Furthermore, the SoC <NUM> may further include processors (not shown) and/or AI accelerator <NUM> dedicated to artificial intelligence (AI) and/or neural network (NN) processing. For example, the system SoC <NUM> may include vision processing units (VPUs,) and/or other AI/NN-specific processors such as AI accelerator <NUM>, etc. In some embodiments, any aspect of the embodiments described herein may be implemented in the processors and/or accelerators dedicated to AI and/ or NN processing such as AI accelerator <NUM>, the graphics processor <NUM> and/or the host processor <NUM>.

The host processor <NUM>, the graphics processor <NUM>, the FPGA <NUM> and/or the IO module <NUM> may execute instructions <NUM> retrieved from the system memory <NUM> and/or the mass storage. When the instructions <NUM> are executed, the computing system <NUM> may implement one or more aspects of the embodiments described herein. For example, the system <NUM> may implement and/or include one or more aspects of the process <NUM> (<FIG>), the method <NUM> (<FIG>), the architecture <NUM> (<FIG>), the architecture <NUM> (<FIG>), the memory cells <NUM>-<NUM> (<FIG>), already discussed.

The illustrated computing system <NUM> is therefore considered to be performance-enhanced at least to the extent that it enables the computing system <NUM> to take advantage of low latency memory accesses and storage at reduced footprint and hardware cost. Thus, some embodiments may increase throughput while also reducing a size of the package.

<FIG> shows a semiconductor apparatus <NUM> (e.g., chip, die, package). The illustrated apparatus <NUM> includes one or more substrates <NUM> (e.g., silicon, sapphire, gallium arsenide) and logic <NUM> (e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s) <NUM>. In an embodiment, the apparatus <NUM> is operated in an application development stage and the logic <NUM> implements and/or includes one or more aspects of the process <NUM> (<FIG>), the method <NUM> (<FIG>), the architecture <NUM> (<FIG>), the architecture <NUM> (<FIG>), the memory cells <NUM>-<NUM> (<FIG>), already discussed. Thus, the logic <NUM> may store buckets that represent a plurality of clusters in a cache, where each of the buckets is to represent a group of the plurality of clusters and further where the plurality of clusters is in a first data format, modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one bucket of the buckets. Furthermore, the logic <NUM> may further include processors (not shown) and/or AI accelerator dedicated to artificial intelligence AI and/or NN processing. For example, the system logic <NUM> may include VPUs, and/or other AI/NN-specific processors such as AI accelerators, etc. In some embodiments, any aspect of the embodiments described herein may be implemented in the processors and/or accelerators dedicated to AI and/ or NN processing such as AI accelerators.

The logic <NUM> may be implemented at least partly in configurable logic or fixed-functionality hardware logic. In one example, the logic <NUM> includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) <NUM>. Thus, the interface between the logic <NUM> and the substrate(s) <NUM> may not be an abrupt junction. The logic <NUM> may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s) <NUM>.

<FIG> illustrates a processor core <NUM> according to one embodiment. The processor core <NUM> may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core <NUM> is illustrated in <FIG>, a processing element may alternatively include more than one of the processor core <NUM> illustrated in <FIG>. The processor core <NUM> may be a single-threaded core or, for at least one embodiment, the processor core <NUM> may be multithreaded in that it may include more than one hardware thread context (or "logical processor") per core.

<FIG> also illustrates a memory <NUM> coupled to the processor core <NUM>. The memory <NUM> may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory <NUM> may include one or more code <NUM> instruction(s) to be executed by the processor core <NUM>, wherein the code <NUM> may implement and/or include one or more aspects of the process <NUM> (<FIG>), the method <NUM> (<FIG>), the architecture <NUM> (<FIG>), the architecture <NUM> (<FIG>), the memory cells <NUM>-<NUM> (<FIG>), already discussed. The processor core <NUM> follows a program sequence of instructions indicated by the code <NUM>. Each instruction may enter a front end portion <NUM> and be processed by one or more decoders <NUM>. The decoder <NUM> may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion <NUM> also includes register renaming logic <NUM> and scheduling logic <NUM>, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

The processor core <NUM> is shown including execution logic <NUM> having a set of execution units <NUM>-<NUM> through <NUM>-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic <NUM> performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back end logic <NUM> retires the instructions of the code <NUM>. In one embodiment, the processor core <NUM> allows out of order execution but requires in order retirement of instructions. Retirement logic <NUM> may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core <NUM> is transformed during execution of the code <NUM>, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic <NUM>, and any registers (not shown) modified by the execution logic <NUM>.

Although not illustrated in <FIG>, a processing element may include other elements on chip with the processor core <NUM>. For example, a processing element may include memory control logic along with the processor core <NUM>. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.

Referring now to <FIG>, shown is a block diagram of a computing system <NUM> embodiment in accordance with an embodiment. Shown in <FIG> is a multiprocessor system <NUM> that includes a first processing element <NUM> and a second processing element <NUM>. While two processing elements <NUM> and <NUM> are shown, it is to be understood that an embodiment of the system <NUM> may also include only one such processing element.

The system <NUM> is illustrated as a point-to-point interconnect system, wherein the first processing element <NUM> and the second processing element <NUM> are coupled via a point-to-point interconnect <NUM>. It should be understood that any or all of the interconnects illustrated in <FIG> may be implemented as a multi-drop bus rather than point-to-point interconnect.

As shown in <FIG>, each of processing elements <NUM> and <NUM> may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with <FIG>.

Each processing element <NUM>, <NUM> may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory <NUM>, <NUM> for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

While shown with only two processing elements <NUM>, <NUM>, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements <NUM>, <NUM> may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor <NUM>, additional processor(s) that are heterogeneous or asymmetric to processor a first processor <NUM>, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements <NUM>, <NUM> in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements <NUM>, <NUM>. For at least one embodiment, the various processing elements <NUM>, <NUM> may reside in the same die package.

The first processing element <NUM> may further include memory controller logic (MC) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, the second processing element <NUM> may include a MC <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MC's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors. While the MC <NUM> and <NUM> is illustrated as integrated into the processing elements <NUM>, <NUM>, for alternative embodiments the MC logic may be discrete logic outside the processing elements <NUM>, <NUM> rather than integrated therein.

The first processing element <NUM> and the second processing element <NUM> may be coupled to an I/O subsystem <NUM> via P-P interconnects <NUM><NUM>, respectively. As shown in <FIG>, the I/O subsystem <NUM> includes P-P interfaces <NUM> and <NUM>. Furthermore, I/O subsystem <NUM> includes an interface <NUM> to couple I/O subsystem <NUM> with a high performance graphics engine <NUM>. In one embodiment, bus <NUM> may be used to couple the graphics engine <NUM> to the I/O subsystem <NUM>. Alternately, a point-to-point interconnect may couple these components.

In turn, I/O subsystem <NUM> may be coupled to a first bus <NUM> via an interface <NUM>. In one embodiment, the first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.

As shown in <FIG>, various I/O devices <NUM> (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus <NUM>, along with a bus bridge <NUM> which may couple the first bus <NUM> to a second bus <NUM>. In one embodiment, the second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to the second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication device(s) <NUM>, and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. The illustrated code <NUM> may implement one or more aspects of the process <NUM> (<FIG>), the method <NUM> (<FIG>), control of architecture <NUM> (<FIG>) and/or control of the architecture <NUM> (<FIG>) and/or the memory cells <NUM>-<NUM> (<FIG>), already discussed. Further, an audio I/O <NUM> may be coupled to second bus <NUM> and a battery <NUM> may supply power to the computing system <NUM>.

Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or another such communication topology. Also, the elements of <FIG> may alternatively be partitioned using more or fewer integrated chips than shown in <FIG>.

Thus, technology described herein may provide for an enhanced memory access method and multi-buffered system. Furthermore, technology may reduce the size, complexity and hardware of registers and memory architectures.

Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

As used in this application and in the claims, a list of items joined by the term "one or more of" may mean any combination of the listed terms. For example, the phrases "one or more of A, B or C" may mean A, B, C; A and B; A and C; B and C; or A, B and C.

Claim 1:
A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
identify a plurality of registers (<NUM>) that is associated with a system-on-chip, wherein the plurality of registers includes a first portion (104a) dedicated to write operations and a second portion (104b) dedicated to read operations;
control read and write operations to the first and second portions (104a, 104b) based on a first clock signal (<NUM>); and
transfer (<NUM>) data between the first and second portions (104a, 104b) based on a second clock signal (<NUM>) that is to be different from the first clock signal (<NUM>).