Patent Description:
The ongoing trend to higher integration densities and improved device characteristics has boosted the usage of trench structures in semiconductor substrates. In many cases, the sidewalls of the trench structures need to be cladded by an oxide layer of highly controllable dimensional and structural parameters. Especially, parameters such as layer thickness, shape, uniformity and integrity need to be within small tolerance margins to guarantee compliance with device specifications and to keep the scrap rate low.

<CIT>, <CIT>, <CIT> and <CIT> disclose semiconductor devices having a trench gate structure with varying trench oxide thickness. <NPL>, describes a stepped gate oxide with larger thickness at the bottom.

A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method comprises generating the trench in the semiconductor substrate. An oxide layer is generated over opposing sidewalls of the trench. At least a portion of the oxide layer at at least one of the opposing sidewalls is damaged by ion implantation. The oxide layer is coated with an etching mask. At least one opening is formed in the etching mask adjacent to the at least one of the opposing sidewalls. The oxide layer is partly removed by etching the oxide layer beneath the etching mask down to an etching depth at the at least one of the opposing sidewalls by introducing an etching agent into the opening.

A method of manufacturing a transistor comprises manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate, e.g., as described above. The trench is filled with a gate electrode material. Source and drain electrodes of the transistor are produced.

The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification.

It is to be understood that the features of the various exemplary embodiments and examples described herein may be combined with each other, unless specifically noted otherwise.

As used in this specification, the terms "bonded", "attached", "connected", "coupled" and/or "electrically connected/electrically coupled" are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the "bonded", "attached", "connected", "coupled" and/or "electrically connected/electrically coupled" elements, respectively. However, in accordance with the disclosure, the above-mentioned terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e. that no intervening elements or layers are provided between the "bonded", "attached", "connected", "coupled" and/or "electrically connected/electrically coupled" elements, respectively.

Further, the word "over" used with regard to a part, element or material layer formed or located "over" a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) "directly on", e.g. in direct contact with, the implied surface. The word "over" used with regard to a part, element or material layer formed or located "over" a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) "indirectly on" the implied surface with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer.

<FIG> illustrate schematic representations of stages of an exemplary method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate. A semiconductor substrate <NUM> is shown in <FIG>. The semiconductor substrate <NUM> may be or comprise of semiconductor material(s) such as, e.g., Si, SiC, SiGe, etc, and may, e.g., contain inorganic and/or organic materials that are not semiconductors.

Referring to <FIG>, a trench <NUM> is formed in the semiconductor substrate <NUM>. Trench formation may, e.g., be performed by applying an etching mask (not shown) to a horizontal top surface 101A of the semiconductor substrate <NUM>, by shaping the etching mask by a photoresist (not shown) to expose a trench region at the top surface 101A and by etching the trench <NUM> through the shaped etching mask.

Referring to <FIG>, an oxide layer <NUM> is generated over opposing sidewalls (first sidewall 110A and second sidewall 110B) of the trench <NUM>. Further, the oxide layer <NUM> may extend over at least a part of the top surface 101A of the semiconductor substrate <NUM> and may extend over a bottom surface 110C of the trench <NUM>. The oxide layer <NUM> may be continuous and may, e.g., completely cover all substrate surfaces (sidewalls 110A, 110B, bottom surface 110C) of the trench <NUM>. The oxide layer <NUM> may have a thickness of equal to or greater than <NUM>, <NUM> or <NUM>.

The oxide layer <NUM> may be a mono-material layer (i.e. a layer of a single homogeneous material) of a thermal oxide, e.g. a silicon oxide layer which is formed by thermally oxidizing silicon. A mono-material layer of thermal oxide ensures that boundary effects are avoided, i.e. that a uniform etch rate across the layer thickness (as long as the oxide layer <NUM> is undamaged) is provided. Other possibilities such as a mono-material TEOS (tetraethyl orthosilicate) layer or a dual-material layer composed of, e.g., a thermal oxide layer and a TEOS layer could, e.g., also be used.

Referring to <FIG>, at least a portion <NUM> of the oxide layer <NUM> is damaged by ion implantation. In <FIG> the damaged portion <NUM> is depicted to be arranged only over the first sidewall 110A of the trench <NUM>, but generally, a damaged portion (not shown in <FIG>) similar to the damaged portion <NUM> can also be arranged over the second sidewall 110B opposite the first sidewall 110A. In the example of <FIG>, the damaged portion <NUM> is, e.g., not arranged over the bottom surface 110C of the trench <NUM>.

Further, in the example of <FIG>, the damaged portion <NUM> (and, e.g., a damaged portion arranged along the second sidewall 110B opposite the damaged portion <NUM>) extends along the first sidewall 110A (respectively along the second sidewall 110B) of the trench <NUM> down to a damaging depth DD (as measured from the top surface 101A), while a residual depth of the oxide layer <NUM> down to the bottom surface 110C of the trench <NUM> is kept undamaged.

As shown in <FIG>, only a region close to the surface of the oxide layer <NUM> may be damaged, while deeper regions of the oxide layer <NUM> beneath the damaged portion <NUM> (in lateral direction) may remain substantially undamaged.

Referring to <FIG>, the oxide layer <NUM> is coated with an etching mask <NUM>. The etching mask <NUM> may, e.g., be a nitride film. The etching mask <NUM> may completely cover the oxide layer <NUM>.

Referring to <FIG>, an opening <NUM> may be generated in the etching mask <NUM>. The opening <NUM> may be generated in a horizontal portion of the etching mask <NUM> outside the trench <NUM>. The opening <NUM> may be located near an edge of the trench <NUM>. In particular, the opening <NUM> (or openings) may be arranged adjacent to only one sidewall (here the first sidewall 110A) of the trench <NUM>, while the etching mask <NUM> remains unopened in the vicinity of the other sidewall (here second sidewall 110B).

Referring to <FIG>, the oxide layer <NUM> beneath the etching mask <NUM> is etched down to a predetermined etching depth ED (as measured from the top surface 101A) at the first sidewall 110A. That way, an exposed surface portion 110A_1 of the first sidewall 110A of the trench <NUM> of length ED is generated. As will be explained further below in more detail, by virtue of the damaging procedure, a surface <NUM> of a residual portion of the oxide layer <NUM> may be tilted with respect to a transverse plane of the trench <NUM>. More specifically, the surface <NUM> of the residual portion of the oxide layer <NUM> may have a monotonically increasing surface progression in lateral outward trench direction.

The damaging depth DD may be less than or greater than or approximately equal to the etching depth ED, i.e. DD < ED, DD > ED or DD = ED, respectively. In the latter case (DD = ED), the lower end of the damaged portion <NUM> may serve as an etch stop or etch deceleration means. The approach to control the tilt angle of the surface <NUM> by ion implantation parameters (e.g. by the implantation dose) and the etching depth ED by etching parameters (e.g. by the etching time) will be discussed further below in greater detail.

Referring to <FIG>, the etching mask <NUM> may then be removed. Removal of the etching mask <NUM> may be done by any appropriate technique available in the art. As a result, a trench oxide as formed by the residual portion of the partly removed oxide layer <NUM> is provided.

Referring to <FIG>, a thin oxide layer <NUM> may then be generated (grown) over the exposed surface portion 110A_1 of the first sidewall 110A of the trench <NUM>. There are various different processes available for generating the thin oxide layer <NUM>. The generation of the thin oxide layer <NUM> results in a semiconductor substrate <NUM> including a trench <NUM> formed in the semiconductor substrate <NUM>, and including an oxide layer <NUM> formed over the first and second sidewalls 110A, 110B of the trench <NUM>, wherein the oxide layer <NUM> comprises a first portion 120A formed over the first sidewall 110A of the trench <NUM> and a second portion 120B formed over the second sidewall 110B of the trench <NUM>. Further, the first portion 120A of the oxide layer <NUM> includes a first section 120A_1 (e.g. the thin oxide layer <NUM> as referred to above) having a first thickness, a second section 120A_2 beneath the first section 120A_1 having a second thickness and a transitional section 120A_3 (e.g. partially limited by the surface <NUM>) connecting the first section 120A_1 and the second section 120A_2.

The second thickness (of the second section 120A_2) is greater than the first thickness (of the first section 120A_1). Further, a thickness of the second portion 120B may, e.g., be substantially equal to the second thickness (of the second section 120A_2).

Referring to <FIG>, the trench <NUM> may then be filled with a gate electrode material <NUM>. The gate electrode material <NUM> may, e.g., comprise or be of polysilicon or any other electrically conducting material.

The structure shown in <FIG> may be used for manufacturing a transistor gate. More specifically, vertical transistor gates such as, e.g., transistor gates of IGBTs (insulated gate bipolar transistors) or other MOSFETs (metal oxide semiconductor field effect transistors) for switching high voltages may utilize one or more of the techniques described herein. In such transistor gate applications the first section 120A_1 of the oxide layer <NUM> (which corresponds to the thin oxide layer <NUM>) may form the channel gate oxide and needs to be comparatively thin (first thickness may be equal to or less than <NUM>, <NUM> or <NUM>) in order to provide for suitable threshold voltages of the transistor. On the other hand, the oxide layer <NUM> (i.e. trench oxide) along the residual parts of the first and second sidewalls 110A, 110B as well as along the bottom surface 110C of the trench <NUM> needs to be significantly thicker than the channel gate oxide to avoid degradation of the oxide layer <NUM> and to ensure mechanical strength and sufficient resistance against mechanical tension during filling the trench <NUM> with the gate electrode material <NUM>.

Therefore, the transitional section 120A_3 connecting the first section 120A_1 with the second section 120A_2 is a performance-critical structural element of the oxide layer <NUM>. The more controllable the transitional section 120A_3 can be shaped in terms of position (i.e. depth in the trench <NUM>), inclination angle and contour smoothness, the more reliable and better are the device characteristics and the easier it is to guarantee compliance with manufacturing tolerances and to keep the scrap rate low.

According to one aspect, the implantation energy may be used to control the damage profile of the oxide layer <NUM> in lateral direction, i.e. the lateral thickness of the damaged portion <NUM> of the oxide layer <NUM>.

According to one aspect, the implantation dose may be used to control the degree of damage of the oxide layer <NUM> (for a given implantation ion species). As the lateral and vertical etch rate depends on the degree of damage of the oxide layer <NUM>, the etching will proceed more rapidly in the damaged portion <NUM> of the oxide layer <NUM> than in the laterally deeper undamaged region. Therefore, the etching front proceeds with a constant inclination angle (depending only on the implantation dose for a given implantation energy) down the sidewall of the trench <NUM>. Hence, the implantation dose (which controls the degree of damage) may be used to precisely control the inclination angle of the surface <NUM> of the residual portion of the oxide layer <NUM> during the etching process. The higher the implantation dose, the more acute is the inclination angle of the surface <NUM> created (for a given implantation energy).

The lateral and vertical etch rate also depends on the ion species which is used for implantation. Therefore, different inclination angles could also be obtained by using different implantation ion species for a given implantation dose.

It is to be noted that the inclination angle of the surface <NUM> is identical with the inclination angle of the transitional section 120A_3 of the oxide layer <NUM>. Therefore, without loss of generality, the inclination angle is related to the transitional section 120A_3 of the oxide layer <NUM> in the following.

The vertical position of the transitional section 120A_3 of the oxide layer <NUM> adjacent to the sidewall 110A, i.e. the etching depth ED, is controlled by the etching time. The longer the etching process is continued, the greater is the etching depth ED. The etching depth ED does not depend on the implantation dose for a damage profile where damaging is produced only in a region close to the surface of the oxide layer <NUM>.

Therefore, a combination of controlling the damage implantation dose, the etching time and, optionally, the implantation energy allows to obtain user-definable and arbitrary combinations of inclination angle and etching depth (i.e. depth of the transitional section 120A_3) of the oxide layer <NUM>. More specifically, for a given implantation energy (damage profile), the inclination angle may be controlled by the implantation dose and does not depend from the etching time and the etching depth ED may be controlled by the etching time and does not dependent from the implantation dose. This independency allows a highly reproducible shaping of the transitional section 120A_3.

Referring to <FIG>, damaging may comprise ion implantation using an ion beam <NUM> having a beam axis tilted against a vertical axis <NUM> of the trench <NUM>. As shown in <FIG>, the damaging depth DD can be controlled by a variation of the tilt angle α.

Any ion species that causes implanted damage in the oxide layer <NUM> may be used. In particular, the ion beam <NUM> may comprise argon or any other non-dopant ion species. However, it is also possible that the ion beam comprises dopant species.

Implantation doses may range, e.g., from about <NUM> × <NUM><NUM> cm-<NUM> to about <NUM> × <NUM><NUM> cm-<NUM> according to the requested inclination angle of the transitional section 120A_ <NUM>. However, doses outside this range may also be used. Tilt angles α may, e.g., be in a range of <NUM>° to <NUM>°. However, tilt angles α outside this range may also be used.

<FIG> illustrates tilted ion beam damaging similar to <FIG>, and reference is made to the above description in order to avoid reiteration. However, in contrast to the damaging process of <FIG>, another damaging profile is obtained by using higher implantation energy. In <FIG> the oxide layer <NUM> may be damaged throughout its entire lateral dimension along the damaged portion <NUM> of the oxide layer <NUM>.

<FIG> illustrates an exemplary option of damaging the oxide layer <NUM> along both sidewalls 110A, 110B of the trench <NUM> and, optionally, along its entire extension (i.e. also along the bottom surface 110C of the trench <NUM>). This type of damaging may be obtained by using plasma immersion ion implantation. Plasma immersion ion implantation is a cost efficient process which, however, does not allow to selectively damage only one of the two sidewalls 110A, 110B of the trench <NUM>.

As already mentioned above, although not specifically depicted in the Figures, according to various embodiments the oxide layer <NUM> is damaged along both sidewalls 110A, 110B (as shown in <FIG>) but only down to a damaging depth DD (as shown in <FIG>) rather than along its entire extension. Such damaging profile may, e.g., be produced by <NUM>° rotation of the substrate <NUM> during tilted ion beam <NUM> implantation (see <FIG>) or by masking a lower part of the trench <NUM> followed by plasma immersion ion implantation and mask removal.

Similar to <FIG>, <FIG> illustrates an example in which damaging of the oxide layer <NUM> is only produced in a region close to the surface of the oxide layer <NUM>, while <FIG> illustrates an example where the damage portion <NUM> of the oxide layer <NUM> may completely penetrate the oxide layer <NUM> similar to <FIG>.

<FIG> illustrates inclination angles of the transitional section 120A_3 for damaging profiles obtained from different implantation doses at the same etching time. The greater the implantation dose, the more acute is the inclination angle of the transitional section 120A_3 at <NUM>, <NUM> and <NUM>, respectively.

<FIG> illustrates the position and inclination angle of the transitional section 120A_3 depending on the etching time for a given implantation dose. The longer the etching time for the transitional section 120A_3 at <NUM>, <NUM> and <NUM>, respectively, the greater is the etching depth ED. The inclination angle does not depend on the etching time, i.e. irrespective of ED, the inclination angle at <NUM>, <NUM> and <NUM> is always the same. <FIG> illustrates the inclination angle for the case of ED <= DD. However, the independency of the inclination angle from the etching time may remain valid for some range at ED > DD (at least as long as ED >> DD is not reached).

Referring to <FIG>, the inclination angle of the transitional section 120A_3 also does not depend on the etching depth ED if the damaging profile of <FIG> is used.

Referring to <FIG>, an edge and sidewall region of the trench <NUM> before etching is shown. The opening <NUM> in the etching mask <NUM> is arranged in the horizontal part of the etching mask <NUM> close to the edge of the trench <NUM>.

<FIG> illustrates the surface and sidewall region of the semiconductor substrate <NUM> after etching. As apparent in <FIG>, the etching process between the substrate <NUM> and the etching mask <NUM> proceeds both in the vertical direction down the first sidewall 110A as well as in the horizontal direction along the top surface 101A of the semiconductor substrate <NUM>.

<FIG> is a traced microscope image illustrating a contour of the transitional section 120A_3 connecting the first section 120A_1 and the second section 120A_2 of the oxide layer <NUM>. The oxide layer <NUM> (trench oxide) shown in <FIG> may have been produced by a method as displayed in <FIG>, <FIG>, <FIG>, <FIG>. Apparently the transitional section 120A_3 has an increasing surface progression in lateral trench direction (i.e. from left to right). <FIG> is drawn to scale.

In <FIG> the surface progression of the transitional section 120A_3 is monotonically increasing. Further, the transitional section 120A_3 has a smooth contour which is free of any steps or kinks. This significantly facilitates the filling of the trench <NUM> by the gate electrode material <NUM>. In particular, the smooth contour of the transitional section 120A_3 prevents that bubbles are captured during the filling process at the transitional section 120A_3. Void generation during the filling process is therefore effectively ruled out by the highly controllable trench oxide generation process as disclosed herein.

Electron microscope images of <FIG> illustrate the dependency of the inclination angle of the transitional section 120A_3 form the implantation dose. Referring to <FIG>, an inclination angle of <NUM>° was obtained by using an implantation dose of <NUM><NUM> cm-<NUM>. In <FIG> an inclination angle of <NUM>° was obtained by using a higher implantation dose. In both cases, the same implantation energy was used. <FIG> are drawn to scale.

<FIG> is a top view of an exemplary circumferential trench <NUM> of a gate structure of a transistor. The trench <NUM> may, e.g., have a rectangular or quadratic circumferential shape. Other shapes, such as circular, etc., may also be feasible. Damaging of both sidewalls 110A, 110B of the trench <NUM> may, e.g., be achieved by tilted ion beam damaging as exemplified in <FIG> in combination with sequential rotations of the semiconductor substrate <NUM> by steps of a rotation angle of <NUM>°.

<FIG> is a cross-sectional view of an exemplary circumferential trench <NUM> of a transistor such as, e.g., the circumferential trench <NUM> of the transistor shown in <FIG>. In <FIG> the trench <NUM> is filled with the gate electrode material <NUM>. <FIG> illustrates that only one of the two sidewalls (in <FIG> the outward sidewall - see the encircled portion) of the trench <NUM> is covered by the "thin" gate oxide (i.e. first section 120A_1 of the oxide layer <NUM> corresponding to the thin oxide layer <NUM> in <FIG>) while the bottom surface 110C of the trench <NUM> and the second sidewall 110B of the trench <NUM> are covered with trench oxide of the "thick" oxide layer <NUM>. It is to be noted that this asymmetry in shape of the oxide layer <NUM> (a transitional section 120A_3 and a thin gate oxide only exist at one of the sidewalls) results in that the trench <NUM> provides for a smaller electrical capacitance compared with a symmetrical trench oxide design. As a consequence, the transistor (e.g. IGBT) provides for smaller switching losses.

<FIG> is a schematic cross-sectional view of a trench transistor <NUM>. The trench transistor <NUM> may, e.g., be a vertical device. A drain electrode <NUM> may be formed, e.g., at the backside (bottom) of the semiconductor substrate <NUM>. A gate electrode <NUM> may be formed at the front side of the semiconductor substrate <NUM> and is electrically connected to the gate electrode material <NUM>. A source electrode <NUM> may be formed at the front side of the semiconductor substrate in the vicinity of the trench gate oxide region.

Optionally, a region 101_1 in the semiconductor substrate <NUM> may be doped (e.g. by a p-dopant), while a zone 101_2 below the doped region 101_1 may serve as a n-drift zone.

While <FIG> schematically illustrates one possible design of a trench transistor, many other implementations are possible and the disclosure of trench transistors provided herein is not restricted to the exemplary design of <FIG>.

<FIG> is a flowchart illustrating an exemplary method of manufacturing a transistor, e.g. a transistor as shown in <FIG>.

At S1 a trench oxide in a trench for a gate structure in a semiconductor substrate is manufactured according to any one of the techniques disclosed herein.

At S2 the trench is filled with a gate electrode material.

Claim 1:
Method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate, the method comprising:
generating the trench (<NUM>) in the semiconductor substrate (<NUM>);
generating an oxide layer (<NUM>) over opposing sidewalls (110A, 110B) of the trench;
damaging at least a portion of the oxide layer at at least one (110A) of the opposing sidewalls (110A, 110B) by ion implantation;
coating the oxide layer (<NUM>) with an etching mask (<NUM>) ;
generating at least one opening (<NUM>) in the etching mask (<NUM>) adjacent to the at least one (110A) of the opposing sidewalls (110A, 110B); and
partly removing the oxide layer (<NUM>) by etching the oxide layer (<NUM>) beneath the etching mask (<NUM>) down to an etching depth at the at least one (110A) of the opposing sidewalls (110A, 110B) by introducing an etching agent into the opening (<NUM>).