Patent Description:
Current DIMM form factors use a card edge connector. For example, a typical Double Data Rate <NUM> (DDR5) connector latch design merely secures the DIMM into position. As a result, signal integrity performance (e.g., bandwidth) may decrease and pin counts (e.g., capacity) may be limited.

Document <CIT> relates to the inclusion of a latch system in a circuit board's connector. This latch system consists of a latch frame and a movable ejector assembly that is attached to the latch frame.

Document <CIT> proposes a connector for an electronic card. One version of the connector includes a body that is attached to a motherboard and has a socket for securely holding a DIMM in place. When the DIMM is seated, its terminals are in electrical contact with the terminals in the socket, allowing it to communicate electronically with the motherboard. A lever is connected to one end of the connector body and can be moved to engage with the DIMM and raise it. There is also a linear actuator that can move along a track and can be brought into contact with the lever. To eject the DIMM, a user presses down on the linear actuator at a particular point. This causes the linear actuator to engage with the lever, lifting the DIMM from its seated position to a raised position, which separates the electrical contact between the terminals of the DIMM and the socket terminals.

Document <CIT> relates to a latch device for a circuit board. In one example, the device includes a first latch body with a mechanism for holding the circuit board in place, a second latch body with a mechanism for connecting to a connector, and a spring mechanism that connects the first and second latch bodies.

Turning now to <FIG>, a first computing system <NUM> is shown in which a memory module <NUM> is coupled to a printed circuit board (PCB, e.g., motherboard) <NUM> via an LGA connector <NUM>. In the illustrated example, compression forces are used to form electrical connections between contact pins <NUM> and the memory module <NUM>. Additionally, a second computing system <NUM> includes a memory module <NUM> that is coupled to a PCB <NUM> via a CMT connector <NUM>. Again, compression forces are used to form electrical connectors between contact pins <NUM> and the memory module <NUM>. The compression forces generally provide better signal integrity performance (e.g., bandwidth) and an increased pin count (e.g., capacity) relative to conventional edge card connectors. As will be discussed in greater detail, embodiments provide for a latch assembly that facilitates the compression forces achieved in the first computing system <NUM> and the second computing system <NUM>. As a result, embodiments provide enhanced performance relative to traditional edge card connector solutions.

<FIG> shows a latch assembly <NUM> in an open position with respect to a memory module (e.g., DIMM). The illustrated latch assembly <NUM> includes a connector <NUM> (e.g., LGA connector, CMT connector) and an L-shaped lever <NUM> coupled to the connector <NUM> via a first pivot point <NUM> (e.g., pin, hinge). In an embodiment, the first pivot point <NUM> provides an axis (e.g., into the page) about which the L-shaped lever <NUM> rotates. The latch assembly <NUM> also includes an L-shaped load member <NUM> extending through an opening <NUM> in the L-shaped lever <NUM>. A longitudinal (e.g., substantially straight) lever <NUM> is coupled to the L-shaped load member <NUM> via a second pivot point <NUM> (e.g., pin, hinge). In one example, the second pivot point <NUM> provides an axis (e.g., into the page) about which the longitudinal lever <NUM> rotates. The latch assembly <NUM> also includes a spring <NUM> to bias the L-shaped load member <NUM> away from the opening <NUM> in the L-shaped lever <NUM>. Thus, in the open position as shown, the longitudinal lever <NUM> causes the L-shaped load member <NUM> to compress the spring <NUM> (e.g., due to a user action) and the L-shaped lever <NUM> may be rotated away from the memory module <NUM>. The L-shaped lever <NUM> may alternatively be formed in a shape other than an L-shape (e.g., asymmetric T-shape).

<FIG> shows the latch assembly <NUM> in an installed position. More particularly, the L-shaped lever <NUM> is rotated towards the memory module <NUM> while the longitudinal lever <NUM> continues to cause the L-shaped load member <NUM> to compress the spring <NUM>. Of particular note is that a protrusion <NUM> on the L-shaped load member <NUM> extends away from the spring <NUM> but has clearance to come into alignment with surfaces defining a recess <NUM> in the memory module <NUM>.

<FIG> shows the latch assembly <NUM> in a latched position. More particularly, the L-shaped lever <NUM> has rotated toward the memory module <NUM> and the spring <NUM> engages the protrusion <NUM> with the recess <NUM> in the memory module <NUM>. Thus, by releasing the longitudinal lever <NUM>, the load is applied through a guided post of the L-shaped load member <NUM> to the memory module <NUM>. As a result, the latch assembly <NUM> provides better signal integrity performance (e.g., bandwidth) and increased pin counts (e.g., capacity) with respect to CMT and LGA technologies. The new form factor and spring stiffness of the latch assembly <NUM> also enables the memory module <NUM> to meet electrical performance requirements associated with CMT and LGA technologies.

The memory module <NUM> may be part of a memory device that includes non-volatile memory and/or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium. In one embodiment, the memory structure is a block addressable storage device, such as those based on NAND or NOR technologies. A storage device may also include future generation nonvolatile devices, such as a three-dimensional (3D) crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the storage device may be or may include memory devices that use silicon-oxide-nitride-oxide-silicon (SONOS) memory, electrically erasable programmable read-only memory (EEPROM), chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The term "storage device" may refer to the die itself and/or to a packaged memory product. In some embodiments, 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In particular embodiments, a memory module with non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD235, JESD218, JESD219, JESD220-<NUM>, JESD223B, JESD223-<NUM>, or other suitable standard (the JEDEC standards cited herein are available at jedec.

Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of the memory modules complies with a standard promulgated by JEDEC, such as JESD79F for Double Data Rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at jedec. Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

As used in this application and in the claims, a list of items joined by the term "one or more of" may mean any combination of the listed terms. For example, the phrases "one or more of A, B or C" may mean A; B; C; A and B; A and C; B and C; or A, B and C.

Claim 1:
A latch assembly (<NUM>) comprising:
a connector (<NUM>);
a first lever (<NUM>) coupled to the connector (<NUM>) via a first pivot point (<NUM>);
an L-shaped load member (<NUM>) extending through an opening (<NUM>) in the first lever (<NUM>), wherein the first lever (<NUM>) comprises a first part coupled to the connector (<NUM>) and a second part extending perpendicular to the first part, wherein the opening (<NUM>) is formed in the second part of the first lever (<NUM>);
a second lever (<NUM>) coupled to the L-shaped load member (<NUM>) via a second pivot point (<NUM>); and
a spring (<NUM>) to bias the L-shaped load member (<NUM>) away from the opening (<NUM>) in the first lever (<NUM>).