Patent Description:
The following relates generally to a system that includes at least one memory device and more specifically to a socket design for a memory device.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic <NUM> or a logic <NUM>. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, decreasing stress on a memory cell or other components of memory devices, or reducing manufacturing costs, among other metrics.

<CIT> generally relates to a semiconductor memory device including plural word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; plural variable resistance elements each having a first terminal connected to either one of the first and third bit lines; plural active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; plural select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and plural contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line.

The present invention provides an apparatus as recited in claim <NUM>. Further optional features are set out in the dependent claims.

In some cases, a memory device (e.g., a cross-point memory device) is configured to access a memory cell and sense a logic state stored in the memory cell, in accordance with aspects of the present disclosure. The access may occur as part of a read operation, a write operation, or a combination thereof. Memory cells in the memory array may be arranged into columns and rows where each row of memory cells corresponds to (e.g., is coupled with) a same word line, and each column of memory cells corresponds to (e.g., is coupled with) a same bit line. Bit lines and word lines of the memory device may be non-parallel (e.g., orthogonal) to one another, and each memory cell in the memory array may be located at an intersection of a word line and a bit line.

In some memory architectures, accessing a memory cell during a read or write operation may include applying a non-zero voltage across the memory cell in order to read (e.g., sense) a logic state stored by the memory cell. Accessing the memory cell thus may include selecting a bit line and a word line coupled with the memory cell by applying respective voltages to the bit line and the word line. Bit lines and word lines (either or both of which may be referred to as access lines) may be coupled with respective sockets, which may in turn be coupled with respective drivers configured to apply a current and a voltage to the word lines and bit lines as part of the access operation. For example, each socket may be coupled with a via, and the via may be coupled with the driver for the socket and associated bit line or word line. Vias may extend in a different direction than the bit lines and words lines (e.g., vias may extend through layers or decks of a memory device, which may be referred to as a vertical direction for clarity, whereas bit lines and word lines may extend horizontally within respective layers or decks of the memory device). In some examples, sockets may be disposed in rows, and an area of the memory device that includes one or more socket rows may be referred to as a socket region. In general, a socket region may be defined as a region (e.g., of a memory die) where access lines terminate into (e.g., are coupled with) vias that carry signals to and from the access lines.

A memory device may be configured to apply a voltage Vcell across a memory cell as part of an access operation. For example, the voltage Vcell may represent a threshold voltage for sensing the logic state stored by the memory cell. The memory device may configure the drivers to select the word line and the bit line coupled with the memory cell by applying a current I and a voltage Vsource. The voltage Vsource may be determined or otherwise configured based on the voltage Vcell, as well as a resistance RWL associated with the word line and a resistance RBL associated with the bit line. For example, the voltage Vsource may be determined such that Vcell = Vsource - I · (RWL + RBL), where the resistance of vias or other interconnect structures between the source and the memory cell may be considered negligible compared to RWL and RBL. Further, the resistances associated with the word line and the bit line may be functions of the respective lengths of the word line and the bit line. Specifically, the resistance RWL and the resistance RBL may be defined as RWL = ρLWL and RBL = ρLBL, where LWL represents a length of the word line from the word line socket to the memory cell, LBL represents a length of the bit line from the bit line socket to the memory cell, and p represents a resistivity (i.e., a resistance per unit length) of the word line and the bit line. In some examples, the word line and the bit line may have the same resistivity (e.g., when the word line and the bit line are composed of the same material). In some other examples, the word line and the bit line may be composed of different materials, or may have different cross-sectional areas (e.g., different widths and/or thicknesses) or other variations, and the word line and the bit line each have different resistivities p.

A memory cell may have an associated electrical distance (ED) based on the corresponding resistance RWL and resistance RBL. The ED associated with the memory cell may, for example, be expressed as a sum of a first quantity of lines and spaces between the memory cell and the word line socket, and a second quantity of lines and spaces between the memory cell and the bit line socket. For example, a memory cell that is located one thousand lines (and spaces between the lines) from the word line socket and five hundred lines from the bit line socket may have an associated ED of <NUM>, which may be expressed as <NUM> ED. Accordingly, a first memory cell (which may be referred to as a near-near memory cell) that is physically located near a word line socket and near a bit line socket may have a smaller ED than a second memory cell (which may be referred to as a far-far memory cell) that is physically located further from a word line socket and further from a bit line socket.

Variations in ED associated with memory cells in a memory array may negatively impact performance and design optimization of the memory device. For example, accessing a far-far memory cell may require a relatively large amount of drive current, which may impact driver designs or other design considerations along with power consumption and other performance aspects. Accessing a near-near memory cell may result in a large amount of discharge current (e.g., a current spike) when the memory cell is activated (e.g., when Vcell reaches the threshold voltage of the cell), due to charge build up in associated parasitic capacitances and the relatively low values of the corresponding RWL and RBL, which may increase wearout of near-near memory cells unless reduced drive currents or other mitigation techniques are used for near-near memory cells.

Some memory devices may attempt to compensate for variations in ED across memory cells by adjusting driver operation based on memory cell location (e.g., based on increasing the driver current for far-far memory cells and decreasing the driver current for near-near memory cells, such as by adjusting Vsource), but use of such an algorithm or scheme may introduce operational complexity or latency (e.g., to execute the algorithm and adjust drivers based on the algorithm). Further, some such techniques may rely on mapping tables of memory cell addresses to associated EDs or drive currents, which may occupy storage that could otherwise be used to store other data.

As described herein, it may be beneficial to reduce variation in ED across the memory cells of a memory device and thereby improve performance and efficiency of the memory device through structural features of the memory device. For example, the rows of bit line sockets and the rows of word line sockets (and thus the associated socket regions) may be slanted (tilted) relative to the word lines or bit line such that the rows of sockets extend in a direction that is skew (i.e., not orthogonal) to the word lines or the bit lines. In some cases, the rows of bit line sockets and the rows of word line sockets may be parallel to one another.

In some examples, such as when the resistivity p is the same for the word lines and the bit lines, the rows of sockets may extend in a direction that is tilted <NUM>° relative to the direction of the word lines and the direction of the bit lines. In some examples, such as when the resistivity ρW of the word lines is different than the resistivity ρB of the bit lines, the rows of sockets may extend in a direction that is tilted at an angle relative to the direction of the bit lines (and tilted at a complementary angle relative to the direction of the word lines), where the angle is based on the resistivity ρW of the word lines and the resistivity ρB of the bit lines. For example, a reference angle θ may be defined relative to the direction of the bit lines and determined according to the equation tan θ = ρB/ρW, though one of ordinary skill in the art will appreciate that a like reference angle may alternatively be defined relative to the direction of the word lines.

Features of the disclosure are initially described in the context of a memory system and memory die as described with reference to <FIG> and <FIG>. Features of the disclosure are then described in the context of socket designs, a die layout, and a socket region as described with reference to <FIG>. These and other features of the disclosure are further illustrated by and described with reference to a flowchart that relates to a socket design for a memory device as described with reference to <FIG>.

<FIG> illustrates an example memory device <NUM> that supports a socket design for a memory device in accordance with examples as disclosed herein. Memory device <NUM> may also be referred to as an electronic memory apparatus. <FIG> is an illustrative representation of various components and features of the memory device <NUM>. As such, it should be appreciated that the components and features of the memory device <NUM> are shown to illustrate functional interrelationships, and not necessarily actual physical positions within the memory device <NUM>. In the illustrative example of <FIG>, the memory device <NUM> includes a three-dimensional (3D) memory array <NUM>. The 3D memory array <NUM> includes memory cells <NUM> that may be programmable to store different states. In some examples, each memory cell <NUM> may be programmable to store one of two states, denoted as a logic <NUM> and a logic <NUM>. In some examples, a memory cell <NUM> may be configured to store one of more than two logic states. Although some elements included in <FIG> are labeled with a numeric indicator, other corresponding elements are not labeled, though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

The 3D memory array <NUM> may include two or more two-dimensional (2D) memory arrays formed on top of one another. This may increase a number of memory cells that may be placed or created on a single die or substrate as compared with 2D arrays, which in turn may reduce production costs, or increase the performance of the memory device, or both. The memory array <NUM> may include two levels of memory cells <NUM> and may thus be considered a 3D memory array; however, the number of levels is not limited to two and may in some cases be one or more than two. Each level may be aligned or positioned so that memory cells <NUM> may be aligned (exactly, overlapping, or approximately) with one another across each level, forming a memory cell stack <NUM>. In some cases, the memory cell stack <NUM> may include multiple memory cells <NUM> laid on top of another while sharing an access line. The memory cells <NUM> may in some cases be configured to each store one bit of data.

A memory cell <NUM> may, in some examples, be a self-selecting memory cell, a phase change memory (PCM) cell, and/or another type of resistive or threshold-based memory cell. A self-selecting memory cell <NUM> may include one or more components of a material (e.g., a chalcogenide material) that each function both as a storage element and as a cell selector (selection) element, thereby eliminating the need for separate cell selector circuitry (a selector circuitry that does not contribute to storage). Such an element may be referred to as a storage and selector component (or element), or as a self-selecting memory component (or element). In contrast, other types of memory cells, such as dynamic random access memory (DRAM) or PCM cells, may each include a separate (dedicated) cell selector element such as a three-terminal selector element (e.g., a transistor) to contribute to the selection or non-selection of the memory cell without contributing to the storage of any logic state.

Memory array <NUM> may include multiple word lines <NUM> (e.g., row lines) for each deck, labeled WL_1 through WL_M, and multiple bit lines <NUM> (e.g., column lines), labeled BL_1 through BL_N, where M and N depend on the array size. In some examples, each row of memory cells <NUM> is connected to a word line <NUM>, and each column of memory cells <NUM> is connected to a bit line <NUM>. In some cases, word lines <NUM> and bit lines <NUM> may generically be referred to as access lines because they may permit access to memory cells <NUM>. In some examples, bit lines <NUM> may also be known as digit lines <NUM>. References to access lines, word lines, and bit lines, or their analogues, are interchangeable without loss of understanding or operation. Activating or selecting a word line <NUM> or a bit line <NUM> may include applying a voltage to the respective line. Word lines <NUM> and bit lines <NUM> may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductively doped semiconductors, or other conductive materials, alloys, compounds, or the like.

Word lines <NUM> and bit lines <NUM> may be substantially perpendicular (i.e., orthogonal) to one another or otherwise intersect one another to create an array of memory cells. As shown in <FIG>, the two memory cells <NUM> in a memory cell stack <NUM> may share a common conductive line such as a bit line <NUM>. That is, a bit line <NUM> may be in electronic communication with the bottom electrode of the upper memory cell <NUM> and the top electrode of the lower memory cell <NUM>. Other configurations may be possible, for example, a third layer may share an access line <NUM>, <NUM> with a lower layer. In general, one memory cell <NUM> may be located at the intersection of two conductive lines such as a word line <NUM> and a bit line <NUM>. This intersection may be referred to as an address of a memory cell <NUM>. A target memory cell <NUM> may be a memory cell <NUM> located at the intersection of an energized word line <NUM> and bit line <NUM>; that is, word line <NUM> and bit line <NUM> may be energized to read or write a memory cell <NUM> at their intersection. Other memory cells <NUM> that are in electronic communication with (e.g., connected to) the same word line <NUM> or bit line <NUM> may be referred to as untargeted memory cells <NUM>.

Electrodes may be coupled to a memory cell <NUM> and a word line <NUM> or a bit line <NUM>. The term electrode may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell <NUM>. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory device <NUM>. In some examples, a memory cell <NUM> may include multiple self-selecting or other memory components (e.g., a selection component and a storage component) separated from each other and from access lines <NUM>, <NUM> by electrodes. As previously noted, for self-selecting memory cells <NUM>, a single component (e.g., a section or layer of chalcogenide material within the memory cell <NUM>) may be used as both a storage element (e.g., to store or contribute to the storage of a state of memory cell <NUM>) and as a selector element (e.g., to select or contribute to the selection of the memory cell <NUM>).

The electrodes within a memory cell stack <NUM> may each be of a same material (e.g., carbon) or may be of various (different) materials. In some cases, the electrodes may be a different material than the access lines. In some examples, the electrodes may shield a material (e.g., a chalcogenide material) included in a self-selecting or other memory component from the word line <NUM>, from the bit line <NUM>, and from each other to prevent chemical interaction between the material and the word line <NUM>, the bit line <NUM>, or another memory component.

Operations such as reading and writing may be performed on memory cells <NUM> by activating or selecting a corresponding word line <NUM> and bit line <NUM>. Accessing memory cells <NUM> may be controlled through a row decoder <NUM> and a column decoder <NUM>. For example, a row decoder <NUM> may receive a row address from the memory controller <NUM> and activate the appropriate word line <NUM> based on the received row address. Such a process may be referred to as decoding a row or word line address. Similarly, a column decoder <NUM> may receive a column address from the memory controller <NUM> and activate the appropriate bit line <NUM>. Such a process may be referred to as decoding a column or bit line address. A row decoder <NUM> and/or column decoder <NUM> may be examples of decoders implemented using decoder circuitry, for example. In some cases, row decoder <NUM> and/or column decoder <NUM> may include charge pump circuitry that is configured to increase a voltage applied to a word line <NUM> or bit line <NUM> (respectively).

A memory cell <NUM> may be read (e.g., sensed) by a sense component <NUM> when the memory cell <NUM> is accessed (e.g., in cooperation with the memory controller <NUM>, row decoder <NUM>, and/or column decoder <NUM>) to determine a logic state stored by the memory cell <NUM>. The sense component <NUM> may provide an output signal indicative of (e.g., based at least in part on) the logic state stored by the memory cell <NUM> to one or more components (e.g., to the column decoder <NUM>, the input/output component <NUM>, the memory controller <NUM>). In some examples, the detected logic state may be provided to a host device (e.g., a device that uses the memory device <NUM> for data storage, a processor coupled with the memory device <NUM> in an embedded application), where such signaling may be provided directly from the input/output component <NUM> or via the memory controller <NUM>.

Sense component <NUM> may include various transistors or amplifiers to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell <NUM> may then be output through column decoder <NUM> as output <NUM>. In some cases, sense component <NUM> may be part of a column decoder <NUM> or row decoder <NUM>. Or, sense component <NUM> may be connected to or in electronic communication with column decoder <NUM> or row decoder <NUM>. An ordinary person skilled in the art would appreciate that sense component may be associated either with column decoder or row decoder without losing its functional purpose.

In some memory architectures, accessing a memory cell <NUM> may degrade or destroy a logic state stored by one or more memory cells <NUM>, and rewrite or refresh operations may be performed to return the original logic state to the memory cells <NUM>. In architectures that include a material portion for logic storage, for example, sense operations may cause a change in the atomic configuration or distribution of a memory cell <NUM>, thereby changing the resistance or threshold characteristics of the memory cell <NUM>. Thus, in some examples, the logic state stored in a memory cell <NUM> may be rewritten after an access operation.

In some examples, reading a memory cell <NUM> may be non-destructive. That is, the logic state of the memory cell <NUM> may not need to be rewritten after the memory cell <NUM> is read. For example, in architectures that include a material portion for logic storage, sensing the memory cell <NUM> may not destroy the logic state and, thus, a memory cell <NUM> may not need rewriting after accessing. However, in some examples, refreshing the logic state of the memory cell <NUM> may or may not be needed in the absence or presence of other access operations. For example, the logic state stored by a memory cell <NUM> may be refreshed at periodic intervals by applying an appropriate write or refresh pulse or bias to maintain stored logic states. Refreshing a memory cell <NUM> may reduce or eliminate read disturb errors or logic state corruption.

Though illustrated to the side of the memory array <NUM> for clarity, the row decoder <NUM> and column decoder <NUM> may in some cases be below the memory array <NUM>. Each decoder <NUM>, <NUM> may include or be coupled with one or more drivers configured to drive the access lines <NUM>, <NUM> to desired voltages (e.g., to access one or more associated memory cells <NUM>). In some cases, the drivers may be distributed throughout an area under the memory array <NUM>. Vias may extend through one or more layers or decks of the memory device <NUM> to couple the drivers with their corresponding access lines <NUM>, <NUM>. For example, if the access lines <NUM>, <NUM> are considered to extend in horizontal directions (e.g., an x direction or a y direction), vias may extend in a vertical (z) direction. In some cases, one or more layers between the drivers and the access lines may include metal routing lines, which may be referred to as interconnect layers or collectively as an interconnect layer, where drivers may be coupled with corresponding lines in the interconnect layer and vias may extend between the interconnect layer and the layers that include the access lines <NUM>.

The word lines <NUM> may be coupled with the row decoder <NUM> via one or more rows of word line sockets (not shown), and the bit lines <NUM> may be coupled with the column decoder <NUM> via one or more rows of bit line sockets (not shown). For example, each socket may be coupled with a corresponding via or other interconnect structure and thereby serve to couple the corresponding access lines <NUM>, <NUM> with the corresponding decoder <NUM>, <NUM> (e.g., with a driver included in or coupled with the corresponding decoder <NUM>, <NUM>). As described herein, the word line sockets and the bit line sockets may be located such that a same ED is associated with each memory cell <NUM> in the memory array <NUM>, or that variations in ED are otherwise reduced. This may be achieved by tilting the rows of bit line sockets and the rows of word line sockets such that the rows of sockets extend in a direction that is skew (i.e., not orthogonal) to the word lines <NUM> or the bit lines <NUM>. In some cases, the rows of bit line sockets may be parallel to the rows of word line sockets.

Because each memory cell <NUM> has the same or similar associated ED, the memory device <NUM> may apply a same or similar voltage Vsource and thus a same or similar drive current I (e.g., via the memory controller <NUM>) to achieve a same or similar voltage drop Vcell across any memory cell <NUM> in the memory array <NUM>. This may enable the memory device to provide sufficient drive current while avoiding large amounts of current discharge across memory cells <NUM> due to parasitic capacitance of the word lines <NUM> or the bit lines <NUM>, which may improve performance and increase the lifetimes of the memory cells <NUM>, regardless of their physical location in the memory array <NUM>. Additionally, the memory device <NUM> may avoid a need to dynamically vary the voltage Vsource and current I for different memory cells <NUM> at different physical locations, which may reduce a signaling overhead or other complexities along with latencies associated with access operations, and which may support various design optimizations.

<FIG> illustrates an example of a 3D memory array <NUM> that supports a socket design for a memory device in accordance with examples as disclosed herein. The memory array <NUM> may be an example of portions of a memory array <NUM> described with reference to <FIG>. The memory array <NUM> may include a first array or deck <NUM>-a of memory cells that is positioned above a substrate <NUM> and second array or deck <NUM>-b of memory cells on top of the first array or deck <NUM>-a. Though the example of the memory array <NUM> includes two decks <NUM>-a, <NUM>-b, it is to be understood that one deck (e.g., a 2D memory array) or more than two decks are also possible.

The memory array <NUM> may also include word line <NUM>-a and word line <NUM>-b, and bit line <NUM>-a, which may be examples of word line <NUM> and bit line <NUM>, as described with reference to <FIG>. The word lines <NUM> may be coupled with one or more rows of word line sockets (not shown), and the bit lines <NUM> may be coupled with one or more rows of bit line sockets (not shown). Though one memory element <NUM> per memory cell is shown for the sake of clarity, memory cells of the first deck <NUM>-a and the second deck <NUM>-b each may include one or more memory elements <NUM> (e.g., elements including a memory material configurable to store information), which may or may not be self-selecting memory elements. Although some elements included in <FIG> are labeled with a numeric indicator, other corresponding elements are not labeled, though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

Memory cells of the first deck <NUM>-a may include first electrode <NUM>-a, a memory element <NUM>-a, and a second electrode <NUM>-b. In addition, memory cells of the second deck <NUM>-b may include a first electrode <NUM>-c, a memory element <NUM>-b, and a second electrode <NUM>-d. The memory cells of the first deck <NUM>-a and second deck <NUM>-b may, in some examples, have common conductive lines such that corresponding memory cells of each deck <NUM>-a and <NUM>-b may share bit lines <NUM> or word lines <NUM> as described with reference to <FIG>. For example, first electrode <NUM>-c of the second deck <NUM>-b and the second electrode <NUM>-b of the first deck <NUM>-a may be coupled to bit line <NUM>-a such that bit line <NUM>-a is shared by vertically adjacent memory cells.

In some examples, the memory element <NUM> may, for example, include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (IN), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG-alloy. In some examples, a SAG-alloy may also include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some other examples, a SAG-alloy may also contain indium (In), and such chalcogenide material may in some cases be referred to as InSAG-alloy. In some examples, a chalcogenide may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms.

In some cases, a memory element <NUM> may be included in a PCM cell and may change between crystalline and amorphous states. A memory element <NUM> in the crystalline state may have atoms arranged in a periodic structure, which may result in a relatively low electrical resistance (e.g., set state). By contrast, a memory element <NUM> in an amorphous state may have no or relatively little periodic atomic structure, which may have a relatively high electrical resistance (e.g., reset state). The difference in resistance values between amorphous and crystalline states of the memory element <NUM> may be significant; for example, a material in an amorphous state may have a resistance one or more orders of magnitude greater than the resistance of the material in its crystalline state. In some cases, the amorphous state may have a threshold voltage associated with it and current may not flow until Vth is exceeded. In other cases, a memory element <NUM> may be partially amorphous and partially crystalline, and the resistance may be of some value between the resistances of the memory element <NUM> in a wholly crystalline or wholly amorphous state. A memory element <NUM> thus may be used for other than binary logic applications-i.e., the number of possible states stored in a material may be more than two.

A memory element <NUM> may be switched from amorphous to crystalline and vice versa-and thus a state may be written to the memory cell that includes the memory element <NUM>-by applying a voltage across and thus passing current through the memory element <NUM> so as to heat the memory element <NUM> beyond a melting temperature, and then removing the voltage and current according to various timing parameters configured to render the memory element <NUM> in the desired state (e.g., amorphous or crystalline). Heating and quenching of the memory element <NUM> may be accomplished by controlling current flow through the memory element <NUM>, which in turn may be accomplished by controlling the voltage differential between the corresponding word line <NUM> and corresponding bit line <NUM>.

In some cases, a memory element <NUM> included in a self-selecting memory cell may be operated so as to not undergo a phase change during normal operation of the memory cell (e.g., due to the composition of the memory (e.g., chalcogenide) material, and/or due to operational voltages and currents configured to maintain the memory element <NUM> in a single phase, such as an amorphous or glass phase). For example, the memory element <NUM> may include a chemical element, such as arsenic, that inhibits crystallization of a chalcogenide material and thus may remain in an amorphous state. Here, some or all of the set of logic states supported by the memory cells (e.g., including memory element <NUM> and electrodes <NUM>) may be associated with an amorphous state of the memory element <NUM> (e.g., stored by the memory element <NUM> while the memory element <NUM> is in the amorphous state). For example, a logic state '<NUM>' and a logic state '<NUM>' may both be associated with an amorphous state of the memory element <NUM> (e.g., stored by the memory element <NUM> while the memory element <NUM> is in the amorphous state). In some cases, memory element <NUM> may be configured to store a logic state corresponding to an information bit.

During a programming (write) operation of a memory cell (e.g., including electrodes <NUM> a, memory element <NUM> a, and electrode <NUM> b), the polarity used for programming (writing) or whether the memory element <NUM> is programmed into an amorphous or crystalline state may influence (determine, set, program) a particular behavior or characteristic of the memory element <NUM>, such as the threshold voltage of the memory element <NUM>. The difference in threshold voltages of the memory element <NUM> depending on the logic state stored by the memory element <NUM> (e.g., the difference between the threshold voltage when the memory element <NUM> is storing a logic state '<NUM>' versus a logic state '<NUM>') may correspond to the read window of the memory element <NUM>.

The architecture of memory array <NUM> may in some cases be referred to as a cross-point architecture, in which a memory cell is formed at a topological cross-point between a word line and a bit line as illustrated in <FIG>. Such a cross-point architecture may offer relatively high-density data storage with lower production costs compared to at least some other memory architectures. For example, the cross-point architecture may have memory cells with a reduced area and, resultantly, an increased memory cell density compared to other architectures.

The memory array <NUM> may be configured to support a socket design for a memory device that achieves a desirable ED (e.g., <NUM>, <NUM>, etc.) for each memory cell in the memory array <NUM>. For example, each word line <NUM> and bit line <NUM> may be coupled with a corresponding socket (not shown in <FIG>), and the word line sockets and the bit line sockets may be located such that the ED associated with each memory cell in the memory array <NUM> is the same or similar. This may be achieved, for example, by arranging the rows of bit line sockets and the rows of word line sockets such that the rows of sockets may extend in a direction that is skew (i.e., not orthogonal) to the word lines <NUM> or the bit lines <NUM>. In some cases, the rows of bit line sockets may be parallel to the rows of word line sockets.

<FIG> illustrate examples of socket designs <NUM> for cross-point memory in accordance with examples as disclosed herein. In some cases, the socket designs <NUM> may be incorporated in a memory array <NUM> as described with reference to <FIG> or a memory array <NUM> as described with reference to <FIG>. The socket designs <NUM> may also include memory cells <NUM>, word lines <NUM>, and bit lines <NUM>, which may be examples of a memory cell <NUM>, a word line <NUM>, and a bit line <NUM>, as described with reference to <FIG>.

Each row of memory cells <NUM> may be coupled with a corresponding word line <NUM>, and each column of memory cells <NUM> may be coupled with a corresponding bit line <NUM>. The word lines <NUM> may extend in a first direction, which may correspond to an x direction. The bit lines <NUM> may extend in a second direction, which may correspond to a y direction orthogonal to the x direction. Each word line <NUM> may be coupled with a word line socket in a word line socket region <NUM>, and each bit line <NUM> may be coupled with a bit line socket in a bit line socket region <NUM>. A word line socket is coupled with an end (rather than, e.g., a midpoint) of a corresponding word line <NUM>, and a bit line socket is coupled with an end (rather than, e.g., a midpoint) of a corresponding bit line <NUM>.

The word line sockets in the word line socket regions <NUM> may be organized in rows, which may be parallel to the longer edges of the word line socket regions <NUM>. Similarly, the bit line sockets in the bit line socket regions <NUM> may be organized in rows, which may be parallel to the longer edges of the bit line socket regions <NUM>. Each socket region <NUM>, <NUM> may include any number of rows of sockets. As shown in <FIG>, the longer edges of the bit line socket regions <NUM> may be parallel to the longer edges of the word line socket regions <NUM>, and the rows of bit line sockets may be parallel to the rows of word line sockets. Additionally, the rows of bit line sockets and the rows of word line sockets may be skew (i.e., not orthogonal) and non-parallel to the word lines <NUM> and the bit lines <NUM>.

The word line sockets in the word line socket regions <NUM> may couple the word lines <NUM> with vias that extend below the plane of the word lines <NUM> and the bit lines <NUM>. That is, the vias may extend in a third direction, which may correspond to a z direction that is orthogonal to the x direction and the y direction. Similarly, the bit line sockets in the bit line socket regions <NUM> may couple the bit lines <NUM> with vias that extend below the plane of the word lines <NUM> and the bit lines <NUM>. The vias may be coupled with circuitry (e.g., word line drivers or bit line drivers) that is below the plane of the word lines <NUM> and the bit lines <NUM>.

As illustrated in <FIG>, the word lines <NUM>-a through <NUM>-d may each be coupled with a word line socket in one of word line socket regions <NUM>-a and <NUM>-b and may extend in the x direction away from the word line socket regions <NUM>-a and <NUM>-b and toward bit line socket regions <NUM>-a and <NUM>-b. The word lines <NUM>-a through <NUM>-d may end before reaching bit line socket regions <NUM>-a and <NUM>-b. Similarly, the bit lines <NUM>-a through <NUM>-d may each be coupled with a bit line socket in one of bit line socket regions <NUM>-a and <NUM>-b extend in the y direction away the bit line socket regions <NUM>-a and <NUM>-b and toward word line socket regions <NUM>-c and <NUM>-d. The bit lines <NUM>-a through <NUM>-d may end before reaching word line socket regions <NUM>-c and <NUM>-d.

Memory cells <NUM>-a through <NUM>-j may be located at intersections of the word lines <NUM> and the bit lines <NUM>. For example, the memory cell <NUM>-a may be located at the intersection of the word line <NUM>-d and the bit line <NUM>-a. Based on the socket design <NUM>-a, each memory cell <NUM> (e.g., each of the memory cells <NUM>-a through <NUM>-j) may have a same or similar associated ED (e.g., combined RWL and RBL). In a first example, the memory cell <NUM>-a may be located relatively near the word line socket of the word line <NUM>-d in the word line socket region <NUM>-b and relatively far from the bit line socket of the bit line <NUM>-a in the bit line socket region <NUM>-a. Accordingly, a corresponding word line resistance RWL,<NUM>-a for the memory cell <NUM>-a may be small, and a corresponding bit line resistance RBL,<NUM>-a may be large. In a second example, the memory cell <NUM>-d may be located relatively far from the word line socket of the word line <NUM>-d in the word line socket region <NUM>-b and relatively near the bit line socket of the bit line <NUM>-adin the bit line socket region <NUM>-d. Accordingly, a corresponding word line resistance RWL,<NUM>-d for the memory cell <NUM>-d may be large, and a corresponding bit line resistance RBL,<NUM>-d may be small. In both examples, however, the sum of the word line resistance and the bit line resistance may be the same, as RWL,<NUM>-a + RBL,<NUM>-a = RWL,<NUM>-d + RBL,<NUM>-d, or similar. That is, the ED for the memory cell <NUM>-a may be the same or similar as the ED for the memory cell <NUM>-d. By extension, the ED for each of the memory cells <NUM>-a through <NUM>-j may be the same or similar.

In the socket design <NUM>-b illustrated in <FIG>, a word line <NUM>-e may extend in the x direction away from word line socket region <NUM>-e and toward bit line socket region <NUM>-c. The word line <NUM>-e may end before reaching bit line socket region <NUM>-c. Similarly, a bit line <NUM>-e may extend in the y direction away from bit line socket region <NUM>-c and toward word line socket region <NUM>-e, and the bit line <NUM>-e may end before reaching the word line socket region <NUM>-e. A memory cell <NUM>-k may be located at the intersection of the word line <NUM>-e and the bit line <NUM>-e.

In the example of <FIG>, the word line <NUM>-e and the bit line <NUM>-e may have the same resistivity p. In some examples, the word line <NUM>-e and the bit line <NUM>-e may be composed of the same material. In some other examples, the word line <NUM>-e and the bit line <NUM>-e may be composed of different materials, and the memory device may be manufactured or processed (e.g., such that word lines <NUM> and bit lines <NUM> have different cross-sectional areas, such as different thicknesses) such that the word line <NUM>-e and the bit line <NUM>-e have the same resistivity p. The word line socket region <NUM>-e and the bit line socket region <NUM>-c may both be tilted at an angle <NUM>-a relative to the x direction, which may be <NUM>°.

Based on the socket design <NUM>-b, each memory cell <NUM> (e.g., the memory cell <NUM>-k) may have a same associated ED. That is, the sum RWL + RBL of the word line resistance and the bit line resistance may be the same for each memory cell <NUM>. For example, the memory cell <NUM>-k may be located a distance <NUM>-a from the bit line socket in the bit line socket region <NUM>-c along the bit line <NUM>-e. The distance <NUM>-a may be referred to as LBL· Additionally, the memory cell <NUM>-k may be located a distance <NUM>-b from the word line socket in the word line socket region <NUM>-e along the word line <NUM>-e. The distance <NUM>-b may be referred to as LWL. Because the word lines <NUM> and the bit line <NUM> in the socket design <NUM>-b have the same resistivity p, the sum of the corresponding word line distance and the corresponding bit line distance for each memory cell <NUM> in the socket design <NUM>-b may be the same (LWL + LBL). That is, an increased or decreased distance <NUM>-a from the corresponding bit line socket to a memory cell <NUM> may be compensated by a decreased or increased distance <NUM>-b from the corresponding word line socket to the memory cell <NUM> such that each memory cell <NUM> has the same associated ED.

In the socket design <NUM>-c illustrated in <FIG>, a word line <NUM>-f may extend in the x direction away from word line socket region <NUM>-f and toward bit line socket region <NUM>-d. The word line <NUM>-f may end before reaching bit line socket region <NUM>-d and have a length B. Similarly, a bit line <NUM>-f may extend in the y direction away from bit line socket region <NUM>-d and toward word line socket region <NUM>-f. The bit line <NUM>-f may end before reaching word line socket region <NUM>-f and have a length H. A memory cell <NUM>-l may be located at the intersection of the word line <NUM>-f and the bit line <NUM>-f. The memory cell <NUM>-l may be located a distance <NUM>-d from the bit line socket in the bit line socket region <NUM>-d along the bit line <NUM>-f. The distance <NUM>-d may also be referred to as h. Additionally, the memory cell <NUM>-k may be located a distance <NUM>-c from the word line socket in the word line socket region <NUM>-f along the word line <NUM>-f. The distance <NUM>-c may also be referred to as b.

In the example of <FIG>, the word line <NUM>-f and the bit line <NUM>-f may have different resistivities. For example, the word line <NUM>-f may have a resistivity ρW, and the bit line <NUM>-f may have a resistivity ρB. In some examples, the word line <NUM>-f and the bit line <NUM>-f may be composed of different materials. In some other examples, the word line <NUM>-f and the bit line <NUM>-f may be composed of the same material, and the memory device may be manufactured or processed (e.g., such that word lines <NUM> and bit lines <NUM> have different cross-sectional areas, such as different thicknesses) such that the word line <NUM>-f and the bit line <NUM>-f have the respective resistivities ρW and ρB. The word line socket region <NUM>-f and the bit line socket region <NUM>-d may be tilted at an angle <NUM>-b relative to the x direction, which may not be <NUM>°. The angle <NUM>-b may also be referred to as θ, where H/B = tan(θ). Additionally, the angle θ may be expressed as tan(θ) = h/(B - b).

Based on the socket design <NUM>-c, each memory cell <NUM> (e.g., the memory cell <NUM>-l) may have a same associated ED. That is, the sum RWL + RBL of the word line resistance and the bit line resistance may be the same or similar for each memory cell <NUM>. In order for this sum to be the same or similar for each memory cell <NUM>, a memory cell <NUM> at the furthest distance H from the bit line socket region <NUM>-d and a memory cell <NUM> at the furthest distance B from the word line socket region <NUM>-f may have the same or similar resistance; for example, H · ρB = B · ρW. This equality may be rewritten as H/B = ρW/ρB, where H/B = tan(θ).

For the memory cell <NUM>-l, the sum RWL + RBL may be expressed as h · ρB + b · ρW. By substitution, this sum may also be expressed as (B - b) · tan(θ) · ρB + b · ρW. After rearranging, this sum may become B · tan(θ) · ρB + b · (ρW - ρB tan(θ)), which is the same as B · tan(θ) · ρB + b · (ρW - ρB · ρW/ρB). The second term may be equal to <NUM>, and the first term may be rewritten as B · ρW after a substitution. The resistance B · ρW may be a constant value independent of h and b, meaning the resistance B · ρW (or the equivalent resistance H · ρB) may be the same for each memory cell <NUM> in the socket design <NUM>-c. Accordingly, each memory cell <NUM> in the socket design <NUM>-c may have the same or similar ED.

In each of the socket designs <NUM>, because each memory cell <NUM> has the same or similar associated ED, a memory device may, for example, apply a same voltage Vsource and a same current I to achieve a same voltage drop Vcell across any memory cell <NUM>. This may enable the memory device to avoid large current discharge across near-near memory cells <NUM> due to parasitic capacitance of the word lines <NUM> or the bit lines <NUM> along with sufficient drive current for far-far memory cells <NUM>, which may improve performance and increase the lifetimes of the memory cells <NUM>, regardless of their physical location in a memory array. Additionally, the memory device may avoid any need to determine an appropriate voltage Vsource and an appropriate current I for different memory cells <NUM> at different physical locations, which may reduce a signaling overhead and associated latencies for access operations, among other benefits.

<FIG> illustrate examples of a memory die <NUM> that supports a socket design for a memory device in accordance with examples as disclosed herein. The memory die <NUM> may include one or more memory arrays <NUM>, which may each be an example of a memory array described with reference to <FIG>, <FIG>, or <FIG>.

<FIG> illustrates an example of a memory array <NUM>-a. The memory array <NUM>-a may include word line socket rows <NUM> and bit line socket rows <NUM>. Each word line socket in each word line socket row <NUM> may be coupled with a word line, which may be an example of a word line <NUM> as described with reference to <FIG>. Similarly, each bit line socket in each bit line socket row <NUM> may be coupled with a bit line, which may be an example of a bit line <NUM> as described with reference to <FIG>.

As illustrated in <FIG>, word lines may extend from the word line sockets in the word line socket rows <NUM>, and bit lines may extend from the bit line sockets in the bit line socket rows <NUM>. The word lines that extend from the word line sockets in the word line socket row <NUM>-a may end before reaching the bit line socket row <NUM>-a. Similarly, the bit lines that extend from the bit line sockets in the bit line socket row <NUM>-b may end before reaching the word line socket row <NUM>-b.

The word lines may be orthogonal to the bit lines. The word line socket rows <NUM> may be parallel to the bit line socket rows <NUM>. The word line socket rows <NUM> and the bit line socket rows <NUM> may be skew (i.e., not orthogonal or parallel) to the word lines and the bit lines. Additionally, the word line socket rows <NUM> and the bit line socket rows <NUM> may be parallel to an edge of the memory array <NUM>-a.

As illustrated in <FIG>, multiple bit line socket rows <NUM> (e.g., the bit line socket rows <NUM>-a and <NUM>-b) may be located between the consecutive word line socket rows <NUM>-a and <NUM>-b. Bit line socket rows <NUM>-a and <NUM>-b may be considered as included in a single bit line socket region, and word line socket rows <NUM>-a and <NUM>-b may be considered as included in distinct word line socket regions, and thus bit regions and word line regions may alternate, even if multiple rows of a given socket type are between rows of another socket type.

In some examples, such as in a multi-deck configuration, more than two socket rows of a given type may be located in a socket region, where a socket region may be considered a 3D space that includes overlaying 2D areas within different layers that include sockets. For example, within a single socket region, rows of sockets and vias coupled with access lines for one deck may be located between rows of sockets and vias couple with access lines for another deck.

<FIG> illustrates an example layout for a memory die <NUM>. The memory die <NUM> may include multiple memory arrays <NUM>-b, <NUM>-c, and <NUM>-d. Each memory array <NUM> may include word lines, bit lines, bit line socket rows <NUM>, and word line socket rows <NUM> as described with reference to <FIG> or otherwise as described herein, where the socket rows <NUM>, <NUM> may be grouped and/or included in corresponding socket regions. The word line socket rows <NUM> and the bit line socket rows <NUM> of a memory array <NUM> may be parallel to a first edge of the memory die <NUM>. Additionally, the word line socket rows <NUM> and the bit line socket rows <NUM> of a memory array <NUM> may be perpendicular (orthogonal) to a second edge of the memory die <NUM>. The word lines and bit lines may be skew (i.e., neither orthogonal nor parallel) to both the word line socket rows <NUM> and the bit line socket rows <NUM> along with at least two (in some cases all) edges of the memory die <NUM>.

The memory die <NUM> may also include periphery areas <NUM> located between the memory arrays <NUM> (e.g., between socket regions associated with neighboring memory arrays <NUM>). Additional circuitry (e.g., power buses) for operating a memory device may be located beneath the periphery areas <NUM>.

<FIG> illustrates an example of a socket region <NUM> that supports a socket design for a memory device in accordance with examples as disclosed herein. The socket region <NUM> may include sockets <NUM> of a first deck of a memory device, where each socket <NUM> may be coupled with an access line <NUM> of the first deck, which may be an example of a word line <NUM> or a bit line <NUM> described with reference to <FIG>. The socket region <NUM> may also include sockets <NUM> of a second deck of the memory device, where each socket <NUM> may be coupled with an access line <NUM> of the second deck. The second deck may be located above or below the first deck. The socket region <NUM> may also include through vias (e.g., through-silicon vias (TSVs)) <NUM> that may pass through multiple decks, and potentially through the die that includes socket region <NUM>. The access lines <NUM> and <NUM> may extend in a first direction, which may be the x direction or the y direction.

Each socket <NUM>, <NUM> may couple an access line <NUM>, <NUM> with a via that extends from the first deck or the second deck in the z direction. The vias may be coupled with circuitry (e.g., power buses, a memory controller, etc.) which may be located below the decks of the memory device. Because the vias may extend across all the decks of the memory device, one or more rows of sockets <NUM> for one deck may be between one or more rows of sockets <NUM> may be for another deck. Additionally, the sockets <NUM>, <NUM> may be wide compared to the spacing of adjacent access lines <NUM>, <NUM>, and so the sockets <NUM> may be staggered in the first direction to allow for a greater density of access lines <NUM>, <NUM> in each first deck. Staggered sockets <NUM>, <NUM> may include parallel rows <NUM> of sockets <NUM>, <NUM>, where access lines <NUM>, <NUM> coupled with sockets <NUM>, <NUM> of one row <NUM> are separated by access lines <NUM>, <NUM> coupled with sockets <NUM>, <NUM> of one or more other rows <NUM>.

<FIG> includes the sockets <NUM>, <NUM> for the first and second decks, respectively. The socket region <NUM> may further include additional sockets (not shown) for any number of additional decks. As more sockets for additional decks are added to the socket region <NUM>, the socket region <NUM> may become wider to ensure that the vias for the decks are separated (insulated) from one another.

<FIG> shows a flowchart illustrating a method or methods <NUM> that supports a socket design for a memory device in accordance with examples as disclosed herein. The operations of method <NUM> may be implemented by a memory device or its components as described herein. For example, the operations of method <NUM> may be performed by a memory device as described with reference to <FIG>. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform examples of the described functions using special-purpose hardware.

At <NUM>, the memory device may receive an access command for a memory cell coupled with a first access line and a second access line. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the memory device may route, based on the access command, a current through the memory cell, the first access line, a first socket coupled with the first access line, the second access line, and a second socket coupled with the second access line, where the first socket is included in a first row of sockets and the second socket is included in a second row of sockets that is parallel to the first row. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the memory device may read or write the memory cell based on the current. The operations of <NUM> may be performed according to the methods described herein.

In some examples, an apparatus as described herein may perform a method or methods, such as the method <NUM>. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving an access command for a memory cell coupled with a first access line and a second access line, routing, based on the access command, a current through the memory cell, the first access line, a first socket coupled with the first access line, the second access line, and a second socket coupled with the second access line, where the first socket is included in a first row of sockets and the second socket is included in a second row of sockets that is parallel to the first row, and reading or writing the memory cell based on the current.

In some examples of the method <NUM> and the apparatus described herein, the first row of sockets may be non-orthogonal to the first access line, and the second row of sockets may be non-orthogonal to the second access line.

In some examples of the method <NUM> and the apparatus described herein, the first row of sockets may be non-orthogonal to the second access line, and the second row of sockets may be non-orthogonal to the first access line.

Further, portions from two or more of the methods may be combined. For the avoidance of doubt, any variations on the above methods and apparatus are permitted provided they fall within the scope of the appended claims.

As used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly coupled with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term "coupling" refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term "isolated" refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The term "layer" used herein refers to a stratum or sheet of a geometrical structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration.

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to achieve the advantages of the characteristic.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory array.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and include a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may include a heavily doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are signals), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

" The detailed description includes specific details to providing an understanding of the described techniques. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Claim 1:
An apparatus (<NUM>), comprising:
a set of first access lines (<NUM>, <NUM>, <NUM>, <NUM>-a, <NUM>-b, <NUM>, <NUM>-a, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>) for a memory array (<NUM>, <NUM>, <NUM>, <NUM>-a...<NUM>-d) that extend in a first direction;
a set of second access lines (<NUM>, <NUM>, <NUM>, <NUM>-a, <NUM>-b, <NUM>, <NUM>-a, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>) for the memory array (<NUM>, <NUM>, <NUM>, <NUM>-a... <NUM>-d) that extend in a second direction;
a set of first sockets (<NUM>, <NUM>) each coupled with an end of a respective first access line (<NUM>, <NUM>) of the set (<NUM>, <NUM>, <NUM>, <NUM>-a, <NUM>-b, <NUM>, <NUM>-a, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>) and with a respective first driver of a set of first drivers, the set of first sockets (<NUM>, <NUM>) arranged in a first row (<NUM>, <NUM>-a... <NUM>-c) that extends in a third direction; and
a set of second sockets (<NUM>, <NUM>) each coupled with an end of a respective second access line (<NUM>, <NUM>) of the set (<NUM>, <NUM>, <NUM>, <NUM>-a, <NUM>-b, <NUM>, <NUM>-a, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>-a...<NUM>-f, <NUM>, <NUM>) and with a respective second driver of a set of second drivers, the set of second sockets (<NUM>, <NUM>) arranged in a second row (<NUM>, <NUM>-a... <NUM>-c) that is parallel to the first row and extends in the third direction, the third direction non-parallel to both the first direction and the second direction.