Patent Description:
The present disclosure relates generally to methods and apparatuses having improved clocking scheme to receive data and more particularly, to methods and apparatuses utilizing an internal clock generated by a host to receive data from a memory.

A computing device (e.g., a laptop, a mobile phone, etc.) may include one or several processors to perform various functions, such as telephony, wireless data access, and camera/video function, etc. A memory is an important component of the computing device. The one processor may be coupled to the memory to perform the aforementioned computing functions. For example, the one processor may fetch instructions from the memory to perform the computing function and/or to store within the memory temporary data for processing these computing functions, etc. Improvements in performance of the memory would likewise improve the computing device.

Attention is drawn to <CIT> relating to a method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.

Further attention is drawn to <CIT> relating to an integrated circuit device in a low-power signaling system including an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Attention is also drawn to <CIT> relating to a signaling system including a first integrated circuit, IC, chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Further attention is drawn to <CIT> relating to a memory device having a memory core and a signal interface, receiving a command that specifies a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.

This summary identifies features of some example aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Additional features and aspects are described and will become apparent to persons skilled in the art upon reading the following detailed description and viewing the drawings that form a part thereof.

An apparatus in accordance with at least one embodiment includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.

Another apparatus in accordance with at least one embodiment includes a host configured to communicate with a memory via a link. The host is further configured to receive a clock at a frequency from the memory in a training mode; to receive, based on the clock, data from the memory, in a first mode of a read operation; to disable the memory from generating the clock; and to receive data from the memory at the frequency, in the second mode of the read operation with the clock disabled.

A method to reduce power in a system includes receiving, by a host, a first clock from a memory; receiving, by the host and based on the first clock, data from the memory, in a first mode of a read operation; generating, by the host, a second clock, the second clock being generated independent of the first clock; and receiving, by the host and based on the second clock, data from the memory.

Various aspects of apparatus and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:.

The detailed description includes specific details for providing a thorough understanding of various concepts. In some instances, well known structures and components are shown in block diagram form to avoid obscuring such concepts.

As used herein, the term "coupled to" in the various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B), to operate certain intended functions. For example, the term "coupled" may mean that elements A and B communicate or having a transfer of information, either directly or via other elements.

In cases of electrical components, the term "coupled to" may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" may mean a transfer of electrical energy between elements A and B, to operate certain intended functions. In some examples, the term "electrically connected" or "directly coupled" may mean having an electric current or configurable to having an electric current flowing between the elements A and B. For example, the elements A and B may be connected via resistors, transistors, or an inductor, in addition to a wire, trace, or other electrically conductive material and components. Furthermore, for radio frequency functions, the elements A and B may be "electrically connected" via a capacitor.

The terms "first," "second," "third," etc. are employed for ease of reference and may not carry substantive meanings. Likewise, names for components/modules may be adopted for ease of reference and might not limit the components/modules. For example, such non-limiting names may include "enable" circuit. In some examples, modules and components presented in the disclosure may be implemented by circuits. Such circuits may operate, at least in part, in accordance with software/firmware instructions.

The terms "bus system" and/or "signal connection" may provide that elements coupled thereby may exchange information therebetween, directly or indirectly. In such fashion, the terms "bus system" and/or "signal connection" may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc..

In the disclosure, a memory may be embedded with a processor on a semiconductor die or be part of a semiconductor die different from the processor. The memory may perform various functions. For example, the memory may be used as cache, register file, or storage. The memory may be of various kinds. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc..

As demands grow for the computing device to perform more functions with increasing speed, power issue grows as well. While power savings may be of particular interest in mobile computing devices, non-mobile devices may also benefit from reduced power consumption to reduce waste heat generation. Thus, computing devices of various sorts may benefit from memory systems having reduced power consumption. Schemes to reduce power consumption are thus desirable.

Methods and apparatuses utilizing an internal, host-generated clock to receive data with data clock disabled are presented. In some examples, in a read mode and/or operation, a host (e.g., incorporating a memory controller) may receive data from a memory via source synchronous clocking. For example, the host may receive read data and a read clock (e.g., read data strobe or RDQS) from the memory. The read data may be synchronized with the read clock such that the host may receive (e.g., latch, sample, or capture) the read data based on the read clock. However, for low speed communications, the host might not need a synchronized data clock to receive read data. Thus, it would be advantageous to disable the read clock to further reduce power consumption for low speed communications.

Methods and apparatuses are presented in the present disclosure by way of non-limiting examples of Low-Power Double Data Rate (LPDDR) Synchronous Dynamic Random Access Memory (SDRAM). For example, the LPDDR memory operating in accordance with LPDDR specification promulgated by Joint Electronic Device Engineering Council (JEDEC). Such LPDDR specification may be LPDDR5. Moreover, read data is adopted as an example of data in this disclosure. In some examples, the term "data" may refer to information provided by the memory to a host.

<FIG> illustrates an apparatus <NUM> incorporating a host <NUM>, a memory <NUM>, and a link <NUM> coupling the host <NUM> and the memory <NUM>, in accordance with certain aspects of the disclosure. The apparatus <NUM> may be, for example, one of computing systems (e.g., servers, datacenters, desktop computers), mobile computing device (e.g., laptops, cell phones, vehicles, etc.), Internet of Things devices, virtual reality (VR) systems, or augmented reality (AR) systems, etc. The host <NUM> may be configured to communicate (e.g., read, write, request for information, interrupts, etc.) with the memory <NUM> via the link <NUM>. <FIG> illustrates that host includes the at least one processor <NUM> coupled to a memory controller <NUM> via a bus system <NUM>, the at least one processor <NUM> being coupled to the memory <NUM> via the memory controller <NUM> and the link <NUM>. The memory may be an LPDDR DRAM (e.g., LPDDR5). The host <NUM>, the memory <NUM>, and/or the link <NUM> may operate according to an LPDDR (e.g., LPDDR5) specification.

The host <NUM> may include at least one processor <NUM> coupled to the memory <NUM> via the link <NUM> to perform computing functions, such data processing, data communication, graphic display, camera, AR or VR rendering, image processing, etc. For example, the memory <NUM> may store instructions or data for the at least one processor <NUM> to perform the aforementioned computing functions. The at least one processor <NUM> may include a collection of processing logics or one or more central processing units. For example, the at least one processor <NUM> may be a central processing unit (CPU) <NUM>, a graphic processing unit (GPU) <NUM>, or a digital signal processor (DSP) <NUM> configured to implement the computing functions. <FIG> further illustrates the at least one processor <NUM> being coupled to the memory controller <NUM> via the bus system <NUM>.

The memory controller <NUM> may include a control module <NUM> and a host I/O module <NUM>. The host I/O module <NUM> may be configured to output and/or to receive signals on the link <NUM>. The host I/O module <NUM> may be known as a PHY layer and be configured to control electrical characteristics (e.g., voltage levels, phase, delays, frequencies, etc.) or to receive signals based on the electrical characteristics of signaling on the link <NUM>. The control module <NUM> may be configured to issue commands (e.g., read, write, or to select operating modes) to the memory <NUM> via the link <NUM>.

In some examples, the host <NUM> (e.g., the control module <NUM>) may issue a read command to the memory <NUM>, via the host I/O module <NUM> and the link <NUM>, to enact a read mode and/or operation. Further, the host <NUM> (e.g., the host I/O module <NUM>) may be configured to receive a data clock (e.g., RDQS) from the memory <NUM> via the link <NUM> for the read mode and/or operation. For reference, the data clock RDQS may be referred to as a first clock. The host <NUM> (e.g., the memory controller <NUM>) may be further configured to receive, based on the data clock RDQS, read data from the memory <NUM> via the link <NUM> (e.g., DQs) in a first mode (e.g., a first setting) of the read mode and/or operation. The first mode may be, for example, a high-speed mode and may enable and utilize the data clock RDQS for the read mode and/or operation. In some example, high-speed and/or low-speed modes or settings are referenced in terms of relativity, and not absolute operating speeds. In some example, the memory <NUM> may output and provide the data clock RDQS and the read data in synchronization (e.g., phase and/or frequency synchronized) to allow the host I/O module <NUM> to receive (e.g., to latch, sample, or capture), based on the data clock RDQS (e.g., the first clock), the read data.

The host <NUM> (e.g., the host I/O module <NUM>) may be further configured generate to adjust the generation of an internal clock (for reference, a second clock) based on the data clock RDQS (e.g., the first clock) received by the host <NUM>. For example, the control module <NUM> may be configured to issue a training command to the memory <NUM>, via the host I/O module <NUM> and the link <NUM>, to enact a training mode and/or operation. In response, the host <NUM>, the memory <NUM>, may link <NUM> may operate the training mode and/or operation. In the training mode and/or operation, the host <NUM> (e.g., the host I/O module <NUM>) may be configured adjust a generation of the internal clock to synchronize the internal clock in phase and/or frequency with the received data clock RDQS. Such training may be known as read clock window training.

The host <NUM> (e.g., the control module <NUM>) may be further configured to instruct the memory <NUM> to disable outputting the data clock RDQS, to communicate in a second mode (e.g., a second setting) of the read mode and/or operation. In some examples, the second mode may correspond to a read mode and/or operation without using the data clock RDQS. In some example, the second mode may be a slow-speed mode or setting. In response, the memory <NUM> may output read data without outputting the data clock RDQS. The host <NUM> (e.g., the host I/O module <NUM>) may be further configured to generate the internal clock not from the received data clock RDQS. For example, the host <NUM> may be configured to generate the internal clock independent of the received data clock RDQS, and/or the data clock RDQS might not be used as an input in the generation of the internal clock.

The host <NUM> (e.g., the host I/O module <NUM>) may be further configured receive, based on the internal clock generated independent of the data clock RDQS, read data from the memory <NUM> in the second mode of the read mode and/or operation. In some examples, since the internal clock was adjusted to synchronize with the data clock RDQS in the training operation, the host (e.g., the control module <NUM>) may be configured to receive read data without using the data clock RDQS. For example, the host <NUM> (e.g., the host I/O module <NUM>) may latch, sample, or capture the read data from the link <NUM> using the internal clock instead of the data clock RDQS (the memory <NUM> may stop outputting the data clock RDQS in this case). In such fashion, power consumed by outputting the data clock RDQS and toggling the data clock RDQS in the link <NUM> could be conserved.

In some examples, the link <NUM> may be a chip-to-chip or a die-to-die link between the host <NUM> and the memory <NUM>, the host <NUM> and the memory <NUM> being on different dies. In some examples, the link <NUM> may be an in-die link, the host <NUM> and the memory <NUM> being on a same die. For example, the link <NUM> may include multiple signal lines, including signal lines to transmit unidirectional signals from the host <NUM> to the memory <NUM> (e.g., write data clock (WCK), command and address (CA), CA clock (CLK) etc.) and bidirectional directional signals (e.g., data or DQs), read data strobe clock (RDQS), etc.). For example, the CA may include a CAS signaling/pin, a chip select (CS) signaling/pin, and column address (CA) signaling. The link <NUM> and signaling between the host <NUM> and the memory <NUM> may be in accordance with the JEDEC DRAM specification (e.g., LPDDR5).

<FIG> illustrates the memory <NUM> having a memory I/O module <NUM>, a memory array <NUM>, a mode register <NUM>, and a command and control module <NUM>, the components being coupled via a bus system <NUM>. The memory <NUM> may be configured to communicate with the host <NUM> via the link <NUM>. For example, the memory <NUM> may be configured to store write data in the memory array <NUM>, in response to a write command from the host <NUM> (e.g., a write operation). The write data and the write command may be received from the host <NUM> via the link <NUM>. The memory <NUM> may be configured to output data stored in the memory array <NUM> as read data, in response to a read command from the host <NUM> (e.g., a read mode and/or operation). The read data and the read command may be received from the host <NUM> via the link <NUM>. Other communications may include mode register reads and/or writes to adjust operating modes or conditions of the memory <NUM> and to provide information on the operating modes or conditions of the host <NUM> and/or the memory <NUM>.

To facilitate communications to/from the host <NUM>, the memory array <NUM> may be configured to store write data and to output stored data as read data, via the link <NUM> and the memory I/O module <NUM>, from and to the host <NUM>. The mode register <NUM>, which may include multiple registers, may be configured to store operating modes and/or conditions of the memory <NUM>. The mode register <NUM> may include a RDQS mode register <NUM>. The host <NUM> (e.g., the control module <NUM>) may be configured to instruct the memory <NUM> to disable outputting the data clock RDQS to communicate in the second mode of the read mode and/or operation. For example, the host <NUM> may turn off the data clock RDQS by accessing (reading or writing) the mode register <NUM> (e.g., the RDQS mode register <NUM>) via the link <NUM> and the memory I/O module <NUM>. Consequently, the memory <NUM> may output read data without outputting the data clock RDQS (e.g., in a second mode of the read mode and/or operation), in response to a mode or setting of the RDQS mode register <NUM>.

The command and control module <NUM> may be configured to receive commands from the host <NUM> via the link <NUM> (e.g., CAs) and the memory I/O module <NUM>. The commands may include read, write, mode register read/write, etc. The commands may include a training mode command that places the memory <NUM> in a training mode and/or operation. The command and control module <NUM> may be configured to decode various commands provided by the host <NUM> (e.g., the memory controller <NUM>) via the link <NUM> and to arrange the memory <NUM> to operate according to the commands. For example, the command and control module <NUM> may be configured to decode a training command that puts the memory <NUM> into a training mode and/or operation. In the training mode and/or operation, the memory <NUM> may be configured to output the data clock RDQS at a predetermined frequency (without outputting data).

The memory I/O module <NUM> may be configured to drive and to receive signals on the link <NUM>. The memory I/O module <NUM> may be known as a PHY layer and be configured to control electrical characteristics (e.g., voltage levels, phase, delays, frequencies, etc.) or to receive signals based on the electrical characteristics of signaling on the link <NUM>. For example, memory I/O module <NUM> may be configured to capture (e.g., to sample) write data from the host <NUM> via the link <NUM> (e.g., DQs) based on the data clock WCK. In some examples, the memory I/O module <NUM> may be configured to output read data to the host <NUM> via the link <NUM> (e.g., DQs) based on a data clock RDQS in a first mode (e.g., a high-speed setting or mode) of a read mode and/or operation. For example, the host I/O module <NUM> may be configured to synchronize read data with the data clock RDQS and output the data clock RDQS with read data. In some examples, based on a setting or mode of the RDQS mode register <NUM>, the memory I/O module <NUM> may be configured to output read data and not the data clock RDQS (e.g., a second mode of the read mode and/or operation).

For a write operation, the at least one processor <NUM> may issue a write request to the memory controller <NUM> via the bus system <NUM>. The memory controller <NUM> may issue a WRITE command via CA and CLK of the link <NUM> to the memory <NUM>. Write data are provided by the memory controller <NUM> via DQs of the link <NUM>, clocked by the data clock WCK. In response, the memory <NUM> stores the write data into the memory array <NUM>, addressed by the WRITE command.

<FIG> illustrates portions of the host I/O module <NUM> of <FIG> configured to generate and to adjust the generation of the internal clock, in accordance with certain aspects of the present disclosure. <FIG> illustrates the host <NUM> components, including a clock source <NUM>, an internal clock module <NUM>, an internal clock control <NUM>, and input circuits 206_1 and 206_2. As illustrated, the internal clock module <NUM> may include a calibrated delay circuit <NUM>, a phase detector <NUM>, a multiplexer <NUM>, an enable circuit <NUM>, and various signal connections. The input circuits 206_1, 206_2 may be configured to receive signals external to the host <NUM> and may include, for example, input buffers/latching circuits. The input circuit 206_1 may be configured to receive the data clock RDQS from the memory <NUM> and output an internal version of the data clock RDQS, based on the received data clock RDQS, onto a signal connection <NUM>. The signal connection <NUM> may be provided to the internal clock module <NUM>.

In a high-speed mode (e.g., a first setting or mode of a read mode and/or operation), the host <NUM> may be configured to receive (e.g., to capture, sample, or latch), based on the data clock RDQS, data (e.g., DQs) from the memory <NUM> in the high-speed mode of the read mode and/or operation. For example, the internal clock module <NUM> may be configured to provide clocking, based on the received data clock on the signal connection <NUM>, to the input circuit 206_2 via the multiplexer <NUM>, the signal connection <NUM>, the enable circuit <NUM>, and the signal connection <NUM>, in the high-speed mode of the read mode and/or operation.

In a low-speed mode (e.g., a second mode or setting) of the read mode and/or operation, jitters on the received data may be relatively negligible or be absorbed by timing margins. The internal clock module <NUM> may be further configured to generate the internal clock (e.g., the second clock) on the signal connection <NUM> independent of the received data clock RDQS, in the low-speed mode of the read mode and/or operation. For example, the data clock RDQS (e.g., the first clock) might not be an input in generating the internal clock (e.g., the second clock). The host <NUM> may be configured to receive (e.g., via the input circuit 206_2), based on the internal clock on the signal connection <NUM> (e.g., the second clock) and not the first clock, data (e.g., DQs) from the memory <NUM>. Thus, in one aspect of the disclosure, the host <NUM> may be configured to instruct the memory <NUM> to disable outputting the data clock RDQS (e.g., the first clock) to communicate in the low-speed mode (e.g., the second setting or mode of the read mode and/or operation). In such fashion, power consumption for clocking the data clock RDQS on the link <NUM> may be eliminated.

The clock source <NUM> may be configured to provide a reference clock on a signal connection <NUM> to the calibrated delay circuit <NUM>. The calibrated delay circuit <NUM> may be configured to adjust delay/phase/frequency of the reference clock, based on a control or setting on a signal connection <NUM>. The calibrated delay circuit <NUM> may be further configured to output a calibrated reference clock, onto a signal connection <NUM>, as an input to the phase detector <NUM>. The calibrated delay circuit <NUM> may be further configured to output the calibrated reference clock, onto the signal connection <NUM>, as an input to a multiplexer <NUM>. The control signal on a signal connection <NUM> may be outputted by an internal clock control <NUM>.

The host <NUM> may receive the data clock RDQS from the memory <NUM> via the input circuit 206_1, which may be configured to output, as a received data clock RDQS, onto a signal connection <NUM> and as another input to the multiplexer <NUM>. The multiplexer <NUM> may be configured to select among the calibrated reference clock on the signal connection <NUM> and the received data clock RDQS on the signal connection <NUM>, based on a select signal on a signal connection <NUM>, and configured to output a selected signal onto a signal connection <NUM>. Via the signal connection <NUM>, the multiplexer <NUM> may be configured to output the selected signal to the phase detector <NUM> and an enable circuit <NUM>. The select signal on the signal connection <NUM> may be outputted by the internal clock control <NUM>.

The enable circuit <NUM> may be configured to output the selected signal on the signal connection <NUM> to the signal connection <NUM> as the internal clock, based on an enable signal on a signal connection <NUM>. The enable signal on the signal connection <NUM> may be outputted by the internal clock control <NUM>. For example, the enable circuit <NUM> may be configured to enable or disable outputting the internal clock onto the signal connection <NUM> based on the enable signal on the signal connection <NUM>. In some examples, the enable circuit <NUM> may be configured to output the internal clock (e.g., the second clock), outputting the internal clock being gated an enable signal. For example, the enable circuit <NUM> may include a gating circuit where an output is gated by the enable signal. In such fashion, a number of pulses of the internal clock may correspond (e.g., controlled by) an ON duration of the enable signal.

In a training mode and/or operation, the memory <NUM> may be configured to output the data clock RDQS at a frequency to allow the host <NUM> to calibrate internal settings in a generation of the internal clock to receive data (e.g., DQs) from the memory <NUM>. For example, the host <NUM> may be configured to adjust, in the training mode and/or operation, the generation of the internal clock based on the data clock RDQS. Examples of such training mode and/or operation are presented herein. The internal clock control <NUM> may be configured to output the select signal on the signal connection <NUM> such that the multiplexer <NUM> selects the received data clock RDQS on the signal connection <NUM> and outputs to the phase detector <NUM> on the signal connection <NUM>. The phase detector <NUM> may be configured to detect a phase difference between the received data clock RDQS outputted by the multiplexer <NUM> and the calibrated reference clock on the signal connection <NUM> (from the calibrated delay circuit <NUM>). The phase detector <NUM> may be further configured to output the phase difference, via the signal connection <NUM>, to the internal clock control <NUM>.

In response to the phase difference on the signal connection <NUM>, the internal clock control <NUM> may be configured to adjust a setting of the calibrated delay circuit <NUM> via the signal connection <NUM>. In a subsequent cycle in the training mode and/or operation, the calibrated delay circuit <NUM> may be configured to adjust the reference clock received on the signal connection <NUM>, based on the setting on the signal connection <NUM>, and to output the calibrated reference clock to the multiplexer <NUM> and to the phase detector <NUM> (via the signal connection <NUM>). In such fashion, the setting of the calibrated delay circuit <NUM> may be adjusted such that the outputted calibrated reference clock may be in phase and/or frequency synchronization with the received data clock RDQS. Such setting may be stored (e.g., by the internal clock control <NUM>) to generate the internal clock (e.g., the second clock), via the enable circuit <NUM>, in a read mode and/or operation subsequent to the training mode and/or operation. In such fashion, the host <NUM> may be configured to synchronize the internal clock (e.g., the second clock) with the data clock RDQS (e.g., the first clock) to adjust the generation of the internal clock.

In a read mode and/or operation, the memory <NUM> may be configured to output data stored in the memory array <NUM> (see <FIG>) via the link <NUM> (e.g., DQs), in response to a read command from the host <NUM>. The host <NUM> may be configured to utilize different clock schemes to receive the data from the memory <NUM> in different settings or modes of the read mode and/or operation. For example, in the high-speed mode (e.g., the first mode or setting), the host <NUM> may be configured to receive, based on the data clock RDQS, the data on DQs via input circuit 206_2. In the low-speed mode (e.g., the second mode or setting), the host <NUM> may be configured to receive, based on the internal clock on the signal connection <NUM>, the data on DQs via input circuit 206_2.

In the low-speed mode, the internal clock might be generated independent of (e.g., not from) the data clock RDQS. For example, in the low-speed mode, the internal clock control <NUM> may be configured to, via signal connection <NUM>, cause the calibrated delay circuit <NUM> to output a calibrated reference clock onto the signal connection <NUM>. In the low-speed mode, the calibrated reference clock may be in phase and/or frequency synchronization with an expected data clock RDQS, as a result of the training mode. Thus, the calibrated delay circuit <NUM> may output a version of the internal clock onto the signal connection <NUM>. The multiplexer <NUM> may be configured to select the calibrated reference clock on the signal connection <NUM> (and not select the received data clock RDQS on the signal connection <NUM>) to output to the enable circuit <NUM>, in generating the internal clock on the signal connection <NUM>. In some examples, the terms "high-speed" and "low-speed" denote relative operating or I/O speeds, and not necessarily defined in by absolute speeds.

In some examples, the multiplexer <NUM> may be configured to select among the host <NUM> receiving data based on the data clock RDQS and receiving data based on the internal clock generated independent of (e.g., not generated from) the data clock RDQS. For example, in the high-speed mode, the internal clock control <NUM> may be configured to arrange the select signal on the signal connection <NUM> to facilitate the multiplexer <NUM> to select the received data clock on the signal connection <NUM>. The input circuit 206_2 may be configured to receive data on DQs based on (e.g., clocked by) the selected received data clock RDQS (via the signal connection <NUM>, the enable circuit <NUM>, the signal connection <NUM>). In the low-speed mode, the internal clock control <NUM> may be configured to arrange the select signal on the signal connection <NUM> to facilitate the multiplexer <NUM> to select the calibrated reference clock on the signal connection <NUM>. The calibrated delay circuit <NUM> may be configured to output the calibrated reference clock onto the signal connection <NUM>, based on a mode provided on the signal connection <NUM>.

The internal clock control <NUM> may be configured to store the setting obtained from a previous training mode and/or operation. The setting could be such that the calibrated reference clock on the signal connection <NUM> (and therefore, the internal clock on the signal connection <NUM>) would be in phase and/or frequency synchronization with the data clock RDQS. Further in the low-speed mode, the enable circuit <NUM> may be configured to enable the internal clock onto the signal connection <NUM>, based on an output of the multiplexer <NUM> on the signal connection <NUM>. In such fashion, in the low-power mode, the internal clock is generated independent of (e.g., not generated from) the data clock RDQS. For example, the data clock RDQS is not an input (e.g., not selected by the multiplexer <NUM>) in generating the internal clock on the signal connection <NUM> used to receive data on the DQs.

As presented above, the enable circuit <NUM> may configured to enable receiving data from the memory <NUM> in both the high-speed and the low-speed modes the read mode and/or operation, based on the enable signal on the signal connection <NUM>. The internal clock control <NUM> may be configured to generate the enable signal on the signal connection <NUM> based on (e.g., having an ON period corresponding to) a burst length of the read mode and/or operation. For example, based on a clock period of the data clock RDQS and/or the internal clock, the internal clock control <NUM> may be configured to have the enable signal on for an on period corresponding to a number of the burst length multiplied by the clock period. In such fashion, the burst length control and the enable circuit <NUM> are used for both the high-speed and the low-speed modes of the read mode and/or operation, reducing an overhead of the improved clock scheme to receive data in the present disclosure.

<FIG> illustrates a relationship between the enable signal (e.g., on the signal connection <NUM> in <FIG>) and clocking, in accordance with circuit aspects of the present disclosure. In the training mode and/or operation, the enable signal does not need to be turned on, as no data are received. In a burst operation of the read mode and/or operation, the enable signal is ON for a period corresponding to a burst length of data (e.g., DQs) from the memory <NUM>.

In some examples, referring to <FIG> and <FIG>, the apparatus <NUM> includes the host <NUM> configured to communicate with the memory <NUM> via the link <NUM>. The host <NUM> may be further configured to receive a clock (e.g., the data clock RDQS) at a frequency from the memory <NUM> in a training mode. In the training mode, the host <NUM> may train a generation of an internal clock at synchronize with clock at the frequency. The host <NUM> may be further configured to receive, based on the clock, data from the memory <NUM>, in a first mode of a read operation. For example, in a high-speed mode of the read mode and/or operation, the host <NUM> may receive data on DQs based on the data clock RDQS.

The host <NUM> may be further configured to disable the memory <NUM> from generating the clock. For example, the host <NUM> may write to the RDQS mode register <NUM> (see <FIG>) to inform the memory <NUM> to disable a generation of the data clock RDQS. The host <NUM> may be further configured to receive data from the memory <NUM> at the frequency, in the second mode of the read operation with the clock disabled. For example, in a low-speed mode, the memory <NUM> may output data at the DQs with the data clock RDQS disabled. The data at the DQs may be outputted at the frequency at which the host <NUM> training the internal clock (e.g., at the signal connection <NUM>). Accordingly, the host <NUM> would be receive data at the DQs at the frequency using the internal clock, in the low-speed mode of the read operation with the data clock RDQS disabled.

<FIG> illustrates another example of portions of the host I/O module <NUM> of <FIG> configured to generate and to adjust the generation of the internal clock, in accordance with certain aspects of the present disclosure. In reference to <FIG>, reference characters are preserved for performing or having same or similar functions/structures. In <FIG>, the clock source <NUM> may be configured to provide a reference clock on a signal connection <NUM> to an enable circuit <NUM>. The enable circuit <NUM> may be configured to enable generating the second clock in the low-speed or second mode and to disable generating the second clock in the high-speed or first mode of the read mode and/or operation, based on an enable signal on the signal connection <NUM>. For example, in the low-speed mode, the enable circuit <NUM> may be configured to provide the reference clock onto the signal connection <NUM> and to provide the reference clock to the calibrated delay circuit <NUM>.

The calibrated delay circuit <NUM> may be configured to output a calibrated reference clock, based on a setting provided on the signal connection <NUM>, onto the signal connection <NUM>. Based on the training mode, the internal clock control <NUM> may be configured to provide the setting on the signal connection <NUM> such that the calibrated reference clock on the signal connection <NUM> correspond to a version of the internal clock. For example, the calibrated reference clock or the version of the internal clock outputted by the calibrated delay circuit <NUM> onto the signal connection <NUM> may be in phase and/or frequency synchronization of the data clock RDQS in the slow-speed mode. The data clock RDQS in the slow-speed mode might not be outputted by the memory <NUM> or received by the host <NUM>, in some examples. In the high-speed mode, the enable circuit <NUM> may be configured to disable generating the internal clock at an input of the multiplexer <NUM> (e.g., on the signal connection <NUM>). For example, the enable circuit <NUM> may be configured to not provide the reference clock onto the signal connection <NUM> and to the calibrated delay circuit <NUM>. In such fashion, since the internal clock is not used on the high-speed mode of the read mode and/or operation, power to generate the internal clock would be saved.

<FIG> illustrates operations of an improved clocking scheme between the host <NUM> and the memory <NUM> over the link <NUM> of <FIG>, in accordance with certain aspects of the present disclosure. These operations may be performed by, for example, structures presented with <FIG> and <FIG>. At <NUM>, a first clock is received by a host from a memory. For example, referring to <FIG>, the host <NUM>, via the host I/O module <NUM>, receives the data clock RDQS from the memory <NUM>. Referring to <FIG>, the host including the input circuit 206_1 receives the data clock RDQS from the memory <NUM> and outputs the received data clock RDQS onto the signal connection <NUM>.

At <NUM>, data from the memory are received by the host based on a first clock, in a first mode of a read mode and/or operation. For example, referring to <FIG>, data on the DQs are received by the input circuit 206_2 based on the received data clock RDQS, in a high-speed mode of a read mode and/or operation.

At <NUM>, a second clock is generated by the host, the second clock being generated independently of the first clock. For example, referring to <FIG>, the host <NUM> generates the internal clock on the signal connection <NUM> not from the data clock RDQS in a low-speed mode of the read mode and/or operation. In the low-speed mode, the internal clock control <NUM> arranges the select signal on the signal connection <NUM> to facilitate the multiplexer <NUM> to select the calibrated reference clock on the signal connection <NUM>. The calibrated delay circuit <NUM> outputs the calibrated reference clock onto the signal connection <NUM>, based on a setting provided on the signal connection <NUM>.

The internal clock control <NUM> stores the setting obtained from a previous training mode and/or operation. The setting is such that the calibrated reference clock on the signal connection <NUM> (and therefore, the internal clock on the signal connection <NUM>) would be in phase and/or frequency synchronization with the data clock RDQS. Further in the low-speed mode, the enable circuit <NUM> enables the internal clock onto the signal connection <NUM>, based on an output of the multiplexer <NUM> on the signal connection <NUM>. In such fashion, in the low-power mode, the internal clock is generated independent of the data clock RDQS. For example, the data clock RDQS is not an input (e.g., not selected by the multiplexer <NUM>) in generating the internal clock on the signal connection <NUM> used to receive data on the DQs.

At <NUM>, data are received by the host based on the second clock from the memory in a second mode of the read operation. For example, referring to <FIG>, data on DQs are received by the host <NUM> from the memory <NUM>. Referring to <FIG>, data on the DQs are received by the input circuit 206_2 based on clocking on the signal connection <NUM>, in a low-speed mode of the read mode and/or operation.

At <NUM>, the memory is instructed by the host to disable outputting the first clock to communicate in the second mode of the read operation. For example, referring to <FIG>, the host <NUM> instructs the memory <NUM> to off the data clock RDQS by accessing (reading or writing) the mode register <NUM> (e.g., the RDQS mode register <NUM>) via the link <NUM> and the memory I/O module <NUM>. Consequently, the memory <NUM> outputs read data without outputting the data clock RDQS (e.g., in a low-speed mode or the second mode of the read mode and/or operation), in response to a mode or setting of the RDQS mode register <NUM>. In such fashion, power to toggle the data clock RDQS is conserved.

At <NUM>, a generation of the second clock is adjusted by the host based on the first clock in a training mode. At <NUM>, the second clock is synchronized with the first clock in the generation of the second clock. For example, referring to <FIG>, in a training mode and/or operation, the memory <NUM> outputs the data clock RDQS to allow the host <NUM> to calibrate internal settings in a generation of the internal clock to receive data (e.g., DQs) from the memory <NUM>. For example, the host <NUM> adjusts, in the training mode and/or operation, the generation of the internal clock based on the data clock RDQS. The internal clock control <NUM> outputs the select signal on the signal connection <NUM> such that the multiplexer <NUM> selects the received data clock RDQS on the signal connection <NUM> and outputs to the phase detector <NUM> on the signal connection <NUM>. The phase detector <NUM> detects a phase difference between the received data clock RDQS outputted by the multiplexer <NUM> and the calibrated reference clock on the signal connection <NUM> (from the calibrated delay circuit <NUM>). The phase detector <NUM> outputs the phase difference, via the signal connection <NUM>, to the internal clock control <NUM>.

In response to the phase difference on the signal connection <NUM>, the internal clock control <NUM> adjusts a setting of the calibrated delay circuit <NUM> via the signal connection <NUM>. In a subsequent cycle in the training mode and/or operation, the calibrated delay circuit <NUM> adjusts the reference clock received on the signal connection <NUM>, based on the setting on the signal connection <NUM>, and outputs the calibrated reference clock to the multiplexer <NUM> and to the phase detector <NUM> (via the signal connection <NUM>). In such fashion, the setting of the calibrated delay circuit <NUM> is adjusted such that the outputted calibrated reference clock is in phase and/or frequency synchronization with the received data clock RDQS. Such setting is be stored (e.g., by the internal clock control <NUM>) to generate the internal clock (e.g., the second clock), via the enable circuit <NUM>, in a read mode and/or operation subsequent to the training mode and/or operation. In such fashion, the host <NUM> synchronizes the internal clock (e.g., the second clock) with the data clock RDQS (e.g., the first clock) to adjust the generation of the internal clock.

At <NUM>, among the host receiving data based on the first clock and receiving data based on the second clock generated independent of the first clock is selected by a multiplexer of the host. For example, referring to <FIG>, the multiplexer <NUM> selects among the host <NUM> receiving data based on the data clock RDQS and receiving data based on the internal clock not generated from the data clock RDQS. For example, in the high-speed mode, the internal clock control <NUM> arranges the select signal on the signal connection <NUM> to facilitate the multiplexer <NUM> to select the received data clock on the signal connection <NUM>. The input circuit 206_2 receives data on DQs based on (e.g., clocked by) the selected received data clock RDQS (via the signal connection <NUM>, the enable circuit <NUM>, the signal connection <NUM>). In the low-speed mode, the internal clock control <NUM> arranges the select signal on the signal connection <NUM> to facilitate the multiplexer <NUM> to select the calibrated reference clock on the signal connection <NUM>. The calibrated delay circuit <NUM> outputs the calibrated reference clock onto the signal connection <NUM>, based on a setting provided on the signal connection <NUM>.

At <NUM>, generating the second clock in the second mode is enabled and generating the second clock in the first mode of the read operation is disabled by an enable circuit of the host, based on an enable signal. Referring to <FIG>, for example, the clock source <NUM> provides a reference clock on a signal connection <NUM> to an enable circuit <NUM>. The enable circuit <NUM> enables generating the second clock in the low-speed or second mode and to disable generating the second clock in the high-speed or first mode of the read mode and/or operation, based on an enable signal on the signal connection <NUM>. For example, in the low-speed mode, the enable circuit <NUM> provides the reference clock onto the signal connection <NUM> and to provide the reference clock to the calibrated delay circuit <NUM>.

The calibrated delay circuit <NUM> outputs a calibrated reference clock, based on a setting provided on the signal connection <NUM>, onto the signal connection <NUM>. Based on the training mode, the internal clock control <NUM> provides the setting on the signal connection <NUM> such that the calibrated reference clock on the signal connection <NUM> correspond to a version of the internal clock. For example, the calibrated reference clock or the version of the internal clock outputted by the calibrated delay circuit <NUM> onto the signal connection <NUM> is in phase and/or frequency synchronization of the data clock RDQS in the slow-speed mode. The data clock RDQS in the slow-speed mode might not be outputted by the memory <NUM> or received by the host <NUM>, in some examples. In the high-speed mode, the enable circuit <NUM> disables generating the internal clock at an input of the multiplexer <NUM> (e.g., on the signal connection <NUM>). For example, the enable circuit <NUM> provides the reference clock onto the signal connection <NUM> and to the calibrated delay circuit <NUM>. In such fashion, since the internal clock is not used on the high-speed mode of the read mode and/or operation, power to generate the internal clock would be saved.

Claim 1:
An apparatus, comprising:
a host (<NUM>) configured to communicate with a memory (<NUM>) via a link (<NUM>), the host being further configured to:
receive a first clock (RDQS) from the memory,
receive, based on the first clock, data (DQs) from the memory synchronously, in a high-speed mode of a read operation,
generate a second clock, the second clock being generated independent of the first clock in a low-speed mode of the read operation and being an internal clock of the host, wherein no read clock is between the host and the memory in the low-speed mode, and
receive, based on the second clock, data (DQs) from the memory synchronously, in the low-speed mode of the read operation.