Patent Description:
Split-gate type memory cell arrays are known. For example, <CIT>, which is incorporated herein by reference for all purposes, discloses a split gate memory cell and its formation, which includes forming source and drain regions in the substrate with a channel region there between. A floating gate is disposed over and controls the conductivity of one portion of the channel region, and a control gate is disposed over and controls the conductivity of the other portion of the channel region. The control gate extends up and over the floating gate. The insulation between the floating gate and the control gate is referred to as the tunnel dielectric material (e.g. silicon dioxide, also referred to as oxide), because electrons tunnel through this dielectric material during an erase operation.

<CIT> discloses that a method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.

It is also known to form high voltage logic devices on the same wafer (substrate) as the split-gate memory cell array. <FIG> show the steps in forming high voltage logic devices (e.g. <NUM> volt logic devices) on the same wafer as the split gate memory cells according to a conventional method. A silicon semiconductor substrate <NUM> having an upper surface 10a, a memory cell region <NUM> and a logic region <NUM>. Semiconductor substrate <NUM> is masked, i.e. photo resist is deposited, selectively exposed using a mask, and patterned (i.e., portions selectively removed) using a photolithographic process, leaving portions of the underlying material covered by remaining photo resist while leaving other portions of the underlying material (here the silicon semiconductor substrate <NUM>, particularly upper surface 10a) exposed. The exposed substrate portions are etched away leaving trenches that are then filled with dielectric material (e.g. oxide) to form isolation regions <NUM> in the logic region <NUM> of the wafer, as shown in <FIG> (after photoresist removal). Isolation regions <NUM> are similarly formed in memory cell region <NUM> of the wafer (not shown), defining alternating columns of active regions <NUM> and isolation regions <NUM>.

A dielectric material (e.g. silicon dioxide, hereinafter referred to as oxide) <NUM> is formed on the substrate <NUM>, a layer of polysilicon (hereinafter referred to as poly) <NUM> is formed on oxide layer <NUM>, and a layer of silicon nitride (hereinafter referred to as nitride) <NUM> is formed on poly layer <NUM>, as shown in <FIG>. The wafer is masked with photoresist, and the nitride layer <NUM> selectively etched through openings in the photoresist in the memory cell region <NUM>, to expose portions of the underlying poly layer <NUM>. The exposed portions of the poly layer <NUM> are oxidized using an oxidation process, forming oxide areas <NUM> on the poly layer <NUM>, as shown in <FIG> (after photoresist removal).

A nitride etch is used to remove the remaining nitride layer <NUM>. An anisotropic poly etch is used to remove exposed portions of the poly layer <NUM>, leaving blocks 20a of poly layer <NUM> underneath the oxide areas <NUM> in the memory cell region <NUM> (poly blocks 20a will constitute the floating gates of the memory cells), as shown in <FIG>. An oxide etch is used to remove the exposed portions of oxide layer <NUM> (i.e., those portions not under the remaining portion of poly layer <NUM>). An oxide layer <NUM> is then formed over the structure either by deposition (which also thickens oxide areas <NUM>) and/or by oxidation (which has no effect on oxide areas <NUM>), as shown in <FIG>. A poly layer is then formed on the structure (i.e., on oxide layer <NUM> and oxide areas <NUM>). The poly layer is then patterned by forming and patterning photoresist on the poly layer leaving portions of the poly layer exposed. The exposed portions of the poly layer are selectively removed by a poly etch, leaving poly blocks 28a in the memory cell region and poly blocks 28b in the logic region, as shown in <FIG> (after photoresist removal). Insulation spacers <NUM> are formed on the sides of poly blocks 28a and 28b by insulation material deposition and anisotropic etch, and implantations are performed to form source regions <NUM> and drain regions <NUM> in the memory cell region <NUM>, and source regions <NUM> and drain regions <NUM> in the logic region <NUM>, of substrate <NUM>. The final structure is shown in <FIG>.

The above technique produces non-volatile memory cells (each with a floating gate 20a formed from the remaining portion of poly layer <NUM>, a control gate in the form of poly block 28a, a source region <NUM> adjacent to (and also preferably extending partially under) an end of the floating gate 20a, and a drain region <NUM> adjacent an end of the control gate 28a) on the same substrate <NUM> as high voltage logic devices (each with a logic gate in the form of poly block 28b, source region <NUM> and drain region <NUM> adjacent first and second ends of the logic gate 28b). There are many advantages of this technique. First, the same poly layer is used to form both control gates 28a of the memory cells and the logic gates 28b of the logic devices, using a single poly deposition. Second, the same oxide layer <NUM> is used as the gate oxide for the logic devices (i.e., the oxide layer used to insulate the logic gates 28b from the substrate <NUM>), the word line oxide for the memory cells (i.e., the oxide layer used to insulate the control gates 28a from the substrate <NUM>), and the tunnel oxide for the memory cells (i.e., the oxide insulating the floating gate 20a from the control gate 28a through which electrons tunnel in the erase operation). Common manufacturing steps for forming elements in both the memory cell region <NUM> and the logic region <NUM> simplifies, expedites and lower the costs of manufacturing. Forming oxide areas <NUM>, as described in relation to <FIG>, by oxidation results in the floating gates 20a having a concave upper surface that terminates in a sharp edge <NUM> facing the control gate 28a, which enhances tunneling performance and efficiency during erase (i.e., the erase operation includes placing a high voltage on the control gate 28a to cause electrons to tunnel from the sharp edge <NUM> of the floating gate 20a, through oxide layer <NUM>, to the control gate 28a). The control gate 28a has a lower portion vertically over and insulated from the substrate <NUM> for controlling the conductivity of the channel region therein, and a second portion that extends up and over the floating gate 20a for voltage coupling and proximity to the floating gate sharp edge <NUM> for erasure.

One drawback of the above described technique is that the thickness of oxide layer <NUM> must be compatible for both the logic devices and the memory cells. Specifically, the oxide layer <NUM> must be thick enough for the high voltage operation of the logic gates 28b and control gates 28a, while being thin enough to allow tunneling from the floating gate 20a to the control gate 28a during the erase operation. Therefore, balancing these considerations, there is a lower limit to the thickness of oxide layer <NUM> driven by the high voltage operation of the control gates 28a and logic gates 28b, which means the portion of layer <NUM> through which tunneling occurs during erase operations of the memory cells (i.e. the portion of layer <NUM> between the control gate 28a and floating gate 20a) is unnecessarily thick and therefore limits erase performance and efficiency, and limits endurance performance. However, forming the tunnel oxide (between the control gate 28a and floating gate 20a) separately from the word line oxide (between the control gate 28a and the substrate <NUM>) and the logic gate oxide (between the logic gate 28b and the substrate <NUM>) can significantly increase manufacturing complexity, time and costs, as well as risk the integrity of the previously formed word line oxide and logic gate oxide thus lowering yield.

It would be desirable to increase memory cell erase efficiency between the floating gate and the control gate, without adversely affecting the performance of the control gate as a word line or of the logic gate in the logic device, where the same oxide layer is used in all three places.

The aforementioned problems and needs are addressed by providing a memory device that includes a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region, a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges, an oxide layer having a first portion that extends along the logic region of the substrate upper surface and has a first thickness a second portion that extends along the memory cell region of the substrate upper surface and has the first thickness and a third portion that extends along the front and back edges and along the first and second side edges, wherein the third portion of the oxide layer extending along the front edge has the first thickness and wherein the third portion of the oxide layer extending along a tunnel region portion of the first side edge has a second thickness less than the first thickness, a control gate having a first portion disposed on the second portion of the oxide layer and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge, and a logic gate on the first portion of the oxide layer. The first portion of the oxide layer insulates the substrate from the logic gate, the second portion of the oxide layer insulates the substrate from the control gate first portion, and the third portion of the oxide layer along the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge.

A method of forming a memory device includes providing a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region, forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges, forming an oxide layer having a first portion that extends along the logic region of the substrate upper surface and a second portion that extends along the memory cell region of the substrate upper surface and a third portion that extends along the front and back edges and along the first and second side edges, performing an oxide etch that reduces a thickness of the third portion of the oxide layer along a tunnel region portion of the first side edge wherein the first and second portions of the oxide layer and the third portion of the oxide layer along the front edge of the floating gate are protected from the oxide etch, forming a control gate having a first portion disposed on the second portion of the oxide layer and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge, and forming a logic gate on the first portion of the oxide layer. The first portion of the oxide layer insulates the substrate from the logic gate and has a first thickness, the second portion of the oxide layer insulates the substrate from the control gate first portion and has the first thickness, and the third portion of the oxide layer along the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge and has a second thickness less than the first thickness.

A memory device includes a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region, a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges, a first oxide layer having a first portion that extends along the logic region of the substrate upper surface and has a first thickness and a second portion that extends along the memory cell region of the substrate upper surface and has the first thickness and a third portion that extends along the front edge and has the first thickness, a second oxide layer extending along a tunnel region portion of the first side edge and has a second thickness less than the first thickness, a control gate having a first portion disposed on the second portion of the oxide layer and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge, and a logic gate on the first portion of the oxide layer. The first portion of the first oxide layer insulates the substrate from the logic gate, the second portion of the first oxide layer insulates the substrate from the control gate first portion, and the second oxide layer along the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge.

A method of forming a memory device includes providing a substrate of semiconductor material with a substrate upper surface having a memory cell region and a logic region, forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges, forming a first oxide layer having a first portion that extends along the logic region of the substrate upper surface and a second portion that extends along the memory cell region of the substrate upper surface and a third portion that extends along the front and back edges and along the first and second side edges, performing an oxide etch that removes the third portion of the first oxide layer along a tunnel region portion of the first side edge wherein the first and second portions of the first oxide layer and the third portion of the first oxide layer along the front edge of the floating gate are protected from the oxide etch, forming a second oxide layer along the tunnel region portion of the first side edge, forming a control gate having a first portion disposed on the second portion of the first oxide layer and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge, and forming a logic gate on the first portion of the first oxide layer. The first portion of the first oxide layer insulates the substrate from the logic gate and has a first thickness, the second portion of the first oxide layer insulates the substrate from the control gate first portion and has the first thickness, and the second oxide layer along the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge and has a second thickness less than the first thickness.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

The present invention is a technique of forming memory cells and logic devices on a common substrate, where a portion of the oxide layer used as a tunnel oxide is selectively thinned.

<FIG> and <FIG> disclose steps of an embodiment of the method of the present invention. The process begins using the same steps described above with respect to <FIG>, resulting in the structure shown in the cross sectional view of the memory cell region <NUM> and logic device region <NUM> in <FIG>, and shown in the top view of the memory cell region <NUM> in <FIG>. At this stage of processing, there are alternating columns of active regions <NUM> and isolation regions <NUM> in the memory cell region <NUM>, with pairs of floating gates 20a formed in each active region column <NUM>. Each floating gate 20a has a concave upper surface terminating in sharp edges <NUM>, <NUM> and <NUM> at the perimeter of the upper surface of the floating gate 20a. Each floating gate 20a partially overlap the respective isolation region <NUM> to provide margin for any misalignment. Specifically, for each pair of floating gates 20a, sharp edges <NUM> are the two edges of the two floating gates 20a that face away from each other (also referred to as front edges <NUM>), sharp edges <NUM> are the two edges of the two floating gates 20a that face toward each other (also referred to as back edges <NUM>), and sharp edges <NUM> are the two edges of each floating gate 20a extending between sharp edges <NUM> and <NUM> and are disposed over the isolation regions <NUM> (also referred to as side edges <NUM>). Thus, for each floating gate 20a, front and back edges <NUM> and <NUM> oppose each other, and the two side edges <NUM> oppose each other (also referred to as first and second side edges <NUM>). Floating gates 20a are shown and described herein as rectangular, but they need not be rectangular in shape. Source line diffusion areas <NUM> each extend in the row direction and between the pairs of the floating gates 20a (for connecting together a row of the source regions formed later in the process). Oxide layer <NUM> can be considered to have three portions: a first portion 26a that extends along the logic region <NUM> of the substrate upper surface 10a, a second portion 26b that extends along the memory cell region <NUM> of the substrate upper surface 10a, and a third portion 26c that extends along the sides and sharp edges <NUM>, <NUM>, <NUM> of the floating gates 20a.

Photoresist <NUM> is formed over the structure and patterned to remove portions of the photoresist <NUM>, such that the remaining photoresist <NUM> covers the logic device region <NUM>, but only portions of the memory cell region <NUM>. Specifically, photoresist <NUM> covers front edges <NUM> and only a portion of each side edge <NUM>. However, left uncovered by photoresist <NUM> are back edges <NUM> and a portion of each side edge <NUM>, including the portions of oxide layer 26c thereon, as shown in <FIG> and <FIG>.

An oxide etch (e.g., wet or dry etch) is then performed on the exposed portions of oxide layer 26c and oxide <NUM>, which reduces the thickness of layer portion 26c on portions of the side edges <NUM> and on back edges <NUM> (which are not subjected to high voltage operation), as shown in <FIG>. The photoresist <NUM> protects oxide layer portion 26a in the logic device region <NUM>, as well as the oxide layer portions 26b on the substrate surface that are adjacent front edges <NUM> (on which the control gates will eventually be formed) and the other portions of oxide layer 26c.

After photoresist <NUM> is removed, a poly layer deposition and patterning as described above with respect to <FIG> is performed to form the control gates formed from poly blocks 28a and logic gates formed from poly blocks 28b, as shown in <FIG> and <FIG>. Control gates 28a in each row are formed as a continuous word line WL. Each control gate 28a extends up and over a respective front edge <NUM>, and over a portion of each respective side edge <NUM>, including a tunnel region portion TR of each side edge <NUM> for which layer portion 26c was thinned by the oxide etch shown in <FIG> and is now vertically covered by control gate 28a. Specifically, the tunnel region portion TR is that portion of each side edge <NUM> which was subjected to oxide layer 26a thinning and which is later vertically covered by control gate 28a. The remaining steps described above with respect to <FIG> are performed to result in the final structure shown in <FIG>. Preferably a single implantation is used to simultaneously form the drain regions <NUM> in the memory cell region <NUM>, and source regions <NUM> and drain regions <NUM> in the logic region <NUM>, as shown in <FIG>.

The resulting structure has logic gates 28b and control gates 28a insulated from the substrate <NUM> by portions of the oxide layer <NUM> (i.e., oxide portions 26a and 26b) having a first thickness, and the control gates 28a are insulated from the tunnel region portion TR of the side edges <NUM> by the thinned portions of oxide 26c having a second thickness that is less than the first thickness. This structure enhances the erase efficiency and performance of the memory cell by enhancing tunneling efficiency between the control gate 28a and the tunnel region portions TR of the side edges <NUM>, without compromising the performance of the logic devices or adversely affecting the ability of the control gates 28a to control the conductivity of the channel region portion of the substrate underneath the control gates 28a. Specifically, the above described technique thins the oxide layer 26c on the tunnel region portions TR of the side edges <NUM> without risk of compromising the oxide layer portions 26a and 26b on which the logic gates 28b and control gate 28a are formed and which insulate them from the substrate <NUM>.

<FIG> illustrates an alternate embodiment, which is the same as the embodiment shown in <FIG>, except notches <NUM> are formed in the word lines WL at center portions of the floating gate 20a resulting in protruding tabs <NUM> of the control gates 28a extending out further over the side edges <NUM> than over the center of the floating gate 20a (i.e., each control gate 28a extends deeper over portions of side edges <NUM> than over a center portion of the floating gate 20a relative to front edge <NUM>, such that the control gate 28a does not extend vertically over a portion of the floating gate 20a located between the tunnel region portion TR of the first side edge <NUM> and the tunnel region portion TR of the second side edge <NUM>). Notch <NUM> reduces the amount of overlap between the control gate 28a and floating gate 20a (in the center area of the floating gate 20a that does not contribute to erasure), thus reducing capacitive coupling between control gate 28a and floating gate 20a which in turn can further enhance erase efficiency.

<FIG> illustrates another alternate embodiment, which is the same as the embodiment shown in <FIG>, except that for each row of floating gates 20a, alternate tabs <NUM> are omitted, so that each control gate 28a extends over just one tunnel region portion TR of one side edge for each underlying floating gate 20a. The pattern of tabs <NUM> can alternate row by row, so tabs <NUM> in even numbered rows of floating gates 20a are disposed over different isolation regions <NUM> than tabs <NUM> in odd numbered rows of the floating gates 20a, as shown in <FIG>.

<FIG> illustrate yet another alternate embodiment, which starts with the structure shown in <FIG>. However, unlike the results of the oxide etch shown in <FIG> where the exposed portions of oxide layer 26c are maintained but reduced in thickness, the oxide etch is performed to entirely remove the exposed oxide (i.e., a wet or dry oxide etch is performed on the exposed portions of oxide layer 26c and oxide <NUM>, which removes the oxide layer portions 26c on the side edges <NUM> and on back edges <NUM> and removes exposed portions of oxide <NUM>), as shown in <FIG>. The photoresist <NUM> protects oxide layer portion 26a in the logic device region <NUM>, as well as the oxide layer portions 26b on the substrate surface that are adjacent front edges <NUM> (on which the control gates will eventually be formed) and the other portions of oxide layer 26c protected by photoresist <NUM>.

A layer of oxide <NUM> is then formed on the exposed portions of floating gates 20a and substrate <NUM> (e.g., by thermal oxidation), as shown in <FIG>. The thickness of layer <NUM> can be optimized for a tunnel oxide and is less than the thickness of the remaining oxide layer portions 26a, 26b and 26c. Formation of oxide <NUM> can be performed simultaneously in the logic device region <NUM> for forming logic devices suitable for low voltage operation. After photoresist <NUM> removed, the structure is processed as described above with respect to <FIG> to form the logic gates 28b and control gates 28a, as shown in <FIG>. This structure is then processed as described above with respect to <FIG> to form the various source and drain regions, as shown in <FIG>. This embodiment can be utilized to form any of the configurations in <FIG>, <FIG> and <FIG>. The advantage of this embodiment is that the thickness of oxide layer <NUM> may be better controlled relative to the thickness of thinned portions of oxide layer 26c.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed.

Claim 1:
A memory device, comprising:
a substrate of semiconductor material (<NUM>) with a substrate upper surface (10a) having a memory cell region (<NUM>) and a logic region (<NUM>);
a floating gate (20a) disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in opposing front and back edges and in opposing first and second side edges;
an oxide layer (<NUM>) having a first portion that extends on the logic region of the substrate upper surface and has a first thickness, a second portion that extends on the memory cell region of the substrate upper surface and has the first thickness, and a third portion that extends on the front and back edges and on the first and second side edges;
wherein the third portion of the oxide layer extending on the front edge has the first thickness, and wherein the third portion of the oxide layer extending on a tunnel region portion (TR) of the first side edge has a second thickness less than the first thickness;
a control gate (28a) having a first portion disposed on the second portion of the oxide layer, and having a second portion disposed vertically over the front edge and vertically over the tunnel region portion of the first side edge; and
a logic gate (28b) on the first portion of the oxide layer;
wherein the first portion of the oxide layer insulates the substrate from the logic gate, the second portion of the oxide layer insulates the substrate from the control gate first portion, and the third portion of the oxide layer on the tunnel region portion of the first side edge insulates the control gate second portion from the tunnel region portion of the first side edge, the lesser thickness of the third portion of the oxide layer on the tunnel region portion of the first side edge enhancing the tunneling efficiency between the second portion of the control gate and the tunnel region portion of the first side edge.