Patent Description:
The embodiments of the disclosure relate to the technical field of semiconductors, in particular, to a data receiving circuit, a data receiving system and a storage device.

In memory applications, as the speed of signal transmission becomes increasingly faster, the channel loss has increasingly greater influence on the signal quality, which will easily lead to inter-symbol interference (ISI). At present, an equalization circuit is usually used for compensating the channel, and a Continuous Time Linear Equalizer (CTLE) or Decision Feedback Equalizer (DFE) can be selected as the equalization circuit.

However, although the addition of the equalization circuit can compensate the signal, the addition of the equalization circuit in a data receiving circuit will increase the overall power consumption of the data receiving circuit. Background may be found in <CIT> and <CIT>.

<CIT> discloses a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

<CIT> discloses a data receiver in a memory device including an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal.

One or more embodiments are exemplarily illustrated by the corresponding drawings. These exemplary descriptions do not limit the embodiments. Unless otherwise stated, the pictures in the drawings do not limit the scale. In order to describe the technical solutions of the embodiments of the present disclosure more clearly, drawings required to be used in the embodiments of the present disclosure will be briefly introduced below. Apparently, the drawings described below are only some embodiments of the present disclosure. Those of ordinary skill in the art also can obtain other drawings according to these drawings without doing creative work.

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system and a storage device. In the data receiving circuit, the decision feedback control module and the decision feedback equalization module are integrated into the data receiving circuit, and the decision feedback control module is used to generate a second sampling clock signal for controlling the decision feedback equalization module, so as to flexibly control whether the decision feedback equalization module is to be in an operating state. For example, when it is necessary to reduce the influence of ISI on the data receiving circuit, i.e., when the enable signal is in the first level value interval, the decision feedback equalization module is controlled to perform the decision feedback equalization based on the second sampling clock signal outputted by the decision feedback control module, so as to improve the reception performance of the data receiving circuit; and when the influence of ISI on data receiving circuit is not required to be considered, i.e., when the enable signal is in the second level value interval, the decision feedback equalization module is controlled to stop based on the second sampling clock signal outputted by the decision feedback control module, performing the decision feedback equalization, so as to reduce the overall power consumption of the data receiving circuit. In this way, it is possible to facilitate improving the reception performance of the data receiving circuit and simultaneously reducing the overall power consumption of the data receiving circuit.

Embodiments of the present disclosure will now be described in detail in conjunction with the accompanying drawings. However, those of ordinary skill in the art will appreciate that, in various embodiments of the present disclosure, many technical details have been proposed to better enable the reader to understand the present disclosure. However, the technical solution claimed in the present disclosure can be implemented without these technical details and various changes and modifications based on the following embodiments.

An embodiment of the present disclosure provides a data receiving circuit, and the data receiving circuit provided by the embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. <FIG> is a functional block diagram of a data receiving circuit provided by an embodiment of the present disclosure. <FIG> are other two functional block diagrams of a data receiving circuit provided by embodiments of the present disclosure. <FIG> is a schematic structural diagram of a data receiving circuit provided by an embodiment of the present disclosure. <FIG> are schematic structural diagram of a first decision feedback unit in a data receiving circuit provided by an embodiment of the present disclosure. <FIG> is another schematic structural diagram of a data receiving circuit provided by an embodiment of the present disclosure.

With reference to <FIG>, a data receiving circuit <NUM> includes a first amplification module <NUM>, a decision feedback control module <NUM>, a decision feedback equalization module <NUM> and a second amplification module <NUM>. The first amplification module <NUM> is configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a first sampling clock signal CLK1, and output a first voltage signal and a second voltage signal respectively through a first node n_stg1 and a second node p_stg1. The decision feedback control module <NUM> is configured to generate a second sampling clock signal CLK2 in response to an enable signal DfeEn. The decision feedback equalization module <NUM> is connected to the first node n_stg1 and the second node p_stg1, and configured to, when the enable signal DfeEn is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal CLK2 and based on a feedback signal fb to adjust the first voltage signal and the second voltage signal, and stops performing the decision feedback equalization when the enable signal DfeEn is in a second level value interval. The feedback signal is obtained based on previously received. The second amplification module <NUM> is configured to amplify a voltage difference between the first voltage signal and the second voltage signal, and to output a first output signal Vout and a second output signal VoutN respectively through a third node net3 (with reference to <FIG>) and a fourth node net4 (with reference to <FIG>).

It should be noted that the data receiving circuit <NUM> adopts two stages of amplification modules, e.g., the first amplification module <NUM> and the second amplification module <NUM>, to process the data signal DQ and the reference signal Vref. In this way, it is possible to facilitate enhancing the amplification capability of the data receiving circuit <NUM>, and increasing the voltage amplitudes of the first output signal Vout and the second output signal VoutN, so as to facilitate the processing of subsequent circuits.

In addition, the decision feedback control module <NUM> is used to generate a second sampling clock signal CLK2 for controlling the decision feedback equalization module <NUM>, so as to flexibly control whether the decision feedback equalization module <NUM> is to be in the operating state. For example, when it is necessary to reduce the influence of ISI on the data receiving circuit <NUM>, i.e., when the enable signal DfeEn is in the first level value interval, the decision feedback control module <NUM> generates the second sampling clock signal CLK2 in response to the enable signal DfeEn at this time, and the decision feedback equalization module <NUM> performs decision feedback equalization based on the second sampling clock signal CLK2, so as to improve the reception performance of the data receiving circuit <NUM>. When the influence of the ISI on the data receiving circuit <NUM> is not required to be considered, i.e., when the enable signal DfeEn is in the second level value interval, the decision feedback equalization module <NUM> stops, based on the second sampling clock signal CLK2 at this time, performing the decision feedback equalization, so as to reduce the overall power consumption of the data receiving circuit <NUM>. In this way, it is possible to facilitate improving the reception performance of the data receiving circuit <NUM> and simultaneously reducing the overall power consumption of the data receiving circuit <NUM>.

The integration of the decision feedback equalization module <NUM> into the data receiving circuit <NUM> facilitates the adjustment of the signal outputted by the data receiving circuit <NUM> by using a smaller circuit layout area and a lower power consumption. Furthermore, adjustment capability, for adjusting the first output signal Vout and the second output signal VoutN, of the decision feedback equalization module <NUM> provided in the embodiment of the present disclosure is adjustable, it can be appreciated that, When the data signal DQ and/or the reference signal Vref received by the data receiving circuit <NUM> change, the ability for adjusting the first output signal Vout and the second output signal VoutN by the decision feedback equalization module 103can be flexibly controlled, so as to reduce the influence of the ISI of the data received by the data receiving circuit <NUM> on the data receiving circuit <NUM>, improve the reception performance of the data receiving circuit <NUM>, and reduce the influence of the ISI of the data on the accuracy of the signal outputted by the data receiving circuit <NUM>.

In some embodiments, with reference to <FIG> the first amplification module <NUM> may include a first current source <NUM> configured to be connected between the power supply node Vcc (with reference to <FIG>) and the fifth node net5 to supply current to the fifth node net5 in response to the first sampling clock signal CLK1; a comparison unit <NUM>, connected the fifth node net5, the first node n_stg1 and the second node p_stg1, is the comparison unit <NUM> is configured to receive the data signal DQ and the reference signal Vref, compare the data signal DQ and the reference signal Vref when the first current source <NUM> supplies the current to the fifth node net5 in response to the first sampling clock signal CLK1, output the first voltage signal through the first node n_stg1 and output the second voltage signal through the second node p_stg1.

It can be appreciated that the comparison unit <NUM> may control the difference between the current supplied to the first node n_stg1 and the current supplied to the second node p_stg1 based on the difference between the data signal DQ and the reference signal Vref to output the first voltage signal and the second voltage signal.

The first amplification module <NUM> is described in detail below with reference to <FIG> and <FIG>.

In some embodiments, with reference to <FIG> and <FIG>, the first current source <NUM> may include a first PMOS transistor MP1 connected between the power supply node Vcc and the fifth node net5, and having a gate configured to receive the first sampling clock signal CLK1. When the first sampling clock signal CLK1 is at a low level, the gate of the first PMOS transistor MP1 receives the first sampling clock signal CLK1 to be turned on, the current is supplied to the fifth node net5, so that the comparison unit <NUM> is in an operating state, and compares the received data signal DQ with the reference signal Vref.

In some embodiments, with continued reference to <FIG> and <FIG>, the comparison unit <NUM> may include a third PMOS transistor MP3 connected between the fifth node net5 and the first node n_stg1 and having a gate configured to receive the data signal DQ; and a fourth PMOS transistor MP4 connected between the fifth node net5 and the second node p_stg1 and having a gate configured to receive a reference signal Vref.

It should be noted that the level changes of the data signal DQ and the reference signal Vref are not synchronized, so that the time when the third PMOS transistor MP3 configured to receive the data signal DQ is turned on is different from the time when the fourth PMOS transistor MP4 configured to receive the reference signal Vref is turned on, and at the same time, the extent to which the third PMOS transistor MP3 is turned on is different from the extent to which the fourth PMOS transistor MP4 is turned on. It can be appreciated that, based on the fact that the extent of turning on of the third PMOS transistor MP3 is different from that of the fourth PMOS transistor MP4, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 have different shunt capabilities for the current at the fifth node net5, such that the voltage at the first node n_stg1 is different from the voltage at the second node p_stg1.

In one example, when the level value of the data signal DQ is lower than the level value of the reference signal Vref, the extent of turning on of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4, and the current at the fifth node net5 flow more into the path where the third PMOS transistor MP3 is located, so that the current at the first node n_stg1 is greater than the current at the second node p_stg1, thereby further making the level value of the first voltage signal outputted by the first node n_stg1 to be high and the level value of the second voltage signal outputted by the second node p_stg1 to be low.

In some embodiments, with reference to <FIG>, the first amplification module <NUM> may further include a first reset unit <NUM> connected to the first node n_stg1 and the second node p_stg1 and configured to reset the first node n_stg1 and the second node p_stg1. In this way, after the data receiving circuit completes the reception of the data signal DQ and the reference signal Vref and the output of the first output signal Vout and the second output signal VoutN once, the level values at the first node n_stg1 and the second node p_stg1 can be restored to the initial values by the first reset unit <NUM> so as to facilitate the next data reception and subsequent processing by the data receiving circuit.

In some embodiments, with reference to <FIG> and <FIG>, the first reset unit <NUM> may include a first NMOS transistor MN1 connected between the first node n_stg1 and the ground terminal and having a gate configured to receive the first sampling clock signal CLK1; a second NMOS transistor MN2 connected between the second node p_stg1 and the ground terminal and having a gate configured to receive a first sampling clock signal CLK1.

In one example, when the first sampling clock signal CLK1 is at a low level, the first PMOS transistor MP1 is turned on, and the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off to ensure the normal operation of the data receiving circuit, moreover, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be used as loads of the first amplification module <NUM> to increase the amplification gain of the first amplification module <NUM>. When the first sampling clock signal CLK1 is at a high level, the first PMOS transistor MP1 is turned off, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, and the voltage at the first node n_stg1 and the voltage at the second node p_stg1 are pulled down to implement the reset of the first node n_stg1 and the second node p_stg1.

In some embodiments, with reference to <FIG>, the feedback signal fb includes a first feedback signal fbn and a second feedback signal fbp that are differential signals to each other. The decision feedback equalization module <NUM> may include a second current source <NUM> configured to be connected between the power supply node Vcc (with reference to <FIG>) and the sixth node net6 to supply current to the sixth node net6 in response to the second sampling clock signal CLK2; a first decision feedback unit <NUM> connected the first node n_stg1 and the sixth node net6 and configured to perform decision feedback equalization on the first node n_stg1 based on the first feedback signal fbn to adjust the first voltage signal, when the second current source <NUM> supplies a current to the sixth node net6 in response to the second sampling clock signal CLK2; and a second decision feedback unit <NUM> connected the second node p_stg1 and the sixth node net6 and configured to perform decision feedback equalization on the second node p_stg1 based on the second feedback signal fbp to adjust the second voltage signal when the second current source <NUM> supplies the current to the sixth node net6 in response to the second sampling clock signal CLK2.

It can be appreciated that, the current source in the first amplification module <NUM> is a first current source <NUM>, the current source in the decision feedback equalization module <NUM> is the second current source <NUM>. It can be seen that different current sources are used for respectively supplying currents to the first amplification module <NUM> and the decision feedback equalization module <NUM>, so that the decision feedback equalization module <NUM> has an independent second current source <NUM>, so as to independently control whether the decision feedback equalization module <NUM> is to be in an operating state.

The second sampling clock signal CLK2 is controlled by the enable signal DfeEn, and when the enable signal DfeEn is in the first level value interval, the second current source <NUM> supplies a current to the sixth node net <NUM> in response to the second sampling clock signal CLK2 at this time, so that the first decision feedback unit <NUM> can perform decision feedback equalization on the first node n_stg1 based on the received first feedback signal fbn to adjust the first voltage signal, and at this time, the second decision feedback unit <NUM> can perform decision feedback equalization on the second node p_stg1 based on the received second feedback signal fbp to adjust the second voltage signal. In this way, when the enable signal DfeEn is in the first level value interval, the decision feedback equalization module <NUM> performs decision feedback equalization in response to the second sampling clock signal CLK2 and based on the feedback signal fb, to adjust the first voltage signal and the second voltage signal.

When the enable signal DfeEn is in a second level value interval, the second current source <NUM> is in an off state in response to the second sampling clock signal CLK2 at this time, that is, no current is supplied to the sixth node net <NUM>, and no current passes through either the first decision feedback unit <NUM> or the second decision feedback unit <NUM>, so that the decision feedback equalization module <NUM> stops performing the decision feedback equalization and the overall power consumption of the data receiving circuit <NUM> is reduced.

The first decision feedback unit <NUM> is used for adjusting the current in the third PMOS transistor MP3 to adjust the voltage at the first node n_stg1, which is equivalent to adjusting the data signal DQ, and the second decision feedback unit <NUM> is used for adjusting the current in the fourth PMOS transistor MP4 to adjust the voltage at the second node p_stg1, which is equivalent to adjusting the reference signal Vref.

It should be noted that, the second amplification module <NUM> receives the first voltage signal and the second voltage signal and amplifies the voltage difference between the first voltage signal and the second voltage signal, to output a first output signal Vout and a second output signal VoutN. That is to say, the first output signal Vout and the second output signal VoutN are affected by the first voltage signal and the second voltage signal, and the decision feedback equalization module <NUM> adjusts the first voltage signal and the second voltage signal based on the feedback signal fb, and may further adjust the first output signal Vout and the second output signal VoutN. Furthermore, the adjustment of the first voltage signal and the second voltage signal by the decision feedback equalization module <NUM> will be described in detail with reference to a specific circuit diagram.

In some embodiments, with reference to <FIG> and <FIG>, the second current source <NUM> may include a second PMOS transistor MP2 connected between the power supply node Vcc and the sixth node net6 and having a gate configured to receive the second sampling clock signal CLK2.

In one example, when the enable signal DfeEn is in a first level value interval, the decision feedback control module <NUM> generates a second sampling clock signal CLK2 in response to the enable signal DfeEn, when the second sampling clock signal CLK2 is at a low level, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and is turned on, so as to supply a current to the sixth node net6 and cause the decision feedback equalization module <NUM> to perform decision feedback equalization in response to the second sampling clock signal CLK2 at this time and based on the feedback signal fb to adjust and the second voltage signal. When the enable signal DfeEn is in a second level value interval, the second sampling clock signal CLK2 generated by the decision feedback control module <NUM> in response to the enable signal DfeEn at this time is always high, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and is turned off, then no current is supplied to the sixth node net6, so that the decision feedback equalization module <NUM> stops performing the decision feedback equalization so as to reduce the overall power consumption of the data receiving circuit <NUM>.

In some embodiments, with continued reference to <FIG> and <FIG>, the decision feedback control module <NUM> may include a NAND gate <NUM> having one input terminal configured to receive the fourth sampling clock signal CLK4, another input terminal configured to receive the enable signal DfeEn, and an output terminal configured to output the second sampling clock signal CLK2.

It should be noted that, in one example, the first level value interval of the enable signal DfeEn refers to a level value range that causes the decision feedback control module <NUM> to determine that the enable signal DfeEn is at a logic level <NUM>, i.e., a high level. the second level value interval of the enable signal DfeEn refers to a level value range that causes the decision feedback control module <NUM> to determine that the enable signal DfeEn is at a logic level <NUM>, i.e., a low level.

In one example, when it is necessary to reduce the influence of ISI on the data receiving circuit <NUM>, the enable signal DfeEn is in the first level value interval, i.e., the enable signal DfeEn is at the high level, at this time, a phase of the second sampling clock signal CLK2 outputted by the NAND gate circuit <NUM> is inverse to a phase of the fourth sampling clock signal CLK4; when the second sampling clock signal CLK2 is at the low level, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and the second PMOS transistor is turned on, to supply the current to the sixth node net <NUM>, moreover, the phase of the first sampling clock signal CLK1 is synchronized with the phase of the second sampling clock signal CLK2, and when the first sampling clock signal CLK1 and the second sampling clock signal CLK2 are both at low levels, the decision feedback equalization module <NUM> and the first amplification module <NUM> are both in the operating state, so as to reduce the influence of the ISI on the data receiving circuit <NUM>. When the influence of ISI on the data receiving circuit <NUM> is not required to be considered, the enable signal DfeEn is in the second level value interval, i.e., the enable signal DfeEn is at the low level, at this time, regardless of whether the fourth sampling clock signal CLK4 is at the high level or the low level, the second sampling clock signal CLK2 outputted by the NAND gate circuit <NUM> is at the high level, and the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and is turned off, so that no current is supplied to the sixth node net <NUM>, i.e., the decision feedback equalization module <NUM> is made to be in a non-operating state.

It should be noted that the NAND gate circuit <NUM> includes only one NAND gate as an example in <FIG> and <FIG>. In practical application, the specific structure of the NAND gate circuit <NUM> is not limited, and all circuits capable of implementing the NAND gate logic can be NAND gate circuit <NUM>.

In some embodiments, with reference to <FIG>, any one of the first decision feedback unit <NUM> and the second decision feedback unit <NUM> includes a switching unit <NUM> configured to connect the sixth node net6 and the seventh node net7 in response to the feedback signal fb; and an adjusting unit <NUM> connected between the seventh node net7 and an output node. The output node is one of the first node n_stg1 and the second node p_stg1, and is configured to adjust a magnitude of an equivalent resistance between the seventh node net7 and the output node in response to a control signal. In the first decision feedback unit <NUM>, if the feedback signal is the first feedback signal fbn, and the output node is the first node n_stg1, the switching unit <NUM> responds to the first feedback signal fbn; and in the second decision feedback unit <NUM>, if the feedback signal is the second feedback signal fbp and the output node is the second node p_stg1, the switching unit <NUM> responds to the second feedback signal fbp.

The switching unit <NUM> in the first decision feedback unit <NUM> is turned on or turned off based on the first feedback signal fbn and the switching unit <NUM> in the second decision feedback unit <NUM> is turned on or turned off based on the second feedback signal fbp. Regardless of the first decision feedback unit <NUM> or the second decision feedback unit <NUM>, when the switching unit <NUM> is turned on, the adjusting unit <NUM> is in an operating state to adjust the voltage at the first node n_stg1 or the second node p_stg1.

In some embodiments, with continued reference to <FIG>, the switching unit <NUM> may include a fifth PMOS transistor MP5 connected between the sixth node net6 and the seventh node net7 and having a gate configured to receive the feedback signal fb.

It should be noted that, only the gate of the fifth PMOS transistor MP5 receives the first feedback signal fbn and the output node is the first node n_stg1 as an example in <FIG>. The specific structure of the first decision feedback unit <NUM> is shown in <FIG>, in practical application, the specific structure of the second decision feedback unit <NUM> is similar to the specific structure of the first decision feedback unit <NUM>, except that the gate of the fifth PMOS transistor MP5 in the second decision feedback unit <NUM> receives the second feedback signal fbp, and the output node is the second node p_stg1, which is the same elsewhere.

In one example, if the first feedback signal fbn received by the switching unit <NUM> in the first decision feedback unit <NUM> is at the low level, the fifth PMOS transistor MP5 is turned on and at this time the adjusting unit <NUM> adjusts the voltage at the first node n_stg1 based on the control signal. In another example, if the second feedback signal fbp received by the switching unit <NUM> in the second decision feedback unit <NUM> is at the low level, the fifth PMOS transistor MP5 is turned on and at this time the adjusting unit <NUM> adjusts the voltage at the second node p_stg1 based on the control signal.

In some embodiments, with continued reference to <FIG>, the adjusting unit <NUM> may include multiple transistor groups connected in parallel between the seventh node net7 and the output node. The control terminals of different transistor groups receive different control signals, and different transistor groups have different equivalent resistances. It can be appreciated that, the different equivalent resistances of different transistor groups make the equivalent resistance of the whole adjusting unit <NUM> flexible and controllable, and if the control terminals of different transistor groups receive different control signals, the number of transistor groups in the on state can be selected by the control signals to implement the adjustment of the equivalent resistance of the whole adjusting unit <NUM>, thereby implementing flexible control of the voltage at the first node n_stg1.

In one example, with reference to <FIG>, the adjusting unit <NUM> may include three single MOS transistors connected in parallel between the seventh node net7 and the first node n_stg1, in turn a first MOS transistor M01, a second MOS transistor M02, and a third MOS transistor M03. A gate of the first MOS transistor M01 receives a first control signal DfeTrim <<NUM>>, a gate of the second MOS transistor M02 receives a second control signal DfeTrim <<NUM>>, and a gate of the third MOS transistor M03 receives a third control signal DfeTrim <<NUM>>.

In some embodiments, with reference to <FIG>, the different transistor groups may include at least one of the transistor groups that includes a single MOS transistor; and at least one of the transistor groups that includes at least two MOS transistors connected in series. In this way, it is possible to adjust the equivalent width-to-length ratio of the channel of a transistor group formed by using multiple individual MOS transistors having a same channel width-to-length ratio and connected in series with each other, so as to realize a diversified design of the adjusting unit <NUM>. It can be appreciated that different equivalent channel width-to-length ratios of transistor groups can make the equivalent resistances of the transistor group different.

In one example, the adjusting unit may include first transistor groups, a second transistor group and a third transistor group connected in parallel and between the seventh node and the first node. The first transistor group includes a first MOS transistor having a gate configured to receive a first control signal; the second transistor group includes a second MOS transistor having a gate configured to receive a second control signal; the third transistor group includes a third MOS transistor and a fourth MOS transistor connected in series. The a end of the fourth MOS transistor is connected to the seventh node, a second end of the fourth MOS transistor is connected to a first end of the third MOS transistor, and a second end of the third MOS transistor is connected to the first node. The gate of the third MOS transistor and the gate of the fourth MOS transistor both receive the third control signal.

In another example, with reference to <FIG>, the adjusting unit <NUM> may include, in addition to the first transistor group <NUM>, the second transistor group <NUM>, and the third transistor group <NUM> in the above example, a fourth transistor group <NUM> and a fifth transistor group <NUM> connected in parallel and between the seventh node net7 and the first node n_stg1. The first transistor group <NUM> includes a first MOS transistor M01 having a gate configured to receive a first control signal DfeTrim <<NUM>>. The second transistor group <NUM> includes a second MOS transistor M02 having a gate configured to receive a second control signal DfeTrim <<NUM>>. The third transistor group <NUM> includes a third MOS transistor M03 and a fourth MOS transistor M04 connected in series, the first end of the fourth MOS transistor M04 is connected to the seventh node net7, the second end of the fourth MOS transistor M04 is connected to the first end of the third MOS transistor M03, the second end of the third MOS transistor M03 is connected to the first node n_stg1, and the gate of the third MOS transistor M03 and the gate of the fourth MOS transistor M04 both receive a third control signal DfeTrim <<NUM>>. The fourth transistor group <NUM> includes a fifth MOS transistor M05 having a gate configured to receive a fourth control signal DfePerpin <<NUM>>. The fifth transistor group <NUM> includes a sixth MOS transistor M06 and a seventh MOS transistor M07 connected in series. The first end of the seventh MOS transistor M07 is connected to the seventh node net7, the second end of the seventh MOS transistor M07 is connected to the first end of the sixth MOS transistor M06, and the second end of the sixth MOS transistor M06 is connected to the first node n_stg1. The gates of both the sixth MOS transistor M06 and the seventh MOS transistor M07 receive a fifth control signal DfePerpin <<NUM>>.

It should be noted that, in the above three examples, the first control signal DFeTrim <<NUM>>, the second control signal DFeTrim <<NUM>>, and the third control signal DFeTrim <<NUM>> may be shared to all the data receiving circuits <NUM>, that is to say, for different data receiving circuits <NUM> connected to different DQ ports, the first control signal DFeTrim <<NUM>>, the second control signal DFeTrim <<NUM>> and the third control signal DFeTrim <<NUM>> supplied to the different data receiving circuits <NUM> are the identical. In addition, in the example shown in <FIG>, the fourth control signal DFePerPin <<NUM>> and the fifth control signal DFePerPin <<NUM>> are designed separately for each DQ port. It can be appreciated that, for different data receiving circuits connected to different DQ port, for example, a first data receiving circuit connected to a port DQ1 and a second data receiving circuit connected to a port DQ2, the fourth control signal DFePerpin <<NUM>> and the fifth control signal DFePerpin <<NUM>> in the first data receiving circuit are designed based on the port DQ1, and the fourth control signal DFePerpin <<NUM>> and the fifth control signal DFePerpin <<NUM>> in the second data receiving circuit are designed based on the port DQ2. Because the data received by different DQ ports suffer from different ISI, each data signal DQ also suffers from different interference in the transmission path, and different fourth control signals DfePerpin <<NUM>> and fifth control signals DfePerpin <<NUM>> are individually designed for the data signals DQ received by different DQ port, which facilitates targeted adjustment of each DQ port by the adjusting unit <NUM> to further improve reception performance of the data receiving circuit. The DQ port is the port used by the data receiving circuit to receive the data signal DQ.

In the above embodiment, with reference to <FIG>, different transistor groups may include a first transistor group <NUM>, a second transistor group <NUM> and a third transistor group <NUM> which are connected in parallel with each other. The equivalent width-to-length ratio of the channel of the first transistor group <NUM> is twice that of the second transistor group <NUM>, and the equivalent width-to-length ratio of the channel of the second transistor group <NUM> is twice that of the third transistor group <NUM>. In this way, the ratio of the equivalent resistance of the first transistor group <NUM>, the equivalent resistance of the second transistor group <NUM> and the equivalent resistance of the third transistor group <NUM> is <NUM>: <NUM>: <NUM>, so that the total equivalent resistance of the adjusting unit <NUM> can be linearly adjusted, thereby implementing linear adjustment of the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

It should be noted that, it is exemplified that the ratio of the equivalent width-to-length ratio of the channel of the first transistor group <NUM> to the equivalent width-to-length ratio of the channel of the second transistor group <NUM> is <NUM>, and the ratio of the equivalent width-to-length ratio of the channel of the second transistor group <NUM> to the equivalent width-to-length ratio of the channel of the third transistor group <NUM> is <NUM>, In practical applications, the ratio of the equivalent width-to-length ratio of the channel of the first transistor group <NUM> to the equivalent width-to-length ratio of the channel of the second transistor group <NUM>, or the ratio of the equivalent width-to-length ratio of the channel of the second transistor group <NUM> to the equivalent width-to-length ratio of the channel of the third transistor group <NUM> may also be other values, such as <NUM> or <NUM>.

It should be noted that, in <FIG>, the width-to-length ratio of the channel of the first MOS transistor M01 can be controlled to be twice the width-to-length of the channel of the second MOS transistor M02, so that the equivalent width-to-length ratio of the channel of the first transistor group <NUM> can be realized to be twice the equivalent width-to-length ratio of the channel of the second transistor group <NUM>. The equivalent width-to-length ratio of the channel of the second MOS transistor M02 can be controlled to be twice the width-to-length ratio of the channel of the third MOS transistor M03, so that the equivalent width-to-length ratio of the channel of the second transistor group <NUM> can be realized to be twice the equivalent width-to-length ratio of the channel of the third transistor group <NUM>. In <FIG>, the width-to-length ratio of the channel of the first MOS transistor M01 can be controlled to be twice the width-to-length of the channel of the second MOS transistor M02, so that the equivalent width-to-length ratio of the channel of the first transistor group <NUM> can be realized to be twice the equivalent width-to-length ratio of the channel of the second transistor group <NUM>. The width-to-length ratio of the channel of the second MOS transistor M02, the width-to-length ratio of the channel of the third MOS transistor M03 and the width-to-length ratio of the channel of the fourth MOS transistor M04 are controlled to be equal, so that the width-to-length ratio of the channel of the second MOS transistor M02 is twice the equivalent width-to-length ratio of the channel of the third transistor group <NUM>, that is to say, the equivalent width-to-length ratio of the channel of the second transistor group <NUM> is twice the equivalent width-to-length ratio of the channel of the third transistor group <NUM>.

In addition, in <FIG>, the width-to-length ratio of the channel of the fifth MOS transistor M05, the width-to-length ratio of the channel of the sixth MOS transistor M06 and the width-to-length ratio of the channel of the seventh MOS transistor M07 can be controlled to be equal, so that the width-to-length ratio of the channel of the fifth MOS transistor M05 can be realized to be twice the equivalent width-to-length ratio of the channel of the fifth transistor group <NUM>, that is to say, the equivalent width-to-length ratio of the channel of the fourth transistor group <NUM> is twice the equivalent width-to-length ratio of the channel of the fifth transistor group <NUM>. In some embodiments, the width-to-length ratio of the channel of the fifth MOS transistor M05 may also be equal to the width-to-length ratio of the channel of the second MOS transistor M02.

In one example, with reference to <FIG>, the length of the channel of the first MOS transistor M01, the length of the channel of the second MOS transistor M02 and the length of the channel of the third MOS transistor M03 may be equal. The width of the channel of the first MOS transistor M01 may be twice the width of the channel of the second MOS transistor M02, and the width of the channel of the second MOS transistor M02 may be twice the width of the channel of the third MOS transistor M03. It should be noted that, in practical application, in a case where the widths of the channels of the first MOS transistor M01, the second MOS transistor M02 and the third MOS transistor M03 are kept to be equal, the ratio relationship of equivalent width-to-length ratio of the channels of the first transistor group <NUM>, the second transistor group <NUM> and the third transistor group <NUM> can be implemented by adjusting the ratio relationship of lengths of the channels of the first MOS transistor M01, the second MOS transistor M02 and the third MOS transistor M03, alternatively, by adjusting the ratio relationship of widths of the channels of the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03, and simultaneously adjusting the ratio relationship of lengths of the channels the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03.

It should be noted that the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06 and the seventh MOS transistor M07 can all be PMOS transistors or NMOS transistors. When any one of the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06 and the seventh MOS transistor M07 is the PMOS transistor, the phase of the control signal for controlling the PMOS transistor in the on state is a first phase. When the MOS transistor is an NMOS transistor, the phase of the control signal for controlling the NMOS transistor in the on state is a second phase. The first phase is inverse to the second phase.

In some embodiments, with reference to <FIG>, the second amplification module <NUM> may include an input unit connected to the first node n_stg1 and the second node p_stg1, and configured to compare the first voltage signal and the second voltage signal and provide a third voltage signal and a fourth voltage signal respectively to an eighth node n_stg2and a ninth node p_stg2; and a latch unit <NUM> configured to amplify and latch the third voltage signal and the fourth voltage signal, output the first output signal Vout to the third node net3 and output the second output signal VoutN to the fourth node net4.

The input unit <NUM> is configured to compare the first voltage signal and the second voltage signal to output the third voltage signal and the fourth voltage signal. The latch unit <NUM> is configured to output, according to the third voltage signal and the fourth voltage signal, a high level signal to the third node net3 and a low level signal to the fourth node net4, or the latch unit <NUM> is configured to output, according to the third voltage signal and the fourth voltage signal, a low level signal to the third node net3 and a high level signal to the fourth node net4.

In some embodiments, with reference to <FIG> and <FIG>, the input unit <NUM> may include a third NMOS transistor MN3 connected between the eighth node n_stg2 and the ground terminal and having a gate configured to receive the first voltage signal; and a fourth NMOS transistor MN4 connected between the ninth node p_stg2 and the ground terminal, and having a gate configured to receive the second voltage signal.

In one example, when the level value of the first voltage signal outputted by the first node n_stg1 is higher than the level value of the second voltage signal outputted by the second node p_stg1, and the extent of turning on of the third NMOS transistor MN3 is greater than the extent of turning on of the fourth NMOS transistor MN4, so that the voltage at the eighth node n_stg2 is less than the voltage at the ninth node p_stg2, and then the extent of turning on of the fifth NMOS transistor MN5 is greater than the extent of turning on of the sixth NMOS transistor MN6, so that the voltage at the third node net3 is less than the voltage at the fourth node net4. Thus, the extent of turning on of the seventh PMOS transistor MP7 is greater than the extent of turning on of the sixth PMOS transistor MP6, and the latch unit <NUM> forms a positive feedback amplifier, further making the first output signal Vout outputted by the third node net3 to be at a low level and the second output signal VoutN outputted by the fourth node net4 to be at a high level.

In some embodiments, with continued reference to <FIG> and <FIG>, the latch unit <NUM> may include a fifth NMOS transistor MN5 connected between the eighth node n_stg2 and the third node net3 and having a gate configured to receive the second output signal VoutN; a sixth NMOS transistor MN6 connected between the ninth node p_stg2 and the fourth node net4 and having a gat configured to receive the first output signal Vout; a sixth PMOS transistor MP6 connected between the power supply node Vcc and the third node net3 and having a gate configured to receive the second output signal VoutN; and a seventh PMOS transistor MP7 connected between the power supply node Vcc and the fourth node net4 and having a gate configured to receive the first output signal Vout.

In some embodiments, with reference to <FIG>, the second amplification module <NUM> may further include a second reset unit <NUM> connected to the latch unit <NUM> and configured to reset the latch unit <NUM>. In this way, after the data receiving circuit completes the reception of the data signal DQ and the reference signal Vref and the output of the first output signal Vout and the second output signal VoutN once, the level values at the third node net3 and the fourth node net4 can be restored to the initial values by the second reset unit <NUM> so as to facilitate the next data reception and subsequent processing by the data receiving circuit.

In some embodiments, with reference to <FIG> and <FIG>, the second reset unit <NUM> may include an eighth PMOS transistor MP8 connected between the power supply node Vcc and the third node net3; and a ninth PMOS transistor MP9 is connected between the power supply node Vcc and the fourth node net4. A gate of the eighth PMOS transistor MP8 and a gate of the ninth PMOS transistor MP9 are both responsive to the third sampling clock signal CLK3.

In one example, the phase of the third sampling clock signal CLK3 is inverse to the phase of the first sampling clock signal CLK1, and the third sampling clock signal CLK3 and the fourth sampling clock signal CLK4 may be the same clock signal or different clock signals having the identical phase but different amplitudes. In this way, when it is necessary to reduce the influence of ISI on the data receiving circuit <NUM>, the enable signal DfeEn is in a first level value interval, i.e., the enable signal DfeEn is at the high level, when the first sampling clock signal CLK1 is at a low level, the fourth sampling clock signal CLK4 is at a high level, so that the second sampling clock signal CLK2 is at a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on; at this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off, the third sampling clock signal CLK3 is at a high level, and the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both turned off, so as to ensure the normal operation of the data receiving circuit <NUM>. When the influence of ISI on the data receiving circuit <NUM> is not required to be considered, the enable signal DfeEn is in a second level value interval, i.e., the enable signal DfeEn is at the low level, at this time, regardless of whether the first sampling clock signal CLK1 is at a low level or a high level, the second sampling clock signal CLK2 is at a fixed high level, the second PMOS transistor MP2 is turned off, and no current is supplied to the sixth node net <NUM>, i.e., the decision feedback equalization module <NUM> stops performing the decision feedback equalization to reduce the overall power consumption of the data receiving circuit <NUM>. In addition, whether or not the influence of ISI on the data receiving circuit <NUM> needs to be considered, when the first sampling clock signal CLK1 is high, the third sampling clock signal CLK3 is at a low level, and the first PMOS transistor MP1 is turned off, at this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, and the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both turned on, to pull down the voltage at the first node n_stg1 and the voltage at the second node p_stg1, and pull up the voltage at the third node net3 and the voltage at the fourth node net4,, so that the reset of the first node n_stg1, the second node p_stg1, the third node net3 and the fourth node net4 can be implemented.

In some embodiments, on the basis that the second reset unit <NUM> includes the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9, the second reset unit <NUM> may further include a tenth PMOS transistor (not shown in the figures) connected between the power supply node Vcc and the eighth node n_stg2; and an eleventh PMOS transistor (not shown in the figures) connected between the power supply node Vcc and the ninth node p_stg2. The gate of the tenth PMOS transistor and the gate of the eleventh PMOS transistor both response to the third sampling clock signal CLK3. In this way, when the data receiving circuit <NUM> does not need to receive the data signal DQ and the reference signal Vref, the third sampling clock signal CLK3 is at a low level, and both the tenth PMOS transistor and the eleventh PMOS transistor are turned on, so that the voltage at the eighth node n_stg2 and the voltage at the ninth node p_stg2 are pulled up to implement the reset of the eighth node n_stg2 and the ninth node p_stg2.

In some embodiments, with reference to <FIG>, the data receiving circuit <NUM> (with reference to <FIG>) may further include an offset compensation module <NUM> connected to the second amplification module <NUM> (with reference to <FIG>) and configured to compensate an offset voltage of the second amplification module <NUM>. Specifically, the offset compensation module <NUM> may connect to the eighth node n_stg2 and the ninth node p_stg2.

In some embodiments, with continued reference to <FIG>, the offset compensation module <NUM> may include a first offset compensation unit <NUM> connected between the eighth node n_stg2 and the ground terminal; and a second offset compensation unit <NUM> connected between the ninth node p_stg2 and the ground terminal. The first offset compensation unit <NUM> is configured to compensate the parameters of the third NMOS transistor MN3; and the second offset compensation unit <NUM> is configured to compensate the parameters of the fourth NMOS transistor MN4. The first offset compensation unit <NUM> and the second offset compensation unit <NUM> can adjust the offset voltage of the data receiving circuit by compensating the parameters of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

In some embodiments, with continued reference to <FIG>, the first offset compensation unit <NUM> may include at least two transistor groups connected in parallel, each transistor group includes a seventh NMOS transistor MN7 having a first end connected to an eighth node n_stg2 and a gate connected to the first node n_stg1; and a seventh MOS transistor M7 arranged in one-to-one correspondence with the seventh NMOS transistor MN7, the seventh MOS transistor M7 is connected between a second end of the seventh NMOS transistor MN7 and the ground terminal, and a gate of the seventh MOS transistor M7 is configured to receive the first mismatch adjustment signal Offset_1. It should be noted that for the sake of simplicity of illustration, only one transistor group in the first offset compensation unit <NUM> is schematically illustrated in <FIG>.

In this way, the extent of turning on of the seventh NMOS transistor MN7 can be controlled by the first mismatch adjustment signal Offset_1 to adjust the overall equivalent resistance of the first offset compensation unit <NUM> to further adjust the voltage at the eighth node n_stg2.

In some embodiments, the first offset compensation unit <NUM> includes two transistor groups connected in parallel. One of the transistor groups includes a (<NUM>-<NUM>)-th NMOS transistor (not shown in the figures) and a (<NUM>-<NUM>)-th MOS transistor (not shown in the figures), and the other of transistor groups includes a (<NUM>-<NUM>)-th NMOS transistor (not shown in the figures) and a (<NUM>-<NUM>)-th MOS transistor (not shown in the figures). The first mismatch adjustment signal Offset_1 includes a third mismatch adjustment signal (not shown in the figures) and a fourth mismatch adjustment signal (not shown in the figures), a gate of the (<NUM>-<NUM>)-th NMOS transistor and a gate of the (<NUM>-<NUM>)-th NMOS transistor are connected to the first node n_stg1, a gate of the (<NUM>-<NUM>)-th MOS transistor is configured to receive the third mismatch adjustment signal, and a gate of the (<NUM>-<NUM>)-th MOS transistor is configured to receive the fourth mismatch adjustment signal.

The third mismatch adjustment signal and the fourth mismatch adjustment signal may be different. In this way, the extent of turning on of the (<NUM>-<NUM>)-th NMOS transistor and/or the extent of turning on of the (<NUM>-<NUM>)-th MOS transistor can be controlled based on the third mismatch adjustment signal and the fourth mismatch adjustment signal, to flexibly adjust the overall equivalent resistance of the first offset compensation unit <NUM> and improve the adjustment effect for the voltage at the eighth node n_stg2.

In some embodiments, with reference to <FIG>, the second offset compensation unit <NUM> may include at least two transistor groups connected in parallel, each transistor group includes an eighth NMOS transistor MN8 having a first end connected to a ninth node p_stg2 and a gate connected to a second node p_stg1; and an eighth MOS transistor M8 arranged in one-to-one correspondence with an eighth NMOS transistor M8, the eighth MOS transistor M8 is connected between a second end of the eighth NMOS transistor MN8 and the ground terminal, and a gate of the eighth MOS transistor M8 is configured to receive a second mismatch adjustment signal Offset_2. It should be noted that for the sake of simplicity of illustration, only one transistor group in the second offset compensation unit <NUM> is schematically illustrated in <FIG>.

In this way, the extent of turning on of the eighth NMOS transistor MN8 can be controlled by the second mismatch adjustment signal Offset_2 to adjust the overall equivalent resistance of the second offset compensation unit <NUM> to further adjust the voltage at the ninth node p_stg2.

In some embodiments, the second offset compensation unit <NUM> includes two transistor groups connected in parallel. One of transistor groups includes an (<NUM>-<NUM>)-th NMOS transistor (not shown in the figures) and an (<NUM>-<NUM>)-th MOS transistor (not shown in the figures), and the other of transistor groups includes an (<NUM>-<NUM>)-th NMOS transistor (not shown in the figures) and an (<NUM>-<NUM>)-th MOS transistor (not shown in the figures). The second mismatch adjustment signal Offset_2 includes a fifth mismatch adjustment signal (not shown in the figures) and a sixth mismatch adjustment signal (not shown in the figures), a gate of the (<NUM>-<NUM>)-th NMOS transistor and a gate of the (<NUM>-<NUM>)-th NMOS transistor are connected to the first node n_stg1, a gate of the (<NUM>-<NUM>)-th MOS transistor is configured to receive the fifth mismatch adjustment signal, and a gate of the (<NUM>-<NUM>)-th MOS transistor is configured to receive the sixth mismatch adjustment signal.

The fifth mismatch adjustment signal and the sixth mismatch adjustment signal may be different. In this way, the extent of turning on of the (<NUM>-<NUM>)-th NMOS transistor and/or the extent of turning on of the (<NUM>-<NUM>)-th MOS transistor can be controlled based on the fifth mismatch adjustment signal and the sixth mismatch adjustment signal, to flexibly adjust the overall equivalent resistance of the second offset compensation unit <NUM> and improve the adjustment effect for the voltage at the ninth node p_stg2.

It should be noted that the seventh MOS transistor M7, the (<NUM>-<NUM>)-th MOS transistor, the (<NUM>-<NUM>)-th MOS transistor, the eighth MOS transistor M8, the (<NUM>-<NUM>)-th MOS transistor and the (<NUM>-<NUM>)-th MOS transistor can all be PMOS transistors or NMOS transistors. When any MOS transistor is a PMOS transistor, the phase of the first mismatch adjustment signal Offset_1 for controlling the PMOS transistor to be turned on is a third phase; when the MOS transistor is an NMOS transistor, the phase of the second mismatch adjustment signal Offset_2 for controlling the NMOS transistor to be turned on is a fourth phase. The third phase is inverse to the fourth phase.

It should be noted that in the above description of the high level and the low level, the high level may have a level value greater than or equal to the level value of the power supply voltage, and the low level may have a level value less than or equal to the level value of the ground voltage. Moreover, the high level and the low level are relative, and the specific level value ranges included in the high level and the low level can be determined according to the specific device. For example, for an NMOS transistor, the high level refers to the level value range of the voltage of the gate that enables the NMOS transistor to be turned on, and the low level refers to the level value range of the voltage of the gate that enables the NMOS transistor to be turned off. For a PMOS transistor, a low level refers to a level value range of the voltage of the gate that enables the PMOS transistor to be turned on, and a high level refers to a level value range of the voltage of the gate that enables the PMOS transistor to be turned off.

In view of above, the decision feedback control module <NUM> is configured to generate a second sampling clock signal CLK2 for controlling the decision feedback equalization module <NUM>, so as to flexibly control whether the decision feedback equalization module <NUM> is to be in an operating state. For example, when it is necessary to reduce the influence of ISI on the data receiving circuit <NUM>, i.e., when the enable signal DfeEn is in the first level value interval, the decision feedback control module <NUM> generates the second sampling clock signal CLK2 in response to the enable signal DfeEn at this time, and the decision feedback equalization module <NUM> performs decision feedback equalization based on the second sampling clock signal CLK2, so as to improve the reception performance of the data receiving circuit <NUM>. When the influence of the ISI on the data receiving circuit <NUM> is not required to be considered, i.e., when the enable signal DfeEn is in the second level value interval, the decision feedback equalization module <NUM> stops, based on the second sampling clock signal CLK2 at this time, performing the decision feedback equalization, so as to reduce the overall power consumption of the data receiving circuit <NUM>. In this way, it is possible to facilitate improving the reception performance of the data receiving circuit <NUM> and simultaneously reducing the overall power consumption of the data receiving circuit <NUM>.

Another embodiment of the present disclosure also provides a data receiving system, which will be described in detail below with reference to the accompanying drawings. <FIG> is a functional block diagram of a data receiving system according to another embodiment of the present disclosure.

With reference to <FIG>, the data receiving system includes multiple cascaded stages of data transmission circuits <NUM>. Each of the data transmission circuits <NUM> includes the data receiving circuit <NUM> as in the embodiments of the present disclosure and a latch circuit <NUM> connected to the data receiving circuit <NUM>, each of the data receiving circuits <NUM> connected to a data port to receive a data signal DQ; the data transmission circuit <NUM> of a preceding stage is connected to the decision feedback equalization module <NUM> of the transmission circuit <NUM> (with reference to <FIG>) of a following stage, and the output of the data transmission circuit <NUM> of the preceding stage serves as a feedback signal fb of the decision feedback equalization module <NUM> of the data transmission circuit <NUM> the following stage; and the data transmission circuit <NUM> of a last stage is connected to the decision feedback equalization module <NUM> of the data transmission circuit <NUM> of a first stage, and an output of the data transmission circuit <NUM> of the last stage serves as a feedback signal fb of the decision feedback equalization module <NUM> of the data transmission circuit <NUM> of the first stage.

The latch circuit <NUM> is arranged in one-to-one correspondence with the data receiving circuit <NUM>, and the latch circuit <NUM> is configured to latch and output a signal outputted by the data receiving circuit <NUM> corresponding to the latch circuit <NUM>.

In some embodiments, the data receiving circuit <NUM> is configured to receive data in response to the sampling clock signal; and the data receiving system includes four cascaded stages of data receiving circuits <NUM>, and the phase difference of sampling clock signals of the data receiving circuits <NUM> of adjacent stages is <NUM> degrees. In this way, the period of sampling the clock signal is twice the period of the data signal DQ received by the data port, which is beneficial to clock wiring and power consumption saving.

It should be noted that, the data receiving system includes four cascaded stages of the data receiving circuits <NUM>,and the phase difference of the sampling clock signals of the data receiving circuits <NUM> of the adjacent stages is <NUM> degrees as an example, In practical application, the number of cascaded stages of the data receiving circuits <NUM> included in the data receiving system is not limited, and the phase difference of sampling clock signals of data receiving circuits <NUM> of adjacent stages can be reasonably set based on the number of cascaded stages of the data receiving circuits <NUM>.

In some embodiments, the decision feedback equalization module <NUM> of the data receiving circuit <NUM> of the current stage is connected to the output of the second amplification module <NUM> of the data receiving circuit <NUM> of the previous stage, and the first output signal Vout and the second output signal VoutN outputted by the second amplification module <NUM> of the data receiving circuit <NUM> of the preceeding stage serve as the feedback signal fb of the data receiving circuit <NUM> of the following stage. In this way, the output of the data receiving circuit <NUM> is directly transmitted to the data transmission circuit <NUM> of the following stage without passing through the latch circuit <NUM>, which facilitates the reduction of the data transmission delay.

In other embodiments, the decision feedback equalization module <NUM> of the data receiving circuit <NUM> of the current stage is connected to the output of the latch circuit <NUM> of the previous stage, and the signal outputted by the latch circuit <NUM> of the proceeding stage serves as the feedback signal fb of the data receiving circuit <NUM> of the following stage.

In view of above, according to the data receiving system provided by another embodiment of the present disclosure, the decision feedback control module <NUM> is configured to generate the second sampling clock signal CLK2 for controlling the decision feedback equalization module <NUM>, so as to flexibly control whether the decision feedback equalization module <NUM> is to be in an operating state. For example, when it is necessary to reduce the influence of ISI on the data receiving circuit <NUM>, the decision feedback equalization module <NUM> performs decision feedback equalization based on the second sampling clock signal CLK2 to improve the reception performance of the data receiving circuit <NUM>. When the influence of the ISI on the data receiving circuit <NUM> is not required to be considered, the decision feedback equalization module <NUM> stops, based on the second sampling clock signal CLK2, performing the decision feedback equalization, to reduce the overall power consumption of the data receiving circuit <NUM>.

Another embodiment of the present disclosure also provides a storage device including multiple data ports; multiple data receiving systems as provided in another embodiment of the present disclosure, and each data receiving system corresponds to one data port.

In this way, when it is necessary to reduce the influence of ISI on the storage device, each data port in the storage device can flexibly adjust the received data signal DQ through the data receiving system, and improve the adjustment capability for the first output signal Vout and the second output signal VoutN, thereby improving the reception performance of the storage device. When the influence of the ISI is not required to be considered, the decision feedback equalization module <NUM> stops, based on the second sampling clock signal CLK2, performing the decision feedback equalization, to reduce the power consumption of the storage device.

In some embodiments, the storage device may be double date rate (DDR) memory, such as DDR4 memory, DDR5 memory, DDR6 memory, low power DDR4 (LPDDR4) memory, LPDDR5 memory, or LPDDR6 memory.

Claim 1:
A data receiving circuit (<NUM>), comprising:
a first amplification module (<NUM>), configured to receive a data signal (DQ) and a reference signal (Vref), compare the data signal (DQ) and the reference signal (Vref) in response to a first sampling clock signal (CLK1), and output a first voltage signal and a second voltage signal respectively through a first node (n_stg1) and a second node (p_stg1);
a decision feedback control module (<NUM>), configured to generate a second sampling clock signal (CLK2) in response to an enable signal (DfeEn);
a decision feedback equalization module (<NUM>), connected to the first node (n_stg1) and the second node (p_stg1), wherein the decision feedback equalization module (<NUM>) is configured to, when the enable signal (DfeEn) is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal (CLK2) and based on a feedback signal (fb) to adjust the first voltage signal and the second voltage signal, and stop performing the decision feedback equalization when the enable signal (DfeEn) is in a second level value interval, the feedback signal (fb) being obtained based on previously received data; and
a second amplification module (<NUM>), configured to amplify a voltage difference between the first voltage signal and the second voltage signal, and output a first output signal (Vout) and a second output signal (VoutN) respectively through a third node (net3) and a fourth node (net4).