Patent Description:
Document <CIT> discloses a power semiconductor module comprising a main substrate, at least one first semiconductor chip mounted on the main substrate, and at least one auxiliary substrate mounted on the main substrate, the at least one auxiliary substrate comprises a top face remote from the main substrate, wherein the at least one auxiliary substrate comprises an insulation layer which is based on an organic material and which is in direct contact with the main substrate, and comprises a top metal layer forming at least part of the top face.

Document <CIT> discloses a circuit arrangement including at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips.

Document <CIT> discloses an implementation of a semiconductor package including one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Power semiconductor module arrangements often include at least one semiconductor substrate arranged in a housing. A semiconductor arrangement including a plurality of controllable semiconductor elements (e.g., IGBTs, MOSFETs, HEMTs, etc.) is arranged on each of the at least one substrate. Each substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and, optionally, a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to a base plate. The layout of the semiconductor arrangement should be chosen to minimize the required size of the at least one substrate while, at the same time, heat that is generated during operation of the power semiconductor module arrangement is efficiently dissipated away from the controllable semiconductor elements and the substrate.

There is a need for a power semiconductor module arrangement that allows to efficiently dissipate heat away from the controllable semiconductor elements, while requiring a minimum of space on a substrate.

A power semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer includes a plurality of different sections that are separate and distinct from each other, a plurality of semiconductor bodies arranged on the first metallization layer, and a connection clip, the connection clip including a layer of an electrically conducting material having a thickness in a vertical direction that is significantly smaller than its length in a first horizontal direction and its width in a second horizontal direction, wherein a first electrode of each of the plurality of semiconductor bodies is electrically coupled to a first section of the first metallization layer, a second electrode of each of the plurality of semiconductor bodies is electrically coupled to a second section of the first metallization layer, a third electrode of each of the plurality of semiconductor bodies is electrically coupled to an additional metallization layer by means of one or more electrical connection elements, the additional metallization layer is arranged distant from and in parallel to the first metallization layer, and the additional metallization layer is arranged on an additional dielectric insulation layer, wherein the additional dielectric insulation layer is arranged in parallel to and distant from the dielectric insulation layer, and wherein the additional dielectric insulation layer is arranged between the additional metallization layer and the first metallization layer. The second electrode of each of the plurality of semiconductor bodies is electrically coupled to the second section of the first metallization layer by means of the connection clip. The additional dielectric insulation layer is coupled to the connection clip by means of a second connection layer, wherein the connection clip is arranged between the additional dielectric insulation layer and the second section of the first metallization layer.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description, as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". An electrical line or electrical connection as described herein may be a single electrically conductive element, or include at least two individual electrically conductive elements connected in series and/or parallel. Electrical lines and electrical connections may include metal and/or semiconductor material, and may be permanently electrically conductive (i.e., non-switchable). A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

Referring to <FIG>, a cross-sectional view of a power semiconductor module arrangement <NUM> is schematically illustrated. The power semiconductor module arrangement <NUM> includes a housing <NUM> and a substrate <NUM>. The substrate <NUM> includes a dielectric insulation layer <NUM>, a (structured) first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a (structured) second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The substrate <NUM> may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulation layer <NUM> may consist of or include one of the following materials: Al<NUM>O<NUM>, AlN, SiC, BeO or Si<NUM>N<NUM>. For instance, the substrate <NUM> may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Further, the substrate <NUM> may be an Insulated Metal Substrate (IMS). An Insulated Metal Substrate generally comprises a dielectric insulation layer <NUM> comprising (filled) materials such as epoxy resin or polyimide, for example. The material of the dielectric insulation layer <NUM> may be filled with ceramic particles, for example. Such particles may comprise, e.g., SiO<NUM>, Al<NUM>O<NUM>, AlN, or BN and may have a diameter of between about <NUM> and about <NUM>. The substrate <NUM> may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer <NUM>. For instance, a non-ceramic dielectric insulation layer <NUM> may consist of or include a cured resin.

The substrate <NUM> is arranged in a housing <NUM>. In the example illustrated in <FIG>, the substrate <NUM> is arranged on a base plate <NUM> which forms a ground surface of the housing <NUM>, while the housing <NUM> itself solely comprises sidewalls and a cover. This, however, is only an example. It is also possible that the housing <NUM> further comprises a ground surface and the substrate <NUM> and the base plate <NUM> be arranged inside the housing <NUM>. In some power semiconductor module arrangements <NUM>, more than one substrate <NUM> is arranged on a single base plate <NUM> or on the ground surface of a housing <NUM>. It is also possible that the substrate <NUM> itself forms a ground surface of the housing <NUM>.

One or more semiconductor bodies <NUM> may be arranged on the at least one substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on the at least one substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), and/or any other suitable semiconductor element.

The one or more semiconductor bodies <NUM> may form a semiconductor arrangement on the substrate <NUM>. In <FIG>, only two semiconductor bodies <NUM> are exemplarily illustrated. The second metallization layer <NUM> of the substrate <NUM> in <FIG> is a continuous layer. The first metallization layer <NUM> is a structured layer in the example illustrated in <FIG>. "Structured layer" means that the first metallization layer <NUM> is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this example includes three different sections. This, however, is only an example. Any other number of sections is possible. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer <NUM> may have no electrical connection or may be electrically connected to one or more other sections using electrical connection elements <NUM> such as, e.g., bonding wires or bonding ribbons. Electrical connections <NUM> may also include connection plates, conductor rails, or connection clips, for example, to name just a few examples. The one or more semiconductor bodies <NUM> may be electrically and mechanically connected to the substrate <NUM> by a first electrically conductive connection layer <NUM>. The first electrically conductive connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver powder, for example. According to other examples, it is also possible that the second metallization layer <NUM> is a structured layer. It is further possible to omit the second metallization layer <NUM> altogether.

The power semiconductor module arrangement <NUM> illustrated in <FIG> further includes terminal elements <NUM>. The terminal elements <NUM> are electrically connected to the first metallization layer <NUM> and provide an electrical connection between the inside and the outside of the housing <NUM>. The terminal elements <NUM> may be electrically connected to the first metallization layer <NUM> with a first end <NUM>, while a second end <NUM> of each of the terminal elements <NUM> protrudes out of the housing <NUM>. The terminal elements <NUM> may be electrically contacted from the outside at their respective second ends <NUM>. A first part of the terminal elements <NUM> may extend through the inside of the housing <NUM> in a vertical direction y. The vertical direction y is a direction perpendicular to a top surface of the substrate <NUM>, wherein the top surface of the substrate <NUM> is a surface on which the at least one semiconductor body <NUM> is mounted. The terminal elements <NUM> illustrated in <FIG>, however, are only examples. Terminal elements <NUM> may be implemented in any other way and may be arranged anywhere within the housing <NUM>. For example, one or more terminal elements <NUM> may be arranged close to or adjacent to the sidewalls of the housing <NUM>. Terminal elements <NUM> could also protrude through the sidewalls of the housing <NUM> instead of through the cover. The first end <NUM> of a terminal element <NUM> may be electrically and mechanically connected to the substrate <NUM> by an electrically conductive connection layer, for example (not explicitly illustrated in <FIG>). Such an electrically conductive connection layer may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder, for example. The first end <NUM> of a terminal element <NUM> may also be electrically coupled to the substrate <NUM> via one or more electrical connections <NUM>, for example.

The power semiconductor module arrangement <NUM> may further include an encapsulant <NUM>. An encapsulant <NUM> may consist of or include a silicone gel or may be a rigid molding compound, for example. The encapsulant <NUM> may at least partly fill the interior of the housing <NUM>, thereby covering the components and electrical connections that are arranged on the substrate <NUM>. The terminal elements <NUM> may be partly embedded in the encapsulant <NUM>. At least their second ends <NUM>, however, are not covered by the encapsulant <NUM> and protrude from the encapsulant <NUM> through the housing <NUM> to the outside of the housing <NUM>. The encapsulant <NUM> is configured to protect the components and electrical connections of the power semiconductor module <NUM>, in particular the components arranged on the substrate <NUM> inside the housing <NUM>, from certain environmental conditions and mechanical damage.

Now referring to <FIG>, a cross-sectional view of another power semiconductor module arrangement is schematically illustrated. The power semiconductor module arrangement of <FIG> essentially corresponds to the power semiconductor module arrangement <NUM> as has been described with respect to <FIG> above. A housing <NUM>, an encapsulant <NUM>, and terminal elements <NUM>, however, are not specifically illustrated in <FIG> schematically illustrates a top view of the power semiconductor module arrangement of <FIG>.

In particular, <FIG> schematically illustrate a substrate <NUM> comprising a structured first metallization layer <NUM> arranged on a first side of the dielectric insulation layer <NUM> and comprising a plurality of different sections that are separate and distinct from each other. The semiconductor bodies <NUM> are mounted on a first section <NUM><NUM> of the first metallization layer <NUM>. Each of the plurality of semiconductor bodies <NUM> comprises a control electrode and a controllable load path between a first load electrode and a second load electrode. The first load electrode of each of the plurality of semiconductor bodies <NUM> is electrically coupled to the first section <NUM><NUM> of the first metallization layer <NUM>, the second load electrode of each of the plurality of semiconductor bodies <NUM> is electrically coupled to a second section <NUM><NUM>, of the first metallization layer <NUM>, and the control electrode of each of the plurality of semiconductor bodies <NUM> is electrically coupled to one or more third sections <NUM><NUM> of the first metallization layer <NUM>. In the example of <FIG>, three third sections <NUM><NUM> are schematically illustrated. The different third sections <NUM><NUM> are separate and distinct from each other as well as from each of the other sections of the first metallization layer <NUM>. The different third sections <NUM><NUM>, however, are all designated as third sections <NUM><NUM> herein, as they are all electrically coupled to the control electrode of one or more of the plurality of semiconductor bodies <NUM>. Instead of a plurality (two or more) of separate third sections <NUM><NUM>, a single third section <NUM><NUM> could be provided instead. In the arrangement illustrated in <FIG>, the one or more third sections <NUM><NUM> are horizontally surrounded by the second section <NUM><NUM>. That is, the third sections <NUM><NUM> form a plurality of islands that are surrounded by the second section <NUM><NUM>. Instead, the one or more third sections <NUM><NUM> could also be arranged beside the second section <NUM><NUM> in any other way. All of the different sections of the first metallization layer <NUM>, however, are arranged on the dielectric insulation layer <NUM> and in one and the same plane. This requires a significant amount of space on the dielectric insulation layer <NUM>. The size of the dielectric insulation layer <NUM> in the power semiconductor module of <FIG> is chosen to be able to accommodate all of the different sections of the first metallization layer <NUM>. The substrate <NUM>, therefore, has a comparably large size and the overall costs of the power semiconductor module are comparably high.

Now referring to <FIG>, a power semiconductor module arrangement according to embodiments of the disclosure is schematically illustrated, wherein <FIG> schematically illustrates a cross-sectional view, and <FIG> schematically illustrates a top view of the exemplary power semiconductor module arrangement. The power semiconductor module arrangement, instead of the one or more third sections <NUM><NUM> arranged on the dielectric insulation layer <NUM>, comprises an additional metallization layer <NUM>A arranged in parallel to and distant from the first metallization layer <NUM>. The additional metallization layer <NUM>A is not arranged in the same plane as the first metallization layer <NUM>. Instead, the additional metallization layer <NUM>A is arranged vertically above the first metallization layer <NUM>. That is, a distance d1 between the first metallization layer <NUM> and the additional metallization layer <NUM>A in the vertical direction y is greater than zero. For example, the distance d1 may be at least <NUM>, at least <NUM>, or at least <NUM>. The distance d1, however, may be less than <NUM>, or less than <NUM>, for example. The distance d1 may be defined by the components that are arranged between the first metallization layer <NUM> and the additional metallization layer <NUM>A (e.g., connection layer, dielectric insulation layer, connection clip, etc.), as will be described in further detail below.

The semiconductor bodies <NUM> each may comprise a controllable semiconductor element, For example, the semiconductor bodies <NUM> may be implemented as IGBTs (Insulated-Gate Bipolar Transistor), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), JFETs (Junction Field-Effect Transistor), HEMTs (High-Electron-Mobility Transistor), and/or any other suitable controllable semiconductor elements. That is, each semiconductor body <NUM> comprises a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode, and the third electrode are each a different one of the first load electrode, the second electrode, and the control electrode. The first load electrodes of the plurality of semiconductor bodies <NUM> may be drain electrodes, the second load electrodes of the semiconductor bodies <NUM> may be source electrodes, and the control electrodes of the semiconductor bodies <NUM> may be gate electrodes. According to another example, the first load electrodes of the plurality of semiconductor bodies <NUM> may be collector electrodes, the second load electrodes of the semiconductor bodies <NUM> may be emitter electrodes, and the control electrodes of the semiconductor bodies <NUM> may be base electrodes. According to one embodiment of the disclosure, the plurality of semiconductor bodies <NUM> are all of the same kind. That is, each of the plurality of semiconductor bodies <NUM> may be or may comprise an IGBTs, for example. It is, however, also possible that the plurality of semiconductor bodies <NUM> comprises two different kinds of controllable semiconductor elements.

The first load electrode of each of the plurality of semiconductor bodies <NUM> may be electrically coupled to the first section <NUM><NUM> of the first metallization layer (<NUM>) by means of a first electrically conductive connection layer <NUM>. The first electrically conductive connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder, for example. The second load electrode of each of the plurality of semiconductor bodies <NUM> may be electrically coupled to the second section <NUM><NUM> of the first metallization layer <NUM> by means of one or more electrical connection elements <NUM> such as, e.g., bonding wires or bonding ribbons. The control electrode of each of the plurality of semiconductor bodies <NUM> may be electrically coupled to the additional metallization layer <NUM>A by means of one or more electrical connection elements <NUM>.

As the additional metallization layer <NUM>A is arranged in an additional plane in parallel to the first metallization layer <NUM>, less space is required on the dielectric insulation layer <NUM>. The semiconductor bodies <NUM>, during operation, generally generate a significant amount of heat. This heat is dissipated away from the semiconductor bodies <NUM> through the dielectric insulation layer <NUM>, e.g., towards a heat sink (not specifically illustrated). The additional metallization layer <NUM>A is not directly coupled to the dielectric insulation layer <NUM>. Any heat generated on the additional metallization layer <NUM>A, therefore, may not be conducted away as efficiently as heat generated on the first metallization layer <NUM>. However, as the additional metallization layer <NUM>A is electrically coupled to the control electrodes of the semiconductor bodies <NUM>, only control signals are conducted through the additional metallization layer <NUM>A. Control signals usually comprise electrical signals of 15V or less and are configured to control the function of the different semiconductor bodies <NUM>. Control signals, however, may also comprise electrical signals of more than 15V. In any case, however, control signals comprise electrical signals of voltages and currents that are significantly lower than the common supply voltages / load currents. The power semiconductor module arrangement may switch from an off state (non-working state) to an on state (working state), for example, when a supply voltage is provided. Supply voltages may be voltages of more than 100V, for example. Due to the comparably low voltages and low currents of the control signals only an insignificant amount of heat is generated in the additional metallization layer <NUM>A. Arranging the additional metallization layer <NUM>A distant from the dielectric insulation layer <NUM>, therefore, is not critical in view of overheating.

In the embodiments of the disclosure described with respect to <FIG>, the additional metallization layer <NUM>A is arranged on an additional dielectric insulation layer <NUM>A, wherein the additional dielectric insulation layer <NUM>A is arranged in parallel to and distant from the dielectric insulation layer <NUM>, and wherein the additional dielectric insulation layer <NUM>A is arranged between the additional metallization layer <NUM>A and the first metallization layer <NUM>. In this way, the additional metallization layer <NUM>A is electrically insulated from the first metallization layer <NUM>. The additional dielectric insulation layer <NUM>A may be coupled to the first metallization layer <NUM> by means of a second connection layer <NUM>. The second connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, a layer of an electrically insulating adhesive, or a layer of a sintered metal powder. In the example illustrated in <FIG>, an additional second metallization layer <NUM>A is arranged between the additional dielectric insulation layer <NUM>A and the second connection layer <NUM>. Therefore, solder or sintering techniques may be used, for example, in order to couple the additional dielectric insulation layer <NUM>A with the additional second metallization layer <NUM>A arranged thereon to the first metallization layer <NUM>. It is, however, also possible to glue the additional dielectric insulation layer <NUM>A with the additional second metallization layer <NUM>A arranged thereon to the first metallization layer <NUM>, using an electrically conductive or an electrically insulating adhesive, for example.

It is also possible that the additional second metallization layer <NUM>A be omitted, as is schematically illustrated in <FIG>. That is, the additional dielectric insulation layer <NUM>A may be directly attached to the first metallization layer <NUM>. In this case, soldering or sintering the additional dielectric insulation layer <NUM>A to the first metallization layer <NUM> may not be possible. The additional dielectric insulation layer <NUM>A may be glued to the first metallization layer <NUM> using an electrically conducting or an electrically insulating adhesive, for example. The additional second metallization layer <NUM>A generally has no function that is required for the operation of the power semiconductor module. That is, the sole function of the additional second metallization layer <NUM>A may be to facilitate mounting the additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A arranged thereon to the first metallization layer <NUM>.

The additional dielectric insulation layer <NUM>A may be arranged on and mechanically coupled to the second section <NUM><NUM> of the first metallization layer <NUM>. It is, however, also possible to arrange the additional dielectric insulation layer <NUM>A on any other section of the first metallization layer <NUM>. As is schematically illustrated in <FIG>, for example, the additional metallization layer <NUM>A may be electrically coupled to a fourth section <NUM><NUM> of the first metallization layer <NUM> by means of one or more electrical connection elements <NUM>. The fourth section <NUM><NUM> of the first metallization layer <NUM> may be electrically contacted by means of one or more terminal elements <NUM>, as has been described with respect to <FIG> above, for example (terminal elements not specifically illustrated in <FIG>).

Alternatively, it is also possible that the additional metallization layer <NUM>A be electrically coupled to a terminal element <NUM> extending vertically through a sidewall of the housing <NUM>, as is schematically illustrated in <FIG>. The additional metallization layer <NUM>A may be electrically coupled to the terminal element <NUM> by means of one or more electrical connection elements <NUM>, for example. The terminal element <NUM> may be molded into the sidewall of the housing <NUM>, for example, or may be arranged in a vertical hole extending through the sidewall of the housing <NUM>. The additional metallization layer <NUM>A, however, may also be electrically contacted from outside of the housing <NUM> in any other suitable way. For example, the additional metallization layer <NUM>A may be electrically contacted by mans of terminal elements <NUM>, similar to what has been described with respect to <FIG> above.

Arranging the additional metallization layer <NUM>A on an additional dielectric insulation layer <NUM>A and mounting the additional dielectric insulation layer <NUM>A to a section of the first metallization layer <NUM>, however, is only an example. Now referring to <FIG> which illustrate a power semiconductor module arrangement according to embodiments of the disclosure, the power semiconductor module arrangement comprises a connection clip <NUM>. The connection clip <NUM> comprises a layer of an electrically conducting material having a thickness t34 in a vertical direction y that is significantly smaller than its length l34 in a first horizontal direction x and its width w34 in a second horizontal direction z. For example, the thickness t34 of the connection clip <NUM> may be between <NUM> and <NUM>. The length l34 and width w34 of the connection clip <NUM> may be in the range of several millimeters up to several tens of millimeters, for example. The connection clip <NUM> may comprise or consist of copper, for example. Any other electrically conducting materials, however, are also possible. The connection clip <NUM> can essentially be regarded as an extensive metallic layer that is used to electrically couple the second load electrode of each of the plurality of semiconductor bodies <NUM> to the second section <NUM> of the first metallization layer <NUM>. The connection clip <NUM> may have any suitable regular or irregular shape. Instead of electrical connection elements <NUM> such as, e.g., bonding wires or bonding ribbons (see, e.g., <FIG> and <FIG>), the connection clip <NUM> is used to electrically couple the second load electrode of each of the plurality of semiconductor bodies <NUM> to the second section <NUM><NUM> of the first metallization layer <NUM>. The connection clip <NUM> may replace any other kind of electrical connection elements <NUM>. One electrical connection element <NUM> usually electrically couples a single semiconductor body <NUM> to the respective section of the first metallization layer <NUM>. The extensive connection clip <NUM> electrically couples a plurality of semiconductor bodies <NUM> to one and the same section of the first metallization layer <NUM>.

As the connection clip <NUM> is an extensive element, it provides a surface area (surface facing away from the substrate <NUM>) that is large enough to easily accommodate the additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A arranged thereon. As is schematically illustrated in the cross-sectional view of <FIG>, the additional metallization layer <NUM>A is arranged on the connection clip <NUM>, with the additional dielectric insulation layer <NUM>A arranged between the connection clip <NUM> and the additional metallization layer <NUM>A. Similar to what has been described above, an additional second metallization layer <NUM>A may be arranged between the additional dielectric insulation layer <NUM>A and the connection clip <NUM>. The additional second metallization layer <NUM>A, however, can also be omitted. The additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A arranged thereon may be mounted to the connection clip <NUM> similar to what has been described above with respect to <FIG> and <FIG>. That is, the additional dielectric insulation layer <NUM>A may be attached to the connection clip <NUM> (instead of to the first metallization layer <NUM>) by means of a second connection layer <NUM>. If the additional second metallization layer <NUM>A is present, the second connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, a layer of an electrically insulating adhesive, or a layer of a sintered metal powder, for example. If the additional second metallization layer <NUM>A is omitted, the additional dielectric insulation layer <NUM>A may be glued to the connection clip <NUM>, using an electrically conductive or an electrically insulating adhesive, for example.

The additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A and the optional additional second metallization layer <NUM>A arranged thereon may be implemented as a so-called flex-board (flexible printed circuit board). Conventional stiff or rigid printed circuit boards could also be used, for example. That is, the additional dielectric insulation layer <NUM>A may consist of a polymer, for example. The dielectric insulation layer <NUM> on the other hand, may consist of a ceramic material, similar to what has been described with respect to <FIG> above. The substrate <NUM>, however, may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer <NUM>. For instance, a non-ceramic dielectric insulation layer <NUM> may consist of or include a cured resin. It is, however, generally also possible that the additional dielectric insulation layer <NUM>A is a ceramic layer, similar to the dielectric insulation layer <NUM>. That is, the additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A and the optional additional second metallization layer <NUM>A arranged thereon may also be implemented as a conventional ceramic substrate (e.g., IMS, FPC, DCB, AMB, Al<NUM>O<NUM>, AlN, or Si<NUM>N<NUM> substrate). The additional dielectric insulation layer <NUM>A generally provides sufficient dielectric insulation between the additional metallization layer <NUM>A and the first metallization layer <NUM>, or between the additional metallization layer <NUM>A and the connection clip <NUM>. As has been described above, the additional metallization layer <NUM>A carries comparably small voltages and currents. The requirements concerning dielectric insulation, therefore, are comparably low.

As is illustrated in <FIG> and <FIG>, only the additional metallization layer <NUM>A may be provided on the surface of the additional dielectric insulation layer <NUM>A facing away from the substrate <NUM>. <FIG> schematically illustrates a three-dimensional view of an embodiment similar to the embodiment of <FIG> comprising only the additional metallization layer <NUM>A on the surface of the additional dielectric insulation layer <NUM>A facing away from the substrate <NUM>. It is, however, also possible that further metallization layers are provided on the additional dielectric insulation layer <NUM>A. This is exemplarily illustrated in <FIG>. In this example, one further metallization layer <NUM>E is arranged on the surface of the additional dielectric insulation layer <NUM>A facing away from the substrate <NUM>. This further metallization layer <NUM>E may be electrically coupled to an auxiliary emitter of each of the plurality of semiconductor bodies <NUM> by means of one or more electrical connection elements <NUM>, for example. The further metallization layer <NUM>E is only specifically illustrated with regard to the embodiments comprising a connection <NUM>, but may be implemented in similar ways in other embodiments not comprising a connection clip <NUM>. The at least one further metallization layer <NUM>E may be electrically coupled to a respective section <NUM><NUM> of the first metallization layer <NUM> by means of one or more electrical connection elements <NUM>, for example, similar to what has been described with respect to the additional metallization layer <NUM>A (see, e.g., <FIG>). The at least one further metallization layer <NUM>E, however, can also be electrically contacted in any other suitable way.

Now referring to all <FIG>, the additional metallization layer <NUM>A, and any further metallization layers <NUM>E arranged on the additional dielectric insulation layer 11A, may have a thickness t111A in the vertical direction y of up to <NUM>, up to <NUM>, up to <NUM>, or up to <NUM>. For example, the thickness t111A of the additional metallization layer <NUM>A may be between <NUM> and <NUM> for ceramic substrates or conventional printed circuit boards, or between <NUM> to <NUM>, possibly even between <NUM> and <NUM> for flex-boards. The additional metallization layer <NUM>A may comprise or consist of copper or aluminum, for example. The same applies for the optional additional second metallization layer <NUM>A. The additional dielectric insulation layer <NUM>A may have a thickness t11A in the vertical direction y of at least <NUM>, at least <NUM>, or at least <NUM>.

A cross-sectional area of the dielectric insulation layer <NUM> may be significantly larger than a cross-sectional area of the additional dielectric insulation layer <NUM>A. For example, the cross-sectional area of the dielectric insulation layer <NUM> may be at least ten times or at least <NUM> times larger than a cross-sectional area of the additional dielectric insulation layer <NUM>A.

The additional dielectric insulation layer <NUM>A with the additional metallization layer <NUM>A, the (optional) additional second metallization layer <NUM>A, and any further metallization layers <NUM>E arranged thereon may be mounted to a connection clip <NUM> before the connection clip <NUM> is stamped (cut) from a large metal sheet, or after the connection clip <NUM> has been stamped (cut) from a large metal sheet but before it has been bent in any way, or after stamping (cutting) and bending the connection clip <NUM> but before mounting it to the substrate <NUM>, or even after mounting the connection clip <NUM> to the substrate <NUM>.

Claim 1:
A power semiconductor module arrangement comprises,
a substrate (<NUM>) comprising a dielectric insulation layer (<NUM>) and a first metallization layer (<NUM>) arranged on a first side of the dielectric insulation layer (<NUM>), wherein the first metallization layer (<NUM>) comprises a plurality of different sections that are separate and distinct from each other;
a plurality of semiconductor bodies (<NUM>) arranged on the first metallization layer (<NUM>); and
a connection clip (<NUM>), the connection clip (<NUM>) comprising a layer of an electrically conducting material having a thickness (t34) in a vertical direction (y) that is significantly smaller than its length (l34) in a first horizontal direction (x) and its width (w34) in a second horizontal direction (z), wherein
a first electrode of each of the plurality of semiconductor bodies (<NUM>) is electrically coupled to a first section (<NUM><NUM>) of the first metallization layer (<NUM>),
a second electrode of each of the plurality of semiconductor bodies (<NUM>) is electrically coupled to a second section (<NUM><NUM>) of the first metallization layer (<NUM>),
a third electrode of each of the plurality of semiconductor bodies (<NUM>) is electrically coupled to an additional metallization layer (<NUM>A) by means of one or more electrical connection elements (<NUM>),
the additional metallization layer (<NUM>A) is arranged distant from and in parallel to the first metallization layer (<NUM>),
the additional metallization layer (<NUM>A) is arranged on an additional dielectric insulation layer (<NUM>A), wherein the additional dielectric insulation layer (<NUM>A) is arranged in parallel to and distant from the dielectric insulation layer (<NUM>), and wherein the additional dielectric insulation layer (<NUM>A) is arranged between the additional metallization layer (<NUM>A) and the first metallization layer (<NUM>),
the second electrode of each of the plurality of semiconductor bodies (<NUM>) is electrically coupled to the second section (<NUM><NUM>) of the first metallization layer (<NUM>) by means of the connection clip (<NUM>), and
the additional dielectric insulation layer (<NUM>A) is coupled to the connection clip (<NUM>) by means of a second connection layer (<NUM>), wherein the connection clip (<NUM>) is arranged between the additional dielectric insulation layer (<NUM>A) and the second section (<NUM><NUM>) of the first metallization layer (<NUM>).