Patent Description:
Rapidly, semiconductor devices formed on silicon substrates have become more highly integrated to have a relatively high performance. However, there is a limitation in improving the performance of semiconductor devices due to characteristics of silicon itself and in manufacturing processes. Accordingly, research has been conducted into next generation devices that may overcome the limitations of conventional semiconductor devices having silicon substrates.

Graphene, a graphite monoatomic layer, is being considered as a next generation material due to its superior electrical and mechanical properties. Graphene is a material in which carbon atoms are connected as a hexagon in a plane, and has a relatively small thickness corresponding to a monoatomic layer. Thus, graphene conducts electricity about a hundred times faster than polycrystalline silicon that is mainly used as a semiconductor, and theoretically has an electron mobility of about <NUM>,<NUM><NUM>/Vs, <NUM><NUM>/Vs. In addition, it is known that graphene may conduct electricity about a hundred times more than copper, and thus, graphene is considered as a basic material of electronic devices.

In particular, graphene is a zero gap semiconductor material, and thus, if a graphene nanoribbon (GNR) is manufactured to have a channel width of about <NUM> or less, a band gap is generated due to a size effect. Thus, a field effect transistor (FET) capable of operating at about room temperature may be manufactured.

Conventionally, graphene is grown on a metal thin film formed of copper (Cu) or nickel (Ni) by a chemical vapor deposition (CVD) method, and then, may be transferred onto an insulating thin film.

<CIT> discloses a graphene-channel based device having metal layers connecting regions of a graphene layer on a substrate as drain, source and gate terminals. These terminals may connect the device to a CMOS device on a different wafer.

<CIT> discloses a graphene-based device in which metal contacts adjacent respective metal gates are formed in a trench in an insulating substrate, and are covered by a graphene layer. Applying a voltage bias across the gates forms a PN junction in the graphene layer between them.

Example embodiments provide graphene switching devices including graphene field effect transistors (FETs) and graphene diodes.

Example embodiments provide graphene memory devices formed by combining graphene FETs and graphene diodes.

According to an aspect of the invention, there is provided a graphene electronic device according to claim <NUM>.

According to at least some example embodiments, the first gate structure may include a first ferroelectric layer and a first gate. The second gate structure may include a second ferroelectric layer and a second gate.

According to at least some example embodiments, the first gate structure may include a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate. The second gate structure may include a second tunneling oxide layer, a second floating gate, a second blocking oxide layer, and a second gate.

According to another aspect of the invention, there is provided a method of forming a graphene electronic device according to claim <NUM>.

According to at least some example embodiments, the method of forming a graphene electronic device may further include: forming a support structure on the intermediate layer, after forming the intermediate layer.

In at least one example embodiment, the substrate may include silicon and a silicon oxide layer, and the substrate may be removed by etching the silicon oxide layer. In at least one other example embodiment, the substrate may include a transparent substrate, and the substrate may be removed by a laser lift-off process.

The graphene layer may be formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method, after forming the catalyst layer on the intermediate layer.

These and/or other aspects will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings in which:.

Example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements.

Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may be embodied in many alternate forms and should not be construed as limited to only those set forth herein.

It should be understood, however, that there is no intent to limit this disclosure to the particular example embodiments disclosed. On the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.

For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of this disclosure.

It will be understood that when an element is referred to as being "connected," or "coupled," to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected," or "directly coupled," to another element, there are no intervening elements present.

Various example embodiments of the present invention will now be described more fully with reference to the accompanying drawings in which some example embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

<FIG> is a cross-sectional view of a graphene electronic device <NUM> according to an example embodiment. In addition, <FIG> is a schematic plan view of the graphene electronic device <NUM> shown in <FIG> is a cross-sectional view taken along line m1-m2 of <FIG>.

Referring to <FIG>, the graphene electronic device <NUM> includes an intermediate layer <NUM> formed on a support structure <NUM>, a first conductive layer <NUM> and a semiconductor layer <NUM> formed on a first region of the intermediate layer <NUM>, and a second conductive layer <NUM> formed on a second region of the intermediate layer <NUM>. In addition, a graphene layer <NUM> is formed on the intermediate layer <NUM>, the semiconductor layer <NUM>, and the second conductive layer <NUM>. First and second gate structures are formed on the graphene layer <NUM>. The first gate structure includes a gate insulating layer <NUM> and a first gate <NUM>. The second gate structure includes the gate insulating layer <NUM> and a second gate <NUM>. On the graphene layer <NUM>, the first gate structure is formed corresponding to the first region of the intermediate layer <NUM>, and the second gate structure is formed in a space between the first and second regions of the intermediate layer <NUM>.

The graphene electronic device according to at least this example embodiment may be configured to perform functions of a graphene transistor and/or a graphene diode. Referring to <FIG>, the semiconductor layer <NUM> and the graphene layer <NUM> may be a diode region functioning as a graphene tunable diode according to a voltage applied via the first gate <NUM>. In addition, regarding the graphene transistor function, the first conductive layer <NUM> and the semiconductor layer <NUM> in <FIG> may be a source electrode, the second conductive layer <NUM> may be a drain electrode, the graphene layer <NUM> may be a channel region, and the second gate <NUM> may be a gate electrode.

Materials forming each of the layers in the graphene electronic device according to at least this example embodiment are described below.

The support structure <NUM> supports each of the layers of the graphene electronic device formed thereon, and may be formed in manufacturing processes for processing stability. The support structure <NUM> may be formed of various materials, for example, a semiconductor substrate such as a Si substrate that is used as a substrate of a semiconductor device, a polymer substrate, an adhesive tape, etc. The support structure <NUM> may include a material having relatively high attachability to the intermediate layer <NUM>, and if necessary, the support structure <NUM> may be formed of the same or substantially the same material as that of the intermediate layer <NUM>.

The intermediate layer <NUM> may be formed of a polymer material, or a material having an insulating property. The intermediate layer <NUM> may be a protective layer that protects the graphene layer <NUM> and the first and second conductive layers <NUM> and <NUM> during forming of the graphene electronic device <NUM>. The first conductive layer <NUM>, the second conductive layer <NUM>, the first gate <NUM>, and the second gate <NUM> may be formed of a conductive material such as metal, a metal alloy, conductive metal oxide, conductive polymer, etc..

The semiconductor layer <NUM> may be formed of a semiconductor material, for example, a material including silicon (Si), amorphous silicon (a-Si), zinc-oxide (ZnO), gallium-indium-zinc-oxide (GalnZnOx), hafnium-indium-zinc-oxide (HflnZnOx), gallium-nitride (GaN), gallium-arsenic (GaAs), aluminum-gallium-arsenic (AlGaAs), etc., and may be formed to have a single or multi-layer structure. In addition, the semiconductor layer <NUM> may include a layer doped with impurities, for example, a-Si/n-type Si structure.

The gate insulating layer <NUM> may be formed of an insulating material such as that formed in a semiconductor device. For example, the gate insulating layer <NUM> may be silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zinc oxide, magnesium oxide, etc..

The graphene layer <NUM> may be formed by using various methods. For example, to form the graphene layer <NUM>, a catalyst layer including nickel (Ni), copper (Cu), cobalt (Co), platinum (Pt), or ruthenium (Ru) may be formed first, and the graphene layer <NUM> may be formed on the catalyst layer, for example, by a pyrolysis method or a chemical vapor deposition (CVD) method.

<FIG> is a graph schematically showing example electrical characteristics of the graphene electronic device <NUM> shown in <FIG>.

Referring to <FIG>, an electric current according to a voltage applied via the first conductive layer <NUM> and the second conductive layer <NUM> in a state where a voltage is not applied to the first gate <NUM> and the second gate <NUM> (Vg1=<NUM> and Vg2=<NUM>) follows graph <NUM>.

When the voltage is not applied to the first gate <NUM> (Vg=<NUM>) and a voltage is applied to the second gate <NUM> (Vg2><NUM>), the electric current increases according to the transistor characteristics illustrating graph <NUM>. On the other hand, when a voltage is applied to the first gate <NUM> (Vg><NUM>) and a voltage is not applied to the second gate <NUM> (Vg2=<NUM>), a turn-on voltage increases due to tunable diode characteristics as shown in graph <NUM>. If the voltage is applied to both of the first gate <NUM> and the second gate <NUM> (Vg><NUM> and Vg2><NUM>), the electric current and the turn-on voltage both increase as shown in graph <NUM> according to the transistor characteristics and the tunable diode characteristics.

Hereinafter, an example embodiment of a method of manufacturing a graphene electronic device is described with reference to <FIG>.

<FIG> are diagrams illustrating an example embodiment of a method of manufacturing the graphene electronic device <NUM> shown in <FIG>.

Referring to <FIG>, a semiconductor layer <NUM>, a first conductive layer <NUM>, and a second conductive layer <NUM> are formed on substrate <NUM> and <NUM>. The substrate <NUM> and <NUM> may be formed of various substrate materials. For example, the substrate <NUM> and <NUM> may be a silicon substrate <NUM> on which a silicon oxide layer <NUM> is formed, a glass substrate, a SiC substrate, a GaN substrate, etc..

A semiconductor material layer is formed on the substrate <NUM> and <NUM> and patterned to form the semiconductor layer <NUM>. A conductive material layer is formed on the semiconductor layer <NUM> and the substrate <NUM> and <NUM>, patterned to form the first conductive layer <NUM> and the second conductive layer <NUM>.

Referring to <FIG>, an insulating material is formed on the substrate <NUM> and <NUM>, the semiconductor layer <NUM>, the first conductive layer <NUM>, and the second conductive layer <NUM> to form an intermediate layer <NUM>. The intermediate layer <NUM> may be formed of an insulating material such as polymer, silicon oxide, silicon nitride, etc..

After forming the intermediate layer <NUM>, a support structure <NUM> is formed on the intermediate layer <NUM>. The support structure <NUM> is formed to support a device in post processes, and may be selectively omitted.

Referring to <FIG>, the substrate <NUM> and <NUM> are removed. The substrate <NUM> and <NUM> may be removed in various ways. For example, if the substrate <NUM> and <NUM> include silicon/silicon oxide, then the silicon oxide may be removed by etching. In addition, an interface area of the substrate <NUM> and <NUM> may be divided by irradiating laser in a laser lift-off (LLO) process. In this case, the substrate <NUM> and <NUM> may be used in a state where a material such as SiO:H, SiN:H, a-Si:H, AlO, ZnO, MgO, or GaN is formed on a transparent substrate such as glass by a plasma-enhanced CVD (PECVD) method. When the laser is irradiated to separate the substrates formed as described above, a gas is generated at an interface of the transparent substrate so that the transparent substrate may be separated. A graphene layer <NUM> is then formed on a portion from which the substrate <NUM> and <NUM> are separated.

Referring to <FIG>, a gate insulating layer <NUM> is formed on the graphene layer <NUM>. A conductive material is then applied on the gate insulating layer <NUM>, and patterned to form a first gate 39a and a second gate 39b.

The graphene electronic device according to at least some example embodiments may be used to form various kinds of electronic devices according to a gate structure formed on a graphene layer.

<FIG> is a cross-sectional view of an example embodiment of a ferroelectric random access memory (FRAM) device including graphene.

Referring to <FIG>, an intermediate layer <NUM> is formed on a support structure <NUM>, a first conductive layer <NUM> and a semiconductor layer <NUM> are formed on a first region of the intermediate layer <NUM>, and a second conductive layer <NUM> is formed on a second region of the intermediate layer <NUM>. A graphene layer <NUM> is formed on the intermediate layer <NUM>, the semiconductor layer <NUM>, and the second conductive layer <NUM>. First and second gate structures are formed on the graphene layer <NUM>. The first gate structure includes a ferroelectric layer <NUM> and a first gate <NUM>. The second gate structure includes a ferroelectric layer <NUM> and a second gate <NUM>. In this example embodiment, the first gate structure is formed on the graphene layer <NUM> to correspond to the first region of the intermediate layer <NUM>, and the second gate structure is formed on the graphene layer <NUM> in a space between the first and second regions of the intermediate layer <NUM>. The ferroelectric layers <NUM> and <NUM> may be formed of a ferroelectric material such as lead zirconate titanate (PZT), BaTiO<NUM>, polyvinylidene difluoride (PVDF), etc. The memory device having the structure shown in <FIG> may be a <NUM>-bit/cell memory device.

<FIG> is a cross-sectional view of an example embodiment of a flash memory device including graphene.

Referring to <FIG>, the flash memory device includes an intermediate layer <NUM> formed on a support structure <NUM>, a first conductive layer <NUM> and a semiconductor layer <NUM> formed on a first region of the intermediate layer <NUM>, and a second conductive layer <NUM> formed on a second region of the intermediate layer <NUM>. A graphene layer <NUM> is formed on the intermediate layer <NUM>, the semiconductor layer <NUM>, and the second conductive layer <NUM>. A first gate structure and a second gate structure are formed on the graphene layer <NUM>. The first gate structure is formed on the graphene layer <NUM> to correspond to the first region of the intermediate layer <NUM>. The second gate structure is formed on the graphene layer <NUM> in a space between the first and second regions of the intermediate layer <NUM>. The first gate structure includes a first tunneling oxide layer <NUM>, a first floating gate <NUM>, a first blocking oxide layer <NUM>, and a first gate <NUM>. The second gate structure includes a second tunneling oxide layer <NUM>, a second floating gate <NUM>, a second blocking oxide layer <NUM>, and a second gate <NUM>. The memory device shown in <FIG> may be a <NUM>-bit/cell flash memory device.

<FIG> is a cross-sectional view of an example embodiment of a hybrid-type memory device including graphene.

Referring to <FIG>, the hybrid-type memory device includes an intermediate layer <NUM> formed on a support structure <NUM>, a first conductive layer <NUM> and a semiconductor layer <NUM> formed on a first region of the intermediate layer <NUM>, and a second conductive layer <NUM> formed on a second region of the intermediate layer <NUM>. A graphene layer <NUM> is formed on the intermediate layer <NUM>, the semiconductor layer <NUM>, and the second conductive layer <NUM>. A first gate structure and a second gate structure are formed on the graphene layer <NUM>. The first gate structure is formed on the graphene layer <NUM> to correspond to the first region of the intermediate layer <NUM>. The second gate structure is formed in a space between the first and second regions of the intermediate layer <NUM>. The first gate structure includes a tunneling oxide layer <NUM>, a floating gate <NUM>, a blocking oxide layer <NUM>, and a first gate <NUM>. The second gate structure includes a ferroelectric layer <NUM> and a second gate <NUM>. In the memory device shown in <FIG>, the first gate structure is a flash memory region, and the second gate structure is a ferroelectric memory region. However, the first gate structure may be formed as a ferroelectric memory region including a ferroelectric layer and a gate, and the second gate structure may be formed as a flash memory region.

According to at least some example embodiments, graphene electronic devices having improved electrical characteristics by using graphene may be formed. Also, switching devices having characteristics of both graphene transistors and graphene diodes may be formed. In addition, memory devices having characteristics of both graphene transistors and graphene diodes may be formed.

Claim 1:
A graphene electronic device comprising:
a first conductive layer (<NUM>, <NUM>, <NUM>, <NUM>) formed on a first region of an intermediate layer (<NUM>, <NUM> ,<NUM>, <NUM>) and a semiconductor layer (<NUM>, <NUM>, <NUM>, <NUM>) formed over the first conductive layer;
a second conductive layer (<NUM>, <NUM>, <NUM>, <NUM>) formed on a second region spaced from the first region of the intermediate layer;
a graphene layer (<NUM>, <NUM>, <NUM>, <NUM>) formed on the intermediate layer, the semiconductor layer and the second conductive layer, so that the semiconductor layer (<NUM>, <NUM>, <NUM>, <NUM>) is between the first conductive layer (<NUM>, <NUM>, <NUM>, <NUM>) and the graphene layer (<NUM>, <NUM>, <NUM>, <NUM>); and
a first gate structure (<NUM>) and a second gate structure (<NUM>) formed on the graphene layer, so that the graphene layer is between the gate structures and the intermediate layer, wherein the first gate structure is formed in a space that corresponds to the first region of the intermediate layer (<NUM>, <NUM>), wherein the second gate structure is formed in the space between the first region and the second region of the intermediate layer (<NUM>, <NUM>, <NUM>, <NUM>), and wherein there is no gate structure in the second region of the intermediate layer (<NUM>, <NUM>, <NUM>, <NUM>).