Patent Description:
Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by wireless communication technologies, such as Wi-Fi, long-term evolution (LTE), and fifth-generation new-radio (<NUM>-NR). In part because of the frequencies at which it operates, <NUM>-NR implements a rigorous power control scheme with frequent changes to transmission power levels. The frequent changes in transmission power levels in turn necessitate the ability to change the output of power amplifier arrays quickly, which is typically done through some form of envelope tracking (ET) or average power tracking (APT). Even with ET and APT approaches, frequent power level changes necessitate frequently changing control signals sent to the power amplifier arrays.

Conventional approaches to fast changes in control signals generated by ET and APT circuits involve changing the size of capacitors and inductors in the control circuit, and specifically, reducing the size of capacitors and inductors in the control circuit, which generally makes the control signal change faster. However, reducing the size of the capacitors and inductors may introduce other unwanted ripples in the control signal. Accordingly, improved control techniques are warranted.

Steve Taranovich, Enhancing the inefficiency of an RF power amp: The envelope tracking system, XP055954227, discloses envelope tracking as a means of solving inefficiencies in wideband power amplifiers in the context of wireless telecom and other base station transmitters. <CIT> discloses a variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking and average power tracking. <CIT> discloses techniques for regulating voltage supplied to a power amplifier.

Aspects disclosed in the detailed description include a dual-mode average power tracking (APT) controller. In a first mode, the APT controller operates to move the control voltage quickly without concern for ripple or ringing. When this coarse adjustment takes the control voltage to within a desired margin of a target, the controller may switch to a second mode, where the APT controller more slowly approaches the target, but has reduced ringing or ripples. The mode is changed by changing resistance and capacitance values in a loop filter within the APT circuit. In a further aspect, a pulse shaper circuit may inject a pulse to force the control voltage to change more rapidly. By switching modes in this fashion, the control voltage may quickly reach a desired target, and then remain in the second mode during a transmission time slot such that the control voltage is clean throughout.

In one aspect, an APT circuit is disclosed. The APT circuit comprises a digital-to-analog converter (DAC). The DAC comprises a change signal output configured to provide a change signal indicative of a needed change in a voltage control signal (Vcc) and a target control voltage signal output. The APT circuit also comprises a transition management circuit coupled to the change signal output and configured to receive the change signal and comprising a mode output configured to provide a mode signal based on the change signal. The APT circuit also comprises a loop filter coupled to the target control voltage signal output and the mode output. A change in the mode signal causes the loop filter to switch between a first mode and a second mode and the loop filter is configured to provide a signal. The APT circuit also comprises output circuitry configured to provide the Vcc based on the signal from the loop filter.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

It should be understood that these concepts and applications fall within the scope of the disclosure if they fall within the scope of the accompanying claims.

In this regard, <FIG> illustrates a block diagram of a conventional APT circuit <NUM>. The APT circuit <NUM> includes a digital-to-analog converter (DAC) <NUM>. The DAC <NUM> includes an input <NUM> (input <NUM> may be a pin or a node as is well understood) that receives a digital signal <NUM> from an envelope tracking (ET) circuit (not shown). The DAC <NUM> converts the digital signal <NUM> to an analog target control voltage signal <NUM>. An adder <NUM> adds the target control voltage signal <NUM> to an inverted (negative) feedback signal <NUM>. The adder <NUM> is coupled to a loop filter <NUM>. The loop filter <NUM> may also include a controller (not shown) and/or an error amplifier (also not shown). A signal <NUM> from the adder <NUM> is filtered by the loop filter <NUM> to produce a signal <NUM>. The signal <NUM> is provided to a switch control circuit <NUM>, which turns on and off switches in a switch array circuit <NUM> based on the signal <NUM>. The switch control circuit <NUM> represents a function that sequences the closing of the various power switches in the switch array circuit <NUM> to control the output of the switch array circuit <NUM>. In an exemplary aspect, the switch control circuit <NUM> may be a pulse width modulation (PWM) modulator. The output of the switch array circuit <NUM> is filtered by an inductor <NUM> and a capacitor <NUM> to provide a voltage control signal <NUM> (also referred to as Vcc), which is used to control power amplifiers in a transmitter (not shown). The voltage control signal <NUM> is also provided to a feedback circuit <NUM>, which provides the feedback signal <NUM> to the adder <NUM>.

New cellular standards like <NUM> changed the RF output power control scheme such that power changes are frequent, especially compared to previous cellular standards. For example, <NUM>-NR may have a power change occurring within <NUM> microseconds (µs) with a <NUM> kilohertz (kHz) sub-carrier spacing (SCS). Consequently, the power amplifier voltage must settle extremely fast when there is a power level change. For APT, where Vcc is only supposed to change when power is requested to change, such fast transitions are a challenge while having stable Vcc during unchanging slots.

In conventional systems, for a given load, and assuming an "ideal" control of the switches in the switch array circuit <NUM>, the limit on how fast Vcc can change is the capacitance of the capacitor <NUM> along with a rate of charging for the capacitor (i.e., how quickly can current be "poured into" the capacitor <NUM>). The charging rate is a function of the inductor <NUM>, with the rate increasing as the inductance of the inductor <NUM> decreases. Further, the more voltage across the inductor <NUM>, the faster the current change rate. Using traditional systems may result in a slow settle as seen in <FIG> where graph <NUM> shows Vcc requiring time Tsettle to get to a lower threshold <NUM> and even more time to get to the final target level <NUM>. The slow approach to the final target level <NUM> results in relatively low ringing in the frequency domain as evidenced by spurs <NUM>.

While one approach to get fast APT transitions is to decrease the inductance and capacitance of the inductor <NUM> and the capacitor <NUM>, reductions in these values increase the ripple or ringing at harmonics. Using this approach results in graph <NUM> shown in <FIG>, where Vcc reaches a lower threshold <NUM>, relatively quickly as shown by the small Tsettle, but has ripple <NUM> before settling at the final target level <NUM>. Likewise, there is substantial ringing as shown by spurs <NUM>. The presence of this ripple requires the switching frequency to be increased to limit the ripple. The net result of this approach negatively impacts noise performance and efficiency, such that this solution is not commercially practical for <NUM>-NR.

Exemplary aspects of the present disclosure adopt a two-mode approach, where a first fast mode, but likely ringing- or ripple-inducing, circuit is used to make a coarse adjustment that quickly changes Vcc to a value within a predefined threshold of a target Vcc value, and a second slow mode is used to provide a clean non-ringing, but comparatively slow, fine adjustment to Vcc that changes Vcc to the final target Vcc value and holds Vcc at this final target cleanly for the desired duration (e.g., in the "slot"). To switch between modes, the loop filter circuit is changed. In a specifically contemplated aspect, the resistance(s) and/or capacitance(s) within the loop filter are changed. In a further aspect, a pulse shaper circuit may be used to inject a hard pulse form to assist in changing the input to the switch control circuit to the desired target value.

In this regard, <FIG> illustrates an APT circuit <NUM> that includes a DAC <NUM>. The DAC <NUM> includes an input <NUM> (which may be a pin or a node as is well understood) that receives a digital signal <NUM> from an ET circuit (not shown). The DAC <NUM> converts the digital signal <NUM> to an analog target control voltage signal <NUM> at a target control voltage signal output <NUM> (which may also be a pin or a node). An adder <NUM> (equivalently an adder circuit) adds the target control voltage signal <NUM> to an inverted (negative) feedback signal <NUM>. The adder <NUM> is coupled to a loop filter <NUM>, and thus, the loop filter <NUM> is coupled to the target control voltage signal output <NUM> indirectly. The loop filter <NUM> may also include a controller (not shown) and/or an error amplifier (also not shown). A signal <NUM> from the adder <NUM> is filtered by the loop filter <NUM> to produce a signal <NUM>. The signal <NUM> is provided to a switch control circuit <NUM>, which turns on and off switches in a switch array circuit <NUM> based on the signal <NUM>. The switch control circuit <NUM> represents a function that sequences the closing of the various power switches in the switch array circuit <NUM> to control the output of the switch array circuit <NUM>. In an exemplary aspect, the switch control circuit <NUM> may be a PWM modulator. The output of the switch array circuit <NUM> is filtered by an inductor <NUM> and a capacitor <NUM> to provide a voltage control signal <NUM> (also referred to as Vcc) at an output <NUM> (which may also be a pin or a node). The voltage control signal <NUM> is used to control power amplifiers in a transmitter (not shown). The voltage control signal <NUM> is also provided to a feedback circuit <NUM>, which provides the feedback signal <NUM> to the adder <NUM>. Collectively, the switch control circuit <NUM>, the switch array circuit <NUM>, and the filter formed by the inductor <NUM> and the capacitor <NUM> may be considered output circuitry that is configured to provide the voltage control signal <NUM> based on the signal <NUM> at the output <NUM>. The constituent elements of the output circuitry may vary without departing from the scope of the present disclosure.

With continued reference to <FIG>, the DAC <NUM> also includes a change signal output <NUM> (which may also be a pin or node) that provides a signal <NUM> indicative of a change in state of the DAC <NUM>. In an exemplary aspect, the signal <NUM> is generated each time there is a change in the state of the DAC <NUM>. Alternatively, the signal <NUM> may be generated only when the change in state exceeds a predefined threshold. The signal <NUM> may include information not merely relating to the existence of a change in state, but also a magnitude and direction of the change. The change in state of the DAC <NUM> is indicative of a needed change in the voltage control signal <NUM>, and thus, small changes needed to the voltage control signal <NUM> may not need to implement the fast mode of the present disclosure.

A transition management circuit <NUM> is coupled to the change signal output <NUM> to receive the signal <NUM>. The transition management circuit <NUM> is configured to provide a mode signal <NUM> to the loop filter <NUM>. Based on the mode signal <NUM>, the loop filter <NUM> may change between a first mode (i.e., a fast mode) and a second mode (i.e., a slow mode). <FIG> illustrates the difference in modes. Specifically, graph <NUM> shows Vcc rapidly climbing in the first mode <NUM> until a threshold <NUM> is reached, at which time the mode signal <NUM> causes the loop filter <NUM> to change the second mode <NUM> which allows Vcc to settle slowly to the target value <NUM>, effectively without ripple and as evidenced by the spectrum graph <NUM>, with little or no problematic ringing <NUM>.

Exemplary test results comparing the dual-mode approach of the present disclosure to conventional systems are shown in graph <NUM> of <FIG>, where the first mode <NUM> lasts from approximately <NUM> to <NUM> (or about <NUM>) after which the second mode <NUM> begins. Vcc <NUM> reaches a zone close to the target Vcc value much faster than the Vcc baseline <NUM> of the conventional approach. The signal <NUM> from the DAC <NUM> is also included to show the transition relative to the change in the DAC <NUM>.

<FIG> provides an alternate aspect where a pulse shaper circuit <NUM> is added to the APT circuit <NUM>'. The pulse shaper circuit <NUM> is coupled to an adder <NUM> (equivalently an adder circuit or second adder circuit) positioned between the loop filter <NUM> and the switch control circuit <NUM>. The pulse shaper circuit <NUM> may inject voltage spurs or other pulse signals <NUM> (positive or negative) through the adder <NUM> to facilitate more rapid changes in Vcc.

In an exemplary aspect, the pulse shaper circuit <NUM> is controlled by the transition management circuit <NUM> and may have a programmable duration period. That is, the height and/or length of the pulse to be injected may be varied. The programmable duration period may be a function of a battery voltage and/or a voltage step change. For example, if there is a relatively small voltage step change of one volt (<NUM> V), a smaller (magnitude and/or duration) pulse may be applied than if there were a relatively larger step change of three volts (<NUM> V).

While the loop filter <NUM> may take any number of forms including, for example, type I, II, or III loop filters, most such filters include one or more resistors and one or more capacitors. Exemplary aspects of the present disclosure change these resistances and capacitances to change between the first mode and the second mode. In a first exemplary aspect, variable resistors are used as illustrated in <FIG>. In a second exemplary aspect, switches are used to switch between resistors and/or capacitors having different values as illustrated in <FIG>.

In this regard, <FIG> illustrates a loop filter 94A, with variable capacitors <NUM>(<NUM>)-<NUM>(N) and variable resistors <NUM>(<NUM>)-<NUM>(N). The mode signal <NUM> causes the values of the variable elements to be changed.

Claim 1:
An average power tracking, APT, circuit (<NUM>; <NUM>') comprising:
a digital-to-analog converter, DAC (<NUM>) comprising:
a change signal output (<NUM>) configured to provide a change signal (<NUM>) indicative of a needed change in a voltage control signal, Vcc, (<NUM>); and
a target control voltage signal output (<NUM>);
a transition management circuit (<NUM>) coupled to the change signal output and configured to receive the change signal (<NUM>) and comprising a mode output configured to provide a mode signal (<NUM>) based on the change signal (<NUM>);
a loop filter (<NUM>) coupled to the target control voltage signal output and the mode output, wherein a change in the mode signal causes the loop filter to switch between a first mode and a second mode and wherein the loop filter is configured to provide a signal; and
output circuitry (<NUM>, <NUM>) configured to provide the Vcc based on the signal from the loop filter.