Patent Description:
Imaging arrays having focal plane phase detect (FPPD) pixels are known in the art. FPPD pixels collect light selectively from either left or right side of the camera lens. FPPD pixels are always placed in pairs adjacent to each other. The pairs are distributed over most of the pixel array, typically over about <NUM> percent of the area around the center of the array, leaving the edges clear. The density of the FPPD pixel pairs is a few percent (<NUM>-<NUM>) of the pixels within that central area.

The most common method used to implement FPPD pixels in imaging arrays is to employ metal layers disposed in layers above the sensors to shadow selected portions of the FPPD pixels. <FIG> shows exemplary prior-art FPPD pixel sensors employing metal layers disposed in layers above the sensors to shadow selected portions of the FPPD pixels. <FIG> is a cross-sectional view of a right FPPD pixel sensor 10a and a left FPPD pixel sensor 10b. Pixel sensors 10a and 10b are n-type diffused regions formed in a p-type semiconductor substrate <NUM> as is known in the art. An interlayer dielectric layer <NUM> is formed over the surface of the substrate <NUM> and the pixel sensors 10a and 10b. Microlenses 16a and 16b are formed, respectively, over pixel sensors 10a and 10b. A metal segment 18a is formed and defined over pixel sensor 10a and is positioned to block light from entering on the left side of the pixel sensor 10a. A metal segment 18b is formed and defined over pixel sensor 10b and is positioned to block light from entering on the right side of the pixel sensor 10b.

Another technique that has been suggested for creating FPPD pixel sensors is to deposit an opaque silicide layer over selected portions of the FPPD pixels. <FIG> shows exemplary prior-art FPPD pixel sensors employing an opaque silicide layer over selected portions of the FPPD pixels to shadow selected portions of the FPPD pixels. Many of the features of the pixel sensors are the same in <FIG> and will be identified using the same reference numerals.

<FIG> is a cross-sectional view of a right FPPD pixel sensor 10a and a left FPPD pixel sensor 10b. Pixel sensors 10a and 10b are n-type diffused regions formed in a p-type semiconductor substrate <NUM> as is known in the art. An interlayer dielectric layer <NUM> is formed over the surface of the substrate <NUM> and the pixel sensors 10a and 10b. Microlenses 16a and 16b are formed, respectively, over pixel sensors 10a and 10b. An opaque silicide layer 20a is formed and defined on the surface of the diffused region forming pixel sensor 10a and is positioned to block light from entering on the left side of the pixel sensor 10a. An opaque silicide layer 20b is formed and defined on the surface of the diffused region forming pixel sensor 10b and is positioned to block light from entering on the right side of the pixel sensor 10b. This technique has proved to be unsatisfactory since the silicide layers create significant amounts of leakage current in the FPPD pixels.

As digital cameras become thinner, the angles of light irradiating the individual pixel sensors in the imaging array become larger as measured normal to the surface. Designers have employed several techniques to accommodate these angles.

According to one possible solution, the pixel sensors that make up the array can be increased in size at the cost of decreasing resolution. This is generally not considered to be a satisfactory solution in view of the trend to increase rather than decrease the resolution of digital cameras.

In very small pixel sensors, such as those used for cell-phone camera sensors, a "light pipe" has been employed. This is similar in concept to a fiber optic cable, relying upon total internal reflection (TIR). It therefore requires the use of a high-index polymer as the core of the light pipe. The concept will work well for small incident angles (steep angle of incidence on the sidewall), but it becomes progressively less useful as incident angles increase. According to one particular prior-art light-pipe solution shown in <FIG>, light pipes employing internal reflection at the edges of lenses are positioned over the pixel sensors. Adjacent pixel sensors 10a and 10b are shown formed in p-type substrate (or well) <NUM>. Dielectric layer <NUM> is formed over the pixel sensors 10a and 10b. Lenses 16a and 16b are formed on the surface of the dielectric layer as is known in the art.

Unlike the pixel sensors depicted in <FIG>, vias are formed in the dielectric layer, respectively over and in alignment with pixel sensors 10a and 10b and are both filled with a polymer to form light pipes (indicated at reference numerals 18a and 18b) having a high index of refraction (e.g., n ≅ <NUM>). A layer of material (shown by reference numerals <NUM>) provides total internal reflection is formed at the edges of the lenses 16a and 16b between adjacent pixel areas.

Light rays directed at the surface of the pixel sensor array containing pixel sensors 10a and 10b, two of which are shown symbolically at reference numerals <NUM>. As shown in <FIG>, the light rays bend at the interface of the lenses 16a and 16b. The light rays <NUM> are also shown reflecting from the layer <NUM> at the edges of the lenses. Without the presence of the layers of material <NUM>, these light rays <NUM> would continue along a path that would lead into the next adjacent pixel but the presence of the layer of reflective material <NUM> reflects them back into the pixel area into which they entered.

As the light rays <NUM> continue downward from the lens into the polymer layers 18a and 18b, they are reflected by the interface (shown at reference numerals 26a and 26b) between the respective polymer layers 18a and 18b and the dielectric layer <NUM> (having an index of refraction of about n = <NUM>) in which they are formed. This interface is not <NUM>% reflective and so some of the light shown in dashed lines at reference numerals <NUM> passes through the interface, through the dielectric layer separating the two adjacent pixels, and undesirably into adjacent pixel sensors causing undesirable crosstalk.

Ideally, it would be desirable for a small pixel to have the same acceptance angles as a large pixel without the aforementioned drawbacks of the present solutions. It would also be desirable to provide a light pipe pixel sensor array that both accepts light from relatively large angles and includes FPPD pixels.

<CIT> describes an image sensor for high angular response discrimination. Microlenses associated with phase detection autofocus (PDAF) pixels have a larger optical power than microlenses associated with image capture pixels or comprise a location or shape so a receiving surface of a PDAF pixel has an asymmetric profile.

A pixel sensor array includes a plurality of surface pixel sensors disposed in a substrate, a layer of dielectric material formed over the surface of the pixel sensors, a plurality of apertures formed in the dielectric layer each aligned with one of the surface pixel sensors and having an inner side wall. A lining layer is formed on the inner side wall of each aperture and is substantially fully reflective to visible light. The lining layer is spaced apart from the surface of the substrate and has a smaller cross-sectional area than a cross-sectional area of each surface pixel sensor. A filler material substantially transparent to visible light is disposed inside of the reflective lining layer and has a top surface lying in the plane with the top surface of the layer of dielectric material. A microlens is disposed over the top surface of each aperture. FPPD pixels created by placement of metal layers are placed in pairs adjacent to each other and are distributed over most of the pixel sensor array.

According to an aspect of the invention the pixel sensing layer is a layer of silicon doped with a dopant species having a first conductivity type, and each surface pixel sensing element is a photodiode formed at the surface of the layer of silicon. Each photodiode has an anode formed from a region of silicon doped with a dopant species having a second conductivity type opposite the first conductivity type.

The pixel sensor array also includes at least one subsurface pixel sensing element disposed in the pixel sensing layer below, in alignment with, and insulated from the surface pixel sensing element. In one exemplary embodiment, a first subsurface pixel sensing element is disposed in the pixel sensing layer below, in alignment with, and insulated from the surface pixel sensing element, and a second subsurface pixel sensing element is disposed in the pixel sensing layer below, in alignment with, and insulated from the first subsurface pixel sensing element.

The invention will be explained in more detail in the following with reference to embodiments and to the drawing in which are shown:.

Referring now to <FIG>, a portion <NUM> of an illustrative array of pixel sensors is depicted. <FIG> is a cross sectional view and <FIG> are top views, respectively, of left/right and top/bottom FPPD pixels 32a and 32b in accordance with one aspect of the present invention. The particular pixel sensors depicted in <FIG> are vertical color pixel sensors of the type manufactured and sold by Foveon, Inc. of San Jose, CA. The two vertical color pixel sensors shown in <FIG> are both formed in a p-type substrate (or well) <NUM> and include buried n-type red sensors 34a and 34b, buried n-type green sensors 36a and 36b overlying the red sensors 34a and 34b.

Persons of ordinary skill in the art will appreciate that some vertical color pixel sensors include a single n-type blue surface pixel sensor, and others include blue pixel sensors having multiple segments. An example of a vertical color pixel sensor having blue pixel sensors with multiple segments is found in <CIT>, assigned to Foveon, Inc. and includes four n-type blue surface pixel sensors. Persons of ordinary skill in the art will appreciate that each vertical color pixel sensor in the particular embodiment shown in <FIG> includes two subsurface (buried) pixel sensors disposed at different depths in the substrate or well, buried n-type red sensors 34a and 34b, and buried n-type green sensors 36a and 36b overlying the buried sensors 34a and 34b, but that other embodiments of the invention are contemplated where vertical color pixel sensors each include a single buried pixel sensor or more than two buried pixel sensors at different depths in the substrate or well.

The pixel sensors 32a and 32b in the embodiment of the present invention depicted in <FIG> takes advantage of the layout for a four-segment blue pixel sensor having sensors smaller in area that the areas of the red and green pixel sensors, but includes only a single n-type blue surface pixel sensor B <NUM> (referred to by reference numerals 38a and 38b), that occupies no more than about the same area as two of the four blue pixel sensor segments as most easily seen in <FIG>. If the pixel sensor area is thought of as including four quadrants in cartesian coordinate space (indicated in <FIG>), a left FPPD blue pixel sensor can occupy quadrants II and III, a right FPPD blue pixel sensor can occupy quadrants I and IV, a top FPPD blue pixel sensor can occupy quadrants I and II, and a bottom FPPD blue pixel sensor can occupy quadrants III and IV.

In accordance with this aspect of the present invention, blue surface pixel sensors have smaller areas than regular pixels and are offset to the left, right, top, or bottom portion of the pixel sensor area. The left side of <FIG> shows a left FPPD pixel sensor and the right side of <FIG> shows a right FPPD pixel sensor. If <FIG> is interpreted as being a cross section in the vertical direction rather than the horizontal direction, then the left side of <FIG> shows a top FPPD pixel sensor and the right side of <FIG> shows a bottom FPPD pixel sensor. In cartesian coordinate space, a left FPPD blue pixel sensor occupies quadrants II and III, a right FPPD blue pixel sensor occupies quadrants I and IV, a top FPPD blue pixel sensor occupies quadrants I and II, and a bottom FPPD blue pixel sensor occupies quadrants III and IV.

Persons of ordinary skill in the art will understand that the result shown in <FIG> can be achieved by performing a simple alteration of the blue pixel sensor implant mask in the mask set for fabricating the pixel sensor array to size and position the blue pixel sensor according to whether a left, right, top, or bottom FPPD pixel is to be formed.

In accordance with a similar embodiment, shown in <FIG>, the width of the blue sensor segments that are formed can also be narrowed in accordance with another aspect of the present invention. The amount that the width of the blue sensor can be narrowed will depend on the intensity of the phase difference effect that is desired subject to a limit dictated by minimum signal and signal-to-noise ratio requirements. <FIG> shows a cross-sectional view, <FIG> shows left and right FPPD pixel sensors, and <FIG> shows top and bottom FPPD pixel sensors.

Referring now to <FIG>, a cross-sectional diagram shows a portion <NUM> of an imaging array including a pair of surface pixel sensors 52a and 52b formed on a substrate <NUM>. The substrate is shown in <FIG> as a p-type substrate and the surface pixel sensors 52a and 52b are n-type regions disposed in the p-type substrate forming the anodes of photodiodes as is known in the art, the substrate forming the cathodes of the photodiodes. Persons of ordinary skill in the art will appreciate that the p-type substrate may be a p-well formed in an underlying semiconductor substrate. Such skilled persons will also appreciate that while the portion of the array <NUM> depicted in <FIG> includes only two pixel sensors 52a and 52b, any array actually fabricated according to the principles of the present invention may include an arbitrary number of pixel sensors. Such skilled persons will also appreciate that surface pixel sensors 52a and 52b may be the blue pixel sensor components in vertical color pixel sensors such as X3® vertical color sensors fabricated by Foveon, Inc. Green and red sensors, not shown would be located further into the substrate <NUM> under the pixel sensors 52a and 52b.

A first interlayer dielectric layer <NUM> is formed over the surface of the substrate <NUM> and the n-type regions forming the surface pixel sensors 52a and 52b. Vias are formed to function as light pipes 58a and 58b. as presently preferred, the light pipes 58a and 58b are tapered, having a larger cross-sectional area at top ends 60a and 60b that are planar with the top surface <NUM> of the first interlayer dielectric layer <NUM> than at bottom ends 64a and 64b. The cross-sectional area of the bottom ends 64a and 64b of the light pipes 58a and 58b is smaller than the cross-sectional area of the pixel sensors 52a and 52b and are substantially centered over the pixel sensors 52a and 52b. The bottom ends 64a and 64b of the light pipes 58a and 58b are spaced apart from the top surface of the substrate. Microlenses 66a and 66b focus light into the pixel sensors 52a and 52b as is known in the art.

Although providing a vertical sidewall is conceptually simpler, it has several practical disadvantages. The most important disadvantage is that it limits the view angle at the top of the light pipe, which necessitates a larger pixel size and/or places very stringent restrictions on process control. In view of these disadvantages, a tapered design is preferred.

A process to form the tapered vias forming the light pipes 58a and 58b employs an etch chemistry that includes fluorine (F) to etch the SiO<NUM> and chemistry to create an organic polymer to deposit on the etched sidewall to protect it. The fluorine etches the bottom of the via while the polymer is deposited on its sidewalls to protect them from the etching process. At each interval of time Δt the SiO2 is etched down a distance Δy and a polymer having a thickness Δx is deposited on the sidewall. By controlling the amount of F and polymer, the degree of taper is controlled. Since processes differ from foundry to foundry, routine testing may be employed to achieve the desired degree of taper in any given process.

A typical plasma etch chemistry that may include CF<NUM> which acts as the main source of F, CHF<NUM> which is the main source of hydrocarbon polymers CxHy. CxHyFz, and Ar which acts as a carrier gas and as a source of ions.

The light pipes 58a and 58b are leach lined with reflective lining layers shown at reference numerals 68a and 68b.

The light pipe in the present invention may be formed in one of two ways. According to one aspect of the present invention, where the first interlayer dielectric layer <NUM> is formed from silicon dioxide (SiO<NUM>), the light pipe via may be filled with a filler material that is substantially transparent in the visible spectrum. Examples of suitable filler materials include dielectric materials like SiO<NUM>, or a polymer having an index of refraction higher than the surrounding the first silicon dioxide interlayer dielectric layer <NUM>.

To form a good reflective surface on the sidewall of the light pipes 58a and 58b, the reflective lining layer shown at reference numerals is deposited to line the inner wall of the light pipe must exhibit good reflection over the entire visible wavelength range, i.e., it is preferred that it have a silvery appearance. It is preferred that the reflective lining layer be a metal lining layer and has a smooth surface because rough surfaces are known to scatter light, and what is preferred is a surface having a high specular reflection. The thickness of the metal layer must be sufficient to prevent light from penetrating the sidewall to avoid cross-talk between pixel sensors at larger incident angles and also thick enough to avoid pinhole defects.

In accordance with one aspect of the present invention, an Al-Cu metallization material commonly used in CMOS processes as a metallization interconnect layer has the required properties. Tungsten metallization is also currently in use but has a dull gray appearance and an unacceptably large surface roughness which result in poor reflectivity.

At light wavelengths of <NUM> the theoretical minimum Al-Cu thickness for a light transmission attenuation of 10e6 is about <NUM>, however, this is likely to be insufficient because the resistivity of an Al-Cu thin film may be higher than the bulk resistivity and films having thicknesses in this range are known to have pinholes. It is a minimum thickness for Al-Cu films is at least about <NUM>. Further, because the step coverage of plasma vapor deposited (PVD) Al-Cu is relatively poor, a sputter thickness of about <NUM> at the top ends 60a and 60b is presently preferred, which results in a minimum thickness of about <NUM> at the bottom ends 64a and 64b of the light pipes 58a and 58b.

In one exemplary non-limiting embodiment, the top ends 60a and 60b of the light pipes are chosen to provide a minimum photoresist width between adjacent light pipe openings of <NUM>). In an exemplary embodiment where a pixel sensor size of <NUM> is assumed, this gives a top dimension of <NUM> - <NUM> = <NUM>.

In a tapered light pipe design the bottom of the light pipe has to be smaller than the dimensions of the top surface of the photodiode, which, in a non-limiting example, assumed to be about <NUM> active. As an example, if active enclosure of the light pipe is taken as <NUM>, the bottom width can be determined = <NUM> - <NUM> = <NUM>.

The length of the light pipe is not critical for the optics design, providing considerable freedom to choose it. It is advantageous to have a thicker back-end-of-line (BEOL) for additional metal layers. In one exemplary embodiment, the thickness of the interlayer dielectric layer <NUM> is chosen to be about <NUM>, which allows the inclusion of four metal interconnect layers within the interlayer dielectric layer <NUM>.

Given the above parameters, the sidewall angle will be, nominally, about <NUM>°. Persons of ordinary skill in the art will appreciate that a thicker first interlayer dielectric layer <NUM> will reduce the angle further; however, increasing the thickness of the first interlayer dielectric layer <NUM> from <NUM> to <NUM> only reduces the sidewall angle by <NUM>°, which does not provide much of an advantage, and increases the aspect ratio of the via forming the light pipes 58a and 58b.

A base layer <NUM> is interposed to separate the bottoms of the light pipes 58a and 58b from the surfaces of the pixel sensors 52a and 52b. It would be optically advantageous if the light pipe extended all the way down to the silicon surface. However, this would cause damage in the silicon, result in excess dark current, and may even etch into the silicon. In addition, if the metal material from which the reflective liner is made comes into contact with the upper surface of the pixel sensor, the thermal budget of subsequent process steps will cause metal ions to diffuse into and severely damage the pixel sensor layer, rendering the pixel sensors 52a and 52b inoperative. The base layer is composed of residual SiO<NUM> from the first interlayer dielectric layer that is left unetched below the bottom ends 64a and 64b of the light pipes 58a and 58b, respectively.

If the thickness of the base layer <NUM> is too large, light will be permitted to escape under the metal and fall outside the active areas of the pixel sensors 52a and 52b, especially at larger angles, decreasing the efficiency of the light capture.

In one exemplary embodiment. at an incident angle of <NUM>°, the light entering the light pipe has a maximum angle of <NUM>°. The thickness of the base layer is chosen to allow no more than <NUM>% of light falling outside the active pixel sensor area, allowing for <NUM> of mis-alignment between the active pixel sensor area and the light pipe. Simulations have shown that with zero misalignment between the active pixel sensor area and the light pipe, no light falls outside of the active pixel sensor area and with a misalignment of <NUM> <NUM>% of the light falls outside of the active pixel sensor area. Based on simulation results, a thickness of about <NUM> for the base layer <NUM> has been found to be satisfactory. If a thickness of about <NUM> is used for the base layer <NUM>, simulation results have shown that with zero misalignment between the active pixel sensor area and the light pipe, <NUM>% of the light falls outside of the active pixel sensor area and with a misalignment of <NUM> <NUM>% of the light falls outside of the active pixel sensor area.

A second interlayer dielectric layer <NUM> is disposed over the top of first interlayer dielectric layer <NUM> and the planarized tops of the reflective lining layers 68a and 68b as and the top of the filler material in each of the light pipes 58a and 58b. In one exemplary embodiment, this second interlayer dielectric layer <NUM> may have a thickness of about <NUM> and at that thickness can support two layers of metal interconnect.

A passivation layer <NUM> is formed over the top surface of the second interlayer dielectric layer <NUM> and a planarization layer <NUM> is formed over the top surface of the passivation layer <NUM>. In one exemplary embodiment, the thickness of the passivation layer <NUM> may be about <NUM> and the thickness of the planarization layer <NUM> may be about <NUM>. These layers may be formed from, for example, deposited silicon dioxide.

<FIG> shows a plurality of light rays 78a and 78b entering pixel sensors 52a and 52b through microlenses 66a and 66b respectively. The focal lengths of microlenses 66a and 66b are chosen to position the focal points of the light rays at positions 80a and 80b respectively. Persons of ordinary skill in the art will note that the positions of focal points 80a and 80b are located within the lightpipes 58a and 58b. Accordingly and as may be seen in <FIG>, all incoming light rays 78a and 78b diverging past the focal points 80a and 80b strike the pixel sensors 52a and 52b, either directly or after reflection from the reflective lining layers 68a and 68b.

Referring now to <FIG>, two diagrams illustrate structures for eliminating the effects of flare light in pixel sensor arrays such as the array portion <NUM> of <FIG> in accordance with an embodiment of the present invention. <FIG> is a cross-sectional view of an adjacent pair of lightpipe structures 58a and 58b such as those of <FIG>.

Flare in the lens and camera can result in incident angles for incoming light in the range of from about <NUM>° to about <NUM>°. In conventional optical designs, it is not possible to protect the pixel sensor against flare light, but in accordance with an aspect of the present invention there are some measures that can be taken to suppress flare light. The effect of flare light has to be considered both at the top ends 60a and 60b and at the bottom ends 64a and 64b of the light pipes 58a and 58b. As noted above, at the bottom ends 64a and 64b of the light pipes 58a and 58b, flare can be minimized by using a thin base layer, i.e., a thickness of about <NUM> for a lightpipe having the dimensions recited herein in the exemplary embodiment discussed above. Up to <NUM>% of flare light can fall outside the active pixel sensor area but should not be a problem since the amount of flare light captured in in any single pixel sensor 52a or 52b is a small fraction of total light.

As shown in <FIG>, metal interconnect layer segments 82a, 84a, and 86a form a vertical structure to the left side of lightpipe 58a. Metal interconnect layer segment 82a is formed in the first interlayer dielectric layer <NUM> and metal interconnect layer segments 84a and 86a are formed in the second interlayer dielectric layer <NUM>. Similarly, metal interconnect layer segments 82b, 84b, and 86b form a vertical structure between lightpipes 58a and 58b. Metal interconnect layer segment 82b is formed in the first interlayer dielectric layer <NUM> and metal interconnect layer segments 84b, and 86b are formed in the second interlayer dielectric layer <NUM>. Metal interconnect layer segments 82c, 84c, and 86c form a vertical structure to the right side of lightpipe 58b. Metal interconnect layer segment 82c is formed in the first interlayer dielectric layer <NUM> and metal interconnect layer segments 84c and 86c are formed in the second interlayer dielectric layer <NUM>.

The openings between metal segments 84a, 84b, and 84c define the light-admitting areas for pixel sensors 52a and 52b. In the embodiment shown in <FIG>, the light admitting area is large enough to admit light over the entire surface of each of pixel sensors 52a and 52b. Pixel sensors that are configured to admit light over their entire surfaces may be referred to herein as regular pixel sensors.

Metal interconnect layer segments 82a, 84a, and 86a are all connected together using a plurality of interconnect vias, one of which is shown at reference numeral <NUM>. Metal interconnect layer segments 82b, 84b, and 86b and metal interconnect layer segments 82c, 84c, and 86c are also connected together using a plurality of interconnect vias, one of which is indicated at reference numeral <NUM>.

<FIG> shows a top view of an illustrative one of the vertical structures showing the layout of the interconnect vias <NUM> (using one of metal interconnect segments 82abc, 84abc, or 86abc as an illustrative example). The vias <NUM> are laterally positioned so that flare light indicated by arrows as entering from the left side of <FIG> is effectively blocked from passing between any of the metal interconnect layer segments that make up any of the vertical structures. A path for flare light that is blocked from entering lightpipe 58b from the region above lightpipe 58a is also shown by arrows in <FIG>. These multiple sheets of metal are preferably all tied to Vpix, to suppress noise.

Referring now to <FIG>, a cross-sectional view is presented of a portion of a pixel sensor array <NUM> employing vertical color pixel sensors that are configured as regular pixel sensors like the pixel sensors 52a and 52b in <FIG>. The only difference between the portion of the pixel sensor array <NUM> of <FIG>. and the portion of the pixel sensor array <NUM> is that the pixel sensors include surface blue pixel sensors 52a_blue and 52b_blue, and buried green and red pixel sensors 52a_green and 52b_green and 52a_red and 52b_red, respectively. As in the embodiment shown in FIGS. <FIG>, persons of ordinary skill in the art will appreciate that each vertical color pixel sensor the particular embodiment shown in <FIG> includes two subsurface (buried) pixel sensors, buried green and red pixel sensors 52a_green and 52b_green and 52a_red and 52b_red, but other embodiments of the invention are contemplated having vertical color pixel sensors that include a single buried pixel sensor or more than two buried pixel sensors.

Referring now to <FIG>, a cross-sectional view of a portion <NUM> of a pixel sensor array including a pair of pixel sensors formed under lightpipes 102a and 102b, respectively. Instead of being regular pixel sensors, the pixel sensors depicted in <FIG> are FPPD pixel sensors. The array portion <NUM> is in most respects similar to the array portion <NUM> of <FIG>, and <FIG>. Accordingly, the same reference numerals that were used in <FIG>, and <FIG> will be used to identify the elements of the portion <NUM> in <FIG>. The two differences between the pixel sensors in <FIG>, and the array portion <NUM> of <FIG> and the pixel sensors 102a and 102b of <FIG> is that the metal segment 84a includes a portion <NUM> extending to the right above the left-hand portion of the lightpipe 102a to mask the left side of the blue pixel sensor 58a as shown by dashed vertical axis <NUM> to form a right FPPD pixel sensor. Similarly, the metal segment 84c includes a portion <NUM> extending to the left above the right-hand portion of the lightpipe 102b to mask the right side of the blue pixel sensor 58b as shown by dashed vertical axis <NUM> to form a left FPPD pixel sensor. Persons of ordinary skill in the art will appreciate that the pixel sensors depicted in <FIG> would not be placed adjacent to one another in an array as indicated by separation line <NUM>. Such skilled persons will also appreciate that if the cross section of <FIG> is interpreted to be vertically oriented rather than horizontally oriented, pixel sensors 102a and 102b represent top and bottom FPPD pixel sensors.

Claim 1:
A focal plane phase detecting pixel sensor formed on a substrate (<NUM>) and comprising:
a pixel sensor area comprising four quadrants in cartesian coordinate space centered in the pixel sensor area;
a subsurface pixel sensor (<NUM>) coextensive with the pixel sensor area in the substrate (<NUM>);
a surface pixel sensor (<NUM>) formed in the pixel sensor area of the substrate (<NUM>) and occupying no more than two adjacent quadrants;
a layer of dielectric material (<NUM>), formed over the surface of the substrate (<NUM>);
an aperture (<NUM>) formed in the dielectric layer (<NUM>) and aligned with the surface pixel sensor, the aperture (<NUM>) having an inner side wall;
a reflective lining layer (<NUM>) formed on the inner side wall of the aperture (<NUM>) and spaced apart from the surface of the substrate (<NUM>), the reflective lining layer (<NUM>) being substantially fully reflective to visible light, an inner wall of the reflective lining layer (<NUM>) having a smaller cross-sectional area than the pixel sensor area, a top edge of the inner lining wall of the reflective lining layer (<NUM>) lying in a plane with a top surface of the layer of dielectric material (<NUM>);
a filler material disposed in the aperture inside of the reflective lining layer (<NUM>) and having a top surface lying in the plane with the top surface of the layer of dielectric material (<NUM>), the filler material being substantially transparent to visible light;
a metal layer (<NUM>) disposed over the surface pixel sensor (<NUM>);
a void formed in the metal layer and positioned over the pixel sensor area; and
a microlens (<NUM>) disposed over the void in the metal layer (<NUM>).