Patent Description:
The present disclosure relates generally to a layout structure, and more particularly, to a dummy cell and tap cell layout structure.

A cell device is an integrated circuit (IC) that implements digital logic. Such cell device may be reused multiple times within an application-specific IC (ASIC). An ASIC, such as a system-on-a-chip (SoC) device, may contain thousands to millions of cell devices. A typical IC includes a stack of sequentially formed layers. Each layer may be stacked or overlaid on a prior layer and patterned to form the shapes that define transistors (e.g., field effect transistors (FETs), fin FETs (FinFETs), gate-all-around (GAA) FETs (GAAFETs), and/or other multigate FETs) and connect the transistors into circuits. Cell devices may be arranged based on a particular layout structure. There is currently a need for improved layout structures.

Further attention is drawn to <CIT> describing that in a circuit block, a plurality of cell rows, each being comprised of a plurality of standard cells arranged in a first direction, are arranged in a second direction perpendicular to the first direction, thereby forming a circuit of SOI transistors. The circuit block includes a plurality of antenna cells, each including an antenna diode provided between a power supply line and a substrate or a well. In at least a part of the circuit block, the antenna cells are arranged at constant intervals in at least one of the first and second directions.

Attention is further drawn to <CIT> describing that first and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

Attention is also drawn to <CIT> describing an example circuit which includes: one or more power rails and a tap cell structure. The tap cell structure includes one or more decoupling capacitor cells and one or more tap cells. The one or more tap cells are electrically coupled to the one or more power rails. The one or more decoupling capacitor cells are disposed adjacent to the tap cells and electrically coupled to the one or more power rails.

The present invention is set forth in the independent claim. Further embodiments of the invention are described in the dependent claims.

In an aspect of the disclosure, a metal oxide semiconductor (MOS) IC includes a first circuit and a second circuit. The first circuit includes a first plurality of n-type MOS (nMOS) devices, a first p-type tap (p-tap) cell, and a first dummy nMOS cell. The first plurality of nMOS devices is spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the first plurality of nMOS devices. The first p-tap cell is configured to be coupled to a first voltage source. The second circuit includes a first plurality of p-type MOS (pMOS) devices, a first dummy pMOS cell, and a first n-type tap (n-tap) cell. The first plurality of pMOS devices is adjacent to the first plurality of nMOS devices in a second direction orthogonal to the first direction. The first plurality of pMOS devices is spaced apart in the first direction. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the first plurality of pMOS devices. The first n-tap cell is configured to be coupled to a second voltage source. The first p-tap cell and the first dummy pMOS cell are adjacent to each other in the second direction. The first dummy nMOS cell and the first n-tap cell are adjacent to each other in the second direction.

Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc..

<FIG> is a first diagram <NUM> illustrating a side view of various layers within a cell device and IC. The various layers change in the y direction. As illustrated in <FIG>, a transistor has a gate <NUM> (which may be referred to as POLY in some instances even though the gate may be formed of metal, polysilicon, or a combination of polysilicon and metal), a source <NUM>, and a drain <NUM>. The source <NUM> and the drain <NUM> may be formed by fins. The gate <NUM> may extend in a second direction (e.g., vertical direction along the z axis coming out of the page), and the fins may extend in a first direction orthogonal to the second direction (e.g., horizontal direction along the x axis). A contact layer interconnect <NUM> (also referred to as a metal POLY (MP) layer interconnect, or contact B (CB) layer interconnect) may contact the gate <NUM>. A contact layer interconnect <NUM> (also referred to as a metal diffusion (MD) layer interconnect, or contact A (CA) layer interconnect) may contact the source <NUM> and/or the drain <NUM>. A via <NUM> (also referred to as via A (VA)) may contact the contact layer interconnect <NUM>. A metal <NUM> (M1) layer interconnect <NUM> may contact the via <NUM>. The M1 layer interconnect <NUM> may extend in the first direction only (i.e., unidirectional in the first direction). A via V1 <NUM> may contact the M1 layer interconnect <NUM>. A metal <NUM> (M2) layer interconnect <NUM> may contact the via V1 <NUM>. The M2 layer interconnect <NUM> may extend in the second direction only (i.e., unidirectional in the second direction). Higher layers include a via layer including vias V2 and a metal <NUM> (M3) layer including M3 layer interconnects. The M3 layer interconnects may extend in the first direction. A cell device may be implemented with FinFETs (as illustrated), GAAFETs, or other multigate FETs. For a continuous oxide diffusion (OD) region across multiple devices, the fins are continuous (in the first direction) across the multiple devices. For a discontinuous OD region across multiple devices, the fins are separate at a diffusion break (e.g., single/double diffusion break extending in the second direction) between different sets of the multiple devices.

<FIG> is a second diagram <NUM> illustrating a side view of various layers within a standard cell and IC. The various layers change in the y direction. As illustrated in <FIG>, a transistor has a gate <NUM>, a source <NUM>, and a drain <NUM>. The source <NUM> and the drain <NUM> may be formed by fins. The gate <NUM> may extend in a second direction (e.g., vertical direction along the z axis coming out of the page), and the fins may extend in a first direction orthogonal to the second direction (e.g., horizontal direction along the x axis). A contact layer interconnect <NUM> (also referred to as CB layer interconnect) may contact the gate <NUM>. A contact layer interconnect <NUM> (also referred to as CA layer interconnect) may contact the source <NUM> and/or the drain <NUM>. A via <NUM> (also referred to as via B (VB)) may contact the contact layer interconnect <NUM>. An M1 layer interconnect <NUM> may contact the via <NUM>. The M1 layer interconnect <NUM> may extend in the first direction only (i.e., unidirectional in the first direction). A via V1 <NUM> may contact the M1 layer interconnect <NUM>. An M2 layer interconnect <NUM> may contact the via V1 <NUM>. The M2 layer interconnect <NUM> may extend in the second direction only (i.e., unidirectional in the second direction). Higher layers include a via layer including vias V2 and an M3 layer including M3 layer interconnects. The M3 layer interconnects may extend in the first direction. A cell device may be implemented with FinFETs (as illustrated), GAAFETs, or other multigate FETs. For a continuous OD region across multiple devices, the fins are continuous (in the first direction) across the multiple devices. For a discontinuous OD region across multiple devices, the fins are separate at a diffusion break (e.g., single/double diffusion break extending in the second direction) between different sets of the multiple devices.

<FIG> is a diagram <NUM> conceptually illustrating a top-view of a tap cell layout structure. A cell device may include pMOS devices and/or nMOS devices. The nMOS devices include n-type doped (n+) source and drain regions. The n+ source and drain regions may be referred to as n-plus (NP) implant layers. Each set of nMOS devices is illustrated by an NP layer with an OD layer on the NP layer. The pMOS devices include p-type doped (p+) source and drain regions. The p+ source and drain regions may be referred to as p-plus (PP) implant layers. Each set of pMOS devices is illustrated by a PP layer with an OD layer on the PP layer. Of an IC, tap cells (also referred to as guard tap cells) may be located adjacent to a set of pMOS devices and to a set of nMOS devices to provide body connections to the pMOS devices and to the nMOS devices, respectively. A p-tap cell includes a p-type doped (p+) region and provides a body connection for a set of nMOS devices. The p+ region of the p-tap cell may be referred to as a PP implant layer. Each p-tap cell is illustrated by a PP layer with an OD layer on the PP layer. An n-tap cell includes an n-type doped (n+) region and provides a body connection for a set of pMOS devices. The n+ region of the n-tap cell may be referred to as an NP implant layer. Each n-tap cell is illustrated by an NP layer with an OD layer on the NP layer. A set of pMOS devices and adjacent n-tap cells may be within an n-type well (n-well), assuming the IC is implemented with a p-type substrate.

For some fabrication processes, design rule check (DRC) violations may be encountered at corner areas <NUM> (see markers within the circles <NUM> illustrating the four-corner areas, with PP,NP, PP,NP layers meeting at each corner) of the NP layers and PP layers, where PP layers of a set of pMOS devices and a p-tap cell are diagonal from each other and NP layers of a set of nMOS devices and an n-tap cell are diagonal from each other. Specifically, the four-corner areas are defined by <NUM>° edges of an nMOS device (NP), a p-tap cell (PP), an n-tap cell (NP), and a pMOS device (PP) all meeting at one corner. The DRC violations may occur for the illustrated corner case abutment of nMOS devices, pMOS devices, and corresponding tap cells, and may report width and spacing errors in association with the corner case abutment of the NP/PP layers. To avoid such DRC violations, a dummy cell and tap cell layout structure is provided below with respect to <FIG>.

<FIG> is a first diagram <NUM> conceptually illustrating a top-view of a dummy cell and tap cell layout structure. The illustrated dummy cell and tap cell layout structure is a subsection of a larger layout structure, where the pattern illustrated may be repeated The illustrated dummy cell and tap cell layout structure includes four columns of devices/cells, including a first column <NUM> of active devices, a second column <NUM> of PP implant cells including dummy pMOS cells (P-D) / p-tap cells (P-T), a third column <NUM> of NP implant cells including dummy nMOS cells (N-D) / n-tap cells (N-T), and a fourth column <NUM> of active devices. The active devices in the columns <NUM>, <NUM> include both nMOS devices <NUM> and pMOS devices <NUM>. In an alternative configuration, the columns <NUM>, <NUM> may be swapped, with the NP implant cells in the second column <NUM> and the PP implant cells in the third column <NUM>. Such a layout structure can be obtained by flipping / mirroring the illustrated layout structure, or rotating the illustrated layout structure clockwise/counterclockwise by <NUM>°. The active devices in the columns <NUM>, <NUM> are illustrated with pairs of adjacent nMOS devices <NUM> interleaved with pairs of adjacent pMOS devices <NUM>. Generally, each row of active devices may include n adjacent nMOS devices <NUM> interleaved with m adjacent pMOS devices <NUM>, where n ≥ <NUM> and m ≥ <NUM> (see <FIG>). In the illustrated dummy cell and tap cell layout structure, n = <NUM> and m = <NUM>.

As illustrated in the dummy cell and tap cell layout structure, a dummy nMOS cell <NUM> is located adjacent to each p-tap cell <NUM>, and a dummy pMOS cell <NUM> is located adjacent to each n-tap cell <NUM>, where cells with PP layers are in one column and cells with NP layers are in an adjacent column. Through placement of the dummy nMOS cells <NUM> and the dummy pMOS cells <NUM> within the layout structure, the four-corner areas (see <NUM>) with the PP, NP, PP, NP layers meeting at one corner can be avoided. Accordingly, by avoiding such four-corner areas, associated DRC violations can be avoided. Avoid DRC violations can improve the yield of corresponding fabricated MOS ICs and performance of the fabricated MOS ICs.

<FIG> is a second diagram <NUM> conceptually illustrating a top-view of a dummy cell and tap cell layout structure. As illustrated in <FIG>, the addition of the dummy pMOS cells <NUM> and dummy nMOS cells <NUM> within the layout structure as illustrated in <FIG> provides a layout structure that excludes the four-corner areas of the NP/PP layers. As illustrated by the arrows in <FIG>, the PP/NP layers each have a C-shape within the layout structure. Four-corner areas of the NP/PP layers are non-existent in the configuration.

<FIG> is a first diagram <NUM> conceptually illustrating a top-view of a first configuration of a dummy cell and tap cell layout structure. <FIG> is a second diagram <NUM> conceptually illustrating a top-view of the first configuration of a dummy cell and tap cell layout structure. The first and second diagrams <NUM>, <NUM> illustrate a MOS IC. The MOS IC includes circuits <NUM> - <NUM>. The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in a first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to a first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In one example, the first voltage source is configured to provide the voltage Vss.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in a second direction orthogonal to the first direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to a second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In one example, the second voltage source is configured to provide the voltage Vdd. The p-tap cell <NUM> and the dummy pMOS cell <NUM> are adjacent to each other in the second direction. The dummy nMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the second direction.

The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is adjacent to the plurality of pMOS devices <NUM>/<NUM> in the second direction. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in the first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to the first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. The dummy pMOS cell <NUM> and the p-tap cell <NUM> are adjacent to each other in the second direction. The n-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the second direction.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in the second direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to the second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. The p-tap cell <NUM> and the dummy pMOS cell <NUM> are adjacent to each other in the second direction. The dummy nMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the second direction.

The dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. Likewise, the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. The second voltage source, for example Vdd, may be configured to provide a higher voltage than the first voltage source, for example Vss. As can be appreciated in <FIG>, an area of each of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>; and the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> is approximately equal. OD regions (shown in <FIG> by the inner rectangle within each device/cell; may also be referred to as OD islands in this case) of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>; and the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> are separate and discontinuous with respect to each other.

Referring to <FIG>, the NP layers of the nMOS devices, dummy nMOS cells, and n-tap cells form C-shapes <NUM>, <NUM> around PP layers of pMOS devices, and the PP layers of the pMOS devices, dummy pMOS cells, and p-tap cells form C-shapes <NUM>, <NUM> around NP layers of nMOS devices. The dummy cell and tap cell layout structure excludes corner case abutment of four-corner areas of adjoining NP, PP, NP, PP layers, and consequently, avoids DRC violations in association with such corner case abutment.

The dummy cell and tap cell layout structure discussed in relation to <FIG>, <FIG>, include dummy nMOS/pMOS cells that change the configuration of the NP/PP layers in order to exclude corner case abutment of NP, PP, NP, PP four-corner areas. The addition of the dummy nMOS/pMOS cells increases an overall area of the IC. Several alternative configurations of the dummy cell and tap cell layout structure that may reduce the amount of area utilized by the dummy cells are provided below with respect to <FIG>, <FIG>, <FIG>.

<FIG> is a diagram <NUM> conceptually illustrating a top-view of a second configuration of a dummy cell and tap cell layout structure. In <FIG>, the dummy nMOS/pMOS cells are reduced in width and the adjacent p-tap cells and n-tap cells are enlarged in width by the same amount as the reduction in width of the dummy nMOS/pMOS cells. Providing a larger OD area for the tap cell body connections may provide some performance improvements in some configurations. The diagram <NUM> illustrates a MOS IC. The MOS IC includes circuits <NUM> - <NUM>. The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in a first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to a first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In one example, the first voltage source is configured to provide the voltage Vss.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in a second direction orthogonal to the first direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to a second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In one example, the second voltage source is configured to provide the voltage Vdd. In this configuration, the p-tap cell <NUM> is adjacent to both the dummy pMOS cell <NUM> and the n-tap cell <NUM> in the second direction. In addition, the n-tap cell <NUM> is adjacent to both the p-tap cell <NUM> and the dummy nMOS cell <NUM> in the second direction. Further, the nMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the dummy pMOS cell <NUM> and the n-tap cell <NUM>, and the pMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the p-tap cell <NUM> and the dummy nMOS cell <NUM>.

The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is adjacent to the plurality of pMOS devices <NUM>/<NUM> in the second direction. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in the first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to the first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In this configuration, the n-tap cell <NUM> is adjacent to both the p-tap cell <NUM> and the dummy nMOS cell <NUM> in the second direction. In addition, the p-tap cell <NUM> is adjacent to both the dummy pMOS cell <NUM> and the n-tap cell <NUM> in the second direction. Further, the pMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the p-tap cell <NUM> and the dummy nMOS cell <NUM>, and the nMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the dummy pMOS cell <NUM> and the n-tap cell <NUM>.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in the second direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to the second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In this configuration, the p-tap cell <NUM> is adjacent to both the dummy pMOS cell <NUM> and the n-tap cell <NUM> in the second direction. In addition, the n-tap cell <NUM> is adjacent to both the p-tap cell <NUM> and the dummy nMOS cell <NUM> in the second direction. Further, the nMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the dummy pMOS cell <NUM> and the n-tap cell <NUM>, and the pMOS devices <NUM>/<NUM> are non-adjacent in the second direction to the p-tap cell <NUM> and the dummy nMOS cell <NUM>.

The dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. Likewise, the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. The second voltage source, for example Vdd, may be configured to provide a higher voltage than the first voltage source, for example Vss. As can be appreciated in <FIG>, an area of each of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM> is greater than an area of each of the dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM>. In addition, an area of each of the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> is greater than an area of each of the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>. OD regions (shown in <FIG> by the inner rectangle within each device/cell; may also be referred to as OD islands in this case) of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>; and the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> are separate and discontinuous with respect to each other.

The dummy cell and tap cell layout structure discussed in relation to <FIG>, includes dummy nMOS/pMOS cells that change the configuration of the NP/PP layers in order to exclude corner case abutment of NP, PP, NP, PP four-corner areas. The addition of the dummy nMOS/pMOS cells increases an overall area of the IC. However, the area utilized by the dummy nMOS/pMOS cells is reduced by reducing a width of the dummy nMOS/pMOS cells as compared the dummy nMOS/pMOS cells in the layout structure discussed in relation to <FIG>. Further, the n-tap cells are enlarged by the same width reduced from the dummy nMOS/pMOS cells, providing a larger OD area for the nMOS/pMOS device body connections, which may provide some performance improvements in some configurations.

<FIG> is a diagram <NUM> conceptually illustrating a top-view of a third configuration of a dummy cell and tap cell layout structure. In <FIG>, the dummy nMOS/pMO S cells are reduced in width and the adjacent nMOS/pMOS devices are enlarged in width by the same amount as the reduction in width of the dummy nMOS/pMOS cells. Providing a larger OD area for the active nMOS/pMOS devices may provide some performance improvements in some configurations. The diagram <NUM> illustrates a MOS IC. The MOS IC includes circuits <NUM> - <NUM>. The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in a first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to a first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In one example, the first voltage source is configured to provide the voltage Vss.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in a second direction orthogonal to the first direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to a second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In one example, the second voltage source is configured to provide the voltage Vdd. In this configuration, the p-tap cell <NUM> is adjacent in the second direction to both the dummy pMOS cell <NUM> and the pMOS device <NUM>. In addition, the n-tap cell <NUM> is adjacent in the second direction to both the dummy nMOS cell <NUM> and the nMOS device <NUM>.

The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is adjacent to the plurality of pMOS devices <NUM>/<NUM> in the second direction. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in the first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to the first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In this configuration, the n-tap cell <NUM> is adjacent in the second direction to both the dummy nMOS cell <NUM> and the nMOS device <NUM>. In addition, the p-tap cell <NUM> is adjacent in the second direction to both the dummy pMOS cell <NUM> and the pMOS device <NUM>.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in the second direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to the second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In this configuration, the p-tap cell <NUM> is adjacent in the second direction to both the dummy pMOS cell <NUM> and the pMOS device <NUM>. In addition, the n-tap cell <NUM> is adjacent in the second direction to both the dummy nMOS cell <NUM> and the nMOS device <NUM>.

The dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. Likewise, the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. The second voltage source, for example Vdd, may be configured to provide a higher voltage than the first voltage source, for example Vss. As can be appreciated in <FIG>, an area of each of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM> is greater than an area of each of the dummy nMO S cells <NUM>, <NUM>, <NUM>, <NUM>. In addition, an area of each of the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> is greater than an area of each of the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>. OD regions (shown in <FIG> by the inner rectangle within each device/cell; may also be referred to as OD islands in this case) of the p-tap cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM>; the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM>; and the n-tap cells <NUM>, <NUM>, <NUM>, <NUM> are separate and discontinuous with respect to each other.

The dummy cell and tap cell layout structure discussed in relation to <FIG>, includes dummy nMOS/pMOS cells that change the configuration of the NP/PP layers in order to exclude corner case abutment of NP, PP, NP, PP four-corner areas. The addition of the dummy nMOS/pMOS cells increases an overall area of the IC. However, the area utilized by the dummy nMOS/pMOS cells is reduced by reducing a width of the dummy nMOS/pMOS cells as compared the dummy nMOS/pMOS cells in the layout structure discussed in relation to <FIG>. Further, the adjacent nMOS/pMOS devices are enlarged by the same width reduced from the dummy nMOS/pMOS cells, providing a larger OD area for the nMOS/pMOS devices, which may provide some performance improvements in some configurations.

The dummy cell and layout structure discussed in relation to <FIG>, <FIG>, avoids the corner case abutment of NP, PP, NP, PP four-corner areas, but the implant is unbalanced, as evidenced by the <NUM>nd and <NUM>rd columns of dummy/tap cells having a jagged boundary of the NP/PP layers. Having an unbalanced implant may potentially cause manufacturing yield issues. An alternative configuration is provided with respect to <FIG> that provides a balanced implant while also avoiding the corner case abutment of NP, PP, NP, PP four-corner areas.

<FIG> is a diagram <NUM> conceptually illustrating a top-view of a fourth configuration of a dummy cell and tap cell layout structure. In <FIG>, the dummy nMOS cells have a continuous OD region with adjacent nMOS devices, and the dummy pMOS cells have a continuous OD region with adjacent pMOS devices. Providing for a continuous OD region of the active devices and dummy nMOS/pMO S cells may also provide some performance improvements in some configurations, as the active devices may have more OD area to utilize for performing the designed functions without taking up space for diffusion breaks. The MOS IC includes circuits <NUM> - <NUM>. The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in a first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to a first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. In one example, the first voltage source is configured to provide the voltage Vss. The nMOS device <NUM> and the dummy nMOS cell <NUM> have a continuous OD region in the first direction.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in a second direction orthogonal to the first direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to a second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. In one example, the second voltage source is configured to provide the voltage Vdd. The p-tap cell <NUM> and the dummy pMOS cell <NUM> are adjacent to each other in the second direction. The dummy nMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the second direction. The pMOS device <NUM> and the dummy pMOS cell <NUM> have a continuous OD region in the first direction.

The circuit <NUM> includes a plurality of nMOS devices <NUM>/<NUM>, a p-tap cell <NUM>, and a dummy nMOS cell <NUM>. The plurality of nMOS devices <NUM>/<NUM> is adjacent to the plurality of pMOS devices <NUM>/<NUM> in the second direction. The plurality of nMOS devices <NUM>/<NUM> is spaced apart in the first direction. The p-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the first direction between the plurality of nMOS devices <NUM>/<NUM>. The p-tap cell <NUM> is configured to be coupled to the first voltage source. The p-tap cell <NUM> provides a body connection for the plurality of nMOS devices <NUM>/<NUM>. The dummy pMOS cell <NUM> and the p-tap cell <NUM> are adjacent to each other in the second direction. The n-tap cell <NUM> and the dummy nMOS cell <NUM> are adjacent to each other in the second direction. The nMOS device <NUM> and the dummy nMOS cell <NUM> have a continuous OD region in the first direction.

The circuit <NUM> includes a plurality of pMOS devices <NUM>/<NUM>, a dummy pMOS cell <NUM>, and an n-tap cell <NUM>. Assuming the IC is implemented with a p-type substrate, the circuit <NUM> is located within an n-well on the p-type substrate. The plurality of pMOS devices <NUM>/<NUM> is adjacent to the plurality of nMOS devices <NUM>/<NUM> in the second direction. The plurality of pMOS devices <NUM>/<NUM> is spaced apart in the first direction. The dummy pMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the first direction between the plurality of pMOS devices <NUM>/<NUM>. The n-tap cell <NUM> is configured to be coupled to the second voltage source. The n-tap cell <NUM> provides a body connection for the plurality of pMOS devices <NUM>/<NUM>. The p-tap cell <NUM> and the dummy pMOS cell <NUM> are adjacent to each other in the second direction. The dummy nMOS cell <NUM> and the n-tap cell <NUM> are adjacent to each other in the second direction. The pMOS device <NUM> and the dummy pMOS cell <NUM> have a continuous OD region in the first direction.

The dummy nMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. Likewise, the dummy pMOS cells <NUM>, <NUM>, <NUM>, <NUM> may be configured to be floating, coupled to the first voltage source, or coupled to the second voltage source. The second voltage source, for example Vdd, may be configured to provide a higher voltage than the first voltage source, for example Vss. OD regions for each dummy nMOS/pMOS cell in each circuit <NUM> - <NUM> is continuous with the OD region of the adjacent nMOS/pMOS device in the first direction. Accordingly, each dummy nMOS cell has a continuous OD region with the corresponding adjacent nMOS device, and each dummy pMOS cell has a continuous OD region with the corresponding adjacent pMOS device.

The dummy cell and tap cell layout structure discussed in relation to <FIG>, includes dummy nMOS/pMOS cells that change the configuration of the NP/PP layers in order to exclude corner case abutment of NP, PP, NP, PP four-corner areas. The addition of the dummy nMOS/pMOS cells increases an overall area of the IC. However, the area utilized by the dummy nMOS/pMOS cells is reduced as compared to the dummy cell and tap cell layout structure in <FIG> through the use of continuous OD regions for the dummy cells and adjacent active devices. Accordingly, the dummy cell and tap cell layout structure of <FIG> may provide a larger OD area for the nMOS/pMO S devices due to the absence of diffusion breaks than that provided by <FIG>, and the larger OD area for the nMOS/pMOS devices may provide some performance improvements in some configurations.

<FIG> is a third diagram <NUM> conceptually illustrating a top-view of a dummy cell and tap cell layout structure. Each of the plurality of nMOS devices in a circuit may include n rows of nMOS devices, where n ≥ <NUM>, and each of the plurality of pMOS devices in a circuit may include m rows of pMOS devices, where m ≥ <NUM>. In one example, m may be equal to n. In addition, each p-tap cell in a circuit may include n rows of p-tap cells, and each dummy nMOS cell may include n rows of dummy nMOS cells. Further, each dummy pMOS cell may include m rows of dummy pMOS cells, and each n-tap cell may include m rows of n-tap cells. Referring to <FIG>, <FIG>, m=<NUM> and n=<NUM>. Referring to <FIG>, each circuit of nMOS devices, p-tap cell, and dummy nMOS cell includes n rows, and each circuit of pMOS devices, n-tap cell, and dummy pMOS cell includes m rows. In one example, m is equal to n for <FIG>. However, m and n may be unequal in other configurations.

Referring again to <FIG>, a MOS IC includes a first circuit (<NUM>, <NUM>, <NUM>, <NUM>) including a first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>), and a first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>). The first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in a first direction. The first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to a first voltage source. The MOS IC further includes a second circuit (<NUM>, <NUM>, <NUM>, <NUM>) including a first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>), and a first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>). The first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is adjacent to the first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) in a second direction orthogonal to the first direction. The first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in the first direction. The first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to a second voltage source. The first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction.

In one configuration, the MOS IC may further include a third circuit (<NUM>, <NUM>, <NUM>, <NUM>) including a second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>), and a second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>). The second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in the first direction. The second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is adjacent to the first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) in the second direction. The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to the first voltage source.

In one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) includes a first set of nMOS devices (<NUM>) and a second set of nMOS devices (<NUM>). The first plurality of pMOS devices (<NUM>/<NUM>) includes a first set of pMOS devices (<NUM>) and a second set of pMOS devices (<NUM>). The second plurality of nMOS devices (<NUM>/<NUM>) includes a third set of nMOS devices (<NUM>) and a fourth set of nMOS devices (<NUM>). The second set of nMOS devices (<NUM>), the first dummy nMOS cell (<NUM>), the first n-tap cell (<NUM>), the second dummy nMOS cell (<NUM>), and the fourth set of nMOS devices (<NUM>) form an n-type C-shape (<NUM>) on the MOS IC with the second set of pMOS devices (<NUM>) located within the n-type C-shape (<NUM>). Note that the NP/PP layers form C-shapes <NUM>, <NUM>, <NUM>, <NUM> in each of the configurations in association with <FIG>, <FIG>, <FIG>, <FIG>.

In one configuration, the MOS IC may further include a fourth circuit (<NUM>, <NUM>, <NUM>, <NUM>) including a second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>), and a second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>). The second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in the first direction. The second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is adjacent to the second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) in the second direction. The second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to the second voltage source.

In one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) includes a first set of nMOS devices (<NUM>) and a second set of nMOS devices (<NUM>). The first plurality of pMOS devices (<NUM>/<NUM>) includes a first set of pMOS devices (<NUM>) and a second set of pMOS devices (<NUM>). The second plurality of nMOS devices (<NUM>/<NUM>) includes a third set of nMOS devices (<NUM>) and a fourth set of nMOS devices (<NUM>). The second plurality of pMOS devices (<NUM>/<NUM>) includes a third set of pMOS devices (<NUM>) and a fourth set of pMOS devices (<NUM>). The second set of nMOS devices (<NUM>), the first dummy nMOS cell (<NUM>), the first n-tap cell (<NUM>), the second dummy nMOS cell (<NUM>), and the fourth set of nMOS devices (<NUM>) form an n-type C-shape (<NUM>) on the MOS IC with the second set of pMOS devices (<NUM>) located within the n-type C-shape (<NUM>), The first set of pMOS devices (<NUM>), the first dummy pMOS cell (<NUM>), the second p-tap cell (<NUM>), the second dummy pMOS cell (<NUM>), and the third set of pMOS devices (<NUM>) form a p-type C-shape (<NUM>) on the MOS IC with the third set of nMOS devices (<NUM>) located within the p-type C-shape (<NUM>). Note that the NP/PP layers form C-shapes <NUM>, <NUM>, <NUM>, <NUM> in each of the configurations in association with <FIG>, <FIG>, <FIG>, <FIG>.

In one configuration, the MOS IC further includes a third circuit including a second plurality ofpMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>), and a second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>). The second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in the first direction. The second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is adjacent to the first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) in the second direction. The second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to the second voltage source.

In one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) includes a first set of nMOS devices (<NUM>) and a second set of nMOS devices (<NUM>). The first plurality of pMOS devices (<NUM>/<NUM>) includes a first set of pMOS devices (<NUM>) and a second set of pMOS devices (<NUM>). The second plurality ofpMOS devices (<NUM>/<NUM>) includes a third set of pMOS devices (<NUM>) and a fourth set of pMOS devices (<NUM>). The first set of pMOS devices (<NUM>), the first dummy pMOS cell (<NUM>), the first p-tap cell (<NUM>), the second dummy pMOS cell (<NUM>), and the third set of pMOS devices (<NUM>) form a p-type C-shape (<NUM>) on the MOS IC with the first set of nMOS devices (<NUM>) located within the p-type C-shape (<NUM>). Note that the NP/PP layers form C-shapes <NUM>, <NUM>, <NUM>, <NUM> in each of the configurations in association with <FIG>, <FIG>, <FIG>, <FIG>.

In one configuration, the MOS IC further includes a fourth circuit including a second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>), a second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>), and a second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>). The second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is spaced apart in the first direction. The second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) is adjacent to the second plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) in the second direction. The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the first direction between the second plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>). The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) and the second n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) are adjacent to each other in the second direction. The second p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be coupled to the first voltage source.

In one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) includes a first set of nMOS devices (<NUM>) and a second set of nMOS devices (<NUM>). The first plurality of pMOS devices (<NUM>/<NUM>) includes a first set of pMOS devices (<NUM>) and a second set of pMOS devices (<NUM>). The second plurality of pMOS devices (<NUM>/<NUM>) includes a third set of pMOS devices (<NUM>) and a fourth set of pMOS devices (<NUM>). The second plurality of nMOS devices (<NUM>/<NUM>) includes a third set of nMOS devices (<NUM>) and a fourth set of nMOS devices (<NUM>). The first set of pMOS devices (<NUM>), the first dummy pMOS cell (<NUM>), the first p-tap cell (<NUM>), the second dummy pMOS cell (<NUM>), and the third set of pMOS devices (<NUM>) form a p-type C-shape (<NUM>) on the MOS IC with the first set of nMOS devices (<NUM>) located within the p-type C-shape (<NUM>). The second set of nMOS devices (<NUM>), the first dummy nMOS cell (<NUM>), the second n-tap cell (<NUM>), the second dummy nMOS cell (<NUM>), and the fourth set of nMOS devices (<NUM>) form an n-type C-shape (<NUM>) on the MOS IC with the fourth set of pMOS devices (<NUM>) located within the n-type C-shape (<NUM>). Note that the NP/PP layers form C-shapes <NUM>, <NUM>, <NUM>, <NUM> in each of the configurations in association with <FIG>, <FIG>, <FIG>, <FIG>.

In one configuration, the first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be one of floating, coupled to the first voltage source, and coupled to the second voltage source. In one configuration, the first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) is configured to be one of floating, coupled to the first voltage source, and coupled to the second voltage source.

Referring to <FIG>, in one configuration, an area of each of the first p-tap cell (<NUM>), the first dummy nMOS cell (<NUM>), the first dummy pMOS cell (<NUM>), and the first n-tap cell (<NUM>) is approximately equal.

Referring to <FIG>, <FIG>, in one configuration, an area of the first p-tap cell (<NUM>, <NUM>) and the first n-tap cell (<NUM>, <NUM>) is greater than an area of the first dummy pMOS cell (<NUM>, <NUM>) and the first dummy nMOS cell (<NUM>, <NUM>). Referring to <FIG>, in one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) are non-adjacent the first dummy pMOS cell (<NUM>) and the first n-tap cell (<NUM>) in the second direction, and the first plurality of pMOS devices (<NUM>/<NUM>) are non-adjacent the first p-tap cell (<NUM>) and the first dummy nMOS cell (<NUM>) in the second direction. Referring to <FIG>, in one configuration, at least one nMOS device (<NUM>) of the first plurality of nMOS devices (<NUM>/<NUM>) is adjacent to the first n-tap cell (<NUM>) in the second direction, and at least one pMOS device (<NUM>) of the first plurality of pMOS devices (<NUM>/<NUM>) is adjacent to the first p-tap cell (<NUM>) in the second direction.

Referring to <FIG>, in one configuration, the first plurality of nMOS devices (<NUM>/<NUM>) includes a first set of nMOS devices (<NUM>) and a second set of nMOS devices (<NUM>), and the first dummy nMOS cell (<NUM>) and the second set of nMOS devices (<NUM>) have a continuous OD region in the first direction.

Referring to <FIG>, in one configuration, the first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) includes a first set of nMOS devices (<NUM>, <NUM>, <NUM>) and a second set of nMOS devices (<NUM>, <NUM>, <NUM>), and an OD region of the first dummy nMOS cell (<NUM>, <NUM>, <NUM>) and an OD region of the second set of nMOS devices (<NUM>, <NUM>, <NUM>) are discontinuous in the first direction with respect to each other.

Referring to <FIG>, in one configuration, the first plurality of pMOS devices (<NUM>/<NUM>) includes a first set of pMOS devices (<NUM>) and a second set of pMOS devices (<NUM>), and the first set of pMOS devices (<NUM>) and the first dummy pMOS cell (<NUM>) have a continuous OD region in the first direction.

Referring to <FIG>, in one configuration, the first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) includes a first set of pMOS devices (<NUM>, <NUM>, <NUM>) and a second set of pMOS devices (<NUM>, <NUM>, <NUM>), and an OD region of the first set of pMOS devices (<NUM>, <NUM>, <NUM>) and an OD region of the first dummy pMOS cell (<NUM>, <NUM>, <NUM>) are discontinuous in the first direction with respect to each other.

In one configuration, the second voltage source is higher than the first voltage source.

In one configuration, the first plurality of nMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) includes a first set of nMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) and a second set of nMOS devices (<NUM>, <NUM>, <NUM>, <NUM>). As illustrated in <FIG>, the first set of nMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) and the second set of nMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) each includes n rows of nMOS devices, where n ≥ <NUM>. The first plurality of pMOS devices (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) includes a first set of pMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) and a second set of pMOS devices (<NUM>, <NUM>, <NUM>, <NUM>). As illustrated in <FIG>, the first set of pMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) and the second set of pMOS devices (<NUM>, <NUM>, <NUM>, <NUM>) each includes m rows of pMOS devices, where m ≥ <NUM>. In one configuration, m is equal to n.

In one configuration, the first p-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) includes n rows of p-tap cells, and the first dummy nMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) includes n rows of dummy nMOS cells. In one configuration, the first dummy pMOS cell (<NUM>, <NUM>, <NUM>, <NUM>) includes m rows of dummy pMOS cells, and the first n-tap cell (<NUM>, <NUM>, <NUM>, <NUM>) includes m rows of n-tap cells.

As discussed above, for some fabrication processes, DRC violations may be encountered at four-corner areas where, clockwise or counterclockwise, NP, PP, NP, PP layers meet at one corner with <NUM>° edges. With respect to <FIG>, multiple configurations of a dummy cell and tap cell layout structure are provided that avoid the corner case abutment DRC violations. Each of the multiple configurations of the dummy cell and tap cell layout structure include dummy nMOS/pMOS cells that, while increasing an overall size of the IC, also provide NP/PP layers in a configuration that avoid the corner case abutment DRC violations. By avoiding the corner case abutment DRC violations, yield/performance may be improved of corresponding fabricated MOS ICs.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

Claim 1:
A metal oxide semiconductor, MOS, integrated circuit, IC, comprising:
a first circuit including a first plurality of n-type MOS, nMOS, devices (<NUM>), a first p-type tap, p-tap, cell (<NUM>), and a first dummy nMOS cell (<NUM>), the first plurality of nMOS devices being spaced apart in a first direction, the first p-tap cell (<NUM>) and the first dummy nMOS cell (<NUM>) being adjacent to each other in the first direction between the first plurality of nMOS devices (<NUM>), the first p-tap cell (<NUM>) being configured to be coupled to a first voltage source; and
a second circuit including a first plurality of p-type MOS, pMOS, devices (<NUM>), a first dummy pMOS cell (<NUM>), and a first n-type tap, n-tap, cell (<NUM>), the first plurality of pMOS devices (<NUM>) being adjacent to the first plurality of nMOS devices (<NUM>) in a second direction orthogonal to the first direction, the first plurality of pMOS devices (<NUM>) being spaced apart in the first direction, the first dummy pMOS cell (<NUM>) and the first n-tap cell (<NUM>) being adjacent to each other in the first direction between the first plurality of pMOS devices (<NUM>), the first n-tap cell (<NUM>) being configured to be coupled to a second voltage source,
characterised in that
the first p-tap cell (<NUM>) and the first dummy pMOS cell (<NUM>) are +t+T adjacent to each other in the second direction, and in that
the first dummy nMOS cell (<NUM>) and the first n-tap cell (<NUM>) are adjacent to each other in the second direction.