Patent Description:
A prior art non-volatile memory cell <NUM> is shown in <FIG>. The memory cell <NUM> comprises a semiconductor substrate <NUM> of a first conductivity type, such as P type. The substrate <NUM> has a surface on which there is formed a first region <NUM> (also known as the source line SL) of a second conductivity type, such as N type. A second region <NUM> (also known as the drain line) also of N type is formed on the surface of the substrate <NUM>. Between the first region <NUM> and the second region <NUM> is a channel region <NUM>. A bit line BL <NUM> is connected to the second region <NUM>. A word line WL <NUM> is positioned above a first portion of the channel region <NUM> and is insulated therefrom. The word line <NUM> has little or no overlap with the second region <NUM>. A floating gate FG <NUM> is over another portion of the channel region <NUM>. The floating gate <NUM> is insulated therefrom, and is adjacent to the word line <NUM>. The floating gate <NUM> is also adjacent to the first region <NUM>. The floating gate <NUM> may overlap the first region <NUM> to provide coupling from the region <NUM> into the floating gate <NUM>. A coupling gate CG (also known as control gate) <NUM> is over the floating gate <NUM> and is insulated therefrom. An erase gate EG <NUM> is over the first region <NUM> and is adjacent to the floating gate <NUM> and the coupling gate <NUM> and is insulated therefrom. The top corner of the floating gate <NUM> may point toward the inside corner of the T-shaped erase gate <NUM> to enhance erase efficiency. The erase gate <NUM> is also insulated from the first region <NUM>. The cell <NUM> is more particularly described in <CIT>.

One exemplary operation for erase and program of prior art non-volatile memory cell <NUM> is as follows. The cell <NUM> is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate <NUM> with other terminals equal to zero volt. Electrons tunnel from the floating gate <NUM> into the erase gate <NUM> causing the floating gate <NUM> to be positively charged, turning on the cell <NUM> in a read condition. The resulting cell erased state is known as '<NUM>' state. The cell <NUM> is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate <NUM>, a high voltage on the source line <NUM>, a medium voltage on the erase gate <NUM>, and a programming current on the bit line <NUM>. A portion of electrons flowing across the gap between the word line <NUM> and the floating gate <NUM> acquire enough energy to inject into the floating gate <NUM> causing the floating gate <NUM> to be negatively charged, turning off the cell <NUM> in read condition. The resulting cell programmed state is known as '<NUM>' state.

Exemplary voltages that can be used for the read, program, and erase operations in memory cell <NUM> is shown below in Table <NUM>:.

For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells.

Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell <NUM> is shown below in Table <NUM>:.

Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell <NUM> is shown below in Table <NUM>:.

For programming operation, the EG voltage is applied much higher, e.g. <NUM>-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells.

Also known in the prior art are fully depleted silicon-on-insulator ("FDSOI") transistor designs as shown in <FIG>. The FDSOI advantages includes a back gate (with buried oxide as a gate oxide) to modulate the threshold voltage (forward body bias or reverse body bias), an ultrathin un-doped channel that gives higher mobility and no random doping fluctuation. It has a ground plane on the back gate to adjust implant to adjust the threshold voltage. It also has a channel that is fully depleted to give better electrostatic control, lower drain-induced-barrier-lowering DIBL and short channel effect. It has minimum source and drain junction. Metal gate and channel length are also used to adjust threshold voltage.

<FIG> depicts FDSOI CMOS circuit cross section <NUM>. FDSOI CMOS circuit <NUM> comprises silicon substrate <NUM>, silicon insulators <NUM>, FDSOI NMOS transistor <NUM>, and FDSOI PMOS transistor <NUM>.

FDSOI NMOS transistor <NUM> comprises gate <NUM>, and source and drain <NUM>. FDSOI NMOS transistor <NUM> further comprises p-well <NUM>, buried oxide layer <NUM> (which is an insulator), and channel <NUM>. Channel <NUM> is an undoped, fully depleted channel. During operation, buried oxide layer <NUM> minimizes any leakage out of channel <NUM>. FDSOI NMOS transistor <NUM> further comprises p-well back gate terminal <NUM>, which can be used to add a bias to p-well <NUM> such as to adjust the threshold voltage Vt of the NMOS <NUM>.

FDSOI PMOS transistor <NUM> comprises gate <NUM>, and source and drain <NUM>. FDSOI PMOS transistor <NUM> further comprises n-well <NUM>, buried oxide layer <NUM> (which is an insulator), and channel <NUM>. Channel <NUM> is an undoped, fully depleted channel. During operation, buried oxide layer <NUM> minimizes any leakage out of channel <NUM>. FDSOI PMOS transistor <NUM> further comprises n-well back gate terminal <NUM>, which can be used to add a bias to n-well <NUM> such as to adjust the threshold voltage Vt of the PMOS <NUM>.

<FIG> depicts FDSOI CMOS circuit cross section <NUM>. FDSOI CMOS <NUM> circuit comprises silicon substrate <NUM>, silicon insulators <NUM>, FDSOI NMOS transistor <NUM>, and FDSOI PMOS transistor <NUM>.

FDSOI NMOS transistor <NUM> comprises gate <NUM>, and source and drain <NUM>. FDSOI NMOS transistor <NUM> further comprises n-well <NUM>, buried oxide layer <NUM> (which is an insulator), and channel <NUM>. Channel <NUM> is an undoped, fully depleted channel. During operation, buried oxide layer <NUM> minimizes any leakage out of channel <NUM>. FDSOI NMOS transistor <NUM> further comprises n-well back gate terminal <NUM>, which can be used to add a bias to n-well <NUM> such as to adjust the threshold voltage Vt of the NMOS <NUM>.

FDSOI PMOS transistor <NUM> comprises gate <NUM>, and source and drain <NUM>. FDSOI PMOS transistor <NUM> further comprises p-well <NUM>, buried oxide layer <NUM> (which is an insulator), and channel <NUM>. Channel <NUM> is an undoped, fully depleted channel. During operation, buried oxide layer <NUM> minimizes any leakage out of channel <NUM>. FDSOI PMOS transistor <NUM> further comprises p-well back gate terminal <NUM>, which can be used to add a bias to p-well <NUM> such as to adjust the threshold voltage Vt of the PMOS <NUM>.

<FIG> depicts FDSOI and bulk CMOS hybrid MOS circuit cross section <NUM>. Bulk CMOS refers to standard PMOS and NMOS transistor on bulk silicon. Hybrid MOS circuit <NUM> comprises silicon substrate <NUM>, silicon insulators <NUM>, FDSOI NMOS transistor <NUM> and NMOS transistor <NUM>. NMOS transistor <NUM> is a traditional NMOS transistor and not an FDSOI NMOS transistor.

NMOS transistor <NUM> comprises gate <NUM>, and source and drain <NUM>. NMOS transistor <NUM> further comprises p-well bulk <NUM> and doped channel <NUM>. NMOS transistor <NUM> further comprises p-well bulk terminal <NUM>, which can be used to add a bias to p-well bulk <NUM>. <CIT> discloses a prior art row decoder circuit.

<CIT> discloses an integrated circuit wherein fully depleted silicon on insulator devices are used for parts of the circuitry.

To date, fully depleted silicon-on-insulator transistor designs have not been used in flash memory systems. What is needed is a flash memory system that utilizes fully depleted silicon-on-insulator transistor designs. What is further needed is a partitioned flash memory chip that comprises a bulk region and an FDSOI region to maximize area and minimize leakage.

<FIG> depicts eight FDSOI transistor types that are used in the embodiments described herein.

Standard fixed bias FDSOI MOS transistors includes PMOS transistor <NUM> and NMOS transistor <NUM>. FDSOI PMOS transistor <NUM> comprises an n-well that is biased to Vdd power supply and optionally to ground, in this case transistor channel length is modified to have similar threshold voltage level. FDSOI NMOS transistor <NUM> comprises a p-well that is biased to ground. The PMOS <NUM> and NMOS <NUM> are regular threshold voltage devices.

Flipped well fixed bias FDSOI MOS transistors includes PMOS transistor <NUM> and NMOS transistor <NUM>. FDSOI PMOS transistor <NUM> comprises a p-well that is biased to ground. FDSOI NMOS transistor <NUM> comprises an n-well that is biased to ground. The PMOS <NUM> and NMOS <NUM> are low threshold voltage devices, i.e., its threshold voltage is lower than that of the PMOS <NUM> and NMOS <NUM>.

Standard dynamic bias FDSOI MOS transistors includes PMOS transistor <NUM> and NMOS transistor <NUM>. FDSOI PMOS transistor <NUM> comprises an n-well that is biased to a dynamic voltage source Vb_PRW. FDSOI NMOS transistor <NUM> comprises a p-well that is biased to a dynamic voltage source Vb_NRW. The dynamic voltage source is used to forward body (well) bias FBB or reverse body bias RBB to optimize performance. For the PMOS <NUM> dynamic voltage source Vb_PRW varies to positive voltage (e.g., up to 3V) for RBB and varies to negative voltage (e.g., up to -<NUM>. 5V) for FBB. For the NMOS <NUM> dynamic voltage source Vb_NRW varies to positive voltage (e.g., 0V to 3V) for FBB and varies to negative voltage (e.g., 0V to -3V) for RBB. A deep nwell is needed to isolate the pwell from p substrate to allow pwell to be biased at a high level, e.g. 3V or -3V.

Flipped well dynamic bias FDSOI MOS transistors includes PMOS transistor <NUM> and NMOS transistor <NUM>. FDSOI PMOS transistor <NUM> comprises a p-well that is biased to a dynamic voltage source Vb_PLW. FDSOI NMOS transistor <NUM> comprises an n-well that is biased to a dynamic voltage source Vb_NLW. For the PMOS <NUM> dynamic voltage source Vb_PLW varies to positive voltage (e.g., 0V to 3V) for RBB and varies to negative voltage (e.g., 0V to -3V) for FBB. For the NMOS <NUM> dynamic voltage source Vb_NLW varies to positive voltage (e.g., 0V to 3V) for FBB and varies to negative voltage (e.g., 0V to -<NUM>. 5V) for RBB. A deep nwell is needed to isolate the pwell from p substrate to allow pwell to be biased at a high level, e.g. 3V or -3V.

In the embodiments that follow, one or more the eight types of FDSOI transistors shown in <FIG> are used in a flash memory system.

<FIG> depicts an embodiment of an architecture for a flash memory system comprising die <NUM>. Die <NUM> comprises: flash memory arrays 601comprising rows and columns of memory cells of the type described previously as memory cell <NUM> in <FIG>; row decoder circuits <NUM> used to access the rows in flash memory arrays 601to be read from or written to; column decoder circuits <NUM> used to access bytes in flash memory arrays <NUM> to be read from or written to; sensing circuits <NUM> used to read data from flash memory arrays <NUM>; high voltage (HV) decoder <NUM> consisting of HV decoding block <NUM> and HV passing blocks <NUM> and <NUM> for delivering voltages and biases needed for non-volatile operation for the flash memory arrays <NUM>; control logic <NUM> for providing various control functions, such as redundancy and built-in self-testing; analog circuit <NUM>; bulk bias control <NUM> for controlling the voltage of the bulk (well) regions of transistors; high voltage charge pump circuit <NUM> used to provide increased voltages for program and erase operations for flash memory arrays <NUM>. The chip partition for the blocks for FDSOI vs. Bulk CMOS region to achieve optimal performance is as following.

An embodiment of array <NUM> is shown in <FIG>. Array <NUM> comprises a first plurality of subarrays <NUM> and a second plurality of subarrays <NUM>. Here, the first plurality of subarrays <NUM> has a bias voltage applied to its p-well and n-well areas (to achieve higher performance), and the second plurality of subarrays <NUM> does not have a bias voltage applied to its p-well and n-well areas (to achieve less leakage). Array <NUM> further comprises row decoder <NUM>, high voltage subarray source <NUM>, and high voltage decoder <NUM>.

<FIG> depicts decoder <NUM> for generating bias control voltages P1_PW, P2_PW, N1_NW, and N2_NW, which are used in the embodiments that follow. Decoder <NUM> comprises NAND gate <NUM>, inverter <NUM>, and programmable voltage sources <NUM>, <NUM>, <NUM>, and <NUM>, as shown.

<FIG> depicts row decoder <NUM>. Row decoder <NUM> comprises NAND gate <NUM>, inverter <NUM>, as well as PMOS transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and NMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> as shown. The NAND gate <NUM> and inverter <NUM> serves as row address decoder to decoding address signal XPA-D for row address decoding. The PMOS <NUM> and NMOS <NUM> serves as row driver with strong strength to drive pre-determined signal ZVDD into wordlines WL0-<NUM> of memory cell. The PMOS <NUM>, PMOS <NUM>, and NMOS <NUM> serves dual functions, as a row pre-driver and decoding address signals XPZB0-<NUM>.

NAND gate <NUM> comprises transistors of type FDSOI PMOS with the p-well biased to P2_PW and transistors of type FDSOI NMOS with the n-well biased to N2_NW.

Inverter <NUM> comprises transistors of type FDSOI PMOS with the p-well biased to P1_PW and transistors of type FDSOI NMOS with the n-well biased to N1_NW.

PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are transistors of type FDSOI PMOS with the p-well biased to P2_PW. PMOS transistors <NUM> and <NUM> are transistors of type FDSOI PMOS with the p-well biased to P1_PW.

NMOS transistors <NUM> and <NUM> are transistors of type FDSOI NMOS with the n-well biased to N2_NW. NMOS transistors <NUM> and <NUM> are transistors of type FDSOI NMOS with the n-well biased to N1_NW. The well bias levels for P1_PW/P2_PW/N1_NW/N2_NW are such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage.

<FIG> depicts row decoder <NUM>. Row decoder <NUM> is structurally identical to row decoder <NUM>, except that all of the transistors are of type FDSOI PMOS <NUM>, with the p-well biased to P1_PW. The well bias levels for P1_PW is such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage
<FIG> depicts row decoder <NUM>. Row decoder <NUM> is structurally identical to row decoder <NUM>, except that all of the transistors are of type FDSOI NMOS <NUM>, with the n-well biased to P1_NW. The well bias levels for P1_NW is such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage
<FIG> depicts row decoder <NUM>. Row decoder <NUM> is structurally identical to row decoder <NUM>, except that: NAND gate <NUM> comprises transistors of type FDSOI NMOS <NUM> with the p-well biased to P2_PW; inverter <NUM> comprises transistors of type FDSOI NMOS <NUM> with the n-well biased to P1_NW; PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are transistors of type FDSOI PMOS <NUM> with the p-well biased to P1_NW; PMOS transistors <NUM> and <NUM> are transistors of type FDSOI PMOS <NUM> with the p-well biased to P2_PW; NMOS transistors <NUM> and <NUM> are transistors of type FDSOI NMOS <NUM>, with the n-well biased to P2_PW; and NMOS transistors <NUM> and <NUM> are transistors of type FDSOI NMOS <NUM> of with the n-well biased to P1_NW. The well bias levels for P2_PW/P1_NW are such that using forward bias FBB for speed performance and reverse bias RBB to reduce leakage
<FIG> depicts erase gate decoder <NUM>. No FDSOI transistors are used in erase gate decoder <NUM> in this example but of bulk CMOS types. HV PMOS <NUM> to control current from HV supply VEGSUP, HV PMOS <NUM> is used as address decoding. HV NMOS <NUM> is used as pull down device to pull EG <NUM> to a low level or as a passing transistor to pass bias level EG_LOW_BIAS <NUM> into the EG terminal.

<FIG> depicts source line decoder <NUM>. No FDSOI transistors are used in source line decoder <NUM> in this example but of bulk CMOS types. NMOS <NUM> is used to pass SL supply VSLSUP, NMOS <NUM> is used to measure (monitor) voltage on SL <NUM>, NMOS <NUM> is used to pass a low bias level SLRD_LOW_BIAS in read or standby, NMOS <NUM> is used to pass a low bias level SLP_LOW_BIAS in program.

<FIG> depicts high voltage circuit selector <NUM> that once it is enabled will output positive high voltage level on ENHV and/or negative high voltage level on ENHVNEG. No FDSOI transistors are used in high voltage logic selector <NUM> in this example.

<FIG> depicts coupling gate decoder <NUM>. No FDSOI transistors are used in coupling gate decoder <NUM><NUM> in this example but of bulk CMOS types. HV PMOS <NUM> is used to pass CG supply, HV PMOS <NUM> is as address decoding, PMOS <NUM> is used to control current from CG read supply VCGRSUP, HV PMOS <NUM> is used to pass CG read supply. PMOS <NUM> is used to isolate negative voltage level. NMOS <NUM> is used as address decoding, NMOS <NUM> and <NUM> are used as for negative voltage isolation, NMOS <NUM> is used to pass a bias level CG_LOW_BIAS into CG <NUM>. NMOS <NUM> is used to pass negative voltage supply VHVNEG, NMOS <NUM> is used as negative cascoding.

<FIG> depicts low voltage sector enabling latch logic <NUM>. Low voltage logic <NUM> comprises latched inverters <NUM> and <NUM> and NMOS transistors <NUM> (wordline enabling), <NUM> (sector enabling), and <NUM> (used for resetting the latched <NUM>/<NUM> ), all of which are constructed from transistors of type that utilize a p-well. Alternatively inverter <NUM> can be constructed from transistors that utilize n-well.

<FIG> depicts sensing system <NUM>, similar to blocks <NUM>/<NUM>/<NUM>/<NUM> of die <NUM> of <FIG>. Sensing system <NUM> comprises sensing amplifiers <NUM>, <NUM>, <NUM>, and <NUM>. Embodiments of sensing amplifiers <NUM>, <NUM>, <NUM>, and <NUM> are shown in <FIG>. A reference sector <NUM> is used to generate reference bias from reference memory cell for the sensing. The two inputs of a sense amplifier couples to two bitlines of two array planes, for example the sense amplifier <NUM> couples to top array plane <NUM> and bottom array plane <NUM>. One of array plane provides a selected bitline (hence a selected memory cell through one wordline enabled) and the other array plane provides an un-selected bitline (all wordlines are disabled for this array plane) for sensing for symmetrical bitline sensing.

<FIG> depicts sensing amplifier <NUM>. Sensing amplifier <NUM> comprises PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> (of type FDSOI PMOS <NUM>, with p-well coupled to ground), PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> (of type FDSOI PMOS <NUM> with n-well coupled to Vbias), NMOS transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> (of type FDSOI NMOS <NUM>, with n-well coupled to ground), and NMOS transistor <NUM> (of type FDSOI NMOS <NUM>, with p-well coupled to ground). The PMOS <NUM> and NMOS <NUM> (and PMOS <NUM> and NMOS <NUM>) is first (read-out) stage of the sensing amplifier. The PMOS <NUM> is mirrored from a reference current Iref (such as from a reference cell in the reference sector <NUM> in sensing system <NUM> or a resistor). The NMOS <NUM> couples to a cell current Icell through the bitline of the selected memory cell. The drain of the NMOS <NUM> is sensing out node <NUM> which is equal to difference between Iref and Icell times output impedance at node <NUM>, i.e., Vsensed=Ro*(Icell-Iref). The drain of the NMOS <NUM> is a reference node <NUM>. The PMOS <NUM> is in a disabled state with a Ileakpmos (duplicating the off state leakage of the PMOS <NUM>), The NMOS <NUM> couples to cell current leakage Icellleak through an unselected bitline (selected bitline with all wordlines disabled) of the memory cell. The drain of the NMOS <NUM> is sensing out node <NUM> which is equal to difference between Ileakpmos and Icellleak times output impedance at node <NUM>, i.e., Vrefsen=Ro*(Icellleak-Ileakpmos). The sensing node <NUM> and reference node <NUM> are precharged at start of sensing to reference voltage level <NUM> and <NUM> respectively. The transistors <NUM>-<NUM> is second (comparison) stage of the sensing amplifier. It is a dynamic latched differential amplifier with transistor NMOS <NUM> and <NUM> as input pair with the sensing out node <NUM> and the reference node <NUM> as inputs. The transistors <NUM>,<NUM>,<NUM>, and <NUM> are latched inverters with outputs ON and OP as full voltage level (Vdd/gnd) sensing outputs after sensing the difference between the sensing out node <NUM> and the reference node <NUM>. The PMOS transistors <NUM>,<NUM>,<NUM>,<NUM> are for precharging the nodes of the latched inverters to high supply level. The NMOS <NUM> and <NUM> are footed input pairs (meaning connecting in series to NMOS transistors of the latched inverters). The NMOS <NUM> is enabling bias transistor for the input pairs.

<FIG> depicts sensing amplifier <NUM>. Sensing amplifier <NUM> is structurally identical to sensing amplifier <NUM>, except that the n-well of NMOS transistor <NUM> is coupled to a variable voltage source, NL5_NWB, and the n-well of NMOS transistor <NUM> is coupled to a variable voltage source, NL5_NWB. The variable voltage source is used to dynamically bias the well to optimize speed in active (forward body bias) and reduce leakage in standby (reverse body bias). It could also be used to nullify the threshold voltage offset of the sense amplifier.

<FIG> depicts sensing amplifier <NUM>. Sensing amplifier <NUM> is structurally identical to sensing amplifier <NUM>, except that the p-well of PMOS transistor <NUM>, <NUM>, <NUM>, and 1907are coupled to a variable voltage source, PL1_PW, and the n-well of NMOS transistor <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are coupled to a variable voltage source, NL1_NW. The variable voltage source is used to optimize speed in active (forward bias the well) and reduce leakage in standby (reverse bias the well)
<FIG> depicts sensing amplifier <NUM> with FDSOI and bulk CMOS hybrid region partition. Sensing amplifier <NUM> is structurally identical to sensing amplifier <NUM>, except that the p-well of PMOS transistor <NUM> and 1907are coupled to a variable voltage source, PL1_PW, and the n-well of NMOS transistor <NUM> and <NUM> are coupled to a variable voltage source, NL1_NW and PMOS transistor <NUM> and <NUM> and NMOS transistors <NUM> and <NUM> are bulk CMOS transistors. The PMOS <NUM> and NMOS <NUM> and PMOS <NUM> and NMOS <NUM> are bulk cmos read-out stage of the amplifier. This read-out stage couples to a high supply level (due to bulk cmos transistor), for example <NUM>. 8v, instead of a logic supply level, for example Vdd1.2v for wide sensing range.

Claim 1:
A flash memory system (<NUM>) comprising:
an array (<NUM>) of flash memory cells arranged into rows and columns; and
a row decoder (<NUM>, <NUM>, <NUM>) comprising for each row in the array:
a row address decoder (<NUM> and <NUM>) to select the row in response to an address signal (XPA-A to XPA-D);
an inverter (<NUM>) to invert the output of the row address decoder;
a row pre-driver (<NUM>, <NUM>, <NUM>) to receive the output of the row address decoder and an output of the inverter, the row pre-driver comprising:
a first fully depleted silicon-on-insulator PMOS transistor (<NUM>) comprising a first terminal, a gate coupled to an output from the row address decoder, and a second terminal coupled to ground;
a second fully depleted silicon-on-insulator PMOS transistor (<NUM>) comprising a first terminal coupled to a first voltage source (ZVDD2), a second terminal coupled to the first terminal of the first PMOS transistor, and a gate coupled to an output of the inverter; and
a first fully depleted silicon-on-insulator NMOS transistor (<NUM>) comprising a first terminal coupled to the second terminal of the second PMOS transistor, a gate coupled to the output of the inverter, and a second terminal coupled to ground; and
a row driver comprising a second fully depleted silicon-on-insulator NMOS transistor (<NUM>, <NUM>) comprising a first terminal coupled to a second voltage source (ZVDD), a second terminal, and a gate coupled to an output of the row pre-driver and a third fully depleted silicon-on-insulator PMOS transistor (<NUM>, <NUM>) comprising a first terminal coupled to the second terminal of the fully depleted silicon-on-insulator NMOS transistor, a second terminal coupled to ground, and a gate coupled to the output of the row pre-driver to drive a word line (WLO) in the array;
wherein each of the fully depleted silicon-on-insulator NMOS transistors comprises an n-well under a buried oxide layer being coupled to a respective one of two different bias control voltages (N1_NW, N2_NW) which provide a forward body bias or a reverse body bias to the NMOS transistor; and
wherein each of the fully depleted silicon-on-insulator PMOS transistors comprises a p-well under a buried oxide layer being coupled to a respective one of two different bias control voltages (P1_PW, P2_PW) which provide a forward body bias or a reverse body bias to the PMOS transistor.