Patent Description:
This section is intended to introduce the reader to various aspects of art that may be related to aspects of the present disclosure, which are described and/or claimed below. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.

When receiving certain input, such as when operating using certain communications networks (e.g., <NUM> cellular network, <NUM> cellular network, mmWave), vectors of data may be received and transmitted that are made up of multiple streams of data. While each stream of data may be of the same format, compression schemes, packing schemes, and so on (thus referred to as a homogeneous data stream), the received or transmitted vector may include multiple streams of data having different formats, compression schemes, packing schemes, and so on, with samples from multiple streams possibly being interleaved and arranged in different possible orders, depending upon the data packing format specified in the communication protocol (thus collectively referred to as a heterogeneous vector or data stream).

Upon receipt of the heterogeneous vector, a receiving device may separate portions (e.g., bits) of data from received vector and re-form them into their original respective homogeneous streams. Further processing may take place using these resulting homogeneous data streams. Similarly, a transmitting device may combine portions of data from multiple homogeneous streams of data into a heterogeneous vector of data (e.g., a byte in length) for transmission to a receiving device. However, serial or sequential processing of a received heterogeneous data stream to re-form the original respective homogeneous streams may be inefficient and slow. Likewise, serial or sequential processing of the various homogeneous streams to form a homogeneous vector for transmission may likewise be inefficient and slow.

<CIT> describes instructions to extract data elements from specific positions within data structures. <CIT> describes instructions to extract data elements from even numbered locations or from odd numbered locations within two source vector register.

It may be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it may be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

The presently disclosed systems and methods include a vector processor having multiple parallel processing units (e.g., single input multiple data (SIMD) units) coupled to grouping memory having multiple bins. The vector processor may receive and read an input vector of data that includes portions (e.g., bits) of multiple data streams, and write each portion corresponding to a respective data stream to a respective bin in parallel. The vector processor may also or alternatively receive and read multiple outgoing data streams, write portions of the data streams in respective bins of the grouping memory, and intersperse the portions in an outgoing vector of data in parallel.

This may accelerate processing of input and output vectors of data compared to scalar processing (e.g., by a factor of <NUM> for byte-length vectors). For example, a scalar processor may loop through input vectors of data once for each data stream to determine the portions of data for a data stream, and then write the portions to data words of that data stream. Instead, the disclosed vector processor may loop through the input vectors once while writing data from the input vectors into a corresponding memory or grouping bin in parallel, providing a more efficient approach that reduces the overhead of multiple loops. Similarly, a scalar processor may loop through data words for each data stream one at a time to determine the portions of data to write to an outgoing vector of data, and then write the portions to the outgoing vector. Instead, the disclosed vector processor may write the data words to corresponding grouping bins and loop through the grouping bins to write data from the grouping bins to the outgoing vector in parallel, providing a more efficient approach that reduces the overhead of multiple loops.

By way of introduction, <FIG> illustrates a block diagram of a data processing system <NUM> having a vector processor <NUM> that processes heterogeneous data streams, according to embodiments of the present disclosure. While the system <NUM> is illustrated as a data processing system, it should be understood that the system <NUM> may be any suitable system that implements the vector processor <NUM> to process heterogeneous data streams, such as a communication system, a networking system, and the like. Moreover, it should be understood that while the vector processor <NUM> is described in terms of hardware (e.g., processing and/or supporting circuitry), at least some of the vector processor <NUM> may be implemented in software (e.g., instructions stored in a memory device).

The data processing system <NUM> may include processing circuitry <NUM> (e.g., a host processor), memory/storage circuitry <NUM>, and a network interface <NUM>. The data processing system <NUM> may include more or fewer components (e.g., electronic display, user interface structures, application specific integrated circuits (ASICs)). While the vector processor <NUM> is illustrated as external to the processing circuitry <NUM>, in some embodiments, the vector processor <NUM> may be internal to or part of the processing circuitry <NUM>. The processing circuitry <NUM> may include any additional suitable processors, such as an Intel® Xeon® processor or a reduced-instruction processor (e.g., a reduced instruction set computer (RISC), an Advanced RISC Machine (ARM) processor) that may manage a data processing request for the data processing system <NUM> (e.g., to perform machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or the like).

The memory and/or storage circuitry <NUM> may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, or the like, and store data to be processed by the data processing system <NUM>. The network interface <NUM> may allow the data processing system <NUM> to communicate with other (e.g., external) electronic devices. The data processing system <NUM> may include several different packages or may be contained within a single package on a single package substrate.

In one example, the data processing system <NUM> may be part of a data center that processes a variety of different requests. For instance, the data processing system <NUM> may receive a data processing request via the network interface <NUM> to perform machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or some other specialized task.

<FIG> is a block diagram of a controller <NUM> having the vector processor <NUM> that processes heterogeneous data streams, according to embodiments of the present disclosure. The controller <NUM> may be any suitable controller that uses the vector processor <NUM> that processes heterogeneous data streams, such as a baseband unit, a radio equipment controller, a network controller, a communications controller, a video controller, a graphics controller, a data management controller, and so on. The controller <NUM> may include the processing circuitry <NUM> of the data processing system <NUM>, which may be communicatively coupled to the vector processor12. In some embodiments, the controller <NUM> may be part of a system on a chip (SoC), such that the processing circuitry <NUM>, the vector processor <NUM>, and other components may be disposed on an integrated circuit or chip.

In some embodiments, the controller <NUM> may also include or be coupled to a transceiver <NUM>, which may send and receive data, using any suitable communication protocol, to and from an external device <NUM> separate or apart from the data processing system <NUM>. The transceiver <NUM> may be part of the network interface <NUM> of the data processing system <NUM> of <FIG>. In some embodiments, the transceiver <NUM> may be split into a transmitter and a receiver. The transceiver <NUM> may also be communicatively coupled to the processing circuitry <NUM>, and may send or receive heterogeneous or irregular data to or from the vector processor <NUM> via the processing circuitry <NUM>. For example, in remote radio heads, data from multiple streams may be packed into an input vector of data, where each stream may include respective data elements having different sizes, alignments, formats, and so on. The format of each data element, portion, or sample may be specified by a specification or configuration. That is, in certain telecommunication systems, communication data associated with multiple data streams may have an irregular data format. While the vector processor <NUM>, the processing circuitry <NUM>, and the transceiver <NUM> are shown as part of the controller <NUM>, it should be understood that in alternative or additional embodiments, these components may not be contained in or part of the controller <NUM> (e.g., may be external to the controller <NUM>).

Each stream of data may vary with compression, specialized packing, and/or data protocols. As such, an input vector of data may be heterogeneous or irregular as it may be made up of data samples having these different characteristics or properties. That is, a heterogeneous data stream may include data samples having different data types, formats, and/or alignments, whereas a homogeneous data stream may include data samples having the same data types, formats, and/or alignments. For the purposes of this disclosure, the terms "heterogeneous" and "irregular" are used interchangeably and mean the same thing. <FIG> is a diagram of heterogeneous data <NUM> and homogeneous data <NUM>, according to embodiments of the present disclosure. As illustrated, the heterogeneous data <NUM> and the homogeneous data <NUM> are made up of three different streams of data, stream A (e.g., as represented by data samples starting with the letter "a", of which data sample <NUM> is an example), stream B (e.g., as represented by data samples starting with the letter "b", of which data sample <NUM> is an example), and stream C (e.g., as represented by data samples starting with the letter "c", of which data sample <NUM> is an example).

The vector processor <NUM> may receive the heterogeneous data <NUM> from an external source or device <NUM> via the transceiver <NUM>. The vector processor <NUM> may convert, organize, or categorize the heterogeneous data <NUM> into the homogeneous data <NUM> for use (e.g., by portions of the controller <NUM>). The vector processor <NUM> may also or alternatively receive the homogeneous data <NUM> (e.g., from an internal source or component of the controller <NUM>), and convert, organize, or categorize the homogeneous data <NUM> to the heterogeneous data <NUM> for transmission (e.g., by the transceiver <NUM>).

Some data processing systems may process input data streams or prepare output data streams having heterogeneous data in a serial manner (e.g., on a per-stream basis). However, with the evolution of high bandwidth radio communication systems (e.g., implementing <NUM>, <NUM>, and/or mmWave technologies), single stream processing of data may be insufficient to handle increased data rates. Therefore, parallel processing techniques may be improve performance of processing data streams having heterogeneous data. The vector processor <NUM> may include single input multiple data (SIMD) very large instruction word (VLIW) processors that process such data streams using parallel processing techniques.

<FIG> is a block diagram of an example of the vector processor <NUM> and hardware components supporting the vector processor <NUM>, according to embodiments of the present disclosure. The illustrated vector processor <NUM> may include multiple parallel scalar and single input multiple data functional units <NUM> (labeled "FU1", "FU2",. , "FU'n"') that perform arithmetic operations, logic operations, or any other suitable data processing operations, provided as a set of instructions, which may be stored in program memory <NUM>. While the program memory <NUM> is illustrated as part of the vector processor <NUM>, in additional or alternative embodiments, the program memory <NUM> may be external to and support the vector processor <NUM>. The illustrated vector processor <NUM> may also include vector load and store units <NUM> that transfer data from and/or to vector memory blocks <NUM> (labeled "VMEM0", "VMEM1") that store input and/or output data. The illustrated vector processor <NUM> may include a load-store unit controller <NUM> (labeled "LSUCtl") that executes load and store instructions, generates virtual addresses of load and store operations, and/or loads data from or stores data to memory blocks <NUM> (labeled "DMEMCtl") that store control data.

The illustrated vector processor <NUM> may also include grouping memory <NUM> used to store data to be processed from input vectors or as output vectors. The grouping memory <NUM> may be part of the grouping memory functional unit (labeled "GMEM FU") <NUM>. The grouping memory functional unit <NUM> may be a single input multiple data functional unit (e.g., <NUM>), that writes data samples to the multiple bins in parallel, and/or reads data sample from the multiple bins in parallel. The grouping memory <NUM> may include multiple bins and each bin, which may be one vector wide, can hold data samples belonging to one single stream. The illustrated vector processor <NUM> may also include a bitformatting functional unit <NUM> (labeled "Bitfmt FU"), which may include a control pattern memory <NUM> (labeled "Ctrl Pattern Mem"). The bitformatting functional unit <NUM> may perform bit-level data arrangements using any suitable technique or network, such as a Benes network. The control pattern memory <NUM> may enable flexible (e.g., reconfigurable, programmable) functionality to change heterogeneous data streams to homogeneous data streams, and vice versa, as explained in further detail below. As illustrated, the vector processor <NUM> also includes base functions <NUM> that facilitate operation of the vector processor <NUM>, and register files and connection network storage and functionality <NUM>. While the register files and connection network storage and functionality <NUM> is illustrated as part of the vector processor <NUM>, in additional or alternative embodiments, the register files and connection network storage and functionality <NUM> may be external to and support the vector processor <NUM>.

The vector processor <NUM> may write data samples from different streams stored in a single input vector to different bins of the grouping memory <NUM> to produce homogeneous data. <FIG> is a flow diagram of a process <NUM> for converting heterogeneous data in input vectors to homogeneous data in the grouping memory <NUM>, according to embodiments of the present disclosure. While the process <NUM> is described using steps in a specific sequence, it should be understood that the present disclosure contemplates that the described steps may be performed in different sequences than the sequence illustrated, and certain described steps may be skipped or not performed altogether. In some embodiments, the process <NUM> may be implemented by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the memory/storage circuitry <NUM>, the program memory <NUM>, and/or the control pattern memory <NUM>, using a processor, such as the processing circuitry <NUM> and/or the vector processor <NUM>.

As illustrated, in process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> receives the heterogeneous data input. In particular, the heterogeneous data input may include multiple data samples of different data types in an input vector of data. The input vector may be any suitable size, such as one word or byte (e.g., eight bits) long. The input vector may be received via the transceiver <NUM>.

In process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> may apply a bit-level Benes Network (e.g., as implemented by the bitformatting functional unit <NUM>) to determine which data stream each data sample belongs to, and align the data samples belonging to the same data stream. In process blocks <NUM> and <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> may use the grouping memory functional unit <NUM> to employ single input multiple data arithmetic processing to write the data samples into grouping memory <NUM> corresponding to the multiple data streams in parallel (e.g., simultaneously or at the same or approximately the same time, as opposed to sequentially or serially). In process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> may use the grouping memory functional unit <NUM> to read the data samples stored in the grouping memory <NUM> to output homogeneous data. In this manner, the process <NUM> may enable the processing circuitry <NUM> and/or the vector processor <NUM> to align the data samples in their original stream form using parallel processing techniques.

The vector processor <NUM> may also or alternatively read and combine data samples from different bins of the grouping memory <NUM> into a single output vector when receiving homogeneous data input (e.g., from an internal source of the controller <NUM>). <FIG> is a flow diagram of a process <NUM> for converting homogeneous data to heterogeneous data to be output in vectors, according to embodiments of the present disclosure. While the process <NUM> is described using steps in a specific sequence, it should be understood that the present disclosure contemplates that the described steps may be performed in different sequences than the sequence illustrated, and certain described steps may be skipped or not performed altogether. In some embodiments, the process <NUM> may be implemented by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the memory/storage circuitry <NUM>, the program memory <NUM>, and/or the control pattern memory <NUM>, using a processor, such as the processing circuitry <NUM> and/or the vector processor <NUM>.

As illustrated, in process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> receives the homogeneous data input. In particular, the homogeneous data input may include multiple streams of data samples, wherein each stream is of the same data type, format, and/or alignment. The homogeneous data input may be sent from, for example, an internal source within the controller <NUM>. In process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> stores the homogeneous data input into the grouping memory <NUM>. In particular, each bin of the grouping memory <NUM> may correspond to a data stream, such that samples from the stream may be stored in the same bin or bins.

In process blocks <NUM> and <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> may use the output of the grouping memory functional unit <NUM> to employ single input multiple data arithmetic processing and a bit-level Benes Network (e.g., as implemented by the bitformatting functional unit <NUM>) to write data samples from multiple bins (e.g., that may correspond to different data streams) to an output vector in parallel (e.g., simultaneously or at the same or approximately the same time, as opposed to sequentially or serially). In process block <NUM>, the processing circuitry <NUM> and/or the vector processor <NUM> may send the output vector to a recipient (e.g., a device <NUM> external to the controller <NUM>). In this manner, the process <NUM> may enable the processing circuitry <NUM> and/or the vector processor <NUM> to generate output vectors having heterogeneous data for output using parallel processing techniques.

<FIG> is a block diagram of the bitformatting functional unit <NUM>, according to embodiments of the present disclosure. The bitformatting functional unit <NUM> may include a bit-level Benes network <NUM>, which may include a butterfly (e.g., one source to many destinations) and/or an inverse butterfly (e.g., multiple sources to one destination) network, that provides arbitrary permutations and rearrangements of data. While the presently disclosed systems and methods are discussed as using a bit-level Benes network <NUM>, other circuit topologies, including Clos networks or crossbars, may perform bit-level formatting. As employed herein, the bit-level Benes network <NUM> may generate bit-level permutations and/or arrangements of data, as controlled by a bitformatting control pattern table <NUM>, which may be stored in the control pattern memory <NUM>.

The bit-level Benes network <NUM> may permute and align data samples to regular and/or recognized (e.g., byte, half word, and word) boundaries based on control patterns (which may be selected by a selection signal labeled "pattern_select" <NUM>) stored in the control pattern table <NUM>, when receiving heterogeneous data input <NUM> (labeled "input"). Additionally or alternatively, the bit-level Benes network <NUM> may permute and align data samples to any suitable output format based on the control patterns stored in the control pattern table <NUM> when generating heterogeneous data output <NUM> (labeled "output").

The control patterns may define how data samples from certain data streams should be permuted or aligned based on the format, alignment, and/or size of a data sample in a data stream. That is, the control patterns may be precomputed based on a format specification (e.g., of a data stream). In general, a number of control patterns may be stored in the control pattern table <NUM>, and an appropriate control pattern for each stream or data input or output may be selected. In some embodiments, the selection of a control pattern corresponding to a respective stream may be preselected (e.g., prior to runtime), while in additional or alternative embodiments, the selection may be made at run time. The control pattern table <NUM> may be reinitialized at the start of processing input and/or output vectors to support different sets of formatting types or specifications. It should be noted that the bit-level Benes network <NUM> may also perform de-interleaving and alignment of the data streams to a regular boundary. In some situations, the bit-level Benes network <NUM> may also facilitate compression and/or decompression of data streams by handling (e.g., adding, removing, editing) redundancy bits, compression exponents, and/or error checking bits. In this manner, the control pattern table <NUM> may enable the bit-level Benes network <NUM> to identify a data stream to which a data sample belongs (e.g., associate data samples with data streams), and thus read the data sample from an input vector or write the data sample to an output vector.

<FIG> is a circuit diagram of the grouping memory <NUM>, according to embodiments of the present disclosure. The grouping memory <NUM> may be a specialized memory architecture that employs flip-flops and logic circuitry. The grouping memory <NUM> may arrange the incoming data <NUM> (labeled "indata") (e.g., on the order of n times a word-length or byte) in a series of bins <NUM> based on a control signal <NUM> (labeled "ctrl_in") (e.g., sent by the bitformatting functional unit <NUM>) and a crossbar multiplexer <NUM>, wherein each bin <NUM> may be associated with a stream of data. In some embodiments, control signals <NUM> may store units (e.g., bits, words, bytes, or half words) of data from a common data stream in a common bin when receiving heterogeneous data input. Control signals <NUM> may also or alternatively cause the grouping memory <NUM> to scramble data units from different data streams based on the specification of the heterogeneous data output when producing heterogeneous data output. Data (e.g., on the order of n times a word-length or byte) may be read (and removed) from the bins <NUM> via read ports <NUM> and selected using element-wide multiplexers <NUM>, and output <NUM> (labeled "outdata") (e.g., on the order of n times a word-length or byte) using crossbar multiplexer <NUM> (e.g., as controlled by a control signal <NUM>).

<FIG> is a circuit diagram of a grouping bin <NUM>, according to embodiments of the present disclosure. As illustrated, the grouping bin <NUM> may operate as a logical first-in first-out (FIFO) buffer on a per-stream basis. The grouping bin <NUM> may include input rotator circuitry <NUM>, output rotator circuitry <NUM>, and a FIFO buffer <NUM> having multiple flip-flops <NUM>. A control signal <NUM> (labeled "ctrl") may select data that is output by the grouping bin <NUM> via multiplexers <NUM>. Also illustrated is an enable signal <NUM> (labeled "enable") that may enable the input rotator circuitry <NUM>, the output rotator circuitry <NUM>, and/or the multiplexers <NUM>. While circuity may maintain a state of the grouping bin <NUM> (e.g., via read pointers, write pointers), the state of the grouping bin <NUM> may be additionally or alternatively determined (e.g., at each iteration of using the grouping bin <NUM>) by control generator software, and may be translated and provided to the grouping memory <NUM> via the control signal ctrl_in <NUM> shown in <FIG>.

The bin <NUM> may provide temporary storage during processing of data samples as inputs and/or outputs. As described herein, the grouping memory functional unit <NUM> may perform the operations described below on the grouping memory <NUM> (e.g., based on instructions stored in any suitable medium, such as the program memory <NUM>), though any suitable processor, such as the processing circuitry <NUM>, is contemplated to perform the described operations. In particular, the grouping memory functional unit <NUM> may "evict" the grouping bin <NUM> by reading and removing the data from the grouping bin <NUM>, when the processing circuitry <NUM> determines that the amount of data stored in the bin <NUM> exceeds a threshold. For example, in some embodiments, the processing circuitry <NUM> may determine that the grouping bin <NUM> is full and/or cannot store additional data, and thus may instruct the grouping memory functional unit <NUM> to evict the data stored in the bin <NUM>. In additional or alternative embodiments, the grouping memory functional unit <NUM> may evict the bin <NUM> when new or additional data cannot be stored in an existing bin <NUM> and all available bins <NUM> of the grouping memory <NUM> are occupied. The data from the evicted bin may then be used for subsequent processing by any of the functional units FU1. FU'n' <NUM>, the bitformatting functional unit Bitfmt FU <NUM>, and/or storage into the vector memory blocks VMEM0,VMEM1 <NUM>.

The grouping memory <NUM> may operate in at least two different modes. The 1Read-M-Write mode, which may be used for grouping when receiving heterogeneous data input, and the 1Write-M-Read mode, which may be used for scrambling (e.g., "ungrouping") to generate heterogeneous data output. In the 1Read-M-Write mode, the grouping memory <NUM> may read one grouping bin <NUM> and perform a partial write of 'M' bins <NUM> in parallel (e.g., simultaneously or at the same or approximately the same time, as opposed to sequentially or serially). In the <NUM> Write-M-Read mode, the grouping memory <NUM> may read multiple bins <NUM> (e.g., all the bins <NUM>) and perform write operations sample-by-sample to scramble the data samples in an output vector. In general, the number of bins <NUM> may be selected based on the number of streams and/or distributions (e.g., of data samples in an output vector). For example, there may be one bin <NUM>, two bins <NUM>, or any other suitable number of bins <NUM> for each stream.

<FIG> is a diagram of the grouping memory <NUM> operating in the 1Read-M-Write mode, according to embodiments of the present disclosure. In particular, <FIG> illustrates how data samples are read from input vectors and written to the grouping bins <NUM> based on data streams. A first input vector <NUM> (e.g., which may be stored in a common bin of the grouping memory <NUM>) includes a data sample (e.g., bit <NUM>) from data Stream <NUM>, data samples (e.g., bits <NUM>, <NUM>, <NUM>) from data Stream <NUM>, data samples (e.g., bits <NUM>, <NUM>) from data Stream <NUM>, and data samples (e.g., bits <NUM>, <NUM>) from data stream Stream <NUM>. As illustrated, data samples or bits of each data stream in the first input vector <NUM> may be non-contiguous.

As illustrated, the grouping memory functional unit <NUM> writes the data samples stored in the first input vector <NUM> into the grouping bins <NUM> based on the data streams associated with the data samples in parallel (e.g., simultaneously or at the same or approximately the same time, as opposed to sequentially or serially). In particular, Bin <NUM> corresponds to Stream <NUM>, Bin <NUM> corresponds to Stream <NUM>, Bin <NUM> corresponds to Stream <NUM>, and Bin <NUM> corresponds to Stream <NUM>. As such, the grouping memory functional unit <NUM> writes the data sample (e.g., bit <NUM>) from data Stream <NUM> into Bin <NUM>, the data samples (e.g., bits <NUM>, <NUM>, <NUM>) from data Stream <NUM> into Bin <NUM>, the data samples (e.g., bits <NUM>, <NUM>) from data Stream <NUM> into Bin <NUM>, and the data samples (e.g., bits <NUM>, <NUM>) from data stream Stream <NUM> into Bin <NUM> in parallel. The grouping memory functional unit <NUM> similarly writes the data samples stored in second input vector <NUM>, third input vector <NUM>, and fourth input vector <NUM> into the grouping bins <NUM> based on the data streams associated with the data samples in parallel.

When the processing circuitry <NUM> determines that a grouping bin <NUM> has reached a threshold storage amount (e.g., by executing software which may precompute a state of fullness of each grouping bin <NUM>, and determine which grouping bin(s) <NUM> to evict), such as when the grouping bin <NUM> is full, then the processing circuitry <NUM> may instruct the grouping memory functional unit <NUM> to evict the grouping bin <NUM>. In some embodiments, the processing circuitry <NUM> may write to software control headers that correspond to evicting one or more grouping bins <NUM>, and the grouping memory functional unit <NUM> may evict those grouping bins <NUM>. As illustrated, during processing of the third input vector <NUM>, Bin <NUM> reaches a threshold storage amount (e.g., becomes full). As such, the grouping memory functional unit <NUM> may evict Bin <NUM> by reading the data samples from Bin <NUM> and/or writing the data samples to the program memory <NUM>, and remove the data samples from Bin <NUM>. Similarly, during processing of the fourth input vector <NUM>, Bin <NUM> reaches a threshold storage amount and, as such, the grouping memory functional unit <NUM> evicts Bin <NUM>. As illustrated, additional grouping bins <NUM>, such as Bin <NUM>, may be assigned to store data samples from streams when available bins (e.g., Bin <NUM>) for those streams are full. This assignment may be made at runtime. Furthermore, while only five grouping bins <NUM> are illustrated in <FIG>, it should be understood that the grouping memory <NUM> may have any suitable number of grouping bins <NUM>.

Moreover, while the example above describes evicting a grouping bin <NUM> when the grouping bin <NUM> is full, it should be understood that a grouping bin <NUM> may be evicted when any suitable threshold fullness of the grouping bin <NUM> is reached. That is, the processing circuitry <NUM> may evict a grouping bin <NUM> when it is partially full (e.g., between <NUM>-<NUM>% full, <NUM>% full, <NUM>% full, <NUM>% full, <NUM>% full, <NUM>% full), when all the samples for the particular stream in that grouping bin <NUM> have finished arriving, based on a fullness that achieves better overall performance, and so on. Indeed, any suitable algorithm may be devised to that results in more efficient eviction of grouping bins <NUM> for a particular application. As such, the complexity of bin state management may be moved to offline software (e.g., stored in the memory/storage circuitry <NUM> of the data processing system <NUM> to be executed by the processing circuitry <NUM>), freeing up processing resources in the controller <NUM>.

The grouping memory <NUM> may operate in the 1Write-M-Read mode to facilitate performing the actions of the 1Read-M-Write mode described above in reverse order. In particular, the grouping memory <NUM> may receive multiple streams of data (e.g., from an internal source or component of the controller <NUM>) that are to be sent to, for example, an external source or device <NUM> via the transceiver <NUM>. The multiple streams of data may be stored in the grouping bins <NUM>, where each grouping bin <NUM> may correspond to a stream of data (as shown in <FIG>). The grouping memory <NUM> may form output vectors (e.g., <NUM>, <NUM>, <NUM>, <NUM>) by iterating through the grouping bins <NUM> and writing (and removing) data samples from the grouping bins <NUM> to the output vectors in parallel (e.g., simultaneously or at the same or approximately the same time, as opposed to sequentially or serially).

The vector processor <NUM> may employ a control header to implement data processing loop techniques to process or generate heterogeneous vectors. <FIG> is an example data processing loop, according to embodiments of the present disclosure. The generic processing iteration <NUM> illustrated <FIG> includes a sequence of instructions <NUM> that may be executed to process a certain amount of input data. The specific behavior for each execution instruction <NUM> may be defined by a control header <NUM>, which may be a set of control inputs <NUM> for each instruction <NUM>. As illustrated, the vector processor <NUM> may generate a control header <NUM> for the instructions <NUM> in the generic processing iteration <NUM>. The control header <NUM> may include pointers <NUM> to input data (stored in an input buffer <NUM>), output data (stored in an output buffer <NUM>), coefficients, and/or controls for each instruction <NUM> of the iteration <NUM>. In general, any processing loop may be implemented as a loop of generic processing iterations <NUM>, and the loop of generic processing iterations <NUM> may have a corresponding control header sequence <NUM>. The headers <NUM> may be stored sequentially in memory <NUM> (e.g., the program memory <NUM>) and processed in a loop <NUM>. The execution of the loop <NUM> may be software pipelined. By performing data processing loops such as that illustrated in <FIG>, the amount of overhead associated with the execution of instructions <NUM> may be reduced. Such implementation may be suitable in situations in which a total number of execution calls is not particularly high and where the control memory requirements are manageable. Examples of such situation include radio heads, in which the input block sizes per-stream may be small to meet low latency requirements.

In some embodiments, the vector processor <NUM> may be employed in communication infrastructure, such as in wireless base station architecture <NUM> as illustrated in <FIG>. Specifically, the vector processor <NUM> may perform operations that mediate interaction between baseband unit (e.g., radio equipment controller <NUM>) and a digital front end <NUM> of a radio unit <NUM>. For example, the baseband unit <NUM> may include processing circuitry <NUM> that includes the vector processor <NUM>, and one or more baseband modems. The vector processor <NUM> may process incoming or outgoing heterogeneous vectors to implement certain functionalities and protocols, such as the common public radio interface (CPRI), radio access network (RAN), open RAN (oRAN), virtualized RAN (vRAN), or extensible RAN (xRAN), thus increasing the speed and efficiency of processing data in the form of heterogeneous vectors. A baseband modem <NUM> may send heterogeneous vectors of data (e.g., that include data samples from multiple, different data streams) to and from the vector processor <NUM>.

A baseband-digital front end digital interface <NUM> may transfer the heterogeneous vectors of data between the baseband modem <NUM> of the baseband unit <NUM> and the digital front end <NUM> of the radio unit <NUM>. The digital front end <NUM> may send the heterogeneous vectors of data to and receive homogeneous vectors of data (e.g., to be converted to the heterogeneous vectors of data) from analog-to-digital (labeled "A/D") and/or digital-to-analog (labeled "D/A") converters <NUM>, which may be coupled to radio frequency units <NUM> and radio frequency amplifiers <NUM>. Antennas <NUM> coupled to the radio frequency amplifiers <NUM> may send or receive the heterogeneous vectors of data to and from devices external to the wireless base station architecture <NUM> using any suitable wireless communication protocol. As such, the radio unit <NUM> may be an example of an external device <NUM>, as shown in <FIG>, separate or apart from a data processing system <NUM> (e.g., the baseband unit <NUM>).

In additional or alternative embodiments, the vector processor <NUM> may be incorporated in an artificial intelligence inferencing system <NUM>, as illustrated in <FIG>. Specifically, an artificial intelligence inference engine <NUM> may include processing circuitry <NUM> that receives training data from a knowledge base <NUM>, and causes the artificial intelligence inference engine <NUM> to learn from repetitive iterations of using the training data to develop more accurate results. In particular, the processing circuitry <NUM> may include the vector processor <NUM>, which may receive the training data from the knowledge base <NUM> in the form of heterogeneous vectors. The vector processor <NUM> may convert the heterogeneous vectors of training data into homogeneous vectors for use by the artificial intelligence inference engine <NUM>. In this manner, the vector processor <NUM> may increase efficiency of processing data in the form of heterogeneous vectors for the artificial intelligence inference engine <NUM>, thus increasing the speed of training the artificial intelligence inference engine <NUM>. The artificial intelligence inference engine <NUM> may output results or predictions to a user interface <NUM>, which may also serve to input user commands or preferences. As such, the knowledge base <NUM> may be an example of an external device <NUM>, as shown in <FIG>, separate or apart from a data processing system <NUM> (e.g., the artificial intelligence inference engine <NUM>).

In yet another embodiment, the vector processor <NUM> may be incorporated in an autonomous or assisted driving system <NUM>, as illustrated in <FIG>. Specifically, an autonomous or assisted driving control unit <NUM> may include processing circuitry <NUM> that receives sensor information from one or more vehicle sensors <NUM>. For example, the vehicle sensors <NUM> may include a proximity sensor, accelerometer, location sensor, camera, tire pressure sensor, humidity sensor, temperature sensor, and so on. In particular, the processing circuitry <NUM> may include the vector processor <NUM>, which may receive the sensor information from the one or more vehicle sensors <NUM> in the form of heterogeneous vectors. The vector processor <NUM> may convert the heterogeneous vectors of sensor information into homogeneous vectors for use by the autonomous or assisted driving control unit <NUM>. In this manner, the vector processor <NUM> may increase the efficiency of processing data in the form of heterogeneous vectors for the autonomous or assisted driving control unit <NUM>, thus increasing the speed of processing sensor information. The autonomous or assisted driving control unit <NUM> may control a vehicle control system <NUM> based on the processed sensor information. That is, the autonomous or assisted driving control unit <NUM> may operate a steering control <NUM>, a brake <NUM>, a throttle <NUM>, and/or a gear selector <NUM> to cause a vehicle to turn, change speed, stop, accelerate, and so on. In some embodiments, the vector processor <NUM> may convert homogeneous control data to heterogeneous data, which may be processed by and used to control the vehicle control system <NUM>. As such, the vector processor <NUM> may increase the speed of controlling the vehicle control system <NUM> (e.g., in normal operation or to perform evasive or incident avoiding actions). Accordingly, the vehicle sensors <NUM> and/or the vehicle control system <NUM> may be examples of external devices <NUM>, as shown in <FIG>, separate or apart from a data processing system <NUM> (e.g., the autonomous or assisted driving control unit <NUM>).

It should be understood the disclosed examples are not limiting, and that the vector processor <NUM> may be employed in any suitable system or application. For example, in one embodiment, a system comprises: a vector processor to receive a vector of heterogeneous data from or send the vector of heterogeneous data to a device separate from the system, wherein the heterogeneous data include a plurality of data streams having different data types, formats, alignments, or any combination thereof, wherein the vector processor comprises: a grouping memory comprising a plurality of bins to store a plurality of data samples of a plurality of homogeneous data streams, wherein each homogeneous data streams of the plurality of homogeneous data streams comprises a same data type, format, alignment or any combination thereof; a bitformatting functional unit to associate the plurality of data samples in the vector of heterogeneous data with the plurality of homogeneous data streams; and a grouping memory functional unit to write the plurality of data samples to the plurality of bins in parallel.

In an additional or alternative example embodiment, an integrated circuit comprises: processing circuitry to receive a vector of heterogeneous data from or send the vector of heterogeneous data to devices apart from the integrated circuit; and vector processing circuitry to receive the vector of heterogeneous data and generate homogeneous data streams from the vector of heterogeneous data in parallel.

In yet another additional or alternative example embodiment, a vector processor comprises: a grouping memory functional unit; a grouping memory comprising a plurality of bins; and a bitformatting functional unit, wherein the vector processor is to receive a first data sample in a first data arrangement and to provide the first data sample in a second data arrangement different from the first data arrangement after execution by the bitformatting functional unit, the grouping memory, and the grouping memory functional unit.

While the embodiments set forth in the present disclosure may be susceptible to various modifications, implementations, and/or alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it may be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, implementations, and alternatives falling within the scope of the disclosure as defined by the following appended claims.

Claim 1:
A system comprising:
a vector processor (<NUM>) configured to
(a) receive a vector of heterogeneous data from a device separate from the system and generate homogeneous data from the received heterogeneous data in parallel, or
(b) generate a vector of heterogeneous data from received homogeneous data in parallel and send the vector of heterogeneous data to the device separate from the system,
wherein the heterogeneous data include a plurality of data streams having different characteristics or properties, wherein the different characteristics or properties comprise different data types, formats, alignments, or any combination thereof;
wherein the vector processor (<NUM>) comprises:
a grouping memory (<NUM>) comprising a plurality of bins, configured to store a plurality of data samples of a plurality of homogeneous data streams, wherein each homogeneous data stream of the plurality of homogeneous data streams comprises a same data type, format, alignment or any combination thereof;
a bitformatting functional unit (<NUM>) configured to associate the plurality of data samples in the vector of heterogeneous data with the plurality of homogeneous data streams; and
a grouping memory functional unit (<NUM>) configured to write the plurality of data samples to the plurality of bins in parallel.