Patent Description:
A typical PLL contains a phase frequency detector (PFD), a controlled oscillator and a feedback path that includes a feedback divider. The PFD receives two clock inputs; a feedback clock from the feedback divider, and a reference clock. A clock has two edges, a leading or rising edge at the start of the clock period and a negative or edge that marks the end of a half clock period. PFDs detect a phase difference or time delay between rising edges of the reference and feedback clocks. The phase difference, depending on whether it is positive, negative, or zero, determines whether the controlled oscillator increases, decreases, or maintains the frequency fout of the output clock it generates. The feedback divider is positioned in the feedback path between the controlled oscillator and the PFD. The feedback divider, also called a clock divider, receives the output clock, and generates the feedback clock with frequency ffb = fout/Nfb where Nfb is often an integer. If the phase of the reference and feedback clocks are kept in lock step, the reference and feedback clock frequencies should be the same.

Digital PLLs are replacing analog PLLs in many applications. Digital PLLs often employ phase-to-digital convertors, which in turn employ time-to-digital convertor subsystems that convert a phase difference between reference and feedback clocks into a digital representation. Unfortunately, time-to-digital convertors can present new challenges to accurate operation of systems, including digital PLLs, in which they are employed. <CIT> describes a PLL having a phase to digital converter that operates on a positive edge of a reference clock and a digital filter that operates on a negative edge of the reference clock.

The present technology may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

Phase-to-digital convertors generate a digital signal that is proportional to a phase difference between a pair of clock signals. The accuracy of a phase-to-digital convertor can be subject to unexpectedly short or unexpectedly long signal transmission delay within the converter. Disclosed is a phase-to-digital convertor whose accuracy is less sensitive to signal transmission delay. The phase-to-digital convertor of the present disclosure employs a time-to-digital convertor, which includes a subsystem (referred to as the "stopwatch system") that includes an oscillator and at least two counters. The oscillator generates a periodic signal when activated by the rising edge of a first clock. The counters increment their respective counter values at different points during each cycle of the oscillator's periodic signal. When the oscillator is deactivated by the rising edge of a second clock, the phase-to-digital convertor selects one of the counter values based on the point during the last periodic cycle when the oscillator was deactivated. The phase-to-digital convertor uses the selected counter value to generate a digital representation of a phase difference between the first and second clocks. The phase-to-digital convertor of the present disclosure will be described with reference to use within a phase-locked loop, PLL, as defined in the appended claims.

As noted above, the accuracy of phase-to-digital convertors can be sensitive to signal transmission delay. <FIG> illustrate this problem in greater detail. <FIG> is a block diagram of a simple PLL <NUM> that includes a phase-to-digital convertor (PDC) <NUM>. PLL <NUM> generates an output clock OCLK that tracks an externally provided reference clock RCLK. PDC <NUM> receives and compares the rising edges of the reference clock RCLK and a feedback clock FBCLK output of feedback divider <NUM>. PDC <NUM> generates a multi-bit digital value indicative of a phase difference or time delay between the two input clocks. The multi-bit digital value will be referred to herein as the binary time delay (BTD) value.

Digital filter <NUM>, which in one embodiment is a narrowband device, filters BTD, the result of which is subsequently processed by sigma delta modulator (SDM) <NUM>. A controlled oscillator system <NUM> generates an output clock OCLK, the frequency fout of which depends on the output of SDM <NUM>. The output clock OCLK is provided to feedback divider <NUM>, which in turn provides feedback clock FBCLK to PDC <NUM> with frequency ffb = fout/Nfb.

PDC <NUM> includes a phase frequency detector (PFD) <NUM> and time-to-digital converter (TDC) <NUM>. PFD <NUM> detects the phase or time delay between the reference clock RCLK and the feedback clock FBCLK. PFD <NUM> also determines whether the reference clock RCLK is leading or lagging. TDC <NUM> translates this information into the multibit BTD value that represents the magnitude and sign (e.g., leading or lagging) of the phase difference.

An example PFD <NUM> is shown in the schematic diagram of <FIG>. PFD <NUM> includes a pair of input D flip-flops <NUM> and <NUM>. Flip-flop <NUM> receives reference clock RCLK at its clock input, and flip-flop <NUM> receives feedback clock FBCLK at its clock input. The D inputs of flip-flops <NUM> and <NUM> are connected to supply voltage VDD. The Q output of D flip-flop <NUM> is designated as the up signal UP, while the Q output of D flip-flop <NUM> is designated as the down signal DOWN. After flip-flops <NUM> and <NUM> are reset, the UP and DOWN outputs transition to a high voltage level with the rising edges of RCLK and FBCLK, respectively. Both UP and DOWN signals are input to AND gate <NUM> and OR gate <NUM> as shown. The output of AND gate <NUM> is designated as the up and down signal UaD, while the output of OR gate <NUM> is designated as the up or down signal UoD. The clear-inputs of D flip-flops <NUM> and <NUM> receive the UaD output of AND gate <NUM> via signal delay <NUM> and OR gate <NUM>, which also receives the Reset signal. Accordingly, the UP and DOWN outputs of D flip-flops <NUM> and <NUM> are cleared to low when UaD or Reset goes high. Finally, as shown in <FIG> the clock input of D flip-flop <NUM> receives the UP signal, and the D input of flip D flip-flop <NUM> receives the DOWN signal. If feedback clock FBCLK leads reference clock RCLK, the output of flip-flop <NUM>, which is designated as TD_Sign, will go high, and vice versa. Like flip flops <NUM> and <NUM>, flip-flop <NUM> is cleared by Reset, which can be asserted between cycles of the reference clock RCLK.

The operation of PFD <NUM> can best be understood with reference to the timing diagram shown within <FIG>, which shows reference clock RCLK leading feedback clock FBCLK by phase difference ΦΔ. The UP signal output of flip-flop <NUM> transitions to high at the leading edge <NUM> of reference clock RCLK. This in turn causes the UoD output of OR gate <NUM> to go high. Although not shown in <FIG>, TD_Sign output of flip-flop <NUM> stays low at the transition of the UP signal, thus indicating that reference clock RCLK leads the feedback clock FBCLK. The DOWN signal output of flip-flop <NUM> transitions to high at the leading edge <NUM> of feedback clock FBCLK. With both UP and DOWN asserted high, UaD goes high. ΦΔ is represented by the time difference between UoD and UaD as shown. After a delay introduced by delay element <NUM> (and to a lesser extent by OR gate <NUM>), asserted UaD causes the UP and DOWN outputs of flip-flops <NUM> and <NUM>, respectively, to go low at substantially the same point in time. This in turn causes both the UoD and UaD outputs of OR gate <NUM> and AND gate <NUM>, respectively, to go low.

With continuing reference to <FIG>, <FIG> illustrates TDC <NUM>, which generates a multibit binary time delay BTD value that represents the phase difference ΦΔ between reference clock RCLK and feedback clock FBCLK. As will be more fully described, BTD is generated by concatenating three values; TD_Sign, BTD_Upper, and BTD_Lower.

TDC <NUM> includes an example gated ring oscillator (GRO), which in turn includes signal delay elements <NUM> connected in a ring as shown via NAND gate <NUM>. The delay elements <NUM> take form in noninverting buffers, it being understood alternative delay elements are contemplated. The output of buffer <NUM>-<NUM> is fed back to the input of NAND gate <NUM> via feedback path <NUM>. NAND gate <NUM> also receives UoD from PFD <NUM> (not shown in <FIG>). The outputs of NAND gate <NUM> and buffers <NUM>, which are designated as nodes N0 - N15 of the GRO, are at a high voltage level prior to GRO activation.

The GRO is activated when UoD goes high. When activated, the GRO repeats a cycle. <FIG> illustrates the states of nodes N0 - N15 shown in <FIG> as the GRO undergoes a cycle. The GRO cycle consists of a first half cycle followed by a second half cycle as shown in <FIG>.

With continuing reference to <FIG> and <FIG>, when UoD transitions to high, node N0 goes low, and this low voltage level propagates sequentially through buffers <NUM> during the first half of the GRO cycle, which ends when all of nodes N0 - N15 are low. And the second half of the GRO cycle starts after node N15 transitions to low. Because the output of buffer <NUM>-<NUM> is fed back to an input of NAND gate <NUM>, node N0 goes high in response to N15 going low. And this high level propagates sequentially through buffers <NUM>. The GRO cycle ends, and the next begins after the output (i.e., node N15) of buffer <NUM>-<NUM> transitions back to high. It is noted the GRO cycle repeats while UoD is high.

TDC <NUM> includes D flip-flops <NUM> that capture the state of the GRO immediately when the GRO is deactivated. In other words, flip-flops <NUM>-<NUM> - <NUM>-<NUM> capture the voltage levels at nodes N0 - N15, respectively, when UaD transitions from low to high. The Q outputs of flip-flops <NUM>-<NUM> - <NUM>-<NUM> are collectively provided as an input to thermometric-to-binary converter (TBC) <NUM> for translation into BTD_Lower. The table of <FIG> maps BTD_Lower outputs to respective sets of Q inputs for TBC <NUM>. <FIG> shows that BTD_Lower increases sequentially from <NUM> to <NUM> during the first half of the GRO cycle, and increases sequentially from <NUM> to <NUM> during the second half of the GRO cycle.

Counter <NUM> is configured to count the number of completed GRO cycles. Counter <NUM> includes several inputs including INCRT, ENBL and CLR, which receive the output of AND gate <NUM>, the output of flip-flop <NUM>, and the Reset signal, respectively. AND gate <NUM> receives the output of buffer <NUM>-<NUM> and the output of inverter <NUM>, which in turn receives UaD. Counter <NUM> must be enabled before it begins counting. ENBL of counter <NUM> is coupled to the output of flip-flop <NUM>. The D input of flip-flop <NUM> is coupled to supply voltage VDD, and the clock input of flip-flop <NUM> is connected to the output of the inverter <NUM>, which in turn receives the output of buffer <NUM>-<NUM>. Counter <NUM> is enabled when the output of buffer <NUM>-<NUM> first transitions from high to low, which occurs at end of the first half of the initial GRO cycle as noted above. Counter <NUM>, when enabled, will increment its counter value BTD_Upper each time N15 transitions from low to high (i.e., at the end of each second half cycle) until UaD is asserted high. Counter <NUM> will clear BTD_Upper when Reset is asserted high.

TDC <NUM> includes a latch <NUM> that latches the value of BTD_Upper when the GRO is deactivated. Latch <NUM> includes separate inputs CLR and LTCH. The latch input LTCH receives UaD. Accordingly, latch <NUM> latches the BTD_Upper value of counter <NUM> when UaD goes high. Latch <NUM> will clear its stored content when Reset is asserted high.

Combiner <NUM>, as its name implies, combines or concatenates the time delay signal TD_Sign, the latched BTD_Upper value provided by the latch <NUM>, and the BTD_Lower value provided by TBC <NUM>, to create BTD. In other words, combiner <NUM> generates BTD = TD_Sign∥ BTD_Upper∥BTD_Lower.

Most of the time the BTD value output of TDC <NUM> is a substantially accurate digital representation of the phase delay ΦΔ. Unfortunately, under some circumstances TDC <NUM> may generate a less than accurate BTD value. For example, TDC <NUM> may not produce an accurate BTD when the GRO is deactivated (i.e., when UaD transitions to high) near the end of a GRO cycle. To illustrate, <FIG> illustrates a timing diagram that shows oscillator signals near the end of a GRO cycle. In particular the figure shows: the state at nodes N14 and N15, which correspond to the outputs of buffers <NUM>-<NUM> and <NUM>-<NUM>, respectively; UaD, and; the value of BTD_Upper of counter <NUM>. For convenience, relevant components of the TDC <NUM> are shown in <FIG>.

UaD goes high at time t1, which is just before the end of a GRO cycle (i.e., before N15 goes high at time t2). Ideally, counter <NUM> should deactivate immediately when UaD goes high so that counter <NUM> does not increment BTD_Upper after N15 transitions to high at time t2. Further latch <NUM> should capture BTD_Upper immediately when UaD goes high. Due to signal delay, however, counter <NUM> may increment BTD_Upper from M to M+<NUM> at time t3. Depending on signal delay, latch <NUM> will capture BTD_Upper either at time t4, which is before BTD_Upper is incremented, or at time t5, which is after BTD_Upper is incremented. If latch <NUM> captures BTD_Upper at time t5, the resulting BTD value will be higher than it should be and thus a substantially inaccurate representation of ΦΔ.

<FIG> is a timing chart that illustrates another example in which TDC <NUM> may generate an inaccurate representation of ΦΔ. <FIG> shows UaD signal going high at time t2, which is just after the end of a full GRO cycle (i.e., after N15 goes high at time t1). Due to signal delay, counter <NUM> may increment BTD_Upper from M to M+<NUM> at time t3. Latch <NUM> will capture BTD_Upper either at time t4, which is before BTD_Upper is incremented, or at time t5, which is after BTD_Upper is incremented. If latch <NUM> captures BTD_Upper at time t4, the resulting BTD value will be lower than it should be and thus a substantially inaccurate representation of ΦΔ.

The present disclosure provides a TDC that is substantially more accurate when compared to TDC <NUM>. <FIG> is a block diagram illustrating an example PLL employing a PDC, which in turn employs a TDC according to one embodiment of the present disclosure. PLL <NUM> is similar to PLL <NUM> shown in <FIG> in that they both contain digital filter <NUM>, SDM <NUM>, oscillator system <NUM>, and feedback divider <NUM>. PLL <NUM> includes PDC <NUM>, which in turn includes PFD <NUM> and TDC <NUM>. Like TDC <NUM>, TDC <NUM> generates a binary time delay BTD for subsequent processing by digital filter <NUM>. However, TDC <NUM> generates BTD in a substantially different manner.

An example TDC <NUM> is shown in <FIG>. TDC <NUM> includes a stopwatch system <NUM> that concurrently provides a pair of BTD_Upper values (BTD_Upper1 and BTD_Upper2), and Q outputs (Q0 - Q15). As will be shown in later figures, stopwatch system <NUM> includes an oscillator that generates a periodic signal when activated, and separate counters that increment BTD_Upper1 and BTD_Upper2 at different points in the cycle of the periodic signal. At each point in the cycle at least one of the two counter values will be stable or unaffected by signal transmission delay problems like those described above. TDC <NUM> selects a stable counter value to produce binary time delay BTD.

TDC <NUM> includes TBC <NUM>, which generates BTD_Lower as described above. TDC <NUM> also includes a BTD generator <NUM> that generates BTD based on TD_Sign provided by PFD <NUM>, BTD_Lower provided by TBC <NUM>, and one of BTD_Upper1 and BTD_Upper2 provided by stopwatch system <NUM>. BTD generator <NUM> selects one of BTD_Upper1 and BTD_Upper2 for use in generating BTD based upon BTD_Lower. In one embodiment, BTD generator <NUM> generates BTD according to the following conditions:.

<FIG> and <FIG> illustrate alternative embodiments of BTD generator <NUM>. Each of these figures show stopwatch system <NUM> in block diagram form, which generates BTD_Upper1 and BTD_Upper2. TBC <NUM> generates BTD_Lower based upon the Q0 - Q15 outputs of stopwatch system <NUM>. In <FIG>, BTD generator <NUM> includes a multiplexer <NUM> that receives BTD_Upper1 and BTD_Upper2 from stopwatch system <NUM>. Additionally, multiplexer <NUM> receives BTD_Upper1-<NUM> from decrementor <NUM>. Decoder <NUM> provides a select signal that is used by multiplexer <NUM> to select one of the three inputs for output to combiner <NUM>. In the disclosed embodiment decoder <NUM> decodes BTD_Lower to generate the select signal, which is set to: a first state if <NUM> ≤ BTD_Lower ≤ <NUM>; a second state if <NUM> ≤ BTD_Lower ≤ <NUM>, or; a third state if <NUM> ≤ BTD_Lower ≤ <NUM>. Multiplexer <NUM> outputs: BTD_Upper1 if the select signal is set to the first state; BTD_Upper2 if the select signal is set to the second state, or; BTD_Upper1 - <NUM> if the select signal is set to the third state. Combiner <NUM> receives and combines TD_Sign, the output of multiplexer <NUM>, and BTD_Lower to generate BTD.

In <FIG> BTD generator <NUM> includes multiplexer <NUM> that receives BTD_Upper1 and BTD_Upper2 from stopwatch system <NUM>. Decoder <NUM> provides a select signal that is used by multiplexer <NUM> to select one of the two inputs for output to decrementor <NUM>. Decoder <NUM> decodes BTD_Lower to generate the select signal, which is set to: a first state if <NUM> ≤ BTD_Lower ≤ <NUM> or if <NUM> ≤ BTD_Lower ≤ <NUM>, or; a second state if <NUM> ≤ BTD_Lower ≤ <NUM>. Multiplexer <NUM> outputs: BTD_Upper1 if the select signal is set to the first state, or; BTD_Upper2 if the select signal is set to the second state. Decoder <NUM> generates a second signal based upon BTD_Lower, and this second signal is provided to decrementor <NUM>. Decrementor <NUM> may or may not decrement the output of multiplexor <NUM>. When the second signal is asserted, decrementor <NUM> decrements the value provided by multiplexer <NUM>. Otherwise, decrementor <NUM> passes the value it receives from multiplexer <NUM> to combiner <NUM> without modification. In one embodiment, the second signal is asserted only when <NUM> ≤ BTD_Lower ≤ <NUM>. Combiner <NUM> receives and combines TD_Sign, the output of decrementor <NUM>, and BTD_Lower to generate BTD.

<FIG> illustrates relevant aspects of stopwatch system <NUM>, which includes many of the components shown within <FIG>. For example, stopwatch system <NUM> includes the GRO of <FIG>, which in turn includes fifteen non-inverting buffers <NUM> connected in a ring via NAND gate <NUM>, which in turn receives the output of buffer <NUM>-<NUM> and UoD from the PFD <NUM> (not shown in <FIG>). When the GRO is activated by UoD, the GRO repeats a cycle in which each of nodes N0 - N15 oscillates between high and low values. <FIG> illustrates the states of nodes N0 - N15 as the GRO undergoes a complete GRO cycle. Each full GRO cycle consists of a first half cycle followed by a second half cycle.

With continuing reference to <FIG> and <FIG>, stopwatch system <NUM> includes first and second counters <NUM> and <NUM>. Each of the counters will be enabled soon after the GRO is activated. In the embodiment shown, first counter <NUM>, when enabled, will increment its counter value BTD_Upper1 at the end of each first half cycle, and second counter <NUM>, when enabled, will increment its counter value BTD_Upper2 at the end of each second half cycle. It should be noted that counters <NUM> and <NUM> increment their respective counter values at different points in the GRO cycle in alternative embodiments.

Counter <NUM> includes several inputs including INCRT, ENBL and CLR, which receive the output signal of AND gate <NUM>, the Enable1 output signal of flip-flop <NUM>, and the Reset signal, respectively. The clock input of flip-flop <NUM> receives the output of inverter <NUM>-<NUM>. Counter <NUM> resets its counter value BTD_Upper1 to zero each time the Reset signal goes high. Counter <NUM> is enabled when the Enable1 output of flip-flop <NUM> goes high, which occurs the first time node N0 goes low. AND gate <NUM> receives the output NAND gate <NUM> and the output of inverter <NUM>, which in turn receives UaD. When enabled and while UaD is low, counter <NUM> increments BTD_Upper1 each time the output N0 of NAND gate <NUM> transitions from low to high, which occurs at the end of each first half cycle as shown in <FIG>.

Counter <NUM> includes the same inputs as counter <NUM>. INCRT, ENBL and CLR, receive the output signal of AND gate <NUM>, the Enable2 output signal of flip-flop <NUM>, and the Reset signal, respectively. The clock input of flip-flop <NUM> receives the output of inverter <NUM>-<NUM>. Counter <NUM> resets its counter value BTD_Upper2 to zero each time Reset is asserted. Counter <NUM> is enabled when Enable2 goes high, which occurs the first time when node N15 goes low. Counter <NUM> is enabled during the initial first half cycle of the GRO cycle. AND gate <NUM> receives the output buffer <NUM>-<NUM> and the output of inverter <NUM>, which in turn receives UaD. When enabled and while UaD is low, counter <NUM> increments its counter value BTD_Upper2 each time the output N15 of buffer <NUM>-<NUM> transitions from low to high, which occurs at the end of each GRO cycle as shown in <FIG>. Since N0 transitions to high before N15 transitions to high, counter <NUM> increments before counter <NUM> during each GRO cycle. Depending on when the GRO is deactivated, counter <NUM> may not increment after counter <NUM> increments. While counters <NUM> and <NUM> increment when N0 and N15 transition, they can increment when different nodes transition in alternative embodiments. For example, inputs to AND gates <NUM> and <NUM> can be connected to nodes N1 and N14, respectively, which means counters <NUM> and <NUM> would increment with transitions at nodes N1 and N14, respectively.

Stopwatch system <NUM> includes flip-flops <NUM>-<NUM> - <NUM>-<NUM>, which capture the voltage levels at nodes N0 - N15, respectively, when UaD transitions from low to high (i.e., when in the GRO is deactivated). The Q outputs of flip-flops <NUM>-<NUM> - <NUM>-<NUM> are provided as inputs to thermometric-to-binary converter (TBC) <NUM> for translation into BTD_Lower.

Stopwatch system <NUM> also includes a pair of latches circuits <NUM> and <NUM>, which receive the BTD_Upper1 and BTD_Upper2 values, respectively from counters <NUM> and <NUM>, respectively. Counter latch <NUM> includes a clear input CLR that receives Reset, and a latch input LTCH that receives UaD. Counter latch <NUM> latches or captures the value of BTD_Upper1 when the GRO is deactivated (i.e., when UaD transitions from low to high). Counter latch <NUM> includes a clear input CLR that receives Reset and a latch input LTCH that receives BTD_Upper2. Counter latch <NUM> captures the value of BTD_Upper2 when the GRO is deactivated. Both latches <NUM> and <NUM> clear their captured values when Reset is asserted high.

The accuracy of counter <NUM> or <NUM> may be susceptible to signal delay issues at various points in the GRO cycle. However, the accuracy of both will not be susceptible at the same time. In other words, at least one of BTD_Upper1 or BTD_Upper2 will be accurate or stable at all times during the GRO cycle. Based on the point in the cycle at which the GRO is deactivated, TDC <NUM> will select the stable value (i.e., BTD_Upper1 or BTD_Upper2) for subsequent use in generating BTD. Because BTD is generated with a stable BTD_Upper1 or BTD_Upper2, the BTD generated by TDC <NUM> is substantially insensitive to the signal delay issues described with reference to <FIG> and <FIG>. In other words, BTD generator <NUM> will generate an accurate BTD representation of phase delay ΦΔ, regardless of the point during the full GRO cycle at which UaD transitions to high. To illustrate, <FIG> is a diagram similar to that shown within <FIG> and shows the levels of nodes N0, N14, and N15 near the end of a GRO cycle (i.e., when N15 transitions to high). With continuing reference to <FIG>, UaD goes high at time t1, which is between the times at which nodes N14 and N15 go high. One of ordinary skill understands that M, not M+<NUM>, should be used to generate BTD since UaD goes high before the completion of the full GRO cycle. Due to signal delay BTD_Upper2 increments to M+<NUM> at time t3, which is shortly after t2, the time at which N15 goes high. BTD_Upper1 will not increment between times t1 and t4. Latches <NUM> and <NUM> will capture BTD_Upper1 and BTD_Upper2, respectively, in response to the assertion of UaD. Latch <NUM> will capture either BTD_Upper2=M or BTD_Upper2=M+<NUM> depending upon whether latch <NUM> completes its latching operation before or after BTD_Upper2 increments to M+<NUM>. Due to the uncertainty of when latch <NUM> captures BTD_Upper2, the value captured by latch <NUM> should not be used to generate BTD. However, latch <NUM> will capture BTD_Upper1=M+<NUM> regardless of whether latch <NUM> completes its operation before or after time t3. The value for BTD_Lower is most probably <NUM> or <NUM>, and as a result BTD generator <NUM> selects BTD_Upper1-<NUM> = M, for use in generating BTD. The resulting BTD will be a substantially accurate representation of ΦΔ.

<FIG> shows another example in which an unstable value is avoided when generating BTD. In <FIG> BTD_Upper2 increments to M+<NUM> at t4, which occurs after N15 transitions to high at t1 and after N0 transitions to low at t2. BTW_Lower is properly <NUM> after UaD transitions to high at time t3. BTD_Upper2 is slow to increment due to signal delay. As a result, BTD_Upper2 is unstable just after UaD transitions to high (i.e., deactivation of the GRO). BTD_Upper2 should not be used to generate BTD. Fortunately, BRD_Lower1 is stable after time t3. The value for BTD_Lower is most probably <NUM> or <NUM>, and as a result BTD generator <NUM> selects BTD_Upper1 = M+<NUM>, for use in generating BTD. The resulting BTD will be a substantially accurate representation of ΦΔ.

The following are various embodiments of the present disclosure. In one embodiment, a phase-locked loop, PLL, is provided that comprises: a phase to digital converter, PDC, configured to receive and compare edges of a reference clock, Rclk, and a feedback clock, Fbclk derived from an output signal of the PLL and generate a digital output, BTD, that represents a phase difference between the Rclk and the Fbclk; a gated ring oscillator, GRO, arranged to generate a periodic signal, wherein the GRO comprises N signal delay elements connected together in a ring via a logic gate having a second input for receiving a first input signal, wherein a first signal delay element of the ring comprises an input connected to an output (NO) of the logic gate, and wherein a Nth signal delay element of the ring comprises an output (N15) connected to a first input of the logic gate; and wherein the PDC comprises:a convertor connected to the GRO and configured to generate low order bits of the digital output that represent a value that is contained in a range of values comprising first and second non-overlapping ranges, based on captured voltage levels of the outputs of the logic gate and the N signal delay elements responsive to a second input signal; wherein
the PDC further comprises:.

In another embodiment, the PDC further comprises a phase frequency detector, PFD, comprising a first output connected to the second input of the logic gate, wherein the PFD is configured to start the GRO with a first edge of the first clock, and wherein the PFD is configured to stop the GRO with a first edge of the second clock.

In another embodiment, the input of the first counter is connected to the output of the logic gate, and the input of the second counter is connected to the output of the N th signal delay element.

In another embodiment, the PDC further comprises a multiplexor for selecting the first or second digital counter value based on the bits.

In another embodiment, the PDC further comprises a combinational arithmetic circuit that decrements the first digital counter value when selected by the multiplexor, and when the bits represent a value that is contained in a second range of values.

In another embodiment, each of the N signal delay elements is a non-inverting buffer.

In another embodiment, the PLL further comprises: a controlled oscillator configured to generate an output clock with a frequency that depends on the digital output of the PDC; and a feedback divider configured to generate the second clock based on a system clock.

Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein.

Claim 1:
A phase-locked loop, PLL, comprising:
a phase to digital converter, PDC, (<NUM>) configured to receive and compare edges of a reference clock, Rclk, and a feedback clock, Fbclk derived from an output signal of the PLL and generate a digital output, BTD, that represents a phase difference between the Rclk and the Fbclk;
a gated ring oscillator, GRO, arranged to generate a periodic signal, wherein the GRO comprises N signal delay elements (<NUM>-<NUM> ... <NUM>-<NUM>) connected together in a ring via a logic gate (<NUM>) having a second input for receiving a first input signal, wherein a first signal delay element (<NUM>-<NUM>) of the ring comprises an input connected to an output (N0) of the logic gate (<NUM>), and wherein a Nth signal delay element (<NUM>-<NUM>) of the ring comprises an output (N15) connected to a first input of the logic gate (<NUM>); and
wherein the PDC comprises:
a convertor connected to the GRO and configured to generate low order bits of the digital output that represent a value that is contained in a range of values comprising first and second non-overlapping ranges, based on captured voltage levels of the outputs of the logic gate (<NUM>) and the N signal delay elements responsive to a second input signal;
wherein the apparatus is characterized in that the PDC further comprises:
a first counter (<NUM>) comprising an input connected to the output of the logic gate (<NUM>) in a first half cycle of a GRO signal, wherein the first counter (<NUM>) is configured to increment a first digital counter value at an end of each first half cycle of the GRO periodic signal; and
a second counter (<NUM>) comprising an input connected to an input of the logic gate in a second half cycle of the GRO signal, wherein the second counter (<NUM>) is configured to increment a second digital counter value at the end of each cycle of the GRO periodic signal;
wherein the digital output signal comprises a concatenation of the low order bits that represent a value that is contained in a range of values and a selected one of the first and second digital counter values that represent upper order bits, wherein the first digital counter value is selected if the low order bits represent a value contained in the first range and the second counter value is selected if the low order bits represent a value contained in the second range.