Patent Description:
Document <CIT> describes a semiconductor device comprising a through-electrode.

Document <CIT> describes a semiconductor device comprising a via.

Document <CIT> describes a semiconductor device comprising a through-silicon via.

For electrically contacting an integrated circuit of a semiconductor device or another part of a semiconductor device, a common method is to form a through-substrate via, TSV, through the substrate of the device. Therefore, a trench is formed in the substrate. The trench is at least partially filled with an electrically conductive contact material and this contact material is electrically isolated against the substrate. An integrated circuit, which may be arranged at a circuit side of the substrate, can be electrically contacted via the TSV. The TSV can be electrically contacted at a contact side of the substrate facing away from a circuit side of the substrate by means of a solder bump. In this way, the device or the integrated circuit can be electrically contacted from the contact side of the substrate.

For realizing the above-mentioned TSV structures, different material layers are employed. The electrical insulation between the electrically conductive contact material, which typically is a metal, and the substrate, which typically is a silicon substrate, is achieved by means of an insulation layer such as a silicon dioxide layer. In addition, a capping layer may be employed in order to protect certain parts of the TSV and/or remaining parts of the semiconductor device.

However, the different materials employed may possess significantly distinct material properties such as different values for Young's modulus. This may in turn lead to large stress gradients between the different layers which potentially lead to unwanted strain in the finalized devices and hence to an increased cracking probability. Conventional approaches employ a high stress insulation layer in order to compensate for any stress formed in the remaining layers. However, this approach may lead to an increased cracking probability inside the trench of the TSV.

It is an object of the invention to provide an improved concept for a TSV structure with increased stress compensation. This object is achieved with the subject-matter of the independent claim. Further developments and embodiments are described in the dependent claims.

The improved concept is based on the idea of depositing an insulation layer and/or a capping layer during the manufacturing of the TSV as sublayers. These sublayers possess different intrinsic stress such that any unwanted significant strain of the finalized device is prevented, while maintaining an insignificant cracking probability particularly in the TSV region of the finalized device.

An open TSV comprises a substantially planar substrate body including a semiconducting portion and an interlayer dielectric portion disposed adjacent to the semiconducting portion, wherein the semiconducting portion has a surface facing away from the interlayer dielectric portion. The TSV further comprises a trench extending from the surface at least through the semiconducting portion, wherein the trench is characterized by side walls and a bottom wall. The TSV further comprises an insulation layer that is disposed onto at least a portion of the side walls and the surface, a metallization layer that is disposed onto at least a portion of the insulation layer that is disposed in contact with the side walls and onto at least a portion of the bottom wall, and a redistribution layer that is disposed onto at least a portion of the metallization layer and onto a portion of the insulation layer disposed in contact with the surface. The TSV further comprises a capping layer that is disposed onto at least a portion of the metallization layer and onto at least a portion of the redistribution layer.

The insulation layer and/or the capping layer comprise sublayers wherein a first sublayer is arranged between the surface and a second sublayer. The first of the sublayers extends into the trench. The second of the sublayers is disposedin contact with the first sublayer without extending into the trench.

The substrate body, for example, comprises a semiconductor substrate as the semiconducting portion. The semiconductor substrate is a silicon substrate, for instance. The interlayer dielectric portion, for example, comprises metal layers that are insulated from each other by means of an interlayer dielectric such as an oxide and form active circuitry of an integrated circuit, for instance. The interlayer dielectric portion is arranged on a substrate surface of the semiconducting portion. For example, the interlayer dielectric portion is arranged on a processed surface of the semiconducting portion which may be referred to as a top side of the silicon substrate. The TSV is realized by first forming a trench that extends from the surface of the substrate body that faces away from the interlayer dielectric portion through at least the semiconducting portion and optionally partially through the interlayer dielectric portion in a vertical or in a substantially vertical direction. The surface of the semiconducting portion may be referred to as the bottom surface of the substrate. "Vertical" in this context refers to the direction that is perpendicular to said surface of the substrate body. The trench is characterized by side walls that are oriented perpendicular or substantially perpendicular to the surface and by a bottom wall that is parallel or substantially parallel to the surface.

The insulation layer is disposed adjacent to at least a portion of the side walls and to the surface. For example, the insulation layer is a conformal type layer that covers at least a portion of, or optionally the entire, side walls of the trench. The insulation layer may be disposed immediately adjacent to, i.e. directly in contact with, the side walls. Alternatively, an additional layer may be arranged between the side walls of the trench and the portion of the insulation layer that covers the side walls. Furthermore, the insulation layer covers at least a portion of the surface. Analogous to the portion of the insulation layer that covers the side walls, the portion of the insulation layer covering the surface may be either immediately adjacent to, i.e. in direct contact with, the surface or an additional layer may be arranged in between the surface and said portion of the insulation layer.

The metallization layer is disposed adjacent to the bottom wall and to the portion of the insulation layer that is disposed adjacent to the side walls. This means that the metallization layer is disposed within the trench. Analogously to the arrangement of the insulation layer described above, adjacent may indicate an immediate adjacent arrangement or alternatively the arrangement of an additional layer in between the insulation layer and the metallization layer. The metallization layer is of an electrically conductive material such as a metal.

The redistribution layer, like the metallization layer, is also of an electrically conductive material. For example, the material of the metallization layer and that of the redistribution layer are the same. The redistribution layer is disposed immediately adjacent to at least a portion of the metallization layer and adjacent to the portion of the insulation layer that is adjacent to the surface. In particular, the metallization layer is in electrical contact with said portion of the metallization layer and hence may extend partially into the trench. In some embodiments, the metallization layer and the redistribution layer are disposed as a single layer, such as a conformal metal layer, for instance.

The capping layer is disposed such that the metallization layer and the redistribution layer are covered by said capping layer in region of the trench, for instance. The capping layer may be of a material that is the same as a material of the insulation layer. The capping layer may serve as a protective layer and/or as a stress compensation layer that compensates stress formed within and/or across the remaining layers.

The insulation layer and/or the capping layer comprise sublayers. This means that the insulation layer and/or the capping layer is formed by means of depositing at least two sublayers. For example, the insulation layer and/or the capping layer comprise a first and a second of the sublayers wherein the first may be a conformal layer disposed adjacent to a portion of the side walls and to a portion of the surface, while the second may be a non-conformal layer disposed adjacent to the portion of the first sublayer that is disposed adjacent to said portion of the surface.

The sublayers are distinct from each other in terms of material properties. For example, the sublayers are of different materials or they are of the same material but have different material properties that follow from different compositions and/or deposition methods, for instance. For example, the first and the second of the sublayers differ from each other in terms of intrinsic stress, a material composition and/or a microstructure.

Since a high amount of intrinsic stress inside the trench is not desirable as it may lead to an increased cracking probability, the second of the sublayers may be a non-conformal layer as described above and may have an intrinsic stress that is larger than that of the first of the sublayers, which may be a conformal layer. This way, intrinsic stress formed by, i.e. within or across, the other layers of the TSV may be compensated in a manner that a significant strain in the finalized TSV is prevented, while at the same time avoiding significant intrinsic stress inside the trench of the TSV.

In some embodiments, the insulation layer comprises a first and a second insulation sublayer, wherein the first insulation layer is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface. Moreover, the second insulation sublayer is disposed immediately adjacent to the first insulation sublayer and adjacent to at least a portion of the surface.

In these embodiments, the first insulation sublayer corresponds to the first of the sublayers, while the second insulation sublayer corresponds to the second of the sublayers.

In some embodiments, the capping layer comprises a first and a second capping sublayer, wherein the first capping sublayer is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface. Moreover, the second capping sublayer is disposed immediately adjacent to the first capping sublayer and adjacent to at least a portion of the surface.

In these embodiments, the first capping sublayer corresponds to the first of the sublayers, while the second capping sublayer corresponds to the second of the sublayers.

Depending on the manufacturing process, either the insulation or the capping layer may be formed by depositing sublayers as described above. Alternatively, both the insulation layer and the capping layer may both be formed by means of depositing respective sublayers.

The first of the sublayers is arranged between the surface and the second of the sublayers. In some alternative examples not forming part of the invention as claimed, the second of the sublayers is arranged between the surface and the first of the sublayers.

Depending on the manufacturing process, the second of the sublayers may be either deposited before or after the first of the sublayers. This means that the second of the sublayers that may be a non-conformal layer is arranged either at a larger or at a smaller distance from the surface of the substrate body compared to the first of the sublayers that may be a conformal layer.

The first of the sublayers has a tensile type or a compressive type of intrinsic stress, and the second of the sublayers has an intrinsic stress of the respective other type.

Alternatively, the first of the sublayers is characterized by a tensile type or a compressive type of intrinsic stress, and the second of the sublayers is characterized by an intrinsic stress of the same respective type but different magnitude than that of the first of the sublayers.

Depending on what type of intrinsic stress the remaining layers exhibit, the sublayers may be either both of a compressive or tensile type or they have different types of stress. For example, the first of the sublayers is a conformal layer that extends into the trench and has a compressive type of intrinsic stress. However, this stress may be chosen to be smaller than that required in order to compensate for intrinsic stress generated by the remaining layers in order to reduce the cracking probability within the trench. The second of the sublayers in this example, which may be a non-conformal layer, may possess a compressive type of intrinsic stress larger than that of the first of the sublayers in order to compensate for said intrinsic stress generated by the remaining layers. If said intrinsic stress generated by the remaining layers is of a compressive type, the first of the sublayers may still be chosen to have a compressive type as well while the second of the sublayers has a tensile type of intrinsic stress in order to compensate for stress formed within or across the first sublayer and the remaining layers. This scenario is relevant for cases in which an overall small compressive stress is desired within the trench of the TSV for further reduction of the cracking probability.

In some embodiments, the trench extends at least partially into the dielectric portion.

Contact layers may be buried within the dielectric portion. In order for the TSV to electrically contact these contact layers, the trench in these embodiments is required to extend partially into the dielectric portion.

In some embodiments, the insulation layer and/or the capping layer are of a dielectric material such as an oxide.

Dielectric materials such as silicon dioxide or silicon nitride are suitable materials for achieving electrical insulation while keeping the overall manufacturing process simple. Furthermore, the insulation layer and the capping layer may be of the same material.

In some embodiments, the first of the sublayers is of a material that is based on a tetraethoxysilane, TEOS, precursor, and the second of the sublayers is of a material that is based on a silane precursor that is different from TEOS.

In order to achieve the sublayers with different intrinsic stress types and/or values, the sublayers may be formed from different precursors. For example, the first of the sublayers is formed from a TEOS precursor while the second of the sublayers is formed from a different silane precursor.

In some embodiments, the metallization layer and the redistribution layer are arranged between the insulation layer and the capping layer.

The object is further solved by a semiconductor device comprising an open TSV according to one of the embodiments described above. The semiconductor device may be any type of device that employs open TSVs to provide electrical connection of an integrated circuit through a substrate. Examples for such devices include ASICs that are commonly employed in sensors such as environmental sensors and image sensors.

The object is further solved by a method for manufacturing an open through-substrate via, TSV, wherein the method comprises providing a substantially planar substrate body including a semiconducting portion and an interlayer dielectric portion that is disposed adjacent to the semiconducting portion, wherein the semiconducting portion has a surface facing away from the interlayer dielectric portion. The method further comprises forming a trench that extends from the surface at least through the semiconducting portion and is characterized by side walls and a bottom wall, depositing an insulation layer onto at least a portion of the side walls and onto at least a portion of the surface, and depositing a metallization layer onto at least a portion of the insulation layer that is disposed in contact with the side walls and onto at least a portion of the bottom wall. The method further comprises depositing a redistribution layer onto at least a portion of the metallization layer and onto at least a portion of the insulation layer that is disposed in contact with the surface. The method further comprises depositing a capping layer onto at least a portion of the metallization layer and onto at least a portion of the redistribution layer. The insulation layer and/or the capping layer are deposited as sublayers, wherein a first sublayer is arranged between the surface and the second sublayer. The first of the sublayers extends into the trench. The second of the sublayers is deposited in contact with the first sublayer without extending into the trench.

Further embodiments of the method become apparent to the skilled reader from the embodiments of the open through-substrate via described above.

The following description of figures of exemplary embodiments may further illustrate and explain aspects of the improved concept. Components and parts of the open TSV with the same structure and the same effect, respectively, appear with equivalent reference symbols. Insofar as components and parts of the open TSV correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the following figures.

<FIG> shows an exemplary embodiment of an open TSV <NUM> according to the improved concept. In this embodiment, the insulation layer <NUM> comprises a first and a second sublayer <NUM>, <NUM>.

In detail, the embodiment shown comprises a substrate body <NUM> that has a semiconducting portion <NUM> and an interlayer dielectric portion <NUM>. For example, the semiconducting portion <NUM> is a silicon substrate. The semiconducting portion <NUM> comprises a surface <NUM> that is arranged on the side of the semiconducting portion <NUM> that faces away from the interlayer dielectric portion <NUM>. For example, the surface <NUM> is a process surface such as a polished surface. Typically, this surface <NUM> is referred to as the backside of the semiconducting portion <NUM>.

The interlayer dielectric portion <NUM> is arranged adjacent to a further surface, typically a processed surface referred to as the top surface of the semiconducting portion <NUM>, of the semiconducting portion <NUM> that faces away from the surface <NUM>. For example, the interlayer dielectric portion <NUM> is arranged immediately adjacent to the semiconducting portion <NUM>, i.e. the interlayer dielectric portion <NUM> is in direct contact with the semiconducting portion <NUM>. The interlayer dielectric portion <NUM> comprises metal contact layers <NUM> that are insulated from each other by means of an interlayer dielectric such as an oxide and form active circuitry of an integrated circuit, for instance. For illustration purposes, <FIG> only shows a single contact layer <NUM>.

The TSV <NUM> further comprises a trench <NUM> that X tends from the surface <NUM> at least through the semiconducting portion <NUM> and optionally, as illustrated here, partially through the interlayer dielectric portion <NUM>. The trench <NUM> is characterized by side walls <NUM> that extend vertically, i.e. in a direction perpendicular to the surface <NUM>, and a bottom wall <NUM> that extends horizontally, i.e. in a direction parallel to the surface <NUM>. The trench <NUM> may be configured to expose a contact surface of a contact layer <NUM> arranged within the interlayer dielectric portion <NUM>.

The surface <NUM> and the side walls <NUM> are covered by the insulation layer <NUM>. To this end, in this embodiment the insulation layer <NUM> comprises sublayers <NUM>, <NUM>, which may be referred to as the first insulation sublayer and the second insulation sublayer. The first of the sublayers <NUM> in this embodiment is a conformal layer extending into the trench <NUM>, i.e. it covers both at least portions of the surface <NUM> and at least portions of the side walls <NUM> with a substantially identical thickness. The thickness is measured in a perpendicular direction with respect to the surface <NUM> and the side walls <NUM>. The second of the sublayers <NUM> in this embodiment is a non-conformal layer, i.e. it covers at least portions of the surface <NUM> without extending into the trench <NUM>.

The first and the second of the sublayers <NUM>, <NUM> differ from each other in terms of material properties such as intrinsic stress. For example, the first of the sublayers <NUM> is based on a tetraethoxysilane, TEOS, precursor while the second of the sublayers <NUM> is based on a different silane precursor. In this way, the first of the sublayers <NUM> may be characterized by a certain intrinsic stress while the second of the sublayers <NUM> has an intrinsic stress larger than that of the first of the sublayers <NUM>. Hence, the overall intrinsic stress inside the trench <NUM> is capped at a level at which the cracking probability is insignificant. Outside the trench <NUM>, the second of the sublayers <NUM> in this embodiment serves the purpose of compensating intrinsic stress formed within or across the substrate body <NUM> and the remaining layers <NUM>, <NUM>, <NUM>. The sublayers <NUM>, <NUM> can be distinguished and/or identified by means of a short hydrofluoric etch as they possess significantly distinct etch rates.

The insulation layer <NUM> in this embodiment is disposed immediately adjacent to the substrate body <NUM>. In alternative embodiments, additional layers may be arranged in between the insulation layer <NUM> and the substrate body <NUM>. Examples of such additional layers include adhesive promoting layers. Moreover, in alternative embodiments, the first of the sublayers <NUM> may be a non-conformal layer while the second of the sublayers <NUM> may be a conformal layer extending into the trench <NUM>.

The insulation layer <NUM> is covered by a metallization layer <NUM> and a redistribution layer <NUM>. The metallization layer <NUM> is configured to cover at least portions of the insulation layer <NUM> that is disposed adjacent to the side walls <NUM> as well as the bottom wall <NUM>. Optionally, the metallization layer <NUM> is arranged immediately adjacent to, i.e. in contact with, a contact layer <NUM>. The redistribution layer <NUM> is configured to cover at least portions of the metallization layer <NUM> and at least portions of the insulation layer <NUM> that is disposed adjacent to the surface <NUM>. In this embodiment, the metallization layer <NUM> is disposed immediately adjacent to the bottom wall <NUM> and to the insulation layer <NUM>, i.e. the first of the sublayers <NUM>. In alternative embodiments not shown, additional layers may be arranged in between the insulation layer <NUM> and the metallization layer <NUM>.

The redistribution layer <NUM> is arranged immediately adjacent to the metallization layer <NUM>, i.e. said layers are in direct contact with each other. To this end, the redistribution layer extends at least partially into the trench <NUM>. The metallization layer <NUM> and the redistribution layer <NUM> are of an electrically conductive materials such as metals. For example, the metallization layer <NUM> and the redistribution layer <NUM> of the same material such as tungsten. Likewise, the contact layer <NUM> is of an electrically conductive material, such that the metallization layer <NUM> provides an electrically conductive connection between the contact layer <NUM> and the redistribution layer <NUM>, wherein the latter may be in electrical contact with contact pads. Alternatively, the redistribution layer <NUM> may be at least partially exposed in order to form contact pads.

A capping layer <NUM> is disposed adjacent to at least a portion of the metallization layer <NUM> and to at least a portion of the redistribution layer <NUM>. The capping layer <NUM> may serve as a protective layer and/or for stress compensation and may be of a semiconductor material such as an oxide. For example, the material of the capping layer <NUM> corresponds to a material of the insulation layer <NUM>. In this embodiment, the capping layer <NUM> is disposed immediately adjacent to the metallization layer <NUM> and the redistribution layer <NUM>. In alternative embodiments not shown, additional layers may be arranged in between the capping layer <NUM> and the metallization and redistribution layers <NUM>, <NUM>.

The intrinsic stress of the first and the second of the sublayers <NUM>, <NUM> is chosen in such a manner that an overall strain of the TSV <NUM> is prevented. For example, the intrinsic stress of the first of the sublayers <NUM> is chosen in the way that the overall stress resulting from the substrate body <NUM> and all layers <NUM>, <NUM>, <NUM>, <NUM> within the trench <NUM> is substantially zero. The metallization layer <NUM> for example has a tensile type stress, which is typical for tungsten, such that a material of the first of the sublayers <NUM> is chosen to have an intrinsic stress of substantially the same magnitude but of a compressive type. In order to compensate for a global compressive or tensile stress, the second of the sublayers <NUM> is consequently chosen to have a stress necessary for the desired compensation. For example, an intrinsic stress of the second of the sublayers <NUM> is compressive or tensile with a magnitude larger than the intrinsic stress of the first of the sublayers <NUM>. The intrinsic stress is controlled during deposition of the respective sublayer, for instance.

<FIG> shows an alternative exemplary embodiment of an open TSV <NUM>. In this embodiment, the insulation layer <NUM> is a single layer extending into the trench <NUM> in order to cover both the surface <NUM> and the side walls <NUM>. For example, the insulation layer <NUM> in this embodiment is a conformal layer.

However, a thickness of the portion of the insulation layer <NUM> that is disposed adjacent to the surface <NUM> may be different than a thickness of the portion of the insulation layer <NUM> that is disposed adjacent to the side walls <NUM>. For example, the latter thickness is smaller than the former thickness in order to keep the overall stress within the trench <NUM> at a low level.

In contrast to the embodiment shown in <FIG>, in this embodiment the capping layer <NUM> comprises sublayers <NUM>, <NUM>. Similar to the embodiment of <FIG>, the first of the sublayers <NUM>, which may be referred to as the first capping sublayer, in this embodiment is a conformal layer covering the surface <NUM> and extending into the trench <NUM> for covering the sidewalls <NUM> and the bottom wall <NUM>. The first of the sublayers <NUM> in this embodiment is disposed immediately adjacent to the redistribution layer <NUM> and the metallization layer <NUM>. In alternative embodiments not shown, additional layers may be arranged in between said layers.

The second of the sublayers <NUM>, which may be referred to as the second capping sublayer, in this embodiment is a non-conformal layer covering the surface <NUM> without extending into the trench <NUM>. The second of the sublayers <NUM> in this embodiment is disposed immediately adjacent to the first of the sublayers <NUM>. In alternative embodiments not shown, the second of the sublayers <NUM> may be arranged in between the redistribution layer <NUM> and the first of the sublayers <NUM>. In other words, the one of the sublayers that is arranged closest to the surface <NUM> may be a non-conformal layer while the respective other of the sublayers is a conformal layer in said alternative embodiments.

In this embodiment, the sublayers <NUM>, <NUM> of the capping layer <NUM> serve the purpose of stress compensation similar to the sublayers <NUM>, <NUM> of the embodiment shown in <FIG>. For example, the first of the sublayers <NUM> is based on a TEOS precursor while the second of the sublayers <NUM> is based on the different silane precursor analogous to the embodiment shown in <FIG>. In this embodiment, a material of the capping layer <NUM> corresponds to the material of the insulation layer <NUM>, for instance.

<FIG> shows an alternative exemplary embodiment of an open TSV <NUM>. This embodiment combines the sublayer options of the embodiments shown in <FIG>. In detail, both the insulation layer <NUM> and the capping layer <NUM> comprises sublayers <NUM>, <NUM>, <NUM>, <NUM> according to the embodiments described above. Forming both the insulation layer <NUM> and the capping layer <NUM> from sublayers <NUM>, <NUM>, <NUM>, <NUM> may serve the purpose of compensating for a substantial overall stress formed by the substrate body <NUM> and the remaining layers <NUM>, <NUM>.

For example, the material of the first capping sublayer <NUM> corresponds to the material of the first insulation sublayer <NUM> while the material of the second capping sublayer <NUM> corresponds to the material of the second insulation sublayer <NUM>. Alternatively, all sublayers <NUM>, <NUM>, <NUM>, <NUM> are different materials based on different precursors, for instance.

The embodiments shown in the <FIG> as stated represent exemplary embodiments of the TSV <NUM>, therefore they do not constitute a complete list of all embodiments according to the improved concept. Actual TSV configurations may vary from the embodiments shown in terms of shape, size and materials, for example.

Claim 1:
An open through-substrate via (<NUM>), TSV, the through-substrate via (<NUM>) comprising
- a substantially planar substrate body (<NUM>) including a semiconducting portion (<NUM>) and an interlayer dielectric portion (<NUM>) disposed in contact with the semiconducting portion (<NUM>), the semiconducting portion (<NUM>) having a surface (<NUM>) facing away from the interlayer dielectric portion (<NUM>);
- a trench (<NUM>) extending from the surface (<NUM>) at least through the semiconducting portion (<NUM>), the trench (<NUM>) having side walls (<NUM>) and a bottom wall (<NUM>);
- an insulation layer (<NUM>) disposed onto at least a portion of the side walls (<NUM>) and the surface (<NUM>);
- a metallization layer (<NUM>) disposed onto at least a portion of the insulation layer (<NUM>) that is disposed in contact with the side walls (<NUM>) and onto at least a portion of the bottom wall (<NUM>);
- a redistribution layer (<NUM>) disposed onto at least a portion of the metallization layer (<NUM>) and onto a portion of the insulation layer (<NUM>) that is disposed in contact with the surface (<NUM>); and
- a capping layer (<NUM>) disposed onto at least a portion of the metallization layer (<NUM>) and onto at least a portion of the redistribution layer (<NUM>); wherein
- the insulation layer (<NUM>) and/or the capping layer (<NUM>) comprise a first sublayer (<NUM>, <NUM>) and a second sublayer (<NUM>, <NUM>), wherein the first sublayer (<NUM>, <NUM>) is arranged between the surface (<NUM>) and the second sublayer (<NUM>, <NUM>);
- the first sublayer (<NUM>, <NUM>) extends into the trench;
- the second sublayer (<NUM>, <NUM>) is disposed in contact with the first sublayer (<NUM>, <NUM>) without extending into the trench (<NUM>);
- the first sublayer (<NUM>, <NUM>) has a tensile type or a compressive type of intrinsic stress; and
- the second sublayer (<NUM>, <NUM>) has an intrinsic stress of the respective other type or of the same type but different magnitude than that of the first sublayer (<NUM>, <NUM>).