Patent Description:
In safety-critical systems, at least some of the components of the system must meet safety goals sufficient to enable the system as a whole to meet a level of safety deemed necessary for the system. For example, in most jurisdictions, seat belt retractors in vehicles must meet specific safety standards in order for a vehicle provided with such devices to pass safety tests. Likewise, vehicle tyres must meet specific standards in order for a vehicle equipped with such tyres to pass the safety tests appropriate to a particular jurisdiction. Safety-critical systems are typically those systems whose failure would cause a significant increase in the risk to the safety of people or the environment.

Data processing devices often form an integral part of safety-critical systems, either as dedicated hardware or as processors for running safety-critical software. For example, fly-by-wire systems for aircraft, driver assistance systems, railway signalling systems and control systems for medical devices would typically all be safety-critical systems running on data processing devices. Where data processing devices form an integral part of a safety-critical system it is necessary for the data processing device itself to satisfy safety goals such that the system as a whole can meet the appropriate safety level. In the automotive industry, the safety level is normally an Automotive Safety Integrity Level (ASIL) as defined in the functional safety standard ISO <NUM>.

Increasingly, data processing devices for safety-critical systems comprise a processor running software. Both the hardware and software elements must meet specific safety goals. Some software failures can be systematic failures due to programming errors or poor error handling. These issues can typically be addressed through rigorous development practices, code auditing and testing protocols. Even if systematic errors could be completely excluded from a safety-critical system, random errors can be introduced into hardware, e.g. by transient events (e.g. due to ionizing radiation, voltage spikes, or electromagnetic pulses). In binary systems transient events can cause random bit-flipping in memories and along the data paths of a processor. The hardware may also have permanent faults.

The safety goals for a data processing device may be expressed as a set of metrics, such as a maximum number of failures in a given period of time (often expressed as Failures in Time, or FIT), and the effectiveness of mechanisms for detecting single point failures (Single Point Failure Mechanisms, or SPFM) and latent failures (Latent Failure Mechanisms, or LFM). There are various approaches to achieving safety goals set for data processing devices: for example, by providing hardware redundancy so that if one component fails another is available to perform the same task, or through the use of check data (e.g. parity bits or error-correcting codes) to allow the hardware to detect and/or correct for minor data corruptions.

For example, data processors can be provided in a dual lockstep arrangement <NUM> as shown in <FIG> in which a pair of identical processing cores <NUM> and <NUM> are configured to process a stream of instructions <NUM> in parallel. The output of either one of the processing cores (<NUM>) may be used as the output <NUM> of the lockstep processor. When the outputs of the processing cores <NUM> and <NUM> do not match, a fault can be raised to the safety-critical system. A delay <NUM> can be introduced on the input to one of the cores so as to improve the detection probability of errors induced by extrinsic factors such as ionizing radiation and voltage spikes (with typically a corresponding delay <NUM> being provided on the output of the other core). However, since a second processing core is required, dual lockstep processors are expensive in that they necessarily consume double the chip area compared to conventional processors and consume approximately twice the power.

Advanced driver-assistance systems and autonomous vehicles may incorporate data processing systems that are suitable for such safety-critical applications which have significant graphics and/or vector processing capability. However, the increases in the area and power consumption (and therefore cost) of implementing a dual lockstep processor might not be acceptable or desirable. For example, driver-assistance systems often provide computer-generated graphics illustrating hazards, lane position, and other information to the driver. Typically, this will lead the vehicle manufacturer to replace a conventional instrument cluster with a computer-generated instrument cluster which also means that the display of safety-critical information such as speed and vehicle fault information becomes computer-generated. Such processing demands can be met by graphics processing units (GPUs). However, in the automotive context, advanced driver-assistance systems typically require a data processing system which meets ASIL level B of ISO <NUM>.

For example, in the automotive context, graphics processing systems may be used to render an instrument cluster for display at a dashboard display screen. The instrument cluster provides critical information to the driver, such as vehicle speed and details of any vehicle faults. It is important that such critical information is reliably presented to the driver and vehicle regulations would typically require that the critical information is rendered in a manner which satisfies a predefined safety level, such as ASIL B of the ISO <NUM> standard.

<FIG> illustrates an instrument cluster <NUM>. The instrument cluster comprises a speedometer <NUM> in the form of a traditional dial having speed values <NUM> around the edge of the dial and a needle <NUM> whose angular orientation indicates the current speed of the vehicle. The instrument cluster further comprises an oil temperature gauge <NUM>, an information icon <NUM> (e.g. indicating the selected radio station), a non-critical warning icon <NUM> (e.g. indicating a fault with the air conditioning system), and a critical warning icon <NUM> (e.g. indicating a serious engine problem). It may be necessary to render the instrument cluster <NUM> in a manner which satisfies a mandated safety level, such as ASIL B of the ISO <NUM> standard.

Autonomous vehicles must in addition process very large amounts of data (e.g. from RADAR, LIDAR, map data and vehicle information) in real-time in order to make safety-critical decisions. Graphics processing units can also help meet such processing demands but safety-critical systems in autonomous vehicles are typically required to meet the most stringent ASIL level D of ISO <NUM>.

<CIT> relates to checking frames of a graphical user interface by a real-time operating system. <CIT> relates to displaying safety-critical and safety-uncritical image content, for example with regard to the ISO <NUM> standard in the field of transport.

According to a first aspect of the present invention there is provided a method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering, the method comprising: generating configuration data for initialising rendering of safety critical graphical data at the graphics processing unit, said configuration data specifying a configuration to be adopted by the graphics processing unit; causing an instruction comprising the configuration data for initialising rendering and a request for response from the graphics processing unit to be provided to the graphics processing unit; initialising a timer, said timer being configured to expire after a time period; monitoring, during the time period, for a response from the graphics processing unit; configuring the graphics processing unit in accordance with the configuration data for initialising rendering; determining whether the graphics processing unit is correctly configured in accordance with the configuration data; and determine, by a safety controller external to the graphics processing unit, that an initialisation error has occurred if:(i) it is determined that the graphics processing unit is not correctly configured in accordance with the configuration data; or (ii) no response is received from the graphics processing unit before the timer expires.

The safety controller may cause the graphics processing unit to be reset in response to determining that the initialisation error has occurred.

The method may further comprise: proceeding with rendering of safety critical graphical data at the graphics processing unit if: (i) it is determined that the graphics processing unit is correctly configured in accordance with the configuration data; and (ii) the response from the graphics processing unit is received by the safety controller.

The configuration data may comprise one or more register entries to be written into one or more registers of the graphics processing unit, said configuration data specifying a configuration to be adopted by the graphics processing unit.

The configuring of the graphics processing unit in accordance with the configuration data may comprise one of: the safety controller writing the one or more register entries into the one or more registers; or a firmware of the graphics processing unit writing the one or more register entries into the one or more registers.

Determining whether the graphics processing unit has been correctly configured in accordance with the configuration data may comprise: reading the one or more register entries corresponding to the configuration data back from each of the one or more registers of the graphics processing unit after configuring the graphics processing unit; and comparing the one or more register entries read back from each register with an expected data entry for that register specified by the configuration data.

Determining whether the graphics processing unit has been correctly configured in accordance with the configuration data may comprise: reading the one or more register entries corresponding to the configuration data back from each of the one or more registers of the graphics processing unit after configuring the graphics processing unit; performing a checksum over the one or more register entries read back from the one or more registers; performing a checksum over the configuration data; and comparing the results of said checksums.

The checksum may be dependent upon the location of the one or more register entries within the one or more registers.

According to a second aspect of the present invention there may be provided a graphics processing system comprising a graphics processing unit configured to perform safety-critical rendering and a safety controller for the graphics processing system, the safety controller being external to the graphics processing unit, in which the safety controller is configured to: generate configuration data for initialising rendering of safety critical graphical data at the graphics processing unit, said configuration data specifying a configuration to be adopted by the graphics processing unit;.

The graphics processing unit may be configured to: proceeding with rendering of safety critical graphical data if: (i) it is determined that the graphics processing unit is correctly configured in accordance with the configuration data; and (ii) the response from the graphics processing unit is received by the safety controller.

The graphics processing system may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, the graphics processing system. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture the graphics processing system. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the graphics processing system.

There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable integrated circuit description that describes the graphics processing system; a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing system; and an integrated circuit generation system configured to manufacture the graphics processing system according to the circuit layout description.

There may be provided computer program code for performing a method as described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the methods as described herein.

The present invention is described by way of example with reference to the accompanying drawings. In the drawings:.

Embodiments are described by way of example only.

The present disclosure relates to methods and graphics processing systems for initialising safety-critical rendering.

A graphics processing system <NUM> is shown in <FIG>. Graphics processing system <NUM> comprises at least one graphics processing unit (GPU) <NUM>. GPU <NUM> may be suitable for rendering the instrument cluster <NUM> shown in <FIG>. GPU <NUM> may comprise hardware components (e.g. hardware processing units) and software components (e.g. firmware and procedures and tasks for execution at the hardware processing units). The operation and arrangement of the GPU units will vary depending on the particular architecture of the GPU.

GPU <NUM> may comprise one or more processing units <NUM>, labelled in <FIG> as PU0, PU1 and PU(n). There may be any number of processing units in GPU <NUM>. GPU <NUM> may also comprise firmware <NUM>. Firmware <NUM> may be embodied in software, hardware, or any combination of software and hardware. For example, firmware <NUM> may be software being executed using hardware processing logic. Firmware <NUM> which may, for example, perform low-level management of the GPU and provide an interface for instructions directed to the GPU. In some arrangements, GPU <NUM> may be configured to execute software in the form of functions, routines and other code arranged for execution at units of the GPU (e.g. its processing units <NUM> and/or firmware <NUM>).

GPU <NUM> may also comprise a register bank <NUM> comprising one or more registers. Register bank <NUM> may be accessible by the processing units <NUM>. Data for the processing units <NUM> may be stored within the register bank <NUM>, and read by those processing units <NUM>. Said data may include data to be processed by the processing units <NUM>, and/or configuration data specifying a configuration to be adopted by the processing units <NUM>. For example, said configuration may determine how one of the processing units <NUM> processes data, such as during the rendering of graphical data. The register bank <NUM> may be populated and managed by firmware <NUM>. That is, firmware <NUM> may have permission to read from and write into the one or more registers in the register bank <NUM>. GPU <NUM> may also comprise any other form of memory (not shown). Said memory may comprise any type of memory, such as caches, or buffers.

GPU <NUM> may also comprise a reset unit <NUM> configured to cause a reset, such as a hardware recovery reset, of the GPU <NUM>. The reset may involve returning some or all of the GPU flip-flops to a known safe state, and/or invalidating some or all data stored in memory, such as register bank <NUM>, within the GPU <NUM>. The reset may eliminate certain errors, such as those causing a GPU to malfunction. The reset may be instructed by the GPU <NUM> itself. Alternatively, said reset may be caused by a command <NUM> sent from an external entity, such as host data processing system <NUM>.

GPU <NUM> may comprise various other functional elements for, by way of example, processing data, communicating with external devices such as host data processing system <NUM>, and supporting the processing performed at the one or more processing units <NUM>.

Graphics processing system <NUM> may also comprise a driver <NUM> for the GPU <NUM>. For example, the driver <NUM> could be a software driver. The driver <NUM> may provide an interface to the GPU <NUM> for processes (e.g. software applications) running at a data processing system. In the example shown in <FIG>, graphics processing system <NUM> comprises a host data processing system <NUM>. One or more processes <NUM> may run on host data processing system <NUM>. These processes <NUM> are labelled in <FIG> as A0, A1, A(n). There may be any number of processes <NUM> running on the host data processing system <NUM>. One or more processes <NUM> may interact <NUM> with the GPU <NUM> by means of the driver <NUM>. The host data processing system <NUM> may comprise one or more processors (e.g. CPUs - not shown) at which the processes <NUM> and driver <NUM> are executed. A graphics application programming interface (API) <NUM> (e.g. OpenGL) may be provided at the driver <NUM> by means of which the processes <NUM> can submit rendering calls. Driver <NUM> may be a software component of the host data processing system <NUM>.

The API <NUM> may be arranged to receive draw calls from processes <NUM> so as to cause the GPU <NUM> to render a scene. For example, the API may be an OpenGL API and a process may be an application arranged to issue OpenGL draw calls so as to cause the GPU to render the instrument cluster shown in <FIG> to a display screen at the dashboard of a vehicle. Driver <NUM> also comprises a safety controller <NUM>, which is discussed in further detail herein.

In the example depicted in <FIG>, driver <NUM> generates command and/or control instructions so as to cause the GPU <NUM> to effect the draw calls submitted to the API <NUM> by a process <NUM>. The instructions may pass data defining the scene to be rendered to the GPU <NUM> in any suitable manner - e.g. as a reference to the data in memory. As shown in <FIG>, said instructions may be sent <NUM> to one or more buffers <NUM> in memory <NUM>. GPU <NUM> may read <NUM> instructions from memory <NUM>. Memory <NUM> may be provided at host data processing system <NUM>. Memory <NUM> may also include a buffer <NUM> for receiving instructions returning from GPU <NUM>. The buffers may be circular buffers.

Graphics processing unit <NUM> may be, for example, any kind of graphical and/or vector and/or stream processing unit. GPU <NUM> may comprise a rendering pipeline for performing geometry processing and/or fragment processing of primitives of a scene. Each processing unit <NUM> may be a different physical core of a GPU.

The following examples are described with reference to tile-based rendering techniques, however it is to be understood the that graphics processing system could instead or additionally be capable of other rendering techniques, such as immediate mode rendering or hybrid techniques that combine elements of both tile-based and immediate mode rendering.

A graphics processing system <NUM> configured in accordance with the principles herein may have any tile-based architecture - for example, the system could be operable to perform tile based deferred rendering. Each processing unit <NUM> depicted in <FIG> may be able to process a tile independently of any other processing unit and independently of any other tile.

Tile-based rendering systems use a rendering space which is subdivided into a plurality of tiles. As is known in the art, tiles can be any suitable shape and size, e.g. rectangular (including square) or hexagonal. A tile of the rendering space may relate to a portion of a render target, e.g. representing a frame which is to be rendered at a graphics processing system. A frame may be all or part of an image or video frame. In some examples, the render output is not a final image to be displayed, but instead may represent something else, e.g. a texture which can subsequently be applied to a surface when rendering an image which includes that texture. In the examples described below, the render output is a frame representing an image to be displayed, but it is to be understood that in other examples, the render output can represent other surfaces, such as textures or environment maps, etc..

Tile-based rendering systems generally perform two distinct phases of operation: (i) a geometry processing phase in which geometry (e.g. primitives) is processed to determine, for each tile of the rendering space, which items of geometry may be relevant for rendering that tile (e.g. which primitives at least partially overlap the tile), and (ii) a rendering phase (or "fragment processing phase") in which geometry relevant for rendering a particular tile is processed so as to render the tile - for example, to produce pixel values for the pixel positions in the tile, which can then be output from the rendering system, e.g. for storage in a buffer (such as a frame buffer) and/or for display. Processing geometry relevant to a tile may comprise, for example, generating primitive fragments by sampling the primitives at the sample positions of the tile, and determining which of the fragments are visible and determining how the fragments affect the appearance of the pixels. There may be a one-to-one relationship between the sample positions and the pixels. Alternatively, more than one sample position may relate to each pixel position, such that the final pixel values can be produced by combining rendered values determined for a plurality of sample positions. This can be useful for implementing anti-aliasing.

A graphics processing unit (such as GPU <NUM>) may be configured to perform part or all of any aspect of graphics processing in the geometry processing phase and in the rendering phase, including, for example, tiling, geometry processing, texture mapping, shading, depth processing, vertex processing, tile acceleration, clipping, culling, primitive assembly, colour processing, stencil processing, anti-aliasing, ray tracing, pixelization and tessellation.

Geometry processing logic and fragment processing logic may share resources of a graphics processing unit (such as GPU <NUM>). For example, the processing units of a graphics processing unit (such as processing units <NUM> of GPU <NUM>) may be used to implement part of both the geometry processing logic and the fragment processing logic, e.g. by executing different software instructions on execution units of the processing units. Processing units (such as processing units <NUM>) may be configured to perform SIMD processing.

A graphics processing system configured in accordance with the principles described herein may be arranged to render any kind of scene.

Returning to <FIG>, a graphics processing system <NUM> in accordance with the principles described herein comprises at least one graphics processing unit (GPU) <NUM>. The graphics processing system <NUM> also comprises a safety controller <NUM>. Safety controller <NUM> may be embodied in hardware (e.g. fixed-function hardware), software or any combination thereof (e.g. as a software process running at general purpose hardware). Safety controller <NUM> may be in communication with GPU <NUM>. Safety controller <NUM> may communicate with GPU <NUM> in any suitable manner. Safety controller <NUM> may be present in any suitable location. In one example, safety controller <NUM> and GPU <NUM> may be part of the same system on chip architecture. In <FIG>, safety controller <NUM> is shown as being comprised within host data processing system <NUM>. Safety controller <NUM> may be a component of driver <NUM>, which provides an interface to the GPU <NUM> for processes <NUM> (e.g. software applications) running at the host data processing system <NUM>.

Safety controller <NUM> may be configured to cause safety checks for GPU <NUM> to be performed. A safety check may be performed at any time. In an example, a safety check is performed when initialising the rendering of graphical data. For example, a safety check may be performed when the GPU <NUM> is initialised to perform the rendering of a frame of graphical data. Said frame may include data for safety-critical rendering. A safety check may be performed every time that the GPU <NUM> is initialised to perform the rendering of a frame of safety-critical data, or on a subset of those occasions. In another example, a safety check may be performed when the GPU <NUM> is initialised to perform the rendering of a tile of graphical data. Said tile may include data for safety-critical rendering. A safety check may be performed every time that the GPU <NUM> is initialised to perform the rendering of a tile of safety-critical data, or on a subset of those occasions. A safety check may be performed when initialising geometry processing, fragment processing, or both geometry processing and fragment processing.

<FIG> is a flow diagram <NUM> for a method of initialising safety-critical rendering at a graphics processing unit within a graphics processing system in accordance with the principles described herein.

One type of safety check caused by safety controller <NUM> may involve verifying whether a GPU <NUM> has been correctly configured to perform safety critical rendering. In order to perform this safety check, configuration data for initialising rendering of safety critical graphical data at the graphics processing unit is generated <NUM>.

Said configuration data may, when read by a processing unit <NUM> of GPU <NUM>, cause that processing unit <NUM> to adopt a specific configuration. For example, the configuration data may cause a processing unit <NUM> to be configured to perform a specific processing task, or series of processing tasks, on received data (such as graphical data). Said configuration data may also mandate from where (e.g. an address in memory <NUM>) that a processing unit <NUM> is to retrieve data to be processed, and/or how intermediate data or final output generated during rendering is to be handled (e.g. stored and/or reported).

The configuration data may comprise one or more register entries to be written into one or more registers in register bank <NUM>. Said register entries may comprise register data. The configuration data may dictate a specified configuration for the register entries. For example, the configuration data may dictate that specific register entries are to be written into specific registers, and/or define specific relationships between the register entries that are to be written into each register within register bank <NUM>. In a simple example, configuration data may include register entries <NUM> to <NUM> to be written in ascending numerical order into registers A to J (not shown).

Safety controller <NUM> may generate one or more instructions comprising said configuration data. Said instruction(s) may be sent to GPU <NUM> via buffer <NUM> in memory <NUM>. Configuration data relating to safety critical rendering may bypass the queue in buffer <NUM>, such that it can be read into GPU <NUM> more quickly.

The configuration data is received <NUM> at the graphics processing unit (e.g. GPU <NUM>). For example, the configuration data may be comprised within an instruction that is read from memory <NUM> into GPU <NUM>.

The graphics processing unit (e.g. GPU <NUM>) is configured <NUM> in accordance with the configuration data. In an example, said configuration data may be sent <NUM> to firmware <NUM> of GPU <NUM> - and the firmware <NUM> may be responsible for writing the configuration data into the register bank <NUM>. In another example, the safety controller <NUM> may cause the configuration data to be written <NUM> directly into the register bank <NUM>. In this example, configuration data may also be sent <NUM> to firmware <NUM> of GPU <NUM> (the reasons for which are explained in the following paragraphs). A graphics processing unit may be considered to be configured in accordance with the configuration data once said configuration data has been written into the registers. The configuration data, once written into the registers, may cause the GPU to operate in one or more different modes, cause different combinations of components of the GPU to be switched on or off, and/or cause any other change to the configuration of the GPU.

According to the principles described herein, it is then determined <NUM> whether the graphics processing unit (e.g. GPU <NUM>) has been correctly configured in accordance with the configuration data. This step may involve determining whether the configuration data has been correctly written into the one or more registers of register bank <NUM>. For example, it may be determined whether register entries specified in the configuration data have been written into the register bank <NUM> in the specified configuration.

In an example, the safety controller <NUM> may compare the configuration data with the outcome of the configuration step. The comparison may be performed in any suitable manner.

In an example, safety controller <NUM> may read back the contents (e.g. the set of data entries) of each of the registers in register bank <NUM> and compare their contents to the expected contents according to the configuration data. That is, for each register, the safety controller <NUM> may check whether the read register entry matches the expected register entry for that register. In one example, this comparison may be completed before the register entries are subsequently modified as a result of rendering performed by GPU. That is, before the contents of the registers are accessed by a processing unit <NUM> in order to perform rendering. In another example, a snapshot of the register bank may be stored in the host data processing system <NUM>. The snapshot may be a read back of data entries in the registers of the register bank <NUM> to a memory external to the GPU (such as memory <NUM> in the host data processing system <NUM>). A snapshot of the register bank <NUM> may be published and sent <NUM>, <NUM> to the safety controller <NUM> (e.g. via memory <NUM>) for comparison to the configuration data. In this example, the snapshot of the register bank <NUM> may be verified by comparison to the expected contents according to the configuration data. That is, for each register, the safety controller <NUM> may check whether the register entry found in the snapshot matches the expected register entry for that register. Whilst this comparison is being performed, the contents of the actual registers may be used for rendering.

In another example, the safety controller <NUM> may perform the comparison by performing a checksum over the contents (e.g. the set of data entries) of the registers, and comparing that to an equivalent checksum performed over the configuration data. The checksum may be dependent upon the location of the data within the registers. In other words, the checksum may not be location invariant. That is, the checksum calculation may account for both the values of the stored register entries and their location within the register bank <NUM>. In other words, the checksum may return different results when (i) the expected register entries are stored in the correct register locations, and (ii) the expected register entries are stored in the incorrect register locations. In an example, safety controller <NUM> may read back the contents of each of the registers in register bank <NUM> in order for a checksum to be performed. In another example, a snapshot of the register bank <NUM> may be stored by a memory external to the GPU (such as memory <NUM> in the host data processing system <NUM>) in order for a checksum to be performed.

In an example, firmware <NUM> may compare the configuration data with the outcome of the configuration step. The comparison may be performed in any suitable manner.

In an example, firmware <NUM> may read back the contents (e.g. the set of data entries) of each of the registers in register bank <NUM> and compare their contents to the expected contents according to the configuration data. That is, for each register, the firmware may check whether the read register entry matches the expected register entry for that register. In one example, this comparison may be completed before the register entries are subsequently modified as a result of rendering performed by GPU. That is, before the contents of the registers are accessed by a processing unit <NUM> in order to perform rendering. In another example, a snapshot of the register bank may be stored by firmware <NUM>. The snapshot may be a read back of data entries in the registers of the register bank <NUM> to an internal core memory (not shown) exclusive to the firmware <NUM>. In this example, the snapshot of the register bank <NUM> may be verified by comparison to the expected contents according to the configuration data. That is, for each register, the firmware may check whether the register entry found in the snapshot matches the expected register entry for that register. Whilst this comparison is being performed, the contents of the actual registers may be used for rendering.

In another example, the firmware <NUM> may perform the comparison by performing a checksum over the contents (e.g. the set of data entries) of the registers, and comparing that to an equivalent checksum performed over the configuration data. The checksum may be dependent upon the location of the data within the registers. In other words, the checksum may not be location invariant. That is, the checksum calculation may account for both the values of the stored register entries and their location within the register bank <NUM>. In other words, the checksum may return different results when (i) the expected register entries are stored in the correct register locations, and (ii) the expected register entries are stored in the incorrect register locations. In an example, firmware <NUM> may read back the contents of each of the registers in register bank <NUM> in order for a checksum to be performed. In another example, a snapshot of the register bank <NUM> may be stored by firmware <NUM> in order for a checksum to be performed.

In some examples, the GPU firmware (e.g. firmware <NUM>) sets up a flag or status value to confirm that the determination step has been completed. Different flags or status values may be used to indicate whether it has been determined that the GPU <NUM> has been correctly or incorrectly configured.

In some examples, any combination of two or more of the comparisons described herein may be performed in order to determine whether the graphics processing unit (e.g. GPU <NUM>) has been correctly configured in accordance with the configuration data.

According to the principles described herein, it is determined <NUM> that an initialisation error has occurred if it is determined that the graphics processing unit has not been correctly configured in accordance with the configuration data.

In response to determining that an initialisation error has occurred, the safety controller may cause the graphics processing unit to be reset. For example, referring to <FIG>, if the firmware <NUM> determines that the GPU <NUM> has not been configured in accordance with the configuration data, it may inform <NUM> the host data processing system of the initialisation error via returning buffer <NUM> in memory <NUM>. Safety controller <NUM> may then cause GPU <NUM> to be reset by commanding <NUM> reset unit <NUM>.

A hardware recovery reset is an example of such a reset. A reset may involve returning some or all of the GPU flip-flops to a known safe state, and/or invalidating some or all data stored in memory, such as register bank <NUM>, within the GPU <NUM>. A reset may eliminate certain errors, such as those causing a GPU to malfunction (e.g. causing the GPU to be incorrectly configured). Resetting the GPU in this way may allow errors in configuration to be corrected before they can cause errors in the graphical rendering of a frame or tile.

The reset may comprise any other type of reset. For example, the reset may be a soft reset. A soft reset may comprise resetting the hardware components of the GPU <NUM>. For example, during a soft reset, the processing units <NUM> may be re-initialised and returned to a known state, and register entries in register bank <NUM> may be invalidated. During a soft reset, the software components of the GPU <NUM>, such as firmware <NUM>, may continue to run. In contrast, a reset may be a hard reset. A hard reset may comprise resetting both the hardware and software components of GPU <NUM>. For example, during a hard reset, the processing units <NUM> and firmware <NUM> may be re-initialised and returned to a known state, and register entries in register bank <NUM> may be invalidated may be invalidated or cleared. Any other type of reset that comprises invalidating the register entries in register bank <NUM> and resetting any other combination of the components of a graphics processing unit (such as GPU <NUM>) is also possible.

In other examples, the safety controller <NUM> may inform other entities external to the GPU <NUM> that an initialisation error has occurred. For example, the safety controller may communicate the detected initialisation error to an application <NUM> running on the host data processing system <NUM>, such as the application that submitted the rendering call with which the initialisation error is associated.

The graphics processing unit may proceed to perform rendering prior to the safety check described with reference to <FIG> being completed. If the safety check determines that the graphics processing unit has been configured in accordance with the configuration data, the rendering of graphical data may proceed. For example, the rendering of graphical data that has already begun may continue unaffected or the rendering of graphical data may not begin until the safety check has been completed.

Another type of safety check caused by safety controller <NUM> is described with reference to <FIG>.

<FIG> is a flow diagram <NUM> for another method of initialising safety-critical rendering at a graphics processing unit within a graphics processing system in accordance with the principles described herein.

An instruction for initialising rendering of safety critical graphical data at the graphics processing unit is written into <NUM> the graphics processing unit (such as GPU <NUM>). As described previously, a safety check may be performed when the GPU <NUM> is initialised to perform the rendering of a frame of graphical data. Said frame or tile may include data for safety-critical rendering. A safety check may be performed every time that the GPU <NUM> is initialised to perform the rendering of a frame of safety-critical data, or on a subset of those occasions. In another example, a safety check may be performed when the GPU <NUM> is initialised to perform the rendering of a tile of graphical data. Said tile may include data for safety-critical rendering. A safety check may be performed every time that the GPU <NUM> is initialised to perform the rendering of a tile of safety-critical data, or on a subset of those occasions. A safety check may be performed when initialising geometry processing, fragment processing, or both geometry processing and fragment processing.

The instruction for initialising rendering of safety critical graphical data comprises a request for a response from the GPU. The request for a response may require the GPU to respond immediately upon reading the request, or on completion of a predetermined task. The request for a response may be embedded in the instruction as a flag. For example, the flag may be present in an instruction header. Said instruction header may be in a kick command of the instruction. A kick command is the name given to an instruction or part of an instruction that instructs the GPU to begin processing a render or part of a render.

A timer may be initialised <NUM>. Returning to <FIG>, a timer <NUM> is schematically shown as a component of the safety controller <NUM>. This is because the timer <NUM> may be under the control of the safety controller <NUM>. It is to understood that the timer could be located remotely from the safety controller <NUM>. The timer may be configured to expire after a time period.

The time period may be defined as a measure of real time. For example, the time period may be <NUM>. Alternatively, the time period may be defined relative to a number of processor clocks (e.g. according to the clock rate of the GPU on which processing is being initialised). For example, the time period may be <NUM>,<NUM>,<NUM> clocks.

The time period may be set relative to the expected duration of the graphical processing being initialised. For example, the time period may be set such that it represents a fraction or percentage of the expected duration of the graphical processing being initialised. For example, the time period may be set as <NUM>% of the expected duration of the graphical processing being initialised. That is, the time period may be determined in dependence on the graphical processing being initialised.

In other examples, the timer period may be predetermined. For example, the time period may be set at design time. The time period may be set at design time for the graphics processing system, or for individual graphics processing units included in the graphics processing system. Alternatively, the time period may be user-configurable. A user may set a desired time period when setting up an application <NUM> for running on the host data processing system <NUM>. In another example, the desired time period may be determined by an application <NUM> running on the host data processing system <NUM>. An application may communicate said desired time period to the safety controller <NUM> (e.g. in the example shown in <FIG>, via API <NUM> in driver <NUM>).

In an example, the timer may be initialised when the instruction for initialising rendering of safety critical graphical data at the GPU is sent <NUM> from the safety controller <NUM> (e.g. to a buffer <NUM> in memory <NUM>). In another example, the timer may be initialised when the instruction is sent <NUM> from the host data processing system <NUM> (e.g. when the instruction departs from buffer <NUM>). The timer may be initialised at any other suitable time.

During the time period, the safety controller monitors <NUM> for a response from the graphics processing unit (e.g. GPU <NUM>). As described herein, the instruction for initialising rendering of safety critical graphical data comprises a request for a response from the GPU. Referring to <FIG>, the firmware <NUM> of GPU <NUM> may act on the request for response. For example, on receiving (e.g. via <NUM>) the instruction comprising a request for a response from the GPU <NUM>, the firmware <NUM> may read the request for a response, and then send <NUM> a response to the safety controller <NUM> (e.g. via memory <NUM>). Any suitable response may be sent. For example, the response may comprise an interrupt. Said interrupt may cause the host data processing system <NUM> to read a message in system memory.

According to the principles described herein, it is determined <NUM> that an initialisation error has occurred if no response is received from the GPU before the timer expires.

In response to determining that an initialisation error has occurred, the safety controller may cause the graphics processing unit to be reset. Referring to <FIG>, safety controller <NUM> may cause GPU <NUM> to be reset by commanding <NUM> reset unit <NUM>. As described herein, the reset performed may be a hardware recovery reset, a soft reset, a hard reset, or may involve resetting any combination of one or more units of the GPU <NUM>.

In some examples, no response is received from the GPU because it has stalled, locked-up, or faulted. For example, a fault may occur when an invalid memory access occurs and the memory management unit signals a page fault. Thus, performing the method described herein with reference to <FIG> enables GPU stalls or lock-ups to be efficiently identified and resolved (e.g. through a reset).

Rendering of graphical data by the graphics processing unit may be performed whilst a safety check as described with reference to <FIG> is being performed on that graphics processing unit. If a response is received before the time period expires the rendering of graphical data may proceed. For example, the rendering of graphical data that has already begun may continue unaffected or the rendering of graphical data may not begin until the safety check has been completed.

The methods described with reference to <FIG> and <FIG> are used in combination. This type of safety check caused by safety controller <NUM> is described with reference to <FIG>.

<FIG> is a flow diagram <NUM> for yet another method of initialising safety-critical rendering at a graphics processing unit within a graphics processing system in accordance with the principles described herein.

Configuration data for initialising rendering of safety critical graphical data at the graphics processing unit (e.g. GPU <NUM>) may be generated <NUM>. Configuration data may be generated in accordance with the principles described herein with reference to <FIG>.

The configuration data and an instruction comprising a request for response from the graphics processing unit (as described herein) may be written into <NUM> the graphics processing unit (e.g. GPU <NUM>). Configuration data may be written into the GPU in accordance with the principles described herein with reference to <FIG>. In an example, the configuration data may be comprised within the kick command comprising a request for response from the GPU. For example, the configuration data may form the body of the command, whilst the request for a response from the GPU is present as an instruction flag in the command header. In another example, the configuration data may be comprised in one or more different instructions.

A timer may be initialised <NUM>. The timer may be configured to expire after a time period. The timer may be initialised according to the principles described herein with reference to <FIG>. During the time period, the safety controller monitors for a response from the graphics processing unit (e.g. GPU <NUM>), in accordance with the principles described herein with reference to <FIG>.

The graphics processing unit (e.g. GPU <NUM>) may be configured <NUM> in accordance with the configuration data in the instruction according the principles described herein with reference to <FIG>. As described herein, the instruction comprises a request for response from the GPU. In an example, it is requested that a response from the GPU be sent once the GPU <NUM> has been configured in accordance with the configuration data. In another example, it is requested that a response from the GPU <NUM> be sent once the firmware <NUM> reads the request for response.

According to the principles described herein with reference to <FIG>, it is determined <NUM> whether the graphics processing unit (e.g. GPU <NUM>) has been correctly configured in accordance with the configuration data.

According to the principles described herein, it is determined <NUM> that an initialisation error has occurred if it is determined that the graphics processing unit has not been correctly configured in accordance with the configuration data. In addition, according to the principles described herein, it is determined <NUM> that an initialisation error has occurred if it is determined that no response is received from the GPU before the timer expires.

In response to determining that an initialisation error has occurred, the safety controller may cause the graphics processing unit to be reset as described with reference to <FIG> and <FIG>. In other examples, the safety controller <NUM> may inform other entities external to the GPU <NUM> that an initialisation error has occurred. For example, the safety controller may communicate the detected initialisation error to an application <NUM> running on the host data processing system <NUM>, such as the application that submitted the rendering call with which the initialisation error is associated.

Rendering of graphical data by the graphics processing unit may be performed whilst a safety check as described with reference to <FIG> is being performed on that graphics processing unit. If it is determined that the graphics processing unit has been configured in accordance with the configuration data and a response is received before the time period expires the rendering of graphical data may proceed. For example, the rendering of graphical data that has already begun may continue unaffected or the rendering of graphical data may not begin, or be suspended, until the safety check has been completed.

In examples, a second timer may be initialised. The second timer may be configured to expire after a second time period. The second time period may be shorter than the time period previously described herein (referred to in the following paragraphs as the first time period, associated with the first timer).

Each time period may be defined as a measure of real time. For example, the first time period may be <NUM> and the second time period may be <NUM>. Alternatively, each time period may be defined relative to a number of processor clocks (e.g. according to the clock rate of the GPU on which processing is being initialised). For example, the first time period may be <NUM>,<NUM>,<NUM> clocks and the second time period may be <NUM>,<NUM> clocks.

Each time period may be set relative to the expected duration of the graphical processing being initialised. For example, each time period may be set such that it represents a fraction or percentage of the expected duration of the graphical processing being initialised. For example, the first time period may be set as <NUM>% of the expected duration of the graphical processing being initialised, and the second time period may be set as <NUM>% of the expected duration of the graphical processing being initialised. That is, each time period may be determined in dependence on the graphical processing being initialised.

In other examples, each timer period may be predetermined. For example, each time period may be set at design time. Each time period may be set at design time for the graphics processing system, or for individual graphics processing units included in the graphics processing system. Alternatively, each time period may be user-configurable. A user may set desired time periods when setting up an application <NUM> for running on the host data processing system <NUM>. In another example, desired time periods may be determined by an application <NUM> running on the host data processing system <NUM>. An application may communicate said desired time period to the safety controller (e.g. in the example shown in <FIG>, via API <NUM> in driver <NUM>).

The first timer and the second timer may be initialised at the same time.

During the first and second time periods, the safety controller may monitor for a response from the graphics processing unit (e.g. GPU <NUM>). For example, the GPU <NUM> may be instructed to respond once it has been determined whether the GPU has been configured in accordance with the configuration data, as described with reference to <FIG>.

In an example, if no response is received before the second time period expires, but a response is received before the first time period expires and it is determined that the GPU has been correctly configured in accordance with the configuration data, it may be determined that the GPU <NUM> is functioning correctly (e.g. the GPU has not locked up, stalled or faulted), but that its workload has exceeded an acceptable threshold. In this example, the safety controller may manage the workload of the GPU <NUM>. For example, the safety manager may cause the rate at which graphical processing instructions are sent to the GPU to be reduced. The degree to which the GPU's workload is decreased may depend on the duration of time surpassed before a response was received.

The response of the safety controller with regards to the monitoring performed during the first time period is described herein with reference to <FIG>.

Initialising rendering in accordance with the principles described herein with reference to <FIG>, <FIG> or <FIG> is advantageous over performing resets only in response to detecting a fault in a GPU's render output (such as a frame or tile rendered by a graphics processing unit). This is because the latter approach often involves waiting for frame to complete rendering before an error can be detected. In some examples, an incorrectly configured GPU may not even be able to complete rendering of a frame or tile. The safety checks performed in accordance with the principles described herein with reference to <FIG>, <FIG> or6 can be performed in a fraction of the time that it typically takes for a frame to be rendered. For this reason, a fault can be detected, and optionally cleared by resetting the GPU, before that fault manifests itself in an incorrectly rendered frame or tile (and before the GPU commits time and resources to incorrectly rendering that frame or tile). Thus, the detection and elimination of faults can be performed more efficiently.

For example, detecting a transient fault may require a dual-lockstep type arrangement to be implemented - as described with reference to <FIG>. In such an arrangement, a pair of identical processing cores <NUM> and <NUM> are configured to process a stream of instructions <NUM> in parallel. The outputs of the processing cores <NUM> and <NUM> can be compared. When the outputs of the processing cores <NUM> and <NUM> do not match, a fault can be raised to the safety-critical system. This approach to detecting faults requires the rendering of a frame or tile to be completed, so that the outputs of each of the processing cores <NUM> and <NUM> can be compared. In addition, a second processing core is required to implement a dual lockstep processor, making them expensive in that they necessarily consume double the chip area compared to conventional processors and consume approximately twice the power. That said, it is to be understood that the method of initialising safety-critical rendering at a graphics processing unit in accordance with the principles described herein may be used in combination with such approaches. This may be appropriate for graphics processing systems with highly-stringent safety requirements. For example, rendering may be initialised in accordance with the principles described herein for one or both of processing cores <NUM> and <NUM> in a dual lockstep arrangement.

Initialising rendering in accordance with the principle described herein also improves the robustness of a graphics processing system by verifying the data path from the host data processing system to a GPU's register bank via its firmware.

Safety controller <NUM> may selectively perform safety checks for only the GPUs performing safety critical rendering. For example, the instrument cluster <NUM> shown in <FIG> comprises a speedometer <NUM> in the form of a traditional dial having speed values <NUM> around the edge of the dial and a needle <NUM> whose angular orientation indicates the current speed of the vehicle. The instrument cluster <NUM> further comprises an oil temperature gauge <NUM>, an information icon <NUM> (e.g. indicating the selected radio station), a non-critical warning icon <NUM> (e.g. indicating a fault with the air conditioning system), and a critical warning icon <NUM> (e.g. indicating a serious engine problem). In this example, only the speedometer <NUM> and the critical warning icon <NUM> of the display elements are deemed to be critical to the safety of the vehicle and its occupants. It may be necessary to render those display elements in a manner which satisfies a mandated safety level, such as ASIL B of the ISO <NUM> standard. The oil temperature gauge <NUM>, information icon <NUM> and non-critical warning icon <NUM> do not need to be rendered to that safety level. The rendering space used to render the frame representing the rendered instrument cluster is divided into a plurality of tiles <NUM> each comprising a plurality of pixels. Only the highlighted tiles <NUM> include the critical display elements in that at least part of a critical display element overlaps with each of the highlighted tiles. The safety controller <NUM> may perform safety checks for only the processing unit(s) <NUM> or GPU(s) that are configured to perform the rendering of the highlighted tiles. , and/or only for instructions associated with the rendering of the highlighted tiles.

The graphics processing system of <FIG> is shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by graphics processing system need not be physically generated by the graphics processing system at any point and may merely represent logical values which conveniently describe the processing performed by a graphics processing system between its input and output.

A graphics processing system described herein may be embodied in hardware on one or more integrated circuits. The graphics processing system described herein may be configured to perform any of the methods described herein.

Examples of a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.

A processor may be any kind of general purpose or dedicated processor, such as a CPU, GPU, vector processor, tensor processor, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), or the like.

It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed in an integrated circuit manufacturing system configures the system to manufacture a graphics processing system configured to perform any of the methods described herein, or to manufacture a graphics processing system comprising any apparatus described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.

There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a graphics processing system as described herein. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a graphics processing system to be performed.

An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation.

An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a graphics processing system will now be described with respect to <FIG>.

<FIG> shows an example of an integrated circuit (IC) manufacturing system <NUM> which is configured to manufacture a graphics processing system as described in any of the examples herein. In particular, the IC manufacturing system <NUM> comprises a layout processing system <NUM> and an integrated circuit generation system <NUM>. The IC manufacturing system <NUM> is configured to receive an IC definition dataset (e.g. defining a graphics processing system as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a graphics processing system as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system <NUM> to manufacture an integrated circuit embodying a graphics processing system as described in any of the examples herein.

In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture a graphics processing system without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA).

Claim 1:
A method of initialising rendering at a graphics processing unit (<NUM>) configured to perform safety-critical rendering, the method comprising:
generating (<NUM>) configuration data for initialising rendering of safety critical graphical data at the graphics processing unit (<NUM>), said configuration data specifying a configuration to be adopted by the graphics processing unit (<NUM>);
causing (<NUM>) an instruction comprising the configuration data for initialising rendering and a request for a response from the graphics processing unit (<NUM>) to be provided to the graphics processing unit (<NUM>);
initialising (<NUM>) a timer (<NUM>), said timer (<NUM>) being configured to expire after a time period;
monitoring (<NUM>), during the time period, for the response from the graphics processing unit (<NUM>);
configuring (<NUM>) the graphics processing unit (<NUM>) in accordance with the configuration data for initialising rendering;
determining (<NUM>) whether the graphics processing unit (<NUM>) is correctly configured in accordance with the configuration data; and
determining (<NUM>), by a safety controller (<NUM>) external to the graphics processing unit (<NUM>), that an initialisation error has occurred if:
(i) it is determined that the graphics processing unit (<NUM>) is not correctly configured in accordance with the configuration data; or
(ii) no response is received from the graphics processing unit (<NUM>) before the timer expires.