Patent Description:
The <CIT> discloses an input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and a low or moderate speed output. One of the input and output circuits is selected and the other is deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to inter-face to lower speed circuitry inside the core of an integrated circuit.

The <CIT> discloses an apparatus comprising a first contact location; a second contact point; a first single-ended driver coupled to the first pad; a second single-ended driver coupled to the second pad; a differential driver coupled to the first and second pads; and a logic unit to activate the first and second single-ended drivers or to activate the differential driver.

The <CIT> discloses both a SDR and a DDR using different clocks so that an input signal can be selected without changing a separate metal option. For this end, it compares the first clock when the DDR selection signal is activated and the second clock having a phase opposite to that of the first clock, and outputs a DDR clock according to the result. A SDR receiver that compares the voltage level of one clock and the reference voltage and outputs the SDR clock according to the result, and drives only one of the DDR receiver and the SDR receiver according to the DDR selection signal and the SDR selection signal to drive the SDR or DDR clock.

The present disclosure describes methods, devices, systems, and techniques for managing data transfers in semiconductor devices, e.g., by separating logic circuits for lower-speed-type data (e.g., SDR data) and higher-speed-type data (e.g., DDR data) to increase data transfer speed for the higher-speed-type data.

The problem of the present invention is solved by an integrated circuit according to the independent claim <NUM> or by an integrated circuit according to the independent claim <NUM>. The dependent claims refer to further advantageous developments of the present invention.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below.

It is also to be understood that the various exemplary implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

Implementations of the present disclosure provide techniques for managing data transfers in semiconductor devices, e.g., for high speed data transfers such as DDR data transfers in the semiconductor devices such as memory devices.

For example, a memory device can include a memory cell array, a data cache circuit coupled to the memory cell array and configured to cache data from the memory cell array, and a data output buffer coupled to the data cache circuit and configured to transfer cached data from the data cache circuit, e.g., to an external controller or host device through a memory interface. The cached data can be transferred from the data cache circuit in different speed types. For example, at a same clock frequency, the cached data can be transferred out from the data cache circuit with a single data rate (SDR) as SDR data, with a double data rate (DDR) as DDR data, or with a quad data rate (QDR) as QDR data. The data output buffer can be configured to transfer SDR data, DDR data, or QDR data along a data path out at a data output port to the memory interface. In some embodiments, SDR is used as a lower speed type, and DDR or QDR is used as a higher speed type. In some embodiments, DDR is used as a lower speed type, and QDR is used as a higher speed type. For illustration purposes, in the present disclosure, SDR is used as an example of a lower speed type, and DDR is used as an example of a higher speed type.

The data output buffer can be configured to support transferring DDR data at a higher speed (or higher frequency) and transferring SDR data at a lower speed (or lower frequency). Besides supporting the data transfer modes (e.g., SDR mode, DDR mode), the data output buffer can be also configured to implement one or more other modes (or functions), including on die termination (ODT) mode and Output Disable mode (or off chip drive (OCD) mode). For example, the ODT mode can be enabled, for example, during transferring data through a data input buffer (e.g., the data input buffer <NUM> as illustrated in <FIG>) into the memory cell array, which may reduce current reflections or other noises. The Output Disable mode can be enabled, for example, during transferring data through the data input buffer into the memory cell array, which can be used to isolate the input data transfer from the data output buffer.

In some embodiments, a data path (e.g., a higher speed data path) is shared to transfer both SDR data and DDR data. A multiplexer is coupled to a DDR interface and an SDR interface and configured to select either DDR data or SDR data at a time to transfer along the shared data path through the data output buffer. Implementing all of DDR mode, SDR mode, ODT mode, and Output Disable mode on the shared data path requires a number of logic control circuits or gates (e.g., a multiplexer, NAND gates, and NOR gates), which can affect the loading of the data path and a transfer speed (or frequency) along the data path.

In some embodiments, e.g., as described with further details in <FIG> and <FIG>, in a data output buffer, the techniques can separate SDR logic and DDR logic into separate data paths for corresponding data transfers (e.g., a lower speed data path for SDR data and a higher speed data path for DDR data) and one or more operation modes (e.g., DDR mode, SDR mode, ODT mode, and/or Output Disable mode), which can reduce logic complexity on the critical path (e.g., the higher speed data path for DDR data) and reduce capacitor loading on the critical path to thereby increase the maximum speed (or frequency) of the higher speed data path.

The techniques implemented in the present disclosure can be applied to any suitable semiconductor devices, e.g., integrated circuit (IC) devices that transfer data with a high speed, or the IC devices (that output/transmit data in DDR or SDR) such as flash memories and dynamic random-access memories (DRAMs), and logic devices such as microcontrollers. For example, the techniques can be applied to various types of volatile memory or non-volatile memory, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) such as phase-change random-access memory (PCRAM), spin-transfer torque (STT)-Magnetoresistive random-access memory (MRAM), synchronous dynamic random-access memory (SDRAM) such as DDR SDRAM, among others. The techniques can also be applied to charge-trapping based memory, e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory, and floating-gate based memory. The techniques can be applied to two-dimensional (2D) memory or three-dimensional (3D) memory. The techniques can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices like <NUM>-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSDs), embedded systems, among others.

<FIG> illustrates an example of a system <NUM>. The system <NUM> includes a device <NUM> and a host device <NUM>. The device <NUM> includes a device controller <NUM> and a memory <NUM>. The device controller <NUM> includes a processor <NUM> and an internal memory <NUM>. In some implementations, the device <NUM> includes a plurality of memories <NUM> that are coupled to the device controller <NUM>.

The host device <NUM> includes a host controller <NUM> that can include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform one or more corresponding operations.

In some implementations, the device <NUM> is a storage device. For example, the device <NUM> can be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage. In some implementations, the device <NUM> is a smart watch, a digital camera or a media player. In some implementations, the device <NUM> is a client device that is coupled to a host device <NUM>. For example, the device <NUM> is an SD card in a digital camera or a media player that is the host device <NUM>.

The device controller <NUM> is a general-purpose microprocessor, or an application-specific microcontroller. In some implementations, the device controller <NUM> is a memory controller for the device <NUM>. The following sections describe the various techniques based on implementations in which the device controller <NUM> is a memory controller. However, the techniques described in the following sections are also applicable in implementations in which the device controller <NUM> is another type of controller that is different from a memory controller.

The processor <NUM> is configured to execute instructions and process data. The instructions include firmware instructions and/or other program instructions that are stored as firmware code and/or other program code, respectively, in the secondary memory. The data includes program data corresponding to the firmware and/or other programs executed by the processor, among other suitable data. In some implementations, the processor <NUM> is a general-purpose microprocessor, or an application-specific microcontroller. The processor <NUM> is also referred to as a central processing unit (CPU).

The processor <NUM> accesses instructions and data from the internal memory <NUM>. In some implementations, the internal memory <NUM> is a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM). For example, in some implementations, when the device <NUM> is an eMMC, an SD card or a smart watch, the internal memory <NUM> is an SRAM. In some implementations, when the device <NUM> is a digital camera or a media player, the internal memory <NUM> is DRAM.

In some implementations, the internal memory is a cache memory that is included in the device controller <NUM>, as shown in <FIG>. The internal memory <NUM> stores instruction codes, which correspond to the instructions executed by the processor <NUM>, and/or the data that are requested by the processor <NUM> during runtime.

The device controller <NUM> transfers the instruction code and/or the data from the memory <NUM> to the internal memory <NUM>. The memory <NUM> can be a semiconductor device. In some implementations, the memory <NUM> is a non-volatile memory that is configured for long-term storage of instructions and/or data, e.g., a NAND flash memory, or some other suitable non-volatile memory. In implementations where the memory <NUM> is NAND flash memory, the device <NUM> is a flash memory, e.g., a flash memory card, and the device controller <NUM> is a NAND flash controller. For example, in some implementations, when the device <NUM> is an eMMC or an SD card, the memory <NUM> is a NAND flash; in some implementations, when the device <NUM> is a digital camera, the memory <NUM> is an SD card; and in some implementations, when the device <NUM> is a media player, the memory <NUM> is a hard disk.

In some implementations, the device controller <NUM> is configured to receive data and instructions from and to send data to the host device <NUM>. The device controller <NUM> is further configured to send data and commands to the memory <NUM> and to receive data from the memory <NUM>. For example, the device controller <NUM> is configured to send data and a write command to instruct the memory <NUM> to store the data to a specified address. As another example, the device controller <NUM> is configured to receive a read request (or a read command) from the host device <NUM> and send a corresponding read command to the memory <NUM> to read data from a specified address in the memory <NUM>.

The memory <NUM> includes a plurality of blocks. The memory <NUM> can be a two-dimensional (2D) memory including 2D memory blocks. The memory <NUM> can also be a three-dimensional (3D) memory including 3D memory blocks. Each block can include a same number of pages. Each page has a unique number in the block. Data is stored in the pages of the block according to the order of the unique numbers of the pages in the block. Each page can be read or written separately, and pages in a block can be erased together.

<FIG> illustrates an example configuration of a memory device <NUM>. The memory device <NUM> can be implemented as the memory <NUM> of <FIG>. The memory device <NUM> includes a memory cell array <NUM>. The memory cell array <NUM> can include a number of memory cells coupled in series to a number of row word lines and a number of column bit lines.

A memory cell can include a memory transistor configured as a storage element. The memory transistor can include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal-oxide-silicon (MOS) device that can store charges.

The memory device <NUM> includes a memory interface <NUM> having multiple input/output (I/O) ports for receiving data, e.g., from a controller such as the device controller <NUM> of <FIG> or the host controller <NUM> of <FIG>, or outputting data from the memory cell array <NUM>. The memory device <NUM> includes a data buffer <NUM> configured to buffer data through the memory interface <NUM>. The data buffer <NUM> can include a data input buffer <NUM> configured to buffer/transmit data from a controller (e.g., the device controller <NUM> of <FIG> or the host controller <NUM> of <FIG>) through the memory interface <NUM> to the memory cell array <NUM>. The data buffer <NUM> can also include a data output buffer <NUM> configured to buffer/transmit out data from the memory cell array <NUM> through the memory interface <NUM>, e.g., to a host device such as the host device <NUM> of <FIG>.

In some embodiments, the memory device <NUM> further includes an X-decoder (or row decoder) <NUM> and an optional Y-decoder (not shown). Each memory cell is coupled to the X-decoder <NUM> via a respective word line and coupled to the Y-decoder via a respective bit line <NUM>. Accordingly, each memory cell can be selected by the X-decoder <NUM> and the Y-decoder for read or write operations through the respective word line and the respective bit line <NUM>.

The memory device <NUM> includes a page buffer circuit <NUM> that includes a number of page buffers. Each page buffer is connected to the memory cell array <NUM> through a respective bit line <NUM>. In some embodiments, a page buffer is connected to the Y-decoder through a data line associated with a corresponding bit line <NUM> that connects a corresponding line of memory cells in the memory cell array <NUM>. A page buffer is configured to control a voltage on a corresponding bit line to perform an operation, e.g., read, program, or erase, on a memory cell coupled to the corresponding bit line. A page buffer can include at least one latch circuit.

In some embodiments, the memory device <NUM> further includes a data cache circuit <NUM> coupled between the page buffer circuit <NUM> and the data buffer <NUM>. During a program or erase operation, the data cache circuit <NUM> is configured to store data from the data buffer <NUM> (e.g., from the data input buffer <NUM>) and/or output through the page buffer circuit <NUM> to the memory cell array <NUM>. During a read operation, the data cache circuit <NUM> is configured to store data from the memory cell array through the page buffer circuit <NUM> and/or output data to the data buffer <NUM> (e.g., to the data output buffer <NUM>).

In some embodiments, the memory device <NUM> further includes a control logic <NUM> coupled to components in the memory device <NUM> including the X-decoder <NUM> and the Y-decoder, the data buffer <NUM>, the page buffer circuit <NUM>, and the data cache circuit <NUM>. The control logic <NUM> is configured to receive a command, address information, and/or data, e.g., from a memory controller such as the device controller <NUM> or the host controller <NUM> of <FIG>, via the memory interface <NUM>. The control logic <NUM> can also process the command, the address information, and/or the data, for example, to generate physical address information, e.g., of blocks/pages, in the memory cell array <NUM>. The control logic <NUM> can include circuitry, e.g., an integrated circuit integrating multiple logics, circuits, and/or components.

In some implementations, the control logic <NUM> includes a data register, an SRAM buffer, an address generator, a mode logic, and a state machine. The mode logic can be configured to determine whether there is a read or write operation and provide a result of the determination to the state machine.

During a write operation, the data register in the control logic <NUM> can register input data from the memory interface <NUM>, and the address generator in the control logic <NUM> can generate corresponding physical addresses to store the input data in specified memory cells of the memory cell array <NUM>. The address generator can be connected the X-decoder <NUM> and the Y-decoder that are controlled to select the specified memory cells through corresponding word lines and bit lines. The SRAM buffer can retain the input data from the data register in its memory as long as power is being supplied. The state machine can process a write signal from the SRAM buffer and provide a control signal to a voltage generator that can provide a write voltage to the X-decoder <NUM> and/or the Y-decoder. The Y-decoder is configured to output the write voltage to the bit lines (BLs) for storing the input data in the specified memory cells.

During a read operation, the state machine can provide control signals to the voltage generator and the page buffer circuit <NUM>. The voltage generator can provide a read voltage to the X-decoder <NUM> and the Y-decoder for selecting a memory cell. A page buffer can sense a small power signal (e.g., a current signal) that represents a data bit ("<NUM>" or "<NUM>") stored in the selected memory cell through a bit line <NUM> coupled to the page buffer and the selected memory cell. A sense amplifier can amplify the small power signal swing to recognizable logic levels so the data bit can be interpreted properly by logic inside or outside the memory device <NUM>. In some implementations, the page buffer circuit <NUM> and/or the data cache circuit <NUM> are included in the sense amplifier. The data buffer <NUM> (e.g., the data output buffer <NUM>) can receive the amplified voltage from the sensor amplifier and output the amplified power signal to the logic outside the memory device <NUM> through the memory interface <NUM>.

<FIG> illustrate an example data output buffer <NUM> for SDR and DDR data transfers in a semiconductor device, according to one or more implementations of the present disclosure. The semiconductor device can be the memory <NUM> of <FIG> or the memory device <NUM> of <FIG>. The data output buffer <NUM> can be implemented as the data output buffer <NUM> of <FIG>. The data output buffer <NUM> can be coupled between a data storage circuit such as a data cache circuit (e.g., the data cache circuit <NUM> of <FIG>) in the semiconductor device and a device interface (e.g., the memory interface <NUM> of <FIG>) of the semiconductor device. The data output buffer <NUM> can be configured to transfer data stored or cached in the data storage circuit through the device interface to a controller (e.g., the device controller <NUM> or the host controller <NUM> of <FIG>). <FIG> illustrate the data output buffer <NUM> in DDR data transfer mode, SDR data transfer mode, ODT mode, and Output Disable mode, respectively.

<FIG> is a schematic diagram of the example data output buffer <NUM> for SDR and DDR data transfers, according to independent claim <NUM>. <FIG> is an example circuit diagram of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. The data output buffer <NUM> separates a higher speed data path <NUM> (as illustrated as thick lines in <FIG>) for DDR data transfer and a lower speed data path <NUM> for SDR data transfer, and simplifies logic circuits on the higher speed data path <NUM> to increase a transfer speed (or frequency) of the DDR data transfer. Also, with the separated data paths <NUM>, <NUM>, the data output buffer <NUM> does not need to include a multiplexer to separate SDR data and DDR data from input interfaces, which can further simplify the logic circuits on the higher speed data path <NUM> to further increase the transfer speed of the DDR data transfer.

In some embodiments, the data output buffer <NUM> includes a first interface (e.g., DDR interface) for receiving DDR data (or DDR_DATA) <NUM> and a second interface (e.g., SDR interface) for receiving SDR data (or SDR_DATA) <NUM>. Each of the first interface and the second interface can be respectively coupled to the data storage circuit. In some embodiments, the semiconductor device is configured to receive a command from the controller. The command can include information for selecting one of DDR mode (or DDR interface) and the SDR mode (or SDR interface) for data transfer following the command. For example, each of the DDR mode and the SDR mode has a respective value, and the command can include a value set for one of the DDR mode and SDR mode. If the DDR mode or DDR interface is indicated in the command, the semiconductor device can be configured to transfer storage data (or cached data) in the data storage circuit out as DDR data to the first interface of the data output buffer <NUM>, e.g., by transferring data at both a falling edge and a rising edge of a clock signal at a clock frequency. If the SDR mode or SDR interface is indicated in the command, the semiconductor device can be configured to transfer storage data (or cached data) in the data storage circuit out as SDR data to the second interface of the data output buffer <NUM>, e.g., by transferring data at a falling edge or a rising edge of the clock signal at the clock frequency.

The data output buffer <NUM> includes a first logic circuit <NUM> coupled to the first interface to receive the DDR data <NUM> and a second logic circuit <NUM> coupled to the second interface to receive the SDR data <NUM>. The data output buffer <NUM> also includes a driving circuit <NUM> separately coupled to the first logic circuit <NUM> and the second logic circuit <NUM>. The driving circuit <NUM> includes a data output (data output node or data queue - DQ) <NUM> for outputting data corresponding to the DDR data <NUM> or data corresponding to the SDR data <NUM>, e.g., to the device interface. The first interface, the first logic circuit <NUM>, and the driving circuit <NUM> can be arranged in series to form the higher speed data path <NUM> to transfer the DDR data <NUM> with a first speed. The second interface, the second logic circuit <NUM>, and the driving circuit <NUM> can be arranged in series to form the lower speed data path <NUM> to transfer the SDR data <NUM> with a second speed. The first speed can be higher than the second speed, e.g., more than <NUM> %, twice, <NUM> times, <NUM> times, or more. In a particular example, the second speed is about <NUM>, while the first speed is about <NUM>,<NUM>. As discussed with further details below, the first logic circuit <NUM> and the second logic circuit <NUM> can be configured to cause data to be transferred through the first logic circuit <NUM> with a higher speed than through the second logic circuit <NUM>, e.g., by including a smaller number of logic gates or transistors in the first logic circuit <NUM> than in the second logic circuit <NUM>.

In some embodiments, e.g., as illustrated in <FIG>, the driving circuit <NUM> includes one or more first driving subcircuits <NUM>-<NUM> each having at least one first-type transistor and one or more second driving subcircuits <NUM>-<NUM> each having at least one second-type transistor. The first-type transistor can be a p-type transistor such as p-channel metal-oxide-semiconductor (PMOS) transistor, and the second-type transistor can be an n-type transistor such as n-channel metal-oxide-semiconductor (NMOS) transistor. The one or more first driving subcircuits <NUM>-<NUM> can be coupled between a supply voltage (e.g., VDD) and the data output <NUM>, and the one or more second driving subcircuits <NUM>-<NUM> are coupled between the data output <NUM> and an electrical ground (e.g., VSS or <NUM> V).

The first logic circuit <NUM> for the DDR data <NUM> can include a first logic subcircuit <NUM>-<NUM> (e.g., P_PreDRV shown in <FIG>) coupled to the one or more first driving subcircuits <NUM>-<NUM> and a second logic subcircuit <NUM>-<NUM> (e.g., N_PreDRV shown in <FIG>) coupled to the one or more second driving subcircuits <NUM>-<NUM>. The second logic circuit <NUM> for the SDR data <NUM> can include a third logic subcircuit <NUM>-<NUM> (e.g., PS_PreDRV shown in <FIG>) coupled to the one or more first driving subcircuits <NUM>-<NUM> and a fourth logic subcircuit <NUM>-<NUM> (e.g., NS_PreDRV shown in <FIG>) coupled to the one or more second driving subcircuits <NUM>-<NUM>.

In some embodiments, each first driving subcircuit <NUM>-<NUM> includes two p-type transistors 312a, 312b coupled in series between the supply voltage and the data output <NUM>, and each second driving subcircuit <NUM>-<NUM> includes two n-type transistors 314a, 314b coupled in series between the data output <NUM> and the electrical ground. As shown in <FIG>, each of the first logic subcircuit <NUM>-<NUM> and the third logic subcircuit <NUM>-<NUM> is coupled to a respective p-type transistor 312b, 312a in each of the one or more first driving subcircuit <NUM>-<NUM>; each of the second logic subcircuit <NUM>-<NUM> and the fourth logic subcircuit <NUM>-<NUM> is coupled to a respective n-type transistor 314a, 314b in each of the one or more second driving subcircuit <NUM>-<NUM>.

In some embodiments, the second logic circuit <NUM> is configured such that, if the first interface (e.g., DDR interface) is selected to receive the DDR data <NUM>, the respective p-type transistor 312a coupled to the third logic subcircuit <NUM>-<NUM> and the respective n-type transistor 314b coupled to the fourth logic subcircuit <NUM>-<NUM> are turned on, and the driving circuit <NUM> outputs the data corresponding to the DDR data at the data output <NUM>. In some embodiments, the first logic circuit <NUM> is configured such that, if the second interface (e.g., SDR interface) is selected to receive the SDR data <NUM>, the respective p-type transistor 312b coupled to the first logic subcircuit <NUM>-<NUM> and the respective n-type transistor 314a coupled to the second logic subcircuit <NUM>-<NUM> are turned on, and the driving circuit <NUM> outputs the data corresponding to the SDR data at the data output <NUM>.

In some embodiments, the first logic subcircuit <NUM>-<NUM> includes a first inverter <NUM>, a first NAND gate <NUM>, and a second inverter <NUM> that are coupled in series between the first interface and the one or more first driving subcircuits <NUM>-<NUM>. The first inverter <NUM> is configured to receive the DDR data <NUM> from the first interface and output inverted DDR data (e.g., DOPB shown in <FIG>) to a first input of the first NAND gate <NUM>. The first NAND gate <NUM> includes the first input for receiving the inverted DDR data DOPB, a second input for receiving a first control signal <NUM>, and an output for outputting data DOP. The second inverter <NUM> includes an input coupled to the output of the first NAND gate <NUM> and an output for outputting data PU to the respective p-type transistor 312b in each of the one or more first driving subcircuits <NUM>-<NUM>.

In some embodiments, the second logic subcircuit <NUM>-<NUM> includes a third inverter <NUM>, a first NOR gate <NUM>, and a fourth inverter <NUM> that are coupled in series between the first interface and the one or more second driving subcircuits <NUM>-<NUM>. The third inverter <NUM> is configured to receive the DDR data <NUM> from the first interface and output the inverted higher-speed-type data (e.g., DONB shown in <FIG>) to a first input of the first NOR gate <NUM>. The first NOR gate <NUM> includes the first input for receiving the inverted higher-speed-type data DONB, a second input for receiving a second control signal <NUM>, and an output for outputting data DON. The fourth inverter <NUM> includes an input coupled to the output of the first NOR gate <NUM> for receiving data DON and an output for outputting data PD to the respective n-type transistor 314a in each of the one or more second driving subcircuits <NUM>-<NUM>.

In some embodiments, the first logic circuit <NUM> includes an additional NOR gate <NUM> having a first input for receiving an ODT enable (ODTEN) signal, a second input for receiving an inverted DDR enable (DDREN#) signal, and an output for outputting the first control signal <NUM> to the second input of the first NAND gate <NUM>. The inverted DDR enable signal (DDREN#) can be obtained by using an inverter to invert a DDR enable (DDREN) signal. The first logic circuit <NUM> can further include an additional inverter <NUM> coupled to the output of the additional NOR gate <NUM> and configured to receive the first control signal <NUM> and output the second control signal <NUM> to the second input of the first NOR gate <NUM>. Thus, the second control signal <NUM> can be an inversion of the first control signal <NUM>. In some embodiments, at least one of the additional NOR gate <NUM> or the additional inverter <NUM> can be arranged in the data output buffer <NUM> and out of the first logic circuit <NUM>.

As discussed with further details in <FIG>, the data output buffer <NUM> (or the first control signal <NUM> and the second control signal <NUM>) are configured to perform at least one of: i) allowing to output the DDR data if the first interface is selected to receive the DDR data <NUM> (e.g., as illustrated in <FIG>), ii) keeping a respective p-type transistor 312b coupled to the first logic subcircuit <NUM>-<NUM> on and a respective n-type transistor 314a coupled to the second logic subcircuit <NUM>-<NUM> on if the second interface is selected to receive the SDR data <NUM> (e.g., as illustrated in <FIG>) or in response to receiving an on die termination (ODT) enable signal for enabling an ODT mode (e.g., as illustrated in <FIG>), or iii) keeping the respective p-type transistor 312a coupled to the third logic subcircuit <NUM>-<NUM> off and the respective n-type transistor 314b coupled to the fourth logic subcircuit <NUM>-<NUM> off in response to receiving an output disable signal for disabling the data output <NUM> of the driving circuit <NUM> (e.g., as illustrated in <FIG>).

As noted above, the second logic circuit <NUM> for SDR data <NUM> includes the third logic subcircuit <NUM>-<NUM> coupled between the second interface and the one or more first driving subcircuits <NUM>-<NUM> and the fourth logic subcircuit <NUM>-<NUM> coupled between the second interface and the one or more second driving subcircuits <NUM>-<NUM>. As described with further details below, the second logic circuit <NUM> can include more complicated logic gates or components than the first logic circuit <NUM>, such that the data output buffer <NUM> can implement all of DDR mode, SDR mode, ODT mode, and Output Disable mode (or OCD mode). In such a way, DDR data <NUM> can be transferred with a higher speed along the higher speed data path <NUM> through the data output buffer <NUM>, e.g., than sharing a same data path with SDR data <NUM>.

In some embodiments, e.g., as illustrated in <FIG>, the third logic subcircuit <NUM>-<NUM> includes an OR gate <NUM> and a second NAND gate <NUM> that are coupled between the second interface and the one or more first driving subcircuits <NUM>-<NUM>. The OR gate <NUM> has a first input for receiving the SDR data <NUM> from the second interface, a second input for receiving an ODT enable (ODTEN) signal, a third input for receiving a DDR enable (DDREN) signal, and an output. The second NAND gate <NUM> has a first input coupled to the output for the OR gate <NUM>, a second input for receiving an output enable (OE) signal, a third input for receiving a first selection signal (e.g., OCDPEN[M:<NUM>] as shown in <FIG>), and an output coupled to a respective p-type transistor 312a coupled to the third logic subcircuit <NUM>-<NUM> in each of the one or more first driving subcircuits <NUM>-<NUM>.

In some embodiments, e.g., as illustrated in <FIG>, the fourth logic subcircuit <NUM>-<NUM> includes: an AND gate <NUM> and a second NOR gate <NUM> that are coupled in series between the second interface and the one or more second driving subcircuits <NUM>-<NUM>. The AND gate <NUM> has a first input for receiving the SDR data <NUM> from the second interface, a second input for receiving an inversion of the ODT enable (ODTEN#) signal, a third input for receiving an inversion of the DDR enable (e.g., DDREN#) signal, and an output. The second NOR gate <NUM> has a first input coupled to the output of the AND gate <NUM>, a second input for receiving an inversion of the OE (OE#) signal, a third input for receiving a second selection signal (e.g., OCDNENB[M:<NUM>] as shown in <FIG>), and an output coupled to a respective n-type transistor 314b coupled to the fourth logic subcircuit <NUM>-<NUM> in each of the one or more second driving subcircuits <NUM>-<NUM>. The ODTEN# signal can be obtained by using an inverter to invert the ODT enable (ODTEN) signal. The OE# signal can be obtained by using an inverter to invert the OE signal. The second selection signal can be an inversion of the first selection signal or be controlled independently from the first selection signal.

As discussed with further details in <FIG>, the data output buffer <NUM> is configured to perform at least one of: i) allowing to output the SDR data if the second interface is selected to receive the SDR data <NUM> (e.g., as illustrated in <FIG>), ii) keeping a respective p-type transistor 312a coupled to the third logic subcircuit <NUM>-<NUM> on and a respective n-type transistor 314b coupled to the fourth logic subcircuit <NUM>-<NUM> on if the first interface is selected to receive the DDR data <NUM> (e.g., as illustrated in <FIG>) or in response to receiving the ODT enable signal (ODTEN) for enabling the ODT mode (e.g., as illustrated in <FIG>) and the output enable (OE) signal with a higher voltage level, or iii) keeping the respective p-type transistor 312a coupled to the third logic subcircuit <NUM>-<NUM> off and the respective n-type transistor 314b coupled to the fourth logic subcircuit <NUM>-<NUM> off in response to receiving the output disable signal for disabling the data output <NUM> of the driving circuit <NUM> (e.g., as illustrated in <FIG>). The output disable signal can be the output enable signal with a lower voltage level.

In some embodiments, e.g., as illustrated in <FIG>, the driving circuit <NUM> includes a plurality of first driving subcircuits <NUM>-<NUM> coupled in parallel with the supply voltage and the data output <NUM> and a plurality of second driving subcircuits <NUM>-<NUM> coupled in parallel with the data output <NUM> and the electrical ground. The plurality of second driving subcircuits <NUM>-<NUM> can correspond to the plurality of first driving subcircuits <NUM>-<NUM>. In some examples, e.g., as shown in <FIG>, the number of the second driving subcircuits <NUM>-<NUM> (e.g., M) is identical to the number of the first driving subcircuits <NUM>-<NUM> (e.g., M), where M can be an integer larger than <NUM>. In some examples, the number of the second driving subcircuits <NUM>-<NUM> (e.g., N) is different from (e.g., greater or smaller) the number of the first driving subcircuits <NUM>-<NUM> (e.g., M), where N can be an integer larger than <NUM>. For illustration purposes, in the following, the number of the first driving subcircuits <NUM>-<NUM> and the number of the second driving subcircuits <NUM>-<NUM> are identical to M.

The second NAND gate <NUM> is configured to receive the first selection signal OCDPEN [M:<NUM>] and output data PUS [M:<NUM>] for selecting one or more first driving subcircuits <NUM>-<NUM> for data transfer among the M first driving subcircuits <NUM>-<NUM>. The second NOR gate <NUM> is configured to receive the second selection signal OCDNENB [M:<NUM>] and output data PDS [M:<NUM>] for selecting one or more second driving subcircuits <NUM>-<NUM> for the data transfer among the M second driving subcircuits <NUM>-<NUM>. The one or more second driving subcircuits <NUM>-<NUM> can correspond to the one or more first driving subcircuits <NUM>-<NUM>. For example, the number of the selected one or more second driving subcircuits <NUM>-<NUM> is identical to the number of the selected one or more first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] can be an inversion of the first selection signal OCDPEN [M:<NUM>]. Note that the first logic circuit <NUM> for DDR data <NUM> does not include logic gates for receiving the first selection signal or the second selection signal, which is simpler than the second logic circuit <NUM>. For DDR data transfer, the first logic subcircuit <NUM>-<NUM> can be conductively coupled to each of the M first driving subcircuits <NUM>-<NUM>, and the second logic subcircuit <NUM>-<NUM> can be conductively coupled to each of the M second driving subcircuits <NUM>-<NUM>.

In some embodiments, each of the first selection signal and the second selection signal is associated with a predetermined impedance for the driving circuit <NUM>. The predetermined impedance for the driving circuit <NUM> can be based on a combination of the one or more first driving subcircuits <NUM>-<NUM> and the one or more second driving subcircuits <NUM>-<NUM>. In some embodiments, the semiconductor device receives a command from the controller. The command can include information indicating the predetermined impedance for the driving circuit <NUM>, e.g., based on a loading coupled to the data output buffer <NUM>. For example, the command can include a set value for the predetermined impedance. Based on the set value in the command, the semiconductor device can select the one or more first driving subcircuits <NUM>-<NUM> and the one or more second driving subcircuits <NUM>-<NUM>. In some embodiments, the driving circuit <NUM> is configured to provide a series of impedances, and the controller can select one of the series of impedances to be included in the command. The controller can be configured to test different impedances to match the loading of the data output buffer <NUM> to identify an impedance that can provide a highest transfer speed for data transfer.

In the following, operations of the data output buffer <NUM> are described in view of <FIG>, showing the data output buffer <NUM> in DDR mode, SDR mode, ODT mode, and Output Disable mode, respectively. Table <NUM> also shows the operations of the data output buffer <NUM> under the four modes, where "<NUM>" and "<NUM>" correspond to a higher voltage level and a lower voltage level, respectively. Note that the ODTEN signal, the DDREN signal, the OE signal, OCDPEN[M:<NUM>] signal, and the OCDNENB[M:<NUM>] signal can be provided by the semiconductor device (e.g., the control logic <NUM> in the memory device <NUM> of <FIG>) to the data output buffer <NUM>. Each of the DDREN# signal, the ODTEN# signal, and the OE# signal can be obtained by using an inverter to invert the corresponding DDREN signal, the ODTEN signal, or the OE signal, respectively.

<FIG> illustrates DDR data transfer <NUM> in the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. As shown in Table <NUM> and <FIG>, at DDR mode, the DDREN signal has a higher voltage level "<NUM>", the ODTEN signal has a lower voltage level "<NUM>", and the output enable (OE) signal has a higher voltage level "<NUM>". The first selection signal OCDPEN[M:<NUM>] has a higher voltage level "<NUM>" for one or more selected first driving subcircuits <NUM>-<NUM> and a lower voltage level "<NUM>" for one or more other unselected first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] has a lower voltage level "<NUM>" for one or more selected second driving subcircuits <NUM>-<NUM> and a higher voltage level "<NUM>" for one or more other unselected second driving subcircuits <NUM>-<NUM>. Accordingly, the data PUS[M:<NUM>] has a constant value "<NUM>" to turn on the p-type transistor 312a in each of the one or more first driving subcircuits <NUM>-<NUM>, and the data PDS[M:<NUM>] has a constant value "<NUM>" to turn on the n-transistor 314b in each of the one or more second driving subcircuits <NUM>-<NUM>.

When DDR data <NUM> (either "<NUM>" or "<NUM>") is transferred through the data output buffer <NUM>, the data output buffer <NUM> outputs the DDR data <NUM> at the data output <NUM> of the driving circuit <NUM>, having the same value as the DDR data <NUM>. For example, with ODTEN being "<NUM>" and DDREN# being "<NUM>", the additional NOR gate <NUM> outputs the first control signal <NUM> with a higher voltage level "<NUM>". The second control signal <NUM> has a lower voltage level "<NUM>". Thus, the first NAND gate <NUM> outputs data DOP having the same value of DDR data <NUM>, and the first NOR gate <NUM> outputs data DON having the same value of DDR data <NUM>. Accordingly, the second inverter <NUM> outputs data PU with an inversion of the DDR data <NUM>, and the fourth inverter <NUM> outputs data PD having the inversion of the DDR data <NUM>.

When DDR data <NUM> is "<NUM>", the data PU is "<NUM>" and the data PD is "<NUM>", the p-type transistor 312b coupled to the first logic subcircuit <NUM>-<NUM> is turned on, while the n-type transistor 314a coupled to the second logic subcircuit <NUM>-<NUM> is turned off. As the p-type transistor 312a is on, the data output <NUM> is conductively coupled to the supply voltage and isolated from the electrical ground, thus providing a higher voltage level corresponding to "<NUM>", same as the DDR data <NUM>. Similarly, when DDR data <NUM> is "<NUM>", the data PU is "<NUM>" and the data PD is "<NUM>", the p-type transistor 312b coupled to the first logic subcircuit <NUM>-<NUM> is turned off, while the n-type transistor 314a coupled to the second logic subcircuit <NUM>-<NUM> is turned on. As the n-type transistor 314b is on, the data output <NUM> is conductively coupled to the electrical ground and isolated from the supply voltage, thus providing a lower voltage level corresponding to "<NUM>", same as the DDR data <NUM>.

<FIG> illustrates SDR data transfer <NUM> in the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. When SDR data <NUM> (either "<NUM>" or "<NUM>") is transferred through the data output buffer <NUM>, the data output buffer <NUM> outputs the SDR data <NUM> at the data output <NUM> of the driving circuit <NUM>, having the same value as the SDR data <NUM>.

As shown in Table <NUM> and <FIG>, at SDR mode, the DDREN signal has a lower voltage level "<NUM>", the ODTEN signal has a lower voltage level "<NUM>", and the output enable (OE) signal has a higher voltage level "<NUM>". The first selection signal OCDPEN[M:<NUM>] has a higher voltage level "<NUM>" for one or more selected first driving subcircuits <NUM>-<NUM> and a lower voltage level "<NUM>" for other unselected first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] has a lower voltage level "<NUM>" for one or more selected second driving subcircuits <NUM>-<NUM> and a higher voltage level "<NUM>" for other unselected second driving subcircuits <NUM>-<NUM>. Thus, with ODTEN being "<NUM>", DDREN being "<NUM>", and OE being "<NUM>", e.g., as shown in Table <NUM>, the data PUS[M:<NUM>] has a value "<NUM>" to turn off the p-type transistor 312a in each of the other unselected first driving subcircuits <NUM>-<NUM>, and the data PDS[M:<NUM>] has a value "<NUM>" to turn off the n-transistor 314b in each of the other unselected second driving subcircuits <NUM>-<NUM>. In contrast, the data PUS[M:<NUM>] has an inverted value of the SDR data <NUM> for the one or more selected first driving subcircuits <NUM>-<NUM>, and the data PDS [M:<NUM>] has an inverted value of the SDR data <NUM> for the one or more selected second driving subcircuits <NUM>-<NUM>.

Additionally, with ODTEN being "<NUM>" and DDREN# being "<NUM>", the additional NOR gate <NUM> outputs the first control signal <NUM> with a lower voltage level corresponding to "<NUM>". Thus, the first NAND gate <NUM> outputs data DOP having a value of "<NUM>" and the second inverter <NUM> outputs data PU having a value of "<NUM>" to turn on the p-type transistor 312b in each of the one or more first driving subcircuits <NUM>-<NUM>. Similarly, the second control signal <NUM> has a higher voltage level "<NUM>", and thus the first NOR gate <NUM> outputs data DON having "<NUM>" and the fourth inverter <NUM> outputs data PD having "<NUM>" to turn on the n-type transistor 314a in each of the one or more second driving subcircuits <NUM>-<NUM>.

When SDR data <NUM> is "<NUM>", the p-type transistor 312a in each of the one or more selected first driving subcircuits <NUM>-<NUM> is turned on, while the n-type transistor 314b in each of the one or more selected second driving subcircuits <NUM>-<NUM> is turned off. As the p-type transistor 312b is on, the data output <NUM> is conductively coupled to the supply voltage and isolated from the electrical ground, thus providing the output SDR data <NUM> having a higher voltage level corresponding to "<NUM>", same as the SDR data <NUM>. Similarly, when SDR data <NUM> is "<NUM>", the p-type transistor 312a in each of the one or more selected first driving subcircuits <NUM>-<NUM> is turned off, while the n-type transistor 314b in each of the one or more selected second driving subcircuits <NUM>-<NUM> is turned on. As the n-type transistor 314a is on, the data output <NUM> is conductively coupled to the electrical ground and isolated from the supply voltage, thus providing the output SDR data <NUM> having a lower voltage level corresponding to "<NUM>", same as the SDR data <NUM>.

<FIG> illustrates ODT mode <NUM> of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. The ODT mode can be enabled by the semiconductor device, e.g., based on a command from the controller.

In the ODT mode, the ODTEN signal <NUM> has a higher voltage level "<NUM>", and the data output buffer <NUM> is configured to turn on the p-type transistors 312a, 312b in the one or more first driving subcircuits <NUM>-<NUM> and the n-type transistors 314a, 314b in the one or more second driving subcircuits <NUM>-<NUM>, such that a current flow path <NUM> is formed from the supply voltage through the driving circuit <NUM> to the electrical ground. Thus, the data output <NUM> of the driving circuit <NUM> can be terminated.

In some embodiments, as illustrated in Table <NUM> and <FIG>, to enable the ODT mode, the ODTEN signal has a higher voltage level "<NUM>", and the OE signal has a higher voltage level "<NUM>". There can be no input for SDR data and DDR data. It does not care what the DDREN signal is. Accordingly, the data PU has a lower voltage level "<NUM>" to turn on the p-type transistor 312b in each of the one or more first driving subcircuits <NUM>-<NUM>, and the data PD has a higher voltage level "<NUM>" to turn on the n-type transistor 314a in each of the one or more second driving subcircuits <NUM>-<NUM>. The first selection signal OCDPEN[M:<NUM>] has a value "<NUM>" for one or more selected first driving subcircuits <NUM>-<NUM> and a value "<NUM>" for one or more other unselected first driving subcircuits <NUM>-<NUM>. Accordingly, the p-type transistor 312a in each of the one or more selected first driving subcircuits <NUM>-<NUM> is turned on and the p-type transistor 312a in each of the one or more other unselected first driving subcircuit <NUM>-<NUM> is turned off. Similarly, the second selection signal OCDNENB[M:<NUM>] has a value "<NUM>" for one or more selected second driving subcircuits <NUM>-<NUM> and a value "<NUM>" for one or more other unselected second driving subcircuits <NUM>-<NUM>. Accordingly, the n-type transistor 314b in each of the one or more selected second driving subcircuits <NUM>-<NUM> is turned on and the n-type transistor 314b in each of the one or more other unselected second driving subcircuit <NUM>-<NUM> is turned off. In such a way, the current flow path <NUM> can be formed from the supply voltage through the one or more selected first driving subcircuits <NUM>-<NUM> and the one or more selected second driving subcircuits <NUM>-<NUM> to the electrical ground.

<FIG> illustrates Output Disable mode <NUM> of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. The Output Disable mode can be enabled (or activated) by the semiconductor device, e.g., based on a command from the controller.

To enable the Output Disable mode, the ODTEN signal has a lower voltage level "<NUM>", the OE signal <NUM> has a lower voltage level "<NUM>" and the OE# signal <NUM> has a higher voltage level "<NUM>". It does not care for other signals, including DDREN signal, OCDPEN[M:<NUM>] signal, and OCDNENB[M:<NUM>] signal. As illustrated in Table <NUM> and <FIG>, the data PUS[M:<NUM>] has a higher voltage level "<NUM>" and the data PU has a higher voltage level "<NUM>", thus, the p-type transistors 312a, 312b in each of the one or more first driving subcircuits <NUM>-<NUM> are both turned off. Similarly, the data PDS[M:<NUM>] has a lower voltage level "<NUM>" and the data PD has a lower voltage level "<NUM>", thus, the n-type transistors 314a, 314b in each of the one or more second driving subcircuits <NUM>-<NUM> are both turned off. Therefore, there is no output at the data output <NUM>, or the data output <NUM> is floating.

<FIG> show another example data output buffer <NUM> for SDR and DDR data transfers in a semiconductor device, according to one or more implementations of the present disclosure. The semiconductor device can be the memory <NUM> of <FIG> or the memory device <NUM> of <FIG>. The data output buffer <NUM> can be implemented as the data output buffer <NUM> of <FIG>. The data output buffer <NUM> can be coupled between a data storage circuit such as a data cache circuit (e.g., the data cache circuit <NUM> of <FIG>) in the semiconductor device and a device interface (e.g., the memory interface <NUM> of <FIG>) of the semiconductor device. The data output buffer <NUM> can be configured to transfer data stored or cached in the data storage circuit through the device interface to a controller (e.g., the device controller <NUM> or the host controller <NUM> of <FIG>). <FIG> illustrate the data output buffer <NUM> in DDR data transfer mode, SDR data transfer mode, ODT mode, and Output Disable mode, respectively.

As discussed with further details in <FIG>, similar to the data output buffer <NUM> of <FIG>, the data output buffer <NUM> includes a first interface for receiving DDR data <NUM>, a second interface for receiving SDR data <NUM>, a first logic circuit <NUM> coupled to the first interface, and a second logic circuit <NUM> coupled to the second interface. Thus, the data output buffer <NUM> does not need to include a multiplexer, similar to the data output buffer <NUM>. However, different from the data output buffer <NUM>, the first logic circuit <NUM> and the second logic circuit <NUM> in the data output buffer <NUM> are coupled to same logic gates and transistors in a driving circuit <NUM>. That is, the DDR data transfer and the SDR data transfer share the same data path through the driving circuit <NUM>. Thus, the data output buffer <NUM> can include less logic gates or components than the data output buffer <NUM>, though a higher speed path for DDR data transfer may experience more complicated logic gates or components in the data output buffer <NUM> than the higher speed path for DDR data transfer in the data output buffer <NUM>.

<FIG> is a schematic diagram of the example data output buffer <NUM> for SDR and DDR data transfers, according to independent claim <NUM>. <FIG> is an example circuit diagram of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. The data output buffer <NUM> separates the higher speed data path <NUM> (as illustrated as thick lines in <FIG>) for DDR data transfer and a lower speed data path <NUM> for SDR data transfer, and simplifies logic circuits on the higher speed data path <NUM> to increase a transfer speed of the DDR data transfer. Also, with the separated data paths <NUM>, <NUM>, the data output buffer <NUM> can have no multiplexer to separate SDR data and DDR data from input interfaces, which can further simplify the logic circuits on the higher speed data path <NUM> to further increase the transfer speed of the DDR data transfer.

In some embodiments, the data output buffer <NUM> includes the first interface (e.g., DDR interface) for receiving DDR data (or DDR_DATA) <NUM> and the second interface (e.g., SDR interface) for receiving SDR data (or SDR_DATA) <NUM>. Each of the first interface and the second interface can be respectively coupled to the data storage circuit. In some embodiments, the semiconductor device is configured to receive a command from the controller. The command can include information for selecting one of DDR mode (or DDR interface) and the SDR mode (or SDR interface) for data transfer following the command. If the DDR mode or DDR interface is indicated in the command, the semiconductor device can be configured to transfer storage data (or cached data) in the data storage circuit out as DDR data to the first interface of the data output buffer <NUM>, e.g., by transferring data at both a falling edge and a rising edge of a clock signal at a clock frequency. If the SDR mode or SDR interface is indicated in the command, the semiconductor device can be configured to transfer storage data (or cached data) in the data storage circuit out as SDR data to the second interface of the data output buffer <NUM>, e.g., by transferring data at a falling edge or a rising edge of the clock signal at the clock frequency.

The data output buffer <NUM> includes the first logic circuit <NUM> coupled to the first interface to receive the DDR data <NUM> and the second logic circuit <NUM> coupled to the second interface to receive the SDR data <NUM>. The data output buffer <NUM> also includes the driving circuit <NUM> separately coupled to the first logic circuit <NUM> and the second logic circuit <NUM>. The driving circuit <NUM> includes a data output (data output node or data queue - DQ) <NUM> for outputting data corresponding to the DDR data <NUM> or data corresponding to the SDR data <NUM>, e.g., to the device interface. The first interface, the first logic circuit <NUM>, and the driving circuit <NUM> can be arranged in series to form the higher speed data path <NUM> to transfer the DDR data <NUM> with a first speed. The second interface, the second logic circuit <NUM>, and the driving circuit <NUM> can be arranged in series to form the lower speed data path <NUM> to transfer the SDR data <NUM> with a second speed. The first speed can be higher than the second speed, e.g., more than <NUM> %, <NUM> %, <NUM> %, or twice. As discussed with further details below, the first logic circuit <NUM> and the second logic circuit <NUM> can be configured to cause data to be transferred through the first logic circuit <NUM> with a higher speed than through the second logic circuit <NUM>, e.g., by including a smaller number of logic gates or transistors in the first logic circuit <NUM> than in the second logic circuit <NUM>.

In some embodiments, e.g., as illustrated in <FIG>, the driving circuit <NUM> includes one or more first driving subcircuits <NUM>-<NUM> each having at least one first-type transistor and one or more second driving subcircuits <NUM>-<NUM> each having at least one second-type transistor. The first-type transistor can be a p-type transistor such as p-channel metal-oxide-semiconductor (PMOS) transistor, and the second-type transistor can be an n-type transistor such as n-channel metal-oxide-semiconductor (NMOS) transistor. The one or more first driving subcircuits <NUM>-<NUM> are coupled between a supply voltage (e.g., VDD) and the data output <NUM>, and the one or more second driving subcircuits <NUM>-<NUM> are coupled between the data output <NUM> and an electrical ground (e.g., VSS or <NUM> V).

The first logic circuit <NUM> for the DDR data <NUM> can include a first logic subcircuit <NUM>-<NUM> coupled to the one or more first driving subcircuits <NUM>-<NUM> and a second logic subcircuit <NUM>-<NUM> coupled to the one or more second driving subcircuits <NUM>-<NUM>. The second logic circuit <NUM> for the SDR data <NUM> can include a third logic subcircuit <NUM>-<NUM> coupled to the one or more first driving subcircuits <NUM>-<NUM> and a fourth logic subcircuit <NUM>-<NUM> coupled to the one or more second driving subcircuits <NUM>-<NUM>.

In some embodiments, e.g., as illustrated in <FIG>, each of the one or more first driving subcircuits <NUM>-<NUM> includes a first NAND gate <NUM> and a p-type transistor <NUM> that are coupled in series between the first logic circuit <NUM> and the second logic circuit <NUM> and the data output <NUM>. The first NAND gate <NUM> has a first input coupled to the first logic subcircuit <NUM>-<NUM>, a second input coupled to the third logic subcircuit <NUM>-<NUM>, and an output coupled to a gate of the p-type transistor <NUM>. The p-type transistor <NUM> is coupled between a supply voltage (e.g., VDD) and the data output <NUM>. Each of the one or more second driving subcircuits <NUM>-<NUM> includes a first NOR gate <NUM> and an n-type transistor <NUM> that are coupled in series between the first logic circuit <NUM> and the second logic circuit <NUM> and the data output <NUM>. The first NOR gate <NUM> has a first input coupled to the second logic subcircuit <NUM>-<NUM>, a second input coupled to the fourth logic subcircuit <NUM>-<NUM>, and an output coupled to a gate of the n-type transistor <NUM>. The n-type transistor <NUM> is coupled between the data output <NUM> and an electrical ground (e.g., VSS or <NUM> V).

In some embodiments, e.g., as illustrated in <FIG>, the first logic subcircuit <NUM>-<NUM> includes a first inverter <NUM> and a second NAND gate <NUM> that are coupled in series between the first interface and the one or more first driving subcircuits <NUM>-<NUM>. The first inverter <NUM> is configured to invert the DDR data <NUM> from the first interface and output inverted DDR data DOPB. The second NAND gate <NUM> has a first input for receiving the inverted DDR data DOPB from the first inverter <NUM>, a second input for receiving a first control signal <NUM>, and an output for outputting data DOP to the first input of the first NAND gate <NUM> in each of the one or more first driving subcircuits <NUM>-<NUM>. The second logic subcircuit <NUM>-<NUM> includes a second inverter <NUM> and a second NOR gate <NUM> that are coupled in series between the first interface and the one or more second driving subcircuits <NUM>-<NUM>. The second inverter <NUM> is configured to invert the DDR data <NUM> from the first interface and output inverted DDR data DONB. The second NOR gate <NUM> has a first input for receiving the inverted DDR data DONB from the second inverter <NUM>, a second input for receiving a second control signal <NUM>, and an output for outputting data DON to the first input of the first NOR gate <NUM> in each of the one or more second driving subcircuits <NUM>-<NUM>.

In some embodiments, the first logic circuit <NUM> includes an additional first NOR gate <NUM> having a first input for receiving an ODT enable (ODTEN) signal, a second input for receiving an inverted DDR enable (DDREN#) signal, and an output for outputting the first control signal <NUM> to the second input of the second NAND gate <NUM>. The first logic circuit <NUM> can also include an additional inverter <NUM> coupled to the output of the additional first NOR gate <NUM> and configured to invert the first control signal <NUM> and output the second control signal <NUM> to the second input of the second NOR gate <NUM>. The second control signal <NUM> can be an inversion of the first control signal <NUM>. In some embodiments, at least one of the additional first NOR gate <NUM> or the additional inverter <NUM> can be arranged in the data output buffer <NUM> and out of the first logic circuit <NUM>.

As discussed with further details in <FIG>, the first control signal <NUM> and the second control signal <NUM> are configured to perform at least one of: i) allowing to output the DDR data <NUM> if the first interface is selected to receive the DDR data (e.g., as illustrated in <FIG>), or ii) keeping the output of the second NAND gate <NUM> to be "<NUM>" and the output of the second NOR gate <NUM> to be "<NUM>" if the second interface is selected to receive the lower-speed-type data (e.g., as illustrated in <FIG>) or in response to receiving an on die termination (ODT) enable signal for enabling an ODT mode (e.g., as illustrated in <FIG>).

In some embodiments, the second logic circuit <NUM> includes an additional second NOR gate <NUM> having a first input for receiving the ODTEN signal, a second input for receiving a DDR enable (DDREN) signal, and an output for outputting a third control signal <NUM>. In some embodiments, the additional second NOR gate <NUM> can be also included in the data output buffer <NUM> but out of the second logic circuit <NUM>.

In some embodiments, e.g., as illustrated in <FIG>, the third logic subcircuit <NUM>-<NUM> in the second logic circuit <NUM> includes a first OR gate <NUM> and a first AND gate <NUM> that are coupled in series between the second interface and the one or more first driving subcircuits <NUM>-<NUM>. The third logic subcircuit <NUM>-<NUM> can further include a third inverter <NUM> having an input coupled to the output of the additional second NOR gate <NUM> for receiving the third control signal <NUM> and an output for outputting an inverted third control signal <NUM> to the first OR gate <NUM>. The first OR gate <NUM> has a first input coupled to the output of the third inverter <NUM> for receiving the inverted third control signal <NUM>, a second input coupled to the second interface for receiving the SDR data <NUM>, and an output coupled to the first AND gate <NUM>. The first AND gate <NUM> has a first input coupled to the output of the first OR gate <NUM>, a second input for receiving an output enable (OE) signal, a third input for receiving a selection signal OCDPEN[M:<NUM>], and an output coupled to the second input of the first NAND gate <NUM> in each of the one or more first driving subcircuits <NUM>-<NUM>.

In some embodiments, as illustrated in <FIG>, the fourth logic subcircuit <NUM>-<NUM> in the second logic circuit <NUM> includes a second AND gate <NUM> and a second OR gate <NUM> that are coupled in series between the second interface and the one or more second driving subcircuits <NUM>-<NUM>. The second AND gate <NUM> has a first input coupled to the second interface for receiving the SDR data, a second input coupled to the output of the additional second NOR gate <NUM> for receiving the third control signal <NUM>, and an output coupled to the second OR gate <NUM>. The second OR gate <NUM> has a first input coupled to the output of the second AND gate <NUM>, a second input for receiving an inversion of the OE signal (OE#), a third input for receiving a second selection signal OCDNENB[M:<NUM>], and an output coupled to the second input of the first NOR gate <NUM> in each of the one or more second driving subcircuits <NUM>-<NUM>.

As discussed with further details in <FIG>, the data output buffer <NUM> is configured to perform at least one of i) allowing to output the SDR data <NUM> if the second interface is selected to receive the SDR data <NUM> (e.g., as illustrated in <FIG>), ii) keeping the output of the first AND gate <NUM> to be "<NUM>" and the output of the second OR gate <NUM> to be "<NUM>" if the first interface is selected to receive the DDR data (e.g., as illustrated in <FIG>) or in response to receiving the ODTEN signal for enabling the ODT mode and the OE signal with a higher voltage level (e.g., as illustrated in <FIG>), or iii) keeping the output of the first AND gate <NUM> to be "<NUM>" and the output of the second OR gate <NUM> to be "<NUM>" in response to receiving an output disable signal for disabling the data output <NUM> of the driving circuit <NUM>. The output disable signal can be the output enable (OE) signal with a lower voltage level "<NUM>".

In some embodiments, e.g., as illustrated in <FIG>, the driving circuit <NUM> includes M first driving subcircuits <NUM>-<NUM> coupled in parallel with the supply voltage and the data output <NUM> and M second driving subcircuits <NUM>-<NUM> coupled in parallel with the data output <NUM> and the electrical ground. The M second driving subcircuits <NUM>-<NUM> can correspond to the M first driving subcircuits <NUM>-<NUM>. M can be an integer larger than <NUM>. For example, the number of the second driving subcircuits <NUM>-<NUM> (e.g., M) is identical to the number of the first driving subcircuits <NUM>-<NUM> (e.g., M).

The first AND gate <NUM> is configured to receive the first selection signal OCDPEN [M:<NUM>] and output data for selecting one or more first driving subcircuits <NUM>-<NUM> for data transfer among the M first driving subcircuits <NUM>-<NUM>. The second OR gate <NUM> is configured to receive the second selection signal OCDNENB [M:<NUM>] and output data for selecting one or more second driving subcircuits <NUM>-<NUM> for the data transfer among the M second driving subcircuits <NUM>-<NUM>. The one or more second driving subcircuits <NUM>-<NUM> can correspond to the one or more first driving subcircuits <NUM>-<NUM>. For example, the number of the selected one or more second driving subcircuits <NUM>-<NUM> is identical to the number of the selected one or more first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] can be an inversion of the first selection signal OCDPEN [M:<NUM>]. Note that the first logic circuit <NUM> for DDR data <NUM> does not include logic gates for receiving the first selection signal or the second selection signal, which is simpler than the second logic circuit <NUM>.

In some embodiments, each of the first selection signal and the second selection signal is associated with a predetermined impedance for the driving circuit <NUM>. The predetermined impedance for the driving circuit <NUM> can be based on a combination of the selected one or more first driving subcircuits <NUM>-<NUM> and the selected one or more second driving subcircuits <NUM>-<NUM>. In some embodiments, the semiconductor device receives a command from the controller. The command can include information indicating the predetermined impedance for the driving circuit <NUM>, e.g., based on a loading coupled to the data output buffer <NUM>. For example, the command can include a set value for the predetermined impedance. Based on the set value in the command, the semiconductor device can select the one or more first driving subcircuits <NUM>-<NUM> and the one or more second driving subcircuits <NUM>-<NUM>. In some embodiments, the driving circuit <NUM> is configured to provide a series of impedances, and the controller can select one of the series of impedances to be included in the command. The controller can be configured to test different impedances to match the loading of the data output buffer <NUM> to identify an impedance that can provide a highest transfer speed for data transfer.

In the following, operations of the data output buffer <NUM> are described in view of <FIG>, showing the data output buffer <NUM> in DDR mode, SDR mode, ODT mode, and Output Disable mode, respectively. Table <NUM> also shows the operations of the data output buffer <NUM> under the four modes, where "<NUM>" and "<NUM>" correspond to a higher voltage level and a lower voltage level, respectively. Note that the ODTEN signal, the DDREN signal, the OE signal, OCDPEN[M:<NUM>] signal, and the OCDNENB[M:<NUM>] signal can be provided by the semiconductor device (e.g., the control logic <NUM> in the memory device <NUM> of <FIG>) to the data output buffer <NUM>. The DDREN# signal can be obtained by using an inverter to invert the corresponding DDREN signal, and the OE# signal can be obtained by using an inverter to invert the corresponding the OE signal.

<FIG> illustrates DDR data transfer <NUM> in the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. As shown in Table <NUM> and <FIG>, at DDR mode, the DDREN signal has a higher voltage level "<NUM>", the ODTEN signal has a lower voltage level "<NUM>", and the output enable (OE) signal has a higher voltage level "<NUM>". The first selection signal OCDPEN[M:<NUM>] has a higher voltage level "<NUM>" for one or more selected first driving subcircuits <NUM>-<NUM> and a lower voltage level "<NUM>" for other unselected first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] has a lower voltage level "<NUM>" for one or more selected second driving subcircuits <NUM>-<NUM> and a higher voltage level "<NUM>" for other unselected second driving subcircuits <NUM>-<NUM>.

When DDR data <NUM> (either "<NUM>" or "<NUM>") is transferred through the data output buffer <NUM>, the data output buffer <NUM> outputs the DDR data <NUM> at the data output <NUM> of the driving circuit <NUM>, having the same value as the DDR data <NUM>. For example, with ODTEN being "<NUM>" and DDREN# being "<NUM>", the additional first NOR gate <NUM> outputs the first control signal <NUM> with a higher voltage level corresponding to "<NUM>". The second control signal <NUM> has a lower voltage level corresponding to "<NUM>". Thus, the second NAND gate <NUM> outputs data DOP having the same value of DDR data <NUM>, and the second NOR gate <NUM> outputs data DON having the same value of DDR data <NUM>.

Accordingly, for the one or more selected first driving subcircuits <NUM>-<NUM>, the first NAND gate <NUM> outputs data PU0 with an inversion of the DDR data <NUM>, and the p-type transistor <NUM> is turned on when the DDR data <NUM> has a value "<NUM>" and turned off when the DDR data <NUM> has a value "<NUM>". Similarly, for the one or more selected second driving subcircuits <NUM>-<NUM>, the first NOR gate <NUM> outputs data PD having the inversion of the DDR data <NUM>, and the n-type transistor <NUM> is turned off when the DDR data <NUM> has a value "<NUM>" and turned on when the DDR data <NUM> has a value "<NUM>". Therefore, when the DDR data <NUM> has a value "<NUM>", the p-type transistor <NUM> coupled to the supply voltage is turned on and the n-type transistor <NUM> coupled to the electrical ground is turned off. Thus, the data output <NUM> is conductively coupled to the supply voltage and isolated from the electrical ground, providing a higher voltage level corresponding to "<NUM>", same as the DDR data <NUM>. Similarly, when DDR data <NUM> has a value "<NUM>", the p-type transistor <NUM> coupled to the supply voltage is turned off and the n-type transistor <NUM> coupled to the electrical ground is turned on. Thus, the data output <NUM> is conductively coupled to the electrical ground and isolated from the supply voltage, providing a lower voltage level corresponding to "<NUM>", same as the DDR data <NUM>.

As shown in Table <NUM> and <FIG>, at SDR mode, the DDREN signal has a lower voltage level "<NUM>", the ODTEN signal has a lower voltage level "<NUM>", and the output enable (OE) signal has a higher voltage level "<NUM>". The first selection signal OCDPEN[M:<NUM>] has a higher voltage level "<NUM>" for one or more selected first driving subcircuits <NUM>-<NUM> and a lower voltage level "<NUM>" for other unselected first driving subcircuits <NUM>-<NUM>. The second selection signal OCDNENB[M:<NUM>] has a lower voltage level "<NUM>" for one or more selected second driving subcircuits <NUM>-<NUM> and a higher voltage level "<NUM>" for other unselected second driving subcircuits <NUM>-<NUM>. Thus, with ODTEN being "<NUM>", DDREN being "<NUM>", and OE being "<NUM>", e.g., as shown in Table <NUM>, the first AND gate <NUM> outputs the SDR data <NUM> for the one or more selected first driving subcircuits <NUM>-<NUM> and "<NUM>" for the other unselected first driving subcircuits <NUM>-<NUM>, and the second OR gate <NUM> outputs the SDR data <NUM> for the one or more selected second driving subcircuits <NUM>-<NUM> and "<NUM>" for the other unselected second driving subcircuits <NUM>-<NUM>.

Additionally, with ODTEN being "<NUM>" and DDREN# being "<NUM>", the additional first NOR gate <NUM> outputs the first control signal <NUM> with a lower voltage level corresponding to "<NUM>". Thus, the second NAND gate <NUM> outputs data DOP having "<NUM>". The additional inverter <NUM> receives the first control signal <NUM> and outputs the second control signal <NUM> with a higher voltage level "<NUM>". Thus, the second NOR gate <NUM> outputs data DON having "<NUM>".

Accordingly, with the DOP being "<NUM>", for the one or more selected first driving subcircuits <NUM>-<NUM>, the first NAND gate <NUM> outputs data PU0 with an inversion of the SDR data <NUM>, and the p-type transistor <NUM> is turned on when the SDR data <NUM> has a value "<NUM>" and turned off when the SDR data <NUM> has a value "<NUM>". Similarly, with DON being "<NUM>", for the one or more selected second driving subcircuits <NUM>-<NUM>, the first NOR gate <NUM> outputs data PD having the inversion of the SDR data <NUM>, and the n-type transistor <NUM> is turned off when the SDR data <NUM> has a value "<NUM>" and turned on when the SDR data <NUM> has a value "<NUM>". Therefore, when the SDR data <NUM> has a value "<NUM>", the p-type transistor <NUM> coupled to the supply voltage is turned on and the n-type transistor <NUM> coupled to the electrical ground is turned off. Thus, the data output <NUM> is conductively coupled to the supply voltage and isolated from the electrical ground, providing a higher voltage level corresponding to "<NUM>", same as the SDR data <NUM>. Similarly, when SDR data <NUM> has a value "<NUM>", the p-type transistor <NUM> coupled to the supply voltage is turned off and the n-type transistor <NUM> coupled to the electrical ground is turned on. Thus, the data output <NUM> is conductively coupled to the electrical ground and isolated from the supply voltage, providing a lower voltage level corresponding to "<NUM>", same as the SDR data <NUM>.

<FIG> illustrates ODT mode <NUM> of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. In the ODT mode, the ODTEN signal <NUM> has a higher voltage level corresponding to value "<NUM>", and the data output buffer <NUM> is configured to turn on the p-type transistor <NUM> in the one or more first driving subcircuits <NUM>-<NUM> and the n-type transistor <NUM> in the one or more second driving subcircuits <NUM>-<NUM>, such that a current flow path <NUM> is formed from the supply voltage through the driving circuit <NUM> to the electrical ground. Thus, the data output <NUM> of the driving circuit <NUM> is terminated.

In some embodiments, as illustrated in Table <NUM> and <FIG>, to enable the ODT mode, the ODTEN signal has a higher voltage level "<NUM>", and the OE signal has a higher voltage level "<NUM>". There can be no input for SDR data and DDR data. It does not care what the DDREN signal is. Accordingly, the second NAND gate <NUM> outputs DOP having a higher voltage level "<NUM>", and the first AND gate <NUM> outputs data identical to the first selection signal OCDPEN[M:<NUM>], that is, "<NUM>" for the one or more selected first driving subcircuits <NUM>-<NUM> and "<NUM>" for the other unselected first driving subcircuits <NUM>-<NUM>. Thus, the first NAND <NUM> outputs data PU0 having a lower voltage level "<NUM>" for the one or more selected first driving circuits <NUM>-<NUM> and a higher voltage level "<NUM>" for the other unselected first driving circuits <NUM>-<NUM>. Accordingly, the p-type transistor <NUM> in each of the one or more selected first driving subcircuits <NUM>-<NUM> is turned on and the p-type transistor <NUM> in each of the other unselected first driving subcircuits <NUM>-<NUM> is turned off.

Similarly, with the ODTEN having the higher voltage level "<NUM>", the second NOR gate <NUM> outputs DON with a lower voltage level "<NUM>", and the second OR gate <NUM> outputs data identical to the second selection signal OCDNENB[M:<NUM>], that is, "<NUM>" for the one or more selected second driving subcircuits <NUM>-<NUM> and "<NUM>" for the other unselected second driving subcircuits <NUM>-<NUM>. Thus, the first NOR <NUM> outputs data PD0 having a higher voltage level "<NUM>" for the one or more selected second driving circuits <NUM>-<NUM> and a lower voltage level "<NUM>" for the other unselected second driving circuits <NUM>-<NUM>. Accordingly, the n-type transistor <NUM> in each of the one or more selected second driving subcircuits <NUM>-<NUM> is turned on and the n-type transistor <NUM> in each of the other unselected second driving subcircuits <NUM>-<NUM> is turned off. In such a way, the driving circuit <NUM> can have a predetermined impedance and the current flow path <NUM> can be formed from the supply voltage through the one or more first driving subcircuits <NUM>-<NUM> and the one or more second driving subcircuits <NUM>-<NUM> to the electrical ground.

<FIG> illustrates Output Disable mode <NUM> of the data output buffer <NUM> of <FIG>, according to one or more implementations of the present disclosure. To enable the Output Disable mode, the OE signal <NUM> has a lower voltage level "<NUM>" and the OE# signal <NUM> has a higher voltage level "<NUM>". It does not care for other signals, including ODTEN signal, DDREN signal, OCDPEN[M:<NUM>] signal, and OCDNENB[M:<NUM>] signal. As illustrated in Table <NUM> and <FIG>, the data PU0 has a higher voltage level "<NUM>", thus, the p-type transistor <NUM> in each of the one or more first driving subcircuits <NUM>-<NUM> is turned off. Similarly, the data PD0 has a lower voltage level "<NUM>", thus, the n-type transistor <NUM> in each of the one or more second driving subcircuits <NUM>-<NUM> is turned off. Therefore, there is no output at the data output <NUM>, or the data output <NUM> is floating.

<FIG> is a flow chart of an example process <NUM> of managing data transfers in a semiconductor device, according to one or more implementations of the present disclosure. The semiconductor device can be the memory <NUM> of <FIG> or the memory device <NUM> of <FIG>. The semiconductor device can include a data output buffer, e.g., the data output buffer <NUM> of <FIG>, the data output buffer <NUM> of <FIG>, or the data output buffer <NUM> of <FIG>.

In some embodiments, the semiconductor device includes a data storage circuit such as a data cache circuit (e.g., the data cache circuit <NUM> of <FIG>) and a device interface (e.g., the memory interface <NUM> of <FIG>). The semiconductor device can include a memory cell array (e.g., the memory cell array <NUM> of <FIG>) for storing data. During a read operation, data can be read out from the memory cell array and cached in the data storage circuit. The data output buffer can be coupled between the data storage circuit and the device interface. The data output buffer can be configured to transfer data stored or cached in the data storage circuit through the device interface to a controller (e.g., the device controller <NUM> or the host controller <NUM> of <FIG>).

The process <NUM> can be performed by the semiconductor device. As shown in <FIG>, the process <NUM> can include subprocess <NUM> for transferring higher-speed-type data and subprocess <NUM> for transferring lower-speed-type data. In some embodiments, the higher-speed-type data includes double data rate (DDR) data and the lower-speed-type data includes single data rate (SDR) data. In some embodiments, the higher-speed-type data includes quad data rate (QDR) data and the lower-speed-type data includes SDR data or DDR data. Subprocess <NUM> and subprocess <NUM> can be performed in any suitable order. Each subprocess <NUM>, <NUM> can include one or more steps.

For subprocess <NUM>, at step <NUM>, a first interface is selected to receive higher-speed-type data. The first interface can be selected by the semiconductor device based on a command received from the controller. The command can indicate which interface to be selected for data transfer following the command. The semiconductor can include the first interface for receiving the higher-speed-type data and a second interface for receiving the lower-speed-type data. Based on the command, the semiconductor device can transfer data stored or cached in the data storage circuit as the higher-speed-type data or the lower-speed-type data.

At step <NUM>, the higher-speed-type data is transferred with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit. The first logic circuit can be the first logic circuit <NUM> in <FIG> or the first logic circuit <NUM> in <FIG>. The driving circuit can be the driving circuit <NUM> in <FIG> or <NUM> in <FIG>. The first data path can be the higher speed data path <NUM> in <FIG> or <NUM> in <FIG>.

At step <NUM>, the higher-speed-type data is outputted at a data output of the driving circuit, e.g., to the device interface. The data output can be the data output <NUM> of <FIG> or <NUM> of <FIG>.

For subprocess <NUM>, at step <NUM>, the second interface is selected to receive lower-speed-type data, e.g., based on a command from the controller. At step <NUM>, the lower-speed-type data is transferred with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit. The second logic circuit can be the second logic circuit <NUM> in <FIG> or the second logic circuit <NUM> in <FIG>. The second data path can be the higher speed data path <NUM> in <FIG> or <NUM> in <FIG>. At step <NUM>, the lower-speed-type data is outputted at the data output of the driving circuit, e.g., to the device interface. The data output can be the data output <NUM> of <FIG> or <NUM> of <FIG>.

In some embodiments, the first logic circuit and the second logic circuit are configured to cause data to be transferred through the first logic circuit with a higher speed than through the second logic circuit. In some embodiments, the first logic circuit includes a smaller number of logic gates or transistors than the second logic circuit.

In some embodiments, the driving circuit includes one or more first driving subcircuits (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) each including at least one first-type transistor, and one or more second driving subcircuits (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) each including at least one second-type transistor. The first logic circuit can include a first logic subcircuit (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) coupled to the one or more first driving subcircuits and a second logic subcircuit (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) coupled to the one or more second driving subcircuits. The second logic circuit can include a third logic subcircuit (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) coupled to the one or more first driving subcircuits and a fourth logic subcircuit (e.g., <NUM>-<NUM> of <FIG> or <NUM>-<NUM> of <FIG>) coupled to the one or more second driving subcircuits. The first-type transistor can include a p-type transistor (e.g., PMOS transistor), and the second-type transistor can include an n-type transistor (e.g., NMOS transistor). The one or more first driving subcircuits can be coupled between a supply voltage and the data output, and the one or more second driving subcircuits can be coupled between the data output and an electrical ground.

In some embodiments, e.g., as illustrated in <FIG>, each of the one or more first driving subcircuits (e.g., <NUM>-<NUM> of <FIG>) includes two first-type transistors (e.g., the p-type transistors 312a, 312b of <FIG>) coupled in series between the supply voltage and the data output, and each of the first logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) and the third logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) is coupled to a respective first-type transistor (e.g., 312b, 312a of <FIG>) of the two first-type transistors in each of the one or more first driving subcircuits. Each of the one or more second driving subcircuits (e.g., <NUM>-<NUM> of <FIG>) can include two second-type transistors (e.g., 314a, 314b of <FIG>) coupled in series between the data output and the electrical ground, and each of the second logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) and the fourth logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) is coupled to a respective second-type transistor (e.g., 314a, 314b of <FIG>) of the two second-type transistors in each of the one or more second driving subcircuits.

In some embodiments, the second logic circuit is configured such that, if the first interface is selected to receive the higher-speed-type data, the respective first-type transistor coupled to the third logic subcircuit and the respective second-type transistor coupled to the fourth logic subcircuit are turned on, and the driving circuit outputs the data corresponding to the higher-speed-type data at the data output, e.g., as illustrated in <FIG>. The first logic circuit is configured such that, if the second interface is selected to receive the lower-speed-type data, the respective first-type transistor coupled to the first logic subcircuit and the respective second-type transistor coupled to the second logic subcircuit are turned on, and the driving circuit outputs the data corresponding to the lower-speed-type data at the data output, e.g., as illustrated in <FIG>.

In some embodiments, each of the two first-type transistors includes a p-type transistor, and each of the two second-type transistors includes an n-type transistor. The first logic subcircuit includes a first NAND gate (e.g., <NUM> of <FIG>) having a first input for receiving inverted higher-speed-type data and a second input for receiving a first control signal (e.g., <NUM> of <FIG>). The second logic subcircuit includes a first NOR gate (e.g., <NUM> of <FIG>) having a first input for receiving the inverted higher-speed-type data and a second input for receiving a second control signal (e.g., <NUM> of <FIG>).

In some embodiments, the first control signal and the second control signal are configured to perform at least one of: i) allowing to output the higher-speed-type data if the first interface is selected to receive the higher-speed-type data (e.g., as illustrated in <FIG>), ii) keeping a respective p-type transistor coupled to the first logic subcircuit on and a respective n-type transistor coupled to the second logic subcircuit on if the second interface is selected to receive the lower-speed-type data (e.g., as illustrated in <FIG>) or in response to receiving an on die termination (ODT) enable signal for enabling an ODT mode (e.g., as illustrated in <FIG>), or iii) keeping the respective p-type transistor coupled to the first logic subcircuit off and the respective n-type transistor coupled to the second logic subcircuit off in response to receiving an output disable signal for disabling the data output of the driving circuit (e.g., as illustrated in <FIG>).

In some embodiments, the first logic circuit further includes: an additional NOR gate (e.g., <NUM> of <FIG>) having a first input for receiving the ODT enable signal (e.g., ODTEN of <FIG>), a second input for receiving an inverted higher-speed-type enable signal (e.g., DDREN# of <FIG>), and an output for outputting the first control signal to the second input of the first NAND gate, and an additional inverter (e.g., <NUM> of <FIG>) configured to receive the first control signal from the output of the additional NOR gate and output the second control signal (e.g., <NUM> of <FIG>) to the second input of the first NOR gate, the second control signal being an inversion of the first control signal.

In some embodiments, the first logic subcircuit further includes: a first inverter (e.g., <NUM> of <FIG>) configured to receive the higher-speed-type data from the first interface and output the inverted higher-speed-type data to the first input of the first NAND gate, and a second inverter (e.g., <NUM> of <FIG>) having an input coupled to an output of the first NAND gate and an output coupled to the respective p-type transistor coupled to the first logic subcircuit in each of the one or more first driving subcircuits. The second logic subcircuit can further include: a third inverter (e.g., <NUM> of <FIG>) configured to receive the higher-speed-type data from the first interface and output the inverted higher-speed-type data to the first input of the first NOR gate, and a fourth inverter (e.g., <NUM> of <FIG>) having an input coupled to an output of the first NOR gate and an output coupled to the respective n-type transistor coupled to the second logic subcircuit in each of the one or more second driving subcircuits.

In some embodiments, the third logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) includes: an OR gate (e.g., <NUM> of <FIG>) having a first input for receiving the lower-speed-type data from the second interface, a second input for receiving an ODT enable signal, a third input for receiving a higher-speed-type enable signal (e.g., DDREN of <FIG>), and an output, and a second NAND gate (e.g., <NUM> of <FIG>) having a first input coupled to the output for the OR gate, a second input for receiving an output enable signal (e.g., OE of <FIG>), and an output coupled to a respective p-type transistor (e.g., 312a of <FIG>) coupled to the third logic subcircuit in each of the one or more first driving subcircuits. The fourth logic subcircuit can include: an AND gate (e.g., <NUM> of <FIG>) having a first input for receiving the lower-speed-type data from the second interface, a second input for receiving an inversion of the ODT enable signal, a third input for receiving an inversion of the higher-speed-type enable signal, and an output, and a second NOR gate (e.g., <NUM> of <FIG>) having a first input coupled to the output of the AND gate, a second input for receiving an inversion of the output enable signal, and an output coupled to a respective n-type transistor coupled to the fourth logic subcircuit in each of the one or more second driving subcircuits.

In some embodiments, the data output buffer is configured to perform at least one of: i) allowing to output the lower-speed-type data if the second interface is selected to receive the lower-speed-type data (e.g., as illustrated in <FIG>), ii) keeping a respective p-type transistor coupled to the third logic subcircuit on and a respective n-type transistor coupled to the fourth logic subcircuit on if the first interface is selected to receive the higher-speed-type data (e.g., as illustrated in <FIG>) or in response to receiving the ODT enable signal for enabling the ODT mode and the output enable signal with a higher voltage level (e.g., as illustrated in <FIG>), or iii) keeping the respective p-type transistor coupled to the third logic subcircuit off and the respective n-type transistor coupled to the fourth logic subcircuit off in response to receiving the output disable signal for disabling the data output of the driving circuit (e.g., as illustrated in <FIG>). The output disable signal can be the output enable signal with a lower voltage level.

In some embodiments, the driving circuit includes a plurality of first driving subcircuits coupled in parallel with the supply voltage and the data output and a plurality of second driving subcircuits coupled in parallel with the data output and the electrical ground. The plurality of second driving subcircuits can correspond to the plurality of first driving subcircuits. The second NAND gate can include a third input for receiving a first selection signal (e.g., OCDPEN[M:<NUM>]) for selecting one or more first driving subcircuits for data transfer among the plurality of first driving subcircuits. The second NOR gate includes a third input for receiving a second selection signal for selecting one or more second driving subcircuits for the data transfer among the plurality of second driving subcircuits. The one or more second driving subcircuits can correspond to the one or more first driving subcircuits. The second selection signal can be an inversion of the first selection signal or be controlled independently from the first selection signal. Each of the first selection signal and the second selection signal can be associated with a predetermined impedance for the driving circuit, and the predetermined impedance for the driving circuit can be based on a combination of the one or more first driving subcircuits and the one or more second driving subcircuits.

In some embodiments, e.g., as illustrated in <FIG>, in the driving circuit (e.g., <NUM> of <FIG>), each of the one or more first driving subcircuits (e.g., <NUM>-<NUM> of <FIG>) includes: a first-type transistor (e.g., the p-type transistor <NUM> of <FIG>) coupled between the supply voltage and the data output, and a first NAND gate (e.g., <NUM> of <FIG>) having a first input coupled to the first logic subcircuit, a second input coupled to the third logic subcircuit, and an output coupled to the first-type transistor. Each of the one or more second driving subcircuits (e.g., <NUM>-<NUM> of <FIG>) can include: a second-type transistor (e.g., the n-type transistor <NUM> of <FIG>) coupled between the data output and the electrical ground, and a first NOR gate (e.g., <NUM> of <FIG>) having a first input coupled to the second logic subcircuit, a second input coupled to the fourth logic subcircuit, and an output coupled to the second-type transistor.

In some embodiments, the first logic subcircuit includes: a first inverter (e.g., <NUM> of <FIG>) configured to invert the higher-speed-type data from the first interface, and a second NAND gate (e.g., <NUM> of <FIG>) having a first input for receiving the inverted higher-speed-type data from the first inverter, a second input for receiving a first control signal (e.g., <NUM> of <FIG>), and an output coupled to the first input of the first NAND gate in each of the one or more first driving subcircuits. The second logic subcircuit includes: a second inverter (e.g., <NUM> of <FIG>) configured to invert the higher-speed-type data from the first interface, and a second NOR gate (e.g., <NUM> of <FIG>) having a first input for receiving the inverted higher-speed-type data from the second inverter, a second input for receiving a second control signal (e.g., <NUM> of <FIG>), and an output coupled to the first input of the first NOR gate in each of the one or more second driving subcircuits.

In some embodiments, the first control signal and the second control signal are configured to perform at least one of: i) allowing to output the higher-speed-type data if the first interface is selected to receive the higher-speed-type data (e.g., as illustrated in <FIG>), or ii) keeping the output of the second NAND gate to be "<NUM>" and the output of the second NOR gate to be "<NUM>" if the second interface is selected to receive the lower-speed-type data (e.g., as illustrated in <FIG>) or in response to receiving an on die termination (ODT) enable signal for enabling an ODT mode (e.g., as illustrated in <FIG>).

In some embodiments, the data output buffer further includes: an additional first NOR gate (e.g., <NUM> of <FIG>) having a first input for receiving the ODT enable signal, a second input for receiving an inverted higher-speed-type enable signal, and an output for outputting the first control signal to the second input of the second NAND gate, and an additional inverter (e.g., <NUM> of <FIG>) configured to receive the first control signal from the output of the additional first NOR gate and output the second control signal to the second input of the second NOR gate, the second control signal being an inversion of the first control signal. In some embodiments, the first logic circuit includes the additional first NOR gate and the additional inverter.

In some embodiments, the data output buffer further includes an additional second NOR gate (e.g., <NUM> of <FIG>) having a first input for receiving the ODT enable signal, a second input for receiving a higher-speed-type enable signal, and an output for outputting a third control signal (e.g., <NUM> of <FIG>).

In some embodiments, the third logic subcircuit includes: a third inverter (e.g., <NUM> of <FIG>) having an input coupled to the output of the additional second NOR gate for receiving the third control signal and an output for outputting an inverted third control signal (e.g., <NUM> of <FIG>), a first OR gate (e.g., <NUM> of <FIG>) having a first input coupled to the output of the third inverter for receiving the inverted third control signal, a second input coupled to the second interface for receiving the lower-speed-type data, and an output, and a first AND gate (e.g., <NUM> of <FIG>) having a first input coupled to the output of the first OR gate, a second input for receiving an output enable signal, and an output coupled to the second input of the first NAND gate in each of the one or more first driving subcircuits.

In some embodiments, the fourth logic subcircuit (e.g., <NUM>-<NUM> of <FIG>) includes a second AND gate (e.g., <NUM> of <FIG>) having a first input coupled to the second interface for receiving the lower-speed-type data, a second input coupled to the output of the additional second NOR gate for receiving the third control signal, and an output, and a second OR gate (e.g., <NUM> of <FIG>) having a first input coupled to the output of the second AND gate, a second input for receiving an inversion of the output enable signal, and an output coupled to the second input of the first NOR gate in each of the one or more second driving subcircuits.

In some embodiments, the data output buffer is configured to perform at least one of: i) allowing to output the lower-speed-type data if the second interface is selected to receive the lower-speed-type data (e.g., as illustrated in <FIG>), ii) keeping the output of the first AND gate to be "<NUM>" and the output of the second OR gate to be "<NUM>" if the first interface is selected to receive the higher-speed-type data (e.g., as illustrated in <FIG>) or in response to receiving the ODT enable signal for enabling the ODT mode and the output enable signal with a higher voltage level (e.g., as illustrated in <FIG>), or iii) keeping the output of the first AND gate to be "<NUM>" and the output of the second OR gate to be "<NUM>" in response to receiving an output disable signal for disabling the data output of the driving circuit (e.g., as illustrated in <FIG>). The output disable signal can be the output enable signal with a lower voltage level.

In some embodiments, the driving circuit includes a plurality of first driving subcircuits coupled in parallel with the supply voltage and the data output and a plurality of second driving subcircuits coupled in parallel with the data output and the electrical ground. The plurality of second driving subcircuits can correspond to the plurality of first driving subcircuits. The first AND gate can include a third input for receiving a first selection signal for selecting one or more first driving subcircuits for data transfer among the plurality of first driving subcircuits, and the second OR gate includes a third input for receiving a second selection signal for selecting one or more second driving subcircuits for the data transfer among the plurality of second driving subcircuits. The one or more second driving subcircuits can correspond to the one or more first driving subcircuits. The second selection signal can be an inversion of the first selection signal, or be controlled independently from the first selection signal.

In some embodiments, each of the first selection signal and the second selection signal is associated with a predetermined impedance for the driving circuit, and wherein the predetermined impedance for the driving circuit is based on a combination of the one or more first driving subcircuits and the one or more second driving subcircuits.

The disclosed and other examples can be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more them.

A system may encompass all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. A system can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A computer program can be deployed for execution on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communications network.

The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein.

Claim 1:
An integrated circuit (<NUM>), comprising:
a first interface (<NUM>) for receiving higher-speed-type data;
a second interface (<NUM>) for receiving lower-speed-type data;
a first logic circuit (<NUM>) coupled to the first interface (<NUM>), comprising a first logic subcircuit (<NUM>-<NUM>) and a second logic subcircuit (<NUM>-<NUM>);
a second logic circuit (<NUM>) coupled to the second interface (<NUM>), comprising a third logic subcircuit (<NUM>-<NUM>) and a fourth logic subcircuit (<NUM>-<NUM>); and
a driving circuit (<NUM>) comprising:
a data output (<NUM>);
one or more first driving subcircuits (<NUM>-<NUM>) each comprising two first-type transistors (312a, 312b) coupled in series between a supply voltage and the data output (<NUM>); and
one or more second driving subcircuits (<NUM>-<NUM>) each comprising two second-type transistors (314a, 314b) coupled in series between the data output (<NUM>) and an electrical ground;
wherein each of the first logic subcircuit (<NUM>-<NUM>) and the third logic subcircuit (<NUM>-<NUM>) is coupled to a respective first-type transistor (312a, 312b) of the two first-type transistors in each of the one or more first driving subcircuits (<NUM>-<NUM>),
wherein each of the second logic subcircuit (<NUM>-<NUM>) and the fourth logic subcircuit (<NUM>-<NUM>) is coupled to a respective second-type transistor (314a, 314b) of the two second-type transistors in each of the one or more second driving subcircuits (<NUM>-<NUM>),
wherein the driving circuit (<NUM>) is configured to output i) data corresponding to the higher-speed-type data if the first interface (<NUM>) receives the higher-speed-type data, and ii) data corresponding to the lower-speed-type data if the second interface (<NUM>) receives the lower-speed-type data, and
wherein the first interface (<NUM>), the first logic circuit (<NUM>), and the driving circuit (<NUM>) are arranged to form a first data path for transferring the higher-speed-type data with a first speed, and wherein the second interface (<NUM>), the second logic circuit (<NUM>), and the driving circuit (<NUM>) are arranged to form a second data path for transferring the lower-speed-type data with a second speed, the first speed being higher the second speed.