Patent Description:
One or more embodiments may be applied to manufacturing integrated circuits (ICs).

Various technologies are currently available for manufacturing semiconductor devices such as integrated circuits.

Desirable features in that technical field may include reduced assembly cost, possibility of replacing the leadframe with a custom-made substrate, high flexibility in substrate manufacturing, modular configuration for multiple dice, and capability of possibly dispensing with wire bonding.

Document <CIT> discloses a wire bond type semiconductor package comprising a semiconductor chip mounting board and a semiconductor chip mounted thereon. The mounting board and the semiconductor chip are bonded by a die bond film or paste. The semiconductor chip and wire bonding connecting terminals are electrically connected together by a wire bond. The semiconductor chip may be sealed with a semiconductor sealing resin. Solder connecting terminals may have solder balls, for example, mounted thereon for electrical connection with a motherboard. The wire bonding connecting terminals and solder connecting terminals are each formed by a method comprising a step in which an electroless nickel plating film, a first palladium plating film, a second palladium plating film, and a displacement gold plating film are formed in that order on the surface of a conductive layer as part of the wiring. When the core board is a non-photosensitive base, laser light may be used to form the through-holes (IVHs) for the first via holes running through the core board for connection with the wire bonding connecting terminals.

Document <CIT> discloses an electronics package including backside functionality. The package includes a semiconductor device having an active surface and a back surface including one or more backside contact pads. The active surface of the semiconductor device is affixed to a first surface of an insulating substrate in the form of an insulating film or dielectric substrate, such as a Kapton® laminate flex, Ultem®, polytetrafluoroethylene (PTFE), or another polymer film. An insulating structure with at least one tapered or sloped side surface or side wall is coupled to the first surface of the insulating substrate. A functional layer is provided on the back surface of semiconductor device. Alternatively, all of functional layer or select portions thereof may be formed on the outer surface or sloped side wall of the insulating structure, the back surface of the semiconductor device, and/or cover a portion of the first surface of the insulating substrate. Connection lines (electrical lines or communication lines) may be formed on the back surface of the semiconductor device, the sloped side wall of the insulating structure, or the first surface of the insulating substrate. In particular, after forming the insulating structure, the connection lines are formed by applying one or more layers of conductive and/or non-conductive materials on the sloped side walls of the insulating structure, the back surface of the semiconductor device, and exposed regions of the first surface of the insulating substrate. The connection lines can be laser activated and then selectively plated.

Document <CIT> discloses a semiconductor device in which a semiconductor element is connected by wire bonding. The semiconductor element on which the circuitry is not formed is bonded with an adhesive to the surface of a wiring board on which a first electrode is formed, and the electrodes of the semiconductor element and the first electrodes are connected by bonding wires and are covered with a sealing resin.

An object of one or more embodiments is to contribute in providing further improvements along the lines discussed in the foregoing.

According to one or more embodiments, that object may be achieved by means of a method having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding semiconductor device (an integrated circuit, for instance).

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

One or more embodiments provide a method of manufacturing semiconductor devices, such as integrated circuits, comprising providing a leadframe having a core or substrate comprising plastic material and selective surface metallization at the leads area.

The invention comprises providing plastic material suitable for laser direct structuring (LDS) in the plastic core or substrate of the leadframe.

One or more embodiments may thus facilitate replacing a metallic leadframe with a cheaper plastic leadframe, providing improved flexibility of routing to simplify wire bonding inside the body of the package, and providing low cost packages for integrated circuits.

It will be appreciated that, for the sake of clarity and ease of representation, the various Figures may not be drawn to scale and may not be drawn all to the same scale.

Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

Laser Direct Structuring (LDS) is a laser-based machining technique now widely used in various sectors of the industrial and consumer electronics markets, for instance for high-performance antenna integration, where an antenna design can be directly formed onto a molded plastic part.

In an exemplary process, the molded parts can be produced with commercially available resins which include additives suitable for the LDS process. A broad range of resins such as polymer resins like PC, PC/ABS, ABS, LCP are currently available for that purpose.

In LDS, a laser beam can be used to transfer a desired electrically-conductive pattern onto a plastic material which may then be subjected to metallization (for instance via electroless plating with copper or other metals) to finalize a desired conductive pattern. Electroless plating may be followed by an electrolytic deposition of copper or other metals, e.g., to increase the thickness of the conductive pattern to a certain (e.g., defined) value.

One or more embodiments as exemplified herein are based on the recognition that LDS facilitates providing electrically-conductive formations such as vias and lines in a plastic (molding) compound, without additional manufacturing steps and with a high flexibility in the shapes which can be obtained.

One or more embodiments may facilitate providing semiconductor devices which include a leadframe comprising plastic material.

The designation "leadframe" (or "lead frame") is currently used (see, for instance, the Consolidated Glossary of USPC Terms of the United States Patent and Trademark Office) to indicate a metal frame which provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip to other electrical components or contacts.

Essentially, a lead frame comprises an array of electrically-conductive formations (leads) which, from an outline location, extend inwardly in the direction of a semiconductor chip or die thus forming an array of electrically-conductive formations from a die pad configured to have at least one semiconductor chip or die attached thereon.

<FIG> is a cross-sectional view across an integrated circuit <NUM> according to one or more embodiments. The integrated circuit <NUM> comprises a foil <NUM> of plastic (e.g., polymeric) material which provides a core or substrate of a leadframe <NUM>. The plastic material may comprise a material suitable for LDS processing, such as Liquid Crystal Polymers (LCP), polytetrafluoroethylene (PTFE), or a thermo-setting resin (ECN, Biphenyl, DCP, Multi-aromatic).

A (e.g., central) portion <NUM> of the leadframe <NUM> may be configured to host a die or dice <NUM> attached on the leadframe <NUM> via die attach material <NUM>, e.g., an epoxy glue containing silver (Ag) or a film containing silver.

Electrically-conductive formations (i.e., the leads of the leadframe <NUM>) are provided on the plastic foil <NUM> by forming (e.g., plating, for instance via electroless plating possibly followed by electrolytic deposition) metal layers 108a, 108b on selected portions of the plastic foil <NUM>. For instance, a metal layer 108a may be formed on (part of) the front (e.g., top) surface of the foil <NUM>, and/or a metal layer 108b may be formed on (part of) the rear (e.g., bottom) surface of the foil <NUM>.

The metal layer 108a and/or 108b may comprise at least one metal selected out of copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), gold (Au).

The die <NUM> may be electrically coupled to the leads of the leadframe <NUM> by means of bonding wires (or any other type of inter-connections like, for instance, copper bumps or solder bumps) coupling the die pads provided on the front surface 104a of the die <NUM> to electrically-conductive formations provided, e.g., in the metal layer 108a.

The integrated circuit <NUM> may also comprise a package <NUM> comprising, e.g., a molding compound such as epoxy molding compound (EMC) which encapsulates the die <NUM>, the bonding wires and a portion of the leadframe <NUM>.

In one or more embodiments, the thickness of the plastic foil <NUM> may be in the range of about <NUM> to <NUM>.

In one or more embodiments, the thickness of the metal layers 108a, 108b may be in the range of about <NUM> to <NUM>.

For Thin Quad Flat Packages (TQFP), the thickness of the metal layers 108a, 108b may be in the range of about <NUM> mils to <NUM> mils (<NUM> mil = <NUM> in = <NUM>).

The thickness of the plastic foil <NUM> and/or of the metal layers 108a, 108b may be selected so to facilitate correct forming of the integrated circuit <NUM>.

<FIG> are exemplary of possible manufacturing steps in one or more embodiments. In particular, Figures designated with letter "A" are exemplary (top) plan views of subsequent fabrication steps according to embodiments, and Figures designated with letter "B" are respective cross-sectional side views.

As exemplified in <FIG> (top view) and 2B (side view), a (planar) plastic foil <NUM> may be provided as a core or substrate for a plastic leadframe <NUM>. The plastic foil <NUM> may be shaped (e.g., by stamping or punching) to a "leadframe-like" structure having die mounting locations <NUM> surrounded by lead-shaped portions. The plastic foil <NUM> may comprise a material suitable for LDS processing.

As conventional in the fabrication of integrated circuits, in early steps of the fabrication flow the leadframe <NUM> may comprise a plurality of mounting locations <NUM> for a respective plurality of dies <NUM>. The devices may be singulated (prior to or after molding of the molding material <NUM>) by sawing or cutting along the sawing lines <NUM> indicated in <FIG>.

For the sake of clarity and ease of illustration, the following <FIG> illustrate further steps of a manufacturing method according to embodiments with reference to only two adjacent mounting locations <NUM>, i.e., a limited portion of the leadframe <NUM> such as portion <NUM> exemplified in <FIG>.

As exemplified in <FIG> (top view) and 3B (side view), the LDS-activatable material of the plastic foil <NUM> may be selectively activated by scanning laser radiation on the lead areas <NUM> of the leadframe <NUM>. Laser radiation may be scanned on the front side and/or on the rear side of the foil <NUM>, thereby providing laser-activated regions 100a and/or 100b, respectively, corresponding to the lead areas <NUM>. The laser-activated regions 100a and/or 100b may extend for about <NUM> to <NUM> in thickness from the surface(s) of the foil <NUM>.

Once the selected areas <NUM> of the plastic leadframe <NUM> have been laser-activated, the selected areas <NUM> may be covered with a metallic layer (e.g., by electroless plating) as exemplified in <FIG> (top view) and 4B (side view) to provide the metal layers 108a and/or 108b.

Alternatively, the laser-activated regions 100a, 100b may provide sufficient electrical conductivity and may not involve a surface metallization 108a, 108b.

It will be appreciated that, in one or more embodiments, the plastic foil <NUM> may not be stamped or punched to provide physically separated lead areas <NUM>, insofar as the leads may be electrically insulated one from the other by properly selecting the areas of the plastic foil <NUM> to be laser-activated and/or covered with metal.

Once the metal layers 108a and/or 108b are formed on the lead areas <NUM>, the fabrication flow of the integrated circuit <NUM> may comprise conventional steps such as attaching dies <NUM> at the respective die mounting locations <NUM> (e.g., by means of soft-solder attach material) and wiring the die pads of the dies <NUM> to the respective leads provided on the plastic leadframe <NUM> (e.g., the metallic formations 108a), as exemplified in <FIG> (top view) and 5B (side view).

As exemplified in <FIG> (top view) and 6B (side view), a molding compound <NUM> (e.g., epoxy molding compound, EMC) may be provided to encapsulate the dies <NUM> attached to the leadframe <NUM> prior to or after a singulation step of the devices <NUM> (e.g., sawing along lines <NUM>).

In one or more embodiments, after molding of the packages <NUM>, the leadframe <NUM> may be further plated with an additional layer of metal (e.g., tin), trimmed, and formed (with such steps not visible in the Figures annexed herein).

In one or more embodiments as exemplified in <FIG>, the lead areas <NUM> may be selected so as to reduce the complexity of wire bonding, e.g., by reducing (e.g., minimizing) the length of the bonding wires coupling the die pads to the leads, with such an improvement being facilitated by the flexibility of the LDS technique (or, in variant embodiments, of the masking technique) for patterning the lead areas <NUM>.

In one or more embodiments as exemplified in <FIG>, the metal layers 108a, 108b may be provided also at the die pad area (or mounting location <NUM>), e.g., by laser-activating those areas during the laser activation step exemplified in <FIG>. The top metal layer 108a and the bottom metal layer 108b provided at the mounting locations <NUM> may be thermally coupled by fabricating one or more thermal vias <NUM> which extend through the thickness of the plastic foil <NUM>, with such thermal vias possibly fabricated by laser direct structuring.

Alternatively, as exemplified in <FIG>, the plastic foil <NUM> may be selectively removed at the mounting locations <NUM> to improve thermal dissipation from the die <NUM> during operation. For instance, a method according to embodiments may comprise:.

One or more embodiments may thus offer one or more of the following advantages:.

As exemplified herein, a method of manufacturing semiconductor devices (e.g., <NUM>) may comprise:.

As exemplified herein, said plastic material substrate may comprise laser direct structuring material, and forming metallic traces on selected areas of said plastic material substrate may comprise laser activating said laser direct structuring material.

As exemplified herein, a method may comprise applying laser radiation energy to said laser direct structuring material at said selected areas of said plastic material substrate to provide activated regions of said plastic material substrate, and plating (e.g., by electroless plating) electrically-conductive material onto said activated regions of said plastic material substrate.

As exemplified herein, a method may comprise selectively forming said metallic traces on said selected areas of said plastic material substrate by applying a masking layer on said plastic material substrate.

As exemplified herein, a method may comprise providing (e.g., plating) a further metallic layer on portions of said selected areas left exposed by said package material, wherein said further metallic layer preferably comprises tin.

As exemplified herein, a method may comprise forming (e.g., plating) metallic areas (e.g., 108a, 108b) at said at least one die mounting location of said plastic material substrate prior to attaching onto said at least one die mounting location said respective at least one semiconductor die.

As exemplified herein, a method may comprise:.

As exemplified herein, a method may comprise selectively removing said plastic material substrate at said at least one die mounting location prior to attaching onto said at least one die mounting location said respective at least one semiconductor die.

As exemplified herein, a thickness of said plastic material substrate may be in the range of <NUM> to <NUM>.

As exemplified herein, a thickness of said metallic traces may be in the range of <NUM> to <NUM>.

As exemplified herein, a semiconductor device may comprise:.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

Claim 1:
A method of manufacturing semiconductor devices (<NUM>), the method comprising:
- providing a plastic material substrate (<NUM>) having at least one die mounting location (<NUM>) for a semiconductor die (<NUM>), wherein said plastic material substrate (<NUM>) comprises laser direct structuring material,
- forming metallic traces (108a, 108b) on selected areas (<NUM>) of said plastic material substrate (<NUM>), wherein said metallic traces (108a, 108b) provide electrically-conductive paths for coupling to said semiconductor die (<NUM>), and wherein forming said metallic traces (108a, 108b) on selected areas (<NUM>) of said plastic material substrate (<NUM>) comprises laser activating said laser direct structuring material,
- attaching said semiconductor die (<NUM>) onto said at least one die mounting location (<NUM>),
- bonding said semiconductor die (<NUM>) attached onto said at least one die mounting location (<NUM>) to selected ones of said metallic traces (108a, 108b) formed on the plastic material substrate (<NUM>),
- molding package material (<NUM>) onto said semiconductor die (<NUM>) attached onto said at least one die mounting location (<NUM>).