Patent Description:
For an integrated circuit electrostatic discharge (hereinafter abbreviated ESD) structure <NUM> as shown in <FIG>, I/O (input/output) pads <NUM> are placed around a circuit area <NUM> inside a plurality of chip edges <NUM> based on particular sequence and position, wherein the placement of the I/O pads <NUM> is adjustable within a specific range.

In general, it is commonly to place filler cells F1 and F2 at empty spaces between the I/O pads <NUM>, and connect the filler cells F1 and F2 to an electrostatic discharge (ESD) bus <NUM> (e.g., a layout trace connected to a ground or a system voltage), which makes each portion of the circuit area <NUM> and the filler cells F1 and F2 are connected to the continuous ESD bus to provide ESD protection to the integrated circuit ESD bus structure <NUM>.

However, the filler cells F1 and F2 take a portion of the circuit area <NUM> to be wasteful to the integrated circuit ESD bus structure <NUM>. Further, under the strict requirement of the integrated circuit ESD bus structure <NUM> having a rectangular shape, it causes the lack of flexibility for internal circuit layout design.

Further, when there are circuits with irregular shapes and different areas, the circuit area <NUM> must be increased in order to contain the circuits with irregular shapes and different areas, which increases production cost. The <CIT> describes an integrated circuit device in which portion of the interconnect lines are replaced by bonding wires. The <CIT> describes a semiconductor device with improved resistance to electrostatic discharge noise. The <CIT> describes a transient voltage suppressing integrated circuit. The <CIT> describes a semiconductor integrated circuit device with enhanced protection from electrostatic breakdown. The <CIT> describes an electrostatic discharge protection circuit. The <CIT> describes an integrated circuit with improved electrostatic discharge protection including multi-level inductor. The <CIT> describes an apparatus for electrostatic discharge protection and noise suppression in circuits. The <CIT> describes ESD bus lines in CMOS integrated circuits for whole-chip ESD protection.

Accordingly, it is desirable to provide an integrated circuit ESD bus structure and related method to make full use of the circuit area.

It is therefore an objective of the present invention to provide an integrated circuit electrostatic discharge bus structure and related method.

To achieve the above technical object, according to the present invention, an integrated circuit electrostatic according to claim <NUM> is provided.

To achieve the above technical object, according to the present invention, a method according to claim <NUM> is provided.

<FIG> is a schematic diagram of an integrated circuit electrostatic discharge (ESD) structure <NUM> according to an embodiment of the present invention. The integrated circuit ESD bus structure <NUM> includes a circuit area <NUM>, a plurality of ESD buses E1, E2 and E3, a plurality of pad groups G1, G2 and G3, a common ESD bus <NUM>, and a plurality of bonding wires <NUM>.

The circuit area <NUM> is formed by a plurality of chip edges <NUM>; for example, the four chip edges <NUM> forms a rectangular area configured to contain the circuit area <NUM>. The circuit area <NUM> includes a plurality of discontinuous boundaries B1, B2 and B3. The plurality of ESD buses E1, E2 and E3 is formed inside the chip edges <NUM>, corresponding and adjacent to the plurality of discontinuous boundaries B1, B2, and B3.

The plurality of pad groups G1, G2 and G3 is formed inside the chip edges <NUM>, adjacent and connected to the plurality of ESD buses E1, E2 and E3. The common ESD bus <NUM> is formed outside the chip edges <NUM>, which is not limited. The common ESD bus <NUM> may not be formed in one piece, and include a plurality of discontinuous ESD bus groups. The plurality of bonding wires <NUM> is formed across the chip edges <NUM>, and configured to connect the plurality of pad groups B1, B2 and B3 to the common ESD bus <NUM>. In one embodiment, the common ESD bus <NUM> is parallel to the plurality of ESD buses E1, E2 and E3 and the plurality of pad groups G1, G2 and G3.

Each of the plurality of pad groups G1, G2 and G3 includes at least one pad <NUM>, wherein the pad <NUM> is an input/output pad connected to a ground or a system low voltage. At least one of the plurality of bonding wires <NUM> is configured to connect the at least one pad <NUM> to the common ESD bus <NUM>. In one embodiment, multiple bonding wires <NUM> may be configured to connect multiple pads <NUM> of the pad group G1 to the common ESD bus <NUM>, which provides multiple connections to enhance conductivity between the pad group G1 and the common ESD bus <NUM> to improve ESD protection.

In such a structure, the discontinuous ESD buses E1, E2 and E3 may be connected together by connecting the pads <NUM> of the pad groups G1, G2 and G3 to the common ESD bus <NUM> through the bonding wires <NUM>, which equivalently forms a continuous ESD bus for the integrated circuit ESD bus structure <NUM>. As a result, the present invention may get rid of the filler cells of the prior art. In addition, spaces between the discontinuous ESD buses E1 and E2 (or, E2 and E3) may be configured with circuit elements to make full use of the integrated circuit ESD bus structure <NUM>.

For example, the ESD bus <NUM> and the filler cells F1 and F2 shown in <FIG> are replaced by saved areas SA1 and SA2 in <FIG>. The saved area SA1 is adjacent to the ESD buses E1 and E2 and the pads <NUM> of the pad groups G1 and G2. The saved area SA2 is adjacent to the ESD buses E2 and E3 and the pads <NUM> of the pad groups G2 and G3. In one embodiment, the common ESD bus <NUM> is formed inside the chip edges <NUM>, and adjacent to the plurality of pad groups G1, G2 and G3 and the saved areas SA1 and SA2.

<FIG> is a schematic diagram of an integrated circuit ESD bus structure <NUM> according to an embodiment of the present invention. The integrated circuit ESD bus structure <NUM> includes a circuit area <NUM>, a plurality of ESD buses E1, E2 and E3, a plurality of pad groups G1, G2 and G3, and a plurality of bonding wires <NUM>.

The circuit area <NUM> is formed by a plurality of chip edges <NUM>; for example, the four chip edges <NUM> form a rectangular area to contain the circuit area <NUM>. The circuit area <NUM> includes a plurality of discontinuous boundaries B1, B2 and B3. The plurality of ESD buses E1, E2 and E3 is formed inside the chip edges <NUM>, corresponding and adjacent to the plurality of discontinuous boundaries B1, B2, and B3.

The plurality of discontinuous ESD buses E1, E2 and E3 is formed inside the chip edges <NUM>, and adjacent to the plurality of discontinuous boundaries B1, B2, and B3. The plurality of pad groups G1, G2, and G3 is formed inside the chip edges <NUM>, adjacent and connected to the plurality of ESD buses E1, E2 and E3. The plurality of bonding wires <NUM> is formed across the circuit area <NUM>, and configured to connect the plurality of pad groups G1, G2, and G3 from one group to another group, e.g., one bonding wire <NUM> may connect the pad group G1 to the pad group G2, and another bonding wire <NUM> may connect the pad group G2 to the pad group G3.

Each of the plurality of pad groups G1, G2 and G3 includes a plurality of pads <NUM>, wherein the pad <NUM> is an input/output pad connected to a ground or a system low voltage. The plurality of bonding wires <NUM> is configured to connect the pads <NUM> of one group to another group. Each of the plurality of pad groups G1, G2 and G3 comprises a connecting pad (e.g., a right most pad of the pad group G1, left and right most pads of the pad group G2, and a left most pad of the pad group G3), and the plurality of bonding wires <NUM> are configured to connect the connecting pad of one of the plurality of pad groups to the connecting pad of another of the plurality of pad groups. For example, one of the bonding wires <NUM> is configured to connect the right most pad <NUM> of the pad group G1 to the left most pad <NUM> of the pad group G2, and one of the bonding wires <NUM> is configured to connect the right most pad <NUM> of the pad group G2 to the left most pad <NUM> of the pad group G3, which is not limited.

In such a structure, the discontinuous ESD buses E1, E2 and E3 may be connected together by connecting the pads <NUM> of the pad groups G1, G2 and G3 from one group to another group, which equivalently forms a continuous ESD bus for the integrated circuit ESD bus structure <NUM>. As a result, the present invention may get rid of the filler cells of the prior art. In addition, spaces between the discontinuous ESD buses E1 and E2 (or, E2 and E3) may be configured with circuit elements to make full use of the integrated circuit ESD bus structure <NUM>. For example, the ESD bus <NUM> and the filler cells F1 and F2 shown in <FIG> are replaced by saved areas SA1 and SA2 in <FIG>, and thus the circuit area <NUM> may contain the circuits with irregular shapes and different areas without increasing its area, which saves production cost.

<FIG> is a flowchart of an integrated circuit ESD bus structure process <NUM> according to an embodiment of the present invention.

Step <NUM>: Form a plurality of pad groups corresponding to a plurality of discontinuous boundaries of the circuit area inside a plurality of chip edges.

Step <NUM>: Form a common ESD bus outside the plurality of chip edges.

Step <NUM>: Connect a plurality of pads corresponding to the plurality of pad groups to the common ESD bus by a plurality of bonding wires across the plurality of chip edges.

In Step <NUM>, a circuit area is formed; in step <NUM>, a plurality of pad groups corresponding to a plurality of discontinuous boundaries of a circuit area inside a plurality of chip edges is formed; in step <NUM>, a common ESD bus outside the plurality of chip edges is formed; and in step <NUM>, a plurality of pads corresponding to the plurality of pad groups is connected to the common ESD bus by a plurality of bonding wires across the plurality of chip edges. By the integrated circuit ESD bus structure process <NUM>, a continuous ESD bus may be equivalently formed and the filler cells of the prior art may be omitted.

Step <NUM>: Connect one and another of the plurality of pad groups by a plurality of bonding wires across the circuit area inside the plurality of chip edges.

In Step <NUM>, a circuit area is formed; in step <NUM>, a plurality of pad groups corresponding to a plurality of discontinuous boundaries of a circuit area inside a plurality of chip edges is formed; and in step <NUM>, one and another of the plurality of pad groups are connected together by a plurality of bonding wires across the circuit area inside the plurality of chip edges. By the integrated circuit ESD bus structure process <NUM>, a continuous ESD bus may be equivalently formed and the filler cells of the prior art may be omitted.

To sum up, the present invention utilizes bonding wires to connect a plurality of pads of a plurality of pad groups, so as to equivalently form a continuous ESD bus. As a result, the present invention may get rid of the filler cells of the prior art. In addition, spaces between the discontinuous ESD buses may be configured with circuit elements to make full use of the integrated circuit ESD bus structure.

Claim 1:
An integrated circuit structure, comprising:
a circuit area;
ESD buses; and
pad groups connected to the ESD buses;
wherein the circuit area comprises at least one first area, each of the first area (SA1, SA2) is adjacent to two ESD buses of the ESD buses and two pad groups of the pad groups;
wherein one of the two pad groups of the pad groups is connected to the other of two pad groups of the pad groups via a bonding wire;
wherein each of the two pad groups of the pad groups comprises a connecting pad, and the connecting pad of one of the two pad groups is connected to the connecting pad of the other of the two pad groups via the bonding wires.