Patent Description:
Circuits and methods of driving Laser Diodes (LD) such as vertical cavity surface emitting laser (VCSEL) diodes are known.

An issue with conventional current drivers and laser diode technologies is one of driving current to the laser diode and the inductance produced by the connections between the driver circuitry and the laser diode.

Laser diode driver circuit modules (and other circuit modules such as time of flight determination modules) are typically mounted as dies on a sub-mount away from the laser diode die. This is done in order to physically, optically and electrically isolate the laser diode as far as possible from the other circuitry. Furthermore this allows the production of the laser diode to be fabricated using a first process technology and the driver circuitry and other circuitry using a second process technology, where each process technology is optimised for the module.

Connections between modules are then formed by the use of contact pads and bonding wires. These contact pads and bonding wires form parasitic inductances which are significant with respect to the currents (<NUM>-<NUM> A) and pulse widths (<NUM>-<NUM> ns with 1ns rise time) used for example in time of flight range detecting applications.

<CIT> describes a driver circuit for a laser diode where a first inductor and first capacitor are connected to the anode of the laser diode, and a second inductor and second capacitor are connected to the cathode of the laser diode, where the inductance of the first and second inductor is equal, and the capacitance of the first and second capacitor is equal.

According to a first aspect, there is provided a laser diode driver circuit according to claim <NUM>.

According to a second aspect there is provided a method according to claim <NUM>.

According to a third aspect there is provided an apparatus comprising a laser diode driver circuit according to the first aspect and a laser diode.

Some embodiments will now be described by way of example only and with reference to the accompanying Figures in which:.

The concept as embodied herein is shown by apparatus and methods for controlling laser diode driver currents.

As discussed previously for Time of Flight (TOF) range or distance determination applications a modulated optical signal is employed as a transmission signal for ranging.

A pulse train offers the advantage of a higher modulation contrast versus a sinusoid and can produce better signal to noise ratios. Furthermore a pulse signal with less than <NUM>% duty cycle presents suitable power efficiency advantages versus a sinusoid. For example a Root Mean Squared (RMS) current (IDC = Ipeak/sqrt(<NUM>)) of a sinusoid versus a Pulse Width Modulated (PWM) current operating at <NUM>% duty cycle (IDC = Ipeak*<NUM>).

The modulation frequency of the TOF transmission signal also affects the ranging accuracy, expressed as a standard deviation (i.e. ranging distance error) from the ideal distance. This standard deviation is known in the art to relate inversely proportional to the modulation frequency. In other words an increasing frequency transmission signal reduces the ranging error. It is hence beneficial to increase the operation frequency of the transmit signal.

In Direct TOF (DTOF) implementations, a receiver can be configured to generate a Time Correlated Single Photon Counting (TCSPC) histogram which is builds up an image of a return pulse, in other words the time of flight of light, integrating the photon counts over time.

In a pulse train transmission signal system, it is beneficial to maintain a pulse width of low duty cycle, to be able to resolve multiple targets (in other words to be able to receive return pulses from both near and far targets without the return pulses overlapping) within region of interest (ROI). This as well produces the power efficiency gain highlighted above. In an idealised scenario, the transmission pulse would resemble an impulse.

The generation of the optical transmission pulse train may be performed by an electrical current pulse train directly modulating a VCSEL (or suitable solid-state LASER). The electrical current pulse being designed such that it has a high peak-to-trough modulation contrast ratio, a minimum pulse width to maximise power efficiency, and a high frequency of modulation for increasing the resolution of ranging and hence reducing the standard deviation of error.

It is known that the voltage across an inductor equals the value of its inductance multiplied by the step change in current through the inductor (VL = L. It can be observed that any inductance in series to the driven path of a TOF system described above would impede its operation with respect to attempting to achieve the best performance as the inductance would potentially limit peak-to-trough modulation contrast ratio, minimum pulse width, and highest frequency of modulation.

As mentioned previously the sensor/controller module and laser module (or dies) may be connected using wire-bonding. An example of which is shown in <FIG> which shows the sub-mount <NUM> on which there is mounted a sensor/laser diode driver module <NUM> and a laser diode module <NUM>. The sensor/laser diode driver module <NUM> is connected a contact pad <NUM>. The contact pad <NUM> is connected to a further contact pad <NUM> by a wire-bonding <NUM>. The further contact pad <NUM> is connected to the laser diode module <NUM>. Furthermore electrical routing may also traverse via a wire-bonding to an electrical trace on the sub-mount, where the inductive contribution from both is summed to form the effective inductance.

The approximate inductance of a <NUM> (1mil) diameter gold wire-bonding is 1nH per millimetre. This parasitic inductance cannot be eliminated.

As discussed above this parasitic inductance has the effect of limiting substantially instantaneous switching of current. This can be seen as shown in the <FIG> based on an inductor analogy example from https://ece. ca/~dwharder/Analogy/Inductors/ to be analogous to the effect of a water wheel impeding the immediate change of flow of water in a system. For example as shown in on the left hand side of <FIG> a motor <NUM> which is connected to a pump <NUM> attempts to change the flow of water (shown by arrow <NUM>) in a system <NUM>. However the system furthermore comprises a water wheel <NUM> which is analogous to the inductor such as the 'connection' or parasitic inductor. When the motor <NUM> attempts to generate a pulse and pump water through the system (the laser diode current driver attempting to generate an electrical pulse) the waterwheel <NUM>, which is initially static, slows the change of the flow until the wheel is turning at the speed of the pump <NUM> (in a manner similar that the current driven by the current driver is impeded until the inductor current is the same as the driver current).

The concept as discussed in further detail by the embodiments hereafter is for a laser diode (LD) driver design which is able to utilise this 'connection' inductance and by utilising the inductance to enable a good contrast ratio, power efficiency, and resolution and reduced ranging error. This is shown analogously on the right hand side of <FIG> where the motor <NUM> which is connected to a pump <NUM> and which attempts to change the flow of water (shown by arrow <NUM>) in a system <NUM>. In this example the system furthermore comprises a water wheel <NUM> which is analogous to the 'connection' or parasitic inductor. In this example the water wheel <NUM> is already spinning at the desired flow rate before the motor <NUM> attempts to generate a pulse and pump water through the system (the laser diode current driver attempting to generate an electrical pulse) and thus the waterwheel <NUM>, does not slow the change of the flow. In other words in the embodiments as described hereafter the inductor is configured such that it is 'pre-charged' with a current that is the same as the current driven by the current driver before the current pulse is provided to the laser diode.

An example conventional laser diode and driver configuration is shown in the circuit diagram shown in <FIG>.

<FIG> shows the diode <NUM> which is coupled at an anode node via a first wire-bonding <NUM> (which operates as a first inductor) and a pad <NUM> to a first switching element <NUM> suitable for switching on a positive (or high) supply voltage. Furthermore the diode <NUM> is coupled at a cathode node via a second wire bonding <NUM> (which operates as a second inductor) and a second pad to a second switching element <NUM> which may switch to a negative (or low) supply voltage and via a current source.

The effect of the inductors can be shown by the graphs shown in <FIG>. The first graph <NUM> indicating the voltage across the pads formed by switching on the first switching element <NUM> and second switching element <NUM> to generate a control pulse.

The second graph <NUM> shows the current through the first wire bonding <NUM>, the second graph <NUM> shows the current through the second wire bonding <NUM> and the third graph <NUM> shows the current through the laser diode <NUM>. All three show the same effect of the inductors slowing the rate of change of the current such that the peak current shown at time <NUM> occurs significantly after the switching on of the control pulse.

With respect to <FIG> is shown an overview summary of a schematic view according to the invention. The diode <NUM> is coupled at an anode node via a first anode wire-bonding <NUM> (which operates as a first inductor) and a pad <NUM> to a first anode switching element <NUM> suitable for switching on a positive (or high) supply voltage.

The diode <NUM> is furthermore coupled at an anode node via a second anode wire-bonding <NUM> (which operates as a second inductor) and a pad <NUM> to a second anode switching element <NUM>.

In the following embodiments the first inductor and the second inductor are matched. This for example may be achieved by the wire-bondings being the same for the first anode wire-bonding <NUM> and the second anode wire-bonding <NUM>.

Furthermore the diode <NUM> is coupled at a cathode node via a first cathode wire bonding <NUM> (which operates as a third inductor) and a pad <NUM> to a first cathode switching element <NUM>.

Also the diode <NUM> is coupled at a cathode node via a second cathode wire bonding <NUM> (which operates as a fourth inductor) and a pad <NUM> to a second cathode switching element <NUM> which may for example switch to a negative (or low) supply voltage and via a current source.

In the following embodiments the third inductor and the fourth inductor are matched. This for example may be achieved by the wire-bondings being the same for the first cathode wire-bonding <NUM> and the second cathode wire-bonding <NUM>.

Thus although in the embodiments shown herein wire bonding or inductance <NUM> = <NUM>, and wire bonding or inductance <NUM> = <NUM> it is not necessary for a sum of inductance <NUM>+<NUM> to equal <NUM>+<NUM>.

The signalling path (both forward and return) in the embodiments as described herein may be implemented as two pairs of wires, with a switching sequence broken down into three distinct stages.

The three distinct stages are shown in <FIG>.

<FIG> shows schematically the first phase, a pre-biasing inductance phase. In this example the first anode switching element is shown comprising a pmos transistor <NUM> configured to couple the pad <NUM> to a positive (or high) supply voltage Vdd. The pmos transistor <NUM> may be controlled by a safety signal.

The second anode switching element is shown comprising a nmos transistor <NUM> configured to couple the pad <NUM> to a current source <NUM> which in turn is coupled to a negative (or low) supply voltage.

The first cathode switching element is shown comprising a nmos transistor <NUM> configured to couple the pad <NUM> to a positive (or high) supply voltage Vdd. The nmos transistor <NUM> may also be controlled by the safety signal.

The second cathode switching element is shown coupling the pad <NUM> to a further current source <NUM> which in turn is coupled to a negative (or low) supply voltage.

In such a manner due to the symmetry in the anode and cathode supplies there is no potential difference across the diode, in other words the voltage at the node <NUM> is the same as the voltage at the node <NUM>.

Furthermore a first pre-bias current Iprebias starting from <NUM> to a value Ivcsel flows from the positive (or high) supply voltage Vdd via the anode to the negative supply voltage and a second pre-bias current Iprebias starting from <NUM> to a value Ivcsel flows from the positive (or high) supply voltage Vdd via the cathode to the negative supply voltage.

These currents are shown in <FIG> by a graph <NUM> of current against time for the first inductor <NUM> showing the current rising linearly from <NUM> to Ivcsel based on the inductance of the inductor L00, a graph <NUM> of current against time for the second inductor <NUM> showing the current rising linearly from <NUM> to Ivcsel based on the inductance of the inductor L01, a graph <NUM> of current against time for the third inductor <NUM> showing the current rising linearly from <NUM> to Ivcsel based on the inductance of the inductor L02, and a graph <NUM> of current against time for the fourth inductor <NUM> showing the current rising linearly from <NUM> to Ivcsel based on the inductance of the inductor L03. Furthermore is shown the lack of current though the laser diode in the graph <NUM>.

In other words in the first phase, inductance pre-biasing current sources, set at the same magnitude as the peak lasing current, present a direct current loop back. The pair of anode pads <NUM> AN00 and <NUM> AN01 form an anode loop back path <NUM>, where the pad <NUM> AN00 conveys the forward current path and pad <NUM> AN01 receives the return current path. Similarly pads <NUM> KA00 (return path) and <NUM> KA01 (forward path), form a cathode loop back path.

As described above the path inductances (e.g. inductors <NUM> L00 and <NUM> L01) forming a loop back current <NUM> are configured to be substantially identical (i.e. inductance L00 + L01 = L00*<NUM> = L01*<NUM>). Similarly the same limitation applies to the cathode loop back path inductors. However it is understood that the inductors <NUM> and <NUM> may not be equal to inductors <NUM> and <NUM>.

In some embodiments where L00 + L01 is not equal L02 + L03 (or with tolerance mismatch), a non - lasing condition can still be met where the voltage across the laser diode (VCSEL) is less than its turn on voltage.

<FIG> shows schematically the second phase, a laser diode turn on phase. In this example the first anode switching element is shown comprising the pmos transistor <NUM> configured to couple the pad <NUM> to the positive (or high) supply voltage Vdd. The pmos transistor <NUM> may be controlled by the safety signal.

The second anode switching element is shown being configured to couple the pad <NUM> via a diode <NUM> to a positive (or high) supply voltage.

The first cathode switching element is shown configured to couple the pad <NUM> via a diode <NUM> to a negative (or low) supply voltage.

The second cathode switching element is shown coupling the pad <NUM> to the further current source <NUM> which in turn is coupled to a negative (or low) supply voltage.

In such a manner the pre-charged currents are such that for the second phase the diode current Ivcsel <NUM>, <NUM> can pass via inductor <NUM> and through the diode <NUM> and inductor <NUM>. Also the pre-charged currents for the inductor <NUM> and inductor <NUM> can be shunted via the diodes <NUM> and <NUM> respectively.

Thus in the second phase, as the current through inductor <NUM> L00 (and thus inductor L01 <NUM>) and inductor <NUM> L02 (and thus inductor <NUM> L03) reach the same magnitude as the peak lasing current, the pre-biasing current source terminates, whilst the residual pre-bias current that had built up in inductors <NUM> L01 and <NUM> L02 decays through their respective shunting paths.

The current flowing through inductor <NUM> L00 and <NUM> L03 thus enters steady-state (i.e. di/dt = <NUM>) and the voltage across L00 and L03 is zero volt (i.e. a voltage short) when the turn-on phase is started thus in effect cancelling out the inductance that was present in series to the pulsed current.

These currents are shown in <FIG> by a graph <NUM> of current against time for the first inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias being in the steady-state region, a graph <NUM> of current against time for the second inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias then being shunted back to zero in the second phase, a graph <NUM> of current against time for the third inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias then being shunted back to zero in the second phase, and a graph <NUM> of current against time for the fourth inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias and being in the steady-state region in the second phase. Furthermore is shown in the graph <NUM> the current pulse through the laser diode in the second phase.

Thus, it is demonstrated, in using this scheme, the turn on di/dt is improved upon the prior art.

<FIG> shows schematically the third phase, a laser diode turn off phase. In this example the first anode switching element is shown comprising the pmos transistor <NUM> configured to couple the pad <NUM> to the positive (or high) supply voltage Vdd. The pmos transistor <NUM> may be controlled by the safety signal.

The second anode switching element is shown being configured to couple the pad <NUM> to a floating node (i.e. operating as a high impedance node).

The first cathode switching element is shown configured to couple the pad <NUM> to a floating node (i.e. operating as a high impedance node).

The second cathode switching element is shown comprising a (snubber) pmos transistor <NUM> configured to couple the pad <NUM> to the positive (or high) supply voltage Vdd. The (snubber) pmos transistor <NUM> may be controlled by a snubber signal.

The snubber transistor allows a shunting of the current Ivcsel. The turn off termination of the pulsed current, with the clamping path via the snubber switch can be applied dissipating the residual current shown as current <NUM> and <NUM> within inductors <NUM> L00 and <NUM> L03 and clamps the laser diode (VCSEL) anode and cathode as a short circuit.

In such a manner it can be seen that the turn off di/dt would be limited by the combined inductance of inductors <NUM> L00 and <NUM> L03.

These currents are shown in <FIG> by a graph <NUM> of current against time for the first inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias then being in the steady-state region and then in the third phase dissipating quickly. The graph <NUM> of current against time for the second inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias in the first phase then being shunted back to zero in the second phase and remaining zero in the third phase. The graph <NUM> of current against time for the third inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias in the first phase, then being shunted back to zero in the second phase and remaining zero in the third phase. The graph <NUM> of current against time for the fourth inductor <NUM> showing the current having risen linearly from <NUM> to Iprebias in the first phase, being in the steady-state region in the second phase and then dissipating in the third phase. Furthermore is shown in the graph <NUM> the current pulse dissipating through the laser diode in the third phase.

The timing between the first phase and second phase, sets up an inductance pre-biasing current. This current di/dt is relative to the inductance value (in other words of the signal path), required peak pulsed current and available driving DC supply voltage source (in other words across the high supply voltage VDD and low supply voltage GND).

For example for a total path inductance of 2nH, with a voltage source of <NUM>. 6V, and peak pulsed current 320mA, the time duration at which a pre-biasing is applied is <NUM>. 8ps (V = L. di/dt, V=<NUM>, L=2e-<NUM>, di=320e-<NUM>).

For a pulse width, the transmission bandwidth (BW) for a pulse signal of minimum pulse width (PW) equal to the pulse rise time, (Tr) + fall time (Tf), is approximated as BW = <NUM> / (Tr + Tf), or <NUM>/PW. This is an interpretation from the Fourier transform of a rectangular function in a time domain to a sinc function in a frequency domain.

In some embodiments the generation of timing pulses can be designed for the generation of inductance pre-biasing current. In these embodiments a timing generator is utilised to encode this timing information using a series of phase differences between four digital signals of <NUM>% duty cycle.

This set of digital signals in some embodiments can have an equal repetition rate (but different phases) equal to that of the pulsing frequency of the system operation.

For example <FIG> shows example timing generation signals.

The first signal is a <NUM>% duty cycle square wave with Tphase=<NUM> defined as VCSEL_ON_AN_N_GO1 signal <NUM>.

The second signal is a further <NUM>% duty cycle square wave but with a Tphase=125ps defined as VCSEL_ON_KA_N_GO1 signal <NUM>.

The third signal is also a <NUM>% duty cycle square wave but with a Tphase=250ps defined as VCSEL_ON_START_N_GO1 signal <NUM>.

A fourth signal is also a <NUM>% duty cycle square wave but with a Tphase=250ps+Tperiod/<NUM> defined as VCSEL_ON_STOP_GO1 signal <NUM>.

The signals defined with a 'N' (VCSEL_ON_AN_N_GO1 signal <NUM>, VCSEL_ON_KA_N_GO1 signal <NUM> and VCSEL_ON_START_N_GO1 signal <NUM>) have phase or timing information encoded on a falling or negative edge and the signals without (VCSEL_ON_STOP_GO1 signal <NUM>) encoded on a rising or positive edge.

Thus as shown on the lower part timing diagram of <FIG>, the encoded pulse information is shown by the shaded area.

Thus the time and duration of the anode inductance prebiasing (defined as AN IND prebiasing region <NUM>) is shown in <FIG> by the difference between the falling edges of the first (VCSEL_ON_AN_N_GO1) signal <NUM> and the third (VCSEL_ON_START_N_GO1) signal <NUM>.

The time and duration of the cathode inductance prebiasing (defined as KA IND prebiasing region <NUM>) is shown in <FIG> by the difference between the falling edges of the second (VCSEL_ON_KA_N_GO1) signal <NUM> and the third (VCSEL_ON_START_N_GO1) signal <NUM>.

Also the time and duration of the laser diode on period (defined as VCSEL optical pulse region <NUM>) is shown in <FIG> by the difference between the falling edge of the third (VCSEL_ON_START_N_GO1) signal <NUM> and the rising edge of the fourth (VCSEL_ON_STOP_GO1) signal <NUM>.

The timing signal distribution apparatus in some embodiments may be shown in <FIG>. The timing generator <NUM> configured to generate the first to fourth timing signals <NUM>, <NUM>, <NUM>, and <NUM> are then configured to pass these to a clock tree <NUM> which then output the signals to level shifters <NUM> for each channel (in the example shown in <FIG> there are shown a first channel level shifter <NUM><NUM>, a second channel level shifter <NUM><NUM>, a third channel level shifter <NUM><NUM>, and a 512th channel level shifter <NUM><NUM>,.

To maintain fidelity of phase information over large spatial layout on a die, for example an implementation of an integrated driver with multiple output channels the apparatus uses pairs of pad, for forward and return paths, double the spatial need required with the extra pads (i.e. the contrast between the example shown in <FIG> versus the example shown in <FIG>), and the encoded phase information can be distributed via high BW, small geometry CMOS logic (using process GO1, e.g. <NUM> logic), using the clock tree, to equalise the transmission delay (i.e. intrinsic delay of the repeater logic and interconnect RC, which may be represented using Elmore delay model).

In some embodiments is possible to remove any restrictions of how or where the source of this phase information is controlled, programmed, derived, thus encoded, where it can be digitally synthesised with Register Transfer Level (RTL) design abstraction and placed in proximity to the Phase Lock Loop (PLL) synthesising the system operating frequencies and/or generating the required relative phase resolution.

Furthermore in some embodiments by using small geometry logic at this stage also significantly reduces the dynamic power consumption, as represented by P = C. V^<NUM>, for C = total switching CMOS gate capacitance, f = switching frequency, V = supply voltage of logic.

The level shifter converts the clock tree GO1 logic level to the output driving GO2 level. In other words to bias (or pulse) a VCSEL in excess of its forward biasing turn on voltage (Vf, e.g. for <NUM> GaAs diode is approximately <NUM> ~ <NUM>. 5V at room temperature), it requires higher voltage tolerant devices (GO2), in which case, at the terminating branch of the clock tree signals (i.e. logic level), high speed voltage level shifting is performed to interface GO2 devices. With the BW limitation of GO2 devices, these level-shifters are placed within close proximity to the driving output stages, and specifically designed to ensure the level shifted GO2 signal with pass-through GO1 signal remaining synchronised. Thus is shown in <FIG> by the generated signals VCSEL_ON_AN_N_GO1 <NUM>, VCSEL_ON_KA_N_GO1 <NUM>, VCSEL_ON_START_N_GO1 <NUM>, and VCSEL_ON_STOP_GO1 <NUM> and their GO2 level shifted associated signals VCSEL_ON_AN_N_GO2 <NUM>, VCSEL_ON_KA_N_GO2 <NUM>, VCSEL_ON_START_N_GO2 <NUM>, and VCSEL_ON_STOP_GO2 <NUM>.

Furthermore, it is within the driver output stage that the combinatorial logic decodes the encoded phase information, into the set timing requirements, and to summarise, for said method of compensating the path parasitic inductances for high bandwidth pulsed current signalling for laser diode driver.

Various embodiments with different variations have been described here above. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations.

Claim 1:
A laser diode driver circuit comprising:
a first pair of contacts and connectors configured to be coupled to an anode of a laser diode (<NUM>), the first pair of contacts and connectors comprising a first contact (<NUM>) and first connector (<NUM>) and a second contact (<NUM>) and a second connector (<NUM>), wherein an inductance of the first contact and first connector is the same as the inductance of the second contact and second connector;
a second pair of contacts and connectors, configured to be coupled to a cathode of the laser diode (<NUM>), the second pair of contacts and connectors comprising a third contact (<NUM>) and third connector (<NUM>) and a fourth contact (<NUM>) and a fourth connector (<NUM>), wherein an inductance of the third contact and third connector is the same as the inductance of the fourth contact and fourth connector;
current driving circuitry, characterized in that the current driving circuitry is configured to operate such that:
in a first phase a first current passes through the first pair of contacts and connectors and a further current passes through the second pair of contacts and connectors such that a potential difference between the cathode and anode is below a diode activation value;
in a second phase, succeeding the first phase, the further current passes through the first contact (<NUM>) and first connector (<NUM>), the laser diode (<NUM>) and the third contact (<NUM>) and third connector (<NUM>) such that the potential difference between the cathode and anode is above the diode activation value;
in a third phase, succeeding the second phase, a current passes through the first contact (<NUM>) and first connector (<NUM>), the laser diode (<NUM>) and the third contact (<NUM>) and third connector (<NUM>) and the potential difference between the cathode and anode is below the diode activation value.