Patent Description:
In optical communications, information is transmitted by way of an optical carrier whose frequency typically is in the visible or near-infrared region of the electromagnetic spectrum. A carrier with such a high frequency is sometimes referred to as an optical signal, an optical carrier, or a lightwave signal. A typical optical communication network includes several optical fibers, each of which may include several channels. A channel is a specified frequency band of an electromagnetic signal, and is sometimes referred to as a wavelength.

Technological advances today include optical communication at the level of a photonic integrated circuit (PIC) chip. This is because PICs have size advantages that are attractive in computer systems. Optical photonics devices such as lasers, modulators, and detectors are typically fabricated on silicon-on-insulator (SOI) wafers which are subsequently singulated to form PIC chips. Silicon waveguides of a PIC chip are typically designed with submicron cross-sections, allowing dense integration of active and passive devices to achieve higher speed and lower driving power. A grating structure typically serves as an optical mode converter (OMC) to provide optical coupling between a silicon waveguide of a PIC chip and an optical fiber.

As successive generations of semiconductor technologies continue to scale in terms of size, as well as speed and other capabilities, there is expected to be an increasing premium placed on improvements to techniques for providing optical signal communication between different devices.

<CIT> discloses an optical connector including a semiconductor substrate, an epitaxial layer of photoelectric element, and a waveguide. The semiconductor substrate has a surface that includes a photoelectric element zone, a wave guide zone, and an optical fiber zone, and defines a receiving groove in the optical fiber zone extending through the optical fiber zone and connecting with the waveguide zone and configured for receiving an optical fiber. The epitaxial layer of photoelectric element is grown up from the photoelectric element zone. The waveguide is directly formed on the waveguide zone.

<CIT> discloses a 3D coupling system including a layered structure that receives an input of a defined mode size. The layered structure includes a plurality of layers with varying indexes, and outputs a vertically mode converted beam associated with the input beam. A planar lens structure receives the vertically mode converted beam, and performs lateral mode conversion on the vertically mode converted beam. The 3D coupling structure outputs a laterally and vertically mode converted beam. A high index-contrast waveguide structure receives the laterally and vertically mode converted beam, and provides the laterally and vertically mode converted beam to a receiving device with less than <NUM> dB loss.

The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:.

Embodiments discussed herein variously provide techniques and mechanisms for coupling a lens structure of a photonic integrated circuit (PIC) chip to an optical fiber via a waveguide which is distinct from the PIC. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a PIC which is coupled to a substrate to accommodate optical coupling, via a waveguide, between an optical fiber and a cylindrical lens formed at an edge of the PIC.

In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

Embodiments described herein variously facilitate the provisioning of an assembly which comprises a substrate and a photonic integrated circuit (PIC) chip coupled thereto, wherein an optical waveguide structure is adjacent and optically coupled to photonic structures formed by the PIC chip. More particularly, the PIC chip forms one or more integrated optical structures - referred to herein as integrated edge-oriented couplers (IECs) - which are configured to be optically coupled for horizontal signal communication with the optical waveguide structure. In this particular context, "horizontal" refers to a direction in parallel with a plane in which one of two opposite sides of a PIC chip extends (e.g., wherein an edge of the PIC chip extends between the two sides). In various embodiments, an arrangement of the optical waveguide structure and one or more IECs facilitates the communication of an optical signal - in a direction parallel to a side of the PIC chip - between an IEC and a corresponding optical fiber. In various embodiments, a planar optical waveguide structure enables beam expansion, mode conversion, and/or other functionality to facilitate photonic signal communication between IECs of a PIC chip and another device (such as a fiber array) which is optically coupled to said PIC chip.

In providing such an assembly, some embodiments variously improve the ease, efficiency and accuracy with which a PIC chip is optically coupled to an array of optical fibers (and/or to another PIC chip, for example). Additionally or alternatively, such embodiments efficiently provide a low (z-dimension) profile solution for communicating optical signals to and/or from a packaged device.

Certain features of various embodiments are described herein with reference to an assembly comprising a PIC chip, and a preformed optical waveguide structure (referred to herein as an "waveguide preform") which are variously adhered, connected or otherwise coupled - directly or indirectly - each to a substrate. The PIC chip and the optical waveguide preform are distinct from each other, and extend over different respective regions of a package substrate (or other suitable substrate).

In other embodiments, a PIC chip comprises both a plurality of IECs and an integrated optical waveguide structure which is optically coupled to said plurality of IECs. In one such embodiment, a PIC chip is of a silicon on insulator (SOI) type - e.g., comprising an upper layer of a semiconductor material, an underlayer which, for example, comprises the same (or another) semiconductor material, and a layer of a buried oxide between the upper layer and the underlayer. The upper layer comprises silicon and/or the buried oxide comprises silicon dioxide, for example. By way of illustration and not limitation, the integrated optical waveguide structure is deposited, nano-imprinted and/or otherwise formed on a region of the buried oxide which, for example, was previously exposed by removal of a portion of the upper layer.

Certain features of various embodiments are described herein with reference to a given IEC of a PIC chip forming a divergent lens surface. In this particular context, "divergent" refers to the characteristic of the lens surface extending out from - e.g., as opposed to recessing into - a given edge (or other) surface of a PIC chip. In one illustrative embodiment, a divergent lens surface comprises a continuous convex surface at an edge of a PIC chip. Alternatively, a divergent lens surface comprises a plurality of discrete facets, individual ones of which are each substantially flat - e.g., over a respective transverse length and a respective longitudinal height of the lens surface. In one such embodiment, the plurality of discrete facets are "piecewise convex" - e.g., wherein corners (or other such structures) formed by said facets are variously located along the same convex curve.

<FIG> shows features of a device <NUM> to facilitate optical signal communication between a photonic integrated circuit (PIC) chip and an optical fiber according to an embodiment not according to the claimed invention. <FIG> shows a perspective view <NUM> of selected structures of device <NUM>. Device <NUM> illustrates one example of an embodiment wherein a PIC chip is coupled to a substrate to accommodate edge-wise optical coupling, via a waveguide structure (in this case, a waveguide preform), to one or more optical fibers.

As variously shown in <FIG>, device <NUM> comprises a substrate <NUM> and a PIC chip <NUM> coupled thereto. Substrate <NUM> comprises any of various organic, glass, silicon or other suitable substrate materials that (for example) are adapted from conventional packaging techniques. In one such embodiment, substrate <NUM> functions as a package substrate which is to provide support for PIC chip <NUM>, an optical waveguide structure, and (for example) one or more other integrated circuit (IC) chips - e.g., including the illustrative IC chip <NUM> shown. By way of illustration and not limitation, PIC <NUM> and IC chip <NUM> are variously coupled to the substrate <NUM> via respective ones of conductive contacts <NUM>, which (for example) are disposed in any of various suitable underfill materials. The conductive contacts <NUM> comprise any type of structure and materials - whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds - capable of providing electrical communication between substrate <NUM> and one or more chips including (in this example embodiment) IC chip <NUM> and PIC chip <NUM>. For example, conductive contacts <NUM> include copper, aluminum, gold, silver, nickel, titanium, tungsten, as well as any combination of these and/or other metals.

In an embodiment, each of conductive contacts <NUM> (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) couples to a corresponding electrically conductive terminal (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) on a respective chip. Solder (e.g., in the form of balls or bumps) is disposed on the conductive contacts <NUM> or on terminals of a given chip, which are then used to join PIC chip <NUM> (and, for example, IC chip <NUM>) to substrate <NUM> - e.g., using a solder reflow process. In some embodiments, the solder material comprises any one or more of tin, copper, silver, gold, lead, nickel, indium, as well as any combination of these and/or other metals. In one such embodiment, the solder also includes one or more additives and/or filler materials to alter a characteristic of the solder (e.g., to alter the reflow temperature). Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wirebonds extending between substrate <NUM> and one of IC chip <NUM> or PIC chip <NUM>). Device <NUM> further comprises a ball grid array <NUM> positioned proximate a surface of the substrate <NUM> to provide electrical connections with an underlying device (not shown) - e.g., a printed circuit board.

The one or more IC chips illustrated by IC chip <NUM> comprise (for example) any of a variety of integrated circuit devices which are suitable for a particular application, such as (but not limited to) a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, etc. In one embodiment, IC chip <NUM> comprises a system-on-chip (SoC) comprising one or more functional units (e.g., one or more processing units, one or more graphics units, one or more communications units, one or more signal processing units, one or more security units, etc.). However, it should be understood that some disclosed embodiments are not limited to any particular type or class of functionality to be provided with IC chip <NUM> (or other such integrated circuitry coupled to substrate <NUM> and PIC chip <NUM>).

PIC chip <NUM> comprises one or more optical coupler structures - e.g., including the illustrative integrated edge-oriented couplers (IECs) <NUM> shown - which are formed at an edge <NUM> of PIC chip <NUM>. PIC <NUM> further comprises integrated circuitry <NUM> which, for example, comprises optical signal transit circuitry and/or optical signal receiver circuitry. For example, integrated circuitry <NUM> - e.g., comprising any of a various lasers, modulators, photodetectors and/or other integrated photonics circuits - is formed on an active side <NUM> of PIC chip <NUM>, wherein an opposite side <NUM> comprises terminals with which PIC chip <NUM> is to variously communicate electrical signals (for example, with IC chip <NUM> and/or other circuitry via substrate <NUM>). In some embodiments, one or more optical signal transit circuits and/or one or more optical signal receiver circuits of integrated circuitry <NUM> are optically coupled each to a respective one of IECs <NUM> - e.g., via a corresponding one of one or more photonic waveguides of PIC chip <NUM> (such as the illustrative photonic waveguides <NUM> shown).

In an example embodiment, a semiconductor substrate of PIC chip <NUM> is of a silicon on insulator (SOI) type, and comprises (for example) an upper layer of a semiconductor material comprising silicon, an underlayer of the same semiconductor material (or another semiconductor material), and a buried oxide (BOX) layer between the upper layer and the underlayer. Photonic waveguides <NUM> and/or IECs <NUM> comprise any of various materials (such as crystalline silicon) which are suitable to communicate an optical signal - e.g., wherein such materials are adapted from conventional PIC chip designs.

To facilitate edge-wise communication of one or more optical signals to and/or from PIC chip <NUM> - i.e., via edge <NUM> - device <NUM> further comprises a planar optical waveguide preform <NUM> which is adhered to, or otherwise coupled over, a second region of substrate <NUM>. In an embodiment, an edge <NUM> of waveguide preform <NUM> - which comprises claddings <NUM>, <NUM>, and a core <NUM> therebetween - is adjacent to IECs <NUM> at edge <NUM>. In the example embodiment shown, device <NUM> further comprises (or facilitates coupling to) a fiber array housing <NUM> which has optical fibers <NUM> extending therein. By way of illustration and not limitation, device <NUM> supports coupling to a pluggable connector of an optical cable - e.g., wherein the connector includes fiber array housing <NUM>, and wherein optical fibers <NUM> of the cable extend from device <NUM> to couple to a remote packaged, or other, device (not shown). Although some embodiments are not limited in this regard, respective distal ends of some or all of optical fibers <NUM> variously form (or are coupled to) lens structures <NUM> to facilitate optical coupling with an adjacent edge <NUM> of waveguide preform <NUM>.

In various embodiments, waveguide preform <NUM> is formed by processing which, for example, is adapted from conventional photonics fabrication techniques. By way of illustration and not limitation, core <NUM> comprises any of various light transmissive materials - such as silicon nitride (Si<NUM>N<NUM>), silicon oxynitride (SiOxNy), and/or any of a various suitable doped oxides - exhibiting refractive index characteristics which facilitate optical coupling with optical fiber materials. However, it is to be appreciated that some embodiments are not limited to a particular one or more materials of waveguide preform <NUM>, and the such materials may differ in various embodiments according to implementation-specific details. As described herein, one or more surfaces of waveguide preform <NUM> (in some embodiments) are etched, laser ablated or otherwise shaped to form any of various recess structures therein - e.g., wherein one or more such recess structures are each to facilitate optical interfacing between waveguide preform <NUM> and a respective IEC or a respective optical fiber.

In some embodiments, photonic waveguides <NUM> are coplanar with each other - e.g., wherein the plurality of photonic waveguides <NUM> each extend in an x-y plane such as one at (or under) a side <NUM> of PIC chip <NUM>. For example, some or all of photonic waveguides <NUM> are each within a thickness of material in or on a semiconductor substrate of PIC chip <NUM> - e.g., wherein photonic waveguides <NUM> are within a top portion of the semiconductor substrate. In one such embodiment, some or all of IECs <NUM> are coplanar with each other - e.g., wherein IECs <NUM> each extend in an x-y plane such as one at (or under) side <NUM>.

IECs <NUM> each terminate a respective one of photonic waveguides <NUM>, and each form a respective lens surface that is divergent (in a y-z plane) and, in some embodiments, is substantially flat (in a x-y plane) over at least a thickness of the semiconductor substrate of PIC chip <NUM>. For example, IECs <NUM> are each substantially flat at side <NUM>, in some embodiments.

In the example embodiment shown, IECs <NUM> variously extend from an otherwise flat (in an y-z plane) side <NUM> - e.g., wherein IECs <NUM> form a portion of edge <NUM> which is positioned farthest along the x-axis in the direction of waveguide preform <NUM>. According to the invention, edge <NUM> forms a stepped structure, wherein an upper (along the z-axis) portion of the stepped structure comprises IECs <NUM>, and wherein a lower (along the z-axis) portion of the stepped structure extends past IECs <NUM> - e.g., by at least as much as a (x-axis) depth of a curvature of one of IECs <NUM> - to provide mechanical support for an overlapping portion of waveguide preform <NUM>.

In some embodiments, a given one of IECs <NUM> forms a convex lens surface which is substantially semicylindrical - e.g., wherein a curvature of the convex lens surface is symmetrical about a primary axis (along the x-dimension) of the convex lens surface. In one such embodiment, the primary axis of the given convex lens surface is in a lateral (y-axis) alignment with an optical axis of a corresponding one of the photonic waveguides <NUM> - e.g., wherein a radius of curvature of the given convex lens surface is equal to or larger than one half of a (y-axis) width of the corresponding photonic waveguide.

Additionally or alternatively, a divergent lens surface of one of IECs <NUM> comprises a plurality of discrete diffractive edge facets which are symmetrically distributed about a primary axis of said divergent lens surface. In one such embodiment, individual ones of the edge facets are substantially flat over a transverse (y-axis) length and a longitudinal (z-axis) height of the lens surface.

In some embodiments, one or more divergent lens surfaces of IECs <NUM> each extend into a semiconductor substrate of PIC chip <NUM>. By way of illustration and not limitation, photonic waveguides <NUM> and IECs <NUM> each comprise a material including silicon. In one such embodiment, the semiconductor substrate of PIC chip <NUM> is of a silicon-on-insulator (SOI) type - e.g., wherein PIC chip <NUM> comprises a layer of silicon dioxide between the material and an underlayer. For example, one or more divergent lens surfaces of IECs <NUM> each stop at, or within, the layer of silicon dioxide. Additionally or alternatively, one or more divergent lens surfaces of IECs <NUM> each extend at least partially through the underlayer.

In the example embodiment shown, core <NUM> forms a portion of edge <NUM> which is substantially flat (for example, in a y-z plane) across some or all of IECs <NUM>. In some alternative embodiments, edge <NUM> forms one or more surface recesses which are each to at least partially receive or otherwise interface with a corresponding one of IECs <NUM>. For example, in one such embodiment, some or all of said surface recesses each have a respective profile which is complementary to the profile of a divergent lens surface formed by a corresponding one of IECs <NUM>. By way of illustration and not limitation, one or more divergent lens surfaces of IECs <NUM> are each semicylindrical and convex, where one or more surface recesses at edge <NUM> each comprises a concave semicylinder. Some or all recesses formed at edge <NUM>, in some embodiments, extend through an entire (z-axis) thickness of core <NUM> and of cladding <NUM>. Additionally or alternatively, some or all such recesses at edge <NUM> each form a respective surface which is substantially flat (in a x-y plane) over at least a partial thickness of core <NUM>.

In the example embodiment shown, another edge <NUM> of waveguide preform <NUM> - the edge <NUM> opposite edge <NUM> - is substantially flat (for example, in a y-z plane) across some or all of IECs <NUM>. In some other embodiments, edge <NUM> alternatively forms one or more surface recesses which are each to at least partially receive or otherwise interface with a corresponding one of optical fibers <NUM> (for example, to a corresponding one of lens structures <NUM>). For example, in one such embodiment, edge <NUM> forms one or more substantially semispherical recesses, wherein core <NUM> optically couples individual ones of IECs <NUM> each to a corresponding one of said one or more semispherical recesses. For example, fiber array housing <NUM> is connected to, adhered to and/or otherwise disposed over a third region of substrate <NUM>, wherein individual ones of optical fibers <NUM> (and, for example, individual ones of lens structures <NUM>) are to be received by, or otherwise optically coupled to, individual ones of the second plurality of concave lens surfaces.

Although <FIG> show device <NUM> as providing optical coupling between IECs <NUM> of PIC chip <NUM> and optical fibers <NUM>, it is to be appreciated that planar optical waveguide preform <NUM> (or any of various other planar optical waveguide structures having features described herein) additionally or alternatively supports optical coupling between IECs of a PIC chip, and any of various other external photonic devices (such as another PIC chip), in different embodiments. For example, some embodiments are variously provided entirely by a PIC chip, or entirely by a packaged device which includes such a PIC chip (e.g., independent of whether a PIC chip of said packaged device is optically coupled to another device via a planar optical waveguide structure of said packaged device).

<FIG> shows features of a method <NUM> to facilitate optical coupling of a PIC chip to a waveguide according to an embodiment not according to the claimed invention. Operations such as those of method <NUM> are performed, for example, to provide structures of device <NUM>.

As shown in <FIG>, method <NUM> comprises (at <NUM>) patterning a plurality of coplanar optical waveguides into a thickness of a material over a plane of a substrate. In one illustrative embodiment, a silicon-on-insulator (SOI) substrate comprises an upper layer, an underlayer, and a buried dielectric (e.g. oxide) layer disposed therebetween. The upper layer (and, in some embodiments, the underlayer) comprises crystalline silicon and/or any of various other materials suitable to communicate an optical signal. In one such embodiment, the upper layer is then etched and/or otherwise patterned to form one or more rib waveguide structures therein or thereon. The patterning at <NUM> involves, for example, wet or dry etching techniques, any of various lithographic processes, or other patterning processes such as ablation, ruling, or other techniques which will be apparent to those skilled in the art.

Method <NUM> further comprises (at <NUM>) subtractively patterning divergent lens profiles each at a terminus of a respective one of the plurality of coplanar optical waveguides. By way of illustration and not limitation, the subtractive patterning comprises deposition of a patterned mask over a region of the substrate where the plurality of coplanar optical waveguides are to end (and, for example, where an edge of a PIC chip is to be subsequently formed). Subsequently, deep reactive ion etching (DRIE) and/or other suitable etch processing is performed through the patterned mask to form one or more lens structures. In some embodiments the patterning at <NUM> is performed concurrently with the subtractive patterning at <NUM>.

Method <NUM> further comprises (at <NUM>) singulating a photonic integrated circuit (PIC) chip comprising the plurality of coplanar optical waveguides, the divergent lens profiles, and a portion of the substrate. For example, the singulating at <NUM> comprises dicing a semiconductor wafer to form the edges of the PIC chip, wherein one such edge comprises integrated edge-oriented couplers (IECs) which each include a respective lens structure formed at <NUM>. In some embodiments, method <NUM> additionally or alternatively comprises operations (not shown) to form a planar optical waveguide structure which is integrated on the substrate - e.g., wherein a core of the planar optical waveguide structure is adjacent to (and optically coupled with) the IECs, and wherein the planar optical waveguide structure is integrated with, and extends to an edge of, the singulated PIC chip.

Method <NUM> further comprises (at <NUM>) coupling the PIC chip over a first region of a package substrate - e.g., wherein such coupling comprises operations adapted from conventional flip-chip, wire bonding and/or other techniques. Method <NUM> further comprises (at <NUM>) coupling an optical waveguide preform over a second region of the package substrate - e.g., wherein the waveguide preform is adhered or otherwise bonded to the second region. In other embodiments, method <NUM> omits the coupling at <NUM> - e.g., wherein the planar optical waveguide structure is formed as an integrated structure of the PIC chip. Method <NUM> further comprises (at <NUM>) coupling an array of optical fibers to the planar optical waveguide preform. In an embodiment, the waveguide preform comprises a core, opposite ends of which are optically coupled (respectively) to the IECs and to the array of optical fibers.

<FIG> shows features of an assembly <NUM> to facilitate optical communications with a PIC chip and a waveguide according to an embodiment. In various embodiments, assembly <NUM> provides functionality such as that of device <NUM> - e.g., wherein one or more operations of method <NUM> are to provide structures of assembly <NUM>.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, a fiber array housing <NUM>, and a waveguide preform <NUM> which are variously coupled, directly or indirectly, to a substrate (not shown) such as substrate <NUM>. Waveguide preform <NUM> facilitates edge-wise communication of one or more optical signals to and/or from PIC chip - e.g., wherein a core <NUM> of waveguide preform <NUM> optically couples optical fibers 352a, 352b, in fiber array housing <NUM>, each to a respective one of IECs 336a, 336b which are variously formed at an edge of PIC chip <NUM>. In one such embodiment, PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively) - e.g., wherein IECs 336a, 336b, core <NUM>, and optical fibers 352a, 352b correspond functionally to IECs <NUM>, core <NUM>, and optical fibers <NUM> (respectively).

In the example embodiment shown, a length x2 of core <NUM>, between the edge of PIC chip <NUM> and fiber array housing <NUM>, is in a range of <NUM> to <NUM> - e.g., wherein length x2 is in a range of <NUM> to <NUM> (and, in some embodiments, in a range of <NUM> to <NUM>). In one such embodiment, an x-axis depth x1 of a curvature of IEC 336a (for example) is in a range of <NUM> to <NUM> - e.g., wherein depth x1 is in a range of <NUM> to <NUM> and, in some embodiments, in a range of <NUM> to <NUM>. By way of illustration and not limitation, a y-axis width y1 of a given one of IECs 336a, 336b is in a range of <NUM> to <NUM> (e.g., in a range of <NUM> to <NUM> and, in some embodiments, in a range of <NUM> to <NUM>). In one such embodiment, IEC 336a forms a convex surface, wherein a radius of curvature r1 of the convex surface is at least <NUM>% of width y1 (e.g., where radius r1 is in a range of <NUM>% to <NUM>% of width y1).

In the example embodiment shown, core <NUM> has a (z-axis) thickness z1 which is the same along the length x2. For example, thickness z1 is in a range of <NUM> microns (µm) to <NUM> (e.g., in a range of <NUM> to <NUM>). In some alternative embodiments, core <NUM> has different thicknesses at various points along the length x2. In one such embodiment, a first end of core <NUM>, which adjoins IECs 336a, 336b, is in a range of <NUM> to <NUM> - e.g., wherein a second end of core <NUM>, which adjoins optical fibers 352a, 352b at fiber array housing <NUM>, is in a range of <NUM> to <NUM>. It is appreciated that, in some embodiments, the above described ranges of values for various dimensions of assembly <NUM> are merely illustrative, and that some or all such ranges may differ in other embodiments, according to implementation-specific details.

<FIG> show features of respective PIC chips <NUM>, <NUM> which are each to communicate an optical signal with a waveguide according to a corresponding embodiment. PIC chips <NUM>, <NUM> variously provide functionality such as that of PIC chip <NUM> - e.g., wherein operations of method <NUM> are to facilitate optical coupling of a waveguide preform with one of PIC chips <NUM>, <NUM>.

As shown in <FIG>, a surface <NUM> of PIC chip <NUM> has formed therein or thereon silicon waveguides 434a, 434b, 434c that, for example, variously extend from integrated circuitry (not shown) - e.g., including integrated photonic circuitry and, in some embodiments, integrated electrical circuitry - which is formed in or on surface <NUM>. An edge <NUM> of PIC chip <NUM> forms the respective divergent lens surfaces of IECs 436a, 436b, 436c, which are each at a respective terminus of a corresponding one of silicon waveguides 434a, 434b, 434c. In various embodiments, PIC chip <NUM> provides functionality of PIC chip <NUM> - e.g., wherein silicon waveguides 434a, 434b, 434c, edge <NUM>, and IECs 436a, 436b, 436c correspond functionally to photonic waveguides <NUM>, edge <NUM>, and IECs <NUM> (respectively).

PIC chip <NUM> illustrates one embodiment wherein one or more IECs each form a respective divergent lens surface which is piecewise convex. For example, the divergent lens surface of IEC 436c comprises a plurality of discrete diffractive edge facets <NUM> which, in some embodiments, are symmetrically distributed about a primary axis CL1 of IEC 436c. In one such embodiment, individual ones of said edge facets <NUM> are each substantially flat over a transverse (y-axis) length and a longitudinal (z-axis) height of IEC 436c. Additionally or alternatively, the primary axis CL1 of IEC 436c is in a transverse (y-axis) alignment with an optical axis of the corresponding silicon waveguide 434c. In one such embodiment, the divergent lens surface of IEC 436c includes corners (or other such points) which are distributed along a semicylindrical curve, a radius of which is equal to or larger than one half of a (y-axis) width w1 of silicon waveguide 434c.

As shown in <FIG>, a surface <NUM> of PIC chip <NUM> has formed therein or thereon silicon waveguides 484a, 484b, 484c that, for example, variously extend from integrated circuitry (not shown) which is formed in or on surface <NUM>. An edge <NUM> of PIC chip <NUM> forms the respective divergent lens surfaces of IECs 486a, 486b, 486c, at the respective termini of silicon waveguides 484a, 484b, 484c. In various embodiments, PIC chip <NUM> provides functionality of PIC chip <NUM> - e.g., wherein silicon waveguides 484a, 484b, 484c, edge <NUM>, and IECs 486a, 486b, 486c correspond functionally to photonic waveguides <NUM>, edge <NUM>, and IECs <NUM> (respectively).

PIC chip <NUM> illustrates one embodiment wherein one or more IECs each form a respective convex lens surface. For example, IEC 486a forms a convex lens surface which is symmetrical about a primary axis CL2. In one such embodiment, the primary axis CL2 of IEC 486a is in a transverse (y-axis) alignment with an optical axis of the corresponding silicon waveguide 484a. Additionally or alternatively, the convex surface of IEC 486a conforms to a semicylindrical curve, a radius of which is equal to or larger than one half of a (y-axis) width w2 of silicon waveguide 484a.

<FIG> show various structures during respective stages <NUM>, <NUM>, <NUM> of processing to fabricate IECs of a PIC chip according to an embodiment not according to the claimed invention. Processing such as that illustrated by stages <NUM>, <NUM>, <NUM> is performed, for example, to provide structures of one of PIC chips <NUM>, <NUM>, <NUM>, or <NUM> - e.g., wherein operations of method <NUM> include or are otherwise based on some or all such processing. The various structures in stages <NUM>, <NUM>, <NUM> are also shown by the respective cross-sectional side views <NUM>, <NUM>, <NUM> in <FIG> (respectively). The cross-sections for side views <NUM>, <NUM>, <NUM> correspond to the line A-A' shown.

As shown in <FIG>, structures at stage <NUM> are formed by processing of a SOI wafer which comprises an underlayer <NUM> of a semiconductor material, an insulator layer <NUM> comprising any of various suitable dielectric materials (such as SiOz) over underlayer <NUM>, and an upper layer <NUM> of a material which (for example) comprises silicon. Some or all of upper layer <NUM> (and, in some embodiments, the underlayer <NUM>) comprises crystalline silicon and/or any of various other materials suitable to communicate an optical signal.

At stage <NUM>, photonic waveguide structures (such as the illustrative silicon waveguides <NUM> shown) are formed in or on layer <NUM> - e.g., where such forming includes any of various suitable wet or dry etching techniques, any of various lithographic processes, or other patterning processes such as ablation, ruling, or the like. In one such embodiment, silicon waveguides <NUM> are rib waveguide structures formed by patterned etching of crystalline silicon in a material layer above a horizontal (x-y) plane p1 which extends in or on layer <NUM>. Silicon waveguides <NUM> variously extend to a body of a material <NUM> which (for example) comprises crystalline silicon or any of various other materials which are suitable to communicate an optical signal. At stage <NUM> (or alternatively, at a later processing stage), silicon waveguides <NUM> further extend variously between material <NUM> and integrated circuitry (not shown) - e.g., including integrated photonic circuitry and, in some embodiments, integrated electrical circuitry - which is formed in or on layer <NUM>. In various embodiments, material <NUM> has a same composition as a material of silicon waveguides <NUM>.

As shown in <FIG>, a patterned mask <NUM> is formed at stage <NUM> on structures which are variously formed in or on layer <NUM> - e.g., the structures including silicon waveguides <NUM>, and portions of material <NUM>. In an embodiment, some portions of patterned mask <NUM> - which extend over material <NUM> - comprise various concave or otherwise divergent profiles, which are to facilitate the formation of IEC structures.

As shown in <FIG>, structures at stage <NUM> are formed by an etch process, after which the patterned mask <NUM> is removed from silicon waveguides <NUM> and/or from other structures which are formed in or on layer <NUM>. In some embodiments, the etch process - e.g., comprising deep reactive ion etching (DRIE) - selectively removes portions of material <NUM>, wherein remaining portions of material <NUM> form IECs <NUM> which are at an edge portion of layer <NUM>, and which are each at a respective termini of a corresponding one of silicon waveguides <NUM>.

In this example embodiment, IECs <NUM> extend vertically to insulator layer <NUM> - e.g., wherein the etch process exposes a surface <NUM> of insulator layer <NUM> (for example). IECs <NUM> forms one or more divergent lens profiles, wherein a maximum horizontal (x-axis) extent of said lens profiles is indicated by the vertical plane <NUM> (i.e., an y-z plane) shown. In various embodiments, subsequent singulation forms a PIC chip which comprises the structures shown in view <NUM>. For example, an edge of the singulated PIC chip forms a stepped structure comprising an upper portion and a lower portion. In one such embodiment, the upper portion, which is above surface <NUM>, comprises the respective divergent lens profiles of IECs <NUM> - e.g., wherein the lower portion is below surface <NUM>, and extends horizontally past vertical plane <NUM> to another vertical plane <NUM>. As described herein, the lower portion provides support for, and/or facilitates alignment with, a waveguide preform that is to be optically coupled with IECs <NUM>, in some embodiments.

<FIG> show features of respective assemblies <NUM>, <NUM> each to facilitate optical communications with a respective waveguide according to a corresponding embodiment not according to the claimed invention. <FIG> shows features of an assembly <NUM> to facilitate optical communications with a respective waveguide according to a corresponding embodiment according to the claimed invention. Assemblies <NUM>, <NUM>, <NUM> variously illustrate embodiments wherein a (z-axis) thickness of a waveguide core increases along a distance from IECs of a PIC chip to one or more optical fibers which are optically coupled thereto. Some or all of assemblies <NUM>, <NUM>, <NUM> each provide respective functionality of device <NUM>, or assembly <NUM> (for example) - e.g., wherein method <NUM> is to provide functionality of one or more of assemblies <NUM>, <NUM>, <NUM>.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, a fiber array housing <NUM>, and a waveguide preform <NUM> which optically couples optical fibers <NUM> (which extend in fiber array housing <NUM>) each to a respective one of IECs <NUM> which are variously formed at an edge <NUM> of PIC chip <NUM>. IECs <NUM> facilitate edge-wise communication of optical signals - via silicon waveguides <NUM> of PIC chip <NUM> - between waveguide preform <NUM> and integrated circuitry of PIC chip <NUM>. For example, waveguide preform <NUM> comprises cladding <NUM>, cladding <NUM>, and a core <NUM> which is extends therebetween, wherein a first edge of waveguide preform <NUM> is positioned to have one end of core <NUM> be adjacent to IECs <NUM> (which are each at a terminus of a respective one of silicon waveguides <NUM>). A second edge of waveguide preform <NUM> (opposite the first edge) is positioned to have an opposite end of core <NUM> be adjacent to optical fibers <NUM> which variously extend in fiber array housing <NUM>.

In one such embodiment, PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively) - e.g., wherein silicon waveguides <NUM>, edge <NUM>, IECs <NUM>, cladding <NUM>, core <NUM>, cladding <NUM>, and optical fibers <NUM> correspond functionally to photonic waveguides <NUM>, edge <NUM>, IECs <NUM>, cladding <NUM>, core <NUM>, cladding <NUM>, and optical fibers <NUM> (respectively).

In the example embodiment shown, the top and bottom surfaces of core <NUM> are variously inclined each with respect to a horizontal (x-y) plane in which silicon waveguides <NUM> variously extend. Accordingly, core <NUM> provides for an expansion of an optical signal during communication thereof from one of IECs <NUM> to a corresponding one of optical fibers <NUM>. Alternatively or in addition, core <NUM> provides for an optical signal decreasing in size during communication thereof from one of optical fibers <NUM> to a corresponding one of IECs <NUM>.

According to the invention, edge <NUM> of PIC chip <NUM> forms a stepped structure, wherein an upper portion of the stepped structure comprises IECs <NUM>, and a lower portion of the stepped structure extends past IECs <NUM>. In one such embodiment, waveguide preform <NUM> overlaps the lower portion of said stepped structure - e.g., wherein the lower portion facilitates alignment of, and/or provides support for, at least a portion of waveguide preform <NUM>.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, a fiber array housing <NUM>, and a waveguide preform <NUM> which optically couples optical fibers <NUM> (which extend in fiber array housing <NUM>) each to a respective one of IECs <NUM> which are variously formed at an edge <NUM> of PIC chip <NUM>. IECs <NUM> facilitate edge-wise communication of optical signals - via silicon waveguides <NUM> of PIC chip <NUM> - between waveguide preform <NUM> and integrated circuitry of PIC chip <NUM>. In one such embodiment PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively). In the example embodiment shown, a core of waveguide preform <NUM> (the core adjacent to IECs <NUM> and optical fibers <NUM>) comprises a top surface <NUM> and a bottom surface <NUM>, only one of which is inclined with respect to a horizontal (x-y) plane in which silicon waveguides <NUM> variously extend. For example, top surface <NUM> is inclined toward a top side <NUM> of waveguide preform <NUM>, while bottom surface <NUM> is parallel to both top side <NUM> and a bottom side <NUM> of waveguide preform <NUM>.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, a fiber array housing <NUM>, and a waveguide preform <NUM> which optically couples optical fibers <NUM> (which extend in fiber array housing <NUM>) each to a respective one of IECs <NUM> which are variously formed at an edge <NUM> of PIC chip <NUM>. IECs <NUM> facilitate communication of optical signals, via silicon waveguides <NUM> of PIC chip <NUM>, between waveguide preform <NUM> and integrated circuitry of PIC chip <NUM>. In one such embodiment PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively). In the example embodiment shown, a core of waveguide preform <NUM> (the core adjacent to IECs <NUM> and optical fibers <NUM>) comprises a top surface <NUM> and a bottom surface <NUM>, which are variously inclined step-wise in different respective vertical (z-axis) directions, along the length of waveguide <NUM>, from IECs <NUM> to optical fibers <NUM>.

<FIG> shows, in an exploded view, features of an assembly <NUM> to communicate an optical signal with a PIC chip according to an embodiment not according to the claimed invention. <FIG> shows a cross-sectional top view <NUM> of assembly <NUM>. In various embodiments, assembly <NUM> includes some or all features of device <NUM> - e.g., wherein structures of assembly <NUM> are provided by and/or used in operations of method <NUM>, for example.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, a waveguide preform <NUM>, and a fiber array housing <NUM> which, for example, correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively). In one such embodiment, IECs <NUM>, which are formed by an edge <NUM> of PIC chip <NUM>, facilitate edge-wise communication of optical signals between waveguide preform <NUM> and integrated circuitry (not shown) of PIC chip <NUM>. For example, waveguide preform <NUM> comprises cladding <NUM>, cladding <NUM>, and a core <NUM> which is extends therebetween, wherein an edge <NUM> of waveguide preform <NUM> is positioned to have one end of core <NUM> be adjacent to edge <NUM>. Another edge <NUM> of waveguide preform <NUM> is positioned to have an opposite end of core <NUM> be adjacent to an edge <NUM> of fiber array housing <NUM>. In an embodiment, optical fibers <NUM> extending from edge <NUM> are optically coupled, via core <NUM>, each to a corresponding one of IECs <NUM>.

In the example embodiment shown, edge <NUM> forms recess structures <NUM>, individual ones of which are each to receive, or otherwise interface with, a corresponding one of IECs <NUM>. For example, individual ones of recess structures <NUM> each have a respective profile which is complementary to a profile of the divergent lens surface of the corresponding IEC. In some embodiments, some or all of recess structures <NUM> extend only partially along the (z-axis) height of edge <NUM> - e.g., wherein individual ones of recess structures <NUM> each form a substantially flat, horizontal (in an x-y plane) surface over at least a partial (z-axis) thickness of core <NUM>. In one such embodiment, a divergent lens surface formed by a given one of IECs <NUM> is convex and (for example) substantially semicylindrical, wherein a corresponding of recess structures <NUM> comprises a concave semicylinder. Additionally or alternatively, individual ones of recess structures <NUM> extend through the entire thickness of cladding <NUM> (for example).

In the example embodiment shown, the edge <NUM> of waveguide preform <NUM> (opposite edge <NUM>) forms recess structures <NUM> which are each to receive or otherwise interface with a corresponding one of optical fibers <NUM>. By way of illustration and not limitation, recess structures <NUM> comprise substantially hemispherical surfaces, wherein core <NUM> optically couples individual ones of IECs <NUM> to individual ones of said substantially hemispherical surfaces.

<FIG> show exploded views of respective assemblies <NUM>, <NUM> each to facilitate edge-wise optical signal communications with a PIC chip, and a waveguide preform according to a corresponding embodiment not according to the claimed invention. One or both of assemblies <NUM>, <NUM> each provide respective functionality such as that of device <NUM> (for example) - e.g., wherein method <NUM> is to provide functionality of one or more of assemblies <NUM>, <NUM>.

As shown in <FIG>, assembly <NUM> comprises a sub-assembly <NUM> and a cable <NUM> which (in this example) is to be pluggably connected to sub-assembly <NUM>. Sub-assembly <NUM> comprises a substrate <NUM> and a PIC chip <NUM> coupled thereto. PIC chip <NUM> comprises integrated circuitry <NUM> and IECs <NUM> which are variously optically coupled to integrated circuitry <NUM> each via a respective silicon waveguide on a substrate of PIC chip <NUM>. Furthermore, cable <NUM> comprises a pluggable connector <NUM> and a fiber array housing <NUM> coupled thereto - e.g., wherein optical fibers <NUM> in fiber array housing <NUM> variously extend from pluggable connector <NUM> to facilitate coupling of assembly <NUM> to another device. Pluggable connector <NUM> includes a waveguide preform which comprises a core <NUM> that is optically coupled to respective distal ends of optical fibers <NUM>. In one such embodiment, PIC chip <NUM>, the waveguide preform of pluggable connector <NUM>, and fiber array housing <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively) - e.g., wherein integrated circuitry <NUM>, IECs <NUM>, core <NUM>, and optical fibers <NUM> correspond functionally to integrated circuitry <NUM>, IECs <NUM>, core <NUM>, and optical fibers <NUM> (respectively).

In the example embodiment of assembly <NUM>, PIC chip <NUM> is positioned at an edge of substrate <NUM> - e.g., wherein IECs <NUM> extend to (and in some embodiments, beyond) said edge of substrate <NUM>, and wherein cable <NUM> includes a waveguide preform to be optically coupled to IECs <NUM>. In various embodiments, respective alignment features of sub-assembly <NUM> and cable <NUM> facilitate efficient optical alignment of IECs <NUM> each with a respective one of optical fibers <NUM>. By way of illustration and not limitation, substrate <NUM> and pluggable connector <NUM> have formed therein respective alignment features <NUM>, <NUM> (e.g., comprising one or more holes, pins, posts, or other suitable structures), which are reciprocal to each other, to facilitate an optical interfacing of IECs <NUM> with recess structures <NUM> which are variously formed at a nearest side of core <NUM>. In an alternative embodiment, alignment features <NUM> are formed in a package mold (not shown) or other suitable structure of sub-assembly <NUM> which is disposed on, under and/or around substrate <NUM>. In some embodiments, IECs <NUM> and recess structures <NUM> are themselves additional or alternative alignment features of assembly <NUM> - e.g., wherein each of recess structures <NUM> is to receive, at least in part, a corresponding one of IECs <NUM>.

As shown in <FIG>, assembly <NUM> comprises a sub-assembly <NUM> and a cable <NUM> which (for example) is pluggably connected to sub-assembly <NUM>. Sub-assembly <NUM> comprises a substrate <NUM> and a PIC chip <NUM> coupled thereto. PIC chip <NUM> comprises integrated circuitry <NUM> and IECs <NUM> which are variously coupled to integrated circuitry <NUM> each via a respective silicon waveguide on a substrate of PIC chip <NUM>. Sub-assembly <NUM> further comprises a waveguide preform which includes a core <NUM> that is optically coupled to PIC chip <NUM> - e.g., wherein IECs <NUM> are each received into a respective recess structure formed at an adjoining side of core <NUM>. Furthermore, cable <NUM> comprises a pluggable connector <NUM>, wherein optical fibers <NUM> of cable <NUM> variously extend from pluggable connector <NUM> to facilitate coupling of assembly <NUM> to another device. In one such embodiment, PIC chip <NUM>, the waveguide preform of sub-assembly <NUM>, and pluggable connector <NUM> correspond functionally to PIC chip <NUM>, waveguide preform <NUM>, and fiber array housing <NUM> (respectively) - e.g., wherein integrated circuitry <NUM>, IECs <NUM>, core <NUM>, and optical fibers <NUM> correspond functionally to integrated circuitry <NUM>, IECs <NUM>, core <NUM>, and optical fibers <NUM> (respectively).

In the example embodiment of assembly <NUM>, PIC chip <NUM> is recessed from an edge of substrate <NUM> - e.g., wherein core <NUM>, which extends to said edge of substrate <NUM>, forms recess structures <NUM> which are each to receive or otherwise interface with a corresponding one of optical fibers <NUM>. In various embodiments, respective alignment features of sub-assembly <NUM> and cable <NUM> facilitate efficient optical alignment of IECs <NUM> each with a respective one of optical fibers <NUM>. By way of illustration and not limitation, substrate <NUM> and pluggable connector <NUM> have formed therein respective alignment features <NUM>, <NUM> (e.g., comprising one or more holes, pins, posts, or other suitable structures), which are reciprocal to each other, to facilitate an optical interfacing of recess structures <NUM> each with a corresponding one of optical fibers <NUM>. In some embodiments, alignment features <NUM> are alternatively formed in a package mold (not shown) or other suitable structure of sub-assembly <NUM> which is disposed on, under and/or around substrate <NUM>. In some embodiments, recess structures <NUM> and respective lens structures formed by optical fibers <NUM> are themselves additional or alternative alignment features of assembly <NUM> - e.g., wherein each of recess structures <NUM> is to receive, at least in part, a corresponding lens structure formed by one of optical fibers <NUM>.

<FIG> show features of an assembly <NUM> to facilitate optical communications with a PIC chip comprising both IECs, and an integrated planar waveguide structure according to an embodiment not according to the claimed invention. Assembly <NUM> provides functionality of device <NUM>, or of one of assemblies <NUM>, <NUM>, <NUM>, <NUM> (for example) - e.g., wherein method <NUM> is to provide functionality of assembly <NUM>.

As shown in <FIG>, assembly <NUM> comprises a PIC chip <NUM>, and a fiber array housing <NUM>, wherein an integrated planar waveguide structure <NUM> of PIC chip <NUM> optically couples optical fibers <NUM> (which extend in fiber array housing <NUM>) each to a respective one of IECs <NUM> which are variously formed at a sidewall structure 935a of PIC chip <NUM>. IECs <NUM> facilitate edge-wise communication of optical signals - via silicon waveguides <NUM> of PIC chip <NUM> - between integrated planar waveguide structure <NUM> and integrated circuitry <NUM> of PIC chip <NUM>. For example, integrated planar waveguide structure <NUM> comprises cladding <NUM>, and a core <NUM> which is extends therebetween, wherein a first edge of integrated planar waveguide structure <NUM> is positioned to have one end of core <NUM> be adjacent to IECs <NUM> (which are each at a terminus of a respective one of silicon waveguides <NUM>). An edge 935b of PIC chip <NUM> forms, or is otherwise proximate to, a second edge of integrated planar waveguide structure <NUM> (opposite the first edge) - wherein the second edge is positioned to have an opposite end of core <NUM> be adjacent to optical fibers <NUM>. In one such embodiment, integrated planar waveguide structure <NUM>, corresponds functionally to waveguide preform <NUM> - e.g., wherein silicon waveguides <NUM>, IECs <NUM>, cladding <NUM>, core <NUM>, and optical fibers <NUM> correspond functionally to photonic waveguides <NUM>, IECs <NUM>, cladding <NUM>, core <NUM>, and optical fibers <NUM> (respectively).

In the example embodiment shown, PIC chip <NUM> is of a silicon on insulator (SOI) type - e.g., wherein integrated circuitry <NUM>, silicon waveguides <NUM>, and IECs <NUM> are variously formed in an upper layer comprising a semiconductor material. PIC <NUM> further comprises an underlayer <NUM> (of the same semiconductor material, for example), and a buried oxide layer <NUM> which is between the upper layer and underlayer <NUM>. The upper layer comprises silicon and/or the buried oxide comprises silicon dioxide, for example. By way of illustration and not limitation, the core <NUM> of integrated optical waveguide structure <NUM> is deposited, nano-imprinted and/or otherwise formed on a region of the buried oxide layer <NUM> - e.g., where such region was previously exposed by removal of a portion of the upper layer. Formation of core <NUM>, and cladding <NUM> on buried oxide layer <NUM> includes any of various suitable operations which (for example) are adapted from conventional lithographic etch, and deposition techniques. In some embodiments, the underlying portion of buried oxide layer <NUM> functions as a bottom cladding beneath the core <NUM>.

<FIG> illustrates a computing device <NUM> in accordance with one embodiment not according to the claimed invention. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Some embodiments may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc..

<FIG> illustrates a diagrammatic representation of a machine in the exemplary form of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system <NUM> includes a processor <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory <NUM> (e.g., a data storage device), which communicate with each other via a bus <NUM>.

Processor <NUM> represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor <NUM> is configured to execute the processing logic <NUM> for performing the operations described herein.

The computer system <NUM> may further include a network interface device <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), and a signal generation device <NUM> (e.g., a speaker).

The secondary memory <NUM> may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) <NUM> on which is stored one or more sets of instructions (e.g., software <NUM>) embodying any one or more of the methodologies or functions described herein. The software <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processor <NUM> also constituting machine-readable storage media. The software <NUM> may further be transmitted or received over a network <NUM> via the network interface device <NUM>.

While the machine-accessible storage medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any of one or more embodiments. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

<FIG> illustrates an interposer <NUM> that includes one or more embodiments. The interposer <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some embodiments, the first and second substrates <NUM>, <NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the first and second substrates <NUM>, <NUM> are attached to the same side of the interposer <NUM>. And in further embodiments, three or more substrates are interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer <NUM>. In accordance with some embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer <NUM>.

Techniques and architectures for optically coupling a photonic integrated circuit with optical fibers via a waveguide are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

Claim 1:
A photonic device comprising:
a package substrate (<NUM>); and
a photonic integrated circuit, PIC, chip (<NUM>) which extends over a first region of the package substrate (<NUM>), the PIC chip (<NUM>) comprising:
a plurality of coplanar photonic waveguides (<NUM>); and
a plurality of coplanar integrated edge-oriented couplers, IECs (<NUM>),
wherein a planar optical waveguide structure of the photonic device extends over a second region of the package substrate (<NUM>), the planar optical waveguide structure comprising a core (<NUM>),
wherein an edge of the core (<NUM>) is adjacent to the plurality of coplanar IECs (<NUM>);
characterized in that: individual ones of the plurality of coplanar IECs (<NUM>) each terminate a respective one of the coplanar photonic waveguides (<NUM>) with a respective divergent lens surface that is substantially flat over at least the thickness;
the PIC chip (<NUM>) forms a stepped structure;
an upper portion of the stepped structure comprises the plurality of coplanar IECs (<NUM>);
a lower portion of the stepped structure extends past the plurality of coplanar IECs (<NUM>); and
the planar optical waveguide structure overlaps the lower portion.