Patent Description:
A storage device is a device, which stores data. For example, the storage device may operate under a control of a host device such as a computer, a smart phone, or a smart pad, and may include, for example, a device, which stores data in a semiconductor memory, in particular, a nonvolatile memory, such as a solid state drive (SSD), a memory card, etc. In addition, the storage device may perform calculation functions depending on implementation thereof, and may include an additional volatile memory and a core for executing the calculation functions, to perform the calculation functions. A long latency of a nonvolatile memory such as a NAND flash memory included in the storage device is a major factor in degrading performance, and thus, techniques capable of improving the performance of a storage device are desired.

<CIT> discloses a computer memory expansion device and method of operation.

<CIT> discloses a disaggregated memory server.

<CIT> discloses a method and system for host-assisted data recovery assurance for data center storage device architectures.

Embodiments of the present disclosure provide a storage system capable of improving performance by performing caching and pre-fetching using data access features.

The above and other aspects and features of the present disclosure will be more clearly understood from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which:.

Hereinafter, embodiments will described with reference to the accompanying drawings. Embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure.

<FIG> illustrates a storage system 100A, according to an embodiment.

Referring to <FIG>, the storage system 100A according to an embodiment includes a host system <NUM>, a backplane <NUM>, a storage set <NUM>, and a battery module <NUM>.

The storage system 100A may be implemented as, for example, a server, a data center, a personal computer (PC), a network-attached storage, an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices may include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-books, wearable devices, etc..

The host system <NUM> may communicate with the storage set <NUM> through various interfaces. For example, the host system <NUM> may be implemented with an Application Processor (AP) or a System-On-a-Chip (SoC). Also, for example, the host system <NUM> may be implemented with an integrated circuit or a main board, but embodiments are not limited thereto.

The host system <NUM> may transmit a write request and a read request to the storage set <NUM>. The storage set <NUM> may store data received from the host system <NUM> in response to a write request, and may read stored data and transmit the read data to the host system <NUM> in response to a read request. In addition, the host system <NUM> may transmit a pre-fetch request to the storage set <NUM>. In response to the pre-fetch request, the storage set <NUM> may perform caching or pre-fetching of data stored in a memory region with relatively long latency to a memory region with relatively short latency.

The backplane <NUM> is provided between the host system <NUM> and the storage set <NUM>, is connected to the host system <NUM> and the storage set <NUM>, and may be configured to allow the host system <NUM> and the storage set <NUM> to exchange data through various communication protocols.

The storage set <NUM> and the battery module <NUM> may be accommodated in a form factor. The form factor may include a variety of form factors conforming to standard specifications, and may be, for example, an Enterprise and Data Center Standard Form Factor (EDSFF) including E3. L 2T, but embodiments are not limited thereto.

A plurality of storage sets 160a to 160c may be provided in the storage set <NUM> and may be connected to the host system <NUM> and the battery module <NUM> through the backplane <NUM>. The storage set <NUM> is a device having a calculation function and a data storage function, and may be referred to as a smart storage device. The storage set <NUM> may receive power from the host system <NUM> and the battery module <NUM> through the backplane <NUM>.

The battery module <NUM> is connected to the host system <NUM> and the plurality of storage sets <NUM> through the backplane <NUM>. The battery module <NUM> may be implemented with, for example, a lithium-ion battery, a rechargeable battery, a capacitor, a super-capacitor, etc. However, this is only illustrative, and embodiments are not limited thereto. The battery module <NUM> may provide power to the host system <NUM> and the plurality of storage sets <NUM>. In addition, when main power provided by the host system <NUM> decreases below a reference power level, the battery module <NUM> may be used as a reserve power source. In this case, the battery module <NUM> may be used to replace or supplement power supplied from an external power source.

In an embodiment, at least one of the plurality of storage sets <NUM> may include a plurality of memory regions. For convenience of description, it will be assumed that the storage set <NUM> includes three memory regions MR1, MR2, and MR3. However, this is only illustrative, and embodiments are not limited thereto. For example, the storage set <NUM> may include two memory regions or more than three memory regions.

The plurality of memory regions MR1, MR2, and MR3 form a memory hierarchy, and may be provided to store data of different characteristics, respectively.

For example, the first memory region MR1 may be provided to store immediately used data. In this case, the immediately used data may refer to data that should be immediately transferred in response to a request received from the host system <NUM>. The first memory region MR1 may be implemented with a memory having relatively low latency. The first memory region MR1 may be implemented with, for example, a volatile memory such as a DRAM. In addition, the first memory region MR1 may be implemented with an SRAM or an eSRAM.

For example, the second memory region MR2 may be provided to store frequently used data. In this case, the frequently used data may be data that is accessed by the host system <NUM> with high frequency, and may refer to data that is likely to be accessed by the host system <NUM> at a near point in time. The second memory region MR2 may be implemented with a memory having relatively low latency. The second memory region MR2 may be implemented with, for example, a volatile memory such as a DRAM.

For example, the third memory region MR3 may be provided to store important data. In this case, the important data may refer to data that should not be lost even in situations such as sudden power off (SPO). The third memory region MR3 may be implemented with a memory having relatively long latency. The third memory region MR3 may be implemented with a nonvolatile memory such as, for example, a NAND flash memory.

The storage system <NUM> according to an embodiment may store data in any one of the first to third memory regions MR1 to MR3 based on a data access feature. Alternatively, the storage system <NUM> may move data stored in the third memory region MR3 having a long latency to the first memory region MR1 or the second memory region MR3 having a relatively short latency. For example, the data access feature may indicate whether the data is data that should be immediately transferred in response to a request received from the host system <NUM>, data that is accessed by the host system <NUM> with high frequency, data that should not be lost even in situations such as SPO, or data that should be transferred securely against attack. In this way, by changing the memory region in which data is stored depending on the data access feature, the storage system <NUM> according to an embodiment may efficiently manage data, and thus overall performance may be improved.

Hereinafter, components included in the storage system <NUM> will be described.

<FIG> illustrates a host system <NUM>, according to an embodiment.

Referring to <FIG>, the host system <NUM> according to an embodiment includes a power supply <NUM> and a main board <NUM>. The power supply <NUM> generates power PWR from a power source and supplies the generated power PWR to the main board <NUM>. Alternatively, the power supply <NUM> may directly supply power to the backplane <NUM>.

The main board <NUM> may be referred to as a mother board or a base board, and includes a first processor <NUM>, a plurality of first memories 124a and 124b connected to the first processor <NUM>, a second processor <NUM>, a plurality of second memories 126a and 126b connected to the second processor <NUM>, and a Baseboard Management Controller (BMC) <NUM>.

The first processor <NUM> may use the plurality of first memories 124a and 124b as operation memories, and the second processor <NUM> may use the plurality of second memories 126a and 126b as operation memories. The first processor <NUM> and the second processor <NUM> may be configured to run an operating system and various applications.

For example, the first processor <NUM> and the second processor <NUM> may transmit information associated with the data access feature to the plurality of storage sets <NUM> through the backplane <NUM>. In this case, at least one storage set among the plurality of storage sets <NUM> may move data stored in the third memory region MR3 (refer to <FIG>) to the first memory region MR1 or the second memory region MR2, based on the data access feature. In addition, the first processor <NUM> and the second processor <NUM> may access the backplane <NUM> to control power management with respect to the plurality of storage sets <NUM>.

The first processor <NUM> and the second processor <NUM> may be central processing units (CPUs), and the plurality of first memories 124a and 124b and the plurality of second memories 126a and 126b may be a volatile memory such as a DRAM or an SRAM.

The BMC <NUM> may be a separate system from the first processor <NUM> and the second processor <NUM>, and may monitor physical states of components of the storage system <NUM>, including, for example, temperature, humidity, a voltage of the power supply <NUM>, a fan speed, communication parameters, or operating system functions. Alternatively, for example, the BMC <NUM> may offload power management operations to the battery module <NUM>.

<FIG> is a diagram illustrating an interface method between a host system <NUM> and a plurality of storage sets <NUM>, according to an embodiment.

Referring to <FIG>, the backplane <NUM> is connected to the host system <NUM> and each storage set <NUM> through a connection interface. The connection interfaces include, for example, any one of interfaces, or a combination thereof, such as a Peripheral Component Interconnect Express (PCIe), an Advanced Technology Attachment (ATA), a Serial ATA (SATA), a Parallel ATA (PATA), a Small Computer Systems Interface (SCSI), a serial attached SCSI (SAS), a Nonvolatile Memory Express (NVMe), a NVMe-over-fabric (NVMeoF), an Advanced eXtensible Interface (AXI), an Ultra Path Interconnect (UPI), an Ethernet, a Transmission Control Protocol/Internet Protocol (TCP/IP), a remote direct memory access (RDMA), RDMA over Converged Ethernet (ROCE), a FibreChannel, an InfiniBand, an iWARP, a Memory Semantic Interface, a Memory Coherent Interface, a Compute Express Link (CXL), a CXL. mem, a CXL. cache, a Gen-Z, a Coherent Accelerator Processor Interface (CAPI), a Cache Coherent Interconnect for Accelerators (CCIX), a System Management (SM) Bus, a Universal Serial Bus (USB), an Multi-Media Card (MMC), an Enhanced Small Disk Interface (ESDI), or an Integrated Drive Electronics (IDE).

In an embodiment, the host system <NUM> and the plurality of storage sets <NUM> may be connected through two different interfaces. For example, at least one of the processors <NUM> and <NUM> of the host system <NUM> may be connected to the plurality of storage sets <NUM> through first and second interfaces, and the BMC <NUM> of the host system <NUM> may be connected to the plurality of storage sets <NUM> through a third interface. Hereinafter, for convenience of description, it is assumed that the CXL. mem interface is used as the first interface, the PCIe interface is used as the second interface, and the SM Bus is used as the third interface. However, this is an example, and the interfaces may be variously combined. For example, the CXL. io interface may be used instead of the PCIe interface, and the CXL. cache interface may be used instead of the CXL. mem interface. Alternatively, the CXL. mem interface and the CXL. cache interface may be used simultaneously.

As described above, the host system <NUM> and the plurality of storage sets <NUM> according to an embodiment may be connected to each other through a plurality of different interfaces. In this case, data transferred through the plurality of different interfaces may be stored in any one of the first to third memory regions MR1 to MR3 depending on the data access feature. For example, data transferred to the storage set 160a through the CXL. mem interface may be stored in any one of the first to third memory regions MR1 to MR3 depending on the data access feature, and data transferred to the storage set 160a through the PCIe interface may also be stored in any one of the first to third memory regions MR1 to MR3 depending on the data access feature. The operation of receiving data through the CXL. mem interface and the operation of receiving data through the PCIe interface may be performed at different times or simultaneously. In this way, by differentiating the memory region in which data is stored according to the data access feature, efficient data management is possible, and thus overall performance may be improved.

<FIG> illustrates a storage set, according to an embodiment. Hereinafter, for convenience of description, it is assumed that the CXL. mem, the PCIe, and the SM Bus are used as the first to third interfaces, respectively.

Referring to <FIG>, the storage set 160a may be connected to the host system <NUM> (refer to <FIG>) through a plurality of different connection interfaces (the CXL. mem, the PCIe, and the SM Bus). The storage set 160a includes a bridge module <NUM>, an accelerator <NUM>, a first memory region <NUM>, and a storage controller <NUM>, and the storage controller <NUM> includes a control block (e.g., controller) <NUM>, a second memory region <NUM>, a third memory region <NUM>, and a mapping table <NUM>.

The bridge module <NUM> may perform an interface operation between the host system <NUM> and the storage controller <NUM>. When information associated with the data access feature of data is received from the host system <NUM>, the bridge module <NUM> may transmit the information to the storage controller <NUM>. Alternatively, when information associated with the data access feature of data is received, the bridge module <NUM> may check whether the corresponding data is stored in the first memory region <NUM>.

The accelerator <NUM> may perform an acceleration function of assisting a calculation of the host system <NUM> by performing some calculations that would otherwise be performed by the host system <NUM>. For example, the accelerator <NUM> is connected to the storage controller <NUM>, may receive input data from the storage controller <NUM>, may perform a calculation on the input data to generate calculation data, and may store the generated calculation data into the first memory region MR1 or may transmit the generated calculation data to the storage controller <NUM>. The accelerator <NUM> may perform the above-described calculation operations in response to a command of the host system <NUM>.

The first memory region <NUM> may be referred to as a first buffer memory and may store immediately used data. For example, the first memory region <NUM> may store calculation data according to the calculation from the accelerator <NUM>. Alternatively, the first memory region <NUM> may store data to be returned relatively quickly among read-requested data from the host system <NUM>. Alternatively, the first memory region <NUM> may store data having a relatively high priority among pre-fetching-requested data from the host system <NUM>.

The first memory region <NUM> may be, for example, a volatile memory such as a DRAM or an SRAM.

The storage controller <NUM> may include an internal memory embedded in an electronic device. For example, the storage controller <NUM> may include a Solid State Drive (SSD), an embedded Universal Flash Storage (UFS) memory device, or an embedded Multi-Media Card (eMMC). In some embodiments, the storage controller <NUM> may be or may include an external memory removable from the electronic device. For example, the storage controller <NUM> may be or may include a UFS memory card, a Compact Flash (CF), a Secure Digital (SD), a MicroSecure Digital (Micro-SD), a Mini Secure Digital (Mini-SD), an extreme Digital (xD), or a memory stick.

The storage controller <NUM> may communicate with the host system <NUM> through a plurality of different interfaces (the CXL. mem, the PCIe, the SM Bus) described above. The storage controller <NUM> may receive a command (host command) from the host system <NUM> and may analyze the command to generate a command to control the accelerator <NUM>.

The storage controller <NUM> includes the control block <NUM>, the second memory region <NUM>, the third memory region <NUM>, and the mapping table <NUM>.

The control block <NUM> may generate input data required to perform an operation requested by the host system <NUM> based on a command. Alternatively, the control block <NUM> may read data from the second memory region <NUM> or the third memory region <NUM> in response to a request from the host system <NUM>. Also, the control block <NUM> may receive information associated with the data access feature of data from the bridge module <NUM>. The control block <NUM> may check whether corresponding data is stored in the second memory region <NUM> or the third memory region <NUM>.

The second memory region <NUM> may be referred to as a second buffer memory and may store frequently used data. Alternatively, the second memory region <NUM> may store data to be returned relatively slowly among read-requested data from the host system <NUM>. Alternatively, the second memory region <NUM> may store data having a relatively low priority among pre-fetching-requested data from the host system <NUM>. For example, the second memory region <NUM> may be a volatile memory such as a DRAM or an SRAM.

The third memory region <NUM> is a nonvolatile memory and may store important data. For example, the third memory region <NUM> may be a nonvolatile memory such as a NAND flash memory.

The mapping table <NUM> may manage an address ADDR with regard to data stored in the third memory region <NUM> that is a nonvolatile memory. For example, the mapping table <NUM> may manage an address such as a logical address (LA) or a physical address (PA) of data stored in the third memory region <NUM>. In this case, the control block <NUM> may check whether data requested by the host system <NUM> is stored in the third memory region MR3 through the mapping table <NUM>. However, this is illustrative, and the mapping table <NUM> may also manage addresses for data stored in the first memory region <NUM> and/or the second memory region <NUM>, which are volatile memories.

According to an embodiment, the storage controller <NUM> may store data in any one of the first to third memory regions MR1 to MR3, based on the data access feature. Alternatively, the storage controller <NUM> may move data stored in any one of the first to third memory regions MR1 to MR3 to another memory region based on the data access feature. For example, the storage controller <NUM> may move data stored in the first memory region MR1 to the second memory region MR2 or the third memory region MR3 based on the data access feature. For example, the storage controller <NUM> may move data stored in the second memory region MR2 to the first memory region MR1 or the third memory region MR3 based on the data access feature. For example, the storage controller <NUM> may move data stored in the third memory region MR3 to the first memory region MR1 or the second memory region MR2 based on the data access feature. In this way, by changing the memory region in which data is stored depending on the data access feature, overall system performance may be improved.

<FIG> is a flowchart illustrating an example of an operation of the storage system 100A, according to an embodiment.

In operation S1100, the storage set 160a may receive information associated with the data access feature from the host system <NUM>. For example, the storage set 160a may receive information associated with the data access feature through at least one of the first to third interfaces.

In operation S1200, the storage set 160a may classify data as data corresponding to one of the first to third memory regions MR1 to MR3 based on the data access feature. For example, the storage set 160a may classify data to be immediately returned to the host system <NUM> as those corresponding to the first memory region MR1, may classify frequently used data as those corresponding to the second memory region MR2, and may classify important data as those corresponding to the third memory region MR3.

In operation S1300, the storage set 160a may check whether the classified data is stored in the corresponding memory region. For example, the storage set 160a may check whether data classified as corresponding to the first memory region MR1 is actually stored in the first memory region MR1.

In operation S1400, the storage set 160a may determine whether data movement is necessary based on whether the memory region to which the data corresponds and the memory region in which the data is actually stored match each other.

When the corresponding memory region and the stored memory region do not match, the storage set 160a may move the corresponding data to the corresponding memory region (operation S1500). For example, when immediately used data corresponding to the first memory region MR1 is stored in the third memory region MR3, the storage set 160a may cache or pre-fetch the corresponding data into the first memory region MR1.

When the corresponding memory region and the stored memory region match each other, the storage set 160a may continue to store the corresponding data in the corresponding memory region. In this regard, the operation of moving the data may be omitted when the corresponding memory region and the stored memory region match each other.

In this way, the overall performance of the storage system 100A may be improved by changing the memory region in which the data is to be stored depending on the access feature of the data.

<FIG> is a flowchart illustrating an example of an operation of the storage system 100A, according to an embodiment. For convenience of description, it is assumed that the data access feature of data received from the host system <NUM> in <FIG> is associated with frequently used data, and the corresponding data is classified as data corresponding to the second memory region MR2.

In operation S100, the host system <NUM> may analyze the data access feature of data received by the host system <NUM>.

In operation S110, the host system <NUM> may transmit information associated with the data access feature to the storage set 160a. For example, the host system <NUM> may transmit information associated with the data access feature using any one of the CXL. mem interface protocol, the PCIe interface protocol, or the SM Bus interface protocol. In an embodiment, the host system <NUM> may transmit information associated with the data access feature together with a command. For example, the command may be a pre-fetching command or a caching command. However, this is an example, and the command may be a lead command.

In operation S120, the storage set 160a may classify corresponding data as those corresponding to the second memory region MR2, based on information associated with the data access feature.

In operation S130, the storage set 160a may check whether corresponding data is stored in the second memory region MR2. When the corresponding data is not stored in the second memory region MR2, operation S140 may be performed. When the corresponding data is stored in the second memory region MR2, the storage set 160a may return a response, in operation S180, indicating that the operating is complete.

In operation S140, the storage set 160a may check whether corresponding data is stored in the third memory region MR3. For example, the storage set 160a may check whether corresponding data is stored in the third memory region MR3 by referring to the mapping table <NUM>.

When the corresponding data is stored in the third memory region MR3, operation S150 may be performed. In operation S150, the storage set 160a may move the data stored in the third memory region MR3 to the second memory region MR2. Then, in operation S180, the storage set 160a may return a response to the host system <NUM> indicating that the operating is complete.

When the corresponding data is not stored in the third memory region MR3, operation S160 may be performed. In operation S160, the storage set 160a may check whether corresponding data is stored in the first memory region MR1.

When the corresponding data is stored in the first memory region MR1, operation S170 may be performed. In operation S170, the storage set 160a may move the data stored in the first memory region MR1 to the second memory region MR2. Thereafter, in operation S180, the storage set 160a may transmit a response to the host system <NUM> indicating that the operating is complete.

When the corresponding data is not stored in the first memory region MR1, the storage set 160a may return a false response, in operation S190.

As described above, the storage system 100A according to an embodiment may efficiently manage data by differentiating the memory region in which data is to be stored depending on the data access feature, thereby improving overall performance of the storage system.

In <FIG>, for convenience of description, it is assumed that the data access feature corresponds to the second memory region MR2. However, this is only illustrative, and even when the data access feature corresponds to the first memory region MR1 or the third memory region MR3, the storage system 100A may operate in the same manner or similar manner as in <FIG>.

In <FIG>, it has been described that data access feature is analyzed by the host system <NUM> and the host system <NUM> transmits the analyzed data access feature to the storage set 160a. However, this is only illustrative, and embodiments are not limited thereto. For example, the data access feature may be identified by the storage set 160a. This will be described in more detail below.

<FIG> illustrates a storage set 160a_1, according to an embodiment. The storage set 160a_1 of <FIG> is similar to the storage set 160a of <FIG> therefore, the same or similar components are denoted using the same or similar reference numerals, and additional descriptions will be omitted to avoid redundancy.

Referring to <FIG>, the storage set 160a_1 according to an embodiment further includes a data pattern analyzer <NUM> compared to the storage set 160a of <FIG>.

The data pattern analyzer <NUM> may analyze an access pattern of data received by the host system <NUM> (refer to <FIG>). For example, the data pattern analyzer <NUM> may analyze the data access pattern based on data call frequency, importance, security level, etc., and may extract the data access feature therefrom.

The storage set 160a_1 according to an embodiment may analyze the pattern of received data and may extract the data access feature based on the pattern analysis result. The storage set 160a_1 may store data in any one of the first to third memory regions MR1 to MR3 based on the extracted data access feature, or may move previously stored data from one memory region to another memory region. Accordingly, efficient data management is possible, and overall performance may be improved.

<FIG> is a flowchart illustrating an example of an operation of the storage set 160a_1 of <FIG>.

In operation S2100, the storage set 160a_1 may analyze the access pattern associated with data. For example, the storage set 160a_1 may analyze the data access pattern based on data call frequency, importance, security level, etc., and may extract the data access feature therefrom.

In operation S2200, the storage set 160a_1 may classify data as data corresponding to one of the first to third memory regions MR1 to MR3 based on the data access feature.

In operation S2300, the storage set 160a_1 may check whether the classified data is stored in the corresponding memory region.

In operation S2400, the storage set 160a_1 may determine whether data movement is necessary based on whether the memory region to which the data corresponds and the memory region in which the data is actually stored match each other.

When the corresponding memory region and the stored memory region do not match, the storage set 160a_1 may move the corresponding data to the corresponding memory region (operation S2500). When the corresponding memory region and the stored memory region match each other, the storage set 160a_1 may continue to store the corresponding data in the corresponding memory region.

The storage set 160a_1 according to an embodiment may analyze the pattern of received data and may extract the data access feature based on the pattern analysis result. In addition, the storage set 160a_1 may change the memory region in which data is to be stored depending on the data access feature. Accordingly, overall system performance may be improved.

<FIG> illustrates a storage set 160a_2, according to an embodiment. The storage set 160a_2 of <FIG> is similar to the storage set 160a_1 of <FIG> therefore, the same or similar components are denoted using the same or similar reference numerals, and additional descriptions will be omitted to avoid redundancy.

Referring to <FIG>, the storage set 160a_2 according to an embodiment further includes a pre-fetching order scheduler <NUM> compared to the storage set 160a_1 of <FIG>.

The pre-fetching order scheduler <NUM> monitors information associated with an operation state of the storage set 160a_2. In this case, the information associated with the operation state includes information associated with the operation state affecting the latency of the third memory region <NUM>, which is a nonvolatile memory. For example, the information associated with the operation state may include information associated with a garbage collection, a wear leveling, a depth of an ECC protection code, etc. In addition, the information associated with the operation state may include whether the requested data is stored in a Single Level Cell (SLC) method or a Multi-Level Cell (MLC) method.

For example, when an operation with a long latency such as a garbage collection (GC) is being performed or is scheduled to be performed in a memory block corresponding to pre-fetching-requested data, the order of the corresponding pre-fetch operation may be adjusted to be performed later than one or more other pre-fetch operations.

In this way, overall system performance may be further improved by considering not only the data access feature but also information on the operation state that affects the latency.

<FIG> is a flowchart illustrating an example of an operation of the storage set 160a_2 of <FIG>.

In operation S3100, the storage set 160a_2 may analyze the access pattern associated with data. For example, the storage set 160a_2 may analyze the data access pattern based on data call frequency, importance, security level, etc., and may extract the data access feature therefrom.

In operation S3200, the storage set 160a_2 may classify data as data corresponding to one of the first to third memory regions MR1 to MR3 based on the data access feature.

In operation S3300, the storage set 160a_2 may check whether the classified data is stored in the corresponding memory region.

In operation S3400, the storage set 160a_2 may determine whether data movement is necessary based on whether the memory region to which the data corresponds and the memory region in which the data is actually stored match each other.

When the corresponding memory region and the stored memory region match each other, the storage set 160a_2 may continue to store the corresponding data in the corresponding memory region, and operations S3500, S3600 and S3700 may be omitted. When the corresponding memory region and the stored memory region do not match, operation S3500 may be performed.

In operation S3500, the storage set 160a_2 may check the operation state of the third memory region <NUM>, which is a nonvolatile memory. For example, the storage set 160a_2 may check whether a garbage collection, a wear leveling, ECC protection codes, etc. are being performed in the third memory region <NUM>. Alternatively, the storage set 160a_2 may check whether the requested data is stored in an SLC or an MLC method.

In operation S3600, the storage set 160a_2 may re-schedule the pre-fetching order based on the data access pattern and/or the operation state of the nonvolatile memory.

In operation S3700, the storage set 160a_2 may move data to a corresponding memory region according to the adjusted pre-fetching order.

For convenience of description, it is assumed that a first pre-fetching command (<NUM>st pre-fetching CMD) and a second pre-fetching command (<NUM>nd pre-fetching CMD) are sequentially received to the storage set 160a_2. Also, it is assumed that data corresponding to the first and second pre-fetching commands are frequently used data and corresponds to the second memory region <NUM> but is stored in the third memory region <NUM>.

In an embodiment, a garbage collection operation may be being performed on a memory block corresponding to the first pre-fetching command among memory blocks of the third memory region <NUM>. In this case, the storage set 160a_2 may adjust the pre-fetching order such that the pre-fetching operation corresponding to the second pre-fetching command is performed before the pre-fetching operation corresponding to the first pre-fetching command. In detail, the storage set 160a_2 first may pre-fetch data corresponding to the second pre-fetching command from the third memory region <NUM> to the second memory region <NUM>, and may pre-fetch data corresponding to the first pre-fetching command from the third memory region <NUM> to the second memory region <NUM> after the garbage collection operation is completed.

In an embodiment, a high-level ECC protection code is applied to a memory block corresponding to the first pre-fetching command among memory blocks of the third memory region <NUM>, and a low-level ECC protection code is applied to a memory block corresponding to the second pre-fetching command among memory blocks of the third memory region <NUM>. In this case, the storage set 160a_2 may adjust the pre-fetching order such that the pre-fetching operation corresponding to the second pre-fetching command is performed before the pre-fetching operation corresponding to the first pre-fetching command. That is, the storage set 160a_2 may delay a pre-fetching operation of data corresponding to the first pre-fetching command, which requires a long latency, and may first perform a pre-fetching operation of data corresponding to the second pre-fetching command.

In this way, overall system performance may be further improved by considering not only the data access feature but also information on the operation state of the nonvolatile memory that affects the latency.

<FIG> is a diagram illustrating a storage set 160a_3, according to an embodiment. The storage set 160a_3 of <FIG> is similar to the storage set 160a of <FIG> therefore, the same or similar components are denoted using the same or similar reference numerals, and additional descriptions will be omitted to avoid redundancy.

In <FIG>, it has been described that the control block <NUM>, the second memory region <NUM>, and the third memory region <NUM> are implemented as one storage controller <NUM>. However, this is only illustrative, and the present disclosure is not limited thereto. For example, as illustrated in <FIG>, the control block <NUM> and the bridge module <NUM> may be implemented as one storage controller 170_1. However, this is just an example, and the control block <NUM>, the second memory region <NUM>, and the third memory region <NUM> may be implemented as separate chips.

<FIG> illustrates a storage system 100B, according to an embodiment. The storage system 100B of <FIG> is similar to the storage system 100A of <FIG>. Therefore, the same or similar components are denoted using the same or similar reference numerals, and additional descriptions will be omitted to avoid redundancy.

Unlike the storage system 100A of <FIG>, the storage system 100B of <FIG> may not include a backplane. In detail, the storage system 100B of <FIG> includes the host system <NUM> and the storage set <NUM>, and the host system <NUM> and the storage set <NUM> may be connected through first to third interfaces.

Also, in some embodiments, the storage system 100B may not include the battery module <NUM>. In this case, when the main power decreases below the stored level, the storage system 100B may receive power from an external power source.

According to an embodiment, a storage system caches or pre-fetches data in different memory regions based on data access features. Accordingly, data may be efficiently managed, and performance of the storage system may be improved.

Claim 1:
A storage system comprising:
a host system (100A); and
a plurality of storage sets (<NUM>) configured to interface through two different protocols with the host system, and
wherein at least one of the plurality of storage sets comprises:
a first memory region (MR1) comprising a volatile memory;
a second memory region (MR2) comprising a volatile memory; and
a third memory region (MR3) comprising a nonvolatile memory, and
wherein:
the at least one of the plurality of storage sets is configured to move data stored in the third memory region to a selected memory region among the first memory region and the second memory region based on a data access feature; and
the at least one of the plurality of storage sets is further configured to adjust an execution order of pre-fetching commands received from the host system to pre-fetch data stored in the third memory region based on an operation state affecting the latency of of the third memory region.