Patent Description:
In many radio frequency (RF) systems, such as portable wireless devices designed to operate in LTE or <NUM> based cellular systems, a wide variety circuits and systems are used to implement RF and baseband functions. For example, most systems include an RF downconverter that downconverts RF signals received from an antenna to baseband and/or to an intermediate frequency signals, an analog-to-digital converter (ADC) that digitizes the downconvertered RF signals, a processor that performs computation and processing on the digitized signals, a digital-to-analog converter (DAC) that generates baseband or intermediate signals for transmission, an RF upconverter that upconverts the baseband or intermediate signals to an RF frequency for transmission over an antenna. In addition to the requisite signal path circuity, such as amplifiers, mixers, filters, and data conversion circuits and processing circuits used to implement these functions, each of these functions may require clock signals or oscillator signals for operation. For example, the RF downconverters and RF upconverters generally utilize RF local oscillator (LO) signals, and the ADC, DAC and processor utilize digital clock signals. Accordingly, such RF systems additionally include frequency generation circuitry to support RF, baseband and processing functionality.

Many RF systems use frequency generation systems in which one the frequency of one or more voltage-controlled oscillators (VCOs) is referenced to the frequency of a crystal oscillator using one or more phase-locked loop (PLL) circuits. One or more additional PLLs or delay locked loops (DLLs) may also be used to generate high frequency clocks for the digital processor and/or the data converters. In some cases, these clock and oscillator signals may have performance requirements governing phase noise and duty cycle. Designing frequency generation systems in portable devices that are configured to generate such a multiplicity of clock signals that meet performance requirements in a cost effective manner presents a number of challenges and trade-offs with respect to board space, component cost and power consumption. Publications <CIT>, <CIT> and <NPL> relate to duty cycle adjustments in frequency doublers or multipliers.

There may be a demand for providing an improved concept for providing a method, a system and an RF system.

Such a demand may be satisfied by the subject matter of any of the claims. In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency;using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, comprising: generating a digitized second clock signal; transforming the digitized second clock signal from a time domain to a frequency domain to form a frequency domain second clock signal, measuring a difference between a first frequency bin of the frequency domain second clock signal corresponding to a frequency of the second clock signal and at least one second frequency bin of the frequency domain second clock signal to form the measured duty cycle parameter; using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the duty cycle parameter.

In accordance with another embodiment, a system includes: an adjustable frequency doubling circuit comprising a clock input, a clock output and a duty cycle adjustment input, the adjustable frequency doubling circuit configured to receive a first clock signal having a first clock frequency at the clock input, generate a second clock signal having a second clock frequency that is twice the first clock frequency at the clock output, and adjust a duty cycle of the first clock signal or the second clock signal based on a duty cycle adjustment signal received at the duty cycle adjustment input; a duty cycle measurement and adjustment circuit comprising: an analog-to-digital converter, ADC, having an ADC signal input coupled to the clock output of the adjustable frequency doubling circuit and an ADC signal output configured to provide a digitized second clock signal; and a processor coupled to the ADC signal output of the ADC, the processor configured to:transform the digitized second clock signal from a time domain to a frequency domain to form a frequency domain second clock signal, measure a difference between a first frequency bin of the frequency domain second clock signal corresponding to a frequency of the second clock signal and at least one second frequency bin of the frequency domain second clock signal to form the measured duty cycle parameter, and generate the duty cycle adjustment signal based on the measured duty cycle parameter.

In accordance with a further embodiment, an RF system includes: an RF front-end having an input port configured to be coupled to an antenna; a test tone generation circuit;a multiplexer having a first input coupled to an output of the RF front-end, and a second input coupled to an output of the test tone generation circuit; an adjustable frequency doubling circuit comprising a clock input, a clock output and a duty cycle adjustment input, the adjustable frequency doubling circuit configured to receive a first clock signal having a first clock frequency at the clock input, generate a second clock signal having a second clock frequency that is twice the first clock frequency at the clock output, and adjust a duty cycle of the first clock signal or the second clock signal based on a duty cycle adjustment signal received at the duty cycle adjustment input; and a duty cycle measurement and adjustment circuit comprising: an analog-to-digital converter, ADC, having a clock input coupled to the clock output of the adjustable frequency doubling circuit, an ADC signal input coupled to an output of the multiplexer and an ADC signal output configured to provide a digitized second clock signal; and a processor coupled to the ADC signal output of the ADC, the processor configured to: transform the digitized second clock signal from a time domain to a frequency domain to form a frequency domain second clock signal, measure a difference between a first frequency bin of the frequency domain second clock signal corresponding to a frequency of the second clock signal and at least one second frequency bin of the frequency domain second clock signal to form the measured duty cycle parameter, and generate the duty cycle adjustment signal based on the measured duty cycle parameter.

To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferred embodiments in a specific context, a system and method for calibrating a frequency doubler used in a radio transceiver.

In various embodiments, the frequency of an input clock signal is doubled using an adjustable clock doubling circuit configured to provide a clock signal having an adjustable duty cycle. By calibrating the doubled clock signal to have a duty cycle that is substantially <NUM>% by adjusting the duty cycle of the doubled clock signal, the doubled clock signal can be used to clock duty cycle sensitive circuitry such as an ADC or a phase-locked loop circuit. In some embodiments, the duty cycle is calibrated by providing a test tone, such as an analog test tone, to the ADC, monitoring the spurious response of the ADC converter, and iteratively adjusting the duty cycle of the clock doubling circuit to reduce or minimize the spurious response of the ADC converter. In other embodiments, the doubled clock signal may be directly monitored during calibration to determine and calibrate the duty cycle of the doubled clock signal.

Alternatively or in addition to adjusting the duty cycle of the double clock signal, the duty cycle of the input clock signal may be adjusted prior to the input clock signal being doubled. In various cases, the presence of a duty cycle error on the input clock signal may cause a periods of alternating duration on the doubled clock signal. These periods of alternating duration may cause spurious behavior when used as input to circuits that are sensitive to such errors on doubled clock signals. Circuits that exhibit such sensitivity include, for example, ADCs that use an odd number of clock cycles for each conversion. Thus, in various embodiments, the duty cycle of the input clock signal may be adjusted or calibrated to be substantially <NUM>% prior to the input clock signal being doubled, thereby advantageously reducing the spurious behavior of data converters and other circuitry.

In some portable wireless systems, the clock frequencies needed to clock data converters and phase-locked loop (PLL) circuits may be higher than clock frequencies routinely used to clock digital processing circuits. For example, in some systems, <NUM> crystals are routinely used to generate clock signals for application processors, while higher clock frequencies in the neighborhood of <NUM> may be used to clock analog-to-digital converters and PLL circuits. In some systems, because of the relatively large size of oscillator crystals and the limited amount of board space available in compact portable wireless devices, the higher clock frequency used to provide clock signals to data converters and PLL circuits is often derived using frequency multiplication circuitry such as a delay locked loop (DLL), an additional PLL, or a delay-based frequency multiplication circuit. While delay-based frequency multiplication circuits may be physically compact and consume relatively low power, some frequency multiplication circuits may be sensitive to duty cycle errors in the clock signal produced by the crystal oscillator and may be additionally prone to produce frequency multiplied clock signals having duty cycles that deviate from <NUM>%. In some cases, these duty cycle errors may degrade the performance of duty cycle sensitive circuitry that is referenced to the multiplied clock signal.

For example, in an analog-to-digital converter that utilizes both edges of a system clock to perform sampling and other operations, clock asymmetries may lead to spurious behavior and reduced spurious-free dynamic range (SFDR). Errors in the duty cycle of the clock may translate into a frequency error that creates in a jump between two frequencies. In addition, charge pump circuits that rely on both edges of the clock may encounter operational difficulty as the duty cycle of the clock deviates from <NUM>%. In an analog-to-digital converter that utilizes an odd number of system clocks to perform an conversion, periodic variation in the length of the clock period of the system clock caused by duty cycle asymmetries of the input clock to a frequency doubler may also lead to spurious behavior and reduced spurious-free dynamic range (SFDR).

Thus, in embodiments of the present invention, a calibrated frequency doubler is used to provide a clock having a duty cycle substantially equal to <NUM>% and/or provide a clock that has substantially equal consecutive clock periods, while advantageously benefiting from the small size and power savings provided by delay-based frequency doubler circuits.

<FIG> illustrates an embodiment frequency doubler system <NUM>. As shown, system <NUM> includes frequency doubler <NUM>, duty cycle sensitive circuitry <NUM>, and a duty cycle measurement and adjustment circuit <NUM>. Duty cycle sensitive system circuitry <NUM> may include, for example, analog-to-digital converters, duty cycle sensitive voltage boosting circuits such as charge pumps, and/or other circuitry such as PLLs and timing sensitive digital circuits that are sensitive to the duty cycle of its input clock or is sensitive to clock period variations caused by duty cycle errors in a pre-doubled clock. Frequency doubler circuit <NUM> (also referred to as an "adjustable frequency doubling circuit") is configured to double the frequency of first clock signal Clk1x coupled to a clock input of frequency doubler circuit <NUM> and form second clock signal Clk2x. For example, if first clock signal Clk1x has a clock frequency of <NUM>, second clock signal Clk2x would have a clock frequency of <NUM>. It should be understood, however, that first clock signal Clk1x and second clock signal Clk2x could be any frequency depending on the particular application and its specifications.

As shown, frequency doubler circuit <NUM> include a duty cycle adjustment input, such that duty cycle adjustment signal DutyAdj is used to adjust the duty cycle of first clock signal Clk1x and/or the duty cycle of second clock signal Clk2x. Duty cycle adjustment signal DutyAdj may be implemented as an analog signal or a digital signal comprising one or more bits. In various embodiments, frequency doubler circuit <NUM> is implemented using a frequency doubling circuit known in the art. For example, frequency doubler circuit <NUM> may be implemented using an exclusive or gate and an adjustable delay circuit as explained below. However, in alternative embodiments, other frequency doubling circuits may be used.

Duty cycle measurement and adjustment circuit <NUM> may be used to directly or indirectly measure the duty cycle of first clock signal Clk1x and/or second clock Clk2x and provide duty cycle adjustment signal DutyAdj in response to these measurements. The measured duty cycle or the measured value related to the duty cycle may also be referred to as a duty cycle parameter. In some embodiments duty cycle measurement and adjustment circuit <NUM> is operational only during a calibration time period, such as during a calibration mode. During periods of normal operation, duty cycle measurement and adjustment circuit <NUM> may be inactive or powered down. In other embodiments, duty cycle measurement and adjustment circuit <NUM> may only be operational during manufacturing and/or testing of the particular part. In such cases, all or part of duty cycle measurement and adjustment circuit <NUM> may reside on test fixture that is separate from the remaining portion of the circuit that includes frequency doubler circuit <NUM> and duty cycle sensitive system circuitry <NUM>. For example, frequency doubler <NUM> may be calibrated by duty cycle measurement and adjustment circuit <NUM> during a wafer or production test of an integrated circuit that includes duty cycle sensitive system circuitry <NUM>. In other embodiments, duty cycle measurement and adjustment circuit <NUM> may be resident on the same integrated circuit or the same system as frequency doubler circuit <NUM> and duty cycle sensitive system circuitry <NUM>. In yet other embodiments duty cycle measurement and adjustments circuit <NUM> may continuously monitor second clock signal Clk2x and provide for a continuous adjustment of the duty cycle of first clock signal Clk1x and/or second clock signal Clk2x produced by frequency doubler circuit <NUM>.

Duty cycle measurement and adjustment circuit <NUM> may be implemented, for example, using duty cycle measurement circuits known in the art including but not limited to high-speed counters, mixers, and analog-to-digital converters. In addition, duty cycle measurement and adjustment circuit <NUM> may include digital circuitry such as state machine and/or processing circuits that assist in the measurement of the duty cycle and in the formation of duty cycle adjustment signal DutyAdj.

<FIG> illustrates frequency doubler system <NUM> according to an alternative embodiment of the present invention. As shown, frequency doubler system <NUM> includes a duty cycle sensitive analog-to-digital converter <NUM> whose input ADCIN (also referred to as an "ADC signal input") is selectively coupled to system circuitry <NUM> or test tone generator <NUM> (also referred to as a "test tone generation circuit"). During normal operation of system <NUM>, system circuitry <NUM> provides an analog signal at input ADCIN of duty cycle sensitive analog-to-digital converter <NUM> via selection switch <NUM>. As shown, duty cycle sensitive analog-to-digital converter <NUM> is coupled to second clock signal Clk2x, which provides a clock signal to duty cycle sensitive analog-to-digital converter <NUM> at a clock input, such that second clock signal Clk2x clocks duty cycle sensitive analog-to-digital converter <NUM> during operation. System circuitry <NUM> may include any system circuitry that produces an analog signal utilized by system <NUM>. For example, in RF systems, system circuitry <NUM> may include an RF front end and/or a down converter that produces an analog signal that is related to a received RF signal. In other systems, system circuitry <NUM> may generate other types of analog signals including, but not limited to audio signals, sensor signals, image signals, video signals and the like.

Duty cycle sensitive analog-to-digital converter <NUM> converts the analog signal at input ADCIN to digital signal ADCOUT (also referred to as an "ADC signal output") at the output of duty cycle sensitive analog-to-digital converter <NUM>. Duty cycle sensitive analog-to-digital converter <NUM> may implemented using a variety of analog-to-digital converter architectures including, but not limited to, successive approximation converters Sigma Delta converters, flash converters pipeline converters, and other data converter architectures known in the art. During calibration, test tone generator <NUM> provides a test tone to duty cycle sensitive analog-to-digital converter <NUM>, which is analyzed by duty cycle analysis and adjustment circuit <NUM>. In some embodiments, the combination of duty-cycle sensitive analog-to-digital converter <NUM> and duty cycle analysis and adjustment circuit <NUM> may also be referred to as a duty cycle measurement and adjustment circuit. Test tone generator <NUM> may be implemented, for example, using a digital frequency divider and a low pass filter. Other test tone generation circuits known in the art may also be used.

Duty cycle analysis and adjustment circuit <NUM> is configured to analyze the spurious behavior of digital signal ADCOUT and adjust the duty cycle a frequency doubler circuit <NUM> using duty cycle adjustment signal DutyAdj. In some embodiments, duty cycle analysis and adjustment circuit <NUM> iteratively adjusts duty cycle adjustment signal DutyAdj until the spurious response of digital signal ADCOUT meets a predetermined performance requirement and/or a predetermined threshold requirement. In some embodiments, duty cycle analysis and adjustment circuit <NUM> may reside on the same system integrated circuit, circuit board, and/or housing as system circuitry <NUM>, test tone generator <NUM>, duty cycle sensitive analog-to-digital converter <NUM> and frequency doubler circuit <NUM>. In other embodiments, duty cycle analysis and adjustment circuit <NUM> may reside on a separate test fixture used during manufacturing testing and/or calibration of system <NUM>. Duty cycle analysis and adjustment circuit <NUM> may include, for example, a microprocessor, digital signal processing circuitry, dedicated logic, or other circuitry suitable for determining the spurious response of digital signal ADCOUT according to systems and methods explained further below.

In some embodiments, test controller <NUM> may be used to configure frequency doubler system <NUM> to perform a calibration of frequency doubler circuit <NUM>. For example, during calibration, test controller <NUM> may control switch <NUM> to route the output of test tone generator <NUM> to the input of duty cycle sensitive analog-to-digital converter <NUM>. In some embodiments, calibration may occur during a calibration test time or during a calibration mode. Test controller <NUM> may also initiate the measurement of digital signal ADCOUT by duty cycle analysis and adjustment circuit <NUM>, initiate the adjustment of the duty cycle of frequency doubler circuit <NUM>, and activate test tone generator <NUM> during duty cycle calibration of frequency doubler circuit <NUM>. In various embodiments, test controller <NUM> or portions of test controller <NUM> may reside on the same system integrated circuit, circuit board, and/or housing as system circuitry <NUM>, test tone generator <NUM>, duty cycle sensitive analog-to-digital converter <NUM> and frequency doubler circuit <NUM>. In other embodiments, of test controller <NUM> or portions of test controller <NUM> may reside on a separate test fixture used during manufacturing testing and/or calibration of system <NUM>.

<FIG> illustrate waveform diagrams pertaining to embodiments of the present invention. Referring to <FIG>, three waveform diagrams are shown. The first waveform diagram shows first clock signal Clkix, which represents the clock signal presented to the input of frequency doubler circuit <NUM>; the second diagram shows second clock signal Clk2x output from frequency doubler circuit <NUM> having a non-<NUM>% duty cycle; and the third diagram shows second clock signal Clk2x having a <NUM>% duty cycle. As shown, second clock signal Clk2x has a high value for a time period of tH, and a low value for a time period of tL. For non-<NUM>% duty cycles, time periods tH and tL, are not equal. In the illustrated example, time period tH is shown to be shorter than time period tL. However, in other situations in which second clock signal Clk2x has a non-<NUM>% duty cycle, time period tH could be longer than time period tL. When the duty cycle of second clock signal Clk2x is substantially <NUM>%, time period tH is substantially equal to time period tL. In various embodiments, the duty cycle of second clock signal Clk2x is adjusted until the duty cycle is substantially <NUM>%. In some embodiments, the duty cycle of second clock signal Clk2x is considered to be substantially <NUM>% when a measured duty cycle parameter is within a predetermined range and/or the duty cycle is adjusted to have an acceptable quality measure.

<FIG> illustrates a waveform diagram showing first clock signal Clk1x having a non-<NUM>% duty cycle, and a resulting second clock signal Clk2x having varying time periods. As shown, first clock signal has a high value for a time period tH and a low value for a time period tL, where time period tH is not equal to time period tL, The resulting doubled second clock signal Clk2x has a time periods of alternating duration. For example, in the time period corresponding to time tH of first clock signal Clkix, second clock signal Clk2x has a clock period of tP1. However, in the time period corresponding to time tL of first clock signal Clkix, second clock signal Clk2x has a clock period of tP2, where time period tp1 is not equal to time period tp2. These time periods tP1and tP2 alternate with respect to each other. Thus, as the duty cycle of first clock signal Clk1x approaches <NUM>%, the variation between clock periods tP1 and tP2 of second clock signal is reduced.

In various embodiments, the duty cycle of first clock signal Clk2x is adjusted until the length of consecutive clock periods tH and tL have a substantially equal lengths. In some embodiments, the length of consecutive clock periods tH and tL are considered to have substantially equal lengths when a measured duty cycle parameter is within a predetermined range and/or the duty cycle of the first clock signal Clk1x is adjusted to have an acceptable quality measure.

<FIG> illustrates a diagram of the output spectrum of duty cycle sensitive analog-to-digital converter <NUM> when being presented with a <NUM> test tone from test tone generator <NUM> at input ADCIN and when being clocked by second clock signal Clk2x having a non-<NUM>% duty cycle. The diagram of <FIG> was generated using a fast Fourier transform (FFT). The peak of the spectrum at point <NUM> represents the <NUM> test tone, while the peak at point <NUM> represents a frequency spur at <NUM> caused by the non-<NUM>% duty cycle of second clock signal Clk2x.

The specific example shown in <FIG> represents a case in which the duration of the sampling intervals of duty cycle sensitive analog-to-digital converter <NUM> alternate due to the asymmetric nature of the non-<NUM>% duty cycle. For example, during operation, a short sampling intervals and long sampling intervals alternate with each other. This alternation in sampling intervals effectively causes a tone at one-half of the sampling frequency fs. This tone mixes with the input tone to cause a spur at: <MAT> where fspur is the spur frequency and fin is the frequency of the tone generated by test tone generator <NUM>. In the illustrated case where the sampling frequency is <NUM> and the input tone is <NUM>, the expected spur is at <NUM>. It should be understood that the above equation assumes that the duration of the sampling intervals alternate at each sampling interval. In alternative embodiments of the invention where duty cycle sensitive analog-to-digital converter <NUM> is not clocked at every cycle of second clock signal Clk2x, the frequency of the spur may be different from fs/<NUM> - fin, depending on the particular clocking scheme of the ADC.

<FIG> illustrates a graph of spurious free dynamic range with respect to duty cycle for various frequencies. Curve <NUM> represents an input frequency of <NUM>, curve <NUM> represents an input frequency of <NUM>, curve <NUM> illustrates an input frequency of <NUM>, curve <NUM> represents an input frequency of <NUM>, and curve <NUM> represents an input frequency of <NUM>. As can be seen by the graph of <FIG>, the spurious free dynamic range of duty cycle sensitive analog-to-digital converter <NUM> degrades as the duty cycle of second clock signal Clk2x diverges from a <NUM>% duty cycle. For example, for a <NUM>% duty cycle, the spurious free dynamic range of duty cycle sensitive analog-to-digital converter <NUM> exceeds <NUM> dB. However, for a duty cycle of either <NUM>% or <NUM>%, the spurious free dynamic range of duty cycle sensitive analog-to-digital converter <NUM> is only about <NUM> dB. Furthermore, the spurious free dynamic range of duty cycle sensitive analog-to-digital converter <NUM> also degrades with increasing tone frequency. As shown the spurious free dynamic range with an input tone of <NUM> is about <NUM> dB while the spurious free dynamic range with an input tone of <NUM> is about <NUM> dB for duty cycle of <NUM>% or <NUM>%. It should be appreciated that the actual resulting spurious free dynamic range may vary depending on the particular architecture used, its architecture, its clocking speed, the amplitude of the input tone, and other factors. While the waveform diagrams of <FIG> illustrate an example of spurious performance in a system in which the duty cycle of second clock signal Clk2x is varied, similar comparative performance may be seen with respect to an analog-to-digital converter when the duty cycle of first clock signal Clk1x is varied, particularly with respect to analog-to-digital converters that are sensitive to alternating period lengths of second clock signal Clk2x caused by duty cycle errors in first clock signal Clk1x.

<FIG> illustrate schematics of frequency doubler circuit <NUM> in accordance with an embodiment of the present invention. <FIG> illustrates a top-level schematic of frequency doubler circuit <NUM>. As shown, frequency doubler circuit <NUM> includes duty cycle correction circuit <NUM>, adjustable delay circuit <NUM> and exclusive-or gate <NUM>. During operation, duty cycle correction circuit <NUM> corrects the duty cycle of first clock signal Clk1x and produces adjusted duty cycle clock signal ClkixC. By correcting errors in the duty cycle of first clock signal Clk1x prior to doubling its frequency, a more accurate doubled clock signal frequency may be produced as described above. However, in some embodiments, either duty cycle correction circuit <NUM> or adjustable delay circuit may be omitted in some embodiments. For example, in embodiments where first clock signal Clk1x already has a relatively accurate duty cycle, duty cycle correction circuit <NUM> may be omitted, whereas in embodiments in which clocked circuitry is insensitive to non-<NUM>% cycles, adjustable delay circuit <NUM> may be implemented using a fixed delay.

The actual doubling of the clock frequency is performed by adjustable delay circuit <NUM> and exclusive-or gate <NUM>. During operation, adjustable delay circuit <NUM> delays adjusted duty cycle clock signal ClkixC by a quarter of its clock cycle to form delayed first clock signal ClkixD. By performing an exclusive-or operation on adjusted duty cycle clock signal ClkixC and delayed first clock signal ClkixD, a clock signal having twice the frequency of first clock signal Clk1x is generated. By adjusting the delay of adjustable delay circuit <NUM>, the resulting duty cycle of second clock signal Clk2x can be adjusted. In various embodiments, the delay of adjustable delay circuit <NUM> is set by signal DutyAdj, which is provided to a control input of adjustable delay circuit <NUM>.

<FIG> illustrates a schematic of adjustable delay circuit <NUM> according to an embodiment of the present invention. As shown, adjustable delay circuit <NUM> includes a plurality of delay cells <NUM> coupled in series with each other. Delay cells <NUM> may also be referred to as selectable delay circuits. Multiplexer <NUM> selects the output of one delay cell <NUM> from among the plurality of delay cells <NUM> according to duty cycle adjustment signal DutyAdj. Thus, for a longer programmed delay, a delay cell <NUM> coupled near the end of the chain of delay cells may be selected; for a shorter programmed delay, a delay cell <NUM> coupled near the beginning of the chain of delay cells <NUM> may be selected. In various embodiments, adjustable delay circuit <NUM> may contain any number of delay cells <NUM>. The number of delay cells <NUM> and the amount of time delay that each delay cell <NUM> is capable of producing may vary depending on the particular an embodiment and its specifications. For example, systems having higher clock frequencies may require less delay and fewer delay cells than systems having lower clock frequencies.

<FIG> illustrate schematics of delay cells that may be used to implement delay cell <NUM> shown in <FIG>. The delay of <FIG> includes a buffer <NUM> loaded by a capacitor <NUM>. The amount of delay time implemented by the delay cell is a function of the strength of buffer <NUM> and the size of capacitor <NUM>. For example, when the strength of buffer <NUM> is weak and the size of capacitor <NUM> is large, delay cell <NUM> may produce a longer delay. On the other hand, when buffer <NUM> has a strong output and the size of capacitor <NUM> is small, delay cell <NUM> may produce a shorter delay. In various embodiments, buffer <NUM> may be implemented using digital buffer circuitry known in the art. For example, buffer <NUM> may be implemented using two inverters coupled in series with each other. The delay cell of <FIG> includes an inverter <NUM> loaded by capacitor <NUM> and buffered by a second inverter <NUM>. Again, the amount of delay time is a function of the capacitance of capacitor <NUM> and the strength of inverter <NUM> driving capacitor <NUM>. Alternatively, delay cells may be constructed using a chain of inverters such the delay cell shown in <FIG>. The delay of the delay cell shown in <FIG> is a function of the number and strength of inverters <NUM> used to construct the delay cell. Generally, longer delays are associated with weaker inverters and/or a large number of inverters, while shorter delays are associated with stronger inverters and/or a smaller number of inverters.

It should be understood, however, that delay cells shown in <FIG> are just a few examples of many possible delay cell architectures that may be used in embodiments of the present invention. In alternative embodiments, other structures may be used. For example, delay cell <NUM> may be implemented by using other delay structures may be used such as chains of buffers, RC networks, and the like. In some embodiments, a combination of different delay structures may be combined to implement a delay cell.

<FIG> illustrates an adjustable delay circuit <NUM> that may also be used to implement adjustable delay circuit <NUM> in <FIG>. As shown, adjustable delay circuit <NUM> includes an inverter <NUM> loaded by variable capacitor <NUM> and buffered by a second inverter <NUM>. The delay of the adjustable delay circuit <NUM> may be programmed by adjusting the capacitance of variable capacitor <NUM> based on a value of duty cycle adjustment signal DutyAdj. In some embodiments, variable capacitor <NUM> may be implemented using a plurality of switched capacitors. Thus, the delay of adjustable delay circuit <NUM> can be increased by coupling in more capacitors of the plurality of capacitors to inverters <NUM>, and the delay can be reduced by coupling fewer capacitors of the plurality of capacitors to inverters <NUM>. In alternative embodiments of the present invention, variable capacitor <NUM> may be implemented using other adjustable capacitance circuits known in the art, such as a varactor.

In some embodiments, a plurality of the adjustable delay circuit <NUM> may be coupled in series. In further embodiments, adjustable delay circuit <NUM> may be used to implement individual delay cells <NUM> shown in <FIG>, such that the delay of adjustable delay circuit <NUM> is programmable both by adjusting the capacitance of variable capacitor <NUM> and by selecting one or more delay cells <NUM> via multiplexer <NUM>.

<FIG> illustrates a schematic of adjustable delay circuit <NUM> according to an alternative embodiment of the present invention. As shown, adjustable delay circuit <NUM> includes a plurality of delay cells <NUM> coupled in series with each other and separated by multiplexers <NUM> that are configured to selectively bypass its associated delay cell <NUM> according to a select signal provided by duty cycle adjustment signal DutyAdj. Thus, for a longer programmed delay, more selectable delay cells <NUM> are switched into the signal path using multiplexers <NUM>; for a shorted programmed delay, fewer delay cells <NUM> are switched into the signal path using multiplexers <NUM>. In various embodiments, adjustable delay circuit <NUM> may contain any number of stages containing delay cell <NUM> and multiplexer <NUM>. The number of stages and the amount of time delay that each delay cell <NUM> is capable of producing may vary depending on the particular an embodiment and its specifications. For example, systems having higher clock frequencies may require less delay and fewer delay cells than systems having lower clock frequencies. In some embodiments, adjustable delay circuit <NUM> shown in <FIG> may be used to implement delay cell <NUM>.

<FIG> illustrates a duty cycle correction circuit <NUM> that may be used to implement duty cycle correction circuit <NUM> shown in <FIG>. As shown, the duty cycle correction circuit includes inverter <NUM>, multiplexer <NUM>, adjustable delay circuit <NUM> and OR gate <NUM>. During operation, multiplexer selects either the clock input signal at node Clkix, or the inverse of the clock input signal in produced by inverter <NUM> at node ClkixB according to multiplexer select signal POL. This polarity signal determines the polarity of the output node ClkixC of the duty cycle correction circuit, as well as which portion of the clock input signal at node ClkixB is adjusted. For example, when the clock input signal at node Clk1x is selected, the time during which the clock input signal at node Clk1x is high is adjustable by extending time period tH of the clock input signal at node Clk1x. On the other hand, when input signal Clk1xB is selected, the time during which the clock input signal at node Clk1x is low is adjustable by extending time period tL of the clock input signal at node Clk1x.

During operation, the output of multiplexer MOUT is delayed by adjustable delay circuit <NUM> to form delayed signal DOUT. Delayed signal DOUT is ORed with multiplexer output MOUT using OR gate <NUM> to form the duty cycle corrected signal at output node OUT. As the delay of adjustable delay circuit <NUM> is increased, the time during which a clock signal present on output node OUT is high increases. Conversely, as the delay of adjustable delay circuit <NUM> is decreased, the time during which a clock signal present on output node OUT is high decreases. In various embodiments, adjustable delay circuit <NUM> may be implemented as described above with respect to <FIG>.

In alternative embodiments, duty cycle correction circuit <NUM> may be implemented differently. For example, <FIG> illustrates a duty cycle correction circuit that may also be used to implement duty cycle correction circuit <NUM> shown in <FIG>. As shown, duty cycle correction circuit <NUM> includes a plurality of inverters <NUM> coupled in parallel with each other. That is, the input to each inverter <NUM> is connected to input node IN and the output of each inverter <NUM> is connected to output node OUTB. As shown, each inverter <NUM> includes NMOS devices M1 and M2 and PMOS devices P2 and P1 coupled in series with each other. NMOS device M2 and PMOS device P2 each have gates connected to input node IN and load paths coupled to output node OUTB. The gates of NMOS devices M1 of inverters <NUM> are respectively coupled to digital select signals DCPN[n:<NUM>] and the gates of PMOS devices P1 are respectively coupled to digital select signals DCPb[n:o]. Thus, during operation, one or more of NMOS transistors M1 and PMOS transistors P1 are selectively activated in order to adjust the relative strengths of the PMOS pull-up path and the NMOS pull-down path of inverters <NUM>. For example, in cases where the rising edge of first clock signal Clk1x needs to be delayed, fewer PMOS transistors P1 may be selected in order to slow-down or delay the rising edge produced by duty cycle correction circuit <NUM>, while more NMOS devices M1 may be selected to maintain a falling edge with less delay. Similarly, in cases where the falling edge of first clock signal Clk1x needs to be delayed, fewer NMOS transistors M1 may be selected in order to slow down or delay the falling edge produced by duty cycle correction circuit <NUM>, while more PMOS devices P1 may be selected to maintain a rising edge with less delay. Inverter <NUM> may be coupled to the output of inverters <NUM> to buffer the output of inverters <NUM>. In various embodiments, the size of transistors M1, M2, P1 and M2 may be the same or different in each of inverters <NUM>.

It should be understood that the implementation examples of frequency doubling circuit <NUM> shown in <FIG> are just a few example of many possible embodiment implementations of frequency doubling circuit <NUM>. In alternative embodiments, other circuits and methods may be used to achieve the same or similar functionality.

<FIG> illustrates method <NUM> of calibrating frequency doubler circuit <NUM> according to the embodiment of <FIG>. In step <NUM>, the duty cycle parameter of second clock signal Clk2x is measured using duty cycle measurement and adjustment circuit <NUM>. In various embodiments, the duty cycle parameter of second clock signal Clk2x may be directly measured using high-speed counters or other duty cycle measurement techniques known in the art. In step <NUM>, the duty cycle of first clock signal Clk1x and/or second clock signal Clk2x is adjusted until the determined duty cycle is <NUM>% or within a predetermined tolerance of <NUM>%, or the duty cycle of first clock signal Clk1x is adjusted until differences in adjacent clock periods is within a predetermined tolerance. In some embodiments, the determined duty cycle parameter is compared to a threshold duty cycle parameter and method <NUM> shown in <FIG> is iteratively performed until the measured duty cycle parameter meets the predetermined requirement.

<FIG> illustrates method <NUM> of calibrating frequency doubler circuit <NUM> according to the embodiment of <FIG>. In step <NUM>, a test tone is generated by test tone generator <NUM> and routed to the input of duty cycle sensitive analog-to-digital converter <NUM>. The frequency of the tone generated by test tone generator <NUM> can vary depending on the particular system and its specifications. In one embodiment the frequency of the tone generated by test tone generator <NUM> is <NUM>, however, other frequencies may be used in other embodiments.

In step <NUM>, second clock signal Clk2x produced by frequency doubler <NUM> is provided as a clock signal to duty cycle sensitive analog-to-digital converter <NUM> that is sensitive to duty cycle variations in first clock signal Clk1x or second clock signal Clk2x. In step <NUM>, duty cycle sensitive analog-to-digital converter <NUM> is operated in a manner such that the test tone produced by test tone generator <NUM> is digitized, and the digital output is sent to duty cycle analysis and adjustment circuit <NUM>. In step <NUM>, a frequency transformation is performed on the digitized tone transform the digitized signal from the time domain to the frequency domain to form a frequency domain signal. In some embodiments, this frequency transformation is a FFT, however in alternative embodiments of the present invention other frequency transformation algorithms may be used, such as, but not limited to a discrete Fourier transform, discrete cosine transform (DCT), or other or other transform types known in the art. In some embodiments, a windowing function may be applied to the digitized tone prior to performing the frequency transformation. In step <NUM>, the SFDR of the frequency-transformed signal is determined. In some embodiments, the determination of the SFDR is accomplished by determining a difference in amplitude between the frequency bin corresponding to the frequency of the test tone and a frequency bin corresponding to a spur caused by asymmetries in the duty cycle of second clock signal Clk2x. As described above, in some embodiments this spur frequency may be fspur = fs/<NUM> - fin. In other embodiments, the spur frequency may be different depending on the details of the particular implementation and its specifications. Alternatively, the SFDR may be calculated by determining a difference between the power of the signal in the frequency bin corresponding to the test tone and the sum of the power in the remaining frequency bins.

In step <NUM> the duty cycle of first clock signal Clk1x and/or second clock signal Clk2x is adjusted until the determined SFDR is minimized or is within a predetermined range. In some embodiments, the determined SFDR is compared to a threshold and method <NUM> shown in <FIG> is iteratively performed until the SFDR meets the predetermined requirement.

It should be understood that in methods <NUM> and <NUM> described above, the duty cycle of the first clock signal Clkix, the duty cycle of the second clock signal Clk2x, or both the duty cycle of the first clock signal and the duty cycle of the second clock signal may be adjusted. In some embodiments, the adjustment of the duty cycle of the first clock signal Clk1x and the duty cycle of the second clock signal Clk2 are performed sequentially. For example, in one embodiment, methods <NUM> and/or <NUM> are performed to first correct the duty cycle of first clock signal Clkix, and then correct the duty cycle of second clock signal Clk2x. In other embodiments, methods <NUM> and/<NUM> are performed to first correct the duty cycle of second clock signal Clk2x, and then correct the duty cycle of first clock signal Clk1x.

<FIG> illustrates system <NUM> that includes integrated circuit <NUM> coupled to test fixture <NUM>. System <NUM> is similar to system <NUM> shown in <FIG> in that frequency doubler circuit <NUM> is calibrated by directly measuring the doubled clock signal. As shown, integrated circuit <NUM> includes frequency doubler circuit <NUM>, duty cycle sensitive analog-to-digital converter <NUM>, system circuitry <NUM>, test multiplexer <NUM>, and control logic interface circuitry <NUM>. In various embodiments, system circuitry <NUM> is representative of any type of system circuit that produces a signal for measurement by duty cycle sensitive analog-to-digital converter <NUM>. System circuitry <NUM> may include, for example, RF circuitry, sensor circuitry, audio circuitry, or any other circuitry that can be integrated on an integrated circuit. In alternative embodiments of the present invention, the various components disposed on integrated circuit <NUM> may be partitioned in a different manner. For example, one or more components of integrated circuit <NUM> may be disposed on a plurality of integrated circuits or may be implemented on a circuit board. System <NUM> also includes oscillator <NUM>, which generates first clock signal Clk1x. In various embodiments, oscillator <NUM> may be a crystal oscillator or other type of oscillator capable of generating a clock signal. In some embodiments, system <NUM> may be configured such that oscillator <NUM> is a crystal and the active circuitry used to drive the crystal (not shown) resides on integrated circuit <NUM>.

Control logic and interface circuitry <NUM> includes logic that controls the states of some or all of the various components on integrated circuit <NUM>, and includes digital interface circuitry configured to communicate with external components via a digital bus DBUS. In various embodiments, the digital interface of control logic and interface circuitry <NUM> may be a serial bus interface circuit, a parallel bus interface circuit, and/or may comply with any bus standard including, but not limited to SPI, CAN, I2C, LVDS, and USB. Accordingly, the number n of signal pins of digital bus DBUS may be any number appropriate to the implemented bus protocol.

Test fixture <NUM> may be coupled to integrated circuit <NUM> when frequency doubler circuit <NUM> is being calibrated. For example, test fixture <NUM> may be coupled to integrated circuit <NUM> during wafer testing, package testing, manufacturing testing or during routine maintenance or calibration operations. Test fixture <NUM> may be implemented, for example, using a wafer test fixture, packaging test fixture, or any other system that is configured to be coupled to integrated circuit <NUM> for the purpose of testing. In some embodiments, the functionality of test fixture <NUM> may reside in the same system as integrated circuit <NUM>. As shown, test fixture <NUM> includes clock measurement circuit <NUM>, processor <NUM> and memory <NUM>. Clock measurement circuit <NUM> is configured to be coupled to integrated circuit <NUM> via a test interface signal line TEST. As shown, test interface signal line TEST is coupled to the output of multiplexer <NUM> on integrated circuit <NUM>. During operation, control logic and interface circuitry <NUM> selects various signals to be output to test interface signal line TEST. Among these selectable signals is second clock signal Clk2x, which is the frequency doubled clock signal. It should be understood that multiplexer <NUM> may select from among any number of selectable signals within integrated circuit <NUM>. However, in some embodiments, the multiplexer <NUM> may be omitted and second clock signal Clk2x may be directly routed to test interface signal line TEST.

During testing calibration, clock measurement circuit <NUM> monitors second clock signal Clk2x and performs a duty cycle parameter measurement. In some embodiments, this duty cycle parameter measurement is transmitted to processor <NUM>. Based on this duty cycle parameter measurement, processor <NUM> adjusts the duty cycle of frequency doubler circuit <NUM> by issuing commands to control logic interface circuit <NUM> via digital bus DBUS. In some embodiments, the monitoring of the duty cycle measured by clock measurement circuit <NUM> and the adjustment of the duty cycle of frequency doubler circuit <NUM> is functionally accomplished by executing a program that resides in memory <NUM>. In some embodiments, memory <NUM> may be used to store a plurality of duty cycles measured by clock measurements circuit <NUM>, as well as a plurality of corresponding duty cycle adjustment settings. Thus, during operation, processor <NUM> can select duty cycle adjustment settings that meet a predetermined duty cycle parameter requirement.

In some embodiments, processor <NUM> may be implemented using a microcontroller or other processing circuit known in the art. In alternative embodiments of the present invention, the duty cycle monitoring and duty cycle adjustment functionality described above may be implemented using dedicated logic such as a state machine. In some embodiments, processor <NUM> also includes digital signal processing circuitry that is used to assist with the determination of the duty cycle monitored by clock measurements circuit <NUM>. For example, in some embodiments, clock measurement circuit <NUM> includes an analog-to-digital converter that provides a digital data stream to processor <NUM>. In such embodiments, processor <NUM> receives the data stream produced by clock measurements circuit <NUM> and determines the duty cycle parameter of second clock signal Clk2x using one or more digital signal processing algorithms.

Embodiment digital signal processing algorithms may include, for example, performing a frequency transformation, such as an FFT, on second clock signal Clk2x, and measuring the spurious behavior of second clock signal Clk2x. In one embodiment, the duty cycle parameter corresponding to the duty cycle of second clock signal Clk2x is the second harmonic of clock signal Clk2x. Thus, the difference in amplitude between a frequency bin at the frequency of second clock signal Clk2x and a frequency bin at the second harmonic of second clock signal Clk2x is changes according to the duty cycle of second clock signal Clk2x. The closer the duty cycle of second clock signal Clk2x to <NUM>%, the larger the difference in amplitude between these frequency bins.

In some embodiments, the duty cycle parameter corresponding to the duty cycle of the first clock signal is the amplitude of a spur at one-half the clock frequency of second clock signal Clk2x. This assumes that the clock period of second clock signal Clk2x changes every other clock period. Thus, the difference in amplitude between a frequency bin at the frequency of second clock signal Clk2x and a frequency bin at one-half of the frequency of second clock signal Clk2x changes according to the duty cycle of first clock signal Clk1x. The closer the duty cycle of first clock signal Clk1x to <NUM>%, the larger the difference in amplitude between these frequency bins. In alternative embodiments, other digital signal processing algorithms known in the art may be used to determine the duty cycle parameter.

<FIG> illustrates one circuit that could be used to implement clock measurement circuit <NUM>. In one embodiment, clock measurement circuit <NUM> includes a counter <NUM> that monitors the time during which second clock signal Clk2x is high and/or low. This time measurement can be accomplished, for example, by incrementing counter <NUM> when second clock signal Clk2x is in a high and/or low state. The result of this count can be transmitted to processor <NUM>, which may be configured to determine the duty cycle of second clock signal Clk2x based on a comparison of the number of counts that second clock signal Clk2x is in the high state (high count) and the number of counts that second clock signal Clk2x is in the low state (low count). When these counts are equal, the measured duty cycle is considered to be <NUM>%. The degree to which these counts are not equal is related to the deviation from an ideal <NUM>% duty cycle. In some embodiments, the difference between the high count and the low count may be used as a duty cycle metric for the purpose of adjusting the duty cycle of frequency doubler circuit <NUM>.

In alternative embodiments, different metrics may be used. For example, in another embodiment, counter <NUM> may be incremented when second clock signal Clk2x is in a first state (e.g., high or low) and not incremented or decremented when second clock signal Clk2x is in a second state (e.g., low or high). A resulting count after a predetermined prior of time may be used as a parameter that represents the duty cycle of second clock signal Clk2x.

The duty cycle parameter as it relates to first clock signal Clk1x may be determined by measuring the length of consecutive clock periods of second clock signal Clk2x using counter <NUM>. Thus, the duty cycle of first clock signal Clk1x approaches <NUM>% as two consecutive clock periods become closer in length to each other.

<FIG> represents another manner in which clock measurement circuit <NUM> may be implemented. In an embodiment, clock measurement circuit <NUM> may be implemented using analog-to-digital converter <NUM>. In such an embodiment, analog-to-digital converter <NUM> digitizes second clock signal Clk2x and transmits the converted digital value to processor <NUM>. Processor <NUM> may, in turn, perform a frequency transformation of the converted digital value, determine a spurious free dynamic range, and adjust the duty cycle of frequency doubler circuit <NUM> on the basis of the determined spurious free dynamic range.

<FIG> illustrates a further circuit that may be used to implement clock measurements circuit <NUM>. As shown, clock measurements circuit <NUM> may be implemented using analog-to-digital converter <NUM> and mixer <NUM>. Mixer <NUM> may be used, for example, to downconvert the clock signal to a lower frequency such that a lower sampling rate may be used for analog-to-digital converter <NUM>. In some embodiments, the frequency of the local oscillator signal LO used to drive mixer <NUM> may be set to down convert a spurious signal that is significantly affected by the duty cycle of second clock signal Clk2x. Similar to the embodiment of <FIG>, the digitized output of analog-to-digital converter <NUM> is analyzed using processor <NUM> to perform a frequency conversion, such as an FFT, and comparing the relative magnitudes of the downconverted clock signal and the downconverted spurious response. The difference in these relative magnitudes may be used as a basis for adjusting the duty cycle of frequency doubler circuit <NUM>. In various embodiments, analog-to-digital converter <NUM> may be implemented using any type of analog-to-digital converter architecture appropriate to the particular application and the particular monitored clock frequencies. In some embodiments analog-to-digital converter <NUM> may be implemented using the Sigma Delta analog-to-digital converter, a pipeline analog-to-digital converter, a flash analog to digital converter, or other type of analog-to-digital converter. Mixer <NUM> may be implemented using mixer circuits known in the art. It should be understood that the examples of <FIG> are just three examples of many types of circuits that can be used to measure the duty cycle of second clock signal Clk2x. In alternative embodiments of the present invention, other circuits known in the art may be used.

<FIG> illustrates a method <NUM> of calibrating the duty cycle of frequency doubler circuit <NUM> of system <NUM> shown in <FIG>. In step <NUM>, frequency doubler circuit <NUM> is initialized. This initialization may include, for example, configuring the various delay settings (also referred to as duty cycle settings) within frequency doubler circuit <NUM> to predetermined values. In some embodiments, initializing frequency doubler circuit <NUM> may include writing these predetermined values to a local register or memory resident on the system or integrated circuit <NUM> in which frequency doubler circuit <NUM> resides. In one example, processor <NUM> may send the configuration command to control logic and interface circuitry <NUM> via a digital bus DBUS. This configuration command may be, for example, a single command within a control word, or a register write command that is addressed to the particular register and/or registers devoted to the delay settings of frequency doubler circuit <NUM>.

In step <NUM>, second clock signal Clk2x is configured to be routed to clock measurement circuit <NUM> on test fixture <NUM>. In an embodiment, second clock signal Clk2x is routed to clock measurements circuit <NUM> by configuring multiplexer <NUM> to route second clock signal Clk2x two external test pin TEST. Next, clock measurement circuit <NUM> is initialized in step <NUM>. In some embodiments, such as the embodiments of <FIG>, analog-to-digital converter <NUM> residing within clock measurement circuit <NUM> is initialized. This initialization may include, for example, the activation of analog-to-digital converter <NUM> and/or routing the input coupled to signal TEST to the input of analog-to-digital converter <NUM>.

In step <NUM>, frequency doubler circuit <NUM> may be configured according to a first doubler configuration. This first doubler configuration may include, for example, a first predetermined set of delay settings for frequency doubler circuit <NUM>. In some embodiments, step <NUM> is performed in conjunction with step <NUM> as described above. In step <NUM>, second clock signal Clk2x is captured by clock measurements circuit <NUM>. In some embodiments, the capturing of second clock signal Clk2x is performed by digitizing second clock signal Clk2x using analog-to-digital converter <NUM> as shown in <FIG>. In embodiments that utilize frequency transformations, such as an FFT, the capturing of second clock signal Clk2x may be accomplished by digitizing the predetermined number of samples. In some embodiments, this predetermined number of samples may be a power of two. For example, <NUM>, <NUM>, <NUM>, or <NUM> samples may be digitized by analog-to-digital converter <NUM>. In alternative embodiments of the present invention, other powers of two or even a number of samples that is not a power of two may be captured according to the particular system and its specifications. In some embodiments, a window function may be applied to the digitized samples. Such window functions may include, but are not limited to, a rectangular window, a triangular window, a cosine-sum window a Hann window, a Hamming window, a Blackman window as well as other windows known in the art. In some embodiments, the application of such a window may reduce spectral leakage and improve the accuracy of spectral measurements.

In step <NUM>, a quality metric is calculated and stored. Such a quality metric may be calculated as described according to the embodiment of <FIG>. For example, the duty cycle of second clock signal Clk2x and/or clock period variation of second clock signal Clk2x may be measured directly according to the digitized output. Alternatively, the spurious free dynamic range of the frequency transformed digitized output may be determined by determining a difference between a tone corresponding to the frequency of second clock signal Clk2x and a spur corresponding to the distortion caused by a duty cycle error within second clock signal Clk2x. In some embodiments, the SFDR is determined by determining a difference between a power of a tone in a frequency bin corresponding to the frequency of second clock signal Clk2x and the sum of the power of one or more other frequency bins. Alternatively, other performance metrics may be used. In some embodiments, the calculated quality metric is stored in a memory or register. In some embodiments, the calculated quality metric is stored in memory <NUM> within test fixture <NUM>. Alternatively, the calculated quality metric may be stored in a memory or register disposed on integrated circuit <NUM>.

In step <NUM>, a determination is made as to whether all configurations of frequency doubler circuit <NUM> have been evaluated. In some embodiments, all possible configurations of frequency doubler circuit <NUM> are evaluated. In alternative embodiments a subset of all configurations of frequency doubler circuit <NUM> are evaluated. In yet other embodiments, a search algorithm such as a binary search or a linear search is performed until the calculated quality metric meets predetermined criteria such as a predetermined duty cycle or predetermined spurious free dynamic range. If the condition of step <NUM> is not satisfied, then a further configuration of frequency doubler circuit <NUM> is provided (step <NUM>). Once all configurations are provided, the method continues to step <NUM>.

In step <NUM>, a search is performed for the best quality measure. In some embodiments, each calculated quality metric is compared with each other and the doubler configuration corresponding to the best quality metric is selected to configure frequency doubler circuit <NUM> during normal operation. In other embodiments, the search is performed until the calculated quality metric is within a predetermined range. In some embodiments, step <NUM> is performed iteratively along with capturing the clock output in step <NUM> and the calculation and storage of the quality metric in step <NUM>. The frequency doubler configuration with the best quality metric is then applied to frequency doubler circuit <NUM> in step <NUM>. In some embodiments this frequency doubler configuration is written into a register or memory coupled to frequency doubler circuit <NUM>.

<FIG> illustrates system <NUM> that includes integrated circuit <NUM> coupled to test fixture <NUM>. System <NUM> is similar to system <NUM> shown in <FIG> in that frequency doubler circuit <NUM> is calibrated by monitoring the output of duty cycle sensitive analog-to-digital converter <NUM> and determining a quality metric (such as a spurious-free dynamic range) that is dependent on the duty cycle of first clock signal Clk1x and/or second clock signal Clk2x. As shown, integrated circuit <NUM> includes frequency doubler circuit <NUM>, duty cycle sensitive analog-to-digital converter <NUM>, system circuitry <NUM>, test multiplexer <NUM>, control logic and interface circuitry <NUM>, test tone generator <NUM> and first-in first-out (FIFO) memory <NUM>. During calibration, control logic and interface circuitry <NUM> activates test tone generator <NUM>, the output of which is routed to the input of duty-cycle sensitive analog-to-digital converter <NUM> via test multiplexer <NUM>. The output ADCOUT of analog-to-digital converter <NUM> is buffered by FIFO <NUM>, and the output of FIFO <NUM> is transmitted via digital bus DBUS to controller <NUM>, which determines the quality metric, for example, by performing a frequency transformation, such as an FFT, and determining an SFDR based on the frequency transformed output, as described above with respect to <FIG>.

Based on the determined quality metric, processor <NUM> adjusts the duty cycle of frequency doubler circuit <NUM> by issuing commands to control logic interface circuit <NUM> via digital bus DBUS. In some embodiments, the calculation of the quality metric and the adjustment of the duty cycle of frequency doubler circuit <NUM> is functionally accomplished by executing a program that resides in memory <NUM>. In some embodiments, memory <NUM> may be used to store a plurality of quality metrics determined by processor <NUM>, as well as a plurality of corresponding duty cycle adjustment settings. Thus, during operation, processor <NUM> can select duty cycle adjustment settings that meet a predetermined quality metric.

In alternative embodiments of the present invention, the various components disposed on integrated circuit <NUM> may be partitioned in a different manner. For example, one or more components of integrated circuit <NUM> may be disposed on a plurality of integrated circuits or may be implemented on a circuit board. System <NUM> also includes oscillator <NUM>, which generates first clock signal Clk1x. In various embodiments, oscillator <NUM> may be a crystal oscillator or other type of oscillator capable of generating a clock signal. In some embodiments, system <NUM> may be configured such that oscillator <NUM> is a crystal and the active circuitry used to drive the crystal (not shown) resides on integrated circuit <NUM>.

Test fixture <NUM> may be coupled to integrated circuit <NUM> at times during which frequency doubler circuit <NUM> is being calibrated. For example, test fixture <NUM> may be coupled to integrated circuit <NUM> during wafer testing, package testing, manufacturing testing or during routine maintenance or calibration operations. Test fixture <NUM> may be implemented, for example, using a wafer test fixture, packaging test fixture, or any other system that is configured to be coupled to integrated circuit <NUM> for the purpose of testing. In some embodiments, the functionality of test fixture <NUM> may reside in the same system as integrated circuit <NUM>.

<FIG> illustrates one circuit that could be used to implement test tone generator <NUM> in accordance with an embodiment. As shown, test tone generator <NUM> includes a frequency divider <NUM> that can be implemented using frequency divider circuits known in the art. During operation, frequency divider <NUM> divides second clock signal Clk2x down to a lower frequency. In one embodiment, the frequency produced by frequency divider <NUM> is about <NUM> as described above with respect to the embodiment of <FIG>. Alternatively, other frequencies may be generated depending on particular system and its specifications. In some embodiments, the frequency division ratio of frequency divider <NUM> may be programmable according to a frequency division ratio DIV provided as an input to frequency divider <NUM>. In some embodiments, the operation of frequency divider <NUM> may be enabled by control logic interface <NUM> via signal pin EN. In some embodiments, frequency divider <NUM> is configured to divide second clock signal Clk2x by at least a factor of two using only the rising edge or only the falling edge of second clock signal Clk2x. In such embodiments, a <NUM>% duty cycle of the produced test tone can be ensured even when the duty cycle of second clock signal Clk2x is not <NUM>%.

In some embodiments, frequency divider <NUM> is implemented using ripple counter or a synchronous counter having one or more registers. In other embodiments, frequency divider <NUM> may be implemented using various prescaler circuits and systems known in the art.

In some embodiments, the output of frequency divider <NUM> is low pass filtered in order to attenuate or remove harmonics, as shown in <FIG>, which illustrates low-pass filter <NUM> coupled to the output of frequency divider <NUM>. Low-pass filter <NUM> may be implemented using analog low-pass filter circuits known in the art. For example, in some embodiments, low-pass filter <NUM> may be implemented using a simple single pole RC filter using a series resistor and a shunt capacitor. Higher order passive filters; well as passive LC and/or RLC filters may also be used. In other embodiments, more complex filter topologies may be used. For example, an active filter having one or more implementing one or more poles may be used. Such an active filter may be implemented, for example, using opamp-based filter structures, transconductance amplifier based filter structures (such as gmC filters) or other active filter structures known in the art. In some embodiments, low-pass filter <NUM> is coupled between the output of test multiplexer <NUM> and the input to duty cycle sensitive analog-to-digital converter <NUM>. In such embodiments, low-pass filter <NUM> also serves as an anti-aliasing filter for duty cycle sensitive analog-to-digital converter <NUM>. The bandwidth of low-pass filter <NUM> may be set to a frequency appropriate to the particular system being implemented. For example, in some embodiments, the cutoff frequency of low-pass filter <NUM> may be less than one-half the sampling frequency of duty cycle sensitive analog-to-digital converter <NUM>.

<FIG> illustrates a method <NUM> of calibrating the duty cycle of frequency doubler circuit <NUM> of system <NUM> shown in <FIG>. In step <NUM>, frequency doubler circuit <NUM> is initialized. This initialization may entail, for example, configuring the various delay settings (also referred to as duty cycle settings) within frequency doubler circuit <NUM> to predetermined values. In some embodiments, initializing frequency doubler circuit <NUM> may include writing these predetermined values to a local register or memory resident on the system or integrated circuit <NUM> in which frequency doubler circuit <NUM> resides. In one example, processor <NUM> may send the configuration command to control logic and interface circuitry <NUM> via a digital bus DBUS. This configuration command may be, for example, a single command within a control word, or a register write command that is addressed to the particular register and/or registers devoted to the delay settings of frequency doubler circuit <NUM>.

In step <NUM>, test tone generator <NUM> is initialized and activated such that a test tone is generated. Next, in step <NUM> duty cycle sensitive analog-to-digital converter is initialized such that the output of test tone generator <NUM> is converted to a digital signal on the basis of second clock signal Clk2x. Such an initialization may be performed by configuring test multiplexer <NUM> to route the output of test tone generator <NUM> to the input of duty cycle sensitive analog-to-digital converter <NUM>. In step <NUM>, frequency doubler circuit <NUM> may be configured according to a first doubler configuration. This first doubler configuration may include, for example, a first predetermined set of delay settings for frequency doubler circuit <NUM>. In some embodiments, step <NUM> is performed in conjunction with step <NUM> as described above.

In step <NUM>, duty cycle sensitive analog-to-digital converter <NUM> digitizes the test tone, the output of which is sent to FIFO <NUM>. Next, in step <NUM>, the digitized test tone data stored in FIFO <NUM> is read by processor <NUM> in test fixture <NUM>. In some embodiments, one or more samples of the digitized test tone data may be stored in memory <NUM> on test fixture <NUM>. In some embodiments, a predetermined number of samples may be transferred to processor <NUM> for each quality metric measurement. In embodiments in which processor <NUM> performs an FFT on the digitized data, this predetermined number of samples may be a power of two. For example, <NUM>, <NUM>, <NUM>, or <NUM> samples may be digitized by duty cycle sensitive analog-to-digital converter <NUM>. In alternative embodiments of the present invention, other powers of two or even a number of samples that is not a power of two may be captured according to the particular system and its specifications. In some embodiments, a window function may be applied to the digitized samples. Such window functions may include, but are not limited to, a rectangular window, a triangular window, a cosine-sum window a Hann window, a Hamming window, a Blackman window as well as other windows known in the art. In some embodiments, the application of such a window may reduce spectral leakage and improve the accuracy of spectral measurements.

In step <NUM>, a quality metric is calculated and stored. Such a quality metric may be calculated as described according to the embodiment of <FIG>. For example, an FFT may be applied to the digitized tone, and an SFDR may be determined by determining a difference between a power of a tone in a frequency bin corresponding to the frequency of the digitized tone and sum of the power of one or more other frequency bins. Alternatively, other performance metrics may be used. In some embodiments, the calculated quality metric is stored in memory <NUM> within test fixture <NUM>. Alternatively, the calculated quality metric may be stored in a memory or register disposed on integrated circuit <NUM>.

In step <NUM>, a search is performed for the best quality measure. In some embodiments, each calculated quality metric is compared with each other and the doubler configuration corresponding to the best quality metric is selected to configure frequency doubler circuit <NUM> during normal operation. In other embodiments, the search is performed until the calculated quality metric is within a predetermined range. In some embodiments, step <NUM> is performed iteratively along with digitizing the test tone in step <NUM> and the calculation and storage of the quality metric in step <NUM>. The frequency doubler configuration with the best quality metric is then applied to frequency doubler circuit <NUM>. In some embodiments, this frequency doubler configuration is written into a register or memory coupled to frequency doubler circuit <NUM> in step <NUM>.

<FIG> illustrates an RF system <NUM> according to an embodiment of the present invention. RF system <NUM> incorporates the frequency doubler duty cycle adjustment circuitry shown and described with respect to integrated circuit <NUM> in <FIG> with the addition of additional RF circuitry. As shown, RF system <NUM> includes RF integrated circuit <NUM> coupled to antenna <NUM> and oscillator <NUM>. RF integrated circuit <NUM> may include one or more additional interface pins configured to be coupled to other portions of RF system <NUM> that are not illustrated in <FIG>. In various embodiments, RF integrated circuit <NUM> may be used in various RF applications including but not limited to cellular communication systems such as a cell phone radar systems such as automotive radar and other RF systems. RF integrated circuit <NUM> includes frequency doubler circuit <NUM>, test multiplexer <NUM>, duty cycle sensitive analog-to-digital converter <NUM>, and control logic and interface circuitry <NUM>. These blocks are configured to operate in accordance with the embodiment of <FIG> as described above, as well as the principle of operation of the embodiment of <FIG>. The output of test multiplexer <NUM> and digital bus DBUS may be coupled to an external test fixture as described above with respect to the embodiment of <FIG>. In some embodiments, the functionality of test fixture <NUM> may be incorporated within RF integrated circuit <NUM>.

In addition to the above-mentioned blocks, RF integrated circuit <NUM> includes RF components such as RF front-end <NUM>, downconverter <NUM>, VCO <NUM>, and phase locked loop circuitry <NUM>. RF front-end <NUM> has an input port configured to be coupled to antenna <NUM> and RF front-end <NUM> includes RF circuitry configured to amplify RF signals received from antenna <NUM>. Downconverter <NUM> is configured to downconvert the amplified RF signals to a lower frequency, such as an intermediate frequency (IF) or a baseband frequency. In some embodiments, downconverter <NUM> downconverts the amplified RF signals to a zero intermediate frequency (zero IF). The output of downconverter <NUM> is coupled to the input of optional anti-alias filter <NUM>, which is configured to attenuate frequency components higher than one-half the sampling frequency of duty cycle sensitive analog-to-digital converter <NUM>. In some embodiments, RF integrated circuit <NUM> also includes a transmit path (not shown) that is configured to provide a transmitted RF signal to antenna <NUM> and/or to another antenna (not shown). RF front-end <NUM> and downconverter <NUM> may be implemented using RF circuitry known in the art.

RF integrated circuit <NUM> also includes frequency generation blocks such as voltage-controlled oscillator (VCO) <NUM> and phase locked loop circuitry <NUM>. In accordance with an embodiment of the invention, phase locked loop circuitry <NUM> receives second clock signal Clk2x and tunes VCO <NUM> to a frequency that is a multiple of the frequency of second clock signal Clk2x using phase locked loop circuits and systems known in the art. For example, phase locked loop circuitry <NUM> may include a phase detector, a charge pump, and one or more dividers and/or prescalers. VCO <NUM> may be implemented using VCO circuits known in the art. In one example, VCO <NUM> is implemented using a single ended or differential Colpitts or negative resistance oscillator, or other oscillator type. In some embodiments, all or portions of VCO <NUM> and phase locked loop circuitry <NUM> may be implemented external to RF integrated circuit <NUM>.

RF integrated circuit <NUM> also includes optional processor <NUM> that is configured to perform baseband signal processing on the output ADCOUT of duty cycle sensitive analog-to-digital converter <NUM>. In alternative embodiments, baseband signal processing may be performed by an external processor instead of or in addition to processor <NUM>. In some embodiments, optional processor <NUM> may also perform baseband filtering instead of or in addition to baseband filter <NUM>. Processor <NUM> may also provide data to an external data bus (not shown) and/or to control logic interface circuit <NUM>.

<FIG> illustrates an RF system <NUM> according to a further embodiment of the present invention. RF system <NUM> incorporates the frequency doubler duty cycle adjustment circuitry shown and described with respect to embodiments described above with the addition of additional RF circuitry described above with respect to <FIG>. During calibration, the output of test tone generator <NUM> is routed to the input of duty cycle sensitive analog-to-digital converter <NUM> via test multiplexer <NUM>. In some embodiments, baseband filter <NUM> is coupled between test multiplexer <NUM> and the input of duty cycle sensitive analog-to-digital converter <NUM> to perform baseband filtering of the downconverter signal and/or anti-alias filtering of the baseband signal prior to its being converter by analog-to-digital converter <NUM>.

As shown, RF integrated circuit <NUM> includes frequency doubler circuit <NUM>, test multiplexer <NUM>, duty cycle sensitive analog-to-digital converter <NUM>, and control logic and interface circuitry <NUM>, test tone generator <NUM>, and FIFO <NUM>. These blocks are configured to operate in accordance with the embodiment of <FIG> as described above, as well as the principle of operation of the embodiment of <FIG>. The output of FIFO <NUM> and digital bus DBUS may be coupled to an external test fixture <NUM> as described above with respect to the embodiment of <FIG>. In some embodiments, the functionality of test fixture <NUM> may be incorporated within RF integrated circuit <NUM>. RF front-end <NUM>, downconverter <NUM>, VCO <NUM>, phase locked loop circuitry <NUM>, and anti-alias filter <NUM> operate as described above with respect to the embodiment of <FIG>.

It should be understood that the embodiments of <FIG> and <FIG> are only two of many possible system implementations of embodiments of the present invention.

Referring now to <FIG>, a block diagram of a processing system <NUM> is provided in accordance with an embodiment of the present invention. The processing system <NUM> depicts a general-purpose platform and the general components and functionality that may be used to implement portions of the embodiment radar system and/or an external computer or processing device interfaced to the embodiment radar system. For example, processing system <NUM> may be used to implement processor <NUM> and/or control logic and interface circuitry <NUM> shown in <FIG> or control logic interface circuit <NUM> shown in <FIG>, and processor <NUM> shown in <FIG> and <FIG>. In some embodiments, processing system <NUM> may be used to determine and evaluate embodiment duty cycle metrics, control operation of the embodiment RF systems, as well as control the calibration of frequency doubler <NUM>.

Processing system <NUM> may include, for example, a central processing unit (CPU) <NUM>, and memory <NUM> connected to a bus <NUM>, and may be configured to perform the processes described above. In some embodiments, memory <NUM> may be used to implement memory <NUM> shown in <FIG> and <FIG>. Alternatively, memory <NUM> may be separate from memory <NUM>. The processing system <NUM> may further include, if desired or needed, a display adapter <NUM> to provide connectivity to a local display <NUM> and an input-output (I/O) Adapter <NUM> to provide an input/output interface for one or more input/output devices <NUM>, such as a mouse, a keyboard, flash drive or the like.

The processing system <NUM> may also include a network interface <NUM>, which may be implemented using a network adaptor configured to be coupled to a wired link, such as a network cable, USB interface, or the like, and/or a wireless/cellular link for communications with a network <NUM>. The network interface <NUM> may also comprise a suitable receiver and transmitter for wireless communications. It should be noted that the processing system <NUM> may include other components. For example, the processing system <NUM> may include hardware components power supplies, cables, a motherboard, removable storage media, cases, and the like if implemented externally. These other components, although not shown, are considered part of the processing system <NUM>. In some embodiments, processing system <NUM> may be implemented on a single monolithic semiconductor integrated circuit and/or on the same monolithic semiconductor integrated circuit as other disclosed system components.

Claim 1:
A method comprising:
receiving, by an adjustable frequency doubling circuit (<NUM>), a first clock signal having a first clock frequency;
using the adjustable frequency doubling circuit (<NUM>), generating a second clock signal having a second clock frequency that is twice the first clock frequency;
measuring (<NUM>) a duty cycle parameter of the second clock signal, comprising:
generating a digitized second clock signal
transforming the digitized second clock signal from a time domain to a frequency domain to form a frequency domain second clock signal,
measuring a difference between a first frequency bin of the frequency domain second clock signal corresponding to a frequency of the second clock signal and at least one second frequency bin of the frequency domain second clock signal to form the measured duty cycle parameter;
using the adjustable frequency doubling circuit, adjusting the duty cycle (<NUM>) of the first clock signal or the second clock signal based on the duty cycle parameter.