Patent Description:
The invention generally relates to switch mode power supplies. More particularly, the invention relates to switch mode power supplies that are current controlled to maintain a substantially constant line current at an optimized power factor.

As the power capability of a power converter, or power supply, grows, the need to better utilize the power source follows close behind. The distribution of power throughout the world has coalesced on a sinusoidal AC network leading to the advent of power factor corrected processing. Prior developed power factor correction or PFC stages have used a two-stage boost based converter, or a single stage converter to achieve the voltage requirements for a load on the power supply and to achieve galvanic isolation.

In prior art PFC stages, the line current supplied is subject to substantial changes in magnitude due to the sinusoidal nature of the line voltage and current and a typically varying load. In order to achieve unity power factor, the peak current should occur substantially in phase with the peak voltage. As a result, the PFC stage switches the highest current and the highest voltage at the same time. Due to the high magnitude of current drawn during peak and valley voltages, the number and/or robustness of the switching devices are increased. In addition, higher stresses on the switching devices may be experienced during operation. These factors tend to increase cost, reduce longevity and reduce overall efficiency of the power converter. Overall efficiency can be compromised by energy loss and accompanying buildup of heat that accompanies such high magnitude current and voltage switching.

<NPL>, discloses an integrated controller which is optimized for zero-voltage resonant switching of a square-wave bridge power topology. As shown in <FIG> of this document, the basic phase-shifted bridge circuit comprises four controllable switches Q1 to Q4. Control is achieved by driving the switches as half-bridge pairs and varying the phase relationship between the two halves of the bridge. Since power is only delivered to the load when diagonal switches are conducting, a phase shift between the two half-bridges will provide a variable-width output pulse. A transformer is connected between the nodes A and B. The controller has four separate outputs for driving the four bridge switches.

"<NPL> is a datasheet describing the controller UNITRODE UC1875 in more detail.

<CIT> relates to a further resonant converter. According to this document, a parallel loaded series resonant converter is shown which is suitable for supplying DC to a three axis gradient amplifier in a magnetic resonant imaging system. It is mentioned that in conventional resonant circuits, output voltage is regulated by controlling the switching frequency of an H-bridge or half bridge switching arrangement and the resonant circuit is under more stress at no load than at full load. The voltage across the resonant capacitor is a function of the switching frequency, the load and the voltage applied across the resonant circuit. According to this document, the peak current at no load is reduced to lower than the peak current at full load by controlling the voltage applied to the resonant circuit rather than controlling the switching frequency.

<NPL>) discloses various current sensing solutions for power supply designers.

<CIT> relates to a family of soft-switched, full-bridge pulse-width-modulated (FB PWM) converters which provide zero-voltage-switching (ZVS) conditions for the turn-on of the bridge switches over a wide range of input voltage and output load. The FB PWM converters of this family achieve ZVS with the minimum duty cycle loss and circulating current, which optimizes the conversion efficiency. The ZVS of the primary switches is achieved by employing two magnetic components whose volt-second products change in the opposite directions with a change in phase shift between the two bridge legs. One magnetic component always operates as a transformer, where the other magnetic component can either be a coupled inductor, or uncoupled (single-winding) inductor. The transformer is used to provide isolated output(s), whereas the inductor is used to store the energy for ZVS.

<CIT> relates to an HVIC primary side power supply controller including full-bridge/half-bridge driver. According to this document, a primary side power supply controller includes a full-bridge/half-bridge driver and is capable of being implemented on a single HVIC chip. Control circuitry enables operation in PWM, resonant, and phase-shift control modes. In the phase-shift control mode, a phase shift generator receives two input pulse train signals and generates two output pulse train signals, each having a <NUM>% duty cycle, which are phase-shifted in a range from <NUM> to <NUM>° by an amount proportional to the duty cycle of the input pulse train signals and also proportional to the power supply load requirement. Dead time circuitry for ensuring that no two switching devices in a half-bridge, or in the same leg of a full-bridge, are conductive simultaneously employs a symmetrical delay circuit which independently delays the rising and falling edges of each signal pulse.

<CIT> relates to a single stage PFC + ballast control circuit/general purpose power converter. Two switching half-bridges are operated to achieve constant power delivered to a resonant load while achieving a high power factor. A half-bridge connected to a circuit input draws a sinusoidal current that is in phase with the input voltage to achieve the high power factor. The two half-bridges are composed of two switches each, which are operated to obtain constant load power in satisfaction of calculated conduction angles. Alternatively, the switches are operated on complementary <NUM>% duty cycles to regulate output voltage and shape the input current waveform. Output regulation is achieved by frequency control while input current wave shaping is realized by phase shifts between the two half-bridges.

Instead of focusing on achievement of a unity power factor, the power converter may beneficially operate to control the shape of the current imposed on the power supply line. This may allow the capability to achieve nearly unity power factor as well as reduce device stress in devices operating in the power converter. As a result, less heat may be produced and the number of parallel devices employed in the power converter may be reduced.

The power converter may be a single stage capable of producing relatively high power output, such as greater than 10kW. In addition, the power converter can accept a line voltage as an input voltage in a predetermined range, such as anywhere between about <NUM> to about <NUM> volts. The power converter can also provide power factor correction using a series-resonant phase shifted full bridge clamped-mode topology. In one example, the power converter may be included with an audio amplifier to supply power to one or more power supply rails within the audio amplifier. Accordingly, the power converter can be subject to a constantly varying load as the audio signal being amplified by the audio amplifier varies.

These and other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description.

<FIG> is a simplified circuit schematic of an example power processing stage of a power converter <NUM>. The power converter <NUM> includes an input rectifier <NUM>, a switching stage <NUM>, a controller <NUM>, a transformer <NUM>, and an output rectifier <NUM> that includes associated storage capacitance. In other examples, other configurations of power processing stages that are capable of providing switched mode power conversion are possible.

In <FIG>, power processing begins with a supply line input voltage and a supply line input current provided by a power source <NUM>, such as an AC power source provided by an electricity supply company, on a supply line <NUM>. In some examples, the AC power source may include electromagnetic interference (EMI) filtering capabilities, such as with an EMI line filter. The line input voltage may be full-bridge rectified by the input rectifier <NUM>. The input rectifier <NUM> may be any system or device capable of rectifying an AC voltage. The example input rectifier <NUM> is a full bridge rectifier that includes a plurality of diodes <NUM> identified as (Dp1-Dp4) connected in a bridge. In this configuration, each half cycle of a sinusoidal wave is rectified by a pair of diodes that are in opposite quarters of the bridge and in series with each other. The input rectifier <NUM> may rectify the line voltage on the power supply line <NUM>. In an alternative example, the power source <NUM> may be a DC power source. In this alternative example, the input rectifier <NUM> would be unnecessary. The rectified and filtered, or not, line voltage is provided to the switching stage <NUM> as a bulk voltage (Vbulk) on a voltage supply line <NUM> and as a bulk voltage return (Vbulk_return) on a voltage return line <NUM>.

The switching stage <NUM> includes a charge storage (Cp) <NUM>, a first set of switches <NUM>, a second set of switches <NUM>, and a series resonance tank (SRT) <NUM>. The charge storage (Cp) <NUM> may be one or more capacitors, such as a bank of film capacitors, or any other device capable of storing an electrical charge. In one example, the capacitance of charge storage (Cp) <NUM> may be relatively low, such as in the range of <NUM> microfarad to <NUM>'s of microfarads for varying loads on the power converter <NUM>, such as loads present in audio amplifier applications. The relatively low capacitance of the charge storage (Cp) <NUM> may not be configured to store a great deal of energy during operation, but may be configured to create a high-current low impedance source of high frequency current for the power converter. Accordingly, during line current controlled operation of the power converter <NUM>, line current drawn from the power supply line <NUM> may be stored in the charge storage (Cp) <NUM>. The stored line current may be drawn from the charge storage (Cp) <NUM> as a supply current, such as a high frequency supply current, resulting in minimization of electromagnetic interference (EMI) on the power supply line <NUM>.

The first and second switch sets <NUM> and <NUM> are formed in a single stage and may include a plurality of switches (S<NUM>-S<NUM>) <NUM> and a plurality of diodes (D<NUM>-D<NUM>) <NUM>. As used herein, the term "single stage" is defined as a switching stage that includes only two sets of switches, where each set of switches includes only two switches. The switches (S<NUM>-S<NUM>) <NUM> may be any form of switching device, such as an insulated gate bipolar transistor (IGBT) or MOSFET. The diodes (D<NUM>-D<NUM>) <NUM> may be any device capable of anti-paralleling operation and may be integrated into a device such as the body diode of a MOSFET. The first and second switch sets <NUM> and <NUM> may be configured to form a primary side full-bridge. In addition, the switches (S<NUM>-S<NUM>) <NUM> in the first switch set <NUM> and the switches (S<NUM>-S<NUM>) <NUM> in the second switch set <NUM> are configured as a first half bridge and a second half bridge, respectively. During operation, the first set of switches <NUM> are operated to produce a first voltage output from the bulk voltage (Vbulk) on the voltage supply line <NUM> and the bulk voltage return (Vbulk_return) on the voltage return line <NUM>. The second set of switches <NUM> may be independently but similarly operated to produce a second voltage output. Each of the first and second voltage outputs may be a switch-generated time variable magnitude of voltage with an associated switch generated current. The relative phase of the first and second sets of switches <NUM> and <NUM> is varied such that a phase difference is selectively created between the first and second voltage outputs. The first and second voltage outputs are applied to the series connected SRT <NUM> and transformer <NUM>.

The SRT <NUM> may be any device capable of filtering a voltage by acting as an interface between two voltage sources. In effect, the SRT <NUM> may act as a current source to generate a square wave output at a primary winding of the transformer <NUM>. In <FIG>, the example SRT <NUM> is constructed of an inductor (L) <NUM>, such as a close coupled inductor, and a capacitor <NUM>, such as the two banks of capacitors C<NUM> & C<NUM>. The capacitor <NUM> may include multiple capacitors and the inductor (L) <NUM> may include two or more inductors that are close coupled to enable relatively high power throughput operation. In one example, the inductor (L) <NUM> may include multiple tightly coupled windings with substantially equal flux so that voltage and current flowing in the inductor (L) <NUM> and thus the transformer (T) <NUM> are shared substantially equally. In other examples, any other configuration of capacitance and inductance may be used to create the SRT <NUM>. The switches (S<NUM>-S<NUM>) <NUM> may be coupled with the transformer (T) <NUM> through the SRT <NUM>. As used herein, the terms "connected," "coupled" and "electrically coupled" are intended to broadly encompass both direct and/or indirect connections capable of conducting voltage and current between components and/or devices.

The controller <NUM> may be any circuit or device capable of switching the first and second sets of switches <NUM> and <NUM> with switching signals provided over switch control lines <NUM>. The controller <NUM> controls the frequency and relative phase of the first and second sets of switches <NUM> and <NUM> to perform power factor correction and voltage regulation. Power factor correction and voltage regulation by the controller <NUM> may be based on a voltage signal sensed by the controller <NUM> on a voltage sensing line <NUM>. The voltage may be sensed from the SRT <NUM> as described later.

The transformer (T) <NUM> may be any form or transformer providing a step change in voltage between one or more primary winding(s) and one or more secondary winding(s) included in the transformer (T) <NUM>. For example, the transformer (T) <NUM> may be an isolation and step-up transformer with dual primary windings and low leakage. The transformer (T) <NUM> may provide one or more output voltages, and may be wound to provide paralleled interleave to better couple the primary winding(s) to the secondary winding(s). In <FIG>, the transformer (T) <NUM> is configured to provide a dual set of output voltages on a secondary winding. The output voltages may be supplied on one or more power supply output rails, and may be fed into a regulation control scheme (not shown) included in the power converter <NUM>. In the example power converter <NUM>, the power supply output rails include a first power supply output rail <NUM> that is a low voltage DC rail and a second power supply output rail <NUM> that is a main DC rail. The first and second power supply output rails <NUM> and <NUM> may be derived from the output rectifier <NUM>.

The output rectifier <NUM> may be a secondary side full bridge rectifier. In other examples, any other device or circuit may be used to rectify the output of the secondary side of the transformer (T) <NUM>. In <FIG>, the rectifier <NUM> includes a plurality of diodes (Dlv1-Dlv4) <NUM> connected in a bridge to form a low voltage full bridge rectifier and a plurality of diodes (Dhv1-Dhv4) <NUM> connected in a bridge to form a high voltage full bridge rectifier. Thus, a separate full bridge rectifier may supply rectified voltage to each of the first and second power supply rails <NUM> and <NUM>. Each of the full bridge rectifiers may include capacitors (Clv1-Clv2 and Chv1-Chv2) <NUM> to provide high frequency filtering.

During operation, the switches (S1-S4) <NUM> may be directed by the controller <NUM> to turn on and off in a manner that maintains a substantially constant supply of line current from the power supply line <NUM>. In addition, the switching of the switches (S1-S4) <NUM> may be controlled by the controller <NUM> to optimize the power factor of the power converter <NUM> by controlling the shape of the waveform of the line current imposed on the power supply line <NUM>. More specifically, the controller <NUM> may selectively operate the switches (S1-S4) <NUM> to flatten or clip the peak portions of line current by enabling the generation of a square wave current and a primary voltage that is controlled to a conduction voltage. The square wave current and the primary voltage may be generated with the first and second voltage outputs from the respective first and second sets of switches <NUM> and <NUM>. Thus, in the case of an AC line current, the controller <NUM> may operate to purposefully "distort" the sinusoidal waveform of the line current to avoid imposing on the power supply line <NUM> what would otherwise be peak currents of the sinusoidal wave of the line current. By controlling the shape of the line current waveform, nearly unity power factor may be achieved. In addition, due to the lower peak current, device stress in devices operating in the power converter <NUM> may be reduced.

Unity power factor maximizes efficiency of the power consumed by a load. In order to best use the full potential of an AC line having a line voltage and a line current, while minimizing distortion caused by a load, such as a power supply, connected to the AC line, an ideal load would be a resistive one. With a fully resistive load, the line current is in phase with the line voltage and harmonic content is determined by a fundamental frequency of the line voltage. Power factor is determined by the ratio of the real power to the product of the RMS voltage and RMS current consumed by a load. With a resistive load, this leads to a value of unity. Most conventional power supplies with a simple transformer/rectifier combination have effective power factors in the <NUM>-<NUM> range; hence the AC line is called to deliver a larger RMS current than is actually ideally necessary to meet the power demands of a power supply and any load supplied thereby.

<FIG> depicts a first graph <NUM> that shows an ideal power factor for an AC power source and a second graph <NUM> that shows a power factor generated, for example, with the power converter <NUM> using an AC power source. The first graph <NUM> includes a line voltage (Vin<NUM>) that is in phase with a line current (Iin<NUM>), such as could occur with a purely resistive load. The second graph <NUM> includes a line voltage (Vin<NUM>) and a line current (Iin<NUM>) that is a nearly constant line current and has a square wave shaped current waveform. The square wave shaped current waveform (Iin<NUM>) may be generated by the power converter <NUM> at the same frequency and duty cycle as the power supply line. If the time during which the power converter <NUM> draws current from the power supply line is defined as "d", then an expression for the power factor PF(d) of the second graph <NUM> can be expressed as: <MAT>.

The derivative with respect to duty cycle of the line current (Iin<NUM>) may be used to find the maximum power factor. Accordingly, an optimum line current (Iin<NUM>) may be determined at a certain power factor. In the example second graph <NUM>, the optimum power factor one can achieve may occur when the duty cycle of the square wave shaped current waveform (Iin<NUM>) nears <NUM> (or <NUM>% of the possible <NUM>% available duty cycle of the line current (Iin<NUM>)) with a theoretical power factor of about <NUM>. Accordingly, in the second graph <NUM>, the line current is conducting during <NUM>% of a positive portion of the line current duty cycle and not conducting during the remaining <NUM>%. Similarly, the line current (Iin<NUM>) may also be conducting during <NUM>% of a negative portion of the line current duty cycle and not conducting during the remaining <NUM>%. The power factor of such a line current remains desirably close to unity and allows optimum power supply switch utilization and regulation in a single stage of power processing. In other examples, other line current duty cycles and corresponding power factors are possible.

In this example, 120Vac was chosen as the line voltage (Vin<NUM>) for which the power factor would be maximum. In other examples, any other magnitude of voltage may be chosen. The greatest line current occurs at the lowest operating voltage for a given power level, thus the greatest benefit for high power factor also occurs at the lowest operating voltage. To maximize the power factor in the 120Vac example, conduction of the constant current waveform (Iin<NUM>) may be selected to begin at a conduction voltage of approximately 67V, which in this example, is the lowest anticipated operating voltage. Taking into consideration losses, such as circuitry losses, the design point may be selected to be about 60V in order to ensure conduction at 67V.

Accordingly, the power converter <NUM> may be designed to begin conducting and induce the flow of line current (Iin<NUM>) through the power converter <NUM> when the sinusoidal waveform of the voltage is at or above 60V. Thus, the transformer (T) <NUM> may be designed with a turns ratio of the primary winding and the secondary winding so that a reflected voltage of the secondary winding is about equal to the conduction voltage. In other examples other lowest projected operating voltages and corresponding magnitudes of reflected voltage may be chosen, and conduction of the constant current waveform (Iin<NUM>) may occur at different conduction voltages.

In <FIG>, the line current (Iin<NUM>) <NUM> is a square shaped current waveform with a peak current <NUM>. The line current (Iin<NUM>) <NUM> can be substantially constant within each half of a time interval (T) <NUM> during the time when the line current (Iin<NUM>) <NUM> is being drawn (conducting) from the power supply line <NUM> (<FIG>). During operation with the power converter <NUM>, both the onset of conduction, and termination of conduction of the line current (Iin<NUM>) <NUM> may include rounded edges due primarily to non-zero throughput impedances. In addition, there may be some variation in the magnitude of the magnitude of the line current (Iin<NUM>) <NUM> during conduction due to source variation, load variation, and/or control loop speed. Thus, during conduction, the line current (Iin<NUM>) <NUM> is a substantially constant current that attempts to achieve the ideal square wave shape depicted in <FIG> but falls short due to the aforementioned constraints. As such, the term "substantially constant current" or "substantially constant line current" is defined herein as when the line current (Iin<NUM>) <NUM> reaches at least about <NUM>% of a maximum during an alternating current half-cycle, and varies by no more then about <NUM>% from the at least <NUM>% of the maximum within one-half of the alternating current half-cycle or one-quarter of the time interval (T) <NUM>.

<FIG> is an example graph <NUM> of power factor vs. line voltage (Vin<NUM>) for the example selected line voltage (Vin<NUM>) of 120Vac. In other examples, plots similar to <FIG> may be depicted to illustrate other magnitudes of line voltage and corresponding maximum power factor points. As the line voltage (Vin<NUM>) varies on either side of a selected maximum power factor point <NUM>, the power factor may fall off. The power converter <NUM> may be operated to optimize the power factor within a particular region, such as the region of the lowest anticipated operating voltage (the conduction voltage), while operating with a lesser power factor elsewhere where stresses in the devices of the power converter <NUM> are less. Accordingly, stresses associated with high current may be avoided thereby reducing heating in the die of devices included in the power converter <NUM>. In addition, due to lowered stresses, fewer components may be employed in the power converter.

In <FIG>, phase-shift modulation is used to control the first and second sets of switches <NUM> and <NUM>. During operation, one of the first and second sets of switches <NUM> and <NUM> may be a leading leg, and the other set of switches <NUM> may be a lagging leg. For example, where the first and second set of switches <NUM> and <NUM> form a full-bridge, the first set of switches <NUM> may be operated by the controller <NUM> to be a leading leg, or rotating half bridge of the full bridge, and the second set of switches <NUM> may be a lagging leg, or static half-bridge, of the full-bridge.

As previously discussed, the first set of switches <NUM> and the second set of switches <NUM> are connected differentially between the bulk voltage (Vbulk) on the voltage supply line <NUM> and the bulk voltage return (Vbulk_return) on the voltage return line <NUM>. During operation, the switches (S1-S4) <NUM> may be directed by the controller <NUM> to turn on and off in such a way, that a quasi-square wave voltage (the conduction voltage) is generated across the series connected SRT <NUM> and transformer <NUM>. As described later, the quasi-square wave voltage is filtered by the SRT <NUM> to generate a square wave voltage of magnitude equal to the reflected voltage on the primary of the transformer (T) <NUM>. The magnitude of a fundamental of the square wave voltage may be controlled by the controller <NUM> to be equal to or greater than the conduction voltage.

The switching of the switches (S1-S4) <NUM> may determine the frequency of the square wave voltage. The controller <NUM> may include a clock, or any other timing mechanism, operating at a predetermined frequency, such as <NUM>. Using the clock, the controller <NUM> may control the switching frequency and thus the frequency of the square wave voltage that is generated. In other examples, the switching frequency may be variable instead of fixed.

<FIG> is an example graph <NUM> depicting the first voltage output <NUM> of the first set of switches <NUM>, the second voltage output <NUM> of the second set of switches <NUM>, and a differential voltage <NUM> representative of the combination of the first and second voltage outputs <NUM> received by the SRT <NUM>. The filtered differential voltage <NUM> forms a primary voltage that is received at the primary of the transformer (T) <NUM>. Over a switching cycle of either of the first or second set of switches <NUM> or <NUM>, a <NUM>% duty cycle square wave could be observed for the respective first or second voltage outputs <NUM> and <NUM>. By varying the relative phase of these <NUM>% duty cycle square waves, the effective duty cycle of the differential voltage <NUM>, can range from <NUM>% to <NUM>% corresponding to the phase relationship of the first and second voltage outputs <NUM> and <NUM>. As used herein, the term "relative phase" is defined to be the phase relationship between the periodic first and second voltage output signals generated by the respective first and second set of switches <NUM> and <NUM>.

In <FIG>, in a first column <NUM> the effective duty cycle of the differential voltage <NUM> is zero percent since the first and second voltage outputs <NUM> and <NUM> are in relative phase (zero degrees of phase difference). Thus the magnitude of the effective differential voltage <NUM> applied to the SRT <NUM> and subsequently to the transformer (T) <NUM> is substantially zero. In a second column <NUM>, a third column <NUM>, and a fourth column <NUM>, the effective duty cycle of the differential voltage <NUM> has been increased to <NUM>%, <NUM>%, and <NUM>%, respectively, due to a corresponding difference in the relative phase (or phase relationship) of the first voltage output <NUM> to the second voltage output <NUM>. As a result, the fundamental amplitude of the quasi-square wave of the differential voltage <NUM> has increased in magnitude. When the effective duty cycle is <NUM>% in column <NUM>, the first and second voltage outputs <NUM> and <NUM> are <NUM> degrees out of relative phase and the differential voltage <NUM> is a square wave as illustrated. At other percentages, such as the <NUM>% duty cycle and the <NUM>% duty cycle illustrated in respective columns <NUM> and <NUM>, the differential voltage <NUM> is a quasi-square wave. In other examples, other percentage increases in the effective duty cycle of the differential voltage <NUM> are possible.

Phase shift modulation may be used, in conjunction with the series resonant tank (SRT) <NUM>, to provide a primary voltage to the transformer (T) <NUM> that is a square wave with a peak amplitude approximately equal to the predetermined conduction voltage. In the previously described example, the transformer primary conduction voltage threshold was a square wave with approximately a 60V peak amplitude. The primary voltage is provided to the primary winding of the transformer (T) <NUM> to induce the flow of the line current from the power supply line <NUM>. Accordingly, the current flow induced by the primary voltage may shape the current drawn as the line current (the square wave current Iin2 of <FIG>). As previously discussed, the conduction voltage must be greater in magnitude than the voltage reflected from the secondary of the transformer (T) <NUM> to the primary winding of transformer (T) <NUM> to induce the flow of line current in the secondary of transformer (T) <NUM>.

During operation, as the line voltage varies, such as a <NUM>-<NUM> sine wave that varies sinusoidally over each half cycle, the relative phase of the first and second voltage outputs <NUM> and <NUM> may be varied by the controller <NUM> with the respective first and second sets of switches <NUM> and <NUM> in an effort to maintain the primary voltage about equal to the conduction voltage. The relative phase of the first and second voltage outputs <NUM> and <NUM> may be varied by the controller <NUM> in order to achieve the desired shape of the line current by generating the necessary effective duty cycle of the differential voltage <NUM>.

The effective duty cycle of the differential voltage <NUM> that is calculated by the controller <NUM> may also be based on a load placed on the power converter <NUM>. The larger the measured voltage drop on the power supply output rail(s), when compared to a predetermined reference voltage(s), the larger the error signal generated with the controller <NUM>, and thus the duty cycle of the first and second sets of switches <NUM> and <NUM> may be increased. In other words, as the load on the secondary of the transformer (T) <NUM> increases, the primary voltage on the primary winding of the transformer (T) <NUM> decreases, and more line current is drawn from the power supply line <NUM> to maintain the primary voltage of the transformer (T) <NUM> at the conductive voltage so that the line current continues to flow.

In <FIG>, by adjusting the effective duty cycle of the differential voltage <NUM> to a higher percentage (such as from <NUM>% to <NUM>%) by adjustment of the relative phase of the first and second switches <NUM> and <NUM> with the controller <NUM>, the conductive voltage of the primary of the transformer (T) <NUM> may be maintained as the secondary voltage of the transformer (T) <NUM> falls. Thus, line current continues to flow from the primary of the transformer (T) <NUM> to the secondary of the transformer (T) <NUM> and the secondary voltage is maintained. Similarly, as the secondary voltage of the transformer (T) <NUM> falls, the duty cycle of the first and second switches <NUM> and <NUM> may be adjusted by the controller <NUM> to lower the effective duty cycle of the differential voltage <NUM> (such as from <NUM>% to <NUM>%) to lower the conductive voltage of the primary of the transformer (T) <NUM>.

Accordingly, during operation, the controller <NUM> may work to maintain the peak magnitude of the primary voltage at a predetermined magnitude (the conductive voltage), such as about <NUM> volts, based on the line voltage of the power supply line <NUM> and the power consumption of the load. The primary voltage may be maintained at the conduction voltage to regulate the power supplied to a load of the power converter <NUM>. In the example of a load that is the power rails of an output stage of an audio amplifier, the load is varied almost constantly when audio is being amplified by the audio amplifier and thus the effective duty cycle may similarly constantly vary to maintain the peak amplitude of the primary voltage about equal to the predetermined conductive voltage.

In <FIG>, the series resonant tank (SRT) <NUM> is used in conjunction with the phase shift modulated first and second sets of switches <NUM> and <NUM> at a fixed frequency or a variable frequency. The basic function of the SRT <NUM> can be to average the duty cycle modulated quasi-square wave of the differential voltage <NUM> (<FIG>) into a square wave of approximately the peak amplitude of the conduction voltage, such as approximately 60V peak amplitude. During operation, the SRT <NUM> may convert the quasi-square wave of the differential voltage <NUM> (<FIG>) to the square wave provided to the primary of the transformer <NUM>.

Conversion by the SRT <NUM> may involve filtering the quasi-square wave to limit the associated current to a predetermined frequency, such as a fundamental frequency (first harmonic). Thus, the quasi-square wave voltage may be filtered by the SRT <NUM> to generate a square wave voltage with a current consisting primarily of the fundamental. The amplitude of the fundamental voltage of the quasi-square wave may be controlled by the controller <NUM> to be equal to or greater than the fundamental of the square wave induced upon the primary winding(s) of the transformer with the amplitude of the square wave just equal to or greater then the conduction voltage. In this way the SRT <NUM> may act as a constant current source for the transformer (T) <NUM>, and as an intermediate filter between the first and second sets of switches <NUM> and <NUM> and the transformer (T) <NUM>.

The resonant frequency (fr) of the example SRT <NUM> illustrated in <FIG> may be expressed as: <MAT>.

The inductance expressed as L in Equation <NUM> may include the leakage inductance of the transformer as seen from the primary with any single secondary shorted. The power converter <NUM> may be operated at a frequency above that of the resonant tank or below, thus achieving various states of soft switching for each of the first and second sets of switches <NUM> and <NUM>. In the example power converter <NUM>, the resonant frequency may be chosen to be below that of the switching frequency. Throughout most of the operating range, the power converter <NUM> may achieve zero voltage switching at turn on for the leading leg, such as the first set of switches <NUM>. Similarly, the lagging leg, such as the second set of switches <NUM> may achieve zero current switching at turn off throughout a great deal of the operating range.

<FIG> depicts an example switching cycle <NUM> of a power converter <NUM> operating with AC power supplied from the power supply line <NUM>. The example switching cycle occurs at the frequency of the switching frequency provided by the controller <NUM>, such as <NUM>. A resonant current waveform (Ir) <NUM>, and the differential voltage <NUM>, are shown along with a plurality of time steps (t<NUM>-t<NUM>) indicating where switching transitions take place. The differential voltage <NUM> is the quasi-square wave and is represented with a resonant voltage waveform (Vr). The resonant current waveform (Ir) <NUM> is provided to the primary of the transformer <NUM>, and is proportional to the difference in the fundamental components of the voltage between the differential voltage <NUM> and the primary voltage supplied to the primary winding of the transformer <NUM>.

In <FIG>, the time steps include a first time period <NUM> that is identified to be from time t<NUM> to time t<NUM>, a second time period <NUM> is identified to be from time t<NUM> to time t<NUM>, a third time period <NUM> is identified to be from time t<NUM> to time t<NUM>, a fourth time period <NUM> is identified to be from time t<NUM> to time t<NUM>, a fifth time period <NUM> is identified to be from time t<NUM> to time t<NUM>, and a sixth time period <NUM> is identified to be from time t<NUM> to time t<NUM>.

<FIG> depicts a plurality of example switch position scenarios <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> within the switching stage <NUM> (<FIG>) and a corresponding current path <NUM>. The example switch position scenarios <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> correspond to the time periods <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of <FIG>. In each of the switch position scenarios, the switches <NUM> and/or diodes <NUM> that are conducting are denoted with a black dot.

During operation, in the first switch position scenario <NUM> and the first time period <NUM>, the switches <NUM> identified as S<NUM> and S<NUM> are conducting. When the second time period <NUM> is entered, the switch <NUM> identified as S<NUM> has turned off, and the current path <NUM> transitions to the diode <NUM> identified as D2, while the switch <NUM> identified as S<NUM> continues conducting. When the third time period <NUM> commences, there is a current direction reversal as illustrated by the current path <NUM> when the diode <NUM> identified as D4 begins conducting, and the switch <NUM> identified as S<NUM> begins conducting. During the fourth time period <NUM>, the switch <NUM> identified as S<NUM> begins conducting, and the switch <NUM> identified as S<NUM> continues conducting. In the fifth time period <NUM>, the switch <NUM> identified as S<NUM> turns off, and the current path transitions to flow through the diode <NUM> identified as D1 and the switch <NUM> identified as S<NUM>. When the sixth time period <NUM> is entered, another current reversal occurs, and the diode <NUM> identified as D3, and the switch <NUM> identified as S<NUM> provide the current path <NUM>.

In <FIG> and <FIG>, during the first time period <NUM> from t<NUM> - t<NUM>, as depicted in the first switch position scenario <NUM>, the switch <NUM> identified as S<NUM> in the first set of switches <NUM> and the switch <NUM> identified as S<NUM> the second set of switches <NUM> are conducting. Accordingly, a line current may flow from the power supply line <NUM> through the switch <NUM> identified as S<NUM> in the first set of switches <NUM> and the switch <NUM> identified as S<NUM> in the second set of switches <NUM>. The resulting resonant current waveform (Ir) <NUM> coincides with a current flow from the AC line during the time period from t<NUM>-t<NUM>. During the time period t<NUM>-t<NUM>, the relative phase of the first and second voltage outputs <NUM> and <NUM> is also greater than zero resulting in the differential voltage <NUM> being greater than zero. (<FIG>) The peak of the quasi-square wave of the differential voltage <NUM> may be about equal to the instantaneous supply line voltage provide from the power supply line <NUM> (<FIG>). In addition, during the time period t<NUM>-t<NUM>, the line current may also flow from the power supply line <NUM> to charge the charge storage (Cp) <NUM> (<FIG>).

The fourth time period <NUM> from t<NUM>-t<NUM> and the fourth switch position scenario <NUM> of <FIG> and <FIG> illustrate a second period of conduction of line current from the source <NUM>. As illustrated by the corresponding current path <NUM> in the fourth switch position scenario <NUM> of <FIG>, the line current <NUM> is again flowing from the power supply line <NUM> during time t<NUM>-t<NUM> through the switches <NUM> identified as S<NUM> and S<NUM> and may also flow to charge the charge storage (Cp) <NUM> (<FIG>). In addition, the relative phase of the first and second voltage outputs <NUM> and <NUM> may be greater than zero resulting in a differential voltage <NUM>.

The remainder of the time periods <NUM>, <NUM>, <NUM> and <NUM>, namely t<NUM>-t<NUM>, t<NUM>-t<NUM>, t<NUM>-t<NUM> and t<NUM>-t<NUM>, and respective switch position scenarios <NUM>, <NUM>, <NUM> and <NUM> are representative of time periods where the current is circulating without conduction from the source <NUM> through the switches <NUM>. During the time periods where the current is circulating, charge storage (Cp) <NUM> (<FIG>) may still receive line current from the power supply line <NUM>. In <FIG>, the time when no line current is flowing to the sets of switches <NUM> and <NUM> is identified as the cross-hatched areas inside of the resonate current waveform <NUM> when the differential voltage <NUM> is substantially zero. During the time when no line current is flowing to the first and second sets of switches <NUM> and <NUM>, circulating current is flowing out of one set of switches <NUM> or <NUM> to the other set of switches <NUM> or <NUM> and then through the SRT <NUM> and the transformer <NUM>. The charge storage (Cp) <NUM> also may be discharging to provide circulating current during the when no line current is flowing to the first and second sets of switches <NUM> and <NUM>.

Another function of the series resonant tank (SRT) <NUM> can be to provide a mechanism to determine the current flowing through the switching stage <NUM>. By integrating the voltage (vL) across a known inductance (L), the current through the inductor (iL), and hence the resonant tank current (iL) can be calculated as follows: <MAT>.

The SRT <NUM> may have a voltage gain that operates over the full range of possible loads. As the current in the SRT <NUM> increases, with frequency being fixed or variable, the effective impedance can become significant. At voltages near the line current conduction point, the effective duty cycle of the differential voltage <NUM> can approach <NUM>% in order to conduct the demanded line current to the load side of the transformer (T) <NUM>. The SRT <NUM> may be designed such that the voltage gain, defined from the input of the inductor (L) <NUM> to the output of the capacitor <NUM>, deviates as little as possible from unity. The more the gain of the SRT <NUM> drops, the greater can be the impact on the effective power factor due to reduced effective conduction angle or line voltage duty cycle.

<FIG> is a block diagram of a portion of the power converter <NUM> illustrated in <FIG> that includes the controller <NUM>, the switching stage <NUM>, and the output rectifier <NUM>. In the example controller <NUM> depicted in <FIG>, the controller <NUM> includes a current sensor circuit <NUM> that is coupled to a first input of a comparator <NUM>. The controller <NUM> also includes a feedback controller circuit <NUM> coupled with a limiter circuit <NUM>. The limiter circuit <NUM> is coupled with a second input of the comparator <NUM>. The output of the comparator <NUM> is coupled with a pulse width modulation-to-phase shift modulation (PWM-to-PSM) converter <NUM>, which may be coupled to a leg swapping circuit <NUM>.

The leg swapping circuit <NUM> is an optional control feature that may or may not be included. Hence, the leg swapping circuit <NUM> is depicted with dotted lines in <FIG>. The leg swapping circuit <NUM> may be coupled with switching stage <NUM>. Alternatively, where the leg swapping circuit <NUM> is not included, the PWM-to-PSM converter <NUM> may be coupled with the switching stage <NUM>. The PWM-to-PSM converter <NUM> may generate the switching signals used to drive the first and second sets of switches <NUM> and <NUM> (<FIG>) included in the switching stage <NUM>. The switching stage <NUM> also includes the SRT <NUM>, and may be coupled with the output rectifier <NUM>.

A first feedback line <NUM> may provide a first feedback signal indicative of the line current provided from the power supply line <NUM>. In one example, the first feedback signal may be representative of an inductor voltage of the inductor (L) <NUM> that is used to determine the line current. The inductor voltage of the inductor (L) <NUM> may be measured across a separate winding within the inductor (L) <NUM>, across an entire winding representative of inductor (L) <NUM>, measure with a tap formed across a portion of one or more windings forming inductor (L) <NUM>, or with any other technique to obtain a voltage representative of a voltage drop across at least a portion of the inductor (L) <NUM>. In another example, the first feedback signal may be provided from a current sensor monitoring the current through the SRT <NUM>, the output rectifier <NUM>, or any other device.

A second feedback signal is provided on a second feedback line <NUM> to the feedback controller circuit <NUM>. The second feedback signal may be representative of an output voltage, such as the scaled supply rail voltage feeding the load from a power supply rail <NUM>. Alternatively, where there are multiple power supply rails, the second feedback signal may be an indication of a scaled differential voltage of the power supply rail voltages feeding the load.

The current sensor circuit <NUM> includes an integrator <NUM> and a forward current integrator <NUM>. The integrator <NUM> may be any circuit or device capable of providing integration of an input signal over a time(t). In <FIG>, the integrator <NUM> may receive the first feedback signal from the first feedback line <NUM>. The integrator <NUM> may use the first feedback signal to determine the current flowing through the inductor (L) <NUM> based on the voltage across the inductor (L) <NUM>. An output of the integrator <NUM> may be representative of an inductor current that is provided on an inductor current line <NUM>. More specifically, the inductor current may be a scaled current through the resonant inductor (L) <NUM> determined by mathematical integration of the inductor voltage of the inductor (L) <NUM>.

The forward current integrator <NUM> may be any circuit or device capable of integration. In one example, the forward current integrator <NUM> may integrate the inductor current when the power converter <NUM> is conducting in a forward direction. The inductor current may be integrated during the time when the power converter <NUM> is conducting in a forward direction to determine the line current, such as an average AC line current.

<FIG> is a more detailed circuit diagram of one example of the average line current circuit <NUM>. The current sensor circuit <NUM> can be connected with the inductor (L) <NUM> at an inductor voltage input <NUM> that receives the inductor voltage. The average line circuit <NUM> may provide an average line current to the comparator <NUM> (<FIG>) at an average line current output <NUM>. The integrator <NUM> may be a passive integrator and differential receiver that includes a plurality of resistors <NUM>, a plurality of capacitors <NUM>, and an amplifier <NUM>. The output of the amplifier <NUM> is provided on the inductor current line <NUM>. The forward current integrator <NUM> may be an active integrator. The forward current integrator <NUM> includes a resistor <NUM>, a switch <NUM>, a capacitor <NUM>, and an amplifier <NUM>. The current sensor circuit <NUM> also includes a rectifier <NUM> coupled between the integrator <NUM> and the forward current integrator <NUM>. The rectifier <NUM> may be a precision full-bridge rectifier.

During operation, an inductor voltage signal may be provided to the inductor voltage input <NUM>, passively integrated and scaled by the resistors <NUM> and the capacitors <NUM>, and provided to the amplifier <NUM>. The amplifier <NUM> may act as a differential receiver to mathematically integrate the inductor voltage signal as previously discussed with reference to EQUATION <NUM>. The output signal of the amplifier <NUM> is representative of an inductor current and is provided on the inductor current line <NUM>. The output representative of the inductor current may be rectified by the rectifier <NUM> and provided to the forward current integrator <NUM>. The rectified output representative of the inductor current may be received and integrated by the amplifier <NUM> when the switch <NUM> is closed. The switch <NUM> may be closed whenever the power converter <NUM> is conducting in a forward direction.

The power converter <NUM> conducts in a forward direction when the relative phase of the first and second voltage outputs is different. When the relative phase of the first and second voltage outputs is different, the first and second voltage outputs do not completely overlap, and the differential voltage <NUM> (<FIG>) is greater than zero. In other words, as discussed with reference to <FIG> and <FIG>, during the first time period <NUM> and the fourth time period <NUM> when line current is being supplied from the power supply line <NUM> while the resonant voltage (Vr) (differential voltage <NUM>) is greater than zero. Control of the switch <NUM> may be with a processor, a sensor, or any other device capable of determining when the power converter <NUM> is conducting in a forward direction. The output of the amplifier <NUM> is representative of the average line current drawn from the power supply line <NUM>. The output of the forward current integrator <NUM> can be time averaged in order to create a representation of the line current, and is used to determine the overlap or relative phase of the first and second voltage outputs from the first and second sets of switches <NUM> and <NUM>.

In <FIG>, the feedback controller circuit <NUM> can be any form of proportional and/or integral control device. Alternatively, the feedback controller circuit <NUM> may also include a derivative term to speed up the response of the controller <NUM>, at the possible expense of optimizing the power factor. The feedback controller circuit <NUM> may be used in the main voltage feedback control loop to provide constant current control as previously discussed. Inputs to the feedback controller circuit <NUM> may include the second feedback signal that is the scaled supply rail voltage feeding the load and a reference voltage (VREF) supplied on a reference voltage line <NUM>. The reference voltage may be a constant, predetermined voltage, or a variable voltage that is variable in a predetermined range.

<FIG> is a more detailed circuit diagram of one example of the feedback controller circuit <NUM> depicted in <FIG>. The feedback controller circuit <NUM> includes an open collector comparator <NUM>, a main feedback controller <NUM>, a plurality of resistors <NUM> and a plurality of capacitors <NUM> coupled as illustrated. The open collector comparator <NUM> may receive the second feedback signal on the second feedback line <NUM>. In addition, the open collector comparator <NUM> may receive a scaled reference signal on a reference signal line <NUM>. In one example, the scaled reference signal may be the reference voltage (VREF) provided on the reference voltage line <NUM> that has been increased by a constant M.

During operation, the second feedback signal on the second feedback line <NUM> may have a value at or very near the reference voltage (VREF). In order to clamp an overshoot of the output voltage provided on the power supply rail <NUM>, the scaled reference signal provided on the reference signal line <NUM> may be made larger then the reference voltage (VREF) by a determined percentage. Accordingly, the reference voltage (VREF) may be multiplied by a constant M, where M is equal to the sum of unity and the predetermined percentage, to form the scaled reference signal on the reference signal line <NUM>.

The output of the open collector comparator <NUM> may be provided as a feed forward signal to adjust the reference voltage (VREF) provided to the main feedback controller <NUM> on the reference voltage line <NUM>. The main feedback controller <NUM> may include one or more non-linear loop(s) formed with, for example, the open collector comparator <NUM> in order to intercept the reference voltage (VREF). The main feedback controller <NUM> also may receive the previously described second feedback signal from the second feedback signal line <NUM>. The main feedback controller <NUM> may be any form of proportional, integral and/or derivative controller.

During operation, as the scaled power supply rail voltage (second feedback signal) begins to overshoot the scaled reference signal, the reference voltage (VREF) that is an input to the main feedback controller <NUM> may be immediately reduced, thus forcing an output error signal on an output line <NUM> of the main feedback controller <NUM> to a low or non-conducting state. This in turn may clamp the voltage on the main output of the power converter <NUM> (the power supply rail <NUM>) from further increasing. Such control techniques may be deployed to optimize the power factor when the tolerance for overshoot in the power converter <NUM> is low. This technique may allow for a relatively slow main feedback loop around the main controller <NUM> and relatively fast acting overshoot protection formed by the components around the open collector comparator <NUM>.

In <FIG>, the limiter circuit <NUM> may be any circuit or device capable of preventing an input signal from exceeding a determined maximum threshold value. The limiter circuit <NUM> may have one or more inputs, such as a first variable input on a first variable input line <NUM> and a second variable input on a second variable input line <NUM> that may be used in the calculation of an absolute limit. The first variable input may be a load related variable input and the second variable input may be a line related variable input. For example, the first variable input may be predetermined value, or derived from a measured voltage such as from the scaled differential rail voltage of the power supply rails <NUM> and/or <NUM>.

The second variable input may be a predetermined value, or may be derived from a measured voltage, such as a line voltage supplied from the power supply line <NUM>. During operation, the limiter circuit <NUM> may vary the absolute limit applied to the output error signal received from the feedback controller circuit <NUM> to keep the output error signal generated by the feedback controller circuit <NUM> within set limits. An output of the limiter circuit <NUM> may be the output error signal provided by the feedback controller circuit <NUM> that has been limited to a range controlled by the limiter circuit <NUM>. In other words, the limiter circuit <NUM> may limit the output error signal when the output error signal exceeds a determined threshold, and may otherwise pass the output error signal unchanged to the comparator <NUM>. The limited, or not limited, output error signal may be a reference supply line current that is provided to the comparator <NUM>.

<FIG> is a more detailed circuit schematic of one example of the limiter circuit <NUM> depicted in <FIG>. The limiter circuit <NUM> may include a multiplier/divider <NUM>, a first amplifier <NUM>, a second amplifier <NUM>, a transistor <NUM>, and a plurality of resistors <NUM>. The limiter circuit <NUM> may determine an upper current limit for the line current to protect the power converter <NUM> from overload In addition, the limiter circuit <NUM> may compensate for the increased conduction angle on the power supply line <NUM> at higher input voltages. Further, the limiter circuit <NUM> may compensate for current related losses in the power converter <NUM> in determining the upper current limit for the line current. The first and second amplifiers <NUM> and <NUM>, the transistor <NUM> and the resistors <NUM> can avoid an excessive calculated upper current limit as line voltage is increased.

There may be multiple operating control modes for the power converter <NUM>. In one example, there are two control modes. Mode <NUM> may be used when power is initially applied to the power converter <NUM>. In addition, mode <NUM> may be used for various other conditions, such as when the line voltage drops below a determined threshold, a front panel switch of the power converter <NUM> is cycled, a breaker feeding the power supply line <NUM> is cycled, or if for some reason the power supply output rail(s) voltage drops below a preset minimum indicating either a short circuit or an amplifier problem. Mode <NUM> may be considered as a soft start operational mode used to reduce stress on the power supply line <NUM> when charging up the secondary side capacitors <NUM>. In mode <NUM>, the current limit may be fixed at a suitably low level, and the control loops of the power converter control and the limiter circuit <NUM> may be disabled. With the current limit set low, the bulk of the capacitance can be charged at a desirably low line current flow rate such that any surges on the power supply line <NUM> may be minimized. Mode <NUM> may be disabled once the power supply output rail(s) reach a predetermined threshold, such as a respective nominal voltage value.

Mode <NUM> may be a second operational mode of the power converter <NUM>. During mode <NUM>, calculations may be constantly being made by the limiter circuit <NUM> to set the upper limit for the line current in order to obtain the same maximum power output regardless of the line voltage from the power supply line <NUM>. As previously discussed, the power converter may have a "universal input" so that the line voltage may be anywhere in a predetermined range such as between about 85Vac and 277Vac or between about 120Vac and 240Vac. In other examples, additional modes may also be included in the power converter <NUM>, such as a thermally limited power mode. In a thermal limit mode, for example, the power converter <NUM> may sense temperatures of one or more circuit elements. The upper current limit may be reduced by the limiter circuit <NUM> accordingly when the sensed temperature(s) is at or above a determined temperature, thereby reducing dissipation.

Because the turns ratio of the step-up transformer (T) <NUM> may be fixed, and the output voltage of the power converter <NUM> can be regulated, the voltage needed on the primary of the transformer (T) <NUM> can be achieved earlier in a duty cycle of the power supply line <NUM>, such as an AC half-cycle. In addition, the throughput conduction percentage of the line cycle time period can be increased as the voltage on the power supply line <NUM> is increased. Accordingly when the line voltage is decreased the throughput conduction percentage of the line cycle time period can be reduced. Conduction losses may also increase with lower line voltages, due to the high currents necessary to achieve a regulated supply with a fixed output voltage.

Referring to <FIG>, <FIG>, <FIG>, and <FIG>, during operation in one example, the limiter circuit <NUM> may receive with the second amplifier <NUM> the line voltage, such as an average AC line voltage, as the second variable input signal on the second variable input line <NUM>. The line voltage may be scaled by the second amplifier <NUM> and provided to the multiplier/divider <NUM>. In addition, the first amplifier <NUM> may receive a power supply rail voltage, such as the differential rail voltage of the power supply rails <NUM> and/or <NUM>, as the first variable input signal on the first variable input line <NUM>. The multiplier/divider <NUM> may calculate an upper current limit (Iupper) for the power converter <NUM> to achieve maximum power output based on the line voltage (Vin), the power supply rail voltage (Vrail), and a constant K as: <MAT> The value K may be used to bring the output of the multiplier/divider <NUM> in to the operational range of the comparator <NUM>. K may also exhibit a nonlinear quality in order to compensate for an increasing line conduction angle as the line voltage is increased.

By comparing the power supply rail voltage, such as a scaled differential rail voltage, to a known reference voltage, a current limit may be derived, such as from the feedback controller circuit <NUM>. As demand on the power converter <NUM> increases, the power supply rail voltage may decrease. The difference between the reference voltage and the scaled power supply rail voltage may be referred to as an error. The error may be used to determine an average that may be used as the upper current limit. The upper current limit may be determined by the limiter circuit <NUM> when the power converter <NUM> is powered up, and may be maintained until the power converter <NUM> is powered down. Alternatively, a predetermined magnitude of variation in the line voltage on the power supply line <NUM> may trigger re-calculation of the upper current limit.

In <FIG>, during operation, the comparator <NUM> can generate a varying drive signal that is provided to the PWM-to-PSM converter <NUM>. The drive signal may be generated based on comparison of the output representative of the average line current from the current sensor circuit <NUM> and the range limited, or not range limited, output error signal provided by the limiter circuit <NUM>. The comparator <NUM> may be fast enough to generate the drive signal multiple times within a cycle of the first and second voltage outputs generated by the respective first and second sets of switches <NUM> and <NUM>. Thus, for example, at the time during the cycle when the output representative of the average line current exceeds the output error signal, the comparator <NUM> may generate a drive signal.

In one example, the drive signal may be a digital signal that is at a logic zero to enable phase shifting of the relative phase of the first and second voltage outputs generated by the respective first and second set of switches <NUM> and <NUM>. Conversely, when the drive signal is at a logic one, phase shifting of the first and second voltage outputs may be disabled. In other examples, the logic states may be reversed. The relative phase shifting switching signals may be generated by the PWM-to-PSM converter <NUM>.

In this example, when a cycle commences, the drive signal may be at a logic zero, and shifting of the relative phase is enabled. As the cycle proceeds, while the relative phase continues to shift towards the maximum relative phase shift of <NUM>% (<FIG>), the output representative of the average line current may exceed the output error signal. At this time in the cycle, the comparator <NUM> may generate a logic one drive signal, thus terminating further relative phase shifting during that cycle and resulting in some percentage of relative phase shift, such as <NUM>% or <NUM>% of a relative phase shift (see <FIG>). In one example, the change in logic state of the drive signal may occur twice per cycle, once during the positive portion of the cycle and once during the negative portion of the cycle. Accordingly, the relative phase shift may commence at the beginning of each half cycle and may terminate sometime during the half cycle when the output representative of the average line current exceeds the output error signal. It follows that when the output representative of the average line current does not exceed the output error signal, the drive signal will enable the relative phase to be shifted by <NUM>%. In other examples, the change in logic state of the drive signal may occur any number of times during a cycle.

The PWM-to-PSM converter <NUM> may not only create a pulse width modulated signal based on the switching control signals, but also convert a pulse width modulated signal to a phase shift modulated signal based on the drive signal input and the switching control signals. The phase shift modulated signal may be provided to the switching stage <NUM> to control the switching of the first and second sets of switches <NUM> and <NUM>. The respective first and second voltage outputs may be provided to the SRT <NUM> for filtering or averaging and then be provided to the transformer (T) <NUM> and output rectifier <NUM>.

The average line current, such as an AC line current, may be determined by integrating the voltage across a single turn of wire on the resonant inductor (L) <NUM>, as previously discussed. The integrated voltage may yield a scaled waveform that has the shape of the current through the series resonant tank (SRT) <NUM> and a known scaled magnitude. The scaled waveform may then be integrated over only the portion of time that the phase shifted voltage outputs of the first and second sets of switches <NUM> and <NUM> overlap. The result of the integration may be an average input line current. In <FIG> and <FIG>, as previously discussed, the line current is conducting, or forwarded, during the time durations t<NUM>-t<NUM> and t<NUM>-t<NUM> and thus the first and second voltages of the respective first and second switches are overlapped during these time durations. By utilizing an integrator during these time durations that is reset when not in use, the average line current can be calculated twice per switching period.

Once the integrated line current reaches a determined threshold, such as a "forward current reference" that is the input current limit, the switching cycle of the first and second switches <NUM> and <NUM> may be terminated. The operation of the current sensor circuit <NUM> may lead to generation of a pulse width modulated control signal within the PWM-to-PSM converter <NUM> , which may be converted to phase shift modulation by the PWM-to-PSM converter <NUM> (<FIG>). The control signal may be used to control each of the first and second set of switches <NUM> and <NUM> in the switching stage <NUM>. The control signal may change substantially continuously throughout each cycle of the power supply line <NUM>, such as being refreshed numerous times throughout each AC half-cycle in order to maintain a relative constant current draw from the power supply line <NUM>. In addition, the duty cycle envelope of the control signal may be continued over successive power supply line <NUM> cycles or for a predetermined period of time since it is a function of the input voltage, the output voltage, and the load seen by the power converter <NUM>.

In order to achieve desirable power factor, the response of the controller <NUM> may be made slow enough so that transient load conditions on the power converter <NUM> are not transferred immediately to the power supply line <NUM>. However, slower control may create a condition, under highly dynamic conditions, where overshoot can occur at the output of the power converter <NUM>. In order to alleviate the possibility of this condition, a non-linear element may be added to the control loop. For example, a non-linear element may be added to the circuit that includes the comparator <NUM> in <FIG>. The non-linear element may have greater speed then the main control loop as previously discussed to avoid overshoot of the power supply output.

In <FIG>, another feature that may be implemented in the power converter <NUM> is the leg-swapping circuit <NUM>. As previously discussed, the power converter <NUM> may include a leading leg and a lagging leg. Each of the leading and lagging legs may include one or more sets of switches. In <FIG>, each of the leading and lagging legs include one set of switches <NUM> and <NUM> having two switches <NUM>. In other examples, additional or fewer sets of switches, and switches within each set may be present. For purposes of explanation only, the example of <FIG> will be further described, but should not be construed as limiting the configuration or operational functionality of the leg-swapping circuit <NUM> to any particular switching stage configuration.

In <FIG>, due to the different switching conditions that each of the first and second set of switches <NUM> and <NUM> may be subjected to, losses may tend to be greater in one leg then the other. During the time when the power converter <NUM> is not conducting current to the secondary or output side of the power converter <NUM> (at zero crossing of the sine wave), the leading and lagging legs can be swapped or exchanged in response to a predetermined event or condition. Swapping of the leading and lagging legs may be accomplished by intercepting switching control signals (or switching signals) provided by the controller <NUM> and exchanging their destinations. Effectively, in the example of <FIG>, the control signals controlling the switching of the first and second sets of switches <NUM> and <NUM> may be exchanged.

In one example, a temperature driven leg-swapping function may be implemented. During operation, switching of the switches <NUM> may generate heat. Conduction cooling such as with a heatsink may be used to minimize this heating. When the switches <NUM> are heated unevenly, that is, one or more switches <NUM> are hotter than the remaining switches <NUM>, the hotter switch(s) <NUM> may experience additional stress, decreased efficiency, etc..

In one example, each of the sets of switches <NUM> and <NUM> may have a heatsink. The temperature of heatsinks associated with each of the sets of switches <NUM> and <NUM> may be monitored with a temperature sensor, such as a thermocouple. The temperature sensor may provide a signal indicative of temperature to the controller <NUM>, or some other device capable of exchanging the switching control signals. The hotter of the two heat sinks may trigger a swap in the control signals allowing the hotter heat sink to cool. In other examples, the temperature of each of the switches <NUM>, groups of switches, or any other associated hardware may be monitored with a temperature sensor. Such a leg swapping technique may extend the range of power the power converter <NUM> is capable of providing and/or allow the power converter <NUM> to run longer at a given power level.

In another example, an automatic leg swapping circuit may be implemented. In this example, the legs may be swapped every AC half-cycle to make the average heat dissipation of the first and second sets of switches <NUM> and <NUM> substantially equal. A voltage detector may be used to determine when the AC voltage is below a predetermined threshold so that current draw from the line is substantially absent. For example, the voltage detector may detect the time during each duty cycle when the line current is not conducting.

<FIG> is circuit schematic that depicts an example automatic leg swapping circuit <NUM> and a portion of the switching stage <NUM>. The illustrated portion of the switching stage <NUM> includes the first set of switches <NUM> and the second set of switches <NUM>. In the first set of switches <NUM>, a first switch (S1) <NUM> includes a first control line (AH') <NUM> for receiving switching control signals, and a second switch (S2) <NUM> includes a second control line (AL') <NUM> for receiving switching control signals. In the second set of switches <NUM>, a third switch (S3) <NUM> includes a third control line (BH') <NUM> for receiving switching control signals, and a fourth switch (S4) <NUM> includes a fourth control line (BL') <NUM> for receiving switching control signals.

The leg swapping circuit <NUM> of this example includes a detector circuit <NUM>, a register <NUM>, and an exchange circuit <NUM>. The detector circuit <NUM> may be any device or circuit capable of detecting a variable associated with the operation of the power converter <NUM>. In <FIG>, the detector circuit <NUM> is a voltage detector. In one example, when the power supply line is an AC power supply line, the detector circuit <NUM> may be a hysteretic AC voltage detector. In other examples the detector circuit may detect any other predetermined condition or event, such as an event or condition related to temperature, power, current, switching frequency and/or any other variable parameter. The example detector circuit <NUM> includes a plurality of resistors <NUM>, and a comparator <NUM>. The register <NUM> may be any form of settable register. In <FIG>, the register <NUM> is an edge triggered D flip-flop. The exchange circuit <NUM> may be any form of circuit or device capable of exchanging the control signals provided to the first and second sets of switches <NUM> and <NUM>. In the example of <FIG>, a <NUM>-line to <NUM>-line multiplexer may be used to swap the switching control signals provided to the leading leg and the lagging leg.

The automatic exchange of the switching control signals may be synchronized to a predetermined time, such as once per half-cycle. In addition or alternatively, the automatic exchange of the switching control signals may be confined to an exchange opportunity window. The exchange opportunity window may define ranges of line current flow and/or line voltage magnitude with regard to the first and second switches where swapping control signals is enabled. Alternatively, or in addition, the exchange opportunity window may define a load range where swapping is enabled. For example, in an audio amplifier application, the exchange opportunity window may enable exchange of the control signals only during times when an input audio signal falls below a determined threshold. In other examples, other techniques may be employed to achieve automatic leg swapping or leg swapping based on operational conditions.

In <FIG> during operation, a reference voltage (VREF), such as a predetermined fixed voltage, may be received by the comparator <NUM> on a reference line <NUM>. The comparator <NUM> may also receive on a line voltage line <NUM> a line related signal that is representative of the line voltage on the power supply line <NUM>. In one example, when the line voltage is an AC line voltage, the line related signal representative of the line voltage supplied on the line voltage line <NUM> may be a rectified and scaled AC line voltage. In addition, the reference voltage (VREF) may be about zero volts. Thus, the comparator <NUM> may change state when the line voltage is about zero volts, or when the sinusoidal waveform is crossing zero. The output signal of the detector circuit <NUM> may be provided as an exchange signal to update the register <NUM> on an exchange enable line <NUM>. In <FIG>, the exchange signal may be adjusted with a voltage logic signal (Vlogic) on a voltage logic line <NUM> to interface the output of the comparator <NUM> with the register <NUM> when the register <NUM> is operating at a different voltage then the comparator <NUM>. In examples where the voltages are compatible, the voltage logic signal (Vlogic) may be omitted.

As the output signal of the detector circuit <NUM> changes state, the register <NUM> may be enabled to toggle between states. In <FIG>, the output signal of the detector circuit <NUM> is provided as an input to the clock line of the register <NUM> (D flip-flop). Accordingly, as the input to the clock line goes low, the output (Q) of the register <NUM> takes on the then current state of the D input of the register <NUM>. Thus, the register <NUM> may toggle between a logic zero and a logic one state with each falling edge of the output signal of the detector circuit <NUM>. The output of the register <NUM> is an enable signal received by the exchange circuit <NUM> on an enabling input <NUM>. In <FIG>, the enable signal is a digital signal that enables operation of the exchange circuit <NUM>. In other examples, other logic configurations may be used that perform similar functionality. In addition, changes to the detector circuit, the register <NUM> and the exchange circuit <NUM> may be necessary when other example implementations of the leg swapping circuit <NUM> are deployed.

In <FIG>, the exchange circuit <NUM> may include a plurality of control signal outputs <NUM>, identified as control signal outputs 1Y, 2Y, 3Y, and 4Y. The control signal outputs 1Y, 2Y, 3Y, and 4Y are configured to drive respective output switching control signals <NUM> identified as AH', AL', BH' and BL' on the respective control lines <NUM>, <NUM>, <NUM>, and <NUM>. Accordingly, the control signal outputs identified respectively as 1Y, 2Y, 3Y, and 4Y drive respective first (S1), second (S2), third (S3) and fourth (S4) switches <NUM>, <NUM>, <NUM> and <NUM>.

In addition, the exchange circuit <NUM> may include a plurality of sets of control signal inputs. In <FIG> a first set of control signal inputs <NUM> are designated as 1A, 2A, 3A, and 4A, and a second set of control signal inputs <NUM> are designated as 1B, 2B, 3B, and 4B. A set of input switching control signals <NUM> are provided on the sets of control signal inputs <NUM> and <NUM>. The set of input switching control signals <NUM> may be provided from the controller <NUM>. In <FIG>, the input switching control signal <NUM> identified as AH is provided to the first control signal input <NUM> identified as 1A, and to the second control signal input <NUM> identified as 3B. Similarly, the input switching control signals <NUM> identified as AL, BH and BL are provided to the respective first control signal inputs <NUM> identified as 2A, 3A and 4A and to the respective second control signal inputs <NUM> identified as 4B, 1B and 2B.

The exchange circuit <NUM> may selectively direct the input switching control signals <NUM> provided on either the first set of control signal inputs <NUM> or on the second set of control signal inputs <NUM> to the control signal outputs <NUM>. In the first set of control signal inputs <NUM>, each of the control signal inputs identified as 1A, 2A, 3A and 4A may be directed to the respective control signal outputs <NUM> identified as 1Y, 2Y, 3Y and 4Y. Similarly, in the second set of control signal inputs <NUM>, each of the control signal inputs identified as 1B, 2B, 3B and 4B may be directed to the respective control signal outputs <NUM> identified as 1Y, 2Y, 3Y and 4Y.

Thus, when enabled, the exchange circuit <NUM> may redirect the signals being fed to the first set of switches <NUM> to the second set of switches <NUM>, and redirect the signals being fed to the second set of switches <NUM> to the first set of switches <NUM>. Since, in this example, the exchange circuit <NUM> may be enabled during zero crossings of the line voltage, there is substantially no voltage present at the first and second sets of switches <NUM> and <NUM> during the exchange of control signals. The control signals may be redirected by the exchange circuit <NUM> by directing the first set of control signal inputs <NUM> to the control output signals <NUM> instead of the second set of control signal inputs <NUM>, or vice-versa. In other words, the exchange circuit <NUM> may direct either the first set of control inputs <NUM> designated as 1A, 2A, 3A, and 4A or the second set of control signal inputs <NUM> designated by 1B, 2B, 3B, and 4B to the control signal outputs <NUM> designated respectively as 1Y, 2Y, 3Y, and 4Y.

Accordingly, in <FIG> there are two possible inputs (A or B) for each output (Y). Either the A input may be designated or the B input may be designated based on the exchange signal provided as an input to the register <NUM> and thereafter provided as the enable signal on the enabling signal line <NUM>. In <FIG>, during operation, when the enabling signal is a logic low input, the exchange circuit <NUM> will provide the A outputs to Y. When the enable signal is a logic high input, the exchange circuit <NUM> will provide the B inputs to Y. In other examples, more possible inputs are possible. In addition, in other examples, the operation of the exchange circuit may occur with a processor or other logic performing similar functionality.

The previously described power converter <NUM> is operable with a single stage switching stage <NUM> to provide substantially constant line current while optimizing power factor. The power converter may control the shape of the waveform of the line current with phase shift modulation through control of the voltage waveform at the primary of the transformer <NUM>. The voltage present at the primary of the transformer <NUM> may be controlled based on a derived representation of the line current and a load on the power converter <NUM>. The derived representation of the line current may be obtained by integration of a voltage present across the inductor (L) <NUM> in the SRT <NUM>. The power converter <NUM> may also include leg swapping functionality to extend the operating range and/or capability of the power converter <NUM>.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible.

Claim 1:
A resonant power converter (<NUM>) comprising:
a switching stage (<NUM>) that includes a first set of switches (<NUM>) and a second set of switches (<NUM>), wherein the first and second set of switches are operable to respectively produce a first and second voltage from a bulk voltage (Vbulk) on a voltage supply line (<NUM>) and a bulk voltage return (Vbulk_return) on a voltage return line (<NUM>);
a controller (<NUM>) coupled with the switching stage (<NUM>), where the controller (<NUM>) is operable to control switching of the first set of switches (<NUM>) and the second set of switches (<NUM>) to enable the output of the first voltage (<NUM>) from the first set of switches (<NUM>) and the second voltage (<NUM>) from the second set of switches (<NUM>);
a series resonant tank (<NUM>), SRT, comprising an inductor (<NUM>) and a capacitor (<NUM>); and
a transformer (<NUM>) having a primary and a secondary winding;
wherein the first and second voltages are applied to the series connected SRT (<NUM>) and the transformer (<NUM>), wherein the transformer (<NUM>) is operable to receive at the primary winding from the SRT a primary voltage (<NUM>) representative of a combination of the first and second voltages (<NUM>, <NUM>), where the controller (<NUM>) is operable to control the primary voltage (<NUM>) by variation of a relative phase difference between the first voltage (<NUM>) and the second voltage (<NUM>); and
wherein the controller (<NUM>) is operable to determine a primary current by integration of a voltage drop across the inductor (<NUM>);
wherein the controller (<NUM>) is further operable to determine an average line current by integration of the primary current only during times when the first time variable voltage (<NUM>) and the second time variable voltage (<NUM>) have a relative phase difference such that the first time variable voltage (<NUM>) and the second time variable voltage (<NUM>) do not completely overlap, and
wherein the controller (<NUM>) is further configured to generate a drive signal to disable phase shifting of the relative phase of the first and second voltages, if an output representative of the average line current exceeds an output error signal provided by a limiter (<NUM>) within the controller (<NUM>).