Patent Description:
This invention was made with government support under Defense Advanced Research Projects Agency (DARPA) of the United States, under grant contract number HR0011-<NUM>-<NUM>-<NUM>. The government may have certain rights in the invention.

The present disclosure relates to photonics generally and specifically to fabricating of photonics structures.

Commercially available photonic integrated circuits are fabricated on wafers, such as bulk silicon or silicon-on-insulator wafers.

In one aspect photonics integrated circuits can include waveguides for transmission of optical signals between different areas of a photonic integrated circuit chip as well as on and off the chip. Commercially available waveguides are of rectangular or ridge geometry and are fabricated in silicon (single or polycrystalline) or silicon nitride.

Commercially available photonics integrated circuits can include photodetectors and other optical components. Photonic integrated circuits rely on the emission, modulation and the detection of light in the communication band (about <NUM> to about <NUM>). A bandgap absorption edge in germanium is near <NUM>. Germanium has been observed to provide sufficient photo-response for optoelectronic applications using <NUM> and <NUM> carrier wavelengths.

Commercially available photonics integrated circuit chips are available on systems having a photonics integrated circuit chip disposed on a printed circuit board. <CIT> discloses a method for reducing optical coupling loss in a dielectric stack, a dielectric stack, and an optical device. The method comprises the steps of removing at least a portion of the dielectric stack associated with one or more metal layers of the dielectric stack in a region where optical losses are to be eliminated; and replacing said portion with a homogenous dielectric material. <CIT> discloses a silicon carbon nitride film is formed on an interlayer dielectric film having Si-H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption and prevents deterioration associated with the moisture absorption by a lower-layer insulating film and a Cu film, thereby suppressing an increase in the capacitance between interconnections or via resistance.

The shortcomings of the prior art are overcome, and additional advantages are provided, through the provision, in one aspect, of a photonics structure.

There is set forth herein a method according to claim <NUM>.

Additional features and advantages are realized through the techniques of the present disclosure.

The foregoing and other objects, features, and advantages of the disclosure are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:.

Aspects of the present disclosure and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the disclosure, are given by way of illustration only, and not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.

<FIG> illustrates fabrication of photonics structure <NUM> having a photonics dielectric stack <NUM> in which there can be fabricated and defined one or more photonics device such as one or more waveguide of waveguides <NUM>, one or more waveguide of waveguides <NUM>, one or more waveguide <NUM>, one or more grating <NUM>, one or more modulator <NUM>, and one or more photodetector <NUM> having light sensitive material formation <NUM>. A one or more photonics device can in addition or alternatively be provided e.g. by a resonator, a polarizer or another type of photonics device. Waveguides <NUM> can represent waveguides formed of single crystalline silicon (Si), waveguides <NUM> can represent waveguides formed of nitride, e.g. SiN, and waveguides <NUM> can represent waveguides formed of any generic waveguiding material, e.g. single crystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride. Photonics structure <NUM> can be built using a prefabricated silicon on insulator (SOI) wafer having substrate <NUM>, insulator layer <NUM> and silicon layer <NUM>. Waveguides <NUM>, grating <NUM> and modulator <NUM> can be patterned in silicon layer <NUM>.

Patterned within photonics dielectric stack <NUM> there can also be contact conductive material formations such as contact conductive material formations C1, C2, C3, C4, C5 and C6, metallization layer 422A defining metallization layer conductive material formations M1, vias layer 322A defining vias layer conductive material formations V1, metallization layer 422B defining metallization layer conductive material formations M2, vias layer 322B defining vias layer conductive material formations V2, metallization layer 422C defining metallization layer conductive material formations M3, vias layer 322C defining vias layer conductive material formations V3, metallization layer 422D defining metallization layer conductive material formations M4, vias layer 322D defining vias layer conductive material formations V4, and metallization layer 422E defining metallization layer conductive material formations M5.

Contact conductive material formations C1, C2, C3, C4, C5, and C6 can be formed generally by depositing one or more dielectric stack layer to at least top elevation of the respective contact conductive material formation C1, C2, C3, C4, C5, and C6 etching to define cavities for receiving conductive material, filling the cavities with conductive material, and then planarizing to the top elevation of the respective contact conductive material formation C <NUM>, C2, C3, C4, C5, and C6. Contact conductive material formation C1 can be formed e.g. of aluminum (Al), tungsten (W) or another non-copper conductive material. Contact conductive material formations C2-C6 can be formed e.g. of copper (Cu), aluminum (Al), tungsten (W) or another metal or another conductive material.

Metallization layers 422A, 422B, 422C, 422D, 422E can be formed generally by depositing one or more dielectric stack layer to at least top elevation of the respective metallization layer 422A, 422B, 422C, 422D, 422E, etching to define cavities for receiving conductive material, filling the cavities with conductive material, and then planarizing to the top elevation of the respective metallization layer 422A, 422B, 422C, 422D, 422E. Metallization layers 422A, 422B, 422C, 422D, 422E can also be formed generally by depositing uniform thickness metallization layers, and then masking and etching to remove layer material from unwanted areas. Metallization layers 422A, 422B, 422C, 422D defining metallization layer conductive material formations M1-M4 can be formed of e.g. copper (Cu), aluminum (Al), tungsten (W) or another metal or another conductive material. Metallization layer 422E defining metallization layer formations M5 can be formed of aluminum (Al).

Vias layers 322A, 322B, 322C, 322D can be formed generally by one or more dielectric stack layer to at least a top elevation of the respective vias layer 322A, 322B, 322C, 322D, etching to define cavities for receiving conductive material, filling the cavities with conductive material, and then planarizing to the top elevation of the respective vias layer 322A, 322B, 322C, 322D. Vias layers 322A, 322B, 322C, 322D can also be formed generally by depositing uniform thickness metallization layers, and then masking and etching to remove layer material from areas where the layer material is unwanted. Vias layers 322A, 322B, 322C defining vias layer conductive material formations V1-V3 can be formed e.g. of copper (Cu), aluminum (Al), tungsten (W) or another metal or another conductive material. Vias layer 322D defining vias layer conductive material formations V4 can be formed of aluminum (Al).

Metallization layer 422A, metallization layer 422B, metallization layer 422C, metallization layer 422D, and metallization layer 422E can define horizontally extending wires. Wires defined by metallization layers 422A, 422B, 422C, 422D, 422E can be horizontally extending through areas of photonics dielectric stack <NUM>.

Horizontally extending wires defined by metallization layer 422A can be electrically connected to one or more vertically extending contact conductive material formations C1-C6 and vias V1 defined by vias layer 322A for distribution of one or more of control, logic and/or power signals vertically and horizontally to different areas of photonics dielectric stack <NUM> having fabricated therein one or more photonics device.

Horizontally extending wires defined by metallization layer 422B can be electrically connected to one or more of vertically extending vias V1 defined by vias layer 322A and/or vertically extending vias V2 defined by vias layer 322B for distribution of one or more of electrical control, logic and/or power signals vertically and horizontally between different areas of photonics dielectric stack <NUM>.

Horizontally extending wires defined by metallization layer 422C can be electrically connected to one or more of vertically extending vias V2 defined by vias layer 322B and/or vertically extending vias V3 defined by vias layer 322C for distribution of one or more of electrical control, logic and/or power signals vertically and horizontally between different areas of photonics dielectric stack <NUM>.

Horizontally extending wires defined by metallization layer 422D can be electrically connected to one or more of vertically extending vias V3 defined by vias layer 322C and/or vertically extending vias V4 defined by vias layer 322D for distribution of one or more of electrical control, logic and/or power signals vertically and horizontally between different areas of photonics dielectric stack <NUM>.

Horizontally extending wires defined by metallization layer 422E can be electrically connected to one or more of vertically extending vias V4 defined by vias layer 322D for distribution of one or more of electrical control, logic and/or power signals vertically and horizontally between different areas of photonics dielectric stack <NUM>.

Photonics structure <NUM> in can be fabricated using various processes including processes for fabricating light signal transmitting regions of photonics structures. Processes for fabrication of photonics structure <NUM> can include (A) a process for removal of silicon carbon nitride (SiCN) from photonics structure <NUM> to reduce IR light absorption; and (B) a process for removal of SiN to reduce unwanted light coupling between circuit elements.

Embodiments herein recognize that use of copper (Cu) defining conductive material formations in photonics structure <NUM> such as contact conductive material formations C2-C6, metallization layer conductive material formations M1-M4, and vias layer conductive materials formations V1-V3, can increase performance of photonics structure <NUM> based on the low resistivity properties of copper (Cu). Copper can include resistivity of about <NUM>×<NUM>-<NUM> Ohm-m at <NUM>. Thus, use of copper can significantly increase signal propagation speed. Embodiments herein recognize problems with use of copper, however, including copper migration and corrosion of copper. Copper can migrate into material of a dielectric stack for example. Copper can also readily oxidize and corrode resulting in increased resistivity. Dielectric layers of photonics dielectric stack <NUM> that are deposited on metallization layers can be selected to function as a barrier to resist migration of conductive material, and to inhibit corrosion attributable to oxidization. In one embodiment SiCN can be selected to form a barrier to resist migration of copper and to inhibit corrosion by oxidization of copper. SiCN has electrical migration and corrosion barrier properties. While migration of copper can be resisted with use of SiCN, embodiments herein recognize that SiCN can exhibit significant light absorption particularly in the IR band.

Embodiments herein further recognize that SiCN can inhibit performance of a photonics system. For example, embodiments herein recognize that where there is a designed photonics signal transmission path in a photonics system, a presence of SiCN can absorb light energy and accordingly can inhibit (e.g. reduce or prevent performance of) transmission of a light signal.

Referring to <FIG>, photonics structure <NUM> can include one or more designed light signal transmitting region. For example, there can be a light signal transmitting region L1 at the X dimension depth shown (depth <NUM> depicted in <FIG>) between vertically extending planes 1511A and 1512B. There can be a light signal transmitting region L2 at the depth shown between vertically extending planes 1511A and 1512A. In each light signal transmission region L1 and L2 signal light can be transmitted from a higher elevation to a lower elevation and/or from a lower elevation to a higher elevation. Light signal transmitting region L1 and light signal transmitting region L2 can transmit light signals of photonics structure <NUM> e.g. upwardly or downwardly, and in one embodiment can transmit signals vertically (about <NUM>-degree angle with respect to a horizontal plane). Light signal transmitting regions of photonics structure can transmit light signals in any direction.

Light signal transmission within light signal transmission region L1 can include light signal transmissions between photonics devices at different elevations, e.g. between two or more waveguides within light signal transmission region L1 at the respective elevations 1602A, 1602B, 1602C, 1604A, 1604B depicted in <FIG>.

Photonics structure <NUM> can be configured so that first and second waveguides of waveguides <NUM>, <NUM>, <NUM> couple light signals therebetween, or alternatively are in optical isolation from one another and do not couple light signals. Coupling between waveguides can be controlled by controlling spacing between waveguides and additional parameters, e.g. controlling spacing so that intended light signal coupling between waveguides occurs or controlling spacing so that waveguides are in optical isolation. Light signal coupling between waveguides can include e.g. evanescent coupling or tap coupling.

Light signal transmission region L1 can include an associated light input device 702A shown in dashed in form in <FIG>. Light input device 702A can be provided e.g. by a laser light source or a fiber optic cable carrying light. Light signal transmission within light signal transmission region L2 can include light signal transmissions between light input device 702B and a photonics device provided by a grating <NUM> shown in <FIG>. Light input device 702B can be provided e.g. by a laser light source or a fiber optic cable carrying light that emits light downwardly through light signal transmission region L2. The photonics device provided by a grating <NUM> depicted in <FIG> can be provided e.g. by a photonics grating that receives signal light emitted by light input device 702B. Photonics structure <NUM> can have associated light input devices 702A and 702B associated to photonics structure <NUM> for inputting light generally downwardly e.g. vertically or about vertically. Photonics structure <NUM> can additionally or alternatively have associated light input devices (e.g. laser light sources or light carrying cables) that input light into photonics structure <NUM> generally laterally e.g. horizontally or about horizontally.

A top view cross sectional view of <FIG> taken along <FIG> elevation <NUM> is shown in <FIG>. In <FIG> depth <NUM> can illustrate the cut depth of the cross-sectional Z-Y plane cross sectional view shown in <FIG> and depth <NUM> (<FIG>) can illustrate a depth into the paper with respect to the view of <FIG>. Light input device 702B can couple light downwardly to a photonics device depicted in <FIG> as being provided by a photonics grating <NUM> at about X dimension depth <NUM> (the cut depicted in <FIG>). Light input device 702A depicted in dashed form in <FIG> can couple light downwardly to the photonics device provided by grating <NUM> e.g. provided at about the X dimension depth <NUM> (<FIG>). The photonics device provided by grating <NUM> at depth <NUM> (<FIG>) can be integrally formed with a forwardly extending waveguide <NUM> as shown (extending out of the paper in <FIG>) and a photonics device provided by grating <NUM> at depth <NUM> (<FIG>) can be integrally formed with a waveguide <NUM> extending into the paper with respect to the cut depth depicted in <FIG>.

Embodiments herein recognize that the presence of light absorbing materials in the light signal transmitting region L1 between vertically extending plane 1511A and vertically extending plane 1512A and the light signal transmitting region L2 between vertically extending plane 1511B and vertically extending plane 1512B can negatively impact operation of photonics structure <NUM>. Embodiments herein recognize e.g. that a presence of SiCN within light signal transmission region L1 can inhibit light signal transmission for coupling between depicted photonics structures fabricated within dielectric stack <NUM> within light signal transmitting region L1. Embodiments herein recognize e.g. that a presence of SiCN within light signal transmission region L2 can inhibit light signal transmission between depicted light input device 702B and the photonics device provided by grating <NUM> fabricated within dielectric stack <NUM> within light signal transmitting region L2. Embodiments herein recognize that waveguides have transmission modes wherein light signals propagating through a waveguide travel partially externally to an external wall of the waveguide. Such waveguide external light can undesirably be absorbed by formations of SiCN.

Referring to areas AA of <FIG> and <FIG> aspects of (A) a process for removal of SiCN from light signal transmitting regions to reduce IR light absorption are set forth herein. Referring again to <FIG>, layers 502A, 502B, and 502C can be formed as barrier layers to inhibit migration and corrosion of conductive material formations formed of copper (Cu) or other conductive material capable of migration and/or corrosion. Conductive material formations formed of copper (Cu) can include contact conductive material formations C2-C6, metallization layer conductive material formations M1-M4 defined by metallization layers 422A-422D, and/or vias layer conductive material formations V1-V3 defined by vias layers 322A-322C.

Referring to <FIG>, there are shown a series of fabrication stage views illustrating fabrication of areas AA of photonics structure <NUM>, depicted in <FIG>. <FIG> illustrates photonics structure <NUM> in an intermediary stage of fabrication after depositing of layer <NUM> provided by SiCN.

In the stage views depicted in <FIG>, and <FIG> layer <NUM> generically represents any of layers 502A-502C, depicted in <FIG>, layer <NUM> generically represents any of layers 422A-422B, or 422D of <FIG>, pairs of vertically extending planes <NUM> and <NUM> generically represents any of pairs of vertically extending planes 1511A and 1512A, or vertically extending planes 1511B and 1512B of <FIG>, metallization layer formation M generically represents any of metallization layer formations M1, M2, or M4 depicted in <FIG>, and light signal transmitting region L generically represents any of light signal transmitting regions L1 or L2 depicted in <FIG>. Layer <NUM> in the stage views depicted in <FIG>, and <FIG> can alternatively represent a vias layer 322A-322C, another metallization layer of metallization layers 422A-422E or a layer defining contact conductive material formations C1-C6 as set forth in <FIG>.

As shown in the stage view depicted in <FIG>, depositing of SiCN can include depositing a portion of layer <NUM> on a top surface of dielectric stack <NUM> and depositing a portion of layer <NUM> on one or more section of layer <NUM>, which layer <NUM> can be formed of copper (Cu). Layer <NUM> can be formed of copper (Cu) e.g. where layer <NUM> defines a conductive material formation other than contact conductive material formation C1, a vias layer other than a vias layer defining conductive material formations V4, or a metallization layer other than a metallization layer defining conductive material formations M5. The portion of layer <NUM> deposited on dielectric stack <NUM> can extend through a light signal transmitting region defined between vertically extending plane <NUM> and vertically extending plane <NUM>.

Prior to the depositing of layer <NUM> formed of SiCN, the photonics structure <NUM> depicted in the stage view of <FIG> can be subject to CMP planarization to reduce an elevation of photonics structure <NUM> to elevation <NUM>, representative generically of any of the elevations 1602A-1602C depicted in <FIG>. The performance of CMP planarization to reduce an elevation of photonics structure <NUM> to elevation <NUM> can be accompanied by CMP polishing to polish photonics structure <NUM> at elevation <NUM>. CMP planarization can result in photonics structure <NUM> defining planar horizontal surface at elevation <NUM> prior to deposition of layer <NUM> formed of silicon carbon nitride (SiCN) so that deposition of layer <NUM> can include deposition of layer <NUM> on a planar surface.

CMP polishing can result in photonics structure <NUM> featuring an atomically smooth surface at elevation <NUM> prior to the deposition of layer <NUM>. Providing the surface of photonics structure <NUM> to be atomically smooth at elevation <NUM> can facilitate performance of light signal transmitting region L, e.g. by the reduction of unwanted light scattering.

For depositing of layer <NUM> formed of SiCN partially on metallization layer formation M, plasma enhanced chemical vapor deposition (PECVD) can be employed. PECVD can be performed with use of reduced thermal budget, e.g. in a temperature range of from about <NUM> to about <NUM>.

Still referring to the stage view of <FIG>, layer <NUM> on completion of depositing of layer <NUM> can exhibit a roughened top surface as depicted in the stage view of <FIG>.

<FIG> illustrates photonics structure <NUM> as depicted in the stage view of <FIG> after subjecting a top surface of layer <NUM> to processing for smoothing of a top surface of layer <NUM>. Photonics structure <NUM> as depicted in the intermediary stage view of <FIG> can be subject to CMP planarization to planarize the top surface of layer <NUM> so that the top surface of layer <NUM> is planar and extends in a horizontal plane. The CMP planarization can be accompanied by CMP polishing so that the top surface of layer <NUM> depicted in the intermediary stage view of <FIG> is an atomically smooth surface.

Layer <NUM> can provide a barrier to electrical migration and corrosion with respect to layer <NUM> formed of conductive material, e.g. copper (Cu) or another conductive material susceptible to electrical migration and corrosion. Layer <NUM> can be formed of copper (Cu) e.g. where layer <NUM> defines a conductive material formation other than contact conductive material formation C1, a vias layer other than a vias layer defining conductive material formations V4, or a metallization layer other than a metallization layer defining conductive material formations M5. Embodiments herein recognize that SiCN features high-quality electrical migration and corrosion barrier properties. In one embodiment, layer <NUM> which can be formed as an electrical migration and corrosion barrier layer may be subject to processing so that layer <NUM> has high quality photonics properties, so that a portion of layer <NUM> can facilitate light signal transmission through a light signal transmitting region e.g. through an elevation of layer <NUM> within light signal transmission region L. Layer <NUM> can provide electrical insulation and spacing functionality irrespective of whether the conductive material defining layer <NUM> is susceptible to electrical migration or corrosion. For example, in some embodiments layer <NUM> as depicted in the stage views of <FIG> can define contact conductive material formation C1, which can be formed of aluminum or another non-copper conductive material. In some embodiments, conductive material formations C2-C6 and/or metallization layers 422A-422D and/or vias layers 322A-322C can be formed of conductive material other than copper. As noted metallization layer 422E and vias layer 322D can be formed of aluminum (Al).

<FIG> is an intermediary fabrication stage view of photonics structure <NUM> as depicted in the stage view of <FIG> after depositing of a photolithography stack for use in etching of layer <NUM> in light signal transmitting region L between vertically extending plane <NUM> and vertically extending plane <NUM>.

The photolithography stack depicted in the intermediary fabrication stage view of <FIG> can be an organic photolithography stack. The photolithography stack depicted in the intermediary fabrication stage view of <FIG> can be a multilayer organic photolithography stack and can include layers <NUM>, <NUM>, and <NUM>. Layer <NUM> can be an organic planarization layer (OPL), layer <NUM> can be a silicon-containing anti-reflective coating (SIARC) layer, and layer <NUM> can be a resist layer. Referring to the intermediary fabrication stage view of <FIG>, the intermediary fabrication stage view of <FIG> depicts photonics structure <NUM> subsequent to patterning of layer <NUM> to define a pattern for etching away of a portion of layer <NUM> within light signal transmitting region L.

Patterning of layer <NUM> can be performed with use of a photolithography mask disposed in a photolithography tool (not shown) that is activated to expose areas of layer <NUM> not protected by the photolithography mask within the photolithography tool.

<FIG> illustrating photonics structure <NUM> as shown in <FIG> in an intermediary stage of fabrication after performance of etching using the pattern of layer <NUM> to remove material of layer <NUM> in light signal transmitting region L between vertically extending plane <NUM> and vertically extending plane <NUM>.

For performance of etching depicted in the intermediary fabrication stage view of <FIG>, reactive ion etching (RIE) can be used. RIE depicted in the intermediary stage view of <FIG> can include use of an etching process that is selective to oxide so that material of layer <NUM> provided by SiCN can be removed without removal of material of dielectric stack <NUM>. On completion of RIE as depicted in the intermediary fabrication stage view of <FIG>, etching products <NUM> can remain on photonics structure <NUM>. Etching products <NUM> can include, e.g. residual amounts of the photolithography stack including layers <NUM>, <NUM>, <NUM> and residual amounts of SiCN, which can be located on dielectric stack <NUM> depicted in light signal transmitting region L as shown in the intermediary fabrication stage view of <FIG>.

<FIG> depicts photonics structure <NUM> as shown in <FIG>, in an intermediary stage of fabrication subsequent to cleaning to remove etching products <NUM>, depicted in <FIG>. Cleaning as depicted in <FIG> can include temperature controlled cleaning to avoid damage to surfaces of photonics structure <NUM> such as a top surface of dielectric stack <NUM>. For cleaning of RIE products <NUM> a mixture that can be used that includes ammonia hydroxide (NH<NUM>OH) and peroxide (H<NUM>O<NUM>). Temperature controlled cleaning can include performing of cleaning at temperatures of about <NUM> or less.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage view of fabrication, subsequent to depositing of layer <NUM> which can be formed of cladding dielectric material e.g. oxide such as silicon dioxide (SiO2). As seen in the stage view depicted in <FIG>, layer <NUM> may have multiple elevations, e.g. a lower elevation within the light signal transmitting region L between vertically extending plane <NUM> and vertically extending plane <NUM> and a higher elevation to the left of vertically extending plane <NUM> and to the right of vertically extending plane <NUM>. The differing elevations can result from the removal of portion of layer <NUM> in the stage depicted in <FIG>.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to further processing to planarize and to polish layer <NUM>. Depicted in the intermediary fabrication stage view of <FIG>, layer <NUM> which can be formed of cladding dielectric material e.g. oxide such as SiO2 can be subject to CMP planarization to reduce an elevation of layer <NUM> and to planarize layer <NUM> so that a top surface of layer <NUM> is planar and extends in a horizontal plane. The CMP planarization to planarize layer <NUM> can be accompanied by CMP polishing to polish a top surface of layer <NUM>, so that a top surface of layer <NUM> is atomically smooth.

Example conditions for the process (A) described in connection with <FIG> are set forth in Table A.

Providing layer <NUM> to be atomically smooth can facilitate light signal transmissions through layer <NUM>. Providing processing of layer <NUM> so that a top surface of layer <NUM> is planarized and atomically smooth can provide processing planarity for subsequent fabrication including for fabrication of photonics devices. Layer <NUM> can support fabrication of a photonic device formed over layer <NUM>.

<FIG> are fabrication stage views illustrating fabrication of a photonics device provided by a waveguide <NUM> over layer <NUM>. Referring again to <FIG>, there is illustrated waveguide <NUM> in dashed line form formed on a dielectric layer that is formed on layer 502C of SiCN. However, it is understood that waveguide <NUM> shown in dashed form in <FIG> can additionally or alternatively be formed on respective dielectric layers formed on layer 502A and/or layer 502B.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication after depositing of layer <NUM>, formed of waveguiding material. Waveguiding material defining layer <NUM> can be provided, e.g. by single crystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride. Depositing of layer <NUM> formed of waveguiding material can include use of PECVD at a reduced thermal budget, e.g. at a processing temperature of from about <NUM> to about <NUM>. As depicted in the intermediary fabrication stage view of <FIG>, processing of layer <NUM> can include depositing layer <NUM> on layer <NUM> and then subjecting layer <NUM> to additional processing after deposition of layer <NUM>. The additional processing can include subjecting layer <NUM> to CMP planarization to planarize layer <NUM> so that a top surface of layer <NUM> is planar and extends in a horizontal plane. The subjecting of layer <NUM> to CMP planarization can include subjecting layer <NUM> to CMP polishing so that a top surface of layer <NUM> is atomically smooth.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to forming of a photolithography stack on layer <NUM> formed of waveguiding material. The photolithography stack depicted in <FIG> can include layer <NUM> formed of OPL, layer <NUM> formed of SIARC, and layer <NUM> formed of resist.

<FIG> illustrates photonics structure <NUM> as illustrated in <FIG> in an intermediary stage of fabrication subsequent to etching away of material of layer <NUM> formed of waveguiding material using the photolithography stack depicted in <FIG> to define waveguide <NUM>. Waveguide <NUM> can be formed of any suitable waveguiding material, e.g. monocrystalline silicon, single crystalline silicon, polycrystalline silicon, amorphous silicon, silicon nitride, or silicon oxynitride.

Regarding waveguide <NUM> shown in an intermediary stage of fabrication in <FIG>, waveguide <NUM> can include vertically extending sidewalls 218W. Anisotropic etching can be used for the formation of vertically extending sidewalls 218W. Etching to define waveguide <NUM> so that waveguide <NUM> features vertically extending sidewalls 218W can improve coupling between waveguide <NUM> and photonics devices external to waveguide <NUM>.

Vertically extending sidewalls 218W can be fabricated, using reactive ion etching (RIE). RIE can be performed or define vertically extending sidewalls 218W. RIE can include a series of etching and depositing steps. RIE for etching of layer <NUM> to define vertically extending sidewalls 218W can include use of a Bosch type RIE, and an amount of material of layer <NUM> can be removed according to an iterative etch step followed by an iterative deposit step. In each iterative deposit step, material can be deposited on a defined sidewall 218W. Deposited material deposited on sidewall 218W can include a polymer material. Following each iterative depositing step, there can be performed a further etching to etch away another amount of material of layer <NUM> formed of waveguiding material.

Vertically extending sidewalls 218W which can be formed, e.g. using a Bosch process can be subject to line edge roughness treatment. In the case where waveguide <NUM> is formed of nitride. line edge roughness treatment can include application of a steam or high pressure oxidation at moderate to high temperatures to convert a few outermost nanometers of the silicon nitride (SiCN) defining waveguide <NUM> to form silicon dioxide (SiO2). The formed SiO2 can then be subject to removal by immersion in an aqueous hydrofluoric solution to remove the formed SiO2 in order to improve line edge roughness of the defined waveguide <NUM>. In the case waveguide <NUM> is formed of silicon line edge roughness treatments can include H2 annealing using reduced pressure chemical vapor deposition (RPCVD) or rapid thermal chemical vapor deposition (RTCVD) processing or depositing epitaxial silicon on the surfaces to reduce line edge roughness.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to depositing of layer <NUM> formed of dielectric material, e.g. SiO2. A PECVD process can be used for deposition of layer <NUM> at a reduced thermal temperature budget, e.g. using a temperature in the range of about <NUM> to about <NUM>. Depositing of layer <NUM> can include depositing non-conformal material over defined waveguide <NUM> patterned as described in connection with <FIG>.

Depositing of layer <NUM> can include use of PECVD with high aspect ratio processing (HARP). Non-conformality may be achieved using plasma enhancements during a deposition phase with conditions tuned to enhance deposition rates on horizontal surfaces while suppressing deposition rates on vertical surfaces (e.g. on step edges defined with use of a Bosch process). Thus, voids and other defects resulting from pinch off of a cladding layer can be avoided and detrimental effects of the same on photonics signal transmission can be minimized. Layer <NUM> can be formed of non-conformal oxide material, e.g. non-conformal SiO2. Use of non-conformal oxide material for layer <NUM> can reduce in incidents of voids and other defects in dielectric stack <NUM> that surrounds waveguide <NUM>. A non-conformal oxide material can be a material that is adapted to a deposit at a higher rate, on horizontal surfaces while exhibiting a suppressed sidewall deposition rate. In a method for providing non-conformal oxide material a deposition of oxide material can be plasma enhanced. It can be envisioned (but is not depicted) that with the use of conformal material for use of layer <NUM> pinch off can occur when layer <NUM> is deposited over high aspect ratio features and accordingly can result in an introduction of voids with oxide surrounding waveguides such as waveguides <NUM>.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG>, subsequent to further processing of layer <NUM> formed of a cladding dielectric material e.g. oxide such as SiO2 to define a cladding layer. Referring to <FIG> a top surface of layer <NUM> can be subject to CMP planarization to reduce an elevation of layer <NUM> and to provide processing so that a top surface of layer <NUM> is planar and extends in a horizontal plane to provide processing planarity for subsequent layers. CMP planarization can be accompanied by CMP polishing so that a top surface of layer <NUM> is atomically smooth.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to depositing of layer <NUM>. Layer <NUM> can be provided by capping dielectric material e.g. oxide such as SiO2. Depositing of layer <NUM> can include use of a saline based PECVD at a reduced thermal budget, e.g. at a temperature of between about <NUM> and about <NUM>. Layer <NUM> can be regarded as a capping layer.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to further processing of layer <NUM>. Further processing of layer <NUM> depicted in <FIG> can include subjecting layer <NUM> to CMP planarization to provide a top surface of layer <NUM> so that a top surface of layer <NUM> is planar and extends in a horizontal plane. CMP planarization of layer <NUM> can be accompanied by CMP polishing so that a top surface of layer <NUM> is atomically smooth.

Photonics devices of photonics structure <NUM> can transmit or receive light signals transmitted through elevation <NUM> within light signal transmitting region L with material of layer <NUM> removed within light signal transmitting region. Light signal coupling can be between any two waveguides within light signal transmitting region including a waveguide <NUM> of <FIG> if fabricated. Light signal coupling can be between a light input device 702B and a the photonics device provided by grating <NUM> in light signal transmitting region L2.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to deposition of layer <NUM> and further processing of layer <NUM>. Referring to <FIG>, layer <NUM> can be a waveguiding layer provided, e.g. by single crystalline silicon, polycrystalline silicon, silicon nitride, or silicon oxynitride, deposited on a top surface of layer <NUM> using e.g. PECVD and a reduced thermal budget, e.g. in a temperature range of from about <NUM> to about <NUM>. As depicted in <FIG>, layer <NUM> can be subject to further processing to define waveguide <NUM> depicted in dashed form of <FIG>. Patterning to define waveguide <NUM> depicted in dashed form in <FIG> can be performed according to the processing to define waveguide <NUM> (not dashed) as depicted in <FIG>, subsequent to patterning to define waveguide <NUM> depicted in dashed form of <FIG>. The defined waveguide <NUM> depicted in dashed form can be subject to further processing as depicted with reference to waveguide <NUM> (not dashed) described in reference to <FIG> to surround the additional waveguide <NUM> defined by layer <NUM> with a cladding dielectric material e.g. oxide and then forming on the cladding dielectric material oxide a capping dielectric material, e.g. oxide. Use of plural dielectric e.g. oxide layers such as may be provided by layer <NUM> and <NUM> between waveguides <NUM> (dashed and not dashed) as depicted in <FIG> provides for controlled spacing distance between waveguides, useful for achieving design tolerances in accordance with the specified design. For example, spacing distances can be readily achieved so that different waveguides can couple light signals therebetween when light coupling is desired and can be prevented from coupling light signals therebetween when photonics isolation is specified in a design specification for photonics structure <NUM>.

Aspects of a process (B) for removal of silicon nitride (SiN) are now described. In one aspect, now described in reference to areas BB of <FIG> and fabrication stage view of <FIG>. Referring again to <FIG>, layers 602A and 602B can be formed as barrier layers to inhibit migration and corrosion of conductive material formations formed of copper (Cu) or other conductive material capable of migration and/or corrosion. Conductive material formation formed of copper can include contact conductive material formations C2-C6, metallization layer conductive material formations M1-M4 defined by metallization layers 422A-422D, and/or vias layer conductive material formations V1-V3 defined by vias layers 322A-322C.

Embodiments herein recognize that silicon nitride (SiN) has significant electrical migration and corrosion barrier properties. SiN can inhibit the electrical migration of copper and corrosion of copper. Embodiments herein further recognize that use of silicon nitride in photonics structure <NUM> can present risk and that due to the index of refraction of silicon nitride, silicon nitride material can undesirably couple light signals transmitted within light signal transmitting region L1 between vertically extending plane <NUM> and vertically extending plane <NUM> wherein light signals can be desirably coupled between photonics devices e.g. including waveguides and light signals transmitted within light signal transmitting region L2 between vertically extending plane 1511B and vertically extending plane 1512B wherein a light signal can be introduced to photonics structure <NUM> by light input device 702B.

The process (B) for removal of silicon nitride can result in the removal of silicon nitride from light signal transmitting region L1 or L2. Referring to details of a process (B) for removal of silicon nitride from a light signal transmitting region there are provided fabrication stage views depicted in <FIG>.

In the fabrication stage views depicted in <FIG>, layer <NUM> generically represents any of layers 602A or 602B, depicted in <FIG>, layer <NUM> of <FIG> generically represents any of layer 422C or the layer(s) forming contact conductive material formations C2, C3, C4, and C5 of <FIG>, vertically extending planes <NUM> and <NUM> generically represents any of pairs of vertically extending planes such as vertically extending planes 1511A and 1512A, or vertically extending planes 1511B and 1512B of <FIG>, conductive material formation M of <FIG> generically represents any of metallization layer formation M3 or conductive material formations C2, C3, C4, and C5 depicted in <FIG>, and light signal transmitting region L generically represents any of light signal transmitting regions L1 or L2 depicted in <FIG>. Layer <NUM> in the stage views depicted in <FIG> can alternatively represent a vias layer 322A-322C, another metallization layer of metallization layers 422A-422E or a layer defining one or more other contact conductive material formation of contact conductive material formations C1-C6 as set forth in <FIG>.

Referring to the intermediary stage view of <FIG>, layer <NUM> can be deposited on dielectric stack <NUM> and layer <NUM> as depicted in <FIG> with a portion of layer <NUM> being deposited on a top surface of dielectric stack <NUM> within light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM> and a portion of layer <NUM> being deposited on layer <NUM>. The portion of layer <NUM> deposited on layer <NUM> can include a first section located to the left of vertically extending plane <NUM> and a second section located to the right of vertically extending plane <NUM>.

Referring to the depositing in the fabrication stage view of <FIG>, a portion of layer <NUM> can be deposited on a top surface of dielectric stack <NUM> in the fabrication stage view depicted, which dielectric stack <NUM> can be provided, e.g. in one embodiment by a plurality of layers of oxide such as SiO2.

Prior to the depositing of layer <NUM>, photonics structure <NUM> as depicted in <FIG> can be subject to CMP planarization to reduce an elevation of the surface defined by layer <NUM> formed of conductive material and dielectric stack <NUM> to reduce the elevation of such defined surface and to planarize the defined surface so that the defined surface extends in a horizontal plane at elevation <NUM>. The CMP planarization can be accompanied by CMP polishing so that the defined planar surface extending horizontally at elevation <NUM> is atomically smooth.

For the depositing of layer <NUM> onto the planar surface defined by layer plasma enhanced chemical vapor deposition (PECVD) can be employed. PECVD can be performed at the use of reduced thermal budget, e.g. at temperatures in a temperature range of between about <NUM> and about <NUM>.

Layer <NUM> can provide a barrier to electrical migration and corrosion with respect to layer <NUM> formed of conductive material, e.g. copper (Cu) or another conductive material susceptible to electrical migration and corrosion. Layer <NUM> can be formed of copper (Cu) e.g. where layer <NUM> defines a conductive material formation other than contact conductive material formation C1, a vias layer other than conductive material formation V4, or a metallization layer other than conductive material formation M5. Embodiments herein recognize that SiN features high-quality electrical migration and corrosion barrier properties. In one embodiment, layer <NUM> which can be formed as an electrical migration and corrosion barrier layer may be subject to processing so that layer <NUM> has high quality photonics properties, so that a portion of layer <NUM> can be removed to facilitate light signal transmission through a light signal transmitting region, e.g. through an elevation of layer <NUM> within light signal transmission region L and, according to the claimed invention, is patterned to define a waveguide for transmission of a light signal. Layer <NUM> can provide electrical insulation and spacing functionality irrespective of whether the conductive material defining layer <NUM> is susceptible to electrical migration or corrosion. For example, in some embodiments layer <NUM> as depicted in the stage views of <FIG> can define contact conductive material formation C1, which can be formed of aluminum or another non-copper conductive material. In some embodiments, conductive material formations C2-C6 and/or metallization layers 422A-422D and/or vias layers 322A-322C can be formed of conductive material other than copper. As noted metallization layer 422E and vias layer 322D can be formed of aluminum (Al).

On completion of the depositing stage as depicted in <FIG>, layer <NUM> can be deposited. However, on the depositing of layer <NUM> the top surface of layer <NUM> can be roughened, depicted in <FIG>.

Now referring to the intermediary stage view of <FIG> layer <NUM> (shown in roughened form in <FIG>) can be subject to processing for planarizing and polishing of layer <NUM>, namely a top surface of layer <NUM>. Layer <NUM> as depicted in <FIG> is subject to planarization, e.g. by CMP planarization so that a top surface of layer <NUM> is planarized and extends in a horizontal plane parallel to the X-Y horizontal plane defined by the depicted reference coordinate system shown in connection with <FIG>. The CMP planarization can be accompanied by CMP polishing so that a top planar surface of layer <NUM> is atomically smooth.

Referring to the stage views of <FIG> layer <NUM> provided by SiN is subject to processing for removal of at least a portion of layer <NUM> from a light signal transmitting region L between vertically extending plane <NUM> and vertically extending plane <NUM>. Regarding the depositing of layer <NUM>, deposition pressure, power, and flow rate can be controlled to provide layer <NUM> so that layer <NUM> features an index of refraction of about <NUM>.

For patterning of layer <NUM>, a multilayer organic photolithography stack can be deposited over layer <NUM>. A multilayer photolithography stack as shown in <FIG> can include layer <NUM>, layer <NUM>, and layer <NUM>. Layer <NUM> can be provided by an organic planarization layer (OPL). Layer <NUM> can facilitate protection of layer <NUM>. Layer <NUM> can be provided by a silicon-containing anti-reflective coating (SIARC) layer, and layer <NUM> can be provided by a resist layer. Layer <NUM> can include about <NUM>% silicon in one embodiment.

Referring further to the patterning stack depicted in the intermediary fabrication stage view of <FIG>, the stage view of <FIG> depicts photonics structure <NUM> subsequent to patterning of layer <NUM> formed of resist. Patterning of layer <NUM> can include exposing layer <NUM> (not shown) having a mask disposed therein including an inverse of the pattern of layer <NUM>.

<FIG> illustrates photonics structure <NUM> after performance of processing described with reference to the intermediary fabrication stage view of <FIG> illustrates photonics structure <NUM> as depicted in <FIG> after performance of etching to remove material of layer <NUM>. Etching can be selective to dielectric material e.g. oxide defining dielectric stack <NUM> so that material of layer <NUM> is removed without removal of material of dielectric stack <NUM>. Etching can be performed according to the pattern of the multilayer photolithography stack having layers <NUM>, <NUM>, and <NUM> so that etching selectively removes material of layer <NUM> without removal of material of dielectric stack <NUM>. Etching can include use of reactive ion etching (RIE).

Vertically extending sidewalls 214W of defined waveguide <NUM> depicted in the intermediary stage of fabrication of <FIG> can be fabricated in one embodiment, using reactive ion etching (RIE). RIE can be performed or define vertically extending sidewalls 214W. RIE can include a series of etching and depositing steps. RIE for etching of layer <NUM> to define vertically extending sidewalls 214W can include use of a Bosch type RIE, and in one embodiment an amount of material of layer <NUM> can be removed according to an iterative etch step followed by an iterative deposit step. In each iterative deposit step, material can be deposited on a defined sidewall 214W. Deposited material deposited on sidewall 214W can include a polymer material. Following each iterative depositing step, there can be performed a further etching to etch away another amount of material of layer <NUM> formed of waveguiding material provided by SiN in the embodiment described.

Vertically extending sidewalls 214W which can be formed, e.g. using a Bosch process can be subject to line edge roughness treatment. In a case where waveguide <NUM> is formed of nitride as depicted in <FIG> line edge roughness treatment can include application of a steam or high pressure oxidation at moderate to high temperatures to convert a few outermost nanometers of the silicon nitride (SiN) defining waveguide <NUM> to form silicon dioxide (SiO2). The formed SiO2 can then be subject to removal by immersion in an aqueous hydrofluoric solution to remove the formed SiO2 in order to improve line edge roughness of the defined waveguide <NUM>.

On the completion of performance of etching as depicted in <FIG> etching products <NUM> can remain on a top surface of the photonics structure <NUM> depicted in the intermediary stage of fabrication depicted in <FIG>. Etching products <NUM> can include e.g. portions of the photolithography stack having layers <NUM>, <NUM>, and <NUM> and residual amounts of SiN from layer <NUM>.

<FIG> illustrates photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication subsequent to processing to remove etching products <NUM>. Cleaning etching products <NUM> can include e.g. use of a mixture of ammonia hydroxide (NH<NUM>OH) and peroxide (H<NUM>O<NUM>). Cleaning etching products <NUM> can include use a low temperature cleaning process, e.g. performed at a temperature of about <NUM> or less.

<FIG> illustrates the photonics structure <NUM> as depicted in <FIG> in an intermediary stage of fabrication after depositing of layer <NUM> which can be formed of cladding dielectric material e.g. oxide such as silicon dioxide (SiO2). Depositing of layer <NUM> can include use of PECVD with high aspect ratio processing (HARP). Non-conformality may be achieved using plasma enhancements during a deposition phase with conditions tuned to enhance deposition rates on horizontal surfaces while suppressing deposition rates on vertical surfaces (e.g. on step edges defined with use of a Bosch process). Thus, voids and other defects resulting from pinch off of a cladding layer can be avoided and detrimental effects of the same on photonics signal transmission can be minimized. In one embodiment, layer <NUM> can be formed of non-conformal oxide material, e.g. SiO2. Use of non-conformal oxide material for layer <NUM> can reduce in incidents of voids and other defects in dielectric stack <NUM> that surrounds waveguide <NUM>. A non-conformal oxide material can be a material that is adapted to a deposit at a higher rate, on horizontal surfaces while exhibiting a suppressed sidewall deposition rate. In one embodiment, of a method for providing non-conformal oxide material a deposition of oxide material can be plasma enhanced. It can be envisioned (but is not depicted) that with the use of conformal material for use of layer <NUM> pinch off can occur when layer <NUM> is deposited over high aspect ratio features and accordingly can result in an introduction of voids with oxide surrounding waveguides such as waveguides <NUM>. Processing conditions can be tuned to that layer <NUM> features an index of refraction of about <NUM>.

Layer <NUM> can define a cladding dielectric layer. Layer <NUM> can be deposited using a high aspect ratio PECVD process as set forth herein. In a stage view depicted in <FIG> it is seen that layer <NUM> on the deposition thereof can have multiple elevations, i.e. dips in the areas above which layer <NUM> has been etched.

<FIG> depicts photonics structure <NUM> as shown in <FIG> in an intermediary stage of fabrication after planarizing of layer <NUM>. For planarizing of layer <NUM>, a chemical/mechanical planarization (CMP planarization) process can be used. On the performance of planarization, an elevation of a top surface of layer <NUM> can be reduced and planarized to extend in a horizontal plane parallel with the reference coordinate system X-Y plane at elevation <NUM>. CMP planarization can be accompanied by CMP polishing so that a top surface of layer <NUM> is atomically smooth.

Patterning of layer <NUM> includes patterning to define waveguide <NUM> formed of silicon nitride (SiN) within the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM>. Thus, by way of patterning of layer <NUM> which can be a single layer in one embodiment there can be defined multiple formations that provide different functions. A first formation defined by patterning of layer <NUM> can be a migration and corrosion barrier formation, e.g. as provided by portions of layer <NUM> formed on layer <NUM> formed of conductive material. A second formation defined by patterning of layer <NUM> is a photonics device formation provided by waveguide <NUM> depicted in <FIG>.

According to the fabrication stages depicted in the stage views of <FIG>, layer <NUM> formed of silicon nitride (SiN) is deposited and then patterned to define both of a formation provided by a barrier formation for inhibiting conductive material e.g. copper (Cu) migration and conductive material corrosion and a formation provided by a waveguide <NUM>.

Process (B), not being part of the claimed invention, which can include patterning of a silicon nitride (SiN) layer to remove material of layer <NUM> from a light signal transmitting region L can be provided in the manner depicted with reference to the stage views of <FIG> except that processing can be absent of processing to define waveguide <NUM> in the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM>. In accordance with the processing described with reference to the stage views of <FIG>-<NUM>, processing of layer <NUM> can be performed so that material of layer <NUM> provided by SiN can be entirely removed in the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM>.

Referring again to <FIG> in one embodiment, patterning of layer <NUM> can be performed in one embodiment so that waveguide <NUM> is defined within light transmitting region L1 defined at about the depth <NUM> (<FIG>) and further so that waveguide <NUM> is not defined within light transmitting region L2 defined at about the same depth <NUM> (<FIG>) depicted in <FIG>. Further referring to <FIG>, layer 602B formed of SiN can patterned for defining waveguide <NUM> within light signal transmitting region L1 and layer 602A formed of SiN may not be patterned for defining waveguide <NUM> within light signal transmitting region L1. In one embodiment, not being part of the claimed invention, neither of layer 602A nor layer 602B may be patterned for formation of waveguide <NUM> within light signal transmitting region L1.

Providing such alternative processing can include changing the pattern of the photolithography stack including layers <NUM>, <NUM>, <NUM> at different region in the X-Y plane so that the portion of layer <NUM> formed of resist in the light signal transmitting region L between vertically extending plane <NUM> and vertically extending plane <NUM> is removed in a manner so that the formation provided by waveguide <NUM> is not defined by the etching of layer <NUM> depicted in the stage view of <FIG>. The resulting structure resulting from the described alternative processing is shown in <FIG>.

Removal of material of layer <NUM> from the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM> as depicted in the stage views of <FIG> can avoid unwanted light coupling between transmitting light rays and silicon nitride formations whether or not a photonics device defined by layer <NUM> is defined by the patterning. Removal of material of layer <NUM> from the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM> as depicted in the stage views of <FIG> can facilitate light signal coupling between photonics devices defined above or below layer <NUM> within light transmitting region L (as depicted with reference to light transmitting region L1 of <FIG>). Removal of material of layer <NUM> from the light signal transmitting region L defined between vertically extending plane <NUM> and vertically extending plane <NUM> as depicted in the stage views of <FIG> can facilitate light signal coupling between a light input device and a photonics device fabricated within dielectric stack (as depicted with reference to light transmitting region L2 of <FIG>).

Photonics devices of photonics structure <NUM> can transmit or receive light signals transmitted through elevation <NUM> within light signal transmitting region L with material of layer <NUM> removed within light signal transmitting region L. Light signal coupling can be between any two waveguides <NUM>, <NUM>, <NUM> on opposite sides of elevation <NUM> within light signal transmitting region L1. Additionally or alternatively, light signal coupling can include light signal coupling of any waveguide <NUM>, <NUM>, <NUM> within light signal transmitting region L1 and waveguide <NUM> (<FIG>) fabricated at elevation <NUM> if fabricated. Light signal coupling can be between a light input device 702B and a photonics device provided by a grating <NUM> in light signal transmitting region L2.

Example conditions for the process (B) described in connection with <FIG> are set forth in Table B according to one embodiment.

Waveguides as set forth herein such as waveguides <NUM>, <NUM>, and/or <NUM> within light sensitive region L1 as shown in <FIG>, <FIG>, or <FIG> can have respective light transmission axes running in parallel with the X axis of the reference coordinate system shown.

Atomically smooth surfaces set forth herein in various embodiments can refer to surfaces having smoothness ratings of about < 5A RMS in one embodiment. Atomically smooth surfaces set forth herein in various embodiments can refer to surfaces having smoothness ratings of about < 4A RMS in one embodiment. Atomically smooth surfaces set forth herein in various embodiments can refer to surfaces having smoothness ratings of about < 3A RMS in one embodiment. Atomically smooth surfaces set forth herein in various embodiments can refer to surfaces having smoothness ratings of about < 2A RMS in one embodiment.

Referring again to <FIG>, fabricating of photonics structure <NUM> can further include etching of dielectric stack <NUM> to define trenches exposing top surfaces of metallization layer conductive material formations M5 and in some embodiments fabricating of further features within such trenches further adapting photonics structure <NUM> for electrical and/or mechanical connection to one or more structure external to photonics structure <NUM>.

The term "on" in one embodiment refers to a relationship where an element is "directly on" a specified element without intervening elements between the element and the specified element. It will be further understood that the terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including"), and "contain" (and any form contain, such as "contains" and "containing") are open-ended linking verbs. As a result, a method or device that "comprises," "has," "includes," or "contains" one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that "comprises," "has," "includes," or "contains" one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Forms of the term "defined by" encompass relationships where an element is partially defined by as well relationships where an element is entirely defined by. Numerical identifiers herein, e.g. "first" and "second" are arbitrary terms to designate different elements without designating an ordering of elements.

Claim 1:
A method comprising:
depositing a layer (<NUM>) formed of silicon nitride so that the layer (<NUM>) formed of silicon nitride includes a first portion extending through a light signal transmitting region (L) of a photonics structure (<NUM>), and further so that the layer (<NUM>) formed of silicon nitride includes a second portion formed on a conductive material formation (<NUM>), wherein the first portion extending through the light signal transmitting region is formed on a dielectric stack (<NUM>);
removing material of the first portion of the layer (<NUM>) formed of silicon nitride that is formed on the dielectric stack (<NUM>) to expose the dielectric stack (<NUM>) within the light signal transmitting region (L);
depositing a layer (<NUM>) of cladding dielectric material so that a portion of the layer (<NUM>) of cladding dielectric material is formed on the layer (<NUM>) formed of silicon nitride and a portion of the layer (<NUM>) of cladding dielectric material is formed on the exposed portion of the dielectric stack (<NUM>) formed within the light signal transmitting region (L); and
planarizing the layer (<NUM>) of cladding dielectric material so that a top surface of the cladding dielectric material extends in a horizontal plane;
characterized in that removing material of the first portion of the layer (<NUM>) formed of silicon nitride that is formed on the dielectric stack (<NUM>) to expose the dielectric stack (<NUM>) within the light signal transmitting region (L) includes patterning within the light signal transmitting region (L) a silicon nitride waveguide (<NUM>), the silicon nitride waveguide (<NUM>) defined by the layer (<NUM>) formed of silicon nitride.