Patent Description:
<CIT> describes a distortion generating circuit. <CIT> describes a transistorized broadband amplifier with gain control.

According to a first aspect of the present disclosure there is provided an attenuation circuit according to claim <NUM>.

Advantageously, such a circuit can have low insertion loss, low gain-to-phase error and a compact layout size.

In one or more embodiments the attenuation circuit is in an attenuation mode of operation when the first-control-signal has a higher voltage than the second-control-signal.

In one or more embodiments the attenuation circuit is in a bypass mode of operation when the first-control-signal has a lower voltage than the second-control-signal.

In one or more embodiments the first-attenuation-resistor and the first-attenuation-diode are connected in series with each other, in that order, between the first-control-node and the internal-node.

In one or more embodiments the second-attenuation-diode and the second-attenuation-resistor and are connected in series with each other, in that order, between the internal-node and the second-control-node.

In one or more embodiments the attenuation circuit may further comprise a tuning-inductor connected in series between the connection-node and an AC-reference-node.

In one or more embodiments the attenuation circuit may further comprise:.

In one or more embodiments the attenuation circuit may further comprise one or both of:.

In one or more embodiments the first-attenuation-diode and the second-attenuation-diode are PiN diodes.

In one or more embodiments the attenuation circuit may further comprise an amplifier-inductor connected in series between the connection-node and a supply-node. The amplifier-inductor may be configured to: provide some of the functionality of an amplifier that provides an output signal to the connection-node; and compensate for the off-capacitance of the first- and second-attenuation-diodes.

There is also provided an amplifier circuit comprising:.

In one or more embodiments the amplifier circuit further comprises an inter-stage matching network connected in series between the connection node of the attenuation circuit and the additional-amplifier-input-terminal of an additional amplifier.

In one or more embodiments the amplifier circuit further comprises a control signal generator that is configured to provide the first-control-signal and the second-control-signal such that:.

It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications and alternative embodiments falling within the scope of the appended claims are covered as well.

The above discussion is not intended to represent every example embodiment or every implementation within the scope of the Claim sets. The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

Digital-step-attenuators (DSA) have many applications. One of the key applications is an analog beamformer.

<FIG> shows block diagrams of one channel in an analog beamformer line up.

<FIG> shows a configuration in which the transmitter and the receiver do not work at the same time (e.g. for the application of time division duplex (TDD) communication). <FIG> shows a TRX channel input <NUM>, the DSA <NUM>, a phase shifter <NUM>, a single pole double toggle (SPDT) switch <NUM>, a power amplifier (PA) <NUM> (which can be single or several stages amplifier), a low noise amplifier (LNA) <NUM> (single or several stages amplifier), and an antenna <NUM>. The positions of the DSA <NUM> and the phase shifter <NUM> as they are shown in <FIG> can be swapped. The TRX channel input <NUM> can be connected to a power combiner/splitter for multiple channel operation.

<FIG> shows a configuration in which the transmitter and the receiver can work at the same time (e.g. for the application of radar). Components of <FIG> that are also in <FIG> have been given the same reference numbers. <FIG> also shows an input <NUM> of the transmitter, an output <NUM> of the receiver, an output antenna <NUM> of the transmitter, and an input antenna <NUM> of the receiver.

<FIG> shows an example of a <NUM>-bit attenuation circuit. The attenuation circuit includes a connection-node <NUM> for connecting to an RF connection, such as an RF input terminal <NUM> or an RF output terminal <NUM>.

The attenuation circuit does not include any components in series in between the RF input terminal <NUM> and the RF output terminal <NUM>. That is, the attenuation circuit includes only a single connection-node <NUM> for connecting to the RF connection / transmission line such that the attenuation circuit is in a shunt connection with the RF signal path. In this way, insertion losses and the layout size can be reduced, when compared with a circuit that includes components (such as switches or series capacitors) in series between the RF input terminal <NUM> and an RF output terminal <NUM>.

As will be described below, the attenuation circuit has an attenuation mode of operation and a bypass mode of operation. In the attenuation mode of operation, the power of the RF signal at the RF connection is attenuated such that the power of the RF signal at the RF output terminal <NUM> is lower than the power at the RF input terminal <NUM>. In the bypass mode of operation, no significant attenuation occurs such that the power of the RF signal at the RF output terminal <NUM> is about the same as the power at the RF input terminal <NUM>.

The attenuation circuit includes a first-control-node (V1) <NUM> that receives a first-control-signal, and also includes a second-control-node (V2) <NUM> that receives a second-control-signal. As will be discussed below, the first-control-signal and the second-control signal can be provided in order to cause the attenuation circuit to operate in either the attenuation or the bypass mode of operation. The attenuation circuit also includes a reference-node <NUM> for connecting to a reference terminal. In this example the reference terminal is ground.

The attenuation circuit includes an isolation-capacitor (C3) <NUM>, which is connected in series between the connection-node and an internal-node <NUM>. The isolation-capacitor (C3) <NUM> can be a large DC decoupling capacitor that prevents any DC components at the RF connection from being passed to the other components of the attenuation circuit.

The attenuation circuit includes: a first-bias-resistor (Rbias) <NUM> connected in series between the first-control-node (V1) <NUM> and the internal-node <NUM>; and a second-bias-resistor <NUM> (Rbias) connected in series between the internal-node <NUM> and the second-control-node (V2) <NUM>. The presence of the first- and second-bias-resistors <NUM>, <NUM> is particularly relevant when the attenuation circuit is in the bypass mode of operation, as will be discussed below.

The attenuation circuit also includes: a first-attenuation-diode (D1) <NUM> connected in series between the first-control-node (V1) <NUM> and the internal-node <NUM>; and a second-attenuation-diode (D2) <NUM> connected in series between the internal-node <NUM> and the second-control-node (V2) <NUM>. The anode of the first-attenuation-diode (D1) <NUM> is closest to the first-control-node (V1) <NUM> (in the electrical current flow path between the first-control-node (V1) <NUM> and the internal-node <NUM>), such that the first-attenuation-diode (D1) <NUM> is forward biased when the voltage at the first-control-node (V1) <NUM> is higher than the voltage at the internal-node <NUM>. The anode of the second-attenuation-diode (D2) <NUM> is closest to the internal-node <NUM> (in the electrical current flow path between the internal-node <NUM> and the second-control-node (V2) <NUM>), such that the second-attenuation-diode (D2) <NUM> is forward biased when the voltage at the internal-node <NUM> is higher than the voltage at the second-control-node (V2) <NUM>. As will be discussed below, the presence of the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> is particularly relevant when the attenuation circuit is in the attenuation mode of operation. In this example the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> are PiN diodes, although in other examples different types of diodes can be used.

Finally, the attenuation circuit of Figure includes: a first-decoupling-capacitor (C1) <NUM> connected in series between the first-control-node (V1) <NUM> and the reference-node <NUM>; and a second-decoupling-capacitor (C2) <NUM> connected in series between the second-control-node (V2) <NUM> and the reference-node <NUM>. The first- and second-decoupling-capacitors (C1, C2) <NUM>, <NUM> can be large DC decoupling capacitors that prevent any significant AC coupling between the attenuation circuit and the reference-node / ground <NUM>. In this way, the first- and the second-control-nodes (V1, V2) <NUM>, <NUM> can be considered as "AC ground".

In order to put the attenuation circuit in the bypass mode of operation, the first-control-signal (at the first-control-node (V1) <NUM>) has a lower voltage than the second-control-signal (at the second-control-node (V2) <NUM>). For example, the first-control-node (V1) <NUM> can be biased with a low volage such as 0V, and the second-control-node (V2) <NUM> can be biased with a high volage such as a supply voltage (Vcc). With such control signals, the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> are reverse biased and turned off. The first- and second-bias-resistors (Rbias) <NUM>, <NUM> can beneficially assist in ensuring that the voltage at the internal-node is properly biased to (V1+V2)/<NUM> (that is the mid-point between the first- and second-control-signals). The first- and second-bias-resistors (Rbias) <NUM>, <NUM> can be relatively large (~<NUM> KOhm) such that they can provide the functionality of DC bias resistors. This can be especially useful where the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> are PiN diodes that have very high and sensitive DC resistance when they are in their off state. Furthermore, when the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> are turned off, they have a small capacitance (Coff) and provide a high Ohmic impedance loading at the connection-node <NUM>. Thus, the RF signal directly passes from the RF input terminal <NUM> to the RF output terminal <NUM> without any significant attenuation.

In order to put the attenuation circuit in the attenuation mode of operation, the first-control-signal (at the first-control-node (V1) <NUM>) has a higher voltage than the second-control-signal (at the second-control-node (V2) <NUM>). For example, the first-control-node (V1) <NUM> can be biased with a high volage such as a supply voltage (Vcc), and the second-control-node (V2) <NUM> can be biased with a low volage such as 0V. With such control signals, the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> are forward biased and turned on. The on-resistance (Ron) of the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> sets the loading impedance at the connection-node <NUM> in order to control the attenuation ratio.

One specification of a DSA is the gain-to-phase error, which means that the output signal (i.e. the RF signal at the RF output terminal <NUM>) should have a constant phase response when switching between the bypass and the attenuation modes of operation. In this example the off-capacitance (Coff) of the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> is sufficiently small such that the gain-to-phase error is acceptable. In other examples, as will discussed below, a tuning-inductor can be used to further improve the gain-to-phase error.

<FIG> shows an example embodiment of a <NUM>-bit attenuation circuit.

The circuit of <FIG> includes all of the components of <FIG>, which have been labelled with corresponding reference numbers in the <NUM> series.

The attenuation circuit of <FIG> also includes a tuning-inductor (L1) <NUM> connected in series between the connection-node <NUM> and an AC-reference-node, such as AC ground. In this example the AC-reference-node is the same reference-node <NUM> to which the first- and second-decoupling-capacitors (C1, C2) <NUM>, <NUM> are connected, although in other examples the AC-reference-node can be any other reference node such as a supply-node. The tuning-inductor (L1) <NUM> can also be referred to as a shunt inductor. The tuning-inductor (L1) <NUM> is used to tune out the off-capacitance (Coff) of the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> and thereby further improve gain-to-phase error. Simulation results that illustrate this improvement in gain-to-phase error are described below.

The attenuation circuit of <FIG> also includes a first-attenuation-resistor (R1) <NUM> and a second-attenuation-resistor (R2) <NUM>. The first-attenuation-resistor (R1) <NUM> and the first-attenuation-diode (D1) <NUM> are connected in series with each other between the first-control-node (V1) <NUM> and the internal-node <NUM>. The second-attenuation-resistor (R2) <NUM> and the second-attenuation-diode (D2) <NUM> are connected in series with each other between the internal-node <NUM> and the second-control-node (V2) <NUM>. The first- and second-attenuation-resistors (R1, R2) <NUM>, <NUM> combine the on-resistances (Ron) of the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> to set the loading impedance at the connection-node <NUM>, as discussed below with reference to equations <NUM> to <NUM>.

In this example, the first-attenuation-resistor (R1) <NUM> and the first-attenuation-diode (D1) <NUM> are connected in series with each other, in that order, between the first-control-node (V1) <NUM> and the internal-node <NUM>. A first terminal of the first-attenuation-resistor (R1) <NUM> is connected to the first-control-node (V1) <NUM>. A second terminal of the first-attenuation-resistor (R1) <NUM> is connected to the anode of the first-attenuation-diode (D1) <NUM>. The cathode of the first-attenuation-diode (D1) <NUM> is connected to the internal-node <NUM>. It will be appreciated that in some examples each of these connections can be indirect connections, in that one or more intermediate components can be provided between the connections without preventing the desired functionality of the attenuation circuit. Either way, the first-attenuation-diode (D1) <NUM> is closer to the internal-node <NUM> than the first-attenuation-resistor (R1) in this example.

Similarly, in this example the second-attenuation-diode (D2) <NUM> and the second-attenuation-resistor (R2) <NUM> are connected in series with each other, in that order, between the internal-node <NUM> and the second-control-node (V2) <NUM>. The anode of the second-attenuation-diode (D2) <NUM> is connected to the internal-node <NUM>. The cathode of the second-attenuation-diode (D2) <NUM> is connected to a first terminal of the second-attenuation-resistor (R2) <NUM>. A second terminal of the second-attenuation-resistor (R2) <NUM> is connected to the second-control-node (V2) <NUM>. Again, in some examples each of these connections can be indirect connections. Either way, the second-attenuation-diode (D2) <NUM> is closer to the internal-node <NUM> than the second-attenuation-resistor (R2) <NUM> in this example.

It has been found that putting the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> in the center of the attenuation circuit (i.e. closer to the internal-node <NUM> than the respective first- and second-attenuation-resistors (R1, R2) <NUM>, <NUM>) as shown in <FIG> can achieve lower gain-to-phase errors than putting first- and second-attenuation-resistors (R1, R2) <NUM>, <NUM> in the center. This has been proven by simulation, as will be discussed below. The reason is that when switching the first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> between the ON and OFF state, the substrate capacitance change compensates the junction capacitance change.

<FIG> show small-signal models of the <NUM>-bit DSA in <FIG>. <FIG> refers to the attenuation circuit in the bypass mode of operation. <FIG> refers to the attenuation circuit in the attenuation mode of operation. We will use these models to calculate the required value of the tuning-inductor (L1) and attenuation ratio expressions. Each of the components in <FIG> have been given labels that are either used in <FIG> or referred to in the above description of <FIG>. Since C1, C2 and C3 are large DC decoupling capacitors, they are treated as short RF connections. Since the Rbias resistors are large DC bias resistors, they are treated as open RF connections. Rs is the source resistance, RI is the load resistance, and the voltage at the RF input terminal is modelled as a supply voltage Vs.

To simplify the mathematical calculations, we assume Rs=RI=Z0, R1=R2=R0, D2_Coff=D1_Coff=Coff, D2_Ron=D1_Ron=Ron.

Output voltage of bypass mode in Figure <NUM>(a) is: <MAT>.

In which w=<NUM>*pi*fc, fc is the center of operational frequency.

Output voltage of by-pass mode in Figure <NUM>(b) is: <MAT>.

In order to get the same phase between Vout_a and Vout_b, we have: <MAT>.

Hence, after simplifying the equations <NUM>-<NUM>, we have: <MAT>.

It means that given a certain diode size (Ron, Coff), attenuation resistance (R1, R2) and frequency, there is one corresponding shunt inductance L1 for zero gain-to-phase error (i.e. for which the phase is the same for bypass mode and attenuation mode).

Since Vout_a and Vout_b have the same phase, we can also get the attenuation ratio as: <MAT>.

Intuitively speaking, the attenuation ratio is monotonically increasing with R0 increasing. When R0=<NUM>, we get maximum attenuation ratio of <NUM>+Z0/Ron. When R0=+∞, we get minimum attenuation ratio of <NUM> (0dB).

<FIG> shows an attenuation circuit that is similar to that of <FIG>, but without the tuning-inductor. <FIG> shows an attenuation circuit that is similar to that of <FIG>, but with: the positions of the first-attenuation-resistor (R1) <NUM> and the first-attenuation-diode (D1) <NUM> reversed; and the positions of the second-attenuation-resistor (R2) <NUM> and the second-attenuation-diode (D2) <NUM> reversed. The circuits of <FIG> have the same values for all components.

<FIG> shows the simulated attenuation ratio (dB) versus frequency for: the attenuation circuit of <FIG> as a solid line, and the attenuation circuit of <FIG> as a (horizontal) dashed line. <FIG> shows that both attenuation circuits achieve an attenuation ratio of 8dB at the centre frequency.

<FIG> shows the simulated gain-to-phase (G2P) error in degrees versus frequency for: the attenuation circuit of <FIG> as a solid line, and the attenuation circuit of <FIG> as a dashed line. <FIG> shows that the G2P error of the attenuation circuit of <FIG> at the centre frequency (having a value of <NUM> degrees) than is better than the G2P error of the attenuation circuit of <FIG> at the centre frequency (having a value of <NUM> degrees).

Therefore, <FIG> shows that the arrangement of diodes and attenuation resistors in <FIG> achieves a better gain-to-phase error than the arrangement in <FIG>.

<FIG> shows an attenuation circuit that is similar to that of <FIG>, but without the tuning-inductor. <FIG> shows the same attenuation circuit as that of <FIG> (i.e. with the tuning-inductor <NUM>). The circuits of <FIG> have the same values for all components.

<FIG> shows the simulated gain-to-phase (G2P) error in degrees versus frequency for: the attenuation circuit of <FIG> as a solid line, and the attenuation circuit of <FIG> as a dashed line. <FIG> shows that the G2P error of the attenuation circuit of <FIG> at the centre frequency (having a value of <NUM> degrees) than is better than the G2P error of the attenuation circuit of <FIG> at the centre frequency (having a value of <NUM> degrees). That is, inclusion of the tuning-inductor (L1) <NUM> of <FIG> completely compensates the G2P error at the center frequency. Nonetheless, as indicated above in some cases it can still be possible to meet a system specification for G2P error without the tuning-inductor.

<FIG> shows an example embodiment of an amplifier circuit <NUM> that includes a <NUM>-bit digital signal attenuation circuit <NUM>. Components of the attenuation circuit <NUM> that have already been described with reference to an earlier drawing will not necessarily be described again here.

In this example, the attenuation circuit <NUM> includes an amplifier-inductor (L2) <NUM> connected in series between the connection-node <NUM> and a supply-node <NUM>. The amplifier-inductor <NUM> reduces the gain-to-phase error of the attenuation circuit <NUM> by compensating for the off-capacitance of the first- and second-attenuation-diodes (D1, D2). Therefore the amplifier-inductor <NUM> can be considered as an example of the tuning-inductor that is described above with reference to <FIG>, and the supply-node can be considered as an example of the AC-reference-node. In addition, as will be described below, the amplifier-inductor (L2) provides some of the functionality of an amplifier <NUM> that provides an output signal to the connection-node <NUM>.

<FIG> shows how the <NUM>-bit DSA circuit <NUM> is integrated between two amplifiers - a first amplifier <NUM> and a second amplifier <NUM>.

The first amplifier <NUM> that has a first-amplifier-output-terminal <NUM>, which is connected to the connection-node <NUM> of the attenuator circuit <NUM>. The components of the first amplifier <NUM> that are outside (to the left of) the attenuation circuit <NUM> in <FIG> can be considered as a unit cell of an amplifier. In <FIG> the unit cell is illustrated as a cascode stage, although it will be appreciated that in other examples the unit cell can be provided as a common-emitter, common-base, common-source, common-gate or any other amplifier unit cell configuration.

An RF amplifier (such as the first amplifier <NUM>) usually has a parallel inductor between the first-amplifier-output-terminal <NUM> and a supply-node <NUM> (which can also be consider as an AC ground node). Advantageously, in <FIG> the functionality of the tuning-inductor of the attenuation circuit <NUM> and the functionality of the parallel inductor of the RF amplifier is combined and provided by a single component: the amplifier-inductor (L2) <NUM>. As shown in <FIG>, the amplifier-inductor (L2) <NUM> can provide both functionalities at the same time. Therefore, amplifier circuit <NUM> of <FIG> has less components than would be the case if the inductors were implemented separately, and advantageously a more compact layout size can be achieved with lower insertion loss.

The second amplifier <NUM> has a second-amplifier-input-terminal <NUM>. The second-amplifier-input-terminal <NUM> is connected to the connection-node <NUM>, and therefore is also connected to the first-amplifier-output-terminal <NUM>.

In this example, an ISMN (inter-stage-matching-network) <NUM> is connected in series between the connection-node <NUM> and the second-amplifier-input-terminal <NUM>. The ISMN <NUM> is used to transform the input impedance of the sconed amplifier <NUM> to the optimal load impedance of the first amplifier <NUM>. In general, the input impedance of the second amplifier <NUM> is likely to be lower than the load impedance of the first amplifier <NUM>. From equation <NUM> above, we see that an increasing Z0 will increase the attenuation ratio. Thus, positioning the connection-node <NUM> between the first-amplifier-output-terminal <NUM> and the ISMN <NUM> can provide better performance than positioning the connection-node <NUM> between the ISMN <NUM> and the second amplifier <NUM>.

As will be discussed below, an amplifier circuit according to the present disclosure can include a plurality of amplifiers connected in series, with any of the attenuator circuits disclosed herein connected to an RF connection between amplifiers.

<FIG> shows an example embodiment of a multiple-bit attenuation circuit (DSA) line-up configuration. Just as an example, Bits <NUM>,<NUM>,<NUM> of the DSA are set for attenuation control of <NUM>,<NUM>,<NUM> dB, respectively. Therefore, in total an attenuation range of <NUM>-<NUM> dB can be achieved. It will be appreciated that the functionality of <FIG> can be used with any number of bits.

As shown in <FIG>, an amplifier <NUM>, <NUM> is positioned between each DSA stage 802a, 802b, 802c in order to improve an attenuation step error (to decrease glitches between attenuation state transitions). A potential issue of cascading DSA stages / cores 802a, 802b 802c without any amplifiers is that a <NUM>-bit DSA will provide a different interface impedance between the bypass mode and the attenuation mode of operation, and consequently can impact the operation of other "neighborhood" DSA stages. Adding an amplifier <NUM>, <NUM> between each DSA stage / core 802a, 802b 802c can beneficially isolate this impedance change and ensure each DSA stage /core 802a, 802b 802c is working independently. This approach can significantly improve the attenuation step error.

In this way, an amplifier circuit can be provided that includes a first amplifier <NUM> and one or more additional amplifiers <NUM>, <NUM>, <NUM> connected in series with the first amplifier <NUM>. Each additional amplifier <NUM>, <NUM>, <NUM> comprises an additional-amplifier-input-terminal and an additional-amplifier-output-terminal. The amplifier circuit further including an attenuation circuit 802a, 802b, 802c connected to the additional-amplifier-output terminal of each of the additional amplifiers <NUM>, <NUM> except the last additional amplifier <NUM> in the series. Further still, the amplifier circuit can include an amplifier-inductor 842a, 842b, 842c associated with each of the attenuation circuits 802a, 802b, 802c. Each amplifier-inductor 842a, 842b, 842c is connected in series between the connection-node of the associated attenuation circuit 802a, 802b, 802c and the supply-node. As discussed above, each amplifier-inductor 842a, 842b, 842c is configured to: provide some of the functionality of the preceding additional amplifier <NUM>, <NUM>, <NUM> in the series; and compensate for the off-capacitance of the first- and second-attenuation-diodes (D1, D2). Yet further, as shown in <FIG>, the amplifier circuit can include an inter-stage matching network (ISMN) connected in series between the connection node of each attenuation circuit and the additional-amplifier-input-terminal of the next additional amplifier in the series.

<FIG> show simulation results of the amplifier circuit of <FIG>, and more particularly to show that a gain step error (glitch) will be improved by adding amplifiers to isolate each DSA core.

<FIG> shows a schematic of the test bench that was used for the simulation. In order to simplify the simulation, a voltage-control-voltage-source (vcvs) with <NUM>-Ohm resistor was used to represent ideal amplifiers. The attenuator line-up includes <NUM> DSA cores with <NUM>,<NUM>,<NUM>,<NUM> dB attenuation ratios, respectively. Thus, the line-up has <NUM>-dB attenuation range with each attenuation step of 1dB.

<FIG> shows the simulation results. The darker lines (with crosses) relate to the performance of <FIG>. The lighter lines (with squares) relate to the case that all the ideal amplifiers are removed in <FIG>. The first plot relates to S21 (the gain from the input to the output). The second plot relates to attenuation DNL (differential non-linearity). The third plot relates to attenuation INL (integral non-linearity). Attenuation DNL is defined by the delta gain between each attenuation state and ideally is equal to <NUM> dB. Attenuation INL is defined by the gain error between the target (each step with ideal attenuation of 1dB) and is ideally equal to <NUM> dB.

It can be seen from <FIG> that the darker lines (with the crosses) are close to an ideal attenuator case, while the lighter lines (with the squares) have quite some glitches between each attenuation state transition. To be more specific, if we look at the INL of the lighter lines, only with attenuator code <NUM>,<NUM>,<NUM>,<NUM> INL is close to <NUM> dB because with these states only one DSA core is turned on (i.e. the other DSA cores are turned off). With the other attenuator codes, at least two DSA cores are turned on at the same time and the DSA cores interface impedance change will impact the operation of the others. This is the root cause of the glitches in the lighter lines.

<FIG> shows an embodiment of an attenuation circuit that includes an example circuit design of a control signal generator for providing the first- and the second-control-signals that are described above for setting the mode of operation of the attenuation circuit. The control signal generator can also be referred to as one or more bias circuits for DC control of V1 and V2 (as they are shown in <FIG> and <FIG>).

<FIG> shows a straightforward way of using a voltage-controlled bias circuit for <NUM>-bit DSA. A DC control input is provided at a control-node <NUM> and invertors are provided to create <NUM> V and Vcc bias voltages.

In the bypass mode, the control-node <NUM> is at the supply voltage (Vcc). Invertors provide Vcc at the second-control-node (V2) <NUM>, and <NUM> V at the first-control-node (V1) <NUM>, respectively. Thus, PiN diodes D1 and D2 are reverse-biased and turned off.

In the attenuation mode, the control-node <NUM> is at <NUM> V. Invertors provide <NUM> V at the second-control-node (V2) <NUM>, and Vcc at the first-control-node (V1) <NUM>, respectively. Thus, PiN diodes D1 and D2 are forward-biased and turned on.

However, with the voltage-controlled bias circuit of <FIG>, the bias current of D1 and D2 are dependent on the attenuation resistors R1 and R2. Current consumption of a DSA core therefore cannot be accurately controlled.

<FIG> illustrates a current-controlled bias circuit for providing the first- and the second-control-signals. More particularly, it shows a schematic of a <NUM>-bit DSA with a bottom current-controlled bias circuit. The motivation of this bias circuit is to accurately control the DC bias current of PiN diodes in ON stage (attenuation mode).

In the bypass mode, a control-node <NUM> input is Vcc. N1 has the gate voltage of Vcc, N1 is turned on and pull down the gate voltage of N3 to <NUM> V, and N3 is turned off (as "open"). Invertor provides <NUM> V bias at the first-control-node (V1) <NUM>. Since the gate voltage of P1 is <NUM> V, P1 is turned on and the second-control-node (V2) <NUM> is biased to Vcc. Hence, PiN diodes D1 and D2 are reverse biased and turned off.

In the attenuation mode, the control-node <NUM> input is <NUM> V. Since N1 has gate voltage of <NUM> V, N1 is turned off and does not impact other transistors operation. N2 and N3 work as a normal current mirror at the bottom of the second-control-node (V2) <NUM>. Invertor provides Vcc bias at the first-control-node (V1) <NUM>. Since the gate voltage of P1 is Vcc, P1 is turned off (as "open"). Hence, PiN diodes D1 and D2 are forward-biased. The bias current of PiN diode is the same as the drain current of N3 and accurately controlled by the current mirror N2, N3 and Iref.

<FIG> shows an example schematic of a <NUM>-bit DSA with a top current-controlled bias circuit. <FIG> is similar to <FIG>, the main difference is that <FIG> uses an NMOS current mirror at the bottom of attenuator core to provide bias current, while <FIG> uses a PMOS current mirror at the top of attenuator core to provide bias current.

In the bypass mode, the control-node <NUM> input is <NUM> V. Since P1 has the gate voltage of <NUM> V, P1 is turned on and pull up the gate voltage of P3 to Vcc, and P3 is turned off (as "open"). Invertor provides Vcc bias at the second-control-node (V2) <NUM>. Since the gate voltage of N1 is Vcc, N1 is turned on and it pulls down the bias voltage at the first-control-node (V1) <NUM> to <NUM> V. Hence, PiN diodes D1 and D2 are reverse biased and turned off.

In the attenuation mode, the control-node <NUM> input is Vcc. Since P1 has the gate voltage of Vcc, P1 is turned off and does not impact other transistors operation. P2 and P3 work as a normal current mirror at the top of the first-control-node (V1) <NUM>. Invertor provides <NUM> V bias at the second-control-node (V2) <NUM>. Since the gate voltage of N1 is <NUM> V, N1 is turned off (as "open"). Hence, PiN diodes D1 and D2 are forward-biased. The bias current of PiN diode is the same as the drain current of P3 and accurately controlled by the current mirror P2, P3 and Iref.

<FIG> shows another example embodiment of an attenuation circuit. Components that are also shown in <FIG> are given corresponding reference numbers in the <NUM> series and will not necessarily be described again here. The circuit of <FIG> is a <NUM>-bit DSA core with an extra diode branch (which may include PiN diodes in some examples) for wide-band G2P compensation.

In addition to the components of <FIG>, the attenuation circuit of <FIG> includes:.

The first-terminal of the first-resistor (R1) <NUM> is connected to the first-control-node (V1) <NUM>. The second-terminal of the first-resistor (R1) <NUM> is connected to the anode-terminal of the first-attenuation-diode (D1) <NUM>. The cathode-terminal of the first-attenuation-diode (D1) <NUM> is connected to the internal-node <NUM>. The anode-terminal of the second-attenuation-diode (D2) <NUM> is connected to the internal-node <NUM>. The cathode-terminal of the second-attenuation-diode (D2) <NUM> is connected to the first-terminal of the second-attenuation-resistor (R2) <NUM>. The second-terminal of the second-attenuation-resistor (R2) <NUM> is connected to the second-control-node (V2) <NUM>. The anode-terminal of the first-compensation-diode (DCOMP1) <NUM> is connected to the second-terminal of the first-resistor (R1) <NUM>. The cathode-terminal of the first-compensation-diode (DCOMP1) <NUM> is connected to the anode-terminal of the second-compensation-diode (DCOMP2) <NUM>. The cathode-terminal of the second-compensation-diode (DCOMP2) <NUM> is connected to the first terminal of the second resistor (R2) <NUM>.

As discussed above, the root cause of G2P error is the load reactance change in the DSA core. The first- and second-attenuation-diodes (D1, D2) <NUM>, <NUM> show a capacitive loading (Coff) at the RF path in off-state (bypass mode), while they show a resistive loading (Ron) at the RF path in on-state (attenuation mode). In <FIG>, instead of using a parallel tuning-inductor to tune out the Coff (although in some examples a tuning-inductor L1 can be used too), an extra branch of diodes (the first- and second-compensation-diodes (DCOMP1, DCOMP2)) is used to introduce shunt capacitance in the attenuation mode. Thus, D1 and D2 show capacitive loading both in bypass and attenuation mode. By properly optimizing the values for DCOMP1 and DCOMP2, a reduced G2P error can be achieved at the center frequency. Since an LC resonant circuit usually has a narrower frequency bandwidth than an RC network, the circuit of <FIG> advantageously has a wider frequency bandwidth than that of <FIG> (which includes a tuning-inductor L1).

The circuit of <FIG> also includes one or both of the following optional components: a first-compensation-capacitor (CCOMP1) <NUM>; and a second-compensation-capacitor (CCOMP2) <NUM>. The values for the first- and second-compensation-capacitors (CCOMP1, CCOMP2) <NUM>, <NUM> can also be optimized to reduce the G2P error at the center frequency, potentially to bring the G2P error down to zero.

The first-compensation-capacitor (CCOMP1) <NUM> is connected in series between: i) the internal-node <NUM>; and ii) the connection between the cathode-terminal of the first-compensation-diode (DCOMP1) <NUM> and the anode-terminal of the second-compensation-diode (DCOMP2) <NUM>. The second-compensation-capacitor (CCOMP2) <NUM> is connected in series between: i) the connection between the cathode-terminal of the first-compensation-diode (DCOMP1) <NUM> and the anode-terminal of the second-compensation-diode (DCOMP2) <NUM>; and ii) the reference-node <NUM>.

The compensation capacitance CCOMP1 and CCOMP2 values are highly dependent on the substrate capacitance of DCOMP1 and DCOMP2. As indicated above, CCOMP1 and CCOMP2 could even be removed in some cases. Furthermore, in a practical layout, the DC decoupling capacitors C1, C2, C3 are chip area dominant. CCOMP1 and CCOMP2 values are typically less than <NUM>% of C1. Thus, the inclusion of CCOMP1 and CCOMP2 does not significantly increase chip area.

<FIG> shows simulation results to compare different DSA core circuits. The lightest lines <NUM> shows the performance of a DSA core without a parallel tuning-inductor, such as the circuit of <FIG>. The dark dashed lines <NUM> shows the performance of a DSA core with a parallel tuning-inductor, such as the circuit of <FIG>. The dark solid lines <NUM> show the performance of a DSA core with an extra PiN diode branch, such as the circuit shown in <FIG>.

The left-hand plot in <FIG> shows that all three DSA cores have wideband <NUM>-dB attenuation ratio over the frequency. The right-hand plot in <FIG>) shows that both the parallel L and the extra PiN diode branch correct G2P error at the center frequency very well. Moreover, with the extra PiN diode branch, the DSA core has less G2P error over the frequency variation (as shown by the solid dark line <NUM>). In other words, the DSA core of <FIG> has a wider operational frequency bandwidth.

One or more of the examples disclosed herein relate to a novel Digital-Step-Attenuator (DSA) circuit based on a PiN diode device. The DSA core is connected as shunt to a RF signal path. The DSA is switched between bypass or attenuation mode by reverse-biasing or forward-biasing the PiN diodes, respectively. Such a circuit has the feature of low insertion loss, low gain-to-phase error and compact layout size. Based on such DSA cores, there is also provided a distributed multiple-bit DSA line-up which can be integrated between amplifiers. By adding amplifiers between each DSA stage, the DSA impedance variation between by-pass and attenuation mode can be isolated. The proposed line-up has a low gain step error (with few glitches between attenuation state transitions).

The following example circuit topologies are disclosed in order to improve the Digital-Step-Attenuator (DSA).

An example <NUM>-bit DSA core of the present disclosure can provide the following features:.

The following additional features can also be provided::.

Example applications of the attenuations circuits disclosed herein include RF and millimeter-wave front-end IC and beamformer products for <NUM> and future <NUM> communication networks.

It will be appreciated that any components that are described or illustrated herein as being coupled or connected could be directly or indirectly coupled or galvanically connected. That is, one or more components could be located between two components that are said to be coupled or connected whilst still enabling the required functionality to be achieved.

Claim 1:
An attenuation circuit comprising:
a connection-node (<NUM>, <NUM>) configured to connect to an RF connection (<NUM>, <NUM>) such that the attenuation circuit is arranged as a shunt connection with an RF signal path;
a first-control-node (<NUM>, <NUM>) configured to receive a first-control-signal;
a second-control-node (<NUM>, <NUM>) configured to receive a second-control-signal;
an internal-node (<NUM>, <NUM>);
a reference-node (<NUM>, <NUM>) for connecting to a reference terminal;
an isolation-capacitor (<NUM>) connected in series between the connection-node and the internal-node;
a first-bias-resistor (<NUM>) connected in series between the first-control-node (<NUM>, <NUM>) and the internal-node (<NUM>, <NUM>);
a second-bias-resistor (<NUM>) connected in series between the internal-node (<NUM>, <NUM>) and the second-control-node (<NUM>, <NUM>);
a first-attenuation-diode (<NUM>, <NUM>) connected in series between the first-control-node (<NUM>, <NUM>) and the internal-node (<NUM>, <NUM>), wherein the anode of the first-attenuation-diode (<NUM>, <NUM>) is closest to the first-control-node (<NUM>, <NUM>);
a second-attenuation-diode (<NUM>, <NUM>) connected in series between the internal-node (<NUM>, <NUM>) and the second-control-node (<NUM>, <NUM>), wherein the anode of the second-attenuation-diode (<NUM>, <NUM>) is closest to the internal-node (<NUM>, <NUM>);
a first-decoupling-capacitor (<NUM>, <NUM>) connected in series between the first-control-node (<NUM>, <NUM>) and the reference-node (<NUM>, <NUM>);
a second-decoupling-capacitor (<NUM>, <NUM>) connected in series between the second-control-node (<NUM>, <NUM>) and the reference-node (<NUM>, <NUM>); and
a first-attenuation-resistor (<NUM>) and a second-attenuation-resistor (<NUM>), wherein:
the first-attenuation-resistor (<NUM>) and the first-attenuation-diode (<NUM>) are connected in series with each other between the first-control-node (<NUM>)and the internal-node (<NUM>); and
the second-attenuation-resistor (<NUM>) and the second-attenuation-diode (<NUM>) are connected in series with each other between the internal-node (<NUM>) and the second-control-node (<NUM>).