Patent Description:
Aspects of the disclosure relate generally to electronic circuits, and more specifically, but not exclusively, to a three-dimensional (3D) integrated circuit (IC).

Conventional 3D integrated circuit (3D-IC) architectures include a so-called <NUM>. 5D architecture and a fully stacked 3D architecture. In a <NUM>. 5D architecture, dies are placed side-by-side and interconnected via a horizontal interposer layer. A fully stacked 3D architecture employs dies that are stacked on top of one another. Both architectures use through-silicon vias (TSVs) to connect the metal layers.

Existing 3D-IC routing design faces several critical challenges relating to power distribution network (PDN) design, thermal management, and testing methodology. A typical 3D-IC PDN is implemented as a pyramid shape where power rails are used to supply the power from the bottom of the IC to the top of the IC. This PDN occupies significant die area and leads to routing congestion. Regarding thermal management, when multiple dies are stacked together, it is difficult to dissipate the heat, especially for bottom dies. This can lead to a dramatic degradation in overall system performance at high temperatures. Regarding testing, it is difficult (if not impossible in some cases) to fully test dies before packaging. In particular, cross die functionality might not be fully testable before the dies are assembled. Accordingly, there is a need for better testing methodologies for 3D-ICs. <CIT> describes a 3D IC structure and method. <CIT> describes a stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks. <CIT> describes energy efficient power distribution for 3D integrated circuit stack. <CIT> describes a structure to share internally generated voltages between chips in MCP.

The following presents a simplified summary of some aspects of the disclosure to provide a basic understanding of such aspects. Its sole purpose is to present various concepts of some aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

Various aspects of the present disclosure provide for a 3D-IC architecture that incorporates dies on different geometric planes and at least one switch on each geometric plane to connect the dies. In this architecture, a PDN can be routed from a first die on one geometric plane through the switches to supply power to at least one other die on at least one other geometric plane. This can significantly reduce the PDN area in the first die (and, potentially, adjacent dies) and mitigate routing congestion problems. Moreover, the switches can be placed around the periphery of the IC package to improve heat dissipation. By placing the switches on the periphery, heat can be transferred more quickly from the center to the edge of the IC package through a redistribution layer (RDL) and TSVs. Also, the switches are used for routing test signals and/or other signals between dies, thereby improving test functionality and/or fault recovery.

Various aspects of the present disclosure provide for a 3D-IC architecture that incorporates multiple layers, where each layer includes multiple dies, and at least one interposer for wire routing in one dimension (e.g., a horizontal dimension) to connect the dies of a given layer. The 3D-IC architecture further includes at least one switch on each layer for wire routing in another dimension (e.g., a vertical dimension) to connect the dies of different layers. In this architecture, a PDN and/or other wiring can be routed from a first die of one layer through the switches and the interposer(s) to supply power and/or other signals to at least one other die of at least one other layer.

In accordance with the teachings herein, 3D-ICs with TSVs may be used to address advanced semiconductor device scaling problems. Through the use of 3D-ICs, multiple dies with the same and/or different technologies can be integrated into a single IC package. This approach can improve overall system performance and reduce total power consumption, while also offering a cost advantage through the use of a low cost mainstream process, without advanced technology migration.

In one aspect of the invention, an integrated circuit according to claim <NUM> is provided.

Additional aspects of the invention are claimed in dependent claims <NUM>-<NUM>.

In another aspect of the invention, an integrated circuit according to claim <NUM> is provided.

Additional aspects of the invention are claimed in claims <NUM> and <NUM>.

Another aspect of the disclosure, which does not form part of the claimed invention, is a method for switching a signal including receiving a signal via a first signal path at a first switch circuit on a first die lying within a first geometric plane; controlling the first switch circuit via a first circuit on the first die to route the signal to a second switch circuit on a second die lying within a second geometric plane that is different from the first geometric plane; and controlling the second switch circuit via a second circuit on the second die to route the signal to a second signal path.

Examples of additional aspects of the disclosure for the method, which do not form part of the claimed invention, follow. In some aspects, the second die is stacked on top of the first die. In some aspects, the signal includes a test signal. In some aspects, the signal includes a power supply voltage signal. In some aspects, the method further includes: identifying a fault condition on the first die; and triggering the routing of the signal to the second signal path as a result of the identification of the fault condition. In some aspects, the method further includes: controlling the first switch circuit via the first circuit to route the signal to a memory device on the first die as a result of the identification of the fault condition. In some aspects, the method further includes: disabling the first die as a result of the identification of the fault condition. In some aspects, the method further includes: controlling the second switch circuit via the second circuit to route the signal to a third switch circuit on a third die lying within a third geometric plane that is different from the first and second geometric planes; and controlling the third switch circuit via a third circuit on the third die to route the signal to a third signal path. In some aspects, the first and second circuits include logic circuits. In some aspects, the first and second switch circuits include analog switch circuitry.

Yet another aspect of the disclosure, which does not form part of the claimed invention, provides an apparatus configured for switching a signal. The apparatus including a first die lying within a first geometric plane; a first signal path on the first die; a first switch circuit on the first die coupled to the first signal path; a second die lying within a first geometric plane; a second signal path on the second die; a second switch circuit on the second die coupled to the second signal path; first means for controlling the first switch circuit to couple a signal from the first signal path to the second switch circuit; and second means for controlling the second switch circuit to couple the signal to a second signal path.

These and other aspects of the disclosure will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and implementations of the disclosure will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific implementations of the disclosure in conjunction with the accompanying figures. While features of the disclosure may be discussed relative to certain implementations and figures below, all implementations of the disclosure can include one or more of the advantageous features discussed herein. In other words, while one or more implementations may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various implementations of the disclosure discussed herein. In similar fashion, while certain implementations may be discussed below as device, system, or method implementations it should be understood that such implementations can be implemented in various devices, systems, and methods.

Only <FIG> and <FIG> show embodiments of the claimed invention. The other figures shows aspects of the disclosure, which do not form part of the claimed invention, but are useful for understanding the claimed invention.

<FIG> is a simplified example of a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first die <NUM> lying within a first geometric plane and a second die <NUM> lying within a second geometric plane. In this example, the first and second dies <NUM> and <NUM> are parallel to one another and in a stacked arrangement. Specifically, the second die <NUM> is stacked on top of the first die <NUM>. Other die configurations may be employed in other implementations. For example, a 3D-IC implemented in accordance with the teachings herein may include more than two dies. In addition, in some implementations the dies are not stacked on top of the other. Also, in some implementations, the dies are not parallel (i.e., the dies lie in geometric planes that are not parallel with respect to one another).

Each of the dies includes electrically coupled switch circuits and other circuits (e.g., logic circuits, digital circuits, analog circuits, and so on). The first die <NUM> includes switch circuits <NUM> and circuits <NUM>, where at least one of the switch circuits <NUM> is electrically coupled to at least one of the circuits <NUM> via at least one electrical path <NUM> (e.g., a signal bus). Similarly, the second die <NUM> includes switch circuits <NUM> and circuits <NUM>, where at least one of the switch circuits <NUM> is electrically coupled to at least one of the circuits <NUM> via at least one electrical path <NUM> (e.g., a signal bus). Also, interconnections (e.g., an electrical path <NUM>) are provided between the switch circuits <NUM> and <NUM>.

In some implementations, each switch circuit supports one or more of: programmable signal routing, distribution of a voltage supply, distribution of multiple voltage supplies, or voltage level shifting. For convenience, such a switch circuit may be referred to herein as a peripheral switch (e.g., indicating that the switch may be separate from other circuit components of an IC).

A voltage control circuit (e.g., including a voltage regulator) can be integrated into a switch circuit to provide one or more voltages for an individual die. Thus, in some aspects, switch circuits on different dies may each be coupled to a power distribution path on the respective die. Moreover, in some aspects, switch circuits on different dies may each include a supply voltage control circuit. In implementations that employ multiple supply voltage levels, each of the supply voltage control circuits may generate a plurality of supply voltage levels. A level shifter can be included in a switch circuit to shift signal levels between different power supply domains. Thus, in some aspects, switch circuits on different dies may each be coupled to a power distribution path on the respective die.

In accordance with the claimed invention, for IC testing, a switch circuit can reroute test signals from one die to another. Thus, in accordance with the claimed invention, switch circuits on different dies may each be coupled to a test signal path on the respective die. By dynamically configuring the routing of test signals in this manner, design feasibility can be improved. Moreover, this dynamic switching functionality can be used to bypass a failed die by rerouting signals. The switch is thus valuable during the IC (chip) "bring-up" stage since it can be used to isolate the verification target and isolate the root cause of a failure.

Switch circuits as discussed herein may provide digital and/or analog connectivity. Digital switch circuitry may connect, for example and without limitation, one or more of: digital logic circuits, digital memory circuits, or digital power distribution circuits. Analog switch circuitry may connect, for example and without limitation, one or more of: analog logic circuits, analog power distribution circuits, analog radio frequency (RF) circuits (e.g., RF transmitter and/or RF receiver circuits), analog phase locked loop (PLL) circuits, or analog circuitry of digital-to-analog converter (DAC) circuits and/or analog-to-digital converter (DAC) circuits.

In view of the above, multiple dies with different functionality can be integrated into a single IC package. Advantageously, this can be achieved while mitigating conventional routing congestion and heat dissipation problems seen in conventional 3D architectures. As mentioned above, a conventional 3D-IC is implemented using either a <NUM>. 5D interposer architecture or fully stacked 3D architecture.

In a <NUM>. 5D interposer architecture, multiple dies are placed on top of an interposer and connected together through TSVs and a flip chip configuration. This approach reuses current system-on-chip (SoC) design methodology to shorten the design cycle as well as reduce the design cost. The interposer is manufactured with mature main stream technology to further offset the cost.

The concept of <NUM>. 5D ICs is based on a system-in-package (SiP) approach where different dices are placed on a common substrate. The interconnect between each die is built on the common substrate. Compared with SoC devices, SiP devices have the advantages of lower cost and higher flexibility because each die is implemented using that domain's most appropriate technology process.

<FIG> is a side sectional view of a simplified example of a conventional <NUM>. 5D IC <NUM>. 5D IC <NUM> includes a first die <NUM> and a second die <NUM>.

As indicted, a silicon interposer <NUM> is placed between a SiP substrate <NUM> and the dice <NUM> and <NUM>. The silicon interposer <NUM> includes topside metal layers <NUM>, an interposer substrate <NUM>, and backside metal layers <NUM>. The silicon interposer <NUM> also includes through-silicon vias (TSVs) <NUM> connecting the metallization layers <NUM> and <NUM> on the upper and lower surfaces. Micro-bumps <NUM> attach the dice <NUM> and <NUM> and the interposer <NUM>. The interposer <NUM> is attached to the SiP substrate <NUM> via flip-chip bumps <NUM>. Package bumps <NUM> attach the SiP substrate <NUM> to a circuit board <NUM>.

The tracks on the topside and backside metal layers of the interposer <NUM> are created using the same process as the track on the silicon chip, which resolves a major problem of two-dimensional (2D) ICs due to the size difference of tracks on substrate and those on dice. This discrepancy in 2D architectures results in performance loss and increased power consumption.

In a fully stacked 3D architecture, multiple dies are stacked together and connected through on-die TSVs. This can improve the overall system performance as well as reduce the cost. For example, fully stacked 3D-ICs are seen as a desirable alternative to overcome interconnect scaling issues that can be a major bottleneck on 2D ICs. Fully stacked 3D-ICs, with the advantage of a smaller footprint area, reduce the wire length on each layer. Also, TSV technology is implemented for vertical interconnect between dies, which reduces the long cross-chip interconnects that may exist in 2D ICs.

<FIG> is a side sectional view of a simplified example of a conventional fully stacked 3D-IC <NUM>. The 3D-IC <NUM> includes a first die <NUM> and a second die <NUM>.

The first die <NUM> includes backside metal layers <NUM>, a chip substrate <NUM>, a device layer <NUM>, and standard metal layers <NUM>. The second die <NUM> includes a chip substrate <NUM>, a device layer <NUM>, and standard metal layers <NUM>. The first die <NUM> includes TSVs <NUM> for connecting the metallization layers <NUM> and <NUM> on the upper and lower surfaces. Micro-bumps <NUM> attach the dice <NUM> and <NUM>. The first die <NUM> is attached to a SiP substrate <NUM> via flip-chip bumps <NUM>. Package bumps <NUM> attach the SiP substrate <NUM> to a circuit board <NUM>.

Instead of using an interposer for routing and power distribution as in <NUM>. 5D ICs, the 3D-IC stacks dices directly and implements the routing in the intermediate dices. Since the thickness of an individual die is very small, ideally one could mount as many dices as needed. In practice, however, there are several challenges involved in manufacturing 3D-ICs, which restricts the application of 3D-ICs.

One challenge relates to the PDN design. The typical 3D-IC PDN is implemented as a pyramid shape where additional power rails supply power from the bottom die to the top die.

<FIG> is a side sectional view of such a power distribution network in a conventional 3D-IC <NUM>. The 3D-IC <NUM> includes a first die <NUM>, a second die <NUM>, and a third die <NUM>. Each of the dice includes TSVs <NUM> for connecting, for example, respective metallization layers on upper and lower surfaces.

Here, it may be seen that the PDN TSVs <NUM> occupy significant die area and can create a routing congestion problem, particularly, on the lower dies. Moreover, in modern IC design, the current*resistance (IR) drop may be significant even if TSVs are used because the margin working voltage is smaller.

Besides the IR drop and space usage, PDNs have conventionally supplied only a restricted voltage scale because the PDNs use a single power supply from the circuit board. Therefore, the voltage only scales down as the supply passes from one layer to the next (e.g., due to IR drop). Moreover, a higher voltage in the lower layer leads to more severe thermal issues in that layer.

Another challenge in 3D-IC design relates to thermal management. When multiple dies are stacked together, it is difficult to dissipate the heat, especially for bottom dies. The overall system performance is dramatically degraded at high temperature. The use of micro-channels and liquid cooling has been proposed for 3D-IC designs; however, this technology has major drawbacks due to additional hardware requirements and operation difficulty. The use of additional TSVs can improve the heat dissipation, however, this may negatively impact the usable area on the die and the amount of stress the die can withstand.

Finally, testing methodology presents a challenge for 3D-IC design. It may be impractical or impossible to fully test the dies before packaging. Thus, traditional Known Good Die (KGD) procedures may be inapplicable. IEEE <NUM> has been proposed to resolve this issue using an embedded testing approach; however, this approach is still under development.

Referring now to <FIG>, the disclosure relates in some aspects to a 3D-IC hybrid architecture that includes programmable switch routing along with configuration advantages of the <NUM>. 5D and fully stacked 3D architectures. In some aspects, the architecture of <FIG> not only resolves PDN design and thermal management issues, but also provides additional power control and programmable routing capability for 3D-IC design.

In the side sectional view <FIG>, a 3D-IC <NUM> includes a first layer L1, a second layer L2, and a third layer L3 in respective geometric planes (horizontal planes in the perspective of <FIG>). Each of the first, second, and third layers L1, L2, and L3 includes a respective first, second, or third interposer layer <NUM>, <NUM>, or <NUM>, and a respective first, second or third die layer D1, D2, or D3.

The first layer L1 lies within a first geometric plane. The first interposer layer <NUM> includes wire traces for electrically coupling the dice <NUM> - <NUM> of the first die layer D1. At least two of the stacked dice (e.g., a first pair of stacked dice <NUM> and <NUM> and/or a second pair of stacked dice <NUM> and <NUM>) include at least one peripheral switch for wire routing in another dimension (a vertical dimension in the perspective of <FIG>) to connect the first layer L1 to the other layers. At least one of the dice <NUM> - <NUM> (e.g., a third pair of stacked dice <NUM> and <NUM>) includes at least one other circuit (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.).

The second layer L2 lies within a second geometric plane. The second interposer layer <NUM> includes wire traces for electrically coupling the dice <NUM> - <NUM> of the second die layer D2. At least two of the stacked dice (e.g., a first pair of stacked dice <NUM> and <NUM> and/or a second pair of stacked dice <NUM> and <NUM>) include at least one peripheral switch for wire routing in another dimension (a vertical dimension in the perspective of <FIG>) to connect the second layer L2 to the other layers. At least one of the dice <NUM> - <NUM> (e.g., a third pair of stacked dice <NUM> and <NUM>) includes at least one other circuit (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.).

The third layer L3 lies within a third geometric plane. The third interposer layer <NUM> includes wire traces for electrically coupling the dice <NUM> and <NUM> of the third die layer D3. A portion of the stacked dice <NUM> and <NUM> includes at least one peripheral switch for wire routing in another dimension (a vertical dimension in the perspective of <FIG>) to connect the third layer L3 to the other layers. Another portion of the stacked dice <NUM> and <NUM> includes at least one other circuit (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.).

Each of the first, second and third layers L1, L2, and L3 includes TSVs as represented by the thick vertical lines. For example, a TSV <NUM> is specifically referenced in the third interposer layer <NUM> and a TSV <NUM> is specifically referenced in the third die layer D3.

<FIG> also illustrates the bonding and interconnections within and between the first, second and third layers L1, L2, and L3 and other components of the 3D-IC <NUM>. Bumps (e.g., solder balls) <NUM> attach the dice of the first layer L1 to the first interposer layer <NUM>. Bumps <NUM> attach the dice of the second layer L2 to the second interposer layer <NUM>. Bumps <NUM> attach the dice of the third layer L3 to the third interposer layer <NUM>. Bumps <NUM> attach the stacked dice of the first layer L1. Bumps <NUM> attach the stacked dice of the second layer L2. Bumps <NUM> attach the stacked dice of the third layer L3. Bumps <NUM> attach the dice of the first layer L1 to the second interposer layer <NUM>. Bumps <NUM> attach the dice of the second layer L2 to the third interposer layer <NUM>. Bumps <NUM> attach the first interposer layer <NUM> to a SiP substrate <NUM>. Bumps <NUM> attach the SiP substrate <NUM> to a circuit board <NUM>.

The peripheral switches (e.g., crossbar switches, field programmable switches, or other dynamically switchable switches) can be used to reroute signals between layers by dynamically coupling at least one signal path on one layer (e.g., a signal bus, a test signal path, a power distribution path, etc.) to at least one signal path on at least one other layer. Thus, the 3D-IC <NUM> can be reprogrammable for different applications. In accordance with the claimed invention, the switches are dynamically programmable switches and the signal path on the one layer and in the at least one other layer are test signal paths.

In this architecture, a PDN can be routed from the bottom substrate through vertical peripheral switches and horizontal interposers to supply power to upper dies. Thus, this architecture may significantly reduce the PDN area in the bottom active dies and mitigate routing congestion problems. Moreover, for multi-core architectures (e.g., quad core processors, etc.) each fabricated layer (e.g., die) in a 3D-IC can be identical (the peripheral switches may subsequently be programmed to provide the desired routing). Thus, in contrast to the architecture of <FIG>, a 3D-IC constructed in accordance with the teachings herein may be easier to design and manufacture.

Other types of signals (i.e., not just PDN signals) can be routed through peripheral switches in accordance with the teachings herein. For example, critical signals could be routed to different dies through the interposer and peripheral switch.

A voltage control circuit and regulator can be integrated into a peripheral switch to supply different voltages to the individual die. Moreover, a peripheral switch can include an additional level shifter and a storage unit to transfer the signals among different power domains and even store the data before shut down of the individual die.

Advantageously, a peripheral switch can be implemented using a low cost, main stream process with large feature geometry. Consequently, the disclosed architecture is highly suitable for voltage regulator implementations and reduced product cost. Moreover, a peripheral switch can be implemented in different 3D-ICs to improve the overall flexibility.

From a testing perspective, the disclosed architecture not only increases design feasibility, it can facilitate bypassing a failed die and rerouting the signals to preserve the overall integrity of the IC. This functionality is valuable in the chip bring-up stage since it can be used to isolate the verification target and identify the root cause of a failure.

In view of the above, peripheral switching as taught herein supports a multiple voltage supply mechanism as well as programmable routing for heterogeneous integration. In some aspects, peripheral switching as taught herein can provide predefined dynamic power control and a routing switch center. Moreover, several dies with different functionality can integrated into single package without some of the routing congestion and heat dissipation problems seen in conventional architectures.

<FIG> is a plan view of a simplified example of a 3D-IC <NUM> in accordance with some aspects of the disclosure. Logic circuits or other types of circuits are represented by the larger tiles (e.g., the largest tile <NUM> and a medium-sized tile <NUM>). Peripheral switches (S) are represented by the smaller tiles (e.g., the peripheral switch <NUM>). Routing tracks (e.g., a routing track <NUM>) between peripheral switches and/or other circuits are also indicated, as well as input/output (I/O) connections (e.g., an I/O connection <NUM>) between circuits and routing tracks. In some aspects, a peripheral switch may couple any of the routing tracks from one side (e.g., top, bottom, left or right) of the switch to any other routing track or I/O connection on another side of the switch. <FIG> and <FIG> illustrate two examples of the peripheral switch <NUM>.

<FIG> illustrates an example of a routing switch <NUM> (e.g., the peripheral switch <NUM>) that includes a series of <NUM>:<NUM> multiplexers (e.g., a multiplexer <NUM>). Each multiplexer couples one of four inputs <NUM> to a corresponding output <NUM> according to control signals <NUM>. Thus, in operation, a logic circuit on the die or some other circuit generates the control signals <NUM> to dynamically control which tracks (e.g., one or more of the routing tracks of <FIG>) the routing switch <NUM> will couple together at a given point in time. It should be appreciated that a routing switch may take other forms in other implementations.

<FIG> illustrates an example of a power switch <NUM> (e.g., the peripheral switch <NUM>) that includes a series of two input control gates (e.g., a control gate <NUM>). In some implementations, the control gates are AND gates. The control gates couple power from a given input <NUM> to a given output <NUM> according to control signals <NUM>. Thus, in operation, a logic circuit on the die or some other circuit generates the control signals <NUM> to dynamically control which tracks (e.g., one or more of the routing tracks of <FIG>) the power switch <NUM> will couple together at a given point in time. It should be appreciated that a power switch may take other forms in other implementations.

<FIG> is a plan view of a simplified example of peripheral switches in a 3D-IC <NUM> in accordance with some aspects of the disclosure. Logic blocks or other types of circuits are represented by the tiles (e.g., a tile <NUM>). Peripheral switches are represented by programmable routing switches (e.g., a routing switch <NUM>) disposed between the tiles. This figure also shows signal paths (e.g., a routing track <NUM>) that connect to the logic blocks (or other circuits) and the peripheral switches. <FIG> also illustrates I/O connections for the tiles including input connections (e.g., an input connection <NUM>) and output connections (e.g., an output connection <NUM>).

Referring now to <FIG>, in accordance with the claimed invention, each of the peripheral switches (switch circuits) are dynamically switchable. For example, a switch circuit may take the form of a crossbar switch and/or a field programmable switch. In some aspects, a switch circuit may selectively couple signals to another circuit (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.). In accordance with the claimed invention, a switch circuit selectively couples test signals to a switch circuit on another die in another layer.

<FIG> is a schematic representation of an example of dynamically programmable switches in a 3D-IC <NUM> in accordance with some aspects of the claimed invention. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>. The 3D-IC includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM> stacked on top of the first layer <NUM>.

Dynamically programmable switches (DPSs) are distributed throughout each layer in the horizontal direction (from this view). For example, the second layer <NUM> includes DPSs <NUM> and <NUM>, while the first layer <NUM> includes DPSs <NUM> and <NUM>. This facilitates connectivity with other components on the respective layer.

As indicated in <FIG>, dynamically programmable switches (e.g., switches <NUM> and <NUM> and switches <NUM> and <NUM>) are stacked in the vertical direction (from this view). This facilitates connectivity between layers, thus enabling signals to be dynamically switched across layers. As represented by the signal paths (e.g., the signal paths <NUM> and <NUM>) between circuits (e.g., the circuits <NUM> and <NUM>) and the dynamically programmable switches (e.g., the switches <NUM> and <NUM>), one or more of the circuits of the 3D-IC <NUM> may control the dynamically programmable switches. As represented by the signal paths (e.g., the signal path <NUM>) between the dynamically programmable switches (e.g., the switches <NUM> and <NUM>), one or more of the dynamically programmable switches control another dynamically programmable switch or route corresponding control signals thereto.

Through the use of such dynamically programmable switches, signal paths on different layers are dynamically coupled and decoupled. Signal paths in accordance with the claimed invention are depicted in <FIG> where a first die layer <NUM> and a second die layer <NUM> are coupled to an interposer (interposer layer) <NUM>. Here, a first signal path <NUM> of the first die layer <NUM> is electrically coupled to a first switch circuit (DPS) <NUM>. For example, the first signal path <NUM> may be a signal bus, a test signal path, a power distribution path, or some other signal path that is electrically coupled to a first circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.). In accordance with the claimed invention, the first signal path is a test signal path. A second signal path <NUM> of the second die layer <NUM> is electrically coupled to a second switch circuit <NUM>. The second signal path <NUM> is electrically coupled to a second circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.). A third signal path <NUM> is routed from the first die layer <NUM> to the second die layer <NUM> through the interposer <NUM>, thereby electrically coupling the first switch circuit <NUM> and the second switch circuit <NUM>. Thus, the first signal path <NUM> is dynamically coupled to and uncoupled from the second signal path <NUM>.

Referring to <FIG>, in some aspects, each of the switch circuits may be located at a periphery of a die. In this way, heat dissipation on the die may be improved and routing congestion on the die may be mitigated as compared to conventional architectures. For example, by locating the switch circuits in this manner, improved heat transfer may be achieved from the center to the edge of the IC package (e.g., through an RDL and TSVs). Moreover, this scheme is much simpler than micro-channel solutions for thermal management.

<FIG> is a schematic representation of an example of switches located at a periphery of a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first switch circuit <NUM> is located at a first periphery <NUM> of the first layer <NUM>, and a second switch circuit <NUM> is located at a second periphery <NUM> of the second layer <NUM>.

In some aspects, switch circuits may be used in a power distribution network of a 3D-IC to distribute power to other circuits (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.). <FIG> is a schematic representation of an example of power distribution in a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first power distribution path <NUM> (e.g., for providing power to a first circuit <NUM>) of the second layer <NUM> is electrically coupled to a first switch circuit <NUM>. Similarly, a second power distribution path <NUM> (e.g., for providing power to a second circuit <NUM>) of the first layer <NUM> is electrically coupled to a second switch circuit <NUM>. In addition, a third power distribution path <NUM> electrically couples the first switch circuit <NUM> and the second switch circuit <NUM>. Thus, power may be dynamically switched between layers as needed.

In some aspects, one or more of the switch circuits may each include a power control circuit for supplying power to a corresponding layer (e.g., die layer). <FIG> is a schematic representation of an example of power control circuits in a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first switch circuit <NUM> on the first layer <NUM> includes a first supply voltage control circuit (SVCC) <NUM>, and a second switch circuit <NUM> on the second layer <NUM> includes a second supply voltage control circuit <NUM>. Thus, the first SVCC <NUM> may control power supplied to a first circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.) via a first supply path <NUM> on the first layer <NUM>. In addition, the second SVCC <NUM> may control power supplied to a second circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.) via a second supply path <NUM> on the second layer <NUM>. Accordingly, independent power control can be provided on a layer-by-layer basis through the use of peripheral switches as taught herein. Moreover, in some aspects, the first SVCC <NUM> and the second SVCC <NUM> may cooperate via signaling <NUM> to provide power to the different layers.

Referring to <FIG>, in some aspects, more than one power supply voltage level may be used on a given die. For example, one or more of the supply voltage control circuits of <FIG> may each generate a plurality of supply voltage levels used by different voltage domains on a respective die.

<FIG> is a schematic representation of an example of multi-level supply voltage circuits in a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first switch circuit <NUM> on the first layer <NUM> includes a first voltage supply circuit <NUM> coupled to a first supply path <NUM> of the first layer <NUM> and a second voltage supply circuit <NUM> coupled to a second supply path <NUM> of the first layer <NUM>. Similarly, a second switch circuit <NUM> on the second layer <NUM> includes a first voltage supply circuit <NUM> coupled to a first supply path <NUM> of the second layer <NUM> and a second voltage supply circuit <NUM> coupled to a second supply path <NUM> of the second layer <NUM>. Thus, different power levels can be independently provided on a layer-by-layer basis through the use of peripheral switches as taught herein. For example, different dies manufactured using different processes may employ different power levels (e.g., <NUM> V versus <NUM> V). Accordingly, a single power supply voltage (e.g., a main supply signal <NUM>) could be supplied to the peripheral switches whereby the voltage supply circuit(s) on each peripheral switch provides the appropriate voltage level(s) for the die(s) on the corresponding level.

Referring to <FIG>, in some aspects, one or more of the switch circuits may each include a voltage shifter circuit that is used to shift the level of a signal on a respective die. For example, the level of a signal may need to be shifted to accommodate different voltage domains (e.g., on different dies) that use different supply voltage levels.

<FIG> is a schematic representation of an example of signal level shifter circuits in a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first switch circuit <NUM> on the first layer <NUM> includes a first voltage level shifter (VLS) <NUM> coupled to a first signal path <NUM> and a second signal path <NUM> of the first layer <NUM>. Thus, the first VLS <NUM> may shift the signaling level of a signal received on the first signal path <NUM> (e.g., from one die) to a different signaling level and output the resulting signal on the second signal path <NUM> (e.g., to a different die). Similarly, a second switch circuit <NUM> on the second layer <NUM> includes a second VLS <NUM> coupled to a third signal path <NUM> and a fourth signal path <NUM> of the second layer <NUM>. Accordingly, the second VLS <NUM> may shift the signaling level of a signal received on the third signal path <NUM> to a different signaling level and output the resulting signal on the fourth signal path <NUM>.

Referring to <FIG>, a memory device (e.g., a register file) can be included in a peripheral switch to store data. For example, data from a die may be stored in such a memory device prior to shutting down the individual die (e.g., due to a fault condition). <FIG> is a schematic representation of an example of memory circuits in a 3D-IC <NUM> in accordance with some aspects of the disclosure. <FIG> includes a plan view as shown in <FIG>, and a side sectional view as shown in <FIG> taken from the view A-A of <FIG>.

The 3D-IC <NUM> includes a first layer (e.g., die) <NUM> and a second layer (e.g., die) <NUM>. As indicated, a first switch circuit <NUM> on the first layer <NUM> includes a first memory device (MD) <NUM> that is coupled to a first signal path <NUM> of the first layer <NUM>. Similarly, a second switch circuit <NUM> on the second layer <NUM> includes a second memory device <NUM> that is coupled to a second signal path <NUM> of the second layer <NUM>. Accordingly, data from a first circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.) on the first layer <NUM> and/or a second circuit <NUM> (e.g., at least one logic circuit, at least one digital circuit, at least one analog circuit, etc.) on the second layer <NUM> may be stored in the first MD <NUM> and/or the second MD <NUM>.

As mentioned above, dies may be oriented with respect to each other in different ways in different implementations. <FIG> illustrate three non-limiting examples of potential orientations.

<FIG> is a side view of a simplified example of offset dies <NUM> in accordance with some aspects of the disclosure. Here, a first die <NUM> is offset (horizontally in this view) from a second die <NUM>. In accordance with the teachings herein, at least one peripheral switch <NUM> is included in and/or coupled to each of the first and second dies <NUM> and <NUM>.

<FIG> is a side view of a simplified example of dies in different geometric planes <NUM> in accordance with some aspects of the disclosure. In this case, a first die <NUM> is at a right angle to a second die <NUM>. In accordance with the teachings herein, at least one peripheral switch <NUM> is included in and/or coupled to each of the first and second dies <NUM> and <NUM>.

<FIG> is a simplified example of dies in different geometric planes <NUM> in accordance with some aspects of the disclosure. <FIG> includes a perspective view as shown in <FIG>, and a plan view as shown in <FIG>. In this example, a first die <NUM>, a second die <NUM>, and a third die <NUM> are all at right angles with respect to one another. In accordance with the teachings herein, at least one peripheral switch <NUM> is included in and/or coupled to each of the first die <NUM>, the second die <NUM>, and the third die <NUM>.

It should be appreciated that dies need not be disposed at right angles as shown in <FIG> and <FIG>. Rather, it may be advantageous to route dies at other angles in some implementations.

<FIG> is an illustration of an apparatus <NUM> that may be implemented as a 3D-IC according to one or more aspects of the disclosure. The apparatus <NUM> includes a communication interface (e.g., at least one transceiver) <NUM>, a storage medium <NUM>, a user interface <NUM>, a memory device <NUM>, and a processing circuit <NUM>.

These components can be coupled to and/or placed in electrical communication with one another via a signaling bus or other suitable component, represented generally by the connection lines in <FIG>. The signaling bus may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The signaling bus links together various circuits such that each of the communication interface <NUM>, the storage medium <NUM>, the user interface <NUM>, and the memory device <NUM> are coupled to and/or in electrical communication with the processing circuit <NUM>. The signaling bus may also link various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The communication interface <NUM> may be adapted to facilitate wireless communication of the apparatus <NUM>. For example, the communication interface <NUM> may include circuitry and/or programming adapted to facilitate the communication of information bi-directionally with respect to one or more communication devices in a network. The communication interface <NUM> may be coupled to one or more antennas <NUM> for wireless communication within a wireless communication system. The communication interface <NUM> can be configured with one or more standalone receivers and/or transmitters, as well as one or more transceivers. In the illustrated example, the communication interface <NUM> includes a transmitter <NUM> and a receiver <NUM>.

The memory device <NUM> may represent one or more memory devices. As indicated, the memory device <NUM> may maintain switch information <NUM> along with other information used by the apparatus <NUM>. In some implementations, the memory device <NUM> and the storage medium <NUM> are implemented as a common memory component. The memory device <NUM> may also be used for storing data that is manipulated by the processing circuit <NUM> or some other component of the apparatus <NUM>.

The storage medium <NUM> may represent one or more computer-readable, machine-readable, and/or processor-readable devices for storing programming, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. The storage medium <NUM> may also be used for storing data that is manipulated by the processing circuit <NUM> when executing programming. The storage medium <NUM> may be any available media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying programming.

By way of example and not limitation, the storage medium <NUM> may include a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The storage medium <NUM> may be embodied in an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium in packaging materials. In view of the above, in some implementations, the storage medium <NUM> may be a non-transitory (e.g., tangible) storage medium.

The storage medium <NUM> may be coupled to the processing circuit <NUM> such that the processing circuit <NUM> can read information from, and write information to, the storage medium <NUM>. That is, the storage medium <NUM> can be coupled to the processing circuit <NUM> so that the storage medium <NUM> is at least accessible by the processing circuit <NUM>, including examples where at least one storage medium is integral to the processing circuit <NUM> and/or examples where at least one storage medium is separate from the processing circuit <NUM> (e.g., resident in the apparatus <NUM>, external to the apparatus <NUM>, distributed across multiple entities, etc.).

Programming stored by the storage medium <NUM>, when executed by the processing circuit <NUM>, causes the processing circuit <NUM> to perform one or more of the various functions and/or process operations described herein. For example, the storage medium <NUM> may include operations configured for regulating operations at one or more hardware blocks of the processing circuit <NUM>, as well as to utilize the communication interface <NUM> for wireless communication utilizing their respective communication protocols.

The processing circuit <NUM> is generally adapted for processing, including the execution of such programming stored on the storage medium <NUM>. As used herein, the term "programming" shall be construed broadly to include without limitation instructions, instruction sets, data, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

The processing circuit <NUM> is arranged to obtain, process and/or send data, control data access and storage, issue commands, and control other desired operations. The processing circuit <NUM> may include circuitry configured to implement desired programming provided by appropriate media in at least one example. For example, the processing circuit <NUM> may be implemented as one or more processors, one or more controllers, and/or other structure configured to execute executable programming. Examples of the processing circuit <NUM> may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit <NUM> may also be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, or any other number of varying configurations. These examples of the processing circuit <NUM> are for illustration and other suitable configurations within the scope of the disclosure are also contemplated.

According to one or more aspects of the disclosure, the processing circuit <NUM> may be adapted to perform any or all of the features, processes, functions, operations and/or routines for any or all of the apparatuses described herein. As used herein, the term "adapted" in relation to the processing circuit <NUM> may refer to the processing circuit <NUM> being one or more of configured, employed, implemented, and/or programmed to perform a particular process, function, operation and/or routine according to various features described herein.

According to at least one example of the apparatus <NUM>, the processing circuit <NUM> may include one or more of a first module for controlling a first switch circuit <NUM>, a second module for controlling a second switch circuit <NUM>, and a third module for controlling a third switch circuit <NUM>.

The first module for controlling a first switch circuit <NUM> may include circuitry and/or programming (e.g., a first module for controlling a first switch circuit <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example controlling a switch circuit to couple electrical paths on one die to electrical paths on another die. In some aspects, this coupling is achieved via another switch circuit on the other die. Initially, the first module for controlling a first switch circuit <NUM> obtains received information (e.g., from the memory device <NUM>, the receiver <NUM>, or some other component). For example, the first module for controlling a first switch circuit <NUM> may receive an indication that affects how the switch circuit is to be controlled. In some implementations, the first module for controlling a first switch circuit <NUM> identifies a memory location in the memory device <NUM> that stores the indication and invokes a read of that location. In some implementations, the first module for controlling a first switch circuit <NUM> processes the received indication to determine how to control the switch circuit. The first module for controlling a first switch circuit <NUM> then generates, based on the received information, a control signal that controls the switch circuit.

The second module for controlling a second switch circuit <NUM> may include circuitry and/or programming (e.g., a second module for controlling a second switch circuit <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example controlling a switch circuit to couple electrical paths on one die to electrical paths on another die. In some aspects, this coupling is achieved via another switch circuit on the other die. Initially, the second module for controlling a second switch circuit <NUM> obtains received information (e.g., from the memory device <NUM>, the receiver <NUM>, or some other component). For example, the second module for controlling a second switch circuit <NUM> may receive an indication that affects how the switch circuit is to be controlled. In some implementations, the second module for controlling a second switch circuit <NUM> identifies a memory location in the memory device <NUM> that stores the indication and invokes a read of that location. In some implementations, the second module for controlling a second switch circuit <NUM> processes the received indication to determine how to control the switch circuit. The second module for controlling a second switch circuit <NUM> then generates, based on the received information, a control signal that controls the switch circuit.

The third module for controlling a third switch circuit <NUM> may include circuitry and/or programming (e.g., a third module for controlling a third switch circuit <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example controlling a switch circuit to couple electrical paths on one die to electrical paths on another die. In some aspects, this coupling is achieved via another switch circuit on the other die. Initially, the third module for controlling a third switch circuit <NUM> obtains received information (e.g., from the memory device <NUM>, the receiver <NUM>, or some other component). For example, the third module for controlling a third switch circuit <NUM> may receive an indication that affects how the switch circuit is to be controlled. In some implementations, the third module for controlling a third switch circuit <NUM> identifies a memory location in the memory device <NUM> that stores the indication and invokes a read of that location. In some implementations, the third module for controlling a third switch circuit <NUM> processes the received indication to determine how to control the switch circuit. The third module for controlling a third switch circuit <NUM> then generates, based on the received information, a control signal that controls the switch circuit.

As mentioned above, programming stored by the storage medium <NUM>, when executed by the processing circuit <NUM>, causes the processing circuit <NUM> to perform one or more of the various functions and/or process operations described herein. For example, the storage medium <NUM> may include one or more of the first module for controlling a first switch circuit <NUM>, the second module for controlling a second switch circuit <NUM>, or the third module for controlling a third switch circuit <NUM>.

<FIG> illustrates a switching process <NUM> in accordance with some aspects of the disclosure. The process <NUM> may take place within a 3D-IC (e.g., one or more of the 3D-IC of any of <FIG>, <FIG>, <FIG>, or <FIG>), at least partially within a processing circuit (e.g., the processing circuit <NUM> of <FIG>), which may be located in an electronic device, a transceiver, or some other suitable apparatus. Of course, in various aspects within the scope of the disclosure, the process <NUM> may be implemented by any suitable apparatus capable of supporting switching operations.

At block <NUM>, a signal is received via a first signal path at a first switch circuit. The first switch circuit is on a first die that lies within a first geometric plane.

The signal may take different forms in different implementations. In some aspects, the signal may be a test signal (e.g., that is selectively routed between first and second dies). In some aspects, the signal may be a power supply voltage signal (e.g., a +<NUM> V supply voltage, a -<NUM> V supply voltage, etc.).

At block <NUM>, the first switch circuit is controlled via a first circuit to route the signal to a second switch circuit. The first circuit is on the first die. The second switch circuit is on a second die that lies within a second geometric plane. The second geometric plane is different from the first geometric plane.

At block <NUM>, the second switch circuit is controlled via a second circuit to route the signal to a second signal path. The second circuit is on the second die.

In some aspects, the first and second circuits include logic circuits. In some aspects, the first and second switch circuits include analog switch circuitry.

The first and second die may be oriented relative to one another in various ways. In some cases, the second die is stacked on top of the first die. In some cases, the first and second geometric planes are parallel, while in other cases they might not be.

In some implementations, the signal is routed to at least one other die. For example, the process <NUM> also may include controlling the second switch circuit via the second logic circuit to route the signal to a third switch circuit, where the third circuit is on a third die lying within a third geometric plane that is different from the first and second geometric planes. The process <NUM> may then include controlling the third switch circuit via a third logic circuit to route the signal to a third signal path, where the third logic circuit is on the third die.

<FIG> illustrates a process <NUM> for handling a fault condition in accordance with some aspects of the disclosure. The process <NUM> may take place within a 3D-IC (e.g., one or more of the 3D-IC of any of <FIG>, <FIG>, <FIG>, or <FIG>), at least partially within a processing circuit (e.g., the processing circuit <NUM> of <FIG>), which may be located in an electronic device, a transceiver, or some other suitable apparatus. Of course, in various aspects within the scope of the disclosure, the process <NUM> may be implemented by any suitable apparatus capable of supporting fault operations.

At block <NUM>, a fault condition is identified on the first die. For example, a diagnostic test performed on a component of the first die may have returned a failure indication.

At block <NUM>, routing of the signal to the second signal path (e.g., at block <NUM> above) may be triggered as a result of the identification of the fault condition at block <NUM>.

At block <NUM>, in some implementations, the first die is disabled as a result of the identification of the fault condition at block <NUM>.

Claim 1:
An integrated circuit, comprising:
a first die (<NUM>) lying within a first geometric plane and comprising a first circuit (<NUM>) and a first switch circuit (<NUM>, <NUM>), and a first signal path (<NUM>) between the first circuit and first switch circuit, the first switch circuit and the first signal path electrically coupled to the first circuit;
a second die (<NUM>) lying within a second geometric plane that is different from the first geometric plane, the second die comprising a second circuit (<NUM>) and a second switch circuit (<NUM>, <NUM>), and a second signal path (<NUM>) between the second circuit and second switch circuit, the second switch circuit electrically coupled to the second circuit and the second signal path;
and a third signal path (<NUM>) routed from the first switch circuit (<NUM>) to the second switch circuit (<NUM>), and electrically coupling the first switch circuit to the second switch circuit;
wherein each of the first switch circuit (<NUM>) and second switch circuit (<NUM>) comprises a dynamically programmable switch, characterized in that the dynamically programmable switches are configured to dynamically couple the first signal path to - and decouple the first signal path from -
the second signal path, the first signal path being a test signal path and the second signal path being a test signal path.