Patent Description:
Usually, transistor arrangements include a plurality of transistor devices formed in a semiconductor body. A superjunction transistor device, for example, usually includes at least one drift region of a first doping type (conductivity type) and a compensation region of a second doping type (conductivity type) complementary to the first doping type. The drift region and the compensation region are connected such that in an on-state (switched on state) of the transistor device a current can flow in the drift region, while in the off-state (switched off state) a depletion region expands in the drift region and the compensation region that prevents a current flow through the drift region. A transistor arrangement including a plurality of superjunction transistor devices, therefore, includes a plurality of drift regions and compensation regions. The drift regions and compensation regions of a transistor arrangement may be implemented as a layer stack with a plurality of first semiconductor layers of the first doping type and a plurality of second semiconductor layers of the second doping type.

Document <CIT> discloses a semiconductor device manufactured in a semiconductor body of a wafer by forming a mask on a surface of the semiconductor body. The mask has a plurality of first mask openings in a transistor cell area and a mask opening design outside the transistor cell area. The mask opening design includes one second mask opening or a plurality of second mask openings encircling the transistor cell area. The plurality of second mask openings are consecutively arranged at lateral distances smaller than a width of the plurality of second mask openings. A plurality of first trenches are formed in the semiconductor body at the first mask openings. One or a plurality of second trenches are formed at the one or plurality of second mask openings. The first trenches and the one or more of the plurality of second trenches are filled with a filling material including at least a semiconductor material.

<CIT> further discloses a method comprising: forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier, wherein the first layers and the second layers are arranged alternatingly within the layer stack,.

forming the layer stack comprises forming a plurality of epitaxial layers on the carrier, forming each of the plurality of epitaxial layers comprises depositing a layer of semiconductor material, forming at least two first implantation regions of one of said first doping type or said second doping type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of the doping type that is complementary to the doping type of the first implantation regions, wherein the first implantation regions and the second implantation regions are arranged alternatingly, wherein forming implantation regions of the first doping type comprises implanting ions of the first doping type, forming implantation regions of the second type comprises implanting ions of the second doping type; and heating the epitaxial layers with the implantation regions formed therein, thereby diffusing the implanted ions and the first implantation regions forming the first layers and the second implantation regions forming the second layers.

Document <CIT> discloses a transistor device including: a first source region and a first drain region spaced apart from each other in a first direction of a semiconductor body; at least two gate regions arranged between the first source region and the first drain region and spaced apart from each other in a second direction of the semiconductor body; at least one drift region adjoining the first source region and electrically coupled to the first drain region; at least one compensation region adjoining the at least one drift region and the at least two gate regions; a MOSFET including a drain node connected to the first source region, a source node connected to the at least two gate region, and a gate node. Active regions of the MOSFET are integrated in the semiconductor body in a device region that is spaced apart from the at least two gate regions.

It is desirable to provide a semiconductor device that requires as few production steps as possible and that may be produced at low costs, and a fast and cost effective method for producing the same.

One example relates to a method for producing a semiconductor device. The method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. The first and second layers are arranged alternatingly within the layer stack. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, wherein the first implantation regions and the second implantation regions are arranged alternatingly. Forming implantation regions of the first type comprises implanting ions of a first type, and forming implantation regions of the second type comprises implanting ions of a second type. The method further includes heating the epitaxial layers with the implantation regions formed therein, thereby diffusing the implanted ions and forming the first and second layers. If two or more first semiconductor layers are formed within the same epitaxial layer, the different first semiconductor layers within the respective epitaxial layer have different thicknesses, the thickness decreasing towards the top of the layer stack. If two or more second semiconductor layers are formed within the same epitaxial layer, the different second semiconductor layers within the respective epitaxial layer have different thicknesses, the thickness decreasing towards the top of the layer stack. The type of the topmost implantation region of an epitaxial layer differs from the type of a directly adjoining lowermost implantation region of a subsequent epitaxial layer.

Another example relates to a semiconductor device. The semiconductor device includes a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. The first and second layers are arranged alternatingly within the layer stack. The first and second layers are arranged in a plurality of groups, each of the plurality of groups including at least two layers of one of the first or the second doping type, and at least one further layer of the complementary doping type. If a group comprises two or more first layers, a thickness of the different first layers within the respective group decreases towards the top of the layer stack, and, if a group comprises two or more second layers, a thickness of the different second layers within the respective group decreases towards the top of the layer stack. The type of the topmost layer of a group differs from the type of a directly adjoining lowermost layer of a subsequent group.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

<FIG> show a perspective sectional view (<FIG>), a vertical cross sectional view (<FIG>), and a horizontal cross sectional view (<FIG>) of a transistor arrangement that includes a first semiconductor component M1 (here: first transistor device) and a second semiconductor component M2 (here: second transistor device). The transistor arrangement includes a layer stack with a plurality of first semiconductor layers <NUM> of a first doping type and a plurality of second semiconductor layers <NUM> of a second doping type that are arranged alternatingly. The second doping type is complementary to the first doping type. A source region <NUM> of the first transistor device M1 adjoins the plurality of first semiconductor layers <NUM>, and a drain region <NUM> of the first transistor device M1 adjoins the plurality of first semiconductor layers <NUM> and is located spaced apart from the source region <NUM> in a first direction x. The source region <NUM> of the first transistor device M1 is also referred to as first source region <NUM> in the following, and the drain region <NUM> of the first transistor device M1 is also referred to as first drain region <NUM> in the following. The transistor arrangement further includes a plurality of gate regions <NUM> of the first transistor device M1. Each of the plurality of gate regions <NUM> adjoins at least one of the plurality of second semiconductor layers <NUM>, is arranged between the first source region <NUM> and the first drain region <NUM>, and is spaced apart from the first source region <NUM> and the first drain region <NUM>.

As used herein, a layer or region of the first doping type is a layer or region with an effective doping of the first doping type. Such region or layer of the first doping type, besides dopants of the first doping type, may also include dopants of the second doping type, but the dopants of the first doping type prevail. Equivalently, a layer or region of the second doping type is a layer or region with an effective doping of the second doping type and may contain dopants of the first doping type.

Still referring to <FIG>, the transistor arrangement further includes a third semiconductor layer <NUM> that adjoins the layer stack with the first layers <NUM> and the second layers <NUM> and each of the first source region <NUM>, the first drain region <NUM>, and the gate regions <NUM>. Active regions of the second transistor device M2 are integrated in the third semiconductor layer <NUM> in a second region <NUM>. The second region <NUM> is spaced apart from a first region <NUM> of the third semiconductor layer <NUM>, wherein the first region <NUM> is bordered by the first source region <NUM> and the first drain region <NUM>. At least the first region <NUM> is a region of the second doping type. The second transistor device M2 is only schematically illustrated in <FIG> and represented by a circuit symbol.

The third semiconductor layer <NUM> and the layer stack with the first and second semiconductor layers <NUM>, <NUM> form an overall layer stack <NUM>, which is also referred to as semiconductor body <NUM> in the following. The semiconductor body <NUM> may include a conventional semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. The semiconductor body <NUM> may be arranged on any kind of carrier <NUM> (illustrated in dashed lines in <FIG>. Examples of this carrier <NUM> are explained herein further below.

According to one example, the overall number of first layers <NUM> in the layer stack equals the overall number of second layers <NUM>. In the example shown in <FIG>, an uppermost layer of the layer stack is a second layer <NUM> and a lowermost layer is a first layer <NUM>. The "uppermost layer" is the layer adjoining the third layer <NUM>, and the lowermost layer is the layer spaced apart from the uppermost layer most distantly. However, implementing the uppermost layer as a second layer <NUM> and the lowermost layer as a first layer <NUM> is only an example. According to another example (not illustrated) the uppermost layer is a first layer <NUM> and the lowermost layer is a second layer <NUM>. Just for the purpose of illustration, the layer stack with the first and second layers <NUM>, <NUM> includes two first layers <NUM> and two second layers <NUM>, that is, four layers overall. This, however, is only an example. According to one example, the overall number of first and second layers <NUM>, <NUM> in the layer stack is between <NUM> and <NUM>, in particular between <NUM> and <NUM>.

The first direction, which is the direction in which the first source region <NUM> and the first drain region <NUM> are spaced apart from each other, is a first lateral direction x of the semiconductor body <NUM> in the example shown in <FIG>. A "lateral direction" of the semiconductor body <NUM> is a direction parallel to a first surface <NUM> of the semiconductor body <NUM>. The first and second layers <NUM>, <NUM> and the third layer <NUM> are essentially parallel to the first surface <NUM> in the example shown in <FIG>. In this example, each of the first source region <NUM> and the first drain region <NUM> extend in a vertical direction z into the semiconductor body <NUM> so that each of the first source region <NUM> and the first drain region <NUM> adjoins the third layer <NUM> and the first layers <NUM>. The "vertical direction" z is a direction perpendicular to the first surface <NUM>. Further, the gate regions <NUM> extend in the vertical direction z in the semiconductor body <NUM> so that each of the plurality of gate regions <NUM> adjoins each of the second semiconductor layers <NUM>. The gate regions <NUM> are spaced apart from each other in a second lateral direction y. This second lateral direction y is different from the first lateral direction x and may be perpendicular to the first lateral direction x.

In the example illustrated in <FIG>, the first transistor device M1 is a lateral superjunction depletion device, more specifically, a lateral superjunction JFET (Junction Field-Effect Transistor). In this transistor device M1, each of the first source region <NUM> and the first drain region <NUM> is a region of the first doping type and each of the gate regions <NUM> is a region of the second doping type. Further, in the section of the semiconductor body <NUM> between the first source region <NUM> and the first drain region <NUM>, the first semiconductor layers <NUM> form drift regions <NUM> and the second semiconductor layers <NUM> form compensation regions <NUM> of the superjunction device. The function of these drift and compensation regions <NUM>, <NUM> is explained herein further below.

A type of this first transistor device M1 is defined by the first doping type. The first transistor device M1 is an n-type JFET when the first doping type is an n-type and the second doping type is a p-type. Equivalently, the first transistor device M1 is a p-type JFET when the first doping type is a p-type and the second doping type is an n-type.

According to one example, the first source region <NUM>, the first drain region <NUM>, the plurality of gate regions <NUM>, the first and second layers <NUM>, <NUM> forming the drift and compensation regions <NUM>, <NUM>, and the third layer <NUM> are monocrystalline semiconductor regions. According to one example, these regions include monocrystalline silicon (Si) and a doping concentration of the first source region <NUM> is selected from a range of between 1E17 cm-<NUM> (=<NUM>·<NUM><NUM> cm-<NUM>) and 1E21 cm-<NUM>, a doping concentration of the drift regions <NUM> is selected from a range of between 1E13 cm-<NUM> and 5E17 cm-<NUM>, and a doping concentration of the gate regions <NUM> is selected from a range of between 1E17 cm-<NUM> and 1E21 cm-<NUM>. The doping concentration of the first drain region <NUM> can be selected from the same range as the doping concentration of the first source region <NUM>, and the doping concentration of the compensation regions <NUM> can be selected from the same range as the doping concentration of the drift regions <NUM>.

Referring to <FIG>, the gate regions <NUM> of the first transistor device M1 are connected to a first gate node G1 and the first drain region <NUM> is connected to a first drain node D1. The first gate node G1 and the first drain node D1 are only schematically illustrated in <FIG>. These nodes G1, D1 may include metallizations (not illustrated) on top of the semiconductor body <NUM>. Optionally, as illustrated in dashed lines in <FIG>, a first connection electrode <NUM> may be embedded in each of the gate regions <NUM> and a second connection electrode <NUM> may be embedded in the drain region <NUM>. The first connection electrodes <NUM> are connected to the gate node G1 and serve to provide a low-ohmic connection between each section of the gate regions <NUM> and the first gate node G1. The second electrode <NUM> is connected to the drain node D1 and provides a low-ohmic connection between each section of the drain region <NUM> and the drain node D1. Further, a third electrode <NUM> may be embedded in the first source region <NUM>. Referring to <FIG>, each of the first, second and third connection electrodes <NUM>, <NUM>, <NUM> may extend along a complete length of the respective semiconductor region <NUM>, <NUM>, <NUM> in the vertical direction z. Each of these electrodes <NUM>, <NUM>, <NUM> includes an electrically conducting material. Examples of such electrically conducting material include, but are not restricted to: a metal such as copper (Cu), aluminum (Al), tantalum (Ta), titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (W); a highly doped polycrystalline semiconductor material such as polysilicon; or a metal silicide, such as tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi).

The main function of the third semiconductor layer <NUM> is to accommodate the second transistor device M2. Therefore, the semiconductor layer <NUM> is designed such that it provides sufficient space to integrate active regions of the second transistor device M2 in the second region <NUM>. According to one example, a thickness of the third semiconductor layer <NUM> in the second region <NUM> is between <NUM> micrometers (µm) and <NUM> micrometers, in particular between <NUM> and <NUM> micrometers. The "thickness" is the dimension of the third layer <NUM> in the vertical direction z. According to an example, a thickness of the third semiconductor layer <NUM> is at least twice a thickness of a single first semiconductor layer <NUM> or a single second semiconductor layer <NUM>. According to one example, a thickness of the third semiconductor layer <NUM> is at least twice a thickness of each of the first semiconductor layers <NUM> and the second semiconductor layers <NUM>. The thickness of a single first semiconductor layer <NUM> or a single second semiconductor layer <NUM> is, for example, between <NUM> nanometers (nm) and <NUM> micrometers (µm). According to another example, a thickness of the third semiconductor layer <NUM> is greater than a distance between the first source region <NUM> and each of the gate regions <NUM>.

In or on top of the first region <NUM> the transistor arrangement may include an edge termination structure (not shown in <FIG>). This edge termination structure may reduce the thickness of the third layer <NUM> in the first region <NUM> as compared to the second region <NUM>.

At least the first region <NUM> of the third semiconductor layer <NUM> is a region of the second doping type so that a first p-n junction is formed between the first drain region <NUM> and the first region <NUM> and a second p-n junction is formed between the first source region <NUM> and the first region <NUM>. These p-n junctions are part of two bipolar diodes, a first bipolar diode BD1 formed by the gate regions <NUM>, the first region <NUM> and the first drain region <NUM>, and a second bipolar diode BD2 formed by the gate regions <NUM>, the first region <NUM> and the first source region <NUM>. In each of these bipolar diodes BD1, BD2, the first region <NUM> of the third semiconductor layer <NUM> forms a base region. Circuit symbols of these bipolar diodes BD1, BD2 are shown in <FIG>. According to one example, a doping concentration of the first region <NUM> of the third semiconductor layer <NUM> is such that a voltage blocking capability of the first bipolar diode BD1 is equal to or higher than a voltage blocking capability of the first transistor device M1.

The "voltage blocking capability" of the first transistor device M1 is defined by a maximum level of a voltage between the first drain node D1 and the gate node G1 the first transistor device M1 can withstand in an off-state. Dependent on the specific design, the voltage blocking capability may range from 20V up to several <NUM> volts. This voltage blocking capability may be adjusted, inter alia, by suitably selecting a distance between the first gate region <NUM> and the first drain region <NUM>. In a first transistor device with a voltage blocking capability of <NUM> volts, for example, the distance may be selected from between <NUM> micrometers and <NUM> micrometers and a doping concentration of the first region <NUM> may be selected from a range of between 1E13 cm-<NUM> and 1E15 cm-<NUM>, in particular from between <NUM> E14 cm-<NUM> and <NUM>. 6E14 cm-<NUM>.

The layer stack with the first and second semiconductor layers <NUM>, <NUM> adjoins the third layer <NUM> and, therefore, the second region <NUM> in which active regions of the second transistor device M2 are integrated. However, the third layer <NUM> and, in particular, the second region <NUM> is not obtained based on the first and second layers <NUM>, <NUM>. That is, the second region <NUM> is not obtained by additionally doping sections of the first and second layers <NUM>, <NUM> with dopants of the second doping type in order to obtain an effective doping of the second doping type.

Referring to <FIG>, the first source region <NUM> is electrically connected to a drain node D2 of the second transistor device M2. The second transistor device M2 further includes a gate node G2 and a source node S2. According to one example, the second transistor device M2 is a normally-off transistor device such as, for example, an enhancement MOSFET. Just for the purpose of illustration, the circuit symbol of the second transistor device M2 shown in <FIG> represents an n-type enhancement MOSFET. This, however, is only an example. The second transistor device may be implemented as a p-type enhancement MOSFET or a p-type or n-type depletion MOSFET as well.

Optionally, as illustrated in dashed lines in <FIG>, those sections of the second semiconductor layers <NUM> that are arranged below the second region <NUM> and are separated from those sections that form the compensation regions <NUM> are connected to the second source node S2. Connections between these second layers <NUM> and the second source node S2 are schematically illustrated in <FIG>.

The first and second transistor device M1, M2 can be interconnected in various ways. According to one example, the source node S2 of the second transistor device M2 is connected to the gate node G1 of the first transistor device M1. An electronic circuit diagram of a transistor arrangement in which the gate node G1 of the first transistor device M1 is connected to the source node S2 of the second transistor device M2 is shown in <FIG>. Just for the purpose of illustration and the following explanation it is assumed that the first transistor device M1 is an n-type JFET and the second transistor device M2 is an n-type enhancement MOSFET. The second gate node G2, the second source node S2 and the first drain node D1 are circuit nodes that may serve to connect the transistor arrangement to other devices, a power source, ground or the like in an electronic circuit.

The transistor arrangement may include a housing (package) <NUM> that is schematically illustrated in <FIG>. In this case, the second gate node G2, the second source node S2 and the first drain node D1 are external circuit nodes that are accessible outside the housing <NUM>. According to one example, the gate node G1 of the first transistor device M1 is connected to the source node S2 of the second transistor device M2 inside the housing. A connection between the second source node S2 and the first gate node G1 may be formed by a wiring arrangement (not shown in the figures) that is located on top of the first surface <NUM> of the semiconductor body <NUM>. According to another example, the first gate node G1 is accessible outside the housing <NUM> and the first gate node G1 is connected to the second source node S2 by a connection outside the housing <NUM>.

Although the transistor arrangement includes two transistors, first transistor device (JFET) M1 and second transistor device (MOSFET), it can be operated like one single transistor. An operation state of the transistor arrangement is defined by an operation state of the MOSFET M2. The transistor arrangement acts like a voltage controlled transistor that switches on or off dependent on a drive voltage VGS2 received between the second gate node G2 and the second source node S2. This drive voltage is also referred to as gate-source voltage VGS2 in the following.

The function of the transistor arrangement shown in <FIG> and <FIG> is explained below. Just for the purpose of explanation, it is assumed that the first transistor device M1 is an n-type JFET and the second transistor device M2 is an n-type enhancement MOSFET. Furthermore, for the purpose of explanation, it is assumed that the transistor arrangement operates as an electronic switch connected in series with a load Z, wherein a series circuit with the load Z and the transistor device receives a supply voltage V1.

Referring to <FIG>, the MOSFET M2 is controlled by the gate-source voltage VGS2 received between the second gate node G2 and the second source node S2. The MOSFET M2 is in an on-state (conducting state) when a voltage level of the gate-source voltage VGS2 is higher than a predefined threshold voltage level Vth1. In an n-type enhancement MOSFET, the threshold voltage level Vth1 is a positive voltage level. The JFET M1 is controlled by a gate-source voltage VGS1 received between the first gate node G1 and the first source node S1. An n-type JFET, such as the JFET M1 illustrated in <FIG>, is in the on-state when a voltage level of the gate-source voltage, such as the gate-source voltage VGS1 shown in <FIG>, is higher than a predefined threshold level Vth2. That is, the JFET M1 is in the on-state, when VGS1 > Vth1, where Vth1 < <NUM>. As the gate node G1 of the JFET M1 is connected to the source node S2 of the MOSFET M2, the gate-source voltage VGS1 of the JFET M1 equals the inverted drain-source voltage VDS2 of the MOSFET M2, that is, VGS1 = -VDS2. The drain-source voltage VDS2 of the MOSFET M2 is the voltage between the drain node D2 and the source node S2 of the MOSFET M2.

When the MOSFET M2 is in the on-state, a magnitude of the drain-source voltage VDS2 is very low, so that the gate-source voltage VGS1 of the JFET is between the negative threshold level Vth1 and zero. Thus, the JFET M1 is also in the on-state. When the MOSFET M2 switches off, the drain-source voltage VDS2 increases until the inverted drain-source voltage -VDS2 reaches the negative threshold voltage Vth1, so that the JFET M1 also switches off.

Referring to <FIG>, in the on-state of the JFET M1 and the MOSFET M2, a current can flow from the first drain node D1 via the drain region <NUM>, the drift regions <NUM>, the first source region <NUM>, and the drain-source path D2-S2 of the MOSFET M2 to the second source node S2. When the MOSFET M2 switches off, the electrical potential at the first drain node D1 can increase relative to the electrical potential at the second source node S2. This increase of the electrical potential at the first drain node D1 causes an increase of the electrical potential at the first source region <NUM>, while the electrical potential at the gate regions <NUM> is tied to the electrical potential at the second source node S2. The increase of the electrical potential of the first source region <NUM> and the drift regions <NUM> causes p-n junctions between the first source region <NUM> and the compensation regions <NUM>, and between the gate regions <NUM> and the drift regions <NUM> to be reverse biased. Furthermore, p-n junctions between the drift regions <NUM> and the compensation regions <NUM> are reverse biased. Reverse biasing those p-n junctions causes the drift regions <NUM> to be depleted of charge carriers. The JFET M1 switches off as soon as the drift regions <NUM> between the at least two gate regions <NUM> and/or between the gate regions <NUM> and the first source region <NUM> has been completely depleted of charge carriers.

<FIG> shows a horizontal cross sectional view of the transistor device in a horizontal section plane C-C going through one of drift regions <NUM>. In <FIG>, reference character <NUM><NUM> denotes a section of the drift region <NUM> between two gate regions <NUM>, and <NUM><NUM> denotes a section of the at least one drift region <NUM> between the gate regions <NUM> and the first source region <NUM>. The threshold voltage Vth1 of the JFET M1 is the voltage that needs to be applied between the gate regions <NUM> and the first source region <NUM> in order to completely deplete at least one of these sections <NUM><NUM>, <NUM><NUM>. In <FIG>, d1 denotes a distance between two gate regions <NUM> in the second direction y. The magnitude (the level) of the threshold voltage Vth1 is dependent on several design parameters and can be adjusted by suitably designing these parameters. These design parameters include the (shortest) distance d1 between two gate regions <NUM>, a doping concentration of the drift region <NUM> in the section <NUM><NUM> between the gate regions <NUM>, and a doping concentration of the compensations region <NUM> (out of view in <FIG>) in a section that is located between the gate regions <NUM> and adjoins section <NUM><NUM> of the drift regions <NUM>.

According to one example, the drift regions <NUM> in the section <NUM><NUM> between the gate electrodes <NUM> include a higher doping concentration than in sections spaced apart from the gate regions <NUM> in the direction of the drain region <NUM>. This higher doped section <NUM><NUM> counteracts an increase in the on-resistance caused by the gate regions <NUM>, which reduces the cross section in which a current can flow between the source an drain regions <NUM> and <NUM>. According to one example, the compensation regions at least in parts of sections arranged between the gate regions <NUM> include a higher doping concentration than in other sections, in particular, those sections spaced apart from the gate electrodes <NUM> in the direction of the drain region <NUM>. This higher doped section ensures that the drift regions <NUM> in the section between the gate regions <NUM> is depleted of charge carriers, so that the JFET M1 blocks, when the threshold voltage Vth1 is applied. According to one example, the higher doped region of the at compensation regions <NUM> is not only arranged between the gate regions <NUM>, but surrounds the gate regions <NUM> in a horizontal plane, which is a plane parallel to the first surface <NUM>.

The MOSFET M2 may be designed such that a voltage blocking capability of this MOSFET M2 equals or is higher than a magnitude of threshold voltage Vth1 of the JFET M1, that is VDS2_MAX ≥ | Vth1 |, where VDS2_MAX is the voltage blocking capability of the MOSFET M2. The voltage blocking capability of the MOSFET M2 is the maximum voltage, the MOSFET M2 can withstand between the drain node D2 and the gate node G1.

In the example shown in <FIG>, the transistor arrangement includes three external circuit nodes, the first drain node D1, the second source node S2, and the second gate node G2. According to another example shown in <FIG>, in addition to these circuit nodes D1, S2, G2, the first source node S1 is also accessible. According to yet another example shown in <FIG>, the second transistor M2 may be deactivated by connecting the second gate node G2 with the second source node S2. In this case, only the first transistor device M1 is active and can be driven by applying a drive voltage VGS1 between the first gate node G1 and the first source node S1. According to one example, the first drain node D1, the first gate node G1, the first source node S1, the second gate node G2, and the second source node S2 are external circuit nodes that are accessible outside the housing. In this case, a user/costumer may choose one of the configurations shown in <FIG> by suitably connecting these circuit nodes D1, G1, S1, G2, and S2. <FIG> illustrates another example. In this example, the source nodes S1, S2, the drain nodes D1, D2, and the gate nodes G1, G2 of each of the first and second transistor device M1, M2 are accessible outside of the housing <NUM>.

According to one example, the first and second layers <NUM>, <NUM> are implemented such that the drift regions <NUM> and the compensation regions <NUM> are essentially balanced with regard to their dopant doses. That is, at each position in the current flow direction of the first transistor device, the amount of dopant atoms (dopant charges) in one drift region <NUM> essentially corresponds to the amount of dopant atoms in the neighboring compensation region <NUM>. "Essentially" means that there may be an imbalance of up to +/-<NUM>%. That is, there may be <NUM>% more or less dopant atoms in the drift regions <NUM> than in the compensation regions <NUM>. Thus, when the first transistor device is in the off-state and depletion regions (space charge regions) expand in the drift and compensation regions <NUM>, <NUM> essentially each doping atom in each drift region <NUM> has a corresponding doping atom (which may be referred to as counter doping atom) of a complementary doping in the compensation regions <NUM> and the drift and compensation regions <NUM>, <NUM> can be completely depleted. As commonly known, compensation regions in a superjunction transistor device, such as JFET M1 shown in <FIG> and <FIG>, make it possible to implement the drift regions with a higher doping concentration than in a conventional, non-superjunction device. This reduces the on-resistance, which is the electrical resistance in the on-state, without decreasing the voltage blocking capability.

Referring to the above, the second transistor device M2 may be implemented in various ways. Some examples for implementing the second transistor M2 are explained with reference to <FIG> below. <FIG> show a first example of the second transistor device M2, wherein <FIG> shows a vertical cross sectional view and <FIG> shows a horizontal cross sectional view of the second transistor device M2. Referring to <FIG>, the second transistor device M2 includes a source region <NUM> and a drain region <NUM> spaced apart from the source region <NUM> in the first lateral direction x. The drain region <NUM> adjoins the source region <NUM> of the first transistor device M1 in order to electrically connect the source region <NUM> of the first transistor device with the drain region <NUM> of the second transistor device M2. The drain region <NUM> of the second transistor device M2 is also referred to as second drain region in the following. The source region <NUM> of the second transistor device M2, which is also referred to as second source region <NUM> in the following, and the second drain region <NUM> are separated by a body region <NUM>. The body region <NUM> has a doping type that is complementary to the doping type of the second source region <NUM> and the second drain region <NUM>. A doping concentration of the body region <NUM> is, for example, selected from a range of between 1E16 cm-<NUM> and 1E19 cm-<NUM>, in particular from between 1E17 cm-<NUM> and 1E18 cm-<NUM>.

The second transistor device M2 may be implemented as an enhancement device (normally-off device) or a depletion (normally on-device). In a normally-off device, the body region <NUM> adjoins the gate dielectric <NUM> (and the gate electrode <NUM>, in the on-state of the second transistor device M2, generates an inversion channel in the body region <NUM> along the gate dielectric <NUM>). In a normally-on device, a channel region (not illustrated) of the first doping is arranged between the body region <NUM> and the gate dielectric <NUM> and extends from the second source region <NUM> to the second drain region <NUM> (and the gate electrode <NUM>, in the off-state of the second transistor device M2, depletes the channel region of charge carriers).

In the example shown in <FIG> the second drain region <NUM> adjoins the first source region <NUM>. This, however, is only an example. According to another example (not illustrated), the second drain region <NUM> and the first source region <NUM> are connected via a wiring arrangement located on top of the first surface <NUM> of the semiconductor body <NUM>,.

Referring to <FIG>, a gate electrode <NUM> is adjacent the body region <NUM> and dielectrically insulated from the body region <NUM> by a gate dielectric <NUM>. This gate electrode <NUM> is electrically connected to the second gate node G2. The second source region <NUM> is electrically connected to the second source node S2. According to one example, the second transistor device M2 is an n-type transistor device. In this case, the second source region <NUM> and the second drain region <NUM> is n-doped, while the body region <NUM> is p-doped. According to another example, the second transistor device M2 is a p-type transistor device. In this case, the second source region <NUM> and the second drain region <NUM> are p-doped semiconductor regions, while the body region <NUM> is an n-doped semiconductor region. The second transistor device M2 illustrated in <FIG> is an enhancement transistor device. In this transistor device, the body region <NUM> adjoins the gate dielectric <NUM>. According to another example (not illustrated), the second transistor device M2 is a depletion transistor device. In this case, there is a channel region of the same doping type as the second source region <NUM> and the second drain region <NUM> arranged between the body region <NUM> and the gate dielectric <NUM> and extends from the second source region <NUM> to the second drain region <NUM>. Referring to <FIG>, which shows a horizontal cross sectional view of the second transistor device M2, the second source region <NUM>, the second drain region <NUM>, and the body region <NUM> may be elongated in the second lateral direction y of the semiconductor body <NUM>.

Referring to <FIG>, a connection region <NUM> of the second doping type may be connected to the second source node S2 and extend through the second region <NUM> and the layer stack with the first and second layers <NUM>, <NUM>. This connection region <NUM> connects those sections of the second layers <NUM> that are arranged below the second region <NUM> to the second source region S2. Those sections of the first layers <NUM> that are arranged below the second region <NUM> are connected to the first source region <NUM> and, as the first source region <NUM> is connected to the second drain region <NUM>, to the second drain region <NUM>. Because of the fact that, below the second region <NUM>, the second layers <NUM> are connected to the second source node S2 and that the first layers <NUM> are connected to the second drain node D2 a depletion region can expand in the first and second layer sections <NUM>, <NUM> below the second region <NUM> when the second transistor device M2 is in the off-state.

<FIG> shows a modification of the transistor device shown in <FIG>. In this modification, the transistor device M2 includes a drift region <NUM> (which may also be referred to as drain extension) between the body region <NUM> and the drain region <NUM>. The drift region <NUM> has a lower doping concentration than the drain region <NUM> and the same doping type as the drain region <NUM>. A field electrode <NUM> is adjacent the drift region <NUM> and dielectrically insulated from the drift region <NUM> by a field electrode dielectric <NUM>. According to one example, the field electrode dielectric <NUM> is thicker than the gate dielectric <NUM>. As illustrated, the field electrode <NUM> may be electrically connected with the gate electrode <NUM>, for example, by forming the gate electrode <NUM> and the field electrode as one conductive layer. This is illustrated in <FIG>. According to another example (not illustrated), the field electrode <NUM> is electrically connected to the second source node S2 and electrically insulated from the gate electrode <NUM>.

<FIG> illustrates another modification of the transistor device illustrated in <FIG>. In the example illustrated in <FIG>, the gate electrode <NUM> and the gate dielectric <NUM> overlap the drift region <NUM>, but, in the first lateral direction x, do not extend to the drain region <NUM>. An insulation region <NUM> is arranged between the drift region <NUM> and those regions of the first surface <NUM> that are not covered by the gate electrode <NUM> and the gate dielectric <NUM>. This insulation region <NUM> may adjoin the drain region <NUM>, as illustrated in <FIG>. In this example, the drift region <NUM> adjoins the drain region <NUM> in a region spaced apart from the first surface <NUM>. The insulation region <NUM> may include a conventional electrically insulating material such as an oxide. The insulation region <NUM> may be implemented as a so called STI (Shallow Trench Isolation) and include a thermally grown oxide.

In the example illustrated in <FIG>, the gate electrode <NUM> is arranged on top of the first surface <NUM> of the semiconductor body. This, however, is only an example. According to another example illustrated in <FIG>, there are several gate electrodes <NUM> that are arranged in trenches extending from the first surface <NUM> into the semiconductor body <NUM>. Each of these gate electrodes, in the first lateral direction x, extends from the second source region <NUM> to the second drain region <NUM> through the body region <NUM> and is dielectrically insulated from these semiconductor regions <NUM>, <NUM>, <NUM> by a gate dielectric <NUM>. Each of these gate electrodes <NUM> is electrically connected to the second gate node G2, which is schematically illustrated in <FIG>.

Second transistor devices of the type illustrated in <FIG> and 6A to 6B can be implemented using conventional implantation and oxidation processes known from integrated CMOS (Complementary Metal Oxide Semiconductor) processes. The second transistor device may therefore also be referred to as CMOS device. The second region <NUM> may have a basic doping of the second doping type or may be intrinsic before forming the active regions (source, body and drain regions <NUM>, <NUM>, <NUM>) of the second transistor device M2 in the second region <NUM>. The basic doping concentration can be selected such that it essentially equals the doping concentration of the body region <NUM> or is lower than the doping concentration of the body region <NUM>.

In the example illustrated in <FIG>, the first and second layers <NUM>, <NUM> in the layer stack are arranged such that they are essentially parallel to the third layer <NUM> and, therefore, parallel to the first surface <NUM> of the semiconductor body <NUM>. According to another example (not illustrated), the first and second layers <NUM>, <NUM> may be arranged such that they are essentially perpendicular to the third layer <NUM>, and, therefore, perpendicular to the first surface <NUM> of the semiconductor body <NUM>.

Now referring to <FIG>, a method for forming a layer stack is schematically illustrated. The layer stack may be used for semiconductor devices as have been exemplarily explained with respect to <FIG> above. Any other kind of semiconductor device, however, may also be at least partly integrated in the layer stack.

Referring to <FIG>, a carrier <NUM> is illustrated. The carrier <NUM> may be made of a semiconductor material, for example, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. Now referring to <FIG>, a first epitaxial layer <NUM><NUM> is formed on a first surface <NUM> of the carrier <NUM>. Forming the first epitaxial layer <NUM><NUM> comprises depositing a layer of semiconductor material on the first surface <NUM> of the carrier <NUM> (see <FIG>). For example, the layer of semiconductor material may include a conventional semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. After depositing the layer of semiconductor material, a plurality of implantation regions <NUM>, <NUM> are formed in the semiconductor material. This is exemplarily illustrated in <FIG>. In the example illustrated in <FIG>, four implantation regions <NUM>, <NUM> are formed. This, however, is only an example. At least three implantation regions <NUM>, <NUM> are formed in the semiconductor material. At least two first implantation regions <NUM> of either a first type or a second type are formed at different vertical positions of the layer of semiconductor material. At least one second implantation region <NUM> is formed of a type that is complementary to the type of the first implantation regions <NUM>. For example, the first type may be an n-type implantation region and the second type may be a p-type implantation region, or vice versa.

Generally speaking, a first number N of first implantation regions <NUM>, and a second number M of second implantation regions <NUM> is formed in the layer of semiconductor material. The first number may either equal the second number (N = M), or the first number may be different from the second number (e.g., N = M ± <NUM>). As the first and second implantation regions <NUM>, <NUM> are arranged alternatingly in the epitaxial layer <NUM><NUM>, a difference between the first number N and the second number M is generally not more than <NUM>.

Each second implantation region <NUM> is generally arranged between two first implantation regions <NUM> and vice versa, with the exception of implantation regions <NUM>, <NUM> that are arranged adjacent to the horizontal surfaces (top and bottom surfaces) of the first epitaxial layer <NUM><NUM>. That is, the first and second implantation regions <NUM>, <NUM> are arranged alternatingly in the layer of semiconductor material. In the example illustrated in <FIG>, one first implantation region <NUM> is arranged at a first distance d<NUM> from a top surface of the layer of semiconductor material. A top surface of the layer of semiconductor material is a surface facing away from the carrier <NUM>. A second implantation region <NUM> is arranged at a second distance d<NUM> from the top surface of the layer of semiconductor material. The second distance d<NUM> is less than the first distance d<NUM>. Another first implantation region <NUM> is arranged at a third distance d<NUM> from the top surface of the layer of semiconductor material, wherein the third distance d<NUM> is less than the first distance d<NUM> and the second distance d<NUM>. Another second implantation region <NUM> is arranged at a fourth distance d<NUM> from the top surface of the layer of semiconductor material, wherein the fourth distance d<NUM> is less than the first, second and third distances d<NUM>, d<NUM>, d<NUM>.

The distance dn between an implantation region <NUM>, <NUM> and the top surface generally depends on the implantation energy that is used to form the implantation region <NUM>, <NUM>. For example, the implantation energies for forming the first implantation regions <NUM> may be chosen from a range of between 200keV and 5000keV. A different implantation energy is used for each of the first implantation regions <NUM> of the same epitaxial layer <NUM><NUM>. For example, an implantation energy of 1000keV may be used to form the lowermost first implantation region <NUM> at the first distance d<NUM> from the top surface and an implantation energy of 230keV may be used to form another first implantation region <NUM> at the third distance d<NUM> from the top surface. The lowermost second implantation region <NUM>, for example, may be formed at the second distance d<NUM> from the top surface using an implantation energy of 1200keV, and another second implantation region <NUM> may be formed at the fourth distance d<NUM> by using an implantation energy of 270keV. This, however, is only an example. The implantation energies given above may apply if the semiconductor body <NUM> comprises Si as semiconductor material, for example. Any other suitable implantation energies may be used to form the first and second implantation regions <NUM>, <NUM> at different vertical positions. For example, if other semiconductor materials than Si are used to form the semiconductor body <NUM>, other implantation energies may be suitable. Generally speaking, using higher implantation energies results in implantation regions that are arranged further away from the top surface than implantation regions that are formed with lower implantation energies.

The distance dn between an implantation region <NUM>, <NUM> and the top surface, however, may further depend on the material that is used to form the implantation regions <NUM>, <NUM>. For example, implanting boron with an implantation energy of 1000keV may result in an implantation region that is arranged further away from the top surface than an implantation region that is formed by implanting phosphor at an implantation energy of 1200keV. Using boron or phosphor for forming the implantation regions <NUM>, <NUM>, however, is only an example. Any other suitable materials may be used. Generally, ions of a first type are used to form the first implantation regions <NUM>, and ions of a second type are used to form the second implantation regions <NUM>.

The implantation dose that is used to form different first implantation regions <NUM> may be identical. It is, however, also possible to use different implantation doses for forming different first implantation regions <NUM>. The implantation dose that is used to form different second implantation regions <NUM> may be identical. It is, however, also possible to use different implantation doses for forming different second implantation regions <NUM>. The implantation dose that is used for forming the first implantation regions <NUM> may be the same or may differ from the implantation dose that is used to form the second implantation regions <NUM>. According to one example, if the semiconductor body <NUM> comprises Si, a first dose that is used to form the first implantation regions <NUM> is chosen from a range of between <NUM>. 0E12cm-<NUM> and <NUM>. 0E12cm-<NUM>. A second dose that is used to form the second implantation regions <NUM> may be chosen from a range of between <NUM>. 0E12cm-<NUM> and <NUM>. 0E12cm-<NUM>. Other implantation doses may be used, if the semiconductor body <NUM> comprises another semiconductor material than Si.

Now referring to <FIG>, a second epitaxial layer <NUM><NUM> is formed on the top surface of the first epitaxial layer <NUM><NUM>. A height h<NUM> of the second epitaxial layer <NUM><NUM> may, e.g., equal a height h<NUM> of the first epitaxial layer <NUM><NUM>. The second epitaxial layer <NUM><NUM> may be formed of the same material and in the same way as the first epitaxial layer <NUM><NUM>. That is, a second layer of semiconductor material is formed on the first epitaxial layer <NUM><NUM>. In a further step, first and second implantation regions <NUM>, <NUM> are formed in the second layer of semiconductor material. This is schematically illustrated in <FIG>. The first and second implantation regions <NUM>, <NUM> in the second epitaxial layer <NUM><NUM> may be formed in the same way as the first and second implantation regions <NUM>, <NUM> in the first epitaxial layer <NUM><NUM> (see <FIG>). In particular, corresponding implantation regions <NUM>, <NUM> in the first and second epitaxial layers <NUM><NUM>, <NUM><NUM> may be formed using the same type of ions, the same implantation dose and the same implantation energy. In this way, after forming the implantation regions <NUM>, <NUM> in the second epitaxial layer <NUM><NUM>, the first and the second epitaxial layers <NUM><NUM>, <NUM><NUM> with the implantation regions <NUM>, <NUM> formed therein are essentially identical.

In the same way, further epitaxial layers <NUM>n may be formed. This, however, is not specifically illustrated in the Figures. Any suitable number n of epitaxial layers <NUM>n may be formed on the carrier <NUM>, with n ≥ <NUM>.

After depositing two or more layers of semiconductor material and forming first and second implantation regions <NUM>, <NUM> therein, the arrangement is heated (not specifically illustrated). By heating the first and second implantation regions <NUM>, <NUM>, the implanted ions are diffused, thereby forming first and second layers <NUM>, <NUM>. Such diffusing processes are generally known and will, therefore, not be described in further detail herein.

Now referring to the example illustrated in <FIG>, two epitaxial layers <NUM><NUM>, <NUM><NUM> are formed on the carrier <NUM>. In the example illustrated in <FIG>, each epitaxial layer 140n comprises two first layers <NUM> and two second layers <NUM>. The first and second layers <NUM>, <NUM> are arranged alternatingly, forming a layer stack. Being arranged alternatingly, the first and second layers <NUM>, <NUM> form a plurality of pn-couples (pn-junctions) in the layer stack.

A third layer <NUM> may be formed on a top surface of the layer stack (top surface of the top most epitaxial layer <NUM>n). A top surface of the layer stack is a surface facing away from the carrier <NUM>. The third layer <NUM> may comprise monocrystalline semiconductor material. According to one example, the third layer <NUM> includes monocrystalline silicon (Si). After forming the layer stack and the third layer <NUM>, a first semiconductor component may be formed. The first semiconductor component may be at least partially integrated in the layer stack. Referring to <FIG>, forming the first semiconductor component may comprise forming a first semiconductor region <NUM> in the layer stack adjoining the plurality of first layers <NUM>, and forming at least one second semiconductor region <NUM> in the layer stack, each of the at least one second semiconductor regions <NUM> adjoining at least one of the plurality of second layers <NUM>. Each of the at least one second semiconductor region <NUM> is spaced apart from the first semiconductor region <NUM> in a horizontal direction x. The first semiconductor component may comprise a diode, for example, the first semiconductor region <NUM> forming an anode of the diode and the at least one second semiconductor region <NUM> forming a cathode of the diode, or vice versa. This, however, is only an example.

According to another example, the first semiconductor component may comprise a transistor, as has been described with respect to <FIG> above. In this case, a third semiconductor region <NUM> may be formed in the layer stack, as is exemplarily illustrated in <FIG>. The first, second and third semiconductor regions <NUM>, <NUM>, <NUM> may correspond to the first source region <NUM>, the first drain region <NUM>, and the plurality of gate regions <NUM> of the examples illustrated in <FIG> above. Optionally, first, second and third connection electrodes <NUM>, <NUM>, <NUM> may be formed extending along a complete length of the respective semiconductor region <NUM>, <NUM>, <NUM> in the vertical direction z, as has already been described above.

In the examples illustrated in <FIG> and <FIG>, each epitaxial layer <NUM>n comprises two first implantation regions <NUM>/first layers <NUM> and two second implantation regions <NUM>/second layers <NUM>. This, however, is only an example. As is exemplarily illustrated in <FIG>, it is also possible that one epitaxial layer <NUM><NUM> comprises two first layers <NUM> and one second layer <NUM>, and another epitaxial layer <NUM><NUM> comprises one first layer <NUM> and two second layers <NUM>. Each epitaxial layer 140n comprises at least three first and second layers <NUM>, <NUM> in total. Any other number greater than three is also possible (not illustrated). An epitaxial layer <NUM>n generally may comprise an uneven number of first and second layers <NUM>, <NUM> (N + M uneven) or an even number of first and second layers <NUM>, <NUM> (N + M even). According to another example, each epitaxial layer 140n comprises three first layers <NUM> and three second layers <NUM>, or four first layers <NUM> and four second layers <NUM>, for example.

Now referring to <FIG>, the distribution of ions in the different first and second layers <NUM>, <NUM> after diffusion of the ions is exemplarily illustrated. In the example of <FIG>, the first layers <NUM> comprise phosphorous, while the second layers <NUM> comprise boron. The distribution of boron in the exemplary epitaxial layer <NUM> is illustrated in a bold line. As can be seen, the concentration of the respective ions reaches a maximum in the different layers <NUM>, <NUM>. That is, the concentration of phosphorous reaches a maximum in the first layers <NUM>, and the concentration of boron reaches a maximum in the second layers <NUM>. The concentration of phosphorous, however, is not necessarily zero in the second layers <NUM> and the concentration of boron is not necessarily zero in the first layers <NUM>. However, the concentration of phosphorous exceeds the concentration of boron in the first layers <NUM>, and the concentration of boron exceeds the concentration of phosphorous in the second layers <NUM>. That is, in the first layers <NUM>, the number of electrons exceeds the number of holes, and in the second layers <NUM>, the number of holes exceeds the number of electrons. Using boron and phosphorous is only an example. Any other suitable ions may be used instead.

Still referring to <FIG>, the distribution of ions within different first layers <NUM><NUM>, <NUM><NUM> of the same epitaxial layer <NUM> may not be identical. For example, the maximum of the doping concentration of phosphorous in one of the first layers <NUM><NUM> may be greater than the maximum of the doping concentration of phosphorous in another one of the first layers <NUM><NUM>. Even further, the distribution of the ions within different first layers <NUM><NUM>, <NUM><NUM> differs. This results in different thicknesses x1n of different first layers <NUM><NUM>, <NUM><NUM>. One first layer <NUM><NUM> has a first thickness x<NUM> that is smaller than a second thickness x<NUM> of another one of the first layers <NUM><NUM>. The thickness of a layer may be determined by the type of implanting ions, the implantation energy and the implantation dose that is used to form the layer. The same applies for the second layers <NUM><NUM>, <NUM><NUM> within the same epitaxial layer <NUM>. Further, the distribution of ions within a single layer <NUM>, <NUM> may be asymmetrical. That is, the maximum of the doping concentration is not necessarily in the center of the respective layer <NUM>, <NUM> in the vertical direction z.

Different epitaxial layers <NUM>, however, may have an identical structure. That is, a second epitaxial layer <NUM><NUM> that is formed on a first epitaxial layer <NUM> as illustrated in <FIG>, may have identical first and second layers <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM> with identical maxima of the doping concentrations, identical ion distributions and identical thicknesses x as compared to the epitaxial layer <NUM> illustrated in <FIG>.

In this way, a repetitive pattern may be formed within the layer stack. This is exemplarily illustrated in <FIG>. In the example of <FIG>, two epitaxial layers <NUM>n are exemplarily illustrated. Any other number of epitaxial layers <NUM>n ><NUM>, however, is also possible. Each epitaxial layer <NUM>n comprises two first layers <NUM><NUM>, <NUM><NUM> and two second layers <NUM><NUM>, <NUM><NUM>. The lowermost first layer <NUM><NUM> in each of the epitaxial layers <NUM>n has a greater thickness in the vertical direction z than the second one of the first layers <NUM><NUM> that is arranged closer to the third layer <NUM>. The same applies for the second layers <NUM><NUM>, <NUM><NUM>. That is, the pattern of decreasing thicknesses (towards the top of the layer stack) of the first and second layers <NUM>, <NUM> is repeated within each epitaxial layer <NUM>n.

In the example illustrated in <FIG>, a first and a second semiconductor component M1, M2 are formed similar to the examples illustrated with respect to <FIG> above. Arranging a first semiconductor component M1 in a first region <NUM> of the third semiconductor layer <NUM>, and a second semiconductor component M2 in a second region <NUM> of the third semiconductor layer <NUM>, however, is only an example. As is illustrated in <FIG>, it is, for example, also possible to arrange both the first semiconductor device M1 and the second semiconductor device in the same region of the third semiconductor layer <NUM>, i.e., in the first region <NUM> of the third semiconductor layer <NUM>.

In the examples illustrated in <FIG> above, the layer stack is arranged directly adjacent to the third semiconductor layer <NUM>. This, however, is only an example. As is schematically illustrated in <FIG>, additional layers may be arranged between the third semiconductor layer <NUM> and the layer stack. The additional layers may form at least a first pn-couple (pn-junction) <NUM><NUM> and a second pn-couple <NUM><NUM>. Such additional pn-couples <NUM><NUM>, <NUM><NUM> may form an upper edge of the layer stack.

In the examples of <FIG>, the carrier <NUM> includes a single layer. This, however, is only an example. According to another example, as is illustrated in <FIG>, the carrier <NUM> may comprise a plurality of layers. The plurality of layers may form at least a third and a fourth pn-couples (pn-junction) <NUM><NUM>, <NUM><NUM>. The third and fourth pn-couples <NUM><NUM>, <NUM><NUM> may form a lower edge of the layer stack. The additional pn-couples <NUM>, however, are not part of the layer stack and are not a part of the repetitive pattern of first and second layers <NUM>, <NUM>.

The additional layers forming the additional pn-couples (<NUM>) may be formed using a different implantation dose as compared to the first and second layers <NUM>, <NUM> forming the layer stack.

Referring to the examples illustrated herein before, the first layers <NUM> having the first doping type may adjoin the second layers <NUM> having the second doping type. Towards any interface between a first layer <NUM> and a second layer <NUM>, the doping concentration in the first layer <NUM> decreases towards an intrinsic level, and in the second layer <NUM>, the doping concentration decreases towards the intrinsic level. Thus, inevitably, there is a (narrow) region with an intrinsic doping level between each of the first layers <NUM> and an adjacent second layer <NUM>. According to another example (not illustrated), there may be an intrinsic layer between each of the first layers <NUM> and the adjacent second layer <NUM>. "Intrinsic" in this context means that the doping concentration is either lower than 1E11 cm-<NUM> or lower than <NUM>% or even lower than <NUM>% of a maximum doping concentration of each of the first and second layers <NUM>, <NUM>. A width of these intrinsic layers may be wider than necessary to simply separate the first layers <NUM> from the second layers <NUM>. According to one example, a width of each of these intrinsic layers is between <NUM> % and <NUM> % of a width of a first and second layer <NUM>, <NUM>. The "width" of each of the first and second layers <NUM>, <NUM> in this example may be defined by a shortest distance between the two intrinsic layers bordering the respective first or second layer <NUM>, <NUM>.

As has been described above, the semiconductor body <NUM> with the first and second semiconductor layers <NUM>, <NUM> and the third semiconductor layer <NUM> are arranged on a carrier <NUM>. This carrier <NUM> may be implemented in various ways. Some examples of how the carrier <NUM> may be implemented are explained in the following.

<FIG> illustrates a first example of the carrier <NUM>. In this example, the carrier <NUM> is made of a semiconductor material. According to one example, the semiconductor material of the carrier <NUM> is the same semiconductor material as the semiconductor material of the semiconductor body <NUM> arranged on top of the carrier <NUM>.

In the example illustrated in <FIG>, the first drain region <NUM> and the first source region <NUM>, in the semiconductor body <NUM>, extend down to the carrier <NUM>. In order to avoid a short-circuit between the first drain region <NUM> and the first source region <NUM> in the carrier <NUM>, the carrier <NUM> includes a p-n junction between the first drain region <NUM> and the first source region <NUM>. This p-n junction is formed between a first carrier region <NUM> of the second doping type and a second carrier region <NUM> of the first doping type. The first carrier region <NUM> adjoins the first source region <NUM>, and the second carrier region <NUM> adjoins the first drain region <NUM>. Referring to <FIG>, the second carrier region <NUM>, in the first lateral direction x, may extend along an interface between the carrier <NUM> and the semiconductor body <NUM> to the gate regions <NUM> (from which only one is shown in <FIG>) or beyond the gate regions <NUM>. This, however, is only an example. According to another example (illustrated in <FIG>) the second carrier region <NUM> may end spaced apart from the gate regions <NUM>. According to one example, the second carrier region <NUM> is implemented such that a dimension of the second carrier region <NUM> in the vertical direction z decreases as a distance from the first drain region <NUM> increases. In the example illustrated in <FIG>, the vertical dimension of the second carrier region <NUM> linearly decreases as the distance from the first drain region <NUM> increases. This, however, is only an example. According to another example, the vertical dimension of the second carrier region <NUM> decreases non-linearly as the distance from the drain region <NUM> increases.

<FIG> illustrates a carrier <NUM> according to another example. In this example, the carrier <NUM> includes an insulation layer <NUM> that adjoins the semiconductor body <NUM> and an optional semiconductor substrate <NUM> (illustrated in dashed lines) on which the insulation layer <NUM> is arranged. The substrate <NUM> can be omitted so that the carrier <NUM> may only consist of the insulation layer <NUM>. As in the example illustrated in <FIG>, each of the first source regions <NUM>, the first drain region <NUM> and the gate regions <NUM> extends down to the carrier <NUM> in the semiconductor body <NUM>. In the example shown in <FIG>, the insulation layer <NUM> provides for an insulation between the first source regions <NUM> and the first drain region <NUM> in the carrier <NUM>.

<FIG> illustrates another example of the carrier <NUM>. The carrier <NUM> illustrated in <FIG> includes features from both the example illustrated in <FIG> and the example illustrated in <FIG>. More specifically, the carrier <NUM> includes the first carrier region <NUM> and the second carrier region <NUM> explained with reference to <FIG>. Additionally, the insulation layer <NUM> is arranged between the first carrier region <NUM> and the semiconductor body <NUM>.

<FIG> illustrates a modification of the carrier <NUM> illustrated in <FIG>. In the example illustrated in <FIG>, a semiconductor layer <NUM> of the second doping type is arranged between the insulation layer <NUM> and the layer stack with the first and second semiconductor regions <NUM>, <NUM>. The first source regions <NUM>, the gate regions <NUM>, and the first drain region <NUM> may extend through this layer <NUM> of the carrier <NUM> down to the insulation layer <NUM>. Optionally, semiconductor regions <NUM> are arranged in the layer <NUM>. These semiconductor regions <NUM> have the first doping type and may adjoin the insulation layer <NUM>. Each of these regions <NUM> is connected to at least one of the first source regions <NUM> and the first drain region <NUM>.

Referring to <FIG>, the first transistor device M1 may be implemented as a drain-down transistor. In this case, the carrier <NUM> includes a drain region extension region <NUM> at a first surface <NUM> of the carrier <NUM>. The first surface <NUM> of the carrier <NUM> faces away from the first surface <NUM> of the semiconductor body <NUM>. The drain extension region <NUM> further includes a connection region of the first doping type that connects the drain extension region <NUM> to the first drain region <NUM>. In the example illustrated in <FIG>, the carrier <NUM> further includes a first carrier region <NUM>, and a second carrier region <NUM> as explained herein before. This, however, is only an example. Other topologies of the carrier may be used as well.

<FIG> illustrates a modification of the transistor arrangement illustrated in <FIG>. In this example, the second source region <NUM> can be contacted via the first surface <NUM> of the carrier <NUM>. In this example, the carrier <NUM> includes a source extension region <NUM> along the first surface <NUM> of the carrier <NUM>. Further, the source extension region <NUM> adjoins a contact region <NUM> of the first doping type. This contact region <NUM> extends through the layer stack with the first and second semiconductor layers <NUM>, <NUM> down to the carrier <NUM>. Further, this contact region <NUM> is connected to the source region of the second transistor device M2. This second transistor device M2 is only schematically illustrated in <FIG>. How the contact region <NUM> may be connected to the second source region <NUM> is illustrated in <FIG> in which the contact region <NUM> is illustrated in dashed lines.

Claim 1:
A method comprising:
forming a layer stack with a plurality of first layers (<NUM>) of a first doping type and a plurality of second layers (<NUM>) of a second doping type complementary to the first doping type on top of a carrier (<NUM>), wherein
the first layers (<NUM>) and the second layers (<NUM>) are arranged alternatingly within the layer stack,
forming the layer stack comprises forming a plurality of epitaxial layers (<NUM>n) on the carrier (<NUM>),
forming each of the plurality of epitaxial layers (<NUM>n) comprises depositing a layer of semiconductor material, forming at least two first implantation regions (<NUM>) of one of said first doping type or said second doping type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region (<NUM>) of the doping type that is complementary to the doping type of the first implantation regions, wherein the first implantation regions (<NUM>) and the second implantation regions (<NUM>) are arranged alternatingly, wherein
forming implantation regions of the first doping type comprises implanting ions of the first doping type,
forming implantation regions of the second doping type comprises implanting ions of the second doping type; and
heating the epitaxial layers (<NUM>n) with the implantation regions (<NUM>, <NUM>) formed therein, thereby diffusing the implanted ions and the first implantation regions forming the first layers (<NUM>) and the second implantation regions forming the second layers (<NUM>), wherein
if two or more of the first layers (<NUM>) are formed within the same epitaxial layer (140n), the different first layers (<NUM>) within the respective epitaxial layer (140n) have different thicknesses (x<NUM>, x<NUM>), the thickness decreasing towards the top of the layer stack;
if two or more of the second layers (<NUM>) are formed within the same epitaxial layer (140n), the different second layers (<NUM>) within the respective epitaxial layer (140n) have different thicknesses (x<NUM>, x<NUM>), the thickness decreasing towards the top of the layer stack; and
the doping type of the topmost implantation region (<NUM>, <NUM>) of an epitaxial layer (<NUM>n) differs from the doping type of a directly adjoining lowermost implantation region (<NUM>, <NUM>) of a subsequent epitaxial layer (140n).