Patent Description:
Document <NPL> proposes a Symmetric Modified Multilevel Ladder (SMML) converter for directly converting down from Li-ion battery voltage ranges to System on Chip (SoC) compatible voltage ranges while using low-voltage power Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) in the power stage. Cascode buck converters with multiple stacked MOSFETs for both a low-side and a high-side switches are used. Flying capacitors are provided between MOSFETs of the low-side and the high-side switches. Patent <CIT> discloses digital-to-analog converter using switched-capacitor cells comprising inverter based structures.

An inverter-based digital-to-analog conversion cell in a DAC suffers from parasitic resistances and capacitances. The linearity of DACs suffers from these parasitic resistances and capacitances. In particular at high operating frequencies, the effects of the parasitic capacitances are no longer negligible.

Hence, there may be a desire for improved inverter circuitry.

When two elements A and B are combined using an "or", this is to be understood as disclosing all possible combinations, i.e. only A, only B as well as A and B, unless expressly defined otherwise in the individual case.

<FIG> illustrates a first example of an inverter circuit <NUM>. The inverter circuit <NUM> comprises a first node <NUM> for coupling to (receiving) a first electrical potential (e.g. a positive supply voltage VDD). Further, the inverter circuit <NUM> comprises a second node <NUM> for coupling to (receiving) a second electrical potential (e.g. a negative supply voltage VSS or ground) different from the first electrical potential. The inverter circuit <NUM> additionally comprises a third node <NUM> coupled between the first node <NUM> and the second node <NUM>. The third node <NUM> is configured to output an output signal of the inverter circuit <NUM>.

The inverter circuit <NUM> comprises two transistors <NUM>-<NUM> and <NUM>-<NUM> of a first conductivity type. In the example of <FIG>, the transistors <NUM>-<NUM> and <NUM>-<NUM> are p-type (p-channel) transistors. However, it is to be noted that the transistors <NUM>-<NUM> and <NUM>-<NUM> may be n-type (n-channel) transistors in other examples. The transistors <NUM>-<NUM> and <NUM>-<NUM> are coupled in series between the first node <NUM> and the third node <NUM>. In the example, of <FIG>, two transistors <NUM>-<NUM> and <NUM>-<NUM> are illustrated. However, it is to be noted that the present disclosure is not limited thereto. In general, any number N ≥ <NUM> of transistors of the first conductivity type may be coupled in series between the first node <NUM> and the third node <NUM> (N being an integer). In more general terms, a plurality of transistors of the first conductivity type is coupled in series between the first node <NUM> and the third node <NUM>.

The inverter circuit <NUM> comprises two transistors <NUM>-<NUM> and <NUM>-<NUM> of a second conductivity type, which is different from the first conductivity type. In the example of <FIG>, the transistors <NUM>-<NUM> and <NUM>-<NUM> are n-type (n-channel) transistors as the transistors <NUM>-<NUM> and <NUM>-<NUM> are p-type transistors. However, it is to be noted that the transistors <NUM>-<NUM> and <NUM>-<NUM> may be p-type (p-channel) transistors in other examples in which the transistors <NUM>-<NUM> and <NUM>-<NUM> are n-type transistors. The transistors <NUM>-<NUM> and <NUM>-<NUM> are coupled in series between the third node <NUM> and the second node <NUM>. In the example, of <FIG>, two transistors <NUM>-<NUM> and <NUM>-<NUM> are illustrated. However, it is to be noted that the present disclosure is not limited thereto. In general, any number M ≥ <NUM> of transistors of the second conductivity type may be coupled in series between the third node <NUM> and the second node <NUM> (M being an integer which may be equal to or be different from N). In more general terms, a plurality of transistors of the second conductivity type is coupled in series between the third node <NUM> and the second node <NUM>.

The inverter circuit <NUM> additionally comprises a fourth node <NUM> configured to receive an input signal <NUM> which is a digital signal such as a digital oscillation/control/activation signal) that is to be inverted. The fourth node <NUM> is coupled to a gate (control) terminal of the transistor <NUM>-<NUM> of the first conductivity type and a gate (control) terminal of the transistor <NUM>-<NUM> of the second conductivity type. However, it is to be noted that the present disclosure is not limited thereto. In other examples, the fourth node <NUM> may alternatively be coupled to a gate terminal of the transistor <NUM>-<NUM> of the first conductivity type and a gate terminal of the transistor <NUM>-<NUM> of the second conductivity type. In more general terms, the fourth node is coupled to a gate terminal of one of the plurality of transistors of the first conductivity type and a gate terminal of one of the plurality of transistors of the second conductivity type.

A gate terminal of the of the transistor <NUM>-<NUM> of the first conductivity type is configured to receive a fixed electrical potential <NUM>-<NUM> to (e.g. selectively) keep the transistor <NUM>-<NUM> in a conductive state (e.g. a bias voltage signal or an enable signal). Similarly, a gate terminal of the transistor <NUM>-<NUM> of the second conductivity type is configured to receive a fixed electrical potential <NUM>-<NUM> to (e.g. selectively) keep the transistor <NUM>-<NUM> in a conductive state (e.g. a bias voltage signal or an enable signal). The gate terminals of the of the transistors <NUM>-<NUM> and <NUM>-<NUM> may be coupled to a respective node configured to receive the respective fixed electrical potential. In more general terms, the gate terminals of the other transistors of the plurality of transistors of the first conductivity type and the plurality of transistors of the second conductivity type (i.e. the transistors other than the one transistor of the plurality of transistors of the first conductivity type and the one transistor of the plurality of transistors of the second conductivity type that are coupled to the fourth node <NUM>) are configured to receive a respective fixed electrical potential.

The transistors <NUM>-<NUM> and <NUM>-<NUM> are serially coupled pull-up transistors that allow to selectively couple the third node <NUM> to the first electrical potential based on the input signal <NUM>. Analogously, the transistors <NUM>-<NUM> and <NUM>-<NUM> are serially coupled pull-down transistors that allow to selectively couple the third node <NUM> to the second electrical potential based on the input signal <NUM>. Accordingly, the output signal of the inverter circuit at the third node <NUM> is inverted with respect to the input signal <NUM>.

The cascode formed by the transistors <NUM>-<NUM> and <NUM>-<NUM> suffers from parasitic capacitances. These parasitic capacitances are indicated by the parasitic capacitor <NUM>-<NUM> coupled to a node A between the transistors <NUM>-<NUM> and <NUM>-<NUM>. Similarly, the cascode formed by the transistors <NUM>-<NUM> and <NUM>-<NUM> suffers from parasitic capacitances. These parasitic capacitances are indicated by the parasitic capacitor <NUM>-<NUM> coupled to a node B between the transistors <NUM>-<NUM> and <NUM>-<NUM>.

While the parasitic capacitances at the nodes A and B may be negligible (tolerable) in case a frequency of the input signal <NUM> is low (e.g. below <NUM>), the parasitic capacitances cause additional harmonic distortions in the output signal of the inverter circuit <NUM> for higher frequencies.

The charging and discharging behaviour of the parasitic capacitance at nodes A and B affects the linearity of the inverter circuit <NUM>. Assuming that the transistor <NUM>-<NUM> is fully off (i.e. in a non-conducting state) and that the gate voltage at the transistors <NUM>-<NUM> is at VDD (i.e. the input signal <NUM> indicates a digital one), the parasitic capacitor <NUM>-<NUM> at the node A is discharged. Once the input signal <NUM> changes to VIN,L (i.e. the input signal <NUM> indicates a digital zero), the transistor <NUM>-<NUM> switches to the conductive state and the current flowing from the transistor <NUM>-<NUM> into the node A splits into two branches during a certain time interval. In particular, a part of the current is flowing to the other transistors <NUM>-<NUM> while another part of the current is flowing to the parasitic capacitor <NUM>-<NUM> at the node A until the parasitic capacitor <NUM>-<NUM> is fully charged. If the frequency of the input signal <NUM> is low enough that the time to charge and discharge the parasitic capacitor <NUM>-<NUM> is negligible compared to the switching period of the input signal <NUM>, the linearity of the inverter circuit <NUM> is hardly affected. However, if the frequency of the input signal <NUM> is so high that the time to charge and discharge the parasitic capacitor <NUM>-<NUM> is not negligible compared to the switching period of the input signal <NUM>, the linearity of the inverter circuit <NUM> is decreased.

In order to support the charging and discharging of the parasitic capacitances, the inverter circuit <NUM> additionally comprises a coupling path <NUM> comprising a capacitive element <NUM> (e.g. a single capacitor or a plurality of coupled capacitors). The coupling path <NUM> is coupled to the nodes A and B such that the coupling path <NUM> is coupled to a source terminal of the transistor <NUM>-<NUM> and a source terminal of the transistor <NUM>-<NUM>.

The charge state of the coupling path <NUM>, in particular the capacitive element <NUM>, changes dynamically with the input signal <NUM>. The current (charges) flowing into the capacitive element <NUM> support the charging and discharging of the parasitic capacitances (indicated by the parasitic capacitors <NUM>-<NUM> and <NUM>-<NUM>) such that the on- and off-switching of the transistors <NUM>-<NUM> and <NUM>-<NUM> is no longer influenced by the parasitic capacitances. Accordingly, a linearity of the inverter circuit <NUM> may be increased compared to conventional inverter circuitry - in particular if the frequency of the input signal <NUM> is above <NUM>.

In other words, a capacitor is added between the switch and the cascode device of each of the pull-up network and the pull-down network by means of the coupling path in order to charge and discharge the parasitic capacitances.

For example, a capacitance of the capacitive element <NUM> may be equal to or greater than a gate-source capacitance Cgs of any of the plurality of transistors of the first conductivity type. Similarly, the capacitance of the capacitive element <NUM> may be equal to or greater than a gate-source capacitance Cgs of any of the plurality of transistors of the second conductivity type. The capacitance of the capacitive element may, e.g., be at least three times and at maximum five times the gate-source capacitance Cgs of any of the plurality of transistors of the first conductivity type and/or any of the plurality of transistors of the second conductivity type. Accordingly to examples, the capacitance of the capacitive element <NUM> may, e.g., be four times the gate-source capacitance Cgs of any of the plurality of transistors of the first conductivity type and/or any of the plurality of transistors of the second conductivity type.

In the example of <FIG>, the inverter circuit <NUM> is shown as part of a digital-to-analog conversion cell <NUM>. However, it is to be noted that inverter circuits according to the present disclosure are not limited to being used in digital-to-analog conversion cells. In general, the inverter circuits according to the present disclosure may be used for any application that requires signal inversion.

In addition to the inverter circuit <NUM>, the digital-to-analog conversion cell <NUM> comprises a cell output node <NUM> configured to provide an analog output signal <NUM> of the digital-to-analog conversion cell <NUM>. A load <NUM> is coupled between the inverter circuit <NUM> and the cell output node <NUM>. The load <NUM> receives the output signal of the inverter circuit <NUM> and generates the analog output signal <NUM> based thereon. In the example of <FIG>, the load <NUM> is combination of a resistive element <NUM> (e.g. a single resistor or a plurality of coupled resistors) and a capacitive element <NUM> (e.g. a single capacitor or a plurality of coupled capacitors). However, the present disclosure is not limited thereto. In general, the load <NUM> may be one of a resistive element, a capacitive element, an impedance element (e.g. capacitor, resistor, inductor or combination thereof), or a combination thereof.

The digital-to-analog conversion cell <NUM> may comprise additional circuitry not illustrated in <FIG>. For example, the digital-to-analog conversion cell <NUM> may comprise an input node configured to receive the input signal <NUM> and logic circuitry coupled between the input node of the digital-to-analog conversion cell <NUM> and the inverter circuit <NUM>. The logic circuitry may be configured to selectively supply the input signal <NUM> to the inverter circuit <NUM> based on one or more control (activation) signals of a control circuit of a DAC comprising the digital-to-analog conversion cell <NUM>.

In the example of <FIG>, one coupling path <NUM> is illustrated. However, it is to be noted that the present disclosure is not limited thereto. In other examples, a plurality of coupling paths (i.e. two or more coupling paths) each comprising a respective capacitive element may be provided. The plurality of coupling paths may be coupled between the source terminals of different transistor pairs, each of the different transistor pairs being formed by one of the plurality of transistors of the first conductivity type and one of the plurality of transistors of the second conductivity type.

In more general terms, an inverter circuit according to the present disclosure comprises at least one coupling path comprising a respective capacitive element, wherein the at least one coupling path is coupled between a source terminal of one of the plurality of transistors of the first conductivity type and a source terminal of one of the plurality of transistors of the second conductivity type.

Further exemplary inverter circuits comprising more than one coupling path will be described in the following with respect to <FIG>.

<FIG> illustrates a second example of a digital-to-analog conversion cell <NUM>. The digital-to-analog conversion cell <NUM> is identical to the digital-to-analog conversion cell <NUM> described above except for the implementation of the inverter circuit. Therefore, only the differences between the inverter circuit <NUM> illustrated in <FIG> and the above described inverter circuit <NUM> will be described in the following.

While the inverter circuit <NUM> comprises two transistors <NUM>-<NUM> and <NUM>-<NUM> of the first conductivity type coupled in series and two transistors <NUM>-<NUM> and <NUM>-<NUM> of the second conductivity type coupled in series, the inverter circuit <NUM> comprises three transistors <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of the first conductivity type coupled in series and three transistors <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of the second conductivity type coupled in series.

The gate terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> are coupled to the fourth node <NUM> similar to what is described above. The gate terminals of the transistors <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> are configured to receive a respective fixed electrical potential <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> similar to what is described above.

The higher numbers of transistors of the first and second conductivity type allows to increase the potential difference between the first node <NUM> and the second node <NUM>.

Further, the inverter circuit <NUM> comprises two coupling paths <NUM> and <NUM> instead of only one. The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes A and B such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes A and B (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes C and D such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes C and D (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). The two coupling paths <NUM> and <NUM> allow to support charging and discharging of the parasitic capacitances present in the inverter circuit <NUM> in order to increase the linearity of the inverter circuit <NUM>.

<FIG> illustrates a third example of a digital-to-analog conversion cell <NUM>. The digital-to-analog conversion cell <NUM> is identical to the digital-to-analog conversion cell <NUM> described above except for the implementation of the inverter circuit. Therefore, only the differences between the inverter circuit <NUM> illustrated in <FIG> and the above described inverter circuit <NUM> will be described in the following.

While the inverter circuit <NUM> comprises three transistors <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of the first conductivity type coupled in series and three transistors <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> of the second conductivity type coupled in series, the inverter circuit <NUM> comprises N transistors <NUM>-<NUM>, <NUM>-<NUM>,. <NUM>-N coupled in series and M transistors <NUM>-<NUM>, <NUM>-<NUM>,. <NUM>-M coupled in series. As described above, any number N of transistors of the first conductivity type and any number M of transistors of the second conductivity type may be coupled in series, respectively. For example, the numbers N and M may be selected based on the (e.g. desired, target) potential difference between the first node <NUM> and the second node <NUM>. Similar to what is described above, M may be identical to or be different from N.

<FIG> illustrates a fourth example of a digital-to-analog conversion cell <NUM>. The digital-to-analog conversion cell <NUM> is identical to the digital-to-analog conversion cell <NUM> described above except for the implementation of the inverter circuit. Therefore, only the differences between the inverter circuit <NUM> illustrated in <FIG> and the above described inverter circuit <NUM> will be described in the following.

In the inverter circuit <NUM>, the coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes A and B and the coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes C and D. In difference thereto, the coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes B and C in the inverter circuit <NUM> such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes B and C (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). Further, the coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes A and D in the inverter circuit <NUM> such its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes A and D (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>).

<FIG> illustrates a fifth example of a digital-to-analog conversion cell <NUM>. The digital-to-analog conversion cell <NUM> is identical to the digital-to-analog conversion cell <NUM> described above except for the implementation of the inverter circuit. Therefore, only the differences between the inverter circuit <NUM> illustrated in <FIG> and the above described inverter circuit <NUM> will be described in the following.

While the inverter circuit <NUM> comprises two coupling paths <NUM> and <NUM>, the inverter circuit <NUM> comprises four coupling paths <NUM>, <NUM>, <NUM> and <NUM>.

The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes B and C such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes B and C (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes A and B such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes A and B (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes A and D such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes A and D (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>). The coupling path <NUM> is coupled to the source terminals of the transistors <NUM>-<NUM> and <NUM>-<NUM> at the nodes C and D such that its capacitive element <NUM> supports charging and discharging of the parasitic capacitances at the nodes C and D (illustrated by the parasitic capacitances <NUM>-<NUM> and <NUM>-<NUM>).

It is apparent from the exemplary inverter circuits <NUM>, <NUM>, <NUM> and <NUM> described above that an inverter circuit according to present disclosure may comprises a plurality of coupling paths each comprising a respective capacitive element, wherein the plurality of coupling paths are coupled between the source terminals of different transistor pairs. Each of the different transistor pairs is formed by one of the plurality of transistors of the first conductivity type and one of the plurality of transistors of the second conductivity type. The coupling paths allow to support charging and discharging of the parasitic capacitances present in the inverter circuit in order to increase the linearity of the inverter circuit.

<FIG> illustrates an example of a DAC <NUM> that uses digital-to-analog conversion cells according to the present disclosure.

The DAC <NUM> comprises a plurality of digital-to-analog conversion cells <NUM> (i.e. two or more digital-to-analog conversion cells). At least part of the plurality of digital-to-analog conversion cells <NUM> are implemented according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG>. The number of digital-to-analog conversion cells may, e.g., be based on a (desired, target) resolution of the DAC <NUM>.

The output nodes of the plurality of digital-to-analog conversion cells <NUM> are coupled to a converter output node <NUM> of the DAC. The converter output node <NUM> is configured to provide an analog output signal <NUM> of the DAC based on the analog output signal of the plurality of digital-to-analog conversion cells <NUM>. For example, the analog output signal of the plurality of digital-to-analog conversion cells <NUM> may be combined (e.g. summed) at the converter output node <NUM>.

Further, the DAC <NUM> comprises a control circuit <NUM> configured to selectively activate one or more of the plurality of digital-to-analog conversion cells <NUM> based on a digital input signal <NUM> received by the DAC <NUM>. For example, the control circuit <NUM> may selectively supply one or more control (activation) signals to the plurality of digital-to-analog conversion cells <NUM> for selectively activating one or more of the plurality of digital-to-analog conversion cells <NUM> based on the digital input signal <NUM>.

Further, the control circuit <NUM> or any other circuitry of the DAC <NUM> may be configured to supply an (e.g. digital) control (activation) signal to the plurality of digital-to-analog conversion cells <NUM>. For example, if the one or more control signals supplied to a respective one of the plurality of digital-to-analog conversion cells <NUM> indicate the respective digital-to-analog conversion cell is activated, respective logic circuitry of the digital-to-analog conversion cell may supply (forward) the control (activation)signal as input signal to the inverter circuit of the digital-to-analog conversion cell such that the control (activation)signal is inverted and drives the load of the digital-to-analog conversion cell for generating the analog output signal of the activated digital-to-analog conversion cell.

The plurality of digital-to-analog conversion cells <NUM> as well as the DAC <NUM> may optionally comprise further circuitry - conventional or custom.

Although a plurality of digital-to-analog conversion cells <NUM> is illustrated in <FIG>, it is to be noted that in other examples, the DAC <NUM> may comprise only one digital-to-analog conversion cell according to the present disclosure such that the control circuit <NUM> may selectively activate the one digital-to-analog conversion cell based on the digital input signal <NUM>. Accordingly, a DAC with a one bit resolution may be obtained.

Using at least one digital-to-analog conversion cell according to the present disclosure for the DAC <NUM> may allow to increase a linearity of the DAC <NUM> compared to conventional architectures. This is further illustrated in <FIG> which shows a comparison of the SFDR of a DAC using conventional inverters without additional coupling paths and a DAC according to the present disclosure using at least one additional coupling path in the inverter circuit.

The curve <NUM> illustrates the course of the SFDR for the DAC according to the present disclosure over a normalized frequency range. As a reference, the curve <NUM> illustrates the course of the SFDR for the conventional DAC over the normalized frequency range.

As can be seen from <FIG>, the SFDR (which is a measure for the linearity of a DAC) improves by up to <NUM> dB. In particular, the SFDR for the DAC according to the present disclosure is significantly improved compared to the SFDR for the conventional DAC for higher frequencies of the input signal.

Further, <FIG> illustrate exemplary output spectra that show another beneficial effect of the at least one additional coupling path in the inverter. <FIG> illustrates the output spectrum over a normalized frequency range of a DAC using conventional inverters without additional coupling path. <FIG> illustrates the output spectrum over the normalized frequency range of a DAC according to the present disclosure using at least one additional coupling path in the inverter circuit. The input signal is the same for both DACs and varies from a few hundreds of MHz to <NUM>. A power of the third harmonics <NUM> in the output spectrum of the DAC according to the present disclosure is significantly reduced compared to a power of the third harmonics <NUM> in the output spectrum of the conventional DAC. Also the fifth harmonics are significantly reduced. While the fifth harmonics <NUM> are clearly visible in the output spectrum of the conventional DAC, the fifth harmonics cannot be distinguished from the fundamental noise in the output spectrum of the DAC according to the present disclosure.

The proposed inverter circuit may allow to improve linearity beyond what is practically feasible because part of the charge is no longer lost to charging/discharging the parasitic capacitances when the input signal changes.

An example of an implementation using digital-to-analog conversion according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a radio base station <NUM> (e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising a DAC <NUM> as proposed.

A transmitter <NUM> comprises the DAC <NUM>. Additionally, the transmitter <NUM> comprises digital circuitry <NUM>. The DAC <NUM> is coupled to the digital circuitry <NUM>. The digital circuitry <NUM> is configured to output a digital signal which is converted to an analog signal by the DAC <NUM>. In other words, the analog output signal of the DAC <NUM> is based on the digital signal. The analog output signal of the DAC <NUM> may, e.g., be an analog Radio Frequency (RF) signal. For example, data to be wirelessly transmitted may be encoded in the digital signal.

The base station <NUM> comprises at least one antenna element <NUM> coupled to the transmitter <NUM> for radiating an RF transmit signal to the environment. The RF transmit signal may be equal to the analog output signal of the DAC <NUM> or be based on the analog output signal of the DAC <NUM>. For example, the transmitter <NUM> may be coupled to the antenna element <NUM> via one or more intermediate elements such as a filter, an up-converter (mixer) or a power amplifier.

Additionally, the base station <NUM> comprises a receiver <NUM> configured to receive a RF receive signal from the antenna element <NUM> or another antenna element (not illustrated) of the base station <NUM>.

To this end, a base station with improved digital-to-analog conversion may be provided.

The base station <NUM> may comprise further elements such as, e.g., an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit CPU cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I<NUM>C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/ MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the baseband processor may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using digital-to-analog conversion according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a mobile device <NUM> (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising a DAC <NUM> as proposed.

A transmitter <NUM> comprises the DAC <NUM>. Additionally, the transmitter <NUM> comprises digital circuitry <NUM>. The DAC <NUM> is coupled to the digital circuitry <NUM>. The digital circuitry <NUM> is configured to output a digital signal which is converted to an analog signal by the DAC <NUM>. In other words, the analog output signal of the DAC <NUM> is based on the digital signal. The analog output signal of the DAC <NUM> may, e.g., be an analog RF signal. For example, data to be wirelessly transmitted may be encoded in the digital signal.

The mobile device <NUM> comprises at least one antenna element <NUM> coupled to the transmitter <NUM> for radiating an RF transmit signal to the environment. The RF transmit signal may be equal to the analog output signal of the DAC <NUM> or be based on the analog output signal of the DAC <NUM>. For example, the transmitter <NUM> may be coupled to the antenna element <NUM> via one or more intermediate elements such as a filter, an up-converter (mixer) or a power amplifier.

Additionally, the mobile device <NUM> comprises a receiver <NUM> configured to receive a RF receive signal from the antenna element <NUM> or another antenna element (not illustrated) of the mobile device <NUM>.

To this end, a mobile device with improved digital-to-analog conversion may be provided.

The mobile device <NUM> may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I<NUM>C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

Claim 1:
An inverter circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a first node (<NUM>) for coupling to a first electrical potential;
a second node (<NUM>) for coupling to a second electrical potential different from the first electrical potential;
a third node (<NUM>) configured to output an output signal of the inverter circuit;
a plurality of transistors of a first conductivity type (<NUM>-<NUM>, ..., <NUM>-N) coupled in series between the first node (<NUM>) and the third node (<NUM>);
a plurality of transistors of a second conductivity type (<NUM>-<NUM>, ..., <NUM>-M) coupled in series between the third node and the second node, the second conductivity type being different from the first conductivity type;
a fourth node (<NUM>) configured to receive an input signal (<NUM>) to be inverted, wherein the input signal (<NUM>) is a digital signal, wherein the fourth node (<NUM>) is coupled to a gate terminal of one of the plurality of transistors of the first conductivity type (<NUM>-<NUM>, ..., <NUM>-N) and a gate terminal of one of the plurality of transistors of the second conductivity type (<NUM>-<NUM>, ..., <NUM>-M), and wherein the gate terminals of the other transistors of the plurality of transistors of the first conductivity type (<NUM>-<NUM>, ..., <NUM>-N) and the plurality of transistors of the second conductivity type (<NUM>-<NUM>, ..., <NUM>-M) are configured to receive a respective fixed electrical potential; and
wherein a source terminal of the one of the plurality of transistors of the first conductivity type is coupled to the first node (<NUM>) and a source terminal of the one of the plurality of transistors of the second conductivity type is coupled to the second node (<NUM>); and
characterized by
at least one coupling path (<NUM>, ..., <NUM>) comprising a capacitive element (<NUM>, ..., <NUM>), wherein the at least one coupling path (<NUM>, ..., <NUM>) is coupled between a source terminal of one of the other transistors of the plurality of transistors of the first conductivity type (<NUM>-<NUM>, ..., <NUM>-N) and a source terminal of one of the other transistors of the plurality of transistors of the second conductivity type (<NUM>-<NUM>, ..., <NUM>-M).