Patent Description:
Conventional bootstrappers used to linearize the input signal switch in an Analog-to-Digital Converter (ADC) load the buffer preceding the ADC. The capacitance seen at the input of the bootstrapper may be as big or even larger than the sample capacitance itself.

When turning on the switch, a large current spike is needed. Further, the buffer and the connection between the buffer and the ADC must be designed accordingly. In a differential system, the buffer voltage is a common mode voltage +/- the AC part of the input signal. Unless the common mode voltage is 0V, the buffer has to deliver a non-differential current to charge to the wanted voltage. The voltage at the ADC input must settle within the sampling period. The current spike in combination with the more or less inductive signal distribution limits the settling speed.

Document <CIT> proposes a bootstrap switch circuit with over-voltage prevention. The bootstrap switch circuit comprises bootstrap circuitry for switching a switch of the bootstrap switch circuit on and off. The bootstrap circuitry comprises a first capacitor which is charged before the switch is turned on. The bootstrap circuitry comprises a second capacitor injecting charge into the gate of the switch while the switch is turned on.

Document <CIT> proposes a constant impedance sampling switch. The circuitry comprises switch is implemented by a transistor which is bootstrapped. The circuitry further comprises a capacitor which is charged before the switch is turned on. The circuitry comprises a second capacitor injecting charge into the gate of the switch while the switch is turned on.

There may be a desire for improved bootstrapping.

A bootstrapping circuit for a semiconductor switch and a corresponding method of operating a bootstrapping circuit for a semiconductor switch are defined in independent claims <NUM> and <NUM>.

When two elements A and B are combined using an "or", this is to be understood as disclosing all possible combinations, i.e. only A, only B as well as A and B, unless expressly defined otherwise in the individual case.

<FIG> illustrates an example of a bootstrapping circuit <NUM> for a semiconductor switch <NUM>.

The bootstrapping circuit <NUM> comprises a first node <NUM> for coupling to an input node <NUM> of the semiconductor switch <NUM>. An input signal <NUM> to be sampled by the semiconductor switch <NUM> is received by the bootstrapping circuit <NUM> at the first node <NUM>. Similarly, the semiconductor switch <NUM> receives the input signal <NUM> at the input node <NUM>. The input signal <NUM> may, e.g., be an analog Radio Frequency (RF) signal.

The bootstrapping circuit <NUM> further comprises a second node <NUM> for coupling to a control node <NUM> of the semiconductor switch <NUM>. The switching operation of the semiconductor switch <NUM> (i.e. the opening and closing of the semiconductor switch <NUM>) is controlled by the input to the control node <NUM>. For example, the control node <NUM> may be a gate node or be coupled to one or more gate nodes of the semiconductor switch <NUM>.

The bootstrapping circuit <NUM> additionally comprises a capacitor <NUM>.

Further, the bootstrapping circuit <NUM> comprises a switch circuit configured to selectively couple the capacitor <NUM> to a charge source <NUM> while the semiconductor switch <NUM> is open (i.e. in a non-conductive state), i.e. while the semiconductor switch <NUM> is kept open by the bootstrapping circuit <NUM>. In the example of <FIG>, the switch circuit of the bootstrapping circuit <NUM> comprises switches <NUM> and <NUM> for coupling the capacitor <NUM> to the charge source <NUM>. As illustrated in <FIG>, the charge source <NUM> may comprise a third node <NUM> configured to receive a first voltage supply signal (e.g. a positive supply voltage VDD) and a fourth node <NUM> configured to receive a second voltage supply signal (e.g. a negative supply voltage Vss or ground). However, it is to be noted that charge source <NUM> may also be implemented different. Accordingly, the switch <NUM> selectively couples the capacitor <NUM> to the third node <NUM> and the switch <NUM> selectively couples the capacitor <NUM> to the fourth node <NUM> such that the capacitor <NUM> is charged by the potential difference between the nodes <NUM> and <NUM> while the semiconductor switch <NUM> is open. In other words, the capacitor <NUM> is pre-charged while the semiconductor switch <NUM> is open.

The switch circuit is further configured to selectively close a conductive path <NUM> between the first node <NUM> and the second node <NUM> for closing the semiconductor switch <NUM>. The conductive path <NUM> includes the capacitor <NUM>. In the example of <FIG>, the switch circuit of the bootstrapping circuit <NUM> comprises switches <NUM> and <NUM> for selectively closing the conductive path <NUM>. The switch <NUM> is coupled between the capacitor <NUM> and the first node <NUM>. The switch <NUM> is coupled between the capacitor <NUM> and the second node <NUM>. When the switches <NUM> and <NUM> are closed, the conductive path <NUM> along the capacitor <NUM> is closed such that the voltage at the second node <NUM> is equal to the sum of the voltage of the input signal <NUM> and the voltage generated by the pre-charged capacitor <NUM>.

When turning on the semiconductor switch <NUM> by closing the switches <NUM> and <NUM>, a (large) current spike is needed to charge the parasitic capacitances of the bootstrapping circuit <NUM>. The current spike is conventionally drawn from preceding circuitry that supplies the input signal <NUM> to the first node <NUM> of the bootstrapping circuit <NUM> and the input node <NUM> of the semiconductor switch <NUM>. As a consequence, the preceding circuitry and the signal line(s) connecting the preceding circuitry with the bootstrapping circuit <NUM> and the semiconductor switch <NUM> should be designed accordingly. The preceding circuitry may, e.g., be a buffer. For example, in a differential system, the buffer voltage may be some common mode voltage +/- the AC part of the input signal <NUM>. Unless the common mode voltage is 0V, the buffer has to deliver a non-differential current to charge to the wanted voltage.

Further, the voltage at the input node <NUM> of the semiconductor switch <NUM> (i.e. the input signal <NUM>) needs to settle within a sampling period of the semiconductor switch <NUM>. Accordingly, the drawn current spike in combination with an, e.g., more or less inductive signal distribution may limit the settling speed and, hence, the sampling speed of the semiconductor switch <NUM>.

In order to reduce the current drawn from the preceding circuitry, the bootstrapping circuit <NUM> comprises charge injection circuitry <NUM>. The charge injection circuitry <NUM> is configured to inject additional charge into the conductive path <NUM> before, while or after the conductive path <NUM> is closed by the switch circuit. In other words, the charge injection circuitry <NUM> injects further charge into the conductive path <NUM> in addition to the charge already stored in the pre-charged capacitor <NUM>. The additional charge injected by the charge injection circuitry <NUM> allows to charge the parasitic capacitances of the bootstrapping circuit <NUM> such that less current needs to be drawn from the preceding circuitry (e.g. a buffer).

Accordingly, the voltage at the input node <NUM> of the semiconductor switch <NUM> (i.e. the input signal <NUM>) can settle faster such that the sampling speed of the semiconductor switch <NUM> may be increased compared to conventional approaches. Further, the specifications for the preceding circuitry and the signal line(s) connecting the preceding circuitry with the bootstrapping circuit <NUM> and semiconductor switch <NUM> may be more relaxed as the drawn current is lower. For example, the achieved decrease of drawn current may allow to reduce the current capability of a preceding buffer as well as its power supply.

In other words, an aspect of the present disclosure is to reduce the current drawn from the preceding circuitry such as a buffer (i.e. the current that flows through the switch <NUM>) by injecting charge. For example, the charge may be injected like a "pre-charging" when the semiconductor switch <NUM> is closing or just before the semiconductor switch <NUM> is closing, or after the semiconductor switch <NUM> is closing. The semiconductor switch <NUM> outputs a sampled signal <NUM>.

Although <FIG> illustrates that the charge injection circuitry <NUM> is configured to inject charge into the conductive path <NUM> at a node between the capacitor <NUM> and the switch <NUM>, it is to be noted that the charge injection circuitry <NUM> according to the claimed invention is configured to inject charge into the conductive path <NUM> at the node <NUM>.

The switch circuit by means of the switches <NUM> and <NUM> is further configured to decouple the capacitor <NUM> from the charge source <NUM> before the conductive path <NUM> is closed by the switch circuit (here the switches <NUM> and <NUM>).

The switch circuit by means of the switches <NUM> and <NUM> is further configured to decouple the capacitor <NUM> from the first node <NUM> and the second node <NUM> while the capacitor is coupled to the charge source <NUM> by the switch circuit (here the switches <NUM> and <NUM>).

The switch circuit is further configured to selectively couple the second node <NUM> to a fifth node <NUM> for opening the semiconductor switch <NUM> and keeping the semiconductor switch <NUM> open (i.e. in a non-conductive state). The fifth node <NUM> is configured to receive a reference voltage signal (e.g. the negative supply voltage Vss or ground). In the example of <FIG>, the switch circuit of the bootstrapping circuit <NUM> comprises a switch <NUM> for selectively coupling the second node <NUM> to the fifth node <NUM>. The switch circuit by means of the switch <NUM> is further configured to decouple the second node <NUM> from the fifth node <NUM> when/while closing the semiconductor switch <NUM>.

The switches <NUM>,. , <NUM> of the switch circuit may be implemented as semiconductor switches (e.g. Metal-Oxide-Semiconductor, MOS, switches). The opening and closing of the switches <NUM>,. , <NUM> is controlled by means of a respective control signal <NUM>-<NUM>,. , <NUM>-<NUM>. The control signals <NUM>-<NUM>,. , <NUM>-<NUM> may be provided by control circuitry for controlling the sampling operation of the semiconductor switch <NUM>.

The charge injection circuitry <NUM> may be implemented in various ways. In the following, three exemplary implementations will be described with reference to <FIG>. However, it is to be noted that the present disclosure is not limited thereto. Also other implementations of the charge injection circuitry <NUM> may in general be used.

<FIG> illustrates exemplary charge injection circuitry <NUM>. The charge injection circuitry <NUM> comprises a node <NUM> configured to receive the first voltage supply signal (e.g. the positive supply voltage VDD).

Additionally, the charge injection circuitry <NUM> comprises a pulse generator <NUM> configured to selectively generate a pulse <NUM> based on a control signal <NUM>. The charge injection circuitry <NUM> comprises a switch <NUM> configured to selectively couple the sixth node <NUM> with the conductive path <NUM> upon reception of the pulse <NUM>. In the example of <FIG>, the switch <NUM> is implemented by a transistor. In general, the switch <NUM> may be any type of switch, e.g., a semiconductor switch. The switch <NUM> couples the sixth node <NUM> to the conductive path <NUM> for the duration (length) of the pulse <NUM>. Accordingly, a (e.g. short) current pulse is injected into the conductive path <NUM> for charging the parasitic capacitances in the conductive path <NUM>. The duration (length) of the pulse <NUM> may be selected based on the, e.g., estimated parasitic capacitances in the bootstrapping circuit <NUM>.

The control signal <NUM> may be identical to or be derived from another control signal received by the switch circuit of the bootstrapping circuit <NUM> for controlling the selective closure of the conductive path <NUM>. For example, the control signal <NUM> may be identical to or be derived from the control signal <NUM>-<NUM> for the switch <NUM>.

In other words, the pulse generator <NUM> is used to close the switch from the conductive path <NUM> to the first voltage supply signal for a short time so that the voltage in the conductive path <NUM> is quickly charged to a voltage which is close to, e.g., the common mode voltage of the circuitry preceding the bootstrapping circuit <NUM> (e.g. a buffer). The pulse generator <NUM> connected to the (e.g. an NMOS or PMOS) switch <NUM> may allow to implement a current pulse for (e.g. pre-) charging the capacitor <NUM> of the bootstrapping circuit <NUM>.

The first voltage supply signal may be provided by a local power supply. Using the local power supply may be advantageous in that the current loop is reduced since local decoupling capacitors (e.g. only a couple µm away) may deliver the current instead of circuitry preceding the bootstrapping circuit <NUM> (e.g. a buffer), which may be about <NUM> distant.

<FIG> illustrates another exemplary charge injection circuitry <NUM> which uses a current source <NUM> instead of the voltage source. The current source <NUM> is configured to generate a current signal. Similarly to what is described above for the pulse generator <NUM>, the pulse generator <NUM> of the charge injection circuitry <NUM> is configured to selectively generate a pulse <NUM> based on a control signal <NUM>. The control signal <NUM> may be identical to or be derived from another control signal received by the switch circuit of the bootstrapping circuit <NUM> for controlling the selective closure of the conductive path <NUM> (e.g. the control signal <NUM>-<NUM> for the switch <NUM>).

A switch <NUM> of the charge injection circuitry <NUM> is configured to selectively couple the current source <NUM> with the conductive path <NUM> upon reception of the pulse <NUM>. In the example of <FIG>, the switch <NUM> is implemented by a transistor. In general, the switch <NUM> may be any type of switch, e.g., a semiconductor switch. The switch <NUM> couples the current source <NUM> to the conductive path <NUM> for the duration (length) of the pulse <NUM>. Accordingly, a (e.g. short) current pulse is injected into the conductive path <NUM> for charging the parasitic capacitances in the conductive path <NUM>.

Another exemplary charge injection circuitry <NUM> based on a switched capacitor is illustrated in <FIG>. The charge injection circuitry <NUM> comprises a buffer capacitor <NUM> and switches <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. The switches <NUM> and <NUM> allow to couple the buffer capacitor <NUM> to nodes <NUM> and <NUM> that receive the first voltage supply signal. The switches <NUM> and <NUM> allow to couple the buffer capacitor <NUM> to nodes <NUM> and <NUM> that receive the second voltage supply signal. The switch <NUM> allows to couple the buffer capacitor <NUM> to the conductive path <NUM>.

Further, the charge injection circuitry <NUM> comprises a control circuit <NUM> configured to control the switches <NUM>, <NUM>, <NUM>, <NUM> and <NUM> by means of the signals Φ1,. In particular, the control circuit <NUM> configured to control, based on a control signal <NUM>, the switches <NUM>, <NUM>, <NUM>, <NUM> to selectively couple the buffer capacitor <NUM> to or more of the nodes <NUM>,. <NUM> for charging the buffer capacitor <NUM>. The control circuit <NUM> controls the switch <NUM> to selectively decouple the buffer capacitor <NUM> from the conductive path <NUM> while charging the buffer capacitor <NUM>.

The control circuit <NUM> is further configured to control, based on the control signal <NUM>, the switch <NUM> to selectively couple the buffer capacitor <NUM> to the conductive path <NUM>. The control circuit <NUM> controls the switches <NUM>, <NUM>, <NUM>, <NUM> to selectively decouple the buffer capacitor <NUM> from the nodes <NUM>,. <NUM> while the buffer capacitor <NUM> is coupled to the conductive path <NUM>.

The control signal <NUM> may be identical to or be derived from another control signal received by the switch circuit of the bootstrapping circuit <NUM> for controlling the selective closure of the conductive path <NUM> (e.g. the control signal <NUM>-<NUM> for the switch <NUM>).

In other examples, the charge injection circuitry <NUM> may comprise more than the one buffer capacitor <NUM> illustrated in <FIG>. Further, the charge injection circuitry <NUM> may comprise more or less switches than in illustrated in <FIG> for selectively coupling the one or more buffer capacitors to nodes receiving a respective one of the first voltage supply signal and the second voltage supply signal. Similarly, the charge injection circuitry <NUM> may comprise more switches for selectively coupling the one or more buffer capacitors to the coupling path.

The charge injection circuitry <NUM> is flexible and can deliver charge in both directions, which may be beneficial if one wants to push charge into and out of the conductive path <NUM>.

In general, the switching circuitry <NUM> may comprise one or more buffer capacitors and a plurality of switches. The control circuit <NUM> may, in general, be configured to control, based on the control signal <NUM>, the plurality of switches to selectively couple one or more of the one or more buffer capacitors to nodes configured to receive a respective one of the first voltage supply signal and the second voltage supply signal for charging one or more of the one or more buffer capacitors. The control circuit <NUM> may, in general, further be configured to control, based on the control signal <NUM>, the plurality of switches to selectively couple one or more of the one or more buffer capacitors to the conductive path <NUM>.

<FIG> illustrates an example of a sampling apparatus <NUM> that uses a bootstrapping circuit according to the present disclosure.

The sampling apparatus <NUM> comprises an input node <NUM> configured to receive an input signal <NUM> from a buffer <NUM>. Further, the sampling apparatus <NUM> comprises a sampling capacitor <NUM>.

A semiconductor switch <NUM> of the sampling apparatus <NUM> is coupled between the input node <NUM> and the sampling capacitor <NUM>. The semiconductor switch <NUM> is configured to selectively couple the sampling capacitor <NUM> to the input node <NUM> for sampling the input signal <NUM>. In particular, an input node <NUM> of the semiconductor switch <NUM> is coupled to the input node <NUM> of the sampling apparatus <NUM> for receiving the input signal <NUM>. Further, an output node <NUM> of the sampling switch <NUM> is coupled to the sampling capacitor <NUM>.

The operation of the semiconductor switch <NUM> is controlled by a bootstrapping circuit <NUM> according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG>. The first node <NUM> of the bootstrapping circuit <NUM> is coupled to the input node <NUM> of the sampling apparatus <NUM> and the input node <NUM> of the semiconductor switch <NUM> such that the bootstrapping circuit <NUM> receives the input signal <NUM>. The second node <NUM> of the bootstrapping circuit <NUM> is coupled to a control node <NUM> of the semiconductor switch <NUM>.

By selectively closing the coupling path within the bootstrapping circuit <NUM> as described above, the semiconductor switch <NUM> may be selectively closed by the bootstrapping circuit <NUM> in order to sample the input signal <NUM>. Similar to what is described above, the additional charge injected by the charge injection circuitry of the bootstrapping circuit <NUM> may allow to charge the parasitic capacitances of the bootstrapping circuit <NUM> such that a smaller current peak is drawn from the buffer <NUM>. Accordingly, the input signal <NUM> may settle faster at the input node <NUM> of the semiconductor switch <NUM> such that the sampling speed of the semiconductor switch <NUM> may be increased compared to conventional approaches. Further, the specifications for the buffer <NUM> and the signal line(s) connecting the buffer <NUM> with the bootstrapping circuit <NUM> and the semiconductor switch <NUM> may be more relaxed as the drawn current is lower. For example, the achieved decrease of drawn current may allow to reduce the current capability of the buffer <NUM> as well as its power supply.

The sampling apparatus <NUM> may, e.g., be an ADC that is configured to generate a digital output signal based on a charge state of the sampling capacitor <NUM> according to generally known techniques.

<FIG> illustrates another sampling apparatus <NUM> which is a slightly modified compared to the above described sampling apparatus <NUM>. In the sampling apparatus <NUM>, a bootstrapping circuit <NUM> is used instead of the bootstrapping circuit <NUM>. The bootstrapping circuit <NUM> differs from the bootstrapping circuit <NUM> in that the charging injection circuitry <NUM> is removed from the bootstrapping circuit <NUM> as the charging injection circuitry <NUM> is coupled to the output node <NUM> of the semiconductor switch <NUM>. In the example of <FIG>, the charge injection circuitry <NUM> is configured to inject charge into the output node <NUM> of the semiconductor switch <NUM> before, while or after the conductive path <NUM> is selectively closed by the switch circuit of the bootstrapping circuit <NUM>.

Injecting the additional charge into the output node <NUM> of the semiconductor switch <NUM> is an alternative to injecting the additional charge into the conductive path <NUM> itself. Once the bootstrapping circuit <NUM> closes the semiconductor switch <NUM>, the additional charge at the output node <NUM> of the semiconductor switch <NUM> can be drawn into the bootstrapping circuit <NUM> for charging the parasitic capacitances of the bootstrapping circuit <NUM>.

Therefore, the sampling apparatus <NUM> may provide the same technical advantages as the above described sampling apparatus <NUM>. Also the sampling apparatus <NUM> may, e.g., be an ADC that is configured to generate a digital output signal based on a charge state of the sampling capacitor <NUM> according to generally known techniques.

<FIG> illustrates a comparison of a voltages and currents at the input node of a conventional bootstrapper and a bootstrapping circuit according to the present disclosure.

The curve <NUM> represents the temporal course of the voltage at the input node of the conventional bootstrapper while the semiconductor switch is closed by the bootstrapper. The curve <NUM> represents the temporal course of the voltage at the input node of the bootstrapping circuit according to the present disclosure (i.e. the first node <NUM>) while the semiconductor switch is closed by the bootstrapping circuit.

The curve <NUM> represents the temporal course of the current at the input node of the bootstrapper while the semiconductor switch is closed by the bootstrapper. The curve <NUM> represents the temporal course of the current at the input node of the bootstrapping circuit according to the present disclosure (i.e. the first node <NUM>) while the semiconductor switch is closed by the bootstrapping circuit.

As can be seen from curves <NUM> and <NUM>, the voltage variation is smaller for the bootstrapping circuit according to the present disclosure compared to the conventional bootstrapper.

Similarly, as can be seen from curves <NUM> and <NUM>, the current variation is smaller for the bootstrapping circuit according to the present disclosure compared to the conventional bootstrapper. Therefore, less current is drawn from preceding circuitry providing the input signal for the bootstrapping circuit and the semiconductor switch. Further, as can be seen from curves <NUM> and <NUM>, the settling time is smaller for the bootstrapping circuit according to the present disclosure compared to the conventional bootstrapper. Accordingly, the semiconductor switch may be turned on faster.

An example of an implementation using bootstrapping according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a radio base station <NUM> (e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising a sampling apparatus <NUM> as proposed.

A receiver <NUM> of the base station <NUM> comprises the sampling apparatus <NUM>. The receiver <NUM> additionally comprises analog circuitry <NUM> configured to receive an RF receive signal from at least one antenna element <NUM> of the base station <NUM>. The analog circuitry <NUM> is further configured to supply the input signal to the input node of the sampling apparatus <NUM> based on the RF receive signal. The sampling apparatus <NUM> samples the input signal. The sampling apparatus <NUM> may, e.g., be an ADC configured to generate a digital output signal based on a charge state of the sampling capacitor of the sampling apparatus <NUM>. For example, the analog circuitry <NUM> may be an analog RF front-end and comprising one or more of a Low-Noise Amplifier (LNA), a filter, a down-conversion mixer, ElectroStatic Discharge (ESD) protection circuitry, an attenuator etc. The analog circuitry <NUM> may additionally or alternatively comprise an input buffer coupled to the input node of the sampling apparatus <NUM>. The input buffer may be configured to supply the input signal to the input node of the sampling apparatus <NUM>.

Further, the base station <NUM> comprises a transmitter <NUM> configured to generate an RF transmit signal. The transmitter <NUM> may use the antenna element <NUM> or another antenna element (not illustrated) of the base station <NUM> for radiating the RF transmit signal to the environment.

To this end, a base station with improved sampling capabilities may be provided may be provided.

The base station <NUM> may comprise further elements such as, e.g., an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit CPU cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I<NUM>C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/ MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the baseband processor may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using bootstrapping according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a mobile device <NUM> (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising a sampling apparatus <NUM> as proposed.

A receiver <NUM> of the mobile device <NUM> comprises the sampling apparatus <NUM>. The receiver <NUM> additionally comprises analog circuitry <NUM> configured to receive an RF receive signal from at least one antenna element <NUM> of the mobile device <NUM>. The analog circuitry <NUM> is further configured to supply the input signal to the input node of the sampling apparatus <NUM> based on the RF receive signal. The sampling apparatus <NUM> samples the input signal. The sampling apparatus <NUM> may, e.g., be an ADC configured to generate a digital output signal based on a charge state of the sampling capacitor of the sampling apparatus <NUM>. For example, the analog circuitry <NUM> may be an analog RF front-end and comprising one or more of a LNA, a filter, a down-conversion mixer, ESD protection circuitry, an attenuator etc. The analog circuitry <NUM> may additionally or alternatively comprise an input buffer coupled to the input node of the sampling apparatus <NUM>. The input buffer may be configured to supply the input signal to the input node of the sampling apparatus <NUM>.

Further, the mobile device <NUM> comprises a transmitter <NUM> configured to generate an RF transmit signal. The transmitter <NUM> may use the antenna element <NUM> or another antenna element (not illustrated) of the mobile device <NUM> for radiating the RF transmit signal to the environment.

To this end, a mobile device with improved sampling capabilities may be provided.

The mobile device <NUM> may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I<NUM>C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The wireless communication circuits using bootstrapping according to the proposed architecture or one or more of the examples described above may be configured to operate according to one of the 3rd Generation Partnership Project (3GPP)-standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a <NUM>th Generation New Radio (<NUM> NR), a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM), an Enhanced Data rates for GSM Evolution (EDGE) network, or a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuits may be configured to operate according to mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WIMAX) network IEEE <NUM> or Wireless Local Area Network (WLAN) IEEE <NUM>, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc..

For further illustrating the bootstrapping described above, <FIG> illustrates a flowchart of method <NUM> of operating a bootstrapping circuit for a semiconductor switch. The bootstrapping circuit comprises a capacitor, a first node for coupling to an input node of the semiconductor switch and a second node for coupling to a control node of the semiconductor switch. The method <NUM> comprises selectively coupling <NUM> the capacitor to a charge source by a switch circuit of the bootstrapping circuit while the semiconductor switch is open. Further, the method <NUM> comprises selectively closing <NUM> a conductive path between the first node and the second node by the switch circuit for closing the semiconductor switch. The conductive path includes the capacitor. Additionally, the method <NUM> comprises injecting <NUM> charge into the conductive path by charge injection circuitry of the bootstrapping circuit before, while or after the conductive path is closed by the switch circuit. The method <NUM> may allow to charge the parasitic capacitances of the bootstrapping circuit by means of the additional charge injected by the charge injection circuitry such that a smaller current peak is drawn from circuitry preceding the bootstrapping circuit and the semiconductor switch.

More details and aspects of the method <NUM> are explained in connection with the proposed technique or one or more examples described above (e.g. <FIG>). The method <NUM> may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

Claim 1:
A bootstrapping circuit (<NUM>) for a semiconductor switch (<NUM>), the bootstrapping circuit (<NUM>) comprising:
a capacitor (<NUM>);
a first node (<NUM>) for coupling to an input node (<NUM>) of the semiconductor switch (<NUM>);
a second node (<NUM>) for coupling to a control node (<NUM>) of the semiconductor switch (<NUM>);
a switch circuit configured to selectively couple the capacitor (<NUM>) to a charge source (<NUM>, <NUM>, <NUM>, <NUM>) while the semiconductor switch (<NUM>) is open and to selectively close a conductive path (<NUM>) between the first node (<NUM>) and the second node (<NUM>) for closing the semiconductor switch (<NUM>), wherein the conductive path (<NUM>) includes the capacitor (<NUM>), wherein the switch circuit is further configured to decouple the capacitor (<NUM>) from the first node (<NUM>) and the second node (<NUM>) while the capacitor (<NUM>) is coupled to the charge source (<NUM>, <NUM>, <NUM>, <NUM>) by the switch circuit, and wherein the switch circuit is further configured to selectively couple the second node (<NUM>) to a third node (<NUM>) for opening the semiconductor switch (<NUM>), wherein the third node (<NUM>) is configured to receive a reference voltage signal; and
charge injection circuitry (<NUM>) configured to inject charge into the conductive path (<NUM>) at the first node (<NUM>) before, while or after the conductive path (<NUM>) is closed by the switch circuit.