Patent Description:
The present disclosure relates to the field of display techniques, and particularly, to an array substrate and a method for manufacturing the same, and a display device.

For a full-screen display device or an intelligent wearable display device having an irregular shape (e.g., circular, round-cornered, U-shaped, etc.), it is required that an edge of a display region also has a non-rectangular irregular shape, so as to meet diversified requirements of users on an appearance of a display device.

<CIT> discloses a liquid crystal display device. The liquid crystal display device having a non-rectangular display panel includes an active area which is defined by a peripheral shield layer. A plurality of pixels are formed in the active area in a matrix, and each pixel includes a plurality of sub-pixels to display colors different from each other. A part of the sub-pixels of peripheral pixels located in a peripheral region of the active area is covered with a peripheral shield layer. Shield elements are arranged in the sub-pixels which are not covered with the peripheral shield layer so that an effective display area of each of the sub-pixels of the peripheral pixel is substantially equal.

<CIT> (A1) discloses a color image display device. The color image display device is capable of displaying an image with no differences in color balance between end portions and inner portions of anon-rectangle image display region. The color image display device includes an end portion unit pixel formed in an edge portion of a display region in which a color image is displayed and including end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship and an inner unit pixel formed in an inside of the display region with respect to the end portion unit pixels and including inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship. With such a configuration, a relative area proportion of the end portion sub-pixels that correspond to the primary colors respectively in a one-to-one relationship is set equal to that of the inner sub-pixels that correspond to the primary colors respectively in a one-to-one relationship. The plurality of kinds of the end portion sub-pixels is arrayed in accordance with a position or a shape on an outer edge of the display region, an array direction of the plurality of kinds of the end portion sub-pixels and an array direction of the plurality of kinds of the inner sub-pixels configured to intersect each other.

<CIT> discloses a color filter substrate The color filter substrate includes a plurality of edge pixels. Each edge pixel includes a plurality of subpixels. Each subpixel is divided by the border line into a display portion at the display region and a non-display portion beyond the display region. The non-display portion is covered with a light-shielding layer. The plurality of subpixels includes a standard subpixel and a plurality of to-be-adjusted subpixels. For each to-be-adjusted subpixel, an additional light-shielding layer is provided at the display portion of the to-be-adjusted subpixel, or the light-shielding layer covering the non-display portion of the to-be-adjusted subpixel is provided with at least one aperture.

<CIT> is also of relevance to the claimed invention.

The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device.

In a first aspect of the present disclosure, there is provided an array substrate as defined in claim <NUM>.

In the embodiments of the present disclosure, the array substrate further comprises a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer on the substrate, and the array substrate further comprising a light shielding layer located between the active layer and the substrate, wherein the light shielding block is disposed on a same layer as the light shielding layer.

In the embodiments of the present disclosure, the array substrate further comprises a thin film transistor located on the substrate and in the light shielding region, wherein the thin film transistor comprises an active layer, a gate electrode and a gate dielectric layer therebetween, and the light shielding block is disposed on a same layer as the gate electrode.

In the embodiments of the present disclosure, the array substrate further comprises a thin film transistor located on the substrate, wherein the thin film transistor comprises an active layer, a gate electrode, a gate dielectric layer therebetween and a source/drain electrode disposed on the active layer, and the light shielding block is disposed on a same layer as the source/drain electrode.

In the embodiments of the present disclosure, the light shielding block further comprises a third portion located between the first portion and the second portion.

In the embodiments of the present disclosure, an absolute value of a difference between the one of the N values and a desired set value depending on a shape of an edge of the display region is smaller than an absolute value of a difference between any other one of the N values and the desired set value.

In a second aspect of the present disclosure, there is provided a display device. The display device comprises any of the array substrates as described in the first aspect of the present disclosure.

In a third aspect of the present disclosure, there is provided a method for manufacturing an array substrate as defined in claim <NUM>.

In the embodiments of the present disclosure, the method further comprises forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises: forming a light shielding material layer on the substrate; patterning the light shielding material layer to form a light shielding layer in the light shielding region, and form the light shielding block; forming a first insulating layer on the light shielding layer and the light shielding block; forming an active layer in the light shielding region and on the first insulating layer; forming a second insulating layer as a gate dielectric layer on the active layer; and forming a gate electrode in the light shielding region and on the second insulating layer.

In the embodiments of the present disclosure, the method further comprises forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises: forming an active layer on the substrate and in the light shielding region; forming a third insulating layer as a gate dielectric layer on the active layer; forming a first conductive layer on the third insulating layer; and patterning the first conductive layer to form a gate electrode in the light shielding region, and form the light shielding block.

In the embodiments of the present disclosure, before forming the active layer, the method further comprises forming a light shielding layer on the substrate and in the light shielding region, and forming a fourth insulating layer on the light shielding layer.

In the embodiments of the present disclosure, the method further comprises forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises: forming a second conductive layer on the substrate; patterning the second conductive layer to form a gate electrode in the light shielding region, and form the light shielding block; forming a fourth insulating layer on the gate electrode and the light shielding block; and forming an active layer in the light shielding region and on the fourth insulating layer.

In the embodiments of the present disclosure, the method further comprises forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises: forming a third conductive layer on the substrate; patterning the third conductive layer to form a gate electrode in the light shielding region; forming a fifth insulating layer as a gate dielectric layer on the gate electrode; forming an active layer in the light shielding region and on the fifth insulating layer; forming a fourth conductive material layer on the active layer; and patterning the fourth conductive material layer to form a source/drain electrode in the light shielding region, and form the light shielding block.

In the embodiments of the present disclosure, a third portion located between the first portion and the second portion is further formed.

In the embodiments of the present disclosure, an absolute value of a difference between the one of the N values and a desired set value depending on a shape of an edge of the display region is smaller than an absolute value of a difference between any other one of the N values and the desired set value.

Further aspects and scopes of applicability will become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended merely for the purpose of illustration, rather than limiting the scope of this application.

The drawings described herein are only for the purpose of illustration of the selected embodiments rather than any possible implementation, and they are not intended to limit the scope of this application, in which:.

Various embodiments will now be described in detail with reference to the drawings, and those embodiments are provided as exemplary embodiments of the present disclosure to enable persons skilled in the art to implement the technical solutions of the present disclosure.

It should be noted that the following drawings and examples are not intended to limit the scope of the present disclosure. In the case where specific elements of the present disclosure can be partially or entirely implemented using known components (or methods or processes), only those portions of such known components (or methods or processes) necessary to understand the present disclosure will be described, and the detailed description of other portions of such known components will be omitted so as not to obscure the technical solutions of the present disclosure. Further, by means of illustration, various embodiments comprise equivalents known at present and in future, which are equivalent to the components concerned herein.

The flowchart described in the present disclosure is just one example. There may be many modifications to the flowchart or the steps described therein without departing from the spirit of the present disclosure. For example, the steps may be performed in a different order, or the steps may be added, deleted, or amended. These modifications are considered as parts of the claimed aspects.

In the description of the present disclosure, the orientations or positional relations indicated by the terms "on", "above", "under", "below", "between", etc. are those illustrated based on the drawings. They are just used to facilitate and simplify the description of the present disclosure, rather than indicating or implying that any mentioned device or element must have a particular orientation, or be constructed or operated in a particular orientation, and hence cannot be construed as limitations to the present disclosure. In addition, when an element or layer is referred to as being "on" another element or layer, it may be directly located on the another element or layer, or there may be an intermediate element or layer; similarly, when an element or layer is referred to as being "under" another element or layer, it may be directly located under the another element or layer, or there may be at least one intermediate element or layer; and when an element or layer is referred to as being "between" two elements or layers, it may be an unique element or layer between the two elements or layers, or there may be more than one intermediate element or layer.

Unless additionally and explicitly pointed out in the context, the singular form of the words used herein and in the appended claims comprises the plural form, and vice versa. Thus, when a word is mentioned in the singular form, it usually comprises the plural form. Similarly, the words "comprise", "comprise", "contain", "have" and grammatical modifications thereof are intended to be inclusive and indicate that there may be additional elements in addition to the listed elements. Where the term "example" is used herein, and particularly following a group of terms, it is merely exemplary and illustrative, and should not be considered as exclusive or extensive. The terms "first", "second", "third" and the like are just used for description, and should not be understood as indicating or implying any relative importance or formation order.

<FIG> illustrates a schematic diagram of a structure of a display device. <FIG> illustrates a schematic diagram of a part of an array substrate of the display device as illustrated in <FIG>. As illustrated in <FIG>, an edge of a display region a of the display device is round-cornered macroscopically. However, microscopically, as illustrated in <FIG>, pixels b in the display region a are generally rectangular, and since an arrangement of the pixels b at the edge is uneven, the edge of the display region a appears to be sawtoothed. Thus, on displaying, the edge of the display region a will present a graininess and sawtooth feeling, thereby affecting the display effect of the display device.

<FIG> illustrates a schematic diagram of a part of an array substrate according to an embodiment of the present disclosure. As illustrated in <FIG>, the array substrate <NUM> may comprise a substrate <NUM>. The substrate <NUM> has a display region <NUM> and a peripheral region <NUM> surrounding the display region <NUM>. The peripheral region <NUM> may be disposed corresponding to a black matrix (not illustrated) on a color filter substrate (not illustrated). The display region <NUM> has a plurality of pixels <NUM> arranged in an array, and the pixels <NUM> may be disposed corresponding to color block (not illustrated) on the color filter substrate. The pixel <NUM> comprises a light transmission region <NUM> and a light shielding region <NUM>. The pixels located outside the display region <NUM> constitute a plurality of edge pixels <NUM>, i.e., pixels close to the peripheral region. According to the embodiment of the present disclosure, the array substrate <NUM> may further comprise a light shielding block <NUM> that covers at least a part of the light transmission region <NUM> of the edge pixel <NUM> to shield light transmission.

According to the embodiment of the present disclosure, since the light shielding block <NUM> covers at least a part of the light transmission region <NUM> of the edge pixel <NUM> of the array substrate <NUM>, a light transmittance of the edge pixel <NUM> (i.e., a ratio of a difference between an area of the light transmission region and an area of the light shielding block to an area of the light transmission region) is reduced, and a brightness of the edge pixel <NUM> is decreased, thereby reducing the acuity of human eyes in capturing the edge of the display region having a non-rectangular shape, finally relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect.

It should be noted that <FIG> illustrates only a part of the array substrate having the non-rectangular edge. In addition, the number of the pixels is not limited and can be set based on the actual need.

<FIG> illustrates a cross-sectional diagram of an edge pixel of an array substrate <NUM> according to an embodiment of the present disclosure. According to the embodiment of the present disclosure, the array substrate <NUM> may further comprise a thin film transistor <NUM> located on the substrate <NUM> and in the light shielding region <NUM>. The thin film transistor <NUM> comprises an active layer <NUM>, a gate dielectric layer <NUM>, and a gate electrode <NUM> sequentially disposed on the substrate <NUM>, i.e., the thin film transistor <NUM> is a top gate structure. According to the embodiment of the present disclosure, a material of the active layer may comprise Low Temperature Poly-Silicon (LTPS). The array substrate <NUM> may further comprise a light shielding layer <NUM> located between the active layer <NUM> and the substrate <NUM>. The light shielding layer <NUM> can prevent light rays from irradiating the active layer, and then avoid the performance of the thin film transistor <NUM> from being affected. According to the embodiment of the present disclosure, the light shielding block <NUM> in the light transmitting region <NUM> of the edge pixel <NUM> may be disposed on a same layer as the light shielding layer <NUM>. It should be noted that in the embodiments of the present disclosure, "disposed on a same layer" means being formed of a same film layer. The light shielding layer <NUM> and the light shielding block <NUM> thus may be made of a same material. In this case, the light shielding layer <NUM> and the light shielding block <NUM> can be simultaneously formed by the masking, exposing and etching processes at one time, thereby simplifying the process flow. In addition, an insulating layer <NUM> is disposed between the light shielding layer <NUM> and the active layer <NUM>.

As can be seen from the above description, the light transmittance of the edge pixel <NUM> can be reduced by disposing the light shielding block <NUM> in the light transmission region <NUM> of the edge pixel <NUM> of the array substrate <NUM>, thereby relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect. In addition, by disposing the light shielding block <NUM> on a same layer as the light shielding layer <NUM>, the process flow can be simplified.

<FIG> illustrates a cross-sectional diagram of an edge pixel of an array substrate <NUM> according to another embodiment of the present disclosure. According to the embodiment of the present disclosure, the array substrate <NUM> may further comprise a thin film transistor <NUM> located on the substrate <NUM> and in the light shielding region <NUM>. Like the thin film transistor <NUM> as illustrated in <FIG>, the thin film transistor <NUM> comprises an active layer <NUM>, a gate dielectric layer <NUM>, and a gate electrode <NUM> sequentially disposed on the substrate <NUM>. The array substrate <NUM> further comprises a light shielding layer <NUM> disposed between the active layer <NUM> and the substrate <NUM>, and an insulating layer <NUM> disposed between the light shielding layer <NUM> and the active layer <NUM>. According to the embodiment of the present disclosure, the light shielding block <NUM> in the light transmission region <NUM> of the edge pixel <NUM> may be disposed on a same layer as the gate electrode <NUM>. The light shielding block <NUM> and the gate electrode <NUM> may be made of a same material. In this case, the light shielding block <NUM> and the gate electrode <NUM> can be simultaneously formed by the masking, exposing and etching processes at one time, thereby simplifying the process flow.

<FIG> illustrates a cross-sectional diagram of an edge pixel of an array substrate <NUM> according to still another embodiment of the present disclosure. According to the embodiment of the present disclosure, the array substrate <NUM> may further comprise a thin film transistor <NUM> located on the substrate <NUM> and in the light shielding region <NUM>. The thin film transistor <NUM> comprises a gate electrode <NUM>, a gate dielectric layer <NUM>, and an active layer <NUM> sequentially disposed on the substrate <NUM>, i.e., the thin film transistor <NUM> is a bottom gate structure. According to the embodiment of the present disclosure, the light shielding block <NUM> in the light transmitting region <NUM> of the edge pixel <NUM> may be disposed on a same layer as the gate electrode <NUM>. The light shielding block <NUM> and the gate electrode <NUM> may be made of a same material. In this case, the light shielding block <NUM> and the gate electrode <NUM> can be simultaneously formed by the masking, exposing and etching processes at one time, thereby simplifying the process flow.

As can be seen from the above description, the light transmittance of the edge pixel <NUM> can be reduced by disposing the light shielding block <NUM> to cover at least a part of the light transmission region <NUM> of the edge pixel <NUM> of the array substrate <NUM>, thereby relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect. In addition, by disposing the light shielding block <NUM> on a same layer as the gate electrode <NUM>, the process flow can be simplified.

<FIG> illustrates a cross-sectional diagram of an edge pixel of an array substrate <NUM> according to yet another embodiment of the present disclosure. According to the embodiment of the present disclosure, the array substrate <NUM> may further comprise a thin film transistor <NUM> located on the substrate <NUM> and in the light shielding region <NUM>. The thin film transistor <NUM> comprises a gate electrode <NUM>, a gate dielectric layer <NUM> and an active layer <NUM> sequentially disposed on the substrate <NUM>, i.e., the thin film transistor <NUM> is a bottom gate structure. According to the embodiment of the present disclosure, the thin film transistor <NUM> may further comprise a source electrode <NUM>/ drain electrode <NUM> disposed on the active layer <NUM>. The light shielding block <NUM> in the light transmission region <NUM> of the edge pixel <NUM> may be disposed on a same layer as the source electrode <NUM>/drain electrode <NUM>. The light shielding block <NUM> and the source electrode <NUM>/drain electrode <NUM> may be made of a same material. In this case, the light shielding block <NUM> and the source electrode <NUM>/drain electrode <NUM> can be simultaneously formed by the masking, exposing and etching processes at one time, thereby simplifying the process flow.

As can be seen from the above description, the light transmittance of the edge pixel <NUM> can be reduced by disposing the light shielding block <NUM> to cover at least a part of the light transmission region <NUM> of the edge pixel <NUM> of the array substrate <NUM>, thereby relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect. In addition, by disposing the light shielding block <NUM> on a same layer as the source electrode <NUM>/drain electrode <NUM>, the process flow can be simplified.

According to the embodiment of the present disclosure, <FIG> illustrate schematic diagrams of a structure of a pixel <NUM> according to an embodiment of the present disclosure. As illustrated in <FIG>, a pixel <NUM> and an edge pixel <NUM> each may comprise three sub-pixels <NUM> located in a light transmission region <NUM>. The sub-pixels <NUM> may be red, green and blue sub-pixels, respectively, which may be disposed corresponding to respective color block (not illustrated) on the color film substrate. For the edge pixel <NUM>, as illustrated in <FIG>, the light shielding block <NUM> may be disposed within the three sub-pixels <NUM> to shield light transmission. Specifically, the light shielding block <NUM> within each of the sub-pixels <NUM> may have a same area, so that each of the sub-pixels <NUM> in a same edge pixel <NUM> has a same light transmittance, thereby avoiding the problem that one of the sub-pixels <NUM> is too bright and causing color difference.

According to the embodiment of the present disclosure, <FIG> illustrate schematic diagrams of a structure of an edge pixel <NUM> according to an embodiment of the present disclosure. As illustrated in <FIG>, the light shielding block <NUM> may comprise a first portion <NUM> and a second portion <NUM> that cover opposite ends of a light transmission region of an edge pixel <NUM>, respectively. In this way, the edge pixel <NUM> can be covered finely to achieve a better display effect. According to the embodiment of the present disclosure, as illustrated in <FIG>, the light shielding block <NUM> may further comprise a third portion <NUM> located between the first portion <NUM> and the second portion <NUM>. In this way, the edge pixel <NUM> can be further covered finely to achieve a better display effect.

According to the embodiment of the present disclosure, an area of the light shielding block <NUM> of each of the edge pixels <NUM> may be set according to a desired shape of an edge of the display region <NUM>. However, since the area of each of the light shielding blocks may be different depending on the shape of the edge, it is necessary to separately design a mask for each of the light shielding blocks, which potentially increases the number of the masks. In order to reduce the number of the masks, a ratio of the area of the light shielding block <NUM> of the edge pixel <NUM> to an area of the edge pixel <NUM> may be set as one of N values constituting an arithmetic progression, and specifically, <NUM>≤N≤<NUM>. The arithmetic progression has a first item of <NUM> and a last item of <NUM>%. This setting can reduce the number of the mask during manufacturing. In an exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%. According to the embodiment of the present disclosure, an absolute value of a difference between one of the N values and a desired set value depending on the shape of the edge of the display region may be smaller than an absolute value of a difference between any other one of the N values and the desired set value. For example, according to the shape of the edge of the display region <NUM>, if a ratio of an area of the light shielding block <NUM> of one of the edge pixels <NUM> to an area of the edge pixel <NUM> should be <NUM>%, the ratio of the area of the light shielding block <NUM> of the edge pixels <NUM> to the area of the edge pixel <NUM> can be set as <NUM>%, i.e., a value closest to <NUM>% selected from the above arithmetic progression. In another exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%. In still another exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%, <NUM>%.

In another aspect of the present disclosure, a method for manufacturing an array substrate described herein is provided. <FIG> illustrates a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.

The method for manufacturing the array substrate may comprise the following steps:.

In this embodiment, the substrate has a display region and a peripheral region surrounding the display region. The display region has a plurality of pixels arranged in an array, and each of the pixels comprises a light transmission region and a light shielding region. The pixels located outside the display region constitute a plurality of edge pixels.

According to the embodiment of the present disclosure, in S102, the light shielding block may comprise a first portion and a second portion that cover opposite ends of a light transmission region of an edge pixel, respectively. In this way, the edge pixel can be covered finely to achieve a better display effect. According to the embodiment of the present disclosure, the light shielding block may further comprise a third portion located between the first portion and the second portion. In this way, the edge pixel can be further covered finely to achieve a better display effect.

According to the embodiment of the present disclosure, an area of the light shielding block of each of the edge pixels may be set according to a desired shape of an edge of the display region. A ratio of the area of the light shielding block <NUM> of the edge pixel <NUM> to an area of the edge pixel <NUM> may be set as one of N values constituting an arithmetic progression, and specifically, <NUM>≤N≤<NUM>. The arithmetic progression has a first item of <NUM> and a last item of <NUM>%. This setting can reduce the number of the mask during manufacturing. In an exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%. In another exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%. In still another exemplary embodiment, N is equal to <NUM>, and the arithmetic progression may be <NUM>, <NUM>%, <NUM>%, <NUM>%.

As can be seen from the above description, since the light shielding block covers the light transmission region of the edge pixel, a light transmittance of the edge pixel is reduced, and a brightness of the edge pixel is decreased, thereby reducing the acuity of human eyes in capturing the edge of the display region having a non-rectangular shape, finally relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect.

According to an embodiment of the present disclosure, the method for manufacturing the array substrate may further comprise forming a thin film transistor on the substrate and in the light shielding region. Specifically, the steps of forming the thin film transistor may comprise S201 to S206.

The method provided by this embodiment is used for the array substrate as illustrated in <FIG> and described in the aforementioned embodiments, and its structure, function and/or advantages are the same as those of the array substrate in the aforementioned embodiments, which will not be described in detail here.

According to another embodiment of the present disclosure, the method for manufacturing the array substrate may further comprise forming a thin film transistor on the substrate and in the light shielding region. Specifically, the steps of forming the thin film transistor may comprise S301 to S304.

In this embodiment, before S301, the method may further comprise forming a light shielding layer <NUM> on the substrate <NUM> and in the light shielding region, and forming a fourth insulating layer <NUM> on the light shielding layer <NUM>.

According to still another embodiment of the present disclosure, the method for manufacturing the array substrate may further comprise forming a thin film transistor on the substrate and in the light shielding region. Specifically, the steps of forming the thin film transistor may comprise S401 to S404.

According to yet another embodiment of the present disclosure, the method for manufacturing the array substrate may further comprise forming a thin film transistor on the substrate and in the light shielding region. Specifically, the steps of forming the thin film transistor may comprise S501 to S506.

In still another aspect of the present disclosure, there is also provided a display device comprising the array substrate described in the aforementioned embodiments. <FIG> illustrates a schematic diagram of a display device according to an embodiment of the present disclosure. As illustrated in <FIG>, the display device <NUM> according to the present disclosure comprises the aforementioned array substrate <NUM>. The light transmittance of the edge pixel can be reduced by disposing the light shielding block to cover at least a part of the light transmission region of the edge pixel of the array substrate of the display device, thereby relieving the problem of graininess and sawtooth feeling at the edge of the display region, and improving the display effect.

Claim 1:
An array substrate (<NUM>), comprising:
a substrate (<NUM>) having a display region (<NUM>) and a peripheral region (<NUM>) surrounding the display region (<NUM>), the display region (<NUM>) having a plurality of pixels (<NUM>) arranged in an array, the substrate further comprising edge pixels (<NUM>) located outside the display region and close to the peripheral region, wherein each of the plurality of pixels (<NUM>) and edge pixels (<NUM>) comprises a light transmission region (<NUM>) and a light shielding region (<NUM>), a light shielding block (<NUM>) covering at least a part of the light transmission region (<NUM>) of the edge pixels (<NUM>), wherein the display region (<NUM>) has a non-rectangular shape and each edge pixel (<NUM>) has a rectangular shape,
wherein the light shielding block (<NUM>) comprises a first portion (<NUM>) and a second portion (<NUM>) respectively covering opposite ends of the light transmission region (<NUM>) of each edge pixel (<NUM>) ,
characterized in that
an area of the light shielding block (<NUM>) of each edge pixel (<NUM>) is set according to the shape of the associated edge of the display region (<NUM>), such that a ratio of the area of the light shielding block (<NUM>) to the area of the edge pixel (<NUM>) is set as one of N values constituting an arithmetic progression, wherein <NUM>≤N≤<NUM>, and the arithmetic progression has a first item of <NUM>% and a last item of <NUM>%.