Patent Description:
In certain wireless communication systems, a cellular base station transmitter lineup includes a digital signal processor connected to one or more radio frequency (RF) transmit front end circuits over one or more communication links. The digital signal processor produces digital samples that are communicated over the communication link(s) to RF transmit front end circuit(s). Each RF transmit front end circuit includes a data converter (e.g., a digital-to-analog converter), a transmit power amplifier, and an antenna. The data converter converts the digital samples received from the digital signal processor into analog signals, which are upconverted and amplified by the power amplifier, and communicated over the air interface by the antenna.

In some systems, the digital samples to be communicated from the digital signal processor to the data converter are sent according to one of a number of known serial link communications protocols, and in particular, a protocol that defines a serialized communication interface between a logic device and data converters (e.g., digital-to-analog converters and analog-to-digital converters). According to some serial link communications protocols, the logic device sends the digital samples to a serialized transmitter, which buffers, frames, and serializes the digital samples, and transmits the serialized sample stream over one or more "lanes" (i.e., where a "lane" is a differential signal pair for data transmission) to the data converter. As indicated above, the data converter, and more specifically a digital-to-analog converter, converts the digital samples to an analog signal. The analog signal is upconverted and amplified by the power transistor, and ultimately transmitted over the air interface by the antenna.

In some cases, control information that should be synchronized (or time-aligned) with the digital samples also may need to be sent from the digital signal processor to downstream components. This control information is sent over a communications link that is separate and distinct from the serial communication interface. Given ever-increasing wireless communication frequencies, system designers are increasingly finding it challenging to synchronize the analog signal (i.e., converted digital samples) and the control information at the downstream component. Accordingly, what are needed are improved apparatus and methods for communicating and synchronizing, at a downstream component, control information with an analog signal converted from digital samples sent over a serial communication link.

Document <CIT> discloses a base station comprising a JESD204 serial data link between the digital front end and the RF transceiver/transmit front end circuit.

<FIG> is a simplified block diagram of a wireless communication system <NUM> in which a device <NUM>, <NUM> includes a digital front end (DFE) <NUM>, <NUM> that communicates both data and control information to a radio frequency (RF) transmitter lineup within an RF transceiver <NUM>, <NUM> using a serial link communications protocol. More specifically, wireless communication system <NUM> includes a plurality of wireless devices or subscriber stations <NUM> (e.g., hand-held computers, personal digital assistants (PDAs), cellular telephones, etc.) that wirelessly communicate with one or more base station systems (BSS) <NUM> (e.g., evolved Node-B or eNB devices of an LTE (Long Term Evolution) network) using RF communication signals.

Each wireless device <NUM> may include a baseband processor <NUM> (e.g., a digital signal processor) connected through a DFE processor <NUM> to an RF transceiver <NUM>, which in turn is connected to one or more antennas <NUM>. The baseband processor <NUM> and the DFE processor <NUM> may be implemented as one or more integrated circuits to provide the digital processing functionality of the wireless device <NUM>. The digital processing components consolidated on the DFE processor <NUM> may include one or more control processors and digital transmit/receive filters, as well as interface peripherals and other I/O for RF subsystem functions. Essentially, each RF transceiver <NUM> (including an RF transmitter and an RF receiver) is configured to receive or transmit voice, data, or both voice and data using the antenna(s) <NUM>, and to provide an interface for signals between the antennas <NUM> and the DFE processor <NUM>. More specifically, each RF transceiver <NUM> is configured to perform digital-to-analog conversion and amplification of signals from the DFE processor <NUM>, and to amplify and perform analog-to-digital conversion of signals received over the air interface by an antenna <NUM>. In addition, each wireless device <NUM> may include one or more input/output devices <NUM> (e.g., a camera, a keypad, display, etc.), along with other components (not shown).

The BSS <NUM> includes a base station controller (BSC) <NUM> and one or more base transceiver stations (BTS) <NUM>, where each BTS <NUM> provides a communication interface between the BSC <NUM> and antennas <NUM>. The BSC <NUM> may, for example, be configured to schedule communications for the wireless devices <NUM>. Through antennas <NUM>, <NUM>, each wireless device <NUM> communicates with the BSC <NUM> of the BSS <NUM> via one of the BTS <NUM>.

Essentially, each BTS <NUM> is configured to receive or transmit signals that include processed voice, data, or both voice and data through the antenna(s) <NUM>, and to provide an interface for signals between the antennas <NUM> and the BSC <NUM>. The BTS(s) <NUM> each include a DFE processor <NUM> which may be implemented as one or more integrated circuits to provide the digital processing functionality of the BTS <NUM>. The digital processing components consolidated on the DFE processor <NUM> may include one or more control processors and digital transmit/receive filters, as well as interface peripherals and other I/O for RF subsystem functions. In addition, the BTS(s) <NUM> each include an RF transceiver <NUM> (including an RF transmitter and an RF receiver), which is configured to perform digital-to-analog conversion and amplification of signals from the DFE processor <NUM>, and to amplify and perform analog-to-digital conversion of signals received over the air interface by an antenna <NUM>. As will be described in more detail below, the DFE processor <NUM> and the RF transmitter of the RF transceiver <NUM> communicate digital samples over one or more serialized links, and according to an embodiment, control information may be multiplexed with at least some of the digital samples.

As will be appreciated, the digital sample and control information communication techniques disclosed herein with reference to the base station system <NUM> may also be used in connection with a wireless communication device, such as the wireless devices <NUM>. To this end, and as mentioned earlier, each wireless device <NUM> may also include a DFE processor <NUM> connected to a corresponding RF transceiver <NUM>, and the DFE processor <NUM> and the RF transmitter of the RF transceiver <NUM> also may be configured to communicate digital samples over one or more serialized links, where control information may be multiplexed with at least some of the digital samples.

To further illustrate the digital sample and control information communication techniques disclosed herein, reference is now made to <FIG> which is a high level architecture block diagram illustration of a portion of a multi-antenna RF BTS <NUM> (e.g., BTS <NUM>, <FIG>). The BTS <NUM> is connected between a base station controller (e.g., BSC <NUM>, <FIG>) and transmit antennas <NUM>-<NUM> and receive antennas <NUM>-<NUM>. The BTS <NUM> includes a DFE processor <NUM> (or more generally, a "digital data processor") connected through a plurality of lanes <NUM>-<NUM>, <NUM>-<NUM> (i.e., differential signal line pairs for data transmission in one direction) to a plurality of RF transmit front end circuits <NUM>-<NUM> and RF receive front end circuits <NUM>-<NUM>. As will be appreciated, the DFE processor <NUM> may be located in a radio head that is co-located with the base station controller (e.g., BSC <NUM>, <FIG>), or may be located at a remote radio head that is not co-located with the base station controller. For simplicity of illustration, the transmit antennas <NUM>-<NUM> and receive antennas <NUM>-<NUM> are shown as being separate from one another, but it will be appreciated that a shared plurality of antennas may be used for both signal transmission and reception in a shared or switched circuit arrangement. In such an arrangement, a duplexer (e.g., a circulator) and/or an RF switch between each antenna and a transceiver (consisting of a RF transmit front end circuit and a receive front end circuit) may be used to isolate the transmit signals from the receive signals during operation.

The DFE processor <NUM> essentially is a digital signal processor (or digital data processor), which is provided to perform digital signal processing for the BTS <NUM> across the separate transmit antennas <NUM>-<NUM> and/or receive antennas <NUM>-<NUM>. To this end, the DFE processor <NUM> partitions transmit and receive signals to and from the antennas into transmit processing paths and receive processing paths, and communicates with a baseband modem (not illustrated) through a modem interface (e.g., a Common Public Radio Interface (CPRI) interface and/or JESD204 interface, not illustrated). For example, a base station controller (e.g., BSC <NUM>, <FIG>) may generate real (I) and imaginary (Q) samples (i.e., instantaneous values of a signal measured or determined at discrete times) for each transmit signal path, which are to be transmitted via diversity antennas <NUM>-<NUM>.

The DFE processor <NUM> may include one or more control processors or CPUs <NUM> (e.g., one or more ARM processor cores), memory subsystems (e.g., instruction and data caches), memory controllers (not illustrated) for interfacing with external memory (e.g., flash memory, SDRAM, and so on), one or more modem interfaces, and I/O facilities (e.g., a host bridge) for I/O devices (not illustrated). As a general matter, any of a variety of memory designs and hierarchies may be employed in, or in conjunction with, with the DFE processor <NUM>. Also, it will be appreciated that the I/O devices may include any desired I/O device, such as Ethernet, I2C, SPI, GPIO, and/or UART devices. All processor subsystems are linked by a multi-level interconnect fabric <NUM>.

To digitally process transmit signals, the DFE processor <NUM> may also include a programmable transmit signal processing path for each transmit antenna <NUM>-<NUM>, where each processing path includes a transmit signal processor <NUM>, a serialized transmit (TX) interface <NUM>-<NUM> (SER TX IFC), a transmit lane <NUM>-<NUM> (i.e., a differential signal pair), and an RF transmit front end circuit <NUM>-<NUM>. In this way, a first transmit signal processing path is formed by the connection of the transmit signal processor <NUM> and serialized TX interface <NUM> (including interface <NUM>-<NUM> and <NUM>-Q), which are connected over real and imaginary (I and Q) signal lines of a first transmit lane <NUM> to RF transmit front end circuit <NUM> and antenna <NUM>, a second transmit signal processing path is formed by the connection of the transmit signal processor <NUM> and serialized TX interface <NUM>, which are connected over differential signal lines of a second transmit lane <NUM> to RF transmit front end <NUM> and antenna <NUM>, and a third transmit signal processing path is formed by the connection of the transmit signal processor <NUM> and serialized TX interface <NUM>, which are connected over differential signal lines of a third transmit lane <NUM> to RF transmit front end <NUM> and antenna <NUM>. Although three transmit signal processing paths are depicted in <FIG>, fewer or more transmit signal processing paths may be implemented in other systems.

The transmit signal processor <NUM> may include one or more processors (e.g., vector processors) and associated memory (e.g., RAM) for performing carrier-related signal processing and antenna-specific processing on I and Q samples received from the baseband modem. In addition, and according to an embodiment, the transmit signal processor <NUM> may produce control information (in the form of one or more control bits) that is correlated in time with the processed samples. According to an embodiment, the transmit signal processor <NUM> determines the values of the control bit(s) based on the instantaneous voltage values (or magnitudes) of the samples being processed by the transmit signal processor <NUM>. For example, as will be discussed in more detail later, the control bits may be selected to configure an externally controllable sub-circuit in the amplifier (e.g., sub-circuits <NUM>, <NUM>, <FIG>, <FIG>, described in more detail below) in a first state when the instantaneous voltage value is relatively high (e.g., approaching or above a transition point α, <FIG>), and may be selected to configure the externally controllable sub-circuit in the amplifier in a second state when the instantaneous voltage value is relatively low (e.g., below transition point α, <FIG>). In other embodiments, the transmit signal processor <NUM> determines the values of the control bit(s) based on the envelope amplitude of the transmit signal. For example, the control bits may be selected to configure the externally controllable sub-circuit in the amplifier in a first state when the envelope amplitude is relatively high, and may be selected to configure the externally controllable sub-circuit in the amplifier in a second state when the envelope amplitude is relatively low.

Once signal processing is completed, and as will be described in more detail in conjunction with <FIG>, the transmit signal processor <NUM> may send the processed I and Q samples and the control bit(s) to associated transmit-side serialized interfaces (e.g., serialized TX interface <NUM>-<NUM> and <NUM>-Q, respectively). Basically, each of serialized TX interface <NUM>-<NUM> and serialized TX interface <NUM>-Q comprise a circuit that serializes input frames (e.g., sets of consecutive words/octets in which the position of each word/octet can be identified by reference to a frame alignment signal) and transports the resulting bit stream across a lane (e.g., lane <NUM>). According to an embodiment, each serialized TX interface <NUM>-I and serialized TX interface <NUM>-Q implements a JESD204 serial link communications protocol (e.g., according to a JESD204A (<NUM>), JESD204B (<NUM>), or JESD204C (<NUM>) serial interface for data converter standard, issued by JEDEC Solid State Technology Association, including future versions). The JESD204 serial link communications protocol represents one family of serial link communications protocols. It should be appreciated that, although a JESD204 serial link communications protocol is used as an example herein, the data interface may be implemented with other suitable serialized interfaces, or alternatively may be implemented with a parallel interface, or with other protocols with similar capabilities.

According to an embodiment, the serialized TX interface <NUM>-<NUM> may combine the control bit(s) with I samples, the serialized TX interface <NUM>-Q may combine (e.g., multiplex) the control bit(s) with Q samples, or both serialized TX interface <NUM>-I and serialized TX interface <NUM>-Q may combine control bits with both I and Q samples. Serialized TX interface <NUM>-I then frames, optionally encodes, and serializes the I data stream, and transfers the serialized I data stream to the transceiver (e.g., RF transmit front end circuit <NUM>) over one of the differential signal lines of the first transmit lane <NUM>. Serialized TX interface <NUM>-Q frames, optionally encodes, and serializes the Q data stream and transfers the serialized Q data stream to the transceiver over the other of the differential signal lines of the first transmit lane <NUM>. According to another embodiment, rather than combining the control bit(s) with either or both of the I and/or Q samples, the serialized TX interface <NUM> may interject an octet or a word into either or both of the I and/or Q data streams that includes the control information (e.g., without sample data). It should be understood that a particular data link may consist of a single lane (e.g., lane <NUM>) or multiple lanes (e.g., multiple ones of lanes <NUM>-<NUM>) as needed to support the required data throughput. Further, each lane <NUM>-<NUM> may convey synchronization and alignment data that allows transmitted data to be reassembled in the RF transmit front end circuit <NUM>, thus enabling the original data samples to be reproduced.

According to an embodiment, RF transmit front end circuit <NUM> includes one or two serialized receive (RX) interfaces <NUM>-<NUM>, <NUM>-Q (SER RX IFC), one or more control circuits <NUM>, <NUM>, digital-to-analog converters (DACs) <NUM>, <NUM>, low pass filters (LPFs), an oscillator, mixers, a signal combiner <NUM>, and a power amplifier <NUM>. Basically, each of serialized RX interface <NUM>-I and serialized RX interface <NUM>-Q comprise a circuit attached to a lane (e.g., lane <NUM>), where the circuit is configured to reconstruct a serial bit stream into time-aligned frames. According to an embodiment, each serialized RX interface <NUM>-I and serialized RX interface <NUM>-Q implements a JESD204 serial link communications protocol, although other protocols could be implemented as well, as mentioned above. Serialized RX interface <NUM>-I is configured to receive the I data stream from one of the differential signal lines of the first transmit lane <NUM>. Serialized RX interface <NUM>-Q, when included, is configured to receive the Q sample stream from the other of the differential signal lines of the first transmit lane <NUM>. In embodiments in which the serialized TX interface <NUM> combines control bit(s) with only the I sample stream (but not the Q sample stream), serialized RX interface <NUM>-Q and control circuit <NUM> may be excluded, and the associated differential signal line of the first transmit lane <NUM> may instead be directly coupled to DAC <NUM>, as indicated by the dashed-line arrow. In other embodiments in which the serialized TX interface <NUM> combines control bit(s) with only the Q sample stream (but not the I sample stream), serialized RX interface <NUM>-I and control circuit <NUM> may be excluded, and the associated differential signal line of the first transmit lane <NUM> may instead be directly coupled to DAC <NUM>, as indicated by the other dashed-line arrow.

Upon receiving an I or Q serialized data stream, each serialized RX interface <NUM>-I, <NUM>-Q is configured to separate the control bit(s) from the sample bits within the serialized data stream, and to re-construct the I or Q samples from the extracted sample bits. Each serialized RX interface <NUM>-I, <NUM>-Q sends the I or Q samples to DAC <NUM> or <NUM>. Each DAC <NUM>, <NUM> includes a circuit for converting a digital sampled data stream to an analog signal. Because the analog signals are converted from a complex data stream, each DAC <NUM>, <NUM> may be defined as a subblock accepting either the real (I) or the imaginary (Q) component of the data stream. Each DAC <NUM>, <NUM> performs a digital-to-analog conversion on each received sample, and the resulting analog samples are filtered (e.g., by an LPF). The oscillator produces an RF sinusoidal signal that is used to upconvert (to RF) the analog I and Q sample streams. The filtered, analog I sample stream is mixed with the RF signal, and the filtered, analog Q sample stream is mixed with a <NUM> degree delayed version of the RF signal in order to re-align the I and Q sample streams. Combiner <NUM> then combines the two sample streams and provides a single RF input signal to the power amplifier <NUM>.

As mentioned above, the power amplifier <NUM> may include one or more externally controllable sub-circuits (e.g., circuits <NUM>, <NUM>, <FIG>, <FIG>), the operation of which is controlled using the control bit(s) received in the I and/or Q serialized data streams. Accordingly, upon separating the control bit(s) from the sample bits within a serialized data stream, each serialized RX interface <NUM>-I, <NUM>-Q sends the control bit(s) to the control circuit <NUM>, <NUM>. According to an embodiment, each control circuit <NUM>, <NUM> may convert the received control bit(s) to control signals, and may send the control signals to the power amplifier <NUM> so that the control signals are time-aligned with the converted I or Q samples. In other words, the control circuit <NUM>, <NUM> may buffer, and more specifically impart a programmable delay, to a control signal to ensure that the amplifier <NUM> performs a desired circuit modification operation (as controlled by the control signal) simultaneously with amplifying the converted I or Q sample from the same word that the control bit(s) associated with the control signal were extracted.

Turning now to the receive side of the system of <FIG>, received signals may be received and digitally processed at the DFE processor <NUM> with a programmable receive signal processing path for each receive antenna <NUM>-<NUM>. Each receive signal processing path is formed with a RF receive front end circuit <NUM>-<NUM> that is connected to a receive antenna <NUM>-<NUM>, a receive lane <NUM>-<NUM> (i.e., a differential signal pair), an associated serialized RX interface <NUM>-<NUM> (e.g., a JESD204 RX interface), and a receive signal processor <NUM>. In this way, a first receive signal processing path is formed by the connection of the antenna <NUM> and RF receive front end circuit <NUM> which are connected over differential signal lines of a first receive lane <NUM> to the serialized RX interface <NUM> and receive signal processor <NUM>, a second receive signal processing path is formed by the antenna <NUM> and RF receive front end <NUM> which are connected over differential signal lines of a second receive lane <NUM> to the serialized RX interface <NUM> and receive signal processor <NUM>, and a third receive signal processing path is formed by the antenna <NUM> and RF receive front end <NUM> which are connected over differential signal lines of a third receive lane <NUM> to the serialized RX interface <NUM> and receive signal processor <NUM>. Although three receive signal processing paths are depicted in <FIG>, fewer or more receive signal processing paths may be implemented in other systems.

Each RF receive front end circuit <NUM>-<NUM> includes RF conversion circuit components (e.g., a splitter, an oscillator, mixers, low pass filters (LPF), amplifiers, analog-to digital converters (ADCs), etc.) that process an RF signal from the corresponding antenna (e.g., antenna <NUM>) by separating the signal into I and Q signal components, and converting the I and Q signals into digitized serial I and Q data streams for processing by the DFE processor <NUM>.

The receive signal processor <NUM> may include one or more processors (e.g., vector processors) and associated memory (e.g., RAM) for performing receive signal processing on IQ samples received from each RF receive front end circuit <NUM>-<NUM> over one of the serialized RX interfaces <NUM>-<NUM>. Once signal processing is completed, the receive signal processor <NUM> may send the processed samples to the baseband modem.

With multiple transmit and/or receive signal paths between the DFE processor <NUM> and antennas <NUM>-<NUM>, <NUM>-<NUM>, there may be different signal path latencies on each signal path due to different hardware implementations and link delays for each path. For example, different inherent signal path delays can arise along each signal path due to digital filtering, analog-to-digital or digital-to-analog converters, analog components, coaxial length, and other wire delays. To avoid potential problems that may otherwise arise due to different inherent delays in each transmit signal path, a software-based and/or hardware-based synchronization may be implemented by the DFE processor <NUM> that controls the serialized interfaces <NUM>-<NUM>, <NUM>-<NUM> in order to provide timing alignment of the data into and out of the DFE processor <NUM>.

To provide additional details of selected embodiments, reference is now made to <FIG> which depicts a block diagram of a portion of RF BTS <NUM> (e.g., BTS <NUM>, <FIG>) in more detail. To avoid obfuscating the inventive subject matter, <FIG> depicts only one transmit signal path within BTS <NUM>, which includes serialized TX interfaces <NUM>-I, <NUM>-Q (within DFE <NUM>) coupled to serialized RX interfaces <NUM>-I, <NUM>-Q (within RF transmit front end <NUM>).

As discussed previously in conjunction with <FIG>, RF BTS <NUM> includes DFE <NUM> and RF transmit front end circuit <NUM>, which are communicatively coupled through IQ signal lines of transmit lane <NUM>. Among other components, as discussed above, DFE <NUM> includes sample memory <NUM>, serialized TX interface <NUM>-I, and serialized TX interface <NUM>-Q. Sample memory <NUM> (e.g., RAM) is configured to store I and Q data samples for transmission to the RF transmit front end circuit <NUM>, and ultimately, over the air interface via antenna <NUM>.

In operation, the base station controller <NUM> (e.g., BSC <NUM>, <FIG>) generates the I and Q data samples, which are to be transmitted via antenna <NUM>. According to an embodiment, each I and Q data sample includes N bits, where N may be any integer that is not an integer multiple of the number of bits, M, in a data packet (e.g., N may be an integer between <NUM> bits and <NUM> bits), according to various embodiments. In the examples described below, N=<NUM> bits (i.e., each I and Q sample is a <NUM>-bit sample). However, in other examples, N may be less than or greater than <NUM> bits. Either way, the I and Q data samples for the transmit signal path are stored in sample memory <NUM> (e.g., including RAM with an I-sample buffer and a Q-sample buffer).

Each of serialized TX interface <NUM>-I and serialized TX interface <NUM>-Q includes a first-in first-out (FIFO) input buffer <NUM>, <NUM> connected in series with a switched-framer module <NUM>, <NUM> (referred to simply as "framer", below), an encoder <NUM>, <NUM>, and a serializer <NUM>, <NUM>. Each FIFO input buffer <NUM>, <NUM> receives I or Q data (and more specifically, a stream of I or Q data samples), respectively, from the sample memory <NUM> (e.g., over the interconnect fabric <NUM>, <FIG>) and stores the I or Q data as one or more data packets. Each data packet may have a same number of bits, M. In a specific embodiment, each data packet is an octet (i.e., a group of eight adjacent binary digits, similar to a byte), and accordingly M=<NUM> bits. In other example embodiments, M may be less than or greater than <NUM> bits.

According to an embodiment, the number of bits in a data sample, N, is not equal to the number of bits in a data packet, M. According to a further embodiment, N is also not equal to integer multiples of M (e.g., 2xM, 3xM, and so on). Accordingly, when the N-bit data sample is stored in one or more M-bit data packets in a FIFO input buffer <NUM> or <NUM>, the N bits of the sample will only partially fill the M available bits of the one or more data packets, and at least one bit of the one or more data packets will be "unfilled" or "empty" (i.e., devoid of data sample bits). The number of unfilled or empty bits of a data packet may include as few as one bit, or as many as M-<NUM> bits, in various embodiments.

<FIG>, which should be viewed simultaneously with <FIG>, is provided to further illustrate the data formatting and operations that are performed by serialized TX interface <NUM>-I and serialized TX interface <NUM>-Q, in accordance with an example embodiment. The example depicted in <FIG> corresponds to an embodiment in which the length of each data sample is <NUM> bits (i.e., N=<NUM>) and the length of each data packet is <NUM> bits (i.e., M=<NUM>). Specifically, data format <NUM> depicts a data sample <NUM> (I or Q) that includes <NUM> bits (S0-S14), and data format <NUM> depicts the bits of data sample <NUM> stored (e.g., in FIFO <NUM> or <NUM>) in two, equal-sized data packets <NUM>, <NUM>. More specifically, the first <NUM> bits of the data sample <NUM> are stored in the first data packet <NUM>, and the next <NUM> bits of the data sample <NUM> are stored in the second data packet <NUM>. This leaves one bit <NUM> of data packet <NUM> unfilled. It should be noted that, although the last bit <NUM> of data packet <NUM> is shown to be unfilled in <FIG>, the storage of the bits of data sample <NUM> into data packets <NUM>, <NUM> could be modified so that a different bit of either data packet <NUM> or <NUM> is unfilled, instead.

Referring again also to <FIG>, each framer <NUM>, <NUM> receives a stream of I or Q data packets (e.g., data packets <NUM>, <NUM>, <FIG>) from a FIFO input buffer <NUM>, <NUM>, and adds markers to frame each data packet. In addition, and according to an embodiment, each framer <NUM>, <NUM> also receives one or more control bits from the transmit processor <NUM> through inputs <NUM>, <NUM>, where the control bit(s) are aligned, in time, with the I or Q data packets that are received from the FIFO input buffer <NUM>, <NUM>. The framer <NUM>, <NUM> is configured to combine (or multiplex) the received control bit(s) into one or more of the received data packets. More specifically, each framer <NUM>, <NUM> inserts the control bit(s) into one or more of the unfilled bits (e.g., bit <NUM>, <FIG>) of the received data packets. For example, each framer <NUM>, <NUM> may include a multiplexer (not shown), which receives the I or Q data packets as one input and the control bit(s) as another input, and outputs modified versions of the I or Q data packets that include the inserted the control bit(s). Referring again to <FIG>, for example, data format <NUM> depicts data packets <NUM>, <NUM>', where data packet <NUM>' includes a control bit <NUM> (C1) inserted into the previously unfilled bit <NUM> of data packet <NUM>. After inserting the control bit(s) into the data packet(s), each framer <NUM>, <NUM> conveys the M-bit data packets to encoders <NUM>, <NUM>.

Each encoder <NUM>, <NUM> may be configured to convert the M-bit data packets into encoded symbols with more than M bits. Encoding in this manner may enhance DC-balance and provide bounded disparity, while providing a sufficient number of state changes to allow reasonable clock recovery. For example, each encoder <NUM>, <NUM> may be an 8b/10b encoder, in an embodiment, which receives <NUM>-bit data packets (e.g., data packets <NUM>, <NUM>', <FIG>), and converts each <NUM>-bit data packet into a <NUM>-bit symbol. In other embodiments, each of the encoders <NUM>, <NUM> may be a 64b66b encoder, which converts a <NUM>-bit output from a framer <NUM>, <NUM> to <NUM>-bit format, or each of the encoders <NUM>, <NUM> may be a 64b80b encoder, which converts a <NUM>-bit output from a framer <NUM>, <NUM> to <NUM>-bit format. The 8b/10b link layer organizes the data into multiframes, which contain K x F octets, where K is the number of frames in a multiframe, and F is the number of octets in each frame. The 64b/66b and 64b/80b link layers organize the data into multiblocks, which contain <NUM> blocks, with each block containing eight octets. Other encoding schemes may be implemented, as well. In some embodiments, the data is communicated without encoding, in which case encoders <NUM>, <NUM> and decoders <NUM>, <NUM> may be excluded.

The encoded symbols produced by encoders <NUM>, <NUM> (or the framed data if encoding is not implemented) are provided to serializers <NUM>, <NUM>, which proceed to communicate the encoded symbols to the RF transmit front end circuit <NUM> in a serial manner over the IQ signal lines of the transmit lane <NUM>.

As discussed previously, the RF transmit front end circuit <NUM> includes serialized RX interfaces <NUM>-I and/or <NUM>-Q, which are coupled to the I and Q signal lines, respectively, of transmit lane <NUM>. Essentially, upon receiving I or Q serialized symbols, each serialized RX interface <NUM>-I, <NUM>-Q is configured to decode the symbols (assuming prior encoding), separate the control bit(s) from the sample bits within the resulting data packet stream, and re-construct the I or Q samples from the extracted sample bits. The RF transmit front end circuit <NUM> is further configured to convert the I and Q samples to analog signals, and to upconvert, combine, and amplify the analog I and Q samples. In addition, the RF transmit front end circuit <NUM> is configured to convert the control bit(s) using one or more control circuits <NUM>, <NUM> into control signals (e.g., analog or digital control signals) that are provided to the amplifier <NUM>. The amplifier <NUM> utilizes the control signals to control one or more aspects of the amplification process, according to an embodiment. Ultimately, the amplified RF signal produced by the amplifier <NUM> is conveyed to antenna <NUM>, which transmits the amplified RF signal over the air interface.

Each of serialized RX interface <NUM>-I and serialized RX interface <NUM>-Q includes a deserializer <NUM>, <NUM> connected in series with a decoder <NUM>, <NUM>, and a switched de-framer module <NUM>, <NUM> (referred to simply as "de-framer", below). Essentially, these components are configured to re-construct the data packets that were previously supplied to the framer <NUM> on the transmit side, and also to extract the control bits from the I and/or Q data streams. More particularly, the de-serializers <NUM>, <NUM> receive the encoded, serialized I and Q symbols, respectively, that were transmitted by the DFE processor <NUM> over the IQ signal lines of the transmit lane <NUM>. The de-serializers <NUM>, <NUM> convert the serialized symbol streams into discrete symbols. Assuming encoding was performed on the transmit side, the decoders <NUM>, <NUM> then decode the symbols by performing an inverse operation to the encoding operation previously performed by encoders <NUM>, <NUM>. For example, when the encoders <NUM>, <NUM> are 8b/10b encoders, decoders <NUM>, <NUM> should be 8b/10b decoders, which produce a stream of <NUM>-bit decoded I and Q data packets (e.g., reconstructed versions of data packets <NUM>, <NUM>', <FIG>) from received <NUM>-bit symbols. Alternatively, the encoders <NUM>, <NUM> may be 64b66b decoders (i.e., producing <NUM>-bit data packets from <NUM>-bit symbols), 64b80b decoders (i.e., producing <NUM>-bit data packets from <NUM>-bit symbols), or other compatible types of decoders.

The reconstructed I and Q data packets are provided to de-framers <NUM>, <NUM>, respectively. According to an embodiment, each de-framer <NUM>, <NUM> is configured to separate (or demultiplex) the control bit(s) from the received data packets. More specifically, each de-framer <NUM>, <NUM> extracts the control bit(s) from the one or more bits of the received data packets (e.g., bit <NUM>, <FIG>). For example, each de-framer <NUM>, <NUM> may include a de-multiplexer (not shown), which receives the I or Q data packets from a decoder <NUM>, <NUM>, extracts the control bit(s) (e.g., C1 <NUM>, <FIG>) from one or more designated bits (e.g., bit <NUM>) of the I or Q data packets, and conveys the control bit(s) to the corresponding control circuit <NUM>, <NUM>. Although separate control circuits <NUM>, <NUM> are shown in <FIG>, in some embodiments, a single control circuit (e.g., either control circuit <NUM> or <NUM>) may be implemented, even though control bits are conveyed in both the I and Q data packets. For example, an embodiment of system <NUM> may include only control circuit <NUM>, and both de-framers <NUM> and <NUM> may be coupled to the single control circuit <NUM>. In another embodiment, system <NUM> may include only control circuit <NUM>, and both de-framers <NUM> and <NUM> may be coupled to the single control circuit <NUM>. In either of these two embodiments, the control circuit <NUM> or <NUM> may combine control bits extracted from corresponding, time-aligned I and Q data packets into a multi-bit control signal.

In addition to extracting the control bit(s), when each data sample includes data from multiple data packets (e.g., the length of a data sample, N, is <NUM> bits, and the length of each data packet, M, is <NUM> bits), each de-framer <NUM>, <NUM> reconstructs each data sample from the data bits within multiple (e.g., two or more) consecutive I or Q data packets. For example, referring again to <FIG>, each de-framer <NUM>, <NUM> may combine the <NUM> data bits from reconstructed data packets <NUM>, <NUM> (e.g., bits S0-S14) into a reconstructed data sample that should be identical to data sample <NUM>.

The de-framers <NUM>, <NUM> provide the reconstructed I and Q data samples to digital-to-analog converters <NUM>, <NUM> (DACs), respectively. As discussed previously, each DAC <NUM>, <NUM> then performs a digital-to-analog conversion on each received sample, and the resulting analog samples are filtered (e.g., by LPFs <NUM>, <NUM>). Oscillator <NUM> produces an RF sinusoidal signal that is used to upconvert (to RF) the analog I and Q sample streams produced by DACs <NUM>, <NUM> and LPFs <NUM>, <NUM>. The filtered, analog I sample stream is mixed, using mixer <NUM>, with the RF signal, and the filtered, analog Q sample stream is mixed, using mixer <NUM>, with a <NUM> degree delayed version of the RF signal in order to re-align the upconverted I and Q sample streams in time. Combiner <NUM> then combines the two sample streams and provides a single RF signal <NUM> to the power amplifier <NUM>.

As mentioned above, the power amplifier <NUM> may include one or more externally controllable sub-circuits (e.g., circuits <NUM>, <NUM>, <FIG>, <FIG>), the operation of which is controlled using the control bit(s) extracted from the I or Q serialized data streams by de-framers <NUM>, <NUM> and provided to control circuits <NUM>, <NUM>. According to an embodiment, each control circuit <NUM>, <NUM> converts the received control bit(s) to control signals (e.g., TTL signals with low and high logic levels). In some embodiments, the control circuits <NUM>, <NUM> may include logic circuits configured to perform the conversion, and in other embodiments, each control circuit <NUM>, <NUM> may include a look-up table (LUT), which correlates control bit values to control signal characteristics. In the latter embodiment, each control circuit <NUM>, <NUM> may include additional circuitry to produce the control signals with the signal characteristics that are associated (e.g., in the LUT) with the control bit values. Either way, each control circuit <NUM>, <NUM> sends the control signals <NUM>, <NUM> to the power amplifier <NUM> so that the control signals are synchronized (or time-aligned) with the RF signal provided by the combiner <NUM> to the power amplifier <NUM>. According to an embodiment, each control circuit <NUM>, <NUM> may impart a programmable delay to a control signal <NUM>, <NUM> to ensure that the amplifier <NUM> performs a desired operation (as controlled by the control signals <NUM>, <NUM>) simultaneously with amplifying the converted I and/or Q sample(s) from which the associated control bit(s) were extracted. The programmable delay should substantially equal the cumulative sample processing delays through the DACs <NUM>, <NUM>, LPFs <NUM>, <NUM>, mixers <NUM>, <NUM>, combiner <NUM>, and portions of amplifier <NUM> that precede the point(s) at which the amplifier control circuit (e.g., switch <NUM>, <FIG> or variable phase shifters/attenuators <NUM>-<NUM>) is tied into the transmit path. In some systems, this cumulative sample processing delay may be substantially fixed, and accordingly the programmable delay may be a substantially fixed value. In other systems, this cumulative sample processing delay may be variable but determinable (e.g., using a feedback circuit, not shown, between the amplifier <NUM> and the DFE <NUM>, for example), and accordingly the programmable delay may be a dynamic variable value. Either way, upon amplification of the RF signal by power amplifier <NUM>, the amplified RF signal is provided to antenna <NUM> for radiation over the air interface.

As mentioned above, the power amplifier <NUM> includes one or more externally controllable sub-circuits, the operation of which is controlled using the control bit(s) received in the I or Q serialized data streams. For example, <FIG> is a simplified block diagram of a Doherty power amplifier <NUM> with an externally controllable sub-circuit <NUM> that is operated based on the values of the control bit(s) received in the I or Q serialized data streams, in accordance with an example embodiment.

More specifically, Doherty amplifier <NUM> (e.g., amplifier <NUM>, <FIG>, <FIG>) includes an input terminal <NUM>, a power splitter <NUM>, a carrier amplifier path <NUM>, a peaking amplifier path <NUM>, a summing node <NUM>, an externally controllable sub-circuit <NUM>, and an output terminal <NUM>. The power splitter <NUM> is coupled both to the carrier amplifier path <NUM> and to the peaking amplifier path <NUM>, and is configured to divide an input signal (RF-IN, which is characterized by an instantaneous voltage of Vin) (e.g., signal <NUM>, <FIG>) received at input terminal <NUM> into a carrier RF signal and a peaking RF signal. More specifically, the outputs of power splitter <NUM> are connected to carrier amplifier <NUM> (also referred to as a main amplifier) and to peaking amplifier <NUM>. Impedance matching networks or circuits (not illustrated) may be included along the signal transmission paths between the outputs of power splitter <NUM> and the inputs to the carrier and peaking amplifiers <NUM>, <NUM>. To ensure proper Doherty operation, the carrier amplifier <NUM> along the carrier amplifier path <NUM> is biased to operate in Class-AB, and the peaking amplifier <NUM> along the peaking amplifier path <NUM> is biased to operate in Class-C.

In the illustrated embodiment, Doherty amplifier <NUM> has a "non-inverted" Doherty configuration, in which an impedance inverter and/or a λ/<NUM> (<NUM> degree) phase shift element <NUM> is connected between the output of carrier amplifier <NUM> and the summing node <NUM>. The output of peaking amplifier <NUM> also is connected to the summing node <NUM>. The phase shift introduced by element <NUM> is, in some implementations, compensated by a <NUM> degree relative phase shift present on path <NUM> introduced by phase shift element <NUM>, which is present between the power splitter <NUM> and the input to the peaking amplifier <NUM>. In an alternate embodiment, amplifier <NUM> may have an "inverted" Doherty configuration. In such a configuration, the impedance inverter and/or λ/<NUM> line phase shift element <NUM> instead is connected between the output of peaking amplifier <NUM> and the summing node <NUM>, rather than being connected between the output of carrier amplifier <NUM> and the summing node <NUM>. In addition, in an inverted Doherty implementation, the phase shift introduced by element <NUM> between the output of the peaking amplifier <NUM> and the summing node <NUM> can be compensated by a <NUM> degree relative phase shift present on path <NUM> (e.g., between power splitter <NUM> and the input to the carrier amplifier <NUM>), rather than on path <NUM>. An impedance transformation network <NUM> between summing node <NUM> and the amplifier output <NUM> functions to present the proper load impedances to each of carrier amplifier <NUM> and peaking amplifier <NUM>, and outputs the combined signal produced at summing node <NUM> to the output terminal <NUM> as an output signal (RF-OUT). The output signal, RF-OUT, in turn, may be provided to an antenna (e.g., antenna <NUM>, <FIG>, <FIG>), for radiation over the air interface.

The operation of a Doherty amplifier is based on well-known first order concepts where the carrier amplifier <NUM> and peaking amplifier <NUM> are modeled as current sources when not saturated, and voltage sources when saturated. The Doherty amplifier operational concept is illustrated in <FIG>, which are graphs depicting the operation of an idealized Doherty amplifier, a conventional Doherty amplifier, and the Doherty amplifier depicted in <FIG>. Each graph shows data for the carrier amplifier and peaking amplifier of the Doherty amplifier. In <FIG>, line <NUM> shows the voltage for the carrier amplifier, and line <NUM> shows voltage for the peaking amplifier of an idealized Doherty amplifier. In <FIG>, line <NUM> shows the current for the carrier amplifier, and line <NUM> shows the current for the peaking amplifier of an idealized Doherty amplifier. In both graphs, the voltage and current values have been normalized around the value of <NUM>.

At low input power levels, the peaking amplifier is non-conducting due to the Class-C bias of peaking amplifier. As such, all amplification generated by the amplifier is achieved using only the carrier amplifier. With increasing input power levels (e.g., increasing levels of Vin), a point is reached (i.e., transition point α as labeled on both <FIG>) where the radio frequency (RF) input signal is sufficiently large such that the carrier amplifier is at the onset of saturation and produces a consistent RF output voltage of <NUM> V (normalized) (see the horizontal portion of line <NUM> of <FIG>). When saturated, the carrier amplifier can be represented and modeled by first order principles as a voltage source such that with further increases in input power, Vcarrier remains at unity (normalized). Due to impedance inverters <NUM> and <NUM> (shown in <FIG>), voltage Vpeaking is less than unity. With further increases in input power, the operation of the carrier amplifier and the peaking amplifier moves beyond the point α. The carrier amplifier begins to conduct and contribute current, Ipeaking, which has the effect of modulating the impedance seen by the carrier amplifier. This further allows the carrier amplifier to contribute additional RF current. Under full drive conditions where Vin/Vin_max equals unity, both the carrier amplifier and the peaking amplifier are saturated and producing maximum power.

In reality, the peaking amplifier is not an ideal voltage and current source. Ipeaking does not transition abruptly from zero to above zero as Vin/Vin_max transitions from below α to above α due to the Class-C operation of the peaking amplifier. In other words, the sharp corners in lines <NUM>, <NUM>, <NUM>, and <NUM> at transition point α of <FIG> do not accurately depict the operation of a real Doherty amplifier. In practice, the responses are more gradual for both Ipeaking and Vcarrier.

Dashed lines <NUM> and <NUM> represent the actual voltage and current curves of a conventional Doherty amplifier about transition point α. As seen in <FIG>, about transition point α the voltage of the carrier amplifier (depicted by line <NUM>) does not sharply transition from increasing to reaching a maximum value of <NUM> V. Instead, as shown by dashed line <NUM>, the transition is gradual. As such, in a real amplifier, even at some power output level greater than that of transition point α, the carrier amplifier has still not reached full saturation, again, in contradiction to the idealized model. Similarly, as seen in <FIG>, the current of the peaking amplifier (depicted by line <NUM>) does not sharply transition when the peaking amplifier begins conducting near transition point α. Instead, as shown by dashed line <NUM>, the transition is gradual. As such, in a real amplifier, even at some power output less than that of transition point α, the peaking amplifier is already conducting, in contradiction to the idealized model. These effects may be deleterious on the overall Doherty efficiency about transition operating point α.

By incorporating switch <NUM> into the Doherty amplifier <NUM> and controlling the variable resistance of switch <NUM> according to the methods described below, the performance of Doherty amplifier <NUM> can be made to more closely approximate that of an ideal amplifier in comparison to conventional devices.

In the embodiment of <FIG>, externally controllable sub-circuit <NUM> includes a resistive switch <NUM>, which is connected to peaking path <NUM> in a shunt configuration. In various implementations, the resistive switch <NUM> may include one or more transistors, for example, P-high-electron-mobility transistors (pHemts) that may be manufactured using gallium arsenide (GaAs), FETs (Field Effect Transistors) using silicon-on-insulator technologies, or other types of transistors. In one implementation, the resistive switch <NUM> is a circuit element having two terminals having an adjustable resistance between the two terminals. An analog control input <NUM> receives an analog control signal (e.g., from one of control circuits <NUM>, <NUM>, <FIG>, <FIG>), which is configured to control the resistance between the two terminals.

In the illustrated embodiment, a first current carrying terminal of switch <NUM> is connected to peaking path <NUM> between an output of power splitter <NUM> and an input of peaking amplifier <NUM>. A second current carrying terminal of switch <NUM> is connected to a voltage reference (e.g., Vdd or ground), for example through a ground voltage node. Switch <NUM> includes a control input <NUM> for receiving an analog control signal, Vcontrol. According to an embodiment, analog control input <NUM> may be coupled to a control circuit (e.g., control circuit <NUM> or <NUM>, <FIG>, <FIG>), which produces the analog control signal (e.g., signal <NUM> or <NUM>, <FIG>,<FIG>), and the voltage of the control signal sets switch <NUM> to a desired resistance level between the current carrying terminals. In this manner, operation of the externally controllable sub-circuit <NUM> may be modified based on the analog control signal provided by the control circuit (e.g., control circuit <NUM> or <NUM>, <FIG>, <FIG>).

In one implementation, switch <NUM> may be binary, and thus controlled to be in a first or second state based on the voltage, Vcontrol, of the control signal present at the control input <NUM>. For example, a first input value or voltage at input <NUM> may configure switch <NUM> in a low resistance or conductive state (i.e., a "closed" state with relatively low resistance between the current carrying terminals), and a second input value or voltage at input <NUM> may configure switch <NUM> in a high resistance or non-conductive state (i.e., an "open" state with a relatively high resistance between the current carrying terminals). Alternatively, the input, Vcontrol, at input <NUM> of switch <NUM> may be analog. In that case, the resistance of switch <NUM> may be set in response to Vcontrol being set to a particular analog voltage value. The analog voltage value may then be mapped by switch <NUM> to a particular resistance value. In still other implementations, switch <NUM> may be configurable to a plurality of different resistances, where the Vcontrol at input <NUM> of switch <NUM> may be one of a plurality of values to select a particular one of those different resistances.

In the embodiment of Doherty amplifier <NUM> depicted in <FIG>, the RF voltage at the input of the peaking amplifier <NUM> is modulated using the variable resistance or resistive switch element <NUM>. This modulation controls the operation of the peaking amplifier and may improve overall efficiency of the Doherty amplifier <NUM>. Referring again to <FIG>, curves <NUM> and <NUM> represent the voltage and current curves about transition point α of a Doherty amplifier configured in accordance with <FIG>. As seen in <FIG>, in the amplifier <NUM> incorporating switch <NUM>, the carrier amplifier <NUM> reaches saturation voltage at a reduced output beyond transition point α as compared to a conventional device (see line <NUM>). Similarly, with regards to <FIG>, in the amplifier <NUM> incorporating switch <NUM>, the peaking amplifier <NUM> begins conducting at a greater input power level as compared to a conventional device (see line <NUM>). These two attributes of the Doherty amplifier <NUM> may realize a more ideal and more efficient Doherty power amplifier by enhancing the effective turn-on characteristics of the peaking amplifier <NUM>. More specifically, as is illustrated in <FIG>, by incorporating switch <NUM> into the Doherty amplifier <NUM> and controlling the variable resistance of switch <NUM> according to the methods described herein, the performance of Doherty amplifier <NUM> can be made to more closely approximate that of an ideal amplifier in comparison to conventional devices.

In one implementation, for input signal levels of RF-IN less than the signal levels corresponding to threshold value α, the control signal, Vcontrol, provided at input <NUM> of switch <NUM> causes switch <NUM> to be set to a low resistance in order to shunt RF signal energy present on the peaking amplifier path <NUM> to ground, and thus to prevent the Class-C biased peaking amplifier <NUM> turning on and conducting current. Specifically, the RF voltage present at the input to the peaking amplifier <NUM> is reduced when switch <NUM> is set to a low resistance, thereby keeping the peaking amplifier in a non-conducting state. The equivalent resistance of the resistive switch <NUM> in this state need not be close to zero ohms, and in fact, a value greater than zero ohms may be utilized so as to limit RF voltage standing wave ratio (VSWR) mismatch effects due to the switching action. Hence, the resistive switch <NUM> is operated as a resistive element, switching between two resistance values or states where the lower resistance value may be in the <NUM>'s of ohms (e.g., between about <NUM> ohms and about <NUM> ohms or more), and the high resistance value may be several orders of magnitude larger (e.g., between about <NUM> ohms to about <NUM> ohms or more). This allows carrier amplifier <NUM> to approach its saturation voltage without interference from peaking amplifier <NUM>, resulting in higher Doherty efficiency at transition point α. Conversely, as the input signal levels grow greater than α, at which point carrier amplifier <NUM> is saturated, the control signal, Vcontrol, provided at input <NUM> of switch <NUM> causes switch <NUM> to be set to a relatively high resistance, allowing peaking amplifier <NUM> to begin operating.

Generally, when transitioning from a low resistance to a high resistance, the control signal, Vcontrol, provided at input <NUM> may cause switch <NUM> to make the transition over a relatively small transition voltage range. For example, the voltage transition range may be between about <NUM>% and about <NUM>% of Vin_max. As the resistance of switch <NUM> increases, peaking amplifier <NUM> observes an increasing magnitude of the input signal at the input of peaking amplifier <NUM> and begins conducting. The transition of resistance of switch <NUM> from low to high over a relatively small transition voltage may result in a smooth, but relatively abrupt turn-on of peaking amplifier <NUM>, thereby preserving a smooth gain response of the overall Doherty amplifier <NUM>. If, however, switch <NUM> were to change from low resistance to high resistance instantaneously or near-instantaneously, such a change in resistance could introduce transient signals into the signal path of the Doherty amplifier.

By keeping the resistance of switch <NUM> low at input levels below transition point α, the input signal to peaking amplifier <NUM> is kept small as much of the signal provided by the power splitter <NUM> to the peaking amplifier path <NUM> passes through switch <NUM> due to the low resistance of switch <NUM>. Therefore, the input signal amplitude is kept small enough to prevent peaking amplifier <NUM> from conducting before carrier amplifier <NUM> has reached saturation. At full drive conditions and when the input levels exceed the transition point α, switch <NUM> is set to a relatively high resistance, and normal Doherty operation is achieved. In one implementation, the low resistance value of switch <NUM> is greater than about <NUM> ohms and may be between about <NUM> and about <NUM> ohms. In an alternate embodiment, the low resistance value of switch <NUM> may be in a range of about <NUM> ohms to about <NUM> ohms or more. The high resistance value of switch <NUM> may be greater than <NUM>,<NUM> ohms and, in some cases, as high a resistance value as the amplifier design allows (e.g., up to about <NUM>,<NUM> ohms or more).

In the present embodiment, it is desirable that the low resistance value of switch <NUM> not be equal to, or approximately equal to, about <NUM> ohms. If the low resistance of switch <NUM> were to approximate a short circuit, when changing state (either from low to high resistance or high to low resistance), the switch <NUM> may create an undesirable transient glitch into the amplifier's complex gain response and degrade amplifier linearity. That transient may be observed in the amplifier's gain, amplitude-modulation/phase-modulation, linearity, etc. Linearity performance and amplifier linearizability (using DPD for example) is important for cellular infrastructure transmitter applications. Accordingly, the in the present system, switch <NUM>, when in its low resistance state, exhibits a resistance of at least <NUM> ohms for a <NUM> ohm system.

In some embodiments, switch <NUM> exhibits a resistance that is a function of Vin/Vin_max. <FIG> is a graph depicting a resistance of switch <NUM> versus Vin/Vin_max. As shown in <FIG>, the response of switch <NUM> is piece-wise-linear, although other functions can be used as well. At levels of Vin/Vin_max below transition point α, the resistance of switch <NUM> is set to a relatively low value. As the value of Vin/Vin_max transitions above transition point α, the resistance of switch <NUM> increases linearly over a transition range that is denoted Vtransition. At the end of the transition range, switch <NUM> is set to a relatively high (e.g., maximum) resistance. In various other implementations, the resistance of switch <NUM>, rather than being determined by the value of Vin/Vin_max may instead be a function of the amplitude of an envelope of an input signal to the Doherty amplifier. For example, when the envelope amplitude is relatively low, switch <NUM> may be set to a first resistance state (e.g., a low resistance state), and when the envelope amplitude is relatively high, switch <NUM> may be set to a second resistance state (e.g., a high resistance state).

An alternative implementation of Doherty amplifier <NUM> calls for switch <NUM> to be connected in series between power splitter <NUM> and peaking amplifier <NUM>, rather than in the shunt configuration depicted in <FIG>. More specifically, a first current carrying terminal of switch <NUM> is connected to the peaking path output of power splitter <NUM>, and a second current carrying terminal of switch <NUM> is connected to the input to the peaking amplifier <NUM>. When connected in series, switch <NUM> would exhibit the opposite resistance characteristics than those described above where switch <NUM> is in a shunt configuration. Accordingly, when switch <NUM> is coupled in series, for levels of Vin/Vin_max below transition point α, the resistance of the switch would be set to a high value, and the resistance would be controlled to decrease linearly over a transition range. At the end of the transition range, the resistance of the switch <NUM> would be set to a low (e.g., minimum) resistance value. In the series configuration, though, in contrast to the shunt configuration described above, the low resistance state may be at or near zero ohms (e.g., between about <NUM> ohms and about <NUM> ohms), while the high resistance state should be limited to a maximum higher value (e.g., between about <NUM> ohms and about <NUM> ohms or more), such as approximately <NUM> ohms to prevent VSWR mismatch effects leading to discontinuities in amplifier gain and or phase, for example.

As indicated above, Doherty amplifier <NUM> with externally controllable sub-circuit <NUM> could be utilized as amplifier <NUM> of <FIG> and <FIG>. Accordingly, the control signal <NUM> or <NUM> may correspond to the control signals provided to control input <NUM>. In other embodiments, Doherty amplifiers with additional or different externally controllable sub-circuits could be utilized for amplifier <NUM>. For example, another embodiment of a Doherty amplifier may include variable phase and/or variable amplitude circuits along the carrier and/or peaking paths <NUM>, <NUM>, and control signals <NUM>, <NUM> may provide signals to the Doherty amplifier that affect the operation of the variable phase and/or variable amplitude circuits.

For example, <FIG> is a simplified block diagram of another embodiment of a Doherty power amplifier <NUM> with an externally controllable sub-circuit <NUM> that may be operated based on the values of the control bit(s) received in the I or Q serialized data streams, in accordance with an example embodiment.

More specifically, Doherty amplifier <NUM> (e.g., amplifier <NUM>, <FIG>, <FIG>) includes an input terminal <NUM>, a power splitter <NUM>, a carrier amplifier path <NUM>, a peaking amplifier path <NUM>, a summing node <NUM>, an externally controllable sub-circuit <NUM>, and an output terminal <NUM>. The power splitter <NUM> is coupled both to the carrier amplifier path <NUM> and to the peaking amplifier path <NUM>, and is configured to divide an input signal (RF-IN) (e.g., signal <NUM>, <FIG>) received at input terminal <NUM> into a carrier RF signal and a peaking RF signal. The outputs of power splitter <NUM> are connected to carrier amplifier <NUM> and to peaking amplifier <NUM>, and impedance matching networks or circuits (not illustrated) may be included along the signal transmission paths between the outputs of power splitter <NUM> and the inputs to the carrier and peaking amplifiers <NUM>, <NUM>. To ensure proper Doherty operation, the carrier amplifier <NUM> is biased to operate in Class-AB, and the peaking amplifier <NUM> is biased to operate in Class-C.

In the illustrated embodiment, Doherty amplifier <NUM> has a "non-inverted" Doherty configuration, as described above, and in which an impedance inverter and/or a λ/<NUM> (<NUM> degree) phase shift element <NUM> is connected between the output of carrier amplifier <NUM> and the summing node <NUM>. The output of peaking amplifier <NUM> also is connected to the summing node <NUM>. The phase shift introduced by element <NUM> is, in some implementations, compensated by a <NUM> degree relative phase shift present on path <NUM> introduced by phase shift element <NUM>, which is present between the power splitter <NUM> and the input to the peaking amplifier <NUM>. In an alternate embodiment, amplifier <NUM> may have an "inverted" Doherty configuration, as described above in conjunction with <FIG>. An impedance transformation network <NUM> between summing node <NUM> and the amplifier output <NUM> functions to present the proper load impedances to each of carrier amplifier <NUM> and peaking amplifier <NUM>, and outputs the combined signal produced at summing node <NUM> to the output terminal <NUM> as an output signal (RF-OUT). The output signal, RF-OUT, in turn, may be provided to an antenna (e.g., antenna <NUM>, <FIG>, <FIG>), for radiation over the air interface.

Doherty amplifier <NUM> also includes an externally controllable sub-circuit <NUM>. Sub-circuit <NUM> specifically includes any one or more of a first variable phase shifter <NUM> and/or a first variable attenuator <NUM> disposed along the carrier amplification path <NUM> between the power splitter <NUM> and the input to the carrier amplifier <NUM>, and a second variable phase shifter <NUM> and/or a second variable attenuator <NUM> disposed along the peaking amplification path <NUM> between the power splitter <NUM> and the input to the peaking amplifier <NUM>. Each of the variable phase shifters <NUM>, <NUM> may be controlled, by controller <NUM>, to apply one of a plurality of phase shifts to the carrier RF signal or the peaking RF signal, respectively. Similarly, each of the variable attenuators <NUM>, <NUM> may be controlled, by controller <NUM>, to attenuate the carrier RF signal or the peaking RF signal, respectively, by one of a plurality of attenuation levels.

Controller <NUM> includes a control input <NUM> for receiving a digital control signal, Dcontrol, which may be a single-bit or multi-bit value. The value of Dcontrol may specifically indicate one of a plurality of phase shift and/or attenuation settings (or a combination of settings) for the variable phase shifters <NUM>, <NUM> and/or the variable attenuators <NUM>, <NUM>. According to an embodiment, digital control input <NUM> may be coupled to a control circuit (e.g., control circuit <NUM> or <NUM>, <FIG>, <FIG>), which produces the control signal (e.g., signal <NUM> or <NUM>, <FIG>, <FIG>), and the controller <NUM> determines a phase shift and/or attenuation level to be applied by one or more of the variable phase shifters <NUM>, <NUM> or the variable attenuators <NUM>, <NUM> based on the digital value of the control signal. In this manner, operation of the externally controllable sub-circuit <NUM> may be modified based on the digital control signal provided by the control circuit (e.g., control circuit <NUM> or <NUM>, <FIG>, <FIG>). Although two example amplifiers with controllable sub-circuits are illustrated and described in conjunction with <FIG>, in still other embodiments, other types of amplifiers that include other types of externally controllable sub-circuits also could be used for amplifier <NUM> (<FIG>, <FIG>).

<FIG> is a flowchart of a method for communicating data and control signals over a serial link between a digital data processor (e.g., DFE <NUM>, <FIG>, <FIG>), a digital-to-analog converter (e.g., DAC <NUM>, <NUM>, <FIG>, <FIG>), and an amplifier (e.g., amplifier <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>, <FIG>) of an RF transmitter lineup, in accordance with an example embodiment. In block <NUM>, a digital data processor (e.g., transmit processor <NUM>, <FIG>) produces a plurality of digital data samples (e.g., I and/or Q samples) and one or more control bits. In block <NUM>, the digital data sample and the one or more control bits are combined by one or more serialized transmit interfaces (e.g., interface <NUM>-I and/or <NUM>-Q, <FIG>, <FIG>) into one or more data packets. In block <NUM>, the serialized transmit interface sends the one or more data packets over a signal line (e.g., one of signal lines <NUM>, <FIG>, <FIG>) or a signal lane (e.g., including both of signal lines <NUM>) as one or more transmitted data packets.

On the receive side, one or more serialized receive interfaces (e.g., interface <NUM>-I and/or <NUM>-Q, <FIG>, <FIG>) receive the one or more transmitted data packets from the signal line (or signal lane), in block <NUM>. The serialized receive interface(s) then produce one or more reconstructed digital data samples from the one or more transmitted data packets. Further, and according to an embodiment, the serialized receive interface(s) also produce the one or more control bits from the one or more transmitted data packets. In block <NUM>, one or more control circuits (e.g., control circuits <NUM>, <NUM>, <FIG>, <FIG>) produce one or more analog and/or digital control signals from the one or more control bits produced by the serialized receive interface.

In block <NUM>, a converter circuit (e.g., including DACs <NUM>, <NUM>, LPFs <NUM>, <NUM>, mixers <NUM>, <NUM>, and combiner <NUM>, <FIG>, <FIG>) produce an RF input signal (e.g., signal <NUM>, <FIG>) by performing a digital-to-analog conversion of the reconstructed digital data sample to produce an analog data sample signal, and upconverting the analog data sample signal to RF. Finally, in block <NUM>, a power amplifier (e.g., PA <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>, <FIG>) amplifies the RF input signal. As described previously, the power amplifier includes a sub-circuit (e.g., sub-circuit <NUM>, <NUM>, <FIG>, <FIG>) that is controllable based on the control signal produced by the control circuit. According to an embodiment, the power amplifier modifies operation of the sub-circuit based on the control signal.

Although embodiments of the inventive subject matter described above and illustrated in the drawings include receiver circuitry with a digital-to-analog converter that converts received digital data samples to an analog signal, which is coupled to a power amplifier with a sub-circuit that is controllable based on received control bits, the inventive subject matter may be applied in other types of systems, as well. More generally, the inventive subject matter includes encapsulating (e.g., combining in one or more data packets) control bits with digital data samples, so that, when the combined control bits and digital data samples are conveyed through a communications link (e.g., a signal line or lane) with a variable delay, the control bits and digital data samples remain synchronous (i.e., time-aligned with each other) all the way to the receiver circuitry. As discussed in detail above, the control bits are inserted in the data packets into bits that otherwise are unused (i.e., not filled with data bits). On the receive side of the system, utilization and/or processing of the control bits and the digital data samples is application specific. Accordingly, although some embodiments include applications associated with a receiver that includes a digital-to-analog converter that produces an analog signal from the received digital data samples, and the resulting analog signal is upconverted to an RF signal that is amplified by a power amplifier (e.g., where an aspect of the amplification is affected by the received control bits), other embodiments may include receiver circuitry other than a digital-to-analog converter (i.e., a digital device other than a digital-to-analog converter), and/or applications other than RF amplification. In other words, how the control bits and digital data samples are utilized and processed on the receive side of the system is application specific, and is not limited to receiver circuitry that includes a digital-to-analog converter or an RF power amplifier. Further still, although some embodiments discussed above and illustrated in the drawings are associated with communication systems that transmit/receive RF signals over an air interface utilizing antennas, in other embodiments, the communication medium may include physical transmission media such as electrical cables, optical fiber, and so on, instead of an air interface.

The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).

The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.

Claim 1:
A communication system comprising:
a digital data processor (<NUM>) configured to produce a digital data sample and one or more control bits;
a serialized transmit interface (<NUM>-I, <NUM>-Q) coupled to the digital data processor and to a first end of a signal line, wherein the serialized transmit interface is configured to
combine the digital data sample and the one or more control bits into one or more data packets, and
send the one or more data packets over the signal line as one or more transmitted data packets;
a serialized receive interface (<NUM>-I, <NUM>-Q) coupled a second end of the signal line, wherein the serialized receive interface is configured to
receive the one or more transmitted data packets from the signal line,
produce a reconstructed digital data sample from the one or more transmitted data packets, and
produce the one or more control bits from the one or more transmitted data packets;
a converter circuit (<NUM>, <NUM>) configured to produce a radio frequency, RF, input signal by performing a digital-to-analog conversion of the reconstructed digital data sample to produce an analog data sample signal, and upconverting the analog data sample signal to RF;
a power amplifier (<NUM>);
a control circuit (<NUM>) coupled to the serialized receive interface, and configured to produce a control signal from the one or more control bits provided by the serialized receive interface and send the control signal to the power amplifier (<NUM>) such that the control signal is time-aligned with the RF input signal;
wherein the power amplifier (<NUM>) includes a sub-circuit that is controllable based on the control signal produced by the control circuit, and the power amplifier is configured to amplify the RF input signal, and to modify operation of the sub-circuit based on the control signal.