Patent Description:
Embodiments of the present description generally relate to the field of integrated circuit assemblies and, more particularly, to the integration of thermal interface structures for the removal of heat from optical communication devices.

The integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit devices for use in various server and mobile electronic products, including, but not limited to, computer server products and portable products, such as wearable integrated circuit systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.

As these goals are achieved, the integrated circuit devices become smaller. However, communication demands have been increasing considerably faster than scaling (e.g., Moore's law) can achieve. For example, machine intelligence systems are requiring core counts in the thousands, "near compute" memory of greater than <NUM> gigabytes, connectivity bandwidth of greater than one terabyte per second between multiple nodes, low latency, thermal control, and good manufacturability, as will be understood to those skilled in the art. Of course, signal loss significantly increases with metal conductive routes (used for electrical interconnects) as signaling frequency increases and distance between the integrated circuit devices increases. Furthermore, the routing of the conductive routes becomes increasingly complex as more integrated circuit devices are added to an integrated circuit package. Thus, optical interconnects are being used to replace electrical interconnects, as optical interconnects offer very high bandwidths compared to electrical interconnects. As will be understood to those skilled in the art, photonic integrated circuit devices are used to convert electrical signals to optical signals. As will be further understood, photonic integrated circuit devices may have lasing components, amplifiers, and/or other electrical circuits which generate significant power densities (e.g., about <NUM> to <NUM> watts per square millimeter compared to a processing or computing device which may have power densities of about <NUM> to <NUM> watts per square millimeter, depending on use condition). Furthermore, optical components, such as lasers, can typically only tolerate a maximum temperature of between about <NUM> and <NUM> degrees Celsius compared to the maximum junction temperatures on processing or computing devices of between about <NUM> to <NUM> degrees Celsius.

Ordinarily, heat is removed with a heat dissipation device, such as an integrated heat spreader, a heat sink, a heat pipe, a thermoelectric cooler, a cold plate, and the like, thermally attached with thermal interface materials to the integrated circuit devices within the integrated may be greases, gels, pads, films, and the like, with a high loading of thermally conductive filler materials, such as metal and/or ceramic particles. However, such thermal interface materials may not be compatible with photonic integrated circuit devices. For example, with silicon photonic integrated circuit devices, particularly those with thin buried oxide layers, the silicon substrate, from which the device is made, must be thinned in order to remove silicon in areas where optical waveguides are located to ensure that the optical beam stays in the waveguide and does not couple with the silicon substrate, as will be understood to those skilled in the art. As previously discussed, the silicon photonic integrated circuit devices need to be thermally coupled to the heat dissipation device in order to maintain an acceptable operating temperature. The required thinning of the silicon photonic integrated circuit devices will bring the thermal interface materials into close proximity with the waveguides of the silicon photonic integrated circuit devices. However, the thermally conductive fillers in the thermal interface materials will absorb, scatter, and/or couple the light from the waveguides, resulting in significant waveguide insertion loss and sometimes even "optical blindness" where no light comes out of the waveguide at all. Although, one could limit the contact area of the thermal interface material and the silicon photonic integrated circuit device, such as at a periphery thereof, this will constrain the heat flow path and result in lower cooling efficiency. Thus, cooling photonic integrated circuit devices is a significant challenge. <CIT> describes an optical circuit board including a top face, a bottom face, an optical layer buried between bottom and top faces, the optical layer being adapted to transmit optical signals, an opto-electronic component adapted to emit or receive light transmitted through the optical layer, a solid heat dissipative element adapted to dissipate heat generated at the opto-electronic component. <CIT> describes an asymmetric thermo-optical device comprising a waveguiding structure which comprises at least one input light path and a first output light path and a second output light path, the second output light path having a smaller width than the first output light path, and the first output light path being provided with a first heating element, wherein the second output light path is provided with a second heating element. In a preferred embodiment of the invention the second heating element is connected to a capacitor which is connected in parallel with the first heating element. <CIT> describes a tunable optical waveguide chip for optical transforms. Roughly described, the chip includes a planar waveguide having a lens region and a plurality of individually addressable energy applicators distributed transversely across an optical path through the lens region. By individually controlling the energy applied to each of the energy applicators, a desired index of refraction profile can be induced in the lens region transversely across the optical path for performing any of a variety of optical transforms. The device may include an upstream AWG which focus a wavelength de-multiplexed signal on a focal plane within the lens region. The applicators may be thermo-optic or electro-optic, for example. <CIT> describes a device for variable attenuation of an optical channel which includes an elongated core surrounded by a cladding. Optical energy propagating along the longitudinal axis of the core is normally confined thereto by the difference in refractive indices between the core and cladding. The thermo-optic coefficients of the core and cladding are closely matched such that waveguide confinement is substantially invariant with respect to ambient temperature. The device further includes a thermal source arranged above the core. The thermal source is operable to generate a temperature gradient of controllable magnitude along a vertical axis extending through the core. The temperature gradient causes reduction of the local refractive index within the core relative to surrounding regions of the cladding such that a portion of the optical energy is deflected away from the thermal source and extracted from the core. <CIT> describes an optical semiconductor element which comprises a substrate, an optical waveguide structure including an optical waveguiding layer and a cladding part formed above the substrate; a heater thermally connected to the optical waveguide structure; conductor wiring electrically connected to the heater; and an electrode pad electrically connected to the conductor wiring. The conductor wiring has a small structure such that a portion positioned in the vicinity of the heater has a cross sectional area smaller than a cross sectional area of a portion positioned close to the electrode pad. <CIT> describes an apparatus comprising a photonic integrated circuit device, a thermal interface material and a heat dissipation device. The invention is set forth in independent claim <NUM>. Embodiments of the invention described in the dependent claims.

The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings, the invention being defined by the claims. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:.

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "over" or "on" another layer or bonded "to" another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.

The term "package" generally refers to a self-contained carrier of one or more dice, where the dice are attached to the package substrate, and may be encapsulated for protection, with integrated or wire-bonded interconnects between the dice and leads, pins or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing a specific function. The package is usually mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.

Here, the term "cored" generally refers to a substrate of an integrated circuit package built upon a board, card or wafer comprising a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.

Here, the term "coreless" generally refers to a substrate of an integrated circuit package having no core. The lack of a core allows for higher-density package architectures, as the through-vias have relatively large dimensions and pitch compared to high-density interconnects.

Here, the term "land side", if used herein, generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side", which is the side of the substrate of the integrated circuit package to which the die or dice are attached.

Here, the term "dielectric" generally refers to any number of non-electrically conductive materials that make up the structure of a package substrate. For purposes of this disclosure, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.

Here, the term "metallization" generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.

Here, the term "bond pad" generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dies. The term "solder pad" may be occasionally substituted for "bond pad" and carries the same meaning.

Here, the term "solder bump" generally refers to a solder layer formed on a bond pad. The solder layer typically has a round shape, hence the term "solder bump".

Here, the term "substrate" generally refers to a planar platform comprising dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies on a single platform, with encapsulation of the one or more IC dies by a moldable dielectric material. The substrate generally comprises solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the "die side", comprises solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the "land side", comprises solder bumps for bonding the package to a printed circuit board.

Here, the term "assembly" generally refers to a grouping of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, where the parts may be removable. In another instance, the parts may be permanently bonded together. In some instances, the parts are integrated together.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The vertical orientation is in the z-direction and it is understood that recitations of "top", "bottom", "above" and "below" refer to relative positions in the z-dimension with the usual meaning. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).

Views labeled "cross-sectional", "profile" and "plan" correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

Embodiments of the present description relate to the removal of heat from a silicon photonic integrated circuit device, wherein the removal of heat is facilitated with an optically compatible thermal interface structure thereon. The thermal interface structures may comprise stack-up designs, including an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature thereof.

<FIG> illustrates an electronic assembly <NUM>, such as an integrated circuit package. The electronic assembly <NUM> may include at least one silicon photonic integrated circuit device <NUM> electrically attached to a package substrate <NUM>, wherein each silicon photonic integrated circuit device <NUM> may have an optical communication cable <NUM>, such as an optic fiber cable, attached thereto. The package substrate <NUM> may be any appropriate structure, including, but not limited to, an interposer. The package substrate <NUM> may have a first surface <NUM>, an opposing second surface <NUM>, and at least one side <NUM> extending between the first surface <NUM> and the second surface <NUM>. As illustrated, the silicon photonic integrated circuit devices <NUM> may be attached proximate the side(s) <NUM> of the package substrate <NUM> to allow for easier attachment access for the optical communication cable <NUM>.

As further shown in <FIG>, a plurality of additional integrated circuit devices <NUM>, <NUM>, and <NUM> may also be electrically attached to the package substrate <NUM>. Each of the additional integrated circuit devices <NUM>, <NUM>, and <NUM> may be any appropriate device, including, but not limited to, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, a transceiver device, an input/output device, combinations thereof, stacks thereof, or the like. In a specific embodiment, integrated circuit device(s) <NUM> may be input/output control hubs (such as electronic integrated chips), integrated circuit device(s) <NUM> may be processing units, and integrated circuit device(s) <NUM> may be cache memory devices.

In one embodiment of the present description, at least one of the integrated circuit devices <NUM>, <NUM>, <NUM>, and <NUM> may be electrically attached to the package substrate <NUM> in a configuration generally known as a flip-chip or controlled collapse chip connection ("C4") configuration. In another embodiment of the present description (not shown), the silicon photonic integrated circuit devices <NUM> may be electrically attached to the package substrate <NUM> in an "open cavity" configuration, wherein the silicon photonic integrated circuit devices <NUM> are at least partially embedded in the package substrate <NUM> that allows for direct attachment of the silicon photonic integrated circuit devices <NUM> to electronic integrated chips <NUM> (a controller for the silicon photonic integrated circuit devices <NUM>) for better power efficiency and allows for less obstructed access to the silicon photonic integrated circuit device for the attachment of the optical communication cables <NUM>.

The package substrate <NUM> may comprise a plurality of dielectric material layers (not shown), which may include build-up films and/or solder resist layers, and may be composed of an appropriate dielectric material, including, but not limited to, bismaleimide triazine resin, fire retardant grade <NUM> material, polyimide material, silica filled epoxy material, glass reinforced epoxy material, low temperature co-fired ceramic materials, and the like, as well as low-k and ultra low-k dielectrics (dielectric constants less than about <NUM>), including, but not limited to, carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymeric dielectrics, fluoropolymers, and the like.

The package substrate <NUM> may further include conductive routes or "metallization" (not shown) extending through the package substrate <NUM> for the interconnection of the integrated circuit devices <NUM>, <NUM>, <NUM>, and <NUM> and/or for the interconnection of the package substrate <NUM> to an external board (not shown). These conductive routes (not shown) may be a combination of conductive traces (not shown) formed between the dielectric material layers (not shown) and conductive vias (not shown) extending through the dielectric material layers (not shown). The structure and fabrication of conductive traces and conductive vias are well known in the art and are not shown or described for purposes of clarity and conciseness. The conductive traces and the conductive vias may be made of any appropriate electrically conductive material, including, but not limited to, metals, such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like. As will be understood to those skilled in the art, the package substrate <NUM> may be a cored substrate or a coreless substrate.

As shown in <FIG>, the package substrate <NUM> may include a heat dissipation device <NUM> disposed thereon, wherein the heat dissipation device <NUM> may be thermally coupled to the integrated circuit devices <NUM>, <NUM>, <NUM>, and <NUM> with one or more thermal interface materials (not shown). As previously discussed, the thermal interface materials for the "non-photonic" integrated circuit devices, such as integrated circuit devices <NUM>, <NUM>, and <NUM>, may be thermally coupled to the heat dissipation device <NUM> with standard thermal interface materials with a high loading of thermally conductive filler materials, such as metal and/or ceramic particles. However, as also previously discussed, such thermal interface materials may not be compatible with the silicon photonic integrated circuit devices <NUM>. The embodiments of the present description are directed to thermal interface structures for these photonic integrated circuit devices <NUM>.

The heat dissipation device <NUM> may comprise any appropriate thermally conductive structure, including but not limited to an integrated heat spreader, a heat sink, a heat pipe, a thermoelectric cooler, a cold plate, and the like, and may be made of any appropriate thermally conductive material, including, but not limited to, metals, such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like. In one embodiment of the present description, the heat dissipation device <NUM> may include a cut-out window or notch therein to allow for a less obstructed access to the silicon photonic integrated circuit device for the attachment of the optical communication cables <NUM>.

<FIG> illustrate side cross-sectional views of embodiments of the present description. It is noted that various processes and techniques for the electrical attachment of a photonic integrated circuit device to a package substrate is well known in the art and, thus, for the sake of clarity and conciseness will not be discussed nor will the package substrate be illustrated.

As shown in <FIG>, the silicon photonic integrated circuit device <NUM> may be formed having a first surface <NUM> and an opposing second surface <NUM>. As will be understood to those skilled in the art, the first surface <NUM> may contain active circuitry (not shown), active structures (not shown), communication structures (not shown - such as waveguides, grating couplers, and the like), interconnection structures (not shown - such as bond pads, and structures (not shown - e.g., sockets, clips, plugs and the like) for connection of the optical communication cable <NUM>. In one embodiment of the present description, the entire silicon photonic integrated circuit device <NUM> may be thinned, such as by etching, to a thickness T1 of between about <NUM> and <NUM> microns. A thermal interface structure <NUM> may then be formed on the silicon photonic integrated circuit device <NUM>. The thermal interface structure <NUM> may comprise an optical isolation structure, such as a light insulating die attach film <NUM>, a silicon heat spreader <NUM>, and a thermal interface material layer <NUM>. The light insulating die attach film <NUM> may be formed abutting the first surface <NUM> of the silicon photonic integrated circuit device <NUM>. The light insulating die attach film <NUM> may be any appropriate adhesive which does not significantly absorb, scatter, and/or couple light (photons) from the communication structures on the first surface <NUM>. In one embodiment, the light insulating die attach film <NUM> may include, but is not limited to, silicones, acrylates, epoxies, rubbers, fused silicas, acrylics, and the like. The light insulating die attach film <NUM> includes silica filler particles. When the refraction index of the light insulating die attach film <NUM> substantially matches the refraction index of the silica filler particles, the light insulating die attach film <NUM> is substantially optically transparent.

In one embodiment of the present description, the light insulating die attach film <NUM> may have a thickness T2 of between about <NUM> and <NUM> microns, but not limited thereto. The rule of thumb is that the minimum thickness T2 needs to be at least two times larger than the mode field diameter of communication structures on the first surface <NUM> in order to effectively insulate light. As will be understood to those skilled in the art, the maximum thickness T2 of the light insulation die attach film <NUM> will depend on desired parameter goals. For example, as the thermal conductivity of die attach films are typically relatively low (e.g., between about <NUM> and <NUM> watts per meter*Kelvin), a thinner film closer to <NUM> microns may result in a lower thermal resistance and may be preferred in most cases for more efficient heat removal. However, in order to accommodate larger packages and potential warpage, a thicker film of closer to <NUM> microns may be chosen to accommodate such warpage.

The silicon heat spreader <NUM> may contact the light insulating die attach film <NUM> to adhere it to the silicon photonic integrated circuit device <NUM> for improved heat removal. As the light insulating die attach film <NUM> optically isolates the first surface <NUM> of the silicon photonic integrated circuit device <NUM>, the silicon heat spreader <NUM> will not cause light absorption, scattering, and/or coupling. Furthermore, the silicon heat spreader <NUM> will have substantially the same coefficient of thermal expansion as the silicon photonic integrated circuit device <NUM> to minimize thermally induced mechanical stresses that could damage components of the silicon photonic integrated circuit device <NUM>.

The thermal interface material layer <NUM> may be disposed between the silicon heat spreader <NUM> and the heat dissipation device <NUM> for thermal coupling therebetween. As the thermal interface material layer <NUM> is between the silicon heat spreader <NUM> and the heat dissipation device <NUM>, and does not contact the silicon photonic integrated circuit device, the thermal interface material layer <NUM> may be any appropriate thermally conductive material, filled or unfilled.

As will be understood, before the assembly of the electronic assembly <NUM> (see <FIG>), the light insulative die attach film <NUM> may be pre-attached to the silicon heat spreader <NUM> for easier handling. As will be further understood, the thermal interface material layer <NUM> may be pre-attached to heat dissipation device <NUM> to eliminate a step of pick and place.

As shown in <FIG>, in one embodiment of the present description, a thermal interface structure <NUM> may comprise an optical isolation structure, such as an air gap <NUM> formed in a silicon plateau <NUM> of the silicon photonic integrated circuit device <NUM>, and a thermal interface material, such as a compliant thermal interface pad <NUM>. In an embodiment of the present description, the silicon photonic integrated circuit device <NUM> may be thinned by selective etching to form the first surface <NUM>, such that the at least one silicon plateau <NUM> extends from the first surface <NUM>. The selective etching forms the air gap <NUM> within the silicon plateau <NUM> in at least one area <NUM> where at least one waveguide is formed, and removes silicon in at least one area <NUM> where a grating coupler is formed (i.e., area for the attachment of the optical communication cable <NUM>), which results in the formation of the at least one silicon plateau <NUM>. In one embodiment of the present description, the silicon plateau <NUM> may have a thickness T3 of between about <NUM> and <NUM> microns for heat spreading. The air gap <NUM> in at least one area <NUM> (where at least one waveguide is formed) prevents light absorption, scattering, and/or coupling, as will be understood to those skilled in the art.

In an embodiment of the present description, the compliant thermal interface pad <NUM> may be disposed between the silicon plateau <NUM> of the silicon photonic integrated circuit device <NUM> and the heat dissipation device <NUM>. In one embodiment, the compliant thermal interface pad <NUM> is sufficiently conformable, resilient, and/or deformable is to reduce loading stress from the heat dissipation device <NUM> to the silicon photonic integrated circuit device <NUM>, which may damage components within the silicon photonic integrated circuit device <NUM> or even crack the silicon photonic integrated circuit device <NUM> itself. Furthermore, in an embodiment of the present description, the compliant thermal interface pad <NUM> may be sufficiently rigid to prevent it from extending too far into the air gap <NUM> over the waveguide area <NUM>. It is understood that the compliant thermal interface pad <NUM> may partially extend into the air gap <NUM>, as long as there is a distance of two times the "mode field diameter (MFD)" between the first surface <NUM> over the waveguide area <NUM> and the thermal interface pad <NUM>. In one embodiment, the compliant thermal interface pad <NUM> may include, but is not limited to, gap filler material (such as silicone rubber carrier material containing thermally conductive ceramic filler particles), thermally conductive elastomer, vertical carbon thermal interface material, and the like.

In an embodiment of the present description, as shown in <FIG>, a thermal interface structure <NUM> may be formed between the silicon photonic integrated circuit device <NUM> and the heat dissipation device <NUM>. The thermal interface structure <NUM> may comprise an optical isolation structure, such as a cladding material layer <NUM>, and a thermal interface material layer, such as a thermal interface tape <NUM>. The cladding material layer <NUM> may be formed abutting the first surface <NUM> of the silicon photonic integrated circuit device <NUM>. The cladding material layer <NUM> may be any appropriate material which does not significantly absorb, scatter, and/or couple light (photons). The cladding material layer <NUM> includes silicones, acrylates, epoxies or acrylics. In one embodiment of the present description, the cladding material layer <NUM> may be substantially transparent. In another embodiment of the present description, the cladding material layer <NUM> may have a refraction index between about <NUM> and <NUM>. In a further embodiment of the present description, the cladding material layer <NUM> may have a thickness T4 of between about <NUM> and <NUM> times the mode field diameter of connection structures, such as waveguides, within the silicon photonic integrated circuit device <NUM>.

In one embodiment of the present description, the thermal interface tape <NUM> may include, but is not limited to, gap filler material (such as silicone rubber carrier material containing thermally conductive ceramic filler particles), thermally conductive elastomer, vertical carbon thermal interface material, and the like. In another embodiment of the present description, the thermal interface tape <NUM> can be replaced by thermal grease or a polymer thermal interface material.

As will be understood, the thermal interface structure <NUM> may be pre-attached to the heat dissipation device <NUM> for easier handling, as shown in <FIG>. As will be further understood, the thermal interface structure, i.e., the combination of the cladding material layer <NUM> and the thermal interface tape <NUM> may be supplied as a stand-alone product, as shown in <FIG>. As will be further understood, the cladding material layer <NUM> may be pre-attached to the silicon photonic integrated circuit device <NUM>, as shown in <FIG>.

<FIG> illustrates an electronic or computing device <NUM> in accordance with one implementation of the present description. The computing device <NUM> may include a housing <NUM> having a board <NUM> disposed therein. The computing device <NUM> may include a number of integrated circuit components, including but not limited to a processor <NUM>, at least one communication chip 706A, 706B, volatile memory <NUM> (e.g., DRAM), non-volatile memory <NUM> (e.g., ROM), flash memory <NUM>, a graphics processor or CPU <NUM>, a digital signal processor (not shown), a crypto processor (not shown), a chipset <NUM>, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board <NUM>. In some implementations, at least one of the integrated circuit components may be a part of the processor <NUM>.

The communication chip enables wireless communications for the transfer of data to and from the computing device. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

At least one of the integrated circuit components may include an integrated circuit package, which comprises a package substrate, wherein the package substrate includes a first surface; a heat dissipation structure within the package substrate; and a photonic integrated circuit device, wherein the silicon photonic integrated circuit device is attached adjacent to the first surface of the package substrate and thermally coupled to the heat dissipation structure.

In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in <FIG>. The subject matter may be applied to other integrated circuit devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.

Claim 1:
An apparatus, comprising:
a photonic integrated circuit device (<NUM>), wherein the photonic integrated circuit device (<NUM>) has a first surface;
an optical isolation structure proximate the first surface of the photonic integrated circuit device (<NUM>);
a thermal interface material (<NUM>) on the optical isolation structure; and
a heat dissipation device (<NUM>), wherein the heat dissipation device (<NUM>) is thermally coupled to the thermal interface material (<NUM>), characterized in that
the optical isolation structure comprises a light insulating die attach film (<NUM>) selected from the group consisting of silicones, acrylates, epoxies, rubbers, fused silicas, and acrylics, or a cladding material layer selected form the group consisting of silicones, acrylates, epoxies, and acrylics, in that
the light insulating die attach film (<NUM>) comprises silica filler particles and has a refraction index substantially matching the refraction index of the silica filler particles, or in that
the optical isolation structure comprises an air gap formed in the photonic integrated circuit device (<NUM>).