Patent Description:
With developments of technology, many electrical devices can support audio playing functions. However, in some application scenarios, due to some factors (e.g., poor circuit design on a circuit board, impedance mismatch, and unstable power supply/audio data/clock signal), audio data may be lost or overflowed, and thus noise is generated e.g., during decoding, and affects user's hearing experience.

Document <CIT> describes a voice decoder.

Document <CIT> describes a voice decoding device.

Document <CIT> describes a digital audio data muting system and method.

Document <CIT> describes a game machine.

Document <CIT> describes a pulse code modulation signal processor.

Some aspects of the present disclosure are to provide an audio processor circuit according to claim <NUM> and an audio processing method according the independent method claim <NUM>. Further embodiments are set in the dependent claims <NUM>-<NUM> and <NUM>-<NUM>.

Based on the descriptions above, the audio processor circuit and the audio processing method of the present disclosure can prevent the user from hearing noise so as to improve the user's hearing experience.

The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:.

In the present disclosure, "connected" or "coupled" may refer to "electrically connected" or "electrically coupled. " "Connected" or "coupled" may also refer to operations or actions between two or more elements.

Reference is made to <FIG> is a schematic diagram illustrating an audio playing system <NUM> according to some embodiments of the present disclosure. As illustrated in <FIG>, the audio playing system <NUM> includes an electrical device D1, an audio adapter device D2, and an audio playing device D3. The audio adapter device D2 can be coupled between the electrical device D1 and the audio playing device D3.

In some embodiments, the electrical device D1 may be a cell phone, a laptop, a tablet, or other electrical apparatuses which can provide audio data. The audio adapter device D2 may be an audio dongle. The audio playing device D3 may be headphones/earphones, a speaker, or other playing apparatuses with audio playing functions.

The aforementioned implementations of the electrical device D1, the audio adapter device D2, and the audio playing device D3 are merely for illustration, and various implementations of the electrical device D1, the audio adapter device D2, and the audio playing device D3 are within the contemplated scopes of the present disclosure.

As described above, the audio adapter device D2 can be coupled between the electrical device D1 and the audio playing device D3. As illustrated in <FIG>, the electrical device D1 includes a connection portion P1, the audio adapter device D2 includes a connection portion T1 and a connection portion P2, and the audio playing device D3 includes a connection portion T2. In some embodiments, a type of the connection portion T1 corresponds to that of the connection portion P1, and a type of the connection portion T2 corresponds to that of the connection portion P2. For example, the connection portion P1 is a female connector with Type-C standard, the connection portion T1 is a male connector with Type-C standard, and the connection portion T1 can be inserted into the connection portion P1. The connection portion P2 is a headphones/earphones jack, the connection portion T2 is a headphones/earphones plug, and the connection portion T2 can be inserted into the connection portion P2.

In some embodiments, the electrical device D1 can be connected to an audio platform to receive audio data from the audio platform. Then, the electrical device D1 can output digital audio data DS to the audio adapter device D2 according to the audio data from the audio platform. In some other embodiments, the digital audio data DS is stored in the electrical device D1.

As illustrated in <FIG>, the audio adapter device D2 includes an audio processor circuit <NUM>. The audio processor circuit <NUM> can generate an output audio signal OUT according to the digital audio data DS, and provide the output audio signal OUT to an audio playing circuit <NUM> in the audio playing device D3. Then, the audio playing circuit <NUM> can play corresponding audio according to the output audio signal OUT.

Reference is made to <FIG> is a functional block diagram illustrating the audio processor circuit <NUM> according to some embodiments of the present disclosure. As illustrated in <FIG>, the audio processor circuit <NUM> includes a receiver circuit <NUM>, a storage circuit <NUM>, a digital-to-analog converter circuit <NUM>, an amplifier circuit <NUM>, a detector circuit <NUM>, and a control circuit <NUM>.

The storage circuit <NUM> is coupled to the receiver circuit <NUM>. The digital-to-analog converter circuit <NUM> is coupled to the storage circuit <NUM>. The amplifier circuit <NUM> is coupled to the digital-to-analog converter circuit <NUM>. The detector circuit <NUM> and the control circuit <NUM> are coupled to the receiver circuit <NUM>, the storage circuit <NUM>, the digital-to-analog converter circuit <NUM>, and the amplifier circuit <NUM>.

In some embodiments, the receiver circuit <NUM> may be a PHY circuit. The storage circuit <NUM> may be a register that can perform a first-in-first-out (FIFO) process. The amplifier circuit <NUM> may be an audio amplifier. The control circuit <NUM> may be a micro controller unit (MCU).

The aforementioned implementations of the receiver circuit <NUM>, the storage circuit <NUM>, the amplifier circuit <NUM>, and the control circuit <NUM> are merely for illustration, and various implementations of the storage circuit <NUM>, the amplifier circuit <NUM>, and the control circuit <NUM> are within the contemplated scopes of the present disclosure.

References are made to <FIG>. <FIG> is a flow diagram illustrating an audio processing method <NUM> according to some embodiments of the present disclosure. The audio processing method <NUM> includes operations S310, S320, S330, and S340.

In operation S310, the storage circuit <NUM> stores the digital audio data DS from the electrical device D1. For example, the receiver circuit <NUM> receives the digital audio data DS from the electrical device D1 first, and then the receiver circuit <NUM> transmits the digital audio data DS to the storage circuit <NUM> in order to store the digital audio data DS in the storage circuit <NUM>.

In operation S320, the digital-to-analog converter circuit <NUM> converts the digital audio data DS from the storage circuit <NUM> into an analog audio signal AS. For example, the digital-to-analog converter circuit <NUM> receives the digital audio data DS stored in the storage circuit <NUM> according to a clock signal CLK, and converts the received digital audio data DS into an analog form in order to generate the analog audio signal AS.

In operation S330, the amplifier circuit <NUM> provides the output audio signal OUT to the audio playing circuit <NUM> according to the analog audio signal AS. For example, the amplifier circuit <NUM> receives the analog audio signal AS and provides the output audio signal OUT to the audio playing circuit <NUM> according to the analog audio signal AS such that the audio playing device D3 can play corresponding audio according to the output audio signal OUT.

In operation S340, if an abnormal condition occurs, the amplifier circuit <NUM> is turned off such that the amplifier circuit <NUM> stops providing the output audio signal OUT to the audio playing circuit <NUM>.

Reference is made to <FIG> is a detailed flow diagram illustrating the operation S340 according to some embodiments of the present disclosure.

In operation S341, the detector circuit <NUM> detects whether a total data volume of the digital audio data DS in the storage circuit <NUM> is a multiple of a throughput or whether the total data volume of the digital audio data DS in the storage circuit <NUM> is less than an upper limit value.

If the audio processor circuit <NUM> operates normally, the total data volume of the digital audio data DS in the storage circuit <NUM> will be a multiple of the throughput, in which the throughput may be a product of a channel number and a transmission bit number. For example, if the audio playing device D3 includes two sound channels (e.g., a left sound channel and a right sound channel) and the transmission bit number of each sound channel (i.e., the transmission bit number) is <NUM> bits, the throughput is <NUM> (the product of <NUM> and <NUM>) bits. In other words, the storage circuit <NUM> receives a multiple of <NUM> bits per millisecond.

However, when an abnormal condition occurs (e.g., the electrical device D1 loses one or more bits), it will cause that the total data volume of the digital audio data DS in the storage circuit <NUM> is not a multiple of <NUM> bits.

Reference is made to <FIG> is a schematic illustrating a normal data transmission procedure and an abnormal data transmission procedure according to some embodiments of the present disclosure. For example, under the normal condition, the left sound channel corresponds to <NUM> bits, e.g., data LO-L23, and the right sound channel corresponds to <NUM> bits, e.g., data R0-R23. When the abnormal condition occurs (e.g., one or more bits are lost), it will cause sequential errors in the arrangement of the audio data. As illustrated in <FIG>, the data R1 of the right sound channel is lost, and this causes the data R0 of the right sound channel to be shifted to fill the vacancy of the data R1 of the right sound channel. However, since the data R0 of the right sound channel is shifted to an original position of the data R1 of the right sound channel, the data L23 of the left sound channel is shifted to the right sound channel. Then, the data L22 of the left sound channel is shifted to an original position of the data L23 of the left sound channel, and so on. It causes the arrangement of the data to be wrong and cause the analog audio signal AS passing through the digital-to-analog converter circuit <NUM> and the amplifier circuit <NUM> as noise.

In order to avoid affecting the user's hearing experience (e.g., to prevent the user from hearing noise), the control circuit <NUM> turns off the amplifier circuit <NUM> under a condition that the total data volume of the digital audio data DS in the storage circuit <NUM> is not a multiple of the throughput (<NUM> bits), such that the amplifier circuit <NUM> stops providing the output audio signal OUT to the audio playing circuit <NUM>. In some other embodiments, the control circuit <NUM> turns off the amplifier circuit <NUM> under a condition that the total data volume of the digital audio data DS in the storage circuit <NUM> is not a multiple of <NUM> bits for a time interval. For example, it is assumed that the digital-to-analog converter circuit <NUM> receives the digital audio data DS from the storage circuit <NUM> according to the clock signal CLK corresponding to a sampling period (e.g., <NUM> millisecond). The aforementioned time interval may be twice (e.g., <NUM> milliseconds) or more than twice (e.g., more than <NUM> milliseconds) the sampling period.

In addition, it is assumed that the digital-to-analog converter circuit <NUM> receives the digital audio data DS from the storage circuit <NUM> with a sampling period (e.g., <NUM> millisecond), the total volume per millisecond of the received data received by the storage circuit <NUM> is equal to a product of one-thousand of the sampling rate, the channel number, and the transmission bit number. Under a normal condition, the storage circuit <NUM> does not store too much data. However, when an abnormal condition occurs (e.g., the digital-to-analog converter circuit <NUM> receives the digital audio data DS from the storage circuit <NUM> abnormally), it causes the storage circuit <NUM> to store too much data. That is, the total data volume of the audio data stored in storage circuit <NUM> are overflowed. Accordingly, the control circuit <NUM> turns off the amplifier circuit <NUM> under a condition that the total data volume of the digital audio data DS in the storage circuit <NUM> is equal to or greater than the upper limit value such that the amplifier circuit <NUM> stops providing the output audio signal OUT to the audio playing circuit <NUM>. In order to avoid misjudgment, the upper limit value may be three times or more than three times a throughput per millisecond (a throughput of the sampling period). For example, in the embodiments where the sampling rate is <NUM> and each of two sound channels corresponds to <NUM> bits, the throughput per millisecond (the throughput of the sampling period) is <NUM>×<NUM>×<NUM>=<NUM> bits. The upper limit value may be <NUM> (a product of <NUM> and <NUM>) bits or greater than <NUM> (a product of <NUM> and <NUM>) bits.

Based on the operations above, if the total data volume of the digital audio data DS in the storage circuit <NUM> is not a multiple of the throughput or the total data volume of the digital audio data DS in the storage circuit <NUM> is equal to or greater than the upper limit value (i.e., the determination result of operation S341 is "NO"), it goes to operation S342.

In operation S342, the amplifier circuit <NUM> is turned off. To be more specific, the control circuit <NUM> turns off the amplifier circuit <NUM> such that the amplifier circuit <NUM> stops providing the output audio signal OUT to the audio playing circuit <NUM>. Then, it goes to operation S343.

In operation S343, the storage circuit <NUM> stops receiving the digital audio data DS from the electrical device D1. For example, the control circuit <NUM> controls (disables) the receiver circuit <NUM> to stop transmitting the digital audio data DS to the storage circuit <NUM>. Then, it goes to operation S344.

In operation S344, the digital audio data DS stored in the storage circuit <NUM> is erased and the clock signal CLK is reset. For example, the control circuit <NUM> erases the digital audio data DS stored in the storage circuit <NUM> and resets the clock signal CLK. Then, it goes to operation S345.

In operation S345, the storage circuit <NUM> receives the digital audio data DS from the electrical device D1 again. For example, the control circuit <NUM> controls (enables) the receiver circuit <NUM> to transmit the digital audio data DS to the storage circuit <NUM> again in the time interval when the electrical device D1 does not transmit any data. Then, it goes to operation S346.

In operation S346, the detector circuit <NUM> detects whether the total data volume of the digital audio data DS in the storage circuit <NUM> is a multiple of the throughput and whether the total data volume of the digital audio data DS in the storage circuit <NUM> is less than the upper limit value again. If the total data volume of the digital audio data DS in the storage circuit <NUM> is a multiple of the aforementioned throughput and the total data volume of the digital audio data DS in the storage circuit <NUM> is less than the aforementioned upper limit value (i.e., the determination result of operation S346 is "YES"), it goes to operations S347. If the determination result of operation S346 is "NO", it returns back to operation S342.

In operation S347, the amplifier circuit <NUM> is turned on again. For example, the control circuit <NUM> restarts the amplifier circuit <NUM> such that the amplifier circuit <NUM> provides the output audio signal OUT to the audio playing circuit <NUM> again.

In some application environments, due to some factors (e.g., poor circuit design on a circuit board, impedance mismatch, and unstable power supply/audio data/clock signal), audio data may be lost or overflowed, and thus noise is generated and affects user's hearing experience. In some related approaches, it requires user to replay or replug the audio adapter device D2 to reduce the noise.

Compared to the aforementioned related approaches, the audio processor circuit <NUM> of the present disclosure can automatically turn off the amplifier circuit <NUM> under a condition that the total data volume of the digital audio data DS in the storage circuit <NUM> is not a multiple of the throughput or the total data volume of the digital audio data DS in the storage circuit <NUM> is equal to or greater than the upper limit value such that the amplifier circuit <NUM> stops providing the output audio signal OUT to the audio playing circuit <NUM>. Thus, it can prevent the user from hearing noise so as to improve the user's hearing experience.

Reference is made to <FIG> is a functional block diagram illustrating an audio processor circuit 200A according to some embodiments of the present disclosure. In some other embodiments, the aforementioned operations can be executed by firmware. As illustrated in <FIG>, a control circuit <NUM> can cooperate with related code to detect and control the receiver circuit <NUM>, the storage circuit <NUM>, the digital-to-analog converter circuit <NUM>, and the amplifier circuit <NUM>. Other operation principles of the audio processor circuit 200A in <FIG> are similar to those of the audio processor circuit <NUM> in <FIG>, so they are not described herein again.

Reference is made to <FIG> is a schematic diagram illustrating an audio playing system <NUM> according to some embodiments of the present disclosure. A major difference between the audio playing system <NUM> in <FIG> and the audio playing system <NUM> in <FIG> is that, the audio processor circuit <NUM> (or 200A) and the audio playing circuit <NUM> are integrated together in an audio playing device D3 in <FIG>. In other words, in <FIG>, a connection portion T2 of the audio playing circuit <NUM> can be inserted into a connection portion P1 of the electrical device D1 in order to directly couple the electrical device D1 without a coupled between an audio adapter device (as the audio adapter device D2 shown in <FIG>) and the electrical device D1. In these embodiments, a type of the connection portion T2 of the audio playing circuit <NUM> corresponds to the type of the connection portion P1.

The operations of the audio processor circuit <NUM> (or 200A) in <FIG> are similar to those of the audio processor circuit <NUM> (or 200A) in <FIG> (or <FIG>), so they are not described herein again.

Claim 1:
An audio processor circuit (<NUM>), comprising
a storage circuit (<NUM>) configured to store digital audio data (DS) from an electrical device (D1);
a digital-to-analog converter circuit (<NUM>) configured to convert the digital audio data (DS) from the storage circuit (<NUM>) into an analog audio signal (AS); and
an amplifier circuit (<NUM>) configured to provide an output audio signal (OUT) to an audio playing circuit (<NUM>) according to the analog audio signal (AS),
a detector circuit (<NUM>) configured to detect whether a total data volume of the digital audio data (DS) stored in the storage circuit (<NUM>) is multiple of a throughput and whether the total data volume of the digital audio data (DS) stored in the storage circuit (<NUM>) is less than an upper limit value;
wherein if the total data volume of the digital audio data (DS) stored in the storage circuit (<NUM>) is detected to be not the multiple of the throughput or the total data volume of the digital audio data (DS) stored in the storage circuit (<NUM>) is detected to be equal to or greater than the upper limit value, the amplifier circuit (<NUM>) is configured to be turned off such that the amplifier circuit stops providing the output audio signal (OUT) to the audio playing circuit (<NUM>),
wherein the throughput is a product of a channel number of the audio playing circuit (<NUM>) and a transmission bit number of each channel, and
wherein the upper limit value is equal to or greater than three times the throughput.