Patent Description:
The present disclosure relates to a control apparatus and a robot system.

<CIT> discloses an electronic apparatus configured to activate the electronic apparatus by reading in and executing a program stored in external memory means. According to the electronic apparatus, even when a boot program stored in a read-only memory (ROM) or the ROM itself is defective, the electronic apparatus can be activated. Thereby, time and effort for repairing including replacement of the ROM may be saved.

Additional prior art is represented by documents <CIT>, <CIT>, <CIT> and <CIT>.

An electronic apparatus may include a main board at least for activation and a sub-board for functionality expansion. When the electronic apparatus including the plurality of boards is activated, in related art, a program necessary for activation is once read out from external memory means into a memory of the main board, and then, a processor of the main board executes processing of loading programs for the respective boards. The loading processing is performed after the programs for the respective boards are read in a work area of the memory of the main board. Accordingly, the work area of the main board is temporarily reduced and the speed of the loading processing and the speed of the activation processing of the main board become lower. As a result, a problem that time is taken for activation of the electronic apparatus arises.

A control apparatus according to an application example of the present disclosure includes a first board having a first memory unit containing a first work area and a first coupling area and a first processing unit executing a first program stored in the first work area, a second board having a second memory unit containing a second work area and a second processing unit executing a second program stored in the second work area, a communication interface linking the first coupling area and the second work area, and a memory medium storing a compressed file containing the first program and the second program, wherein the compressed file is read out from the memory medium into the first work area, the first program contained in the compressed file is loaded in the first work area, the second program contained in the compressed file is loaded in the first coupling area, and the second program is transferred from the first coupling area to the second work area via the communication interface.

A robot system according to an application example of the present disclosure includes a robot including a robot arm, and the control apparatus according to the application example of the present disclosure controlling a motion of the robot.

As below, a control apparatus and a robot system of the present disclosure will be explained in detail based on preferred embodiments shown in the accompanying drawings.

First, a robot system according to an embodiment will be explained.

<FIG> is a conceptual diagram showing a robot system <NUM> according to the embodiment.

The robot system <NUM> shown in <FIG> includes a robot <NUM>, a control apparatus <NUM> (a control apparatus according to the embodiment), a teach pendant <NUM>, a personal computer <NUM>, and a display unit <NUM>.

The robot <NUM> shown in <FIG> includes a base <NUM> and a robot arm <NUM>. The robot arm <NUM> includes six arms coupled sequentially from the base <NUM> side and six joints J1 to J6 coupling between the base <NUM> and the arm and between the arms. Of the six joints J1 to J6 shown in <FIG>, the three joints J2, J3, J5 are bending joints and the other three joints J1, J4, J6 are twisting joints. Each of the joints J1 to J6 includes a motor as a drive source and an encoder for detecting a rotation amount of the motor, i.e., position information of the motor (not shown). In the specification, the motor and the encoder are combined as a servo motor. A control point showing a position of the robot arm <NUM> as an object to be controlled is set at a distal end of the robot arm <NUM>.

Note that, in the embodiment, a six-axis vertical articulated robot is exemplified as the robot <NUM>, however, the number of axes is not particularly limited, but may be more or less than six. Or, the robot <NUM> may be a horizontal articulated robot, a dual-arm robot, or a robot having another form.

An arm end <NUM> is provided at the distal end of the robot arm <NUM>, i.e., an end of the robot arm <NUM> opposite to the base <NUM>. An end effector <NUM> is attached to the arm end <NUM>. The end effector <NUM> is detachably attached. The end effector <NUM> includes e.g., a hand gripping a workpiece and a suction tool suctioning a work piece.

<FIG> is a block diagram showing a hardware configuration of the control apparatus <NUM> shown in <FIG>.

The control apparatus <NUM> shown in <FIG> includes a main board <NUM> (first board), a first sub-board <NUM> (second board), and a second sub-board <NUM> (third board). These respective boards can communicate with one another via a communication interface <NUM>.

The main board <NUM> shown in <FIG> includes a printed wiring board <NUM>, a processor <NUM> (first processing unit), a system bus <NUM>, a RAM <NUM> (first memory unit), a ROM <NUM>, an input/output port <NUM>, a memory card interface <NUM>, and a memory card <NUM> (memory medium). The RAM is abbreviated for Random Access Memory and the ROM is abbreviated for Read-Only Memory.

The printed wiring board <NUM> includes an insulated substrate and wires and electrically couples attached electronic components.

The processor <NUM> realizes various functions by executing a first program loaded in the RAM <NUM>. The processor <NUM> includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). The microprocessor and the core include e.g., CPUs (Central Processing Units) and DSPs (Digital Signal Processors). The processor circuit includes e.g., a SoC (System on a Chip) and a SiP (System in a Package). Or, a part or all of the processor <NUM> may be formed by a device such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

The system bus <NUM> is a transmission route coupling between the processor <NUM> and the RAM <NUM> and ROM <NUM> for enabling mutual communication.

The RAM <NUM> temporarily stores the first program to be executed by the processor <NUM>, read-out data, etc. The RAM <NUM> includes e.g., a DRAM (Dynamic Random Access Memory).

The ROM <NUM> stores a boot program to be executed by the processor <NUM> etc. The ROM <NUM> includes e.g., an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory) and a Flash ROM (Flash Read-Only Memory). Note that the ROM <NUM> may be an external memory.

The input/output port <NUM> is an interface for communication between the respective units of the main board <NUM> and another apparatus. The input/output port <NUM> includes e.g., a digital input/output port such as a USB (Universal Serial Bus), an Ethernet (registered trademark) port, and a picture output port.

The memory card interface <NUM> is an interface for the memory card <NUM> (memory medium) to be detachable. The memory card interface <NUM> reads out a file stored in the attached memory card <NUM> and writes a file in the attached memory card <NUM>. A compressed file <NUM>, which will be described later, is stored in the memory card <NUM>.

The memory card <NUM> includes e.g., various memory media such as an SD card and a USB memory. Preferably, the memory media are data-writable and non-volatile. Thereby, for example, the memory medium may be easily replaced by a memory card <NUM> storing a new compressed file <NUM>, and the new compressed file <NUM> may be introduced into the main board <NUM> easily in a short time.

Note that the memory card <NUM> is detachable and external data may be easily read in the main board <NUM>. On the other hand, the memory card <NUM> may be undetachable and, in this case, may be fixed to the control apparatus <NUM> as a mere memory medium. Further, data may be downloaded in the memory medium via a network or the like.

The first sub-board <NUM> shown in <FIG> includes a printed wiring board <NUM>, a processor <NUM> (second processing unit), a system bus <NUM>, and a RAM <NUM> (second memory unit).

The processor <NUM> realizes various functions by executing a second program loaded in the RAM <NUM>. The processor <NUM> includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). Or, a part or all of the processor <NUM> may be formed by a device such as an ASIC or an FPGA.

The system bus <NUM> enables communication between the processor <NUM> and the RAM <NUM>. The RAM <NUM> temporarily stores the second program to be executed by the processor <NUM>, read-out data, etc..

The second sub-board <NUM> shown in <FIG> includes a printed wiring board <NUM>, a processor <NUM> (third processing unit), a system bus <NUM>, and a RAM <NUM> (third memory unit).

The processor <NUM> realizes various functions by executing a third program loaded in the RAM <NUM>. The processor <NUM> includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). Or, a part or all of the processor <NUM> may be formed by a device such as an ASIC or an FPGA.

The system bus <NUM> enables communication between the processor <NUM> and the RAM <NUM>. The RAM <NUM> temporarily stores the third program to be executed by the processor <NUM>, read-out data, etc..

The communication interface <NUM> is a transmission route for transmission of programs, data, etc., e.g., a serial communication interface such as a PCI or PCI-Express (registered trademark) or the like. In the following description, the PCI-Express is also referred to as "PCle".

As above, the hardware configuration example of the control apparatus <NUM> is explained, however, the hardware configuration is not limited to that. For example, the second sub-board <NUM> may be omitted or another sub-board may be added.

<FIG> is a functional block diagram showing functions of the control apparatus <NUM> shown in <FIG>.

The main board <NUM> shown in <FIG> has an interface control unit <NUM>, a language analysis unit <NUM>, an input/output control unit <NUM>, an interrupt control unit <NUM>, and an activation processing unit <NUM> as functional units. The functions of these respective functional units are realized by e.g., the processor <NUM> executing the first program stored in the RAM <NUM> of the main board <NUM> and the boot program stored in the ROM <NUM> depending on the hardware configuration of the main board <NUM>.

For example, the interface control unit <NUM> controls communication among the main board <NUM>, the first sub-board <NUM>, and the second sub-board <NUM>.

The language analysis unit <NUM> reads and analyzes a robot language describing a motion of the robot <NUM>. The unit receives a motion program of the robot <NUM> from the personal computer <NUM> via the input/output control unit <NUM>, which will be described later, analyzes the motion program, and acquires target position information of the robot arm <NUM>. The target position information is information on a target position as a target location to which the control point of the robot arm <NUM> is moved, e.g., data representing coordinates of the target position.

The input/output control unit <NUM> controls coupling to the teach pendant <NUM>, the personal computer <NUM>, and another peripheral device coupled to the main board <NUM>.

The interrupt control unit <NUM> controls processing of branching from a program being executed to another program (interrupt processing).

The activation processing unit <NUM> has a function of activating the main board <NUM>. The activation processing unit <NUM> has a hardware initialization section <NUM>, a program readout section <NUM>, a program certification section <NUM>, a program loading section <NUM>, and a program execution section <NUM>.

The hardware initialization section <NUM> initializes at least the main board <NUM> and the communication interface <NUM>.

The program readout section <NUM> reads out a file stored in the memory card <NUM>. Then, the program readout section <NUM> copies the read-out file in the RAM <NUM>.

<FIG> shows a file structure of overall firmware <NUM> stored in the memory card <NUM> in <FIG>. As shown in <FIG>, the overall firmware <NUM> has a main board firmware <NUM> (first program), a first sub-board firmware <NUM> (second program), and a second sub-board firmware <NUM> (third program). Each firmware is a program containing e.g., an OS (operating system), an application, data, etc. The overall firmware <NUM> is generally in a binary format, but may be in a text format.

<FIG> shows a memory map of the memory card <NUM> shown in <FIG> and a memory map of the main board <NUM> shown in <FIG>. Note that the memory map shown in <FIG> is an example and the memory map is not limited to that.

As shown in <FIG>, the RAM <NUM> of the main board <NUM> contains memory spaces including a PCIe link area <NUM> (first coupling area), a peripheral area <NUM>, a work area <NUM> (first work area), and a boot area <NUM>. Of the areas, the boot area <NUM> stores a public key <NUM> and a bootloader <NUM>.

Further, as shown in <FIG>, the memory space of the memory card <NUM> is divided in a first partition <NUM> and a second partition <NUM>. The first partition <NUM> stores the compressed file <NUM> and an electronic signature <NUM>. The second partition <NUM> stores a root file system <NUM>.

The compressed file <NUM>, the electronic signature <NUM>, and the root file system <NUM> shown in <FIG> are copied in the work area <NUM> in the activation processing of the control apparatus <NUM>, which will be described later.

The program certification section <NUM> certifies the compressed file <NUM> read out in the RAM <NUM>. The certification refers to verification of integrity and authenticity of the compressed file <NUM>. In the specification, as a result of the verification, a status that the integrity and the authenticity are confirmed is referred to as "certified".

The program loading section <NUM> loads the main board firmware <NUM> of the certified compressed file <NUM> in the work area <NUM> of the RAM <NUM> of the main board <NUM>. Further, the program loading section <NUM> loads the first sub-board firmware <NUM> and the second sub-board firmware <NUM> of the certified compressed file <NUM> in the PCIe link area <NUM> of the RAM <NUM>.

The program execution section <NUM> executes the certified main board firmware <NUM>. Thereby, the main board <NUM> is activated.

Note that these functional units of the main board <NUM> are examples and may be partially omitted or partially provided on another board, and another functional unit may be added.

The first sub-board <NUM> shown in <FIG> has a trajectory generation unit <NUM> and an activation processing unit <NUM> as functional units. The functions of these respective functional units are realized by e.g., the processor <NUM> executing the second program stored in the RAM <NUM> of the first sub-board <NUM> depending on the hardware configuration of the first sub-board <NUM>.

The trajectory generation unit <NUM> generates a trajectory when the robot arm <NUM> is driven based on the target position information received from the main board <NUM>.

The activation processing unit <NUM> executes the certified first sub-board firmware <NUM>. Thereby, the first sub-board <NUM> is activated.

Note that these functional units of the first sub-board <NUM> are examples and may be partially omitted or partially provided in another board, and another functional unit may be added.

The second sub-board <NUM> shown in <FIG> has a servo processing unit <NUM> and an activation processing unit <NUM> as functional units. The functions of these respective functional units are realized by e.g., the processor <NUM> executing the second program stored in the RAM <NUM> of the second sub-board <NUM> depending on the hardware configuration of the second sub-board <NUM>.

The servo processing unit <NUM> controls an operation of the servo motor of the robot <NUM>.

The activation processing unit <NUM> executes the certified second sub-board firmware <NUM>. Thereby, the second sub-board <NUM> is activated.

Note that these functional units of the second sub-board <NUM> are examples and may be partially omitted or partially provided in another board, and another functional unit may be added.

Next, an activation method for the control apparatus <NUM> shown in <FIG> is explained.

<FIG> is a flowchart for explanation of the activation method for the control apparatus <NUM>. <FIG> are conceptual diagrams for explanation of the activation method shown in <FIG>.

The activation method for the control apparatus <NUM> shown in <FIG> has step S102 to step S114.

After the control apparatus <NUM> is turned on, the process goes to step S102. At step S102, the program readout section <NUM> of the activation processing unit <NUM> performs processing of reading out the public key <NUM> and the bootloader <NUM> stored in the boot area <NUM> shown in <FIG>. Then, the program certification section <NUM> performs processing of certifying the public key <NUM> and the bootloader <NUM>. The certification processing is processing of verifying integrity and authenticity of the public key <NUM> and the bootloader <NUM>.

At step S104, the hardware initialization section <NUM> initializes the main board <NUM> and the communication interface <NUM>.

At step S106, the program execution section <NUM> executes the bootloader <NUM>. Thereby, preparation for execution of the firmwares is made.

At step S108, the program readout section <NUM> reads out the compressed file <NUM>, the electronic signature <NUM>, and the root file system <NUM> stored in the memory card <NUM> in the work area <NUM>.

The electronic signature <NUM> is a digital signature associated with the compressed file <NUM>. The compressed file <NUM> is a file formed by data compression of the overall firmware <NUM>. The root file system <NUM> is a root file system of each firm ware.

In <FIG>, generation processing of the electronic signature <NUM> is explained.

First, the overall firmware <NUM> is data-compressed and the compressed file <NUM> is obtained. The compressed file <NUM> is stored in the memory card <NUM> without change. The overall firmware <NUM> is compressed and stored, and thereby, data capacity of the memory card <NUM> may be reduced and time taken for reading out and loading of the stored compressed file may be reduced.

On the other hand, a hash function is executed on the compressed file <NUM>. Thereby, a hash value <NUM> is obtained. The hash function is a function of returning output data (hash value) having a fixed length from data having an arbitrary length and has a property of returning the same hash value from the same data. The hash function includes e.g., SHA-<NUM>, SHA-<NUM>, and SHA-<NUM>.

The obtained hash value <NUM> is encrypted using a secret key <NUM>. The encryption of the hash value <NUM> may be performed by e.g., a certificate authority as a certification institution using the secret key <NUM>. Thereby, the electronic signature <NUM> is obtained. The electronic signature <NUM> is stored in the memory card <NUM>.

At step S110, the program certification section <NUM> certifies the compressed file <NUM> based on the electronic signature <NUM> read out in the work area <NUM>.

In <FIG>, the certification processing of the compressed file <NUM> is explained.

First, the read-out electronic signature <NUM> is decrypted using the public key <NUM>. The public key <NUM> forms a pair with the above-described secret key <NUM> and is issued from the certificate authority in advance. By decryption, a hash value <NUM> (first hash value) is generated. On the other hand, the hash function is executed on the compressed file <NUM>. Thereby, a hash value <NUM> (second hash value) is generated. Then, the hash value <NUM> and the hash value <NUM> are compared. When the values are the same, integrity and authenticity of the compressed file <NUM> are confirmable, and thereby, the compressed file is certified. When the values are different, integrity and authenticity of the compressed file <NUM> are impaired, and thereby, the compressed file is not certified.

According to the certification processing, the certification of the compressed file <NUM> may be achieved only by comparison between the values having fixed lengths as hash values. Accordingly, the certification may be achieved in a shorter time and that contributes to shortening of the activation time of the control apparatus <NUM>. Further, it is preferable that the public key <NUM> is stored in the control apparatus <NUM>. Thereby, the certification processing may be performed in a local environment and that contributes to further shortening of the activation time.

At step S111, whether the compressed file <NUM> is certified is determined. When the compressed file is certified, the process goes to step S112. When the compressed file is not certified, the flow is ended. Thereby, the control apparatus <NUM> may be activated only when the file is certified and secure boot is realized.

At step S112, the program loading section <NUM> loads the respective firmwares from the compressed file <NUM>.

<FIG> and <FIG> are respectively for explanation of the processing of loading the respective firmwares from the compressed file <NUM>.

As shown in <FIG> and <FIG>, the main board <NUM> contains the PCIe link area <NUM> (first coupling area), the peripheral area <NUM>, and the work area <NUM> (first work area) as the memory spaces. Of the areas, the PCIe link area <NUM> contains a first sub-board link area 512a and a second sub-board link area 512b. The peripheral area <NUM> is a memory space provided to a peripheral device coupled to the main board <NUM>. The work area <NUM> is a memory space accessed by the processor <NUM>. Note that these memory spaces are set in e.g., the RAM <NUM>, however, may be set in another memory device. Further, the setting of the memory spaces is performed by e.g., a controller (not shown) contained in the chipset of the communication interface <NUM>.

As shown in <FIG>, the first sub-board <NUM> contains a PCIe link area <NUM> (second coupling area) and a work area <NUM> (second work area) as memory spaces. Of the areas, the PCIe link area <NUM> contains a second sub-board link area 522b. The work area <NUM> is a memory space accessed by the processor <NUM>. Note that these memory spaces are set in e.g., the RAM <NUM>, however, may be set in another memory device.

As shown in <FIG>, the second sub-board <NUM> contains a work area <NUM> (third work area) as a memory space. The work area <NUM> is a memory space accessed by the processor <NUM>.

The first sub-board link area 512a is linked to the work area <NUM> via the communication interface <NUM>.

The second sub-board link area 512b is mutually linked to the second sub-board link area 522b and the work area <NUM> via the communication interface <NUM>.

At step S112, as shown in <FIG>, the program loading section <NUM> extracts the main board firmware <NUM> (first program) from the compressed file <NUM> and loads the firmware in the work area <NUM> of the main board <NUM>. Further, as shown in <FIG>, the program loading section <NUM> extracts the first sub-board firmware <NUM> (second program) from the compressed file <NUM> and loads the firmware in the first sub-board link area 512a contained in the PCIe link area <NUM> (first coupling area) of the main board <NUM>. Furthermore, as shown in <FIG>, the program loading section <NUM> extracts the second sub-board firmware <NUM> (third program) from the compressed file <NUM> and loads the firmware in the second sub-board link area 512b contained in the PCIe link area <NUM> of the main board <NUM>. The loading processing is performed by e.g., the processor <NUM> or the controller (not shown) contained in the chipset of the communication interface <NUM>.

Note that, when the program loading section <NUM> performs the above-described loading, the section may load the respective firmwares remaining in the compressed conditions or in decompressed conditions. When loaded in the compressed conditions, the firmwares may be decompressed in the respective boards.

At step S114, as shown in <FIG>, the first sub-board firmware <NUM> is transferred from the first sub-board link area 512a contained in the PCIe link area <NUM> (first coupling area) to the work area <NUM> (second work area) of the first sub-board <NUM> via the communication interface <NUM>.

Further, at step S114, as shown in <FIG>, the second sub-board firmware <NUM> is transferred from the second sub-board link area 512b contained in the PCIe link area <NUM> (first coupling area) through the PCIe link area <NUM> (second coupling area) of the first sub-board <NUM> to the work area <NUM> (third work area) of the second sub-board <NUM> via the communication interface <NUM>. The loading processing is performed by e.g., the controller (not shown) contained in the chipset of the communication interface <NUM>. Thereby, the transfer processing may be performed with the minimized load on the processor <NUM>.

In the above-described manner, the respective firmwares may be loaded in the respective work areas. Then, the respective firmwares are executed in the respective work areas, and thereby, the respective boards may be activated and the activation of the control apparatus <NUM> is completed.

As described above, not all of the compressed file <NUM> read out into the work area <NUM> of the main board <NUM> is loaded in the work area <NUM>, but only the main board firmware <NUM> is loaded in the work area <NUM>. On the other hand, the first sub-board firmware <NUM> and the second sub-board firmware <NUM> are loaded in the PCIe link area <NUM>.

Then, the first sub-board firmware <NUM> is transferred from the PCIe link area <NUM> to the work area <NUM> of the first sub-board <NUM> and the second sub-board firmware <NUM> is transferred from the PCIe link area <NUM> through the PCIe link area <NUM> to the work area <NUM> of the second sub-board <NUM>.

Thereby, the work area <NUM> of the main board <NUM> may be avoided from being occupied by the loading and the transfer of the respective firmwares. As a result, the temporal reduction of the work area <NUM> may be suppressed and the reduction of the processing speed of the processor <NUM> of the main board <NUM> may be suppressed. Further, in parallel to the operation of the processor <NUM>, the respective firmwares can be transferred. Accordingly, the reduction of the operation speed of the processor <NUM> with the transfer of the respective firmwares may be suppressed. Therefore, the activation time of the control apparatus <NUM> may be shortened using the above-described activation method.

In the control apparatus <NUM>, the system of reading out the compressed file <NUM> is employed, and therefore, compared to a case where an uncompressed firmware is read out, data capacity of the memory card <NUM> may be reduced. Thereby, the time taken to read out the firmware may be reduced.

As described above, the control apparatus <NUM> (the control apparatus according to the above-described embodiment) includes the main board <NUM> (first board), the first sub-board <NUM> (second board), the communication interface <NUM>, and the memory card <NUM> (memory medium) as shown in <FIG> and <FIG>.

As shown in <FIG> and <FIG>, the main board <NUM> has the RAM <NUM> (first memory area) containing the work area <NUM> (first work area) and the PCIe link area <NUM> (first coupling area) and the processor <NUM> (first processing unit) executing the main board firmware <NUM> (first program) stored in the work area <NUM>.

The first sub-board <NUM> has the RAM <NUM> (second memory unit) containing the work area <NUM> (second work area) and the processor <NUM> (second processing unit) executing the first sub-board firmware <NUM> (second program) stored in the work area <NUM>.

The communication interface <NUM> links the PCIe link area <NUM> and the work area <NUM>.

The memory card <NUM> (memory medium) stores the compressed file <NUM> containing the main board firmware <NUM> and the first sub-board firmware <NUM>.

Then, the control apparatus <NUM> reads out the compressed file <NUM> from the memory card <NUM> into the work area <NUM>, loads the main board firmware <NUM> contained in the compressed file <NUM> in the work area <NUM>, loads the first sub-board firmware <NUM> contained in the compressed file <NUM> in the PCIe link area <NUM>, and transfers the first sub-board firmware <NUM> from the PCIe link area <NUM> to the work area <NUM> via the communication interface <NUM>.

According to the configuration, the work area <NUM> of the main board <NUM> may be avoided from being occupied by the loading and the transfer of the respective firmwares. As a result, the temporal reduction of the work area <NUM> may be suppressed and the reduction of the processing speed of the processor <NUM> of the main board <NUM> may be suppressed. Further, in parallel to the operation of the processor <NUM>, the respective firmwares can be transferred. Accordingly, the reduction of the operation speed of the processor <NUM> with the transfer of the respective firmwares may be suppressed. Therefore, according to the above-described configuration, the activation time of the control apparatus <NUM> may be shortened.

Further, in the above-described embodiment, the memory card <NUM> (memory medium) stores the electronic signature <NUM> associated with the compressed file <NUM>.

It is preferable that the control apparatus <NUM> according to the above-described embodiment performs the certification processing of certifying the compressed file <NUM> based on the electronic signature <NUM>, when the compressed file is certified in the certification processing, loads the main board firmware <NUM> (first program) and the first sub-board firmware <NUM> (second program) and, when the compressed file is not certified, does not load the main board firmware <NUM> and the first sub-board firmware <NUM>.

Thereby, the secure boot of the control apparatus <NUM> may be realized. That is, the activation of the control apparatus <NUM> based on the uncertified compressed file <NUM> may be prevented.

Further, in the above-described embodiment, the certification processing has the processing of generating the hash value <NUM> (first hash value) from the electronic signature <NUM> using the public key <NUM>, the processing of generating the hash value <NUM> (second hash value) by executing the hash function on the compressed file <NUM>, and the processing of comparing the hash value <NUM> and the hash value <NUM>.

Thereby, the certification of the compressed file <NUM> may be achieved only by reading out of the two files (the electronic signature <NUM> and the compressed file <NUM>) from the memory card <NUM> and comparison between the values having fixed lengths generated from the files. Thereby, the activation time of the control apparatus <NUM> may be further shortened. Further, the public key <NUM> is stored in the control apparatus <NUM>, and thereby, the activation time may be further shortened.

In the above-described embodiment, the communication interface <NUM> is the PCI-Express interface. The PCI-Express interface includes a mechanism for performing transfer processing with suppressed loads on the processors <NUM>, <NUM>, <NUM>, e.g., bus master transfer. Thereby, in the processors <NUM>, <NUM>, <NUM>, other processing than the transfer processing may be performed in parallel. As a result, the activation time of the control apparatus <NUM> may be further shortened.

In the above-described embodiment, the control apparatus <NUM> further includes the second sub-board <NUM> (third board). The second sub-board <NUM> has the RAM <NUM> (third memory unit) containing the work area <NUM> (third work area) and the processor <NUM> (third processing unit) executing the second sub-board firmware <NUM> (third program) stored in the work area <NUM>.

The RAM <NUM> (second memory unit) further contains the PCIe link area <NUM> (second coupling area) and the communication interface <NUM> mutually links the PCIe link area <NUM> (first coupling area), the PCIe link area <NUM> (second coupling area), and the work area <NUM> (third work area).

The control apparatus <NUM> transfers the second sub-board firmware <NUM> from the PCIe link area <NUM> through the PCIe link area <NUM> to the work area <NUM> via the communication interface <NUM>.

According to the configuration, even the control apparatus <NUM> having two or more expansion boards (sub-boards) may shorten the activation time. Thereby, a balance between improvements in performance and stability with function distribution and shortening of the activation time may be achieved.

The robot system <NUM> according to the above-described embodiment includes the robot <NUM> having the robot arm <NUM> and the control apparatus <NUM> (the control apparatus according to the embodiment) controlling the motion of the robot <NUM>.

According to the configuration, the robot system <NUM> that may enjoy the effects exerted by the control apparatus <NUM> and can be activated in a shorter time may be realized.

As above, the control apparatus and the robot system of the present disclosure are explained based on the illustrated embodiments, however, the present disclosure is not limited to those.

Claim 1:
A control apparatus comprising:
a first board having a first memory unit containing a first work area and a first coupling area and a first processing unit executing a first program stored in the first work area;
a second board having a second memory unit containing a second work area and a second processing unit executing a second program stored in the second work area;
a communication interface linking the first coupling area and the second work area; and
a memory medium storing a compressed file containing the first program and the second program, wherein
the compressed file is read out from the memory medium into the first work area,
the first program contained in the compressed file is loaded in the first work area,
the second program contained in the compressed file is loaded in the first coupling area, and
the second program is transferred from the first coupling area to the second work area via the communication interface.