Patent Description:
Insulated gate transistor devices such as MOSFETs or IGBTs are widely used as electronic switches in various kinds of electronic circuits. Examples of such circuits include switched-mode power supplies, motor drive circuits, or inverters to name only a few.

An insulated gate transistor device is a voltage-controlled transistor device that is configured to switch on and off dependent on a drive voltage received at a drive input. In the on-state, the transistor device is configured to conduct a current through a load path. In the off-state, the transistor device is configured to block.

Inevitably, in an insulated gate transistor device, the load path is capacitively coupled with the drive input. In a MOSFET, for example, a drain node, which is part of the load path, is capacitively coupled with the gate node, which is part of the drive input.

The capacitive coupling between the load path and the drive input may have the effect that the transistor device erroneously switches on after having been switched off. More specifically, switching off the transistor device may cause a voltage across the load path to rapidly increase, which may cause the electrical potential at the drain node to rapidly increase. Due to the capacitive coupling between the load path and the drive input, such rapid increase of the potential at the drain node may cause a voltage spike at the gate node that causes the transistor device to switch on. This is highly undesirable.

There is therefore a need to protect a transistor device, in particular an insulated gate transistor device, from erroneously switching on due to a rapidly increasing voltage across the load path. This problem is already addressed in <CIT>, which proposes a solution different from the present invention.

One example relates to an electronic circuit. The electronic circuit includes a first transistor device and a protection circuit. The first transistor device includes a first drive node, a second drive node, and a load path. The protection circuit is coupled to the first and second drive nodes and the load path of the first transistor device. The protection circuit includes a second transistor device having a first drive node, a second drive node, and a load path. Furthermore, the protection circuit includes a capacitor coupled between the load path of the first transistor device and the first drive node of the second transistor device. The load path of the second transistor device is connected between the first and second drive nodes of the first transistor device. A capacitance of the capacitor is voltage dependent such that the capacitance decreases as a voltage across the capacitor increases.

Another example relates to a method. The method includes switching off a first transistor device protection circuit. The transistor device includes a first drive node, a second drive node, and a load path. The protection circuit is coupled to the first and second drive nodes and the load path of the first transistor device. The protection circuit includes a second transistor device comprising a first drive node, a second drive node, and a load path connected between the first and second drive nodes of the first transistor device, and a capacitor coupled between the load path of the first transistor device and the first drive node of the second transistor device, wherein the capacitance of the capacitor is voltage dependent such that the capacitance decreases as a voltage across the capacitor increases.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented.

<FIG> shows a circuit diagram of an electronic circuit according to one example. The electronic circuit includes a first transistor device <NUM> and a protection circuit <NUM>. The first transistor device <NUM> includes a first drive node G1, a second drive node S1, and a load path D1-S1. The protection circuit <NUM> includes a second transistor device <NUM> with a first drive node G2, a second drive node S2, and a load path D2-S2. Furthermore, the protection circuit <NUM> includes a capacitor <NUM> coupled between the load path D1-S1 of the first transistor device <NUM> and the first drive node G2 of the second transistor device <NUM>. The load path D2-S2 of the second transistor device <NUM> is connected between the first and second drive nodes G1, S1 of the first transistor device <NUM>. Furthermore, the capacitor <NUM> of the protection circuit <NUM> is selected such that its capacitance decreases as a voltage V3 across the capacitor <NUM> increases V3.

The first transistor device <NUM> may be used as an electronic switch that controls a voltage across any type of load or circuit element connected in series with the load path D1-S1 of the first transistor device <NUM>. For this, as illustrated in dashed lines in <FIG>, the load path D1-S1 of the first transistor device <NUM> may be connected in series with the load or circuit element Z, wherein the series circuit including the first transistor device <NUM> and the load or circuit element Z is connected to a power source that provides a supply voltage Vsup. The load or circuit element, which is represented by reference character Z in <FIG>, may be any type of load, such as a light, a magnetic valve, or the like, or any type of circuit element, such as an inductor in a switched-mode power supply. According to one example, the transistor device <NUM> is used as an electronic switch in a switched-mode power supply (SMPS).

As illustrated in <FIG>, the load or circuit element Z may be connected between the transistor device <NUM> and a first supply node of the power supply, so that the transistor device <NUM> may operate as a low-side switch. This, however, zone an example. It is also possible to connect the transistor device <NUM> between the first supply node and the load Z, so that the transistor device <NUM> may operate as a high-side switch. Furthermore, it is possible to implement the transistor device <NUM> as part of an electronic circuit in which one or more elements of the circuit are connected between the transistor device <NUM> and the first supply node and or more other elements of the electronic circuit are connected between the transistor device <NUM> and a second supply node of the power source.

The first transistor device <NUM> is configured to switch on in order to be in an on-state, or to switch off in order to be in an off-state. In the on-state, the load path D1-S1 of the first transistor device <NUM> is conducting, so that a voltage V1 across the load path D1-S1 is essentially zero and a voltage across the load or circuit element Z essentially equals the supply voltage Vsup. In the off-state, the load path D1-S1 of the first transistor device <NUM> is blocking, so that the voltage V1 across the load path D1-S1 of the first transistor device <NUM> essentially equals the supply voltage Vsup.

The first transistor device <NUM> switches on or off dependent on a drive voltage Vgs1 received between the first drive node G1 and the second drive node S1. The load path D1-S1 is a circuit path between a first load path node D1 and a second load path node S1. Just for the purpose of illustration, in the first transistor device <NUM> according to <FIG>, the second drive node and the second load path node are formed by the same circuit node of the first transistor device <NUM>. This, however, is only an example. It is also possible to implement the first transistor device <NUM> such that the second drive node and the second load path node are different circuit nodes of the first transistor device <NUM>. In this example, the protection circuit <NUM> may be connected to both the second drive node and the second load path node.

Just for the purpose of illustration, the first transistor device according to <FIG> is a MOSFET, in particular an N-type enhancement MOSFET. In this example, the drive node G1 is a gate node of the MOSFET, the first load path node D1 is a drain node of the MOSFET, and the second drive node and second load path node S1 is a source node of the MOSFET.

Referring to <FIG>, the first load path node D1 and the drive node G1 of the first transistor device <NUM> are capacitively coupled, wherein such capacitive coupling is represented by a capacitor C12 connected between the first load path node D1 and the first drive node G1. In a MOSFET, for example, this capacitor C12 is formed by an inherent gate-drain capacitance of the MOSFET. In addition to the gate-drain capacitance, the MOSFET may include a gate-source capacitance, which is represented by capacitor C11 connected between the gate node G1 and the source node S1 in <FIG>.

The first transistor device <NUM> may be implemented in such a way that it switches on when the drive voltage Vgs1 received between the first and second drive nodes G1, S1 reaches a predefined positive voltage threshold (that is usually referred to as threshold voltage), and switches off when the drive voltage Vgs1 falls below the threshold voltage. The drive voltage may be generated by a drive circuit (not illustrated in <FIG>). An N-type enhancement MOSFET is one example of a transistor device that operates in this way.

When the first transistor device <NUM> switches from the on-state, in which the voltage V1 across the load path D1-S1 is essentially zero, to the off-state, in which the voltage V1 across the load path D1-S1 essentially equals the supply voltage Vsup, an electrical potential at the first load path node D1 may rapidly increase. Due to the capacitive coupling between the first load path node D1 and the first drive node G1 such rapid increase of the electrical potential at the first load path node D1 may cause an increase of the electrical potential at the first drive node G1, wherein such increase of the electrical potential at the first drive node G1 may have the effect that the drive voltage Vgs1, which is supposed to be below the threshold voltage in the off-state, rises above the threshold, so that the first transistor device unintentionally switches on.

Such unintended switching on of the first transistor device <NUM> is highly undesirable. In the electronic circuit according to <FIG>, the protection circuit <NUM> is configured to protect the first transistor device <NUM> from unintentionally switching on when the switching state changes from the on-state to the off-state.

In the protection circuit <NUM> according to <FIG>, the second transistor device <NUM>, which has its load path D2-S2 connected between the first and second drive nodes G1, S1 of the first transistor device <NUM>, can be operated in an on-state or an off-state. In the on-state, the load path D2-S2 of the second transistor device <NUM> is conducting, so that the second transistor device <NUM> essentially clamps the drive voltage Vgs1 of the first transistor device <NUM> to zero, so that the drive voltage Vgs1 is below the threshold voltage and the first transistor device <NUM> is maintained in the off-state. In the off-state of the second transistor device, the load path D2-S2 is blocking, so that the drive voltage Vgs1 of the first transistor device <NUM>, governed by a drive circuit (not illustrated), may rise above the threshold voltage, so that the first transistor device <NUM> switches on.

The second transistor device <NUM> switches on or off dependent on a drive voltage Vgs2 received between a first drive node G2 and a second drive node S2, wherein the second drive node S2 and the second load path node S2 of the load paths D2-S2 may be formed by the same circuit node of the second transistor device <NUM>. Referring to <FIG>, the second transistor device <NUM> may include an inherent capacitance between the first and second drive nodes G2, S2. This capacitance, which is referred to as drive capacitance in the following, is represented by capacitor C21 in <FIG>. The second transistor device <NUM> may be implemented such that it switches on when the drive voltage Vgs2 rises above a predefined threshold voltage and switches off when the drive voltage Vgs2 falls below the threshold voltage. The threshold voltage is a positive voltage according to one example.

The second transistor device <NUM> may be implemented as a MOSFET, in particular an N-type enhancement MOSFET. In this example, the drive capacitance is formed by a gate-source capacitance of the MOSFET. An N-type enhancement MOSFET is a transistor device having a positive threshold voltage. A gate node of the MOSFET forms the first drive node G1, a drain node of the MOSFET forms the first load path node D1, and a source node of the MOSFET forms the second drive node and second load path node S2.

Referring to <FIG>, the drive capacitance C21 of the second transistor device <NUM> and the capacitor <NUM> of the protection circuit <NUM> form a capacitive voltage divider connected in parallel with the load path D1-S1 of the first transistor device <NUM>. When the first transistor device <NUM> switches from the on-state to the off-state, so that the voltage V1 across the load path D1-S1 rapidly increases, a capacitive displacement current flows into the capacitive voltage divider formed by the capacitor <NUM> and the drive capacitance C21 of the second transistor device <NUM>. This capacitive displacement current charges the drive capacitance C21 of the second transistor device <NUM>. In this way, the second transistor device <NUM> switches on when the voltage V1 across the load path D1-S1 the first transistor device rapidly increases, so that the first transistor device <NUM> is maintained in the of state.

Referring to the above, the capacitor <NUM> of the protection circuit <NUM> has a voltage dependent capacitance such that the capacitance decreases as a voltage V3 across the capacitor <NUM> increases. The drive capacitance C21 of the second transistor device <NUM> is essentially constant and independent of the drive voltage Vgs2. The voltage V3 across the capacitor <NUM> and the drive voltage Vgs2 are each a portion of the load path voltage V1, wherein the drive voltage Vgs2 is given by <MAT> and wherein the voltage V3 across the capacitance C3 is given by <MAT> where C21 denotes the capacitance of the drive capacitance of the second transistor device <NUM>, C3 denotes the capacitance of the capacitor <NUM>, V3 denotes the voltage across the capacitor, V1 denotes the load-path voltage of the first transistor device <NUM>, and Vgs2 denotes the drive voltage of the second transistor device <NUM>. Furthermore, a ratio between the drive voltage Vgs2 of the second transistor device <NUM> and the voltage V3 across the capacitor <NUM> is given by <MAT>.

As can be seen from equations (<NUM>)-(<NUM>) the lower of the capacitance C3 of the capacitor <NUM> the lower the portion of the load path voltage V1 that forms the drive voltage Vgs2. Thus, given that the capacitance of the capacitor <NUM> increases as the voltage V3 increases, the portion of the load path voltage V1 that forms the drive voltage Vgs2 decreases as the load path voltage V1 increases. Thus, when the load path voltage V1 is low, a relatively high portion of the load path voltage V1 drops across the drive capacitance of the second transistor device <NUM>, and when the load path voltage V1 is high, a relatively low portion of the load path voltage V1 drops across the drive capacitance of the second transistor device <NUM>. In this way, the drive capacitance C21 is rapidly charged at the beginning of the transition process in which the first transistor device <NUM> changes from the on-state to the off- state and the load path voltage V1 increases, so that the second transistor device <NUM> rapidly switches on in order to maintain the first transistor device <NUM> in the off-state. Furthermore, when the load path voltage V1 increases, the drive capacitance C21 of the second transistor device <NUM> is protected against high voltages as the capacitor <NUM> of the protection circuit <NUM> takes over most of the load path voltage V1. Which portion of the load path voltage V1 is taken over by the capacitor <NUM> when the load path voltage V1 reaches the supply voltage level is dependent on the dimensioning of the capacitor C3 and the drive capacitance C21 of the second transistor device <NUM> and can be adjusted by suitably selecting the capacitor <NUM>.

According to one example, the capacitor <NUM> is configured to withstand essentially the same voltage as the first transistor device <NUM> in the blocking state. According to one example, a voltage blocking capability of the first transistor device <NUM> is in the range of between <NUM> volts (V) and <NUM> V, for example.

According to one example, a resistor <NUM> is connected in parallel with the drive capacitance C21 of the second transistor device <NUM>. The resistor <NUM> discharges the drive capacitance C21 of the second transistor device <NUM> after the transition of the first transistor device <NUM> from the on-state to the off-state in order to switch off the second transistor device <NUM>. The time duration it takes to discharge the drive capacitance C21 such that the drive voltage Vgs2 falls below the threshold voltage of the second transistor device <NUM> and the second transistor device <NUM> switches off can be adjusted by suitably adjusting a resistance of the resistor <NUM> in view on the drive capacitance C21. Basically, at a given drive capacitance C21, the higher the resistance of the resistor <NUM> the longer it takes for the drive capacitance C21 to be discharged.

Referring to <FIG>, the electronic circuit includes three (external) terminals, wherein each of these terminals is connected to a respective one of the three circuit nodes of the first transistor device <NUM>. A first terminal <NUM> is connected to the first drive node G1 of the first transistor device <NUM>, a second terminal <NUM> is connected to the second drive node and second load path node S1 of the first transistor device <NUM>, and a third terminal <NUM> is connected to the first load path node D1 of the first transistor device <NUM>. The drive voltage Vgs1 of the first transistor device <NUM> is a voltage received between the first and second terminals <NUM>, <NUM>. The electronic circuit operates as a transistor device that is protected from unintentionally switching on.

According to one example, the electronic circuit is integrated in one single semiconductor body <NUM>. This is schematically illustrated in dashed-and-dotted lines in <FIG> and is explained in detail herein further below. The semiconductor body <NUM> may include a conventional semiconductor material, such as silicon (Si) or silicon carbide (SiC).

<FIG> illustrates examples of a voltage dependency of a capacitance C3 of the capacitor <NUM>. Curves <NUM>, <NUM> illustrate two different examples in which the capacitance C3 decreases as the voltage V3 across the capacitor <NUM> increases. In a first example represented by curve <NUM> the capacitance C3 decreases slower as the voltage V3 increases than in a second example represented by curve <NUM>. The characteristic of the capacitor <NUM>, that is, the way in which the capacitance C3 decreases as the voltage V3 increases can be adjusted in the way explained herein before.

For the purpose of illustration, curve <NUM> illustrated in <FIG> represents a conventional capacitor in which the capacitance is essentially constant and independent of a voltage across the capacitor.

The capacitor <NUM> can be implemented in various ways. According to one example illustrated in <FIG>, the capacitor <NUM> is implemented as a MOSFET, wherein a gate node G3 of the MOSFET is connected to a source node S3 of the MOSFET. A drain node D3 of the MOSFET forms a first capacitor node N31 that, referring to <FIG>, is connected to the first load path node D1 of the first transistor device. The source node S3 of the MOSFET forms a second capacitor node N32 that, referring to <FIG>, is connected to the drive node G3 of the second transistor device. According to one example, the MOSFET forming the capacitor <NUM> is of the same type as a MOSFET forming the first transistor device <NUM>. According to one example (as illustrated in the drawings) these MOSFETs are N-type enhancement MOSFETs.

<FIG> illustrates one example for implementing the first transistor device <NUM>. More specifically, <FIG> schematically illustrates a perspective sectional view of one section of a semiconductor body <NUM> in which the first transistor device <NUM> is integrated. The first transistor device is a MOSFET in this example.

Referring to <FIG>, the transistor device <NUM> may include a plurality of transistor cells <NUM>, wherein each transistor cell includes a drift region <NUM> of a first doping type (conductivity type), a body region <NUM> of a second doping type complementary to the first doping type and separating a source region <NUM> of the first doping type from the drift region <NUM>, and a drain region <NUM> of the first doping type. Furthermore, each transistor cell <NUM> includes a gate electrode <NUM> that is dielectrically insulated from the body region <NUM> by a gate dielectric <NUM> and is configured to control a conducting channel in the body region <NUM> along the gate dielectric <NUM> between the source region <NUM> and the drift region <NUM>.

The gate electrodes <NUM> are trench electrodes in the example illustrated in <FIG>. That is, the gate electrodes <NUM> are arranged in trenches that, from a first surface <NUM> of the semiconductor body <NUM>, extend into the semiconductor body <NUM>.

Referring to <FIG>, each transistor cell <NUM> may further include a field electrode <NUM> that is dielectrically insulated from the drift region <NUM> by a field electrode dielectric <NUM>. In the example illustrated in <FIG>, the gate electrode <NUM> and the field electrode <NUM> of each transistor cell <NUM> are arranged in the same trench and insulated from one another, wherein, as seen from the first surface <NUM>, the field electrode <NUM> is located below the gate electrode <NUM>. This, however, is only an example. It is also possible, to implement the gate electrode <NUM> and the field electrode <NUM> of each transistor cell <NUM> in different trenches that are spaced apart from each other in a lateral direction of the semiconductor body <NUM>. A "lateral direction" is a direction that is essentially parallel to the first surface <NUM>.

Referring to the above, the first transistor device <NUM> may be implemented as an N-type MOSFET. In this example, the first doping type is an N-type and the second doping type is a P-type.

Referring to <FIG>, the first transistor device <NUM> may be implemented as a vertical transistor device. In this example, the source and drain regions <NUM>, <NUM> of the transistor cells <NUM> are spaced apart from each other in a vertical direction of the semiconductor body <NUM>. The "vertical direction" is a direction that is essentially perpendicular to the first (main) surface <NUM> of the semiconductor body <NUM>.

Referring to <FIG>, the first transistor device <NUM> further includes a gate conductor <NUM>, wherein the gate conductor <NUM> forms the drive node (gate node) G1 or is connected to the drive node G1 of the first transistor device <NUM>. The gate electrodes <NUM> of the individual transistor cells <NUM> are connected to the gate conductor <NUM>. The gate conductor <NUM> may be formed on top of an insulating layer <NUM>, wherein the insulating layer <NUM> is formed on top of the first surface <NUM> of the semiconductor body <NUM> and separates the gate conductor <NUM> from the semiconductor body <NUM>. The gate conductor <NUM> may be connected to the gate electrodes <NUM> through gate vias <NUM>. The gate vias <NUM> extend from the gate conductor <NUM> through the insulating layer <NUM> to the gate electrodes <NUM>.

The first transistor device <NUM> further includes a source electrode <NUM>, wherein the source electrode <NUM> is connected to the second drive node (second load path node, source node) S2 or forms the second drive node S2. The field electrodes <NUM> and the source regions <NUM> of the individual transistor cells <NUM> are connected to the source electrode <NUM>. One way of connecting the field electrodes <NUM> to the first electrode <NUM> is illustrated in <FIG>.

<FIG> shows a vertical cross-sectional view of the semiconductor body <NUM> in a section plane A-A illustrated in <FIG>. In the example illustrated in <FIG>, the source electrode <NUM> is arranged on top of the insulating layer <NUM>. Referring to <FIG>, the source regions <NUM> and the body regions <NUM> of the individual transistor cells <NUM> are connected to the source electrode <NUM> through source vias <NUM> that extend from the source electrode <NUM> through the insulating layer <NUM> down to the source and body regions <NUM>, <NUM>.

Referring to <FIG>, the gate electrodes <NUM> and the field electrodes can be implemented as elongated electrodes that longitudinally extend in a lateral direction of the semiconductor body <NUM>. Each field electrode <NUM> may include a contact section <NUM> that extends to the first surface <NUM> where the field electrode section <NUM> is connected to an electrically conducting via. The electrically conducting via extends through the insulating layer <NUM> and connects the contact section <NUM> of the field electrode <NUM> to the source electrode <NUM>. Referring to <FIG>, the contact section <NUM> extends towards the first surface <NUM> between two gate electrodes <NUM>, wherein each of these gate electrodes <NUM> is connected to a respective gate conductor <NUM> (only one of these gate conductors is illustrated in <FIG>).

Referring to <FIG>, the drift regions <NUM> of the transistor cells <NUM> may be formed by one contiguous semiconductor region of the first doping type. Furthermore, the drain regions <NUM> of the individual transistor cells <NUM> may be formed by one contiguous semiconductor region of the first doping type. According to one example, the semiconductor region forming the drain regions <NUM> of the transistor cells <NUM> is formed by a first semiconductor layer <NUM> on top of which a second semiconductor layer <NUM> is formed. According to one example, the first semiconductor layer <NUM> is a semiconductor substrate and the second semiconductor layer <NUM> is an epitaxial layer. According to one example, the second semiconductor layer <NUM> has a basic doping of the first doping type, wherein the semiconductor region forming the drift regions <NUM> is a region having the basic doping of the epitaxial layer <NUM>. The source and body regions <NUM>, <NUM> may be formed by implanting and/or diffusing dopant atoms into the second semiconductor layer <NUM>.

<FIG> illustrates one example of the capacitor <NUM> of the protection circuit <NUM>. As explained hereinabove, the capacitor <NUM> and the first transistor device <NUM> may be integrated in the same semiconductor body <NUM>. <FIG> shows a vertical cross-sectional view of one section of the semiconductor body <NUM> in which the capacitor <NUM> is integrated.

The capacitor <NUM> according to <FIG> is implemented very similar to the first transistor <NUM> according to <FIG>. This offers the advantage that the first transistor device <NUM> and the capacitor <NUM> can be implemented by widely using the same process steps.

Referring to <FIG>, the capacitor <NUM> includes a first contact electrode <NUM> which forms the second circuit node N32 of the capacitor <NUM>, and a second contact electrode <NUM> which forms the first circuit node N31 of the capacitor <NUM>. The first contact electrode <NUM> is formed on top of the first surface <NUM> of the semiconductor body <NUM> and is separated from the semiconductor body <NUM> by an insulating layer <NUM>. The second contact electrodes <NUM> is formed on top of the second surface <NUM> of the semiconductor body <NUM>. Furthermore, the capacitor <NUM> according to <FIG> includes doped semiconductor regions of the same type as the first transistor device <NUM>. More specifically, the capacitor <NUM> includes a first doped region <NUM> corresponding to the drift region <NUM> of the first transistor device <NUM>, second doped regions <NUM> corresponding to the body regions <NUM>, third doped regions <NUM> corresponding to the source regions <NUM>, and a fourth doped region <NUM> corresponding to the drain region <NUM>. Furthermore, the capacitor <NUM> includes a plurality of trenches <NUM> in which first electrodes <NUM> corresponding to the gate electrodes <NUM> and second electrodes <NUM> corresponding to the field electrodes <NUM> are arranged. The first electrodes <NUM> are dielectrically insulated from the semiconductor body <NUM> by dielectric layers <NUM> corresponding to the gate dielectrics <NUM>, and the second electrodes <NUM> are dielectrically insulated from the semiconductor body <NUM> by dielectric layers <NUM> corresponding to the field electrodes dielectrics <NUM>.

Each of the first and second electrodes <NUM>, <NUM> and the second and third doped regions <NUM>, <NUM> are connected to the first contact electrode <NUM> through respective electrically conducting vias <NUM>, <NUM> that extend through the insulating layer <NUM>. The connection between the second electrodes <NUM> and the first contact electrodes <NUM> is only schematically illustrated in <FIG>. Vias that connect the second electrodes <NUM> to the first contact electrodes <NUM> are out of view in <FIG>. The second electrodes <NUM> may be connected to the first contact electrodes <NUM> in the same way in which the field electrodes <NUM> of the first transistor device <NUM> are connected to the source electrode <NUM>.

In the capacitor <NUM> according to <FIG>, the first and second electrodes <NUM>, <NUM> arranged in the trenches <NUM> and connected to the first contact electrode <NUM> form a first capacitor electrode, the dielectric layers <NUM>, <NUM> form a capacitor dielectric, and the first and fourth doped region <NUM>, <NUM> connected to the second contact electrode <NUM> form a second capacitor electrode. The second contact electrode <NUM> and the drain electrode <NUM> of the first transistor device <NUM> may be formed by the same electrode or metallization layer.

In the capacitor according to <FIG>, when a voltage is applied between the first and second contact electrodes <NUM>, <NUM> in such a way that a PN junction formed between the first regions <NUM> of the first doping and the second regions <NUM>, <NUM> of the second doping type is reverse biased, a space charge region expands in the first semiconductor region <NUM>. This space charge region (depletion region), which is due to the reverse biased PN-junction and the first and second electrodes <NUM>, <NUM> dielectrically insulated from the first doped region <NUM> is associated with storing charge carriers in the first region <NUM> and at the interface between the first and second electrodes <NUM>, <NUM> and the dielectric layers <NUM>, <NUM>, so that the arrangement according to <FIG> acts as a capacitor <NUM>.

According to one example, the first, third and fourth regions <NUM>, <NUM>, <NUM> are N-type regions and the second regions <NUM> are P-type regions. In this example, a space charge region is formed in the first region <NUM> when a positive voltage is applied between the first and second circuit nodes <NUM>, <NUM> of the capacitor <NUM>.

As the voltage between the first and second contact electrodes <NUM>, <NUM> increases mesa regions are arranged between the trenches <NUM> are completely depleted of charge carriers, which is associated with a reduction of the capacitance of the capacitor <NUM>. In this way, the capacitor <NUM> according to <FIG> has a voltage dependent capacitance that decreases as the voltage V3 applied between the first and second contact electrodes <NUM>, <NUM> increases.

<FIG> shows a modification of the capacitor <NUM> according to <FIG>. In the capacitor <NUM> according to <FIG>, the second and third doped regions <NUM>, <NUM> and the first electrodes <NUM> are omitted, so that the first contact electrode <NUM> is only connected to the second electrodes <NUM>, wherein the second electrodes <NUM> form the first capacitor electrode in this example. The second capacitor electrode is formed by the first and fourth doped regions <NUM>, <NUM>. In the capacitor <NUM> according to <FIG>, a space charge region (depletion region) that expands in the first doped region <NUM> when a respective voltage is applied between the first and second contact electrodes <NUM>, <NUM> is governed only by the electrical potential applied to the second electrodes <NUM>. In the same way as in the capacitor <NUM> according to <FIG>, the mesa regions are entirely depleted of charge carriers as the voltage V3 applied between the first and second circuit nodes N31, N32 increases, so that the capacitance of the capacitor C3 decreases as the voltage Vout <NUM> increases.

In <FIG>, voltage levels V31, V32 of voltage V3 at which the decrease of the capacitance slows down with a further increase of the voltage V3 represents those voltage level of the voltage V3 at which the mesa regions are entirely depleted.

<FIG> shows a horizontal cross-sectional view of a capacitor <NUM> of the type illustrated in <FIG> in a section plane B-B illustrated in <FIG>. Referring to <FIG>, the electrodes <NUM> that form the first capacitor electrode may be implemented as elongated electrodes. In the following "basic capacitance" of the capacitor <NUM> denotes the capacitance when the voltage V3 applied to the capacitor is zero. This basis capacitance can be adjusted by suitably adjusting the number and the size, in particular the length, of the electrodes <NUM>. Basically, the capacitance increases as the number and/or the size of the second electrodes <NUM> increases.

<FIG> shows a modification of the capacitor <NUM> according to <FIG>. The capacitor <NUM> according to <FIG> is different from the capacitor <NUM> according to <FIG> in that it includes the second doped regions <NUM> connected to the first contact electrode <NUM>. The second doped region <NUM> that has a doping type complementary to the doping type of the first region <NUM> may help to increase the voltage blocking capability of the capacitor <NUM> according to <FIG> as compared to the capacitor <NUM> according to <FIG>.

In each of the capacitors illustrated in <FIG>, the voltage characteristic can be adjusted by suitably adjusting dimensions and mutual distances of the trenches <NUM> that include the second electrodes <NUM> (and, optionally, the first electrode <NUM>). In <FIG> and <FIG>, d2 denotes a depth of the trenches <NUM>, which is a dimension of the trenches <NUM> in the vertical direction, w2 denotes a width of the trenches <NUM>, which is a dimension of the trenches <NUM> in a lateral direction perpendicular to the longitudinally direction, and m2 denotes a (shortest) distance between the trenches <NUM>. The distance m2 between the trenches <NUM> equals a width of the mesa regions arranged between the trenches <NUM>. According to one example, the trenches <NUM> of the capacitor <NUM> are implemented such that at least <NUM> of the following applies: (a) the trench depth d2 is larger than the trench depth d1 of the trenches with the gate electrodes <NUM> and the field electrodes <NUM> of the first transistor device <NUM>; (b) the trench width w2 is larger than the width of the trenches with the gate electrodes <NUM> and the field electrodes <NUM> of the first transistor device <NUM>; (c) the distance m2 between the trenches <NUM> is smaller than a distance m1 between the trenches with the gate electrodes <NUM> and the field electrodes <NUM> of the first transistor device <NUM>.

By increasing the trench depth d2 and/or increasing the trench width w2 the basic capacitance can be increased. By reducing the distance m2 between the trenches <NUM> the voltage at which the mesa regions are entirely depleted can be reduced. Thus, by suitably adjusting the distance m2 between the trenches <NUM> the voltage level of the voltage V3 can be adjusted at which the capacitor <NUM> reaches its minimum capacitance.

The resistor <NUM> of the protection circuit <NUM> can be implemented in various ways. Some examples are explained with reference to <FIG> in the following.

According to one example illustrated in <FIG>, the resistor <NUM> includes a plurality of resistive conductors <NUM> wherein each of these conductors <NUM> is arranged in a respective trench <NUM> in the semiconductor body <NUM> and is electrically insulated from the semiconductor body <NUM> by an insulating layer <NUM>. The conductors <NUM> may include any kind of resistive material, such as doped polysilicon. The insulating layers <NUM> may include any kind of insulating material, such as an oxide or a nitride.

Referring to <FIG>, each of the conductors <NUM> longitudinally extends in a lateral direction of the semiconductor body <NUM> and is connected to a first contact electrode <NUM> at a first longitudinal end and a second contact electrode <NUM> at a second longitudinal end opposite the first longitudinal end. The first and second contact electrodes <NUM>, <NUM> may be arranged on top of the first surface <NUM> of the semiconductor body <NUM> and insulated from the semiconductor body <NUM>. The first and second contact electrodes <NUM>, <NUM> are illustrated in dashed lines in <FIG>. The contact electrodes <NUM>, <NUM> may be connected to the resistive conductors <NUM> through electrically conducting vias which are schematically illustrated as bold dots in <FIG>.

An overall resistance of the resistor <NUM> can be adjusted by suitably selecting one or more of the following parameters: the length of the resistive conductors <NUM>; a cross-sectional area of the resistive conductors <NUM> in a plane perpendicular to the longitudinally directions of the conductors <NUM>; the resistive material of the resistive conductors <NUM>; and the number of resistive conductors <NUM> that are connected in parallel. Basically, the longer the resistive conductors <NUM> the higher the resistance, the higher the lateral cross-sectional area the lower the resistance, and the higher the number of resistive conductors <NUM> the lower the resistance.

The resistive conductors <NUM> may be implemented in various ways. According to one example, the resistive conductors <NUM> are formed by the same process in which the gate electrodes <NUM> of the first transistor device <NUM> are formed. The insulating layer <NUM> separating the conductor <NUM> from the semiconductor body <NUM> may be formed by the same process in which the gate dielectrics <NUM> are formed in the first transistor device <NUM>. Vertical cross-sectional views of a resistive conductor <NUM> of this type are illustrated in <FIG>.

<FIG> shows a vertical cross-sectional view of a conductor <NUM> in a first section plane C-C according to <FIG>, and <FIG> shows a vertical cross-sectional view of the conductor <NUM> in a second section plane D-D according to <FIG>. The first section plane C-C is essentially perpendicular to the longitudinally direction of the conductor <NUM>, and the second section plane D-D essentially extends in the longitudinal direction of the conductor <NUM>.

In the example illustrated in <FIG>, a further conductor <NUM> is arranged in the trench <NUM> in addition to the resistive conductor <NUM>. The further conductor <NUM> may be formed by the same process in which the field electrodes <NUM> are formed in the first transistor device <NUM>. The further conductor <NUM> is insulated from the semiconductor body <NUM> by an insulating layer <NUM>, which may be formed by the same process in which the field electrodes dielectrics <NUM> are formed in the first transistor device <NUM>.

Referring to <FIG>, the contact electrodes <NUM>, <NUM> may be arranged on top of an insulating layer <NUM> that separates the contact electrodes <NUM>, <NUM> from the semiconductor body <NUM>. In this example, the conductor <NUM> is connected to the first and second contact electrodes <NUM>, <NUM> through electrically conducting vias <NUM>, <NUM> that extend through the insulating layer <NUM>. The further conductor <NUM> may be implemented as a floating conductor which is insulated from the contact electrodes <NUM>, <NUM> and from the semiconductor body <NUM>.

<FIG> shows a modification of the resistor <NUM> illustrated in <FIG>. In the resistor <NUM> according to <FIG>, the conductor <NUM> and the further conductor <NUM> arranged below the conductor <NUM> are both connected to each of the first and second contact electrodes <NUM>, <NUM>. In this example, both conductors <NUM>, <NUM> contribute to the resistance of the resistor <NUM>.

<FIG> illustrates another example of the resistor <NUM>. In this example, only the first resistive conductor <NUM> is arranged in each trench and is connected to the first and second contact electrodes <NUM>, <NUM>. Within the trench, the conductor <NUM> is insulated from the semiconductor body <NUM> by the insulating layer <NUM>.

<FIG> illustrates another example of the resistor <NUM>. In this example, the resistor <NUM> includes a resistive layer <NUM> formed on top of the insulating layer <NUM>. The second nodes N41, N42 for contacting the resistor formed by the resistive layer <NUM> are only schematically illustrated in <FIG>.

<FIG> schematically illustrate one example for integrating the second transistor device <NUM> in the semiconductor body <NUM>. <FIG> shows a vertical cross-sectional view of a region <NUM> of the semiconductor body <NUM> in which the second transistor device <NUM> is integrated, and <FIG> shows a top view of the region <NUM> of the semiconductor body <NUM> in which the second transistor device <NUM> is integrated. The region <NUM> in which the second transistor device <NUM> is integrated is referred to as second transistor region in the following.

Referring to <FIG>, the second transistor region <NUM> is separated from a remainder of the semiconductor body <NUM> by an insulating region <NUM>. This insulating region <NUM>, in lateral directions of the semiconductor body <NUM>, surrounds the second transistor region <NUM>. In the vertical direction of the semiconductor body <NUM>, the insulating region <NUM> extends from the first surface <NUM> through the semiconductor body <NUM> to the second surface <NUM>. Those sections of the insulating region <NUM> that extend from the first surface <NUM> to the second surface <NUM> may be referred to as sidewall sections of the insulating region <NUM>.

According to one example, on top of the second surface <NUM> an electrode <NUM> may be formed. This electrode may be formed by the same electrode layer or metallization layer that forms the drain electrode <NUM> of the first transistor device <NUM> and the second contact electrode <NUM> of the capacitor <NUM>. In this example, the insulating region <NUM> includes a bottom section that separates the second transistor region <NUM> from the electrode layer <NUM>. The sidewall sections and the bottom section form a well-like structure that surrounds the second transistor region <NUM>.

<FIG> illustrates one example for implementing the second transistor device <NUM> in the second transistor region <NUM>. More specifically, <FIG> shows a vertical cross-sectional view of one section of the second transistor region <NUM> and the second transistor device <NUM> integrated therein.

In a similar way as the first transistor device <NUM> explained herein before, the second transistor device <NUM> may include a plurality of transistor cells <NUM>. Each transistor cells <NUM> includes a drift region <NUM> of a first doping type, a body region <NUM> of a second doping type separating the drift region <NUM> from a source region <NUM> of the first doping type, and a drain region <NUM> of the first to doping type separated from the body region <NUM> by the drift region <NUM>. Furthermore, each transistor cell <NUM> includes a gate electrode <NUM> dielectrically insulated from the body region <NUM> and configured to control a conducting channel in the body region <NUM> between the source region <NUM> and the drift region <NUM>.

The gate electrodes <NUM> of the individual transistor cells <NUM> are connected to a gate conductor <NUM> that is formed on top of the first surface <NUM> of the semiconductor body <NUM> and is insulated from the semiconductor body <NUM> by an insulating layer <NUM>. Electrically conducting vias <NUM> that extend through the insulating layer <NUM> connect the gate electrodes <NUM> to the gate conductor <NUM>. The gate conductor <NUM> forms the first drive node G2 or is connected to the drive node G2 of the second transistor device <NUM>.

The source and body regions <NUM>, <NUM> are connected to a source electrode, which is out of view in the cross-sectional view illustrated in <FIG>. The source and body regions <NUM>, <NUM> may be connected to the source electrode in the same way as the source and body regions <NUM>, <NUM> of the first transistor device <NUM> are connected to the source electrode <NUM> of the first transistor device.

Optionally, each transistor cells <NUM> further includes a field electrode <NUM> that is dielectrically insulated from the drift region <NUM> by a field electrode dielectric <NUM>. The field electrodes <NUM> are also connected to the source electrode (which is out of view in <FIG>).

Referring to <FIG>, the second transistor device <NUM> further includes a drain electrode <NUM> which is formed on top of the insulating layer <NUM>, so that the drain electrode <NUM> is formed on top of the first surface <NUM>. A doped connection region <NUM> extends from the first surface <NUM> down to the drain region <NUM> and is connected to the drain electrode <NUM> through electrically conducting vias <NUM> that extend through the insulating layer <NUM>. The doped connection region <NUM> is highly doped in order to achieve a low resistance between the drain electrode <NUM> and the drain region <NUM> of the second transistor device <NUM>.

Basically, the second transistor device is a vertical transistor device because the source regions <NUM> are spaced apart from the drain region <NUM> in the vertical direction of the semiconductor body <NUM>. However, different from the first transistor device <NUM>, which is also a vertical transistor device, the gate, source and drain electrodes <NUM>, <NUM> of the second transistor device <NUM> of formed on top of the first surface <NUM> of the semiconductor body <NUM>.

There are various ways for arranging the first transistor device <NUM> and the protection circuit <NUM> within the semiconductor body <NUM>. Different examples are explained with reference to <FIG> in the following. <FIG> and <FIG> each show a top view of the overall semiconductor body <NUM>, and <FIG> and <FIG> each show a detailed top view of a section of the semiconductor body <NUM> in which the protection circuit <NUM> or a portion of the protection circuit <NUM> is integrated. In each of these examples, the semiconductor body <NUM> may include only one section in which the protection circuit <NUM> is integrated. This is illustrated in <FIG> and <FIG> in which the solid lines labeled with reference number <NUM> schematically illustrated a section of the semiconductor body <NUM> in which the protection circuit <NUM> is integrated.

Alternatively, the semiconductor body <NUM> may include two or more sections in which the protection circuit <NUM> is integrated. In this case, the protection circuit <NUM> includes several sub-circuits that each include a second transistor device <NUM>, a capacitor <NUM>, and a resistor <NUM>, wherein each of these sub-circuits is connected between the first and second load path node D1, S1 of the first transistor device <NUM>. More specifically, each of these sub-circuits is connected between a source electrode <NUM> and the drain electrode <NUM> of the first transistor device <NUM>. In <FIG> the dashed line labeled with reference number <NUM> illustrates a further section of the semiconductor body <NUM> in which a portion of the protection circuit <NUM> may be integrated. Of course, the protection circuit <NUM> is not restricted to include only two sub-circuits circuits (as illustrated by the solid line and the dashed line in <FIG>) but may include a plurality of sub-circuits that each include a second transistor to, a capacitor <NUM>, and a resistor <NUM>.

<FIG> show a top view of the first surface of the semiconductor body <NUM>, so that the drain electrode <NUM>, which is formed on top of the second surface <NUM> is out of view in these figures. Equivalently, the second contact electrode <NUM> of the capacitor <NUM>, which may be formed by the same electrode or metallization layer as the drain electrode <NUM> of the first transistor device <NUM> is out of view in <FIG>.

Referring to <FIG> and <FIG>, the first transistor device may include several source electrodes <NUM> and several gate conductors <NUM>, wherein the gate conductors <NUM> are electrically connected to a gate pad <NUM> formed on top of the first surface <NUM> of the semiconductor body <NUM>. The gate pad <NUM> forms the drive node (gate node) G1 of the first transistor device <NUM>. The gate pad <NUM> is insulated from the semiconductor body <NUM> by an insulating layer (not illustrated), for example.

Referring to <FIG>, the gate conductors <NUM>, which may also be referred to as gate runners, may form a finger-like structure, wherein the fingers of the structure separate the source electrodes <NUM> from each other. According to another example illustrated in <FIG>, the gate runners <NUM> may entirely surround the source electrodes <NUM>. In the finished device, the source electrodes <NUM> are electrically connected with each other by bond wires, clips, or the like, wherein the source electrodes <NUM> together form the second drive node and second load path node S2 of the first transistor device <NUM>.

<FIG> shows a top view of the section of the semiconductor body <NUM> according to <FIG> in which the protection circuit <NUM> or a sub-circuit of the protection circuit <NUM> is integrated. For the ease of illustration, only the contact electrodes of the respective circuit elements of the protection circuit <NUM> are illustrated in <FIG>. Furthermore, the dashed lines in <FIG> schematically illustrate the position of the insulation region <NUM> that surrounds the second transistor region <NUM>, in which the second transistor device <NUM> is integrated.

In the example illustrated in <FIG>, the second transistor device <NUM> includes two source electrodes <NUM>, wherein each of these source electrodes <NUM> is connected to at least one source electrode <NUM> of the first transistor device <NUM>. Connections between the source electrodes <NUM> of the second transistor device <NUM> and the source electrode <NUM> of the first transistor device <NUM> are only schematically illustrated in <FIG>. These connections may be implemented using any kind of electrical conductors, such as bond wires. The drain electrode <NUM> of the second transistor device <NUM> is electrically connected to one of the gate runners <NUM> of the first transistor device <NUM>. Furthermore, the gate conductor <NUM> of the second transistor device <NUM> is electrically connected to an electrode or metallization layer which at the same time forms the first contact electrode <NUM> of the capacitor <NUM> and the first contact electrode <NUM> of the resistor. The capacitor <NUM> is integrated in the semiconductor body <NUM> below this electrode or metallization layer. Furthermore, a portion of the resistor is integrated in the semiconductor body below this electrode or metallization layer and extends in the semiconductor body <NUM> towards the second contact electrode <NUM> of the resistor. The second contact electrode <NUM> of the resistor <NUM> is connected to at least one of the source electrodes <NUM> of the first transistor device <NUM>.

In the example illustrated in <FIG>, the protection circuit <NUM> is integrated in an inner region of the semiconductor body. In the inner region of the semiconductor body <NUM> transistor cells of the first transistor device <NUM> are integrated. Thus, the area in which the protection circuit <NUM> is integrated is surrounded by those sections of the semiconductor body <NUM> that includes transistor cells of the first transistor device. Such transistor cells, however, are not illustrated in <FIG>.

Claim 1:
An electronic circuit, comprising:
a first transistor device (<NUM>) comprising a first drive node (G1), a second drive node (S1), and a load path (D1-S1); and
a protection circuit (<NUM>) coupled to the first and second drive nodes (G1, S1) and the load path (D1-S1) of the first transistor device (<NUM>),
wherein the protection circuit (<NUM>) comprises:
a second transistor device (<NUM>) comprising a first drive node (G2), a second drive node (S2), and a load path (D2-S2) connected between the first and second drive nodes (G1, S1) of the first transistor device (<NUM>); and
a capacitor (<NUM>) coupled between the load path (D1-S1) of the first transistor device (<NUM>) and the first drive node (G2) of the second transistor device (<NUM>),
characterised in that
a capacitance of the capacitor (<NUM>) is voltage dependent such that the capacitance decreases as a voltage (V3) across the capacitor (<NUM>) increases.