Patent Description:
It is known to provide data processing systems that support the virtualization of one or more guest execution environments. As an example, it is known to provide data processing systems using a hypervisor which controls and schedules the execution of one or more guest execution environments which themselves may include a guest operating system and one or more guest application programs. It is desirable within at least some uses of such systems that the data (potentially secret data) of a given guest execution environment should be protected from access by other processes within the system.

<CIT> describes example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method involves enabling a sharing of a memory page of a source domain executing on a first virtual machine with a destination domain executing on a second virtual machine. The example method also involves mapping the memory page to an address space of the destination domain and adding an address translation entry for the memory page in a table. In addition, the example method involves sharing the memory page with a hardware device for direct memory access of the memory page by the hardware device.

<NPL>, describes Mondriaan Memory Protection (MMP), which is a hardware/software design for fine-grained memory protection that can enforce module boundaries for systems written in unsafe languages. The paper presents the design of an MMP-based modular operating system kernel and shows how MMP can be used to provide module isolation while maintaining performance.

<CIT> describes a virtual computer system having a plurality of virtual computers, the virtual computer system including: an area assignment unit operable to, when a virtual computer attempts to perform writing to a basic area which is assigned to and shared by the plurality of virtual computers, change an assignment to the virtual computer from the basic area to a copy area to which the basic area is copied and the writing is performed; and an area freeing unit operable to, when a content of the basic area matches a content of at least one copy area, change area assignment to one or more virtual computers, to which have been assigned one or more other areas than one area among the areas whose contents match each other, to the one area, and free the one or more other areas.

<CIT> describes protection entries and techniques for providing fine granularity computer memory protection. A method of protecting a computer memory may include separating or parsing the computer memory, containing data or code, into blocks and creating protection entries for each block. The protection entries optionally include a reference field for identifying a block of memory, and a protection field for specifying one or more levels of access to the identified block of memory. The protection entries may then be used to pass messages between various system entities, the messages specifying one or more levels of access to the one or more blocks of memory or code.

Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which:.

Some specific examples of the present technique are discussed below.

<FIG> schematically illustrates an example of processes which can be executed by a data processing apparatus. A hypervisor <NUM> may manage a number of virtual machines (VMs, also known as guest operating systems or guest OS) <NUM>. Each VM <NUM> may manage one or more applications <NUM>. For example the hypervisor <NUM> may control which regions of an address space are allocated to each virtual machine <NUM> and control switching between the virtual machines <NUM>, e.g. scheduling interrupts to time share processing resource between the respective virtual machines <NUM>. Similarly, each VM <NUM> may control which regions of the address space are allocated to each application <NUM> executing under that VM <NUM>, and may control switching between the applications as required.

As shown in <FIG>, each process is associated with a given privilege level EL0, EL1, EL2, EL3. In this example higher numbered privilege levels are more privileged than lower numbered privilege levels, although it could be numbered the other way round in other examples. In this example, the applications <NUM> execute at privilege level EL0, the VMs <NUM> execute at privilege level EL1 and the hypervisor <NUM> executes at privilege level EL2. Typically, a process executing at a higher privilege level has rights not available to a process executing at a lower privilege level.

As shown in <FIG>, the hypervisor <NUM>, VMs <NUM> and apparatus <NUM> may operate in a normal domain. In addition, the apparatus may support a secure domain which is partitioned from the normal domain so that processes executing in the normal domain cannot access data or instructions associated with the secure domain. Hence, there may also be processes running in the secure domain, such as a secure operating system (OS) <NUM> and trusted applications <NUM> executing in the secure domain under control of the secure OS <NUM>. The secure OS <NUM> and trusted applications <NUM> execute at privilege levels S-EL1, S-EL0 respectively. A secure monitor process <NUM> is also provided at privilege level EL3 to manage transitions between the normal domain and the secure domain. The secure monitor process <NUM> may for example manage which regions of the address space are associated with the secure or non-secure domains, with some protection hardware being provided to prevent non-secure processes in the normal domain accessing data or instructions within the secure regions. An example of a technique for partitioning the normal and secure domains is the Trustzone® technique provided by ARM® Limited of Cambridge, UK, although other examples could also be used. The provision of a secure domain as shown in <FIG> is optional and other embodiments may not support the secure monitor <NUM>, secure OS <NUM> and trusted applications <NUM> for example.

The processes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> each use virtual addresses (VAs) to identify locations to be accessed in a data store such as memory. The VAs are translated into physical addresses (PAs) directly identifying corresponding storage locations. For an application <NUM> or a virtual machine <NUM>, the VAs are first translated into intermediate physical addresses (IPAs), and then the IPAs are translated into PAs. By providing two levels of address translation, the virtual machine <NUM> may control page tables for the VA to IPA translation to control which portions of the address space are allocated to each application <NUM>, and the hypervisor <NUM> may control page tables for the IPA to PA translation to control which portions of the address space are allocated to each virtual machine <NUM>, for example. For the other processes <NUM>, <NUM>, <NUM>, <NUM> the VAs are translated directly into PAs with the hypervisor <NUM> (in the normal domain) or the secure OS <NUM> (in the secure domain) for example controlling the page tables which control which portions of the address space each process can access.

Hence, there may be a number of processes which can be executed by a data processing apparatus. In typical systems, control over access to the address space is managed in a "top down" manner with processes at higher privilege levels controlling what addresses can be accessed by processes at lower privilege levels. For example, the hypervisor <NUM> at EL2 sets access permissions defining which addresses can be accessed by the virtual machines <NUM> at EL1. However, typically the process running at the higher privilege level can read or write to all the addresses associated with each process running under it at lower privilege levels. This can cause security issues for developers of processes operating at lower privilege levels. For example, in a cloud platform which implements a number of virtual machines <NUM> provided by different parties, one of the parties may wish to prevent data or code associated with the virtual machine <NUM> being exposed to the hypervisor <NUM>, which may be provided by a different party such as the cloud operator.

The present application introduces the concept of a "blind hypervisor" which still manages the virtual machines <NUM> and controls which portions of the address space they can access, but which cannot necessarily see all the data associated with a given virtual machine <NUM>. Similarly, for processes operating at other privilege levels, a process running at a higher privilege level can be prevented from accessing addresses which are used by a process running at a lower privilege level.

<FIG> shows an example of a data processing apparatus <NUM> comprising a number of bus masters including several processing circuits for processing data in response to instructions. In this example, the processing circuits include two central processing units (CPUs) <NUM>, a graphics processing unit (GPU) <NUM>) and a security complex <NUM> which is a dedicated processing unit for managing certain security functions as will be discussed below. The bus masters also include other devices which can execute processing tasks on behalf of one of the processing circuits, such as a direct memory access (DMA) controller <NUM> or an input/output (I/O) interface (not shown in <FIG>) for controlling input or output of data to an external device for example. It will be appreciated that other types of master devices could also be provided. A system bus <NUM> couples each of the bus masters to a memory controller (DMC) <NUM> which controls access to memory <NUM>. In this example, the memory is implemented using dynamic random access memory (DRAM), but it will be appreciated that other forms of memory or other types of data store could also be provided. Each bus master <NUM>, <NUM>, <NUM>, <NUM> may issue data access transactions (reads or writes) to the memory controller <NUM> via the bus <NUM>, and the controller controls the memory <NUM> to service the transactions.

A number of caches <NUM> are provided for caching data or instructions local to the processing circuits <NUM>, <NUM>. The CPUs <NUM> each have their own level <NUM> instruction cache and level <NUM> data cache but share a level <NUM> cache. The GPU <NUM> has a cache <NUM> for caching data or instructions. It will be appreciated that this is just an example of a possible cache hierarchy that could be used and other arrangements are possible. Each processing circuit (CPU or GPU) <NUM>, <NUM> also has a memory management unit <NUM> for translating between a virtual address (VA), intermediate physical address (IPA) and physical address (PA) and enforcing access permissions set by certain processes using page tables, as will be discussed in more detail below.

The CPUs <NUM> and GPU <NUM> can execute instructions from any of the types of processes discussed above with respect to <FIG>. Each of the processes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of <FIG> may be referred to as a "blind domain" (BD) and has a corresponding blind domain identifier (BDID). For some of the processes, BDIDs could be allocated arbitrarily to the respective processes. For example, the hypervisor <NUM>, secure monitor <NUM> or secure OS <NUM> could simply be assigned a corresponding BDID value. However, for other processes the BDID could be a concatenation of existing identifiers already assigned to the individual processes. For example, the BDID for a given application <NUM> executing under a particular virtual machine <NUM> may be formed at least in part from an application space identifier (ASID) associated with that application and a virtual machine identifier (VMID). A secure bit S indicating whether the process is associated with the secure domain or the normal domain could also be included in the BDID. In summary, each process is uniquely identifiable using its corresponding BDID.

A blind domain descriptor table (BDDT) <NUM> is provided within the memory <NUM> to track the state of each BD <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. For example, for each BDID, the BDDT <NUM> may specify a state of the blind domain as one of the following:.

For example, the BDDT <NUM> may specify a <NUM>-bit state field for each BDID to identify the state of the corresponding blind domain. The life cycle of states of a blind domain is described in more detail below. The BDDT entries for applications identified by ASID may be tracked using a VMID-to-ASID indirection table which maps a VMID of a given virtual machine <NUM> to the ASIDs of the applications <NUM> executing under that virtual machine <NUM>. It will be appreciated that the BDDT <NUM> may also include other information associated with a given BD, not just the state identifier mentioned above.

Each blind domain (BD) may protect its data or instructions from any other blind domain. Any BD may request that it becomes an owner BD for a selected page of the physical address space. A page ownership table (POT) <NUM> is stored in memory <NUM> tracking which BD (if any) is the owner BD for each physical page of memory. The owner BD (also referred to as an owner process) for a given page of memory has the exclusive right to control access to that page. For example, the owner BD can set attributes in the page ownership table <NUM> which control whether other BDs are allowed to access the page. Each bus master is provided with protection hardware <NUM>, <NUM> for enforcing the permission attributes set by the owner BD of a given page to prevent access requests targeting that page from other BDs being output onto the bus <NUM> if they violate the restrictions controlled by the owner BD. In this way, any process can prevent other processes (including higher privilege level processes) accessing its data or instructions.

As shown in <FIG>, the page ownership table (POT) <NUM> includes a number of entries <NUM> each corresponding to a different page of the physical address space. The POT <NUM> is indexed by physical address. Each entry <NUM> of the POT <NUM> includes the following information:.

It is also possible to store the claim counter <NUM> in a different location such as within registers of a CPU <NUM> or GPU <NUM> or a stack structure in memory <NUM>, so the claim count field <NUM> could be omitted from the POT <NUM> if desired.

The attribute field <NUM> of a POT entry <NUM> for a given page is set by the owner BD for that page, to provide the owner BD with exclusive control over the way in which other BDs access the page. The attribute field <NUM> may include a range of attributes for controlling access to the corresponding pages, for example:.

As shown in <FIG>, the memory controller <NUM> may include encryption circuitry <NUM> for encrypting data written to memory <NUM> and decrypting data read from the memory <NUM>. The encryption circuitry <NUM> may maintain a number of secret encryption keys and each BDID may have its own key. The encryption circuitry <NUM> supports a number of different levels of encryption, ranging from no encryption at all (data is written to the memory in the clear), through successively stronger forms of encryption. In general, the stronger the encryption, the greater security, but the greater resource is consumed in encrypting and decrypting the data.

In some implementations, a given BD may specify the same level of encryption for all the pages owned by it. If the level of encryption is the same for all pages owned by a BD, an alternative would be to specify the level of encryption in that BD's entry in the BDDT <NUM>, instead of in each POT entry <NUM> for the pages owned by the BD. However, specifying the level of encryption in the page table allows for faster performance because then the encryption circuitry <NUM> only needs to read one table <NUM> to identify both the owner BD for the page and the level of encryption, rather than reading the POT <NUM> and the BDDT <NUM>.

However, in other embodiments, an owner BD may specify different levels of encryption for different pages that it owns. By allowing the owner BD to select the level of encryption required on a page by page basis, the strongest encryption can be reserved for the pages which really need it and pages storing less sensitive information can use a weaker level of encryption to save energy. This allows a better balance between security and energy consumption.

Hence, on a write the encryption circuitry <NUM> checks the POT entry <NUM> for the target address to determine the level of encryption applied to the corresponding page. The encryption circuitry <NUM> selects the appropriate encryption key for the owner BD indicated in the BDID <NUM> field of that POT entry <NUM>, and encrypts the data using the key and the specified level of encryption, before writing the encrypted data to memory <NUM>. Similarly, on a read access, the encryption circuitry <NUM> checks the POT entry <NUM> for the corresponding page to determine the level of decryption required and which owner BD's key should be used for the decryption, decrypts the data read from memory <NUM> and then outputs the decrypted data over the bus <NUM> to the master that requested the data.

Hence, each process can become an owner for a corresponding page of physical addresses and has exclusive control over whether other processes can access that page, including control over processes at higher privilege levels. This enables a virtual machine <NUM> for example to prevent a hypervisor <NUM> accessing its data or instructions, to address the problems discussed above.

Enforcement of the policy set in the page ownership table <NUM> is carried out by a blind domain management unit (BDMU) <NUM> associated with each processing circuit <NUM>, <NUM>, <NUM>. As shown in <FIG>, the BDMU <NUM> may act as a further stage of transaction validation which operates on transactions which have passed any checks performed by the memory management unit (MMU) <NUM>.

As shown in <FIG> the MMU <NUM> may include a stage <NUM> MMU (S1 MMU) <NUM>-<NUM> and a stage <NUM> MMU (S2MMU) <NUM>-<NUM> for providing two stages of address translation respectively. The transactions input to the MMU comprise a virtual address <NUM> to be accessed, a transaction type attribute <NUM> specifying whether the transaction is a read or write transaction, an ASID <NUM> identifying the application <NUM> which issued the transaction, and a VMID <NUM> identifying the virtual machine <NUM> under which that application <NUM> is executing. The ASID and VMID may together be considered to form a context identifier identifying the context in which the transaction was executed.

The S1MMU <NUM>-<NUM> looks up the virtual address <NUM> and ASID <NUM> in a stage <NUM> translation lookaside buffer (S1TLB), which is a local cache within the S1MMU for caching a subset of entries from stage <NUM> (S1) page tables <NUM> stored in memory <NUM>. In the normal domain, the S1 page tables <NUM> are set by the virtual machine <NUM> which controls the application <NUM>, and in the secure domain the S1 page tables <NUM> are set by the secure OS <NUM>. Each S1 page table entry specifies a VA-PA or VA-IPA mapping for a corresponding page of the virtual address space together with attributes specifying whether the corresponding ASID has read or write permission for the corresponding page. If the S1TLB does not contain a corresponding entry for the VA <NUM> and ASID <NUM>, a page table walk is performed to fetch the required entry from the S1 page tables <NUM>. Once the required entry is in the S1TLB, the S1MMU <NUM>-<NUM> checks whether an access of the type specified by the read/write attribute <NUM> is permitted for the specified ASID <NUM> and virtual address <NUM>. If the access is not permitted then the transaction is rejected and a stage <NUM> access violation may be signalled. On the other hand, if the permissions are satisfied then a translated PA or IPA <NUM> corresponding to the input VA <NUM> is output.

If the input transaction was issued at one of exception levels S-EL0, S-EL1, EL2 or EL3, then the output of the S1MMU <NUM>-<NUM> is a PA and the stage <NUM> MMU <NUM>-<NUM> can be bypassed.

However, if the input transaction was issued by an application <NUM> or virtual machine <NUM> executing at EL0 or EL1, then the S2MMU <NUM>-<NUM> performs further address translation and access permission checking. The S2MMU <NUM>-<NUM> includes a stage <NUM> TLB (S2TLB) which caches a subset of entries from stage <NUM> (S2) page tables <NUM> in memory <NUM>. The S2 page tables <NUM> are set by the hypervisor <NUM> (for the normal domain) or the secure OS <NUM> (for the secure domain). The S2MMU <NUM>-<NUM> looks up the S2TLB to check whether there is an entry for the specified IPA <NUM> and VMID <NUM>, and if not performs a page table walk to fetch the required entry from the S2 page tables <NUM>. When the required entry is in the S2TLB, the S2MMU <NUM>-<NUM> checks whether a transaction of the type specified in the attributes <NUM> is permitted, and if so outputs a translated PA <NUM> corresponding to the IPA <NUM>. If the transaction is not permitted, a stage <NUM> access violation is flagged and the transaction is rejected.

Hence, each stage of the MMU <NUM>-<NUM>, <NUM>-<NUM> can be considered to be access control circuitry for checking whether an access request satisfies access permissions set by a predetermined process at a given privilege level (e.g. the S1 MMU <NUM>-<NUM> enforces the permissions set by the virtual machine <NUM> or the secure OS <NUM>, and the S2MMU <NUM>-<NUM> enforces the permissions set by the hypervisor <NUM>).

The physical address <NUM> is then passed to the BDMU <NUM> to enforce any access controls set by the owner BD in the POT <NUM> for the corresponding page of the physical address space. In a similar way to the TLBs within each stage of the MMU <NUM>, the BDMU <NUM> may include lookaside buffers for caching portions of the POT <NUM> and BDDT <NUM> from memory <NUM> (see <FIG> below). Hence, when a physical address <NUM> is received (whether from a physically addressed transaction from EL2, EL3 or S-EL1, or translated from a VA or IPA by the MMU <NUM>), the BDMU <NUM> checks whether the required POT entry <NUM> and BDDT entry are in the respective lookaside buffers, and if not the required entries are fetched from memory <NUM>. Once the required entries are available, the physical address is validated using a series of checks as follows:.

If any of these checks fails, the access is rejected and an access violation triggered. Otherwise, the physically address transaction is validated and is output onto the system bus <NUM>. It will be appreciated that the checks described above could be performed in any order or could be performed at least partially in parallel.

Similarly, the BD filter <NUM> may control whether a transaction targeting a particular page of the physical address space is output onto the system bus <NUM> based on whether the owner of that page has marked the page as "IO" type in the attribute field <NUM> of the corresponding POT entry <NUM>.

Hence, as shown in <FIG>, each bus master <NUM>, <NUM>, <NUM>, <NUM> coupled to the system bus <NUM> may be provided with either a BDMU <NUM> or a BD filter <NUM> for validating physically addressed transactions, so that all transactions output on the system bus are validated transactions specifying physical addresses and so there is no need for any subsequent validation at the memory controller <NUM>. An alternative would be to move the BDMU functionality <NUM> to the memory controller <NUM> so that transactions which have been validated by the MMU <NUM>, but not yet compared against any permissions set in the POT <NUM> by the page owner, are output onto the bus and then checked against the POT <NUM> when they reach the memory controller <NUM>. However, providing the BDMU <NUM> is advantageous because it reduces bus traffic by preventing transactions which would fail the POT <NUM> checks being output onto the bus, and avoiding the need for additional tags to be transmitted from the bus masters to the memory controller identifying the current context BD associated with each transaction. Conversely, the encryption/decryption circuitry <NUM> is provided at the memory controller <NUM> so that data written to memory can be encrypted to prevent hardware attacks, but there is no need for the bus masters <NUM>, <NUM>, <NUM>, <NUM> themselves to have any encryption capability.

<FIG> shows a method of checking whether a data access transaction (access request) issued by one of the processing circuits <NUM> is permitted. At step <NUM> an input transaction is received specifying a VA <NUM>. At step <NUM> the S1MMU <NUM>-<NUM> looks up the S1TLB for an entry corresponding to the input VA <NUM> and the current context (VMID, ASID). The S1 MMU <NUM>-<NUM> checks whether there is a violation of the access permissions set in that entry. If there is a S1 access violation, then at step <NUM> the transaction request is rejected. If there is no S1 access violation, a translated IPA or PA is output. Also, the PISG state (expected sharing attribute) for the page is output by the S1 MMU <NUM>-<NUM>, as will be discussed in more detail below. If the transaction was issued at EL2, EL3, S-EL0 or S-EL1 then the translated address is a PA and the S2MMU <NUM>-<NUM> is bypassed. If the transaction was issued at EL0 or EL1 then the output address is an IPA and a second stage of address translation is performed. In this case, the S2MMU MMU <NUM>-<NUM> similarly looks up the S2TLB for an entry corresponding to the IPA <NUM> and the current context (VMID). The access permissions in that entry are checked and if there is an access violation then again the request is rejected at step <NUM>. If the access is permitted by the S2MMU <NUM>-<NUM> then the IPA is translated into a PA <NUM> which is output to the BDMU <NUM>.

Hence, provided there is no access violation at either the stage <NUM> or stage <NUM> address translation, a physical address is obtained. At step <NUM> the physical address is provided to the BDMU <NUM> which checks whether the current context's BDID is shown in the BDDT <NUM> as being in the "Execute" state. If not, then at step <NUM> the request is rejected. In order to progress to the Execute state, that BDID would first need to progress through the "Scrub" and "Prepare" states as will be discussed below. This step of validating the BDID prevents the secure initialisation process being circumvented by issuing accesses for BDIDs which have not yet been initialised securely. Again, a local lookaside buffer caching some recently seen entries of the BDDT <NUM> may be maintained within the BDMU <NUM> to speed up checking of BDDT entries.

If the current context's BDID is validated as in the "Execute" state, then at step <NUM> the BDMU <NUM> checks the POT entry <NUM> corresponding to the required physical address <NUM> (the notation POT[PA] refers to the corresponding POT entry <NUM>). Again, this may be accessed within a local POT lookaside buffer provided within the BDMU <NUM> for caching a subset of recently encountered POT entries for quicker access. The BDMU checks whether the corresponding POT entry <NUM> identifies the current context's BDID as the owner BD for the target page. If not, then at step <NUM> the BDMU checks whether the sharing attribute for the corresponding POT entry <NUM> is marked as either "Global" or "Shared" with the specific BDID of the current context. The BDMU <NUM> may also check whether the read/write type of the access request matches the permitted types defined for BD's other than the owner in the attribute field <NUM> of the corresponding POT entry <NUM>. If these checks are passed, then at step <NUM> the BDMU validates the transaction and outputs it onto the system bus <NUM>. On the other hand, if the page was not shared with the current context's BDID (e.g. the page was Private or Shared with a different BD only), or the access request specified a write but the page is marked Read only, then the request is rejected at step <NUM>.

On the other hand, if at step <NUM> the current context is the owner BD for the corresponding page, then there is no need to check the sharing attributes <NUM> since the owner BD is permitted to access its own page. However, at step <NUM>, if the source of the transaction is at privilege level EL0, EL1 or S-EL0, then the BDMU <NUM> checks whether the VA or IPA of the transaction matches the VA or IPA stored in the address field <NUM> of the corresponding POT entry <NUM>. For transactions issued at EL0 or S-EL0, the BDMU <NUM> checks whether the VA of the transaction matches the VA in the address field <NUM>, while for transactions issued at EL1, the BDMU <NUM> checks whether the IPA of the transaction matches the IPA in the address field <NUM>. If there is a match, the transaction is validated and output on the bus <NUM> at step <NUM>. If the addresses do not match, the request is rejected at step <NUM>.

It may not be immediately apparent why this last check of the VA or IPA against the VA or IPA recorded in the POT <NUM> is useful. Consider the following situation:
A hypervisor <NUM> may for example allocate two physically addressed pages PA0, PA1 to a particular virtual machine <NUM> with address mappings in the S2 page tables <NUM> as follows:.

The virtual machine <NUM> could then take ownership of both of these pages and set the sharing attribute in the POT <NUM> as follows:.

The virtual machine <NUM> could then for example include some code writing sensitive data to IPA4 (which the VM <NUM> would expect to have been marked as Private in the POT <NUM>), to prevent other processes accessing this data.

However, before the VM <NUM> starts the secure portion of the code for writing the sensitive data, the hypervisor <NUM> could modify the S2 page tables <NUM> as follows:.

If the VM <NUM> now executes its secure portion of the code using intermediate physical address IPA4, this would now be mapped to a different physical address PA0, which is marked in the POT <NUM> as a "Global" page. The VM <NUM> would write its sensitive data to the "Global" page, exposing this information to any other process including the hypervisor <NUM> itself.

This problem can be avoided by providing information <NUM> in the POT <NUM> to "lock" the address mapping for an owned page to a certain mapping, so that an access violation can be triggered if another process changes the address mappings in the page tables <NUM>, <NUM> after the ownership attribute information has been set in the POT <NUM>. For example, when a page is claimed by an owner BD, the current VA-PA or IPA-PA mapping at the time of claiming the page may be recorded using the address field <NUM> of the POT entry <NUM> corresponding to that physically addressed page. In the example above, the POT <NUM> might be as follows:.

Later, when the VM <NUM> attempts to access the private page using intermediate address IPA4, if the hypervisor <NUM> has in the meantime remapped IPA4 to point to PA0, this will be detected because the intermediate address of the access, IPA4, will now match the intermediate address IPA9 in the POT entry <NUM> for physical page PA0. Therefore, an error can be flagged and the VM <NUM> can halt its secure processing to avoid exposing sensitive information to other processes. This avoids attacks of the type discussed above. The VM <NUM> could then request ownership of IPA4 and IPA9 again to set the required access control permissions for the physical pages PA0, PA8 which are now mapped to these IPAs.

Hence, including a reverse address translation mapping in the POT <NUM> can help to avoid attacks of the type described above caused by changes in the page tables. While the example above discusses a hypervisor modifying the page table mappings for a page owned by a virtual machine <NUM>, a similar technique can be used to prevent a virtual machine <NUM> modifying the page table mappings for a page owned by an application <NUM> or trusted application <NUM>, in which case a VA would be stored address field <NUM> rather than the IPA.

Although not shown in <FIG>, the method of validating the transaction may also include an additional step of validating whether the "Sharing" attribute of the POT entry <NUM> corresponding to the target PA matches an expected attribute specified in the S1 page table entry for the corresponding VA. When a page owner sets the Sharing attribute for a given page (which indicates whether the page is Private, IO, Shared or Global as discussed above), this may also trigger an update of the S1 page tables so that the corresponding page table entry specifies a corresponding attribute. In some cases, the page table entry could be updated initially only in the S1 TLB, and then the S1 page tables <NUM> in memory could be updated later when the corresponding page table entry is evicted from the S1 TLB. Later, when an access request is issued to that page, the S1 MMU <NUM> may output the expected Sharing attribute (PISG type) specified in the corresponding S1 page table entry, and the BDMU <NUM> may check whether the expected Sharing attribute matches the Sharing attribute specified in the POT entry <NUM> corresponding to the PA. If there is a match, then the access request can be validated (subject to the other checks described above). However, if the actual Sharing attribute does not match the expected Sharing attribute specified in the S1 page table entry, then the access request is rejected. This guards against potential attacks as follows.

For example, a given BD may claim ownership of a given physical page and mark it as Private in preparation for writing sensitive information to that page. However, before the BD starts writing the sensitive information, another BD could claim ownership of the same page and could mark that page as Global. When the previous owner BD then attempts to write the sensitive information to the page, as the page is marked Global by the current owner, the request could be validated, and so this could potentially lead to exposure of the sensitive information to other processes. This can be avoided by writing information to the corresponding page table entry indicating the page sharing type expected for that page, and checking whether this matches the actual sharing type recorded in the POT when accessing that page.

In the above example, the expected Sharing attribute (PISG type) is specified in the S1 page tables, but other examples could specify this in the S2 page tables. Also, in some cases some pages may have the expected Sharing attribute specified in the S1 page tables while other pages have the Sharing attribute specified in the S2 page tables, depending on which process set the Sharing attribute.

In summary, the BDMU <NUM> provides an additional layer of access permission checking on top of the MMU <NUM>, so that validation of transactions requires checks to be passed in both the MMU <NUM> and BDMU <NUM>. Whereas the MMU <NUM> checks permissions set by processes at certain privilege levels (e.g. EL1 controls the S1 page tables and EL2 controls the S2 page tables), the BDMU <NUM> enforces permissions which can be applied to particular pages by owner processes executing at any privilege level. Hence, while the hypervisor <NUM> for example can still allocate particular regions of the address space to a particular virtual machine <NUM> and prevent other VMs <NUM> accessing those regions using the S2MMU <NUM>-<NUM> and S2 page tables, the virtual machine <NUM> itself can prevent the hypervisor <NUM> accessing some pages within its allocated "pool" of pages by setting suitable permissions in the POT <NUM> to control the BDMU <NUM> to reject any requests from the hypervisor <NUM> for those pages. This enables a system in which each "blind domain" can enforce its security so that it can hide data from any other domain within the system.

<FIG> shows an example of a method by which a BD may request ownership of any page of the physical address space to which it has write access. On requesting ownership of a page, it is possible that a previous owner of the same physical page may previously have written secure data to that page. To prevent leakage of data when ownership of a page transfers between different BDs, the new owner may be required to complete an overwriting process <NUM> for overwriting the data in each location of the requested page before becoming the valid owner of the page. The particular data value written to each location does not matter, so long as the previous data is overwritten - e.g. each location could be written with a <NUM> or any other dummy value. By requiring the new owner to perform a destructive claim sequence to overwrite any existing data within a page before it can validly claim ownership, security of data can be enforced even once a particular BD which previously owned a given page is no longer in existence (for example the hypervisor <NUM> may have terminated execution of a given VM <NUM>). In some examples, some dedicated hardware could be provided within the processing circuits <NUM>, <NUM>, <NUM> to perform the overwriting sequence when page ownership is requested. However, in the example given below the software associated with the new owner BD performs the overwriting by triggering a series of writes to each location of the page being claimed, but some control hardware in the processing circuitry <NUM>, <NUM>, <NUM> executing that software checks whether the new owner BD has successfully completed the overwriting process <NUM> and prevents the page being marked as valid in the POT <NUM> until this is done.

The ownership request may for example correspond to the prospective owner BD executing an ownership claim instruction specifying an address corresponding to the page to be claimed. At step <NUM> an ownership request is received specifying a VA to identify the page for which ownership is requested. At step <NUM>, the MMU <NUM> determines whether write access is permitted for the specified page, and if either stage <NUM> or stage <NUM> of the MMU <NUM> determines that write access is not permitted, then at step <NUM> the request is rejected. Hence, a BD is prevented from claiming ownership of a page to which it is not itself allowed to write data. If write access is permitted, then the VA is translated into a PA (either directly or via an IPA) and the PA is output.

The method then proceeds with the overwriting procedure <NUM> for overwriting the data in each location of the page corresponding to the target PA. The claim counter <NUM> described above is used by the control hardware to track the progress of the overwriting process and count the number of lines of the page that have been overwritten so far. At step <NUM> the overwrite counter <NUM> is initialised to point to the first address in the page, e.g. the address which has an offset of zero from the base address of the page. At step <NUM> the control hardware waits for the requester BD (the BD which requested ownership) to trigger a write. When a write is performed, at step <NUM> the control hardware checks whether the target address of the write is correct. For example, the control hardware may require that the requester BD iterates through each line of the page in a fixed order, so may simply check whether the next address has been written to (e.g. whether the write offset matches the increment counter). If the address is not correct, then at step <NUM> the ownership request is rejected and the page marked in the POT as invalid, to prevent the requesting BD circumventing the overwriting procedure by writing to other addresses not in that page, or repeatedly writing to the same address, for example. When the ownership request is rejected, if the requester BD wishes to request ownership again, they will have to start again with a new ownership request and correctly complete the overwriting procedure <NUM>.

If the target address was correct at step <NUM>, then at step <NUM> the control hardware increments the overwrite counter. At step <NUM> the control hardware checks whether the requesting BD has declared that it has reached the end of the ownership claim process. For example, the requesting BD may execute an ownership claim end instruction to flag that it has finished the overwriting procedure <NUM>. If the ownership claim end has not been reached then the method returns back to step <NUM> to check for the next line of the page to be overwritten. The process loops through steps <NUM> to <NUM> a number of times for each line of the page. Eventually the requesting process declares that it has reached the end of its overwriting procedure <NUM>, and at step <NUM> the control hardware checks whether a full page has been written (e.g. whether the overwrite counter matches the number of lines in the page). If a full page has not been written, the ownership request is again rejected at step <NUM> and the page marked as invalid in the POT <NUM>. If the full page has been written, then the page is marked as valid at step <NUM> so that the requester BD now becomes the valid owner of the page and so can exclusively control access to the page. Also, the PISG type (Sharing attribute) for the page is written to the corresponding POT entry <NUM>. In some cases, newly claimed pages may by default be marked as Private initially, with a subsequent change of attribute being required (e.g. as shown in <FIG> or <FIG> below) if the new owner wishes to change the page to IO, Shared or Global. Alternatively, it may be possible to specify in the initial ownership request what value of the Sharing attribute is to be specified for that page. Updating the Sharing attribute may also trigger an update to the corresponding page table entry in the S1 TLB and/or S1 page tables <NUM>, to encode the expected Sharing type so that it can be validated against the POT sharing attribute on later accesses to memory.

At step <NUM> if the requester BD is a process at EL0 or S-EL0 then the VA specified in the ownership request is written to the address field <NUM> of the POT entry <NUM> for the claimed page, while if the requester BD is a process at EL1 then the IPA obtained by the MMU is written to the address field <NUM>, to lock the reverse PA-VA or PA-IPA mapping into the POT to prevent against the attacks of the type discussed above. It will be appreciated that in other embodiments step <NUM> could be performed earlier, e.g. as soon as the ownership request was received. Similarly, the BDID of the requester process could be written to the POT <NUM> at any time during the method shown in <FIG>, as long as the POT entry <NUM> does not become valid until step <NUM>.

An example of some pseudocode for the requester BD to execute the ownership request and the overwriting procedure <NUM> is shown below:
BD. Invalidate(VA1) // broadcast page invalidate
BD. Start(VA1) // requires an invalid page
line = (*64byte_ptr) VA1
do while ( line < (VA1 + PAGESIZE) )
DC2. WT(line++) // ordered zeroing of page
BD. End(VAl) // make page valid.

<FIG> is a flow diagram explaining the pseudocode. An application for example wishes to claim ownership of a page corresponding to virtual address "VA1". Before requesting ownership, the requester BD executes an invalidate instruction (BD. lnvalidate) to invalidate any POT entries associated with address VA1 from any lookaside buffers within the BDMUs <NUM>. This ensures that following the ownership claim, old data will not be resident with the lookaside buffers. Hence, at step <NUM> of <FIG> the page is initially in the Invalid state. The requester BD then executes a page claim start instruction (BD. Start) to issue an ownership request. This causes the physically addressed page PA1 (whose address is obtained by translating VA1 using the MMU <NUM>) to transition to the "Claiming" state. The BDID of the Requester (Caller) BD is written to the BDID field <NUM> of the POT entry <NUM> for page PA1. Virtual address VA1 which currently maps to PA1 is written to the address field <NUM>. The claim counter is initialised at zero.

The requesting process then executes a data zeroing instruction (DCZ. WT) to start the first overwriting operation. In this example, the data zeroing instruction zeroes <NUM> bytes of the page at a time, but it will be appreciated that other examples could act on blocks of data of other sizes. At step <NUM> the control hardware checks whether the write offset of that instruction matches the claim count. If there is no match, the request is rejected and the page transitions back to the "Invalid" state at step <NUM>, so the requester BD will have to execute another BD. Start instruction if they want to make another attempt at claiming ownership. On the other hand, if the write offset matches the claim count, then at step <NUM> the claim counter <NUM> is incremented, and the requester BD executes another data zeroing instruction DCZ. WT at step <NUM>. Steps <NUM>, <NUM>, <NUM> loop until the requester BD executes the page claim end instruction (BD. End) to signal it has finished all the overwriting operations. At step <NUM>, the control hardware checks that the claim counter matches the number of addresses in the page. If the number of bits of the claim counter is selected corresponding to the page size, the claim counter will overflow when all the locations in the corresponding page have been written to, so the control hardware can simply check the overflow bit of the claim counter which if equal to <NUM> will show that the overwriting procedure was completed. If the claim counter has not overflowed at step <NUM>, then the page again transitions back to the invalid state at step <NUM> and the requester BD will have to start again to claim ownership. If the claim counter has overflowed at step <NUM>, then at step <NUM> the page PA1 becomes valid and now the owner can set the attributes for this page.

A similar destructive overwriting procedure <NUM> can also be performed when recycling a particular BDID for use by a new process. For example, to transition a given BDID from the "Invalid" state to the "Prepare" state, the BDID is first transitioned to the "Scrub" state. While in the "Scrub" state, the hardware may check that the overwriting procedure <NUM> is performed to overwrite each address within each page for which the given BDID is currently shown as the owner in the POT <NUM>. The hardware may also require that each POT entry <NUM> associated with that BDID is invalidated. The actual overwriting operations may be performed in software by the hypervisor <NUM> or other process requesting that a new BD is established, but the hardware may check that the overwriting procedure is successfully completed and prevent the BDID transitioning to the "Prepare" state until it has been successfully completed. This prevents sensitive information associated with the old process having that BDID from being leaked to a new process sharing the same BDID.

Other embodiments could omit the "Scrub" state, but a transition from the "Invalid" state to the "Prepare" state could be prohibited until the overwriting process has been successfully completed to overwrite the data in each page recorded in the POT <NUM> as being owned by the corresponding BDID and invalidate each POT entry <NUM> associated with that BDID.

<FIG> shows a method for the owner BD of a given page to update the attributes in the POT <NUM>. At step <NUM> a POT update request is issued specifying a VA identifying the target page and one or more attributes to be written to the POT entry <NUM> for that page. At step <NUM> the MMU <NUM> checks whether write access to that page is permitted, and if either the S1 or S2 MMU <NUM>-<NUM>, <NUM>-<NUM> signals an access violation then the request is rejected. If write access is permitted, then a translated PA is obtained (either directly from the VA or via an IPA).

At step <NUM> the POT <NUM> is looked up using the physical address to determine whether the current context BD which issued the update request is the owner BD for the required page. If not then at step <NUM> the request is rejected.

If the current context BDID is the owner for the required page then at step <NUM> the address field <NUM> is checked against the VA/IPA of the update request (for requests originating from EL0, EL1 or S-EL0), to check whether the address mapping is still the same as when the POT entry <NUM> was allocated. If not, then at step <NUM> the update request is rejected. If the addresses match, then at step <NUM> the attributes of the corresponding page ownership table entry are updated based on the attributes specified in the update request. For example, the owner of the page could change the attributes so that a private page is now made shared or a shared page is made private, or could change whether read or write is permitted for that page. If there is a change to the sharing attribute, then this may also trigger a corresponding update to the expected sharing attribute (PISG state) recorded in the S1 page table entry in the S1 TLB or page tables <NUM>.

Step <NUM> is optional and another embodiment could proceed from step <NUM> direct to step <NUM>, since the change of address mapping could in any case be detected when a memory access is later issued as shown in <FIG> above. Nevertheless, if a change of address mapping is flagged when updating the POT attributes, this could flag earlier to the owner BD that there is a potential problem.

As shown in <FIG>, the BDMU <NUM> may have a page ownership table lookaside buffer (POTLB) <NUM> for caching recently accessed entries of the POT <NUM> and a BDDT lookaside buffer (BDDTLB) for caching recently accessed entries of the BDDT <NUM>. These operate in an analogous way to the TLBs <NUM> within the MMU <NUM>. As shown in the lower part of <FIG>, the system bus <NUM> and processing units <NUM>, <NUM>, <NUM> may support invalidation instructions for invalidating entries of the POTLB <NUM> or BDDTLB <NUM>. When a processing unit <NUM>, <NUM>, <NUM> executes one of these instructions, a command is broadcast over the bus <NUM> to each of the BDMUs <NUM> in the system, to trigger each BDMU <NUM> to invalidate entries from the TLBs <NUM>, <NUM>. Instructions <NUM>, <NUM> are for invalidating entries of the POTLB <NUM>. They can be used just prior to claiming ownership of a page or updating attributes in the POT <NUM> for example. Instruction <NUM> triggers a BDMU <NUM> to invalidate all its entries from the POTLB <NUM>. Instruction <NUM> triggers a BDMU <NUM> to invalidate only those entries of the POTLB <NUM> which correspond to a specified page address (if the instruction specifies a VA or IPA, it is translated to a PA by the MMU and a physically addressed invalidate transaction is broadcast to the BDMUs <NUM> to invalidate the corresponding POT entries). Similarly, instructions <NUM>, <NUM> are for invalidating entries of the BDDTLB <NUM>, with instruction <NUM> triggering invalidation of all entries of the BDDTLBs <NUM> and instruction <NUM> invalidating only entries associated with a specified BDID. Following invalidation, when a subsequent access request requiring a particular BDID or page is encountered, the corresponding entries would need to be fetched from the main BDDT <NUM> or POT <NUM> in memory <NUM>.

In some cases similar invalidation commands could be generated automatically as a result of other instructions executed by a given BD. For example, when a process executes an invalidation instruction to invalidate an entry of the POT <NUM>, this could automatically result in generation of a broadcast invalidation command by hardware within the processing circuit <NUM>, <NUM>, BDMU <NUM> or memory controller <NUM> to trigger corresponding invalidations of entries in the BDMUs <NUM>. Similarly, an update to an POT entry, or a lifecycle update or change in the status of a BD could result in an invalidation of POT or BDDT entries in the BDMUs <NUM>.

Some specific examples have been discussed above. However, the technique is not limited to these precise examples. For instance, the examples above manage ownership of blocks of memory in units of pages, but the POT <NUM> could have entries corresponding to blocks of physical addresses of some other size (which could be multiples of pages or could correspond to more arbitrary blocks of addresses which do not necessarily need to correspond with the same sized pages used by the MMU <NUM>).

While the examples above show a system comprising one page ownership table <NUM>, in some cases there could be multiple POTs <NUM> in the same system. For example, if there are multiple memory controllers for controlling different DRAMs which are disjointed in physical memory, then it could be useful to provide a separate POT <NUM> for each memory controller/DRAM.

Also, while the examples above show the commands for controlling and updating the POT being issued by the owner process, in other examples these commands could come from another process which is trusted by the owner process. For example, in some systems the POT <NUM> could be managed on behalf of the owner domains by a process running on the security controller <NUM>. Hence, when the owner process requires ownership of a page to be requested or an update to the POT <NUM>, it could send a command to the trusted process (e.g. a process running on the security controller <NUM>) which triggers the trusted process to issue an ownership request or update request. Similarly, the overwriting (destructive claiming) process described above could be performed by a trusted process which is not necessarily the owner process.

Also, while examples above describe executing an instructions to trigger an ownership request or POT update request, in other examples a request for ownership or table update could be triggered by other forms of commands. For example, the commands could be instructions, a direct I/O operation to a hardware controller for controlling the POT, or a (trusted) function call. Similarly, the ownership claim start and end commands need not necessarily be instructions and could be other forms of command.

<FIG> schematically illustrates the secure initialization of a guest execution environment (GEE). The guest execution environment can take a number of different forms, e.g. a stand alone application, an operating system supporting execution of one or more application programs, or even a further virtualization system. The secure initialization is started by the sending of a request to initiate a guest execution environment from a source of executable code for that guest execution environment. The request to initiate is sent to a hypervisor. The request may, for example, be the result of a user wishing to initiate some desired processing using a virtualized computer system (cloud based computing system) controlled by the hypervisor. The request to initiate the guest execution environment is accompanied at the same time (or potentially at a later time) by an encrypted version of executable code for at least the first portion of the execution of the guest execution environment. This encrypted executable code may be encrypted to help protect its security during transfer to its intended recipient in a variety of different ways. In this example, the encrypted executable code is encrypted with a public key of a public/private key pair. The private key pair is held by, and secret, to a security controller (described later).

The hypervisor receives the request to initiate the guest execution environment creates a new virtual machine (VM) and allocates with the physical memory address space the pages to be used by the guest execution environment as well as setting up other parameters associated with the guest execution environment, as is normal in the action of a hypervisor. The hypervisor then forwards to the security controller the request for initialization of the guest execution environment, the encrypted executable code, page identifiers indicating the pages of physical memory address space that have been allocated by the hypervisor to the guest execution environment and a blind domain identifier to be used by the guest execution environment. It will be understood that in a typical system the hypervisor will allocate a large amount of physical memory address space to a guest execution environment which may use some or all of this allocated address space in its operation. In the present example embodiment the security controller (and later the guest execution environment itself) first destructively claims any pages of the physical memory address space it wishes to use, from among those already allocated by the hypervisor as available for use by the guest execution environment as owned by the security controller and subsequently the guest execution environment.

The security controller receives the request forwarded from the hypervisor and destructively claims all pages into which it wishes to install the encrypted executed code. The security controller marks the process that is claiming and scrubbing into a state "scrub" as indicated in a process descriptor entry for the requested process while they are being claimed and scrubbed. The process is then marked as "preparing" as the executable code is installed. The security controller decrypts the executable code it has received using its private key. The decrypted code is stored into the claimed pages which are at this stage owned by the security controller. The pages storing the decrypted executable code are then marked as "executing" which indicates they are closed and ready to execute. The security controller then transfers ownership of the pages that it has claimed to the guest execution environment which is being initialized. A default, empty CPU execution context structure within the blind domain concerned is also initiated at this time. In this example embodiment, the security controller has preformed a secure initialisation by applying its private key to decrypt the executable code. In other example embodiments, the secure initialisation may additionally or alternatively include validation of the executable code and/or secure install attestation by the security controller.

At this stage, the security controller notifies the hypervisor that the guest execution environment is now ready to "execute". The state indicating that this is a "first" execution may be separately stored with a CPU context table entry for the process concerned.

The hypervisor performs the role of scheduling processes for execution. When the time has arrived for the newly initialized guest execution environment to be executed for the first time, then the hypervisor starts this execution. The guest execution environment then executes the decrypted executable code which was stored into the physical pages that have been transferred in ownership of the guest execution environment by the security controller. The code executing in the guest execution environment destructively claims any further pages it needs for its operation from among those pages marked as available to it by the hypervisor.

It will be appreciated that the guest execution environment may take a variety of different forms. In some embodiments, the guest execution environment may be a full operating system supporting multiple guest application programs. In other example embodiments the guest execution environment may be a single bare application executing using its own memory pages and without a separate operating system or other associated systems. The present techniques may be used in these and other circumstances. The guest execution environment operating under control of the hypervisor provides the ability for separate processes to execute in isolation from each other. Furthermore, the provision of the security controller and the mechanisms of the page ownership tables and the destructive claiming of the ownership of pages seeks to provide a system in which the data of a guest execution environment (of whatever form) may be protected from access by other guest execution environments and the hypervisor itself.

In this example embodiment the security controller takes the form of a separate processor. In other example embodiments the security controller could take the form of a trusted process running on the same processor (e.g. a trusted process running in secure mode on a processor supporting ARM Limited's TrustZone) or a trusted hypervisor depending upon the particular degree of security required/desired.

<FIG> is a flow diagram schematically illustrating a process of destructive page claiming. At step <NUM>, processing waits until a request to take ownership of the page is received. When such a request is received, step <NUM> determines whether the normal memory management unit provides write permission for the page concerned to the requesting process. This memory management unit may be controlled by the hypervisor. If the memory management unit does not give write permission, then the request is rejected and processing returns to step <NUM>. If the memory management unit does give write permission, then processing proceeds to step <NUM>, where an overwrite counter is initiated. Step <NUM> waits until a line of the page for which ownership is requested is detected as having been overwritten. Step <NUM> determines whether this was the next expected line to be overwritten. It is assumed in this example embodiment that it is expected that the lines forming the page of memory are written in sequence. If the expected line was not overwritten, then the request to claim ownership again fails and processing returns to step <NUM>. If the determination at step <NUM> is that the expected next line was overwritten, then processing proceeds to step <NUM> where the overwrite counter is incremented. Step <NUM> determines whether or not the full page has yet been overwritten as indicated by the overwrite counter reaching a predetermined value. If the overwrite counter has not yet reached the value indicating that the full page has been overwritten, then processing returns to step <NUM> where the system waits for the next line of the page to be overwritten. If the full page has been overwritten, then step <NUM> serves to mark the page as now owned by the requester in the page ownership table.

<FIG> schematically illustrates a hardware environment <NUM> for providing the systems described herein. In this example in the hardware environment <NUM> there are provided a plurality of processors <NUM>, <NUM>, a security controller <NUM>, a physical main memory <NUM> and bus mastering device, such as a memory mapped input output device <NUM> all connected via an interconnect <NUM>. It will be appreciated that the hardware environment <NUM> could take a wide variety of different forms. The present techniques are well suited for use, for example, in the context of cloud computing in which a tenant (cloud customer) has a processing task they wish to be performed. Rather than having their own processing hardware to perform the required task, they send the required task to be executed within a guest execution environment provided by a cloud services provider. The cloud services provider may receive the request for the guest execution environment with a hypervisor program and then initiate execution of that guest execution environment as previously discussed. The execution of the guest execution environment may itself be distributed across multiple processes, or even multiple sites, depending upon the type of cloud execution support being provided. The mechanisms described herein seek to provide an increased level of security between guest execution environments whereby guest execution environments may be protected from one another and may also be protected against the hypervisor itself.

The hardware execution environment <NUM> of <FIG> supports page ownership tables as described herein. The processors <NUM>, <NUM> and the security controller <NUM> are each provided with ownership and overwrite tracking hardware (OTH) which serves to manage the process of obtaining ownership of a page of the physical memory address space and the overwriting of that page as part of the claiming process as described elsewhere herein. Also provided within at least the processor <NUM> and <NUM> which support context switching is context switching circuitry (CS) which serves to save context data to a context data memory <NUM> within the main memory <NUM> as part of a context switching process. The context switching circuitry is a form of exception handling circuitry. The regions forming the context data memory <NUM> in respect of each context will be owned by the associated process concerned, which can thereby control the access to that context data to ensure that it is kept private if this is desired.

<FIG> schematically illustrates a software layer model using the current techniques. This software layer model includes multiple levels of privilege extending from a security controller at a highest level down to a hypervisor and a guest execution environment, which may itself include a guest operating system and guest applications. A new guest execution environment is initialized at a privilege level lower than that of the hypervisor.

In one example embodiment, the privilege levels could extend from a lowest level corresponding to the guest application programs. The next higher level would be the guest operating systems followed by the hypervisor and then the monitor program or firmware executed by the security controller. A highest level of privilege can be associated with the security complex which manages the access to, distribution of and validation of the cryptographic keys used in the system. It will be appreciated that other privilege level models may be adopted.

A feature of the present techniques is that the page ownership mechanisms permit the system to operate such that a guest execution environment has control of access to pages which it owns whereas, for example, a hypervisor which has a higher level of privilege may be prevented by the guest execution environment from having access to those pages. This is contrary to normal expectations in which higher levels of privilege give more access rights and control over access rights. The ownership and overwrite tracking circuitry illustrated in <FIG> may serve to enforce ownership rights of memory regions within the physical memory address space in accordance with an access configuration controlled by the owning process for that page. The owning process (as indicated in the page ownership table) may mark the page ownership as private to the owning process, or shared between the owning process and one or more further sources of memory access requests. A page would normally be initialized into the private state following its destructive claiming. The sharing of access by the owning process may take a variety of different forms, as illustrated in <FIG>. An owning process for a page may transfer ownership of that page to a "child" process which is initialized by the owning process (the "parent" process). When such a parent process has initialized a child process and the child process is still in the "prepare" state, then it can transfer ownership of one or more of the pages which the parent owns to that child process. The child process will initially receive those pages marked as private to that child process. The child process may then, if it so wishes, change the shared access control status for any of the pages it owns to indicate a shared status in which it is shared with its parent process. The child process destructively claims new pages allocated to it when it receives them from its parent process. Sharing can also be with an ancestor process, such as a grandparent process or any older process in an ancestor hierarchy.

When a process accesses a page it may, in some example embodiments, check that that shared access control data for that page is the same as the process is expecting. As an example, if a process owns a page and has set it up as having shared access control a "private", then it may check that the page is still configured in this way within the page ownership tables before it stores any sensitive data to that page.

Another form of sharing which may be selected by an owning process is to share a page with a memory mapped device in which the memory map device concerned is mapped into a page of memory which is owned by the process changing the access control. Accordingly, memory mapped devices sitting within memory address space owned by a process may be given the right to access that some page or another page of memory owned by that same process.

A further form of shared access which may be specified by an owning process is a globally shared status whereby a page of the physical address memory, is permitted to be accessed by any other process and is no longer owned by any individual process (in some example embodiments a unique BDID may be provided to be associated with all global pages). The owning process may ensure that sensitive data of that owning process is not written into that globally shared page.

<FIG> schematically illustrates how the ownership and overwrite tracking hardware serving as ownership circuitry serves to handle request for change of sharing permissions received from a process. At step <NUM> processing waits until a request to change sharing permissions is received. When such a request is received, then step <NUM> determines whether or not the request to change an access permission has been received from the process indicated in the page ownership table as owning the page concerned. If the request has been received from the owning process, then step <NUM> actions that requested change in access permissions (e.g. adopts one of the access control status options indicated in <FIG>) and then processing returns to step <NUM>. If the determination at step <NUM> is that the request is from a process which does not own the page concerned, then step <NUM> serves to ignore the requested change and optionally raise a warning that an incorrect and/or inappropriate request for change has been received before processing again returns to step <NUM>.

As mentioned in connection with <FIG>, the hypervisor may serve to schedule the execution of different execution environments. These different execution environments respectively own their own pages of the physical memory address space. When the hypervisor stops the processing of one guest execution environment and starts the processing of a different guest execution environment, then this is a switch of execution context and a switch of which process will be active. This context switching may be performed by protected exception handling. The state data of the processor, or wider system, at the time the change of context occurs may include many state parameters, e.g. register contents, configuration variables, program status values, etc. This state data is context data and may represent private information that it is desired not to allow to be available to other guest execution environments, or the hypervisor itself. <FIG> are flow diagrams illustrating how execution context may be protected.

At step <NUM> processing waits until a context switching interrupt is received such as involuntary exit to a different process. State <NUM> saves restart data to a portion of a context data memory <NUM> owned by the process (guest execution environment) that is subject to the interruption. This restart data may, in some example embodiments, be state data sufficient to restart the interrupted process, but need not include all state data which is dependent upon the interrupted process. As an example, the restart data may include general purpose register contents, but need not include microarchitectural state such as cache contents, translation look aside buffer contents, and the like. Following the saving of the restart data into portions of the context data memory <NUM> owned by the process being interrupted at step <NUM>, step <NUM> serves to destructively overwrite state data which is dependent upon the current process and that would be accessible to any other process following the switch to another process. The overwritten data may be superset of the restart data. The overwritten data may also exclude microarchitectural data, and other data which is not accessible to the newly started process, e.g. data within memory regions owned by the process which is being interrupted, but that will be inaccessible to a newly started process by virtue of the action of the page ownership tables and other mechanisms. The overwriting may, for example, set all of the accessible state dependent upon the current process to zero values or some other predetermined value which is not dependent upon the processing which was actually performed by the process which is being interrupted. The system then returns to step <NUM> to await the next context switching interrupt. In the case of a voluntary exit from a process, e.g. a process call to a higher exception level, a subset of register contents, e.g. R0-R7, may be passed to the call target with other registers/state being stored and restored on exit and re-entry.

As shown in <FIG>, the system waits at step <NUM> until there is a new process to be started. Step <NUM> serves to determine whether or not the new process to be started is one for which the associated status is "ready"in the CPU context data. If the process is not in the ready state , then this indicates that it has already been scheduled for execution and executed at least once and accordingly will have its own context data which should be restored before its execution is re-started. If the process to be started is not in the "ready state", then step <NUM> serves to restore its restart data from the pages of memory which it owns within the context data memory <NUM>. If the process to be started is in the "ready" state, e.g. is in the "ready for first execution" state, then step <NUM> is bypassed. Finally, at step <NUM> the execution of the new process is commenced before process is returned to step <NUM> to await another new process.

<FIG> indicates a process descriptor entry which may be one of a plurality of process descriptor entries within a process descriptor table. The process descriptor entry includes, for example, the blind domain identifier (BDID). The page descriptor entry also includes pointer (handle) to a location within the context data memory <NUM> to which context data for the process concerned is to be saved (and from which it is restored) when the process concerned is switched out. This pointer indicates a region of memory which is owned by the process concerned. The page descriptor entry also includes a current process status as will be discussed further below.

<FIG> schematically illustrates example process status states for a process. A process that has ceased to be used is marked as invalid and its BDID will be available to be reclaimed by a new process. The hypervisor may be responsible for creating a process and setting up the process descriptor entry. The initialization of that process may be performed in conjunction with the security controller as previously described. The next state in sequence which may be adopted by the process is a "scrub" state. This indicates that the process BDID concerned has been claimed and associated pages for ownership by the process are undergoing scrubbing, e.g. existing entries in page ownership tables for earlier uses of the BDID concerned are removed and then new pages for the BDID are claimed and scrubbed (subject to destructive overwriting). When scrubbing has completed, then the process concerned is switched to a "prepare" state this indicates that the process concerned is open and ready to have its pages populated. When the population of the pages has completed the process is changed to an "executing" state which is closed and ready to execute. There is a ready for first execution state that is stored in a status field of a CPU execution context within the domain and used to control whether or not restart data is restored when execution of the process is started. <FIG> illustrates the "lifecycle" of a process including a plurality of process states through which the process is moved in sequence following its preparation for execution. The number and particular form of these states may vary.

At least some example embodiments include a blind domain execution context (or frame) BDEC that may be used to store state data of a process when switching that process into and out of execution. Included within this state data is an indication of whether or not the process concern has already undergone some execution. If the process has not been executed already, then it is marked in this example as "new" (see "ready" state previously discussed). The execution context data may also include state data such as the general purpose register contents at the time the process was exited. These register contents may be restored when the process is re-entered. There are status parameters that further specify whether a process was exited voluntarily (e.g. following a software function call) or involuntarily (e.g. following a hardware interrupt); this information may be used to control how the process is re-started as well as the actions preformed as the process is exited. The context data may be stored so as to be private to the process concerned.

Each BDEC may contain an indication of state such as: New, Voluntary_Exit, Involuntary_Exit, Voluntary_Complete, Involuntary_Complete and Invalid. The BDEC may also include an indication of the exception level that owns the domain, the contents of the general purpose registers for the domain (e.g. R0 - R30, PC, P-State, etc) and the content of the exception level registers for the domain (e.g. TTBR_ELx, etc).

In general an ownership table may be provided comprising one or more entries each indicating, for a corresponding block of physical addresses, which of a plurality of processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. This can be useful to allow any one of a plurality of processes to take exclusive control over a given region of the physical address space in order to restrict access to that region by other processes. This is particularly useful as it can allow a process at a lower privilege level to control or restrict access to data by a more privileged process, which is not possible in typical systems.

In general, there may be some means for a requesting process to request ownership of a target block of physical addresses. The target block of physical addresses could be identified directly in the request, or indirectly by specifying a virtual address or intermediate address or in some other manner. The ownership request could be a dedicated ownership request instruction (such as the claim start instruction discussed above), or another kind of instruction with a parameter indicating that ownership is requested for a given page, or the request could correspond to another kind of ownership request command (not necessarily an instruction), e.g. by setting some control information which triggers some other process to initiate the ownership request, for example. In response to the ownership request, processing circuitry can update the ownership table to indicate that the requesting process is now the owner for the target page. Hence, a requesting process can protect sensitive data by requesting ownership of the corresponding blocks of addresses before writing the sensitive data to memory, for example.

When ownership of a given block of addresses changes from one process to another, a number of techniques could be used to prevent leakage of sensitive information from the old owner to the new owner. As discussed in the examples above, one way is to require successful completion of an overwriting procedure to overwrite each address in the target block before the process requesting ownership can validly become the owner process for that block. This could be enforced either by hardware which actually performs the overwriting procedure, or with the requesting process itself or another trusted process carrying out the overwriting procedure but hardware checking whether it has successfully been completed. One way for hardware to check whether the overwriting procedure has successfully completed may be to check that the physical addresses overwritten in one or more write operations performed between an ownership claim start command and an ownership claim end command include every physical address of the target block. If the writes performed between the ownership claim start and end commands do not contiguously cover the entire block of addresses, then the overwriting procedure may fail and the requester cannot validly become the owner. For example, these checks could be performed using a claim count value tracking the number of completed writes and their address offsets as discussed above. It will be appreciated that there may be other techniques for determining that the overwriting procedure has successfully overwritten the data at each physical address of the target block.

Some embodiments may provide encryption circuitry to encrypt data written to memory and decrypt data read from memory. Each process may have one or more associated keys and data written to a particular block of addresses may be encrypted using a key associated with the owner of that block, and decrypted on reading the data back from the memory. In systems comprising encryption, the overwriting procedure may not be necessary since even if the data associated with one process remains in memory following transfer of a block of addresses to another owner, the new owner would not be able to read the data since it is encrypted using the key of the old owner.

Nevertheless, for increased security, even if there is encryption capability, it may be preferred to also require that the overwriting procedure is performed for a block of addresses when ownership of that block is transferred. Combining both encryption and the overwriting procedure also has the benefit that the owner process can vary the level of encryption required for each of the blocks of addresses it owns without risking data being lost when ownership of a block is transferred. The different encryption modes may comprise different levels or strengths of encryption, for example.

In general, ownership protection circuitry may be provided to reject access requests from a current process to access data at a target physical address when a corresponding entry of the ownership table indicates that the current process is not permitted by the owner process to access that address. For example, the ownership protection circuitry may comprise the BDMU described above, or alternatively could be some circuitry provided within a memory controller. By rejecting requests which do not satisfy the owner's permissions, the owner process can have exclusive control over access to the owned block of addresses.

In addition to ownership protection circuitry, there may also be access control circuitry which enforces access permissions set by particular processes, such as a hypervisor, virtual machine or operating system. For example the access control circuitry could correspond to an MMU as discussed above. Whereas the access control circuitry enforces permissions set by particular processes at particular privilege levels (e.g. to allow the hypervisor to partition the address space between different virtual machines for example), the ownership protection circuitry can allow any process to enforce permissions on other processes regardless of their privilege level, by requesting ownership of the pages for which those permissions is required.

The technique can be particularly useful for systems supporting two or more of a hypervisor, one or more virtual machines, one or more guest operating systems and one or more applications. However, more generally the technique could be applied to any system in which multiple processes co-exist and one process may prevent another process accessing data.

As discussed above, the POT <NUM> may include the address field <NUM> which effectively represents a "reverse translation mapping" from the PA associated with the POT entry <NUM> to a VA or IPA from which the PA was translated at some reference point in time.

However, a similar technique could also be applied more generally to any table indexed by physical address, for which at least one entry may identify a first address from which the corresponding physical address was translated by address translation circuitry. By retaining a snapshot of a reverse mapping from a physical address to a first address from which the physical address was translated, it is possible to later check whether the mapping is still the same, which can be useful for detecting subsequent changes in the address mapping which might affect the validity of the contents of the table.

In general, processing circuitry may be responsive to the occurrence of a reference event to record, in the entry of the table corresponding to a given physical address, the first address currently translated into the given physical address by the address translation circuitry. The reference event could for example be the allocation of a new entry into the table for the given physical address, the updating of information in an existing entry of the table for the given physical address, the execution of a predetermined type of instruction (e.g. an instruction specifying the given first address) or a predetermined change of operating mode of the data processing apparatus (e.g. a change to a secure mode). Hence, the first address recorded in the table may represent the mapping between the first address and the corresponding physical address which existed at the time of the reference event.

Later, when an access request is received which specifies a target first address to be translated into a target physical address by the address translation circuitry, control circuitry can determine whether there is a mismatch between the target first address and the first address specified by the entry of the table corresponding to the target physical address. For example, this effectively determines whether the address mapping is still the same as the time of the reference event which led to the first address being stored to the table. If there is a mismatch between these addresses, the request can be rejected or an error can be signalled.

In some cases, the physically indexed table may be provided solely for the purpose of tracking past address mappings and detecting whether they are still the same at a later time, so it is not necessary for the physically indexed table to contain any information besides the first address itself.

While this technique can be used for any physically indexed table, it is particularly useful for the ownership table of the form discussed above which indicates owners for corresponding blocks of physical addresses and where the owner has exclusive control of access to those addresses. Recording a reverse physical-to-first address mapping in the table can help to prevent attacks of the type discussed above where a change of address mapping could lead to loss of sensitive information.

In some cases, the first address may be a virtual address. In other cases the first address may be an intermediate physical address. Also, it is possible for one table to have some entries where the first address is a virtual address and other entries where the first address is an intermediate address.

Claim 1:
Apparatus for processing data comprising:
ownership circuitry (<NUM>) to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified in an ownership table from among a plurality of processes and independently of privilege level, said given owning process having rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of:
private to said given owning process; and
shared between said given owning process and at least one further source of memory access requests;
wherein said ownership circuitry permits said given owning process to set one or more attributes in the ownership table to deny access to said given memory region to a process having a greater level of privilege than said given owning process; and
wherein in response to receiving a target physical address associated with a read or write transaction requesting a read or write to a target memory region associated with the target physical address, the ownership circuitry is configured to:
access an entry of the ownership table corresponding to the target physical address;
perform access permission checking based on the entry of the ownership table corresponding to the target physical address; and
when the access permission checking fails, reject the read or write transaction.