Patent Description:
Numerous scientific papers have reported good switching performances of silicon carbide (SiC) MOSFET devices. From an industrial point of view, in addition to switching performances, SiC devices also have good structural robustness which is a desirable characteristic for power systems.

During the steps of manufacturing and handling the SiC wafers, the interaction between machinery and SiC wafers may cause the release of debris, due to the high hardness of SiC. Therefore, such debris may permanently deposit on the surface of the same wafers and form local defectiveness, which may impact on the functionality of the final MOSFET device.

In this regard, <FIG> illustrates, in lateral sectional view, a transistor <NUM>, in particular a vertical-channel MOSFET transistor, comprising: a substrate <NUM> of SiC; a gate region <NUM>, for example of polysilicon, arranged at a first surface of the substrate <NUM>; a body region <NUM>, extending into the substrate <NUM> at the first surface; a source region <NUM>, extending into the body region <NUM> at the first surface of the substrate <NUM>; and a drain region <NUM>, extending at a second surface of the substrate <NUM>, opposite to the first surface.

The transistor <NUM> has debris <NUM> interposed between the gate region <NUM> and the source region <NUM>. Furthermore, a gate oxide layer <NUM> extends, above the source region <NUM>, between the substrate <NUM> and the gate region <NUM>; in particular, the debris <NUM> extends through the gate oxide layer <NUM> throughout the entire thickness of the latter, electrically connecting the source region <NUM> and the gate region <NUM> to each other. Therefore, the debris <NUM> is a punctual defect which short-circuits the gate region <NUM> with the source region <NUM>.

<FIG> is a circuit representation of the transistor <NUM> of <FIG>.

In use, when the gate region <NUM> is biased with a biasing voltage VGS, the debris <NUM> forms a conductive electrical path which causes the flow of a current iSC between the gate region <NUM> and the source region <NUM> (hereinafter also referred to as "short-circuit current" between the gate region <NUM> and the source region <NUM>). In the presence of this current iSC, the transistor <NUM> fails.

A similar problem may occur in case of imperfections resulting from the gate oxide formation process, resulting in the formation of leakage paths by direct connection or tunnel effect between the gate region <NUM> and the source region <NUM>.

Similarly, defectiveness of the type described above may also, or alternatively, form between the gate region <NUM> and the drain region <NUM>.

Commercially available MOSFET devices are typically formed by a plurality of transistors <NUM> of the type shown in <FIG>, which are connected in parallel to each other and cooperate with each other in order to suitably manage the currents required by the specific application wherein they are used. In case of failure of even just one transistor <NUM>, belonging to the MOSFET device, the entire MOSFET device must be rejected; this causes an increase in manufacturing costs.

Fuse or anti-fuse elements for protecting semiconductor devices are known in the prior art, for example from document <CIT> or from document <CIT>.

The need is therefore felt to provide a solution to the problems set forth above.

According to the present invention, an electronic device provided with a protection element and a method for manufacturing the electronic device are provided, as defined in the attached claims.

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

<FIG> illustrates an equivalent circuit of a transistor <NUM>, in particular a vertical-channel MOSFET, even more in particular a power MOSFET, according to an aspect of the present invention. The transistor <NUM> comprises, in a per se known manner and as briefly described with reference to <FIG>: a gate region, or gate, <NUM> (forming a control terminal G) coupeable, in use, to a generator <NUM> of a biasing voltage VGS; a source region or source <NUM> (forming a first conduction terminal S); and a drain region or drain <NUM> (forming a second conduction terminal D).

In particular, according to the present invention, a protection element <NUM> is interposed between the gate region <NUM> and the generator <NUM>. More in particular, the protection element <NUM> is a fuse configured to interrupt the electrical connection between the generator <NUM> and the gate region <NUM> in the presence of the short-circuit current iSC (illustrated in <FIG> and described with reference to this Figure), caused by the presence of the defectiveness, or punctual defect, <NUM> (the latter exemplarily represented in <FIG>, as previously described).

A MOSFET device according to the present invention is formed by a plurality (two or more) of transistors <NUM> of the type shown in <FIG>, connected to each other in parallel. In case of failure of a transistor <NUM> that generates a flow of short-circuit current through one or more fuses <NUM> higher than what is expected during the normal operativeness of the device, the respective fuse <NUM> melts/blows, causing the interruption of the flow of short-circuit current iSC between the generator <NUM> and the source region <NUM> through the gate region <NUM> and the punctual defect <NUM>.

<FIG> shows, in a triaxial Cartesian reference system X, Y, Z, a portion of a MOSFET device <NUM> according to an embodiment of the present invention; in particular, the MOSFET device <NUM> is shown in an XY-plane top view and only the elements essential to the understanding of the present embodiment are shown.

The MOSFET device <NUM> comprises an active-area region <NUM>, a protection region <NUM>, and a connection region <NUM>. The protection region <NUM> is interposed between the active-area region <NUM> and the connection region <NUM>.

In detail, the active-area region <NUM> includes a plurality of gate regions <NUM> and a plurality of source regions <NUM>, of the strip type, each extending along a respective main direction, parallel to the Y axis, in a per se known manner.

The connection region <NUM> is a conductive path (e.g., having a ring-like shape) that connects all the gate regions <NUM> to a common gate terminal.

Each gate region <NUM>, in particular of polysilicon or metal, has a width dG, measured along the X axis, for example comprised between <NUM> and <NUM>.

The protection region <NUM> includes a plurality of protection elements <NUM> (also referred to as "fuses"), each of which being in electrical connection with a respective gate region <NUM>. In particular, in the embodiment of <FIG>, each fuse <NUM> is in structural and electrical continuity with the respective gate region <NUM>. In other words, the fuse <NUM> and the respective gate region <NUM> form a monolithic structure. According to an aspect of the present invention, both the gate region <NUM> and the fuse <NUM> are of conductive polysilicon or of metal material. In a further embodiment, each fuse <NUM> is of a different material with respect to the material of the gate region <NUM> whereto it is coupled (e.g., the gate region <NUM> is of polysilicon and the fuse <NUM> is of metal).

Each fuse <NUM> has, in one embodiment, a substantially parallelepipedal shape with width dP, measured along the X axis, smaller than the respective width dG of the gate region <NUM> whereto it is coupled. The width dP is, for example, comprised between <NUM> and <NUM>.

Alternatively to what has been said, in a further embodiment, each fuse <NUM> has dimensions (in particular width dP) equal to the dimensions (in particular width dG) of the gate region <NUM> whereto it is coupled. In this case, the short-circuits protection (i.e., the ability of the fuse <NUM> to melt/blow before the gate region <NUM>) is obtained by suitably selecting the material of the fuse <NUM> (material having a melting point for lower temperatures with respect to the material of the gate region <NUM>).

The connection region <NUM> comprises a conductive portion <NUM> which extends coplanar with the fuse <NUM> and in continuity with the fuse <NUM>. In particular, the conductive portion <NUM> is of polysilicon or metal, and is electrically coupled to each fuse <NUM> and, through the latter, to each gate region <NUM>; above the conductive portion <NUM>, and in electrical contact with the conductive portion <NUM>, a metal layer <NUM> extends which forms a pad configured to be electrically coupled to the generator <NUM>, in a per se known manner.

The conductive portion <NUM> may have any shape, for example it extends to form a ring that follows the shape and the extension of the region <NUM> of <FIG>. Alternatively, a plurality of conductive portions <NUM> may be present which extend in the form of a strip, each of which being electrically in contact with the metallization <NUM>.

In one embodiment, each fuse <NUM> is in structural and electrical continuity with the respective conductive portion <NUM> in the connection region <NUM>. In other words, the conductive portion <NUM>, the respective fuse <NUM> coupled thereto and the respective gate region <NUM> coupled to this fuse <NUM> form a monolithic structure. In a different embodiment, each fuse <NUM> is of a material different from the material of the gate region <NUM> and the conductive region <NUM> whereto it is coupled (e.g., the gate region <NUM> and the conductive region <NUM> are of polysilicon, and the fuse <NUM> is of metal).

<FIG> shows a cross-sectional view of the MOSFET device <NUM> of <FIG>; in particular, <FIG> is taken along scribe line IV-IV of <FIG>.

In detail, the transistor <NUM> comprises a substrate <NUM>, in particular of SiC, having a first and a second face 48a, 48b opposite to each other. In particular, in the present embodiment, the term "substrate" means a structural element which may comprise (but does not necessarily comprise) one or more epitaxial layers grown on a starting substrate.

An insulating layer <NUM> (in particular, a gate oxide), for example of deposited Silicon Oxide (SiO2), with thickness, measured along the Z axis, comprised between <NUM> and <NUM>, extends on the first face 48a.

The gate region (strip) <NUM> extends at the active-area region <NUM>, on the insulating layer <NUM>.

A field plate oxide layer <NUM>, in particular of TEOS, extends at the protection region <NUM> and at the connection region <NUM>, on the insulating layer <NUM>. The field plate oxide layer <NUM> has a thickness, measured along the Z axis, at the protection region <NUM>, comprised between <NUM> and <NUM>. The field-plate-oxide layer <NUM> has a thickness, measured along the Z axis, at the connection region <NUM>, comprised between <NUM> and <NUM>.

The fuse <NUM>, of thickness h, measured along the Z axis, comprised between <NUM> and <NUM> extends at the protection region <NUM>, on the field-plate-oxide layer <NUM>. In one embodiment, the fuse <NUM> has a XZ-plane section (i.e., base area of the fuse <NUM>) comprised between <NUM> and <NUM><NUM>.

According to an embodiment, as said, the fuse <NUM> is in electrical and structural continuity with the gate region <NUM>. Furthermore, the fuse <NUM> is at least in part in electrical and structural continuity with the conductive region <NUM>.

A further insulating layer <NUM> extends on the gate region <NUM> and on the fuse <NUM>, at the active region <NUM> and at the protection region <NUM>, respectively. The insulating layer <NUM> also extends at the connection region <NUM>, above the conductive strip which extends in continuity with the fuse <NUM>. The further insulating layer <NUM> is, in particular, of TEOS and has a thickness, measured along the Z axis, comprised between <NUM> and <NUM>.

A metallization layer <NUM>, for example of Al/Si/Cu and of thickness, measured along the Z axis, comprised between <NUM> and <NUM>, extends at the active region <NUM>, on the further insulating layer <NUM>. The metallization layer <NUM> forms the first conduction terminal S (source) of the transistor <NUM> of <FIG>.

A passivation layer <NUM>, for example of SiN, extends at the active region <NUM>, the protection region <NUM> and the connection region <NUM>, in particular respectively on the metallization layer <NUM>, and on the further insulating layer <NUM>.

A metal layer <NUM> extends, at the connection region <NUM>, through the insulating layer <NUM> and the passivation layer <NUM>, up to electrically contacting the conductive portion <NUM>. The metal layer <NUM> (and at least in part also the underlying conductive portion <NUM>) forms the aforementioned gate ring and is therefore in electrical contact with the gate regions <NUM> through the respective fuses <NUM>.

An interface layer <NUM>, in particular of nickel silicide, extends on the second face 48b. A metallization layer <NUM>, for example of Ti/Ni/Au, extends on the interface layer <NUM>. The metallization layer <NUM> forms the second conduction terminal D (drain) of the transistor <NUM> of <FIG>.

According to the present invention, at the protection region <NUM>, i.e. at the fuse <NUM>, a buried cavity <NUM> is present which extends completely through the insulating layer <NUM> (above the fuse <NUM> along Z) and in part through the field-plate-oxide layer <NUM> (below the fuse <NUM> along Z). The fuse <NUM> is supported, in the cavity <NUM>, by a portion 54a of the field-plate-oxide layer <NUM> which protrudes within the cavity <NUM>. The cavity <NUM> is closed at the top by a polymeric layer <NUM>, in particular insulating (e.g., of Polyimide, PI, or Polyimide-Iso-IndroQuinazalinedione, PIQ). The insulating polymeric layer <NUM> extends above the passivation layer <NUM> and, at the protection region <NUM>, extends into an opening made through the passivation layer <NUM> and the insulating layer <NUM>, up to reaching the cavity <NUM> and the fuse <NUM>. As better illustrated hereinbelow, the formation of the insulating polymeric layer <NUM> is such that the cavity <NUM> is not completely filled by the insulating polymeric layer <NUM>, but is closed at the top by the insulating polymeric layer <NUM>.

Under normal operating conditions, i.e. in the absence of defectiveness of the type shown 1A, there are no leakage currents between the gate region <NUM> and the source region <NUM> or, in any case, possible leakage currents are of the order of <NUM> nA (for gate biasing voltages VGS of the order of ± <NUM> V), and therefore negligible. Conversely, in the presence of the aforementioned defectiveness, a current (i.e., the short-circuit current iSC) of the order of mA or slightly less (e.g., greater than <NUM> mA) is observed.

The Applicant has verified that when, during use, the short-circuit current iSC, in particular equal to about <NUM> mA, flows through the fuse <NUM> for a time t equal to about <NUM>, a temperature variation ΔT of the order of <NUM><NUM> K, develops according to the formula: <MAT> where ρ is the electrical resistivity of the fuse <NUM> (in the case of polysilicon equal to <NUM>e-<NUM> Ω·cm), c is the specific heat (in the case of polysilicon equal to <NUM> J/kg·keV), D is the density of the material of the fuse <NUM> (in the case of polysilicon equal to <NUM>/m<NUM>), h is the thickness along the Z axis of the fuse <NUM> and dP is the width along the X axis of the fuse <NUM>.

The Applicant has also verified that such a temperature variation ΔT in the time interval considered causes the fuse <NUM> to melt/blow, resulting in the insulation of the transistor <NUM> from the generator <NUM> (<FIG>).

The fuse <NUM> is designed in such a way as to interrupt the electrical connection between the connection region <NUM> (connected in use to the generator <NUM>) and the gate region <NUM> in the presence of the short-circuit current iSC between the gate region <NUM> and the source region <NUM>, whose value depends on the biasing voltage VGS and which is, in any case, greater than the leakage current observable under normal operating conditions. In particular, the fuse <NUM> is designed in such a way as to change physical state (e.g., from solid to melted or from solid to gaseous) in the presence of the short-circuit current iSC.

In general, therefore, the fuse <NUM> is designed so as to interrupt the electrical connection between the connection region <NUM> and the gate region <NUM> (e.g., by changing physical state) in the presence of a current greater than a critical threshold equal to at least one order of magnitude higher with respect to the leakage current under normal operating conditions (e.g., critical threshold equal to or greater than <NUM> nA).

The presence of the buried cavity <NUM> around the fuse <NUM> or, in other words, the formation of the fuse <NUM> at least in part within the buried cavity <NUM>, allows the material in melted state or gaseous state of the fuse <NUM> to flow and be gathered within the buried cavity <NUM>. In this manner, possible problems linked to a breakdown of the device <NUM> caused by the local increase in pressure following the change of state of the material of the fuse <NUM> are overcome.

<FIG> shows a cross-sectional view, taken along scribe line IV-IV, of an embodiment of the MOSFET device <NUM> of <FIG> alternative to the embodiment of <FIG>. Elements corresponding to those shown in <FIG> are indicated in <FIG> with the same reference numbers and will not be further described.

In the embodiment of <FIG>, each fuse <NUM> is in electrical continuity with the respective gate region <NUM> and with the conductive portion <NUM> extending into the connection region <NUM>; however, in this case the gate region <NUM> and the conductive portion <NUM> do not form a monolithic body with the fuse <NUM>. The fuse <NUM> is here formed by a material different from the material of the gate region <NUM> and the conductive portion <NUM> (e.g., the latter are of polysilicon and the fuse <NUM> is of metal).

<FIG> show manufacturing steps of the MOSFET device <NUM> of <FIG>, according to an embodiment of the present invention.

With reference to <FIG>, the substrate <NUM>, for example of Silicon Carbide, SiC, is provided.

Then, on the front side 48a, the oxide layer <NUM>, for example SiO<NUM>, is formed by CVD deposition and/or thermal oxidation. Subsequently, the field-plate-oxide layer <NUM> is formed on the oxide layer <NUM>; more in particular, the field-plate-oxide layer <NUM> is formed at the protection region <NUM> intended to accommodate the fuse <NUM> and at the connection region <NUM> intended to accommodate the gate ring. To this end, it is performed a step of depositing TEOS and subsequently patterning the same to remove the field-plate-oxide layer <NUM> from the active-area region <NUM>. In this manner, at the active-area region <NUM>, the field-plate-oxide layer <NUM> is removed up to reaching the underlying oxide layer <NUM>.

Then, a conductive layer, e.g. of polysilicon, is formed over the oxide layer <NUM> in the active-area region <NUM>, and over the field-plate-oxide layer <NUM> in the protection <NUM> and connection regions <NUM>; this conductive layer is then patterned (e.g., by lithography and etching steps) to form the conductive strips relating to the gate regions <NUM>, the fuses <NUM> and the conductive portions <NUM>, in the respective regions <NUM>, <NUM> and <NUM>.

Then, the insulating layer <NUM> is formed by depositing TEOS on the gate regions <NUM>, fuses <NUM> and conductive portions <NUM>.

With reference to <FIG>, the insulating layer <NUM> is opened at the connection region <NUM> up to reaching the conductive portions <NUM>; conductive material, in particular metal, is then deposited to form the metallizations <NUM> and <NUM>. The metallizations <NUM> and <NUM> do not extend at the protection region <NUM>.

Then, <FIG>, the method proceeds with the formation of the passivation layer <NUM>, depositing SiN. The passivation layer extends on the metallizations <NUM> and <NUM> and on the insulating layer <NUM> where the latter is exposed (protection region <NUM>).

Then, <FIG>, a step of etching the passivation layer <NUM> is performed at the protection region <NUM> (i.e. between the metallizations <NUM> and <NUM>), up to reaching the underlying insulating layer <NUM>. The etching of the passivation layer <NUM> is performed where it is desired to form the fuses <NUM> and, in particular, the buried cavities <NUM> accommodating the fuses <NUM>. Where the buried cavities <NUM> are not formed, the passivation layer <NUM> is not removed.

An opening <NUM> is thus formed wherethrough, <FIG>, the material of the insulating layer <NUM> and field-plate-oxide layer <NUM> may be removed, by isotropic etching, to form the buried cavity <NUM>. Since the material of the insulating layer <NUM> and field-plate-oxide layer <NUM> is the same, a single etching, using for example HF-(hydrofluoric acid) based chemistries, is sufficient to form the cavity <NUM>. Since, as illustrated in <FIG>, the gate regions <NUM> and the fuses <NUM> extend in the form of a strip, forming the opening <NUM> having a dimension (along the Y axis) greater than the corresponding width of the relative fuse <NUM>, the etching of the step of <FIG> extends to the portions of the field-plate-oxide layer <NUM> lateral with respect to the strip of fuse <NUM>, removing in part the material below the fuse <NUM>. By adjusting the etching by time, a portion of the field-plate-oxide layer <NUM> may be maintained below and vertically aligned to the fuse <NUM>, in physical support of the latter, (i.e. the portion 54a previously described).

A step of forming the insulating polymeric layer <NUM>, as said of Patterned Polyimide, PI, or Polyimide-Iso-IndroQuinazalinedione, PIQ, is then performed. The polymeric material PI or PIQ is deposited in a per se known manner.

The polymeric material PI or PIQ is known to be a material that may be deposited by spinning technique. When it is dispensed in the liquid phase on the rotating wafer, it forms a thin film which is then made denser, if necessary, with thermal treatments. Considering the planarizing and viscosity properties of the polymeric material PI or PIQ, it does not completely penetrate within the cavity that accommodates the fuse, but closes it at the top.

The device <NUM> of <FIG> is thus obtained.

Then, the oxide layer <NUM>, for example SiO<NUM>, is formed on the front side 48a as described with reference to <FIG>.

Subsequently, the field-plate-oxide layer <NUM> is formed on the oxide layer <NUM>; more particularly, the field-plate-oxide layer <NUM> is formed at the protection region <NUM> intended to accommodate the fuse <NUM> and at the connection region <NUM> intended to accommodate the gate ring. To this end, it is performed a step of depositing TEOS and subsequently patterning the same to remove the field-plate-oxide layer <NUM> from the active-area region <NUM>. In this manner, at the active-area region <NUM>, the field-plate-oxide layer <NUM> is removed up to reaching the underlying oxide layer <NUM>.

Then, a conductive layer, e.g. of polysilicon, is formed over the oxide layer <NUM> in the active-area region <NUM>, and over the field-plate-oxide layer <NUM> in the protection <NUM> and connection regions <NUM>; this conductive layer is then patterned (e.g., by lithography and etching steps) to form the conductive strips relating to the gate regions <NUM> and the conductive portions <NUM>, in the respective regions <NUM> and <NUM>. The polysilicon conductive layer is removed at the protection region <NUM>, i.e. it is removed where the formation of the fuses <NUM> is foreseen.

Then, the insulating layer <NUM> is formed by depositing TEOS on the gate regions <NUM> and conductive portions <NUM>, and over the field-plate-oxide layer <NUM> in the protection region <NUM> where the polysilicon layer is missing.

With reference to <FIG>, the insulating layer <NUM> is removed in the protection region <NUM>, between the gate regions <NUM> and the conductive portions <NUM>, exposing respective terminal portions of the gate regions <NUM> and of the conductive portions <NUM>. Then a step of depositing and patterning conductive material (such as for example Ti, or TiN, or Al, or Ni), more particularly metal, is performed. The deposition of this conductive material is performed in particular on the terminal portions of the gate regions <NUM> and of the conductive portions <NUM> exposed, and on the field-plate-oxide layer <NUM> comprised between the gate regions <NUM> and the conductive portions <NUM>. The fuses <NUM> are thus formed.

The method then proceeds with steps similar to those of <FIG>, and therefore not further described.

From an examination of the characteristics of the invention made according to the present invention, the advantages that it affords are evident.

In particular, the fuses are implemented without modifications to the passivating cover, while the melted/gaseous material of the fuse after breaking has sufficient space to drain without negatively affecting the structure of the device.

Furthermore, in MOSFET devices formed by a plurality of transistors, connected in parallel to each other and cooperating with each other in order to suitably manage the currents required by the specific application wherein they are used, in case of failure of even just one transistor, belonging to the MOSFET device, the functionality of the entire MOSFET device may be restored by disconnecting the single faulty transistor, maintaining good electrical insulation characteristics and having a fractional loss on the current flow of the device.

Furthermore, in case of degradation of the insulation between the gate terminal and the source terminal of one or more transistors of the MOSFET device due to a leakage current greater than <NUM> mA, in use, the fuse relating to such one or more degraded transistors would melt, automatically segregating the degraded transistor.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the attached claims.

For example, the present invention may be applied to devices with a substrate of a material other than SiC, for example Si, GaN (gallium nitride) or glass or other material.

Furthermore, the present invention finds applications in devices other than MOSFETs, for example GaN power devices, LDMOS ("Laterally Diffused MOS"), VMOS ("Vertical MOS"), DMOS ("Diffused MOS"), CMOS ("Complementary MOS"), or other integrated devices provided with a control terminal and at least one conduction terminal.

Furthermore, the device <NUM> may include one or more horizontal-channel MOSFET transistors.

Furthermore, the device <NUM> may be formed by a single transistor <NUM>. In this case, the melting/blowing of the fuse <NUM> interrupts the operation of the entire device <NUM>. This embodiment may be useful in the event that the device <NUM> is integrated in a complex electronic system and is not vital for the operation of the electronic system (for example, in the presence of redundancy), but wherein the failure of this device <NUM> could compromise the operation of other elements of the electronic system.

In addition, in the embodiment of <FIG>, the fuse <NUM> may be of a material different from metal or the material of the gate region <NUM> and/or the connection region <NUM>, for example of a conductive polymer, with electrical resistivity lower than Ω·cm.

Furthermore, the fuse <NUM> may have a geometrical shape different from the parallelepipedal shape, such as, for example, a cylindrical or generically polyhedral shape.

According to a further embodiment, the protection element <NUM> is configured to interrupt the electrical connection between the connection region <NUM> and the gate region <NUM> in the absence of a change of physical state, but by breaking (direct or mediated by the presence of a further element) of the protection element <NUM> in the presence of the short-circuit current iSC.

Furthermore, it is evident that the cavity <NUM> may have a different shape from what has been shown, depending on the type of etching used to form the cavity.

Claim 1:
An electronic device (<NUM>; <NUM>) comprising:
a solid body (<NUM>), in particular including Silicon Carbide;
a gate terminal (<NUM>), extending into the solid body (<NUM>);
a conductive path (<NUM>), extending at a first side of the solid body (<NUM>), configured to be electrically coupeable to a generator (<NUM>) of a biasing voltage (VGS) of said gate terminal (<NUM>);
a protection element (<NUM>) of a solid-state material, coupled to the gate terminal (<NUM>) and to the conductive path (<NUM>), the protection element (<NUM>) forming an electrical connection between the gate terminal (<NUM>) and the conductive path (<NUM>), and being configured to go from the solid state to a melted or gaseous state, interrupting said electrical connection, in response to a leakage current (iSC) through said protection element (<NUM>) greater than a critical threshold,
characterized in that it further comprises a buried cavity (<NUM>) in the solid body (<NUM>) accommodating, at least in part, said protection element (<NUM>).