Patent Description:
This invention relates generally to a vertical interconnection structure for interconnecting circuitry on an upper layer to a circuitry on a lower layer of a multi-layer substrate or a circuit board.

As known in the art, vertical interconnection is one of the key components for on chip, on package substrate and on PCB, especially in high frequency or millimeter-wave applications. Conventional vertical connections in a multi-layer substrate exhibit strong capacitive behavior resulting from dielectric loading due to the presence of the substrate and dielectrics. It is a great concern under limited design solutions in the real fabrication to reduce the mismatch caused by strong capacitance at high frequencies and also reduced insertion loss.

<CIT> discloses an interconnection structure for interconnecting circuitry on a first conductive layer to circuitry on a second conductive layer.

<CIT> discloses a finger metal oxide metal capacitor that includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit.

<CIT> discloses a capacitive element, including a first electrode formed on a substrate and a second electrode provided so as to sandwich a dielectric between the first electrode and the second electrode and so as to surround the first electrode on four sides along a surface of the substrate. <CIT> discloses signal wiring conductors which are provided at opposing positions on the upper surface of the uppermost dielectric layer and on the lower surface of the bottommost dielectric layer.

It is one object of the invention to provide an improved a vertical interconnection structure of a multi-layer substrate to solve the above-mentioned deficiencies or shortcomings. Vertical interconnection structures according to the invention are defined in the independent claims. The dependent claims define preferred embodiments thereof.

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. In the drawings:.

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

The present invention pertains to a circuit board topology that is capable of extending operating frequency and achieving better voltage standing wave ratio (VSWR) performance than traditional substrate design. Packaging of an integrated circuit (IC) chip can involve attaching the IC chip to a substrate (a packaging substrate) which, among other things, provides mechanical support and electrical connections between the chip and other electronic components of a device. Substrate types include, for example, cored substrates, including thin core, thick core (laminate BT (bismaleimide-triazine resin) or FR-<NUM> type fibrous board material), and laminate core, as well as coreless substrates. Cored package substrates, for example, can be built up layer by layer around a central core, with layers of conductive material (usually copper) separated by layers of insulating dielectric, with interlayer connections being formed with through holes or microvias (vias). In other embodiments, the substrate could be a flexible substrate or flexible PCB, which is made of a thin, heat-resistant material, typically made of polymers like polyimide and polyethylene terephthalate (PET).

Please refer to <FIG> is a schematic, cross-sectional diagram showing a vertical interconnection structure in a multi-layer substrate according to one embodiment of the invention. <FIG> is a perspective view showing the vertical interconnection structure in <FIG>. It is to be understood that the number of layers of the multi-layer substrate is for illustration purposes only. For the sake of simplicity, exemplary six layers of metal interconnect (L<NUM>-L<NUM>) are shown in the figures. In <FIG>, the dielectric layers are omitted. It is to be understood that the dimensions and precise number of layers of the vertical interconnection structure may depend upon the design requirements in different cases.

As shown in <FIG>, a vertical interconnection structure VI is fabricated in a multi-layer substrate <NUM> including, but not limited to, six layers of metal interconnect (L<NUM>-L<NUM>). Preferably, the vertical interconnection structure VI may be a signal trace-to-via transition constructed in accordance with one embodiment of the invention. For example, the vertical interconnection structure VI may be used to transmit radio frequency (RF) signals between a RF chip or die and an antenna element (not shown). For example, the antenna element may be disposed in the multi-layer substrate <NUM>, but not limited thereto. Preferably, the multi-layer substrate <NUM> may include, but not limited to, a packaging substrate, a printed circuit board, or the like. Preferably, the multi-layer substrate <NUM> may include a RF circuit board that is suitable for <NUM> applications.

Preferably, the multi-layer substrate <NUM> may comprise a plurality of layers of dielectric material (or build-up layers) <NUM>-<NUM>. Preferably, the vertical interconnection structure VI may comprise a signal via structure Vs that is composed of a top layer via pad VP<NUM>, a conductor via SV<NUM> connecting the top layer via pad VP<NUM> to an inner layer via pad VP<NUM>, a conductor via SV<NUM> connecting the inner layer via pad VP<NUM> to an inner layer via pad VP<NUM>, a conductor via SV<NUM> connecting the inner layer via pad VP<NUM> to an inner layer via pad VP<NUM>, and a conductor via SV<NUM> connecting the inner layer via pad VP<NUM> to an inner layer via pad VP<NUM>. Preferably, the conductor vias SV<NUM>-SV<NUM> may be disposed in the dielectric layers <NUM>-<NUM>, respectively. Preferably, the conductor vias SV<NUM>-SV<NUM> may be contributed as a conductive path, for example, a signal path to transmit radio frequency (RF) signal. An exemplary signal trace T that terminates at the inner layer via pad VP<NUM> is disposed on the metal interconnect layer L<NUM>. The inner layer via pad VP<NUM> and the signal trace T are backed by a ground plane GL<NUM> disposed on the metal interconnect layer L<NUM>. The dielectric layer <NUM> is disposed between the inner layer via pad VP<NUM> and the ground plane GL<NUM>. In some embodiments, the top layer via pad VP<NUM> may be a bump pad.

Preferably, the vertical interconnection structure VI further comprises a ground plane (or frame) GL<NUM> disposed around the perimeter of the top layer via pad VP<NUM>, a ground plane GL<NUM> disposed around the perimeter of the inner layer via pad VP<NUM>, a ground plane GL<NUM> disposed around the perimeter of the inner layer via pad VP<NUM>, a ground plane GL<NUM> disposed around the perimeter of the inner layer via pad VP<NUM>, and a ground plane GL<NUM> disposed around the perimeter of the inner layer via pad VP<NUM>. A ground pullback region GP<NUM> is disposed between the ground plane GL<NUM> and the top layer via pad VP<NUM>. A ground pullback region GP<NUM> is disposed between the ground plane GL<NUM> and the inner layer via pad VP<NUM>. A ground pullback region GP<NUM> is disposed between the ground plane GL<NUM> and the inner layer via pad VP<NUM>. Aground pullback region GP<NUM> is disposed between the ground plane GL<NUM> and the inner layer via pad VP<NUM>. A ground pullback region GP<NUM> is disposed between the ground plane GL<NUM> and the inner layer via pad VP<NUM>. As can be discerned from <FIG>, the ground pullback regions GP<NUM>-GP<NUM> have a non-circular shape, such as a rectangular shape or a quasi-rectangular shape (two merged or partially overlapping rectangles), and electrically isolate the circular shaped via pads VP<NUM>-VP<NUM> from the ground planes GL<NUM>-GL<NUM>, respectively.

Preferably, the vertical interconnection structure VI further comprises ground vias GV<NUM> between the ground plane GL<NUM> and the ground plane GL<NUM>, ground vias GV<NUM> between the ground plane GL<NUM> and the ground plane GL<NUM>, ground vias GV<NUM> between the ground plane GL<NUM> and the ground plane GL<NUM>, ground vias GV<NUM> between the ground plane GL<NUM> and the ground plane GL<NUM>, and ground vias GV<NUM> between the ground plane GL<NUM> and the ground plane GL<NUM>.

Please refer to <FIG> illustrate layer views of the vertical interconnection structure VI from layer L<NUM> to L<NUM> in <FIG> according to an embodiment of the invention. As shown in <FIG>, the ground pullback region GP<NUM> is disposed between the non-circular ground plane GL<NUM> and the top layer via pad VP<NUM>. The outer boundary of the ground pullback region GP<NUM> has a non-circular shape, preferably a rectangular shape or a square shape. The ground pullback region GP<NUM> electrically isolates the circular shaped top layer via pad VP<NUM> from the ground plane GLe. As shown in <FIG>, the ground pullback region GP<NUM> is disposed between the non-circular ground plane GL<NUM> and the inner layer via pad VP<NUM>. The outer boundary of the ground pullback region GP<NUM> has a non-circular shape, preferably a rectangular shape or a square shape. The ground pullback region GP<NUM> electrically isolates the circular shaped via pad VP<NUM> from the ground plane GL<NUM>. As shown in <FIG>, the ground pullback region GP<NUM> is disposed between the non-circular ground plane GL<NUM> and the inner layer via pad VP<NUM>. For example, the inner layer via pad VP<NUM> may comprise two partially overlapping circular pads. The outer boundary of the ground pullback region GP<NUM> has a non-circular shape, for example, a quasi-rectangular shape or a quasi-square shape (two merged or partially overlapping rectangles). The ground pullback region GP<NUM> electrically isolates the circular shaped via pad VP<NUM> from the ground plane GL<NUM>. As shown in <FIG>, the ground pullback region GP<NUM> is disposed between the non-circular ground plane GL<NUM> and the inner layer via pad VP<NUM>. The outer boundary of the ground pullback region GP<NUM> has a non-circular shape, preferably a quasi-rectangular shape or a quasi-square shape. The ground pullback region GP<NUM> electrically isolates the circular shaped via pad VP<NUM> from the ground plane GL<NUM>. As shown in <FIG>, the ground pullback region GP<NUM> is disposed between the non-circular ground plane GL<NUM> and the inner layer via pad VP<NUM>. The outer boundary of the ground pullback region GP<NUM> has a non-circular shape, preferably a rectangular shape or a quasi-square shape. The ground pullback region GP<NUM> electrically isolates the circular shaped via pad VP<NUM> from the ground plane GL<NUM>. The non-circular ground plane GL<NUM> is formed in such as manner so as to surround the trace T in plane.

Preferably, the outer boundary of the ground pullback regions, for example, the rectangular shaped ground pullback region GP<NUM> in <FIG> or the polygonal shaped ground pullback region GP<NUM> in <FIG>, may generally include at least one set of opposite, parallel sides. For example, the rectangular shaped ground pullback region GP<NUM> in <FIG> has four sides E1∼E4. The sides E1 and E3 are in parallel to each other and the sides E2 and E4 are in parallel to each other. Further, as shown in <FIG>, the annular ground pullback region GP<NUM> may have various widths. For example, in <FIG>, the width W<NUM> is smaller than the width W<NUM>.

Please refer to <FIG> is a schematic plan view showing non-circular ground vias and non-circular signal via of a vertical interconnection structure according to a preferred embodiment of the invention. As shown in <FIG>, the vertical interconnection structure VI' comprises non-circular (or trench-type) ground vias, for example, ground vias GV<NUM>, electrically connected to a ground plane, for example, ground plane GL<NUM>, and a non-circular (or trench-type) signal via, for example, signal via SV<NUM>, electrically connected to an inner layer via pad, for example, via pad VP<NUM>. The trench-type ground vias GV<NUM> and the trench-type signal via SV<NUM> have a strip shape and are in parallel to one another. Preferably, the trench-type ground vias GV<NUM> and the trench-type signal via SV<NUM> have longitudinal axes that extend along a reference Y-axis direction.

It is beneficial to use such trench-type ground vias GV<NUM> and the trench-type signal via SV<NUM> in the vertical interconnection structure VI' because the lateral distance S<NUM> along a reference X-axis direction between inner edges of the trench-type ground via GV<NUM> and the trench-type signal via SV<NUM> is increased compared to the circular type ground via and signal via as set forth in <FIG>. Preferably, the lateral distance S<NUM> along the reference X-axis direction between outer edges of the two trench-type ground vias GV<NUM> remains substantially the same compared to the circular type ground vias as set forth in <FIG>.

<FIG> is a schematic plan view showing a close-loop, ring-type ground via surrounding a non-circular signal via of a vertical interconnection structure according to another preferred embodiment of the invention. As shown in <FIG>, the vertical interconnection structure VI" comprises a close-loop, ring-type ground via, for example, ring-type ground via GV<NUM>, electrically connected to a ground plane, for example, ground plane GL<NUM>. The ring-type ground via GV<NUM> surrounds a non-circular (or trench-type) signal via, for example, signal via SV<NUM>, electrically connected to an inner layer via pad, for example, via pad VP<NUM>. It is beneficial to use such close-loop, ring-type ground via in the vertical interconnection structure VI" because the electromagnetic interference (EMI) shielding effect can be improved.

In summary, a vertical interconnection structure particularly suited for radio frequency devices is disclosed. As can be discerned from <FIG>, the vertical interconnection structure VI may comprise a signal path (i.e., the path provided by at least the signal via structure Vs) disposed in a substrate <NUM>, a first ground plane (e.g., the ground plane GL<NUM>) surrounding the signal path, and a first ground pullback region (e.g., the ground pullback region GP<NUM>) disposed between the signal path and the first ground plane. The first ground pullback region (e.g., the ground pullback region GP<NUM>) electrically isolates the signal path from the first ground plane (e.g., the ground plane GL<NUM>). The first ground pullback region (e.g., the ground pullback region GP<NUM>) has at least two different widths.

Preferably, the signal path comprises a first via pad (e.g., the via pad VP<NUM>). The first ground pullback region (e.g., the ground pullback region GP<NUM>) is a gap between the first via pad (e.g., the via pad VP<NUM>) and the first ground plane (e.g., the ground plane GL<NUM>). Preferably, the signal path further comprises a second via pad (e.g., the via pad VP<NUM>), and a signal via (e.g., the signal via SV<NUM>) electrically connecting the first via pad (e.g., the via pad VP<NUM>) to the second via pad (e.g., the via pad VP<NUM>).

Preferably, the vertical interconnection structure further comprises a second ground plane (e.g., ground plane GL<NUM>) surrounding the second via pad (e.g., the via pad VP<NUM>); and a second ground pullback region (e.g., ground pullback region GP<NUM>) disposed between the second via pad (e.g., the via pad VP<NUM>) and the second ground plane (e.g., ground plane GL<NUM>). The second ground pullback region (e.g., ground pullback region GP<NUM>) electrically isolates the second via pad (e.g., the via pad VP<NUM>) from the second ground plane (e.g., ground plane GL<NUM>). The second ground pullback region (e.g., ground pullback region GP<NUM>) has at least two different widths.

Preferably, the vertical interconnection structure further comprises at least one ground via (e.g., ground via GV<NUM>) interconnecting the first ground plane (e.g., ground plane GL<NUM>) to the second ground plane (e.g., ground plane GL<NUM>).

Claim 1:
A vertical interconnection structure (VI) of a multi-layer substrate (<NUM>), comprising:
a first via pad (VP<NUM>) disposed in a first layer of metal interconnect (L<NUM>) of the multi-layer substrate (<NUM>);
a second via pad (VP<NUM>) disposed in a second layer of metal interconnect (L<NUM>) of the multi-layer substrate (<NUM>);
a signal via (SV<NUM>) electrically connecting the first via pad (VP<NUM>) to the second via pad (VP<NUM>);
a non-circular first ground plane (GL<NUM>) disposed in the first layer of metal interconnect (L<NUM>) of the multi-layer substrate (<NUM>) and surrounding the first via pad (VP<NUM>); and
a non-circular first ground pullback region (GP<NUM>) between the first via pad (VP<NUM>) and the non-circular first ground plane (GL<NUM>) for electrically isolating the first via pad (VP<NUM>) from the non-circular first ground plane (GL<NUM>),
the first via pad (VP<NUM>) and the second via pad (VP<NUM>) have a circular shape when viewed from above, and
the non-circular first ground pullback region (GP<NUM>) has a rectangular shape, a square shape, a quasi-rectangular shape or a quasi-square shape around a perimeter of the first via pad (VP<NUM>) when viewed from above,
characterized by
a signal trace (T) terminating at the second via pad (VP<NUM>);
wherein the second via pad (VP<NUM>) and the signal trace (T) are backed by a ground plane (GL<NUM>) disposed on a third layer of metal interconnect (L<NUM>).