Patent Description:
Generally, a semiconductor device (e.g., a semiconductor chip) communicates with the outside world through various input/output (I/O) pad structures, such as signaling pad structures, and power/ground (P/G) pad structures and the like. In some examples, a semiconductor chip can include multiple metal layers formed on top of circuitry above a substrate. One or more of the metal layers are used to form pad structures that are conductively coupled with the circuitry above the substrate. The pad structures can be formed to facilitate attachment of bonding wires that can conductively couple the pad structures with external components, such as power supply, ground, other semiconductor chips, metal lines on printed circuit board (PCB) and the like.

<CIT> discloses bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer.

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die bonded face-to-face. The first die includes first transistors formed on a face side of the first die in a semiconductor portion and at least a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and second transistors formed on a face side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. The semiconductor device includes a connection structure disposed on the back side of the first die above the semiconductor portion and conductively connected with the semiconductor portion.

In an embodiment, an interface between the connection structure and the semiconductor portion is substantially flat over the semiconductor portion. In some examples, a bottom surface and a top surface of the connection structure on the semiconductor portion are about a same size.

In some embodiments, the contact structure includes at least a first metal material that is different from a second metal material in the first pad structure. In an example, the first metal material includes tungsten and the second metal material includes aluminum.

In some examples, due to the protrusion of the end of the contact structure, a bottom surface of the first pad structure that interfaces with the insulating portion has a concave portion corresponding to the end of the contact structure.

In some embodiments, the first die includes at least a memory cell array formed in the semiconductor portion, and the second die includes a periphery circuit for the memory cell array. The contact structure on the first die is electrically coupled to an input/output circuit on the second die via bonding structures.

In some embodiments, the first die includes an input/output circuit that is electrically coupled to the contact structure.

Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes bonding a first die and a second die face-to-face. The first die includes a first substrate, first transistors formed in a semiconductor portion on a face side of the first die, and a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a second substrate with second transistors formed on a face side of the second. Further, the method includes removing the first substrate from a back side of the first die. The removing of the first substrate exposes an end of the contact structure on the back side of the first die. Then the method includes forming, on the back side of the first die, a first pad structure conductively connected with the contact structure. The end of the contact structure protrudes from the insulating portion inward the first pad structure. The method includes forming, on the back side of the first die above the semiconductor portion, a connection structure that is conductively connected with the semiconductor portion.

In an embodiment, the removing of the first substrate exposes the semiconductor portion from the back side of the first die, and the method includes depositing layers for forming the connection structure. An interface of the layers to the semiconductor portion is substantially flat over the semiconductor portion. In some examples, the method includes patterning the layers to form the connection structure. A bottom surface and a top surface of the connection structure on the semiconductor portion are about a same size.

In some embodiments, the method includes depositing, on the contact structure that includes at least a first metal material, a second metal material that is different from the first metal material. The first pad structure includes at least the second metal material. The first metal material can be tungsten and the second metal material can be aluminum in an example.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Aspects of the disclosure provide techniques for forming pad structures for a semiconductor device with two dies (e.g., a first die and a second die) bonded face-to-face. The pad structures are formed on a back side of one of the two dies, such as the first die. The techniques to form the pad structures do not need to form through silicon contacts (TSC) from the back side of the first die and simplify the processes to form the pad structures. In some embodiments, circuit components are formed on the face sides of the two dies. Additionally, at least a contact structure is formed in an insulating portion of the first die from the face side of the first die, and the contact structure is connected to an input/output (I/O) circuit. One of the pad structures on the back side of the first die, such as a first pad structure, is conductively coupled with the contact structure, and the contact structure includes an end that protrudes from the insulating portion inward the first pad structure. In some examples, the first die includes a semiconductor portion with transistors formed in the semiconductor portion. In some embodiments, a connection structure is formed with the pad structures, and is conductively coupled with the semiconductor portion. In an example, the connection structure is conductively coupled with the semiconductor portion without forming contact hole based contacts from the back side of the first die. The pad structures and the connection structure can be formed using same metal layer(s) in some examples.

According to some aspects of the disclosure, the semiconductor device can be a semiconductor memory device in which one of the two dies includes a memory cell array formed on the face side and is referred to as an array die and the other of the two dies includes periphery circuitry formed on the face side and is referred to as periphery die. In some examples, the periphery circuitry is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the periphery die is also referred to as CMOS die. The pad structures and the connection structure can be formed on the back of the array die or can be formed on the back of the periphery die.

In some embodiments, the pad structures and the connection structure are formed on the back side of the array die. The array die includes a memory cell array formed in the semiconductor portion. Then, in an example, the connection structure that is conductively coupled with the semiconductor portion can be configured to provide a connection for an array common source (ACS) of the memory cell array.

According to some aspects of the disclosure, the two dies (e.g., the array die and the periphery die) are formed separately on two wafers. In some embodiments, a first wafer that includes array dies and a second wafer that includes periphery dies are formed separately. For example, the first wafer can be fabricated to optimize density and performance of the memory cell arrays without compromising to fabrication limitations due to the periphery circuitry; and the second wafer can be fabricated to optimize the performance of the periphery circuitry without compromising to fabrication limitations due to the memory cell array. In some embodiments, the first wafer and the second wafer can be bonded face to face using a wafer-to-wafer bonding technology, thus the array dies on the first wafer are respectively bonded with periphery dies on the second wafer. Then, the techniques provided in the present disclosure can be used to fabricate pad structures on a back side of one of the two wafers.

<FIG> shows a cross-sectional view of a semiconductor device, such as a semiconductor memory device <NUM>, according to some embodiments of the disclosure. The semiconductor memory device <NUM> includes two dies that are bonded face to face. Pad structures and connection structures are formed on a back side of one of the two dies using the techniques provided in the present disclosure.

Specifically, in the <FIG> example, the semiconductor memory device <NUM> includes an array die <NUM> and a CMOS die <NUM> bonded face to face. It is noted that, in some embodiments, a semiconductor memory device can include multiple array dies and a CMOS die. The multiple array dies and the CMOS die can be stacked and bonded together. The CMOS die is respectively coupled to the multiple array dies, and can drive the respective array dies in a similar manner.

The semiconductor device <NUM> can be any suitable device. In some examples, the semiconductor device <NUM> includes at least a first wafer and a second wafer bonded face to face. The array die <NUM> is disposed with other array dies on the first wafer, and the CMOS die <NUM> is disposed with other CMOS dies on the second wafer. The first wafer and the second wafer are bonded together, thus the array dies on the first wafer are bonded with corresponding CMOS dies on the second wafer. In some examples, the semiconductor device <NUM> is a semiconductor chip with at least the array die <NUM> and the CMOS die <NUM> bonded together. In an example, the semiconductor chip is diced from wafers that are bonded together. In another example, the semiconductor device <NUM> is a semiconductor package that includes one or more semiconductor chips assembled on a package substrate.

The array die <NUM> includes one or more semiconductor portions <NUM>, and insulating portions <NUM> between the semiconductor portions <NUM>. The memory cell arrays can be formed in the semiconductor portions <NUM>, the insulating portions can isolate the semiconductor portions <NUM> and provide space for contact structures <NUM>. The CMOS die <NUM> includes a substrate <NUM>, and peripheral circuitry formed on the substrate <NUM>. For simplicity, the main surface (of the dies or wafers) is referred to as an X-Y plane, and the direction perpendicular to the main surface is referred to as Z direction.

Further, in the <FIG> example, connection structures <NUM> and pad structures <NUM>-<NUM> are formed on a back side of one of the two dies, such as the array die <NUM>. Specifically, in the <FIG> example, the pad structures <NUM>-<NUM> are above the insulating portions <NUM> and each of the pad structures <NUM>-<NUM> can be conductively connected with one or more of the contact structures <NUM>. In the <FIG> example, a connection structure <NUM> is above a semiconductor portion <NUM> and is conductively connected to the semiconductor portion <NUM>. In some examples, the semiconductor portion <NUM> is coupled to an array common source (ACS) for a memory cell array, and the connection structure <NUM> is disposed over semiconductor portion(s) <NUM> for a block of memory cell arrays. In some example, the connection structure <NUM> is formed of metal layers of relatively low resistivity, and when the connection structure <NUM> covers a relatively large portion of the semiconductor portion <NUM>, the connection structure <NUM> can connect the ACS of the block of the memory cell arrays with very small parasitic resistance. The connection structure <NUM> can include a portion that is configured as a pad structure for ACS to receive ACS signal from an external source. The pad structures <NUM>-<NUM> and the connection structure <NUM> are made of suitable metal material(s), such as aluminum, and the like that can facilitate attachment of bonding wires. In some examples, the pad structures <NUM>-<NUM> include a titanium layer <NUM> and an aluminum layer <NUM>, and the connection structure <NUM> includes a titanium silicide layer <NUM> and the aluminum layer <NUM>.

It is noted that, for ease of illustration, some components of the semiconductor memory device <NUM>, such as passivation structures, and the like are not shown.

It is noted that the array die <NUM> initially includes a substrate and semiconductor portions <NUM> and the insulating portions <NUM> are formed on the substrate. The substrate is removed before the formation the pad structures <NUM>-<NUM> and the connection structure <NUM>.

<FIG> shows a flow chart outlining a process <NUM> for forming a semiconductor memory device, such as the semiconductor memory device <NUM> according to some embodiments of the disclosure, and <FIG> show cross-sectional views of the semiconductor device <NUM> during the process in accordance with some embodiments. The process <NUM> starts from S201 and proceeds to S210.

At S210, a first die and a second die are bonded face to face. The first die includes a first substrate, and includes semiconductor portions and insulating portions disposed on the first substrate on the face side. The insulating portions can insulate the semiconductor portions. The first die also includes first transistors formed in the semiconductor portions from the face side of the first die. Further, the first die includes contact structures disposed in the insulating portions that are outside the semiconductor portions. The insulating portions can also insulate the contact structures from each other and from the semiconductor portions. The second die includes a second substrate with second transistors formed on a face side of the second die.

In some embodiments, the first die is an array die, such as the array die <NUM> and the second die is a CMOS die, such as the CMOS die <NUM>. In some examples, the first die can be a CMOS die and the second die can be an array die.

<FIG> shows a cross-sectional view of the semiconductor memory device <NUM> after a bonding process of two dies. The semiconductor memory device <NUM> includes the array die <NUM> and the CMOS die <NUM> that are bonded face to face.

In some embodiments, the array die <NUM> is fabricated with other array dies on a first wafer, and the CMOS die <NUM> is fabricated with other CMOS dies on a second wafer. In some examples, the first wafer and the second wafer are fabricated separately. For examples, memory cell arrays and I/O contact structures are formed on the first wafer using processes that operate on the face side of the first wafer. Further, first bonding structures are formed on the face side of the first wafer. Similarly, periphery circuitry is formed on the second wafer using processes that operate on the face side of the second wafer, and second bonding structures are formed on the face side of the second wafer.

In some embodiments, the first wafer and the second wafer can be bonded face to face using a wafer-to-wafer bonding technology. The first bonding structures on the first wafer are bonded with corresponding second bonding structures on the second wafer, thus the array dies on the first wafer are respectively bonded with the CMOS dies on the second wafer.

The array die <NUM> includes a substrate <NUM>. On the substrate <NUM>, one or more semiconductor portions <NUM> and insulating portions <NUM> are formed. The insulating portions <NUM> are formed of insulating material, such as silicon oxide and the like that can insulate the semiconductor portions <NUM>. Further, memory cell arrays can be formed in the semiconductor portions <NUM> and contact structures can be formed in the insulating portions <NUM>. The CMOS die <NUM> includes a substrate <NUM>, and includes peripheral circuitry formed on the substrate <NUM>.

The substrate <NUM> and the substrate <NUM> respectively can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate <NUM> and the substrate <NUM> respectively may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate <NUM> and the substrate <NUM> respectively may be a bulk wafer or an epitaxial layer. In some examples, a substrate is formed of multiple layers. For example, the substrate <NUM> includes multiple layers, such as a bulk portion <NUM>, a silicon oxide layer <NUM> and a silicon nitride layer <NUM>, as shown in <FIG>.

In the <FIG> example, the memory cell arrays are formed on the substrate <NUM> of the array die <NUM> and the peripheral circuitry is formed on the substrate <NUM> of the CMOS die <NUM>. The array die <NUM> and the CMOS die <NUM> are disposed face to face (the surface with circuitry disposed on is referred to as face, and the opposite surface is referred to as back), and bonded together.

In some examples, a semiconductor portion <NUM> is formed on the substrate <NUM>, and a block of three dimensional (3D) NAND memory cell strings can be formed in the semiconductor portion <NUM>. The semiconductor portion <NUM> is conductively coupled with an array common source of the memory cell strings. In some examples, a memory cell array is formed in a core region <NUM> as an array of vertical memory cell strings. Besides the core region <NUM>, the array die <NUM> includes a staircase region <NUM> and an insulating region <NUM>. The staircase region <NUM> is used to facilitate making connections to, for example, gates of the memory cells in the vertical memory cell strings, gates of the select transistors, and the like. The gates of the memory cells in the vertical memory cell strings correspond to word lines for the NAND memory architecture. The insulating region <NUM> is used to form the insulating portion <NUM>.

In the <FIG> example, vertical memory cell strings <NUM> are shown as representation of an array of vertical memory cell strings formed in the core region <NUM>. The vertical memory cell strings <NUM> are formed in a stack of layers <NUM>. The stack of layers <NUM> includes gate layers <NUM> and insulating layers <NUM> that are stacked alternatingly. The gate layers <NUM> and the insulating layers <NUM> are configured to form transistors that are stacked vertically. In some examples, the stack of transistors includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors and the like. In some examples, the stack of transistors can include one or more dummy select transistors. The gate layers <NUM> correspond to gates of the transistors. The gate layers <NUM> are made of gate stack materials, such as high dielectric constant (high-k) gate insulator layers, metal gate (MG) electrode, and the like. The insulating layers <NUM> are made of insulating material(s), such as silicon nitride, silicon dioxide, and the like.

According to some aspects of the disclosure, the vertical memory cell strings are formed of channel structures <NUM> that extend vertically (Z direction) into the stack of layers <NUM>. The channel structures <NUM> can be disposed separate from each other in the X-Y plane. In some embodiments, the channel structures <NUM> are disposed in the form of arrays between gate line cut structures (not shown). The gate line cut structures are used to facilitate replacement of sacrificial layers with the gate layers <NUM> in a gate-last process. The arrays of the channel structures <NUM> can have any suitable array shape, such as a matrix array shape along the X direction and the Y direction, a zig-zag array shape along the X or Y direction, a beehive (e.g., hexagonal) array shape, and the like. In some embodiments, each of the channel structures has a circular shape in the X-Y plane, and a pillar shape in the X-Z plane and Y-Z plane. In some embodiments, the quantity and arrangement of the channel structures between gate line cut structures is not limited.

In some embodiments, the channel structure <NUM> has a pillar shape that extends in the Z direction that is perpendicular to the direction of the main surface of the substrate <NUM>. In an embodiment, the channel structure <NUM> is formed by materials in the circular shape in the X-Y plane, and extends in the Z direction. For example, the channel structure <NUM> includes function layers, such as a blocking insulating layer <NUM> (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) <NUM>, a tunneling insulating layer <NUM> (e.g., silicon oxide), a semiconductor layer <NUM>, and an insulating layer <NUM> that have the circular shape in the X-Y plane, and extend in the Z direction. In an example, the blocking insulating layer <NUM> (e.g., silicon oxide) is formed on the sidewall of a hole (into the stack of layers <NUM>) for the channel structure <NUM>, and then the charge storage layer (e.g., silicon nitride) <NUM>, the tunneling insulating layer <NUM>, the semiconductor layer <NUM>, and the insulating layer <NUM> are sequentially stacked from the sidewall. The semiconductor layer <NUM> can be any suitable semiconductor material, such as polysilicon or monocrystalline silicon, and the semiconductor material may be un-doped or may include a p-type or n-type dopant. In some examples, the semiconductor material is intrinsic silicon material that is un-doped. However due to defects, intrinsic silicon material can have a carrier density in the order of <NUM><NUM> cm-<NUM> in some examples. The insulating layer <NUM> is formed of an insulating material, such as silicon oxide and/or silicon nitride, and/or may be formed as an air gap.

According to some aspects of the disclosure, the channel structure <NUM> and the stack of layers <NUM> together form the memory cell string <NUM>. For example, the semiconductor layer <NUM> corresponds to the channel portions for transistors in the memory cell string <NUM>, and the gate layers <NUM> corresponds to the gates of the transistors in the memory cells string <NUM>. Generally, a transistor has a gate that controls a channel, and has a drain and a source at each side of the channel. For simplicity, in the <FIG> example, the bottom side of the channel for transistors in <FIG> is referred to as the drain, and the upper side of the channel for transistors in <FIG> is referred to as the source. It is noted that the drain and the source can be switched under certain driving configurations. In the <FIG> example, the semiconductor layer <NUM> corresponds to connected channels of the transistors. For a specific transistor, the drain of the specific transistor is connected with a source of a lower transistor below the specific transistor, and the source of the specific transistor is connected with a drain of an upper transistor above the specific transistor in the <FIG> example. Thus, the transistors in the memory cell string <NUM> are connected in series. It is noted that "upper" and "lower" are used specific to <FIG> where the array die <NUM> is disposed upside down.

The memory cell string <NUM> includes memory cell transistors (or referred to as memory cells). A memory cell transistor can have different threshold voltages based on carrier trappings in a portion of the charge storage layer <NUM> that corresponds to a floating gate for the memory cell transistor. For example, when a significant amount of holes are trapped (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, then the memory cell transistor is in a un-programed state (also referred to as erased state) corresponding to logic "<NUM>". When holes are expelled from the floating gate, the threshold voltage of the memory cell transistor is above a predefined value, thus the memory cell transistor is in a programed state corresponding to logic "<NUM>" in some examples.

The memory cell string <NUM> includes one or more top select transistors configured to couple/de-couple the memory cells in the memory cell string <NUM> to a bit line, and includes one or more bottom select transistors configured to couple/de-couple the memory cells in the memory cell string <NUM> to the ACS.

The top select transistors are controlled by top select gates (TSG). For example, when a TSG voltage (voltage applied to the TSG) is larger than a threshold voltage of the top select transistors, the top select transistors in the memory cell string <NUM> are turned on and the memory cells in the memory cell string <NUM> are coupled to the bit line (e.g., drain of the string of memory cells is coupled to the bit line); and when the TSG voltage (voltage applied to the TSG) is smaller than the threshold voltage of the top select transistors, the top select transistors are turned off and the memory cells in the memory cell string <NUM> are de-coupled from the bit line (e.g., drain of the string of memory cells is decoupled from the bit line).

Similarly, the bottom select transistors are controlled by bottom select gates (BSG). For example, when a BSG voltage (voltage applied to the BSG) is larger than a threshold voltage of the bottom select transistors in a memory cell string <NUM>, the bottom select transistors are turned on and the memory cells in the memory cell string <NUM> are coupled to the ACS (e.g., source of the string of memory cells in the memory cell string <NUM> is coupled to the ACS); and when the BSG voltage (voltage applied to the BSG) is smaller than the threshold voltage of the bottom select transistors, the bottom select transistors are turned off and the memory cells are de-coupled from the ACS (e.g., source of the string of memory cells in the memory cell string <NUM> is de-coupled from the ACS).

Shown in <FIG>, the upper portion of the semiconductor layer <NUM> in the channel hole corresponds to a source side of the vertical memory cell string <NUM>, and the upper portion is labeled as <NUM>(S). In the <FIG> example, a common source layer <NUM> is formed in conductive connection with the source of the vertical memory cell string <NUM>. The common source layer <NUM> can includes one or more layers. In some examples, the common source layer <NUM> includes silicon material, such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon, P-type doped silicon and the like) and the like. In some examples, the common source layer <NUM> may include metal silicide to improve conductivity. The common source layer <NUM> is similarly in conductive connection with sources of other vertical memory cell strings (not shown) in the semiconductor portion <NUM>, and thus forms an array common source (ACS).

According to some aspects of the disclosure, the semiconductor portion <NUM> and the common source layer <NUM> are conductively coupled in some examples, thus the semiconductor portion <NUM> can be configured as the array common source for the vertical memory cell strings formed in the semiconductor portion <NUM>.

In the <FIG> example, in the channel structure <NUM>, the semiconductor layer <NUM> extends vertically from the source side of the channel structure <NUM> down, and forms a bottom portion corresponds to a drain side of the vertical memory cell string <NUM>. The bottom portion of the semiconductor layer <NUM> is labeled as <NUM>(D). It is noted that drain side and the source side are named for the ease of description. The drain side and the source side may function differently from the names.

In the <FIG> example, interconnection structures, such as a via <NUM>, a metal wire <NUM>, a bonding structure <NUM>, and the like, can be formed to electrically couple the bottom portion of the semiconductor layer <NUM>(D) to a bit line (BL).

Further in <FIG> example, the staircase region <NUM> includes a staircase that is formed to facilitate word line connections to the gates of transistors (e.g., memory cells, top select transistor(s), bottom select transistor(s) and the like). For example, a word line connection structure <NUM> includes a word line contact plug <NUM>, a via structure <NUM>, and metal wire <NUM> that are conductively coupled together. The word line connection structure <NUM> can electrically couple a WL to a gate terminal of a transistor in the memory cell string <NUM>.

In the <FIG> example, the contact structures <NUM> are formed in the insulating region <NUM>. In some embodiments, the contact structures <NUM> can be formed at the same time as the word line connection structures <NUM> by processing on the face side of the array die <NUM>. Thus, in some examples, the contact structures <NUM> have similar structures as the word line connection structures <NUM>. Specifically, a contact structure <NUM> can include a contact plug <NUM>, a via structure <NUM>, and metal wire <NUM> that are conductively coupled together.

In some examples, a mask that includes patterns for the contact plugs <NUM> and the word line contact plugs <NUM> can be used. The mask is used to form contact holes for the contact plugs <NUM> and the word line contact plugs <NUM>. Etch process can be used to form the contact holes. In an example, etching of the contact holes for the word line contact plugs <NUM> can stop on the gate layers <NUM> and the etching of the contact holes for the contact plugs <NUM> can stop in the oxide layer <NUM>. Further, the contact holes can be filled with suitable liner layer (e.g., titanium/titanium nitride) and a metal layer (e.g., tungsten) to form the contact plugs, such as the contact plugs <NUM> and the word line contact plugs <NUM>. Further back end of line (BEOL) processes are used to form various connection structures, such via structures, metal wires, bonding structures, and the like.

Further, in the <FIG> examples, bonding structures are respectively formed on the face sides of the array die <NUM> and the CMOS die <NUM>. For example, bonding structures <NUM> and <NUM> are formed on face side of the array die <NUM>, and bonding structures <NUM> and <NUM> are formed on the face side of the CMOS die <NUM>.

In the <FIG> example, the array die <NUM> and the CMOS die <NUM> are disposed face-to-face (circuitry side is face, and the substrate side is back) and bonded together. Corresponding bonding structures on the array die <NUM> and the CMOS die <NUM> are aligned and bonded together, and form a bonding interface that conductively couple suitable components on the two dies. For example, the bonding structure <NUM> and the bonding structure <NUM> are bonded together to couple the drain side of the memory cell string <NUM> with a bit line (BL). In another example, the bonding structure <NUM> and the bonding structure <NUM> are bonded together to couple a contact structure <NUM> on the array die <NUM> with an I/O circuit on the CMOS die <NUM>.

Referring back to S220, the first substrate of the first die is removed from the back side of the first die. The removal of the first substrate exposes the semiconductor portion and the contact structures <NUM> on the back side of the first die.

<FIG> shows a cross-sectional view of the semiconductor memory device <NUM> after the removal of the first substrate <NUM> from the array die <NUM>. In the <FIG> example, the bulk portion <NUM>, the silicon oxide layer <NUM> and the silicon nitride layer <NUM> are removed from the back side of the array die <NUM>. In some examples, after a wafer-to-wafer bonding process, a first wafer with array dies is bonded with a second wafer with CMOS dies. Then, the first substrate is thinned from the back side of the first wafer. In an example, a chemical mechanical polishing (CMP) process or a grind process is used to remove a majority portion of the bulk portion <NUM> of the first wafer. Further, suitable etch process can be used to remove remaining bulk portion <NUM>, the silicon oxide layer <NUM> and the silicon nitride layer <NUM> from the back side of the first wafer. The removal of the bulk portion <NUM>, the silicon oxide layer <NUM> and the silicon nitride layer <NUM> can reveal the ends (as shown by <NUM>) of the contact structures <NUM> that protrude from the insulating portions <NUM>. The removal of the bulk portion <NUM>, the silicon oxide layer <NUM> and the silicon nitride layer <NUM> can also reveal the semiconductor portion <NUM>.

Referring back to <FIG>, at S230, at the back side of the first die, pad structures and connection structures are formed. In some embodiments, the pad structures include first pad structures that are conductively connected with the contact structures <NUM>. The connection structures are conductively connected with semiconductor portions <NUM>.

In some embodiments, the pad structures and the connection structures are mainly formed of aluminum (Al). In some embodiments, interfacing layer(s) can be formed between the aluminum and the semiconductor portion <NUM>. In some examples, metal silicide thin films can be used as the interfacing layer(s). In an example, a metal silicide thin film can be used to enable ohmic contacts between the aluminum and the semiconductor portion <NUM>. In another example, a metal silicide thin film is used to form local interconnects to the semiconductor portion <NUM>. In another example, a metal silicide thin film is used as diffusion barriers to prevent aluminum diffusion into the semiconductor portion <NUM>.

In some examples, titanium is deposited overall on the back side of the first wafer that is face-to-face bonded with the second wafer, and is then heated in a nitrogen atmosphere. The titanium can react with exposed silicon surfaces (such as the semiconductor portion <NUM>) to form titanium silicide. The portions (e.g., above the insulating portions, above the ends of the contact structures <NUM> and the like) of titanium which did not react to form silicide.

Then, metal film(s) can be formed on the surface of the back side of the first wafer. <FIG> shows a cross-sectional view of the semiconductor memory device <NUM> after the deposition of metal film(s). In the <FIG> example, a metal film <NUM> is deposited on the back side of the first wafer. The metal film <NUM> may have uneven surface due to the protrusion by the ends of the contact structures <NUM>. In some embodiments, the metal film <NUM> includes a titanium layer <NUM> and an aluminum layer <NUM>. In an embodiment, the titanium layer <NUM> on the semiconductor portion <NUM> can react with silicon surface to form titanium silicide <NUM>. For example, the titanium layer <NUM> is deposited and heated in nitrogen atmosphere. Then the aluminum layer <NUM> is deposited.

The metal film <NUM> can be patterned to form pad structures and connection structures. <FIG> shows a cross-sectional view of the semiconductor memory device <NUM> after the metal film <NUM> is patterned into pad structures <NUM>-<NUM> and connection structure <NUM>. In the <FIG> example, the pad structures <NUM>-<NUM> are respectively connected to the contact structures <NUM> and are disposed above the insulating portions <NUM>; the connection structure <NUM> is connected to the semiconductor portion <NUM>. In some embodiments, a photolithography process is used to define patterns for the pad structures <NUM>-<NUM> and the connection structure <NUM> into a photoresist layer according to a mask, then an etch process is used to transfer the patterns into the metal film <NUM> and to from the pad structures <NUM>-<NUM> and the connection structure <NUM>.

According to an aspect of the disclosure, films of the connection structure <NUM> are directly deposited on the semiconductor portion <NUM>, thus an interface between the connection structure <NUM> and the semiconductor portion <NUM> is substantially flat over the semiconductor portion <NUM>. In a related example, the semiconductor portion <NUM> can be covered by an insulating layer, contact holes are formed in the insulating layer, then suitable metal layers are deposited (into the holes and over the insulating layer) to form contacts and connections. Comparing to the related example, the connection structure <NUM> is formed without using contact holes in insulating layers, and the interface between the connection structure <NUM> and the semiconductor portion <NUM> relatively flat, the bottom surface and the top surface of the connection structure <NUM> on the semiconductor portion <NUM> are about the same when etch profile related difference is ignored.

According to another aspect of the disclosure, due to the protrusion of the ends of the contact structures <NUM>, the metal film <NUM> may have uneven surface. For example, the bottom surface of the metal film <NUM> that interfaces with the insulating portion <NUM> may have concave portions corresponding to the ends of the contact structures <NUM>, thus the bottom surface of the pad structures <NUM>-<NUM> may have concave portions corresponding to the ends of the contact structures <NUM>.

Claim 1:
A semiconductor device, comprising:
a first die and a second die bonded face-to-face, the first die comprising first transistors formed on a face side of the first die in a semiconductor portion (<NUM>) and at least a contact structure (<NUM>) disposed in an insulating portion (<NUM>) outside the semiconductor portion (<NUM>), the second die comprising a substrate (<NUM>/<NUM>) and second transistors formed on a face side of the second die;
a first pad structure (<NUM>/<NUM>) disposed on a back side of the first die and conductively coupled with the contact structure (<NUM>), an end of the contact structure (<NUM>) protruding from the insulating portion (<NUM>) into the first pad structure (<NUM>/<NUM>); and
a connection structure (<NUM>) disposed on the back side of the first die above the semiconductor portion (<NUM>) and conductively connected with the semiconductor portion (<NUM>).