Patent Description:
Researchers, including Roger Espasa and Mateo Valero, have investigated scheme to record strided operations as base+range, and scatter/gather with the whole address range for purposes of detecting memory hazards for program ordering.

<CIT> describes secure memory paging technologies. Embodiments of the disclosure may include checking attributes of secure page cache map to determine whether a target page to be evicted is clean and replay protected by a unified version-paging data structure and checking the unified version-paging data structure to determine whether contents of the unified version-paging data structure match the target page. When the target page to be evicted is clean and replay protected and the contents match, the target page can be removed without encrypting the contents of the target page.

Described herein are systems and methods for memory protection for vector operations. Some processor architectures may implement in-order or out-of-order vector machines. Vector memory instructions can take several cycles to execute. Even for an in-order vector machine it is advantageous to allow a following instruction to begin execution before current vector instruction has completed, even when both access memory and can cause exceptions. It may also be useful to determine if a following memory instruction has any read after write (RAW), write after read (WAR), or write after write (WAW) hazards with the current vector memory instruction.

To enable fast scan of vector for memory protection violations, it is advantageous to check a vector memory instruction for any memory protection violations at high speed with minimal hardware. Each vector memory instruction may touch many elements at many different addresses and may take many cycles to execute. When the address range is known at instruction issue (e.g., for a vector with unit-stride or a greater constant stride), then the possible range of addresses can be calculated at issue time as:<MAT> where Base is a base address in memory of the vector and VL is an active vector length of the instruction. Hardware in a processor architecture may then be optimized to check only the range not each element address within the range. When addresses are not known until execution time (e.g., for scatter-gather instructions) conventional designs would be conservative and assume any address could be touched.

For unit-stride or other constant-stride vector memory instructions, if C is the number of individual hardware memory checks possible per cycle, a conventional system would only process C elements per cycle. Some processor architectures and methods described herein may increase a number of elements processed per cycle, K, for a given C to allow greater throughput from the same hardware. Checking fewer memory addresses/cycle (e.g., C=<NUM> or C=<NUM>) allows for simpler hardware, higher frequency, and/or lower power.

In the case where C=<NUM>, performance may be improved by choosing K><NUM> based on the stride value and protection granule such that still only two memory addresses need to be checked for the group, where the two memory addresses correspond to the first and last byte address touched by the group. For example, maximum number of elements per group or subvector may be determined as: <MAT> where f1() is an arbitrary function mapping the stride, width, and protection granule to a maximum number of elements. In some implementations, K may be constrained to takes values of powers of two to simplify the hardware.

In the case where C=<NUM>, the checks may be optimized by considering the base address also (e.g., K = f2(base, stride, protection-granule, machine-width)), such that checking only C=<NUM> memory address is sufficient for the group with a size K>=<NUM>. The range of addresses touched by the K-element group may be constrained to be all on a single protection granule, i.e., the last byte address is on the same protection granule as the base address. In this C=<NUM> case, either all the elements would raise a protection violation, or none of the elements would raise a protection violation, which simplifies exception handling.

In some architectures, scatter/gather vector memory operations may be contained within a memory-protection granule. If the width of the address index elements is constrained to be 8b or 16b, or any known value less than full address width, then the range is constrained independent of the data values. For unsigned n-bit indices: <MAT> Independent of the base address, if the index range would fit inside a single protection granule, then can use C=<NUM> protection checks to check entire range (e.g., check first and last byte address in range). If the base is known, then can optimize to use only a single memory check (C=<NUM>) when the base and last byte of range would fall in the same protection granule.

In some architectures, if n is unknown or large, can still optimize memory protection violation checks for scatter/gather instructions by memoizing the range of addresses that might be referenced when a vector register is used as the index vector for a scatter/gather instruction. When a vector register is written, the smallest and largest elements within the vector may be recorded. It is then guaranteed that the elements implicated by the instruction are stored within the range: <MAT> Depending on the values of base, min, and max, the memory protection checks may be handled efficiently on C=<NUM> or C=<NUM> machines.

As used herein, the term "memoize" means that the min/max are computed on the fly as a vector register is written and recorded in a microarchitectural structure (e.g., registers) on the side. The granularity at which the information is memoized may be finer (e.g., subpieces of vector registers) or coarser (e.g., groups of vector registers).

In some implementations, to save space versus having a side structure to hold min/max, but still compute min/max with fast and small circuitry, an approximation that min=(bitwise AND of all elements in the vector of indices) and max=(bitwise OR of all elements) may be used. If VL is less than the maximum possible VL, leaving tail elements undisturbed, or if some elements are masked off and left undisturbed, then the previous range is extended, rather than overwritten. If VL is less than the maximum possible VL, with tail-agnostic policy setting tail elements to their maximum possible value, or if some elements are masked off, with mask-agnostic policy setting masked-off elements to their maximum possible value, then the memoized upper bound is set to its maximum possible value. If VL is less than the maximum possible VL, with tail-agnostic policy setting tail elements to their minimum possible value, or if some elements are masked off, with mask-agnostic policy setting masked-off elements to their minimum possible value, then the memoized lower bound is set to its minimum possible value.

When min/max are known to a programmer, more efficient hazard checks may also be implemented. Instead of recording min/max, can have explicit arguments to an instruction for min/max. Can assume all elements lie within min/max, then raise exception at runtime if assumption is violated.

In some implementations, the techniques for memory protection for vector operations may be used to realize one or more advantages over conventional processors. For example, the structures and techniques described herein may enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit that has small circuit area and power consumption.

As used herein, the term "circuit" refers to an arrangement of electronic components (e.g., transistors, resistors, capacitors, and/or inductors) that is structured to implement one or more functions. For example, a circuit may include one or more transistors interconnected to form logic gates that collectively implement a logical function.

<FIG> is a block diagram of an example of an integrated circuit <NUM> for executing instructions using memory protection for vector memory operations. The integrated circuit <NUM> includes a processor core <NUM>. The processor core <NUM> includes a vector partition circuit <NUM> configured to partition vectors in memory into subvectors to facilitate fast memory protection scanning for vector memory instructions. The processor core <NUM> is configured to fetch instructions from and access data stored in a memory <NUM> external to the integrated circuit <NUM> and/or a memory <NUM> internal to the integrated circuit <NUM>. The integrated circuit <NUM> includes a memory protection circuit <NUM>, which may be configured to perform memory protection checks for one or more addresses with a protection granule. The integrated circuit <NUM> may provide advantages over conventional processor architectures, such as, for example, enabling fast memory protection scanning for vector memory operations, using a simple memory protection circuit that has small circuit area and power consumption. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>.

The integrated circuit <NUM> includes a processor core <NUM>, which may include a pipeline configured to execute instructions, including constant-stride vector memory instructions. The pipeline stages, such as fetch, decode, rename, dispatch, issue, execute, memory access, and write-back stages. For example, the processor core <NUM> may be configured to execute instructions of a RISC V instruction set.

The processor core <NUM> may be configured to fetch instructions from a memory <NUM> external to the integrated circuit <NUM> that stores instructions and/or data. The processor core <NUM> may be configured to access data in the memory <NUM> in response to instructions, including vector memory instructions (e.g., the vector load instruction <NUM> or the vector store instruction <NUM>). For example, the processor core <NUM> may access data in the memory directly or via one or more caches. The processor core <NUM> may also be configured to fetch instructions from a memory <NUM> internal to the integrated circuit <NUM> that stores instructions and/or data. The processor core <NUM> may be configured to access data in the memory <NUM> in response to instructions, including vector memory instructions. Although not shown in <FIG>, the integrated circuit <NUM> may include multiple processor cores in some implementations.

The integrated circuit <NUM> includes a memory protection circuit <NUM> configured to check for memory protection violations with a protection granule. The memory protection circuit <NUM> may allow the privileged software to define memory regions and assign memory access permission to each of them. The protection granule of the memory protection circuit <NUM> limits the size and thus resolution of these memory regions with associated access permissions. For example, the protection granule may correspond to pages of memory (e.g., 4kB or 8kB pages). In some implementations, the memory protection circuit <NUM> also specifies memory attributes for these memory regions, which may specify the ordering and merging behaviors of these regions, as well as caching and buffering attributes. The memory protection circuit <NUM> may be used to monitor transactions, including instruction fetches and data accesses by the processor core <NUM>, which can trigger a fault exception when a memory protection violation is detected. For example, an attempt to access unauthorized memory may result in a hardware fault (e.g., a segmentation fault, storage violation exception, or abnormal termination of the offending process). The memory protection circuit <NUM> may serve to prevent a process from accessing memory that has not been allocated to it, which may prevent a bug or malware within a process from affecting other processes, or the operating system. In this example, the memory protection circuit <NUM> is part of the processor core <NUM>. In some implementations, the memory protection circuit <NUM> may be outside of the processor core <NUM> (e.g., part of an external memory system).

The memory protection circuit <NUM> may be of various sizes and complexities. In some implementations, the memory protection circuit <NUM> is configured to check two addresses per clock cycle. For example, the memory protection circuit <NUM> may have two address ports that allow it to receive two addresses and independently check both of the two addresses in memory for a memory protection violation during a single clock cycle. For example, an address may be checked by comparing a memory protection key or ring for a memory region that includes the address to a memory protection key or ring number associated with a process that is being executed by the processor core <NUM> and is attempting to access the memory at the address. In some implementations, the memory protection circuit <NUM> is configured to check a single address per clock cycle, and thus may occupy less circuit area and consume less power. In some implementations, the memory protection circuit <NUM> may have more than two address ports or otherwise be configured to check more than two addresses or ranges of addresses per clock cycle for memory protection violations.

The integrated circuit <NUM> includes a vector partition circuit <NUM>. The vector partition circuit <NUM> may be configured to partition a vector being accessed in memory (e.g., the memory <NUM> or the memory <NUM>) to allow for memory protection scanning for subvectors to be performed in parallel with memory access for other subvectors of the vector and increase the throughput for vector memory instructions. The vector partition circuit <NUM> may be configured to partition a vector that is identified by a vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length. In some implementations, the maximum length may be determined based on the protection granule and a stride of a vector that is identified by a vector memory instruction (e.g., the vector load instruction <NUM> or the vector store instruction <NUM>). For example, vector partition circuit <NUM> may be configured to determine the maximum length such that the maximum length is directly proportional to the protection granule and inversely proportional to the stride of the vector. For example, the maximum length may be determined as g/s, where g is the protection granule (e.g., in bytes) and s is the stride (e.g., in bytes) of the vector. In some implementations, the maximum length is constrained to be a power of two (e.g., the largest power of two less than or equal to g/s). The maximum length may also depend on the element width of the vector. The maximum length may also depend on the machine width of the processor core <NUM>, i.e., how many elements of a vector the processor core can process per clock cycle. For example, maximum length may be determined as min(w, (g/s)), where w is the machine width of the processor core <NUM>. For example, the vector may be a unit-stride vector such that the stride is one. For example, the vector may have a constant stride that is greater than one (e.g., the stride may correspond to the length of a row in a matrix to access a column vector of a matrix data structure that is stored as a sequence of rows). The vector partition circuit <NUM> may be configured to check, using the memory protection circuit <NUM>, whether accessing elements of the subvector will cause a memory protection violation. The vector partition circuit <NUM> may be configured to access the elements of the subvector before checking, using the memory protection circuit <NUM>, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation. For example, the vector partition circuit <NUM> may be part of an execution stage of a pipeline of the processor core <NUM>.

In some implementations, the memory protection circuit <NUM> is configured to check two addresses per clock cycle, and the vector partition circuit <NUM> checks whether accessing elements of the subvector will cause a memory protection violation by inputting, during a single clock cycle, an address of a first element of the subvector and an address of a last element of the subvector to the memory protection circuit <NUM>. In some implementations, the memory protection circuit <NUM> is configured to check a single address per clock cycle, and the vector partition circuit <NUM> is configured to determine the maximum length based on a base address of the vector. For example, taking the base address for vector into account may enable the determination of a partition of the vector into subvectors aligned with protection granule boundaries in memory to ensure that a subvector is contained within a single protection granule and thus can be checked for memory protection violations with a single reference to the memory protection circuit <NUM> using an address associated with any of the elements of the subvector.

For example, the integrated circuit <NUM> may be configured to, responsive to detection of a memory protection violation associated with an element of one of the one or more additional subvectors, raise an exception. In some implementations, raising the exception may halt execution in the processor core <NUM>. In some implementations, raising the exception may cause a page to be brought in from a disk to the memory <NUM> or the memory <NUM>.

<FIG> is a block diagram of an example of an integrated circuit <NUM> for executing instructions using memory protection for vector operations. The integrated circuit <NUM> includes a processor core <NUM>. The processor core <NUM> includes a processor pipeline <NUM> that includes a vector partition circuit <NUM> configured to partition vectors in memory into subvectors to facilitate fast memory protection scanning for vector memory instructions. The processor core <NUM> includes one or more register files <NUM>, which may include vector registers. The processor core <NUM> includes an L1 instruction cache <NUM> and an L1 data cache <NUM>. The integrated circuit <NUM> includes an outer memory system <NUM>, which may include memory storing instructions and data and/or provide access to a memory <NUM> external to the integrated circuit <NUM> that stores instructions and/or data. The outer memory system <NUM> includes a memory protection circuit <NUM>, which may be configured to perform memory protection checks for one or more addresses with a protection granule. The integrated circuit <NUM> may provide advantages over conventional processor architectures, such as, for example, enabling fast memory protection scanning for vector memory operations, using a simple memory protection circuit that has small circuit area and power consumption. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>. For example, the integrated circuit <NUM> may implement the process <NUM> of <FIG>.

The integrated circuit <NUM> includes a processor core <NUM> including a pipeline <NUM> configured to execute instructions, including constant-stride vector memory instructions. The pipeline <NUM> includes one or more fetch stages that are configured to retrieve instructions from a memory system of the integrated circuit <NUM>. For example, the pipeline <NUM> may fetch instructions via the L1 instruction cache <NUM>. The pipeline <NUM> may include additional stages, such as decode, rename, dispatch, issue, execute, memory access, and write-back stages. For example, the processor core <NUM> may include a pipeline <NUM> configured to execute instructions of a RISC V instruction set.

The integrated circuit <NUM> includes one or more register files <NUM> for the processor core <NUM>. The one or more register files <NUM> may store part or all or an architectural state of the processor core <NUM>. For example, the one or more register files <NUM> may include a set of vector registers. For example, the one or more register files <NUM> may include a set of control and status registers (CSRs) For example, the one or more register files <NUM> may include a set of scalar registers.

The integrated circuit <NUM> includes an L1 instruction cache <NUM> for the processor core <NUM>. The L1 instruction cache <NUM> may be a set-associative cache for instruction memory. To avoid the long latency of reading a tag array and a data array in series, and the high power of reading the arrays in parallel, a way predictor may be used. The way predictor may be accessed in an early fetch stage and the hit way may be encoded into the read index of the data array. The tag array may be accessed in later fetch stage and may be used for verifying the way predictor.

The integrated circuit <NUM> includes an L1 data cache <NUM> for the processor core <NUM>. For example, the L1 data cache <NUM> may be a set-associative VIPT cache, meaning that it is indexed purely with virtual address bits VA[set] and tagged fully with all translate physical address bits PA[msb:<NUM>]. For low power consumption, the tag and data arrays may be looked up in serial so that at most a single data SRAM way is accessed. For example, the line size of the L1 data cache <NUM> may be <NUM> Bytes, and the beat size may be <NUM> Bytes.

The integrated circuit <NUM> includes an outer memory system <NUM>, which may include memory storing instructions and data and/or provide access to a memory <NUM> external to the integrated circuit <NUM> that stores instructions and/or data. For example, the outer memory system <NUM> may include an L2 cache, which may be configured to implement a cache coherency protocol/policy to maintain cache coherency across multiple L1 caches. Although not shown in <FIG>, the integrated circuit <NUM> may include multiple processor cores in some implementations. For example, the outer memory system <NUM> may include multiple layers.

The outer memory system <NUM> includes a memory protection circuit <NUM> configured to check for memory protection violations with a protection granule. The memory protection circuit <NUM> may allow the privileged software to define memory regions and assign memory access permission to each of them. The protection granule of the memory protection circuit <NUM> limits the size and thus resolution of these memory regions with associated access permissions. For example, the protection granule may correspond to pages of memory (e.g., 4kB or 8kB pages). In some implementations, the memory protection circuit <NUM> also specifies memory attributes for these memory regions, which may specify the ordering and merging behaviors of these regions, as well as caching and buffering attributes. The memory protection circuit <NUM> may be used to monitor transactions, including instruction fetches and data accesses by the processor core <NUM>, which can trigger a fault exception when a memory protection violation is detected. For example, an attempt to access unauthorized memory may result in a hardware fault (e.g., a segmentation fault, storage violation exception, or abnormal termination of the offending process). The memory protection circuit <NUM> may serve to prevent a process from accessing memory that has not been allocated to it, which may prevent a bug or malware within a process from affecting other processes, or the operating system.

The pipeline <NUM> includes a vector partition circuit <NUM>. The vector partition circuit <NUM> may be configured to partition a vector being accessed in memory to allow for memory protection scanning for subvectors to be performed in parallel with memory access for other subvectors of the vector and increase the throughput for vector memory instructions. The vector partition circuit <NUM> may be configured to determine a maximum length, greater than one, corresponding to a number of vector elements to be accessed in a single clock cycle. The maximum length may be determined based on the protection granule and a stride of a vector that is identified by a vector memory instruction (e.g., the vector load instruction <NUM> or the vector store instruction <NUM>). For example, the maximum length may be directly proportional to the protection granule and inversely proportional to the stride. For example, the maximum length may be determined as g/s, where g is the protection granule (e.g., in bytes) and s is the stride (e.g., in bytes) of the vector. In some implementations, the maximum length is constrained to be a power of two (e.g., the largest power of two less than or equal to g/s). The maximum length may also depend on the element width of the vector. The maximum length may also depend on the machine width of the pipeline <NUM>, i.e., how many elements of a vector the pipeline can process per clock cycle. For example, maximum length may be determined as min(w, (g/s)), where w is the machine width of the pipeline <NUM>. For example, the vector may be a unit-stride vector such that the stride is one. For example, the vector may have a constant stride that is greater than one (e.g., the stride may correspond to the length of a row in a matrix to access a column vector of a matrix data structure that is stored as a sequence of rows). The vector partition circuit <NUM> may be configured to partition the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length. The vector partition circuit <NUM> may be configured to check, using the memory protection circuit <NUM>, whether accessing elements of the subvector will cause a memory protection violation. The vector partition circuit <NUM> may be configured to
access the elements of the subvector before checking, using the memory protection circuit <NUM>, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation. For example, the vector partition circuit <NUM> may be part of an execution stage of the pipeline <NUM>.

For example, the integrated circuit <NUM> may be configured to, responsive to detection of a memory protection violation associated with an element of one of the one or more additional subvectors, raise an exception. In some implementations, raising the exception may halt execution in the processor core <NUM>. In some implementations, raising the exception may cause a page to be brought in from a disk.

<FIG> is a memory map of examples vector memory instructions <NUM> that includes a vector load instruction <NUM> and a vector store instruction <NUM>. The vector load instruction <NUM> includes an opcode <NUM>, a destination register field <NUM> that identifies an architectural register to be used to store a result of the vector load instruction <NUM>, a width field <NUM> that specifies the size of memory elements of a vector being loaded from memory, a base register field <NUM> that identifies an architectural register that stores a base address for the vector in memory, a stride register field <NUM> that identifies an architectural register that stores a stride (e.g., one for a unit-stride vector load or a another constant stride) for the vector in memory, and a mode field <NUM> that specifies additional or optional parameters (e.g., including a memory addressing mode and/or a number of fields in each segment) for the vector load instruction <NUM>. The vector store instruction <NUM> includes an opcode <NUM>, a source register field <NUM> that identifies an architectural register holding vector data for storage, a width field <NUM> that specifies the size of memory elements of a vector being stored in memory, a base register field <NUM> that identifies an architectural register that stores a base address for the vector in memory, a stride register field <NUM> that identifies an architectural register that stores a stride for the vector in memory, and a mode field <NUM> that specifies additional or optional parameters (e.g., including a memory addressing mode and/or a number of fields in each segment) for the vector store instruction <NUM>. For example, in a RISC-V processor core, the vector load instruction <NUM> may be a LOAD-FP instruction with a vector encoding extension and the vector store instruction <NUM> may be a STORE-FP instruction a vector encoding extension.

<FIG> is a flow chart of an example of a process <NUM> for memory protection for vector operations. The process <NUM> includes fetching <NUM> a vector memory instruction using a processor core; partitioning <NUM> a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length; checking <NUM> whether accessing elements of the subvector will cause a memory protection violation; if (at step <NUM>) a memory protection violation is detected, then raising <NUM> an exception; and, if (at step <NUM>) a memory protection violation is not detected, then accessing <NUM> the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation. The process <NUM> may provide advantages over conventional techniques, such as, for example, enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit that has small circuit area and power consumption. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>.

The process <NUM> includes fetching <NUM> a vector memory instruction using a processor core (e.g., the processor core <NUM>) including a pipeline configured to execute instructions, including constant-stride vector memory instructions. For example, the vector memory instruction may be the vector load instruction <NUM>. For example, the vector memory instruction may be the vector store instruction <NUM>. In some implementations, the vector memory instruction is fetched <NUM> from a memory (e.g., the memory <NUM>) via one or more caches (e.g., the L1 instruction cache <NUM>).

The process <NUM> includes partitioning <NUM> a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length. For example, the vector may be identified in part by parameters of the vector memory instruction including a base address in memory, an element width, and/or a stride that specify where the vector is or will be stored in memory. In some implementations, the maximum length may be determined based on a protection granule and a stride of the vector (e.g., the vector load instruction <NUM> or the vector store instruction <NUM>). For example, the process <NUM> may include determining the maximum length such that the maximum length is directly proportional to a protection granule of a memory protection circuit (e.g., the memory protection circuit <NUM>) and inversely proportional to the stride of the vector. For example, the maximum length may be determined as g/s, where g is the protection granule (e.g., in bytes) and s is the stride (e.g., in bytes) of the vector. In some implementations, the maximum length is constrained to be a power of two (e.g., the largest power of two less than or equal to g/s). The maximum length may also depend on the element width of the vector. The maximum length may also depend on the machine width of the processor core executing the instruction, i.e., how many elements of a vector the processor core can process per clock cycle. For example, maximum length may be determined as min(w, (g/s)), where w is the machine width of the processor core. For example, the vector may be a unit-stride vector such that the stride is one. For example, the vector may have a constant stride that is greater than one (e.g., the stride may correspond to the length of a row in a matrix to access a column vector of a matrix data structure that is stored as a sequence of rows). In some implementations, the maximum length is determined based on a base address of the vector, which may enable alignment of subvectors resulting from partitioning <NUM> of the vector with protection granules in memory to ensure that all elements of a subvector are located in a single protection granule to simplify memory protection scanning for the subvectors. For example, this simplification may enable the use of a memory protection circuit that is configured to check a single address per clock cycle, which may therefore occupy less circuit area and consume less power.

The process <NUM> includes checking <NUM>, using a memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation. In some implementations, a memory protection circuit (e.g., the memory protection circuit <NUM>) is configured to check two addresses per clock cycle, and checking <NUM> whether accessing elements of the subvector will cause a memory protection violation includes inputting, during a single clock cycle, an address of a first element of the subvector and an address of a last element of the subvector to the memory protection circuit. For example, this approach may be effective where the maximum length of the subvector ensures that the elements of the subvector can be located in no more than two adjacent protection granules. In some implementations, where the elements of the subvector are known to be in a single protection granule, checking <NUM> whether accessing elements of the subvector will cause a memory protection violation may be accomplished by inputting a single address associated with an element (e.g., the first element or any other element) of the subvector to a memory protection circuit. In some implementations, where larger subvectors are used, the complexity associated with checking <NUM> the elements of the subvector for memory protection violations may scale with the number of protection granules implicated. For example, a larger memory protection circuit with more input address ports may be used to check more elements per clock cycle to increase performance for execution of the vector memory instruction.

If (at step <NUM>) a memory protection violation is detected, then responsive to detection of a memory protection violation associated with an element of the subvector, raising <NUM> an exception. In some implementations, raising the exception may halt execution in the processor core (e.g., the processor core <NUM>). In some implementations, raising the exception may cause a page to be brought in from a disk to the memory (e.g., the memory <NUM> or the memory <NUM>).

If (at step <NUM>) a memory protection violation is not detected, then accessing <NUM> the elements of the subvector before checking (e.g., using the memory protection circuit <NUM>), whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation. For example, accessing <NUM> elements may include reading values of those elements from memory (e.g., from the memory <NUM>) during execution of a vector load instruction. For example, accessing <NUM> elements may include writing values of those elements to memory (e.g., from the memory <NUM>) during execution of a vector store instruction. The partitioning <NUM> of the vector into subvectors for memory protection scanning may thus enable more parallelism in the execution of the vector memory instruction and increase performance of the processing core. Although not explicitly shown in <FIG>, the checking <NUM> of subvectors of the vector for memory protection violations may continue in series while previously checked <NUM> subvectors continue to be accessed <NUM> in memory by a subsequent stage in a pipeline of the processor core until all subvectors have been checked <NUM> and accessed <NUM> or an exception has been raised <NUM>.

<FIG> is a flow chart of an example of a process <NUM> for memory protection for vector operations. The process <NUM> includes determining <NUM> a maximum length, greater than one, corresponding to a number of vector elements to be accessed in a single clock cycle; partitioning <NUM> the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length; checking <NUM> whether accessing elements of the subvector will cause a memory protection violation; if (at step <NUM>) a memory protection violation is detected, then raising <NUM> an exception; and, if (at step <NUM>) a memory protection violation is not detected, then accessing <NUM> the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation. The process <NUM> may provide advantages over conventional techniques, such as, for example, enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit that has small circuit area and power consumption. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>.

The process <NUM> includes determining <NUM> a maximum length, greater than one, corresponding to a number of vector elements to be accessed in a single clock cycle. The maximum length may be determined <NUM> based on a protection granule (e.g., a protection granule of the memory protection circuit <NUM>) and a stride of a vector that is identified by a vector memory instruction. In some implementations, the maximum length is directly proportional to the protection granule and inversely proportional to the stride. For example, the maximum length may be determined <NUM> as g/s, where g is the protection granule (e.g., in bytes) and s is the stride (e.g., in bytes) of the vector. In some implementations, the maximum length is constrained to be a power of two (e.g., the largest power of two less than or equal to g/s). The maximum length may also depend on the element width of the vector. The maximum length may also depend on the machine width of the processor core executing the instruction, i.e., how many elements of a vector the processor core can process per clock cycle. For example, maximum length may be determined as min(w, (g/s)), where w is the machine width of the processor core. For example, the vector may be a unit-stride vector such that the stride is one. For example, the vector may have a constant stride that is greater than one (e.g., the stride may correspond to the length of a row in a matrix to access a column vector of a matrix data structure that is stored as a sequence of rows). In some implementations, the maximum length is determined <NUM> based on a base address of the vector, which may enable alignment of subvectors resulting from partitioning <NUM> of the vector with protection granules in memory to ensure that all elements of a subvector are located in a single protection granule to simplify memory protection scanning for the subvectors. For example, this simplification may enable the use of a memory protection circuit that is configured to check <NUM> a single address per clock cycle, which may therefore occupy less circuit area and consume less power.

The process <NUM> includes partitioning <NUM> the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length. In some implementations, partitioning <NUM> the vector includes assigning groups of maximum length consecutive elements of the vector to respective subvectors until all of the elements of the vector have been assigned to a subvector. For example, a subvector may have less elements than the maximum length if the number of elements in the vector is not divisible by the maximum length. In some implementations, partitioning <NUM> the vector includes assigning groups of consecutive elements of the vector with size less than or equal to the maximum length to respective subvectors, where each group is known (e.g., based on the base address of the vector and in turn the addresses of the elements in the group) to be located within the boundaries of a single protection granule of a memory protection circuit. For example, a subvector may have less elements than the maximum length if its first element or its last element are located far from a protection granule boundary.

The process <NUM> includes checking <NUM> (e.g., using a memory protection circuit) whether accessing elements of the subvector will cause a memory protection violation. In some implementations, a memory protection circuit (e.g., the memory protection circuit <NUM>) is configured to check two addresses per clock cycle, and checking <NUM> whether accessing elements of the subvector will cause a memory protection violation includes inputting, during a single clock cycle, an address of a first element of the subvector and an address of a last element of the subvector to the memory protection circuit. For example, this approach may be effective where the maximum length of the subvector ensures that the elements of the subvector can be located in no more than two adjacent protection granules. In some implementations, where the elements of the subvector are known to be in a single protection granule, checking <NUM> whether accessing elements of the subvector will cause a memory protection violation may be accomplished by inputting a single address associated with an element (e.g., the first element or any other element) of the subvector to a memory protection circuit. In some implementations, where larger subvectors are used, the complexity associated with checking <NUM> the elements of the subvector for memory protection violations may scale with the number of protection granules implicated. For example, a larger memory protection circuit with more input address ports may be used to check more elements per clock cycle to increase performance for execution of the vector memory instruction.

<FIG> is a flow chart of an example of a process <NUM> for memory protection for vector operations using a memory protection circuit with two input address ports. The process <NUM> includes determining <NUM> a maximum length of a subvector such that elements of the subvector are stored in at most two adjacent protection granules in memory; and inputting <NUM>, during a single clock cycle, an address of a first element of the subvector and an address of a last element of the subvector to check the entire subvector for memory protection violations. By limiting the size of subvectors for processing in a partition a vector, the complexity of performing a memory protection scan for each subvector may be reduced. By tailoring the limit on the size of subvectors to a memory protection granule of the memory protection circuit and the stride and/or element width of the vector, the parallelism and performance of execution of vector memory instructions may be increased. The process <NUM> may provide advantages over conventional techniques, such as, for example, enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit that has small circuit area and power consumption. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>.

<FIG> is a flow chart of an example of a process <NUM> for memory protection for vector operations using a memory protection circuit with a single input address port. The process <NUM> includes determining <NUM> subvectors of a partition based on a protection granule of the memory protection circuit and a stride, width, and based address of a vector, such that each subvector has elements in only one protection granule in memory; and inputting <NUM> an address of any element (e.g., a first element) of a subvector to the memory protection circuit to check the entire subvector for memory protection violations. By comparing addresses of the elements of the vector to addresses corresponding to boundaries of protection granules of the memory protection circuit, a partition may be determined <NUM> to ensure all elements of a subvector are located within a single protection granule. This may reduce complexity of the memory protection scan for each subvector. The process <NUM> may provide advantages over conventional techniques, such as, for example, enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit that has small circuit area and power consumption. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>. For example, the process <NUM> may be implemented using the integrated circuit <NUM> of <FIG>.

In a first aspect, the subject matter described in this specification can be embodied in an integrated circuit for executing instructions that includes a processor core including a pipeline configured to execute instructions, including constant-stride vector memory instructions; a memory protection circuit configured to check for memory protection violations with a protection granule; and a vector partition circuit. The vector partition circuit is configured to: determine a maximum length, greater than one, corresponding to a number of vector elements to be accessed in a single clock cycle, wherein the maximum length is determined based on the protection granule and a stride of a vector that is identified by a vector memory instruction; partition the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length; check, using the memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation; and access the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.

In a second aspect, the subject matter described in this specification can be embodied in methods that include fetching a vector memory instruction using a processor core including a pipeline configured to execute instructions, including constant-stride vector memory instructions; partitioning a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length; checking, using a memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation; and accessing the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.

Claim 1:
A method comprising:
fetching (<NUM>) a vector memory instruction using a processor core (<NUM>, <NUM>) including a pipeline (<NUM>) configured to execute instructions, including constant-stride vector memory instructions;
partitioning (<NUM>) a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length;
checking (<NUM>), using a memory protection circuit (<NUM>, <NUM>), whether accessing elements of the subvector will cause a memory protection violation; and
accessing (<NUM>) the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.