Patent Description:
Some semiconductor die utilize electrostatic discharge (ESD) circuitry for discharging charge from an ESD event affecting an external die terminal. An ESD event may occur when a charged object (e.g., a human finger) inadvertently contacts a conductive surface of a semiconductor die (e.g., a contact pad) or a conductive surface of a semiconductor die package coupled to the pad where charge at an elevated voltage is applied to the conductive surface due to the contact. Being at an elevated voltage, such charge may cause voltage differentials across the devices of the semiconductor die that may exceed their safe operating areas and damage those devices. An ESD event may also occur when a charged conductive surface of a die or package contacts an external object where charge is transferred between the conductive surface and the external object.

<CIT> relates to an apparatus for an electrostatic discharge protection of a transformer balun including an input coil connected to an integrated circuit and an output coil connected to output terminals and an ESD protection circuit connected to a center tap of the output coil.

<CIT> relates to semiconductor integrated circuit including a low-noise amplifier circuit, a transformer, and an ESD protection circuit being connected to a center tap of a first winding of the transformer.

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.

The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.

As disclosed herein, a semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

In one embodiment, the ESD clamp discharges ESD current flowing in the second winding of the transformer from an ESD event affecting an external die terminal coupled to a winding terminal of the transformer. Accordingly, the ESD clamp circuit can be used to protect internal circuity of the semiconductor die electrically coupled to the second winding of the transformer from damage. In one embodiment, the transformer is used for ESD protection of an internal circuit (e.g., an amplifier) from ESD events affecting external die terminals receiving external signals to be processed by the internal circuitry.

<FIG> is a block diagram of a semiconductor die <NUM> showing portions of a receiver circuit implemented therein. Die <NUM> includes external die terminals <NUM>-<NUM> for exchanging signals or receiving supply voltages from sources external to die <NUM>. In one embodiment, die terminals <NUM>-<NUM> are implemented with die pads, but may be implemented with other types of external die terminals such as bumps or posts.

In some embodiments, die <NUM> is encapsulated with an encapsulate (e.g., molding compound, epoxy, or plastic (not shown)) to form a semiconductor die package where die <NUM> can be implemented in an electronic system such as automobile electronics, computer system, industrial control system, cellular phone, or communication device etc., depending upon the circuitry of die <NUM>. The die terminals would be electrically connected to external terminals (not shown) of the die package (not shown) with conductive structures of the die package (e.g., bond wires, solder, traces, lead frame structures).

In the embodiment of <FIG>, die <NUM> includes circuitry for implementing a receiver for receiving and processing a differential communication signal (RFINP and RFINN) at terminals <NUM> and <NUM>, respectively. In one embodiment, terminals <NUM> and <NUM> are coupled to an antenna (not shown) that may be in the same package as the die <NUM> or may be external to the package of die <NUM>. In one embodiment, the differential signal received at terminals <NUM> and <NUM> is modulated at a frequency in the Gigahertz range (e.g., in the range of <NUM>-<NUM>). However, the signal may be modulated at other frequencies in other embodiments.

The differential input signal (RFINP and RFINN) is provided to a low noise amplifier (LNA) circuit <NUM>. As will be described below with regard to <FIG>, LNA circuit <NUM> includes an LNA amplifier <NUM> and ESD circuitry for protecting the circuitry of die <NUM> from damage due to an ESD even affecting terminals <NUM> or <NUM>.

Die <NUM> includes a mixer <NUM> that mixes a low frequency clock signal (CLOCK) from low frequency oscillator (LO) <NUM> for converting the amplified differential output signals AOP, AON to a lower frequency differential signal (LFP, LFN) which is amplified and demodulated into a data signal (DATA) that is processed by processor <NUM>. In other embodiments, a receiver may have other configurations in other embodiments. For example, it may include additional mixers and/or process non differential signals and include other types of amplifiers. Also, other types of circuity such as transmitting circuitry may be implemented on die <NUM>. In some embodiments, die <NUM> may implement other types of circuits other than a receiver.

Die <NUM> also includes external die terminals <NUM>-<NUM> for receiving supply voltages VDD, VSSA, and GND ESD, respectively. Die <NUM> may include other external die terminals (not shown) including other signal die terminals and supply voltage die terminals.

<FIG> is a circuit diagram of LNA circuit <NUM> accordingly to one embodiment. Circuit <NUM> includes a low noise amplifier <NUM> for producing an amplified differential signal AOP and AON on signal lines <NUM> and <NUM>, respectively. Amplifier <NUM> is biased at its high supply terminal by rail <NUM> which is connected to VDD terminal <NUM>. The low supply terminal of amplifier <NUM> is biased by rail <NUM> which is connected to VSSA terminal <NUM>. In one embodiment, an ESD clamp circuit (not shown) is connected to both VDD rail <NUM> and VSSA rail <NUM> for discharging charge from an ESD event affecting either terminal <NUM> or <NUM>. In one embodiment, the ESD clamp circuit (not shown) electrically coupled between rail <NUM> and rail <NUM> includes a relatively large field effect transistor (FET) and a diode coupled across the source and drains of the FET. In some embodiments, the clamp circuit may include a trigger circuit (not shown) for turning on the FET in response to an ESD event.

Rail <NUM> is coupled to an ESD ground (GND ESD) rail <NUM> by an ESD clamp circuit <NUM> for discharging charge from an ESD event affecting terminal <NUM> or terminal <NUM>. In the embodiment shown, clamp circuit <NUM> is implemented with diodes in an anti-parallel configuration. Accordingly, if an ESD event affecting terminal <NUM> raises the voltage of rail <NUM> above the voltage of rail <NUM> (or vice versa) by a threshold voltage of clamp circuit <NUM>, ESD charge will be discharged to the lower voltage bus. In one embodiment, the diodes of clamp circuit <NUM> are shallow trench isolation (STI) diodes. Ground rail <NUM> may traverse other locations of die <NUM> and may be coupled to other ground rails of other domains (not shown) by ESD clamp circuits (not shown) similar to ESD clamp circuit <NUM>.

Circuit <NUM> includes circuitry for protecting LNA amplifier <NUM> from ESD events affecting terminals <NUM> and <NUM>. In the embodiment shown, transformer <NUM> includes a primary side winding with input terminals <NUM> and <NUM> coupled through lines <NUM> and <NUM>, respectively, to terminals <NUM> and <NUM>, respectively. The center tap <NUM> of transformer <NUM> is connected to a first terminal of an ESD clamp circuit <NUM>. The second terminal of ESD clamp circuit <NUM> is connected to VSSA rail <NUM>. Consequently, charge from an ESD event affecting at least one of terminal <NUM> or <NUM>, either elevating the voltage of that terminal above the voltage of rail <NUM> or dropping he voltage below the voltage of rail <NUM>, will have a discharge path through the primary windings of transformer <NUM>, through center tap <NUM>, and through clamp circuit <NUM> to rail <NUM>. An ESD event affecting a die terminal may include an ESD occurring at the die terminal or at package terminal coupled to the die terminal.

In the embodiment shown, clamp circuit <NUM> is implemented with two diodes in an antiparallel configuration, where the anode of one diode and the cathode of the other diode are connected to one clamp terminal and the cathode of the one diode and the anode of the other diode are connected to the other terminal of the clamp circuit. In one embodiment, the two diodes of clamp circuit <NUM> are implemented with gated diodes. In some embodiments, utilizing gated diodes in an ESD clamp circuit may provide for a relatively fast turn on ESD discharge voltage and reduced voltage overshoot for fast charge device model (CDM) transients. In addition, utilizing gated diode in an ESD clamp circuit may also provide for relatively good ESD robustness per input capacitance. However, other types of ESD clamp circuits can be utilized in other embodiments.

In the embodiment shown, center tap <NUM> is biased at reference voltage VB to set the common mode voltage of the differential inputs of LNA amplifier <NUM>. In one embodiment, voltage VB is halfway between the voltage of VDD and the voltage of VSSA.

During an ESD event affecting terminal <NUM> or terminal <NUM>, ESD charge on either of terminal <NUM> or <NUM> discharging to rail <NUM> through the primary winding of transformer <NUM> and clamp circuit <NUM> (or discharging from rail <NUM> to terminal <NUM> or <NUM>), may generate a voltage across at least half of the secondary winding of transformer <NUM>. Accordingly, to protect LNA <NUM> from damage due to such ESD events, an ESD clamp circuit <NUM> includes a terminal connected to the center tap <NUM> of the secondary winding of transformer <NUM> and a second terminal connected to supply rail <NUM> for providing a pathway for discharging ESD current that develops on the secondary winding from an ESD event that affects either terminal <NUM> or <NUM>.

In the embodiment shown, clamp circuit <NUM> includes two diodes <NUM> and <NUM> coupled in series to provide a diode path for discharging ESD current from tap <NUM> to rail <NUM> when tap <NUM> is at a higher voltage than VSSA rail <NUM> during an ESD event by the threshold voltage of the diode path. The anode of diode <NUM> is connected to tap <NUM> and the cathode of diode <NUM> is connected to rail <NUM>. The cathode of diode <NUM> is connected to the anode of diode <NUM>. In one embodiment, two diodes (<NUM> and <NUM>) are positioned in series between tap <NUM> and rail <NUM> due to tap <NUM> being biased at VB (e.g., <NUM> mV) so to increase the voltage threshold of the clamp in the current direction and to reduce leakage current at higher temperatures when no ESD event is occurring.

Clamp circuit <NUM> also includes a diode <NUM> positioned in a diode path that is in an anti-parallel configuration with the diode path of diodes <NUM> and <NUM>. Diode <NUM> provides a path for discharging ESD current from rail <NUM> to tap <NUM> when tap <NUM> is at a lower voltage than VSSA rail <NUM> during an ESD event by the threshold voltage of the diode path (e.g., the diode drop of diode <NUM>). In one embodiment, diodes <NUM>-<NUM> are gated diodes that may provide for improved ESD performance in an ESD clamp circuit as described above.

In one embodiment, clamp circuits <NUM> and <NUM> has on resistance of approximately one ohm, but may be of other values in other embodiments. In one embodiment, clamp circuit <NUM> has a turn-on threshold voltage of <NUM> volts in both directions, whereas clamp circuit <NUM> has a turn-on voltage of <NUM> volts in one direction and <NUM> volts in the other direction due to diodes <NUM> and <NUM>, however these voltages may be of other values in other embodiments.

In one embodiment, protecting LNA amplifier <NUM> from ESD events at its inputs with a transformer (<NUM>) whose taps are coupled to a supply rail with ESD clamp circuits may provide for an ESD protection scheme that has a relatively low parasitic capacitance and junction capacitance while minimizing input leakage for the high frequency signals (e.g., in the Gigahertz range). Such an ESD scheme may reduce the degradation of key RF parameters such as noise figure (NF), linearity (IIP1, IIP3), impedance matching (S11), and gain S21) over conventional ESD protection schemes. Implementing a clamp circuit (<NUM>) on the secondary tap (<NUM>) provides protection to the inputs of amplifier <NUM> from high voltages that may occur on the secondary windings due to an ESD event affecting terminals <NUM> and <NUM>. Thus, such a center tap clamp circuit <NUM> may enable the use of a transformer for in an ESD protection scheme of an amplifier circuit in that it protects against an over voltage condition on a secondary side of the transformer <NUM>.

<FIG> is another circuit diagram showing a portion of circuitry of die <NUM>. In the embodiment of <FIG>, the primary winding of transformer <NUM> is implemented with a circular signal line <NUM> around a circular signal line <NUM> that is used to implement the second winding of transformer <NUM>. In one embodiment, signal lines <NUM> and <NUM> are implemented in a metal layer (not shown) in die <NUM> that is located above the semiconductor substrate (not shown) of die <NUM>. However, a transformer may be implemented in a semiconductor die with other structures in other embodiments.

In the embodiment shown, signal lines <NUM> and <NUM> are implemented with a co-planer wave guide <NUM> that includes directional couplers <NUM> and <NUM>. Typically, a directional coupler is a device used for sampling incident and/or reflected power of a signal. In the embodiment shown, directional couplers <NUM> and <NUM> are each connected to an ESD clamp circuit <NUM> and <NUM>, respectively, for discharging ESD current to VSSA rail <NUM> during an ESD event affecting terminal <NUM> or terminal <NUM> for protecting the directional couplers from damage. In the embodiment shown, clamp circuits <NUM> and <NUM> are implemented with gated diodes in an anti-parallel configuration, but other types of clamp circuits may be utilized in other embodiments. Other embodiments may not include clamp circuits <NUM> and <NUM>.

In one embodiment, clamp circuit <NUM> is implemented in a solder ball breakage detection circuit (not shown) of the semiconductor die <NUM>, but may be implemented in other circuits of die <NUM> in other embodiments.

<FIG> is a circuit diagram of an LNA circuit 1clamp <NUM> according to another embodiment. The items in the embodiment of <FIG> having the same reference numbers as the items in the embodiment of <FIG> are similar.

Circuit <NUM> of <FIG> is different than circuit <NUM> of <FIG> in that circuit <NUM> of <FIG> has an additional VSSA external die terminal <NUM>, an additional VSSA rail <NUM>, an additional ESD GND rail <NUM>, and an additional GND ESD terminal <NUM>. Terminal <NUM> is configured to be biased at the same supply voltage as terminal <NUM>, and terminal <NUM> is configured to be biased at the same supply voltage as terminal <NUM>. Rail <NUM> is coupled to rail <NUM> with an ESD clamp circuit <NUM> that is similar to ESD clamp circuit <NUM>.

Center tap <NUM> is coupled to rail <NUM> with ESD clamp circuit <NUM>, which in the embodiment shown in implemented with two diodes in an anti-parallel configuration. Center tap <NUM> is coupled to rail <NUM> with an ESD clamp circuit <NUM>. In the embodiment shown, clamp circuit <NUM> has a configuration similar to clamp circuit <NUM>. One advantage of having the additional VSSA rail, GND ESD rail <NUM>, and ESD clamp circuits <NUM>, <NUM>, and <NUM> is that it provides additional path ways for discharging ESD current for an ESD event at terminals <NUM> and <NUM>. An ESD clamp circuit (not shown) is coupled to VDD rail <NUM> and VSSA rail <NUM> for discharging ESD current between the two rails.

In <FIG>, the ESD clamp circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are implemented with diodes in an anti-parallel configuration. Although the Figures show the clamp circuits with diode paths of <NUM> or <NUM> diodes, other clamp circuits may include diode paths with a different number of diodes. Also, these ESD clamp circuits may be implemented with other types of ESD clamp circuits such as clamp circuits with a transistor (e.g., FETs, bipolar transistors).

<FIG> is a circuit diagram of an ESD clamp circuit according to another embodiment of the present invention. Clamp circuit <NUM> can used for clamp circuit <NUM> of <FIG> and clamp circuit <NUM> of <FIG>. Circuit <NUM> can also be used for circuits <NUM> and <NUM>. In the embodiment shown, clamp circuit <NUM> includes an NFET <NUM> with a source connected to rail <NUM> and its drain connected to center tap <NUM>. The gate of NFET <NUM> is coupled to rail <NUM> through a resistor <NUM>. In one embodiment, resistor <NUM> is <NUM> ohms, but may be of other values in other embodiments, depending upon the desired threshold voltage of the clamp circuit. In one embodiment, clamp circuit <NUM> is characterized as having a grounded gate NMOS configuration. In one embodiment, the turn on threshold voltage of clamp circuit <NUM> is <NUM>.

Although the Figures show embodiments where transformer <NUM> is utilized for ESD protection, a transformer with a clamp circuit electrically coupling its secondary center tap to ground may be utilized in other types of circuits. For example, such a transformer may be used to step down or step up a supply voltage. Also, such a transformer may be used for ESD protection of non differential signal terminal inputs.

Also, in other circuits, the terminals of the secondary winding may be electrically coupled to external die terminals and the terminals of the primary winding may be coupled to internal circuitry. With such an embodiment, the primary center tap would be coupled to a supply rail with an ESD clamp circuit (e.g., similar to circuit <NUM>) for ESD protection of the internal circuitry. Such a transformer may be used by a semiconductor die in providing an output signal (e.g., to an antennae for transmission). Also, such a transformer may be used by a power supply controller for externally providing a step up or step down supply voltage.

A source and drain are current terminals of a FET. A gate is a control terminal of a FET.

Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

In an embodiment, a semiconductor die includes a transformer including a primary winding and a secondary winding. The primary winding includes a first terminal electrically coupled to a first external die terminal, a second terminal electrically coupled to a second external die terminal, and a first center tap. The secondary winding includes a third terminal, a fourth terminal, and a second center tap. The semiconductor die includes a first electrostatic discharge (ESD) clamp circuit including a fifth terminal electrically coupled to the first center tap and a sixth terminal electrically coupled to a supply rail. When made conductive in response to an ESD event affecting at least one of the first external die terminal and the second external die terminal, the first ESD clamp circuit discharges ESD current between the first center tap and the supply rail. The semiconductor die includes a second ESD clamp circuit including a seventh terminal electrically coupled to the second center tap and an eighth terminal electrically coupled to the supply rail. When made conductive in response to the ESD event affecting at least one of the first external die terminal and the second external die terminal, the second ESD clamp circuit discharges ESD current between the second center tap and the supply rail.

Claim 1:
A semiconductor die (<NUM>), comprising:
a transformer (<NUM>) including a first winding and a second winding, wherein:
the first winding includes a first terminal (<NUM>) electrically coupled to a first external die terminal (<NUM>) and a second terminal (<NUM>) electrically coupled to a second external die terminal (<NUM>); and
the second winding includes a third terminal (<NUM>), a fourth terminal (<NUM>), and a center tap (<NUM>), wherein:
the third terminal and the fourth terminal are electrically coupled to internal circuitry (<NUM>) of the semiconductor die;
a first electrostatic discharge (ESD) clamp circuit (<NUM>) including a fifth terminal electrically coupled to the center tap (<NUM>) of the second winding and a sixth terminal electrically coupled to a supply rail (<NUM>), wherein the ESD clamp circuit when made conductive during an ESD event, discharges ESD current between the center tap and the supply rail;
wherein the first winding includes a center tap (<NUM>);
wherein the semiconductor die includes a second ESD clamp circuit (<NUM>) including a seventh terminal electrically coupled to the center tap (<NUM>) of the first winding and an eighth terminal electrically coupled to the supply rail, wherein the second ESD clamp circuit when made conductive during an ESD event affecting at least one of the first external die terminal and the second external die terminal, discharges ESD current between the center tap of the first winding and the supply rail.