Patent Description:
In some embodiments, multiple levels of Forward Error Correction (FEC) codes are used, including binary (bit-level) and non-binary (symbol level) FEC codes.

Spreading of a signal over multiple time/frequency resources is performed for the purpose of achieving higher diversity, reliability and robustness to interference and channel variations.

Code division multiple access (CDMA) is a multiple access technique in which data symbols are spread out over orthogonal or near-orthogonal code sequences. Conventional CDMA encoding is a two-step process in which a binary code is mapped to a quadrature amplitude modulation (QAM) symbol before a spreading sequence is applied. CDMA can be considered a form of repetition of QAM symbols by using different amplitude and phases in accordance with the spreading sequence.

Conventional CDMA encoding can provide relatively high coding rates. However, new techniques/mechanisms for achieving even higher coding rates may be desirable to meet the ever-growing demands of next-generation wireless networks. Low density spreading (LDS) is a form of CDMA used for multiplexing different layers of data. LDS uses repetitions of the same symbol on layer-specific nonzero positions in time or frequency. As an example, in LDS-orthogonal frequency division multiplexing (OFDM) a constellation point is repeated over nonzero frequency tones of an LDS block. This sparse spreading helps reduce the decoding complexity when many (e.g., more than the spreading length) LDS signals are multiplexed together.

In sparse code multiple access (SCMA), a multidimensional codebook is used to spread data over tones without necessarily repeating symbols. In SCMA the multidimensional spreading codebooks are sparse and hence detection can be made simpler.

<CIT> concerns an apparatus and method in a receiver for assigning reliability weight factors (RWFs) to soft metrics output from demodulators in a mobile communication system using different modulation schemes. Codeword level scrambling for MIMO transmission is described in <CIT>. <CIT> suggests encoding an input signal using a forward error correcting code to produce a codeword corresponding to the input signal.

Embodiments of the present invention are specified by the appended claims.

Embodiments will be described in greater detail with reference to the accompanying drawings.

It should be understood at the outset that although illustrative implementations of one or more embodiments of the present disclosure are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or later developed. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims.

Demand for higher data rates in telecommunications systems continues to increase. At the same time, more transmission flexibility and robustness toward network impairments is demanded with minimal change to current network architecture. Improvement in efficient signalling design for signal spreading and multi-user signal multiplexing by reusing current physical layer structure is an area that could aid in meeting these demands.

Aspects of the present disclosure may involve using current physical layer communication system structure to provide efficient signaling design for spreading. Signal spreading may provide more reliability, diversity and robustness towards network impairments. Multi-user signal multiplexing may provide more spectral efficiency, scheduling flexibility, robustness to channel state information (CSI) feedback accuracy, robustness to channel aging, and robustness to issues that may arise from UE mobility, for example.

The present disclosure provides many different methods that can be used or performed by a transmitter. A first comparative method includes generating different streams of binary sequences at the output of a bit mapping component that is coupled to an output of a FEC encoder, e.g. a turbo encoder, and mapping each stream of the binary sequences to a QAM symbol or another complex-valued modulation symbol using a stream-specific modulator, and mapping these streams of complex-valued modulation symbols to another stream of complex-valued symbols using a non-binary FEC encoding, such as Reed-Solomon encoding.

The comparative method may include generating different streams of binary sequences at the output of a bit mapping component that is coupled to an output of a FEC encoder, e.g. a turbo encoder, and mapping each stream of the binary sequences to a QAM symbol or another complex-valued modulation symbol.

An embodiment according to the invention of a method at a transmitter includes two-level FEC encoding. Such a method may involve using binary FEC encoding to generate a coded bit stream which is then divided into a plurality of coded bit streams, mapping each coded bit stream to a QAM symbol or another complex-valued modulation symbol using a stream-specific modulator to generate a plurality of QAM symbols or other complex-valued modulation symbols, and mapping these complex-valued modulation symbols to complex-valued symbols using a non-binary FEC encoding, such as Reed-Solomon encoding.

A method at a transmitter could also involve applying sparse spreading on the generated complex-valued symbols by mapping the complex-valued symbols to non-zero entries of a signature pattern.

A comparative method at a transmitter involves multiplexing complex-valued signals that are to be transmitted to multiple UEs. In an example, the comparative method involves generating complex-valued modulation symbols for each UE signal using a UE-specific (and/or user-specific) mapping rule and/or UE-specific (and/or user-specific) sparse spreading, and multiplexing the symbols in the UEs' signals together using a UE-specific (and/or user-specific) power scaling vector.

In another example, the comparative method at a transmitter involve generating a signal that includes data to be transmitted to a plurality of UEs. Binary sequences are generated by a stream-specific bit mapper that is coupled to an output of an FEC encoder, e.g. a turbo encoder, and each multiplexed binary sequence is mapped to a QAM symbol or another complex-valued modulation symbol using a stream-specific modulator.

An embodiment of the invention includes, at a transmitter, generating the signal that includes the data to be transmitted to a plurality of UEs by first using a binary FEC to generate a plurality of coded bit streams for each UE, and then multiplexing the coded bit streams of different UEs to generate a binary stream which is then mapped to a plurality of binary streams using a bit mapping component. The method further includes mapping each binary stream to a QAM symbol or another complex-valued modulation symbol using a stream-specific modulator, generating a plurality of QAM symbols or other complex-valued modulation symbols, and mapping the complex-valued modulation symbols to a plurality of complex-valued symbols using non-binary FEC encoding.

The present disclosure also provides many different comparative methods that can be used or performed by a receiver. A first comparative method at a receiver includes attempting to decode the data of at least one of a plurality of UEs. The comparative method further includes joint maximum likelihood (ML) detection of the data of at least one of the plurality of UEs, calculating the log-likelihood ratios (LLRs) for the coded bits of at least one of the plurality of UEs, and decoding the data of at least one of the plurality of UEs using FEC decoding, e.g. in a Turbo decoder.

In another example, a comparative method at a receiver involves using a message passing algorithm (MPA) to calculate the LLRs for the coded bits of at least one of a plurality of UEs, and decoding the data of at least one of the plurality of UEs using FEC decoding, e.g. in a Turbo decoder.

Another comparative method at a receiver includes QAM de-mapping to generate the likelihood values of each symbol that includes data for at least one of plurality of UEs, iterative message passing to find a second set of LLRs for coded bits of at least one of plurality of UEs, and decoding the data of at least one of plurality of UEs using FEC decoding, e.g. in a Turbo decoder.

Another comparative method at a receiver includes non-binary FEC decoding to generate the likelihood values of each symbol that includes the data of at least one of plurality of UEs, iterative message passing to find the second set of LLRs for coded bits of at least one of plurality of UEs, and decoding the data of at least one of plurality of UEs using FEC decoding, e.g. in a Turbo decoder.

Example embodiments will now be described with reference to the drawings. The embodiments set forth herein represent information sufficient to practice the claimed subject matter and illustrate the best way of practicing such subject matter. Upon reading the following description in light of the accompanying figures, those of skill in the art will understand the concepts of the claimed subject matter and will recognize applications of these concepts not particularly addressed herein.

Moreover, it will be appreciated that any module, component, or device disclosed herein that executes instructions may include or otherwise have access to a non-transitory computer/processor readable storage medium or media for storage of information, such as computer/processor readable instructions, data structures, program modules, and/or other data. A non-exhaustive list of examples of non-transitory computer/processor readable storage media includes magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, optical disks such as compact disc read-only memory (CD-ROM), digital video discs or digital versatile discs (i.e. DVDs), Blu-ray Disc™, or other optical storage, volatile and non-volatile, removable and non-removable media implemented in any method or technology, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology. Any such non-transitory computer/processor storage media may be part of a device or accessible or connectable thereto. Computer/processor readable/executable instructions to implement an application or module described herein may be stored or otherwise held by such non-transitory computer/processor readable storage media.

Embodiments disclosed herein could be applied in multiple access scenarios, including but not in any way limited to non-orthogonal multiple access NoMA, for example. <FIG> is a block diagram illustrating an example of an apparatus that could be used in implementing a NoMA scheme.

NoMA generally allows multiple signals to be transmitted from one or more transmitters to one or more receivers simultaneously on a given shared resource. The shared resource may include a time resource, a frequency resource, a space resource or some combination thereof. In a downlink (DL) scenario, a network side device can transmit to multiple separate user equipment (UE). In an uplink (UL) scenario multiple UEs can transmit to a network side receiver.

In the UL NoMA scenario, the UEs process information bits arranged in one or more layers to become symbols for transmission on multiple tones. In NoMA, there are likely to be collisions of symbols from the multiple UEs at the receiver that receives the signals. A NoMA technique may attempt to distinguish the transmitted signals from the multiple UEs by applying some UE specific (and/or user-specific) or layer-specific features that are unique to the UE or layer, respectively.

Distinct multiple access schemes can be developed based on such UE-specific (and/or user-specific) or layer specific (or both) features or signal processing operations. These signal processing operations may include, but are not limited to: FEC, bit-level interleaving/scrambling; modulated symbol sequence generator; and symbol to RE mapping.

A framework is proposed for generating a NoMA signal based on selection of a particular set of signal processing operations. The set of signal processing operations are then used to process information bits and generate the NoMA signal for transmission. Various NoMA schemes that each includes a different subset of the signal processing operations can be derived using the framework. Such a framework can be used by a UE to select a NoMA scheme having a set of signal processing operations that meets a desired transmission application.

<FIG> illustrates an example of a system <NUM> implementing a collection of signal processing operations that may be part of a framework for generating a NoMA signal, which includes units to function as a FEC encoder <NUM>, a bit-level interleaver/scrambler <NUM>, a modulated symbol sequence generator <NUM>, and a symbol to RE mapper <NUM>. Bit-level operations and symbol-level operations are also labelled at <NUM>, <NUM>, respectively, in <FIG>.

A stream of information bits is provided to the FEC encoder <NUM> to perform forward error correction (FEC) encoding <NUM>. The information bits are processed with a FEC channel code, which could be a low density parity check (LDPC) code, a Turbo code, a polar code, or another type of code. For instance, a block of K information bits is encoded and N > K coded bits are generated.

The encoded bits are then provided to bit-level interleaver/scrambler <NUM> for bit-level interleaving/scrambling. In the bit-level interleaver/scrambler <NUM>, the coded bits are interleaved and/or scrambled, and interleaved/scrambled bits are generated. The bit-level interleaver/scrambler <NUM> could be user- (or receiver) specific, such that each user or receiver is associated with a specific interleaver/scrambler sequence or scheme, or is associated with a cell-specific interleaver/scrambler sequence, such that a specific interleaver/scrambler sequence or scheme is applied for receivers in each cell or service area in a network.

An output of coded bits from the bit-level interleaver/scrambler <NUM> is provided to the modulated symbol level sequence generator <NUM>. The modulated symbol level sequence generator <NUM> generates symbols from the coded bits. In the modulated symbol sequence generator <NUM>, the interleaved/scrambled bits are mapped to modulated symbols, with or without additional symbol-level spreading operations. The bit-to-symbol mapping could be one or multiple bits to one or multiple symbols. Symbol-level spreading could involve multiplying the symbols with spreading codes, which may include one or multiple stages, and the length of spreading code could be different at each stage.

Although not specifically shown in <FIG>, an output of the modulated symbol level sequence generator <NUM> could be provided to a symbol sequence precoder that performs symbol precoding. Such precoding could be intended to reduce the peak to average power ratio (PAPR) of a transmitted signal, which may improve coverage of the transmitted signal. In the case of an OFDM waveform, discrete Fourier transform (DFT) precoding might be used.

A symbol sequence, which may have been precoded, is provided to the symbol to resource element (RE) mapper <NUM>. The modulation symbols are mapped to resource elements for transmission, with or without additional symbol-level interleaving/scrambling. A symbol-level interleaver/scrambler could be user-specific, such that each user has a specific symbol-level interleaver/scrambler sequence or scheme, or cell-specific, with a specific symbol-level interleaver/scrambler sequence or scheme being applied for the receiver in each cell or coverage area of a network.

Other operations or features could also be implemented. For example, a waveform modulator could be implemented to generate, after the symbols have been mapped the REs, the actual signal to be transmitted over the air.

According to the framework illustrated in <FIG>, information bits are first encoded using a FEC encoder, and bit-level interleaving/scrambling is applied to coded bits. These are bit-level operations. UE-specific, or more generally user-specific, symbol-level operations including modulated symbol sequence generation and symbol-to RE mapping are applied. Such a framework may assist a receiver in decoding signals of multiplexed receivers more efficiently.

<FIG> is intended solely as an illustrative example of a multiple access scenario in which disclosed embodiments could be applied. Embodiments disclosed herein could be used, for example, to implement modulated symbol sequence generation at <NUM> in <FIG>. As will be apparent from the other drawings and the following description, however, embodiments could be related to other parts of the NoMA framework illustrated in <FIG>.

Referring to <FIG>, an example of a general framework for signal spreading will be described. <FIG> is a block diagram of an apparatus implementing a signal spreading technique according to an aspect of the disclosure. The example apparatus includes a binary FEC encoder <NUM>, a bit mapper <NUM> coupled to the binary FEC encoder, modulators 150a, 150b, 150c coupled to the bit mapper, and a non-binary FEC encoder <NUM> coupled to the modulators. The components in <FIG> could be implemented in circuitry that is configured to perform operations as disclosed herein. These components could be implemented using hardware, firmware, and/or other components which execute software that is stored on one or more non-transitory computer or processor readable media (e.g. in the form of modules), examples of which are provided above, or some combination thereof. Electronic devices that might be suitable for implementing any or all of these components include, among others, microprocessors, microcontrollers, Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), and/or other types of "intelligent" integrated circuits.

A bit stream or sequence <NUM> is shown to represent input binary bits that are to be transmitted to an intended receiver, such as user equipment (UE). The input bits of the bit sequence <NUM> are fed into the binary FEC encoder <NUM> to generate the stream or sequence of coded bits <NUM>. Then, the sequence of coded bits <NUM> is mapped to a plurality of binary sequences 140a, 140b and 140c using a bit mapper <NUM>. The binary sequences 140a-c include subsets of the coded bits <NUM>. These subsets are determined by bit mapper <NUM>. Bit mapper <NUM> also determines the order of the coded bits in each binary sequence 140a-c. The bit mapper <NUM> could interleave, scramble, or otherwise change the order of the coded bits <NUM> before they are mapped to the binary sequences 140a-c. A separate bit level interleaver / scrambler as shown at <NUM> in <FIG>, could be provided and coupled between the binary FEC encoder <NUM> and the bit mapper <NUM>. Or, a bit mapper <NUM> performs any bit-level interleaving, and a separate bit-level scrambler is coupled between the FEC encoder <NUM> and the bit mapper.

The binary sequences 140a-c are mapped to complex-value symbols 160a, 160b and 160c using stream-specific modulators 150a, 150b and 150c. The modulators 150a-c could be QPSK modulators, for example. Or, the modulators 150a-c are QAM modulators with Gray labeling or different labeling. Different modulators 150a-c could potentially be used for different streams.

The set of complex-value symbols 160a, 160b and 160c are fed into the non-binary FEC encoder <NUM> to generate the output symbols <NUM> to be transmitted. The non-binary FEC encoder <NUM> could apply a spreading matrix in which the output of each modulator 150a-c is multiplied by a spreading sequence. Symbol-level scrambling and/or interleaving could also or instead be implemented by the non-binary FEC encoder <NUM>, by applying a scrambling sequence and/or interleaving matrix to the symbols 160a-c.

With reference to the NoMA architecture in <FIG>, the generated output symbols <NUM> could be provided as inputs for symbol to RE mapping at <NUM>.

Referring to <FIG>, an example of a general framework for signal spreading and multi-user multiplexing shown in <FIG> will be described. <FIG> is a block diagram of an apparatus implementing a signal spreading technique according to another aspect of the disclosure. The apparatus in <FIG>, like the apparatus in <FIG>, includes a binary FEC encoder <NUM>, a bit mapper <NUM> coupled to the binary FEC encoder, and modulators 250a, 250b, 250c coupled to the bit mapper. The example implementations of components in <FIG> provided above also apply to the corresponding components in <FIG>. Operation of components as described above with reference to <FIG> also apply to the corresponding components in <FIG>.

The sequence <NUM> is shown to represent input binary bits that are to be transmitted to a receiver, such as a UE, for uplink communications, and/or for uplink communications from UEs to a base station or a network node. Therefore, a UE is referenced herein as an illustrative example of a receiver. A base station, network node, or other network equipment could also or instead be an intended receiver of transmitted signals.

Input bits <NUM> are fed into the binary FEC encoder <NUM> to generate the sequence of coded bits <NUM>. Then, the sequence of coded bits <NUM> is fed into the bit mapper <NUM>, which outputs a plurality of output streams 240a, 240b, 240c. Each output binary stream 240a-c is mapped to a stream-specific modulator 250a-c, examples of which are described above with reference to <FIG>, generating complex-valued symbols of 260a, 260b, 260c per stream. The complex-valued symbols could be encoded by a non-binary FEC encoder as shown at <NUM> in <FIG>, and/or mapped to REs as shown at <NUM> in <FIG>.

The coded bit stream <NUM> includes coded bits b0b1b2, bit mapper <NUM> generates two streams 240a-b of size <NUM>, including a first stream with bits b0b1 and a second stream including bits b1b2, and the modulators 250a-b are QPSK modulators. In this example, b1 is present in both streams.

Referring to <FIG>, an example of a general framework for signal spreading and multi-user multiplexing shown in <FIG> will be described. <FIG> is a block diagram of an apparatus implementing a signal spreading technique according to another aspect of the disclosure. The apparatus in <FIG>, like the apparatus in <FIG>, includes a binary FEC encoder <NUM>, a bit mapper <NUM> coupled to the binary FEC encoder, and modulators 350a, 350b, 350c coupled to the bit mapper. The example implementations of components in <FIG> provided above also apply to the corresponding components in <FIG>. Operation of components as described above with reference to <FIG> also apply to the corresponding components in <FIG>.

The sequence <NUM> is shown to represent input binary bits to be transmitted to a receiver, such as a UE. Input bits <NUM> are fed into the FEC encoder <NUM> to generate the sequence of coded bits <NUM>. Then, the sequence of coded bits <NUM> is divided into a plurality of binary sequences 340a, 340b and 340c using a serial to parallel (S/P) converter <NUM>. Bit-level interleaving and/or scrambling, as shown at <NUM> in <FIG>, could be implemented in an interleaver/scrambler that is coupled between the FEC encoder <NUM> and the S/P converter <NUM>, or as a feature of the S/P converter <NUM> itself. The binary sequences 340a-c are mapped to complex-value symbols 360a, 360b and 360c using stream-specific modulators 350a, 350b and 350c, examples of which are described above with reference to <FIG>. Then, the sets of complex-value symbols 360a, 360b and 360c are fed into the symbol-level FEC encoder <NUM>, examples of which are also described above, to generate the output symbols <NUM> to be transmitted. The symbols <NUM> could be mapped to REs as shown at <NUM> in <FIG>.

<FIG> and <FIG> represent example implementations of the overall framework of <FIG>. Signal spreading could be provided by bit mapping at <NUM> such that the bit streams 240a-c have some common bits and some different bits, by the non-binary FEC encoder <NUM>, or both.

<FIG> are block diagrams of an apparatus implementing bit mapping and modulation techniques. The example implementations and operation of components in <FIG> provided above also apply to the corresponding components in <FIG>. Although <FIG> illustrate only a bit mapper and modulators coupled to the bit mapper, other components such as a binary FEC encoder, a bit-level interleaver/scrambler, a non-binary FEC encoder, and/or a symbol to RE mapper, for example.

In <FIG>, the bit mapper <NUM> maps input bits <NUM> to bit streams 440a-b such that bits b11 and b12 are common to both bit streams, and bits b01, b02, b21, and b22 are disjoint between the bit streams. The QPSK modulators 450a-b are stream-specific modulators in <FIG>. The bit mapper <NUM> provides signal spreading, and therefore there may or may not be a non-binary FEC encoder coupled to the QPSK modulators 450a-b.

In <FIG>, the bit mapper <NUM> maps input bits <NUM> to bit streams 540a and 540b such that bit b11 is common to both bit streams. The QPSK modulator 550a and <NUM>-QAM modulator 550b are the stream-specific modulators in this example. As shown, the bit streams 540a-b include segments b11b20 and b13b12b14b11 of different lengths, in ratios proportional to the modulation orders of the modulators 550a, 550b. Furthermore, the order of the bits can be changed by the bit mapper <NUM>, or by a separate interleaver/scrambler coupled to the bit mapper, for both streams. Again, the bit mapper <NUM> provides signal spreading, and therefore there may or may not be a non-binary FEC encoder coupled to the modulators 550a-b.

Referring to <FIG>, which is a block diagram of an apparatus implementing a sparse signal spreading technique according to another aspect of the disclosure, an example of sparse spreading will be described. The apparatus shown in <FIG> includes a FEC modulation and spreading module <NUM> and a sparse spreader <NUM>. The example implementations in <FIG> provided above also apply to the components in <FIG>. Other components such as a bit-level interleaver/scrambler, a non-binary FEC encoder, and/or a symbol to RE mapper.

In the context of <FIG> relates to an example in which the generated output symbols <NUM>, generated from input bits <NUM>, are fed into the sparse spreader <NUM>. Binary FEC encoding, modulation, and spreading (by bit mapping and/or non-binary FEC encoding) are performed by module <NUM>. The sparse spreader <NUM> maps the output symbols <NUM> to corresponding non-zero entries of a sparse spreading vector and generates the sparse output symbols <NUM>. Sparse symbol to RE mapping could also or instead be implemented in <FIG>. For example, a sparse symbol to RE mapper, instead of the sparse spreader <NUM>, could be coupled to the module <NUM> to implement sparse symbol to RE mapping.

In another example of a sparse signal spreading technique illustrated by way of an example apparatus in <FIG>, the sequences of complex-valued symbols at <NUM> are fed into non-binary FEC encoder <NUM> with possible "<NUM>" output to generate the sparse output symbols <NUM>. For completeness in <FIG>, the input bits <NUM>, binary FEC encoder <NUM>, coded bit stream <NUM>, bit mapper <NUM>, bit streams 740a-c, and modulators 750a-c are also shown. The example implementations and operation of components in <FIG> provided above also apply to the corresponding components in <FIG>.

Referring now to <FIG>, which is a block diagram of a signal spreading and multi-user signal multiplexing apparatus according to another aspect of the disclosure, an example of signal spreading and multiplexing of receivers, such as multiple UEs, will be discussed. The example implementations of components in <FIG> provided above also apply to the components of at least the transmit point <NUM> in <FIG>. Such implementations could also be applied to the UEs <NUM>, 870b. The antennas <NUM>, 860a, 860b could include one or more physical antenna elements of any of various types, together with appropriate transmit circuitry or modules at the transmit point <NUM> and at least appropriate receive circuitry or modules at the UEs 870a-b.

In the example transmit point <NUM>, the input bit streams 810a and 810b are first fed into the blocks 820a and 820b representing binary FEC, modulation, and spreading, by stream-specific bit mapping and/or non-binary FEC encoding, for example. Bit-level interleaving/scrambling, symbol-level interleaving/scrambling, and/or symbol to RE mapping could also be provided. Each stream of output symbols is fed into UE-specific (and/or user-specific) power scalers 830a-b, which apply power scaling vectors to scale the input symbols using a real-valued vector to generate the output power-scaled symbols. These power-scaled vectors are added together by adder <NUM> and generate a multiplexed symbol stream for transmission to UEs 870a-b through antennas <NUM> and 860a-b. The UEs 870a-b are examples of receivers.

Referring to <FIG>, which is a block diagram of a signal spreading and multi-user signal multiplexing apparatus according to another aspect of the disclosure, another example of signal spreading and multiplexing of receivers, such as multiple UEs, will be discussed. The example implementations and operation of components in <FIG> provided above also apply to the components shown in <FIG>.

The input bit streams 910a and 910b are first fed into the binary FEC encoders 920a and 920b. The streams of output coded bits at <NUM> are fed into bit multiplexer <NUM>, which performs bit multiplexing to generate a single stream of bits <NUM>. The bit multiplexer <NUM> may apply additional transformations or logical operations, such as bit-level interleaving/scrambling for example, but in an example applies only bit multiplexing. Bit-level interleaving/scrambling could also or instead be applied to the stream <NUM> by the bit mapper <NUM> or by a separate interleaver/scrambler, and/or to any or all of the coded bit streams <NUM> by one or more interleavers/scramblers.

The stream <NUM> is divided into a plurality of binary sequences 950a, 950b and 950c by the bit mapper <NUM>. Then, these binary sequences are mapped to complex-value symbols at <NUM>, by stream-specific modulators 960a, 960b and 960c. Then, the sets of complex-value symbols at <NUM> are fed into the non-binary FEC encoder <NUM> to generate the output symbols <NUM> to be transmitted, and those symbols could be mapped to REs, as shown at <NUM> in <FIG>.

Referring to <FIG>, which is a block diagram of a receiver apparatus according to another aspect of the disclosure, an example of a receiver to decode the data streams corresponding to a plurality of receivers such as UEs will be described. The example apparatus includes a joint maximum likelihood (ML) detector or receiver <NUM>, and binary FEC decoders 1030a, 1030b, 1030c coupled to the joint ML detector. The components in <FIG> could be implemented in circuitry that is configured to perform operations as disclosed herein, and examples are described above.

The received signal <NUM> is fed into the joint ML detector <NUM> to generate the output LLRs of coded bit streams 1020a, 1020b and 1020c corresponding to each data stream. Coded bit streams 1020a, 1020b and 1020c are then fed into the binary FEC decoders 1030a, 1030b and 1030c to generate the final decoded bit streams 1040a, 1040b and 1040c.

Referring to <FIG>, which is a block diagram of a receiver apparatus according to another aspect of the disclosure, an example of the receiver in <FIG> to decode the data streams corresponding to a plurality of receivers such as UEs with sparse spreading will be described. The detector or receiver <NUM> and the binary FEC decoders 1130a, 1130b, 1130c coupled thereto could be implemented as described above for the receiver/detector and decoders in <FIG>.

The received signal <NUM> is fed into the message passing algorithm (MPA) detector <NUM> to generate the output LLRs of coded bit streams 1120a, 1120b and 1120c corresponding to each data stream. Coded bit streams 1120a, 1120b and 1120c are then fed into the binary FEC decoders 1130a, 1130b and 1130c to generate the final decoded bit streams 1140a, 1140b and 1140c.

Referring to <FIG>, which is a block diagram of a receiver apparatus according to another aspect of the disclosure, an example of a receiver to decode the data streams corresponding to a plurality of receivers such as UEs will be described. The example apparatus includes a demodulator <NUM>, an iterative MPA detector <NUM> coupled to the demodulator, and binary FEC decoders 1250a, 1250b, 1250c coupled to the detector. The components in <FIG> could be implemented in circuitry that is configured to perform operations as disclosed herein, and examples are described above.

The received signal <NUM> is fed into the demodulator <NUM> to generate the output likelihood streams 1220a, 1220b and 1220c corresponding to each data stream. An example of the demodulator <NUM> includes a QAM demapper. The streams of likelihood values are fed into the iterative message passing detector <NUM> to take advantage of the redundant bits in the streams of symbols and potentially enhance the reliability of the LLRs of coded bit streams 1240a, 1240b and 1240c. The LLR streams 1240a, 1240b and 1240c are then fed into the binary FEC decoders 1250a, 1250b and 1250c to generate the final decoded bit streams 1260a, 1260b and 1260c.

Referring to <FIG>, which is a block diagram of a receiver apparatus according to another aspect of the disclosure an example of a receiver to decode the data streams corresponding to a plurality of receivers such as UEs will be described. The iterative MPA detector <NUM> and the binary FEC decoders 1350a, 1350b, 1350c coupled thereto could be implemented as described above for the detector and decoders in <FIG>. The example component implementation options provided above for other components could also be applied to the non-binary FEC decoder <NUM>.

The received signal <NUM> is fed into the non-binary FEC decoder <NUM> to generate the output likelihood streams 1320a, 1320b and 1320c corresponding to each data stream. An example of a non-binary FEC decoder is a Reed-Solomon decoder. The streams of likelihood values are fed into the iterative message passing detector <NUM> to take advantage of the redundant bits in the streams of symbols and potentially enhance the reliability of the LLRs of coded bit streams 1340a, 1340b and 1340c. The LLR streams 1340a, 1340b and 1340c are then fed into the FEC decoders 1350a, 1350b and 1350c to generate the final decoded bit streams 1360a, 1360b and 1360c.

Various examples are described above. <FIG> is a flow diagram of an embodiment of the present invention, and more generally illustrates aspects of the present disclosure.

The example method <NUM> includes applying binary FEC encoding to a stream of input bits at <NUM>, to generate a stream of coded bits. As also described elsewhere herein, the mapping could include interleaving and/or scrambling of the stream of coded bits. In other embodiments, either or both of interleaving and scrambling could be provided separately from the mapping, as shown at <NUM>. The example method <NUM> also includes mapping the stream of coded bits to a plurality of binary streams at <NUM>. In some embodiments, at least one coded bit is mapped to more than one of the binary streams and none of the binary streams are identical to each other. Stream-specific modulations are applied to the plurality of binary streams at <NUM>.

Applying stream-specific modulations at <NUM> involves generating a plurality of first streams comprising complex-valued signals. the method involves applying non-binary FEC encoding to the plurality of first complex-valued streams, at <NUM>, to generate a second complex-valued stream.

An operation of transmitting signals is shown at <NUM> as an illustrative example of further operations that could be performed after coding and modulation. Other variations of the example method <NUM> could include performing the illustrated operations in any of various ways, in a similar or different order than shown, and/or performing additional or fewer operations.

For example, the binary streams into which coded bits are mapped at <NUM> could, but might not necessarily be, disjoint. The mapping at <NUM> could involve dividing the stream of coded bits among the binary streams.

Applying binary FEC encoding at <NUM> involves applying binary FEC encoding to streams of input bits that are associated with multiple UEs, to generate streams of coded bits. The method further involves bit multiplexing the streams of coded bits into a bit multiplexed stream of coded bits, and mapping the bit multiplexed stream of coded bits into multiple streams at <NUM>. In comparative example, the streams of coded bits are mapped at <NUM>, and symbols that are generated from the binary streams by the stream-specific modulations at <NUM> (or a second complex-valued stream generated by optional non-binary FEC encoding at <NUM>) are multiplexed using stream-specific power scaling vectors.

The stream-specific modulations that are applied at <NUM> includes QAM mapping, for example with Gray or non-Gray labeling, and/or stream-specific modulations of different orders.

In a comparative example, the non-binary FEC encoding at <NUM> involves symbol-level spreading in which each of the first complex-valued streams is multiplied by a spreading sequence. Embodiments of the invention encompass non-binary FEC encoding that includes one or both of: symbol-level scrambling in which each of the first complex-valued streams is multiplied by a scrambling sequence, and symbol-level interleaving in which each of the first complex-valued streams is multiplied by an interleaving matrix.

Methods could also involve sparsely spreading the stream-specific modulated binary streams, or a second complex-valued stream from non-binary FEC encoding, using a sparse spreading vector. Such spreading involves spreading symbols that are generated from the binary streams by the stream-specific modulations, or FEC-encoded symbols if non-binary FEC encoding is applied.

Sparsely spreading the stream-specific modulated binary streams or a second complex-valued stream may involve using non-binary FEC encoding with at least one "<NUM>" output.

Example receiver/decoder-side operations are also shown by way of example in <FIG>. A signal that includes a data stream, or multiple data streams, to be decoded is received at <NUM>. Coded bit likelihood values, such as LLRs, are generated at <NUM>. This could involve using ML detection, or a message passing algorithm, for example. In another embodiment, generation of likelihood values at <NUM> involves demodulation, and calculating a stream of likelihood values by using iterative message passing. Another embodiment involves using non-binary FEC decoding and calculating a stream of coded bit LLRs by using iterative message passing. At <NUM>, the data stream, or each data stream in the case of multiple data streams, in a received signal is decoded using FEC decoding.

<FIG> is a block diagram of an example apparatus in which embodiments could be implemented. The apparatus <NUM> includes a modulator/encoder <NUM> coupled to an input <NUM>. The apparatus <NUM> also includes a transmitter <NUM> coupled to the parity modulator/encoder <NUM>. In the illustrated embodiment, the apparatus <NUM> also includes an antenna <NUM>, coupled to a transmitter <NUM>, for transmitting signals over a wireless channel. In some embodiments, the transmitter <NUM> includes components of an RF transmit chain. A memory <NUM> is also shown in <FIG>, coupled to the modulator/encoder <NUM> and to the transmitter <NUM>.

In an embodiment, the modulator/encoder <NUM> is implemented in circuitry, such as a processor, that is configured to implement features as disclosed herein. The modulator/encoder <NUM> could include components as shown in any of <FIG>, for example. In a processor-based implementation of the modulator/encoder <NUM>, processor-executable instructions to configure a processor to perform operations disclosed herein are stored in a non-transitory processor-readable medium. The non-transitory medium could include, in the memory <NUM> for example, one or more solid-state memory devices and/or memory devices with movable and possibly removable storage media.

An apparatus could therefore include a processor, and a memory such as <NUM> coupled to the processor, storing instructions which, when executed by the processor, cause the processor to perform a method as disclosed herein.

<FIG> generalizes an apparatus that includes a binary FEC encoder to encode a stream of input bits into a stream of coded bits; a bit mapper, coupled to the binary FEC encoder, to map the stream of coded bits to a plurality of binary streams; and a modulator, coupled to the bit mapper, to apply stream-specific modulations to the plurality of binary streams. These components represent one example implementation of the modulator/encoder <NUM>.

A bit mapper could be configured to interleave and/or scramble the stream of coded bits. In other embodiments, either or both of interleaving and scrambling could be implemented separately from a bit mapper, in a bit-level interleaver/scrambler as shown in <FIG> for example.

The bit mapper may be configured to map coded bits such that at least one coded bit is mapped to more than one of the binary streams and none of binary streams are identical to each other.

The modulator may be configured to generate a plurality of first streams comprising complex-valued signals. A non-binary FEC encoder could be coupled to the bit mapper, to encode the plurality of first complex-valued streams into a second complex-valued stream.

Any of the variations described above with reference to encoding, modulation, transmission, and/or related features in <FIG> could be applied in an apparatus implementation. For example, the binary streams into which coded bits are mapped by a bit mapper could, but might not necessarily be, disjoint. The bit mapper could be configured to divide the coded bits among the binary streams.

The binary FEC encoder is configured to apply binary FEC encoding to streams of input bits associated with multiple UEs to generate streams of coded bits. A bit multiplexer could be coupled to the binary FEC encoder, and configured to bit multiplex the streams of coded bits into a bit multiplexed stream of coded bits, with the mapper being configured to map the bit multiplexed stream of coded bits. In embodiment comparative example, a power scaler is operatively coupled to the modulator, or to the non-binary FEC encoder if non-binary FEC encoding is implemented, to multiplex the stream-specific modulated binary streams or the second complex-valued stream using stream-specific power scaling vectors.

The modulator includes a plurality of stream-specific QAM mappers, to apply QAM mapping, with Gray or non-Gray labeling, and/or a plurality of stream-specific modulators, which could be of different orders.

A non-binary FEC encoder is configured to implement one or both of: symbol-level scrambling in which each of the first complex-valued streams is multiplied by a scrambling sequence, and symbol-level interleaving in which each of the first complex-valued streams is multiplied by an interleaving matrix.

A sparse spreader could be coupled to the modulator to spread the stream-specific modulated binary streams, or a second complex-valued stream from non-binary FEC encoding, using a sparse spreading vector. Such spreading involves spreading symbols that are generated from the binary streams by the stream-specific modulations, or FEC-encoded symbols if non-binary FEC encoding is applied.

A non-binary FEC encoder coupled to the modulator, or a further non-binary FEC encoder coupled to another non-binary FEC encoder, could be configured to spread the stream-specific modulated binary streams, or the second complex-valued stream, using non-binary FEC encoding with at least one "<NUM>" output.

<FIG> is a block diagram of another example apparatus in which embodiments could be implemented. The apparatus <NUM> includes a receiver <NUM> coupled to an antenna <NUM> for receiving signals from a wireless channel, and to a demodulator/decoder <NUM>. A memory <NUM> is also shown in <FIG>, coupled to receiver <NUM> and to the demodulator/decoder <NUM>.

The receiver <NUM> includes components of an RF receive chain. The receiver <NUM> receives, via the antenna <NUM>, signals that include data streams that are to be decoded. The demodulator/decoder <NUM> is configured to implement receiver decoder-side features as disclosed herein. Decoded bits are output at <NUM> for further receiver processing.

The apparatus <NUM>, and similarly the apparatus <NUM> in <FIG> as noted above, include a non-transitory computer readable medium at <NUM>, <NUM> that includes instructions for execution by a processor to implement and/or control operation of the modulator/encoder <NUM> in <FIG>, to implement and/or control operation of the and the demodulator/decoder <NUM> in <FIG>, and/or to otherwise control the execution of methods described herein. The processor may be a component of a general-purpose computer hardware platform. Or, the processor may be a component of a special-purpose hardware platform. For example, the processor may be an embedded processor, and the instructions may be provided as firmware. The instructions for execution by a processor may be embodied in the form of a software product. The software product may be stored in a non-volatile or non-transitory storage medium, which could be, for example, a compact disc read-only memory (CD-ROM), universal serial bus (USB) flash disk, or a removable hard disk, at <NUM>, <NUM>.

The demodulator/decoder <NUM> is implemented in circuitry that is configured to implement features as disclosed herein. The demodulator/decoder <NUM> could include components as shown in any of <FIG>, for example. The receiver <NUM> and/or the demodulator/decoder <NUM> could be fully or partially implemented in software or modules stored in the memory <NUM> and executed by a processor(s) of the apparatus <NUM>.

An apparatus could therefore include a processor, and a memory such as <NUM> coupled to the processor, storing instructions which, when executed by the processor, cause the processor to perform a method as disclosed herein, or receiving / decoding operations corresponding to transmitting / encoding operations disclosed herein.

<FIG> generalizes an apparatus that includes a receiver to receive a signal comprising a data stream, or multiple data streams, to be decoded; a signal detector, coupled to the receiver, to generate coded bit likelihood values such as LLRs; and a FEC decoder, coupled to the signal detector, to decode the data stream, or each data stream, in a received signal. The signal detector could be configured to generate coded bit likelihood values using one of: ML detection, a message passing algorithm, a combination of demodulation and iterative message passing, and a combination of non-binary forward error correcting (FEC) decoding and iterative message passing, for example.

Communication equipment could include the apparatus <NUM>, the apparatus <NUM>, or both a transmitter and a receiver and both a modulator/encoder and a demodulator/decoder as described above. Such communication equipment could be user equipment or communication network equipment.

<FIG> are generalized block diagrams of apparatus that could be used to implement embodiments disclosed herein. <FIG> is a block diagram of an example processing system which provides a higher level implementation example and which may be used to implement embodiments disclosed herein.

The apparatus <NUM>, the apparatus <NUM>, or both, may be implemented using the example processing system <NUM>, or variations of the processing system <NUM>. The processing system <NUM> could be a radio access node or a wireless device, for example, or any suitable processing system. Other processing systems suitable for implementing embodiments described in the present disclosure may be used, which may include components different from those discussed below. Although <FIG> shows a single instance of each component, there may be multiple instances of each component in the processing system <NUM>.

The processing system <NUM> may include one or more processing devices <NUM>, such as a processor, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a dedicated logic circuitry, or combinations thereof. The processing system <NUM> may also include one or more input/output (I/O) interfaces <NUM>, which may enable interfacing with one or more appropriate input devices <NUM> and/or output devices <NUM>. The processing system <NUM> may include one or more network interfaces <NUM> for wired or wireless communication with a network (e.g., an intranet, the Internet, a P2P network, a WAN and/or a LAN) or other node. The network interfaces <NUM> may include wired links (e.g., Ethernet cable) and/or wireless links (e.g., one or more antennas) for intra-network and/or inter-network communications. The network interfaces <NUM> may provide wireless communication via one or more transmitters or transmit antennas and one or more receivers or receive antennas, for example. In this example, a single antenna <NUM> is shown, which may serve as both transmitter and receiver. However, in other examples there may be separate antennas for transmitting and receiving. The processing system <NUM> may also include one or more storage units <NUM>, which may include a mass storage unit such as a solid state drive, a hard disk drive, a magnetic disk drive and/or an optical disk drive.

The processing system <NUM> may include one or more memories <NUM>, which may include a volatile or non-volatile memory (e.g., a flash memory, a random access memory (RAM), and/or a read-only memory (ROM)). The non-transitory memories <NUM> may store instructions for execution by the processing devices <NUM>, such as to carry out examples described in the present disclosure. The memories <NUM> may include other software instructions, such as for implementing an operating system and other applications/functions. In some examples, one or more data sets and/or modules may be provided by an external memory (e.g., an external drive in wired or wireless communication with the processing system <NUM>) or may be provided by a transitory or non-transitory computer-readable medium. Examples of non-transitory computer readable media include a RAM, a ROM, an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a CD-ROM, or other portable memory storage.

There may be a bus <NUM> providing communication among components of the processing system <NUM>. The bus <NUM> may be any suitable bus architecture including, for example, a memory bus, a peripheral bus or a video bus. In <FIG>, the input devices <NUM> (e.g., a keyboard, a mouse, a microphone, a touchscreen, and/or a keypad) and output devices <NUM> (e.g., a display, a speaker and/or a printer) are shown as external to the processing system <NUM>. In other examples, one or more of the input devices <NUM> and/or the output devices <NUM> may be included as a component of the processing system <NUM>.

<FIG> is a block diagram of an example communication system in which embodiments of the present disclosure could be implemented. The example communication system <NUM> in <FIG> includes a Core Network (CN) <NUM> and an access network (e.g. Radio Access Network (RAN)) <NUM>. The access network <NUM> includes network equipment <NUM>, <NUM>, <NUM> that implements the access methods described above to provide UEs <NUM>, <NUM> with access to networks and/or services available via the core network <NUM>. The UEs <NUM>, <NUM> are configured to transmit and/or receive data to and/or from the network equipment <NUM> via wireless communication links <NUM>, <NUM>. Each user equipment <NUM>, <NUM> represents any suitable end user device and may include (or be referred to as) an Electronic Device (ED), wireless device, Wireless Transmit/Receive Unit (WTRU), Machine Type Communication (MTC) device, station (STA), mobile station, fixed or mobile subscriber unit, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, or other consumer electronics device.

In the communication system <NUM>, the access network <NUM> communicates with the core network <NUM> over another network communication link <NUM>. The core network <NUM>, like the access network <NUM>, may include network equipment that communicates with one or more installations of the network equipment <NUM>, <NUM>, <NUM> in the access network <NUM>. However, in a communication system with an access network <NUM> and a core network <NUM>, the core network might not itself directly provide communication service to user equipment.

The communication system <NUM> is intended solely as an illustrative example. An access network <NUM> could include more or fewer than three installations of network equipment, for example, which might or might not all directly communicate with each other as shown. Also, more than one installation of network equipment in the access network <NUM> could provide communication service to user equipment. There could be more than one access network <NUM> coupled to a core network <NUM>. It should also be appreciated that the present disclosure is not in any way limited to communication systems having an access network / core network structure.

Considering the access network <NUM>, any of various implementations are possible. The exact structure of network equipment <NUM>, <NUM>, <NUM>, and user equipment <NUM>, <NUM> for which such network equipment provides communication service, is implementation-dependent. The apparatus <NUM>, <NUM>, <NUM> in <FIG> are examples of communication equipment that could be implemented at user equipment <NUM>, <NUM> and/or network equipment <NUM>, <NUM>, <NUM>.

At least the network equipment <NUM> that provides communication service to the user equipment <NUM>, <NUM> includes a physical interface and communications circuitry to support communications with the user equipment over the links <NUM>, <NUM>. The physical interface could be in the form of an antenna or an antenna array, for example, where the access communication links <NUM>, <NUM> are wireless links. Multiple interfaces could be provided at the network equipment <NUM> to support multiple access communication links <NUM>, <NUM> of the same type or different types, for instance. The type of communications circuitry coupled to the physical interface or interfaces at the access network equipment <NUM> is dependent upon the type or types of access communication links <NUM>, <NUM> and the communication protocol or protocols used to communicate with the user equipment <NUM>, <NUM>.

The network equipment <NUM>, <NUM>, <NUM> also includes a physical interface, or possibly multiple physical interfaces, and communications circuitry to enable communications with other network equipment in the access network <NUM>. At least some installations of network equipment <NUM>, <NUM>, <NUM> also include one or more physical interfaces and communications circuitry to enable communications with core network equipment over the communication link <NUM>. There could be multiple communication links between network equipment <NUM>, <NUM>, <NUM> and the core network <NUM>. Communication links <NUM>, <NUM>, <NUM> in the access network <NUM>, and the communication link <NUM> to the core network <NUM>, could be the same type of communication link. In this case the same type of physical interface and the same communications circuitry at the network equipment <NUM>, <NUM>, <NUM> could support communications between access network equipment within the access network <NUM> and between the access network <NUM> and the core network <NUM>. Different physical interfaces and communications circuitry could instead be provided at the network equipment <NUM>, <NUM>, <NUM> for communications within the access network <NUM> and between the access network <NUM> and the core network <NUM>.

In the communication system <NUM>, the network equipment <NUM> (and network equipment <NUM>, <NUM> if used for network access) is configured to wirelessly communicate with one or more user equipment <NUM>, <NUM>, to enable access to the core network <NUM> and/or other networks or services available via the core network <NUM>. The network equipment <NUM> (and possibly <NUM>, <NUM>) may include (or be) one or more of several well-known devices, such as a base station, a base transceiver station (BTS), a radio access node, a Node-B (NodeB or NB), an evolved NodeB (eNodeB), a gNodeB (sometimes called a "gigabit" NodeB), a Home NodeB (e.g. a Home eNB / gNB), a Transmission Point (TP), a site controller, an access point (AP), or a wireless router. The network equipment <NUM> operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a "cell. " Multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell. The term network equipment may also refer to modules on the network side configured to perform certain processing operations and which are not necessarily part of the equipment housing the network equipment transceiver. Or, the network equipment <NUM> (and possibly <NUM>, <NUM>) may actually be a plurality of base stations or TPs that are operating together to serve the user equipment <NUM>, <NUM>, e.g. with multi-point transmissions.

Network equipment in the core network <NUM> could be similar in structure to the network equipment <NUM>, <NUM>, <NUM>. However, as noted above, network equipment in the core network <NUM> might not directly provide communication service to user equipment and therefore might not include physical interfaces for access communication links or associated communications circuitry. Physical interfaces and communications circuitry at network equipment in the core network <NUM> could support the same type or types of network communication link or links as in the access network <NUM>, different type or types of network communication link or links, or both.

Just as the exact structure of physical interfaces at network equipment <NUM>, <NUM>, <NUM> and network equipment in the core network <NUM> is implementation-dependent, the associated communications circuitry is implementation-dependent as well. In general, hardware, firmware, components which execute software, or some combination thereof, might be used in implementing such communications circuitry. Examples of electronic devices that might be suitable for implementing communications circuitry are provided above.

Each installation of user equipment <NUM>, <NUM> includes a physical interface and communications circuitry compatible with a physical interface and communications circuitry at the network equipment <NUM>, to enable the user equipment to communicate with the network equipment. Multiple physical interfaces of the same or different types could be provided at the user equipment <NUM>, <NUM>. The user equipment <NUM>, <NUM> could also include such components as input/output devices through which functions of the user equipment are made available to a user. In the case of a wireless communication device such as a smartphone, for example, these functions could include not only communication functions, but other local functions which need not involve communications. Different types of user equipment <NUM>, <NUM>, such as different smartphones for instance, could be serviced by the same network equipment <NUM>.

Claim 1:
A method comprising:
applying binary forward error correcting, FEC, encoding (<NUM>) to a stream of input binary bits to generate a stream of coded bits;
mapping (<NUM>) the stream of coded bits to a plurality of binary streams; and
applying stream-specific modulations (<NUM>) to the plurality of binary streams (<NUM>), the stream-specific modulations comprising QAM mapping and/or stream-specific modulations of different orders to generate a plurality of first complex-valued streams,
characterized in that the method further comprises applying non-binary FEC encoding (<NUM>) to the generated plurality of first complex-valued streams to generate a second complex-valued stream, wherein applying non-binary FEC encoding comprises one or both of: symbol-level scrambling and symbol-level interleaving, wherein in symbol-level scrambling each of the plurality of first complex-valued streams is multiplied by a scrambling sequence, and wherein in symbol-level interleaving each of the plurality of first complex-valued streams is multiplied by an interleaving matrix;
wherein applying binary FEC encoding comprises applying binary FEC encoding to streams of input bits associated with multiple UEs to generate streams of coded bits,
wherein the method further comprises bit multiplexing the streams of coded bits into a bit multiplexed stream of coded bits,
wherein mapping comprises mapping the bit multiplexed stream of coded bits.