Patent Description:
Switched-mode power supply (SMPS) converters are widely used in various electronic applications ranging from telecommunication equipment to automobiles. The SMPS system offers advantageous power conversion efficiency and increased design flexibility over linear regulators.

One challenge of SMPS design is managing power loss due to switching losses. One way to reduce such switching losses is to use gallium nitride GaN power devices instead of silicon-based transistors to implement switching transistors. The low parasitic capacitance and lower on-resistance of GaN power devices reduce switching losses compared to traditional silicon-based transistors. As such GaN power devices are increasingly being used to implement compact power chargers for portable electronic devices.

<CIT> discloses a power converter that includes a first transistor and a second transistor that each have a drain node connected to a primary winding of a transformer. A gate node of the first transistor is connected to a control circuit, and a gate node of the second transistor is connected to a source node of the first transistor. The second transistor is a normally-on transistor. A source node of the second transistor is connected to a start-up circuit. The start-up circuit is connected to a supply node of the control circuit and to a capacitor configured to supply the control circuit.

<CIT> discloses a switching converter that includes a switch connected to a power supply portion; a transformer connected to the power supply portion; a first rectifying and smoothing circuit and a second rectifying and smoothing circuit each connected to at least the transformer; and a switching control circuit which is connected to the first rectifying and smoothing circuit and the second rectifying and smoothing circuit and which controls operation of the switch. The switching control circuit includes a control circuit configured to control the switch and operation of a starter circuit; and the starter circuit is configured to control a start-up of the control circuit. The starter circuit includes a transistor and a resistor each including a wide-gap semiconductor.

<CIT> discloses a semiconductor device that includes a III-nitride channel region and a silicon carbide drift region.

<NPL>, in <FIG>, discloses a GaN based gate injection transistor (GIT).

One embodiment of the invention relates to a method of starting a circuit according to claim <NUM>. Further embodiments relate to a circuit according to claim <NUM> and a switched-mode power supply according to claim <NUM>.

For a more complete understanding of the invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:.

To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferred embodiments in a specific context, a system and method of starting-up a switched mode power supply using a GaN-based startup circuit. The invention may also be applied to the startup of other electronic circuits and systems.

In various embodiments, a GaN-based startup circuit is used to provide the initial startup power for an electronic system, such as a switched-mode power supply that is configured to convert a higher AC line voltage to a lower DC voltage that is usable, for example, by portable electronic systems such as smartphone, cellular telephones and tablet computers, and other electronic systems that require a DC voltage for operation. Such switched-mode power supplies generally include control and switching circuitry that also operate using a DC power supply voltage. During normal operation of the switched-mode power supply, this DC power supply voltage is often provided to the control and switching circuit by the switched-mode power supply itself. The challenge becomes how to provide a DC power supply voltage to the control and switching circuits at the initial startup of the switched-mode power supply and prior to the time that the switched-mode power supply is ready to provide power to the control and switching circuit.

In various embodiments of the present invention, this initial DC power supply voltage is provided by the AC line input to the control and switching circuit via a start-up circuit that includes a normally-on GaN transistor having a load path coupled to a capacitor and a gate coupled to a ground or reference node. During operation, the capacitor is charged by the normally-on GaN transistor while the gate-source voltage of the normally-on GaN transistor decreases. During this time, power is supplied to the control and switching circuit from the charged capacitor, which allows the control and switching circuit to start-up the switched-mode power supply. Once the switched-mode power supply has started, power is supplied to the control and switching circuit from the switched-mode power supply.

The normally-on GaN transistor is, according to the invention, integrated on the same semiconductor substrate as a normally-off GaN transistor used to implement a switch of the switched-mode power supply. In such embodiments, the drains of the normally-on GaN transistor may be connected together with the drain of the normally-off GaN transistor. Thus, in switched-mode flyback converters in which the switch of the switched-mode power supply is coupled to the AC line input via the primary winding of the transformer, the same AC line input (or rectified AC line input) can be made available to the normally-on GaN transistor for the purpose of starting up the switched-mode power supply. According to the invention, the normally-off GaN transistor is implemented using a fully recessed pGaN gate with a second barrier region, while the normally-on transistor is implemented using similar processes without recessing the pGaN gate, thereby allowing for the implementation of both normally-on and normally-off GaN transistors using the same process flow. One advantage of such an embodiment is the ability to start-up the operation of a switched-mode power supply with no standby current or very little standby current. A further advantage is the ability to implement a start-up circuit in a cost efficient manner. The start-up circuit may implemented on the same substrate as the switching transistor using a semiconductor process in which both normally-on and normally-off GaN transistors can be implemented using the same process flow.

<FIG> illustrates a start-up circuit <NUM> according to an embodiment of the present invention. As shown, start-up circuit <NUM> includes normally-off switch transistor M1, normally-on start-up transistor M2, capacitor C and diode D1. In various embodiments normally-off switch transistor M1 and normally-on start-up transistor M2 are implemented as GaN HEMT transistors disposed on a single semiconductor substrate and/or package <NUM>. In alternative embodiments, however, normally-off switch transistor M1 and normally-on start-up transistor M2 may be implemented separately and/or may be implemented in other technologies besides GaN. For example, normally-off switch transistor M1 and normally-on start-up transistor M2 may be implemented as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Field-Effect Transistors) or BJTs (Bipolar Junction Transistors) implemented using a silicon process technology or other process technologies known in the art.

Normally-off switch transistor M1 has a gate terminal coupled to node VG, a source terminal coupled to ground node GND (also referred to as a reference terminal), and a drain terminal coupled to node VD. Thus, during operation of the switched mode power supply, the gate of normally-off switch transistor M1 can be driven with a gate drive signal, such as a pulse width modulated signal at node VG while the source is grounded and the drain is coupled to a higher voltage at node VD. Normally-on startup transistor M2 has its gate coupled to ground node GND, its drain coupled to node VD, and its source coupled to power supply node VDD. Capacitor C is coupled between power supply node VDD and ground node GND. Power supply node VDD is coupled to power source node VDDIN via optional diode D1. Power source node VDDIN represents a power supply voltage that becomes available after the system to which start-up circuit <NUM> is coupled becomes operational. In alternative embodiments, power supply node VDD may be interfaced to power source node VDDIN using other circuits and/or circuit elements known in the art instead of diode D1, such as switches and/or switching transistors.

In one embodiment, normally-off switch transistor M1 has a threshold of between about +1V and +<NUM>. 5V and normally-on startup transistor M2 has a threshold between about -4V and about -6V. In alternative embodiments of the present invention, other thresholds may be used depending on the particular embodiment and its specifications.

During operation, when the circuit first starts-up, a positive voltage, also referred to as a start-up voltage, is applied to node VD. Because the voltage across capacitor C and the gate-source voltage of normally-on startup transistor M2 is zero, drain current IDM2 flows through the load path (e.g., from the drain to the source) of normally-on startup transistor M2 and charges capacitor C. As the voltage across capacitor C increases, gate-source voltage VGSM2 of normally-on startup transistor M2 decreases, which causes a corresponding decrease in drain current IDM2 of normally-on startup transistor M2. The relationship between drain current IDM2 (also known as the load path current) of normally-on startup transistor M2 is illustrated in <FIG>. As shown, when the gate-source voltage VGSM2 of normally-on startup transistor M2 is zero, drain current IDM2 has a value of IDstart. However, as the applied voltage across the gate-source voltage VGSM2 of normally-on startup transistor M2 decreases to the threshold of -4V, drain current IDM2 approaches zero.

<FIG> illustrates a waveform diagram that shows how the voltages of drain node VD, power supply node VDD and power source node VDDIN change over time when start-up circuit <NUM> begins operation. As shown, at time to, a voltage is applied to drain node VD. This applied voltage at node VD may represent, for example, an AC line voltage or rectified AC line voltage being applied to node VD via a primary winding of a transformer. In some switched-mode power supply embodiments, the voltage applied to node VD may be pulsed after the initial start-up as is illustrated in <FIG> and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -VT_M2, which has a magnitude of the threshold voltage of normally-on startup transistor M2. For example, if the threshold of normally-on startup transistor M2 is -4V, then -VT_M2 is 4V. At time t1, the voltage of power source node VDDIN increases and further charges capacitor C via diode D1 such that the voltage of power supply node VDD is one diode drop Vdf below the voltage of power source node VDDIN. It should be appreciated that the waveform diagram of <FIG> is just one of many examples of the transient behavior of embodiment start-up circuits.

In some cases, embodiment start-up circuit <NUM> can be modified to produce higher start-up voltages by using a plurality of normally-on start-up transistors as illustrated with respect to start-up circuit <NUM> shown in <FIG>, which includes normally-off switch transistor M1, two normally-on start-up transistors M2A and M2B, capacitors CA and CB, and diodes D1, D2 and D3. As shown, normally-on start-up transistors M2A and M2B are coupled in series between drain node VD and ground node GND, with capacitors CA and CB coupled respectively between the gate and drain terminals of normally-on start-up transistors M2A and M2B. Diode D1 is coupled between nodes VDDIN and VDD, zener diode D2 is coupled between node VDD and GND, and diode D3 is coupled between the drain and source of normally-on start-up transistor M2B. The drain, gate and source of normally-off switch transistor M1 are coupled respectively to nodes VD, VG and GND in a similar manner as the start-up circuit <NUM> shown in <FIG>. Normally-off switch transistor M1, normally-on start-up transistors M2A and M2B and diode D3 may be implemented on a single semiconductor substrate and/or package <NUM>. However, in alternative embodiments, the various components shown in <FIG> may be partitioned differently. Normally-off switch transistor M1 and normally-on start-up transistors M2A and M2B may be implemented as GaN transistors or as other transistor types as described above.

At start-up, when a voltage is applied to node VD, normally-on start-up transistors M2A and M2B charge capacitors CA and CB such that voltage across the series combination of capacitors CA and CB is about -VT_M2A - VT_M2B, which has a magnitude of the sum of the threshold voltages of normally-on startup transistors M2A and M2B. Thus, the start-up circuit <NUM> of <FIG> is capable of delivering twice the start-up voltage of the start-up circuit <NUM> shown in <FIG>. In alternative embodiments, additional normally-on start-up transistors can be coupled in series with normally-on start-up transistors M2A and M2B and additional corresponding capacitors can be coupled in series with capacitors CA and CB in order to further increase the start-up voltage of start-up circuit <NUM>. For example, if three normally-on start-up transistors are coupled in series, the resulting startup-voltage between power supply node VDD and ground node GND would be three times the start-up voltage of start-up circuit <NUM> shown in <FIG>.

In some embodiments, optional zener diode D2 may be used to limit and/or regulate the start-up voltage generated by start-up circuit <NUM>. Diode D3 coupled between the source and drain of normally-on start-up transistor is included to create a discharge path for capacitor CB, and to ensure a discharge path exists between ground node GND and node VD.

<FIG> illustrates a schematic of a gate drive system <NUM> that shows how the embodiment start-up circuit can be interfaced with gate drive circuits. As shown, driver circuit <NUM> drives the gates of pre-driver transistors M3 and M4 based on the state of pulse-width modulated signal PWM. Pre-driver transistors M3 and M4, in turn, drive the gate of normally-off switch transistor M1. For example, when the PWM signal is in a first state, pre-driver transistor M3 is turned-on and pre-driver transistor M4 is turned-off. As a result, the voltage at power supply node VDD is applied to the gate of normally-off switch transistor M1, which turns-on normally-off switch transistor M1. On the other hand, when the PWM signal is in a second state, pre-driver transistor M3 is turned-off and pre-driver transistor M4 is turned-on. As a result, the voltage at ground node GND is applied to the gate of normally-off switch transistor M1, which turns-off normally-off switch transistor M1. In one embodiment, the PWM signal is a digital signal such that the first state of the PWM signal is a "high" state and the second state is a "low" state. In alternative embodiments, the PWM signal may be configured to be a digital active low signal such that the first state of the PWM signal is a "low" state and the second state is a "high" state. Driver circuit <NUM> may include, for example, digital circuitry known in the art that creates appropriate gate drive signals for pre-driver transistors M3 and M4 based on the state of the PWM signal.

In various embodiments, a gate interface network including resistors R1, R2 and RG and capacitor CG interfaces pre-driver transistors M3 and M4 to the gate of normally-off switch transistor M1. The RC network formed by resistors R1, R2 and RG and capacitor CG may be used to provide a negative turn-off voltage at the gate of transistor M1. This is particularly useful in when transistor M1 is implemented as a GaN HEMT having a relatively low threshold voltage. By using the illustrated RC network both a positive and negative gate voltage can be generated using a positive single supply voltage. It should be understood that the illustrated gate interface network is just one example of many possible gate interface network topologies. In alternative embodiments, other circuit topologies may be used depending on the particular system and its specifications.

During operation, start-up circuit <NUM> generates a start-up voltage at power supply node VDD that provides power to a power supply input of driver circuit <NUM> and pre-driver transistor M3 via normally-on start-up transistor M2 as described above. Thus, during start-up, energy from capacitor C is provided to driver circuit <NUM>. Once the voltage of capacitor C reaches a threshold defined by the threshold voltage of normally-on start-up transistor M2, normally-on start-up transistor is turned-off. In some embodiments, when start-up circuit <NUM> initially turns-on, pre-driver transistor M4 is turned-on. When pre-driver transistor M4 is turned-on, the gate of normally-off switch transistor M1 is grounded, thereby shutting-off normally-off switch transistor M1. Shutting-off switch transistor M1 ensures that node VD is not shorted to ground via normally-off switch transistor M1, which would prevent capacitor C from being charged via normally-on start-up transistor M2. In some embodiments, a pulldown resistor (not-shown) may be coupled between node VG and ground node GND to ensure that normally off switch transistor M1 is initially turned-off at the beginning of a start-up sequence.

Once the system has started-up, power is provided to driver circuit <NUM> and pre-driver transistor M3 from power source node VDDIN via diode D1. In alternative embodiments, start-up circuit <NUM> shown in <FIG> may be replaced by other embodiment start-up circuits, such as start-up circuit <NUM> described above with respect to <FIG> in order to provide a higher start-up voltage at power supply node VDD.

<FIG> illustrates a switched-mode power converter <NUM> that incorporates an embodiment start-up circuit <NUM>. In various embodiments switched-mode power converter <NUM> is configured to convert an AC input voltage VAC produced by power source <NUM> to a DC output voltage VOUT that supplies load <NUM>. Power source <NUM> may represent, for example, an AC power line. Load <NUM> may represent, for any type of circuitry that accepts a DC voltage, such as computer circuit, charging circuitry, and other types of circuitry. For example, switched-mode power converter <NUM> may convert an AC line input voltage about <NUM> Vrms or <NUM> Vrms to about <NUM> Vdc.

As shown, switched mode power converter includes a rectifier <NUM> coupled to power source <NUM> and to input capacitor CIN. Rectifier <NUM> is configured to provide full-wave or half-wave rectification of input voltage VAC. In some embodiments, rectifier <NUM> is implemented using a diode bridge or other rectifier circuit known in the art. The output of rectifier <NUM> is coupled to primary winding <NUM> of transformer <NUM>. In the depicted embodiment, switched-mode power converter <NUM> is operated as a flyback converter. During operation, controller <NUM> turns normally-off switch transistor M1 on and off, which has the effect of magnetizing the primary winding <NUM> of transformer <NUM>. A portion of the energy stored in primary winding <NUM> is transferred to secondary winding <NUM> of transformer <NUM>, thereby inducing a current in the secondary winding. This induced current is rectified by diode DS, filtered by capacitor CL and provided to load <NUM>. In some embodiments, diode DS may be replaced by a synchronous rectifier.

Another portion of the energy stored in primary winding <NUM> is transferred to auxiliary winding <NUM> in order to provide power to start-up circuit <NUM> and controller <NUM>. During operation, current induced in auxiliary winding <NUM> is rectified by diode D1 and filtered by capacitor C in start-up circuit <NUM>. Operation of start-up circuit <NUM> proceeds as described with respect to the embodiment of <FIG> as described above. In an embodiment, the voltage at node VD of start-up circuit <NUM> during start-up behaves in accordance with the voltage waveform shown in <FIG> above in which voltage VD is pulsed once VDD has attained a sufficient voltage level to enable controller <NUM> to provide a switching signal to the gate of normally-off switch transistor M1. It is this switching signal that allows energy to be transferred from the primary winding <NUM> to the auxiliary winding <NUM> of transformer <NUM>, which ultimately completes the start-up process of switched-mode power converter <NUM>.

Feedback circuit <NUM> may be configured to measure DC output voltage VOUT at the secondary side of switched-mode power converter <NUM> and provide a feedback signal FB that is proportional to the measured DC output voltage VOUT. In some embodiments, feedback circuit provides galvanic isolation between the primary and secondary sides of switched-mode power converter <NUM>. Feedback circuit <NUM> may be implemented, for example, using an optoisolator circuits and/or other feedback circuits suitable for use in switched-mode power converters known in the art.

In various embodiments, controller <NUM> is configured to generate a pulse-width modulated signal at node GD based on feedback signal FB and current sense signal CS. During normal operation, controller <NUM> adjusts the pulse-width of the pulse-width modulated signal in order to regulate DC output voltage VOUT. For example, when feedback signal FB indicates that the DC output voltage VOUT is below a target voltage, controller <NUM> increases the pulse-width of the pulse-width modulated signal at node GD, which has the effect of increasing the current produced by secondary winding <NUM>, increasing the current available to load <NUM> and increasing DC output voltage VOUT. On the other hand, when feedback signal FB indicates that the DC output voltage VOUT is above the target voltage, controller <NUM> decreases the pulse-width of the pulse-width modulated signal at node GD, which has the effect of decreasing the current produced by secondary winding <NUM>, decreasing the current available to load <NUM> and decreasing DC output voltage VOUT.

Current flowing through normally-off switch transistor M1 is determined by controller <NUM> by measuring the voltage across current sense resistor RS coupled in series with normally-off switch transistor M1. The measured current through RS may be used, for example, to help control the timing of the pulse-width modulated signal at node GD and/or to regulate peak or average currents within switched-mode power converter <NUM> in accordance with switched-mode power supply conversion systems and methods known in the art. In various embodiments, controller <NUM> may include gate driving circuitry suitable for driving the gate of normally-off switch transistor M1, for example, driver circuit <NUM>, pre-driver transistors M3 and M4, and resistors R1 and R2 shown and described above with respect to <FIG>. Other known gate driving circuits known in the art may also be used.

It should be understood that the operation and implementation of controller <NUM> described herein is just one of many example controllers that could be used to implement an embodiment switched-mode power converter. In alternative embodiments, other switched-mode power supply controller systems and methods known in the art may also be used.

During start-up and normal operation, power is provided to controller via node VDD. For example, as switched-mode power converter <NUM> initially starts-up, power is supplied to controller <NUM> via normally-on start-up transistor M2 in start-up circuit <NUM>; and during normal operation, power is suppled to controller <NUM> via auxiliary winding <NUM> as explained above. In alternative embodiments, other embodiment start-up circuits, such as start-up circuit <NUM> described with respect to <FIG>, may be used besides start-up circuit <NUM> described with respect to <FIG> above.

It should be understood that while <FIG> illustrates a switched-mode power converter configured as a flyback converter, other switch-mode power converter circuits (and non-switched-mode power converter circuits) may be used in conjunction with embodiment start-up circuits and methods. For example, in alternative embodiments of the invention, power supply topologies such as active clamp using complementary or non-complimentary control, hybrid flyback or other half bridge-based topologies may be used in along with embodiment start-up circuits. One such example of a half-bridge based topology is illustrated in <FIG>, which shows a switched-mode power converter <NUM> that incorporates an embodiment start-up circuit <NUM>. Similar to switched-mode power converter <NUM> depicted in <FIG>, embodiment startup circuit <NUM> is coupled to auxiliary winding <NUM> in order to provide power to controller <NUM> during startup and during normal operation as described above.

As shown, switched-mode power converter <NUM> includes a half-bridge circuit having a high-side transistor MH having a source coupled to the drain of normally-off switch transistor M1 and a first end of primary winding <NUM> of transformer <NUM>, while the second end of primary winding <NUM> is coupled to ground via resonant capacitor Cr. In various embodiments, high-side transistor MH may be implemented using a normally-off GaN transistor fabricated in a similar manner as normally-off switch transistor M1, or may be implemented using other transistor types as described above.

During operation controller <NUM> turns on and off high-side transistor MH and normally-off switch transistor M1 in an alternating manner. The gates of these transistors may be driven, for example by boosted gate driver <NUM> and driver <NUM> shown in controller <NUM> according to frequency modulated switching signal VSW. In alternative embodiments, boosted gate driver <NUM> and driver <NUM> may be implemented externally to controller <NUM>. When high-side transistor MH is on and normally-off switch transistor M1 is off, the first end of primary winding <NUM> is connected to the output of rectifier <NUM> via high-side transistor MH. When high-side transistor MH is off and normally-off switch transistor M1 is on, the first end of primary winding <NUM> is connected ground via normally-off switch transistor M1.

In various embodiments, the series inductance of primary winding <NUM> and resonant capacitor Cr form a series resonant circuit. Accordingly, the amount of transferred from the primary side to the secondary side of switched-mode power converter <NUM> can be adjusted by varying the frequency of the switching signals used to activate and deactivate high-side transistor MH and normally-off switch transistor M1.

In some embodiments, high-side transistor MH is driven using a boosted gate driver <NUM> disposed within controller <NUM>. As shown, the half-bridge output node B is coupled to the negative power supply terminal of boosted gate drive circuit <NUM>, and boosted power supply node P is coupled to the positive power supply terminal of boosted gate driver <NUM>. In some embodiments, boosted gate drive circuit be galvanically isolated from the local power supply of controller <NUM> using isolation circuit <NUM>. Isolation circuit <NUM> may be implemented using one or more capacitors or transformers according to isolation circuits and methods known in the art. Logic circuit <NUM> may be used to produce logic signals S+ and S- of opposite logical sense from switching signal VSW to drive boosted gate driver circuit <NUM> and driver <NUM>. During operation, bootstrap capacitor Cb is charged from power supply node VDD via diode DB when normally-off switch transistor M1 couples half-bridge output node B to ground. When normally-off switch transistor M1 is turned off via node GDL and high-side transistor MH is turned on via node GDH, the voltage of half-bridge output node B increases. The increase in the voltage of half-bridge output node B causes a corresponding increase in the voltage of boosted power supply node P due to the charge stored across bootstrap capacitor Cb.

It should be understood that half-bridge based switched-mode power converter <NUM> is just one example implementation of many possible half-bridge based topologies that utilize embodiment start-up circuits. In alternative embodiments, other topologies could be used.

<FIG> illustrates a schematic cross-section of a GaN enhancement mode transistor cell <NUM> that is, according to the invention, used to implement normally-off switch transistor M1 as described above. In various embodiments, GaN enhancement mode transistor cell <NUM> is a wide bandgap (WBG) semiconductor group III-V device forming a HEMT formed using gallium nitride (GaN) technology. GaN based devices are well suited for power switching applications due to the higher band gap, higher breakdown electric field, higher thermal conductivity, high saturated drift velocity, and high radiation tolerance.

GaN enhancement mode transistor cell <NUM> includes a channel layer <NUM> including undoped GaN material and a barrier layer <NUM> formed over channel layer <NUM>. Channel layer <NUM> may disposed on a substrate (not shown) that may be a silicon substrate including a (<NUM>) silicon, silicon on oxide (SOI), sapphire, silicon carbide, or other silicon based substrates. Alternatively, the substrate may comprise other materials.

Barrier layer <NUM> includes an undoped AlxGa<NUM>-xN material, where x may vary from about <NUM> to about <NUM> in one embodiment. In various embodiments, channel layer <NUM> has a thickness between about <NUM> and about <NUM>, and first barrier layer <NUM> has a thickness of between about <NUM> and about <NUM>. Values outside of these ranges may also be possible in some embodiments for x and the various thicknesses. A two-dimensional electron gas (2DEG) region <NUM> is formed at the junction between the AlGaN/GaN heterostructure solely from spontaneous and piezoelectric induced polarization charge.

A fully recessed gate structure includes a regrown AlGaN layer <NUM> disposed over a portion of channel layer <NUM> and extending through a recess in barrier layer <NUM>. P-doped GaN material <NUM> is formed over the regrown AlGaN layer <NUM> and within the recess in barrier layer <NUM>, and a gate contact <NUM> is formed over the p-doped GaN material <NUM>. In some embodiments, regrown AlGaN layer <NUM> includes an undoped AlyGa<NUM>-yN material, where y may vary from about <NUM> to about <NUM>. Values outside of this range may also be possible in some embodiments.

During operation, when the voltage applied between the gate and source of GaN enhancement mode transistor cell <NUM> is less than a predetermined positive threshold, no current is conducted between the source and drain regions. When the applied voltage between the gate and source of GaN enhancement mode transistor cell <NUM> exceeds this predetermined positive threshold, current is conducted between the source and drain regions. In some embodiments, this predetermined positive threshold is between about 1V and about <NUM>. However, thresholds outside of this range may be possible depending on the specific embodiment and its implementations. Thus GaN enhancement mode transistor cell <NUM> functions as an enhancement mode device.

In some embodiments, an optional second p-doped region is formed over the barrier layer <NUM> close to the drain region and is electrically coupled to the drain contact <NUM>. In such embodiments, the p-doped region injects holes during a hard switching event where there is simultaneous a high drain voltage and a high drain current present. These holes recombine with possibly trapped electrons in the III-N buffer layers, thereby avoiding an increased on-state resistance after the switching event (so called dynamic RDSon). As shown, this second p-doped region includes the regrown AlGaN layer <NUM> formed over barrier layer <NUM>, the p-doped GaN material <NUM> formed over regrown AlGaN layer <NUM> and a second contact <NUM> formed over p-doped GaN material <NUM>. Because the second p-doped region is not recessed like the first p-doped region of the gate and electrically connected to the drain region, the conducting channel formed by the 2DEG region <NUM> below the second p-doped region stays conductive in all cases.

A source contact <NUM> is formed over a source region of barrier layer <NUM> and a drain contact is formed over a drain region of barrier layer <NUM>. In various embodiments, source contact <NUM>, drain contact <NUM> and gate contacts <NUM> and <NUM> are ohmic contacts and are formed from a metallic and/or conductive material known in the art. For example, in one embodiment, source contact <NUM> and drain contact <NUM> are each implemented by forming a Ti/Al layer stack that includes a Ti layer disposed over barrier layer <NUM> and a layer of Al disposed over the Ti layer. The Ti layer may be a few tens of nanometers thick, while the Al layer may be from a few tens of nanometers thick to a few hundreds of nanometers thick. Once the Ti layer and the Al layer has been disposed over the barrier layer <NUM>, a thermal annealing step of above <NUM> is performed such that nitrogen from the AlGaN material of barrier layer <NUM> is absorbed by the Ti layer, thereby creating N vacancies that act as electron donors. This mechanism effectively causes the AlGaN of barrier layer <NUM> below the Ti/Al metal contact to be n-doped and creates a low ohmic contact to 2DEG region <NUM>. In some embodiments the contact resistivity can be made to be on the order of about <NUM>Ω·mm, although other values are possible.

<FIG> illustrates a schematic cross section of a GaN depletion mode transistor cell <NUM> that is, according to the invention, used to implement normally-on start-up transistors M2, M2A and M2B as described above. The structure of GaN depletion mode transistor cell <NUM> is similar in structure to GaN enhancement mode transistor cell <NUM> shown in <FIG> with the exception that the gate is not recessed. As shown, the gate includes a regrown AlGaN layer <NUM> disposed over a portion of barrier layer <NUM>. The p-doped GaN material <NUM> is formed over a surface of the regrown AlGaN layer <NUM> (without extending through AlGaN layer <NUM>), and the gate contact <NUM> is formed over the p-doped GaN material <NUM>.

GaN depletion mode transistor cell <NUM> may formed in a similar manner as GaN enhancement mode transistor cell <NUM> with the exception that, during fabrication, the gate recess step is omitted before forming the regrown AlGaN layer <NUM> and p-doped GaN material <NUM>. In some embodiments, the selection between enhancement mode and depletion mode for a particular transistor may be advantageously determined during the layout stage of the embodiment device.

During operation, when the voltage applied between the gate and source of GaN depletion mode transistor cell <NUM> is greater than a predetermined negative threshold, current is conducted between the source and drain regions. However, when the applied voltage between the gate and source of GaN depletion mode transistor cell <NUM> is less than this predetermined negative threshold, current is not conducted between the source and drain regions. In some embodiments, this predetermined negative threshold is between about -6V and about -4V. However, thresholds outside of this range may be possible depending on the specific embodiment and its implementations. Thus, GaN depletion mode transistor cell <NUM> functions as a depletion mode device.

<FIG> illustrates a schematic cross section of a GaN depletion mode transistor cell <NUM> that may be used, in an alternative that is not covered by the claimed invention, to implement normally-on start-up transistors M2, M2A and M2B as described above. The structure of GaN depletion mode transistor cell <NUM> is similar in structure to GaN depletion mode transistor cell <NUM> shown in <FIG> with the exception that the gate is implemented using a Schottky gate metal <NUM> disposed over barrier layer <NUM>. In various embodiments the gate may be made into a T-shape by etching into a first level passivation with a stop of the barrier layer <NUM> before gate metal deposition. Dielectric layer <NUM> may be disposed over barrier layer <NUM>, as well as underneath the extended portions of Schottky gate metal <NUM>. In one embodiment, the predetermined negative threshold is about -<NUM>. 5V, however, other negative threshold values are possible.

<FIG> illustrates a schematic cross section of a GaN depletion mode transistor cell <NUM> that may be used, in an alternative that is not covered by the claimed invention, to implement normally-on start-up transistors M2, M2A and M2B as described above. The structure of GaN depletion mode transistor cell <NUM> is similar in structure to GaN depletion mode transistor cell <NUM> shown in <FIG> with the exception that a dielectric layer <NUM> is disposed between Schottky gate metal <NUM> and barrier layer <NUM>. By adjusting the thickness and other characteristics of the dielectric layer <NUM>, the predetermined negative threshold of GaN depletion mode transistor cell <NUM> may be adjusted, for example, between about -10V and about - 12V. Thresholds outside of this range may also be possible.

In various embodiments, dielectric layer <NUM> is implemented using silicon nitride (Si<NUM>N<NUM>) or silicon dioxide (SiO<NUM>) or aluminum oxide (Al<NUM>O<NUM>), and has a thickness between about <NUM> and about <NUM>. In some embodiments, an additional dielectric layer <NUM> is disposed over dielectric layer <NUM> in order to form a T-shape gate field plate to reduce the electric field under blocking conditions at the gate foot.

<FIG> illustrates a layout view of an embodiment start-up circuit cell <NUM> that can be used to implement single semiconductor substrate in package <NUM> described above with respect to <FIG> using GaN enhancement mode transistor cell <NUM> described above with respect to <FIG> and GaN depletion mode transistor cell <NUM> described above with respect to <FIG>.

As shown, the drain metallization for both transistors M1 and M2 coupled to drain node VD is represented by layer <NUM>; the source metallization for transistor M1 coupled to ground node GND is represented by layer <NUM>, the gate layer for transistor M1 coupled to gate node VG is represented by layer <NUM>, the gate layer for transistor M2 coupled to node GND is represented by layer <NUM>; and the source metallization for transistor M2 coupled to node VDD is represented by layer <NUM>. Actual device gates are formed at the intersection of layers <NUM> and active area <NUM> and layer <NUM> and active area <NUM>.

In various embodiments, regions <NUM> define the implementation of a fully recessed gate that can be used to implement an enhancement mode GaN transistor such as is described above with respect to <FIG>. Accordingly, regions <NUM> are disposed over portions of layer <NUM> within active area <NUM> to designate transistor M1 as being an enhancement mode device. By omitting region <NUM>, such as is the case with layer <NUM> representing the gate of transistor M2, the fully recessed gate is omitted and a depletion mode GaN transistor such as is described with respect to <FIG> is implemented. Accordingly, the designation of enhancement mode and depletion mode devices can be advantageously made by including an extra definition layer in during the layout phase of the design of a GaN integrated circuit. It should be understood that the layout of <FIG> is just one of many possible embodiment device layouts according to embodiment concepts. Other layouts and implementation of embodiment devices are possible.

Claim 1:
A method of starting a circuit, the method comprising:
receiving a first voltage at a drain node (VD) of a start-up circuit (<NUM>) comprising a first gallium nitride (GaN) transistor (M1) having a drain coupled to the drain node (VD), a second GaN transistor (M2) having a drain coupled to the drain node (VD) and a gate coupled to a reference node (GND), and a first capacitor (C; CA) coupled to a source of the second GaN transistor (M2; M2A);
charging the first capacitor (C; CA) via the second GaN transistor (M2; M2A);
providing energy from the first capacitor (C; CA) to a driver circuit (<NUM>) coupled to a gate of the first GaN transistor (M1); and
turning-off the second GaN transistor (M2; M2A) when a voltage of the first capacitor (C; CA) reaches a threshold,
wherein the first GaN transistor (M1) and the second GaN transistor (M2; M2A) are integrated on a same semiconductor substrate, and
wherein the first GaN transistor (M1) is a normally-off device, and the second GaN transistor (M2; M2A) is a normally-on device,
characterised in that
the gate of the first GaN transistor (M1) comprises a fully recessed gate comprising a p-doped GaN material (<NUM>) on top of a second AlGaN layer (<NUM>) that extends through a first AlGaN layer (<NUM>),
wherein the first AlGaN layer (<NUM>) is disposed over a channel layer (<NUM>) comprising undoped GaN material and
wherein the gate of the second GaN transistor (M2; M2A) is disposed over surfaces of the first and second AlGaN layers (<NUM>, <NUM>) without extending through the first AlGaN layer (<NUM>).