Patent Description:
Various examples address technical problems associated with disabling a voltage regulator, independent of control over the input power supplies and tolerant to high voltages. As understood by those of skill in the field to which the present disclosure pertains, there are numerous example scenarios in which a user may need to disable a voltage regulator independent of the supply of voltage received at the voltage regulator.

For example, a power management unit (PMU) is generally responsible for providing a stable source of power to a system-on-chip (SoC) electronic device. Many regulators may support multiple power domains, for example, a regulator may provide both a low voltage supply and a high voltage supply depending on the supplied power. In general, the PMU generates a low voltage power supply to be supplied to the core logic of the SoC. However, in some instances, the low voltage power supply may be provided by an external power supply. When the low voltage supply is supplied externally, the voltage regulator should be disabled. In an instance in which power is supplied by an external power supply, the change in power supplies may not be synchronized, potentially leading to undesirable electrical flow conditions.

Document <CIT> discloses a regulator circuit that includes a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator includes an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated. Document <CIT> discloses an apparatus and method for disabling an internal voltage regulator of a circuit to voltage stress test the circuit. The apparatus includes a circuit having an internal voltage regulator and a design-for-test circuit coupled to the circuit to disable the internal voltage regulator to voltage stress test the circuit in a test mode.

Document <CIT> discloses methods and apparatus to provide multiple input voltage regulation in which one regulator is selected for operation based on input power conditions. A dual input voltage regulator system in a combination smart card selects between contact and contactless (e.g., RF) operation based on which power source provides the highest available voltage level. A single transistor drop architecture provides low drop-out voltage regulation capability without substantially increased transistor size. Multiplexed control of the regulators for each of a number independent power source inputs may be arranged to substantially reduce or prevent reverse current flow through regulators connected to inactive power inputs.

Applicant has identified many technical challenges and difficulties associated with disabling a voltage regulator independent of supply voltages. Through applied effort, ingenuity, and innovation, Applicant has solved problems related to disabling voltage regulators by developing solutions embodied in the present disclosure, which are described in detail below.

Various embodiments are directed to an example circuit, and power management unit utilizing the example circuit to disable a voltage regulator. In some embodiments, the circuit comprises a voltage selection circuit configured to receive a first voltage source and a second voltage source, and further configured to output a selected voltage. The voltage selection circuit comprises a first transistor component having a first transistor component source, a first transistor component gate, and a first transistor component drain, wherein the first transistor component source is electrically connected to the first voltage source, and wherein the first transistor component gate is electrically connected to the first transistor component drain. The voltage selection circuit further comprises a second transistor component having a second transistor component source, a second transistor component gate, and a second transistor component drain, wherein the second transistor component source is electrically connected to the first voltage source, and wherein a second transistor gate voltage at the second transistor component gate is generated based at least in part on a first transistor component drain voltage at the first transistor component drain. In some embodiments, the selected voltage is generated based at least in part on a second transistor drain voltage at the second transistor component drain. The electrical circuit further comprises a power-down switching device configured to generate a regulator gate voltage for a voltage regulator based at least in part on the selected voltage.

In some embodiments, the power-down switching device may further comprise a pull-up switching component having a pull-up transistor source, a pull-up transistor gate, and a pull-up transistor drain, wherein the pull-up transistor source is electrically connected to the selected voltage of the voltage selection circuit, and wherein the pull-up transistor gate is electrically connected to a power-down output signal of a power-down generator circuit.

In some embodiments, the power-down generator circuit may be configured to receive the first voltage source and a power-down signal, wherein the power-down generator circuit further comprises a power-down voltage divider electrically connected to the first voltage source and the power-down signal, wherein the power-down voltage divider is enabled by the power-down signal, and wherein the power-down voltage divider generates the power-down output signal based at least in part on a voltage difference between the first voltage source and the power-down signal.

In some embodiments, the voltage selection circuit further comprises a first voltage selection circuit voltage divider electrically connected to the first transistor component drain of the first transistor component and the second voltage source, wherein the first voltage selection circuit voltage divider is configured to generate a first voltage divided output based on a voltage difference between the first transistor component drain voltage at the first transistor component drain and the second voltage source. In some embodiments, the first voltage divided output may be electrically connected to the second transistor component gate of the second transistor component.

In some embodiments, the voltage selection circuit may further comprise a second voltage selection circuit voltage divider electrically connected to the selected voltage and a ground, wherein a second voltage selection circuit voltage divider tap is electrically connected to the second voltage source.

In some embodiments, the second voltage selection circuit voltage divider may comprise a second voltage selection circuit voltage divider first resistive component electrically connected to the selected voltage and the second voltage selection circuit voltage divider, the second voltage selection circuit voltage divider tap, and a second voltage selection circuit voltage divider second resistive component electrically connected to the ground and the second voltage selection circuit voltage divider tap. In some embodiments, a resistive value of the second voltage selection circuit voltage divider first resistive component may be greater than the resistive value of the second voltage selection circuit voltage divider second resistive component.

In some embodiments, the power-down voltage divider may comprise a power-down voltage divider first resistive component electrically connected to the first voltage source and the power-down output signal, a power-down voltage divider tap electrically connected to the power-down output signal; and a power-down voltage divider second resistive component electrically connected to the power-down voltage divider tap and the power-down signal.

In some embodiments, the power-down voltage divider further comprises a first power-down transistor component having a first power-down transistor component source, a first power-down transistor component gate, and a first power-down transistor component drain. In some embodiments, the first power-down transistor component drain is electrically connected to the power-down voltage divider tap, the first power-down transistor component source is electrically connected to the power-down voltage divider second resistive component, and the first power-down transistor component gate, and wherein the first power-down transistor component gate is further connected to a floating voltage supply block.

In some embodiments, the power-down voltage divider further comprises a second power-down transistor component having a second power-down transistor component source, a second power-down transistor component gate, and a second power-down transistor component drain. In some embodiments, the second power-down transistor component drain is electrically connected to the power-down voltage divider second resistive component, the second power-down transistor component gate is electrically connected to the power-down signal, and the second power-down transistor component source is electrically connected to ground.

In some embodiments, a conductive path diode may be electrically connected between the power-down voltage divider tap and the first power-down transistor component gate.

In some embodiments, the floating voltage supply block may generate a floating supply voltage based on a voltage output of the first voltage source.

In some embodiments, the first transistor component and the second transistor component may be p-type metal-oxide-semiconductor field-effect transistors.

In some embodiments, the first power-down transistor component and the second power-down transistor component may be n-type metal-oxide-semiconductor field-effect transistors.

In some embodiments, the voltage regulator may comprise an operational amplifier having a first input and a second input, wherein the first input is electrically connected to a reference voltage. In some embodiments, the voltage regulator may further comprise a voltage regulator transistor component having a voltage regulator transistor component source, a voltage regulator transistor component gate, and a voltage regulator transistor component drain.

In some embodiments, the voltage regulator transistor component source may be electrically connected to an output of the operational amplifier, the voltage regulator transistor component gate may be electrically connected to an output of the operational amplifier and to the regulator gate voltage; and the voltage regulator transistor component drain may be electrically connected to the second input of the operational amplifier.

In some embodiments an example power management unit utilizing an example circuit to disable a voltage regulator is further provided. In some embodiments, the example power management unit may comprise a transformer, a rectifier circuit electrically connected to the transformer, a filter circuit electrically connected to the rectifier circuit, and a voltage regulator. In some embodiments, the voltage regulator may comprise a voltage selection circuit configured to receive a first voltage source and a second voltage source, and further configured to output a selected voltage. In some embodiments, the voltage selection circuit may comprise a first transistor component having a first transistor component source, a first transistor component gate, and a first transistor component drain, wherein the first transistor component source is electrically connected to the first voltage source, and wherein the first transistor component gate is electrically connected to the first transistor component drain. In some embodiments, the voltage selection circuit may further comprise a second transistor component having a second transistor component source, a second transistor component gate, and a second transistor component drain. In some embodiments, the second transistor component source may be electrically connected to the first voltage source, and a second transistor component gate voltage at the second transistor component gate may be generated based at least in part on a first transistor component drain voltage at the first transistor drain. In some embodiments, the selected voltage may be generated based at least in part on a second transistor component drain voltage at the second transistor component drain. In some embodiments, the voltage regulator may further comprise a power-down switching device configured to generate a regulator gate voltage for the voltage regulator based at least in part on the selected voltage. In some embodiments, the voltage regulator may further comprise an operational amplifier having a first input and a second input, wherein the first input may be electrically connected to a reference voltage. In some embodiments, the voltage regulator may further comprise a voltage regulator transistor component having a voltage regulator transistor component source, a voltage regulator transistor component gate, and a voltage regulator transistor component drain. In some embodiments, the voltage regulator transistor component source may be electrically connected to an output of the operational amplifier, the voltage regulator transistor component gate may be electrically connected to an output of the operational amplifier and to the regulator gate voltage, and the voltage regulator transistor component drain may be electrically connected to the second input of the operational amplifier.

In some embodiments, the power-down switching device may further comprise a pull-up switching component having a pull-up transistor source, a pull-up transistor gate, and a pull-up transistor drain. In some embodiments, the pull-up transistor source may be electrically connected to the selected voltage of the voltage selection circuit, and the pull-up transistor gate may be electrically connected to a power-down output signal of a power-down generator circuit.

In some embodiments, the power-down generator circuit may be configured to receive the first voltage source and a power-down signal, wherein the power-down generator circuit further comprises a power-down voltage divider electrically connected to the first voltage source and the power-down signal. In some embodiments, the power-down voltage divider may be enabled by the power-down signal, and the power-down voltage divider may generate the power-down output signal based at least in part on a voltage difference between the first voltage source and the power-down signal.

In some embodiments, the voltage selection circuit may further comprise a first voltage selection circuit voltage divider electrically connected to the first transistor component drain of the first transistor component and the second voltage source. In some embodiments, the first voltage selection circuit voltage divider may be configured to generate a first voltage divided output based on a voltage difference between the first transistor component drain voltage at the first transistor component drain and the second voltage source, and the first voltage divided output may be electrically connected to the second transistor component gate of the second transistor component.

Reference will now be made to the accompanying drawings. The components illustrated in the figures may or may not be present in certain embodiments described herein. Some embodiments may include fewer (or more) components than those shown in the figures in accordance with an example of the present disclosure.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the inventions of the disclosure are shown. Indeed, embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.

As described herein, the term "high" when referring to voltages indicates the identified voltage is above a certain minimum voltage threshold for the electronic device, generally between <NUM> volts and <NUM> volts. Similarly, the term "low" when referring to voltages indicates the identified voltage is below a certain voltage threshold for the electronic device, generally at or near <NUM> volts.

Various example embodiments address technical problems associated with disabling a voltage regulator, independent of synchronization with supply voltages. As understood by those of skill in the field to which the present disclosure pertains, there are numerous example scenarios in which a user may need to disable a voltage regulator independent of the supply of voltage received at the voltage regulator. For example, a power management unit (PMU) is generally responsible for providing a stable source of power to a system-on-chip (SoC) electronic device. Many regulators may support multiple power domains, for example, a regulator may provide both a low voltage supply and a high voltage supply depending on the supplied power. In addition, in some instances, an SoC or other electronic device may support an externally supplied voltage source. In an instance in which the power supply is provided by an external voltage regulator, one or more voltage regulators of the PMU may need to be disabled.

Referring to <FIG>, a common voltage regulator <NUM> is provided. As shown in <FIG>, the common voltage regulator <NUM> comprises an op amp <NUM> having a first input terminal where a reference voltage <NUM> is received, and a second input terminal <NUM> configured to receive feedback from the drain terminal 108c of an electrically connected transistor (e.g., power MOSFET <NUM>). In some embodiments, the reference voltage may be supplied by a bandgap circuit and may comprise a voltage at or near <NUM> millivolts, however, a reference voltage <NUM> may be received from any stable voltage source and may comprise a wide range of voltages. The op amp <NUM> may further receive power from a high voltage source <NUM>. In some embodiments, the high voltage source <NUM> may comprise a voltage in a range from <NUM> volts to <NUM> volts, however, a high voltage source <NUM> may comprise a wide range of voltages with a peak voltage greater than the low voltage source <NUM>. The op amp <NUM> depicted in <FIG>, generates a regulator gate voltage <NUM> on an output. The output of the op amp <NUM> is electrically connected to a power metal-oxide-semiconductor field-effect-transistor (MOSFET) <NUM>.

As shown in <FIG>, the power MOSFET <NUM> includes three terminals, a source terminal 108a, a gate terminal 108b, and a drain terminal 108c. The source terminal 108a is the point at which, when enabled, current generally flows into the power MOSFET <NUM>. As depicted in <FIG>, the source terminal 108a is electrically connected to the high voltage source <NUM>. The drain terminal 108c is the point at which the current generally flows out of the power MOSFET <NUM>. As depicted in <FIG>, the drain terminal 108c is electrically connected to the second input terminal <NUM> of the op amp <NUM>. In addition, as depicted in <FIG>, the drain terminal 108c of the power MOSFET <NUM> supplies the low voltage source <NUM> to the electrically connected device.

In general, the gate terminal 108b of a MOSFET is used to control the flow of current between the source terminal 108a and the drain terminal 108c. In some embodiments, a gate terminal voltage at or near the voltage at the source terminal 108a may be applied to turn off the MOSFET and stop the flow of current through the MOSFET. Conversely, a gate terminal voltage that creates a voltage difference between the gate terminal and the source terminal may turn on the MOSFET and allow the flow of current through the MOSFET.

When a power supply is supplied externally, a voltage regulator, for example the voltage regulator <NUM> shown in <FIG>, may be disabled. For example, in an instance in which the voltage regulator <NUM> supplies the low voltage power source to the electrically connected device, the voltage regulator <NUM> may be disabled. However, because of the asynchronous nature of the external power source, the high voltage source <NUM> may be enabled and providing power at a voltage higher than the low voltage source <NUM>, or, alternatively, the high voltage source <NUM> may be disabled at a voltage at or near <NUM>.

The state of the high voltage source <NUM> when the voltage regulator <NUM> is disabled is important in determining the regulator gate voltage <NUM> necessary to disable the power MOSFET <NUM>. For example, in an instance in which the high voltage source <NUM> is at <NUM> volts, if the regulator gate voltage <NUM> is pulled to the high voltage source <NUM> in an attempt to turn off the MOSFET, the voltage at the gate terminal 108b (<NUM> volts) and at the source terminal 108a (<NUM> volts) are both lower than the voltage at the drain terminal 108c. Thus, current may flow from the low voltage source <NUM> into the high voltage source <NUM>, which is undesirable.

In addition, in some embodiments, the maximum voltage rating of one or more of the electrical components may be less than the voltage provided by the high voltage source <NUM>. In such an embodiment, electrical components may be damaged or destroyed if the voltage drop across the component is greater than the maximum voltage rating.

The various example embodiments described herein utilize various techniques to ensure a voltage regulator is properly disabled in an instance in which the voltage source is provided by an external, asynchronous source. For example, in some embodiments, a voltage selection circuit is provided to generate a selected voltage that is the higher of the two supply voltages. In addition, the voltage selection circuit ensures that the voltage drop across the electrical components does not exceed the maximum voltage rating of the electrical components, for example, <NUM> volts.

In some embodiments, a power-down generator circuit is further provided. In general, a power-down generator circuit may be configured to relay a power-down signal from the logic domain of the electronic device and enable the selected voltage supply to the voltage regulator. However, in some embodiments, the power-down signal may be adjusted based on the selected voltage. For example, in some embodiments, the selected voltage may be greater than the maximum voltage rating of the electrical components of a power-down switching device, such as a transistor. In such an embodiment, the power-down signal may be adjusted to prevent a voltage drop across the electrical components greater than the maximum voltage rating of the electrical components.

As a result of the herein described example embodiments and in some examples, the performance of a voltage regulator may be greatly improved. In addition, electrical components having a maximum voltage rating lower than the voltage of a high voltage source may be utilized.

Referring now to <FIG>, an example supply voltage independent voltage regulator disable circuit <NUM> is provided. As shown in <FIG>, the example supply voltage independent voltage regulator disable circuit <NUM> supplies a regulator gate voltage <NUM> to an electrically connected voltage regulator <NUM>, the voltage regulator <NUM> further configured to receive a reference voltage <NUM>. The regulator gate voltage <NUM> is supplied by a power-down switching device <NUM> electrically connected to the voltage regulator <NUM>. The power-down switching device <NUM> is configured to output the regulator gate voltage <NUM> based on a power-down output signal <NUM> and a selected voltage <NUM> supplied by an electrically connected voltage selection circuit <NUM>. The voltage selection circuit <NUM> is configured to select the selected voltage <NUM> based on output voltages received from an electrically connected high voltage source <NUM> and an electrically connected low voltage source <NUM>.

As depicted in <FIG>, the supply voltage independent voltage regulator disable circuit <NUM> supplies a regulator gate voltage <NUM> to a voltage regulator <NUM>. As described in relation to <FIG>, the voltage regulator <NUM> may be any electronic component or device comprising hardware, firmware, software, or a combination thereof and configured to receive a reference voltage <NUM> and output a stable, consistent voltage within a specified range based on the reference voltage <NUM>. The voltage regulator <NUM> may comprise a linear regulator, a switch regulator, a low-dropout regulator, a fixed voltage regulator, an adjustable voltage regulator, or similar type regulator. As described in relation to <FIG>, the voltage regulator <NUM> may be controlled by a regulator gate voltage <NUM>. In an instance in which the regulator gate voltage <NUM> is at or near the voltage at the source terminal of the internal switch device (e.g., power MOSFET <NUM>), the switch device is turned off and the output voltage from the voltage regulator <NUM> is stopped. Conversely, in an instance in which the regulator gate voltage <NUM> creates a voltage difference between the gate terminal and the source terminal of the switch device, the voltage regulator <NUM> is turned on and an output voltage from the voltage regulator <NUM> is generated.

As further depicted in <FIG>, the supply voltage independent voltage regulator disable circuit <NUM> comprises a power-down switching device <NUM>. A power-down switching device <NUM> may be any electrical component, plurality of components, or device, configured to control the passage of the selected voltage <NUM> from the voltage selection circuit <NUM> to the voltage regulator <NUM>. In some embodiments, the power-down switching device <NUM> may comprise a MOSFET, a bipolar junction transistor (BJT), a switch, or other switching device. In some embodiments, the power-down switching device <NUM> may be a short, or resistor, allowing the selected voltage <NUM> or a portion of the selected voltage <NUM> to pass without switching. An example power-down switching device <NUM> is further provided in <FIG>.

In some embodiments, the power-down switching device <NUM> may be enabled by a power-down output signal <NUM>. A power-down output signal <NUM> may be any electrical signal or series of signals providing indication to disable the voltage regulator <NUM>. For example, a power-down output signal <NUM> may be asserted when the voltage regulator <NUM> is to be powered down. In some embodiments, the voltage of the power-down output signal <NUM> may be elevated above a pre-determined minimum voltage to indicate power down. In some embodiments, the voltage of the power-down output signal <NUM> may be dropped below a pre-determined maximum voltage to indicate power down. In some embodiments, the voltage of the power-down output signal <NUM> may be altered by a power-down generator circuit (as described in relation to <FIG>) to protect the electrical components comprising the power-down switching device <NUM>, and other electrical components, from exposure to high voltages exceeding the maximum voltage rating of the underlying semiconductor technology.

As further depicted in <FIG>, the supply voltage independent voltage regulator disable circuit <NUM> further comprises a voltage selection circuit <NUM>. A voltage selection circuit <NUM> may be any electrical components, including hardware, firmware, software, or any combination thereof configured to determine a selected voltage <NUM> based at least in part on the higher voltage between the high voltage source <NUM> and the low voltage source <NUM>. In some embodiments, an external low voltage source <NUM> may supply the low voltage within an electronic device. In an instance in which the low voltage is supplied by an external low voltage source <NUM>, the internal voltage regulator <NUM> responsible for providing a low voltage source to the electronic device may be disabled. In such an embodiment, the high voltage source <NUM> may output a high voltage, no voltage, or any voltage in between. In an instance in which the low voltage source <NUM> is provided but the high voltage source <NUM> is at or near <NUM> volts, disabling the voltage regulator <NUM> by tying the regulator gate voltage <NUM> to the high voltage source <NUM> may result in a voltage at the drain terminal of the power MOSFET (e.g., power MOSFET <NUM>) within the voltage regulator <NUM> that is higher than the voltage at the gate terminal and the voltage at the source terminal. This scenario may result in current flowing from the low voltage source <NUM> to the high voltage source <NUM>, which may be undesirable. Thus, the voltage selection circuit <NUM> may not simply provide a selected voltage <NUM> equal to the high voltage source <NUM> but may select the selected voltage <NUM> based on the greater of the high voltage source <NUM> and the low voltage source <NUM>. Example embodiments of the voltage selection circuit <NUM> are described in further detail in relation to <FIG> and <FIG>.

Referring now to <FIG>, an example power-down switching device <NUM> component of a supply voltage independent voltage regulator disable circuit (e.g., supply voltage independent voltage regulator disable circuit <NUM>) is provided. As depicted in <FIG>, the example power-down switching device <NUM> comprises a pull-up transistor <NUM> (e.g., pull-up switching component). The pull-up transistor <NUM> is electrically connected to the selected voltage <NUM> output of a voltage selection circuit (e.g., voltage selection circuit <NUM> as depicted in <FIG>) at the source terminal and the regulator gate voltage <NUM> of the voltage regulator <NUM> at the drain terminal. In addition, the pull-up transistor <NUM> depicted in <FIG> is electrically connected to a power-down output signal <NUM> at the gate terminal of the pull-up transistor <NUM>.

As depicted in <FIG>, the example power-down switching device <NUM> includes a pull-up transistor <NUM>. Although depicted as a pull-up transistor <NUM> in <FIG>, a pull-up switching component may be any transistor, MOSFET, BJT, or other switching device that enables control of the regulator gate voltage <NUM> based on the selected voltage <NUM> and the power-down output signal <NUM>. As depicted, the pull-up transistor <NUM> enables the selected voltage <NUM> to be applied at the gate of the voltage regulator transistor <NUM> of the voltage regulator <NUM>, thus disabling the flow of current through the voltage regulator transistor <NUM>.

For example, in some embodiments, the high voltage source <NUM> may be high (e.g., between <NUM> volts and <NUM> volts) when the power-down output signal <NUM> is asserted. In such an instance, the pull-up transistor <NUM> is enabled and the flow of current through the pull-up transistor <NUM> increases the regulator gate voltage <NUM> to the selected voltage <NUM>, which is equivalent to the voltage (high voltage source <NUM>) at the source of the voltage regulator transistor <NUM>. Thus, the flow of current at the voltage regulator transistor <NUM> and into the low voltage source <NUM> is disabled. Similarly, in some embodiments, the high voltage source <NUM> may be low (e.g., at or near <NUM> volts) when the power-down output signal <NUM> is asserted. In such an instance, the pull-up transistor <NUM> is enabled and the flow of current through the pull-up transistor <NUM> increases the regulator gate voltage <NUM> to the selected voltage <NUM>, which is equivalent to the voltage (low voltage source <NUM>) at the drain of the voltage regulator transistor <NUM>. Thus, the flow of current at the voltage regulator transistor <NUM> is disabled and current flow from the low voltage source <NUM> to the high voltage source <NUM> through the voltage regulator transistor <NUM> is prevented.

Referring now to <FIG>, an example supply voltage independent voltage regulator disable circuit <NUM> is provided. As depicted in <FIG>, the example supply voltage independent voltage regulator disable circuit <NUM> includes a voltage selection circuit <NUM> electrically connected to a high voltage source <NUM> and a low voltage source <NUM> and generating a selected voltage <NUM> based on the high voltage source <NUM> and the low voltage source <NUM>. In addition, the example supply voltage independent voltage regulator disable circuit <NUM> includes a power-down switching device <NUM> receiving the selected voltage <NUM> from the electrically connected voltage selection circuit <NUM> and further receiving a power-down output signal <NUM> from an electrically connected power-down generator circuit <NUM>. As depicted in <FIG>, the power-down generator circuit <NUM> is electrically connected to the high voltage source <NUM> and is further configured to receive a power-down signal <NUM>. As further depicted in <FIG>, the power-down switching device <NUM> is configured to generate a regulator gate voltage <NUM> supplied to an electrically connected voltage regulator <NUM>.

As depicted in <FIG>, the example supply voltage independent voltage regulator disable circuit <NUM> includes a power-down generator circuit <NUM> configured to receive a power-down signal <NUM>. A power-down generator circuit <NUM> may be any hardware, firmware, software, or combination thereof configured to receive a power-down signal <NUM> and apply necessary adjustments to the power-down signal <NUM> to avoid damage to electrical components due to high voltages. A power-down signal <NUM> may be any signal or sequence of signals providing an indication to power-down one or more electrically connected components, such as voltage regulator <NUM>.

For example, in some embodiments, the electrical components of the supply voltage independent voltage regulator disable circuit <NUM> may support a maximum voltage of <NUM> volts. In an instance in which the high voltage source is greater than <NUM> volts, for example <NUM> volts, some electrical components may be exposed to a voltage difference greater than the maximum <NUM> volts. For example, a power-down switching device <NUM> may comprise one or more transistors (e.g., pull-up transistor <NUM> as depicted in <FIG>) having a maximum voltage rating of <NUM> volts. In an instance in which the high voltage source <NUM> is greater than <NUM> volts (e.g., <NUM> volts) and the power-down output signal <NUM> is low (e.g., <NUM> volts), the voltage difference across the one or more transistors may be greater than <NUM> volts causing stress on and potentially damaging the one or more transistors. Thus, the power-down generator circuit <NUM>, in some embodiments, may adjust the power-down signal <NUM> to avoid exceeding the maximum voltage rating of the electrical components of the supply voltage independent voltage regulator disable circuit <NUM>, the voltage regulator <NUM>, and other electrically connected components.

Referring now to <FIG>, a specific embodiment of an example voltage selection circuit <NUM> is provided. As depicted in <FIG>, the example voltage selection circuit <NUM> includes a first transistor <NUM> (e.g., first transistor component) and a second transistor <NUM> (e.g., second transistor component) wherein the source terminal 550a, 551a of each transistor <NUM>, <NUM> are electrically connected to the high voltage source <NUM>. As further depicted in <FIG>, a first voltage divider <NUM> (e.g., first voltage selection circuit voltage divider) having a first resistor <NUM>, a second resistor <NUM>, and a first voltage divider tap <NUM> (e.g., first voltage divided output) electrically connected to the first voltage divider <NUM> between the first resistor <NUM> and the second resistor <NUM> is electrically connected between the drain terminal 550c of the first transistor <NUM> and the low voltage source <NUM>. In addition, the drain terminal 550c of the first transistor <NUM> is electrically connected to the gate terminal 550b of the first transistor <NUM>. As further depicted in <FIG>, the first voltage divider tap <NUM> is electrically connected to the gate terminal 551b of the second transistor <NUM>. In addition, a second voltage divider <NUM> (e.g., second voltage selection circuit voltage divider) having a first resistor <NUM> (e.g., second voltage selection circuit voltage divider first resistive component), a second resistor <NUM> (e.g., second voltage selection circuit voltage divider second resistive component), and a second voltage divider tap <NUM> (e.g., second voltage circuit voltage divider tap) electrically connected to the second voltage divider <NUM> between the first resistor <NUM> and the second resistor <NUM> is electrically connected between the drain terminal 551c of the second transistor <NUM> and ground. As further depicted in <FIG>, the low voltage source <NUM> is electrically connected to the second voltage divider tap <NUM>. In addition, the selected voltage <NUM> output is supplied by making an electrical connection at the drain terminal 551c of the second transistor <NUM>.

As depicted in <FIG>, the example voltage selection circuit <NUM> includes a first transistor <NUM>. Although depicted as a transistor, the first transistor <NUM> may be any transistor, MOSFET, BJT, or other switching device that prevents the flow of current from the low voltage source <NUM> to the high voltage source <NUM> when a voltage from the low voltage source <NUM> is present and a voltage from the high voltage source <NUM> is not. In such an instance, the voltage at the gate terminal 550b is equivalent to the voltage at the drain terminal 550c (e.g., at or near the voltage of the low voltage source <NUM>) and greater than the voltage at the source terminal 550a (e.g., approximately <NUM> volts), thus the first transistor <NUM> is disabled. Further, in an instance in which the high voltage source <NUM> is high, the voltage at the source terminal 550a of the first transistor <NUM> is higher than the voltage at the gate terminal 550b of the first transistor <NUM> and the first transistor <NUM> is turned on. In such an instance, a voltage drop exists across the first transistor <NUM> and the first voltage divider <NUM> as described further herein.

As further depicted in <FIG>, the example voltage selection circuit <NUM> includes a first voltage divider <NUM> electrically connected between the drain terminal 551c of the first transistor <NUM> and the low voltage source <NUM>. A voltage divider <NUM> may be any hardware, firmware, software, or combination thereof configured to provide a reduced voltage level based on the voltage drop across the voltage divider <NUM>. As depicted in <FIG>, the first voltage divider <NUM> comprises a plurality of resistors (e.g., first resistor <NUM> and second resistor <NUM>) connected in series. The first voltage divider <NUM> further includes a tap output provided by supplying an electrical contact to a point between the two resistors (e.g., first voltage divider tap <NUM>). The voltage at the first voltage divider tap <NUM> may be determined based on the value of the two resistors and the voltage drop across the voltage divider <NUM>. For example, the voltage at the first voltage divider tap <NUM> may be equal to: <MAT> where VDIV is the voltage drop across the voltage divider, VTAP is the voltage drop across the resistor R<NUM>, R<NUM> is the resistance of the second resistor (e.g., second resistor <NUM>), and R<NUM> is the resistance of the first resistor (e.g., first resistor <NUM>). By electrically connecting the first voltage divider <NUM> between the high voltage source <NUM> and the low voltage source <NUM>, in an instance in which the first transistor <NUM> is enabled, a reduced voltage level is generated at the first voltage divider tap <NUM> based on the resistance values of first resistor <NUM> and second resistor <NUM> and provided to the gate terminal 551b of the second transistor <NUM>.

For example, as depicted in <FIG>, the voltage at the tap (V<NUM>) of the first voltage divider <NUM> may be determined as follows: <MAT> where V<NUM> is the voltage at the low voltage source <NUM>, V<NUM> is the voltage at the high voltage source <NUM>, VGS_550 is the voltage drop from the gate terminal 551b to the source terminal 551a of the first transistor <NUM>, R<NUM> is the resistance of the first resistor <NUM>, and R<NUM> is the resistance of the second resistor <NUM>. In some embodiments, the second resistor <NUM> may have a resistance of <NUM> ohms, while the first resistor <NUM> may have a resistance of <NUM> ohms.

As further depicted in <FIG>, the example voltage selection circuit <NUM> includes a second transistor <NUM>. Although depicted as a transistor, the second transistor <NUM> may be any transistor, MOSFET, BJT, or other switching device that allows the flow of current through when the voltage at high voltage source <NUM> is high and prevents the flow of current in an instance in which the high voltage source is low. Thus, when the voltage at high voltage source <NUM> is high, the voltage received from the first voltage divider tap <NUM> will be sufficiently lower than the high voltage source <NUM> at the gate terminal 551b of the second transistor <NUM>, such that the second transistor <NUM> will be enabled and the selected voltage will be at or near the voltage of the high voltage source <NUM>. In an instance in which the high voltage source <NUM> is low, the second transistor <NUM> will be off, or disabled, such that the selected voltage <NUM> is at or near the voltage of the low voltage source <NUM>.

As depicted in <FIG>, the first transistor <NUM> and the second transistor <NUM> utilize fully depleted silicon-on-insulator (FDSOI) technology. In general, FDSOI technology enables adjustments to the threshold voltage of a transistor to be made by applying a bias voltage to the bulk terminal (e.g., bulk terminal 550d, bulk terminal 551d) of the transistor. For p-type MOSFET transistors, increasing the voltage applied to the bulk terminal may increase the threshold voltage. Conversely, for n-type MOSFET transistors, increasing the voltage applied to the bulk terminal may decrease the threshold voltage. As depicted in <FIG>, electrically connecting the bulk terminal of the p-type MOSFETs to ground decreases the threshold voltage. As shown in <FIG>, the bulk terminal 550d of first transistor <NUM> is electrically connected to the high voltage source <NUM>, thus increasing the threshold voltage of first transistor <NUM> and the bulk terminal 551d of second transistor <NUM> is electrically connected to ground, thus decreasing the threshold voltage of second transistor <NUM>. Biasing first transistor <NUM> and second transistor <NUM> in this way ensures the second transistor <NUM> is strongly on when the high voltage source <NUM> is high.

In some embodiments, both the first transistor <NUM> and the second transistor <NUM> may comprise p-type transistors.

As further depicted in <FIG>, the example voltage selection circuit <NUM> includes a second voltage divider <NUM> electrically connected between the drain terminal 551c of the second transistor <NUM> and ground. The second voltage divider <NUM> may be any hardware, firmware, software, or combination thereof configured to prevent the flow of current from the high voltage source <NUM> to the low voltage source <NUM> in an instance in which the high voltage source <NUM> is high and the regulator is disabled, such that the low voltage source <NUM> is low. As depicted in <FIG>, the second voltage divider <NUM> comprises a plurality of resistors (e.g., first resistor <NUM> and second resistor <NUM>) connected in series. The second voltage divider <NUM> further includes a tap output provided by supplying an electrical contact to a point between the two resistors (e.g., second voltage divider tap <NUM>). In some embodiments, the resistance value of second resistor <NUM> may be much less than the resistance value of the first resistor <NUM>. For example, the second resistor <NUM> may have a resistance of <NUM> ohms, while the first resistor <NUM> may have a resistance of <NUM> ohms. By utilizing a second voltage divider <NUM> wherein the second resistor <NUM> is much smaller than the first resistor <NUM>, the low voltage source <NUM> may be kept close to ground in an instance in which the low voltage source <NUM> is not provided, and may be protected from receiving charge from the high voltage source <NUM> when the second transistor <NUM> is enabled.

As further depicted in <FIG>, the example voltage selection circuit <NUM> may enable the use of voltages greater than the maximum tolerable voltage difference across two terminals of the underlying electrical components. For example, in an instance in which the maximum tolerable voltage difference across two terminals of the first transistor <NUM> and the second transistor <NUM> is <NUM> volts, and the high voltage source <NUM> is <NUM> volts, the transistors may be protected from a voltage difference of more than <NUM> volts at any of the terminals. To illustrate, in an instance in which the high voltage source <NUM> is high (e.g., <NUM> volts), the first voltage divider <NUM> ensures that the voltage at the drain terminal 550c and thus the gate terminal 550b is at or near <NUM> volts, thus, none of the terminals on the first voltage divider <NUM> exceed the maximum tolerable voltage difference across two terminals. Similarly, since the second resistor <NUM> is greater than the first resistor <NUM>, the first voltage divider tap <NUM> supplied to the gate terminal 551b of the gate terminal is sufficiently close to the high voltage source <NUM> as to not exceed the maximum tolerable voltage difference across two terminals of the second transistor <NUM>.

Referring now to <FIG>, an example power-down generator circuit <NUM> of an example supply voltage independent voltage regulator disable circuit is provided. As depicted in <FIG>, the example power-down generator circuit <NUM> includes a voltage divider <NUM> (e.g., power-down voltage divider) comprising a first resistor <NUM> (e.g., power-down voltage divider first resistive component), a second resistor <NUM> (e.g., power-down voltage divider second resistive component), and a tap <NUM> (e.g., power-down voltage divider tap). Further, the example power-down generator circuit <NUM> includes a first transistor <NUM> (e.g., first power-down transistor component) electrically connected to the first resistor <NUM> at the drain terminal 661a and the second resistor <NUM> at the source terminal 661c. The power-down generator circuit <NUM> further comprises a conductive path diode <NUM> electrically connected at the anode end to the source terminal 661c of the first transistor <NUM>, and electrically connected at the cathode end to the gate terminal 661b of the first transistor <NUM>. In addition, a floating voltage supply <NUM> is electrically connected to the gate terminal 661b of the first transistor <NUM>. As further depicted in <FIG>, a second transistor <NUM> (e.g., second power-down transistor component) is electrically connected between the second resistor <NUM> and ground. Further, a power-down signal <NUM> is electrically connected to the gate terminal 663b of the second transistor <NUM> as provided by electrically connected logic circuitry <NUM> and an electrically connected internal supply generator <NUM>. Further depicted in <FIG>, the high voltage source <NUM> is electrically connected to the first resistor <NUM> of the voltage divider <NUM>, and the power-down output signal <NUM> is provided to the power-down switching device <NUM> through an electrical connection to the drain terminal 661a of the first transistor <NUM>.

As depicted in <FIG>, the power-down generator circuit <NUM> receives a power-down signal <NUM> from logic circuitry <NUM> located on or near an electronic device utilizing the high voltage source <NUM>. In some embodiments, the logic circuitry <NUM> receives a power supply from an internal supply generator <NUM> that may be a reduced voltage from the high voltage source <NUM>. For example, in some embodiments, the high voltage source may be <NUM> volts, while the power supply provided to the logic circuitry <NUM> by the internal supply generator is only <NUM> volts. The logic circuitry <NUM> may be configured to generate a power-down signal <NUM> providing an indication to power-down the voltage regulator <NUM>. For example, in some embodiments, the logic circuitry <NUM> may assert, or raise the voltage of the power-down signal <NUM> to initiate the power-down of the voltage regulator <NUM>, and de-assert, or set the voltage of the power-down signal <NUM> to <NUM> volts, to enable the voltage regulator <NUM>.

However, in some embodiments, the power-down signal <NUM> may operate in the reduced voltage range provided by the internal supply generator <NUM> (e.g., <NUM> to <NUM> volts). In such an instance, the power-down generator circuit <NUM> may alter the signal to prevent exceeding the maximum tolerable voltage difference across two terminals of any electrical devices when the high voltage source <NUM> is in excess of the maximum tolerable voltage difference across two terminals of the electrical components. For example, in an instance in which the high voltage source <NUM> is <NUM> volts, and the power-down signal <NUM> is <NUM> volts, if the power-down signal was provided directly to the power-down switching device <NUM> where the selected voltage <NUM> was equivalent to the high voltage source <NUM> (e.g., <NUM> volts) then the voltage difference between the gate terminal at the power-down switching device <NUM> and the source terminal may be <NUM> volts which is greater than the maximum tolerable voltage difference across two terminals of the power-down switching device <NUM>. Thus, the power-down generator circuit <NUM> may shift the power domain of the power-down signal <NUM> to be equivalent to the high voltage source <NUM> when the voltage regulator <NUM> is to be disabled, and half of the high voltage source <NUM> when the voltage regulator <NUM> is to be enabled.

As further depicted in <FIG>, the power-down generator circuit <NUM> includes a voltage divider <NUM> comprising a first resistor <NUM> and a second resistor <NUM>. The first resistor <NUM> and the second resistor <NUM> create a voltage divider from which the power-down output signal <NUM> is generated. In some embodiments, the first resistor <NUM> and the second resistor <NUM> may be nearly equivalent. In such an instance, the voltage at the tap <NUM> is half the value of the high voltage source <NUM> when the opposite end of the voltage divider <NUM> is electrically connected to ground. As further depicted in <FIG>, the voltage divider <NUM> is essentially enabled by the power-down signal <NUM> at the second transistor <NUM>. As shown in <FIG>, the second transistor <NUM> is an n-type transistor and is electrically connected between the second resistor <NUM> of the voltage divider <NUM> and ground. In an instance in which the power-down signal <NUM> is low (e.g., <NUM> volts), the second transistor <NUM> is turned off, and the voltage at the high voltage source <NUM> is output as the power-down output signal <NUM>. In such an instance, the power-down output signal <NUM> and the selected voltage <NUM> are both essentially equal to the high voltage source <NUM> and the power-down switching device <NUM> is disabled, allowing the voltage regulator <NUM> to continue to operate. Conversely, in an instance in which the power-down signal <NUM> is high (e.g., <NUM> volts, indicating voltage regulator <NUM> to power down), the second transistor <NUM> is turned on, thus, the voltage divider <NUM> is connected to ground and the voltage divider <NUM> activated. In such an instance, the power-down output signal <NUM> is equivalent to approximately one-half of the high voltage source <NUM>, while the selected voltage <NUM> remains at the high voltage source <NUM>. Thus, the power-down switching device <NUM> is enabled, the high voltage source <NUM> is transmitted through the power-down switching device <NUM> as the regulator gate voltage <NUM>, and the voltage regulator <NUM> is disabled.

As further depicted in <FIG>, the power-down generator circuit <NUM> includes a first transistor <NUM> electrically connected to the first resistor <NUM> at the drain terminal 661a, to the second resistor <NUM> at the source terminal 661c, and to the floating voltage supply <NUM> at the gate terminal 661b. In an instance in which the high voltage source <NUM> exceeds the maximum tolerable voltage difference across two terminals of the electrical components (e.g., second transistor <NUM>), the electrical components may be damaged if the voltage difference across the component is greater than the maximum tolerable voltage difference across two terminals of the component. For example, if the high voltage source is <NUM> volts, and the maximum tolerable voltage difference across two terminals of the second transistor <NUM> is <NUM> volts, if the voltage at the source terminal 663a was allowed to exceed <NUM> volts and the power-down signal <NUM> was held at <NUM> volts, the second transistor <NUM> may be damaged. The purpose of the first transistor <NUM> may be to protect the second transistor <NUM> from such a situation. As depicted in <FIG>, the gate terminal 661b of the first transistor <NUM> is electrically connected to a floating voltage supply <NUM>. The floating voltage supply <NUM> depicted in <FIG> generates a bias voltage based on the voltage of the high voltage source <NUM>. For example, in an instance in which the high voltage source <NUM> exceeds a voltage threshold (e.g., <NUM> volts), the floating voltage supply <NUM> generates a voltage equivalent to one-half of the high voltage source <NUM>. However, when the high voltage source <NUM> is less than or equal to the voltage threshold, the floating voltage supply <NUM> generates a voltage equivalent to the high voltage source. Thus, by biasing the voltage at the gate terminal 661b of the first transistor <NUM> according to the floating voltage supply <NUM>, the voltage at the tap <NUM> and the source of the second transistor <NUM> may be held below the maximum tolerable voltage difference across two terminals of the second transistor <NUM>.

In some embodiments, both the first transistor <NUM> and the second transistor <NUM> may comprise n-type transistors.

As further depicted in <FIG>, the example power-down generator circuit <NUM> includes a conductive path diode <NUM> with the anode electrically connected to the source terminal 661c of the first transistor <NUM>, and the cathode electrically connected to the gate terminal 661b of the first transistor <NUM>. A conductive path diode <NUM> may be any electronic device that allows the flow in only one direction, from the anode to the cathode. As depicted in <FIG>, the conductive path diode <NUM> further protects the second transistor <NUM> by preventing any increase in voltage above the bias voltage of the floating voltage supply <NUM> at the tap <NUM> and/or source terminal 663a of the second transistor <NUM> due to leakage or other factors. Referring now to <FIG>, an example embodiment of a voltage selection circuit <NUM> of a supply voltage independent voltage regulator disable circuit is provided. As depicted in <FIG>, the voltage selection circuit <NUM> is designed using transistors without FDSOI technology. Thus, the bulk terminal 771d of the second transistor <NUM> is electrically connected to the selected voltage <NUM>, and the bulk terminals 770d, 772d of the first and third transistors <NUM>, <NUM> are electrically connected to the selected voltage <NUM>, since the bulk terminal of a non-FDSOI transistor may not be lower than the voltage of the source terminal or the drain terminal on the non-FDSOI transistor. Without the ability to adjust the threshold voltage of the second transistor <NUM> through FDSOI technology, an additional transistor (third transistor <NUM>) is added to create an additional voltage drop from the high voltage source <NUM> across the first transistor <NUM> and the third transistor <NUM>, such that the total voltage drop across the first transistor <NUM> and the third transistor <NUM> is sufficiently greater than the required threshold voltage of the second transistor <NUM>.

As such, the example voltage selection circuit <NUM>, includes a first transistor <NUM> electrically connected in series with a third transistor <NUM> and a first resistor <NUM> between the high voltage source <NUM> and the low voltage source <NUM>. As depicted in <FIG>, the source terminal 770a of the first transistor <NUM> is electrically connected to high voltage source <NUM>, the gate terminal 770b is electrically connected to the drain terminal 770c, and the bulk terminal 770d is electrically connected to the selected voltage <NUM>. Further, the source terminal 772a of the third transistor <NUM> is electrically connected to the drain terminal 770c of the first transistor <NUM>, the gate terminal 772b is electrically connected to the drain terminal 772c, the drain terminal 772c is further electrically connected to the first resistor <NUM>, and the bulk terminal 772d is electrically connected to the selected voltage <NUM>. The first resistor <NUM> is further electrically connected to the low voltage source <NUM>.

As further depicted in <FIG>, the voltage selection circuit <NUM> further includes a second transistor <NUM> electrically connected in series with a second resistor <NUM>, and a third resistor <NUM> between the high voltage source <NUM> and low voltage source <NUM>, and in parallel to the first transistor <NUM>, third transistor <NUM>, and first resistor <NUM>, wherein the voltage at the gate terminal 771b of the second transistor <NUM> is supplied by the voltage at the drain terminal 772c of the third transistor <NUM>.

As further shown in <FIG>, the source terminal 771a of the second transistor <NUM> is electrically connected to the high voltage source <NUM>, the gate terminal 771b is electrically connected to the drain terminal 772c of the third transistor <NUM>, the drain terminal 771c is electrically connected to the second resistor <NUM>, and the bulk terminal 771d is electrically connected to the selected voltage <NUM>. Further, the second resistor <NUM> is further electrically connected to the third resistor <NUM>. As depicted in <FIG>, the selected voltage is generated at the drain terminal 771c of the second transistor <NUM>.

As depicted in <FIG>, the first transistor <NUM>, the third transistor <NUM>, and the first resistor <NUM> essentially act as a voltage divider with a voltage divider tap <NUM> generating the output voltage used to control the second transistor <NUM>. Due to the lack of FDSOI technology, there is less flexibility in control of the threshold voltage using the bulk terminal. Thus, the additional transistor (third transistor <NUM>) is added to ensure the voltage difference between the gate terminal 771b and the source terminal 771a at second transistor <NUM> is high enough to reduce the effective resistance of the second transistor <NUM>.

As further depicted in <FIG>, the bulk terminals of the transistors (770d, 771d, 772d) are electrically connected to the selected voltage <NUM>. Connecting the bulk terminals to the selected voltage <NUM> biases the bulk terminal to avoid forward bias of the transistors, for example, when a voltage is present at low voltage source <NUM> and not at high voltage source <NUM>. In addition to connecting the bulk terminals of the transistors within the voltage selection circuit <NUM> to the selected voltage <NUM>, any transistor connected to the gate terminal of a transistor may be connected to the selected voltage <NUM>. , the bulk terminal of any transistor connected to the gate terminal may be connected to selected voltage <NUM>.

Referring now to <FIG>, an example voltage regulator <NUM> and associated example power-down switching device <NUM> are depicted. As depicted in <FIG>, the gate terminal of the power MOSFET <NUM> of the example voltage regulator <NUM> receives a regulator gate voltage <NUM> based on the selected voltage <NUM> and the power-down output signal <NUM> as received by the power-down switching device <NUM>. Thus, any transistor connected to the gate terminal of the power MOSFET <NUM> may receive the selected voltage <NUM> at the bulk terminal of the transistor. For example, as shown in <FIG>, the last stage of the operational amplifier <NUM> may comprise one or more transistors. As shown, the transistors within the last stage of the operational amplifier <NUM> are powered by the high voltage source <NUM> and thus may additionally receive the selected voltage <NUM> at the bulk terminals of the transistors.

Referring now to <FIG>, an example power management unit (PMU) <NUM> comprising a voltage regulator <NUM> disabled by a regulator gate voltage <NUM> according to one or more embodiments of the present disclosure is provided. As depicted in <FIG>, the example PMU <NUM> includes a transformer <NUM> which may be configured to receive an alternating current (AC) power source <NUM> and transfer the received electrical energy at the proper voltage level to the rectifier <NUM>. The rectifier <NUM> may be configured to receive the altered AC power from the transformer <NUM> and convert the AC power into direct current (DC) power usable by the electronic circuit. As depicted in <FIG>, the PMU <NUM> may further include a filter <NUM> configured to receive DC power from the rectifier <NUM> and generate a clean (noise reduced) DC power source to be transmitted to the voltage regulator <NUM>. As described herein, the voltage regulator <NUM> may receive a DC voltage from the filter <NUM> as a reference voltage (e.g., reference voltage <NUM>). The voltage regulator <NUM> ensures that the DC voltage supplied to the electrical circuit remains stable, despite fluctuations in the AC power source <NUM>. As further described herein, the voltage regulator <NUM> may receive a power-down signal (e.g., regulator gate voltage <NUM>, used to shut off the voltage regulator <NUM>, for example, in an instance in which the low voltage supply is supplied by an external source. The voltage output of the voltage regulator <NUM> is transmitted to a voltage divider <NUM>. The voltage divider <NUM> may be configured to generate one or more lower voltages based on the voltage generated by the voltage regulator <NUM>. The output DC power <NUM> of the voltage divider <NUM> may be utilized as a power source to various electrical components of an electrical device, processor, core logic of a system-on-chip, or other electrical components.

One skilled in the art may recognize that such principles may be applied to any electronic device that utilizes a voltage regulator. For example, a power supply, a battery charger, a mobile device, a system-on-chip, or other similar electrical devices, particularly electrical devices utilizing a high voltage power source.

Claim 1:
An electrical circuit comprising:
a voltage selection circuit (<NUM>) configured to receive a first voltage source (<NUM>) and a second voltage source (<NUM>), and further configured to output a selected voltage (<NUM>), the voltage selection circuit comprising:
a first transistor component (<NUM>) having a first transistor component source (550a), a first transistor component gate (550b), and a first transistor component drain (550c),
wherein the first transistor component source (550a) is electrically connected to the first voltage source (<NUM>), and
wherein the first transistor component gate (550b) is electrically connected to the first transistor component drain (550c);
a second transistor component (<NUM>) having a second transistor component source (551a), a second transistor component gate (551b), and a second transistor component drain (551c),
wherein the second transistor component source (551a) is electrically connected to the first voltage source (<NUM>), and
wherein a second transistor gate voltage at the second transistor component gate (551b) is generated based at least in part on a first transistor component drain voltage at the first transistor component drain (<NUM>),
wherein the selected voltage (<NUM>) is generated based at least in part on a second transistor drain voltage at the second transistor component drain (551c); and
a power-down switching device (<NUM>) configured to generate a regulator gate voltage for a voltage regulator based at least in part on the selected voltage.