Patent Description:
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cells used in the analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

One challenge in VMM systems is the ability to program selected cells with the precision and granularity required for different values of N. For example, if a selected cell can include one of <NUM> different values, extreme precision is required in program operations.

What is needed are improved programming systems and methods suitable for use with a VMM in an analog neuromorphic memory system.

<CIT> discloses that techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

<CIT> discloses that a program verification method is for a nonvolatile memory device which programs a plurality of memory cells. The program verification method includes applying a plurality of verification voltages, and determining whether programming of memory cells, having different target threshold voltage distributions, from among the plurality of memory cells is completed based on one of the plurality of verification voltages.

Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the source region <NUM> (source line terminal) towards the drain region <NUM>. The electrons will accelerate and become heated when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). The erase, programming, and read operations operate in a similar manner to that described previously for memory cell <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

The methods and means described herein may apply to other non-volatile memory technologies such as SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and other volatile synapse cells, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of a system that can be used for that purpose. Vector-by-matrix multiplication (VMM) system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> includes VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT> where w = e (- Vth)/nVt
where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT> Here, wp is w of a reference or peripheral memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>.

Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely <MAT> <MAT> <MAT> Here, wa = w of each memory cell in the memory array.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region:<MAT> Wα (Vgs-Vth), meaning weight W in the linear region is proportional to (Vgs-Vth).

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region:<MAT> Wα (Vgs-Vth)<NUM>, meaning weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation).

Other embodiments for VMM array <NUM> of <FIG> are described in <CIT>. As described in that application, a sourceline or a bitline can be used as the neuron output (current summation output).

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

In VMM array <NUM>, the inputs INPUT<NUM>. , INPUTN are received on bit lines BL<NUM>,. BLN, respectively, and the outputs OUTPUT<NUM>, OUTPUT<NUM>, OUTPUT<NUM>, and OUTPUT<NUM> are generated on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively.

In this example, the inputs INPUT<NUM>, INPUT<NUM>, INPUT<NUM>, and INPUT<NUM> are received on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTN are received on vertical control gate lines CG<NUM>,. , CGN, respectively, and the outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SL<NUM>.

In this example, the inputs INPUT<NUM>,. , INPUTN are received on the gates of bit line control gates <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(N-<NUM>), and <NUM>-N, respectively, which are coupled to bit lines BL<NUM>,. , BLN, respectively. Exemplary outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SL<NUM>.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, and the outputs OUTPUT<NUM>,. , OUTPUTN are generated on bit lines BL<NUM>,. , BLN, respectively.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical source lines SL<NUM>,. , SLN, respectively, where each source line SLi is coupled to the source lines of all memory cells in column i.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical bit lines BL<NUM>,. , BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in column i.

The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.

<FIG> depicts an exemplary LSTM <NUM>. LSTM <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an LSTM with four cells is merely an example.

<FIG> depicts an exemplary implementation of an LSTM cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>. LSTM cell <NUM> receives input vector x(t), cell state vector c(t-<NUM>) from a preceding cell, and output vector h(t-<NUM>) from a preceding cell, and generates cell state vector c(t) and output vector h(f).

LSTM cell <NUM> comprises sigmoid function devices <NUM>, <NUM>, and <NUM>, each of which applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. LSTM cell <NUM> also comprises tanh devices <NUM> and <NUM> to apply a hyperbolic tangent function to an input vector, multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, and addition device <NUM> to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

<FIG> depicts an LSTM cell <NUM>, which is an example of an implementation of LSTM cell <NUM>. For the reader's convenience, the same numbering from LSTM cell <NUM> is used in LSTM cell <NUM>. Sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation circuit blocks <NUM>. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems.

An alternative to LSTM cell <NUM> (and another example of an implementation of LSTM cell <NUM>) is shown in <FIG>. In <FIG>, sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> may share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. LSTM cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, tanh device <NUM> (which comprises activation circuit block <NUM>), register <NUM> to store the value i(t) when i(t) is output from sigmoid function block <NUM>, register <NUM> to store the value f(t) * c(t-<NUM>) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to store the value i(t) * u(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to store the value o(t) * c~(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and multiplexor <NUM>.

Whereas LSTM cell <NUM> contains multiple sets of VMM arrays <NUM> and respective activation function blocks <NUM>, LSTM cell <NUM> contains only one set of VMM = arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of LSTM cell <NUM>. LSTM cell <NUM> will require less space than LSTM <NUM>, as LSTM cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to LSTM cell <NUM>.

It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.

<FIG> depicts an exemplary GRU <NUM>. GRU <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an GRU with four cells is merely an example.

<FIG> depicts an exemplary implementation of a GRU cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> of <FIG>. GRU cell <NUM> receives input vector x(t) and output vector h(t-<NUM>) from a preceding GRU cell and generates output vector h(t). GRU cell <NUM> comprises sigmoid function devices <NUM> and <NUM>, each of which applies a number between <NUM> and <NUM> to components from output vector h(t-<NUM>) and input vector x(t). GRU cell <NUM> also comprises a tanh device <NUM> to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, an addition device <NUM> to add two vectors together, and a complementary device <NUM> to subtract an input from <NUM> to generate an output.

<FIG> depicts a GRU cell <NUM>, which is an example of an implementation of GRU cell <NUM>. For the reader's convenience, the same numbering from GRU cell <NUM> is used in GRU cell <NUM>. As can be seen in <FIG>, sigmoid function devices <NUM> and <NUM>, and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation function blocks <NUM>. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems.

An alternative to GRU cell <NUM> (and another example of an implementation of GRU cell <NUM>) is shown in <FIG>. In <FIG>, GRU cell <NUM> utilizes VMM arrays <NUM> and activation function block <NUM>, which when configured as a sigmoid function applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. In <FIG>, sigmoid function devices <NUM> and <NUM> and tanh device <NUM> share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. GRU cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, complementary device <NUM> to subtract an input from <NUM> to generate an output multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) * r(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) *z(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to hold the value h^(t) * (<NUM>-z(t)) when that value is output from multiplier device <NUM> through multiplexor <NUM>.

Whereas GRU cell <NUM> contains multiple sets of VMM arrays <NUM> and activation function blocks <NUM>, GRU cell <NUM> contains only one set of VMM arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of GRU cell <NUM>. GRU cell <NUM> will require less space than GRU cell <NUM>, as GRU cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to GRU cell <NUM><NUM>.

It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

The input to the VMM arrays can be an analog level, a binary level, timing pulses, or digital bits and the output can be an analog level, a binary level, timing pulses, or digital bits (in this case an output ADC is needed to convert output analog level current or voltage into digital bits).

For each memory cell in a VMM array, each weight w can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> or more cells). In the differential cell case, two memory cells are needed to implement a weight w as a differential weight (w = w+ - w-). In the two blend memory cells, two memory cells are needed to implement a weight w as an average of two cells.

<FIG> depicts programming method <NUM>. First, the method starts (step <NUM>), which typically occurs in response to a program command being received. Next, a mass program operation programs all cells to a '<NUM>' state (step <NUM>). Then a soft erase operation erases all cells to an intermediate weakly erased level such that each cell would draw current of, for example, approximately <NUM>-<NUM>µA during a read operation (step <NUM>). This is in contrast to a deeply erased level where each cell would draw current of approximately ~ <NUM>-<NUM>µA during a read operation. Then, a hard program is performed on all unselected cells to a very deep programmed state to add electrons to the floating gates of the cells (step <NUM>) to ensure that those cells are really "off," meaning that those cells will draw a negligible amount of current during a read operation.

A coarse programming method (to get the cell much closer to the target, for example 2X-100X the target) is then performed on the selected cells (step <NUM>), followed by a precision programming method on the selected cells (step <NUM>) to program the precise value desired for each selected cell.

<FIG> depicts another programming method <NUM>, which is similar to programming method <NUM>. However, instead of a program operation to program all cells to a '<NUM>' state as in step <NUM> of <FIG>, after the method start (step <NUM>), an erase operation is used to erase all cells to a '<NUM>' state (step <NUM>). Then a soft program operation (step <NUM>) is used to program all cells to an intermediate state (level) such that each cell would draw current of approximately <NUM>-5uA during a read operation. Afterward, coarse and precision programming method would follow as in <FIG>. A variation of the embodiment of <FIG> would remove the soft programing method (step <NUM>) altogether.

<FIG> depicts a first embodiment of coarse programming method <NUM>, which is search and execute method <NUM>. First, a lookup table search is performed to determine a coarse target current value (ICT) for the selected cell based on the value that is intended to be stored in that selected cell (step <NUM>). This table is, for example, created by silicon characterization or from calibration from wafer testing. It is assumed that the selected cell can be programmed to store one of N possible values (e.g., <NUM>, <NUM>, <NUM>, etc.). Each of the N values would correspond to a different desired current value (ID) that is drawn by the selected cell during a read operation. In one embodiment, a look-up table might contain M possible current values to use as the coarse target current value ICT for the selected cell during search and execute method <NUM>, where M is an integer less than N. For example, if N is <NUM>, then M might be <NUM>, meaning that there are <NUM> possible values that the selected cell can store, and one of <NUM> coarse target current values will be selected as the coarse target for search and execute method <NUM>. That is, search and execute method <NUM> (which again is an embodiment of coarse programming method <NUM>) is intended to quickly program the selected cell to a value (ICT) that is somewhat close to the desired value (ID), and then the precision programming method <NUM> is intended to more precisely program the selected cell to be extremely close to the desired value (ID).

Examples of cell values, desired current values, and coarse target current values are depicted in Tables <NUM> and <NUM> for the simple example of N=<NUM> and M=<NUM>:.

The offset values ICTOFFSETx are used to prevent overshooting the desired current value during coarse tuning.

Once the coarse target current value ICT is selected, the selected cell is programmed by applying the voltage v<NUM> to the appropriate terminal of selected cell based on the cell architecture type of the selected cell (e.g., memory cells <NUM>, <NUM>, <NUM>, or <NUM>) (step <NUM>). If the selected cell is of type memory cell <NUM> in <FIG>, then the voltage v<NUM> will be applied to control gate terminal <NUM>, and v<NUM> might be <NUM>-7V depending on coarse target current value ICT. The value of v<NUM> optionally can be determined from a voltage look up table that stores v<NUM> vs. coarse target current value Icr.

Next, the selected cell is programmed by applying the voltage vi = vi-<NUM>+vincrement, where i starts at <NUM> and increments each time this step is repeated, and where vincrement is a small, fine voltage that will cause a degree of programming that is appropriate for the granularity of change desired (step <NUM>). Thus, the first time step <NUM> is performed, i=<NUM>, and v<NUM> will be v<NUM> + vincrement. Then a verify operation occurs (step <NUM>), wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured. If Icell is less than or equal to ICT (which here is a first threshold value), then search and execute method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to ICT, then step <NUM> is repeated, and i is incremented.

Thus, at the point when coarse programming method <NUM> ends and precision programming method <NUM> begins, the voltage vi will be the last voltage used to program the selected cell, and the selected cell will be storing a value associated with the coarse target current value ICT. The goal of precision programming method <NUM> is to program the selected cell to the point where during a read operation it draws a current ID (plus or minus an acceptable amount of deviation, such as +/-<NUM> pA or +/-<NUM>% or less), which is the desired current value that is associated with the value that is intended to be stored in the selected cell.

<FIG> depicts examples of different voltage progressions that can be applied to the control gate of a selected memory cell during coarse and/or precision program method <NUM>.

Under a first approach, increasing voltages are applied in progression to the control gate to further program the selected memory cell. The starting point is vi, which is the last voltage applied during coarse programming method <NUM>. An increment of vp1 is added to v<NUM> and the voltage v<NUM> + vp1 is then used to program the selected cell (indicated by the second pulse from the left in progression <NUM>). vp1 is an increment that is smaller than vincrement (the voltage increment used during coarse programming method <NUM>). After each programming voltage is applied, a verify step (similar to step <NUM>) is performed, where a determination is made if Icell is less than or equal to IPT1 (which is the first precision target current value and here is a second threshold value), where IPT1 = ID + IPT1OFFSET, where IPT1OFFSET is an offset valued added to prevent program overshoot. If it is not, then another increment vp1 is added to the previously-applied programming voltage, and the process is repeated. At the point where Icell is less than or equal to IPT1, then this portion of the programming sequence stops. Optionally, if IPT1 is equal to ID, or almost equal to ID with sufficient precision, then the selected memory cell has been successfully programmed.

If IPT1 is not close enough to ID, then further programming of a smaller granularity can occur. Here, progression <NUM> is now used. The starting point for progression <NUM> is the last voltage used for programming under progression <NUM>. A increment of Vp2 (which is smaller than vp1) is added to that voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verify step (similar to step <NUM>) is performed, where a determination is made if Icell is less than or equal to IPT2 (which is the second precision target current value and here is a third threshold value), where IPT2= ID + IPT2OFFSET, IPT2OFFSET is an offset value added to prevent program overshoot. If it is not, then another increment Vp2 is added to the previously-applied programming voltage, and the process is repeated. At the point where Icell is less than or equal to IPT2, then this portion of the programming sequence stops. Here, it is assumed that IPT2 is equal to ID or close enough to ID that the programming can stop, since the target value has been achieved with sufficient precision. One of ordinary skill in the art can appreciate that additional progressions can be applied with smaller and smaller programming increments used. For example, in <FIG>, three progressions (<NUM>, <NUM>, and <NUM>) are applied instead of just two.

A second approach is shown in progression <NUM>. Here, instead of increasing the voltage applied during the programming of the selected memory cell, the same voltage is applied for durations of increasing period. Instead of adding an incremental voltage such as vp1 in progression <NUM> and Vp2 in progression <NUM>, an additional increment of time tp1 is added to the programming pulse such that each applied pulse is longer than the previously-applied pulse by tp1. After each programming pulse is applied, the same verify step is performed as described previously for progression <NUM>. Optionally, additional progressions can be applied where the additional increment of time added to the programming pulse is of a smaller duration than the previous progression used. Although only one temporal progression is shown, one of ordinary skill in the art will appreciate that any number of different temporal progressions can be applied.

Additional detail will now be provided for three additional coarse programming methods <NUM>.

<FIG> depicts a first example of coarse programming method <NUM>, which does not fall under the scope of the appended claims and is adaptive calibration method <NUM>. The method starts (step <NUM>). The cell is programmed at a default start value v<NUM> (step <NUM>). Unlike in search and execute method <NUM>, here v<NUM> is not derived from a lookup table, and instead can be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100na) and a second current value IR2 (e.g., 10na), and a sub-threshold slope is determined based on those measurements (e.g., 360mV/dec) and stored (step <NUM>).

A new desired voltage, vi, is determined. The first time this step is performed, i=<NUM>, and v<NUM> is determined based on the stored sub-threshold slope value and a current target and offset value using a sub-threshold equation, such as the following: <MAT> vincrement is proportional to slope of Vg <MAT> Here, wa is w of a memory cell, Ids is the current target plusoffset value.

If the stored slope value is relatively steep, then a relatively small current offset value can be used. If the stored slope value is relatively flat, then a relatively high current offset value can be used. Thus, determining the slope information will allow for a current offset value to be selected that is customized for the particular cell in question. This ultimately will make the programming process shorter. When this step is repeated, i is incremented, and vi = vi-<NUM> + vincrement. The cell is then programmed using vi. vincrement can be determined from a lookup table storing values of vincrement. vs. target current value.

Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured (step <NUM>). If Icell is less than or equal to ICT (which here is a coarse target threshold value), where ICT is set = ID + ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, then adaptive calibration method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to ICT, then steps <NUM>-<NUM> are repeated, and i is incremented.

<FIG> depicts aspects of adaptive calibration method <NUM>. During step <NUM>, current source <NUM> is used to apply the exemplary current values IR1 and IR2 to the selected cell (here, memory cell <NUM>), and the voltage (CGR1 for IR1 and CGR2 for IR2) at the control gate of memory cell <NUM> is then measured. The slope will be (CGR2-CGR1)/dec.

<FIG> depicts the inventive programming method <NUM>, which is adaptive calibration method <NUM>. The method starts (step <NUM>). The cell is programmed at a default start value V<NUM> (step <NUM>). V<NUM> is derived from a lookup table such as created from silicon characterization, the table value is offset such as not to overshoot the programmed target.

In next step <NUM> a I-V slope parameter is created which is used in predicting the next programming voltage, a first control gate read voltage, VCGR1, is applied to the selected cell, and the resulting cell current, IR<NUM>, is measured. Then a second control gate read voltage, VCGR2, is applied to the selected cell, and the resulting cell current, IR<NUM>, is measured. A slope is determined based on those measurements and stored, for example as according to the equation in sub threshold region (cell operating in sub threshold): <MAT> (step <NUM>). Examples of values for VCGR1 and VCGR2 are <NUM>. 5V and <NUM>. 3V, respectively.

Determining the slope information allows for a vincrement value to be selected that is customized for the particular cell in question. This ultimately will make the programming process shorter.

When step <NUM> is repeated, i is incremented, a new desired programming voltage, Vi, is determined based on the stored slope value and a current target and offset value using an equation such as the following: <MAT> where for i-<NUM>, vincrement = alpha* slope * (LOG (IR<NUM>) - LOG (IcT)),
where ICT is the target current and alpha is a pre-determined constant < <NUM> (programming offset value) to prevent overshoot, e.g., <NUM>. For example Vi is VSLP or VCGP, source line or control gate programming voltage.

The cell is then programmed using Vi. (step <NUM>).

Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured (step <NUM>). If Icell is less than or equal to ICT (which here is a coarse target threshold value), where ICT is set = ID + ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, then the process proceeds to the step <NUM>. If not, then the process returns to step <NUM> and i is incremented.

In step <NUM>, Icell is compared against a threshold value, CT2, that is smaller than ICT. The purpose of this is to see if an overshoot has occurred. That is, although the goal is for Icell to be below ICT, if it falls too far below ICT, then an overshoot has occurred and the stored value may actually correspond to the wrong value. If Icell is not less than or equal to ICT2, then no overshoot has occurred, and adaptive calibration method <NUM> has completed, as which point the process progresses to precision programming method <NUM>. If Icell is less than or equal to ICT2, then an overshoot has occurred. The selected cell is then erased (step <NUM>), and the programming process starts over at step <NUM>. Optionally, if step <NUM> is performed more than a predetermined number of times, the selected cell can be deemed a bad cell that should not be used.

The precision program method <NUM> is such as consisting of multiple verify and program cycles, in which the program voltage is incremented by a constant fine voltage with a fixed pulse width or in which the program voltage is fixed and the program pulse width is varied or constant for next pulses.

Optionally, the step of determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value can be performed by applying a fixed bias to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current.

Optionally, the step of determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value can be performed by applying an input to a terminal of the non-volatile memory cell, modulating the current drawn by the selected non-volatile memory cell with an output pulse to generate a modulated output, digitizing the modulated output to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current.

<FIG> depicts a third example of programming method <NUM>, which does not fall under the scope of the appended claims and is absolute calibration method <NUM>. The method starts (step <NUM>). The cell is programmed at a default starting value V<NUM> (step <NUM>). The control gate voltage of the cell (VCGRx) is measured at a current value Itarget and stored (step <NUM>). A new desired voltage, v<NUM>, is determined based on the stored control gate voltage and a current target and offset value, Ioffset+Itarget (step <NUM>). For example, the new desired voltage, v<NUM>, can be calculated as follows: v<NUM>= v<NUM> + (VCGBIAS - stored VCGR), where VCGBIAS =~ <NUM>. 5V, which is the default read control gate voltage at a maximum target current and stored VCGR is the measured read control gate voltage of step <NUM>.

The cell is then programmed using vi. When i=<NUM>, the voltage v<NUM> from step <NUM> is used. When i>=<NUM>, the voltage vi = vi-<NUM> + Vincrement is used. vincrement can be determined from a lookup table storing values of vincrement. vs. target current value. Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured (step <NUM>). If Icell is less than or equal to ICT (which here is a threshold value), then absolute calibration method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to ICT, then steps <NUM>-<NUM> are repeated, and i is incremented.

<FIG> depicts circuit <NUM> for implementing step <NUM> of absolute calibration method <NUM>. A voltage source (not shown) generates VCGR, which begins at an initial voltage and ramps upward. Here, n+<NUM> different current sources <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n) generate different currents IO0, IO1, IO2,. IOn of increasing magnitude. Each current source <NUM> is connected to inverter <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n) and memory cell <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. As VCGR ramps upward, each memory cell <NUM> draws increasing amounts of current, and the input voltage to each inverter <NUM> decreases. Because IO0 < IO1 < IO2 <. < IOn, the output of inverter <NUM>-<NUM> will switch from low to high first as VCGR increases. The output of inverter <NUM>-<NUM> will switch from low to high next, then the output of inverter <NUM>-<NUM>, and so on, until the output of inverter <NUM>-n switches from low to high. Each inverter <NUM> controls switch <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n), such that when the output of inverter <NUM> is high, switch <NUM> is closed, which will cause VCGR to be sampled by capacitor <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n). Thus, switch <NUM> and capacitor <NUM> form a sample-and-hold circuit. The values of IO0, IO1, IO2,. , IOn are used as possible values of Itarget and the respective sampled voltage is used as the associated value VCGRx in absolute calibration method <NUM> of <FIG>. Graph <NUM> shows VCGR ramping upward over time, and the outputs of inverters <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-n switching from low to high at various times.

<FIG> depicts exemplary progression <NUM> for programming a selected cell during adaptive calibration method <NUM> or absolute calibration method <NUM>. In one embodiment, the voltage Vcgp is applied to the control gates of a selected row of memory cells. The number of selected memory cells in the selected row is for example = <NUM> cells. Hence, up to <NUM> memory cells in a selected row can be programmed in parallel. Each memory cell is enabled to couple to a programming current Iprog by a bitline enable signal. If the bitline enable signal is inactive (meaning a positive voltage being applied to selected bitline), the memory cell is inhibited (not being programmed). As shown in <FIG>, bitline enabling signal En_blx (where x varies between <NUM> and n, where n is the number of bit lines) is enabled at different time with a Vcgp voltage level desired for that bitline (hence for selected memory on said bitline). In another embodiment, the voltage applied to the control gate of the selected cell can be controlled using enable signals on the bitline. Each bitline enable signal causes a desired voltage (such as vi described in <FIG>) corresponding to that bitline to be applied as Vcgp. The bitline enable signal may also control the programming current flowing into the bitline. In this example, each subsequent control gate voltage Vcgp is higher than the previous voltage. Alternatively, each subsequent control gate voltage can be lower or higher than the previous voltage. Each subsequent increment in Vcgp can either be equal or not equal to the previous increment.

<FIG> depicts exemplary progression <NUM> for programming a selected cell during adaptive calibration method <NUM> or absolute calibration method <NUM>. In one embodiment, bitline enable signal enables the selected bitline (meaning selected memory cell in said bitline) to be programmed with corresponding Vcgp voltage level. In another embodiment, the voltage applied to the increment ramping control gate of the selected cell can be controlled using bitline enable signals. Each bitline enable signal causes a desired voltage (such as vi described in <FIG>) corresponding to that bitline to be applied to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

<FIG> depicts a system for implementing the input and output method for reading or verifying with a VMM array. The input function circuit <NUM> receives digital bit values and converts those digital values into an analog signal that is then used to apply a voltage to the control gate of selected cells in array <NUM>, which is determined through control gate decoder <NUM>. Meanwhile, word line decoder <NUM> also is used to select the row in which the selected cell is located. Output neuron circuit block <NUM> performs an output action of each column (neuron) of cells in array <NUM>. The output circuit block <NUM> can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation (SAR) ADC, a Sigma-Delta ADC, or any other ADC schemes.

In one embodiment, the digital values provided to input function circuit <NUM> comprise four bits (DIN3, DIN2, DIN1, and DINO) as an example, and the various bit values correspond to different numbers of input pulses applied to the control gate. A greater number of pulses will cause a greater output value (current) of the cell. An example of bit values and pulse values is shown in Table No. <NUM>:.

In the above example, there are a maximum of <NUM> pulses for <NUM> bit digital values for reading out the cell value. Each pulse is equal to one unit cell value (current). For example, if Icell unit = 1nA, then for DIN[<NUM>-<NUM>] = <NUM>, Icell = <NUM>*1nA = 1nA,; and for DIN[<NUM>-<NUM>] = <NUM>, Icell = <NUM>*1nA = 15nA.

In another embodiment, the digital bit input uses digital bit position summation to read out the cell or neuron (e.g., value on bitline output) value as shown in Table <NUM>. Here, only <NUM> pulses or <NUM> fixed same bias input (for example input on wordline or control gate) are needed to evaluate the <NUM> bit digital value. For example, a first pulse or a first fixed bias is used to evaluate DIN0, a second pulse or a second fixed bias with same value as the first one is used to evaluate DIN1, a third pulse or a third fixed bias with same value as the first one is used to evaluate DIN2, and a fourth pulse or a fourth fixed bias with same value as the first one is used to evaluate DIN3. Then, the results from the four pulses are summed according to bit position with each output result multiplied (scaled) by a multiplier factor that is <NUM>^n, n is the digital bit position as shown in Table <NUM>. The digital bit summation equation realized is the following: Output =<NUM>^<NUM>*DIN0 + <NUM>^<NUM>*DIN1 + <NUM>^<NUM>*DIN2 + <NUM>^<NUM>*DIN3)*Icell unit.

For example, if Icell unit = 1nA, then for DIN[<NUM>-<NUM>] = <NUM>, Icell total = <NUM>+<NUM>+<NUM>+<NUM>* 1nA = 1nA; and for DIN[<NUM>-<NUM>] = <NUM>, Icell total = <NUM>*1nA + <NUM>*1nA + <NUM>*1nA + <NUM>*1nA =26nA.

Another embodiment with a hybrid input with multiple digital input pulse ranges and input digital range summations is shown in Table <NUM> for an exemplary <NUM>-bit digital inputIn this embodiment, DINn-<NUM> can be divided into m different groups, where each group is evaluated and the output is scaled by a multiplication factor by the group binary position. As example, for <NUM>-bit DIN3-<NUM>, the groups can be DIN3-<NUM> and DIN1-<NUM>, where the output for DIN1-<NUM> is scaled by one (X1) and the output for DIN3-<NUM> is scaled by <NUM> (X4).

Another embodiment combines a hybrid input range with a hybrid supercell. A hybrid super cells includes multiple physical x-bit cells to implement a logical n-bit cell with the x-cell output scaled by the <NUM>^n binary position. For example, to implement an <NUM>-bit logical cell, two <NUM>-bit cells (cell1,cell0) are used. The output for cell0 is scaled by one (X1) and the output for cell1 is scaled by four (X, <NUM>^<NUM>). Other combinations of physical x-cells to implement n-bit logical cell are possible such as two <NUM>-bit physical cell and one <NUM>-bit physical cell to implement <NUM>-bit logical cell.

<FIG> depicts another embodiment, similar to the system of <FIG>, except that the digital bit input uses digital bit position summation to read out the cell or neuron (e.g., value on bitline output) current modulated by modulator <NUM> with the output pulsewidth that is designed according to the digital input bit position (e.g. to convert current into output voltage V = Current*Pulswidth/Capacitance). For example, a first bias (applied on the input like wordline or control gate) is used to evaluate DIN0, the current (cell or neuron) output is modulated by modulator <NUM> by a unit pulsewidth that is proportional to the DIN0 bit position, which is one (x1) unit, a second input bias is used to evaluate DIN1, the current output is modulated by modulator <NUM> by a pulsewidth that is proportional to the DIN1 bit position, which is two (x2) units, a third input bias is used to evaluate DIN2, the current output is modulated by modulator <NUM> by a pulsewidth that is proportional to the DIN2 bit position, which is four (x4) units, a fourth input bias is used to evaluate DIN3, the current output is modulated by modulator <NUM> by a pulsewidth that is proportional to the DIN3 bit position, which is eight (x8) units. Each converted voltage is then converted into digital bits by ADC (Analog-to-Digital converter) <NUM> for each digital input bits. The total output is then output by summer <NUM> as the summation of the four digital outputs generated from DIN0-<NUM> inputs.

<FIG> depicts an example of charge summer <NUM> that can be used to sum the output of a VMM during a verify operation or during output neuron analog to digital conversion to obtain a single analog value that represents the output, and that can optionally be then converted into digital bit values. Charge summer <NUM> can be used, for example, as summer <NUM>. Charge summer <NUM> comprises current source <NUM> and a sample-and-hold circuit comprising switch <NUM> and sample-and-hold (S/H) capacitor <NUM>. As shown for an example of a <NUM>-bit digital value, there are <NUM>/H circuits to hold the value from <NUM> evaluation pulses, where the values are summed up at the end of the process. S/H capacitors <NUM> are selected with ratios that are associated with the <NUM>^n*DINn bit position for that S/H capacitor; for example C_DIN3 = x8 Cu, C_DIN2 = x4 Cu, C_DIN1 = x2 Cu, DIN0 = x1 Cu. The current source <NUM> is also ratioed accordingly.

<FIG> depicts current summer <NUM> that can be used to sum the output of a VMM during a verify operation or during output neuron analog to digital conversion. Current summer <NUM> comprises current source <NUM>, switch <NUM>, switches <NUM> and <NUM>, and switch <NUM>. As shown for an example of a <NUM>-bit digital value, there are current source circuits to hold the value from <NUM> evaluation pulses, where the values are summed up at the end of the process. The current source is ratioed based on the <NUM>^n*DINn bit position; for example, I_DIN3 = x8 Icell unit, _I_DIN2 = x4 Icell unit, I_DIN1 = x2 Icell unit, I_DIN0 = x1 Icell unit.

<FIG> depicts digital summer <NUM>, which receives a plurality of digital values, sums them together and generates an output DOUT representing the sum of the inputs. Digital summer <NUM> can be used during a verify operation or during output neuron analog to digital conversion. As shown for an example of a <NUM>-bit digital value, there are digital output bits to hold the value from <NUM> evaluation pulses, where the values are summed up at the end of the process. The digital outputs are digitally scaled based on the <NUM>^n*DINn bit position;, for example, DOUT3 = x8 DOUT0, _DOUT2 = x4 DOUT1, I_DOUT1 = x2 DOUT0, I_DOUT0 = DOUT0.

<FIG> shows an integrating dual-slope ADC <NUM> applied to an output neuron to convert the cell current into digital output bits. An integrator consisting of integrating op-amp <NUM> and integrating capacitor <NUM> integrates a cell current ICELL versus a reference current IREF. As shown in <FIG>, during a fixed time t1, the cell current is up integrated (Vout rises), and then a reference current is applied to down integrated for a time t2 (Vout falls). The current Icell is = t2/t1* IREF. For example, for t1, for <NUM> bit digital bits resolution, <NUM> cycles are used, and the cycle number for t2 varies from <NUM> to <NUM> cycles depending on the Icell value.

<FIG> shows integrating single slope ADC <NUM> applied to an output neuron to convert the cell current into digital output bits. An integrator consisting of integrating op-amp <NUM> and integrating capacitor <NUM> integrates a cell current ICELL. As shown in <FIG>, during a time t1, a cell current is up integrated (Vout rises until it reaches Vref2), and during time t2, another cell current is up integrated. The cell current I cell = Cint*Vref2/t. A pulse counter is used to count the number of pulses (digital output bits) during integration time t. For example as shown digital output bits for t1 is less than that of t2, meaning the cell current during t1 is larger the cell current during t2 integration. An initial calibration is done to calibrate the integrating capacitor value with a reference current and a fixed time, Cint = Tref*Iref/Vref2.

<FIG> shows integrating dual slope ADC <NUM> applied to an output neuron to convert the cell current into digital output bits. The integrating dual slope ADC <NUM> does not utilize an integrating op-amp. The cell current or the reference current is integrated directly on the capacitor <NUM>. A pulse counter is used to count pulses (digital output bits) during integration time. The current Icell is = t2/t1* IREF.

<FIG> shows integrating single slope ADC <NUM> applied to an output neuron to convert the cell current into digital output bits. The integrating single slope ADC <NUM> does not utilize an integrating op-amp. The cell current is integrated directly on the capacitor <NUM>. A pulse counter is used to count pulses (digital output bits) during integration time. The cell current I cell = Cint*Vref2/t.

<FIG> shows a SAR (Successive Approximation Register) ADC applied to an output neuron to convert a cell current into digital output bits. Cell current can be dropped across a resistor to convert into a VCELL. Alternatively, the cell current can charge up a S/H capacitor to convert into a VCELL. A binary search is used to compute the bit starting from MSB bit (most significant bit). Basing on the digital bits from SAR <NUM>, DAC <NUM> is used to set appropriate analog reference voltage to comparator <NUM>. The output of the comparator <NUM> in turns feedback to SAR <NUM> to choose the next analog level. As shown in <FIG>, for the example of <NUM>-bit digital output bits, there are <NUM> evaluation periods: a first pulse to evaluate DOUT3 by setting an analog level half-way, then a second pulse to evaluate DOUT2 by setting an analog level half way of the top-half or half way of the bottom-half, etc..

A Modified Binary Search such as a cyclic (algorithmic) ADC can be used for the cell tuning (e.g., programming) verification or the output neuron conversion. A Modified Binary Search such as a switched cap (SC) charge re-distribution ADC can be used for the cell tuning (e.g., programming) verification or the output neuron conversion.

<FIG> shows sigma delta ADC <NUM> applied to an output neuron to convert a cell current into digital output bits. An integrator consisting of op-amp <NUM> and capacitor <NUM> integrates the summation of current from a selected cell current and a reference current resulting from <NUM>-bit current DAC <NUM>. A comparator <NUM> compares integrating output voltage versus a reference voltage. The clocked DFF <NUM> provides digital output streams depending on the output of the comparator <NUM>. The digital output stream typically goes to a digital filter before outputting into digital output bits.

<FIG> depicts ramp analog-to-digital converter <NUM>, which comprises current source <NUM> (which represents a received neuron current, Ineu), switch <NUM>, variable configurable capacitor <NUM>, and comparator <NUM>, which receives the voltage developed across variable configurable capacitor <NUM>, denoted Vneu, as the non-inverting input and configurable reference voltage Vreframp as the inverting input and generates output Cout. Vreframp is ramped up in discrete levels with each comparison clock cycle. Comparator <NUM> compares Vneu against Vreframp, and as a result output Cout will be "<NUM>" when Vneu>Vreframp and will be "<NUM>" otherwise. Thus, output Cout will be a pulse, whose width varies in response to Ineu. A larger Ineu will cause Cout to be "<NUM>" for a longer period of time, resulting in a wider pulse for output Cout. A digital counter <NUM> converts each pulse of output Cout into digital output bits as shown in <FIG> for two different Ineu currents, denoted OT1A and OT2A, respectively. Alternatively ramp voltage Vreframp is a continuous ramp voltage <NUM> as shown in graph <NUM> of <FIG>. A multi-ramp embodiment is shown in <FIG> for reducing the conversion time by utilizing a coarse-fine ramp conversion algorithm. First coarse reference ramp reference voltage <NUM> is ramped in a fast manner to figure out the sub range for each Ineu. Next, fine reference ramp reference voltages <NUM>, i.e. Vreframp1 and Vreframp2, are used respectively for each sub-range for converting Ineu. currents within the respective sub-range. As shown there are two sub-ranges for fine reference ramp voltages. More than two coarse/fine steps or two sub-ranges are possible.

<FIG> depicts algorithmic analog-to-digital output converter <NUM>, which comprises switch <NUM>, switch <NUM>, sample-and-hold (S/H) circuit <NUM>, <NUM> bit analog-to-digital converter (ADC) <NUM>, <NUM> bit digital-to-analog converter (DAC) <NUM>, summer <NUM>, and gain of two residue operational amplifier (2x opamp) <NUM>. Algorithmic analog-to-digital output converter <NUM> generates conversion digital output <NUM> in response to analog input Vin and control signals applied to switches <NUM> and <NUM>. An input received at analog input Vin (e.g. Vneu in <FIG>) is sampled first by the S/H circuit <NUM> by the switch <NUM>, then conversion is performed in N clock cycles for N bits. For each conversion clock cycle, the <NUM>-bit ADC <NUM> compares the S/H voltage <NUM> against a reference voltage (e.g., VREF/<NUM>, with VREF is full scale voltage for N bits) and outputs a digital bit (e.g., a "<NUM>" if input <=VREF/<NUM> and a "<NUM>" if input > VREF/<NUM>). This digital bit, which is the Digital Output signal <NUM>, is in turn converted into an analog voltage by the <NUM>-bit DAC <NUM> (e.g. to either VREF/<NUM> or 0V) and feed to the summer <NUM> to be subtracted from the S/H voltage <NUM>. The 2x residue opamp <NUM> then amplifies the summer difference voltage output into a conversion residue voltage <NUM> which is fed to the S/H circuits <NUM> through the switch <NUM> for next clock cycle. Instead of this <NUM>-bit (i.e., <NUM> levels) algorithmic ADC, a <NUM>-bit (i.e., <NUM> levels) algorithmic ADC can be used to reduce the effect of offset such as from ADC <NUM> and residue opamp <NUM>. A <NUM>-bit or <NUM>-bit (i.e., <NUM> levels) DAC is required for the <NUM>-bit algorithmic ADC.

In another embodiment, a hybrid ADC can be used. For example, for a <NUM>-bit ADC, the first <NUM> bits can be generated by a SAR ADC and the remaining <NUM> bits can be generated using a slope ADC or a ramp ADC.

Claim 1:
A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than <NUM>, the selected non-volatile memory cell comprising a floating gate and a control gate, the method comprising:
performing a coarse programming process (<NUM>) comprising:
programming the non-volatile memory cell with an initial programming voltage (<NUM>);
applying a first voltage (VCGR1) to the control gate of the selected non-volatile memory cell and measuring a first current (IR1) that results through the selected non-volatile memory cell (<NUM>);
applying a second voltage (VCGR2) to the control gate of the selected non-volatile memory cell and measuring a second current (IR2) that results through the selected non-volatile memory cell (<NUM>);
determining a slope value based on the first voltage, the second voltage, the first current, and the second current according to the equation (first voltage - second voltage) / (LOG(first current) - LOG(second current)) (<NUM>);
determining a next programming voltage based on the slope value (<NUM>);
programming the non-volatile memory cell with the next programming voltage (<NUM>);
repeating the steps of determining a next programming voltage and programming the non-volatile memory cell with the next programming voltage until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value (ICT, <NUM>);
when a current through the selected non-volatile memory cell is less than or equal to a second threshold current value (ICT, <NUM>) smaller than the first threshold current value, erasing the selected non-volatile memory cell (<NUM>) and repeating the coarse programming process; and
performing a precision programming process until a current through the selected non-volatile memory cell during a read or verify operation is the target current (ID) within an acceptable deviation range (<NUM>).