Patent Description:
The ever-increasing complexity and performance requirements of portable media devices call for effective system-level power management in integrated circuits (ICs). Having one or more switchable power-domains in core-logic is a well-known low-power methodology that is employed for ICs in portable media devices. When a supply of a specific power domain is powered down, the outputs of that power-domain serving as inputs to IO (input/output) circuits are no longer valid, and these IO circuits are tri-stated to avoid possible leakage current. An IO circuit drives and receives signals on a PAD to interface with the outside world. If the IO circuit is not properly tri-stated, it results in high leakage currents (conduction currents) from the PAD into the IO circuit. A similar condition results when the IO supply voltage is powered up or down, while the PAD is held at a logical high state. Serial low-power inter-chip media bus (SLIMbus) is a standard interface between baseband or application processors and peripheral components in portable media devices. The SLIMbus is a failsafe interface and specifies that devices have ultra low PAD current (or pin current) while powering up, while powering down, and while having a stable power state in portable media devices.

<CIT> relates to multiple supply-voltage power up and down detectors.

In described examples of an input/output (IO) circuit powered by an input/output (IO) supply voltage, a supply detector cell detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell control a leakage current from the PAD according to independent claim <NUM>.

<FIG> is a block diagram of a supply detector cell <NUM>. The supply detector cell <NUM> is powered by an input/output (IO) supply voltage (VDDS) <NUM> and receives a core supply voltage (VDD) <NUM> as an input signal. A diode connected transistor <NUM> is powered by the IO supply voltage (VDDS) <NUM>. In at least one example, the diode connected transistor <NUM> is an NMOS transistor or a PMOS transistor. An input inverter stage <NUM> is coupled to the diode connected transistor <NUM>. The input inverter stage <NUM> receives the core supply voltage (VDD) <NUM>. A second inverter stage <NUM> receives an output of the input inverter stage <NUM> and is powered by the IO supply voltage (VDDS) <NUM>. A pair of weak keeper transistors <NUM> is coupled to an output of the second inverter stage <NUM>. The weak keeper transistors <NUM> are connected in series and powered by the IO supply voltage (VDDS) <NUM>. An output of the pair of weak keeper transistors <NUM> is provided as input to the second inverter stage <NUM>, which is also the output of the input inverter stage <NUM>. An output inverter stage <NUM> is coupled to the second inverter stage <NUM> and generates a supply detect signal <NUM>. The output inverter stage <NUM> is powered by the IO supply voltage (VDDS) <NUM>.

The supply detector cell <NUM> is configured to detect the core supply voltage (VDD) <NUM> and generate the supply detect signal <NUM>. When the core supply voltage (VDD) <NUM> is in OFF state, and IO supply voltage (VDDS) <NUM> is ramping up, the diode connected transistor <NUM> is turned ON. Accordingly, the output of the input inverter stage <NUM> is (IO supply voltage (VDDS)-Vtn). Vtn is a threshold voltage of diode connected transistor <NUM>. The output of the input inverter stage <NUM> (IO supply voltage (VDDS)-Vtn), which is a weak logic-HIGH, is inverted by the second inverter stage <NUM>. Accordingly, the output of the second inverter stage <NUM> becomes weak logic-LOW. In response to receiving this weak logic-LOW signal, the pair of weak keeper transistors <NUM> pull the output of the input inverter stage <NUM> to an IO supply voltage (VDDS) level from (VDDS -Vtn). This provides for zero static leakage current in the second inverter stage <NUM>, because a logic-HIGH signal is now provided to the second inverter stage <NUM>. This logic-HIGH signal received at the second inverter stage <NUM> results in a logic-LOW signal at the output of the second inverter stage <NUM>. The logic-LOW signal output of the second inverter stage <NUM> is provided as input to the output inverter stage <NUM>, which results in a logic-HIGH supply detect signal <NUM>. Accordingly, the output inverter stage <NUM> buffers the output of the input inverter stage <NUM>.

<FIG> is a schematic of a supply detector cell <NUM>. The supply detector cell <NUM> is similar in connections and operation to supply detector cell <NUM>. The supply detector cell <NUM> is powered by an input/output (IO) supply voltage (VDDS) <NUM> and receives a core supply voltage (VDD) <NUM>. A diode connected NMOS transistor <NUM> is powered by the IO supply voltage (VDDS) <NUM>. The diode connected NMOS transistor <NUM> includes a gate terminal <NUM> and a drain terminal 206D connected to the IO supply voltage (VDDS) <NUM>. In one embodiment, the diode connected NMOS transistor <NUM> is a PMOS transistor. An input inverter stage <NUM> is coupled to the diode connected NMOS transistor <NUM>. The input inverter stage <NUM> includes a PMOS transistor 208a and two NMOS transistors 208b and 208c connected in series. Gate terminals 208aG, 208bG and 208cG of the three transistors 208a, 208b and 208c respectively receive the core supply voltage (VDD) <NUM>. Drain terminals 208aD and 208bD of the respective transistors <NUM> a and 208b are combined to generate an output of the input inverter stage <NUM>. A second inverter stage <NUM> receives the output of the input inverter stage <NUM>. The second inverter stage <NUM> includes a PMOS transistor 210a and an NMOS transistor 210b. A source terminal 210aS of the PMOS transistor 210a receives the IO supply voltage (VDDS) <NUM>. Gate terminals 210aG and 210bG receive the output of the input inverter stage <NUM>. Drain terminals <NUM>0aD and 210bD of the transistors 210a and 210b respectively are combined to generate an output of the second inverter stage <NUM>. A pair of weak keeper transistors <NUM> is coupled to the output of the second inverter stage <NUM>. The weak keeper transistors include a top PMOS transistor 212a and a bottom PMOS transistor 212b connected in series. Gate terminals 212aG and 212bG of the top PMOS transistor 212a and the bottom PMOS transistor 212b respectively are combined together to receive the output of the second inverter stage <NUM>. A source terminal 212aS of the top PMOS transistor 212a is coupled to the IO supply voltage (VDDS) <NUM>, and a drain terminal 212bD of the bottom PMOS transistor 212b is coupled to the output of the input inverter stage <NUM>, which is also the input to the second inverter stage <NUM>. An output inverter stage <NUM> is coupled to the second inverter stage <NUM> and generates a supply detect signal <NUM>. The output inverter stage <NUM> includes a PMOS transistor 214a and an NMOS transistor 214b. A source terminal 214aS of the PMOS transistor 214a is connected to the IO supply voltage (VDDS) <NUM>. Gate terminals 214aG and 214bG receive the output of the second inverter stage <NUM>. Drain terminals 214aD and 214bD of the transistors 214a and 214b respectively are combined to generate the supply detect signal <NUM>. Source terminals 208cS, 210bS and 214bS of the transistors 208c, 210b and 214b are connected to a ground terminal. Also, the PMOS transistors 208a, 210a and 214a receive the IO supply voltage (VDDS) <NUM> at a substrate. In one embodiment, an inverter stage in supply detector cell <NUM> is replaced by any inverter.

The supply detector cell <NUM> is configured to detect the core supply voltage (VDD) <NUM> and generate the supply detect signal <NUM>. When the core supply voltage (VDD) <NUM> is in OFF state, the NMOS transistors 208b and 208c are in OFF state. When the IO supply voltage (VDDS) <NUM> starts ramping and becomes more than a threshold voltage (Vtn) of the diode connected NMOS transistor <NUM>, the diode connected NMOS transistor <NUM> is turned ON. Accordingly, the output of the input inverter stage <NUM> is (VDDS -Vtn). The voltage of (VDDS - Vtn), which is a weak logic-HIGH, is inverted by the second inverter stage <NUM> whose output becomes weak logic-LOW. In response to receiving this weak logic-LOW signal, the pair of weak keeper transistors <NUM> pulls the output of the input inverter stage <NUM> to an IO supply voltage (VDDS) level from (VDDS-Vtn). This provides for zero static leakage current in the second inverter stage <NUM>, because a logic-HIGH signal is provided to the second inverter stage <NUM>. The logic-HIGH signal received at the second inverter stage <NUM> results in a logic-LOW signal at an output of the second inverter stage <NUM>. The logic-LOW signal output of the second inverter stage <NUM> is provided as input to the output inverter stage <NUM>, which results in a logic-HIGH supply detect signal <NUM>. Accordingly, the output inverter stage <NUM> buffers the output of the input inverter stage <NUM>. The supply detector cell <NUM> provides a logic-HIGH supply detect signal <NUM> when the core supply voltage (VDD) <NUM> is in OFF state. The logic-HIGH supply detect signal is suitable to tristate associated input/output circuits. Advantageously, when the IO supply voltage (VDDS) <NUM> ramps up, the supply detect signal <NUM> also ramps up with IO supply voltage (VDDS) <NUM>. Moreover, the supply detector cell <NUM> generates zero static current from the IO supply voltage (VDDS) <NUM> at all values of core supply voltage (VDD) <NUM>.

In a state when IO supply voltage (VDDS) <NUM> is stable, and core supply voltage (VDD) ramps up, the NMOS transistors 208b and 208c are turned ON, thereby pulling the output of the input inverter stage <NUM> to a logic-LOW. The supply detect signal <NUM> is also pulled to a logic-LOW. In this condition, the PMOS transistor 208a will be in OFF stage if the source-gate voltage (Vsg) of the PMOS transistor 208a is less than a threshold voltage (Vtp) of the PMOS transistor 208a.

So long as the condition of equation (<NUM>) is met across process, voltage and temperature combinations, it results in a zero static current consumption in the supply detector cell <NUM>. Accordingly, the supply detector cell <NUM> is applicable across multiple IO circuits, operating conditions and different ranges of core supply voltage (VDD) that satisfy (<NUM>). This is further shown with reference to <FIG>.

<FIG> is an example graph of the operation of the supply detector. <FIG> shows the core-supply values at which the supply detect signal switches to logic-HIGH and logic-LOW, when core-supply powers down and powers-up respectively. These core-supply voltage values (Y-axis) are plotted under different operating conditions (X-axis).

<FIG> is an example graph of the zero-static current behavior of the supply detector at different states of the core supply voltage (VDD) and IO supply voltage (VDDS). The leakage current through the IO supply voltage (VDDS) is plotted under different operating conditions. The maximum IO supply leakage current is 224nA at core supply voltage (VDD) value of <NUM>. 1V, IO supply voltage (VDDS) value of <NUM>. 98V, and temperature of 125C.

<FIG> is a block diagram of a driver circuit <NUM> coupled to a PAD <NUM>. The driver circuit <NUM> is powered by an IO (input/output) supply voltage (VDDS) <NUM>. The driver circuit <NUM> includes a pair of level shifter circuits <NUM> and <NUM>. The level shifter circuit <NUM> receives an input signal A, and the level shifter circuit <NUM> receives a tristate signal GZ, as respective inputs. Also, the pair of level shifter circuits <NUM> and <NUM> receives the core supply voltage (VDD) <NUM> and the IO supply voltage (VDDS) <NUM>. Moreover, the driver circuit <NUM> includes a pair of predriver logic circuits <NUM> and <NUM>. Each predriver logic circuit is coupled to an output of the level shifter circuit, so the predriver logic circuit <NUM> is coupled to an output of level shifter circuit <NUM>, and the predriver logic circuit <NUM> is coupled to an output of level shifter circuit <NUM>. The pair of predriver logic circuits <NUM> and <NUM> is powered by IO supply voltage (VDDS) <NUM>. A pair of gating circuits <NUM> and <NUM> is coupled to the pair of predriver logic circuits <NUM> and <NUM> respectively. The gating circuit <NUM> is coupled to an output of predriver logic circuit <NUM>, and the gating circuit <NUM> is coupled to an output of predriver logic circuit <NUM>. The pair of gating circuits <NUM> and <NUM> receives a control signal (Noff) <NUM> from a failsafe circuit (not shown in <FIG>). The gating circuit <NUM> also receives the IO supply voltage (VDDS) <NUM> and a substrate signal (X) <NUM> from the failsafe circuit. A final driver circuit <NUM> is coupled to the pair of gating circuits <NUM> and <NUM>. The final driver circuit <NUM> includes a final driver PMOS transistor <NUM> and a final driver NMOS transistor <NUM>. The final driver PMOS transistor <NUM> is powered by the IO supply voltage (VDDS) <NUM> and receives a substrate signal (X) <NUM> from the failsafe circuit (not shown in <FIG>). The PAD <NUM> is coupled to the final driver circuit <NUM>. The pair of level shifter circuits <NUM> and <NUM>, the pair of predriver logic circuits <NUM> and <NUM>, the gating circuit <NUM> and the final driver NMOS transistor <NUM> are also connected to a ground terminal. The operation of the driver circuit <NUM> is described in connection with <FIG>.

<FIG> is a schematic of an input/output (IO) circuit <NUM>. The IO circuit <NUM> includes a driver circuit <NUM>, a PAD <NUM> and a failsafe circuit <NUM>. The driver circuit <NUM> is similar in connections and operation to the driver circuit <NUM>. The driver circuit <NUM> is powered by an IO (input/output) supply <NUM>. The driver circuit <NUM> includes a pair of level shifter circuits <NUM> and <NUM>. The level shifter circuit <NUM> receives an input signal A, and the level shifter circuit <NUM> receives a tristate signal GZ. Also, the level shifter circuits <NUM> and <NUM> receive the core supply voltage (VDD) <NUM> and the IO supply voltage (VDDS) <NUM>. Moreover, the driver circuit <NUM> includes a pair of predriver logic circuits <NUM> and <NUM>. Each predriver logic circuit is coupled to an output of the level shifter circuit, so the predriver logic circuit <NUM> is coupled to an output of the level shifter circuit <NUM>, and the predriver logic circuit <NUM> is coupled to an output of the level shifter circuit <NUM>. The pair of predriver logic circuits <NUM> and <NUM> is powered by IO supply voltage (VDDS) <NUM>.

A pair of gating circuits <NUM> and <NUM> is coupled to the pair of predriver logic circuits <NUM> and <NUM> respectively. The gating circuit <NUM> is coupled to an output of the predriver logic circuit <NUM>, and the gating circuit <NUM> is coupled to an output of the predriver logic circuit <NUM>. The gating circuit <NUM> includes two PMOS transistors 514a and 514b and an NMOS transistor 514c. The PMOS transistor 514a receives a control signal (Noff) <NUM> at a gate terminal and a substrate signal (X) <NUM> at a body terminal from the failsafe circuit <NUM>. The PMOS transistor 514b receives the IO supply voltage (VDDS) <NUM> at a gate terminal and the substrate signal (X) <NUM> at a body terminal. The NMOS transistor 514c receives an inverted control signal (Noffz) 515X at a gate terminal. The gating circuit <NUM> includes an NMOS transistor 516a. The NMOS transistor 516a receives the control signal (Noff) <NUM> at a gate terminal from the failsafe circuit <NUM>, and its source terminal is connected to ground. A final driver circuit <NUM> is coupled to the pair of gating circuits <NUM> and <NUM>. The final driver circuit <NUM> includes a final driver PMOS transistor <NUM> and a final driver NMOS transistor <NUM>. The final driver PMOS transistor <NUM> receives the IO supply voltage (VDDS) <NUM> at a source terminal and receives the substrate signal (X) <NUM> at a body terminal. An output of the gating circuit <NUM> is connected to a gate terminal of the final driver PMOS transistor <NUM>. A gate terminal of the final driver NMOS transistor <NUM> is connected to an output the gating circuit <NUM>. The source terminal of the final driver NMOS transistor <NUM> is connected to ground terminal. The PAD <NUM> is coupled to the final driver circuit <NUM>.

The failsafe circuit <NUM> generates the control signal (Noff) <NUM> and the substrate signal (X) <NUM>. The failsafe circuit <NUM> includes a first PMOS transistor <NUM>, a second PMOS transistor <NUM> and an inverting stage <NUM>. A source terminal of the first PMOS transistor <NUM> is connected to the IO supply voltage (VDDS) <NUM>. A drain terminal of the second PMOS transistor <NUM> is connected to the PAD <NUM>, and a gate terminal of the second PMOS transistor <NUM> is connected to the IO supply voltage (VDDS) <NUM>. A source terminal of the second PMOS transistor <NUM>, the drain terminal of the first PMOS transistor <NUM>, body terminal of the first PMOS transistor <NUM>, and the body terminal of second PMOS transistor <NUM> are combined together to generate the substrate signal (X) <NUM>. The inverting stage <NUM> of the failsafe circuit <NUM> includes a third PMOS transistor <NUM>, a first NMOS transistor <NUM>, a second NMOS transistor <NUM> and a third NMOS transistor <NUM>. The first NMOS transistor <NUM>, the second NMOS transistor <NUM> and the third NMOS transistor <NUM> are connected in cascode arrangement. Gate terminals of the third PMOS transistor <NUM>, the first NMOS transistor <NUM>, the second NMOS transistor <NUM> and the third NMOS transistor <NUM> are configured to receive the IO supply voltage (VDDS) <NUM>. A source terminal of the third PMOS transistor <NUM> is connected to the PAD <NUM>. A drain terminal of the first NMOS transistor <NUM> is connected to a drain terminal of the third PMOS transistor <NUM> to generate the control signal (Noff) <NUM>. A source terminal of a third NMOS transistor <NUM> is connected to ground.

The pair of level shifter circuits <NUM> and <NUM> translates a signal from a core supply voltage (VDD) level to an IO supply voltage (VDDS) level, because the IO circuit (the pair of predriver logic circuits <NUM> and <NUM>, final driver circuit <NUM> and the failsafe circuit <NUM>) operates with IO supply voltage (VDDS) <NUM>. The pair of predriver logic circuits <NUM> and <NUM> implement a logic based on the level-shifted versions of the input signal A and the tristate signal GZ. The final driver PMOS transistor <NUM> and the final driver NMOS transistor <NUM> are controlled by output of the pair of predriver logic circuits <NUM> and <NUM>. The predriver logic circuits <NUM> and <NUM> implement the following truth table:.

where 'High-Impedance' state is achieved when both final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM> are in OFF state.

In one of the operating modes, the PAD <NUM> is at logic-HIGH, IO supply voltage (VDDS) is powered down, and the final driver PMOS transistor <NUM> and the final driver NMOS transistor <NUM> are not turned OFF, which results in leakage currents (conduction currents) from the PAD <NUM> to either: the IO supply voltage (VDDS) <NUM> through the final driver PMOS transistor <NUM>; or the ground terminal through the final driver NMOS transistor <NUM>. The failsafe circuit <NUM> avoids this operating mode by correctly turning OFF the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM>. The failsafe circuit <NUM> generates the control signal (Noff) <NUM> to turn OFF final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM>. The failsafe circuit <NUM> is powered by a PAD voltage and receives the IO supply voltage (VDDS) <NUM>. The PAD voltage is the voltage at the PAD <NUM>. When no IO supply voltage (VDDS) <NUM> exists, and the PAD voltage is at logic-HIGH, the PMOS transistor <NUM> turns ON and passes the logic-HIGH voltage on the PAD <NUM> to the control signal (NOFF) signal <NUM>. Also, the PMOS transistor <NUM> turns ON and pulls up the substrate signal (X) <NUM> to logic-HIGH. As the control signal (NOFF) <NUM> is at logic-HIGH, the PMOS <NUM> is turned OFF. The logic-HIGH control signal (Noff) <NUM> turns OFF the final driver NMOS transistor <NUM> by pulling the gate terminal of the NMOS <NUM> to ground. The PMOS transistor 514a and the NMOS transistor 514c are also turned OFF by the logic-HIGH control signal (Noff) <NUM> and the logic-LOW inverted control signal(NoffZ) 515X respectively, thereby cutting off the output of the predriver logic circuit <NUM> from the final driver PMOS transistor <NUM>. As the PAD voltage is at logic-HIGH, the gate terminal of the final driver PMOS transistor <NUM> is pulled up to logic-HIGH by the PMOS 514b, which is turned ON due to IO supply voltage (VDDS) <NUM> at its gate terminal and PAD voltage at its drain, thereby avoiding any leakage current (conduction current) from the PAD <NUM> to the IO supply voltage (VDDS) <NUM> through the final driver PMOS transistor <NUM>. Also, because the substrate signal (X) <NUM> is pulled to logic-HIGH, it avoids forward-biasing the internal pn-junction of the final driver PMOS <NUM>. The failsafe circuit <NUM> is effective when the IO supply voltage (VDDS) <NUM> is below a trip-point voltage. In at least one version, this trip-point voltage is dependent on a threshold voltage of the transistors in the inverting stage <NUM> in the failsafe circuit <NUM>. For example, the trip-point voltage is selectable by designing the relative widths of the PMOS transistor <NUM> and the cascoded NMOS transistors <NUM>, <NUM> and <NUM> in the failsafe circuit <NUM>. The extent of skewing the ratio of widths of the PMOS transistor <NUM> and the cascoded NMOS transistors <NUM>, <NUM> and <NUM> determines the trip-point voltage during IO supply voltage (VDDS) <NUM> ramp-up, when NOFF trips from logic-HIGH to logic-LOW. If PAD <NUM> is at logic-HIGH, and the IO supply voltage (VDDS) <NUM> is above the trip-point voltage, then the control signal (Noff) <NUM> is turned OFF, so the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM> are not turned OFF. This causes leakage currents (conduction currents) from the PAD <NUM> to the IO supply voltage (VDDS) <NUM> or to the ground terminal. This is further shown with reference to <FIG>.

<FIG> is an example graph of the response of a control signal (Noff) <NUM> to the IO supply voltage (VDDS) <NUM>. As shown in <FIG>, the control signal (Noff) <NUM> remains constant when IO supply voltage (VDDS) <NUM> increases as a ramp function from <NUM> volt to <NUM> volt. However, when the IO supply voltage (VDDS) <NUM> exceeds the trip-point voltage, which is <NUM> volt in the example graph, the control signal (Noff) <NUM> is turned OFF.

<FIG> is an example graph of the conduction (leakage) current from the PAD <NUM> to the IO supply voltage (VDDS) <NUM> when the IO supply voltage (VDDS) <NUM> exceeds the trip-point voltage while PAD <NUM> is at logic-HIGH. The graph shows a huge spike in leakage current (conduction current) (about 20mA) from the pad at the trip-point voltage.

As shown in <FIG> and <FIG>, an input/output (IO) circuit <NUM> includes a driver circuit <NUM>, a PAD <NUM>, a failsafe circuit <NUM> and a supply detector cell <NUM>. The driver circuit <NUM> is similar in connections and operation to driver circuit <NUM>. The failsafe circuit <NUM> is similar in connections and operation to the failsafe circuit <NUM>. The supply detector cell <NUM> is similar in connections and operation to the supply detector cell <NUM>.

The supply detector cell <NUM> is powered by an input/output (IO) supply <NUM> and receives a core supply voltage (VDD) <NUM> as an input signal. A diode connected transistor <NUM> is powered by the IO supply voltage (VDDS) <NUM>. In at least one example, the diode connected transistor <NUM> is an NMOS transistor or a PMOS transistor. An input inverter stage <NUM> is coupled to the diode connected transistor <NUM>. The input inverter stage <NUM> receives the core supply voltage (VDD) <NUM>. The second inverter stage <NUM> receives an output of the input inverter stage <NUM> and is powered by the IO supply voltage (VDDS) <NUM>. A pair of weak keeper transistors <NUM> is coupled to an output of the second inverter stage <NUM>. The transistors <NUM> are connected in series and powered by the IO supply voltage (VDDS) <NUM>. An output of the pair of weak keeper transistors <NUM> is provided as input to the second inverter stage <NUM>, which is also the output of the input inverter stage <NUM>. An output inverter stage <NUM> is coupled to the second inverter stage <NUM> and generates a supply detect signal <NUM>. The output inverter stage <NUM> is powered by the IO supply voltage (VDDS) <NUM>.

The driver circuit <NUM> is powered by an IO (input/output) supply <NUM>. The driver circuit <NUM> includes a pair of level shifter circuits <NUM> and <NUM>. The level shifter circuit <NUM> receives an input signal A, and the level shifter circuit <NUM> receives a tristate signal GZ. The level shifter circuits <NUM> and <NUM> receive the supply detect signal <NUM> from the supply detector cell <NUM>. Also, the level shifter circuits <NUM> and <NUM> receive the core supply voltage (VDD) <NUM> and the IO supply voltage (VDDS) <NUM>. Moreover, the driver circuit <NUM> includes a pair of predriver logic circuits <NUM> and <NUM>. Each predriver logic circuit is coupled to an output of the level shifter circuit, so the predriver logic circuit <NUM> is coupled to an output of the level shifter circuit <NUM>, and the predriver logic circuit <NUM> is coupled to an output of the level shifter circuit <NUM>. The pair of predriver logic circuits <NUM> and <NUM> is powered by IO supply voltage (VDDS) <NUM>.

A pair of gating circuits <NUM> and <NUM> is coupled to the pair of predriver logic circuits <NUM> and <NUM> respectively. The gating circuit <NUM> is coupled to an output of the predriver logic circuit <NUM>, and the gating circuit <NUM> is coupled to an output of the predriver logic circuit <NUM>. The gating circuit <NUM> includes two PMOS transistors 714a and 714b and an NMOS transistor 714c. The PMOS transistor 714a receives a control signal (Noff) <NUM> at a gate terminal and a substrate signal (X) <NUM> at a body terminal from the failsafe circuit <NUM>. The PMOS transistor 714b receives the IO supply voltage (VDDS) <NUM> at a gate terminal and the substrate signal (X) <NUM> at a body terminal. The NMOS transistor 714c receives an inverted control signal (Noffz) 715X at a gate terminal. The gating circuit <NUM> includes an NMOS transistor 716a. The NMOS transistor 716a receives the control signal (Noff) <NUM> at a gate terminal from the failsafe circuit <NUM>, and its source terminal is connected to ground. A final driver circuit <NUM> is coupled to the pair of gating circuits <NUM> and <NUM>. The final driver circuit <NUM> includes a final driver PMOS transistor <NUM> and a final driver NMOS transistor <NUM>. The final driver PMOS transistor <NUM> receives the IO supply voltage (VDDS) <NUM> at a source terminal and receives the substrate signal (X) <NUM> at a body terminal. An output of the gating circuit <NUM> is connected to a gate terminal of the final driver PMOS transistor <NUM>. A gate terminal of the final driver NMOS transistor <NUM> is connected to an output of the gating circuit <NUM>. The source terminal of the final driver NMOS transistor <NUM> is connected to ground terminal. The PAD <NUM> is coupled to the final driver circuit <NUM>. The pair of level shifter circuits <NUM> and <NUM> and the pair of predriver logic circuits <NUM> and <NUM> are also connected to the ground terminal.

The failsafe circuit <NUM> generates the control signal (Noff) <NUM> and the substrate signal (X) <NUM>. The failsafe circuit <NUM> includes a first PMOS transistor <NUM>, a second PMOS transistor <NUM> and an inverting stage <NUM>. The source terminal of the first PMOS transistor <NUM> is configured to receive the IO supply voltage (VDDS) <NUM>. A drain terminal of the second PMOS transistor <NUM> is connected to the PAD <NUM>, and a gate terminal of the second PMOS transistor <NUM> is connected to the IO supply voltage (VDDS) <NUM>. A source terminal of the second PMOS transistor <NUM>, the drain terminal of the first PMOS transistor <NUM>, body terminal of the first PMOS transistor <NUM>, and the body terminal of second PMOS transistor <NUM> are combined together to generate the substrate signal (X) <NUM>. The inverting stage <NUM> of the failsafe circuit <NUM> includes a third PMOS transistor <NUM>, a first NMOS transistor <NUM>, a second NMOS transistor <NUM> and a third NMOS transistor <NUM>. The first NMOS transistor <NUM>, the second NMOS transistor <NUM> and the third NMOS transistor <NUM> are connected in cascode arrangement. Gate terminals of the third PMOS transistor <NUM>, the first NMOS transistor <NUM>, the second NMOS transistor <NUM> and the third NMOS transistor <NUM> are configured to receive the IO supply voltage (VDDS) <NUM>. A source terminal of the third PMOS transistor <NUM> is connected to the PAD <NUM>. A drain terminal of the first NMOS transistor <NUM> is connected to a drain terminal of the third PMOS transistor <NUM> to generate the control signal (Noff) <NUM>. A source terminal of a third NMOS transistor <NUM> is connected to ground.

The supply detector cell <NUM> is configured to detect the core supply voltage (VDD) <NUM> and generate the supply detect signal <NUM>. The pair of level shifter circuits <NUM> and <NUM> translates a signal from a core supply voltage (VDD) level to an IO supply voltage (VDDS) level, because the IO circuit (the pair of predriver logic circuits <NUM> and <NUM>, final driver circuit <NUM> and the failsafe circuit <NUM>) operates with IO supply voltage (VDDS) <NUM>. The supply detect signal <NUM> is also received as an input to the pair of level-shifter circuits <NUM> and <NUM>. The pair of predriver logic circuits <NUM> and <NUM> implement a logic based on the level-shifted versions of the input signal A and the tristate signal GZ. The input signal A and the tristate signal GZ are modified based on the supply-detect signal <NUM> received by the pair of level shifters circuits <NUM> and <NUM>. The final driver PMOS transistor <NUM> and the final driver NMOS transistor <NUM> are controlled by output of the pair of predriver logic circuits <NUM> and <NUM>. If core supply voltage (VDD) is in OFF state, then the supply detect signal <NUM> is in logic-HIGH state. In this case, outputs of the pair of level shifter circuits <NUM> and <NUM> are logic-HIGH, which turns OFF both the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM>.

For the failsafe IO, in one of the operating modes, the PAD <NUM> is at logic-HIGH, IO supply voltage (VDDS) <NUM> is powered down, and the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM> are not turned OFF, which results in leakage currents (conduction currents) from the PAD <NUM> to either: the IO supply voltage (VDDS) <NUM> through the final driver PMOS transistor <NUM>; or the ground terminal through the final driver NMOS transistor <NUM>. The failsafe circuit <NUM> avoids this operating mode by correctly turning OFF the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM>. The failsafe circuit <NUM> generates the control signal (Noff) <NUM> to turn OFF final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM>. The failsafe circuit <NUM> receives a PAD voltage and the IO supply voltage (VDDS) <NUM>. The PAD voltage is the voltage at the PAD <NUM>. When no IO supply voltage (VDDS) <NUM> exists, and the PAD voltage is at logic-HIGH, the PMOS transistor <NUM> turns ON and passes the logic-HIGH voltage on the PAD <NUM> to the control signal (Noff) <NUM>. Also, the PMOS <NUM> turns ON and pulls up the substrate signal (X) <NUM> to logic-HIGH. As the control signal (NOFF) <NUM> is at logic-HIGH, the PMOS <NUM> is turned OFF. The logic-HIGH control signal (Noff) <NUM> turns OFF the final driver NMOS transistor <NUM> by pulling the gate terminal of the NMOS <NUM>. The PMOS transistor 714a and the NMOS transistor 714c are also turned OFF by the logic-HIGH control signal (Noff) <NUM> and the logic-LOW inverted control signal(NoffZ) 715X respectively, thereby cutting off the output of the predriver logic circuit <NUM> from the final driver PMOS transistor <NUM>. As the PAD voltage is at logic-HIGH, the gate terminal of the final driver PMOS transistor <NUM> is pulled up to logic-HIGH by the PMOS 714b, which is turned ON due to IO supply voltage (VDDS) <NUM> at its gate terminal and PAD voltage at its drain, thereby avoiding any leakage current (conduction current) from the PAD <NUM> to the IO supply voltage (VDDS) <NUM> through the final driver PMOS transistor <NUM>. Also, because the substrate signal (X) <NUM> is pulled to logic-HIGH, it avoids forward-biasing the internal pn-junction of the final driver PMOS <NUM>. The failsafe circuit <NUM> is effective when the IO supply voltage (VDDS) <NUM> is below a trip-point voltage. In at least one version, the trip-point voltage is dependent on a threshold voltage of the transistors in the inverting stage <NUM> in the failsafe circuit <NUM>. For example, the trip-point voltage is selectable by designing the relative widths of the PMOS transistor <NUM> and the cascoded NMOS transistors <NUM>, <NUM> and <NUM> in the failsafe circuit <NUM>. The extent of skewing the ratio of widths of the PMOS transistor <NUM> and the cascoded NMOS transistors <NUM>, <NUM> and <NUM> determines the trip-point voltage during IO supply voltage (VDDS) ramp-up, when NOFF trips from logic-HIGH to logic-LOW. Accordingly, the failsafe circuit <NUM> controls the leakage current (conduction current) through deactivation of the final driver circuit <NUM>, when the PAD <NUM> is at logic-HIGH, and the IO supply voltage (VDDS) <NUM> is below the trip-point voltage. However, if the core supply voltage (VDD) <NUM> is in OFF state, the PAD <NUM> is at logic-HIGH, and the IO supply voltage (VDDS) <NUM> is above the trip-point voltage, then the control signal (Noff) <NUM> is turned OFF. Accordingly, the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM> would be incorrectly gated, resulting in leakage currents. This state is avoided by the supply detector cell <NUM>.

When the core supply voltage (VDD) <NUM> is in OFF state, and IO supply voltage (VDDS) <NUM> is ramping up, the diode connected transistor <NUM> is turned ON. Accordingly, the output of the input inverter stage <NUM> is (VDDS-Vtn). Vtn is a threshold voltage of diode connected transistor <NUM>. The output of the input inverter stage <NUM> (IO supply voltage (VDDS)-Vtn), which is a weak logic-High, is inverted by the second inverter stage <NUM>. Accordingly, the output of second inverter stage <NUM> becomes weak logic-LOW. In response to receiving this weak logic-LOW signal, the pair of weak keeper transistors <NUM> pull the output of the input inverter stage <NUM> to the IO supply voltage (VDDS) level from (VDDS-Vtn). This provides for zero static leakage current in the second inverter stage <NUM>, because a logic-HIGH signal is provided to the second inverter stage <NUM>. The logic-HIGH signal received at the second inverter stage <NUM> results in a logic-LOW signal at an output of the second inverter stage <NUM>. The logic-LOW signal output of the second inverter stage <NUM> is provided as input to the output inverter stage <NUM>, which results in a logic-HIGH supply detect signal <NUM>. Accordingly, the output inverter stage <NUM> buffers the output of the input inverter stage <NUM>. A logic-HIGH supply detect signal <NUM> is provided to the pair of level shifter circuits <NUM> and <NUM>. The outputs of the pair of level shifter circuits <NUM> and <NUM> become logic-HIGH, which drives the outputs of the pair of predriver logic circuits <NUM> and <NUM> to logic-HIGH and logic-LOW respectively, thereby turning OFF both the final driver PMOS transistor <NUM> and final driver NMOS transistor <NUM> using predriver logic ciruits710 and <NUM>. Accordingly, when core supply voltage (VDD) <NUM> is in OFF state, the supply detector cell <NUM> turns OFF or deactivates the final driver circuit <NUM> when the IO supply voltage (VDDS) <NUM> is above the trip-point voltage. The IO circuit <NUM> provides very low leakage current from the PAD <NUM> when the core supply voltage (VDD) is in OFF state and the IO supply voltage (VDDS) <NUM> is above the trip-point, even when PAD is at logic-HIGH. This method of choosing the trip-point by skewing relative widths of the PMOS transistor <NUM> and the NMOS transistors <NUM>, <NUM>, <NUM> is used in controlling the maximum PAD current/pin-current. During power-down sequencing, when IO supply voltage (VDDS) <NUM> ramps-down, before the trip-point, the supply detector disables the final driver circuit <NUM> while core-supply is LOW. Below the trip-point voltage, the failsafe circuit <NUM> and gating circuits <NUM> and <NUM> disable (by tristate) the final driver. The IO circuit <NUM> provides ultra low PAD current (pin current) during powering up or powering down of a failsafe IO interface (such as the SLIMbus interface), thereby achieving true fail safe compliance.

<FIG> is an example graph of the leakage current from the PAD <NUM> to the IO supply voltage (VDDS) <NUM> when the IO supply voltage (VDDS) <NUM> exceeds the trip-point voltage. The graph shows that leakage current from the PAD <NUM> to IO supply voltage (VDDS) <NUM> is negligible, because the supply detector cell <NUM> deactivates the final driver circuit <NUM> when the PAD voltage is at logic-HIGH while the IO supply voltage (VDDS) is above the trip-point voltage.

<FIG> is a block diagram of a computing device <NUM>. The computing device <NUM> is (or is an integrated circuit incorporated into) a mobile communication device, such as a mobile phone, a personal digital assistant, a personal computer, or any other type of electronic system.

In some embodiments, the computing device <NUM> is one of, but not limited to, a microcontroller, microprocessor or system-on-chip (SoC), which includes a processing unit <NUM> such as a CPU (central processing unit), a memory unit <NUM> (such as random access memory (RAM)), and a tester <NUM>. The processing unit <NUM> can be, for example, a CISC-type (complex instruction set computer) CPU, RISC-type CPU (reduced instruction set computer), or a digital signal processor (DSP). The memory module <NUM> (which can be memory, such as RAM, flash memory, or disk storage) stores one or more software applications <NUM> (such as embedded applications) that, when executed by the processing unit <NUM>, perform any suitable function associated with the computing device <NUM>. The tester <NUM> includes logic that supports testing and debugging of the computing device <NUM> executing the software application <NUM>. For example, the tester <NUM> is suitable for emulating a defective or unavailable component(s) of the computing device <NUM> to allow verification of how the component(s), if actually existing on the computing device <NUM>, would perform in various situations (such as how the component(s) would interact with the software application <NUM>). In this way, the software application <NUM> can be debugged in an environment that resembles post-production operation.

The processing unit <NUM> includes cache-memory and logic, which store and use information frequently accessed from the memory module <NUM>, and which are responsible for operation of the computing device. The computing device <NUM> includes logic circuits <NUM> coupled to the processing unit <NUM> and the memory module <NUM>. An IO circuit <NUM> is coupled to at least one logic circuit of the logic circuits <NUM>. The IO circuit <NUM> operates as an interface between the computing device <NUM> and the external world. The IO circuit <NUM> is analogous to the IO circuit <NUM> in connection and operation. The IO circuit <NUM> has low leakage current from the PAD during power-up sequence, during power-down sequence, and during stable powered up states, because it uses: the failsafe circuitry mechanism when the IO supply voltage (VDDS) is below the trip-point voltage; and the core-supply detection mechanism when the IO supply voltage (VDDS) is above the trip-point voltage.

In the foregoing discussion, the term "logic-HIGH" refers to a signal that is at logic state "<NUM>," and the term "logic-LOW" refers to a signal that is at logic state "<NUM>. " Also, the terms "OFF state" or turn "OFF" or turned "OFF" refer to deactivation of a device, a component or a signal. The term turned "ON" refer to activation of a device, a component or a signal.

Claim 1:
An input/output IO circuit powered by an input/output IO supply voltage (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), the IO circuit comprising:
a supply detector cell (<NUM>, <NUM>, <NUM>) configured to detect a core supply voltage (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and generate a supply detect signal (<NUM>, <NUM>, <NUM>);
a driver circuit (<NUM>, <NUM>, <NUM>) connected to a PAD (<NUM>, <NUM>, <NUM>) and configured to receive the supply detect signal (<NUM>, <NUM>, <NUM>); and
a failsafe circuit (<NUM>, <NUM>) configured to receive the PAD voltage,
wherein the failsafe circuit (<NUM>, <NUM>) is configured to control a leakage current from the PAD (<NUM>, <NUM>, <NUM>) through deactivation of a final driver circuit of the driver circuit (<NUM>, <NUM>, <NUM>) when the IO supply voltage (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is below a trip-point and the PAD is at the high logic level; and
wherein the supply detector cell (<NUM>, <NUM>, <NUM>) is configured to control the leakage current from the PAD (<NUM>, <NUM>, <NUM>) through deactivation of the final driver circuit when the IO supply voltage (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is above a trip-point and the PAD is at the high logic level.