Patent Description:
Microprocessors, also known as "processors," perform computational tasks for a wide variety of applications. A conventional microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also known as "processors" or "CPU cores," that execute software instructions. The software instructions instruct a processor to perform operations based on data. The processor executes computer program instructions ("instructions"), also known as "software instructions," to perform operations based on data and generate a result, which is a produced value. An instruction that generates or writes a produced value is a "producer" instruction. The produced value may then be stored in a memory, provided as an output to an input/output ("I/O") device, or made available (i.e., communicated) as an input value to another "consumer" (e.g., a read/load) instruction executed by the processor, as examples.

The processors include instruction processing circuits configured to decode the fetched instructions for a given software process being executed by a respective processor into decoded instructions to determine the instruction type and actions required. The decoded instructions are placed in one or more of the instruction pipelines and processed based on source and target operands of the decoded instructions according to the instruction set architecture (ISA) of the processor. Conventionally, ISAs have been oriented around the use of general purpose registers (GPRs) as source and target operands, with the ISA encoding in instructions designating its sources and targets through encoding of GPR numbers. The values stored in these GPRs are "persistent," meaning that for each GPR, once a given instruction has written a result into it, that value in that GPR remains an "architecturally required" value available to any subsequent instruction that uses that GPR as a source operand. The value stored in GPRs are available up until the point that either some subsequent instruction writes a new value into that GPR or the processor gets "reset. " Essentially, for any given software "process," the values in the GPRs are considered part of the "state" for that process. As such, the processor hardware must maintain the values of the GPRs, and software must take care to save and restore those values when a processor switches between different processes.

<FIG> is an exemplary set of computer software instructions <NUM> of a software process <NUM> that can be executed by a processor. The computer software instructions <NUM> include instructions I1-<NUM> that include instructions that name GPRs as source and/or target operands. In this example, instructions I1 and I2 are move (MOV) instructions that move immediate values into registers R0 and R1, respectively. The values in registers R0 and R1 are consumed by the add (ADD) write instruction I3 that loads the values stored in registers R0 and R1 and add these two values together and store (i.e., write) the result in register R2. As seen in the computer software instructions <NUM>, registers R0 and R1 are overwritten by instructions I10 and I11 before the values stored in registers R0 and R1 are accessed again after the write instruction I3. So in this example, instructions I4-I9 in the software process <NUM> no longer need the values stored in registers R0 and R1 after execution of instruction I3 is complete. In short, the values stored in registers R0 and R1 have become obsolete after execution of instruction I3 is completed.

If instruction execution of the computer software instructions <NUM> were interrupted after execution of instruction I3 for example, the operating system software executing on the processor would decide to switch software processes executing on the processor. The software handling the process switch would be obligated to save the values currently stored in registers RO-RP at the time of the interrupt, including the values in registers R0 and R1, as part of the context of the software process <NUM> before a new software process and its context is switched into the processor to execute. This is so that when the software process <NUM> is switched back in to the processor to be executed, the previously stored context of the software process <NUM> that existed at the time of the interrupt can be restored in (switched into) the processor so that software process <NUM> can be executed where it was left out at the time of the interruption based on the correct context. This context restoration would include restoring the values stored in the registers RO-RP, including registers R0 and R1, for the software process <NUM> that existed at the time of the interruption. The operating system software has to expend processing cycles, and thus performance of the processor, storing and restoring the complete context of the interrupted software process <NUM> even though some values stored in the context, such as the values stored in registers R0 and R1 are never reused after execution of instruction I3.

<CIT> describes that an instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are made active or inactive after an instruction specified last-use by an instruction, wherein the architected operands are made active by performing a write operation to an inactive operand, wherein the activation/deactivation may be performed by the instruction having the last-use of the operand or another (prefix) instruction.

<NPL> - describes live dead tags on computer registers.

<CIT> describes that a processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

<CIT> describes a method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in which the processor supports multiple contexts (threads), and either rapid context switching from thread to thread or scheduling of instructions from different threads within a single cycle. An important component of processors for such systems is the register file; the processor needs a large register file or resource to provide the registers used for the threads. One form of the invention maintains a set of private architecturally specified registers, and a set of private renaming register for each different thread. In the other three embodiments, sharing of renaming registers between different threads is permitted, to enable a reduction in the total number of registers required. One of these three embodiments enables any of the architecturally specified registers that are private to a thread but are not in use, to be employed as renaming registers. Another of the embodiments treats all registers as sharable and enables any register from the register file or resource to be used as a renaming register for any thread.

<CIT> describes that object code is generated from an internal representation that includes a plurality of source operands. The generating includes performing for each source operand in the internal representation determining whether a last use has occurred for the source operand. The determining includes accessing a data flow graph to determine whether all uses of a live range have been emitted. If it is determined that a last use has occurred for the source operand, an architected resource associated with the source operand is marked for last-use indication. A last-use indication is then generated for the architected resource. Instructions and the last-use indications are emitted into the object code.

Aspects disclosed herein include obsoleting values stored in registers in a processor based on processing of obsolescent register-encoded instructions. Related methods and computer-readable media are also disclosed. The processor is in a central processing unit (CPU) that can include other processors (also known as CPU cores) as a multi-processor CPU. In exemplary aspects disclosed herein, the processor is configured to support execution of instructions that include obsolescence encoding ("obsolescent-encoded instructions") indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. Such instructions may call for a source register to be read and/or a target register to be written. A register that is encoded as being obsolescent means that the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. For example, if a particular instruction is the last instruction in an instruction stream to read a data value from a source register indicated by a source operand before the source register is overwritten by another instruction, the data value stored in the source register will not be used after such last instruction. Thus, such source register can be obsoleted by the processor. In response to a processor processing an instruction having obsolescence encoding, an obsolescence indicator associated with a register indicated as being obsolescent can be set by processing such instruction to an obsolescent state to indicate that the data value stored in such register is no longer used.

In this manner, as one example, the processor setting an obsolescence indicator of a register to an obsolescent state in response to the processing of an obsolescence-encoded instruction allows the processor to ignore the data value stored in such register to improve performance. For example, data values for source registers having an obsolescent state can be ignored and not stored in a saved context for a process being switched out, thus conserving memory and improving processing time to perform a process switch. As another example, the processor may be configured to release renamed registers in a physical register file that are mapped to registers having an obsolescent state so that such renamed registers can be reallocated before such registers are overwritten to reduce the possibility of not having an available register that may incur a pipeline stall. As another example, a processor may be configured to ignore and not use data values stored in registers having an obsolescent state for speculative use of such data values when processing subsequent instructions, because such data values may be invalid. This can reduce re-execution processing that may occur as a result of using an invalid data value as a source value of an instruction. The processor can also be configured to generate an exception and/or use a default value for a data value read from a source register that is in an obsolescent state.

As discussed above, the processor supports instructions that have obsolescence encoding as part of its instruction set architecture (ISA). As one example, the ISA may support an obsolescence encoding for an instruction to cause a processor to immediately obsolesce a register after such obsolescence-encoded instruction is executed. The processor can be configured to recognize such encoding as immediately obsolescing a register after such obsolescence-encoded instruction is executed. As another example, the ISA may support obsolescence encoding for an instruction to cause a processor to obsolesce a register after a given number of instructions are executed in an instruction stream following such obsolescence-encoded instruction. The processor can be configured to recognize such encoding as obsolescing a register after a given number of instructions encoded in the obsolescence-encoded instruction are executed in the instruction stream following the obsolescence-encoded instruction. As another example, the ISA may support an obsolescence encoding for an instruction to cause a processor to obsolesce a register after a specified event following the execution of such obsolescence-encoded instruction. The processor can be configured to recognize such encoding as obsolescing a register after such event occurs and synchronize the setting of an obsolescence indicator for such register after such event occurs. As another example, in response to determining the processed instruction includes the obsolescence encoding identifying at least one register operand to be obsoleted: determine if all instructions among the plurality of instructions that are dependent on the at least one register associated with the at least one register operand have been committed; and in response to determining all instructions among the plurality of instructions that are dependent on the at least one register associated with the at least one register operand have been committed: set the obsolescence indicator associated with the at least one register associated with the at least one register operand to an obsolescent state indicating the at least one register is obsolete.

In this regard, in one exemplary aspect, a processor is provided. The processor is configured to receive a plurality of instructions in an instruction stream from an instruction memory to be executed, the plurality of instructions comprising at least one instruction that includes a register operand. The processor is also configured to process an instruction among the plurality of instructions and determine if the processed instruction includes an obsolescence encoding identifying at least one register operand associated with at least one register among a plurality of registers in the processor to be obsoleted. In response to determining the processed instruction includes the obsolescence encoding identifying at least one register operand to be obsoleted, the processor is also configured to set an obsolescence indicator associated with the at least one register associated with the at least one register operand to an obsolescent state indicating the at least one register is obsolete.

In another exemplary aspect, method of obsoleting a data value stored in a register in a processor is provided. The method comprises receiving a plurality of instructions in an instruction stream from an instruction memory to be executed, the plurality of instructions comprising at least one computer instruction that includes a register operand. The method also comprises processing an instruction among the plurality of instructions and determining if the processed instruction includes an obsolescence encoding identifying at least one register operand associated with at least one register among a plurality of registers in the processor to be obsoleted. In response to determining the processed instruction includes the obsolescence encoding identifying at least one register operand to be obsoleted, the method also comprises setting an obsolescence indicator associated with the at least one register associated with the at least one register operand to an obsolescent state indicating the at least one register is obsolete.

In another exemplary aspect, a non-transitory computer-readable medium having stored thereon an instruction program comprising a plurality of computer executable instructions for execution by a processor is provided. The plurality of computer-executable instructions comprises an obsolescence register-encoded instruction comprising an instruction type, one or more register operands, and obsolescence instruction type identifying at least one register among the one or more register operands to be obsoleted by the processor when executed.

Before discussing examples of a processor obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions, an exemplary processing-based system that includes a CPU with one or more processors is first discussed with regard to <FIG> and <FIG>.

<FIG> is a diagram of an exemplary processor-based system <NUM> that includes a central processing unit (CPU) <NUM>. The CPU <NUM> is configured to issue memory requests (i.e., data read and data write requests) to a memory system <NUM> that includes a cache memory system <NUM> and a main memory <NUM>. For example, the main memory <NUM> may be a dynamic random access memory (DRAM) provided in a separate DRAM chip. The CPU <NUM> includes one or more respective processors <NUM>(<NUM>)-<NUM>(N), wherein 'N' is a positive whole number representing the number of processors included in the processor <NUM>. As will be discussed in more detail below, the processors <NUM>(<NUM>)-<NUM>(N) are each configured to obsolete values stored in their registers (e.g., general purpose registers (GPRs)) based on processing obsolescent register-encoded instructions in an instruction stream. The CPU <NUM> can be packaged in an integrated circuit (IC) chip <NUM>. The cache memory system <NUM> includes one or more cache memories <NUM>(<NUM>)-<NUM>(X) that may be at different hierarchies in the processor-based system <NUM> and that are logically located between the processors <NUM>(<NUM>)-<NUM>(N) and the main memory <NUM>, where 'X' is a positive whole number representing the number of processors included in the CPU <NUM>. A memory controller <NUM> controls access to the main memory <NUM>.

For example, a processor <NUM>(<NUM>)-<NUM>(N) as a requesting device may issue a data request <NUM> to read data in response to processing a load instruction. The data request <NUM> includes a target address of the data to be read from memory. Using processor <NUM>(<NUM>) as an example, if the requested data is not in a private cache memory <NUM>(<NUM>) (i.e., a cache miss to cache memory <NUM>(<NUM>)), which may be considered a level one (L1) cache memory, the private cache memory <NUM>(<NUM>) sends the data request <NUM> over an interconnect bus <NUM> in this example to a shared cache memory <NUM>(X) shared with all of the processors <NUM>(<NUM>)-<NUM>(N), which may be a level (<NUM>) cache memory. The requested data in the data request <NUM> is eventually either fulfilled in a cache memory <NUM>(<NUM>)-<NUM>(X) or the main memory <NUM> if not contained in any of the cache memories <NUM>(<NUM>)-<NUM>(X).

<FIG> illustrates an instruction processing circuit <NUM> that can be provided in a processor <NUM> in the CPU <NUM> in <FIG>. The instruction processing circuit <NUM> includes one or more instruction pipelines I<NUM>-IN for processing fetched computer instructions 306F fetched by an instruction fetch circuit <NUM> for execution from a series of instructions <NUM> stored in an instruction cache memory <NUM> or instruction memory <NUM>, as examples. The instruction fetch circuit <NUM> is configured to provide fetched instructions 306F into the one or more instruction pipelines I<NUM>-IN as an instruction stream <NUM> in the instruction processing circuit <NUM> to be pre-processed before the fetched instructions 306F reach an execution circuit <NUM> to be executed. The instruction pipelines I<NUM>-IN are provided across different processing circuits or stages of the instruction processing circuit <NUM> to pre-process and process the fetched instructions 306F in a series of steps that can be performed concurrently to increase throughput prior to execution of the fetched instructions 306F by the execution circuit <NUM>.

As will be discussed in more detail below, instructions 306F in the instruction stream <NUM> can include obsolescent register-encoded instructions that are encoded such that when processed by a processor <NUM>, an encoded register operand in the obsolescent register-encoded instruction is obsoleted by the processor <NUM>. This allows a data value stored in a register indicated as having obsoleted data to be ignored in various processing to improve performance of the CPU <NUM>.

With continuing reference to <FIG>, the instruction processing circuit <NUM> includes an instruction decode circuit <NUM> configured to decode the fetched instructions 306F fetched by the instruction fetch circuit <NUM> into decoded instructions 306D to determine the instruction type and actions required. The decoded instructions 306D are placed in one or more of the instruction pipelines I<NUM>-IN and are next provided to a rename circuit <NUM> in the instruction processing circuit <NUM> to determine if any register names in the decoded instructions 306D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The rename circuit <NUM> is configured to call upon a register map table (RMT) <NUM> to rename a logical source register operand and/or write a destination register operand of a decoded instruction 306D to available physical registers <NUM>(<NUM>)-<NUM>(X) (P0, P1,. , PX) in a physical register file (PRF) <NUM>. The RMT <NUM> contains a plurality of mapping entries <NUM>(<NUM>)-<NUM>(P) each mapped to (i.e., associated with) a respective logical register RO-RP. The mapping entries <NUM>(<NUM>)-<NUM>(P) are each configured to store respective mapping information PR(<NUM>)-PR(P) in the form of an address pointer in this example to point to a physical register <NUM>(<NUM>)-<NUM>(X) in the PRF <NUM>. Each physical register <NUM>(<NUM>)-<NUM>(X) in the PRF <NUM> is configured to store a data entry for the source and/or destination register operand of a decoded instruction 306D.

The instruction processing circuit <NUM> also includes a register access (RACC) circuit <NUM> configured to access a physical register <NUM>(<NUM>)-<NUM>(X) in the PRF <NUM> based on a mapping entry mapped to a logical register RO-RP in the RMT <NUM> of a source register operand of a decoded instruction 306D to retrieve a produced value from an executed instruction 306E in the execution circuit <NUM>. Also, in the instruction processing circuit <NUM>, a scheduler circuit <NUM> is provided in the instruction pipelines I<NUM>-IN and is configured to store decoded instructions 306D in reservation entries until all source register operands for the decoded instructions 306D are available. A write circuit <NUM> is also provided in the instruction processing circuit <NUM> to write back or commit produced values from executed instructions 306E to memory, such as the PRF <NUM>, the cache memory system <NUM> (<FIG>), or the main memory <NUM> (<FIG>).

With continuing reference to <FIG>, the instruction processing circuit <NUM> also includes a flow control prediction circuit <NUM>. The flow control prediction circuit <NUM> is configured to speculatively predict the outcome of a condition of a fetched conditional flow control instruction 306F, such as a conditional branch instruction, that controls whether the taken or not taken path in the instruction control flow path of the instruction stream <NUM> is fetched into the instruction pipelines I<NUM>-IN for execution. In this manner, the condition of the fetched conditional flow control instruction 306F does not have to be resolved in execution by the execution circuit <NUM> before the instruction processing circuit <NUM> can continue processing speculatively fetched instructions 306F. The prediction made by the flow control prediction circuit <NUM> can be provided as prediction information <NUM> to the instruction fetch circuit <NUM> to be used by the instruction fetch circuit <NUM> to determine the next instructions <NUM> to fetch.

However, if the condition of the conditional flow control instruction 306F is determined to have been mispredicted when the conditional flow control instruction 306F is executed in the execution circuit <NUM>, the instruction 306F is interrupted. The speculatively fetched instructions 306F that were processed in the instruction processing circuit <NUM> after the conditional flow control instruction 306F are flushed because the direction of program flow is changed and will not include processing of these instructions. Load or store instructions 306F for which a calculated address of a memory location may be invalid or cannot be accessed for some other reason can also cause a flush of subsequent instructions 306F. The program flow of the instruction processing circuit <NUM> is interrupted under these conditions, and the instruction processing circuit <NUM> is returned to a previous state. The previous state to which the processor is restored depends on the type of interrupted instruction 306F and may be a state that existed either prior to or as a result of the instruction 306F that is interrupted ("interrupting instruction"). In particular, the present disclosure is directed to recovering the previous state of the RMT <NUM> to restore logical register-to-physical register mappings that have been changed by instructions that entered the instruction processing circuit <NUM> after the interrupting instruction <NUM> ("younger instructions").

With continuing reference to <FIG>, the instruction processing circuit <NUM> also includes an optional reorder buffer (ROB) <NUM> containing entries ("ROB entries") <NUM>(<NUM>)-<NUM>(N) allocated to each instruction <NUM> that is being processed by the instruction processing circuit <NUM>, but has not yet been committed. A ROB <NUM> can be used if the CPU is an out-of-order processor that is configured to execute instructions 306F out of order. A ROB index identifies the position of each ROB entry <NUM>(<NUM>)-<NUM>(N) in the ROB <NUM>. The ROB entries <NUM>(<NUM>)-<NUM>(N) are allocated sequentially in program order to instructions <NUM>. The ROB index for each instruction <NUM> is reported back to the instruction processing circuit <NUM> when the ROB entry <NUM>(<NUM>)-<NUM>(N) is initially allocated. In this manner, the instruction processing circuit <NUM> can associate a ROB index to the interrupting instruction. Information about changes to the mapping of the logical registers RO-RP as a result of an instruction <NUM> is stored in the ROB entry <NUM>(<NUM>)-<NUM>(N) corresponding to the instruction <NUM>.

The ROB <NUM> includes a Read Pointer RD_PTR pointing to the ROB index of the ROB entry <NUM>(<NUM>)-<NUM>(N) from which information about the oldest uncommitted instruction <NUM> is read when it is committed. The Read Pointer RD_PTR is updated each time an uncommitted instruction <NUM> is committed. The ROB <NUM> also includes a Write Pointer WR_PTR indicating the ROB index of the last ROB entry <NUM>(<NUM>)-<NUM>(N) to which information is written about the youngest uncommitted instruction <NUM>. When an instruction <NUM> updates a logical register-to-physical register mapping of a logical register RO-RP in the RMT <NUM>, the ROB index of a ROB entry <NUM>(<NUM>)-<NUM>(N) of the instruction <NUM> is associated with that logical register RO-RP. Therefore, the ROB index corresponding to the last instruction <NUM> that updated the mapping of a logical register R0-RP is stored in the RMT <NUM> with the entry for the logical register RO-RP.

With continuing reference to <FIG>, the instruction processing circuit <NUM> also includes a committed map table (CMT) <NUM> which stores the logical register-to-physical register mapping of each logical register RO-RP of the processor <NUM> as a result of committed instructions <NUM>. The CMT <NUM> is only updated when an instruction <NUM> is committed. The CMT <NUM> is not changed by the recovery of the RMT <NUM> in response to a flush. The instruction processing circuit <NUM> also includes a mapping control circuit <NUM>, which includes a register rename recover circuit (RRRC) <NUM> for controlling the RMT flush recovery. The mapping control circuit <NUM> is configured to allocate new ROB entries <NUM>(<NUM>)-<NUM>(N) to new instructions <NUM> entering the instruction pipeline I<NUM>-IN and set the Write Pointer WR_PTR accordingly. Therefore, the ROB entries <NUM>(<NUM>)-<NUM>(N) may also be referred to herein as instruction entries <NUM>(<NUM>)-<NUM>(N). The mapping control circuit <NUM> also deallocates a ROB entry <NUM>(<NUM>)-<NUM>(N) when an oldest uncommitted instruction <NUM> is committed. This includes moving the Read Pointer RD_PTR to the next oldest uncommitted instruction.

As discussed above and in more detail below, the processor <NUM> can be configured to process an obsolescence register-encoded instruction <NUM> in the instruction stream <NUM> to indicate that a logical register RO-RP is obsolescent. In this example, the RMT <NUM> is appended with obsolescence indicators <NUM>(<NUM>)-<NUM>(P) to provide storage for the processor <NUM> to record and track the obsolescent state of the logical registers RO-RP based on the processing of obsolescence register-encoded instructions <NUM>. For example, the obsolescence indicators <NUM>(<NUM>)-<NUM>(P) may be a bit in size and configured to store a '<NUM>' bit to indicate that an associated logical register RO-RP in an obsolescent state meaning obsolescent, and a '<NUM>' bit to indicate that an associated logical register RO-RP in a non-obsolescent state meaning not obsolescent. The processor <NUM> can be configured to set an obsolescence indicator <NUM>(<NUM>)-<NUM>(P) for a logical register RO-RP to the obsolescent state when so encoded in a processed obsolescence register-encoded instruction <NUM>. The processor <NUM> can be configured to set an obsolescence indicator <NUM>(<NUM>)-<NUM>(P) for a logical register RO-RP to the non-obsolescent state when the logical register is overwritten by a subsequent instruction following execution of the obsolescence register-encoded instruction <NUM> that caused the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) to be set to the obsolescent state.

With continuing reference to <FIG>, as discussed above and in more detail below, the processor <NUM> may also be configured to record an obsolescent state in response to processing an obsolescence register-encoded instruction <NUM> in the instruction stream <NUM> within the ROB <NUM>. In this example, the ROB <NUM> can be appended with obsolescence indicators <NUM>(<NUM>)-<NUM>(P) that are associated with respective ROB entries <NUM>(<NUM>)-<NUM>(N) to provide an indication for the processor <NUM> that the instruction in a given ROB entry <NUM>(<NUM>)-<NUM>(N) has a register operand that was set to be obsolete by the processor <NUM> in response to processing an obsolescence register-encoded instruction <NUM>. For example, the obsolescence indicators <NUM>(<NUM>)-<NUM>(P) may be a bit in size and configured to store a '<NUM>' bit to indicate that an associated instruction has an operand for logical register RO-RP in an obsolescent state meaning obsolescent, and a '<NUM>' bit to indicate that an associated instruction has an operand for logical register RO-RP in a non-obsolescent state meaning not obsolescent. In this manner, if the processor <NUM> performs a flush operation in response to an interruption event, the obsolescence indicators <NUM>(<NUM>)-<NUM>(P) can be consulted to restore the RMT <NUM> to a state that existed prior to the interruption. The obsolescence indicators <NUM>(<NUM>)-<NUM>(P) can be used by the processor <NUM> to determine the ROB entry <NUM>(<NUM>)-<NUM>(N) with the oldest instruction entry for example that has obsolescence indicator <NUM>(<NUM>)-<NUM>(P) set to a non-obsolescent state so that RMT <NUM> is restored to values for instructions that have been committed and did not execute on a data value from a logical register RO-RP that was obsolescent.

<FIG> is a set of computer software instructions <NUM> of an instruction stream <NUM> that can be executed by the instruction processing circuit <NUM> of the processor <NUM> in <FIG> as the instruction stream <NUM>, wherein the computer software instructions <NUM> include obsolescence register-encoded instructions. The computer software instructions <NUM> include instructions I1-<NUM> that include instructions that name GPRs as source and/or target operands. In this example, instructions I1 and I2 are move (MOV) instructions that move immediate values as data values into source registers R0 and R1 identified by respective source register operands in instructions I1 and I2, respectively. These data values loaded in registers R0 and R1 are consumed by the add (ADD) instruction I3 which accesses the values stored in registers R0 and R1 and adds these two values together to store (i.e., write) the result in target register R2 identified by target register operand R2 in instruction I3.

As seen in the computer software instructions <NUM>, registers R0 and R1 are overwritten by instructions I10 and I11 before the values stored in registers R0 and R1 are accessed again after the write instruction I3. In this regard, in this example, instruction I3 is encoded as obsolescence register-encoded instruction. This is notated in this example by their instruction type "ADD. S" indicating an add instruction with an '. O' notation indicating an obsolescence register-encoded instruction and '. S' meaning source registers. This notation as an example can be used with a compiler that is compatible with an ISA that includes obsolescence register-encoded instructions according to the desired format. As will be discussed below, other obsolescence encoding formats are possible. In this example, instruction I3 is encoded as an obsolescence register-encoded instruction with the "ADD. S" instruction type, meaning that all provided source registers, which are registers R0 and R1 respectively in this example, are to be obsoleted by the processor <NUM> after instruction I3 is processed. As will be discussed below, in response to the processor <NUM> processing instruction I3, registers R0 and R1 will be indicated as containing obsolete data values so that these data values can be ignored for various performance reasons. The reason this is possible in this example is because as shown in the computer software instructions <NUM>, instructions I4-I9 do not access registers R0 and R1 as source registers after execution of instruction I3 is complete before the data values stored in registers R0 and R1 are overwritten by instructions I10 and I11.

As will be discussed in more detail below, the processor <NUM> being capable of processing an obsolescent register-encoded instruction allows the processor <NUM> to later ignore the data value stored in such register to improve performance. For example, data values for source registers that are noted as obsolescent can be ignored and not stored in a saved context for a process being switched out, thus conserving memory and improving processing time to perform a process switch. If execution of the computer software instructions <NUM> were interrupted after execution of instruction I3 for example, operating system software executing on the processor <NUM> could decide to switch software processes executing on the processor <NUM>. The software handling the process switch would be obligated to save the values currently stored in physical registers PO-PX at the time of the interrupt, including the physical registers PO-PX mapped to registers R0 and R1 in the RMT <NUM> (<FIG>), as part of the context of the current process before a new software process and its context is switched into the processor <NUM> to execute. This is so that when the previous software process is switched back into the processor <NUM> to be executed, the previously stored context of the software process that existed at the time of the interrupt can be restored in (switched into) the processor <NUM> so that software process can be executed where it was left out at the time of the interruption based on the current context. However, if registers R0 and R1 in the RMT <NUM> were designated as obsolete, the data values stored in the physical registers PO-PX mapped to registers R0 and R1 would be obsolete and thus would not have to be stored for the current context. Thus, the operating system software could avoid expending processing cycles storing data for obsolete registers to save processing time and memory.

<FIG> illustrates an exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type "INST. O' extension in the instruction type INST signifies to the processor <NUM> that the instruction <NUM> has obsolescent register-encoded information. S' extension in the instruction type INST signifies to the processor <NUM> that the instruction <NUM> has encoding to obsolete all the source registers identified by the source register operands. The instruction format <NUM> includes a target register operand OP. The instruction format <NUM> also includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. In this example, the '. S' extension appended in the instruction type INST signifies that all source registers identified by the source register operands OP. S<NUM> - OP. Sx <NUM> are to be made obsolescent by the processor <NUM>. <FIG> also illustrates an example of an ADD instruction <NUM> encoded with instruction type "ADD. S" according to the instruction format <NUM> that names a target source operand R2 and two source register operands R1 and R0 to be made obsolete. As one example, the processor <NUM> could be configured to make obsolete the source registers identified by the source register operands OP. S<NUM> - OP. Sx <NUM> after the register obsolescent register-encoded instruction <NUM> is executed.

<FIG> illustrates another exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type "INST. O' extension in the instruction type INST signifies to the processor <NUM> that the instruction <NUM> has obsolescent register-encoded information. S' extension in the instruction type INST signifies to the processor <NUM> that the instruction <NUM> has encoding to obsolete all the source registers identified by the source register operands. #' extension in the instruction type INST signifies to the processor <NUM> that the source register identified by the source register operand to be obsoleted is to be obsoleted by the processor <NUM> after the instruction following the identified number (#) of instructions is executed by the processor <NUM>. The instruction format <NUM> includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. The instruction format <NUM> includes a target register operand OP. <FIG> also illustrates an example of an ADD instruction <NUM> encoded with instruction type "'ADD. <NUM>" <NUM> according to the instruction format <NUM> that names a target source operand R2 and two source register operands R1 and R0 to be made obsolete. The encoding of the ADD instruction <NUM> instructs the processor <NUM> to obsolete the source registers identified by the source register operands R1, R0 to be obsoleted following execution of the third instruction following the ADD instruction <NUM> in an instruction stream.

<FIG> illustrates another exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type INST without the obsolescence encoding extension '. O' like the instruction format <NUM> in <FIG>. The instruction format <NUM> includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. O' extension is optional and is used when it is desired to encode the instruction <NUM> to signify that the source register identified by such encoded source register operand is to be made obsolete. The instruction format <NUM> includes a target register operand OP. T <NUM> which in this example is register R2. <FIG> also illustrates an example of an ADD instruction <NUM> encoded with instruction type 'ADD' <NUM> according to the instruction format <NUM> that namessource register R0 to be made obsolete. This is encoded by the source register operand encoding 'R0. O' in the ADD instruction <NUM>.

<FIG> illustrates another exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type INST without the obsolescence encoding extension '. O' like the instruction format <NUM> in <FIG>. The instruction format <NUM> includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. O' extension is optional and is used when it is desired to encode the instruction <NUM> to signify that the source register identified by such encoded source register operand is to be made obsolete. #' extension in the instruction type INST signifies to the processor <NUM> that the source register identified by the source register operand to be obsoleted is to be obsoleted by the processor <NUM> after the instruction following the identified number (#) of instructions is executed by the processor <NUM>. The instruction format <NUM> includes a target register operand OP. T <NUM> which in this example is register R2. <FIG> also illustrates an example of an ADD instruction <NUM> encoded with instruction type 'ADD' <NUM> according to the instruction format <NUM> that register R0 to be made obsolete after the processor <NUM> executes three (<NUM>) instructions following the ADD instruction <NUM> in the instruction stream. This is encoded by the source register operand encoding 'R0. <NUM>' in the ADD instruction <NUM>.

<FIG> is a flowchart illustrating an exemplary process <NUM> that can be performed by the processor <NUM> in <FIG> to process obsolescence register-encoded instructions to set an obsolescence indicator for a source register encoded as being obsolescent. The process includes the processor <NUM> receiving a plurality of instructions <NUM> in an instruction stream <NUM> from an instruction memory <NUM> or instruction cache memory <NUM> to be executed (block <NUM> in <FIG>). The instructions <NUM> can include at least one instruction that includes a register operand as a source and/or target operand. The processor <NUM> processes the instructions <NUM> in its instruction processing circuit <NUM> (block <NUM> in <FIG>). The processor <NUM> can also be configured to determine if the processed instruction <NUM> includes a source register operand (block <NUM> in <FIG>). In response to determining the processed instruction <NUM> includes a source register operand (block <NUM> in <FIG>), the processor <NUM> can optionally be configured to first determine if the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the source register RO-RP associated with the source register operand in the processed instruction <NUM> indicates an obsolescent state (block <NUM> in <FIG>). If so, this means that the source register indicated as being obsolescent should not be used to execute the instruction <NUM>. In response to determining the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the source register RO-RP associated with the source register operand in the processed instruction <NUM> indicates an obsolescent state (block <NUM> in <FIG>), the processor <NUM> can generate an exception or use a default value for the value of the source operand, as examples, for the processed instruction <NUM> (block <NUM> in <FIG>), and the process ends (block <NUM> in <FIG>). Alternatively, the processor <NUM> could be configured to generate and return a predetermined data value (e.g., all zeros) for a processed instruction <NUM> that names the source register operand associated with a source register RO-RP being in an obsolescent state.

However, in response to determining the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the source register RO-RP associated with the source register operand in the processed instruction <NUM> does not indicate an obsolescent state (block <NUM> in <FIG>), the processor <NUM> determines if a processed instruction <NUM> includes an obsolescence encoding that identifies at least one register operand associated with at least one logical register RO-RP in the processor <NUM> to be obsoleted (block <NUM> in <FIG>). In response to the processor <NUM> determining that the processed instruction <NUM> includes an obsolescence encoding identifying at least one register operand to be obsoleted, the processor <NUM> sets the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the logical register RO-RP associated with the register operand identified to be obsoleted in an obsolescent state to indicate that the data value stored in such logical register RO-RP is obsolete (block <NUM> in <FIG>), and the process ends (block <NUM> in <FIG>). As one example, the processor <NUM> may be configured to set an obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the logical register RO-RP associated with the register operand identified to be obsoleted in an obsolescent state once it has been determined that the instruction identifying the register operand to be obsoleted has itself been committed or executed. This information may be provided by the scheduler circuit <NUM> for example in the instruction processing circuit <NUM> in <FIG>.

The processor <NUM> can also be configured to set an obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the processed instruction <NUM> entered in a ROB entry <NUM>(<NUM>)-<NUM>(N) in the ROB <NUM> to be consulted in the event of an instruction flush where the ROB <NUM> is used to restore the RMT <NUM>.

As previously discussed and discussed below, the processor <NUM> can also consult the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) when processed instructions <NUM> that include a source register operand naming a logical register RO-RP as a source to determine if the data value stored in the source logical register RO-RP is obsolete. The source logical register RO-RP should not be obsolete, because the instruction stream <NUM> is supposed to only have obsolescence register-encoded instructions <NUM> that encode a logical register RO-RP for obsoletion when it is known that no other access will be made to the logical register RO-RP in a subsequent instruction as a source before the logical register RO-RP is overwritten. For example, a compiler or programmer is charged with encoding instructions as obsolescence register-encoded instructions <NUM> when it is known that no other instruction names the obsoleted logical register RO-RP as a source operand in a subsequent instruction before the logical register RO-RP is overwritten. However, in case an error is introduced by a programmer, compiler, or other source, the processor <NUM> can also be configured to generate an exception in response to an instruction <NUM> being processed that names a logical register RO-RP as a source operand that is determined to be obsolete based on its associated obsolescence indicator <NUM>(<NUM>)-<NUM>(P).

If a subsequent processed instruction <NUM> by the processor <NUM> is an instruction that names a target register operation for a logical register RO-RP to be written, the processor <NUM> can be also configured to set the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) associated with the target register RO-RP associated with the target register operand to a non-obsolescent state. This is because the data value written by the processor <NUM> into the target register RO-RP associated with the target register operand of the subsequent instruction <NUM> is current and not obsolete. In this manner, if the logical register RO-RP that is written is named in a source register operand in a subsequent instruction <NUM> to be executed, the data value stored in the logical register RO-RP will not be returned and an exception or predetermined data value is returned instead, as discussed above.

As discussed above, the recording of a logical register RO-RP as obsolete based on the processing of an obsolescence register-encoded instruction <NUM> in the processor <NUM> can be useful for other applications. For example, a logical register RO-RP being in an obsolescent state allows the processor <NUM> to determine such state and to ignore the data value stored in such logical register RO-RP for improved performance. For example, data values stored in logical register RO-RP indicated as being in an obsolescent state according to their respective obsolescence indicator <NUM>(<NUM>)-<NUM>(P) can be ignored and not stored in a saved context for a process being switched out, thus conserving memory and improving processing time to perform a process switch. For example, the operating system software executed by the processor <NUM> can cause the processor <NUM> to determine a currently executed process is scheduled to be switched out for a next process. In response, the processor <NUM> can be configured to store a current context for the currently executing process. The stored context can include the data values stored in the logical registers R0-RP in the PRF <NUM> as well as the mapping information PR(<NUM>)-PR(P) stored in the RMT <NUM>. In this manner, when the currently executed process that is switched out is later switched back into the instruction processing circuit <NUM> to be executed, the state of the processor <NUM> for such process that includes the previously stored logical registers RO-RP in the PRF <NUM> as well as the mapping information PR(<NUM>)-PR(P) stored in the RMT <NUM> can be restored. In this manner, the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) for each logical register RO-RP can be consulted to determine if it indicates an obsolescent state when saving the current context. The data value for any logical register RO-RP having an associated obsolescence indicator <NUM>(<NUM>)-<NUM>(P) indicating an obsolescent state can be ignored and not saved so as to save memory storage space and conserve memory access processing time in process switching.

As another example of a processor <NUM> being able to ignore data values associated with logical register RO-RP indicated in an obsolescent state, the processor <NUM> may be configured to release renamed physical registers <NUM>(<NUM>)-<NUM>(X) in the PRF <NUM> that are mapped to logical registers RO-RP having an obsolescent state so that such renamed physical registers <NUM>(<NUM>)-<NUM>(X) can be reallocated before being overwritten. This can reduce the possibility of not having an available physical register <NUM>(<NUM>)-<NUM>(X) for an instruction <NUM> being processed that has a target register, which may incur a pipeline stall until a physical register <NUM>(<NUM>)-<NUM>(X) becomes available. In response to the processor <NUM> determining that a processed instruction <NUM> includes a target register operand associated with a logical register RO-RP that is in an obsolescent state, the processor <NUM> can be configured to reclaim a mapping information PR(<NUM>)-PR(P) in the RMT <NUM> associated with the target logical register RO-RP to be available for renaming for another target operand in another processed instruction <NUM>. As yet another example of a processor <NUM> being able to ignore data values associated with a logical register R0-RP indicated in an obsolescent state, the processor <NUM> may be configured to ignore and not use data values stored in physical registers <NUM>(<NUM>)-<NUM>(X) associated with a logical register RO-RP having an obsolescent state for speculative use of such data values when processing subsequent instructions, because such data values may be invalid. This can reduce re-execution processing that may occur as a result of using an invalid data value as a source value of an instruction <NUM>.

As discussed above, the processor <NUM> can be configured to set an obsolescence indicator <NUM>(<NUM>)-<NUM>(P) in the ROB <NUM> to be used to recover the state of the RMT <NUM> in response to an exception that causes an instruction flush. In this regard, <FIG> is an illustration of the RMT <NUM>, the ROB <NUM>, the CMT <NUM>, and the mapping control circuit <NUM> of the instruction processing circuit <NUM> in <FIG>. When a flush occurs due to an interrupting instruction <NUM>, as discussed above, the instruction processing circuit <NUM> provides a flush indicator <NUM> indicating a flush of one or more instructions <NUM> in the instruction processing circuit <NUM>. The instruction processing circuit <NUM> also provides the ROB index of the ROB entry <NUM>(<NUM>)-<NUM>(N) of the interrupting instruction <NUM>, which may be referred to herein as the "interrupting instruction indicator. " The flush indicator <NUM> and the interrupting instruction indicator are received by the RRRC <NUM> to control the RMT flush recovery. The interrupting instruction indicator points to the ROB index of the ROB entry <NUM>(<NUM>)-<NUM>(N) of the interrupting instruction <NUM> that caused the flush. Based on the interrupting instruction indicator, an oldest flushed instruction entry, identified by an oldest flush instruction pointer, indicates the oldest instruction in the ROB <NUM> that is to be flushed. In recovery of the RMT <NUM>, the oldest flushed instruction <NUM> indicated by the oldest flushed instruction entry in a ROB entry <NUM>(<NUM>)-<NUM>(N) and any younger instructions identified in the ROB <NUM> will be flushed. The interrupting instruction <NUM> may be the oldest instruction to be flushed depending on the instruction type of the interrupting instruction <NUM>. Alternatively, the interrupting instruction <NUM> may not be flushed, depending on the instruction type. In this case, the interrupting instruction <NUM> is the youngest surviving instruction. Any logical register-to-physical register mapping changes that resulted from a flushed instruction must be negated (i.e., undone) to restore the RMT <NUM> to the desired previous state. As discussed above, the processor <NUM> can be configured to also check the obsolescence indicator <NUM>(<NUM>)-<NUM>(P) in the instructions in ROB entries <NUM>(<NUM>)-<NUM>(N) that are not determined to be flushed to ensure that their respective instructions are not obsolete. If they are obsolete, then such instructions should also be flushed to restore the RMT <NUM>.

With further reference to <FIG>, an example state of the RMT <NUM>, the ROB <NUM>, and the CMT <NUM> are shown. The RMT <NUM> in <FIG> has entry assignments for logical registers R0-R5. The column entries in each row indicate, for each of the logical registers R0-R5, a logical register number (LOG), a physical register number (PHY) to which the logical register R0-R5 is mapped, and a ROB index (IDX) of the ROB entry <NUM>(<NUM>)-<NUM>(N) of the instruction <NUM> that resulted in the logical register-to-physical register mapping of the logical register R0-R5. The ROB <NUM> is a table including a row for each ROB entry <NUM>(<NUM>)-<NUM>(N). Each of the ROB entries <NUM>(<NUM>)-<NUM>(N) include a respective index (IDX), a logical register number (LOG) of the logical register RO-RP whose mapping was changed by the instruction <NUM> associated with the ROB entry <NUM>(<NUM>)-<NUM>(N), the new physical register (P_NEW) to which the logical register RO-RP is mapped, and the old physical register (P_OLD) to which the logical register RO-RP was previously mapped. The ROB <NUM> is shown with ROB entries <NUM>(<NUM>)-<NUM>(N) having ROB indexes A-I. The CMT <NUM> includes entries for each logical register RO-RP with logical registers R0-R5 shown. Each entry in the CMT <NUM> includes a logical register number (LOG) and the corresponding physical register (PHY) to which its associated logical register RO-RP is mapped.

Information about any logical register-to-physical register mapping of logical registers RO-RP is updated since the last committed instruction <NUM> is stored in the ROB entries <NUM>(<NUM>)-<NUM>(N) in program order. The logical register-to-physical register mapping of each of the logical registers RO-RP whose mapping was updated as a result of an instruction <NUM> to be flushed must be recovered to the state of the mapping that existed at the time of the interrupting instruction <NUM>. Each ROB entry <NUM>(<NUM>)-<NUM>(N) contains information about the logical register mapping change that resulted from the particular instruction <NUM> to which that ROB entry <NUM>(<NUM>)-<NUM>(N) is allocated. Because the information in a ROB entry <NUM>(<NUM>)-<NUM>(N) includes both the new physical register (P_NEW) and the old physical register (P_OLD) to which a logical register RO-RP is mapped, the information from the ROB entries <NUM>(<NUM>)-<NUM>(N) can be used to negate ("undo") or recreate ("redo") the logical mapping of any logical register(s) RO-RP updated since the last committed instruction <NUM>. All ROB entries <NUM>(<NUM>)-<NUM>(N) having a ROB index from the oldest flushed instruction <NUM> and younger may have changed the logical register-to-physical register mapping of a logical register RO-RP. Therefore, when a flush indicator <NUM> is received from the instruction processing circuit <NUM>, the ROB indexes associated with each logical register map in the RMT <NUM> are compared to the oldest flush instruction pointer to identify all of the logical registers RO-RP that were mapped to a new physical register PO-PX as a result of an instruction <NUM> that is to be flushed.

Instructions can also be encoded as obsolescence register-encoded instructions to instruct the processor <NUM> to obsolete a target register that will be used as source register by a subsequent instruction <NUM>. For example, <FIG> is a set of computer software instructions <NUM> of an instruction stream <NUM> that can be executed by the instruction processing circuit <NUM> of the processor <NUM> in <FIG> as the instruction stream <NUM>, wherein the computer software instructions <NUM> include obsolescence register-encoded instructions. The computer software instructions <NUM> include instructions I1-I11 that include instructions that name GPRs as source and/or target operands. In this example, instructions I1 and I2 are move (MOV) instructions that move immediate values as data values into registers R0 and R1, respectively. These data values loaded in registers R0 and R1 are consumed by the add (ADD) instruction I3, which is an instruction, and that loads the data values stored in registers R0 and R1 and adds these two values together and stores (i.e., writes) the result in register R2.

As seen in the computer software instructions <NUM>, register R2 written by add instruction I3 is named by a source register operand in the load (LOAD) instruction I4. Register R2 is not used as a source register in any other instructions after instruction I4 until the register R2 is overwritten by instruction I10. In this regard, in this example, instruction I3 is encoded as obsolescence register-encoded instruction. Target register operand R2 is encoded to be obsolete after instruction I4 executes. This is notated in this example by "R2. <NUM>" encoded for the target register operand R2 in instruction I3 where the 'O' signifies obsoletion of logical register R2 to processor <NUM>, and the '<NUM>' signifies for the processor <NUM> to obsolete register R2 after the next one (<NUM>) instruction in the instruction stream <NUM> is executed, meaning instruction I4 in this example.

<FIG> illustrates another exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type INST. The instruction format <NUM> includes a target register operand OP. # <NUM> in the instruction <NUM>. The 'O' in target register operand OP. # <NUM> signifies an obsolescence encoding of the target register OP. T, and the '#' is encoded with a number signifying the number of subsequent instructions in an instruction stream following the instruction encoded with the instruction format <NUM> to obsolete the named target register OP. The instruction format <NUM> also includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. <FIG> also illustrates an example of an ADD instruction <NUM>. In the example of the instruction <NUM>, there are two source register operands R1 and R0. The ADD instruction <NUM> is encoded with instruction type 'ADD' <NUM> according to the instruction format <NUM> that names a target register R2 to be made obsolete. This is encoded by the source register operand encoding 'R2. <NUM>' in the ADD instruction <NUM>. The encoding of '. <NUM>' signifies the number of subsequent instructions in an instruction stream following the ADD instruction <NUM> to obsolete the named target register R2.

<FIG> illustrates another exemplary instruction format <NUM> of a register obsolescent register-encoded instruction <NUM> according to an exemplary ISA. In this example, the instruction format <NUM> has an instruction type INST. The instruction format <NUM> includes a target register operand OP. E# <NUM> in the instruction <NUM>. The 'O' in target register operand OP. E# <NUM> signifies an obsolescence encoding of the target register OP. T, and the "E#" is encoded with an event number corresponding to an event that occurs in the processor <NUM> that when occurs, triggers the processor <NUM> to obsolete the named target register OP. Examples of such events include a next read of the register. For example, a given instruction can declare that its target register becomes obsolete upon the completion of the next instruction that reads such register, as opposed to the instruction format <NUM> in <FIG> example where the target register becomes obsolete after the completion of '#' subsequent instructions. The instruction format <NUM> also includes one or more source register operands OP. S<NUM> - OP. Sx <NUM> which signifies 'X' number of source register operands. In the example of the instruction <NUM>, there are two source register operands R1 and R0. <FIG> also illustrates an example of an ADD instruction <NUM> encoded with instruction type 'ADD' <NUM> according to the instruction format <NUM> that names a target register R2 to be made obsolete. This is encoded by the source register operand encoding 'R2. E4' in the ADD instruction <NUM>. The encoding of '. E4' signifies event number '<NUM>' and that the processor <NUM> is to obsolete target register R2 after event number '<NUM>' occurs.

<FIG> is a block diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> (e.g., a microprocessor) that includes an instruction processing circuit <NUM> configured to process an obsolescence register-encoded instruction indicating one or more registers to be made obsolescent and setting an obsolescence indicator(s) for such registers to cause the data value stored in such registers to be ignored, including but not limited to the processor <NUM> and instruction processing circuit <NUM> in <FIG>, <FIG>, and <FIG>. The instruction processing circuit <NUM> can be the instruction processing circuit <NUM> in <FIG> and <FIG> as examples. The processor-based system <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server, or a user's computer.

In this example, the processor-based system <NUM> includes the processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from execution of producer instructions. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions accessible by the instruction processing circuit <NUM>. Fetched or prefetched instructions from a memory, such as from a main memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution. The processor <NUM> can include a local cache memory <NUM> to store cached data in the main memory <NUM>. Cache memory <NUM> outside the processor <NUM> between the local cache memory <NUM> and the main memory <NUM> can also be provided to provide a cache memory system <NUM>.

The processor <NUM> and the main memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based system <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the main memory <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the main memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The main memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the main memory <NUM>, one or more input device(s) <NUM>, one or more output device(s) <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based system <NUM> in <FIG> may include a set of instructions <NUM> to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may include obsolescence register-encoded instructions and may be stored in the main memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of a non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that stores the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that causes the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is in no way intended that any particular order be inferred.

Claim 1:
A processor (<NUM>, <NUM>) configured to:
receive a plurality of instructions (<NUM>, 306F, 306D) in an instruction stream (<NUM>) from an instruction memory (<NUM>, <NUM>) to be executed, the plurality of instructions (<NUM>, 306F, 306D) comprising at least one instruction that includes a register operand (OP.S<NUM> - OP.SX; OP.O. #.S<NUM> - OP.O. #.SX; OP.T.O.#; OP.T.O.E#);
process an instruction (<NUM>, 306F, 306D) among the plurality of instructions (<NUM>, 306F, 306D);
determine if the processed instruction (<NUM>, 306F, 306D) includes an obsolescence encoding identifying at least one register operand (OP.S<NUM> - OP.Sx; OP.O.S<NUM> - OP.O.Sx; OP.O.#.S<NUM> - OP.O.#.Sx; OP.T.O.#; OP.T.O.E#) associated with at least one register among a plurality of registers in the processor (<NUM>, <NUM>) to be obsoleted following a number of instructions in the instruction stream following the processed instruction in the instruction stream, wherein a register that is encoded as being obsolescence means that the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained; and
in response to determining the processed instruction includes the obsolescence encoding identifying at least one register operand (OP.S<NUM> - OP.Sx; OP.O.S<NUM> - OP.O.Sx; OP.O.#.S<NUM> - OP.O.#.Sx; OP.T.O.#; OP.T.O.E#) to be obsoleted following the number of instructions in the instruction stream following the processed instruction in the instruction stream, set an obsolescence indicator (<NUM>(<NUM>)-<NUM>(P), <NUM>(<NUM>)-<NUM>(P)) associated with the at least one register associated with the at least one register operand (OP.S<NUM> - OP.Sx; OP.O.S<NUM> - OP.O.Sx; OP.O.#.S<NUM> - OP.O.#.Sx; OP.T.O.#; OP.T.O.E#) to an obsolescent state indicating the at least one register is obsolete after execution of instructions in the instruction stream following the processed instruction in the instruction stream by the number of instructions.