Patent Description:
Wireless charging systems have been deployed to enable certain types of devices to charge internal batteries without the use of a physical charging connection. Devices that can take advantage of wireless charging include mobile processing and/or communication devices. Standards, such as the Qi standard defined by the Wireless Power Consortium enable devices manufactured by a first supplier to be wirelessly charged using a charger manufactured by a second supplier. Standards for wireless charging are optimized for relatively simple configurations of devices and tend to provide basic charging capabilities.

Conventional wireless charging systems typically use a "Ping" to determine if a receiving device is present on or proximate to a transmitting coil in a base station for wireless charging. The transmitter coil has an inductance (L) and, a resonant capacitor that has a capacitance (C) is coupled to the transmitting coil to obtain a resonant LC circuit. A Ping is produced by delivering power to the resonant LC circuit. Power is applied for a duration of time (<NUM> in one example) while the transmitter listens for a response from a receiving device. The response may be provided in a signal encoded using Amplitude Shift Key (ASK) modulation. This conventional Ping-based approach can be slow due to the <NUM> duration, and can dissipate large and significant amounts of energy, which may amount to <NUM> mJ per Ping. In one example, a typical transmitting base station may ping as fast as <NUM> times a second (period = <NUM>/<NUM>) with a power consumption of (<NUM> mJ * <NUM>) per second = 1W. In practice most, designs trade off responsiveness for a lower quiescent power draw by lowering the ping rate. As an example, a transmitter may ping <NUM> times a second with a resultant power draw of <NUM> mW. <CIT> discloses a method for decoding data, comprising demodulating a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit. <CIT> discloses a wireless power transmitter having an ASK demodulator in which a clock signal is used to encode/demodulate a data signal. <CIT> discloses a communication system that uses keyed modulation to encode fixed frequency communications on a variable fre-quency power transmission signal where the modulation signal may be created by combining a clock signal and encoded data.

Improvements in wireless charging capabilities are required to support continually increasing complexity of mobile devices. For example, there is a need for improved communication between charging devices and device being charged.

According to the present invention, a method and a charging device are provided having the features of the respective independent claim. Preferred embodiments of the invention are subject-matter of the dependent claims.

Several aspects of wireless charging systems will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawing by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements").

The software may reside on a processor-readable storage medium. A processor-readable storage medium, which may also be referred to herein as a computer-readable medium may include, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., compact disk (CD), digital versatile disk (DVD)), a smart card, a flash memory device (e.g., card, stick, key drive), Near Field Communications (NFC) token, random access memory (RAM), read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), a register, a removable disk, a carrier wave, a transmission line, and any other suitable medium for storing or transmitting software. The computer-readable medium may be resident in the processing system, external to the processing system, or distributed across multiple entities including the processing system. Computer-readable medium may be embodied in a computer-program product. By way of example, a computer-program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

Certain aspects of the present disclosure relate to apparatus and methods applicable to wireless charging devices and techniques as defined in the appended claims. Charging cells may be configured with one or more inductive coils to provide a charging surface that can charge one or more devices wirelessly. The location of a device to be charged may be detected through sensing techniques that associate location of a device to changes in a physical characteristic centered at a known location on the charging surface. Sensing of location may be implemented using capacitive, resistive, inductive, touch, pressure, load, strain, and/or another appropriate type of sensing.

One aspect of the present disclosure relates to systems, apparatus and methods that enable fast, low-power detection of objects placed in proximity to a charging surface. In one example, an object may be detected when a pulse provided to a charging circuit stimulates an oscillation in the charging circuit, or in some portion thereof. A frequency of oscillation of the charging circuit responsive to the pulse or a rate of decay of the oscillation of the charging circuit may be indicative or determinative of presence of a chargeable device has been placed in proximity to a coil of the charging circuit. Identification of a type or nature of the object may be made based on changes in a characteristic of the charging circuit. The pulse provided to the charging circuit may have a duration that is less than half the period of a nominal resonant frequency of the charging circuit.

In one aspect of the disclosure, an apparatus for detecting objects near a charging surface has a resonant circuit that includes a charging coil attached to the charging surface, a circuit configured to provide a measurement signal representative of the quality factor of the resonant circuit based on a measured response of the resonant circuit to a passive ping, a filter configured to provide a filtered version of the measurement signal that changes at a slower rate than the measurement signal, and comparison logic configured to generate a detection signal that switches when a difference between the measurement signal and the filtered version of the measurement signal exceeds a threshold level. The detection signal may indicate whether an object is positioned proximate to the charging coil.

According to certain aspects disclosed herein, a charging surface may be provided using charging cells that are deployed adjacent to the charging surface. In one example the charging cells are deployed in accordance with a honeycomb packaging configuration. A charging cell may be implemented using one or more coils that can each induce a magnetic field along an axis that is substantially orthogonal to the charging surface adjacent to the coil. In this description, a charging cell may refer to an element having one or more coils where each coil is configured to produce an electromagnetic field that is additive with respect to the fields produced by other coils in the charging cell, and directed along or proximate to a common axis.

In some implementations, a charging cell includes coils that are stacked along a common axis and/or that overlap such that they contribute to an induced magnetic field substantially orthogonal to the charging surface. In some implementations, a charging cell includes coils that are arranged within a defined portion of the charging surface and that contribute to an induced magnetic field within the substantially orthogonal to portion of the charging surface associated with the charging cell. In some implementations, charging cells may be configurable by providing an activating current to coils that are included in a dynamically-defined charging cell. For example, a charging device may include multiple stacks of coils deployed across a charging surface, and the charging device may detect the location of a device to be charged and may select some combination of stacks of coils to provide a charging cell adjacent to the device to be charged. In some instances, a charging cell may include, or be characterized as a single coil. However, it should be appreciated that a charging cell may include multiple stacked coils and/or multiple adjacent coils or stacks of coils.

<FIG> illustrates an example of a charging cell <NUM> that may be deployed and/or configured to provide a charging surface. In this example, the charging cell <NUM> has a substantially hexagonal shape that encloses one or more coils <NUM> constructed using conductors, wires or circuit board traces that can receive a current sufficient to produce an electromagnetic field in a power transfer area <NUM>. In various implementations, some coils <NUM> may have a shape that is substantially polygonal, including the hexagonal charging cell <NUM> illustrated in <FIG>. Other implementations may provide coils <NUM> that have other shapes. The shape of the coils <NUM> may be determined at least in part by the capabilities or limitations of fabrication technology, and/or to optimize layout of the charging cells on a substrate <NUM> such as a printed circuit board substrate. Each coil <NUM> may be implemented using wires, printed circuit board traces and/or other connectors in a spiral configuration. Each charging cell <NUM> may span two or more layers separated by an insulator or substrate <NUM> such that coils <NUM> in different layers are centered around a common axis <NUM>.

<FIG> illustrates an example of an arrangement of charging cells from two perspectives <NUM>, <NUM> when multiple layers are overlaid within a segment of a charging surface that may be adapted in accordance with certain aspects disclosed herein. Layers of charging cells <NUM>, <NUM>, <NUM>, <NUM> provided within a segment of a charging surface. The charging cells within each layer of charging cells <NUM>, <NUM>, <NUM>, <NUM> are arranged according to a honeycomb packaging configuration. In one example, the layers of charging cells <NUM>, <NUM>, <NUM>, <NUM> may be formed on a printed circuit board that has four or more layers. The arrangement of charging cells <NUM> can be selected to provide complete coverage of a designated charging area that is adjacent to the illustrated segment.

<FIG> illustrates a wireless transmitter <NUM> that may be provided in a charger base station. A controller <NUM> may receive a feedback signal filtered or otherwise processed by a filter circuit <NUM>. The controller may control the operation of a driver circuit <NUM>. The driver circuit <NUM> provides an alternating current to a resonant circuit <NUM> that includes a capacitor <NUM> and inductor <NUM>. The frequency of the alternating current may be determined by a charging clock signal <NUM> provided by timing circuits <NUM>. A measurement circuit may obtain a measurement signal <NUM> indicative of current flow or voltage <NUM> measured at an LC node <NUM> of the resonant circuit <NUM>. The measurement signal <NUM> may be used to calculate or estimate Q factor of the resonant circuit <NUM>.

The timing circuits <NUM> may provide the controller with one or more clock signals <NUM>, including a system clock signal that controls the operation of the controller <NUM>. The one or more clock signals <NUM> may further include a clock signal used to modulate or demodulate a data signal carried on a charging current in the resonant circuit <NUM>. The timing circuits <NUM> may include configurable clock generators that produce signals at frequencies defined by configuration information, including the charging clock signal <NUM>. The timing circuits <NUM> may be coupled to the controller through an interface <NUM>. The controller <NUM> may configure the frequency of the charging clock signal <NUM>. In some implementations, the controller <NUM> may configure the duration and frequency of a pulsed signal used for passive ping in accordance with certain aspects disclosed herein. In one example, the pulsed signal includes a number of cycles of the pulsed signal.

Certain aspects of the disclosure relate to wireless communication of configuration, control, status and other information between a power transmitter and a power receiver that is being wirelessly charged through the power transmitter. The Qi standard defines protocols (the QI protocols) that are commonly-employed protocol used by wireless chargers and include protocols for wireless communication between a power transmitter and a power receiver using. The Qi protocols can enable the power receiver to control the power transmitter wirelessly. The exchange of messages from power receiver to power transmitter is typically effected by way of Amplitude Shift Keying (ASK) modulation that produces an ASK signal carried in the electromagnetic flux between the power transmitter and power receiver. A digital signal processor (DSP) may be employed to decode the ASK signal from the voltage or current in the tank circuit of the inductive power transfer device. In many conventional systems, interrupts are used to measure timing between level changes on the ASK signal. Such methods are applicable to single channel operation and lack the ability to coordinate and validate information received in an ASK encoded signal. In one example, an external demodulation circuit may cooperate with a timer provided by a microcontroller (MCU) to generate interrupts used to calculate time between edges, which can be used to decode the ASK-modulated signal. In another example, a DSP or digital signal controller may be used to demodulate the ASK-modulated signal using digital signal processing methods. In these and other examples, expensive resources are consumed to obtain a minimalist decoding system.

In accordance with certain aspects disclosed herein, an inductive power transmission system (IPTS) enables multiple asynchronous amplitude modulated messages to be multiplexed. The asynchronous amplitude modulated messages may be received from one or more inductively powered devices (IPDs). The amplitude modulated messages may be transparently multiplexed without regard to timing. Reception and resolution of the timing of pulses that are encoded with multiple message streams can be accomplished by sampling multiple signals periodically and measuring each channels pulse sizes to decode all the channels. Two independent but coincident demodulations of the analog ASK signal operating in a band from <NUM>,<NUM> - <NUM>,<NUM>, with a base-band of <NUM> Hertz can be provided by external demodulation circuits that enable decoding based on signals extracted from both voltage and current amplitudes. The two decoded signals can be used to provide a reliable communication system.

A demodulation scheme provided in accordance with certain aspects of this disclosure can enable a designer to use a single <NUM>-bit parallel port to capture and decode encoded information transmitted through four different charging pads, where each charging pad provides current-derived and voltage-derived versions of an ASK signal. Communication with up to four different IPDs can be handled through the parallel port, and the recurring time and processing costs of conventional methods of wireless inductive communication associated with the decoding of dedicated signals from multiple inductive charging pads may be significantly reduced.

<FIG> illustrates an MCU <NUM> that may be configured to implement a demodulation scheme provided in accordance with certain aspects of this disclosure. In the illustrated example, a parallel port <NUM> of an MCU <NUM> receives ASK input <NUM>, which may be obtained from multiple charging pads. A clock generator circuit <NUM> provides a clock signal used to clock a direct memory access (DMA) controller <NUM>. In one example, the DMA controller <NUM> is clocked by a clock signal at <NUM>,<NUM> Hertz in order to sample the signals concurrently. Samples are moved to a buffer <NUM> of size <NUM> bytes every millisecond. Each bit of the byte inducted is used for a different channel. Pairs of bits in the byte may represent decoded corresponding bits decoded from current and voltage state.

In one example, a processor <NUM> processes the buffer <NUM> for all eight channels at least once every millisecond. The processor <NUM> may provide the messages contained therein to be processed by a master control module. Information decoded from ASK signals carried in the current and voltage channels may be combined to obtain a reliably decoded message even where only one of the channels has correctly decoded the message.

The MCU <NUM> may operate without the use of dedicated timers and/or any interrupts in the processor <NUM>, thereby avoiding inefficiencies that can arise from context-switching and task-switching. The timing of the ASK signals and their encoded messages can be quickly recovered by sampling signal state between edges, without resort to edge-driven methods that can burden or waste processor resources. Eliminating the need for interrupts can increase the reliability of the system when multiple sources of interrupts may require servicing that can cause disruption and unexpected effects on processing. The multiple sources of interrupts, and functions or processes that employ, rely on, or are supported by interrupts may be implemented using certain combinational logic in the same IC device that carries the MCU <NUM>.

An example used in this disclosure relates to decoding of ASK signals from four devices that are being concurrently charged. In other examples, inputs from more than four concurrently-charging devices may be received and decoded in manner that provides reliable communication and control in addition to efficiency at a cost point below conventional systems. In one example, eight charging pads may be connected to the parallel port <NUM>. In another example, only one of the current and voltage, or a combination of the current and voltage in the tank circuit may be used to derive the demodulated ASK signal. In some instances, information decoded from ASK signals carried in ASK-modulated current and voltage waveforms can be combined using a combination of logic and gates to produce a demodulated ASK signal that may be passed to the parallel port <NUM> as one ASK signal allowing for a total of eight charge pads to be connected to the parallel port.

<FIG> illustrates examples of encoding schemes <NUM>, <NUM> that may be adapted to digitally encode messages exchanged between power receivers and power transmitters. In the first example, a differential bi-phase encoding scheme <NUM> encodes binary bits in the phase of a data signal <NUM>. In the illustrated example, each bit of a data byte <NUM> is encoded in a corresponding cycle <NUM> of an encoder clock signal <NUM>. The value of each bit is encoded in the presence or absence of a transition <NUM> (phase change) in the data signal <NUM> during the corresponding cycle <NUM>.

In the second example, a power supply <NUM> is encoded using a power signal amplitude encoding scheme <NUM>. In the illustrated example, binary bits of a data byte <NUM> are encoded in level of the power supply <NUM>. Each bit of the data byte <NUM> is encoded in a corresponding cycle <NUM> of an encoder clock signal <NUM>. The value of each bit is encoded in the voltage level of the power supply <NUM> relative to a nominal <NUM>% voltage level <NUM> of the power supply <NUM> during the corresponding cycle <NUM>.

<FIG> illustrates a data flow <NUM> illustrating the decoding of messages that may be exchanged between power receivers and power transmitters in accordance with certain aspects of this disclosure. The messages may be transmitted through multiple coils of a charging surface. A general-purpose input/output (GPIO) port <NUM> may receive N channels of ASK-encoded input. The GPIO port <NUM> may include analog and digital circuits that are configured to condition and decode the ASK-encoded input. ASK data decoded by the GPIO port <NUM> may be read using a DMA <NUM> controller in accordance with timing provided by a clock circuit <NUM>. The ASK data may be organized in multiple ASK data streams <NUM> that are accessible to a message decoder <NUM>. The message decoder <NUM> may process individual ASK data stream using a channel multiplexer <NUM> to handle a current ASK data stream for processing. The message decoder may include bit or nibble processors <NUM>, a byte generation circuit <NUM> and a packet assembler <NUM> that produces a message that is buffered using first-in, first-out registers <NUM>.

<FIG> is flowchart <NUM> illustrating one example of a method for decoding messages from an ASK-encoded data signal received during a wireless charging event. The method may be performed by a processor or controller in a charging device. At block <NUM>, the processor or controller may demodulate or cause demodulation of a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit. At block <NUM>, the processor or controller may capture a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a DMA circuit. At block <NUM>, the processor or controller may stream bit sequences received from the DMA circuit into a plurality of data streams. At block <NUM>, the processor or controller may decode one or more messages from the plurality of data streams. A tank circuit in each inductive power transfer circuit may include a charging coil and a capacitor.

In one example, the processor or controller may demodulate or cause demodulation of a voltage waveform in a first tank circuit to obtain a first demodulated signal. In another example, the processor or controller may demodulate or cause demodulation of a current waveform in the first tank circuit to obtain a first demodulated signal. The processor or controller may capture a first bitstream that includes bits representing the first demodulated signal by clocking signal state of the first demodulated signal through the DMA circuit, capture a second bitstream that includes bits representing the second demodulated signal by clocking signal state of the second demodulated signal through the DMA circuit, decode the first bitstream and the second bitstream independently to obtain two versions of a first encoded message, and select between the two versions of a first encoded message to provide one of the one or more messages decoded from the plurality of data streams. In one example, the processor or controller may capture a combined bitstream by clocking bits representing the combined signal state of first demodulated signal and the second demodulated signal through the DMA circuit, decode the combined bitstream to provide one of the one or more messages decoded from the plurality of data streams.

In certain implementations, capturing the bit sequence from each demodulated signal includes receiving a first demodulated signal at a first input of a GPIO port, and receiving a second demodulated signal at a second input of the GPIO port. The first demodulated signal may be obtained from a first inductive power transfer circuit. The second demodulated signal may be obtained from a second inductive power transfer circuit. The first demodulated signal may be obtained from a voltage waveform in a tank circuit of a first inductive power transfer circuit. The second demodulated signal may be obtained from a current waveform in the tank circuit of the first inductive power transfer circuit.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM> that may be incorporated in a charging device or in a receiving device that enables a battery to be wirelessly charged. In some examples, the apparatus <NUM> may perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using a processing circuit <NUM>. The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and storage <NUM>. Storage <NUM> may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The storage <NUM> may include transitory storage media and/or non-transitory storage media.

The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers <NUM>. In one example, a transceiver <NUM> may be provided to enable the apparatus <NUM> to communicate with a charging or receiving device in accordance with a standards-defined protocol. Depending upon the nature of the apparatus <NUM>, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage <NUM> or in an external computer-readable medium. The external computer-readable medium and/or storage <NUM> may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), RAM, ROM, a programmable read-only memory (PROM), an erasable PROM (EPROM) including EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The computer-readable medium and/or storage <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The storage <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM>, and may manage access to external devices such as a transceiver <NUM>, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to a transceiver <NUM>, the user interface <NUM>, and so on.

In one implementation, the apparatus <NUM> may be implemented in a wireless charging device that has a battery charging power source coupled to multiple inductive power transfer circuits, a plurality of charging cells and a controller, which may include the one or more processors <NUM>. The plurality of charging cells may be configured to provide a current to one or more charging coils near a surface of the charging device. At least one coil may be configured to direct an electromagnetic field through a charge transfer area of each charging cell. The apparatus <NUM> may further include a DMA circuit configured to receive at least one demodulated signal from each inductive power transfer circuit. The at least one demodulated signal may be obtained from a voltage or current waveform in a tank circuit of a corresponding inductive power transfer circuit.

The controller may be configured to capture a bit sequence from each demodulated signal by clocking signal state of the each demodulated signal through the DMA circuit, stream bit sequences received from DMA circuit into a plurality of data streams, and decode one or more messages from the plurality of data streams.

In some implementations, each inductive power transfer circuit has a tank circuit that includes a capacitor and a charging coil. A first demodulated signal may be obtained from a first inductive power transfer circuit by demodulating a voltage waveform in a corresponding first tank circuit. The second demodulated signal may be obtained from the first inductive power transfer circuit by demodulating a current waveform in the first tank circuit. In certain implementations, the controller is further configured to capture a first bitstream that includes bits representing the first demodulated signal by clocking signal state of the first demodulated signal through the DMA circuit, capture a second bitstream that includes bits representing the second demodulated signal by clocking signal state of the second demodulated signal through the DMA circuit, decode the first bitstream and the second bitstream independently to obtain two versions of a first encoded message, and select between the two versions of a first encoded message to provide one of the one or more messages decoded from the plurality of data streams.

The controller may be further configured to capture a combined bitstream by clocking bits representing the combined signal state of first demodulated signal and the second demodulated signal through the DMA circuit, and decode the combined bitstream to provide one of the one or more messages decoded from the plurality of data streams.

In some implementations, the controller is further configured to receive a first demodulated signal at a first input of a GPIO port, and receive a second demodulated signal at a second input of the GPIO port. The first demodulated signal may be obtained from a first inductive power transfer circuit. The second demodulated signal may be obtained from a second inductive power transfer circuit. The first demodulated signal may be obtained from a voltage waveform in a tank circuit of a first inductive power transfer circuit. The second demodulated signal may be obtained from a current waveform in the tank circuit of the first inductive power transfer circuit.

In some implementations, the storage <NUM> maintains instructions and information where the instructions are configured to cause the one or more processors <NUM> to demodulate or cause demodulation of a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit, capture a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a DMA circuit, stream bit sequences received from the DMA circuit into a plurality of data streams and decode one or more messages from the plurality of data streams. A tank circuit in each inductive power transfer circuit may include a charging coil and a capacitor.

Claim 1:
A method (<NUM>) for decoding data, comprising:
demodulating a voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit (<NUM>), and characterised by:
capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access, DMA, circuit (<NUM>);
streaming bit sequences received from the DMA circuit into a plurality of data streams (<NUM>); and
decoding one or more messages from the plurality of data streams (<NUM>).