Patent Description:
The present disclosure generally relates to timing switch circuits for maintaining timing precision in different power modes.

The world is getting more connected every day. For example, the Internet of Things (IOT) can connect various devices (e.g., appliances, speakers, etc.) to the Internet so that, among other things, they can be controlled remotely. Wireless nodes can be embedded with the devices to connect those devices to a wireless network. The devices can therefore communicate using the wireless nodes and the wireless network.

Furthermore, the wireless nodes, because of their size and location, can be powered by batteries. To conserve power and extend battery life, the wireless nodes can reduce their power consumption by operating in a low-power mode (e.g., sleep mode) when not in active communication. For example, the wireless nodes can wake up from sleep mode and enter active mode to perform communications (e.g., transmit and/or receive data) using synchronized or coordinated communication protocols, where the wireless nodes communicate at specified times. That is, the wireless nodes can wake up at specified times for communications and then re-enter sleep mode to conserve power. But timing in the wireless nodes can drift while in sleep mode, impacting the reliability of such communications. Clock drift can also lead to other issues, such as precisely scheduling activities, accurately taking timestamps, etc. Moreover, compensating drift can require operating in active mode longer, diminishing the benefits of operating in sleep mode. <CIT> discloses a dynamic clocking computer system for a processor. The dynamic clocking computer system comprises a clock divider circuit, a multiplexer, and a state machine circuit. The clock divider circuit receives a first clock and outputs the first clock and generates a second clock. The second clock is supplied to external circuitry. <CIT> discloses a system that divides the control circuit of the embedded memory unit into an embedded memory, a self-testing circuit and a scanning other-circuit circuit according to the operating mode. <CIT> discloses lock generating circuitry including a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios. <CIT> discloses a system for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. <CIT> discloses a multiplexer that selectively provides a raw clock signal and/or a divided version of the clock signal to a microprocessing engine. <CIT> discloses a clock generation system configured to generate a clock signal and including a plurality of configuration registers and selection circuitry. Each of the configuration registers includes fields that control a frequency of the clock signal. <CIT> discloses an apparatus for generating system clock synchronization pulses using a Phase Locked Loop (PLL) lock detect signal.

Various ones of the appended drawings merely illustrate example embodiments of the present disclosure and should not be considered as limiting its scope.

Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device. For example, a timing circuit may be provided in the device, which may switch clock signals between different modes (e.g., a relatively higher power consumption mode and a relatively lower power consumption mode as compared to the higher power consumption mode) while preserving timing precision across such modes. In some embodiments, a ratio of digital logic power consumption in higher power consumption modes is more than 2x the power consumption in low power mode. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. The low frequency clock signal may be synthesized from the high frequency clock signal, so the high and low frequency clock signals may be substantially synchronized. Moreover, the switching between the different clock signals may be synchronized to select edges of a designated clock. This switching scheme may maintain frequency stability and accuracy. Furthermore, the timing circuit may drive a system time counter, which switches time base depending on the modes to maintain timing precision for use with, for example, coordinated or synchronized communication protocols.

<FIG> illustrates an example of portions of a wireless communication network <NUM>. The wireless communication network <NUM> may include a plurality of wireless nodes <NUM>, <NUM>, <NUM> and a master node <NUM>. The wireless nodes <NUM>, <NUM>, <NUM> may be communicatively coupled to the master node <NUM>, which in turn may be coupled to the internet. The wireless nodes <NUM>, <NUM>, <NUM> may communicate with the master node based on a communication protocol. The communication protocol may be for short-range wireless communications or long-range wireless communications. For short-range wireless communications, the protocol may include Bluetooth (e.g., Low Energy Bluetooth), Zigbee, IrDa or another suitable protocol.

The wireless nodes <NUM>, <NUM>, <NUM> may be coupled to or embedded in various devices, such as sensors, appliances, lighting systems, speakers, and so forth. The wireless nodes <NUM>, <NUM>, <NUM> may transmit and/or receive data to/from the master node <NUM>. The master node <NUM> may send control information to wireless nodes <NUM>, <NUM>, <NUM>. The wireless nodes <NUM>, <NUM>, <NUM> may send data (e.g., measurement or status data) to the master node <NUM>. Communications between the wireless nodes <NUM>, <NUM>, <NUM> and the master node <NUM> may be coordinated based on the communication protocol (e.g., a synchronized, contention-less network). That is, the master controller <NUM> may send data to the wireless nodes <NUM>, <NUM>, <NUM> at specified times, and the wireless nodes <NUM>, <NUM>, <NUM> may send data to the master node <NUM> at other specified times. Thus, the timing between the wireless nodes <NUM>, <NUM>, <NUM> and the master node <NUM> may be synchronized based on the communication protocol used by the network. In some embodiments, the wireless nodes <NUM>, <NUM>, <NUM> may communicate with each other or may connect directly to the internet (e.g., master node may be optional). The wireless network <NUM> may be provided as different types, such as a star network, multi-hop mesh network, and other known network types.

<FIG> illustrates an example of portions of a wireless node <NUM>. The wireless node <NUM> may include a clock circuit <NUM>, a processor <NUM>, a wireless network interface <NUM>, a memory <NUM>, and a power source <NUM>. The wireless node <NUM> may operate in different power or operating modes. For example, the wireless node <NUM> may operate in a high-power mode (e.g., wake or active mode) and one or more low-power modes (e.g., sleep, hibernation, etc.). The clock circuit <NUM> may generate different clock signals to be used in the different power modes. As explained in further detail below, the clock circuit <NUM> may generate a high frequency clock signal to be used in the high-power mode and one or more low frequency clock signals to be used in the low-power mode(s). The processor <NUM> may be coupled to the memory <NUM> and may execute instructions stored in the memory <NUM> to perform operations. The processor <NUM> may operate in the different power modes.

The wireless network interface <NUM> may include radio frequency (RF) circuits to provide wireless communication. The wireless network interface <NUM> may communicate with other devices, such as the master device, using a coordinated communication protocol, as described herein. The wireless network interface <NUM> may operate in different modes, as described herein. For example, the wireless network interface <NUM> may be powered down or put in sleep mode during low-power mode(s) and powered on for full operation during the high-power mode.

The power source <NUM> may be provided as a battery, a capacitor, an energy harvesting device, or other suitable power supplies. The power source <NUM> may supply power to other components in the wireless node <NUM>. For example, the power source <NUM> may be provided as a lithium cell battery. The charge of the power source <NUM> may drain more power when the wireless node <NUM> is operating in the high-power mode as compared to the low-power mode(s). Thus, the charge of power source <NUM> may be extended by operating in low-power mode(s).

<FIG> illustrates an example of portions of a clock switching circuit <NUM>. The clock switching circuit <NUM> may include an oscillator <NUM>, a clock gate <NUM>, a clock divider <NUM>, a multiplexor <NUM>, a system time counter <NUM>, and a controller <NUM>. The oscillator <NUM> may generate a high frequency clock signal. The oscillator <NUM> may be provided as a crystal oscillator. For example, the oscillator <NUM> may generate a ~<NUM> clock signal. The oscillator <NUM> may consume low power while generating the high frequency clock signal. As described below, the high frequency clock signal may be generated in both high- and low-power modes. The oscillator <NUM> may be part of a reference clock generator.

The clock gate <NUM> may receive the high frequency clock signal and may provide the high frequency clock signal to the multiplexor <NUM>, responsive to an enable signal. For example, when the enable signal is high, the clock gate <NUM> may provide the high frequency clock signal to the multiplexor <NUM>. But when the enable signal is low, the clock gate <NUM> may block the high frequency clock signal from the multiplexor <NUM>. As described in further detail below, the clock gate <NUM> may provide the high frequency clock signal to the multiplexor <NUM> during high-power mode and may disable or block it during low-power mode(s), except for a short period of time preceding a transition from a low-power mode to a high-power mode. The clock gate <NUM> may be provided spatially close to the crystal oscillator <NUM> to minimize wiring parasitic that may consume power (as shown using dashed lines in <FIG>).

The clock divider <NUM> may also receive the high frequency clock signal and may divide or scale the high frequency clock signal by an integer (e.g., <NUM>) to generate a low frequency clock signal (e.g., <NUM>). The clock divider <NUM> may generate a low frequency clock signal that is substantially synchronous with corresponding edges of the high frequency clock signal, except for possibly a slight delay (e.g., <NUM>-<NUM> nanoseconds) due to the delay inherent in the circuitry of the clock divider <NUM>. The clock divider <NUM> may also be provided spatially close to the crystal oscillator <NUM> to minimize wiring parasitic that may consume power. In an embodiment described in further detail below (e.g., <FIG>), the clock divider <NUM> may include a plurality of dividers for generating a plurality of low frequency clock signals to be used in a plurality of different low-power modes. A ripple divider may be provided as a low-power component, and ripple dividers may naturally divide by binary ratios. This binary high/low relationship may allow counter segmentation based on binary subsections.

The multiplexor <NUM> (also sometimes referred to as clock switching block) may receive the high frequency clock signal (e.g., from clock gate <NUM>) and the low frequency clock signal (e.g., from clock divider <NUM>). The multiplexor <NUM> may output either the high frequency clock signal during high-power mode or the low frequency clock signal during low-power mode to the system time counter <NUM> and other components. The system time counter <NUM> may maintain a system time that is to be used by a timer-scheduler, for example, for coordinated communications as described herein. During high-power mode, the multiplexor <NUM> may provide the high frequency clock signal, and the system time counter <NUM> may use the high frequency clock to maintain the system time. During low-power mode, the multiplexor <NUM> may provide the low frequency clock signal, and the system time counter <NUM> may use the low frequency clock to maintain the system time. Low-power mode may correspond to a sleep mode. The system time counter <NUM> may also count by a different base depending on the power mode. For example, with the use of a "<NUM>" integer divider, the system time count may be counted <NUM>*25ns every low flow frequency clock during low-power mode and it may be counted by 25ns every high frequency clock during high-power mode. The system time may be used to schedule activities such as sampling a sensor or input pin, toggling an output pin, triggering an actuator, triggering a sequence of operations, etc..

The controller <NUM> may control the switching of the multiplexor <NUM> in a synchronized fashion to maintain timing precision. During a transition from a high-power mode to a low-power mode, the controller <NUM> may switch the output of the multiplexor <NUM> from the high frequency clock signal to the low frequency clock signal synchronized to the next specified edge of the low frequency clock. The specified edge for transition synchronization may be selected to be either a rising or falling edge. Hence, if a rising edge is selected, the controller <NUM> may wait until the next specified rising edge of the low frequency clock signal for the clock-signal switch to maintain precision of the system time. The next specified rising edge may be the subsequent rising edge, or the controller <NUM> may bypass one or more cycles for the next specified rising edge. Likewise, during a transition from a low-power mode to a high-power mode, the controller <NUM> may switch the output of the multiplexor <NUM> from the low frequency clock signal to the high frequency clock signal synchronized to the next specified edge of the low frequency clock. Again, if a rising edge is selected, the controller <NUM> may wait until the next specified rising edge of the low frequency clock signal for the clock. -signal switch to maintain precision of the system time. The next specified rising edge may be the subsequent rising edge, or the controller <NUM> may bypass one or more cycles for the next specified rising edge. The controller <NUM> may be provided as a digital logic circuit.

<FIG> illustrates a flow diagram of an example of portions of a method <NUM> for transitioning from a high-power mode to a low-power mode. The method <NUM> may be executed by the clock circuit <NUM>, for example. At <NUM>, a command may be received to transition from a high-power mode to a low-power mode. The command may be sent by a central processing unit of the device (e.g., processor <NUM>). At <NUM>, the next specified edge of the low frequency clock signal may be detected. The selected edge may be set to be a rising or falling edge of the low frequency clock signal. At <NUM>, in response to detecting the next specified edge of the low frequency clock signal, the output of the clock switching block may be switched from the high frequency clock signal to the low frequency clock signal. At <NUM>, the high frequency clock may be blocked (e.g., by clock gate <NUM>) from reaching the clock switching block (e.g., multiplexor <NUM>). The components of the device may then operate using the low frequency clock signal. For instance, the device may enter a sleep mode. Moreover, the system time may be tracked by incrementing its step based on the low frequency clock period.

<FIG> illustrates a flow diagram of an example of portions of a method <NUM> for transitioning from a low-power mode to a high-power mode. The method <NUM> may be executed by the clock circuit <NUM>. At <NUM>, a command may be received to transition from a low-power mode to a low high mode. The command may be sent by a central processing unit of the device (e.g., processor <NUM>). At <NUM>, the high frequency clock signal may be enabled; for example, the high frequency clock signal may be permitted (e.g., by clock gate <NUM>) to reach the clock switching block (e.g., multiplexor <NUM>). At <NUM>, the next specified edge of the low frequency clock signal may be detected. The selected edge may be set to be a rising or falling edge of the low frequency clock signal. At <NUM>, in response to detecting the next specified edge of the low frequency clock signal, the output of the clock switching block may be switched from the low frequency clock signal to the high frequency clock signal. The components of the device may then operate using the high frequency clock signal Moreover, the system time may be tracked by incrementing its step based on the high frequency clock period. In some embodiments, lower significant bits (LSBs) of a counter may be held static while the upper most significant bits (MSBs) may be incremented.

The system time may then be used to control other operations, such as scheduling communications, obtaining timestamps, etc. For example, the device may enter active mode to send and/or receive messages based on coordinated communication protocol, where communications are scheduled at specified times. In lower-power mode, the device may use the system time to obtain accurate timestamps.

By synchronizing the transition from high-to-low and low-to-high modes on the specified low frequency clock edges, timing precision is maintained. The timer-scheduler of the device may maintain timing precision of the high frequency oscillator even when the high frequency clock signal is not available in low-power modes. Thus, timing errors due to clock domain crossings may be reduced or eliminated.

As mentioned above, a device may operate in different low-power modes. Each low-power mode may operate using a different low frequency clock signal. <FIG> illustrates an example of portions of a clock circuit <NUM> for use in a high-power mode and different low-power modes. The clock circuit <NUM> may include a crystal oscillator <NUM>, a clock gate <NUM>, a multiplexor <NUM>, and a system time counter <NUM>, as described above with reference to <FIG>. The clock circuit <NUM> may also include a clock divider circuit <NUM> and controller <NUM> to provide the different low frequency clock signals.

The clock divider circuit <NUM> may include a clock divider and a second multiplexor. The clock divider circuit <NUM> may receive the high frequency clock signal. The clock divider in the clock divider circuit <NUM> may divide or scale the high frequency clock signal by different integers to generate different low frequency clock signals, and the second multiplexor may output a selected low frequency clock signal. The output of the second multiplexor may be controlled by the controller <NUM>. The low frequency clock signals may be multiples of each other. For example, a first low frequency clock signal may be generated by dividing the high frequency clock signal by a first integer. A second low frequency clock signal may be generated by dividing the first low frequency clock signal by a second integer. The third low frequency clock signal may be generated by dividing the second low frequency clock signal by a third integer and so forth. The clock divider circuit <NUM> may generate low frequency clock signals that are substantially synchronous with corresponding edges of the high frequency clock signal, except for possibly a slight delay (e.g., <NUM>-<NUM> nanoseconds) due to the delay inherent in the circuitry of the clock divider circuit <NUM>. The clock divider circuit <NUM> may also be provided spatially close to the crystal oscillator <NUM> to minimize wiring parasitic that may consume power.

As described above, the multiplexor <NUM> (also sometimes referred to as clock switching block) may receive the high frequency clock signal (e.g., from clock gate <NUM>) and the selected low frequency clock signal (e.g., from clock divider circuit <NUM>). The multiplexor <NUM> may output either the high frequency clock signal during high-power mode or the selected low frequency clock signal during low-power mode to the system time counter <NUM> and other components. The system time counter <NUM> may maintain a system time that is to be used by a timer scheduler, for example for coordinated communications as described herein. During high-power mode, the multiplexor <NUM> may provide the high frequency clock signal, and the system time counter <NUM> may use the high frequency clock signal to maintain of the system time. During each of the low-power modes, the multiplexor <NUM> may provide the selected low frequency clock signal, and the system time counter <NUM> may use the selected low frequency clock signal to maintain the system time. The different low-power modes may correspond to different levels of low operating modes (e.g., sleep mode, standby mode, hibernating mode, etc.).

The controller <NUM> may control selection of the low frequency clock signal and the switching of the multiplexor <NUM> in a synchronized fashion to maintain timing precision, as described herein (e.g., <FIG> and <FIG>). For example, during a transition from a high-power mode to a low-power mode, the controller <NUM> may switch the output of the multiplexor from the high frequency clock signal to the low frequency clock signal synchronized to the next specified edge of the low frequency clock. The edge for transition synchronization may be selected to be either a rising or falling edge. Likewise, during a transition from a low-power mode to a high-power mode, the controller <NUM> may switch the output of the multiplexor from the low frequency clock signal to the high frequency clock signal synchronized to the next specified edge of the low frequency clock. The controller <NUM> may be provided as a digital logic circuit.

The controller, as described herein, may be implemented using different configurations of logic circuits, processors, and the like. <FIG> illustrates an example of portions of a clock circuit <NUM> with a digital logic circuit configuration for the controller. The clock circuit <NUM> may include a crystal oscillator <NUM>, a clock gate <NUM>, a clock divider <NUM>, a multiplexor <NUM>, a system time counter <NUM>, and a controller <NUM>. The crystal oscillator <NUM> may generate a high frequency clock signal as described herein (e.g., <NUM>).

The clock gate <NUM> may receive the high frequency clock signal and may provide the high frequency clock signal (hf_xtal_clk) to the multiplexor <NUM> based on an enable signal (xo_40mhz_clk_out_en_lv). The clock gate <NUM> may be provided as a NAND gate. The controller <NUM> may generate the enable signal to control the clock gate <NUM>. As described in further detail below with reference to <FIG> and <NUM>, the clock gate <NUM> may provide the high frequency clock signal to the multiplexor <NUM> during high-power mode and may disable or block it during low-power models), except for a short period of time preceding a transition from a low-power mode to a high-power mode. The clock gate <NUM> may be provided spatially close to the crystal oscillator <NUM> to minimize wiring parasitic that may consume power.

The clock divider <NUM> may also receive the high frequency clock signal and may divide or scale the high frequency clock signal by an integer (e.g., <NUM>) to generate a low frequency clock signal (lf_xtal_clk). The clock divider <NUM> may generate a low frequency clock signal that is substantially synchronous with certain edges of the high frequency clock signal, except for possibly a slight delay (e.g., <NUM>-<NUM> nanoseconds) due to the delay inherent in the circuitry of the clock divider <NUM>. The clock divider <NUM> may also be provided spatially close to the crystal oscillator <NUM> to minimize wiring parasitic that may consumes power.

The multiplexor <NUM> (or clock switching block) may receive the high frequency clock signal (e.g., from clock gate <NUM>) and the low frequency clock signal (e.g., from clock divider <NUM>), The multiplexor <NUM> may output either the high frequency clock signal during high-power mode or the low frequency clock signal during low-power mode to the system time counter <NUM> and other components. The system time counter <NUM> may maintain a system time that is to be used by a timer scheduler, for example for coordinated communications as described herein. During high-power mode, the multiplexor <NUM> may provide the high frequency clock signal, and the system time counter <NUM> may use the high frequency clock to maintain the system time. During low-power mode, the multiplexor <NUM> may provide the low frequency clock signal, and the system time counter <NUM> may use the low frequency clock to maintain the system time. Low-power mode may correspond to a sleep mode.

The controller <NUM> may control the switching of the multiplexor <NUM> in a synchronized fashion to maintain timing precision. The controller <NUM> may include a NOT gate <NUM>, a first D flip-flop <NUM>, a second D flip-flop <NUM>, and a NAND gate <NUM>. The NOT gate <NUM> may invert a hf_osc_pd_enb signal, which may be indicative of a command for whether the device is in high or low-power mode; the output of the NOT gate <NUM> may be provided as an input to the first D flip-flop <NUM> and the NAND gate <NUM>. The low frequency clock signal (lf_xtal_clk) may also be provided as an input into the first D flip-flop <NUM>. The output of the first D flip-flop (hf_osc_pd_en_lf_negedge) may control the switching of the multiplexor <NUM>. The output of the multiplexor is represented by clk_var. In this example, the switching between the different modes is conducted on the falling (negative) edge of the low frequency clock signal, as described herein. The second flip-flop <NUM>, which may receive the output of the first D flip-flop <NUM> and the low frequency clock (If_xtal_clk), and the NAND gate <NUM> may generate the enable signal for controlling the clock gate <NUM>.

<FIG> is a timing diagram illustrating a transition from a high-power mode to a low-power mode for a clock circuit as described herein. For example, the timing diagram may illustrate the operations of the clock circuit <NUM> of <FIG> during a transition from a high-power mode to a low-power mode. The timing diagram shows a low frequency clock <NUM>, which may be the output of the clock divider <NUM>; a gated high frequency clock output <NUM>, which may be the output of the clock gate <NUM>; a switch clock command <NUM>; a synched command <NUM>, which may represent a command to switch clocks synchronized to a falling edge of the low frequency clock; an enable command <NUM> for the clock gate <NUM>; and an output <NUM>, which may be the output of the multiplexor <NUM>. As shown and discussed above, the transition from the high-power mode to low-power mode is made on a falling edge of the low frequency clock. That is, the transition is made on the subsequent falling edge of the low frequency clock <NUM>) after the command for going to low-power mode is received (<NUM>). Moreover, after the transition, the clock gate <NUM> may disable the high frequency clock signal (<NUM>).

<FIG> is a timing diagram illustrating a transition from a low-power mode to a high-power mode for a clock circuit as described herein. For example, the timing diagram may illustrate the operations of the clock circuit <NUM> of <FIG> during a transition from a low-power mode to a high-power mode. As shown and discussed above, the transition from the low-power mode to high-power mode is made on a falling edge of the low frequency clock. That is, the transition is made on the subsequent falling edge of the low frequency clock (<NUM>) after the command for going to high power is received (<NUM>). Moreover, before the transition, the clock gate 810may enable the high frequency clock signal (<NUM>).

Claim 1:
A clock circuit (<NUM>) comprising:
a clock (<NUM>) to generate a first clock signal having a first frequency;
a clock divider (<NUM>) to divide the first clock signal to generate a second clock signal output at a second frequency, wherein the first frequency is higher than the second frequency;
a multiplexor (<NUM>) to receive the first and second clock signals as inputs;
a controller (<NUM>) coupled to the multiplexor (<NUM>) to control the multiplexor (<NUM>) to output the first clock signal during a first mode and to output the second clock signal during a second mode,
wherein switching between the first clock signal and second clock signal by the multiplexor (<NUM>) is performed based on a select edge of the second clock signal;
characterized by:
a system time counter (<NUM>) coupled to the multiplexor (<NUM>) to maintain a system time count, wherein the system time counter (<NUM>) is configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.