Patent Description:
The PCB and the electrical components are sometimes collectively called a printed circuit board assembly (PCBA). Generally, the terms PCB and PCBA are used interchangeably, i.e., the term PCB can denote the board itself, as well as an assembly of the board and the electrical components that are carried by the board.

Testing of the PCBs (or the PCBAs) can be in-circuit (in-circuit test or ICT) or functional (functional test or FT). In-circuit test performs a "schematic verification" by testing individual components of the PCB one at a time. For example, resistance, voltage drop, polarity, etc., of the individual electrical components are measured and compared against expected values for that component. Typically, the in-circuit test is not done "at speed," and does not verify interoperability of the electrical components. However, the in-circuit test can still be effective in finding manufacturing defects of the PCB, the electrical components, or the defects in the attachment of the components to the PCB. For example, the in-circuit test may detect solder shorts, missing components, wrong components, improperly attached components (e.g., a diode that is rotated <NUM>°), or open connections. Most of the in-circuit tests are performed without the PCB being powered, thus avoiding the conditions that could damage components. Test programming effort can be minimized as the programming consists of switching the test instruments to connect to the PCB via a bed-of-nails (BON) fixture.

Functional testing is designed to assure that circuitry functions within the specifications. Such testing may be done "at speed" through the PCB connectors (e.g., edge connectors on the PCB) and/or the BON fixture. Functional tests can identify functional defects within the PCB as well as the defects in the components. For example, functional test may assess functionality of the PCB while applying marginal power supply voltage and/or current to an IC to assess functionality of the IC, may determine power consumption of the PCB or a component on the PCB during operation, may test operation of the components at their specification frequency, etc..

However, the test programs for functional test require a thorough understanding of the device under test (DUT) performance, thus programming costs are typically higher than those for the in-circuit test. Furthermore, with conventional BON systems, the programming has to be repeated for every new PCB design, because the pins of the BON (e.g., pogo pins) are wired back to the corresponding pins of the instruments in the PCB testers, and the instruments must be reprogrammed for the next PCB design. Additionally, some high frequency tests may not be possible due to relatively large distance from the instruments in the PCB tester to the PCB under test (also referred to as "unit under test" or UUT). This relatively large distance may cause significant attenuation of the signals in the cables that run from the mainframe to the UUT. Accordingly, systems and methods for improved in-circuit test and functional test are needed.

The foregoing aspects and many of the attendant advantages of the inventive technology will become more readily appreciated and better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:.

Specific details of several embodiments of the PCB testers are disclosed herein. The inventive technology relates to PCB testers that are configurable, and can perform functional tests on multiple PCBs in parallel. More particularly, the present technology relates to PCB testers that are configurable, and can perform both in-circuit test (ICT) and functional test (FT) on multiple PCBs in parallel. A significant portion of the test electronics may be located on the test fixture itself (i.e., close to the PCBs under test, also referred to as units under test or UUTs). As a result, signal/power path to the UUTs is shortened. In some embodiments, the tester may test multiple PCBs in parallel. These PCBs may have different configurations (e.g., different designs).

In some embodiments, the test electronics may be distributed over master/slave modules (also referred to as remote test peripherals or RTPs). Several RTP master/slave module chains may be connected through USB link or other fast serial link to an universal serial bus (USB) hub, and further to a host controller (i.e., a computer or a server). The RTP master/server modules (RTPM/RTPS) in the chain can communicate through a serial link, for example, an <NUM>-bit asynchronous serial link. The RTPM/RTPS module chains can be reconfigured or reprogrammed depending on the configuration and number of the UUTs tested in parallel, without having to replace the RTPM/RTPS modules.

In some embodiments, the test fixture is "self-aware," i.e., capable of reporting its configuration back to the control system. For example, the test fixture may report configuration of the RTP master/slave modules, number of the boards, assignments of the pin contacts, revision number of the master/slave module, etc..

In some embodiments, the test program (also referred to as a test sequence) is loaded directly on the test fixture. For example, the test fixture may include memory chips for storing the test program and data files having the test point assignments.

A person skilled in the art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below.

<FIG> is a partially schematic, isometric view of a PCB tester <NUM> in accordance with prior art. The PCB tester <NUM> includes a mainframe <NUM> and a test fixture <NUM>. The conventional test fixture is typically built as a mechanical "bed of nails" (BON) fixture that is specifically designed for a particular layout of the UUT. The mainframe <NUM> includes electronics that sends test vectors and power to a UUT <NUM>. For example, the mainframe <NUM> can include test instruments 13a for checking open/shorts on the UUT <NUM>, and a power supply 13b for powering components <NUM> on the UUT <NUM>.

The test fixture <NUM> includes contact pins <NUM> (e.g., pogo pins) that electrically connect electronics in the mainframe <NUM> with traces <NUM>, and further with components <NUM> of the UUT <NUM>. Additional electrical connectivity between the test fixture <NUM> and the UUT <NUM> is provided through a cable <NUM>.

Test cables <NUM> connect the test instruments and power supplies of the mainframe <NUM> with the test fixture <NUM>. A host computer <NUM> controls the operation of the mainframe <NUM> (e.g., sending the test vectors through the cables <NUM>) and interprets the results of the test (e.g., presence/absence of defective components on the UUT <NUM>).

However, a relatively long length of the test cables <NUM> can degrade signal integrity due to noise and transmission line effects, especially for the high frequency testing.

<FIG> is a partially schematic view of a test fixture in accordance with prior art. The test fixture <NUM> can include an assembly of plates 18a and 18b for improved vertical alignment of the contact pins <NUM>. The mainframe tester <NUM> provides test vectors and/or power through test cables <NUM>. In operation, the contact pins <NUM> make contact with the components <NUM> or the traces of the UUT <NUM> to provide electrical connectivity to/from the mainframe tester <NUM>. After completing the testing of the UUT <NUM>, the tested UUT is removed and the next UUT is loaded to make contact with the test fixture <NUM>.

<FIG> is a block diagram of a PCB tester <NUM> in accordance with an embodiment of the present technology. The PCB tester <NUM> includes a test fixture <NUM> and a control system <NUM>.

According to the invention, the control system <NUM> includes an ICT (in-circuit tester)/MDA (manufacturing defects analyzer) <NUM> and a host computer (host controller) <NUM>. The control system <NUM> may also be referred to as the ICT/MDA system <NUM>. A host computer <NUM> provides an operator interface for communicating with the ICT/MDA system <NUM> through a bus <NUM>, which may be a USB connection or other high speed serial bus.

The test fixture <NUM> can be connected with the control system <NUM> through one or more high speed serial buses <NUM>, for example USB buses. In addition to the control/test signals received from the control system <NUM>, the test fixture <NUM> may generate test signals and power for functional test (FT) of the UUTs <NUM> through one or more RTPM/RTPS chains <NUM>/<NUM> carried by the test fixture. The test fixture <NUM> can be connected to a UUT panel <NUM>, which includes one or more PCBs <NUM> (UUTs <NUM>).

In operation, the ICT may, for example, detect opens/shorts on the UUTs <NUM>, and the MDA may evaluate manufacturing defects of the UUTs <NUM>. Some examples of the ICT tests in combination with the functional test (FT) are described below.

In some embodiments, much of the electronics for the functional test (FT) resides within the test fixture <NUM>, therefore minimizing the number of test cards in the control system <NUM>. The FT hardware of the test fixture <NUM> can include one or more RTP master (RTPM) modules <NUM>, each controlling one or more RTP slave (RTPS) modules <NUM>-i. The RTPS modules can perform a variety of tasks including, for example, power regulation, load switching, current/voltage sensing, UCT (universal counter/timer), logic analysis / playback, LED optical testing, RF (radio frequency) testing, HIPOT (high potential) testing, relay control, and customer-specific functions.

Furthermore, the RTP bus <NUM> (for example, a universal asynchronous receiver-transmitter or UART) can support a relatively simple addition of the RTPS module, therefore enabling expansion of the functional tests as required by different number of UUTs <NUM> from one test to another. In many embodiments, the number of RTPM/RTPS chains and the composition of the RTPS modules can be changed to suit a specific test or a specific UUT. As a result, the tester is modular, scalable and customizable.

In some embodiments, RTPM/RTPS modules are programmable. Therefore, the modules can be reconfigured to test different UUTs (through, for example, Command Descriptors and Pin Information) or reprogrammed with different firmware without replacing the RTPM/RTPS modules. Furthermore, since the RTPM/RTPS modules are carried by the test fixture <NUM>, changes of the control system <NUM> can be minimized for different configurations/numbers of the UUTs <NUM>.

In operation, the RTPS modules can communicate with UUTs through buses <NUM>, e.g., CAN (controller area network), LIN (local interconnect network), I<NUM>C (inter integrated circuit), I<NUM>S (inter integrated sound), JTAG (join test action group), SPI (serial parallel interface), UART (universal asynchronous receiver-transmitter), etc. Stated differently, the RTPM module establishes a control channel over the RTPS module through the RTP bus <NUM>. These bus communication protocols can support a variety of RTPMs/RTPSs having different test capabilities. Generally, the UUTs <NUM> that are being tested in parallel have the same design. However, in some embodiments, the UUTs having different designs may be tested simultaneously through a single fixture by differently programming the RTPM/RTPS modules that interface with different UUT designs.

In many embodiments, tester quoting process is simplified for the tester that has modular RTPM/RTPS design. For example, the test fixture <NUM> that carries standardized RTPM/RTPS modules <NUM>/<NUM> is generally easier to quote than a custom-designed test fixture <NUM> having the same capability. Furthermore, quoting the test fixture <NUM> that carries standardized RTPM/RTPS modules <NUM>/<NUM> can be more precise.

Conventional FT systems reserve a block of testpoint numbers which may not correspond to the testpoint numbers that the tester instruments are actually connected to. Therefore, additional knowledge is required to connect the wires of the tester to the testpoints of the UUTs. In some embodiments of the inventive technology, the testpoint information may be stored with the test program (the test sequence) directly on the test fixture <NUM>, for example, on a memory storage device <NUM> (e.g., flash memory, EPROM, etc.) of the test fixture <NUM>. The testpoint information may be used for the functional test programs and to simplify wiring of the fixture <NUM>. The testpoint information may assist with auto-generation of a netlist template, which the user can use to fill in appropriate testpoint information for the fixture. Furthermore, the testpoint information can be used for generating wiring instructions, fixture hardware diagrams and/or for self-test of the RTPM/RTPS modules on the test fixture.

In some embodiments, the UUTs <NUM> are tested in less time because the communication between the control system <NUM> and the test fixture <NUM> is minimized (e.g., no need to transfer the listings of the testpoints from the control system <NUM> to the test fixture <NUM>). In operation, the test results may be aggregated for several UUTs <NUM>, and then collectively sent to the control system <NUM> over the high speed serial bus <NUM> to further minimize data transfers between the control system and the test fixture.

In some embodiments, the RTPM module <NUM> can perform a system query to, for example, determine the number and type of the RTPS modules <NUM> in the RTP fixture. The system query may also determine particular addresses of the RTPM/RTPS modules, and the corresponding features that specific RTPM/RTPS module support. These capabilities enable the test fixture to be self-aware.

In some embodiments, the RTPS modules <NUM> also include commands. For example, an RTPS module <NUM> may include a default set of commands, which can be used for querying information pertaining to each module (e.g., board information, pin information, command descriptions, etc.), therefore allowing the RTP fixture <NUM> to be self-discoverable. For example, information stored in RTPS modules <NUM> may allow the user or other modules <NUM>/<NUM> to:.

In some embodiments, the RTPM module <NUM> and/or RTPS module <NUM> may carry hardware that enables the microcontroller to perform self-test diagnostic tests of on-board circuitry to detect issues with the RTPM/RTPS modules (e.g., erroneous wiring, hardware failures, power issues, etc.). Some examples of self-tests executed by the RTPS module <NUM> are:.

<FIG> is a block diagram of a PCB tester in accordance with an embodiment of the present technology. The illustrated PCB tester <NUM> includes the control system <NUM> and the test fixture <NUM>. Signals/power from the test fixture <NUM> to the UUTs <NUM> can be routed through contact pins <NUM>, optical connections <NUM>, solenoids <NUM>, and/or wirelessly. In some embodiments, the control system <NUM> is connected to the test fixture <NUM> through a transfer block <NUM> (e.g., paired connectors suitable for high speed signals).

In some embodiments, the RTPM module <NUM> serves as a master device in the RTP bus chain, the RTPS modules <NUM> being attached-to and controlled-by the RTPM module <NUM>. In some embodiments, during the power-on sequence for the test fixture <NUM> or when a bus reset is requested, the RTP modules undergo an auto-addressing phase to automatically detect how many RTPS modules <NUM> are included in the RTP chain, and what their respective positions are within the chain.

In some embodiments, the per-channel circuitry of the RTPS module is duplicated for each channel supported by the RTPS module. The channels of the RTPS module may be capable of operating independently from one other. The microcontroller firmware of the RTPS module may disable/enable the independent channels, or certain features could be applied to one enabled channel and not others. In some embodiments, the RTPS modules are capable of simultaneous (i.e., parallel) functional testing of multiple or all UUTs <NUM>, therefore increasing the throughput of the PCB tester <NUM>.

With the conventional testers, a relatively long distance between the sources of the signals and the UUTs limits the signal frequency and/or power available for testing the UUTs. In some embodiments of the present technology, for example with high-speed testing of the UUTs <NUM>, a signal sources on the RTPS modules <NUM> are located closer to the UUTs <NUM>, therefore reducing issues that are caused by long transmission lines (e.g., degraded signal integrity).

The RTPS modules <NUM> may be designed to interface with and test multiple UUTs <NUM> connected to a channel (also referred to as a "data channel"). For example, the individual channels of the RTP module <NUM> may utilize one or more contact pins <NUM>, optical connections <NUM>, solenoids <NUM>, and/or wireless connections to transfer signals to/from the UUTs <NUM>. In many embodiments of the present technology, the distance between the RTPS modules <NUM> and the UUTs <NUM> is shortened because the RTPM/RTPS modules are carried by the test fixture <NUM>.

In some embodiments, the tester <NUM> is configured to execute both the ICT and the FT. For example, for the ICT test, the ICT/MDA <NUM> can be wired directly through traces <NUM>-<NUM> to some of the contact pins <NUM>. Other pins <NUM> in the ICT test may be connected to the ICT/MDA <NUM> through traces <NUM>-<NUM> and relays <NUM> of the RTPS modules <NUM>. The relays <NUM> may be, for example, electromechanical or solid-state relays (e.g., banks of transistors). The relays may switch the UUTs <NUM> from ICT test (UUT test points directly connected to ICT/MDA <NUM>) to functional test (UUT test points connected to the circuitry of RTPS <NUM>), and vice versa.

In many embodiments, when ICT and FT are combined into one tester <NUM>, the test flow is simplified and accelerated. Furthermore, if the ICT finds problems (e.g., shorts on the UUT), then the select relays may switch to isolate particular parts of the FT circuitry on the RTPS <NUM>, therefore preventing damage to the RTPS modules <NUM>.

In some embodiments, the RTPM <NUM> may be in communication with the controller <NUM> through a bus <NUM>-<NUM> (e.g., high speed serial bus) and in communication with the ICT/MDA <NUM> through a bus <NUM>-<NUM> (e.g., a serial or parallel bus, also referred to as a handshake connection). In some embodiments, the handshake connection <NUM>-<NUM> may be a parallel bus. When exchanging small amounts of data between the ICT/MDA system <NUM> and the RTPM <NUM>, the handshake connection <NUM>-<NUM> may be more agile and faster than a nominally faster USB bus.

The RTPM <NUM> may also include one or more operational amplifiers (OP AMP) and analog to digital converters (A/D). The OP AMPs and A/Ds may be connected to the ICT/MDA <NUM> through an analog bus <NUM>-<NUM>. For some relatively slow-speed UUT tests, for example, a DC test, the bus <NUM>-<NUM> may connect the A/D of the RTPM module to the UUTs through a bus <NUM>-<NUM> (also referred to as "conventional ICT wiring"), or through a bus <NUM>-<NUM> (also referred to as "MDA wiring") and further through the relay bank <NUM> and a bus <NUM>-<NUM> (also referred to as "UUT wiring").

<FIG> shows detail A of <FIG>. In particular, the relay <NUM>-i may connect the UUT <NUM> to either the RTPS module <NUM>-i for the FT or to the ICT/MDA <NUM> for the ICT. In some embodiments, a resistor <NUM> is added in parallel with the relay's path to the ICT/MDA <NUM> to isolate the FT points from the loading capacitance of the wires coming from the ICT/MDA <NUM> (the wires of the bus <NUM>-<NUM>). Additionally, a voltage drop can be measured from the UUT <NUM> to the ICT/MDA <NUM> even when the relay connects the UUT <NUM> with the RTPS <NUM>. As a result, in at least some embodiments, the ICT/MDA <NUM> can determine if the connection from the RTPS to the UUT functions properly (e.g., no opens in the path). In many situations, in absence of the resistor <NUM>, determination about the integrity of the connection from the RTPS to the UUT must be performed manually, resulting in higher cost and longer fixture development/debug times.

<FIG> is a partially schematic isometric view of a PCB tester in accordance with an embodiment of the present technology. In some embodiments, the test fixture <NUM> carries the RTPM/RTPS chain that is vertically stacked. For example, the RTPM module <NUM> may support one or more RTPS modules <NUM> in a vertical stack. The uppermost RTPS module <NUM> in the stack contacts a test interface <NUM> that supports the UUTs <NUM>. In some embodiments, the contact pins <NUM> of the test interface <NUM> touch the test points of the UUTs <NUM> to establish electrical connectivity. The electrical connectivity may be established with mechanical pins, optical contacts, solenoids, or wireless connections. In some embodiments, vertical stacking of the RTPM/RTPS chain results in a more compact test fixture. Furthermore, a reduced distance between the RTPS modules and the UUTs decreases signal/power degradation because of the shortened electrical path from the RTPS modules to the UUTs.

<FIG> is a schematic view of RTP module mounting holes in accordance with an embodiment of the present technology. In some embodiments, the RTPMs and RTPSes may include a standardized distribution of mounting holes <NUM>. For example, the rows and columns of the mounting holes <NUM> may be separated by standardized widths W and heights H. Suitable standoffs may maintain vertical offsets between individual RTPM/RTPS modules.

<FIG> is a block diagram of RTPM/RTPS chains in accordance with an embodiment of the present technology. The illustrated RTPM/RTPS chains are individually connected to a fast serial hub <NUM> through a high speed serial bus 122A, and further to the control system <NUM> with a high speed serial bus 122B. In some embodiments, the high speed serial buses 122A/122B are USB buses. Multiple RTPM/RTPS chains in parallel may allow for a higher data throughput. For example, conventional functional tests are performed on one UUT at a time. As a result, with the conventional systems, time required to test the entire batch of the UUTs <NUM> generally corresponds to the time required for testing an individual UUT multiplied by the number of UUTs <NUM> in the UUT panel <NUM>. In some embodiments of the present technology, a single RTPM/RTPS chain <NUM>/<NUM> can test multiple UUTs <NUM> in parallel. Additionally, multiple RTPM/RTPS chains may further increase the parallelism of the test. As a result, multiple UUTs <NUM> can undergo the same FT in the same time as it takes for one UUT <NUM>. Such a capability may be useful for the test processes having strict takt time requirements.

In some embodiments, multiple RTP master/slave chains <NUM>/<NUM> can further increase throughput when, for example, the number of UUTs <NUM> is increased. For example, in some tests three RTPM/RTPS chains <NUM>/<NUM> may be configured to support testing of three UUTs in parallel. When a fourth UUT <NUM> is added to the parallel test, the resources of the existing three RTPM/RTPS chains <NUM>/<NUM> may be reconfigured to support testing of the fourth UUT without having to add additional RTPM/RTPS chains. In contrast with the embodiments of the inventive technology, the addition of another UUT requires adding dedicated test resources to conventional PCB testers.

In some embodiments, the test fixture <NUM> includes the memory storage device <NUM> for storing test programs, test pin assignments, test vectors, and/or other data for testing the UUTs <NUM>. In some embodiments, the test fixture <NUM> communicates with the ICT/MDA <NUM> through the host controller <NUM>.

<FIG> is a block diagram of connections between the control system <NUM> and the test fixture <NUM> in accordance with an embodiment of the present technology. In some embodiments, the control system <NUM> includes a relay switching matrix <NUM> that may be a solid relay switching matrix (e.g., a bank of transistors). Depending on the isolation requirements of the testpoints on the UUTs <NUM>, the relay switching matrix <NUM> may connect the testpoints on the UUTs <NUM> to the RTPM/RTPS chain <NUM>/<NUM> without isolation or with isolation. For example, the relays may be closed to directly connect the testpoints on the UUTs <NUM> with the ICT/MDA <NUM> for the ICT (e.g., testing opens/shorts, resistance measurements, etc.). Analogously, the UUT testpoints that are used in conjunction with FT may require isolation or local switching. In some embodiments, the test fixture <NUM> includes in-system programming (ISP) hardware, for example ISP controller and/or ISP buffers. In some embodiments, the ISP hardware may include MultiWriter.

In some embodiments, the test fixture <NUM> may include RTPS modules <NUM> that include the functionality of power control (e.g., the RTPS <NUM>-<NUM>) or analog divider (e.g., the RTPS <NUM>-<NUM>). In some embodiments, the test fixture <NUM> includes RTPS modules with other functions, for example:.

<FIG> is a block diagram of connections among RTPM and RTPS modules in accordance with an embodiment of the present technology. The RTPM/RTPS modules <NUM>/<NUM> may be carried by the test fixture <NUM> (not shown). In some embodiments, the RTPM/RTPS modules <NUM>/<NUM> have their upstream ports connected ("chained") to the corresponding downstream ports through RTP bus <NUM>. For example, a downstream transmitter node TXD of the RTPM module <NUM> may be chained to an upstream receiver node RXU of the RTPS module <NUM>-<NUM>. As another example, a downstream receiver node RXD of the RTPS module <NUM>-<NUM> may be chained to an upstream transmitter node TXU of the RTPS module <NUM>-<NUM>. On the upstream end of the RTPM/RTPS module chain, the RTPM module <NUM> has only the downstream nodes TXD/RXD for connecting with the rest of the chain. Analogously, on the downstream end of the RTPM/RTPS chain, a termination may be added to short the TXD to the RXD node of the RTPS module <NUM>-<NUM>. In some embodiments, the RTPS module <NUM> may automatically detect which of the two ports is upstream or downstream, resulting in simpler chaining of the modules.

In operation, the RTPM module <NUM> may initiate communication over the RTP bus <NUM>. In some embodiments, the RTPM and RTPS modules implement a common communication protocol, whereby the RTPM module can select and initiate commands, and transfer data to one or more RTPS modules. For example, the RTPM module <NUM> may communicate to the RTPS modules <NUM> to obtain information about the RTPS modules: the module board number and board revision, build revision number, communications driver version information, descriptions, and usage information about any of the supported command handler functions (parameter data, return data), and information about the number of output channels and respective header pins. The RTPM module <NUM> may also control the RTPS modules <NUM> to: modify communications settings, download error reporting information for RTP bus communication errors, perform a soft reset of the RTPS module, read from the device memory, manipulate the device memory, etc..

In some embodiments, the RTP bus is an <NUM>-bit asynchronous serial bus. When the RTP modules are powered on, the RTPM module <NUM> may initiate a synchronization phase, during which the RTPS modules <NUM> are synchronized to the bus <NUM>. The synchronization phase can force all devices on the RTP bus <NUM> into the same communication state. When this phase is completed, the RTPS modules <NUM> can start accepting command packets from the RTPM module <NUM>, thereby the internal functions of the individual RTPS modules <NUM> become available to the RTPM module <NUM> and the controller <NUM>.

In some embodiments, each RTPS module <NUM> includes two <NUM>-bit multiplexers MPLX for outputting upstream TXU and downstream TXD signals. The multiplexers MPLX may be controlled by the signals TXD_EN and TXU_EN. Depending on the state of these two signals, the RTPS can be in one of the four modes described in Table <NUM> below.

<FIG> is a block diagram of the RTPS module <NUM> in accordance with an embodiment of the present technology. With the illustrated embodiment, a microcontroller MICRO is directly connected to fewer points on bus <NUM>, because the microcontroller MICRO is not connected to the RXD and TXD ports any more. Instead, the RXD and TXD ports are connected to the multiplexers MPLX.

<FIG> is a block diagram of an RTPM module <NUM> in accordance with an embodiment of the present technology. In some embodiments, the RTPM module <NUM> includes several inputs/outputs: analog input bus, USB input and handshaking signal port at its upstream side, and RTP bus TX/RX ports, flag (FLAG) and reset (RESET) ports on its downstream side.

The RESET port may drive a hard reset of the RTPS boards. In response, the RTP hardware is configured into a known reset state. The FLAG port may be pulled up by the RTPM module <NUM>, and may be programmed as an interrupt request (IRQ) pin for coordinating tasks between RTPM/RTPS modules. In some embodiments, the FLAG pin also provides a conduit of passing control of RTPS module features to other electronics of the test fixture <NUM>.

The RTPM module <NUM> may also include a general purpose input/output (GPIO) header <NUM> to provide access directly to port pins on the microcontroller MICRO. In some embodiments, the GPIO header <NUM> may be used for controlling in-fixture signals. In other embodiments, the GPIO header may be used for connections directly to the contact pins.

In some embodiments, the analog input port of the RTPM module <NUM> can be an <NUM>-channel analog input port. For example, the analog input port may be configured to measure differential voltages or single-supply voltages.

In some embodiments, the RTPM module <NUM> is connected to the control system <NUM> via the USB port. The USB port may also provide power to the module.

On initialization, the RTPM module <NUM> may synchronize the RTPS modules <NUM> and may perform a full hardware scan of the devices contained on the RTP bus. The RTPM module may also collect information about the module part numbers, supported commands, and pin information, which can be stored in a memory (e.g., the memory storage device <NUM>).

In some embodiments, the stored information may be used to check against test programs, and can be used to detect proper hardware configuration and proper functions of the test fixture <NUM>. Furthermore, the RTPM software may store a hash of the RTPS in-memory data, to be used to verify that the test fixture <NUM> includes the proper hardware and firmware during the run of any test program.

In some embodiments, the hardware scan compares configurations of the RTPM/RTPS modules in the fixture to the hardware listing in the specification file. In general, if differences between the real and expected hardware configurations are detected, the scan fails. The hardware scan may also provide a list of detected hardware differences to the operator. In some embodiments, an operator may load description of the expected hardware from a file. In some embodiments, the detected hardware configuration is saved as a hardware descriptor in a dedicated file.

<FIG> is a block diagram of an RTPS module <NUM> in accordance with an embodiment of the present technology. In some embodiments, the RTPS module <NUM> may be powered from a DC power supply using, for example, a 12V power connector. Additionally, the RTPS module <NUM> may include DC-to-DC converters to provide power for the on-board electronics. The operation of the upstream and downstream port connectors, the RESET pin, and the FLAG pin may be similar to those described with reference to <FIG> and <FIG>.

In some embodiments, the RTPS module <NUM> includes module-specific circuitry that is tailored for each RTPS variant to facilitate specific function of that module (e.g., output buffers, voltage translators, transceivers, etc.). The RTPS module <NUM> may include multiple test channels (Ch1 TPs, CH2 TPs, etc.) for testing one or more UUTs <NUM>. In some embodiments, the circuitry on the RTPS module <NUM> is duplicated for each test channel supported. The contact pins <NUM> may be assigned to the individual test channels (Ch1 TPs, CH2 TPs, etc.) of the UUT.

In some embodiments, the RTPS module <NUM> may use a communications driver to control an upstream and downstream TX/RX ports, and process telegrams transmitted over those ports. The RTPS module <NUM> may also control its own functions, for example, control an SPI or I2C device, turn on or off timer or pin edge/level detection interrupts, toggle various GPIO pins high or low, read the states of GPIO pins or on-chip ADCs, coordinate measurements with other RTPS modules, reprogram the RTPS module firmware, and/or perform self-test routines.

Claim 1:
A tester (<NUM>) for printed circuit boards, "PCBs", comprising:
a control system (<NUM>) comprising a host controller (<NUM>); and
a test fixture (<NUM>) having a plurality of electrical contacts (<NUM>) for contacting the PCBs that are units under test (<NUM>), "UUTs", wherein the test fixture carries:
a remote test peripheral master, "RTPM", module (<NUM>), wherein the RTPM module is configured to communicate with the host controller through a high speed serial bus (<NUM>-<NUM>); and
a remote test peripheral slave, "RTPS", module (<NUM>), wherein the RTPM module and the RTPS module are serially connected through a remote test peripheral, "RTP", serial bus (<NUM>);
wherein the RTPS module is configured to communicate with the UUTs, and the RTPM module is configured to establish a control channel over the RTPS module through the RTP serial bus (<NUM>);
characterized in that:
the control system includes an in-circuit tester and manufacturing defects analyzer (<NUM>), "ICT/MDA", and
the tester further comprises a plurality of relays (<NUM>) connecting the ICT/MDA with the RTPS module.