Patent Description:
The development of semiconductor technology enables integrated circuits (ICs) with smaller, faster and more transistors. The development gives advantages, such as the possibility to implement more functionality to ever-increasing performance. There are, however, growing challenges to avoid malfunctioning. Smaller and faster transistors lead to tighter margins, both in device sizes and timing, which, in combination with higher transistor count, increase the need of testing, tuning, configuration, and so on.

Embedded (on-chip) features, often referred to as instruments, are increasingly used at different stages through the life cycle of ICs: from prototype debug, test and validation to in-field monitoring and test. The number of instruments in modern ICs increases and can be in order of thousands.

<NUM> and IEEE Std. <NUM> were developed to offer flexible and scalable access to embedded instruments. The flexibility to access arbitrary instruments is achieved by dynamically configuring the active scan-path so that only desired instruments are included, for example by means of segment insertion bits (SIBs). The standards include two description languages, instrument connectivity language (ICL) and procedural description language (PDL). ICL describes how instruments are interconnected. PDL describes how to operate on instruments. The access to reconfigurable scan networks is typically performed via the test access port of IEEE Std.

While embedded instruments are needed to test, tune, and configure ICs throughout its lifetime, the flexibility in accessing these instruments is limited. For example, if a physical implementation of an IEEE Std. <NUM> network changes due to faults, the ICL and PDL need to be updated for the faulty IC. There is thus a need for an improved and efficient solution for access control of instruments of ICs.

<CIT> discloses a position-based scheduling capability that supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain.

<CIT> discloses a method and circuit arrangement that utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.

The present disclosure relates to a system for testing a semiconductor device, localization of faults and work around faults by excluding them from tests. According to a first aspect the present disclosure relates to a system for accessing a plurality of instruments embedded in a semiconductor device, the system comprising:.

Preferably the test controller is located outside the semiconductor device, whereas the test block is a hardware component placed between the semiconductor device boundary and the instruments, which may be reconfigurable scan networks.

The present disclosure describes systems and methods for test and repair of faulty elements of the semiconductor device and repair of the same. The term 'repair' does not imply an actual physical repair of the semiconductor device but repairing the functionality of the instrument in order to perform the test. A further advantage of the presently disclosed system is that, in the case where one or more instruments are broken or non-functional in any way, the remaining instruments in the semiconductor device can still be used.

Instruments may be accessed by a SIB control register (SCR), operation commands for each instrument, an instrument control register (ICR), and the length of instruments - Instrument length memory (ILM). One advantage of the presently proposed access control is the possibility to:.

The present disclosure further relates to a method for accessing a plurality of instruments embedded in a semiconductor device, the method comprising the steps of:.

As would be understood by a person skilled in the art, the system for testing a semiconductor device may be configured to perform any step of the method for testing a semiconductor device or method for accessing a plurality of instruments embedded in a semiconductor device and vice versa.

The invention will in the following be described with reference to the accompanying drawings, which are exemplary and not limiting to the presently disclosed system and method for accessing a plurality of instruments embedded in a semiconductor device.

The present disclosure relates to a system for accessing a plurality of instruments embedded in a semiconductor device. Preferably the system comprises a hardware interface, such as a test access port or a functional port, configured to access a control mechanism, such as segment insertion bits, for controlling the the plurality of instruments and a test controller for testing the semiconductor device or generating test patterns for the semiconductor device. The hardware interface may be a dedicated test port, such as IEEE Std. <NUM> (JTAG), or a functional port, such as UART, SPI, I2C etc. The test controller may comprise an instrument connectivity language and a procedural description language configuration for operating the instruments. The IEEE Std. <NUM> standard introduces two description languages, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). The purpose of PDL is to describe the operations of the instruments. The ICL is used to describe the characteristics of the instruments such as data length and position within the network and the requirements for interfacing them.

In a first embodiment the test controller is configured to test at least one functionality of each of the plurality of instruments by accessing the segment insertion bits of the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments. The step of testing at least one functionality of each of the plurality of instruments may comprise generating and shifting a test sequence through scan chains of all instruments. In one embodiment of the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device, the system is configured to automatically exclude faulty scan chains from the scan testing. Moreover, an active scan-path may be configured such that only instruments without faulty scan chains are included in the testing. The test controller may be further configured to, based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration.

In the electronics industry, embedded instrumentation refers to the integration of test and measurement instrumentation into semiconductor chips (or integrated circuit devices). Instrumentation embedded into chips (embedded instrumentation) is employed in a variety of electronic test applications, including validating and testing chips themselves, validating, testing and debugging the circuit boards where these chips are deployed, and troubleshooting systems once they have been installed in the field. Instruments include, but are not limited to bit error rate test (BERT) engines, BIST for logic devices, margining engines, memory BIST, memory test, random pattern generators, scan chains etc. Specifically, the instruments may be reconfigurable scan networks and the testing may be scan testing.

<NUM> enables reconfigurable scan networks which allow only desirable instruments to be included in the active scan-path. Reconfigurable scan networks can become faulty, which may lead to the situation there will be no possibility left to test, trim and configure the IC. In the present disclosure, test and repair of the faulty scan registers is described. Two solutions, based on the hardware and software, to test the reconfigurable scan network, to identify faulty scan registers, and repair the network by excluding the faulty scan register from the network, are provided. In one embodiment the test block in the semiconductor device is configured to exclude faulty hardware parts for specific instruments based on the fault status. According to one embodiment of the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device, the test block in the semiconductor device is configured to replace a faulty hardware part for a specific instrument with a corresponding repair part.

<FIG> shows an embodiment of the presently disclosed system (<NUM>) for accessing a plurality of instruments (<NUM>) embedded in a semiconductor device (<NUM>). The system (<NUM>) comprises a test controller (<NUM>) for testing the semiconductor device (<NUM>) or generating test patterns for the semiconductor device and a test block (<NUM>) embedded in the semiconductor device (<NUM>). The system (<NUM>) further comprises a hardware interface (<NUM>) for accessing segment insertion bits (<NUM>). The hardware interface may be, for example, a dedicated test port, such as IEEE Std. <NUM> (JTAG), or a functional port, such as UART, SPI or I2C. The test controller (<NUM>) comprises an instrument connectivity language (<NUM>) and a procedural description (<NUM>) language configuration for operating the instruments (<NUM>). PDL and ICL may be given as inputs to an Electronic Design Automation (EDA) tool or an embedded controller. The test controller may output test patterns.

<FIG> shows an example of a semiconductor device comprising a test access port and a reconfigurable scan network based on IEEE Std. The embedded instruments are coupled with the scan registers and connected as a reconfigurable scan network based on IEEE Std. The Test Access Port (TAP) of IEEE Std. <NUM> is used to connect the reconfigurable scan network and the outside world. Instead of using dedicated test port, IEEE Std. <NUM> introduces a way to access the scan network with the functional ports. As an example, UART may be used as the functional port, which is shown in <FIG>.

UART is a computer hardware device for asynchronous serial contact, it includes a transmitter and a receiver. The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then reassembles the data.

The IJTAG standard is a methodology for accessing on-chip instrumentations through the reconfigurable scan network. There are different network architectures, such as flat networks, hierarchical networks, multiple networks, and daisy-chained networks. <FIG> shows an example of a flat reconfigurable network. Therefore, the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device may comprises an implementation of an IEEE Std. <NUM> for accessing the instruments.

The system may include a control mechanism for including and excluding instruments in the semiconductor device. A segment insertion bit (SIB) is an example of such a control mechanism, which is used to include or exclude instruments in the reconfigurable network. <FIG> shows an example of a schematic of a SIB. In the example there are three control signals (shift_en, update_en and capture_en) to control a SIB. At the beginning, the control bit in the U flip-flop is '<NUM>'. Therefore, the MUX H will be connected to the TDI port, and the instruments are excluded from the network. If the SIB unit is in shift mode, the shift_en becomes '<NUM>' and MUX K1 will be connected to MUX H. Data will be shifted from the TDI into the S flip-flop at the rising edge of the CLK signal. When the SIB unit is not in shift mode, the shift_en becomes '<NUM>' and the S flip-flop remains its value through the feedback from K1.

If the SIB unit is in update mode, update_en becomes '<NUM>' and MUX K2 is connected to the S flip-flop. In this way, the U flip-flop gets the values saved in the S flip-flop. When the SIB unit is not in update mode, update_en becomes '<NUM>' and the U flip-flop keeps its value through the feedback from K2. If the value in the U flip-flop is '<NUM>', the instrument will be excluded and MUX H will receive the value directly from TDI. If the value stored in the U flip-flop is '<NUM>', the MUX H will be connected to the FSO port and the instrument select signal ToSel will enable the instrument network and the instrument will be included in the scan path.

<FIG> shows an embodiment of the presently disclosed system (<NUM>) for accessing a plurality of instruments (<NUM>) embedded in a semiconductor device. The embodiment comprises a UART, a network controller and a reconfigurable scan network. When the test controller (<NUM>) is to access the reconfigurable network, the test controller will first send the PDL commands to the UART, which will transfer these commands to a network controller (<NUM>). The network controller (<NUM>) will control the reconfigurable network according to these commands. The network controller (<NUM>) may comprise <NUM> parts: an IEEE <NUM> FSM (<NUM>), a SIB control register (SCR) (<NUM>), an instrument length memory (<NUM>) and a discard unit (<NUM>). The IEEE <NUM> FSM is for controlling the shift, update and capture signals. The SCR stores information about which instruments are part of the active scan path and what command is to be executed on them. The ILM holds information about the data lengths of the instruments in the network and the position of each instrument. The Discard Unit may allow the controller to discard garbage bits that are outputted by the network during the CSU cycles.

An iApply command groups a set of commands to specify the way to operate on an instrument such as reading from or writing to the hardware The set of commands may be applied in parallel. Such commands may also be referred to as Level-<NUM> PDL commands. Both the commands are sent by the test controller outside the device under test. The action commands are an iApply command. Setup commands such as iRead or iWrite will be lined up and wait for the action commands.

<FIG> shows a hardware-implemented embodiment of the presently disclosed system (<NUM>) for accessing a plurality of instruments (<NUM>) embedded in a semiconductor device (<NUM>).

The system (<NUM>) comprises a test controller (<NUM>) for testing the semiconductor device (<NUM>) or generating test patterns for the semiconductor device. The system (<NUM>) further comprises a hardware interface (<NUM>). The system (<NUM>) further comprises a test block (<NUM>) embedded in the semiconductor device (<NUM>). The testing of the reconfigurable network (<NUM>) is initiated by an iTest command being sent from the test controller (<NUM>). The iTest command will enable the test block (<NUM>). After the testing process ends, the test block (<NUM>) will get faulty scan registers locations. When the test controller (<NUM>) sends the iRepair command to the UART, the faulty scan registers' locations will be sent to the repair component (<NUM>) in the network controller (<NUM>). After that, when the test controller (<NUM>) wants to access the faulty scan registers in the network, the repair component (<NUM>) will check the address with the faulty scan registers' location. If the addresses are the same, the access process will be bypassed. According to one embodiment of the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device, the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface.

<FIG> shows examples of bit sequences for test and repair commands. In this example both commands have <NUM> bits. The first byte '<NUM><NUM>' of iTest bit sequence specifies the iTest command and the first byte '<NUM><NUM>' of iRepair bit sequence specifies the iRepair command. When the test controller sends the iTest command to the device under test, the test function will be enabled. The overall idea of the test function is to detect and localize faulty scan registers. It may comprise two processes, the FULLTEST and ONEBY- ONE process. First, the FULLTEST process will be executed to test if there are any faults in the scan registers. If there are faults, the ONEBYONE process will be executed to test the scan registers one by one, which will localize the locations of the faults. <FIG> shows an example of a test block according to the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device, which includes the sequence generator, the shift-update (SU) controller and the sequence detector.

<FIG> shows examples of scan paths and an example of use of the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device. <FIG> shows an example of a flat reconfigurable network with <NUM> SIBs and <NUM> scan registers where the length of the scan registers is <NUM> bit. For illustration, we inject a fault in the second scan register, which is controlled by the second SIB. The test function operates as follows:.

The present disclosure introduces a repair function, which may bypass the faulty scan registers. When the iRepair commands are applied, the repair component will be enabled to save the faulty scan registers location from the repair register of sequence generator. After that, when the test controller wants to access faulty scan registers, the repair component will check the faulty scan register locations and automatically exclude them from the scan path.

The test block in the hardware embodiment of the presently disclosed system for accessing a plurality of instruments embedded in a semiconductor device may comprise a repair component configured to exclude specific faulty scan registers from a scan-path.

The system may employ a FAULTScanRegister_reg in the form of register array of <NUM> bits-std_logic_vector type registers. One example is set out as follows: First, in the IDLE state, reset puts everything in default values. When the repair component starts, the state machine will go to the S0 state. In the S0 state, the component will check the first bit of SCR_test_in signal, which is the signal that transfers the faulty scan registers location from the repair register of sequence generator. As we discussed in the last subsection, the information in the repair register is '<NUM>'. Since the first scan register is not faulty, nothing will be saved in the first register of FAULTScanRegister reg array. After that, in the next rising edge of the clock cycle, the state machine will move to the S1 state. In S1 state, the SCR_counter adds <NUM>, which will make the S0 state check the second bit of the repair register. The FAULTScanRegister_counter will also add <NUM>, which will transform the second scan register location to binary type (<NUM>). If there is a faulty scan register location in the next state, the fault location will be saved at the second vector of the FAULTScanRegister_reg array. Then the state machine goes to S0 state again, since the second bits of repair register is '<NUM>', the faulty scan register location will be saved as "<NUM><NUM>" in the second register of FAULTScanRegister_reg array. The component will stop until every bits of repair register has been checked. As expected, the component will only save the second scan register location into the FAULTScanRegister_reg array.

<FIG> shows a software-implemented embodiment of the presently disclosed system (<NUM>) for accessing a plurality of instruments (<NUM>) embedded in a semiconductor device (<NUM>). In this embodiment the test (<NUM>) and repair (<NUM>) functions are implemented in the test controller (<NUM>). By applying iTest and iRepair commands, the test and repair functions will be enabled. First, the iTest command will be applied to enable the test function. During the test process, the faulty scan registers locations will be detected and saved into a file. After that, the iRepair command will be applied to enable the repair function. During the repair process, when the test controller wants tosend the iWrite or iRead commands which related to the faulty scan registers, the iRepair commands will check the faults location file and the iWrite or iRead commands will be bypassed.

In one example the same reconfigurable network as in <FIG> is used to explain the test process of software solution. <FIG> shows an example of a work flow of the test process. The test function first applies the ALLWrite command to write test data '<NUM>' into all scan registers one by one. <FIG> shows the bit sequence of the ALLWrite process.

Then the ALLRead command is be applied to send the dummy bits '<NUM>' to the scan network so that all the test data can be pushed out from the scan network back to the test controller. In this example, since the second scan register is an inverter which is considered as a fault, the second incoming data should be '<NUM>'. <FIG> shows the bit sequence of the ALLRead process.

The data flow of ALLWrite and ALLWrite process are shown in <FIG>.

After that, the iTest function will look for the same data as incoming data in the original data buffer. If there is same data, the corresponding scan register is not faulty. If not, the corresponding scan register has a fault and the address of the scan register will be stored in the FaultScanRegisters file. In this example the second scan register's location will be saved into this file.

The idea of the repair function is to check what PDL commands use. If PDL commands want to access a faulty scan register, the repair function will exclude this PDL command from the iApply group. Hence, the scan path will be modified such that the defective scan register is excluded. For example, in <FIG>, the commands where the second scan register is bypassed, and the test controller only send the commands which is related to the normal scan registers.

The present disclosure further relates to applying the system and methods for controlling that instruments are only accessed in allowed combinations and detection of access attempts of instruments in non-permitted combinations.

One aspect of the present disclosure relates to a system for controlling access to instruments embedded in a semiconductor device, the system comprising:.

The test block may be further configured to block accesses that are not allowed. The test block may also be configured to limit the number of bits in, for example, a scan chain that may be accessed.

The system for controlling access to instruments embedded in a semiconductor device may be operated according the following example. If, for example, in the system of <FIG>, instrument i1 should only be accessed is when it is the only instrument in the active scan-path. To enable this, an access control register (ACR) may be used, as shown in the example of <FIG>. In this example, the PDL will try to access i1 and i3 by setting the SCR so that instruments i1 and i3 are active at the same time. However, as ACR is specified to <NUM> the logic function will indicate that when instrument i3 is on the active scan-path it must be the only instrument. In this case, the content of the SCR is not accepted by the ACR and the logic function. The result is that access to instruments in this combination can be blocked, a signal can be sent to indicate that an attempt to access instruments in a not allowed combination has been made, and that the involved instruments, the content of SCR, are reported, as the information that instrument i1 was included in the PDL may help in determining if instrument i1 is a Trojan.

Claim 1:
A system (<NUM>) for accessing a plurality of instruments (<NUM>) embedded in a semiconductor device (<NUM>), the system comprising:
- a hardware interface (<NUM>) configured to access a control mechanism for controlling the plurality of instruments (<NUM>);
- a test controller (<NUM>) for testing the semiconductor device (<NUM>) or generating test patterns for the semiconductor device (<NUM>), wherein the test controller (<NUM>) comprises an instrument connectivity language and procedural description language configuration for operating the plurality of instruments (<NUM>), the test controller (<NUM>) being configured to perform the steps of:
o testing at least one functionality of each of the plurality of instruments (<NUM>) by accessing the control mechanism for controlling the plurality of instruments (<NUM>) through the hardware interface (<NUM>), thereby receiving a fault status of each of the plurality of instruments (<NUM>);
characterized in that the test controller (<NUM>) is configured to perform:
o based on the fault status of the plurality of instruments (<NUM>), configuring a test block (<NUM>) in the semiconductor device (<NUM>) such that valid test patterns for the semiconductor device (<NUM>) can be generated without updating the instrument connectivity language and procedural description language configuration,
and in that:
the instruments (<NUM>) are reconfigurable scan networks and the testing is scan testing,
the test block (<NUM>) comprises a repair component (<NUM>) configured to exclude specific faulty scan registers from a scan-path,
an active scan-path is configured such that only instruments (<NUM>) without faulty scan chains are included in the testing, and
the test controller (<NUM>) is configurable to send a test command to the test block (<NUM>) through the hardware interface (<NUM>) and/or wherein the test controller (<NUM>) is configurable to send a repair command to the test block (<NUM>) through the hardware interface (<NUM>).