Patent Description:
Various display devices used in multimedia devices, such as televisions, mobile phones, tablet computers, navigation devices, and game consoles, are being developed. Devices, such as a keyboard, a mouse, etc., are used as an input device for these multimedia devices. In addition, input sensors incorporated into the display devices are used as input devices for the multimedia devices.

For instance, <CIT> discloses a display panel including a sensing electrode unit comprising a plurality of input sensors. Furthermore, <CIT> relates to a touch sensor panel including metal mesh touch electrodes and routing in the active area.

A display device is provided as defined in claim <NUM>.

The above and other aspects of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:.

In the present disclosure, it will be understood that when an element (or area, layer, or portion) is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.

Like numerals may refer to like elements throughout the specification and the drawings. As used herein, the term "and/or" may include any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not necessarily be limited by these terms. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the singular forms, "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another elements or features as shown in the figures.

It will be further understood that the terms "include" and/or "including", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the phrase "conductive" is understood to mean "electrically conductive" and the phrase "insulative" is understood to mean "electrically insulative. " Similarly, the phrase, "connected" is understood to mean "electrically connected" unless the context clearly indicates a structural connection.

Hereinafter, embodiments of the present disclosure will be described with reference to accompanying drawings.

<FIG> is a perspective view of a display device DD according to an embodiment of the present disclosure. As shown in <FIG>, the display device DD may display an image through a display surface DD-IS. The display surface DD-IS may be substantially parallel to a plane defined by a first directional axis DR1 and a second directional axis DR2. A third directional axis DR3 may indicate a normal line direction of the display surface DD-IS, e.g., a thickness direction of the display device DD.

Front (or upper) and rear (or lower) surfaces of each member or each unit described below may be distinguished from each other by the third directional axis DR3. However, directions indicated by the first, second, and third directional axes DR1, DR2, and DR3 are merely examples. First, second, and third directions used hereinafter may be assigned with the same reference numerals as and may indicate the same directions as the first, second, and third directional axes DR1, DR2, and DR3.

In the present embodiment of the present disclosure, the display device DD may include a flat display surface, however, it should not necessarily be limited thereto or thereby. The display device DD may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas facing different directions from each other, for example, a bent display surface. The display device DD, according to the present embodiment, may be a flexible display device DD that can be bent without sustaining damage thereto. The flexible display device DD may be a foldable display device that can be folded without sustaining damage thereto.

In the present embodiment, the display device DD that may be applied to a tablet computer is illustrated as a representative example. Various electronic modules, a camera module, and a power module, which are mounted on a main board, may be placed on a bracket/a case with the display device DD to form the tablet computer. The display device DD, according to the present disclosure, may be applied to a large-sized electronic item, such as a television set and a computer monitor, and a small and medium-sized electronic item, such as a mobile phone, a vehicle navigation unit, a game console, and a smart watch.

As shown in <FIG>, the display surface DD-IS may include an image area DD-DA, through which the image is displayed, and a bezel area DD-NDA, defined adjacent to the image area DD-DA. The image is not displayed through the bezel area DD-NDA. <FIG> shows images of application icons as a representative example of the image.

As shown in <FIG>, the image area DD-DA may have a substantially quadrilateral shape. The expression "substantially quadrilateral shape" may mean not only a quadrilateral shape mathematically defined but also a variation of a quadrilateral shape in which a curved line boundary, instead of a vertex, is defined in a vertex area (or a corner area).

The bezel area DD-NDA may fully surround the image area DD-DA, however, it should not necessarily be limited thereto or thereby. The shape of the bezel area DD-NDA may be changed. For example, the bezel area DD-NDA may be defined only at one side of the image area DD-DA or at some but not all sides thereof.

<FIG> is a cross-sectional view of the display device DD according to an embodiment of the present disclosure.

The display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may be coupled with the window WM by an adhesive layer PSA.

The display module DM may include a display panel <NUM>, an input sensor <NUM>, and an anti-reflective layer <NUM>. The display panel <NUM> may include a base layer <NUM>, a driving element layer <NUM>, a light emitting element layer <NUM>, and an encapsulation layer <NUM>.

The driving element layer <NUM> may be disposed on an upper surface of the base layer <NUM>. The base layer <NUM> may be a flexible substrate that is bendable, foldable, or rollable to an appreciable extent without cracking or otherwise sustaining damage. The base layer <NUM> may be a glass substrate, a metal substrate, or a polymer substrate, however, it should not necessarily be limited thereto or thereby. According to an embodiment, the base layer <NUM> may be an inorganic layer, an organic layer, or a composite material layer. The base layer <NUM> may have substantially the same shape as that of the display panel <NUM>.

The base layer <NUM> may have a multi-layer structure. For example, the base layer <NUM> may include a first synthetic resin layer, a second synthetic resin layer, and inorganic layers disposed between the first synthetic resin layer and the second synthetic resin layer. Each of the first and second synthetic resin layers may include a polyimide-based resin, however, it should not necessarily be particularly limited thereto.

The driving element layer <NUM> may be disposed on the base layer <NUM>. The driving element layer <NUM> may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and signal lines. The driving element layer <NUM> may include a driving circuit for driving a pixel.

The light emitting element layer <NUM> may be disposed on the driving element layer <NUM>. The light emitting element layer <NUM> may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

The encapsulation layer <NUM> may be disposed on the light emitting element layer <NUM>. The encapsulation layer <NUM> may protect the light emitting element layer <NUM>, e.g., the light emitting element, from moisture, oxygen, and a foreign substance such as dust particles. The encapsulation layer <NUM> may include at least one encapsulation inorganic layer. The encapsulation layer <NUM> may include a stack structure in which a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer are sequentially stacked.

The input sensor <NUM> may be disposed directly on the display panel <NUM>. The input sensor <NUM> may sense a user's input (e.g., a touch) by an electromagnetic induction method and/or a capacitive method. The input sensor <NUM> and the display panel <NUM> may be formed through successive processes. The expression "A component A is disposed directly on a component B. ", as used herein, means that no intervening elements are present between the component A and the component B. For example, a separate adhesive layer might not be disposed between the input sensor <NUM> and the display panel <NUM>.

The anti-reflective layer <NUM> may reduce a reflectance with respect to an external light incident thereto from the above of the window WM. The anti-reflective layer <NUM>, according to the present embodiment, may include a retarder and a polarizer. The retarder may be a film type or liquid crystal coating type and may include a λ/<NUM> retarder (e.g., a half-wave plate) and/or a λ/<NUM> retarder (e.g., a quarter-wave plate). The polarizer may be a film type or liquid crystal coating type. The film type retarder and polarizer may include a stretched synthetic resin film, and the liquid crystal coating type retarder and polarizer may include liquid crystals aligned in a predetermined alignment. The retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as a base layer of the anti-reflective layer <NUM>.

The anti-reflective layer <NUM> may include color filters. The color filters may be arranged in a predetermined arrangement. As an example, the color filters may be arranged by taking into account colors of lights emitted from pixels included in the display panel <NUM>. The anti-reflective layer <NUM> may further include a black matrix adjacent to the color filters. The anti-reflective layer <NUM> including the color filters may be disposed directly on the display panel <NUM>.

According to an embodiment, the window WM may include a base layer and a light blocking pattern. The base layer may include a glass substrate and/or a synthetic resin film. The light blocking pattern may partially overlap the base layer. The light blocking pattern may be disposed on a rear surface of the base layer, and the light blocking pattern may substantially define the bezel area DD-NDA (refer to <FIG>) of the display device DD. An area in which the light blocking pattern is not disposed may define the image area DD-DA (refer to <FIG>) of the display device DD.

<FIG> is a plan view of the display panel <NUM> according to an embodiment of the present disclosure.

Referring to <FIG>, the display panel <NUM> may include a plurality of pixels PX, a scan driver SDV, a light emission driver EDV, a plurality of signal lines, and a plurality of pads PD. The pixels PX may be arranged in a display area <NUM>-DA. A driving chip DIC disposed in a non-display area <NUM>-NDA may include a data driver. The display area <NUM>-DA may correspond to the image area DD-DA of <FIG>, and the non-display area <NUM>-NDA may correspond to the bezel area DD-NDA. In the following descriptions, the expression "An area/portion corresponds to another area/portion. " means that "An area/portion overlaps another area/portion. ", but the expression should not necessarily be limited to meaning "An area/portion has the same area and/or the same shape as another area/portion". According to an embodiment, the data driver may be integrated into the display panel <NUM> like the scan driver SDV and the light emission driver EDV.

The signal lines may include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emission lines EL1 to ELm, first and second control lines SL-C1 and SL-C2, and first and second power lines PL1 and PL2. Here, "m" and "n" are integers equal to or greater than <NUM>.

The scan lines SL1 to SLm may extend in the first direction DR1 and may be electrically connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be electrically connected to the pixels PX and the driving chip DIC. The light emission lines EL1 to Elm may extend in the first direction DR1 and may be electrically connected to the pixels PX and the light emission driver EDV.

The first power line PL1 may receive a first power supply voltage, and the second power line PL2 may receive a second power supply voltage having a voltage level that is lower than that of the first power supply voltage. A second electrode of the light emitting element, for example, a cathode, may be connected to the second power line PL2.

The first control line SL-C1 may be connected to the scan driver SDV and may extend toward a lower end of the display panel <NUM>. The second control line SL-C2 may be connected to the light emission driver EDV and may extend toward the lower end of the display panel <NUM>. The pads PD may be disposed in the non-display area <NUM>-NDA adjacent to the lower end of the display panel <NUM> and may be closer to the lower end of the display panel <NUM> than the driving chip DIC is. The pads PD may be connected to the driving chip DIC and some of the signal lines.

The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX via the scan lines SL1 to SLm. The driving chip DIC may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX via the data lines DL1 to DLn. The light emission driver EDV may generate a plurality of light emission signals, and the light emission signals may be applied to the pixels PX via the light emission lines EL1 to ELm. The pixels PX may receive the data voltages in response to the scan signals. The pixels PX may emit light with luminance corresponding to the data voltages in response to the light emission signals to display the image.

<FIG> are enlarged plan views of display areas according to embodiments of the present disclosure.

Referring to <FIG>, the display area <NUM>-DA may include a plurality of light emitting areas LA1, LA2, and LA3 and a non-light-emitting area NLA adjacent to the light emitting areas LA1, LA2, and LA3. The non-light-emitting area NLA may define a boundary between the light emitting areas LA1, LA2, and LA3.

The light emitting areas LA1, LA2, and LA3 may correspond to the pixels PX of <FIG> in a one-to-one correspondence. Each of the pixels PX may include the light emitting element, and the light emitting areas LA1, LA2, and LA3 may be areas from which the light emitted from the light emitting element exits. An arrangement relationship between the light emitting areas LA1, LA2, and LA3 and the non-light-emitting area NLA will be described later with reference to <FIG>.

The light emitting areas LA1, LA2, and LA3 may include a first light emitting area LA1 (or a first color light emitting area) forming a first color light, a second light emitting area LA2 (or a second color light emitting area) forming a second color light, and a third light emitting area LA3 (or a third color light emitting area) forming a third color light. In the present embodiment, the first color light may be a red light, the second color light may be a green light, and the third color light may be a blue light.

The first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may have sizes that are different from each other, however, they should not necessarily be limited thereto or thereby. In the present embodiment, the first light emitting area LA1 may have the smallest size, and the third light emitting area LA3 may have the largest size.

The first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may define one unit light emitting area UA. The unit light emitting area UA is a unit that is repeated for the arrangement of the light emitting areas defined in the display area <NUM>-DA. In the present embodiment, the unit light emitting area UA may include a first unit light emitting area UA1 and a second unit light emitting area UA2.

Referring to the first unit light emitting area UA1 and the second unit light emitting area UA2, the first light emitting area LA1 and the second light emitting area LA2 may be disposed at one side (e.g., a left side in <FIG>) of the third light emitting area LA3 in the first direction DR1. The second light emitting area LA2 of each of the first unit light emitting area UA1 and the second unit light emitting area UA2 may be disposed at one side (e.g., a lower side in <FIG>) of the first light emitting area LA1.

A position of the third light emitting area LA3 of the first unit light emitting area UA1 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2 may be different from a position of the third light emitting area LA3 of the second unit light emitting area UA2 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2. The position of third light emitting area LA3 of the first unit light emitting area UA1 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2 may be located at a lower side. The position of the third light emitting area LA3 of the second unit light emitting area UA2 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2 may be located at an upper side. A degree of shift of the third light emitting area LA3 of the first unit light emitting area UA1 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2 may be different from a degree of shift of the third light emitting area LA3 of the second unit light emitting area UA2 with respect to the first light emitting area LA1 and the second light emitting area LA2 in the second direction DR2. In the present embodiment, the third light emitting area LA3 of the second unit light emitting area UA2 may be shifted further.

The first unit light emitting area UA1 may be alternately arranged with the second unit light emitting area UA2 along the first direction DR1 in a pixel row PXR. The first unit light emitting area UA1 may be alternately arranged with the second unit light emitting area UA2 along the second direction DR2 in a pixel column PXC. Due to the arrangement of the first unit light emitting area UA1 and the second unit light emitting area UA2, the third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2 may be arranged in a specific rule. The third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2 adjacent to the first unit light emitting area UA1 may be spaced apart from each other by a first distance DT1. The third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2, which are spaced apart from each other by the first distance DT1, may define a light emitting area pair LP. The light emitting area pair LP may be spaced apart from another light emitting area pair LP by a second distance DT2 in each pixel column PXC. The second distance DT2 may be greater than the first distance DT1.

The light emitting area pair LP is formed because of the mask used during a deposition process. The light emitting element disposed in the third light emitting area LA3 of the first unit light emitting area UA1 and the light emitting element disposed in the third light emitting area LA3 of the second unit light emitting area UA2 may include a light emitting layer having a single integral form. For example, the light emitting layer disposed in the third light emitting area LA3 of the first unit light emitting area UA1 and the light emitting layer disposed in the third light emitting area LA3 of the second unit light emitting area UA2 may be provided integrally with each other and may be deposited using one mask. The mask may be provided with openings defined therethrough to correspond the light emitting area pairs LP. An area between the openings of the mask may correspond to a blocking area of the mask. As the openings corresponding to the light emitting area pairs LP are defined, the number of the openings may be reduced, and a width of the blocking area of the mask disposed between the openings in the second direction DR2 may be secured. Thin film masks may be used to secure the width of the blocking area thereof in the second direction DR2 to prevent defects of the mask, e.g., sagging, during the deposition process.

This may be understood by comparing a third distance DT3 between third light emitting areas LA3 shown in <FIG>. Referring to <FIG>, unit light emitting areas UA disposed in the display area <NUM>-DA belong to one type. The third distance DT3 between the third light emitting areas LA3 of the unit light emitting areas UA adjacent to each other in a pixel column PXC may be smaller than the second distance DT2 of <FIG>. The number of openings defined through a mask used to form the third light emitting areas LA3 of <FIG> is greater than that of the mask used to form the third light emitting areas LA3 of <FIG>, and a width of a blocking area of the mask is reduced.

Referring to <FIG>, unit light emitting areas UA0 disposed in the display area <NUM>-DA belong to one type. The unit light emitting area UA0 may include second light emitting areas LA2 disposed spaced apart from each other in the first direction DR1 and a first light emitting area LA1 and a third light emitting area LA3 disposed spaced apart from each other in the second direction DR2. Four light emitting areas LA1, LA2, and LA3 of the unit light emitting area UA0 may be arranged in a lozenge (e.g., diamond) shape. The unit light emitting areas UA0 of pixel rows PXR may be arranged in the first direction DR1. The unit light emitting areas UA0 of the pixel rows PXR adjacent to each other may be arranged staggered with each other along the first direction DR1. The unit light emitting areas UA0 of pixel columns PXC adjacent to each other may be arranged staggered with each other along the second direction DR2.

<FIG> is a cross-sectional view of the display device DD taken along a line I-I' of <FIG>. In <FIG>, some components of the display device DD, for example, the anti-reflective layer <NUM> to the window WM of <FIG>, are not shown.

A pixel driving circuit PC that drives the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit PC may include a plurality of transistors S-TFT and O-TFT and a capacitor Cst. <FIG> shows a silicon transistor S-TFT and an oxide transistor O-TFT as a representative example of the transistor. The pixel driving circuit PC of <FIG> is an example, and components of the pixel driving circuit PC should not necessarily be limited thereto or thereby. The pixel driving circuit PC may include only one type of transistor of the silicon transistor S-TFT and the oxide transistor O-TFT.

Referring to <FIG>, the base layer <NUM> has a single-layer structure. The base layer <NUM> may include a synthetic resin such as polyimide. The base layer <NUM> may be formed by coating a synthetic resin layer on a work substrate (or a carrier substrate). When the display module DM is completed through subsequent processes, the work substrate may be removed.

Referring to <FIG>, a barrier layer 10br may be disposed on the base layer <NUM>. The barrier layer 10br may prevent a foreign substance from entering thereinto from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the silicon oxide layers and the silicon nitride layers may be alternately stacked with each other.

The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. A first shielding electrode BMLa may be disposed between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLa may correspond to the silicon transistor S-TFT. The first shielding electrode BMLa may include a metal material, e.g., molybdenum.

The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive the first power supply voltage. The first shielding electrode BMLa may prevent an electric potential caused by a polarization phenomenon from exerting influence on the silicon transistor S-TFT. The first shielding electrode BMLa may prevent an external light from reaching the silicon transistor S-TFT. According to an embodiment, the first shielding electrode BMLa may be a floating electrode isolated from other electrodes or lines.

A buffer layer 10bf may be disposed on the barrier layer 10br. The buffer layer 10bf may prevent metal atoms or impurities from being diffused to a first semiconductor pattern SC1 disposed thereon from the base layer <NUM>. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

The first semiconductor pattern SC1 may be disposed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. As an example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon.

The first semiconductor pattern SC1 may have different electrical properties depending on whether or not it is doped or whether it is doped with an N-type dopant or a P-type dopant. The first semiconductor pattern SC1 may include a first region having a relatively high conductivity and a second region having a relatively low conductivity. The first region may be doped with the N-type dopant or the P-type dopant. The second region may be a non-doped region or a region doped at a concentration lower than that of the first region. A source area SE1, a channel area AC1 (or an active area), and a drain area DE1 of the silicon transistor S-TFT may be formed from the first semiconductor pattern SC1. The source area SE1 and the drain area DE1 may extend in opposite directions to each other from the channel area AC1 in a cross-section.

A first insulating layer <NUM> of the driving element layer may be disposed on the buffer layer 10bf. The first insulating layer <NUM> of the driving element layer may cover the first semiconductor pattern SC1. The first insulating layer <NUM> of the driving element layer may be an inorganic layer. The first insulating layer <NUM> of the driving element layer may have a single-layer structure of a silicon oxide layer, however, it should not necessarily be limited thereto or thereby. Not only the first insulating layer <NUM> of the driving element layer, but also the further insulating layers of the driving element layer <NUM> described later may have a single-layer or multi-layer structure and may include at least one of a silicon oxide, a silicon nitride or a silicon oxy nitride, however, it should not necessarily be limited thereto or thereby.

A gate GT1 of the silicon transistor S-TFT may be disposed on the first insulating layer <NUM> of the driving element layer. The gate GT1 may be a portion of a metal pattern. The gate GT1 may overlap the channel area AC1. The gate GT1 may be used as a mask in a process of doping the first semiconductor pattern SC1. A first electrode CE10 of the capacitor Cst may be disposed on the first insulating layer <NUM> of the driving element layer. Different from the display device DD shown in <FIG>, the gate GT1 and the first electrode CE10 may be provided integrally with each other.

A second insulating layer <NUM> of the driving element layer may be disposed on the first insulating layer <NUM> of the driving element layer and may cover the gate GT1. An upper electrode may be further disposed on the second insulating layer <NUM> of the driving element layer and may overlap the gate GT1. A second electrode CE20 may be disposed on the second insulating layer <NUM> of the driving element layer and may overlap the first electrode CE10. The upper electrode may be provided integrally with the second electrode CE20, in a plan view.

A second shielding electrode BMLb may be disposed on the second insulating layer <NUM> of the driving element layer. The second shielding electrode BMLb may correspond to the oxide transistor O-TFT. According to an embodiment, the second shielding electrode BMLb may be omitted. According to an embodiment, the first shielding electrode BMLa may extend to a lower portion of the oxide transistor O-TFT and may replace the second shielding electrode BMLb.

A third insulating layer <NUM> of the driving element layer may be disposed on the second insulating layer <NUM> of the driving element layer. A second semiconductor pattern SC2 may be disposed on the third insulating layer <NUM> of the driving element layer. The second semiconductor pattern SC2 may include a channel area AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx), or indium oxide (In<NUM>O<NUM>).

The metal oxide semiconductor may include a plurality of areas SE2, AC2, and DE2 distinguished from each other depending on whether or not a transparent conductive oxide is reduced. The area (hereinafter, referred to as a reduced area) in which the transparent conductive oxide is reduced has a conductivity that is greater than that of the area (hereinafter, referred to as a non-reduced area) in which the transparent conductive oxide is not reduced. The reduced area may substantially act as the source/drain of the transistor or the signal line. The non-reduced area may substantially correspond to the semiconductor area (or the channel) of the transistor. A fourth insulating layer <NUM> of the driving element layer may be disposed on the third insulating layer <NUM> of the driving element layer. As shown in <FIG>, the fourth insulating layer <NUM> of the driving element layer may cover the second semiconductor pattern SC2. According to an embodiment, the fourth insulating layer <NUM> of the driving element layer may be an insulating pattern that overlaps a gate GT2 of the oxide transistor O-TFT and exposes a source area SE2 and a drain area DE2.

The gate GT2 of the oxide transistor O-TFT may be disposed on the fourth insulating layer <NUM> of the driving element layer. The gate GT2 of the oxide transistor O-TFT may be a portion of a metal pattern. The gate GT2 of the oxide transistor O-TFT may overlap the channel area AC2. A fifth insulating layer <NUM> of the driving element layer may be disposed on the fourth insulating layer <NUM> of the driving element layer and may cover the gate GT2. Each of the first to fifth insulating layers <NUM> to <NUM> of the driving element layer may be an inorganic layer.

A first connection pattern CNP1 and a second connection pattern CNP2 may be disposed on the fifth insulating layer <NUM> of the driving element layer. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed through a same process, and thus, the first connection pattern CNP1 and the second connection pattern CNP2 may include a same material and a same stack structure. The first connection pattern CNP1 may be connected to the drain area DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 defined through the first, second, third, fourth, and fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> of the driving element layer. The second connection pattern CNP2 may be connected to the source area SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 defined through the fourth and fifth insulating layers <NUM> and <NUM> of the driving element layer. The connection relationship of the first connection pattern CNP1 and the second connection pattern CNP2 with respect to the silicon transistor S-TFT and the oxide transistor O-TFT should not necessarily be limited thereto or thereby.

A sixth insulating layer <NUM> of the driving element layer may be disposed on the fifth insulating layer <NUM> of the driving element layer. A third connection pattern CNP3 may be disposed on the sixth insulating layer <NUM> of the driving element layer. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 via a third pixel contact hole PCH3 defined through the sixth insulating layer <NUM> of the driving element layer. A data line DL may be disposed on the sixth insulating layer <NUM> of the driving element layer. A seventh insulating layer <NUM> of the driving element layer may be disposed on the sixth insulating layer <NUM> of the driving element layer and may cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed through the same process, and thus, the third connection pattern CNP3 and the data line DL may include the same material and the same stack structure. Each of the sixth insulating layer <NUM> of the driving element layer and the seventh insulating layer <NUM> of the driving element layer may be an organic layer.

The light emitting element LD may include an anode AE (or a first electrode), a light emitting layer EL, and a cathode CE (or a second electrode). The anode AE of the light emitting element LD may be disposed on the seventh insulating layer <NUM> of the driving element layer. The anode AE may be a (semi-)transmissive electrode or a reflective electrode. The anode AE may have a stack structure of ITO/Ag/ITO. Positions of the anode AE and the cathode CE may be interchanged.

A pixel definition layer PDL may be disposed on the seventh insulating layer <NUM>. The pixel definition layer PDL may be an organic layer. The pixel definition layer PDL may have a light absorbing property and may have a black color. As an example, the pixel definition layer PDL may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include a metal material, such as carbon black, chromium, or an oxide thereof. The pixel definition layer PDL may correspond to a light blocking pattern having a light blocking property.

The pixel definition layer PDL may cover a portion of the anode AE. As an example, an opening PDL-OP may be defined through the pixel definition layer PDL to expose a portion of the anode AE. The light emitting area LA1 may be defined to correspond to the opening PDL-OP. <FIG> shows one light emitting area LA1 corresponding to the first light emitting area LA1 of <FIG>. A cross-section corresponding to the second light emitting area LA2 and the third light emitting area LA3 of <FIG> may be substantially the same as that of <FIG>. However, the light emitting layer EL of each of the second light emitting area LA2 and the third light emitting layer LA3 may include a material that is different from a light emitting material included in the light emitting layer EL of the first light emitting layer LA1. In addition, referring to the light emitting area pair LP of <FIG>, the pixel definition layer PDL may be disposed between the third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2. The light emitting layer EL disposed in the third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2 may be disposed on the pixel definition layer PDL disposed between the third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2.

In the present disclosure, a hole control layer may be disposed between the anode AE and the light emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

The encapsulation layer <NUM> may cover the light emitting element LD. The encapsulation layer <NUM> may include an encapsulation inorganic layer <NUM>, an encapsulation organic layer <NUM>, and an encapsulation inorganic layer <NUM>, which are sequentially stacked, however, layers forming the encapsulation layer <NUM> should not necessarily be limited thereto or thereby. The encapsulation inorganic layers <NUM> and <NUM> may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of the encapsulation inorganic layers <NUM> and <NUM> may have a multi-layer structure. The encapsulation organic layer <NUM> may include an acrylic-based organic layer, however, it should not necessarily be particularly limited thereto.

The input sensor <NUM> may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulation layer). In the present embodiment, the input sensor <NUM> may include a first insulating layer <NUM> (or a first sensor insulation layer), a first conductive layer <NUM> (or a first sensor conductive layer), a second insulating layer <NUM> (or a second sensor insulation layer), a second conductive layer <NUM> (or a second sensor conductive layer), and a third insulating layer <NUM> (or a third sensor insulation layer). <FIG> schematically shows a conductive line of the first conductive layer <NUM> and a conductive line of the second conductive layer <NUM>.

The first insulating layer <NUM> may be disposed directly on the display panel <NUM>. The first insulating layer <NUM> may be an inorganic layer including a silicon nitride, a silicon oxynitride, and/or a silicon oxide. Each of the first conductive layer <NUM> and the second conductive layer <NUM> may have a single-layer structure or a multi-layer structure of layers stacked in the third direction DR3. The first conductive layer <NUM> and the second conductive layer <NUM> may include conductive lines that define a mesh shape. The conductive line of the first conductive layer <NUM> and the conductive line of the second conductive layer <NUM> may be connected to each other via a contact hole defined through the second insulating layer <NUM> or might not be connected to each other depending on their positions.

The first conductive layer <NUM> and the second conductive layer <NUM>, which have the single-layer structure, may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (ITZO), or the like. In addition, the transparent conductive layer may include conductive polymer such as PEDOT, metal nanowire, graphene, or the like.

The first conductive layer <NUM> and the second conductive layer <NUM>, which have the multi-layer structure, may include metal layers. The metal layers may have a three-layer structure of titanium/aluminum/titanium. The first conductive layer <NUM> and the second conductive layer <NUM>, which have the multi-layer structure, may include at least one metal layer and at least one transparent conductive layer. The second insulating layer <NUM> may be disposed between the first conductive layer <NUM> and the second conductive layer <NUM>. The third insulating layer <NUM> may cover the second conductive layer <NUM>. According to an embodiment, the third insulating layer <NUM> may be omitted. The second insulating layer <NUM> and the third insulating layer <NUM> may include an inorganic layer or an organic layer.

<FIG> is a plan view of the input sensor <NUM> according to an embodiment of the present disclosure, and <FIG> is an equivalent circuit diagram of the input sensor <NUM> according to an embodiment of the present disclosure.

The input sensor <NUM> may include a sensing area <NUM>-SA and a non-sensing area <NUM>-NSA. The sensing area <NUM>-SA may correspond to the display area <NUM>-DA of <FIG>, and the non-sensing area <NUM>-NSA may correspond to the non-display area <NUM>-NDA of <FIG>. According to an embodiment, the sensing area <NUM>-SA and the display area <NUM>-DA may have a same size, and the non-sensing area <NUM>-NSA and the non-display area <NUM>-NDA may have a same size.

The input sensor <NUM> may include a first input sensor <NUM> and a second input sensor <NUM>. The first input sensor <NUM> and the second input sensor <NUM> may be respectively disposed in a first sensing area <NUM>-SA1 and a second sensing area <NUM>-SA2 of the sensing area <NUM>-SA. The first sensing area <NUM>-SA1 may overlap a first area of the display area <NUM>-DA, and the second sensing area <NUM>-SA2 may overlap a second area of the display area <NUM>-DA. Dividing the sensing area into multiple areas and place input sensors in each sensing area reduces the load of the input sensors.

The first input sensor <NUM> and the second input sensor <NUM> may have substantially the same structure as each other. In the present embodiment, the first input sensor <NUM> and the second input sensor <NUM> are arranged symmetrically at left and right sides as a representative example, however, they should not necessarily be limited thereto or thereby. Hereinafter, descriptions of the input sensor <NUM> will be mainly focused on the first input sensor <NUM>.

The first input sensor <NUM> may include a first sensing electrode E1 (hereinafter, referred to as a first electrode) and a second sensing electrode E2 (hereinafter, referred to as a second electrode) crossing the first sensing electrode E1. As the plural input sensors <NUM> and <NUM> are disposed in the sensing area <NUM>-SA, a length of at least one of the first electrode E1 and the second electrode E2 may be reduced. This may cause a reduction in resistance of electrodes and a reduction in load of the input sensor <NUM>. For example, when one first sensing electrode E1 extending in the first direction DR1 is commonly disposed in the first sensing area <NUM>-SA1 and the second sensing area <NUM>-SA2, the resistance of the first sensing electrode E1 may significantly increase. The first input sensor <NUM> and the second input sensor <NUM> may be driven synchronously with each other or driven independently of each other.

The first electrode E1 may be provided in plural, and the second electrode E2 may be provided in plural. The first electrodes E1 may extend substantially in the first direction DR1 and may be arranged in the second direction DR2. The expression "The first electrodes E1 are substantially extended in the first direction DR1" not only means that the first electrodes extend in a straight line in the first direction DR1 but also means that one ends and the other ends of the first electrodes are disposed spaced apart from each other in the first direction DR1. The second electrodes E2 may extend substantially in the second direction DR2 and may be arranged in the first direction DR1.

A sensing unit SU may be defined for each intersection area where the first electrodes E1 intersect the second electrodes E2. The first sensing area <NUM>-SA1 of <FIG> may include a plurality of sensing units SU arranged in a matrix form, however, the sensing units SU might not necessarily be the same as one another. Some of the sensing units SU may have a relatively small size. For example, the sensing units SU placed at corners of the sensing area <NUM>-SA may have a relatively small size. This is because the display area <NUM>-DA and the sensing area <NUM>-SA may have rounded corners. In addition, an opening through which a light passes may be formed in a specific sensing area <NUM>-SA.

The first input sensor <NUM> may include a first trace line TL1 electrically connected to the first electrode E1, a second trace line TL2 electrically connected to the first electrode E1, and a third trace line TL3 electrically connected to the second electrode E2. One end of the first trace line TL1 may be connected to the first electrode E1 at a first point P1, one end of the second trace line TL2 may be connected to the first electrode E1 at a second point P2, and one end of the third trace line TL3 may be connected to the second electrode E2 at a third point P3. The other end of the first trace line TL1 may be connected to a first pad PD1, the other end of the second trace line TL2 may be connected to a second pad PD2, and the other end of the third trace line TL3 may be connected to a third pad PD3. Each of the first pad PD1 to the third pad PD3 may be a conductive pattern disposed on a layer different from a layer on which at least a portion of the trace line is disposed.

The first trace line TL1 and the second trace line TL2 may be connected to different points of the first electrode E1, and each of the first trace line TL1 and the second trace line TL2 may be provided in plural to correspond to the first electrodes E1. The third trace line TL3 may be provided in plural to correspond to the second electrodes E2. Hereinafter, a structure in which two trace lines are connected to one electrode such as the first electrode E1 may be referred to as a double-routing structure. A structure in which one trace line is connected to one electrode such as the second electrode E2 may be referred to as a single-routing structure.

One electrode of the first electrode E1 and the second electrode E2 may receive a driving signal. Current may flow from one electrode of the first electrode E1 and the second electrode E2 to the other electrode of the first electrode E1 and the second electrode E2 via a mutual capacitor defined between the first electrode E1 and the second electrode E2. Only one of the first electrode E1 and the second electrode E2 may receive the driving signal, however it should not necessarily be limited thereto or thereby. According to an embodiment, the first electrode E1 may receive the driving signal in a first period, and the second electrode E2 may receive the driving signal in a second period. In the present embodiment, the first electrode E1 will be described as receiving the driving signal, however, the second electrode E2 may receive the driving signal.

<FIG> shows an intersection area LCA of the trace lines TL1, TL2, and TL3. The intersection area LCA of the second trace line TL2 and the third trace line TL3 is shown as a representative example. In the intersection area LCA, one of the second trace line TL2 and the third trace line TL3 may include a bridge pattern. The bridge pattern may be disposed on a layer different from a layer on which the second trace line TL2 and the third trace line TL3 are disposed and may prevent the second trace line TL2 and the third trace line TL3 from being short-circuited.

<FIG> shows an equivalent circuit of the first input sensor <NUM> between a driving circuit DCC and a sensing circuit SCC. The equivalent circuit will be described based on a current path formed between the first electrode E1 disposed at the uppermost side of the first input sensor <NUM> shown in <FIG> and the second electrode E2 disposed at the rightmost side of the first input sensor <NUM> shown in <FIG>.

The driving signal Sdr may be applied to the first electrode E1 via the first trace line TL1 and the second trace line TL2. A sensing signal Sse corresponding to the driving signal Sdr may be input to the sensing circuit SCC via the third trace line TL3. An integrated circuit mounted on a circuit board electrically connected to the first pad PD1 to the third pad PD3 may include the driving circuit DCC and the sensing circuit SCC.

The sensing circuit SCC may include a sensing channel <NUM>, an analog-to-digital converter <NUM> (hereinafter, referred to as an ADC), and a processor <NUM>. The sensing channel <NUM> may be provided in each of the second electrodes E2 (refer to <FIG>). The sensing channels <NUM> may be connected to the same ADC <NUM>.

In the present embodiment, the sensing channel <NUM> may include an amplifier AMP1 such as an operational (OP) amplifier. A first input terminal IN1 of the amplifier AMP1, e.g., an inverting input terminal of the OP amplifier, may receive the sensing signal Sse. In addition, a second input terminal IN2 of the amplifier AMP1, e.g., a non-inverting input terminal of the OP amplifier, may act as a reference electric potential terminal and may receive a reference voltage such as a ground (GND) voltage. A capacitor CC and a reset switch SW may be connected between the first input terminal IN1 and an output terminal OUT1 of the amplifier AMP1 in parallel to each other.

The ADC <NUM> may convert an analog signal from the sensing channel <NUM> to a digital signal. The processor <NUM> may process the converted signal (the digital signal) from the ADC <NUM> and may sense a touch input according to the signal process result. As an example, the processor <NUM> may comprehensively analyze the signal (the amplified and converted sensing signal Sse) input thereto from the second electrodes E2 (refer to <FIG>) via the sensing channel <NUM> and the ADC <NUM> and may sense the input. The processor <NUM> may be implemented by a microprocessor (MPU). In this case, the sensing circuit SCC may further include a memory required to drive the processor <NUM>. According to an embodiment, the processor <NUM> may be implemented by a microcontroller.

A first resistor R-T1 and a second resistor R-E1 may be connected in series between the first pad PD1 and a mutual capacitor Cse. The first resistor R-T1 may be an equivalent resistor of the first trace line TL1, and the second resistor R-E1 may be an equivalent resistor of the first electrode E1. A first parasitic capacitor C-T1 and a second parasitic capacitor C-E1 may be connected between the first pad PD1 and the mutual capacitor Cse. The first parasitic capacitor C-T1 may be defined between the first trace line TL1 and the cathode CE (refer to <FIG>), and the second parasitic capacitor C-E1 may be defined between the first electrode E1 and the cathode CE.

A third resistor R-T2 may be formed between the second pad PD2 and the mutual capacitor Cse and may be connected to the first resistor R-T1 in parallel. A third parasitic capacitor C-T2 may be formed between the second pad PD2 and the mutual capacitor Cse and may be connected to the first parasitic capacitor C-T1 in parallel. The third resistor R-T2 may be an equivalent resistor of the second trace line TL2, and the third parasitic capacitor C-T2 may be defined between the second trace line TL2 and the cathode CE.

In addition, a fourth resistor R-E2 and a fifth resistor R-T3 may be connected in series between the third pad PD3 and the mutual capacitor Cse. The fourth resistor R-E2 may be an equivalent resistor of the second electrode E2, and the fifth resistor R-T3 may be an equivalent resistor of the third trace line TL3. A fourth parasitic capacitor C-E2 and a fifth parasitic capacitor C-T3 may be connected between the third pad PD3 and the mutual capacitor Cse. The fourth parasitic capacitor C-E2 may be defined between the second electrode E2 and the cathode CE, and the fifth parasitic capacitor C-T3 may be defined between the third trace line TL3 and the cathode CE.

The driving signal Sdr may be an alternating current signal, e.g., a sine wave signal. As the double-routing structure is applied to the first electrode E1, a combined resistance of the equivalent circuit shown in <FIG> may be lowered. Accordingly, bandwidth characteristics of the input sensor <NUM> may be improved, and a bandwidth of the alternating current signal may be widened.

Referring to <FIG> again, at least one of the first trace line TL1 and the second trace line TL2 may overlap the first sensing area <NUM>-SA1. In the present embodiment, the second trace line TL2 may overlap the first sensing area <NUM>-SA1. The first trace line TL1 connected to an end of the first electrode E1 might not overlap the first sensing area <NUM>-SA1. Even though the first trace line TL1 is not connected to the end of the first electrode E1, the first point P1 where the first electrode E1 is connected to the first trace line TL1 may be disposed closer to the non-sensing area <NUM>-NSA than the second point P2 where the first electrode E1 is connected to the second trace line TL2 is. The first point P1 might not overlap the sensing area <NUM>-SA, and even though the first point P1 overlaps the sensing area <NUM>-SA, the first point P1 may be disposed relatively close to the non-sensing area <NUM>-NSA. However, the second point P2 might only overlap the sensing area <NUM>-SA, and thus, there is a limitation in arranging the second point P2 closer to the non-sensing area <NUM>-NSA. For the same reason, the second electrode E2 and the third point P3 may also be disposed closer to the non-sensing area <NUM>-NSA than second point P2 is.

The second trace line TL2 may overlap the first electrode E1 and might not overlap the second electrode E2 in the sensing area <NUM>-SA. Referring to the second trace line TL2 disposed at the rightmost position of the first input sensor <NUM>, the second trace line TL2 may extend in the same direction, e.g., the second direction DR2, as the direction in which the second electrodes E2 extend in the first sensing area <NUM>-SA1. The second trace line TL2 may extend in the second direction DR2 via the area in which the first electrodes E1 are disposed, and this will be described later.

<FIG> and <FIG> are enlarged plan views of the sensing area <NUM>-SA according to an embodiment of the present disclosure, and <FIG> is a cross-sectional view of the input sensor <NUM> taken along a line II-II' of <FIG>.

<FIG> and <FIG> respectively show a first sensing unit SU1 where one first electrode E1 intersects one second electrode E2 and a second sensing unit SU2 where another first electrode E1 intersects the one second electrode E2 among the sensing units SU of <FIG>. The first sensing unit SU1 and the second sensing unit SU2 may have substantially the same structure as one another except the second trace line TL2 is connected to one first electrode E1 in the first sensing unit SU1. When the second sensing unit SU2 overlaps the second trace line TL2, the other first electrode E1 disposed in the second sensing unit SU2 may be connected to a corresponding second trace line TL2 via another sensing unit SU as shown in <FIG>.

Referring to <FIG> and <FIG>, the second electrode E2 includes a plurality of divided electrodes E2D1, E2D2, and E2D3 extending substantially in the second direction DR2 and arranged spaced apart from each other in the first direction DR1 in the sensing area <NUM>-SA. Three divided electrodes E2D1, E2D2, and E2D3 are shown in <FIG> and <FIG> as a representative example. Hereinafter, the three divided electrodes E2D1, E2D2, and E2D3 may be referred to as a first divided electrode E2D1, a second divided electrode E2D2, and a third divided electrode E2D3, respectively, to differentiate and explain the three divided electrodes E2D1, E2D2, and E2D3.

Each of the divided electrodes E2D1, E2D2, and E2D3 may include two types of portions with different shapes. A portion with a relatively large size may be referred to as a sensing portion E2P1, and a portion with a relatively small size may be referred to as an intermediate portion E2P2. The sensing portions E2P1 and the intermediate portions E2P2 may be alternately arranged with each other in the second direction DR2. The sensing portions E2P1 may be provided integrally with the intermediate portions E2P2. The divided electrodes E2D1, E2D2, and E2D3 may be formed from the second conductive layer <NUM> described with reference to <FIG>.

The first electrode E1 may include sensing patterns E1D1 and bridge patterns E1D2 disposed on a layer different from a layer on which the sensing patterns E1D1 are disposed. For instance, the sensing patterns E1D1 may be disposed on the second insulating layer <NUM> and the bridge patterns E1D2 may be disposed on the first insulating layer <NUM>, i.e. the bridge patterns E1D2 is disposed under the second insulating layer <NUM> and connecting neighboring pairs of sensing patterns. The sensing patterns E1D1 may be spaced apart from each other in the first direction DR1 and may be disposed between the divided electrodes E2D1, E2D2, and E2D3. Each of the sensing patterns E1D1 may include two types of portions with different shapes. A portion with a relatively large size may be referred to as a sensing portion E1P1, and a portion with a relatively small size may be referred to as an intermediate portion E1P2. The sensing patterns E1D1 including three sensing portions E1P1 and two intermediate portions E1P2 are shown as an example. The sensing portions E1P1 and the intermediate portions E1P2 may be alternately arranged with each other in the second direction DR2. The sensing portions E1P1 may be provided integrally with the intermediate portions E1P2. The sensing portion E1P1 of the sensing patterns E1D1 may be disposed between the intermediate portions E2P2 of the divided electrodes E2D1, E2D2, and E2D3.

<FIG> shows only a portion of the first electrode E1 corresponding to the first sensing unit SU1, however, referring to <FIG> and <FIG>, the first electrode E1 may include the sensing patterns E1D1 corresponding to the sensing units SU arranged in the first direction DR1.

Referring to <FIG>, <FIG>, and <FIG>, the sensing patterns E1D1 of the first sensing unit SU1 and the sensing patterns E1D1 of the second sensing unit SU2 may be spaced apart from each other in the second direction DR2. Six bridge patterns E1D2 that connect two sensing patterns E1D1 disposed adjacent to each other in the first direction DR1 are shown as a representative example. The shape and number of the bridge patterns E1D2 should not necessarily be particularly limited thereto.

Referring to <FIG> and <FIG>, the second trace lines TL2 may be disposed between the first divided electrode E2D1 and the second divided electrode E2D2 and between the second divided electrode E2D2 and the third divided electrode E2D3. The second trace line TL2 may overlap at least one of the sensing patterns E1D1 and might not overlap the second electrode E2, in the plan view. Accordingly, a signal interference between the second electrode E2 and the second trace line TL2 or an influence (e.g. parasitic capacitance) of the parasitic capacitor may be minimized. <FIG> and <FIG> show the structure in which one sensing unit SU1 or SU2 overlaps two second trace lines TL2, however, the structure should not necessarily be limited thereto or thereby. One second trace line TL2 overlapping one sensing pattern among the sensing patterns E1D1 may correspond to the sensing unit SU1 or SU2.

Referring to <FIG>, the second trace line TL2 may be connected to a corresponding first electrode E1 among the first electrodes E1. The second trace line TL2 may be connected to the corresponding first electrode E1 via a contact hole TH-I defined through the second insulating layer <NUM>. The third insulating layer <NUM> may cover the first electrode E1. The sensing pattern E1D1 and the bridge pattern E1D2 of <FIG> and <FIG> may also be connected to each other via the contact hole TH-I. Referring to <FIG>, a dummy electrode DME and the second trace line TL2 may be disposed on the same layer, and the dummy electrode DME will be described later with reference to <FIG>.

<FIG> is an enlarged plan view of the second conductive layer <NUM> corresponding to a first area A1 of <FIG>. <FIG> is an enlarged plan view of the first conductive layer <NUM> corresponding to the first area A1 of <FIG>. <FIG> is an enlarged plan view of the second conductive layer <NUM> corresponding to a second area B1 of <FIG>. <FIG> is an enlarged plan view of the first conductive layer <NUM> corresponding to the second area B1 of <FIG>. <FIG> is an enlarged plan view of the second conductive layer <NUM> corresponding to a third area C1 of <FIG>. <FIG> is an enlarged plan view of the first conductive layer <NUM> corresponding to the third area C1 of <FIG>.

In <FIG>, the second conductive layer <NUM> corresponds to the second conductive layer <NUM> of <FIG>, and the first conductive layer <NUM> corresponds to the first conductive layer <NUM> of <FIG>. <FIG> is an enlarged view of the sensing portion E2P1 formed from the second conductive layer <NUM>. The sensing portion E2P1 is shown to represent the second electrode E2. In <FIG>, the display area <NUM>-DA shown in <FIG> is shown.

Referring to <FIG> and <FIG>, a plurality of openings EOP1, EOP2, and EOP3 may be defined through the sensing portion E2P1 of the second electrode E2. The openings EOP1, EOP2, and EOP3 may include a first opening EOP1 corresponding to the first light emitting area LA1, a second opening EOP2 corresponding to the second light emitting area LA2, and a third opening EOP3 corresponding to the light emitting area pair LP. The first light emitting area LA1 may be disposed inside the first opening EOP1, the second light emitting area LA2 may be disposed inside the second opening EOP2, and the light emitting area pair LP may be disposed inside the third opening EOP3. The third light emitting area LA3 of the first unit light emitting area UA1 and the third light emitting area LA3 of the second unit light emitting area UA2 shown in <FIG> may be commonly disposed inside the third opening EOP3.

The sensing portion E2P1 may include a plurality of line components L1 and L2 that defines the openings EOP1, EOP2, and EOP3. The line components L1 and L2 may include first line components L1 extending in the first direction DR1 and second line components L2 extending in the second direction DR2. Each of the first line components L1 may extend from one second line component L2 to another second line component L2 adjacent to the one second line component L2. The first line components L1 may be disposed between two openings EOP1, EOP2, and EOP3 adjacent to each other in the second direction DR2 among the openings EOP1, EOP2, and EOP3, and the first line components L1 may include plural groups of the line components, which are distinguished from each other depending on their widths in the second direction DR2.

Referring to <FIG>, a plurality of dummy electrodes DME may be disposed in an area overlapping the sensing portion E2P1 shown in <FIG>. The dummy electrodes DME may be arranged in an arrangement obtained by cutting (or dividing) the sensing portion E2P1 shown in <FIG> in a predetermined rule. Since the dummy electrodes DME completely overlap the sensing portion E2P1, a step difference due to the first conductive layer <NUM> (refer to <FIG>) may be prevented from occurring.

Four dummy electrodes DME may be arranged around a first area EOP1-A. The first area EOP1-A may correspond to the first opening EOP1. Two cutting areas (or divided areas) facing each other in the second direction DR2 may be arranged around the first area EOP1-A, and two cutting areas facing each other in the first direction DR1 may be arranged around the first area EOP1-A. Four dummy electrodes DME may be arranged around the second area EOP2-A corresponding to the second opening EOP2. Two cutting areas facing each other in the second direction DR2 may be arranged around the second area EOP2-A, and two cutting areas facing each other in the first direction DR1 may be arranged around the second area EOP2-A. Two pairs of cutting areas facing each other in the second direction DR2 may be arranged around the third area EOP3-A, and two cutting areas facing each other in the first direction DR1 may be arranged around the third area EOP3-A.

Referring to <FIG> and <FIG>, the sensing portion E2P1 may have a width that is greater than that of the dummy electrode DME. The first line component L1 of the sensing portion E2P1 may have a width W1 that is greater than a width W10 of a cut first line component L10 of the dummy electrode DME, and the second line component L2 of the sensing portion E2P1 may have a width W2 that is greater than a width W20 of a cut second line component L20 of the dummy electrode DME. Accordingly, the sensing portion E2P1 may cover the dummy electrode DME. Referring to <FIG> and <FIG>, the widths of the first line component L1 of the sensing portion E2P1 and the first line component L10 of the dummy electrode DME, which overlap each other, may be compared with each other. Referring to <FIG>, the width of the sensing portion E1P1 of the first electrode E1 and the width of the dummy electrode DME may be compared with each other.

Referring to <FIG> and <FIG>, the sensing portion E1P1 of the first electrode E1 may be substantially the same as the sensing portion E2P1 of the second electrode E2 of <FIG> and <FIG>. Referring to <FIG>, the second trace line TL2 and the dummy electrodes DME may be disposed in the area overlapping the sensing portion E1P1 of <FIG>. The second trace line TL2 may include second line components L200 extending in the second direction DR2 and first line components L100 disposed between the second line components L20. A first opening EOP10 corresponding to the first opening EOP1 of <FIG> and a second opening EOP20 corresponding to the second opening EOP2 of <FIG> may be defined through the second trace line TL2. The dummy electrodes DME may be disposed in an area except the area in which the second trace line TL2 is disposed. When compared with <FIG>, some of the dummy electrodes DME may be connected to each other to define the second trace line TL2.

Referring to <FIG> and <FIG>, a boundary line BL between the sensing portion E1P1 of the first electrode E1 and the sensing portion E2P1 of the second electrode E2 is shown. As the conductive pattern of the second conductive layer <NUM> shown in <FIG> is cut in a predetermined rule, a boundary area between the sensing portion E1P1 of the first electrode E1 and the sensing portion E2P1 of the second electrode E2 may be defined.

Referring to <FIG>, the dummy electrodes DME may be arranged in a predetermined rule regardless of the sensing portion E1P1 of the first electrode E1 and the sensing portion E2P1 of the second electrode E2. The dummy electrodes DME may be arranged according to the same rule as that described with reference to <FIG>.

<FIG> are plan views of input sensors <NUM> according to embodiments of the present disclosure. In <FIG>, the same reference numerals denote the same elements in <FIG>, and thus, to the extent that an element is not described in detail herein, that element may be assumed to be at least similar to a corresponding element described elsewhere within the present disclosure.

Referring to <FIG>, second electrodes E2 may also have a double-routing structure. A fourth trace line TL4 may be connected to the second electrode E2 at a fourth point P4. The fourth trace line TL4 may overlap a non-sensing area <NUM>-NSA and may be connected to a fourth pad PD4. The fourth pad PD4 may be disposed adjacent to a first pad PD1. The fourth point P4 may also be disposed closer to the non-sensing area <NUM>-NSA than a second point P2 is. The fourth point P4 may be located at a position opposite to a third point P3 in the second direction DR2.

Referring to <FIG>, a first trace line TL1 and a second trace line TL2 may be branched from a pad connection line PCL at one point of a non-sensing area <NUM>-NSA. Accordingly, the first trace line TL1 and the second trace line TL2 may be electrically connected to a first pad PD1 via the pad connection line PCL. The second pad PD2 (refer to <FIG>) of the input sensor <NUM> of <FIG> may be omitted from the input sensor of <FIG>.

Referring to <FIG>, the input sensor <NUM> may further include at least one input sensor disposed between a first input sensor <NUM> and a second input sensor <NUM>. <FIG> show the input sensor <NUM> further including a third input sensor <NUM> and a fourth input sensor <NUM> as a representative example. The third input sensor <NUM> and the fourth input sensor <NUM> may be respectively disposed in a third sensing area <NUM>-SA3 and a fourth sensing area <NUM>-SA4 of a sensing area <NUM>-SA. The third input sensor <NUM> and the fourth input sensor <NUM> may have substantially the same structure. Hereinafter, descriptions of the input sensors <NUM> and <NUM> will be focused on the third input sensor <NUM>.

Referring to the first input sensor <NUM> to the fourth input sensor <NUM> of <FIG>, fewer sensing electrodes are illustrated as compared with <FIG> and <FIG>, and fewer trace lines are illustrated as corresponding to the sensing electrodes. First electrodes E1 and E1-<NUM> corresponding to each other and second electrodes E2 and E2-<NUM> corresponding to each other of the first input sensor <NUM> to the fourth input sensor <NUM> are shown.

Referring to <FIG>, the third input sensor <NUM> may include the first electrode E1-<NUM> (hereinafter, referred to as a first-first electrode) corresponding to the first electrode E1 of the first input sensor <NUM> and the second electrode E2-<NUM> (hereinafter, referred to as a second-first electrode) corresponding to the second electrode E2 of the first input sensor <NUM>. The third input sensor <NUM> may include a second trace line TL2-<NUM> (hereinafter, referred to as a second-first trace line) corresponding to a second trace line TL2 of the first input sensor <NUM>, a third trace line TL3-<NUM> (hereinafter, referred to as a third-first trace line) corresponding to a third trace line TL3 of the first input sensor <NUM>, and a fourth trace line TL4-<NUM> (hereinafter, referred to as a fourth-first trace line) corresponding to a fourth trace line TL4.

Different reference numerals are assigned to distinguish and explain the electrodes corresponding to each other and the trace lines corresponding to each other. The first electrode E1 and the second electrode E2 of the first input sensor <NUM> may correspond to the first-first electrode E1-<NUM> and the second-first electrode E2-<NUM> of the third input sensor <NUM> and may be distinguished from the first-first electrode E1-<NUM> and the second-first electrode E2-<NUM> of the third input sensor <NUM>. In addition, the first-first electrode E1-<NUM> and the second-first electrode E2-<NUM> of the second input sensor <NUM> or the first-first electrode E1-<NUM> and the second-first electrode E2-<NUM> of the fourth input sensor <NUM> may be used in the present disclosure to explain and distinguish them from the first electrode E1 and the second electrode E2 of the first input sensor <NUM>.

The first electrode E1 of the first input sensor <NUM> and the first-first electrode E1-<NUM> of the third input sensor <NUM> may have the single-routing structure. The second electrode E2 of the first input sensor <NUM> and the second-first electrode E2-<NUM> of the third input sensor <NUM> may have the double-routing structure. When compared with <FIG>, the first trace line TL1 (refer to <FIG>) and the first pad PD1 (refer to <FIG>) are omitted from the input sensor in <FIG>. The second-first trace line TL2-<NUM> may overlap the first-first electrode E1-<NUM> and might not overlap the second-first electrode E2-<NUM> in the third sensing area <NUM>-SA3 as the second trace line TL2 described with reference to <FIG> and <FIG>.

Referring to <FIG>, the first electrode E1 of the first input sensor <NUM> and the first-first electrode E1-<NUM> of the third input sensor <NUM> may have the double-routing structure. The second electrode E2 of the first input sensor <NUM> and the second-first electrode E2-<NUM> of the third input sensor <NUM> may have the single-routing structure. When compared with <FIG>, the fourth trace line TL4 (refer to <FIG>) and the fourth pad PD4 (refer to <FIG>) are omitted from the input sensor in <FIG>.

A second-first trace line TL2-<NUM> may overlap the first-first electrode E1-<NUM> and might not overlap the second-first electrode E2-<NUM> in the third sensing area <NUM>-SA3 as the second trace line TL2 described with reference to <FIG> and <FIG>. A first-first trace line TL1-<NUM> may overlap the first sensing area <NUM>-SA1 and the third sensing area <NUM>-SA3. The first-first trace line TL1-<NUM> may extend substantially in the same direction as the first electrode E1 and the first-first electrode E1-<NUM> in the first sensing area <NUM>-SA1 and the third sensing area <NUM>-SA3.

<FIG> is an enlarged plan view of one sensing unit SU3 (hereinafter, referred to as a third sensing unit) of <FIG>. The third sensing unit SU3 may be substantially the same as the sensing units SU of <FIG> and may be substantially the same as the first sensing unit SU1 and the second sensing unit SU2 described with reference to <FIG> and <FIG>.

Referring to <FIG>, the first-first trace line TL1-<NUM> may overlap the first electrode E1 and the second electrode E2. An overlap area between the first-first trace line TL1-<NUM> and the first electrode E1 may be greater than an overlap area between the first-first trace line TL1-<NUM> and the second electrode E2 in the third sensing unit SU3. The first-first trace line TL1-<NUM> may overlap intermediate portions E2P2 of divided electrodes E2D1, E2D2, and E2D3 and sensing portion E1P1 of sensing patterns E1D1. An influence of the first-first trace line TL1-<NUM> on the second electrode E2 may be reduced by reducing the overlap area of the first-first trace line TL1-<NUM> and the second electrode E2.

Referring to <FIG>, the first electrode E1 of the first input sensor <NUM> and the first-first electrode E1-<NUM> of the third input sensor <NUM> may have the double-routing structure. The second electrode E2 of the first input sensor <NUM> and the second-first electrode E2-<NUM> of the third input sensor <NUM> may have the double-routing structure.

Claim 1:
A display device, comprising:
a display panel (<NUM>) comprising a display area (<NUM>-DA) and a non-display area (<NUM>-NDA) adjacent to the display area (<NUM>-DA); and
a first input sensor (<NUM>) at least partially overlapping a first area of the display area (<NUM>-DA); and
a second input sensor (<NUM>) at least partially overlapping a second area of the display area (<NUM>-DA),
wherein the first input sensor (<NUM>) comprises:
an insulating layer (<NUM>, <NUM>, <NUM>);
a first electrode (E1);
a second electrode (E2) intersecting the first electrode (E1);
a first trace line (TL1) having one end electrically connected to the first electrode (E1) and another end connected to a first pad (PD1);
a third trace line (TL3) having one end electrically connected to the second electrode (E2) and another end connected to a third pad (PD3), and
a second trace line (TL2) having one end electrically connected to the first electrode (E1) and another end connected to a second pad (PD2);
wherein the second trace line (TL2) at least partially overlaps the first area of the display area (<NUM>-DA), at least partially overlaps the first electrode (E1), and does not overlap the second electrode (E2) in the first area of the display area (<NUM>-DA),
wherein the first electrode (E1) includes a plurality of sensing patterns (E1D1) extending in the second direction (DR2) and spaced apart from each other in the first direction (DR1) in the display area (<NUM>-DA) and bridge patterns (E1D2) connecting neighbouring pairs of sensing patterns,
wherein the second electrode (E2) comprises a plurality of divided electrodes (E2D1, E2D2, E2D3) each extending in a second direction (DR2) crossing the first direction (DR1) in the display area (<NUM>-DA) and spaced apart from each other in the first direction (DR1), and
the second trace line (TL2) is disposed between the divided electrodes (E2D1, E2D2, E2D3) in the display area (<NUM>-DA),
wherein the sensing patterns (E1D1) are disposed between the divided electrodes (E2D1, E2D2, E2D3).