Patent Description:
In communication systems, communication channels are subject to channel noise and, thus, errors can be introduced during transmission from a source to a receiver of digital data. Accordingly, various error detection techniques as well as error correction techniques are often utilized to detect and correct errors to enable reliable delivery of digital data over unreliable communication channels. Polar codes are a type of error correction codes that are linear block error correcting codes. The construction of Polar codes is based on a multiple recursive concatenation of a short kernel code, which transforms the physical channel into virtual outer channels. As the number of recursions increases, the virtual channels tend to have either high reliability or low reliability (and hence are polarized, and data bits can be allocated to the most reliable channel(s) for reliable delivery of the data. In other words, channel polarization is an effective way to transform or polarize a communication channel into better and worse sub-channels. Moreover, by properly exploiting the better sub-channels, it is feasible to approach channel capacity of the communication channel.

<NPL>, discloses an extension of polar codes to allow dynamic frozen symbols to be data dependent.

The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description. Under proposed schemes and concepts in accordance with the present disclosure, channel polarization and coding schemes that can effectively cover smaller codeblock sizes are combined. Advantageously, the combination generates a coding that can effectively cover larger codeblock sizes while realizing maximal reuse of smaller codeblock decoders at lower cost.

It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as Wi-Fi, LTE, LTE-Advanced, LTE-Advanced Pro, <NUM>th Generation (<NUM>), New Radio (NR) and Internet-of-Things (IoT), the proposed concepts, schemes and any variation(s)/derivative(s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies. Moreover, although various examples described herein are in the context of wireless communications, the proposed concepts, schemes and any variation(s)/derivative(s) thereof may be applicable to communications via one or more wired mediums where suitable. Thus, the scope of the present disclosure is not limited to the examples described herein.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of the present disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation in order to clearly illustrate the concept of the present disclosure.

In general, a large Polar code may be regarded as an inner polarization structure over "subcode" units, where each subcode may itself be a small Polar code. That is, a Polar code can be factored into multiple Polar subcodes with different code rates and connecting to an inner channel polarization structure. Selection of code rates may be based on the quality of the sub-channels and/or the total targeted data rate of per-channel usage. Under the proposed schemes in accordance with the present disclosure, by replacing the subcodes with another type of coding such as, for example and without limitation, turbo code, low-density parity-check (LDPC) code or tail-biting convolution code (TBCC), a large code (not Polar code) may be created. The large code may be capable of reusing subcode decoder(s) with additional simple successive cancellation decoding or successive cancellation list (SCL) decoding with a small list size over the inner polarization structure. Therefore, large codeword (Polar-like) performance may be achieved with subcode complexity. Reusing a smaller Polar decoder may be realized by sequentially decoding smaller Polar subcodes and perform Polar successive cancelation (SC) decoding on a per-subcode basis. Accordingly, memory/space complexity may be much reduced. As an example, for size-N successive cancellation list (SCL) decoding, the space complexity is O(LN) with list size of L. For hybrid size-N/M SCL and size-M SC decoding, the space complexity is O(LN/M + N). In this example, space complexity can be reduced to less than <NUM>% for L = <NUM> and M = <NUM>, and to less than <NUM>% for L = <NUM> and M = <NUM>. Similarly, computation/time complexity may also be reduced.

<FIG> illustrates an example design <NUM> with M = <NUM> in accordance with an implementation of the present disclosure. Example design <NUM> is an illustrative and non-limiting example of combined coding for efficient codeblock extension. The size-N/M subcodes shown in <FIG> may be Polar subcodes or other types of subcodes (e.g., turbo code, LDPC code or TBCC). Example design <NUM> combines channel polarization and coding scheme(s) (e.g., Polar code, turbo code, LDPC code and/or TBCC), which can effectively cover smaller codeblock sizes, to generate a coding that can effectively cover larger codeblock sizes while realizing maximal reuse of the smaller codeblock decoder(s) at relatively smaller cost. For instance, in the example shown in <FIG>, for hybrid size-N/M SCL and size-M SC decoding, the space complexity can be reduced from O(LN) to O(LN/M + N).

For Polar code, per-subcode cyclic redundancy check (CRC) are added on a per-subcode basis. When CRC-aided SCL decoding is used, local CRCs for the subcodes may be added. In some cases, specially designed mapping may be introduced before mapping to subcode input. The mechanism may also be added on a per-subcode basis. Addition on a per-subcode basis is a tradeoff regarding overhead.

In addition to per-subcode performance assistance, the proposed schemes in accordance with the present disclosure may add a global check to confirm the correctness of all information bits and/or message bits distributed to multiple sub-codes. <FIG> illustrates an example design <NUM> with M = <NUM> in accordance with an implementation of the present disclosure. In example <NUM>, the local CRC of the last subcode can be extended to check the validity of an entire message. There may be additional check/CRC over the entire message. In the example shown in <FIG>, for Polar code with N/M Polar subcode, subcode-wise decoding show only small loss with respect to whole codeword decoding.

<FIG> is an example chart <NUM> of performance in a simulation in accordance with an implementation of the present disclosure. In the simulation, N = <NUM>, M = <NUM> (with subcode size of <NUM>), code rate = <NUM>, and per-subcode <NUM>-bit CRC is performed with the last one also used as a global CRC. In terms of results, performance loss is up to <NUM>. 02dB with respect to SCL decoding over a size N of <NUM>. Additionally, memory/space complexity is reduced to less than <NUM>% in the simulation. Moreover, there is about <NUM>% reduction in computation/time complexity.

Under the proposed schemes, while each subcode may be a Polar code, in general a subcode may be another type of subcode such as, for example and without limitation, turbo code, LDPC code, TBCC or the like. By combining a subcode type with the channel polarization structure of size M, the subcode may be extended to cover up to M times of codeblock size with enhanced performance. For instance, this may be achieved by proper selection of per-subcode code rate. Alternatively or additionally, this may be achieved by SC decoding or SCL decoding with a small size to exploit the channel polarization structure. Advantageously, as a subcode decoder may be reused to decode a large code in a sequential manner, the overall decoder complexity to decode the large code may be kept around the same order as that of a small subcode decoder.

Under the proposed schemes, information bits and/or message bits may be properly allocated into each subcode according to the sub-channel quality after channel polarization. In some implementations, in a low-complexity realization, the good-bit selection scheme for Polar code may be reused. As an example, considering a size-N Polar code with targeted information bit number i, the good bit indices may be selected according to Polar code rate-matching design. Proper information bit number may be loaded into i-th subcode (with <NUM> ≤ i ≤ M-<NUM>) according to the number of good bit indices lying in the range iN/M to (i +<NUM>)N/(M-<NUM>). Then, each subcode may apply rate matching with respect to the assigned information bit number and code bit number N/M.

Accordingly, the proposed schemes in accordance with the present disclosure may be implemented to allow a control channel decoder, which can effectively decode small control messages, to decode a larger data message encoded by the combined structure according to the present disclosure. Moreover, the proposed schemes in accordance with the present disclosure may be implemented to extend a data coding design of a specified moderate codeblock size to a larger codeblock size to provide the capability of stronger protection over a wider resource span in terms of time, frequency and/or space. Furthermore, the proposed schemes in accordance with the present disclosure is implemented to combine retransmitted codeblock(s) as first sub-codeblock(s) and combine new data codeblock(s) as later sub-codeblock(s) so as to apply higher code rate(s) in new data codeblock(s) by exploiting channel polarization gain.

Under the proposed schemes, Polar code may be adapted to various output code bit length with much reduced complexity. Accordingly, the present disclosure provides a generic procedure to incorporate any suitable low-complexity rate matching designs. The following is a description of encoding design and decoding design in accordance with the present disclosure.

With respect to encoding design, the procedure in accordance with the present disclosure may involve a number of operations. Firstly, a Polar code may be constructed based on required information bit length K and code rate R. The number of code bit N and the punctured coded bit P may be determined by the following expressions: <MAT> <MAT>.

The procedure involves determining the punctured bitmap of size N. Here, value <NUM> may indicate puncture of the corresponding bit position and value <NUM> may denote no puncturing. The procedure also involves determining the frozen bitmap of size N. Here, value <NUM> may indicate frozen of the input value of the corresponding bit position to Polar encoder, and value <NUM> may indicate a variable input bit value that can be used to carry one information bit. The punctured bits may also be frozen bits.

Secondly, the Polar code of size N is partitioned into N subcodes. The size of N may be adjusted according to targeted subcode decoder complexity. The number B of subcodes may be determined by the following expression: <MAT>.

Thirdly, the proper CRC size with each subcode may be determined according to the following expression, with Ci denoting the CRC size in subcode i subject to a predefined set S = {s<NUM>, s<NUM>,. sk-<NUM>}: <MAT>.

Here, Ki is the number of information bits in the subcode i. Fi is the number of frozen bits in the subcode i. Pi is the number of punctured bits in the subcode i. M is the parameter used to keep sufficient number of information bit for CRC encoding and may be properly designed. In some implementations, the value of K may be set to <NUM>. The set S may be designed to include available or preferred CRC size(s). In some implementations, S = {<NUM>, <NUM>, <NUM>, <NUM>}.

Fourthly, CRC bit insertion is performed. The punctured bitmap obtained during construction of the Polar code may not be modified. Thus, the code rate R may not be changed by additional CRC bit insertion. The procedure may involve determining a new frozen bitmap with number of information bit = K + sum of Ci with i varying from <NUM> to B. The procedure may also involve inserting CRC bits into un-frozen bit with lower index in each subcode.

With respect to decoding design, the procedure in accordance with the present disclosure may involve a number of operations. For each subcode, decoding may reuse a SCL decoder with a targeted list size L. CRC may be performed at the end of subcode during list decoding if Ci ≠ <NUM>. The subcode CRC may be used to down-select the information paths passing the CRC check with the L' best path metrics. In some implementations, decoder complexity reduction may be prioritized with L' = <NUM>. After finishing decoding a subcode, the decoder may perform a subcode-wise SCL decoding of list L' so as to acquire the input to a next subcode given its lower indexed subcode decoding result(s).

It is noteworthy that Polar code rate-matching design may be considered. According to the mother code rate of Polar code of size N before rate-matching, some channel output soft values may be set to <NUM> or a value of large magnitude corresponding to known bit sign. Accordingly, multi-CRC aided Polar decoding may be used to decode a Polar code with rate matching and multiple CRC insertions.

In view of the above, it may be appreciated by those with ordinary skill in the art that there may be numerous possible applications of the proposed schemes, such as in <NUM>/NR wireless communication networks. An example application may be Ultra-Reliable Low Latency Communications (URLLC) data by Polar coding in <NUM>/NR networks. In this application, control Polar decoder may apply list-decoding for Polar size of N ≤ <NUM>. A larger Polar code may be required to cover data of size greater than <NUM>. To allow reusing of small Polar decoder, a large Polar code may be factored into size-<NUM> Polar subcodes with insertion of per-subcode CRC to enable reusing of small Polar decoder for each subcode.

Another example application of the proposed schemes may be URLLC data by LDPC coding. In this application, data channel of URLLC may utilize enhanced Mobile Broadband (eMBB) data channel coding such as LDPC, for example. The lowest code rates may be <NUM>/<NUM> or <NUM>/<NUM>. Without redesigning LDPC, the polarized LDPC design may have the potential to provide even lower code rates. Since Polar code has no error floor, the polarized LDPC may also have the potential to improve the error floor performance of existing LDPC.

A further example application of the proposed schemes may be enhanced Machine Type Communications (eMTC). In this application, Narrowband Internet of Things (NB-IoT) utilizing TBCC may be considered for <NUM>/NR eMTC. TBCC is simple, yet its performance for codeblock size greater than <NUM> bits is inferior to Polar and LDPC. Applying the proposed coding combination and extension scheme with TBCC and inner polarization structure, data channel performance can be improved while keeping low cost benefit of TBCC.

<FIG> illustrates an example apparatus <NUM> in accordance with an implementation of the present disclosure. Apparatus <NUM> may perform various functions to implement schemes, techniques, processes and methods described herein pertaining to combined coding design for efficient codeblock extension in communication systems, including designs <NUM> and <NUM> described above as well as process <NUM> described below.

Apparatus <NUM> may be a part of an electronic apparatus, which may be a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus. For instance, apparatus <NUM> may be implemented in a smartphone, a smartwatch, a personal digital assistant, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. In the context of a communications system, apparatus <NUM> may be implemented in or as part of a user equipment (UE) or a base station (e.g., eNB, gNB or transmit-and-receive point (TRP)). In some implementations, apparatus <NUM> maybe a part of a machine type apparatus, which may be an IoT apparatus such as an immobile or a stationary apparatus, a home apparatus, a wire communication apparatus or a computing apparatus. For instance, apparatus <NUM> may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. Alternatively, apparatus <NUM> may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, or one or more complex-instruction-set-computing (CISC) processors. Apparatus <NUM> may include at least some of those components shown in <FIG> such as a processor <NUM>, for example. Apparatus <NUM> may further include one or more other components not pertinent to the proposed scheme of the present disclosure (e.g., internal power supply, display device and/or user interface device). Such component(s) of apparatus 400are neither shown in <FIG> nor described below in the interest of simplicity and brevity.

In one aspect, processor <NUM> may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, even though a singular term "a processor" is used herein to refer to processor <NUM>, processor <NUM> may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, processor <NUM> may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, processor <NUM> is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including those pertaining to combined coding design for efficient codeblock extension in accordance with various implementations of the present disclosure.

In some implementations, apparatus <NUM> may also include a communication device430 coupled to processor <NUM>. Communication device430 may include a transceiver capable of transmitting and receiving data wirelessly and/or via one or more wired mediums.

In some implementations, apparatus <NUM> may further include a memory 420coupled to processor <NUM> and capable of being accessed by processor <NUM> and storing data therein. Memory <NUM> may include a type of random-access memory (RAM) such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM). Alternatively or additionally, memory <NUM> may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, memory <NUM> may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and/or phase-change memory.

In some implementations, processor <NUM> may include a combining circuit <NUM> and a coding circuit <NUM>. Combining circuit <NUM> may be capable of combining channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme. Coding circuit <NUM> may be capable of coding second codeblocks of a larger size using the second coding scheme.

In some implementations, the first coding scheme may utilize one or more smaller codeblock decoders configured to decode the first codeblocks of the smaller size. Accordingly, in coding the second codeblocks of the larger size using the second coding scheme, coding circuit 414may decode the second codeblocks of the larger size by reusing the one or more smaller codeblock decoders of the first coding scheme.

In some implementations, in decoding the second codeblocks of the larger size by reusing the one or more smaller codeblock decoders, coding circuit 414may decode the second codeblocks of the larger size by reusing one or more smaller Polar decoders.

In some implementations, in combining the channel polarization and the first coding scheme, combining circuit 412may factor a large code into a plurality of subcodes with different code rates and connected to an inner channel polarization structure.

In some implementations, in factoring the large code into the plurality of subcodes with different code rates, combining circuit 412may select the different code rates based on a quality of one or more sub-channels of the communication channel as a result of the channel polarization. Alternatively or additionally, in factoring the large code into the plurality of subcodes with different code rates, combining circuit 412may select the different code rates based on a total targeted data rate of per-channel usage.

In some implementations, in factoring the large code into the plurality of subcodes, combining circuit 412may allocate the large code into a plurality of Polar subcodes, a plurality of turbo codes, a plurality of low-density parity-check (LDPC) codes, or a plurality of tail-biting convolution codes (TBCCs).

In some implementations, in decoding the second codeblocks of the larger size using the second coding scheme, coding circuit 414may sequentially decode the plurality of subcodes. Additionally, coding circuit <NUM> may perform successive cancellation (SC) decoding or successive cancellation list (SCL) decoding with a small list size on a per-subcode basis.

In some implementations, in decoding the second codeblocks of the larger size using the second coding scheme, coding circuit 414may also perform cyclic redundancy check (CRC) on a per-subcode basis. Moreover, coding circuit <NUM> may perform a global check for correctness of a plurality of bits distributed into the plurality of subcodes.

In some implementations, the plurality of subcodes may include a plurality of Polar subcodes. Accordingly, in decoding the second codeblocks of the larger size using the second coding scheme, coding circuit 414may sequentially decode the plurality of Polar subcodes. Moreover, coding circuit <NUM> may perform Polar SC decoding or SCL decoding with a small list size on a per-subcode basis.

<FIG> illustrates an example process <NUM> in accordance with an implementation of the present disclosure. Process <NUM> may represent an aspect of implementing the proposed concepts and schemes such as one or more of the various schemes described above with respect to designs <NUM> and <NUM> as well as apparatus <NUM>. More specifically, process <NUM> may represent an aspect of the proposed concepts and schemes pertaining to combined coding design for efficient codeblock extension in communication systems. For instance, process <NUM> may be an example implementation, whether partially or completely, of the proposed scheme described above for combined coding design for efficient codeblock extension in communication systems. Process <NUM> may include one or more operations, actions, or functions as illustrated by one or more of blocks <NUM> and <NUM>. Although illustrated as discrete blocks, various blocks of process <NUM> may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process <NUM> may be executed in the order shown in <FIG> or, alternatively in a different order. The blocks/sub-blocks of process <NUM> may be executed iteratively. Process <NUM> may be implemented by or in apparatus <NUM> as well as any variations thereof. Solely for illustrative purposes and without limiting the scope, process <NUM> is described below in the context of apparatus <NUM> implemented as a communication apparatus (e.g., a UE such as a smartphone). Process <NUM> may begin at block <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> of apparatus 400combining channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> coding second codeblocks of a larger size using the second coding scheme.

In some implementations, the first coding scheme may utilize one or more smaller codeblock decoders configured to decode the first codeblocks of the smaller size. Accordingly, in coding the second codeblocks of the larger size using the second coding scheme, process <NUM> may involve processor <NUM> decoding the second codeblocks of the larger size by reusing the one or more smaller codeblock decoders of the first coding scheme.

In some implementations, in decoding the second codeblocks of the larger size by reusing the one or more smaller codeblock decoders, process <NUM> may involve processor <NUM> decoding the second codeblocks of the larger size by reusing one or more smaller Polar decoders.

In some implementations, in combining the channel polarization of the communication channel with the first coding scheme, process <NUM> may involve processor <NUM> factoring a large code into a plurality of subcodes with different code rates and connected to an inner channel polarization structure.

In some implementations, in factoring the large code into the plurality of subcodes with different code rates, process <NUM> may involve processor <NUM> selecting the different code rates based on a quality of one or more sub-channels of the communication channel as a result of the channel polarization. Alternatively or additionally, in factoring the large code into the plurality of subcodes with different code rates, process <NUM> may involve processor <NUM> selecting the different code rates based on a total targeted data rate of per-channel usage.

In some implementations, in factoring the large code into the plurality of subcodes, process <NUM> may involve processor <NUM> allocating the large code into a plurality of Polar subcodes, a plurality of turbo codes, a plurality of LDPC codes, or a plurality of TBCCs.

In some implementations, in decoding the second codeblocks of the larger size using the second coding scheme, process <NUM> may involve processor <NUM> sequentially decoding the plurality of subcodes. Additionally, process <NUM> may involve processor <NUM> performing SC decoding or SCL decoding with a small list size on a per-subcode basis.

In some implementations, in decoding the second codeblocks of the larger size using the second coding scheme, process <NUM> may involve processor <NUM> performing additional operations. For instance, process <NUM> may involve processor <NUM> performing CRC on a per-subcode basis. Moreover, process <NUM> may involve processor <NUM> performing a local check for correctness of a plurality of bits distributed into the plurality of subcodes.

In some implementations, the plurality of subcodes may include a plurality of Polar subcodes. Accordingly, in decoding the second codeblocks of the larger size using the second coding scheme, process <NUM> may involve processor <NUM> sequentially decoding the plurality of Polar subcodes. Furthermore, process <NUM> may involve processor <NUM> performing Polar SC decoding or SCL decoding with a small list size on a per-subcode basis.

Claim 1:
A method, comprising:
combining, by a combining circuit (<NUM>) of a processor (<NUM>) of an apparatus, channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme (<NUM>); and
coding, by a coding circuit (<NUM>) of the processor (<NUM>), second codeblocks of a larger size using the second coding scheme (<NUM>);
wherein the combining, by the combining circuit (<NUM>) of the processor (<NUM>) of the apparatus, channel polarization of the communication channel with the first coding scheme for the first codeblocks of the smaller size to generate the second coding scheme (<NUM>) comprises:
factoring a large code into a plurality of subcodes with different code rates by a plurality of subcoders;
determining a punctured bitmap and a frozen bitmap;
performing per-subcode cyclic redundancy check, CRC, by a plurality of CRC circuits (CRC<NUM>,CRC<NUM>,CRC<NUM>,CRC<NUM>) each coupled to an input of a respective one of the plurality of mapping circuits (A<NUM>, A<NUM>, A<NUM>, A<NUM>), each coupled to an input of a respective one of the plurality of subcoders, wherein the punctured bitmap and the frozen bitmap are used to determine information bit locations, and
combining retransmitted codeblock(s) as first sub-codeblock(s) and combining new data codeblock(s) as later sub-codeblock(s) for exploiting channel polarization gain;
wherein, during operation:
each sub-block of a plurality of sub-blocks of a message to be coded is provided to a respective one of the plurality of CRC circuits (CRC<NUM>,CRC<NUM>,CRC<NUM>,CRC<NUM>), and
an output of each of the plurality of subcoders is added to an output of each of one or more other subcoders of the plurality of subcoders.