Patent Description:
<CIT> relates to a layer system used in the production of micro-electromechanical structures comprising a passivating layer consisting of an inorganic partial layer and a polymeric partial layer formed on a silicon layer.

<CIT> relates to a semiconductor component with backside contacts.

<CIT> relates a method of forming a through-substrate interconnect.

Background of Related Art: The parallel trends of ever-decreasing size and ever-increasing ability in the electronics industry have driven a need for semiconductor devices, semiconductor device assemblies, and semiconductor device packages of ever-decreasing size and ever-increasing feature density. One approach that has been taken to facilitate these trends has been to make as many electrical connections between components as possible in a given amount of "real estate," or area. This approach is applicable to both adjacent components and non-adjacent components.

Conductive vias have been used to provide electrical pathways between components that are superimposed relative to one another, but that are not directly adjacent to each other. A conductive via, which may be formed through a circuit board, an interposer, or a semiconductor device, provides such an electrical pathway. Conductive vias typically include a hole formed through the substrate, an insulative lining, if the substrate is formed from a semiconductive or conductive material, and a conductive element that passes through the opening and which may be electrically isolated from the substrate by way of the insulative lining. As with most features of semiconductor devices, the dimensions of the various elements of conductive vias also continue to decrease.

<CIT> (hereinafter "Farnworth"), describes exemplary processes for forming conductive vias through semiconductor device structures. In current state-of-the-art processes for fabricating conductive vias, via holes are lined with materials with low dielectric constants, such as parylene and the fluoropolymer resins (including, but not limited to, polytetrafluoroethylene ("PTFE"), fluorinated ethylenepropylene ("FEP"), ethylene-tetrafluoroethylene ("ETFE"), chlorotrifluoroethylene ("CTFE"), and perfluoroalkoxyalkane ("PFA"), which are marketed by E. du Pont de Nemours and Company under the trademark TEFLON®). Although these and similar materials may be used to form very thin insulative coatings <NUM> on the surfaces of via holes, they do not adhere well to the materials (e.g., silicon) of many substrates through which via holes are formed or to the conductive materials that are subsequently introduced into the via holes to form an electrically conductive via.

The low adhesion of such dielectric materials, as well the potential for misalignment when multiple masks are used to form and passivate via holes may result in shorting between a conductive via and the substrate through which the conductive via extends.

In addition, some of the processes that are currently used to fabricate conductive vias are complex, require expensive materials or equipment that is not widely used in semiconductor device fabrication processes, or are otherwise undesirable.

Accordingly, there are needs for processes for fabricating conductive vias with state-of-the-art dimensions and capabilities while employing common semiconductor device fabrication techniques.

Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.

In the drawings, which depict exemplary embodiments of various aspects of the present invention:.

A semiconductor device structure <NUM> according to the present invention may, without limitation, comprise a semiconductor device (e.g., a memory device, such as a dynamic random access memory ("DRAM"), static random access memory ("SRAM"), flash memory, electrically-erasable programmable memory ("EEPROM"), magnetic random access memory ("MRAM"), etc.; a microprocessor; a microcontroller; an imaging device; or any other type of semiconductor device), another electronic component that may be fabricated by semiconductor device fabrication techniques, or a substrate (e.g., an interposer, a circuit board, etc.).

As <FIG> illustrates, a semiconductor device structure <NUM> according to the present invention includes a substrate <NUM> with an active surface <NUM> and a back side <NUM> opposite from active surface <NUM>. Substrate <NUM> may comprise a full or partial wafer of semiconductor material (e.g., silicon, gallium arsenide, indium phosphide, etc.), a semiconductor-on-insulator ("SOI") type substrate (e.g., silicon-on-glass ("SOG"), silicon-on-sapphire ("SOS"), silicon-on-ceramic ("SOC"), etc.), or even a dielectric (e.g., glass, sapphire, ceramic, polymer, resin, etc.) or metal substrate.

Semiconductor device structure <NUM> may be processed to form one or more conductive vias that extend partially into or completely through substrate <NUM>. Processes of the present invention may be effected at the "wafer level" or "wafer scale," prior to separation of adjacent components from one another, as described in Farnworth.

With reference to <FIG>, in forming via holes <NUM> (<FIG>) through substrate <NUM>, a mask <NUM> may be formed over a surface (e.g., active surface <NUM>) of substrate <NUM>. Mask <NUM> may be formed by known processes. For example, a photoresist may be disposed on active surface <NUM> of substrate <NUM>, selectively exposed through a reticle,
then developed, baked, or otherwise processed, as known in the art, to form a photo resist mask, or "photomask.

Apertures <NUM> of mask <NUM> are positioned so as to facilitate material removal from portions of one or more upper bond pads <NUM> that are carried by active surface <NUM> of substrate <NUM> and, thus, the formation of via holes <NUM> (<FIG>) through upper bond pads <NUM>. Apertures <NUM> may be configured so as to form via holes <NUM> with desired. cross-sectional shapes (e.g., circular, square, etc.).

As shown in <FIG>, via holes <NUM> may be formed through upper bond pads <NUM> and into substrate <NUM> by exposing the portions (e.g., center portions 15c) of. upper bond pads <NUM> and substrate <NUM> that are exposed through apertures <NUM> to one or more etchants suitable for removing the material of upper bond pads <NUM>, substrate <NUM>, and any intervening material layers. While the etchant or etchants that are used to form via holes <NUM> may be isotropic (i.e., etch in all directions at substantially the same rate) or anisotropic (i.e., not isotropic), anisotropic etchants are particularly useful. for forming via holes <NUM> with high aspect ratios (i.e., height-to-width, or cross-sectional dimension, ratios). Material may be removed from substrate <NUM> through apertures <NUM> of mask <NUM> until via holes <NUM> of desired depth have been formed. Alternatively, known laser drilling processes may be used, with or without a mask, to form via holes <NUM> in substrate <NUM>.

A single mask <NUM> may be used in the process shown in <FIG>. For example, a first etchant may be used to remove material of upper bond pads <NUM> through apertures <NUM>. A second etchant or solvent may be used to remove material (e.g., borophosphosilicate glass (BPSG), a polymer, etc.) of one or more protective layers <NUM> that laterally surround and may underlie upper bond pad <NUM> through apertures <NUM>, prior to the complete removal of mask <NUM>. As mask <NUM> may be partially or substantially removed while upper bond pads <NUM> and protective layer <NUM> are etched, protective layer <NUM> and the remaining portions of upper bond pads <NUM> may then serve as a mask through which material (e.g., silicon) of substrate <NUM> is removed. Of course, the etchant or etchants that are used to remove material of substrate <NUM> are selective for the material of substrate <NUM> over the materials of upper bond pads <NUM> and protective layer <NUM> (i.e., the etchant removes the material of substrate <NUM> at a faster rate than the materials of upper bond pads <NUM> and protective layer <NUM>). The use of a single mask <NUM> prevents misalignment of the sections of a via hole <NUM> that extend through different materials.

The resulting via holes <NUM> may comprise blind via holes, as illustrated, which do not extend fully through substrate <NUM> and, thus, include blind ends <NUM>: Blind via holes <NUM> facilitate vacuum handling of semiconductor device structure <NUM> or a fabrication substrate (not shown) by which semiconductor device structure <NUM> is carried during fabrication of conductive vias through semiconductor device structure <NUM>.

Alternatively, as depicted in <FIG>, open via holes <NUM>', which extend completely through substrate <NUM>, may be formed by removing the material of substrate <NUM> through apertures <NUM> of mask <NUM>.

If a photomask was used as mask <NUM> to facilitate material removal from selected locations of upper bond pads <NUM>, substrate <NUM>, and any other material layers or features of semiconductor device structure <NUM>, the photomask may be removed once the material removal processes have been completed.

The surface <NUM> or surfaces of each via hole <NUM>, <NUM>' may be sufficiently rough to facilitate adhesion of materials thereto. Such roughness may be achieved through the material removal process by which via holes <NUM>, <NUM>' are formed, or by subsequent processing. For example, without limiting the scope of the present invention, via holes <NUM>, <NUM>' may be formed by a tetramethylammonium hydroxide ("TMAH") wet etch (e.g., <NUM>:<NUM><NUM>O:TMAH), a wet etch with NH<NUM>F (ammonium fluoride), H<NUM>O<NUM> (peroxide), and C<NUM>H<NUM>O<NUM> (citric acid) (e.g., <NUM>:<NUM>:<NUM> NH<NUM>F:H<NUM>O<NUM>: C<NUM>H<NUM>O<NUM>), with an SF<NUM>. plasma etch, by a deep silicon reactive ion etch ("RIE"), or the like. Alternatively, via holes <NUM>, <NUM>' that have been formed by other processes may be roughened by use of a suitable roughening technique, such as one of the just-described etch techniques.

With reference to <FIG>, if substrate <NUM> is formed from a semiconductor material or a conductive material, surfaces <NUM> of via holes <NUM> may be lined or coated with dielectric material to form a dielectric coating <NUM>, which prevents electrical shorting as electrical currents are conveyed along circuitry that extends into or through via holes <NUM>. The thickness of dielectric coating <NUM> may be tailored to position a subsequently formed conductive via at a desired location relative to a surface <NUM> or blind end <NUM> of via hole <NUM>.

As a nonlimiting example, dielectric coating <NUM> may include a parylene, a low-silane oxide ("LSO") (which is deposited by chemical vapor deposition ("CVD") at a relatively low temperature), a material layer (e.g., an aluminum-rich oxide, etc.) that has been deposited by pulsed deposition processes and, thus, is referred to as a pulsed deposition layer ("PDL"), or any combination of dielectric materials or layers may be applied to or deposited onto exposed surfaces of substrate <NUM> by known processes (e.g., spin coating, spraying, programmed material consolidation processes (e.g., those effected by the systems available from Objet Geometries, Ltd. , of Rehovot, Israel, 3D Systems Corporation of Valencia, California, etc.), CVD, thermal growth, spin-on dielectric ("SOD") techniques (e.g., spin-on glass ("SOG" processes), etc.). Examples of processes for forming dielectric layers are disclosed in <CIT> and <CIT>, as well as in U. Patent
Publications <CIT>, <CIT>, and <CIT>.

If desired, portions of dielectric coating <NUM>, for example, portions that cover upper bond pads <NUM> or other locations of active surface <NUM>, may be subsequently removed. Suitable techniques for selectively removing various regions of dielectric coating <NUM> include, but are not limited to, dry etch processes and wet etch processes. For example, spacer etch techniques, in which the etch process is effected at a low pressure that imparts ions with a direction energy that removes material from horizontal surfaces without substantially removing it from vertical surfaces, may be used to selectively remove portions or, or pattern, dielectric coating <NUM>. Such processes may be timed or an end point detected to prevent undesired removal of materials from within via holes <NUM> (e.g., from surfaces <NUM>). Other techniques for selectively removing regions of dielectric coating <NUM> may be effected with our without a mask (e.g., a photomask, which may be sprayed on, for example, by sonic dispense processes), which substantially fills via holes <NUM> and through which upper bond pads <NUM> are exposed, with active surface <NUM> either shielded by or exposed through the mask. When a mask is used, wet or dry, isotropic or anisotropic etch processes may be used to pattern dielectric coating <NUM>. Of course, once dielectric coating <NUM> has been patterned, the mask may be removed (e.g., by known resist strip techniques). As another alternative, planarization or polishing processes, such as chemical mechanical
planarization ("CMP") may be used to remove dielectric coating <NUM> from active surface <NUM> and surfaces of upper bond pads <NUM>.

In forming a dielectric coating <NUM> on surface <NUM> of via hole <NUM>, surface <NUM> of via hole <NUM> is first coated with a first adhesion layer <NUM> comprising an oxide, such as a silicon oxide. The oxide of first adhesion layer <NUM> may be formed by any suitable process, including by deposition using tetraethylorthosilicate ("TEOS"), thermal growth processes, or low-temperature oxidation processes. First adhesion layer <NUM> may facilitate adhesion of a material having an even lower dielectric constant ("K") over surface <NUM> of via hole <NUM>.

A dielectric material having a relatively low dielectric constant of K≈<NUM> is deposited onto adhesion layer <NUM> that coats at least portions of surface <NUM>. Of course, the processes that are used to form dielectric layers <NUM> are compatible with the material or materials from which dielectric layers <NUM> are to be formed, as well as the materials or structures over which dielectric material is to be formed or deposited. Examples of low-K dielectric materials that may be deposited over surface <NUM> include, but are not limited to, parylenes (e.g., PARYLENE HT®), TEFLON®, and other dielectric materials with low dielectric constants of K≈<NUM> that may be deposited on features (e.g., within via holes <NUM>) with relatively high aspect ratios to form relatively thin dielectric layers <NUM>.

A second adhesion layer <NUM> is formed over dielectric layer <NUM> to facilitate adhesion of conductive materials over the surface <NUM> of each via hole <NUM>. Like first adhesion layer <NUM>, second adhesion layer <NUM> comprises an oxide, such as a silicon oxide. Any suitable process may be used to form adhesion layer <NUM>, including, without limitation, deposition of the material of second adhesion layer <NUM> (e.g., with TEOS when second adhesion layer <NUM> comprises a silicon oxide).

Portions of first adhesion layer <NUM>, dielectric layer <NUM>, and second adhesion layer <NUM> that overlie each upper bond pad <NUM> may be removed therefrom to facilitate communication between subsequently formed conductive structures and upper bond pad <NUM>. The removal of the dielectric materials of these layers <NUM>, <NUM>, or <NUM> may be effected simultaneously/sequentially, as shown in <FIG>, or immediately following the formation of each sequential layer <NUM>, <NUM>, or <NUM>.

Layers <NUM>, <NUM>, <NUM> are referred to hereinafter, individually or in any combination, as "dielectric coating <NUM>.

Referring now to <FIG>, a barrier layer <NUM> may be formed over dielectric coating <NUM>. Barrier layer <NUM> is particularly useful for preventing undesirable reactions between copper conductors within via holes <NUM> and the exposed material of dielectric coating <NUM> or substrate <NUM>. Suitable materials from which barrier layer <NUM> may be formed include, without limitation, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and other materials that prevent interdiffusion and spiking between copper and silicon and silicon-containing materials.

As illustrated, barrier layer <NUM> may be formed by so-called "blanket" deposition processes, in which upper exposed surfaces (e.g., active surface <NUM>, surfaces exposed within via hole <NUM>, etc.) of semiconductor device structure <NUM> are coated with the material of barrier layer <NUM>. To facilitate the subsequent, selective deposition of conductive material, for example, on upper bond pads <NUM> and surfaces <NUM> of barrier layer <NUM>, as depicted in <FIG>, the material of barrier layer <NUM> may be removed from locations of semiconductor device structure <NUM> or substrate <NUM> thereof (e.g., active surface <NUM>) where deposition of conductive material could be problematic (e.g., cause electrical shorting) or is otherwise not desired. The removal of unwanted barrier material may be effected by a variety of known processes, including, but not limited to, spacer etching, polishing or planarization techniques (e.g., mechanical polishing, chemical mechanical polishing ("CMP"), etc.), or otherwise, as known in the art.

Surfaces <NUM>, <NUM>, <NUM> of via holes <NUM>, dielectric coating <NUM>, or barrier layer <NUM>, respectively, are at least partially coated with a seed material, which will facilitate subsequent growth of a desired conductive material on surfaces <NUM>, <NUM>, or <NUM>, as shown in <FIG>. Of course, the seed material of the resulting coating <NUM> facilitates growth or deposition of one or more desired types of conductive materials over surfaces <NUM>, <NUM>, or <NUM>. For example, when surface <NUM>, <NUM>, or <NUM> is to be lined with copper, the seed material coating <NUM> may itself comprise copper. A copper seed material coating may be formed by any suitable deposition technique, such as a physical vapor deposition ("PVD") process (e.g., sputtering) or a CVD process. As another example, any suitable process (e.g., PVD, CVD, etc.) may be used to form an aluminum film on surface <NUM>, <NUM> or <NUM>.

When blanket deposition techniques are used to form coating <NUM>, the seed material may cover all of the exposed surfaces of semiconductor device structure <NUM>, including areas where subsequent deposition of conductive material is not desired, (e.g., areas other than upper bond pads <NUM> and surface <NUM>, <NUM>, <NUM>). Accordingly, as illustrated in <FIG>, portions of seed material coating <NUM> may be removed from these areas. Any suitable technique may be used for this purpose, including, without limitation, known polishing or planarization techniques.

When via holes <NUM> are to be filled with copper, as an alternative to separately removing barrier layer <NUM> and seed material coating <NUM> from some of the surfaces of semiconductor device structure <NUM>, as shown in <FIG> and <FIG>, a single removal process may be used to remove both seed material coating <NUM> and barrier layer <NUM>. This single removal process may comprise any process suitable for removing barrier material and seed material from undesired locations on the exposed surface or surfaces of semiconductor device structure <NUM>, while leaving barrier material and seed material at locations where subsequent growth or deposition of conductive material is desired (e.g., on upper bond pads <NUM>, on surfaces <NUM>, <NUM>, <NUM> (<FIG>) within via holes <NUM>, etc.). Exemplary removal processes include, but are not limited to, known spacer etch techniques, polishing or planarization techniques, and the like.

Once seed material coating <NUM> has been formed and patterned, conductive material (e.g., a metal, conductor-filled polymer, etc.) may be selectively deposited on or otherwise applied to a surface <NUM> thereof to form a conductive layer <NUM> over surfaces <NUM> of via holes <NUM> and, optionally, over upper bond pads <NUM> or portions thereof, as shown in <FIG>. By way of nonlimiting example, known electroless plating, immersion plating, or electrolytic plating techniques may be used. Conductive material may be deposited until conductive layer <NUM> reaches a desired thickness, in which case a void <NUM> (<FIG> and <FIG>) may remain within via hole <NUM>, or until via hole <NUM> is completely filled; i.e., no void remains within via hole <NUM>.

<FIG> illustrates selective deposition of a conductive layer <NUM> on seed material coating <NUM>. For example, copper may be selectively deposited (e.g., by electroless or immersion plating; e.g., with the chemistry available from Pac Tech GmbH of Nauen, Germany) onto a seed material coating <NUM> that also comprises copper. Alternatively, a conductive layer <NUM> comprising nickel may be selectively deposited (e.g., by electroless or immersion plating; e.g., with the chemistry available from Pac Tech) on a seed material coating <NUM> that comprises aluminum.

As an alternative to selective techniques for depositing conductive material to form conductive layers <NUM> over surfaces <NUM> of via holes <NUM>, nonselective deposition processes may be employed. An exemplary method for forming conductive layers <NUM>' by nonselective deposition processes is shown in <FIG>.

In <FIG>, a mask <NUM>' is formed over active surface <NUM> by known processes. For example, and not to limit the scope of the present invention, mask <NUM>' may comprise a photomask that is formed by applying a photoresist over active surface <NUM>, selectively exposing the photoresist, developing the photoresist, removing undeveloped photoresist, then baking the photoresist. Mask <NUM>' includes apertures <NUM>' that are aligned over via holes <NUM> that have been formed within substrate <NUM>, lined with one or more dielectric material layers or coatings (e.g., dielectric coating <NUM> or sublayers thereof, including, without limitation, adhesion layers <NUM> and <NUM> and dielectric layer <NUM> (see <FIG>)), optionally coated with a barrier layer <NUM>, and optionally including a seed material coating <NUM>. Apertures <NUM>' need not expose entire upper bond pads <NUM>, as upper bond pads <NUM> may include a material or materials that facilitate adhesion of a desired material thereto.

As mask <NUM>' will physically separate portions of a subsequently formed conductive layer <NUM>', as shown (<FIG>), from portions of each of the aforementioned layers that overlie non-upper bond pad <NUM>-bearing regions of active surface <NUM> of substrate <NUM>, portions of seed material coating <NUM>, the optional barrier layer (not shown), and dielectric coating <NUM> that overlie non-upper bond pad <NUM>-bearing regions of active surface <NUM> need not be removed prior to the formation of conductive layer <NUM>'.

Conductive layer <NUM>' may be formed by any suitable process, including, but not limited to, PVD, CVD, electrolytic plating, electroless plating, and immersion plating techniques. Such a deposition or plating process may be used to form conductive layer <NUM>' on surfaces of seed material coating <NUM> that are exposed through aperture <NUM>' of mask <NUM>' and, when the deposition process is not selective, on exposed surfaces of mask <NUM>'. By way of nonlimiting example, a conductive layer <NUM>' comprising nickel may be formed on a seed material coating <NUM> that comprises copper. The nickel may be deposited onto mask <NUM>' and portions of seed material coating <NUM> that are exposed through aperture <NUM>' by any suitable process, such as an electrolytic, electroless, or immersion plating process.

Thereafter, as depicted in <FIG>, mask <NUM>' may be removed by suitable processes. Continuing with the example of a photomask, any suitable mask-strip process may be employed. As mask <NUM>' (<FIG>) is removed from semiconductor device structure <NUM>', any portions of conductive layer <NUM>' that previously overlied mask <NUM>' are "lifted off" of semiconductor device structure <NUM>'.

If undesired portions of seed material coating <NUM>, or barrier layer <NUM> were not previously removed from exposed surfaces of semiconductor device structure <NUM>' (e.g., from non-upper bond pad <NUM>-bearing regions of active surface <NUM>), suitable processes may be used to remove one or more of these layers or coatings following the removal of mask <NUM>'. In addition to the aforementioned techniques for removing these layers or coatings, removal processes (e.g., use of wet or dry etchants in appropriate processes) with selectivity for the materials of the layers or coatings over the material of conductive layer <NUM>' may be employed.

Optionally, as depicted in <FIG>, if any of conductive layer <NUM>, seed material coating <NUM>, or barrier layer <NUM> extends onto upper bond pads <NUM> and the material of conductive layer <NUM>, seed material coating <NUM>, or barrier layer <NUM> forms an oxide which is not compatible with processes for subsequently securing conductive elements (e.g., bond wires, solder balls, leads, conductive elements of tape-automated bonding ("TAB") substrates, etc.) to upper bond pads <NUM>, an electrically conductive, oxidation resistant coating <NUM> may be formed on conductive layer <NUM>, seed material coating <NUM>, or barrier layer <NUM>. Oxidation resistant coating <NUM> may, for example, comprise aluminum, gold, platinum, or any other oxidation resistant material that is compatible with the material of conductive layer <NUM>. Oxidation resistant coating <NUM> may be formed by a selective (e.g., electroless or immersion plating) or non-selective (e.g., CVD, PVD, etc.) deposition process. If a non-selective deposition process is used, oxidation resistant coating <NUM> may be patterned by known processes (e.g., use of mask and etch processes, mask and lift-off processes, etc.).

With reference to <FIG>, if, following the formation of conductive layer <NUM>, <NUM>', a void <NUM> remains within via hole <NUM>, a filler material <NUM> may be introduced into void <NUM>. Filler material <NUM> may comprise a conductive material, such as the same type of material use to form conductive layer <NUM>, <NUM>' (e.g., a metal) or a material that is compatible with the material of conductive layer <NUM>, <NUM>' (e.g., another metal, a metal alloy, a conductive polymer, conductor-filled polymer, etc.), or a dielectric material (e.g., a polymer). Filler material <NUM> in a liquid state (e.g., molten metal, heated thermoplastic polymer, uncured polymer, etc.) may be introduced into void <NUM> by any suitable process. For example, a known "backfilling" process, in which filler material <NUM> is mechanically forced into void <NUM>, may be used. Alternatively, if a vent (not shown) has been formed between blind end <NUM> of via hole <NUM> and a back side <NUM> of substrate <NUM>, filler material <NUM> may be drawn into void <NUM> by capillary action or under a negative pressure (e.g., a vacuum), or forced into void <NUM> under positive pressure.

While a bump <NUM>' may be formed by a dielectric filler material <NUM>, as shown in <FIG>, such a bump <NUM>' may prevent a conductive structure from being secured to and establishing adequate electrical communication with upper bond pad <NUM>. Accordingly, as illustrated in <FIG>, dielectric bumps <NUM>' may be removed from over surfaces of upper bond pad <NUM> and, thus, dielectric filler material <NUM> may have an upper surface <NUM> that is flush, or substantially coplanar, with the surface <NUM> of each upper bond pad <NUM>.

Alternatively, as depicted in <FIG>, a conductive via <NUM> may be completed by filling void <NUM> with a conductive material. In the illustrated example, a conductive filler <NUM> (e.g., a solder, such as tin/lead (Pb/Sn) solder, a so-called "lead-free solder," such as a copper/tin/silver (Cu/Sn/Ag), tin/copper (Sn/Cu), tin/silver (Sn/Ag), or gold/tin (Au/Sn) alloy), or other suitable conductive material) may be introduced into void <NUM> to fill the same and, optionally, to form a bump <NUM> on upper bond pad <NUM>.

As yet another alternative, voids <NUM> may remain within the conductive via <NUM>, avoiding the stresses (e.g., mismatched coefficients of thermal expansion, mismatched electrical conductivities or resistivities, etc.) that may be caused by introducing dielectric or conductive material therein.

As illustrated in <FIG>, blind ends <NUM> (<FIG>) of via holes <NUM> and, thus, of conductive vias <NUM> may be exposed through back side <NUM> of substrate <NUM> by removing material from back side <NUM> of substrate <NUM>. Of course, any suitable technique may be used to expose blind ends <NUM>. For example, a so-called "back grinding" process may be used to remove material from a back side <NUM> of substrate <NUM> until the bottom portion <NUM> of conductive layer <NUM>, which is located at blind ends <NUM> (see <FIG>), is exposed, as illustrated, or until a partial or full cross section of the various layers of conductive via <NUM> is exposed. The exposed bottom portion <NUM> of conductive layer. <NUM> of each conductive via <NUM> forms a bottom bond pad <NUM> of semiconductor device structure <NUM>.

Back side <NUM> may be subsequently processed to passivate the same, to form larger bond pads at the bottom ends of conductive vias <NUM>, as well as to form conductive traces that extend laterally to other bond pad locations, and other features, as desired.

The following EXAMPLES describe various examples of processes that may be used to form various embodiments of conductive vias that extend into or through semiconductor device components.

With reference to <FIG>, an example of a process that may be used to form via holes <NUM> in a substrate <NUM> and insulate, or passivate, surfaces <NUM> thereof is described.

In <FIG>, a via hole <NUM> is formed in substrate <NUM>. While via hole <NUM> is depicted as extending only partially through substrate <NUM> and is, thus, known in the art as a "blind via hole," via hole <NUM> may alternatively extend completely through substrate <NUM>. Via hole <NUM> may be formed by any suitable process, including, without limitation, by use of a mask through which one or more etchants selectively remove material of substrate <NUM>, by laser ablation techniques, or otherwise, as known in the art.

While <FIG> depict the process of EXAMPLE <NUM> as being useful for forming conductive vias that extend through "blind" areas of substrate <NUM>, which do not include integrated circuitry or bond pads, these processes may also be used to form conductive vias that extend through bond pads that are located over either blind or active areas of substrate <NUM>.

As shown in <FIG>, a first adhesion layer <NUM> is formed on surface <NUM> of via hole <NUM> and on an active surface <NUM> of substrate <NUM>. Adhesion layer <NUM> may be formed by any suitable process, such as a deposition process (e.g., pulsed layer
deposition ("PLD") (which forms a PDL), CVD, atomic layer deposition ("ALD"), a process for forming an LSO, etc.), as a thermal oxide, by a low-temperature oxidation process, such as that disclosed in <CIT>.

Known processes are then used to deposit a layer <NUM> comprising low-K dielectric material, such as parylene, TEFLON®, or the like over first adhesion layer <NUM>, as depicted in <FIG>. Due to the low K of the material or materials from which dielectric layer <NUM> is formed, it may be relatively thin, facilitating the fabrication of via holes <NUM> with relatively large aspect ratios and, thus, increasing the potential density of conductive vias that may be included on substrate <NUM> per a given area over active surface <NUM> or back side <NUM> thereof.

As the material from which dielectric layer <NUM> is formed may not adhere well to many conductive materials, another, second adhesion layer <NUM>, formed from a material that will adhere to both the material of dielectric layer <NUM> and a subsequently deposited material, may be formed over dielectric layer <NUM>, as shown in <FIG>. Second adhesion layer <NUM> comprises an oxide material (e.g., a silicon oxide) and may be formed by known processes, such as suitable PLD or LSO techniques.

Next, as shown in <FIG>, a conductive layer, which may also be referred to as "seed material coating <NUM>" or as a "metal mask," is formed over second adhesion layer <NUM>. In this EXAMPLE <NUM>, seed material coating <NUM> is formed by depositing tungsten over second adhesion layer <NUM>. Tungsten is useful for facilitating the subsequent formation of nickel over surface <NUM> of via hole <NUM>.

Portions of seed material coating <NUM> that overlie active surface <NUM> of substrate <NUM> are removed, as illustrated in <FIG>. These portions may be removed by any suitable process, including the use of so-called "spacer etch" techniques, which will not remove significant portions of seed material coating <NUM> located within via hole <NUM>.

Thereafter, as depicted in <FIG>, exposed portions of second adhesion layer <NUM> (i.e., those overlying active surface <NUM> of substrate <NUM>) are removed. Again, any suitable removal processes may be used, such as a selective wet etch (i.e., the etchant has selectivity for the material of second adhesion layer <NUM> over seed material coating <NUM>). Thus, seed material coating <NUM> acts as a "metal mask" that prevents removal of portions of second adhesion layer <NUM> that overlie surface <NUM> of via hole <NUM> while exposed portions of second adhesion layer <NUM> are removed.

Portions of dielectric layer <NUM> that overlie active surface <NUM> of substrate <NUM> may also be removed. Again, any suitable process may be used to remove material of dielectric layer <NUM>. For example, when dielectric layer <NUM> is formed from parylene or TEFLON, a known, so-called "plasma strip," process may be employed.

Once desired portions of dielectric layer <NUM> have been removed, portions of first adhesion layer <NUM> that overlie active surface <NUM> of substrate <NUM> may be removed. Any suitable processes may be used to remove these portions of first adhesion layer <NUM>, including, but not limited to, the use of wet etchants, including wet etchants that will remove material of first adhesion layer <NUM> with selectivity over the material or materials that are present at active surface <NUM> of substrate <NUM>.

<FIG> illustrate another example of a process that may be used to form via holes <NUM> in a substrate <NUM> and insulate, or passivate, surfaces <NUM> of via holes <NUM>.

In <FIG>, a via hole <NUM> is formed in substrate <NUM>.

As shown in <FIG>, a first adhesion layer <NUM> is formed on surface <NUM> of via hole <NUM> and on an active surface <NUM> of substrate <NUM>. Portions of first adhesion layer <NUM> that overlie active surface <NUM> of substrate <NUM> are then immediately removed, as shown in <FIG>.

Next, as illustrated in <FIG>, a layer <NUM> comprising low-K dielectric material is deposited over remaining portions of first adhesion layer <NUM> and over active surface <NUM>. Thereafter, portions of dielectric layer <NUM> that overlie active surface <NUM> are removed, as depicted in <FIG>.

A second adhesion layer <NUM> is then formed, as shown in <FIG>. Portions of second adhesion layer <NUM> that overlie active surface <NUM> are subsequently removed, while portions of second adhesion layer <NUM> that are adjacent to dielectric layer <NUM> remain, as shown in <FIG>.

Thereafter, as shown in <FIG>, a conductive layer <NUM> and any underlying layers may be formed. Thereafter, any voids <NUM> remaining within via hole <NUM> may be filled, as described above in reference to <FIG>.

In another exemplary via hole formation and insulation technique, which does not form part of the claimed invention, but which builds upon the process flow described in EXAMPLES <NUM> and <NUM>, the first adhesion layer may be omitted and replaced with a process for roughening surface <NUM> of via hole <NUM>, as shown in <FIG>. Surface <NUM> may be roughened, for example, by the process or processes that are used to form via hole <NUM>. Alternatively, a separate etch process may be used to increase the roughness of surface <NUM>. The roughness of surface <NUM> enhances the direct adhesion of dielectric layer <NUM> or dielectric coating <NUM> to the material of substrate <NUM> at surface <NUM>, as shown in <FIG>.

<FIG> though <NUM> illustrate the formation of a via hole:<NUM> (<FIG>) through an upper bond pad <NUM> carried by substrate <NUM>. When mask and etch techniques are employed to form via hole <NUM>, a series of etch processes may be used. This is because the material of upper bond pad <NUM> differs from the material of underlying portions of a dielectric protective layer <NUM> and the material of substrate <NUM>, over which protective layer <NUM> lies, and different etchants may be needed to remove these materials.

In <FIG>, a mask <NUM> is formed over active surface <NUM> of substrate <NUM>. Any suitable masking process may be used, including the formation of a photomask over active surface <NUM>. An aperture <NUM> of mask <NUM> is positioned so as to facilitate material removal from a portion of upper bond pad <NUM>. Aperture <NUM> may be located so that material may be removed from the center of upper bond pad <NUM>, or so that material removal will be effected from a location that is offset from the center of upper bond pad <NUM>.

As shown in <FIG>, material of upper bond pad <NUM> is removed. The removal of material of upper bond pad <NUM> may be effected with a single etch or, if necessary to remove multiple conductive layers, a plurality of etches. The removal process may be either isotropic or anisotropic, either wet or dry.

Once a portion of protective layer <NUM> that underlies upper bond pad <NUM> is exposed through upper bond pad <NUM>, a material removal process that is suitable for removing the material of protective layer <NUM> is effected, as <FIG> illustrates. This protective layer <NUM>-removal process may be isotropic or anisotropic, wet or dry.

If necessary, another mask <NUM>", such as a photomask, may be formed over active surface <NUM> to prevent the removal of material of protective layer <NUM> during subsequent processing, as illustrated in <FIG>.

Portions of substrate <NUM> that are exposed through the opening <NUM>' in upper bond pad <NUM> and protective layer <NUM>, and through an aperture <NUM>" of mask <NUM>", may be exposed to an etchant to extend opening <NUM>' into substrate <NUM> and, thus, to form a via hole <NUM> therein. While the etchant may be an isotropic etchant or an anisotropic etchant, a wet etchant or a dry etchant, it is notable that the use of an anisotropic etchant may maximize the aspect ratio of the resulting via hole <NUM>.

Once via hole <NUM> has been formed, any resist remaining on substrate <NUM> may be removed therefrom, as known in the art (e.g., by use of suitable resist strip processing). The surface areas of surfaces <NUM> of each via hole <NUM> may be increased, as explained in EXAMPLE <NUM>, and a dielectric coating <NUM> (not shown in <FIG>) may be fabricated over surfaces <NUM> of each via hole <NUM>, as described in EXAMPLES <NUM> and <NUM>.

Alternatively, via hole <NUM> may be formed by other known processes (e.g., laser ablation).

EXAMPLES <NUM> through <NUM> describe various techniques and process flows for forming conductive layers within via holes <NUM>.

Referring now to <FIG>, an exemplary process for forming conductive vias that comprise copper conductive elements is described.

Once a via hole <NUM> has been formed, surfaces <NUM> thereof may be coated with one or more layers of dielectric material, as illustrated in <FIG>, to form a dielectric coating <NUM> over surfaces <NUM>. Processes such as those disclosed in EXAMPLES <NUM>-<NUM> may be used to coat surfaces <NUM> of via holes <NUM> with dielectric material, as may any other suitable techniques.

A copper barrier layer <NUM>" (e.g., Ta, TaN, Ti, TiN, etc.) (e.g., about <NUM>Å thick) may then be formed, as depicted in <FIG>. Copper barrier layer <NUM>" overlies dielectric coating <NUM> and prevents undesirable interdiffusion between a subsequently formed copper conductive element and the material or materials of dielectric coating <NUM> or substrate <NUM>. Examples of materials that may be used to form copper barrier layer <NUM>" include, without limitation, titanium nitride, tantalum nitride, tantalum, and the like. These and other materials that act as a barrier between copper and silicon-containing materials may be deposited by known processes (e.g., CVD).

Portions of copper barrier layer <NUM>" that overlie active surface <NUM> of substrate <NUM> are then removed. Known processes may be used to remove these portions of copper barrier layer <NUM>", including, but not limited to, spacer etch processes and mask and etch processes. Following removal, and depending at least in part upon the type of removal process employed, portions of copper barrier layer <NUM>" remain within via hole <NUM> and, optionally, over upper bond pad <NUM>.

In <FIG>, a seed material coating <NUM>" of copper (e.g., about <NUM>,<NUM>Å thick) is formed on upper bond pads <NUM>, over active surface <NUM> of substrate <NUM>, and on portions of copper barrier layer <NUM>" that remain within via holes <NUM>. The copper of seed material coating <NUM>" may be deposited by known processes, including CVD and PVD processes.

When blanket deposition processes are used to deposit the copper of seed material coating <NUM>", portions of seed material coating <NUM>" that overlie active surface <NUM> of substrate <NUM> are removed to prevent electrical shorting across active surface <NUM> (e.g., at locations between conductive vias or between a conductive via and a bond pad or other electrically conductive structure that is exposed to active surface <NUM>). These portions of seed material coating <NUM>" may be removed by any suitable process, including by known planarization or polishing processes (e.g., mechanical polishing, chemical-mechanical polishing, etc.), with a spacer etch, or otherwise, as known in the art.

Next, as shown in <FIG>, a conductive layer <NUM>" (e.g., about <NUM> thick), which comprises copper, is formed over remaining portions of seed material coating <NUM>". Conductive layer <NUM>" may be formed selectively on seed material coating <NUM>", without covering other regions of substrate <NUM> or features carried thereby. For example, known electroless plating, immersion plating, or electrolytic plating technologies, such as the chemistries available from Pac Tech, may be used to selectively deposit the copper of conductive layer <NUM>".

The process flow of EXAMPLE <NUM> may be modified somewhat, as shown in <FIG>. In <FIG>, barrier layer <NUM>‴ remains completely intact as a seed material coating <NUM>‴ is formed thereover. Once seed material coating <NUM>‴ is formed, regions of both seed material coating <NUM>‴ and barrier layer <NUM>‴ that are not located within via hole <NUM> or over upper bond pad <NUM> are removed, as shown in <FIG>. These portions of seed material coating <NUM>'" and barrier layer <NUM>‴ may be removed by any suitable process or processes, including, but not limited to, use of a polishing technique (e.g., CMP), a spacer etch, or the like.

Turning now to <FIG>, an exemplary embodiment for forming a nickel conductive element in a via hole <NUM> is described.

<FIG> shows a substrate <NUM> with an upper bond pad <NUM> carried by active surface <NUM> thereof. A nickel film <NUM>' is plated onto upper bond pad <NUM> by known techniques, such as electroless, immersion, or electrolytic plating techniques. A via hole <NUM> is then formed through upper bond pad <NUM> and in substrate <NUM>, by a suitable process, such as that described in EXAMPLES <NUM>-<NUM>.

Thereafter, as shown in <FIG>, a dielectric coating <NUM>"" is formed over surfaces <NUM> of via hole <NUM>, on nickel film <NUM>', and on active surface <NUM> of substrate <NUM>. In exampels not forming part of the claimed invention, dielectric coating <NUM>"" may include one layer (e.g., an oxide film formed by PLD or LSO) or more (e.g., a dielectric layer formed from a non-silicon-containing low-K material and one or more optional adhesion layers, as described in EXAMPLES <NUM> and <NUM>). Notably, dielectric coating <NUM>"" need not be etched or otherwise selectively removed prior to the subsequent deposition process. Optionally, a barrier layer <NUM> (not shown) may be formed over dielectric coating <NUM>"".

A seed material coating <NUM>"" is then formed over dielectric coating <NUM>"". Seed material coating <NUM>"", which may comprise copper, is formed on dielectric coating 28ʺʺ by known processes, such as by CVD or PVD techniques. A mask <NUM>"", such as a photomask, may then be formed over seed material coating <NUM>"". Mask <NUM>"" includes an aperture <NUM>"" positioned relative to each via hole <NUM> so as to facilitate the introduction of material into via hole <NUM>, but prevent the exposure of portions of seed material coating <NUM>"" that overlie remaining portions of upper bond pad <NUM> and active surface <NUM> to such material:.

As <FIG> illustrates, following the formation of mask <NUM>"", nickel is plated onto portions of seed material coating <NUM>"" that are exposed through each aperture <NUM>"" to form a conductive layer <NUM>"" (e.g., having a thickness of about <NUM> to. about <NUM>) thereover. Nickel plating may be effected by any suitable process, including, but not limited to, electroless plating techniques, immersion plating techniques, and electrolytic plating techniques. As illustrated, mask <NUM>"" limits the extent of conductive layer <NUM>"". Once conductive layer <NUM>"" has been formed, mask 40ʺʺ may be removed by techniques that are known in the art. Any nickel remaining on mask <NUM>"" is lifted off as mask <NUM>"" is removed.

Conductive layer <NUM>"" may then serve as a mask for the removal of exposed portions of seed material coating <NUM>"" and, once these portions of seed material coating <NUM>"" are removed, for the removal of the subsequently exposed portions of dielectric coating <NUM>"", as shown in <FIG>. Such removal may be effected by use of one or more etchants that remove the copper or other material of seed material coating <NUM>"" or the material or materials of dielectric coating <NUM>"" with selectivity over the nickel of conductive layer <NUM>"".

Another technique for forming a nickel conductive element of a conductive via is described with reference to <FIG>.

After a via hole <NUM> has been formed in active surface <NUM> of substrate <NUM> (e.g., through an upper bond pad <NUM> carried by active surface <NUM>, as depicted), and a dielectric coating <NUM> has been formed over surfaces <NUM> of via hole <NUM> (e.g., by the process described in EXAMPLES <NUM> and <NUM>), a base layer comprising an aluminum film <NUM>‴ʺ is formed over active surface <NUM>, upper bond pad <NUM>, and dielectric coating <NUM>, as shown in <FIG>. The use of aluminum is desirable because of its low electrical resistivity and the ease with which aluminum films may be formed and patterned. Aluminum film <NUM>‴ʺ may be formed by known processes, including, without limitation, use of CVD and PVD techniques. These processes may be used to uniformly and conformally coat aluminum over exposed regions of upper bond pad <NUM> and over surfaces <NUM> of relatively deep (i.e., high aspect ratio) via holes <NUM>.

When blanket deposition processes are used to form aluminum film <NUM>‴ʺ, portions of the film that are located over active surface <NUM> of substrate <NUM> (e.g., on protective layer <NUM>, as depicted), are removed, as <FIG> depicts. Such removal may be effected by suitable techniques; for example, with spacer etch or polishing processes.

With reference to <FIG>, remaining portions of aluminum film <NUM>‴ʺ may be coated with nickel. The nickel forms a conductive layer <NUM>‴ʺ over aluminum film <NUM>‴ʺ. While any suitable nickel-deposition process may be employed to form conductive layer <NUM>‴ʺ, if conductive layer <NUM>‴ʺ is formed by a selective deposition process, such as an electroless, immersion, or electrolytic plating process, the resulting conductive layer <NUM>‴ʺ will only coat exposed portions of seed material coating <NUM>‴ʺ and remaining portions of upper bond pad <NUM> and subsequent material removal processes will not be needed. In addition, when such processing is used, nickel may be applied to both upper bond pad <NUM> and over surface <NUM> of via hole <NUM> simultaneously, rather than separately.

As conductive layer <NUM>‴ʺ may extend over upper bond pad <NUM>, it is not necessary to plate upper bond pad <NUM> with nickel or any other conductive material prior to the formation of conductive layer <NUM>‴ʺ.

Conductive features (e.g., portions of seed material coating <NUM>‴ʺ, conductive layer <NUM>‴ʺ, conductive filler <NUM> (e.g., a solder, such as tin/lead (Pb/Sn) solder, a so-called "lead-free solder," such as a copper/tin/silver (Cu/Sn/Ag), tin/copper (Sn/Cu), tin/silver. (Sn/Ag), or gold/tin (Au/Sn) alloy), or other suitable conductive material), etc.) within each via hole <NUM> form a conductive via <NUM> through substrate <NUM>. When these features are exposed to a back side <NUM> of substrate <NUM>, they form a bottom bond pad <NUM> at back side <NUM> of substrate <NUM>, as illustrated by <FIG>.

When blind via holes <NUM> are formed and filled, blind end <NUM> of each via hole <NUM> may be exposed through a back side <NUM> of substrate <NUM> by any suitable process. For example, known back-grinding techniques or etching processes may be used to remove material from back side <NUM> and expose via hole <NUM> or structures therein to back side <NUM>.

With continued reference to <FIG>, a void <NUM> (<FIG>) that remains within a via hole <NUM> may be filled with conductive filler <NUM>, such as a molten metal or metal alloy (e.g., solder): Conductive filler <NUM> may be applied to a surface <NUM>, <NUM> of substrate <NUM> by any suitable process, (e.g., in a bath, in a wave solder apparatus, etc.), and permitted to fill voids <NUM>. Conductive filler <NUM> may, for example, be drawn into void <NUM> by capillary action. Alternatively, conductive filler <NUM> may be forced into, via holes <NUM> under negative pressure, positive pressure, or mechanical force.

As shown, a conductive bump <NUM> may remain on upper bond pad <NUM>. Alternatively, or in addition, a conductive bump could protrude relative to back side <NUM> of substrate <NUM>. If desired, conductive bump <NUM> may be removed by known processes (e.g., by suitable etching processes).

Alternatively, as shown in <FIG>, any void <NUM> (<FIG>) that remains within a via hole <NUM> may be filled with a plug of an electrically nonconductive, or dielectric, filler material <NUM>. By way of nonlimiting example, a liquid (e.g., molten, uncured, etc.) dielectric filler material <NUM> may be applied to active surface <NUM> of substrate <NUM> by any suitable technique (e.g., spin-on processes, spraying, etc.) and may be passively or actively (e.g., under pressure or force) introduced into void <NUM> to at least partially fill the same.

If necessary or desired, excess dielectric filler material <NUM> may be removed (e.g., with a suitable solvent or etchant) from one or both surfaces <NUM>, <NUM> of substrate <NUM>, as well as any features (e.g., upper bond pads <NUM>) thereon.

Turning now to <FIG>, electrical communication may be established with conductive vias <NUM> and, thus, with their corresponding upper bond pads <NUM> and circuitry (e.g., in the case where semiconductor device structure <NUM> is a semiconductor device, with integrated circuitry of the semiconductor device) that communicates with upper bond pads <NUM>, by securing external conductive elements <NUM> to bottom bond pads <NUM>. External conductive elements <NUM> may, by way of example only, comprise the illustrated balls or bumps of conductive material (e.g., metal, a metal alloy such as a solder, a conductive polymer, a conductor-filled polymer, etc.), conductive pins, pillars, or columns, or a so-called z-axis conductive film, which includes a dielectric film with conductive filaments extending only along the thickness, or z-axis, thereof.

External conductive elements <NUM> may be used to electrically connect semiconductor device structure <NUM> to another electronic component. For example, as shown in <FIG>, contacts (e.g., bottom bond pads <NUM>) of semiconductor device structure <NUM> may be aligned with corresponding contacts <NUM> of another semiconductor device component <NUM>, then the contacts (e.g., bottom bond pads <NUM>) and their corresponding contacts <NUM> secured to one another, in electrical communication, with external conductive elements <NUM>. The presence of separate contacts (e.g., upper bond pads <NUM>) on the opposite surface of semiconductor device structure <NUM> facilitates the disposition, or "stacking," of another electronic component, such as the depicted semiconductor device component <NUM>, over semiconductor device structure <NUM>, with contacts <NUM> of the upper semiconductor device component <NUM> being aligned with and secured in electrical communication (e.g., with conductive bump <NUM>) to corresponding contacts (e.g., upper bond pads <NUM>) of the middle semiconductor device structure <NUM>.

Other examples of assemblies in which semiconductor device structures <NUM> according to the present invention may be used are described in Farnworth, as are electronic devices within which semiconductor device structure <NUM> may be incorporated.

Claim 1:
A semiconductor device structure, comprising:
a substrate (<NUM>) comprising a full or partial wafer of semiconductor material;
at least one via hole (<NUM>) extending partially through the semiconductor material of the substrate (<NUM>);
a dielectric coating (<NUM>) on surfaces (<NUM>) of the at least one via hole (<NUM>); wherein:
the dielectric coating (<NUM>) includes a dielectric layer (<NUM>) comprising a low-K dielectric material having a dielectric constant of K≈<NUM>, an adhesion material (<NUM>) different from the dielectric material of the dielectric layer (<NUM>) between the dielectric layer (<NUM>) and the surfaces (<NUM>) of the at least one via hole (<NUM>), wherein the adhesion material (<NUM>) comprises an oxide, characterized in that:
the dielectric coating (<NUM>) includes another adhesion material (<NUM>) different from the dielectric layer (<NUM>) and coating the dielectric layer (<NUM>), wherein the another adhesion material comprises an oxide.