Patent Description:
Metal-oxide semiconductor field-effect transistors (MOSFETs) are valuable components in many high input impedance or high gain circuits, high speed switching circuits, or radio frequency (RF) integrated circuits (ICs) that are used, for example, in set top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, mobile phones, cellular phones, smart phones, tablets, phablets, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, and automobiles. The benefit of power MOSFETs include generally high switching speeds and a relatively low on-resistance.

Prior art document <CIT> discloses a thin film resistor structure formed on a metal gate structure.

Prior art document <CIT> discloses a high density area efficient thin-oxide decoupling capacitor using conductive gate resistor.

Prior art document <CIT> discloses a high resistance metal etch-stop layer positioned above the metal gate of a transistor.

Prior art document <CIT> discloses a shielding structure for use in a metal-oxide-semiconductor device.

Shielded gate MOSFETs are preferred because they provide reduced gate-to-drain capacitance, reduced on-resistance, and increased breakdown voltage of the transistor. By shielding the gate from the electric field in the drift region, the shielded gate MOSFET structure substantially reduces the gate-to-drain capacitance. The shielded gate MOSFET structure also provides the added benefit of higher minority carrier concentration in the drift region for the device's breakdown voltage and hence lower on-resistance.

A conventional way of shielding a gate MOSFET is to fabricate a Tungsten Silicide (WSi) Faraday shield between the gate and the underlying drain. Fabrication of the WSi Faraday shield, however, requires an additional polysilicon deposition, mask, and etch. These additional steps add costs, require additional specification, and may add defects to the IC. As such, there is a need for an apparatus and process for fabricating a shielded gate MOSFET in an IC that reduces costs and steps in process flow, and that still provides effective reduction of gate to drain parasitic capacitance.

A middle of line, MOL, shielded gate for an integrated circuit, IC, is disclosed as recited in claim <NUM>. A method of fabricating a shielded gate in a semiconductor die for an integrated circuit, IC, is disclosed as recited in claim <NUM>.

Aspects disclosed herein include middle-of-line (MOL) shield gates in integrated circuits (ICs). In this regard, in certain aspects disclosed herein, one or more metal resistors are fabricated in a MOL layer of an IC to shield the IC. The MOL layer is formed above and adjacent to an active semiconductor area in a front-end-of-line (FEOL) portion of the IC that includes devices, e.g., MOSFETS. The metal resistor(s) can be coupled through contacts formed in the MOL layer to interconnect lines in interconnect layer(s) so as to be coupled, for example, to a voltage source, on-chip RF, and/or power circuit in the IC.

Thus, by fabricating a metal resistor in the MOL layer in the IC, the metal resistor can advantageously be localized very close to semiconductor devices, such as transistors, to more accurately shield the semiconductor devices. Also, by providing the metal resistor in the MOL layer, the same fabrication processes used to create contacts in the MOL layer can also be used to fabricate the metal resistor in the MOL layer. Further, because the MOL layer is already provided in the IC to provide contacts between the semiconductor devices in the active semiconductor layer and the interconnect layers, additional area may not be required to provide the metal resistors in the IC.

With reference to the drawing figures, several exemplary aspects of the present disclosure are described.

<FIG> is a diagram illustrating a cross-sectional, side view of a semiconductor die <NUM> for an IC <NUM> that includes a MOL shielded gate <NUM>. MOL shielded gate <NUM> is provided on-chip in IC <NUM> in this example. MOL shielded gate <NUM> includes a metal resistor <NUM> that is fabricated from a metal material provided in a MOL layer <NUM> of a MOL area <NUM> of semiconductor die <NUM>. It should be noted that metal resistor <NUM> is present in current fabrication process and, as such, there is no additional etching, mask layering, or costs associated with fabricating metal resistor <NUM>. Metal resistor <NUM> is fabricated at MOL area <NUM> providing a shielded gate and effective reduction of gate to drain parasitic capacitance as further explained below. Metal resistor <NUM> has a resistance based on a material and sizing of metal resistor <NUM>. MOL layer <NUM> is formed above and adjacent to one or more active semiconductor layers <NUM> in a front-end-of-line (FEOL) area <NUM> of semiconductor die <NUM> disposed on a substrate <NUM>. Active semiconductor layers <NUM> include semiconductor devices, such as a MOSFET for example. In this example, the MOSFET is a FinFET <NUM> including a Fin <NUM> providing a conductive channel with a gate material <NUM> disposed above and/or adjacent to Fin <NUM>.

Because metal resistor <NUM> is disposed in MOL layer <NUM> immediately above and/or adjacent to active semiconductor layers <NUM> in this example, metal resistor <NUM> in MOL layer <NUM> can advantageously be localized very close to semiconductor devices in active semiconductor layers <NUM>, such as FinFET <NUM>, to more effectively reduce gate to drain parasitic capacitance.

To provide connectivity to MOL shielded gate <NUM> and direct voltage Vss to metal resistor <NUM>, a first contact <NUM>(<NUM>) is provided in MOL layer <NUM>. First contact <NUM>(<NUM>) is electrically coupled to a contact area <NUM> of metal resistor <NUM>. For example, first contact <NUM>(<NUM>) may be conductive contact pad made out of a Tungsten (W) material. In this example, first contact <NUM>(<NUM>) physically contacts contact area <NUM>. First and second vertical interconnect accesses ViasO (VOs) <NUM>(<NUM>), <NUM>(<NUM>) are fabricated in an interconnect layer <NUM> in an interconnect area <NUM> of semiconductor die <NUM> in aligned contact with first and second contacts <NUM>(<NUM>), <NUM>(<NUM>). For example, interconnect layer <NUM> is shown as a metal <NUM> (M1) layer directly above MOL layer <NUM>. First and second interconnects <NUM>(<NUM>), <NUM>(<NUM>) are formed in interconnect layer <NUM> above and in contact with first and second VOs <NUM>(<NUM>), <NUM>(<NUM>). For example, first and second interconnects <NUM>(<NUM>), <NUM>(<NUM>) may be metal lines <NUM>(<NUM>), <NUM>(<NUM>) that were fabricated from a conductive material disposed in trenches formed in a dielectric material <NUM>. In this manner, connectivity to MOL shielded gate <NUM> is provided through metal lines <NUM>(<NUM>), <NUM>(<NUM>) in this example.

Thus, by fabricating metal resistor <NUM> in MOL layer <NUM> in IC <NUM>, metal resistor <NUM> can advantageously be localized and very close to semiconductor devices in active semiconductor layers <NUM>, to effectively reduce gate to drain parasitic capacitance. The MOL layer <NUM> has a thickness T of approximately eighteen (<NUM>) nanometers (nm) or less, which is a thickness ratio of approximately <NUM> or less to the thickness of semiconductor layers <NUM>. Further, because MOL layer <NUM> is already provided in IC <NUM> to provide contacts between semiconductor devices in the semiconductor layers <NUM> and interconnect layer <NUM> including, e.g., first and second semiconductor layer contacts <NUM>(<NUM>), <NUM>(<NUM>), additional area may not be required to provide metal resistor <NUM> in IC <NUM>. For example, metal resistor <NUM> may have approximately a width/length (W/L) of <NUM> / <NUM>.

Metal resistor <NUM> can be formed from any conductive material. As examples, metal resistor <NUM> can be formed from Tungsten Silicide (WSi), Titanium Nitride (TiN), and Tungsten (W). Metal resistor <NUM> should have a sufficient resistance to be sensitive to changes in ambient temperature. For example, the resistance of metal resistor <NUM> may be at least <NUM> ohms per W/L µm of semiconductor devices. Also, by disposing metal resistor <NUM> in MOL layer <NUM>, it may be efficient from a fabrication process standpoint to form metal resistor <NUM> from the same material as a work function material <NUM> disposed adjacent to gate (G) <NUM> of FinFET <NUM>.

<FIG> is a flowchart illustrating an exemplary process <NUM> of fabricating a MOL shielded gate in an IC, such as MOL shielded gate <NUM> in IC <NUM> in <FIG>. <FIG> are exemplary process stages <NUM>(<NUM>)-<NUM>(<NUM>) of fabricating a MOL metal resistor shielded gate in an IC, such as MOL shielded gate <NUM> comprising metal resistor <NUM> in IC <NUM> in <FIG>. The exemplary process <NUM> in <FIG> and the exemplary process stages <NUM>(<NUM>)-<NUM>(<NUM>) to fabricate a MOL <NUM> in <FIG> will now be described.

As illustrated in processing stage <NUM>(<NUM>) in <FIG>, a first step of fabricating a MOL shielded gate <NUM> in an IC <NUM> is to form a substrate <NUM> (block <NUM> in <FIG>). An active semiconductor layer <NUM> is formed above substrate <NUM> as shown in <FIG> (block <NUM> in <FIG>). Further, as shown in <FIG>, at least one semiconductor device <NUM> is formed in active semiconductor layer <NUM> (block <NUM> in <FIG>). In this example, PFETs <NUM>(<NUM>) and a NFETs <NUM>(<NUM>) are formed in active semiconductor layer <NUM>. As shown, sources (S), drains (D), and gates (G) are formed for PFETs <NUM>(<NUM>) and NFETs <NUM>(<NUM>).

Next, a MOL layer <NUM> is formed above active semiconductor layer <NUM> (block <NUM> in <FIG>). In this example, middle MOL layer <NUM> is comprised of a first insulating layer <NUM> followed by a metal material layer <NUM>, with another second insulating layer <NUM> disposed on metal material layer <NUM>. First and second insulating layers <NUM> and <NUM> in this example are oxide layers. Metal material layer <NUM> may be formed of any conductive material that will provide a desired resistance, such as tungsten. As previously discussed, metal material layer <NUM> may be formed from the same work function material used to create one or more gates (G) in active semiconductor layer <NUM>. First insulating layer <NUM> is configured to insulate the MOL layer <NUM> from the active semiconductor layer <NUM> and semiconductor devices fabricated in the active semiconductor layer <NUM>. Metal material layer <NUM> will be processed to form a metal resistor as will be discussed in more detail below.

Next, as shown in a second process stage <NUM>(<NUM>) in <FIG>, to prepare the metal resistor to be formed in MOL layer <NUM>, a photoresist layer <NUM> is disposed on top of MOL layer <NUM>, and more particularly second insulating layer <NUM>. Next, as shown in a third process stage <NUM>(<NUM>) in <FIG>, a hard mask <NUM> is disposed on photoresist layer <NUM> to prepare for the formation of metal resistor from metal material layer <NUM>. Hard mask <NUM> is sized based on a desired size of the metal resistor. Hard mask <NUM> may be placed so that the metal resistor is formed from metal material layer <NUM> above and/or adjacent to a semiconductor device in active semiconductor layer <NUM> to effectively reduce gate to drain parasitic capacitance. The IC <NUM> is then processed by exposure to light. As shown in the process stage <NUM>(<NUM>) in <FIG>, photoresist layer <NUM>, second insulating layer <NUM>, and metal material layer <NUM> are removed except under the area where hard mask <NUM> was disposed in process stage <NUM>(<NUM>) in <FIG>. After the exposure of photoresist layer <NUM>, second insulating layer <NUM> and metal material layer <NUM> that are not underneath hard mask <NUM> are removed. The remaining metal material layer <NUM> forming a metal resistor <NUM> that has a contact area <NUM>(<NUM>) and <NUM>(<NUM>) for providing electrical contact to metal resistor as part of MOL shielded gate <NUM>. For example, second insulating layer <NUM> may be removed by a chemical etch process or other removal process. Metal material layer <NUM> may be removed by a different chemical etch process or other removal process.

Next, as shown in process stage <NUM>(<NUM>) in <FIG>, another insulating layer <NUM>, which may be an oxide layer, is disposed over the remaining first insulating layer <NUM>, metal resistor <NUM>, and second insulating layer <NUM> to prepare contacts to be formed in MOL layer <NUM>. In subsequent processing steps, to continue with fabrication of MOL shielded gate <NUM>, a first contact is formed with metal resistor <NUM> in MOL layer <NUM> and is in contact with first contact area <NUM> (block <NUM> in <FIG>). At least one interconnect layer is formed above MOL layer <NUM> (block <NUM> in <FIG>). A first interconnect is formed in the at least one interconnect layer electrically coupled to the first contact, to electrically couple first interconnect to first contact area <NUM> of metal resistor (block <NUM> in <FIG>). Vias may be formed in interconnect layer above MOL layer <NUM> to electrically couple contacts in MOL layer <NUM> and in active semiconductor layer <NUM>.

MOL shielded gates in integrated circuits (ICs), and according to any of the examples disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include set top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, mobile phones, cellular phones, smart phones, tablets, phablets, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, and automobiles.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that includes a CPU <NUM> that includes one or more processors <NUM>. The processor-based system <NUM> may be provided as a system-on-a-chip (SoC) <NUM>. The CPU <NUM> may have a cache memory <NUM> coupled to the processor(s) <NUM> for rapid access to temporarily stored data. The CPU <NUM> may include the MOL shielded gate <NUM>. The CPU <NUM> is coupled to a system bus <NUM> and can be coupled to other devices included in the processor-based system <NUM>. The processor(s) <NUM> in the CPU <NUM> can communicate with these other devices by exchanging address, control, and data information over the system bus <NUM>. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric. For example, the CPU <NUM> can communicate bus transaction requests to a memory in a memory system <NUM> as an example of a slave device.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired.

The CPU <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>.

<FIG> illustrates an example of a wireless communications device <NUM> which can include RF components in which a MOL shielded gate <NUM> is used in an integrated circuit (IC) <NUM> to reduce gate to drain parasitic capacitance. In this regard, the wireless communications device <NUM> is provided in IC <NUM>. The wireless communications device <NUM> may include or be provided in any of the above referenced devices such as a smart phone. As shown in <FIG>, the wireless communications device <NUM> includes a transceiver <NUM> and a data processor <NUM>. The IC <NUM> and/or the data processor <NUM> includes the MOL shielded gate <NUM> to reduce gate to drain parasitic capacitance. The data processor <NUM> may include a memory (not shown) to store data and program codes. The transceiver <NUM> includes a transmitter <NUM> and a receiver <NUM> that support bi-directional communication. In general, the wireless communications device <NUM> may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver <NUM> may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc..

A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device <NUM> in <FIG>, the transmitter <NUM> and the receiver <NUM> are implemented with the direct-conversion architecture.

In the transmit path, the data processor <NUM> processes data to be transmitted and provides I and Q analog output signals to the transmitter <NUM>. In the exemplary wireless communications device <NUM>, the data processor <NUM> includes digital-to-analog-converters (DACs) <NUM>(<NUM>) and <NUM>(<NUM>) for converting digital signals generated by the data processor <NUM> into the I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within the transmitter <NUM>, lowpass filters <NUM>(<NUM>), <NUM>(<NUM>) filter the I and Q analog output signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (AMP) <NUM>(<NUM>), <NUM>(<NUM>) amplify the signals from the lowpass filters <NUM>(<NUM>), <NUM>(<NUM>), respectively, and provide I and Q baseband signals. An upconverter <NUM> upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers <NUM>(<NUM>), <NUM>(<NUM>) from a TX LO signal generator <NUM> to provide an upconverted signal <NUM>. A filter <NUM> filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) <NUM> amplifies the upconverted signal from the filter <NUM> to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch <NUM> and transmitted via an antenna <NUM>.

In the receive path, the antenna <NUM> receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch <NUM> and provided to a low noise amplifier (LNA) <NUM>. The duplexer or switch <NUM> is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA <NUM> and filtered by a filter <NUM> to obtain a desired RF input signal. Downconversion mixers <NUM>(<NUM>), <NUM>(<NUM>) mix the output of the filter <NUM> with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator <NUM> to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMP) <NUM>(<NUM>), <NUM>(<NUM>) and further filtered by lowpass filters <NUM>(<NUM>), <NUM>(<NUM>) to obtain I and Q analog input signals, which are provided to the data processor <NUM>. In this example, the data processor <NUM> includes analog-to-digital-converters (ADCs) <NUM>(<NUM>), <NUM>(<NUM>) for converting the analog input signals into digital signals to be further processed by the data processor <NUM>.

In the wireless communications device <NUM> in <FIG>, the TX LO signal generator <NUM> generates the I and Q TX LO signals used for frequency upconversion, while the RX LO signal generator <NUM> generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A transmit (TX) phase-locked loop (PLL) circuit <NUM> receives timing information from the data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator <NUM>. Similarly, a receive (RX) phase-locked loop (PLL) circuit <NUM> receives timing information from the data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator <NUM>.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality.

Claim 1:
A middle-of-line, MOL, shielded gate (<NUM>) for an integrated circuit, IC, (<NUM>) comprising:
an active semiconductor layer (<NUM>) comprising a first semiconductor device (<NUM>);
a metal resistor (<NUM>) comprising a metal material disposed in an MOL layer (<NUM>), the MOL layer disposed above the active semiconductor layer;
wherein the first semiconductor device comprises a transistor comprising a source (S), a drain (D), and a gate (<NUM>) interdisposed between the source and the drain;
wherein the metal resistor is disposed over the gate of the transistor such that gate to drain parasitic capacitance in the transistor is reduced; and
wherein the MOL layer (<NUM>) has a thickness of approximately eighteen, <NUM>, nanometers, nm, or less and wherein a ratio of the thickness of the MOL layer to a thickness of the active semiconductor layer (<NUM>) is approximately <NUM> or less.