Patent Description:
One popular substrate configuration for semiconductor power modules is a so-called DCB (direct bonded copper) substrate. A DCB substrate includes a number of electrically isolated bond pads formed in a metallization layer of conductive material, such as copper. This metallization layer is bonded to a substrate of insulating material, such as ceramic.

Document <CIT> discloses a circuit device having conductive patterns which are equally spaced apart. A method for manufacturing the circuit device includes the steps of: preparing a conductive foil; forming conductive patterns, which are included in a unit having at least regions for mounting circuit elements, by forming isolation trenches having a uniform width in the conductive foil; electrically connecting the conductive patterns to the circuit elements; sealing with a sealing resin so as to cover the circuit elements and to be filled in the isolation trenches; and removing the conductive foil in its thickness portions where no isolation trenches are provided.

Document <CIT> discloses a method of providing a contact mechanism. The method comprising encapsulating a circuit formed on an electrical substrate (the circuit including one or more connector blocks) and machining a hole into the connector blocks through the encapsulating material (e.g., by drilling) such that external connections can be made to each of said connector blocks through the encapsulating material.

Document <CIT> discloses a semiconductor element fixed onto a tab for a lead frame by a cementing material. The element and leads are bonded by bonding wires. The tip section of outer lead pins are inserted into the holes of the lead pins are inserted into the holes of the lead frames, and molded with a resin to seal the semiconductor element, one parts of the lead frame and one parts of the outer lead pins with the resin, thus forming a resin sealing body.

Document <CIT> discloses a semiconductor pellet mounted on a die pad via conductive adhesive layer. Each of inner leads is connected to the inner terminal formed on the surface of the semiconductor pellet via bonding wires. The resin mold layer that seals the assembled die pads, semiconductor pellet, inner leads, and bonding wires is formed. This layer is provided with pin holes penetrating through the top surface to the back, and the pin holes penetrate also through the inner lead parts. Lead pins are each fitted in the pin holes by being driven from the top surface side of the resin mold layer, and the lead pins projected out of the back of the layer are arranged in PAG type. Document <CIT> discloses an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through the thickness of the encapsulation material.

The cost of producing semiconductor power modules with DCB substrates is driven by several factors. These factors include material costs (e.g., ceramic for the insulating layer, copper for the metallization layer, adhesive, etc.) and the time and expense associated with performing each processing step involved in the formation of the substrate, e.g., forming and bonding the layer of conductive metal to the insulating substrate, riveting press-fit connectors to the layer of conductive metal, etc..

It would be desirable to produce a semiconductor power module at lower cost with similar or better performance characteristics than conventional solutions.

According to an embodiment of a method of forming a power semiconductor module, the method comprises providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.

Forming the hole in the molded body and the recess in the upper surface comprises performing a single process step that completely penetrates the molded body and subsequently partially penetrates the substrate.

Separately or in combination, the single process step comprises mechanical or laser drilling.

Separately or in combination, forming the mechanical and electrical connection comprises welding the interior end of the press-fit connector to the substrate.

Separately or in combination, the method further comprises forming a spring contact attachment feature from the substrate, the spring contact attachment feature comprising a tab of the planar sheet metal and a perforation in the tab that completely extends through the thickness of the substrate, wherein the tab and the perforation protrude from the molded body of encapsulant after forming the molded body.

Separately or in combination, forming the channels comprises forming one of the channels as an outer peripheral ring that separates each one of the islands from peripheral edges of the substrate.

Separately or in combination, after forming the channels each one of the islands remain connected to one another by portions of the substrate that are directly beneath the channels, and the method further comprises removing the portions of the substrate after forming the molded body such that each one of the islands are electrically isolated from one another.

Separately or in combination, forming the channels comprises half-etching the upper surface of the substrate such that the portions of the substrate directly underneath the channels are thinner than the islands, and removing the portions of the substrate comprises selectively etching the lower surface of the substrate.

Separately or in combination, forming the channels comprises stamping the upper surface of the substrate such that the portions of the substrate directly underneath the channels are vertically offset from the islands, and removing the portions of the substrate comprises selectively etching the lower surface of the substrate.

Separately or in combination, forming the channels comprises stamping the upper surface of the substrate such that the portions of the substrate directly underneath the channels are vertically offset from the islands, and removing the sections of the substrate comprises planarizing the lower surface of the substrate.

Separately or in combination, the recess is formed in a second one of the islands, and the method further comprises mounting a second semiconductor die on a second one of the islands, forming a plurality of the holes in the molded body and a plurality of the recesses in the upper surface of the substrate beneath each of the respective holes, providing a plurality of the press-fit connectors, and arranging one of the press-fit connectors in each one of the holes and forming a mechanical and electrical connection between an interior end of each of the press-fit connectors and the substrate, the first and second semiconductor dies are configured as power transistors, and the press-fit connectors are configured as externally accessible points of electrical contact to each terminal of the first and second semiconductor dies.

According to an embodiment of a power semiconductor module, the power semiconductor module comprises a substrate of planar sheet metal comprising a plurality of islands that are each defined by channels that extend between upper and lower surfaces of the substrate, a first semiconductor die mounted on a first one of the islands, a molded body of encapsulant that covers the metal substrate, fills the channels, and encapsulates the first semiconductor die, a hole in the molded body that extends to a recess in the upper surface of the substrate, and a press-fit connector arranged in the hole such an interior end of the press-fit connector is mechanically and electrically connected to the substrate.

Separately or in combination, the power semiconductor module the interior end of the press-fit connector is welded to the substrate.

Separately or in combination, the interior end of the press-fit connector is secured within the recess by mechanical pressure.

Separately or in combination, the power semiconductor module further comprises a spring contact attachment feature formed in the substrate, the spring contact attachment feature comprising a tab of the planar sheet metal and a perforation in the tab that completely extends through the tab, and the tab and the perforation are exposed from the molded body.

Separately or in combination, one of the channels is arranged as an outer peripheral ring that separates each one of the islands from peripheral edges of the substrate.

Separately or in combination, the lower surface of the substrate is exposed at a lower surface of the molded body, and the power semiconductor module further comprises a layer of electrically insulating material that covers the lower surface of the substrate.

Separately or in combination, the recess is formed in a second one of the islands, wherein the first semiconductor die comprises a terminal which faces away from the upper surface of the substrate and is electrically connected to the second island by an electrical connector, and wherein the press-fit connector is configured as an externally accessible point of electrical contact to the terminal of the semiconductor die.

Separately or in combination, the power semiconductor module further comprises a second semiconductor die mounted on a second one of the islands, a plurality of the holes in the molded body and a plurality of the recesses in the upper surface of the substrate beneath each of the respective holes, a plurality of the press-fit connectors, one of the press-fit connectors is arranged in each one of the holes and forms a mechanical and electrical connection between an interior end of the respective press-fit connector and the substrate, the first and second semiconductor dies are configured as power transistors, and the press-fit connectors are configured as externally accessible points of electrical contact to each terminal of the first and second semiconductor dies.

The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.

A semiconductor power module construction and corresponding method for forming the semiconductor power module are described herein, according to various embodiments. Advantageously, the semiconductor power module can be produced with relatively few processing steps and with less expensive materials in comparison to other power semiconductor module constructions. For example, processing steps such as frame construction, press-fit soldering, and gel dispensing that are required in DCB based solutions are replaced with more cost-effective alternatives. The techniques utilized herein utilize a metal substrate the basic building block of the power semiconductor module. The metal substrate can be a planar sheet metal such as a panel or strip of copper that is commonly used to form lead frames or printed circuit boards. Each of the features of the power semiconductor module, e.g., isolated bond pads, press-fit connections, insulating materials, etc., can be formed using batch processing tools that can perform these steps to a panel or strip with multiple units being processed simultaneously. These processing steps are highly developed, well-suited for high volume parallelization, and utilize inexpensive materials that are widely available in the semiconductor industry.

Referring to <FIG>, a substrate <NUM> of planar sheet metal is provided. The substrate <NUM> can be a relatively uniform thickness piece of conductive metal with a generally planar upper surface <NUM> and a generally planar lower surface <NUM> that is opposite from the upper surface <NUM>. The substrate <NUM> may be formed from one or more conductive metals such as Cu, Ni and/or Ag, for example. Additionally, the substrate <NUM> may include or be plated with Cu, Ni, Ag, Au, Pd, Pt, NiV, NiP, NiNiP, NiP/Pd, Ni/Au, NiP/Pd/Au, or NiP/Pd/AuAg, for example. Generally speaking, the substrate <NUM> can have a thickness as measured between the upper and lower surfaces <NUM>, <NUM> in the range of <NUM> thick and <NUM> thick. In certain embodiments, the thickness of the substrate <NUM> is in the range of <NUM> thick and <NUM> thick.

Any type of metal substrate to which a semiconductor die is typically joined may be used for the metal substrate <NUM>. For example, the substrate <NUM> can be a commercially available strip of metal used to form a leadframe or metal clip for semiconductor packages. In other embodiment, the substrate <NUM> is a large (e.g., <NUM> x <NUM>) panel of metal used to form a printed circuit board. While the figures depict the steps used to form one power semiconductor module, it is to be understood that the techniques described herein can be performed in parallel to form multiple identical ones of the power semiconductor modules simultaneously. In particular, a large metal strip or panel can be used to provide multiple ones of the substrates <NUM> as shown in <FIG>, and each processing step described hereafter can be performed in parallel to each unit.

Referring to <FIG>, the substrate <NUM> is processed to form channels <NUM> in the upper surface <NUM> of the planar sheet metal. The channels <NUM> partially extend through a thickness of the substrate <NUM> so that portions <NUM> of the substrate <NUM> remain between bottoms the channels <NUM> and the lower surface <NUM> of the substrate <NUM>. The channels <NUM> are formed to define a plurality of islands <NUM> in the substrate <NUM>. This means that from a plan-view perspective of the upper surface <NUM> of the substrate <NUM> the channels <NUM> form enclosed shapes (e.g., circular, rectangular, etc.) with the islands <NUM> corresponding to the portions of the substrate <NUM> that are completely surrounded by the enclosed shapes.

Additionally, the substrate <NUM> is processed to form spring contact attachment features <NUM>. The spring contact attachment feature <NUM> is used to affix the completed power semiconductor module to an external apparatus, such as a heat sink. The spring contact attachment feature <NUM> includes a tab <NUM> portion of the planar sheet metal that protrudes away from a main body section of the substrate <NUM> that includes the channels <NUM> and corresponding islands <NUM> enclosed by the channels <NUM>. Additionally, the spring contact attachment feature <NUM> includes a perforation <NUM> in the tab <NUM> that completely extend through the thickness of the planar sheet metal. The perforation <NUM> is used to accommodate a fastener (e.g., a spring contact) to mount the power semiconductor module to an external apparatus.

The substrate <NUM> depicted in <FIG> can be formed using a half-etch technique. In one example of this technique, two masks are provided on both the upper and lower surfaces <NUM>, <NUM> of the substrate <NUM>. The mask disposed on the upper side <NUM> of the substrate <NUM> is patterned, e.g., using photolithography techniques, to have the desired geometry of the half-etched features (e.g., the channels <NUM>) and (if desired) the fully-etched features (e.g., the tab <NUM> and the perforation <NUM>). The mask disposed on the lower side <NUM> of the substrate <NUM> is patterned asymmetrically such that regions directly underneath the half-etched features are covered and the regions directly underneath the fully-etched features are exposed. The etching is controlled, e.g., through appropriate use of mask geometry, time, etchant chemical, etc., so that the etchant removes about one half of the thickness of the substrate <NUM> from either side. As a result, depth of the channels <NUM> is about one half of the thickness of the substrate <NUM>, with remaining portions <NUM> of the substrate <NUM> underneath the channels <NUM> having about one half of the thickness of the substrate <NUM>. Meanwhile, the etchant removes the complete thickness of the substrate <NUM> to form the tabs <NUM> and the perforations <NUM>.

Referring to <FIG>, another technique for processing the planar sheet metal to form the channels <NUM> and the spring contact attachment feature <NUM> is depicted. In the embodiment of <FIG>, the channels <NUM> are formed by stamping the upper surface <NUM> of the planar sheet metal, e.g., by a metal punching or coining technique. These techniques can form the channels <NUM> to have the same enclosed geometry, thereby forming a plurality of the enclosed islands <NUM> in an identical manner. Different to the previously described half-etch technique, the portions <NUM> of the substrate <NUM> underneath the channels <NUM> are not half-thickness regions. Instead, these portions <NUM> have about the same thickness as the original thickness of the planar sheet metal and are vertically offset from the non-stamped regions. As a result, the lower surface <NUM> of the substrate <NUM> is undulated. The spring contact attachment feature <NUM> including the tab <NUM> and the perforation <NUM> can be formed concurrently with the channels <NUM>, e.g., by performing a complete punch of the metal. Alternatively, the spring contact attachment feature <NUM> can be formed by a separate cutting process that is performed before or after the stamping process which forms the channels <NUM>.

Referring to <FIG>, a plurality of semiconductor dies <NUM> is mounted on the substrate <NUM>. In the depicted embodiment of <FIG>, the substrate <NUM> is a half-etched substrate <NUM> that was formed according to the technique described with reference to <FIG>. Alternatively, the substrate <NUM> can be a stamped substrate <NUM> formed according to the technique described with reference to <FIG>. With the exception of <FIG> which describes specific techniques for processing each kind of substrate <NUM>, it is to be understood that each of the processing steps described hereafter are equally applicable to either kind of substrate <NUM>.

In an embodiment, the semiconductor dies <NUM> are mounted by a soldering technique which forms an electrically conductive solder joint between a metal surface (e.g., a bond pad) of each semiconductor die <NUM> and the substrate <NUM>. For example, a soft solder paste, e.g., a tin based lead-free solder paste comprising Sn/Ag, Sn/Ag/Cu, Sn/Cu, etc., can be provided between the metal surface of the semiconductor die and the upper surface <NUM> of the substrate <NUM> and subsequently reflowed to form a typical solder bond. In another example, the semiconductor dies <NUM> can be soldered by a diffusion process wherein the solder joint includes a high number of intermetallic phases with a higher melting point than the joined elements. This diffusion process can be performed providing a very thin (e.g., less than <NUM> thick) layer of solder (e.g., printed or preformed solder) between the metal surface of the semiconductor die and the upper surface <NUM> of the substrate <NUM> and subsequently reflowing the solder.

In an embodiment, the semiconductor dies <NUM> are configured as power devices that are designed to withstand very high voltages, e.g., 600V (volts), <NUM>,200V, and/or substantially large currents, e.g., currents on the order of 1A (amperes), 2A, etc. Examples of these devices include power transistor dies, e.g., power MOSFETs, (metal-oxide semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), HEMTS (high electron mobility transistors), etc. More generally, the semiconductor dies <NUM> can be configured as a logic dies such as a gate-drivers, microcontrollers, memory devices, etc., or passive dies such as inductors, capacitors, etc. The semiconductor dies <NUM> may have a lateral device configuration with each conductive terminal being disposed on an upper side of the die that faces away from the substrate <NUM>. In that case, there is no electrical connection between the rear side of the semiconductor die <NUM> and the substrate <NUM>, and the islands <NUM> may serve a non-electrical purpose, e.g., heat dissipation. Alternatively, the semiconductor dies <NUM> may have a vertical device configuration wherein the rear side of the semiconductor die <NUM> includes a conductive bond pad that is electrically connected to the upper surface <NUM> of the substrate <NUM>, e.g., by a solder connection. In that case, the islands <NUM> can be configured as electrical terminals, e.g., drain, source, etc..

In the depicted embodiment of <FIG>, pairs of different semiconductor dies <NUM> are mounted adjacent to one another on a single one of the islands <NUM>, These pairs of different semiconductor dies <NUM> may include a power transistor and a corresponding gate driver used to control each gate transistor, for example. Three of these pairs are mounted on one common island <NUM>, and three of these pairs are mounted separate islands <NUM>. This arrangement can be used for a half-bridge circuit, wherein the common island <NUM> that accommodates three pairs is configured as a common reference potential terminal, e.g., GND for each low-side switch, and the separate islands <NUM> that accommodate single pairs of the different semiconductor dies <NUM> are configured as high-voltage terminals, e.g., VDS, for each high-side switch. This arrangement represents just one example of a variety of configurations wherein the geometry of the channels <NUM> is selected to provide a dedicated bond pad and terminal for the devices mounted thereon.

After mounting the semiconductor dies <NUM> on the substrate <NUM>, an electrical interconnect step is performed to form electrical connections <NUM>. The electrical connections <NUM> can form electrical interconnections between terminals of the semiconductor die which face away from the upper surface <NUM> of the substrate <NUM> and other islands <NUM> that do not include any semiconductor dies <NUM> mounted thereon and/or terminals of different semiconductor dies <NUM>. For example, the electrical connections <NUM> may include an electrical connection between the source terminal of a power transistor and a separate island <NUM> that does not accommodate any semiconductor die <NUM>. In another example, the electrical connections <NUM> may include an electrical connection between the gate terminals of a driver die and a separate island <NUM> that does not accommodate any semiconductor die <NUM>. More generally, the separate islands <NUM> can be configured to provide pan-out redistribution for the different terminals of each semiconductor die <NUM>. These electrical connections <NUM> may be formed using bond wires (as shown), metal clips, ribbons, etc. <FIG> depicts only some of the necessary electrical connections <NUM> for a power module being effectuated using conductive bond wires.

Referring to <FIG>, an encapsulation process is performed on the assembly. The encapsulation process forms a molded body <NUM> of electrically insulating encapsulant material that covers the substrate <NUM>, fills each of the channels <NUM>, and encapsulates the semiconductor dies <NUM>. Thus, the molded body <NUM> forms an insulative and protective structure that protects each semiconductor die <NUM> and the associated electrical connections <NUM>. The molded body <NUM> can include a wide variety of electrically insulating encapsulant materials including ceramics, epoxy materials and thermosetting plastics, to name a few. In an embodiment, the molded body <NUM> is formed by placing the assembly in a three-dimensional chamber and injecting liquified encapsulant material into the chamber. Examples of these techniques include injection molding, transfer molding, and compression molding. In another embodiment, the molded body <NUM> is formed by a lamination technique.

The channels <NUM> may be formed to include a ring-shaped channel <NUM> (shown in <FIG>) that surrounds each one of the islands <NUM> and separates each one of the islands <NUM> from peripheral edges of the substrate <NUM>. This ring-shaped channel <NUM> advantageously serves to enhance adhesion of the encapsulant material during the encapsulation process by providing additional interlocking surfaces between the encapsulant material and the substrate <NUM>. More generally, this concept can be utilized to form extraneous channels <NUM> or other features that increase the available surface area of the substrate <NUM> that interact with of the encapsulant material.

The encapsulation process is performed such that the tab <NUM> of the planar sheet metal and the perforation <NUM> in the tab <NUM> which form the spring contact attachment feature <NUM> protrude from the molded body <NUM>. Thus, these features are accessible for attachment in the completed module. Optionally, the tab <NUM> can be coated with molding compound in the same encapsulation step or in a further step. Moreover, as shown in the rear-side view of <FIG>, the lower surface <NUM> of the substrate <NUM> remains exposed from the molded body <NUM>. In the case that the substrate <NUM> is a stamped substrate <NUM> (e.g., as described with reference to <FIG>), the complete lower surface <NUM> of the substrate <NUM> including the lower sides of the islands <NUM> and the vertically offset portions can be exposed from the molded body <NUM>.

Referring to <FIG>, a plurality of holes <NUM> is formed in the molded body <NUM> and a plurality of recesses <NUM> is formed the upper surface <NUM> of the substrate <NUM>. Each recess <NUM> is disposed beneath each of the respective holes <NUM>. That is, a single perforation <NUM> that penetrates the molded body <NUM> and terminates within the substrate <NUM> is provided by a combination of one of the holes <NUM> and one of the recesses <NUM>. These holes <NUM> and the corresponding recesses <NUM> can be formed in any one of the islands <NUM> including the islands <NUM> which accommodate the semiconductor dies <NUM> and the islands <NUM> that do not accommodate the semiconductor dies <NUM> and are electrically connected to the semiconductor dies <NUM>.

The holes <NUM> in the molded body <NUM> and the corresponding recesses <NUM> in the upper surface <NUM> that are beneath each hole <NUM> are formed by a single process step that completely penetrates the molded body <NUM> and subsequently partially penetrates the substrate <NUM>. For example, the single process step can include a mechanical drilling technique whereby a drill bit penetrates the molded body <NUM> and partially penetrates the substrate <NUM>. In another embodiment, the single process step can include can include a laser drilling technique whereby highly concentrated energy is directed at the upper surface <NUM> of the module until the molded body <NUM> is penetrated and the substrate <NUM> is partially penetrated.

Referring to <FIG>, press-fit connectors <NUM> are arranged in each one of the holes <NUM> such that a mechanical and electrical connection exists between interior ends of the press-fit connectors <NUM> and the substrate <NUM>. The press-fit connectors <NUM> are electrically conductive structures that are designed to provide I/O connectivity for a power semiconductor module. The press-fit connectors <NUM> may include an electrically conductive metal, e.g., Cu, Al, etc., and may include one or more layer of anticorrosion plating, e.g., Ni, Ag, Au, etc. The press-fit connectors <NUM> provide externally accessible points of electrical contact to the various terminals of the second semiconductor dies <NUM> via the electrical connections <NUM> contained within the molded body <NUM>. The press-fit connectors <NUM> can be designed to provide a force-fitting connection with a circuit interface, such as a printed circuit board, by inserting distal ends of the press-fit connectors <NUM> into correspondingly shaped receptacles in the circuit interface. The mechanical connection between the press-fit connectors <NUM> and the substrate <NUM> is sufficiently force-resistant such that the press-fit connectors <NUM> are not easily removed by ordinary human pulling force and can be inserted and withdrawn from the receptacles of the circuit interface without breakage. Generally speaking, a diameter of the press-fit connectors <NUM> may be in the range of <NUM> - <NUM> and may be <NUM> in a certain embodiment. The distal ends may of the press-fit connectors <NUM> may be designed to plastically deform and/or may include a spring-loaded contact mechanism to enhance I/O connectivity.

In an embodiment, the mechanical and electrical connection between the press-fit connectors <NUM> and the substrate <NUM> is provided by welding the interior ends of the press-fit connectors <NUM> to the substrate <NUM>. More specifically, an electrical resistance welding technique can be performed whereby very large amounts of current are passed through the two elements, thereby generating sufficient heat to melt the metals and effectuate the weld. In another example, a laser welding technique can be performed whereby concentrated radiation, e.g., from a continuous or pulsed laser beam, is directed at the joining interface until sufficient heat is generated to melt the metals and effectuate the weld. More generally, any of a variety of welding techniques may be employed.

In an embodiment, the mechanical and electrical connection between the press-fit connectors <NUM> and the substrate <NUM> is provided without welding. For example, the recesses <NUM> can be dimensioned to have a diameter that is slightly less than the diameter of the press-fit connectors <NUM> (e.g., about <NUM>-<NUM>% less) such press-fit connector <NUM> can be inserted in the recesses <NUM> and securely retained thereafter by mechanical pressure. In another example, the interior end of the press-fit connector <NUM> may include protruding features, e.g., ridges or threads, that engage with the sidewalls of the recess <NUM> in a similar manner as a screw or bolt.

In any of the above examples, the substrate <NUM> acts as an anchor point that provides substantial mechanical stabilization for each press-fit connector <NUM> and simultaneously provides electrical redistribution. Advantageously, no soldering or additional features such as pin rivets are needed to form the mechanical and electrical connection between the press-fit connectors <NUM> and the substrate <NUM>.

Instead of forming the holes <NUM> in the molded body <NUM> subsequently attaching the press-fit connectors <NUM> to the substrate, the press-fit connectors <NUM> can be attached before forming the molded body <NUM>. For example, the press-fit connectors <NUM> can be welded to the substrate <NUM> or attached to the substrate through mechanical means according to the above described techniques and the molded body <NUM> can be subsequently formed around the press-fit connectors <NUM>.

Referring to <FIG>, rear side processing steps for electrically isolating the islands <NUM> are shown. In either one of the techniques described with reference to <FIG>, after forming the channels <NUM>, each one of the islands <NUM> remain connected to one another by the portions <NUM> of the substrate <NUM> that are directly beneath the channels <NUM>. In the case of the half-etching technique described with reference to <FIG>, these portions <NUM> of the planar sheet metal directly underneath the channels <NUM> are thinner than the islands <NUM>. In the case of the stamping technique described with reference to <FIG>, these portions <NUM> of the planar sheet metal directly underneath the channels <NUM> are vertically offset from the islands <NUM> and have about the same thickness as the islands, <NUM>. In either case, the process steps shown in <FIG> remove these portions <NUM> of the substrate <NUM> so as to eliminate any connection between adjacent islands <NUM>, thereby forming isolated bond pads.

Referring to <FIG>, a selective etching technique is applied to the lower surface <NUM> of the substrate <NUM>. In the embodiment of <FIG>, the substrate <NUM> is the half-etched substrate <NUM> that was formed according to the technique described with reference to <FIG>. According to this technique, a mask <NUM> is provided on the lower surface <NUM> of the substrate <NUM> and the portions of the substrate <NUM> exposed from the mask <NUM> are etched, e.g., in a similar manner as the half-etching technique described with reference to <FIG>. As the geometry of the desired regions to be removed is the same as the geometry of the channels <NUM>, a common photomask can be used to form both masks (i.e., the mask used to form the channels <NUM> and the mask used to remove the portions <NUM> underneath the channels <NUM>).

Referring to <FIG>, a selective etching technique is applied to the lower surface <NUM> of a differently configured substrate <NUM>. In the embodiment of <FIG>, the substrate <NUM> is a stamped planar sheet metal that was formed according to the technique described with reference to <FIG>. The rear side etching process can be substantially similar as the technique of <FIG> except that the etching conditions are selected to remove the thicker vertically offset portions <NUM> of the substrate <NUM>.

Referring to <FIG>, a planarizing technique is applied to the lower surface <NUM> of the planar sheet metal. In the embodiment of <FIG>, the substrate <NUM> is a stamped planar sheet metal that was formed according to the technique described with reference to <FIG>. The planarization technique uniformly removes material from the stamped substrate <NUM> until the bottom of the channels <NUM> is exposed. This may be done using a chemical polishing process, a mechanical polishing process (e.g., grinding) or a chemical-mechanical polishing (CMP) process, for example.

Referring to <FIG>, after performing the rear side processing step, the islands <NUM> are completely separated and isolated from one another by the encapsulant material of the molded body <NUM> If desired, these islands <NUM> can be configured as electrical terminals for electrically accessing each terminal of the semiconductor dies <NUM> at the lower side of the module.

As shown in <FIG>, the lower surface <NUM> of the substrate <NUM> can be covered by a layer of electrically insulating material. As a result, the module can be mounted on an external apparatus, e.g., a heat sink, with the layer of electrically insulating material providing electrical isolation for each of the islands <NUM>. Generally speaking, the layer of electrically insulating material may be any commercially available high-K packaging dielectric. According to an embodiment, the layer of electrically insulating material is or comprises a ceramic material. In another embodiment, the layer of electrically insulating material is or comprises an oxide layer that is deposited by oxidation in an electrochemical or chemical process. In another embodiment, the layer of insulation material is or comprises particles and a matrix material. The Matrix material can be, e.g., epoxy, silicone or an acrylate. The particles can be e.g., from ceramic, coated metals, and glass. The particles can be mixed from two and more materials. The form of particles can be spherical, crushed spheres, plates and nail shapes. A thickness of the layer of electrically insulating material may be between <NUM> and <NUM>, for example, and may be between <NUM> and <NUM> in certain embodiments.

Terms such as "first", "second", and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

Claim 1:
A method of forming a power semiconductor module, the method comprising:
providing a substrate (<NUM>) of planar sheet metal;
forming channels (<NUM>) in an upper surface (<NUM>) of the substrate (<NUM>) that partially extend through a thickness of the substrate (<NUM>) and define a plurality of islands (<NUM>) in the substrate (<NUM>);
mounting a first semiconductor die (<NUM>) on a first one of the islands (<NUM>);
forming a molded body (<NUM>) of encapsulant that covers the substrate (<NUM>), fills the channels (<NUM>), and encapsulates the semiconductor die (<NUM>); characterized by
forming a hole (<NUM>) in the molded body (<NUM>) and a recess (<NUM>) in the upper surface (<NUM>) of the substrate (<NUM>) beneath the hole (<NUM>) in a single process step that completely penetrates the molded body (<NUM>) and subsequently partially penetrates the substrate (<NUM>), and
arranging a press-fit connector (<NUM>) in the hole (<NUM>) and forming a mechanical and electrical connection between an interior end of the press-fit connector (<NUM>) and the substrate (<NUM>).