Patent Description:
An artificial neural network, which may be composed of an interconnected group of artificial neurons (e.g., neuron models), is a computational device or represents a method performed by a computational device. These neural networks may be used for various applications and/or devices, such as internet protocol (IP) cameras, Internet of Things (IoT) devices, autonomous vehicles, and/or service robots.

Convolutional neural networks are a type of feed-forward artificial neural network. Convolutional neural networks may include collections of neurons that each has a receptive field and that collectively tile an input space. Convolutional neural networks (CNNs) have numerous applications. In particular, CNNs have broadly been used in the area of pattern recognition and classification.

Deep learning architectures, such as deep belief networks and deep neural networks (DNNs), are layered neural network architectures. In these layered neural network architectures, the output of a first layer of neurons becomes an input to a second layer of neurons, the output of a second layer of neurons becomes and input to a third layer of neurons, and so on. Deep neural networks may be trained to recognize a hierarchy of features and so they have increasingly been used in object recognition applications. Like convolutional neural networks, computation in these deep learning architectures may be distributed over a population of processing nodes, which may be configured in one or more computational chains. These multi-layered architectures may be trained one layer at a time and may be fine-tuned using back propagation.

Deep learning neural networks, having either convolution or fully connected layers, enable processing for image recognition, object detection, and natural language processing. These features enable support for autonomous driving applications as well as content-aware camera processing. Deep convolutional neural networks (DCNs) have promising applications in emerging embedded, wearable, and Internet of Things (IoT) markets.

<NPL>, relates to an energy efficient engine optimized to operate on compressed deep neural networks.

Although these deep neural network solutions achieve excellent results, their computational complexity can be prohibitively high. Additionally, training of the models may be challenging.

A deep neural network for exploiting activation sparsity is described. The deep neural network includes means for retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The deep neural network also includes means for generating a compressed activation tensor comprising non-zero activations of the activation tensor. The compressed activation tensor has fewer columns than the activation tensor. The deep neural network further includes means for processing the compressed activation tensor and the weight tensor to generate an output tensor.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

Deep learning neural networks, having either convolutional or fully connected layers, enable processing for image recognition, object detection, and natural language processing. These features enable support for autonomous driving applications as well as content-aware camera processing. Deep convolutional neural networks (DCNs) have promising applications in emerging embedded, wearable, and Internet of Things (IoT) markets.

In operation, a deep convolutional network (or DCN) may be composed of a large number of weight tensors multiplied by activation tensors. These weight tensors and activation tensors enable multiplying of input data by weights in various filters of the DCN. For example, the activation tensors may be fed through nonlinear functions (e.g., in a previous layer of the DCN). In DCNs using rectified linear unit (ReLU) nonlinear activation functions, a significant number of activation values are zero. The zero activations are produced because ReLU nonlinear activation functions are generally configured to clamp activation values less than zero to an activation value of zero. Consequently, non-zero activation values may be sparse in DCNs using ReLU nonlinear activation functions.

DCNs are generally composed of a large number of weight tensors multiplied by activation tensors to perform a task. DCNs, therefore, consume significant computing power when handling multiply-accumulate (MAC) operations of the large number of weight tensors and activation tensors. Multiplying a weight by a zero activation, however, does not affect a resulting MAC sum. Consequently, a MAC hardware time slot is wasted when processing a zero activation at the next network layer. Depending on the amount of non-zero activation values, significant resources may be wasted on zero activations. Instead, these MAC time slots are better served for useful (non-zero) activation computations. Aspects of the present disclosure describe methods of exploiting activation sparsity in deep neural networks (DNNs).

<FIG> illustrates an example implementation of a system-on-a-chip (SOC) <NUM>, which may include a central processing unit (CPU) <NUM> or multi-core CPUs configured to exploit activation sparsity in accordance with certain aspects of the present disclosure. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) <NUM>, in a memory block associated with a CPU <NUM>, in a memory block associated with a graphics processing unit (GPU) <NUM>, in a memory block associated with a digital signal processor (DSP) <NUM>, in a memory block <NUM>, or may be distributed across multiple blocks. Instructions executed at the CPU <NUM> may be loaded from a program memory associated with the CPU <NUM> or may be loaded from a memory block <NUM>.

The SOC <NUM> may also include additional processing blocks tailored to specific functions, such as a connectivity block <NUM>, which may include fifth generation (<NUM>) connectivity, fourth generation long term evolution (<NUM> LTE) connectivity, unlicensed Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor <NUM> that may, for example, detect and recognize gestures. In one implementation, the NPU is implemented in the CPU, DSP, and/or GPU. The SOC <NUM> may also include a sensor processor <NUM>, image signal processors (ISPs) <NUM>, and/or navigation module <NUM>, which may include a global positioning system.

The SOC <NUM> may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the NPU <NUM> may include code to exploit activation sparsity in deep neural networks (DNNs).

Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, a machine learning approach to an object recognition problem may have relied heavily on human engineered features, perhaps in combination with a shallow classifier. A shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs. Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.

A deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.

Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.

Neural networks may be designed with a variety of connectivity patterns. In feed-forward networks, information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers. A hierarchical representation may be built up in successive layers of a feed-forward network, as described above. Neural networks may also have recurrent or feedback (also called top-down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer. A recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence. A connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.

The connections between layers of a neural network may be fully connected or locally connected. <FIG> illustrates an example of a fully connected neural network <NUM>. In a fully connected neural network <NUM>, a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer will receive input from every neuron in the first layer. <FIG> illustrates an example of a locally connected neural network <NUM>. In a locally connected neural network <NUM>, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, a locally connected layer of the locally connected neural network <NUM> may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connections strengths that may have different values (e.g., <NUM>, <NUM>, <NUM>, and <NUM>). The locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer, because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.

One example of a locally connected neural network is a convolutional neural network. <FIG> illustrates an example of a convolutional neural network <NUM>. The convolutional neural network <NUM> may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., <NUM>). Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.

One type of convolutional neural network is a deep convolutional network (DCN). <FIG> illustrates a detailed example of a DCN <NUM> designed to recognize visual features from an image <NUM> input from an image capturing device <NUM>, such as a car-mounted camera. The DCN <NUM> of the current example may be trained to identify traffic signs and a number provided on the traffic sign. Of course, the DCN <NUM> may be trained for other tasks, such as identifying lane markings or identifying traffic lights.

The DCN <NUM> may be trained with supervised learning. During training, the DCN <NUM> may be presented with an image, such as the image <NUM> of a speed limit sign, and a forward pass may then be computed to produce an output <NUM>. The DCN <NUM> may include a feature extraction section and a classification section. Upon receiving the image <NUM>, a convolutional layer <NUM> may apply convolutional kernels (not shown) to the image <NUM> to generate a first set of feature maps <NUM>. As an example, the convolutional kernel for the convolutional layer <NUM> may be a 5x5 kernel that generates 28x28 feature maps. In the present example, because four different convolutional kernels were applied to the image <NUM> at the convolutional layer <NUM>, four different feature maps are generated in the first set of feature maps <NUM>,. The convolutional kernels may also be referred to as filters or convolutional filters.

The first set of feature maps <NUM> may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps <NUM>. The max pooling layer reduces the size of the first set of feature maps <NUM>. That is, a size of the second set of feature maps <NUM>, such as 14x14, is less than the size of the first set of feature maps <NUM>, such as 28x28. The reduced size provides similar information to a subsequent layer while reducing memory consumption. The second set of feature maps <NUM> may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

In the example of <FIG>, the second set of feature maps <NUM> is convolved to generate a first feature vector <NUM>. Furthermore, the first feature vector <NUM> is further convolved to generate a second feature vector <NUM>. Each feature of the second feature vector <NUM> may include a number that corresponds to a possible feature of the image <NUM>, such as "sign," "<NUM>," and "<NUM>. " A softmax function (not shown) may convert the numbers in the second feature vector <NUM> to a probability. As such, an output <NUM> of the DCN <NUM> is a probability of the image <NUM> including one or more features.

In the present example, the probabilities in the output <NUM> for "sign" and "<NUM>" are higher than the probabilities of the others of the output <NUM>, such as "<NUM>," "<NUM>," "<NUM>," "<NUM>," "<NUM>," "<NUM>," and "<NUM>". Before training, the output <NUM> produced by the DCN <NUM> is likely to be incorrect. Thus, an error may be calculated between the output <NUM> and a target output. The target output is the ground truth of the image <NUM> (e.g., "sign" and "<NUM>"). The weights of the DCN <NUM> may then be adjusted so the output <NUM> of the DCN <NUM> is more closely aligned with the target output.

To adjust the weights, a learning algorithm may compute a gradient vector for the weights. The gradient may indicate an amount that an error would increase or decrease if the weight were adjusted. At the top layer, the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer. In lower layers, the gradient may depend on the value of the weights and on the computed error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as "back propagation" as it involves a "backward pass" through the neural network.

In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level. After learning, the DCN may be presented with new images (e.g., the speed limit sign of the image <NUM>) and a forward pass through the network may yield an output <NUM> that may be considered an inference or a prediction of the DCN.

Deep belief networks (DBNs) are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors, and the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.

Deep convolutional networks (DCNs) are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.

DCNs may be feed-forward networks. In addition, as described above, the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of DCNs may be exploited for fast processing. The computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.

The processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The outputs of the convolutional connections may be considered to form a feature map in the subsequent layer <NUM> and <NUM>, with each element of the feature map (e.g., <NUM>) receiving input from a range of neurons in the previous layer (e.g., <NUM>) and from each of the multiple channels. The values in the feature map may be further processed with a non-linearity, such as a rectification, max(<NUM>,x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.

The performance of deep learning architectures may increase as more labeled data points become available or as computational power increases. Modern deep neural networks are routinely trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms may further boost the performance of deep learning. Rectified linear units may reduce a training issue known as vanishing gradients. New training techniques may reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques may abstract data in a given receptive field and further boost overall performance.

<FIG> is a block diagram illustrating an deep convolutional network <NUM>. The deep convolutional network <NUM> may include multiple different types of layers based on connectivity and weight sharing. As shown in <FIG>, the deep convolutional network <NUM> includes the convolution blocks 354A, 354B. Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) <NUM>, a normalization layer (LNorm) <NUM>, and a max pooling layer (MAX POOL) <NUM>.

The convolution layers <NUM> may include one or more convolutional filters, which may be applied to the input data to generate a feature map. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354A, 354B may be included in the deep convolutional network <NUM> according to design preference. The normalization layer <NUM> may normalize the output of the convolution filters. For example, the normalization layer <NUM> may provide whitening or lateral inhibition. The max pooling layer <NUM> may provide down sampling aggregation over space for local invariance and dimensionality reduction.

The parallel filter banks, for example, of a deep convolutional network may be loaded on a CPU <NUM> or GPU <NUM> of an SOC <NUM> to achieve high performance and low power consumption. In alternative embodiments, the parallel filter banks may be loaded on the DSP <NUM> or an ISP <NUM> of an SOC <NUM>. In addition, the deep convolutional network <NUM> may access other processing blocks that may be present on the SOC <NUM>, such as sensor processor <NUM> and navigation module <NUM>, dedicated, respectively, to sensors and navigation.

The deep convolutional network <NUM> may also include one or more fully connected layers <NUM> (FC1 and FC2). The deep convolutional network <NUM> may further include a logistic regression (LR) layer <NUM>. Between each layer <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the deep convolutional network <NUM> are weights (not shown) that are to be updated. The output of each of the layers (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) may serve as an input of a succeeding one of the layers (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) in the deep convolutional network <NUM> to learn hierarchical feature representations from input data <NUM> (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A. The output of the deep convolutional network <NUM> is a classification score <NUM> for the input data <NUM>. The classification score <NUM> may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.

<FIG> is a block diagram illustrating an exemplary software architecture <NUM> that may modularize artificial intelligence (AI) functions. Using the architecture, applications may be designed that may cause various processing blocks of an SOC <NUM> (for example a CPU <NUM>, a DSP <NUM>, a GPU <NUM> and/or an NPU <NUM>) to exploit activation sparsity in computations during run-time operation of an AI application <NUM>, according to aspects of the present disclosure.

The AI application <NUM> may be configured to call functions defined in a user space <NUM> that may, for example, provide for the detection and recognition of a scene indicative of the location in which the device currently operates. The AI application <NUM> may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The AI application <NUM> may make a request to compiled program code associated with a library defined in an AI function application programming interface (API) <NUM>. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example.

A run-time engine <NUM>, which may be compiled code of a runtime framework, may be further accessible to the AI application <NUM>. The AI application <NUM> may cause the run-time engine, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the application. When caused to provide an inference response, the run-time engine may in turn send a signal to an operating system in an operating system (OS) space <NUM>, such as a Linux Kernel <NUM>, running on the SOC <NUM>. The operating system, in turn, may exploit activation sparsity in computations performed on the CPU <NUM>, the DSP <NUM>, the GPU <NUM>, the NPU <NUM>, or some combination thereof. The CPU <NUM> may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver <NUM>, <NUM>, or <NUM> for, respectively, the DSP <NUM>, the GPU <NUM>, or the NPU <NUM>. In the exemplary example, the deep neural network may be configured to run on a combination of processing blocks, such as the CPU <NUM>, the DSP <NUM>, and the GPU <NUM>, or may be run on the NPU <NUM>.

<FIG> is a block diagram illustrating vector lanes to compute dot products of activations and weights in a deep neural network (DNN) <NUM>. This example illustrates a part of processing a layer of DNN <NUM>, in which an X*I activation tensor and a W*I weight tensor are retrieved from memory. <FIG> shows a simplified example in which X=<NUM>, I=<NUM>, and W=<NUM> to avoid obscuring details of the present disclosure. Processing the layer of the DNN <NUM> may include calculating the dot product of every column of an activation tensor <NUM> with every column of a weight tensor <NUM> using multiple accumulate (MAC) hardware <NUM>. In this example, a calculation of <NUM> (=<NUM>*<NUM>*<NUM>) products can be done in <NUM> (X*W) clock cycles. Notably, the activation tensor <NUM> has many zero values. Processing of activations having a zero value may be wasteful. Aspects of the present disclosure exploit activation sparsity caused by zero value activations to reduce the total number of multiplications performed. As detailed below, compacting and rearranging the non-zero values of the activation tensor <NUM> allows for the calculation of the output of the layer of the DNN <NUM> in fewer clock cycles.

Activations in the DNN <NUM> may be understood as activation blocks that are represented as 3D activation tensors, including an X-component, a Y-component, and a location component (e.g., a corresponding sample location/pixel location of the activation in an audio/video stream). In this example, the activation tensor <NUM> may be represented as an I*X array, with elements from A(<NUM>,<NUM>) to A(I,X). In addition, the weight tensor <NUM> may be represented as an I*W array, with elements from B(<NUM>,<NUM>) to B(I,W). In order to avoid overcrowding the figures, however, the elements of the activation tensor <NUM> and the weight tensor <NUM> are shown in the figures with a number indicating the channel (e.g., of the I channels) and a shade indicating the column. Computed products of the activation tensor <NUM> and the weight tensor <NUM> may be stored in memory for processing at a next layer of the DNN <NUM>.

As shown in <FIG>, each shade (e.g., source-column) of the activation tensor <NUM> may correspond to an activation from a different input location. The different input location (e.g., number of the source-column) may correlate to a different element (e.g., number of elements) in a previous layer of the DNN <NUM>. In addition, each channel label (e.g., <NUM>-<NUM>) of the activation tensor <NUM> may include a different activation value. That is, the channel label (e.g., <NUM>-<NUM>) of the activation tensor <NUM> is not indicative of the value of the activation. For example, the I number of channels may correlate to the number of filters in the previous layer of the DNN <NUM>. In addition, values of the weight tensor <NUM> are read from memory. The number of weights W of the weight tensor <NUM> may correlate to the number of filters of the present layer, which should correspond to the number of channels in the next layer.

In operation, multiply-accumulate (MAC) hardware <NUM> computes a dot product of each weight column of the weight tensor <NUM> with each column of the activation tensor <NUM>, one dot product for each clock cycle. In this example, the MAC hardware <NUM> processes each multiplier/vector lane (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) with a corresponding MAC unit. Notably, zero activations contribute nothing to the dot product, but consume a multiplier/vector lane (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) as well as a clock cycle. This wastes valuable resources available to the DNN <NUM>.

In particular, application of a rectified linear unit (ReLU) nonlinear activation function in a previous layer of the DNN <NUM> to compute the activation tensor <NUM> results in sparse activations <NUM> when the activation tensor <NUM> is viewed with zero value activations removed. Notably, a significant number of activation values are zero, in which zero activation values are shown as a blank space (e.g., zero activation <NUM>). The zero activations are produced because ReLU nonlinear activation functions are generally configured to clamp activation values less than zero to an activation value of zero in the previous layer. The non-zero activation values in the sparse activations <NUM> are shown including their corresponding channel and their shade to indicate their original location.

As further illustrated in the sparse activations <NUM>, a column <NUM> is shown including zero activations in channels <NUM>, <NUM>, <NUM>, and <NUM> (corresponding to multiplier/vector lanes <NUM>, <NUM>, <NUM>, and <NUM>). As noted above, computing a dot product by the MAC hardware <NUM> on these zero activations during the clock cycle corresponding to the column <NUM> wastes resources of the MAC hardware <NUM>. In the column <NUM>, valuable work is not performed in the blank rows because the dot product computed by the MAC unit is zero when the value of the activation is zero. That is, there is no useful work to be performed when multiplying by zero. Thus, the multiplier/vector lanes (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) of the MAC hardware <NUM> are effectively empty for zero activation values.

As should be recognized by the sparse activations <NUM>, a given row of the activation tensor <NUM> may be highly correlated. For example, some channels of the activation tensor <NUM> corresponding to multiplier/vector lanes of the MAC hardware <NUM> have a significant amount of computations to perform. By contrast, other channels of the activation tensor <NUM> correspond to vector lanes (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) of the MAC hardware <NUM> having a minimal amount of computations to perform due to increased numbers of zero activations. In aspects of the present disclosure, non-zero activations are redistributed in time (and clock cycle) to empty multiplier/vector lanes of the MAC hardware <NUM>, for example, as shown in <FIG>. As described herein, the redistribution of non-zero activations in time and clock cycle to empty multiplier/vector lanes may be referred to as lane sloshing. An empty multiplier/vector lane occurs when a number of the multiplier/vector lanes processing a non-zero activation during a clock cycle is less than a vector width (e.g., = eight (<NUM>)) of the MAC hardware <NUM>.

<FIG> is a block diagram further illustrating the multiplier/vector lanes of multiply-accumulate (MAC) hardware of <FIG> to compute dot products of sparse activations and weights in a deep neural network (DNN) <NUM>, in accordance with aspects of the present disclosure. In this aspect of the present disclosure, non-zero activations are packed into the multiplier/vector lanes of the MAC hardware <NUM> to avoid wasting processing resources during a clock cycle due to processing a zero-activation value.

In this example, the activation tensor <NUM> is shown as a first multilane segment <NUM> (e.g., a first input stream) of s-rows (e.g., <NUM>-<NUM>) of the X activations that may use any corresponding one of the multiplier/vector lanes (e.g., <NUM> to <NUM>) of the MAC hardware <NUM>. In addition, a second multilane segment <NUM> (e.g., a second input stream) of s-rows of the X activations that may be redistributed (e.g., activation sloshing) to any corresponding one of the multiplier/vector lanes (e.g., <NUM> to <NUM>). That is, activation sloshing across the multiplier/vector lanes (e.g., <NUM> to <NUM> or <NUM> to <NUM>) of MAC hardware <NUM> increases processing of non-zero activations. In this example, activations from the first multilane segment <NUM> are packed (e.g., compacted) in first-in-first-out (FIFO) buffers <NUM> (or memory buffer) in a maximally dense form using intra-segment lane sloshing. That is, the FIFO buffers <NUM> include only non-zero activations of the first multilane segment <NUM> in a first compressed-activation column <NUM> and a second compressed-activation column <NUM>.

According to the configuration shown in <FIG>, the sparse activations <NUM> of the first multilane segment <NUM> are shown in five columns. A first column <NUM> includes non-zero activations from channels one (<NUM>) and two (<NUM>). A second column <NUM> includes activations from channels <NUM> and <NUM>. A third column <NUM> includes a single activation from channel <NUM>. A fourth column <NUM> includes activations from channels <NUM> and <NUM>. In addition, a fifth column <NUM> includes activations from channels <NUM> and <NUM>. It should be recognized that the various columns (e.g., <NUM>-<NUM>) include non-zero activations having the same source-column (shown here as grey scale shading). The various shades of grey scale are shown to represent the different columns for the purpose of simplifying explanation of the present disclosure. Although described as shades of grey, this is provided for illustration purposes only, such that the shade generally indicates a corresponding input location.

In this configuration, each of the FIFO buffers <NUM> includes an S:<NUM> multiplexer (not shown) at an input of each of the FIFO buffers <NUM>. The S:<NUM> multiplexers enable packing of the sparse activations <NUM> in the FIFO buffers <NUM>. In this example, the activations from the second column <NUM> are packed with the activations from the first column <NUM> of the sparse activations <NUM> into the first column <NUM> of the FIFO buffers <NUM>. Similarly, activations from the third column <NUM>, the fourth column <NUM>, and the fifth column <NUM> of the sparse activations <NUM> are packed into the second column <NUM> of the FIFO buffers <NUM>. An activation from channel <NUM> of the fifth column <NUM> of the sparse activations <NUM> is stored in the third column <NUM> of the FIFO buffers <NUM>, which is not full.

A painting algorithm may pack the activations in the FIFO buffers <NUM>. For example, the painting algorithm may be used to populate the FIFO buffer <NUM> from the first multilane segment <NUM> of the activation tensor <NUM>. In this example, the painting function operates by traversing down and across the sparse activations <NUM> and populating the FIFO buffer <NUM> with the non-zero activation values. For example, arrows are shown to illustrate packing of the first column <NUM> and the second column <NUM> of the sparse activations <NUM> in the first column of the FIFO buffers <NUM>. According to aspects of the present disclosure, the FIFO buffers may include multiplexers (not shown) that may be used to implement the painting function and the compacting function of non-zero activations of the activation tensor <NUM>.

According to aspects of the present disclosure, hardware complexity is controlled by limiting the compressed activation columns (e.g., <NUM>, <NUM>, and <NUM>) of the FIFO buffers <NUM>. In this configuration, the compressed activation columns of the FIFO buffer are limited to K (e.g., two) source-columns. Accordingly, activation values from the source-columns (e.g., <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) of the sparse activations <NUM> may be moved to other compressed activation columns of the FIFO buffer <NUM> to meet, but not exceed, the source-column constraint when stored in memory for processing by the MAC hardware <NUM>, as described in further detail below.

Once loaded into the compressed activation columns of the FIFO buffers <NUM>, activations from the compressed activation columns of the FIFO buffers <NUM> may be popped from the FIFO buffers <NUM> and written to tightly coupled memory (TCM <NUM>) with their metadata for processing on a corresponding one of the multiplier/vector lanes (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) by the MAC hardware <NUM>. In this example, however, writing of the activations to the vector lanes (e. g, <NUM>, <NUM>, <NUM>, and <NUM>) corresponding to columns (e.g., <NUM>, <NUM>, <NUM>) of the TCM <NUM> does not match the arrangement of the activations in the compressed activation columns (e.g., <NUM>, <NUM>, <NUM>) of the FIFO buffers <NUM>. The mismatch is caused by enforcement of a constraint on the number of different source-column (e.g., grey scale activations) for each compressed activation column of the FIFO buffers <NUM>. In other words, only activations from two source-columns (e.g., two grey scales) of the first multilane segment <NUM> of the activation tensor <NUM> are allowed in a single column in the TCM <NUM>. In this example, the source-column constraint is K-source-column activations (e.g., two grey scale activations) for each column, which may be referred to as a maximum product number.

In this aspect of the present disclosure, the second column <NUM> of the FIFO buffers <NUM> does not match the second column <NUM> of the TCM <NUM> because the activation of channel <NUM> is written to the third column <NUM> of the TCM <NUM>. That is, including the activation of channel <NUM> in the second column <NUM> of the TCM <NUM> would violate the source-column constraint by having three different grey scale activations in the second column <NUM> of compressed activations of the TCM <NUM>. As described herein the activation columns of the TCM <NUM> may be referred to as compressed activation columns, and the contents of the TCM <NUM> may be referred to as a compressed activation tensor. As a result, a zero activation value <NUM> is loaded into the TCM <NUM> and loaded onto the multiplier/vector lane <NUM>. In addition, the non-zero activation <NUM> is loaded into the TCM <NUM> and mapped to the multiplier/vector lane <NUM> for processing during a subsequent clock cycle. In aspects of the present disclosure, at least one processor (not shown) coupled to the MAC hardware <NUM>, is configured to redistribute a non-zero activation of the activation tensor <NUM> to an available location.

In operation, metadata regarding the grey scale (original source-column) and a number (original row/channel) of the activations is stored in the TCM <NUM> to direct, for example, multiplexers to provide the corresponding weight column of the weight tensor <NUM>. The metadata is written to the TCM <NUM> so that each multiplier of the MAC hardware <NUM> matches a weight row of the weight tensor <NUM> to the channel lane of the respective activation. The MAC hardware <NUM> may include an arithmetic logic unit (ALU) to compute a dot product of a non-zero activation multiplied by one weight of the weight tensor <NUM> corresponding to the channel. In this example, the number associated with the activation tensor <NUM> may indicate an input channel. In addition, shades of the activation tensor <NUM> indicate a sample from the input (e.g., a pixel with many input channel values). A shade of the weight tensor <NUM> indicates output channel (or filter). For example, an activation from channel <NUM> in the first column <NUM> of the TCM <NUM> is multiplied by a weight (e.g., corresponding to channel one (<NUM>)) in column <NUM> of the weight tensor <NUM>, in which a column <NUM> is also shown. This is performed for each of the activations in a respective column of the TCM <NUM> for each clock cycle.

<FIG> is a block diagram illustrating the multiply-accumulate (MAC) hardware <NUM> to support the configuration of the DNN <NUM> of <FIG> in accordance with aspects of the present disclosure. In this configuration, S multipliers <NUM> are shown along with K accumulator trees. A first accumulator tree <NUM> include a first adder <NUM> and a first accumulator <NUM>. In addition, a second accumulator tree includes a second adder <NUM> and a second accumulator <NUM>. Although this configuration of the MAC hardware is shown for two source-columns (e.g., K = <NUM>) of activations and eight multipliers (e.g., S = <NUM>), it should be recognized that other configurations are possible. In the configuration shown, hardware costs are reduced and adjustable relative to the K value of the K accumulator trees. In this configuration, each clock cycle may compute up to K distinct dot product results, in which the K accumulator trees may be cleared after each clock cycle and assigned to new multiplier/vectors lanes according to the source-column constraint.

In this example, the MAC hardware <NUM> is configured to process activations of the first multilane segment <NUM> and the second multilane segment <NUM> rearranged in the TCM memory <NUM> to reduce processing of zero value activations, as described in <FIG>. As shown in <FIG>, the TCM memory <NUM>, including rearranged/sloshed activations is subject to a number of different source-columns (=<NUM>). This constraint is shown using different shading of the activations in the TCM <NUM>. Because this example is limited to a source-column constraint of two different numbers of source-columns, implementation of accumulators for the MAC hardware <NUM> is simplified. In particular, this configuration may be implemented with two adders (e.g., <NUM> and <NUM>) and two corresponding accumulators (e.g., <NUM> and <NUM>), as described in further detail below.

In this example, the column <NUM> and the column <NUM> from the weight tensor <NUM> in <FIG> are rotated horizontally to represent the weight tensor <NUM>, without obscuring details of the present disclosure. During each clock cycle, the activation of a column of the TCM <NUM> are multiplied by a corresponding weight using multiplexers <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>). For example, for a first activation <NUM> in the first column <NUM> of the TCM <NUM>, the multiplexer <NUM>-<NUM> is configured to route each weight corresponding to channel <NUM> to match the channel of the first activation <NUM>. Similarly, for a second activation <NUM>, the multiplexer <NUM>-<NUM> is configured to route each weight corresponding to channel <NUM> to match the channel of the second activation <NUM>. In addition, the multiplexer <NUM>-<NUM> is configured to route each weight corresponding to channel <NUM> to match the channel of a third activation <NUM> in the first column <NUM>. The multiplexer <NUM>-<NUM> is also configured to route each weight corresponding to channel <NUM> to match the channel of the fourth activation <NUM> in the first column.

Depending on a source-column of the activation (shown with a fill pattern), the product is sent to an appropriate accumulator tree of the K accumulators. As described herein an accumulator tree collective refers to the combination of an adder and an accumulator. For example, a first accumulator tree may refer to the combination of the first adder <NUM> and the first accumulator <NUM>. In addition, a second accumulator tree may refer to the combination of the second adder <NUM>, and a second accumulator <NUM>.

In this configuration, stored metadata is used to determine the accumulator tree to which a dot product is sent. For example, the first activation <NUM> and the second activation <NUM> from the first column <NUM> of the TCM <NUM> having the same source-column and are, therefore, routed to the first adder <NUM> and the first accumulator <NUM> (acc0) of the first accumulator tree <NUM>. By contrast, the third activation <NUM> and the fourth activation <NUM> from the first column <NUM> of the TCM <NUM> are routed to the second adder <NUM> and the second accumulator <NUM> (acc1) of the second accumulator tree <NUM>. The adders (e.g., <NUM> and <NUM>) add the products and send them to the respective accumulator (e.g., <NUM> and <NUM>). After a processing of a source-column is finished, the first accumulator tree <NUM> are popped and a source-column of activations is sent to the first accumulator tree <NUM> and the second accumulator tree <NUM> for the next column of the TCM <NUM>. The processing of non-zero activation input tensors and weight tensors is performed by the first accumulator tree <NUM> and the second accumulator tree <NUM> to produce an output tensor <NUM>.

<FIG> is a block diagram <NUM> illustrating the multiplier/vector lanes (e.g., <NUM>,. , <NUM>) of multiply-accumulate (MAC) hardware when an empty stream (e.g., a second multilane <NUM>) of an activation tensor <NUM> is detected, in accordance with aspects of the present disclosure. In this example, a first multilane segment <NUM> and a second multilane segment <NUM> are shown as a first input stream and a second input stream of the activation tensor <NUM>. In contrast to the configurations shown in <FIG>, channels (e.g., <NUM>-<NUM>) of the second multilane segment <NUM> are empty. This scenario occurs when the number of channels of the activation tensor <NUM> is less than the vector width (e.g., eight) of the MAC hardware <NUM>. That is, although a vector width of the MAC hardware <NUM> is eight in this example, the activation tensor <NUM> is limited to the four channels of the first multilane segment <NUM>, as the second multilane segment <NUM> is empty. Nevertheless, instead of allowing half of the MAC hardware <NUM> to remain idle, artificial sparsity is introduced to spread the four channels of the first multilane segment <NUM> across the MAC hardware <NUM> to maximize resource utilization.

Once the second multilane segment <NUM> is detected as empty, control logic (e.g., the SOC <NUM>) may be configured to spread the first multilane segment <NUM> of the activation tensor <NUM> across the multiplier/vector lanes of the MAC hardware <NUM>. This process includes grouping non-zero activations from different channel lanes into activation groups <NUM>, including a first activation group <NUM> and a second activation group <NUM>. As shown in <FIG>, the number of activation groups (e.g., <NUM> and <NUM>) of activations is less than a channel depth of the first multilane segment <NUM> of the activation tensor <NUM>. The activation groups (e.g., <NUM> and <NUM>) include a number of non-zero channels and zero channels. In addition, a group depth multiplied by the number of groups equals the processing vector width of the MAC hardware <NUM>. In this configuration, the non-zero activations from the first activation group <NUM> are packed into the FIFO buffers <NUM>. Similarly, the non-zero activations from the second activation group <NUM> are packed into FIFO buffers <NUM>. Subsequently, the non-zero activations are popped from the FIFO buffers <NUM> and the FIFO buffers <NUM> and stored in the TCM memory <NUM> and the TCM memory <NUM> for processing on the vector lanes of the MAC hardware <NUM> to compute dot products of the activations and the weights of a weight tensor <NUM>.

As shown in <FIG>, the packing process into the FIFO buffers (e.g., <NUM> and <NUM>) and the TCM memory (e.g., <NUM> and <NUM>) is similar to the methodologies shown in <FIG>. While some resources of the MAC hardware <NUM> may go unused during certain clock cycles, using artificial sparsity and packing of the FIFO buffers (e.g., <NUM> and <NUM>) and the TCM memory (e.g., <NUM> and <NUM>) according to the source-column activation constraint reduces an amount of wasted resources when encountering empty activation channels. A process for exploiting activation sparsity is shown in <FIG>.

<FIG> illustrates a method of exploiting activation sparsity to improve efficiency of multiply-accumulate (MAC) hardware in accordance with aspects of the present disclosure. A method <NUM> begins at block <NUM>, in which a variable number of channels of multilane segments of an activation tensor of sparse activations are redistributed into a number of activation groups that are smaller than a channel depth of a first multilane segment when a number of channels of the activation tensor is less than a machine's processing vector width. For example, as shown in <FIG>, the first multilane segment <NUM> (e.g., first input stream) and the second multilane segment <NUM> (second input stream ) of the activation tensor <NUM> are shown. The first multilane segment <NUM> has a channel depth of four lanes of activations. Because the number of channels (=<NUM>) of the activation tensor <NUM> is less than the machine's processing vector width (=<NUM>), the first multilane segment <NUM> includes activations, whereas the second multilane segment <NUM> is empty. In this example, the first multilane segment <NUM> of activation tensor <NUM> is distributed into activation groups, including a first activation group <NUM> and a second activation group <NUM>.

Referring again to <FIG>, in block <NUM>, non-zero activations from each group are packed into vector lanes. For example, as shown in <FIG>, the non-zero activations from the first activation group <NUM> are packed into the FIFO buffers <NUM>. Similarly, the non-zero activations from the second activation group <NUM> are packed into FIFO buffers <NUM>. Subsequently, the non-zero activations are popped from the FIFO buffers <NUM> and the FIFO buffers <NUM> and stored in the TCM memory <NUM> and the TCM memory <NUM> for processing on the vector lanes of the MAC hardware <NUM>.

In block <NUM>, an artificial zero activation is inserted into a vector lane when a constraint on a number of unique computations for each vector operation is exceeded. For example, as shown in <FIG>, a zero activation value <NUM> is inserted in the second column <NUM> of the vector lane corresponding to channel <NUM>. In addition, the non-zero activation (channel <NUM>) is loaded on the vector lane corresponding to channel <NUM> at the third column <NUM> of the vector lanes, which corresponds to a next clock cycle. The constraint may be violated when a group of the non-zero activation input values packed onto vector lanes of the MAC hardware <NUM> includes a number of different source locations (e.g., channel number) greater than a maximum product number of the MAC hardware <NUM>.

In block <NUM>, the input tensor of activations is processed to obtain an output tensor. For example, as shown in <FIG>, the processing of the input tensor of activations (e.g., activation tensor <NUM>) and weight tensors (e.g., weight tensor <NUM>) is performed by the MAC hardware to produce an output tensor <NUM>. This process may include determining original channel lanes (e.g., channels) of the non-zero activations of the input tensor of activations to identify the corresponding weight tensor(s). The process also includes computing a dot product of the non-zero activations of the activation tensor and a weight tensor corresponding to the original channel lane of the non-zero activations to obtain an output tensor at block <NUM>.

In one configuration, a machine learning model is configured for receiving an activation from an intermediate layer of the DNN. The model is also configured for spreading sparse activations according idle vector lanes. The model is further configured for tracking the spreading of the activations to enable dot product computation of the activations with corresponding weight tensors and introducing artificial sparsity when empty activation channels are detected.

In some aspects, the method <NUM> may be performed by the SOC <NUM> (<FIG>). That is, each of the elements of method <NUM> may, for example, but without limitation, be performed by the SOC <NUM> or one or more processors (e.g., CPU <NUM> and/or NPU <NUM>) and/or other components included therein.

Aspects of the disclosure spread work across vector lanes of multiply-accumulate (MAC) hardware to improve multiplier utilization. Work is spread across the vector lanes of the MAC hardware by compressing sparse activations onto vector lanes to minimize a number of empty (e.g., including a zero activation) vector lanes for each clock cycle. In addition, on-chip memory bandwidth and power are reduced with compact zeros removed from of activation data before writing to on-chip memory, thereby improving operational efficiency of a deep neural network (DNN). Aspects of the present disclosure also use both a slosh constraint (maximum sloshing across S rows), and an accumulator constraint (maximum different source-column number) to trade off area/power cost versus efficiency. When the number of input channels is less than the vector width of the machine, resulting in empty activation channels, artificial sparsity is introduced to spread the activations of the non-empty channel across the vector lanes of MAC hardware. Aspects of the disclosure support efficient execution of layers (e.g., pixel values/audio samples) whose shape does not map perfectly to a vector unit width. Aspects of the disclosure compress sparse activations to accelerate processing. That is, a number of elements in a vector are remapped to avoid idle time slots.

The model includes means for distributing, means for packing non-zero activations, means for inserting, and means for processing. The model also includes means for computing, means for detecting, means for determining original channel lanes of an input tensor of activations, means for painting, means for redistributing, and means for multiplexing weights of the weight tensor. In one aspect, the distributing means, packing means, inserting means, means for multiplexing, means for painting, means for redistribution, and/or processing means may be the multiplexers <NUM>, the CPU <NUM>, program memory associated with the CPU <NUM>, memory block <NUM>, the NPU <NUM> program memory associated with the NPU <NUM>, the CPU <NUM>, and/or the NPU <NUM> configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus.

The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The computer-program product may comprise packaging materials.

In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described herein. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.

The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.

A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium.

Claim 1:
A method of exploiting activation sparsity in deep neural networks, comprising:
retrieving an activation tensor (<NUM>) and a weight tensor (<NUM>) where the activation tensor is a sparse activation tensor comprising a number of non-zero activations and a number of zero value activations;
generating a compressed activation tensor (<NUM>) comprising the non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor based on a source-column constraint, wherein generating the compressed activation tensor (<NUM>) comprises:
moving only the non-zero activations from first memory locations of source-columns of the sparse activation tensor to second memory locations of compressed columns of a first-in-first-out, FIFO, buffer to meet, but not exceed, the source-column constraint, wherein
the second locations in the FIFO buffer are mapped to empty vector lanes of a multiply-accumulate, MAC, hardware during a clock cycle;
and
processing the compressed activation tensor and the weight tensor using the MAC hardware to generate an output tensor (<NUM>), wherein the processing comprises:
moving the non-zero activations from the second memory locations of the compressed columns of the FIFO buffer to third memory locations in tightly coupled memory for processing on said empty vector lanes of the MAC hardware during the clock cycle;
redistributing at least one non-zero activation from one of the third memory locations to a fourth memory location in the tightly coupled memory for processing during a subsequent clock cycle when the source-column constraint will be exceeded; and
inserting an artificial zero activation in the memory location of the at least one redistributed non-zero activation.