Patent Description:
In general, various data processing applications may rely on transistor technologies. However, it was found that resistor arrays may be useful for some data processing applications as well. Such resistor-based technologies were further developed to allow for a selective reconfiguration of an electric resistance of resistors. Such devices having a non-volatile, reconfigurable electric resistance, may be referred to as memristive devices or memristors, for example. Memristor crossbar arrays were developed to replace transistors and memory cells in some data processing and data storage applications. However, an occurrence of leakage currents in memristor based crossbar arrays may limit a scalability of such structures. Therefore, several types of memristors with nonlinear resistance behavior have been proposed to reduce leakage currents when reconfiguring and reading selective memristors over nonselective memristors. These include so-called complementary resistance switches, which include two memristive structures connected in series, wherein a disadvantage of this technology may be that the state of the complementary resistance can be only read out destructively and, therefore, the complementary resistance switch has to be rewritten after readout. An approach for a nondestructive readout of a state of a complementary resistive switch may be based on capacitance measurements. A complementary resistive switch may include a two-layer memristive structure with strong nonlinear resistive behavior and a single-layer memristive structure with strong nonlinear resistive behavior.

<CIT> discloses a method and apparatus for modeling memristor devices. <CIT> discloses methods for resistive switching of memristors. A further exemplary modeling method is disclosed in <NPL>.

According to the present invention, a method defined in claim <NUM> is provided. Exemplary embodiments are defined in the dependent claims.

In the following description, various aspects of the invention are described with reference to the following drawings, in which:.

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details, and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods and various aspects are described in connection with devices (e.g., arrangements). However, it may be understood that aspects described in connection with methods may similarly apply to the devices, and vice versa.

The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, [. ], etc. The term "a plurality" may be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, [. ], etc. The phrase "at least one of" with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase "at least one of" with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of listed elements.

The phrase "unambiguously assigned" may be used herein to mean a one-to-one-assignment (e.g., allocation, e.g., correspondence) or a bijective assignment. As an example, a first element being unambiguously assigned to a second element may include that the second element is unambiguously assigned to the first element. As another example, a first group of elements being unambiguously assigned to a second group of element may include that each element of the first group of elements is unambiguously assigned to a corresponding element of the second group of elements and that that corresponding element of the second group of elements is unambiguously assigned to the element of the first group of elements.

The term "coupled" may be used herein with respect to nodes, circuit elements, and the like, to mean a, e.g. direct or indirect, connection and/or interaction. Several elements may, for example, be coupled together along an interaction chain (e.g., an electrically conductive path), along which the interaction (e.g., electrical charges) may be transmitted. For example, two elements coupled together may interact with each other.

The term "connected" or "connection" may be used herein with respect to nodes, circuit elements, and the like, to mean electrically connected, which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not influence the substantial functioning of the described circuit or device. The term "electrically conductively connected" that is used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc., may be understood as an electrically conductive connection with, for example, ohmic behavior, e.g., provided by a metal or degenerate semiconductor in absence of p-n junctions in the current path. The term "electrically conductively connected" may be also referred to as "galvanically connected.

In some aspects, two physical and/or chemical properties (e.g., an electrical voltage, an electrical current, an electrical conductance, a thickness, an electrical conductivity, a doping concentration, as examples) may be compared with one another by relative terms such as "greater", "higher", "lower", "less", or "equal", for example. It is understood that, in some aspects, a comparison may include a sign (positive or negative) of a value representing the physical and/or chemical properties or, in other aspects, the absolute values are considered for the comparison. However, a comparison of measurement values representing a physical and/or chemical property may usually include a measurement of such measurement values by the same measurement principle or at least by comparable measurement principles.

According to various aspects, a memristive structure in an array of memristive structures (e.g., within a crossbar array) may be addressable, e.g. by being unambiguously assigned to a logic address. The addressability and the logic addresses may be provided by the architecture of the control lines connected to a respective memristive structure. In a crossbar array, two sets of control lines (e.g., a set of word-lines and a set of bit-lines) may be utilized to address an array of memristive structures. According to various aspects, an analog memristive structure may reside in one of various memristive states (also referred to as resistance states) associated therewith. As an example, the actual electrical resistance (or conductivity) associated with a memristive structure can be determined via a read operation to evaluate in which of the distinct memristive states the memristive structure is residing in. As another example, the actual electrical resistance (or conductivity) associated with a memristive structure can be utilized in a neuronal network configuration to influence a data or signal processing.

In some aspects, a plurality of memristive structures may be arranged in a crossbar configuration. In such a crossbar configuration, a memristive material portion (also referred to as memristor or memristive device) can be addressed by a corresponding cross-point formed by input-lines and output-lines of the crossbar arrangement. Neuromorphic and/or analog computing technologies, only as examples, may utilize an ideal analog switching of a memristive structure.

<FIG> show various aspects of a memristive structure <NUM>. As illustrated in <FIG>, according to various aspects, the memristive structure <NUM> may include a first electrode <NUM> and a second electrode <NUM>. The first electrode <NUM> and/or the second electrode <NUM> may include any suitable electrically conductive material, e.g., Al, Cu, Ti, AlCu, TiN, W, Ta, only as examples. The memristive structure <NUM> may further include a memristive material portion <NUM> (e.g., a memristive element). The memristive material portion <NUM> may be disposed between the first electrode <NUM> and the second electrode <NUM>. Illustratively, the region in which the first electrode <NUM> and the second electrode <NUM> overlap one another may be (e.g., partially or completely) filled with memristive material. According to various aspects, the memristive material portion <NUM> may be in electrical contact and in direct physical contact with both the first electrode <NUM> and the second electrode <NUM>. Therefore, a dimension <NUM> (e.g., a height or a thickness) of the memristive material portion <NUM> may be defined by a distance 101d from the first electrode <NUM> to the second electrode <NUM>. The distance 101d from the first electrode <NUM> to the second electrode <NUM> may be understood as a shortest distance measure, for example, perpendicular to the planes in which the electrodes are formed. According to various aspects, the dimension (e.g., the height) of the memristive material portion <NUM> may be in a predefined range such that the memristive structure <NUM> has a substantially symmetric read characteristic and/or at least one curvature change in the read characteristic. The first electrode <NUM> and the second electrode <NUM> may be planar electrodes.

According to various aspects, the memristive structure <NUM> may be a memristive cross-point structure included in a memristive crossbar array. The first electrode <NUM> and the second electrode <NUM> may be each a portion of a corresponding crossbar control line. As an example, a crossbar array may include a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode <NUM> may be a portion of a first control line <NUM> of the set of first control lines and the second electrode <NUM> may be a portion of a second control line <NUM> of the set of second control lines, as illustrated in <FIG>. In this example, the memristive material portion <NUM> may be in direct physical contact with both the first control line <NUM> and the second control line <NUM>, and the memristive material portion <NUM> may be disposed between both the first control line <NUM> and the second control line <NUM>. Accordingly, a memristive structure <NUM> can be provided in each of various cross-point regions of the crossbar array.

In other aspects, the first electrode <NUM> may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a corresponding first control line (e.g., a first control line of a crossbar array) and the second electrode <NUM> may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a corresponding second control line (e.g., a second control line of a crossbar array). As an example, a crossbar array may include a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode <NUM> may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a first control line <NUM> of the set of first control lines and the second electrode <NUM> may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a second control line <NUM> of the set of second control lines, as illustrated in <FIG>. In this example, the memristive material portion <NUM> may not be in direct physical contact with the first control line <NUM> and the second control line <NUM>. But the first electrode <NUM> may be in direct physical contact with the first control line <NUM> and the second electrode <NUM> may be in direct physical contact with the second control line <NUM>. The first electrode <NUM>, the second electrode <NUM>, and the memristive material portion <NUM> may be disposed between the first control line <NUM> and the second control line <NUM>. Accordingly, a memristive structure <NUM> can be provided in each of various cross-point regions of a crossbar array.

According to various aspects, a crossbar array may define lateral (e.g., in plane) dimensions, e.g., along lateral directions <NUM>, <NUM> shown in the figures. As an example, each control line (e.g., first control line <NUM>) of a set of first control lines of the crossbar array may extend along a first lateral direction <NUM> and each control line (e.g., second control line <NUM>) of a set of second control lines of the crossbar array may extend along a second lateral direction <NUM>. The first lateral direction <NUM> may be perpendicular to the second lateral direction <NUM>. A height direction <NUM> may be perpendicular to the first lateral direction <NUM> and/or the second lateral direction <NUM>. The height direction <NUM> may be perpendicular to a planar surface of the first electrode <NUM> facing the memristive material portion <NUM> and/or perpendicular to a planar surface of the second electrode <NUM> facing the memristive material portion <NUM>.

The dimension <NUM> (e.g., a height or a thickness) of the memristive material portion <NUM> may be defined along a direction parallel to the height direction <NUM>. Accordingly, the distance 101d between the first electrode <NUM> and the second electrode <NUM> may be defined along a direction parallel to the height direction <NUM>. The dimension <NUM> of the memristive material portion <NUM> may be greater than <NUM>. Accordingly, the distance 101d from the first electrode <NUM> to the second electrode <NUM> may be greater than <NUM>.

As explained above, the first control line <NUM> and the second control line <NUM> may be in a crossbar configuration to allow for an electrical addressing of the memristive structure <NUM> (i.e., the memristive material portion <NUM>) via the first control line <NUM> and the second control line <NUM>. An electrical addressing of the memristive structure <NUM> may be used to read information stored in the memristive structure <NUM> and/or to write (e.g., store) information into the memristive structure <NUM>. In other words, an electrical addressing of the memristive structure <NUM> may be used to determine a state (e.g., a memristive state) in which the memristive structure <NUM> is residing and/or to set (e.g., keep or change) a (e.g., a memristive) state of the memristive structure <NUM>.

In some aspects, the memristive material portion <NUM> may be patterned. Since the electric field between the first electrode <NUM> and the second electrode <NUM> may be substantially formed in the overlap region between the respective electrodes <NUM>, <NUM>, it may be sufficient to provide the memristive material only in the overlap region to form the memristive material portion <NUM>, see, for example, <FIG>. In this case, according to various aspects, the memristive material portion <NUM> has an aspect ratio of greater than <NUM>, e.g., greater than <NUM>, greater than <NUM>, greater than <NUM>. The aspect ratio may be defined by the height (e.g., the dimension along the height direction <NUM>) of the memristive material portion <NUM> divided by a width (e.g., along one of the lateral directions <NUM>, <NUM>) of the memristive material portion <NUM>. A sufficiently great height of the memristive material portion <NUM> and therefore a comparatively high aspect ratio may be essential to provide a memristive material portion <NUM> with ideal analog read properties. However, since due to manufacturing aspects, it may be difficult to form such a memristive material portion <NUM> with a comparatively high aspect ratio, the memristive material portion <NUM> may be provided by a non-patterned layer of a memristive material and/or the memristive material portion <NUM> may have a greater lateral extension than the overlap region between the electrodes <NUM>, <NUM>. However, a sufficiently great height of the memristive material portion <NUM> may be realized in any cases to achieve ideal analog read properties.

Possible materials that can be used to form the memristive material portion <NUM> may be, for example, a ternary oxide, a quaternary oxide, and/or a quinary oxide. Examples for ternary oxides are perovskite oxides with a base structure ABO3 or bixbyite with a base structure of A2O3 or B2O3 or mixtures thereof. Further, mixtures may include different impurities at the A or B site. Examples of elements for A may include La3+, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yp, Lu, Ca, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, Ba, Cr, Pu (e.g., all <NUM>+ like La3+). Examples of elements for B may include Al3+, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn (e.g., all <NUM>+ like AI3+). Examples of impurities at the A site may include Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr Pu, Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, e.g., with a different valence than <NUM>+. Examples of impurities at the B site may include Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr, Pu, e.g., with a different valence than <NUM>+. Perovskite oxides may be present in different phases like for example a rhombohedral alpha phase, an orthorhombic beta phase, a hexagonal phase, and/or a cubic bixbyite phase. Examples of suitable crystalline materials may include the ternary oxides CaTiO3, BaTiO3, PbTiO3, LaNiO3, NdAlO3, and/or PrAlO3. The memristive material portion <NUM> may be or may include one or more of the following materials and/or material combinations: Al2O3/TaOx, SiOx:Ag/TiOx, TaO, HfAlyOx/TaO, Pr0.7Ca0.3MnO3 (PCMO), Si-In-Zn-O/ion gel, SilnZnO, SiN/TaN, SrFeO3, only as examples.

In some aspects, at least a portion of the memristive material portion <NUM> may be modified, e.g., to cause a vacancy doping V+ or V-. In some aspects, the memristive material portion <NUM> may include an n-type memristive material that has a positive vacancy doping V+, e.g. anion vacancy. In other aspects, the memristive material portion <NUM> may include a p-type memristive material that has a negative vacancy doping V-, e.g. cation vacancy. In the case that the memristive material that form the memristive material portion <NUM> is an oxide, e.g., BiFeyOx, the vacancy doping V+ may be cause by oxygen vacancies VO+. In some aspects, at least a portion of the memristive material portion <NUM> may be modified, e.g., to cause traps, T. Accordingly, the memristive material portion <NUM> may include traps T. As an example, the traps T may be caused by introduction of metal iones (e.g., titanium ions) into the memristive material. A function of the memristive material portion <NUM> may be understood in terms of movable vacancies V+ that can be locally trapped in regions of the memristive material portion <NUM>. The traps T may be introduced adjacent to the first electrode <NUM> and second electrode <NUM> and the movable vacancies V+ may selectively move either into the region adjacent to the first electrode <NUM> or into the region adjacent to the second electrode <NUM> and trapped there accordingly in an electric field. This may allow for generating selectively a Schottky-type diode either with maximum barrier height at the first electrode <NUM> or with maximum barrier height at the second electrode <NUM> such that the memristive structure <NUM> exhibit a nonlinear switching behavior and is self-rectifying.

A memristive structure (also referred to as memristive device, memristive element, resistive switch, memristor, memristor element, or memristor structure) may be regarded as an analog memristive structure in the case that the memristive structure exhibits a continuous change in current (e.g., in the read current Iread) when (e.g., linearly) ramping the applied voltage (e.g., from <NUM> V to +Vmax and from +Vmax to <NUM> V and from <NUM> V to -Vmax and from -Vmax to <NUM> V), as illustrated, for example, in <FIG>. This current may be associated with a current through the memristive structure <NUM>. In the following various aspects are described with reference to the memristive structure <NUM>; it is noted that this serves for illustration and that other memristive structures may be used accordingly.

Up to now, a memristive structure was set either into a high resistive state (HRS) or a low resistive state (LRS). This process of setting the memristive structure into the high resistive state (HRS) or the low resistive state (LRS) was often referred to as writing a memristive state of the memristive structure. However, it is found that the high resistive state (HRS) is always associated with changing memristive states, ms. In this case, aspects of an applied write signal (e.g., a maximum applied voltage value or a maximum applied current value, a shape of the write signal, etc.) may define the memristive state into which the memristive structure is written in (e.g., in the case of a voltage signal, the memristive state after reducing the voltage to <NUM> V). This curve associated with changing the memristive states may be denoted as transition curve. It is found that this transition curve is common for all memristive states. Further, it is found that each memristive state is associated with a corresponding resistance-characteristic curve such that information about the resistance-characteristic curve allows to conclude the memristive state the memristive structure is in. Hence, each resistance-characteristic curve may be unambiguously assigned to a respective memristive state, and vice versa. This resistance-characteristic curve may be independent on how the memristive structure was set into the corresponding memristive state. As described in the following, these findings allow to use less complex writing schemes as well as various kinds of reading schemes to read out the memristive state of the memristive structure <NUM>. The described writing and/or reading schemes allow, for example, to differentiate between more than <NUM> (e.g., more than <NUM>, e.g., more than <NUM>) different memristive states. Hence, as compared to two memristive states (HRS or LRS), the memristive structure <NUM> may be in one of more than <NUM> (e.g., more than <NUM>, e.g., more than <NUM>) memristive states enhancing the number of bits associated with the memristive structure <NUM> significantly. In the following, various reading schemes for reading out a memristive state are exemplarily described for the memristive structure <NUM>. It is understood that any memristive structure may be read using one or more of these reading schemes and that any kind of device which includes at least one memristive structure may employ any of these reading schemes. According to an example, the device may include a read circuit configured to read out the memristive state of the at least one memristive structure. According to another example, the device may be (e.g., for analysis) coupled to another device which is configured to apply a measurement signal to the memristive structure in order to read out the memristive state of the at least one memristive structure.

According to various aspects, a (e.g., measurement) signal may be applied to the memristive structure to set a memristive state and/or to read a prior set memristive state. The (e.g., measurement) signal may be, for example, a signal pulse. The memristive structure <NUM> may be addressed via a voltage-driven mode or a current-driven mode. In the case of the voltage-driven mode, a voltage signal (e.g., a voltage pulse) may be applied to the memristive structure <NUM> and an induced current through the memristive structure <NUM> may be determined (e.g., measured). In the case of the current-driven mode, a current signal (e.g., a current pulse) may be applied to the memristive structure <NUM> and an induced voltage may be determined (e.g., measured). Herein, various aspects of memristive structures and of various reading schemes are described for the voltage-driven mode (e.g., in the case of the shown IV-characteristics). It is noted that this serves for illustration and that other modes, such as the current-driven mode, can be used accordingly.

<FIG> shows a first exemplary ramping scheme 200a that can be used to set the memristive structure <NUM> into the high resistive state (HRS) and a second exemplary ramping schemes 200b that can be used to set the memristive structure <NUM> into a low resistive state (LRS). <FIG> shows an exemplary current/voltage (I/V) characteristic of the memristive structure <NUM> obtained via the two exemplary ramping schemes 200a, 200b, according to various aspects. <FIG> shows two equivalent circuits representing the electrical condition of a memristive structure for the HRS and the LRS. The memristive structure <NUM> may be in a self-rectifying configuration. The self-rectifying configuration and/or the desired switching behavior may be caused by a formation of a diode (e.g., a Schottky contact) and a resistor at the interfaces between the first electrode <NUM> and the memristive element <NUM> and between the second electrode <NUM> and the memristive element <NUM> (the memristive element <NUM> may be a memristive material portion). The diode and the resistor are coupled to one another in a series connection and provide the described HRS and LRS states for a defined polarity. The switching of the memristive structure <NUM> and therefore the presence of a diode-contact or a resistive contact at the respective electrode regions may be defined by the memristive material, e.g., by presence and/or absence of oxygen vacancies in the electrode regions.

It is understood that the IV-characteristics shown in <FIG> are exemplary and schematically serving for illustration and that the IV-characteristic of a memristive structure may be different. In particular, many different types of IV-characteristics are possible for various kinds of memristive structures (e.g., depending on the material, the size, the thickness of the layers, etc.). <NUM> to FIG. <NUM> each show an exemplarily measured IV-characteristic of a respective memristive structure.

Up to now, the memristive structure <NUM> may be set into a well-defined memristive state by applying an initialization voltage, Vini , (in some aspects referred to as programming voltage or write voltage) and subsequently applying a desired write voltage scheme to set a memristive state in which the memristive structure <NUM> is residing in after the write voltage has been applied.

As shown in <FIG>, the memristive structure <NUM> may be set into the low resistive state (LRS, branch <NUM>) by ramping the voltage from <NUM> V to +|Vmax | (branch <NUM>) and into low resistance state (LRS, branch <NUM>) by ramping the voltage from 0V to -|Vmax| (branch <NUM>). As shown in <FIG>, the memristive structure <NUM> may be set into the low resistive state (LRS, branch <NUM>) by ramping the voltage from <NUM> V to -|Vmax | (branch <NUM>) and into low resistance state (LRS, branch <NUM>) by ramping the voltage from 0V to +|Vmax| (branch <NUM>). The resistance state in branch <NUM> and in branch <NUM> in <FIG> can be determined by applying a read voltage that is less than the write voltage and has the same polarity as the write voltage, i.e. positive polarity in branch <NUM> and negative polarity in branch <NUM>. The resistance state in branch <NUM> and in branch <NUM> in <FIG> may be determined by applying a read voltage (value) that is smaller than the write voltage (value) and has the same polarity as the write voltage (value), i.e. a negative polarity in branch <NUM> and positive polarity in branch <NUM>. In this case, the state of the memristive structure <NUM> may be read out by applying a positive read voltage having a voltage value between about <NUM> V and about +Vmax. Depending on the state of the memristive structure <NUM>, the applied read voltage always causes a larger current flow associated with low resistance state in comparison to the small current flow flowing during application of the write voltage. Here, the voltage, V, may be ramped up to a maximum positive voltage value, +Vmax, and up to a maximum negative voltage value, -Vmax. In an example, the respective maximum voltage, |Vmax |, may be the highest voltage that can be applied such that no breakdown (e.g., of the diode described with reference to <FIG>) occurs. In another example, the respective maximum voltage, |Vmax |, may have any voltage value different from <NUM>. However, as described above, these complex writing schemes may not be necessary by employing the findings that the high resistive state (HRS) is always associated with changing memristive states (branches <NUM> and <NUM> in <FIG> and branches <NUM> and <NUM> in <FIG>) and that each memristive state is associated with a corresponding resistance-characteristic curve (branches <NUM> and <NUM> in <FIG> and branches <NUM> and <NUM> in <FIG>).

The IV-characteristics may show ferroelectric and interface switching current. Exemplary IV-characteristics which include ferroelectric and/or interface switching effects are shown in <FIG> as obtained via the first exemplary ramping scheme 200a and via the second exemplary ramping scheme 200b. According to various aspects, these effects may be subtracted from the IV-characteristics. For example, the ferroelectric current may be subtracted from the IV-characteristics to obtain corrected IV-characteristics. <FIG> exemplarily shows a ferroelectric current <NUM> which may be subtracted from the IV-characteristics shown in <FIG> to obtain the corrected IV-characteristics <NUM>. <FIG> shows the corresponding electric field vs. polarization behavior. In contrast to ferroelectric switching, when using barrier switching information about properties can be obtained by means of the polarity of the voltage signal.

<FIG> shows a schematic IV-characteristic of the memristive structure <NUM> exemplarily for the first quadrant of the IV-diagram. The following description may apply similarly to the third quadrant. For example, the first quadrant and the third quadrant may be associated with a respective transition curve. Also, the first quadrant (i.e., positive applied voltages) may be associated with a plurality of (positive) memristive states and the third quadrant (i.e., negative applied voltages) may be associated with a plurality of (negative) memristive states. It is understood that, in some aspects, the described behavior may be only present in either the first quadrant or the third quadrant. <FIG> also shows a voltage signal scheme including writing (dashed lines) as well as reading (solid lines) memristive states.

As exemplarily shown for the first quadrant, the transition curve <NUM> (branch <NUM>) may be associated with changing the resistivity of the memristive structure <NUM> (e.g., via moving traps T), thereby changing the memristive state, ms. Each current-voltage (I-V) data point, I(V), on the transition curve <NUM> may be associated with a corresponding memristive state, <NUM> ≤ ms ≤ M (with M being any integer number equal to or greater than one (e.g., equal to or greater than <NUM>, e.g., equal to or greater than <NUM>, etc.), of the memristive structure <NUM>. This transition curve <NUM> may be associated with the HRS state. As described herein, it is found that, when setting the memristive structure into a respective memristive state, this transition curve <NUM> is similar for all memristive states (since each data point of the transition curve <NUM> corresponds to a respective memristive state). Hence, a memristive structure <NUM> has one transition curve <NUM> (transitioning from a lowest memristive state, ms = <NUM>, over various intermediate memristive states to a highest memristive state, ms = M). For illustration, the transition curve <NUM> is herein shown (substantially) linearly. It is understood that the transition curve <NUM> may have any course depending the memristive structure. <FIG> shows an IV-characteristic measured for a manufactured memristive structure illustrating that the transition curve <NUM> can have a substantially linear course. However, it is noted that there may be a highest memristive state, ms = M, associated with a corresponding voltage value. Within the same quadrant (e.g., the first or the third quadrant), the memristive states (from ms = <NUM> to ms = M-<NUM>) between the lowest memristive state, ms = <NUM>, and the highest memristive state, ms = M, may be referred to as intermediate memristive states. When applying a voltage having a voltage value greater than the voltage value corresponding to the highest memristive state, ms = M, the memristive structure <NUM> may be set into the highest memristive state. In this case, the transition curve <NUM> may, at the voltage value corresponding to the highest memristive state, (e.g., slowly) change from the linear behavior into saturation (hence a substantially stable current). It is understood that by further increasing the voltage value beyond that saturation regime, the current value may increase significantly due to the diode character of the memristive structure <NUM> (hence, a breakthrough of the Schottky-type diode).

As described herein, each memristive state (thus, each data point, I(V)), on the transition curve <NUM>) may be associated with (e.g., unambiguously assigned to) a corresponding resistance-characteristic curve (branch <NUM> in the case of the branch <NUM> transition curve or branch <NUM> in the case of the branch <NUM> transition curve) (as understood up to the highest memristive state). This resistance-characteristic curve may be characteristic for a corresponding memristive state (hence characteristic for the resistance corresponding to the memristive state). A resistance-characteristic curve may be understood as a respective characteristic LRS curve for each memristive state. <FIG> schematically shows a first resistance-characteristic curve <NUM> (e.g., a first LRS curve) corresponding to a first memristive state, a second resistance-characteristic curve <NUM> (e.g., a second LRS curve) corresponding to a second memristive state different from the first memristive state, and a third resistance-characteristic curve <NUM> (e.g., a third LRS curve) corresponding to a third memristive state different from both, the first memristive state and the second memristive state. <FIG> shows the common transition curve <NUM> (HRS curve) and a corresponding (individual) resistance-characteristic curve (hence, a respective LRS curve) for five different memristive states set via a respective programming voltage (<NUM> V, <NUM>,<NUM> V, <NUM> V, <NUM>,<NUM> V, and <NUM> V).

Thus, depending on the memristive state the memristive structure resides in, the IV-characteristic may follow the transition curve <NUM> (in the case of changing the memristive state) or may follow the resistance-characteristic curve corresponding to a current memristive state (in the case of keeping (i.e., not changing) the memristive state). Hence, a measured IV-characteristic may depend on a current memristive state of the memristive structure <NUM>. To program a memristive state and/or to determine the current memristive state of the memristive structure <NUM>, a (e.g., measurement) signal may be applied to the memristive structure <NUM>. For example, the measurement signal may be a measurement pulse (e.g., a voltage pulse or a current pulse).

As detailed above, herein the measurement source/input signal (short measurement signal) is described as voltage pulse for illustration and the measurement output signal is described as corresponding current pulse for illustration. Exemplary courses and shapes of one or more voltage pulses are shown in <FIG>. For simplicity, the voltage pulses are shown rising from and falling to <NUM> V as base voltage. It is understood that the base voltage may have any suitable voltage value. According to some aspects, the voltage may be applied to one of the first electrode <NUM> or the second electrode <NUM> and that the base voltage may be applied to the other one of the first electrode <NUM> or the second electrode <NUM>. According to other aspects, a respective voltage (different from the base voltage) may be applied the first electrode <NUM> and to the second electrode <NUM>. In this case, the voltage values of herein described voltages (e.g., the maximum positive read voltage value, +Vread,max, the maximum negative read voltage value, +Vread,max, etc.) may be voltage drops over the memristive structure <NUM> (hence a voltage difference between the voltage applied at the first electrode <NUM> and the voltage applied at the second electrode <NUM>).

As shown, a voltage pulse may have a linear triangular course (see, for example, <FIG>), a stepwise triangular course (see, for example, <FIG>), a sinusoidal course (see, for example, <FIG>), or an exponentially falling/rising course (see, for example, <FIG>), as examples. It is understood that any other course and/or shape may be used. Even though these voltage pulses are described as read signals, it is understood that a write signal may have a similar course and/or shape. A voltage pulse may be characterized by a rising edge from the base voltage (e.g., <NUM> V) to a maximum read voltage value and a falling edge from the maximum read voltage value to the base voltage (e.g., <NUM> V). For example, a first voltage pulse may be characterized by a rising edge <NUM> from the base voltage (e.g., <NUM> V) to a maximum positive read voltage value, +Vread,max , and a falling edge <NUM> from the maximum positive read voltage value, +Vread,max , to the base voltage (e.g., <NUM> V). A second voltage pulse may be characterized by a rising edge <NUM> from the base voltage (e.g., <NUM> V) to a maximum negative read voltage value, -Vread,max , and a falling edge <NUM> from the maximum negative read voltage value, -Vread,max , to the base voltage (e.g., <NUM> V). A rising edge may be associated with (e.g., continuously) increasing (e.g., ramping) a voltage up to up to the maximum (positive or negative) voltage value (different from zero volts). According to various aspects, only one voltage pulse (e.g., the first voltage pulse or the second voltage pulse) may be applied. According to other aspects, the first voltage pulse and the second voltage pulse may be (in any order) applied subsequent to each other. In this case, the first voltage pulse and the second voltage pulse may be (in any order) applied directly subsequent to each other or there may be a time delay between them.

As described herein, a measured IV-characteristic (e.g., branch <NUM> and/or branch <NUM>) depend on a current (i.e., an actual or present) memristive state of the memristive structure <NUM>. This memristive state of the memristive structure <NUM> may depend on a prior applied measurement signal (in the present example a prior applied voltage signal). The memristive state may be set by applying a programming voltage pulse. For simplicity, in the following, the maximum voltage (in some aspects referred to as programming voltage) of the programming voltage pulse is considered as defining the memristive state the memristive structure <NUM> is set into. However, it is noted that the memristive state into which the memristive structure <NUM> is set by applying the programming voltage pulse may also depend on other aspects, such as the shape and/or course of the programming voltage pulse.

Hence, the current/voltage (I/V) characteristic of the memristive structure <NUM> can depend on a prior applied voltage value, Vprior , associated with a prior applied voltage. <FIG> schematically show a respective IV-characteristic depending on the prior applied voltage value, Vprior , for the memristive structure <NUM> having the IV-characteristic shown in <FIG>. In the case that a prior voltage has a negative voltage value (i.e., Vprior < <NUM>), the memristive structure <NUM> resides either in a (negative) memristive state associated with the third quadrant (i.e., a negative voltage value and a negative current value) since the negative voltage would either write a (negative) memristive state associated with the third quadrant (e.g., in the case that the memristive structure <NUM> is in a memristive state associated with the first quadrant or in a memristive state associated with a negative voltage value having an absolute value less than the voltage value of the applied negative voltage) or would keep the (negative) memristive state in the case that the memristive structure <NUM> is in a (negative) memristive state associated with a negative voltage value having an absolute value greater than the voltage value of the applied negative voltage. When applying a first read voltage pulse (e.g., having a shape and/or course as shown in <FIG>, <FIG>) with a first voltage value, V<NUM> , as maximum positive read voltage value, +Vread,max , the rising edge <NUM> of the first read voltage pulse (continuously) changes the memristive state, ms , (over the memristive states starting from ms = <NUM>) until setting the memristive structure <NUM> into the memristive state ms = ms (V<NUM> ) associated with the first voltage value, V<NUM> (see <FIG>). Hence, the IV-characteristic follows the transition curve <NUM> during the rising edge <NUM> of the first read voltage pulse. The falling edge <NUM> of the first read voltage pulse keeps (i.e., does not change) the set (e.g., written) memristive state ms = ms (V<NUM> ) since the voltage value is reduced (and not further increased). Hence, the IV-characteristic follows the first resistance-characteristic curve <NUM> associated with the first voltage value, V<NUM> , during the falling edge <NUM> of the first read voltage pulse. When applying a (subsequent) second read voltage pulse (having the same polarity as the first read voltage pulse) with another voltage value, V<NUM> , (being less than the first voltage value, V<NUM> ,) as maximum positive read voltage value, +Vread,max , the rising edge <NUM> of the second read voltage pulse keeps (i.e., does not change) the memristive state ms = ms (V<NUM>) (see <FIG>). Therefore, the rising edge <NUM> of the second read voltage pulse follows the first resistance-characteristic curve <NUM> associated with the first voltage value, V<NUM>. When applying a third read voltage pulse (having the same polarity as the first read voltage pulse) with the first voltage value, V<NUM> , as maximum positive read voltage value, +Vread,max, the rising edge <NUM> of the third read voltage pulse keeps (i.e., does not change) the memristive state ms = ms (V<NUM>) up to the first voltage value, V<NUM> (see <FIG>). Therefore, the rising edge <NUM> of the third read voltage pulse follows the first resistance-characteristic curve <NUM> associated with the first voltage value, V<NUM> , up to the first voltage value, V<NUM>. When applying a fourth read voltage pulse (having the same polarity as the first read voltage pulse) with a second voltage value, V<NUM> , (being greater than the first voltage value, V<NUM> ,) as maximum positive read voltage value, +Vread,max , the rising edge <NUM> of the second read voltage pulse keeps (i.e., does not change) the memristive state ms = ms (V<NUM> ) up to the first voltage value, V<NUM> (see <FIG>). Therefore, the rising edge <NUM> of the second read voltage pulse follows the first resistance-characteristic curve <NUM> associated with the first voltage value, V<NUM> , up to the first voltage value, V<NUM>. Once the voltage value of the rising edge <NUM> surpasses (hence, is greater than) the first voltage value, V<NUM> , the memristive state ms of the memristive structure <NUM> is (continuously) changed (starting from the memristive state ms = ms (V<NUM> ) to the memristive state ms = ms (V<NUM> ). Hence, from the first voltage value, V<NUM> , to the second voltage value, V<NUM> , the rising edge <NUM> of the fourth read voltage pulse follows the transition curve <NUM>. The falling edge <NUM> of the fourth read voltage pulse keeps (i.e., does not change) the set (e.g., written) memristive state ms = ms (V<NUM> ) since the voltage value is reduced. Hence, the IV-characteristic follows the second resistance-characteristic curve <NUM> associated with the second voltage value, V<NUM> , during the falling edge <NUM> of the fourth read voltage pulse. This applies similar to applying any read voltage pulse having a greater voltage value (up to the highest voltage value) than a prior applied read voltage pulse. Hence, when applying a (subsequent) fifth read voltage pulse (having the same polarity as the second read voltage pulse) with a third voltage value, V<NUM> , (being greater than the second voltage value, V<NUM> ,) as maximum positive read voltage value, +Vread,max , the IV-characteristic of the memristive structure <NUM> follows the second resistance-characteristic curve <NUM> associated with the second voltage value, V<NUM> , up to the second voltage value, V<NUM> during the rising edge <NUM> of the fifth read voltage pulse and follows the transition curve <NUM> from the second voltage value, V<NUM> , to the third voltage value, V<NUM>. The falling edge <NUM> of the fifth read voltage pulse keeps the set memristive state ms = ms (V<NUM> ) and the IV-characteristic, therefore, follows the third resistance-characteristic curve <NUM> associated with the third voltage value, V<NUM>.

According to various aspects, a memristive state of the memristive structure <NUM> may be read either non-destructively (while keeping the memristive state, see, for example, <FIG>) or destructively (which includes changing the memristive state, see, for example, <FIG>).

In the case of a non-destructive read, the memristive structure <NUM> may reside in a memristive state, ms (+Vprogram ), associated with a positive programming voltage value, +Vprogram , equal to or greater than the maximum read voltage value, +Vread,max , of the read voltage pulse. In this case, as described herein (e.g., regarding <FIG>), the rising edge <NUM> of the read voltage pulse causes a current through the memristive structure <NUM> according to the resistance-characteristic curve corresponding to the memristive state, ms (+Vprogram ). Hence, applying the read voltage pulse may keep the memristive state, ms (+Vprogram ), associated with the positive programming voltage. This allows, for example, to read the memristive state, ms (+Vprogram ), of the memristive structure <NUM> multiple times as long as the respective maximum read voltage value, +Vread,max , of each read voltage pulse is equal to or lower than the positive programming voltage value, +Vprogram (and of course within the same quadrant, i.e., having the same polarity). When ramping the read voltage in a range between the base voltage (e.g., <NUM> V) and the maximum read voltage value, +Vread,max , less than the programming voltage value, +Vprogram , also the falling edge <NUM> of the read voltage pulse causes a current according to the resistance-characteristic curve corresponding to the memristive state, ms (+Vprogram ), (since the memristive state is not changed by the maximum read voltage value, +Vread,max). It is understood that, in this example, no negative voltages may be applied since, as described herein, a negative voltage would write a memristive state in the third quadrant of the IV characteristic.

In the case of a destructive read, the memristive structure <NUM> may reside in a memristive state, ms (+Vprogram ), associated with a positive programming voltage value, +Vprogram , less than the maximum read voltage value, +Vread,max , of the read voltage pulse. In this case, as described herein (e.g., regarding <FIG>), the rising edge <NUM> of the read voltage pulse causes, once the voltage value surpasses the positive programming voltage value, +Vprogram , a current through the memristive structure <NUM> according to the transition curve (e.g., transition curve <NUM>). Hence, applying the read voltage pulse may change the memristive state from the memristive state, ms (+Vprogram ), associated with the positive programming voltage to the memristive state, ms (+Vread,max ), associated with the maximum read voltage value, +Vread,max.

<FIG> shows a reading scheme <NUM> for (e.g., non-destructively or destructively) reading a memristive state <NUM> of the memristive structure <NUM> according to various aspects. A read circuit <NUM> (in some aspects referred to as read-out circuit) may be configured to read (out) the memristive state <NUM> of a respective memristive structure (e.g., a memristive structure of a plurality of memristive structures in a crossbar array). The read circuit <NUM> may be configured to apply a read signal (e.g., a read voltage pulse or a read current pulse, as described herein) to the memristive structure <NUM>.

As described, the memristive state <NUM> may be read non-destructively (e.g., the memristive structure <NUM> may reside in a memristive state, ms (+Vprogram ), associated with a positive programming voltage value, +Vprogram , equal to or greater than the maximum read voltage value, +Vread,max , of the read voltage pulse.

According to various aspects, the read circuit <NUM> may (in <NUM>) be configured to measure a respective read current value at at least two (e.g., exactly two, three, or more than three) different voltage values. In the following, the read out is described exemplarily for exactly two different voltage values; however, it is noted that any number of different voltage values may be used. The read circuit <NUM> may be configured to measure the respective current value at the (at least) two different voltage values within the same read voltage pulse and/or within two separate (e.g., subsequent) read voltage pulses. According to an example, the read circuit <NUM> may be configured to measure a first read current value, Iread1 , at a first read voltage value, Vread1 , and a second read current value, Iread2 , at a second read voltage value, Vread2 , during applying a single read voltage pulse. According to another example, the read circuit <NUM> may be configured to measure the first read current value, Iread1 , at the first read voltage value, Vread1 , during applying a first read voltage pulse and to measure the second read current value, Iread2 , at the second read voltage value, Vread2 , during applying a second read voltage pulse. The first read voltage value, Vread1 , may be any voltage value between the base voltage (e.g., <NUM> V) and the maximum read voltage, Vread,max , of the first read voltage pulse and the second read voltage value, Vread2 , may be any voltage value between the base voltage (e.g., <NUM> V) and the maximum read voltage, Vread,max , of the second read voltage pulse as long as the second read voltage value, Vread2 , is different from the first read voltage value, Vread1. The maximum read voltage, Vread,max , of the first read voltage pulse and the maximum read voltage, Vread,max , of the second read voltage pulse may have the same or different voltage values. The application of a read voltage pulse and the determination (e.g., measurement) of a respective read current value (e.g., by measuring a voltage responsive to integrating a current) at two or more (e.g., different) read voltage values may be referred to as a read-out operation. Hence, the read circuit <NUM> may be configured to determine (e.g., measure) the first read current value, Iread1 , via a first measurement and the second read current value, Iread2 , via a second measurement during a single read-out operation. As described herein, a current value may be determined by directly measuring a current value or by measuring a voltage value representing the current value. For example, one or more integrators may integrate the current (over time) and output a voltage value representing the integrated current. The current value may then be determined using the voltage value representing the integrated current. According to other aspects, as an alternative to using the IV-characteristics described herein, a functional correlation between the voltage representing the integrated current and the read voltage may be used.

In the case that the read voltage of the read voltage pulse is in the range between the base voltage (e.g., <NUM> V) and the programming voltage value, +Vprogram , both, the rising edge <NUM> and the falling edge <NUM> of the read voltage pulse cause a current according to the resistance-characteristic curve <NUM> corresponding to the memristive state, ms (+Vprogram ), (since the memristive state is not changed). Hence, the first read current value, Iread1 , and/or the second read current value, Iread2 , may be measured on the rising edge <NUM> and/or the falling edge <NUM> of the read voltage pulse. According to an example, both, the first read current value, Iread1 , and the second read current value, Iread2 , may be measured during the rising edge <NUM> or the falling edge <NUM> of the read voltage pulse. According to another example, the first read current value, Iread1 , may be measured during the rising edge <NUM> of the read voltage pulse and the second read current value, Iread2 , may be measured during the falling edge <NUM> of the read voltage pulse, or vice versa.

In the case of a destructive read, both, the first read current value, Iread1 , and the second read current value, Iread2 , may be measured during the rising edge <NUM> of the read voltage pulse (since, during the falling edge <NUM>, the IV-characteristic may follow the resistance-characteristic curve of the newly set memristive state, ms (+Vread,max )).

As described herein, the resistance-characteristic curve may be characteristic for a respective memristive state, thereby allowing to determine the memristive state based on information regarding (e.g., by knowing) the resistance-characteristic curve (such as the first current value and the second current value). The read circuit <NUM> may be configured to determine the memristive state <NUM> using the first read current value, Iread1 , and the second read current value, Iread2.

According to various aspects, the reading scheme may include a programming circuit (e.g., a write circuit) configured to set (e.g., write) the memristive structure <NUM> into a memristive state (e.g., by applying the programming voltage).

<FIG> shows a reading scheme <NUM> for destructively reading the memristive state <NUM> of the memristive structure <NUM> (i.e., by changing the memristive state) according to various aspects. According to some aspects, the first read current value, Iread1 , and the second read current value, Iread2 , may be measured during the rising edge <NUM> of the read voltage pulse at the first voltage value, Vread1 , and the second voltage value, Vread2 , less than a destruction voltage, Vdes. The destruction voltage, Vdes , may substantially correspond to the programing voltage, +Vprogram. Hence, voltage values higher than the destruction voltage, Vdes , may change the memristive state of the memristive structure <NUM>. Thus, the first read current value, Iread1 , and the second read current value, Iread2 , may be measured during the rising edge <NUM> of the read voltage pulse at the resistance-characteristic curve <NUM> associated with the memristive state, ms (+Vprogram ) priorly set by applying the programming voltage, +Vprogram. Additionally or alternatively, the read circuit <NUM> may be (e.g., in <NUM>) configured to determine the destruction voltage, Vdes (and optionally also the destruction current, Ides , corresponding to the destruction voltage, Vdes ). For example, the read circuit <NUM> may (e.g., continuously) measure the current through the memristive structure <NUM> as a function of the applied voltage and may determine the change of the slope of the measured current curve (e.g., from the resistance characteristic curve <NUM> to the (e.g., linear) transition curve <NUM>). Since the destruction voltage, Vdes , may substantially correspond to the programing voltage, +Vprogram , the read circuit <NUM> may be configured to determine the memristive state as ms (+Vdes ).

In the case of a non-destructive read, the programming voltage values (which may be used to set a respective memristive state) may be within a predefined programming voltage range. Hence, in order to non-destructively read the memristive state <NUM>, the maximum read voltage, Vread,max , has to be equal to or lower than a lower boundary of the predefined programming voltage range. This may limit both, the predefined programming voltage range and the range for the maximum read voltage, Vread,max. Hence, a limited predefined programming voltage range may also limit the number of possible memristive states the memristive structure <NUM> can be set into. On the other hand, the non-destructive read allows to read the memristive structure <NUM> multiple times and/or within different parts of the read voltage pulse (e.g., during the rising edge <NUM> and the falling edge <NUM>) and/or within different read voltage pulses. Even though a destructive read only allows to read the memristive state at the rising edge <NUM> of the read voltage pulse, the destructive read does not limit the maximum read voltage value, Vread,max , to be lower than the lower boundary of the predefined programming voltage range. This allows to use an increased range for the programming voltage, thereby increasing the number of possible memristive states.

<FIG> shows a reading scheme <NUM> for (e.g., non-destructively or destructively) reading the memristive state <NUM> of the memristive structure <NUM> according to various aspects. The read circuit <NUM> may be configured to determine (e.g., measure) a current/voltage (IV) characteristic of the memristive element <NUM>. For example, the read circuit <NUM> may be configured to measure (in <NUM>) at least a part (e.g., within a predefined voltage range) of the resistance-characteristic curve (current-voltage) <NUM> corresponding to the memristive state, ms (+Vprogram ), the memristive structure <NUM> resides in. The read circuit <NUM> may be configured to measure the (e.g., part of the) resistance-characteristic curve <NUM> by measuring a respective current value at a plurality of voltage values (e.g., at predefined voltage steps or in predefined time steps). For example, the read circuit <NUM> may be configured to apply a read voltage sequence to the memristive structure <NUM> to cause a corresponding current sequence through the memristive structure <NUM> and to measure (e.g., in predefined time steps or predefined voltage steps) current values of the caused corresponding current sequence.

According to various aspects, the read circuit <NUM> may be configured to fit (in <NUM>) the (e.g., measured) resistance-characteristic curve <NUM> (e.g., to determine a fitting curve <NUM>). The read circuit <NUM> may be configured to fit the resistance-characteristic curve <NUM> by a physical model. The physical model may be based on one or more static state parameters. The read circuit <NUM> may be configured to determine a respective static state parameter value for at least one (e.g., each) of the one or more static state parameters. Hence, the read circuit <NUM> may be configured to determine one or more static state parameter values <NUM>. Even though the fitting of the resistance-characteristic curve <NUM> and the determination of the one or more static state parameter values is described herein as being carried out by the read circuit <NUM>, it is understood that any other kind of processor may be used to carry these processes.

A "static state parameter", as used herein, may describe (e.g., physical, electrical, chemical, etc.) properties (or other manufacturing-related properties) of a memristive structure. Thus, the static state parameter(s) may be correlated to (memristor) properties of the memristive structure. A "static state parameter value", as used herein, may a value of such a static state parameter. The static state parameter value may be indicative of (e.g., unambiguously assigned to) the memristive state, ms , the memristive structure resides in. Hence, the static state parameter(s) may characterize the memristive states of the memristive structure and a value of the static state parameter(s) (i.e., the static state parameter value(s)) may be "static" for a respective memristive state.

According to the invention, the physical model (e.g., used for fitting the resistance-characteristic curve <NUM>) is given by: <MAT> wherein: V is the applied read voltage, I is the current through the memristive structure responsive to applying the read voltage, kB is the Boltzmann constant, T is the temperature of the memristive structure, q is the electron charge, and A, B, C, and D each is a respective static state parameter. Hence, in this example, the physical model may include four static state parameters. It is understood that the static state parameters do not change when a respective resistance-characteristic curve of branch <NUM> and/or branch <NUM> is measured.

The static state parameter A may represent an ideality of the memristive structure <NUM>. For example, an ideality factor, n, may be given by n = A(<NUM> + C * Videal). The ideal voltage, Videal, may be given by: <MAT>.

According to an example, the static state parameter B may represent a reverse saturation current, IS, through the memristive structure <NUM> responsive to applying the read voltage. The reverse saturation current, IS, may be substantially proportional to <MAT>. The static state parameter D may represent a series resistance, RS, of the memristive structure <NUM>. The series resistance, RS, may be given by: <MAT> , wherein Rmax is a maximum resistance and Rmin a minimum resistance of the memristive structure <NUM>, and wherein Imax is a maximum current through the memristive structure <NUM>. <FIG> shows measured IV-characteristics for four different memristive structures <NUM>, <NUM>, <NUM>, <NUM> and respectively determined static state parameters using the above physical model (with A=n<NUM>, B=IS, C=K, and D=RS).

According to another example, the static state parameter B may represent a ratio ( <MAT>) between the reverse saturation current, IS, and an area, Amem, of the memristive structure <NUM>. The static state parameter D may represent a product (RS * Amem) of the reverse saturation current, IS, and the area, Amem, of the memristive structure <NUM>. In this example, the physical model may model the current density as a function of the voltage. <FIG> shows current density-voltage-characteristics for the four different memristive structures <NUM>, <NUM>, <NUM>, <NUM> of <FIG> and respectively determined static state parameters using the above physical model (with A=n<NUM>, <MAT>, C=K, and D=RS * Amem).

As described above, <FIG> shows a corresponding (individual) resistance-characteristic curve for five different memristive states set via a respective programming voltage (<NUM> V, <NUM>,<NUM> V, <NUM> V, <NUM>,<NUM> V, and <NUM> V). <FIG> shows the static state parameter D being the series resistance, RS, and the static state parameter B being the reverse saturation current, IS, respectively determined for each of these five different memristive states using the above physical model. As illustratively shown, the static state parameters have a substantially linear behavior and characterize physical properties of the memristive structure.

In the following, with reference to <FIG>, various processing schemes are described which employ the determined one or more static state parameter values <NUM>. At least a part of the processing may be carried out by at least one processor <NUM>.

The term "processor", as used herein, may be understood as any kind of entity capable to process data and/or signals. For example, the data or signals may be handled according to at least one (i.e., one or more than one) specific function performed by the processor. A processor may include or may be an analog circuit, a digital circuit, a mixed signal circuit, a logic circuit, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a programmable gate array (FPGA), an integrated circuit, or any combination thereof. Any other method of implementing the respective functions, described herein, may also be understood to include a processor or logic circuit. It is understood that one or more of the method steps described in detail herein may be carried out (e.g., implemented) by a processor, through one or more specific functions performed by the processor. The processor may therefore be arranged to carry out any of the information processing methods or components thereof described herein.

According to the processing scheme <NUM> shown in <FIG>, the at least one processor <NUM> may be configured to select (e.g., initially select or adapt), using the one or more static state parameter values <NUM>, one or more operating parameters <NUM> associated with an operation of the memristive structure <NUM> (e.g., as a function of the determined static state parameter values). For example, the processing scheme <NUM> may include an analysis of one or more memristive structures (e.g., a plurality of memristive structures of a device). This analysis may include the determination of the one or more static state parameter values <NUM>. Sine these one or more static state parameter values <NUM> represent respective (e.g., physical and/or electrical) properties of the one or more memristive structures, this allows to select corresponding operating parameters <NUM> at which the one or more memristive structures may be operated. Such operating parameters <NUM> may be, for example, a read voltage, a programming (e.g., write) voltage, a read current, a programming (e.g., write) current, and/or an operating temperature. As shown above, the physical model may depend on the temperature of the memristive structure. Knowing the respective values of the static state parameter(s) allows, for example, to determine a current-voltage characteristic at another temperature value. For example, this allows to simulate the behavior of the memristive structure at another (e.g., non-measured) temperature (see, for example, description with reference to <FIG>). According to some aspects, the static state parameter values <NUM> may be determined during use of the device which includes the one or more memristive structures. In this case, the operating parameters <NUM> used for operating the one or more memristive structures may be adapted based on the one or more static state parameter values <NUM>. For example, some (e.g., physical, electrical, chemical, etc.) properties of the memristive structure may change over time. Using the physical model to determine the one or more static state parameter values <NUM> may allow to determine such a change and, therefore, allows to adapt the operating parameters <NUM> to the changed properties. This may increase the lifetime, accuracy, reliability, etc. of the device.

According to the processing scheme <NUM> shown in <FIG>, the at least one processor <NUM> may be configured to carry out a simulation <NUM> using the one or more static state parameter values <NUM>. The simulation <NUM> may be a simulation of the behavior of a memristive circuit including one or more memristive structures. These one or more memristive structures may be configured in accordance with the memristive structure <NUM> for which the one or more static state parameter values <NUM> are determined. This kind of simulation may be referred to as electronic circuit simulation. Hence, the static state parameter values <NUM> may be measured for a manufactured memristive structure and then the behavior of a memristive circuit, which includes one or more (e.g., a plurality of) such memristive structures, is simulated (in <NUM>). For example, the simulation <NUM> may include varying one or more simulation parameters associated with an operation of the memristive circuit. These simulation parameters may, for example, include a temperature of the memristive circuit (or optionally a respective temperature for each memristive structure of the memristive circuit), a programming (e.g., write) voltage for setting a memristive state, a programming (e.g., write) current for setting a memristive state, a read voltage for reading the memristive state of the memristive structure, a read current for reading the memristive state of the memristive structure, a desired current through the memristive structure responsive to applying a corresponding read voltage (pulse), and/or a desired voltage drop over the memristive structure responsive to applying a corresponding read current (pulse). As an example, the one or more static state parameter values <NUM> of the manufactured memristive structure may be measured at a first temperature value and the simulation <NUM> may simulate the behavior of the memristive circuit at a second temperature value different from the first temperature value (e.g., using the herein described physical model). According to various aspects, each static state parameter value of the one or more static state parameter values <NUM> may be associated with a respective error. Here, the simulation <NUM> of the behavior of the memristive circuit may be carried out in consideration of the respective error (e.g., as noise) of the determined static state parameter values <NUM>. According to various aspects, the determined one or more static state parameter values <NUM> may be verified by measuring the corresponding (physical) parameter underlying the respective static state parameter. For example, a respective state parameter value of the one or more static state parameter values <NUM> may be verified in the case that a difference between the measured value of the parameter and the determined static state parameter value is less than a predefined verification value. According to various aspects, the at least one processor <NUM> may be configured to determine a respective functional correlation between the one or more static state parameter values <NUM> and the memristive states, ms (e.g., as shown in <FIG>). The simulation <NUM> may include extrapolating this functional correlation. This allow, for example, to simulate a respective resistance-characteristic curve for each (e.g., non-measured) memristive state.

According to the processing scheme <NUM> shown in <FIG>, the at least one processor <NUM> may be configured to carry out the simulation <NUM> (e.g., including varying the one or more simulation parameters associated with the operation of the memristive circuit) using the one or more static state parameter values <NUM> and to determine the one or more operating parameters <NUM> for operation of the memristive circuit based on a result of the simulation <NUM>.

According to the processing scheme <NUM> shown in <FIG>, the at least one processor <NUM> may be configured to carry out a validation <NUM> of at least one memristive structure (e.g., for each memristive structure of a memristive circuit including a plurality of memristive structures) using the one or more static state parameter values <NUM>. Each static state parameter may be associated with a respective predefined validation range of static state parameter values.

The at least one processor <NUM> may be configured to determine, for at least one static state parameter value determined for the at least one memristive structure, whether the at least one static state parameter value is within the predefined validation range associated with the static state parameter. The at least one processor <NUM> may be configured to validate the at least one memristive structure in the case that the at least one static state parameter value is within the predefined validation range associated with the static state parameter.

According to various aspects, the at least one processor <NUM> may be configured to respectively determine, for each static state parameter value determined for the at least one memristive structure, whether the static state parameter value is within the predefined validation range associated with the static state parameter. The at least one processor <NUM> may be configured to validate the at least one memristive structure in the case that each static state parameter is within the respective predefined validation range. Hence, if at least one static state parameter is not within the predefined validation range, the at least one processor <NUM> may not validate (e.g., invalidate) the at least one memristive structure.

According to various aspects, a memristive circuit may include a plurality of memristive structures. The at least one processor <NUM> may be configured to determine respective one or more static state parameter values <NUM> for each memristive structure of the plurality of memristive structures. The at least one processor <NUM> may be configured to respectively validate each of the memristive structures as described above. For example, the at least one processor <NUM> may be configured to validate a respective memristive structure of the plurality of memristive structures in the case that each static state parameter value of the one or more static state parameter values <NUM> is within the respectively associated predefined validation range. According to some aspects, in the case that a memristive structure is not validated (e.g., invalidated), the memristive structure may be, for example, not addressed during use. As described herein, the one or more static state parameter values may be determined during use of the memristive circuit. In this case, the herein described validation may (e.g., additionally) carried out during use. This allows to "sort out" memristive structures which change (e.g., of which the properties change) during use, such that these memristive structures may be, for example, not further addressed during use. This ensures the reliability, lifetime, data security, etc. of the memristive circuit. According to various aspects, the at least one processor <NUM> may be configured to validate the memristive circuit in the case that each memristive structure of the plurality of memristive structures is validated. It is noted that the respectively assigned predefined validation range serves as an example and that one or more other criteria may be used for validation. Such a criterium may be, for example, a variation of the values of a static state parameter among the plurality of memristive structures (e.g., a deviation from an average over the plurality of memristive structures). For example, the at least one processor <NUM> may be configured to respectively determine, for each memristive structure of the plurality of memristive structures, a respective value for one or more static state parameters. The at least one processor <NUM> may be configured to respectively determine, for at least one (e.g., each) static state parameter of the one or more static state parameters a variation of the determined values and whether this determined variation is equal to or less than a predefined threshold variation. The at least one processor <NUM> may be configured to validate the memristive circuit in the case that, for the at least one (e.g., each) static state parameter of the one or more static state parameters, the variation is equal to or less than the predefined threshold variation. Hence, a respective variation (e.g., a variation value) may be determined for each of the one or more static state parameters and the memristive circuit may be validated in the case that each of the determined variations is equal to or less than the predefined threshold variation. According to some aspects, in the case that a variation of the values of at least one static state parameter is greater than the threshold, the memristive circuit may be invalidated. This ensures consistent (unvarying) properties of the memristive structures of the memristive circuit, thereby increasing, for example, the reliability of the memristive circuit. The variation of the (static state parameter) values of a static state parameter may be, for example, a deviation from an average value. This average value may be, for example, determined by averaging the determined (static state parameter) values of the static state parameter over the plurality of memristive structures.

According to various aspects, a memristive structure (e.g., each memristive structure of the memristive circuit) may be set (one after another) into different memristive states and in each memristive state a respective validation may be carried out, as described herein.

Using the (static state parameter) values of the one or more static state parameters for validation of a memristive circuit may be a more objective criterium for the certification of the memristive circuit as compared to currently used certification criteria (e.g., since the static state parameters directly describe (e.g., physical, electrical, etc.) properties (and variations of these properties) of the memristive structures of the memristive circuit).

As described herein, the one or more static state parameter values <NUM> of the one or more static state parameters may be indicative of the memristive state the memristive structure resides in. Hence, the determined one or more static state parameter values allow to determine the memristive state, ms , of the memristive structure. According to the processing (e.g., reading) scheme <NUM> shown in <FIG>, the read circuit <NUM> may be configured to, using the one or more static state parameter values <NUM>, determine (e.g., classify) the memristive state <NUM> of the memristive structure <NUM>. As described herein, a memristive structure may be in one of over one hundred (e.g., more than <NUM>, e.g., more than <NUM>) different memristive states. Since the differences between the resistance-characteristic curves of the different memristive states may be small (e.g., when using only one read voltage value), using only the current value corresponding a read voltage value may not allow to different between each of these different memristive states. However, since the one or more static state parameters <NUM> are directly indicative of the resistance-characteristic curves of the different memristive states, using the static state parameter values <NUM> may allow to differentiate between more (e.g., each) of the different memristive states. This also allows to use more logic states. For example, the memristive structure may be associated with over one hundred different logic states. According to the processing (e.g., reading) scheme <NUM> shown in <FIG>, the read circuit <NUM> may be configured to, using the one or more static state parameter values <NUM>, determine (e.g., classify) a logic state <NUM> (of two or more logic states) of the memristive structure <NUM>. According to various aspects, each logic state of the two or more logic states may be associated with one or more memristive states of the memristive structure. Hence, more than one memristive state may be associated with the same logic state. Alternatively, each memristive state may be associated with respective logic state. For various possibilities to determine the logic state of a memristive structure see also the description with reference to <FIG>.

<FIG> shows a device <NUM> according to various aspects. The device <NUM> may be, for example, a memory device, a storage device, and/or a processing device. As an example, the device <NUM> may be used as a back-up memory (e.g., for BIOS configuration data) since memristive structures are faster than transistors. As another example, the device <NUM> may be used as a working memory (e.g., a resistive random-access memory, ReRAM) since memristive structures are not affected by sudden power losses. As a further example, the device <NUM> may be used for inter-of-things application since, due to the non-volatile data storage, memristive structures can store data without energy consumption and may, thus, require less energy. As an even further example, the device <NUM> may be a reprogrammable logic device or a reconfigurable computing device. The device <NUM> may be, for example, a neuromorphic computing device since the plurality of memristive states may serve as a gradient for the neuromorphic computing. The device <NUM> may be, for example, used for neural network computing since the plurality of memristive states may provide a gradient representing weights (and/or biases) within the neural network. The device <NUM> may also be a near-memory computing device or an in-memory computing device. Here, some memristive structures of the device <NUM> may carry out computing processes and other memristive structures of the device <NUM> may be used to store data.

The device <NUM> may include a memristive circuit <NUM>. The memristive circuit <NUM> may include one or more (e.g., a plurality of) memristive structures. The memristive circuit <NUM> may include the read circuit <NUM>. The read circuit <NUM> may be configured to (e.g., individually) address each of the one or more (e.g., plurality of) memristive structures. The read circuit <NUM> may be configured to read a respective memristive state <NUM> and/or a respective logic state <NUM> of each of the one or more (e.g., plurality of) memristive structures. According to some aspects, read circuit <NUM> may be configured to read a respective memristive state <NUM> and/or a respective logic state <NUM> of a respective memristive structure using, for example, at least two times (e.g., via at least two measurements) during a single read-out operation using different read-out voltage values or different read-out current values, as described herein (see, for example, description with reference to <FIG>). It is understood that measuring the resistance-characteristic curve, as describe herein, may include measuring several data points, I(V) or V(I), and, thus, several measurements. However, it is also understood that these measurements may be carried out during the same read-out operation (e.g., during applying a single measurement signal (e.g., measurement pulse)).

For example, in the case that the read circuit <NUM> is configured to determine (e.g., measure) the first current value, Iread1 , corresponding to first voltage value, Vread1 , and the second current value, Iread2 , corresponding to the second voltage value, Vread2 (see <FIG> and corresponding description), the read circuit <NUM> may be configured to determine a first expected memristive state of the memristive structure <NUM> using the first current value, Iread1 , and to determine a second expected memristive state of the memristive structure <NUM> using the second current value, Iread2. The read circuit <NUM> may be configured to determine the memristive state of the memristive structure <NUM> based on the determined first expected memristive state and the determined second expected memristive state. For example, the read circuit <NUM> may be configured to determine, whether the first expected memristive state corresponds to the second expected memristive state, determine the first expected memristive state as the memristive state of the memristive structure <NUM> in the case that the first expected memristive state corresponds to the second expected memristive state. Illustratively, the memristive state of the memristive structure <NUM> is read out at least two (e.g., exactly two, three, more than three) times at different voltage (or current) values and the memristive state is determined based on these at least two measurements. As described herein, the differences between the resistance-characteristic curves of the different memristive states may be small. Thus, using at least two measurements during a single read-out operation may allow to differentiate between more memristive states as compared to using only one measurement.

As described herein, each data point, (I/V), on the transition curve <NUM> may (unambiguously or bijectively) correspond to one memristive state, ms (V), of the plurality of memristive states. In the case that the read circuit <NUM> is configured to determine the destruction voltage, Vdes (see <FIG> and corresponding description), during a single read-out operation, even more memristive states as compared to using two measurements during the read-out operation may be differentiated.

In the case that the read circuit <NUM> is configured to determine the one or more static state parameter values <NUM> (see, for example, <FIG> and corresponding description), even more memristive states as compared to using the two measurements and as compared to using the destruction voltage can be differentiated. It is understood that the capability to differentiate between more memristive states allows to use more logic states and, thus increases the processing or computational power.

<FIG> each show a device <NUM> according to various aspects. The device <NUM> may be a memory device or a storage device. For example, the device <NUM> may be an n-logic memory. The device <NUM> may include a plurality of memristive structures <NUM>(n = <NUM> to N). "N" may be any integer number equal to or greater than two. According to various aspects, "N" may be any integer number equal to or greater than twenty (e.g., equal to or greater than one hundred).

The device <NUM> may include the read circuit <NUM>. As described herein, the read circuit <NUM> may be configured to read out a respective logic state (of two or more logic states) of each memristive structure of the plurality of memristive structures <NUM>(n = <NUM> to N) via at least two measurements during a single read-out operation (such as, for example, described with reference to any of the <FIG>, and <FIG>).

The device <NUM> may include one or more processors <NUM>. The one or more processors <NUM> may be configured to determine a key <NUM>. The key <NUM> may be, for example, a private key or an authentication key. According to some aspects, the one or more processors <NUM> may be configured to determine the key <NUM> based on the logic states determined for the plurality of memristive elements. According to various aspects, process variations or deviations among the plurality of memristive structures <NUM>(n = <NUM> to N) may be employed to generate the key <NUM>. Thereby, the plurality of memristive structures <NUM>(n = <NUM> to N) is confgiured as a physical unclonable function (PUF). In particular, variations of the production process may induce variations of the plurality of memristive structures <NUM>(n = <NUM> to N). The variations of the production process introduce randomness into the properties of the plurality of memristive structures <NUM>(n = <NUM> to N) and can therefore provide the entropy for generating the key <NUM>. Such variations in the properties of the plurality of memristive structures <NUM>(n = <NUM> to N) may lead to slightly differences in resistance-characteristic curves (which are associated with the same memristive state) of the plurality of memristive structures <NUM>(n = <NUM> to N). As an example, <FIG> shows a respective resistance-characteristic curve of a first memristive structure <NUM>(n = <NUM>), a second memristive structure <NUM>(n = <NUM>), a third memristive structure <NUM>(n = <NUM>), and a fourth memristive structure <NUM>(n = <NUM>) for a case in which each of the first to fourth memristive structures <NUM>(n = <NUM> to <NUM>) are in the same memristive state, ms = o. As described herein, each memristive state, ms , may be associated with a corresponding destruction current, Ides , at which the memristive state may be changed. According to some aspects, each memristive structure of the plurality of memristive structures <NUM>(n = <NUM> to N) may be in the same memristive state. According to other aspects, each memristive structure of the plurality of memristive structures <NUM>(n = <NUM> to N) may be in a memristive state within a predefined subrange of a plurality of memristive states. For example, the variations among the plurality of memristive structures <NUM>(n = <NUM> to N) may lead an overlap of the resistance-characteristic curves of two or more memristive structures even in the case that the two or more memristive structures are in different memristive states. Therefore, the predefined subrange of a plurality of memristive states may allow to introduce a further entropy and therefore to increase the security of the PUF.

According to various aspects, the read circuit <NUM> may be configured to read out the respective logic state of each of the plurality of memristive structures <NUM>(n = <NUM> to N) non-destructively. Here, threshold values may be used to determine the respective logic state (of two or more logic states) of each of the plurality of memristive structures <NUM>(n = <NUM> to N). A threshold value may be, for example, selected such that <NUM> % to <NUM> % (e.g., about <NUM> %) of the plurality of memristive structures <NUM>(n = <NUM> to N) are in one logic state and that the other memristive structures are in another logic state. For example, extracted discrete parameters may be "sorted" with respect to corresponding threshold values which are the values separating discrete values corresponding to different logic states (e.g., "<NUM>" and "<NUM>"). In the following, two examples of determining the respective logic state are described:.

As a first example, the read circuit <NUM> may be configured to carry out a first measurement during a read-out operation at the first voltage value, Vread1 , and a second measurement during the read-out operation at the second voltage value, Vread2 (see, for example, <FIG> and corresponding description). It is understood that this serves for illustration and that more than two measurements may be carried out during the read-out operation. As exemplarily shown in <FIG>, each of the first voltage value, Vread1 , and the second voltage value, Vread2 , may be associated with a respective current threshold value, Ith1 or Ith2. All memristive structures of the plurality of memristive structures <NUM>(n = <NUM> to N) having a current value less than the respective current threshold value may be associated with a first logic state and all memristive structures of the plurality of memristive structures <NUM>(n = <NUM> to N) having a current value greater than the respective current threshold value may be associated with a second logic state (e.g., "<NUM>") different from the first logic state (e.g., "<NUM>"). This may be carried out using a (e.g., current) comparator. Thus, a first intermediate logic state (being the first logic state (e.g., "<NUM>") the second logic state (e.g., "<NUM>")) may be determined (using the first current threshold value, Ith1 ) corresponding to the first voltage value, Vread1 , and a second intermediate logic state (being the first logic state (e.g., "<NUM>") the second logic state (e.g., "<NUM>")) may be determined (using the second current threshold value, Ith2 ) corresponding to the second voltage value, Vread2. The logic state of a respective memristive structure may be determined using first intermediate logic state and the second intermediate logic state. This may allow to different between up to four different logic states (hence, the device may be multi-bit-device): As an example, the logic state of the respective memristive structure may be:.

However, it is understood that less than four logic states may be used by assigning these four combinations to two or three different logic states.

It is understood that each read voltage value may be associated with more than one current threshold value. For example, in the case that the first voltage value, Vread1 , may be associated with two threshold values, Ith1a and Ith1b , all memristive structures of the plurality of memristive structures <NUM>(n = <NUM> to N) having a current value less than the first, Ith1a , of the two current threshold values, Ith1a and Ith1b , may be associated with the first logic state, all memristive structures of the plurality of memristive structures <NUM>(n = <NUM> to N) having a current value greater than the first, Ith1a , and lower than the second, Ith1b , of the two current threshold values, Ith1a and Ith1b , may be associated with the second logic state, and all memristive structures of the plurality of memristive structures <NUM>(n = <NUM> to N) having a current value greater than the second, Ith1b , of the two current threshold values, Ith1a and Ith1b , may be associated with a third logic state. Hence, this may increase the number of possible logic states.

As described herein, more than two measurements may be carried out at different voltage values during a single read-out operation. Here, each voltage value may be associated with one or more current threshold values as described above. Thus, a maximum number of (e.g., intermediate) logic states may be given by (t + <NUM>)r, wherein t is the number of current threshold values respectively used for each measurement and r is the number of measurements during the read-out operation. As understood, the read circuit <NUM> may be configured to determine each of these (e.g., intermediate) logic states (t + <NUM>)r as a respective logic state or to map these (e.g., intermediate) logic states (t + <NUM>)r to less logic states (e.g., in the case of a binary device to either "<NUM>" or "<NUM>").

As described herein, applying the read voltage pulse serves as an example for a measurement signal. Hence, in the case that the measurement signal is a current pulse, the described thresholds apply in an analog (vice versa) manner to voltage threshold values.

As a second example, the read circuit <NUM> may be configured to read out a respective memristive structure by measuring the resistance-characteristic curve of the respective memristive structure. Here, the read circuit <NUM> may be configured to determine the one or more static state parameter values <NUM> via fitting the resistance-characteristic curve based on the physical model. <FIG> shows measured resistance-characteristic curves of a plurality of memristive structures which are in the same memristive state. This shows illustratively the process variation induced variations among the plurality of memristive structures. <FIG> shows the static state parameter values <NUM> of the reverse saturation current, IS, the series resistance, RS, as well as n<NUM> and K (which both describe an ideality of the respective memristive structure) obtained by respectively fitting each of the measured resistance-characteristic curves using the physical model according to: <MAT>.

Each static state parameter may be associated with a respective parameter threshold value. For example, all memristive structures of the plurality of memristive structures having a respective static state parameter value less than the respective parameter threshold value may be associated with a first logic state (e.g., "<NUM>") and all memristive structures of the plurality of memristive structures having a respective static state parameter value greater than the respective parameter threshold value may be associated with a second logic state (e.g., "<NUM>") different from the first logic state. Thus, a maximum number of possible memristive states may be given by <NUM>s, wherein s is the number of static state parameters.

As shown in <FIG>, the factors n<NUM> and K (which represent the ideality of the respective memristive structure) may vary among a comparatively broad range. This may allow to increase the number of memristive states used for the device <NUM> since memristive structures having different memristive states may have similar "ideality" and memristive structures being in the same memristive state may have a different "ideality" (as shown in <FIG>). Increasing the number of used memristive states (i.e., increasing the number of memristive states within the predefined subrange of memristive states, e.g., up to all memristive states) may further increase the security of the device (e.g., of the PUF). In this case, the memristive states of the plurality of memristive structures may be (e.g., randomly) distributed over the memristive states within the predefined subrange of memristive states (e.g., over all memristive states of the memristive structures).

As described herein, a memristive structure may be in a (positive) memristive state associated with the first quadrant of the IV-curve or in a (negative) memristive state associated with the third quadrant of the IV-curve. All of the plurality of memristive structures <NUM>(n = <NUM> to N) may be either in a (positive) memristive state associated with the first quadrant of the IV-curve or in a (negative) memristive state associated with the third quadrant of the IV-curve. The memristive structures, for which the resistance-characteristic curves are shown in <FIG>, are in the same (positive) memristive state within the first quadrant. For illustration, <FIG> shows measured resistance-characteristic curves for the plurality of memristive structures of <FIG> which are set in the same (negative) memristive state within the third quadrant and <FIG> shows correspondingly determined static state parameter values. <FIG> shows measured resistance-characteristic curves for another plurality of memristive structures set in the same (positive) memristive state within the first quadrant and <FIG> shows measured resistance-characteristic curves for the other plurality of memristive structures set in the same (negative) memristive state within the third quadrant. <FIG> shows the static state parameters determined for the measured resistance-characteristic curves of <FIG> and <FIG> shows the static state parameters determined for the measured resistance-characteristic curves of <FIG>.

With reference to <FIG>, the one or more processors <NUM> may be configured to generate a cryptographic key <NUM> using the determined key <NUM>. Hence, the device <NUM> may serve as a cryptographic device. As described, each memristive structure may be associated with two or more intermediate logic states. Hence, the device <NUM> may be a many-state-device. The one or more processors <NUM> may be, for example, configured to map these two or more logic states to either two logic states (e.g., "<NUM>" and "<NUM>") or a combination of these two logic states. As an example, in the case of the two measurements during the read-out operation, the four possible intermediate logic states may be mapped to "<NUM>", "<NUM>", "<NUM>", and "<NUM>". The key <NUM> may then, for example, include these combinations of all memristive structures. As described herein, in the case of using the static state parameter values <NUM>, the number of possible intermediate logic states and, therefore, also the number of combinations of two logic states may be increased. The one or more processors <NUM> may be configured to generate the cryptographic key <NUM> by applying an encryption algorithm on the determined key <NUM>. With reference to <FIG>, the one or more processors <NUM> may be configured to generate (e.g., using a shift register) a random number <NUM> using the determined key <NUM>. Hence, the device <NUM> may serve as a random number generator.

With reference to <FIG>, the device <NUM> may include a programming circuit <NUM>. The programming circuit <NUM> may be configured to (individually) set (e.g., write) each of the memristive structures into a respective memristive state. Hence, the device <NUM> may be a reconfigurable device (e.g., may serve as a reconfigurable PUF). This may allow to change the key <NUM> (and, hence, e.g., the cryptographic key <NUM>). According to various aspects, the device <NUM> may include a random number generator and the programming circuit may be configured to select the memristive state into which a respective memristive element of the plurality of memristive elements is to be written from the plurality of memristive states based on a random number generated by the random number generator. This may further increase the randomness and, thus, the security.

The device <NUM> may be any device which may use or may be employed to generate a key (e.g., a cryptographic key), a random number, etc. Thus, the device <NUM> may be or may be part of any suitable security device. For example, the device <NUM> may be or may be part of a hardware security module, a security key (e.g., a Universal Serial Bus (USB) security key), and/or a secure cryptoprocessor.

When determining the logic state via two or more measurements during a single read-out operation (e.g., using the static state parameter values), the variability of different PUFs may be determined with reduced error rate (in comparison to a single read-out value).

As described herein, the device <NUM> and/or the device <NUM> may be an analog device.

<FIG> shows a flow diagram of a method <NUM> for reading a memristive element using at least two different reading voltages.

The method <NUM> may include applying a measurement pulse (e.g., a voltage pulse or a current pulse) to a memristive element which is set into a memristive state (in <NUM>).

The measurement pulse may be a voltage pulse. In this case, the method <NUM> may include (in <NUM>) during applying the voltage pulse to the memristive element, measuring a first current value associated with a current through the memristive element at a first voltage value and a second current value associated with the current through the memristive element at a second voltage value different from the first voltage value.

An alternative method may include applying a first voltage pulse to a memristive element which is set into a memristive state, during applying the first voltage pulse to the memristive element, measuring a first current value associated with a current through the memristive element at a first voltage value. This alternative method may include applying a second voltage pulse to the memristive element and during applying the second voltage pulse to the memristive element, measuring a second current value associated with the current through the memristive element at a second voltage value.

The measurement pulse may be a current pulse. In this case, the method <NUM> may include (in <NUM>) during applying the current pulse to the memristive element, measuring a first voltage value associated with a voltage drop over the memristive element at a first current value and a second voltage value associated with the voltage drop over the memristive element at a second current value different from the first current value.

An alternative method may include applying a first current pulse to a memristive element which is set into a memristive state, during applying the first current pulse to the memristive element, measuring a first voltage value associated with a voltage drop over the memristive element at a first current value. This alternative method may include applying a second current pulse to the memristive element and during applying the second current pulse to the memristive element, measuring a second voltage value associated with the voltage drop over the memristive element at a second current value.

The method <NUM> may include applying a measurement pulse (e.g., a voltage pulse or a current pulse) to a memristive element (in <NUM>).

The measurement pulse may be a voltage pulse. In this case, the method <NUM> may include (in <NUM>) during a falling edge of the applied voltage pulse, measuring a first current value associated with a current through the memristive element at a first voltage value and a second current value associated with the current through the memristive element at a second voltage value different from the first voltage value.

The measurement pulse may be a current pulse. In this case, the method <NUM> may include (in <NUM>) during a falling edge of the applied current pulse, measuring a first voltage value associated with a voltage drop over the memristive element at a first current value and a second voltage value associated with the voltage drop over the memristive element at a second current value different from the first current value.

In each of the methods <NUM>, <NUM>, the application of the measurement pulse and the measurement of the first current or voltage value and the second current or voltage value may be carried out as described with reference to, for example, any of <FIG>.

<FIG> shows a flow diagram of a method <NUM> for determining a respective value of one or more static state parameters associated with a memristive state of a memristive structure.

The method <NUM> may include setting a memristive element into a memristive state of a plurality of memristive states (in <NUM>).

The method <NUM> may include determining one or more static state parameter values of the memristive element associated with the memristive state (in <NUM>). Determining the one or more static state parameter values may include determining a current/voltage characteristic of the memristive element. The current/voltage characteristic may be determined by applying a read voltage sequence to the memristive element to cause a corresponding current sequence through the memristive element or by applying a read current sequence to the memristive element to cause a corresponding voltage drop sequence over the memristive element. The one or more static state parameters may be determined via fitting the current/voltage characteristic by a physical model. The physical model may be based on static state parameters for which the static state parameter values are determined.

The determination of the one or more static state parameter values of the memristive element may be carried out as described with reference to any of <FIG>.

Claim 1:
A method, comprising:
setting a memristive element into a memristive state of a plurality of memristive states,
determining one or more static state parameter values (<NUM>) of the memristive element associated with the memristive state, wherein determining the one or more static state parameter values (<NUM>) comprises:
determining a current/voltage characteristic (<NUM>) of the memristive element, and
fitting (<NUM>) the current/voltage characteristic (<NUM>) based on a physical model to determine the one or more static state parameter values (<NUM>), wherein the physical model is based on static state parameters for which the static state parameter values (<NUM>) are determined,
wherein the current/voltage characteristic (<NUM>) is fitted (<NUM>) based on the following formula: <MAT>
wherein V is an applied voltage, I is a current through the memristive element responsive to applying the voltage V, kB is the Boltzmann constant, T is the temperature of the memristive element, q is the electron charge, and A, B, C, and D are static state parameters.