Patent Description:
Phase change memory (PCM) can be utilized for both training and inference in analog computing for artificial intelligence. The PCM structures can include phase change memristive devices with tunable conductivities and overall high device resistance with high retention to minimize energy consumption. The tuning can be accomplished by forming different structural states with varying proportions of crystalline and amorphous phases of PCM material. The formation of these phases can occur by heating the PCM material in varying amounts in a controlled fashion.

According to an embodiment of the present invention, a PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

According to an embodiment of the present invention, a method of manufacturing a PCM cell includes forming a first electrode and forming an electrical insulator stack on the first electrode. The stack includes a plurality of first layers comprised of a first material, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material. The method also includes forming a via in the stack, removing portions of the plurality of second layers from the via while leaving the plurality of first layers intact, forming a wall in the via on the plurality of first layers, which creates a plurality of gaps, forming a heater/PCM portion inside the wall, and forming a second electrode on the heater/PCM portion.

According to an embodiment of the present invention, a PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner, the stack defining a plurality of gaps. Each of the gaps has a toroidal shape, is axially spaced apart from each other from one or more other gaps, and surrounds a portion of the PCM material.

<CIT> illustrates a phase change material random access memory (PRAM) including a tantalum nitride heater. <CIT> discloses a phase change memory device having a patterned projection segment on a heater terminal and the publication titled "<NPL> reveals a mushroom-type PCM device design with a projection liner between a bottom electrode heater and a phase-change material.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the present invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present disclosure is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layers "C" and "D") are between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

In addition, any numerical ranges included herein are inclusive of their boundaries unless explicitly stated otherwise.

For purposes of the description hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms "overlying," "atop," "on top," "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted, the term "selective to," such as, for example, "a first element selective to a second element," means that a first element can be etched, and the second element can act as an etch stop.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography.

Deposition can be any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Removal/etching can be any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

Semiconductor doping can be the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing ("RTA"). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

Semiconductor lithography can be the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device.

<FIG> and <FIG> are cross-section views of PCM cell <NUM> for use in, for example, an integrated circuit (not shown). In the illustrated embodiment, PCM cell <NUM> comprises bottom wire <NUM>, insulator <NUM>, bottom electrode <NUM>, insulator <NUM>, wall <NUM>, projection liner <NUM>, PCM material <NUM>, stack <NUM>, gaps <NUM>, insulator <NUM>, top electrode <NUM>, and top wire <NUM>.

In the illustrated embodiment, the bottom of bottom electrode <NUM> is in direct contact with and electrically connected to the top of bottom wire <NUM>, which can receive electrical signals from other components (not shown) of the integrated circuit. The bottom of projection liner <NUM> is in direct contact with and electrically connected to the top of bottom electrode <NUM>. The bottom and side of PCM material <NUM> is in direct contact with and electrically and thermally connected to the inner surface of projection liner <NUM>. The bottom of top electrode <NUM> is in direct contact with and electrically connected to the top of PCM material <NUM>. The bottom of top wire <NUM> is in direct contact with and electrically connected to the top of top electrode <NUM>, and top wire <NUM> can deliver electrical signals from PCM cell <NUM> to other components (not shown) of the integrated circuit.

In the illustrated embodiment, wall <NUM> is in direct contact with and laterally surrounds the outer sides of projection liner <NUM>. As such, wall <NUM> encloses projection liner <NUM> on all parallel sides in at least one direction (e.g., the sides that extend vertically, as shown in <FIG>). Stack <NUM> generally laterally surrounds and is selectively in direct contact with the outer sides of wall <NUM>. More specifically, stack <NUM> is an electrical insulator that has a bi-layer configuration comprising alternating A layers <NUM> and B layers <NUM>. While inner sides <NUM> of A layers <NUM> are in direct contact with wall <NUM> and laterally surround the corresponding axial sections thereof, inner sides <NUM> of B layers <NUM> are laterally spaced apart from wall <NUM>. This forms a series of axially spaced, toroidal gaps <NUM> that each surround a portion of wall <NUM>, projection liner <NUM>, and PCM material <NUM>, wherein each gap <NUM> is bounded by two A layers <NUM>, a B layer, and wall <NUM>. Because gaps <NUM> are voids in stack <NUM>, no solid material contacts the outer sides of wall <NUM> at gaps <NUM>. The bottom and top of stack <NUM> are formed by two A layers <NUM>, which are directly in contact with insulator <NUM>, bottom electrode <NUM>, insulator <NUM>, and top electrode <NUM>, respectively. Top electrode <NUM> is also in direct contact with and surrounded by insulator <NUM> laterally on its outer side and axially on a portion of its top side, and the outer sides of top wire <NUM> are in direct contact with and laterally surrounded by insulator <NUM>.

While there are nine layers shown in <FIG> (i.e., five A layers <NUM> and four B layers <NUM>), there can be fewer (e.g., three) or greater (e.g., twenty-one). In addition, A layers <NUM> and B layers <NUM> can be, for example, between <NUM> nanometers (nm) and <NUM> thick. Furthermore, the thickness of A layers <NUM> can be the same as or different from the thickness of B layers <NUM>.

In the illustrated embodiment, A layers <NUM> and B layers <NUM> are comprised of a dielectric (electrical insulating) material, such as, for example, NBLoK, silicon nitride (SiN), aluminum oxide (Al<NUM>O<NUM>), aluminum nitride (AIN), silicon oxide (SiO<NUM>), or silicon oxycarbide (SiOXCY). A layers <NUM> and B layers <NUM> are comprised of different materials such that portions of B layers <NUM> can be selectively removed without removing a significant amount of A layers <NUM> (thereby forming gaps <NUM>). For example, A layers <NUM> can be comprised of SiN and B layers <NUM> can be comprised of AIN. The difference in the materials of A layers <NUM> and B layers <NUM> can be utilized during the manufacturing of PCM cell <NUM>. For example, there is significant selectivity with respect to the removal of AIN and the removal of SiN by some reactants and/or processes, with a ratio of etching rates (i.e., AlN:SiN or SiN:AIN), for example, of <NUM>:<NUM>, <NUM>:<NUM>, or greater. More specifically, SiN is susceptible to being removed using a RIE process, whereas AIN is resistant to an RIE process, so SiN can be removed without substantially removing AIN. On the other hand, AIN is susceptible to being removed using certain wet etching processes and chemicals, whereas SiN is resistant to such processes, so AIN can be removed without substantially removing SiN. For another example, A layers <NUM> can be comprised of SiO<NUM> and B layers <NUM> can be comprised Al<NUM>O<NUM>. Al<NUM>O<NUM> has a higher selectivity with chlorine gas (Cl<NUM>), argon (Ar), and an argon-boron-chlorine (Ar/B/Cl<NUM>) mixture. Furthermore, the SiO<NUM> and SiN etching rates are related to carbon tetrafluoride (CF<NUM>) and oxygen (O<NUM>), while the Al<NUM>O<NUM> etching rate is related to aluminum chloride (AlCl<NUM>) or a chlorine-boron trichloride (Cl<NUM>/BCl<NUM>) mixture. Therefore, gasses such as fluorine (F), Cl<NUM>, sulfur hexafluoride (SF<NUM>), fluorocarbon (CxFy), Ar, hydrogen (H<NUM>), etc. can provide RIE selectivity between Al<NUM>O<NUM> and SiN or SiO<NUM>.

In the illustrated embodiment, insulators <NUM>, <NUM>, <NUM> and stack <NUM> structurally support and electrically isolate the other components of PCM cell <NUM>, selectively, and fill in the space therebetween, as appropriate. Thus, the outer side of bottom wire <NUM> is in direct contact with and laterally surrounded by insulator <NUM>, and the outer side of bottom electrode <NUM> is in direct contact with and laterally surrounded by insulator <NUM>. Furthermore, the top side of stack <NUM>, the outer side and part of the top side of top electrode <NUM>, and the outer side of top wire <NUM> are in direct contact with insulator <NUM>.

In the illustrated embodiment, a cross-section of various components and/or the entirety of PCM cell <NUM> (into the page in <FIG>) can be circular, although in other embodiments, it can be rectangular, square, oval, or any other suitable shape. In addition, the width of PCM material <NUM> is smaller than the widths of bottom electrode <NUM> and top electrode <NUM>, whereas the axial length of PCM material <NUM> is substantially longer than its width. Thereby, PCM cell <NUM> can be said to have a confined cell configuration wherein an electrical signal (i.e., electrical current) can flow from bottom electrode <NUM> to top electrode <NUM> through projection liner <NUM> and PCM material <NUM>. In some embodiments, PCM material <NUM> can be between <NUM> and <NUM> wide and between <NUM> and <NUM> thick (i.e., tall).

In the illustrated embodiment, bottom electrode <NUM> and top electrode <NUM> are comprised of a very electrically conductive material, such as metal or metallic compound, for example, titanium nitride (TiN) or tungsten (W). Wall <NUM> has a high electrical resistance component that is comprised of a dielectric (e.g., SiN) or a higher resistance metal, such as, for example, tantalum nitride (TaN). Wall <NUM> can have a thickness in the range of, for example, <NUM> to <NUM>. In addition, projection liner <NUM> is comprised of a higher resistance metal, such as, for example, TaN. Projection liner <NUM> can have a thickness in the range of, for example, <NUM> to <NUM>.

In the illustrated embodiment, insulators <NUM>, <NUM>, <NUM> are comprised of a dielectric (electrical insulating) material, such as, for example, SiN, SiO<NUM>, silicon nitride carbide (SiNC), or tetraethyl orthosilicate (TEOS). In some embodiments, all of the insulators <NUM>, <NUM>, <NUM> are the same material, and in other embodiments, different materials are used for some or all of insulators <NUM>, <NUM>, <NUM>. In some embodiments, insulator <NUM> (and bottom electrode <NUM>) has a thickness in the range of <NUM> to <NUM>.

In the illustrated embodiment, PCM material <NUM> is composed essentially of a phase change material such as a germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-iridium-antimony-telluride (AIST) material, although other materials can be used as appropriate. Examples of other PCM materials can include, but are not limited to, germanium-tellurium compound material (GeTe), silicon-antimony-tellurium (Si-Sb-Te) alloys, gallium-antimony-tellurium (Ga-Sb-Te) alloys, germanium-bismuth-tellurium (Ge-Bi-Te) alloys, indium-tellurium (In-Se) alloys, arsenic-antimony-tellurium (As-Sb-Te) alloys, silver-indium-antimony-tellurium (Ag-In-Sb-Te) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, Ge-Te alloys and combinations thereof. PCM material <NUM> may be undoped or doped (e.g., doped with one or more of oxygen (O), nitrogen (N), silicon (Si), or titanium (Ti). The terms "composed essentially" and "consist essentially," as used herein with respect to materials of different layers, indicates that other materials, if present, do not materially alter the basic characteristics of the recited materials. For example, a PCM material <NUM> consisting essentially of GST material does not include other materials that materially alter the basic characteristics of the GST material.

In the illustrated embodiment, PCM cell <NUM> can be operated as a memory cell by passing an electrical current pulse from bottom electrode <NUM> to top electrode <NUM> to program PCM cell <NUM>. This can be done at a variety of voltages and/or for a variety of durations to read or write a value on PCM cell <NUM>. For example, to write, a high voltage can be used (e.g., <NUM> volt (V) to <NUM> V) for a short duration, which can cause PCM material <NUM> to heat itself (via resistive heating) beyond its melting point. Thereby, PCM material <NUM> serves the function of heater as well as of memory. Once the flow of current ceases, PCM material <NUM> can cool down rapidly, which forms amorphous zone <NUM> in a process called "resetting". Amorphous zone <NUM> is a dome-shaped region of PCM material <NUM> having an amorphous configuration, although the remainder of PCM material <NUM> is still in a polycrystalline configuration. In general, this amorphous configuration has no definite structure. However, there can be local, disjoint crystalline nuclei (i.e., small, crystallized regions of phase change material <NUM>) present in amorphous zone <NUM>. The creation of amorphous zone <NUM> can cause the electrical resistance across PCM cell <NUM> to increase as compared to a solely polycrystalline configuration (à la PCM cell <NUM> in <FIG>). These resistance values of PCM cell <NUM> can be read without changing the state of PCM material <NUM> (including that of amorphous zone <NUM>) or the resistance value of PCM cell <NUM>, for example, by sending a current pulse at a low voltage (e.g., <NUM> V) from bottom electrode <NUM> to top electrode <NUM>.

In addition, PCM material <NUM> can be rewritten and returned back to a solely polycrystalline configuration by "setting" PCM cell <NUM>. One way to set PCM material <NUM> uses a high voltage electrical pulse (e.g., <NUM> V to <NUM> V) for a short period of time (e.g., <NUM> nanoseconds (ns)), which can cause PCM material <NUM> to heat up beyond its crystallization point but not to its melting point. Since the crystallization temperature is lower than the melting temperature, once the flow of current ceases, PCM material <NUM> can anneal and form crystals. Another way to set PCM material <NUM> uses an electrical pulse with a relatively long trailing edge (e.g., <NUM> microsecond) (as opposed to a square pulse with a relatively short trailing edge on the order of nanoseconds) that is strong enough to heat PCM material <NUM> beyond its melting point, after which, PCM material <NUM> is cooled down slowly, allowing crystals to form. Either of these processes cause the electrical resistance across a solely polycrystalline PCM cell <NUM> to decrease as compared to a PCM cell <NUM> having an amorphous zone <NUM> (à la PCM cell <NUM> in <FIG>). This new resistance value can then be read using current at a low voltage (e.g., <NUM> V) without changing the state of PCM material <NUM> or the resistance value of PCM cell <NUM>.

In some embodiments, the melting temperature of PCM material <NUM> is about <NUM>. In some embodiments, the crystallization temperature of PCM material <NUM> is about <NUM>. In addition, the process of setting and resetting PCM cell <NUM> can occur repeatedly, and in some embodiments, different amorphous zones <NUM> with different resistances can be created in PCM materials <NUM> (e.g., due to having different sizes of amorphous zone <NUM> and/or amounts of crystallization nuclei in amorphous zone <NUM>). This allows for PCM cell <NUM> to have various distinct resistances that can be created by varying the resetting parameters. Thereby, if PCM cell <NUM> is considered to represent information digits, these digits can be non-binary (as opposed to traditional bits). However, in some embodiments, PCM cell <NUM> can be used as a bit by either having or not having a uniform amorphous zone <NUM> in PCM material <NUM>. In such embodiments, PCM cells <NUM> can have a high resistance (a. , low voltage output or "<NUM>") or low resistance (a. , high voltage output or "<NUM>").

The components and configuration of PCM cell <NUM> allows for gaps <NUM> to reduce heat conduction away from PCM material <NUM>. This is because gaps <NUM> have lower thermal conductivity than B layers <NUM> would. This allows for more of the heat generated in PCM material <NUM> to stay in PCM material <NUM>, which increases the speed and efficiency of PCM cell <NUM> and lowers the amount of energy required to tune/program PCM cell <NUM>. Furthermore, the degradation of the performance PCM cell <NUM> is also reduced, and bottom wire <NUM> and top wire <NUM> are heated less than they would be without gaps <NUM>. In addition, projection liner <NUM> thermally insulates bottom electrode <NUM> from PCM material <NUM>, further increasing the efficiency of PCM cell <NUM>.

<FIG> is a flowchart of method <NUM> of manufacturing PCM cell <NUM>. <FIG> are a series of views of method <NUM> of manufacturing PCM cell <NUM>. <FIG> and <FIG> will now be discussed in conjunction with one another wherein each operation of method <NUM> is illustrated by one of <FIG>. In addition, during this discussion, references may be made to features of PCM cell <NUM> shown in <FIG> and/or 1B.

In the illustrated embodiment, method <NUM> starts at operation <NUM>, wherein bi-layer dielectric block <NUM> is formed on bottom electrode <NUM> and insulator <NUM>. At operation <NUM>, mask <NUM> is formed on block <NUM>. Mask <NUM> is comprised of organic planarization layer (OPL) <NUM>, silicon with anti-reflective coating (SiARC) <NUM>, and photoresist layer <NUM>. Photoresist layer <NUM> includes gap <NUM> for formation of via <NUM> during operation <NUM>. More specifically, via <NUM> has, for example, a width of <NUM>, which is smaller than the width of bottom electrode <NUM>. Via <NUM> is formed by etching each layer of block <NUM> equally, after which mask <NUM> is removed.

At operation <NUM>, block <NUM> is selectively etched, for example, using a wet or RIE process to remove portions of one type of the bi-layer dielectric material in via <NUM> while leaving the other type of the bi-layer dielectric material intact. Thereby, at operation <NUM>, pore <NUM> is formed, as is stack <NUM> (having A layers <NUM> and B layers <NUM>), wherein inner sides <NUM> of B layers <NUM> are offset from inner sides <NUM> of A layers <NUM>. At operation <NUM>, TaN layer <NUM> is formed on stack <NUM> using a CVD or PVD process. Thereby, TaN layer <NUM> conforms to the interior edges of A layers <NUM>, avoiding contact with B layers <NUM> and separating pore <NUM> into cavity <NUM> and gaps <NUM>. The forming of gaps <NUM> occurs under the condition of the CVD or PVD process, during which a vacuum is present. This vacuum can be, for example, at a pressure of <NUM> millitorr (mTorr) or less, which leaves some fluid (e.g., air) sealed in gaps <NUM>. In some embodiments, an ALD process is used at operation <NUM> instead of CVD or PVD. However, if ALD is used, the resulting TaN layer <NUM> may intrude farther into pore <NUM>, toward B layers <NUM>, resulting in smaller gaps <NUM>. This can reduce the thermal insulating properties of stack <NUM> since air has a lower thermal conductivity than a dielectric material.

At operation <NUM>, TaN layer <NUM> is etched, for example, using an RIE process to remove its horizontal portions, thereby exposing bottom electrode <NUM> and stack <NUM>, as well as forming wall <NUM>. At operation <NUM>, projection layer <NUM> and PCM layer <NUM> are deposited inside wall <NUM>. More specifically, projection layer <NUM> is formed on stack <NUM>, wall <NUM>, and bottom electrode <NUM>, and PCM layer <NUM> is formed on projection layer <NUM>. At operation <NUM>, chemical mechanical polishing (CMP) is performed to remove the excess material from projection layer <NUM> and PCM layer <NUM> to form projection liner <NUM> and PCM material <NUM>, respectively, which are coterminous with stack <NUM>. At operation <NUM>, insulator <NUM>, top electrode <NUM>, and top wire <NUM> are formed on stack <NUM>, wall <NUM>, projection liner <NUM>, and PCM material <NUM>, respectively.

The components, configuration, and operation of PCM cell <NUM> and method <NUM> allow for gaps <NUM> to be formed around PCM material <NUM>. This can occur because B layers <NUM> are susceptible to at least one material removal processes that A layers <NUM> are resistant to.

<FIG> is a flowchart of method <NUM> of manufacturing PCM cell <NUM>. <FIG> are a series of cross-section views of method <NUM> of manufacturing PCM cell <NUM>. <FIG> and <FIG> will now be discussed in conjunction with one another wherein each operation of method <NUM> is illustrated by one of <FIG>. During this discussion, references may be made to features of PCM cell <NUM> (shown in <FIG>) and PCM cell <NUM> (shown in <FIG>). Features that are the same in PCM cell <NUM> as PCM cell <NUM> may have the same reference numerals, and features that are similar in PCM cell <NUM> to those of PCM cell <NUM> may have reference numerals that are <NUM> higher.

In some embodiments, method <NUM> begins at operation <NUM> of method <NUM> (shown in <FIG>), and in other embodiments, method <NUM> begins after operation <NUM> of method <NUM> (shown in <FIG>). Figures 5A-5I will depict the latter embodiment. At operation <NUM>, TiN layer <NUM> and high electrical resistance layer <NUM> are deposited inside wall <NUM>. More specifically, TiN layer <NUM> is formed on stack <NUM>, wall <NUM>, and bottom electrode <NUM>, and high electrical resistance layer <NUM> is formed on TiN layer <NUM> and can be comprised of, for example, SiN or high resistance TaN. At operation <NUM>, chemical mechanical polishing (CMP) is performed to remove the excess material from TiN layer <NUM> and high electrical resistance layer <NUM> to form heater <NUM>, which is coterminous with stack <NUM>. At operation <NUM>, PCM layer <NUM>, TiN layer <NUM>, and SiN layer <NUM> are formed on stack <NUM> and heater <NUM>. In some embodiments, PCM layer <NUM> is about <NUM> thick, TiN layer <NUM> is about <NUM> thick, and SiN layer <NUM> is about <NUM> thick. In some embodiments, prior to operation <NUM>, projection liner <NUM> (shown in phantom as it is not included in the subsequent steps of method <NUM>) is formed on stack <NUM> and heater <NUM>.

At operation <NUM>, masking and etching are performed to form PCM material <NUM>, top electrode <NUM>, and hard mask <NUM>, which exposes stack <NUM>. In the illustrated embodiment, the lateral widths of PCM material <NUM> and top electrode <NUM> are the same, whereas the width of heater <NUM> is substantially reduced, comparatively (e.g., three to seven times smaller, or about five times smaller). Thereby, PCM cell <NUM> can be said to have a mushroom configuration wherein an electrical signal (i.e., electrical current) can flow from bottom electrode <NUM> to top electrode <NUM> through heater <NUM> and PCM material <NUM>. In contrast with PCM cell <NUM>, PCM cell <NUM> has a two-part heater/PCM portion comprised of heater <NUM> and a separate PCM material <NUM>. However, the memory function can be operated in the same way as that of PCM cell <NUM>, albeit using heater <NUM> to program PCM material <NUM> instead of relying on PCM material <NUM> to heat itself.

At operation <NUM>, encapsulation layer <NUM> is formed on stack <NUM>, PCM material <NUM>, top electrode <NUM>, and hard mask <NUM>. Encapsulation layer <NUM> can be comprised of, for example, SiN or silicon carbonitride (SiCN). At operation <NUM>, etching is performed to form encapsulator <NUM> and cap <NUM>, which exposes insulator <NUM>. At operation <NUM>, insulator <NUM> and top wire <NUM> are formed on insulator <NUM>, stack <NUM>, top electrode <NUM>, encapsulator <NUM>, and cap <NUM>, respectively, to complete PCM cell <NUM>.

The components, configuration, and operation of PCM cell <NUM> and method <NUM> allow for gaps <NUM> to be formed around heater <NUM>. This can occur because B layers <NUM> are susceptible to at least one material removal processes that A layers <NUM> are resistant to.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the claims. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claim 1:
A phase change memory (PCM) cell (<NUM>) comprising
a first electrode (<NUM>);
a heater/PCM portion electrically connected to first electrode (<NUM>), the heater/PCM portion comprising a PCM material (<NUM>);
a second electrode (<NUM>) electrically connected to the PCM material (<NUM>); and an electrical insulator stack (<NUM>) surrounding at least some of the heater/PCM portion, the stack (<NUM>) comprising
a plurality of first layers (<NUM>) comprised of a first material and having a plurality of first inner sides facing towards the heater/PCM portion; and
a plurality of second layers (<NUM>) alternating with the plurality of first layers (<NUM>), the plurality of second layer (<NUM>) comprised of a second material that is different from the first material, and the plurality of second layers (<NUM>) having a plurality of second inner sides facing towards the heater/PCM portion;
characterized in that the plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps (<NUM>).