Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. <CIT> discloses a 3D semiconductor memory device including a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate and <CIT> discloses a 3D memory device including an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, wherein a source conductive line structure is provided between the substrate and the alternating stack.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

A three-dimensional memory device according to the invention is defined in claim <NUM>; a method for forming a three-dimensional memory device according to the invention is defined in claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of channel structures, e.g., known as sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plugs that are formed at the lower end of the channel structures, e.g., bottom SEG, the formation of sidewall SEG avoids the etching of the memory film and semiconductor channel at the bottom surface of channel holes (also known as "SONO" punch), thereby increasing the process window, in particular when fabricating 3D NAND memory devices with advanced technologies, such as having <NUM> or more levels with a multi-deck architecture. However, as the thickness and profile of the sidewall SEG depend on the surface condition of the semiconductor channel along the sidewall of the channel structure, the residues on the semiconductor channels may cause large variations in epitaxially growing the sidewall SEG.

Moreover, some 3D NAND memory devices having sidewall SEG employ the gate-induced-drain-leakage (GIDL)-assisted body biasing for erase operations (referred to herein as "GIDL erase"), which suffers low device reliability due to the large electrical stress. The relatively large potential drop can also reduce the erase speed of GIDL erase. The amounts of holes and the efficiencies of generating holes vary among different channel structures, which further affecting the performance of GIDL erase.

Various embodiments in accordance with the present disclosure provide improved 3D memory devices and fabrication methods thereof. An N-type doped semiconductor layer can be deposited to be in contact with the semiconductor channels along the sidewalls of the channel structures, which is not affected by any residues on the semiconductor channels. The N-type doped semiconductor layer in combination with a P-type doped region can enable P-well bulk erase, instead of GIDL erase, by the 3D memory devices, thereby avoiding issues, such as low reliability and erase speed, associated with GIDL erase. In some embodiments, the hole current path for erase operation and the electron current path for read operation are separately formed without the need of inversion channel when performing read operations, which simplifies the control of the source select gate. In some embodiments, each opening (e.g., gate line slits (GLSs)) for forming the source contact structure falls into a respective enlarged recess in the P-type doped region to avoid any negative impact due to gouging variations among different openings.

<FIG> illustrates a side view of a cross-section of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure. 3D memory device <NUM> can include a substrate, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some embodiments, the substrate is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. It is noted that x and y axes are included in <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM>. The substrate of 3D memory device <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a 3D memory device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the 3D memory device in the y-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the 3D memory device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

3D memory device <NUM> can be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., NAND memory strings) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, 3D memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It is understood that in some embodiments, the memory array device substrate is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the backside of the thinned memory array device substrate.

As shown in <FIG>, the substrate of 3D memory device <NUM> can include a P-type doped region <NUM>. P-type doped region <NUM> can be doped with any suitable P-type dopants, such as boron (B), gallium (Ga), or aluminum (Al), to an intrinsic semiconductor creates deficiencies of valence electrons, called "holes. " In some embodiments, the substrate is a P-type silicon substrate, and P-type doped region <NUM> is any part of the P-type silicon substrate close to its top surface. In some embodiments, the substrate is an N-type silicon substrate, and P-type doped region <NUM> is a P-well. For example, part of the N-type silicon substrate may be doped with any suitable P-type dopants, such as B, Ga, or Al, to form a P-well close to the top surface of the N-type silicon substrate. In some embodiments in which the substrate is a single crystalline silicon, P-type doped region <NUM> includes single crystalline silicon doped with P-type dopant(s).

As shown in <FIG>, 3D memory device <NUM> can also include an N-type doped semiconductor layer <NUM> on P-type doped region <NUM>. N-type doped semiconductor layer <NUM> can be an example of the "sidewall SEG" as described above. N-type doped semiconductor layer <NUM> can include a semiconductor material, such as silicon. In some embodiments, N-type doped semiconductor layer <NUM> includes polysilicon formed by deposition techniques, as described below in detail. In some embodiments, the thickness t of N-type doped semiconductor layer <NUM> in the vertical direction is between about <NUM> and about <NUM>, such as between <NUM> and <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values).

N-type doped semiconductor layer <NUM> can be doped with any suitable N-type dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. For example, N-type doped semiconductor layer <NUM> may be a polysilicon layer doped with N-type dopant(s), such as P, Ar, or Sb. In some embodiments, N-type doped semiconductor layer <NUM> is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sub-layers with nonuniform doping concentrations at their interfaces (e.g., a sudden doping concentration change at an interface between two sub-layers). It is understood that the doping concentration of the N-type dopant(s) of N-type doped semiconductor layer <NUM> may still gradually change in the vertical direction as long as there are not any sudden doping concentration changes that can distinguish two or more sub-layers by doping concentration variations. In some embodiments, the doping concentration of N-type doped semiconductor layer <NUM> is between about <NUM><NUM> cm-<NUM> and about <NUM><NUM> cm-<NUM>, such as between <NUM><NUM> cm-<NUM> and <NUM><NUM> cm-<NUM> (e.g., <NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM>×<NUM><NUM> cm-<NUM>, <NUM><NUM> cm-<NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values).

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string can include a channel structure <NUM> that extends through a plurality of pairs each including a conductive layer <NUM> and a dielectric layer <NUM> (referred to herein as "conductive/dielectric layer pairs"). The stacked conductive/dielectric layer pairs are also referred to herein as a memory stack <NUM>. The number of the conductive/dielectric layer pairs in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) determines the number of memory cells in 3D memory device <NUM>. Although not shown in <FIG>, it is understood that in some embodiments, memory stack <NUM> may have a multi-deck architecture, such as a dual-deck architecture that includes a lower memory deck and an upper memory deck on the lower memory deck. The numbers of the pairs of conductive layers <NUM> and dielectric layers <NUM> in each memory deck can be the same or different. As shown in <FIG>, N-type doped semiconductor layer <NUM> having a uniform doping concentration profile is disposed vertically between P-type doped region <NUM> and memory stack <NUM>, according to some embodiments. In other words, there is not another N-type doped semiconductor layer, which has a different doping concentration from N-type doped semiconductor layer <NUM>, disposed vertically between P-type doped region <NUM> and memory stack <NUM>, according to some embodiments.

Memory stack <NUM> can include a plurality of interleaved conductive layers <NUM> and dielectric layers <NUM> on N-type doped semiconductor layer <NUM>. Conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductive layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductive layers <NUM> on both sides. Conductive layers <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer <NUM> can include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of conductive layer <NUM> can extend laterally as a word line, ending at one or more staircase structures (not shown) of memory stack <NUM>. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, channel structure <NUM> extending vertically through memory stack <NUM> and N-type doped semiconductor layer <NUM> into P-type doped region <NUM>. That is, channel structure <NUM> can include three portions: the lower portion surrounded by P-type doped region <NUM> (i.e., below the interface between N-type doped semiconductor layer <NUM> and P-type doped region <NUM>), the upper portion surrounded by memory stack <NUM> (i.e., above the interface between N-type doped semiconductor layer <NUM> and memory stack <NUM>), and the middle portion surrounded by N-type doped semiconductor layer <NUM>. As used herein, the "upper portion" of a component (e.g., channel structure <NUM>) is the portion farther away from the substrate in the y-direction, and the "lower portion" of the component (e.g., channel structure <NUM>) is the portion closer to the substrate in the y-direction when the substrate is positioned in the lowest plane of 3D memory device <NUM>. In some embodiments, the depth d that channel structure <NUM> extends into P-type doped region <NUM> (i.e., the depth of the lower portion of channel structure <NUM>) is between about <NUM> and about <NUM>, such as between <NUM> and <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values).

Channel structure <NUM> can include a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel <NUM>) and dielectric material(s) (e.g., as a memory film <NUM>). In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In one example, semiconductor channel <NUM> includes polysilicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole can be partially or fully filled with a capping layer <NUM> including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). Capping layer <NUM>, semiconductor channel <NUM>, the tunneling layer, the storage layer, and the blocking layer of memory film <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film <NUM> can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In some embodiments, channel structure <NUM> further includes a channel plug <NUM> at the top of the upper portion of channel structure <NUM>. Channel plug <NUM> can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug <NUM> functions as the drain of the NAND memory string.

As shown in <FIG>, part of semiconductor channel <NUM> along the sidewall of channel structure <NUM> (e.g., in the middle portion of channel structure <NUM>) is in contact with N-type doped semiconductor layer <NUM>, according to some embodiments. That is, memory film <NUM> is disconnected in the middle portion of channel structure <NUM> that abuts N-type doped semiconductor layer <NUM>, exposing semiconductor channel <NUM> to be in contact with the surrounding N-type doped semiconductor layer <NUM>, according to some embodiments. As a result, N-type doped semiconductor layer <NUM> surrounding and in contact with semiconductor channel <NUM> can work as the "sidewall SEG" of channel structure <NUM> to replace the "bottom SEG" as described above, which can mitigate issues such as overlay control, epitaxial layer formation, and SONO punch.

As shown in <FIG>, 3D memory device <NUM> can further include an N-type doped semiconductor plug <NUM> extending vertically into P-type doped region <NUM>. In some embodiments, the upper portion of N-type doped semiconductor plug <NUM> extends vertically through N-type doped semiconductor layer <NUM> as well. N-type doped semiconductor plug <NUM> can include a semiconductor material, such as silicon, doped with N-type dopants, such as P, As, or Sb. In some embodiments, N-type doped semiconductor plug <NUM> includes single crystalline silicon. For example, N-type doped semiconductor plug <NUM> may be epitaxially grown from surrounding P-type doped region <NUM> of the substrate, which includes single crystalline silicon. That is, N-type doped semiconductor plug <NUM> and P-type doped region <NUM> include the same material, e.g., single crystalline silicon, but with different dopants, according to some embodiments. On the other hand, N-type doped semiconductor plug <NUM> and N-type doped semiconductor layer <NUM> include different materials, e.g., single crystalline silicon and polysilicon, respectively, but with the same type of dopants, according to some embodiments. It is understood that the doping concentrations of the N-type dopants in N-type doped semiconductor plug <NUM> and N-type doped semiconductor layer <NUM> may be the same or different. In some embodiments, the lateral distance D (e.g., in the x-direction in <FIG>) between channel structure <NUM> and N-type doped semiconductor plug <NUM> is between about <NUM> and about <NUM>, such as between <NUM> and <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values).

As shown in <FIG>, 3D memory device <NUM> can further include a source contact structure <NUM>. Source contact structure <NUM> can extend vertically through the conductive/dielectric layer pairs in memory stack <NUM> to be in contact with N-type doped semiconductor plug <NUM>. That is, source contact structure <NUM> and N-type doped semiconductor plug <NUM> are aligned laterally, e.g., in the x-direction, according to some embodiments. In some embodiments, as the upper portion of N-type doped semiconductor plug <NUM> extends vertically through N-type doped semiconductor layer <NUM>, source contact structure <NUM> is in contact with N-type doped semiconductor plug <NUM>, but not N-type doped semiconductor layer <NUM>. For example, the bottom surface of source contact structure <NUM>, the top surface of N-type doped semiconductor plug <NUM>, and the top surface of N-type doped semiconductor layer <NUM> may be in the same plane (i.e., flush with one another), as shown in <FIG>. Each source contact structure <NUM> can be part of an array common source (ACS) of multiple NAND memory strings, for example, being electrically connected to multiple channel structures <NUM>.

According to the invention, a lateral dimension (e.g., in the x-direction in <FIG>) of N-type doped semiconductor plug <NUM> is greater than a lateral dimension (e.g., in the x-direction in <FIG>) of source contact structure <NUM>, which can facilitate the alignment between N-type doped semiconductor plug <NUM> and source contact structure <NUM> during the fabrication of 3D memory device <NUM>. That is, N-type doped semiconductor plug <NUM> may be viewed as "an enlarged plug" compared with source contact structure <NUM>. It is understood that the lateral dimension of N-type doped semiconductor plug <NUM> and/or the lateral dimension of source contact structure <NUM> may not be uniform in the vertical direction. According to the invention, the lateral dimension of the lower portion of N-type doped semiconductor plug <NUM> surrounded by P-type doped region <NUM> is greater than the lateral dimension of the upper portion of N-type doped semiconductor plug <NUM> surrounded by N-type doped semiconductor layer <NUM> due to the process of removing the same material (e.g., polysilicon) of N-type doped semiconductor layer <NUM> formed on the sidewall of the recess in which N-type doped semiconductor plug <NUM> is formed as described below in detail with respect to the fabrication process. In one example, the lateral dimensions of N-type doped semiconductor plug <NUM> and source contact structure <NUM> may be measured at the interface therebetween, e.g., the bottom surface of source contact structure <NUM> and the top surface of N-type doped semiconductor plug <NUM>. According to the invention, the lateral dimension of N-type doped semiconductor plug <NUM> is the minimum lateral dimension along the vertical direction, and the lateral dimension of source contact structure <NUM> may be the maximum lateral dimension along the vertical direction, such that any lateral dimension of N-type doped semiconductor plug <NUM> is greater than any lateral dimension of source contact structure <NUM>.

Source contact structure <NUM> can also extend laterally (e.g., in the direction perpendicular to x- and y- directions) to separate memory stack <NUM> into multiple blocks. Source contact structure <NUM> can include an opening (e.g., a slit) filled with conductive materials including, but not limited to, W, Co, Cu, Al, titanium (Ti), titanium nitride (TiN), silicides, or any combination thereof, to form a source contact <NUM>. In some embodiments, source contact <NUM> includes polysilicon surrounded by TiN. Source contact <NUM> can be above and in contact with N-type doped semiconductor plug <NUM> to make electrical connections with N-type doped semiconductor plug <NUM>, N-type doped semiconductor layer <NUM>, and/or P-type doped region <NUM>. Source contact structure <NUM> can further include a spacer <NUM> having dielectric materials, such as silicon oxide, laterally between source contact <NUM> and memory stack <NUM> to electrically insulate source contact <NUM> from surrounding conductive layers <NUM> in memory stack <NUM>. As a result, multiple source contact structures <NUM> can separate 3D memory device <NUM> into multiple memory blocks and/or memory fingers. In some embodiments, source contact <NUM> includes polysilicon in its lower portion and a metal (e.g., W) in its upper portion contacting a metal interconnect (not shown), both of which are surrounded by an adhesion layer (e.g., TiN), to form electrical connections between N-type doped semiconductor plug <NUM>, N-type doped semiconductor layer <NUM>, and/or P-type doped region <NUM> (e.g., as the source of the NAND memory string) and the metal interconnect.

The design of the 3D memory device <NUM> disclosed herein can achieve the separation of the hole current path and the electron current path for forming erase operations and read operations, respectively. As shown in <FIG>, 3D memory device <NUM> is configured to form an electron current patent (as indicated by the black arrow) between electron sources (e.g., N-type doped semiconductor plug <NUM> and/or N-type doped semiconductor layer <NUM>) and semiconductor channel <NUM> of channel structure <NUM> to provide electrons to the NAND memory string when performing a read operation, according to some embodiments. Conversely, 3D memory device <NUM> is configured to form a hole current path (as indicated by the white arrow in <FIG>) between hole sources (e.g., P-type doped region <NUM>) and semiconductor channel <NUM> of channel structure <NUM> to provide holes to the NAND memory string when performing a P-well bulk erase operation. As a result, issues associated with GIDL erase, such as low reliability and erase speed, can be avoided by performing P-well bulk erase. Moreover, the control of the source select gate can be simplified since the inversion channel is no longer needed when performing read operations by separating the electron current path and the hole current path.

<FIG> illustrate a fabrication process for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. <FIG> illustrates a flowchart of a method <NUM> for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory device <NUM> depicted in <FIG>. <FIG> and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a recess is formed in a P-type doped region of a substrate. In some embodiments, the substrate is a P-type silicon substrate. In some embodiments, the substrate is an N-type silicon substrate, and the P-type doped region is a P-well. As illustrated in <FIG>, a P-type doped region <NUM> is formed. In some embodiments, P-type doped region <NUM> is a P-well formed by doping a portion of an N-type silicon substrate close to its top surface by P-type dopant(s), such as B, Ga, or Al, using ion implantation and/or thermal diffusion processes. In some embodiments, P-type doped region <NUM> is a portion of a P-type silicon substrate close to its top surface. A recess <NUM> can be formed in P-type doped region <NUM> using dry etch and/or wet etch processes.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a sacrificial layer on the P-type doped region and in the recess, and a dielectric stack on the sacrificial layer are subsequently formed. The sacrificial layer can be a polysilicon layer. The dielectric stack can include a plurality of interleaved stack sacrificial layers and stack dielectric layers.

As illustrated in <FIG>, a sacrificial layer <NUM> is formed on P-type doped region <NUM> and in recess <NUM>. Sacrificial layer <NUM> can be formed by depositing polysilicon or any other suitable sacrificial material (e.g., carbon) that can be later selectively removed on P-type doped region <NUM> as well as into recess <NUM> using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a pad oxide layer is formed between sacrificial layer <NUM> and P-type doped region <NUM> by depositing dielectric materials, such as silicon oxide, or thermal oxidation, on P-type doped region <NUM> prior to the formation of sacrificial layer <NUM>.

As illustrated in <FIG>, a dielectric stack <NUM> including a plurality pairs of a first dielectric layer (known as a "stack sacrificial layer <NUM>") and a second dielectric layer (known as a "stack dielectric layer <NUM>") is formed on sacrificial layer <NUM>. Dielectric stack <NUM> includes interleaved stack sacrificial layers <NUM> and stack dielectric layers <NUM>, according to some embodiments. Stack dielectric layers <NUM> and stack sacrificial layers <NUM> can be alternatively deposited on sacrificial layer <NUM> to form dielectric stack <NUM>. In some embodiments, each stack dielectric layer <NUM> includes a layer of silicon oxide, and each stack sacrificial layer <NUM> includes a layer of silicon nitride. Dielectric stack <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel structure extending vertically through the dielectric stack and the sacrificial layer into the P-type doped region is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the sacrificial layer into the P-type doped region is formed, and a memory film and a semiconductor channel are subsequently formed along a sidewall of the channel hole. In some embodiments, a channel plug is formed above and in contact with the semiconductor channel.

As illustrated in <FIG>, a channel hole is an opening extending vertically through dielectric stack <NUM> and sacrificial layer <NUM> into P-type doped region <NUM>. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure <NUM> in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure <NUM> include wet etch and/or dry etch processes, such as deep-ion reactive etching (DRIE). In some embodiments, the channel hole of channel structure <NUM> extends further through the upper portion of P-type doped region <NUM>. The etching process through dielectric stack <NUM> and sacrificial layer <NUM> may continue to etch part of P-type doped region <NUM>. In some embodiments, a separate etching process is used to etch part of P-type doped region <NUM> after etching through dielectric stack <NUM> and sacrificial layer <NUM>.

As illustrated in <FIG>, a memory film <NUM> (including a blocking layer, a storage layer, and a tunneling layer) and a semiconductor channel <NUM> are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, memory film <NUM> is first deposited along the sidewalls and bottom surface of the channel hole, and semiconductor channel <NUM> is then deposited over memory film <NUM>. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor channel <NUM> can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of memory film <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are subsequently deposited to form memory film <NUM> and semiconductor channel <NUM>.

As illustrated in <FIG>, a capping layer <NUM> is formed in the channel hole and over semiconductor channel <NUM> to completely or partially fill the channel hole (e.g., without or with an air gap). Capping layer <NUM> can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug <NUM> then can be formed in the upper portion of the channel hole. In some embodiments, parts of memory film <NUM>, semiconductor channel <NUM>, and capping layer <NUM> that are on the top surface of dielectric stack <NUM> are removed and planarized by CMP, wet etch, and/or dry etch processes. A recess then can be formed in the upper portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel <NUM> and capping layer <NUM> in the upper portion of the channel hole. Channel plug <NUM> then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure <NUM> is thereby formed through dielectric stack <NUM> and sacrificial layer <NUM> into P-type doped region <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an opening extending vertically through the dielectric stack into the sacrificial layer in the recess is formed. In some embodiments, a lateral dimension of the recess is greater than a lateral dimension of the opening.

As illustrated in <FIG>, a slit <NUM> is an opening formed that extends vertically through dielectric stack <NUM> into sacrificial layer <NUM> in recess <NUM>, which exposes part of sacrificial layer <NUM> in recess <NUM>. In some embodiments, recess <NUM> is an enlarged recess with a lateral dimension in the x-direction greater than that of slit <NUM>. Slit <NUM> can be first patterned using lithography process to be aligned with recess <NUM> laterally. The enlarged dimension of recess <NUM> can increase the overlay margin in the lateral direction. In some embodiments, fabrication processes for forming slit <NUM> further include wet etch and/or dry etch processes, such as DRIE. The existence of recess <NUM> filled with sacrificial layer <NUM> can increase the gouging margin of slit <NUM> in the vertical direction. That is, the etching of slit <NUM> no longer has to stop in sacrificial layer <NUM> above the top surface of the substrate and may stop in sacrificial layer <NUM> in recess <NUM>. It is understood that the etching of slit <NUM> may stop at any depth in sacrificial layer <NUM>. As a result, the gouging variation requirement among different slits <NUM> can be relaxed, thereby improving the production yield. In some embodiments, a spacer <NUM> is formed along the sidewall of slit <NUM> by depositing one or more dielectrics, such as high-k dielectrics, along the sidewall of slit <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the sacrificial layer is replaced, through the opening, with an N-type doped semiconductor layer between the P-type doped region and the dielectric stack. In some embodiments, to replace the sacrificial layer with the N-type doped semiconductor layer, the sacrificial layer is removed to form a cavity between the P-type doped region and the dielectric stack, part of the memory film is removed to expose part of the semiconductor channel along the sidewall of the channel hole, and N-type doped polysilicon is deposited into the cavity to form the N-type doped semiconductor layer. In some embodiments, to deposit the N-type doped polysilicon into the cavity, the polysilicon is in-situ doped with a uniform doping concentration profile to fill the cavity.

As illustrated in <FIG>, sacrificial layer <NUM> (shown in <FIG>) is removed by wet etching and/or dry etching to form a cavity <NUM> as well as to reopen recess <NUM>. In some embodiments, sacrificial layer <NUM> includes polysilicon, spacer <NUM> includes a high-k dielectric, and sacrificial layer <NUM> is etched by applying tetramethylammonium hydroxide (TMAH) etchant through slit <NUM>, which can be stopped by the high-k dielectric of spacer <NUM> as well as the pad oxide layer between sacrificial layer <NUM> and P-type doped region <NUM>. That is, the removal of sacrificial layer <NUM> does not remove dielectric stack <NUM> and P-type doped region <NUM>, according to some embodiments. Sacrificial layer <NUM> in recess <NUM> can be removed as well to reopen recess <NUM>.

As illustrated in <FIG>, part of memory film <NUM> exposed in cavity <NUM> is removed to expose part of semiconductor channel <NUM> along the sidewall of channel structure <NUM>. In some embodiments, parts of the blocking layer (e.g., including silicon oxide), storage layer (e.g., including silicon nitride), and tunneling layer (e.g., including silicon oxide) are etched by applying etchants through slit <NUM> and cavity <NUM>, for example, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide. The etching can be stopped by spacer <NUM> and semiconductor channel <NUM>. That is, the removal of part of memory film <NUM> exposed in cavity <NUM> does not remove dielectric stack <NUM> (protected by spacer <NUM>) and semiconductor channel <NUM> including polysilicon and capping layer <NUM> enclosed by semiconductor channel <NUM>, according to some embodiments. In some embodiments, the pad oxide layer (including silicon oxide) is removed as well by the same etching process.

As illustrated in <FIG>, an N-type doped semiconductor layer <NUM> is formed between P-type doped region <NUM> and dielectric stack <NUM>. In some embodiments, N-type doped semiconductor layer <NUM> is formed by depositing polysilicon into cavity <NUM> (shown in <FIG>) through slit <NUM> using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. In some embodiments, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing polysilicon to form N-type doped semiconductor layer <NUM>. N-type doped semiconductor layer <NUM> can fill cavity <NUM>, such that N-type doped semiconductor layer <NUM> is in contact with the exposed part of semiconductor channel <NUM> of channel structure <NUM>. Since N-type doped semiconductor layer <NUM> is formed by deposition, as opposed to epitaxial growth from the exposed part of semiconductor channel <NUM>, the surface conditions (e.g., cleanness) of semiconductor channel <NUM> do not affect the formation of N-type doped semiconductor layer <NUM>, according to some embodiments. Moreover, N-type doped semiconductor layer <NUM> can be a single polysilicon layer with a uniform doping concentration profile between P-type doped region <NUM> and dielectric stack <NUM> formed by a single polysilicon deposition process with in-situ doping.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an N-type doped semiconductor plug is formed in the recess. In some embodiments, to form the N-type doped semiconductor plug, single crystalline silicon is epitaxially grown to fill the recess, and the single crystalline silicon is in-situ doped.

As illustrated in <FIG>, N-type doped semiconductor layer <NUM> formed in recess <NUM> (shown in <FIG>) and along the sidewall of slit <NUM> is removed using wet etching and/or dry etching to expose P-type doped region <NUM> in recess <NUM>. The etching process can be controlled (e.g., by controlling the etching rate and/or time), such that N-type doped semiconductor layer <NUM> still remains between P-type doped region <NUM> and dielectric stack <NUM> and in contact with semiconductor channel <NUM> of channel structure <NUM>. In some embodiments, the etching of N-type doped semiconductor layer <NUM> formed in recess <NUM> (e.g., etching of polysilicon deposited on the sidewall of recess <NUM>) results in the remainder of recess <NUM> having a shape with nonuniform lateral dimension (e.g., in the x-direction) along the vertical direction. For example, as shown in <FIG>, the lateral dimension of a lower portion of the remainder of recess <NUM> surrounded by P-type doped region <NUM> may be greater than the lateral dimension of an upper portion of the remainder of recess <NUM> surrounded by N-type doped semiconductor layer <NUM>.

As illustrated in <FIG>, an N-type doped semiconductor plug <NUM> is formed in recess <NUM>. In some embodiments, N-type doped semiconductor plug <NUM> is formed by epitaxially growing single crystalline silicon from P-type doped region <NUM> in any suitable direction (e.g., from the bottom and sidewalls) to fill the remainder of recess <NUM>. In some embodiments, the shape of N-type doped semiconductor plug <NUM> is substantially the same as the shape of the remainder of recess <NUM>. For example, the lateral dimension of a lower portion of N-type doped semiconductor plug <NUM> surrounded by P-type doped region <NUM> may be greater than the lateral dimension of an upper portion of N-type doped semiconductor plug <NUM> surrounded by N-type doped semiconductor layer <NUM>. The fabrication processes for epitaxially growing N-type doped semiconductor plug <NUM> can include pre-cleaning recess <NUM> followed by, for example, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof. In some embodiments, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when epitaxially growing single crystalline silicon to form N-type doped semiconductor plug <NUM>. In some embodiments, N-type doped semiconductor plug <NUM> fully fills recess <NUM> using epitaxial growth process, which is difficult to achieve using deposition process due to the enlarged dimension of recess <NUM> compared with slit <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the dielectric stack is replaced, through the opening, with a memory stack. As illustrated in <FIG>, spacer <NUM> (as shown in <FIG>) covering the sidewalls of slit <NUM> is removed using wet etching and/or dry etching to expose stack sacrificial layers <NUM> (as shown in <FIG>) of dielectric stack <NUM>. A memory stack <NUM> can be formed by a gate replacement process, i.e., replacing stack sacrificial layers <NUM> with stack conductive layers <NUM>. Memory stack <NUM> thus can include interleaved stack conductive layers <NUM> and stack dielectric layers <NUM> on N-type doped semiconductor layer <NUM>. In some embodiments, to form memory stack <NUM>, stack sacrificial layers <NUM> are removed by applying etchants through slit <NUM> to form a plurality of lateral recesses. Stack conductive layers <NUM> then can be deposited into the lateral recesses by depositing one or more conductive materials using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combinations thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a source contact structure is formed in the opening to be in contact with the N-type doped semiconductor plug. As illustrated in <FIG>, a spacer <NUM> including one or more dielectrics, such as silicon oxide, is formed along the sidewall of slit <NUM> using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combinations thereof. As illustrated in <FIG>, a source contact <NUM> is formed over spacer <NUM> to fill the remaining space of slit <NUM> (as shown in <FIG>) to be in contact with N-type doped semiconductor plug <NUM>. In some embodiments, source contact <NUM> is formed by first depositing an adhesion layer (e.g., including TiN) over spacer <NUM>, followed by depositing polysilicon in the lower portion of slit <NUM> and a metal (e.g., W) in the upper portion of slit <NUM> using one or more thin film deposition processes, such as PVD, CVD, ALD, electroplating, electroless plating, or any combinations thereof, to fill slit <NUM>. A source contact structure <NUM> including spacer <NUM> and source contact <NUM> above and in contact with N-type doped semiconductor plug <NUM> is hereby formed, according to some embodiments.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional (3D) memory device (<NUM>), comprising:
a P-type doped region (<NUM>, <NUM>) of a substrate;
an N-type doped semiconductor layer (<NUM>, <NUM>) on the P-type doped region (<NUM>, <NUM>);
a memory stack (<NUM>, <NUM>) comprising interleaved conductive layers (<NUM>) and dielectric layers (<NUM>) on the N-type doped semiconductor layer (<NUM>, <NUM>);
a channel structure (<NUM>, <NUM>) extending vertically through the memory stack (<NUM>, <NUM>) and the N-type doped semiconductor layer (<NUM>, <NUM>) into the P-type doped region (<NUM>, <NUM>) wherein the channel structure (<NUM>, <NUM>) comprises a memory film (<NUM>, <NUM>) and a semiconductor channel (<NUM>), and part of the semiconductor channel (<NUM>) along the sidewall of the channel structure (<NUM>, <NUM>) is in contact with the N-type doped semiconductor layer (<NUM>, <NUM>);
an N-type doped semiconductor plug (<NUM>, <NUM>) extending vertically into the P-type doped region (<NUM>, <NUM>); and
a source contact structure (<NUM>) extending vertically through the memory stack (<NUM>, <NUM>) to be in contact with the N-type doped semiconductor plug (<NUM>, <NUM>),
wherein a lateral dimension of the N-type doped semiconductor plug (<NUM>, <NUM>) is greater than a lateral dimension of the source contact structure (<NUM>), wherein a lateral dimension of a portion of the N-type doped semiconductor plug (<NUM>, <NUM>) surrounded by the P-type doped region (<NUM>, <NUM>) is greater than a lateral dimension of a portion of the N-type doped semiconductor plug (<NUM>, <NUM>) surrounded by the N-type doped semiconductor layer (<NUM>, <NUM>),
wherein a lateral dimension of N-type doped semiconductor plug (<NUM>, <NUM>) is the minimum lateral dimension along the vertical direction, and a lateral dimension of source contact structure (<NUM>) is the maximum lateral dimension along the vertical direction, such that any lateral dimension of N-type doped semiconductor plug (<NUM>, <NUM>) is greater than any lateral dimension of the source contact structure (<NUM>).