Patent Description:
To reduce the chance that a failure of a physical or logical memory impacts a user, computing devices may utilize a built-in self-test (BIST) component. A BIST component can be included in a device to detect faults in circuitry generally. In the context of memory circuitry, a memory built-in self-test (MBIST) component can detect faults in the memory of a computing device. To do so, the MBIST component can store known values as data in a memory location and then retrieve the stored data from the location. If the retrieved data fails to match the known values, the MBIST component may infer that the memory is faulty.

<CIT> describes methods for adjustable column address scramble using fuses.

This document describes techniques and apparatuses for logical memory repair with a shared physical memory. A memory cluster can include multiple logical memories that are overlaid on multiple physical memories. For instance, a memory cluster may overlay two or more logical memories on a single physical memory such that the physical memory is shared by at least two logical memories. The memory cluster also includes a shared bus interface that enables components external to the memory cluster to access the logical memories without knowledge of the underlying physical memories. A memory built-in self-test (MBIST) controller may be located external of the memory cluster to enable the MBIST controller to test the multiple logical memories using, for instance, standardized MBIST algorithms. The MBIST controller may include built-in repair analysis (BIRA) functionality. The logic realizing the BIRA functionality can produce built-in self-repair (BISR) parameters on a per-logical-memory basis. The repair logic of each individual physical memory may be unable to process the BISR parameters properly because the MBIST controller produced the BISR parameters in terms of logical memories without considering the underlying physical memory. This can result in memory errors or nondeterministic signaling states that render an entire memory cluster defective and thus necessitate scrapping a whole integrated circuit chip.

To avoid creating such a defective memory condition, each physical memory of multiple physical memories of a memory cluster can include arbitration logic. The arbitration logic of an instance of physical memory can form at least part of a memory wrapper that supports memory portion redundancy for the physical memory instance in a manner that is transparent to an MBIST controller that is external to the memory cluster. This transparency enables an MBIST controller to test and repair multiple logical memories without accounting for the architecture of the underlying physical memory or memories. By enabling the MBIST controller to test logical memories from outside the memory cluster, the MBIST controller can employ and rely on time-tested MBIST algorithms.

The arbitration logic can be coupled between one or more registers holding BISR parameters and repair logic, which includes at least one repair port, that feeds into a memory decoder. In example operations, the arbitration logic converts from logical-memory level BISR parameters that are set by the external MBIST controller to physical-memory level signaling that can be utilized by the repair logic of the physical memory. In some cases, the arbitration logic can include one or more repair control ports that convert a targeted address and BISR parameters to signals that the at least one repair port of the repair logic properly interprets to replace faulty memory portions of the single physical memory as intended by the MBIST controller. For instance, arbitration logic can ensure that the repair logic does not attempt to simultaneously activate two replacement memory portions when a same faulty memory address is detected twice in the shared physical memory across the two or more logical memories.

In example aspects, an apparatus for logical memory repair is described. The apparatus includes a memory built-in self-test controller including circuitry that is configured to perform at least one test on multiple logical memories. The apparatus also includes a memory cluster that includes a shared bus interface and multiple physical memories. The shared bus interface is coupled to the memory built-in self-test controller and configured to provide access to the multiple logical memories. The multiple physical memories are coupled to the shared bus interface. The multiple physical memories include at least one physical memory configured to have two or more logical memories of the multiple logical memories overlaid thereon. The at least one physical memory includes a first address register configured to store a first faulty memory address as determined by the memory built-in self-test controller and a second address register configured to store a second faulty memory address as determined by the memory built-in self-test controller. The at least one physical memory also includes arbitration logic coupled to the first address register and the second address register. The arbitration logic includes circuitry configured to arbitrate access to at least one spare memory portion responsive to the first faulty memory address conflicting with the second faulty memory address.

In example aspects, a method for logical memory repair is described. The method includes performing, by a memory built-in self-test controller, at least one test on multiple logical memories. The method also includes identifying, by the memory built-in self-test controller, two or more faulty memory portions of at least one physical memory based on the performing. The method additionally includes loading, by the memory built-in self-test controller, a first address register with a first faulty memory address and a second address register with a second faulty memory address based on the identifying. The method further includes arbitrating, by the at least one physical memory, access to at least one spare memory portion, which corresponds to the two or more faulty memory portions, responsive to the first faulty memory address conflicting with the second faulty memory address.

In example aspects, an apparatus for logical memory repair is described. The apparatus includes a memory built-in self-test controller including circuitry configured to perform at least one test on multiple logical memories. The apparatus also includes a memory cluster. The memory cluster includes a shared bus interface coupled to the memory built-in self-test controller and configured to provide access to the multiple logical memories. The memory cluster also includes at least one physical memory coupled to the shared bus interface and configured to have two or more logical memories of the multiple logical memories overlaid thereon. The at least one physical memory includes one or more built-in self-repair registers configured to store one or more built-in self-repair parameters established by the memory built-in self-test controller based on the at least one test performed on the multiple logical memories. The at least one physical memory also includes repair logic and an address decoder coupled to the repair logic. The at least one physical memory further includes arbitration logic coupled between the one or more built-in self-repair registers and the repair logic. The arbitration logic includes circuitry configured to convert the built-in self-repair parameters into physical-memory level built-in self-repair parameters.

In other example aspects, techniques, processes, and computer-readable media for performing logical memory repair are disclosed. This Summary is provided to introduce simplified concepts of techniques, methods, and apparatuses for logical memory repair, the concepts of which are further described below in the Detailed Description and depicted in the Drawings.

The details of one or more aspects of logical memory repair are described below. The use of the same reference numbers in different instances in the description and the figures may indicate similar elements:.

Although features and concepts of the described techniques and apparatuses for logical memory repair can be implemented in any number of different environments, aspects are described in the context of the following examples.

This document describes techniques and apparatuses for logical memory repair with a shared physical memory. An example type of memory organization that is used in computing devices is called a memory cluster. A memory cluster includes multiple physical memories that are interconnected via a shared bus. The memory cluster can also overlay multiple logical memories over the multiple physical memories. For instance, a single physical memory of the multiple physical memories may correspond to, include, or otherwise be shared by two logical memories of the multiple logical memories. The memory cluster also includes a shared bus interface that enables components external to the memory cluster to access the logical memories. Thus, in at least some cases, components that are external to the memory cluster cannot readily access the physical memories directly. Instead, an external component uses the storage resources of the memory cluster by accessing a logical memory through the shared bus interface.

A memory built-in self-test (BIST) controller may also be located external of a memory cluster. This arrangement can enable the memory BIST (MBIST) controller to test the multiple logical memories in a same manner as the logical memories are used by other external components. General MBIST techniques provide memory tests that are usually independent of the design or architectures in which such techniques are employed. Adding MBIST directly to the physical memories of a memory cluster would negatively impact the timing and performance of a shared bus architecture. Consequently, for purposes of MBIST testing, the MBIST controller and a test access port (TAP) are often located outside of the memory cluster. Thus, the circuitry used to access the logical memories is implemented in the MBIST interface outside the memory cluster. This approach preserves the performance of the shared bus while maintaining the benefits of self-test, analysis/debug, and repair associated with MBIST techniques.

MBIST technology that operates on logical memories through a shared bus interface has an architecture that does not interface directly with the physical memories being tested. The external MBIST controller may treat each logical memory as a separate test target, regardless of the number of whole or partial physical memories covered by a given logical memory. An MBIST controller can also include built-in self-repair (BISR) and/or built-in repair-analysis (BIRA) technology for use with shared-bus applications. The BISR registers that store BISR parameters resulting from BIRA, however, are located inside the memory cluster because such registers may be associated with particular physical memories to drive one or more corresponding memory repair ports of repair logic of each physical memory. This is acceptable because the BISR registers need not be located on the shared bus or other performance-critical paths. In some cases, the MBIST controller can use a separate serial port to load the self-repair registers.

As part of a testing operation, an MBIST controller applies specialized memory testing routines that include storing and retrieving data in particular patterns and orders to "stress" the memory arrays. The testing routines thereby elicit potential failure responses for memory locations that are part of an identifiable memory portion. The MBIST controller can include BIRA logic that establishes a replacement memory portion in response to detecting a faulty memory portion, such as a faulty memory row or column. During the testing of a memory cluster, the MBIST controller may sequentially test the logical memories thereof. Accordingly, the MBIST controller establishes BISR parameters for each logical memory separately from those of other logical memories and without regard for at least one underlying physical memory, including potentially a shared physical memory. If two or more logical memories overlay a same physical memory (e.g., a shared physical memory), for instance, the repair logic of that shared physical memory may be unable to properly identify or employ a replacement memory portion responsive to BISR parameters that conflict or cause conflicts due to the serialized analysis that does not consider underlying physical interrelationships. In short, this BISR malfunction can occur during regular, non-testing memory operations because the BISR parameters are determined in isolation with respect to each other.

To counteract such conflicts, in example implementations, each physical memory of multiple physical memories of a memory cluster can include arbitration logic. The arbitration logic is coupled between the repair logic of the physical memory and the BISR registers that store BISR parameters from the BIRA process. The arbitration logic can convert the BISR parameters that are determined at a logical-memory level to signaling (e.g., to one or more BISR values or voltages) that enable the repair logic to correctly operate the physical memory. This enables the repair logic to correctly select a spare memory portion for memory accessing responsive to a targeted memory portion being replaced by the BIRA process. For example, the arbitration logic can include one or more repair control ports that convert a targeted address and BISR parameters to signals that one or more repair ports of the repair logic can properly interpret to replace faulty memory portions as intended by the MBIST controller.

In some implementations, the arbitration logic of a respective physical memory can form at least part of a memory wrapper that supports memory portion redundancy in a manner that is transparent to an MBIST controller that is external to a memory cluster of the physical memory. This transparency enables one MBIST controller to test and repair multiple logical memories of the memory cluster without accounting for the underlying physical memory or memories. This, in turn, enables the MBIST controller to employ and rely on known, reliable MBIST algorithms.

Certain implementations can also increase repair coverage by enabling the use of all spare memory portions if required by a determined quantity of faulty memory portions. Thus, there need not be any bits that are automatically deemed irreparable. The strategies described herein can provide a lower defective parts per million (DPPM) by accounting for the potential conflicts described herein. The architecture can also offer an area improvement because although dedicated physical memories may have multiple instances of repair logic and associated BISR registers, a shared physical memory can be constructed with a single set of repair ports for a single instance of repair logic in some cases as described herein. Further, the arbitration logic need not add gates in a timing-critical path because the start-points can be from pseudo-static fuse registers. Other example implementations and advantages are described herein.

<FIG> illustrates an example operating environment <NUM> in which logical memory repair with a shared physical memory may be implemented. <FIG> illustrates, at <NUM> generally, an example apparatus <NUM> with an integrated circuit <NUM> (IC <NUM>). In this example, the apparatus <NUM> is depicted as a smartphone. However, the apparatus <NUM> may be implemented as any suitable computing or electronic device.

Examples of the apparatus <NUM> include a mobile electronic device, mobile communication device, modem, cellular or mobile phone, mobile station, gaming device, navigation device, media or entertainment device (e.g., a media streamer or gaming controller), laptop computer, desktop computer, tablet computer, smart appliance, vehicle-based electronic system, wearable computing device (e.g., goggles, watch, or clothing), Internet of Things (IoTs) device, sensor, stock management device, electronic portion of a machine or a piece of equipment, server computer or portion thereof (e.g., a server blade or rack), and the like. Illustrated examples of the apparatus <NUM> include a tablet device <NUM>-<NUM>, a smart television <NUM>-<NUM>, a desktop computer <NUM>-<NUM>, a server computer <NUM>-<NUM>, a smartwatch <NUM>-<NUM>, a smartphone (or document reader) <NUM>-<NUM>, and intelligent glasses <NUM>-<NUM>.

In example implementations, the apparatus <NUM> includes at least one integrated circuit <NUM>. The integrated circuit <NUM> can be mounted on a printed circuit board (PCB) (not shown). Examples of a PCB include a flexible PCB, a rigid PCB, a single or multi-layered PCB, a surface-mounted or through-hole PCB, combinations thereof, and so forth. Each integrated circuit <NUM> can be realized as a general-purpose processor, a system-on-chip (SoC), a security-oriented IC, a memory chip, a communications IC (e.g., a modem or a radio-frequency IC), a graphics processor, an artificial intelligence (AI) processor, combinations thereof, and so forth.

As shown, the integrated circuit <NUM> includes at least one memory cluster <NUM> coupled to a memory built-in self-test controller <NUM> (MBIST controller <NUM>) and multiple other components (not shown). The memory cluster <NUM> includes at least one physical memory <NUM> with one or more associated logical memories. The associated logical memories may include at least a logical memory <NUM>-<NUM> and a logical memory <NUM>-<NUM>. Although shown as being part of a single integrated circuit <NUM>, the memory cluster <NUM> and the MBIST controller <NUM> may be disposed on separate integrated circuits and/or separate printed circuit boards.

The physical memory <NUM> features arbitration logic <NUM> utilized in a repair of the physical memory <NUM> in conjunction with the MBIST controller <NUM>. The memory cluster <NUM> overlays a first logical memory <NUM>-<NUM> and a second logical memory <NUM>-<NUM> over the physical memory <NUM> such that the physical memory <NUM> is shared by the two logical memories. In example operations, the MBIST controller <NUM> may detect multiple faulty memory locations that correspond to multiple faulty memory addresses. In some cases, each logical memory <NUM> may include at least one respective faulty memory address, which can lead to conflicts between two or more faulty memory addresses.

To address such situations with multiple faulty memory addresses, the arbitration logic <NUM> can arbitrate access to at least one spare memory portion responsive to a first faulty memory address conflicting with a second faulty memory address. This is described further with reference to <FIG> and <FIG>. The memory cluster <NUM> and the MBIST controller <NUM> may be integrated on a single IC as shown; alternatively, two or more components, such as instances of logic and/or memory arrays, may be distributed across two or more ICs. Examples of a memory cluster <NUM> that includes at least one physical memory <NUM> and multiple logical memories <NUM> are described next with reference to <FIG> and <FIG>.

<FIG> illustrates an example architecture <NUM> that can relate to logical memory repair including the memory cluster <NUM> and the MBIST controller <NUM>. The example architecture <NUM> includes a shared bus interface <NUM> that is part of, or integrated with, the memory cluster <NUM>. As shown, the shared bus interface <NUM> may include mapping logic <NUM>. A test access port <NUM> (TAP <NUM>) can be coupled to the MBIST controller <NUM> to enable control of the MBIST controller <NUM> by another processor or circuit. The MBIST controller <NUM> can be coupled to the memory cluster <NUM> via the shared bus interface <NUM>. The components of the memory cluster <NUM> may be integrated onto a single circuit or distributed across multiple integrated circuits and/or disposed on one or across multiple printed circuit boards.

In example implementations, a component that is external to the memory cluster <NUM> may use a logical address <NUM> to access the memories thereof. Within the memory cluster <NUM>, however, the physical memories may be addressed using a physical address <NUM>. To accommodate different addressing schemes (e.g., logical addresses external to the memory cluster <NUM> and physical addresses internal to the memory cluster <NUM>), the shared bus interface <NUM> can include mapping logic <NUM>. The mapping logic <NUM> maps between logical addresses <NUM> and physical addresses <NUM>. Thus, for a communication (e.g., a memory request) propagating from the MBIST controller <NUM> to a physical memory <NUM>, the mapping logic <NUM> converts a logical address <NUM> to a corresponding physical address <NUM>. For a memory response that is part of a testing procedure, the mapping logic <NUM> can convert a physical address <NUM> to a corresponding logical address <NUM>.

As shown, the memory cluster <NUM> can include multiple physical memories <NUM>-<NUM> to <NUM>-<NUM> and a shared bus <NUM>. Although not explicitly shown in <FIG>, each physical memory <NUM> is coupled to the shared bus <NUM>, and the shared bus <NUM> is coupled to the shared bus interface <NUM>. Thus, each physical memory <NUM> can be coupled to the shared bus interface <NUM> via the shared bus <NUM>. Of the multiple physical memories <NUM>-<NUM> to <NUM>-<NUM>, each respective physical memory <NUM> can include respective arbitration logic <NUM>. The memory cluster <NUM> can also include multiple logical memories <NUM>-<NUM> to <NUM>-<NUM>, which are described below. Although five physical memories <NUM> and seven logical memories <NUM> are shown, a given memory cluster <NUM> may have more or fewer than five or seven physical or logical memories, respectively. Further, a one-to-one correspondence between physical memories and logical memories may not be created, as is described next.

In some cases, a single physical memory may share multiple logical memories. For example, the memory cluster <NUM> features a first physical memory <NUM>-<NUM> (PM1) with a first logical memory <NUM>-<NUM> (LM1) and a second logical memory <NUM>-<NUM> (LM2) overlaid thereon. The physical memory <NUM>-<NUM> features arbitration logic <NUM> to arbitrate access to at least one spare memory portion thereof. An example instance that is analogous to these cases is described below with reference to <FIG>. Examples in which spare memory portions correspond to memory rows in scenarios like these cases are described below with reference to <FIG> and <FIG>.

In other cases, multiple physical memories may correspond to a single logical memory. For example, the memory cluster <NUM> also features a second physical memory <NUM>-<NUM> (PM2) and a third physical memory <NUM>-<NUM> (PM3) that are associated with a single logical memory, a third logical memory <NUM>-<NUM> (LM3). The third logical memory <NUM>-<NUM> is distributed across two physical memories in such cases. The second physical memory <NUM>-<NUM> and the third physical memory <NUM>-<NUM> each features respective arbitration logic <NUM> to arbitrate access to at least one spare memory portion of the respective physical memory.

In still other cases, multiple physical memories may share multiple logical memories. For example, the memory cluster <NUM> also features a fourth physical memory <NUM>-<NUM> (PM4) and a fifth physical memory <NUM>-<NUM> (PM5) that correspond to a fourth logical memory <NUM>-<NUM> (LM4), a fifth logical memory <NUM>-<NUM> (LM5), a sixth logical memory <NUM>-<NUM> (LM6), and a seventh logical memory <NUM>-<NUM> (LM7). Each of the fourth, fifth, sixth, and seventh logical memories <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> is distributed across the fourth and fifth physical memories <NUM>-<NUM> and <NUM>-<NUM>. The fourth physical memory <NUM>-<NUM> and the fifth physical memory <NUM>-<NUM> each features arbitration logic <NUM> to arbitrate access to at least one spare memory portion of the respective physical memory. Examples in which spare memory portions correspond to memory columns in scenarios like these cases are described below with reference to <FIG>.

<FIG> illustrates an example arrangement <NUM> of multiple logical memories and at least one physical memory in which logical memory repair with a shared physical memory may be performed. As illustrated in <FIG>, a physical memory <NUM> is shared by two or more logical memories: a logical memory <NUM>-<NUM> and a logical memory <NUM>-<NUM>. The physical memory <NUM> can include a repair port <NUM>. The repair port <NUM> may include circuitry associated with one or more built-in self-repair (BISR) registers <NUM>-<NUM> and <NUM>-<NUM>. Each BISR register <NUM> can include one or more flip-flops, with each flip-flop storing one bit of a BISR parameter.

In example implementations, the first and second BISR registers <NUM>-<NUM> and <NUM>-<NUM> may each store a faulty memory address (e.g., a faulty row address or an indication of a faulty column, such as an identified column of bits) and an indication of whether the corresponding BISR register <NUM> has been enabled. More generally, each BISR register <NUM> can store at least one Faulty memory Portion Address (FPA) and at least one Redundant memory Portion ENable (RPEN) indication. The faulty memory portion address may include at least as many bits as are used to identify the memory portion, and the redundant memory portion enable indication may include one bit. Values from the first and second BISR registers <NUM>-<NUM> and <NUM>-<NUM> are fed to the repair port <NUM>, which may be associated with repair logic (not shown).

The physical memory <NUM> may be coupled to a first MBIST interface <NUM>-<NUM> and to a second MBIST interface <NUM>-<NUM> to access (e.g., send or receive) a data signal, such as to obtain a data output signal (DOUT). In this example, the physical memory <NUM> is wider than the two logical memories. As shown, each logical memory data out signal is "m" bits wide (LM_DOUT [m:<NUM>]). This "m-bits" width is half the bit-width of the underlying physical memory, which extends from DOUT [n-<NUM>:n/<NUM>] in one "half' and from DOUT [n/<NUM>-<NUM>:<NUM>] in the other "half' of memory. If each logical memory were wider than the underlying physical memory, the physical memory would not be tested twice. However, with each logical memory being narrower than the physical memory, the physical memory is tested twice-once for each logical memory-but not in a manner where the testing component can intelligently account for the double testing procedure in terms of accurately implementing a memory repair, as is described next.

In example operations, the MBIST controller <NUM> (e.g., of <FIG> and <FIG>) accesses the physical memory <NUM> in terms of the first logical memory <NUM>-<NUM> and the second logical memory <NUM>-<NUM> via the first MBIST interface <NUM>-<NUM> and the second MBIST interface <NUM>-<NUM>, respectively. The MBIST controller <NUM> tests part of the physical memory <NUM> using the first MBIST interface <NUM>-<NUM> in accordance with the size and data widths of the first logical memory <NUM>-<NUM>. The MBIST controller <NUM>, therefore, populates the first BISR registers <NUM>-<NUM> based on test results that are obtained via the first MBIST interface <NUM>-<NUM> in terms of the first logical memory <NUM>-<NUM>.

The MBIST controller <NUM> then tests another part of the physical memory <NUM> using the second MBIST interface <NUM>-<NUM> in accordance with the size and data widths of the second logical memory <NUM>-<NUM>. The MBIST controller <NUM>, therefore, populates the second BISR registers <NUM>-<NUM> based on test results that are obtained via the second MBIST interface <NUM>-<NUM> in terms of the second logical memory <NUM>-<NUM>. Moreover, the MBIST controller <NUM> may be uninformed that these two tests for the two logical memories pertain to a same underlining physical memory or that the first and second BISR registers <NUM>-<NUM> and <NUM>-<NUM> relate to a common memory.

This can result in a situation where a same faulty memory portion address (FPA) is stored twice, once each in two or more different BISR registers. Such a situation can cause a conflict responsive to a subsequent access of the physical memory <NUM> in a standard, non-testing memory mode in which this same faulty memory portion address is targeted by a memory access request. For example, two memory portion redundancy-enable signals (e.g., two replacement enablement signals) may be activated at the same time, which can create a failure condition in a memory address decoder. To counter such a scenario, certain described implementations realize a memory wrapper that can transparently support memory portion redundancy in a memory cluster environment. Example memory wrapper implementations are described next with reference to <FIG>.

<FIG> illustrates an example architecture <NUM> for implementing a memory wrapper with arbitration logic that can be used for performing logical memory repair. In example implementations, the physical memory <NUM> includes a memory wrapper <NUM> that supports memory portion redundancy in a cluster memory environment. The memory wrapper <NUM> enables the MBIST controller <NUM> to perform memory tests on logical memories without adjusting for one or more underlying physical memories.

As shown, the physical memory <NUM> includes at least one instance of repair logic <NUM>, at least one address decoder <NUM>, at least one memory array <NUM>, and data input/output logic <NUM> (data I/O logic <NUM>). The address decoder <NUM> can be coupled between the repair logic <NUM> and the memory array <NUM>. The data I/O logic <NUM> can be coupled between the memory array <NUM> and the shared bus <NUM>. The repair logic <NUM> provides at least one BISR indicator signal <NUM> (e.g., one or more memory portion redundancy-enable signals) to the address decoder <NUM>. The BISR indicator signal <NUM> indicates whether a spare memory portion (not shown in <FIG>) is to be accessed based on an address <NUM> that is being targeted by a memory access request and one or more BISR parameters of the BISR registers <NUM>-<NUM> and <NUM>-<NUM>.

In some implementations, the arbitration logic <NUM> is coupled between the BISR registers <NUM>-<NUM> and <NUM>-<NUM> and the repair logic <NUM>. The repair logic <NUM> may be coupled between the arbitration logic <NUM> and the address decoder <NUM>. The first and second BISR registers <NUM>-<NUM> and <NUM>-<NUM> may be coupled between the shared bus <NUM> and the arbitration logic <NUM>. The arbitration logic <NUM> interprets BISR parameters stored in the BISR registers <NUM>-<NUM> and <NUM>-<NUM> for at least one repair port (not shown) of the repair logic <NUM>.

As part of the interpretation, the arbitration logic <NUM> can convert the BISR parameters to account for one or more logical memories that are overlaid on the physical memory <NUM>. To do so, the arbitration logic <NUM> may implement two or more repair control ports, such as at least one default repair control port <NUM> and at least one pseudo repair control port <NUM>. The repair control ports can enable the repair of a faulty memory portion, such as a faulty row or a faulty column, that is identified via testing of two or more logical memories. Generally, the repair logic <NUM> can direct a memory access request to a spare memory portion based on a memory address <NUM> that is targeted by a memory access request and at least one faulty memory address, such as a first faulty memory address and a second faulty memory address, that is stored in at least one BISR register <NUM>.

In example operations, the data I/O logic <NUM> can store information into the memory array <NUM> or load information from the memory array <NUM> as part of one or more memory operations. The I/O logic <NUM> can communicate or propagate information between the memory array <NUM> and the shared bus interface <NUM> via the shared bus <NUM>. The MBIST controller <NUM> operates through the shared bus interface <NUM> to perform a test on multiple addresses of at least one logical memory <NUM>, such as the address <NUM> (e.g., a memory address). The address <NUM>, which may be a physical address within the memory cluster, can be provided to the address decoder <NUM> and the repair logic <NUM>. The arbitration logic <NUM> can also receive the address <NUM> to perform the arbitration in some cases.

The memory wrapper <NUM> can include (e.g., have or realize) multiple repair control ports, such as one repair control port per logical memory that is overlaid on the physical memory <NUM>. Each respective logical memory <NUM> can correspond to a respective virtual repair control port created by the arbitration logic <NUM>. As shown, the multiple repair control ports can include a default repair control port <NUM> and pseudo repair control port <NUM>.

In some cases, the default repair control port <NUM> corresponds to a logical memory <NUM> that the MBIST controller <NUM> tests first. Each logical memory <NUM> that is tested subsequently can correspond to a pseudo repair control port like the pseudo repair control port <NUM>. Thus, the first logical memory <NUM>-<NUM> can correspond to the default repair control port <NUM>, the second logical memory <NUM>-<NUM> can correspond to the depicted pseudo repair control port <NUM>, and a third logical memory (not shown in <FIG>) can correspond to another pseudo repair control port <NUM> (not shown). Examples of repair control ports are described herein with reference to <FIG>.

<FIG> illustrates architecture <NUM> including arbitration logic and memory components for performing logical memory repair with at least one spare memory portion acccording to the invention. As shown the physical memory <NUM> includes the arbitration logic <NUM>, the repair logic <NUM>, the address decoder <NUM>, and the memory array <NUM>. The memory array <NUM> includes multiple memory portions, such as a first memory portion <NUM>-<NUM> and a second memory portion <NUM>-<NUM>. Each memory portion <NUM> can correspond to, for example, at least one memory row or at least one memory column. To enable redundancy for at least one memory portion <NUM> of the memory array <NUM>, the physical memory <NUM> includes multiple spare memory portions, a first spare memory portion <NUM>-<NUM> and a second spare memory portion <NUM>-<NUM>. Each spare memory portion <NUM> can likewise correspond to at least one spare memory row or at least one spare memory column. The physical memory <NUM> also includes the first BISR register <NUM>-<NUM> and the second BISR register <NUM>-<NUM> to store BISR parameters.

Each BISR register <NUM> includes at least one address register <NUM> and at least one enablement register <NUM>. Thus, the first BISR register <NUM>-<NUM> includes a first address register <NUM>-<NUM> and a first enablement register <NUM>-<NUM>, and the second BISR register <NUM>-<NUM> includes a second address register <NUM>-<NUM> and a second enablement register <NUM>-<NUM>. The first address register <NUM>-<NUM> stores a first faulty memory address as determined by the MBIST controller <NUM>. The second address register <NUM>-<NUM> stores a second faulty memory address as determined by the MBIST controller <NUM>. The first enablement register <NUM>-<NUM> stores an indication that a corresponding first (redundant) spare memory portion is enabled for usage as determined by the MBIST controller <NUM>. The second enablement register <NUM>-<NUM> stores an indication that a corresponding second (redundant) spare memory portion is enabled for usage as determined by the MBIST controller <NUM>.

To enable the arbitration logic <NUM> to analyze the faulty memory address and enablement indication parameters, the arbitration logic <NUM> can be coupled to the first address register <NUM>-<NUM>, the second address register <NUM>-<NUM>, the first enablement register <NUM>-<NUM>, and the second enablement register <NUM>-<NUM>. The arbitration logic <NUM> includes circuitry to arbitrate access to at least one spare memory portion <NUM> responsive to the first faulty memory address conflicting with the second faulty memory address.

In example operations, the circuitry of the MBIST controller <NUM> determines a first faulty memory address corresponding to the at least one physical memory <NUM> by testing the first logical memory <NUM>-<NUM> and/or the second logical memory <NUM>-<NUM>. The circuitry of the MBIST controller <NUM> also determines a second faulty memory address corresponding to the physical memory <NUM> by testing the first logical memory <NUM>-<NUM> and/or the second logical memory <NUM>-<NUM>. The MBIST controller <NUM> can store the faulty memory addresses in the BISR registers <NUM>-<NUM> and <NUM>-<NUM> as part of a BISR procedure.

The first BISR register <NUM>-<NUM> includes the first address register <NUM>-<NUM> and the first enablement register <NUM>-<NUM> indicating if the first BISR register <NUM>-<NUM> has been enabled. For example, the first address register <NUM>-<NUM> can store the first faulty memory address that corresponds to the first memory portion <NUM>-<NUM> responsive to the MBIST controller <NUM> detecting that the first memory portion <NUM>-<NUM> is faulty. Further, the first enablement register <NUM>-<NUM> stores an affirmative indication that the first spare memory portion <NUM>-<NUM> is to be accessed if the first faulty memory address is being targeted-e.g., if the address <NUM> (of <FIG>) corresponds to the first faulty memory address. The second BISR register <NUM>-<NUM> includes the second address register <NUM>-<NUM> and the second enablement register <NUM>-<NUM> indicating if the second BISR register <NUM>-<NUM> has been enabled.

In part because the MBIST controller <NUM> tests the multiple logical memories <NUM>-<NUM> and <NUM>-<NUM> sequentially and at least partially independently, the MBIST controller <NUM> may store a same faulty memory address in the first address register <NUM>-<NUM> and in the second address register <NUM>-<NUM>. Absent the arbitration logic <NUM>, this can cause the repair logic <NUM> to activate two spare memory portions simultaneously-e.g., during a single memory access. The arbitration logic <NUM>, however, operates to prevent this error condition. To do so, the first BISR register <NUM>-<NUM> and the second BISR register <NUM>-<NUM> provide address and enablement information to the arbitration logic <NUM>.

The arbitration logic <NUM> processes the address and enablement BISR parameters to resolve a single spare memory portion <NUM> for accessing if a corresponding memory portion <NUM> was identified as being faulty. The arbitration logic <NUM> provides converted BISR parameter information to one or more repair ports (not shown) of the repair logic <NUM> so that the repair logic <NUM> can activate a single spare memory portion <NUM> for a given memory access using the address decoder <NUM>.

Thus, the physical memory <NUM> includes the repair logic <NUM> to direct a memory access request to a spare memory portion (e.g., <NUM>-<NUM> or <NUM>-<NUM>) based on a memory address <NUM> targeted by a memory access request, a first faulty memory address (e.g., that is stored in the first address register <NUM>-<NUM>), and a second faulty memory address (e.g., that is stored in the second address register <NUM>-<NUM>). To do so, the repair logic <NUM> communicates with the address decoder <NUM>, which is coupled to the memory array <NUM> and/or at least one spare memory portion <NUM>. The repair logic <NUM> may be coupled between the arbitration logic <NUM> and the address decoder <NUM>. The arbitration logic <NUM> can be coupled between the repair logic <NUM> and the BISR registers <NUM>-<NUM> and <NUM>-<NUM>. This can enable the arbitration logic <NUM> to convert one or more BISR parameters that are stored in the BISR registers <NUM>-<NUM> and <NUM>-<NUM> into at least one arbitration signal <NUM> for the one or more repair ports of the repair logic <NUM> to ensure that multiple spare memory portions <NUM>-<NUM> and <NUM>-<NUM> are not simultaneously activated.

During a testing phase, the circuitry of the MBIST controller <NUM> accesses multiple logical memories (e.g., <NUM>-<NUM> and <NUM>-<NUM>) using logical memory addresses. The mapping logic <NUM> of the shared bus interface <NUM> can map the logical memory addresses to physical memory addresses, which are memory addresses associated with the physical memory <NUM>. If the MBIST controller <NUM> determines that the logical memories <NUM>-<NUM> and <NUM>-<NUM> are faulty due to one or more memory locations, the first faulty logical memory (e.g., <NUM>-<NUM>) and the second faulty logical memory (e.g., <NUM>-<NUM>) thus share the same physical address space of the physical memory <NUM>. Consequently, a first faulty memory address and a second faulty memory address may correspond to a common faulty memory portion (e.g., the first memory portion <NUM>-<NUM>) or a same spare memory portion (e.g., the spare memory portion <NUM>-<NUM>) as indicated by the BISR parameters stored in the BISR registers <NUM>-<NUM> and <NUM>-<NUM>. In some of such cases, the circuitry of the arbitration logic <NUM> can route memory requests that are associated with different logical memories (e.g., <NUM>-<NUM> and <NUM>-<NUM>) but that target the same physical memory address to the same spare memory portion <NUM>-<NUM>.

After the testing phase, the first enablement register <NUM>-<NUM> stores a first indication of whether a first faulty memory portion <NUM>-<NUM> has been replaced by a corresponding first spare memory portion <NUM>-<NUM>, with the first faulty memory portion <NUM>-<NUM> corresponding to a first faulty memory address. The second enablement register <NUM>-<NUM> stores a second indication of whether a second faulty memory portion <NUM>-<NUM> has been replaced by a corresponding second spare memory portion <NUM>-<NUM>, with the second faulty memory portion <NUM>-<NUM> corresponding to a second faulty memory address. The circuitry of the arbitration logic <NUM> arbitrates access to the first spare memory portion <NUM>-<NUM> as well as the second spare memory portion <NUM>-<NUM> responsive to the first indication and the second indication. For example, the arbitration logic <NUM> can utilize a first memory portion redundancy-enable signal and a second memory portion redundancy-enable signal as generated by the repair logic <NUM> to prevent two or more spare memory portions from being simultaneously active responsive to the first faulty memory address matching the second faulty memory address.

<FIG> illustrates example circuitry <NUM> for an example first approach to performing logical memory repair in which a spare memory portion is implemented with a spare memory row. Thus, each of the spare memory portions <NUM>-<NUM> and <NUM>-<NUM> can be realized with a spare memory row <NUM>-<NUM> or <NUM>-<NUM>. In such cases, a first faulty memory address and a second faulty memory address can include at least one faulty row address (FRA) of a memory row that is faulty of a physical memory.

For clarity, the physical memory of <FIG> is a split memory having a left half of physical memory <NUM>-<NUM> and a right half of physical memory <NUM>-<NUM>. Further, a first logical memory (not shown in <FIG>) is overlaid on the left half of physical memory <NUM>-<NUM>, and a second logical memory (not shown) is overlaid on the right half of physical memory <NUM>-<NUM>. The spare columns <NUM>-<NUM> and <NUM>-<NUM> are not shared between the left and right halves of the physical memory <NUM>-<NUM> and <NUM>-<NUM> in this split memory example. Accordingly, the arbitration logic <NUM> may not be applied to column redundancy BISR parameters or indications of a faulty column in such architectures.

The spare rows <NUM>-<NUM> and <NUM>-<NUM>, however, are shared between the left and right halves of the physical memory <NUM>-<NUM> and <NUM>-<NUM>. Accordingly, the arbitration logic <NUM> may be applied to prevent conflicts with faulty memory row addresses. An environment with a physical memory that is split into halves and has a logical memory respectively applied to each half is used to describe certain principles with reference to <FIG> here and <FIG> below. The principles presented are applicable, however, to other quantities and combinations of physical memory and logical memory.

The example circuitry <NUM> can also include spare columns <NUM>-<NUM> and <NUM>-<NUM>, an address decoder <NUM>, and I/O circuitry <NUM>. Illustrated signals include an address (A[m:<NUM>]) targeted for a memory access of a logical memory, a first faulty row address (FRA1[m:<NUM>]), a first redundant row enable signal (RREN1), a second faulty row address (FRA2[m:<NUM>]), and a second redundant row enable signal (RREN2). Other illustrated signals include a first data portion (D[<NUM>:n/<NUM>-<NUM>]), a first faulty column indicator (FCI1[m:<NUM>]), a first redundant column enable signal (CRE1) or first column redundancy-enable signal, a second redundant column enable signal (CRE2) or second column redundancy-enable signal, a second faulty column indicator (FCI2[m:<NUM>]), and a second data portion (D[n/<NUM>:n-<NUM>]). The address decoder <NUM> can receive the address (A) and, from the repair logic <NUM>, a first row redundancy-enable signal (RRE1) and a second row redundancy-enable signal (RRE2).

If the circuitry <NUM> of <FIG> were to omit the arbitration logic <NUM>, the second redundant row enable signal (RREN2) would be applied directly to the second input of the "right" (as depicted) AND gate <NUM> via a repair port of the repair logic <NUM>. In some defect scenarios, an MBIST controller can load a same faulty row address into two BISR registers such that the first faulty row address (FRA1[m:<NUM>]) and the second faulty row address (FRA2[m:<NUM>]) match. When the targeted address (A) is the same as the matching faulty row address, the repair logic <NUM>-absent the arbitration logic <NUM>-would drive both the first and second row redundancy-enable signals (RRE1 and RRE2) active at the input of the address decoder <NUM>. This would result in an error condition.

To counteract such scenarios, however, the circuitry <NUM> can include the arbitration logic <NUM>. The example arbitration logic <NUM> of <FIG> includes a comparator <NUM> and an AND gate <NUM>, which has a "regular" (non-inverting) input and an inverting input. In example operations, the comparator <NUM> receives the first and second faulty row addresses (FRA1 and FRA2) at first and second inputs thereof. Responsive to these two faulty row addresses being equal, the comparator <NUM> outputs a high signal. The inverting input of the AND gate <NUM> inverts this to a low signal. Responsive to processing at least one low signal, the AND gate <NUM> outputs a low signal, regardless of the value of the second redundant row enable signal (RREN2) at the non-inverting input. This low signal is coupled to an input of the AND gate <NUM> via a repair port of the repair logic <NUM> as an arbitration signal <NUM>. The AND gate <NUM> therefore outputs a low value for the second row redundancy-enable signal (RRE2) to deactivate this input to the address decoder <NUM>.

Meanwhile, one or more repair ports of the repair logic <NUM> receive one or more BISR parameters "directly" (e.g., without being converted or modified by the arbitration logic <NUM>) from the BISR registers <NUM>-<NUM> and <NUM>-<NUM> (not shown in <FIG>). The "left" (as depicted) AND gate <NUM> of the repair logic <NUM> generates a high signal to activate the first row redundancy-enable signal (RRE1) at the address decoder <NUM>. Thus, in scenarios in which both the first faulty row address (FRA1[m:<NUM>]) and the second faulty row address (FRA2[m:<NUM>]) match each other, as well as match the targeted address (A), the arbitration logic <NUM> causes the repair logic <NUM> to activate a single row redundancy-enable signal (RRE1 in this case) to avoid an error condition. The avoided error condition is the one that would result if multiple row redundancy-enable signals (RRE1 and RRE2) are activated during a single memory access cycle at two inputs to the address decoder <NUM>.

<FIG> illustrates example circuitry <NUM> for an example second approach to performing logical memory repair in which a spare memory portion is implemented with a spare memory row. As shown, the arbitration logic <NUM> includes or instantiates multiple repair control ports <NUM> and <NUM>. The arbitration logic <NUM> also includes decoder logic <NUM>, which may be realized as row-decoder logic <NUM>. In example implementations, the decoder logic <NUM> can provide enhanced row replacement support by correcting for a greater variety of potential multi-defect scenarios.

In some cases, with the example circuitry <NUM> that is explicitly depicted in <FIG>, one set of spare rows is allocated to each logical memory. Consequently, some multi-defect scenarios can become unrepairable. The approach using repair-control ports, however, can correct for more diverse defect scenarios by allowing for independent BIRA at the logical memory level. To do so, each respective logical memory can be mapped to a respective repair control port. For example, the arbitration logic <NUM> can map a default repair control port <NUM> to a first logical memory of two or more logical memories. The arbitration logic <NUM> can map a pseudo repair control port <NUM> to a second logical memory of the two or more logical memories.

In <FIG>, the first BISR registers <NUM>-<NUM> can provide at least one faulty row address (FRA) and at least one redundant row enable (RREN) signal. As shown for the default repair control port <NUM>, the first BISR registers <NUM>-<NUM> can provide first and second faulty row addresses (FRA1 and FRA2) and first and second redundant row enable (RREN1 and RREN2) signals. In some scenarios, the "default" repair control port <NUM> can correspond to the logical memory that is tested first. The second BISR registers <NUM>-<NUM> can provide at least one pseudo faulty row address (P_FRA) and at least one pseudo redundant row enable (P_RREN) signal. As shown for the pseudo repair control port <NUM>, the second BISR registers <NUM>-<NUM> can provide first and second pseudo faulty row addresses (P_FRA1 and P_FRA2) and first and second pseudo redundant row enable (P_RREN1 and P_RREN2) signals. Although one pseudo repair control port is shown, there may be multiple pseudo repair control ports corresponding to multiple logical memories in addition to a first-tested logical memory.

The decoder logic <NUM> decodes the BISR parameters as input from the first and second BISR registers <NUM>-<NUM> and <NUM>-<NUM> to provide arbitrated output values for the faulty row addresses and faulty redundant row enable signals as one or more arbitration signals <NUM>. The one or more arbitration signals <NUM> function as a single repair control port at the physical-memory level. Thus, the arbitration logic <NUM> can convert the multiple repair control ports <NUM> and <NUM> into a single repair control port to access one or more spare memory portions (e.g., spare rows <NUM> or spare columns <NUM>) of at least one physical memory. The arbitrated signals <NUM> are output by the decoder logic <NUM> of the arbitration logic <NUM> and provided to one or more repair ports (not separately indicated) of the repair logic <NUM>. These values can include a first arbitrated faulty row addresses (FRA1_arb), a first arbitrated redundant row enable (RREN1_arb) signal, a second arbitrated faulty row addresses (FRA2_arb), and a second arbitrated redundant row enable (RREN2_arb) signal.

The pseudo repair control port allows for substantially independent BIRA of the second logical memory relative to the first logical memory. The decoder logic <NUM> can produce physical-memory-level row-repair control signals for the repair logic <NUM> from the logical-memory-level BISR parameters established by the MBIST controller that is external to the memory cluster. In example operations, the decoder logic <NUM> can determine these arbitrated values at the physical-memory level so that the first row redundancy-enable signal (RRE1) does not equal the second row redundancy-enable signal (RRE2) to avoid activating both of the replacement rows during a single access cycle.

The decoder logic <NUM> can be constructed using logic gates to implement a logical relationship between two or more signals. The logical relationship may depend, for instance, on the quantity of logical memories overlaid on the at least one physical memory and/or on the quantity of redundant replacement rows that are to be available. Table <NUM> below presents an example logical relationship between the multiple signals. The logical relationship depicts an example conversion of signals (e.g., values) at a logical-memory level to signals at a physical-memory level.

Using the logical relationship presented in the matrix of Table <NUM>, several multi-fault (e.g., multi-defect) scenarios across one or more logical memories can be repaired. For example, one fault in each of two logical memories that consume one spare row in each logical memory can be repaired. Second, one or two faults in a first of two logical memories can be repaired if the faults can be fixed with one or two rows, respectively. Third, one or two faults in a second of two logical memories can be repaired if the faults can be fixed with one or two rows, respectively. In these scenarios, {RREN1=<NUM>, RREN2=<NUM>} is considered an invalid condition. A three-fault scenario (e.g., a first logical memory of two logical memories has one fault and a second of the two logical memories has two faults, or vice versa) can be covered with additional overhead circuitry in the decoder logic <NUM>. Further, additional BISR registers and/or repair control ports can be incorporated into decoder logic <NUM> that realizes an expanded logical relationship among the signals.

<FIG> and <FIG> are described above in terms of spare rows that can replace faulty rows. For example, the decoder logic <NUM> is described as row-decoding logic. The principles, however, are applicable to circuitry in which spare columns (or other types of spare memory portions) can replace faulty columns (or other types of faulty memory portions). Example circuitry that can repair faults in memory columns is described next with reference to <FIG>.

<FIG> illustrates example circuitry <NUM> for performing logical memory repair in which a spare memory portion is implemented with a spare memory column. As illustrated, multiple logical memories (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) are shared across multiple physical memories (<NUM>-<NUM>, <NUM>-<NUM>). In this circuitry, a spare memory portion <NUM> includes or is realized as a spare memory column for replacing a faulty memory column. With continuing reference to the example split memory of <FIG> and <FIG>, the spare columns <NUM>-<NUM> and <NUM>-<NUM> respectively correspond to the left and right halves of physical memory <NUM>-<NUM> and <NUM>-<NUM>. These spare columns are not shared between the halves. If four logical memories are overlaid on the split physical memory, however, each set of spare columns <NUM>-<NUM> and <NUM>-<NUM> is shared between two of the four logical memories.

A decision on whether a memory column that is targeted by a memory access request is a faulty memory column can be based on a Faulty Column Indicator (FCI) and a Column Row Enablement (CRE) signal from at least one BISR register <NUM>. Thus, a first faulty memory address and a second faulty memory address can correspond to at least one memory column indicator identifying a memory column that is faulty (e.g., identifying a column of bits having at least one faulty bit). The one or more faulty memory column indicators can be stored in a BISR register <NUM> (e.g., a BISR register <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and/or <NUM>-<NUM>). Each respective BISR register <NUM> can store a respective indication of whether the associated faulty memory column indicator register stores a valid replacement indicator identifying a replacement column of bits.

In example implementations, the arbitration logic <NUM> and the repair logic <NUM> are each divided into two parts, such as arbitration logic <NUM>-<NUM> and <NUM>-<NUM>. Each respective set of BISR registers <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> corresponds to a respective first, second, third, and fourth logical memory (not shown in <FIG>) that can provide respective enablement indications and faulty column indicators CRE10/FCI10, CRE11/FCI11, CRE20/FCI20, and CRE21/FCI21. These enablement indications and faulty column indicators are provided to the arbitration logic <NUM>-<NUM> or <NUM>-<NUM> as shown. The instances of the arbitration logic <NUM>-<NUM> and <NUM>-<NUM> provide respective arbitration signals <NUM>-<NUM> and <NUM>-<NUM> to one or more repair ports of the repair logic <NUM> for respective ones of the first and second halves of physical memory <NUM>-<NUM> and <NUM>-<NUM> as indicated by the CRE1/FCI1 and CRE2/FCI2, respectively.

In these manners, faulty memory columns can be replaced by spare memory columns using at least one instance of arbitration logic <NUM> in a split memory environment while accounting for conflicts arising from performing memory tests at the logical memory level. The example implementations described herein with reference to <FIG> relate to split memory environments. The described principles, however, as well as the logical memory repair techniques and apparatuses that are presented by this document, are applicable to memory environments generally.

<FIG> illustrates example methods <NUM> for performing logical memory repair with a shared physical memory. In these examples, a method can repair at least one physical memory that is behind a shared bus interface as part of a memory cluster and that is tested based on at least one logical memory, which is overlaid on the at least one physical memory.

At <NUM>, a memory built-in self-test controller performs at least one test on multiple logical memories. In one example, an MBIST controller <NUM> can perform a test on a first logical memory <NUM>-<NUM> and a second logical memory <NUM>-<NUM>, which are distributed across a single physical memory <NUM>. In another example, the MBIST controller <NUM> can perform a test on multiple logical memories <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> that are distributed across multiple physical memories <NUM>-<NUM> and <NUM>-<NUM>.

At <NUM>, the memory built-in self-test controller identifies two or more faulty memory portions of at least one physical memory based on the performed test. For example, the MBIST controller <NUM> can identify a first memory portion <NUM>-<NUM> and a second memory portion <NUM>-<NUM> of at least one physical memory <NUM> as being faulty. Such faulty memory portions can correspond to at least one memory row, at least one memory column, at least one memory row and at least one memory column, and so forth. The performed test can correspond to one or more standard MBIST testing algorithms.

At <NUM>, the memory built-in self-test controller loads a first address register with a first faulty memory address and a second address register with a second faulty memory address based on the identified two or more faulty memory portions. For example, the MBIST controller <NUM> can load a first address register <NUM>-<NUM> with a first faulty memory address and a second address register <NUM>-<NUM> with a second faulty memory address. Each faulty memory address may correspond, for instance, to a memory portion <NUM> that is identified as being faulty responsive to a test. In some cases, the first faulty memory address, which is stored in the first address register <NUM>-<NUM>, may match (e.g., be equal to) the second faulty memory address, which is stored in the second address register <NUM>-<NUM>. Without employing arbitration logic <NUM>, these matching faulty memory addresses can cause two redundancy-enable signals to be active at one time, which can lead to errors with the address decoding. The arbitration logic <NUM>, however, can resolve such conflicting addresses.

At <NUM>, the at least one physical memory arbitrates access to at least one spare memory portion, which corresponds to the two or more faulty memory portions, responsive to the first faulty memory address conflicting with the second faulty memory address. For example, arbitration logic <NUM> of the at least one physical memory <NUM> can arbitrate access to a spare memory portion <NUM> used for repairing a corresponding failed memory portion. For instance, the arbitration logic <NUM> may cause repair logic <NUM> to assert a first memory portion redundancy-enable signal and cause the repair logic <NUM> to de-assert a second memory portion redundancy-enable signal. Alternatively, the arbitration logic <NUM> may cause the repair logic <NUM> to de-assert the first memory portion redundancy-enable signal and cause the repair logic <NUM> to assert the second memory portion redundancy-enable signal.

Generally, any of the components, modules, methods/processes, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. Some operations of the example methods or processes may be described in the general context of executable instructions stored on computer-readable storage memory that is local and/or remote to a computer processing system, and implementations can include software applications, programs, functions, and the like. Alternatively or in addition, any of the functionality described herein can be performed, at least in part, by one or more hardware logic components, including, but without limitation, Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SoCs), Complex Programmable Logic Devices (CPLDs), and the like.

Claim 1:
An apparatus comprising:
a memory built-in self-test controller (<NUM>) including circuitry configured to perform at least one test on multiple logical memories (<NUM>); and
a memory cluster (<NUM>) including:
a shared bus interface (<NUM>) coupled to the memory built-in self-test controller and configured to provide access to the multiple logical memories; and
multiple physical memories (<NUM>) coupled to the shared bus interface, the multiple physical memories including at least one physical memory configured to have two or more logical memories of the multiple logical memories overlaid thereon, the at least one physical memory including a first built-in self repair, BISR, register (<NUM><NUM>-<NUM>) and a second BISR register (<NUM>-<NUM>), wherein the first BISR register (<NUM>-<NUM>) comprises a first address register (<NUM>-<NUM>) and a first enablement register (<NUM>-<NUM>), and the second BISR register (<NUM>-<NUM>) comprises a second address register (<NUM>-<NUM>) and a second enablement register (<NUM>-<NUM>), wherein:
the first address (<NUM>) register (<NUM>-<NUM>) is configured to store a first faulty memory address as determined by the memory built-in self-test controller;
the second address register (<NUM>-<NUM>) is configured to store a second faulty memory address as determined by the memory built-in self-test controller;
the first enablement register (<NUM>-<NUM>) is configured to store a first indication of whether a first faulty memory portion has been replaced by a first spare memory portion (<NUM>-<NUM>), the first faulty memory portion corresponding to the first faulty memory address; and
the second enablement register (<NUM>-<NUM>) configured to store a second indication of whether a second faulty memory portion has been replaced by a second spare memory portion (<NUM>-<NUM>), the second faulty memory portion corresponding to the second faulty memory address; and
arbitration logic (<NUM>) coupled to the first BISR register (<NUM>-<NUM>) and the second BISR register (<NUM>-<NUM>), the arbitration logic (<NUM>) including circuitry configured to arbitrate access to the first spare memory portion (<NUM>-<NUM>) or the second spare memory portion (<NUM>-<NUM>) responsive to the first indication and the second indication and further responsive to the first faulty memory address conflicting with the second faulty memory address.