Patent Description:
A capacitive sensor device, such as a Coriolis-based gyroscope transducer, an accelerometer, a pressure sensor, and the like, outputs a capacitive signal indicative of measurements or other properties of the capacitive sensor device. Subsequent signal conditioning for such devices can be more efficient by first converting the capacitance signal to an analog voltage signal, processing the analog voltage signal, and converting the analog voltage signal to a digital representation of the signal. The market demands high performance sensors with good offset stability over temperature (TCO), low noise, and low power consumption.

European patent application, publication number <CIT> discloses a transducer in which a guard electrode is formed in a frontside of a semiconductor substrate and a fixed electrode is formed on the guard electrode by the insulating layer. A cavity is formed on the fixed electrode by a diaphragm and a movable electrode is formed between the layers of the diaphragm. An operational amplifier which drives the guard electrode so as to equalise an electric potential of the guard electrode with that of the fixed electrode is provided. Change in the capacitance between the fixed electrode and a movable electrode is converted into a voltage directly concerned with a displacement of the diaphragm. As illustrated at figure <NUM>, the voltage source or the ground may be always connected to the moving electrode and the reference electrode which face the frontside surface side of the pressure sensor although they are switched by the switch. Thus, it is stated, even if the electric lines of force from the external noise source drop to the pressure sensor, since the charges flow to the ground through the voltage source or directly, they do not stray into the fixed electrode and the apparatus has a shielding effect against the electrostatic noises. Since the electric lines of force from the backside surface of the substrate drop to the guard electrode which is driven at the low impedance by the operational amplifier, they do not reach the fixed electrode and the reference fixed electrode, and the noises from the backside surface of the substrate can be blocked.

In a first aspect, there is provided a sensor package comprising a first die having a capacitive sensor, the capacitive sensor including an active sensing portion and a shield surrounding the active sensing portion, and a second die comprising a voltage regulator configured to produce a shield voltage and a compensation circuit configured to produce a compensation signal, the voltage regulator and the compensation circuit each being directly electrically coupled to the shield, wherein the voltage regulator is configured to regulate the shield to the shield voltage, and the compensation signal produced by the compensation circuit is configured to reduce an interference signal on the shield voltage.

The accompanying figures in which like reference numerals refer to identical or functionally similar elements throughout the separate views, the figures are not necessarily drawn to scale, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.

In overview, the present disclosure concerns a sensor package with enhanced robustness against interference from data communication and a method of operation. More particularly, the sensor package includes a compensation circuit integrated into an application specific integrated circuit (ASIC) die of the sensor package. The compensation circuit is configured to inject a compensating charge into a shield surrounding the active sensing portion that has a similar magnitude, but an opposite polarity, as an interference signal injected into the shield via package parasitics. Injection of a compensating charge similar in magnitude and opposite in polarity may achieve significant charge reduction and shield voltage stabilization. Thus, a disturbance on a shield voltage of the shield, that might otherwise corrupt an output signal from the sensor package, may be reduced for improved performance of the sensor package. The description provided below relates to a capacitive transducer in the form of a microelectromechanical systems (MEMS) capacitive accelerometer. It should be appreciated, however, that embodiments described below may be generalized to other capacitive transducers, circuits, and components, such as gyroscopes, pressure sensors, microphones, and so forth.

The instant disclosure is provided to further explain in an enabling fashion at least one embodiment in accordance with the present invention. The disclosure is further offered to enhance an understanding and appreciation for the inventive principles and advantages thereof, rather than to limit in any manner the invention. The invention is defined solely by the appended claims.

It should be understood that the use of relational terms, if any, such as first and second, top and bottom, and the like are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, some of the figures may be illustrated using various shading and/or hatching to distinguish the different elements produced within the various structural layers. These different elements within the structural layers may be produced utilizing current and upcoming microfabrication techniques of depositing, may be is utilized in the illustrations, the different elements within the structural layers may be formed out of the same material.

Referring to <FIG> shows a block diagram of a sensor package <NUM>. Sensor package <NUM> generally includes a first die, referred to herein as a sensor die <NUM>, and a second die, referred to herein as an ASIC die <NUM>. In the block diagram of <FIG>, sensor die <NUM> and ASIC die <NUM> are delineated by boxes for clarity. In this example, sensor die <NUM> is a capacitive transducer, and more specifically, a capacitive accelerometer. As such, sensor die <NUM> may alternatively be referred to herein as accelerometer die <NUM>. Sensor die <NUM> includes an active sensing portion <NUM>, configured as a differential sensor, and a shield <NUM> at least partially surrounding active sensing portion <NUM>. ASIC die <NUM> includes excitation circuitry <NUM>, processing circuitry <NUM>, and a voltage regulator <NUM>, each of which are delineated by dashed line boxes.

Active sensing portion <NUM> of sensor die <NUM> includes first and second movable masses <NUM>, <NUM>. First and second movable masses <NUM>, <NUM> may be configured to undergo motion in a direction substantially parallel to a Y-axis in a three-dimensional coordinate system in response to an acceleration force imposed on first and second movable masses <NUM>, <NUM>. The Y-axis may be, for example, in a vertical direction. The motion of first and second movable masses <NUM>, <NUM> in response to the acceleration force can be detected as a change in capacitance between certain electrodes. By way of example, sensor die <NUM> includes fixed electrodes <NUM>, <NUM> positioned proximate first movable mass <NUM> and fixed electrodes <NUM>, <NUM> positioned proximate second movable mass <NUM>. First and second movable masses <NUM>, <NUM> are configured to move relative to fixed electrodes <NUM>, <NUM>, <NUM>, <NUM> in response to an external stimulus (e.g., acceleration).

In a structure of this type, charge is injected into sensor die <NUM> through excitation signals <NUM>, <NUM> provided by excitation circuitry <NUM> to enable capacitance measurement. Fixed electrodes <NUM>, <NUM> receive excitation signal <NUM> in the form of a voltage step, labeled Y1, relative to a rest voltage. Fixed electrodes <NUM>, <NUM> receive excitation signal <NUM> in the form of a voltage step, labeled Y2, relative to the rest voltage. In such systems, the rest voltage is typically half of the voltage between the minimum and maximum voltages. Thus, in an example, excitation signal <NUM> may rise from a rest level (e.g., the rest voltage) to a high level (e.g., from <NUM>. 8V to <NUM>. 6V) while excitation signal <NUM> drops from the rest level to a low level (e.g., from <NUM>. These voltage steps create charge transfers in the sensor capacitance. Additionally, the voltage at first and second movable masses <NUM>, <NUM> is regulated to the rest voltage (e.g., <NUM>.

Parallel-plate capacitors <NUM>, <NUM>, <NUM>, <NUM> are effectively formed between first and second movable masses <NUM>, <NUM> and respective fixed electrodes <NUM>, <NUM>, <NUM>, <NUM>. When first and second movable masses <NUM>, <NUM> move in response to an acceleration force, the width of the gaps between fixed electrodes <NUM>, <NUM> and first movable mass <NUM> and the width of the gaps between fixed electrodes <NUM>, <NUM> and second movable mass <NUM> change which in turn causes the capacitances (labeled CM1Y1, CM1Y2, CM2Y1, CM2Y2) of capacitors <NUM>, <NUM>, <NUM>, <NUM> to change. The charges on capacitors <NUM>, <NUM>, <NUM>, <NUM> can be collected in downstream processing circuitry <NUM>. First and second movable masses <NUM>, <NUM> move commensurate with the magnitude of the acceleration force, such that the larger the magnitude of the acceleration force, the more first and second movable masses <NUM>, <NUM> will move toward an extreme position and the larger the differential charge output from sensor die <NUM> will be.

Sensor die <NUM> and ASIC die <NUM> are electrically coupled to convey excitation signals <NUM>, <NUM> from excitation circuitry <NUM> to sensor die <NUM> and to convey the excitation results (e.g., a first capacitance <NUM>), labeled CM1 (as a first differential charge component), and a second capacitance <NUM>), labeled CM2 (as a second differential charge component), from sensor die <NUM> to processing circuitry <NUM>. Processing circuitry <NUM> generally includes a signal chain used to process first and second capacitances <NUM>, <NUM> to yield a signal representative of the acceleration force imposed upon sensor die <NUM>. A first stage of the signal chain includes a capacitance-to-voltage converter stage <NUM>, abbreviated C2V herein, having first and second inputs <NUM>, <NUM> which receive first and second capacitances <NUM>, <NUM> from sensor die <NUM> and converts them to a first stage analog output voltage. Subsequent processing stages in the signal chain for processing circuitry <NUM> are generally represented by a box <NUM> and may include a gain stage, a chopper circuit, and analog-to-digital processor, and so forth to produce a digital output signal <NUM>, labeled OUT. The processing stages represented by box <NUM> can vary widely and are not described in detail herein for brevity.

The current market demands high performance sensors with good offset stability over temperature (TCO), low noise, and low power consumption. Differential sensor architectures may be preferred to meet the low TCO requirement. In a differential sensor architecture such as in sensor die <NUM>, a shield structure surrounding the active sensing portion (e.g., shield <NUM> surrounding active sensing portion <NUM>) is typically regulated to a constant shield voltage <NUM>, labeled VSH. In the illustrated example, shield voltage <NUM> is provided by voltage regulator <NUM>. Voltage regulator <NUM> may also provide a reference voltage <NUM>, labeled VREF, and/or a rest voltage <NUM>, labeled VMID.

In differential sensor architectures, the fixed electrodes (e.g., fixed electrodes <NUM>, <NUM>, <NUM>, <NUM>) are commonly driven by excitation signals <NUM>, <NUM> while first and second movable masses <NUM>, <NUM> are connected to respective first and second inputs <NUM>, <NUM> of C2V <NUM>, regulated to a constant reference voltage <NUM>. Shield voltage <NUM> may be equal to reference voltage <NUM> in order to avoid applying unwanted electrostatic forces to first and second movable masses <NUM>, <NUM>, which would otherwise create offset and sensitivity errors.

The low power consumption requirement imposed on sensor package <NUM> can cause shield voltage <NUM> to be susceptible to interference <NUM>, represented by a lightning bolt in <FIG>, resulting from parasitic capacitive coupling at the package level thereby inducing unwanted charge injection. That is, due to the low power consumption requirement, voltage regulator <NUM> driving shield voltage <NUM> has neither a very strong current capability nor a wide frequency bandwidth. As such, shield voltage <NUM> is susceptible to interferences from nearby electric fields.

One common source of interference on digital output sensors is data communication. Data communication may be implemented using, for example, I2C or SPI communication protocols. I2C is a synchronous, multi-master, multi-slave, packet-switched, single-ended, serial communication bus typically used for attaching lower-speed peripheral integrated circuits to processors and microcontrollers in short-distance, intra-board communication and SPI is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. The clock and data lines of I2C or SPI communication protocols carry high-amplitude, sharp-edge square signals which can couple to shield <NUM>.

Sensor die <NUM> typically senses capacitances (e.g., CM1Y1, CM1Y2, CM2Y1, CM2Y2) according to a periodic sequence that is synchronous to an internal clock of sensor package <NUM>. Conversely, an end-use application into which sensor package <NUM> is incorporated may poll sensor package <NUM> for data asynchronously, relative to the internal clock of sensor package <NUM>, as the communication line clock (e.g., the clock line of the I2C or SPI communication protocol) is independent from the internal clock of sensor package <NUM>. That is, the end-use application may poll sensor package <NUM> periodically, but with a period which is different from the internal clock of sensor package <NUM>. Accordingly, there may be instances where the reading taken at the polling period falls at critical times of the sensor data acquisition sequence, which can cause measurement corruption. Communication from the end-use application (e.g., a microcontroller unit connected to sensor package) and other components of the application may also produce asynchronous interferences.

Once shield voltage <NUM> is disturbed by digital communication interferers, it can easily corrupt the signal change. For example, a differential signal <NUM>, QDIFF, may be created by mismatch between two mass-to-shield capacitances <NUM>, <NUM>. Further, a large common-mode signal <NUM>, QCM, may be created which can overwhelm the common-mode regulation of C2V <NUM>. When mass-to-shield capacitances <NUM>, <NUM> are not equal, a disturbance in shield voltage <NUM> produces different charge injections into first and second inputs <NUM>, <NUM> of C2V <NUM>. In an example, the average of two injected charges is common-mode signal <NUM>, QCM. The difference between the two injected charges is <NUM>*QDIFF. The charge injected in first input <NUM> of C2V <NUM> is thus QCM-QDIFF and the charge injected in second input <NUM> of C2V <NUM> is thus QCM+QDIFF C2V <NUM> reacts differently to differential signal <NUM> and common-mode signal <NUM> because those charges may be handled by distinct amplifiers of C2V <NUM>. Nevertheless, both differential signal <NUM> and common-mode signal <NUM> can cause problems.

In addition to differential signal <NUM> and common-mode signal <NUM>, other voltage references may be corrupted (represented in <FIG> by zigzag patterns <NUM>) as the low-power requirement dictates sharing of a single voltage regulator <NUM> to generate multiple voltages (e.g., shield voltage <NUM>, reference voltage <NUM>, rest voltage <NUM>), including those needed by amplifiers of the signal chain of processing circuitry <NUM>. Depending upon the amplitude of the disturbance to shield voltage <NUM>, corruption of digital output signal <NUM> can range from a simple increase in noise density to a catastrophic failure (e.g., digital output signal <NUM> collapsing to zero regardless of the actual sensed signal value).

<FIG> shows a simplified side sectional view of sensor die <NUM> of sensor package <NUM> (<FIG>). In the side sectional view of <FIG>, shield <NUM> is in the form of a polysilicon ground plane separating a floating bulk silicon <NUM> of sensor die <NUM> from active sensing portion <NUM> of sensor die <NUM>.

In this architecture, bulk silicon <NUM> is not electrically biased by an ohmic contact. Rather, bulk silicon <NUM> touches nonconductive materials (e.g., a die attach film <NUM> at the bottom and an oxide dielectric material layer <NUM> interposed between bulk silicon <NUM> and shield <NUM>. A direct current (DC) potential of bulk silicon <NUM> is undefined. However bulk silicon <NUM> has parasitic capacitances with neighboring conductive layers. The neighboring conductive layers can include a package substrate <NUM> having package leads <NUM>, in which the parasitic capacitance is through die attach film <NUM>. The neighboring conductive layers can also include polysilicon shield <NUM>, in which the parasitic capacitance is through oxide dielectric material layer <NUM>. If the neighboring conductive layers (e.g., package leads <NUM> and/or polysilicon shield <NUM>) have rapid voltage changes, these changes will couple to the floating bulk silicon <NUM> through the parasitic capacitors. Thus, floating bulk silicon <NUM> may have a significant alternating current (AC) voltage. Due at least in part to a large parasitic capacitance (e.g., <NUM> pFarad) between bulk silicon <NUM> and polysilicon shield <NUM>, the AC voltage of bulk silicon <NUM> can propagate readily to shield <NUM> with almost no attenuation.

In other architectures, bulk silicon <NUM> may be directly biased to shield voltage <NUM> (<FIG>) by an electrical (ohmic) contact. In such an architecture, a voltage change on package leads <NUM> couples directly through the parasitic capacitance of die attach film <NUM> to the potential of shield voltage <NUM> of bulk silicon <NUM>.

Referring now to <FIG> shows a side view of sensor package <NUM> and <FIG> shows a plan view of sensor package <NUM>. Sensor package <NUM> includes sensor die <NUM> and ASIC die <NUM> stacked on and coupled to sensor die <NUM>. Inter-chip bond wires <NUM> suitably interconnect first bond pads <NUM> of sensor die <NUM> with second bond pads <NUM> of ASIC die <NUM>. Among the various inter-chip bond wires <NUM>, at least one of inter-chip bond wires <NUM> is electrically connected to shield <NUM>. For simplicity in <FIG>, shield <NUM> is represented by a dashed line box and an electrically conductive pathway or via <NUM>, also represented by dashed lines, extends from first bond pad <NUM> of sensor die <NUM> to shield <NUM> to represent the electrical interconnection of first bond pad <NUM> to shield <NUM>. Additionally, the one or more inter-chip bond wires <NUM> that interconnect first and second bond pads <NUM>, <NUM> and form the electrically conductive pathway to shield <NUM> are referred to hereinafter as shield lines <NUM>. Shield lines <NUM> are illustrated with thicker lines in <FIG> to distinguish them from the remaining inter-chip bond wires <NUM>.

ASIC die <NUM> may further include off-chip bond pads <NUM>. Off-chip bond wires <NUM> may be electrically connected between off-chip bond pads <NUM> and package leads <NUM> of package substrate <NUM>. Among the various off-chip bond wires <NUM> at least one of off-chip bond wires <NUM> may provide a communication signal to ASIC die <NUM>. As mentioned previously, the communication signal or signals may be clock and data lines of I2C or SPI communication protocols. Again, these digital communication signal(s) carry high-amplitude, sharp-edge square signals which can couple to shield <NUM>. For simplicity in <FIG>, the one or more off-chip bond wires <NUM> that interconnect off-chip bond pads <NUM> with package leads <NUM> and are utilized to carry the digital communication signals (e.g., clock and data signals) are referred to hereinafter as communication lines <NUM>. Communication lines <NUM> are illustrated with thicker lines in <FIG> to distinguish them from the remaining off-chip bond wires <NUM>.

With regard to <FIG>, communication signals on communication lines <NUM> can couple to shield <NUM> via multiple paths, such as capacitive coupling from bond pads (e.g., first and/or second bond pads <NUM>, <NUM>), bond wires (e.g., shield lines <NUM> and/or communication lines <NUM>), and/or package leads (e.g., package leads <NUM>). Due to the relatively large volume of a MEMS sensor die stack that is biased or strongly coupled to shield voltage <NUM> (<FIG>), parasitic capacitive coupling between shield <NUM> and interferers is highly likely. This parasitic capacitance may inject disturbance onto shield voltage <NUM> which, in turn, can corrupt sensor output signal <NUM> (<FIG>). In order to alleviate the problem of injecting a disturbance to shield voltage <NUM>, digital communication between applications and sensor package <NUM> may be performed synchronously and no other devices may be on the communication bus. However, this requirement severely limits the served market and the potential applications into which sensor package <NUM>. Alternatively, it may be impractical to remove all the propagation paths leading from a disturbance on shield voltage <NUM> to corruption of sensor output signal <NUM> due to the large number and variety of propagation mechanisms. Accordingly, embodiments discussed below entail injection an opposite charge into the shield through a compensation circuit integrated into ASIC die <NUM> to achieve charge cancelation and stabilization of shield voltage <NUM>.

<FIG> shows a simplified plan view of a sensor package <NUM> in accordance with an embodiment. Sensor package <NUM> may be similar to sensor package <NUM>. Therefore, features common to both of sensor packages <NUM>, <NUM> will share the same reference numerals. For simplicity, reference should be made concurrently to <FIG> and <FIG>. Capacitive sensor packages <NUM>, <NUM> are provided for illustrative purposes herein. It should be understood that one or more movable masses of a capacitive transducer can encompass a great variety of shapes and configurations capable of single or multiple axis sensing. Further, although a capacitive accelerometer is discussed herein, embodiments described below may be generalized to other capacitive transducers, circuits, and components, such as gyroscopes, pressure sensors, microphones, and so forth. Still further, although embodiments are discussed in connection with a differential sensor architecture in which shield <NUM> is connected to shield voltage <NUM>, embodiments may alternatively be incorporated in a single-ended architecture when the shield of the singled-ended architecture is connected to a different voltage rail instead of to a system ground.

Sensor package <NUM> includes a first die (e.g., sensor die <NUM>) having a capacitive sensor that includes an active sensing portion (e.g., active sensing portion <NUM>, <FIG>) and a shield (e.g., shield <NUM>, <FIG>) surrounding the active sensing portion. Additionally, sensor package <NUM> includes a second die (e.g., ASIC die <NUM>) that includes a voltage regulator (e.g., voltage regulator <NUM>) configured to produce a shield voltage (e.g., shield voltage <NUM>). ASIC die <NUM> may be electrically connected to electronic components <NUM> (generally represented by a box) in an end-use application. Such an application may include, for example, a controller that provides one or more digital communication signals <NUM>, <NUM> to ASIC die <NUM> via communication lines <NUM> of off-chip bond wires <NUM>. In an example, communication signal <NUM> may be a serial data acquisition (SDA) communication signal <NUM> and communication signal <NUM> may be a serial clock (SCL) communication signal <NUM>. Of course, other off-chip bond wires <NUM> connected to package leads <NUM> of sensor package <NUM> may be electrically connected to electronic components <NUM> (not shown herein for simplicity).

In accordance with an embodiment, a compensation circuit <NUM> is integrated into ASIC <NUM>. Compensation circuit <NUM> is configured to produce a compensation signal <NUM> (e.g., a compensating charge) labeled QCOMP. Voltage regulator <NUM> and compensation circuit <NUM> are electrically coupled to shield <NUM> via one or more second bond pads <NUM>, one or more shield lines <NUM> of inter-chip bond wires <NUM>, one or more first bond pads <NUM>, and one or more conductive pathways through sensor die <NUM> (e.g., conductive via <NUM>, <FIG>). The illustrated configuration of <FIG> includes a single shield line <NUM> for simplicity. Alternative architectures may include two or more shield lines <NUM> electrically connected to shield <NUM> for redundancy.

In general, voltage regulator <NUM> is configured to regulate shield <NUM> to shield voltage <NUM> and compensation signal <NUM>, produced by compensation circuit <NUM>, is configured to reduce an interference signal <NUM>, labeled ISDA, and/or an interference signal <NUM>, labeled ISCL. Interference signals <NUM>, <NUM> represent unwanted signals coupling to shield <NUM> via parasitic capacitive coupling from bond pads (e.g., first and/or second bond pads <NUM>, <NUM>), bond wires (e.g., shield lines <NUM> and/or communication lines <NUM>), and/or package leads (e.g., package leads <NUM>) as discussed in detail above. In this example, interference signals <NUM>, <NUM> may be voltage spikes resulting from, for example, logic transitions on serial data acquisition (SDA) communication line <NUM> from SDA communication signal <NUM> and/or on serial clock (SCL) communication line <NUM> from SCL communication signal <NUM>. Thus, in this scenario, SDA and/or SCL communication signals <NUM>, <NUM> can impose interference signals <NUM>, <NUM> (e.g., disturbances) on shield voltage <NUM>.

For clarity, package lead <NUM>, off-chip bond pad <NUM>, and communication line <NUM> providing SDA communication signal <NUM> to ASIC die <NUM> are referred to hereinafter respectively as SDA package lead 100A, SDA off-chip bond pad 112A, and SDA communication line 116A. Similarly, package lead <NUM>, off-chip bond pad <NUM>, and communication line <NUM> providing SCL communication signal <NUM> to ASIC die <NUM> are referred to hereinafter respectively as SCL package lead 100B, SCL off-chip bond pad 112B, and SCL communication line 116B. Although SDA and SCL communication signals <NUM>, <NUM> are mentioned herein, any logic package lead in sensor package <NUM> with a large voltage swing can potentially affect shield voltage <NUM> and may thus benefit from compensation signal <NUM>.

In some embodiments, compensation circuit <NUM> includes a first logic inverter <NUM> and a first coupling capacitor <NUM>. First logic inverter <NUM> has a first input <NUM> and a first output <NUM>, with first input <NUM> being electrically connected to SDA bond pad 112A. First coupling capacitor <NUM> has a first terminal <NUM> electrically connected to first output <NUM> of first logic inverter <NUM> and a second terminal <NUM> electrically connected to second bond pad <NUM> that is connected to shield line <NUM>. Compensation circuit <NUM> further includes a second logic inverter <NUM> and a second coupling capacitor <NUM>. Second logic inverter <NUM> has a second input <NUM> and a second output <NUM>, with second input <NUM> being electrically connected to SCL bond pad 112B. Second coupling capacitor <NUM> has a third terminal <NUM> electrically connected to second output <NUM> of second logic inverter <NUM> and a fourth terminal <NUM> electrically connected to second bond pad <NUM> that is connected to shield line <NUM>.

In operation, first logic inverter <NUM> is configured to receive SDA communication signal <NUM> at first input <NUM> and invert SDA communication signal <NUM> to produce an inverted communication signal at first output <NUM>. First coupling capacitor <NUM> is configured to receive the inverted communication signal at first terminal <NUM>. The inverted communication signal drives first coupling capacitor <NUM> to produce compensation signal <NUM> having an opposite polarity and a similar or equivalent magnitude to SDA interference signal <NUM>. Through the electrical interconnection of compensation circuit <NUM> to shield <NUM> (<FIG>), compensation signal <NUM> may therefore reduce SDA interference signal <NUM> on shield <NUM>. Likewise, second logic inverter <NUM> is configured to receive SCL communication signal <NUM> at second input <NUM> and invert SCL communication signal <NUM> to produce an inverted communication signal at second output <NUM>. Second coupling capacitor <NUM> is configured to receive the inverted communication signal at third terminal <NUM>. The inverted communication signal drives second coupling capacitor <NUM> to produce compensation signal <NUM> having an opposite polarity and similar or equivalent magnitude to SCL interference signal <NUM>. Again through the electrical interconnection of compensation circuit <NUM> to shield <NUM> (<FIG>), compensation signal <NUM> may therefore reduce SCL interference signal <NUM> on shield <NUM>. Accordingly, compensation circuit <NUM> can inject compensating charges (e.g., compensation signal <NUM>) synchronously in response to SDA interference signal <NUM> and SCL interference signal <NUM>. Further, if SDA and SCL interference signals <NUM>, <NUM> are occurring simultaneously, two compensating charges will be injected simultaneously as compensation signal <NUM>.

In some embodiments, first and second coupling capacitors <NUM>, <NUM> may be fixed capacitors having a capacitance value determined during manufacture or final test. Alternatively, first and second coupling capacitors <NUM>, <NUM> may be programmable capacitor arrays. A programmable capacitor array is typically configured with an array of switches each connected in series to one of an array of capacitors which in turn are connected to an input. Each switch of the array may be switched on to load a capacitor on the input of the array or switched off to remove the capacitor from the input. Thus, such programmable capacitor arrays have a variable capacitance.

In some embodiments, digital processing circuitry <NUM>, labeled PROCESSOR, of ASIC <NUM> may include a calibration algorithm <NUM>, labeled CAL, that may be executed during final test of sensor package <NUM> and/or periodically when sensor package <NUM> is operational to calibrate or otherwise set capacitance values for each of first and second coupling capacitors <NUM>, <NUM> (e.g., the programmable capacitor arrays). Thus, through the execution of calibration algorithm <NUM>, digital processing circuitry <NUM> may determine the capacitance values for each of first and second coupling capacitors <NUM>, <NUM> for producing compensation signal <NUM>. The calibration of first and second capacitors <NUM>, <NUM> (e.g., the programmable capacitor arrays) will be discussed in detail in connection with <FIG>.

ASIC <NUM> further includes logic buffers <NUM> interconnected between SDA off-chip bond pad 112A and digital processing circuitry <NUM>, as well as between SCL off-chip bond pad 112B and digital processing circuitry <NUM>. Logic buffers <NUM> include multiple inverters connected in series that function to preserve the sharp edges of the logic signals (e.g., SDA and SCL communication signals <NUM>, <NUM>) despite capacitive loading along the signal path. In the illustrated configuration, logic buffers <NUM> have a tri-state capability because the signal path is bi-directional. That is, SDA communication signal <NUM> (bits) can be transmitted from SDA package lead 100A to digital processing circuitry <NUM> (e.g., sensor package <NUM> receiving data from electronic components <NUM> in a first state) or from digital processing circuitry <NUM> to SDA package lead 100A (e.g., sensor package <NUM> sending data to electronic components <NUM> in a second state). Similarly, SCL communication signal <NUM> (bits) can be transmitted from SCL package lead 100B to digital processing circuitry <NUM> (e.g., sensor package <NUM> receiving a clock signal from electronic components <NUM> in the first state) or from digital processing circuitry <NUM> to SCL package lead 100B in the second state. Thus, logic buffers <NUM> may be inserted in both directions. However, when logic buffers <NUM> that are used to receive data are operating, the logic buffers used to send data must be disabled to avoid the electrical nodes(s) from being driven simultaneously to conflicting logic states (hence the third state, output in high impedance). In some embodiments, these logic buffers <NUM> may be used to drive state transitions at SDA and SCL off-chip bond pads 112A, 112B when executing calibration algorithm <NUM>, as will be discussed below.

<FIG> shows a flowchart of an interference compensation process <NUM> in accordance with another embodiment. Interference compensation process <NUM> may be implemented in sensor package <NUM> utilizing compensation circuit <NUM> to compensate for disturbances on shield <NUM> (<FIG>) that might otherwise corrupt the accuracy of output signal <NUM> (<FIG>). Thus, <FIG> should be referred to concurrently with the following description of interference compensation process <NUM>.

At a block <NUM>, activation of sensor package <NUM> commences and shield voltage <NUM> is provided to shield <NUM> (<FIG>) by voltage regulator <NUM>. At a block <NUM>, communication signals (SDA and SCL communication signals <NUM>, <NUM>) are monitored for interference signals (SDA and SCL interference signals <NUM>, <NUM>). By way of example, first and second logic inverters <NUM>, <NUM> receive and invert their respective communication signals <NUM>, <NUM>. SDA and SCL interference signals <NUM>, <NUM> may include noise spikes (e.g., logic transitions). At a query block <NUM>, a determination is made as to whether SDA and/or SCL interference signals <NUM>, <NUM> are detected.

When either of SDA and/or SCL interference signals <NUM>, <NUM> is detected at query block <NUM>, process control continues with a block <NUM> where compensation signal <NUM> is produced by compensation circuit <NUM> as described above. At a block <NUM>, compensation signal <NUM> is provided to shield <NUM>. That is, compensation signal <NUM> is electrically communicated to second bond pad <NUM> of ASIC <NUM> that is electrically coupled to shield <NUM> via shield line <NUM>, first bond pad <NUM> of sensor die <NUM>, and an electrically conductive pathway represented by via <NUM> (<FIG>). Following either of block <NUM> or when a determination is made at query block <NUM> that neither SDA interference signal <NUM> nor SCL interference signal <NUM> is detected, process control continues with a query block <NUM>.

At query block <NUM>, a determination is made as to whether interference compensation process <NUM> is to continue. For example, a continuation of interference compensation process <NUM> may occur for a total duration that sensor package <NUM> is activated (e.g., powered up) and a discontinuation of interference compensation process <NUM> may occur when sensor package <NUM> is deactivated (e.g., powered down). When the execution of interference compensation process <NUM> is to continue, process control loops back to block <NUM> to continue monitoring for SDA and/or SCL interference signals <NUM>, <NUM>. Alternatively, the execution of interference compensation process <NUM> ends when a determination is made that the execution of interference compensation process <NUM> is to be discontinued.

<FIG> shows a flowchart of a calibration process <NUM> in accordance with some embodiments. Calibration process <NUM> provides example methodology that may be performed through the execution of calibration algorithm <NUM> embedded in digital processing circuitry <NUM> of sensor package <NUM>. Thus, <FIG> should be referred to concurrently with the following description of calibration process <NUM>. When first and second coupling capacitors <NUM>, <NUM> are programmable capacitor arrays, calibration process <NUM> enables the capacitance values of first and second coupling capacitors <NUM>, <NUM> to be set to match the package parasitic capacitance resulting from interference signals <NUM>, <NUM>. Thus, calibration process <NUM> may be performed during final test of sensor package <NUM> and prior to execution of interference compensation process <NUM> (<FIG>). Alternatively, calibration process <NUM> may be executed as a Built-in-Self-Test (BIST) calibration function in sensor package <NUM>. For simplicity, calibration process <NUM> will be described in connection with determining a capacitance value for the programmable capacitor array represented by first coupling capacitor <NUM>. However, the same methodology can be repeated to determine a capacitance value for the programmable capacitor array represented by second coupling capacitor <NUM>.

Calibration process <NUM> relies upon the presumption that the signal acquisition sequence in an analog signal chain implemented with switched capacitor technology is especially susceptible to interferences at critical times (e.g., just before the end of a SAMPLE phase resulting in corruption of the sampled signal or just before the end of an AUTOZERO phase of an amplifier stage resulting in corruption of a sampled offset). In accordance with calibration process <NUM>, by purposely creating a disturbance on shield voltage <NUM> at one of these critical times, the susceptibility of sensor package to communication noise (e.g., interference signals <NUM>, <NUM>) can be detected by comparing output signal <NUM> with and without disturbance induced on shield <NUM> and subsequently can be corrected by determining the proper capacitance value of the coupling capacitor (e.g., first coupling capacitor <NUM>).

At a block <NUM>, sensor package <NUM> is placed in a test mode and the capacitor value for first coupling capacitor <NUM> is set to zero. In response to the capacitor value being zero, at a block <NUM>, a baseline signal output, e.g., a first output signal <NUM>, is measured. The measured first output signal <NUM> is referred to herein as "RESULT#<NUM>. " Next at a block <NUM>, a transition is driven on SDA communication line 116A. That is, processing circuitry <NUM>, via logic buffers <NUM> coupled to SDA off-chip bond pad <NUM> A, periodically drives a state transition (e.g., High-to-Low or Low-to-High) on SDA communication line 116A at a critical time of the signal acquisition sequence, which can impose SDA interference signal <NUM> on shield voltage <NUM>.

At a block <NUM>, a second output signal <NUM> is measured. The measured second output signal <NUM> is referred to herein as "RESULT#<NUM>. " Since the state transition driven on SDA communication line 116A and the acquisition sequence are synchronous, the delay between them can be accurately controlled and is repeatable. Therefore, averaging can be applied to get an accurate measured second output signal <NUM> (e.g., RESULT#<NUM>). At a block <NUM>, an absolute value of a difference between the first and second output signals <NUM> is calculated (e.g. DIFF#<NUM> = ABS(RESULT#<NUM>-RESULT#<NUM>)). This difference is referred to as an error or shift.

At a query block <NUM>, a determination is made as to whether DIFF#<NUM> (e.g., the error) is greater than an internal threshold (THR). When DIFF#<NUM> is less than the threshold, a conclusion is made at a block <NUM> that the package parasitic coupling is negligible and the capacitance value for compensation signal <NUM> is set to zero. Thereafter, calibration process <NUM> ends or calibration process <NUM> may be repeated for second coupling capacitor <NUM>, as mentioned above. However, when a determination is made that DIFF#<NUM> is greater than the internal threshold, calibration is launched at a block <NUM>. During calibration, the capacitance value of the programmable capacitor array represented by first coupling capacitor <NUM> is swept to search for the minimum error on output signal <NUM>.

At block <NUM>, the current best, or minimum, error (e.g., BEST_DIFF) is set equal to the current error (e.g., DIFF#<NUM>). Further, the current best capacitance value (e.g., BEST_CAP) is set equal to zero. Next, at a block <NUM>, the capacitor value of the programmable capacitor array represented by first coupling capacitor <NUM> is incremented. At a block <NUM>, a transition is again driven on SDA communication line 116A. That is, processing circuitry <NUM>, via logic buffers <NUM> coupled to SDA off-chip bond pad <NUM> A, periodically drives a state transition (e.g., High-to-Low or Low-to-High) on SDA communication line 116A at a critical time of the signal acquisition sequence, which can impose SDA interference signal <NUM> on shield voltage <NUM>. At a block <NUM>, sensor output signal <NUM> is again measured. The measured output signal <NUM> is referred to herein as "RESULT#n. " Again, averaging can be applied to get an accurate measured output signal <NUM> (e.g., RESULT#n). At a block <NUM>, an absolute value of a difference between the output signals <NUM> is calculated (e.g. DIFF#n = ABS(RESULT#n-RESULT#<NUM>).

At a query block <NUM>, a determination is made as to whether DIFF#n (e.g., the calculated error) is less than the current best, or minimum error (e.g., BEST _DIFF). When a determination is made at query block <NUM> that DIFF#n is less than the BEST DIFF, thereby indicating that the error has been reduced, process control continues at a block <NUM>. At block <NUM>, the current best, or minimum, error (e.g., BEST_DIFF) is set equal to the current error (e.g., DIFF#n). Further, the current best capacitance value (e.g., BEST_CAP) is set to the current capacitor value (set at block <NUM>). Following block <NUM>, process control continues with a query block <NUM>. When a determination is made at query block <NUM> that DIFF#n (e.g., the calculated error) is greater than the current best, or minimum, error (e.g., BEST_DIFF), process control also proceeds to query block <NUM>.

At query block <NUM>, a determination is made as to whether the maximum capacitance value for the programmable capacitor array, represented by first coupling capacitor <NUM>, has been reached. When the maximum capacitance value has not been reached, process control loops back to block <NUM> to increment the capacitance value and repeat process blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> for the next capacitance value for programmable capacitor array. However, when a determination is made at query block <NUM> that the maximum capacitance value for the programmable capacitor array, represented by first coupling capacitor <NUM>, has been reached calibration process <NUM> continues with a processing block <NUM>.

At block <NUM>, the compensation signal value (e.g., compensation signal <NUM>) is set to the best capacitance value (e.g., BEST_CAP), saved at processing block <NUM>, that produced the minimal error on the output signal <NUM>. The capacitance value which minimized the error on output signal <NUM> is thus selected and can be written in memory associated with digital processing circuitry <NUM> for using during operation of sensor package <NUM>. Thereafter, calibration process <NUM> ends or calibration process <NUM> may be repeated for second coupling capacitor <NUM>, as mentioned above.

To summarize, during execution of calibration process <NUM> for first coupling capacitor <NUM>, a sensor state machine periodically drives a state transition (e.g., edge) on SDA communication line 116A at a known critical time of the acquisition sequence to disturb shield voltage <NUM> and cause corruption of output signal <NUM> (<FIG>). The state machine sweeps the values of the programmable capacitor array for first coupling capacitor <NUM> and monitors the error on output signal <NUM>. Calibration process <NUM> ends by selecting the capacitance value for first coupling capacitor <NUM> which has produced the minimal error on output signal <NUM>. Thereafter, calibration process <NUM> can be repeated for second coupling capacitor <NUM>. Calibration process <NUM> may be executed individually for each of first and second coupling capacitors <NUM>, <NUM> because the parasitic capacitance between SDA communication signal <NUM> and shield voltage <NUM> may be different from the parasitic capacitance between SCL communication signal <NUM> and shield voltage <NUM>. Although calibration process <NUM> is discussed in connection with the calibration of first and second coupling capacitors <NUM>, <NUM> associated with communication lines 116A and 116B, is should be understood that calibration process <NUM> may be executed in connection with other programmable capacitor arrays associated with other logic pins of a sensor package.

Thus, execution of the various processes described herein enable the utilization of a compensation circuit in a sensor package to compensate for disturbances on the shield that might otherwise corrupt the accuracy of output signal from the sensor package. Further, capacitance values can be selected to ideally minimize the error on the output signal. It should be understood that certain ones of the process blocks depicted in <FIG> and <FIG> may be performed in parallel with each other or with performing other processes. In addition, the particular ordering of some of the process blocks depicted in <FIG> and <FIG> may be modified while achieving substantially the same result. Accordingly, such modifications are intended to be included within the scope of the claimed invention.

Embodiments described herein entail a sensor package with enhanced robustness against interference from data communication and a method of operation. More particularly, the sensor package includes a compensation circuit integrated into an application specific integrated circuit (ASIC) die of the sensor package. The compensation circuit is configured to inject a compensating charge into a shield surrounding the active sensing portion that has a similar magnitude, but an opposite polarity, as an interference signal injected into the shield via package parasitics. Injection of a compensating charge similar in magnitude and opposite in polarity may achieve significant charge reduction and shield voltage stabilization. Thus, a disturbance on a shield voltage of the shield, that might otherwise corrupt an output signal from the sensor package, may be reduced for improved performance of the sensor package. The embodiments described herein may be generalized to a variety of capacitive transducers, circuits, and components, such as accelerometers, gyroscopes, pressure sensors, microphones, and so forth.

Claim 1:
A sensor package (<NUM>) comprising:
a first die (<NUM>) having a capacitive sensor, the capacitive sensor including an active sensing portion (<NUM>) and a shield (<NUM>) surrounding the active sensing portion; and
a second die (<NUM>) comprising a voltage regulator (<NUM>) configured to produce a shield voltage (<NUM>) and a compensation circuit (<NUM>) configured to produce a compensation signal (<NUM>), the voltage regulator and the compensation circuit each being directly electrically coupled to the shield, wherein the voltage regulator is configured to regulate the shield to the shield voltage, and the compensation signal produced by the compensation circuit is configured to reduce an interference signal (<NUM>, <NUM>) on the shield voltage.