Patent Description:
As a scaling technique for increasing a density of a semiconductor device, a multi-gate transistor for forming a silicon body of a fin or nano-wire shape on a substrate and forming a gate on a surface of the silicon body has been suggested.

Because this multi-gate transistor uses a three-dimensional channel, the multi-gate transistor may be scaled. Also, even though a gate length of the multi-gate transistor is not increased, a current control capability may be improved. In addition, a short channel effect (SCE) in which a potential of a channel region is affected by a drain voltage may be suppressed effectively.

One or more embodiments provide a semiconductor device in which a lower wiring layer, which is a power rail or a ground rail, is disposed below a substrate, a sacrificial layer is disposed between a lower surface of the substrate and a lower wiring layer, and a through via insulating layer vertically overlapped with the lower wiring layer is disposed inside the sacrificial layer. The through via insulating layer disposed inside the sacrificial layer may serve as an etch stop layer in a process of forming a lower wiring trench in which a lower wiring layer is formed. Accordingly, the semiconductor device may prevent the lower wiring trench from being excessively etched or slightly etched, thereby improving reliability of a connection relation between a through via and a lower wiring layer.

According to some embodiments, a semiconductor device includes: a first substrate including a first surface and a second surface opposite the first surface; an active pattern extending in a first horizontal direction on the first surface of the first substrate; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern; a source/drain region on at least one side of the gate electrode on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the second surface of the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer including a first portion extending along the sidewall of the through via trench and a second portion in the recess. The second portion of the through via insulating layer is in contact with an uppermost surface of the lower wiring layer.

According to some embodiments, a semiconductor device includes: a first substrate including a first surface and a second surface opposite the first surface; an active pattern extending in a first horizontal direction on the first surface of the first substrate; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern; an interlayer insulating layer surrounding a sidewall of the gate electrode; a sacrificial layer on the second surface of the first substrate; a lower wiring trench on a lower surface of the sacrificial layer; a lower wiring layer inside the lower wiring trench and spaced apart from the sacrificial layer; a through via connected to the lower wiring layer and passing through the interlayer insulating layer and the sacrificial layer in a vertical direction; and a through via insulating layer including a first portion extending along a sidewall of the through via and a second portion protruding from the first portion in the second horizontal direction. A lower surface of the second portion of the through via insulating layer and the lower surface of the sacrificial layer are provided on a first common plane, and an upper surface of the second portion of the through via insulating layer and an upper surface of the sacrificial layer are provided on a second common plane, and the second portion of the through via insulating layer is in contact with an uppermost surface of the lower wiring layer.

The above and other aspects and features will be more apparent from the following description of embodiments with reference to the attached drawings, in which:.

Embodiments will now be described with reference to the accompanying drawings. Embodiments described herein are example embodiments. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be also understood that, even if a certain step or operation of manufacturing an apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation. A semiconductor device according to some embodiments includes a multi-bridge channel field effect transistor (MBCFET™) including a nanosheet by way of example, but embodiments are not limited thereto. In some other embodiments, the semiconductor device may include a fin-type transistor (FinFET) that includes a channel region of a fin-type pattern shape.

Hereinafter, a semiconductor device according to some embodiments will be described with reference to <FIG>.

<FIG> is a schematic layout view illustrating a semiconductor device according to some embodiments. <FIG> is a cross-sectional view taken along line A-A' of <FIG>. <FIG> is a cross-sectional view taken along line B-B' of <FIG>. <FIG> is a cross-sectional view taken along line C-C' of <FIG>. <FIG> is an enlarged view illustrating a region S1 of <FIG>.

Referring to <FIG>, the semiconductor device according to some embodiments includes a first substrate <NUM>, an active pattern <NUM>, a field insulating layer <NUM>, first and plurality of second nanosheets NW1 and NW2, a sacrificial layer <NUM>, a second substrate <NUM>, a lower wiring layer <NUM>, a lower wiring insulating layer <NUM>, first and second gate electrodes G1 and G2, a gate spacer <NUM>, a gate insulating layer <NUM>, a capping pattern <NUM>, a source/drain region SD, a first interlayer insulating layer <NUM>, a silicide layer <NUM>, a through via <NUM>, a through via insulating layer <NUM>, a source/drain contact CA, first and second gate contacts CB1 and CB2, an etch stop layer <NUM>, a second interlayer insulating layer <NUM>, first and second vias V1 and V2, a third interlayer insulating layer <NUM>, and first to third upper wiring layers <NUM>, <NUM> and <NUM>.

The first substrate <NUM> may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the first substrate <NUM> may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but embodiments are not limited thereto.

The first substrate <NUM> may include a first surface 100a and a second surface 100b opposite the first surface 100a. For example, the first surface 100a of the first substrate <NUM> may be an upper surface of the first substrate <NUM>, and the second surface 100b of the first substrate <NUM> may be a lower surface of the first substrate <NUM>.

Hereinafter, each of a first horizontal direction DR1 and a second horizontal direction DR2 may be a direction parallel with the first surface 100a of the first substrate <NUM>. The second horizontal direction DR2 may be different from the first horizontal direction DR1. The vertical direction DR3 may be perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2.

The active pattern <NUM> may extend in the first horizontal direction DR1 on the first surface 100a of the first substrate <NUM>. The active pattern <NUM> may protrude from the first surface 100a of the first substrate <NUM> in the vertical direction DR3. For example, the active pattern <NUM> may be a portion of the first substrate <NUM>, or may include an epitaxial layer grown from the first substrate <NUM>.

The field insulating layer <NUM> may be disposed on the first surface 100a of the first substrate <NUM>. The field insulating layer <NUM> may surround a sidewall of the active pattern <NUM>. For example, an upper surface of the active pattern <NUM> may be protrude in the vertical direction DR3 past an upper surface of the field insulating layer <NUM>, but embodiments are not limited thereto. In some other embodiments, the upper surface of the active pattern <NUM> may be formed on the same plane as the upper surface of the field insulating layer <NUM>. The field insulating layer <NUM> may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or their combination layer.

The plurality of first nanosheets NW1 may be disposed on the active pattern <NUM>. The plurality of first nanosheets NW1 may be disposed at a portion where the active pattern <NUM> and the first gate electrode G1 cross each other. The plurality of first nanosheets NW1 may include a plurality of nanosheets stacked to be spaced apart from each other in the vertical direction DR3. The plurality of second nanosheets NW2 may be disposed on the active pattern <NUM>. The plurality of second nanosheets NW2 may be disposed at a portion where the active pattern <NUM> and the second gate electrode G2 cross each other. The plurality of second nanosheets NW2 may be spaced apart from the plurality of first nanosheets NW <NUM> in the first horizontal direction DR1. The plurality of second nanosheets NW2 may include a plurality of nanosheets stacked to be spaced apart from each other in the vertical direction DR3.

In <FIG> and <FIG>, each of the plurality of first and second nanosheets NW <NUM> and NW2 is shown to include three nanosheets stacked to be spaced apart from one another in the vertical direction DR3, but this is for convenience of description, and embodiments are not limited thereto. In some other embodiment, each of the plurality of first and second nanosheets NW1 and NW2 may include four or more nanosheets stacked to be spaced apart from each other in the vertical direction DR3.

The sacrificial layer <NUM> may be disposed on the second surface 100b of the first substrate <NUM>. An upper surface 110a of the sacrificial layer <NUM> may be in contact with the second surface 100b of the first substrate <NUM>. For example, the sacrificial layer <NUM> may be disposed to be conformal. The sacrificial layer <NUM> may include a material different from that of the first substrate <NUM>. The sacrificial layer <NUM> may include a material having an etching selectivity with respect to the material included in the first substrate <NUM>. For example, the sacrificial layer <NUM> may include silicon germanium (SiGe). That is, for example, the first substrate <NUM> may include silicon (Si), and the sacrificial layer <NUM> may include silicon germanium (SiGe).

The second substrate <NUM> may be disposed on a lower surface 110b of the sacrificial layer <NUM>, which is disposed on the second surface 100b of the first substrate <NUM>. The second substrate <NUM> may be in contact with the lower surface 110b of the sacrificial layer <NUM>. The second substrate <NUM> may include a material different from that of the sacrificial layer <NUM>. The second substrate <NUM> may include a material having an etching selectivity with respect to the sacrificial layer <NUM>. For example, the second substrate <NUM> may include silicon (Si). That is, the second substrate <NUM> may include silicon (Si), and the sacrificial layer <NUM> may include silicon germanium (SiGe).

The first gate electrode G1 may extend in the second horizontal direction DR2 on the active pattern <NUM> and the field insulating layer <NUM>. The first gate electrode G1 may surround the plurality of first nanosheets NW1. The second gate electrode G2 may extend in the second horizontal direction DR2 on the active pattern <NUM> and the field insulating layer <NUM>. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The second gate electrode G2 may surround the plurality of second nanosheets NW2.

Each of the first and second gate electrodes G1 and G2 may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or their combination. Each of the first and second gate electrodes G1 and G2 may include a conductive metal oxide, a conductive metal oxynitride, and the like, and may include oxidized forms of the aforementioned materials.

The gate spacer <NUM> may extend in the second horizontal direction DR2 along both sidewalls of the first gate electrode G1 on the field insulating layer <NUM> and the upper surface of the uppermost nanosheet of the plurality of first nanosheets NW1. In addition, the gate spacer <NUM> may extend in the second horizontal direction DR2 along both sidewalls of the second gate electrode G2 on the field insulating layer <NUM> and the upper surface of the uppermost nanosheet of the plurality of second nanosheets NW2. The gate spacer <NUM> may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO<NUM>), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or their combination, but embodiments are not limited thereto.

The source/drain region SD may be disposed on at least one side of each of the first and second gate electrodes G1 and G2 on the active pattern <NUM>. For example, the source/drain region SD may be disposed between the first gate electrode G1 and the second gate electrode G2 on the active pattern <NUM>. The source/drain region SD may be in contact with each of the plurality of first nanosheets NW1 and the plurality of second nanosheets NW2. For example, an upper surface of the source/drain region SD may be formed to be higher than the upper surface of the uppermost nanosheet of the plurality of first nanosheets NW1, but embodiments are not limited thereto.

The gate insulating layer <NUM> may be disposed between each of the first and second gate electrodes G1 and G2 and the gate spacer <NUM>. The gate insulating layer <NUM> may be disposed between each of the first and second gate electrodes G1 and G2 and the active pattern <NUM>. The gate insulating layer <NUM> may be disposed between each of the first and second gate electrodes G1 and G2 and the field insulating layer <NUM>. The gate insulating layer <NUM> may be disposed between the first gate electrode G1 and the plurality of first nanosheets NW1. The gate insulating layer <NUM> may be disposed between the second gate electrode G2 and the plurality of second nanosheets NW2.

The gate insulating layer <NUM> may be disposed between each of the first and second gate electrodes G1 and G2 and the source/drain region SD. For example, the gate insulating layer <NUM> may be in contact with the source/drain region SD, but embodiments are not limited thereto. In some other embodiments, an inner spacer may be disposed between each of the first and second gate electrodes G1 and G2 and the source/drain region SD.

The gate insulating layer <NUM> may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of the silicon oxide. The high dielectric constant material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

The semiconductor device according to some other embodiments may include a negative capacitance (NC) FET based on a negative capacitor. For example, the gate insulating layer <NUM> may include a ferroelectric material layer having ferroelectric characteristics and a paraelectric material layer having paraelectric characteristics.

The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the total capacitance is more reduced than the capacitance of each individual capacitor. On the other hand, when at least one of capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than an absolute value of each individual capacitance.

When a ferroelectric material layer having a negative capacitance and a paraelectric material layer having a positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer, which are connected in series, may be increased. Based on the total capacitance value that is increased, a transistor having a ferroelectric material layer may have a subthreshold swing (SS) less than <NUM> mV/decade at a room temperature.

The ferroelectric material layer may have ferroelectric characteristics. The ferroelectric material layer may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. In this case, for example, the hafnium zirconium oxide may be a material doped with zirconium (Zr) in hafnium oxide. For another example, the hafnium zirconium oxide may be a compound of hafnium (Hf) and zirconium (Zr) and oxygen (O).

The ferroelectric material layer may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). A type of the dopant included in the ferroelectric material layer may be varied depending on the ferroelectric material of the ferroelectric material layer.

When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

When the dopant is aluminum (Al), the ferroelectric material layer may include aluminum of <NUM> at% to <NUM> at% (atomic%). In this case, a ratio of the dopant may be a ratio of aluminum to a sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material layer may include silicon of <NUM> at% to <NUM> at%. When the dopant is yttrium (Y), the ferroelectric material layer may include yttrium of <NUM> at% to <NUM> at%. When the dopant is gadolinium (Gd), the ferroelectric material layer may include gadolinium of <NUM> at% to <NUM> at%. When the dopant is zirconium (Zr), the ferroelectric material layer may include zirconium of <NUM> at% to <NUM> at%.

The paraelectric material layer may have paraelectric characteristics. The paraelectric material layer may include, for example, at least one of silicon oxide or metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, or aluminum oxide.

The ferroelectric material layer and the paraelectric material layer may include the same material. Although the ferroelectric material layer has ferroelectric characteristics, the paraelectric material layer may not have ferroelectric characteristics. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, a crystal structure of hafnium oxide included in the ferroelectric material layer is different from that of hafnium oxide included in the paraelectric material layer.

The ferroelectric material layer may have a thickness having ferroelectric characteristics. The thickness of the ferroelectric material layer may be, for example, <NUM> to <NUM>, but is not limited thereto. Because a threshold thickness indicating ferroelectric characteristics may be varied depending on each ferroelectric material, the thickness of the ferroelectric material layer may be varied depending on the ferroelectric material.

For example, the gate insulating layer <NUM> may include one ferroelectric material layer. For another example, the gate insulating layer <NUM> may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer <NUM> may have a stacked layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

The capping pattern <NUM> may extend in the second horizontal direction DR2 on each of the first gate electrode G1, the gate insulating layer <NUM> and the gate spacer <NUM>. Also, the capping pattern <NUM> may extend in the second horizontal direction DR2 on each of the second gate electrode G2, the gate insulating layer <NUM>, and the gate spacer <NUM>. For example, the capping pattern <NUM> may be in contact with an upper surface of the gate spacer <NUM>, but embodiments are not limited thereto. In some other embodiments, the capping pattern <NUM> may be disposed between the gate spacers <NUM>.

The capping pattern <NUM> may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO<NUM>), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or their combination, but embodiments are not limited thereto.

The first interlayer insulating layer <NUM> may be disposed on the field insulating layer <NUM>. The first interlayer insulating layer <NUM> may cover the source/drain regions SD. The first interlayer insulating layer <NUM> may surround a sidewall of each of the gate spacer <NUM> and the capping pattern <NUM>. For example, an upper surface of the first interlayer insulating layer <NUM> may be formed on the same plane as that of the capping pattern <NUM>, but embodiments are not limited thereto. In some other embodiments, the first interlayer insulating layer <NUM> may the upper surface of the capping pattern <NUM>.

The first interlayer insulating layer <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. For example, the low dielectric constant material may include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCycloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoxySiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), Tonen SilaZen (TOSZ), Fluoride Silicate Glass (FSG), polyimide nanofoams such as polypropylene oxide, Carbon Doped silicon Oxide (CDO), Organo Silicate Glass (OSG), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica or their combination, but embodiments are not limited thereto.

A through via trench 160T may extend into the second substrate <NUM> by passing through the first interlayer insulating layer <NUM>, the field insulating layer <NUM>, the first substrate <NUM>, and the sacrificial layer <NUM> in the vertical direction DR3. For example, the through via trench 160T may be formed between the first gate electrode G1 and the second gate electrode G2. The through via trench 160T may be spaced apart from each of the first gate electrode G1 and the second gate electrode G2 in the first horizontal direction DR1. For example, the through via trench 160T may be spaced apart from the active pattern <NUM> in the second horizontal direction DR2.

A first recess R1 may be formed inside the sacrificial layer <NUM>. The first recess R1 may protrude from a first sidewall of the through via trench 160T in a reverse direction of the second horizontal direction DR2. For example, an upper surface of the first recess R1 may be formed on the same plane as the upper surface of the sacrificial layer <NUM>. Also, a lower surface of the first recess R1 may be formed on the same plane as the lower surface of the sacrificial layer <NUM>.

A second recess R2 may be formed inside the sacrificial layer <NUM>. The second recess R2 may protrude in the second horizontal direction DR2 from a second sidewall of the through via trench 160T opposite the first sidewall of the through via trench 160T in the second horizontal direction DR2. For example, an upper surface of the second recess R2 may be formed on the same plane as the upper surface of the sacrificial layer <NUM>. In addition, a lower surface of the second recess R2 may be formed on the same plane as the lower surface of the sacrificial layer <NUM>. Although the first recess R1 and the second recess R2 are described to be provided separately, for example, the first recess R1 and the second recess R2 may protrude in a lateral direction from the sidewall of the through via trench 160T and thus may be integrally formed.

The through via insulating layer <NUM> may be disposed along the sidewall of the through via trench 160T. For example, the through via insulating layer <NUM> may be disposed to be conformal. The through via insulating layer <NUM> may include a first portion 165_1 and a second portion 165_2. The first portion 165_1 of the through via insulating layer <NUM> may be disposed along the sidewall of the through via trench 160T. For example, the first portion 165_1 of the through via insulating layer <NUM> may extend to the upper surface of the first interlayer insulating layer <NUM>. Also, the first portion 165_1 of the through via insulating layer <NUM> may extend to the inside of the second substrate <NUM>.

The second portion 165_2 of the through via insulating layer <NUM> may be disposed inside each of the first recess R1 and the second recess R2. For example, the second portion 165_2 of the through via insulating layer <NUM> may fill the inside of each of the first recess R1 and the second recess R2. The second portion 165_2 of the through via insulating layer <NUM> may protrude in a lateral direction from the first portion 165_1 of the through via insulating layer <NUM>.

For example, the second portion 165_2 of the through via insulating layer <NUM> disposed inside the first recess R1 may protrude in a reverse direction of the second horizontal direction DR2 from the first portion 165_1 of the through via insulating layer <NUM> disposed along the first sidewall of the through via trench 160T. In addition, the second portion 165_2 of the through via insulating layer <NUM> disposed inside the second recess R2 may protrude from the first portion 165_1 of the through via insulating layer <NUM> disposed along the second sidewall of the through via trench 160T in the second horizontal direction DR2.

An upper surface of the second portion 165_2 of the through via insulating layer <NUM> may be formed on the same plane as the upper surface of the sacrificial layer <NUM>. In addition, a lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be formed on the same plane as the lower surface of the sacrificial layer <NUM>. Although the second portions 165_2 of the through via insulating layer <NUM> disposed inside the first recess R1 and the second recess R2 are described to be provided separately, for example, the second portions 165_2 of the through via insulating layer <NUM> disposed inside the first recess R1 and the second recess R2 may protrude in a lateral direction from the first portion 165_1 of the through via insulating layer <NUM> and may be integrally formed.

The through via insulating layer <NUM> may include an insulating material. For example, the through via insulating layer <NUM> may include at least one of silicon nitride (SiN), silicon oxide (SiO<NUM>), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN), but embodiments are not limited thereto.

The through via <NUM> may be disposed on the through via insulating layer <NUM> inside the through via trench 160T. For example, the through via <NUM> may overlap the sacrificial layer <NUM> in the second horizontal direction DR2. That is, a lower surface of the through via <NUM> may be formed to be lower than the lower surface 110b of the sacrificial layer <NUM>. The through via <NUM> may include a through via barrier layer <NUM> and a through via filling layer <NUM>.

The through via barrier layer <NUM> may be disposed on the through via insulating layer <NUM> along the sidewall of the through via trench 160T. The through via barrier layer <NUM> may be disposed along a bottom surface of the through via trench 160T. For example, the through via barrier layer <NUM> may be disposed to be conformal. For example, an uppermost surface of the through via barrier layer <NUM> may be formed on the same plane as that of the first interlayer insulating layer <NUM>, but embodiments are not limited thereto.

The through via barrier layer <NUM> may include one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and their combination, but embodiments are not limited thereto.

The through via filling layer <NUM> may be disposed on the through via barrier layer <NUM> inside the through via trench 160T. The through via filling layer <NUM> may fill the inside of the through via trench 160T on the through via barrier layer <NUM>. For example, an upper surface of the through via filling layer <NUM> may be formed on the same plane as the uppermost surface of the first interlayer insulating layer <NUM>, but embodiments are not limited thereto.

The through via filling layer <NUM> may include at least one of, for example, molybdenum (Mo), copper (Cu), carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), tungsten (W), ruthenium (Ru), iridium (Ir), or rhodium (Rh), but embodiments are not limited thereto.

The lower wiring trench 130T may be formed on the second surface 100b of the first substrate <NUM>. For example, the lower wiring trench 130T may be formed inside the second substrate <NUM> on the lower surface 110b of the sacrificial layer <NUM>. For example, as the lower wiring trench 130T approaches the lower surface 110b of the sacrificial layer <NUM>, its width in the second horizontal direction DR2 may be reduced.

For example, the lower wiring trench 130T may overlap each of the through via <NUM> and the through via insulating layer <NUM> in the vertical direction DR3. For example, the lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be exposed through the lower wiring trench 130T. Also, the first portion 165_1 of the through via insulating layer <NUM> and the through via <NUM> may be exposed through the lower wiring trench 130T. In this case, the through via barrier layer <NUM> forming the bottom surface of the through via trench 160T may be exposed through the lower wiring trench 130T.

For example, a width W2 of the through via trench 160T in the second horizontal direction DR2, at a position adjacent to the second portion 165_2 of the through via insulating layer <NUM>, may be smaller than a width W1 of the second portion 165_2 of the through via insulating layer <NUM> in the second direction DR2. In this case, the width W1 of the second portion 165_2 of the through via insulating layer <NUM> in the second horizontal direction DR2 may be referred to as a width in the second horizontal direction DR2 between a sidewall of the second portion 165_2 of the through via insulating layer <NUM>, which is in contact with the sacrificial layer <NUM> inside the first recess R1, and a sidewall of the second portion 165_2 of the through via insulating layer <NUM>, which is in contact with the sacrificial layer <NUM> inside the second recess R2.

For example, the lower surface of the second portion 165_2 of the through via insulating layer <NUM> disposed inside the first recess R1 may be in contact with the second substrate <NUM> disposed on a first sidewall 130Ts1 of the lower wiring trench 130T. In addition, the lower surface of the second portion 165_2 of the through via insulating layer <NUM> disposed inside the second recess R2 may be in contact with the second substrate <NUM> disposed on a second sidewall 130Ts2 of the lower wiring trench 130T opposite the first sidewall 130Ts1 of the lower wiring trench 130T in the second horizontal direction DR2.

The lower wiring insulating layer <NUM> may be disposed along the sidewall of the lower wiring trench 130T. For example, the lower wiring insulating layer <NUM> may be in contact with the lower surface 110b of the sacrificial layer <NUM>. The lower wiring insulating layer <NUM> may include an insulating material. For example, the lower wiring insulating layer <NUM> may include the same material as that of the through via insulating layer <NUM>, but embodiments are not limited thereto. In some other embodiments, the lower wiring insulating layer <NUM> and the through via insulating layer <NUM> may include different materials. The lower wiring insulating layer <NUM> may include at least one of, for example, silicon nitride (SiN), silicon oxide (SiO<NUM>), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN), but embodiments are not limited thereto.

The lower wiring layer <NUM> may be disposed inside the lower wiring trench 130T. At least a portion of the lower wiring layer <NUM> may be disposed inside the second portion 165_2 of the through via insulating layer <NUM>. An uppermost surface 130a of the lower wiring layer <NUM> may be in contact with the second portion 165_2 of the through via insulating layer <NUM>. Also, the lower wiring layer <NUM> may be in contact with a lowermost surface of the first portion 165_1 of the through via insulating layer <NUM> and a lowermost surface of the through via <NUM>. For example, the lower wiring layer <NUM> may be in contact with the through via barrier layer <NUM> forming a bottom surface of the through via <NUM>. For example, the lower wiring layer <NUM> may be spaced apart from the through via filling layer <NUM> in the vertical direction DR3, but embodiments are not limited thereto. For example, the lower wiring layer <NUM> may be either a power rail to which a power source is supplied or a ground rail that is grounded.

The uppermost surface 130a of the lower wiring layer <NUM> may be formed to be lower than the upper surface of the second portion 165_2 of the through via insulating layer <NUM>. That is, the uppermost surface 130a of the lower wiring layer <NUM> may be formed to be lower than the upper surface 110a of the sacrificial layer <NUM>. In addition, the uppermost surface 130a of the lower wiring layer <NUM> may be formed to be higher than the lower surface of the second portion 165_2 of the through via insulating layer <NUM>. That is, the uppermost surface 130a of the lower wiring layer <NUM> may be formed to be lower than the lower surface 110b of the sacrificial layer <NUM>.

For example, a width of the lower wiring layer <NUM> in the second horizontal direction DR2, at a position adjacent to the second portion 165_2 of the through via insulating layer <NUM>, may be smaller than the width W1 of the second portion 165_2 of the through via insulating layer <NUM> in the second horizontal direction DR2. For example, at least a portion of the lower wiring insulating layer <NUM> may be disposed between the lower wiring layer <NUM> and the first portion 165_1 of the through via insulating layer <NUM>, but embodiments are not limited thereto.

The lower wiring layer <NUM> may include a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM>. The lower wiring barrier layer <NUM> may be disposed along sidewalls and upper surface of the lower wiring trench 130T. For example, the lower wiring barrier layer <NUM> may be disposed to be conformal. For example, at least a portion of the lower wiring barrier layer <NUM> may be disposed inside the second portion 165_2 of the through via insulating layer <NUM>. The lower wiring layer <NUM> may be insulated from the second substrate <NUM> through the lower wiring insulating layer <NUM>.

The lower wiring barrier layer <NUM> includes one of, for example, cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and their combination, but embodiments are not limited thereto.

The lower wiring filling layer <NUM> may be disposed on the lower wiring barrier layer <NUM> inside the lower wiring trench 130T. The lower wiring filling layer <NUM> may fill the inside of the lower wiring trench 130T on the lower wiring barrier layer <NUM>. For example, a lower surface of the lower wiring filling layer <NUM> may be formed on the same plane as the lower surface of the second substrate <NUM>, but embodiments are not limited thereto.

The lower wiring filling layer <NUM> includes at least one of, for example, molybdenum (Mo), copper (Cu), carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), aluminum (Al), zirconium (Zr), tungsten (W), ruthenium (Ru), iridium (Ir), or rhodium (Rh), but embodiments are not limited thereto.

The source/drain contact CA may be disposed inside the first interlayer insulating layer <NUM>. The source/drain contact CA may be connected to the source/drain region SD. For example, an upper surface of the source/drain contact CA may be formed on the same plane as that of the through via <NUM>. For example, the upper surface of the source/drain contact CA may be formed on the same plane as the upper surface of the first interlayer insulating layer <NUM>, but embodiments are not limited thereto.

The source/drain contact CA may be in contact with the through via <NUM>. For example, the source/drain contact CA may be in contact with the through via filling layer <NUM>. The source/drain contact CA may overlap the through via <NUM> in the vertical direction DR3. Although the source/drain contact CA is shown as being formed as a single layer in <FIG> and <FIG>, this is for convenience of description, and embodiments are not limited thereto. That is, the source/drain contact CA may be formed of a multi-layer. The source/drain contact CA may include a conductive material.

The silicide layer <NUM> may be disposed between the source/drain region SD and the source/drain contact CA. The silicide layer <NUM> may be disposed along a boundary surface between the source/drain region SD and the source/drain contact CA. The silicide layer <NUM> may include, for example, a metal silicide material.

The first gate contact CB1 may be connected to the first gate electrode G1 by passing through the capping pattern <NUM> in the vertical direction DR3. The second gate contact CB2 may be connected to the second gate electrode G2 by passing through the capping pattern <NUM> in the vertical direction DR3. For example, upper surfaces of the first gate contact CB1 and the second gate contact CB2 may be formed on the same plane as the upper surface of the capping pattern <NUM>, but embodiments are not limited thereto.

Although <FIG> and <FIG> show that each of the first and second gate contacts CB1 and CB2 is formed as a single layer, this is for convenience of description, and embodiments are not limited thereto. That is, each of the first and second gate contacts CB1 and CB2 may be formed of a multi-layer. Each of the first and second gate contacts CB1 and CB2 may include a conductive material.

The etch stop layer <NUM> may be disposed on upper surfaces of the first interlayer insulating layer <NUM>, the capping pattern <NUM>, the first and second gate contacts CB <NUM> and CB2, the source/drain contact CA, and the through via <NUM>. <FIG> show that the etch stop layer <NUM> is formed as a single layer, but embodiments are not limited thereto. In some other embodiments, the etch stop layer <NUM> may be formed of a multi-layer. The etch stop layer <NUM> may include at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. The second interlayer insulating layer <NUM> may be disposed on the etch stop layer <NUM>. For example, the second interlayer insulating layer <NUM> may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material.

The first via V1 may be connected to each of the first gate contact CB <NUM> and the second gate contact CB2 by passing through the second interlayer insulating layer <NUM> and the etch stop layer <NUM> in the vertical direction DR3. The second via V2 may be connected to the source/drain contact CA by passing through the second interlayer insulating layer <NUM> and the etch stop layer <NUM> in the vertical direction DR3. Although <FIG> show that each of the first and second vias V1 and V2 is formed as a single layer, this is for convenience of description, and embodiments are not limited thereto. That is, each of the first and second vias V1 and V2 may be formed of a multi-layer. Each of the first and second vias V1 and V2 may include a conductive material.

The third interlayer insulating layer <NUM> may be disposed on the second interlayer insulating layer <NUM>. The third interlayer insulating layer <NUM> may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. Each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> may be disposed inside the third interlayer insulating layer <NUM>. For example, each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> may be sequentially spaced apart from one another in the first horizontal direction DR1. For example, each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> may extend in the second horizontal direction DR2, but embodiments are not limited thereto.

For example, the first upper wiring layer <NUM> may be disposed on the first via V1 disposed on the first gate contact CB1. The first upper wiring layer <NUM> may be connected to the first via V1 disposed on the first gate contact CB1. The second upper wiring layer <NUM> may be disposed on the second via V2 disposed on the source/drain contact CA. The second upper wiring layer <NUM> may be connected to the second via V2 disposed on the source/drain contact CA. The third upper wiring layer <NUM> may be disposed on the first via V1 disposed on the second gate contact CB2. The third upper wiring layer <NUM> may be connected to the first via V1 disposed on the second gate contact CB2.

Although <FIG> show that each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> is formed as a single layer, this is for convenience of description, and embodiments are not limited thereto. That is, each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> may be formed of a multi-layer. Each of the first to third upper wiring layers <NUM>, <NUM> and <NUM> may include a conductive material.

In the semiconductor device according to some embodiments, the lower wiring layer <NUM> which is a power rail or a ground rail may be disposed below the first substrate <NUM>, the sacrificial layer <NUM> may be disposed between the lower surface of the first substrate <NUM> and the lower wiring layer <NUM>, and the through via insulating layer <NUM>, which overlaps the lower wiring layer <NUM> in the vertical direction DR3, may be disposed inside the sacrificial layer <NUM>. The through via insulating layer <NUM> disposed inside the sacrificial layer <NUM> may serve as an etch stop layer in the process of forming the lower wiring trench 130T in which the lower wiring layer <NUM> is formed. Therefore, the semiconductor device according to some embodiments may improve reliability of a connection relation between the through via <NUM> and the lower wiring layer <NUM> by preventing the lower wiring trench 130T from being excessively or less etched.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments will be described with reference to <FIG>.

<FIG> are views illustrating operations of a method of manufacturing a semiconductor device shown in <FIG>.

Referring to <FIG> and <FIG>, a sacrificial layer <NUM> and a first substrate <NUM> may be sequentially formed on a second substrate <NUM>. For example, the sacrificial layer <NUM> may be epitaxially grown to be formed on the second substrate <NUM>.

A stacked structure <NUM> may be formed on the first substrate <NUM>. The stacked structure <NUM> may include first semiconductor layers <NUM> and second semiconductor layers <NUM>, which are alternately stacked on the first substrate <NUM>. For example, a first semiconductor layer <NUM> may be formed at a lowermost portion of the stacked structure <NUM>, and a second semiconductor layer <NUM> may be formed at an uppermost portion of the stacked structure <NUM>, but embodiments are not limited thereto. In some other embodiments, a first semiconductor layer <NUM> may be also formed at the uppermost portion of the stacked structure <NUM>. The first semiconductor layer <NUM> may include, for example, silicon germanium (SiGe). The second semiconductor layer <NUM> may include, for example, silicon (Si).

Referring to <FIG> and <FIG>, a portion of the stacked structure <NUM> may be etched. While the stacked structure <NUM> is being etched, a portion of the first substrate <NUM> may be also etched. Through the etching process, an active pattern <NUM> may be defined below the stacked structure <NUM> on a first surface 100a that is an upper surface of the first substrate <NUM>. The active pattern <NUM> may extend in the first horizontal direction DR1.

A field insulating layer <NUM> may be formed on the first surface 100a of the first substrate <NUM>. The field insulating layer <NUM> may surround sidewalls of the active pattern <NUM>. For example, an upper surface of the active pattern <NUM> may be formed to be higher than an upper surface of the field insulating layer <NUM>.

A pad oxide layer <NUM> may be formed to cover the upper surface of the field insulating layer105, exposed sidewalls of the active pattern <NUM> and sidewalls and upper surface of the stacked structure <NUM>. For example, the pad oxide layer <NUM> may be formed to be conformal. The pad oxide layer <NUM> may include, for example, silicon oxide (SiO<NUM>).

Referring to <FIG>, first and second dummy gates DG1 and DG2, and first and second dummy capping patterns DC1 and DC2 which extend in the second horizontal direction DR2 on the pad oxide layer <NUM> may be formed on the stacked structure <NUM> and the field insulating layer <NUM>. The first dummy capping pattern DC1 may be formed on the first dummy gate DG1. Also, the second dummy capping pattern DC2 may be formed on the second dummy gate DG2. The second dummy gate DG2 and the second dummy capping pattern DC2 may be respectively spaced apart from the first dummy gate DG1 and the first dummy capping pattern DC1 in the first horizontal direction DR1.

While the first and second dummy gates DG1 and DG2 and the first and second dummy capping patterns DC1 and DC2 are being formed, the remaining pad oxide layer <NUM>, except a portion overlapped with each of the first and second dummy gates DG1 and DG2 in the vertical direction DR3 on the first substrate <NUM>, may be removed.

A spacer material layer SM may be formed to cover sidewalls of each of the first and second dummy gates DG1 and DG2, sidewalls and upper surface of each of the first and second dummy capping patterns DC1 and DC2, exposed sidewalls and upper surface of the stacked structure <NUM>, and the upper surface of the field insulating layer <NUM>. For example, the spacer material layer SM may be formed to be conformal. The spacer material layer SM may include at least one of, for example, silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or their combination.

Referring to <FIG> and <FIG>, the stacked structure (<NUM> of <FIG>) may be etched using the first and second dummy capping patterns DC1 and DC2 and the first and second dummy gates DG1 and DG2 as masks to form a source/drain trench ST. For example, the source/drain trench ST may extend into the active pattern <NUM>.

While the source/drain trench ST is being formed, the spacer material layer (SM of <FIG>) formed on the upper surfaces of the first and second dummy capping patterns DC1 and DC2 and a portion of each of the first and second dummy capping patterns DC1 and DC2 may be removed. The spacer material layer (SM of <FIG>) remaining on sidewalls of each of the first and second dummy capping patterns DC1 and DC2 and the first and second dummy gates DG1 and DG2 may be referred to as a gate spacer <NUM>. After the source/drain trench ST is formed, the second semiconductor layers (<NUM> of <FIG>) remaining below the first dummy gate DG1 may be referred to as a plurality of first nanosheets NW1. In addition, after the source/drain trench ST is formed, the second semiconductor layers (<NUM> of <FIG>) remaining below the second dummy gate DG2 may be referred to as a plurality of second nanosheets NW2.

Referring to <FIG> and <FIG>, a source/drain region SD may be formed inside the source/drain trench ST. For example, an upper surface of the source/drain region SD may be formed to be higher than an upper surface of the uppermost nanosheet of the plurality of first nanosheets NW1, but embodiments are not limited thereto.

Referring to <FIG>, a first interlayer insulating layer <NUM> may be formed to cover sidewalls and upper surface of the source/drain region SD, the gate spacer <NUM>, and each of the first and second dummy capping patterns (DC1 and DC2 of <FIG>). The upper surfaces of the first and second dummy gates (DG1 and DG2 of <FIG>) may be exposed through a planarization process. Each of the first and second dummy gates (DG1 and DG2 of <FIG>), the pad oxide layer (<NUM> of <FIG>) and the first semiconductor layer (<NUM> of <FIG>) may be removed. A portion from which the first dummy gate (DG1 of <FIG>) is removed may be referred to as a first gate trench GT1. In addition, a portion from which the second dummy gate (DG2 of <FIG>) is removed may be referred to as a second gate trench GT2.

Referring to <FIG> and <FIG>, a gate insulating layer <NUM> may be formed at the portion from which each of the first and second dummy gates (DG1 and DG2 of <FIG>), the pad oxide layer (<NUM> of <FIG>) and the first semiconductor layer (<NUM> of <FIG>) is removed. For example, the gate insulating layer <NUM> may be formed to be conformal.

A first gate electrode G1 may be formed on the gate insulating layer <NUM> at the portion from which each of the first dummy gate (DG1 of <FIG>), the pad oxide layer (<NUM> of <FIG>) and the sacrificial layer (<NUM> of <FIG>) is removed. The first gate electrode G1 may surround the plurality of first nanosheets NW1. In addition, a second gate electrode G2 may be formed on the gate insulating layer <NUM> at the portion from which each of the second dummy gate (DG2 of <FIG>), the pad oxide layer (<NUM> of <FIG>) and the first semiconductor layer (<NUM> of <FIG>) is removed. The second gate electrode G2 may surround the plurality of second nanosheets NW2.

A portion of an upper portion of each of the gate spacer <NUM>, the gate insulating layer <NUM>, the first gate electrode G1 and the second gate electrode G2 may be etched. A capping pattern <NUM> may be formed at the portion from which a portion of the upper portion of each of the gate spacer <NUM>, the gate insulating layer <NUM>, the first gate electrode G1 and the second gate electrode G2 is etched. For example, an upper surface of the capping pattern <NUM> may be formed on the same plane as an upper surface of the first interlayer insulating layer <NUM>, but embodiments are not limited thereto.

Referring to <FIG>, a through via trench 160T, which extends into the second substrate <NUM> by passing through the first interlayer insulating layer <NUM>, the field insulating layer <NUM>, the first substrate <NUM> and the sacrificial layer <NUM> in the vertical direction DR3, may be formed. For example, the through via trench 160T may be spaced apart from the source/drain region SD in the second horizontal direction DR2. Also, the through via trench 160T may be formed between the first gate electrode G1 and the second gate electrode G2.

Referring to <FIG>, a portion of the sacrificial layer <NUM>, which is exposed to the through via trench 160T, may be etched. A portion of the sacrificial layer <NUM> may be etched through a wet etching process. Through this etching process, a first recess R1 and a second recess R2 may be formed inside the sacrificial layer <NUM> adjacent to the through via trench 160T.

Referring to <FIG>, a through via insulating layer <NUM> may be formed along sidewalls and a bottom surface of the through via trench 160T. In addition, the through via insulating layer <NUM> may fill the inside of each of the first recess R1 and the second recess R2. For example, the through via insulating layer <NUM> may be formed to be conformal. In this case, a portion of the through via insulating layer <NUM> formed along the sidewalls and the bottom surface of the through via trench 160T may be referred to as a first portion 165_1 of the through via insulating layer <NUM>. Also, a portion of the through via insulating layer <NUM> formed inside each of the first recess R1 and the second recess R2 may be referred to as a second portion 165_2 of the through via insulating layer <NUM>.

A through via <NUM>, which includes a through via barrier layer <NUM> and a through via filling layer <NUM>, may be formed on the through via insulating layer <NUM> inside the through via trench 160T. For example, the through via barrier layer <NUM> may be formed on the through via insulating layer <NUM> inside the through via trench 160T. For example, the through via barrier layer <NUM> may be formed to be conformal. The through via filling layer <NUM> may be formed on the through via barrier layer <NUM> inside the through via trench 160T. The through via filling layer <NUM> may fill the inside of the through via trench 160T.

Referring to <FIG>, a first gate contact CB1 and a second gate contact CB2, which are respectively connected to the first gate electrode G1 and the second gate electrode G2, may be formed by passing through the capping pattern <NUM> in the vertical direction DR3. In addition, a source/drain contact CA connected to the source/drain region SD may be formed by passing through the first interlayer insulating layer <NUM> in the vertical direction DR3. A silicide layer <NUM> may be formed between the source/drain region SD and the source/drain contact CA.

For example, the source/drain contact CA may be also formed at a portion from which a portion of each sidewall of the through via <NUM> and the through via insulating layer <NUM> is etched. For this reason, the source/drain contact CA may be in contact with the through via <NUM>. Also, the source/drain contact CA may overlap the through via <NUM> in the vertical direction DR3.

Referring to <FIG>, an etch stop layer <NUM> and a second interlayer insulating layer <NUM> may be sequentially formed on an upper surface of each of the first interlayer insulating layer <NUM>, the capping pattern <NUM>, the first and second gate contacts CB1 and CB2, the source/drain contact CA and the through via <NUM>. A first via V1 connected to each of the first gate contact CB1 and the second gate contact CB2 may be formed by passing through the second interlayer insulating layer <NUM> and the etch stop layer <NUM> in the vertical direction DR3. In addition, a second via V2 connected to the source/drain contact CA may be formed by passing through the second interlayer insulating layer <NUM> and the etch stop layer <NUM> in the vertical direction DR3.

A third interlayer insulating layer <NUM> may be formed on an upper surface of each of the second interlayer insulating layer <NUM>, the first via V1 and the second via V2. First to third upper wiring layers <NUM>, <NUM> and <NUM> may be formed inside the third interlayer insulating layer <NUM>. For example, the first to third upper wiring layers <NUM>, <NUM> and <NUM> may be sequentially spaced apart from one another in the first horizontal direction DR1. For example, the first to third upper wiring layers <NUM>, <NUM> and <NUM> may extend in the second horizontal direction DR2.

The first upper wiring layer <NUM> may be connected to the first via V1 on the first gate contact CB1. The second upper wiring layer <NUM> may be connected to the second via V2 on the source/drain contact CA. The third upper wiring layer <NUM> may be connected to the first via V1 on the second gate contact CB2.

Referring to <FIG>, after the manufacturing process shown in <FIG> is performed, upper and lower portions may be inverted. In a state that the upper and lower portions are inverted, a lower wiring trench 130T may be formed inside the second substrate <NUM>. The lower wiring trench 130T may be formed inside the second substrate <NUM> overlapped with the second portion 165_2 of the through via insulating layer <NUM> in the vertical direction DR3. The through via insulating layer <NUM> may be exposed through the lower wiring trench 130T.

Referring to <FIG>, a lower wiring insulating layer <NUM> may be formed inside the lower wiring trench 130T and on the exposed surface of the second substrate <NUM>. For example, the lower wiring insulating layer <NUM> may be formed to be conformal.

Referring to <FIG>, for example, a portion of the lower wiring insulating layer <NUM> may be removed by an etch-back etching process. For example, the lower wiring insulating layer <NUM> formed on the uppermost surface of the first portion 165_1 of the through via insulating layer <NUM> and the upper surface of the second portion 165_2 of the through via insulating layer <NUM> may be removed through the etch-back etching process. For example, a portion of the second portion 165_2 of the through via insulating layer <NUM> may be also removed. However, for example, a portion of the lower wiring insulating layer <NUM> formed on the first portion 165_1 of the through via insulating layer <NUM> may remain without being etched, but embodiments are not limited thereto. In addition, the lower wiring insulating layer <NUM> formed on the surface of the second substrate <NUM> adjacent to the lower wiring trench 130T may be removed through the etch-back etching process.

Referring to <FIG>, a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM> may be sequentially formed inside the lower wiring trench 130T. Therefore, the lower wiring layer <NUM> may be formed inside the lower wiring trench 130T. After the manufacturing process is performed, the semiconductor device shown in <FIG> may be manufactured by inversion of the upper and lower portions.

Hereinafter, a semiconductor device according to some other embodiments will be described with reference to <FIG> and <FIG>. The following description will be based on differences from the semiconductor device shown in <FIG>.

<FIG> is a cross-sectional view illustrating a semiconductor device according to some other embodiments. <FIG> is an enlarged view illustrating a region S2 of <FIG>.

Referring to <FIG> and <FIG>, in the semiconductor device according to some other embodiments, a lower wiring layer <NUM> may be disposed inside a lower interlayer insulating layer <NUM>. The lower interlayer insulating layer <NUM> may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material.

For example, the lower interlayer insulating layer <NUM> may be disposed on the lower surface 110b of the sacrificial layer <NUM>. The lower interlayer insulating layer <NUM> may be in contact with the lower surface 110b of the sacrificial layer <NUM>. A lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be in contact with the lower interlayer insulating layer <NUM> disposed on a first sidewall 230Ts1 of a lower wiring trench 230T. In addition, the lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be in contact with the lower interlayer insulating layer <NUM> disposed on a second sidewall 230Ts2 of the lower wiring trench 230T. For example, a width W22 of the through via trench 160T in the second horizontal direction DR2, which is adjacent to the second portion 165_2 of the through via insulating layer <NUM>, may be smaller than the width W1 of the second portion 165_2 of the through via insulating layer <NUM> in the second horizontal direction DR2.

For example, at least a portion of the lower wiring layer <NUM> may be disposed inside the second portion 165_2 of the through via insulating layer <NUM>. An uppermost surface 230a of the lower wiring layer <NUM> may be in contact with the second portion 165_2 of the through via insulating layer <NUM>. Also, the lower wiring layer <NUM> may be in contact with each of the lowermost surface of the first portion 165_1 of the through via insulating layer <NUM> and the lowermost surface of the through via <NUM>. For example, the lower wiring layer <NUM> may be in contact with the through via barrier layer <NUM> forming the bottom surface of the through via <NUM>.

For example, the uppermost surface 230a of the lower wiring layer <NUM> may be formed to be lower than the upper surface of the second portion 165_2 of the through via insulating layer <NUM>. That is, the uppermost surface 230a of the lower wiring layer <NUM> may be formed to be lower than the upper surface 110a of the sacrificial layer <NUM>. In addition, the uppermost surface 230a of the lower wiring layer <NUM> may be formed to be higher than the lower surface of the second portion 165_2 of the through via insulating layer <NUM>. That is, the uppermost surface 230a of the lower wiring layer <NUM> may be formed to be lower than the lower surface 110b of the sacrificial layer <NUM>.

For example, the lower wiring layer <NUM> may include a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM>. The lower wiring barrier layer <NUM> may be disposed along sidewalls and upper surface of the lower wiring trench 230T. For example, the lower wiring barrier layer <NUM> may be disposed to be conformal. The lower wiring barrier layer <NUM> may be in contact with the lower interlayer insulating layer <NUM>. The lower wiring filling layer <NUM> may be disposed on the lower wiring barrier layer <NUM> inside the lower wiring trench 230T. The lower wiring filling layer <NUM> may fill the inside of the lower wiring trench 230T on the lower wiring barrier layer <NUM>.

Hereinafter, a method of manufacturing the semiconductor device shown in <FIG> and <FIG> will be described with reference to <FIG>. The following description will be based on differences from the method of manufacturing a semiconductor device, which is shown in <FIG>.

Referring to <FIG>, after the manufacturing process shown in <FIG> is performed, upper and lower portions may be inverted. In a state that the upper and lower portions are inverted, the second substrate (<NUM> of <FIG>) may be removed. Therefore, each of the sacrificial layer <NUM> and the through via insulating layer <NUM> may be exposed.

Referring to <FIG>, a lower interlayer insulating layer <NUM> may be formed to cover the exposed sacrificial layer <NUM> and the exposed through via insulating layer <NUM>.

Referring to <FIG>, a lower wiring trench 230T may be formed inside the lower interlayer insulating layer <NUM>. The lower wiring trench 230T may be formed inside the lower interlayer insulating layer <NUM> overlapped with the second portion 165_2 of the through via insulating layer <NUM> in the vertical direction DR3. The through via insulating layer <NUM> may be exposed through the lower wiring trench 230T.

Referring to <FIG>, for example, a portion of the through via insulating layer <NUM> may be removed by an etch-back etching process. For example, the through via insulating layer <NUM> formed on the through via <NUM> may be removed through the etch-back etching process, so that the through via barrier layer <NUM> may be exposed. For example, the second portion 165_2 of the through via insulating layer <NUM> may be also removed.

Referring to <FIG>, a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM> may be sequentially formed inside the lower wiring trench 230T. Therefore, the lower wiring layer <NUM> may be formed inside the lower wiring trench 230T. After the manufacturing process is performed, the semiconductor device shown in <FIG> and <FIG> may be manufactured by inversion of the upper and lower portions.

<FIG> is a cross-sectional view illustrating a semiconductor device according to some other embodiments. <FIG> is an enlarged view illustrating a region S3 of <FIG>.

For example, the lower interlayer insulating layer <NUM> may be disposed on the lower surface 110b of the sacrificial layer <NUM>. The lower interlayer insulating layer <NUM> may be in contact with the lower surface 110b of the sacrificial layer <NUM>. A lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be in contact with the lower interlayer insulating layer <NUM> disposed on a first sidewall 330Ts1 of a lower wiring trench 330T. In addition, the lower surface of the second portion 165_2 of the through via insulating layer <NUM> may be in contact with the lower interlayer insulating layer <NUM> disposed on a second sidewall 330Ts2 of the lower wiring trench 330T. For example, a width W32 of the through via trench 160T in the second horizontal direction DR2, which is adjacent to the second portion 165_2 of the through via insulating layer <NUM>, may be smaller than the width W1 of the second portion 165_2 of the through via insulating layer <NUM> in the second horizontal direction DR2.

For example, an uppermost surface 330a of the lower wiring layer <NUM> may be in contact with the second portion 165_2 of the through via insulating layer <NUM>. The uppermost surface 330a of the lower wiring layer <NUM> may be formed on the same plane as the upper surface of the lower interlayer insulating layer <NUM>. Also, the lower wiring layer <NUM> may be in contact with each of the lowermost surface of the first portion 165_1 of the through via insulating layer <NUM> and the lowermost surface of the through via <NUM>. For example, the lower wiring layer <NUM> may be in contact with each of the through via barrier layer <NUM> and the through via filling layer <NUM>.

For example, the lower wiring layer <NUM> may include a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM>. The lower wiring barrier layer <NUM> may be disposed along sidewalls and upper surface of the lower wiring trench 330T. For example, the lower wiring barrier layer <NUM> may be disposed to be conformal. The lower wiring barrier layer <NUM> may be in contact with the lower interlayer insulating layer <NUM>. The lower wiring filling layer <NUM> may be disposed on the lower wiring barrier layer <NUM> inside the lower wiring trench 330T. The lower wiring filling layer <NUM> may fill the inside of the lower wiring trench 330T on the lower wiring barrier layer <NUM>.

<FIG> are views illustrating intermediate operations of a method of manufacturing a semiconductor device shown in <FIG> and <FIG>.

Referring to <FIG>, a portion of the lower interlayer insulating layer <NUM> and a portion of the through via insulating layer <NUM> may be etched by a planarization process. For example, the through via barrier layer <NUM> formed on the through via filling layer <NUM> may be also etched. Therefore, the uppermost surface of the through via insulating layer <NUM>, the uppermost surface of the through via barrier layer <NUM> and the uppermost surface of the through via filling layer <NUM> may be exposed, respectively. For example, a portion of the lower interlayer insulating layer <NUM> may remain on the second portion 165_2 of the through via insulating layer <NUM> and the sacrificial layer <NUM>.

Referring to <FIG>, a lower interlayer insulating layer <NUM> may be additionally formed on the uppermost surface of the through via insulating layer <NUM>, the uppermost surface of the through via barrier layer <NUM>, the uppermost surface of the through via filling layer <NUM>, and the remaining lower interlayer insulating layer <NUM>.

Referring to <FIG>, a lower wiring trench 330T may be formed inside the lower interlayer insulating layer <NUM>. The lower wiring trench 330T may be formed inside the lower interlayer insulating layer <NUM> overlapped with the second portion 165_2 of the through via insulating layer <NUM> in the vertical direction DR3. The through via insulating layer <NUM>, the uppermost surface of the through via barrier layer <NUM> and the uppermost surface of the through via filling layer <NUM> may be respectively exposed through the lower wiring trench 330T.

Referring to <FIG>, a lower wiring barrier layer <NUM> and a lower wiring filling layer <NUM> may be sequentially formed inside the lower wiring trench 330T. Therefore, the lower wiring layer <NUM> may be formed inside the lower wiring trench 330T. After the manufacturing process is performed, the semiconductor device shown in <FIG> and <FIG> may be manufactured by inversion of the upper and lower portions.

<FIG> is a schematic layout view illustrating a semiconductor device according to some other embodiments. <FIG> is a cross-sectional view taken along line D-D' of <FIG>.

Referring to <FIG> and <FIG>, in the semiconductor device according to some other embodiments, a through via <NUM> may be spaced apart from a source/drain contact CA4 in the second horizontal direction DR2.

For example, a through via trench 460T may extend into the second substrate <NUM> by passing through the first interlayer insulating layer <NUM>, the field insulating layer <NUM>, the first substrate <NUM>, and the sacrificial layer <NUM> in the vertical direction DR3. A through via insulating layer <NUM> may be disposed along sidewalls of the through via trench 460T. That is, a first portion 465_1 of the through via insulating layer <NUM> may be disposed along the sidewalls of the through via trench 460T.

For example, the through via <NUM> may be disposed on the through via insulating layer <NUM> inside the through via trench 460T. The through via <NUM> may include a through via barrier layer <NUM> disposed on the through via insulating layer <NUM> and a through via filling layer <NUM> disposed on the through via barrier layer <NUM>.

For example, an upper surface of each of the through via insulating layer <NUM> and the through via <NUM> may be formed on the same plane as the upper surface of the first interlayer insulating layer <NUM>. The third via V3 may pass through the second interlayer insulating layer <NUM> and the etch stop layer <NUM> in the vertical direction DR3. The third via V3 may connect the through via <NUM> with the second upper wiring layer <NUM>.

Hereinafter, a semiconductor device according to some other embodiments will be described with reference to <FIG>. The following description will be based on differences from the semiconductor device shown in <FIG>.

<FIG> is a cross-sectional view illustrating a semiconductor device according to some other embodiments.

Referring to <FIG>, in the semiconductor device according to some other embodiments, a through via <NUM> may be spaced apart from the source/drain contact CA4 in the second horizontal direction DR2.

For example, a through via trench 560T may extend into the second substrate <NUM> by passing through the second interlayer insulating layer <NUM>, the etch stop layer <NUM>, the first interlayer insulating layer <NUM>, the field insulating layer <NUM>, the first substrate <NUM> and the sacrificial layer <NUM> in the vertical direction DR3. A through via insulating layer <NUM> may be disposed along sidewalls of the through via trench 560T. That is, a first portion 565_1 of the through via insulating layer <NUM> may be disposed along the sidewalls of the through via trench 560T.

For example, the through via <NUM> may be disposed on the through via insulating layer <NUM> inside the through via trench 560T. The through via <NUM> may include a through via barrier layer <NUM> disposed on the through via insulating layer <NUM> and a through via filling layer <NUM> disposed on the through via barrier layer <NUM>.

Claim 1:
A semiconductor device comprising:
a first substrate (<NUM>) comprising a first surface (100a) and a second surface (100b) opposite the first surface (100a);
an active pattern (<NUM>) extending in a first horizontal direction (DR1) on the first surface (100a) of the first substrate (<NUM>);
a gate electrode (G1) extending in a second horizontal direction (DR2) different from the first horizontal direction (DR1) on the active pattern (<NUM>);
a source/drain region (SD) on at least one side of the gate electrode (G1) on the active pattern (<NUM>);
a first interlayer insulating layer (<NUM>) on the source/drain region (SD);
a sacrificial layer (<NUM>) on the second surface (100b) of the first substrate (<NUM>);
a lower wiring layer (<NUM>, <NUM>, <NUM>) on a lower surface (<NUM>10b) of the sacrificial layer (<NUM>);
a through via trench (160T, 460T, 560T) extending to the lower wiring layer (<NUM>, <NUM>, <NUM>) by passing through the first interlayer insulating layer (<NUM>) and the sacrificial layer (<NUM>) in a vertical direction (DR3);
a through via (<NUM>, <NUM>, <NUM>) inside the through via trench (160T, 460T, 560T) and connected to the lower wiring layer (<NUM>, <NUM>, <NUM>);
a recess (R1, R2) inside the sacrificial layer (<NUM>) and protruding from a sidewall of the through via trench (160T, 460T, 560T) in the second horizontal direction (DR2); and
a through via insulating layer (<NUM>, <NUM>, <NUM>) comprising a first portion (165_1, 465_1, 565_1) extending along the sidewall of the through via trench (160T, 460T, 560T) and a second portion (165_2) in the recess (R1, R2),
wherein the second portion (165_2) of the through via insulating layer (<NUM>, <NUM>, <NUM>) is in contact with an uppermost surface (130a, 230a, 330a) of the lower wiring layer (<NUM>, <NUM>, <NUM>).