Patent Description:
The demand for miniaturization of form factor and increased levels of integration for high performance are driving sophisticated packaging approaches in the semiconductor industry. Die partitioning enabled by embedded multi-die interconnect bridge (EMIB) architectures allows for miniaturization of small form factor and high performance without yield issues seen with other methods. However, such packaging architectures require fine die-to-die interconnects that are susceptible to yield issues due to poor bump thickness variation (BTV) (e.g., due to warpage, limitations on assembly tools, and the like).

Alternative approaches using a patch containing a coarse node die between the fine dies and traditional organic substrates have been proposed as well. Such architectures allow for the integration of dies that are formed at different process nodes. This architecture also has several limitations as well. Particularly, the advanced node dies are attached to the lower node die at later stages of the package formation using thermal compression bonding (TCB). Accordingly, die placement accuracy is limited by the TCB toolset and by warpage. The TCB attach in later stages imposes stringent warpage limitations on the patch and drives a significantly lower TCB window. Furthermore, architecture proposed also relies on a second carrier attach after the advanced node dies are attached in order to implement mid-level interconnect (MLI) and Package Side Bumps (PSB). This leads to additional yield losses.

Document <CIT> describes a stacked integrated circuit structure.

Described herein are multi-die electronic packages with first dies and a second die over the first dies and methods of forming such electronic packages, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, multi-die packages provide the ability to continue scaling to smaller form factors while also obtaining advanced performance. However, current architectures suffer from assembly issues that negatively impact yield. Accordingly, embodiments disclosed herein include multi-die packages that are assembled with a process flow that minimizes warpage and alignment issues.

Particularly, embodiments disclosed herein include a plurality of first dies that are at an advanced process node and one or more second dies at a lower process node. In an embodiment, the first dies are placed into the package at the initial stages of package assembly. The early placing of the first dies has several advantages. For one, the placement process may be implemented with a die mounter instead of a thermal compression bonding (TCB) tool. Die mounters have a placement accuracy that is an order of magnitude accurate than a TCB tool. Additionally, there is less warpage during early stage placement of the first dies.

In an embodiment, the attachment of the lower node second die to the first dies also has a larger TCB window. The TCB window is improved since the package is still attached to the first dies on a dimensionally stable (e.g., glass) carrier in place which results in low warpage. Additionally, embodiments allow for mid-level interconnects (MLI) and PSB formation before the carrier is removed. Accordingly, additional carriers otherwise needed for the formation of such features is avoided.

Referring now to <FIG>, a cross-sectional illustration of a multi-die electronic package <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic package <NUM> may comprise a mold layer <NUM> with a plurality of dies embedded in the mold layer. For example, a plurality of first dies <NUM> and a second die <NUM> may be embedded in the mold layer <NUM>. In an embodiment, the mold layer <NUM> may comprise a first surface <NUM> and a second surface <NUM> opposite from the first surface <NUM>. The mold layer <NUM> may comprise any suitable material for electronic packaging, such as epoxy or the like.

In an embodiment, a plurality of first dies <NUM> may be embedded in the mold layer <NUM> such that a surface <NUM> of the first dies <NUM> is substantially coplanar with the first surface <NUM> of the mold layer <NUM>. In an embodiment, the surface <NUM> may be referred to as a backside surface of the first dies <NUM>. Since the backside surface <NUM> is exposed, thermal management of the electronic package <NUM> is improved. In some embodiments, a heat sink or other thermal solution may be attached to the backside surface <NUM> of the first dies <NUM>.

In an embodiment, a plurality of high speed input/out HSIO dies <NUM> may also be embedded in the mold layer <NUM>. The HSIO dies <NUM> may be substantially coplanar with the first dies <NUM>. That is, a backside surface <NUM> of the HSIO dies <NUM> may be substantially coplanar with the first surface <NUM> of the mold layer <NUM> and the backside surface <NUM> of the first dies <NUM>.

In an embodiment, the plurality of first dies <NUM> may be electrically coupled to a second die <NUM> that is embedded in the mold layer <NUM>. In an embodiment, the second die <NUM> is positioned between an active surface <NUM> of the first dies <NUM> and the second surface <NUM> of the mold layer <NUM>. The second die <NUM> may have an active surface <NUM> and a backside surface <NUM>. In an embodiment, the second die <NUM> and the first dies <NUM> are arranged in a face-to-face configuration. That is, the active surface <NUM> of the second die <NUM> faces the active surfaces <NUM> of the first dies <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second die <NUM> may be fabricated at a second process node that is less advanced than the first process node.

In an embodiment, the first dies <NUM> may be electrically coupled to the second die <NUM> with first level interconnects (FLIs) <NUM>. For example, pads <NUM> of the first dies <NUM> may be electrically coupled to pads <NUM> of the second die <NUM> by FLIs <NUM>, such as controlled collapse chip connection (C4) bumps, or the like. In an embodiment, the pads <NUM> of the second die <NUM> and the FLIs <NUM> may be surrounded by an underfill material <NUM>, and the pads <NUM> of the first die <NUM> may be surrounded by the mold layer <NUM>.

In a particular embodiment, the first dies <NUM> may be interconnected to each other through the second die <NUM>. That is, the second die <NUM> may function as a patch to provide interconnections between each of the first dies <NUM>. In some embodiments, the first dies <NUM> may all be substantially similar to each other. In other embodiments, the first dies <NUM> may comprise different functionalities. In the illustrated embodiment, four first dies <NUM> are shown. However, it is to be appreciated that an array of any number of first dies <NUM> (e.g., two or more) may be used in an electronic package <NUM>.

In an embodiment, the HSIO dies <NUM> may also be electrically coupled to the second die <NUM>. For example, the HSIO dies <NUM> may be electrically coupled to pads <NUM> on the second die <NUM> by FLIs <NUM> in substantially the same manner the first dies <NUM> are connected to the second die <NUM>. In an embodiment, the second die <NUM> may provide interconnections between the first dies <NUM> and the HSIO dies <NUM>.

In an embodiment, a plurality of redistribution layers (RDLs) comprising conductive traces, pads <NUM>, and vias <NUM> may be embedded in the mold layer <NUM>. The RDLs may electrically couple surfaces of the first dies <NUM>, the second die <NUM>, and the HSIO dies <NUM> to mid-level interconnects (MLIs) <NUM> over the second surface <NUM> of the mold layer <NUM>. In an embodiment, the MI,Is <NUM> may be positioned in openings through a solder resist <NUM>, as is known in the art.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> is shown, in accordance with an additional embodiment. In an embodiment, the electronic package <NUM> may be substantially similar to the electronic package <NUM> described above with respect to <FIG>, with the exception that a plurality of second dies <NUM> are included. In the illustrated embodiment, two second dies <NUM>A and <NUM>B are shown. However, it is to be appreciated that an array of any number of second dies <NUM> (e.g., two or more) may be included in electronic package <NUM>.

In an embodiment, the second dies <NUM> may be electrically coupled together with one or more bridges <NUM>. The bridge <NUM> may be an embedded multi-die interconnect bridge (EMIB) or the like. For example, the bridge <NUM> may include pads <NUM> with fine pitch that is suitable for connecting to pads <NUM> on the backside surface <NUM> of the second dies <NUM>. For example, FLIs <NUM> may electrically couple pads <NUM> to pads <NUM>. In an embodiment, the pads <NUM> and FLIs <NUM> may be surrounded by an underfill material <NUM>, and the pads <NUM> on the backside surface <NUM> of the second dies <NUM> may be surrounded by the mold layer <NUM>.

The interconnection of an array of second dies <NUM> with one or more bridges <NUM> provides a die tiling architecture. That is, the plurality of second dies <NUM> may function as a single die. This may be particularly beneficial when the combined area of the second dies exceeds the reticle limit of the process node used to fabricate the second dies <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic package <NUM> may comprise a mold layer <NUM> with a plurality of dies embedded in the mold layer. For example, a plurality of first dies <NUM> and a second die <NUM> may be embedded in the mold layer <NUM>. While the mold layer <NUM> is shown as being comprised of discrete layers, it is to be appreciated that no discernable boundary may be present between the different portions of the mold layer <NUM>. In an embodiment, the mold layer <NUM> may comprise a first surface <NUM> and a second surface <NUM> opposite from the first surface <NUM>. The mold layer <NUM> may comprise any suitable material for electronic packaging, such as epoxy or the like.

In an embodiment, a plurality of first dies <NUM> may be embedded in the mold layer <NUM>. In contrast to the electronic package <NUM> described above, a surface <NUM> of the first dies <NUM> may be covered by the mold layer <NUM>. In an embodiment, the surface <NUM> may be referred to as a backside surface of the first dies <NUM>.

In an embodiment, a plurality of HSIO dies <NUM> may also be embedded in the mold layer <NUM>. The HSIO dies <NUM> may be substantially coplanar with the first surface <NUM> of the mold layer <NUM>. That is, a backside surface <NUM> of the HSIO dies <NUM> may be substantially coplanar with the first surface <NUM> of the mold layer <NUM>. In an embodiment, a thickness T<NUM> of the first dies <NUM> may be different than a thickness T<NUM> of the HSIO dies <NUM>. For example, the thickness T<NUM> of the first dies <NUM> may be less than the thickness T<NUM> of the HSIO dies <NUM>. As shown in <FIG>, the backside surfaces <NUM> of HSIO dies <NUM> are substantially coplanar with the surface <NUM> of mold layer <NUM>. However, it is to be appreciated that the mold layer <NUM> may also completely embed the HSIO dies <NUM> so that backside surface <NUM> is covered by the mold layer <NUM>.

In an embodiment, the plurality of first dies <NUM> may be electrically coupled to a second die <NUM> that is embedded in the mold layer <NUM>. In an embodiment, the second die <NUM> is positioned between an active surface <NUM> of the first dies <NUM> and the second surface <NUM> of the mold layer <NUM>. The second die <NUM> may have an active surface <NUM> and a backside surface <NUM>. In an embodiment, the second die <NUM> and the first dies <NUM> are arranged in a face-to-face configuration. That is, the active surface <NUM> of the second die <NUM> faces the active surfaces <NUM> of the first dies <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second die <NUM> may be fabricated at a second process node that is less advanced than the first process node. In an embodiment, a solder resist layer <NUM> may be located between the first dies <NUM> and the second die <NUM>.

In an embodiment, the first dies <NUM> may be electrically coupled to the second die <NUM> with first level interconnects (FLIs) <NUM> and a via <NUM> through the solder resist layer <NUM>. For example, pads <NUM> of the first dies <NUM> may be electrically coupled to the vias <NUM> by FLIs <NUM>. The opposite surface of the vias <NUM> may be electrically coupled to pads <NUM> of the second die <NUM> by FLIs <NUM> as well. In an embodiment, the pads <NUM> of the second die <NUM> and the FLIs <NUM> between the vias <NUM> and the second die <NUM> may be surrounded by an underfill material <NUM>. In an embodiment, the pads <NUM> of the first die <NUM> and the FLIs <NUM> between the first dies <NUM> may be surrounded by a different underfill material <NUM>.

In an embodiment, the HSIO dies <NUM> may also be electrically coupled to the second die <NUM>. For example, the HSIO dies <NUM> may be electrically coupled to pads <NUM> on the second die <NUM> by FLIs <NUM> and vias <NUM> through the solder resist layer <NUM> in substantially the same manner the first dies <NUM> are connected to the second die <NUM>. In an embodiment, the second die <NUM> may provide interconnections between the first dies <NUM> and the HSIO dies <NUM>.

In an embodiment, the second dies <NUM> may be electrically coupled together with one or more bridges <NUM>. The bridge <NUM> may be an EMIB or the like. For example, the bridge <NUM> may include pads <NUM> with fine pitch that is suitable for connecting to pads <NUM> on the backside surface <NUM> of the second dies <NUM>. For example, FLIs <NUM> may electrically couple pads <NUM> to pads <NUM>. In an embodiment, the pads <NUM> and FLIs <NUM> may be surrounded by an underfill material <NUM>, and the pads <NUM> on the backside surface <NUM> of the second dies <NUM> may be surrounded by the mold layer <NUM>.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process for fabricating an electronic package <NUM> similar to the electronic package <NUM> described in <FIG> is shown, in accordance with an embodiment. As will be apparent, the process includes mounting the first dies <NUM> early in the assembly process in order to provide improved alignment that is not susceptible to variations arising from warpage.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> after placement of the first dies <NUM> is shown, in accordance with an embodiment. In an embodiment, the first dies <NUM> may be attached to a release layer <NUM> over a carrier <NUM>. The carrier <NUM> may be a dimensionally stable material that is not susceptible to significant warpages. For example, the carrier <NUM> may be a glass carrier.

In an embodiment, the first dies <NUM> may be mounted to the release layer with a die mounter tool. The use of a die mounter tool to place the first dies <NUM> provides improved placement accuracy compared to TCB tools. A die mounter tool typically has a placement precision that is an order of magnitude better than TCB tools. For example, a TCB tool typically has a precision of ± <NUM> whereas a die mounter tool has a precision of ± <NUM>.

In an embodiment, the first dies <NUM> are mounted to the release layer <NUM> with a backside surface <NUM> interfacing with the release layer <NUM>. Accordingly, an active surface <NUM> and pads <NUM> on the active surface <NUM> of the first dies <NUM> are facing away from the carrier <NUM>. In an embodiment, a plurality of HSIO dies <NUM> may also be mounted to the release layer <NUM>. A backside surface <NUM> of the HSIO dies <NUM> may interface with the release layer <NUM> with pads <NUM> facing away from the carrier <NUM>. Accordingly, the backside surfaces <NUM> of the first dies <NUM> may be substantially coplanar with backside surfaces <NUM> of the HSIO dies <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a mold layer <NUM> is disposed over the first dies <NUM>, the HSIO dies <NUM> and the carrier <NUM> is shown, in accordance with an embodiment. In an embodiment, the mold layer <NUM> may be disposed and planarized in order to expose surfaces of the pads <NUM> of the first dies <NUM> and the HSIO dies <NUM>. The mold layer <NUM> may be planarized with a grinding or polishing process, as is known in the art.

Referring now <FIG>, a cross-sectional illustration of the electronic package <NUM> after vias <NUM> are fabricated over selected pads <NUM> is shown, in accordance with an embodiment. In an embodiment, the vias <NUM> may be conductive pillars or any other suitable conductive feature for forming vias in an electronic package. In an embodiment, the vias <NUM> may be fabricated over pads <NUM> on the HSIO dies <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package after a second die <NUM> is attached to the first dies <NUM> and the HSIO dies <NUM> is shown, in accordance with an embodiment. In an embodiment, the second die <NUM> may be attached with a TCB tool. Since the TCB attach happens in the early stages of package assembly (and with the dimensionally stable carrier <NUM> still in place) the impact of warpage is minimal. Accordingly, yield loss is minimal or none.

In an embodiment, the second die <NUM> may be coupled to the first dies <NUM> and the HSIO dies <NUM> with FLIs <NUM>. For example, C4 bumps may electrically couple pads <NUM> of the first dies <NUM> and the HSIO dies <NUM> to pads <NUM> of the second die <NUM>. In an embodiment, an underfill material <NUM> may surround the FLIs <NUM> and the pads <NUM> of the second die <NUM>.

In an embodiment, the second die <NUM> may be mounted to the first dies <NUM> in a face-to-face configuration. That is, an active surface <NUM> of the second die <NUM> may face the active surface <NUM> (i.e., the surface below pads <NUM>) of the first dies <NUM>. In an embodiment, pads <NUM> may also be formed over a backside surface <NUM> of the second die <NUM>. The pads <NUM> over the backside surface <NUM> may be pads for through substrate vias (TSVs) (not shown) that allow for electrical connections to pass through the second die <NUM> from the active surface <NUM> to the backside surface <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second die <NUM> may be fabricated at a second process node that is less advanced than the first process node.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a mold layer <NUM> is disposed over and around the second die <NUM> and the vias <NUM> is shown, in accordance with an embodiment. In an embodiment, the mold layer <NUM> may be planarized (e.g., with polishing or grinding) to expose surfaces of the pads <NUM> and the vias <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after pads <NUM> and vias <NUM> are formed is shown, in accordance with an embodiment. In an embodiment, the pads <NUM> and the vias <NUM> may be for a redistribution layer (RDL) formed above the second die <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after additional RDLs are formed is shown, in accordance with an embodiment. In an embodiment, the RDLs may comprise pads <NUM> and vias <NUM> embedded in a mold layer <NUM>. In an embodiment, the RDLs are fabricated with a lithographic via process (e.g., pad/via formation, molding, mold grinding/polishing to expose the vias, etc.). In other embodiments, the RDLs may be fabricated with a suitable semi-additive process (SAP) using traditional High Density Interconnect (HDI) organic build-up dielectric layers, plating, and the like. As shown in <FIG>, the mold layer <NUM> includes a plurality of distinguishable layers. However, it is to be appreciated that in some embodiments there may be no discernable boundary between layers of the mold layer <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a solder resist layer <NUM> is disposed over a surface <NUM> of the mold layer <NUM> and patterned is shown, in accordance with an embodiment. In an embodiment, the resist layer is patterned to form a plurality of openings <NUM> that expose pads <NUM> over the mold layer <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after MLIs <NUM> are disposed in the openings <NUM> is shown, in accordance with an embodiment. In an embodiment, the MI,Is <NUM> may comprise a solder or the like. Furthermore, it is to be appreciated that the MIL formation is implemented while the dimensionally stable carrier is still attached to the electronic package <NUM>. Accordingly, the attachment of an additional carrier is not needed, as is the case with previously disclosed approaches.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after the carrier <NUM> and the release layer <NUM> are removed is shown, in accordance with an embodiment. In an embodiment, any release layer residue may be removed with typical wet or dry cleaning methods, as is known in the art. After cleaning, the package <NUM> may be singulated to have the desired size.

As shown in <FIG>, backside surfaces <NUM> of the first dies <NUM> are exposed. Accordingly, thermal management of the electronic package <NUM> is improved. In some embodiments, a thermal solution (e.g., a heat sink, a heat spreader, etc.) may be coupled to the backside surfaces <NUM> of the first dies <NUM>. In an embodiment, the backside surfaces <NUM> of the first dies <NUM> may be substantially coplanar with the backside surfaces <NUM> of the HSIO dies <NUM> and the surface <NUM> of the mold layer <NUM>.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process of forming an electronic package <NUM> similar to the electronic package <NUM> described with respect to <FIG> is shown, in accordance with an embodiment.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> after a plurality of second dies <NUM> are attached to first dies is shown, in accordance with an embodiment. In an embodiment, the incoming electronic package <NUM> may be fabricated with substantially similar processing operations described with respect to <FIG>. For example, the backside surfaces <NUM> of first dies <NUM> and backside surfaces <NUM> of HSIO dies <NUM> may be mounted to a release layer <NUM> over a dimensionally stable carrier <NUM>, and vias <NUM> may be formed over the HSIO dies <NUM>.

In an embodiment, the second dies <NUM>A and <NUM>B may be attached to the first dies <NUM> with a TCB tool. Since the TCB attach happens in the early stages of package assembly (and with the dimensionally stable carrier <NUM> still in place) the impact of warpage is minimal. Accordingly, yield loss is minimal or none.

In an embodiment, the second dies <NUM>A and <NUM>B may be coupled to the first dies <NUM> and the HSIO dies <NUM> with FLIs <NUM>. For example, C4 bumps may electrically couple pads <NUM> of the first dies <NUM> and the HSIO dies <NUM> to pads <NUM> of the second dies <NUM>. In an embodiment, an underfill material <NUM> may surround the FLIs <NUM> and the pads <NUM> of the second die <NUM>.

In an embodiment, the second dies <NUM> may be mounted to the first dies <NUM> in a face-to-face configuration. That is, an active surface <NUM> of the second dies <NUM> may face the active surface <NUM> of the first dies <NUM>. In an embodiment, pads <NUM> may also be formed over a backside surface <NUM> of the second die <NUM>. The pads <NUM> over the backside surface <NUM> may be pads for through substrate vias (TSVs) (not shown) that allow for electrical connections to pass through the second die <NUM> from the active surface <NUM> to the backside surface <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second dies <NUM> may be fabricated at a second process node that is less advanced than the first process node.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a bridge <NUM> is attached across the second dies <NUM>A and <NUM>B is shown, in accordance with an embodiment. In an embodiment, the bridge <NUM> may be an EMIB or the like that provides electrical coupling between second dies <NUM>A and <NUM>B. The interconnection of an array of second dies <NUM> with one or more bridges <NUM> provides a die tiling architecture. That is, the plurality of second dies <NUM> may function as a single die. This may be particularly beneficial when the combined area of the second dies <NUM> exceeds the reticle limit of the process node used to fabricate the second dies <NUM>.

In an embodiment, the bridge <NUM> may comprise pads <NUM> that are electrically coupled to pads <NUM> on the backside surface <NUM> of the second dies <NUM>. In an embodiment the pads <NUM> may be electrically coupled to pads <NUM> with FLIs <NUM>. The pads <NUM> and the FLIs <NUM> may be surrounded by an underfill material <NUM>. While a single bridge <NUM> is shown in <FIG>, it is to be appreciated that electronic package <NUM> may comprise a plurality of bridges <NUM> to provide connections between any number of second dies <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package after RDLs comprising pads <NUM>, vias <NUM>, and mold layers <NUM> is fabricated over the second dies <NUM> is shown, in accordance with an embodiment. In an embodiment, the RDLs may be fabricated with a lithographic via process or with standard SAP processes. In an embodiment, a solder resist <NUM> may be formed over a surface <NUM> of the mold layer <NUM>. MI,Is <NUM> may pass through the solder resist <NUM> to provide connections to pads <NUM>. Furthermore, it is to be appreciated that the MIL formation is implemented while the dimensionally stable carrier is still attached to the electronic package <NUM>. Accordingly, the attachment of an additional carrier is not needed, as is the case with previously disclosed approaches.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process to form an electronic package <NUM> similar to the electronic package <NUM> shown in <FIG> is shown, in accordance with an embodiment.

Referring now to <FIG>, a cross-sectional illustration of a first carrier <NUM> with a seed layer <NUM> is shown, in accordance with an embodiment. In an embodiment, the first carrier <NUM> may be any dimensionally stable carrier, such as glass.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a solder resist layer <NUM> with patterned openings <NUM> is disposed over the seed layer <NUM> is shown, in accordance with an embodiment. The solder resist layer <NUM> may be disposed with a lamination process, or the like.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after vias <NUM> and FLIs <NUM> are disposed in the openings <NUM> is shown, in accordance with an embodiment. In an embodiment, the vias <NUM> may be copper or the like, and the FLIs <NUM> may be solder bumps or the like.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after first dies <NUM> and HSIO dies <NUM> are mounted is shown, in accordance with an embodiment. In an embodiment, the first dies <NUM> and the HSIO dies <NUM> may be mounted to FLIs <NUM> with a TCB tool. Accordingly, pads <NUM> may be attached to the FLIs <NUM>. The pads <NUM> and FLIs <NUM> may be surrounded by an underfill material <NUM>. As shown, the first dies <NUM> may be attached with a face down configuration. That is, active surfaces <NUM> of the first dies <NUM> may face towards the first carrier <NUM> and backside surfaces <NUM> of the first dies <NUM> may face away from the first carrier <NUM>.

In an embodiment, the face down configuration provides an advantage in that thicknesses of the first dies <NUM> and the HSIO dies <NUM> need not be the same. For example, first dies <NUM> may have a first thickness T<NUM> and HSIO dies <NUM> may have a second thickness T<NUM> that is different (e.g., greater) than the first thickness T<NUM>. In an embodiment, a mold layer <NUM> may be disposed over and around the first dies <NUM> and the HSIO dies <NUM> after they have been mounted to the first carrier <NUM>. In some embodiments, the molded layer <NUM> may be recessed with a grinding or polishing process to expose the HSIO die back surface.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after the first carrier <NUM> is removed and a second carrier <NUM> is attached to an opposing surface of the electronic package <NUM>. As shown, the second carrier <NUM> may interface with the mold layer <NUM> and the solder resist <NUM> is now facing upwards away from the second carrier <NUM>. In an embodiment, the seed layer <NUM> may be patterned to form pads <NUM> over the vias <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after vias <NUM> are fabricated and a second die <NUM> is attached to the first dies <NUM> and the HSIO dies <NUM> is shown, in accordance with an embodiment. In an embodiment, the second die <NUM> may be attached with a TCB tool. Since the TCB attach happens in the early stages of package assembly (and with the dimensionally stable second carrier <NUM> still in place) the impact of warpage is minimal. Accordingly, yield loss is minimal or none.

In an embodiment, the second die <NUM> may be coupled to the first dies <NUM> and the HSIO dies <NUM> with FLIs <NUM>. For example, FLIs <NUM> may couple pads <NUM> of the second die <NUM> to the vias <NUM> through the solder resist <NUM>. In an embodiment, an underfill material <NUM> may surround the FLIs <NUM> and the pads <NUM> of the second die <NUM>.

In an embodiment, the second die <NUM> may be mounted to the first dies <NUM> in a face-to-face configuration. That is, an active surface <NUM> of the second die <NUM> may face the active surface <NUM> of the first dies <NUM>. In an embodiment, pads <NUM> may also be formed over a backside surface <NUM> of the second die <NUM>. The pads <NUM> over the backside surface <NUM> may be pads for through substrate vias (TSVs) (not shown) that allow for electrical connections to pass through the second die <NUM> from the active surface <NUM> to the backside surface <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second die <NUM> may be fabricated at a second process node that is less advanced than the first process node.

Referring now to <FIG>, a cross-sectional illustration after RDLs comprising pads <NUM> and vias <NUM> are formed and the second carrier <NUM> is removed is shown, in accordance with an embodiment. In an embodiment, the RDLs are fabricated with a lithographic via process or a SAP process, as is known in the art. As shown in <FIG>, the mold layer <NUM> includes a plurality of distinguishable layers. However, it is to be appreciated that in some embodiments there may be no discernable boundary between layers of the mold layer <NUM>.

In an embodiment a solder resist layer <NUM> is disposed over a surface <NUM> of the mold layer <NUM>. In an embodiment, the resist layer is patterned and MI,Is <NUM> may be disposed. In an embodiment, the MI,Is <NUM> may comprise a solder or the like. Furthermore, it is to be appreciated that the MLI formation is implemented while the dimensionally stable second carrier <NUM> is still attached to the electronic package <NUM>. Accordingly, the attachment of an additional carrier is not needed, as is the case with previously disclosed approaches.

In an embodiment the second carrier <NUM> is removed to expose a surface <NUM> of the mold layer <NUM>. As shown in <FIG>, backside surfaces <NUM> of the first dies <NUM> are embedded in the mold layer <NUM>. The backside surface <NUM> of the HSIO dies <NUM> are exposed in some embodiments. However, in other embodiments, the backside surface <NUM> of the HSIO dies <NUM> may also be embedded in the mold layer <NUM>.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process for forming an electronic package <NUM> similar to the electronic package <NUM> described with respect to <FIG> is shown, in accordance with an embodiment.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> after a plurality of second dies <NUM> are coupled to first dies <NUM> is shown, in accordance with an embodiment. In an embodiment, the incoming electronic package <NUM> may be fabricated with substantially similar processing operations described with respect to <FIG>. For example, the backside surfaces <NUM> of first dies <NUM> and backside surfaces <NUM> of HSIO dies <NUM> may be facing a second carrier <NUM>, and vias <NUM> may be formed over the HSIO dies <NUM>. Additionally, a solder resist <NUM> with vias <NUM> may be positioned over the first dies <NUM> and the HSIO dies <NUM>.

In an embodiment, the second dies <NUM>A and <NUM>B may be attached to the first dies <NUM> with a TCB tool. Since the TCB attach happens in the early stages of package assembly (and with the dimensionally stable second carrier <NUM> still in place) the impact of warpage is minimal. Accordingly, yield loss is minimal or none.

In an embodiment, the second dies <NUM>A and <NUM>B may be coupled to the first dies <NUM> and the HSIO dies <NUM> with FLIs <NUM>. For example, FLIs <NUM> may couple pads <NUM> of the second dies <NUM> to the vias <NUM> through the solder resist <NUM>. In an embodiment, an underfill material <NUM> may surround the FLIs <NUM> and the pads <NUM> of the second die <NUM>.

In an embodiment, the second dies <NUM> may be mounted to the first dies <NUM> in a face-to-face configuration. That is, an active surface <NUM> of the second dies <NUM> may face the active surface <NUM> of the first dies <NUM>. In an embodiment, pads <NUM> may also be formed over backside surfaces <NUM> of the second dies <NUM>. The pads <NUM> over the backside surface <NUM> may be pads for through substrate vias (TSVs) (not shown) that allow for electrical connections to pass through the second dies <NUM> from the active surface <NUM> to the backside surface <NUM>. In an embodiment, the first dies <NUM> may be fabricated at a first process node and the second dies <NUM> may be fabricated at a second process node that is less advanced than the first process node.

Referring now to <FIG>, a cross-sectional illustration of the electronic package <NUM> after a mold layer <NUM> surrounds the second dies <NUM> and a bridge <NUM> is attached across the second dies <NUM>A and <NUM>B is shown, in accordance with an embodiment. In an embodiment, the bridge <NUM> may be an EMIB or the like that provides electrical coupling between second dies <NUM>A and <NUM>B. The interconnection of an array of second dies <NUM> with one or more bridges <NUM> provides a die tiling architecture. That is, the plurality of second dies <NUM> may function as a single die. This may be particularly beneficial when the combined area of the second dies <NUM> exceeds the reticle limit of the process node used to fabricate the second dies <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic system <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic system <NUM> may comprise an electronic package <NUM> that comprises a plurality of dies. For example, the plurality of dies may comprise first dies <NUM> and second dies <NUM>. In an embodiment, the second dies <NUM> may be electrically coupled together by a bridge <NUM>, such as an EMIB. In some embodiments, the first dies <NUM> and the second dies <NUM> are oriented in a face-to-face configuration. In some embodiments, the first dies <NUM> have are fabricated at a first process node and the second dies <NUM> are fabricated at a second process node that is less advanced than the first process node. In an embodiment, the electronic package <NUM> may be any electronic package such as those disclosed in greater detail above.

In an embodiment, the electronic package <NUM> may be electrically coupled to a board <NUM>. For example, MI,Is <NUM> of the electronic package <NUM> may be electrically and mechanically coupled to pads (not shown) on the board <NUM>. While the MI,Is <NUM> are illustrated as solder bumps, it is to be appreciated that the electronic package <NUM> may be connected to the board <NUM> with any suitable interconnect architecture. The board <NUM> may be any suitable board, such as a printed circuit board (PCB) or the like.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the invention. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the invention, the integrated circuit die of the processor may be packaged in an electronic system that comprises a package substrate with first dies and second dies in a face-to-face configuration, in accordance with embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be packaged in an electronic system that comprises a package substrate with first dies and second dies in a face-to-face configuration, in accordance with embodiments described herein.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed.

Claim 1:
A multi-die electronic package, comprising:
a second die (<NUM>, <NUM>) in a first mold layer (<NUM>), the second die (<NUM>, <NUM>) comprising interconnections;
a first via in the first mold layer (<NUM>), the first via laterally adjacent to a first side of the second die (<NUM>, <NUM>), and the first via extending from a top surface of the first mold layer to a bottom surface of the first mold layer;
a second via in the first mold layer (<NUM>), the second via laterally adjacent to a second side of the second die (<NUM>, <NUM>), and the second via extending from the top surface of the first mold layer to the bottom surface of the first mold layer;
a plurality of high speed input/out dies (<NUM>, <NUM>) electrically coupled to the second die (<NUM>, <NUM>), and a third die of the plurality of high speed input/out dies (<NUM>, <NUM>) electrically coupled to the first via;
a plurality of first dies (<NUM>, <NUM>) electrically coupled to the second die (<NUM>, <NUM>), a first die of the plurality of first dies electrically coupled to the third die of the plurality of high speed input/out dies (<NUM>, <NUM>) by the interconnections of the second die (<NUM>, <NUM>); and
a second mold layer (<NUM>) between and in contact with the plurality of high speed input/out dies (<NUM>, <NUM>) and the plurality of first dies (<NUM>, <NUM>), the second mold layer (<NUM>) having a surface co-planar with pads (<NUM>) of the plurality of first dies (<NUM>, <NUM>), the second mold layer (<NUM>) between the plurality of high speed input/out dies (<NUM>, <NUM>) and the second die (<NUM>, <NUM>), and the second mold layer (<NUM>) between the plurality of first dies (<NUM>, <NUM>) and the second die (<NUM>, <NUM>).