Patent Description:
<CIT> describes a multilevel nonvolatile memory via dual polarity programming.

<CIT> describes reading phase change memories without triggering reset cell threshold devices.

<CIT> describes a non-volatile memory cell stack with dual resistive elements.

Example apparatuses are disclosed herein. An example apparatus may include a memory cell configured to store multiple bits of data that correspond to logic states of the memory cell. The apparatus may also include a first memory access line coupled to the memory cell; and a second memory access line coupled to the memory cell. At least one of the multiple bits of data may be determined by a magnitude of a current applied across the memory cell during a write pulse. At least one of the multiple bits of data may be determined by a polarity of a voltage applied across the memory cell during the write pulse.

Another example apparatus may include a memory cell with a memory element and a selector device electrically coupled to the memory element. The example apparatus may also include first and second memory access lines, each coupled to the memory cell; and first and second access line driver coupled to respective memory access lines. The first and second access line drivers are configured to provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell; and configured to provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell. The first and second access line drivers are also configured to provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell; and configured to provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell.

Example methods are disclosed herein. An example method may include selecting a voltage of a write pulse and selecting a polarity of the write pulse. The example method may further comprise applying the write pulse having the voltage and polarity across a memory cell. The write pulse may write a logic state to the memory cell. The logic state may be based, at least in part, on the voltage and polarity of the write pulse.

Another example method may include applying a read pulse having a first polarity to a memory cell. The logic state of a plurality of logic states may be written to the memory cell. The logic state may be based, at least in part, on a voltage and a polarity of a write pulse applied across the memory cell. The example method may further include sensing a current through the memory cell responsive to the read pulse and determining the logic state of the plurality of logic states, based on the current through the memory cell.

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

A memory array may include memory cells that each include a memory element and a selector device. In some embodiments, both the memory element and the selector device of a memory cell are utilized to store data. The utilization of both elements of the memory cell may allow the memory cell to store multiple bits of data. The memory cell capable of storing multiple bits of data may be referred to as a multi-level cell. Multiple bits of data may include a non-integer number of bits (e.g., <NUM>, <NUM> bits). The multiple bits of data may correspond to different logic levels (e.g., <NUM>, <NUM>, <NUM>, <NUM>). For example, two bits of data may be stored with four logic levels and <NUM> bits of data may be stored with three logic levels in the memory cell. Other combinations of logic levels and bits may be used. The logic levels may be associated with different threshold voltages (e.g., VTH) of the memory cell and/or associated with different threshold voltage properties exhibited by the memory cell. A memory cell may exhibit a threshold voltage property, for example, by having or appearing to have a particular threshold voltage. The memory cell may or may not experience a threshold event when exhibiting the threshold voltage properties.

A memory element may include a phase change material (PCM). When the PCM is in an amorphous state, the PCM may have a high resistance. This may be referred to as a reset state. When the PCM is in a crystalline or semi-crystalline state, the PCM may have a lower resistance than when in the amorphous state. This may be referred to as a set state. In some embodiments, the PCM may have multiple crystalline states that may have distinct resistance levels and correspond to different set states. The crystalline state of the PCM may depend on a magnitude of a voltage and/or current of a write pulse applied across the memory cell. The change of resistance between the states of the PCM may affect a threshold voltage of the PCM. For example, the memory element may exhibit a different threshold voltage based, at least in part, on the crystalline state of the PCM.

A selector device may be a different material than the memory element in some embodiments. In some embodiments, the selector device may be a different PCM, a chalcogenide material, and/or chalcogenide alloy. The threshold voltage exhibited by the selector device may depend on the relative voltage polarities of read and write pulses applied across the memory cell. For example, the selector device may exhibit a first threshold voltage when read if the memory cell was written to and then read with the same voltage polarity. The selector may exhibit a second threshold voltage when read if the memory cell was written to and then read with different (e.g., opposite) voltage polarities.

Threshold voltage properties of the memory element may be based on the magnitude of the voltage and/or current applied to a memory cell, and the threshold voltage properties of the selector device may be based on the voltage polarities applied to the memory cell. The threshold voltage properties of the memory element and selector device may be combined to provide a memory cell that can be programmed to exhibit one of multiple threshold voltages. These multiple threshold voltages may be used to correspond to logic levels that correspond to multiple bits of data (e.g., VTH0=<NUM>, VTH1=<NUM>, VTH2=<NUM>, VTH3=<NUM>). The multiple logic levels may allow the memory cell to store multiple bits of data. One or more of the multiple bits of data may be stored in different physical locations in the memory cell. In some embodiments, one bit of data is stored in the memory element and one bit of data is stored in the selector device. In some embodiments, for example, when the memory element has multiple crystalline states, multiple bits of data may be stored in the memory element and one bit of data may be stored in the selector device. Other distributions of data between the memory element and the selector device may be used.

A logic state may be written to the memory cell, which may correspond to one or more bits of data. A logic state may be written to the memory cell by applying voltages of different polarities at different voltage and/or current magnitudes. The memory cell may be read by applying voltages of a single polarity. The writing and reading protocols may take advantage of different threshold voltages of the memory element and selector device that result from the different magnitudes and polarities, respectively. The memory cell may require short, relatively low power pulses to read. In some embodiments, the memory element may include a chalcogenide material. In some embodiments, the selector device may include a chalcogenide material. However, the chalcogenide material of the selector device may or may not undergo a phase change during reading and/or writing. In some embodiments, the chalcogenide material may not be a phase change material.

<FIG> illustrates an apparatus that includes a memory <NUM> according to an embodiment of the present invention. The memory <NUM> includes a memory array <NUM> with a plurality of memory cells that are configured to store data. The memory cells may be accessed in the array through the use of various access lines, word lines (WLs) and/or bit lines (BLs). The memory cells may be non-volatile memory cells, such as NAND or NOR flash cells, phase change memory cells, or may generally be any type of memory cells. The memory cells of the memory array <NUM> can be arranged in a memory array architecture. For example, in one embodiment, the memory cells are arranged in a three-dimensional (3D) cross-point architecture. In other embodiments, other memory array architectures may be used, for example, a single-deck cross-point architecture, among others. The memory cells may be single level cells configured to store data for one bit of data. The memory cells may also be multi-level cells configured to store data for more than one bit of data.

An I/O bus <NUM> is connected to an I/O control circuit <NUM> that routes data signals, address information signals, and other signals between the I/O bus <NUM> and an internal data bus <NUM>, an internal address bus <NUM>, and/or an internal command bus <NUM>. An address register (not shown) may be provided address information by the I/O control circuit <NUM> to be temporarily stored. In some embodiments, the I/O control circuit <NUM> may include the address register. The I/O control circuit <NUM> is coupled to a status register <NUM> through a status register bus <NUM>. Status bits stored by the status register <NUM> may be provided by the I/O control circuit <NUM> responsive to a read status command provided to the memory <NUM>. The status bits may have respective values to indicate a status condition of various aspects of the memory and its operation.

The memory <NUM> also includes a control logic <NUM> that receives a number of control signals <NUM> either externally or through the command bus <NUM> to control the operation of the memory <NUM>. The control signals <NUM> may be implemented with any appropriate interface protocol. For example, the control signals <NUM> may be pin based, as is common in dynamic random access memory and flash memory (e.g., NAND flash), or op-code based. Example control signals <NUM> include clock signals, read/write signals, clock enable signals, etc. A command register <NUM> is coupled to the internal command bus <NUM> to store information received by the I/O control circuit <NUM> and provide the information to the control logic <NUM>. The control logic <NUM> may further access a status register <NUM> through the status register bus <NUM>, for example, to update the status bits as status conditions change. The control logic <NUM> may be configured to provide internal control signals to various circuits of the memory <NUM>. For example, responsive to receiving a memory access command (e.g., read, write), the control logic <NUM> may provide internal control signals to control various memory access circuits to perform a memory access operation. The various memory access circuits are used during the memory access operation, and may generally include circuits such as decoder circuits, charge pump circuits, access line drivers, data and cache registers, I/O circuits, as well as others.

The address register provides block-row address signals to a decoder circuit <NUM> and column address signals to a decoder circuit <NUM>. The decoder circuit <NUM> and decoder circuit <NUM> may be used to select blocks of memory cells for memory operations, for example, read and write operations. The decoder circuit <NUM> and/or the decoder circuit <NUM> may include one or more access line drivers configured to provide signals to one or more of the access lines in the memory array <NUM> to perform memory operations. For example, read pulses and write pulses may be provided to the access lines for read and write operations. The access line drivers may be coupled to access lines of the memory array <NUM>. The access line drivers may drive the access lines with a voltage that is provided by voltage circuit <NUM>. The voltage circuit <NUM> may provide different voltages V1, V2,. , VN used during operation of the memory <NUM>, for example, during memory access operations. The voltages V1, V2,. , VN provided by the voltage circuit <NUM> may include voltages that are greater than a power supply voltage provided to the memory <NUM>, voltages that are less than a reference voltage (e.g., ground) provided to the memory <NUM>, as well as other voltages.

A data I/O circuit <NUM> includes one or more circuits configured to facilitate data transfer between the I/O control circuit <NUM> and the memory array <NUM> based on signals received from the control logic <NUM>. In various embodiments, the data I/O circuit <NUM> may include one or more sense amplifiers, registers, buffers, and other circuits for sensing logic states, managing data transfer between the memory array <NUM> and the I/O control circuit <NUM>. For example, during a write operation, the I/O control circuit <NUM> receives the data to be written through the I/O bus <NUM> and provides the data to the data I/O circuit <NUM> via the internal data bus <NUM>. The data I/O circuit <NUM> writes the data to the memory array <NUM> based on control signals provided by the control logic <NUM> at a location specified by the decoder circuit <NUM> and the decoder circuit <NUM>. During a read operation, the data I/O circuit reads data from the memory array <NUM> based on control signals provided by the control logic <NUM> at an address specified by the decoder circuit <NUM> and the decoder circuit <NUM>. The data I/O circuit provides the read data to the I/O control circuit via the internal data bus <NUM>. The I/O control circuit <NUM> then provides the read data on the I/O bus <NUM>.

In some embodiments, the control logic <NUM> controls circuits (e.g., access line drivers) such that during a write operation on a memory cell of the memory array <NUM>, a first voltage (e.g., 0V) may be provided to a selected word and a second voltage may be provided to a selected bit line. The memory cell may be at the intersection of the selected word line and bit line. The second voltage may be higher or lower than the voltage provided to the word line, based on the logic state to be stored at the address corresponding to the selected word line and bit line. The amplitude of the second voltage may be based on the logic state to be stored at the address corresponding to the selected word line and bit line (e.g., -6V for '<NUM>', -4V for '<NUM>', +4V for `<NUM>', and +6V for '<NUM>'). In some embodiments, during a write operation, the selected bit line may always be provided a specific voltage, and the word line may be provided a voltage higher or lower than the voltage of the bit line, based on the logic state to be stored at the address.

In some embodiments, during a read operation on a memory cell, a first voltage (e.g., 0V) may be provided to a selected word line and a second voltage (e.g., -5V, +5V) may be provided to a selected bit line. The memory cell may be at the intersection of the selected word line and bit line. The second voltage may be greater than or less than the first voltage provided to the word line, however, the second voltage may provide the same voltage polarity for every read operation. The logic state of the memory cell may be sensed by a sense amplifier coupled to the selected bit line. The sensed logic state of the memory cell may be provided to the data I/O circuit <NUM>.

<FIG> illustrates a memory array <NUM> according to an embodiment of the invention. The memory array <NUM> includes a plurality of access lines, for example, access lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM> and access lines BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>. Memory cells (not shown in <FIG>) may be at the intersections of the access lines. A plurality of individual or groups of memory cells of the memory array <NUM> are accessible through the access lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM> and access lines BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>. Data may be read from or written to the memory cells. A decoder circuit <NUM> is coupled to the plurality of access lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, with respective access line drivers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> biasing each of the respective access lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>. A decoder circuit <NUM> is coupled to the plurality of access lines BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, with respective access line drivers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> biasing each of the respective access lines BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>.

Internal control signals are provided, for example, by the control logic <NUM>, to the access line drivers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in order to bias the respective access lines BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>. Internal control signals are also provided, for example, also by the control logic <NUM>, to the access line drivers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in order to bias the respective word lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>. The control logic <NUM> may be a state machine that, upon receiving commands such as read, write, etc., determines which biasing signals need to be provided to which signal lines at which biasing levels. The biasing signals that need to be provided to the access lines WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, WL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM>, BL-<NUM> may depend on an operation that will be performed responsive to a received command.

<FIG> is a diagram illustrating a portion of an array <NUM> of memory cells according to an embodiment of the disclosure. The array <NUM> may be used to implement the memory array <NUM> of <FIG> in some embodiments. In the example illustrated in <FIG>, the array <NUM> is a cross-point array including a first number of conductive lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N, e.g., access lines, which may be referred to herein as word lines, and a second number of conductive lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M, e.g., access lines, which may be referred to herein as bit lines. A memory cell <NUM> is located at each of the intersections of the word lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and bit lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M and the memory cells <NUM> can function in a two-terminal architecture, e.g., with a particular word line <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and bit line <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M serving as the electrodes for the memory cells <NUM>.

The memory cells <NUM> can be resistance variable memory cells, e.g., RRAM cells, CBRAM cells, PCRAM cells, and/or STT-RAM cells, among other types of memory cells. The memory cell <NUM> can include a material programmable to different data states (e.g., chalcogenide). For example, the memory cell <NUM> may include a composition that may include selenium (Se), arsenic (As), germanium (Ge), silicon (Si), or combinations thereof. Other materials may also be used. For instance, the memory cell <NUM> may be written to store particular levels corresponding to particular data states responsive to applied writing voltage and/or current pulses, for instance. Embodiments are not limited to a particular material or materials. For instance, the material can be a chalcogenide formed of various doped or undoped materials. Other examples of materials that can be used to form memory elements or selector devices include binary metal oxide materials, colossal magnetoresistive materials, and/or various polymer based resistance variable materials, among others.

In operation, the memory cells <NUM> of array <NUM> can be written to by applying a voltage, e.g., a write voltage, across the memory cells <NUM> via selected word lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and bit lines <NUM>-<NUM>, <NUM>-<NUM>,. A sensing, e.g., read, operation can be used to determine the data state of a memory cell <NUM> by sensing current, for example, on a bit line <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M corresponding to the respective memory cell responsive to a particular voltage applied to the selected word line <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N to which the respective cell is coupled.

<FIG> is a diagram illustrating a portion of an array <NUM> of memory cells. The array <NUM> may be used to implement the memory array <NUM> of <FIG> in some embodiments. In the example illustrated in <FIG>, the array <NUM> is configured in a cross-point memory array architecture, e.g., a three-dimensional (3D) cross-point memory array architecture. The multi-deck cross-point memory array <NUM> includes a number of successive memory cells, e.g., <NUM>, <NUM>, <NUM> disposed between alternating, e.g., interleaved, decks of word lines, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N extending in a first direction and bit lines, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M and <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M extending in a second direction. The number of decks can be expanded in number or can be reduced in number, for example. Each of the memory cells <NUM>, <NUM> can be configured between word lines, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N and bit lines, e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M and <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-M, such that a single memory cell <NUM>, <NUM> is directly electrically coupled with and is electrically in series with its respective bit line and word line. For example, array <NUM> can include a three-dimensional matrix of individually-addressable, e.g., randomly accessible, memory cells that can be accessed for data operations, e.g., sense and write, at a granularity as small as a single storage element or multiple storage elements. In a number of embodiments, memory array <NUM> can include more or less decks, bit lines, word lines, and/or memory cells than shown in the examples in <FIG>.

<FIG> is an illustration of a portion of a memory array <NUM> according to an embodiment of the disclosure. The portion of the memory array <NUM> may be included in the memory array <NUM> of <FIG>. The memory array <NUM> may include a first access line <NUM> and a second access line <NUM>. For ease of reference, the first access line may also be referred to as a word line (WL) <NUM> and the second access line may also be referred to as a bit line (BL) <NUM>. As shown in <FIG>, the WL <NUM> extends parallel to the plane of the page, and the BL <NUM> extends into the plane of the page, perpendicular to the WL <NUM>. A memory cell <NUM> may be located at the intersection of the WL <NUM> and BL <NUM>. The memory cell <NUM> may include a selector device <NUM>. The selector device <NUM> may be coupled to WL <NUM> by a first electrode <NUM> and coupled to a second electrode <NUM>. The electrode <NUM> may couple the selector device <NUM> to a memory element <NUM> included in the memory cell <NUM>. The memory element <NUM> may be coupled to BL <NUM> by a third electrode <NUM>. The memory element <NUM> may include a chalcogenide material. In some embodiments, the chalcogenide material may be a phase change material, but other materials may be used. In some embodiments, the selector device <NUM> may also include a chalcogenide material. In some embodiments, the selector device <NUM> may include a material that does not undergo a phase change during operation. In some embodiments, the memory element <NUM> and/or selector device <NUM> may include a ternary composition that may include selenium (Se), arsenic (As), germanium (Ge), and combinations thereof. In some embodiments, the memory element <NUM> and/or selector device <NUM> may include a quaternary composition that may include silicon (Si), Se, As, Ge, and combinations thereof. Other materials may also be used.

As will be described in more detail below, voltages and/or currents may be provided to the memory cell <NUM> using the first and second access lines WL <NUM> and BL <NUM>. The first and second access lines WL <NUM> and BL <NUM> may also be used to sense a voltage and/or current of the memory cell <NUM>, as well. Voltages and/or currents may be provided to the memory cell <NUM> to write data to the memory cell, and voltages and/or currents may be sensed to read data from the memory cell <NUM>. Circuits, such as access line drivers may be coupled to the access lines WL <NUM> and BL <NUM> to provide the voltages to the memory cell <NUM>, and a sense amplifier may be coupled to the access lines WL <NUM> and/or BL <NUM> to sense a voltage and/or current of the memory cell <NUM>. Based on the voltage and/or current that is sensed, a logic value or logic values stored by the memory cell <NUM> may be determined.

The memory element <NUM> may be written to store one of at least two different logic states (e.g., '<NUM>,' '<NUM>') by a write operation. In some embodiments, the different logic states may be represented by different threshold voltages (VTH) of the memory element <NUM>. For example, a '<NUM>' logic state may be represented by a first VTH and a '<NUM>' logic state may be represented by a second VTH. The threshold voltage the memory element <NUM> exhibits may be based on a state of a phase change material (PCM) included in the memory element <NUM> (e.g., amorphous or crystalline). The state of the PCM may be based on the magnitude of a current of a write pulse applied to the memory cell <NUM> during a write operation. In some embodiments, the magnitude of the voltage may be used to adjust the magnitude of the current of the write pulse. The state of the memory element <NUM> may be determined by applying a read pulse during a read operation. The write pulse and read pulse may be applied to the memory cell <NUM> using the first and second access lines <NUM> and <NUM>.

The selector device <NUM> may be written to store one of at least two different logic states (e.g., '<NUM>,' '<NUM>') by a write operation. In some embodiments, the different logic states may be represented by different threshold voltages (VTH) of the selector device <NUM>. For example, a '<NUM>' logic state may be represented by a first VTH and a '<NUM>' logic state may be represented by a second VTH. The threshold voltage the selector device <NUM> exhibits may be based on a polarity of a write pulse applied to the memory cell <NUM> during a write operation and a polarity of a read pulse applied to the memory cell <NUM> during a read operation. The write pulse and read pulse may be applied to the memory cell <NUM> using the first and second access lines <NUM> and <NUM>.

The memory cell <NUM> may be configured as a two-terminal device between the BL <NUM> and WL <NUM> in some embodiments. A first logic state may be written to the memory cell <NUM> by applying a voltage (e.g., a write pulse) across the memory cell <NUM> in a first polarity at a first voltage. A second logic state may be written to the memory cell <NUM> by applying a voltage (e.g., a write pulse) across the memory cell <NUM> in the first polarity at a second voltage. A third logic state may be written to the memory cell <NUM> by applying a voltage (e.g., a write pulse) across the memory cell <NUM> in a second polarity, which may be opposite to the first polarity, at a third voltage. A fourth logic state may be written to the memory cell <NUM> by applying a voltage (e.g., a write pulse) across the memory cell <NUM> in the second polarity at a fourth voltage. In some embodiments, the first and third voltages may be the same magnitude. In some embodiments, the second and fourth voltages may be the same magnitude.

The memory cell <NUM> may be read by applying a voltage (e.g., a read pulse) across the memory cell <NUM> (e.g., using BL <NUM> and WL <NUM>). In some embodiments, the memory cell <NUM> is read by applying a voltage across the memory cell <NUM> in the first polarity. In other embodiments, the memory cell <NUM> is read by applying a voltage across the memory cell <NUM> in the second polarity. The memory cell <NUM> may always be read with the same polarity. When the memory cell <NUM> is read with a voltage in the same voltage polarity with which the memory cell <NUM> was written, the selector device <NUM> may exhibit a first VTH. When the memory cell <NUM> is read with a voltage in the opposite voltage polarity with which the memory cell <NUM> was written, the selector device <NUM> may exhibit a second VTH. In some embodiments, the memory element <NUM> may exhibit the same threshold voltage regardless of the polarity of the write and read pulses. In some embodiments, the threshold voltage of the memory element <NUM> may be based on the magnitude of the write pulse applied across the memory cell <NUM>. The different threshold voltages of the memory cell <NUM>, based on the threshold voltages of the memory element <NUM> and selector device <NUM>, may be used to represent different logic states.

When the memory cell <NUM> is a two-terminal device, the relative values of the voltages between the terminals determines the magnitude and the polarity of the voltage applied across the memory cell <NUM>. For example, providing a voltage of 3V to the BL <NUM> and 0V to WL <NUM> results in the same magnitude and polarity of voltage as providing a voltage of 6V at BL <NUM> and 3V at WL <NUM>. Other non-negative (e.g., 0V or greater), negative, and/or positive voltages may be provided to the memory access lines in some embodiments. As used herein, forward polarity indicates that the BL <NUM> is set at a higher voltage than the WL <NUM> and reverse polarity indicates that the BL <NUM> is set at a lower voltage than the WL <NUM>. However, the use of "forward" and "reverse" polarities is by way of example, and the embodiments of the invention are not limited to those of the particular polarity directions described herein.

<FIG> is a voltage plot <NUM> of threshold voltages for logic states of a memory cell according to an embodiment of the disclosure. In the embodiment shown in <FIG>, a memory element of the memory cell may be programmed into one of two logic states and a selector device of the memory cell may be programmed into one of two logic states to store two bits of data in the memory cell, which may correspond to a total of four logic states for the memory cell. For purposes of explaining the principles of the disclosure, the application will describe a four logic state memory cell. However, a memory cell having two, three, six, eight, or other number of logic states may be used.

The threshold voltages of the memory cell are the threshold voltages observed when the memory cell is read. The memory cell may be read using a read voltage in the same polarity each time it is read, for example, in forward polarity. VTH0 may be observed in the memory cell when the memory cell was written to at a low voltage in the same polarity as the read voltage. This may correspond to logic State<NUM>. By low voltage, it is meant a voltage appropriate to program a PCM memory element to a set state. For example, the memory cell may have been written to in a forward polarity at a low voltage and is then read in forward polarity. In some embodiments, multiple low voltage magnitudes may be used to read or write to the memory cell. For example, a first low voltage magnitude may be used to write the memory cell in a first polarity and a second low voltage magnitude may be used to write the memory cell in a second polarity in some embodiments.

Conversely, VTH1 may be observed in the memory cell when the memory cell was written to at the low voltage in the opposite polarity as the read voltage. This may correspond to logic State<NUM>. For example, the memory cell may have been written to at a low voltage in a reverse polarity and is then read in a forward polarity. In some embodiments, multiple high voltage magnitudes may be used to read or write to the memory cell. For example, a first high voltage magnitude may be used to write the memory cell in a first polarity and a second high voltage magnitude may be used to write the memory cell in a second polarity in some embodiments.

VTH2 may be observed in the memory cell when the memory cell was written to at a high voltage in the same polarity as the read voltage. This may correspond to logic State<NUM>. By high voltage, it is meant a voltage appropriate to program a PCM memory element to a reset state. For example, the memory cell may have been written to in a forward polarity at a high voltage and is then read in forward polarity.

Finally, VTH3 may be observed in the memory cell when the memory cell was written to at the high voltage in the opposite polarity as the read voltage. This may correspond to logic State<NUM>. For example, the memory cell may have been written to at a high voltage in a reverse polarity and is then read in a forward polarity.

As illustrated by <FIG>, in some embodiments, different threshold voltages may be observed for the memory cell written and read in opposite polarities in comparison to the memory cell written and read in the same polarity. These different threshold voltages may be observed even when the same or similar magnitude voltage write pulse is used. In summary, in the embodiment illustrated in <FIG>, State<NUM> is written by applying a low voltage in a first polarity. State<NUM> is written by applying the low voltage in a second polarity. State<NUM> is written by applying a high voltage in the first polarity, and State<NUM> is written by applying the high voltage in the second polarity. It is understood that different assignments of the logic states to the different threshold voltages may be used. For example, the threshold voltages assigned to State<NUM> and State<NUM> may be reversed. The magnitudes of the threshold voltages and/or differences between the threshold voltages exhibited by the memory cell may be based, at least in part, on the materials included in the memory element and/or selector device. The number of possible logic states of the memory cell may be based, at least in part, on the materials included in the memory element and/or selector device. The physical geometry of the memory element and/or selector device may affect the threshold voltage levels and/or the number of possible logic states of the memory cell.

<FIG> is a voltage plot <NUM> of four exemplary write pulses <NUM>, <NUM>, <NUM>, <NUM> according to an embodiment of the disclosure. The write pulses <NUM>, <NUM>, <NUM>, <NUM> may be used to write a logic state to a memory cell, such as memory cell <NUM> shown in <FIG>, during a write operation. The write pulses may be applied by providing a first voltage to the BL and providing a second voltage to the WL. Circuits coupled to access lines to which memory cells may be coupled may be used to provide the first voltage, for example, access line drivers included in the decoder circuits <NUM> and <NUM> of <FIG>. The circuits may be controlled by the internal control signals provided by a control logic, for example, control logic <NUM> of <FIG>. The resulting voltage applied to the memory cell is the difference between the first and second voltages. The write pulses may be the same duration as read pulses in some embodiments. In some embodiments the duration is 10ns-50ns. In some embodiments, the duration is <NUM>-100ns. In some embodiments, the duration is 1ns-<NUM>. Writing to the memory cell may take the same time as reading the memory cell in some embodiments. Although shown as square pulses in <FIG>, write pulses of other shapes may be implemented. Other suitable write pulse shapes include, but are not limited to, triangular, trapezoidal, and/or sinusoidal. In some embodiments, write pulses may include leading and/or trailing edges.

The polarity of the write pulses may be either a first polarity or a second polarity (e.g., forward or reverse). Write pulse <NUM> may apply a voltage VW3 to a memory cell in a first polarity (e.g., bit line at 6V and word line at 0V). The polarity of the write pulse <NUM> may be the same as the polarity of read pulses (not shown in <FIG>). This may write logic state State<NUM> to the memory cell shown in <FIG>. As shown in <FIG>, when write pulse <NUM> writes State<NUM> to the memory cell, the memory cell exhibits threshold voltage VTH2 when read.

Write pulse <NUM> may apply a voltage VW2 to a memory cell in the first polarity (e.g., bit line at 4V and word line at 0V). The polarity of the write pulse <NUM> may be the same as the polarity of read pulses (not shown in <FIG>). This may write logic state State<NUM> to the memory cell shown in <FIG>. As shown in <FIG>, when write pulse <NUM> writes State<NUM> to the memory cell, the memory cell exhibits threshold voltage VTH0 when read.

Write pulse <NUM> may apply a voltage VW1 to the memory cell in a second polarity (e.g., bit line at -4V and word line at 0V or bit line at 0V and word line at 4V). Write pulse <NUM> may have the opposite polarity of write pulses <NUM>, <NUM> and read pulses (not shown in <FIG>). Write pulse <NUM> may write logic state State<NUM> to the memory cell. As shown in <FIG>, when write pulse <NUM> writes State<NUM> to the memory cell, the memory cell exhibits threshold voltage VTH1 when read.

Write pulse <NUM> may apply a voltage VW0 to the memory cell in the second polarity (e.g., bit line at -6V and word line at 0V or bit line at 0V and word line at 6V). Write pulse <NUM> may have the opposite polarity of write pulses <NUM>, <NUM> and read pulses (not shown in <FIG>). Write pulse <NUM> may write logic state State<NUM> to the memory cell. As shown in <FIG>, when write pulse <NUM> writes State<NUM> to the memory cell, the memory cell exhibits threshold voltage VTH3 when read.

In some embodiments VW0 and VW3 may have the same voltage magnitude. In some embodiments, VW0 and VW3 may have different magnitudes. The magnitudes of VW0 and VW3 may be selected to completely melt a PCM or melt at least a portion of a PCM included in a memory element of a memory cell. In some embodiments VW1 and VW2 may have the same voltage magnitude. In some embodiments, VW1 and VW2 may have different magnitudes. The magnitudes of VW1 and VW2 may be selected to crystallize a PCM included in a memory element of a memory cell.

In some embodiments, two or more states, which may correspond to two or more different threshold voltages, may be associated with a same logic state of the memory cell. For example, a memory cell may have three logic states: StateA, StateB, and StateC. In this example, State<NUM> and State<NUM> shown in <FIG> may correspond to a same logic state (e.g., StateB) and both write pulses <NUM> and <NUM> shown in <FIG> may be used to write StateB to the memory cell. Other combinations of logic states may be used. In some embodiments, a memory cell with three logic states may correspond to a <NUM> bit memory cell. Two or more logic states, having different threshold voltages, corresponding to the same state may be desirable in some embodiments to provide sufficient differences between threshold voltages of different logic states. For example, when VTH1 and VTH2, as shown in <FIG>, are similar values, it may be desirable for VTH1 and VTH2 to correspond to the same logic state.

Although the write pulses shown in <FIG> are plotted and described with respect to voltage, the write pulses could be plotted and described with respect to current and be within the scope of the present disclosure. Voltage and current are proportional, and absent other factors, increasing or decreasing the current of a write pulse may have a similar effect on the operation of a memory device as increasing or decreasing the voltage of a write pulse in some embodiments.

<FIG> are voltage plots of exemplary read pulses <NUM>, <NUM>, <NUM>, respectively, according to embodiments of the disclosure. Circuits coupled to access lines to which memory cells may be coupled may be used to provide the read pulses, for example, access line drivers included in the decoder circuits <NUM> and <NUM> of <FIG>. The circuits may be controlled by the internal control signals provided by a control logic, for example, control logic <NUM> of <FIG>. A read pulse may be a voltage VR applied to the memory cell for a period of time (e.g., 10ns-50ns, 1ns-100ns, 1ns-<NUM>). In some embodiments, the read pulse may be a square pulse <NUM> as shown in <FIG>. In some embodiments, as shown in <FIG>, the read pulse may be a ramp <NUM>, that is, a linearly increasing voltage may be applied across the memory cell. In some embodiments, the read pulse may be a staircase <NUM> as shown in <FIG>, where two or more discrete voltages increasing in magnitude are applied across the memory cell at different periods of time. Read pulses of other shapes may be implemented. Other suitable read pulse shapes include, but are not limited to, triangular, trapezoidal, and/or sinusoidal. In some embodiments, read pulses may include leading and/or trailing edges. Although read pulses <NUM>, <NUM>, <NUM> are all shown as having forward polarity, the read pulses <NUM>, <NUM>, <NUM> may be implemented in reverse polarity. In some embodiments, the read pulses may always be applied with the same polarity (e.g., all read pulses exhibit forward polarity, all read pulses exhibit reverse polarity).

In some embodiments, the memory cell may be implemented using the memory cell <NUM> illustrated in <FIG>. The read pulse may be applied by providing a first voltage to a bit line (e.g., BL <NUM>) and providing a second voltage to a corresponding word line (e.g., WL <NUM>). A sense amplifier (not shown) coupled to a bit line associated with the memory cell to be read may be used to detect a current through the memory cell. The sense amplifier may be configured to sense the current through the memory cell responsive to the read operation and provide an output signal indicative of the logic state stored by the memory cell. The sense amplifier may be included in a memory that includes the memory cell. For example, the sense amplifier may be included with other read and write circuits, decoding circuits, register circuits, etc. of the memory that may be coupled to a memory array. When a read pulse is applied to a memory cell, the memory cell conducts current when the read pulse exceeds the threshold voltage of the memory cell. The sense amplifier may detect a current IS through the memory cell. When a read pulse below the threshold voltage is applied to a memory cell, the memory cell does not conduct current. The sense amplifier may detect little or no current through the memory cell. In some embodiments, a threshold current ITH may be defined for sensing the logic state stored by the memory cell. The threshold current ITH may be set above a current that may pass through the memory cell when the memory cell does not threshold in response to the read pulse, but equal to or below an expected current through the memory cell when the memory cell does threshold in response to the read pulse. That is, the threshold current ITH should be higher than a leakage current of the bit line and/or word line. When sense amplifier detects Is≥ITH, a logic state may be read from the memory cell. Other methods of detecting a current and/or a voltage across the memory cell may be used.

The threshold event may be used to determine the logic state of the memory cell in some embodiments. For example, using the ramp read pulse <NUM> shown in <FIG>, a threshold event (e.g., Is≥ITH), may be detected when the read pulse <NUM> is at a voltage (V). V may be less than or equal to VR. Based, at least in part, on the value of V when the threshold event is detected, the logic state of the memory cell may be determined. Continuing this example, if VR = 6V, VTH0 = 4V, VTH1 = <NUM>. 5V, VTH2 = <NUM>. 0V, and VTH3 = <NUM>. If V is equal to <NUM>. 0V or slightly greater than <NUM>. 0V when a threshold event is detected, it may be determined that the memory cell is in State<NUM> as shown in <FIG>. Similarly, if the read pulse is a staircase such as read pulse <NUM> in <FIG>, the voltage V of the step of the staircase when a threshold event is detected may be used to determine a logic state of the memory cell.

In some embodiments, a time from when the read pulse is applied to when the threshold event is detected (e.g., detecting a voltage or current across the memory cell) may be used to determine the logic state of the memory cell. For example, if a time to threshold a memory cell at a voltage may be known and/or a time to reach a voltage for a read pulse (e.g., a read pulse with a voltage ramp) may be known. Returning to the example of a voltage ramp read pulse, such as read pulse <NUM> shown in <FIG>, it may be known that the voltage ramp is between <NUM>-<NUM>. 1V at <NUM>-10ns, <NUM>-<NUM>. 6V at <NUM>-15ns, <NUM>-<NUM>. 1V at <NUM>-20ns, and <NUM>-6V at <NUM>-30ns. If a threshold event is detected at 8ns, the memory cell may be determined to have a VTH=4V and the logic state of the memory cell may be determined to be State<NUM>. The examples provided are for explanatory purposes and should not be interpreted to limit the disclosure to the examples given.

Although the read pulses shown in <FIG> are plotted and described with respect to voltage, the read pulses could be plotted and described with respect to current and be within the scope of the present disclosure. Voltage and current are proportional, and absent other factors, increasing or decreasing the current of a read pulse may have a similar effect on the operation of a memory device as increasing or decreasing the voltage of a write pulse in some embodiments.

A variety of writing and reading protocols may be used with a memory cell having the threshold voltage properties as described in reference to <FIG>.

<FIG> is a flow chart of a method <NUM> for writing a memory cell according to an embodiment of the disclosure. In some embodiments, the method <NUM> may be used by the memory <NUM> of <FIG> for writing logic states, which may correspond to bits in some embodiments, to a memory cell, and the memory cell may be implemented by memory cell <NUM> shown in <FIG>. For example, the control logic <NUM> may provide internal control signals to various circuits in the memory <NUM> to perform the method <NUM>. The memory cell may exhibit the threshold voltage characteristics illustrated in <FIG>. In some embodiments, a first bit may be stored in the memory element <NUM>, and a second bit may be stored in the selector device <NUM>. At Step <NUM>, a voltage is selected for a write pulse. A voltage magnitude of a write pulse may be selected based on a first bit to be written to the memory element <NUM>. For example, a high magnitude may be selected to write '<NUM>' and a low magnitude may be selected to write '<NUM>' to the memory element <NUM>. At Step <NUM>, a polarity is selected for the write pulse. A polarity of the write pulse may be selected based on a second bit to be written to the selector device <NUM>. For example, a forward polarity may be selected to write '<NUM>' and a reverse polarity may be selected to write '<NUM>' to the selector device <NUM>. At Step <NUM>, the write pulse at the selected voltage and polarity is applied. The write pulse at the selected voltage magnitude and polarity may be applied across the memory cell <NUM>. In some embodiments, the write pulse may be applied by charging WL <NUM> and BL <NUM> to appropriate voltages. After the write pulse is applied, the memory cell <NUM> may exhibit a threshold voltage corresponding to the values of the first and second bits. For example, the memory cell <NUM> may exhibit one of the threshold voltages shown in <FIG>.

In some embodiments, Steps <NUM> and <NUM> may be performed in reverse order. In some embodiments, Steps <NUM> and <NUM> may be performed simultaneously. In some embodiments, the locations of the first and second bits may be reversed. That is, the first bit may be written to the selector device <NUM> and the second bit may be written to the memory element <NUM>. In some embodiments, multiple bits, for example, more than two logic states, may be stored in the memory element <NUM>.

Method <NUM> may be used for writing to memory cells having other numbers of bits and/or logic levels. In some embodiments, certain combinations of voltage magnitude and/or polarity selections may be combined into same logic states. For example, for a three level memory cell, after Step <NUM>, the memory cell <NUM> may exhibit threshold voltages corresponding to only three logic states. In this example, for a certain voltage magnitude selected at Step <NUM>, the same logic state may be written to the memory cell <NUM> regardless of what polarity is selected at Step <NUM>. Other combinations of voltage magnitude and polarity may be used.

<FIG> is a flow chart of a method <NUM> for reading a memory cell according to an embodiment of the disclosure. In some embodiments, the method <NUM> may be used by the memory <NUM> of <FIG> for writing a memory cell, and the memory cell may be implemented by memory cell <NUM> shown in <FIG>. For example, the control logic <NUM> may provide internal control signals to various circuits in the memory <NUM> to perform the method <NUM>. The memory cell may exhibit the threshold voltage characteristics illustrated in <FIG>. The method <NUM> may utilize a ramped voltage read pulse, for example, read pulse <NUM> shown in <FIG>. The read pulse may apply an increasing voltage level up to a maximum voltage of VR. The read pulse may be the same polarity each time a read operation is performed by a memory. The maximum voltage VR of the read pulse may be selected to be greater than the threshold voltage for one or more of the logic states of the memory cell <NUM>. In some embodiments, the maximum voltage of the read pulses may be high enough to threshold a memory cell in any logic state. For example, in some embodiments VR = 6V, VTH0 = 4V, VTH1 = <NUM>. 5V, VTH2 = <NUM>. 0V, and VTH3 = <NUM>. In some embodiments, VR may be chosen to fall between VTH2 and VTH3, for example, VR=<NUM>. Other maximum voltages of the read pulse and other threshold voltage distributions of the memory cell may be used.

At Step <NUM>, a read pulse is applied to the memory cell. The polarity of the read pulse may be a same or different polarity than a write pulse applied to the memory cell. The voltage of the read pulse may be ramped linearly as shown in <FIG> or nonlinearly (e.g., exponentially). In some embodiments, the voltage is increased to a maximum voltage VR. In some embodiments, the voltage is increased until a threshold event is detected in the memory cell.

At Step <NUM>, a threshold event of the memory cell is detected. The threshold may be detected by a sense amplifier in some embodiments. In some embodiments, a voltage and/or current may be detected in response to the read pulse and/or threshold event. In some embodiments, at Step <NUM>, no threshold event of the memory cell is detected. In these embodiments, VR may have been selected to below the highest threshold voltage of the memory cell (e.g., VR= <NUM>. 0V and VTH3= <NUM>.

The logic state of the memory cell is determined at Step <NUM>. In some embodiments, the logic state of the memory cell may be one of a plurality of logic states. In some embodiments, the logic state of the memory cell is determined by the voltage required to threshold the memory cell. In embodiments where no threshold event is detected at Step <NUM>, it may be determined that the memory cell is in the logic state having the highest threshold voltage. In some embodiments, the time required to threshold the memory cell may be used to determine the logic state of the memory cell. For example, if a memory cell thresholds between <NUM>-4ns, it may be determined to have been in State<NUM> and if the memory cell thresholds between <NUM>-10ns, it may be determined to have been in State<NUM>. Other time distributions may be possible. In some embodiments, using the time required to threshold may be used with a voltage ramp pulse such as read pulse <NUM> in <FIG>.

The method <NUM> for reading a memory cell may be destructive. That is, the application of the read pulse may change the threshold voltage of the memory cell, and thus, change the logic state of the memory cell. Consequently, the logic state of the memory cell may need to be rewritten after the memory cell is read. The logic state of the memory cell may be rewritten following Step <NUM>. A write operation, such as method <NUM> may be used to rewrite the logic state to the memory cell.

<FIG> is a flow chart of a method <NUM> for reading a memory cell according to an embodiment of the disclosure. In some embodiments, the method <NUM> may be used by the memory <NUM> of <FIG> for reading a memory cell, and the memory cell may be implemented by memory cell <NUM> shown in <FIG>. The memory cell may exhibit the threshold voltage characteristics illustrated in <FIG>. The method <NUM> may utilize a staircase voltage read pulse, for example, read pulse <NUM> shown in <FIG>.

At Step <NUM>, a first voltage (e.g., 4V) is applied across the memory cell. At Step <NUM>, a threshold event may be detected. If a threshold event is detected, a first logic state (e.g., State<NUM>) may be determined at Step <NUM>, and the other steps shown in method <NUM> may be omitted.

If no threshold event is detected at Step <NUM>, a second voltage (e.g., <NUM>. 5V), greater than the first voltage, may be applied across the memory cell at Step <NUM>. At Step <NUM>, a threshold event may be detected. If a threshold event is detected, a second logic state (e.g., State<NUM>) may be determined at Step <NUM>, and the other steps shown in method <NUM> may be omitted.

If no threshold event is detected at Step <NUM>, a third voltage (e.g., 5V), greater than the first and second voltages, may be applied across the memory cell at Step <NUM>. At Step <NUM>, a threshold event may be detected. If a threshold event is detected, a third logic state (e.g., State<NUM>) may be determined at Step <NUM>. If no threshold event is detected, a fourth logic state (e.g., State<NUM>) may be determined at Step <NUM>.

In some embodiments, even if a threshold event is detected at Step <NUM> and/or Step <NUM>, additional voltages of the staircase voltage read pulse may be applied to the memory cell. That is, the additional steps are not omitted from method <NUM>. In some embodiments, the staircase voltage read pulse may include more or less than three voltages. The number of voltages included in the read pulse may be determined, at least in part, on the possible number of logic states of the memory cell. For example, in a memory cell having three logic levels (e.g., StatesA-C), which may correspond to <NUM> bits, the staircase voltage read pulse may include two voltages and Steps <NUM> and <NUM> may be omitted from method <NUM>.

Other writing and reading protocols and/or modifications to the protocols described herein may be used without departing from the principles of the disclosure. For example, in some methods, sensing currents and/or voltages may be limited to a specific time period. The time period may be from the initiation of a read pulse to a point in time after the initiation of the read pulse (e.g., 20ns). In some embodiments, a memory cell may be read in a forward polarity and written in either the forward or reverse polarity. In some embodiments, the memory cell may be read in a reverse polarity and written in either the forward or reverse polarity.

In some embodiments, the materials of the memory element and/or selector device of the memory cell may exhibit a greater difference between threshold voltages of several logic states when read in a reverse polarity. In some embodiments, the materials of the memory element and/or selector device of the memory cell may exhibit a greater difference between threshold voltages of the several logic states when read in a forward polarity. The polarity of the read pulses may be selected to provide the greatest difference between threshold voltages.

Memories in accordance with embodiments of the present invention may be used in any of a variety of electronic devices including, but not limited to, computing systems, electronic storage systems, cameras, phones, wireless devices, displays, chip sets, set top boxes, or gaming systems.

Claim 1:
An apparatus, comprising:
a non-volatile memory cell (<NUM>) including:
a memory element (<NUM>) comprising a first chalcogenide material, wherein the memory element (<NUM>) is configured to exhibit a first threshold voltage based on the magnitude of a voltage applied across the memory cell; and
a selector device (<NUM>) electrically coupled to the memory element comprising a second chalcogenide material, wherein the selector device (<NUM>) is configured to exhibit a second threshold voltage based on the relative voltage polarities of read and write pulses applied across the memory cell;
a first memory access line (<NUM>) coupled to the memory cell;
a second memory access line (<NUM>) coupled to the memory cell;
a first access line driver coupled to the first memory access line (<NUM>); and
a second access line driver coupled to the second memory access line (<NUM>),
wherein the first and second access line drivers are configured to:
provide a first voltage at a first polarity across the memory cell (<NUM>) to write a first logic state to the memory cell,
provide a second voltage at a second polarity across the memory cell (<NUM>) to write a second logic state to the memory cell,
provide a third voltage at the first polarity across the memory cell (<NUM>) to write a third logic state to the memory cell, and
provide a fourth voltage at the second polarity across the memory cell (<NUM>) to write a fourth logic state to the memory cell, wherein the first, second, third, and fourth logic states correspond to values of a first bit and a second bit of data stored in the memory cell (<NUM>), wherein the first bit is stored in the memory element and is represented by the first threshold voltage, and the second bit is stored in the selector device and is represented by the second threshold voltage.