Patent Description:
Power semiconductor module arrangements usually include at least one substrate. The substrate may be arranged on a base plate. A semiconductor arrangement including a plurality of semiconductor components (e.g., two diodes, MOSFETs, JFETs, HEMTs, IGBTs, or any other suitable controllable semiconductor elements in a parallel, half-bridge, or any other configuration) is usually arranged on at least one of the at least one substrates. Each substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor components are mounted, for example, on the first metallization layer. The first metallization layer may be a structured layer while the second metallization layer is usually a continuous layer. The second metallization layer may be attached to a base plate.

Heat that is generated by the controllable semiconductor components is dissipated through the substrate to the base plate. A heat-conducting layer is usually arranged between the substrate and the base plate to effectively conduct the heat away from the substrate. The substrate, the base plate and the heat-conducting layer, however, usually each have a different coefficient of thermal expansion. A mismatch of the thermal expansion coefficients of the different parts, however, may result in a degradation of the heat-conducting layer due to thermal cycling and the different linear expansion of the different parts during the use of the power semiconductor module arrangement. In particular, a shear stress arising in the heat-conducting layer may accelerate the degradation of the heat-conducting layer. The shear stress within the heat-conducting layer may be caused, inter alia, by a different linear expansion of the substrate and the base plate when heated. Document <CIT> discloses semiconductor chips of a semiconductor module that are located on the top side of a metallized ceramic substrate having a first expansion coefficient. The substrate underside is located on a base plate of good thermal conductivity and high heat capacity, of a material with a second different expansion coefficient. Between the substrate and base plate is fitted an intermediate plate of a material of a third expansion coefficient of a magnitude lying between the first two expansion coefficients. The substrate is firmly coupled to the intermediate plate top side, while the base plate is secured to its underside. Document <CIT> discloses an electronic device comprising at least one electronic part and a substrate on which said electronic part is mounted. There is a need for an improved power semiconductor module arrangement which provides for a good thermal conductivity between the substrate and the base plate and which has an increased lifetime.

A power semiconductor module arrangement includes a semiconductor substrate including a dielectric insulation layer, a first metallization layer attached to the dielectric insulation layer, and a second metallization layer attached to the dielectric insulation layer, wherein the dielectric insulation layer is disposed between the first and second metallization layers. The power semiconductor module arrangement further includes a base plate, and a layer of heat-conducting material arranged between the semiconductor substrate and the base plate in a vertical direction of the power semiconductor module arrangement. The layer of heat-conducting material is arranged adjacent to a surface of the semiconductor substrate and adjacent to a surface of the base plate, wherein the surface of the semiconductor substrate and the surface of the base plate are plane surfaces. The semiconductor substrate has a first thermal expansion coefficient of <NUM> ppm/K or lower, the base plate has a second thermal expansion coefficient of <NUM> ppm/K or lower, and the layer of heat-conducting material has a third thermal expansion coefficient that is <NUM> ppm/K or higher. The layer of heat-conducting material is a solder layer, and has a thickness in the vertical direction, wherein the thickness is between <NUM> and <NUM>.

The components in the figures are not necessarily to scale, emphasis is instead being placed upon illustrating the principles of the invention.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

<FIG> exemplarily illustrates a semiconductor substrate <NUM>. The semiconductor substrate <NUM> includes a dielectric insulation layer <NUM>, a (structured) first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. Optionally, the first and/or second metallization layer <NUM>, <NUM> may be covered by a thin layer of nickel or silver, for example. Such a layer may be formed using a nickel plating process or a silver plating process, for example. The semiconductor substrate <NUM> may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulation layer <NUM> may consist of or include one of the following materials: Al<NUM>O<NUM>, AlN, or Si<NUM>N<NUM>. For instance, the substrate <NUM> may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate.

Usually one or more semiconductor bodies <NUM> are arranged on a semiconductor substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on a semiconductor substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), or any other suitable controllable semiconductor element. One or more semiconductor bodies <NUM> may form a semiconductor arrangement on the semiconductor substrate. In <FIG>, two semiconductor bodies <NUM> are exemplarily illustrated. Any other number of semiconductor bodies <NUM>, however, is also possible.

In the example illustrated in <FIG>, the semiconductor substrate <NUM> is attached to a base plate <NUM> with the second metallization layer <NUM> arranged between the dielectric insulation layer <NUM> and the base plate <NUM>. A layer <NUM> of heat-conducting material is arranged between the second metallization layer <NUM> and the base plate <NUM> and is configured to form a firm substance-to-substance bond between the semiconductor substrate <NUM> and the base plate <NUM>. Heat that is generated by the semiconductor bodies <NUM> may be dissipated through the semiconductor substrate <NUM> and the layer <NUM> of heat-conducting material to the base plate <NUM>. This is exemplarily illustrated by the bold arrows in <FIG>. The second metallization layer <NUM> of the semiconductor substrate <NUM> in <FIG> is a continuous layer. The first metallization layer <NUM> is a structured layer in the arrangement illustrated in <FIG>. "Structured layer" in this context means that the first metallization layer <NUM> is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this arrangement exemplarily includes four different sections. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer <NUM> may have no electrical connection or may be electrically connected to one or more other sections using electrical connections such as, e.g., bonding wires. Electrical connections may also include connection plates or conductor rails, for example, to name just a few examples. The first metallization layer <NUM> being a structured layer, however, is only an example. It is also possible that the first metallization layer <NUM> be a continuous layer. According to another example, the semiconductor substrate <NUM> may only comprise a dielectric insulation layer <NUM> and a first metallization layer <NUM>. The second metallization layer <NUM> may be omitted.

The base plate <NUM> may comprise a metal. According to one example, the base plate comprises at least one of Al and Cu. According to another example, the base plate <NUM> may be a metal matrix composite (MMC) base plate comprising an MMC material such as AlSiC. Any other suitable materials are possible. The base plate <NUM>, optionally, may also be covered by a thin layer of nickel or silver, for example. Such a layer may be formed using a nickel plating process or a silver plating process, for example.

The thermal expansion coefficient of semiconductor substrates <NUM> usually lies in the range of 8ppm/K or lower. A ceramic material that is used for semiconductor substrates may have a CTE of between 4ppm/K and 8ppm/K. However, ceramic materials having a CTE of >8ppm/K are also known. , zirconium dioxide ceramics usually have a CTE of about <NUM>,5ppm/K. The thermal expansion coefficient of typical base plates is generally higher than the CTE of typical substrates, and usually lies in the range of about <NUM> ppm/K. The thermal expansion coefficient of typical heat-conducting pastes usually lies in the range of about <NUM> ppm/K or even ><NUM> ppm/K.

The difference between the thermal expansion coefficients CTE of typical substrates and that of base plates is problematic in many cases. The different CTEs may lead to severe damage of the power semiconductor module arrangement, especially within the layer <NUM> of heat-conducting material that is used to attach the substrate <NUM> to the base plate <NUM>. This is because the substrate <NUM> and the base plate <NUM>, when heated, expand to a different degree (linear expansion), resulting in shear forces within the substrate <NUM> and the base plate <NUM>. This again may result in shear forces within the layer <NUM> of heat-conducting material. When using an MMC base plate, for example, the thermal expansion coefficient of the base plate <NUM> may be adjusted to the CTE of typical semiconductor substrates. Considering the vertical gradient in temperature of the arrangement including the substrate <NUM>, the layer <NUM> and the base plate <NUM>, the CTE of the base plate <NUM> may be higher to some extent. MMC base plates usually have a CTE of about <NUM> ppm/K or about <NUM> ppm/K or lower. Choosing a base plate <NUM> having a CTE that is essentially equal to the CTE of the substrate <NUM> may significantly reduce the stress that is induced on the power semiconductor module arrangement because the substrate <NUM> and the base plate <NUM> expand to a similar degree, resulting in essentially equal linear expansion. For example, a difference between the CTEs of the semiconductor substrate <NUM> and the CTEBP of the base plate <NUM> may be <NUM> ppm/K or lower (|CTEs - CTEBP| < <NUM> ppm/K), <NUM> ppm/K or lower (|CTEs - CTEBP| < <NUM> ppm/K), or <NUM> ppm/K or lower (|CTEs - CTEBP| < <NUM> ppm/K). Preferably, the base plate <NUM> has a CTE that is higher than the CTE of the substrate <NUM>. The substrate <NUM> may have a CTE of <NUM> ppm/K, 6ppm/K, or <NUM> ppm/K, for example. Choosing a base plate <NUM> with a CTE of <NUM> ppm/K or <NUM> ppm/K results in a difference of the CTEs between the substrate <NUM> and the base plate <NUM> of <NUM> ppm/K, <NUM> ppm/K, <NUM> ppm/K, <NUM> ppm/K, <NUM> ppm/K, or <NUM> ppm/K, respectively. While the CTEs of the substrate <NUM> and the base plate <NUM> may be adjusted to each other, the layer <NUM> of heat-conducting material that is arranged between the substrate <NUM> and the base plate <NUM> remains problematic, having a CTE that is significantly higher than both the CTE of the substrate <NUM> and the CTE of the base plate <NUM>. This results in a three-dimensional deformation of the layer <NUM> during each thermal cycle. The layer <NUM> of heat-conducting material may be a solder layer, for example. According to one example, the layer <NUM> may comprise at least one of Au, SnAu, SnAg, SnCu, SnSb, and an eutectic alloy (e.g., Sn<NUM>Pb<NUM>).

With respect to differences in thermal expansion, one also has to consider the temperature gradient from chip (semiconductor body <NUM>) to heat sink or to ambient. As thermal cycles are caused by power losses within the chip, resulting in the chips having the highest temperature, and temperature decreasing from layer to layer (semiconductor substrate, base plate) downwards towards the heat sink and finally the ambient. Therefore the linear thermal expansion may be similar in base plate and substrate for a CTE of the base plate that is a little higher than the CTE of the substrate. However, the magnitude of vertical gradient in temperature depends on cooling intensity in the application of the modules and differs from case to case. Therefore, adjusting the thermal expansion from baseplate to substrate is the compromise.

In order to reduce the stress on the layer <NUM> of heat-conducting material, according to one example, the thickness d1 of the layer <NUM> is kept comparably small. That is, a thickness d1 of the layer <NUM> between the substrate <NUM> and the base plate <NUM> is chosen from between <NUM> and <NUM>. A thickness d1 of less than <NUM> may be chosen in order to reduce the stress that is induced on the layer <NUM>. The layer <NUM> usually covers a comparably large area of the base plate <NUM> and the substrate <NUM>. For example, in the horizontal directions x, z, the layer <NUM> may cover an area of up to <NUM><NUM> or even up to <NUM><NUM> and more. When heated, the material of the layer <NUM> expands significantly. Material that is arranged in a central part of the layer <NUM> is surrounded by other material horizontally (see section B in <FIG>). Therefore, this material can only expand in a vertical direction y. The neighboring material prevents the material in this inner section B from expanding in width. This results in a three-dimensional deformation of the layer <NUM> each time the temperature changes.

A minimum thickness d1 may be chosen in order to allow at least for a certain difference of expansion between the substrate <NUM> and the base plate <NUM>.

Known heat-conducting (solder) layers generally have a thermal conductivity of between <NUM> and 60W/mK. This, however, may not be enough for certain applications. Therefore, in order to further increase the thermal conductivity of the layer <NUM>, thermally conductive particles <NUM> may be added to the heat-conducting layer <NUM>. This is schematically illustrated in <FIG>, which shows the section A of the power semiconductor module arrangement of <FIG>.

The thermally conductive particles <NUM> that may be added to the layer <NUM> of heat-conducting material may be evenly distributed within the layer <NUM>. The thermal conductivity of the particles <NUM> is generally greater than the thermal conductivity of the surrounding material of the heat-conducting layer <NUM>. For example, the particles <NUM> may have a thermal conductivity of more than 60W/mK. For example, the particles <NUM> may have a thermal conductivity of between <NUM> and 400W/mK. The particles <NUM> may comprise a ceramic material, glass, or a metal powder, for example. The mixture comprising the material of the heat-conducting layer <NUM> and the particles <NUM>, however, usually still has a CTE that is significantly higher than the CTEs of the substrate <NUM> and the base plate <NUM>. A diameter of each of the particles may be equal to or less than the thickness d1 of the layer <NUM>. According to one example, a diameter of at least a part of the particles <NUM> equals the thickness d1 of the layer <NUM>. In this way, the particles <NUM> may function as spacers, as will be described in further detail with respect to <FIG> below.

In a power semiconductor arrangement comprising a substrate <NUM> and a base plate <NUM> which have essentially matching CTEs, and further comprising only a thin layer <NUM> (e.g., with a thickness d1 of between <NUM> and <NUM>) of heat-conducting material between the substrate <NUM> and the base plate <NUM>, it is generally not necessary to provide an anchoring structure or anything similar. An anchoring structure may comprise indentations/protrusions in the second metallization layer <NUM> of the substrate <NUM>, for example. Such protrusions reach into the layer <NUM> and are surrounded by the material of the layer <NUM>. The function of such anchoring structures is to distribute the mechanical stress over the full thickness of the layer <NUM>. For the geometry of the metallization layer <NUM> in each case (semiconductor assembly, circuit substrate size, shape and material of the baseplate), an anchoring structure may be optimized so that the mechanical stress is correspondingly distributed and reduced.

In the present case, however, the surface <NUM> of the second metallization layer <NUM> as well as the surface <NUM> of the base plate <NUM> may be plane and not comprise any indentations or protrusions. This is because the mechanical stress is reduced by adapting the CTEs of the substrate <NUM> and the base plate <NUM> and by forming only a thin layer <NUM> of heat-conducting material between the substrate <NUM> and the base plate. "Plane" in this context also refers to surfaces <NUM>, <NUM> having a certain surface roughness that results from the manufacturing process of the surface <NUM>, <NUM>. For example, metallization layers <NUM>, <NUM> of a semiconductor substrate usually have a certain surface roughness. The surfaces having such a common surface roughness, however, are still essentially plane in the sense of the present invention.

In the following, several different examples of possible power semiconductor arrangements are given.

According to a first example, the substrate comprises a CTE of <<NUM> ppm/K. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or less. The thickness d1 of the heat-conducting layer <NUM> is between <NUM> and <NUM>.

According to a second example, the substrate <NUM> is an A1N substrate. That is, the dielectric insulation layer <NUM> comprises AlN. The dielectric insulation layer <NUM> has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> comprises copper (Cu) and has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> may be covered by a thin layer of nickel or silver, as has been described above. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or lower. The thickness d1 of the layer <NUM> is between <NUM> and <NUM>.

According to a third example, the substrate <NUM> is a Si<NUM>N<NUM> substrate. That is, the dielectric insulation layer <NUM> comprises Si<NUM>N<NUM>. The dielectric insulation layer <NUM> has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> comprises copper and has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> may be covered by a thin layer of nickel or silver, as has been described above. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or lower. The thickness d1 of the layer <NUM> is between <NUM> and <NUM>.

According to a fourth example, the substrate <NUM> is an A1N substrate. That is, the dielectric insulation layer <NUM> comprises AlN. The dielectric insulation layer <NUM> has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> comprises copper and has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> may be covered by a thin layer of nickel or silver, as has been described above. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or lower. The thickness d1 of the layer <NUM> is between <NUM> and <NUM>.

According to a fifth example, the substrate <NUM> is a Si<NUM>N<NUM> substrate. That is, the dielectric insulation layer <NUM> comprises Si<NUM>N<NUM>. The dielectric insulation layer <NUM> has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> comprises copper and has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> may be covered by a thin layer of nickel or silver, as has been described above. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or lower. The thickness d1 of the layer <NUM> is between <NUM> and <NUM>.

According to a sixth example, the substrate <NUM> is an Al<NUM>O<NUM> substrate. That is, the dielectric insulation layer <NUM> comprises Al<NUM>O<NUM>. The dielectric insulation layer <NUM> has a thickness of about <NUM> to <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> comprises copper and has a thickness of about <NUM> in the vertical direction y. Each of the first and second metallization layers <NUM>, <NUM> may be covered by a thin layer of nickel or silver, as has been described above. The base plate <NUM> is an MMC base plate having a CTE of about <NUM> ppm/K or lower. The thickness d1 of the layer <NUM> is between <NUM> and <NUM>.

Generally speaking, the thickness of the dielectric insulation layer <NUM> may be chosen from a range between <NUM> to <NUM>. The thickness of the first and the second metallization layers <NUM>, <NUM> may each be chosen from a range between <NUM> and <NUM>. The first metallization layer <NUM> may have the same or a different thickness than the second metallization layer <NUM>. A thickness of the base plate <NUM> in the vertical direction may be chosen from between <NUM> to <NUM>.

In order to prevent the heat-conducting layer <NUM> from becoming too thin (less than the minimum thickness d1) during production, spacers <NUM> may be arranged between the substrate <NUM> and the base plate <NUM>. This is schematically illustrated in <FIG>. One or more spacers <NUM> may be arranged on the base plate <NUM> together with the layer <NUM> of heat-conducting material, for example, before arranging the substrate <NUM> on the layer <NUM> and the spacers <NUM>. Usually, as few spacers <NUM> as possible are used in order to save costs. According to one example, one spacer <NUM> is arranged at each corner of a rectangular semiconductor substrate <NUM>. When joining the substrate <NUM> to the base plate <NUM> by means of the layer <NUM>, the material forming the layer <NUM> is usually liquid or viscous. Therefore, when pressing the substrate <NUM> on the layer <NUM>, the still liquid or viscous material may be displaced in the horizontal directions x, z, and the thickness d1 of the layer d1 may be decreased. The spacers <NUM> prevent the substrate <NUM> from being pressed closer to the base plate <NUM>. In this way, an even layer <NUM> having a desired thickness d1 over the entire surface may be formed. The spacers <NUM> may remain between the substrate <NUM> and the base plate <NUM> after mounting/joining the substrate <NUM> onto the base plate <NUM>. Mounting the substrate <NUM> on the base plate <NUM> may comprise a soldering process, for example, or a heating step wherein liquid is removed from the layer <NUM> in order to form a firm substance-to-substance bond between the substrate <NUM> and the base plate <NUM>. The spacers <NUM> may have a rounded or a square cross-section, for example. Any other cross-sections, however, are also possible. As has been described with respect to <FIG> above, heat-conducting particles <NUM> may function as spacers.

According to another example, a maximum thickness d1 of the layer <NUM> of heat-conducting material may be controlled by the applied volume size or thickness of a so-called (solder) preform or a (solder) paste layer. The preform may be arranged between the semiconductor substrate <NUM> and the base plate <NUM> to form the layer <NUM> of heat-conducting material. The volume of the preform may be chosen such that after forming the connection between the substrate <NUM> and the base plate <NUM>, it results in an average of the thickness d1 or at least <NUM>% of the thickness d1 of the layer of heat-conducting material <NUM>. A preform is generally provided as a solid piece that is fused by applying heat while forming the connection between the substrate <NUM> and the base plate <NUM>. During the heating step, the height of the preform is generally reduced to a certain degree by pressing the substrate <NUM> onto the preform.

According to another example, a barrier may be provided on the base plate <NUM> that extends around the substrate <NUM> and that prevents the material (solder) from flowing outside of a defined area. In particular, the barrier may be arranged such that it ensures that the material of the layer <NUM> stays within a defined area below the substrate <NUM> during the mounting process (while it is liquid or viscous). The volume, and therefore the height of the preform or (solder) material may be chosen such that it results in the desired thickness of the layer <NUM> after connecting the substrate <NUM> to the base plate <NUM>, that is, after rigidifying the material and forming the connection. The (solder) material generally has a certain surface tension which prevents the substrate <NUM> from sinking in too far into the material of the layer <NUM>.

According to an even further example, a height limiter may be provided on top of the substrate <NUM> that is configured to prevent the thickness of the layer <NUM> from exceeding a maximum thickness. In particular, the height limiter prevents the substrate <NUM> from moving away from the substrate <NUM> in a vertical direction. A distance between the substrate <NUM> and the base plate <NUM> that is filled with the layer <NUM>, therefore, is prevented from becoming greater than the maximum thickness.

Claim 1:
A power semiconductor module arrangement comprising:
a semiconductor substrate (<NUM>) comprising a dielectric insulation layer (<NUM>), a first metallization layer (<NUM>) attached to the dielectric insulation layer (<NUM>), and a second metallization layer (<NUM>) attached to the dielectric insulation layer (<NUM>), wherein the dielectric insulation layer (<NUM>) is disposed between the first and second metallization layers (<NUM>, <NUM>);
a base plate (<NUM>); and
a layer of heat-conducting material (<NUM>) arranged between the semiconductor substrate (<NUM>) and the base plate (<NUM>) in a vertical direction (y) of the power semiconductor module arrangement, wherein
the layer of heat-conducting material (<NUM>) is arranged adjacent to a surface (<NUM>) of the semiconductor substrate (<NUM>) and adjacent to a surface (<NUM>) of the base plate (<NUM>), wherein the surface (<NUM>) of the semiconductor substrate (<NUM>) and the surface (<NUM>) of the base plate (<NUM>) are plane surfaces,
the semiconductor substrate (<NUM>) has a first thermal expansion coefficient of <NUM> ppm/K or lower,
the base plate (<NUM>) has a second thermal expansion coefficient of <NUM> ppm/K or lower,
the layer of heat-conducting material (<NUM>) has a third thermal expansion coefficient that is <NUM> ppm/K or higher,
characterized in that
the layer of heat-conducting material (<NUM>) is a solder layer, and
the layer of heat-conducting material (<NUM>) has a thickness (d1) in the vertical direction (y), wherein the thickness (d1) is between <NUM> and <NUM>.