Patent Description:
A neural network refers to a computational architecture that models the biological brain. With the development of neural network technology, various kinds of electronic systems have been actively studied for analyzing input data and extracting valid information using a neural network device. Apparatuses for processing a neural network require a large amount of data transmission and computation with respect to complex input data. Accordingly, in order to extract desired information by analyzing a large amount of input data in real time using a neural network, a technology capable of efficiently processing a data flow related to a neural network is required. <CIT> relates to data inspection for compression/decompression configuration and data type determination. Distribution of data in a neural network data set is used to determine an optimal compressor configuration for compressing the neural network data set and/or the underlying data type of the neural network data set. By using a generalizable optimization of examining the data prior to compressor invocation, this technique allows to tune a compressor to better target the incoming data. For sparse data compression, this step may involve examining the distribution of data. By inspecting the distribution of data, it is also possible to very accurately predict the data width of the underlying data. <CIT> relates to autonomous vehicle neural network optimization. Methods and apparatus relating to providing an adaptive compression algorithm selection for different layer parameters using a highly-parallel general-purpose graphics processing unit are disclosed therein.

It is the object of the present invention to provide an improved method and apparatus for processing data of a neural network.

However, the present invention is defined solely by the appended claims.

Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems defined in the appended claims.

Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on an understanding of the disclosure of the present application. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure of the present application and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein. The use of the term "may" herein with respect to an example or embodiment (e.g., as to what an example or embodiment may include or implement) means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto.

<FIG> is a diagram illustrating an architecture of a neural network <NUM> according to one or more examples.

Referring to <FIG>, the neural network <NUM> may include an architecture of a deep neural network (DNN) or n-layers neural networks. The DNN or n-layers neural networks may correspond to convolutional neural networks (CNNs), recurrent neural networks (RNNs), deep belief networks, restricted Boltzman machines, etc. For example, the neural network <NUM> may be implemented as a CNN, but is not limited thereto. The neural network <NUM> of <FIG> may be representative of some layers of the CNN. Accordingly, the neural network <NUM> may be representative of a convolutional layer, a pooling layer, or a fully connected layer, etc. of a CNN. However, for convenience of explanation, in the following descriptions, it is assumed that the neural network <NUM> corresponds to the convolutional layer of the CNN.

In the convolution layer, a first feature map FM1 may correspond to an input feature map, and a second feature map FM2 may correspond to an output feature map. The feature map may denote a data set representing various characteristics of input data. The first and second feature maps FM1 and FM2 may each be a high-dimensional matrix of two or more dimensions, and have respective activation parameters. When the first and second feature maps FM1 and FM2 correspond to, for example, three-dimensional feature maps, the first and second feature maps FM1 and FM2 have a width W (or column), a height H (or row), and a depth D. The depth D may correspond to the number of channels.

In the convolution layer, a convolution operation with respect to the first feature map FM1 and a weight map WM may be performed, and as a result, the second feature map FM2 may be generated. The weight map WM may filter the first feature map FM1 and is referred to as a filter or kernel. In one example, a depth of the weight map WM, that is, the number of channels is the same as the depth D of the first feature map FM1, that is, the number of channels. The weight map WM is shifted by traversing the first feature map FM1 as a sliding window. In each shift, weights included in the weight map WM may respectively be multiplied and added to all feature values in a region overlapping with the first feature map FM1. As the first feature map FM1 and the weight map WM are convolved, one channel of the second feature map FM2 may be generated.

In <FIG>, although one weight map WM is depicted, substantially a plurality of channels of the second feature map FM2 may be generated by converging the plurality of weight maps with the first feature map FM1. The second feature map FM2 of the convolution layer may be an input feature map of the next layer. For example, the second feature map FM2 may be an input feature map of a pooling layer. The present example is not limited to such a configuration.

<FIG> is a diagram for explaining an operation performed in a neural network <NUM> according to one or more examples.

Referring to <FIG>, the neural network <NUM> has a structure including input layers, hidden layers, and output layers, and performs operations based on received input data (for example, I<NUM> and I<NUM>), and may generate output data (for example, O<NUM> and O<NUM>) based on a result of the operations.

As described above, the neural network <NUM> may be a DNN or an n-layer neural network including two or more hidden layers. For example, as illustrated in <FIG>, the neural network <NUM> may be a DNN including an input layer (Layer <NUM>), two hidden layers (Layer <NUM> and Layer <NUM>), and an output layer (Layer <NUM>). When the neural network <NUM> is implemented as a DNN architecture, the neural network <NUM> includes a large number of layers capable of processing valid information, and thus, the neural network <NUM> may process a large number of complex data sets than a neural network having a single layer. However, although the neural network <NUM> is illustrated as including four layers, this is only an example, and the neural network <NUM> may include a smaller or larger number of layers, or a smaller or larger number of channels. That is, the neural network <NUM> may include layers of various structures different from those illustrated in <FIG>.

Each of the layers included in the neural network <NUM> may include a plurality of channels. A channel may be representative of a plurality of artificial nodes, known as neurons, processing elements (PEs), units, or similar terms. For example, as illustrated in <FIG>, Layer <NUM> may include two channels (nodes), and each of Layer <NUM> and Layer <NUM> may include three channels. However, this is only an example, and each of the layers included in the neural network <NUM> may include various numbers of channels (nodes).

The channels included in each of the layers of the neural network <NUM> may be connected to each other to process data. For example, one channel may receive data from other channels for operation and output the operation result to other channels.

Each of inputs and outputs of each of the channels may be referred to as an input activation and an output activation. That is, the activation may be an output of one channel and may be a parameter corresponding to an input of channels included in the next layer. Meanwhile, each of the channels may determine its own activation based on activations and weights received from channels included in the previous layer. The weight is a parameter used to operate an output activation in each channel, and may be a value assigned to a connection relationship between channels.

Each of the channels may be processed by a computational unit or a processing element that outputs an output activation by receiving an input, and an input-output of each of the channels may be mapped. For example, when σ is an activation function, <MAT> is a weight from a kth channel included in an (i-<NUM>)th layer to a jth channel included in an ith layer, <MAT> is a bias of the jth channel included in the ith layer, and <MAT> is an activation of the jth channel in the ith layer, the activation may be calculated by using Equation <NUM> below.

As shown in <FIG>, the activation of a first channel CH1 of the second layer Layer <NUM> may be expressed as <MAT>. Also, <MAT> may have a value of <MAT> according to Equation <NUM>. The activation function σ may be a Rectified Linear Unit (ReLU), but is not limited thereto. For example, the activation function σ may be a sigmoid, a hyperbolic tangent, a maxout, etc..

As described above, in the neural network <NUM>, a large number of data sets are exchanged between a plurality of interconnected channels, and a number of computational processes are performed through layers. Therefore, there is a need for a technique capable of reducing a memory required to process complex data of the neural network <NUM>.

On the other hand, data compression may reduce an amount of memory traffic of an operation of the neural network <NUM> and improve the performance of the operation of the neural network <NUM> limited by a memory bound by compressing the neural network data. Here, the memory bound may denote that a time to complete an operation is determined by an amount of memory.

Neural network data is data used in various processes related to machine learning by using a neural network, and may include all static data and dynamic data used or processed in processes of a neural network regardless of whether a data value is changed or not. Neural network data may include all data having different precisions.

Neural network data may include all data, such as values assigned to connection relations of the layers described above, input and output values used in various phases of a process using a neural network, such as the result of multiply-accumulate (MAC) operation, and preset values for the use of a process, etc., with no restrictions on a representation format and usage time. For example, the data of the neural network may include at least one of activations, weights, and gradients of the neural network, but is not limited thereto, and may be data values used or processed in an inference process or a learning process of the neural network.

The one or more examples herein provide a method of compressing various neural network data with no restrictions on a representation format and usage time, thereby reducing a memory access burden and generally performing compression in different neural networks.

Hereinafter, a method of compressing neural network data used in the neural network <NUM> will be described in detail with reference to drawings.

<FIG> is a diagram illustrating a compression pipeline <NUM> for data compression according to an example.

Referring to <FIG>, the compression pipeline <NUM> includes a lossy transformation block <NUM> and a lossless compression block <NUM>. Since the compression pipeline <NUM> is used, an amount of memory traffic may be reduced and the performance of machine learning workloads limited by a memory bound may be improved. For example, full-precision data at a <NUM>-bit floating point may be compressed by a lossy transformation and/or lossless compression for training or inference. The lossy transformation compresses data by reducing an amount of information in the data, and lossless compression may compress data by increasing information density.

The loss transformation technique includes Pruning, single value decomposition (SVD), and quantization, and the lossless compression technique includes Huffman coding, run-length coding on zeros (Z-RLC), and zero-value compression (ZVC), etc..

However, hardware complexities of the lossless compression technique considerably vary, and some compression techniques may be infeasible in hardware with limited resources, such as an embedded system. As a result, a light-weight lossless compression technique that reliably implements a high compression rate at low hardware cost is required.

Meanwhile, a total compression rate of neural network data may be a compression rate of lossy transform (P) and lossless compression (C) (e.g., total compression rate = P × C). However, in the following description, the compression rate is assumed to be the compression rate of lossless compression. However, the compression method according to the examples is not limited thereto, and an overall compression rate may be increased by combining with various lossy transformations, lossless compressions, and/or quantization methods.

For example, quantization may improve the overall compression rate by combining with lossless compression. Quantization may effectively reduce senseless information of neural network data that are random and have high entropy. Accordingly, after the neural network data is quantized, the amount of information is small, but more meaningful information remains, and thus, the compression rate may be increased.

<FIG> is a block diagram showing a hardware configuration of a neural network apparatus according to the present invention.

Referring to <FIG>, the neural network apparatus <NUM> includes a processor <NUM> and a memory <NUM>. In the neural network apparatus <NUM> shown in <FIG>, only components related to the present examples are shown. Accordingly, it is apparent to those skilled in the art that the neural network apparatus <NUM> may further include other general-purpose components in addition to the components shown in <FIG>.

The neural network apparatus <NUM> may correspond to a computing device having various processing functions, such as generating a neural network, training (or learning) a neural network, analyzing statistical characteristics of neural network data, determining a profile for compressing neural network data, splitting the neural network data into a plurality of lanes and compressing each of the plurality of lanes separately, performing inference using a neural network, or retraining the neural network. For example, the neural network apparatus <NUM> may be implemented as various types of devices, such as a personal computer (PC), a server device, and a mobile device, etc..

The neural network apparatus <NUM> may determine an optimum configuration for compression of neural network data and perform compression considering the processing performance of a device (for example, a mobile device, an embedded device, etc.) to which the neural network is deployed. Devices to which the neural network is deployed include, for example, autonomous vehicles, robotics, smartphones, tablet devices, augmented reality (AR) devices, and Internet of Things (IoT) devices that perform voice recognition, video recognition, etc. using neural networks, etc., but are not limited thereto.

According to the present example, additional neural network apparatuses may exist in addition to the neural network apparatus <NUM>. The neural network apparatus <NUM> and additional neural network apparatuses may each perform separate functions for compressing neural network data. For example, the neural network apparatus <NUM> may determine a profile for compressing neural network data, and other neural network apparatuses may compress the neural network data using the profile. However, in the following description, for convenience of explanation, it is assumed that one neural network apparatus <NUM> performs all functions, and the same will be applied to <FIG> to be described later.

The profile denotes a set of information including information about methods of processing a bit representation of neural network data and information about a plurality of compression techniques for compressing the processed bit representation.

The processor <NUM> generates a plurality of candidate profiles by obtaining one or more bit representations of neural network data, and determine a final profile for compressing the neural network data among the candidate profiles.

The candidate profiles denotes profiles generated as candidates to be selected as a final profile and having different conditions.

The final profile denotes a profile including final information on how the neural network apparatus <NUM> compresses neural network data.

The processor <NUM> determines splitting methods and compression techniques of one or more lanes used in the final profile as an optimal configuration for compression of neural network data. As the optimal configuration is determined, an optimal method for compressing neural network data may be determined.

The processor <NUM> splits neural network data into one or more bit segments according to an optimal configuration, and compresses each bit segment with an optimal compression technique. Statistical characteristics of each bit segment may be exposed by splitting the neural network data into a plurality of bit segments. Since the processor <NUM> applies a suitable optimal compression technique to the exposed statistical characteristics of each bit segment, the compression rate may be increased.

When a data value is split into a plurality of bits, a bit segment may denote a group of bits forming a section of each data.

Here, one bit segment may be referred to as a lane. A technique for compressing a plurality of lanes by applying a compression technique suitable for each lane may be referred to as lane compression.

A method of determining an optimum configuration for compression of neural network data by the processor <NUM> and a specific method of compressing neural network data according to the determined optimum configuration will be described in detail below with reference to related drawings.

The processor <NUM> performs an overall function for controlling the neural network apparatus <NUM>. For example, the processor <NUM> controls an overall operation of the neural network apparatus <NUM> by executing programs stored in the memory <NUM> in the neural network apparatus <NUM>. The processor <NUM> may be implemented as a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP) provided in the neural network quantization apparatus <NUM>, but is not limited thereto.

The memory <NUM> is hardware that stores various data processed in the neural network apparatus <NUM>. For example, the memory <NUM> may store data processed and data to be processed in the neural network apparatus <NUM>. Also, the memory <NUM> may store applications, drivers, and the like to be driven by the neural network apparatus <NUM>. The memory <NUM> may be DRAM, but is not limited thereto. The memory <NUM> may include at least one of volatile memory and nonvolatile memory. The non-volatile memory includes read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The volatile memory includes dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, FeRAM, etc. In an embodiment, the memory 120may include at least one of hard disk drive (HDD), solid state drive (SSD), compact flash (CF), secure digital (SD), micro secure digital (micro-SD), mini-SD (mini secure digital), xD (extreme digital), and Memory Stick.

The memory <NUM> may store, for example, neural network data, and may store various programs related to a training algorithm, a compression algorithm, a profiling algorithm, etc. of a neural network to be executed by the processor <NUM>.

The profiling algorithm may refer to an algorithm that draws a method of compressing neural network data to be compressed by using profiles.

<FIG> is a block diagram showing a hardware configuration of a neural network apparatus <NUM> according to an example.

Referring to <FIG>, the neural network apparatus <NUM> includes a neural processor <NUM> and a memory <NUM>. The neural processor <NUM> may further include a neural network processing unit <NUM>, an encoder <NUM> and a decoder <NUM>. The neural processor <NUM> and the memory <NUM> of the neural network apparatus <NUM> may perform the same roles as the processor <NUM> and the memory <NUM> of <FIG>.

The neural processor <NUM> may perform operations for driving the neural network described above. For example, operations may be operations required for inference, training, and re-training according to input data. The neural processor <NUM> may compress neural network data used for operations by using an optimal configuration, and decompress the compressed data of the neural network by using the optimal configuration.

The neural network processing unit <NUM> may control the encoder <NUM> and the decoder <NUM>. For example, the neural network processing unit <NUM> may control the encoder <NUM> to compress neural network data and the decoder <NUM> to decompress the compressed neural network data.

Compression and decompression using the encoder <NUM> and the decoder <NUM> will be described in detail with reference to <FIG>.

Meanwhile, the neural network apparatus <NUM> of <FIG> may be the neural network apparatus <NUM> (<FIG>) described above, or an additional neural network apparatus other than the neural network apparatus <NUM>.

<FIG> is a conceptual diagram for explaining a compression method according to an example. Referring to <FIG>, the processor <NUM> (refer to <FIG>) may perform profiling to compress neural network data.

The processor <NUM> obtains a bit representation <NUM> of neural network data from the memory <NUM> (refer to <FIG>). The obtained bit representation <NUM> is a bit stream. For example, the neural network data may include at least one of activation, weight, and gradient of the neural network <NUM> (refer to <FIG>), and the processor <NUM> may obtain a bit stream of weight data of the neural network <NUM>.

Neural network data used for processing a neural network may be expressed as a bit stream including <NUM> bits (b0, b1, b2, b3, b4, b5, b6, b7, b8 and b9). Here, the bit representation <NUM> of the neural network data is illustrated as a bit stream including <NUM> bits for explanation, but the data format of the neural network data and the number of bits constituting the bit stream are not limited thereto.

Although only one bit representation <NUM> is shown for explanation, the processor <NUM> may obtain a plurality of bit representations. In a neural network, there may be a myriad of data defined by such bit representation. The processor <NUM> may determine a final profile by obtaining a single bit representation, and determine a final profile by obtaining a plurality of bit representations.

The processor <NUM> generates a plurality of candidate profiles by dividing one or more bit representations of the obtained data into one or more lanes, and applying compression techniques to each lane.

For example, the processor <NUM> may generate candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> by dividing the bit representation <NUM> into one or more lanes and applying compression techniques to each lane. However, in <FIG>, only four candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> are shown for convenience of description, but in fact, candidate profiles may be generated in various numbers.

Lanes may denote bit segments having a predetermined bit width generated by splitting a bit stream. For example, in the bit representation <NUM> of profile <NUM> (<NUM>), Lane <NUM> is a bit segment with a bit width of <NUM>, Lane <NUM> is a bit segment with a bit width of <NUM>, Lane <NUM> is a bit segment with a bit width of <NUM>, and Lane <NUM> is a bit segment having a bit width of <NUM>.

The candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include all combinations for splitting the bit representation <NUM>. For example, the candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include profiles in which the number of lanes for dividing the bit representation <NUM> into a plurality of bit segments and the bit width of the bit segment corresponding to each of the lanes are differently set.

In profile <NUM> (<NUM>), the number of lanes is <NUM>, and bit widths corresponding to each of the lanes are <NUM>, <NUM>, <NUM>, and <NUM>. In profile <NUM> (<NUM>), the number of lanes is <NUM>, and bit widths corresponding to each of the lanes are <NUM>, <NUM>, and <NUM>. In profile n-<NUM> (<NUM>), the number of lanes is <NUM>, and bit widths corresponding to each of the lanes are <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In profile n (<NUM>), the number of lanes is <NUM>, and bit widths corresponding to each of the lanes are <NUM>, <NUM>, and <NUM>. <FIG> shows only profiles in which one of the number of lanes and the bit width corresponding to each of the lanes are different from each other. However, profiles in which the number of lanes and the bit width corresponding to each of the lanes are the same and compression techniques are different may also be included.

The candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include all combinations capable of allocating a plurality of compression techniques to each lane split by any one of the splitting methods.

For example, in the candidate profiles <NUM>, <NUM>, <NUM>, and <NUM>, compression techniques may be independently applied to each lane. A Ca compression technique may be applied to Lane <NUM> of the profile <NUM> (<NUM>), a Cb compression technique may be applied to Lane <NUM>, and a Ca compression technique may be applied to Lane <NUM> again. As compression techniques are applied independently to each lane, the same compression technique may be applied to different lanes.

For example, in the candidate profiles <NUM>, <NUM>, <NUM>, and <NUM>, different compression techniques may be applied to each lane. In the profile n (<NUM>), different Ca, Cb, and none among a plurality of compression methods (Ca, Cb, Cc, Cd, and none) may be applied to each lane. "none" may denote a compression technique that does not compress a lane.

The candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include profiles to which compression techniques having different algorithmic parameters are applied.

The algorithmic parameter denotes a parameter used when using a specific compression technique. Each of the compression techniques may have a corresponding algorithmic parameter, and a plurality of compression techniques may have algorithmic parameters different from each other. For example, a maximum sequence may be an algorithmic parameter of a run-length coding on zeros (Z-RLC), a size of matrix may be an algorithmic parameter of a compressed sparse column/row (CSC/CSR), and a size of block may be an algorithmic parameter of a dynamic precision reduction (DPRed).

However, some compression techniques may not have a corresponding algorithmic parameter. For example, zero-value compression (ZVC) may not have a corresponding algorithmic parameter.

A value of an algorithmic parameter may have a controllable range. As the values of the algorithmic parameters are controlled differently, the compression performance and the degree of required memory resources may be different. For example, referring to profile <NUM> (<NUM>), a compression technique of Ca is applied to both Lane <NUM> and Lane <NUM>, but values of each algorithmic parameter may be different from each other as Ca, and Ca20.

The processor <NUM> determines a final profile by comparing compression performances for each of the generated candidate profiles <NUM>, <NUM>, <NUM>, and <NUM>. The compression performances include the compression rates of each candidate profile.

The processor <NUM> thus calculates compression rates corresponding to each of the candidate profiles <NUM>, <NUM>, <NUM>, and <NUM>, and determines a candidate profile having the highest compression rate among the calculated compression rates as the final profile. The processor <NUM> may calculate that the profile <NUM> (<NUM>) has a compression rate of <NUM>%, the profile <NUM> (<NUM>) has a compression rate of <NUM>%, the profile n-<NUM> (<NUM>) has a compression rate of <NUM>%, and the profile n (<NUM>) has a compression rate of <NUM>%. If the compression rate of profiles between the profile <NUM> (<NUM>) and the profile n-<NUM> (<NUM>) is less than <NUM>%, since the compression rate of the profile n (<NUM>) is the greatest among the candidate profiles, the profile n (<NUM>) will be determined as the final profile.

<FIG>, <FIG>, and <FIG> are graphs for explaining a statistical distribution according to an activation split according to an example.

Referring to <FIG>, the candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include profiles having different sparsity distributions of lanes according to the number and bit width of the lanes. In other words, different portions of neural network data may have different sparsity distributions. The first graph 7a shows a sparsity distribution when there is only one lane. The second graph 7b shows a sparsity distribution when there are three lanes and each bit width is <NUM>, <NUM>, and <NUM>, and the third graph 7c shows a sparsity distribution when there are four lanes and each bit width is <NUM>, <NUM>, <NUM>, and <NUM>.

When comparing lane <NUM> and lane <NUM> of the second graph 7b with lane <NUM> of the first graph 7a, it may be seen that lane <NUM> and lane <NUM> of the second graph 7b tend to be very sparse. When comparing lane <NUM> of the third graph 7c with lane <NUM> of the first graph 7a, it may be seen that lane <NUM> of the third graph 7c still tends to be sparse. That is, the most significant bits (MSB) of lane <NUM> of the first graph 7a, which is not split, tend to be very sparse, and as progresses towards the least significant bits (LSB), the sparsity may be reduced.

In this way, the sparsity distribution of each of the lanes may be different according to the splitting method. Since lanes having high sparsity may be more easily compressed than lanes having low sparsity, the compression rate may increase according to the splitting method.

The candidate profiles <NUM>, <NUM>, <NUM>, and <NUM> may include a profile to which a compression technique that does not compress a lane including the least significant bit (LSB) among lanes is applied. Lane <NUM> of the second graph 7b and lane <NUM> of the third graph 7c may have lower sparsity than lane <NUM> of the first graph 7a. Data having low sparsity may have a low compression rate, or may have a greater data capacity. Accordingly, rather, the compression rate may be increased by compressing only lanes having high sparsity and by not compressing lanes having low sparsity.

<FIG> are graphs for explaining a statistical distribution according to a weight split according to an example.

Referring to <FIG>, it may be seen that even if the type of neural network data is weight, the neural network data has a sparsity distribution similar to those of <FIG>.

The fourth graph 7d shows a sparsity distribution when there is only one lane. The fifth graph 7e shows a sparsity distribution when there are three lanes and each bit width is <NUM>, <NUM>, and <NUM>, and the sixth graph 7f shows a sparsity distribution when there are four lanes and each bit width is <NUM>, <NUM>, <NUM>, and <NUM>.

When comparing lane <NUM> and lane <NUM> of the fifth graph 7e with lane <NUM> of the fourth graph 7d, it may be seen that lane <NUM> and lane <NUM> of the fifth graph 7e tend to be very sparse. When comparing lane <NUM> of the sixth graph 7f with lane <NUM> of the fourth graph 7d, it may be seen that lane <NUM> of the sixth graph 7f still tends to be sparse.

On the other hand, in <FIG>, the most significant bit (MSB) corresponding to a sign bit b0 of the bit stream is not omitted, and in <FIG>, the sign bit b0 of the bit stream is omitted, and thus, there may be differences in the shape of the sparsity distribution. For example, if the neural network data value is always positive, the sign bit may be omitted.

<FIG> is a diagram illustrating a candidate profile generation algorithm <NUM> according to an example.

Referring to <FIG>, the candidate profile generation algorithm <NUM> may be used to generate the candidate profiles described with reference to <FIG>.

In operation <NUM>, the processor <NUM> (refer to <FIG>) obtains neural network data, a bit width of bit representations, compression techniques, and algorithmic parameters corresponding to each of the compression techniques.

In operation <NUM>, the processor <NUM> generates all splitting methods in which the number of lanes and/or a bit width of each of the lanes are different.

In operation <NUM>, the processor <NUM> generates candidate profiles having different compression techniques and/or algorithmic parameters for all splitting methods.

In operation <NUM>, the processor <NUM> outputs a result of generating candidate profiles.

<FIG> is a diagram illustrating an optimal configuration determination algorithm <NUM> according to an example.

Referring to <FIG>, the optimal configuration determination algorithm <NUM> may be used to determine a final profile and optimal configuration described with reference to <FIG>.

In operation <NUM>, the processor <NUM> (refer to <FIG>) obtains candidate profiles generated in the candidate profile generation algorithm <NUM> of <FIG>, a bit width of bit representations, compression techniques, symbol-based compression techniques, algorithmic parameters corresponding to each compression technique, and constraints when implementing in hardware.

In operation <NUM>, the processor <NUM> (refer to <FIG>) obtains a set of cases of splitting each lane by all splitting methods in which the number of lanes and/or a bit width of each of the lanes are different.

In operation <NUM>, the processor <NUM> determines a final profile and an optimal configuration in consideration of a set of all splitting cases obtained in operation <NUM> and the constraints obtained in operation <NUM>.

In operation <NUM>, the processor <NUM> outputs an optimal configuration.

<FIG> is a diagram illustrating an algorithm <NUM> for determining an optimal compression technique and a value of an algorithmic parameter according to an example.

Referring to <FIG>, when determining a final profile in operation <NUM> of <FIG>, the algorithm <NUM> for determining an optimal compression technique and a value of an optimal algorithmic parameter may be used.

In operation <NUM>, the processor <NUM> repeatedly compares compression performances with respect to all algorithmic parameter values that all compression techniques may have, and determines an optimum compression technique and an optimum algorithmic parameter value.

The algorithms <NUM>, <NUM>, and <NUM> of <FIG> are described as examples of determining an optimal configuration, and an algorithm for determining the optimal configuration is not limited to the algorithms <NUM>, <NUM>, and <NUM> of <FIG>.

<FIG> is a diagram for describing compression of a bit representation according to an example.

Referring to <FIG>, an optimal configuration for compression of neural network data for a first bit representation <NUM> having a bit width of <NUM> bits may be determined by the method for determining an optimal configuration described above with reference to <FIG>. For example, the optimal configuration may be determined by splitting the first bit representation <NUM> in order from the most significant bits (MSB) to four lanes <NUM>, <NUM>, <NUM> and <NUM> having bit widths of <NUM>, <NUM>, <NUM> and <NUM>, and by compressing each lane by a first compression technique, a second compression technique, the first compression technique, and a third compression technique, respectively.

The processor <NUM> or <NUM> may compress the lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of bit representations <NUM> and <NUM> using an optimal configuration, and may output compressed lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>.

The processor <NUM> or <NUM> may compress the split lanes <NUM>, <NUM>, <NUM> and <NUM> of the first bit representation <NUM> using an optimal configuration, and may output the compressed lanes <NUM>, <NUM>, <NUM> and <NUM>. For example, the processor <NUM> or <NUM> may output the first compressed lane <NUM> by compressing the first lane <NUM> of the first bit representation <NUM> by using a first compression technique, may output the second compressed lane <NUM> by compressing the second lane <NUM> of the first bit representation <NUM> by using a second compression technique, may output the third compressed lane <NUM> by compressing the third lane <NUM> of the first bit representation <NUM> by using the first compression technique, and may output the fourth compressed lane <NUM> by compressing the fourth lane <NUM> of the first bit representation <NUM> by using a third compression technique.

The processor <NUM> or <NUM> may compress the split lanes <NUM>, <NUM>, <NUM>, and <NUM> of the second bit representation <NUM> by using an optimal configuration, and output the compressed lanes <NUM>, <NUM>, <NUM>, and <NUM>. For example, the processor <NUM> or <NUM> may output the first compressed lane <NUM> by compressing the first lane <NUM> of the second bit representation <NUM> by using a first compression technique, may output the second compressed lane <NUM> by compressing the second lane <NUM> of the second bit representation <NUM> by using a second compression technique, may output the third compressed lane <NUM> by compressing the third lane <NUM> of the second bit representation <NUM> by using the first compression technique, and may output the fourth compressed lane <NUM> by compressing the fourth lane <NUM> of the second bit representation <NUM> by using a third compression technique.

The first bit representation <NUM> and the second bit representation <NUM> are split and compressed in the same optimal configuration, but values of each of the bit representations may be different from each other. Even if the same compression technique (first compression technique) is applied to the same lanes <NUM> and <NUM> according to a value of each bit representation, values of the compressed lanes <NUM> and <NUM> may be different from each other. The compressed lanes <NUM> and <NUM> having values from each other may have different bit widths and compressed lane values, may have the same bit width and different compressed lane values, and may have the same compressed lane value and different bit widths.

Meanwhile, the compressed lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> denote only outputs produced by using a compression technique on the lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, and thus, there is no limitations on the format of information included in each compressed lane. For example, according to the compression technique used for compression, the compressed lane may not include any information, have an increased bit width, have a decrease bit width, have an unchanged bit width, and include the same value as a value of a target lane.

A plurality of compression techniques may compress neural network data by reducing redundancy of neural network data. Neural network data may include a plurality of redundant information. A plurality of compression techniques may reduce the size of neural network data by compressing redundant information included in neural network data by using various techniques.

A plurality of compression techniques may have different compression units used in each compression technique. For example, the compression unit used in each compression technique may be a symbol or a sequence of symbols.

A symbol refers to a unit that is a reference when compression is applied to a compression target. For example, the first lanes <NUM> and <NUM> to which the first compression technique is applied may use a bit segment in which a bit width of the first lanes <NUM> and <NUM> is <NUM> as a symbol, and the second lanes <NUM> and <NUM> to which the second compression technique is applied may use a bit segment having a bit width of <NUM> as a symbol.

The sequence of symbols may denote a unit that is a reference when compression is applied to a compression target. The sequence of symbols may denote a sequence in which symbols are arranged over several sequential compression processes. Here, the compression process may denote that compression techniques are applied to one bit representation once. For example, when the first lane <NUM> of the first bit representation is input in the first compression process and the first lane <NUM> of the second bit representation is input in the second compression process, the first compression technique may use the sequential first lanes <NUM> and <NUM> as a sequence of symbols.

A plurality of compression techniques may be separately referred according to a compression unit used in each compression technique. A compression technique using symbols may be referred to as a symbol-based compression technique, and a compression technique using a sequence of symbols may be referred to as a sequence-based compression technique.

According to the present example, a symbol-based compression technique and/or a sequence-based compression technique may be used regardless of the characteristics of input neural network data. An optimum compression rate may be achieved by splitting a bit representation of neural network data into lanes and using a symbol-based compression technique and/or a sequence-based compression technique suitable for the characteristics of each lane.

Each of the compression techniques may have a corresponding algorithmic parameter, and a plurality of compression techniques may have algorithmic parameters different from each other. For example, a maximum sequence may be an algorithmic parameter of a run-length coding on zeros (Z-RLC), a size of matrix may be an algorithmic parameter of a compressed sparse column/row (CSC/CSR), and a size of block may be an algorithmic parameter of a dynamic precision reduction (DPRed). However, some compression techniques may not have a corresponding algorithmic parameter. For example, zero-value compression (ZVC) may not have a corresponding algorithmic parameter.

The processor <NUM> or <NUM> may concatenate the compressed lanes <NUM>, <NUM>, <NUM> and <NUM> and output the compressed bit representation <NUM>, and concatenate the compressed lanes <NUM>, <NUM>, <NUM> and <NUM> and output the compressed bit representation <NUM>. For example, the processor <NUM> or <NUM> may output compressed bit representations <NUM> and <NUM>.

Meanwhile, it is depicted that, in the compressed bit representations <NUM> and <NUM>, the compressed lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are combined in the order of the lanes <NUM>, <NUM>, <NUM> and <NUM>, but there is no limit in the order of combining the compressed lanes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. However, in the following description, for convenience of explanation, it is assumed that the compressed lanes are combined in the order of the lanes.

<FIG> is a table for describing a plurality of compression techniques according to an example.

Referring to <FIG>, a plurality of compression techniques is shown in table <NUM> and may include None, ZVC, Run-Length Coding (RLC), Z-RLC, and DPRed.

As described above with reference to <FIG>, none may denote a compression technique that does not compress lanes. As the lane is not compressed, the compressed lane may have the same value as the lane before compression.

ZVC may not have a corresponding algorithm parameter and may not have a range of values for the algorithm parameter.

An algorithmic parameter corresponding to RLC may be a maximum sequence <NUM>p, and a range of the algorithmic parameter may be <NUM>≤ p ≤<NUM>.

An algorithmic parameter corresponding to Z-RLC may be a maximum sequence <NUM>p, and a range of the algorithmic parameter may be <NUM>≤ p ≤<NUM>.

When compressing a lane with DPRed, the processor <NUM> or <NUM> may compress the lane by adding one bit to the most significant bit (MSB). DPRed that adds one bit to the MSB may be referred to as Sparse-DPRed (S-DPRed). The added one bit may indicate whether all <NUM> are allocated to the block to be compressed or not. Since it is possible to indicate whether all <NUM> are allocated or not, a compression rate of sparse data may be increased.

The processor <NUM> or <NUM> may remove a zero-bit mask when compressing a lane with DPRed. DPRed from which the zero-bit mask is removed may be referred to as Dense DPRed (D-DPRed). As the zero-bit mask is removed, the compression rate of dense data may be increased.

An algorithmic parameter corresponding to D-DPRed and S-DPRed may be a block size p, and a range of the algorithmic parameter may be <NUM>≤ p ≤<NUM>.

<FIG> is a diagram for describing a method <NUM> of compressing according to an optimal configuration according to an example.

Referring to <FIG>, the processor <NUM> or <NUM> may determine an optimal configuration in which the number of lanes is <NUM>; bit widths of each of the lanes (lane <NUM>, lane <NUM>, lane <NUM>, and lane <NUM>) are <NUM> bits, <NUM> bit, <NUM> bits, and <NUM> bits, respectively; compression techniques applied to each lane are Z-RLC, Z-RLC, D-DPRed and None; and values of algorithmic parameters applied to each lane are <NUM><NUM>, <NUM><NUM> and <NUM>.

Meanwhile, the neural network apparatus <NUM> may compress or decompress neural network data based on an optimal configuration determined in advance through profiling as described above. Hereinafter, a method of compressing or decompressing neural network data will be described with reference to <FIG>.

<FIG> is a diagram for describing an encoder <NUM> according to an example.

Referring to <FIG>, the encoder <NUM> may include a first splitter <NUM>, a plurality of compression units 144a, 144b and 144c, and a first concatenator <NUM>. The encoder <NUM> may be a constituent element corresponding to the encoder <NUM> described with reference to <FIG>.

The encoder <NUM> may split neural network data into a plurality of lanes based on a predetermined optimal configuration, and compress each of the split lanes using an optimal configuration.

The first splitter <NUM> may obtain an optimal configuration predetermined by a final profile in which compression techniques set for each lane are defined by dividing neural network data into one or more lanes. For example, the first splitter <NUM> may obtain the optimal configuration from the memory <NUM> (refer to <FIG>), and may obtain from the memory <NUM> via the neural network processing unit <NUM> (refer to <FIG>) a control signal generated by the neural network processing unit <NUM> based on the optimal configuration.

Meanwhile, the method of obtaining the optimum configuration by the first splitter <NUM> is not limited to the method described above.

The first splitter <NUM> may obtain bit representations of data used for processing a neural network, and may split the bit representations into one or more lanes by using an optimal configuration.

The first splitter <NUM> may extract information required for compression techniques used in a plurality of compression units 144a, 144b, and 144c from the bit representations. The extracted information may be transmitted to the compression units 144a, 144b, and 144c that require the extracted information. For example, the first splitter <NUM> may extract leading zero bits required for a null suppression (NS) technique.

The plurality of compression units 144a, 144b, and 144c may compress each of the split lanes using an optimal configuration and output compressed lanes. For example, the plurality of compression units 144a, 144b, and 144c may compress lanes split by a compression technique applied to each lane in an optimal configuration for each compression unit, and output the compressed lanes. Meanwhile, in <FIG>, for convenience of explanation, only three compression units 144a, 144b and 144c are shown, but N (N is a natural number) compression units may be included in the encoder <NUM>.

The plurality of compression units 144a, 144b, and 144c may perform a plurality of compression techniques for each compression unit. As each compression unit performs a plurality of compression techniques, each compression unit may perform an appropriate compression technique even when the optimum configuration is changed.

The plurality of compression units 144a, 144b, and 144c may be matched one-to-one with split lanes according to an optimal configuration. For example, the first compression unit 144a is matched one-to-one with Lane <NUM> and performs a first compression technique, and the second compression unit 144b is matched one-to-one with Lane <NUM> and performs a second compression technique.

The first concatenator <NUM> may concatenate the compressed lanes and output compressed bit representations. The first concatenator <NUM> may concatenate compressed lanes. The compressed lanes concatenated by the first concatenator <NUM> may be referred to as a concatenated lane. The first concatenator <NUM> may generate a compressed bit representation <NUM> based on the concatenated lane and output the compressed bit representation.

The first concatenator <NUM> may insert a stop code for synchronizing the compressed lanes output from the plurality of compression units 144a, 144b and 144c into the concatenated lanes. For example, the first concatenator <NUM> may insert a stop code into the concatenated lanes. Lanes sequentially input to the compression unit 144a, which is one of the compression units 144a, 144b, and 144c, may not be output through the compression unit 144a more than a predetermined number of times. When the compression unit 144a outputs a lane compressed again, the first concatenator <NUM> may insert a stop code into the concatenated lane including the compressed lane output from the compression unit 144a.

The first concatenator <NUM> may check whether the stop code is inserted or not, and insert a bit value indicating whether the stop code is inserted or not according to the check result. The compressed bit representation <NUM> may include a code in the same format as the stop code, even though the stop code is not inserted. In this case, ambiguity in the decoder <NUM> (refer to <FIG>) may be a problem. As a bit value indicating whether the stop code is inserted or not is inserted into the concatenated lane, the decoder <NUM> may distinguish the stop code inserted by the first concatenator <NUM>.

For example, the first concatenator <NUM> may check whether a stop code is inserted or not in the concatenated lane. When it is checked that the stop code is inserted into the concatenated lane, the first concatenator <NUM> may add a bit value indicating that the stop code is inserted into the concatenated lane. When it is checked that the stop code is not inserted in the concatenated lane, the first concatenator <NUM> may add a bit value indicating that the stop code is not inserted into the concatenated lane.

The first concatenator <NUM> may generate a compressed bit representation <NUM> by inserting a stop code and a bit value indicating whether the stop code is inserted or not into the concatenated lane.

<FIG> is a diagram for describing a stop code insertion algorithm <NUM> according to an example.

Referring to <FIG>, the stop code insertion algorithm <NUM> may be used to insert a stop code and a bit value indicating whether the stop code is inserted or not into the concatenated lane, described with reference to <FIG>.

In operation <NUM>, the first concatenator <NUM> adds a stop code and a bit value indicating that the stop code is inserted into the concatenated lane in a situation when a stop code is required.

In operation <NUM>, the first concatenator <NUM> adds a bit value indicating that the stop code is not inserted into the concatenated lane.

For example, a stop code may have a bit width of C, following one bit value of '<NUM>', a bit value of '<NUM>' of C-<NUM> number of bits may be selected, a bit value indicating that the stop code is inserted in the concatenated lane may be one bit value '<NUM>', and a bit value indicating that the stop code is not inserted may be one bit value '<NUM>'. The width of the stop code and the bit value indicating whether the stop code is inserted or not are for illustration only, and are not limited to the above description.

<FIG> is a diagram for describing compression of an encoder according to an example.

Referring to <FIG>, table <NUM> shows a case in which the encoder <NUM> outputs compressed bit representations in each sequential compression process when bit representations of <NUM>-bits are input to the encoder <NUM>. Here, the stop code is '<NUM>', Lane <NUM> of <NUM> bits is compressed by ZVC, and Lane <NUM> of <NUM> bits is compressed by Z-RLC having a Max seq. of <NUM><NUM>. Meanwhile, for convenience of explanation, it is assumed that Lane <NUM> is compressed by the first compression unit 144a (refer to <FIG>) and Lane <NUM> is compressed by the second compression unit 144b (refer to <FIG>).

In a first compression process <NUM>, the compression unit 144a corresponding to Lane <NUM> outputs a compressed lane of '<NUM>', and the compression unit 144b corresponding to Lane <NUM> outputs a compressed lane of '<NUM>'. The first concatenator <NUM> concatenates the compressed lanes and outputs a compressed bit representation of '<NUM>'.

In second to fifth compression processes <NUM>, <NUM>, <NUM>, and <NUM>, the compression unit 144b corresponding to Lane <NUM> does not output the compressed lane. In sixth compression process <NUM>, the compression unit 144b corresponding to Lane <NUM> outputs a compressed lane again, and the first concatenator <NUM> outputs a compressed bit representation of '<NUM>' by inserting a stop code '<NUM>' and a bit value '<NUM>' indicating that the stop code is inserted into the concatenated lane '<NUM>'.

In the second compression process <NUM>, the compression unit 144a corresponding to Lane <NUM> outputs a compressed lane of'<NUM>', and the compression unit 144b corresponding to Lane <NUM> does not output a compressed lane. Here, the compressed lane of'<NUM>' includes a stop code that has not inserted. Accordingly, the first concatenator <NUM> inserts a bit value '<NUM>' indicating that a stop code is not inserted into the concatenated lane '<NUM>' and outputs a compressed bit representation of '<NUM>'.

In a seventh compression process <NUM>, the compression unit 144a corresponding to Lane <NUM> outputs a compressed lane of '<NUM>', and the compression unit 144b corresponding to Lane <NUM> outputs a compressed lane of '<NUM>'. The first concatenator <NUM> concatenates the compressed lanes and outputs a compressed bit representation of '<NUM>'.

<FIG> is a block diagram for describing an encoder according to an example.

Referring to <FIG>, the first splitter <NUM> may further include an NS logic and a buffer. The NS logic may extract leading zero bits required for a Null Suppression (NS) technique and transfer the leading zero bits to the plurality of compression units 144a, 144b, and 144c. Bit representations input to the first splitter <NUM> may be buffered through a buffer.

The first concatenator <NUM> may further include a Mux and a stop code inserter. The Mux may concatenate compressed lanes, and the stop code insertion unit may insert stop codes into the concatenated lanes.

<FIG> is a diagram for describing a decoder <NUM> according to an example.

Referring to <FIG>, the decoder <NUM> (which may correspond to the decoder <NUM> of <FIG>) includes a second splitter <NUM>, a plurality of decompressors 184a, 184b and 184c, and a second concatenator <NUM>.

The decoder <NUM> may split compressed data of the neural network into a plurality of compressed lanes based on a predetermined optimal configuration, and decompress the neural network data by performing decompression techniques for each compressed lane. Here, the compressed data may denote data compressed by the encoder <NUM> described with reference to <FIG>, and the plurality of decompression techniques may denote the technique of decompression of data compressed by the compression techniques described with reference to <FIG>.

The decoder <NUM> may perform a function of decompression by inversely applying the compression techniques described with reference to <FIG>.

The second splitter <NUM> may obtain a predetermined optimal configuration to perform compression techniques for each lane by dividing neural network data into one or more lanes.

The second splitter <NUM> may obtain a compressed bit representation <NUM> of the compressed data of the neural network, and may split the compressed bit representation <NUM> into one or more compressed lanes based on the obtained optimal configuration. For example, the second splitter <NUM> may predict bit widths of the compressed lanes constituting the compressed bit representation <NUM> based on the optimal configuration, and may split the compressed bit representation <NUM> into one or more compressed lanes based on the predicted bit widths.

The optimal configuration obtained by the second splitter <NUM> may be the same optimal configuration used in the encoder <NUM> (refer to <FIG>). Accordingly, the second splitter <NUM> may predict bit widths of compressed lanes constituting the compressed bit representation <NUM> based on information on how the compressed lanes constituting the compressed bit representation <NUM> are compressed in the encoder <NUM>.

For example, referring again to <FIG>, it may be seen that Lane <NUM> is a lane having a bit width of <NUM> bits, ZVC is applied to Lane <NUM>, and compressed lanes corresponding to Lane <NUM> are <NUM> bit zero-value or a <NUM>-bit non-zero value. Lane <NUM> is a lane having a bit width of <NUM> bits, Z-RLC is applied to Lane <NUM>, and compressed lanes corresponding to Lane <NUM> are <NUM> bits or <NUM> bits. In other words, when each lane is compressed according to an optimal configuration, the second splitter <NUM> may know in advance the number of bit widths that each compressed data may have. The second splitter <NUM> may split the compressed bit representation <NUM> into one or more compressed lanes by predicting bit widths of the compressed lanes constituting the compressed bit representation <NUM> based on the number of bit widths that each compressed data may have.

Meanwhile, a method of predicting the bit widths of the compressed lanes constituting the compressed bit representation <NUM> by the second splitter <NUM> is not limited to the above description. The second splitter <NUM> may predict bit widths of the compressed lanes based on at least one of an order of concatenating compressed lanes constituting the compressed bit representations <NUM>, a stop code included in the compressed bit representation <NUM>, and an operation using a zero-test.

Referring to <FIG>, the second splitter <NUM> may check a stop code included in the compressed bit representation <NUM>. The second splitter <NUM> may check a bit value indicating whether the stop code is inserted or not, and delete the stop code according to the check result.

For example, when it is checked that the stop code is inserted, the second splitter <NUM> may delete the stop code and the bit value indicating that the stop code is inserted, and when it is checked that the stop code is not inserted, the second splitter <NUM> may delete only the bit value indicating that the code is not inserted.

The second splitter <NUM> may transfer the split compressed lanes to decompression units 184a, 184b and 184c. For example, the second splitter <NUM> may transmit each compressed lane to the decompression unit 184a that performs a decompression technique corresponding to each compressed lane.

The plurality of decompression units 184a, 184b, and 184c may be matched one-to-one with each compressed lane according to an optimal configuration. For example, the first decompression unit 184a may be matched one-to-one with a lane in which Lane <NUM> is compressed, and perform a first decompression technique, and the second decompression unit 184b may be matched one-to-one with a lane in which Lane <NUM> is compressed, and perform a second decompression technique.

The plurality of decompression units 184a, 184b, and 184c may decompress each of the split compressed lanes based on an optimum configuration and output the decompressed lanes. The decompressed lanes may be the same as one or more lanes split by the first splitter <NUM> described above with reference to <FIG>.

The second concatenator <NUM> may concatenate the decompressed lanes and output decompressed bit representations. The decompressed bit representations may be the same as those obtained by the first splitter <NUM> described above with reference to <FIG>.

<FIG> is a block diagram for describing a decoder according to an example.

Referring to <FIG>, the second splitter <NUM> may further include a buffer, a stop code detector, and a plurality of selectors (sel <NUM>, sel <NUM>, and sel N). The stop code detector may detect a stop code included in the compressed bit representation <NUM>. The plurality of selectors sel <NUM>, sel <NUM>, and sel N may sequentially predict a bit width of each of compressed lanes, and split the compressed lane into a plurality of compressed lanes. The second concatenator <NUM> may further include a recombiner and a buffer.

<FIG> is a Table <NUM> for explaining statistical characteristics of neural network data according to an example.

Referring to <FIG>, Table <NUM> shows results of analyzing statistical characteristics of neural network data (activation and weight for inference, and activation, weight, and gradient for re-train) from all layers (convolutional layers, fully connected layers, and auxiliary layers for activation function, normalization, and polling) of <NUM> different neural networks (LeNet-<NUM>, CifarNet1, ResNet-<NUM>, SqueezeNet, MobileNet, AlexNet, and LSTM network).

Various neural networks commonly have high sparsity. Redundancy used for compression of neural network data may be sparsity of values and bits. A value sparsity may refer to a ratio of zero-value symbols in a data set, and a bit sparsity may refer to a ratio of zero bits in a binary representation.

Referring to Table <NUM>, many neural network data sources not only have a high value-level sparsity, but also neural network data with a low value-level sparsity have a high bit-level of sparsity. For example, a weight for inferring LeNet-<NUM> has a low value-level sparsity of <NUM>%, but has a high bit-level sparsity of <NUM>%.

In this way, all hidden bit-level sparsity may be exposed by splitting different neural network data into bit segments or lanes.

Accordingly, the compression method according to the examples may be generally applied to various neural network data regardless of the type of neural network, layer type, learning model, and type of input data.

<FIG> is a graph <NUM> for comparing compression rates according to an example.

Referring to <FIG>, compression rates of a network, a data source, and an input data set compressed by the compression method according to the examples may be compared with a Shannon limit. Each bar shown in the graph <NUM> represents an average of compression rates for each network, data source, and input data set, and error bars represent minimum and maximum values. Referring to the graph <NUM>, it may be seen that various data may be compressed close to the Shannon limit by using the compression method according to the examples.

<FIG> is a block diagram illustrating a configuration of an electronic system <NUM> according to an example.

Referring to <FIG>, the electronic system <NUM> may extract valid information by analyzing input data in real time based on a neural network and determine a situation or control the configuration of a device on which the electronic system <NUM> is mounted based on the extracted information. For example, the electronic system <NUM> may be applied to a robotic device, such as a drone or an advanced driver assistance system (ADAS), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measurement device, an loT device and may be mounted on at least one of various types of electronic devices.

The electronic system <NUM> may include a processor <NUM>, a RAM <NUM>, a neural network device <NUM>, a memory <NUM>, a sensor module <NUM>, and a communication module <NUM>. The electronic system <NUM> may further include an input/output module, a security module, and a power control device. Some of hardware components of the electronic system <NUM> may be mounted on at least one semiconductor chip.

The processor <NUM> controls an overall operation of the electronic system <NUM>. The processor <NUM> may include a single processor core (Single Core), or a plurality of processor cores (Multi-Core). The processor <NUM> may process or execute programs and/or data stored in the memory <NUM>. In some embodiments, the processor <NUM> may control functions of the neural network device <NUM> by executing programs stored in the memory <NUM>. The processor <NUM> may be implemented by a CPU, GPU, AP, etc..

The RAM <NUM> may temporarily store programs, data, or instructions. For example, programs and/or data stored in the memory <NUM> may be temporarily stored in the RAM <NUM> according to the control or booting code of the processor <NUM>. The RAM <NUM> may be implemented as a memory, such as dynamic RAM (DRAM) or static RAM (SRAM).

The neural network device <NUM> may perform an operation of the neural network based on received input data and generate an information signal based on the execution result. Neural networks may include convolution neural networks (CNN), recurrent neural networks (RNN), feedforward Neural Network (FNN), deep belief networks, restricted Boltzmann machines, etc., but are not limited thereto. The neural network device <NUM> may be a hardware accelerator itself dedicated to a neural network or an apparatus including the same. The neural network device <NUM> may perform a read or write operation as well as an operation of a neural network.

The neural network device <NUM> may perform an operation of a neural network based on received input data, and may generate an information signal based on the operation result. Neural networks may include CNN, RNN, deep belief networks, restricted Boltzmann machines, etc., but are not limited thereto. The neural network device <NUM> is hardware that processes the neural network data described above, and may correspond to a hardware accelerator dedicated to the neural network described above. The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object recognition signal, an image recognition signal, and a biometric information recognition signal. For example, the neural network device <NUM> may receive frame data included in a video stream as input data and generate, on the basis of the frame data, a recognition signal with respect to an object included in an image displayed by the frame data. However, the present inventive concept is not limited thereto, and the neural network device <NUM> may receive various types of input data according to the type or function of an electronic device on which the electronic system <NUM> is mounted and generate a recognition signal according to the input data.

The memory <NUM> is a storage for storing data and may store an operating system (OS), various programs, and various data. In an embodiment, the memory <NUM> may store intermediate results generated in a process of performing an operation of the neural network device <NUM>.

The memory <NUM> may be DRAM, but is not limited thereto. The memory <NUM> may include at least one of volatile memory and nonvolatile memory. The non-volatile memory includes ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, RRAM, FRAM, etc. The volatile memory includes DRAM, SRAM, SDRAM, PRAM, MRAM, RRAM, FeRAM, etc. In an embodiment, the memory <NUM> may include at least one of HDD, SSD, CF, SD, Micro-SD, Mini-SD, xD and Memory Stick.

The sensor module <NUM> may collect information around an electronic device on which the electronic system <NUM> is mounted. The sensor module <NUM> may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a bio signal, a touch signal, etc.) from the outside of the electronic device and convert the sensed or received signal into data. To this end, the sensor module <NUM> may include at least one of various types of sensing devices, for example, a microphone, an imaging device, an image sensor, a light detection and ranging (LiDAR) sensor, an ultrasonic sensor, an infrared sensor, a bio sensor, and a touch sensor, etc..

The sensor module <NUM> may provide converted data as input data to the neural network device <NUM>. For example, the sensor module <NUM> may include an image sensor, generate a video stream by photographing an external environment of the electronic device, and sequentially provide successive data frames of the video stream to the neural network device <NUM> as input data. However, the configuration is not limited thereto, and the sensor module <NUM> may provide various types of data to the neural network device <NUM>.

The communication module <NUM> may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module <NUM> may include a local area network (LAN), a wireless local area network (WLAN), such as Wi-Fi, a wireless personal area network (WPAN), such as Bluetooth, a wireless universal serial bus (USB), ZigBee, near-field communication (NFC), radio-frequency identification (RFID), power-line communication (PLC), or a communication interface capable of connecting to a mobile cellular network, such as 3rd generation (<NUM>), 4th generation (<NUM>), long-term evolution (LTE), or 5th generation (<NUM>).

<FIG> is a flowchart of a method of processing data of a neural network in a neural network apparatus according to the present invention. The method of processing data of a neural network shown in <FIG> is related to the examples described with reference to the drawings described above, and thus, the descriptions given with respect to the preceding drawings, even though omitted below, may be applied to the method of <FIG>.

In operation <NUM>, the processor <NUM> obtains one or more bit representations of data used for processing a neural network.

In operation <NUM>, the processor <NUM> generates a plurality of candidate profiles by dividing one or more bit representations of the obtained data into one or more lanes and applying compression techniques to each lane.

In operation <NUM>, the processor <NUM> determines a final profile by comparing compression performances for each of the candidate profiles.

In operation <NUM>, the processor <NUM> determines one or more divided lanes and compression techniques used in the determined final profile as an optimal configuration for compressing data of the neural network.

The inventive concept is implemented as a computer-readable program, and may be realized in general computers that execute the program by using non-transitory computer-readable recording media. In addition, the structure of data used in the examples of the inventive concept may be recorded on a non-transitory computer-readable recording medium through various means. The non-transitory computer-readable medium may be magnetic storage media (e.g., ROM, floppy disks, hard disks, etc.) and optical recording media (e.g., CD-ROMs or DVDs).

While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the scope of the claims. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples.

Claim 1:
A method of processing data of a neural network (<NUM>), comprising:
obtaining (<NUM>) bit representations (<NUM>, <NUM>, <NUM>) of neural network data, wherein each of the obtained bit representations of the neural network data is a bit stream having a predetermined number of bits;
for each obtained bit representation, generating (<NUM>) a plurality of candidate profiles (<NUM>, <NUM>, <NUM>, <NUM>) for being selected as a final profile by dividing the respective bit representation (<NUM>, <NUM>, <NUM>) into lanes, each lane of the respective bit representation denoting bit segments having a predetermined bit width generated by applying different splitting methods for splitting the bit stream, and by applying,
for each candidate profile (<NUM>, <NUM>, <NUM>, <NUM>) of the related bit representation, different compression techniques to each of the lanes;
determining (<NUM>) a final profile among the plurality of candidate profiles (<NUM>, <NUM>, <NUM>, <NUM>) of the respective bit representation by calculating compression rates corresponding to each of the candidate profiles for the respective bit representation (<NUM>, <NUM>, <NUM>), comparing the calculated compression rates for each of the candidate profiles, and selecting a candidate profile having the greatest compression rate among the calculated compression rates as the final profile; and
determining (<NUM>) the splitting methods and compression techniques of the lanes used in the selected final profile for compressing data of the neural network,
wherein the candidate profiles (<NUM>, <NUM>, <NUM>, <NUM>) comprise profiles according to which splitting methods in which the number of lanes for dividing the bit representations (<NUM>, <NUM>, <NUM>) into a plurality of bit segments and bit widths of the bit segments corresponding to each of the lanes are differently set from each other, are applied.