Patent Description:
A massive MIMO (multiple-input, multiple-output) base station provides two-way, multiplexed communications to a plurality of wireless devices (i.e., user equipment) within a cell that is serviced by the base station. A typical base station includes a remote radio unit (or remote radio head) connected to an array of antenna elements (e.g., tens to hundreds of antennas) that are configured to communicate over the air interface with the wireless devices. The remote radio unit includes a transceiver front end with an array of transceivers, where each transceiver is coupled to one of the antennas in the antenna array (i.e., there is a <NUM>:<NUM> correlation between transceivers and antenna elements). For example, a typical massive MIMO transceiver array may include anywhere from <NUM> transceivers (e.g., in an 8x8 array, also referred to as an 8T or 8T8R array) up to <NUM> transceivers (e.g., in a 64x64 transceiver array, also referred to as a 64T or 64T64R array), although smaller and larger antenna and transceiver arrays have been contemplated, as well. Given the complexity inherent in such large numbers of transceivers in a massive MIMO transceiver array, system designers continuously strive to achieve high performance systems that meet increasingly stringent size and power consumption requirements.

An embodiment of a multiple-stage amplifier is provided in claim <NUM>. Further embodiments are defined in dependent claims <NUM> to <NUM>.

<FIG> is a simplified diagram of a portion of a massive MIMO system <NUM> with an 8T transceiver array, in accordance with an embodiment. System <NUM> includes a baseband and intermediate frequency (IF) subsystem <NUM>, a transceiver array <NUM>, and an antenna array <NUM>. System <NUM> may be implemented, for example, in a cellular base station, although system <NUM> alternatively may be implemented in another type of wireless system other than a base station, as well.

The baseband and IF subsystem <NUM> is configured to perform baseband and IF processing on a plurality of signals for transmission ("TX signals," herein), and to provide those signals over a plurality of conductors <NUM> to the transceiver array <NUM>. In addition, the baseband and IF subsystem <NUM> is configured to receive and process a plurality of signals ("RX signals," herein) from the transceiver array <NUM> via the plurality of conductors <NUM>. For example, the plurality of conductors <NUM> may include a plurality of coaxial cables or other conductors.

The transceiver array <NUM> includes a plurality of identical transceivers <NUM>, which may be arranged in a plurality of rows and a plurality of columns in the transceiver array <NUM>. In some embodiments, all of the transceivers <NUM> in the array <NUM> may be coupled to a common transceiver array substrate <NUM> (e.g., a multiple-layer printed circuit board (PCB) or other type of substrate), which includes a plurality of transceiver sockets into which the transceivers <NUM> are inserted, or a plurality of transceiver mounting areas to which the transceivers <NUM> are coupled (e.g., soldered). In the illustrated embodiment, the transceiver array <NUM> includes <NUM> rows and <NUM> columns of transceivers <NUM>, for a total of <NUM> transceivers <NUM> in the array <NUM>. In other embodiments, the number of rows and/or columns of transceivers may be smaller or larger, and/or the number of rows may be different from the number of columns. In still other embodiments, sub-arrays of the transceivers <NUM> may be coupled to distinct transceiver substrates. To avoid cluttering <FIG>, only one connection between a connector <NUM> and a transceiver <NUM> is shown in the upper left corner of the transceiver array <NUM>. Those of skill in the art would understand, based on the description herein, that the transceiver array <NUM> may include a dedicated connection between each connector <NUM> and each transceiver <NUM>.

The transceiver array <NUM> is electrically coupled to antenna array <NUM>, which includes a plurality of antennas <NUM>. According to an embodiment, the system <NUM> is a time division duplex (TDD) system, and each antenna <NUM> is configured both to transmit radio frequency (RF) signals over the air interface ("RF TX signals," herein), and also to receive RF signals from the air interface ("RF RX signals," herein). In such an embodiment, each transceiver <NUM> in the transceiver array <NUM> is coupled to a different one of the antennas <NUM> in the antenna array <NUM> (i.e., there is a <NUM>:<NUM> correlation between the number of transceivers <NUM> and the number of antennas <NUM>). To avoid cluttering <FIG>, only one connection between a transceiver <NUM> and an antenna <NUM> is shown in the upper right corner of the transceiver array <NUM>. Those of skill in the art would understand, based on the description herein, that the transceiver array <NUM> may include a dedicated connection between each transceiver <NUM> and each antenna <NUM>.

As will be described in more detail in conjunction with <FIG>, later, each transceiver <NUM> includes a transmitter (e.g., transmitter <NUM>, <FIG>), a receiver (e.g., receiver <NUM>, <FIG>), and a transmit/receive (TX/RX) switch (e.g., TX/RX switch <NUM>, <FIG>). As will be explained in more detail in conjunction with <FIG>, later, the transmitter of each transceiver <NUM> includes one or more multiple-stage amplifiers (e.g., multiple-stage amplifier <NUM>, <FIG>), where each multiple-stage amplifier includes a driver stage amplifier (e.g., driver stage amplifier <NUM>, <FIG>) coupled in series with a final stage amplifier (e.g., final stage amplifier <NUM>, <FIG>). For example, both the driver stage amplifier and the power stage amplifier may be implemented using a field effect transistor (FET). In a particular embodiment, the driver stage amplifier FET and the final stage amplifier FET have significantly different power densities, and may be implemented using different semiconductor technologies on distinct semiconductor dies (e.g., dies <NUM>, <NUM>, <FIG>). For example, the driver stage FET may be a silicon-based FET, and the final stage FET may be a III-V semiconductor-based FET.

Each amplification stage of each multiple-stage amplifier receives one or more DC bias voltages from one or more external voltage sources. According to a particular embodiment, the driver stage amplifier FET and the final stage amplifier FET of each transceiver <NUM> receive a same output (e.g., drain) DC bias voltage ("output/drain bias voltage," herein), even though the driver and final stage amplifier FETs have significantly different power densities and may be implemented using different semiconductor technologies. According to a further embodiment, the output/drain bias voltage for the driver and final stage amplifier FETs of all transceivers <NUM> in the transceiver array <NUM> may be provided by a single, external DC drain bias voltage source <NUM> through a network of interconnected bias supply lines <NUM> that are coupled to the transceiver array substrate <NUM>. For example, the DC drain bias voltage source <NUM> may be configured to provide an output/drain bias voltage in a range of about <NUM> volts (V) to about <NUM> V (e.g., an output/drain bias voltage of about <NUM> V), although the output/drain bias voltage may be lower or higher, as well. Although not illustrated in <FIG>, additional DC bias and other voltages also may be supplied to the transceivers <NUM> in the transceiver array <NUM>, including, for example, one or more input (e.g., gate) DC bias voltages ("input/gate bias voltage," herein) for each transmitter's driver stage amplifier FET and final stage amplifier FET. To avoid cluttering <FIG>, those additional DC voltage sources and bias/supply lines are not illustrated.

<FIG> is a simplified block diagram of a transceiver <NUM> (e.g., transceiver <NUM>, <FIG>) suitable for use in a massive MIMO transceiver array (e.g., transceiver array <NUM>, <FIG>), in accordance with an embodiment. Transceiver <NUM> includes a transmitter <NUM>, a receiver <NUM>, and a TX/RX switch <NUM>. The transmitter <NUM> and the receiver <NUM> each are coupled between a baseband and IF subsystem <NUM> (e.g., system <NUM>, <FIG>) and an antenna <NUM> (e.g., one of antennas <NUM>, <FIG>). The baseband and IF subsystem <NUM> includes a transmit (TX) signal processor <NUM> and a receive (RX) signal processor <NUM>, which are coupled to the input <NUM> of transmitter <NUM> and the output <NUM> of receiver <NUM>, respectively.

Transceiver system <NUM> is a half-duplex transceiver configured to support TDD communications. Accordingly, only one of the transmitter <NUM> or the receiver <NUM> are coupled, through the TX/RX switch <NUM>, to the antenna <NUM> at any given time. More specifically, the state of the TX/RX switch <NUM> is controlled (e.g., by switch controller <NUM>, <FIG>) to alternate between a transmit state in which the switch <NUM> couples an RF TX signal produced by the transmitter <NUM> to the antenna <NUM>, or a receive state in which the switch <NUM> couples an RF RX signal received by the antenna <NUM> to the receiver <NUM>.

The transmit signal processor <NUM> is configured to produce transmit signals, and to provide the transmit signals through input <NUM> to the transmitter <NUM>. For example, the transmitter <NUM> may include a pre-amplifier <NUM> and a power amplifier <NUM>. The pre-amplifier <NUM> modestly amplifies the transmit signal provided by the transmit signal processor <NUM>. The power amplifier <NUM> further amplifies the transmit signal, and provides the amplified TX RF signal to the TX/RX switch <NUM>. As will be described in more detail later, the power amplifier <NUM> includes a multiple-stage amplifier with a driver stage amplifier FET and a final stage amplifier FET, which receive a same output/drain bias voltage. For example, the output/drain bias voltage may be supplied by DC drain bias voltage source <NUM> (e.g., DC drain bias voltage source <NUM>, <FIG>), which is connected to the power amplifier <NUM> (and more particularly to the outputs of the driver and final stage amplifier FETs within the power amplifier <NUM>) through DC bias input <NUM>. When transceiver <NUM> is included within a transceiver array, such as transceiver array <NUM>, <FIG>, the DC bias input <NUM> may be connected, for example, to the previously-discussed network of interconnected bias supply lines <NUM> that are coupled to the transceiver array substrate <NUM>.

The receiver <NUM> may include, for example, a receive amplifier <NUM> (e.g., a low noise amplifier). The receive amplifier <NUM> is configured to amplify relatively low power RF RX signal received from the TX/RX switch <NUM>, and to provide the amplified received signal to the receive signal processor <NUM> through output <NUM>. The receive signal processor <NUM> is configured to consume or process the receive signals.

During each transmit time interval, the TX/RX switch <NUM> is controlled to be in a first or "transmit" state, as depicted in <FIG>, in which a transmit signal path is closed between transmitter node <NUM> and antenna node <NUM>, and in which a receive signal path is open between antenna node <NUM> and receiver node <NUM>. Conversely, during each receive time interval, the TX/RX switch <NUM> is controlled to be in a second or "receive" state, in which the receive signal path is closed between antenna node <NUM> and receiver node <NUM>, and in which the transmit signal path is open between transmitter node <NUM> and antenna node <NUM>.

As will be described in more detail in conjunction with <FIG>, below, the RF transceiver <NUM> may be physically implemented using a variety of active and passive ICs, modules, and electrical components. For example, the various components of the RF transceiver <NUM> may be implemented in a self-contained module or packaged electrical device, which may be coupled to a transceiver substrate (e.g., transceiver substrate <NUM>, <FIG>) along with a plurality of other transceiver modules or devices. As used herein, the term "transceiver device" means a set of active and/or passive electrical devices (e.g., ICs, modules, and electrical components) that together constitute a transceiver (e.g., transceiver <NUM>, <NUM>, <FIG>, <FIG>), and that are physically contained within a single housing (e.g., a device package) or that are physically coupled to a common substrate (e.g., a PCB). A "transceiver device" also includes a plurality of conductive terminals for electrically connecting the set of devices to external circuitry that forms other portions of an electrical system (e.g., baseband and IF subsystem <NUM>, <NUM>, bias voltage source <NUM>, <NUM>, and antennas <NUM>, <NUM>, <FIG>, <FIG>). For example, in various embodiments, a transceiver device may be in the form of a PCB-based module, a surface mount module, a chip carrier device, a ball, pin, or land grid array device, a flat package (e.g., a quad or dual flat package) device, a chip scale packaged device, a system-in-package (SiP) device, or in the form of some other type of integrated circuit package. Although a particular type of transceiver device is described below, it is to be understood that embodiments of the inventive subject matter may be included in other types of transceiver devices, as well.

For example, <FIG> is a top view of a transceiver device <NUM> (e.g. an instance of a transceiver <NUM>, <FIG>) that embodies the RF transceiver <NUM> of <FIG>, in accordance with an embodiment. Device <NUM> is implemented as a PCB-based module, in accordance with the illustrated example embodiment, although device <NUM> may be packaged in other types of packages or modules, as well (e.g., a quad-flat no-leads (QFN) device, or another type of device). In any event, device <NUM> includes a substrate <NUM>, which may include, for example, a plastic substrate, a single- or multi-layer PCB, a conductive flange, and/or another rigid structure.

Device <NUM> also includes a plurality of components coupled to the substrate <NUM>, including a transmit pre-amplifier module <NUM> (e.g., embodying pre-amplifier <NUM>, <FIG>), a transmit amplifier module <NUM> (e.g., embodying transmit amplifier <NUM>, <FIG>), a receive amplifier module <NUM> (e.g., embodying receive amplifier <NUM>, <FIG>), and a TX/RX switch module or duplexer <NUM> (e.g., embodying TX/RX switch <NUM>, <FIG>). In addition, device <NUM> also includes a plurality of connectors (or terminals or leads), which are configured to provide electrical connectivity between electrical systems external to device <NUM> and the transceiver components housed by the device <NUM>. For example, the connectors (or leads or terminals) may include one or more ground connectors <NUM>, a transmit signal input connector <NUM> (e.g., transmitter input <NUM>, <FIG>), a receive signal output connector <NUM> (e.g., receiver output <NUM>, <FIG>), an antenna/load connector <NUM> (e.g., antenna terminal <NUM>, <FIG>), a first DC bias voltage connector <NUM> (e.g., DC bias input <NUM>, <FIG>), and one or more additional power and/or DC bias voltage connectors <NUM>. The various modules <NUM>, <NUM>, <NUM>, <NUM> and connectors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are electrically connected together through a plurality of conductive electrical features (e.g., including conductive traces <NUM>, <NUM> and other conductive features). In other embodiments, various ones of the modules <NUM>, <NUM>, <NUM>, <NUM> and connectors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be electrically connected together using other conductive structures. In various embodiments, the device <NUM> may contained within an air cavity or overmolded (e.g., encapsulated), although the device <NUM> may be considered to be complete without such containment, as well.

After incorporation of device <NUM> into a transceiver array (e.g., transceiver array <NUM>, <FIG>), and during operation of the transceiver system, bias and ground reference voltages may be provided to device <NUM> through bias and ground terminals <NUM>, <NUM>, <NUM>. As mentioned above, and as will be described in more detail in conjunction with <FIG>, for example, the amplifier module <NUM> includes at least one multiple-stage amplifier with a driver stage amplifier FET and a final stage amplifier FET, which are configured to receive a same output/drain DC bias voltage through bias voltage connector <NUM> and conductive trace <NUM>, which may be coupled to an external DC drain bias voltage source (e.g., DC drain bias voltage source <NUM>, <NUM>, <FIG>, <FIG>). The transmit pre-amplifier module <NUM> and/or the receive amplifier module <NUM> may receive one or more other bias and/or operational DC voltages through voltage connector <NUM> and conductive traces <NUM>, which may be coupled to another external DC voltage source (not illustrated).

The TX/RX duplexer <NUM> may operate in a transmit state or a receive state at any given time. When the TX/RX duplexer <NUM> is operating the transmit state, transmit signals received through the transmit signal input connector <NUM> and amplified by the pre-amplifier and power amplifier modules <NUM>, <NUM> are passed through the TX/RX duplexer <NUM> to the antenna connector <NUM>. Conversely, when the TX/RX duplexer <NUM> is operating in the receive state, signals received from the antenna connector <NUM> are passed through the TX/RX duplexer <NUM> to the receive amplifier module <NUM>, which amplifies the received signals and provides the amplified received signals to the receive signal output connector <NUM>.

As discussed previously, the transmit power amplifier (e.g., amplifier <NUM> or amplifier module <NUM>, <FIG>, <FIG>) includes at least one multiple-stage amplifier. <FIG> and <FIG> illustrate a simplified block diagram of a multiple-stage amplifier <NUM>, and a circuit diagram of a multiple-stage amplifier <NUM>, respectively, which may be included within a transmit amplifier or module (e.g., amplifier <NUM> or module <NUM>, <FIG>, <FIG>) and/or a transceiver (e.g., transceiver <NUM>, <NUM>, <FIG>, <FIG>), in accordance with various embodiments.

Briefly, each of the multiple-stage amplifiers <NUM>, <NUM> in <FIG> and <FIG> include a driver stage amplifier <NUM>, <NUM> coupled in series with a final stage amplifier <NUM>, <NUM>. According to an embodiment, both the driver stage amplifier <NUM>, <NUM> and the final stage amplifier <NUM>, <NUM> include a field effect transistor (FET) <NUM>, <NUM>, <NUM>, <NUM>, although the power densities between the driver stage amplifier <NUM>, <NUM> and the final stage amplifier <NUM>, <NUM> are significantly different. In a particular embodiment, the driver stage amplifier FET <NUM>, <NUM> and the final stage amplifier FET <NUM>, <NUM> are implemented using different semiconductor technologies on distinct semiconductor dies. For example, the driver stage FET may be a silicon-based FET, and the final stage FET may be a III-V semiconductor-based FET. In alternate embodiments, either the driver stage FET or the final stage FET may be implemented using technologies other than silicon or GaN, or the driver stage FET and the final stage FET may be implemented using the same semiconductor technology, as long as the power density of the two devices is significantly different.

According to a particular embodiment, the driver stage amplifier FET <NUM>, <NUM> and the final stage amplifier FET <NUM>, <NUM> each receive a same output/drain DC bias voltage from a DC drain bias voltage source <NUM>, <NUM> (e.g., DC drain bias voltage source <NUM>, <NUM>, <FIG>, <FIG>), even though the driver and final stage amplifier FETs <NUM>, <NUM>, <NUM>, <NUM> have different power densities and may be implemented using different semiconductor technologies. For example, the DC drain bias voltage source <NUM>, <NUM> may be configured to provide an output/drain bias voltage in a range of about <NUM> V to about <NUM> V (e.g., an output/drain bias voltage of about <NUM> V), although the output/drain bias voltage may be lower or higher, as well.

Referring first to <FIG>, a simplified block diagram of a two-stage amplifier <NUM> is illustrated, which includes a driver stage IC die <NUM> and a final stage IC die <NUM> electrically coupled together in a cascade arrangement between an RF signal input terminal <NUM> and an RF signal output terminal <NUM>, in accordance with an example embodiment. The essential components of the two-stage amplifier <NUM> include a series-coupled combination of a driver stage transistor <NUM> in the driver stage IC die <NUM>, an interstage impedance matching circuit <NUM>, and a final stage transistor <NUM> in the final stage IC die <NUM>.

The driver stage IC die <NUM> includes an input terminal <NUM>, an output terminal <NUM>, an input impedance matching circuit <NUM>, and the driver stage transistor <NUM>. According to an embodiment, the driver stage IC die <NUM> also includes an integrated portion of the interstage impedance matching circuit <NUM> electrically coupled between the driver stage transistor <NUM> and the output terminal <NUM> of the driver stage IC die <NUM>. The final stage IC die <NUM> includes an input terminal <NUM>, an output terminal <NUM>, and a final stage transistor <NUM>, in an embodiment. An inductive connection <NUM> (e.g., wirebonds) is electrically coupled between the output terminal <NUM> of the driver stage IC die <NUM> and the input terminal <NUM> of the final stage IC die <NUM>.

In the embodiments illustrated in <FIG> and <FIG>, the interstage impedance matching circuit <NUM> includes a plurality of components that are integrally formed in the driver stage IC die <NUM> (referred to as an "integrated portion" of the interstage impedance matching circuit <NUM>), along with an inductive connection <NUM> between the driver and final stage dies <NUM>, <NUM>. In other embodiments, all of portions of the interstage impedance matching circuit <NUM> may be implemented separately from the driver stage IC die <NUM>. For example, the components of the interstage impedance matching circuit <NUM> may be implemented using a separate integrated passive device (IPD) positioned between the driver and final stage dies <NUM>, <NUM>, along with inductive connections (e.g., wirebonds) from the driver stage die <NUM> to the IPD, and from the IPD to the final stage die <NUM>. In still other embodiments, the interstage impedance matching circuit <NUM> may include an inductive connection (e.g., wirebonds) between the driver stage IC die <NUM> and the final stage IC die <NUM>, along with a plurality of components that are integrally formed in the final stage IC die <NUM>. Although only the illustrated embodiment is described in detail, below, the various alternate embodiments mentioned above are intended to be included in the scope of the inventive subject matter.

Along a forward amplification path, the RF signal input terminal <NUM> is electrically coupled to the input terminal <NUM> of the driver stage IC die <NUM> through connection <NUM> (e.g., a wirebond, wirebond array, or other electrical connection), the input terminal <NUM> is coupled to the input impedance matching circuit <NUM>, the input impedance matching circuit <NUM> is coupled to an input <NUM> (e.g., gate or control terminal) of the driver stage transistor <NUM>, an output <NUM> (e.g., a drain or first current-conducting terminal) of the driver stage transistor <NUM> is coupled to the integrated portion of the interstage impedance matching circuit <NUM>, and the integrated portion of the interstate impedance matching circuit <NUM> is coupled to the output terminal <NUM>.

The output terminal <NUM> of driver stage die <NUM> is electrically coupled through a connection <NUM> (e.g., a wirebond array or other conductive connection) to the input terminal <NUM> of the final stage IC die <NUM>. The connection <NUM> represents a non-integrated portion of the interstage matching circuit between the output (e.g., drain terminal) of the driver stage transistor <NUM> and the input (e.g., gate terminal) of the final stage transistor <NUM>. Continuing along the forward amplification path, the input terminal <NUM> of the final stage IC die <NUM> is coupled to an input <NUM> (e.g., gate or control terminal) of the final stage transistor <NUM>, and an output <NUM> (e.g., drain or first current-conducting terminal) of the final stage transistor <NUM> is coupled to the output terminal <NUM>. The output terminal <NUM> is electrically coupled through connection <NUM> (e.g., a wirebond array or other electrical connection) to the RF signal output terminal <NUM>.

During operation, an RF signal received through the RF signal input terminal <NUM> and the driver stage die input terminal <NUM> is conveyed through the input impedance matching circuit <NUM>, which is configured to raise the impedance of the amplifier <NUM> to a higher impedance level (e.g., <NUM> Ohms or another impedance level) to enhance gain flatness and power transfer across the frequency band. The resulting RF signal is then amplified by the driver stage transistor <NUM> (i.e., the driver stage transistor <NUM> functions as a driver amplifier, which applies a first gain to the RF signal). For example, the driver stage transistor <NUM> may apply a gain in a range of about <NUM> decibels (dB) to about <NUM> dB to the RF signal (e.g., about <NUM> dB, in some embodiments), although the gain applied by the driver stage transistor <NUM> may be lower or higher, as well.

The amplified RF signal produced at the output <NUM> of the driver stage transistor <NUM> is then conveyed through the integrated portion of the interstage impedance matching circuit <NUM>. The resulting RF signal produced at output terminal <NUM> is then conveyed through the connection <NUM> to the input terminal <NUM> of the final stage IC die <NUM>. The integrated portion of the interstage impedance matching circuit <NUM> and the connection <NUM> between the die <NUM>, <NUM> together are configured to match the output impedance (or drain impedance) of the driver stage transistor <NUM> with the input impedance of the final stage transistor <NUM> to enhance gain flatness and power transfer across the frequency band. In some embodiments, the connection <NUM> is a non-integrated, series inductive component in the interstage matching circuit between the output of the driver stage transistor <NUM> and the input <NUM> of the final stage transistor <NUM>.

The pre-amplified RF signal received at the input terminal <NUM> of the final stage IC die <NUM> is amplified by the final stage transistor <NUM> (i.e., the final stage transistor <NUM> functions as a final amplifier, which applies a second gain to the RF signal). For example, the final stage transistor <NUM> may apply a gain in a range of about <NUM> dB to about <NUM> dB to the RF signal (e.g., about <NUM> dB, in some embodiments), yielding a total gain through the device <NUM> in a range of about <NUM> dB to about <NUM> dB (e.g., about <NUM> dB, in some embodiments), although the gain applied by the final stage transistor <NUM> and/or the total device gain may be lower or higher, as well. The amplified RF signal produced at the output <NUM> of the final stage transistor <NUM> is then conveyed through the output terminal <NUM> and the connection <NUM> to the RF signal output terminal <NUM>.

According to a specific embodiment, the power transistor <NUM> includes a silicon laterally-diffused, metal oxide semiconductor (LDMOS) field effect transistor, which has a power density in a range of about <NUM> watts/millimeter (W/mm) to about <NUM> W/mm (e.g., about <NUM> W/mm). Further, according to a specific embodiment, the power transistor <NUM> includes a GaN-based high electron mobility transistor (HEMT), which has a power density in a range of about <NUM> W/mm to about <NUM> W/mm (e.g., about <NUM> W/mm) and an input impedance in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms), although the input impedance could be smaller or larger, as well. Although either power transistor <NUM> or power transistor <NUM> could be implemented using a semiconductor technology other than silicon LDMOS or GaN HEMT, respectively (including using the same semiconductor technology), an important aspect of the present invention is that the power densities of the driver stage transistor <NUM> and the final stage transistor <NUM> are significantly different. More particularly, the power density of the driver stage transistor <NUM> is significantly lower than the power density of the final stage transistor <NUM> (or conversely, the power density of the final stage transistor <NUM> is significantly higher than the power density of the driver stage transistor <NUM>). According to an embodiment, a ratio of the power density of the driver stage transistor <NUM> to the power density of the final stage transistor <NUM> is in a range of <NUM>:<NUM> to <NUM>:<NUM> (e.g., <NUM>:<NUM>). For example, the power density ratio would be <NUM>:<NUM> when the driver stage transistor <NUM> has a power density of <NUM> W/mm and the final stage transistor has a power density of <NUM> W/mm.

According to another specific embodiment, both power transistors <NUM>, <NUM> are configured to have an output impedance and a breakdown voltage that is appropriate to support operation using the same drain bias voltage. For example, the driver stage transistor <NUM> may have a real portion of an output impedance in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms), and the final stage transistor <NUM> may have a real portion of an output impedance in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms). As will be discussed in more detail later, the interstage impedance matching circuit <NUM> (including connection <NUM>) is configured to provide an impedance transformation between the output impedance of the driver stage transistor <NUM> and the input impedance of the final stage transistor <NUM>.

Biasing of the driver and final stage IC dies <NUM>, <NUM> will now be described. According to an embodiment, the driver stage IC die <NUM> further includes an integrated bias circuit <NUM> (or "driver stage drain bias circuit"), which is configured to convey a bias voltage to the output <NUM> (e.g., the drain terminal) of the driver stage transistor <NUM>. More specifically, the driver stage IC die <NUM> includes a bias circuit input terminal <NUM> (referred to simply as "bias input terminal"), and the bias voltage control circuit <NUM> electrically coupled between the bias input terminal <NUM> and the output terminal <NUM> of the driver stage transistor <NUM>.

Similarly, the final stage IC die <NUM> further includes an integrated bias circuit <NUM> (or "final stage drain bias circuit"), which is configured to convey a bias voltage to the output <NUM> (e.g., the drain terminal) of the final stage transistor <NUM>. More specifically, the final stage IC die <NUM> includes a bias input terminal <NUM>, and the integrated bias circuit <NUM> electrically coupled between the bias input terminal <NUM> and the output terminal <NUM> of the final stage transistor <NUM>.

The integrated bias circuits <NUM>, <NUM> (and more specifically the bias input terminals <NUM>, <NUM>) are both electrically connected to the DC drain bias voltage source <NUM> (e.g., DC drain bias voltage source <NUM>, <NUM>, <FIG>, <FIG>), in an embodiment, to receive the same output/drain DC bias voltage. In an alternate embodiment, as indicated by the dashed line in <FIG>, the output/drain DC bias voltage for the final stage transistor <NUM> may be supplied through output terminal <NUM>, connection <NUM>, and output terminal <NUM>.

In addition to drain bias circuits and a drain bias voltage source (e.g., circuits <NUM>, <NUM> and voltage source <NUM>), amplifier <NUM> also may include one or more gate bias circuits <NUM>, <NUM>, which are coupled (e.g., through bias input terminals <NUM>, <NUM>, respectively) to one or more DC gate bias voltage sources <NUM>, <NUM>. For example, DC gate bias voltage source <NUM> may provide a DC bias voltage through input terminal <NUM> and driver stage gate bias circuit <NUM> to the input <NUM> (e.g., gate terminal) of driver stage transistor <NUM>. For example, the DC gate bias voltage for the driver stage, Vg1, may have a positive value up to about <NUM> V or more (e.g., about <NUM> V). DC gate bias voltage source <NUM> may provide a DC bias voltage through input terminal <NUM> and final stage gate bias circuit <NUM> to the input <NUM> (e.g., gate terminal) of final stage transistor <NUM>. When the final stage transistor <NUM> is a depletion-mode, normally-on III-V device, the received and conveyed gate bias voltage for the final stage, Vg2, is a negative DC bias voltage that functions to pinch off the final stage transistor <NUM>. For example, the DC gate bias voltage for the final stage, Vg2, may have a negative value down to about -<NUM> V or less (e.g., about -<NUM> V). In contrast, when the final stage transistor <NUM> is an enhancement-mode, normally-off device, the received and conveyed gate bias voltage is a positive DC bias voltage.

A circuit diagram that includes a depiction of a more specific embodiment of amplifier <NUM> will now be described in detail in conjunction with <FIG>. More specifically, <FIG> is a circuit diagram of an embodiment of a two-stage, cascade amplifier <NUM> with a silicon-based driver stage and a GaN-based final stage, in accordance with an example embodiment.

Amplifier <NUM> includes a silicon driver stage IC die <NUM> (e.g., IC die <NUM>, <FIG>) and a GaN final stage IC die <NUM> (e.g., IC die <NUM>, <FIG>), which are electrically coupled together in a cascade arrangement between an RF signal input terminal <NUM> (e.g., input terminal <NUM>, <FIG>) and an RF signal output terminal <NUM> (e.g., output terminal <NUM>, <FIG>). As used herein, the terms "integrated circuit die" and "IC die" mean a single, distinct die within which one or more circuit components (e.g., transistors, passive devices, and so on) are integrated and/or directly physically connected. According to an embodiment, a plurality of circuits, each including an arrangement of passive and/or active electrical components, are integrated within the silicon driver stage IC die <NUM> and the GaN final stage IC die <NUM>. It should be noted that, although die <NUM> is described as being a "silicon" die, and die <NUM> is described as being a "GaN" die, in other embodiments, either or both dies could be formed using different semiconductor materials (e.g., in the case of the GaN die, other III-V semiconductor materials, such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium antimonide (InSb)). Similarly, the transistors <NUM>, <NUM> within dies <NUM>, <NUM> may be formed using different semiconductor materials.

The silicon driver stage IC die <NUM> includes a plurality of circuits integrated within a silicon IC die (e.g., a high-resistivity silicon die). In an embodiment, the integrated circuitry of die <NUM> includes an input terminal <NUM> (e.g., input terminal <NUM>, <FIG>), an output terminal <NUM> (e.g., output terminal <NUM>, <FIG>), a first DC blocking/AC decoupling capacitor <NUM>, a second DC blocking/AC decoupling capacitor <NUM>, an input impedance matching circuit <NUM> (e.g., circuit <NUM>, <FIG>), a power transistor <NUM> (e.g., transistor <NUM>, <FIG>), an integrated portion of an interstage impedance matching circuit <NUM> (e.g., circuit <NUM>, <FIG>), a gate bias circuit <NUM> (e.g., circuit <NUM>, <FIG>), and a drain bias circuit <NUM> (e.g., circuit <NUM>, <FIG>), in an embodiment. As mentioned previously, the integrated portion of the interstage impedance matching circuit <NUM> alternatively may not be integrated in die <NUM>, but instead may be implemented using circuitry that is distinct from die <NUM> (e.g., an IPD between die <NUM> and die <NUM>, or circuitry integrated with die <NUM>).

The power transistor <NUM> is the primary amplification component of the silicon driver stage IC die <NUM>. In an embodiment, power transistor <NUM> includes a FET with a gate terminal <NUM> (control terminal), a drain terminal <NUM> (first current-conducting terminal), and a source terminal <NUM> (second current conducting terminal). The source terminal <NUM> is electrically coupled to a ground node <NUM> (e.g., the source terminal <NUM> is electrically coupled to a conductive layer on a bottom surface of the silicon IC die <NUM> through one or more through substrate vias (TSVs)). According to a specific embodiment, the power transistor <NUM> includes a silicon LDMOS transistor, which has a power density in a range of about <NUM> W/mm to about <NUM> W/mm (e.g., about <NUM> W/mm). Further, the power transistor <NUM> has a real portion of an output impedance in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms), although the input impedance could be smaller or larger, as well.

The RF signal input terminal <NUM> is electrically coupled to the input terminal <NUM> of the silicon driver stage IC die <NUM> with a connection <NUM> (e.g., a plurality of wirebonds or another electrical connection). The first DC blocking/AC decoupling capacitor <NUM> has a first terminal electrically coupled to the input terminal <NUM>, and a second terminal electrically coupled to the input impedance matching circuit <NUM>. The first DC blocking/AC decoupling capacitor <NUM> may provide some impedance transformation, but with a primary functionality of blocking the driver stage gate bias voltage, Vg1, from the input terminal <NUM>.

The input impedance matching circuit <NUM> is electrically coupled between the second terminal of the DC blocking/AC decoupling capacitor <NUM> and the gate terminal <NUM> of the driver stage power transistor <NUM>. The input impedance matching circuit <NUM> includes the first DC blocking/AC decoupling capacitor <NUM>, a second capacitor <NUM>, a first inductor <NUM>, a first resistor <NUM>, and a shunt circuit that includes a series combination of a second resistor <NUM>, a second inductor <NUM>, and a third capacitor <NUM>. The second capacitor <NUM> includes a first terminal coupled to the second terminal of the DC blocking/AC decoupling capacitor <NUM>, and a second terminal coupled to the ground node <NUM>. The first inductor <NUM> includes a first terminal coupled to the second terminal of the DC blocking/AC decoupling capacitor <NUM> (and to the first terminal of capacitor <NUM>), and a second terminal coupled to the gate terminal <NUM> of the power transistor <NUM> through the first resistor <NUM>. The shunt circuit includes the second resistor <NUM>, the second inductor <NUM>, and the third capacitor <NUM> (e.g., a DC blocking capacitor) electrically coupled between the gate terminal <NUM> of the power transistor <NUM> and the ground node <NUM>. In alternate embodiments, the second resistor <NUM> may be excluded, or the order of the second resistor <NUM>, the second inductor <NUM>, and the third capacitor <NUM> may be different from the order depicted in <FIG>.

The input impedance matching circuit <NUM> functions to raise the impedance of amplifier <NUM>, as previously mentioned, and also functions to impart amplitude and phase distortions on the RF signal that are inverse to the amplitude and phase distortions imparted by the GaN-based final stage transistor <NUM> of the GaN final stage IC die <NUM>. The input impedance matching circuit <NUM> may include a low pass circuit, a high pass circuit, a bandpass circuit, or a combination thereof. Generally, the inductance, capacitance, and resistance values will be scaled according to the center frequency of operation of the amplifier <NUM>. Further, although the input impedance matching circuit <NUM> is shown in <FIG> to have a particular configuration, in other embodiments, the input impedance matching circuit <NUM> may be differently configured, while still performing substantially the same functions.

A gate bias voltage, Vg1, for the power transistor <NUM> is provided to the gate terminal <NUM> of the power transistor <NUM> through the shunt circuit of the input impedance matching circuit <NUM>, in an embodiment. More particularly, the gate bias voltage may be provided through an input terminal <NUM>, which is electrically coupled to a node of the shunt circuit (e.g., a node between the second inductor <NUM> and the third capacitor <NUM>). For example, the gate bias voltage, Vg1, may be provided by an external voltage source <NUM>, and may have a positive value up to about <NUM> V or more, although the gate bias voltage may be lower or higher, as well. More typically, the gate bias voltage, Vg1, would be less than about <NUM> V (e.g., about <NUM> V).

The interstage impedance matching circuit <NUM> is electrically coupled between the drain terminal <NUM> of the power transistor <NUM>, and the gate terminal <NUM> of transistor <NUM>. An integrated portion of the interstage impedance matching circuit <NUM> includes a first inductor <NUM>, a shunt circuit, and the second DC blocking/AC decoupling capacitor <NUM>. The first inductor <NUM> includes a first terminal coupled to the drain terminal <NUM> of the power transistor <NUM>, and a second terminal coupled to a first terminal of the second DC blocking/AC decoupling capacitor <NUM>. The shunt circuit includes a series combination of a second inductor <NUM> and a first capacitor <NUM> (e.g., a DC blocking capacitor) electrically coupled between the second terminal of the first inductor <NUM> (and the first terminal of the second DC blocking/AC decoupling capacitor <NUM>) and the ground node <NUM>.

The interstage impedance matching circuit <NUM>, coupled with connection <NUM>, function to match the impedance of the drain terminal <NUM> of power transistor <NUM> to the gate terminal <NUM> of transistor <NUM> for proper power transfer across the frequency band. In addition, the interstage impedance matching circuit <NUM> functions to shape the input RF waveforms to the GaN final stage IC die <NUM>. According to an embodiment, the interstage impedance matching circuit <NUM> (including connection <NUM>) is configured to perform an impedance transformation between the output impedance of driver stage transistor <NUM> and the real portion of the input impedance of final stage transistor <NUM> in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms when the output impedance of transistor <NUM> is <NUM> ohms and the input impedance of transistor <NUM> is <NUM> ohms), according to an embodiment. The interstage impedance matching circuit <NUM> (including connection <NUM>) may be configured as a low pass circuit, a high pass circuit, a bandpass circuit, or a combination thereof. In various embodiments:.

The inductance, capacitance, and resistance values may be lower or higher, in various embodiments. Generally, the inductance, capacitance, and resistance values will be scaled according to the center frequency of operation of the amplifier <NUM>. Further, although the interstage impedance matching circuit <NUM> is shown in <FIG> to have a particular configuration, in other embodiments, the interstage impedance matching circuit <NUM> may be differently configured, while still performing substantially the same functions.

The second DC blocking/AC decoupling capacitor <NUM> may provide some impedance transformation, but with a primary functionality of blocking a drain bias voltage, Vd1, for the driver stage power transistor <NUM> from a gate bias voltage, Vg2, for the final stage power transistor <NUM> of the GaN final stage IC die <NUM>.

The drain bias voltage, Vd1, for the power transistor <NUM> is provided to the drain terminal <NUM> of the power transistor <NUM> through the shunt circuit of the interstage impedance matching circuit <NUM>, in an embodiment. In other words, the shunt circuit functions as the driver stage drain bias circuit <NUM> (e.g., circuit <NUM>, <FIG>). More particularly, the drain bias voltage may be provided through an input terminal <NUM>, which is electrically coupled to a node of the shunt circuit (e.g., a node between the second inductor <NUM> and capacitor <NUM>). For example, the drain bias voltage may be provided by an external voltage source <NUM>, and may have a value in a range of about <NUM> V to about <NUM> V (e.g., about <NUM> V), although the drain bias voltage may be lower or higher, as well.

The silicon driver stage IC die <NUM> (e.g., silicon IC die <NUM>, <FIG>) is electrically coupled to the GaN final stage IC die <NUM> (e.g., GaN IC die <NUM>, <FIG>) through connection <NUM> between the output terminal <NUM> of the silicon IC die <NUM> and an input terminal <NUM> of the GaN IC die <NUM>. For example, the connection <NUM> may include an inductive connection, such as a wirebond array (e.g., wirebond array <NUM>, <FIG>), or may include another type of connection (e.g., including a microstrip line, a printed coil, a parallel-coupled resistor/capacitor circuit, and so on). The connection <NUM> provides a non-integrated portion of the interstage impedance matching circuit <NUM>. According to an embodiment, the connection <NUM> has an inductance value in a range of about <NUM> nH to about <NUM> nH (e.g., about <NUM> nH), although the inductance value may be smaller or larger, as well.

The GaN final stage IC die <NUM> includes a plurality of circuits integrated within a GAN IC die that is distinct from the silicon IC die. In an embodiment, the integrated circuitry of die <NUM> includes an input terminal <NUM> (e.g., input terminal <NUM>, <FIG>), an output terminal <NUM> (e.g., output terminal <NUM>, <FIG>), final stage gate bias circuit <NUM>, a power transistor <NUM> (e.g., transistor <NUM>, <FIG>), and final stage drain bias circuit <NUM>, in an embodiment.

The power transistor <NUM> is the primary amplification component of the GaN final stage IC die <NUM>. In an embodiment, power transistor <NUM> includes a FET with a gate terminal <NUM> (control terminal), a drain terminal <NUM> (first current-conducting terminal), and a source terminal <NUM> (second current conducting terminal). The input terminal <NUM> is coupled to the gate terminal <NUM> of the GaN transistor <NUM>. The drain terminal <NUM> of the GaN transistor <NUM> is coupled to the output terminal <NUM>, and the source terminal <NUM> of the GaN transistor <NUM> is electrically coupled to a ground node <NUM> (e.g., the source terminal <NUM> is electrically coupled to a conductive layer on a bottom surface of the GaN IC die <NUM> through one or more TSVs). The output terminal <NUM> is electrically coupled through a connection <NUM> (e.g., a wirebond array or other electrical connection) to the RF signal output terminal <NUM> of the amplifier <NUM>.

According to a specific embodiment, the power transistor <NUM> includes a GaN-based high electron mobility transistor (HEMT), which has a power density in a range of about <NUM> W/mm to about <NUM> W/mm (e.g., about <NUM> W/mm). Further, the power transistor <NUM> has an input impedance in a range of about <NUM> ohms to about <NUM> ohms (e.g., about <NUM> ohms), although the input impedance could be smaller or larger, as well.

According to an embodiment, the gate bias voltage, Vg2, for the power transistor <NUM> of the GaN final stage IC die <NUM> is provided through the final stage gate bias circuit <NUM> (e.g., circuit <NUM>, <FIG>), which includes an input terminal <NUM>, resistor <NUM>, inductor <NUM>, and capacitor <NUM>, in an embodiment. In alternate embodiments, the resistor <NUM> may be excluded, or the order of the resistor <NUM>, the inductor <NUM>, and the capacitor <NUM> may be different from the order depicted in <FIG>.

During operation, a DC voltage may be provided by an external voltage source <NUM> through the input terminal <NUM>, which is electrically coupled to a node of the bias circuit <NUM> (e.g., a node between inductor <NUM> and capacitor <NUM>). The final stage gate bias voltage circuit <NUM> may convert the received voltage into a DC gate bias voltage, Vg2, for the GaN transistor <NUM>. For example, the DC gate bias voltage for the final stage, Vg2, may have a negative value down to about -<NUM> V or less (e.g., about -<NUM> V), although the gate bias voltage may be lower or higher and/or positive, as well.

The drain bias voltage, Vd2, for the power transistor <NUM> is provided to the drain terminal <NUM> of the power transistor <NUM> through the final stage drain bias circuit <NUM> (e.g., circuit <NUM>, <FIG>), in an embodiment. The final stage drain bias circuit <NUM> includes an input terminal <NUM> and a series combination of an inductor <NUM> and a capacitor <NUM> (e.g., a DC blocking capacitor) electrically coupled between the drain terminal <NUM> of final stage transistor <NUM> and the ground node <NUM>. More particularly, the drain bias voltage, Vg2, may be provided through an input terminal <NUM>, which is electrically coupled to a node of the bias circuit <NUM> (e.g., a node between inductor <NUM> and the capacitor <NUM>). In an alternate embodiment, and as indicated by the dashed line in <FIG>, the drain bias voltage, Vg2, for the GaN power transistor <NUM> may be provided to the drain terminal <NUM> of the power transistor <NUM> through RF output terminal <NUM>. As discussed in detail previously, and according to an embodiment, the final stage drain bias voltage may be provided by the same external voltage source <NUM> as is used to provide the driver stage drain bias voltage. Accordingly, the driver stage drain bias voltage and the final stage drain bias voltage are equal (e.g., Vg1 = Vg2 = <NUM> V or some other value).

The amplifiers <NUM>, <NUM> depicted in <FIG> and <FIG> each include a single amplification path. Other amplifier embodiments may include two or more amplification paths. For example, in some embodiments, multiple amplification paths may be electrically coupled together as part of a multiple-path amplifier system. For example, multiple instances of the amplifier embodiments described in conjunction with <FIG> and <FIG> may be implemented in a Doherty power amplifier, or in another type of multiple-path amplifier. For example, a first instance of the amplifier embodiments described in conjunction with <FIG> and <FIG> may be incorporated into a main amplification path of a Doherty power amplifier, and one or more additional instances of the amplifier embodiments may be incorporated into one or more peaking amplification paths.

For example, <FIG> is a simplified schematic diagram of a Doherty power amplifier <NUM>, which may include one or more instances of RF amplifiers <NUM>, <NUM>. Doherty amplifier <NUM> includes an input node <NUM>, an output node <NUM>, a power divider <NUM> (or splitter), a main amplifier path <NUM> with a two-stage main amplifier <NUM> (including driver stage amplifier <NUM> and final stage amplifier <NUM>), a peaking amplifier path <NUM> with a two-stage peaking amplifier <NUM> (including driver stage amplifier <NUM> and final stage amplifier <NUM>), and a combining node <NUM>. A load <NUM> may be coupled to the combining node <NUM> (e.g., through an impedance transformer, not shown) to receive an amplified RF signal from amplifier <NUM>.

Power divider <NUM> is configured to divide the power of an input RF signal received at input node <NUM> into main and peaking portions of the input signal. The main input signal is provided to the main amplifier path <NUM> at power divider output <NUM>, and the peaking input signal is provided to the peaking amplifier path <NUM> at power divider output <NUM>. During operation in a full-power mode when both the main and peaking amplifier paths <NUM>, <NUM> are supplying current to the load <NUM>, the power divider <NUM> divides the input signal power between the amplifier paths <NUM>, <NUM>. For example, the power divider <NUM> may divide the power equally, such that roughly one half of the input signal power is provided to each path <NUM>, <NUM> (e.g., for a symmetric Doherty amplifier configuration). Alternatively, the power divider <NUM> may divide the power unequally (e.g., for an asymmetric Doherty amplifier configuration). Essentially, the power divider <NUM> divides an input RF signal supplied at the input node <NUM>, and the divided signals are separately amplified along the main and peaking amplifier paths <NUM>, <NUM>. The amplified signals are then combined in phase at the combining node <NUM>.

The amplifier <NUM> is designed so that phase coherency between the main and peaking amplifier paths <NUM>, <NUM> is maintained across a frequency band of interest to ensure that the amplified main and peaking signals arrive in phase at the combining node <NUM>, and thus to ensure proper Doherty amplifier operation. More specifically, Doherty amplifier <NUM> has a "non-inverted" load network configuration. In the non-inverted configuration, the input circuit is configured so that an input signal supplied to the peaking amplifier path <NUM> is delayed by <NUM> degrees with respect to the input signal supplied to the main amplifier path <NUM> at the center frequency of operation, f<NUM>, of the amplifier <NUM>. To ensure that the main and peaking input RF signals are supplied to the main and peaking amplifier paths <NUM>, <NUM> with about <NUM> degrees of phase difference, as is fundamental to proper Doherty amplifier operation, phase delay element <NUM> applies about <NUM> degrees of phase delay to the peaking input signal (i.e., the signal produced at power divider output <NUM>). For example, phase delay element <NUM> may include a quarter wave transmission line, or another suitable type of delay element with an electrical length of about <NUM> degrees.

The <NUM> degree phase delay difference at the inputs to the main and peaking amplifier paths <NUM>, <NUM> is applied to compensate for a <NUM> degree phase delay applied to the signal between the output of main amplifier <NUM> and the combining node <NUM>. This is achieved through an additional delay element <NUM> between the output of the main amplifier <NUM> and the combining node <NUM>. The additional delay element <NUM> also may be configured to perform an impedance inversion, and therefore element <NUM> may be referred to as a "phase delay and impedance inversion" element or structure.

Each of the main amplifier path <NUM> and the peaking amplifier path <NUM> includes an input impedance matching network <NUM>, <NUM> (input MNm and input MNp) and a multiple-stage power amplifier <NUM>, <NUM> (e.g., an instance of amplifier <NUM>, <NUM>, <FIG>, <FIG>). The input impedance matching networks <NUM>, <NUM> may be implemented between the power divider outputs <NUM>, <NUM> and the inputs of the main and peaking amplifiers <NUM>, <NUM> (e.g., the gates of the main and peaking driver stage amplifiers <NUM>, <NUM>). In each case, the matching networks <NUM>, <NUM>, may be used to incrementally increase the circuit impedance toward the load impedance and source impedance. All or portions of the input impedance matching networks <NUM>, <NUM> may be integrally formed with the main and/or peaking amplifiers <NUM>, <NUM>. For example, as is the case with input impedance matching network <NUM>, <NUM> (<FIG>, <FIG>), all or a portion of the input impedance matching network <NUM> may be integrally formed with the IC corresponding to the main amplifier <NUM>, and all or a portion of the input impedance matching network <NUM> may be integrally formed with the IC corresponding to the peaking amplifier <NUM>. Alternatively, all or portions of the input impedance matching networks <NUM>, <NUM> may be implemented on a PCB or other substrate to which the IC is mounted.

The multiple-stage power amplifiers <NUM>, <NUM> (e.g., two instances of amplifiers <NUM>, <NUM>, <FIG>, <FIG>) are configured to amplify RF signals conducted through the main and peaking amplifier paths <NUM>, <NUM>. According to various embodiments, the main and peaking driver stage amplifiers <NUM>, <NUM> each may be implemented, for example, using a field effect transistor (e.g., two instances of FET <NUM>, <NUM>, <FIG>, <FIG>), and the main and peaking final stage amplifiers <NUM>, <NUM> each may be implemented, for example, using another field effect transistor (e.g., two instances of FET <NUM>, <NUM>, <FIG>, <FIG>). As discussed in detail above, the outputs of the FETs corresponding to each driver stage amplifier <NUM>, <NUM> and each final stage amplifier <NUM>, <NUM> are configured to operate with the same output bias voltage (e.g., drain bias voltage). The output bias voltages may be provided, for example, by a single DC drain bias voltage source <NUM> (e.g., DC drain bias voltage source <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>, <FIG>).

During operation of Doherty amplifier <NUM>, the main amplifier <NUM> is biased to operate in class AB mode, and the peaking amplifier <NUM> is biased to operate in class C mode. At low power levels, where the power of the input signal at node <NUM> is lower than the turn-on threshold level of peaking amplifier <NUM>, the amplifier <NUM> operates in a low-power (or back-off) mode in which the main amplifier <NUM> is the only amplifier supplying current to the load <NUM>. When the power of the input signal exceeds a threshold level of the peaking amplifier <NUM>, the amplifier <NUM> operates in a high-power mode in which the main amplifier <NUM> and the peaking amplifier <NUM> both supply current to the load <NUM>. At this point, the peaking amplifier <NUM> provides active load modulation at combining node <NUM>, allowing the current of the main amplifier <NUM> to continue to increase linearly.

Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).

The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the appended claims.

Claim 1:
A multiple-stage amplifier (<NUM>, <NUM>) comprising:
a driver stage transistor (<NUM>, <NUM>) with a first gate terminal (<NUM>), a first drain terminal (<NUM>) and a first source terminal (<NUM>), wherein the driver stage transistor has a first power density, the first gate terminal (<NUM>) is configured to receive an input RF signal, and the first source terminal (<NUM>) is electrically coupled to a ground node (<NUM>);
a first drain bias circuit (<NUM>, <NUM>) coupled to the first drain terminal of the driver stage transistor, and configured to provide a first drain bias voltage from a first bias input terminal (<NUM>, <NUM>) to the first drain terminal, wherein the driver stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die (<NUM>, <NUM>);
a final stage transistor (<NUM>, <NUM>) with a second gate terminal (<NUM>), a second drain terminal (<NUM>) and a second source terminal (<NUM>), wherein the final stage transistor is integrally formed in a second semiconductor die (<NUM>), the second source terminal (<NUM>) is electrically coupled to a ground node (<NUM>), and wherein the highest ratio of the first power density of the driver stage transistor to a second power density of the final stage transistor is <NUM>:<NUM>;
a second drain bias circuit (<NUM>, <NUM>) coupled to the second drain terminal of the final stage transistor (<NUM>, <NUM>), and configured to provide a second drain bias voltage from a second bias input terminal (<NUM>, <NUM>) to the second drain terminal, wherein the second drain bias voltage equals the first drain bias voltage;
and
an interstage impedance matching circuit (<NUM>, <NUM>) coupled between the first drain terminal (<NUM>) and the second gate terminal (<NUM>);
wherein the multiple-stage amplifier is characterized in that the second drain bias circuit (<NUM>, <NUM>) is integrally formed in the second semiconductor die (<NUM>, <NUM>).