Patent Description:
The technology described herein relates to complementary metal oxide semiconductor (CMOS) transducers and methods for forming the same.

Capacitive Micromachined Ultrasonic Transducers (CMUTs) are known devices that include a membrane above a micromachined cavity. The membrane may be used to transduce an acoustic signal into an electric signal, or vice versa. Thus, CMUTs can operate as ultrasonic transducers.

Two types of processes can be used to fabricate CMUTs. Sacrificial layer processes form the membrane of the CMUT on a first substrate above a sacrificial layer. Removal of the sacrificial layer leaves behind the membrane above a cavity. Wafer bonding processes bond two wafers together to form a cavity with a membrane.

<CIT> describes a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer.

<CIT> describes a three-dimensional integrated circuit device including a first substrate having a first crystal orientation comprising at least one or more PMOS devices thereon and a first dielectric layer overlying the one or more PMOS devices. The three-dimensional integrated circuit device also includes a second substrate having a second crystal orientation comprising at least one or more NMOS devices thereon; and a second dielectric layer overlying the one or more NMOS devices. An interface region couples the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.

<CIT> describes a capacitive electromechanical transducer including a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is <NUM> to <NUM>.

According to an aspect of the technology, an ultrasonic transducer is provided as defined in claim <NUM>. The ultrasonic transducer comprises a complementary metal oxide semiconductor (CMOS) wafer having an integrated circuit (IC) formed therein, the CMOS layer wafer comprising a metallization layer as a top layer of the CMOS wafer. The ultrasonic transducer further comprises a membrane for transducing between an acoustic signal and an electric signal, the membrane being disposed above a cavity in the CMOS wafer, being integrated with the CMOS wafer and having a first side proximate the cavity and a second side distal the cavity. The cavity is defined at least in part by a standoff comprising an embedded via in the standoff. The ultrasonic transducer further comprises a conductive electrical path contacting the second side of the membrane distal the cavity and electrically connecting the membrane to the metallization layer comprised in the CMOS wafer. A liner forming the conductive electrical path is formed in the via and on the second side of the membrane. In some embodiments, such a configuration is the basis of, or represents, a device including an integrated ultrasonic transducer and integrated circuit. Thus, a compact ultrasound device may be made by allowing formation of the device components on a single CMOS wafer.

The cavity is defined at least in part by a non-conductive sidewall and the conductive electrical path comprises an embedded via in the non-conductive sidewall. Such a configuration provides beneficial electrical insulating properties by not leaving the conductive electrical path exposed as a boundary of the cavity.

In some embodiments, the membrane comprises polysilicon, and in some embodiments amorphous silicon. The use of such materials may relax fabrication by avoiding the use of monocrystalline materials. The use of such materials requires less effort and time than fabrication with monocrystalline materials, in at least some embodiments. In some embodiments, the membrane comprises degeneratively doped silicon, which in some embodiments contributes to the membrane being electrically conductive.

In some embodiments, the membrane has a non-uniform thickness including a center portion having a first thickness and an outer portion having a second thickness. In some embodiments, the second thickness is less than the first thickness, such that the membrane may be configured as a piston. In some embodiments, the first thickness is less than the second thickness. In some embodiments, the second thickness is between approximately one micron and approximately five microns, and in some embodiments is between approximately <NUM> microns and approximately two microns. In some embodiments, the first thickness is between approximately one micron and approximately <NUM> microns.

The provision for membranes with non-uniform thicknesses facilitates achieving desired operation of the membrane, such as desired frequency and/or power characteristics.

In some embodiments, the CMOS wafer includes a plurality of cavities and a plurality of membranes above respective cavities of the plurality of cavities defining a plurality of ultrasonic transducers. In some embodiments, the membranes are arranged to seal the respective cavities. In some embodiments, the plurality of ultrasonic transducers are configured as at least part of an ultrasound imaging device, which may function to collect ultrasound data suitable for forming ultrasound images. In some embodiments, the plurality of ultrasonic transducers are configured as at least part of a high intensity focused ultrasound (HIFU) device, which may function to apply HIFU energy to a target subject. In some embodiments, the plurality of ultrasonic transducers are configured to form a device operable as an ultrasound imaging device and/or a high intensity focused ultrasound (HIFU) device, and in some embodiments are configured to form a device operable as an imaging device and a HIFU device to perform image-guided HIFU, for example in which ultrasound data collected by at least some of the ultrasonic transducers is used to form an ultrasound image which may be considered in applying HIFU to a subject.

In some embodiments, the ultrasonic transducer further comprises an electrode in the CMOS wafer beneath the cavity, for example being positioned proximate an end of the cavity opposite an end at which the membrane(s) is located. In some embodiments, the cavity has a first width and the electrode has a second width. In some embodiments, the first width is greater than the second width, which may allow for an ultrasonic transducer comprising the cavity to exhibit beneficial capacitive characteristics. In some embodiments, the first width is approximately equal to the second width, and in some embodiments the first width is less than the second width, which in some embodiments minimizes undesirable capacitive behavior by increasing a distance between the electrode and sidewalls of the cavity. In some embodiments, the electrode comprises TiN.

According to embodiments of the present disclosure, the ultrasonic transducer comprises a substrate having the cavity formed therein, and the membrane is integrated with the substrate and overlies the cavity. In some embodiments, the membrane is configured to seal the cavity. In some embodiments, the membrane has a thickness between approximately <NUM> microns and approximately <NUM> micron, which facilitates beneficial operation of the ultrasonic transducer, for example with respect to a desired frequency or range of frequencies.

The substrate is a complementary metal oxide semiconductor (CMOS) wafer having an integrated circuit (IC) formed therein and the membrane is monolithically integrated with the substrate. In at least some embodiments, such a configuration allows for a compact ultrasonic transducing device to be made by allowing the components to be integrated with the same substrate.

In some embodiments, the membrane has a thickness between approximately <NUM> microns and approximately <NUM> microns. In some embodiments, the membrane comprises polysilicon, and in some embodiments the membrane comprises amorphous silicon. The use of such materials requires less effort and time than fabrication with monocrystalline materials, in at least some embodiments.

In some embodiments, the membrane has a non-uniform thickness, including a center portion having a first thickness and an outer portion having a second thickness. In some embodiments, the first thickness is less than the second thickness. In some embodiments, the second thickness is less than the first thickness, such that the membrane may be configured as a piston. In some embodiments, the second thickness is between approximately one micron and approximately five microns, and in some embodiments is between approximately <NUM> microns and approximately two microns. In some embodiments, the first thickness is between approximately one micron and approximately <NUM> microns. In some embodiments, the center portion is configured as a mass for the membrane, for example having a greater thickness than a thickness of the periphery of the membrane. The provision for membranes with non-uniform thicknesses facilitates achieving desired operation of the membrane, such as desired frequency and/or power characteristics.

According to an aspect of the technology, a method of forming an ultrasonic transducer is provided as defined in claim <NUM>.

Embodiments of the ultrasonic transducer and the method are defined in the dependent claims.

Various aspects and embodiments of the application will be described with reference to the following figures. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.

Existing methods for forming CMUTs are impractical for forming ultrasonic transducers integrated with CMOS wafers and, therefore, CMOS integrated circuits (ICs) on such wafers. Thus, such integrated ultrasonic transducers and ICs are nonexistent today. For example, existing methods for forming CMUTs do not provide a practical manner for making electrical connection between the CMUT and integrated circuits on a CMOS wafer. Also, existing methods do not adequately allow for scaling of CMUTs to sizes appropriate for compatibility with low voltage CMOS integrated circuits. Furthermore, CMUT manufacturing processes are too complex to be performed in a cost-effective manner suitable for large scale production of commercial devices, for example because they involve processing with complex materials and too many processing steps.

Accordingly, aspects of the present application provide scalable, relatively low cost methods of fabricating ultrasonic transducers integrated with CMOS wafers and CMOS ICs formed on the CMOS wafers. Such methods enable the formation of a new class of devices including monolithically integrated ultrasonic transducers and CMOS ICs, referred to herein as CMOS Ultrasonic Transducers (CUTs). The CUTs may be used to form ultrasound devices for ultrasound imaging and/or high intensity focused ultrasound (HIFU) applications and/or other ultrasound applications.

To facilitate integration of ultrasonic transducer technology with CMOS processing techniques in a manner suitable for scalable, large scale production of CUTs, it may be desirable for a manufacturing process to exhibit one or more of various characteristics. For example, the process may be suitable for forming ultrasonic transducers without damaging the CMOS wafer and any circuitry (e.g., the IC) formed thereon. Thus, the process may avoid processing steps which require temperatures sufficiently high to cause damage to a CMOS wafer and CMOS ICs. Rather, low temperature processes may be employed. The process may utilize materials common to CMOS process lines, and which do not require extensive effort or time to fabricate and/or deposit, such as polycrystalline and/or amorphous forms of materials rather than single crystal (monocrystalline) forms. The process may provide for suitable manners of making direct or indirect electrical connection to individual ultrasonic transducer cells. The process may also be suitable for making ultrasonic transducers of suitable sizes to enable low voltage operation (e.g., below <NUM> V, below <NUM> V, below <NUM> V, or other suitably low voltages for transducer operation), thus making them more compatible with low voltage CMOS ICs. For example, the processes may be suitable for making membranes of sufficient sizes (e.g., sufficiently small thicknesses) and shapes for operation as low voltage devices while still delivering desired transducer behavior (e.g., desired frequencies of operation, bandwidths, power, or other characteristics). Other characteristics of a manufacturing process may also be desirable in some embodiments to facilitate integration of ultrasonic transducers with CMOS wafers.

Accordingly, aspects of the present application implement low temperature (e.g., below <NUM>° C) wafer bonding to form ultrasonic transducer membranes on CMOS wafers. Low temperature in this context may, in some embodiments, be below <NUM>° C, below <NUM>° C, below <NUM>° C, between <NUM>° C and <NUM>° C, any temperature within that range, or any suitable temperature for preserving structures on a CMOS wafer). Thus, the bonding processes as well as other fabrication steps for forming CUTs according to some embodiments may avoid any anneals above <NUM>° C. In some embodiments, the membranes may be formed of relatively simple and inexpensive materials, such as polycrystalline silicon, amorphous silicon, silicon dioxide, silicon nitride (SiN), and titanium nitride (TiN). The membranes may also be thin, and in at least some embodiments thinner than those previously achievable in CMUTs. Use of such thin membranes may facilitate the formation of ultrasonic transducers operable at voltages sufficiently low to comply with CMOS technology, and thus may facilitate formation of CUTs.

Aspects of the present application provide various designs and processes for making electrical connection to the membrane of an ultrasonic transducer in a manner that facilitates integration of the ultrasonic transducer with a CMOS integrated circuit. In some embodiments, connection may be made from a cavity-side (e.g., a bottom side) of the membrane. Such connection are made by way of an embedded via, a conductive standoff or cavity wall, or in any other suitable manner. Such electrical interconnections may provide local connection to the membrane rather than global connection, whereby the connection to individual membranes may be made close to related circuitry and on an individual basis rather than at great distances from related circuitry and on a multi-membrane basis. Such capability for local connection to membranes may enable a broader range of operating schemes than those afforded by global interconnection, for example because of the capability for individualized control of membranes.

Aspects of the present application provide CUTs having a piston configuration, in which a membrane includes one or more relatively thick center portions and a relatively thin surrounding (or outer) portion. Such a structure may be referred to herein as a piston membrane. In some embodiments, the piston membrane may be fully formed on a transfer wafer prior to wafer bonding. The transfer wafer may then be bonded to a CMOS wafer with low temperature processing methods and the piston membrane removed from the remainder of the transfer wafer. In this manner, piston membranes formed of a single material defining a unitary body may be formed, and such piston membranes may be formed of materials that are processed at temperatures sufficiently high to damage CMOS ICs if such processing had occurred after the wafer bonding.

The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.

A first process for forming an ultrasonic transducer having a membrane above a cavity in a CMOS wafer is now described with reference to <FIG>, which show an example not forming part of the claimed subject-matter, but which contain some features in line with the claimed subject-matter, such as the presence of a metallization layer as a top layer of a CMOS wafer having an IC formed therein, a cavity defined at least in part by a standoff comprising an embedded via in the standoff, and a liner formed in the via and on the side of the membrane distal the cavity. Referring to <FIG>, the process may begin with a CMOS wafer <NUM> including a substrate <NUM>, a dielectric or insulating layer <NUM>, a first metallization layer <NUM> and a second metallization layer <NUM>, which in some embodiments may be a top metallization layer of the CMOS wafer <NUM>.

The substrate <NUM> may be silicon or any other suitable CMOS substrate. In some embodiments, the CMOS wafer <NUM> may include CMOS integrated circuitry (IC), and thus the substrate <NUM> may be a suitable substrate for supporting such circuitry.

The insulating layer <NUM> may be formed of SiO<NUM> or any other suitable dielectric insulating material. In some embodiments, the insulating layer <NUM> may be formed via tetraethyl orthosilicate (TEOS), though alternative processes may be used.

While the CMOS wafer <NUM> is shown as including two metallization layers <NUM> and <NUM>, it should be appreciated that CMOS wafers according to the various aspects of the present application are not limited to having two metallization layers, but rather may have any suitable number of metallization layers, including more than two in some embodiments. Such metallization layers may be used for wiring (e.g., as wiring layers) in some embodiments, though not all embodiments are limited in this respect.

The first and second metallization layers <NUM> and <NUM> may have any suitable construction. In the embodiment illustrated, at least the second metallization layer <NUM> may have a multi-layer construction, including a middle conductive layer <NUM> (e.g., formed of aluminum or other suitable conductive material) and upper and lower liner layers <NUM> and <NUM>, respectively. The liner layers <NUM> and <NUM> may be formed of titanium nitride (TiN) or other suitable conductive material (e.g., metals other than TiN, such as tantalum, or other suitable metals for acting as a liner). In some embodiments, the upper liner layer <NUM> may be used as an etch stop, for example during one or more etch steps used in as part of a process for forming a cavity for an ultrasonic transducer. Thus, the liner layer <NUM> may be formed of a material suitable to act as an etch stop in some embodiments. Moreover, while not shown, the first and second metallization layers <NUM> and <NUM>, as well as any other metallization layers described herein, may optionally include silicon oxynitride (SiON) as an upper layer (e.g., on top of liner layer <NUM>) to serve as an anti-reflective coating during lithography stages.

In some embodiments, it may be desirable to form an electrode from the second metallization layer <NUM> serving as an electrode of an ultrasonic transducer. Also, the second metallization layer <NUM> may be used to make electrical contact to a membrane of a CUT to be formed on the CMOS wafer. Accordingly, as shown in <FIG>, the second metallization layer <NUM> may be suitably patterned to form an electrode <NUM> and one or more contacts <NUM>.

While <FIG> illustrates a configuration in which an electrode and electrical contacts are formed on a CMOS wafer from a metallization layer, it should be appreciated that other manners of forming an electrode (e.g., electrode <NUM>) and/or electrical contacts (e.g., electrical contacts <NUM>) may be implemented. For example, conductive materials other than metals but suitable to act as electrodes and/or electrical contacts may be suitably processed on the CMOS wafer to form the illustrated electrode and/or electrical contacts.

An insulating layer <NUM> may then be deposited as shown in <FIG>. The insulating layer <NUM> may be SiO<NUM> or any other suitable insulator, and may be formed in any suitable manner. In some embodiments, the insulating layer <NUM> may be formed by high density plasma (HDP) deposition. The insulating layer <NUM> may then be planarized (not shown), for example using chemical mechanical polishing (CMP) or other suitable planarization technique.

In <FIG>, the insulating layer <NUM> may be etched as shown to expose the upper surface of the electrode <NUM> and electrical contacts <NUM>. In some embodiments, the upper liner layer <NUM> may be used as an etch stop for a selective etch used to etch the insulating layer <NUM>. As an example, the liner layer <NUM> may be formed of TiN and may be used as an etch stop, though not all embodiments are limited in this respect.

A further insulating layer <NUM> may be deposited as shown in <FIG> to cover the upper surfaces of the electrode <NUM> and electrical contacts <NUM> and may then be patterned as shown in <FIG> to open contact holes <NUM> for the electrical contacts <NUM>. The insulating layer <NUM> may be SiO<NUM> or any other suitable insulator.

As shown in <FIG>, a conductive layer <NUM> may be deposited. The conductive layer may be used to form electrical contacts to a membrane of an ultrasonic transducer, as will be shown in connection with <FIG>. Also, the conductive layer <NUM> may be patterned to form a cavity therein for a CUT, with a remaining portion of the conductive layer <NUM> defining one or more sidewalls of the cavity. In some embodiments, then, the conductive layer <NUM> may also represent a spacer in that a membrane may be separated from the surface of the CMOS wafer <NUM> by the height of the conductive layer <NUM>. Thus, the conductive layer <NUM> may serve one or more of multiple possible functions.

The conductive layer <NUM> may be formed of any suitable conductive material. In some embodiments, the conductive layer <NUM> may be formed of a metal. For example, the conductive layer <NUM> may be TiN in some embodiments.

The conductive layer <NUM> may be planarized (not shown) using CMP or other suitable planarization technique, and then may be patterned as shown in <FIG> to form contacts <NUM>. It can be seen that at this stage a cavity <NUM> has been formed in the CMOS wafer with the contacts <NUM> serving to at least partially define the cavity. Namely, the contacts <NUM> (which in some embodiments may represent a single contact forming a closed contour) function as sidewalls of the cavity <NUM> in the embodiment illustrated and, as will be further appreciated from consideration of <FIG>, create a standoff between the electrode <NUM> and a membrane overlying the cavity <NUM>.

As shown in <FIG>, a second wafer <NUM> may be bonded to the CMOS wafer. In general, the second wafer may be any suitable type of wafer, such as a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, or an engineered substrate including a polysilicon or amorphous silicon layer with an insulating layer between a single crystal silicon layer and the polysilicon or amorphous silicon layer. In the embodiment illustrated, the second wafer <NUM> may include four layers including a base layer or handle layer <NUM>, insulating layer <NUM>, layer <NUM>, and layer <NUM>. The second wafer <NUM> may be used to transfer layers <NUM> and <NUM> to the CMOS wafer for forming a membrane over cavity <NUM>, and thus may be referred to herein as a transfer wafer.

As a non-limiting example of suitable materials making up the second wafer <NUM>, the base layer <NUM> may be a silicon layer (e.g., single crystal silicon), the insulating layer <NUM> may be SiO<NUM> and may represent a buried oxide (BOX) layer, and layer <NUM> may be silicon. In some embodiments, the layer <NUM> may be degeneratively doped silicon phosphide (SiP+). In some embodiments, the layer <NUM> may be polysilicon or amorphous silicon, though other embodiments may utilize single crystal silicon. The layer <NUM> may be formed of a material suitable for bonding to the contacts <NUM> on the CMOS wafer. For example, the contacts <NUM> and layer <NUM> may be formed of the same material. In some embodiments, the contacts <NUM> and layer <NUM> may be formed of TiN.

The process used for bonding the second wafer <NUM> to the CMOS wafer <NUM> may be a low temperature bonding process, for example not exceeding <NUM>° C. In some embodiments, the temperature of the bonding process may be between approximately <NUM>° C and <NUM>° C, between approximately <NUM>° C and approximately <NUM>° C, any temperature(s) within those ranges, any other temperature described herein for low temperature bonding, or any other suitable temperature. Thus, damage to the metallization layers on the CMOS wafer, and any ICs on the CMOS wafer, may be avoided.

The wafer bonding process may be one of various types. In some embodiments, the wafer bonding may be direct bonding (i.e., fusion bonding). Thus, the wafer bonding may involve energizing respective surfaces of the CMOS and second wafers and then pressing the wafers together with suitable pressure to create the bond. A low temperature anneal may be performed. While fusion bonding represents one example of a suitable bonding technique, other bonding techniques may alternatively be used, including for example bonding two wafers through the use of one or more intermediate layers (e.g., adhesive(s)). In some embodiments, anodic or plasma assisted bonding may be used.

The bonding illustrated in <FIG> may result in the second wafer <NUM> being monolithically integrated with the CMOS wafer <NUM>. Thus, the two may form a unitary body in some situations.

A membrane may then be formed from the second wafer <NUM>. The second wafer <NUM> may be thinned from the backside. Such thinning may be performed in stages. For example, mechanical grinding providing coarse thickness control (e.g., <NUM> micron control) may initially be implemented to remove a relatively large amount of the bulk wafer. In some embodiments, the thickness control of the mechanical grinding may vary from coarse to fine as the thinning process progresses. Then, CMP may be performed on the backside, for example to get to a point close to the layer <NUM>. Next, a selective etch, such as a selective chemical etch, may be performed to stop on the layer <NUM>. Other manners of thinning are also possible.

Thus, as shown in <FIG>, the base layer or handle layer <NUM> and insulating layer <NUM> may be removed. A membrane <NUM> formed of the layer <NUM> and layer <NUM> may remain. The membrane may be any suitable thickness TM, non-limiting examples of which are described below. In some embodiments, the layer <NUM> may be etched or otherwise thinned to provide a desired membrane thickness.

Various features of the structure illustrated in <FIG> are noted. First, the structure includes a sealed cavity <NUM> which is sealed by the membrane <NUM>. Also, the sidewalls of the cavity are conductive, i.e., the contacts <NUM> are conductive and form the sidewalls of the sealed cavity. In this respect, the contacts <NUM> represent a conductive standoff for the membrane <NUM> from the surface of the CMOS wafer. The contacts <NUM> may be relatively large area electrical contacts and make contact with a relatively large area of the membrane, thus providing a low resistivity electrical path to/from the membrane. For example, the contacts may provide electrical control between the membrane and an IC on the CMOS wafer (e.g., disposed beneath the cavity) which may interact with the membrane to provide/receive electrical signals and thus in some embodiments control operation of the membrane.

Moreover, it is noted that the membrane <NUM> has a first side <NUM> proximate the cavity <NUM> and a second side <NUM> distal the cavity, and that direct electrical contact is made to the first side <NUM> via the contacts <NUM>. The first side <NUM> may be referred to as a bottom side of the membrane and the second side <NUM> may be referred to as a top side of the membrane. Local connection to the membrane <NUM> may be made in this manner, and the membrane <NUM> may be connected to integrated circuitry in the CMOS wafer via this connection (e.g., via contact <NUM>). In some embodiments, an IC may be positioned beneath the cavity <NUM> and the conductive path configuration illustrated may facilitate making connection between the integrated circuitry beneath the cavity and the membrane <NUM>. The configuration of <FIG> provides a non-limiting example of an embedded contact to the membrane, in that electrical contact is provided by way of a conductive path in the CMOS wafer (e.g., to contact <NUM>) rather than a contact made on the second side <NUM>. Such a configuration may be preferable to making electrical contact on the second side <NUM> since any contact on the second side <NUM> may (negatively) impact vibration of the membrane <NUM>.

Also, it is noted that in the embodiment of <FIG> the electrode <NUM> is narrower than the cavity <NUM>. Namely, the electrode <NUM> has a width W1 less than a width W2 of the cavity <NUM>. Such a configuration may be desirable at least in those embodiments in which the cavity has conductive sidewalls (e.g., the contacts <NUM>) to provide electrical isolation between the sidewalls and the electrode.

Moreover, it is noted that the structure of <FIG> may be altered by not including the layer <NUM> in an embodiment. Thus, in an embodiment a direct bond may be formed between contacts <NUM> (e.g., formed of TiN) and layer <NUM> (e.g., silicon).

The structure illustrated in <FIG> may have any suitable dimensions. Non-limiting examples of dimensions for the membrane <NUM> and cavity <NUM> are described further below.

As non-limiting examples, the width W2 of the cavity <NUM> may be between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, may be approximately <NUM> microns, approximately <NUM> microns, approximately <NUM> microns, any width or range of widths in between, or any other suitable width. In some embodiments, the width may be selected to maximize the void fraction, i.e., the amount of area consumed by the cavity compared to the amount of area consumed by surrounding structures. The width dimension may also be used to identify the aperture size of the cavity, and thus the cavities may have apertures of any of the values described above or any other suitable values.

The depth D1 may be between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, any depth or range of depths in between, or any other suitable depth. If the contacts <NUM> are formed of TiN, it may be preferable in such embodiments for D1 to be less than <NUM> microns, since TiN is commonly formed as a thin film. In some embodiments, the cavity dimensions and/or the membrane thickness of any membrane overlying the cavity may impact the frequency behavior of the membrane, and thus may be selected to provide a desired frequency behavior (e.g., a desired resonance frequency of the membrane). For example, it may be desired in some embodiments to have an ultrasonic transducer with a center resonance frequency of between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, of approximately <NUM>, approximately <NUM>, any frequency or range of frequencies in between, or any other suitable frequency. For example, it may be desired to use the devices in air, gas, water, or other environments, for example for medical imaging, materials analysis, or for other reasons for which various frequencies of operation may be desired. The dimensions of the cavity and/or membrane may be selected accordingly.

The membrane thickness TM (e.g., as measured in the direction generally parallel to the depth D1) may be less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> micron, less than <NUM> microns, any range of thicknesses in between, or any other suitable thickness. The thickness may be selected in some embodiments based on a desired acoustic behavior of the membrane, such as a desired resonance frequency of the membrane.

Also, it should be appreciated that the cavity <NUM>, and more generally the cavities of any embodiments described herein, may have various shapes, and that when multiple cavities are formed not all cavities need have the same shape or size. For example, <FIG> illustrate various potential shapes for cavity <NUM> and the other cavities described herein. Specifically, <FIG> illustrate top views of a portion <NUM> of a CMOS wafer having cavities <NUM> formed therein of various shapes. <FIG> illustrates that the cavities <NUM> may have a square aperture. <FIG> illustrates the cavities <NUM> may have a circular aperture. <FIG> illustrates the cavities may have a hexagonal aperture. <FIG> illustrates the cavities <NUM> may have an octagonal aperture. Other shapes are also possible.

While the portion <NUM> is shown as including four cavities, it should be appreciated that aspects of the present application provide for one or more such cavities to be formed in a CMOS wafer. In some embodiments a single substrate (e.g., a single CMOS wafer) may have tens, hundreds, thousands, tens of thousands, hundreds of thousands, or millions of CUTs (and corresponding cavities) formed therein.

<FIG> illustrates an ultrasonic transducer which has a membrane <NUM> overlying the cavity <NUM>, wherein the membrane has a substantially uniform thickness. In some embodiments, it may be desirable for the membrane to have a non-uniform thickness. For example, it may be desirable for the membrane to be configured as a piston, with a center portion having a greater thickness than an outer portion of the membrane, non-limiting examples of which are described below.

Ultrasonic transducers such as that illustrated in <FIG> may be used to send and/or receive acoustic signals. The operation of the transducer in terms of power generated, frequencies of operation (e.g., bandwidth), and voltages needed to control vibration of the membrane may depend on the shape and size of the membrane. A membrane shaped as a piston with a center mass-like portion that is connected to a CMOS wafer by a thinner peripheral portion may provide various beneficial operating characteristics.

Accordingly, an aspect of the present application provides ultrasonic transducers having piston membranes. Such transducers may be formed by wafer bonding processes according to some embodiments of the present application. In general, the thicker center portion of such membranes may be formed on the top side or bottom side of the membrane, and may be formed prior to or after wafer bonding. Non-limiting examples of suitable fabrication processes are now described.

According to an example not forming part of the claimed subject-matter, a method of making a piston membrane having a thicker center portion on a topside of the membrane and formed from a transfer wafer is provided. The method may involve the same processing steps previously described in connection with <FIG> to arrive at the structure of <FIG>. From that point, as shown in <FIG>, a transfer wafer <NUM> may be bonded with the CMOS wafer, for example using a low temperature (below <NUM>° C) direct bonding technique as previously described.

The transfer wafer <NUM> of <FIG> includes the base layer <NUM>, insulating layer <NUM>, and layer <NUM>. The transfer wafer also includes piston <NUM>, and layer <NUM>, which in some embodiments may be an insulating layer such as SiO<NUM> (e.g., formed via tetraethylorthosilicate (TEOS) or other suitable process), but which is not limited to being formed of any particular type of material. The piston <NUM> may be formed of silicon in some embodiments, and in some embodiments is formed of polysilicon or amorphous silicon, although other embodiments may use single crystal silicon. The use of polysilicon or amorphous silicon may simplify the manufacturing process and/or reduce cost in some cases, among other possible benefits. In some embodiments, the piston <NUM> may be degeneratively doped. In some embodiments, the piston <NUM> is formed of SiP+.

As shown in <FIG>, the transfer wafer <NUM> may be monolithically integrated with the CMOS wafer as a result of the bonding process. Subsequently, as shown in <FIG>, the base layer <NUM>, insulating layer <NUM> and layer <NUM> may be removed by wafer grinding, then etching, and then removal of the buried oxide, or in any other suitable manner. The result may thus include the piston <NUM> overlying the cavity <NUM>. The piston <NUM> and layer <NUM> may form a membrane as shown, and thus may be considered a piston membrane. The piston membrane may have a peripheral (or outer) portion with thickness T1 and a center portion with thickness T2. In some embodiments, T1 may be made as thin as possible, and may, for example, be between approximately <NUM> micron and approximately <NUM> microns. The piston <NUM> may have a width WP. In some embodiments, the width WP may be substantially the same as the width W1 of the electrode <NUM>. However, not all embodiments are limited in this respect, as WP may be greater than W1 in some embodiments or less than W1 in some embodiments.

As non-limiting examples of dimensions, the cavity <NUM> illustrated in <FIG> may have any of the cavity dimensions previously described herein or any other suitable dimensions. For example, D1 and W2 may have any of the various previously described for those dimensions.

The thickness T1 may be any of the values previously described for T1 or any of the values described for TM. Likewise, the thickness T2 may have any of the values previously described in connection with TM or any other suitable values. In some embodiments, the thickness T1 may be made as small as possible and the thickness T2 may assume any of the values previously described in connection with TM. For example, the thickness T2 may be between <NUM> micron and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, any value within such ranges, or any other suitable values.

A non-limiting alternative process for forming a piston membrane overlying a cavity, according to an example not forming part of the claimed subject-matter, is illustrated in <FIG>, in which the thicker center portion of the piston is on a topside of the membrane. The process may begin with the structure of <FIG>, and from there add a passivation layer <NUM> as shown in <FIG>. The passivation layer may be silicon nitride (Si<NUM>N<NUM>) or other suitable passivation material which may be formed at temperatures sufficiently low to prevent damage to the CMOS wafer.

The passivation layer <NUM> may then be suitably etched as shown in <FIG> to create a center portion <NUM> for the piston membrane. It should be noted that in this embodiment the center portion <NUM> is formed of a different material than that of the layer <NUM>.

The piston membrane of <FIG> may have an outer portion with thickness T3 and the center portion may have a thickness T4. The thickness T3 may be any of those values previously described in connection with T1, while T4 may be any of those values previously described in connection with T2.

A further alternative process for forming a piston membrane, according to an example not forming part of the claimed subject-matter, is illustrated in <FIG>. The process may begin with a structure similar to, substantially the same as, or identical to that of <FIG>. However, the contacts <NUM> may have a smaller height in the embodiment of <FIG>. For example, whereas the contacts <NUM> in <FIG> may be the same height as the depth D1 of the cavity <NUM> in the embodiment represented by <FIG>, and therefore may have any of the values previously described herein for D1 (e.g., between <NUM> and <NUM> microns, less than <NUM> microns, etc.), the height of the contact <NUM> in <FIG> may be smaller (e.g., half the height of previously described D1, one-quarter the height of D1, etc.). A transfer wafer having the base layer <NUM>, insulating layer <NUM>, layer <NUM> (e.g., monocrystalline silicon, polysilicon, amorphous silicon, or SiP+ in some embodiments) and a patterned layer <NUM> may be bonded to the CMOS wafer using low temperature bonding. The patterned layer <NUM> may have a thickness between approximately <NUM> micron and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, any value within those ranges, less than <NUM> microns, less than <NUM> microns, or any other suitable value.

The patterned layer <NUM> may be formed of a material suitable for bonding to contacts <NUM>, and in some embodiments may be formed of the same material as contacts <NUM>. In an embodiment the patterned layer <NUM> may be formed of TiN.

As shown in <FIG>, the base layer <NUM> and insulating layer <NUM> may be removed subsequent to bonding of the transfer wafer with the CMOS wafer. Such removal may be performed using grinding, etching, and/or buried oxide removal, or other suitable techniques. In some embodiments, the layer <NUM> may be thinned to a desired membrane thickness. As shown, the resulting structure may include a piston with a thicker center portion formed on an underside of the membrane. In this configuration, electrical connectivity may be provided from the patterned layer <NUM> through the layer <NUM> to the cavity sidewalls since the materials making up those components may be electrically conductive.

It should be appreciated from the discussion of <FIG> that the illustrated CUT may be formed with only two wafers and a single wafer bonding process. The layer <NUM> may function as an etch stop in some embodiments, which may allow for formation of the piston membrane (the combination of <NUM> and <NUM>) to be formed from a single transfer wafer. Thus, the process may be relatively simple and involve a relatively small number of processing steps compared to if three or more wafers and multiple wafer bonding steps were used to form the piston membrane.

Another structure which may be formed as part of an ultrasonic transducer according to an aspect of the present application is a membrane stop, which in some embodiments may function as an isolation post and which may provide various benefits. Membrane stops may effectively alter the depth of a cavity such that a membrane may contact the bottom of the cavity (referred to as collapse) more easily, and may alter the frequency behavior of an ultrasonic transducer. Namely, when the membrane is pulled down far enough, it makes contact with the bottom of the cavity. Such operation may be advantageous since having the membrane hit or contact the bottom of the cavity can dampen certain resonant modes, thereby broadening the frequency response of the transducer. However, there is a "charge trapping" effect, in which charge may end up deposited on the electrodes of the transducer, thereby altering the operating characteristics of the transducer (e.g., increasing the necessary bias voltage), and causing hysteresis. Membrane stops may provide the benefit of "bottoming out" the membrane, while substantially reducing the charge trapping effect and problems with hysteresis. Ultrasonic transducers with membrane stops may be more reliable after collapse than ultrasonic devices lacking such membrane stops. Moreover, because the membrane stop may prevent the membrane from contacting the bottom-most part of the cavity, insulation need not be formed on the bottom surface of the cavity in all embodiments, which can therefore reduce processing steps and time in fabricating an ultrasonic transducer. However, the insulator on the bottom surface of the cavity may be used in case of unanticipated contact between the membrane and the bottom of the cavity (despite any membrane stop) and/or to prevent electrical discharge across the cavity.

Membrane stops may be formed in different locations of an ultrasonic transducer. For example, membrane stops may be formed on the bottom of a cavity of an ultrasonic transducer. In some embodiments, membrane stops may be formed on the bottom of a membrane of the ultrasonic transducer (e.g., on the bottom side of a membrane transferred from a transfer wafer). In other embodiments, membrane stops may be formed on both the bottom of a cavity and the bottom of a membrane of an ultrasonic transducer. Non-limiting examples are now described.

<FIG> illustrates an alternative ultrasonic transducer to that of <FIG>. As shown, the ultrasonic transducer includes the structure of <FIG> with the addition of a membrane stop <NUM> formed on the bottom of the cavity <NUM>.

The membrane stop <NUM> may be formed between the stages of <FIG> of 1E. Namely, subsequent to step 1D the membrane stop may be deposited and patterned on electrode <NUM>. The processing steps of <FIG> may then be performed to arrive at the structure of <FIG>.

According to an example of the present application, an ultrasonic transducer may have a piston membrane and one or more membrane stops. A non-limiting example is illustrated in connection with <FIG>, which combines features of previously described <FIG>.

<FIG> illustrate one non-limiting example of an embedded electrical contact making connection to a bottom side of a membrane of an ultrasonic transducer. In that non-limiting example, the conductive contact also is a sidewall of the cavity of the ultrasonic transducer, meaning that the ultrasonic transducer had conductive sidewalls. An alternative configuration for making direct electrical contact from a CMOS wafer to an underside of membrane of an ultrasonic transducer is to use an embedded via. <FIG> illustrate a non-limiting example.

The processing stages of <FIG> may be performed. Then, as shown in <FIG>, an insulating layer <NUM> may be deposited, for example using high density plasma deposition. The insulating layer <NUM> may be SiO<NUM> or any other suitable insulator. The insulating layer may be planarized, for example by CMP.

As shown in <FIG> one or more vias <NUM> may be etched, for example to land on second metallization layer <NUM>, which may function as an etch stop. Optionally, a relatively thin layer of liner material (e.g., TiN) <NUM> may be deposited conformally, thus covering the vias <NUM> and the top surface of the CMOS wafer.

As shown in <FIG>, the vias may then be filled with conductive plugs <NUM>, for example by depositing a layer of conductive material such as Tungsten (W). As shown in <FIG>, the conductive layer may be etched back.

In <FIG>, the cavity <NUM> may then be etched from the insulating layer <NUM>, leaving sidewalls <NUM> having conductive plugs (i.e., conductive plugs <NUM>) embedded therein.

In <FIG> the upper surface of the CMOS waver may be covered with an insulating layer <NUM>, which may subsequently be removed from the tops of the sidewalls <NUM> in preparation for wafer bonding.

In <FIG>, a transfer wafer <NUM>, which may be similar to or the same as the transfer wafer of <FIG> but lacking the layer <NUM>, may be wafer bonded with the CMOS wafer. As shown in <FIG>, the base layer <NUM> and insulating layer <NUM> may then be removed by suitable techniques, thus leaving the membrane <NUM>.

It should be appreciated that the bonding illustrated in <FIG> causes the plugs <NUM> to be in direct contact with the layer <NUM> on the top of the plugs, i.e., no liner may be formed between the plug <NUM> and the layer <NUM> at the point of intersection. In some embodiments, the layer <NUM> may be silicon (e.g., monocrystalline, polycrystalline, or amorphous). While conventional processing techniques attempt to avoid such a direct connection between a plug formed of, for example, Tungsten, Applicants have appreciated that such direct connection may be acceptable in scenarios in which the direct connection is between the plug and a layer (e.g., layer <NUM>) not being used to support high quality integrated circuits. Rather, because the layer <NUM> is being used to form a membrane, diffusion of the material from plug <NUM> into the layer <NUM> may be acceptable in some embodiments.

<FIG> illustrate a method for forming a piston from the structure of <FIG>. Namely, a passivation layer <NUM> of Si<NUM>N<NUM> or any other suitable passivation material, may be deposited on the membrane <NUM>. Then, as shown in <FIG>, the passivation layer <NUM> may be suitably patterned.

<FIG> illustrate an alternative manner of forming a piston membrane over a cavity in a CMOS wafer where the cavity is bounded by non-conductive sidewalls having an embedded via therein. As shown in <FIG>, the structure of <FIG> may be bonded with a transfer wafer <NUM> similar to the type previously described in connection with <FIG> minus the layer <NUM>. The base layer <NUM>, insulating layer <NUM> and layer <NUM> may be removed as previously described in connection with <FIG>.

Embodiments of the present application provide practical methods for fabricating membranes above cavities in a CMOS wafer and having an embedded via which makes contact to a top side of the membrane. <FIG> illustrate an example.

Beginning with the structure of <FIG>, the insulating layer <NUM> may be patterned as shown in <FIG> to form sidewalls <NUM> at least partially defining the cavity <NUM>. In <FIG>, an insulator (e.g., SiO<NUM>) <NUM> may be deposited and then CMP performed to prepare the topside of the sidewalls <NUM> for bonding with another wafer.

As shown in <FIG>, wafer bonding may then be performed with the CMOS wafer and a second wafer (e.g., a transfer wafer). The transfer wafer may be the same type as that previously described in connection with <FIG>, though other types of transfer wafers are also possible. The bonding process may be a low temperature (e.g., below <NUM>° C) direct bonding process, which may preserve any silicon circuitry (e.g., ICs) on the CMOS wafer.

As shown in <FIG>, the base layer <NUM> and insulating layer <NUM> may be removed, for example using any of the techniques previously described for such removal. Thus, a membrane <NUM> may be monolithically integrated with the CMOS wafer and overlying the cavity <NUM>.

As shown in <FIG>, vias <NUM> are formed through the membrane <NUM> and sidewalls <NUM>, stopping on the contacts <NUM>. The etch may be a selective etch, and may be directional, such as a deep reactive ion etch (DRIE), or any other suitable etch. In line with the claimed subject-matter, a liner <NUM> is then formed in the vias and on the top side of the membrane <NUM>. The liner is conductive, may be a metal, and in some embodiments is TiN, though other materials may alternatively be used.

As shown in <FIG>, plugs <NUM> may then be formed in the vias <NUM> by suitable deposition and etch back. For example, the plugs <NUM> may be formed of tungsten, and may be formed by depositing tungsten to fill the vias <NUM> and then etching the tungsten back using the liner <NUM> (e.g., TiN) as an etch stop.

Subsequently, in <FIG>, layers <NUM> and <NUM> may be deposited on the top side of the membrane <NUM>. The layers may include a passivation layer. For example, layer <NUM> may be SiO<NUM> or any other suitable passivation layer. Layer <NUM> may also be a passivation layer, and in some embodiments be Si<NUM>N<NUM>.

Thus, <FIG> illustrates a configuration of an ultrasonic transducer providing electrical contact through a membrane (and therefore on a top side of the membrane) monolithically integrated with a CMOS wafer, where the contact includes a conductive path formed at least in part by a via embedded in a sidewall of a cavity of the CMOS wafer. Optionally, as shown in <FIG>, the layers <NUM> and <NUM> may be patterned to define a piston membrane <NUM>.

The piston membrane <NUM> of <FIG> is a non-limiting example of a piston membrane that may be formed using the processing steps of <FIG>. The piston membrane may have an outer portion (proximate where the membrane contacts the sidewalls <NUM>) with a thickness assuming any of the values previously described herein for T1 and a center portion having a thickness assuming any of the values previously described herein for T2. As an example, the center portion may have a thickness less than <NUM> microns. As an alternative, it may be desirable in some embodiments for the piston to be thicker than that shown in <FIG> illustrates a non-limiting example.

As shown, the piston membrane <NUM> of <FIG> may be thicker than the piston membrane <NUM> of <FIG> (e.g., <NUM> times as thick, twice as thick, three times as thick, or any other suitable thickness), though the rest of the ultrasonic transducer may be substantially the same as that illustrated in <FIG>. Such a configuration may be achieved by forming the layer <NUM> with a greater thickness in the embodiment of <FIG> than in the embodiment of <FIG>.

As a further alternative configuration for making electrical contact from a metallization layer of CMOS wafer to the top side of a membrane, <FIG> illustrates an embodiment corresponding substantially to the structure of <FIG>. However, in the embodiment of <FIG> the liner <NUM> may be thicker than that of the embodiment of <FIG>. For example, the liner <NUM> may be less than <NUM> micron in the embodiment of <FIG> but may be between approximately <NUM> and <NUM> microns in the embodiments of <FIG>. The liner <NUM> in <FIG> may then serve as the primary electrical contact, without any conductive plug being formed in the vias. Such a configuration may simplify processing of an ultrasonic transducer by avoiding further processing steps associated with forming plugs in the vias.

In some embodiments, CUTs having top side electrical contacts but no embedded electrical contacts are provided. Aspects of the present application provide practical, cost-effective manners of fabricating several different designs of such CUTs. Some non-limiting examples are now described.

<FIG> illustrate a first example of a process for fabricating a CUT having a top side electrical contact. Starting from the structure of <FIG>, the second metallization layer <NUM> may be patterned as shown in <FIG> to form an electrode <NUM>.

As shown in <FIG>, an insulating layer <NUM> may then be deposited. The insulating layer may be SiO<NUM> in some embodiments, for example formed by TEOS or other suitable deposition technique.

As shown in <FIG>, the insulating layer <NUM> may be etched to form a cavity <NUM> having sidewalls or spacers <NUM> at least partially defining the cavity. Any suitable etch of the insulating layer may be performed. In some embodiments, the etch may be a selective etch and the second metallization layer <NUM> may function as an etch stop. For example, the second metallization layer <NUM> may include TiN (e.g., a TiN liner on an upper surface) which may function as an etch stop.

As shown in <FIG>, an insulating layer <NUM> (e.g., SiO<NUM>) may then be deposited. The CMOS wafer may be planarized (e.g., using CMP) and prepared for wafer bonding by performing surface treatment. Thus the insulating layer <NUM> may be removed from the top of the sidewalls <NUM>.

Wafer bonding may then be performed in <FIG> using a transfer wafer of the type previously described in <FIG>, or any other suitable wafer. The base layer <NUM> and insulating layer <NUM> of the transfer wafer may then be removed in the previously described manners as shown in <FIG>, leaving a membrane <NUM> sealing the cavity <NUM>. It should be appreciated that in this embodiment the electrode <NUM> is wider than the cavity <NUM>. For example, the cavity may have a width assuming any of those values previously described herein for W2, and the electrode <NUM> may be <NUM> microns greater than that width, five microns greater than that width, <NUM> microns greater than that width, between <NUM> and <NUM> microns greater than that width, or any other suitable value.

As shown in <FIG>, contacts <NUM> may be formed on the top side of the membrane <NUM>. The contacts may have any suitable structure. In some embodiments, the contacts may be formed by forming a metallization layer on the top side of the membrane and then patterning the metallization layer to arrive at the illustrated structure. The metallization layer may include a multi-layer structure, for example having the three layer structure previously described in connection with second metallization layer <NUM> or any other suitable structure. Thus, as a non-limiting example, the contacts <NUM> may include a layer of aluminum sandwiched between upper and lower TiN layers, though other configurations are possible.

As shown in <FIG>, a passivation step may then be performed, for example by depositing layers <NUM> and <NUM>. Layer <NUM> may be an insulating layer, for example being formed of SiO<NUM>. Layer <NUM> may be formed of Si<NUM>N<NUM> or any other suitable material.

As shown in <FIG>, the layers <NUM> and <NUM> may then be patterned to form passivated contacts <NUM> on the top side of the membrane <NUM>.

<FIG> illustrates an alternative CUT to that of <FIG>. While similar to the CUT of <FIG>, the CUT of <FIG> has a bottom electrode <NUM> that is not as wide as the cavity <NUM>, which may reduce capacitance with the cavity sidewalls. For example, the cavity <NUM> may have a width assuming any of the values previously described herein for W2 and the electrode <NUM> may have a width three-fourths as large, one-half as large, one-third as large, or any other suitable value. The processing steps used to fabricate the CUT of <FIG> may be substantially the same as those used to fabricate the CUT of <FIG>, although the insulating layer deposited in <FIG> may be thicker in the context of fabricating the CUT of <FIG> to account for possible over-etch during <FIG> because of the narrower electrode. For example, the insulating layer deposited in <FIG> may be twice as thick as that used to fabricate the CUT of <FIG>, three times as thick, or any other suitable thickness.

As described previously, in some embodiments a CUT may include a piston, and processes for fabricating such pistons are described herein. As a further non-limiting example, that is not encompassed by the wording of the claims, the CUT of <FIG> may be fabricated to include piston <NUM>. The illustrated CUT is similar to that shown in <FIG>. However, in patterning layers <NUM> and <NUM>, a portion of those layers may be left in place over the center of the membrane <NUM> to form the piston structure.

Pistons of various thicknesses may be desirable to provide various ultrasonic transducer behavior, in terms of frequency response, power handling capabilities, and robustness, among other possible considerations. An alternative CUT construction to that of <FIG>, and having a thicker piston, is described in connection with <FIG> and <FIG>.

The structure of <FIG> is similar to that of previously described <FIG>. However, the layers <NUM> and <NUM> may be formed to greater thicknesses in the example of <FIG>, that is not encompassed by the wording of the claims, in anticipation of forming a thicker piston than that provided in <FIG>. For example, the layers <NUM> and <NUM> may each be between approximately two and twenty microns, between approximately three and ten microns, any value within those ranges, or any other suitable value.

In <FIG>, the layers <NUM> and <NUM> may be patterned using a suitable etching technique to form passivated contacts <NUM> and piston <NUM>.

It is noted that the CUT of <FIG> has the electrode <NUM> which, as previously described, has a width smaller than the width of the cavity. However, the piston configuration of <FIG> may alternatively be formed as part of a CUT having an electrode that has the same width as or a larger width than the cavity of the CUT.

<FIG> illustrate a non-limiting manner of fabricating an alternative CUT design to that of <FIG> and <FIG>, including a piston membrane having a width matched to the width of the electrode underlying the cavity.

As shown in <FIG>, the process may begin with a structure having a sealed cavity <NUM> sealed with a membrane <NUM> monolithically integrated with a CMOS wafer (e.g., using any suitable processing steps described herein). An electrode <NUM> may be disposed underneath the cavity. The contacts <NUM> may be formed in the manner previously described. Insulating layer <NUM> may be deposited on the upper top side of the membrane <NUM> and the contacts <NUM>. The insulating layer <NUM> may be SiO<NUM> or other suitable insulating material.

As shown in <FIG>, the insulating layer <NUM> may be patterned and then layer <NUM> may be deposited on the top side of the membrane <NUM>. Layer <NUM> may function as a passivation layer in some embodiments, and may be formed of Si<NUM>N<NUM> or other suitable passivating material.

As shown in <FIG>, layer <NUM> may then be suitably patterned to form passivated contacts <NUM> and piston <NUM>. It can be seen that the layer <NUM> may be patterned such that it fully covers the insulating layer <NUM> of the passivated contact <NUM>, i.e., the layer <NUM> extends down to the upper surface of the membrane <NUM>. In this manner, the layer <NUM> may prevent humidity from passing through the insulating layer <NUM> and harming (e.g., corroding) the contacts <NUM>.

As previously described, in some embodiments processes are provided for fabricating CUTS having a piston membrane in which the piston membrane is initially formed on a transfer wafer and monolithically integrated with a CMOS wafer by low temperature wafer bonding. A non-limiting example, that is not encompassed by the wording of the claims, of a CUT formed in this manner and having top side electrical contacts to the membrane is described in connection with <FIG>.

As shown in <FIG>, the process for fabricating such a CUT may begin by wafer bonding a CMOS wafer <NUM> with a transfer wafer <NUM> having several of the same layers as previously described for the transfer wafer <NUM> of <FIG> (i.e., having layers <NUM>, <NUM>, <NUM>, and <NUM>, but lacking <NUM>). The CMOS wafer may include an electrode <NUM> and sidewalls <NUM>, the latter of which may be formed by insulating layers <NUM> and <NUM> in the non-limiting embodiment illustrated. The wafer bonding may be a low temperature bonding process suitable to preserve structures such as silicon circuitry on the CMOS wafer, and may create a sealed cavity <NUM>. As shown, in this embodiment the width W5 of the electrode <NUM> may be less than the width W2 of the cavity <NUM>.

The base layer <NUM>, insulating layer <NUM>, and layer <NUM> may be removed from the transfer wafer <NUM> in any of the manners previously described for such removal. Then, as shown in <FIG>, a metal layer <NUM>, for example having the structure previously described in connection with second metallization layer <NUM>, may be deposited.

As shown in <FIG>, the metal layer <NUM> may be patterned to form contacts <NUM> and an insulating layer (e.g., SiO<NUM>) <NUM> may be deposited.

As shown in <FIG>, the insulating layer <NUM> may be patterned and then a layer <NUM> may be deposited as a passivation layer. In some embodiments, the layer <NUM> may be Si<NUM>N<NUM>, though other materials may be used. As shown in <FIG>, the layer <NUM> may be patterned in a manner such that it touches the piston <NUM> and thereby fully covers the remaining portion of layer <NUM>. In this manner, layer <NUM> may prevent humidity from passing through the insulating layer <NUM> and harming (e.g., corroding) the contacts <NUM>.

<FIG> illustrate a process for fabricating a CUT having a piston membrane with a piston width matching the width of an electrode beneath the cavity of the CUT. As shown in <FIG>, the process may begin with a structure similar to that previously described in connection with <FIG> except that the electrode <NUM> beneath the cavity may be narrower.

As shown in <FIG>, the layers <NUM> and <NUM> may be patterned to form a piston <NUM> having a width W3 the same as or substantially the same as the width W4 of the electrode <NUM>.

As described previously, in some embodiments a CUT may include a membrane stop. The membrane stop may be positioned at the bottom of a cavity of the CUT in some embodiments. A non-limiting example, that is not encompassed by the wording of the claims, of such a CUT with electrical contacts on a top side of the membrane of the CUT is shown in connection with <FIG>.

As shown in <FIG>, the process may begin with a CMOS wafer including an electrode <NUM> covered by an insulating layer <NUM>. An etch may then be performed as shown in <FIG> to form a cavity <NUM> having sidewalls or spacers <NUM>.

Subsequently, in <FIG>, an insulating layer <NUM> may be deposited. The insulating layer <NUM> may be SiO<NUM> or any other suitable insulating material. The insulating layer <NUM> may be patterned as shown in <FIG> to form a membrane stop <NUM> in the cavity <NUM>.

As shown in <FIG>, an insulating layer (e.g., SiO<NUM>) <NUM> may be deposited. The insulating layer <NUM> may act to prevent an electrical short circuit if the membrane of the CUT (shown in <FIG>) bottoms out. However, because the membrane stop <NUM> itself may be formed of an insulating material, the insulating layer <NUM> may be omitted in some embodiments.

After deposition of the insulating layer <NUM>, the CMOS wafer may be planarized (e.g., using CMP) and the surface prepared for wafer bonding. Thus, the insulating layer <NUM> may be removed from the top of the sidewalls <NUM>.

As shown in <FIG>, wafer bonding may then be performed to bond the CMOS wafer with a transfer wafer <NUM> of the type previously described in connection with <FIG> (e.g., a multi-layer wafer having a base silicon substrate, a buried oxide layer, and a silicon membrane layer, formed of single crystal silicon, polysilicon or amorphous silicon in some embodiments). The wafer bonding process may be a low temperature process (e.g., below <NUM>° C) to preserve CMOS structures (e.g., ICs) on the CMOS wafer. The wafer bonding process may result in a sealed cavity <NUM>.

As shown in <FIG>, the base layer <NUM> and insulating layer <NUM> may be removed (using any of the techniques described previously herein for removing such layers) and a metallization layer <NUM> may be deposited. The metallization layer <NUM> may have the same construction as second metallization layer <NUM> in some embodiments, though alternative configurations are possible.

As shown in <FIG>, the metallization layer <NUM> may be patterned to form contacts <NUM>, and layers <NUM> and <NUM> may be deposited. In some embodiments, layers <NUM> and <NUM> may serve as passivation layers, and may be formed of SiO<NUM> and Si<NUM>N<NUM>, respectively.

As shown in <FIG>, the layers <NUM> and <NUM> may be patterned to produce passivated contacts <NUM> on the top side of the membrane of the CUT. The passivated contacts <NUM> may be used to apply electrical signals to and/or receive electrical signals from the membrane. In operation, the membrane may contact the membrane stop <NUM> when vibrating. The membrane stop <NUM> may alter the frequency behavior of the CUT in the manner previously described for membrane stops.

<FIG> illustrate an alternative process for fabricating a CUT having a membrane stop and top side electrical contacts to the membrane of the CUT. In this example, that is not encompassed by the wording of the claims, the membrane stop may be on the underside of the membrane of the CUT rather than at the bottom of the cavity of the CUT.

The process may begin as shown in <FIG> with a CMOS wafer prepared for wafer bonding. The CMOS wafer may have a cavity <NUM> formed in an insulating layer <NUM> patterned to define sidewalls or spacers <NUM>. A second insulating layer <NUM> may cover the electrode <NUM>.

As shown in <FIG>, the CMOS wafer may be bonded to a transfer wafer having a patterned insulating layer forming a membrane stop <NUM>. The bonding may result in a sealed cavity <NUM>, as shown in <FIG>.

As shown in <FIG>, the base layer <NUM> and insulating layer <NUM> may be removed, leaving a membrane <NUM>.

Electrical contacts <NUM> may then be formed on the top side of the membrane <NUM>, for example by depositing and patterning a metallization layer, as shown in <FIG>. Subsequently, in <FIG>, a passivation layer <NUM> may be deposited and patterned to passivate the electrical contacts <NUM>. The passivation layer <NUM> may be formed of SiO<NUM> in some embodiments.

In <FIG>, a second passivation layer, for example formed of Si<NUM>N<NUM>, may be deposited and patterned over the electrical contacts <NUM>.

Thus, the CUT of <FIG> may include a membrane stop on a bottom side of the membrane with top side electrical contacts to the membrane. The process for forming the CUT may involve only low temperature processing, thus preserving structures formed on the CMOS wafer, such as ICs.

The structures described herein may have various dimensions suitable for use as ultrasonic transducers, for example in ultrasound imaging applications and/or HIFU applications. For example, the cavity sizes (e.g., widths, or aperture sizes more generally, and depths) may assume any suitable values to provide desired frequency characteristics. The membranes and piston membrane may likewise assume any suitable values. In some embodiments, the dimensions may be selected to make the CUTs suitable for low voltage operation, thus facilitating their integration with low voltage CMOS ICs, though not all embodiments are limited in this respect. For example, high voltage designs may also be used, for example in the context of CUTs operating to provide HIFU. When designed for low voltage operation, the CUTs may have suitable dimensions to operate at, for example, less than <NUM> V, less than <NUM> V, less than <NUM> V, less than <NUM> V, less than <NUM> V, between <NUM> V and <NUM> V, between <NUM> V and <NUM> V, between <NUM> V and <NUM> V, any voltage within those ranges, or any other suitable voltages. Operation at these lower voltages may be allowed, at least in part, by making the membranes sufficiently thin to flex suitably at these lower voltages. Non-limiting examples of membrane thicknesses achievable with embodiments of the present application are described further below.

As non-limiting examples, cavities of CUTs as described herein may have widths, or more generally apertures, between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, may be approximately <NUM> microns, approximately <NUM> microns, approximately <NUM> microns, any width or range of widths in between, or any other suitable width. In some embodiments, the width may be selected to maximize the void fraction, i.e., the amount of area consumed by the cavities compared to the amount of area consumed by surrounding structures.

The cavities of CUTs described herein may have any suitable depths, for example, between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, any depth or range of depths in between, or any other suitable depth. In some embodiments, the cavity dimensions and/or the membrane thickness of any membrane overlying the cavity may impact the frequency behavior of the membrane, and thus may be selected to provide a desired frequency behavior (e.g., a desired resonance frequency of the membrane). For example, it may be desired in some embodiments to have an ultrasonic transducer with a center resonance frequency of between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, of approximately <NUM>, approximately <NUM>, any frequency or range of frequencies in between, or any other suitable frequency. For example, it may be desired to use the devices in air, gas, water, or other environments, for example for medical imaging, materials analysis, or for other reasons for which various frequencies of operation may be desired. The dimensions of the cavity and/or membrane may be selected accordingly.

CUTs as described herein may have any suitable membrane thicknesses. For example, the membranes described herein may have a thickness (e.g., as measured in a direction generally parallel to a depth of a corresponding cavity) less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> microns, less than <NUM> micron, less than <NUM> microns, any range of thicknesses in between, or any other suitable thickness. The thickness may be selected in some embodiments based on a desired acoustic behavior of the membrane, such as a desired resonance frequency of the membrane.

When a piston membrane is formed, the center and outer portions of the piston membrane may have any suitable thicknesses and any suitable ratios of thicknesses. In some embodiments, the outer portion of the membrane (connecting the membrane to the CMOS wafer) may be made as thin as possible (e.g., between approximately <NUM> and approximately <NUM>, as non-limiting examples). The center portions of the piston membranes may have any thickness in accordance with those previously described for membranes. In some embodiments, both the outer and center portions of the piston membranes may have thicknesses between approximately <NUM> micron and approximately <NUM> microns, between approximately <NUM> microns and approximately <NUM> microns, any value with such ranges, or any other suitable values.

As described previously, an aspect of the present application provides an ultrasonic transducer cell integrated with CMOS circuitry where the circuitry is disposed beneath the transducer. <FIG> illustrates a non-limiting example, that is not encompassed by the wording of the claims, of a such a device, using the ultrasonic transducer of <FIG>.

As shown, the device <NUM> may include the ultrasonic transducer of <FIG> with the addition of an integrated circuit <NUM>. The integrated circuit may be formed in the base layer <NUM> of the CMOS wafer. For example, the base layer may be a bulk silicon layer, and the integrated circuitry may include one or more active silicon circuit elements (e.g., MOS transistors having doped source and drain regions in the silicon), capacitors, resistors, or other circuit components. The integrated circuit <NUM> may be suitable to operate the ultrasonic transducer in transmit and/or receive modes.

As shown, both the electrode <NUM> and the contact <NUM> may be connected to the integrated circuit <NUM>. The electrode <NUM> may be connected by the illustrated via <NUM> which may, for example, directly contact a doped source/drain terminal of a MOS transistor in the base layer <NUM>. The contact <NUM> may be connected to the integrated circuit <NUM> by a conductive line <NUM>, which may be a via in some embodiments. Other manners of making connection from the electrode <NUM> and the contact <NUM> to the integrated circuit <NUM> are also possible.

As previously described and as shown in <FIG>, in some embodiments local connection may be made to the membrane of a CUT rather than global connection. For example, contact <NUM> provides for local connection to the membrane of the illustrated CUT. Such local connection may be beneficial to reduce unwanted electrical behavior in biasing the membrane (e.g., unwanted capacitances which can arise with long signal lines), among other potential benefits provided by local connections.

In some embodiments, the membrane of the CUT may be biased, and in some such embodiments the contact <NUM> may be used to supply the bias signal. In such situations, the contact <NUM> may be connected to the integrated circuit <NUM> via a capacitor (not shown) for providing or maintaining a desired bias level. Other biasing configurations are also possible.

In some embodiments, the electrode <NUM> may be driven, and thus the integrated circuit <NUM> may be suitably connected to drive the electrode. In some embodiments, the electrode <NUM> may be biased, rather than the membrane.

Thus, it should be appreciated that various operating scenarios are possible for the ultrasonic transducer. The integrated circuit <NUM> may include suitable circuitry (e.g., switching circuitry, capacitors, etc.) to allow for the various modes of operation, including driving the membrane, driving the electrode <NUM>, or other modes of operation.

Various examples of transfer wafers have been described herein for use with various embodiments. In some embodiments, traditional SOI wafers may be used, having a silicon bulk wafer as a handle layer, buried oxide layer, and monocrystalline silicon layer. However, as previously described, some embodiments implement alternative types of transfer wafers, including transfer wafers having polysilicon or amorphous silicon layers. Since the transfer wafers may be used to form membranes, pistons, and/or membrane stops rather than being used to provide silicon layers for supporting high quality circuitry, Applicants have appreciated that high quality monocrystalline silicon layers need not be used in all embodiments. Rather, as previously described, membranes, pistons, and membrane stops may be formed of polysilicon, amorphous silicon, oxides, TiN, or other suitable materials. Thus, Applicants have appreciated that transfer wafers having such materials may be implemented in some embodiments instead of traditional SOI wafers, and that such alternative types of transfer wafers may be fabricated with significantly less effort and cost than required for form traditional SOI wafers. Accordingly, use of such relatively simple multi-layer transfer wafers may significantly simplify production of CUTs and may allow for cost effective large scale production of CUTs.

Non-limiting examples of how to fabricate some of the transfer wafers described herein are now described. For example, in those embodiments in which the transfer wafer 131has polysilicon (e.g., doped polysilicon) or amorphous silicon as the layer <NUM>, the transfer wafer may be fabricated starting with a silicon bulk wafer as base layer <NUM>, the depositing a layer of SiO<NUM> as insulating layer <NUM>, and then depositing polysilicon or amorphous silicon. Next, the layer <NUM> (e.g., TiN) may be deposited. Performing these steps may require significantly less precision than those used to form traditional SOI wafers, and thus fabricating transfer wafer <NUM> in this manner may simplify the overall process for forming a CUT and reduce the cost of the same.

<FIG> illustrate a process sequence for fabricating the transfer wafer <NUM> of <FIG> and <FIG>, having a piston formed therein, according to a non-limiting embodiment of the present application.

Starting with the base layer <NUM> (e.g., silicon), the insulating layer <NUM> (e.g., SiO<NUM>) may be deposited, followed by deposition of a layer <NUM> as shown in <FIG>. The layer <NUM> may form part of the piston <NUM> previously described, and thus may be made of the material desired for the piston. For example, the layer <NUM> may be doped polysilicon in some embodiments, or may be amorphous silicon in some embodiments.

As shown in <FIG>, the layer <NUM> may be patterned and layer <NUM>, previously described, may be deposited. The layer <NUM> may be an insulating material, such as SiO<NUM> formed by TEOS or other suitable insulating material. CMP may be performed and the wafer may be planarized.

Then, as shown in <FIG>, a layer <NUM> may be deposited. The layer <NUM> may form part of the piston <NUM> and thus may be formed of the material desired for the piston. For example, the layer <NUM> may be doped polysilicon in some embodiments, or may be amorphous silicon in some embodiments. CMP may then be performed.

At the stage of processing illustrated in <FIG>, the layers <NUM> and <NUM> which will make up the piston <NUM> are in place. However, they do not define a unitary body since they have been deposited in separate steps, as reflected by the horizontal line between the two layers. Thus, to achieve the transfer wafer <NUM> with the piston <NUM> representing a unitary body, an anneal may be performed, thus producing the finalized transfer wafer <NUM> as shown in <FIG>. The anneal need not be a low temperature anneal, though it could be, since the transfer wafer is fabricated separately from the CMOS wafers described herein and therefore fabrication of the transfer wafer may include processing steps at temperatures which would damage CMOS circuitry if performed on a CMOS wafer. Moreover, it should be appreciated that the described steps for forming the transfer wafer <NUM> are relatively simple compared to those required to form a traditional SOI wafer.

Optionally, the transfer wafer <NUM> shown in <FIG> may be further processed by depositing previously described layer <NUM> (e.g., TiN), to produce the transfer wafer <NUM> of <FIG>.

<FIG> illustrate a process sequence for fabricating a transfer wafer of the type shown in <FIG>, having a membrane stop, according to a non-limiting embodiment of the present application. Starting with the base layer <NUM> (e.g., silicon), the insulating layer <NUM> (e.g., SiO<NUM>) may be deposited. Then previously described layer <NUM> may be deposited. An insulating layer <NUM> may then be deposited to produce the structure of <FIG>. The insulating layer <NUM> may be SiO<NUM>, and may be formed by TEOS or other suitable deposition method.

As shown in <FIG>, the insulating layer <NUM> may be patterned to form the membrane stop <NUM>. Thus, it should be appreciated that fabrication of the transfer wafer of the type shown in <FIG> may be relatively simple compared to fabrication of traditional SOI wafers in those embodiments in which layer <NUM> is not monocrystalline silicon.

<FIG> illustrate an alternative process sequence for fabricating a transfer wafer having a piston formed therein, according to a non-limiting embodiment of the present application. The transfer wafer may be the type previously described in connection with <FIG>.

The base layer <NUM> may be bulk silicon. Insulating layer <NUM> (e.g., SiO<NUM>) may be deposited on the silicon. Then layer <NUM> may be deposited on the insulating layer <NUM>. In some embodiments, the layer <NUM> may be polysilicon or amorphous silicon, although single crystal silicon may be used in some embodiments. Next, layer <NUM> may be deposited to provide the structure shown in <FIG>.

Subsequently, as shown in <FIG>, the layer <NUM> may be patterned to provide a piston configuration. Thus, it should be appreciated that the illustrated transfer wafer may be fabricated by relatively simple deposition and etching steps, and may be relatively simple to fabricate compared to fabrication of traditional SOI wafers in those embodiments in which the layer <NUM> is not single crystal silicon.

The foregoing discussion has focused on single CUTs and formation of the same for purposes of simplicity. It should be appreciated, however, that the various aspects of the present application are not limited to single CUTs. Rather, the methods disclosed herein may be performed at the wafer level and thus may be used to fabricate multiple CUTs of the types described herein, i.e., aspects of the present application provide for wafer-level processing of CUTs. For example, a single substrate (e.g., a single CMOS wafer) may have tens, hundreds, thousands, tens of thousands, hundreds of thousands, or millions of CUTs formed therein.

According to an aspect of the present application, the CUTs described herein may be fabricated using a full reticle. Such capability may facilitate fabrication of large numbers of CUTs on a single chip.

Moreover, aspects of the present application may provide for larger numbers of ultrasonic transducers per a given chip area than previously attainable. As has been described, aspects of the present application provide for formation of smaller ultrasonic transducers than conventionally possible. The membranes may be made thinner than those of conventional ultrasonic transducers (e.g., than conventional CMUTs) because of the wide variety of types of materials which may be used for membranes according to aspects of the present application and because of the manners in which the membranes may be formed from the transfer wafers described herein. Because transducer behavior may depend at least in part on the relationship between the membrane thickness and the cavity size (e.g., the transducer aperture), making thinner membranes may allow for making smaller transducers than were previously possible. Accordingly, more transducers may be created on a single chip than previously possible.

When multiple CUTs are formed, they may be electrically interconnected in various manners to form a desired device. A single CUT may be referred to herein as a cell. In some embodiments, multiple CUTs may be interconnected to form an element, i.e., an element may include one or more CUT cells. Cells and/or elements may be arranged and electrically connected suitably to form, for example, an ultrasound transducer arrangement operable for ultrasound imaging and/of HIFU. Thus, for example, the cells and/or elements may be arranged and electrically connected suitably to provide desired frequency behavior (e.g., bandwidth, center frequency, etc.) for an ultrasound imaging and/or HIFU device. The grouping or connection of CUT cells into multi-cell elements may be achieved through suitable connection of the CUTs to ICs of the CMOS wafer, in some embodiments.

While various aspects and embodiments have been described as providing monolithically integrated ultrasonic transducers and CMOS wafers having ICs formed therein, not all aspects and embodiments are limited in this respect. For example, some aspects of the present application may also apply to flip-chip bonded and multi-chip configurations. For example, making electrical contact to the bottom side of a membrane may be performed in flip-chip bonded configurations. Other aspects may also apply to non-monolithic devices.

The aspects of the present application may provide one or more benefits, some of which have been previously described. Now described are some non-limiting examples of such benefits. It should be appreciated that not all aspects and embodiments necessarily provide all of the benefits now described. Further, it should be appreciated that aspects of the present application may provide additional benefits to those now described.

Aspects of the present application provide manufacturing processes suitable for formation of monolithically integrated ultrasonic transducers and CMOS structures (e.g., CMOS ICs). In at least some embodiments, the processes may be relatively inexpensive to perform, and may be scalable to large quantities of ultrasonic transducers. Aspects of the present application provide processes for manufacturing suitably sized ultrasonic transducers for operation in connection with low voltage CMOS ICs. Aspects of the present application provide robust processes for making ultrasonic transducers of various configurations. Other benefits may also be provided in accordance with one or more aspects of the present application.

Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the scope of the technology described in the application, which is defined by the appended claims. For example, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and/or methods described herein, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

The above-described embodiments can be implemented in any of numerous ways. One or more aspects and embodiments of the present application involving the performance of processes or methods may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform, or control performance of, the processes or methods. In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various ones of the aspects described above. In some embodiments, computer readable media may be non-transitory media.

The terms "program" or "software" are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present application need not reside on a single computer or processor, but may be distributed in a modular fashion among a number of different computers or processors to implement various aspects of the present application.

When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer, as non-limiting examples. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

As another example, a computer may receive input information through speech recognition or in other audible formats.

Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks or wired networks.

Elements other than those specifically identified by the "and/or" clause may optionally be present, whether related or unrelated to those elements specifically identified.

Claim 1:
An ultrasonic transducer, comprising:
a complementary metal oxide semiconductor (CMOS) wafer (<NUM>) having an integrated circuit (IC) formed therein, wherein the CMOS wafer (<NUM>) comprises a metallization layer (<NUM>) as a top layer of the CMOS wafer (<NUM>);
a membrane (<NUM>; <NUM>) for transducing between an acoustic signal and an electric signal, the membrane (<NUM>; <NUM>) being disposed above a cavity (<NUM>) in the CMOS wafer (<NUM>), being integrated with the CMOS wafer (<NUM>) and having a first side (<NUM>) proximate the cavity (<NUM>) and a second side (<NUM>) distal the cavity (<NUM>);
wherein the cavity (<NUM>) is defined at least in part by a standoff (<NUM>; <NUM>) comprising an embedded via (<NUM>) in the standoff (<NUM>), and
wherein a liner (<NUM>) is formed in the via (<NUM>) and on the second side of the membrane (<NUM>), the liner (<NUM>) forming a conductive electrical path contacting the second side of the membrane (<NUM>) and electrically connecting the membrane (<NUM>) to the metallization layer (<NUM>).