Patent Description:
Constant increase in energy demand requires systems to be more efficient and reliable. The DAB DC-DC converter is known to provide benefits in terms of efficiency, power density, and bidirectional power transfer, as it operates with inherent soft switching (zero voltage switching) and high-frequency link. The three-phase variant of the DAB converter has potential for the higher power applications like DC grid connections and heavy-duty vehicles. For given semiconductor ratings, the <NUM>-Φ DAB results in reduced filtering requirements, reduced AC-link current harmonics and higher power transfer capability when compared to the single-phase DAB converter (<NUM>-Φ DAB).

With a DAB converter, an open-circuit fault may occur due to semiconductor device failure or gate drive circuit failure. A survey on reliability of power electronics reported that <NUM>% of component failures are related to gate drive and <NUM>% are related to the semiconductor device. Both these failures can stop the switching of the device and lead to an open-circuit fault. Further, with the adoption of wide-bandgap semiconductor devices, the rate of failure changes with <NUM>% of component failures related to the gate drive and <NUM>% related to the semiconductor device. In some prior work, the open-circuit fault mode operation, detection, and fault-tolerant strategies were discussed for <NUM>-Φ DAB. The post detection fault tolerant strategies were reported for <NUM>-Φ DAB in other works. However, these studies assume that the fault location is known and do not provide strategies to detect and identify the location of the fault.

Therefore, it would be advantageous to develop a system and method for detecting a fault condition to prevent damage to the converter.

This objective is solved by the features of the independent method and apparatus claim. The dependent claims recite advantageous embodiments of the invention.

In this disclosure, a detailed waveform analysis is presented for transient and steady-state fault operation of <NUM>-Φ DAB. Main symptoms of the converter during normal and fault conditions have been identified and a unique pattern in DC bias of phase currents under fault mode is noted. A logic-based fault diagnosis method is disclosed to detect the fault and identify the faulty transistor. The present invention provides a method of and system for detecting an open-circuit fault in a three-phase dual active bridge converter, as claimed.

The topology of three-phase dual active bridge (<NUM>-Φ DAB) converter <NUM> is shown in <FIG>. It consists of two three-phase active bridges <NUM>/<NUM> connected through a transformer-inductor arrangement <NUM>. The input bridge (referred to as primary bridge <NUM>) acts as an inverter and converts the DC input into high-frequency AC. These AC voltages and currents are transformed as per the turns ratio of the high-frequency transformer. The output bridge (referred to as the secondary bridge <NUM>) acts as a rectifier and converts the transformed AC to DC output.

The <NUM>-Φ DAB <NUM> is typically operated with <NUM>% duty cycle for each phase-leg 'χ' i.e. Tχ1 and Tχ2 are ON for <NUM>% time period (Ts) and are complementary to each other. The gate signals for different phase-legs in a bridge are shifted by <NUM>° with respect to each other. <FIG> shows the normal operating AC current waveforms of <NUM>-Φ DAB converter <NUM>.

The power transfer of the <NUM>-Φ DAB <NUM> is dependent on the phase-shift angle (ø) between the input and output bridge. The converter can have two modes of operation <NUM> ≤ ø ≤ π/<NUM> and π/<NUM>< ø ≤ π/<NUM>. The power transfer equations for <NUM>-Φ DAB <NUM> are given by (<NUM>), where D = nVo/Vin. For reverse power transfer, the phase shift (ø) is negative.

Under normal operation, there is no DC bias in the phase currents, and they are <NUM> shifted with respect to each other. Assuming no dead-time between the top and the bottom switches, the switching time period (Ts) under normal operation can be divided into <NUM> states based on the conducting devices. For <NUM> ≤ ø ≤ π/<NUM>, the AC phase current waveforms are shown in <FIG>. The conducting devices in each state (N1 to N18) are listed below the waveforms in the figure. The relationship between the currents and voltages across the phase inductors is given by (<NUM>).

Any component failure in the gate drive circuit of the transistor, or the failing of the transistor itself can lead to an open-circuit fault. Following assumptions are made to simplify the analysis.

<FIG> shows which transistors conduct in each state. Under normal operation of <NUM>-Φ DAB converter <NUM>, each transistor on the primary side <NUM> conducts for <NUM> out of <NUM> conduction states; on the secondary side <NUM>, each transistor conducts for only <NUM> out of <NUM> conduction states. This indicates that the effect of primary side <NUM> open-circuit fault will be much more pronounced than the fault on the secondary side <NUM>. In contrast, a single-phase DAB primary side transistor conducts <NUM> out of <NUM> conduction states and the secondary side transistor conducts for <NUM> out of <NUM> conduction states.

Primary Fault (TA1): <FIG> and <FIG> show how the phase currents change when the primary side TA1 is faulted. Both transient and steady-state waveforms under fault mode are shown. For a TA1 fault, the positive volt-seconds across LA reduces and the current iA develops a negative DC bias. The current iB and ic develop positive DC bias according to the equations (<NUM>). For a TA1 fault, the negative volt-seconds across LA reduces and the current iA develops a positive DC bias. The current iB and iC develop negative DC bias according to the equations (<NUM>). Since the phase A has no path for positive current, iA completely shifts below the zero line, resulting in a large DC bias.

Secondary Fault (Ta1): <FIG> and <FIG> show how the phase currents change when the secondary side Ta1 is faulted. No new states of conduction are observed, however, in steady-state, states N8 and N11 get skipped. For Ta1 fault, the negative volt-seconds across LA reduces and the current iA develops a positive DC bias. The currents iB and iC develop a negative DC bias according to equations (<NUM>). However, phase C DC bias decays to zero in post fault steady-state (as shown in <FIG>).

In similar manner, the DC bias pattern can be obtained for all the transistor failures and are shown in Table I. The DC bias pattern among the top and bottom transistors of each leg is reversed, and the pattern is cyclic among the three phases. Each fault mode has a unique signature which has been exploited to develop a fault identification scheme.

All the fault conditions listed in Table I produce a DC bias in the phase currents. This DC bias can cause the magnetic elements (inductors and transformers <NUM>) to saturate. It can also cause device failure and extra losses. Therefore, it is of interest to detect the fault as soon as possible and take corrective action. The devices usually handle high currents for a small amount of time. If the response is fast enough to prevent the transformer <NUM> from saturating (order of milliseconds), corrective action can be taken before catastrophic failure.

The fault diagnosis consists of three steps. First, detecting that a fault has occurred. Second, identifying the side of the fault. Third, identifying exactly which transistor has failed. <FIG> shows the graphic representation of step <NUM>. By passing the sensed currents (iA, iB, iC) through low-pass filter <NUM> or calculating the moving average of the sensed currents over a switching period, the DC bias value can be identified. Then, by comparing the value with zero the DC bias is positive of negative can be flagged. Flag X indicates whether the current iX has a DC bias or not. If there is no DC bias in the current iX, then flag X will be set. If the DC bias is positive, then XP is set. Else, if the DC bias is negative, then XN is set.

Step <NUM> is shown in <FIG>. If all the phase currents show DC Bias, then the fault is on the primary side (P is flagged). If the fault is not on primary side and the DC bias in some currents is present, then the fault is on the secondary side (S is flagged).

<FIG> show the faulty transistor detection scheme for the primary and secondary side, respectively (Step <NUM>). The scheme is presented as logic equations and is based on the DC bias pattern given in Table I.

The identification scheme for <NUM>-Φ DAB open-circuit fault was tested according to the rated specification listed in Table II. <NUM> V Silicon Carbide three-phase modules were used for both primary and secondary side active bridges <NUM>/<NUM>. Three single-phase hand-wound transformers <NUM> were connected in star-star configuration and external inductors were used to realize the phase inductances.

<FIG> shows the normal operating waveforms of the phase currents at rated power of <NUM> kW at <NUM> switching frequency. The phase currents are balanced and <NUM>° phase shifted with respect to each other. The DC bias is in the currents is zero and phase shift of <NUM>° between the primary bridge <NUM> and secondary bridge <NUM> of the converter <NUM> is observed (states N1+N2).

For experiments, a fault is introduced by blocking the gate pulse of the target transistor and the corresponding results are provided in this section.

<FIG> shows the phase currents when a primary side fault is introduced at the phase-A top switch (TA1). <FIG> show the observed currents on the primary side as well as the secondary side of the transformer <NUM>, respectively. It is seen that the DC bias get reflected and is present on both sides of the transformers <NUM>. This indicates that sensing of currents on one-side of the transformer <NUM> is sufficient for detecting and identification of the faults on both sides of the transformer <NUM>.

The ability to sense current on one side provides a cost and design benefit especially in high-power and high-gain converters. The high-current and high-frequency current sensors are very costly compared to the low-current and high-frequency sensors. The results in <FIG> show that in the high-power/high-gain converters, the current sensors can be placed on the high-voltage/low-current side only and the detection scheme can identify the faults on both sides of the transformer. Moreover, since the identification scheme is based on the DC bias of the phases current and not the exact waveshape of the currents, the cost of the sensors can be further reduced by using the low current and low bandwidth sensors. At a minimum, detection can be accomplished with <NUM> current sensors and no additional circuit modification.

Note that the DC bias will eventually shift to the magnetizing current and risk transformer saturation if corrective measures are not taken. However, the results indicate that the magnetizing current (iA - nia) rises much slower (order of milliseconds). Therefore, the detection scheme is capable of detecting the faults much before the risk of saturation.

<FIG> show the phase current waveforms when a primary side fault is introduced at the phase-A top switch (TA1). <FIG> shows the waveform signature and <FIG> shows the time averaged waveforms over Ts. The averaged waveforms show the DC bias built in the phase currents in the fault mode. The current iA shows a negative DC bias, and the currents iB, ic show a positive DC bias. This pattern matches the predicted patter in Table I.

<FIG> also indicates that a threshold of <NUM>% (<NUM> pu) with respect to the input DC current can be used for fault indication using the logic-based scheme. The threshold or the hysteresis band is required to avoid false triggers due to noise in the sensed signals.

<FIG> show the phase current waveforms when a secondary side fault is introduced at the phase-A top switch (Ta1). <FIG> shows the waveform signature and <FIG> shows the time averaged waveforms over Ts. The averaged waveforms show the DC bias built in the phase currents in the fault mode. The current iA shows a positive DC bias, and the currents iB, ic develop a negative DC bias in transient mode and the DC bias in current ic decays to zero in steady-state. This pattern matches the predicted pattern in Table <NUM>. <FIG> also indicates that a threshold of <NUM>% (<NUM> pu) with respect to the input DC current can be used for fault identification using the logic-based scheme.

A comparison of <FIG> and <FIG> indicates that the impact of a primary side fault is much more pronounced than a secondary side fault. Since under normal mode the primary side transistor conducts for <NUM> of <NUM> states and the secondary transistor only conducts <NUM> out of <NUM> states.

<FIG> shows that the phase currents can see up to <NUM> pu of DC bias under the primary fault mode operation, indicating that a corrective action is required. In contrast, <FIG> shows that the DC bias produced in the phase currents is less than <NUM> pu under the secondary fault mode operation. It indicates that a <NUM>-Φ DAB converter <NUM> can be run as a normal converter even with a secondary side fault, since the components are usually rated at more than <NUM> times the nominal/standard requirements. This is a benefit of a <NUM>-Φ DAB converter <NUM> over a <NUM>-Φ DAB converter, where the impact of a secondary side fault is almost equally pronounced as a primary side fault.

<FIG> show the detection signals using the fault diagnosis scheme when the converter is subjected to faults. The primary and secondary fault detection signals were observed using DAC signals from a micro-controller <NUM>. Under no-fault normal operation both the DAC signals will remain at <NUM> V. The fault identification scheme can be implemented using a threshold of <NUM>% (<NUM> pu) with respect to the input DC current.

<FIG> shows the detection signals when a fault is introduced at the primary side phase-A top switch (TA1). The scheme correctly identifies the faulty transistor (TA1) as the primary side detection signal rises within <NUM> switching cycles from the fault trigger. The secondary side detection signal remains at <NUM> V indicating no-fault on the secondary side. <FIG> shows the detection signals when a fault is introduced at the secondary side phase-A top switch (Ta1). The scheme correctly identifies the faulty transistor (Ta1) as the secondary side detection signal rises within <NUM> switching cycles from the fault trigger. The primary side detection signal remains at <NUM> V indicating no-fault on the primary side.

The detection method can be implemented via an electronic controller <NUM> which may include one or more of the following: an electronic data processor, an interface <NUM>, a data bus, a data storage device, a data port, and a user interface (e.g., electronic display). The electronic data processor and the data storage device may be coupled to the data bus to facilitate communication of data messages among the electronic data processor, the data storage device, the data port, and the user interface. In some embodiments, each of the primary switches of the DAB <NUM> has a unique corresponding identifier and each of the secondary switches has a unique corresponding identifier. The electronic data processor comprises one or more of the following: a microprocessor, a microcontroller, a programmable logic device, a programmable gate array, an arithmetic logic unit, a Boolean logic unit, an electronic logic circuit or system, a digital circuit, a digital signal processor (DSP), and application specific integrated circuit (ASIC), or another data processing device. In one embodiment, the electronic data processor can execute software instructions stored in the data storage device.

In this disclosure, a diagnosis scheme has been described which identifies a faulty transistor in an open-circuit fault in a <NUM>-Φ DAB converter <NUM>. The AC-link current waveform is systematically analyzed in normal operating and fault conditions, and the DC bias patterns unique to individual transistor failure are identified. The logic-based scheme requires only three low-bandwidth current sensors, with no additional circuit modification.

Additional consideration can be given to the magnitude of DC bias with respect to the fault location, the design of hysteresis in DC bias detection and saturation of transformer-inductor arrangement. In addition, the manner in which the DC bias in the secondary side current is reflected on to the primary side sensors can be evaluated. Stated differently, the pronounced effect of fault in the output currents of the primary converter <NUM> of the <NUM>-Φ DAB converter <NUM> causes excessive rise in the magnetizing current of the isolation transformer <NUM>. The three-phase currents supplied by the primary converter <NUM> have a significant DC component. The fault detection method can be used to promptly shuts down the converter <NUM> well before the DC/DC power conversion system could destroy itself upon occurrence of an open circuit fault in the primary converter <NUM>. Additionally, should the open circuit fault occur in the secondary converter <NUM>, the method serves as a watch-dog or monitoring system to keep the converter <NUM> operational without any need for power derating. Therefore, the fault detection system and method could serves as a watchdog when the DC/DC power conversion system needs to work under limp-home mode and keep vehicle auxiliaries functional until next opportunity for maintenance.

Claim 1:
A method of detecting an open-circuit fault in a three-phase dual active bridge converter (<NUM>) comprising a primary side converter (<NUM>), a secondary side converter (<NUM>), and a transformer (<NUM>), the method comprising:
detecting that a fault has occurred, wherein detecting the fault comprises:
detecting polarity states of a DC signal component in each phase of an output terminal of the primary side converter (<NUM>) during one or more successive sampling intervals;
wherein detecting polarity states of the DC signal component comprises sensing a phase current; and identifying a DC bias in the phase current,
comparing the polarity states to a table of known DC biases which corresponds to a fault and matching the polarity states to the corresponding fault based on the polarity states and the known DC biases during one or more sampling intervals
identifying whether the fault occurred on the
primary side converter (<NUM>) or the secondary side converter (<NUM>) of the dual active bridge converter (<NUM>) by assigning the fault to the primary side converter (<NUM>) if each phase current shows a DC bias or assigning the fault to the secondary side converter (<NUM>) if the fault is not present on the primary side converter (<NUM>) and at least one phase current shows a DC bias; and
identifying exactly which transistor of the three-phase dual active bridge converter (<NUM>) has failed based on the table of known DC biases for a fault.