Patent Description:
A NFC device can operate as a reader or a card. When operating as a card, a signal received by the NFC device is AM/phase modulated with a minimum modulated-to-carrier ratio in the order of <NUM>%, and a carrier frequency mat have a few kHz (kilo hertz) offset. The carrier is provided by a transmitter of a NFC device (operating in reader mode) through the antenna coupling system to generate power for the NFC device in card mode. The NFC device in card mode will AM/phase modulate this carrier signal through the antenna coupling system. However, the NFC device operating in reader mode receives/senses its own transmitted carrier. The signal received by the receiver on the NFC device operating in reader mode could have a carrier-to-modulated signal ratio as high as <NUM> dB. The carrier needs to be removed/cancelled so that the transmitted modulated signal from the NFC device operating in card mode can be processed by the NFC device operating in reader mode.

Some receivers use mixers to first down convert the input signal and then remove the carrier using AC (alternating current) blocking capacitors or DC (direct current) tracking loops. The receiver converts the carrier to DC and no clipping is allowed, requiring a high dynamic range. NFC mixers may have a gain of <NUM> or less and may directly sample the signal with capacitors in the picofarad range (because of KT/C noise requirements) causing glitches and requiring up and/or down noise conversion. Other receivers may process the carrier together with the modulated signal, requiring almost 90dB SNR (signal-to-noise ratio) at <NUM>. Other receivers may cancel the carrier before the mixing operation, using a <NUM> sine wave generator with programmable amplitude and phase (I/Q up mixer) together with a tracking loop.

<CIT> describes how static and dynamic DC offsets in receivers may be cancelled in two stages using a digitally implemented offset-correction loop.

<CIT> discloses a NFC receiver configured to cancel the carrier before the mixing operation using a tracking loop and a wave signal at the carrier frequency.

The present invention is defined by the features of independent claim <NUM>.

Generally, there is provided, a NFC receiver that suppresses a carrier while in reader mode using a current mode quadrature track and hold (T&H) mixer and a low frequency high resolution current steering digital-to-analog converter (DAC). The quadrature T&H mixer circuit has programmable gain and bandwidth, constant input impedance, and samples an input signal at twice the input frequency. An averaging circuit provides an average of two successive samples to return the output frequency of the receiver to be the same as the input frequency of <NUM> megahertz (MHz). The current steering DAC provides a DC or low frequency current that is subtracted from an input current to suppress the carrier in response to a control loop that controls a current level of the DAC to match a level of the carrier to be removed.

The carrier is suppressed in a direct conversion mixer with a bandpass response. In the described implementation, the DACs are controlled independently in order to suppress or partially suppress the average input current during a tracking phase of the T&H circuits. The carrier is suppressed prior to amplification in a mixer leading to lower input referred noise, allowing for more gain, and better sensitivity.

In one embodiment, there is provided, a near-field communication (NFC) receiver as defined in claim <NUM>. This embodiment represents a solution to the problem of how to increase the gain and sensitivity of an NFC receiver. The receiver may further include a variable input resistance coupled to the first and second input terminals. The receiver may further include a baseband circuit having an output for controlling an output level of the DAC in response to receiving the digital representation of the amplified output signal. The baseband circuit may provide gain control to the amplifier. The receiver may further include a parallel-connected resistor and capacitor coupled between the input and the output of the track-and-hold circuit. The input of the track-and-hold circuit may include a positive input and a negative input, and wherein the mixer may further include: a first switch having a first terminal coupled to the first input terminal of the receiver and a second terminal coupled to the positive input; a second switch having a first terminal coupled to the first input terminal of the receiver and a second terminal coupled to the negative input; a third switch having a first terminal coupled to the second input terminal of the receiver and a second terminal coupled to the positive input; and a fourth switch having first terminal coupled to the second input terminal of the receiver and a second terminal coupled to the negative input. The receiver may further include a first capacitor and a first resistor coupled together in series and to the first input terminal, and a second capacitor and a second resistor coupled together in series and to the second input terminal.

<FIG> illustrates NFC receiver <NUM> in accordance with an embodiment. Receiver <NUM> may be implemented on one or more integrated circuits fabricated using conventional semiconductor manufacturing processes. NFC receiver <NUM> includes resistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, amplifier <NUM>, capacitors <NUM> and <NUM>, switches <NUM> and <NUM>, DACs <NUM> and <NUM>, mixers <NUM> and <NUM>, T&H circuits <NUM> and <NUM>, averaging circuits <NUM> and <NUM>, amplifiers <NUM> and <NUM>, ADCs <NUM> and <NUM>, and digital signal processor <NUM>. Mixer <NUM> includes mixer switch portion <NUM> and switch <NUM>. Mixer <NUM> includes mixer switch portion <NUM> and switch <NUM>. The circuit elements of NFC receiver <NUM> form two quadrature channels I and Q. The I channel main signal path includes DAC <NUM>, mixer portion <NUM>, T&H <NUM>, averaging circuit <NUM>, amplifier <NUM>, and ADC <NUM>. The Q channel main signal path includes DAC <NUM>, mixer portion <NUM>, T&H <NUM>, averaging circuit <NUM>, amplifier <NUM>, and ADC <NUM>.

Receiver <NUM> is configured to receive input signals labeled "INPUT SIGNALS" while operating in reader mode. The input signals include a modulated portion and a carrier portion. The carrier portion may have a very high carrier-to-modulated signal ratio, making it difficult to demodulate the modulated portion without first removing or suppressing the carrier. Resistances labeled REXTP and REXTN as "seen" by the input signals (INPUT SIGNALS) are provided by resistors <NUM> and <NUM>. In one embodiment, resistors <NUM> and <NUM> are implemented externally to an integrated circuit implementation of receiver <NUM>. Variable resistors <NUM> and <NUM> provide a tunable attenuator for NFC receiver <NUM>. Amplifier <NUM> provides a voltage buffer, or interface, between mixer switch portions <NUM> and <NUM> and resistors <NUM>, <NUM>, <NUM>, and <NUM>. Resistors <NUM> and <NUM>, and variable resistors <NUM> and <NUM> provide a variable attenuation in response to receiving control signal labeled "ATTENUATION CONTROL". Mixer portions <NUM> and <NUM> receive the output signals from amplifier <NUM> and provide I and Q outputs. Mixers <NUM> and <NUM> function to subtract a current produced by DACs <NUM> and <NUM> from a current of the output signals produced by amplifier <NUM>. This serves to at least partially remove the carrier from input signals INPUT SIGNALS. Digital-to-analog converters <NUM> and <NUM> are N-bit DACs and provide a near DC level signal to mixer portions <NUM> and <NUM>. Digital-to-analog converters <NUM> and <NUM> and T&H circuits <NUM> and <NUM> are clocked at twice the input frequency of <NUM> as shown in <FIG> by switches <NUM> and <NUM>. The two DACs <NUM> and <NUM> are continuously controlled by DSP <NUM>, so that the DC level out of ADCs <NUM> and <NUM> is minimized. When receiver <NUM> is operating in card mode the DACs are off.

The T&H circuits <NUM> and <NUM> receive the I and Q outputs from mixer circuits <NUM> and <NUM> and provide voltage samples to averaging circuits <NUM> and <NUM>. Averaging circuits <NUM> and <NUM> output an average of two consecutive samples. After averaging, the voltage samples are amplified by amplifiers <NUM> and <NUM> and converted to digital by ADC circuits <NUM> and <NUM>. The output of ADC circuits <NUM> and <NUM> is provided at <NUM>. A gain provided by amplifiers <NUM> and <NUM> is controlled with a gain control signal (GAIN CONTROL) provided by DSP <NUM>. Digital Signal Processing block <NUM> monitors the I/Q ADCs output data and manages the operation of receiver <NUM> including the attenuation, gain, and the current provided by DACs <NUM> and <NUM>. <FIG> illustrates a portion of NFC receiver <NUM> of <FIG> in more detail. Input signals VIN_P and VIN_N are provided to AC coupling capacitors <NUM> and <NUM> and variable resistors <NUM> and <NUM>. AC coupling capacitors <NUM> and <NUM> function to remove low frequency noise. As shown in <FIG>, mixer portion <NUM> includes switches <NUM>, <NUM>, <NUM>, and <NUM> and mixer portion <NUM> includes switches <NUM>, <NUM>, <NUM>, and <NUM>. Switch function <NUM> is connected to the output of DAC <NUM> and includes switches <NUM> and <NUM>. Switch function <NUM> is connected to the output of DAC <NUM> and includes switches <NUM> and <NUM>. Averaging circuit <NUM> includes switches <NUM>, <NUM>, <NUM>, and <NUM> and adders <NUM> and <NUM>. Averaging circuit <NUM> includes switches <NUM>, <NUM>, <NUM>, and <NUM>, and adders <NUM> and <NUM>. Control signals for controlling the switches are provided by DSP <NUM> or another control circuit (not shown). The conductors for conveying the control signals are not shown in <FIG> in the interest of simplicity and clarity. In mixer portion <NUM>, switches <NUM> and <NUM> are controlled by control signal TRACK_P1_I, switches <NUM> and <NUM> are controlled by control signal TRACK_P2_I, and switches <NUM> and <NUM> are controlled by control signal TRACK_P1|P2_I. Control signal TRACK_P1|P2_I is a concatenation of control signals TRACK_P1_I and TRACK_P2_I. In mixer portion <NUM>, switches <NUM> and <NUM> are controlled by control signal TRACK_P1_Q, switches <NUM> and <NUM> are controlled by control signal TRACK_P2_Q, and switches <NUM> and <NUM> are controlled by control signal TRACK_P1|P2_Q. Control signal TRACK_P1|P2_Q is a concatenation of control signals TRACK_P1_Q and TRACK_P2_Q. Mixers portions <NUM> and <NUM> split the input signals VIN_P and VIN_N into the I and Q channels. For example, in mixer circuit <NUM>, switches <NUM> and <NUM> couple input signal VIN_P to both inputs of T&H circuit <NUM> and switches <NUM> and <NUM> couple input signal VIN_N to both inputs of T&H circuit <NUM>. Likewise, in mixer circuit <NUM>, switches <NUM> and <NUM> couple input signal VIN_N to both inputs of T&H circuit <NUM>, and switches <NUM> and <NUM> couple input signal VIN_P to both inputs of T&H circuit <NUM>. Mixers <NUM> and <NUM> connect input resistors <NUM> and <NUM> to either the I or Q channel T&H amplifier inputs.

In operation, the input voltage is first converted to a current. In each of the I and Q channel paths, the switches and control signals of mixers <NUM> and <NUM> cause a current from DAC <NUM> to be combined with a current from input signals VIN_P and VIN_N to remove, or subtract, the carrier from the input signals VIN_P and VIN_N. DACs <NUM> and <NUM> function as relatively low frequency current steering DACs having an N-bit resolution. The level of the current contributed by DACs <NUM> and <NUM> is determined by DSP <NUM> and the output signals VOUT I_P/VOUT I_N and VOUT Q _P/VOUT Q_N in a feedback loop. Track-and-hold circuits <NUM> and <NUM> receive the currents from mixers <NUM> and <NUM>, respectively, and operate at <NUM>, twice the input frequency. After the track and hold operation, every two successive samples from T&H circuits <NUM> and <NUM> are averaged so that the input and output frequencies of receiver <NUM> are the same, e.g., <NUM>. Switch <NUM> is controlled by a clock signal CLK_IN and connected between input resistors <NUM> and <NUM> in order to maintain a constant input impedance to T&H circuits <NUM> and <NUM>. Clock signal CLK_IN is provided at <NUM> times the input frequency of <NUM>.

<FIG> is a timing diagram of the control signals of the portion of NFC receiver <NUM> of <FIG>. Each of the control signals is a relatively short duration pulse. When a control signal pulses high, the corresponding switch closes and is closed for the duration of the pulse. Note that in another embodiment, the control signals may be made to pulse low instead of high. When either the P1 or P2 switches are closed, the current from the DAC is subtracted from the input signals VIN_P and VIN_N. For example, time t0 marks a rising edge of control signals TRACK_P1_I and TRACK P1|P2_I. Therefore, at time t0, switches <NUM>, <NUM>, <NUM> and <NUM> close connecting the VIN_P and VIN_N currents to the inputs of T&H <NUM> at the same time the current from DAC <NUM> is connected to the inputs of T&H <NUM>. The currents are combined (subtracted in this case) so that the carrier portion of the input currents is at least partially removed by the current from DAC <NUM>. Also, in averaging circuit <NUM>, the current from two successive samples is averaged at time t0. At time t4, the same switch operation described above is repeated.

Likewise, for the Q channel, at time t1, control signals TRACK_P1_Q and TRACK P1|P2_Q are asserted. Switches <NUM>, <NUM>, <NUM>, and <NUM> close, connecting the VIN_P and VIN_N currents to the inputs of T&H <NUM> at the same time the current from DAC <NUM> is connected to the inputs of T&H <NUM>. The currents are combined so that the carrier portion of the input currents is at least partially removed by the current from DAC <NUM>. Also, in averaging circuit <NUM>, the current from two successive samples is averaged at time t1. At time t5, the same switch operation described above is repeated.

At time t2, control signals TRACK_P2_I and TRACK P1|P2_I are asserted high. Switches <NUM>, <NUM>, <NUM>, and <NUM> are closed, again connecting the VIN_P and VIN_N currents to the inputs of T&H <NUM> at the same time the current from DAC <NUM> is connected to the inputs of T&H <NUM>. The state of the control signals at time t2 is repeated at time t6. Control signals TRACK_P1_I and TRACK_P2_I are shifted <NUM> degrees from each other, and TRACK_P1_Q and TRACK_P2_Q are shifted <NUM> degrees from each other. Also, the control signals are aligned with the input signals VIN_P and VIN_N as illustrated in <FIG>. This provides little or no low frequency error. The tracked current during TRACK_P1_I is almost identical to the current tracked during TRACK _P2 _I and the rate is <NUM>, or twice the input signal frequency.

Clock signal CLK_IN is provided to control the operation of switch <NUM>. The frequency of clock signal CLK_IN is four times higher than for input signals VIN_P and VIN_N and is asserted high during the times when none of the other switches are closed. This provides a relatively constant input impedance and avoids a high impedance state for the input signals. <FIG> illustrates the I channel path of the NFC receiver portion of <FIG> in more detail. The Q channel path is substantially identical to the I channel path and operates the same. More specifically, in <FIG>, T&H circuit <NUM> includes T&H amplifier <NUM> and parallel RC (resistor capacitor) networks <NUM> and <NUM>. Track and hold amplifier <NUM> has positive (+) and negative (-) inputs and outputs. The parallel RC networks <NUM> and <NUM> are each connected between an input and a corresponding output of a T&H amplifier <NUM>. Parallel RC network <NUM> includes capacitor <NUM>, switch <NUM> and resistor <NUM>. Parallel RC network <NUM> includes capacitor <NUM>, switch <NUM>, and resistor <NUM>. In parallel RC network <NUM>, switch <NUM> and resistor <NUM> are connected in series. The series-connection of switch <NUM> and resistor <NUM> are connected in parallel with capacitor <NUM>. The components of parallel RC network <NUM> are connected together the same as parallel RC network <NUM>.

<FIG> illustrates various signals of the NFC receiver portion of <FIG>. The two periods of input signals VIN_P and VIN_N are sinusoidal and <NUM> out of phase with each other. Also, the amplitude of the input signals during the second period is lower than the amplitude of the first period, where the higher amplitude represents a logic one and the lower amplitude represents a logic zero. The outputs DAC_P and DAC_N of current DAC <NUM> are also illustrated as a DC or very low frequency signal. Output signals VOUT_P and VOUT_N are digital signals having the same logic states as the input signals VIN_P and VIN_N. Note that signals VIN_P, VIN_N, DAC_P, and DAC_N are drawn relative to the horizontal dashed line, where the negative signal is below the dashed line and the positive signal is above the dashed line. Control signals TRACK_P1_I, TRACK_P2_I, and TRACK_P1|P2_I are the same as shown in <FIG> and described above. Note that times t0 - t3 correspond to the peak amplitudes of signals VIN_P and VIN_N and align with the falling edges of control signals TRACK_P1_I, TRACK_P2_I, and TRACK_P1|P2_I. In a conventional sample and hold circuit, a capacitor is charged and then the input is sampled. In comparison, in T&H circuit <NUM>, a current is provided in the parallel RC network when the switches are closed during a tracking phase. The current in the parallel RC network is not necessarily equal to the input current. Short pulses of the control signals are used to minimize changes in the input voltage during the tracking phase. Current steering DAC <NUM> is used to generate a DC or low frequency current. The level of the current is determined to reduce or eliminate the carrier from the input signal of NFC receiver <NUM>. In mixer <NUM>, the current from DAC <NUM> is subtracted from the input current when either the TRACK_P1_I or TRACK_P2_I switches are closed. The resulting current from mixer <NUM> feeds parallel RC networks <NUM> and <NUM> during the tracking phase of T&H circuit <NUM>. The parallel RC networks <NUM> and <NUM> provide a low pass filter to remove high frequency noise and reduce input transients. At the end of the tracking phase, a voltage is held across capacitors <NUM> and <NUM> when switches <NUM> and <NUM> are opened. DAC <NUM>, T&H circuit <NUM>, and DSP <NUM> provide a mixed signal tracking loop so that the output signals VOUT_P and VOUT_N converge to the averaged input current over one tracking phase. This operation suppresses the carrier before amplification, thus allowing gain to be applied using resistors <NUM> and <NUM> and amplifiers <NUM> and <NUM> (<FIG>). The resistance of resistor <NUM> divided by the resistance of resistor <NUM> is greater than one. The gain/cut off frequency may be adapted to the modulated signal bandwidth, allowing the overall mixer input referred noise to be significantly reduced. While high resolution is needed for current DAC <NUM> (to allow amplification of the modulated signal) DAC <NUM> can operate at a very low frequency and therefore is not too difficult to implement. In one embodiment, DAC <NUM> is a <NUM>-bit DAC.

The ability to suppress the carrier as described using two T&H circuits running at twice the input frequency provides relatively constant input impedance, averaging of two successive samples, allows for programmable gain and bandwidth, and allows for larger swing VIN_P and VIN_N with a better signal-to-noise ratio (SNR).

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Claim 1:
A near-field communication, NFC, receiver (<NUM>) comprising:
- first and second input terminals for receiving first and second input signals, respectively, wherein the first and second input signals include a modulated portion and a carrier portion;
- a digital-to-analog converter, DAC (<NUM>, <NUM>), for providing a current;
- a mixer (<NUM>, <NUM>) having a first input coupled to receive the first and second input signals and a second input coupled to receive the current from the DAC (<NUM>, <NUM>), and in response, the mixer (<NUM>, <NUM>) is configured to provide a combined current by subtracting said current from the DAC from an input current;
- a track-and-hold circuit (<NUM>, <NUM>) having an input coupled to receive the combined current and an output to provide a series of output samples;
- an averaging circuit (<NUM>, <NUM>) coupled to the output of the track-and-hold circuit (<NUM>, <NUM>), the averaging circuit (<NUM>, <NUM>) having an input coupled to receive the series of output samples from the track-and-hold circuit (<NUM>, <NUM>), and an output for providing an output signal that is an average of two consecutive output samples of the track-and-hold circuit (<NUM>, <NUM>);
- an amplifier (<NUM>, <NUM>) configured to receive the output signal from the averaging circuit (<NUM>, <NUM>) and to provide an amplified output signal; and
- an analog-to-digital converter, ADC (<NUM>, <NUM>), coupled to receive the amplified output signal and to provide a digital representation of the amplified output signal.