Patent Description:
Semiconductor devices and integrated circuit (IC) chips have found numerous applications in the fields of physics, chemistry, biology, computing, and memory devices. An example of a memory device is a non-volatile (NV) memory device. NV memory devices are programmable and have been extensively used in electronic products due to their ability to retain data for long periods, even after the power has been turned off. Exemplary categories for NV memory may include resistive random-access memory (ReRAM), erasable programmable read-only memory (EPROM), flash memory, ferroelectric random-access memory (FeRAM), and magnetoresistive random-access memory (MRAM).

A ReRAM device includes a switching layer that is positioned between a bottom electrode and a top electrode. The ReRAM device can be programmed by changing the resistance across the switching layer to provide different content-storage states, namely a high-resistance state (HRS) and a low-resistance state (LRS), representing the stored bits of data. The switching layer can be modified by applying a programming voltage sufficient to create one or more conductive filaments bridging across the thickness of the switching layer, which sets the low-resistance state. The conductive filaments may be formed, for example, by the diffusion of a conductive species (e.g., metal ions) from one or both of the electrodes into the switching layer. The conductive filaments can be destroyed, also by the application of a programming voltage, to reset the resistive memory element to the high-resistance state. The content-storage state can be read by measuring a voltage drop across the resistive memory element after it is programmed. Document <CIT> discloses, for example, a memory device comprising: a gate electrode; a first insulation layer on the gate electrode; a first conductive pattern and a second conductive pattern, which are spaced apart from each other on the first insulation layer; a channel pattern disposed on the first insulation layer to connect the first conductive pattern and the second conductive pattern; and an interface layer disposed between the channel pattern and the first insulation layer and having a hydrogen atom content ratio (atomic %) greater than that of the first insulation layer. Document <CIT> discloses, for example, a memory device comprising: a first electrode; a memory layer stack located on the first electrode and including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer comprising at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least <NUM>% and comprising hydrogen atoms; and a second electrode located over the memory layer stack. Document <CIT> discloses, for example, a memory device comprising: a first electrode comprising a first side surface and a second side surface opposite to the first side surface; a passivation layer arranged laterally alongside the first side surface of the first electrode; a switching layer arranged laterally alongside the passivation layer; and a second electrode arranged along the switching layer. Document <CIT> discloses, for example, a protonic resistive memory comprising: a substrate having first and second opposing surfaces; first and second contacts disposed on the second surface of the substrate, the first and second contacts spaced apart and provided from a hydrogen inert material; a first metal oxide layer having a first surface disposed over at least a portion of the second surface of the substrate between the first and second contact to form a channel region, the first metal oxide layer disposed over at least a portion of the first contact and over at least a portion of the second contact, the first metal oxide layer forming a metal oxide channel layer; a proton conducting solid electrolyte layer having a first surface disposed over the second surface of the first metal oxide layer, the proton conducting solid electrolyte layer comprising a phosphorus-doped oxide (P-doped oxide); a protonated reservoir layer having a first surface disposed over a second surface of the proton conducting solid electrolyte layer; and a third contact disposed over the protonated reservoir layer to define a gate structure.

The invention according to the appended independent claim <NUM> provides a memory structure including a source electrode, a drain electrode, a control electrode laterally between the source electrode and the drain electrode, the control electrode having a first side and a second side, a hole generating layer above the control electrode, a dielectric channel layer above the hole generating layer, the dielectric channel layer contacts the source electrode and the drain electrode, a first spacer layer on the first side of the control electrode, and a second spacer layer on the second side of the control electrode, in which the first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer.

Further aspects of the invention are set out in the dependent claims <NUM>-<NUM>.

The present disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the present invention. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

Various illustrative embodiments of the present invention are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the present invention.

Referring to <FIG> and <FIG>, the example memory structures <NUM> includes a source electrode <NUM>, a drain electrode <NUM>, a control electrode <NUM> laterally between the source electrode <NUM> and the drain electrode <NUM>, a hole generating layer <NUM> above the control electrode <NUM>, a dielectric channel layer <NUM> above the hole generating layer <NUM>. The dielectric channel layer <NUM> contacts or directly contacts the source electrode <NUM> and the drain electrode <NUM>. In some implementations, the hole generating layer <NUM> is on or directly on the control electrode <NUM>, and the dielectric channel layer <NUM> is on or directly on the hole generating layer <NUM>. The source electrode <NUM>, the drain electrode <NUM>, the dielectric channel layer <NUM>, the hole generating layer <NUM>, and the control electrode <NUM> may provide a memory cell, or a single memory cell unit. The memory structures <NUM> described herein may be formed above a substrate (not shown).

The control electrode <NUM> has a first side 118a and a second side 118b. The first side 118a of the control electrode <NUM> may be oppositely facing the second side 118b of the control electrode <NUM>. The control electrode <NUM> may have a lower surface 118c. The lower surface 118c may adjoin the first side 118a and the second side 118b. The hole generating layer <NUM> may have a first side 116a and a second side 116b. A first spacer layer <NUM> covers at least the first side 118a of the control electrode <NUM> and the first side 116a of the hole generating layer <NUM>. A second spacer layer <NUM> covers at least the second side 118b of the control electrode <NUM> and the second side 116b of the hole generating layer <NUM>. The first spacer layer <NUM> and the second spacer layer <NUM> isolate the source electrode <NUM> and the drain electrode <NUM> from the control electrode <NUM> and the hole generating layer <NUM>. For example, the first spacer layer <NUM> may be on or directly on the first side 118a of the control electrode <NUM> and the first side 116a of the hole generating layer <NUM> while the second spacer layer <NUM> may be on or directly on the second side 118b of the control electrode <NUM> and the second side 116b of the hole generating layer <NUM>.

The dielectric channel layer <NUM> may have a first side 114a and a second side 114b. The first side 114a may contact or directly contact the source electrode <NUM> and the second side 114b may contact or directly contact the drain electrode <NUM>. The first side 114a of the dielectric channel layer <NUM> may have an upper portion <NUM> and a lower portion <NUM>. The second side 114b of the dielectric channel layer <NUM> may have an upper portion <NUM> and a lower portion <NUM>. The first spacer layer <NUM> may overlap with the lower portion <NUM> of the first side 114a of the dielectric channel layer <NUM>. The second spacer layer <NUM> may overlap with the lower portion <NUM> of the second side 114b of the dielectric channel layer <NUM>. For example, the first spacer layer <NUM> may be on or directly on the lower portion <NUM> of the first side 114a of the dielectric channel layer <NUM>. The second spacer layer <NUM> may be on or directly on the lower portion <NUM> of the second side 114b of the dielectric channel layer <NUM>. The source electrode <NUM> may contact or directly contact the upper portion <NUM> of the first side 114a of the dielectric channel layer <NUM>. The drain electrode <NUM> may contact or directly contact the upper portion <NUM> of the second side 114b of the dielectric channel layer <NUM>.

The source electrode <NUM> may have an upper surface 110t. The drain electrode <NUM> may have an upper surface 112t. The dielectric channel layer <NUM> may have an upper surface 114t. The upper surface 110t of the source electrode <NUM>, the upper surface 112t of the drain electrode <NUM>, and the upper surface 114t of the dielectric channel layer <NUM> may be substantially coplanar with each other. For example, the upper surface 114t of the dielectric channel layer <NUM> may be substantially coplanar with the upper surface 110t of the source electrode <NUM> and the upper surface 112t of the drain electrode <NUM>.

Interconnect structures, such as vias, landing pads, and conductive lines, may be formed above or below the control electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM>. These interconnect structures may provide routing or wiring of electrical signals and may connect various devices or components within an IC chip to perform desired functions. As shown, the exemplary memory structures <NUM> may further include a first interconnect structure <NUM> below the control electrode <NUM>, a second interconnect structure <NUM> above the source electrode <NUM>, and a third interconnect structure <NUM> above the drain electrode <NUM>. A conductive line <NUM> may be on the second interconnect structure <NUM> and a conductive line <NUM> may be on the third interconnect structure <NUM>. In some implementations, the first interconnect structure <NUM> may contact or directly contact the lower surface 118c of the control electrode <NUM>. The second interconnect structure <NUM> may contact or directly contact the upper surface 110t of the source electrode <NUM>. The third interconnect structure <NUM> may contact or directly contact the upper surface 112t of the drain electrode <NUM>. In the example shown in <FIG>, the first interconnect structure <NUM> may be a via. The first interconnect structure <NUM> may be coupled and disposed on a conductive line <NUM>. In the example shown in <FIG>, the first interconnect structure <NUM> may be a landing pad. Alternatively, the first interconnect structure <NUM> shown in <FIG> may be a landing pad, and the first interconnect structure <NUM> shown in <FIG> may be a via, in which the first interconnect structure <NUM> may be coupled and disposed on a conductive line.

In the example shown in <FIG>, the second interconnect structure <NUM> may overlap with the source electrode <NUM> and the dielectric channel layer <NUM> such that the second interconnect structure <NUM> may contact or directly contact the upper surface 110t of the source electrode <NUM> and the upper surface 114t of the dielectric channel layer <NUM>. The third interconnect structure <NUM> may overlap with the drain electrode <NUM> and the dielectric channel layer <NUM> such that the third interconnect structure <NUM> may contact or directly contact the upper surface 112t of the drain electrode <NUM> and the upper surface 114t of the dielectric channel layer <NUM>. Alternatively, in the example shown in <FIG>, the second interconnect structure <NUM> may only contact or directly contact the upper surface 110t of the source electrode <NUM>, and the third interconnect structure <NUM> may only contact or directly contact the upper surface 112t of the drain electrode <NUM>.

Advantageously, having the hole generating layer <NUM> above the control electrode <NUM> and the dielectric channel layer <NUM> above the hole generating layer <NUM> may enable the first interconnect structure <NUM> to be positioned below the control electrode <NUM> while the second interconnect structure <NUM> and the third interconnect structure <NUM> to be positioned above the source electrode. The first interconnect structure <NUM> may also be formed in a different dielectric region from the second interconnect structure <NUM> and the third interconnect structure <NUM>. The lateral distance between the second interconnect structure <NUM> and the third interconnect structure <NUM> can be reduced since the first interconnect structure <NUM> connecting to the control electrode does not need to be arranged laterally between the second interconnect structure <NUM> and the third interconnect structure <NUM> and does not need to be in the same dielectric region and the second interconnect structure <NUM> and the third interconnect structure <NUM>. The memory structures <NUM> described herein can achieve a smaller size when compared to other memory structures where an interconnect structure is arranged laterally between the second interconnect structure and the third interconnect structure <NUM>.

The exemplary memory structures <NUM> may also include a first dielectric region <NUM>, a second dielectric region <NUM> on or directly on the first dielectric region <NUM>, and a third dielectric region <NUM> on or directly on the second dielectric region <NUM>. The dielectric regions <NUM>, <NUM>, <NUM> may be a region formed by the middle of line (MOL) or back end of line (BEOL) processing of an IC chip. The dielectric regions <NUM>, <NUM>, <NUM> may include a metallization level. The first interconnect structure <NUM> may be in the first dielectric region <NUM>. The source electrode <NUM>, the drain electrode <NUM>, the control electrode <NUM>, the hole generating layer <NUM>, the dielectric channel layer <NUM>, the first spacer layer <NUM>, and the second spacer layer <NUM> may be in the second dielectric region <NUM>. The second interconnect structure <NUM>, the third interconnect structure <NUM>, and the conductive lines <NUM>, <NUM> may be in the third dielectric region <NUM>.

The source electrode <NUM>, the drain electrode <NUM>, and the control electrode <NUM> may include a metal. Examples of the metal for the source electrode <NUM>, the drain electrode <NUM>, and the control electrode <NUM> may include, but are not limited to, tungsten, molybdenum, vanadium, strontium, cobalt, tantalum, titanium, hafnium, copper, aluminum, or an alloy thereof. In an embodiment, the electrodes <NUM>, <NUM>, <NUM> may have the same material. In another embodiment, the source electrode <NUM>, the drain electrode <NUM>, and the control electrodes <NUM> have different materials from each other. In yet another embodiment, the source electrode <NUM> and the drain electrode <NUM> may have the same material while the control electrode <NUM> may have a different material from the source electrode <NUM> and the drain electrode <NUM>.

The dielectric channel layer <NUM> may include an oxide. In some embodiments, the dielectric channel layer <NUM> may include an oxide of the metal in the source electrode <NUM> and the drain electrode <NUM>. In other embodiments, the dielectric channel layer <NUM> may include an oxide of tungsten, molybdenum, vanadium, or strontium cobalt alloy. The hole generating layer <NUM> may include a material saturated with hydrogen. For example, the material may have a crystalline structure and have hydrogen gas intercalated at the interstitial defect sites in the material. The hole generating layer <NUM> may include a hydrogen doped dielectric material or a hydrogen doped metal. For example, the hole generating layer <NUM> may include hydrogen doped silicon dioxide (SiO<NUM>-H), platinum hydride (Pt-H), or palladium hydride (Pd-H). The hole generating layer <NUM> may be capable of providing holes (i.e., positive charge carriers or protons) that migrate from the hole generating layer <NUM> towards the dielectric channel layer <NUM> under the influence of an electric field.

As an illustrative example, during the operation of the memory structures <NUM> shown in <FIG> and <FIG>, a bias voltage may be applied to the control electrode <NUM> through the first interconnect structure <NUM>. The number of holes migrated towards the dielectric channel layer <NUM> may be dependent on the magnitude and direction of the bias voltage. A current may be allowed to flow through the dielectric channel layer <NUM> and between the source electrode <NUM> and the drain electrode <NUM>. The migration of holes in and out of the dielectric channel layer <NUM> may increase or decrease the conductance of the dielectric channel layer <NUM>, thereby increasing or decreasing the current flow between the source electrode <NUM> and the drain electrode <NUM>. Thus, the control of the bias voltage applied to the control electrode <NUM> may modulate the conductance of the dielectric channel layer <NUM>.

The dielectric regions <NUM>, <NUM>, <NUM> may include dielectric materials <NUM>, <NUM>, <NUM>, respectively. Examples of the dielectric materials <NUM>, <NUM>, <NUM> may include, but are not limited to, silicon dioxide (SiO<NUM>), silicon oxynitride (SiON), silicon nitride (Si<NUM>N<NUM>), Nitrogen doped silicon carbide (SiCN), SiCxHz (i.e., BLoK™), or SiNwCxHz (i.e., NBLoK™), wherein each of w, x, y, and z independently has a value greater than <NUM> and less than <NUM>, tetraethyl orthosilicate (TEOS), or a material having a chemical composition of SiCxOyHz, wherein x, y, and z are in stoichiometric ratio.

The spacer layers <NUM>, <NUM> may include, but are not limited to, silicon dioxide (SiO<NUM>), silicon oxynitride (SiON), silicon nitride (Si<NUM>N<NUM>), Nitrogen doped silicon carbide (SiCN), SiCxHz (i.e., BLoK™), or SiNwCxHz (i.e., NBLoK™), wherein each of w, x, y, and z independently has a value greater than <NUM> and less than <NUM>, tetraethyl orthosilicate (TEOS), or a material having a chemical composition of SiCxOyHz, wherein x, y, and z are in stoichiometric ratio. The spacer layers <NUM>, <NUM> may serve to prevent electrical shorts or migration of holes between the source and drain electrodes <NUM>, <NUM> and the sides 116a, 116b of the hole generating layer <NUM> and the sides 118a, 118b of the control electrode <NUM>, and thereby ensuring that the migration of holes occurs only between the horizontal segment 116c of the hole generating layer <NUM> and the horizontal segment 114c of the dielectric channel layer <NUM>.

<FIG> show structures at successive fabrication stages of a processing method for fabricating an exemplary memory structure shown in <FIG>.

As used herein, "deposition techniques" refer to the process of applying a material over another material (or the substrate). Exemplary techniques for deposition include, but are not limited to, spin-on coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD).

Additionally, "patterning techniques" include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described pattern, structure, or opening. Examples of techniques for patterning include, but are not limited to, wet etch lithographic processes, dry etch lithographic processes, or direct patterning processes. Such techniques may use mask sets and mask layers.

Referring to <FIG>, a first dielectric region <NUM> may be formed over a substrate (not shown). The first dielectric region <NUM> may include a first interconnect structure <NUM> formed in a dielectric material <NUM>. A control electrode <NUM> may be formed on the dielectric material <NUM> and the first interconnect structure <NUM>, for example, using deposition techniques. A hole generating layer <NUM> may be formed on the control electrode <NUM>, for example, using deposition techniques. In an example, the hole generating layer <NUM> may be formed by depositing a silicon dioxide layer. The silicon dioxide layer may be injected, doped, or sputtered by a forming gas <NUM>, such as hydrogen gas. In another example, the hole generating layer <NUM> may be formed by depositing platinum or palladium. The deposited platinum or palladium may be injected, doped, or sputtered by the forming gas <NUM> such that the platinum or palladium is saturated with the forming gas.

Referring to <FIG>, a dielectric channel layer <NUM> may be formed on the hole generating layer <NUM> using deposition techniques. A mask layer <NUM> may be formed on the dielectric channel layer <NUM> and then patterned using patterning techniques. The mask layer <NUM> may be used for the subsequent patterning of the control electrode <NUM>, the hole generating layer <NUM>, and the dielectric channel layer <NUM>. Referring to <FIG>, the control electrode <NUM>, the hole generating layer <NUM>, and the dielectric channel layer <NUM> may be patterned using patterning techniques so that the patterned control electrode <NUM>, hole generating layer <NUM>, and dielectric channel layer <NUM> are aligned vertically over the first interconnect structure <NUM>. The control electrode <NUM> may be patterned to form sides 118a, 118b, the hole generating layer <NUM> may be patterned to form sides 116a, 116b, and the dielectric channel layer <NUM> may be patterned to form sides 114a, 114b. The dielectric channel layer <NUM> may also have an upper surface 114t. The control electrode <NUM> may be patterned such that it has a lower surface 118c that contacts or directly contacts the first interconnect structure <NUM>.

Referring to <FIG>, a spacer material layer <NUM> may be formed using a deposition technique, and preferably, using conformal deposition (e.g., ALD) such that the spacer material layer <NUM> covers the sides 118a, 118b of the control electrode, the sides 116a, 116b of the hole generating layer <NUM>, and the sides 114a, 114b and the upper surface 114t of the dielectric channel layer <NUM>. The spacer material layer <NUM> may also cover the dielectric material <NUM> in the first dielectric region <NUM>.

Referring to <FIG>, the spacer material layer <NUM> may be etched using a directional etching, such as anisotropic etching, to form a first spacer layer <NUM> and a second spacer layer <NUM>. The etching of the spacer material layer <NUM> may be controlled such that the first spacer layer <NUM> and the second spacer layer <NUM> cover the sides 118a, 118b of the control electrode and the sides 116a, 116b of the hole generating layer <NUM>. Additionally, a lower portion <NUM> of side 114a and a lower portion <NUM> of side 114b may be covered by the first spacer layer <NUM> and the second spacer layer <NUM>, respectively, while an upper portion <NUM> of side 114a and an upper portion <NUM> of side 114b may be exposed and uncovered by the first spacer layer <NUM> and the second spacer layer <NUM>, respectively. The etching of the spacer material layer <NUM> may also expose the upper surface 114t of the dielectric channel layer <NUM> and portions of the dielectric material <NUM> in the first dielectric region <NUM>.

Referring to <FIG>, a second dielectric region <NUM> may be formed on the first dielectric region <NUM>. The second dielectric region <NUM> may include a dielectric material <NUM> formed on the dielectric material <NUM> using deposition techniques. The dielectric material <NUM> may have an upper surface 128t. The dielectric material <NUM> may be patterned using patterning techniques to form source/drain openings <NUM> in the second dielectric region <NUM>. The source/drain openings <NUM> may be defined in the dielectric material <NUM>.

Referring to <FIG>, a metal layer <NUM> may be formed in the source/drain openings <NUM>. The metal layer <NUM> may also be formed over the dielectric material <NUM>, the spacer layers <NUM>, <NUM>, the dielectric material <NUM>, and the dielectric channel layer <NUM> using deposition techniques. The metal layer <NUM> may be deposited in the source/drain openings <NUM> such that the metal layer <NUM> is on the upper portion <NUM> of the side 114a of the dielectric channel layer <NUM>, the upper portion <NUM> of the side 114b of the dielectric channel layer <NUM>. The metal layer <NUM> may also extend outside of the source/drain openings <NUM> and overlie the upper surface 128t of the dielectric material <NUM> and the upper surface 114t of the dielectric channel layer <NUM>.

Referring to <FIG>, a chemical mechanical planarization (CMP) process may be performed on the structure shown in <FIG> to remove portions of the metal layer <NUM> and expose the upper surface 114t of the dielectric channel layer <NUM> and the upper surface 128t of the dielectric material <NUM>. A source electrode <NUM> and a drain electrode <NUM> may be formed after the CMP process. The source electrode <NUM> may have an upper surface 110t and the drain electrode <NUM> may have an upper surface 112t. The CMP process may ensure that the upper surface 110t of the source electrode <NUM>, and the upper surface 112t of the drain electrode <NUM> are substantially coplanar with the upper surface 114t of the dielectric channel layer <NUM> and the upper surface 128t of the dielectric material <NUM>. In an implementation, the source electrode <NUM> and the drain electrode <NUM> may include the same metal. The second dielectric region <NUM> may include the source electrode <NUM>, the drain electrode <NUM>, the spacer layers <NUM>, <NUM>, the control electrode <NUM>, the hole generating layer <NUM>, and the dielectric channel layer <NUM>, in addition to the dielectric material <NUM>.

Referring to <FIG>, a third dielectric region <NUM> may be formed on the second dielectric region <NUM>. The third dielectric region <NUM> may include a dielectric material <NUM> formed on the upper surface 110t of the source electrode <NUM>, the upper surface 112t of the drain electrode, the upper surface 114t of the dielectric channel layer <NUM>, and the dielectric material <NUM> using the deposition techniques described herein. Interconnect openings <NUM> may be formed in the dielectric material <NUM> using patterning techniques. Interconnect structures, as described in <FIG>, may be formed in the interconnect openings <NUM>, for example, by forming a metal, such as cobalt (Co), copper (Cu), aluminum (Al), or an alloy thereof, in the interconnect openings <NUM>. Other suitable types of metals or alloys may also be useful. The interconnect openings <NUM> may be formed such that they are aligned vertically above the upper surface 110t of the source electrode <NUM> and the upper surface 112t of the drain electrode <NUM>.

<FIG> and <FIG> show structures at successive fabrication stages of a processing method for fabricating an exemplary memory structure shown in <FIG>.

Referring to <FIG> continues from the structure shown in <FIG>), a metal layer <NUM> may be formed over the dielectric material <NUM>, the spacer layers <NUM>, <NUM>, and the dielectric channel layer <NUM> using deposition techniques. The metal layer <NUM> may be deposited on the upper portion <NUM> of the side 114a of the dielectric channel layer <NUM>, the upper portion <NUM> of the side 114b of the dielectric channel layer <NUM>, and the upper surface 114t of the dielectric channel layer <NUM>. The deposition of the metal layer <NUM> in <FIG> may deposit lesser material as compared to the deposition of the metal layer <NUM> in <FIG>.

Referring to <FIG>, the metal layer <NUM> may be etched using a directional etching such as anisotropic etching. For example, horizontal segments of the metal layer <NUM> covering the dielectric material <NUM> and the upper surface 114t of the dielectric channel layer <NUM> may be removed while vertical segments of the metal layer <NUM> covering the spacer layers <NUM>, <NUM> and the upper portions <NUM>, <NUM> of the sides 114a, 114b of the dielectric channel layer <NUM> are retained. A source electrode <NUM> and a drain electrode <NUM> may be formed after the etching of the metal layer <NUM>. The source electrode <NUM> may have an upper surface 110t and the drain electrode <NUM> may have an upper surface 112t. In an implementation, the source electrode <NUM> and the drain electrode <NUM> may include the same metal.

Referring to <FIG>, a second dielectric region <NUM> may be formed on the first dielectric region <NUM>. The second dielectric region <NUM> may include a dielectric material <NUM> formed laterally adjacent to the source electrode <NUM> and the drain electrode <NUM> and on the dielectric material <NUM> using deposition techniques. Although not shown, the dielectric material <NUM> may be deposited over the upper surface 114t of the dielectric channel layer <NUM>, the upper surface 110t of the source electrode <NUM>, and the upper surface 112t of the drain electrode <NUM>. A CMP process may be performed on the deposited dielectric material <NUM> to expose the upper surface 114t of the dielectric channel layer <NUM>, the upper surface 110t of the source electrode <NUM>, and the upper surface 112t of the drain electrode <NUM>. The CMP process may also ensure that the upper surface 110t of the source electrode <NUM>, the upper surface 112t of the drain electrode <NUM> are substantially coplanar with the upper surface 114t of the dielectric channel layer <NUM>. The second dielectric region <NUM> may include the source electrode <NUM>, the drain electrode <NUM>, the spacer layers <NUM>, <NUM>, the control electrode <NUM>, the hole generating layer <NUM>, and the dielectric channel layer <NUM>.

A third dielectric region <NUM> may be formed on the second dielectric region <NUM>. The third dielectric region <NUM> may include a dielectric material <NUM> formed on the upper surface 110t of the source electrode <NUM>, the upper surface 112t of the drain electrode, the upper surface 114t of the dielectric channel layer <NUM>, and the dielectric material <NUM> using the deposition techniques described herein. Interconnect openings <NUM> may be formed in the dielectric material <NUM> using patterning techniques. Interconnect structures, as described in <FIG>, may be formed in the interconnect openings <NUM>, for example, by forming a metal, such as cobalt (Co), copper (Cu), aluminum (Al), or an alloy thereof, in the interconnect openings <NUM>. Other suitable types of metals or alloys may also be useful. The interconnect openings <NUM> may be formed such that they are aligned vertically above the upper surface 110t of the source electrode <NUM> and the upper surface 112t of the drain electrode <NUM>. The vertical alignment of the interconnect openings <NUM> may also overlap with the source electrode <NUM> and the dielectric channel layer <NUM> and the drain electrode <NUM> and the dielectric channel layer <NUM>.

Throughout this disclosure, it is to be understood that if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms "comprise", "include", "have", and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase "in an embodiment" herein do not necessarily all refer to the same embodiment.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. Additionally, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/- <NUM>% of the stated value(s).

As will be readily apparent to those skilled in the art upon a complete reading of the present application, the disclosed semiconductor devices and methods of forming the same may be employed in manufacturing a variety of different integrated circuit products, including, but not limited to, memory cells, NV memory devices, FinFET transistor devices, CMOS devices, etc..

In summary, the following embodiments are explicitly disclosed.

A memory structure comprising: a source electrode; a drain electrode; a control electrode laterally between the source electrode and the drain electrode, the control electrode having a first side and a second side; a hole generating layer above the control electrode; a dielectric channel layer above the hole generating layer, the dielectric channel layer contacts the source electrode and the drain electrode; a first spacer layer on the first side of the control electrode; and a second spacer layer on the second side of the control electrode, wherein the first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer.

The memory structure of embodiment <NUM>, wherein the dielectric channel layer has a first side and a second side, the first side contacts the source electrode, and the second side contacts the drain electrode.

The memory structure of embodiment <NUM>, further comprising: a first interconnect structure below the control electrode; a second interconnect structure above the source electrode; and a third interconnect structure above the drain electrode.

The memory structure of embodiment <NUM>, wherein the second interconnect structure overlaps with the source electrode and the dielectric channel layer, and the third interconnect structure overlaps with the drain electrode and the dielectric channel layer.

The memory structure of embodiment <NUM>, further comprising: a first dielectric region, wherein the first interconnect structure is in the first dielectric region; and a second dielectric region on the first dielectric region, wherein the source electrode, the drain electrode, the control electrode, the dielectric channel layer, the hole generating layer, the first spacer layer, and the second spacer layer are in the second dielectric region.

The memory structure of embodiment <NUM>, further comprising a third dielectric region on the second dielectric region, wherein the second interconnect structure and the third interconnect structure are in the third dielectric region.

The memory structure of one of embodiments <NUM> to <NUM>, wherein the source electrode has an upper surface, the drain electrode has an upper surface, and the dielectric channel layer has an upper surface, and wherein the upper surface of the source electrode and the upper surface of the drain electrode are preferably coplanar with the upper surface of the dielectric channel layer.

The memory structure of one of embodiments <NUM> to <NUM>, wherein the first spacer layer overlaps with a lower portion of the first side of the dielectric channel layer, and the second spacer layer overlaps with a lower portion of the second side of the dielectric channel layer.

The memory structure of embodiment <NUM>, wherein the source electrode contacts an upper portion of the first side of the dielectric channel layer and the drain electrode contacts an upper portion of the second side of the dielectric channel layer.

The memory structure of one of embodiments <NUM> to <NUM>, wherein the hole generating layer includes a hydrogen doped dielectric material or a hydrogen doped metal.

The memory structure of embodiment <NUM>, wherein the hole generating layer includes hydrogen doped silicon dioxide, platinum hydride, or palladium hydride.

The memory structure of one of embodiments <NUM> to <NUM>, wherein the dielectric channel layer includes an oxide of tungsten, molybdenum, vanadium, or strontium cobalt alloy.

Claim 1:
A memory structure (<NUM>) comprising:
a source electrode (<NUM>);
a drain electrode (<NUM>);
a control electrode (<NUM>) laterally between the source electrode (<NUM>) and the drain electrode (<NUM>), the control electrode (<NUM>) having a first side (118a) and a second side (118b);
a hole generating layer (<NUM>) above the control electrode (<NUM>);
a dielectric channel layer (<NUM>) above the hole generating layer (<NUM>), the dielectric channel layer (<NUM>) contacts the source electrode (<NUM>) and the drain electrode (<NUM>);
a first spacer layer (<NUM>) on the first side (118a) of the control electrode (<NUM>); and
a second spacer layer (<NUM>) on the second side (118b) of the control electrode (<NUM>), wherein the first spacer layer (<NUM>) and the second spacer layer (<NUM>) isolate the source electrode (<NUM>) and the drain electrode (<NUM>) from the control electrode (<NUM>) and the hole generating layer (<NUM>).