Patent Description:
As known, semiconductor materials having a wide bandgap, for example higher than <NUM> eV, low on- resistance, high thermal conductivity, high operating frequency and high saturation velocity of the charge carriers allow to obtain electronic devices, for example diodes and transistors, having better performance than electronic devices formed in a silicon substrate. This applies specifically to power applications, for example in devices operating at voltages comprised between <NUM> V and <NUM> V or in specific operating conditions, such as high temperature.

In particular, MOSFET electronic devices are formed starting from a wafer of silicon carbide in one of its polytypes, for example 3C-SiC, <NUM>-SiC and <NUM>-SiC, which provide the above listed advantages. In particular, in the following description, reference will be made to the <NUM>-SiC polytype, but what will be said also applies to the other polytypes, without limiting the scope.

For instance, <FIG> is a cross-section through a known vertical-conduction MOSFET device <NUM>, in a Cartesian reference system XYZ comprising a first axis X, a second axis Y, and a third axis Z.

The MOSFET device <NUM> is formed by a plurality of elementary cells, only two of which are shown here, which have equal structure, are arranged adjacent in a same die <NUM> and are connected together in parallel. They consequently share a source terminal S, a drain terminal D, and a gate terminal G.

The die <NUM> comprises a substrate <NUM> of silicon carbide, having a first surface 5A and a second surface 5B. The substrate <NUM> accommodates a drain region <NUM>, a plurality of body regions <NUM>, and a plurality of source regions <NUM>.

The drain region <NUM>, here of an N type, extends between the first and the second surface 5A, 5B of the substrate <NUM>. A drain contact region <NUM>, of conductive material such as metal or silicide, extends on the second surface 5B of the substrate <NUM>, in direct electrical contact with the drain region <NUM>, and forms the drain terminal D of the MOSFET device <NUM>.

The body regions <NUM> are of P type and extend in the substrate <NUM>, at a distance from each other, from the first surface 5A.

A superficial portion <NUM> of the drain region <NUM> is comprised between two adjacent body regions <NUM>.

The body regions <NUM> further extend along the second axis Y and have here, in top view, the shape of strips.

The source regions <NUM> extend each, from the first surface 5A of the substrate <NUM>, within a respective body region <NUM> and are of N type. Each source region <NUM> has a width, along the first axis X, smaller than the width of the respective body region <NUM> and a depth, along the third axis Z, smaller than the depth of the respective body region <NUM>.

Each source region <NUM> laterally delimits, together with the adjacent superficial portion <NUM>, a channel portion <NUM> of a respective body region <NUM>.

The MOSFET device <NUM> further comprises a plurality of insulated gate regions <NUM>. The insulated gate regions <NUM> are formed each by a gate insulating layer <NUM>, in contact with the first surface 5A of the substrate <NUM>; a gate conductive region <NUM>, typically of polycrystalline silicon, directly overlying the gate insulating layer <NUM>; and an insulation layer <NUM>, surrounding and sealing the gate conductive region <NUM>, together with the gate insulating layer <NUM>.

The gate insulating layer <NUM> of each insulated gate region <NUM> extends on a respective superficial portion <NUM> of the drain region <NUM>, on two channel regions <NUM> adjacent to the respective superficial portion <NUM>, and partially on two source regions <NUM> adjacent to the respective channel regions <NUM>.

The gate conductive regions <NUM> have here the shape of strips extending parallel to the second axis Y (see also <FIG>) and are electrically connected in parallel to each other and to the gate terminal G of the MOSFET device <NUM>, as explained below.

The MOSFET device <NUM> further comprises a plurality of body contact regions <NUM>.

The body contact regions <NUM> are of P+ type and extend each from the first surface 5A of the substrate <NUM> into a respective source region <NUM>, in contact with a respective body region <NUM>. In the shown embodiment, not being part of the present invention, each source region <NUM> accommodates more than one body contact region <NUM>.

The body contact regions <NUM> are arranged at a distance to each other along the second axis Y, offset to each other along the first axis X, so that, in the cross-section of <FIG>, they are visible only in the two source regions <NUM> on the right and on the left, but not in the central source region <NUM>.

The body contact regions <NUM> and the source regions <NUM> are in direct electrical contact with a source metallization region <NUM>, which is, for example, of metal.

As may be noted in particular from <FIG>, the source metallization region <NUM> is generally divided into two portions (designated by 33A and 33B in <FIG>) arranged adjacent and at a distance to each other, which cover the majority of the first surface 5A of the substrate <NUM>. The two portions 33A and 33B of the source metallization region <NUM> also form pads for external connection of the MOSFET device <NUM> and form the source terminal S of the MOSFET device <NUM>.

In addition, <FIG>, two auxiliary source pads <NUM> and a gate pad <NUM> also extend on the first surface 5A of the substrate <NUM>. The auxiliary source pads <NUM>, the gate pad <NUM>, and the source metallization region <NUM> are formed in a same layer and therefore have the same, high thickness so as to provide the desired current capability for the source terminal S.

The gate pad <NUM> is connected to the gate conductive regions <NUM> (represented dashed in <FIG>) through metal connection portions and a resistive network.

In detail, the metal connection portions are formed in the same metal layer as the pads <NUM>, <NUM> and <NUM> and comprise a gate metal ring 38A and a gate metal strip or "finger" 38B.

In the embodiment, not being part of the present invention, shown in <FIG>, the gate pad <NUM> is arranged in proximity of a side of the die <NUM>, in a median position thereof; the gate metal finger 38B extends from the gate pad <NUM> towards the opposite side of the die <NUM>; and the gate metal ring 38A extends peripherally to the die <NUM>, in electrical contact with, and as an extension of, the gate pad <NUM>.

In particular, in the top view of <FIG>, the die <NUM> has a rectangular shape having a first side 2A; a second side 2B, opposite the first side 2A; a third side 2C; and a fourth side 2D, opposite the third side 2C, wherein the third and fourth sides 2C, 2D extend parallel to the first axis X, and the first and second sides 2A, 2B extend parallel to the second axis Y.

In this geometry, the gate pad <NUM> is arranged in proximity of the first side 2A, the gate metal finger 38B extends parallel to the first axis X from the gate pad <NUM> to the portion of the gate metal ring 38A adjacent the second side 2B, and the gate conductive regions <NUM> extend parallel to the second axis Y.

The resistive network comprises a first and a second connection portion 36A, 38B connected to the gate conductive regions <NUM> and to the metal connection portions 38B, 38A, as described hereinafter and shown in <FIG>, where, for simplicity, the gate insulating layer <NUM> is not represented.

In particular, <FIG> shows a peripheral edge portion (designated by <NUM>) of the die <NUM>, for example adjacent to the fourth side 2D.

An insulation oxide annular portion 40A, for example of silicon oxide, extends over the first surface 5A of the substrate <NUM> and is covered by a passivation layer <NUM>, connected to the insulation layer <NUM>.

A delimitation region <NUM>, having an opposite conductivity with respect to the substrate <NUM>, here of P type, and having an annular shape, extends within the substrate <NUM>, approximately underneath the inner edge of the insulation oxide annular portion 40A. The delimitation region <NUM> surrounds, in the substrate <NUM>, an active area <NUM> (the limit whereof is represented schematically by a dashed line A); accommodating the conduction regions of the MOSFET device <NUM>, including the source regions <NUM> and the body regions <NUM> (not visible in <FIG>). An implanted region <NUM>, here of N+ type and ring-shaped, forming a channel stopper, extends underneath the insulation oxide annular portion 40A, in proximity of the outer edge thereof and of the sides 5A-5D of the die <NUM>, at a distance D from the delimitation region <NUM>.

The first connection portion 36A, of polycrystalline silicon, extends as a ring over and along the inner edge of the insulation oxide annular portion 40A. The first connection portion 36A is here in direct electrical contact with a gate conductive region <NUM>, without interruption, being obtained in the same layer.

<FIG> moreover shows the gate metal ring 38A, which extends above the insulation oxide annular portion 40A; the gate metal ring 38A crosses the passivation layer <NUM> and is here in direct electrical contact with the first connection portion 36A.

<FIG> shows the connection between the gate metal finger 38B and the gate conductive regions <NUM>.

In detail, an insulation oxide finger portion 40B, formed by the same layer as the insulation oxide annular portion 40A, extends over the body <NUM>, parallel to the first direction X, as far as and in contact with the sides of the insulation oxide annular portion 40A adjacent to the first and second sides 2A, 2B of the die <NUM>. The insulation oxide finger portion 40B and the insulation oxide annular portion 40A form an edge insulation region <NUM>.

The second connection portion 36B extends over the insulation oxide finger portion 40B and also has an elongated shape in the first direction X. However, the second connection portion 36B has a width (in a direction parallel to the second direction Y) greater than the width (in the same direction) of the insulation oxide finger portion 40B and therefore extends also on the side of the insulation oxide finger portion 40B, where it is directly connected to the gate conductive regions <NUM>. Moreover, it is directly connected, at its longitudinal ends, to the insulation oxide annular portion 40A.

The insulation layer <NUM> covers the second connection portion 36B and has an opening <NUM> extending parallel to the first direction X, approximately throughout the length of the second connection portion 36B. The gate metal finger 38B extends through the opening <NUM> and is here in direct electrical contact with the second connection portion 36B.

The insulation oxide finger portion 40B extends on a insulation finger region <NUM>, of P type, formed in the body <NUM> and extending parallel to the first direction X, between two opposite sides of the delimitation region <NUM>, with which it is in direct contact.

The insulation oxide finger portion 40B overlies an inactive area <NUM> (also referred to as central edge area) that separates two active areas <NUM>.

In the known device <NUM>, the gate metal finger 38B and the gate metal ring 38A have the aim of reducing the voltage drop between the gate pad <NUM> and the gate conductive regions <NUM> due to the resistivity of the resistive network formed by the connection portions 36A, 36B.

The presence of the metal connection portions 38A, 38B is, however, disadvantageous in certain applications.

In fact, the gate metal finger 38B causes the source metallization to be divided into at least the two portions 33A, 33B (or even more, in devices that, due to their dimensions, have several gate metal fingers 38B). This limits the use of the MOSFET device <NUM> in power modules that have clips sintered or soldered on the die <NUM> or need particular, costly and/or cumbersome solutions for contacting the source metallization region <NUM>.

The presence of the gate metal ring 38A in the peripheral edge portion <NUM> of the die <NUM> moreover is critical during the reliability assessment of the MOSFET device <NUM>. In particular, innovative reliability tests that verify the switching behaviour in high-humidity environments show that the gate metal ring 38A is a weak point of the device.

The metal connection portions 38A, 38B cause a non-negligible encumbrance, both because of their dimensions and due to the minimum safety space to be provided between the portions 33A, 33B of the source metallization region <NUM> and the gate pad <NUM>.

For instance, with the shown configuration, the gate metal ring 38A is designed to maintain the distance D in <FIG> between the channel-stopper region <NUM> and the delimitation region <NUM>. Furthermore, as shown in <FIG>, the distance D' between the active areas <NUM> (areas where the central edge area <NUM> and the gate metal finger 38B extend) cannot be used for the conduction of the MOSFET device <NUM> and represents a waste of area.

<CIT> discloses a power conversion device including a substrate of silicon carbide and having a gate conductive region and a gate connection region formed by a silicon layer and by a metal layer overlying the silicon layer.

<CIT> discloses a power semiconductor device having an annular connection region.

<CIT>, <CIT> and <CIT> disclose other silicon carbide MOSFET transistors.

The aim of the present invention is to overcome the drawbacks of the prior art.

According to the present invention a vertical-conduction MOSFET device and the manufacturing process thereof are provided, as defined in the attached claims.

For a better understanding of the present invention some embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

<FIG> show a MOSFET device <NUM>, with vertical conduction, of silicon carbide.

The MOSFET device <NUM> is formed in a die <NUM> having a generally parallelepipedal shape, with four lateral surfaces or sides 52A-52D and a top surface 52E. In particular, in the top view of <FIG>, the die <NUM> has a first side 52A; a second side 52B, opposite the first side 52A; a third side 52C; and a fourth side 52D, opposite the third side 2C, wherein the third and fourth sides 52C, 52D are parallel to a first axis X of a Cartesian reference system XYZ, and the first and second sides 52A, 52B are parallel to a second axis Y of the Cartesian reference system XYZ.

The MOSFET device <NUM> comprises a plurality of elementary cells (two shown in <FIG>) adjacent to each other and connected together in parallel. They thus share a source terminal S, a drain terminal D, and a gate terminal G.

As may be seen in the cross-sections of <FIG>, the die <NUM> comprises a substrate <NUM> of silicon carbide having a first surface 55A and a second surface 55B. The substrate <NUM> accommodates a drain region <NUM>, a plurality of body regions <NUM>, and a plurality of source regions <NUM>, analogous to the respective same-name regions <NUM>, <NUM> and <NUM> of <FIG> and not described any further herein.

A gate contact region <NUM>, of conductive material such as a metal and/or a silicide, extends on the second surface 55B of the substrate <NUM>, in direct electrical contact with the drain region <NUM>, and forms the drain terminal D of the MOSFET device <NUM>.

Each source region <NUM> laterally delimits, together with an adjacent superficial portion <NUM>, a channel portion <NUM> of a respective body region <NUM>.

The MOSFET device <NUM> further comprises a plurality of insulated gate regions <NUM>. The insulated gate regions <NUM> are each formed by a gate insulating region <NUM>, in contact with the first surface 55A of substrate <NUM>; a gate conductive region <NUM>, directly overlying the gate insulating region <NUM>; and a top insulation layer <NUM>, surrounding and sealing, together with the gate insulating region <NUM>, the gate conductive region <NUM>.

Each gate conductive region <NUM> is here formed by a gate semiconductor portion <NUM>, typically of polycrystalline silicon, and a gate metal portion <NUM>, directly overlying and in direct electrical contact with the gate semiconductor portion <NUM>. The gate metal portion <NUM> is typically a metal silicide, for example tungsten, titanium, nickel, cobalt, or platinum silicide.

In the embodiment of <FIG>, the gate metal portion <NUM> has the same width (in the direction of the first axis X) as the gate semiconductor portion <NUM>; in the embodiment of <FIG>, the gate-metal region (designated by <NUM>') has a smaller width than the gate semiconductor portion <NUM>.

The gate insulating region <NUM> of each insulated gate region <NUM> extends on a respective superficial portion <NUM> of the drain region <NUM>, on two channel regions <NUM> adjacent to the respective superficial portion <NUM>, and partially on two source regions <NUM> adjacent to the respective channel regions <NUM>.

The gate conductive regions <NUM> are electrically connected in parallel to each other and to the gate terminal G of the MOSFET device <NUM>, as explained below.

The MOSFET device <NUM> further comprises a plurality of body contact regions <NUM> (hereinafter also referred to as P-well regions <NUM>), analogous to the body contact regions <NUM> of <FIG>.

The P-well regions <NUM> and the source regions <NUM> are in direct electrical contact with a source metallization region <NUM>, for example of metal and/or metal silicide.

As may be noted from <FIG>, the source metallization region <NUM> is here formed by a single portion occupying most of the top surface 52E of the die <NUM> and forms also a pad for external connection of the MOSFET device <NUM>.

In addition, two auxiliary source pads <NUM> and a gate pad <NUM> extend on the first surface 55A of the substrate <NUM>. The auxiliary source pads <NUM>, the gate pad <NUM>, and the single source metallization region <NUM> are formed in a same layer and therefore have the same high thickness, for example comprised between <NUM> and <NUM>, so as to provide the desired current capability of the source terminal S.

It is highlighted that, if so desired, the source metallization region <NUM> may be formed by several separate portions, instead of a single portion. In any case, in the MOSFET device <NUM>, the distance between them is not critical, and no gate metal finger (38B in <FIG>) is present, nor is a gate metal ring (38A in <FIG>).

The gate pad <NUM> (here arranged in proximity of the first side 52A of the die <NUM>, in a middle position) is connected to the gate conductive regions <NUM> (represented dashed in <FIG>) through an annular connection region <NUM>, which extends in proximity of the periphery of the die <NUM> and has a widened portion forming a contact area 86A arranged underneath the gate pad <NUM>. The annular connection region <NUM> is monolithic with the gate conductive regions <NUM>, is formed by the same layers, and is obtained by the same process steps for forming the gate conductive regions <NUM>, as described in detail hereinafter.

The annular connection region <NUM> is visible also in the cross-sections of <FIG>, wherein, for simplicity, the gate insulating region <NUM> is not represented.

In particular, <FIG> shows a peripheral edge portion (designated by <NUM>), of the die <NUM>, for example adjacent to the second side 52B.

An edge insulation region <NUM>, here of oxide, extends on the first surface 55A of the substrate <NUM>.

The edge insulation region <NUM> here comprises an oxide layer <NUM> and a passivation layer <NUM> overlying the latter. The passivation layer <NUM>, in proximity of the third and the fourth sides 52C, 52D of the die <NUM>, prosecutes with the top insulation layer <NUM> of the insulated gate regions <NUM>, which, in the cross-section of <FIG>, is interrupted by the openings, where the source metallization <NUM> extends.

A delimitation region <NUM>, having a conductivity opposite that of the substrate <NUM>, here of P type and annular shape, extends in the substrate <NUM> underneath the edge insulation region <NUM>, in proximity of, but at a distance from, the inner edge of the latter. The delimitation region <NUM> surrounds, in the substrate <NUM>, an active area <NUM> (whose limit is represented schematically by a dashed line B), accommodating the conduction regions of the MOSFET device <NUM>, including the body regions <NUM> and the source regions <NUM>. A channel-stopper region <NUM>, here of N+ type and annular shape, extends underneath the edge insulation region <NUM>, in proximity of the sides 52A-52D of the die <NUM>, at a distance D1 from the delimitation region <NUM>, to balance the potential in the edge area.

The annular connection region <NUM> extends in an annular way only along the inner edge of the edge insulation region <NUM> and does not have portions extending between active areas.

As mentioned above, the annular connection region <NUM> is formed monolithically with the gate conductive regions <NUM> as a stack of two layers.

In particular, the annular connection region <NUM> comprises a semiconductor connection portion <NUM> and a metal connection portion <NUM>, directly overlying and in direct electrical contact with the semiconductor connection portion <NUM>.

Moreover, the material of the semiconductor connection region <NUM> is the same of the gate semiconductor portions <NUM> (typically of polycrystalline silicon), and the material of the metal connection portion <NUM> is the same of the gate metal portions <NUM> (typically a metal silicide, for example tungsten, titanium, nickel, cobalt, or platinum silicide).

The stack of layers forming the gate semiconductor portions <NUM> and the annular connection region <NUM> forms a gate bias layer <NUM>.

As may be noted from <FIG>, the annular connection region <NUM> extends only to a minimal extent on the edge insulation region <NUM> and has a very small width, for example comprised between <NUM> and <NUM>. In addition, the delimitation region <NUM> has also a small width (in the first direction X, in the cross-section of <FIG>), for example comprised between <NUM> and <NUM>. In this way, the width of the peripheral edge portion <NUM> is reduced, and it is also possible to accordingly increase the dimensions of the active area <NUM>, for same dimensions of the dice <NUM>-<NUM>.

Furthermore, as may be seen from <FIG> (analogous to and to be compared with <FIG> representing the known MOSFET device <NUM>), in the central area of the MOSFET device <NUM> no inactive edge area extends, due to the absence of gate metallization portions.

Consequently, in the MOSFET device <NUM>, the passivation layer <NUM>/<NUM> completely covers the metal connection portion <NUM> of the annular connection region <NUM> at the top, and there are no openings or conductive regions through the passivation layer <NUM>/<NUM>, nor are there surface metal portions providing a direct electrical contact between the top surface of the annular connection region <NUM> and the gate metallization <NUM>. Biasing of the annular connection region <NUM> occurs in fact only at its portions contiguous with the contact area 86A.

The MOSFET device <NUM> thus has a wide active area <NUM> and therefore effectively exploits the area of the die <NUM>.

<FIG> show two possible layouts of the gate bias layer <NUM>.

In particular, <FIG> shows the layout of the gate bias layer <NUM> corresponding to what is shown in <FIG>, with the contact area 86A arranged peripherally.

As may be noted, the annular connection region <NUM> has a first and a second branch 86B, 86C, which extend along and in proximity of two opposite sides of the body <NUM> (and precisely, in the embodiment shown in <FIG>, along the third and fourth sides 52C, 52D of the die <NUM>), and the gate conductive regions <NUM> extend continuously between the first and second branches 86B, 86C of the annular connection region <NUM>.

<FIG> shows a different layout of the gate bias layer, here designated by <NUM>'.

Also here, the gate conductive regions <NUM> extend continuously between the first and second branches 86B, 86C of the annular connection region <NUM>. The gate conductive regions <NUM> arranged most centrally have a widened central portion which is common to different gate conductive regions <NUM> and forms a contact area 86A' on which the gate pad <NUM> extends.

In this case, biasing of the annular connection region <NUM> occurs only through the gate conductive regions <NUM> that connect the annular connection region <NUM> to the contact area 86A'.

In general, with the MOSFET device <NUM>, the position of the gate pad <NUM> and therefore of the contact area 86A, 86A' can be chosen with high freedom, according to the applications and possible customer desires.

The MOSFET device <NUM> of <FIG>, <FIG> and <FIG> may be manufactured by depositing/forming a silicide layer before or after defining the gate semiconductor portions <NUM> of the gate conductive regions <NUM>.

For instance, <FIG> shows a wafer <NUM> of silicon carbide (for example of a 3C-SiC, <NUM>-SiC or <NUM>-SiC type) intended to form, after dicing, the die <NUM> of <FIG>. In particular, in <FIG>, the source regions <NUM>, the body regions <NUM>, and the P-well regions <NUM> are already formed within the substrate <NUM>, as likewise the various edge regions (including the delimitation region <NUM> and the channel-stopper region <NUM> of <FIG>), here not visible.

A gate insulating layer <NUM>, a gate conductive layer <NUM>, and a silicide layer <NUM> have already been deposited, in sequence, on the first surface 55A of the substrate <NUM>.

The gate insulating layer <NUM> is, for example, silicon oxide and is intended to form the gate insulating regions <NUM>.

The gate conductive layer <NUM> is typically polycrystalline silicon and is designed to form the gate semiconductor portions <NUM> of the gate conductive regions <NUM> and the semiconductor connection portion <NUM>.

The silicide layer <NUM> is, for example, tungsten silicide (WSi<NUM>) and is intended to form the gate metal portions <NUM> and the metal connection portion <NUM> (<FIG> and <FIG>).

After a stabilization annealing process, for example at a temperature comprised between <NUM> and <NUM>, the silicide layer <NUM>, the gate conductive layer <NUM>, and the gate insulating layer <NUM> are defined in a known way, by a photolithographic process and using the same etching mask (<FIG>).

Thereby, the gate conductive regions <NUM> (<FIG> and <FIG>), the annular connection region <NUM> (<FIG>) and the gate insulating regions <NUM> are formed. Furthermore, the gate metal portions <NUM> and the gate semiconductor portions <NUM> are self-aligned to each other, as likewise the metal connection portion <NUM> and the semiconductor connection portion <NUM>.

Then usual steps for forming the top insulation layer <NUM>, the passivation layer <NUM>, and the metallizations <NUM>-<NUM> follow.

In particular, while forming the passivation layer <NUM>, no openings are made for directly contacting the annular connection region <NUM>.

<FIG> show steps of a different embodiment of a manufacturing process of the MOSFET device <NUM> of <FIG>, <FIG> and <FIG>.

In detail, <FIG> shows a portion of wafer <NUM>. In the step of <FIG>, the source regions <NUM>, the body regions <NUM>, and the P-well regions <NUM>, as well as the various edge regions, have already been formed in the substrate <NUM>.

Moreover, the gate insulating layer <NUM> has already been deposited on the first surface 55A of the substrate <NUM>, and the gate semiconductor portions <NUM> of the gate conductive regions <NUM>, as well as the semiconductor connection portion <NUM>, have already been formed, for example by depositing and photolithographically defining a polycrystalline silicon layer.

A sacrificial layer <NUM>, for example, of silicon oxide, is deposited on the gate semiconductor portions <NUM> and on the gate insulating layer <NUM>, where exposed.

Then (<FIG>), the sacrificial layer <NUM> is etched to form spacers <NUM> (spacer etching). To this end, etching is of a non-masked, dry, directional type (plasma etching). Due to the etch anisotropy, the horizontal portions of the sacrificial layer <NUM> are removed, and the spacers <NUM> are formed on the vertical walls of the gate semiconductor portions <NUM>. In this step, also the portions of the gate insulating layer <NUM> not covered by the gate semiconductor portions <NUM> and by the spacers <NUM>, on the source regions <NUM>, are eliminated, forming the gate insulating regions <NUM>.

Similar spacers (not shown) form on the lateral surfaces of the semiconductor connection portion <NUM> (<FIG>).

Next (<FIG>), a metal layer (for example, titanium or nickel) is deposited by sputtering and reacts with the polycrystalline silicon of the gate semiconductor portions <NUM> and (in a way not shown) of the semiconductor connection portion <NUM> (<FIG>). To this end, a first annealing is carried out at a low temperature, for example comprised <NUM> and <NUM>.

Then, the non-reacted metal material (for example, on the spacers <NUM>) is removed, and a second annealing is carried out at a higher temperature, for example comprised between <NUM> and <NUM>.

The gate metal portions <NUM> of the gate conductive regions <NUM> and the metal connection portion <NUM> of the annular connection region <NUM> (<FIG>) are thus formed.

Consequently, also in this case, then, the gate metal portions <NUM> are self-aligned with the respective gate semiconductor portions <NUM>, and the metal connection portion <NUM> is self-aligned with the semiconductor connection portion <NUM>.

In this step, a thin silicide layer may form on the exposed portions of the substrate <NUM>, in particular on the source regions <NUM> and on the P-well regions <NUM>; these portions may be removed by an appropriate etch or left, according to the specific process.

The process proceeds with the usual steps for forming the top insulation layer <NUM>, the passivation layer <NUM>, and the metallizations <NUM>-<NUM>.

<FIG> show steps of an embodiment of a process for manufacturing the MOSFET device <NUM> of <FIG>, <FIG> and <FIG>.

In particular, <FIG> shows a wafer <NUM>' after performing the manufacturing steps already described for <FIG>.

In particular, in the wafer <NUM>', the source regions <NUM>, the body regions <NUM>, and the P-well regions <NUM>, as well as the various edge regions, have already been formed in the substrate <NUM>.

The gate insulating layer <NUM> has already been deposited on the first surface 55A of the substrate <NUM>.

The gate semiconductor portions <NUM> of the gate conductive regions <NUM>, as well as the semiconductor connection portion <NUM> (not visible in <FIG>) have already been formed, for example by depositing and photolithographically defining a polycrystalline silicon layer.

A sacrificial layer <NUM>, for example, silicon oxide, has been deposited on the gate semiconductor portions <NUM> and on the gate insulating layer <NUM>, where exposed.

Then (<FIG>), a gate contact mask (not shown) is formed on the sacrificial layer <NUM>, and the sacrificial layer <NUM> is selectively removed on the gate semiconductor portions <NUM> and on the semiconductor connection portion <NUM> (not visible in <FIG>). Masking portions <NUM>' covering the sides and the longitudinal edges of the gate semiconductor portions <NUM> and of the semiconductor connection portion <NUM>, as well as the gate insulating layer <NUM>, where exposed, are thus formed.

Then, a metal layer (for example, of titanium, cobalt, or platinum) is deposited by sputtering and caused to react with the polycrystalline silicon of the gate semiconductor portions <NUM> and (in a way not shown) of the semiconductor connection portion <NUM> (<FIG>). To this end, a first annealing at low temperature, for example comprised between <NUM> and <NUM>, is carried out.

Then, the non-reacted metal material (on the masking portions <NUM>') is removed, and a second annealing is carried out at a higher temperature, for example comprised between <NUM> and <NUM>.

The gate metal portions <NUM> of the gate conductive regions <NUM> and the metal connection portion <NUM> of the annular connection region <NUM> are thus formed (<FIG>).

Next, the remaining, non-reacted, portions of the sacrificial layer <NUM> are removed, and the further steps for forming the top insulation layer <NUM>, the passivation layer <NUM>, and the metallizations <NUM>-<NUM> are carried out.

The MOSFET device <NUM> thus formed has many advantages.

In particular, it has a simplified structure, with increase of the active area, thanks to the size reduction of the peripheral edge areas and elimination of the inner edge area.

The MOSFET device <NUM> has an improved gate resistance Rg, since it has no waste of area due to the metal connection portions.

The MOSFET device <NUM> moreover has excellent robustness and may be used also in high-current and/or high-voltage applications. For instance, it is able to work at voltages up to <NUM> kV or currents up to <NUM> A.

The MOSFET device <NUM> has improved reliability because the structure is simplified and the polysilicon of the gate semiconductor portions <NUM> does not require a particular doping. Consequently, there is no precipitation of dopant (typically, phosphorus) from the gate conductive regions <NUM> into the gate insulating region <NUM>. In this way, the latter region, typically of oxide, presents a high reliability.

Since, in MOSFET devices that use silicon carbide substrates, all the junctions, implanted regions, and enriched contact regions are activated before forming the layers and regions on the surface of the substrate <NUM>, the process has a low thermal budget after forming the silicide portions <NUM>, <NUM>; consequently, these portions have excellent thermal stability.

In addition, the external contact structures (clips) that are brought into contact with the source metallization <NUM> during assembly and packaging of the MOSFET device <NUM> may be simplified, reducing costs and improving the current conduction reliability.

Finally, it is clear that modifications and variations may be made to the MOSFET device and to the manufacturing process described and shown herein, without thereby departing from the scope of the present invention, as defined in the attached claims.

Claim 1:
A vertical-conduction MOSFET device (<NUM>) comprising:
a body (<NUM>) of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone (<NUM>), the body accommodating:
a first current conduction region (<NUM>), of a first conductivity type, extending in the body (<NUM>) from the second face (55B) and having a superficial portion (<NUM>) facing the first face (55A);
a body region (<NUM>), of a second conductivity type, extending in the body from the first face (55A); and
a second current conduction region (<NUM>), of the first conductivity type, extending to the inside of the body region (<NUM>) from the first face (55A) of the body, the second current conduction region (<NUM>) delimiting in the body region (<NUM>), together with the superficial portion (<NUM>), a channel portion (<NUM>);
an insulated gate region (<NUM>), extending on the first face (55A) of the body (<NUM>) and overlying the channel portion (<NUM>), the insulated gate region (<NUM>) comprising a gate conductive region (<NUM>); and
a surface edge structure (<NUM>) comprising an edge insulated region (<NUM>), extending on the first face (55A) of the body (<NUM>), in the peripheral zone (<NUM>) of the body,
a connection region (<NUM>), of conductive material, extending in an annular way only along the inner edge of the edge insulation region and not having portions extending between active areas.
wherein:
the gate conductive region (<NUM>) and the annular connection region (<NUM>) are formed by a gate bias layer (<NUM>) including a silicon layer and a metal silicide layer overlying the silicon layer,
the gate conductive region (<NUM>) comprises a gate semiconductor portion (<NUM>) formed by the silicon layer and a gate metal portion (<NUM>) formed by the metal silicide layer,
the annular connection region (<NUM>) comprises a semiconductor connection portion (<NUM>) formed by the silicon layer and a metal connection portion (<NUM>) formed by the metal silicide layer, and
the surface edge structure (<NUM>) comprises a passivation layer (<NUM>) completely covering the metal connection portion (<NUM>) of the annular connection region (<NUM>).