Patent Description:
Pads disposed on a printed circuit board and exposed to the outside of the printed circuit board are surface-treated with an electrolytic plating (or an electrolytic Au plating) to improve reliability of the pads, to prevent the pads from oxidizing, or to perform a wire bonding on the pads.

For the electrolytic plating, an electroplating line (hereinafter, referred to as a "plating line") is required to be designed when designing the printed circuit board.

The plating line is removed by a process such as an etching process after the electrolytic plating is completed. However, a portion of the plating line remains and causes a signal interference or an electromagnetic interference.

<CIT> discloses a circuit board comprising: a first signal trace present on a first inner layer of the circuit board; a via hole drilled through the circuit board and intersecting the first signal trace; conductive material in the via hole and in electrical contact with the first signal trace; and a first back drill verification feature on a first layer of the circuit board, wherein the first inner layer and the first layer are different layers, a first electrical connection existed between the first back drill verification feature and the conductive material before a first back drill operation, and the first back drill operation created gap and severed the first electrical connection. The first back drill verification feature may comprise a back drill verification signal trace in electrical contact with a second signal trace. Back drill verification feature and signal trace may be provided on outer layers. An improper or missing back drill operation is detected by an electrical connection between conductive material in via hole and signal trace. After the back drill operation, back drill verification feature remains electrically coupled to signal trace. Signal trace may carry a low frequency/DC signal, such a ground signal or a supply voltage.

<CIT> discloses a method that reduces an area of a mounting electrode provided on a first surface of a multilayer body and connected to a specific component and decreases a pitch between mounting electrodes. A plating film is formed on the mounting electrodes with the reduced area. The mounting electrodes for connection to specific components are defined by first end surfaces of first via conductors, and hence, the areas of the mounting electrodes are significantly reduced, and the pitch between the mounting electrodes is significantly decreased. Also, the mounting electrodes defined by the first end surfaces of the first via conductors are connected to plane electrodes at end surfaces of second via conductors exposed from a surface of the multilayer body with internal wiring electrodes interposed there between. Thus, a plating film is able to be reliably provided on the mounting electrodes.

To address the above-discussed deficiencies, it is a primary object to provide a printed circuit board capable of electrically separating a plurality of patterns, which were connected to each other through a via, from each other using a recess and an electronic device with the printed circuit board.

In addition, an aspect of the present disclosure is to provide a printed circuit board including a first pattern formed in a first layer, a second pattern formed in at least one second layer under the first layer, and a recess formed by removing at least a portion of an area in which a via, electrically connecting the first pattern to the second pattern, was formed to electrically separate the first pattern from the second pattern.

In accordance with an aspect of the present disclosure, a printed circuit board is according to claim <NUM> of the appended claims.

In accordance with an aspect of the present disclosure, an electronic device is according to claim <NUM> of the appended claims.

According to an embodiments of present disclosure, the length of the stubs, which are formed by the dummy line, may be reduced without interfering the connection of the signal line through the via.

Those skilled in the art will understand that the invention is as defined in the appended claims.

The terms of a singular form may include plural forms unless otherwise specified. In the present disclosure, the expressions "A or B", "at least one of A and/or B", "A, B, or C", or at least one of "A, B and/or C" may include all possible combinations of one or more of the associated listed items. The terms such as "first", "second", and the like used herein may refer to various elements regardless of the order and/or priority of the elements and may be used to distinguish an element from another element, not to limit the elements. It will be understood that when an element (e.g., a first element) is referred to as being "(operatively or communicatively) coupled with/to" or "connected to" another element (e.g., a second element), the element may be directly coupled with/ to or connected to the another element or an intervening element (e.g., a third element) may be present there between.

In the present disclosure, according to the situation, the expression "adapted to or configured to" used herein may be interchangeably used with, for example, the expression "suitable for", "having the capacity to", "changed to", "made to", "capable of", or "designed to" "adapted to", "made to", or "capable of". Under a certain situation, the expression "a device configured to" may mean that the device is "capable of" operating together with another device or other components. For example, a "processor configured to (or adapted to) perform A, B, and C" may mean a dedicated processor (e.g., an embedded processor) for performing a corresponding operation or a generic-purpose processor (e.g., a central processing unit (CPU) or an application processor) which may perform corresponding operations by executing one or more software programs which are stored in a memory device.

<FIG> illustrates a block diagram showing a configuration of an electronic device according to an embodiment of the present disclosure.

Referring to <FIG>, an electronic device <NUM> according to an embodiment may include a memory <NUM>, a processor <NUM>, and an integrated module <NUM>. According to an embodiment, the memory <NUM>, the processor <NUM>, and the integrated module <NUM> may be mounted on at least one printed circuit board by an SMT process.

According to an embodiment, the memory <NUM> may store instructions to control the integrated module <NUM>. The memory <NUM> may be, for example, a volatile memory, such as an RAM, etc., a non-volatile memory, such as an ROM, a flash memory, etc., or a combination thereof.

According to an embodiment, the processor <NUM> may be electrically connected to the memory <NUM> and the integrated module <NUM>. The processor <NUM> may control the integrated module <NUM> using the instructions stored in the memory <NUM>. For instance, the processor <NUM> may include at least one of a central processing unit (CPU), a graphic processing unit (GPU), a microprocessor, a digital signal processor (DSP), an application processor (AP), or various custom semiconductors (e.g., an application specific integrated circuit (ASIC), field programmable gate arrays (FPGA)) and may include a plurality of cores.

According to an embodiment, the integrated module <NUM> may be a hardware module to execute a specific function. For instance, the integrated module <NUM> may be a hardware module, such as a camera module, a memory, a processor, a melody IC, an LCD driver IC, a power IC, etc., which executes various functions. The integrated module <NUM> may be manufactured by a semiconductor process. In an embodiment, the integrated module <NUM> may be configured with at least one component element. The at least one component element may include, for example, at least one of a processor, an image sensor, a memory, a switching device (e.g., an FET, a transistor, etc.), or a passive device (e.g., a resistor, a capacitor, a transistor, etc.). At least a portion of the integrated module <NUM> may be mounted on a printed circuit board <NUM> (refer to <FIG>). The printed circuit board <NUM> (refer to <FIG>) may be, for example, a semiconductor substrate to which each of the component elements is wire-bonded or a substrate on which the processor <NUM>, the memory <NUM>, and the integrated module <NUM> are mounted by the SMT process.

<FIG> of the present disclosure a block diagram showing an integrated module according to an embodiment of the present disclosure, <FIG> and <FIG> illustrate side views showing a printed circuit board of an integrated module not according to the invention, <FIG> and <FIG> illustrate equivalent circuit diagrams showing a printed circuit board not according to the invention, and <FIG> and <FIG> illustrate top views showing a printed circuit board not according to the invention. For the convenience of explanation, <FIG> show two layers of the printed circuit board, but the number of the layers of the printed circuit board should not be limited to two.

Referring to <FIG>, the integrated module <NUM> may include the at least one component element <NUM> and the printed circuit board <NUM>. For the convenience of explanation, <FIG> shows a case in which the integrated module <NUM> includes one component element <NUM> as a representative example, but the number of the component elements should not be limited to one.

According to an embodiment, the at least one component element <NUM> may include a component forming the integrated module <NUM> that implements a specific function. The at least one component element <NUM> may include at least one pin <NUM> that is wire-bonded. Each pin of the component element <NUM> may be wire-bonded on a pad <NUM> of the printed circuit board <NUM>. The pins <NUM> of the component elements may be connected to each other through a pattern and a via on the printed circuit board <NUM>. For instance, each pin <NUM> of each component element <NUM> may be electrically connected to another pin of at least another component element through the pad <NUM>, the pattern, and the via on the printed circuit board <NUM>. The component element <NUM> may include, for example, at least one of the processor, the image sensor, the memory, the switching device (e.g., the FET, the transistor, etc.), or the passive device (e.g., the resistor, the capacitor, the transistor, etc.).

In an embodiment, the printed circuit board <NUM> may include a plurality of pads <NUM>, a signal line <NUM> (refer to <FIG>), a first pattern <NUM>, and a via <NUM>. The pads <NUM> may be wire-bonded to the pins of the component element <NUM>, respectively. The pads <NUM> may be disposed on an outer layer (e.g., a top layer, a bottom layer, etc.) of the printed circuit board <NUM>. The signal line may be a routing pattern that electrically connects the pads <NUM> of the at least one component element <NUM> to the pins <NUM>, respectively, such that each function of the integrated module <NUM> is implemented. The first pattern <NUM> may be, for example, a plating line branched from the signal line to electroplate (e.g., a soft electroplating) each pad <NUM>. For instance, the first pattern <NUM> may be generated by using at least one signal line <NUM> (e.g., a portion of the first pattern <NUM>) (e.g., a ground) of the printed circuit board <NUM> and may include a dummy line to apply a current to the signal lines <NUM> on the printed circuit board <NUM> in batches. At least a portion of the dummy line of the first pattern <NUM> may be removed after the electrolytic plating is performed. Since the at least portion of the dummy line is removed, the dummy line may be electrically separated from the signal line <NUM>. For instance, the dummy line may be removed by an etching process or a drill process.

In an embodiment, a first end <NUM> of the first pattern <NUM> may be disposed on the outer layer of the printed circuit board <NUM> as a current application point for the electrolytic Au plating. At least a portion of the signal line <NUM> connected to the at least one pad <NUM> may be disposed on at least one of the outer layer or an inner layer of the printed circuit board <NUM>. In a case that the signal line <NUM> connected to each pad <NUM> is disposed in the inner layer of the printed circuit board <NUM>, the first pattern <NUM> may be connected to the signal line <NUM> through the via <NUM>.

Referring to <FIG>, the illustrative printed circuit board <NUM> not according to the invention may include at least two layers (e.g., <NUM> and <NUM>), and the printed circuit board <NUM> may include a first pad <NUM>, a second pad <NUM>, a plurality of vias <NUM>, <NUM>, and <NUM>, the signal line <NUM>, and the first pattern <NUM>. The first pad <NUM> and the second pad <NUM> may be pads wire-bonded to each pin of the at least one component element <NUM>. For instance, the first and second pads <NUM> and <NUM> may be pads connected to two pins included in one component element or pads connected to two pins respectively included in different component elements. In an embodiment, the first pad <NUM> of the printed circuit board <NUM> may be connected to the second pad <NUM> through a first via <NUM>, a first pattern <NUM>, and a second via <NUM>.

The signal line <NUM> may be disposed in the inner layer <NUM> of the printed circuit board <NUM> and connected to the first and second pads <NUM> and <NUM> through the first and second vias <NUM> and <NUM>. The first pattern <NUM> may be connected to the signal line <NUM> through a third via <NUM>, and thus the plating line may be connected to the first and second pads <NUM> and <NUM>. Due to the connection structure, when the current is applied to the first pattern <NUM> through the first end <NUM> of the first pattern <NUM>, the current may be applied to the first and second pads <NUM> and <NUM> through the vias <NUM>, <NUM>, and <NUM> and the signal line <NUM>, and thus the first and second pads <NUM> and <NUM> may be electroplated. Since a process in which the first pattern <NUM> is electroplated by immersing the electroplating line in an electrolyte solution may be derived from known technologies by a person skilled in the art, details thereof will be omitted.

In an embodiment, a first area <NUM> may be formed at a portion of an upper end of the first pattern <NUM> in the outer layer <NUM> of the printed circuit board <NUM> to etch the first pattern <NUM>. A solder resist <NUM> may not be formed in the first area <NUM> such that the first pattern <NUM> is disconnected by the etching process. Accordingly, when the etching process is performed on the printed circuit board <NUM>, i.e., when the printed circuit board <NUM> is immersed in an etching solution, the plating line may be etched in the first area <NUM>. As a result, a first recess <NUM> may be formed in the first area <NUM>.

As shown in <FIG>, when the etching process is performed on the first area <NUM> of the printed circuit board <NUM>, the electroplating line placed in the first area <NUM> may be etched, and thus the first recess <NUM> may be formed in the first area <NUM>. In an embodiment, since the first pattern <NUM> remains on the printed circuit board <NUM> in an area except for the area at which the first recess <NUM> is placed, a second area <NUM> of the electroplating line extending from the signal line <NUM> and remaining on the printed circuit board <NUM> may serve as a stub, and thus noises may be introduced into the signal line <NUM>. As described above, as a length of the second area <NUM> decreases, it is advantageous to prevent the noises from being introduced.

<FIG> and <FIG> illustrate views showing a printed circuit board according to an embodiment of the present disclosure. <FIG> is a cross-sectional view showing a first side surface of a printed circuit board according to an embodiment, <FIG> is a cross-sectional view showing a second side surface of the printed circuit board, which is substantially perpendicular to the first side surface according to an embodiment, and <FIG> is a top view showing the printed circuit board according to an embodiment. <FIG> show the printed circuit board before and after performing an etching process according to an embodiment. There are different features in the etching of the electroplating line between <FIG> and <FIG>, and thus, hereinafter the different features will be mainly described.

Referring to <FIG>, the printed circuit board <NUM> may include a first pad <NUM>, a second pad <NUM>, a first pattern <NUM>, a second pattern <NUM>, a via <NUM>, and a recess <NUM>. The printed circuit board <NUM> may include a plurality of pads wire-bonded to the component element <NUM>. However, for the convenience of explanation, <FIG> and <FIG> show a case in which the printed circuit board <NUM> includes two pads as a representative example. In addition, <FIG> and <FIG> show some layers (first and second layers) of the printed circuit board <NUM> as a representative example, but the number of the layers of the printed circuit board <NUM> should not be limited thereto or thereby.

In an embodiment, the printed circuit board <NUM> may have a stack structure of at least two layers including an upper layer <NUM> and a lower layer <NUM>. In an embodiment, each layer of the printed circuit board <NUM> may be formed by attaching a thin plate to one surface of an insulating plate, etching the thin plate along a circuit pattern (e.g., <NUM>), and forming a via hole (e.g., <NUM>). Accordingly, the printed circuit board <NUM> may have a structure in which the insulating plate (e.g., a phenol resin) and the thin plate (e.g., a copper plate) are alternately stacked with each other. In an embodiment, an insulating material <NUM> (e.g., a solder resist), such as a solder resist, may be coated on outer layers (a top layer and a bottom layer) of the printed circuit board <NUM>.

As shown in <FIG> and <FIG>, the upper layer <NUM> may be the outer layer, and the lower layer <NUM> may be the inner layer or the outer layer. For instance, in a case that the upper layer <NUM> is the top layer, the lower layer <NUM> may be the inner layer or the bottom layer. As described above, the present embodiment may be applied to not only the via formed through the outer layer and the inner layer but also the via formed between the outer layers. However, for the convenience of explanation, <FIG> shows the upper layer corresponding to the outer layer and the lower layer corresponding to the inner layer.

According to an embodiment, the first and second pads <NUM> and <NUM> may be pads connected to each pin of the at least one component element <NUM> by a wire-bonding method. For instance, the first and second pads <NUM> and <NUM> may be pads connected to two pins included in one component element or pads connected to two pins respectively included in different component elements. In an embodiment, the first pad <NUM> of the printed circuit board <NUM> may be connected to the second pad <NUM> through a first via <NUM>, the first pattern <NUM>, and a second via <NUM>.

According to an embodiment, the first pattern <NUM> may be a pattern that applies a current to a pad, which is wire-bonded and electroplated, of an integrated module <NUM> including the first pad <NUM> and the second pad <NUM>. At least a portion of the first pattern <NUM>, for example, a first end <NUM> of the first pattern <NUM> may be disposed on the outer layer <NUM> of the printed circuit board <NUM>. The first pattern <NUM> may be a pattern having a wide width, such as a ground, a power line, etc..

According to an embodiment, the second pattern <NUM> may be a routing pattern to electrically connect the first pad <NUM> to the second pad <NUM>. The second pattern <NUM> may be branched from the first pattern <NUM>, which is connected to the first pad <NUM> and the second pad <NUM>, through the via <NUM> and electrically connected to the first pattern <NUM>. As shown in <FIG> and <FIG>, the second pattern <NUM> may be formed in the inner layer <NUM> of the printed circuit board <NUM> and connected to the first pad <NUM> and the second pad <NUM> through the first and second vias <NUM> and <NUM>.

According to an embodiment, the via <NUM> may electrically connect the second pattern <NUM> placed in the lower layer <NUM> of the printed circuit board <NUM> to the first pattern <NUM> placed in the upper layer <NUM> of the printed circuit board <NUM>. For instance, the via <NUM> may be a thru-hole via that vertically connects the upper layer <NUM> of the printed circuit board <NUM> to the lower layer <NUM> of the printed circuit board <NUM> or a staggered via that connects the upper layer <NUM> of the printed circuit board <NUM> to the lower layer <NUM> of the printed circuit board <NUM> in a zigzag shape. As described above, the embodiment may employ a variety of vias.

According to an embodiment, the recess <NUM> may be formed in the printed circuit board <NUM> by removing at least a portion of the printed circuit board <NUM> in an area in which the via <NUM> is formed, and thus the first pattern <NUM> may be electrically separated from the second pattern <NUM>. In an embodiment, the via <NUM> may be formed by filling a conductive material in a hole penetrating through at least a portion of the first pattern <NUM> of the upper layer <NUM> and at least a portion of the second pattern <NUM> of the lower layer <NUM>, and thus the via <NUM> may electrically connect the first pattern <NUM> to the second pattern <NUM>. In an embodiment, the recess <NUM> may be formed in the via <NUM> to have a size and a shape, which are appropriate to remove the conductive material in the hole of the via <NUM> to electrically separate the first pattern <NUM> from the second pattern <NUM>.

According to an embodiment, the first pattern <NUM> may be disconnected by the recess <NUM> or may not be disconnected. For instance, in a case that the first pattern <NUM> has a width exceeding a diameter of the recess <NUM>, the recess <NUM> may not disconnect the first pattern <NUM>. The first pattern <NUM> having the width exceeding the diameter of the recess <NUM> may be a power line and a ground. As another example, in a case that the width of the first pattern <NUM> is equal to or smaller than the diameter of the recess <NUM>, the recess <NUM> may disconnect the first pattern <NUM>. Since the largest number of the grounds and the power lines are disposed on the printed circuit board <NUM>, the number of the dummy lines for the plating may be reduced in the case that the ground and the power line are used as the first pattern <NUM>.

According to an embodiment, the recess <NUM> may be formed in the printed circuit board <NUM> through various processes. For instance, the recess <NUM> may be formed by etching a portion of the via <NUM> formed in the upper layer <NUM> of the printed circuit board <NUM> through an etching process (e.g., an etch back process). The recess <NUM> may be formed by a drill process that irradiates a laser beam on an upper portion (a portion formed on the outer layer) of the via <NUM>. As described above, the recess according to the embodiment may be applied to the printed circuit board <NUM> through various processes.

Referring to the via <NUM> before being etched as shown in <FIG>, the second pattern <NUM> may be connected to the first pad <NUM> and the second pad <NUM> through the first via <NUM> and the second via <NUM>, and the first pattern <NUM> may be connected to the second pattern <NUM> through the via <NUM>. As shown in <FIG>, the insulating material <NUM> may be coated on a portion of the upper layer of the printed circuit board <NUM>, which is not soldered. However, the insulating material <NUM> may not be coated on a first area <NUM> of the upper layer <NUM> placed above the via <NUM> according to the embodiment. In the present disclosure, a structure in which the insulating material <NUM> is not coated on the upper end of the via <NUM> will be described as a representative example.

Referring to the via <NUM> after being etched as shown in <FIG>, when the first area <NUM> of the printed circuit board <NUM> is etched by a process such as the etch back process, the recess <NUM> may be formed in the first area <NUM> on the via <NUM> to separate the first pattern <NUM> from the second pattern <NUM>. As described above, according to the embodiment, since a branch point at which the dummy line for the plating (e.g., <NUM>) is branched from the signal line (e.g., <NUM>) is disconnected, a length (e.g., about <NUM>) of the plating line connected to the signal line may be significantly reduced, and thus the noises and signal attenuation, which are caused by the plating line, may be prevented from occurring on the signal line.

In an embodiment, a depth of the recess <NUM> may be determined depending on the etching solution and an etching time. Referring to <FIG> and <FIG>, the recess <NUM> may be formed to have a depth appropriate to remove the area placed in the upper layer <NUM> of the via <NUM>. For instance, a depth dep1 of the recess <NUM> may be equal to or greater than a thickness t1 of the first pattern <NUM> of the printed circuit board <NUM> and equal to or smaller than a total thickness t2 of the upper layer <NUM> of the printed circuit board <NUM>. As another way, the depth dep1 of the recess <NUM> may be equal to or greater than the thickness t1 of the first pattern <NUM> and equal to or smaller than a distance d1 between an upper surface of the first pattern <NUM> and an upper surface of the second pattern <NUM>. The former example may be easier to carry out than the latter example, and the latter example may more reduce the introduction of the noises, which is caused by the first pattern <NUM>, than the former example. In an embodiment, each of the patterns <NUM> and <NUM> of the printed circuit board <NUM> may correspond to a thickness of the thin plate of each layer of the printed circuit board <NUM>. The thickness of each layer of the printed circuit board <NUM> may correspond to a thickness including the thin plate and the insulating plate of each layer of the printed circuit board <NUM>. In the present disclosure, since the structure in which the insulating material <NUM> is not coated on the upper end of the recess <NUM> is described, the depth of the recess <NUM> is calculated without considering the insulating material <NUM>. Accordingly, in a case that the insulating material <NUM> is coated on the upper end of the recess <NUM>, the depth of the recess <NUM> may increase by a thickness of the insulating material <NUM>.

<FIG> and <FIG> show the structure in which the second pattern <NUM> is formed in the inner layer <NUM> of the printed circuit board adjacent to the upper layer <NUM> of the printed circuit board and the total thickness t2 of the upper layer <NUM> of the printed circuit board is equal to the distance d1 between the upper surface of the upper layer and the upper surface of the second pattern <NUM>, but it should not be limited thereto or thereby. The insulating material may be coated on the upper end of the recess <NUM> by an additional process. Accordingly, the via <NUM> in the recess <NUM> may be prevented from being exposed in the present embodiment.

In an embodiment, in the case that the signal line is disposed on a different layer from and connected to the plating line through the via, the length of the plating line connected to the signal line may be significantly reduced by etching the portion of the via at the branch point at which the plating line is branched from the signal line. Accordingly, the introduction of the noises, which is caused by the plating line, may be improved in the present embodiment.

According to an embodiment, the first pattern <NUM> may be the signal line rather than the dummy line for the plating. As an example, in a case that the first pattern <NUM> on the outer layer of the printed circuit board is separated from the second pattern <NUM> on at least one lower layer of the printed circuit board due to a process error on the printed circuit board <NUM>, the first pattern <NUM> and the second pattern <NUM> may be electrically separated from each other by the recess <NUM>.

According to an embodiment, the printed circuit board <NUM> may be a printed circuit board of an electronic device <NUM> rather than the semiconductor substrate as described above. In this case, the first and second pads <NUM> and <NUM> may be connected to each pin of the component element <NUM> through the routing pattern.

<FIG> illustrates a view showing a structure in which a via of a lower layer of a printed circuit board is connected to a second pattern according to an embodiment of the present disclosure, <FIG> illustrates a cross-sectional view showing a printed circuit board having a structure in which a via is connected to a second pattern according to an embodiment of the present disclosure, and <FIG> illustrate as a cross-sectional view showing a printed circuit board to explain a depth of a recess formed in at least a portion of a via according to an embodiment of the present disclosure. <FIG> illustrates a view showing a structure in which a via of a lower layer of a printed circuit board is connected to a second pattern according to an embodiment of the present disclosure, <FIG> illustrates a cross-sectional view showing a printed circuit board having a structure in which a via is connected to a second pattern according to an embodiment of the present disclosure, and <FIG> illustrates a cross-sectional view showing a printed circuit board to explain a depth of a recess formed in at least a portion of a via according to an embodiment of the present disclosure. <FIG> illustrates a cross-sectional view showing a printed circuit board having a structure in which a via is connected to first, second, and third patterns according to an embodiment of the present disclosure. <FIG> illustrates a cross-sectional view showing a printed circuit board to explain a depth of a recess that electrically separates first, second, and third patterns according to an embodiment of the present disclosure, and <FIG> illustrates a cross-sectional view showing a printed circuit board to explain a depth of a recess that electrically separates a first pattern from second and third patterns while the second pattern is not electrically separated from the third pattern according to an embodiment of the present disclosure. In <FIG>, an "a" point may be a first end of a first pattern <NUM> connected to an electrolytic plating apparatus. <FIG> show the structure in which the insulating material is not coated on the upper end of the via <NUM> of the printed circuit board <NUM>.

As shown in <FIG>, the via <NUM> according to the embodiment may be formed in the printed circuit board <NUM> to be included in not only the first pattern <NUM> but also in the second pattern <NUM>. As an example, the via <NUM> may be formed such that at least <NUM>/<NUM> of a total area of a cross section of the via <NUM> in the lower layer <NUM> of the printed circuit board <NUM> overlaps with the second pattern <NUM>. Referring to <FIG>, since a center of the via <NUM> is located on a center line of the second pattern <NUM> in the lower layer <NUM> of the printed circuit board <NUM>, the via <NUM> may be formed such that most of the via <NUM> overlaps with the second pattern <NUM>. In this case, a depth dep2 of the recess <NUM> may be equal to or greater than the thickness of the first pattern <NUM> to disconnect the first pattern <NUM>. In addition, the depth dep2 of the recess <NUM> may be equal to or smaller than the distance between the upper surface of the first pattern <NUM> and the upper surface of the second pattern <NUM> to prevent the second pattern <NUM> from being disconnected.

As shown in <FIG> and <FIG>, the via <NUM> according to the embodiment may be formed such that most of the via <NUM> may deviate from the second pattern <NUM> in the lower layer <NUM> of the printed circuit board <NUM>. As an example, the via <NUM> may be formed such that an area less than <NUM>/<NUM> of the total area of the cross section of the via <NUM> in the lower layer <NUM> of the printed circuit board <NUM> overlaps with the second pattern <NUM>. Referring to <FIG>, the via <NUM> may be electrically connected to the second pattern <NUM> on a side surface of the second pattern <NUM> in the lower layer <NUM> of the printed circuit board <NUM>. In this case, a depth dep3 of the recess <NUM> may be equal to or greater than a distance between the upper surface of the first pattern <NUM> and the lower surface of the second pattern <NUM> and equal to or smaller than a total thickness of the printed circuit board <NUM>. However, the depth of the recess <NUM> may be changed depending on other patterns located under the second pattern <NUM> or a connection structure of the via <NUM>. Hereinafter, the embodiment shown in <FIG> will be described.

Referring to <FIG>, a printed circuit board <NUM> may include three layers <NUM>, <NUM>, and <NUM>. A via <NUM> may be a via that electrically connects a second pattern <NUM> located at a second layer of the printed circuit board <NUM> and a third pattern <NUM> located at a third layer of the printed circuit board <NUM> to a first pattern <NUM> located at a first layer of the printed circuit board <NUM>.

As an embodiment, in a case that the second pattern <NUM> and the third pattern <NUM> are different signal lines from each other, a recess <NUM> may be formed at a depth dep appropriate to electrically separate the first pattern <NUM>, the second pattern <NUM>, and the third pattern <NUM> from each other. For instance, as shown in <FIG>, the depth dep of the recess <NUM> may be equal to or greater than a distance between an upper surface of the first pattern <NUM> and a lower surface of the second pattern <NUM> and equal to or smaller than a distance between the upper surface of the first pattern <NUM> and an upper surface of the third pattern <NUM>.

As another embodiment, in a case that the second pattern <NUM> and the third pattern <NUM> are signal lines located in a plurality of lower layers <NUM> and <NUM> of the printed circuit board <NUM>, respectively, the recess <NUM> may be formed at a depth that electrically separates the first pattern <NUM> from the second pattern <NUM> while the second pattern <NUM> is not separated from the third pattern <NUM>. As another example, the recess <NUM> may be formed at a depth at which the second pattern <NUM> is not exposed to an outside of the printed circuit board <NUM>. As shown in <FIG>, the depth dep of the recess <NUM> may be equal to or greater than a thickness of the first pattern <NUM> and equal to or smaller than a distance between the upper surface of the first pattern <NUM> and an upper surface of the second pattern <NUM>.

In the embodiment, the recess may be formed above the via such that the length of the dummy line for the plating connected to the signal line is reduced depending on the structure of the via and the routing pattern connected to the via, and thus the noises may be prevented from being introduced.

<FIG> illustrates a cross-sectional view showing a printed circuit board in which a width of a first pattern is equal to or smaller than a diameter of a recess according to an embodiment of the present disclosure, <FIG> illustrates a top view showing a printed circuit board in which a width of a first pattern is equal to or smaller than a diameter of a recess according to an embodiment of the present disclosure, and <FIG> illustrates an equivalent circuit diagram showing a connection relation between first and second patterns before and after forming a recess in a printed circuit board in which a width of a first pattern is equal to or smaller than a diameter of the recess according to an embodiment of the present disclosure. <FIG> illustrates a cross-sectional view showing a printed circuit board in which a width of a first pattern exceeds a diameter of a recess according to an embodiment of the present disclosure, <FIG> illustrates a top view showing a printed circuit board in which a width of a first pattern exceeds a diameter of a recess according to an embodiment of the present disclosure, and <FIG> illustrates an equivalent circuit diagram showing a connection relation between first and second patterns before and after forming a recess in a printed circuit board in which a width of a first pattern exceeds a diameter of a recess according to an embodiment of the present disclosure. <FIG> show a structure in which a recess <NUM> is formed in a plating line with a width equal to or smaller than a diameter of the recess <NUM>. In <FIG>, an "a" point may be a first end of the first pattern <NUM> connected to an electrolytic plating apparatus. A "b" point may be a first end of the second pattern <NUM> connected to a first pad <NUM>, and a "c" point may be a second end of the second pattern <NUM> connected to a second pad <NUM>. The "b" point and the "c" point may be connected to the first pad <NUM> and the second pad <NUM> through different vias <NUM> and <NUM> (refer to <FIG>), but for the convenience of explanation, a connection structure between the first and second pads <NUM> and <NUM> and the second pattern <NUM> is omitted in <FIG>.

In a structure in which the first pattern <NUM> on an upper layer <NUM> of the printed circuit board is connected to the second pattern <NUM> of a lower layer <NUM> of the printed circuit board through the via <NUM> as shown in <FIG>, a width w1 of the first pattern <NUM> may be equal to or smaller than the diameter of the recess <NUM> as shown in <FIG>. In this case, the first end of the first pattern <NUM> may be disconnected by the recess <NUM> as shown in <FIG>.

In a structure in which the first pattern <NUM> on the upper layer <NUM> of the printed circuit board is connected to the second pattern <NUM> of the lower layer <NUM> of the printed circuit board through the via <NUM> as shown in <FIG>, the width w1 of the first pattern <NUM> may exceed the diameter of the recess <NUM> as shown in <FIG>. In this case, the first pattern <NUM> may not be disconnected by the recess <NUM> as shown in <FIG> and <FIG>. As an example, the first pattern <NUM> may be a pattern having a wide width, such as a ground, a power line, etc. In a case that a pattern which is largely located on the printed circuit board, such as the grounds, the power lines, etc., is used as the first pattern <NUM>, the dummy line for the plating may exert less influences on the routing of other signal lines.

According to an embodiment, the recess <NUM> may be formed in such a manner that the first pattern <NUM> is not disconnected regardless of the width of the first pattern <NUM>. For instance, the recess <NUM> may be formed at a position at which the first pattern <NUM> is not disconnected. The recess <NUM> may be formed in the upper layer <NUM> of the printed circuit board <NUM> such that a portion of the recess <NUM>, which is less than about <NUM>/<NUM> of a cross-sectional area of the recess <NUM>, overlaps with the first pattern <NUM>.

In an embodiment, the recess <NUM> may have various depths depending on the shape of the signal line connected to the via <NUM> and the connection relation with the dummy line. Accordingly, the length of the stubs, which are formed by the dummy line, may be reduced without interfering the connection of the signal line through the via <NUM>.

<FIG> illustrates a flowchart showing a method of manufacturing a printed circuit board according to an embodiment of the present disclosure.

In operation <NUM>, when the printed circuit board <NUM> is designed (e.g., an artwork), the via <NUM> may be formed such that the second pattern <NUM> formed in the lower layer <NUM> of the printed circuit board <NUM> is electrically connected to the first pattern <NUM> formed in the upper layer <NUM> of the printed circuit board <NUM>. In operation <NUM>, the insulating material may not be coated in the area of the upper layer <NUM> of the via <NUM>, which is exposed to the outside of the printed circuit board <NUM>.

In operation <NUM>, the electrolytic plating may be performed on the printed circuit board <NUM> by applying the current to the first end of the first pattern <NUM> and immersing the printed circuit board <NUM> into an electrolytic soft plating solution. Since a method of electroplating the printed circuit board <NUM> is disclosed in a related art, details thereof will be omitted.

In operation <NUM>, at least the portion of the area in which the via <NUM> of the printed circuit board <NUM> is formed may be removed, and thus the recess <NUM> may be formed to electrically separate the first pattern <NUM> from the second pattern <NUM>. For instance, the recess <NUM> may be formed by etching the exposed area of the upper layer <NUM> of the printed circuit board <NUM> through the etching process (e.g., the etch back process). As another example, the recess <NUM> may be formed by the drill process that irradiates the laser beam on the upper portion (the portion formed in the lower layer) of the via <NUM>. In operation <NUM>, the depth of the recess <NUM> may be determined depending on the connection structure between the recess <NUM> and the first pattern <NUM> or between the recess <NUM> and the second pattern <NUM> and the shape of the second pattern <NUM>. This is described with reference to <FIG>, and thus details thereof will be omitted.

The printed circuit board includes a first pattern configured to be formed in a first layer; a second pattern configured to be formed in at least one second layer under the first layer; a via configured to electrically connect the first pattern to the second pattern; and a recess configured to be formed by removing at least a portion of an area in which the via is formed and to electrically separate the first pattern from the second pattern.

The recess is configured to have a diameter equal to or greater than a width of the first pattern and to have a depth smaller than a distance between an upper surface of the first pattern and an upper surface of the second pattern.

The recess is configured not to electrically separate the second pattern.

When the second pattern is configured to comprise one signal line formed in a plurality of the second layers and the one signal line is configured to be connected through the via, the recess is configured to be formed at a depth such that the first pattern and the second pattern are electrically separated from each other and the signal line formed in the plurality of the second layers is not electrically separated.

The via is configured to be formed such that an area less than <NUM>/<NUM> of a cross sectional area of the via overlaps with the second pattern in a connection layer that electrically connects the first pattern to the second pattern in the at least one second layer, and the recess is configured to be formed at a diameter not to disconnect the second pattern of the connection layer.

When the second pattern is configured to comprise different signal lines formed in a plurality of the second layers and the signal lines are configured to be connected through the via, the recess is configured to be formed at a depth such that the signal lines is electrically separated each other.

The via is configured to be formed such that an area equal to or greater than <NUM>/<NUM> of a cross sectional area of the via overlaps with the signal lines in the at least one second layer, and the recess is formed to have a diameter to disconnect the signal lines.

An insulating material is not coated in an area in which the via is formed in the first layer, and the recess is configured to be formed by etching the area.

The recess is formed to have a diameter smaller than a width of the first pattern such that the first pattern is not disconnected on the first layer.

The first pattern is configured to comprise at least one of a ground or a power line.

The recess is formed to have a diameter equal to or greater than a width of the first pattern such that the first pattern is disconnected on the first layer.

An insulating material is coated on an upper end of the recess.

According to an embodiment, the printed circuit board further includes at least one component element mounted on the first layer, wherein the first pattern is a dummy line to electrolytically-softly plate each pad of the component element, and the second pattern is a signal line of the component element.

The at least one pad is formed in the first layer, and each pin of the component element is wire-bonded to the pad corresponding to the each pin.

According to an embodiment, an electronic device includes a printed circuit board configured to mount an integrated module thereon; a memory configured to store instructions therein that controls the integrated module; and a processor configured to be electrically connected to the integrated module and configured to control the integrated module using the instructions, the printed circuit board configured to comprise: a first pattern configured to be formed in a first layer; a second pattern configured to be formed in at least one second layer under the first layer; a via configured to electrically connect the first pattern to the second pattern; and a recess configured to be formed by removing at least a portion of an area in which the via is formed and to electrically separate the first pattern from the second pattern.

The first pattern is a dummy line to electrolytically-softly plate each pad of the printed circuit board, and the second pattern is a signal line disposed on the printed circuit board.

A diameter of the recess is configured to exceed a width of the first pattern such that the first pattern is disconnected on the first layer.

<FIG> illustrates an electronic device in a network environment system, according to embodiment of the present disclosure.

Referring to <FIG>, according to an embodiment of the present disclosure, an electronic device <NUM>, a first electronic device <NUM>, a second electronic device <NUM>, or a server <NUM> may be connected each other over a network <NUM> or a short range communication <NUM>. The electronic device <NUM> includes a bus <NUM>, a processor <NUM>, a memory <NUM>, an input/output interface <NUM>, a display <NUM>, and a communication interface <NUM>. The electronic device <NUM> may not include at least one of the above-described elements or may further include other element(s).

For example, the bus <NUM> may interconnect the above-described elements <NUM> to <NUM> and may include a circuit for conveying communications (e.g., a control message and/or data) among the above-described elements.

The processor <NUM> may include one or more of a central processing unit (CPU), an application processor (AP), or a communication processor (CP). For example, the processor <NUM> may perform an arithmetic operation or data processing associated with control and/or communication of at least other elements of the electronic device <NUM>.

The memory <NUM> may include a volatile and/or nonvolatile memory. For example, the memory <NUM> may store instructions or data associated with at least one other element(s) of the electronic device <NUM>. According to an embodiment of the present disclosure, the memory <NUM> stores software and/or a program <NUM>. The program <NUM> includes, for example, a kernel <NUM>, a middleware <NUM>, an application programming interface (API) <NUM>, and/or an application program (or "an application") <NUM>. At least a part of the kernel <NUM>, the middleware <NUM>, or the API <NUM> may be referred to as an operating system (OS).

For example, the kernel <NUM> may control or manage system resources (e.g., the bus <NUM>, the processor <NUM>, the memory <NUM>, and the like) that are used to execute operations or functions of other programs (e.g., the middleware <NUM>, the API <NUM>, and the application <NUM>). Furthermore, the kernel <NUM> may provide an interface that allows the middleware <NUM>, the API <NUM>, or the application <NUM> to access discrete elements of the electronic device <NUM> so as to control or manage system resources.

The middleware <NUM> may perform, for example, a mediation role such that the API <NUM> or the application <NUM> communicates with the kernel <NUM> to exchange data.

Furthermore, the middleware <NUM> may process task requests received from the application <NUM> according to a priority. For example, the middleware <NUM> may assign the priority, which makes it possible to use a system resource (e.g., the bus <NUM>, the processor <NUM>, the memory <NUM>, and the like) of the electronic device <NUM>, to at least one of the application <NUM>. For example, the middleware <NUM> may process the one or more task requests according to the priority assigned to the at least one, which makes it possible to perform scheduling or load balancing on the one or more task requests.

The API <NUM> may be, for example, an interface through which the application <NUM> controls a function provided by the kernel <NUM> or the middleware <NUM>, and may include, for example, at least one interface or function (e.g., an instruction) for a file control, a window control, image processing, a character control, and the like.

The input/output interface <NUM> may play a role, for example, of an interface which transmits an instruction or data input from a user or another external device, to other element(s) of the electronic device <NUM>. Furthermore, the input/output interface <NUM> may output an instruction or data, received from other element(s) of the electronic device <NUM>, to a user or another external device.

The display <NUM> may include, for example, a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, a microelectrome-chanical systems (MEMS) display, or an electronic paper display. The display <NUM> may display, for example, various content (e.g., a text, an image, a video, an icon, a symbol, and the like) to a user. The display <NUM> may include a touch screen and may receive, for example, a touch, gesture, proximity, or hovering input using an electronic pen or a part of a user's body.

The communication interface <NUM> may establish communication between the electronic device <NUM> and the first electronic device <NUM>, the second electronic device <NUM>, or the server <NUM>. For example, the communication interface <NUM> may be connected to the network <NUM> over wireless communication or wired communication to communicate with the second electronic device <NUM> or the server <NUM>.

The wireless communication may use at least one of, for example, long-term evolution (LTE), LTE advanced (LTE-A), code division multiple access (CDMA), wideband CDMA (WCDMA), universal mobile telecommunications system (UMTS), wireless broadband (WiBro), global system for mobile communications (GSM), and the like, as cellular communication protocol. Furthermore, the wireless communication may include, for example, the short range communication <NUM>. The short range communication <NUM> may include at least one of wireless fidelity (Wi-Fi), light fidelity (Li-Fi), Bluetooth, near field communication (NFC), magnetic stripe transmission (MST), a global navigation satellite system (GNSS), and the like.

The MST may generate a pulse in response to transmission data using an electromagnetic signal, and the pulse may generate a magnetic field signal. The electronic device <NUM> may transfer the magnetic field signal to a POS terminal, and the POS terminal may detect the magnetic field signal using a MST reader. The POS may recover the data by converting the detected magnetic field signal to an electrical signal.

The GNSS may include at least one of, for example, a global positioning system (GPS), a global navigation satellite system (Glonass), a Beidou navigation satellite system (Beidou), or an European global satellite-based navigation system (Galileo) based on an available region, a bandwidth, and the like. Hereinafter, in the present disclosure, the terms "GPS? and "GNSS" may be interchangeably used. The wired communication may include at least one of, for example, a universal serial bus (USB), a high definition multimedia interface (HDMI), a recommended standard-<NUM> (RS-<NUM>), a plain old telephone service (POTS), and the like. The network <NUM> may include at least one of telecommunications networks, for example, a computer network (e.g., LAN or WAN), the Internet, or a telephone network.

Each of the first and second electronic devices <NUM> and <NUM> may be a device of which the type is different from or the same as that of the electronic device <NUM>. According to an embodiment of the present disclosure, the server <NUM> may include a group of one or more servers. All or a portion of operations that the electronic device <NUM> will perform may be executed by another or the first electronic device <NUM>, the second electronic device <NUM> or the server <NUM>. In the case where the electronic device <NUM> executes any function or service automatically or in response to a request, the electronic device <NUM> may not perform the function or the service internally, but, alternatively additionally, it may request at least a portion of a function associated with the electronic device <NUM> be performed with the electronic device <NUM> or <NUM> or the server <NUM>. The other electronic device may execute the requested function or additional function and may transmit the execution result to the electronic device <NUM>. The electronic device <NUM> may provide the requested function or service using the received result or may additionally process the received result to provide the requested function or service. To this end, for example, cloud computing, distributed computing, or client-server computing may be used.

<FIG> illustrates a block diagram of an electronic device, according to an embodiment of the present disclosure.

Referring to <FIG>, an electronic device <NUM> may include, for example, all or a part of the electronic device <NUM> illustrated in <FIG>. The electronic device <NUM> includes one or more application processors AP <NUM>, a communication module <NUM>, a subscriber identification module <NUM>, a memory <NUM>, a sensor module <NUM>, an input device <NUM>, a display <NUM>, an interface <NUM>, an audio module <NUM>, a camera module <NUM>, a power management module <NUM>, a battery <NUM>, an indicator <NUM>, and a motor <NUM>.

The processor <NUM> may drive, for example, an operating system (OS) or an application to control a plurality of hardware or software elements connected to the processor <NUM> and may process and compute a variety of data. For example, the processor <NUM> may be implemented with a system on chip. According to an embodiment of the present disclosure, the processor <NUM> may further include a graphic processing unit (GPU) and/or an image signal processor. The processor <NUM> may include at least a part (e.g., a cellular module <NUM>) of elements illustrated in <FIG>. The processor <NUM> may load an instruction or data, which is received from at least one of other elements (e.g., a nonvolatile memory), into a volatile memory and process the loaded instruction or data. The processor <NUM> may store a variety of data in the non-volatile memory.

The communication module <NUM> may be configured the same as or similar to the communication interface <NUM> of <FIG>. The communication module <NUM> includes the cellular module <NUM>, a Wi-Fi module <NUM>, a Bluetooth™ (BT) module <NUM>, a GNSS module <NUM> (e.g., a GPS module, a Glonass module, a Beidou module, or a Galileo module), a near field communication (NFC) module <NUM>, a MST module <NUM> and a radio frequency (RF) module <NUM>.

The cellular module <NUM> may provide, for example, voice communication, video communication, a character service, an Internet service, and the like over a communication network. According to an embodiment of the present disclosure, the cellular module <NUM> may perform discrimination and authentication of the electronic device <NUM> within a communication network by using the subscriber identification module (e.g., a SIM card) <NUM>. The cellular module <NUM> may perform at least a portion of functions that the processor <NUM> provides. The cellular module <NUM> may include a communication processor (CP).

Each of the Wi-Fi module <NUM>, the BT module <NUM>, the GNSS module <NUM>, the NFC module <NUM>, or the MST module <NUM> may include a processor for processing data exchanged through a corresponding module, for example. According to an embodiment of the present disclosure, at least a part (e.g., two or more) of the cellular module <NUM>, the Wi-Fi module <NUM>, the BT module <NUM>, the GNSS module <NUM>, the NFC module <NUM>, or the MST module <NUM> may be included within one integrated circuit (IC) or an IC package.

For example, the RF module <NUM> may transmit and receive a communication signal (e.g., an RF signal). For example, the RF module <NUM> may include a transceiver, a power amplifier module (PAM), a frequency filter, a low noise amplifier (LNA), an antenna, and the like. According to another embodiment of the present disclosure, at least one of the cellular module <NUM>, the Wi-Fi module <NUM>, the BT module <NUM>, the GNSS module <NUM>, the NFC module <NUM>, or the MST module <NUM> may transmit and receive an RF signal through a separate RF module.

The subscriber identification module <NUM> may include, for example, a card and/or embedded SIM that includes a subscriber identification module and may include unique identify information (e.g., integrated circuit card identifier (ICCID)) or subscriber information (e.g., integrated mobile subscriber identity (IMSI)).

The memory <NUM> (e.g., the memory <NUM>) includes an internal memory <NUM> or an external memory <NUM>. For example, the internal memory <NUM> may include at least one of a volatile memory (e.g., a dynamic random access memory (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), and the like), a nonvolatile memory (e.g., a one-time programmable read only memory (OTPROM), a programmable ROM (PROM), an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a mask ROM, a flash ROM, a flash memory (e.g., a NAND flash memory or a NOR flash memory), and the like), a hard drive, or a solid state drive (SSD).

The external memory <NUM> may further include a flash drive such as compact flash (CF), secure digital (SD), micro secure digital (micro-SD), mini secure digital (mini-SD), extreme digital (xD), a multimedia card (MMC), a memory stick, and the like. The external memory <NUM> may be operatively and/or physically connected to the electronic device <NUM> through various interfaces.

A security module <NUM> may be a module that includes a storage space of which a security level is higher than that of the memory <NUM> and may be a circuit that guarantees safe data storage and a protected execution environment. The security module <NUM> may be implemented with a separate circuit and may include a separate processor. For example, the security module <NUM> may be in a smart chip or a secure digital (SD) card, which is removable, or may include an embedded secure element (eSE) embedded in a fixed chip of the electronic device <NUM>. Furthermore, the security module <NUM> may operate based on an operating system (OS) that is different from the OS of the electronic device <NUM>. For example, the security module <NUM> may operate based on java card open platform (JCOP) OS.

The sensor module <NUM> may measure, for example, a physical quantity or may detect an operation state of the electronic device <NUM>. The sensor module <NUM> may convert the measured or detected information to an electric signal. For example, the sensor module <NUM> includes at least one of a gesture sensor 1140A, a gyro sensor 1140B, a barometric pressure sensor 1140C, a magnetic sensor 1140D, an acceleration sensor 1140E, a grip sensor 1140F, the proximity sensor <NUM>, a color sensor <NUM> (e.g., red, green, blue (RGB) sensor), a biometric sensor 1140I, a temperature/humidity sensor 1140J, an illuminance sensor <NUM>, or an UV sensor <NUM>. The sensor module <NUM> may further include, for example, an E-nose sensor, an electromyography (EMG) sensor, an electroencephalogram (EEG) sensor, an electrocardiogram (ECG) sensor, an infrared (IR) sensor, an iris sensor, and/or a fingerprint sensor. The sensor module <NUM> may further include a control circuit for controlling at least one or more sensors included therein. According to an embodiment of the present disclosure, the electronic device <NUM> may further include a processor that is a part of the processor <NUM> or independent of the processor <NUM> and is configured to control the sensor module <NUM>. The processor may control the sensor module <NUM> while the processor <NUM> remains at a sleep state.

The input device <NUM> includes, for example, a touch panel <NUM>, a (digital) pen sensor <NUM>, a key <NUM>, or an ultrasonic input unit <NUM>. For example, the touch panel <NUM> may use at least one of capacitive, resistive, infrared and ultrasonic detecting methods. Also, the touch panel <NUM> may further include a control circuit. The touch panel <NUM> may further include a tactile layer to provide a tactile reaction to a user.

The (digital) pen sensor <NUM> may be, for example, a part of a touch panel or may include an additional sheet for recognition. The key <NUM> may include, for example, a physical button, an optical key, a keypad, and the like. The ultrasonic input device <NUM> may detect (or sense) an ultrasonic signal, which is generated from an input device, through a microphone <NUM> and may check data corresponding to the detected ultrasonic signal.

The display <NUM> (e.g., the display <NUM>) may include a panel <NUM>, a hologram device <NUM>, or a projector <NUM>. The panel <NUM> may be the same as or similar to the display <NUM> illustrated in <FIG>. The panel <NUM> may be implemented, for example, to be flexible, transparent or wearable. The panel <NUM> and the touch panel <NUM> may be integrated into a single module. The hologram device <NUM> may display a stereoscopic image in a space using a light interference phenomenon. The projector <NUM> may project light onto a screen so as to display an image. For example, the screen may be arranged in the inside or the outside of the electronic device <NUM>. According to an embodiment of the present disclosure, the display <NUM> may further include a control circuit for controlling the panel <NUM>, the hologram device <NUM>, or the projector <NUM>.

The interface <NUM> includes, for example, a high-definition multimedia interface (HDMI) <NUM>, a universal serial bus (USB) <NUM>, an optical interface <NUM>, or a D-subminiature (D-sub) <NUM>. The interface <NUM> may be included, for example, in the communication interface <NUM> illustrated in <FIG>. Additionally or generally, the interface <NUM> may include, for example, a mobile high definition link (MHL) interface, a SD card/multi-media card (MMC) interface, or an infrared data association (IrDA) standard interface.

The audio module <NUM> may convert a sound and an electric signal in dual directions. At least a part of the audio module <NUM> may be included, for example, in the input/ output interface <NUM> illustrated in <FIG>. The audio module <NUM> may process, for example, sound information that is input or output through a speaker <NUM>, a receiver <NUM>, an earphone <NUM>, or the microphone <NUM>.

The camera module <NUM> may shoot a still image or a video. According to an embodiment of the present disclosure, the camera module <NUM> may include at least one or more image sensors (e.g., a front sensor or a rear sensor), a lens, an image signal processor (ISP), or a flash (e.g., an LED or a xenon lamp).

The power management module <NUM> may manage, for example, power of the electronic device <NUM>. According to an embodiment of the present disclosure, a power management integrated circuit (PMIC), a charger IC, or a battery gauge may be included in the power management module <NUM>. The PMIC may have a wired charging method and/or a wireless charging method. The wireless charging method may include, for example, a magnetic resonance method, a magnetic induction method or an electromagnetic method and may further include an additional circuit, for example, a coil loop, a resonant circuit, or a rectifier, and the like. The battery gauge may measure, for example, a remaining charge capacity of the battery <NUM> and a voltage, current or temperature thereof while the battery is charged. The battery <NUM> may include, for example, a rechargeable battery and/or a solar battery.

The indicator <NUM> may display a specific state of the electronic device <NUM> or a part thereof (e.g., the processor <NUM>), such as a booting state, a message state, a charging state, and the like. The motor <NUM> may convert an electrical signal into a mechanical vibration and may generate the following effects: vibration, haptic, and the like. A processing device (e.g., a GPU) for supporting a mobile TV may be included in the electronic device <NUM>. The processing device for supporting the mobile TV may process media data according to the standards of digital multimedia broadcasting (DMB), digital video broadcasting (DVB), MediaFlo™, and the like.

Each of the above-mentioned elements of the electronic device according to an embodiment of the present disclosure may be configured with one or more components, and the names of the elements may vary according to the type of the electronic device. The electronic device may include at least one of the above-mentioned elements, and some elements may be omitted or other additional elements may be added. Furthermore, some of the elements of the electronic device may be combined with each other so as to form one entity, so that the functions of the elements may be performed in the same manner as before the combination.

<FIG> illustrates a block diagram of a program module, according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, a program module <NUM> (e.g., the program <NUM>) may include an operating system (OS) to control resources associated with the electronic device <NUM>, and/or diverse applications (e.g., the application program <NUM>) driven on the OS. The OS may be, for example, Android™, iOS™, Windows™, Symbian™, or Tizen™.

The program module <NUM> includes a kernel <NUM>, a middleware <NUM>, an application programming interface (API) <NUM>, and/or an application <NUM>. At least a portion of the program module <NUM> may be preloaded on an electronic device or may be downloadable from the first electronic device <NUM>, the second electronic device <NUM>, the server <NUM>, and the like.

The kernel <NUM> (e.g., the kernel <NUM>) includes, for example, a system resource manager <NUM> or a device driver <NUM>. The system resource manager <NUM> may perform control, allocation, or retrieval of system resources. According to an embodiment of the present disclosure, the system resource manager <NUM> may include a process managing unit, a memory managing unit, or a file system managing unit. The device driver <NUM> may include, for example, a display driver, a camera driver, a Bluetooth driver, a shared memory driver, a USB driver, a keypad driver, a Wi-Fi driver, an audio driver, or an inter-process communication (IPC) driver.

The middleware <NUM> may provide, for example, a function that the application <NUM> needs in common, or may provide diverse functions to the application <NUM> through the API <NUM> to allow the application <NUM> to efficiently use limited system resources of the electronic device. According to an embodiment of the present disclosure, the middleware <NUM> (e.g., the middleware <NUM>) includes at least one of a runtime library <NUM>, an application manager <NUM>, a window manager <NUM>, a multimedia manager <NUM>, a resource manager <NUM>, a power manager <NUM>, a database manager <NUM>, a package manager <NUM>, a connectivity manager <NUM>, a notification manager <NUM>, a location manager <NUM>, a graphic manager <NUM>, or a security manager <NUM>.

The runtime library <NUM> may include, for example, a library module that is used by a compiler to add a new function through a programming language while the application <NUM> is being executed. The runtime library <NUM> may perform input/output management, memory management, or capacities about arithmetic functions.

The application manager <NUM> may manage, for example, a life cycle of at least one application of the application <NUM>. The window manager <NUM> may manage a graphic user interface (GUI) resource that is used in a screen. The multimedia manager <NUM> may identify a format necessary for playing diverse media files, and may perform encoding or decoding of media files by using a codec suitable for the format. The resource manager <NUM> may manage resources such as a storage space, memory, or source code of at least one application of the application <NUM>.

For example, the power manager <NUM> may operate with a basic input/output system (BIOS) and the like to manage capacity, temperature, or power of a battery, and may determine or provide power information for an operation of an electronic device by using the corresponding information thereof. The database manager <NUM> may generate, search for, or modify database that is to be used in at least one application of the application <NUM>. The package manager <NUM> may install or update an application that is distributed in the form of package file.

The connectivity manager <NUM> may manage, for example, wireless connection such as Wi-Fi or Bluetooth. The notification manager <NUM> may display or notify an event such as arrival message, appointment, or proximity notification in a mode that does not disturb a user. The location manager <NUM> may manage location information about an electronic device. The graphic manager <NUM> may manage a graphic effect that is provided to a user, or manage a user interface relevant thereto. The security manager <NUM> may provide a general security function necessary for system security, user authentication, and the like. According to an embodiment of the present disclosure, in the case where an electronic device <NUM> includes a telephony function, the middleware <NUM> may further include a telephony manager for managing a voice or video call function of the electronic device.

The middleware <NUM> may include a middleware module that combines diverse functions of the above-described elements. The middleware <NUM> may provide a module specialized to each OS type to provide differentiated functions. Additionally, the middleware <NUM> may dynamically remove a part of the preexisting elements or may add new elements thereto.

The API <NUM> may be, for example, a set of programming functions and may be provided with a configuration that is variable depending on an OS. For example, in the case where an OS is Android or iOS™, it may provide one API set per platform. In the case where an OS is Tizen™, it may provide two or more API sets per platform.

The application <NUM> includes, for example, one or more applications capable of providing functions for a home <NUM>, a dialer <NUM>, an SMS/MMS <NUM>, an instant message (IM) <NUM>, a browser <NUM>, a camera <NUM>, an alarm <NUM>, a contact <NUM>, a voice dial <NUM>, an e-mail <NUM>, a calendar <NUM>, a media player <NUM>, an album <NUM>, a timepiece <NUM>, and a payment <NUM> or for offering health care (e.g., measuring an exercise quantity, blood sugar level, and the like) or environment information (e.g., information of barometric pressure, humidity, temperature, and the like).

According to an embodiment of the present disclosure, the application <NUM> may include an information exchanging application to support information exchange between the electronic device <NUM> and the first electronic device <NUM> or the second electronic device <NUM>. The information exchanging application may include, for example, a notification relay application for transmitting specific information to an external electronic device, or a device management application for managing the external electronic device.

For example, the notification relay application may include a function of transmitting notification information, which arise from other applications (e.g., applications for SMS/MMS, e-mail, health care, or environmental information), to an external electronic device. Additionally, the information exchanging application may receive, for example, notification information from an external electronic device and provide the notification information to a user.

The device management application may manage (e.g., install, delete, or update), for example, at least one function (e.g., turn-on/turn-off of an external electronic device itself (or a part of elements) or adjustment of brightness (or resolution) of a display) of the external electronic device which communicates with the electronic device, an application running in the external electronic device, or a service (e.g., a call service, a message service, and the like) provided from the external electronic device.

According to an embodiment of the present disclosure, the application <NUM> may include an application (e.g., a health care application of a mobile medical device) that is assigned in accordance with an attribute of an external electronic device. According to an embodiment, the application <NUM> may include an application that is received from the first electronic device <NUM>, the second electronic device <NUM>, or the server <NUM>. The application <NUM> may include a preloaded application or a third party application that is downloadable from a server. The names of elements of the program module <NUM> may be modifiable depending on kinds of operating systems.

According to an embodiment of the present disclosure, at least a portion of the program module <NUM> may be implemented by software, firmware, hardware, or a combination of two or more thereof. At least a portion of the program module <NUM> may be implemented (e.g., executed), for example, by the processor <NUM>. At least a portion of the program module <NUM> may include, for example, modules, programs, routines, sets of instructions, processes, and the like for performing one or more functions.

The term "module" as used in the present disclosure may represent, for example, a unit including one or more combinations of hardware, software and firmware. The term "module" may be interchangeably used with the terms "unit", "logic", "logical block", "component" and "circuit". The "module" may be a minimum unit of an integrated component or may be a part thereof. The "module" may be a minimum unit for performing one or more functions or a part thereof. The "module" may be implemented mechanically or electronically. For example, the "module" may include at least one of an application-specific IC (ASIC) chip, a field-programmable gate array (FPGA), and a programmable-logic device for performing some operations, which are known or will be developed.

At least a part of an apparatus (e.g., modules or functions thereof) or a method (e.g., operations) according to an embodiment of the present disclosure may be, for example, implemented by instructions stored in a computer-readable storage media in the form of a program module. The instruction, when executed by a processor <NUM>, may cause the one or more processors to perform a function corresponding to the instruction. The computer-readable storage media, for example, may be the memory <NUM>.

A computer-readable recording medium may include a hard disk, a floppy disk, a magnetic media (e.g., a magnetic tape), an optical media (e.g., a compact disc read only memory (CD-ROM) and a digital versatile disc (DVD), a magneto-optical media (e.g., a floptical disk)), and hardware devices (e.g., a read only memory (ROM), a random access memory (RAM), or a flash memory). Also, a program instruction may include not only a mechanical code such as generated by a compiler but also a high-level language code executable on a computer using an interpreter. The above hardware unit may be configured to operate via one or more software modules for performing an operation according to an embodiment of the present disclosure, and vice versa.

A module or a program module according to an embodiment of the present disclosure may include at least one of the above elements, or a part of the above elements may be omitted, or additional other elements may be further included. Operations performed by a module, a program module, or other elements may be executed sequentially, in parallel, repeatedly, or in a heuristic method. In addition, some operations may be executed in different sequences or may be omitted. Alternatively, other operations may be added.

While the present disclosure has been shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as defined by the appended claims and their equivalents.

Claim 1:
A printed circuit board (<NUM>) comprising:
a first pattern (<NUM>) configured to be formed in a first layer (<NUM>), wherein the first pattern (<NUM>) is configured to comprise at least one of a ground or a power line;
a second pattern (<NUM>) configured to be formed in at least one second layer (<NUM>) under the first layer (<NUM>), wherein the second pattern (<NUM>) is configured to comprise at least one signal line;
a first signal pad (<NUM>) disposed on an outer layer of the printed circuit board (<NUM>);
a second signal pad (<NUM>) disposed on the outer layer of the printed circuit board (<NUM>);
a first signal via (<NUM>) configured to electrically connect the first signal pad (<NUM>) to the second pattern (<NUM>);
a second signal via (<NUM>) configured to electrically connect the second signal pad (<NUM>) to the second pattern (<NUM>); the printed circuit board (<NUM>) further comprising:
a recess (<NUM>) obtainable by removing a portion of at least the first layer (<NUM>), wherein the portion before removal was at least a portion of an area (<NUM>)
where a third via (<NUM>) was provided, the third via (<NUM>) being formed in at least the first layer (<NUM>) and configured to electrically connect the first pattern (<NUM>) to the second pattern (<NUM>); such that, upon removing the portion of at least the first layer (<NUM>) to obtain the recess (<NUM>), the first pattern (<NUM>) is electrically separated from the second pattern (<NUM>), thereby electrically separating the ground or the power line from the at least one signal line, while the first signal pad (<NUM>) and the second signal pad (<NUM>) remain electrically connected through the second pattern (<NUM>) after the recess (<NUM>) is formed.