Patent Description:
Systems on a chip may support multiple power domains. Different power domains may utilize different voltages to power components within the respective power domain. It may be desirable to allow a power domain to switch between an internal voltage source and an external voltage source.

Document <CIT> discloses a power management circuit that includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

Document <CIT> discloses a voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Doument <CIT> a chip that includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.

An embodiment herein is a method as claimed in claim <NUM>.

An embodiment herein is a system on a chip (SOC) as claimed in claim <NUM>.

An embodiment herein is a testing system as claimed in claim <NUM>.

Unless otherwise noted, features identified by the same number in different figures represent the same features.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

Systems on a chip (SOCs) may use different voltage supplies for different components that operate at different voltage levels. For example, a SOC may have a high voltage ("HV") power supply, a medium voltage supply, and a low voltage supply.

In some cases, low voltage supply may be used for components that are critical to the operation of a device. Accurate and comprehensive testing of the components during production may be desirable. This may also be true of components on high voltage supply, medium voltage supply or another voltage supply.

The low voltage supply may be received from internal power sources. For example, a medium-voltage supply may receive power from a high-voltage supply. Similarly, a low-voltage supply may receive a power supply from the medium-voltage supply (in the case of a switched mode power supply) or external high-voltage supply (in the case of a second and first voltage regulators). Although, the high voltage supply may be received from an external source the medium voltage and low voltage are still considered to have received an internal supply. For example, an external source may supply 5V. The medium voltage domain may internally receive <NUM> V supplied by one or more regulators powered by the high-voltage supply. And, a low-power domain may internally receive <NUM> V internally from one or more regulators some powered by the MV (medium-voltage) supply and some powered by HV (high-voltage) supply.

Some SOCs may also allow domains on the low voltage supply to be switchable: supplied from internal and external sources. In some cases, low-voltage regulators that are powered internally may be bypassed to make way for an external supply to be coupled with the low power domains on the low power supply. Low power voltage regulators may be turned ON and OFF in response to a bypass selection signal. For example, a "<NUM>" on the low-voltage bypass selection signal may trigger the shutdown of the low-voltage regulators. As will be appreciated, in various embodiments, a "<NUM>" may not trigger the shutdown of the low-voltage regulators. In some instances, voltage regulator may also be turned off by a voltage supply sequence. When a shutdown sequence is detected by the SOC, voltage regulators may be shutdown. For example, the SOC may be configured to shut down low voltage regulators when the SOC detects that low voltage supply is raised before a high-voltage supply and a medium voltage supply. This sequence indicates the availability of an external supply because it deviates from a typical startup sequence (where the high voltage is raised first which supplies the medium voltage, which, in turn, supplies a switched mode power supply providing low voltage. Low voltage regulators may be supplied from the high voltage supply. The shutdown sequence is controllable by an operator.

<FIG> depicts a SOC <NUM> bypassing low voltage regulators.

The SOC <NUM> may comprise a first power domain <NUM>, a second power domain <NUM>, and a third power domain <NUM>. Each of the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> may be on a low-voltage supply. The SOC <NUM> may also comprise other power domains or supplies (not depicted). In various embodiments, the SOC <NUM> may also comprise a test controller <NUM>.

The first power domain <NUM> may comprise an always ON domain. Once it is powered, it always remains ON. The first power domain <NUM> may comprise an ultralow power domain. The first power domain <NUM> may be on during a standby mode of the SOC <NUM>. The second power domain <NUM> may be OFF during a standby mode of the SOC <NUM>, but may be powered during other modes of the SOC <NUM>. The second power domain <NUM> may be powered during a low-power mode of the SOC. The third power domain <NUM> may comprise a RUN switchable domain. The third power domain <NUM> may be OFF during a low power mode of the SOC <NUM>. The third power domain <NUM> may be OFF during the standby mode. And, the third power domain may be switchably ON or OFF at other times. In various embodiments, the test controller may be part of the third power domain <NUM>. This may be advantageous to avoid taxing resources of the first power domain <NUM> and second power domain <NUM>.

The SOC <NUM> may comprise a power management unit <NUM>. The power management unit <NUM> may comprise a first voltage regulator <NUM> and a second voltage regulator <NUM>. The first voltage regulator <NUM> may comprise a linear voltage regulator. The second voltage regulator <NUM> may comprise a linear voltage regulator. The power management unit <NUM> may further comprise a switched mode power supply <NUM> ("SMPS").

In various embodiments, the first power domain <NUM> may be powered by the first voltage regulator <NUM> during standby modes of the SOC <NUM>. The first voltage regulator may have its loop closed within the power management unit <NUM>. A ballast for the first voltage regulator may be located within the power management unit <NUM>.

A second voltage regulator <NUM> may power the first power domain <NUM> when the SOC is in a low power mode or other modes of operation other than a standby mode when all RUN switches (<NUM>, <NUM>, <NUM>) are opened. The second voltage regulator <NUM> may have a ballast <NUM> located in a pad ring <NUM> of the SOC (note ballast is internal to the pad rings so the numeral "<NUM>" points to a location of the ballast <NUM> in the pad ring <NUM>). The second voltage regulator <NUM> may also power the second power domain <NUM> during low power modes or during boots. A first switch <NUM> may be used to couple the second power domain <NUM> and the first power domain <NUM> so the second voltage regulator <NUM> may power both. As will be appreciated, additional switches may also be used for coupling the first power domain <NUM> and the second power domain <NUM>. In various embodiments, the first voltage regulator <NUM> is only ON during standby modes.

The SMPS <NUM> may be configured to supply power to the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> when it is ON. The SOC <NUM> may comprise a RUN switch <NUM> to couple the second power domain <NUM> to the third power domain <NUM> so the SMPS can supply both with a voltage. In various embodiments, the SOC <NUM> may comprise additional switches for coupling the second power domain <NUM> to the third power domain <NUM>. For example, second and third RUN switches (RUN switch <NUM> and RUN switch <NUM>) may also be used. It should be appreciated that, in various embodiments, there may be more RUN switches. The RUN switches may be closed once the SMPS <NUM> is powered. And, when the first switch <NUM> is also closed, the SMPS may power the third power domain <NUM>, the second power domain <NUM> (through the RUN switches), and the first power domain (by the first switch <NUM>). The second voltage regulator <NUM> may be turned OFF when the SMPS powers the second power domain <NUM>, and the first power domain <NUM>.

In various embodiments, the first switch <NUM> (and any additional switches coupling the first power domain <NUM> and the second power domain <NUM>) and the RUN switch <NUM> (and any additional RUN switches) may be operated by the test controller <NUM>. In various embodiment, the first switch <NUM> (and any additional switches coupling the first power domain <NUM> and the second power domain <NUM>) and the RUN switch <NUM> (and any additional RUN switches) may be configured to be closed when there is no high voltage supply available to the SOC <NUM>. The first voltage regulator <NUM> and the second voltage regulator <NUM> may also be turned ON and OFF by the test controller <NUM>.

The pad ring <NUM> may comprise multiple power supply pads <NUM> in the third power domain <NUM> and multiple low voltage power supply pads in the first power domain <NUM>. The ballast <NUM>, in various embodiments may comprise a power supply pad <NUM> and a pad <NUM>. The power supply pad <NUM> may be coupled with a low voltage supply package pin <NUM>. The pad <NUM> may be coupled with a high voltage supply package pin <NUM>. In various embodiments, the first power domain <NUM> may comprise additional ballasts and additional pads. Additional pads may be coupled with the low voltage supply package pin <NUM> or the high voltage supply package pin <NUM>. The low voltage supply package pin <NUM> may be coupled to the power supply pad <NUM> though a power bar. Similarly, the high voltage supply package pin <NUM> may be coupled to pad <NUM> through the power bar.

The first power domain <NUM> may receive power from power supply pads <NUM> for the first power domain <NUM>. And, the third power domain <NUM> may receive power from power supply pads <NUM> for the third power domain <NUM>. The second power domain <NUM> receive power through the first power domain <NUM>, through the third power domain <NUM>, or through both the first power domain <NUM> and the third power domain <NUM> depending on the arrangement the first switch <NUM>, and the RUN switches. For example, when only the first switch <NUM> (or switches) is closed, the second power domain <NUM> may receive power through the first power domain <NUM>. When the RUN switches are closed the second power domain <NUM> may receive power from the third power domain <NUM>. And, when both the first switch <NUM> (or switches) and the RUN switches are closed, the second power domain <NUM> may receive power from both the first power domain <NUM> and the third power domain <NUM>.

In various embodiments, a ballast <NUM> for the SMPS <NUM> may be external to the SOC <NUM>. In this way, the SOC <NUM> may need to be paired an off-chip components to close the loop for the SMPS <NUM>. Off chip components may include a ballast <NUM>, inductor <NUM>, and capacitor <NUM>. When paired with the appropriate off-chip components, the SMPS <NUM> may provide a voltage supply at package pin <NUM> which in turn connected a power bar to all power supply pads <NUM> to power the third power domain <NUM>, and when the first switch <NUM> and RUN switches are closed, the first power domain <NUM> and the second power domain <NUM>. Package pin <NUM> maybe coupled to a power bar connection between the PACKAGE and DIE of the SOC <NUM>.

<FIG> depicts a first low voltage regulator, a second low voltage regulator, and a switched mode power supply of a system on a chip of an embodiment.

The first voltage regulator <NUM> may comprise an op amp <NUM>. The op amp may receive a reference voltage at a first input port 2002A. In various embodiments, the reference voltage may comprise <NUM> mV. However, it will be appreciated that the magnitude of the reference voltage received at the first input port 2002A may be different in various embodiments. The op amp <NUM> may also receive feedback at a second port 2002B. The op amp <NUM> may receive a voltage Vddhv at <NUM> when powered. Vddhv may be received from the high-voltage supply for the SOC <NUM>. The first voltage regulator <NUM> may also comprise a transistor <NUM>. The voltage at a node <NUM> of the voltage regulator may be supplied to power the first power domain <NUM>.

The second voltage regulator <NUM> may comprise an op amp <NUM>. The op amp may receive a reference voltage at a first input port 2006A. In various embodiments, the reference voltage may comprise <NUM> mV. However, it will be appreciated that the magnitude of the reference voltage received at the first input port 2006A may be different in various embodiments. The op amp <NUM> may also receive feedback at a second port 2006B. The op amp <NUM> may receive a voltage Vddhv at <NUM>. Vddhv may be received from the high voltage supply for the SOC <NUM>. The second voltage regulator <NUM> may also comprise ballast <NUM>. The ballast may be located in the pad ring <NUM> of the SOC. The first switch <NUM> may be opened and closed to pair the second voltage regulator <NUM> with the second power domain <NUM>. The voltage at node <NUM> of the voltage regulator may be supplied to power the second power domain <NUM>.

The SMPS <NUM> may be coupled with a driver <NUM> and a circuit <NUM> to protect the input/output from electrostatic discharge. The driver <NUM> may be part of the SMPS <NUM>. The SMPS <NUM> may comprise an input to receive a reference voltage at a first port 1012A. In various embodiments, the reference voltage may comprise <NUM> mV. In various embodiments, the reference voltage may be different. The SMPS <NUM> may be powered by from the medium voltage supply. The SMPS <NUM> may also receive feedback at a second port 1012B. As discussed with reference to <FIG>, the ballast <NUM>, inductor <NUM>, and capacitor <NUM> for closing the SMPS <NUM> loop may be located off chip. In various embodiments, the inductor may comprise <NUM>µH and the capacitor may comprise <NUM>µF. The size of these components may be different in various embodiments. The off-chip components may be needed to close the loop for the SMPS <NUM>.

The SMPS <NUM> may supply a voltage to the third power domain <NUM> at node <NUM>. A RUN switch <NUM> may also couple the SMPS <NUM> with the second power domain <NUM> when the RUN switch <NUM> is closed. Any additional run switches, such as RUN switch <NUM>, and RUN switch <NUM>, are also closed to couple the SMPS with the second power domain <NUM>. When the RUN switch is closed SMPS may provide power to the second power domain <NUM> at node <NUM>. When the first switch <NUM> is also closed, the SMPS may be coupled with the first power domain <NUM> to supply a voltage to the first power domain <NUM> at node <NUM>. Any additional first switches (also referred to as LP switches) are also closed.

Returning the <FIG>, the SOC <NUM> may further comprise a voltage detector circuit <NUM>. In various embodiments, the power management unit may <NUM> comprise the voltage detector circuit <NUM>. The voltage detector circuit <NUM> may be configured to detect when voltages provided by the first voltage regulator <NUM>, the second voltage regulator <NUM>, or the SMPS <NUM> exceed upper or lower limits. The limits may differ for the different regulators. Each of the first voltage regulator <NUM>, the second voltage regulator <NUM>, and the SMPS <NUM> may have their own target voltage range with their own upper and lower limits. For example, the upper limit for the SMPS regulator may be <NUM> V, the upper limit for the second voltage regulator may be <NUM> V, and the upper limit for the first voltage regulator may be <NUM> V. The lower limits for each of the regulators also vary from one regulator to other. If the upper limit for any of the regulator is exceeded, the voltage detector circuit <NUM> may trigger a reset. The same may be true if the voltage falls below the lower limit.

In various embodiments, the SOC <NUM> may comprise a minimum voltage detector, a low voltage detector, a high voltage detector and an upper voltage detector. The voltage detector circuit <NUM> may comprise the minimum voltage detector, the low voltage detector, the high voltage detector and the upper voltage detector.

<FIG> depicts an embodiment of the voltage detector circuit <NUM>.

The voltage detector circuit <NUM> may comprise a minimum voltage detector 1032A, a low voltage detector 1032B, a high voltage detector 1032C, and an upper voltage detector 1032D. The minimum voltage detector 1032A may comprise an input 1031A to receive a voltage level from the second voltage regulator <NUM>. The low voltage detector 1032B may comprise an input 1031B to receive a voltage level from the second voltage regulator <NUM>. The high voltage detector <NUM> C may comprise an input 1031C to receive a voltage level from the second voltage regulator <NUM>. The upper voltage detector 1032D may comprise an input 1031D to receive a voltage level from the second voltage regulator <NUM>.

The minimum voltage detector 1032A may comprise an output 1033A. The value of the output 1033A may depend on whether the voltage level of the second voltage regulator <NUM> falls above or below a minimum voltage threshold. The low voltage detector 1032B may comprise an output 1033B. The value of the output 1033B may depend on whether the voltage level of the second voltage regulator <NUM> falls above or below a low voltage threshold. The high voltage detector 1032C may comprise an output 1033C. The value of the output 1033C may depend on the whether the voltage level of the second voltage regulator <NUM> falls above or below a high voltage threshold. The upper voltage detector 1032D may comprise an output 1033D. The value of the output 1033D may depend on whether the voltage level of the second voltage regulator <NUM> falls above or below an upper voltage threshold.

The output 1033A, output 1033B, output 1033C, and output 1033D maybe coupled with a logic circuit (or circuits) that triggers action depending on the outputs. Action may include a reset if the upper voltage threshold is exceeded. In various embodiments, the voltage detector circuit <NUM> may comprise a minimum voltage detector that receives a voltage level from the first voltage regulator <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise a low voltage detector that receives a voltage level from the first voltage regulator <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise a high voltage detector that receives a voltage level from the first voltage regulator <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise an upper voltage detector that receives a voltage level from the first voltage regulator.

In various embodiments, the voltage detector circuit <NUM> may comprise a minimum voltage detector that receives a voltage level from the SMPS <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise a low voltage detector that receives a voltage level from the SMPS <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise a high voltage detector that receives a voltage level from the SMPS <NUM>. In various embodiments, the voltage detector circuit <NUM> may comprise an upper voltage detector that receives a voltage level from the SMPS <NUM>. These additional voltage detectors may also output data dependent on respective threshold levels to a logic circuit to take corrective actions. The voltage detectors may also be used to determine when to couple the power domains. For example, all RUN switches may be closed to couple the third power domain <NUM> with the second power domain <NUM> after the low voltage threshold for the SMPS <NUM> or (or external supply) crosses the respective low voltage threshold. After which, the second voltage regulator <NUM> may be turned off.

<FIG> depicts a known sequence to internally supply a low voltage supply for the first power domain <NUM>, the second power domain <NUM>, and a third power domain <NUM> on a SOC <NUM>.

At a first step <NUM>, the high voltage supply may be raised from an external voltage source. The external voltage supply may be provided by a tester coupled with the SOC. The supply sequence may then proceed along two parallel paths. On a first path at step <NUM>, the second regulator may start powering the first power domain <NUM>. At a step <NUM>, the first switch <NUM> (the low power or "LP" switch or switches) may be closed. This may couple the second power domain with first power domain <NUM> and provide a path for the second voltage regulator <NUM> to power the second power domain <NUM> at step <NUM>.

Along the second of the parallel paths, at step <NUM>, an internal capless regulator may begin to operate, and at a step <NUM> may provide a medium voltage ("MV") supply. This allows the SMPS <NUM> to begin to supply a voltage. And, at step <NUM>, the third power domain <NUM> may start powering.

The paths of the sequence converge at step <NUM>, when the RUN switch <NUM> is closed. Any additional switches, for example, RUN switch <NUM> and RUN switch <NUM>, that couple the third power domain <NUM> with the second power domain <NUM> are also closed at step <NUM>. At this point, the second voltage regulator <NUM> is switched OFF at step <NUM>. The switches and the second voltage regulator may be turned ON and OFF by a controller. And, at step <NUM>, the SMPS <NUM> powers the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM>.

Testing for a SOC <NUM> may be performed at different points during the production process. This may require powering up SOC components and running tests to determine performance. Electronic Wafer Sort ("EWS") tests may be performed on dies before they are assembled into packages. And, after package assembly, Final Testing ("FT") (Package Testing) may be performed on an assembled package. Tests may be performed with a tester. A tester may be coupled with pads or pins of the dies or packages to supply test voltages, currents, loads and measure the response of the SOC <NUM>. The SOC <NUM> may be tested over a range of different temperatures, voltages and other conditions.

The testing procedure may consume time and resources so efforts to test dies and packages in parallel are advantageous to promote efficiency, production pace, and reduce costs. The degree of parallelism that may be achieved may vary depending on the type of test being performed during wafer sort testing. And, likewise, it may be desirable to test multiple packages in parallel for Final Testing. The degree of parallelism achievable for Final Testing may also vary depending on the test being performed during Final Testing.

Reducing the number of pads of a die or pins of package that need to be coupled with a tester during the various tests may help increase the level parallelism achievable during the tests. For example a tester with <NUM> channels can test up to <NUM> devices simultaneously if tests are performed using only <NUM> pads or pins. If <NUM> couplings between a <NUM> tester and a device are needed to perform a test, the maximum parallelism for the test is reduced to <NUM> devices. Pins or pads on a device under test that are not connected to tester channels may be left floating or connected to GND or VDD at the tester.

For testing purposes, it also may be advantageous to supply the low voltage to a SOC <NUM> from an external source rather than internally. This may allow a test operator more control over the voltage level received, which can facilitate more accurate, and a wider range of testing.

In various embodiments, all the internal LV supply regulators (for example, second voltage regulator <NUM>, first voltage regulator <NUM>, and SMPS <NUM>) may be turned OFF by asserting a bypass signal. The bypass signal may be asserted by a pin when a SOC <NUM>. However, as discussed above, is may be desirable to leave pins unconnected to a tester to promote parallel testing. Additionally, not all embodiments of a SOC <NUM> may comprise a bypass selector. Further, a tester used for EWS testing may not include the off-chip components needed to complete the loop for the SMPS <NUM>. This can reduce costs associated with testing. However, it may render the SMPS <NUM> inoperable during EWS testing unless another voltage supply is provided. Other approaches for bypassing a voltage regulator on a SOC <NUM> are, thus, needed.

As discussed with reference to <FIG>, a SOC <NUM> may be configured to allow a single voltage source to power the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> through operation of the first switch <NUM> (and any additional LP switches) and the RUN switch <NUM> (and any additional RUN switches like RUN switch <NUM> and RUN switch <NUM>). For example, when the SMPS is operating, an external low power supply may also utilize the same pathways to power the other domains on the low power supply (the first power domain <NUM> and the second power domain <NUM>). However, it may be problematic to power the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> just from supply pads of the first power domain <NUM>. There may not be enough supply pads for the first power domain <NUM> to supply enough current for the entire device.

It also may be problematic to power the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> just from the third power domain <NUM>. Although, there may be enough supply pads for the third power domain <NUM> in the pad ring <NUM> to supply all the domains on the low voltage supply, the switches that open and close the pathways between the power domains may need the first power domain <NUM> to be powered to operate the switches so third power domain <NUM> can provide a voltage to each of the power domains on the low voltage supply. So, the first power domain <NUM>, may need to be powered from another source so the switches may be closed that allow the first power domain <NUM> to receive power from the third power domain <NUM>. Known methods for bypassing the voltage regulator for testing, thus, provide an external voltage supply through both the first power domain <NUM> and the third power domain <NUM>.

<FIG> shows a known system <NUM> to provide external power to a SOC during testing.

<FIG> depicts the first power domain <NUM>, the second power domain <NUM> and the third power domain <NUM> of a SOC <NUM>. The first power domain <NUM>, the second power domain <NUM> and the third power domain <NUM> may all be on a low-voltage supply. A device power source <NUM> may provide an external low voltage to the first power domain <NUM> at <NUM>. The first power domain <NUM> may be linked to the device power source <NUM> through power supply pads <NUM> on the pad ring <NUM> of the SOC <NUM>. Once the first power domain <NUM> is powered, the first switch <NUM> (or switches) is closed to link the first power domain <NUM> and the second power domain <NUM> to allow voltage to be supplied to the second power domain <NUM>. The RUN switch <NUM> (and any additional switches such as RUN switch <NUM> and RUN switch <NUM>) are also closed after the first power domain <NUM> is powered.

The device power source <NUM> may also be coupled to the third power domain <NUM> at <NUM>. This coupling may be accomplished by power supply pads <NUM> for the third power domain <NUM> in the pad ring <NUM>. The device power source <NUM> can supply a voltage to power the third power domain <NUM>.

The linking of the device power source <NUM> and the first power domain <NUM> at <NUM> allows the first power domain <NUM> to be powered so that the switches may be closed to couple the domains. And, the coupling between the third power domain <NUM> and the device power source <NUM> at <NUM> may provide enough pads to supply the all three domains from the external power source, the device power source <NUM>. After the switches are closed, the second power domain <NUM> is supplied through both the first power domain <NUM> from <NUM> pads (as first switch <NUM> and additional LP switches, if any, are closed) and through the third power domain <NUM> from <NUM> pads (as RUN switches <NUM>, <NUM>, <NUM> and additional RUN switches if any are closed).

However, providing an external low voltage supply through both the first power domain <NUM> and the third power domain <NUM> has limitations. For example, the aforementioned approach makes it not possible to perform closed loop trimming on the first voltage regulator <NUM> and the second voltage regulator <NUM> because you cannot check the voltage at the supply <NUM> as it is being supplied by the device power source <NUM>. This may be undesirable because open loop trimming is not as accurate as closed loop trimming. Also, load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM> is not possible when the device power source <NUM> provides the voltage supply to the first power domain <NUM> and the second power domain <NUM>. This is because you cannot couple a load at <NUM> because the voltage supply is coupled there. The providing an external low voltage supply through both the first power domain <NUM> and the third power domain <NUM> also limits current detection tests performed on the second voltage regulator <NUM>. The ability to perform power switch testing is also limited when first power domain <NUM> and second power domain are powered from the device power source <NUM> because there is no external load and no internal current sink. Likewise, a consumption test may not be performed on the of the first power domain <NUM> and the second power domain <NUM> together, and a consumption test may not be performed on the first power domain <NUM> by itself.

Coupling the first power domain <NUM> and the third power domain <NUM> with the device power source <NUM> also creates complications for Final Testing on a SOC <NUM> that is performed after the assembly.

<FIG> depicts a system <NUM> for performing a Final Test on a SOC coupled with a device power source.

For FT testing a tester setup <NUM> may have the off chip components to complete the loop for the SMPS <NUM>. The tester setup may receive input from the SOC <NUM> for a PMOS 1028A of the ballast <NUM> and for an NMOS 1028B of the ballast <NUM>. A tester setup <NUM> with the off chip components supplied by the high voltage supply (VDDHV), the SOC may operate using internal voltage supply.

However, the structure needs to be in place to provide both internal and external voltage supply. In known methods, a first relay <NUM> may disposed between the device power source <NUM>, tester setup <NUM> with off chip components, test equipment 503A and the third power domain <NUM>, and a second relay <NUM> may be disposed between the device power source <NUM>, test equipment 503B and the first power domain <NUM>. When the SOC is externally powered, the first relay <NUM> and the second relay <NUM> may be closed to couple the device power source <NUM> with the first power domain <NUM> at <NUM> and the third power domain <NUM> at <NUM>. When the low voltage supply for the first power domain <NUM>, the second power domain <NUM> and the third power domain is supplied by the SMPS <NUM>, the first relay <NUM> may be open to device power source <NUM> but closed to couple the tester setup <NUM> (including off chip components) and test equipment 503A with the third power domain <NUM> at <NUM>. The second relay may be open to the device power source <NUM> but closed to couple the test equipment 503B with the first power domain <NUM> at <NUM>. It would be advantageous to eliminate the one of the relays.

<FIG> depicts a sequence to bypass supply a voltage regulator on a system on a chip for testing of an embodiment at both EWS and FT.

At a step <NUM>, the high voltage supply may be raised from an external voltage source. A test mode pad or pin (pad at EWS [wafer test] and pin at FT [package test]) may be set to a state that indicates that the SOC <NUM> is in a production test. For example a TESTMODE signal may be set to "<NUM>" in some embodiments. It will be appreciated that a TESTMODE signal may be set to the opposite logic state to the same effect in different embodiments. The test mode pad or pin may be set by a testing operator or engineer. The external voltage supply may be provided by a tester coupled with the SOC <NUM>.

Like the sequence described with reference to <FIG>, the sequence may proceed along two parallel paths. On the first path (on the left side of <FIG>) the steps may be similar or identical to the corresponding steps in described with reference to <FIG>. At step <NUM>, the second regulator may start powering the first power domain <NUM>. At a step <NUM>, the first switch <NUM> (the low power or "LP" switch or switches) may be closed. This may couple the second power domain <NUM> with the second voltage regulator <NUM>, which may then begin to start powering the second power domain <NUM>. The second voltage regulator may be powered from the high voltage supply.

Along the second of the parallel paths, at step <NUM>, an internal capless regulator may begin to operate similar to a corresponding step for the sequence described with reference to <FIG>. A MV voltage supply will become available at step <NUM>. In contrast, to the sequence described with reference to <FIG>, however, at this point the SMPS <NUM> is not powering the third power domain <NUM> (for EWS testing). The off-chip components needed to close the loop of the SMPS <NUM> are not available from a tester during EWS testing. And, during FT testing of a sequence to bypass supply a voltage regulator, a first relay <NUM> is open to tester setup <NUM> with off chip components, which prevents the SMPS loop from closing. As a result, the third power domain <NUM> will not yet be powered by the SMPS <NUM>. Rather, the third power domain <NUM> is coupled with the device power source.

At a step <NUM>, the voltage of the external supply (for example, provided by a tester) that is coupled with the third power domain may be raised above second voltage regulator max (upper) voltage threshold. This may be beneficial so that when RUN switches (RUN switch <NUM>, RUN switch <NUM>, and RUN switch <NUM> and additional switches if any) are closed at <NUM> there is no current flow from second voltage regulator <NUM> to device power source <NUM>. But, since second voltage regulator <NUM> max threshold or upper limit may be within the upper voltage detector range (for example max threshold/upper limit of second voltage regulator may be <NUM>. 03v and upper voltage detector may trip anywhere between <NUM>. 026v and <NUM>. 154v) there is a possibility of device getting reset when upper voltage detector trips. However, a reset may be prevented because the test mode pad/pin <NUM> is asserted which masks the output <NUM> of the voltage detector to the reset logic <NUM>. For example, the TESTMODE signal <NUM> and output <NUM> from the voltage detector circuit <NUM> may ORed together. Thus, by asserting the TESTMODE signal <NUM>, a reset may be prevented even if output from the voltage detector circuit <NUM> is "<NUM>.

The paths of the sequence converge at step <NUM>. The SOC may detect that the voltage supply exceeds the second voltage regulator max (upper) threshold and close the RUN switch <NUM>. The voltage may be detected by a voltage detector circuit <NUM>. Any additional switches, for example, RUN switch <NUM> and RUN switch <NUM>, that couple the third power domain <NUM> with the second power domain <NUM> are also closed at step <NUM>. The first power domain <NUM> and the second power domain <NUM> do not need to be powered from the external supply to close the RUN switches because they are powered from the internal supply at this step. As a result, the first power domain <NUM> does not have to be coupled with the external supply. But, after the RUN switches are closed, the domains may be coupled providing pathways for the domains to receive the external voltage supply. At this time, the second voltage regulator <NUM> may be switched OFF at step <NUM>. With the RUN switches and first switch <NUM> closed, the external voltage supply powers the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM>, which may occur at step <NUM>. At a step <NUM>, the external voltage may be reduced below the second voltage regulator max threshold (for example below <NUM> V) to a target level. And, testing may then proceed.

The sequence for bypassing a voltage regulator described with reference to <FIG> allows a SOC to be externally powered through the third power domain <NUM> without coupling power supply pads of the first power domain <NUM> to the external voltage source.

<FIG> depicts a system <NUM> for performing an EWS test on a SOC of an embodiment.

The third power domain <NUM> of a SOC <NUM> may be coupled with a device power source <NUM> at <NUM>. For EWS, the coupling may be made at the power supply pads <NUM> for the third power domain <NUM>, which may be located in the pad ring <NUM> of the SOC <NUM>. As described with reference to <FIG>, the first power domain <NUM> need not also be coupled to the device power source <NUM>. Instead it may be coupled with test equipment <NUM>. The test equipment may be coupled with the first power domain at <NUM>. For EWS, the coupling may be made at power supply pad <NUM> of the first power domain <NUM>, which may be located in the pad ring <NUM>.

For EWS testing, coupling the test equipment to the first power domain <NUM>, rather than coupling the first power domain <NUM> to the device power source <NUM> allows closed loop trimming of the first voltage regulator <NUM> and the second voltage regulator <NUM>. It may also allow load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM>. And, power switch testing may also be allowed by coupling the test equipment to the first power domain <NUM>, rather than coupling the first power domain <NUM> to the device power source <NUM>. Further, consumption of the first power domain <NUM>, or the first power domain <NUM> and the second power domain <NUM> may by checked. Such a test may be checked for consumption on the HV supply.

In various embodiments, the test equipment may comprise Ultraflex Voltage and Current check/forcing equipment. As will be appreciated, test equipment may comprise other types of equipment in various embodiments. The test equipment <NUM> may be coupled with the first power domain <NUM> at node <NUM> in <FIG>. In various embodiments the test equipment may be connected with <NUM> mA current sink at power-up. The first power domain <NUM> may be connected to the test equipment <NUM> with 0ma current sink for all test modes where the first power domain <NUM> and the second power domain <NUM> will be supplied from the external supply such as scan, memory built in self tests ("MBIST") boundary scan, and various analog test modes. The first power domain <NUM> may be connected to the test equipment <NUM> to check voltage for closed loop trimming of the first voltage regulator <NUM> and closed loop trimming of the second voltage regulator <NUM>. During power switch testing, the test equipment <NUM> may be connected with an appropriate current sink. Likewise, for load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM>.

Coupling the first power domain <NUM> to the device power source <NUM> also may be advantageous for FT testing once a package has been assembled.

<FIG> depicts a system <NUM> for performing a FT test on a SOC of an embodiment. In <FIG>, the device power source <NUM> is coupled with the third power domain <NUM>. As a result, the system only comprises one relay, the first relay <NUM>. For FT testing, the coupling of the device power source <NUM> with the third power domain <NUM> may be accomplished through package pin <NUM>. The elimination of the second relay <NUM> from the system <NUM> offers efficiencies over systems for package testing where the external supply voltage is provided through a connection to the first power domain <NUM> and the third power domain <NUM>. This may result in further efficiencies for test equipment that may be used to test multiple SOCs in parallel because one relay may be eliminated for each SOC being tested. For example, if a tester is used to test <NUM> devices in parallel, <NUM> relays may be removed.

Raising the voltage level from the third power domain <NUM> rather than both the first power domain <NUM> and the third power domain <NUM> also allows, during FT testing, closed loop trimming of the first voltage regulator <NUM> and the second voltage regulator <NUM>, load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM>, power switch testing, and consumption testing of the first power domain <NUM> or the first power domain <NUM> and the second power domain <NUM>. Note, in various embodiments, that tests referenced in this paragraph may be performed in an external supply mode of a SOC or an internal supply mode of the SOC because off chip components needed to close the SMPS <NUM> loop may be provided by the tester setup <NUM>.

For package testing, the test equipment 503A and test equipment 503B may comprise Ultraflex Voltage and Current check/forcing equipment. As will be appreciated, test equipment may comprise other types of equipment in various embodiments. In various embodiments, the teste equipment is connected to <NUM> mA current sink at power up.

The test equipment 503A may be coupled with the third power domain <NUM> at node <NUM> in <FIG>. The test equipment 503B may be coupled with the first power domain <NUM> at node <NUM> in <FIG>. For FT testing, the coupling of the device power source <NUM> with the first power domain <NUM> may be accomplished through low voltage supply package pin <NUM>. In various embodiments the test equipment 503A and test equipment 503B may be connected with <NUM> ma current sink for test modes where the first power domain <NUM> and the second power domain <NUM> will be supplied from the external supply such as scan, memory built in self tests ("MBIST") boundary scan, and various analog test modes. The first power domain <NUM> may be connected to the test equipment 503B to check voltage for closed loop trimming of the first voltage regulator <NUM> and closed loop trimming of the second voltage regulator <NUM>. The third power domain <NUM> may be connected to the test equipment 503A to check voltage for closed loop trimming of the SMPS <NUM>. During power switch testing, the test equipment 503B may be connected with an appropriate current sink with first power domain <NUM> and the test equipment 503A may be connected with a <NUM> ma current sink to the third power domain <NUM>. Likewise, for load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM> and the test equipment 503A may be connected with a <NUM> mA current sink to the third power domain <NUM>. Both test equipment 503A and 503B may be used for current sink on the SMPS. During power switch testing, the test equipment 503B may be connected with an appropriate current sink. Likewise, for load regulation of the first voltage regulator <NUM> and the second voltage regulator <NUM>. And, consumption of the first power domain <NUM>, or the first power domain <NUM> and the second power domain <NUM> may by checked. Such a test may be checked for consumption on the HV supply.

To perform a trim on the second voltage regulator <NUM> of a SOC, the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> may all be powered from external supply, which may comprise device power source <NUM>, through power supply pads of the third power domain <NUM> at target voltage. The target voltage, in various embodiments, may comprise <NUM> V. The second voltage regulator <NUM> may be enabled by test controller <NUM>, which is a JTAG operation. To avoid current flow from the second voltage regulator <NUM> to the device power source <NUM>, the second voltage regulator <NUM> may be enabled at less than the target voltage (for example, less than <NUM> V). The RUN switch <NUM> (or switches) may be opened by the test controller <NUM>. The third power domain <NUM> will then be powered by the external supply, and trimming may be performed by applying different trim codes through the test controller <NUM>. After trim, the voltage supply for the second voltage regulator <NUM> may be restored to less than the target voltage and the RUN switch (or RUN switches) may be closed by test controller <NUM>. Load regulation may be performed in same way with appropriate current sink for the test equipment (<NUM> or 503B depending on whether test performed during EWS or FT testing). Consumption on the second power domain <NUM> may be tested by measuring the current on the HV supply that powers the second voltage regulator <NUM>.

To perform a trim on the first voltage regulator <NUM> of a SOC <NUM>, the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> may all be powered from external supply, which may comprise device power source <NUM>, through power supply pads of the third power domain <NUM>) at target voltage. The target voltage, in various embodiments, may comprise <NUM> V. The first voltage regulator <NUM> may be enabled by test controller <NUM>, which is a JTAG operation. To avoid current flow from the first voltage regulator <NUM> to the device power source <NUM>, the first voltage regulator <NUM> may be enabled at less than the target voltage (for example, less than <NUM> V). The first switch <NUM> (or switches) may be opened by the test controller <NUM>. The third power domain <NUM> and second power domain <NUM> will then be powered by the external supply, and trimming may be performed trim codes through the test controller <NUM>. After trim, the voltage supply for the first voltage regulator <NUM> may be restored to less than the target voltage and the first switch (or switches) may be closed by test controller <NUM>. Load regulation may be performed in same way with appropriate current sink for the test equipment (<NUM> or 503B depending on whether test performed during EWS or FT testing). Consumption on the first power domain <NUM> may be tested by measuring the current on the HV supply that powers the first voltage regulator <NUM>.

Current detector trim may be performed for a SOC <NUM> with the second voltage regulator <NUM> turned ON, RUN switch <NUM> (or switches) closed, and first switch <NUM> (or switches) open. The third power domain <NUM> and the second power domain <NUM> may, thus, be supplied from the external supply, which may comprise device power source <NUM>, through the power supply pads of the third power domain <NUM>. Current detector trim operations may then be performed on the closed loop of the second voltage regulator <NUM>.

For power switch testing, the first power domain <NUM>, the second power domain <NUM>, and the third power domain <NUM> may all be powered from external supply through power supply pads of the third power domain <NUM>. An external load (through test equipment) is coupled to the first power domain <NUM>. One of a plurality of RUN switches that couples the third power domain <NUM> with the second power domain <NUM> may be closed. And, one of a plurality of switches (for example <NUM>) that couples the first power domain <NUM> to the second power domain <NUM> may also be closed. The test controller <NUM> may be used to operate the switches. The voltage at the input and output of the closed power switch between the third power domain <NUM> and the second power domain <NUM> may then be checked. The voltage may be checked on a channel of the tester with a test controller <NUM> bit setting. Voltage may also be checked at the power switch closed between the first power domain <NUM> and the second power domain <NUM>. The voltage checked on a channel of the tester with a test controller <NUM> bit setting that is different from the bit setting used for the other voltage switch. After the test is complete, all switches coupling the first power domain <NUM> and the second power domain <NUM> may be closed, and all switches coupling the second power domain <NUM> to the third power domain <NUM> may be closed.

<FIG> depicts a flow chart for a method <NUM> of an embodiment.

In various embodiments, the method <NUM> may comprise at a step <NUM>, powering a first power domain of a system on a chip (SOC) using a voltage regulator of the SOC; at a step <NUM>, powering a second power domain of the SOC using the voltage regulator of the SOC; at a step <NUM>, coupling a third power domain of the SOC with an external voltage source; at a step <NUM>, raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator of the SOC; at a step <NUM>, coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; at a step <NUM>, turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and a step <NUM>, powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.

In various embodiments, the method <NUM> may further comprise, wherein a RUN switch couples the second power domain of the SOC to the third power domain of the SOC.

In various embodiments, the method <NUM> may further comprise, wherein the first power domain of the SOC is powered by the external voltage source through a coupling of the first power domain of the SOC and the second power domain of the SOC to the external voltage source by a first switch and through the coupling of the second power domain of the SOC to the third power domain of the SOC by the RUN switch.

In various embodiments, the method <NUM> may further comprise, wherein powering the second power domain of the SOC using the voltage regulator of the SOC comprises coupling the second power domain of the SOC to the voltage regulator by the first switch.

In various embodiments, the method <NUM> may further comprise, coupling the SOC to a high voltage power supply used to power the voltage regulator of the SOC while the voltage regulator of the SOC powers the first power domain of the SOC, the second power domain of the SOC, or both.

In various embodiments, the method <NUM> may further comprise, setting a test-mode pad or a test-mode pin.

In various embodiments, the method <NUM> may further comprise, wherein the threshold level triggers a reset of the SOC unless the test-mode pad or the test-mode pin is set.

In various embodiments, the method <NUM> may further comprise, performing a trim operation on the voltage regulator.

In various embodiments, the method <NUM> may further comprise, performing a load regulation operation for the voltage regulator.

<FIG> depicts an embodiment of the voltage detector circuit <NUM> with output masked by a TESTMODE signal.

An OR gate <NUM> may receive the output 1033D from the upper voltage detector 1032D. The OR gate may also receive TESTMODE signal <NUM>. The OR gate can thus mask the output of the upper voltage detector 1032D. The output 1102A of the OR gate may be coupled with reset logic <NUM>.

Claim 1:
A method for bypassing a voltage regulator on a system on a chip, SOC (<NUM>), the method comprising:
powering a first power domain (<NUM>) of the system on a chip, SOC (<NUM>) using the voltage regulator (<NUM>) of the SOC (<NUM>);
powering a second power domain (<NUM>) of the SOC (<NUM>) using the voltage regulator (<NUM>) of the SOC (<NUM>);
coupling a third power domain (<NUM>) of the SOC (<NUM>) with an external voltage source (<NUM>);
raising an external voltage supply from the external voltage source (<NUM>) above a threshold level of the voltage regulator (<NUM>) of the SOC (<NUM>);
coupling the first power domain (<NUM>) of the SOC (<NUM>) and the second power domain (<NUM>) of the SOC (<NUM>) to the external voltage source (<NUM>);
turning OFF the voltage regulator (<NUM>) of the SOC after coupling the first power domain (<NUM>) of the SOC (<NUM>) and the second power domain (<NUM>) of the SOC (<NUM>) to the external voltage source (<NUM>); and
powering the first power domain (<NUM>) of the SOC (<NUM>), the second power domain (<NUM>) of the SOC (<NUM>), and the third power domain (<NUM>) of the SOC (<NUM>) with the external voltage source (<NUM>), the external voltage source (<NUM>) bypassing the voltage regulator (<NUM>),
wherein a RUN switch (<NUM>) couples the second power domain (<NUM>) of the SOC (<NUM>) to the third power domain (<NUM>) of the SOC (<NUM>), and the first power domain (<NUM>) of the SOC (<NUM>) is powered by the external voltage source (<NUM>) through a coupling of the first power domain (<NUM>) of the SOC (<NUM>) to the second power domain (<NUM>) of the SOC (<NUM>) by a first switch (<NUM>) and through the coupling of the second power domain (<NUM>) of the SOC (<NUM>) to the third power domain (<NUM>) of the SOC (<NUM>) by the RUN switch (<NUM>).