Patent Description:
Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while an imaging device or camera may be obtained from a second manufacturer and a display controller may be obtained from a third manufacturer. The application processor, the imaging device, the display controller, or other types of devices may be interconnected using a standards-based or proprietary physical interface. In one example, an imaging device may be connected using the Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, a display controller may include an interface that conforms to the Display Serial Interface (DSI) standard specified by the Mobile Industry Processor Interface (MIPI) Alliance.

A multiphase three-wire (C-PHY) interface defined by the MIPI Alliance uses a trio of conductors to transmit information between devices. Each of the three wires may be in one of three signaling states during transmission of a symbol over the C-PHY interface. Clock information is encoded in a sequence of symbols transmitted on the C-PHY interface and a receiver generates a clock signal from transitions between consecutive symbols. The maximum speed of the C-PHY interface and the ability of a clock and data recovery (CDR) circuit to recover clock information may be limited by the maximum time variation related to transitions of signals transmitted on the different wires of the communication link, which can limit the data throughput provided by the C-PHY interface as demand for increased data throughput continue to increase.

Attention is drawn to document <CIT> which relates to a termination circuit. The termination device includes terminals configured to receive a corresponding signal; unit circuits respectively connected to the terminals, the unit circuits each including a unit resistor and a unit switch element connected to each other in series; common mode capacitors; first switch elements respectively connected between each of the unit circuits and a first corresponding common mode capacitor of common mode capacitors, each of the first switch elements being configured to turn on when the corresponding signal is received in a first mode; and second switch elements respectively connected between each of the unit circuits and a second corresponding common mode capacitor of the common mode capacitors, the second switch elements being configured to turn on when the corresponding signal is received in a second mode different from the first mode.

Further embodiments of the present invention are defined by the appended dependent claims. Certain aspects of this disclosure relate to systems, methods and apparatus that enable improved communication on a multi-wire and/or multiphase communication link by managing voltage levels of signals received from the communication link. A feedback circuit provides an injection current to a common node of a terminating network in order to control a common mode voltage associated with the communication link.

In an embodiment according to the invention receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

In a further embodiment according to the invention, a method for regulating a common mode voltage at a receiver includes providing a terminating network for a three-wire serial bus and configuring a feedback circuit. Each wire of the three-wire serial bus is coupled through a resistance to a common node of the terminating network. The feedback circuit includes a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

In some aspects, the three-wire serial bus is operated in accordance with a C-PHY protocol. The terminating network may include a capacitance configured to couple the common node to ground. In some aspects, the receiving apparatus includes a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus. The first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers. The first amplifier circuit and the second amplifier circuit may include tunable transistors configured to set a voltage level at the common node. The feedback circuit may be configured to regulate a voltage level at the common node based on amplitude of the injection current. The voltage level at the common node may be calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol. The voltage level at the common node may be calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

In certain aspects, the apparatus has a third amplifier configured with an automatic frequency equalization circuit. The third amplifier may include a plurality of N-type metal-oxide-semiconductor input transistors and a source degeneration circuit.

As used in this application, the terms "component," "module," "system" and the like are intended to include a computer-related entity, such as, but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various processor-readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal.

Certain aspects of the invention may be applicable to improving a C-PHY interface specified by the MIPI Alliance, which is often deployed to connect electronic devices that are subcomponents of a mobile apparatus such as a telephone, a mobile computing device, an appliance, automobile electronics, avionics systems, etc. Examples of a mobile apparatus include a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, etc.), a drone, a sensor, a vending machine, or any other similarly functioning device.

In various aspects of the disclosure, a data communication apparatus has a plurality of line drivers configured to couple the apparatus to a <NUM>-wire link, and a data encoder configured to encode at least <NUM> bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the <NUM>-wire link such that each pair of consecutively-transmitted symbols includes two different symbols. Each symbol defines signaling states of the <NUM>-wire link during an associated symbol transmission interval such that each wire of the <NUM>-wire link is in a different signaling state from the other wires of the <NUM>-wire link during the associated symbol transmission interval. Data may be encoded in a combination of phase and polarity. The apparatus may include a wire state encoder configured to receive a sequence of symbols from the data encoder, and provide control signals to the plurality of line drivers. The control signals cause each of the plurality of line drivers to drive one wire of the <NUM>-wire link to a signaling state defined by each symbol during a symbol transmission interval provided for each symbol in the sequence of symbols.

The C-PHY interface is a high-speed serial interface that can provide high data throughput over bandwidth-limited channels. The C-PHY interface may be deployed to connect application processors to peripherals, including display controllers and cameras. The C-PHY interface encodes data into symbols that are transmitted in a three-phase signal over a set of three wires, which may be referred to as a trio of wires, or simply as a trio. The three-phase signal is transmitted in a different phase on each wire of the trio. Each trio provides a lane on a communication link. A symbol interval may be defined as the interval of time in which a single symbol controls the signaling state of a trio. During each symbol interval in a conventional C-PHY interface, one wire is "undriven" or driven to a mid-level voltage state while the remaining two of the three wires are differentially driven such that one of the two differentially driven wires assumes a first voltage level and the other differentially driven wire assumes to a second voltage level different from the first voltage level. In some implementations, the third wire is undriven or floating such that it assumes a third voltage level that is at or near the mid-level voltage between the first and second voltage levels due to the action of terminations. In some implementations, the third wire is driven toward the mid-level voltage. In one example, the driven voltage levels may be +V and -V with the undriven voltage being <NUM>. In another example, the driven voltage levels may be +V and <NUM> with the undriven voltage being +V/<NUM>. Different symbols are transmitted in each consecutively transmitted pair of symbols, and different pairs of wires may be differentially driven in different symbol intervals. In C-PHY interfaces, clock information is encoded in the transitions of signaling state at symbol boundaries between consecutive symbol intervals.

<FIG> depicts an example of apparatus <NUM> that may employ C-PHY <NUM>-phase protocols to implement one or more communication links. The apparatus <NUM> may include a system on Chip (SoC), or a processing circuit <NUM> that has multiple circuits or devices <NUM>, <NUM> and/or <NUM>, which may be implemented in an application specific integrated circuit (ASIC). In one example, the apparatus <NUM> may operate as a communication device and the processing circuit <NUM> may include a processing device provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits or functions. The processing circuit <NUM> may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or other processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM>, the processor-readable storage <NUM> may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may provide one or more buses 118a, 118b, <NUM> that enable certain devices <NUM>, <NUM>, and/or <NUM> to communicate. In one example, the ASIC <NUM> may include a bus interface circuit <NUM> that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes IC devices <NUM> and <NUM> that can exchange data and control information through a communication link <NUM>. The communication link <NUM> may be used to connect a pair of IC devices <NUM> and <NUM> that are located in close proximity to one another, or that are physically located in different parts of the apparatus <NUM>. In one example, the communication link <NUM> may be provided on a chip carrier, substrate or circuit board that carries the IC devices <NUM> and <NUM>. In another example, a first IC device <NUM> may be located in a keypad section of a flip-phone while a second IC device <NUM> may be located in a display section of the flip-phone. In another example, a portion of the communication link <NUM> may include a cable or optical connection.

The communication link <NUM> may include multiple channels <NUM>, <NUM> and <NUM>. One or more channel <NUM> may be bidirectional, and may operate in half-duplex and/or full-duplex modes. One or more channel <NUM> and <NUM> may be unidirectional. The communication link <NUM> may be asymmetrical, providing higher bandwidth in one direction. In one example described herein, a first channel <NUM> may be referred to as a forward channel <NUM> while a second channel <NUM> may be referred to as a reverse channel <NUM>. The first IC device <NUM> may be designated as a host system or transmitter, while the second IC device <NUM> may be designated as a client system or receiver, even if both IC devices <NUM> and <NUM> are configured to transmit and receive on the channel <NUM>. In one example, the forward channel <NUM> may operate at a higher data rate when communicating data from a first IC device <NUM> to a second IC device <NUM>, while the reverse channel <NUM> may operate at a lower data rate when communicating data from the second IC device <NUM> to the first IC device <NUM>.

Each of the IC devices <NUM> and <NUM> may each include a processor <NUM>, <NUM> or other processing circuit, computing circuit or device. In one example, the first IC device <NUM> may perform core functions of the apparatus <NUM>, including establishing and maintaining wireless communication through a wireless transceiver <NUM> and an antenna <NUM>, while the second IC device <NUM> may support a user interface that manages or operates a display controller <NUM>, and may control operations of a camera or video input device using a camera controller <NUM>. Other features supported by one or more of the IC devices <NUM> and <NUM> may include a keyboard controller, a voice-recognition component, and other input or output devices. The display controller <NUM> may include circuits and software drivers that support displays such as a liquid crystal display (LCD) panel, touch-screen display, indicators and so on. The storage media <NUM> and <NUM> may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by respective processors <NUM> and <NUM>, and/or other components of the IC devices <NUM> and <NUM>. Communication between each processor <NUM>, <NUM> and its corresponding storage media <NUM> and <NUM> and other modules and circuits may be facilitated by one or more internal bus <NUM> and <NUM> and/or a channel <NUM>, <NUM> and/or <NUM> of the communication link <NUM>.

The reverse channel <NUM> may be operated in the same manner as the forward channel <NUM>. The forward channel <NUM> and the reverse channel <NUM> may be capable of transmitting at comparable speeds or at different speeds, where speed may be expressed as data transfer rate and/or clocking rates. The forward and reverse data rates may be substantially the same or may differ by orders of magnitude, depending on the application. In some applications, a single bidirectional channel <NUM> may support communication between the first IC device <NUM> and the second IC device <NUM>. The forward channel <NUM> and/or the reverse channel <NUM> may be configurable to operate in a bidirectional mode when, for example, the forward and reverse channels <NUM> and <NUM> share the same physical connections and operate in a half-duplex manner. In one example, the communication link <NUM> may be operated to communicate control, command and other information between the first IC device <NUM> and the second IC device <NUM> in accordance with an industry or other standard.

The communication link <NUM> of <FIG> may be implemented according to MIPI Alliance specifications for C-PHY and may provide a wired bus that includes a plurality of signal wires, where the number of the signal wires may be denoted as M wires. The M wires may be configured to carry N-phase encoded data in a high-speed digital interface, such as a mobile display digital interface (MDDI). The M wires may facilitate N-phase polarity encoding on one or more of the channels <NUM>, <NUM> and <NUM>. The physical layer drivers <NUM> and <NUM> may be configured or adapted to generate A-phase polarity encoded data for transmission on the communication link <NUM>. The use of N-phase polarity encoding provides high speed data transfer and may consume half or less of the power of other interfaces because fewer drivers are active in N-phase polarity encoded data links.

The physical layer drivers <NUM> and <NUM> can typically encode multiple bits per transition on the communication link <NUM> when configured for N-phase polarity encoding. In one example, <NUM>-phase, polarity encoding may be used to support a wide video graphics array (WVGA) <NUM> frames per second LCD driver IC without a frame buffer, delivering pixel data at <NUM> Mbps for display refresh.

<FIG> illustrates a C-PHY transmitter <NUM> that may be used to implement certain aspects of the communication link <NUM> depicted in <FIG>. For the purposes of this description, the C-PHY transmitter <NUM> may be assumed to support <NUM>-wire, <NUM>-phase encoding. The example of <NUM>-wire, <NUM>-phase encoding is selected solely for the purpose of simplifying descriptions of certain aspects of the invention. The principles and techniques disclosed for <NUM>-wire, <NUM>-phase encoding may be applicable to other configurations of M-wire, N-phase polarity encoding.

Signaling states defined for each of the <NUM> wires in a <NUM>-wire, <NUM>-phase polarity encoding serial bus may include an undriven or mid-level state, a positively driven state and a negatively driven state. The positively driven state and the negatively driven state may be obtained by providing a voltage differential between two of the signal wires 318a, 318b and/or 318c, and/or by driving a current through two of the signal wires 318a, 318b and/or 318c connected in series such that the current flows in different directions in the two signal wires 318a, 318b and/or 318c. The undriven state may be realized by placing an output of a driver of a signal wire 318a, 318b or 318c in a high-impedance mode. In some instances, a mid-level state may be obtained on a signal wire 318a, 318b or 318c by passively or actively causing a signal wire 318a, 318b or 318c to attain a voltage level that lies substantially halfway between positive and negative voltage levels provided on driven signal wires 318a, 318b and/or 318c. Typically, there is no significant current flow through an undriven or mid-level signal wire 318a, 318b or 318c. Signaling states defined for a <NUM>-wire, <NUM>-phase polarity encoding scheme may be denoted using the three voltage or current states (+<NUM>, -<NUM>, and <NUM>).

A C-PHY transmitter <NUM> may employ line drivers <NUM> to control the signaling state of signal wires 318a, 318b and 318c. The line drivers <NUM> may be implemented as unit-level current-mode or voltage-mode drivers. In one example, each line driver <NUM> may receive sets of two or more of signals 316a, 316b and 316c that determine the output state of corresponding signal wires 318a, 318b and 318c. In one example, the sets of two signals 316a, 316b and 316c may include a pull-up signal (PU signal) and a pull-down signal (PD signal) that, when high, activate pull-up and pull-down circuits that drive the signal wires 318a, 318b and 318c toward a higher level or lower level voltage, respectively. In this example, when both the PU signal and the PD signal are low, the signal wires 318a, 318b and 318c may be terminated to a mid-level voltage.

For each transmitted symbol interval in an AT-wire, N-phase polarity encoding scheme, at least one signal wire 318a, 318b or 318c is in the midlevel/undriven (<NUM>) voltage or current state, while the number of positively driven (+<NUM> voltage or current state) signal wires 318a, 318b or 318c is equal to the number of negatively driven (-<NUM> voltage or current state) signal wires 318a, 318b or 318c, such that the sum of current flowing to the receiver is always zero. For each symbol, the signaling state of at least one signal wire 318a, 318b or 318c is changed from the wire state transmitted in the preceding transmission interval.

In operation, a mapper <NUM> may receive and map <NUM>-bit data <NUM> to <NUM> symbols <NUM>. In the <NUM>-wire example, each of the <NUM> symbols <NUM> defines the states of the signal wires 318a, 318b and 318c for one symbol interval. The <NUM> symbols <NUM> may be serialized using parallel-to-serial converters <NUM> that provide a timed sequence of symbols <NUM> for each signal wire 318a, 318b and 318c. The sequence of symbols <NUM> is typically timed using a transmission clock. A <NUM>-wire, <NUM>-phase encoder <NUM> receives the sequence of <NUM> symbols <NUM> produced by the mapper one symbol at a time and computes the state of each signal wire 318a, 318b and 318c for each symbol interval. The <NUM>-wire, <NUM>-phase encoder <NUM> selects the states of the signal wires 318a, 318b and 318c based on the current input symbol <NUM> and the previous states of signal wires 318a, 318b and 318c.

The use of M-wire, N-phase encoding permits a number of bits to be encoded in a plurality of symbols where the bits per symbol is not an integer. In the example of a <NUM>-wire communication link, there are <NUM> available combinations of <NUM> wires, which may be driven simultaneously, and <NUM> possible combinations of polarity on the pair of wires that is driven, yielding <NUM> possible states. Since each transition occurs from a current state, <NUM> of the <NUM> states are available at every transition. The state of at least one wire is required to change at each transition. With <NUM> states, log<NUM>(<NUM>) ≅ <NUM> bits may be encoded per symbol. Accordingly, a mapper may accept a <NUM>-bit word and convert it to <NUM> symbols because <NUM> symbols carrying <NUM> bits per symbol can encode <NUM> bits. In other words, a combination of seven symbols that encode five states has <NUM><NUM> (<NUM>,<NUM>) permutations. Accordingly, the <NUM> symbols may be used to encode the <NUM><NUM> (<NUM>,<NUM>) permutations of <NUM> bits.

<FIG> includes an example of a timing diagram <NUM> for signals encoded using a three-phase modulation data-encoding scheme, which is based on the circular state diagram <NUM>. Information may be encoded in a sequence of signaling states where, for example, a wire or connector is in one of three phase states S<NUM>, S<NUM> and S<NUM> defined by the circular state diagram <NUM>. Each state may be separated from the other states by a <NUM>° phase shift. In one example, data may be encoded in the direction of rotation of phase states on the wire or connector. The phase states in a signal may rotate in clockwise direction <NUM> and <NUM>' or counterclockwise direction <NUM> and <NUM>'. In the clockwise direction <NUM> and <NUM>' for example, the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. In the counterclockwise direction <NUM> and <NUM>', the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. The three signal wires 318a, 318b and 318c carry different versions of the same signal, where the versions may be phase shifted by <NUM>° with respect to one another. Each signaling state may be represented as a different voltage level on a wire or connector and/or a direction of current flow through the wire or connector. During each of the sequence of signaling states in a <NUM>-wire system, each signal wire 318a, 318b and 318c is in a different signaling state than the other wires. When more than <NUM> signal wires 318a, 318b and 318c are used in a <NUM>-phase encoding system, two or more signal wires 318a, 318b and/or 318c can be in the same signaling state at each signaling interval, although each state is present on at least one signal wire 318a, 318b and/or 318c in every signaling interval.

Information may be encoded in the direction of rotation at each phase transition <NUM>, and the <NUM>-phase signal may change direction for each signaling state. Direction of rotation may be determined by considering which signal wires 318a, 318b and/or 318c are in the '<NUM>' state before and after a phase transition, because the undriven signal wire 318a, 318b and/or 318c changes at every signaling state in a rotating three-phase signal, regardless of the direction of rotation.

The encoding scheme may also encode information in the polarity <NUM> of the two signal wires 318a, 318b and/or 318c that are actively driven. At any time in a <NUM>-wire implementation, exactly two of the signal wires 318a, 318b, 318c are driven with currents in opposite directions and/or with a voltage differential. In one implementation, data may be encoded using two-bit values <NUM>, where one bit is encoded in the direction of phase transitions <NUM> and the second bit is encoded in the polarity <NUM> for the current state.

The timing diagram <NUM> illustrates an example of data encoding using both phase rotation direction and polarity. The curves <NUM>, <NUM> and <NUM> relate to signals carried on three signal wires 318a, 318b and 318c, respectively for multiple phase states. Initially, the phase transitions <NUM> are in a clockwise direction and the most significant bit is set to binary '<NUM>,' until the rotation of phase transitions <NUM> switches at a time <NUM> to a counterclockwise direction, as represented by a binary '<NUM>' of the most significant bit. The least significant bit reflects the polarity <NUM> of the signal in each state.

According to certain aspects disclosed herein, one bit of data may be encoded in the rotation, or phase change in a <NUM>-wire, <NUM>-phase encoding system, and an additional bit may be encoded in the polarity of the two driven wires. Additional information may be encoded in each transition of a <NUM>-wire, <NUM>-phase encoding system by allowing transition to any of the possible states from a current state. Given <NUM> rotational phases and two polarities for each phase, <NUM> states are available in a <NUM>-wire, <NUM>-phase encoding system. Accordingly, <NUM> states are available from any current state, and there may be log<NUM>(<NUM>) ≅ <NUM> bits encoded per symbol (transition), which allows the mapper <NUM> to accept a <NUM>-bit word and encode it in <NUM> symbols.

<FIG> illustrates certain aspects of a C-PHY receiver <NUM>. For the purposes of this description, the C-PHY receiver <NUM> may be assumed to support <NUM>-wire, <NUM>-phase decoding. Differential receivers 502a, 502b, 502c and a wire state decoder <NUM> are configured to provide a digital representation of the state of the three transmission lines (e.g., the signal wires 318a, 318b and 318c illustrated in <FIG>), with respect to one another, and to detect changes in the state of the three transmission lines compared to the state transmitted in the previous symbol period. Seven consecutive states are assembled by the serial-to-parallel convertors <NUM> to obtain a set of <NUM> symbols <NUM> to be processed by the demapper <NUM>. The demapper <NUM> produces <NUM> bits of data <NUM> that may be buffered in a first-in-first-out register (FIFO <NUM>) that provides an output <NUM> of the C-PHY receiver <NUM>.

The wire state decoder <NUM> may extract a sequence of symbols <NUM> from difference signals <NUM> derived from phase encoded signals received by the differential receivers 502a, 502b, 502c from the signal wires 318a, 318b and 318c. The symbols <NUM> are encoded as a combination of phase rotation and polarity as disclosed herein. The wire state decoder may include a CDR circuit <NUM> that extracts timing information from transitions on the signal wires 318a, 318b and 318c and, from the timing information, generates clock signals <NUM> that can be used to reliably capture wire states from the signal wires 318a, 318b and 318c. A transition occurs on least one of the signal wires 318a, 318b and 318c at each symbol boundary and the CDR circuit <NUM> may be configured to generate the clock signals <NUM> based on the occurrence of a transition or multiple transitions. Edges in one or more of the clock signals <NUM> may be delayed to allow time for all signal wires 318a, 318b and 318c to have stabilized and to thereby ensure that the current wire state is captured for decoding purposes. In one example, the one or more of the clock signals <NUM> may include a RDClk signal used to cause the FIFO <NUM> to read or capture data output by the demapper <NUM>. In some examples, other clock signals may be used by the C-PHY receiver <NUM>. For example, a write clock signal <NUM> (WRClk) may be received from a processing circuit to enable the FIFO <NUM> to asynchronously write out its contents to external processing devices or storage devices.

<FIG> is state diagram <NUM> illustrating the possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the three wires of a C-PHY bus, with the possible transitions illustrated from each state. In the example of a C-PHY interface configured for <NUM>-wire, <NUM>-phase encoding, <NUM> states and <NUM> state transitions are available. The possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> include and expand on the states shown in the circular state diagram <NUM> of <FIG>. As shown in the exemplar of a state element <NUM>, each signaling state <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> defines voltage signaling state for the signal wires 318a, 318b, 318c in each state, which are labeled A, B and C respectively. For example, in signaling state <NUM> (+x) wire A= +<NUM>, wire B = -<NUM> and wire C= <NUM>, yielding output of differential receiver 502a (A-B) = +<NUM>, differential receiver 502b (B-C) = -<NUM> and differential receiver 502c (C-A) = -<NUM>. Transition decisions taken by phase change detect circuits in a receiver are based on <NUM> possible levels produced by the differential receivers 502a, 502b, 502c, which include -<NUM>, -<NUM>, <NUM>, +<NUM> and +<NUM> voltage states.

The transitions in the state diagram <NUM> can be represented by a Flip, Rotate, Polarity symbol (e.g., the FRP symbol <NUM>) that has one of the three-bit binary values in the set: {<NUM>, <NUM>, <NUM>, <NUM>, <NUM>}. The Rotation bit <NUM> of the FRP symbol <NUM> indicates the direction of phase rotation associated with a transition to a next state. The Polarity bit <NUM> of the FRP symbol <NUM> is set to binary <NUM> when a transition to a next state involves a change in polarity. When the Flip bit <NUM> of the FRP symbol <NUM> is set to binary <NUM>, the Rotate and Polarity values may be ignored and/or zeroed. A flip represents a state transition that involves only a change in polarity. Accordingly, the phase of a <NUM>-phase signal is not considered to be rotating when a flip occurs and the polarity bit is redundant when a flip occurs. The FRP symbol <NUM> corresponds to wire state changes for each transition. The state diagram <NUM> may be separated into an inner circle <NUM> that includes the positive polarity signaling states <NUM>, <NUM>, <NUM> and an outer circle <NUM> that encompasses the negative polarity signaling states <NUM>, <NUM>, <NUM>.

<FIG> illustrates an example of a system <NUM> that has been adapted in accordance with certain aspects of this disclosure to support various encoding schemes that include <NUM>-phase encoding. A transmitter <NUM> is coupled to a receiver <NUM> by a <NUM>-wire link <NUM>. The transmitter <NUM> includes a data buffer <NUM> that receives and holds data to be communicated to the receiver <NUM>. The data may be received by the data buffer <NUM> from an application processor, peripheral, sensor, storage device, imaging device, display, or another source of data. In some examples, the data is stored as <NUM>-bit bytes, <NUM>-bit, <NUM>-bit or <NUM>-bit words, or words of another size. In some examples, each unit of data is stored with parity bits, and/or error-checking bits; for example, a parity bit may be provided for each byte, and/or parity bits or cyclic redundancy bits may be calculated for a block of data bytes or words and transmitted as additional bytes or words. In some instances, the data may be encapsulated with control information in packets or other data structures generated in accordance with one or more layers of a communication protocol. The data buffer <NUM> may be provided to a data encoder <NUM> in a size defined by the application. The data encoder <NUM> may include components configured to reformat data received from the data buffer <NUM>, map the reformatted data to one or more symbols, and serialize or otherwise sequence the symbols for transmission in accordance with a transmission clock.

In certain implementations, the data encoder <NUM> receives data from the data buffer <NUM> in units that are sized according to the encoding rate associated with the encoding scheme. In some examples, the data encoder <NUM> is configured to process data in <NUM>-bit bytes, <NUM>-bit words or <NUM>-bit words. In some examples, the data encoder <NUM> may include circuits that reorganize data supplied by the data buffer <NUM> to a set of <NUM>-bit bytes or <NUM>-bit words such that the unit size of data is constant regardless of the encoding scheme configured for the data encoder <NUM>. In one example, the data encoder <NUM> generates three multibit codes <NUM> representing the signaling state of each wire of the <NUM>-wire link <NUM> during each symbol transmission interval. The data encoder <NUM> provides the three multibit codes <NUM> to the wire state encoder <NUM>. The wire state encoder <NUM> generates control signals <NUM> that are provided to the line drivers <NUM>. Each of the line drivers <NUM> receives one or more of the control signals <NUM>, which it uses to define the signaling state of a corresponding wire of the <NUM>-wire link <NUM>.

In certain implementations, each of the three multibit codes <NUM> causes the wire state encoder <NUM> to generate a set of control signals <NUM> that configure switches in the line drivers <NUM>, where the state of the switches (e.g., closed or open) may select current or voltage levels to be provided to the wires of the <NUM>-wire link <NUM>. The state of the control signals <NUM> generated by the wire state encoder <NUM> responsive to the three multibit codes <NUM> may be configured based on the active encoding scheme or on the type of line driving circuit used to implement the line drivers <NUM>. Different types of line driving circuits may have different numbers of switches to be controlled to select a desired signaling state. Operations of the data encoder <NUM> and wire state encoder <NUM> may be performed in accordance with timing information indicated in a clock signal provided by a clock generator circuit.

The data encoder <NUM> operates to cause a stream of symbols to be transmitted on the <NUM>-wire link <NUM>, where each symbol is transmitted as a combination of signaling states of the <NUM> wires of the <NUM>-wire link <NUM>. The data encoder <NUM> may be configured for one or more modes of operation and for one or more encoding schemes.

In a first example, the transmitter <NUM> may be actively transmitting a stream of symbols over the <NUM>-wire link <NUM>, where the data encoder <NUM> has generated an Nth symbol (SN) and has added SN to the stream of symbols. The data encoder <NUM> may be configured for a first mode of operation in which each unit of data is encoded independently. In this first mode, the data encoder <NUM> uses the next unit of data to be encoded to select a next symbol for transmission. In one example, the data encoder <NUM> may generate an index used to select a next symbol (SN+<NUM>), where the index to SN+<NUM> is generated using the next four bits as an offset from the index to SN. The index is generated in a manner that prevents the selection of the same symbol as SN and SN+<NUM>. In one example, the index to SN+<NUM> may be calculated by addition or subtraction of the next four bits to the index to SN. In another example, the index to SN+<NUM> may be calculated using an algorithm that receives the next four bits and the index to SN as variables.

In a second example, the transmitter <NUM> may be actively transmitting a stream of symbols over the <NUM>-wire link <NUM>, where the data encoder <NUM> has generated an Nth symbol (SN) and has added SN to the stream of symbols. The data encoder <NUM> may be configured for a second mode of operation in which one or more bytes of data are encoded in a sequence of symbols {SN+<NUM>, SN+<NUM>,. In one example, the data encoder <NUM> uses the value of SN and one or more data bytes to index a table that maintains sequences of symbols. In another example, the data encoder <NUM> uses the one or more data bytes to index a table that maintains sets of offsets used to select a sequence of symbols based on the value of SN. The data encoder <NUM> produces the sequence of symbols by using the combined offsets to generate an index to a next symbol from the index used to generate the previously generated symbol. For example, the data encoder <NUM> may generate an index to the symbol table <NUM> for selecting SN+<NUM> based on the value of the first offset in the set of offsets and the index used to select SN. In some instances, the set of offsets may be obtained by indexing a table using the content of the one or more bytes as an index. In some instances, the set of offsets may be generated by breaking the units of data into one or more bytes or words.

In some implementations, the data encoder <NUM> may include or be coupled to parallel-to-serial convertors that convert symbols expressed as a block of multibit codes representative of the signaling states of the <NUM>-wire link <NUM> into a time-ordered sequence of symbols. A sequence of symbols {S<NUM>, S<NUM>,. SN, SN+<NUM>,. } may be transmitted in corresponding symbol transmission intervals {t<NUM>, t<NUM>,. tN, tN+<NUM>,. }, where the symbol transmission intervals are defined based on a clock signal provided by the clock generator <NUM>. The sequence of multibit codes <NUM> provided to the wire state encoder <NUM> include an Nth symbol (SN) that is used to generate signaling state of the <NUM>-wire link <NUM> during a corresponding Nth symbol transmission interval (tN) symbol, followed by an (N+<NUM>)th symbol (SN+<NUM>) that is used to generate signaling state of the <NUM>-wire link <NUM> during a corresponding (N+<NUM>)th symbol transmission interval (tN+<NUM>).

The receiver <NUM> includes differential receivers <NUM> that receive signals from the <NUM>-wire link <NUM>. The differential receivers <NUM> may be operable to discriminate between the N signaling states defined in an encoding scheme in accordance with certain aspects disclosed herein. The differential receivers <NUM> provide differential output signals to a wire state decoder <NUM> that is configured to extract a symbol from the differential output signals. The symbol is then provided to a data decoder <NUM> that may be configured to operate on individual symbols or on groups of symbols. The data decoder <NUM> may include components configured to deserialize received symbols and demap one or more symbols to obtain decoded data. The data decoder <NUM> may include components configured to reassemble and reformat the decoded data.

In one mode operation, the data decoder <NUM> may use a difference between received symbol (SN+<NUM>) and a preceding symbol (SN) to index a symbol table <NUM> to obtain <NUM> bits of decoded data. In another mode operation, the data decoder <NUM> may use a received sequence of symbols and a preceding symbol (SN) to index the symbol table <NUM> to obtain multiple bits of decoded data. Decoded data may be provided to a first-in, first-out register (FIFO <NUM>) or another buffer.

The wire state decoder <NUM> may include a clock and data recovery circuit (CDR <NUM>) that detects transitions in signaling state on one or more wires of the <NUM>-wire link <NUM> and generates a clock signal based on the timing of the transition. The clock signal may provide timing information used by the data decoder <NUM>, FIFO <NUM> and other components of the receiver <NUM>.

In a CSI interface defined by the MIPI Alliance and operated in accordance with C-PHY specifications a common mode voltage ranging from 95mV to 390mV is defined for the receiver. The C-PHY specifications provide a peak-to-peak voltage (Vpp) at the receiver that can range between 80mV to 290mV in order to account for shifts in ground voltage, termination mismatches and variations associated with sensor usage. Wide common mode direct current (DC) voltage shifts can result in incorrect detection and decoding of received signals. In some other serial interfaces, including interfaces based on a serializer/deserializer (SERDES), DC shifts may be mitigated through the use of alternating current (AC) coupling. Data patterns in transmission according to C-PHY protocols can include long <NUM>'s and <NUM>'s, which can cause drift in DC levels (DC wander), and that can prevent the use of AC coupling to adjust for receiver bias resulting from DC shift. In some conventional systems, the wide common mode voltage range may be accommodated through the use of level shifting. In a C-PHY interface, many level-shifting stages would be required to accommodate the wide common mode voltage range and a supply voltage of <NUM>. 2V may be required to provide a highly linear receiver that can handle a wide common mode voltage range. The resultant receiver would be expected to consume significant additional power and occupy greater space on IC.

<FIG> illustrates the effect of common mode voltage variations in an example of a C-PHY interface. The timing diagram shows three signals <NUM>, <NUM>, <NUM> transitioning between three defined signaling states <NUM>, <NUM>, <NUM>. The high signaling state <NUM> for high-speed operation has a voltage level identified as VIHHS, the low signaling state <NUM> for high-speed operation has a voltage level identified as VILHS, and the mid-level or common mode signaling state <NUM> for high-speed operation has a voltage level identified as VCPRX. In C-PHY specifications for CSI, the common mode voltage for a receiver defined for receiver ranges from 95mV < VCPRX < 390mV to account for any common mode voltage range shifting, termination mismatch or sensor variations. The eye diagram <NUM> shows an eye <NUM> that corresponds to the voltage and time zone in which the three signals <NUM>, <NUM>, <NUM> can be reliably sampled under all expected operating conditions. The eye <NUM> has a width <NUM> and a variable voltage range in which the three signals <NUM>, <NUM>, <NUM> can be sampled. The eye diagram <NUM> also shows the possible output states of differential receivers <NUM> (see <FIG>). A maximum positive difference state <NUM> has a largest voltage level identified as VDIF_RX_Max, a maximum negative difference state <NUM> has a largest voltage level identified as -VDIF_RX_Max, an intermediate positive difference state <NUM> has a largest voltage level identified as VIDTH_Max, an intermediate negative difference state <NUM> has a largest voltage level identified as -VIDTH_Max, The amplitude of the largest expected voltage swing at the beginning of a symbol interval <NUM> is and 2VDIF_RX_Max and the amplitude of the smallest expected voltage swing at the beginning of a symbol interval <NUM> is and 2VIDTH_Max.

Table <NUM>, below, illustrates certain examples of voltages and differential voltage swings (Vdiff1 <NUM> and Vdiff2 <NUM>) for different values of VCPRX.

In the first example shown in Table <NUM>, a large Vdiff2 <NUM> of 540mV is produced when the voltage difference between VIHHS and VCPRX and between VILHS and VCPRX is 135mV and when VCPRX is at the minimum 95mV level. In the second example shown in Table <NUM>, a small Vdiff1 <NUM> of 80mV is produced when the voltage difference between VIHHS and VCPRX and between VILHS and VCPRX is 40mV and when VCPRX is at the minimum 95mV level. In the third example shown in Table <NUM>, a large Vdiff2 <NUM> of 580mV is produced when the voltage difference between VIHHS and VCPRX and between VILHS and VCPRX is 145mV and when VCPRX is at the minimum 390mV level. In the fourth example shown in Table <NUM>, a small Vdiff1 <NUM> of 80mV is produced when the voltage difference between VIHHS and VCPRX and between VILHS and VCPRX is 40mV and when VCPRX is at the minimum 390mV level.

<FIG> shows two examples <NUM>, <NUM> illustrating variability of signaling states at a receiver coupled to a C-PHY communication link <NUM>. In the first example, <NUM>, the high signaling state <NUM> is represented by a voltage level (VTx_High) of <NUM>. 5mV, the low signaling state <NUM> is represented by a voltage level (VTx_Low) of <NUM>. 5mV and the mid-level signaling state corresponding to the common voltage level for the trio <NUM> is represented by a voltage level (VRx_Mid) of <NUM>. In order to support the signaling in these examples <NUM>, <NUM>, a receiver must be capable of handling a common mode voltage that varies by 155mV. In conventional systems, the receivers often use level shifting to accommodate the wide common mode requirement of C-PHY interfaces.

The transmitter common mode voltage (VCPTX) may be calculated as: <MAT>.

The transmitter common mode voltage and receiver common mode voltage (VCPRX) are generally different. The receiver common mode voltage (VCPRX_HL, VCPRX_HM, VCPRX_HM) may be calculated for each pair of wires in a trio <NUM> as follows: <MAT> <MAT> <MAT>.

In the examples illustrated in Table <NUM>, the maximum receiver common mode voltage (VCPRX_Max) is 390mV.

<FIG> illustrates certain aspects of a C-PHY interface <NUM> in which differential receivers <NUM>, <NUM>, <NUM> are coupled to different pairs of wires in a C-PHY link <NUM>. The differential receivers <NUM>, <NUM>, <NUM> include level-shifting amplifiers <NUM> that can be used to accommodate the wide common mode requirement of the C-PHY interface <NUM>. Each level-shifting amplifier <NUM> includes a current source <NUM>. In one example, the current source <NUM> is implemented using a current mirror that is controlled or configured to ensure that the current mirror remains in saturation for all common mode variations. Furthermore, the transistors <NUM>, <NUM> in the level-shifting amplifiers <NUM> are thick-oxide devices in order to accommodate the variabilities in received voltage. However, such thick gate based level shifting device can occupy a die area of <NUM><NUM> or more on an IC and may require an operating voltage of <NUM>. 2V, with a total current requirement of <NUM> A for three C-PHY trios. Version <NUM> of the C-PHY specifications support transmission of <NUM> giga symbols per second (Gsys) for a data rate of <NUM> gigabits per second (Gbps) and, at such signaling rates, the current consumption of a single level shifter operating at <NUM>. 2V may be estimated at approximately <NUM>. 2mA and the level shifter can occupy <NUM><NUM> area of an IC.

Certain aspects of this disclosure relate to the use of a common mode servo loop that can automatically accommodate variations in common mode voltage at a receiver coupled to a serial bus operated in accordance with C-PHY specifications and protocols. The servo loop is self-regulated and configured to monitor the virtual ground or common mode of the trio and thereby ascertain the DC level of received C-PHY signals and to respond immediately to changes in the DC level. The servo loop uses replica receiving circuits and can provide substantial power savings and occupies substantially less area of an IC than thick gate based level shifting stages.

<FIG> illustrates certain aspects of a C-PHY interface <NUM> that includes a servo loop <NUM> configured to regulate DC levels in accordance with the present invention. The C-PHY interface <NUM> is configured to couple a receiving device to a trio of wires <NUM>, <NUM>, <NUM> of a C-PHY link <NUM>. Each of the wires <NUM>, <NUM>, <NUM> is coupled through a resistance to common node <NUM> in a terminating network <NUM>. The common node <NUM> is decoupled from a ground reference <NUM> for the C-PHY link <NUM> through a capacitance <NUM>. Differential receivers <NUM>, <NUM>, <NUM> are coupled to different pairs of the wires <NUM>, <NUM>, <NUM>. The common node <NUM> serves as virtual ground for the differential receivers <NUM>, <NUM>, <NUM> and signals received from the wires <NUM>, <NUM>, <NUM> of the C-PHY link <NUM>.

Each of the differential receivers <NUM>, <NUM>, <NUM> includes an automatic frequency equalization amplifier (the AFE amplifier <NUM>). In the illustrated example, the AFE amplifier <NUM> includes N-type metal-oxide-semiconductor (NMOS) input transistors <NUM>, <NUM> and a source degeneration circuit <NUM> configured to provide automatic frequency equalization. The source degeneration circuit <NUM> includes a source degeneration resistance coupled in parallel with a source degeneration capacitance between the sources of the input transistors <NUM>, <NUM>. The receiving stages of the amplifier <NUM> include a current source <NUM> that may be specified to operate when a voltage (VDAC <NUM>) across the current source <NUM> has a minimum level. The amplifier <NUM> may be configured to provide sufficient headroom for the current source <NUM>. In one example, the headroom is sufficient to accommodate a VDAC of 150mV.

The C-PHY interface <NUM> includes a servo loop <NUM> configured to regulate common mode voltage for the trio of the C-PHY link <NUM>. The servo loop <NUM> operates as a feedback circuit and includes a replica amplifier <NUM>, an error amplifier <NUM> and an A/B amplifier <NUM> and is configured to provide an injection current <NUM> through the common node <NUM>. The replica amplifier <NUM> is constructed from the same combination of active devices used to provide amplifiers that receive signals from the trio of the C-PHY link <NUM> in the differential receivers <NUM>, <NUM>, <NUM>. The replica amplifier <NUM> receives an input signal <NUM> representative of the voltage (VCom) at the common node <NUM>. The replica amplifier <NUM> includes a current source and two transistors <NUM>, <NUM>. The bias of at least one of the two transistors <NUM>, <NUM> can be adjusted, tuned or calibrated to obtain a desired response to the input signal <NUM> representative of the voltage (VCom) at a common node <NUM>. The output (VCS_REF <NUM>) replica amplifier <NUM> is provided as the input signal to the error amplifier <NUM>. The error amplifier <NUM> may be implemented using a comparator or an operational amplifier. The error amplifier <NUM> generates a differential feedback signal <NUM> based on the difference between VCS_REF <NUM> and VDAC <NUM>. The differential feedback signal <NUM> is provided to the transistors <NUM>, <NUM> of the A/B amplifier <NUM>. The A/B amplifier <NUM> generates an injection current <NUM> that is injected through the common node <NUM> that can stabilize and/or prevent drift in the voltage at the common node <NUM>. The transistors <NUM>, <NUM> of the A/B amplifier <NUM> may be tuned by controlling, adjusting or calibrating the bias provided to at least one of the transistors <NUM>, <NUM>.

The common node <NUM> serves as a virtual ground between the trio and as the adjustment point for the servo loop <NUM>. The servo loop <NUM> configures the injection current <NUM> to create the necessary headroom for current source <NUM> in the replica amplifier <NUM>. In some examples, the current source <NUM> is specified to operate with a nominal 150mV for all operating conditions in the replica amplifier <NUM>. The injection current <NUM> modifies the voltage levels of the signals received from the trio of wires <NUM>, <NUM>, <NUM> of the C-PHY link <NUM>.

In some examples, the servo loop <NUM> can reduce common mode noise and improve power supply ripple rejection. The servo loop <NUM> controls the voltage at the common node <NUM> based on a reference signal (VCS_REF <NUM>). The voltage of the VCS_REF <NUM> may be adjusted through a tuning transistor <NUM> (Mtune) and by controlling VDAC <NUM>.

The examples shown in <FIG> and other examples provided elsewhere in this disclosure describe receivers or components of receivers that employ NMOS technology for implementing certain transistors, including the input transistors <NUM>, <NUM>. The concepts disclosed herein are not limited to NMOS technology and can be readily implemented using P-type metal-oxide-semiconductor (PMOS) technology, complementary metal-oxide-semiconductor (CMOS) technology or another type of technology. For example, certain amplifiers, current sources, comparators and logic circuits can be implemented using NMOS transistors, PMOS, transistors, CMOS transistors or some combination of NMOS transistors, PMOS and/or transistors CMOS transistors.

<FIG> illustrates a first example of the effect of a servo loop configured to regulate DC levels in a C-PHY interface according to certain aspects of this disclosure. In one example, the servo loop <NUM> illustrated in <FIG> is used to inject current through a common node <NUM> that serves as virtual ground. <FIG> includes a graphical representation <NUM> of signaling over the three channels 1222a-1222c or 1242a-1242c in a communication link operated in accordance with C-PHY specifications and protocols. The channels 1222a-1222c or 1242a-1242c may be provided by wires, printed circuit board interconnects, traces in metallization layers of an IC or other types of conductors. At a point in time <NUM> a change occurs in the common mode voltage level of the three wires.

A first current flow diagram <NUM> shows current and voltage levels in a receiver circuit that operates without a servo loop. The transmitter drives signals over the three channels 1222a, 1222b, 1222c with a peak voltage level <NUM> (VTx) of 800mV. At the receiving end, the signals received from the three channels 1222a, 1222b, 1222c have a 400mV peak-to-peak voltage <NUM>. In the illustrated example, the common mode voltage level of the three channels 1222a, 1222b, 1222c drops from 400mV to 300mV. A first channel 1222a carries a first current <NUM> from the transmitter at an amplitude of 4mA, a second channel 1222b carries no or negligible current <NUM> from the transmitter, and a third channel 1222c carries a second current <NUM> from the receiver at an amplitude of 4mA.

In the illustrated example, the transmitter is a sensor that has line drivers that nominally drive the channels 1222a, 1222b, 1222c between <NUM> and 800mV. The mid-level voltage at the transmitter is 400mV and the nominal voltage at the common node <NUM> that serves as virtual ground is also 400mV. Termination mismatches, variations associated with sensor usage or other factors affecting shifts in ground voltage may produce an event that causes the change in the common mode voltage at time <NUM>. As depicted, the change is a step change. In other examples, the change may occur more gradually. In conventional systems, level shifters may be required to accommodate the change in the common mode voltage.

A second current flow diagram <NUM> shows current and voltage levels in a receiver circuit that includes a servo loop to automatically regulate common mode voltage. In the illustrated example, the servo loop may be configured to maintain a virtual ground voltage level of 300mV. Here, the common node <NUM> serves as virtual ground. The transmitter drives signals over the three channels 1242a, 1242b, 1242c with a peak voltage level <NUM> (VTx) of 800mV. The servo loop is configured to sink a 6mA injection current <NUM>, resulting in a net current of 6mA flowing through the first channel 1242a from the transmitter, a net current of 2mA flowing through the second channel 1242b from the transmitter, and a net current of 2mA flowing through third channel 1242c to the transmitter.

The servo loop is configured to adjust the injection current <NUM> to accommodate or mitigate for termination mismatches, variations associated with sensor usage or other factors affecting shifts in ground voltage may produce an event that causes the change in the common mode voltage at time <NUM>. As depicted, the change is a step change. In other examples, the change may occur more gradually.

<FIG> illustrates a second example of the effect of a servo loop configured to regulate DC levels in a C-PHY interface according to certain aspects of this disclosure. In some instances, the servo loop <NUM> illustrated in <FIG> is used to inject current through
a common node <NUM> that serves as virtual ground. <FIG> includes a graphical representation <NUM> of signaling over the three channels 1322a-1322c or 1342a-1342c in a communication link operated in accordance with C-PHY specifications and protocols. The channels 1322a-1322c or 1342a-1342c may be provided by wires, printed circuit board interconnects, traces in metallization layers of an IC or other types of conductors. At a point in time <NUM> a change occurs in the common mode voltage level of the three wires.

A first current flow diagram <NUM> shows current and voltage levels in a receiver circuit that operates without a servo loop. The transmitter drives signals over the three channels 1322a, 1322b, 1322c with a peak voltage level <NUM> (VTx) of 300mV. At the receiving end, the signals received from the three channels 1322a, 1322b, 1322c have a 150mV peak-to-peak voltage <NUM>. In the illustrated example, the common mode voltage level of the three channels 1322a, 1322b, 1322c increases from 150mV to 200mV. A first channel 1322a carries a first current <NUM> from the transmitter at an amplitude of <NUM>. 5mA, a second channel 1322b carries no or negligible current <NUM> from the transmitter, and a third channel 1322c carries a second current <NUM> from the receiver at an amplitude of <NUM>.

In the illustrated example, the transmitter is a sensor that has line drivers that nominally drive the channels 1322a, 1322b, 1322c between <NUM> and 300mV. The mid-level voltage at the transmitter is 150mV and the nominal voltage at the common node <NUM> that serves as virtual ground is also 150mV. Termination mismatches, variations associated with sensor usage or other factors affecting shifts in ground voltage may produce an event that causes the change in the common mode voltage at time <NUM>. As depicted, the change is a step change. In other examples, the change may occur more gradually. In conventional systems, level shifters may be required to accommodate the change common mode voltage.

A second current flow diagram <NUM> shows current and voltage levels in a receiver circuit that includes a servo loop to automatically regulate common mode voltage. In the illustrated example, the servo loop may be configured to maintain a virtual ground voltage level of 200mV. Here, the common node <NUM> serves as virtual ground. The transmitter drives signals over the three channels 1342a, 1342b, 1342c with a peak voltage level <NUM> (VTx) of 300mV. The servo loop is configured to source a 3mA injection current <NUM>, resulting in a net current <NUM> of <NUM>. 5mA flowing through the first channel 1342a from the transmitter, a net current <NUM> of 1mA flowing through the second channel 1342b to the transmitter, and a net current <NUM> of <NUM>. 5mA flowing through third channel 1342c to the transmitter.

According to certain aspects of the disclosure, the voltage of the line driver output at the transmitter need not change when the voltage at the common node <NUM>, <NUM> is less than half the maximum voltage of the line driver output. In some instances, a servo loop may be configured to increase the voltage at the common node <NUM>, <NUM> to more than half the maximum voltage of the line driver output and the voltage levels of line driver output may be altered slightly. For example, in the example illustrated in the second current flow diagram <NUM>, the voltage range of the line driver output may be modified by up to <NUM>% in order to maintain the symmetry of termination between the transmitter and receiver.

In some implementations, the voltage at the common node <NUM>, <NUM> may be configured during calibration of the receiver. C-PHY protocols provide for preambles that can be used for such calibration. The voltage measured at the common node <NUM>, <NUM> may be incrementally increased until the voltage measured at the common node <NUM>, <NUM> is equal to or greater than half the maximum voltage of the line driver output. The injection current may then be reduced by two increments. In one example, the voltage at the common node <NUM>, <NUM> may be adjusted by modifying the voltage (VDAC) across the current source <NUM>.

In some implementations, the use of servo loop can accommodate the wide common mode requirement of the C-PHY interface using less power and area on an IC than conventional level-shifting techniques. In one example, a conventional receiver may require <NUM><NUM> × <NUM> thick-gate level shifters for three trios, and may consume between <NUM> and <NUM>. 2mA for each of <NUM> channels. The use of a servo loop in accordance with certain aspects of this disclosure can limit the area used on an IC to <NUM><NUM> for each of <NUM> trios and may reduce current usage to less than 10mA. The servo loop can eliminate the need for a thick gate based level shifter and can support higher bandwidths.

<FIG> is a conceptual diagram <NUM> illustrating an example of a hardware implementation for an apparatus employing a processing circuit <NUM> that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit <NUM>. The processing circuit <NUM> may include certain devices, circuits, and/or logic that support the various encoding schemes disclosed herein. The processing circuit <NUM> may include, configure and/or manage one or more of the circuits illustrated in FIGs. <NUM> and <NUM>-<NUM>. In one example, the processing circuit <NUM> may include some combination of circuitry and modules that facilitates the sampling and decoding of symbols that are encoded using C-PHY encoding, and which define three or more voltage levels on the wires of a serial bus. In another example, the processing circuit <NUM> may include some combination of circuitry and modules that facilitates the generation of clock signals that can control efficient capture of C-PHY encoded symbols in accordance with certain aspects disclosed herein. The processing circuit <NUM> may include a state machine or another type of processing device that manages encoding and/or decoding processes as disclosed herein.

The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and a processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers <NUM>. A transceiver <NUM> may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver <NUM>. Each transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

A processor <NUM> may be responsible for managing the bus <NUM> and for general processing that may include the execution of software stored in a processor-readable medium that may include the processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may be used for storing data that is manipulated by the processor <NUM> when executing software, and the software may be configured to implement any one of the methods disclosed herein.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the processor-readable storage medium <NUM> or in another, external processor-readable medium. The processor-readable storage medium <NUM> may include a non-transitory processor-readable medium. A non-transitory processor-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), RAM, a ROM, a PROM, an erasable PROM (EPROM), an EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The processor-readable storage medium <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Processor-readable storage medium <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The processor-readable storage medium <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a processor-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The processor-readable storage medium <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM>, and may manage access to external devices such as the transceiver <NUM>, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to the transceiver <NUM>, the user interface <NUM>, and so on.

<FIG> is a flow chart <NUM> of a method for regulating a common mode voltage at a receiver coupled to a multi-wire communication link according to the present invention. The communication link has three wires and data may be encoded in phase state and polarity of a signal transmitted in different phases on each of the three wires. At block <NUM>, a terminating network is provided for a three-wire serial bus. Each wire of the three-wire serial bus is coupled through a resistance to a common node of the terminating network. At block <NUM>, a feedback circuit is configured. The feedback circuit includes a first amplifier circuit that has an input coupled to the common node. The feedback circuit includes a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input. The feedback circuit includes a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node. The three-wire serial bus may be operated in accordance with a C-PHY protocol. The terminating network may include a capacitance configured to couple the common node to ground. In one example, each of a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus includes an amplifier circuit corresponding to the first amplifier circuit.

In certain examples, the first amplifier circuit and the second amplifier circuit include tunable transistors configured to set a voltage level at the common node. The feedback circuit may be configured to regulate a voltage level at the common node based on amplitude of the injection current. The voltage level at the common node may be calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol. The voltage level at the common node may be calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

In one example, the method includes equalizing inputs to a differential receiver.

According to the invention, an apparatus has means for terminating a three-wire serial bus and means for regulating a common mode voltage level. The means for terminating a three-wire serial bus is configured to couple each wire of the three-wire serial bus through a resistance to a common node. The means for terminating the three-wire serial bus may include a capacitance configured to couple the common node to ground. The three-wire serial bus may be operated in accordance with a C-PHY protocol.

The means for regulating a common mode voltage level includes a feedback circuit having a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

The apparatus may include means for decoding data from the three-wire serial bus. The means for decoding data may include a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus. The first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers. The first amplifier circuit and the second amplifier circuit may include tunable transistors configured to set a voltage level at the common node. The feedback circuit is configured to regulate the voltage level at the common node based on amplitude of the injection current. The voltage level at the common node may be calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol. The voltage level at the common node may be calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

In certain examples, the apparatus includes means for equalizing inputs to a differential receiver. The means for equalizing inputs to the differential receiver may include a plurality of NMOS input transistors; and a source degeneration circuit.

According to the invention, a receiving apparatus has a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus is coupled through a resistance to a common node of the terminating network. The terminating network may have a capacitance configured to couple the common node to ground. The feedback circuit is configured to regulate the voltage level at the common node based on amplitude of the injection current.

The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node. The first amplifier circuit and the second amplifier circuit may include tunable transistors configured to set a voltage level at the common node.

The receiving apparatus may include a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus. The first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers.

Claim 1:
A receiving apparatus (<NUM>), comprising:
a terminating network (<NUM>) for a three-wire serial bus, each wire of the three-wire serial bus being coupled through a resistance to a common node of the terminating network; and characterised in that the apparatus is further comprising
a feedback circuit (<NUM>) comprising:
a first amplifier circuit (<NUM>) having an input coupled to the common node;
a comparator (<NUM>) that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input; and
a second amplifier circuit (<NUM>) responsive to an output of the comparator and configured to inject a current through the common node.