Patent Description:
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Various configurations of electrostatic discharge diode structures and transistor devices and are described. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor and diode operations, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical or in magnetic contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms.

The term "adjacent" here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms.

Unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

Electrostatic discharge (ESD) is one of the most prevalent threats to electronic components. In an ESD event, a large amount of charge is transferred during the fabrication process to a component of a microchip (e.g., transistor, capacitor etc.) or during use of an already fabricated SoC device. The ESD event can lead to large amounts of current to pass through the components of a microchip within a very short period of time. Large amounts of uncontrolled current can cause device degradation and, in some cases, render the device dysfunctional. Thus, designing and integrating structures to protect integrated circuits against ESD events is an important component of the semiconductor device fabrication process. The problem of ESD becomes even greater when the substrate utilized to build the electronic components cannot discharge the extra charge adequately. Logic transistor technologies that utilize fin-FET and nanowire architecture have channel geometries with cross sectional area (laterally through a channel for example) that cannot adequately support high discharge currents flow (during an ESD event). Hence, it is desirable to implement ESD protection devices, such as diodes, near or directly adjacent to logic transistors within a portion of the substrate.

In some examples where two or more substrates are bonded together, ESD protection devices can be implemented in one or more of the substrates. However, in some fin-FET and nanowire architecture implementations, capacitance between bulk substrate directly below fin structures or nanowires and adjacent well of a diode can detrimentally affect transistor characteristics.

The inventors have devised a solution to address proximity of ESD protection devices to logic transistors as well as capacitance issues.

The present invention concerns a device as defined in claim <NUM>.

In one embodiment, the solution involves removing portions of a substrate directly below fins of active transistors but leaving a portion of the substrate in an adjacent region for diode implementation. The fins of respective transistors are above a dielectric that is adjacent to the substrate. In one such embodiment, a first top portion of the substrate is doped with a dopant of a first conductivity type to form a first well and an adjacent second top portion of the substrate is doped with a dopant of a second conductivity type to form a second well of a diode. The boundary between the first and the second well is a P-N junction of the diode. A plurality of fins are also present above the first and the second well. One or more of the plurality of fins on each of the first well and the second well may be heavily doped to be a respective terminal of the diode. To facilitate a large-area ESD protection diode, the one or more of the plurality of doped fins on each of the first well and the second well are coupled with a respective first and a second interconnect below the level of the substrate. The respective first and a second interconnect may have lateral extensions that extend laterally below fins of active transistors as well as under the diode. In bulk substrates, integration schemes that can co-fabricate transistors alongside an ESD protection device by utilizing fin structures as source and drain for respective transistors and doped fin structures as terminals of diodes can provide significant process advantages and offer cost benefits. Cost savings can stem from a lack of a need to implement separate masks for forming terminals of the diode by utilizing fin patterning to simultaneously form fins and terminals for transistors and one or more diodes, respectively, for example.

Devices on floating substrates such as silicon on insulator (SOI) substrates are especially prone to destruction caused by ESD events. ESD protection devices implemented on an SOI substrate do not have the same depth as their bulk counterpart. The junctions are shallower reducing the volume for heat dissipation. The insulator below devices formed on the thin silicon layer, for example, are not as effective for heat dissipation to the substrate below the insulator. However, to overcome this limitation transistors including fins (in a fin-FET implementation) are located on a level above the insulator or buried oxide, and one or more diodes may be implemented in the substrate portion below the insulator by preferentially doping the substrate below the insulator layer.

<FIG> is a cross-sectional illustration of a semiconductor structure <NUM> including a diode <NUM>. A level <NUM> of the semiconductor structure <NUM> includes an interconnect <NUM> and an interconnect <NUM> and a substrate <NUM> between the interconnects <NUM> and <NUM>. The substrate <NUM> may include one or more wells that form a P-N junction of the diode <NUM>. In the illustrative embodiment, diode <NUM> includes a well <NUM> on a first portion of the substrate <NUM>, and a well <NUM> on a second portion of the substrate <NUM>, directly adjacent to the first portion. The wells <NUM> and <NUM> each include a respective dopant of a first conductivity type and of a second conductivity type. In an embodiment, the well <NUM> has a first conductivity associated with a p-type dopant species and the well <NUM> has a second conductivity associated with an n-type dopant species. In an embodiment p-type dopants includes impurity species such as, but not limited to, boron, aluminum, gallium, indium, titanium, and nihonium. In an embodiment n-type dopants include impurity species such as, but not limited to, nitrogen, phosphorus, arsenic, antimony, bismuth, and moscovium. In a different embodiment, the well <NUM> has a first conductivity type associated with an n-type dopant species and the well <NUM> has a second conductivity type associated with a p-type dopant species. In some embodiments, the substrate <NUM> and the wells <NUM> or <NUM> have a total combined thickness, HD. HD can range between <NUM> and <NUM>. The total thickness is substantially less than a total thickness of a silicon substrate, but adequate for an ESD diode. While, HD, is essentially a thickness of the level <NUM>, interconnects <NUM> and <NUM> have a height that is independent of HD. Though in exemplary embodiments, interconnects <NUM> and <NUM> have a height that is at least HD but can be greater than HD. An approximately equal vertical thickness of the interconnects <NUM> and <NUM> and the combined thickness of substrate <NUM> and wells <NUM> or <NUM> is resultant of a processing operation utilized. In embodiments, interconnects <NUM> is a metal line extending into or out of the plane of <FIG>.

In the illustrative embodiment, sidewalls 101A and 101B of diode <NUM> are substantially vertical. In other embodiments, the sidewalls 101A and 101B may taper from an uppermost surface 101C to a lower most surface 101D. Profiles of sidewalls 101A and 101B are a result of a processing operation utilized to fabricate diode <NUM> (described in association with <FIG>). While wells <NUM> and <NUM> are illustrated as having a substantially flat lower most surface, other shapes such as curved lower most surfaces are also possible and depends on distribution of n and p dopants.

The semiconductor structure <NUM> further includes a level <NUM> above level <NUM>, where the level <NUM> includes multiple fins <NUM> (herein fins <NUM>) over different regions. A total number of fins <NUM> in the semiconductor structure <NUM> depends on a lateral width, LW of the semiconductor structure <NUM>. Each of the fins <NUM> may include a semiconductor material. In some embodiments the semiconductor material includes predominantly silicon, silicon germanium or germanium and may further include different types of dopants depending on the region and on a desired transistor-MOS type that is associated with a particular fin in the fins <NUM>. While each fin <NUM> includes predominantly a same semiconductor material (other than differences in dopant species), some fins <NUM> are utilized as source and drain structures for transistors while other fins <NUM> are utilized as terminals of wells <NUM> and <NUM> and include high levels of dopant species advantageous for current conduction to and from wells <NUM> and <NUM>. The implementation of some of the fins <NUM>, e.g., fins 114A and 114B, as terminals of diode <NUM> is an advantage of the design of semiconductor structure <NUM> which includes diode <NUM>.

In the illustrative embodiment, the fins 114A are on well <NUM> and fins 114B are on well <NUM>. The fins 114A and 114B include a same semiconductor material but dopants of opposite conductivity type. In an exemplary embodiment, fins 114A includes a dopant of the conductivity type of well <NUM> and the fins 114B includes a dopant of the conductivity type of well <NUM>. In some embodiments, fins <NUM> and 114B have a dopant gradient that increases in concentration toward the wells <NUM> and <NUM>, respectively. In other embodiments, the dopant gradient is substantially zero and the fins <NUM> and 114B are uniformly doped. Depending on routing interconnects, each of the fins 114A may singly or collectively represent a first terminal and each of the fins 114A may singly or collectively represent a second terminal of diode <NUM>.

The semiconductor structure <NUM> further includes one or more fins over a region <NUM> between the substrate <NUM> and interconnect <NUM> and one or more fins over a region <NUM> between the substrate <NUM> and interconnect <NUM>. In the illustrative embodiment, a plurality of fins 114C (herein fins 114C) are shown on the region <NUM> and a plurality of fins 114D (herein fins 114D) are shown on the region <NUM>. Fins 114C may be associated with a single transistor (within dashed box 121A) or a plurality of transistors above region <NUM> and fins 114D may be associated with a single transistor (within dashed box 121A) or a plurality of transistors above region <NUM>. Structurally fins 114A, 114B, 114C and 114D may each have a same or substantially the same lateral width WF, and a same or substantially the same height HF relative to an uppermost surface 116A of region <NUM>. As shown, fins 114C and 114D are insulated from the substrate <NUM> and well <NUM> by a dielectric <NUM> within region <NUM>. Electrical insulation from the substrate <NUM> and well <NUM> can advantageously reduce junction capacitance between source, drain or channel of one or more of the plurality of transistors within box 121A and the substrate <NUM>, and between source, drain or channel of one or more of the plurality of transistors within box 121B and substrate <NUM>. The number of fins and transistors above regions <NUM> or <NUM> depends on a lateral spacing between substrate <NUM> and respective interconnect <NUM> or <NUM>. In some embodiments, fins 114A, 114B, 114C and 114D may include pairs of fins, where a first pair is separated from an adjacent pair by a substantially same lateral spacing.

To complete routing between the wells <NUM> and <NUM> and various grounding plates, semiconductor structure <NUM> further includes various interconnects and routing lines across multiple levels. In the illustrative embodiment, interconnect <NUM> is on and coupled with the interconnect <NUM> adjacent to fins 114C. The interconnect <NUM> may be a via or a metal line. The interconnect <NUM> is electrically coupled with one or more fins 114A through an interconnect <NUM> (herein routing line <NUM>). The routing line <NUM> may be within level <NUM> or as illustrated on a level <NUM> above level <NUM>. The routing line <NUM> may electrically couple with well <NUM> through one or more fins 114A. In the illustrative embodiment, a single fin 114A is coupled to routing line <NUM>. Routing line <NUM> may be extended on uppermost surfaces of all fins 114A (as indicated by dashed extension of routing line <NUM>) to enable a larger current flux to and from well <NUM>. The interconnect <NUM> may be electrically coupled to a plate <NUM> on a level <NUM> below the substrate <NUM>, through a series of interconnect structures. In the illustrative embodiment, an intermediate interconnect <NUM> is further implemented on a level <NUM> between levels <NUM> and <NUM> to electrically couple the well <NUM> with the plate <NUM>.

In the illustrative embodiment, interconnect <NUM> is on and coupled with the interconnect <NUM> adjacent to fins 114D in region <NUM>. The interconnect <NUM> is electrically coupled with one or more fins 114B through an interconnect <NUM> (herein routing line <NUM>). The routing line <NUM> may be on level <NUM> or as illustrated on level <NUM> above level <NUM>. The routing line <NUM> may electrically couple with well <NUM> through one or more fins 114B. In the illustrative embodiment, a single fin 114B is coupled to routing line <NUM>. Routing line <NUM> may be extended on uppermost surfaces of all fins 114B (as indicated by dashed extension of routing line <NUM>) to enable a larger current flux to and from well <NUM>. The interconnect <NUM> may be electrically coupled to a plate <NUM> on the level <NUM>, through a series of interconnect structures. In the illustrative embodiment, an intermediate interconnect <NUM> is further implemented on level <NUM> between levels <NUM> and <NUM> to electrically couple the well <NUM> with the plate <NUM>.

Interconnects <NUM> and <NUM> may include a material that is compatible with a front-end-of-the-line (FEOL) processing. In some embodiments, interconnects <NUM> and <NUM> includes a liner layer implemented as a diffusion blocker and a fill metal that include a high conductivity material other than copper. The liner layer may include a material such as, but not limited to, ruthenium, titanium nitride, tantalum nitride or tantalum and a fill metal may include tungsten, ruthenium or molybdenum. Interconnects <NUM>, <NUM>, <NUM> and <NUM> and routing lines <NUM> and <NUM> may include copper as a fill metal in addition to the materials discussed above and a liner layer may include a material such as, but not limited to, ruthenium, titanium nitride, tantalum nitride or tantalum. Routing lines <NUM> and <NUM> may include a copper-based interconnect material or a non-copper-based material such as a material of the interconnect <NUM>. In embodiments where routing lines <NUM> and <NUM> include copper, the copper may be surrounded by a diffusion barrier material to prevent copper diffusion into a transistor region, such as above regions <NUM> and <NUM>.

In embodiments, dielectric <NUM> spans levels <NUM>, <NUM> and <NUM> as shown. In some embodiments, dielectric <NUM> includes silicon and one or more of nitrogen, oxygen and carbon, for example, silicon nitride, silicon dioxide, carbon doped silicon nitride, silicon oxynitride or silicon carbide. The semiconductor structure <NUM> further includes a dielectric <NUM> adjacent to the fins <NUM>. The dielectric <NUM> is on dielectric <NUM> and on portions of interconnects <NUM>, <NUM>, and on portions of wells <NUM> and <NUM>. In embodiments, dielectric <NUM> includes a material that is the same or substantially the same as the material of the dielectric <NUM>.

The combination of plate <NUM>, interconnects <NUM>, <NUM> and <NUM>, routing line <NUM>, one or more fins 114A, wells <NUM> and <NUM>, one or more fins 114B, routing line <NUM>, interconnects <NUM>, <NUM> and <NUM>, and plate <NUM> constitutes a diode <NUM> circuit.

<FIG> is a plan view illustration of the semiconductor structure <NUM> in <FIG>, through a line A-A'. Various structures are superimposed for illustrative purposes only. The diode has a length LD and a width, WD that are determined by a total current requirement of the ESD protection sought. The diode <NUM> width, WD may extend beyond an entire length LF, of fins <NUM> or be less than LF. In the illustrative embodiment, diode <NUM> WD is greater than LF. In embodiments, LD is between <NUM> - <NUM> microns and WD is between <NUM> and <NUM> microns.

<FIG> is an enhanced cross-sectional illustration of the box region 121A and 121B depicting a transistor <NUM>, in accordance with an embodiment of the present disclosure. In the illustrative embodiment, a single transistor <NUM> is shown where the transistor is an example of a fin-FET architectures. As shown transistor <NUM> straddles a pair of fins 114C or 114D. The transistor includes a gate electrode <NUM> and a gate dielectric layer <NUM> between uppermost surfaces 114E and sidewalls 114F of fins 114C or 114D. In the illustrative embodiment, the dielectric layer <NUM> is recessed below uppermost surfaces 114E to facilitate a fin-FET architecture. The fins 114C or 114D extend in and out of the plane of the Figure. Source and drain regions of the transistor <NUM> are on portions of the fins 114C or 114D through planes that are in and out of the plane of the Figure. In other embodiments, transistor <NUM> may straddle a single fin 114C or 114D. In an embodiment, the gate dielectric layer <NUM> includes a high-K gate dielectric material. The gate dielectric layer <NUM> may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO<NUM>) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, or zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer <NUM> to improve its quality when a high-k material is used.

The gate electrode <NUM> of the transistor <NUM> is formed on the gate dielectric layer <NUM> and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode <NUM> may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode <NUM> include, but are not limited to, ruthenium, palladium, platinum, cobalt or nickel. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.

<FIG> is an enhanced cross-sectional illustration through fins 114C on a plane in front of the plane of depicted in <FIG>. In the illustrative embodiment, portion of the fins 114C are replaced by a doped source or drain epitaxial structure <NUM>. The dopants in the doped source epitaxial structure may be different from a N or P type dopant in the wells <NUM> or <NUM>. In an embodiment, the source or drain epitaxial structure <NUM> includes Si and Ge, and may be doped with boron, aluminum, gallium, indium, titanium, nihonium, nitrogen, phosphorus, arsenic, antimony, bismuth, or moscovium depending on whether an N-type or a P-type dopant species is required. In the illustrative embodiment, the doped source or drain epitaxial structure <NUM> is surrounded by a dielectric <NUM> that is above dielectric <NUM>. Dielectric <NUM> may include a material that is the same or substantially the same as the material of the dielectric <NUM>.

In some embodiments, the diode <NUM> includes a single well such as well <NUM> or well <NUM>. <FIG> is a cross-sectional illustration of a semiconductor structure <NUM> that includes a diode <NUM> having a single well <NUM> above substrate <NUM>. In embodiments well <NUM> includes one or more features of well <NUM> or <NUM> (described in association with <FIG>). Well <NUM> includes a semiconductor material that is the same or substantially the same as the material of the substrate <NUM>. The well <NUM> includes a dopant of a first conductivity type or of a second conductivity type. In the illustrative embodiment, the P-N junction is formed at an interface between well <NUM> and one of the sets of fins 114A or 114B depending on the conductivity of the dopant species in the fins 114A or 114B relative to the conductivity of the dopant species in the well <NUM>.

In an embodiment, the well <NUM> and fins 114A both include a dopant of a first conductivity type, and the fins 114B include a dopant of a second conductivity type, that is opposite the first conductivity type. In some such embodiment, a P-N junction is formed at an interface <NUM> between the well <NUM> and fins 114B. In other embodiments, the well <NUM> and fins 114B both include a dopant of a first conductivity type, and the fins 114A include a dopant of a second conductivity type, that is opposite the first conductivity type. In some such embodiment, a P-N junction is formed at an interface <NUM> between the well <NUM> and fins 114A. In an embodiment, the first conductivity type is an n-type dopant, and the second conductivity type is a p-type dopant or vice versa. Having a single well <NUM> compared to laterally adjacent wells <NUM> and <NUM> (illustrated in <FIG>), does not diminish the performance of diode <NUM>.

In the illustrative embodiment, sidewalls 201A and 201B of diode <NUM> are substantially vertical. In other embodiments, the sidewalls. In other embodiments, the sidewalls 201A and 201B may taper from an uppermost surface 201C to a lower most surface 201D. Profiles of sidewalls 201A and 201B are a result of a processing operation utilized to fabricate diode <NUM>. While well <NUM> is illustrated as having a substantially flat lower most surface, other shapes such as curved lower most surfaces are also possible and depends on distribution of n or p-type dopants.

In some embodiments, the substrate <NUM> and the well <NUM> have a total combined thickness, HD. HD can range between <NUM> and <NUM>. Other parameters such as plan view area of diode <NUM> may be the same or substantially the same as diode <NUM>. However, because of the absence of a second well, the diode <NUM> may have a smaller effective plan view surface area of the well <NUM>, where the surface is a horizontal surface in an x-y plane. Other features of semiconductor structure <NUM> are substantially the same as semiconductor structure <NUM>.

In some semiconductor structures, diodes are implemented on a silicon on insulator substrate.

<FIG> is a cross-sectional illustration of a semiconductor structure <NUM> implemented on a silicon on insulator type of substrate. Semiconductor structure <NUM> includes one or more features of the semiconductor structure <NUM>. As shown, level <NUM> of the semiconductor structure <NUM> includes an interconnect <NUM> and an interconnect <NUM> and a substrate <NUM> between the interconnects <NUM> and <NUM>. The substrate <NUM> may include one or more wells that form a P-N junction of the diode <NUM>. In the illustrative embodiment, diode <NUM> includes well <NUM> on a first portion of the substrate <NUM>, and well <NUM> on a second portion of the substrate <NUM>. The wells <NUM> and <NUM> each include a respective dopant of a first conductivity type and of a second conductivity type. In an embodiment, the well <NUM> has a first conductivity associated with a p-type dopant species and the well <NUM> has a second conductivity associated with an n-type dopant species. In a different embodiment, the well <NUM> has a first conductivity type associated with an n-type dopant species and the well <NUM> has a second conductivity type associated with a p-type dopant species. In some embodiments, the substrate <NUM> and the wells <NUM> or <NUM> have a total combined thickness, HD. HD can range between <NUM> and <NUM>. While, HD, is essentially a thickness of the level <NUM>, interconnects <NUM> and <NUM> have a height that is independent of HD. Though in exemplary embodiments, interconnects <NUM> and <NUM> have a height that is at least HD and resultant of a processing operation utilized.

In the illustrative embodiment, sidewalls 301A and 301B of diode <NUM> are substantially vertical. In other embodiments, the sidewalls 301A and 301B may taper from an uppermost surface 301C to a lower most surface 301D. Profiles of sidewalls 301A and 301B are a result of a processing operation utilized to fabricate diode <NUM> and will be discussed in association with <FIG>. While wells <NUM> and <NUM> are illustrated as having a substantially flat lower most surface, other shapes such as curved lower most surfaces are also possible and depend on distribution of n and p dopants. As shown, the semiconductor structure <NUM> further includes regions <NUM> and <NUM>, where region <NUM> is between the substrate <NUM> and interconnect <NUM>, and region <NUM> is between the substrate <NUM> and interconnect <NUM>.

The semiconductor structure <NUM> further includes a level <NUM> above level <NUM>, where the level <NUM> includes multiple fins <NUM> (herein fins <NUM>) over different regions such as wells and dielectrics, in contrast to being in contact with the wells <NUM> and <NUM> as in semiconductor structure <NUM> (<FIG>). The level <NUM> includes an insulator layer <NUM> between the level <NUM> and fins <NUM>. The fins <NUM> are over but not in contact with the well <NUM> or <NUM>.

Each of the fins <NUM> may include a semiconductor material. In some embodiments the semiconductor material includes predominantly silicon, silicon germanium or germanium and depending on the region, further includes different types of dopants. While each fin <NUM> includes predominantly a same semiconductor material utilized in source and drain structures for transistors, different portions of the fin <NUM> (in a direction in and out of the plane of the Figure) may be doped differently for different MOS transistor characteristics. For example, Fin 302A may be associated with an NMOS transistor and Fin 302B may be associated with a PMOS transistor. Other features of fin <NUM>, such as width and spacing between successive fins <NUM>, may be substantially identical to fins <NUM> (<FIG> and <FIG>).

Because fins <NUM> are over regions <NUM> and <NUM> and over wells <NUM> and <NUM>, transistors may be associated with each fin <NUM>. In other embodiments, there can be transistors associated with some of the fins <NUM> and not others. The transistors associated with fins <NUM> may be all NMOS or all PMOS, or a combination thereof. In one or more embodiments, the transistors in boxed region <NUM> may be substantially the same as transistors depicted in <FIG> or discrete transistors above one or more of the fins <NUM>.

The semiconductor structure <NUM> further includes a level <NUM> above level <NUM>, where the level <NUM> includes a plurality of interconnects (herein interconnects) over different regions. As shown, interconnect <NUM> is on the interconnect <NUM> and interconnect <NUM> is on interconnect <NUM>. Unlike diode <NUM> in <FIG>, diode <NUM> utilizes metallic terminals as electrodes in various implementations. For example, interconnects <NUM> are on well <NUM> and interconnects <NUM> are on well <NUM>. In the illustrative embodiment, interfaces <NUM> and <NUM> between interconnect <NUM> and well <NUM>, and between interconnect <NUM> and well <NUM>, respectively are Schottky barriers.

To complete routing between the wells <NUM> and <NUM> and respective grounding plates <NUM> and <NUM>, semiconductor structure <NUM> further includes various interconnects and routing lines across multiple levels as discussed previously. The interconnect <NUM> may be electrically coupled with one or more interconnects on the well <NUM> through a routing line <NUM>. The routing line <NUM> may be on level <NUM> or as illustrated, on a level <NUM> above level <NUM>. The routing line <NUM> may be electrically coupled with well <NUM> through one or more interconnects. In the illustrative embodiment, a single interconnect <NUM> is coupled to routing line <NUM>. Routing line <NUM> may be extended on uppermost surfaces of all interconnects <NUM> (as indicated by dashed extension of routing line <NUM>) to enable a larger current flux to and from well <NUM>. The interconnect <NUM> may be electrically coupled to a plate <NUM> on a level <NUM> below the substrate <NUM>, through a series of interconnect structures as discussed above.

The interconnect <NUM> may be electrically coupled with one or more interconnects on the well <NUM> through a routing line <NUM>. The routing line <NUM> may be on level <NUM> or as illustrated, on a level <NUM> above level <NUM>. The routing line <NUM> may be electrically coupled with well <NUM> through one or more interconnects. In the illustrative embodiment, a single interconnect <NUM> is coupled to routing line <NUM>. Routing line <NUM> may be extended on uppermost surfaces of all interconnects <NUM> (as indicated by dashed extension of routing line <NUM>) to enable a larger current flux to and from well <NUM>. The interconnect <NUM> may be electrically coupled to a plate <NUM> on a level <NUM> below the substrate <NUM>, through a series of interconnect structures as discussed above. The combination of plate <NUM>, interconnects <NUM>, <NUM>, <NUM>, routing line <NUM>, one or more interconnects <NUM>, wells <NUM> and <NUM>, one or more interconnects <NUM>, routing line <NUM>, interconnects <NUM>, <NUM> and <NUM>, and plate <NUM> constitutes a diode <NUM> circuit.

The diode <NUM> facilitates ESD protection to transistors formed above the diode <NUM>.

<FIG> is a method <NUM> to fabricate an ESD diode and fin structures above the diode for transistors, in accordance with an embodiment of the present disclosure. The method <NUM> begins at operation <NUM> with the formation of a plurality of fin structures above a substrate. The method <NUM> continues at operation <NUM> with the formation of a first well region in a first portion of the substrate and doping fins above the first well region. The method <NUM> continues at operation <NUM> with the formation of a second well region in a second portion of the substrate and doping fins above the second well region. The method <NUM> continues at operation <NUM> with the process to deposit a dielectric on the plurality of fins, and then removing a portion of the substrate. The method <NUM> continues at operation <NUM> with the process to etch and remove portions of the substrate adjacent to from the first and the second well regions and expose a lower surface of each of the plurality of fins. The method <NUM> continues at operation <NUM> with a process to deposit a second dielectric layer on the upper surface of each of the plurality of fins and form a first plurality of interconnect vias in the second dielectric laterally spaced from first and second well, in accordance with an embodiment of the present disclosure. The method <NUM> continues at operation <NUM> with a process to form grounding connections above the first interconnects. The method <NUM> concludes at operation <NUM> with a process to deposit a third dielectric layer adjacent to the plurality of fins and form a second plurality of interconnect vias in the third dielectric, where at least one interconnect is formed on each of first plurality of interconnects.

<FIG> is a cross-sectional illustration of a wafer <NUM> including a plurality of fins <NUM> formed above a substrate <NUM>. A mask is formed over a substrate <NUM>. In an embodiment, the mask may be formed by a lithographic process on the substrate <NUM>. In other embodiments, the mask is a hardmask that is not removed by a plasma ash process, for example, a mask fashioned from silicon and one or more of oxygen, nitrogen, or carbon. A plasma etch may be utilized to form the fins <NUM>. The fins can be targeted to a depth that is required for a particular transistor device. The spacing between fins may be designed for placement of interconnects such as interconnect <NUM> or <NUM> (indicated in dashed boxes).

In an embodiment, the substrate includes single crystal silicon and the fins can be doped to provide highly doped terminals over well regions and fin-FET transistors over device regions. In other embodiments, the substrate <NUM> and the fins <NUM> can include two different materials. For example, substrate <NUM> can include silicon and the fins <NUM> can include silicon germanium. In, yet another embodiment, the fins can be formed of a multilayer stack of SiGe/Si bilayer to enable formation of nanowires. The nanowires can be formed in the device regions and the stack of SiGe/Si bilayer can be left as a patterned fin structure that can be doped to form terminals over well regions, in some embodiments.

<FIG> is a cross-sectional illustration of the structure in <FIG> following the formation of a well <NUM> in a region <NUM> of the substrate <NUM> and doping of a plurality of fins 114A above the well <NUM>, in accordance with an embodiment of the present disclosure. A first of a dual mask and implant process is described herein.

In an embodiment, a mask <NUM> is formed over a substrate <NUM>. The mask <NUM> may be formed by a lithographic process on the fins <NUM> and on the substrate <NUM>. The mask has a well opening <NUM> to expose fins <NUM> and portion of the substrate <NUM>. In an embodiment, the portion of the substrate <NUM> exposed by well opening <NUM> is subjected to dopant implant. In an embodiment, the dopants include n-type impurities or p-type impurities. In an embodiment p-type dopants include impurity species such as but not limited to boron, aluminum, gallium, indium, titanium, and nihonium. In an embodiment n-type dopants include impurity species such as but not limited to nitrogen, phosphorus, arsenic, antimony, bismuth, and moscovium. In an embodiment, the n or p-type dopants are implanted into a substrate <NUM> using an ion implanter. In an embodiment, the n or p-type dopants are implanted into the substrate <NUM> to a concentration level between 1e12/cm<NUM> - <NUM> e20/cm<NUM>. In an embodiment, the dopants are subsequently activated by a process of high temperature anneal to form a well <NUM> having an n-conductivity type or a p-conductivity type. The dopant implant process is targeted to various depths in the substrate <NUM> and in the fins <NUM>, so that the fins <NUM> are adequately doped at the end of doping process to formed doped fins 114A (herein fins 114A). In the illustrative embodiment, the fins 114A can act as a mask during dopant implant, but a high temperature anneal process can be utilized to distribute dopants into regions directly under the fins 114A. After the doping process the mask <NUM> may be removed before a high temperature anneal process.

In an embodiment, the high temperature anneal process causes further diffusion of the dopant species in the substrate <NUM> and expanding the well <NUM> by a distance ranging from <NUM> to <NUM> laterally and an approximately equal distance vertically into the substrate <NUM> beyond the initial spatial extent of the well <NUM>. Dopants that may have diffused under the mask and under fins 114C protected by the mask, may be removed in a subsequent process operation where portions of the substrate <NUM> are removed. In an embodiment, the high temperature anneal is carried out using a rapid thermal process (RTP) at a process temperature ranging from <NUM>-<NUM> degrees Celsius and for a time duration ranging from <NUM> - <NUM>. In an embodiment, the RTP is performed in an ambient including one or more combination of gases such as but not limited to H<NUM>, N<NUM>, O<NUM>. In an embodiment, the annealing process is carried out after forming a second well, as will be discussed below. In other embodiments, the anneal process is carried out after performing a second well implant and creating a second well in region <NUM> adjacent to region <NUM>.

<FIG> is a cross-sectional illustration of the structure in <FIG> following the formation of a well <NUM> in the region <NUM>, directly adjacent to well <NUM> and doping of a plurality of fins <NUM> directly above the well <NUM>, in accordance with an embodiment of the present disclosure. The process operation described herein is a second of the mask and dual implant process.

In an embodiment, the process to form well <NUM> is substantially the same as process to form well <NUM>. A mask <NUM> is formed on the fins <NUM>, on the substrate <NUM> and on the well <NUM>. The mask <NUM> includes an opening <NUM> that exposes fins <NUM> in a region <NUM> of the substate <NUM>, directly adjacent to well <NUM>. The dopant species chosen for well implant through the opening <NUM> have a conductivity type that is opposite to the dopant species implanted to form well <NUM> and fins 114A. The dopant concentration may be substantially identical to the processes utilized to dope and form well <NUM>. The dopant implant process is targeted to various depths in the substrate <NUM> and in the fins <NUM> exposed by the mask <NUM>. In an embodiment, the fins <NUM> are sufficiently doped at the end of doping process to formed doped fins 114B (herein fins 114B). The n or p-type dopants may be implanted into the region <NUM> of substrate <NUM> to a concentration level between 1e19/cm3 - <NUM> e20/cm3. In the illustrative embodiment, the fins 114B can act as a mask during dopant implant, but a high temperature anneal process can be utilized to distribute dopants into regions directly under the fins 114B. After the doping process the mask <NUM> may be removed before a high temperature anneal process.

In an embodiment, a thermal anneal process is performed after both n-type and p-type species have been implanted to limit lateral diffusion of dopants utilized to form well <NUM> into region <NUM>. In one or more embodiments the dopant profile may be the same or substantially the same as a dopant profile obtained after forming well <NUM>. Some dopants utilized to form well <NUM> may laterally diffuse under the mask <NUM> and under fins 114D after the anneal.

The dual implant process described above results in formation of wells <NUM> and fins 114A in region <NUM> and well <NUM> and fins 114B in region <NUM> directly adjacent to region <NUM> and forming a P-N junction at interface <NUM> at a boundary between wells <NUM> and <NUM>.

<FIG> is a cross-sectional illustration of the structures in <FIG> following a process to deposit a dielectric <NUM> on the fins <NUM>, followed by removal of a portion of the substrate <NUM>. In an embodiment, the dielectric layer <NUM> is blanket deposited on the fins <NUM> and on portions of the substrate <NUM>, and on the wells <NUM> and <NUM> by a plasma enhanced chemical vapor deposition (PECVD) or a chemical vapor deposition (CVD) process. In an embodiment, the dielectric layer <NUM> includes silicon and one or more of nitrogen, oxygen and carbon, for example, silicon nitride, silicon dioxide, carbon doped silicon nitride, silicon oxynitride or silicon carbide.

After the deposition process the dielectric layer <NUM> may be planarized to form a substantially flat surface 146A. A chemical mechanical polish (CMP) process may be utilized to perform a planarization process. In embodiments, portion of the dielectric <NUM> is left above the fins <NUM> for protection of uppermost fin surfaces during a subsequent planarization process.

In the illustrative embodiment, combination of wet chemical, plasma etch, and a CMP process may be utilized to remove portions of the substrate <NUM>. In an embodiment, the combined vertical thickness, HS, of the substrate <NUM> (excluding fins <NUM>) and well <NUM> or <NUM> is less than <NUM>. In exemplary embodiments, the thickness can be less than <NUM>. In embodiments, HS is designed to substantially match a height of interconnects to be formed laterally adjacent to the substrate <NUM> and well <NUM> or <NUM>.

<FIG> is a cross-sectional illustration of the structures in <FIG> following the process to etch and remove portions of the substrate <NUM> away from the wells <NUM> and <NUM> and expose a surface of each of the fins 114C and 114D. In an embodiment, a mask <NUM> is formed above the substrate. The mask <NUM> may include a hardmask fashioned from a dielectric material such as a silicon nitride, silicon carbide, silicon oxynitride etc. In some embodiments, a metal hard mask may be utilized. A metal hardmask may help to provide vertical etch profiles of the substrate and wells. A metal hardmask may be desirable in some embodiments where the substate is silicon or silicon germanium because a plasma etch process implemented may utilize oxygen gas in addition to a corrosive etchant to etch the silicon or silicon germanium. Implementation of oxygen containing etchants can provided enhanced selectivity during patterning of silicon or silicon germanium substrates. Metal hard masks may provide robust etch selectivity against silicon enabling etching of thick substrates, such as <NUM> or above. Because of proximity to a nearby fin 114C or 114D, it is desirable to have profile of the well <NUM> and <NUM> to be as vertical as possible. In an exemplary embodiment, a plasma etch process is utilized to obtain an anisotropic etch profile. In some embodiments a combination of wet etch and plasma etch may be utilized.

In the illustrative embodiment, expanded portions of wells <NUM> and <NUM> (indicated by curved lines <NUM>) that are formed by diffusion of dopants are not protected by the mask <NUM> and removed by the etch process. The plasma etch process may be utilized to end point and stop once the dielectric <NUM> is exposed. An end-point detection program can be advantageously utilized to detect dielectric <NUM> after the substrate <NUM> is etched. Given that a majority of the wafer <NUM> includes exposed dielectric <NUM>, an-endpoint program can be reliably utilized to etch the substrate <NUM> and prevent over etching into the fins 114C and 114D. In some embodiments, uppermost portions (in the rotated Figure) of the fins 114C and 114D may be partially etched during the etch process but not appreciable to detrimentally affect devices that will be formed utilizing fins 114C and 114D. It is to be appreciated that the doped fins 114A and 114B are not exposed during the etch process as they are covered by the mask <NUM>.

In the illustrative embodiment, wells <NUM> and <NUM> have sidewalls 101A and 101B that are substantially vertical. In other embodiments, the sidewalls 101A and 101B may be tapered outward towards interface with dielectric <NUM>. In other embodiments, the mask <NUM> is wider than a combined lateral width, LW of the wells <NUM> and <NUM>. In some such embodiments, portions of the substrate <NUM> remains adjacent to the wells <NUM> and <NUM>, as indicated by substrate <NUM> (within dashed lines). The mask <NUM> may be removed after etching of substrate <NUM>.

<FIG> is a cross-sectional illustration of the structures in <FIG> following the process to deposit a dielectric layer <NUM> on the upper surface (in the rotated illustration) of each of the plurality of fins 114C and 114D and form a first plurality of interconnects <NUM> and <NUM> in the dielectric <NUM> laterally spaced from the substrate <NUM>, in accordance with an embodiment of the present disclosure. In an embodiment, the dielectric <NUM> includes a material that is blanket deposited on the substrate <NUM>, on the dielectric <NUM>, on fins 114C and 114D and on the mask <NUM>. The dielectric <NUM> may be deposited by a plasma enhanced chemical vapor deposition (PECVD) or a chemical vapor deposition (CVD) process. In an embodiment, the dielectric layer <NUM> includes silicon and one or more of nitrogen, oxygen and carbon, for example, silicon nitride, silicon dioxide, carbon doped silicon nitride, silicon oxynitride or silicon carbide. In an embodiment, a planarization process is utilized to remove portions of the dielectric above the mask <NUM> (in dashed box), the mask <NUM> and portions of the dielectric <NUM> adjacent to the mask <NUM>. In other embodiments, the dielectric above the mask <NUM> is planarized, but left above the mask <NUM> until openings for interconnects are formed and material of the interconnects <NUM> and <NUM> are deposited.

In an embodiment, openings <NUM> and <NUM> are formed in the dielectric <NUM>. One or more metallization layers may be deposited into the openings <NUM> and <NUM> and on the surface of the dielectric <NUM>. In some embodiments where a surface 106A of substrate <NUM> is exposed post dielectric <NUM> deposition and planarization, the metallization layers is also deposited on surfaces of the substrate <NUM>. In other embodiments, metallization layers are deposited on surfaces of the dielectric <NUM> when substrate <NUM> is not exposed.

In an embodiment, deposition of the metallization layers includes forming a liner layer <NUM> in the openings <NUM> and <NUM> and on the dielectric <NUM>, as is shown. A fill metal <NUM> may be deposited in the opening <NUM> on the liner layer <NUM> as well as outside the openings <NUM> and <NUM>. In an exemplary embodiment, a material including ruthenium, tantalum nitride or tantalum may be used as a liner layer <NUM> in the openings <NUM> and <NUM> followed by deposition of a fill metal <NUM> such as copper, tungsten, ruthenium or molybdenum on the liner layer <NUM>. The liner layer <NUM> also serves as a barrier layer against copper diffusion into a vicinity of the fins 114C and 114D, and into wells <NUM> and <NUM>.

In an embodiment, a planarization process is utilized to remove the excess liner layer <NUM> and fill metal <NUM> to form interconnects <NUM> and <NUM> as shown. It is to be appreciated that a height, H<NUM> of level <NUM>, relative to dielectric surface 146A is determined by the planarization process.

<FIG> is a cross-sectional illustration of the structures in <FIG> following the process to deposit a dielectric layer <NUM> on the interconnects <NUM> and <NUM>, on the substrate <NUM> and on the dielectric <NUM>. The dielectric <NUM> may be deposited by a plasma enhanced chemical vapor deposition (PECVD) or a chemical vapor deposition (CVD) process. Dielectric <NUM> may be deposited to a thickness that is desired to tune a height of interconnects to be formed within level <NUM>. Dielectric <NUM> includes a material that is the same or substantially the same as the material of the dielectric <NUM>. The interconnects <NUM> and <NUM> may be formed by a same or substantially the same method as a method utilized to fabricate interconnects <NUM> and <NUM>.

After formation of interconnects <NUM> and <NUM>, a dielectric <NUM> is subsequently blanket deposited on the interconnect <NUM> and <NUM> and on the dielectric <NUM>. Blanket deposition may be performed using a plasma enhanced chemical vapor deposition (PECVD) or a chemical vapor deposition (CVD) process. Dielectric <NUM> includes a material that is the same or substantially the same as the material of the dielectric <NUM> or <NUM>. Dielectric <NUM> may be deposited to a thickness that is desired to tune a height of routing plates to be formed. The routing plates <NUM> and <NUM> may be formed using a same or substantially the same method as a method utilized to fabricate interconnects <NUM> and <NUM>. In the illustrative embodiment, the liner layers and fill layers are removed for clarity.

<FIG> is a cross-sectional illustration of the structures in <FIG> following the process to form a plurality of interconnect vias in the dielectric <NUM> adjacent to fins 114A, 114B, 114C, and 114D. When the dielectrics <NUM>, <NUM> and <NUM> include a same material, dielectrics <NUM>, <NUM> and <NUM> are consolidated into a single dielectric <NUM> as shown in the illustration.

After formation of plates <NUM> and <NUM>, processing is resumed on the fin <NUM> side of wafer <NUM>. In an embodiment, openings are formed in the dielectric <NUM> by masking the dielectric <NUM> and fins 114A, 114B, 114C, and 114D. In an embodiment, interconnects may be formed after fabrication of transistors above the fins 114C, and 114D. In other embodiments interconnects <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> may be formed prior to forming transistors above fins 114C and 114D. In an embodiment, the process to fabricate interconnects <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> includes a method that is the same or substantially the same as the method utilized to fabricate interconnect <NUM> or <NUM>. However, the materials utilized may be different depending on whether the interconnects are formed before or after the transistors are formed above fins 114C and 114D. Copper or other conductive materials that are prone to diffusion may not be compatible with front end of the line transistor fabrication methods.

In an embodiment, fabricating the interconnects <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> includes depositing a liner layer including tantalum, titanium nitride, tantalum nitride, or ruthenium and a fill metal such as but not limited to tungsten or ruthenium on the liner layer in openings formed in the dielectric <NUM>.

In some embodiments, fabrication of interconnect vias <NUM>, <NUM>, <NUM> and <NUM> is optional. In other embodiments, vias <NUM> and <NUM> may be fabricated and routed to a routing lines such as routing line <NUM> and <NUM>, respectively (described in association with <FIG>), however fabrication of interconnects <NUM> and <NUM> may be optional.

In an embodiment, devices such as transistors above fins 114C and 114D, and interconnect routing to transistors can be fabricated next and routing lines <NUM> and <NUM> (not shown in Figure) can be fabricated once the transistors are fabricated.

While a method to fabricate the semiconductor structure <NUM> has been described, methods to fabricate other embodiments of the semiconductor structure <NUM> described herein may utilize one or more processing operations described above. When a single well such as well <NUM> or <NUM> only is desired, then the process operations described in association with <FIG> and <FIG> may be modified to include different mask sizes and target an appropriate doping depth within the fin structures 114B. The modification is illustrated in <FIG>.

<FIG> is a cross-sectional illustration of the structure in <FIG> f following a first of a dual stage implant process, where a first stage of the implant includes implanting a dopant of a same conductivity type to the dopant utilized to form well <NUM> into a region <NUM> of substrate <NUM> directly adjacent to the well <NUM>. In the illustrative embodiment, the implant process (indicated by arrows <NUM>) targets dopants into a region <NUM> of the substrate <NUM> adjacent to well <NUM> through opening <NUM> in mask <NUM>. Region <NUM> is an expansion of the well <NUM> and is doped in two stages to prevent doping of the fins <NUM> exposed in the opening <NUM>.

In some such embodiment, the dopants and dopant concentration are the same as the dopants and dopant concentration utilized to form well <NUM>, where the conductivity type of the dopant may be N or P type. In some embodiments, some negligible amount of dopants will be absorbed by the fins <NUM> during this process because the doping process predominantly targets implants into the region <NUM> of substrate <NUM>.

In other embodiments, a hardmask material, indicated by dashed box <NUM> can be left on the fins 114B post patterning, where the hardmask material can be utilized to block the dopants from reaching the fins.

<FIG> is a cross-sectional illustration of the structure in <FIG> following a second of a dual stage implant process, where a second stage of the dual stage implant includes implanting a dopant of a different conductivity type to the dopant utilized to expand well <NUM> into the region <NUM> of substrate <NUM>. In exemplary embodiments, the implant process (indicated by arrows <NUM>) target dopants to a shallower depth than during a process to implant to form well <NUM>.

In exemplary embodiments, implant dopant density or concentration level targeted in the fins <NUM> in the opening <NUM> is the same or substantially the same as a dopant density or concentration level targeted to form well <NUM>. N or P-type dopants (n-type if well <NUM> is p-type or vice versa) may be implanted into the fins to a concentration level between 1e12/cm3 - <NUM> e20/cm3. In some embodiments, the dopant density or concentration level targeted to produce doped fins 114B is reduced compared a dopant density or concentration level targeted to form well <NUM>. In other embodiments, the well <NUM> could be masked with a flowable material including carbon and oxygen to protect the well <NUM> during doping to fabricate doped fins 114B. The flowable material could partially fill the opening <NUM>.

In embodiments, where the semiconductor structure includes a SOI substrate such as is depicted in <FIG>, the method described in association with <FIG> and <FIG> may be utilized.

<FIG> is a cross-sectional illustration of process to form a well <NUM> in the substrate <NUM> of a workpiece <NUM> that includes a plurality of fins <NUM> fabricated above the substrate <NUM>. In the illustrative embodiment, the targeted region <NUM> for well formation is below a level of insulator layer <NUM>. In an embodiment, a high energy implantation process (indicated by arrows <NUM>) is utilized to drive implants into a region <NUM> below the insulator layer <NUM> directly below opening <NUM> in mask <NUM>. The high energy implantation process is designed to implant dopants into the substrate <NUM> and limit dopants from being implanted into the fins 302A within the opening <NUM>. In embodiments, hardmask <NUM> can be left on fins 302A to prevent dopants from being implanted in the fins 302A. In the illustrative embodiment, the fins 302A can act as a mask during dopant implant, but a high temperature anneal process can be utilized to distribute dopants into regions directly under the fins 302A.

Because the fins 302A are not designed to be terminals, implantation is not required for a diode fabricated downstream. Hence, the method described herein can be replicated to create a well laterally adjacent to well <NUM> and form a P-N junction diode. Once both N and P wells are formed. The process operations outlined above in association with <FIG> or some variations thereof can be implemented to fabricate transistors above the fins <NUM>. It is to be appreciated that fins <NUM> may include a stack of layers that can be utilized in the formation of nanowire transistors or fin-FET devices. In fin-FET devices, portions of the fins <NUM> can be replaced in source and in drain regions of fins <NUM> by etching and regrowing doped epitaxial structures to enable P and/or N-MOS devices.

<FIG> illustrates a computing device <NUM> in accordance with embodiments of the present disclosure. As shown, computing device <NUM> houses a motherboard <NUM>. Motherboard <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communications chip <NUM> or <NUM>. Processor <NUM> is physically and electrically coupled to the motherboard <NUM>. In some implementations, communications chip <NUM> is also physically and electrically coupled to motherboard <NUM>. In further implementations, communications chip <NUM> is part of processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset <NUM>, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communications chip <NUM> enables wireless communications for the transfer of data to and from computing device <NUM>. Communications chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. Computing device <NUM> may include a plurality of communications chips <NUM> and <NUM>. For instance, a first communications chip <NUM> may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communications chip <NUM> may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within processor <NUM>. In some embodiments, the integrated circuit die of processor <NUM> includes non-volatile memory devices, one or more semiconductor structures such as semiconductor structures <NUM>, <NUM> or <NUM> that include an ESD protection diode and transistors adjacent to the ESD protection diode, as described in association with <FIG>, <FIG> or <FIG>. Referring again to <FIG>, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communications chip <NUM> also includes an integrated circuit die packaged within communication chip <NUM>. In another embodiment, the integrated circuit die of communications chips <NUM>, <NUM> includes one or more interconnect structures, non-volatile memory devices, capacitors. Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM) <NUM>, <NUM>, non-volatile memory (e.g., ROM) <NUM>, a graphics CPU <NUM>, flash memory, global positioning system (GPS) device <NUM>, compass <NUM>, a chipset <NUM>, an antenna <NUM>, a power amplifier <NUM>, a touchscreen controller <NUM>, a touchscreen display <NUM>, a speaker <NUM>, a camera <NUM>, and a battery <NUM>, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device <NUM> and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of nonvolatile memory devices.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an Ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

<FIG> illustrates an integrated circuit (IC) structure <NUM> that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some embodiments, the first substrate <NUM> and the second substrate <NUM> are attached to opposing sides of the integrated circuit (IC) structure <NUM>. In other embodiments, the first substrate <NUM> and the second substrate <NUM> are attached to the same side of the integrated circuit (IC) structure <NUM>. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure <NUM>.

The integrated circuit (IC) structure <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group Ill-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The integrated circuit (IC) structure <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such embedded devices <NUM> include capacitors, resistors, inductors, fuses, diodes, transformers, device structure including transistors. The integrated circuit (IC) structure <NUM> may further include embedded devices such as one or more resistive random-access devices, sensors, and electrostatic discharge (ESD) devices such as ESD protection diode <NUM> and transistors adjacent to the ESD protection diode <NUM> that are part of semiconductor structures <NUM>, <NUM> or <NUM>, as described in association with <FIG>, <FIG> or <FIG>, respectively. Referring again to <FIG>, more complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure <NUM>.

Semiconductor device structures including ESD protection diodes and transistors are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Claim 1:
A semiconductor device structure comprising:
a first level (<NUM>) comprising:
a first interconnect (<NUM>) and a second interconnect (<NUM>);
a substrate (<NUM>) between the first and second interconnects; and
one or more wells (<NUM>, <NUM>) on the substrate; and
a second level (<NUM>) comprising:
multiple fins (<NUM>) comprising a semiconductor material, the multiple fins further comprising:
a first fin (114A) and a second fin (114B) each on the one or more wells (<NUM>, <NUM>), wherein the first fin
and the one or more wells comprise respective dopants each of a first conductivity type and wherein the second fin comprises a dopant of a second conductivity type different from the first conductivity type;
characterized in that:
the first fin, second fin and the one or more wells forming a diode structure (<NUM>); and
the second level further comprising:
a third fin (114C) over a first region (<NUM>) between the substrate and the first interconnect; and
a fourth fin (114D) over a second region (<NUM>) between the substrate and the second interconnect;
wherein the first and the second regions comprise a dielectric material;
a third interconnect (<NUM>) on the first interconnect and electrically coupled to the first fin; and
a fourth interconnect (<NUM>) on the second interconnect and electrically coupled to the second fin; and
wherein the semiconductor device structure further comprises transistors (<NUM>) on the third and on the fourth fins but not on the first or on the second fins.