Patent Description:
Three dimensional (3D) NAND flash memory technology has been developed to achieve higher data storage density without requiring smaller memory cells. A 3D NAND memory device usually includes array transistors that form vertical memory cell strings and peripheral transistors that form peripheral circuits. In a traditional 3D NAND device, array transistors and peripheral transistors are processed on a same substrate. In an Xtacking architecture, however, an array substrate containing array transistors and a peripheral substrate containing peripheral transistors are stacked face to face via a bonding interface, with transistors sandwiched between the two substrates. Hence, the Xtacking architecture can achieve a higher storage density, a simpler process flow, and a shorter cycle time.

The Xtacking architecture can also include pad-out structures on the back side of either the array substrate or the peripheral substrate. External circuitry can therefore provide control signals via the pad-out structures to the transistors sandwiched between the two substrates. Pad-out structures can be manufactured in a through-silicon-contact (TSC) configuration. <CIT> relates to a three-dimensional memory device with backside source contact. In more details, <CIT> shows a method for fabricating a semiconductor device, comprising: bonding a first die and a second die face to face, the first die including a first substrate, a first contact structure on the face side of the first die, and a semiconductor layer and first transistors formed on a face side of the semiconductor layer ; exposing the first contact structure from the back side of the first die ; forming, from the back side of the first die, a contact hole, the contact hole exposing the semiconductor layer ; and forming, on the back side of the first die, a first pad-out structure conductively connected with the first contact structure and an electrically conductive structure on the contact hole that is conductively connected with the semiconductor layer. <CIT> relates to a bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer. <CIT> is a prior art document according to Article <NUM>(<NUM>) EPC and describes a bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same.

The disclosure provides a method for fabricating pad-out structures for a semiconductor device of an Xtacking architecture.

The present invention relates to a method for fabricating a semiconductor device according to claim <NUM>.

In accordance with the claimed invention, first transistors are formed on a face side of the semiconductor layer. In some embodiments, the first transistors can include memory cells. The memory cells can include a stack of alternating word line layers and insulating layers, and a plurality of channel structures extending through the stack. In some embodiments, the first die can further include a plurality of contact structures formed in a staircase region of the stack, the plurality of contact structures being coupled with the word line layers. The staircase region can be on a boundary or in the middle of the stack. Further, a channel structure can include a channel layer surrounded by one or more insulating layers.

In some embodiments, the second die can include a substrate and peripheral circuitry that is formed on the face side of the substrate for the memory cells.

The first pad-out structure can include a first portion of a first conductive layer, and the second pad-out structure can include a second portion of the first conductive layer. The first portion of the first conductive layer can be spaced apart from the second portion of the first conductive layer. The first conductive layer can be made of a first metal material. In some embodiments, the first pad-out structure can further include a first portion of a second conductive layer disposed between the first contact structure and the first pad layer. The second pad-out structure can further include a second portion of the second conductive layer disposed between the semiconductor layer and the second pad layer. The first portion of the second conductive layer can be spaced apart from the second portion of the second conductive layer. The second conductive layer can be made of a second metal material. In an example, the first metal material is made of aluminum, and the second metal material is made of titanium.

In some embodiments, the first pad-out structure can be coupled with an input/output circuit of the peripheral circuitry via the first contact structure, a bonding interface between the first die and the second die, and a corresponding second contact structure in the second die. The peripheral circuitry can be coupled with the memory cells via corresponding third contact structures in the first die, the bonding interface, and corresponding fourth contact structures in the second die. The second pad-out structure can be configured to provide an array common source for the memory cells.

In alternative embodiments, the second die can further include memory cells formed on the face side of the substrate, and the first transistors can include peripheral circuitry, formed on the face side of the substrate, for the memory cells. Further, the first pad-out structure can be coupled with an input/output circuit of the peripheral circuitry via the first contact structure, and the peripheral circuitry can be coupled with the memory cells via corresponding contact structures in the first die, a bonding interface between the first die and the second die, and corresponding contact structures in the second die.

In some embodiments, the first die can further include memory cells formed on the face side of the semiconductor layer, and the second die can include peripheral circuitry for the memory cells on a face side of a second substrate. In some embodiments, bonding the first die and the second die face to face can further include bonding a first bonding structure connected with the first contact structure in the first die with a second bonding structure connected to an input/output circuit in the peripheral circuitry in the second die.

In alternative embodiments, the second die can include memory cells disposed on the face side of the second die, and the first die can further include peripheral circuitry for the memory cells.

The method includes removing an etch stop layer after removing the first substrate, wherein the etch stop layer is sandwiched between the first substrate and the insulating layer.

In some embodiments, the second pad-out structure can be configured to provide an array common source for the memory cells.

Further, forming the first pad-out structure and the second pad-out structure can include forming, from the back side of the first die, a first conductive layer over the first contact structure and the semiconductor layer, and the first conductive layer fills the contact hole, and patterning, from the back side of the first die, the first conductive layer to form the first pad-out structure conductively connected with the first contact structure and the second pad-out structure conductive connected with the semiconductor layer. In some embodiments, a second conductive layer can be formed on a back side of the insulating layer where the second conductive layer interfaces the first conductive layer and the first contact structure and interfaces the first conductive layer and the semiconductor layer, and the second conductive layer is patterned using a same photomask as the first conductive layer.

In some embodiments, the first conductive layer can be made of a first metal material, and the second conductive layer can be made of a second metal material. In an example, the first conductive layer includes at least titanium, and the second conductive layer includes at least aluminum.

In fact, the dimensions of the various features may be increased or reduced for clarity of discussion.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

The present disclosure provides a method of forming pad-out structures for a 3D memory device of an Xtacking architecture. The method according to the present invention includes bonding a first die and a second die, removing a substrate of the first die, forming a contact hole, and forming pad-out structures. Compared with through-silicon-contact (TSC) pads for an Xtacking architecture, the disclosed method eliminates the need for deposition and etching of additional dielectric layers and TSC metals, therefore simplifying the manufacturing process.

<FIG> is a cross-sectional view of a semiconductor device <NUM>, in accordance with exemplary embodiments of the disclosure. As illustrated, the device <NUM> includes a first die D1 and a second die D2 bonded together via a bonding interface <NUM> in a face-to-face fashion (a circuitry side is face, and a substrate side is back). The first die D1 and the second die D2 can respectively include bonding structures <NUM> and <NUM> that are correspondingly aligned with each other. Further, a bonding structure <NUM> can be electrically coupled with a corresponding bonding structure <NUM>.

As shown in <FIG>, the first die D1 includes an insulating layer <NUM> (e.g., silicon oxide), a semiconductor layer <NUM> (e.g., doped polysilicon) on the face side of the insulating layer <NUM>, and a first contact structure <NUM> (e.g., tungsten) that is formed on the face side of and extends through the insulating layer <NUM>.

The first die D1 can also include 3D NAND memory cells. For example, a stack of alternating insulating layers <NUM> and word line layers <NUM> (also referred to as gate layers) can be disposed on the face side of the semiconductor layer <NUM>. The stack can include an array region <NUM> where at least one channel structure <NUM> is formed and extends through the stack into the semiconductor layer <NUM>. The stack of insulating layers <NUM> and word line layers <NUM> and the channel structure <NUM> can form a stack of transistors, such as an array of vertical memory cell strings. In some examples, the stack of transistors can include memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, and the like. In some examples, the stack of transistors can also include one or more dummy select transistors.

The insulating layers <NUM> can be made of insulating material(s), such as silicon nitride, silicon dioxide, and the like. The word line layers <NUM> can be made of gate stack materials, such as high dielectric constant (high-k) gate insulator layers, metal gate electrode, and the like. The channel structure <NUM> can include a channel layer <NUM> (e.g., polysilicon), surrounded by one or more insulating layers <NUM>, such as a tunneling layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide) that together form an oxide-nitride-oxide structure surrounding the channel layer <NUM>.

Further, the stack can have a staircase region <NUM> where a plurality of second contact structures <NUM> and a third contact structure <NUM> are formed. The second contact structures <NUM> are connected to the word line layers <NUM> that can function as gates and dummy gates of the vertical memory cell strings. The third contact structure <NUM> is connected to the semiconductor layer <NUM>. Note that the device <NUM> can have various staircase configurations, such as center staircase implementation, side staircase implementation, and the like.

Still in <FIG>, the first die D1 can further include a first conductive layer <NUM> (also referred to as a pad layer) on a back side of a second conductive layer <NUM> (also referred to as a liner layer) that has a first portion 161a covering the back side of the first contact structure <NUM> and a second portion 161b covering a hole of the insulating layer <NUM>. A first portion of the first conductive layer 171a and a second portion of the first conductive layer 171b can be disposed on the back side of the first and second portions of the second conductive layer 161a and 161b, respectively, to form a first pad-out structure and a second pad-out structure. The first portion of the first conductive layer 171a can be electrically coupled with the first contact structure <NUM>, and the second portion of the first conductive layer 171b can be electrically coupled with the semiconductor layer <NUM>. In this example, the first conductive layer <NUM> is aluminum, and the semiconductor layer <NUM> is polysilicon. The second conductive layer <NUM> can be an adhesion layer, such as a titanium layer with a thickness in the range of <NUM>-<NUM>, disposed between aluminum and polysilicon. In some embodiments, the second conductive layer <NUM> may be formed of a titanium silicide under a relatively high temperature (e.g., above <NUM>). In other examples, the first conductive layer <NUM> can be made of other conductive materials, and the second conductive layer <NUM> can be a barrier layer, a seed layer, and/or an adhesion layer. The second conductive layer <NUM> can also be used to reduce contact resistance. In some embodiments, the second conductive layer <NUM> may not be necessary.

In the <FIG> example, the first die D1 can include 3D memory cells, and the second die D2 can include peripheral circuitry (e.g., address decoder, driving circuits, sense amplifier, and the like). Generally, the peripheral circuitry of the second die D2 can interface the memory cells with external circuitry. For example, the peripheral circuitry receives instructions from the external circuitry via the first pad-out structure (171a and 161a), provides control signals to the memory cells, receives data from the memory cells, and outputs data to the external circuitry via the first pad-out structure (171a and 161a). Further, in some embodiments, the semiconductor layer <NUM> is coupled to an array common source (ACS) for a memory cell array so the second pad-out structure (171b and 161b) can provide input/output pad-out structure for ACS.

For simplicity, a substrate <NUM> and two transistors <NUM> formed thereon are shown in the second die D2. For example, the transistors <NUM> can form a complementary metal oxide semiconductor (CMOS). The substrate <NUM> can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate <NUM> may be a bulk wafer or an epitaxial layer. Nota that the first die D1 initially includes a substrate, on which the semiconductor layer <NUM> and the insulating layer <NUM> are disposed. The substrate is removed prior to the formation of the pad-out structures (<NUM> and <NUM>).

In some embodiments, a semiconductor memory device can include multiple array dies (e.g., the first die D1) and a CMOS die (e.g., the second die D2). The multiple array dies and the CMOS die can be stacked and bonded together. Each array die is coupled to a portion of the CMOS die, and the CMOS die can drive the array dies individually or together in a similar manner. Further, in some examples, the semiconductor device <NUM> includes at least a first wafer and a second wafer bonded face to face. The first die D1 is disposed with other array dies like D1 on the first wafer, and the second die D2 is disposed with other CMOS dies like D2 on the second wafer. The first wafer and the second wafer are bonded together so that the array dies on the first wafer are bonded with corresponding CMOS dies on the second wafer.

In alternative embodiments, the first die D1 can include peripheral circuitry, and the second die D2 can include 3D memory cells (not shown). The pad-out structures (<NUM> and <NUM>) can still be disposed on the back side of the first die D1. Since the input/output signals do not need to route through the memory cell array die, the input/output signal paths can be shorter than the signals paths in <FIG>.

<FIG> are cross-sectional views of a semiconductor device, such as the device <NUM> and the like, at various intermediate steps of manufacturing, in accordance with exemplary embodiments of the disclosure. The device <NUM> can refer to any suitable device, for example, memory circuits, a semiconductor chip (or die) with memory circuits formed on the semiconductor chip, a semiconductor wafer with multiple semiconductor dies formed on the semiconductor wafer, a stack of semiconductor chips, a semiconductor package that includes one or more semiconductor chips assembled on a package substrate, and the like.

<FIG> shows a cross-sectional view of a semiconductor device <NUM> that will eventually become the device <NUM>. It should be understood that <FIG> only shows a portion of the device <NUM>. Similar to the device <NUM>, the device <NUM> includes a first die D1', which corresponds to the first die D1, and a second die (not shown), which corresponds to the second die D2, bonded together via a bonding interface (not shown), which corresponds to the bonding interface <NUM>. For simplicity, the bonding structures <NUM> and the cap layer <NUM> of the first die D1 in <FIG> are omitted in <FIG>.

As shown, the device <NUM> includes a substrate <NUM> (e.g., silicon) on a back side of the first die D1' and an etch stop layer <NUM> (e.g., silicon nitride) on a face side of the substrate <NUM>. The device <NUM> also includes an insulating layer <NUM> layer (e.g., silicon oxide), which will eventually become the insulating layer <NUM> in <FIG>, on the face side of the etch stop layer <NUM>.

As illustrated in <FIG>, the device <NUM> has components that are configured similarly to the corresponding components of the device <NUM> in <FIG>. For example, a first contact structure <NUM>, a semiconductor layer <NUM>, a stack of alternating insulating layers <NUM> and word line layers <NUM>, an array region <NUM>, a staircase region <NUM>, a channel structure <NUM>, a plurality of second contact structures <NUM>, and a third contact structure <NUM> are configured similarly to the first contact structure <NUM>, the semiconductor layer <NUM>, the stack of alternating insulating layers <NUM> and word line layers <NUM>, the array region <NUM>, the staircase region <NUM>, the channel structure <NUM>, the plurality of second contact structures <NUM>, and the third contact structure <NUM>, respectively. The descriptions of these components have been provided above and will be omitted here for clarity purpose.

<FIG> shows the device <NUM> in <FIG> after the substrate <NUM> is removed from the back side. Removal of the substrate <NUM> can be accomplished by chemical mechanical polishing (CMP) and/or wet etching. The etch stop layer <NUM> can be used to determine when the CMP and/or wet etching process should stop.

<FIG> shows the device <NUM> in <FIG> after the etch stop layer <NUM> and a portion of the first contact structure <NUM> is removed. Consequently, the remaining first contact structure <NUM> and the insulating layer <NUM> are exposed from the back side. Similar to <FIG>, removal of the etch stop layer <NUM> and the portion of the first contact structure <NUM> can be accomplished by a CMP process. Alternatively, the etch stop layer <NUM> can be removed by a first etching process, and the portion of the first contact structure <NUM> can be removed by a second etching process. In some embodiments, removal of the portion of the first contact structure <NUM> may not be necessary. As a result, the portion of the first contact structure <NUM> will be exposed (not shown). Further, while shown to extend into the etch stop layer <NUM>, the first contact structure <NUM>, in some embodiments, only extends to a back surface <NUM>' of the insulating layer <NUM> (not shown). Therefore, removal of any portion of the first contact structure <NUM> may not be necessary.

In <FIG>, contact holes <NUM> are formed in the insulating layer <NUM> of the device <NUM> so that a portion of the semiconductor layer <NUM> is exposed. A contact hole <NUM> can have a bottom <NUM>' and two sidewalls <NUM>". In the <FIG> example, two contact holes <NUM> are shown to have a trapezoid shape in cross-section that expands from the face side to the back side. It is understood that any number of contact holes <NUM> can be formed and that the contact holes <NUM> can have other shapes, such as a rectangle shape. The contact holes <NUM> can be formed by an etching process using a photoresist as an etching mask defined by a photolithography process.

In <FIG>, a second conductive layer <NUM> that will eventually become the second conductive layer <NUM> in <FIG> can be formed to conformally coat the exposed first contact structure <NUM>, the insulating layer <NUM>, and the exposed portion of the semiconductor layer <NUM>. As a result, the second conductive layer <NUM> covers the bottoms <NUM>' and sidewalls <NUM>" of the contact holes <NUM>. The second conductive layer <NUM> can be made of titanium and formed by chemical vapor deposition. The second conductive layer <NUM> can be have a thickness in the range of <NUM>-<NUM>. In some embodiments, the second conductive layer <NUM> may not be necessary so this step can be skipped.

In <FIG>, a first conductive layer <NUM> that will eventually become the first conductive layer <NUM> in <FIG> can be formed over the second conductive layer <NUM> from the back side so that the contact holes <NUM> can be filled with the first conductive layer <NUM>. The first conductive layer <NUM> can be a conductive layer made of aluminum and formed by chemical vapor deposition. In an example where the second conductive layer <NUM> is titanium and the semiconductor layer <NUM> is polysilicon, titanium can be an adhesion layer between aluminum and polysilicon. Additionally, recess structures <NUM> can be formed on the back side of the first conductive layer <NUM> as a result of the contact holes <NUM>.

<FIG> shows the device <NUM> in <FIG> after removing portions of the first conductive layer <NUM> and portions of the second conductive layer <NUM>. Removal of the portions of the first conductive layer <NUM> and the portions of the second conductive layer <NUM> can be accomplished by etching with photoresist and/or hard mask layers. Consequently, a first portion of the first conductive layer 271a can be disposed over a first portion of the second conductive layer 261a to form a first pad-out structure, and a second portion of the first conductive layer 271b can be disposed over a second portion of the second conductive layer 261b to form a second pad-out structure. Similar to the device <NUM>, external circuitry (not shown) can provide a control signal to and receive data from peripheral circuitry (not shown) of the second die D2' of the device <NUM> via the first pad-out structure (271a and 261a) that is coupled with the peripheral circuitry via the first contact structure <NUM>. The peripheral circuitry can then interact with the transistors of the first die D1'.

<FIG> is a flow chart of an exemplary process <NUM> for manufacturing an exemplary semiconductor device, such as the device <NUM> in <FIG>, the device <NUM> in <FIG>, and the like, in accordance with embodiments of the disclosure. The process <NUM> starts with step S901 where a first die and a second die is bonded face to face (a circuitry side is face, and a substrate side is back). The first die includes a first substrate, first transistors formed on a face side of the first die in a semiconductor layer with an insulating layer between the first substrate and the semiconductor layer, and a first contact structure on the face side of the first die that extends through the insulating layer. The second die can include a second substrate with structures formed on a face side of the second die.

In order to bond the first die to the second die, a plurality of first bonding structures, such as pillars, can be formed on the face side of the first die, and a plurality of second bonding structures can be formed on the face side of the second die. The bonding structures can include Cu, Ni, and SnAg. The bonding process can be operated at a temperature over <NUM> for the bonding structures to melt so that a first bonding structure can form a connection with a corresponding second bonding structure. Consequently, the first transistors in the first die can be coupled with structures in the second die via corresponding bonding structures at the bonding interface and contact structures in the two dies.

Further, the first transistors can form vertical memory cell strings, and the second die can include peripheral circuitry as shown in the <FIG> example. In alternative embodiments, the first transistors can include peripheral circuitry, and the second die can include memory cells.

At step S902, the first substrate is removed from the back side of the first die to expose the first contact structure from the back side of the first die. As a result, the insulating layer is also exposed from the back side of the first die. An etch stop layer is sandwiched between the first substrate and the insulating layer and the etch stop layer is also removed from the back side of the first die. Removal of the first substrate and etch stop layer can be accomplished by CMP and/or etching.

At step S903, a contact hole that exposes a portion of the semiconductor layer is formed in the insulating layer from the back side of the first die. The contact hole has a bottom and two sidewalls. Photolithography technology can be used to define a channel hole pattern in photoresist and/or hard mask layers, and etch technology can be used to transfer the pattern to the insulating layer and then remove the photoresist and/or hard mask layers.

At step S904, a first pad-out structure and a second pad-out structure are formed on the back side of the first die. The first pad-out structure and the second pad-out structure by two deposition processes, a photolithography process, and two etching processes. To begin with, a conformal liner layer can be formed by a first deposition process so that the liner layer covers the exposed first contact structure, the insulating layer, and the exposed portion of the semiconductor layer. The liner layer can also cover the bottom and sidewalls of the contact hole. Then, a pad layer can be formed over the liner layer from the back side by a second deposition process. The pad layer can fill the contact hole and form a recess structure on the back side as a result of the contact hole. Subsequently, a photolithography process can be performed to define a pad-out pattern of photoresist and/or hard mask layers that serve as an etching mask. Next, two etching processes can be performed to transfer the pad-out pattern to the pad layer and the liner layer to form the first pad-out structure and the second pad-out structure. In some embodiments, the two etching processes can be replaced by a single etching process. Additionally, the photoresist and/or hard mask layers will be removed.

As a result, the first pad-out structure is conductively connected to the first contact structure, with a first portion of the liner layer sandwiched in between. External circuitry can be coupled with the peripheral circuitry of the device via the first pad-out structure and the first contact structure. Similarly, the second pad-out structure is formed on the contact hole and conductively connected to the semiconductor layer, with a second portion of the liner layer sandwiched in between. The second pad-out structure can be configured to provide a common source array for the memory cells.

Further, in an example where the pad-out structures are aluminum and the semiconductor layer is polysilicon, the liner layer can be made of an adhesion material, such as titanium. In other examples, the pad-out structures can be made of other conductive materials, and the liner layer can be a barrier layer, a seed layer, and/or an adhesion layer. The liner layer can also be used to reduce contact resistance. In some embodiments, the liner layer may not be necessary.

It should be noted that additional steps can be provided before, during, and after the process <NUM>, and some of the steps described can be replaced, eliminated, or performed in a different order for additional embodiments of the process <NUM>. For example, formation of the liner layer may not be necessary. At step S904 in particular, the pad layer having a recess structure can be planarized by a CMP process, prior to the photolithography process that defines the etching mask. Consequently, the pad-out structures will have flat surfaces on the back side. Additionally, a lift-off process where a photolithography process is performed prior to deposition of the liner layer and the pad layer can also be used to form the pad-out structures.

Claim 1:
A method for fabricating a semiconductor device (<NUM>, <NUM>), comprising:
bonding a first die (D1, D1') and a second die (D2) face to face, the first die (D1, D1') including a first substrate, an insulating layer (<NUM>, <NUM>) on a face side of the first substrate, a first contact structure (<NUM>, <NUM>) on the face side of the first die (D1, D1') extending through a first portion (161a) of the insulating layer (<NUM>, <NUM>), and a semiconductor layer (<NUM>, <NUM>) on a face side of a second portion (161b) of the insulating layer (<NUM>, <NUM>) and first transistors (<NUM>) formed on a face side of the semiconductor layer (<NUM>, <NUM>);
exposing the first contact structure (<NUM>, <NUM>) from the back side of the first die (D1, D1') by removing the first substrate from a back side of the first die (D1, D1');
forming, from the back side of the first die (D1, D1'), a contact hole (<NUM>) in the second portion (161b) of the insulating layer (<NUM>, <NUM>), the contact hole (<NUM>) exposing the semiconductor layer (<NUM>, <NUM>); and
forming, on the back side of the first die (D1, D1'), a first pad-out structure (171a, 161a) conductively connected with the first contact structure (<NUM>, <NUM>) and a second pad-out structure (171b, 161b) on the contact hole (<NUM>) that is conductively connected with the semiconductor layer (<NUM>, <NUM>), wherein exposing the first contact structure (<NUM>, <NUM>) from the back side of the first die (D1, D1') further comprises:
removing an etch stop layer (<NUM>) after removing the first substrate, the etch stop layer (<NUM>) being sandwiched between the first substrate and the insulating layer (<NUM>, <NUM>).