Patent Description:
A photonic chip and an electrical chip can be wire bonded to a shared substrate and/or to each other. However, using wire bonding to connect the photonic chip and the electrical chip to a shared substrate requires the use of external ceramics or Ball Grid Array (BGA) substrates with Vertical Interconnect Accesses (VIAs), which is not desired for achieving dense integration with other Application-Specific Integrated Circuits (ASICs). Also, using wire bonding to connect the photonic chip and the electrical chip with a shared substrate requires that the Input/Output (I/O) interfaces are arranged on the top surface of the photonic chip, which limits the number of I/O interfaces. Also, such wire bonded interconnections can cause several issues in signal integrity for Photonic high speed transmissions (e.g., ><NUM> Gigabits/second) related to parasitic capacitance, mutual inductance and impedance mismatches with the rest of the on-chip and on-substrate circuits. Furthermore, solutions that connect the photonic chip to the electrical chip without wire bonding often require large, and expensive-to-produce, photonic chips to provide sufficiently large surface areas needed to establish connections between the chips and the shared substrate. Prior art optoelectronic assemblies are disclosed in <CIT>, <CIT>, and <CIT>. Prior art embedded electronic chips and interposers are disclosed in <CIT>.

One embodiment presented in this disclosure provides an optoelectronic assembly that comprises: a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, the PIC having a face that is exposed from the mold compound; an interposer embedded in the mold compound, the interposer having a face that is exposed from the mold compound and is co-planar with the face of the PIC; and an electrical integrated circuit (EIC) coupled to the face of the PIC exposed from the mold compound and to the face of the interposer exposed from the mold compound, the EIC comprising bridging electrical connections between the PIC and the interposer.

Another embodiment presented in this disclosure provides reconstituted wafer, comprising: a mold compound; a plurality of dies embedded of in the mold compound, each die of the plurality of dies including: a Photonic Integrated Circuit (PIC) embedded in the mold compound, having an exposed face free of the mold compound; an interposer embedded in the mold compound, having a first face free of the mold compound that is coplanar to the exposed face of the PIC, and having a second face free of the mold compound that is opposite to the first face; and an Electrical Integrated Circuit (EIC) connected to a portion of the exposed face of the PIC and to a portion of the first face of the interposer.

In a further embodiment presented in this disclosure, a method of fabricating optoelectronic assemblies is provided, the method comprising: positioning a Photonic Integrated Circuit (PIC) and an interposer on a carrier, wherein the PIC has an exposed face and the interposer has a first face coplanar with the exposed face; encapsulating the PIC and the interposer using a mold compound to form a reconstituted wafer including the PIC and the interposer, the reconstituted wafer having a first side coplanar with the exposed face and a second side opposite to the first side, wherein the mold compound does not cover the exposed face and the first face; removing a portion of the mold compound from the second side to reveal a portion of the interposer opposite to the first face; and bonding an Electrical Integrated Circuit (EIC) with the PIC face and the interposer face to electrically bridge the PIC and the interposer.

Integrated Circuits (IC) of various types are made of various materials with various physical properties, costs of manufacture, and intended uses. A Photonic IC (PIC) is designed to perform optical operations, such as, for example, to convert optical signals to or from electrical signals as part of a fiber optic system. An Electric IC (EIC) is designed to perform operations using electrical signal, and may be coupled with a PIC to deliver electrical data signals to modulate optical signals, receive converted optical signals as electrical signals to analyze or pass to other circuits, or provide power to the PIC for the analysis or conversion of optical signals to or from electrical signals. PICs are typically made of materials with higher electrical parasitic properties and have higher production costs than a comparable EIC, and therefore optoelectronic assemblies use an EIC in combination with a PIC to perform integrated optical and electronic processing to reduce cost and improve performance efficiencies. Smaller PICs provide greater savings in costs and performance efficiencies relative to larger PICs in optoelectronic assemblies, but PICs should be large enough to incorporate optical interconnects (e.g., for fiber optic cables) and electrical interconnects to receive and transmit electrical signals to and from an associated EIC.

In one embodiment, a PIC and an EIC are coupled with each other to form an optoelectronic assembly using a fan-out wafer level integration in which an interposer substrate and the PIC are embedded together to establish a coplanar topsurface on which an EIC bridges the PIC with electrical connections in the interposer substrate. This embodiment allows for the use of smaller, easier to produce, less expensive PICs that do not need to provide surface area for wire bonding or large EIC attach areas.

<FIG> illustrates a side view of an example optoelectronic assembly <NUM> according to one embodiment of the present disclosure. The example optoelectronic assembly <NUM> illustrated includes a mold compound <NUM> that embeds a PIC <NUM>, an interposer <NUM>, and a constructed VIA <NUM> embedded therein. An EIC <NUM> is coupled to both the PIC <NUM> and the interposer <NUM> using pillar bumps <NUM>. In one embodiment, the EIC <NUM> serves as an electrical bridge between the PIC <NUM> and the interposer <NUM> that is disposed on one side of the optoelectronic assembly <NUM>. An array of external connections <NUM> are mounted on the other side of the optoelectronic assembly <NUM> from the EIC <NUM> via Input/Output (I/O) pads <NUM>. In some embodiments, various passive components <NUM> are also encased in the mold compound <NUM>.

In one embodiment, the mold compound <NUM> is any epoxy or substrate used to fabricate a reconstituted wafer. The reconstituted wafer includes the PIC <NUM> to provide an optical interface to send and/or receive optical signal from/to the optoelectronic assembly <NUM> via an external optical device (not illustrated). Examples of external optical devices include, but are not limited to, lasers, photodiodes, fiber optic cables, lenses, prisms, isolators, optical MUX/DMUX devices, and the like that are connected with the optical interface in the PIC <NUM>. In various embodiments, the PIC <NUM> may be connected to external optical devices via evanescent coupling, edge coupling, butt coupling, grating coupling, etc..

The PIC <NUM> defines a first face (e.g., an exposed face <NUM>) that extends from or is otherwise not covered by the mold compound <NUM> used to capture the PIC <NUM>. This exposed face <NUM> includes a first portion <NUM> that is used for coupling with the external optical device and a second portion <NUM> used for coupling with the EIC <NUM>, the interposer <NUM>, and passive components <NUM>. In one embodiment, the PIC <NUM> includes a second exposed face <NUM> in an intersecting plane to the first exposed face <NUM>, such as the perpendicular second exposed face <NUM> illustrated in <FIG>. However, in another embodiment, the second exposed face <NUM> may be in a plane parallel to the first exposed face <NUM> (i.e., opposite to the exposed face <NUM>). The second exposed face <NUM> may be used for coupling to external electrical devices, external optical devices, the interposer <NUM>, passive components <NUM>, or left free of optical or electrical connections. In embodiments falling within the scope of the appended claims, a reflective coating is applied to the second exposed face <NUM>.

The interposer <NUM> provides a platform to which the EIC <NUM> is mounted, and to which other components of the optoelectronic assembly <NUM> connect to the EIC <NUM>. The interposer <NUM> defines a first face <NUM> that extends from or is otherwise not covered by the mold compound <NUM> used to capture the interposer <NUM>, and is coplanar with the exposed face <NUM> of the PIC <NUM>. Because the exposed face <NUM> of the PIC <NUM> and the first face <NUM> of the interposer <NUM> are both in one shared plane, the EIC <NUM> can evenly mount to both the PIC <NUM> and the interposer <NUM>. In some embodiments, a second face <NUM> of the interposer <NUM>, opposite to the first face <NUM>, is exposed on an opposite side of the optoelectronic assembly <NUM>, while in other embodiments, the second face <NUM> is encased in the mold compound <NUM>.

The interposer <NUM> can be constructed of silicon, glass, ceramic, or an organic substrate that acts as a low parasitic loss electrical conduit between the EIC <NUM> and a Printer Circuit Board (PCB) that provides a rigid interface for flip chip bonding of the EIC <NUM> to the interposer <NUM>. The interposer <NUM> may contain electrical components, optical components, both electrical components and optical components, or neither electrical nor optical components to support the PIC <NUM>.

The coefficient of thermal expansion (CTE) of the mold compound <NUM> is designed as close to that of the PIC <NUM> and interposer <NUM> as possible, to allow for very low warpage or flexing of the molded package. The warpage, however, can also be managed by controlling the volume percentage of the interposer <NUM> and PIC <NUM> (both with lower CTEs) compared to the mold compound <NUM> (generally higher CTE). For example, making sure that <NUM>-<NUM>% of the volume of the package is occupied by the PIC <NUM> and the interposer <NUM> will help lower the impact of a mold compound <NUM> with a high CTE (due to rule of mixtures), and will thus lower the warpage of the entire package significantly. Controlling the flexing or warpage of the molded package is important to obtain a reliable flip chip bond with the EIC <NUM>, since the EIC <NUM> is bonded to both PIC <NUM> and Interposer <NUM>, which are embedded in the mold compound <NUM> of the molded package. After flip chip bonding the EIC <NUM> to the molded package, the overall warpage of the package further improves due to EIC <NUM> acting as a rigid bridge between the PIC <NUM> and interposer <NUM> and also increasing the Silicon volume percentage (Silicon having a low CTE) of the entire package. This further helps in surface mounting the molded package to an external PCB for example.

In some embodiments, a first Redistribution Layer (RDL) <NUM> is formed as part of a fan-out wafer process to extend electrical contacts on the top side of the optoelectronic assembly <NUM> from the various constructed VIAs <NUM> and passive components <NUM> to one another, to the first face <NUM> of the interposer <NUM>, and to the first portion of the exposed face <NUM> of the PIC <NUM>. Additionally, electrical connections between the interposer <NUM> and the PIC <NUM> may also be established in the first RDL <NUM>. A second RDL <NUM> is formed in additional embodiments as part of a fan-out wafer process to extend electrical contacts and create I/O pads <NUM> on the bottom side of the optoelectronic assembly <NUM>. As will be appreciated, the RDL may be fabricated according to various photolithography processes and any I/O pads may be fabricated with Under Bump Metallization (UBM) or another metallization process known to those of skill in the art. In some embodiments, the first portion <NUM> of the exposed face <NUM> is treated with a photoresist to prevent an RDL from forming over the first portion <NUM>. This photoresist is then removed as the final step of the molded package process, thereby exposing the top surface of the PIC <NUM> meant for optical attach to other components, thereby maintaining the ability of the first portion <NUM> to couple with external optical devices.

The EIC <NUM> is a chip for processing electrical signals. These signals may include analog and digital signals that are transmitted to or received from the PIC <NUM>, or transmitted to or received from external electrical components (not illustrated) in communication with the optoelectronic assembly <NUM>. The EIC <NUM> is connected to the PIC <NUM> and the interposer <NUM> via pillar bumps <NUM>. In various embodiments, the pillar bumps <NUM> are pins that extend from the EIC <NUM> to couple with contact pads or sockets on the PIC <NUM> and the interposer <NUM>. In other embodiments, the pillar bumps <NUM> are pins that extend from the PIC <NUM> and the interposer <NUM> to couple with contact pads or sockets on the EIC <NUM>.

The constructed VIA <NUM> provides an electrical pathway between the bottom side of the optoelectronic assembly <NUM> and the top side of the optoelectronic assembly <NUM>. One or more constructed VIAs <NUM> may be present in the optoelectronic assembly <NUM>, and each constructed VIA <NUM> may include one or more pathways from the bottom side to the top side of the optoelectronic assembly <NUM>. As used in the present disclosure, "top," "top side," and related terms refer to the side of the optoelectronic assembly <NUM> that the EIC <NUM> is to be mounted. Similarly, the present disclosures uses the terms "bottom," "bottom side," and related terms to refer to the opposite side of the optoelectronic assembly <NUM>, where external connections <NUM> are arranged in an array to enable the optoelectronic assembly to mount or couple with other electrical components. In various aspects, the external connections <NUM> are solder balls that are part of a Ball Grid Array (BGA) or may be pins or sockets that are part of a Land Grid Array (LGA). The external connections <NUM> are mounted to the bottom side of the optoelectronic assembly <NUM> by one or more I/O pads <NUM> fabricated on the bottom side. In various embodiments, the I/O pads <NUM> are fabricated on the bottom side of the optoelectronic assembly <NUM> as part of an RDL.

The passive components <NUM> can be discrete components, such as capacitors and resistors, that are optionally embedded in the mold compound <NUM>. The passive components <NUM> may be in electrical communication with the PIC <NUM>, the interposer <NUM>, the constructed VIAs <NUM>, the EIC <NUM>, and other passive components <NUM>. Although illustrations given in the present disclosure typically show one or fewer passive components <NUM>, it will be appreciated that more passive components <NUM> may be included in various embodiments made according to the present disclosure.

<FIG> illustrates a side view of an example optoelectronic assembly <NUM> highlighting internal VIAs <NUM> in the interposer <NUM>. In this example, the constructed VIAs <NUM> are discrete components that are embedded in the mold compound <NUM>, but VIAs may also be fabricated through the material of the interposer <NUM>. The internal VIAs <NUM> provide an electrical pathway through the optoelectronic assembly <NUM> between the external connections <NUM> and I/O pads <NUM>, to the EIC <NUM> via the pillar bumps <NUM>. The EIC <NUM>, in turn, is electrically connected to the PIC <NUM> via other connectors within the pillar bumps.

In some embodiments in which the interposer <NUM> includes internal VIAs <NUM>, the constructed VIAs <NUM> are omitted. In other embodiments in which the interposer <NUM> includes internal VIAs <NUM>, the constructed VIAs <NUM> are included to provide additional pathways through the optoelectronic assembly <NUM> to the pathways provided by the internal VIAs <NUM>. The internal VIAs <NUM> may be constructed in the interposer <NUM> prior to integration in the optoelectronic assembly <NUM> (e.g., through-silicon VIA interposers) or as part of the chemical vapor deposition or metallization steps in a fan-out process on a reconstituted wafer including one or more optoelectronic assemblies <NUM>.

<FIG> and <FIG> illustrate top views of example optoelectronic assemblies <NUM> according to embodiments of the present disclosure. Both <FIG> and <FIG> illustrate a first constructed VIA 140a and a second constructed VIA 140b connected with an interposer <NUM> and a passive component <NUM>, all embedded in a mold compound <NUM>. Each optoelectronic assembly <NUM> also includes an EIC <NUM> connected with the interposer, but <FIG> shows the EIC <NUM> connected to one PIC <NUM>, whereas <FIG> shows the EIC <NUM> connected to a first PIC 120a and to a second PIC 120b. It will therefore be understood that a given EIC <NUM> may be connected to a plurality of PICs <NUM>.

In various embodiments, an EIC <NUM> may be connected to multiple PICs <NUM> to receive or transmit optical signals according to different power levels, having different wavelengths, to receive or transmit optical signals from multiple sources or to multiple destinations via dedicated cabling, For example, an EIC <NUM> may receive optical signals via a first PIC 120a, and control transmission of optical signals via a second PIC 120b. In another example, the optoelectronic assembly <NUM> may receive signals of a first wavelength via a first PIC 120a and signals of a second wavelength via a second PIC 120b.

<FIG> and <FIG> illustrate top views of example optoelectronic assemblies <NUM> using two EIC <NUM> according to embodiments of the present disclosure. Both <FIG> and <FIG> illustrate an interposer <NUM> and various PICs <NUM> embedded in a mold compound <NUM>. <FIG> illustrates a first EIC 150a and a second EIC 150b connected with the interposer <NUM> and one PIC <NUM>. <FIG> illustrates a first EIC 150a connected with the interposer <NUM> and a first PIC 120a, and a second EIC 150b connected with the interposer <NUM>, a second PIC 120b, and a third PIC 120c. In will therefore be understood that a given interposer <NUM> may be connected with a plurality of EIC <NUM>, each of which may be connected to one or more PICs <NUM>. Each of the several EIC <NUM> connected to an interposer <NUM> may be electrically connected with one another via the interposer <NUM>, or may be isolated from one another. As will be appreciated, an EIC <NUM> may be connected to more than one interposer <NUM>.

In various embodiments, an interposer <NUM> is connected to multiple EICs <NUM> to perform various functions. For example, a first EIC 150a and a second EIC 150b may be connected to a given PIC <NUM> to process the signals provided by the PIC <NUM> differently, such as via a first EIC 150a that processes analog signals and a second EIC 150b that processes digital signals. In another example, a first EIC 150a drives transmissions sent from a first PIC 120a, and a second EIC 150b processes signals received from a second PIC 120b. Additionally, a manufacturer may make use of several EICs <NUM> (instead of a smaller number of EICs <NUM>) to fit pre-existing form factors of EIC <NUM> or use several EICs <NUM> whose cost of manufacture is less than a single EIC <NUM>.

<FIG> and <FIG> illustrate a top view and a side view, respectively, of an example optoelectronic assembly <NUM> using a first bridge EIC 150a and a second mounted EIC 150b according to one embodiment of the present disclosure. In <FIG> and <FIG>, an interposer <NUM> and a PIC <NUM> embedded in a mold compound <NUM> are bridged by a first EIC 150a, and a second EIC 150b is mounted to the interposer <NUM>. It will therefore be appreciated that an optoelectronic assembly <NUM> may include EICs <NUM> that do not bridge a PIC <NUM> with the interposer <NUM>. The EICs <NUM> that are mounted to the interposer <NUM> are not directly electrically connected with a PIC <NUM>. In some embodiments, these mounted EICs <NUM> are connected to other EICs <NUM>, which may be directly interconnected with a PIC <NUM>. Mounted EICs <NUM> may also be connected to constructed VIAs <NUM> or passive components <NUM> of the optoelectronic assembly, or may be connected to an external electrical device.

<FIG> illustrates a flow chart outlining general operations in an example method <NUM> to fabricate optoelectronic assemblies <NUM> according to one embodiment of the present disclosure. Method <NUM> is discussed in relation to examples of various sub-assemblies created during fabrication of optoelectronic assemblies <NUM> illustrated in <FIG>.

Method <NUM> begins with block <NUM>, where a reconstituted wafer is formed to include at least one die for an optoelectronic assembly <NUM> that includes at least one PIC <NUM> and at least one interposer <NUM>. In various embodiments, constructed VIAs <NUM> and passive components <NUM> are also included in the at least one die. The various PICs <NUM>, interposers <NUM>, (optional) constructed VIAs <NUM>, and (optional) passive components <NUM> may be disposed on a carrier <NUM>, as is illustrated in <FIG>, and then embedded in a mold compound <NUM>, as is illustrated in <FIG>. It should be noted that additional protective layers may be added to the PIC <NUM> (or included in the PIC design) in order to keep mold compound <NUM> out of designated areas. For example, to protect optical coupling interfaces, structures such as trenches, protective/sacrificial layers, or other barriers may be added to keep mold compound <NUM> away from these areas or otherwise allow for the removal of the mold compound <NUM> without damage to the PIC <NUM>.

The carrier <NUM> is in contact with what will be the exposed face <NUM> of the PIC <NUM> and the first face <NUM> of the interposer <NUM>, which ensures that the exposed face <NUM> and the first face <NUM> are co-planar (i.e., disposed in one plane), are on one side of the final optoelectronic assembly <NUM> (i.e., the top side), and are free of the mold compound <NUM>. In contrast, the bottom surfaces of the components of the optoelectronic assembly <NUM> face away from the carrier <NUM>. The carrier <NUM> may be a tape or a steel carrier, as is understood in the art, to which the components of the optoelectronic assembly <NUM> (including the mold compound <NUM>) are temporarily bonded. Once the mold compound <NUM> used to form the reconstituted wafer is set, and the interposer <NUM> and PIC <NUM> are embedded therein, the carrier <NUM> may be removed using a wet etch, laser release, physical peeling, or chemical release process.

Once the carrier <NUM> has been removed, surface feature processing may be performed on the exposed face <NUM>, first face <NUM>, and other faces/surfaces in the plane shared thereby (e.g., on the top side of the optoelectronic assembly <NUM>. For example, chemical vapor deposition, electroplating or a similar process may add solder pads or pins for connection via pillar bumps <NUM>, or may fan out electrical connections in an RDL between any constructed VIAs <NUM>, interposers <NUM>, PICs <NUM>, and/or passive components <NUM>.

Returning to the method <NUM>, at block <NUM>, a portion of the mold compound <NUM> is removed from the "bottom" side of the reconstituted wafer opposite to the side previously bonded with the carrier <NUM>. In some embodiments, sufficient mold compound <NUM> is removed to expose any constructed VIAs <NUM> and/or a second face <NUM> of the interposer <NUM> that extend to the bottom side of the optoelectronic assembly <NUM>; leaving an exposed bottom surface on the optoelectronic assembly <NUM>. For example, the mold compound <NUM> shown in <FIG> may be removed from the bottom side to result in the in-process optoelectronic assembly shown in <FIG>. In other embodiments, the amount of mold compound <NUM> that is removed is such that the second face <NUM> of the interposer <NUM> is not exposed on the bottom side of the optoelectronic assembly <NUM>. For example, the optoelectronic assembly <NUM> shown in <FIG> illustrates a completed optoelectronic assembly <NUM> that includes mold compound <NUM> between the second face <NUM> of the interposer <NUM> and the bottom side of the optoelectronic assembly <NUM> (as well as between the bottom surface of the PIC <NUM> and the bottom side of the optoelectronic assembly <NUM>), where the external connections <NUM> are attached. As will be appreciated, due to thinner substrates being more vulnerable to cracking, the thickness of the mold compound <NUM>, and whether the interposer <NUM> or PIC <NUM> are exposed on both the top and the bottom sides, may be determined based on the desired mechanical properties of the final optoelectronic assembly.

At block <NUM>, an RDL is formed on the bottom side of the reconstituted wafer to form I/O pads <NUM>. In various aspects, the I/O pads <NUM> are fabricated in electrical communication with any constructed VIAs <NUM> or integrated VIAs <NUM> present on the reconstituted wafer, but may also be fabricated at points that are electrically isolated (e.g., to maintain a pattern or provide physical-only connection points) or to electrically connect other components on the bottom side of the optoelectronic assembly <NUM>.

An example of the in-progress optoelectronic assembly <NUM> with an RDL layer formed on the bottom side is illustrated in <FIG> shows the top surface of the optoelectronic assembly <NUM> free of the mold compound <NUM>, from which the first face <NUM> of the interposer <NUM> and the exposed face <NUM> of the PIC <NUM> extend in one plane along with a portion of a constructed VIA <NUM> and a passive component <NUM> (which may be coplanar or not coplanar). <FIG> also shows the bottom side of the optoelectronic assembly <NUM> with several I/O pads <NUM> fabricated thereon.

Additionally, in some embodiments, an RDL is also formed on the top side of the reconstituted wafer at block <NUM> to form solder pads (or other I/O connections, such as sockets or pins) and/or to fan out electrical connections between the components having an exposed surface on the top side of the reconstituted wafer, such as, for example, the interposer <NUM> and the PIC <NUM>. An example of the in-progress optoelectronic assembly <NUM> with an RDL layer formed on the bottom side and a second RDL layer formed on the top side is illustrated in <FIG> shows the top surface of the optoelectronic assembly <NUM> free of the mold compound <NUM>, from which the first face <NUM> of the interposer <NUM> and the exposed face <NUM> of the PIC <NUM> extend in one plane along with a portion of a constructed VIA <NUM> and a passive component <NUM> (which may be coplanar or not coplanar). <FIG> also shows the bottom side of the optoelectronic assembly <NUM> with several I/O pads <NUM> fabricated thereon and several I/O pads <NUM> formed on the first face <NUM> of the interposer <NUM> and the exposed face <NUM> of the PIC <NUM>. In some aspects, the I/O pads <NUM> are formed on one or more of the first face <NUM> of the interposer <NUM> and the exposed face <NUM> of the PIC <NUM> prior to forming the reconstituted wafer.

An EIC <NUM> is bonded to the interposer <NUM> and the PIC <NUM> at block <NUM>, an illustration of which is shown in <FIG>. The EIC <NUM> is coupled with the interposer <NUM> and the PIC <NUM> via pillar bumps <NUM> established between the EIC <NUM> and the I/O pads on the first face <NUM> of the interposer <NUM> and the exposed face <NUM> of the PIC <NUM>.

Proceeding to block <NUM>, external connections <NUM> are mounted on the bottom side of the optoelectronic assembly <NUM>. In various embodiments, the external connections <NUM> include a BGA of solder balls to electrically and physically couple the optoelectronic assembly <NUM> to an external electrical device, as is illustrated in <FIG>. In other embodiments, the external connections <NUM> include the pins or sockets of an LGA.

At block <NUM> the reconstituted wafer is diced into one or more optoelectronic assemblies <NUM> having a predefined shape. <FIG> illustrates a top view of a pre-diced reconstituted wafer <NUM> including several dies of optoelectronic assemblies <NUM>. As shown in <FIG>, each die includes a co-planer PIC <NUM> and interposer <NUM> embedded in the mold compound <NUM>, and an EIC <NUM> couple with the PIC and the interposer <NUM> as shown in greater detail in regard to <FIG> illustrates a top view of one optoelectronic assembly <NUM> and several dice lines <NUM> at which to cut the surrounding mold compound <NUM> of the pre-diced reconstituted wafer <NUM> away from the mold compound <NUM> and other components of the optoelectronic assembly <NUM>. The optoelectronic assembly <NUM> is ready to be coupled with an external electrical device (e.g., via the external connections <NUM>) and to an external optical device (e.g., via the first portion <NUM> of the exposed face <NUM> of the PIC <NUM>). Note that in order to facilitate coupling between the PIC <NUM> and external optical components, the dicing process may be modified based on the PIC design and intended use profile. For example, if it is desired to couple optical components to the edge of the PIC <NUM>, portions of the PIC <NUM> may be designed such that part of the PIC <NUM> is cut away during this final dicing step to provide an exposed face <NUM> as an optical surface for coupling.

In summary, an optoelectronic assembly and methods of fabrication thereof are provided. Embodiments of the assembly include a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

Embodiments of the present disclosure are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments presented in this disclosure.

These computer program instructions may also be stored in a computer readable storage medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable storage medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some other implementations, the functions noted in the block may occur out of the order noted in the figures.

Claim 1:
An optoelectronic assembly (<NUM>), comprising:
a mold compound (<NUM>);
a photonic integrated circuit, PIC (<NUM>), embedded in the mold compound (<NUM>), the PIC (<NUM>) having:
a first face (<NUM>) that is exposed from the mold compound, the face (<NUM>) of the PIC (<NUM>) including electrical contacts comprising pins or contact pads or sockets, and
a second face (<NUM>) perpendicular to the first face (<NUM>), including a reflecting coating;
an interposer (<NUM>) embedded in the mold compound (<NUM>), the interposer (<NUM>) having a face (<NUM>) that is exposed from the mold compound (<NUM>) and is co-planar with the face (<NUM>) of the PIC (<NUM>), the face (<NUM>) of the interposer (<NUM>) having electrical contacts comprising pins or contact pads or sockets; and
an electrical integrated circuit, EIC (<NUM>), having electrical contacts comprising contact pads or sockets or pins configured to form pillar bumps (<NUM>) when electrically coupled to the electrical contacts on the face (<NUM>) of the PIC (<NUM>) exposed from the mold compound (<NUM>) and to the electrical contacts on the face (<NUM>) of the interposer (<NUM>) exposed from the mold compound (<NUM>), the EIC (<NUM>) comprising bridging electrical connections between the PIC (<NUM>) and the interposer (<NUM>).