Patent Description:
Instruction set architectures (ISAs) define the instructions that can be executed by a processor. Most ISAs have a relatively small instruction size (e.g., four bytes). In some cases, it is desired to use an immediate value (i.e., a value that is stored as part of an instruction itself rather than as a pointer to a memory location or register) that is larger than the instruction size defined by the ISA. For example, in an ISA having a four byte instruction length, for a move immediate instruction (e.g., "movi register, immediate," where "movi" is the opcode of the instruction, "immediate" is an immediate operand specifying an immediate value, and "register" is a register operand specifying the register that will be updated with the immediate value), one byte is reserved for the opcode and one byte is reserved for the register operand, leaving only two bytes for the immediate operand. In this example, immediate values with a length over two bytes in length cannot be stored in the instruction itself. As another example, in the same ISA having a four byte instruction length, for a branch to immediate offset instruction (e.g., "bri immediate," where "bri" is the opcode of the instruction and "immediate" is an immediate operand specifying the offset value to jump to) one byte is reserved for the opcode, leaving only three bytes for the immediate operand. In this example, immediate values with a length over three bytes cannot be stored in the instruction itself. Where an immediate value is too large to be stored in an instruction because it is too large to fit in the allotted space provided by the instruction as dictated by the ISA, it is defined herein as a wide immediate.

Instructions including wide immediate operands are conventionally handled by software. For example, in one approach for move immediate instructions having wide immediate operands, the wide immediate operands are embedded in a program binary and the instruction with the wide immediate operand is replaced with a load instruction. Accordingly, a move immediate instruction as follows:
movi r0, 0xBADDF00DDEADCAFE
may be altered such that the wide immediate operand is stored in the program binary (at memory location 0xF9 when the binary is loaded into memory in the present example) and the move immediate instruction becomes:
ldr r0, [0xF9]
This can be done either explicitly by a developer of the program or by a compiler at compile time. Notably, any instructions that are dependent on the move immediate instruction must wait for the wide immediate operand to be loaded from memory before they can be processed. This may take several processing cycles and thus increase the execution time of a program binary.

In another approach for move immediate instructions having wide immediate operands, the instructions are replaced with a sequence of instructions including shift left instructions (shl) and add immediate instructions (addi). Accordingly, the same move immediate instruction as above:
movi r0, 0xBADDF00DDEADCAFE
may be altered to become:.

Again, this can be done either explicitly by a developer of the program or by a compiler at compile time.

As another example, in one approach for branch to immediate offset instructions having a wide immediate operand, multiple branches, each having immediate operands that fit within the instruction length of the ISA, may be chained together to finally arrive at the offset indicated by the wide immediate operand. Such an approach causes multiple control flow redirections and thus consumes additional processor resources. In another approach for branch to immediate offset instructions having a wide immediate operand, an indirect branch may be used to arrive at the offset indicated by the wide immediate operand. Indirect branches occupy space in branch prediction circuitry of the processor, and in the present case in which there is one target that is <NUM>% predictable, occupying this space in the branch prediction circuitry is wasteful.

In all of the examples discussed above, there is a relatively large overhead incurred for processing instructions having wide immediate operands such that the performance of binary execution is reduced. Accordingly, there is a need for improved systems and methods for processing instructions having wide immediate operands. <CIT> describes a hardware-software co-designed processor includes a front end to decode an instruction, an execution unit to execute the instruction, an auxiliary cache to store auxiliary information for consumption during execution of the instruction, an instruction blender, and a retirement unit to retire the instruction. The auxiliary information may include long immediate values, non-working instructions for emulating an untranslated instruction stream, or execution hints, and is not decoded by the front end. The auxiliary cache includes circuitry to receive the auxiliary information from a binary translator, to store the auxiliary information in the auxiliary cache, and to provide the auxiliary information to the instruction blender prior to execution. The instruction blender includes circuitry to receive the auxiliary information, to blend the instruction with the auxiliary information, and to provide the blended instruction to the execution unit. Use of the auxiliary cache may reduce fetch and decode bandwidth requirements.

Exemplary aspects of the present disclosure are related to improved systems and methods for processing instructions having wide immediate values. In this regard, in one exemplary aspect, a processor element in a processor-based system is configured to fetch one or more instructions associated with a program binary, where the one or more instructions include an instruction having an immediate operand. The processor element is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the processor element is configured to retrieve the wide immediate operand from a common immediate lookup table (CILT) in the program binary, where the immediate operand indexes the wide immediate operand in the CII,T. The processor element is then configured to process the instruction having the immediate operand such that the immediate operand is replaced with the wide immediate operand from the CII,T. By allowing instructions with immediate operands to reference a wide immediate operand in the CILT, instructions having wide immediate values can be expressed in the program binary as a single instruction having dual semantics. This may lower the static size of the program binary as well as improve instruction fetch bandwidth compared to conventional approaches, which may improve the performance of the processor-based system.

In another exemplary aspect, a processor element in a processor-based system includes a hardware CILT (HCILT) and instruction processing circuitry. The HCILT includes hardware storage (e.g., a memory or register) configured to store a table indexing immediate values to wide immediate values. The instruction processing circuitry is configured to fetch one or more instructions associated with a program binary from an instruction memory, the instructions including an instruction having an immediate operand. The instruction processing circuitry is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the instruction processing circuitry is configured to search the HCILT for the wide immediate operand indexed by the immediate operand, and, in response to finding the wide immediate operand in the HCILT, process the instruction such that the immediate operand is replaced by the wide immediate operand from the HCILT. If the wide immediate operand is not found in the HCILT, it is retrieved from the CILT as discussed above. If the immediate operand is not a reference to a wide immediate operand, the instruction is processed as usual. Using the HCILT to store and retrieve wide immediate operands avoids having to load the wide immediate operands from memory and thus may significantly improve the performance of the processor-based system.

Exemplary aspects of the present disclosure are related to improved systems and methods for processing instructions having wide immediate values. In this regard, in one exemplary aspect, a processor element in a processor-based system is configured to fetch one or more instructions associated with a program binary, where the one or more instructions include an instruction having an immediate operand. The processor element is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the processor element is configured to retrieve the wide immediate operand from a common immediate lookup table (CILT) in the program binary, where the immediate operand indexes the wide immediate operand in the CII,T. The processor element is then configured to process the instruction having the immediate operand such that the immediate operand is replaced with the wide immediate operand from the CII,T. By allowing instructions with immediate operands to reference a wide immediate operand in the CII,T, instructions having wide immediate values can be expressed in the program binary as a single instruction having dual semantics. This may lower the static size of the program binary as well as improve instruction fetch bandwidth compared to conventional approaches, which may improve the performance of the processor-based system.

In another exemplary aspect, a processor element in a processor-based system includes a hardware CILT (HCILT) and instruction processing circuitry. The HCILT includes hardware storage (e.g., a memory or register) configured to store a table indexing immediate values to wide immediate values. The instruction processing circuitry is configured to fetch one or more instructions associated with a program binary from an instruction memory, the instructions including an instruction having an immediate operand. The instruction processing circuitry is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the instruction processing circuitry is configured to search the HCILT for the wide immediate operand indexed by the immediate operand, and, in response to finding the wide immediate operand in the HCILT, process the instruction such that the immediate operand is replaced by the wide immediate operand from the HCILT. If the wide immediate operand is not found in the HCILT, it is retrieved from the CILT as discussed above. If the immediate operand is not a reference to a wide immediate operand, the instruction is processed as usual. Using the HCILT to store and retrieve wide immediate operands avoids having to load wide immediate operands from memory and thus may significantly improve the performance of the processor-based system.

<FIG> is a schematic diagram of an exemplary processor-based system <NUM> that may include improvements thereto in order to more efficiently process instructions having wide immediate operands. The processor-based system <NUM> includes a number of processor blocks <NUM>(<NUM>)-<NUM>(M), wherein in the present exemplary embodiment "M" is equal to any number of processor blocks <NUM> desired. Each processor block <NUM> contains a number of processor elements <NUM>(<NUM>)-<NUM>(N), wherein in the present exemplary embodiment "N" is equal to any number of processors desired. The processor elements <NUM> in each one of the processor blocks <NUM> may be microprocessors (µP), vector processors (vP), or any other type of processor. Further, each processor block <NUM> contains a shared level <NUM> (L2) cache <NUM> for storing cached data that is used by any of, or shared among, each of the processor elements <NUM>. A shared level <NUM> (L3) cache <NUM> is also provided for storing cached data that is used by any of, or shared among, each of the processor blocks <NUM>. An internal bus system <NUM> is provided that allows each of the processor blocks <NUM> to access the shared L3 cache <NUM> as well as other shared resources such as a memory controller <NUM> for accessing a main, external memory (MEM), one or more peripherals <NUM> (including input/output devices, networking devices, and the like), and storage <NUM>.

In operation, one or more of the processor elements <NUM> in one or more of the processor blocks <NUM> work with the memory controller <NUM> to fetch instructions from memory, execute the instructions to perform one or more operations and generate a result, and optionally store the result back to memory or provide the result to another consumer instruction for consumption.

<FIG> shows details of a processor element <NUM> in a processor block <NUM> of the processor-based system <NUM> according to an exemplary embodiment of the present disclosure. The processor element <NUM> includes an instruction processing circuit <NUM>. The instruction processing circuit <NUM> includes an instruction fetch circuit <NUM> that is configured to fetch instructions <NUM> from an instruction memory <NUM>. The instruction memory <NUM> may be provided in or as part of a system memory in the processor-based system <NUM> as an example. An instruction cache <NUM> may also be provided in the processor element <NUM> to cache the instructions <NUM> fetched from the instruction memory <NUM> to reduce latency in the instruction fetch circuit <NUM>. The instruction fetch circuit <NUM> in this example is configured to provide the instructions <NUM> as fetched instructions 204F into one or more instruction pipelines I<NUM>-IN as an instruction stream <NUM> in the instruction processing circuit <NUM> to be pre-processed, before the fetched instructions 204F reach an execution circuit <NUM> to be executed. The instruction pipelines I<NUM>-IN are provided across different processing circuits or stages of the instruction processing circuit <NUM> to pre-process and process the fetched instructions 204F in a series of steps that can be performed concurrently to increase throughput prior to execution of the fetched instructions 204F in the execution circuit <NUM>.

A control flow prediction circuit <NUM> (e.g., a branch prediction circuit) is also provided in the instruction processing circuit <NUM> in the processor element <NUM> to speculate or predict a target address for a control flow fetched instruction 204F, such as a conditional branch instruction. The prediction of the target address by the control flow prediction circuit <NUM> is used by the instruction fetch circuit <NUM> to determine the next fetched instructions 204F to fetch based on the predicted target address. The instruction processing circuit <NUM> also includes an instruction decode circuit <NUM> configured to decode the fetched instructions 204F fetched by the instruction fetch circuit <NUM> into decoded instructions 204D to determine the instruction type and actions required, which may also be used to determine in which instruction pipeline I<NUM>-IN the decoded instructions 204D should be placed. The decoded instructions 204D are then placed in one or more of the instruction pipelines I<NUM>-IN and are next provided to a register access circuit <NUM>.

The register access circuit <NUM> is configured to access a physical register <NUM>(<NUM>)-<NUM>(X) in a physical register file (PRF) <NUM> to retrieve a produced value from an executed instruction 204E from the execution circuit <NUM>. The register access circuit <NUM> is also configured to provide the retrieved produced value from an executed instruction 204E as the source register operand of a decoded instruction 204D to be executed. The instruction processing circuit <NUM> also includes a dispatch circuit <NUM>, which is configured to dispatch a decoded instruction 204D to the execution circuit <NUM> to be executed when all source register operands for the decoded instruction 204D are available. For example, the dispatch circuit <NUM> is responsible for making sure that the necessary values for operands of a decoded consumer instruction 204D, which is an instruction that consumes a produced value from a previously executed producer instruction, are available before dispatching the decoded consumer instruction 204D to the execution circuit <NUM> for execution. The operands of the decoded instruction 204D can include intermediate values, values stored in memory, and produced values from other decoded instructions 204D that would be considered producer instructions to the consumer instruction.

Notably, an HCILT <NUM> is provided within, or as shown, in addition to the PRF <NUM>. In the present example, the HCILT <NUM> includes a set of HCILT registers <NUM>(<NUM>)-<NUM>(Y), where "Y" is any desired number, dedicated to storing wide immediate values such that the wide immediate values are indexed by immediate values that fit within the instruction size of the ISA of the processor element <NUM>. The HCILT registers <NUM> may include support registers for accomplishing the functionality of the HCILT <NUM> as discussed in detail below. When instructions having immediate operands that reference wide immediate operands (as dictated by the opcode or the semantics of the immediate operand as discussed below), the HCILT <NUM> may be searched for the wide immediate operand such that the immediate operand is replaced with the wide immediate operand from the HCILT <NUM> by the register access circuity <NUM>. This may significantly improve the performance of program binary execution by bypassing loading wide immediate operands from memory, which would otherwise need to occur to process an instruction having a wide immediate value. Further details regarding the functionality of the HCILT <NUM> are discussed below. Notably, while the HCILT <NUM> is illustrated above as a set of registers, the HCILT may be implemented as any type of dedicated hardware storage such as a hardware memory in various embodiments.

The execution circuit <NUM> is configured to execute decoded instructions 204D received from the dispatch circuit <NUM>. As discussed above, the executed instructions 204E may generate produced values to be consumed by other instructions. In such a case, a write circuit <NUM> writes the produced values to the PRF <NUM> so that they can be later consumed by consumer instructions.

<FIG> is a flow diagram illustrating a method for operating the processor element <NUM> to process instructions having wide immediate operands according to an exemplary embodiment of the present disclosure. First, instructions associated with a program binary are fetched from the instruction memory <NUM>, or, if cached, the instruction cache <NUM> (block <NUM>). Notably, as discussed in detail below, the program binary includes a CILT, which is a table storing wide immediate operands that are indexed by immediate operands that fit within an instruction size of the ISA of the processor element <NUM>. The instructions include an instruction having an immediate operand. As discussed above, an immediate operand is a value that is stored as part of an instruction itself, rather than as a point to a memory location or register. A determination is made whether the immediate operand is a reference to a wide immediate operand (block <NUM>). Determining whether the immediate operand is a reference to a wide immediate operand may be accomplished in several ways. In one exemplary embodiment, the ISA of the processor element <NUM> may specify that immediate operands include a reserved bit, which specifies whether the immediate operand is a reference to a wide immediate operand or not. For example, if the most significant bit of an immediate operand is set, the ISA may specify that the immediate operand is a reference to a wide immediate operand, which may be stored in a CILT or HCILT as discussed below. If the most significant bit of the immediate operand is not set, the ISA may specify that the immediate operand is not a reference to a wide immediate operand. In another exemplary embodiment, the ISA of the processor element <NUM> may specify custom opcodes that specify that an immediate operand following the custom opcode is a reference to a wide immediate operand.

If the immediate operand is not a reference to a wide immediate operand, the instruction is processed by the execution circuit <NUM> conventionally (block <NUM>). If the immediate operand is a reference to a wide immediate operand, a determination is made whether the processor element <NUM> includes the HCILT <NUM> (block <NUM>). As discussed above, the HCILT <NUM> is a hardware structure including one or more registers for storing a table which stores wide immediate operands referenced by immediate operands that fit within an instruction size of the ISA of the processor element <NUM>. The HCILT <NUM> is the hardware corollary to the CILT, and is meant to further expedite processing of instructions having wide immediate operands compared to the CILT alone. Determining if the processor element <NUM> includes the HCILT <NUM> may comprise reading a register of the processor element <NUM>. Instructions for determining whether the processor element <NUM> includes the HCILT <NUM> may be included in the ISA of the processor element <NUM>. If the processor element <NUM> does not include the HCILT <NUM>, the wide immediate operand may be retrieved from the CILT in the program binary (block <NUM>). Retrieving the wide immediate operand from the CILT in the program binary may include fetching the wide immediate operand from a memory location that is indexed by the immediate value. The immediate operand may directly point to a memory location including the wide immediate value (e.g., via an offset value from a starting memory address of the CILT) or the CILT may be a map, where the immediate value is hashed to get the actual index of the wide immediate value. Notably, either way the loading of the wide immediate value from memory is performed by the processor element <NUM> in response to encountering an instruction with an immediate operand that references a wide immediate operand (either due to dual semantics of the immediate operand or due to a custom opcode) such that the load from memory is not explicit in instructions associated with the program binary. The difference is expressed below with pseudocode, where an add operation according to conventional approaches would be expressed as: <MAT> is a wide immediate operand <MAT>dependent on preceding load instruction can be reconfigured as: <MAT> is an immediate operand with dual semantics As shown, two instructions used to process an instruction having a wide immediate operand can be condensed into a single instruction, where the loading of the wide immediate value is handled by the processor according to a dedicated ISA specification. This not only reduces the static code size of the program binary but also the instruction fetch bandwidth, which is likely to improve the performance of the processor element <NUM>.

The instruction is then processed such that the immediate operand is replaced with the wide immediate operand from the CILT (block <NUM>). If the processor element <NUM> does include the HCILT <NUM>, a determination is made whether the wide immediate operand referenced by the immediate operand is in the HCILT <NUM> (block <NUM>). The HCILT <NUM> may not be large enough to hold every wide immediate operand in the program binary. That is the, HCILT <NUM> may be smaller than the CILT and thus only some of the wide immediate operands may be present in the HCILT <NUM>. If the wide immediate operand referenced by the immediate operand is not in the HCILT <NUM>, the wide immediate operand is retrieved from the CILT in the program binary (block <NUM>), which is done as discussed above by a dynamic load initiated by the processor element <NUM>. The instruction is then processed such that the immediate operand is replaced with the wide immediate operand from the CILT (block <NUM>). Optionally, the wide immediate operand can also be copied from the CILT to the HCILT <NUM> (block <NUM>) such that the wide immediate operand can be more easily accessed in a future processing cycle. One or more caching rules may dictate whether a wide immediate operand not found in the HCILT <NUM> should be added to the HCILT <NUM> after it is fetched from the CILT as discussed below.

If the wide immediate operand is found in the HCILT <NUM>, the wide immediate operand is retrieved from the HCILT <NUM> (block <NUM>). The wide immediate operand may be retrieved from the HCILT <NUM> using the immediate operand as a direct index or a hashed index as discussed above with respect to the CII,T. The instruction is then processed such that the immediate operand is replaced with the wide immediate operand from the HCILT <NUM> (block <NUM>).

To support the foregoing operations, a number of system registers may be added to the processor element <NUM>, providing support for using the CILT alone or the CILT along with an HCILT. The table below indicates the additional registers and their functions:.

<FIG> is a flow diagram illustrating the application of the process discussed above to a specific instruction, a move immediate (movi) instruction to be processed by the processor element <NUM>. A move immediate instruction includes a register operand and an immediate operand (block <NUM>). The instruction, when processed, moves the immediate operand into the register. The processor element <NUM> determines if the immediate operand is a reference to a wide immediate operand (block <NUM>). As discussed above, determining whether the immediate operand is a reference to a wide immediate operand may include determining if a reserved bit in the immediate operand is set. If the immediate operand is not a reference to a wide immediate operand, the register is set to the immediate operand (block <NUM>) and the move immediate instruction is completed (block <NUM>). If the immediate operand is a reference to a wide immediate operand, the processor element <NUM> determines if it includes the HCILT <NUM> (block <NUM>). If the processor element <NUM> includes the HCILT <NUM>, the register is set to the value in HCILT_table[immediate] (block <NUM>). As shown, the immediate operand indexes the wide immediate operand in the HCILT <NUM>. The move immediate instruction is then completed (block <NUM>). If the processor element <NUM> does not include the HCILT <NUM>, the processor element <NUM> injects a load register instruction ("ldr register, [CILT_base_address + immediate]") to load the wide immediate operand from the CILT (block <NUM>), which is stored in memory starting at CILT_base_address. Again, the immediate operand is used to index the wide immediate operand in the CII,T. Any reserved bits used for determining if the immediate operand is a reference to a wide immediate operand may be stripped from the immediate value before using the immediate value as an index (e.g., offset) to retrieve the wide immediate operand. The move immediate instruction is then completed (block <NUM>).

<FIG> is a flow diagram illustrating how the HCILT <NUM> in the processor element <NUM> is populated from the CILT during a context switch according to an exemplary embodiment of the present disclosure. The population of the HCILT <NUM> occurs in response to a context switch in the program binary (block <NUM>). The processor element <NUM> determines whether a number of entries in the HCILT <NUM> is greater than or equal to a number of entries in the CILT (block <NUM>). As discussed above, the HCILT <NUM> includes a number of registers. The size of the registers determines how many entries (where each entry stores a wide immediate operand) can be stored in the HCILT <NUM> and thus how many entries there are. As discussed above, the number of entries in the HCILT <NUM> may be provided in a register, HCILT_entries, in which case determining if the number of entries in the HCILT <NUM> is greater than or equal to the number of entries in the CILT may be a matter of simply reading a register and performing a comparison. If the number of entries in the HCILT <NUM> is greater than or equal to the number of entries in the CILT, all of the CILT entries are copied into the HCILT (block <NUM>). For example, for a CILT having <NUM> entries and an HCILT <NUM> having <NUM> or more entries, the following exemplary instructions may be executed to populate the HCILT <NUM> from the CILT:
wsr HCILT_active_entry, <NUM>.

where "wsr register, immediate" is a write system register instruction that writes "immediate" to "register," "wide_immediate_x" is wide immediate operand "x" stored in the CII,T. As shown, HCILT_active_entry is written to update the index of the HCILT_table before every write to the HCILT_table. However, in some embodiments the handling of the HCILT table index may be opaque such that it is automatically incremented and decremented (e.g., similar to a stack). The context is then switched in (block <NUM>).

If the number of entries in the HCILT <NUM> is less than the number of entries in the CILT, only a subset of the CILT entries are copied into the HCILT <NUM> (block <NUM>). For example, for a CILT having <NUM> entries and an HCILT having <NUM> entries, the following exemplary instructions may be executed to populate the HCILT <NUM> from the CILT:
wsr HCILT_active_entry, <NUM>.

such that entries <NUM>, <NUM>, <NUM>, and <NUM> of the CILT are copied into the HCILT <NUM>. The context is then switched in (block <NUM>). Any number of different policies can be provided to determine which entries from the CILT are copied into the HCILT <NUM> when the number of entries in the HCILT <NUM> is not sufficient to store all of the entries in the CII,T. Further, a caching policy can be implemented as discussed above such that when a wide immediate operand is not found in the HCILT <NUM> (i.e., an HCILT <NUM> miss) and the wide immediate operand must be fetched from the CILT, the wide immediate operand is copied into the HCILT <NUM> at that time.

The instructions associated with the program binary that are fetched, decoded, and executed by the processor element <NUM> as discussed above are generated by a compiler such that they include the CII,T. <FIG> illustrates an exemplary compiler system <NUM>. The compiler system <NUM> includes a memory <NUM> and processing circuitry <NUM>. The memory <NUM> and the processing circuitry <NUM> are connected via a bus <NUM>. As discussed below, the memory <NUM> stores instructions, which, when executed by the processing circuitry <NUM> cause the compiler system <NUM> to retrieve or otherwise receive source code, generate an intermediate representation of the source code, apply one or more compiler optimizations to the intermediate representation of the source code, and provide the optimized intermediate representation of the source code as machine code suitable for execution by a processor in a processor-based system. The compiler system <NUM> may further include input/output circuitry <NUM>, which may connect to storage <NUM> for storage and retrieval of source code and/or machine code. For purposes of discussion, the operation of the compiler system <NUM> will be described as it relates to compiling source code into machine code for the processor element <NUM> in the processor-based system <NUM>. However, the compiler system <NUM> may more generally compile source code into machine code suitable for any processor in any processor-based system, including several different processors for several different processor-based systems. According to various embodiments of the present disclosure, the memory <NUM> may include instructions, which, when executed by the processing circuitry <NUM> cause the compiler system <NUM> to generate machine code including a CILT and one or more instructions having an immediate value that references a wide immediate value stored in the CILT as discussed in detail below.

<FIG> is a flow diagram illustrating a method for operating the compiler system <NUM> to generate a program binary including a CILT according to an exemplary embodiment of the present disclosure. First, the compiler system <NUM> receives source code (block <NUM>). The source code may be code written in a high-level programming language such as C, Rust, Go, Swift, and the like. Alternatively, the source code may be in a low-level language (i.e., written directly in machine code) that is only assembled by the compiler system <NUM> as discussed below. The compiler system <NUM> identifies wide immediate operands in the source code (block <NUM>). The wide immediate operands may be identified by static code analysis according to one or more rules. For example, wide immediate operands may be identified based on their length, but may also be required to meet additional requirements such as being present in the source code a certain number of times. The compiler system <NUM> may identify the wide immediate operands after converting the source code to an intermediate representation suitable for analysis. The compiler system <NUM> provides the identified wide immediate values in a CILT (block <NUM>), which as discussed above is a data structure, specifically a table, indexing wide immediate operands to immediate values that fit within an instruction length of the ISA of the processor element <NUM>. The compiler system <NUM> may perform one or more additional steps such as code optimization and the like before providing machine code based on the source code (block <NUM>). As discussed above, the CILT data structure, along with the updated ISA for the processor element <NUM> which allows for immediate operands to reference wide immediate operands stored in the CILT, and, optionally, the HCILT <NUM>, may improve the performance of binary execution.

<FIG> is a block diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> configured to support execution of compiler-optimized machine code based on runtime information about the processor <NUM>. For example, the processor <NUM> in Figure <NUM> could be the processor element <NUM> in <FIG>, and the processor-based system <NUM> may be the same as the processor-based system <NUM> in <FIG> with further and/or alternative details shown. The processor-based system <NUM> may be a circuit or circuits included in an electronic board card, such as, a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system <NUM> includes the processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from execution of producer instructions. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions and an instruction processing circuit <NUM>. Fetched or prefetched instructions from a memory, such as from a system memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution.

The processor <NUM> and the system memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based system <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the system memory <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the system memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The system memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random-access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as nonlimiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the system memory <NUM>, one or more input device(s) <NUM>, one or more output device(s) <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based system <NUM> in <FIG> may include a set of instructions <NUM> to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the system memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the system memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes the computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

<FIG> is a flowchart illustrating details regarding what can happen if a wide immediate operand is not found in the HCILT <NUM> (i.e., an HCILT miss) according to one embodiment of the present disclosure. The process begins at block <NUM> of the process discussed above with respect to <FIG>, where the wide immediate operand is not found in the HCILT <NUM> (the NO path from block <NUM> in <FIG>). If the wide immediate operand is not found in the HCILT <NUM>, a determination is made whether the processor element <NUM> has backend support for an HCILT miss (block <NUM>). As discussed herein, backend support for an HCILT miss means that a pipeline (or the part of the pipeline currently executing the instruction having the immediate operand) can be blocked while an instruction to load the immediate operand from the CILT is injected directly into the backend and then processed without a flush of the pipeline. If the processor element <NUM> does have backend support for an HCILT miss, the pipeline is held (block <NUM>) and the instruction is re-processed such that the immediate operand is replaced with the wide immediate operand from the CILT (block <NUM>). A determination is then made if there has been an unforeseen hazard in the pipeline (block <NUM>). This may occur, for example, if the instruction where the immediate operand is replaced with the wide immediate operand from the CILT cannot obtain an execution resource even with the pipeline held, there is a translation fault, etc.) If there has been an unforeseen hazard in the pipeline, the pipeline is flushed (block <NUM>), the instruction is re-fetched (block <NUM>), the instruction is transformed such that the immediate operand is loaded as a wide immediate operand from the CILT (block <NUM>), and the transformed instruction is processed (block <NUM>). Notably, the case in which an unforeseen hazard occurs results in a pipeline flush, which increases overhead of processing the instruction having the immediate operand.

If there was not an unforeseen pipeline hazard (i.e., if re-processing of the instruction such that the immediate operand is replaced with the wide immediate operand from the CILT proceeds without issue after the pipeline is held), a determination is made whether a policy dictates that the wide immediate operand should be inserted in the HCILT (block <NUM>). As part of the support for processing wide immediate operands discussed herein, the processor-based system <NUM> may include a policy for determining when wide immediate operands that were not found in the HCILT <NUM> should be copied from the CILT into the HCILT <NUM>. Notably, this is only an issue when the size of the HCILT <NUM> is smaller than a number of entries in the CII,T. In such a case, policy rules such as a certain number of HCILT misses for a wide immediate operand, a frequency of HCILT misses, or any number of different events may dictate that a wide immediate operand be added to the HCILT <NUM>. If the policy dictates that the wide immediate operand should be inserted in the HCILT <NUM>, a victim entry in the HCILT <NUM> is chosen (block <NUM>), and the victim entry is replaced with the wide immediate operand (block <NUM>). The victim entry may similarly be chosen by any number of policy rules, such as frequency of use, for example.

Moving back to block <NUM>, if the processor element <NUM> does not have backend support for an HCILT miss, meaning that the instruction cannot be re-processed such that the immediate operand is replaced with the wide immediate operand from the CILT without interrupting the pipeline, the pipeline is flushed (block <NUM>), the instruction is re-fetched (block <NUM>) and transformed such that the immediate operand is replaced with the wide immediate operand from the CILT (block <NUM>), and the transformed instruction is processed (block <NUM>). Once again, the process can proceed to block <NUM>, where a determination is made whether the wide immediate should be added to the HCILT <NUM> and can be added or not added based thereon.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is in no way intended that any particular order be inferred.

Claim 1:
A processor-based system (<NUM>), comprising:
a processing element (<NUM>) comprising:
hardware common intermediate lookup table "HCILT" (<NUM>) circuitry comprising a register configured to store a table indexing immediate values to wide immediate values; and
instruction processing circuitry (<NUM>) configured to:
fetch one or more instructions associated with a program binary from an instruction memory (<NUM>), the one or more instructions comprising an instruction having an immediate operand;
determine that the immediate operand is a reference to a wide immediate operand; and
in response to determining that the immediate operand is a reference to a wide immediate operand:
determine whether the processing element includes the HCILT; and in response to determining the processing element does not include an HCILT
retrieve the wide immediate operand from a common intermediate lookup table "CILT" (<NUM>) in the program binary wherein the immediate operand indexes the wide immediate operand in the CILT; and
process the instruction having the immediate operand such that the immediate operand is replaced with the wide immediate operand from the CILT (<NUM>).