Patent Description:
The present invention relates to non-volatile memory arrays, and more particularly to a split gate, <NUM>-bit memory cell having multiple floating and coupling gates, a word line gate and an erase gate. <CIT> discloses that the invention provides a nonvolatile memory. The nonvolatile memory is provided with a storage unit, wherein the storage unit is provided with a stack structure, a first floating gate, a second floating gate, erase gate dielectric layers, auxiliary gate dielectric layers, a first doping region, a second doping region, a first control gate and a second gate, wherein the stack structure comprises a gate dielectric layer, an auxiliary gate, an insulation layer and an erase gate which are sequentially arranged, the first floating gate and the second floating gate are respectively arranged on side walls of two sides of the stack structure, the erase gate dielectric layers are arranged between the erase gate and the first floating grid and between the erase gate and the second floating grid, the auxiliary gate dielectric layers are arranged between the auxiliary gate and the first floating gate and between the auxiliary gate and the second floating gate, the first doping region and the second doping region are respectively arranged at two sides of the stack structure, the first floating gate and the second floating gate, and the first control gate and the second gate are respectively arranged on the first floating gate and the second floating gate. By the nonvolatile memory, low-voltage operation can be performed, and the reliability of a semiconductor component is further improved.

The present invention is set out in the independent claims.

Split gate non-volatile flash memory cells are well known. For example, <CIT> discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region. The memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memory cells). The lines connecting all the control gates for memory cells in a given column run vertically. The same is true for the lines connecting the erase gates and the select gates, and the source lines. The bit lines connecting drain regions for each row of memory cells run horizontally.

Each memory cell stores a single bit of information (based on the programming state of the floating gate). Given the number of electrodes for each cell (source, drain, select gate, control gate and erase gate), and two separate channel regions for each pair of memory calls, configuring and forming the architecture and array layout with all the various lines connected to these electrodes can be overly complex and difficult to implement, especially as critical dimensions continue to shrink.

One solution is to eliminate the source region, and have both memory cells share a single continuous channel region and a common word line gate, and disclosed in <CIT>. However, there are performance limitations with this configuration because, among other things, it lacks erase gates. <CIT> discloses a single continuous channel region and a common erase gate, but lacks any word line gates positioned to control the conductivity of portions of the channel region. <CIT> discloses a single continuous channel region with a common word line gate and erase gates. However, this configuration is not ideal because erase efficiency can be compromised by the high coupling ratio to the drain region and the lack of a geometry that enhances erase tunneling efficiency.

The aforementioned problems and needs are addressed by a memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a channel region in the substrate extending between the first and second regions, wherein the channel region is continuous between the first and second regions, a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a second coupling gate disposed over and insulated from the second floating gate, a word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, and an erase gate disposed over and insulated from the word line gate.

A method of forming a memory cell includes forming a first insulation layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second conductive layer; forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer; forming insulation spacers along a sidewall of the trench; extending the trench through the first conductive layer between the insulation spacers; forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate; forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate; removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates, and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates; and forming first and second regions in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions. The first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate. The second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate. The first coupling gate is disposed over and insulated from the first floating gate. The second coupling gate is disposed over and insulated from the second floating gate.

A method of forming a memory cell, includes forming a first insulation layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second conductive layer; removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates, and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates; forming a word line gate that is disposed vertically over and insulated from the substrate and disposed laterally between the first and second floating gates; forming an erase gate that is disposed vertically over and insulated from the word line gate and disposed laterally between the first and second coupling gates; and forming first and second regions in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions. The first floating gate is disposed over and insulated from the substrate. The second floating gate is disposed over and insulated from the substrate. The first coupling gate is disposed over and insulated from the first floating gate. The second coupling gate is disposed over and insulated from the second floating gate.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

The present invention is a memory cell design, architecture and method of manufacture of a split-gate, <NUM>-bit memory cell. Referring to <FIG>, there are shown cross-sectional views of the steps in the process to make a <NUM>-bit memory cell. While only the formation of a single <NUM>-bit memory cell is shown in the figures, it should be understood that an array of such <NUM>-bit memory cells are formed concurrently when forming a memory device containing an array of such <NUM>-bit memory cells. The process begins by forming a first insulation layer <NUM> (e.g. layer of silicon dioxide, also referred to herein as oxide layer <NUM>) on the top surface 10a of a substrate <NUM> of a semiconductor material (e.g., single crystalline silicon. Thereafter, a first conductive layer <NUM> (e.g. polysilicon (also referred to herein as "poly") or amorphous silicon) is formed on the oxide layer <NUM>. Then a second insulation layer <NUM> is formed on conductive layer <NUM>. Preferably, second insulation layer <NUM> is an ONO layer, meaning it has oxide-nitride-oxide sublayers. A second conductive layer <NUM> (e.g. polysilicon or amorphous silicon) is formed on second insulation layer <NUM>. A third insulation layer <NUM> (e.g. silicon nitride - referred to herein as "nitride") is formed on second conductive layer <NUM>. Photoresist material (not shown) is coated on the structure, and a photolithography masking step is performed exposing selected portions of the photoresist material. The photoresist is developed such that portions of the photoresist are removed. Using the remaining photoresist as a mask, the structure is etched. Specifically, third insulation layer <NUM>, second conductive layer <NUM> and second insulation layer <NUM> are anisotropically etched (using conductive layer <NUM> as an etch stop), leaving a trench <NUM> extending through third insulation layer <NUM>, second conductive layer <NUM> and second insulation layer <NUM>. The resulting structure is shown in <FIG> (after photoresist removal).

Insulation spacers <NUM>/<NUM> (e.g., ON - oxide and nitride) are formed along the sidewalls of trench <NUM>. Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (with a rounded upper surface, not shown). Insulation (ON) spacers <NUM>/<NUM> are formed by oxide deposition, nitride deposition, and then nitride anisotropic etch and oxide anisotropic etch. Oxide spacers <NUM> are then formed in trench <NUM> by oxide deposition followed by oxide anisotropic etch. An anisotropic etch is then performed to remove the exposed portion of conductive layer <NUM> below the area located between oxide spacers <NUM>, as shown in <FIG>, deepening trench <NUM>. An implantation may be performed at this time (through oxide layer <NUM> at the bottom of trench <NUM> and into the portion of the substrate <NUM> underneath (which will eventually be the word line portion of the channel region as described further below).

Oxide spacers <NUM> are next formed along the sidewalls of trench <NUM> (including along the exposed sidewalls of conductive layer <NUM>) by oxide deposition and anisotropic oxide etch. This spacer formation, particularly the anisotropic oxide etch which removes the portion of oxide layer <NUM> at the bottom of trench <NUM>, leaves the portion of the substrate surface 10a between oxide spacers <NUM> exposed. Oxide layer <NUM> is formed on this exposed portion of the substrate surface 10a at the bottom of trench <NUM>, preferably by thermal oxidation. Also preferably oxide layer <NUM> has a thickness that is less than that of oxide layer <NUM>. A first block of conductive material <NUM> is formed on oxide layer <NUM> inside trench <NUM> by material deposition, a chemical mechanical polish (CMP) using third insulation layer <NUM> as a stop layer), and etch back. Preferably, the first block of conductive material <NUM> is formed of polysilicon, and the top surface of the first block of conductive material <NUM> is below the top surface of the conductive layer <NUM>. The first block of conductive material <NUM> is laterally adjacent to, and insulated from, conductive layer <NUM>. An implantation can be performed to dope the first block of conductive material <NUM> should polysilicon be used for the first block of conductive material <NUM>. The resulting structure is shown in <FIG>.

An oxide etch (e.g., wet etch) is used to remove the upper portions of oxide spacers <NUM> (above the block of conductive material <NUM>) and all of oxide spacers <NUM>. An oxide layer <NUM> is then formed over the structure by oxide deposition. A second block of conductive material <NUM> is formed on oxide layer <NUM> inside trench <NUM> by material deposition and a chemical mechanical polish (CMP) using third insulation layer <NUM> as a stop. Preferably, the second block of conductive material <NUM> is formed of polysilicon. The resulting structure is shown in <FIG>.

Photoresist material <NUM> is coated on the structure, and a photolithography masking step is performed exposing selected portions of the photoresist material. The photoresist material <NUM> is developed such that portions of the photoresist material <NUM> are removed (except for photoresist material <NUM> over the second block of conductive material <NUM> and over portions of third insulation layer <NUM> adjacent the second block of conductive material <NUM>). Using the remaining photoresist material <NUM> as a mask, the structure is etched to remove the exposed portions of third insulation layer <NUM>, second conductive layer <NUM>, second insulation layer <NUM> and conductive layer <NUM>, as shown in <FIG>. After photoresist <NUM> is removed, spacers <NUM> (e.g., nitride) are formed along the sides of the structure by deposition and anisotropic etch. An implantation is then performed to form drain regions 44a and 44b in the substrate <NUM> laterally adjacent to the spacers <NUM>, and extending beneath the respective spacers <NUM> and partially under the respective adjacent conductive layer <NUM>. Drain regions 44a/44b are first and second regions of the substrate having a conductivity type different from that of the substrate <NUM> in the vicinity of a channel region <NUM> described below. For example, the channel region <NUM> can be P type conductivity, and the drain regions 44a/44b can be N type conductivity, and vice-versa. The final structure is shown in <FIG>.

The final <NUM>-bit memory cell <NUM> is best shown in <FIG>, where channel region <NUM>, which is continuous, is defined in the substrate <NUM> by, and extends between, spaced apart first and second drain (bit line) regions 44a and 44b. A first floating gate 14a (a first block of material remaining from conductive layer <NUM>) is disposed over and insulated from a first portion of the channel region <NUM> (for controlling the conductivity thereof) adjacent the first drain region 44a, and preferably the first floating gate 14a is partially disposed over and insulated from the first drain region 44a, by a respective remaining portion of oxide layer <NUM>. A first coupling gate 18a (first block of material remaining from conductive layer <NUM>) is disposed over and insulated from the first floating gate 14a (for voltage coupling to the floating gate 14a), by a respective remaining portion of second insulation layer <NUM>. A second floating gate 14b (a second block of material remaining from conductive layer <NUM>) is disposed over and insulated from a third portion of the channel region <NUM> (for controlling the conductivity thereof) adjacent the second drain region 44b, and preferably the second floating gate 14b is partially disposed over and insulated from the second drain region 44b by a respective remaining portion of oxide layer <NUM>. A second coupling gate 18b (second block of material remaining from conductive layer <NUM>) is disposed over and insulated from the second floating gate 14b (for voltage coupling to floating gate 14b) by a respective remaining portion of second insulation layer <NUM>. The first block of conductive material <NUM> is a word line gate disposed vertically over and insulated from a second portion of the channel region <NUM> (for controlling the conductivity thereof), and is laterally adjacent to the first and second floating gates 14a/14b. The second block of conductive material <NUM> is an erase gate that is disposed vertically over and insulated from the word line gate <NUM>, and laterally adjacent to and insulated from the first and second coupling gates 18a/18b, the insulation from the word line gate <NUM> provided by oxide layer <NUM> and the insulation from the first and second coupling gate 18a/18b provided by oxide layer <NUM> and spacer <NUM>/<NUM>. The erase gate <NUM> includes notches 38a each facing a respective edge 14c of one of the first and second floating gates 14a/14b. Insulation blocks 20a and 20b (blocks of material remaining from third insulation layer <NUM>) are disposed over first and second coupling gates 18a/18b.

Table <NUM> below illustrates exemplary operational voltages and currents for program, read and erase operations of the <NUM>-bit memory cell <NUM>.

Programming first floating gate 14a with electrons stores the first bit (i.e., bit <NUM>) of information, and programming second floating gate 14b with electrons stores the second bit (i.e., bit <NUM>) of information. To program first floating gate 14a, a voltage of about <NUM>. 5V is applied to erase gate <NUM> and a voltage of about <NUM>. 5V is applied to first coupling gate 18a which are capacitively coupled to first floating gate 14a. A voltage of about 1V is applied to the word line gate <NUM> which turns on the portion of channel region <NUM> under the word line gate <NUM>. A voltage of about <NUM>. 5V is applied to second coupling gate 18b which is capacitively coupled to second floating gate 14b, to turn on the portion of the channel region <NUM> under the second floating gate 14b. A voltage of about <NUM>. 5V is applied to first drain region 44a and a current of about -1uA is applied to second drain region 44b. Electrons travel from second drain region 44b toward first drain region 44a, and inject themselves onto first floating gate 14a because of the positive voltage capacitively coupled to first floating gate 14a by erase gate <NUM> and first coupling gate 18a. Second floating gate 14b is similarly programmed using the combination of voltages for bit <NUM> in Table <NUM>.

To erase the first and second floating gates 14a and 14b, a voltage of about <NUM> volts is applied to the erase gate <NUM>, and a negative voltage of about -7V is applied to the first and second coupling gates 18a and 18b, which causes electrons to tunnel through the insulation layer <NUM> from the first and second floating gates 14a and 14b to the erase gate <NUM>. Notches 38a facing respective edges 14c enhance the efficiency of this tunneling.

To read first floating gate 14a, Vcc is applied to word line gate <NUM> which turns on the portion of the channel region <NUM> under word line gate <NUM>. A voltage of Vblr is applied to second drain region 44b and zero volts is applied to first drain region 44a. A voltage of about <NUM>. 5V is applied to second coupling gate 18b, which is capacitively coupled to second floating gate 14b (turning on the portion of channel region <NUM> under second floating gate 14b). Current will flow through the channel region <NUM> if first floating gate 14a is erased (i.e., in the erased state first floating gate 14a will have a positive voltage thereon due to positive charge on first floating gate 14a after erasing and a small voltage coupling from word line gate <NUM>, and therefore the portion of the channel region <NUM> under the first floating gate 14a is turned on). Current is sensed as an erased stated. Current is reduced or will not flow through the channel region <NUM> if first floating gate 14a is programmed (i.e. is programmed with electrons sufficient to prevent turning on the portion of the channel region under first floating gate 14a). The low or no current is sensed as a programmed state. Second floating gate 14b is similarly read using the combination of voltages for bit <NUM> in Table <NUM>.

The <NUM>-bit memory cell <NUM> has many advantages. The insulation (i.e., oxide layer <NUM>) under the word line gate can be much thinner than the insulation (i.e., oxide layer <NUM>) under the first and second floating gates 14a/14b, for higher performance especially for high speed applications. The insulation (i.e., oxide layer <NUM>) between the first and second floating gates 14a/14b and the erase gate <NUM> can be thinner than the insulation (i.e., oxide spacer <NUM>) between the first and second floating gates 14a/14b and the word line gate <NUM>. The erase performance is enhanced because of the relatively low voltage coupling ratio between the erase gate <NUM> and the first and second floating gates 14a/14b (because only the corner regions of erase gate <NUM> (with notches 38a) are in close proximity to the corner regions (with edges 14c) of the first and second floating gates 14a/14b). Only two photolithography masking steps are needed to define the structure, one for forming trench <NUM>, and one for etching through conductive layers <NUM> and <NUM> to complete the formation of first and second coupling gates 18a/18b and first and second floating gates 14a/14b. Both word line gate <NUM> and erase gate <NUM> are self-aligned to the first and second floating gates 14a/14b.

<FIG> illustrate an alternate embodiment for forming the <NUM>-bit memory cell, which starts with the structure similar to that shown in <FIG>, except when forming trench <NUM>, additional trenches <NUM> are formed as well (one on each side of trench <NUM>), as shown in <FIG> (after photo resist removal). Forming the two trenches <NUM> along with trench <NUM> therebetween results in stack structures S <NUM> and S2, each having a block of the third insulation layer <NUM> over a block of the second conductive layer <NUM> over a block of the second insulation layer <NUM> over conductive layer <NUM>. Oxide spacers <NUM>, nitride spacers <NUM> and oxide spacers <NUM> are formed along the sidewalls of stack structures S <NUM> and S2 using the same processing steps as described above with respect to <FIG>, resulting in the structure shown in <FIG>. A masking step is then used to cover the stack structures S1 and S2 with photoresist except for oxide spacers <NUM> on the outer facing sidewalls of stack structures S1 and S2. An etch is then used to remove oxide spacers <NUM> on the outer facing sidewalls of stack structures S1 and S2. After photoresist removal, exposed portions of conductive layer <NUM> (i.e., those portions not protected by the stack structures S <NUM> and S2) are removed by an etch, resulting in the structure of <FIG>. An implantation may be performed at this time (through oxide layer <NUM> between the stack structures S <NUM> and S2 and into the portion of the substrate <NUM> underneath (which will eventually be the word line portion of the channel region as described further below).

Oxide spacers <NUM> are next formed along the sidewalls of stack structures S <NUM>/S2 (including along the exposed sidewalls of conductive layer <NUM>) by oxide deposition and anisotropic oxide etch. This spacer formation, particularly the anisotropic oxide etch which removes the portion of oxide layer <NUM> at the bottom of trench <NUM>, removes the exposed portions of oxide layer <NUM>. Oxide layer <NUM> is formed on the exposed portions of the substrate surface 10a at the bottom of trench <NUM>, preferably by thermal oxidation. Also preferably oxide layer <NUM> has a thickness that is less than that of oxide layer <NUM>. A conductive layer <NUM> (e.g. polysilicon or amorphous silicon) is formed on the structure. A CMP is performed on the conductive layer (using third insulation layer <NUM> as a stop layer). An etch is then used to lower the top surface of conductive layer <NUM> preferably below the top surface of the conductive layer <NUM>. An implantation can be performed to dope the conductive layer <NUM> should polysilicon be used for the conductive layer <NUM>. The resulting structure is shown in <FIG>.

An oxide etch (e.g., wet etch) is used to remove the upper portions of oxide spacers <NUM> (above the conductive layer <NUM>) and all of oxide spacers <NUM>. Oxide layer <NUM> is then formed over the structure by oxide deposition. A conductive layer <NUM> is formed on oxide layer <NUM>. Preferably, the conductive layer <NUM> is formed of polysilicon. A chemical mechanical polish (CMP) is then performed using third insulation layer <NUM> as a stop. The resulting structure is shown in <FIG>.

Photoresist material is coated on the structure, exposed, and selectively removed leaving the area above and between the stack structures S <NUM> and S2 covered but the area outside of the stack structures S1 and S2 exposed (i.e., the area to the right of stack structure S2 and the area to the left of stack structure S <NUM> in <FIG>). Etches are then performed to remove portions of the conductive layer <NUM>, oxide layer <NUM> and conductive layer <NUM>, outside of the stack structures S <NUM>/S2. After photoresist removal, spacers <NUM> (e.g., nitride) are formed along the sides of the structure by deposition and anisotropic etch. An implantation is then performed to form first and second drain regions 44a and 44b in the substrate <NUM> laterally adjacent to the spacers <NUM>, and extending beneath the respective spacers <NUM> and partially under the respective adjacent conductive layer <NUM>. The final structure is shown in <FIG>.

The final <NUM>-bit memory cell <NUM> of the alternate embodiment is best shown in <FIG>, which essentially has the same structure as that shown in <FIG>, except the erase gate 58a is the remaining portion of conductive layer <NUM> (with notches 58b facing respective edges 14c of the first and second floating gates 14a/14b), the word line gate 54a is the remaining portion of conductive layer <NUM>, and the tunnel oxide separating erase gate 58a from first and second floating gates 14a/14b is oxide layer <NUM>.

The additional advantages of the alternate embodiment include that the horizontal dimensions of first and second coupling gates 18a/18b are defined by one lithography step, which can reduce dimension variations for the first and second coupling gates 18a/18b.

Control circuitry <NUM> preferably (but not necessarily) formed on the same substrate <NUM> (as shown in <FIG>) is configured to program, read and erase a memory array <NUM> of the <NUM>-bit memory cells <NUM> or <NUM> described herein by applying the voltages of Table <NUM> as described above.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell array of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

Claim 1:
A method of forming a memory cell, comprising:
forming a first insulation layer (<NUM>) on a semiconductor substrate (<NUM>) having a first conductivity type;
forming a first conductive layer (<NUM>) on the first insulation layer;
forming a second insulation layer (<NUM>) on the first conductive layer;
forming a second conductive layer (<NUM>) on the second insulation layer;
forming a third insulation layer (<NUM>) on the second conductive layer;
forming a trench (<NUM>) that extends through the third insulation layer, the second conductive layer, and the second insulation layer;
forming insulation spacers (<NUM>, <NUM>, <NUM>) along a sidewall of the trench;
extending the trench through the first conductive layer between the insulation spacers;
forming a word line gate (<NUM>) in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate;
forming an erase gate (<NUM>) in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate;
removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates (18a, 18b), and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates (14a, 14b); and
forming first and second regions (44a, 44b) in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region (<NUM>) in the substrate extends between the first and second regions;
wherein:
the first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate,
the second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate,
the first coupling gate is disposed over and insulated from the first floating gate, and
the second coupling gate is disposed over and insulated from the second floating gate.