Patent Description:
Firmware upgrade on embedded systems can be slow depending on communication speed and image size. Embedded systems also have limited processing and storage resources. Conventional art typically only works on RAM and is not usable as in embedded environments due to limited RAM space.

In embedded systems, when there is a lack of storage space, there can be difficulty in finding storage space for additional input and output. Additional input can include one or more inputted compressed images.

In addition, when firmware images are transferred to an embedded device, it will usually stored temporarily in external storage. Image encryption can be used to secure the image. If the image is compressed, it is necessary to decrypt the entire image before decompression. Moreover, the image then exits even for a short period as plaintext in its compressed or decompressed form.

As such, a need exists to redirect input and output to arbitrary storage when there is a lack of storage space in the computing device or system. Additional storage is needed to redirect the input and output when there is a lack of storage available in the RAM within the computing device or system.

Further, a need also exits to perform decryption, decompression and reencryption in parallel. In addition, a need exits to perform decryption, decompression, and reencryption in parallel without allowing an attacker to read, analyze, or use the image involved.

An example of a currently used system can be found in <CIT>, which discloses methods and systems for memory decompression using a hardware decompressor that minimizes or eliminates the involvement of software. Custom decompression hardware is added to the memory subsystem, where the decompression hardware handles read accesses caused by, for example, cache misses or requests from devices to compressed memory blocks, by reading a compressed block, decompressing it into an internal buffer, and returning the requested portion of the block. The custom hardware is designed to determine if the block is compressed, and determine the parameters of compression, by checking unused high bits of the physical address of the access. This allows compression to be implemented without additional metadata, because the necessary metadata can be stored in unused bits in the existing page table structures.

The accompanying figures, in which like reference numerals refer to identical or functionally similar elements throughout the separate views and which are incorporated and form a part of the specification, further illustrate the present invention and, together with the detailed description of the invention, serve to explain the principles of the present invention.

Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale.

Embodiments of the present invention include a computing system that lacks storage space in its internal random-access memory (RAM) and needs to be able to redirect input and output to arbitrary storage. The arbitrary storage can include nonvolatile storage that is located within the same computing system, or located externally to the computing system.

In anticipation of the need to redirect input and output within the computing system to the arbitrary storage, a microprocessor core will perform calls to a system of memory caches to facilitate the redirecting of the input and output to the arbitrary storage.

The arbitrary storage can include, but is not limited to, additional random-RAM, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash, and one or more other serial devices. The microprocessor core can redirect the input and output to the nonvolatile or arbitrary storage in response to a lack of available storage within its internal RAM.

Embodiments of the present invention also include perform the process of decryption, decompression, and reencryption in parallel. The processes are perform in parallel to mitigate security risks by firmware images, such as when an attacker tries to read, analyze or otherwise use the image.

In a manufacturer device, a manufacturer key will decrypt a compressed image. The image will then become decompressed and become a plain text box. Once it has become a plain text box, the plain text box can then be reencrypted. As such, the plain text box is reencrypted into a ciphered image. Accordingly, the decryption, decompression, and reencryption occur in parallel to mitigate the security risk presented by firmware images that are stored in plaintext.

<FIG> illustrates a high level system (system) <NUM>. The system will include a product <NUM> that can be input or output. The system <NUM> also includes a communication (comms) interface <NUM> that is configured to communicate with a microprocessor core <NUM>. The microprocessor core <NUM> will be powered by a power supply <NUM> that provides the main power, and include one or more processors. A nonvolatile storage <NUM> will be connected to the microprocessor <NUM>. Random access memory (RAM) <NUM> is also illustrated. The RAM <NUM> is connected to the microprocessor core <NUM>.

Referring to <FIG>, the system <NUM> will receive input such as an inputted compressed image. The microprocessor core <NUM> will attempt to place any input within the system <NUM> into either the RAM <NUM> or the nonvolatile storage <NUM>. The nonvolatile storage <NUM> can be the arbitrary storage in which output and input can be redirected to if the RAM <NUM> does not have any available space to store the input and output. The input can also include an inputted compressed image. The microprocessor core <NUM> will make calls to a system of caches within the nonvolatile storage <NUM> to facilitate redirecting the input and output to the nonvolatile storage <NUM> due to the lack of available storage within the RAM <NUM>. The microprocessor <NUM> will make the calls to the system of caches due to a shortage of memory in the RAM <NUM>, such as during a decompression process. The nonvolatile storage <NUM> can be within the same computing system as the microprocessor core <NUM>. Alternatively, the nonvolatile storage <NUM> can be external to the high-level system <NUM> as well.

In <FIG>, the microprocessor core <NUM>, based on the calls to the system of caches, can redirect input and output to the nonvolatile storage <NUM> to store the input and output. The nonvolatile storage can include additional RAM, EEPROM, ROM, Flash, and other serial devices, etc. When there is a lack of available space in the RAM <NUM> in the high-level system <NUM>, the microprocessor core <NUM> will make calls to a system of caches including the nonvolatile storage <NUM> to facilitate the redirection of the input and output. The microprocessor core <NUM>, after making the calls to the system of caches, will then redirect the input and output to the nonvolatile storage <NUM> to allow the input and output to be stored within the nonvolatile storage <NUM>. As such, the redirecting input and output can be stored in additional RAM, ROM, EEPROM, flash and/or one or more other serial devices.

In <FIG>, a system <NUM> with internal cache synchronization, wherein synchronization is needed only in case of overlap. A process in which output and input is redirected to arbitrary storage in further detail is shown. The system <NUM> includes an overlap area <NUM>, a decompressed read cache RAM <NUM>, and a decompressed write cache RAM <NUM>. The decompressed read cache RAM <NUM> includes a plurality of data bytes <NUM>. The decompressed write cache RAM <NUM> will include data bytes <NUM> that are read into the decompressed read cache RAM <NUM>. The overlap area <NUM> is the area in which the decompressed read cache RAM <NUM> and the decompressed write cache RAM <NUM> overlap, and in which data bytes <NUM> from the decompressed write cache RAM <NUM> are read <NUM> and updated <NUM> into the decompressed read cache (RAM) <NUM>. The overlap area <NUM> would exist only if an intersection of buffers is not empty.

Referring to <FIG>, a decompressed image flash <NUM> is also illustrated. The decompressed write cache RAM <NUM> will write <NUM> the data bytes <NUM> into the decompressed image flash <NUM> for storage. When storage is not available in the decompressed write cache RAM <NUM> or the decompressed read cache RAM <NUM>, the decompressed write cache (RAM) <NUM> will write the data bytes <NUM> into the decompressed image flash <NUM> for storage. The microprocessor core will make calls to the system of memory caches that will include the decompressed image flash <NUM> to facilitate the redirecting of the data bytes <NUM> due to a lack of available storage in the decompressed read cache (RAM) <NUM> and the decompressed write cache (RAM) <NUM>. The decompressed image flash <NUM> will provide the arbitrary storage when the data bytes <NUM>, <NUM> cannot be stored in either the decompressed read cache RAM <NUM> or the decompressed write cache (RAM) <NUM>. The decompressed image flash <NUM> can be within the same system <NUM> as the decompressed read cache (RAM) <NUM> and the decompressed write cache (RAM) <NUM>, or external to the decompressed read cache (RAM) <NUM> and the decompressed write cache (RAM) <NUM>. The decompressed image flash <NUM> can also read <NUM> the data bytes <NUM> from the decompressed read cache RAM <NUM>. Although the decompressed image flash <NUM> is illustrated, other arbitrary storage can be included such as ROM or EEPROM or additional RAM. One or more serial devices can be connected to the decompressed image flash <NUM> and other arbitrary storage including additional RAM, ROM, and EEPROM.

In <FIG>, in summary, data bytes <NUM> can be redirected into arbitrary storage such as the decompressed image flash <NUM> when storage is not available in either the decompressed write cache RAM <NUM> or the decompressed read cache RAM <NUM>. The microprocessor core will include a processor that will perform calls to arbitrary storage including the decompressed image flash <NUM> to facilitate for the data bytes <NUM> to be redirected to the decompressed image flash <NUM> and other arbitrary storage when storage is not available within internal cache synchronization within the decompressed read cache (RAM) <NUM> or decompressed write cache (RAM) <NUM>. As such, when there is no available storage within the system <NUM>, the microprocessor core within the system <NUM> will make calls to a system of caches that include the decompressed image flash <NUM> to facilitate the data bytes <NUM> to be redirected when there is a lack of shortage. Ultimately, the microprocessor core, using the decompressed write cache (RAM) <NUM>, will write <NUM> the data bytes <NUM> to the decompressed image flash <NUM>. The decompressed image flash <NUM> can be part of the same system <NUM> as the cache synchronization, or be external to the system <NUM> that includes the decompressed write cache (RAM) <NUM>. In addition, although not represented in <FIG>, there is a third cache that is used only for reading data from a compressed image.

In <FIG>, a system <NUM> in which decryption, decompression and reencryption occurs in parallel processes. The system <NUM> includes a manufacturer premises <NUM> and an external flash <NUM> as part of a manufacturer device. A plain text image <NUM> is compressed and becomes a plain text compressed image <NUM>. A manufacturer key <NUM> will encrypt the plain text compressed image <NUM>. The ciphered compressed image <NUM> will pass over the air download <NUM> and into the external flash <NUM> within the manufacturer device.

With respect to <FIG>, a manufacturer key <NUM> will decrypt the ciphered compressed image <NUM> to enable the ciphered compressed image <NUM> to then be decompressed. When the ciphered compressed image <NUM> is decrypted, it will become the plain text compressed block <NUM>. The plain text compressed block <NUM> will then become decompressed and then become the plain text box <NUM> after decompression. Further, after the plain text compressed block <NUM> is decompressed, and has become the plain text box <NUM>, the plain text box <NUM> can thereby be reencrypted. In other words, following the decryption and the decompression, the reencryption process can occur. The manufacturer or another key <NUM> can reencrypt the plain text box <NUM>. The plain text box <NUM> can become the ciphered image <NUM> after being reencrypted.

Referring to <FIG>, in summary, a plain text image <NUM> is compressed and becomes a plain text compressed image <NUM>. The plain text compressed image <NUM> then goes thru a process of becoming encrypted, and then passes onto an external flash <NUM> to be decrypted, decompressed, and then reencrypted. The process of decryption, decompression, and reencryption all occur in parallel within the manufacture device or external flash <NUM>. Accordingly, within the external flash <NUM>, decryption, decompression, and reencryption can successfully occur in parallel for the ciphered compressed image.

In <FIG>, a system <NUM> in which the parallel processes of decryption, decompression, and reencryption are illustrated. An inputted compressed image becomes an encrypted compressed image IMG <NUM>. Moreover, a manufacturer key will encrypt the inputted compressed image to put forth the encrypted compressed IMG <NUM>. The encrypted compressed IMG <NUM> is passed onto a manufacturer device that includes a flash device. The decryption process can begin. The encrypted compressed image IMG <NUM> can then be decrypted. A manufacturer key within the manufacturer device can decrypt the encrypted compressed image <NUM>. When the inputted compressed IMG <NUM> is decrypted, it can become a decrypted compressed IMG <NUM> within the RAM <NUM>. After the image has been decrypted to be the decrypted compressed IMG <NUM>, the decompression process can begin. Moreover, the image can then become decompressed and become the decompressed IMG <NUM>. After decompression, the decompressed IMG can become encrypted again or reencrypted. A manufacturer or another key with the manufacturer device can reencrypt the decompressed IMG <NUM>. When the decompressed IMG <NUM> is reencrypted, the image can become the encrypted decompressed IMG <NUM>.

Referring to <FIG>, a parallel process of decryption, decompression and reencryption is illustrated. The inputted and encrypted compressed IMG <NUM> is passed through the manufacturer device. Further, a manufacturer key can decrypt the encrypted compressed IMG <NUM> to produce the decrypted compressed IMG <NUM>. After the decryption has occurred, the decrypted compressed IMG <NUM> can be decompressed. As such, after decompression, the decompressed IMG <NUM> is produced. After decompression, reencryption can occur. A manufacturer key can reencrypt the decompressed IMG <NUM>. After reencryption, the encrypted decompressed IMG <NUM> is produced. Overall, the decryption, decompression, and reencryption process all occur in parallel within the manufacturer device.

In <FIG>, a process <NUM> of redirecting input and output due to a lack of storage is illustrated. When RAM or other storage within a computing device or system lacks available space, input and output can be redirected to nonvolatile storage. The nonvolatile storage can be external to the computing device or system, or be within the computing device or system.

In <FIG>, at step <NUM>, at an initial step or state, an inputted compressed image is received into a computing device or system. The process <NUM> can begin after the inputted compressed image is received.

Referring to <FIG>, at step <NUM>, a designer, using a microprocessor core, or a processor, can identify if there is a shortage of space within the computing device or system to store input and output including the inputted compressed image.

In <FIG>, at step <NUM>, the microprocessor core will perform calls to a system of memory caches to read and write the input and output. The microprocessor makes the calls to the system of memory caches to facilitate the redirecting of the input and output due to the lack of available storage space in the RAM within the computing system.

Referring to <FIG>, at step <NUM>, microprocessor core will redirect the input and output to identified arbitrary storage. The arbitrary storage can be nonvolatile storage that can be within the same computing system as the computing device, or can be external to the computing device. The arbitrary storage can include additional RAM, or ROM, flash, and EEPROM. Moreover, the arbitrary storage can include other serial devices. The input and output is thereby redirected to additional RAM, ROM, EEPROM, or flash for storage.

Overall, a microprocessor core in a computing system can identify when there is a shortage of storage space within the storage of the computing system. The available RAM within the computing system may not have enough storage space to store input and output.

In anticipation of having to redirect the input and output, the microprocessor core will make calls to a system of memory caches to attempt to redirect the input and output to one or more of the memory caches. Moreover, the system of memory caches can be nonvolatile storage that can be within the computing system, or external to the computing system. The nonvolatile storage can include RAM, ROM EEPROM, Flash, and other serial device. As such, the microprocessor core performs the calls to facilitate the redirecting of the input and output to the nonvolatile storage due to the lack of available storage.

After performing the calls to the system of memory caches to facilitate the redirecting of the input and output to the nonvolatile storage, the microprocessor core redirects the input and output to the nonvolatile storage. The nonvolatile storage can include any one of additional RAM, ROM EEPROM, flash, and other serial devices.

Accordingly, the microprocessor core attempts to facilitate the redirecting of input and output when the microprocessor identifies a shortage of storage space within the computing system. After the calls are made to the system of memory caches, the microprocessor core can redirect any input and output to the nonvolatile storage for storage due to a lack of available storage within the computing system. The nonvolatile storage can be within the same computing system, or can be external to the computing system. The nonvolatile storage can include additional RAM, and also ROM, EEPROM, flash, and other serial devices to store the redirected input and output.

Claim 1:
A method for operating a system (<NUM>) with internal cache synchronization, the method comprising:
identifying a storage shortage in at least one of a decompressed write cache RAM (<NUM>) and a decompressed read cache RAM (<NUM>) of the internal cache synchronization, wherein the internal cache synchronization further comprises an overlap area (<NUM>), the overlap area (<NUM>) is an area in which the decompressed read cache RAM (<NUM>) and the decompressed write cache RAM (<NUM>) overlap, and in which data from the decompressed write cache RAM (<NUM>) are read and updated into the decompressed read cache RAM (<NUM>);
performing calls to a system of memory caches to identify arbitrary storage, based on the identification of the storage shortage in at least one of the decompressed write cache RAM (<NUM>) and the decompressed read cache RAM (<NUM>); and
redirecting the data to the identified arbitrary storage.