Patent Description:
Dynamic Random Access Memories (DRAMs) have the advantages of small size, high integration and low power consumption, and are faster than all Read Only Memories (ROMs). With the increase in integration, the feature size of a capacitor and the area of an electrode plate continue to decrease, so dielectric materials that are thinner or/and have higher dielectric constants have to be used to increase the capacitance density. With the development of the semiconductor industry, the critical dimensions of devices such as DRAMs continue to decrease.

However, as the critical dimensions of the devices continue to decrease, a floating gate effect will occur between a transistor and a substrate. This is because, when the transistor is in an off state, some charges in the capacitor structure move into the transistor through a capacitor contact structure and a capacitor pad, as a result, holes in the transistor are increased to increase the voltage in the transistor, a voltage difference is produced between the transistor and the substrate, and then the floating gate effect is produced, which will affect the performance of the semiconductor structure. Background may be found in <CIT>.

Further background may be found in <CIT> which discloses a semiconductor structure according to the preamble of the claims.

The subject matter is described in detail herein below, which is not intended to limit the scope of protection of claims.

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

After the drawings and detailed description are read and understood, other aspects may be understood.

The drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are configured to represent similar elements. The drawings in the following description are only some rather than all of the embodiments of the present disclosure. Those skilled in the art would be able to derive other drawings from these drawings without any creative efforts.

In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure shall fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other on a non-conflict basis.

A floating gate effect may occur between a transistor and a substrate in a semiconductor structure, and the floating gate effect will affect the performance of the semiconductor structure. After search, the inventor found, this is because, when the transistor is in an off state, some charges in the capacitor structure move into the transistor through a capacitor contact structure and a capacitor pad, as a result, holes in the transistor are increased to increase the voltage in the transistor, and a voltage difference is produced between the transistor and the substrate to produce the floating gate effect.

In view of the above technical problems, in the method for manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, one end of the conductive structure is connected to the transistor, and when there are excess holes in the transistor, the holes can be transferred to the outside of the substrate by the conductive structure, thereby avoiding the floating gate effect between the substrate and the transistor and improving the performance of the semiconductor structure.

An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in <FIG> shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, and FIGS. <NUM> to <NUM> are schematic diagrams of various stages of the method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure will be introduced below in conjunction with FIGS. <NUM> to <NUM>.

This embodiment does not limit the semiconductor structure. The following will introduce the semiconductor structure by taking a Dynamic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment may also be other structure.

As shown in <FIG>, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:
Step S100: a substrate is provided, the substrate having a first surface and a second surface opposite to each other, and transistors being arranged on the second surface.

Exemplarily, as shown in <FIG> and <FIG>, the substrate <NUM> is used as a support component of the dynamic random access memory to support other components disposed thereon. The substrate <NUM> may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound and a silicon-carbon compound.

In a direction perpendicular to the substrate <NUM>, that is, the Y direction shown in the figures, the substrate <NUM> has a first surface <NUM> and a second surface <NUM> opposite to each other, wherein the first surface <NUM> may be understood as a top surface of the substrate <NUM>, and the second surface <NUM> may be understood as a bottom surface of the substrate <NUM>.

Exemplarily, as shown in <FIG>, an initial substrate <NUM> is provided, the initial substrate <NUM> having a first initial surface <NUM> and a second surface <NUM> opposite to each other;.

In a vertical direction where the first initial surface <NUM> points to the second surface <NUM>, part of the thickness of the initial substrate <NUM> is removed, the surface of the remaining of the initial substrate <NUM> forms the first surface <NUM>, and the remaining of the initial substrate <NUM> forms the substrate <NUM>.

That is, the first initial surface <NUM> may be planarized using a chemical mechanical polishing process, and remove part of the thickness of the initial substrate <NUM>, the remaining of the initial substrate <NUM> forms the substrate <NUM>, and the planarized first initial surface <NUM> forms the first surface <NUM>.

In this embodiment, a transistor <NUM> is further arranged on the second surface <NUM>. For example, an isolation structure <NUM> may be formed on the second surface through a deposition process, then the isolation structure <NUM> is patterned to form a plurality of trenches in the isolation structure <NUM>, the trenches are arranged at intervals in a first direction, that is, the X direction shown in <FIG>, a bit line structure <NUM> is formed in each trench, and a plurality of active columns arranged in an array are formed on the bit line structures <NUM>.

After the active columns are formed, a word line <NUM> extending in the first direction is formed on the isolation structure <NUM>, part of the word line <NUM> wraps a channel region <NUM> of each active column, and each active column and the word line <NUM> wrapping the active column constitute a transistor <NUM>.

An air gap layer <NUM> is further formed in the isolation structure <NUM>.

Step S200, release holes are formed in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface.

Illustratively, as shown in <FIG>, a mask layer <NUM> is formed on the first surface <NUM>. The mask layer <NUM> may be formed on the first surface <NUM> by a deposition process.

It should be noted that, in this embodiment, the mask layer <NUM> may be a single film layer or a laminated structure. When the mask layer <NUM> includes a laminated structure, the mask layer may include a first mask layer <NUM> and a second mask layer <NUM> laminated, the first mask layer <NUM> is arranged on a first dielectric layer <NUM>, and the first dielectric layer <NUM> may include a silicon oxide layer, wherein the material of the first mask layer <NUM> is different from the material of the second mask layer <NUM>, for example, the material of the first mask layer <NUM> may include amorphous carbon, and the material of the second mask layer <NUM> may include silicon oxynitride.

After the mask layer <NUM> is formed, a photoresist layer <NUM> may be formed on the mask layer <NUM> by coating, and then the photoresist layer is patterned by exposure, development, or etching to form a mask pattern in the photoresist layer <NUM>, wherein the mask pattern includes a plurality of first openings <NUM> and bumps <NUM> for separating the first openings <NUM>, the number of the first openings <NUM> corresponds to the number of the transistors <NUM> one to one, and the projection of the first opening <NUM> in the transistor <NUM> is located in a source <NUM> of the transistor <NUM>.

As shown in <FIG>, an oxide layer <NUM> is formed on side walls of the first openings <NUM>, the oxide layer <NUM> extends to the outside of the first openings <NUM> and cover the top surface of the mask layer <NUM>, and the oxide layer <NUM> located in the first openings <NUM> encloses second openings <NUM>, wherein the oxide layer <NUM> may be a silicon oxide layer.

For example, as shown in <FIG> , an initial oxide layer <NUM> may be formed on the side walls and bottom walls of the first openings <NUM> by an atomic layer deposition process, and the initial oxide layer <NUM> extends to the outside of the first openings <NUM> and covers the top surface of the mask layer <NUM>.

Then, the initial oxide layer <NUM> located on the bottom walls of the second openings <NUM> is removed with an etching gas or etching solution, and the remaining of the initial oxide layer <NUM> forms the oxide layer <NUM>, that is, the formed oxide layer <NUM> covers the top surfaces and side walls of the bumps <NUM>, wherein the oxide layer <NUM> located in the first openings <NUM> encloses the second openings <NUM>.

In this embodiment, the oxide layer <NUM> is formed to reduce the diameter of the first openings <NUM>, thereby reducing the diameter of the release holes <NUM>, reducing excessive damage to the transistors <NUM> by the release holes <NUM>, and ensuring the performance of the transistors <NUM>.

Finally, the mask layer <NUM>, the substrate <NUM>, the sources <NUM> of the transistors <NUM> and part of the channel regions <NUM> of the transistors <NUM> that are exposed in the second openings <NUM> are removed with the etching solution or etching gas, to form the release holes <NUM>, as shown in <FIG>.

It should be noted that, in this embodiment, a part of the release holes <NUM> are located in the transistors <NUM>, and the other part are located in the substrate <NUM>. In addition, in some embodiments, after the release holes <NUM> are formed, the photoresist layer <NUM>, the mask layer <NUM> and the oxide layer <NUM> need to be removed by dry or wet etching.

In this embodiment, the mask layer <NUM> is of a laminated structure. During pattern transfer, the second mask layer <NUM> may be first etched with the mask pattern formed by the bumps <NUM> covered with the oxide layer <NUM> as a mask, and form a patterned second mask layer <NUM>, and then the first mask layer <NUM>, the substrate <NUM> and the transistors <NUM> continue to be etched with the patterned second mask layer <NUM> as a mask, to form the release holes <NUM>.

In this embodiment, multiple times of pattern transfer can ensure the accuracy of the pattern finally transferred to the substrate <NUM> and the transistors <NUM>, and improve the accuracy of the release hole <NUM>.

In some embodiments, after the providing a substrate <NUM> and before the forming a mask layer <NUM> on the first surface <NUM>, the method for manufacturing a semiconductor structure further includes forming a first dielectric layer <NUM> on the first surface <NUM>, that is, the first dielectric layer <NUM> is arranged between the first surface <NUM> and the mask layer <NUM>.

In this embodiment, the first dielectric layer <NUM> is arranged on the first surface <NUM> to protect the substrate <NUM>, which can reduce lateral etching of the substrate <NUM> when the release holes <NUM> are formed, to improve the performance of the semiconductor structure.

Step S300, a conductive structure is formed in the release holes, the conductive structure extending to the outside of the release holes and covering the first surface of the substrate.

Exemplarily, as shown in <FIG>, first, a second initial dielectric layer <NUM> is formed in the release holes <NUM> by an atomic layer deposition process, the second initial dielectric layer <NUM> extending to the outside of the release holes <NUM> and covering the first dielectric layer <NUM>.

Then, the second initial dielectric layer <NUM> on the first dielectric layer <NUM> and the second initial dielectric layer <NUM> on the bottom of the release holes <NUM> are removed with an etching solution or etching gas, the remaining of the second initial dielectric layer <NUM> forms a second dielectric layer <NUM>, and the second dielectric layer <NUM> encloses intermediate holes <NUM> in the release holes <NUM>, as shown in <FIG>.

As shown in <FIG>, the conductive structure <NUM> is formed in the intermediate holes by a deposition process, the conductive structure <NUM> extending to the outside of the intermediate holes <NUM> and covering the first dielectric layer <NUM>, wherein the material of the conductive structure <NUM> may include conductive materials such as copper, aluminum or tungsten.

It should be noted that, in this embodiment, the deposition process may include an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process.

In the method for manufacturing a semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, one end of the conductive structure is connected to the transistors, and when there are excess holes in the transistors, the holes can be transferred to the outside of the substrate by the conductive structure, thereby avoiding the floating gate effect between the substrate and the transistors and improving the performance of the semiconductor structure.

As shown in <FIG>, an embodiment of the present disclosure further provides a semiconductor structure, including:.

The material of the conductive body <NUM> and the material of the conductive bumps <NUM> are metal materials, for example, the materials of the conductive body <NUM> and the conductive bumps <NUM> may include one of copper, aluminum, or tungsten.

In the semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, one end of the conductive structure is connected to the channel regions of the transistors, and when there are excess holes in the transistor, the holes can be transferred to the outside of the substrate by the conductive structure, thereby avoiding the floating gate effect between the substrate and the transistors and improving the performance of the semiconductor structure.

In some embodiments, the semiconductor structure further includes a first dielectric layer <NUM>, the first dielectric layer <NUM> is arranged between the first surface <NUM> and the conductive body <NUM>, and the ends of the conductive bumps <NUM> away from the conductive body <NUM> penetrate the first dielectric layer <NUM> and then are communicated with the channel regions <NUM> of the transistors <NUM>, wherein the material of the first dielectric layer <NUM> may include silicon oxide.

In this embodiment, the first dielectric layer <NUM> can avoid electrical connection of the conductive body <NUM> to other devices arranged in the substrate <NUM>, which ensures normal use of the semiconductor structure.

In some embodiments, the semiconductor structure further includes a second dielectric layer <NUM>, and the second dielectric layer <NUM> is arranged on the surfaces of the conductive bumps <NUM>, wherein the material of the second dielectric layer <NUM> may include silicon nitride.

In this embodiment, the second dielectric layer <NUM> can avoid electrical connection of the conductive bump <NUM> to a drain <NUM> of the transistor <NUM> or other devices arranged in the substrate <NUM>, which ensures the performance of the semiconductor structure.

In some embodiments, the substrate <NUM> is provided with a plurality of bit line structures <NUM> arranged in a row direction of the transistors <NUM>, the top surfaces of the bit line structures <NUM> are located on the second surface <NUM>, and the sources <NUM> of the transistors <NUM> are connected to the bit line structures <NUM>.

It should be noted that, in this embodiment, the row direction of the transistors <NUM> may be the X direction shown in the figures.

The plurality of bit line structures <NUM> may be arranged at intervals in the row direction of the transistors <NUM>, and the bit line structures <NUM> may extend in a column direction of the transistors <NUM>, that is, the bit line structures <NUM> may extend in a direction perpendicular to the X direction.

In some embodiments, the substrate <NUM> is formed with a plurality of word lines <NUM> arranged in the column direction of the transistors <NUM>, and the word lines <NUM> are configured to connect the channel regions <NUM> of the plurality of transistors <NUM>.

A third dielectric layer and an isolation layer stacked are formed on the word lines <NUM>, the third dielectric layer abuts against the word lines <NUM>, the third dielectric layer includes a silicon oxide layer, and the isolation layer includes a silicon nitride layer.

In some embodiments, a capacitor contact structure <NUM> is connected to the drain <NUM> of one of the transistor <NUM>, and a capacitor structure <NUM> is connected to the capacitor contact structure <NUM>, wherein the capacitor structure <NUM> includes an top electrode <NUM>, a dielectric layer <NUM> and a bottom electrode <NUM>, and a capacitor pad <NUM> may be connected to the bottom electrode <NUM>.

It should be noted that the capacitor structure <NUM> and the capacitor contact structure <NUM> are further provided with a plurality of support layers and third dielectric layers alternately arranged in sequence.

Exemplarily, the capacitor contact structure <NUM> includes a first contact structure <NUM> and a second contact structure <NUM> adhered, the end of the first contact structure <NUM> away from the second contact structure <NUM> is connected to the drain <NUM> of one of the transistor <NUM>, and the end of the second contact structure <NUM> away from the first contact structure <NUM> is connected to one of the capacitor structure <NUM>.

This embodiment realizes the connection between the capacitor structure and the drains of the transistors through the capacitor contact structure. During actual application, when data needs to be written into the capacitor structure, a voltage is applied to the word lines to open the channel regions of the transistors, so that the sources of the transistors are connected to the drains. At this time, the data on the word lines is transmitted to the drains by the sources, and then transmitted to the capacitor structure by the capacitor contact structure for storage.

In this embodiment, the first contact structure <NUM> may be in a regular shape, for example, a rectangular shape or a cylindrical shape, or in an irregular shape.

Exemplarily, the first contact structure <NUM> includes a first segment <NUM> and a second segment <NUM> connected to the first segment <NUM>, the end of the first segment <NUM> away from the second segment <NUM> is connected to the drain <NUM>, and the end of the second segment <NUM> away from the first segment <NUM> is connected to the second contact structure <NUM>.

Taking a plane perpendicular to the substrate <NUM> as the longitudinal section, the longitudinal section of the first segment <NUM> is a rectangle, and the longitudinal section of the second segment <NUM> is a trapezoid enlarged from top to bottom, which can increase the area of the first contact structure <NUM> to reduce the resistance of the first contact structure <NUM> and improve the sensitivity of signal transmission.

The second contact structure <NUM> includes a third segment <NUM> and a fourth segment <NUM> connected to the third segment <NUM>, the end of the third segment <NUM> away from the fourth segment <NUM> is connected to the first contact structure <NUM>, and the end of the fourth segment <NUM> away from the third segment <NUM> is connected to one end of the capacitor structure <NUM>.

Taking the plane perpendicular to the substrate <NUM> as the longitudinal section, the longitudinal section of the third segment <NUM> is a trapezoid reduced from top to bottom, and the longitudinal section of the fourth segment <NUM> is a rectangle, which can enlarge the contact area between the second contact structure <NUM> and the first contact structure <NUM> to reduce the contact resistance and improve the sensitivity of signal transmission.

In some embodiments, the first contact structure <NUM> has a first surface and a second surface opposite to each other, that is, the first surface forms one end of the first segment <NUM>, and the second segment forms the end of the second segment <NUM> away from the first segment <NUM>. The second contact structure <NUM> has a third surface and a fourth surface opposite to each other, that is, the third surface forms one end of the third segment <NUM>, and the fourth surface forms the end of the fourth segment <NUM> away from the third segment <NUM>. The second surface is connected to the drain <NUM> of one of the transistor <NUM>, the first surface is connected to the third surface, and the fourth surface is connected to one of the capacitor structure <NUM>. The projection area of the first surface on the substrate <NUM> is larger than the projection area of the third surface on the substrate <NUM>, which facilitates the alignment of the first contact structure <NUM> and the second contact structure <NUM>.

In the semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, one end of the conductive structure is connected to one of the channel region of the transistor, and when there are excess holes in the transistor, the holes can be transferred to the outside of the substrate by the conductive structure, thereby avoiding the floating gate effect between the substrate and the transistor and improving the performance of the semiconductor structure.

The embodiments or implementations in this specification are described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other.

In the description of this specification, the descriptions with reference to the terms "embodiment", "exemplary embodiment", "some implementations", "schematic implementation", "example", etc. mean that specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application.

In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are intended to facilitate the description of the present disclosure and simplify the description only, rather than indicating or implying that the device or element referred to must have a particular orientation or be constructed and operated in a particular orientation, and will not to be interpreted as limiting the present disclosure.

It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only configured to distinguish the first structure from another structure.

In one or more drawings, the same elements are represented by similar reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure are described below, such as the structure, material, dimension, treatment process and technology of devices, in order to understand the present disclosure more clearly. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details.

Finally, it should be noted that the above embodiments are merely configured to describe, but not to limit, the technical solutions of the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that various modifications may be made to the technical solutions described in the foregoing embodiments, or substitutions may be made to some or all technical features thereof, and these modifications or substitutions do not make the technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure.

Claim 1:
A method for manufacturing a semiconductor structure, comprising:
providing a substrate (<NUM>), the substrate (<NUM>) having a first surface (<NUM>) and a second surface (<NUM>) opposite to each other, and transistors (<NUM>) being arranged on the second surface (<NUM>) (S100), and each of the transistors (<NUM>) includes a source (<NUM>), a channel region (<NUM>), a drain (<NUM>) and a word line (<NUM>) surrounding the channel region (<NUM>); wherein capacitor contact structures (<NUM>) are connected to drains (<NUM>) of the transistors (<NUM>), and capacitor structures (<NUM>) are connected to the capacitor contact structures (<NUM>);
characterized in that
forming release holes (<NUM>) in the substrate (<NUM>), each of the release holes (<NUM>) extending into each of a plurality of bit line structures (<NUM>), and into the source (<NUM>) of the transistor (<NUM>),
bottoms of the release holes (<NUM>) being arranged in channel regions (<NUM>) of the transistors (<NUM>), and top surfaces of the release holes (<NUM>) being flush with the first surface (<NUM>) (S200); and
forming a conductive structure (<NUM>) in the release holes (<NUM>), the conductive structure (<NUM>) extending to the outside of the release holes (<NUM>) and covering the first surface (<NUM>) of the substrate (<NUM>) (S300).