Patent Description:
<CIT> describes on-die termination (ODT) control which enables programmable ODT latency settings.

Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory cell. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and others. Memory devices may be volatile or non-volatile. Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.

The invention is as defined in the independent claims <NUM> and <NUM>. Preferred embodiments are set out by the dependent claims.

Memory devices and memory systems can include multiple separately-addressable memory arrays, ranks, banks, channel, or other sub-divisions of memory capacity. In some such devices and systems, multiple separately-addressable memory portions may have terminals connected to one or more common busses (e.g., a data bus, a command/address bus, a clock signal bus, etc.). To improve the signal quality on a bus during communication with one of the separately-addressable portions, one or more terminals of another non-communicating memory portion may enter an "on-die termination" (ODT) mode, in which the impedance at the one or more terminals of the non-communicating portion is modified (e.g., to minimize signal reflections or other potentially signal-degrading or noise-contributing effects).

In some memory systems, a connected host device can indicate to the non-communicating (e.g., non-targeted) memory portion to enter an on-die termination mode with a command (e.g., on a command/address bus) addressed specifically to the non-targeted memory portion. Each command to enter an ODT mode can cause a command decoder of the non-targeted memory portion to consume power in decoding the command, which can contribute to a significant increase in the power consumption of a memory system. It is therefore desirable to provide a way to manage the ODT modes of a memory system with greater power efficiency.

Accordingly, several embodiments of the present invention are directed to memory devices, systems including memory devices, and methods of operating memory devices in which on-die termination can be provided at a second portion during multiple communications at a first portion, without requiring multiple on-die termination commands to be provided to or decoded by the second portion. In one embodiment, a method may comprise receiving a first command instructing a first memory device to perform a first communication and instructing a second memory device to enter an on-die termination mode, performing, with the first memory device, the first communication while the second memory device is in the on-die termination mode based on the first command, receiving a second command instructing the first memory device to perform a second communication with the memory host, and performing, with the first memory device, the second communication while the second memory device is in the on-die termination mode based on the first command.

<FIG> is a block diagram schematically illustrating a memory device <NUM>. The memory device <NUM> may include an array of memory cells, such as memory array <NUM>. The memory array <NUM> may include a plurality of banks (e.g., banks <NUM>-<NUM> in the example of <FIG>), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. The selection of a word line WL may be performed by a row decoder <NUM>, and the selection of a bit line BL may be performed by a column decoder <NUM>. Sense amplifiers (SAMP) may be provided for corresponding bit lines BL and connected to at least one respective local I/O line pair (LIOT/B), which may in turn be coupled to at least respective one main I/O line pair (MIOT/B), via transfer gates (TG), which can function as switches.

The memory device <NUM> may employ a plurality of external terminals that include command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal to receive a chip select signal CS, clock terminals to receive clock signals CK and CKF, data clock terminals to receive data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, VDDQ, and VSSQ.

The command terminals and address terminals may be supplied with an address signal and a bank address signal from outside. The address signal and the bank address signal supplied to the address terminals can be transferred, via a command/address input circuit <NUM>, to an address decoder <NUM>. The address decoder <NUM> can receive the address signals and supply a decoded row address signal (XADD) to the row decoder <NUM>, and a decoded column address signal (YADD) to the column decoder <NUM>. The address decoder <NUM> can also receive the bank address signal (BADD) and supply the bank address signal to both the row decoder <NUM> and the column decoder <NUM>.

The command and address terminals may be supplied with command signals CMD, address signals ADDR, and chip selection signals CS, from a memory controller. The command signals may represent various memory commands from the memory controller (e.g., including access commands, which can include read commands and write commands). The select signal CS may be used to select the memory device <NUM> to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device <NUM>, the commands and addresses can be decoded and memory operations can be performed. The command signals CMD may be provided as internal command signals ICMD to a command decoder <NUM> via the command/address input circuit <NUM>. The command decoder <NUM> may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations, for example, a row command signal to select a word line and a column command signal to select a bit line. The internal command signals can also include output and input activation commands, such as clocked command CMDCK.

When a read command is issued and a row address and a column address are timely supplied with the read command, read data can be read from memory cells in the memory array <NUM> designated by these row address and column address. The read command may be received by the command decoder <NUM>, which can provide internal commands to input/output circuit <NUM> so that read data can be output from the data terminals DQ, RDQS, DBI, and DMI via read/write amplifiers <NUM> and the input/output circuit <NUM> according to the RDQS clock signals. The read data may be provided at a time defined by read latency information RL that can be programmed in the memory device <NUM>, for example, in a mode register (not shown in <FIG>). The read latency information RL can be defined in terms of clock cycles of the CK clock signal. For example, the read latency information RL can be a number of clock cycles of the CK signal after the read command is received by the memory device <NUM> when the associated read data is provided.

When a write command is issued and a row address and a column address are timely supplied with the command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder <NUM>, which can provide internal commands to the input/output circuit <NUM> so that the write data can be received by data receivers in the input/output circuit <NUM>, and supplied via the input/output circuit <NUM> and the read/write amplifiers <NUM> to the memory array <NUM>. The write data may be written in the memory cell designated by the row address and the column address. The write data may be provided to the data terminals at a time that is defined by write latency WL information. The write latency WL information can be programmed in the memory device <NUM>, for example, in the mode register (not shown in <FIG>). The write latency WL information can be defined in terms of clock cycles of the CK clock signal. For example, the write latency information WL can be a number of clock cycles of the CK signal after the write command is received by the memory device <NUM> when the associated write data is received.

The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to an internal voltage generator circuit <NUM>. The internal voltage generator circuit <NUM> can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the row decoder <NUM>, the internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array <NUM>, and the internal potential VPERI can be used in many other circuit blocks.

The power supply terminal may also be supplied with power supply potential VDDQ. The power supply potential VDDQ can be supplied to the input/output circuit <NUM> together with the power supply potential VSS. The power supply potential VDDQ can be the same potential as the power supply potential VDD. The power supply potential VDDQ can be a different potential from the power supply potential VDD in another embodiment of the present invention. However, the dedicated power supply potential VDDQ can be used for the input/output circuit <NUM> so that power supply noise generated by the input/output circuit <NUM> does not propagate to the other circuit blocks.

The clock terminals and data clock terminals may be supplied with external clock signals and complementary external clock signals. The external clock signals CK, CKF, WCK, WCKF can be supplied to a clock input circuit <NUM>. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and transition between the opposite clock levels at the same time. For example, when a clock signal is at a low clock level a complementary clock signal is at a high level, and when the clock signal is at a high clock level the complementary clock signal is at a low clock level. Moreover, when the clock signal transitions from the low clock level to the high clock level the complementary clock signal transitions from the high clock level to the low clock level, and when the clock signal transitions from the high clock level to the low clock level the complementary clock signal transitions from the low clock level to the high clock level.

Input buffers included in the clock input circuit <NUM> can receive the external clock signals. For example, when enabled by a CKE signal from the command decoder <NUM>, an input buffer can receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit <NUM> can receive the external clock signals to generate internal clock signals ICLK. The internal clock signals ICLK can be supplied to an internal clock circuit <NUM>. The internal clock circuit <NUM> can provide various phase and frequency controlled internal clock signal based on the received internal clock signals ICLK and a clock enable signal CKE from the command/address input circuit <NUM>. For example, the internal clock circuit <NUM> can include a clock path (not shown in <FIG>) that receives the internal clock signal ICLK and provides various clock signals to the command decoder <NUM>. The internal clock circuit <NUM> can further provide input/output (<NUM>) clock signals. The IO clock signals can be supplied to the input/output circuit <NUM> and can be used as a timing signal for determining an output timing of read data and the input timing of write data. The <NUM> clock signals can be provided at multiple clock frequencies so that data can be output from and input to the memory device <NUM> at different data rates. A higher clock frequency may be desirable when high memory speed is desired. A lower clock frequency may be desirable when lower power consumption is desired. The internal clock signals ICLK can also be supplied to a timing generator <NUM> and thus various internal clock signals can be generated.

Memory devices such as the memory device <NUM> of <FIG> can provide memory capacity with multiple memory arrays, or with a single array that is subdivided into multiple separately-addressable portions (e.g., into multiple channels, banks, ranks, etc.). Alternatively, a memory system can include multiple memory devices such as the memory device <NUM> of <FIG>, where each memory device represents a separately-addressable sub-division (e.g., rank, etc.) of the memory capacity of the system. Accordingly, a memory device or a memory system with multiple memory devices, ranks, channels, banks or the like can include multiple terminals (e.g., clock terminals, CMD/ADD terminals, I/O terminals, etc.) that are dedicated to one or more, but less than all of, the separately-addressable portions. For example, a multichannel memory device can include multiple terminals, each corresponding to one of the multiple channels of memory. When operating such a memory device, to reduce undesirable noise on a common signal path (e.g., a clock path, a data bus, etc.), the memory device can utilize on-die termination to provide proper impedance at those terminals of the memory device corresponding to the separately-addressable portions of memory that are not communicating on the common signal path. For example, when a connected host or memory controller accesses a first channel of the memory device, terminals of the memory device corresponding to a second channel can be provided with proper impedance by on-die termination circuitry (e.g., integral to a corresponding i/o circuit <NUM>, clock input circuit <NUM>, or the like).

One approach to initiating on-die termination includes a host providing a signal (e.g., via a dedicated or shared pin or terminal) or command (e.g., via the command/address bus) to the non-targeted portion of the memory device to provide termination during a communication performed by a targeted portion of the memory device. For example, a command on a shared command/address bus can indicate to both the targeted and non-targeted portion that a communication (e.g., a read operation, a write operation, an erase operation, a status inquiry operation, etc.) is to be performed, while dedicated chip select terminals for each portion can indicate which portion is targeted (e.g., by a pulse lasting a single clock cycle) and which is non-targeted (e.g., by a pulse lasting two clock cycles). Such an approach is illustrated schematically in the timing diagram <NUM> of <FIG>.

As can be seen with reference to <FIG>, in a memory device or system with two or more separately-addressable portions (e.g., two channels of a memory device, two memory devices of a memory system, etc.), a common command/address bus <NUM> can be used to indicate to the portions that a communication is to be performed by one of the portions (e.g., via a read command). A dedicated chip select terminal for each portion (e.g., CS_A <NUM> and CS_B <NUM>) can be used to provide an indication to each portion whether it is targeted or non-targeted for the communication. In response to receiving an indication that is not the target of a command to communicate, the non-targeted portion can enter an on-die termination mode for the duration of the communication. In this regard, the timing diagram <NUM> of <FIG> illustrates a sequence of read commands targeting different channels of a memory device.

As illustrated, the first read command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the first read command corresponds to the first channel <NUM> of the memory device (e.g., by pulsing a chip select line low for one cycle of a clock <NUM> to indicate the targeted portion, and for two cycles of the clock <NUM> to indicate the non-targeted portion). Accordingly, the second channel <NUM> of the memory device enters an on-die termination mode <NUM> for the duration of a communication <NUM> of the first channel <NUM>. Following the communication <NUM>, the second channel <NUM> returns to a default or "parked" mode of impedance. A second read command <NUM> is similarly sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the second read command corresponds to the first channel <NUM> of the memory device. Accordingly, the second channel <NUM> of the memory device enters an on-die termination mode <NUM> for the duration of a communication <NUM> of the first channel <NUM>. Following the communication <NUM>, the second channel <NUM> returns to the parked mode of impedance. A third read command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the third read command corresponds to the second channel <NUM> of the memory device. Accordingly, the first channel <NUM> of the memory device enters an on-die termination mode <NUM> for the duration of a communication <NUM> of the second channel <NUM>. Following the communication <NUM>, the first channel <NUM> returns to the parked mode of impedance.

A drawback to this approach of providing on-die termination commands to a non-targeted memory portion with each command to a targeted portion (e.g., with a corresponding indication on a chip select terminal) is that the non-targeted memory portion consumes power in decoding each command. In this regard, the command decoder of a memory device (e.g., command decoder <NUM>) may be configured to "wake up" (e.g., to deliver power or signal voltages to one or more components previously in a no-power, low-power, or signal-disconnected state) in response to pulsing a corresponding chip select line low (e.g., whether for one or two clock cycles). Moreover, alternating the impedance from a parked mode to a termination mode (e.g., a read termination mode, a write termination mode, etc.) and back may further consume additional power. Accordingly, embodiments of the present invention may solve the foregoing problems by providing on-die termination at a non-targeted memory portion without the power consumption caused by decoding a non-targeted communication (e.g., read, write, status, etc.) command. Rather, in one embodiment, a memory portion can be configured to provide on-die termination in response to a command received in connection with a previous communication command.

Turning to <FIG>, a simplified timing diagram <NUM> schematically illustrates the operation of a memory system. As can be seen with reference to <FIG>, in a memory device or system with two or more separately-addressable portions (e.g., two channels of a memory device, two memory devices of a memory system), a common command/address bus <NUM> can be used to indicate to the portions that a communication is to be performed by one of the portions (e.g., via a read command). Unlike the approach illustrated in <FIG>, however, in the approach illustrated in <FIG>, in response to an indication to a memory portion that it is not the target of a communication, the memory portion enters and remains in an on-die termination mode until receiving a subsequent indication or command to exit the on-die termination mode.

In the example of <FIG>, a first read command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the first read command corresponds to the first channel <NUM> of the memory device (e.g., by pulsing a chip select line low for one cycle of a clock <NUM> to indicate the targeted portion, and for two cycles of the clock <NUM> to indicate the non-targeted portion). Accordingly, the second channel <NUM> of the memory device enters an on-die termination mode <NUM> for the duration of a communication <NUM> of the first channel <NUM>. Rather than returning to a parked mode of impedance following the completion of the communication <NUM>, however, the second channel <NUM> remains in the on-die termination mode <NUM>. Accordingly, during subsequent communications for which the second channel remains non-targeted, no further indications need be sent to nor commands decoded by the second channel to provide on-die termination thereat.

According to the invention as defined in the claims, as can be seen with reference to <FIG>, a second read command <NUM> is sent with an indication <NUM> on the chip select terminal <NUM> that the target of the second read command corresponds to the first channel <NUM> of the memory device. No indication is sent on the chip select terminal <NUM> corresponding to the second channel <NUM>, however, ensuring that the command decoder of the second channel need not consume power processing the command <NUM>. Rather, the second channel <NUM> of the memory device remains in the on-die termination mode <NUM> initiated for the earlier communication <NUM>, and continues to provide termination for the duration of a communication <NUM> of the first channel <NUM>. When a third read command <NUM> is subsequently sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the third read command corresponds to the second channel <NUM> of the memory device (e.g., by pulsing a chip select line low for one cycle of a clock <NUM> to indicate the targeted portion, and for two cycles of the clock <NUM> to indicate the non-targeted portion), the second channel <NUM> of the memory device exits the on-die termination mode <NUM> and performs the communication <NUM>, and the first channel <NUM> of the memory device enters an on-die termination mode <NUM> (e.g., and may be, like the second channel <NUM>, configured to remain therein until receiving a command to exit the on-die termination mode <NUM>).

Although in the foregoing example embodiment, the on-die termination mode <NUM> is illustrated and described as persisting for the duration of two communications, in other embodiments a persistent on-die termination mode can last for many more communications (e.g., and/or for extended periods during which no communication are taking place). In this regard, a persistent on-die termination mode can be configured to persist until a command (e.g., a communication command targeting the memory portion providing termination, or a command to exit the termination mode without communicating) is received. For each communication for which a memory portion provides termination without requiring the consumption of power in decoding an on-die termination command, the power savings of the present approach will be increased, as compared to the approach illustrated in <FIG>.

In accordance with another aspect of the present disclosure, a persistent on-die termination mode can remain in effect until one or more of a number of different criteria for ending the mode are met. In this regard, a persistent on-die termination can be configured to persist until the receipt of (i) a read command targeting the addressed to the memory portion, (ii) a write command addressed to the terminated memory portion, (iii) a non-targeted termination command addressed to the memory portion (e.g., with a different termination level), (iv) a command to exit the termination mode, or (v) a self-refresh command. In one embodiment, a command to exit the termination mode (a "TermOFF" command) can be executed based on a predetermined delay (e.g., as configured in a predetermined mode register) to facilitate scheduling. In some embodiments, a TermOFF command can be provided immediately following a column access select ("CAS") command to a different memory portion, such that execution of the TermOFF command following the predetermined delay can ensure a change in the termination mode corresponds in time with the execution of the CAS command. The TermOFF command can be either a single-clock-cycle command or a multiple-clock-cycle command.

Turning to <FIG>, a simplified timing diagram <NUM> schematically illustrates the operation of a memory system. As can be seen with reference to <FIG>, in a memory device or system with two or more separately-addressable portions (e.g., two channels of a memory device, two memory devices of a memory system), a common command/address bus <NUM> can be used to indicate to the portions that a communication is to be performed by one of the portions (e.g., via a read command). Unlike the approach illustrated in <FIG>, however, in the approach illustrated in <FIG>, in response to an indication to a memory portion that it is not the target of a communication, the memory portion enters an on-die termination mode to which it reverts following subsequent commands to communicate (e.g., unless instructed otherwise).

In the example of <FIG>, a first read command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the first read command corresponds to the first channel <NUM> of the memory device (e.g., by pulsing a chip select line low for one cycle of a clock <NUM> to indicate the targeted portion, and for two cycles of the clock <NUM> to indicate the non-targeted portion). Accordingly, the second channel <NUM> of the memory device enters an on-die termination mode <NUM> at least for the duration of a communication <NUM> of the first channel <NUM>. When a second read command <NUM> is sent with indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the second read command corresponds to the second channel <NUM> of the memory device, the first channel <NUM> of the memory device enters an on-die termination mode <NUM> at least for the duration of a communication <NUM> of the second channel <NUM>. Because the second channel <NUM> is configured to revert to its previous on-die termination mode following the completion of the communication <NUM>, no subsequent indication need be sent on the corresponding chip select terminal <NUM>, and the second channel <NUM> of the memory device reverts to an on-die termination mode <NUM> rather than a parked mode of termination. Accordingly, when a third read command <NUM> is sent with an indication <NUM> on the chip select terminal <NUM> that the target of the third read command corresponds to first channel <NUM> of the memory device, no indication is sent on the second chip select terminal <NUM>, as the second channel <NUM> has already reverted to the on-die termination mode <NUM>, which provides the desired termination while the first channel <NUM> of the memory device performs the commanded communication <NUM>.

Although in the foregoing example embodiments, the communications performed by one memory portion while another is in an on-die termination mode have been described and illustrated as read operations (e.g., with corresponding read levels of on-die termination), in other embodiments of the present invention, the foregoing and following approaches can similarly be applied to other communications (e.g., write operations, status operations, etc.), with corresponding levels of termination (e.g., non-targeted write level termination, non-targeted status level termination, etc.).

For example, turning to <FIG>, a simplified timing diagram <NUM> schematically illustrates the operation of a memory system. As can be seen with reference to <FIG>, in a memory device or system with two or more separately-addressable portions (e.g., two channels of a memory device, two memory devices of a memory system), a common command/address bus <NUM> can be used to indicate to the portions that a communication is to be performed by one of the portions (e.g., via a write command).

In the approach illustrated in <FIG>, in response to an indication to a memory portion that it is not the target of a communication, the memory portion enters an on-die termination mode in which it remains for an indicated duration (e.g., for an indicated number of subsequent communications). In this regard, a first write command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the first read command corresponds to the first channel <NUM> of the memory device (e.g., by pulsing a chip select line low for one cycle of a clock <NUM> to indicate the targeted portion, and for two cycles of the clock <NUM> to indicate the non-targeted portion). The write command <NUM> can include an indication (e.g., in otherwise-unused bits on the command/address bus <NUM>) to the non-targeted portion of the memory device to provide on-die termination for a number of subsequent communications (e.g., in the illustrated example, for two communications). Accordingly, the second channel <NUM> of the memory device enters an on-die termination mode <NUM> and the first channel <NUM> performs a communication <NUM> (e.g., the requested write operation).

In the example of <FIG>, a second write command <NUM> is sent with an indication <NUM> on the chip select terminal <NUM> that the target of the second write command corresponds to the first channel <NUM> of the memory device. Because the second channel <NUM> was previously commanded (e.g., by write command <NUM>) to remain in the on-die termination mode <NUM> for the duration of two communication events, no subsequent indication need be sent on the corresponding chip select terminal <NUM>, and the second channel <NUM> continues to provide termination during the second communication <NUM>. Following the completion of the second communication <NUM>, the on-die termination mode <NUM> is exited, and the second channel reverts to a default "parked" mode of termination. When a third read command <NUM> is sent with corresponding indications <NUM> and <NUM> on the chip select terminals <NUM> and <NUM> that the target of the third read command corresponds to the second channel <NUM> of the memory device, the first channel <NUM> of the memory device enters an on-die termination mode <NUM> for the duration of a communication <NUM> of the second channel <NUM>. Following the termination mode <NUM>, the first channel <NUM> returns to the parked mode of impedance.

The approach of reverting to a previous on-die termination mode can be combined with the approach of instructing on-die termination to last for a predetermined number of communications (e.g., by instructing a memory portion to provide write-level on-die termination for three communications, after which the memory portion reverts to a previous on-die termination mode, such as a read-level on-die termination).

Although in the foregoing example embodiments, memory devices and systems with just two memory portions (e.g., and just two corresponding chip select terminals) have been illustrated, the foregoing approaches to on-die termination have application to memory devices and systems with more than two channels or other sub-addressable portions. As will be readily understood by those skilled in the art, the power-saving benefits of these approaches will be even greater for devices in which more on-die termination commands corresponding to a single communication command can be omitted.

<FIG> is a simplified block diagram schematically illustrating a memory system <NUM>. Memory system <NUM> includes a host device <NUM> operably coupled to a memory module <NUM> (e.g., a dual in-line memory module (DIMM)). Memory module <NUM> can include a controller <NUM> operably connected by a bus <NUM> to a plurality of memory devices <NUM>. In accordance with one embodiment of the present disclosure, the host device <NUM> can communicate with a first one of the memory devices <NUM> (e.g., via a read command, a write command, etc. communicated over the bus <NUM>), and with one or more of the other memory devices <NUM> to transmit an on-die termination signal (e.g., such as on-die termination signal <NUM> in timing diagram <NUM>, on-die termination signal <NUM> in timing diagram <NUM>, or on-die termination signal <NUM> in timing diagram <NUM>). In an alternative embodiment, the controller <NUM> can communicate with a first one of the memory devices <NUM> (e.g., via a read command, a write command, etc. communicated over the bus <NUM>), and with one or more of the other memory devices <NUM> to transmit an on-die termination signal (e.g., such as on-die termination signal <NUM> in timing diagram <NUM>, on-die termination signal <NUM> in timing diagram <NUM>, or on-die termination signal <NUM> in timing diagram <NUM>). In this regard, the controller <NUM> can intermediate between the host device <NUM> (e.g., which may send a communication (e.g., read, write, etc.) command to a targeted memory device concurrently with an ODT command directed at the non-targeted memory devices) and the memory devices <NUM> to provide the command to the targeted memory device with either a modified ODT command (e.g., indicating a duration corresponding to multiple communication events) or without providing the ODT command to the other memory devices (e.g., relying instead on the non-targeted memory device to either remain in a previously-commanded ODT mode or to revert to a previously-commanded ODT mode).

<FIG> is a flow chart illustrating a method of operating a memory system. The method includes receiving a first command instructing a first memory device of the memory system to perform a first communication and instructing a second memory device of the memory system to enter an on-die termination mode (box <NUM>). According to one aspect of the present disclosure, the command receiving features of box <NUM> may be implemented with a command/address input circuit <NUM> and/or terminals connected thereto, as illustrated in <FIG> in greater detail, above.

The method further includes performing, with the first memory device, the first communication while the second memory device is in the on-die termination mode based at least in part on the first command (box <NUM>). According to one aspect of the present disclosure, the communication features of box <NUM> may be implemented with a memory array <NUM>, decoders (e.g., address decoder <NUM>, command decoder <NUM>, row decoder <NUM>, column decoder <NUM>, etc.) connected thereto, and/or IO circuit <NUM>, as illustrated in <FIG> in greater detail, above.

The method further includes receiving a second command instructing the first memory device to perform a second communication with the memory host (box <NUM>), and performing, with the first memory device, the second communication while the second memory device is in the on-die termination mode based at least in part on the first command (box <NUM>). According to one aspect of the present disclosure, the command receiving and communication features of boxes <NUM> and <NUM> may be implemented with a command/address input circuit <NUM> and/or terminals connected thereto, a memory array <NUM>, decoders (e.g., address decoder <NUM>, command decoder <NUM>, row decoder <NUM>, column decoder <NUM>, etc.) connected thereto, and/or IO circuit <NUM>, as illustrated in <FIG> in greater detail, above.

<FIG> is a flow chart illustrating a method of operating a memory device. The method includes receiving a first command at the memory device instructing the first portion to perform a first communication and instructing the second portion to enter an on-die termination mode (box <NUM>). According to one aspect of the present disclosure, the command receiving features of box <NUM> may be implemented with a command/address input circuit <NUM> and/or terminals connected thereto, as illustrated in <FIG> in greater detail, above.

The method further includes maintaining, at the second portion, the on-die termination mode until receiving a second command instructing the second portion to exit the on-die termination mode (box <NUM>). According to one aspect of the present disclosure, the on-die termination mode maintaining features of box <NUM> may be implemented with a command/address input circuit <NUM>, a clock input circuit <NUM>, an IO circuit <NUM>, and/or any terminals connected thereto, as illustrated in <FIG> in greater detail, above.

<FIG> is a flow chart illustrating a method of operating a memory device. The method includes receiving a command at the memory device instructing a first portion of the memory device to perform a communication (box <NUM>). According to one aspect of the present disclosure, the command receiving features of box <NUM> may be implemented with a command/address input circuit <NUM> and/or terminals connected thereto, as illustrated in <FIG> in greater detail, above.

The method further includes performing the communication at the first portion of the memory device (box <NUM>), and reverting, at the first portion of the memory device, to an on-die termination mode active at the first portion prior to performing the communication (box <NUM>). According to one aspect of the present disclosure, the communication performing features and on-die termination mode reverting features of boxes <NUM> and <NUM> may be implemented with a memory array <NUM>, decoders (e.g., address decoder <NUM>, command decoder <NUM>, row decoder <NUM>, column decoder <NUM>, etc.) connected thereto, input circuits (e.g., command/address input circuit <NUM>, clock input circuit <NUM>, etc.), and/or IO circuit <NUM>, as illustrated in <FIG> in greater detail, above.

<FIG> is a flow chart illustrating a method of operating a memory device. The method includes receiving a command at the memory device instructing a first portion of the memory device to perform a communication having a first duration and instructing a second portion of the memory device to enter an on-die termination mode having a second duration (box <NUM>). According to one aspect of the present disclosure, the command receiving features of box <NUM> may be implemented with a command/address circuit <NUM> and/or terminals connected thereto, as illustrated in <FIG> in greater detail, above.

The method further includes performing the communication at the first portion of the memory device (box <NUM>), and maintaining, at the second portion, the on-die termination mode for the second duration, wherein the second duration is greater than the first duration (box <NUM>). According to one aspect of the present disclosure, the communication performing features and on-die termination mode maintaining features of boxes <NUM> and <NUM> may be implemented with a memory array <NUM>, decoders (e.g., address decoder <NUM>, command decoder <NUM>, row decoder <NUM>, column decoder <NUM>, etc.) connected thereto, input circuits (e.g., command/address input circuit <NUM>, clock input circuit <NUM>, etc.), and/or IO circuit <NUM>, as illustrated in <FIG> in greater detail, above.

The devices discussed herein, including a memory device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

Claim 1:
A method of operating a memory system (<NUM>), comprising:
receiving a first command instructing a first memory device (<NUM>) of the memory system to perform a first communication with a memory host (<NUM>) and instructing a second memory device (<NUM>) of the memory system to enter an on-die termination mode;
performing, with the first memory device, the first communication while the second memory device is in the on-die termination mode based on the first command;
receiving a second command instructing the first memory device to perform a second communication with the memory host; and
performing, with the first memory device, the second communication while the second memory device remains in the on-die termination mode based on the first command.