Patent Description:
<CIT>) describes a switch for turning on/off the connection between a first terminal and a second terminal. The switch includes a first transistor circuit configured from two transistors connected in series between the first terminal and the second terminal; and a second transistor circuit having a gate terminal connected to source terminals of the two transistors and a source terminal connected to gate terminals of the two transistors. The connection between the first terminal and the second terminal is changed over between on and off states by changing over a potential to the source terminal of the second transistor circuit between high and low levels.

The invention relates to a switch according to independent claim <NUM>.

In one or more embodiments the switching arrangement may be configured to:.

In one or more embodiments the switching arrangement may comprise:.

In one or more embodiments a voltage of the first reference voltage terminal may be greater than a voltage of the second reference voltage terminal. The first MOS transistor, the second MOS transistor and the third MOS transistor may be NMOS transistors.

In one or more embodiments the switching arrangement may comprise a fourth NMOS transistor having a gate terminal configured to receive the state signalling. A conduction channel of the fourth NMOS transistor and the second current source may be coupled in series between the source terminal of the third MOS transistor and the second reference voltage terminal.

In one or more embodiments the first current source may comprise an output PMOS transistor of a PMOS current mirror.

In one or more embodiments the switching arrangement may comprise a fifth NMOS transistor having a gate terminal configured to receive the state signalling. A conduction channel of the fifth NMOS transistor, a conduction channel of an input PMOS transistor of the PMOS current mirror and a primary current source may be coupled in series between the first reference voltage terminal and the second reference voltage terminal such that the PMOS current mirror is configured to mirror a current of the primary current source from the input PMOS transistor to the output PMOS transistor to produce the first current.

In one or more embodiments a voltage of the first reference voltage terminal may be less than a voltage of the second reference voltage terminal. The first MOS transistor, the second MOS transistor and the third MOS transistor may be PMOS transistors.

In one or more embodiments the switching arrangement may comprise a fourth NMOS transistor having a gate terminal configured to receive the state signalling. A conduction channel of the fourth NMOS transistor and the first current source may be coupled in series between the first reference voltage terminal and the common gate terminal.

In one or more embodiments the second current source may comprise an output PMOS transistor of a PMOS current mirror.

In one or more embodiments the switching arrangement may comprise a fifth NMOS transistor having a gate terminal configured to receive the state signalling. A conduction channel of an input PMOS transistor of the PMOS current mirror, a primary current source and the conduction channel of the fifth NMOS transistor may be coupled in series between the first reference voltage terminal and the second reference voltage terminal such that the PMOS current mirror is configured to mirror a current of the primary current source from the input PMOS transistor to the output PMOS transistor to produce the second current.

In one or more embodiments the switch may be an analog switch.

According to a second aspect of the present disclosure there is provided a high voltage multiplexer comprising any of the switches disclosed herein.

According to a further aspect of the present disclosure there is provided a battery management system comprising any of the switches disclosed herein or any of the high voltage multiplexers disclosed herein.

It should be understood, however, that the scope of protection is defined solely by the appended claims.

The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

High voltage battery management systems (BMSs) can be required in applications having a plurality of battery cells assembled together to form a battery pack. One such application is in the battery packs of electric and hybrid vehicles. BMSs may have a requirement to monitor and manage the performance of the individual battery cells of the stacked cell battery packs. For example, BMSs can be required to measure stacked cell voltages corresponding to the voltages of individual battery cells and of various combinations of the individual cells. BMS ICs can employ switches to multiplex the cell voltages to an analog to digital converter (ADC).

Previous generations of high-voltage BMSs used low-voltage (LV) multiplexers that were limited to multiplexing two cells together at a maximum voltage of 10V. Each LV multiplexer would connect the successive cells to a level shifter. Therefore, for a battery pack containing <NUM> cells, <NUM> level shifters were required between the LV multiplexers and the ADC.

<FIG> illustrates a BMS <NUM> with an improved BMS integrated circuit (IC) <NUM> incorporating a high voltage (HV) multiplexer <NUM> that can multiplex a wide range of differential voltages to a shared bus. The BMS IC <NUM> may only have one or two level shifters (not shown) resulting in a significant reduction in required die area compared to LV multiplexer solutions.

The HV multiplexer <NUM> comprises a plurality of analog switches <NUM>. Each analog switch <NUM> may be coupled to a corresponding battery cell of a battery pack <NUM> (individual connections not illustrated in <FIG> but are contained within connection labelled N). Each battery cell may be connected to two analog switches <NUM> such that each battery cell may contribute to a high side voltage and / or a low side voltage of a differential voltage. In this way, the HV multiplexer <NUM> can multiplex a wide range of differential voltage to a shared bus, which is then converted by an ADC <NUM> for measurement.

The high-voltage analog switches <NUM> can be controlled by current sources to enable operation over a wide range of common mode voltages (VCM). This is in contrast to a LV switch design driven by a fixed voltage.

The BMS IC <NUM> can convert and sense each cell voltage through a corresponding low pass RC filter <NUM> with a high level of accuracy. However, any control current of the analog switch <NUM> that is injected into the channel path of the analog switch <NUM> can lead to measurement inaccuracies. For example, the injected current may cause an error voltage across the switch <NUM> drain-source on resistance (Rdson) or across the low pass RC filter <NUM>.

Therefore, analog switches <NUM> that can provide a low level of control current injection into the channel path can provide greater measurement accuracy.

When the BMS IC <NUM> is not converting or sensing cell voltages, for example in a sleep mode, current consumption of the BMS IC <NUM> should be kept as low as possible. As the BMS IC <NUM> comprises a plurality of analog switches <NUM>, any current consumption of the analog switch <NUM> in the OFF state will be multiplied up several-fold. Therefore, the current consumption of the analog switches <NUM> should be as low as possible when channels are switched off.

The present disclosure provides a high-voltage switch that: (i) injects zero or minimal control current into a channel path of the switch; and (ii) consumes zero or minimal current when in an open or OFF state.

The switch comprises a channel path and control circuitry. The channel path comprises a first terminal and a second terminal. The switch may be used in a HV multiplexer of a BMS with the first terminal of the channel path connected to a battery cell and the second terminal of the channel path connected to the shared bus. The control circuitry controls the operation of the switch between an ON state and an OFF state.

The channel path comprises a first MOS transistor (metal-oxide-semiconductor transistor, metal-oxide-silicon transistor or equivalently metal-oxide-semiconductor field-effect transistor, MOSFET) and a second MOS transistor (also known as channel switches) arranged in a back to back configuration with a common gate terminal and a common source terminal. In other words, the gate terminals of the first and second MOS transistors are connected together at a common (same) voltage and the source terminals of the first and second MOS transistors are connected together at another common voltage. The back to back configuration can avoid a drain to body diode of a MOS transistor conducting in one direction when the switch is commanded off, when a gate-source voltage is less than a threshold voltage (Vgs < Vth). Conduction channels of the first MOS transistor and the second MOS transistor form the channel path. Drain terminals of the first and second MOS transistors can form the first and second terminals of the channel path.

The control circuitry comprises a third MOS transistor, a drive resistor, a first current source, a second current source and a switching arrangement. The control circuitry can control the operation of the switch between an ON state and an OFF state while preventing or minimising control current injection into the channel path and current consumption during the OFF state.

The third MOS transistor comprises: a gate terminal coupled to the common source terminal of the first and second MOS transistors; a source terminal coupled to a first end of the drive resistor, with a second end of the drive resistor coupled to the common gate terminal of the first and second MOS transistors; and a drain terminal coupled to a first reference voltage terminal. As discussed below, the first reference voltage terminal may be a supply terminal or a reference (or ground) terminal depending upon whether the switch is implemented with PMOS or NMOS transistors. A Zener diode couples together the gate terminal and the source terminal of the third MOS transistor and can provide over-voltage gate protection for the third MOS transistor.

The first current source is coupled between the first reference voltage terminal and the common gate terminal and can provide a first current. The second current source is coupled between the source terminal of the third MOS transistor and a second reference voltage terminal and can provide a second current. The second current should be greater than the first current to provide correct biasing of the third MOS transistor. As discussed below, the second reference voltage terminal may be a supply terminal or a reference terminal depending upon whether the switch is implemented with PMOS or NMOS transistors. As a result, a direction of flow of the first and second current source may depend upon whether the switch is implemented with NMOS or PMOS transistors.

The switching arrangement can selectively enable and disable the first current source and the second current source depending on a ON/OFF state of the switch.

<FIG> illustrates a switch <NUM> according to an embodiment of the present disclosure. In this example, the first, second and third MOS transistors are respectively implemented as a first NMOS (n-type MOS) transistor, M1, <NUM>, a second NMOS transistor, M2, <NUM> and a third NMOS transistor, M3, <NUM>.

The first NMOS transistor <NUM> and the second NMOS transistor <NUM> form the channel path having a common source terminal <NUM> and a common gate terminal <NUM>. Drain terminals of the first and second NMOS transistors <NUM>, <NUM> may form the respective first and second terminals of the channel path.

The control circuitry comprises the third NMOS transistor <NUM> and the drive resistor, R, <NUM>. The drain terminal of the third NMOS transistor <NUM> is coupled to the first reference voltage terminal <NUM>, which in this example is a supply voltage terminal. The gate terminal of the third NMOS transistor <NUM> is coupled to the common source terminal <NUM>. The drive resistor <NUM> couples the source terminal of the third NMOS transistor <NUM> to the common gate terminal <NUM>. The source terminal of the third NMOS transistor <NUM> is coupled to the second reference voltage terminal <NUM> (ground in this example) by the second current source <NUM>. In this way, the third NMOS transistor <NUM> can act as a source follower biased by the second current source <NUM>, with a voltage, VsM1,M2, at the common source terminal <NUM> as an input signal and a voltage, VsM3, at the source terminal of the third NMOS transistor <NUM> as an output signal.

A Zener diode <NUM> is coupled between the gate terminal and the source terminal of the third NMOS transistor <NUM>. An anode of the Zener diode <NUM> is coupled to the source terminal of the third NMOS transistor <NUM>, and a cathode of the Zener diode <NUM> is coupled to the gate terminal of the third NMOS transistor <NUM>. The Zener diode <NUM> can provide over-voltage gate protection for the third NMOS transistor <NUM>. In this way a maximum value of the gate-source voltage, VgsM3, of the third NMOS transistor <NUM> will be limited to a breakdown voltage of the Zener diode <NUM>. The Zener diode breakdown voltage should be higher than an operational value of the gate-source voltage, VgsM3, of the third NMOS transistor <NUM> and lower than a maximum rating of the gate-source voltage, VgsM3, of the third NMOS transistor <NUM>.

In this example, the first current source <NUM> is provided by a conduction channel of an output PMOS (p-type MOS) transistor <NUM>. The output PMOS transistor <NUM> forms part of a PMOS current mirror. The PMOS current mirror further comprises an input PMOS transistor <NUM>. Source terminals of the input PMOS transistor <NUM> and the output PMOS transistor <NUM> are coupled to the supply voltage terminal. A drain of the output PMOS transistor <NUM> is coupled to the common gate terminal <NUM>. Gate terminals of the input PMOS transistor <NUM> and the output PMOS transistor <NUM> are coupled together and to a drain terminal of the input PMOS transistor <NUM>. The PMOS current mirror further comprises a primary current source <NUM> selectively coupled (by the switching arrangement) in series between the drain terminal of the input PMOS transistor <NUM> and the ground terminal.

In this example the switching arrangement comprises a first switching arrangement <NUM> and a second switching arrangement <NUM>. The first switching arrangement <NUM> can selectively enable and disable the first current source <NUM>. The second switching arrangement <NUM> can selectively enable and disable the second current source <NUM>.

In this example, the first switching arrangement <NUM> comprises a fifth NMOS transistor, M5, <NUM> with a conduction channel coupled in series with the primary current source <NUM>. A gate terminal of the fifth NMOS transistor <NUM> can receive state signalling, EN, indicative of whether the switch is in an ON state or an OFF state. The state signalling may comprise a two-level signal with a first level representing an ON state and a second level representing an OFF state. In this way, the PMOS current mirror can selectively mirror a current, Ibias_hs, of the primary current source <NUM> from the input PMOS transistor <NUM> to the output PMOS transistor <NUM> to provide the first current, Ibias_hs, depending on the state signalling. In this example, the first switching arrangement <NUM> can selectively: (i) enable the first current source <NUM> to produce the first current, Ibias_hs, (by enabling the primary current source <NUM>) when the state signalling is a high level, or a logic <NUM>, indicative of an ON state of the switch <NUM>; and (ii) disable the first current source <NUM> from producing the first current, Ibias_hs, when the state signalling is a low level, or a logic <NUM>, indicative of an OFF state of the switch <NUM>.

In other examples, the first current source <NUM> may be provided by alternative means to the PMOS mirror.

The second switching arrangement <NUM> comprises a fourth NMOS transistor, M4, <NUM> with a conduction channel coupled in series with the second current source <NUM> between the source terminal of the third NMOS transistor <NUM> and the second reference voltage terminal <NUM>. A gate terminal of the fourth NMOS transistor <NUM> can receive the state signalling. In this way, the second switching arrangement <NUM> can selectively: (i) enable the second current source <NUM> when the state signalling, EN, is a high level, or a logic <NUM>, indicative of an ON state of the switch <NUM>; and (ii) disable the second current source <NUM> when the state signalling, EN, is a low level, or logic <NUM>, indicative of an OFF state of the switch <NUM>.

When the switch <NUM> is closed or set to an ON state, the state signalling EN is a logic <NUM>. On receipt of the state signalling, EN=<NUM>, the fifth NMOS transistor <NUM> couples the primary current source <NUM> to the drain of the input PMOS transistor <NUM>. The PMOS current mirror mirrors the current, Ibias_hs, of the primary current source <NUM> from the input PMOS transistor <NUM> to the output PMOS transistor <NUM> to provide the first current, Ibias_hs. In this way, the first switching arrangement <NUM> is configured to selectively enable the first current source <NUM>. In this example, the PMOS mirror does not scale the current of the primary current source <NUM>, but in other examples the first current, Ibias_hs, may differ from the current of the primary current source <NUM>.

On receipt of the state signalling, EN=<NUM>, the fourth NMOS transistor <NUM> of the second switching arrangement <NUM> couples the second current source <NUM> between the source terminal of the third NMOS transistor <NUM> and the second reference voltage terminal <NUM>. In this way, the second switching arrangement <NUM> is configured to selectively enable the second current source <NUM>.

The first current, Ibias_hs, is injected into the drive resistor <NUM> providing a voltage across the drive resistor <NUM>. This voltage provides a gate-source voltage, VgsM1,M2, for the first and second NMOS transistors <NUM>, <NUM> that is greater than their threshold voltage, Vth, and the channel path of the switch <NUM> becomes conductive. In other words, the first and second NMOS transistors <NUM>, <NUM> are switched ON and their conduction channels forming the channel path become conductive. The gate-source voltage, VgsM1,M2, controls the first and second NMOS transistors <NUM>, <NUM> based on a resistance, R, of the drive resistor <NUM>, the first current, Ibias_hs, and a gate-source voltage, VgsM3, of the third NMOS transistor <NUM>, according to the equation: <MAT>.

The second current source <NUM> provides a second current, Ibias_ls, for sinking the first current, Ibias_hs, and biasing the third NMOS transistor <NUM>. The second current source <NUM> provides a second current, Ibias_ls, greater than the first current, Ibias_hs. As a result, during the ON state, a current (Ibias_ls - Ibias_hs) will flow from the supply voltage terminal through the third NMOS transistor <NUM> towards the second current source <NUM>. In this way, the third NMOS transistor <NUM> can isolate the first and second current from the channel path of the switch <NUM>. The first and second current may be considered as the control current of the control circuitry. Therefore, the control circuitry can isolate the control current from the channel path of the switch <NUM>.

When the switch <NUM> is opened or set to an OFF state, the state signalling EN is a logic <NUM>. On receipt of the state signalling, EN=<NUM>, the fifth NMOS transistor decouples the primary current source <NUM> from the drain of the input PMOS transistor <NUM>. As a result, there is no current for the PMOS mirror to mirror to the output PMOS transistor <NUM>. In this way, the first switching arrangement <NUM> is configured to selectively disable the first current source <NUM>.

On receipt of the state signalling, EN=<NUM>, the fourth NMOS transistor <NUM> of the second switching arrangement <NUM> decouples the second current source <NUM> from the source terminal of the third NMOS transistor <NUM>. In this way, the second switching arrangement <NUM> is configured to selectively disable the second current source <NUM>.

As the first current source <NUM> and the second current source <NUM> are disabled, neither the first current, Ibias_hs, nor the second current, Ibias_ls, flow in the OFF state. In other words, the control circuitry does not consume current during the OFF state of the switch <NUM>.

As a result of disabling the first and second current sources <NUM>, <NUM> a voltage VSM1,M2, at the common source terminal <NUM>, a voltage, VsM3, at the source terminal of the third NMOS transistor <NUM> and a voltage, VgM1,M2, at the common gate terminal <NUM> can float. As no current flows in the drive resistor <NUM>, the voltage, VgM1,M2, at the common gate terminal <NUM> is equal to the voltage, VsM3, at the source terminal of the third NMOS transistor <NUM>. A voltage difference between the voltage, VsM3, at the source terminal of the third NMOS transistor <NUM> and the voltage, VsM1,M2, at the common source terminal <NUM> will be clamped to a forward voltage of the Zener diode <NUM>, which is typically on the order of <NUM> V. Therefore the gate-source voltage, VgsM1,M2, of the first and second NMOS transistors <NUM>, <NUM> will be no greater than the forward voltage of the Zener diode <NUM>.

In high-voltage CMOS technology (for example from 10V to 100V), such as that used in BMS, a threshold voltage, Vth, of a high voltage MOS switch can be approximately <NUM> V, higher than the forward voltage of the Zener diode <NUM> of approximately <NUM> V. The forward voltage of the Zener is equivalent to a classical forward diode voltage (650mV at room temperature with a -2mV/°C temperature coefficient). A high-voltage MOS transistor (such as the first or second NMOS transistors <NUM>, <NUM>) has a threshold, Vth, about twice the forward voltage of the Zener diode <NUM> (and with a similar temperature coefficient). Therefore, during the OFF state, when the first and second current sources <NUM>, <NUM> are disabled and no current flows in the drive resistor <NUM>, the gate-source voltage, VgsM1,M2, of the first and second NMOS transistors <NUM>, <NUM> is clamped to the forward voltage of the Zener diode (∼<NUM>. 65V) which is less than the threshold voltage, Vth, of the first and second NMOS transistors <NUM>, <NUM>. As a result, the first and second NMOS transistors <NUM>, <NUM> are switched off (cut-off). Therefore, in one or more examples, a threshold voltage of the first and second NMOS transistors <NUM>, <NUM> is greater than a forward voltage of the Zener diode <NUM>. This can ensure that the first and second NMOS transistors <NUM>, <NUM> are switched OFF when the switching arrangement disables the first and second current source <NUM>, <NUM>.

<FIG> illustrates a switch <NUM> according to another embodiment of the present disclosure. In this example, the first, second and third MOS transistors are respectively implemented as a first PMOS transistor, M1, <NUM>, a second PMOS transistor, M2, <NUM> and a third PMOS transistor, M3, <NUM>. It will be appreciated that the switch <NUM> of <FIG> provides essentially the same functionality as the switch of <FIG> but implemented with PMOS transistors. Certain terminology such as the first and second reference voltage terminals, first and second currents and first and second switching arrangements of the switch <NUM> of <FIG> may correspond to opposite ones to the switch of <FIG>.

The first PMOS transistor <NUM> and the second PMOS transistor <NUM> form the channel path having a common source terminal <NUM> and a common gate terminal <NUM>. Drain terminals of the first and second PMOS transistors <NUM>, <NUM> form the respective first and second terminals of the channel path.

The control circuitry comprises the third PMOS transistor <NUM> and drive resistor, R, <NUM>. The drain terminal of the third PMOS transistor <NUM> is coupled to the first reference voltage terminal <NUM>, which in this example is a ground terminal. The gate terminal of the third PMOS transistor <NUM> is coupled to the common source terminal <NUM>. The drive resistor <NUM> couples the source terminal of the third PMOS transistor <NUM> to the common gate terminal <NUM>. The source terminal of the third PMOS transistor <NUM> is coupled to a second reference voltage terminal <NUM> (a supply voltage terminal in this example) by the second current source <NUM>. In this way, the third PMOS transistor <NUM> can act as a source follower biased by the second current source <NUM>, with a voltage, VsM1,M2, at the common source terminal <NUM> as an input signal and a voltage, VsM3, at the source terminal of the third PMOS transistor <NUM> as an output signal.

A Zener diode <NUM> is coupled between the gate terminal and the source terminal of the third PMOS transistor <NUM>. A cathode of the Zener diode <NUM> is coupled to the source terminal of the third PMOS transistor <NUM>, and an anode of the Zener diode <NUM> is coupled to the gate terminal of the third PMOS transistor <NUM>. The Zener diode <NUM> can provide over-voltage gate protection for the third PMOS transistor <NUM>. In this way a maximum value of the gate-source voltage, VgsM3, of the third PMOS transistor <NUM> will be limited to a breakdown voltage of the Zener diode <NUM>. The Zener diode breakdown voltage should be higher than an operational value of the gate-source voltage, VgsM3, of the third PMOS transistor <NUM> and lower than a maximum rating of the gate-source voltage, VgsM3, of the third PMOS transistor <NUM>.

In this example, the second current source <NUM> is provided by a conduction channel of an output PMOS transistor <NUM>. The output PMOS transistor <NUM> forms part of a PMOS current mirror. The PMOS current mirror further comprises an input PMOS transistor <NUM>. Source terminals of the input PMOS transistor <NUM> and the output PMOS transistor <NUM> are coupled to the supply voltage terminal. A drain of the output PMOS transistor <NUM> is coupled to the source terminal of the third PMOS transistor <NUM>. Gate terminals of the input PMOS transistor <NUM> and the output PMOS transistor <NUM> are coupled together and to a drain terminal of the input PMOS transistor <NUM>. The PMOS current mirror further comprises a primary current source <NUM> selectively coupled (by the switching arrangement) in series between the drain terminal of the input PMOS transistor <NUM> and the ground terminal.

In this example, the second switching arrangement <NUM> comprises a fifth NMOS transistor, M5, <NUM> with a conduction channel coupled in series with the primary current source <NUM>. A gate terminal of the fifth NMOS transistor <NUM> can receive state signalling, EN, indicative of whether the switch is in an ON state or an OFF state. The state signalling may comprise a two-level signal with a first level representing an ON state and a second level representing an OFF state. In this way, the PMOS current mirror can selectively mirror a current, Ibias_hs, of the primary current source <NUM> from the input PMOS transistor <NUM> to the output PMOS transistor <NUM> to provide the second current, Ibias_hs, depending on the state signalling. In this example, the second switching arrangement <NUM> can selectively: (i) enable the second current source <NUM> to produce the second current, Ibias_hs, (by enabling the primary current source <NUM>) when the state signalling is a high level, or a logic <NUM>, indicative of an ON state of the switch; and (ii) disable the second current source <NUM> from producing the second current, Ibias_hs, when the state signalling is a low level, or a logic <NUM>, indicative of an OFF state of the switch.

In other examples, the second current source <NUM> may be provided by alternative means to the PMOS mirror.

The first switching arrangement <NUM> comprises a fourth NMOS transistor, M6, <NUM> having a gate terminal configured to receive the state signalling, EN. A conduction channel of the fourth NMOS transistor <NUM> and the first current source <NUM> are coupled in series between the first reference voltage terminal <NUM> (the ground terminal) and the common gate terminal <NUM>. In this way, the first switching arrangement can selectively: (i) enable the first current source <NUM> to produce the first current, Ibias_ls, when the state signalling is a high level, or a logic <NUM>, indicative of an ON state of the switch <NUM>; and (ii) disable the first current source <NUM> from producing the first current, Ibias_ls, when the state signalling is a low level, or a logic <NUM>, indicative of an OFF state of the switch <NUM>.

When the switch <NUM> is closed or set to an ON state, the state signalling EN is a logic <NUM>. On receipt of the state signalling, EN=<NUM>, the fifth NMOS transistor <NUM> couples the primary current source <NUM> to the drain of the input PMOS transistor <NUM>. The PMOS current mirror mirrors the current, Ibias_hs, of the primary current source <NUM> from the input PMOS transistor <NUM> to the output PMOS transistor <NUM> to provide the second current, Ibias_hs. In this way, the second switching arrangement <NUM> is configured to selectively enable the second current source <NUM>.

On receipt of the state signalling, EN=<NUM>, the fourth NMOS transistor <NUM> of the first switching arrangement <NUM> couples the first current source <NUM> to the common gate terminal <NUM>. In this way, the first switching arrangement selectively enables the first current source <NUM>.

The second current, Ibias_hs, is injected into the drive resistor <NUM> providing a voltage across drive resistor <NUM>. This voltage provides a gate-source voltage, VgsM1,M2, for the first and second PMOS transistors <NUM>, <NUM> that is of greater magnitude (more negative) than their threshold voltage, Vth, and the channel path of the switch <NUM> becomes conductive. In other words, the first and second PMOS transistors <NUM>, <NUM> are switched ON and their conduction channels forming the channel path become conductive. The gate-source voltage, VgsM1,M2, controls the first and second PMOS transistors <NUM>, <NUM> based on a resistance, R, of the drive resistor <NUM>, the first current, Ibias_hs, and a gate-source voltage, VgsM3, of the third PMOS transistor <NUM>, according to the equation: <MAT>.

The second current source <NUM> provides a second current, Ibias_hs, for biasing the third PMOS transistor <NUM>. The second current source <NUM> provides a second current, Ibias_hs, greater than the first current, Ibias_ls. As a result, during the ON state, a current (Ibias_hs - Ibias_ls) will flow from the second current source <NUM>, through the third PMOS transistor <NUM> to the ground terminal. In this way, the third PMOS transistor <NUM> can isolate the first and second current from the channel path of the switch <NUM>. The first and second current may be considered as the control current of the control circuitry. Therefore, the control circuitry can isolate the control current from the channel path of the switch <NUM>.

When the switch <NUM> is opened or set to an OFF state, the state signalling, EN, is a logic <NUM>. On receipt of the state signalling, EN=<NUM>, the fifth NMOS transistor <NUM> decouples the primary current source <NUM> from the drain terminal of the input PMOS transistor <NUM>. As a result, there is no current for the PMOS mirror to mirror to the output PMOS transistor <NUM>. In this way, the second switching arrangement <NUM> is configured to selectively disable the second current source <NUM>.

On receipt of the state signalling, EN=<NUM>, the fourth NMOS transistor <NUM> of the first switching arrangement <NUM> decouples the first current source <NUM> from the common gate terminal <NUM>. In this way, the first switching arrangement <NUM> selective disables the first current source <NUM>.

As the first current source <NUM> and the second current source <NUM> are disabled, neither the first current, Ibias_ls, nor the second current, Ibias_hs, flow in the OFF state. In other words, the control circuitry does not consume current during the OFF state of the switch <NUM>.

As a result of disabling the first and second current sources <NUM>, <NUM> a voltage VsM1,M2, at the common source terminal <NUM>, a voltage, VsM3, at the source terminal of the third PMOS transistor <NUM> and a voltage, VgM1,M2, at the common gate terminal <NUM> can float. As no current flows in the drive resistor <NUM>, the voltage, VgM1,M2, at the common gate terminal <NUM> is equal to the voltage, VsM3, at the source terminal of the third PMOS transistor <NUM>. A voltage difference between the voltage, VsM3, at the source terminal of the third PMOS transistor <NUM> will be clamped to a forward voltage of the Zener diode <NUM>, which is typically on the order of <NUM> V. Therefore the gate-source voltage, VgsM1,M2, of the first and second PMOS transistors <NUM>, <NUM> will be no greater than the forward voltage of the Zener diode <NUM>.

In high-voltage CMOS technology (e. g 100V), such as that used in BMS, a threshold voltage, Vth, of a high voltage MOS switch can be approximately <NUM> V, higher than the forward voltage of the Zener diode <NUM> of approximately <NUM> V. Therefore, during the OFF state, when the first and second current sources <NUM>, <NUM> are disabled and no current flows in the drive resistor <NUM>, the gate-source voltage, VgsM1,M2, of the first and second NMOS transistors <NUM>, <NUM> is clamped to the forward voltage of the Zener diode (~<NUM>. 65V) which is less than the threshold voltage, Vth, of the first and second NMOS transistors <NUM>, <NUM>. As a result, the first and second NMOS transistors <NUM>, <NUM> are switched off (cut-off). Therefore, in one or more examples, a threshold voltage of the first and second PMOS transistors <NUM>, <NUM> is greater than a forward voltage of the Zener diode <NUM>. This can ensure that the first and second PMOS transistors <NUM>, <NUM> are switched OFF when the switching arrangement disables the first and second current source <NUM>, <NUM>.

The disclosed switches (such as those of <FIG> and <FIG>) provide several advantages including:.

The disclosed switches can find particularly advantageous application in HV multiplexers of BMS ICs providing a battery cell voltage and temperature measurement chain with high accuracy.

The disclosed switches can provide a very high voltage zero-leakage current-control analog switch with zero control current required to keep switch open.

It will be appreciated that the switching arrangements described above in relation to <FIG> and <FIG> are merely examples of switching arrangements that can selectively enable and disable the first and second current sources. A person skilled in the art will be aware of alternate means for enabling and disabling the current sources and these fall within the scope of the disclosed switching arrangement. For example, the current sources can be disabled by shorting the current source and / or a respective transistor.

Claim 1:
A switch (<NUM>, <NUM>) comprising:
a channel path comprising a first MOS transistor (<NUM>, <NUM>) and a second MOS transistor (<NUM>, <NUM>) arranged in a back to back configuration with a common source terminal (<NUM>, <NUM>) and a common gate terminal (<NUM>, <NUM>), wherein a drain terminal of the first MOS transistor defines a first terminal of the channel path and a drain terminal of the second MOS transistor defines a second terminal of the channel path; and
control circuitry comprising:
a third MOS transistor (<NUM>, <NUM>) comprising:
a gate terminal coupled to the common source terminal (<NUM>, <NUM>);
a source terminal coupled to the common gate terminal (<NUM>, <NUM>) by a resistor (<NUM>, <NUM>); and
a drain terminal coupled to a first reference voltage terminal (<NUM>, <NUM>);
a Zener diode (<NUM>, <NUM>) coupled between the gate terminal of the third MOS transistor (<NUM>, <NUM>) and the source terminal of the third MOS transistor and arranged to provide over-voltage gate protection for the third MOS transistor, wherein a threshold voltage of the first MOS transistor (<NUM>, <NUM>) and a threshold voltage of the second MOS transistor (<NUM>, <NUM>) are both greater than a forward voltage of the Zener diode (<NUM>,<NUM>);
a first current source (<NUM>, <NUM>) coupled between the first reference voltage terminal (<NUM>, <NUM>) and the common gate terminal (<NUM>, <NUM>) and configured to provide a first current;
a second current source (<NUM>, <NUM>) coupled between the source terminal of the third MOS transistor (<NUM>, <NUM>) and a second reference voltage terminal (<NUM>, <NUM>), and configured to provide a second current greater than the first current; and
a switching arrangement (<NUM>, <NUM>, <NUM>, <NUM>) configured to selectively enable and disable the first current source (<NUM>, <NUM>) and the second current source (<NUM>, <NUM>).