Patent Description:
Receivers, such as wireline or wireless signal receivers, are devices that may receive electromagnetic signals. The electromagnetic signals may include high-frequency and low-frequency signal components. Some wireline signal receivers may use frequency synthesizers to generate a waveform at a frequency determined by analog or digital circuits. For instance, a frequency synthesizer may be an electronic device that uses an oscillator to generate a signal with a specific frequency or within a pre-set frequency range. Operation of some such frequency synthesizers may be adversely affected by component and/or system noise. <NPL>ntroduces a special phase locked loop (PLL) but is silent regarding a multi-modulus divider (MMD) circuit that includes a divisor circuit as well as a pulse swallow divider circuit with a controllable delay. <CIT> introduces a frequency multiplier for PLL, but is also silent regarding the proposed MMD circuit that includes a divisor circuit as well as a pulse swallow divider circuit with a controllable delay.

According to an aspect of the present invention, an apparatus is provided as set out in claim <NUM>.

The foregoing summary is not intended to be limiting. Moreover, various aspects of the present disclosure may be implemented alone or in combination with other aspects.

In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like reference character. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating various aspects of the techniques and devices described herein.

Phase-locked loop (PLL) circuits are used in a wide variety of high frequency applications. Non-limiting examples of high frequency applications include clock clean-up circuits, local oscillators (LOs) for high performance communication links, and ultrafast switching frequency synthesizers. Non-limiting examples of high-performance communication links include wireline communication links, such as Ethernet links, and wireless communication links, such as radiofrequency (RF), radar, and satellite communication links. Some PLL circuits include an oscillator (e.g., a digitally controlled oscillator (DCO), a voltage-controlled oscillator (VCO), a voltage-driven oscillator (VDO)) that adjusts (e.g., constantly adjusts) to match the frequency of an input signal. For example, some such PLL circuits may be used to generate, stabilize, modulate, demodulate, filter, or recover a signal from a communications channel from which the reception of data may be affected by noise associated with the communications channel.

One challenge of using a PLL circuit with an oscillator, such as a DCO, is that the oscillator is typically the most power consuming block of the PLL circuit. For example, a DCO may be an oscillator circuit that generates an analog signal, but whose frequency is controlled by a digital control input generated by a digital-to-analog converter. A VCO may be an oscillator circuit that generates an analog signal and whose frequency is controlled by an analog control input, such as a control voltage. In these examples, a DCO may consume more power than the VCO and/or, more generally, more power than other component(s) of the PLL circuit.

Another challenge of using a PLL circuit with an oscillator, such as a DCO, is that the oscillator may introduce substantial noise into the PLL circuit, and/or, more generally, into a system that includes the PLL circuit. A conventional technique for reducing noise associated with the DCO is increasing the PLL bandwidth. However, a challenge of using such a conventional technique is that the PLL bandwidth is limited by the reference clock frequency (FREF) (e.g., the frequency of the input signal to the PLL circuit). For example, the noise bandwidth (NBW) may be approximated by FREF/<NUM> and the NBW is limited by FREF.

A conventional technique for increasing the reference clock frequency, and thereby increasing the PLL bandwidth, is using a frequency doubler. One challenge of using a frequency doubler is that the frequency doubler may introduce duty cycle distortion. For example, the frequency doubler may introduce deterministic jitter into the PLL circuit, which can cause the rising edges of the reference clock signal to be respectively delayed (or advanced) by a first delay value from the expected moment in time and cause the falling edges of the reference clock signal to be respectively delayed (or advanced) by a second delay value from the expected moment in time. For example, a change in the duty cycle of a clock generator that generates the reference clock signal may be +/-<NUM>%. For a <NUM>-megahertz (MHz) clock generator, the deterministic jitter introduced by the frequency doubler may be +/-<NUM> picoseconds (ps), which is substantially large enough such that the use of the frequency doubler may cause erroneous operation of the PLL circuit. In some systems, the duty cycle distortion may be converted to a spur at FREF, which can shift a sampling instant of FREF and thereby degrade the sampling of FREF and cause erroneous operation of the PLL circuit.

The inventors have recognized that the aforementioned challenges have not been overcome by using conventional techniques, such as increasing the PLL bandwidth and/or using a frequency doubler. To overcome the deficiencies of the conventional techniques, the inventors have developed technology for digital phase-locked loops and a related merged duty cycle calibration scheme for frequency synthesizers.

Example digital PLLs disclosed herein include a VCO to generate an output clock frequency. The use of a VCO can overcome the challenges of using a DCO by consuming less power than the DCO. Example digital PLLs disclosed herein include a multi-modulus divider (MMD), and a digitally controlled delay line (DCDL) as an infinite range (e.g., a substantially large range) digital-to-time converter (DTC). For example, the DTC can receive an output clock signal from the VCO, delay the output clock signal by a time delay to generate a feedback clock signal, and provide the feedback clock signal to a phase detector of the PLL circuit for comparison. In some embodiments, control of the DCDL can achieve a first time delay in a range of <NUM> to one time period of the VCO (TVCO). In some embodiments, control of the MMD can achieve a second time delay in a range of <NUM> to TVCO. For example, the DTC can generate the feedback clock signal by delaying the output clock frequency by a total time delay based on a combination of the first time delay and the second time delay (e.g., a total time delay up to 2TVCO (e.g., <NUM>*TVCO)). For example, the MMD can extend a first time delay range achievable by the DCDL to a second time delay range. In some embodiments, control of at least one of the DCDL or the MMD can generate a time delay in a time delay range up to at least the second time delay range.

In some embodiments, the time delay needed to lock the reference clock signal to the feedback clock signal is greater than 2TVCO. Beneficially, the DTC can operate as an infinite range DTC by increasing the time delay range through resetting control of the DCDL (e.g., resetting a digital code output by the DCDL to <NUM>) and changing a configuration of the MMD to further divide the feedback clock signal. For example, the DTC can achieve time delays in time delay ranges up to at least 3TVCO, 4TVCO, 5TVCO, etc., by changing configurations of the DCDL and/or the MMD to increase (e.g., iteratively increase) the total achievable delay.

In some embodiments, digital PLLs disclosed herein can include a retimer to achieve additional time delay and thereby extend a time delay range that the DCDL and the MMD can provide. For example, a digital PLL disclosed herein can include an MMD, a retimer, and a DCDL configurable to achieve a total time delay of at least 3TVCO. Configuration changes of at least one of the MMD or the DCDL can be implemented to achieve additional time delay, such as time delays in time delay ranges up to at least 4TVCO, 5TVCO, 6TVCO, etc..

Beneficially, example PLL circuits disclosed herein overcome the challenges of conventional techniques. For example, the use of a VCO can reduce the power consumption of the PLL circuit with respect to a PLL circuit using a DCO. In some embodiments, the reference clock frequency can be increased to increase the PLL bandwidth, and the corresponding noise can be mitigated by the example MMD, retimer, and/or DCDL disclosed herein. For example, configurations of at least one of the MMD, the retimer, or the DCDL can increase the time delay applied to the feedback clock signal such that the error associated with the reference clock signal is corrected and/or otherwise reduced. Beneficially, by applying time delays in substantially large time delay ranges, the example PLL circuits can eliminate and/or otherwise reduce the duty cycle distortion introduced by frequency increasers, such as frequency doublers.

Turning to the figures, the illustrated example of <FIG> depicts an example phase-locked loop (PLL) <NUM>. The PLL <NUM> is a circuit that generates an output clock signal <NUM> (identified by CLKOUT) whose phase is related to a phase of a reference clock signal <NUM> (identified by REFCLK). For example, the PLL <NUM> can synchronize and/or lock a phase of the output clock signal <NUM> with a phase of the reference clock signal <NUM>. In some embodiments, the PLL <NUM>, or portion(s) thereof, can implement a frequency synthesizer that produces a range of frequencies from a single fixed oscillator.

In the illustrated example, the reference clock signal <NUM> is an input signal that can be transmitted by a transmitter and/or received by a receiver. For example, the PLL <NUM> can be configured to receive the reference clock signal <NUM> from a wireline receiver, such as a data communication wireline receiver. Non-limiting examples of wireline receivers include Ethernet interfaces, Peripheral Component Interconnect (PCI) interfaces, Serial Digital Interfaces (SDI), Universal Serial Bus (USB) interfaces, and High-Definition Multimedia Interfaces (HDMI). Alternatively, the PLL <NUM> can be configured to receive the reference clock signal <NUM> from a wireless receiver. Non-limiting examples of wireless receivers include Wireless Fidelity (Wi-Fi) receivers, Bluetooth receivers, near-field communication (NFC) receivers, radio-frequency identification (RFID) receivers, and satellite receivers (e.g., beyond-line-of-site (BLOS) satellite receivers, line-of-site (LOS) satellite receivers, etc.).

In some embodiments, the PLL <NUM> is included in and/or associated with an electronic device. Non-limiting examples of electronic devices include gateways, routers, switches, laptop computers, tablet computers, cellular phones (e.g., smartphones), televisions (e.g., smart televisions), set-top boxes, streaming devices, and wearable devices (e.g., headphones, headsets, smartwatches, smart glasses, etc.). For example, the output clock signal <NUM> can be provided to additional circuitry, such as a transmitter, a receiver, and/or a programmable processor. Non-limiting examples of programmable processors include central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs).

The PLL <NUM> of the illustrated example includes a frequency doubler <NUM> (identified by DUB) to double and/or otherwise increase a frequency (e.g., a reference clock frequency, an input clock frequency) of the reference clock signal <NUM> to generate a doubled reference clock signal <NUM> (identified by REFCLKDBL). In some embodiments, the frequency doubler <NUM> is a frequency doubler circuit that increases the frequency of the reference clock signal <NUM> to increase a bandwidth of the PLL <NUM>. In some embodiments, the frequency doubler <NUM> is implemented by an oscillator (e.g., a reference oscillator, an oscillator circuit) to increase the frequency of the reference clock signal <NUM>. In some embodiments, the frequency doubler <NUM> can be configured to receive the reference clock signal <NUM> from a receiver (e.g., a wireline receiver, a wireless receiver). Alternatively, the PLL <NUM> may utilize a different frequency increaser than the frequency doubler <NUM> to triple, quadruple, etc., the reference clock signal <NUM>.

The PLL <NUM> of the illustrated example includes a phase detector <NUM> (identified by PD and may also be referred to as a phase comparator or mixer) to compare a first phase of the doubled reference clock signal <NUM> and a second phase of a feedback clock signal <NUM> (identified by FBCLK). The feedback clock signal <NUM> can be a delayed instance of the output clock signal <NUM>. In some embodiments, the PD <NUM> can be a phase detector circuit that can generate and/or output a voltage according to a phase difference of the first and second phases. In some embodiments, the voltage can be an error signal that is representative of an error that is detected between the phases of the doubled reference clock signal <NUM> and the feedback clock signal <NUM>. The PD <NUM> of the illustrated example has a first input (e.g., a first detector input, a first phase detector input) coupled to an output (e.g., a doubler output, a frequency doubler output) of the frequency doubler <NUM>. For example, the PD <NUM> and the frequency doubler <NUM> can be coupled together through one or more electrical connections. Non-limiting examples of electrical connections include opto-isolators, pads, traces, wires, and vias.

The PLL <NUM> of this example includes a loop filter <NUM> (identified by LF). In some embodiments, the LF <NUM> is a loop filter circuit that converts the output of the PD <NUM> into a control signal (e.g., a control voltage) for a voltage-controlled oscillator <NUM> (identified by VCO) of the PLL <NUM>. For example, the PD <NUM> can be implemented by one or more charge pumps that can output a current representative of the detected error. In some such embodiments, the LF <NUM> can convert the current from the one or more charge pumps to the control voltage for the VCO <NUM>. Alternatively, the PD <NUM> may output a voltage representative of the detected error. In some embodiments, the LF <NUM> can filter out and/or attenuate noise coming from the reference clock signal <NUM> to the control voltage. The LF <NUM> of the illustrated example has an input (e.g., a filter input, a loop filter output) coupled to an output (e.g., a detector output, a phase detector output) of the PD <NUM>.

The PLL <NUM> of this example includes the VCO <NUM> to generate and/or output the output clock signal <NUM> according to the control voltage output from the LF <NUM>. In some embodiments, the VCO <NUM> is a VCO circuit that generates and/or outputs the output clock signal <NUM>. In some embodiments, the output clock signal <NUM> is a signal (e.g., a sinusoidal signal) whose frequency closely matches the center frequency provided by the LF <NUM>. The VCO <NUM> of this example has an input (e.g., an oscillator input) coupled to an output (e.g., a filter output, a loop filter output) of the LF <NUM>.

In the illustrated example, the PLL <NUM> includes a multi-modulus divider <NUM> (identified by MMD) to divide and/or reduce a frequency of the output clock signal <NUM>. Additionally or alternatively, a pre-division ratio may be included in the PLL <NUM> prior to the MMD <NUM>. In some embodiments, the MMD <NUM> can be an MMD circuit that divides a frequency of the output clock signal <NUM> by a divisor (e.g., <NUM>, <NUM>, <NUM>, etc.) to generate a divided clock signal. For example, the MMD <NUM> can be implemented using one or more analog and/or digital circuits configured to divide the frequency of the output clock signal <NUM>. In some embodiments, the MMD <NUM> can delay the divided clock signal by a time delay (e.g., a time duration, a time period) in a time delay range to generate a delayed clock signal. For example, time delays in the time delay range can range from zero time delay to a time delay up to at least a period of the VCO <NUM> (e.g., TVCO). Any other time delay range may be utilized. The MMD <NUM> of this example has an input (e.g., a divider input, an MMD input) coupled to an output (e.g., an oscillator output) of the VCO <NUM>.

The PLL <NUM> of the illustrated example includes a digitally controlled delay line (DCDL) <NUM> to delay the output, such as a divided clock signal, from the MMD <NUM>, by a time delay in a time delay range to generate the feedback clock signal <NUM>. In some embodiments, the DCDL <NUM> can cause a reduction of a difference (e.g., a difference in phases) of the doubled reference clock signal <NUM> and the feedback clock signal <NUM>. For example, the difference can be representative of an error generated by duty cycle distortion associated with the doubled reference clock signal <NUM>. In some embodiments, the DCDL <NUM> is implemented by one or more analog and/or digital circuits. For example, the DCDL <NUM> can be implemented by one or more buffers (e.g., circular buffers) that implement one or more discrete digital logic elements. Alternatively, the DCDL <NUM> may be implemented by any other analog and/or digital components or elements.

The DCDL <NUM> of this example has an output (e.g., a delay line output, a digitally controlled delay line output) coupled to a second input (e.g., a second detector input, a second phase detector input) of the PD <NUM>. Alternatively, one or more portions of the DCDL <NUM> may be disposed elsewhere in the PLL <NUM>. For example, a first portion of the DCDL <NUM> can be in circuit with a reference path of the PLL <NUM>, which can be a path that includes at least one of the frequency doubler <NUM>, the PD <NUM>, the LF <NUM>, or the VCO <NUM>. In some embodiments, a second portion of the DCDL <NUM> can be in circuit with a feedback path of the PLL <NUM>, which can be a path that includes at least one of the VCO <NUM>, the MMD <NUM>, the DCDL <NUM>, or the PD <NUM>.

In some embodiments, the DCDL <NUM>, the MMD <NUM>, and/or, more generally, the PLL <NUM>, can be configured to cause generation of the feedback clock signal <NUM> to reduce the error. For example, the PLL <NUM> includes control circuitry <NUM> (identified by Frac-N Control + DCD Calibration), which can be implemented by one or more control circuits, to configure at least one of the MMD <NUM> or the DCDL <NUM> to reduce a difference between the doubled reference clock signal <NUM> and the feedback clock signal <NUM>. In some embodiments, the reduction of the difference can be implemented by shifting the feedback clock signal <NUM> to have the same error as the doubled reference clock signal <NUM>.

In some embodiments, the control circuitry <NUM> implements at least one of fractional-N (Frac-N) control logic or digitally controlled delay (DCD) calibration control logic. In some embodiments, the control circuitry <NUM> can be digital logic and/or implemented at least in part by digital logic to effectuate Frac-N control or DCD calibration. In some embodiments, the control circuitry <NUM> can receive control signal(s) <NUM> (identified by Frac-N Control), such as digital code(s) (e.g., digital code word(s)), to set an initial configuration of the control circuitry <NUM>.

In some embodiments, the control circuitry <NUM> is configured to receive the error signal from the PD <NUM>. For example, the control circuitry <NUM> can determine whether the error signal is greater than or less than a voltage threshold (e.g., <NUM> volts (V), <NUM> V, etc.) for each clock cycle of the PD <NUM>. In some embodiments, the control circuitry <NUM> can generate a first digital code based on the error signal and output the first digital code to the MMD <NUM> to change a configuration of the MMD <NUM>. The configuration of the MMD <NUM> can cause a change in a time delay that the MMD <NUM> applies to the output clock signal <NUM>. In some embodiments, the control circuitry <NUM> can generate a second digital code based on the error signal and output the second digital code to the DCDL <NUM> to change a configuration of the DCDL <NUM>. The configuration of the DCDL <NUM> can cause a change in a time delay that the DCDL <NUM> applies to the delayed clock signal from the MMD <NUM>.

In the illustrated example, the control circuitry <NUM> has an input (e.g., a control input) coupled to an output of the PD <NUM>. In this example, a first output (e.g., a first control output) of the control circuitry <NUM> is coupled to an input of the MMD <NUM>. In this example, a second output (e.g., a second control output) of the control circuitry <NUM> is coupled to an input of the DCDL <NUM>.

Beneficially, in some embodiments, Frac-N control and DCD calibration can be combined and/or merged to improve operation of a frequency synthesizer, such as at least part of the PLL <NUM>. For example, Frac-N control and DCD calibration can be combined and/or merged to improve locking of the phases of the doubled reference clock signal <NUM> and the feedback clock signal <NUM>.

While an example implementation of the PLL <NUM> is depicted in <FIG>, other implementations are contemplated. For example, one or more blocks, components, functions, etc., of the PLL <NUM> may be combined or divided in any other way. The PLL <NUM> of the illustrated example may be implemented by hardware alone, or by a combination of hardware, software, and/or firmware. For example, the PLL <NUM> may be implemented by one or more analog circuits (e.g., capacitors, comparators, diodes, inductors, operational amplifiers, resistors, transistors, etc.), one or more digital circuits (e.g., logic gates, etc.), one or more hardware-implemented state machines, one or more programmable processors, one or more application specific integrated circuits (ASICs), etc., and/or any combination(s) thereof. The PLL <NUM> of the illustrated example can be implemented by one or more integrated circuits (ICs) on the same die or two or more different dies.

<FIG> depicts a schematic illustration of example implementations of an MMD <NUM> and a DCDL <NUM>. In some embodiments, the MMD <NUM> of this example can correspond to and/or implement the MMD <NUM> of <FIG>. In some embodiments, the DCDL <NUM> of this example can correspond to and/or implement the DCDL <NUM> of <FIG>.

The MMD <NUM> of the illustrated example is configured to receive a clock signal <NUM> (identified by VCOCLK) from a VCO, such as the VCO <NUM> of <FIG>, via a first input/output (I/O) port <NUM>. In some embodiments, the clock signal <NUM> of this example can correspond to and/or implement the output clock signal <NUM> of <FIG>.

The MMD <NUM> of this example includes a divisor <NUM>. In some embodiments, the divisor <NUM> is a divisor circuit that divides a frequency of the clock signal <NUM> by a divisor (e.g., <NUM>, <NUM>, <NUM>, etc.). For example, the divisor <NUM> can divide the clock signal <NUM> by the divisor to generate a divided clock signal. An input (e.g., a divisor input) of the divisor <NUM> is coupled to the first I/O port <NUM>.

The MMD <NUM> of this example includes a pulse swallow divider <NUM>. In some embodiments, the pulse swallow divider <NUM> is a pulse swallow divider circuit that outputs a signal (e.g., a pulse) in response to detecting a count of pulses (e.g., a count of rising edges, a count of falling edges) of the divided clock signal from the divisor <NUM>. For example, the pulse swallow divider <NUM> can reduce the frequency of the divided clock signal by swallowing (e.g., not passing and/or outputting) a number of pulses of the divided clock signal and outputting a clock signal after the number of swallowed pulses meets or exceeds a count threshold and thereby satisfies the count threshold. In some embodiments, the outputted clock signal can represent a delayed clock signal, such as a delay or delayed version of the divided clock signal from the divisor <NUM>. In this example, an input (e.g., a pulse swallow divider input) of the pulse swallow divider <NUM> is coupled to an output (e.g., a divisor output) of the divisor <NUM>.

In some embodiments, the control circuitry <NUM> can output a digital code to the pulse swallow divider <NUM>, and/or, more generally, the MMD <NUM>, to configure the count threshold. For example, the control circuitry <NUM> can output the digital code as a divider digital code <NUM> (identified by DIVIDER[N:<NUM>]) to instruct the pulse swallow divider <NUM> to divide the divided clock signal by N+<NUM> or N based on the modulus and/or divider control from the control circuitry <NUM>. For example, the MMD <NUM> can be configured to receive the divider digital code <NUM> from the control circuitry <NUM> via a second I/O port <NUM>.

In the illustrated example, the divider digital code <NUM> is an N+<NUM> bit digital word. For example, the divider digital code <NUM> can be a <NUM>-bit digital word that can configure the pulse swallow divider <NUM> to divide the divided clock signal in a range from <NUM> to <NUM>. For example, the divider digital code <NUM> can be a digital code of a plurality of digital codes associated with a first range of time delays. For example, the divider digital code <NUM> can be a first digital code associated with a first time delay of TVCO, a second digital code associated with a second time delay of 2TVCO, etc. In some embodiments, the first range of time delays can be implemented by a range of <NUM> (or other value) up to at least (N+<NUM>)*TVCO.

In some embodiments, the pulse swallow divider <NUM> can delay the divided clock signal by a time delay in a time delay range based on the swallowing of the number of pulses. For example, the time delay can be implemented by the reduction in the frequency of the divided clock signal based on the number of pulses that the pulse swallow divider <NUM> is configured to swallow.

By way of example, the time delay range can be implemented by a configuration of the pulse swallow divider <NUM>, and/or, more generally, a configuration of the MMD <NUM>. For example, the control circuitry <NUM> of <FIG> can generate the divider digital code <NUM> to be <NUM> or <NUM> in binary (e.g., b'<NUM>) to configure the pulse swallow divider <NUM> to output a pulse in response to detecting <NUM> pulses of the divided clock signal. In some embodiments, the time delay can correspond to a time duration between a rising edge (or falling edge) of the first one of the <NUM> pulses and a rising edge (or falling edge) of the output pulse. For example, the time delay can be a time duration up to at least one period of the VCO <NUM> of <FIG> (Tvco).

By way of another example, the pulse swallow divider <NUM> can be configured to increase a time delay range in which a time delay can be applied to the divided clock signal. For example, the control circuitry <NUM> of <FIG> can generate the divider digital code <NUM> to be <NUM> or <NUM> in binary (e.g., b'<NUM>) to configure the pulse swallow divider <NUM> to output a pulse in response to detecting <NUM> pulses of the divided clock signal. In some embodiments, the time delay can correspond to a time duration between a rising edge (or falling edge) of the first one of the <NUM> pulses and a rising edge (or falling edge) of the output pulse. For example, the time delay can be a time duration up to at least two periods of the VCO <NUM> of <FIG> (2Tvco).

In the illustrated example of <FIG>, the MMD <NUM> is coupled to the DCDL <NUM>. For example, an input (e.g., a DCDL input) of the DCDL <NUM> is coupled to an output (e.g., a divider output, a pulse swallow divider output) of the pulse swallow divider <NUM>, and/or, more generally, the MMD <NUM> via one or more electrical connections.

In some embodiments, the DCDL <NUM> is a DCDL circuit that can delay the delayed clock signal from the pulse swallow divider <NUM> by a time delay in a time delay range. For example, the control circuitry <NUM> of <FIG> can generate and/or output DCDL digital code <NUM> (identified by DCDL[M:<NUM>]) to instruct the DCDL <NUM> to delay the divided clock signal by a time delay in a time delay range. For example, the DCDL <NUM> can be configured to receive the DCDL digital code <NUM> via a third I/O port <NUM>.

In the illustrated example, the DCDL digital code <NUM> is an M+<NUM> bit digital word. For example, the DCDL digital code <NUM> can be a <NUM>-bit digital word that can configure the DCDL <NUM> to divide the divided clock signal in a time delay range from <NUM> to TVCO. By way of example, the DCDL digital code <NUM> can be <NUM> or <NUM> in binary (e.g., b'<NUM>) that corresponds to a zero time delay and/or a minimum time delay in a time delay range up to at least TVCO. In some embodiments, the DCDL digital code <NUM> can be <NUM> or <NUM> in binary (e.g., b' <NUM>) that corresponds to a time delay of TVCO.

In some embodiments, the DCDL digital code <NUM> can be a digital code of a plurality of digital codes associated with a second range of time delays. For example, the DCDL digital code <NUM> can be a first digital code associated with a first time delay of TVCO, a second digital code associated with a second time delay of 2TVCO, etc. In some embodiments, the second range of time delays can be implemented by a range of <NUM> (or other value) up to at least (M+<NUM>)*Tvco.

In the illustrated example, the DCDL <NUM> can be configured to delay the divided clock signal from the pulse swallow divider <NUM> to generate a feedback clock signal <NUM> (identified by FBCLK). In some embodiments, the feedback clock signal <NUM> can correspond to and/or implement the feedback clock signal <NUM> of <FIG>. In the illustrated example, the DCDL <NUM> can output the feedback clock signal <NUM> via a fourth I/O port <NUM>. For example, the DCDL <NUM> can output the feedback clock signal <NUM> to the second input of the PD <NUM> via the fourth I/O port <NUM>.

In example operation, the pulse swallow divider <NUM>, and/or, more generally, the MMD <NUM>, can receive the divider digital code <NUM> to configure the count threshold of the pulse swallow divider <NUM>. For example, the divider digital code <NUM> can correspond to a first time delay of TVCO. The divisor <NUM> can receive the clock signal <NUM> from the VCO <NUM> and divide the clock signal <NUM> by a divisor to generate a divided clock signal. The pulse swallow divider <NUM> can delay the divided clock signal by the first time delay to generate a delayed clock signal.

In example operation, the DCDL can receive the DCDL digital code <NUM> to configure a time delay that the DCDL <NUM> is to apply to the delayed clock signal. The DCDL <NUM> can receive the delayed clock signal. The DCDL <NUM> can delay the delayed clock signal by the time delay to generate the feedback clock signal <NUM>. Beneficially, the feedback clock signal <NUM> can cause a reduction of a difference between the doubled reference clock signal <NUM> and the feedback clock signal <NUM> of <FIG>. In some embodiments, the difference is representative of an error generated by duty cycle distortion associated with the doubled reference clock signal <NUM>, and, beneficially, the MMD <NUM> and/or the DCDL <NUM> can be configured to generate the feedback clock signal <NUM> to reduce the error.

<FIG> is a graph <NUM> of example time delays in example time delay ranges that may be achieved by a PLL, such as the PLL <NUM> of <FIG>, or portion(s) thereof. For example, the graph <NUM> can represent a time delay that can be applied to a clock signal as a function of a configuration of at least one of the MMD <NUM> or the DCDL <NUM> of <FIG>. The x-axis <NUM> of the graph <NUM> (identified by Digital Control Codes) represents a plurality of digital codes (e.g., digital control codes) in an example range of <NUM> to <NUM>. The y-axis <NUM> of the graph <NUM> (identified by time delay (TD)) represents time delays in example ranges of <NUM> to TVCO and TVCO to 2TVCO (e.g., <NUM>*TVCO).

In the illustrated example, the DCDL <NUM> can be configured such that a first digital code (e.g., a digital code of <NUM>) can produce a negligible or zero time delay and a second digital code (e.g., a digital code of <NUM>) can produce a time delay of TVCO. For example, the DCDL <NUM> can be configured to apply a time delay to a clock signal in a first time delay range <NUM> of <NUM> (or a different value) up to at least TVCO. The first time delay range is identified in <FIG> by REGION I.

In the illustrated example, the time delay range of <NUM> to TVCO can be extended up to at least 2TVCO. For example, if a time delay that is to be applied to a clock signal is greater than TVCO, configurations of the DCDL <NUM> and the MMD <NUM> can be adjusted, changed, and/or modified to extend the time delay range. For example, the digital control of the DCDL <NUM> can be reset such that the DCDL digital code <NUM> of <FIG> can be reset to a digital code of <NUM> and the digital control of the MMD <NUM> can be changed to increase the count threshold of the MMD <NUM>. For example, the control circuitry <NUM> can change the divider digital code <NUM> from <NUM> to <NUM> to change the count threshold of the pulse swallow divider <NUM> from <NUM> to <NUM>. In this example, the change from <NUM> to <NUM> can change the baseline time delay from <NUM> to TVCO to <NUM> to 2TVCO and thereby shift the time delay range from the first time delay range <NUM> to a second time delay range <NUM> (identified by REGION II), which ranges from TVCO up to at least 2TVCO. Beneficially, configurations of at least one of the DCDL <NUM> or the MMD <NUM> can be changed as described above to increase the time delay range by increments of at least TVCO (e.g., increase from 2TVCO to 3TVCO, from 3TVCO to 4TVCO, etc.).

<FIG> depicts a schematic illustration of another example PLL <NUM>. The PLL <NUM> of this example includes the reference clock signal <NUM>, the output clock signal <NUM>, the frequency doubler <NUM>, the doubled reference clock signal <NUM>, the PD <NUM>, the feedback clock signal <NUM>, the LF <NUM>, the VCO <NUM>, the MMD <NUM>, the DCDL <NUM>, the control circuitry <NUM>, and the control signal(s) <NUM> of <FIG>.

The PLL <NUM> of the illustrated example includes a retimer <NUM> that can be configured to delay the divided clock signal from the MMD <NUM>. In some embodiments, the retimer <NUM> is a retimer circuit that can be configured to delay the divided clock signal by a time delay in a time delay range up to at least a period of the VCO <NUM> (e.g., TVCO). In this example, an output of the MMD <NUM> is coupled to an input (e.g., a retimer input) of the retimer <NUM>. In this example, an output (e.g., a retimer output) of the retimer <NUM> is coupled to an input of the DCDL <NUM>. In some embodiments, the MMD <NUM> is coupled to the DCDL <NUM> through the retimer <NUM>. Although only retimer <NUM> is depicted in <FIG>, one or more additional retimers (e.g., retimer stages) and/or types of retimers may be utilized in the PLL <NUM>.

Beneficially, the time delay introduced by the retimer <NUM> can achieve a reduction (e.g., a further reduction) in the duty cycle distortion of the PLL <NUM> in combination with at least one of the MMD <NUM> or the DCDL <NUM>. For example, the MMD <NUM> can be configured to provide a first time delay up to at least TVCO, the retimer <NUM> can be configured to provide a second time delay up to at least TVCO, and/or the DCDL <NUM> can be configured to provide a third time delay up to at least TVCO. In some embodiments, the total time delay that can be applied to the output clock signal <NUM> is based on a combination of at least one of the first time delay, the second time delay, or the third time delay. For example, the total time delay that can be applied to the output clock signal <NUM> can be 3TVCO (e.g., <NUM>*TVCO). Beneficially, at least one of the MMD <NUM>, the retimer <NUM>, or the DCDL <NUM> can be configured (e.g., reconfigured) to extend and/or otherwise increase the total time delay that can be achieved, such as by increasing the time delay range of <NUM> to 3TVCO to <NUM> to 4TVCO, <NUM> to 5TVCO, etc..

While an example implementation of the PLL <NUM> is depicted in <FIG>, other implementations are contemplated. For example, one or more blocks, components, functions, etc., of the PLL <NUM> may be combined or divided in any other way. The PLL <NUM> of the illustrated example may be implemented by hardware alone, or by a combination of hardware, software, and/or firmware. For example, the PLL <NUM> may be implemented by one or more analog or digital circuits (e.g., comparators, operational amplifiers, etc.), one or more hardware-implemented state machines, one or more programmable processors, one or more ASICs, etc., and/or any combination(s) thereof. The PLL <NUM> of the illustrated example can be implemented by one or more ICs on the same die or two or more different dies.

<FIG> depicts a schematic illustration of example implementations of the MMD <NUM>, a retimer <NUM>, and the DCDL <NUM> of <FIG> and/or <NUM>. For example, the MMD <NUM> can correspond to and/or implement the MMD <NUM> of <FIG> and/or <NUM>. In some embodiments, the DCDL <NUM> can correspond to and/or implement the DCDL <NUM> of <FIG> and/or <NUM>. In some embodiments, the retimer <NUM> can correspond to and/or implement the retimer <NUM> of <FIG>.

The MMD <NUM> of the illustrated example includes the divisor <NUM> and the pulse swallow divider <NUM> of <FIG>. Further depicted in <FIG> are the clock signal <NUM> and the first I/O port <NUM> of <FIG>. In this example, the pulse swallow divider <NUM>, and/or, more generally, the MMD <NUM>, can be configured by the divider digital code <NUM> of <FIG>, which is received via the second I/O port <NUM>.

In some embodiments, the pulse swallow divider <NUM> can delay the divided clock signal from the divisor <NUM> by a time delay in a time delay range, which can correspond to the divider digital code <NUM>, to generate and/or output a delayed clock signal <NUM> (identified by DVDCLK). For example, the delayed clock signal <NUM> can be a delayed version of the divided clock signal from the divisor <NUM>.

The retimer <NUM> of the illustrated example can be configured to delay the delayed clock signal <NUM> by a time delay. The retimer <NUM> of this example includes a first flip-flop <NUM> (e.g., a first flip-flop circuit), a multiplexer <NUM> (e.g., a multiplexer circuit), and a second flip-flop <NUM> (e.g., a second flip-flop circuit). The first and second flip-flops <NUM>, <NUM> of this example are D flop-flops. Alternatively, the first flip-flop <NUM> and/or the second flip-flop <NUM> may be a different type of a flip-flop or latch. Non-limiting examples of flip-flops include SR flip-flops, JK flip-flops, and T flip-flops.

In the illustrated example, a first input (e.g., a D input, a flip-flop input) of the first flip-flop <NUM> is coupled to an output of the pulse swallow divider <NUM>. An output (e.g., a Q output, a flip-flop output) of the first flip-flop <NUM> is coupled to a second input (identified by <NUM>) (e.g., a second multiplexer input) of the multiplexer <NUM>. A clock input of the first flip-flop <NUM> is coupled to the first I/O port <NUM> such that the clock input can receive the clock signal <NUM>.

In the illustrated example, a first input (identified by <NUM>) (e.g., a first multiplexer input) of the multiplexer <NUM> is coupled to the output of the pulse swallow divider <NUM>. A select input (identified by S) of the multiplexer <NUM> is coupled to a fourth I/O port <NUM> such that the select input can be configured to receive DCDL digital code <NUM> (identified by DCDL[N]). In the illustrated example, the DCDL digital code <NUM> is a <NUM>-bit digital code that is part of DCDL digital code <NUM>. For example, the DCDL digital code <NUM>, which can be provided to the DCDL <NUM> via the third I/O port <NUM>, can be an M-bit digital code of which M-<NUM> bits are provided to the DCDL <NUM> and the Mth bit is provided to the multiplexer <NUM> via the fourth I/O port <NUM>.

In this example, an output (e.g., a multiplexer output) of the multiplexer <NUM> is coupled to a first input (e.g., a D input, a flip-flop input) of the second flip-flop <NUM>. In the illustrated example, an output (e.g., a Q output, a flip-flop output) of the second flip-flop <NUM> is coupled to an input of the DCDL <NUM>. A clock input of the second flip-flop <NUM> is coupled to the first I/O port <NUM> such that the clock input can receive the clock signal <NUM>.

In some embodiments, the retimer <NUM> can be configured to delay the delayed clock signal <NUM> by TVCO according to a mode of operation. For example, in a first mode of operation, the retimer <NUM> can be bypassed. For example, the DCDL digital code <NUM> can have a bit value of <NUM> (e.g., a logic low bit value) that controls the multiplexer <NUM> to select the first input for output as a muxed signal <NUM> (identified by DVDCLK,MUXOUT). In some such embodiments, the multiplexer <NUM> can output the delayed clock signal <NUM> to the second flip-flop <NUM> which, in turn, can output the delayed clock signal <NUM> to the DCDL <NUM>. For example, in the first mode of operation, the retimer <NUM> may not delay the delayed clock signal <NUM>.

In a second mode of operation, the delayed clock signal <NUM> can be routed and/or passed through the retimer <NUM> such that the delayed clock signal <NUM> can be delayed. For example, the DCDL digital code <NUM> can have a bit value of <NUM> (e.g., a logic high bit value) that controls the multiplexer <NUM> to select the second input for output. In some such embodiments, the multiplexer <NUM> can output the output of the first flip-flop <NUM>, which is a retimed clock signal <NUM> (identified by DVDCLK,RETIMED). For example, the first flip-flop <NUM> can cause a delay of the delayed clock signal <NUM> by delaying the output of the delayed clock signal <NUM> by one clock cycle. In some such embodiments, in the second mode of operation, the retimer <NUM> can delay the delayed clock signal <NUM> by TVCO.

Beneficially, the time delay introduced by the retimer <NUM> can achieve a reduction (e.g., a further reduction) in the duty cycle distortion of the PLL <NUM> of <FIG> in combination with at least one of the MMD <NUM> or the DCDL <NUM>. For example, the MMD <NUM> can be configured to provide a first time delay up to at least TVCO, the retimer <NUM> can be configured to provide a second time delay up to at least TVCO, and/or the DCDL <NUM> can be configured to provide a third time delay up to at least TVCO. In some embodiments, the total time delay that can be applied to the clock signal <NUM> is based on a combination of at least one of the first time delay, the second time delay, or the third time delay. For example, the total time delay that can be applied to the clock signal <NUM> can be 3TVCO. Beneficially, at least one of the MMD <NUM>, the retimer <NUM>, or the DCDL <NUM> can be configured (e.g., reconfigured) to extend and/or otherwise increase the total time delay that can be achieved, such as by increasing the time delay range of <NUM> to 3TVCO to <NUM> to 4TVCO, <NUM> to 5TVCO, etc..

<FIG> is a graph <NUM> of example time delays in time delay ranges that may be achieved by a PLL, such as the PLL <NUM> of <FIG>, or portion(s) thereof. For example, the graph <NUM> can represent a time delay that can be applied to a clock signal as a function of a configuration of at least one of the MMD <NUM> or the DCDL <NUM> of <FIG> and/or <NUM>. The x-axis <NUM> of the graph <NUM> (identified by Digital Control Codes) represents a plurality of digital codes (e.g., digital control codes) in an example range of <NUM> to <NUM>. The y-axis <NUM> of the graph <NUM> (identified by time delay (TD)) represents time delays in example ranges of <NUM> to TVCO, TVCO to 2TVCO, and 2TVCO to 3TVCO.

In the illustrated example, the time delay range of <NUM> to TVCO can be extended up to at least 2TVCO. For example, if a time delay that is to be applied to a clock signal is greater than TVCO, configurations of the DCDL <NUM>, the retimer <NUM>, and/or the MMD <NUM> can be adjusted, changed, and/or modified to extend the time delay range. For example, the digital control of the DCDL <NUM> can be reset such that the DCDL digital code <NUM> of <FIG> can be reset to a digital code of <NUM> and the DCDL digital code <NUM> of <FIG> can be changed (e.g., from a logic low bit value to a logic high bit value or vice versa) to delay the delayed clock signal <NUM>. For example, the control circuitry <NUM> can change the DCDL digital code <NUM> such that the retimer <NUM> is not bypassed. In this example, the change from bypassing the retimer <NUM> to not bypassing the retimer <NUM> can change the baseline time delay from <NUM> to TVCO to <NUM> to 2TVCO and thereby shift the time delay range from the first time delay range <NUM> to a second time delay range <NUM> (identified by REGION II), which ranges from TVCO up to at least 2TVCO.

In the illustrated example, the time delay range of <NUM> to 2TVCO can be extended up to at least 3TVCO. For example, if a time delay that is to be applied to a clock signal is greater than 2TVCO, configurations of the DCDL <NUM>, the retimer <NUM>, and/or the MMD <NUM> can be adjusted, changed, and/or modified to extend the time delay range. For example, the digital control of the DCDL <NUM> can be reset such that the DCDL digital code <NUM> of <FIG> can be reset to a digital code of <NUM>, the DCDL digital code <NUM> can be set to not bypass the retimer <NUM>, and the digital control of the MMD <NUM> can be changed to increase the count threshold of the MMD <NUM>. For example, the control circuitry <NUM> can change the divider digital code <NUM> from <NUM> to <NUM> to change the count threshold of the pulse swallow divider <NUM> from <NUM> to <NUM>. In this example, the change from <NUM> to <NUM> can change the baseline time delay from <NUM> to 2TVCO and thereby shift the time delay range from the second time delay range <NUM> to a third time delay range <NUM> (identified by REGION III), which ranges from 2TVCO up to at least 3TVCO. Beneficially, configurations of at least one of the DCDL <NUM> or the MMD <NUM> can be changed as described above to increase the time delay range by increments of at least TVCO (e.g., increase from 2TVCO to 3TVCO, from 3TVCO to 4TVCO, etc.).

<FIG> depicts a timing diagram <NUM> representative of example operation of the multi-modulus divider <NUM>, the retimer <NUM>, and the DCDL <NUM> of <FIG>. For example, the timing diagram <NUM> can be representative of example operation of the MMD <NUM>, the retimer <NUM>, and/or the DCDL <NUM> of <FIG>. In some embodiments, the timing diagram <NUM> represents a first time delay that can be applied to a clock signal by the MMD <NUM>, a second time delay that can be applied to the clock signal by the retimer <NUM>, and/or a third time delay that can be applied to the clock signal by the DCDL <NUM>.

The timing diagram <NUM> of the illustrated example includes a first waveform <NUM>, a second waveform <NUM>, a third waveform <NUM>, a fourth waveform <NUM>, a fifth waveform <NUM>, and a sixth waveform <NUM>.

The first waveform <NUM> can be an example waveform of the clock signal <NUM> of <FIG> and/or <NUM>. The second waveform <NUM> can be an example waveform of the delayed clock signal <NUM> of <FIG>. The third waveform <NUM> can be an example waveform of the retimed clock signal <NUM> of <FIG>. The fourth waveform <NUM> can be an example waveform of the DCDL digital code <NUM> of <FIG>. The fifth waveform <NUM> can be an example waveform of the muxed signal <NUM> of <FIG>. The sixth waveform <NUM> can be an example waveform of the feedback clock signal <NUM> of <FIG> and/or <NUM>.

At a first time <NUM> (identified by T<NUM>) of the timing diagram <NUM>, a rising edge of the delayed clock signal <NUM> is asserted. Because the DCDL digital code <NUM> is not asserted, the retimer <NUM> of <FIG> is bypassed and causes the muxed signal <NUM> to output the delayed clock signal <NUM> without a substantive delay. At a second time <NUM> (identified by T<NUM>), a rising edge of the feedback clock signal <NUM> is asserted. For example, the DCDL <NUM> can delay the muxed signal <NUM> by Tvco.

At a third time <NUM> (identified by T<NUM>) of the timing diagram <NUM>, the rising edge of the delayed clock signal <NUM> is asserted after <NUM> VCO clocks (4TVCO). For example, the MMD <NUM> can delay a rising edge of the delayed clock signal <NUM> from being asserted by a time period of 4Tvco.

At a fourth time <NUM> (identified by T<NUM>), a rising edge of the DCDL digital code <NUM> is asserted, which controls operation of the retimer <NUM> such that the retimer <NUM> is not bypassed. For example, the control circuitry <NUM> of <FIG> and/or <NUM> can determine that, based on the error signal of the PD <NUM> of <FIG> and/or <NUM>, additional delay of the feedback clock signal <NUM> is needed. In response to the determination, the control circuitry <NUM> can cause the retimer <NUM> to add the additional delay by causing the multiplexer <NUM> to select the input corresponding to the output of the first flip-flop <NUM>.

At a fifth time <NUM> (identified by T<NUM>), the delayed clock signal <NUM> is asserted after the divisor <NUM> divides the clock signal <NUM> by a divisor and the pulse swallow divider <NUM> swallows a number of pulses of the clock signal <NUM>.

At a sixth time <NUM> (identified by T<NUM>), the muxed signal <NUM> is asserted after a delay of TVCO because the retimer <NUM> is not bypassed. For example, the first flip-flop <NUM> delays the delayed clock signal <NUM> from being provided to the multiplexer <NUM> by a time period of TVCO. In the illustrated example, the time difference between the delayed clock signal <NUM> being asserted at the third time <NUM> and the muxed signal <NUM> being asserted at the sixth time <NUM> corresponds to a delay of 5TVCO (instead of 4TVCO in this example) because of the delay of TVCO introduced by the retimer <NUM>. At a seventh time <NUM> (identified by T<NUM>), the feedback clock signal <NUM> is asserted. For example, the muxed time signal <NUM> is delayed by the DCDL <NUM> by a time delay of TVCO.

<FIG> depicts example implementations of a single-ended mapping duty cycle correction circuit (DCC) <NUM> and a fractional-N divider (Frac-N divider) circuit <NUM>. In some embodiments, the DCC circuit <NUM> can correspond to and/or implement at least a portion of the control circuitry <NUM> of <FIG> and/or <NUM>. In some embodiments, the Frac-N divider circuit <NUM> can correspond to and/or implement at least a portion of the control circuitry <NUM>.

In some embodiments, the DCC circuit <NUM> implements DCC calibration by using a +<NUM>, -<NUM> template to detect digitally controlled delay (DCD) error at the PD output. For example, the DCC circuit <NUM> can use least-mean squared (LMS) background calibration to minimize the error correlated to the DCD template. In some embodiments, the DCD circuit <NUM> can translate an error signal generated by a PD, such as the PD <NUM> of <FIG> and/or <NUM>, into a control signal, such as a digital code. The DCC circuit <NUM> of the illustrated example can implement single-ended mapping because the DCDL <NUM> of <FIG> and/or <NUM> is included in the feedback path of the PLL <NUM> of <FIG> and/or the PLL <NUM> of <FIG>.

The DCC circuit <NUM> includes an inverter <NUM>, delay flip-flops <NUM>, <NUM>, a logic gate <NUM>, an accumulator <NUM>, a multiplier <NUM>, and single-ended mapping logic <NUM>. The inverter <NUM> inverts the DCC template and a first delay flip-flop <NUM> of the delay flip-flops <NUM>, <NUM> outputs the inverted DCC template to the logic gate <NUM>. The logic gate <NUM> of this example is an XOR gate, but any other logic gate and/or combination of logic gates may be used. The XOR gate can output a signal based on a comparison of the inverted DCC template (e.g., a signal representing a logic -<NUM> or a logic +<NUM>) and an error signal (identified by errreg) based on the error signal from the PD <NUM> of <FIG> and/or <NUM> (identified by PDerr). The accumulator <NUM> can accumulate the values of the output signal of the logic gate <NUM> (identified by correrr). The multiplier <NUM> can multiply the non-inverted DCC template and the output of the accumulator to generate a digital code (identified by DCCcode).

In some embodiments, the single-ended mapping logic <NUM> can map the digital code (identified by DCCcode) to an output digital code (identified by DCCmapped). For example, the single-ended mapping logic <NUM> can output the digital code as the output digital code after a determination that the digital code represents a positive value. In some embodiments, the single-ended mapping logic <NUM> can output a portion of the digital code as the output digital code after a determination that the digital code represents a negative value.

In some embodiments, the Frac-N divider circuit <NUM> generates control signals <NUM> to control at least one of the MMD <NUM> of <FIG> and/or <NUM>, the retimer <NUM> of <FIG>, or the DCDL <NUM> of <FIG> and/or <NUM>. For example, the Frac-N divider circuit <NUM> can generate MMDCTRL to control (e.g., change a configuration of) the MMD <NUM>. In some embodiments, the Frac-N divider circuit <NUM> can generate RetimerCTRL to control the retimer <NUM>. In some embodiments, the Frac-N divider circuit <NUM> can generate FBDCDLCTRL to control the DCDL <NUM>.

The Frac-N divider circuit <NUM> includes a second-order sigma-delta modulator <NUM>, an accumulator <NUM>, an adder <NUM>, overflow logic <NUM>, and a delay flip-flop <NUM>. The second-order sigma-delta modulator <NUM> can receive a first digital code <NUM> (identified by FCWFRAC), which can be at least part of a digital word. For example, the first digital code <NUM> can correspond to and/or implement at least part of the control signal(s) <NUM> of <FIG> and/or <NUM>. In this example, the first digital code <NUM> represents a fraction of an integer of which a signal is to be divided. By way of example, if the MMD <NUM> is to delay the clock signal <NUM> by <NUM>, then the first digital code <NUM> can represent <NUM>.

In some embodiments, the second-order sigma-delta modulator <NUM> can output a bit value corresponding to the first digital code <NUM>. The accumulator <NUM> can accumulate the outputs from the second-order sigma-delta modulator <NUM>. The adder <NUM> can add and/or otherwise combine the output from the accumulator <NUM> and a value that corresponds to the second digital code <NUM>. For example, the second digital code <NUM> can correspond to and/or implement at least part of the control signal(s) <NUM> of <FIG> and/or <NUM>. In this example, the second digital code <NUM> represents an integer of which a signal is to be divided. By way of example, if the MMD <NUM> is to delay the clock signal <NUM> by <NUM>, then the second digital code <NUM> can represent <NUM>. The adder <NUM> can output the sum and/or otherwise the combination of the accumulator output and the value corresponding to the second digital code <NUM> to the delay flip-flop <NUM>. The delay flip-flop <NUM> can output the control signals <NUM> to at least one of the MMD <NUM>, the retimer <NUM>, or the DCDL <NUM> to effectuate respective time delays that is/are to be applied to the clock signal <NUM>.

<FIG> depicts example implementations of a differential mapping duty cycle correction circuit (DCC) <NUM> and the Frac-N divider circuit <NUM> of <FIG>. In some embodiments, the DCC circuit <NUM> can correspond to and/or implement at least a portion of the control circuitry <NUM> of <FIG> and/or <NUM>. In some embodiments, the Frac-N divider circuit <NUM> can correspond to and/or implement at least a portion of the control circuitry <NUM>.

In some embodiments, the DCC circuit <NUM> implements DCC calibration by using a +<NUM>, -<NUM> template to detect DCD error at the PD output. For example, the DCC circuit <NUM> can use LMS background calibration to minimize the error correlated to the DCD template. The DCC circuit <NUM> of the illustrated example can implement differential mapping if a first portion of the DCDL <NUM> of <FIG> and/or <NUM> is included in the reference path (e.g., along a path that includes the frequency doubler <NUM>, the PD <NUM>, the LF <NUM>, and/or the VCO <NUM>) of the PLL <NUM> of <FIG> and/or the PLL <NUM> of <FIG> and a second portion of the DCDL <NUM> is included in the feedback path (e.g., a path that includes the MMD <NUM>, the DCDL <NUM>, and/or the PD <NUM>) of the PLL <NUM> of <FIG> and/or the PLL <NUM> of <FIG>.

The differential mapping logic <NUM> can map the digital code (identified by DCCcode) to an output digital code (identified by DCCmapped). For example, the differential mapping logic <NUM> can output the digital code as the output digital code after a determination that the digital code represents a positive value. In some embodiments, the differential mapping logic <NUM> can output an adjustment of the digital code as the output digital code after a determination that the digital code represents a negative value.

<FIG> depicts example timing diagrams <NUM>, <NUM>, <NUM> representative of example operation of the PLL <NUM> of <FIG> and/or the PLL <NUM> of <FIG>. In some embodiments, the timing diagrams <NUM>, <NUM>, <NUM> represent example operation of the PLL <NUM> and/or the PLL <NUM> using the DCC circuit <NUM> of <FIG> and/or the DCC circuit of <FIG>. For example, the timing diagrams <NUM>, <NUM>, <NUM> can represent example locking of the phases of a reference clock signal and a feedback clock signal to reduce duty cycle distortion.

A first timing diagram <NUM> of the timing diagrams <NUM>, <NUM>, <NUM> can represent the effects of duty cycle distortion on the inability to lock phases of a reference clock signal and a feedback clock signal. For example, the first timing diagram <NUM> can represent a first waveform <NUM> corresponding to a reference clock signal, such as the reference clock signal <NUM> of <FIG> and/or <NUM>. The first timing diagram <NUM> can represent a second waveform <NUM> corresponding to a feedback clock signal, such as the feedback clock signal <NUM> of <FIG> and/or <NUM>. In the first timing diagram <NUM>, prior to settling of the DCC circuit <NUM> of <FIG> and/or the DCC circuit <NUM> of <FIG>, the phases of the reference clock signal <NUM> and the feedback clock signal <NUM> are unable to lock.

A second timing diagram <NUM> of the timing diagrams <NUM>, <NUM>, <NUM> can represent the mitigation of the effects of duty cycle distortion due to settling of the DCC circuit <NUM> of <FIG> and/or the DCC circuit of <FIG>. For example, the second timing diagram <NUM> can represent a third waveform <NUM> corresponding to a reference clock signal, such as the reference clock signal <NUM> of <FIG> and/or <NUM>. The second timing diagram <NUM> can represent a fourth waveform <NUM> corresponding to a feedback clock signal, such as the feedback clock signal <NUM> of <FIG> and/or <NUM>. In the second timing diagram <NUM>, after settling of the DCC circuit <NUM> of <FIG> and/or the DCC circuit <NUM> of <FIG>, the phases of the reference clock signal <NUM> and the feedback clock signal <NUM> are able to lock.

A third timing diagram <NUM> of the timing diagrams <NUM>, <NUM>, <NUM> can represent the settling of the DCC circuit <NUM> of <FIG> and/or the DCC circuit <NUM> of <FIG>. For example, the third timing diagram <NUM> can represent a fifth waveform <NUM> of a digital code to control the MMD <NUM>, such as the divider digital code <NUM> of <FIG> and/or <NUM>. The fifth waveform <NUM> depicts a ramping up of the divider digital code <NUM> from <NUM> to <NUM> to <NUM> to <NUM>, etc., to iteratively increase the time delay that the MMD <NUM> applies to the output clock signal <NUM>. The third timing diagram <NUM> can represent a sixth waveform <NUM> of a digital code to control the DCDL <NUM>, such as the DCDL digital code <NUM> of <FIG> and/or the DCDL digital code <NUM> of <FIG>. The sixth waveform <NUM> depicts a ramping up of the DCDL digital code <NUM> and/or the DCDL digital code <NUM> from <NUM> to <NUM> to iteratively increase the time delay that the DCDL <NUM> applies to the output from the MMD <NUM>.

<FIG> is a flowchart <NUM> representative of an example process that may be performed and/or implemented using hardware logic or machine-readable instructions that may be executed by processor circuitry to implement the PLL <NUM> of <FIG> and/or the PLL <NUM> of <FIG>. The flowchart <NUM> of <FIG> begins at block <NUM>, at which the PLL <NUM> and/or the PLL <NUM> receive a reference clock signal. For example, the frequency doubler <NUM> of <FIG> and/or <NUM> can receive the reference clock signal <NUM> and generate the doubled reference clock signal <NUM> according to a doubling of the reference clock signal <NUM>. The PD <NUM> of <FIG> and/or <NUM> can receive the doubled reference clock signal <NUM> from the frequency doubler <NUM>.

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> compare the reference clock signal and a feedback clock signal to detect an error. For example, the PD <NUM> can compare the doubled reference clock signal <NUM> and the feedback clock signal <NUM> to detect an error based on the comparison.

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine whether an error is detected. For example, the PD <NUM> can output a first signal representative of a +<NUM> in response to a determination that a first phase of the doubled reference clock signal <NUM> is greater than a second phase of the feedback clock signal <NUM>. In some embodiments, the PD <NUM> can output a second signal representative of a -<NUM> in response to a determination that the first phase of the doubled reference clock signal <NUM> is less than the second phase of the feedback clock signal <NUM>. If, at block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine(s) that an error is not detected, control proceeds to block <NUM>. Otherwise, control proceeds to block <NUM>.

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine whether the error is greater than a threshold. For example, the control circuitry <NUM> can determine, based on the error signal from the PD <NUM>, that the time delay that can be applied by at least one of the MMD <NUM> or the DCDL <NUM> is less than a time delay needed to correct the error. If, at block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine that the error is not greater than a threshold, control proceeds to block <NUM>. Otherwise, control proceeds to block <NUM>.

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> increase a first range of time delays to a second range of time delays from which to select a time delay to delay the feedback clock signal. For example, the control circuitry <NUM> can configure (e.g., reconfigure) at least one of the MMD <NUM> or the DCDL <NUM> to generate time delay(s) in an increased time delay range. For example, the control circuitry <NUM> can reset the DCDL digital code <NUM> to <NUM> (or another low value) and/or generate the divider digital code <NUM> to increase a count threshold of the pulse swallow divider <NUM>. In some embodiments, such configurations can increase the time delay range from <NUM> to TVCO to <NUM> to 2TVCO as illustrated in the example of <FIG>.

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> delay the feedback clock signal using the time delay to reduce the error. For example, the MMD <NUM> and/or the DCDL <NUM> can delay the clock signal <NUM> by a time delay up to a time delay range of 2TVCO, 3TVCO, etc..

At block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine whether to continue monitoring for the reference clock signal. If, at block <NUM>, the PLL <NUM> and/or the PLL <NUM> determine to continue monitoring for the reference clock signal, control returns to block <NUM>. Otherwise, the flowchart <NUM> of <FIG> concludes.

Embodiments have been described where the techniques are implemented in circuitry and/or machine-executable instructions. It should be appreciated that some embodiments may be in the form of a method, of which at least one example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Various aspects of the embodiments described above may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

The phrase "and/or," as used herein in the specification and in the claims, should be understood to mean "either or both," of the elements so conjoined, e.g., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with "and/or" should be construed in the same fashion, e.g., "one or more" of the elements so conjoined. Thus, as a non-limiting example, a reference to "A and/or B," when used in conjunction with open-ended language such as "comprising" can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc..

As used herein in the specification and in the claims, the phrase, "at least one," in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. Thus, as a non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B," or, equivalently, "at least one of A and/or B") can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, ,and at least one, optionally including more than one, B (and optionally including other elements); etc..

The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any embodiment, implementation, process, feature, etc., described herein as exemplary should therefore be understood to be an illustrative example and should not be understood to be a preferred or advantageous example unless otherwise indicated.

Claim 1:
An apparatus for duty cycle error calibration for an oscillator (<NUM>) having an output providing an output clock signal (CLKOUT), the apparatus comprising:
a multi-modulus divider, MMD, circuit (<NUM>) having an input coupled to the output of the oscillator;
a digitally controlled delay line, DCDL, circuit (<NUM>) having an input coupled to an output of the MMD; and
a phase detector (<NUM>) having a first input coupled to a reference clock signal (REFCLK), a second input coupled to an output of the DCDL, and an output coupled to an input of the oscillator and configured to generate a phase difference between a first phase and a second phase received by the first input and the second input, respectively, of the phase detector;
wherein the apparatus further comprises:
a controller (<NUM>) configured to provide a first digital code corresponding to a first time delay to control the MMD to perform the first time delay to generate a delayed clock signal, and provide a second digital code corresponding to a second time delay to control the DCDL to perform the second time delay to generate a feedback clock signal (FBCLK) to reduce the phase difference output by the phase detector, the first digital code included in a first plurality of digital codes associated with a first range of time delays, and the second digital code included in a second plurality of digital codes associated with a second range of time delays;
wherein the MMD circuit comprises:
a divisor circuit (<NUM>) having a divisor input and a divisor output, wherein the divisor circuit is configured to receive the output clock signal (CLKOUT), and divide the output clock signal to generate a divided clock signal; and
a pulse swallow divider circuit (<NUM>) having a divider input and a divider output, wherein the divider input is coupled to the divisor output, the divider output is coupled to the input of the DCDL circuit, and the pulse swallow divider circuit is configured to:
receive the first digital code that is representative of a count threshold corresponding to the first time delay;
determine whether a count of received pulses of the divider input satisfies the count threshold; and
output a pulse to form the delayed clock signal to be sent to the DCDL circuit every time determining that the count of received pulses satisfies the count threshold.