Patent Description:
<CIT> discloses a semiconductor module including multiple switching elements connected in parallel to each other. Each of the switching elements has a gate electrode, and a first main electrode and a second main electrode through which a main current flows. The semiconductor module includes a first main terminal and a second main terminal serving as external connection terminals in addition to the switching elements.

<CIT> discloses a semiconductor module comprising:.

Further <CIT>, <CIT>, <CIT> and <CIT> were determined to be state of the art. <CIT>, <CIT>, <CIT> and <CIT> concern semiconductor modules and the semiconductor module in <CIT> comprises two switching elements sandwiched between and electrically connected in parallel by first and second conductive portions.

The semiconductor module described above includes, for example, two switching elements. The two switching elements are driven simultaneously by one driver. Hereinafter, one of the two switching elements is referred to as a first switching element, and the other is referred to as a second switching element.

The semiconductor module includes one first main terminal and one second main terminal. The first main terminal and the second main terminal are horizontally arranged along an alignment direction of the two switching elements. In the alignment direction described above, the first main terminal is arranged close to the first switching element, and the second main terminal is arranged close to the second switching element.

For that reason, between the first switching element and the second switching element, a difference occurs in a self-inductance of a current path provided between the second main electrode (for example, the emitter electrode) and the second main terminal (for example, the emitter terminal). Such a difference in self-inductance leads to a difference in parasitic inductance of the current path described above. When the parasitic inductance is different, a different voltage is induced in the parasitic inductance at a time of switching, so that a gate voltage is unbalanced between the first switching element and the second switching element. In other words, an imbalance (a deviation) occurs in the currents flowing through the two switching elements.

An object of the present disclosure is to provide a semiconductor module capable of restricting a current imbalance at a time of switching.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:.

Two embodiments of the invention will be described with reference to the drawings. In the multiple embodiments, functionally and/or structurally corresponding parts are given the same reference numerals. Hereinafter, a thickness direction of switching elements is indicated by a Z-direction, and an alignment direction of the two switching elements, which is orthogonal to the Z-direction, is indicated by an X-direction. A direction orthogonal to both the Z-direction and the X-direction is denoted as a Y-direction. Unless otherwise specified, a shape along an XY plane defined by the X-direction and the Y-direction is a planar shape.

First, a power conversion device to which a semiconductor module is applied will be described with reference to <FIG>.

A power conversion device <NUM> shown in <FIG> is mounted on, for example, an electric vehicle or a hybrid vehicle. The power conversion device <NUM> is configured to convert a DC voltage applied from a DC power supply <NUM> installed in a vehicle into three-phase AC, and output the three-phase AC to a motor <NUM> of the three-phase AC system. The motor <NUM> functions as a travel driving source of the vehicle. The power conversion device <NUM> can also convert an electric power generated by the motor <NUM> into a direct current and charge the DC power supply <NUM>. In this manner, the power conversion device <NUM> is capable of performing a bidirectional power conversion.

The power conversion device <NUM> includes a smoothing capacitor <NUM> and an inverter <NUM>. A positive terminal of the smoothing capacitor <NUM> is connected to a positive electrode, which is a high potential side electrode of the DC power supply <NUM>, and a negative terminal is connected to a negative electrode, which is a low potential side electrode of the DC power supply <NUM>. The inverter <NUM> converts the input DC power into a three-phase AC with a predetermined frequency, and output the three-phase AC to the motor <NUM>. The inverter <NUM> converts the AC power generated by the motor <NUM> into a DC power.

The inverter <NUM> includes six arms. Each arm is configured by a semiconductor module <NUM>. In other words, the six semiconductor modules <NUM> configure the inverter <NUM>. Among the six arms, three arms are upper arms <NUM> and the remaining three arms are lower arms <NUM>. Each upper arm <NUM> and a corresponding lower arm <NUM> are connected in series to each other to configure upper and lower arms for one phase. A connection point between each upper arm <NUM> and the corresponding lower arm <NUM> is connected to an output line <NUM> to the motor <NUM>. The upper and lower arms for three phases configure the inverter <NUM>.

In the present embodiment, an insulated gate bipolar transistor (hereinafter referred to as an IGBT) is employed as the switching element configuring the inverters <NUM>. The semiconductor module <NUM> includes two IGBTs <NUM> and <NUM> connected in parallel to each other. Freewheel diodes 12a and 13a are connected in anti-parallel to the IGBTs <NUM> and <NUM>, respectively. Reference numeral 14a shown in <FIG> denotes gate electrodes of the IGBTs <NUM> and <NUM>. As described above, the switching element has the gate electrode 14a. The two IGBTs <NUM> and <NUM> connected in parallel are driven simultaneously by one driver. In other words, the gate electrodes 14a of the two IGBTs <NUM> and <NUM> are electrically connected to the same driver.

In addition, the IGBTs <NUM> and <NUM> are of an n-channel type. In the upper arm <NUM>, collector electrodes 14b of the IGBTs <NUM> and <NUM> are electrically connected to a high potential power supply line <NUM>. In the lower arm <NUM>, emitter electrodes 14c of the IGBTs <NUM> and <NUM> are electrically connected to a low potential power supply line <NUM>. Emitter electrodes 14c of the IGBTs <NUM> and <NUM> in the upper arm <NUM> and collector electrodes 14b of the IGBTs <NUM> and <NUM> in the lower arm <NUM> are connected to each other.

The power conversion device <NUM> includes, in addition to the inverter <NUM>, a boost converter for boosting a DC voltage supplied from the DC power supply <NUM>, a gate driver circuit for controlling the operation of the switching element configuring the inverter <NUM> and the boost converter, and so on.

Next, a schematic configuration of the semiconductor module <NUM> will be described with reference to <FIG>.

As shown in <FIG>, the semiconductor module <NUM> includes a sealing resin body <NUM>, the IGBTs <NUM> and <NUM>, a first heat sink <NUM>, a terminal <NUM>, a second heat sink <NUM>, first main terminals <NUM>, a second main terminal <NUM>, and signal terminals <NUM>.

The sealing resin body <NUM> is made of, for example, an epoxy resin. The sealing resin body <NUM> is molded by, for example, a transfer molding method. As shown in <FIG>, the sealing resin body <NUM> has one surface 11a orthogonal to the Z-direction, a rear surface 11b opposite to the one surface 11a, and a side surface connecting the one surface 11a and the rear surface 11b. The one surface 11a and the rear surface 11b are flat surfaces, for example.

The IGBTs <NUM> and <NUM> as semiconductor devices are formed on a semiconductor substrate (semiconductor chip) made of silicon and silicon carbide. The IGBTs <NUM> and <NUM> correspond to switching elements connected in parallel to each other. The IGBT <NUM> corresponds to a first switching element, and the IGBT <NUM> corresponds to a second switching element. The IGBTs <NUM> and <NUM> has a meaning as an element configuring a circuit and a meaning as a chip.

In the present embodiment, as described above, both the IGBTs <NUM> and <NUM> are of the n-channel type. The freewheel diodes 12a and 13a described above are also integrally formed in the IGBTs <NUM> and <NUM>. More specifically, the diode 12b is formed in the IGBT <NUM>, and the diode 13a is formed in the IGBT <NUM>. In this way, reverse conduction (RC)-IGBT is employed as the IGBTs <NUM> and <NUM>.

The IGBTs <NUM> and <NUM> has a vertical structure so that a current flows in the Z-direction. Although illustration is omitted, the gate electrode 14a described above is also formed in each of the IGBTs <NUM> and <NUM>. The gate electrode 14a has a trench structure. As shown in <FIG>, collector electrodes 14b are respectively formed on one surfaces of the IGBTs <NUM> and <NUM> in a plate thickness direction of the elements of the IGBTs <NUM> and <NUM>, that is, in the Z-direction, and emitter electrodes 14c are respectively formed on rear surfaces opposite to the one surfaces. The collector electrode 14b also serves as cathode electrodes of the diodes 12a and 13a, and the emitter electrodes 14c also serve as anode electrodes of the diodes 12a and 13a. The collector electrode 14b corresponds to a first main electrode, and the emitter electrode 14c corresponds to a second main electrode.

The IGBTs <NUM> and <NUM> have substantially the same planar shape, specifically, a substantially rectangular planar shape, and have substantially the same size and substantially the same thickness as each other. The IGBTs <NUM> and <NUM> have the same configuration as each other. The IGBTs <NUM> and <NUM> are disposed such that the collector electrodes 14b are on the same side in the Z-direction and the emitter electrodes 14c are on the same side in the Z-direction. The IGBTs <NUM> and <NUM> are positioned at substantially the same height in the Z-direction and are disposed horizontally in the X-direction. The arrangement of the IGBTs <NUM> and <NUM> will be described in detail later.

As shown in <FIG> and <FIG>, pads 14d, which are electrodes for signals, are also formed on the rear surface of the IGBTs <NUM> and <NUM>, that is, the surface on which emitter electrodes are formed. The pads 14d are formed at positions different from the emitter electrodes 14c. The pads 14d are electrically isolated from the emitter electrodes 14c. The pads 14d are formed at an end portion on the opposite side of a formation region of the emitter electrodes 14c in the Y-direction.

In the present embodiment, each of the IGBTs <NUM> and <NUM> has five pads 14d. Specifically, the five pads 14d are provided for a gate electrode, a Kelvin emitter for detecting a potential of the emitter electrode 14c, a current sense, an anode potential of a temperature sensor (temperature sensitive diode) for detecting the temperature of the IGBTs <NUM> and <NUM>, and a cathode potential. The five pads 14d are collectively formed at one end side in the Y-direction and are aligned in the X-direction in the IGBT <NUM> having a substantially rectangular planar shape.

The first heat sink <NUM> functions to dissipate a heat of the IGBTs <NUM> and <NUM> to the outside of the semiconductor module <NUM>, and also serves as a wiring. For that reason, in order to secure thermal conductivity and electrical conductivity, at least a metal material is used. The first heat sink <NUM> is also referred to as a heat radiation plate. The first heat sink <NUM> corresponds to a first conductor plate. In the present embodiment, the first heat sink <NUM> is provided so as to contain the IGBTs <NUM> and <NUM> in a projection view from the Z-direction. The first heat sink <NUM> is disposed closer to one surface 11a of the sealing resin body <NUM> than the IGBTs <NUM> and <NUM> in the Z-direction. The first heat sink <NUM> has a substantially rectangular planar shape with the X-direction as a longitudinal direction. The thickness of the first heat sink <NUM> is kept substantially constant, and a plate thickness direction of the first heat sink <NUM> is substantially parallel to the Z-direction.

The collector electrodes 14b of the IGBTs <NUM> and <NUM> are individually connected to the same surface of the first heat sink <NUM> through solder <NUM>. Most of the first heat sink <NUM> is covered with the sealing resin body <NUM>. Among the surfaces of the first heat sinks <NUM>, a heat radiation surface 15a, which is a surface opposite to the IGBTs <NUM> and <NUM>, is exposed from the sealing resin body <NUM>. The heat radiation surface 15a is substantially flush with one side 11a. A portion of the surface of the first heat sink <NUM> excluding the connection portion with the solder <NUM> and the heat radiation surface 15a is covered with the sealing resin body <NUM>.

The terminals <NUM> are respectively interposed between the IGBT <NUM> and the second heat sink <NUM>, and between the IGBT <NUM> and the second heat sink <NUM>. The terminals <NUM> are provided for the respective IGBTs <NUM> and <NUM>. The terminals <NUM> are made of at least metal material in order to secure thermal conductivity and electrical conductivity because the terminals <NUM> are located on the thermal and electric conduction path between the IGBTs <NUM> and <NUM> and the second heat sink <NUM>. The terminals <NUM> are disposed to face the emitter electrodes 14c of the corresponding IGBTs <NUM> and <NUM>, and are electrically connected to the emitter electrodes 14c through solders <NUM>.

Like the first heat sink <NUM>, the second heat sink <NUM> also functions to dissipate the heat of the IGBTs <NUM> and <NUM> to the outside of the semiconductor module <NUM>, and also functions as a wiring. The second heat sink <NUM> is also referred to as a heat radiation plate. The second heat sink <NUM> corresponds to a second conductor plate. In the present embodiment, the second heat sink <NUM> is also provided so as to enclose the IGBTs <NUM> and <NUM> in a projection view from the Z-direction. The second heat sink <NUM> is disposed on the rear surface 11b of the sealing resin body <NUM> with respect to the IGBTs <NUM> and <NUM> in the Z-direction. The second heat sink <NUM> also has a substantially rectangular planar shape with the X-direction as a longitudinal direction. Four corners of the rectangular planar shape are notched. The second heat sink <NUM> substantially corresponds with the first heat sink <NUM> in a projection view from the Z-direction. A thickness of the second heat sink <NUM> is also kept substantially constant, and the plate thickness direction of the second heat sink <NUM> is substantially parallel to the Z-direction.

The emitter electrodes 14c of the IGBTs <NUM> and <NUM> are individually electrically connected to the same surface of the second heat sink <NUM> through a solder <NUM>. Specifically, the emitter electrode 14c and the second heat sink <NUM> are electrically connected to each other through the solder <NUM>, the terminal <NUM>, and the solder <NUM>. Most of the second heat sink <NUM> is covered with the sealing resin body <NUM>. Among the surfaces of the second heat sinks <NUM>, a heat radiation surface 19a, which is a surface opposite to the IGBTs <NUM> and <NUM>, is exposed from the sealing resin body <NUM>. The heat radiation surface 19a is substantially flush with the rear surface 11b. A portion of the surface of the second heat sink <NUM> excluding a connection portion with the solder <NUM> and the heat radiation surface 19a is covered with the sealing resin body <NUM>.

The first main terminals <NUM> and the second main terminal <NUM> are main terminals through which a main current flows, among the external connection terminals for electrically connecting the semiconductor module <NUM> and an external device. The first main terminals <NUM> are electrically connected to the collector electrodes 14b of the IGBTs <NUM> and <NUM>. For that reason, the first main terminals <NUM> are also referred to as collector terminals. The first main terminals <NUM> are coupled to the first heat sink <NUM> and extend from the first heat sink <NUM> in the Y-direction. The first main terminals <NUM> are electrically connected to the collector electrodes 14b through the first heat sink <NUM> and the solder <NUM>.

As shown in <FIG> and the like, in the present embodiment, the semiconductor module <NUM> includes two first main terminals <NUM>. The same metal plate is processed so that the first main terminals <NUM> are provided integrally with the first heat sink <NUM>. Reference numeral 21a shown in <FIG> denotes a first coupling portion at which the first main terminals <NUM> are coupled to the first heat sink <NUM>. One end of the first main terminals <NUM> serves as a first coupling portion 21a.

The first main terminals <NUM> have a thickness smaller than that of the first heat sink <NUM>, and are coupled to a surface of the first heat sink <NUM> opposite to the heat radiation surface 15a so as to be substantially flush with each other. Each of the first main terminals <NUM> has a bent portion in the sealing resin body <NUM>. As shown in <FIG>, the first main terminals <NUM> protrude to the outside from the vicinity of the center of the side surface 11c of the sealing resin body <NUM> in the Z-direction. Details of the arrangement of the first main terminals <NUM> will be described later.

The second main terminal <NUM> is electrically connected to the emitter electrodes 14c of the IGBTs <NUM> and <NUM>. For that reason, the second main terminal <NUM> is also referred to as an emitter terminal. The second main terminal <NUM> is coupled to the second heat sink <NUM>, and extends from the second heat sink <NUM> in the Y-direction in the same direction as the first main terminals <NUM>. The second main terminal <NUM> is electrically connected to the emitter electrodes 14c through the second heat sink <NUM>, the solder <NUM>, the terminal <NUM>, and the solder <NUM>.

As shown in <FIG> and the like, in the present embodiment, the semiconductor module <NUM> includes one second main terminal <NUM>. The same metal plate is processed so that the second main terminal <NUM> is provided integrally with the second heat sink <NUM>. Reference numeral 22a shown in <FIG> and <FIG> denotes a second coupling portion at which the second main terminal <NUM> is coupled to the second heat sink <NUM>. One end of the second main terminal <NUM> serves as a second coupling portion 22a.

As shown in <FIG>, the second main terminal <NUM> has a thickness smaller than a thickness of the second heat sink <NUM>, and is coupled to a surface of the second heat sink <NUM> opposite to the heat radiation surface 19a so as to be flush with each other. The second main terminal <NUM> has a bent portion in the sealing resin body <NUM>. As shown in <FIG>, the second main terminal <NUM> protrudes to the outside from the side surface 11c from which the first main terminal <NUM> protrudes. Like the first main terminal <NUM>, the second main terminal <NUM> also protrudes to the outside from the vicinity of the center in the Z-direction. Details of the arrangement of the second main terminal <NUM> will be described later.

The signal terminals <NUM> are electrically connected to the corresponding pads 14d of the IGBTs <NUM> and <NUM> through bonding wires <NUM>. In the present embodiment, aluminum-based bonding wire <NUM> are employed. The signal terminals <NUM> are connected to the bonding wire <NUM> inside the sealing resin body <NUM>, and protrude to the outside from the side surface of the sealing resin body <NUM>, more specifically, the surface opposite to the side surface 11c. The signal terminals <NUM> corresponding to the signal terminals IGBTs <NUM> and <NUM> extend in the Y-direction.

In the semiconductor module <NUM> configured as described above, the IGBTs <NUM> and <NUM>, a part of the first heat sink <NUM>, the terminal <NUM>, a part of the second heat sink <NUM>, a part of the first main terminal <NUM>, a part of the second main terminal <NUM>, and a part of the signal terminal <NUM> are integrally sealed by the sealing resin body <NUM>. The IGBTs <NUM> and <NUM> are sealed by the sealing resin body <NUM>. In other words, the elements configuring one arm are sealed. For that reason, the semiconductor module <NUM> is also referred to as a <NUM> in <NUM> package.

The heat radiation surface 15a of the first heat sink <NUM> is substantially flush with the one surface 11a of the sealing resin body <NUM>. In addition, the heat radiation surface 19a of the second heat sink <NUM> is substantially flush with the rear surface 11b of the sealing resin body <NUM>. In this manner, the semiconductor module <NUM> has a double-sided heat radiation structure in which the heat radiation surfaces 15a and 19a are both exposed from the sealing resin body <NUM>. The semiconductor module <NUM> can be formed, for example, by cutting the first heat sink <NUM> and the second heat sink <NUM> together with the sealing resin body <NUM>. The heat radiation surfaces 15a and 19a can also be formed by molding the sealing resin body <NUM> so as to be in contact with a cavity wall surface of a mold for molding the sealing resin body <NUM>.

Next, with reference to <FIG>, a current path and the arrangement of the IGBTs <NUM> and <NUM>, the first main terminal <NUM>, and the second main terminal <NUM> in the semiconductor module <NUM> will be described. <FIG> is a view in which the sealing resin body <NUM> is omitted from <FIG>.

<FIG> is an equivalent circuit diagram of the semiconductor module <NUM> in consideration of inductance. The current path through which the main current flows between the first main terminal <NUM> and the second main terminal <NUM> includes first current paths <NUM> and <NUM> and second current paths <NUM> and <NUM>. The first current path <NUM> is provided between the first coupling portion 21a of the first main terminal <NUM> and the collector electrode 14b of the IGBT <NUM>. The first current path <NUM> is provided between the first coupling portion 21a and the collector electrode 14b of the IGBT <NUM>.

On the other hand, the second current path <NUM> is provided between the second coupling portion 22a of the second main terminal <NUM> and the emitter electrode 14c of the IGBT <NUM>. The second current path <NUM> is provided between the second coupling portion 22a and the emitter electrode 14c of the IGBT <NUM>. The first current paths <NUM> and <NUM> are collector current paths, and the second current paths <NUM> and <NUM> are emitter current paths.

In this example, self-inductances of the first current paths <NUM> and <NUM> are denoted as Lc1 and Lc2, and self-inductances of the second current paths <NUM> and <NUM> are denoted as Ls1 and Ls2. A mutual inductance between the first current path <NUM> and the second current path <NUM> is denoted by M11, a mutual inductance between the second current path <NUM> and the first current path <NUM> is denoted by M12, a mutual inductance between the second current path <NUM> and the first current path <NUM> is denoted by M21, and a mutual inductance between the first current path <NUM> and the second current path <NUM> is denoted by M22.

If a difference occurs in the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> in the IGBTs <NUM> and <NUM> connected in parallel, the difference leads to a difference in the parasitic inductance of the second current paths <NUM> and <NUM>. When the parasitic inductance is different, a different voltage is induced in the parasitic inductance at the time of switching, so that an emitter potential is different, and a gate voltage Vge of the IGBT <NUM> and a gate voltage Vge of the IGBT <NUM> are unbalanced. In other words, an imbalance (a deviation) occurs in the currents flowing through the two IGBTs <NUM> and <NUM>.

Further, the present inventors have thoroughly studied through simulations and the like, and it has been revealed that not only the difference in the self-inductances Ls1 and Ls2 but also the difference in the mutual inductance between each of the second current paths <NUM> and <NUM> and the other current paths is a factor of the difference in the parasitic inductance, that is, a factor of the imbalance of the gate voltage Vge.

Therefore, in the present embodiment, in a configuration in which the multiple IGBTs are connected in parallel, when the self-inductance of an arbitrary current path which is the second current path in any of the IGBTs is denoted by Lsn, a mutual inductance of the arbitrary current path and other current paths except for the arbitrary current path is denoted as Mn, and the sum (inductance sum) of the self-inductance Lsn and the mutual inductance Mn is denoted as Ln, the multiple IGBTs and the multiple current paths are disposed so that the inductance sum Ln of each of the IGBTs becomes equal to each other. The mutual inductance Mn at the time of acting to weaken the self-inductance Lsn is assumed to be negative, and the mutual inductance Mn at the time of acting to strengthen the self-inductance Lsn is assumed to be positive.

Specifically, in the configuration in which the two IGBTs <NUM> and <NUM> are connected in parallel, the IGBTs <NUM> and <NUM> and the current paths (the first current paths <NUM> and <NUM> and the second current paths <NUM> and <NUM>) are disposed so that an inductance sum L1 of the IGBT <NUM> and an inductance sum L2 of the IGBT <NUM> are equal to each other.

A mutual inductance M1 between the second current path <NUM> of the IGBT <NUM> and other current paths is the sum of the mutual inductances M11 and M12, that is, M1 = M11 + M12. A mutual inductance M2 between the second current path <NUM> of the IGBT <NUM> and other current paths is the sum of the mutual inductances M21 and M22, that is, M2 = M21 + M22. The inductance sum L1 of the IGBT <NUM> is the sum of the self-inductance Ls1 and the mutual inductance M1, that is, L1 = Ls1 + M1. The inductance sum L2 of the IGBT <NUM> is the sum of the self-inductance Ls2 and the mutual inductance M2, that is, L2 = Ls2 + M2. Therefore, when L1 = L2 is met, the following relationship is satisfied.

In order to satisfy the relationship of L1 = L2, that is, the relationship of Mathematical Expression <NUM>, in the present embodiment, as shown in <FIG>, the semiconductor module <NUM> includes, as the main terminals, two first main terminals <NUM> and one second main terminal <NUM> as described above. The second main terminal <NUM> is coupled to one end of the second heat sink <NUM> having a substantially rectangular planar shape in the Y-direction. The second coupling portion 22a of the second main terminal <NUM> is provided between a center 12c of the IGBT <NUM> and a center 13c of the IGBT <NUM> in the X-direction, which is the alignment direction of the IGBTs <NUM> and <NUM>. The center of the second coupling portion 22a in a width direction of the second main terminal <NUM> is on a center line CL that passes through the center between the IGBTs <NUM> and <NUM> in the X-direction and is parallel to the Y-direction.

As described above, the configurations of the two IGBTs <NUM> and <NUM> are the same, and the connection structures of the respective IGBTs <NUM> and <NUM> and the first heat sink <NUM> and the second heat sink <NUM> are also the same. Therefore, the difference in the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> is substantially determined according to a positional relationship between the respective emitter electrodes 14c and the second coupling portion 22a, in other words, a positional relationship between the IGBTs <NUM> and <NUM> and the second coupling portion 22a. In the present embodiment, as described above, since the center of the second coupling portion 22a is provided on the center line CL, the self-inductances Ls and Ls2 are substantially equal to each other.

The two first main terminals <NUM> are coupled to one end of the first heat sink <NUM> having a substantially rectangular planar shape in the Y-direction, more specifically, to an end portion on the same side as the end of the second heat sink <NUM> to which the second main terminal <NUM> is coupled. The first main terminals <NUM> are provided so as to sandwich the second main terminal <NUM> between the first main terminals <NUM> in the X-direction. As shown in <FIG>, the first main terminal <NUM>, the second main terminal <NUM>, and the first main terminal <NUM> are disposed in the stated order in the X-direction orthogonal to the plate thickness direction. The two first coupling portions 21a are provided on both sides of the second coupling portion 22a in the X-direction.

The first main terminals <NUM> are coupled to the vicinity of both ends of the first heat sink <NUM> in the X-direction. As a result, in an XY-plane, the IGBTs <NUM> and <NUM>, the two first main terminals <NUM>, and the one second main terminal <NUM> are disposed symmetrically with respect to the center line CL. Therefore, the mutual inductances M1 and M2 are substantially equal to each other. The first heat sink <NUM> and the second heat sink <NUM> are also symmetrical with respect to the center line CL. In this way, in the semiconductor module <NUM>, M1 = M2 is realized in a case of Ls1 = Ls2, whereby L1 = L2 is satisfied.

As described above, according to the semiconductor module <NUM> of the present embodiment, the knowledge that the mutual inductance is also a factor of the current imbalance at the time of switching is utilized. Specifically, the IGBTs <NUM> and <NUM>, and the first main terminal <NUM> and the second main terminal <NUM>, which are the elements that determine the respective current paths <NUM>, <NUM>, <NUM>, and <NUM>, are disposed in consideration of not only the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> but also the mutual inductances M1 and M2 between the second current paths <NUM> and <NUM> and the other current paths. Therefore, the imbalance of the gate voltage Vge of the IGBTs <NUM> and <NUM> at the time of switching and further a current imbalance can be effectively restricted.

Arrows in one-dot chain lines shown in <FIG> indicate a collector current Ic, and arrows in two-dot chain lines indicate an emitter current Ie. The direction of the arrow is a flow direction of current. Reference numeral <NUM> denotes a busbar <NUM> connecting the two first main terminals <NUM>. With the arrangement described above, the collector current Ic and the emitter current Ie flow so as to be line-symmetrical with respect to a center line CL between the IGBTs <NUM> and <NUM>. In this manner, the current imbalance can be effectively restricted.

In the present embodiment, the semiconductor module <NUM> includes the two first main terminals <NUM> and the one second main terminal <NUM>, and the second coupling portion 22a of the second main terminal <NUM> is provided between the IGBT <NUM> and the IGBT <NUM> in the X-direction, which is the alignment direction of the IGBTs <NUM> and <NUM>. The first coupling portions 21a are provided on both sides of the second coupling portion 22a in the X-direction.

Because the second main terminal <NUM> is disposed between the two first main terminals <NUM>, as compared with a conventional configuration in which the first main terminal and the second main terminal are provided one by one, and the first main terminal and the second main terminal are aligned in a direction orthogonal to the plate thickness direction, the deviation of the arrangement of the main terminals can be restricted, thereby being capable of reducing the imbalance of the sum of inductances L1 and L2. This makes it possible to restrict the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching.

In the present embodiment, the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> satisfy the relationship of Ls1 = Ls2, and the present disclosure is limited to this configuration Modifications, not falling under the scope of the claimed invention, are not limited to this configuration.

For example, the IGBTs <NUM> and <NUM>, the first main terminal <NUM>, and the second main terminal <NUM> may be disposed so that the inductance sums L1 and L2 satisfy the relationship of L1 = L2 by setting the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> to Ls1 > Ls2 and setting the mutual inductances M1 and M2 to M1 < M2. In a first modification, not according to the claimed invention, shown in <FIG>, the second main terminal <NUM> is disposed closer to the IGBT <NUM> with respect to the center line CL between the IGBTs <NUM> and <NUM>, thereby satisfying Ls1 > Ls2. The first main terminals <NUM> are disposed on both sides of the second main terminal <NUM> so as to satisfy M1 < M2 to achieve the relationship of L1 = L2.

In addition, the IGBTs <NUM> and <NUM>, the first main terminal <NUM>, and the second main terminal <NUM> may be disposed so that the inductance sums L1 and L2 satisfy the relationship of L1 = L2 by setting the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> to Ls1 < Ls2 and setting the mutual inductances M1 and M2 to M1 > M2. In a second modification, not according to the claimed invention, shown in <FIG>, the second main terminal <NUM> is disposed closer to the IGBT <NUM> with respect to the center line CL between the IGBTs <NUM> and <NUM>, thereby satisfying Ls1 < Ls2. In addition, the first main terminals <NUM> are disposed on both sides of the second main terminal <NUM> so as to satisfy M1 > M2 to achieve the relationship of L1 = L2.

The present embodiment according to the claimed invention can refer to the preceding embodiment. For that reason, a description of portions common to the semiconductor module <NUM> described in the preceding embodiment will be omitted.

As shown in <FIG>, a semiconductor module <NUM> of the present embodiment according to the claimed invention includes one first main terminal <NUM> and two second main terminals <NUM> as main terminals. <FIG> corresponds to <FIG>, and a sealing resin body <NUM> will be omitted from illustration. The configuration is substantially the same as that of the first embodiment (refer to <FIG>) except that the number and coupling positions of the first main terminal <NUM> and the second main terminals <NUM> are different.

In <FIG>, IGBTs <NUM> and <NUM>, a first main terminal <NUM>, and second main terminals <NUM> are disposed so as to satisfy a relationship of L1 = L2 by Ls1 = Ls2 and M1 = M2. Specifically, the first main terminal <NUM> is provided between the IGBTs <NUM> and <NUM> in the X-direction so that a center of a first coupling portion 21a of the first main terminal <NUM> in a width direction is located on a center line CL. The second main terminals <NUM> are coupled to the vicinity of both ends of the second heat sink <NUM> in the X-direction. As a result, in an XY-plane, the arrangement of the IGBTs <NUM> and <NUM>, one first main terminal <NUM>, and two second main terminals <NUM> is line-symmetrical with respect to the center line CL.

In this manner, in the configuration including one first main terminal <NUM> and two second main terminals <NUM>, M1 = M2 is realized in a case of Ls1 = Ls2, thereby satisfying L1 = L2. Therefore, similarly to the preceding embodiment, the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching can be effectively restricted.

Reference numeral <NUM> shown in <FIG> denotes a busbar connecting the two second main terminals <NUM>. With the above arrangement, a collector current Ic and an emitter current Ie flow in a line-symmetrical manner with respect to the center line CL between the IGBTs <NUM> and <NUM>. In this manner, the current imbalance can be effectively restricted.

In the present embodiment, the semiconductor module <NUM> includes one first main terminal <NUM> and two second main terminals <NUM>, and the first coupling portion 21a of the first main terminal <NUM> is provided between the IGBT <NUM> and the IGBT <NUM> in the X-direction, which is the alignment direction of the IGBTs <NUM> and <NUM>. The second coupling portions 22a are provided on both sides of the first coupling portion 21a in the X-direction.

Since the two second main terminals <NUM> are disposed so as to sandwich the first main terminal <NUM> between the second main terminals <NUM>, the deviation of the arrangement of the main terminals can be restricted, thereby being capable of reducing the unbalance of the inductance sums L1 and L2, as compared with the conventional configuration in which the first main terminal and the second main terminal are provided one by one, and the first main terminal and the second main terminal are disposed side by side in the direction orthogonal to the plate thickness direction. This makes it possible to restrict the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching.

Also, in the present embodiment, the self-inductances Ls1 and Ls2 of the second current paths <NUM> and <NUM> are limited to an example satisfying the relationship of Ls1 = Ls2. In the modified configuration, not falling within the scope of the claimed invention, including one first main terminal <NUM> and two second main terminals <NUM> shown in the modified example, M1 < M2 may be realized in a case of Ls1 > Ls2, thereby satisfying the relationship of L1 = L2. Also, M1 > M2 may be realized in a case of Ls1 < Ls2, thereby satisfying a relationship L1 = L2.

The present alternative which is not part of the invention can refer to the preceding embodiment of the invention. For that reason, a description of portions common to the semiconductor module <NUM> described in the preceding embodiment of the invention will be omitted.

As shown in <FIG>, a semiconductor module <NUM> according to the present alternative has a first main terminal <NUM> and a second main terminal <NUM> one by one. <FIG> corresponds to <FIG>, and a sealing resin body <NUM> will be omitted from illustration. In <FIG>, for convenience of description, the first main terminal <NUM> is shown with a slight displacement. The configuration is substantially the same as that of the first embodiment of the invention (refer to <FIG>) except that the number and coupling positions of the first main terminal <NUM> and the second main terminals <NUM> are different.

In <FIG>, IGBTs <NUM> and <NUM>, the first main terminal <NUM>, and second main terminals <NUM> are disposed so as to satisfy a relationship of L1 = L2 by Ls1 = Ls2 and M1 = M2. Specifically, the first main terminal <NUM> and the second main terminal <NUM> extend on the same side in the Y-direction. The first main terminal <NUM> and the second main terminal <NUM> are provided between IGBTs <NUM> and <NUM> in the X-direction so that a center of a first coupling portion 21a of the first main terminal <NUM> in the width direction and a center of a second coupling portion 22a of the second main terminal <NUM> in the width direction are both located on a center line CL. As a result, in an XY-plane, the arrangement of the IGBTs <NUM> and <NUM>, one first main terminal <NUM>, and one second main terminal <NUM> is line-symmetrical with respect to the center line CL.

In this manner, in the configuration including one first main terminal <NUM> and one second main terminal <NUM>, M1 = M2 is realized in a case of Ls1 = Ls2, thereby satisfying L1 = L2. Therefore, similarly to the preceding embodiment of the invention, the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching can be restricted. In particular, the current imbalance of the IGBTs <NUM> and <NUM> can be effectively restricted while reducing the number of main terminals.

With the above arrangement, as shown in <FIG>, a collector current Ic and an emitter current Ie flow so as to be line-symmetrical with respect to the center line CL between the IGBTs <NUM> and <NUM>. In this manner, the current imbalance can be effectively restricted.

In the present alternative which is not part of the invention, the semiconductor module <NUM> includes one first main terminal <NUM> and one second main terminal <NUM>, and the first coupling portion 21a of the first main terminal <NUM> and the second coupling portion 22a of the second main terminal <NUM> are provided between the IGBT <NUM> and the IGBT <NUM> in the X-direction, which is the alignment direction of the IGBTs <NUM> and <NUM>. A first heat sink <NUM> corresponds to a first conductor portion, and the second heat sink <NUM> corresponds to a second conductor portion.

Since the first coupling portion 21a and the second coupling portion 22a are both provided between the IGBT <NUM> and <NUM> in the X-direction, compared to a configuration in which one first main terminal and one second main terminal are provided, and at least one of the first coupling portion and the second coupling portion is provided outside the space between the two IGBTs, it is possible to restrict the deviation of the arrangement of the main terminals, thereby reducing the unbalance between the inductances L1 and L2. This makes it possible to restrict the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching while reducing the number of main terminals.

It should be noted that the self-inductance Ls1 and Ls2 of the second current paths <NUM> and <NUM> is not limited to the case in which the self-inductance satisfies the relationship of Ls1 = Ls2. In the configuration including one first main terminal <NUM> and one second main terminal <NUM> shown in the present alternative which is not part of the invention, M1 < M2 may be realized in a case of Ls1 > Ls2, thereby satisfying the relationship L1 = L2. Also, M1 > M2 may be realized in a case of Ls1 < Ls2, thereby satisfying a relationship L1 = L2.

Though not mentioned in particular, in the case where the first main terminal <NUM> and the second main terminal <NUM> are disposed so as to overlap with each other more or less in a projection view in the Z-direction, an electrically insulating spacer disposed between the first main terminal <NUM> and the second main terminal <NUM> may be further provided. The spacer is in close contact with a side surface 11c of the sealing resin body <NUM>. The spacer can restrict a resin from leaking from a space between the first main terminal <NUM> and the second main terminal <NUM> at the time of molding the sealing resin body <NUM>. Incidentally, with removal of the spacer after molding, the semiconductor module <NUM> can be configured not to include the spacer.

The configuration in which the first coupling portion 21a and the second coupling portion 22a are provided between the IGBTs <NUM> and <NUM> in the X-direction is not limited to the example described above. For example, as in an alternative modification shown in <FIG>, which is not part of the invention, the first main terminal <NUM> and the second main terminal <NUM> may extend on opposite sides in the Y-direction. In particular, in <FIG>, as in <FIG>, the center of the first coupling portion 21a in the width direction and the center of the second coupling portion 22a in the width direction are both located on the center line CL. For that reason, the current imbalance of the IGBTs <NUM> and <NUM> can be more effectively restricted. In <FIG>, a signal terminal <NUM> and a bonding wire <NUM> are omitted for convenience.

The present alternative which is not part of the invention can refer to the preceding alternative. For that reason, a description of portions common to the semiconductor module <NUM> described in the preceding alternative will be omitted.

In the first alternative which is not part of the invention, the first main terminal <NUM> and the second main terminal <NUM> are provided one by one, and the first coupling portion 21a and the second coupling portion 22a are both provided between the IGBTs <NUM> and <NUM> in the X-direction in the double-sided heat radiation structure. Conversely, in the present alternative which is not part of the invention, as shown in <FIG>, in a one-sided heat radiation structure, a first main terminal <NUM> and a second main terminal <NUM> are provided one by one, and a first coupling portion 21a and a second coupling portion 22a are both provided between IGBTs <NUM> and <NUM> in the X-direction.

A semiconductor module <NUM> shown in <FIG> includes an insulating plate <NUM>, conductor layers <NUM> and <NUM>, and a bonding wire <NUM> in addition to the two IGBTs <NUM> and <NUM>, the first main terminal <NUM>, and the second main terminal <NUM>. The insulating plate <NUM> is made of an electrically insulating material such as ceramics. The conductor layers <NUM> and <NUM> made of a metal material such as copper are provided on one surface of the insulating plate <NUM>. The conductor layers <NUM> and <NUM> are provided on the same surface and are electrically separated from each other.

IGBTs <NUM> and <NUM> are mounted on the conductor layer <NUM>. The IGBTs <NUM> and <NUM> are disposed such that collector electrode forming surfaces face the conductor layer <NUM>, and a collector electrode 14b (not shown) and the conductor layer <NUM> are electrically connected to each other through solder or the like. The IGBTs <NUM> and <NUM> are disposed side by side in the X-direction.

The first main terminal <NUM> is connected to the conductor layer <NUM>. For example, the first main terminal <NUM> is connected to the conductor layer <NUM> through solder (not shown). A connection portion with the conductor layer <NUM> serves as a first coupling portion 21a of the first main terminal <NUM>. The first coupling portion 21a is provided between the center of the IGBT <NUM> and the center of the IGBT <NUM> in the X-direction. The conductor layer <NUM> corresponds to a first conductor portion.

Emitter electrodes 14c (not shown) of the IGBTs <NUM> and <NUM> are electrically connected to the conductor layer <NUM> through bonding wires <NUM>. The conductor layer <NUM> and the bonding wires <NUM> correspond to a second conductor portion. The second main terminal <NUM> is connected to the conductor layer <NUM>. For example, the second main terminal <NUM> is connected to the conductor layer <NUM> through solder (not shown). The connection portion with the conductor layer <NUM> serves as a second coupling portion 22a of the second main terminal <NUM>. The second coupling portion 22a is also provided between the center of the IGBT <NUM> and the center of the IGBT <NUM> in the X-direction.

As described above, in the present alternative which is not part of the invention, since the first coupling portion 21a and the second coupling portion 22a are both provided between the IGBT <NUM> and <NUM> in the X-direction, compared to a configuration in which one first main terminal and one second main terminal are provided, and at least one of the first coupling portion and the second coupling portion is provided outside the space between the two IGBTs, it is possible to restrict the deviation of the arrangement of the main terminals, thereby reducing the unbalance between the inductances L1 and L2. This makes it possible to restrict the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching while reducing the number of main terminals.

Further, in the present alternative which is not part of the invention, the conductor layer <NUM> is substantially U-shaped in a plane. The conductor layer <NUM> has one bent portion of <NUM> degrees. Then, the IGBT <NUM> is attached to one end side of the conductor layer <NUM>, and the IGBT <NUM> is attached to the other end side. The first main terminal <NUM> is coupled to the vicinity of the center of the conductor layer <NUM> so that the center of the first coupling portion 21a in the width direction is located on the center line CL. The first main terminal <NUM> extends in the Y-direction. The conductor layer <NUM> is disposed between opposing regions of the conductor layer <NUM>. The conductor layers <NUM> are disposed between the IGBTs <NUM> and <NUM>. The conductor layer <NUM> is provided on the center line CL. The second main terminal <NUM> is coupled to the conductor layer <NUM> so that the center of the second coupling portion 22a in the width direction is located on the center line CL. The second main terminal <NUM> has a bent portion, and is disposed so as to overlap with the first main terminal <NUM> in a projection view in the Z-direction.

As a result, in an XY-plane, the arrangement of the IGBTs <NUM> and <NUM>, one first main terminal <NUM>, and one second main terminal <NUM> is line-symmetrical with respect to the center line CL. In this manner, in the configuration including one first main terminal <NUM> and one second main terminal <NUM>, M1 = M2 is realized in a case of Ls1 = Ls2, thereby satisfying L1 = L2. Therefore, similarly to the preceding embodiments and alternatives, the current imbalance of the IGBTs <NUM> and <NUM> at the time of switching can be effectively restricted.

In the one-sided heat radiation structure, a configuration in which the first main terminal <NUM> and the second main terminal <NUM> are provided one by one, and the first coupling portion 21a and the second coupling portion 22a are provided between the IGBTs <NUM> and <NUM> is not limited to the above examples. For example, as in the alternative modification shown in <FIG>, which is not part of the invention, the first main terminal <NUM> and the second main terminal <NUM> may have a structure extending in the Z-direction. In <FIG>, each of the first main terminal <NUM> and the second main terminal <NUM> has an L-shape with a bent portion of approximately <NUM> degrees. The other configuration is the same as that of <FIG>. Even in such a configuration, the collector current Ic and the emitter current Ie flow so as to be line-symmetrical with respect to the center line CL (not shown) between the IGBTs <NUM> and <NUM>. Therefore, the current imbalance can be effectively restricted.

In an alternative modification shown in <FIG>, wich is not part of the invention, a metal lead <NUM> is used instead of the conductor layer <NUM> and the bonding wire <NUM>. The lead <NUM> corresponds to a second conductor portion. The lead <NUM> extends in the X-direction. The lead <NUM> has two bent portions, and bridges emitter electrodes 14c (not shown) of the IGBTs <NUM> and <NUM>. The second main terminal <NUM> is coupled to the lead <NUM>. The second main terminal <NUM> and the lead <NUM> are integrated together by processing the same metal plate. The second main terminal <NUM> has a planar L-shape. As a result, the second coupling portion 22a is provided on the center line CL (not shown) and does not overlap with the first main terminal <NUM> in a projection view in the Z-direction. Even in such a configuration, the collector current Ic and the emitter current Ie flow so as to be line-symmetrical with respect to the center line CL (not shown) between the IGBTs <NUM> and <NUM>. Therefore, the current imbalance can be effectively restricted.

The semiconductor module <NUM> may further include a heat radiation member such as a heat sink or a sealing resin body. The heat radiation member is connected to a surface of the insulating plate <NUM> opposite to the conductor layers <NUM> and <NUM>. The sealing resin body seals the IGBT <NUM>, the sealing resin body <NUM>, and the like.

Although an example in which the semiconductor module <NUM> is applied to the inverter <NUM> has been described, the present disclosure is not limited to the above example. For example, the present disclosure can be applied to a boost converter. The present disclosure can also be applied to both the inverter <NUM> and the boost converter.

Although the freewheel diodes 12a and 13a are formed integrally with the IGBTs <NUM> and <NUM>, the present disclosure is not limited to the above example. The freewheel diodes 12a and 13a may be provided as separate chips.

Although examples of the IGBTs <NUM> and <NUM> are shown as the switching elements, the switching elements are not limited to the above example. A switching element having a gate electrode, a first main electrode and a second main electrode through which a main current flows may be used. For example, a MOSFET may be employed. The present disclosure is limited to a vertical switching element. Modifications, not falling within the scope of the claimed invention, can be applied, employing a horizontal switching element (for example, a LDMOS).

Although an example in which the terminal <NUM> is provided as the semiconductor module <NUM> having a double-sided heat radiation structure has been described, the present disclosure is not limited to the above example. A configuration without the terminal <NUM> may also be employed. For example, instead of the terminal <NUM>, the second heat sink <NUM> may be provided with a projection portion projecting toward the emitter electrode 14c. In addition, the heat radiation surfaces 15a and 19a has been presented as an example of being exposed from the sealing resin body <NUM>, but the heat radiation surfaces <NUM> and 19a may not been exposed from the sealing resin body <NUM>. Furthermore, the sealing resin body <NUM> may not be provided.

The example in which the semiconductor module <NUM> includes the two IGBTs <NUM> and <NUM> connected in parallel, but are not limited to this example. The present disclosure is also applicable to a configuration in which three or more IGBTs are connected in parallel. For example, in an alternative modification shown in <FIG>, which is not part of the invention, three IGBTs <NUM>, <NUM> and <NUM> are provided. The collector electrodes 14b of the IGBTs <NUM> and <NUM>, and <NUM> are connected to the same first heat sink <NUM>, and the emitter electrodes 14c of the IGBTs <NUM> and <NUM>, and <NUM> are connected to the same second heat sink <NUM>.

Claim 1:
A semiconductor module comprising:
two switching elements (<NUM>, <NUM>) each including a first main electrode (14b) formed on one surface side, and a second main electrode (14c) and a gate electrode (14a) formed on a rear surface side opposite to the one surface side in a thickness direction of the switching elements (<NUM>, <NUM>), disposed side by side in such a manner that the respective one surfaces are disposed on a same side, and connected in parallel to each other;
two first main terminals (<NUM>) and a second main terminal (<NUM>) serving as external connection terminals; and
a first conductor plate (<NUM>) to which the two first main terminals (<NUM>) are coupled and both the first main electrodes (14b) of the two switching elements (<NUM>, <NUM>) are electrically connected, and a second conductor plate (<NUM>) to which the second main terminal (<NUM>) is coupled and both the second main electrodes (14c) of the two switching elements (<NUM>, <NUM>) are electrically connected, wherein
the two switching elements (<NUM>, <NUM>) are disposed horizontally in an alignment direction orthogonal to the thickness direction,
one end of the second main terminal (<NUM>) serves as a second coupling portion (22a) coupled with the second conductor plate (<NUM>), and a center of the second coupling portion (22a) in a width direction of the second coupling portion (22a) is disposed on a center line (CL) that passes through a center between the two switching elements (<NUM>, <NUM>) in the alignment direction, and
one end of each of the first main terminals (<NUM>) serves as a first coupling portion (21a) coupled with the first conductor plate (<NUM>), and the first coupling portions (21a) are provided on both sides of the second coupling portion (22a) in the alignment direction.