Patent Description:
Computing memory systems are generally composed of one or more dynamic random access memory (DRAM) integrated circuits, referred to herein as DRAM devices, which are connected to one or more processors. Multiple DRAM devices may be arranged on a memory module, such as a dual in-line memory module (DIMM). A DIMM includes a series of DRAM devices mounted on a printed circuit board (PCB) and are typically designed for use in personal computers, workstations, servers, or the like. There are different types of memory modules, including a load-reduced DIMM (LRDIMM) for Double Data Rate Type three (DDR3), which have been used for large-capacity servers and high-performance computing platforms. Memory capacity may be limited by the loading of the data (DQ) bus and the request (RO) bus associated with the user of many DRAM devices and DIMMs. LRDIMMs may increase memory capacity by using a memory buffer component (also referred to as a register). Registered memory modules have a register between the DRAM devices and the system's memory controller. For example, a fully buffer-componented DIMM architecture introduces an advanced memory buffer component (AMB) between the memory controller and the DRAM devices on the DIMM. The memory controller communicates with the AMB as if the AMB were a memory device, and the AMB communicates with the DRAM devices as if the AMB were a memory controller. The AMB can buffer component data, command and address signals. With this architecture, the memory controller does not write to the DRAM devices, rather the AMB writes to the DRAM devices
<CIT> relates to a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.

Lithographic feature size has steadily reduced as each successive generation of DRAM has appeared in the marketplace. As a result, the device storage capacity of each generation has increased. Each generation has seen the signaling rate of interfaces increase, as well, as transistor performance has improved.

Unfortunately, one metric of memory system design which has not shown comparable improvement is the module capacity of a standard memory channel. This capacity has steadily eroded as the signaling rates have increased.

Part of the reason for this is the link topology used in standard memory systems. When more modules are added to the system, the signaling integrity is degraded, and the signaling rate must be reduced. Typical memory systems today are limited to just two or three modules when operating at the maximum signaling rate.

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

The examples described herein describe technologies for memory systems. The invention is set out as defined by the appended claims.

One implementation of a memory system includes a motherboard substrate with multiple module sockets, one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines include a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. The first set of data lines may also include a third subset of point-to-point data lines coupled between the memory controller and a third socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The second set of data lines may also include a fourth subset of data lines coupled between the first socket and the second socket and a fifth subset of data lines coupled between the first socket and the third socket. The first and second sets of data lines can make up a memory channel and the memory channel can be a one socket per channel (SPC) memory channel, a <NUM>-SPC memory channel, or a <NUM>-SPC channel when there are three module sockets. Module sockets are also described herein as slots of a motherboard substrate. Thus, sockets and slots are used interchangeably in the description. Also, nibbles as used herein may include four wires of data signals (with one bit on each wire during each bit interval) and two wires of timing signals (with a differential timing event per bit interval). Various embodiments are directed to DIMMS that are greater than <NUM>-bits, such as <NUM>-bit wide DIMMs that support ECC, such as used in server memory systems.

Description of various embodiments herein are described with respect to memory systems with up to three R+ DDR4 LRDIMMs that can be operated at <NUM> DIMMs per channel (DPC) at <NUM>. 2Gb/s using Dynamic Point-Point (DPP) as described herein. Some embodiments do not require change to DRAM devices themselves and a central processing unit (CPU), but may include changes in a module interface and buffer components of the module and changes to a motherboard. The R+ DDR4 LRDIMMs described herein are compatible with the DDR4 LRDIMM standard. The R+ DDR4 LRDIMMs support various error correction coding (ECC) techniques, including single error correcting and, simultaneously, double error detecting (SEC-DED), as well as the ChipKill™ ECC computer memory technology or other advanced ECC computer memory technologies. The embodiments of R+ DDR4 LRDIMMs described herein do not need dynamic on-die termination (ODT) and may have the same or lower power than standard LRDIMMs. The embodiments of R+ LRDIMM architecture, as described herein, may be scale to beyond-DDR4 data rates, e.g., up to <NUM> Gb/s in one embodiment. The embodiments described herein can be used in a memory system where a primary bus can be run at a higher rate and may only be limited by the speed of transfers.

Embodiments of a motherboard are also described herein. In some embodiments, the motherboard can enable <NUM> DPC at maximum data rates. The R+ DDR4 LRDIMMs can also be used in standard motherboards and behave like standard LRDIMMs in those implementation. In other embodiment where interoperability with standard motherboards is not needed, then R+ LRDIMMs can be developed with lower cost than standard LRDIMM as described in more detail below.

Embodiments of memory modules can also be inserted in sockets of a memory system in different configurations. The R+ LRDIMMs may be built from standard memory components. Standard memory controller components (with minimal modifications) and new memory modules may be used in standard memory systems or in new LRDIMM memory systems. The minimal modifications may be that the memory controllers are configured to send appropriate control information given the different configurations. The embodiments of R+ DDR4 LRDIMMs are described as being deployed using DPP. DPP ensures that all data (DQ) nets in a memory channel are always point-to-point, irrespective of the memory configuration (e.g., <NUM>-SPC, <NUM>-SPC, or <NUM>-SPC). Eliminating the multi-drop topology of DQ nets may reduce reflections and other inter-symbol-interference (ISI) effects, thus allowing higher data rates. In some memory configurations, DPP uses one or more continuity DIMMs (CDIMMs). A CDIMM is a printed circuit board (PCB) (e.g., a FR-<NUM> board) with no active or passive components and includes traces that short one set of DQ pins to another set of DQ pins.

<FIG> are diagrams illustrating <NUM>-SPC memory channel wirings for a <NUM> DPC memory configuration <NUM> and a <NUM> DPC memory configuration <NUM>, respectively.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring with <NUM> R+LRDIMM in a <NUM> DPC memory configuration <NUM> according to one embodiment. In the <NUM> DPC memory configuration <NUM>, a first slot <NUM> is populated with a continuity module (C-DIMM) <NUM> and a second slot <NUM> is populated with a R+LRDIMM <NUM>. <FIG> illustrates an <NUM>-bit slice of a <NUM>-bit wide DIMM architecture, including a first nibble received by the R+LRDIMM <NUM> at the second slot <NUM> on data lines <NUM> and a second nibble received by the C-DIMM <NUM> at the first slot <NUM> on data lines <NUM> and routed to the R+LRDIMM <NUM> at the second slot <NUM> on data lines <NUM>.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring with <NUM> R+LRDIMMs in a <NUM> DPC memory configuration <NUM> according to one embodiment. The <NUM>-SPC memory channel wiring is similar in the <NUM> DPC memory configuration <NUM> is similar to the <NUM>-SPC memory channel wiring in the <NUM> DPC memory configuration <NUM> as noted by similar reference labels. In the <NUM> DPC memory configuration <NUM>, the first slot <NUM> is populated with a first R+LRDIMM <NUM> and the second slot <NUM> is populated with a second R+LRDIMM <NUM>. Since both the first slot <NUM> and the second slot <NUM> are populated with R+LDIMMs108, the data lines <NUM> are not used and the first nibble is received by the second R+LRDIMM <NUM> at the second slot <NUM> on data lines <NUM> and the second nibble is received by the first R+LRDIMM <NUM> at the first slot <NUM> on data lines <NUM>. Although one <NUM>-bit slice of the <NUM>-bit wide DIMM is illustrated in <FIG>, the other slices of the <NUM>-bit wide DIMM architecture may be identical. It should also be noted that the embodiments above describe receiving nibbles at the C-DIMM <NUM> and R+LRDIMM <NUM>, but it would be understood that the nibbles can also be sent by the LRDIMM <NUM> to a memory controller on the data lines, some of which would pass through the C-DIMM <NUM>.

<FIG> are diagrams illustrating <NUM>-SPC memory channel wirings for a <NUM> DPC memory configuration <NUM>, a <NUM> DPC memory configuration <NUM>, and a <NUM> DPC memory configuration <NUM>, respectively.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring with <NUM> R+LRDIMM in a <NUM> DPC memory configuration <NUM> according to one embodiment. In the <NUM> DPC memory configuration <NUM>, a first slot <NUM> is populated with a first C-DIMM <NUM>, a second slot <NUM> is populated with a second C-DIMM <NUM>, and a third slot <NUM> is populated with a R+LRDIMM <NUM>. <FIG> illustrates an <NUM>-bit slice of a <NUM>-bit wide DIMM architecture, including: <NUM>) a first nibble received by the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>; <NUM>) a second nibble received by the second C-DIMM <NUM> at the second slot <NUM> on data lines <NUM> and routed to the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>, <NUM>) a third nibble received by the first C-DIMM <NUM> at the first slot <NUM> on data lines <NUM>, routed to the second C-DIMM <NUM> at the second slot <NUM> on data lines <NUM>, and routed to the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>; <NUM>) a fourth nibble received by the first C-DIMM <NUM> at the first slot <NUM> on data lines <NUM> and routed to the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>; <NUM>) a fifth nibble received by the second C-DIMM <NUM> at the second slot <NUM> on data lines <NUM> and routed to the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>; and <NUM>) a sixth nibble received by the R+LRDIMM <NUM> at the third slot <NUM> on data lines <NUM>.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring with <NUM> R+LRDIMMs in a <NUM> DPC memory configuration <NUM> according to one embodiment. The <NUM>-SPC memory channel wiring in the <NUM> DPC memory configuration <NUM> is similar to the <NUM>-SPC memory channel wiring in the <NUM> DPC memory configuration <NUM> as noted by similar reference labels. In the <NUM> DPC memory configuration <NUM>, the first slot <NUM> is populated with a C-DIMM <NUM>, the second slot <NUM> is populated with a first R+LRDIMM <NUM> and the third slot <NUM> is populated with a second R+LRDIMM <NUM>. Since both the second slot <NUM> and the third slot <NUM> are populated with R+LDIMMs <NUM>, the data lines <NUM>, <NUM> and <NUM> are not used, but the data lines <NUM> and <NUM> are still used since the first slot <NUM> is populated with the C-DIMM <NUM>.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring with <NUM> R+LRDIMMs in a <NUM> DPC memory configuration <NUM> according to one embodiment. The <NUM>-SPC memory channel wiring in the <NUM> DPC memory configuration <NUM> is similar to the <NUM>-SPC memory channel wiring in the <NUM> DPC memory configuration <NUM> as noted by similar reference labels. In the <NUM> DPC memory configuration <NUM>, the first slot <NUM> is populated with a first R+LRDIMM <NUM>, the second slot <NUM> is populated with a second R+LRDIMM <NUM> and the third slot <NUM> is populated with a third R+LRDIMM <NUM>. Since the first slot <NUM>, second slot <NUM>, and third slot <NUM> are populated with R+LDIMMs <NUM>, the data lines <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are not used. Although one <NUM>-bit slice of the <NUM>-bit wide DIMM is illustrated in <FIG>, the other slices of the <NUM>-bit wide DIMM architecture may be identical. It should also be noted that the embodiments above describe receiving nibbles at the C-DIMM <NUM> and R+LRDIMM <NUM>, but it would be understood that the nibbles can also be sent by the LRDIMM <NUM> to a memory controller on the data lines, some of which would pass through the C-DIMM <NUM>.

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring <NUM> with a CPU slot <NUM> and two DIMM slots <NUM>, <NUM> for R+LRDIMMs coupled to the CPU slot <NUM> with data lines according to even and odd nibbles according to one embodiment. A first set of data lines <NUM>, corresponding to even nibbles, are connected to the DIMM slots <NUM>, <NUM> and the CPU slot <NUM>. A second set of data lines <NUM>, corresponding to odd nibbles, are connected between the two DIMM slots <NUM>, <NUM>. That is odd nibbles of one DIMM slot is coupled to odd nibbles of the other DIMM slot. The first and second sets of data lines <NUM>, <NUM> can accommodate <NUM> even nibbles and <NUM> odd nibbles for a <NUM>-bit wide DIMM in <NUM> DPC or <NUM> DPC memory configurations, as described below with respect to <FIG>.

<FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with one DIMM slot populated with one R+LRDIMM <NUM> and another DIMM slot populated with a continuity DIMM (C-DIMM) <NUM> according to one embodiment. The R+LRDIMM <NUM> includes eighteen device sites, where each site may be a single memory component or multiple memory components. For ease of description, the data lines of two devices sites <NUM>, <NUM> in the <NUM>-SPC DDR4 channel <NUM> are described. A first device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (even nibble). A second device site <NUM> is coupled to the C-DIMM <NUM> via data lines <NUM> (odd nibble of R+LRDIMM to odd nibble of C-DIMM). The C-DIMM <NUM> use internal traces <NUM> to couple the data lines <NUM> to data lines <NUM>, which are coupled to the CPU <NUM> (odd nibble).

In <FIG>, a DQ buffer component <NUM> is coupled between the first device site <NUM> and second device site <NUM> and the data lines <NUM> and <NUM>, respectively. The DQ buffer component <NUM> acts as a repeater with one R+LRDIMM <NUM> in the <NUM>-SPC DDR4 channel <NUM>. It should be noted that C1[<NUM>:<NUM>] is qualified by CS1# (not illustrated in <FIG>) and C0[<NUM>:<NUM>] is qualified by CS0# (not illustrated in <FIG>).

<FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with one DIMM slot populated with one R+LRDIMM <NUM> and another DIMM slot populated with another one R+LRDIMM <NUM> according to one embodiment. The <NUM>-SPC DDR4 channel <NUM> is similar to the <NUM>-SPC DDR channel <NUM> as noted by similar reference labels. However, the other slot is populated with a second R+LRDIMM <NUM>. The R+LRDIMM <NUM> includes eighteen device sites, where each site may be a single memory component or multiple memory components. For ease of description, the data lines of two devices sites <NUM>, <NUM> in the <NUM>-SPC DDR4 channel <NUM> are described. A first device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (even nibble) as described above with respect to <NUM>-SPC DDR4 channel <NUM>. A second device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (even nibble). In effect, location of the second device site <NUM> of the <NUM>-SPC DDR4 channel <NUM> is swapped with the first device site <NUM> of <NUM>-SPC DDR4 channel <NUM> when both slots are populated with R+LRDIMMs <NUM>, <NUM>. It should be noted that the electrical connections for data lines <NUM> and internal data lines to the DQ buffer components are present on the motherboard and R+LDIMMs, but are not used.

In <FIG>, the DQ buffer component <NUM> acts as a multiplexer (MUX) with two R+LRDIMMs <NUM>, <NUM> in the <NUM>-SPC DDR4 channel <NUM>. It should be noted that C1[<NUM>:<NUM>] is qualified by CS1# (not illustrated in <FIG>) and C0[<NUM>:<NUM>] is qualified by CS0# (not illustrated in <FIG>).

<FIG> is a diagram illustrating <NUM>-SPC memory channel wiring <NUM> with a CPU slot <NUM> and three DIMM slots <NUM>-<NUM> for R+LRDIMMs coupled to the CPU slot <NUM> with data lines according to sets of nibbles according to one embodiment. A first set of data lines <NUM> of the three DIMM slot <NUM>-<NUM> are connected to CPU slot <NUM>. A second set of data lines <NUM> are connected between the second and third DIMM slots <NUM>-<NUM>. A third set of data lines <NUM> are connected between the first and third DIMM slots <NUM>, <NUM>. A fourth set of data lines <NUM> are connected between the first and second DIMM slots <NUM>, <NUM>. The data lines for only one <NUM>-bit wide slice are labeled, but the first, second, third, and fourth sets of data lines can accommodate eighteen nibbles for <NUM> DPC, <NUM> DPC, and <NUM> DPC memory configurations, as described below with respect to <FIG>.

<FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with one DIMM slot populated with one R+LRDIMM <NUM> and two DIMM slots populated with C-DIMMs <NUM> according to one embodiment. A <NUM>-bit slice of a <NUM>-bit wide DIMM is illustrated, but other slices are wired identically. The slice of R+LRDIMM <NUM> includes six device sites, where each site may be a single memory component or multiple memory components. For ease of description, the data lines of three devices sites <NUM>, <NUM>, <NUM> in the <NUM>-SPC DDR4 channel <NUM> are described. A first device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (first nibble). A second device site <NUM> is coupled to the second C-DIMM <NUM> in the second slot via data lines <NUM>, and the inner traces <NUM> of second C-DIMM <NUM> connect data lines <NUM> to data lines <NUM>, which are coupled to the CPU <NUM> (second nibble). A third device site <NUM> is coupled to the first C-DIMM <NUM> in the first slot via data lines <NUM>, and the inner traces <NUM> of first C-DIMM <NUM> connect data lines <NUM> to data lines <NUM>, which are coupled to the CPU <NUM> (third nibble). Similar data lines can be used to connect the other device sites of the R+LRDIMM <NUM> to the CPU <NUM> for the other three nibbles in the slice. The DQ buffer component <NUM>, with or without DQ buffer component <NUM>, can be used for the other device sites of the R+LRDIMM <NUM>.

In <FIG>, a DQ buffer component <NUM> is coupled between the first device site <NUM> and second device site <NUM> and the data lines <NUM> and <NUM>, respectively. A second DQ buffer component <NUM> is coupled between the third device site <NUM> and data lines <NUM>. In another embodiment, the DQ buffer component <NUM> is coupled to the three device sites <NUM>-<NUM> and the third device site <NUM> is coupled to the DQ buffer component <NUM> via data lines <NUM>. Electrical connections may be presented for data lines <NUM> between the first and second C-DIMMS <NUM>, but may be unused. Similarly, electrical connections may be presented for the data lines <NUM>, but may be unused in some embodiments. The DQ buffer component <NUM> acts as a repeater with one R+LRDIMM <NUM> in the <NUM>-SPC DDR4 channel <NUM>. The DQ buffer component <NUM> could also act as multiplexer in some cases. It should be noted that C2[<NUM>:<NUM>], C1[<NUM>:<NUM>] and C0[<NUM>:<NUM>] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated in <FIG>). <FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with two DIMM slots <CIT>.

populated with R+FRDIMMs <NUM>, <NUM> and another DIMM slot populated with a C-DIMM <NUM> according to one embodiment. The <NUM>-SPC DDR4 channel <NUM> is similar to the <NUM>-SPC DDR channel <NUM> as noted by similar reference labels. However, the second slot is populated with a second R+FRDIMM <NUM>. The corresponding slice of the R+FRDIMM <NUM> includes six device sites, where each site may be a single memory component or multiple memory components. For ease of description, the data lines of three devices sites <NUM>-<NUM> in the <NUM>-SPC DDR4 channel <NUM> are described. A first device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (first nibble) as described above with respect to <NUM>-SPC DDR4 channel <NUM>. A second device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (second nibble). A third device site <NUM> is coupled to the CPU via data lines <NUM>, which are coupled to the first slot with the C-DIMM <NUM>. The internal traces of the C-DIMM <NUM> connect the data lines <NUM> to the data lines <NUM> (third nibble). In effect, location of the second device site <NUM> of the <NUM>-SPC DDR4 channel <NUM> is swapped with the first device site <NUM> of <NUM>-SPC DDR4 channel <NUM> when both slots are populated with R+FRDIMMs <NUM>, <NUM>. It should be noted that the electrical connections for data lines <NUM> and internal data lines to the DQ buffer components are present on the motherboard and R+FDIMMs, but are not used. Similar data lines can be used to connect the other device sites of the two R+FRDIMMs <NUM>, <NUM> to the CPU <NUM> for the other three nibbles in the slice. The DQ buffer components <NUM>-<NUM> and DQ buffer components <NUM>-<NUM> may be used for the device sites of the two R+FRDIMMs <NUM>, <NUM>. In some cases, the DQ buffer components may act as repeaters or multiplexers as described herein. It should be noted that C2[<NUM>:<NUM>], Cl[<NUM>:<NUM>] and C0[<NUM>:<NUM>] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated in <FIG>).

<FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with three DIMM slots populated with R+FRDIMMs <NUM>, <NUM>, <NUM> according to one embodiment. The <NUM>-SPC DDR4 channel <NUM> is similar to the <NUM>-SPC DDR channel <NUM> as noted by similar reference labels. However, the first slot is populated with a third R+FRDIMM <NUM>. The corresponding slice of the
R+LRDIMM <NUM> includes six device sites, where each site may be a single memory component or multiple memory components. For ease of description, the data lines of three devices sites <NUM>, <NUM>, <NUM> in the <NUM>-SPC DDR4 channel <NUM> are described. A first device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (first nibble) as described above with respect to <NUM>-SPC DDR4 channel <NUM>. A second device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (second nibble). A third device site <NUM> is coupled to the CPU <NUM> via data lines <NUM> (third nibble). It should be noted that the electrical connections for data lines <NUM>, <NUM> and internal data lines to the DQ buffer components are present on the motherboard and R+LDIMMs, but are not used. Similar data lines can be used to connect the other device sites of the three R+LRDIMMs <NUM>, <NUM>, <NUM> to the CPU <NUM> for the other three nibbles in the slice. The DQ buffer components <NUM>- <NUM>, DQ buffer components <NUM>-<NUM>, and DQ buffer components <NUM>-<NUM> may be used for the device sites of the three R+LRDIMMs <NUM>, <NUM>, <NUM>. In some cases, the DQ buffer components may act as repeaters or multiplexers as described herein. It should be noted that C2[<NUM>:<NUM>], Cl [<NUM>:<NUM>] and C0[<NUM>:<NUM>] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated in <FIG>).

In some implementations, DDR4 R+ LRDIMM requires that all CS# and CKE signals in a memory channel be broadcast to all the DIMM slots (or DIMM sockets or module sockets) in the channel. With DPP, each data signal is connected to only one R+ LRDIMM. In a channel with multiple R+ LRDIMMs, each and every R+ LRDIMM respond s to a Read or Write operation. The DDR4 specification allows up to <NUM> ranks per DIMM slot. In one implementation, for single rank (SR) DIMM, rank <NUM> is controlled by CS0#, CKE0, and ODTO, for double-rank (DR) DIMM, rank <NUM> is controlled by CS1#, CKE1, and ODT1, and for quadrank (OR) DIMM or octa-rank (OR) DIMM, rank is controlled by C[<NUM>:<NUM>], CS#, CKE, and ODT. The CS# signal may be a <NUM>-cycle signal and is connected to only one DIMM slot, and broadcasting CS# to all DIMM slots may violate register setup and hold times. The embodiments described below create a private shared bus between the DIMM slots in a memory channel using pins defined as not connected (NC) or non-functional (NF) in the DDR4 RDIMM specification. ODT pins in each DIMM slot may optionally be used for the private bus since all DQ nets are always point-to-point. CA buffer components (also referred to as CA register) may be modified for operation with a local CS signal (local CS#) and clock enabled (CKE) signals and a distant CS signal (distant CS#) and CKE signals. Local CS signals are signals received directly from the memory controller (MC) and distant signals are signals from another DIMM connector on the private bus. The CA buffer component treats local CS signals different than distant CS signals. For example, in one embodiment, local signals go through two flip-flops before being driven to
the DRAM devices, whereas distant signals go through <NUM> flip-flop before being driven to the DRAM devices.

<FIG> is a diagram illustrating a private bus <NUM> between three DIMM slots <NUM>-<NUM> of a <NUM>-SPC memory system <NUM> according to one embodiment. In the memory system <NUM>, a memory controller (MC) <NUM> is coupled to three slots <NUM>-<NUM>. A first set of control lines <NUM> is coupled between the MC <NUM> and a first slot <NUM> (slot <NUM>) (e.g., CS0#[<NUM>:<NUM>], CKE0, and ODT0). A second set of control lines <NUM> is coupled between the MC <NUM> and a second slot <NUM> (slot1) (e.g., CS1#[<NUM>:<NUM>], CKE1, and ODT1). A third set of control lines <NUM> is coupled between the MC <NUM> and a third slot <NUM> (slot2) (e.g., CS2#[<NUM>:<NUM>], CKE2, and ODT2). For a SR DIMM configuration, rank <NUM> is controlled by CS0#, CKE0, and ODT0. For a DR DIMM configuration, rank <NUM> is controlled by CS0#, CKE0, and ODT0 and rank <NUM> is controlled by CS1#, CKE1, and ODT1. For a QR DIMM configuration or OR DIMM configuration, ranks are controlled by C[<NUM>:<NUM>], CS#, CKE, and ODT. C[<NUM>:<NUM>] may be <NUM> encoded CS signals with each one of CS0# or CS1#. C[<NUM>:<NUM>] may be used to control up to <NUM> ranks (e.g., stacked devices). For stacked technology devices, also referred to as 3DS technology, there may be <NUM> device sites and three C bits can be used to select devices at the selected device site. The CS# signal may be a <NUM>-cycle signal and is connected to only one DIMM slot.

In one embodiment, the R+LRDIMMs at the three slots <NUM>-<NUM> receive three signals each and the R+LRDIMMs retransmit the signals to the other two slots on the private bus <NUM>. The private bus <NUM> includes a first data line <NUM> for CKE_COPY, a second data line <NUM> for CS#_COPY, and a third set of data lines <NUM> for SLOT_ID[<NUM>:<NUM>] and C[<NUM>:<NUM>]_COPY. The SLOT_ID[<NUM>:<NUM>] can be used to identify which of the three slots <NUM>-<NUM> is retransmitting the CS information. C[<NUM>:<NUM>]_COPY is a copy of the CS[<NUM>:<NUM>] received by the respective slot. Similarly, CKE_COPY is a copy of the CKE received by the respective slot and CS#_COPY is a copy of the CS# received by the respective slot. The private bus <NUM> may use wired-OR pins with a pull-up on a motherboard upon which the three slots <NUM>-<NUM> are disposed.

In one embodiment, the following NC pins are available to use for the private bus <NUM>: <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>. In another embodiment, the following NF pins may be used: <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. These NC and NF pins may be in the vicinity of the CA pins.

<FIG> is a diagram illustrating local control signals <NUM> and distant control signals <NUM> of a private bus <NUM> between two DIMM slots <NUM>, <NUM> of a memory system <NUM> according to one embodiment. A first DIMM slot <NUM> (slot <NUM>) is populated with a first memory module with a CA buffer component <NUM> and a second DIMM slot <NUM> (slot <NUM>) is populated with second memory module with a CA buffer component <NUM>. The first memory module in the first DIMM slot <NUM> includes multiple device sites <NUM> and the second memory module in the second DIMM slot <NUM> includes multiple device sites <NUM>. The device sites <NUM>, <NUM> may each include a single memory component or each multiple memory components. These memory components may be DDR4 DRAM devices and the memory modules may be R+LRDIMMs. It should be noted that <FIG> illustrates two single-rank LRDIMMs for sake of clarity, but similar data lines can be connected to other devices sites <NUM> and <NUM>. The CA buffer component <NUM> includes a primary interface with a first pin <NUM>, which is coupled to data line <NUM> to receive a local chip select (CS) signal (CS0#) <NUM>, and a second pin <NUM>, which is coupled to a data line of the private bus <NUM> to receive a distant CS signal (CS COPY#) <NUM>. The primary interface is coupled to the CPU <NUM>. The CA buffer component <NUM> includes a secondary interface to select one or more of the device sites <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>). The CA buffer component <NUM> selects the device sites <NUM>, <NUM> when the local CS signal <NUM> is received on the first pin <NUM> (for slot <NUM>) and selects the device sites <NUM>, <NUM> when the distant CS signal <NUM> is received on the second pin <NUM> (for slot <NUM>). In other embodiments where there are additional slots, the CA buffer component <NUM> receives a second distant CS signal on a third pin (not illustrated) to select other device sites. In a further embodiment, the CA buffer component <NUM> includes: <NUM>) a first flip-flop <NUM> coupled to the first pin <NUM>; <NUM>) a second flip-flop <NUM> coupled to an output of the first flipflop <NUM>. An output of the second flip-flop <NUM> is coupled to the device sites <NUM>, <NUM>. The CA buffer component <NUM> also includes an input buffer coupled to the second pin <NUM> and an output of the input buffer is coupled to a third flip-flop <NUM>. An output of the third flip-flop <NUM> is coupled to the device sites <NUM>, <NUM>. The first flip-flop <NUM>, second flip-flop <NUM>, and third flip-flop <NUM> are clocked by a timing signal <NUM>. The timing signal <NUM> can be generated by a phase locked loop (PLL) <NUM>, which is coupled to a fourth pin <NUM> that receive a clock signal (CLK0) on data line <NUM> from the CPU <NUM>. The CA buffer component <NUM> also includes an output buffer <NUM> coupled to the output of the first flip-flop <NUM>. An output of the output buffer <NUM> is coupled to the second pin <NUM>. The output buffer <NUM> generates a second distant CS signal (e.g., CS COPY#) on second pin <NUM>. The output buffer <NUM> retransmits the local CS signal <NUM> received on the first pin <NUM> as the distant CS signal <NUM> on the second pin <NUM> to one or more other modules in other slots (e.g., second slot <NUM>). The CA buffer component <NUM> may also include similar primary and secondary interfaces as the CA buffer component <NUM>. The primary interface couples to the CPU <NUM> and the secondary interface is to select one or more of the device sites <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>). The CA buffer component <NUM> selects the device sites <NUM>, <NUM> when the local CS signal (CS1#)
is received on a first pin <NUM> (for slot <NUM>) from data line <NUM> coupled to the CPU <NUM>. The CA buffer component <NUM> selects the device sites <NUM>, <NUM> when the distant CS signal (CS_COPY#) is received on the second pin <NUM> (for slot <NUM>) from the data line of the private bus <NUM> coupled to the first slot <NUM>. The CA buffer component <NUM> includes: <NUM>) a first flip-flop <NUM> coupled to the first pin <NUM>; <NUM>) a second flip-flop <NUM> coupled to an output of the first flip-flop <NUM>. An output of the second flip-flop <NUM> is coupled to the device sites <NUM>, <NUM>. The CA buffer component <NUM> also includes an input buffer <NUM> coupled to the second pin <NUM> and an output of the input buffer <NUM> is coupled to a third flip-flop <NUM>. An output of the third flip-flop <NUM> is coupled to the device sites <NUM>, <NUM>. The first flip-flop <NUM>, second flip-flop <NUM>, and third flip-flop <NUM> are clocked by a timing signal <NUM>. The timing signal <NUM> can be generated by a PLL <NUM>, which is coupled to a fourth pin <NUM> that receives a clock signal (CLK1) on data line <NUM> from the CPU <NUM>. The CA buffer component <NUM> also includes an output buffer <NUM> coupled to the output of the first flip-flop <NUM>. An output of the output buffer <NUM> is coupled to the second pin <NUM>. The output buffer <NUM> generates a second distant CS signal (e.g., CS_COPY#) on second pin <NUM>. The output buffer <NUM> retransmits the local CS signal received on the first pin <NUM> as the distant CS signal on the second pin <NUM> to one or more other modules in other slots (e.g., first slot <NUM>).

Although <FIG> illustrates two DIMM slots <NUM>, <NUM> and only four device sites per DIMM slot, in other embodiments, more than two DIMM slots can be used and more than four device sites per DIMM slot may be used. <FIG> also illustrates single-device memory sites, but in other embodiments, multi-device memory sites may be used, such as illustrated in <FIG>.

<FIG> is a diagram illustrating a CA buffer component <NUM> according to one embodiment. The CA buffer component <NUM> includes a first flip-flop <NUM> that receives a local CS signal (CS0#) on a first pin <NUM>. An output of the first flip-flop <NUM> is coupled to an output driver <NUM> to generate a distant CS signal (CS#_COPY) on a second pin <NUM>. A distant CS signal can also be received on second pin <NUM> and an input buffer <NUM> directs the distant CS signal to a multiplexer <NUM>, which also receives the output of the first flip-flop <NUM>. An output of the multiplexer <NUM> is coupled to a second flip-flop <NUM>. An output of the second flip-flop <NUM> is input into CS generation logic <NUM>. The CS generation logic <NUM> also receives input from a DPC counter <NUM> and signals received on the pins <NUM> through an input buffer <NUM> (e.g., CHIP_ID[<NUM>:<NUM>], C[<NUM>:<NUM>]_ COPY). The CS generation logic <NUM> generates CS signals on pins <NUM> (e.g., Q_CS[n:<NUM>]#). A PLL <NUM> receives a clock signal (CK, CK#) on pin <NUM> and generates a timing signal used to clock the first flip-flop <NUM> and the second flip-flop <NUM>. The timing signal is also output on pin <NUM> (e.g., Q_CK, Q_CK#). CS logic <NUM> receives an output of the first flip-flop <NUM> and a SLOT ID from SLOT ID register <NUM>. An output of the CS logic <NUM> enables fourth flip-flops <NUM> that output signals on pins <NUM> (e.g., Q_C[<NUM>:<NUM>]), sixth flip-flops <NUM> that output signals on pins <NUM> (e.g., Q_ODT0, Q_CKE0), and eighth flip-flop <NUM> that output signals on pins <NUM> (e.g., QA[n:<NUM>], QBA[<NUM>:<NUM>], QBG[<NUM>:<NUM>], Q_RAS#, Q_CAS#, Q_WE#). The fourth flip-flop <NUM>, sixth flip-flop <NUM> and eighth flip-flop <NUM> receives outputs from third flip-flop <NUM>, fifth flip-flop <NUM>, and seventh flip-flop <NUM>. These flip-flops are also clocked by the timing signal generated by the PLL <NUM>. The third flip-flop <NUM> receive signals C[<NUM>:<NUM>] on pins <NUM>. The fifth flip-flops <NUM> receive signals a clock signal enable signal (CKEO) and ODT signal (ODT0) on pins <NUM>. The seventh flip-flops <NUM> receive signals (e.g., A[n:O], BA[<NUM>:<NUM>], BG[<NUM>:<NUM>], RAS#, CAS#, WE#) on pins <NUM>. An output of the third flip-flop <NUM> is coupled to a multiplexer <NUM>, which also receives signals received on the pins <NUM> through the input buffer <NUM> (e.g., CHIP_ID[<NUM>:<NUM>], C[<NUM>:<NUM>]_COPY). An output of the multiplexer <NUM> is coupled to an input of the fourth flip-flop <NUM>. An output of the fifth flip-flop <NUM> is coupled to an output buffer <NUM> to drive copies of the clock enable signal and ODT signal on pins <NUM> (e.g., CKE_COPY). An output of the third flip-flop <NUM> is coupled to an output buffer <NUM> to drive copes of the signals on pins <NUM> (e.g., CHIP_ID[<NUM>:<NUM>], C[<NUM>:<NUM>]_ COPY).

In some implementations, some logic blocks can be bypassed when the CA buffer component <NUM> is operating as a standard DDR4 CA buffer component. The bypass path is not illustrated in <FIG>. It should be noted that clock enable logic (CKEO logic) is similar to the CS logic for CS0# logic, but is not shown for sake of clarity. In a further embodiment, the CA buffer component <NUM> sends configuration information and multiplexer control signals to DQ buffers on existing sideband signals as described herein.

<FIG> is a diagram illustrating a data (DQ) buffer component <NUM> according to one embodiment. The DQ buffer component <NUM> includes a multiplexer <NUM>, control logic <NUM> and a synchronizer <NUM>. The multiplexer <NUM> is coupled to multiple input ports: IN_PORTA, IN_PORTB, and IN_PORTC. The multiplexer <NUM> receives a first nibble, including data signals S_ DQ[<NUM>:<NUM>] and timing signals S_DQS0 and S_DQS0#. It should be noted that nibble, as used herein, refers to the data signals and the corresponding timing signals, and thus, is <NUM>-bits. The multiplexer <NUM> receives a second nibble, including data signals S_DQ[<NUM>:<NUM>] and timing signals S_DQS1 and S_DQSl#. In a further embodiment, the multiplexer <NUM> receives a third nibble, including S_DQ811:<NUM>] and timing signals S_DQS2 and S_DQS2#. The third port can be used for <NUM> SPC configurations, but these pins may not be needed for <NUM> SPC configurations. It should be noted that the multiplexer <NUM> is a bi-directional multiplexer, such as a <NUM>:<NUM> mux and <NUM>:<NUM> demux.

As described above, sideband signals <NUM> can be generated by the CA buffer component <NUM> of <FIG>. Control logic <NUM> receives the sideband signals <NUM> to control the multiplexer <NUM> and the synchronizer <NUM>. The synchronizer <NUM> synchronizes the data to be output on first and second ports (OUT_PORTA, OUT_PORTB). For example, the synchronizer <NUM> can output data signals (e.g., P_DQ[<NUM>:<NUM>]) and timing signals <NUM> (e.g., P_DQS0 and P_DQS0#) on first port and can output data signals (e.g., P_DQ[<NUM>:<NUM>]) and timing signals <NUM> (e.g., P_DQS1 and P_CDQ1#) on the second port.

<FIG> is a diagram illustrating data flow in a <NUM>-SPC system <NUM> when populated with one R+LRDIMM in a <NUM> DPC configuration <NUM> and when populated with two R+LRDIMMs in a <NUM> DPC configuration <NUM> according to one embodiment. The <NUM>-SPC system <NUM> includes a first slot <NUM> (slot <NUM>) and a second slot <NUM> (slot <NUM>). An <NUM>-bit slice of a <NUM>-bit wide DIMM is illustrated in <FIG>, but the other slices are identical. A first set of data lines <NUM> is disposed on a motherboard substrate and coupled to the first slot <NUM> and second slot <NUM> and a memory controller (not illustrated). The first set <NUM> of data lines includes point-to-point data lines, each point-to-point data line of the first set <NUM> is coupled to the memory controller and either one of the slots, but not both slots (also referred to herein as module sockets). The first set <NUM> of data lines is greater than <NUM> data lines. The first set <NUM> of data lines may be <NUM> bits to support ECC as described herein. A second set <NUM> of data lines is disposed on the motherboard substrate and coupled between the first slot <NUM> and second slot <NUM>. The CS signals <NUM> are received at the first slot <NUM> and second slot <NUM>.

In the <NUM> DPC configuration <NUM>, the first slot <NUM> is populated with a C-DIMM <NUM> and the second slot <NUM> is populated with a R+LRDIMM <NUM>. Data flows to and from a first memory site <NUM> of the R+LRDIMM <NUM> along a first data path <NUM> (first nibble) and data flows to and from a second memory site <NUM> of the R+LRDIMM <NUM> along a second path <NUM> through the C-DIMM <NUM> (second nibble). As described herein, the first and second nibbles may include <NUM>-bits of data signals and two timing/clock signals.

In the <NUM> DPC configuration <NUM>, the first slot <NUM> is populated with a first R+LRDIMM <NUM> and the second slot <NUM> is populated with a second R+LRDIMM <NUM>. Data flows to and from a first memory site <NUM> of the second R+LRDIMM <NUM> along a first data path <NUM> (first nibble) and data flows to and from a first memory site <NUM> of the first R+LRDIMM <NUM> along a second path <NUM>. In this <NUM> DPC configuration, the second set of data lines <NUM> are not used and are considered inactive. As described herein, the first and second nibbles may include <NUM>-bits of data signals and two timing/clock signals.

<FIG> is a diagram illustrating chip select (CS) generation in a <NUM>-SPC system <NUM> when populated with one R+LRDIMM in a <NUM> DPC configuration <NUM> and when populated with two R+LRDIMMs in a <NUM> DPC configuration <NUM> according to one embodiment. In the <NUM> DPC configuration <NUM>, a first slot is populated with a C-DIMM <NUM> and a second slot is populated with a R+LRDIMM <NUM>. The R+LRDIMM <NUM> includes a DQ buffer component <NUM> and CA buffer component <NUM>. The CA buffer component <NUM> receives CS information on a primary interface and sends CS information on a secondary interface to select one of the device sites <NUM>, <NUM>. In this configuration, two DRAMS are mapped to a single rank. Alternatively, other configurations may be used.

In the <NUM> DPC configuration <NUM>, the first slot is populated with a second R+LRDIMM <NUM> and the second slot is populated with a first R+LRDIMM <NUM>. The first R+LRDIMM <NUM> includes the DQ buffer component <NUM> and CA buffer component <NUM>. The second R+LRDIMM <NUM> includes a DQ buffer component <NUM> and CA buffer component <NUM>. The CA buffer components <NUM>, <NUM> receive CS information on respective primary interfaces and send CS information on respective secondary interfaces to select the device sites <NUM>, <NUM> and <NUM>, <NUM>, respectively. In this configuration, two DRAMS are mapped to two different ranks (CS#<NUM>, CS0#). Alternatively, other configurations may be used. It should also be noted that <FIG> illustrates one <NUM>-bit slice of a <NUM>-bit wide DIMM, but other slices are identical.

<FIG> is a diagram illustrating CS generation in a <NUM>-SPC system when populated with one R+LRDIMM in a <NUM> DPC configuration <NUM>, when populated with two R+LRDIMMs in a <NUM> DPC configuration <NUM>, and when populated with three R+LRDIMMs in a <NUM> DPC configuration <NUM> according to one embodiment. <FIG> illustrates only one R+LRDIMM <NUM> in the <NUM> DPC, <NUM> DPC, and <NUM> DPC configurations1310, <NUM>, <NUM>. The R+LRDIMM <NUM> includes a CA buffer component <NUM> and three DQ buffer components <NUM> in the <NUM> DPC and <NUM> DPC configurations <NUM>, <NUM>. The R+LRDIMM <NUM> includes a CA buffer component <NUM> and two DQ buffer components <NUM> in the <NUM> DPC configuration <NUM>. In <NUM> DPC configuration <NUM> six DRAM devices are mapped to a single rank. In <NUM> DPC configuration <NUM> six DRAM devices <NUM> are mapped to two ranks (CS2# & CS1#). In <NUM> DPC configuration <NUM> six DRAM devices are mapped to three ranks (CS2#, CS1#, and CSO#) rank. Alternatively, the device sites of the six DRAM devices <NUM> can be device sites with multiple DRAM devices such as in stacked technologies.

The CA buffer component <NUM> receives CS information on a primary interface and sends CS information on a secondary interface to select the appropriate DRAM device <NUM>. In this embodiment, all DRAM devices share common C[<NUM>:<NUM>] bus. In embodiments with multiple devices at a device site, additional CS information may be received on the primary interface to select the appropriate device at the selected device site. It should also be noted that <FIG> illustrates one <NUM>-bit slice of a <NUM>-bit wide DIMM, but other slices are identical.

<FIG> is a diagram illustrating a R+DDR4 DRAM <NUM> according to one embodiment. The R+DDR4 DRAM <NUM> includes an array <NUM>, a data path <NUM> coupled to the array <NUM>, and a command decoder <NUM> coupled to the array <NUM> and the data path <NUM>. A primary port <NUM> is coupled to a secondary port <NUM>, which is coupled to the data path <NUM>. The R+DDR4 DRAM <NUM> also includes a delay locked loop (DLL) <NUM>. The array <NUM> may also refer to a local stack at a device site, such as in a 3DS structure. The data path <NUM> may include a read first-in-first-out (FIFO) buffer, a write deserializer, and a latency counter. The command decoder <NUM> receives CA signals <NUM> from a CA buffer component (not illustrated) to control the array <NUM> and data path <NUM>. In some cases, data (DQ_P) is directed by the data path <NUM> to or from the array <NUM> through the primary port <NUM> and secondary port <NUM>. In other cases, data (DQ_S) is directed by the data path <NUM> to or from the array <NUM> through the secondary port <NUM>. The primary port <NUM> and secondary port <NUM> are coupled to a DQ buffer component (not illustrated). In other scenarios, the primary port <NUM> may be coupled to one DQ buffer component (not illustrated) and the secondary port <NUM> may be coupled to another DQ buffer component (not illustrated).

In one embodiment, the R+ DDR4 DRAM is x4 DDR4 DRAM or DDR4 3DS DRAM with dual x4 ports. The primary port <NUM> maps to the DQ[<NUM>:<NUM>] nibble in a x4 DRAM and the secondary port <NUM> maps to the unused DQ[<NUM>:<NUM>] nibble in a x4 DRAM. The R+ DDR4 DRAM can be configured through a <NUM>-bit configuration register, according to the following: 'b00: DRAM transmits and receives on the primary (DQ[<NUM>:<NUM>]) port; 'b01: DRAM transmits and receives on the secondary (DQ[<NUM>:<NUM>]) port; 'b10: DRAM MUX's primary port to either the internal core (or local 3DS stack) or the secondary port based on an external sideband signal; and 'b11: RFU (reserved for future use). As described herein, the DRAM configuration depends on a number of DIMM slots populated in a memory channel.

<FIG> is a diagram illustrating a <NUM>-SPC DDR4 channel <NUM> with one DIMM slot populated with one low-cost R+LRDIMM <NUM> and another DIMM slot populated with a C-DIMM <NUM> according to one embodiment. The low-cost R+LRDIMM <NUM> is considered low-cost in that it does not include the DQ buffer components present in the R+LRDIMMs described above. All DRAM devices (e.g., <NUM>, <NUM>) of low-cost R+LRDIMM <NUM> are configured to transmit and receive on DQ[<NUM>:<NUM>] port ('b00). The low-cost R+LRDIMM <NUM> includes <NUM> bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices <NUM>, <NUM>. The DRAM device <NUM> is coupled to a CPU <NUM> via a first set of data lines <NUM> (first nibble). The second DRAM device <NUM> is coupled to the CPU <NUM> via a second set of data lines <NUM>, and inner traces <NUM> of C-DIMM <NUM> connect data lines <NUM> to data lines <NUM>, which are coupled to the CPU <NUM> (second nibble). Although only two DRAM devices <NUM>, <NUM> are described, similar sets of data lines can be used to connect the other sixteen DRAM devices to the CPU <NUM> when the <NUM>-SPC DDR4 channel <NUM> is populated with one low-cost R+LRDIMM <NUM>. In this configuration, data lines <NUM> between the first DRAM device <NUM> and second DRAM device <NUM> are unused (inactive). In one implementation, JEDEC standard DDR4 LRDIMM has ten buffer components (<NUM> chips) to address SI limitations of multi-drop topology, including one CA buffer components (also referred to as C/A register (RCD)) and nine DQ buffered components (also referred to as DBs). This <NUM>-chip solution has significant cost premium over RDIMM. The low-cost DDR4 R+LRDIMM <NUM> uses DPP technology to ensure that all DQ signals are always point-to-point and there are no multi-drop DQ nets. Since all DQ signals are point-to-point, RCD and DBs can be combined into a single integrated circuit (IC) (or "single chip"). The single chip solution provides cost savings and power savings over a <NUM>-chip solution, reducing cost premium of LRDIMM over RDIMM. The low-cost DDR4 R+LRDIMM <NUM> can be buffer-less in that the low-cost DDR4 R+LRDIMM <NUM> can implement the buffer function in an R+DDR DRAM device. This cost reduction may fit well with 3DS structures that are supported in the DDR4 specification. 3DS master-slave architecture presents a single electrical load on the channel irrespective of a number of ranks in the DIMM. The changes to the CA buffer component, as described herein, to support R+LRDIMM may also enable low-cost R+LRDIMM. That is, the same CA buffer component can be used for R+LRDIMM and low-cost R+LRDIMM. For example, the steering logic on a master device can be presented and not enabled.

<FIG> is a diagram illustrating <NUM>-SPC DDR4 channel <NUM> with two DIMM slots populated with low-cost R+LRDIMMs <NUM>, <NUM> according to one embodiment. The low-cost R+LRDIMMs <NUM>, <NUM> are considered low-cost in that they do not include the DQ buffer components present in the R+LRDIMMs described above. Some of DRAM devices (e.g., <NUM>, <NUM>) of low-cost R+LRDIMMs <NUM>, <NUM> are configured to transmit and receive on DQ[<NUM>:<NUM>] port ('b01) and others DRAM devices (e.g., <NUM>, <NUM>) are configured as multiplexers (port 'b10) and transmit and receive on DQ[<NUM>:<NUM>] port. The low-cost R+LRDIMM <NUM> includes <NUM> bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices <NUM>, <NUM>. The low-cost R+LRDIMM <NUM> also includes <NUM> bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices <NUM>, 1564and. The DRAM device <NUM> is coupled to a CPU <NUM> via the first set of data lines <NUM> (first nibble). The DRAM device <NUM> is coupled to the CPU <NUM> via data lines <NUM>. The second DRAM device <NUM> is coupled to the first DRAM device <NUM> via data lines <NUM>. The second DRAM device <NUM> is coupled to the first DRAM device <NUM> via data lines <NUM>. Although only two DRAM devices (<NUM>, <NUM> or <NUM>, <NUM>) are described, similar sets of data lines can be used to connect the other sixteen DRAM devices to the CPU <NUM> when the <NUM>-SPC DDR4 channel <NUM> is populated with two low-cost R+LRDIMMs <NUM>, <NUM>. In this configuration, data lines <NUM> between the first and second slots are unused (inactive).

In the <NUM>-SPC DDR4 channel <NUM>, the data lines <NUM> and <NUM> are considered a primary channel and the data lines <NUM> and <NUM> are considered a secondary channel. Simulations have shown that the primary channel and the secondary channel can both operate at <NUM>. In some embodiments, the private bus, as described above, can operate at <NUM> Gb/s, the CA bus can operate at <NUM> Gb/s, and the DQ bus can operate at <NUM> Gb/s for a DDR4 <NUM> SPC memory system. In further embodiments, the R+LRDIMM architecture can scale to rates beyond DDR4 data rates. For example, In one embodiment, the private bus can operate at <NUM> Gb/s, the CA bus can operate at <NUM> Gb/s, and the DQ bus can operate at <NUM> Gb/s for a beyond-DDR4 <NUM> SPC memory system. These data rates can be achieved in <NUM>-bit wide DIMMs as described herein. Alternatively, other width DIMMs can utilize the technologies descried herein.

The beyond-DDR4 DRAM devices can be used in various memory systems, as illustrated in <FIG>. The_beyond-DDR4 DRAM devices can be used for tablets, PCs, and servers. The data rates for the DQ buses may be in a range between <NUM> Gb/s to <NUM> Gb/s data rates with low voltage swing terminated logic (LVSTL), single-ended signaling. Multi-rank and multi-DIMM cycle redundancy check (CRC) may ensure integrity of data transmission. The beyond-DDR4 DRAM devices can have higher power efficiency than DDR4 DRAM devices, such as greater than <NUM>%. For example, there may be zero DRAM input-output (I/O) power dissipation at all times except during CAS operation. In addition, an asymmetric design of the beyond-DDR4 DRAM device may ensure lower DRAM cost and higher DRAM yield. DLL and other complex timing circuits may be moved to the memory controller. As illustrated and described below with respect to <FIG>=16E. For example, unregister DIMM (UDIMM), registered DIMM (RDIMM), LRDIMM, and motherboard configurations can be used to achieve full capacity expansion, <NUM> DPC or <NUM> DPC) at a maximum data rate (e.g., <NUM> Gb/s or <NUM> Gb/s). The beyond-DDR4 DRAM device also reuses existing infrastructure of the DDR4 DRAM device. This may allow the use of standard connectors, memory modules, IC packages, PCBs, or the like.

As described herein, the DPP may permit the memory bus to operate at data rates beyond DDR4 data rates. to operate memory bus at beyond DDR4 data rates. Even with LRDIMM, multi-drop topology limits bus speed to less than 3Gb/s for <NUM> DPC. The proposed DPP implementations fit well within the "beyond-DDR4" DRAM devices being developed. The CA bus may operate at <NUM> Gb/s and the private bus can be implemented with <NUM>-clock added latency if no CPU support. The beyond-DDR4 data rates depend on memory channel configuration. For example, <NUM>. 8Gb/s data rates can be demonstrated under WC conditions with <NUM> CDIMM (i.e. partially loaded channel) and <NUM>. 4Gb/s data rates can be demonstrated under WC conditions with no CDIMMs (i.e. fully loaded channel).

<FIG> is a diagram illustrating a tablet memory configuration <NUM> with a system on chip (SoC) <NUM> and four beyond-DDR4 DRAM devices <NUM> according to one embodiment. A CA bus <NUM> can operate at <NUM> Gb/s to control the four beyond-DDR4 DRAM devices <NUM> and a DQ bus <NUM> between the SoC <NUM> and the four beyond-DDR4 DRAM devices <NUM> can operate at <NUM> Gb/s. This is 2X data rate of DDR4 devices and lower power than DDR4 devices. The tablet memory configuration <NUM> may be used in a tablet device. Alternatively, the tablet memory configuration <NUM> can be used in other portable electronic devices.

<FIG> is a diagram illustrating a personal computer (PC) memory configuration <NUM> with a CPU <NUM> and two memory channels <NUM>, <NUM> to two DIMM slots <NUM>, <NUM>, populated with beyond-DDR4 DRAM devices according to one embodiment. A first memory channel <NUM> is coupled between the first DIMM slot <NUM> (e.g., UDIMM/SODIMM) and includes a CA bus <NUM> that operates at <NUM> Gb/s and DQ bus <NUM> that operates at <NUM> Gb/x. A second memory channel <NUM> is coupled between the second DIMM slot <NUM> (e.g., UDIMM/SODIMM) and includes a CA bus <NUM> that operates at <NUM> Gb/s and DQ bus <NUM> that operates at <NUM> Gb/x. This is 2X data rate of DDR4 devices and lower power than DDR4 devices. The PC memory configuration <NUM> may be used in a PC. Alternatively, the PC memory configuration <NUM> can be used in other electronic devices with a CPU and one or more DIMMs.

<FIG> is a diagram illustrating a first server memory configuration <NUM> with a CPU <NUM><NUM> and a <NUM>-SPC memory channel <NUM> with one DIMM slot <NUM> (e.g., ECC UDIMM) populated with one or more beyond-DDR4 R+LRDIMMs according to one embodiment. The memory channel <NUM> is coupled between the DIMM slot <NUM> (e.g., ECC UDIMM) and includes a CA bus <NUM> that operates at <NUM> Gb/s and DQ bus <NUM> that operates at <NUM> Gb/s. This is 2X data rate of DDR4 devices and lower power than DDR4 devices.

<FIG> is a diagram illustrating a second server memory configuration <NUM> with a CPU <NUM> and a <NUM>-SPC memory channel <NUM> with two DIMM slots <NUM>, <NUM>, populated with one or two R+LRDIMMs with beyond-DDR4 DRAM devices according to one embodiment. The memory channel <NUM> is coupled between a first DIMM slot1664 (e.g., LRDIMM) and a second DIMM slot <NUM> (e.g., RDIMM/LRDIMM). The memory channel <NUM> includes a CA bus <NUM> that operates at <NUM> Gb/s. The CA bus <NUM> may be a multi-drop bus. The memory channel <NUM> also includes a first portion <NUM> of a DQ bus between the CPU <NUM> and the first slot <NUM> that operates at <NUM> Gb/s and a second portion <NUM> of the DQ bus between the CPU <NUM> and the second slot <NUM> that operates at <NUM> Gb/s. Ranks <NUM>-<NUM> may operate at <NUM>. 5X data rate of DDR4 and <NUM> ranks may operate at 2X data rate of DDR4.

<FIG> is a diagram illustrating a third server memory configuration <NUM> with a CPU and a <NUM>-SPC memory channel <NUM> with three DIMM slots populated with one, two or three R+LRDIMMs with beyond-DDR4 DRAM devices according to one embodiment. The memory channel <NUM> is coupled between a first DIMM slot <NUM> (e.g., LRDIMM), a second DIMM slot <NUM> (e.g., LRDIMM), and a third DIMM slot <NUM> (e.g., RDIMM/LRDIMM). The memory channel <NUM> includes a CA bus <NUM> that operates at <NUM> Gb/s. The CA bus <NUM> may be a multi-drop bus. The memory channel <NUM> also includes a DQ bus that operates at <NUM> Gb/s. The DQ bus may include a first portion <NUM> between the CPU <NUM> and the first DIMM slot <NUM>, a second portion <NUM> between the CPU <NUM> and the second DIMM slot <NUM>, and a third portion <NUM> between the CPU <NUM> and the third DIMM slot <NUM>. Ranks <NUM>-<NUM> may operate at <NUM>. 5X data rate of DDR4 and <NUM> ranks may operate at 2X data rate of DDR4. Alternatively, other server memory configurations are possible using the R+LRDIMMs and low-cost R+LRDIMMs described herein.

The embodiments described herein may also be compatible with standard error detection and correction (EDC) codes. This includes standard (Hamming) ECC bit codes and standard "Chip-kill" symbol codes. In fact, in some configurations, the embodiments can correct for the complete failure of a module. In some embodiments, the device sites include at least one of a single memory die, a package stack of at least two memory dies, or a die stack of at least two memory dies. In other embodiments, a memory system includes a memory controller, a motherboard substrate with at least three module sockets (or slots). At least one of the at least three memory modules socket is populated with a memory module including multiple memory components and a command and address (CA) buffer component. The memory system further includes a first set of data lines coupled between the memory controller and the at least three module sockets; and a second set of data lines coupled between the two module sockets. The module sockets may be dual in-line memory modules (DIMM) sockets.

In another embodiment, a memory module includes multiple module connector pins; multiple device sites; and a CA buffer component. The CA buffer component is configured to: receive chip select information on a primary set of CS lines coupled between the module connector pins and the CA buffer component; and send the CS information on a private bus to other modules in other module sockets as described herein. The CS information selects one of multiple ranks.

In other embodiments, the memory module further includes a second set of multiple module connector pins; a DQ buffer component; a third set of data lines coupled between the second multiple module connector pins and the DQ buffer component; and a fourth set of data lines coupled between the DQ buffer component and the multiple device sites. The memory module may include a second DQ buffer component and a third DQ buffer component. Each of the multiple ranks includes at least three device sites. These device sites may contain at least one of a single memory device, a package stack of at least two memory devices, or a die stack of at least two memory devices.

In other embodiments, a memory module includes multiple module connector pins; multiple device sites; and a CA buffer component. The CA buffer component includes a primary CA interface connected to a memory channel and a secondary CA interface connected to the multiple device sites. The CA buffer component is further configured to receive a first set of one-hot chip select control signals on the primary CA interface, and pass the one-hot chip select signals to the private bus to the other module sockets. The CA buffer components selects one memory device at each of the multiple device sites to perform a first command specified on other lines of the CA interface.

In another embodiment, the memory module further includes multiple data-link buffer devices. The memory module is configured to operate in a first mode of operation or a second mode of operation. In the first mode of operation, the memory module is inserted onto a first type of memory channel with multi-drop data links shared with at least one other memory module. In the second mode of operation, the memory module is inserted onto a second type of memory channel with point-to-point data links that do not share with the at least one other memory module as described herein.

In another embodiment, a motherboard substrate includes at least three module sockets (or slots). At least one of the at least three memory modules socket is populated with a memory module. The memory module includes multiple device sites coupled to a DQ buffer component via data lines and coupled to a CA buffer component via CS lines. There are two classes of links: the CA (control-address) links and the DQ (data) links. These signals are transmitted (and received, in the case of DQ links) by a memory controller component (also referred to herein as a memory controller but can be other components that control access to the memory modules). These signals are typically received (and transmitted, in the case of DQ links) by buffer components on a module, such as a CA buffer component and one or more DQ buffer components. Various embodiments discussed in present application are directed to memory modules with seventy-two data links (<NUM> DQ links) to accommodate standard ECC codes. The technologies described in the present embodiments can be applied to memory modules with other number of data links as well, such as sixty-four DQ links.

The embodiments disclosed in this disclosure can be employed to gain a number of important benefits. For example, the signaling integrity of the DQ links may be improved significantly from the multi-drop topology of standard systems: each DQ link uses a point-to-point topology. High capacity systems described herein may allow standard error detection and correction codes (i.e. ECC, Chip-kill); in addition, in some configurations it is possible to correct for the complete failure of a module. These improvements may be achieved while maintaining a high degree of compatibility to standard memory systems and their components. For example, there may be no changes to the memory components, modest changes or no changes to the memory controller component. There may be changes to the module and the motherboard wiring as described herein. However, the modules described herein may be compatible with standard systems, as well as high-capacity systems. By offering a standard mode and an improved mode of operation, the manufacturer of the controller component and the buffer component can deliver the same product into both standard motherboards and improved, high capacity motherboards, for example.

<FIG> is a diagram of one embodiment of a computer system <NUM>, including main memory <NUM> with three memory modules <NUM> according to one embodiment. The computer system <NUM> may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The computer system <NUM> can be a host in a cloud, a cloud provider system, a cloud controller, a server, a client, or any other machine. The computer system <NUM> can operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a console device or set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The computer system <NUM> includes a processing device <NUM> (e.g., host processor or processing device), a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), a storage memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory <NUM> (e.g., a data storage device in the form of a drive unit, which may include fixed or removable computer-readable storage medium), which communicate with each other via a bus <NUM>. The main memory <NUM> includes one, two or three memory modules <NUM> (e.g., R+LRDIMMS) that are described in various embodiments herein.

Processing device <NUM> represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device <NUM> may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processing device <NUM> includes a memory controller <NUM> as described above. The memory controller <NUM> is a digital circuit that manages the flow of data going to and from the main memory <NUM>. The memory controller <NUM> can be a separate integrated circuit, but can also be implemented on the die of a microprocessor. The memory controller <NUM> may the memory controller described in various embodiments described herein.

In one embodiment, the processing device <NUM> may reside on a first integrated circuit and the main memory <NUM> may reside on a second integrated circuit. For example, the integrated circuit may include a host computer (e.g., CPU having one more processing cores, L1 caches, L2 caches, or the like), a host controller or other types of processing devices <NUM>. The second integrated circuit may include a memory device coupled to the host device, and whose primary functionality is dependent upon the host device, and can therefore be considered as expanding the host device's capabilities, while not forming part of the host device's core architecture. The memory device may be capable of communicating with the host device via a DQ bus and a CA bus. For example, the memory device may be a single chip or a multi-chip module including any combination of single chip devices on a common integrated circuit substrate. The components of <FIG> can reside on "a common carrier substrate," such as, for example, an integrated circuit ("IC") die substrate, a multi-chip module substrate or the like. Alternatively, the memory device may reside on one or more printed circuit boards, such as, for example, a mother board, a daughter board or other type of circuit card. In other implementations, the main memory and processing device <NUM> can reside on the same or different carrier substrates.

The computer system <NUM> may include a chipset <NUM>, which refers to a group of integrated circuits, or chips, that are designed to work with the processing device <NUM> and controls communications between the processing device <NUM> and external devices. For example, the chipset <NUM> may be a set of chips on a motherboard that links the processing device <NUM> to very high-speed devices, such as main memory <NUM> and graphic controllers, as well as linking the processing device to lower-speed peripheral buses of peripherals <NUM>, such as USB, PCI or ISA buses.

The computer system <NUM> may further include a network interface device <NUM>. The computer system <NUM> also may include a video display unit (e.g., a liquid crystal display (LCD)) connected to the computer system through a graphics port and graphics chipset, an alphanumeric input device (e.g., a keyboard), a cursor control device (e.g., a mouse), and a signal generation device (e.g., a speaker).

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention.

For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments.

Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links.

Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments.

Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented.

With respect to terminology, a signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition.

Conversely, a signal is said to be "de-asserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition).

A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits.

A signal line is said to be "activated" when a signal is asserted on the signal line, and "deactivated" when the signal is de-asserted.

Additionally, the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state).

A line over a signal name (e.g., ' ') is also used to indicate an active low signal. The term "coupled" is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures.

Integrated circuit device "programming" may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term "exemplary" is used to express an example, not a preference or requirement.

While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

In the above description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that embodiments of the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the description.

Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. An algorithm is here and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like.

Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "encrypting," "decrypting," "storing," "providing," "deriving," "obtaining," "receiving," "authenticating," "deleting," "executing," "requesting," "communicating," or the like, refer to the actions and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

The words "example" or "exemplary" are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as "example' or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this disclosure, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or. " That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this disclosure and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an embodiment" or "one embodiment" or "an implementation" or "one implementation" throughout is not intended to mean the same embodiment or implementation unless described as such.

Embodiments descried herein may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, flash memory, or any type of media suitable for storing electronic instructions. The term "computer-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and/or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term "computer-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.

Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present embodiments are not described with reference to any particular programming language.

The above description sets forth numerous specific details such as examples of specific systems, components, methods and so forth, in order to provide a good understanding of several embodiments of the present invention. It will be apparent to one skilled in the art, however, that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth above are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present invention.

Claim 1:
A memory module comprising:
a data (DQ) buffer (<NUM>) component;
a plurality of device sites coupled to the DQ buffer component; and
a command and address, CA, buffer component (<NUM>, <NUM>, <NUM>), wherein the command and address (CA) buffer component comprises:
a primary interface comprising
a first pin (<NUM>) to receive a local chip select, CS, signal (<NUM>) from the memory controller and
a second pin (<NUM>) to receive a distant CS signal (<NUM>) from another memory module; and
a secondary interface to select a first set of one or more of the plurality of device sites, wherein each of the plurality of device sites comprises at least one of a single memory die, when the local CS signal is received on the first pin or a second set of one or more of the plurality of device sites (<NUM>) when the distant CS signal (<NUM>) is received on the second pin (<NUM>),
wherein the CA buffer component (<NUM>, <NUM>, <NUM>) is configured to retransmit the local CS signal (<NUM>, CSO#) received on the first pin (<NUM>) as a distant CS signal (<NUM>, CS_COPY#) on the second pin (<NUM>) to the another memory module .