Patent Description:
Nonvolatile (NV) memory devices have limited write endurance. NV memory refers to a memory whose state is indeterminate if power to the device is interrupted. Write endurance refers to the number of times the media can be written before becoming unreliable. Additionally, the media is subject to write disturb, which is a condition where repeated access to a target memory address results in an unintended changing of the value at a victim address of an adjacent location.

With potential issues related to the number of writes, systems keep track of number of writes to determine how often to refresh the data and move data to manage cell endurance and write disturb. A traditional approach for tracking the writes is to track the writes per block. Each time data is written to a block, the system accesses the write count to increment it. In a system where the write count is stored in the nonvolatile media itself, the access requires a read of the data before the block is written. Traditionally the media controller reads the data and increments it to be written back to the media with the user data. The operation reduces the effective write bandwidth of the system. <CIT> describes a nonvolatile memory device that includes a memory cell array including a plurality of memory cells and a data comparison write unit connected with the memory cell array and configured to support a comparison write operation. The nonvolatile memory device further includes control logic configured to selectively execute the comparison write operation based on a comparison between an access number of the memory cell array and a reference number. <NPL>, considers implementing a NVM Phase Change Memory (NVM-PCM) as secondary memory in order to build a future PCM-SSD (PSSD) to replace slow traditional FSSD. It is proposed to implement ExTENDS, a hardware assumption of NVM-PCM, instead of the NVM-flash memory as secondary/persistent memory in storage systems. Further a PCM file translation layer (PhaseFTL) is presented that can efficiently manage address translations from a host file system to PCM while hiding PCM constraints and allowing the PCM blocks to wear down evenly. PhaseFTL can efficiently manipulate the bit-addressability and in-place-update feature of PCM.

The present invention relates to a non-volatile memory device as defined in independent device claim <NUM> and a method for storing data as defined in independent method claim <NUM>. In the following description, only embodiments, examples, implementations, illustrations comprising all the technical features of independent claim <NUM> or of independent claim <NUM> fall under the scope of protection of the present invention.

The following description includes discussion of figures having illustrations given by way of example of an implementation. The drawings should be understood by way of example, and not by way of limitation. As used herein, references to one or more examples are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention, and do not necessarily all refer to the same implementation. However, they are also not necessarily mutually exclusive.

Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all examples, and well as other potential implementations.

As described herein, a system can keep track of the number of writes for a nonvolatile (NV) memory by storing metadata in one of multiple NV memory arrays. In one example, the NV memory is a memory device with three-dimensional crosspoint (3DXP) storage media. The NV memory arrays collectively store a block of data, with each array to store a portion of the data block and a selected array to store a write count for the block of data. The system can use the write count to determine how often to refresh data or move data to manage cell endurance and write disturb.

The write procedure for certain NV memory technologies takes a relatively long time and uses a lot of power. To manage energy usage and write delay, the NV memory writes only bits that are changed for a write. The NV memory issues a read operation internally in response to a write command. The internal read can be referred to as a "pre-read" or a "pre-write read," which allows the memory device to read the contents of its memory cells, compare the existing data to the incoming data, and only write the bits that are being changed.

The selected NV memory array that stores the write count will perform an internal read of its contents, which includes the write count. The selected NV memory array auto-increments the write count internally without sending the write count to the controller to be incremented. The selected NV memory array can write the incremented write count back its bitcells. In one example, the selected NV memory array writes the write count back with the user data to be written to the other NV memory arrays. The auto-increment can eliminate the need for the controller to read and increment the write count. Without the involvement of the controller, the auto-increment can save at least a read cycle issued by the controller to the NV media for each write cycle of the NV media.

In one example, the selected NV memory array that stores the write count can include an internal write count threshold. When the NV memory array increments the write count, it can also compare to the threshold and send or pass an alert to the controller when the write count threshold is reached.

In one example, the selected NV memory array performs the auto-incrementing in response to selection of a mode within the memory device. A mode refers in general to operation performed based on a configuration setting, with different operations occurring in response to the same circumstance based on the different configuration. Thus, for example, the selected NV memory array can be configured to perform auto-increment with a pre-read operation, and the other NV memory arrays are configured to simply perform the pre-read operation without auto-increment. In one example, the mode enables auto-increment hardware available in each NV memory array.

<FIG> is a block diagram of an example of a system having a selected memory array store write count and perform auto-increment on the write count. System <NUM> represents a memory system or a memory device. System <NUM> includes multiple memory devices <NUM>, identified as Devices[<NUM>:<NUM>]. It will be understood that having <NUM> devices is an example, and other systems can have more or fewer devices. Each device illustrated can include one or more memory devices.

In one example, devices <NUM> represent separate NV memory arrays for system <NUM>. In one example, the memory arrays can include 3DXP media. In one example, the memory arrays can include other NV storage media. In one example, each device <NUM> includes multiple arrays. In one example, each device <NUM> represents a separate NV memory array. In one example, each device <NUM> represents a separate NV memory chip or memory die. The number of devices <NUM> in system <NUM> will depend on the storage capacity of system <NUM>, the internal architecture, and other factors. In one example, each device <NUM> represents a separate media die. In one example, each device <NUM> represents a separate media device.

In one example, system <NUM> represents an NV storage device such as a storage module, such as an NV dual inline memory module (DIMM). In one example, system <NUM> is or is part of a device such as a solid state drive (SSD). In one example, controller <NUM> represents a media controller for system <NUM>. The media controller represents a control device to control access to the storage media of system <NUM>. From the perspective of a host system in which system <NUM> is integrated, devices <NUM> are simply seen as available storage. Controller <NUM> as a media controller manages the access to specific devices, data address, internal commands and operations to execute a host command, compliance with timing, and other management over access to devices <NUM>. In one example,.

System <NUM> illustrates Devices[<NUM>:<NUM>] as storing data <NUM>. Data <NUM> represents user data, or data created by an associated host to be stored in system <NUM>. In one example, Devices[<NUM>:<NUM>] store ECC <NUM>, which represents error checking and correction (ECC) data for data <NUM>. In one example, Device <NUM> stores ECC <NUM> and metadata (MD) <NUM>. Device <NUM> can thus store ECC data to use with ECC <NUM> as well as having additional metadata for management of access to devices <NUM>. In one example, the additional metadata <NUM> includes a write count to track the number of writes for block <NUM>. Block <NUM> can include data <NUM>, ECC <NUM>, and MD <NUM>. It will be understood from block <NUM> that devices <NUM> collectively store a block of data.

Channel <NUM> represents a communication channel between controller <NUM> and devices <NUM>. In one example, channel <NUM> could be referred to as a 3DXP channel. Channel <NUM> enables controller <NUM> to communicate with devices <NUM>. Channel <NUM> can include control or command signal lines as well as data signal lines.

In one example, when system <NUM> receives a write operation or write command from the host, controller <NUM> can generate commands or control within system <NUM> to cause device <NUM> to execute the write command. The command will include an address and data to be written. Controller <NUM> decodes the command and identifies block <NUM> as the address for the data to be written. In one example, controller <NUM> generates ECC data to write with the data received from the host. In one example, Devices[<NUM>:<NUM>] receive multiple bytes of data to be written to data <NUM>, and controller <NUM> also provides ECC <NUM> to Devices[<NUM>:<NUM>]. In one example, controller <NUM> does not provide the write count to Device <NUM>. If metadata <NUM> includes information other than the write count, controller <NUM> could provide such metadata to Device <NUM>.

In one example, block <NUM> can be considered to have a codeword represented by data <NUM>, written across multiple devices <NUM>. In one example, Device <NUM> is a selected device dedicated to keep track of a write count in metadata. In one example, controller <NUM> identifies the locations of each device <NUM> and selects one device to track the metadata. System <NUM> illustrates Device <NUM> as the selected array to store metadata <NUM>. In one example, controller <NUM> provides configuration settings for each device <NUM>, where device <NUM> is enabled as the selected array to perform auto-increment of the write count. Thus, the configuration setting can selectively enable or disable auto-increment for a selected memory array.

In one example, for every codewrite, or write of the codeword, devices <NUM> first read their respective data contents. As part of the pre-write read, in one example, Device <NUM> reads the write count and increments it for writing back to Device <NUM>. In one example, Device <NUM> places the incremented write count on the data bus with the other data to be written.

Traditionally, the logic for tracking the write count would be included in controller <NUM>. In one example, Device <NUM> includes the logic for tracking the write count. In one example, the logic is enabled when Device <NUM> is placed in an auto-increment mode. In one example, controller <NUM> sets the write count threshold (e.g., a value in a register) in connection with setting Device <NUM> into the auto-increment mode.

In one example, the block size for block <NUM> can be <NUM> bytes, <NUM> bytes, <NUM> bytes, or some other number of bytes for 3DXP media. A NAND (not AND) flash typically has larger block size, such as <NUM> or <NUM> bytes. The management of the write count for the block can have a higher positive performance impact for a system that has smaller block size.

<FIG> is a block diagram of system having a selected memory array perform an auto-increment on write count metadata. System <NUM> provides an example of a system in accordance with system <NUM> of <FIG>. Storage <NUM> can represent an example of system <NUM>, where controller <NUM> is an example of controller <NUM> of system <NUM>.

System <NUM> includes host <NUM> with memory controller <NUM> coupled to storage <NUM>. Host <NUM> represents a computing platform to which storage <NUM> is coupled. For example, host <NUM> can be or include a computer or other computing device. Memory controller <NUM> represents a controller to manage access to memory device <NUM>. In one example, memory controller <NUM> is part of a host processor (not specifically shown) of host <NUM>. Memory controller <NUM> could alternatively be considered a storage controller, depending on the connection of storage <NUM>.

In one example, the nonvolatile memory of memory device <NUM> can be coupled to a storage bus such as a peripheral component interconnect express (PCle) bus. In one example, the nonvolatile memory of memory device <NUM> is nonvolatile but is also byte addressable and random access and can be coupled to a system memory bus such as a double data rate (DDR) memory bus. Host <NUM> includes I/O (input/output) interface <NUM>. I/O <NUM> represents hardware to interface with storage <NUM>. I/O <NUM> can include an interface to a command bus or command and address bus, and a data bus. In one example, the interface includes other signal lines, such as a signal line for a memory device <NUM> to send an alert to host <NUM>.

Memory device <NUM> is illustrated having I/O <NUM>, which represents I/O for the memory devices. While controller <NUM> is not specifically illustrated with I/O, it will be understood that controller <NUM> includes I/O hardware and firmware to receive commands and exchange data with host <NUM>, and to interface with memory devices <NUM>. I/O <NUM> includes command (CMD) <NUM>, which represents an interface to a command bus or CA bus. Data <NUM> represents an interface to a data bus or DQ bus. In one example, I/O <NUM> includes alert <NUM>, which represents an interface to one or more signal lines for memory device <NUM> to an alert to host <NUM>. For example, when memory device <NUM> is a selected device to manage a write count for a group of memory devices, alert <NUM> enables the selected device to send an alert in response to a write count reaching a threshold.

Memory controller <NUM> includes scheduler <NUM> to manage the scheduling and sending of sequences of commands to storage <NUM>. Scheduler <NUM> includes logic to determine the order of commands, as well as timing requirements for the commands. Memory controller <NUM> makes determinations of what commands to send in what order. Scheduler <NUM> determines the order of commands to ensure compliance with timing requirements.

In one example, host <NUM> receives an alert from memory device <NUM> to indicate a write threshold has been reached for a block of data. In one example, in response to the alert flag, memory controller <NUM> can read one or more registers of memory device <NUM> to identify the alert. In response to the alert, in one example, memory controller <NUM> determines whether to send a command to trigger an operation such as a refresh or move of data to a different storage location (e.g., a different address within the storage). If memory controller <NUM> determines to perform an operation in response to an alert, scheduler <NUM> can schedule commands to send to storage <NUM>.

Memory controller <NUM> includes command logic <NUM> to generate commands to send to memory device <NUM>. Commands can include Write commands or Read commands. Memory controller <NUM> sends read command over a command bus, which can also be referred to as a command and address bus, and after a delay period memory device <NUM> will drive the data on the data bus. In one example, command logic <NUM> can send a refresh command or a command to move data to a different location.

Storage <NUM> includes multiple memory devices <NUM>. Memory device <NUM> includes memory array <NUM>, which represents an array of nonvolatile memory cells or storage cells. A memory cell stores a bit of data, or multiple bits for a multilevel cell. In one example, array <NUM> is separated as banks of memory or other subset of memory. In one example, memory device <NUM> is part of a group of memory devices where one or more memory devices are organized as a rank of memory. A rank of memory is a group of memory resources that share a chip select or enable signal and are thus accessed in parallel.

In one example, array <NUM> includes nonvolatile memory cells. A nonvolatile (NV) memory maintains its state even when power is interrupted to the memory. A volatile memory has indeterminate state if power is interrupted to the memory. In one example, the NV media of array <NUM> is a 3DXP media.

System <NUM> includes controller <NUM>, which represents a media controller for storage <NUM>, which represents a memory or storage module. In one example, controller <NUM> receives commands and data from host <NUM> and determines internal commands to send to memory devices <NUM> for the memory devices to respond to the commands. Controller <NUM> can also direct specific portions of data to specific memory devices <NUM>. System <NUM> also illustrates controller <NUM> of memory device <NUM>. Controller <NUM> represents logic at the memory device to receive and decode commands, and can drive the circuitry needed to respond to a command.

Memory device <NUM> includes register <NUM>, which represents one or more registers or storage locations to store configuration information or values related to the operation of memory device <NUM>. In one example, register <NUM> includes one or more mode registers. In one example, register <NUM> includes configuration information to control a write count auto-increment mode for memory device <NUM>.

In one example, memory device <NUM> includes scratchpad <NUM>, which represents a temporary storage location for memory device <NUM> to use for internal operations. In one example, memory device <NUM> performs a pre-write read operation in response to a write command. The pre-write read operation can include reading the contents of an address of array <NUM> and comparing to a buffered copy of the data to be written. The write buffer is not specifically shown, but provides a temporary buffer for the data to be exchanged with array <NUM>. In one example, the buffer can be considered inline to the data bus in that the buffer connects to the data paths to exchange data between array <NUM> and the data bus.

In one example, the compare generates a result that can be stored in scratchpad <NUM>. Scratchpad <NUM> represents storage for an internal operation that is not sent to controller <NUM>. Auto-increment circuit <NUM> represents hardware to enable auto-increment, such as logic circuits to perform the incrementing of the value and combining it back with the user data and ECC data to be written back to the memory array. In one example, auto-increment circuit <NUM> can be dynamically enabled and disabled based on configuration of memory device <NUM>. Namely, when memory device <NUM> is configured as the selected write count array, auto-increment circuit <NUM> can be enabled to perform the auto-increment operation on the write count.

<FIG> is a block diagram of an implementation of performing auto-increment on write count metadata. Diagram <NUM> represents a flow that can be implemented by a system in accordance with a nonvolatile memory system described.

In one example, the controller represents a media controller and 3DXP represents a NV memory device. The middle column represents operations performed by all 3DXP or all memory arrays or memory devices. The right column represents operations to be performed by a selected 3DXP device.

The controller generates a write command and address (ADDR) for the write command, block <NUM>. In one example, in response to the write command, all 3DXP devices decode the address of the command, block <NUM>. After sending the command, the controller sends the data on the DQ bus after an appropriate delay, block <NUM>. The delay is a write delay defined for the 3DXP media.

In one example, in response to decoding the command, all 3DXP devices pre-read their current data contents, block <NUM>. The 3DXP devices compare the pre-read data with the received data on the DQ bus, block <NUM>.

One of the 3DXP devices is selected as a selected 3DXP device to manage the write count. In one example, the selected 3DXP is configured into an auto-increment mode. Such a mode could be configured, in one example, by setting a register or configuration bit. For example, a configuration field or configuration bit could be auto-increment = <NUM> for non-selected 3DXP devices and auto-increment = <NUM> for the selected device.

In one example, the selected 3DXP increments the write count, block <NUM>. In one example, the selected 3DXP device compares the current write count (WR_CNT) with the incremented write count (WR_CNT+<NUM>), block <NUM>. In one example, the selected 3DXP stores ECC data or user data in addition to the write count. Thus, the selected 3DXP could perform the comparison of the pre-read data with the data on the DQ bus.

In one example, for the selected 3DXP device, the auto-increment write count mode is enabled, which means the system can ignore specific N bytes (e.g., two or three bytes) of the DQ bus for a write command. Thus, for example, collectively the 3DXP devices of one example could perform a compare of PRE_RD[<NUM>:<NUM>] with DQ_BUS[<NUM>:<NUM>], where PRE_RD[<NUM>:<NUM>] represents <NUM> bytes of data read from the memory arrays of the 3DXP devices (which could include data from the selected 3DXP device) and DQ_BUS[<NUM>:<NUM>] represents <NUM> bytes of data received from the host. The last three bytes of the DQ bus could be ignored. The selected 3DXP device can perform a compare of PRE_RD[<NUM>:<NUM>] with (PRE_RD[<NUM>:<NUM>]+<NUM>), where PRE_RD[<NUM>:<NUM>] represents the write count metadata and (PRE_RD[<NUM>:<NUM>]+<NUM>) represents the incremented write count.

In one example, the 3DXP devices only write data that is changed in response to a write command. In one example, whether the comparison of the user data, the ECC data, or the write count metadata, the 3DXP devices place the data back on the bus. For example, the devices can place the comparison of the data into a write buffer to be compared for flipped bits. In one example, the 3DXP devices only write the flipped bits, block <NUM>.

In one example, the selected 3DXP device compares the incremented write count (WR_CNT+<NUM>) to a threshold count (WR_CNT_MAX), block <NUM>. In one example, if the threshold is reached, the 3DXP device alerts the host, block <NUM>. In one example, the media controller sets the threshold or the write count limit by configuration register (such as a mode register). Thus, the selected 3DXP can set a flag or other alert if the count reaches the threshold. In response to the alert, the media controller can take proper action to respond to the write count reaching the threshold, block <NUM>.

<FIG> is a flow diagram of an example of a process for write count auto-increment. Process <NUM> for an auto-increment write count can be performed by an example of a system in accordance with system <NUM> of <FIG>, or system <NUM> of <FIG>.

In one example, a nonvolatile memory device, such as a 3DXP device, receives a configuration command from a host controller, at <NUM>. The configuration command can set the NV memory device to perform auto-increment when the NV memory device is the one selected to store the write count.

If the configuration command is to enable auto-increment, at <NUM> YES branch, in one example, the command configures a selected device to manage the write count, at <NUM>. If the configuration command is not to enable auto-increment, at <NUM> NO branch, the device is not selected to manage the write count. If the device is not to manage the write count metadata, in one example, the configuration disables an auto-increment circuit on the device, at <NUM>. Thus, all devices could include auto-increment circuitry, and one selected device has the capability enabled and the other devices have the capability disabled.

Whichever configuration is set for the memory devices, the memory devices can be ready to receive access commands. In response to receiving a write command or in response to receipt of the command, at <NUM>, in one example, the memory devices perform a pre-read of the data they have stored at the address associated with the write command, at <NUM>.

For multiple memory devices, there will be one device selected to manage the write count. Thus, the typical case will be for standard operation, and one device will have other operation to manage the write count. When auto-increment is not enabled, at <NUM> NO branch, in one example, the memory device compares the pre-read data to the received data for the write command, at <NUM>.

In one example, the memory device performs a compare of the current data contents (the pre-read data) with the data to be written because the device only writes the delta or the bits that will be flipped due to the write command. Thus, in one example, the memory devices each determine for each bit of data to be written whether the bit is flipped. If the bit is not flipped, at <NUM> NO branch, in one example, the device does not perform a write for an unchanged bit, <NUM>.

If the bit is flipped, at <NUM> YES branch, in one example, the device flips the bit on the data bus, at <NUM>. Thus, the device can place the results of the compare onto the data bus for writing to the memory array. In one example, the pre-read data is not placed on the data bus but is used only for the compare, with the results placed on the data bus to be written. Once the data on the data bus is set, the device writes the data to the array, at <NUM>.

For the device that stores the write count, auto-increment is enabled, at <NUM> YES branch. In one example, the selected device increments the write count and compares the incremented write count to a threshold, at <NUM>. The threshold can be a threshold to indicate risk of write disturb, a threshold to indicate end of life, or some other threshold. In one example, the device compares the incremented value to multiple different thresholds.

If one or more thresholds have been reached, at <NUM> YES branch, in one example, the device sends an alert to the host, at <NUM>. In one example, if multiple thresholds are compared, the device can send different alerts for different thresholds. In one example, the device sends a single alert and the host queries the device to determine the source of the alert. Whether or not a threshold has been reached, in one example, after incrementing the write count, the device can load the incremented write count for writing back to the array, at <NUM>. The write count can be considered pre-read data and the incremented write count can be in place of write data from the DQ bus to compare for flipped bits for the selected device, returning the process to <NUM>.

<FIG> is a block diagram of an example of a memory subsystem in which write count auto-increment can be implemented. System <NUM> includes a processor and elements of a memory subsystem in a computing device. System <NUM> provides an example of a system in accordance with system <NUM> of <FIG> or system <NUM> of <FIG>.

In one example, system <NUM> includes auto-increment logic <NUM> in memory device <NUM>. In one example, memory device <NUM> can be selected from among multiple memory devices of memory module <NUM> to manage a block write count for a block of memory, in accordance with any example herein. In one example, memory device <NUM> stores write count metadata in memory array <NUM>. In one example, register <NUM> includes a field to be written to determine whether memory device <NUM> is the selected memory device for managing the write count. In one example, auto-increment logic <NUM> includes hardware to perform the auto-increment of the write count.

Processor <NUM> represents a processing unit of a computing platform that may execute an operating system (OS) and applications, which can collectively be referred to as the host or the user of the memory. The OS and applications execute operations that result in memory accesses. Processor <NUM> can include one or more separate processors. Each separate processor can include a single processing unit, a multicore processing unit, or a combination. The processing unit can be a primary processor such as a CPU (central processing unit), a peripheral processor such as a GPU (graphics processing unit), or a combination. Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices can be integrated with the processor in some systems or attached to the processer via a bus (e.g., PCI express), or a combination. System <NUM> can be implemented as an SOC (system on a chip), or be implemented with standalone components.

In one example, reference to memory devices can refer to a nonvolatile memory device whose state is determinate even if power is interrupted to the device. In one example, the nonvolatile memory device is a block addressable memory device, such as NAND or NOR technologies. Thus, a memory device can also include a future generation nonvolatile devices, such as a three dimensional crosspoint memory device, other byte addressable nonvolatile memory devices. A memory device can include a nonvolatile, byte addressable media that stores data based on a resistive state of the memory cell, or a phase of the memory cell. In one example, the memory device can use chalcogenide phase change material (e.g., chalcogenide glass). In one example, the memory device can be or include multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or phase change memory with a switch (PCMS), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque (STT)-MRAM, or a combination of any of the above, or other memory.

Memory controller <NUM> represents one or more memory controller circuits or devices for system <NUM>. Memory controller <NUM> represents control logic that generates memory access commands in response to the execution of operations by processor <NUM>. Memory controller <NUM> accesses one or more memory devices <NUM>. Memory devices <NUM> can be DRAM devices in accordance with any referred to above. In one example, memory devices <NUM> are organized and managed as different channels, where each channel couples to buses and signal lines that couple to multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and the timing, data transfer, command and address exchanges, and other operations are separate for each channel. Coupling can refer to an electrical coupling, communicative coupling, physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes an interface or interconnection that allows electrical flow between components, or allows signaling between components, or both. Communicative coupling includes connections, including wired or wireless, that enable components to exchange data.

In one example, settings for each channel are controlled by separate mode registers or other register settings. In one example, each memory controller <NUM> manages a separate memory channel, although system <NUM> can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, memory controller <NUM> is part of host processor or host processor device <NUM>, such as logic implemented on the same die or implemented in the same package space as the processor.

Memory controller <NUM> includes I/O interface logic <NUM> to couple to a memory bus, such as a memory channel as referred to above. I/O interface logic <NUM> (as well as I/O interface logic <NUM> of memory device <NUM>) can include pins, pads, connectors, signal lines, traces, or wires, or other hardware to connect the devices, or a combination of these. I/O interface logic <NUM> can include a hardware interface. As illustrated, I/O interface logic <NUM> includes at least drivers/transceivers for signal lines. Commonly, wires within an integrated circuit interface couple with a pad, pin, or connector to interface signal lines or traces or other wires between devices. I/O interface logic <NUM> can include drivers, receivers, transceivers, or termination, or other circuitry or combinations of circuitry to exchange signals on the signal lines between the devices. The exchange of signals includes at least one of transmit or receive. While shown as coupling I/O <NUM> from memory controller <NUM> to I/O <NUM> of memory device <NUM>, it will be understood that in an implementation of system <NUM> where groups of memory devices <NUM> are accessed in parallel, multiple memory devices can include I/O interfaces to the same interface of memory controller <NUM>. In an implementation of system <NUM> including one or more memory modules <NUM>, I/O <NUM> can include interface hardware of the memory module in addition to interface hardware on the memory device itself. Other memory controllers <NUM> will include separate interfaces to other memory devices <NUM>.

The bus between memory controller <NUM> and memory devices <NUM> can be implemented as multiple signal lines coupling memory controller <NUM> to memory devices <NUM>. The bus may typically include at least clock (CLK) <NUM>, command/address (CMD) <NUM>, and write data (DQ) and read data (DQ) <NUM>, and zero or more other signal lines <NUM>. In one example, a bus or connection between memory controller <NUM> and memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal lines for CMD can be referred to as a "C/A bus" (or ADD/CMD bus, or some other designation indicating the transfer of commands (C or CMD) and address (A or ADD) information) and the signal lines for write and read DQ can be referred to as a "data bus. " In one example, independent channels have different clock signals, C/A buses, data buses, and other signal lines. Thus, system <NUM> can be considered to have multiple "buses," in the sense that an independent interface path can be considered a separate bus. It will be understood that in addition to the lines explicitly shown, a bus can include at least one of strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or a combination. It will also be understood that serial bus technologies can be used for the connection between memory controller <NUM> and memory devices <NUM>. An example of a serial bus technology is 8B10B encoding and transmission of high-speed data with embedded clock over a single differential pair of signals in each direction. In one example, CMD <NUM> represents signal lines shared in parallel with multiple memory devices. In one example, multiple memory devices share encoding command signal lines of CMD <NUM>, and each has a separate chip select (CS_n) signal line to select individual memory devices.

It will be understood that in the example of system <NUM>, the bus between memory controller <NUM> and memory devices <NUM> includes a subsidiary command bus CMD <NUM> and a subsidiary bus to carry the write and read data, DQ <NUM>. In one example, the data bus can include bidirectional lines for read data and for write/command data. In another example, the subsidiary bus DQ <NUM> can include unidirectional write signal lines for write and data from the host to memory, and can include unidirectional lines for read data from the memory to the host. In accordance with the chosen memory technology and system design, other signals <NUM> may accompany a bus or sub bus, such as strobe lines DQS. Based on design of system <NUM>, or implementation if a design supports multiple implementations, the data bus can have more or less bandwidth per memory device <NUM>. For example, the data bus can support memory devices that have either a x4 interface, a x8 interface, a x16 interface, or other interface. The convention "xW," where W is an integer that refers to an interface size or width of the interface of memory device <NUM>, which represents a number of signal lines to exchange data with memory controller <NUM>. The interface size of the memory devices is a controlling factor on how many memory devices can be used concurrently per channel in system <NUM> or coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices, or stacked memory configurations, or combinations, can enable wider interfaces, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface width.

In one example, memory devices <NUM> and memory controller <NUM> exchange data over the data bus in a burst, or a sequence of consecutive data transfers. The burst corresponds to a number of transfer cycles, which is related to a bus frequency. In one example, the transfer cycle can be a whole clock cycle for transfers occurring on a same clock or strobe signal edge (e.g., on the rising edge). In one example, every clock cycle, referring to a cycle of the system clock, is separated into multiple unit intervals (Uls), where each UI is a transfer cycle. For example, double data rate transfers trigger on both edges of the clock signal (e.g., rising and falling). A burst can last for a configured number of Uls, which can be a configuration stored in a register, or triggered on the fly. For example, a sequence of eight consecutive transfer periods can be considered a burst length eight (BL8), and each memory device <NUM> can transfer data on each UI. Thus, a x8 memory device operating on BL8 can transfer <NUM> bits of data (<NUM> data signal lines times <NUM> data bits transferred per line over the burst). It will be understood that this simple example is merely an illustration and is not limiting.

Memory devices <NUM> represent memory resources for system <NUM>. In one example, each memory device <NUM> is a separate memory die. In one example, each memory device <NUM> can interface with multiple (e.g., <NUM>) channels per device or die. Each memory device <NUM> includes I/O interface logic <NUM>, which has a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). I/O interface logic <NUM> enables the memory devices to interface with memory controller <NUM>. I/O interface logic <NUM> can include a hardware interface, and can be in accordance with I/O <NUM> of memory controller, but at the memory device end. In one example, multiple memory devices <NUM> are connected in parallel to the same command and data buses. In another example, multiple memory devices <NUM> are connected in parallel to the same command bus, and are connected to different data buses. For example, system <NUM> can be configured with multiple memory devices <NUM> coupled in parallel, with each memory device responding to a command, and accessing memory resources <NUM> internal to each. For a Write operation, an individual memory device <NUM> can write a portion of the overall data word, and for a Read operation, an individual memory device <NUM> can fetch a portion of the overall data word. The remaining bits of the word will be provided or received by other memory devices in parallel.

In one example, memory devices <NUM> are disposed directly on a motherboard or host system platform (e.g., a PCB (printed circuit board) on which processor <NUM> is disposed) of a computing device. In one example, memory devices <NUM> can be organized into memory modules <NUM>. In one example, memory modules <NUM> represent dual inline memory modules (DIMMs). In one example, memory modules <NUM> represent other organization of multiple memory devices to share at least a portion of access or control circuitry, which can be a separate circuit, a separate device, or a separate board from the host system platform. Memory modules <NUM> can include multiple memory devices <NUM>, and the memory modules can include support for multiple separate channels to the included memory devices disposed on them. In another example, memory devices <NUM> may be incorporated into the same package as memory controller <NUM>, such as by techniques such as multi-chip-module (MCM), package-on-package, through-silicon via (TSV), or other techniques or combinations. Similarly, in one example, multiple memory devices <NUM> may be incorporated into memory modules <NUM>, which themselves may be incorporated into the same package as memory controller <NUM>. It will be appreciated that for these and other implementations, memory controller <NUM> may be part of host processor <NUM>.

Memory devices <NUM> each include one or more memory arrays <NUM>. Memory array <NUM> represents addressable memory locations or storage locations for data. Typically, memory array <NUM> is managed as rows of data, accessed via wordline (rows) and bitline (individual bits within a row) control. Memory array <NUM> can be organized as separate channels, ranks, banks, and partitions of memory. Channels may refer to independent control paths to storage locations within memory devices <NUM>. Ranks may refer to common locations across multiple memory devices (e.g., same row addresses within different devices) in parallel. Banks may refer to sub-arrays of memory locations within a memory device <NUM>. In one example, banks of memory are divided into sub-banks with at least a portion of shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks, allowing separate addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other organizations of the memory locations, and combinations of the organizations, can overlap in their application to physical resources. For example, the same physical memory locations can be accessed over a specific channel as a specific bank, which can also belong to a rank. Thus, the organization of memory resources will be understood in an inclusive, rather than exclusive, manner.

In one example, memory devices <NUM> include one or more registers <NUM>. Register <NUM> represents one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device. In one example, register <NUM> can provide a storage location for memory device <NUM> to store data for access by memory controller <NUM> as part of a control or management operation. In one example, register <NUM> includes one or more Mode Registers. In one example, register <NUM> includes one or more multipurpose registers. The configuration of locations within register <NUM> can configure memory device <NUM> to operate in different "modes," where command information can trigger different operations within memory device <NUM> based on the mode. Additionally or in the alternative, different modes can also trigger different operation from address information or other signal lines depending on the mode. Settings of register <NUM> can indicate configuration for I/O settings (e.g., timing, termination or ODT (on-die termination) <NUM>, driver configuration, or other I/O settings).

In one example, memory device <NUM> includes ODT <NUM> as part of the interface hardware associated with I/O <NUM>. ODT <NUM> can be configured as mentioned above, and provide settings for impedance to be applied to the interface to specified signal lines. In one example, ODT <NUM> is applied to DQ signal lines. In one example, ODT <NUM> is applied to command signal lines. In one example, ODT <NUM> is applied to address signal lines. In one example, ODT <NUM> can be applied to any combination of the preceding. The ODT settings can be changed based on whether a memory device is a selected target of an access operation or a non-target device. ODT <NUM> settings can affect the timing and reflections of signaling on the terminated lines. Careful control over ODT <NUM> can enable higher-speed operation with improved matching of applied impedance and loading. ODT <NUM> can be applied to specific signal lines of I/O interface <NUM>, <NUM> (for example, ODT for DQ lines or ODT for CA lines), and is not necessarily applied to all signal lines.

Memory device <NUM> includes controller <NUM>, which represents control logic within the memory device to control internal operations within the memory device. For example, controller <NUM> decodes commands sent by memory controller <NUM> and generates internal operations to execute or satisfy the commands. Controller <NUM> can be referred to as an internal controller, and is separate from memory controller <NUM> of the host. Controller <NUM> can determine what mode is selected based on register <NUM>, and configure the internal execution of operations for access to memory resources <NUM> or other operations based on the selected mode. Controller <NUM> generates control signals to control the routing of bits within memory device <NUM> to provide a proper interface for the selected mode and direct a command to the proper memory locations or addresses. Controller <NUM> includes command logic <NUM>, which can decode command encoding received on command and address signal lines. Thus, command logic <NUM> can be or include a command decoder. With command logic <NUM>, memory device can identify commands and generate internal operations to execute requested commands.

Referring again to memory controller <NUM>, memory controller <NUM> includes command (CMD) logic <NUM>, which represents logic or circuitry to generate commands to send to memory devices <NUM>. The generation of the commands can refer to the command prior to scheduling, or the preparation of queued commands ready to be sent. Generally, the signaling in memory subsystems includes address information within or accompanying the command to indicate or select one or more memory locations where the memory devices should execute the command. In response to scheduling of transactions for memory device <NUM>, memory controller <NUM> can issue commands via I/O <NUM> to cause memory device <NUM> to execute the commands. In one example, controller <NUM> of memory device <NUM> receives and decodes command and address information received via I/O <NUM> from memory controller <NUM>. Based on the received command and address information, controller <NUM> can control the timing of operations of the logic and circuitry within memory device <NUM> to execute the commands. Controller <NUM> is responsible for compliance with standards or specifications within memory device <NUM>, such as timing and signaling requirements. Memory controller <NUM> can implement compliance with standards or specifications by access scheduling and control.

Memory controller <NUM> includes scheduler <NUM>, which represents logic or circuitry to generate and order transactions to send to memory device <NUM>. From one perspective, the primary function of memory controller <NUM> could be said to schedule memory access and other transactions to memory device <NUM>. Such scheduling can include generating the transactions themselves to implement the requests for data by processor <NUM> and to maintain integrity of the data (e.g., such as with commands related to refresh). Transactions can include one or more commands, and result in the transfer of commands or data or both over one or multiple timing cycles such as clock cycles or unit intervals. Transactions can be for access such as read or write or related commands or a combination, and other transactions can include memory management commands for configuration, settings, data integrity, or other commands or a combination.

Memory controller <NUM> typically includes logic such as scheduler <NUM> to allow selection and ordering of transactions to improve performance of system <NUM>. Thus, memory controller <NUM> can select which of the outstanding transactions should be sent to memory device <NUM> in which order, which is typically achieved with logic much more complex that a simple first-in first-out algorithm. Memory controller <NUM> manages the transmission of the transactions to memory device <NUM>, and manages the timing associated with the transaction. In one example, transactions have deterministic timing, which can be managed by memory controller <NUM> and used in determining how to schedule the transactions with scheduler <NUM>.

In one example, memory controller <NUM> includes refresh (REF) logic <NUM>. Refresh logic <NUM> can be used to refresh memory resources to retain a deterministic state. Volatile memory resources need to be refreshed regularly to maintain state, while nonvolatile memory resources may need to be refreshed to avoid read/write disturb. In one example, refresh logic <NUM> indicates a location for refresh, and a type of refresh to perform. Refresh logic <NUM> can trigger self-refresh within memory device <NUM>, or execute external refreshes (which can be referred to as auto refresh commands) by sending refresh commands, or a combination. In one example, controller <NUM> within memory device <NUM> includes refresh logic <NUM> to apply refresh within memory device <NUM>. Refresh logic <NUM> generates internal operations to perform refresh either internally, or in accordance with an external refresh received from memory controller <NUM>.

<FIG> is a block diagram of an example of a computing system in which write count auto-increment can be implemented. System <NUM> represents a computing device in accordance with any example herein, and can be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, embedded computing device, or other electronic device. System <NUM> provides an example of a system in accordance with system <NUM> of <FIG> or system <NUM> of <FIG>.

In one example, system <NUM> includes auto-increment logic <NUM> in memory subsystem <NUM> or auto-increment logic <NUM> in storage subsystem <NUM>, or includes both. In one example, one NV memory device or NV memory array of memory <NUM>, or one NV memory device of storage <NUM> can be selected from among multiple devices to manage a block write count for a block of memory, in accordance with any example herein. In one example, the selected NV memory device or NV memory array stores write count metadata. In one example, the selected device is selected based on a configuration mode configured for managing the write count. In one example, auto-increment logic <NUM> or auto-increment logic <NUM> includes hardware to perform the auto-increment of the write count.

System <NUM> includes processor <NUM> can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination, to provide processing or execution of instructions for system <NUM>. Processor <NUM> controls the overall operation of system <NUM>, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of such devices.

In one example, system <NUM> includes interface <NUM> coupled to processor <NUM>, which can represent a higher speed interface or a high throughput interface for system components that need higher bandwidth connections, such as memory subsystem <NUM> or graphics interface components <NUM>. Interface <NUM> represents an interface circuit, which can be a standalone component or integrated onto a processor die. Interface <NUM> can be integrated as a circuit onto the processor die or integrated as a component on a system on a chip. Where present, graphics interface <NUM> interfaces to graphics components for providing a visual display to a user of system <NUM>. Graphics interface <NUM> can be a standalone component or integrated onto the processor die or system on a chip. In one example, graphics interface <NUM> can drive a high definition (HD) display or ultra high definition (UHD) display that provides an output to a user. In one example, the display can include a touchscreen display. In one example, graphics interface <NUM> generates a display based on data stored in memory <NUM> or based on operations executed by processor <NUM> or both.

Memory subsystem <NUM> represents the main memory of system <NUM>, and provides storage for code to be executed by processor <NUM>, or data values to be used in executing a routine. Memory subsystem <NUM> can include one or more memory devices <NUM> such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, 3DXP (three-dimensional crosspoint), or other memory devices, or a combination of such devices. Memory <NUM> stores and hosts, among other things, operating system (OS) <NUM> to provide a software platform for execution of instructions in system <NUM>. Additionally, applications <NUM> can execute on the software platform of OS <NUM> from memory <NUM>. Applications <NUM> represent programs that have their own operational logic to perform execution of one or more functions. Processes <NUM> represent agents or routines that provide auxiliary functions to OS <NUM> or one or more applications <NUM> or a combination. OS <NUM>, applications <NUM>, and processes <NUM> provide software logic to provide functions for system <NUM>. In one example, memory subsystem <NUM> includes memory controller <NUM>, which is a memory controller to generate and issue commands to memory <NUM>. It will be understood that memory controller <NUM> could be a physical part of processor <NUM> or a physical part of interface <NUM>. For example, memory controller <NUM> can be an integrated memory controller, integrated onto a circuit with processor <NUM>, such as integrated onto the processor die or a system on a chip.

While not specifically illustrated, it will be understood that system <NUM> can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or other bus, or a combination.

In one example, system <NUM> includes interface <NUM>, which can be coupled to interface <NUM>. Interface <NUM> can be a lower speed interface than interface <NUM>. In one example, interface <NUM> represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface <NUM>. Network interface <NUM> provides system <NUM> the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface <NUM> can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface <NUM> can exchange data with a remote device, which can include sending data stored in memory or receiving data to be stored in memory.

In one example, system <NUM> includes one or more input/output (I/O) interface(s) <NUM>. I/O interface <NUM> can include one or more interface components through which a user interacts with system <NUM> (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface <NUM> can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system <NUM>. A dependent connection is one where system <NUM> provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system <NUM> includes storage subsystem <NUM> to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage <NUM> can overlap with components of memory subsystem <NUM>. Storage subsystem <NUM> includes storage device(s) <NUM>, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, 3DXP, or optical based disks, or a combination. Storage <NUM> holds code or instructions and data <NUM> in a persistent state (i.e., the value is retained despite interruption of power to system <NUM>). Storage <NUM> can be generically considered to be a "memory," although memory <NUM> is typically the executing or operating memory to provide instructions to processor <NUM>. Whereas storage <NUM> is nonvolatile, memory <NUM> can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system <NUM>). In one example, storage subsystem <NUM> includes controller <NUM> to interface with storage <NUM>. In one example controller <NUM> is a physical part of interface <NUM> or processor <NUM>, or can include circuits or logic in both processor <NUM> and interface <NUM>.

Power source <NUM> provides power to the components of system <NUM>. More specifically, power source <NUM> typically interfaces to one or multiple power supplies <NUM> in system <NUM> to provide power to the components of system <NUM>. In one example, power supply <NUM> includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source <NUM>. In one example, power source <NUM> includes a DC power source, such as an external AC to DC converter. In one example, power source <NUM> or power supply <NUM> includes wireless charging hardware to charge via proximity to a charging field. In one example, power source <NUM> can include an internal battery or fuel cell source.

<FIG> is a block diagram of an example of a mobile device in which write count auto-increment can be implemented. System <NUM> represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, wearable computing device, or other mobile device, or an embedded computing device. It will be understood that certain of the components are shown generally, and not all components of such a device are shown in system <NUM>. System <NUM> provides an example of a system in accordance with system <NUM> of <FIG> or system <NUM> of <FIG>.

In one example, system <NUM> includes auto-increment logic <NUM> in memory subsystem <NUM>. In one example, one NV memory device or NV memory array of memory <NUM> can be selected from among multiple devices to manage a block write count for a block of memory, in accordance with any example herein. In one example, the selected NV memory device or NV memory array stores write count metadata. In one example, the selected device is selected based on a configuration mode configured for managing the write count. In one example, auto-increment logic <NUM> includes hardware to perform the auto-increment of the write count.

System <NUM> includes processor <NUM>, which performs the primary processing operations of system <NUM>. Processor <NUM> can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting system <NUM> to another device, or a combination. The processing operations can also include operations related to audio I/O, display I/O, or other interfacing, or a combination. Processor <NUM> can execute data stored in memory. Processor <NUM> can write or edit data stored in memory.

In one example, system <NUM> includes one or more sensors <NUM>. Sensors <NUM> represent embedded sensors or interfaces to external sensors, or a combination. Sensors <NUM> enable system <NUM> to monitor or detect one or more conditions of an environment or a device in which system <NUM> is implemented. Sensors <NUM> can include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide, carbon dioxide, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiology sensors (e.g., biosensors, heart rate monitors, or other sensors to detect physiological attributes), or other sensors, or a combination. Sensors <NUM> can also include sensors for biometric systems such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user features. Sensors <NUM> should be understood broadly, and not limiting on the many different types of sensors that could be implemented with system <NUM>. In one example, one or more sensors <NUM> couples to processor <NUM> via a frontend circuit integrated with processor <NUM>. In one example, one or more sensors <NUM> couples to processor <NUM> via another component of system <NUM>.

In one example, system <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker or headphone output, as well as microphone input. Devices for such functions can be integrated into system <NUM>, or connected to system <NUM>. In one example, a user interacts with system <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes tactile components or touchscreen elements for a user to interact with the computing device. Display subsystem <NUM> includes display interface <NUM>, which includes the particular screen or hardware device used to provide a display to a user. In one example, display interface <NUM> includes logic separate from processor <NUM> (such as a graphics processor) to perform at least some processing related to the display. In one example, display subsystem <NUM> includes a touchscreen device that provides both output and input to a user. In one example, display subsystem <NUM> includes a high definition (HD) or ultra-high definition (UHD) display that provides an output to a user. In one example, display subsystem includes or drives a touchscreen display. In one example, display subsystem <NUM> generates display information based on data stored in memory or based on operations executed by processor <NUM> or both.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> can operate to manage hardware that is part of audio subsystem <NUM>, or display subsystem <NUM>, or both. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to system <NUM> through which a user might interact with the system. For example, devices that can be attached to system <NUM> might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, buttons/switches, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> or display subsystem <NUM> or both. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of system <NUM>. Additionally, audio output can be provided instead of or in addition to display output. In another example, if display subsystem includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on system <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one example, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS), or other hardware that can be included in system <NUM>, or sensors <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one example, system <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation. Power management <NUM> manages power from power source <NUM>, which provides power to the components of system <NUM>. In one example, power source <NUM> includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion based power). In one example, power source <NUM> includes only DC power, which can be provided by a DC power source, such as an external AC to DC converter. In one example, power source <NUM> includes wireless charging hardware to charge via proximity to a charging field. In one example, power source <NUM> can include an internal battery or fuel cell source.

Memory subsystem <NUM> includes memory device(s) <NUM> for storing information in system <NUM>. Memory subsystem <NUM> can include nonvolatile (state does not change if power to the memory device is interrupted) or volatile (state is indeterminate if power to the memory device is interrupted) memory devices, or a combination. Memory <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system <NUM>. In one example, memory subsystem <NUM> includes memory controller <NUM> (which could also be considered part of the control of system <NUM>, and could potentially be considered part of processor <NUM>). Memory controller <NUM> includes a scheduler to generate and issue commands to control access to memory device <NUM>.

Connectivity <NUM> includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable system <NUM> to communicate with external devices. The external device could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. In one example, system <NUM> exchanges data with an external device for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory, or data already stored in memory, to read, write, or edit data.

Connectivity <NUM> can include multiple different types of connectivity. To generalize, system <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, LTE (long term evolution - also referred to as "<NUM>"), <NUM>, or other cellular service standards. Wireless connectivity <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth), local area networks (such as WiFi), or wide area networks (such as WiMax), or other wireless communication, or a combination. Wireless communication refers to transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs through a solid communication medium.

Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that system <NUM> could both be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. System <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading, uploading, changing, synchronizing) content on system <NUM>. Additionally, a docking connector can allow system <NUM> to connect to certain peripherals that allow system <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, system <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), or other type.

Flow diagrams as illustrated herein provide examples of sequences of various process actions. The flow diagrams can indicate operations to be executed by a software or firmware routine, as well as physical operations. A flow diagram can illustrate an example of the implementation of states of a finite state machine (FSM), which can be implemented in hardware and/or software. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions can be modified. Thus, the illustrated diagrams should be understood only as examples, and the process can be performed in a different order, and some actions can be performed in parallel. Additionally, one or more actions can be omitted; thus, not all implementations will perform all actions.

To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The content can be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content of what is described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A machine readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.

Various components described herein can be a means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc..

Claim 1:
A nonvolatile memory device comprising:
multiple nonvolatile, NV, memory arrays (<NUM>-<NUM>; <NUM>; <NUM>) to collectively store a block of data, each array to store a portion of the block of data, and one of the NV memory arrays to store a write count for the block of data; and
a command bus interface (<NUM>; <NUM>) to receive a write command to write the block of data to the NV memory arrays , wherein the NV memory arrays are configured to perform an internal pre-write read of the block of data in the NV memory arrays in response to receipt of the write command, said internal pre-write read being performed without sending the write count to a controller (<NUM>; <NUM>; <NUM>) to be incremented, wherein the one NV memory array is configured to perform a pre-write read of the write count, increment the write count internal to the one NV memory array, and write the incremented write count to the one NV memory array, wherein the NV memory arrays are configured to perform the internal pre-write read of the block of data in the NV memory arrays, compare data in the NV memory arrays with data to be written, and only write bits having a different value due to the write command.