Patent Description:
Electrical circuits requiring high power handling capability while operating at high frequencies, such as radio frequencies (<NUM>), S-band (<NUM>) and X-band (<NUM>), have in recent years become more prevalent. Because of the increase in high power, high frequency circuits, there has been a corresponding increase in demand for semiconductor devices which are capable of reliably operating at radio and microwave frequencies while still being capable of handling high power loads.

To provide increased output power, semiconductor devices have been developed that include a plurality of "unit cell" transistors that are formed on a common semiconductor structure and that are electrically connected in parallel. Each unit cell transistor may include a gate finger that extends in parallel between elongated source and drain contacts, as is schematically illustrated in <FIG>.

In particular, <FIG> illustrates a metal layout of a conventional semiconductor device <NUM> that includes a gate pad <NUM>, a source pad <NUM> and a drain pad <NUM> on a semiconductor structure <NUM>. <FIG> is a plan view of the semiconductor device (i.e., looking down at the device from above) that illustrates various metal contact structures of the semiconductor device <NUM> that are formed on the underlying semiconductor structure <NUM>. As shown in <FIG>, in the conventional semiconductor device <NUM>, the gate pad <NUM> is connected by a gate bus <NUM> to a plurality of gate fingers <NUM> that extend in parallel in a first direction (e.g., the y-direction indicated in <FIG>). The drain pad <NUM> is connected to a plurality of drain contacts <NUM> via a drain bus <NUM>. The source pad <NUM> is connected to a plurality of parallel source contacts <NUM> via a source bus <NUM> that is disposed at a different metallization layer (here a higher metallization layer that runs above the gate fingers <NUM> and the drain contacts <NUM>). Vertically-extending (i.e., extending in a z-direction that is perpendicular to the x-direction and the y-direction) source contact plugs <NUM> electrically connect each source contact <NUM> to the source bus <NUM>.

Each gate finger <NUM> runs along the y-direction between a pair of adjacent source and drain contacts <NUM>, <NUM>. A unit cell transistor of semiconductor device <NUM> is illustrated at box <NUM>, and includes a gate finger <NUM> that extends between adjacent source and drain contacts <NUM>, <NUM>. The "gate length" refers to the distance of the gate metallization in the x-direction, while the "gate width" is the distance by which the gate fingers <NUM> and the source and drain contacts <NUM>, <NUM> overlap in the y-direction. That is, "width" of a gate finger <NUM> refers to the dimension of the gate finger <NUM> that extends in parallel to the adjacent source/drain contacts <NUM>, <NUM> (the distance along the y-direction). The power handling capability of the semiconductor device <NUM> may be proportional to its "gate periphery. " The gate periphery of semiconductor device <NUM> is the sum of the gate widths for each gate finger <NUM> of the semiconductor device <NUM>.

Semiconductor devices formed of wide band-gap semiconductor materials such as silicon carbide and/or gallium nitride based semiconductor materials may operate at higher current densities and hence are widely used in high power applications. In particular, gallium nitride based transistors that include one or more epitaxial layers of gallium nitride based semiconductor materials such as GaN, AlGaN, InGaN, etc. are now commonly used in high power applications such as transistor amplifiers for wireless communications. These gallium nitride based epitaxial layers are typically grown on silicon carbide or sapphire substrates. There is a need, however, for high power semiconductor devices that exhibit improved performance.

<CIT> describes an electronic device comprising a field effect transistor for high-frequency applications.

<CIT> describes a dual-channel field effect transistor (FET) device having increased amplifier linearity.

<CIT> electrical devices having improved transfer characteristics and a corresponding method of tailoring the transfer characteristics of such electrical devices.

<CIT> describes an apparatus and method for exploiting reverse short channel effects in transistor devices.

In a first aspect, a method according to claim <NUM> is provided. Pursuant to embodiments of the present invention, semiconductor devices are provided that include a plurality of unit cell transistors that are formed on a common semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a gate finger. In some embodiments, the respective threshold voltages of first and second of the unit cell transistors differ by at least <NUM> volts
and/or threshold voltages of first and second portions of a third of the unit cell transistors differ by at least <NUM> volts.

In some embodiments, the gate fingers may extend in parallel to one another. The semiconductor structure includes a gallium nitride based channel layer.

In some embodiments, the threshold voltage of the first and second of the unit cell transistors may differ by at least <NUM> volts. In some embodiments, the threshold voltages of the first and second segments of the third of the unit cell transistors may differ by at least <NUM> volts or by at least <NUM> volts. In some embodiments, the threshold voltage of the first and second of the unit cell transistors may differ by between <NUM>-<NUM> volts. In some embodiments, the threshold voltages of the first and second portions of the third of the unit cell transistors may differ by between <NUM>-<NUM> volts.

In some embodiments, the unit cell transistors may be divided into a plurality of groups, each group including at least five unit cell transistors, where the threshold voltages of the unit cell transistors within each group are within <NUM> volts of each other. Each group may include approximately the same number of unit cell transistors. The number of groups may be two or three in example embodiments.

In some embodiments, each gate finger may include at least two segments having threshold voltages that differ by at least <NUM> volts. In other embodiments, each gate finger may include at least two segments having threshold voltages that differ by at least <NUM> volts or by at least <NUM> volts. In still other embodiments, each gate finger may include at least two segments having threshold voltages that differ by between <NUM>-<NUM> volts.

In some embodiments, the semiconductor structure may include a gallium nitride based layer that acts as a barrier layer for each of the unit cell transistors, and a thickness of the gallium nitride based layer may vary in different regions of the semiconductor device. For example, in some embodiments, the gallium nitride based layer may have a first thickness underneath the first segment of the third of the unit cell transistors and may have a second, different thickness underneath the second segment of the third of the unit cell transistors. In other embodiments, the gallium nitride based layer may have a first thickness underneath the first of the unit cell transistors and may have a second thickness underneath the second of the unit cell transistors.

In some embodiments, a doping concentration of the portion of the channel layer that is underneath a gate finger of the third of the unit cell transistors may vary along the width of the gate finger of the third of the unit cell transistors.

In some embodiments, a first doping concentration of a first portion of the channel layer that is underneath a gate finger of the first of the unit cell transistors fingers may be different than a second doping concentration of a second portion of the channel layer that is underneath a gate finger of the second of the unit cell transistors. For example, one may be doped and the other may be undoped.

In some embodiments, at least a portion of a gate finger of the first of the unit cell transistors may be a different material than at least a portion of a gate finger of a second of the unit cell transistors.

Pursuant to further embodiments. semiconductor devices are provided that include a plurality of unit cell transistors that are formed on a semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor including a gate finger. Threshold voltages of at least a first subset of the unit cell transistors vary along the width of the respective gate fingers of the unit cell transistors in the first subset of the unit cell transistors.

In some embodiments, the threshold voltages of the unit cell transistors in the first subset of the unit cell transistors may vary by at least <NUM> volts along the width of their respective gate fingers. In other embodiments, the threshold voltages of the unit cell transistors in the first subset of the unit cell transistors may vary by at least <NUM> volts (or by at least <NUM> volts) along the width of their respective gate fingers. In still other embodiments, the threshold voltages of the unit cell transistors in the first subset of the unit cell transistors may vary by between <NUM>-<NUM> volts along the width of their respective gate fingers.

In some embodiments, the gate fingers of the unit cell transistors may extend in parallel to one another.

In some embodiments, the semiconductor structure may include a gallium nitride based channel layer.

In some embodiments, each gate finger may include at least three segments that have different threshold voltages.

In some embodiments, the semiconductor device may include a gallium nitride based layer that acts as a barrier layer for each of the unit cell transistors. The gallium nitride based layer may have at least two different thicknesses underneath at least half of the gate fingers.

In some embodiments, the semiconductor device may include a channel layer, and respective portions of the channel layer that are underneath the gate fingers may have different doping concentrations underneath at least two different portions of each of the respective gate fingers.

In some embodiments, each gate finger of the first subset of the unit cell transistors may have between two and five segments. A value of the threshold voltage of each unit cell transistor in the first subset of the unit cell transistors may be substantially constant along each segment, while different segments may have threshold voltages that vary by at least <NUM> volts from at least one other segment.

Pursuant to still further embodiments, semiconductor devices are provided that include a plurality of unit cell transistors that are formed on a semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor including a gate finger. Each unit cell transistor in a first subset of the unit cell transistors may have a first threshold voltage and each unit cell transistor in a second subset of the unit cell transistors may have a second threshold voltage that differs from the first threshold voltage.

In some embodiments, the first threshold voltage may differ from the second threshold voltage by at least <NUM> volts.

In some embodiments, the gate fingers may extend in parallel to one another.

In some embodiments, the first threshold voltage may differ from the second threshold voltage by at least <NUM> volts or by at least <NUM> volts. In some embodiments, the first threshold voltage may differ from the second threshold voltage by between <NUM>-<NUM> volts.

In some embodiments, the first subset of the unit cell transistors and the second subset of the unit cell transistors may each include approximately the same number of unit cell transistors.

In some embodiments, each unit cell transistor in a third subset of the unit cell transistors may have a third threshold voltage that differs from both the first threshold voltage and the second threshold voltage.

In some embodiments, the semiconductor structure may include a gallium nitride based layer that acts as a barrier layer of each of the unit cell transistors. A thickness of the gallium nitride based layer under the gate fingers of each unit cell transistor in the first subset of the unit cell transistors may be different than a thickness of the barrier layer under the gate fingers in each unit cell transistor in the second subset of the unit cell transistors.

In some embodiments, the semiconductor device may include a channel layer, and a first doping concentration of a first portion of the channel layer that is underneath the gate fingers of the unit cell transistors in the first subset of the unit cell transistors may be different from a second doping concentration of a second portion of the channel layer that is underneath the gate fingers of the unit cell transistors in the second subset of the unit cell transistors.

According to the present invention, a method of increasing the linearity of a semiconductor device is provided in which a semiconductor device is formed that includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a gate finger. One or more voltage signals are applied to the gate fingers of the unit cell transistors in order to turn on different portions of the 2DEG channel of the semiconductor device at respective different levels of current flow.

In some embodiments, first and second segments of at least some of the gate fingers may have threshold voltages that differ by at least <NUM> volts. In other embodiments, these first and second segments may have threshold voltages that differ by at least <NUM> volts.

In some embodiments, different ones of the unit cell transistors may have threshold voltages that differ by at least <NUM> volts. In other embodiments, different ones of the unit cell transistors may have threshold voltages that differ by at least <NUM> volts or by at least <NUM> volts. In still other embodiments, different ones of the unit cell transistors may have threshold voltages that differ by between <NUM>-<NUM> volts.

In some embodiments, each unit cell transistor has substantially the same threshold voltage and the same structure. In these embodiments, a first of the voltage signals may be applied to a first subset of the gate fingers of the unit cell transistors and a second of the voltage signals that differs from the first voltage signal by at least <NUM> volts may be simultaneously applied to a second subset of the gate fingers of the unit cell transistors. In other embodiments, the first and second of the voltage signals may differ by at least <NUM> volts or be between <NUM>-<NUM> volts.

According to the present invention, the unit cell transistors are divided into a plurality of groups, each group including at least five unit cell transistors. The threshold voltages of the unit cell transistors within each group is within <NUM> volts of each other in some embodiments. Each group includes the same number of unit cell transistors in accordance with the present invention, and the number of groups may be two, three or more in various embodiments, not forming part of the present invention but useful for understanding it.

According to the present invention, the semiconductor structure includes a gallium nitride based channel layer and a gallium nitride based barrier layer on the gallium nitride based channel layer, and the gate fingers extend in parallel to one another. In such embodiments, a thickness of the gallium nitride based barrier layer may vary in different regions of the semiconductor device. The gallium nitride based barrier layer may, for example, have a first thickness underneath a first segment of a first of the unit cell transistors and a second, different thickness underneath a second segment of the first of the unit cell transistors. Additionally or alternatively, the gallium nitride based layer may have a first thickness underneath a first subset of the unit cell transistors and a second thickness underneath a second subset of the unit cell transistors.

Pursuant to still further embodiments of the present invention, semiconductor devices are provided that include a plurality of unit cell transistors on a semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor including a gate finger that extends above a gallium nitride based barrier layer of the semiconductor structure. A thickness of the gallium nitride based barrier layer is different in different locations within the semiconductor device.

In some embodiments, the gallium nitride based barrier layer may have a first thickness underneath respective first segments of the gate fingers of a first subset of the unit cell transistors and a second, different thickness underneath respective second segments of the gate fingers of the first subset of the unit cell transistors. The first and second thicknesses may differ, for example, by at least <NUM>.

In some embodiments, the gallium nitride based barrier layer may have a first thickness underneath a first subset of the unit cell transistors and a second thickness underneath a second subset of the unit cell transistors. The first and second thicknesses may differ, for example, by at least <NUM>.

In some embodiments, different subsets of the unit cell transistors may have threshold voltages that differ by at least <NUM> volts or by at least <NUM> volts or by at least <NUM> volts.

In some embodiments, different segments of at least one of the gate fingers may have threshold voltages that differ by at least <NUM> volts or by at least <NUM> volts or by at least <NUM> volts.

Pursuant to still further embodiments of the present invention, semiconductor devices are provided that include a plurality of unit cell transistors on a semiconductor structure that includes a gallium nitride based barrier layer. The unit cell transistors are electrically connected in parallel, and each unit cell transistor including a gate finger that extends above the gallium nitride based barrier layer. These devices further include a voltage divider that has a first output that is coupled to the gate fingers of a first subset of the unit cell transistors and a second output that is coupled to the gate fingers of a second subset of the unit cell transistors. The first and second outputs are configured to apply respective first and second voltages to the gate fingers of the respective first and second subsets of the unit cell transistors, where the first and second voltages differ by at least <NUM> volts.

In some embodiments, the unit cell transistors of the first and second subsets of unit cell transistors may have identical designs.

In some embodiments, the first and second voltages may differ by at least <NUM> volts.

In some embodiments, the voltage divider may include a third output that is coupled to the gate fingers of a third subset of the unit cell transistors, where the third output is configured to apply a third voltage to the gate fingers of the third subset of the unit cell transistors, the third voltage differing from both the first and second voltages by at least <NUM> volts (or by at least <NUM> volts or <NUM> volts in other embodiments).

Embodiments of the present invention provide multi-cell semiconductor devices (i.e., a semiconductor device that includes a plurality of unit cell transistors) that may exhibit improved linearity. One common measure of the linearity of a multi-cell semiconductor device is the third order transconductance behavior of the device. Because multi-cell semiconductor devices formed in gallium nitride and various other wide bandgap semiconductor material systems may exhibit sharp turn-on behavior, multi-cell semiconductor devices formed in these material systems may exhibit significant variance in their third order transconductance response at device turn-on. Non-linearities in the third order transconductance may generate third order intermodulation products in the output signal of the transistor. If these third order intermodulation products fall within a channel of a communications system that includes the multi-cell semiconductor device, the third order intermodulation products may degrade the performance of the communications system. The third order transconductance at device turn-on is often the primary parameter contributing to third order intermodulation products in a multi-cell semiconductor device. The peak third order transconductance value increases proportionally with the size of the device. Thus, as applications require larger, higher power semiconductor devices, it may become increasingly difficult to provide a high degree of linearity.

Pursuant to embodiments of the present invention, multi-cell semiconductor devices are provided that may exhibit significantly improved linearity. This improved linearity may be achieved by engineering the threshold voltage of the device to provide the improved linearity, or by applying different gate voltages to different portions of the device. The semiconductor devices according to embodiments of the present invention may, in some embodiments, be high power devices that include a plurality of unit cells that are electrically connected in parallel. Each unit cell may include a gate finger, and the gate fingers may extend in parallel to each other.

The threshold voltage of a field effect transistor refers to the minimum gate-to-source voltage differential that is needed to allow current to pass between the source and drain terminals of the transistor. The multi-cell semiconductor devices according to embodiments of the present invention may have a variable threshold voltage that is different in different locations within the device. In some embodiments, distinct subsets of the gate fingers may have different threshold voltages. In other embodiments, the threshold voltage may vary along the widths of the respective gate fingers. In still other embodiments, the above two approaches can be combined. By designing the semiconductor devices to have different threshold voltages in different regions of the device, different portions of the 2DEG channel of the semiconductor device may turn on at different degrees in response to application of a gate voltage. In other words, different portions of the 2DEG channel of the semiconductor device may turn on at different levels of current flow. For example, in some embodiments, different portions of the 2DEG channel of the semiconductor device may have levels of current flow that differ by at least <NUM>%. In other embodiments, different portions of the 2DEG channel of the semiconductor device may have levels of current flow that differ by at least <NUM>%. In still other embodiments, different portions of the 2DEG channel of the semiconductor device may have levels of current flow that differ by between <NUM>%-<NUM>%. As discussed above, semiconductor devices formed in wide band-gap semiconductor material systems such as, for example, gallium nitride based semiconductors, may exhibit fast turn-on behavior where all of the unit cells turn on essentially simultaneously. Since the third order transconductance tends to peak at turn-on, multi-cell semiconductor devices formed in such material systems may experience a large spike in the third order transconductance at device turn-on, since all of the unit cells turn on simultaneously. By varying the threshold voltage so that different portions of the device have different threshold voltages, the degree to which the channel is turned on at any given time will vary across the device, reducing the magnitude of the spike in the third order transconductance.

In accordance with the present invention, the semiconductor devices are high electron mobility transistors ("HEMT") that include a channel layer and a barrier layer. In such devices, the threshold voltage may be varied in different regions of the device by varying the thickness of the barrier layer. In other embodiments, the doping concentration of the barrier layer and/or the channel layer may be varied in different portions of the device to vary the threshold voltage. In still other embodiments, the composition of the gate fingers may be varied, either along the width of the gate finger and/or between different gate fingers. For example, different metals may be used and/or metal alloys having different compositions in order to vary the threshold voltage.

In still other embodiments, multi-cell semiconductor devices are provided that may include an associated voltage divider circuit that may be configured to provide different gate voltages to different unit cells of the device. These devices may have unit cells that have the same structure and configuration. However, by applying different gate voltages to different subsets of the gate fingers, different unit cell transistors can be configured to turn on at different degrees (i.e., at different levels of current flow) in order to smooth out the peak in the third order transconductance.

The semiconductor devices according to embodiments of the present invention may exhibit significantly improved linearity. For example, if the semiconductor device is divided into two regions having different threshold voltage values, the peak third order transconductance value may be reduced on the order of <NUM>% as compared to a device having uniform threshold voltages throughout. If the semiconductor device is divided into three regions having different threshold voltage values, the peak third order transconductance value may be reduced on the order of <NUM>% as compared to a device having uniform threshold voltages throughout. In semiconductor devices having greater variation in the threshold voltage, further reduction of the third order transconductance may be achieved. These improvements in linearity maybe achieved with little impact on the other operating characteristics of the device such as, for example, the gain of the device.

In some example embodiments, semiconductor devices are provided that include a plurality of unit cell transistors that are formed on a common semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a respective gate finger. The threshold voltages of first and second subsets of the unit cell transistors are designed to differ by, for example, at least <NUM> volts in some embodiments. In other embodiments, this difference may be at least <NUM> volts. In further embodiments, this difference may be at least <NUM> volts. In still other embodiments, the difference may be between <NUM>-<NUM> volts.

In other example embodiments, semiconductor devices are provided that include a plurality of unit cell transistors that are formed on a common semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a respective gate finger. The threshold voltages of first and second segments of at least some of the unit cell transistors are designed to differ by, for example, at least <NUM> volts in some embodiments. In other embodiments, this difference may be at least <NUM> volts or at least <NUM> volts. In still other embodiments, the difference may be between <NUM>-<NUM> volts.

In still further example embodiments, semiconductor devices are provided that include a plurality of unit cell transistors on a semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a gate finger that extends above a gallium nitride based barrier layer of the semiconductor structure. A thickness of the gallium nitride based barrier layer is different in different locations within the semiconductor device in order to vary the threshold voltage throughout the semiconductor device.

In yet additional example embodiments, semiconductor devices are provided that include a plurality of unit cell transistors on a semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a gate finger that extends above a gallium nitride based barrier layer of the semiconductor structure. The semiconductor devices include a voltage divider that has a first output that is coupled to the gate fingers of a first subset of the unit cell transistors and a second output that is coupled to the gate fingers of a second subset of the unit cell transistors. The first and second outputs are configured to apply first and second voltages to the gate fingers of the first and second subsets of the unit cell transistors, respectively, where the first and second voltages differ by, for example, at least <NUM> volts or by at least <NUM> volts in other embodiments.

Methods of increasing the linearity of a semiconductor device in accordance with the present invention are also provided. Pursuant to these methods, a semiconductor device is formed that includes a plurality of unit cell transistors on a common semiconductor structure. The unit cell transistors are electrically connected in parallel, and each unit cell transistor includes a gate finger. One or more voltage signals are applied to the gate fingers of the unit cell transistors in order to turn on between two and ten different portions of the semiconductor device at respective different degrees.

Embodiments of the present invention will now be described in greater detail with reference to <FIG>.

<FIG> is a graph illustrating the transconductance (gm) and the third order transconductance (gm3) as a function of the gate-to-source voltage differential for a conventional gallium nitride based multi-cell semiconductor device, such as the semiconductor device <NUM> of <FIG>. As shown in <FIG>, the third order transconductance has a high positive peak followed by a high negative peak and then tends to smooth out as the applied gate voltage goes from device turn-on to saturation. Due to the sharp turn-on behavior of gallium nitride based transistors, the third order transconductance peaks near pinch off, which refers to the drain to source voltage level after which the drain to source current becomes almost constant (i.e., where the transistor enters into the saturation region). As can be seen in <FIG>, the third order transconductance peaks at a value of -<NUM>/V. As noted above, non-linearities in the third order transconductance may generate third order intermodulation products in the output signal of the device that may degrade the performance of a communications system that includes the device. Consequently, allowable values for third order transconductance are often specified for applications such as various wireless communications applications, and the semiconductor devices suitable for operation in such systems must have peak third order transconductance values that are less than the specified values.

<FIG> is a graph illustrating the threshold voltage variation in a conventional multi-cell semiconductor device having the design of the semiconductor device <NUM> of <FIG>.

Referring to <FIG>, the vertical axis represents the threshold voltage (i.e., the gate-to-source voltage differential at which the unit cell transistors turn on), while the horizontal axis denotes the gate fingers included in the conventional semiconductor device <NUM>, arranged in their order across the device (i.e., arranged in the x-axis direction of <FIG>). In other words, the left portion of the horizontal axis of <FIG> corresponds to the gate fingers <NUM> on the left side of the semiconductor device <NUM> of <FIG> while the right portion of the horizontal axis of <FIG> corresponds to the gate fingers <NUM> on the right side of the semiconductor device <NUM> of <FIG>. Thus, <FIG> shows the threshold voltage for each of the unit cell transistors of the semiconductor device <NUM>. As shown in <FIG>, in the conventional semiconductor device <NUM>, all of the unit cell transistors <NUM> have the same threshold voltage value VTH-C. It should also be noted that in the conventional semiconductor device <NUM>, the threshold voltage value VTH-C is constant along the width of each gate finger <NUM>.

<FIG> are graphs illustrating the threshold voltage variation in multi-cell semiconductor devices according to certain embodiments of the present invention. As with <FIG>, in <FIG> the horizontal axis denotes the locations of the gate fingers within the transistor along the direction of the x-axis of <FIG> (as well as the x-axis direction of <FIG>, which are discussed below), while the vertical axis represents the threshold voltage for the unit cell transistors corresponding to each respective gate finger.

As shown in <FIG>, in a first embodiment in accordance with the present invention, a first subset of the unit cell transistors are designed to have a first threshold voltage value VTH-<NUM> and a second subset of the unit cell transistors are designed to have a second threshold voltage value VTH-<NUM> that is greater than the first threshold voltage value VTH-<NUM>. The first threshold voltage value VTH-<NUM> may, for example, be lower than VTH-C while the second threshold voltage value VTH-<NUM> may, for example, be higher than VTH-C. In example embodiments, VTH-<NUM> - VTH-<NUM> may be between <NUM> and <NUM> volts, although embodiments of the present invention are not limited thereto.

Referring next to <FIG>, in a second embodiment in accordance with the present invention, a first subset of the unit cell transistors are designed to have a first threshold voltage value VTH-<NUM>, a second subset of the unit cell transistors are designed to have a second threshold voltage value VTH-<NUM> that is greater than the first second threshold voltage value VTH-<NUM>, and a third subset of the unit cell transistors are designed to have a third threshold voltage value VTH-<NUM> that is greater than the second threshold voltage value VTH-<NUM>. The first threshold voltage value VTH-<NUM> may, for example, be lower than VTH-C, the second threshold voltage value VTH-<NUM> may, for example, be approximately equal to VTH-C, and the third threshold voltage value VTH-<NUM> may, for example, be higher than VTH-C. In example embodiments, VTH-<NUM> - VTH-<NUM> may be between <NUM> and <NUM> volts, although embodiments of the present invention are not limited thereto. By adding a third discrete threshold voltage value VTH-<NUM>, the peak value of the third order transconductance at device turn-on may be further reduced by spreading out (smoothing) the device turn-on over a larger range of applied gate voltages.

Referring next to <FIG>, in a third example embodiment, not forming part of the present invention, each unit cell transistor may have a different threshold voltage value. In particular, the semiconductor device corresponding to <FIG> has unit cell transistors having steadily increasing threshold voltage values. Thus, for a semiconductor device having N unit cell transistors, the threshold voltage values may range from VTH-<NUM> to VTH-N. The threshold voltage value VTH-N/<NUM> of the center unit cell transistor may, for example, be approximately equal to VTH-C. The design corresponding to <FIG> may further spread out when different portions of the device turn on in response to application of a turn-on voltage to a gate pad of the device. The design of the semiconductor device corresponding to <FIG> may further reduce the peak value of the third order transconductance at device turn-on.

While <FIG> illustrate that the threshold voltage increases (either continuously or in discrete groups) with increasing unit cell transistor (or equivalently, gate finger position) as you move from left to right across the device (or alternatively, from right to left), it will be appreciated that this need not be the case. For example, <FIG> below illustrate additional example embodiments in which the threshold voltages for different sets of unit cell transistors are more randomly distributed throughout the device.

<FIG> are plan views of the metal layouts of three example multi-cell semiconductor devices according to certain embodiments of the present invention. The semiconductor devices of <FIG> correspond to the devices discussed above with reference to <FIG>, respectively.

As shown in <FIG>, a multi-cell semiconductor device <NUM> includes various metal patterns that are formed on a semiconductor structure <NUM>. An example composition of the semiconductor structure <NUM> will be discussed in greater detail below with reference to <FIG> and <FIG>. As shown in <FIG>, the multi-cell semiconductor device <NUM> includes a gate pad <NUM>, a source pad <NUM> and a drain pad <NUM> that are formed on the semiconductor structure <NUM>. The gate pad <NUM> is connected by a gate bus <NUM> to a plurality of gate fingers <NUM> that extend in parallel in a first direction (the y-direction). The drain pad <NUM> is connected to a plurality of parallel drain contacts <NUM> via a drain bus <NUM>. The source pad <NUM> is connected to a plurality of parallel source contacts <NUM> via a source bus <NUM> that may be disposed, for example, at a different metallization layer than the gate bus <NUM> and the drain bus <NUM>. The source bus <NUM> in the depicted embodiment runs above the gate fingers <NUM> and the drain contacts <NUM>. Vertically-extending source contact plugs <NUM> electrically connect each source contact <NUM> to the source bus <NUM>. Each gate finger <NUM> runs along the y-direction between a pair of adjacent source and drain contacts <NUM>, <NUM>. A unit cell of the transistor <NUM> is illustrated at box <NUM>, and includes a gate finger <NUM> that extends between adjacent source and drain contacts <NUM>, <NUM>.

As is further shown in <FIG>, the gate fingers <NUM> may include first gate fingers 116a and second gate fingers 116b. The gate fingers 116a may be in a first region <NUM><NUM> of the semiconductor structure <NUM>, and the gate fingers 116b may be in a second region <NUM><NUM> of the semiconductor structure <NUM>. In the first region <NUM><NUM>, the unit cell transistors <NUM> (i.e., the unit cell transistors that include the gate fingers 116a) may each have a first threshold voltage value VTH-<NUM> along the width of each gate finger 116a. In the second region <NUM><NUM>, the unit cell transistors <NUM> (i.e., the unit cell transistors that include the gate fingers 116b) may each have a second threshold voltage value VTH-<NUM> along the width of each gate finger 116b. The second threshold voltage value VTH-<NUM> may be greater than the first threshold voltage value VTH-<NUM>. As will be discussed below, the unit cell transistors in the first and second regions <NUM><NUM> and <NUM><NUM> may be made to have different threshold voltage values in a variety of ways including using different materials to form the gate fingers or changing the composition, doping concentration and/or thickness of one or more layers that underlie the gate fingers. For ease of description the gate fingers 116a of unit cell transistors having the first threshold voltage value VTH-<NUM> are shown using a first form of cross-hatching in <FIG> while the gate fingers 116b of unit cell transistors having the second threshold voltage value VTH-<NUM> are shown using a second form of cross-hatching. This same convention is also used in the figures depicting additional embodiments of the present invention. It will be appreciated, however, that depending upon the technique used to provide different threshold voltage values the gate fingers (e.g., gate fingers 116a and 116b) may or may not have the same composition.

In some embodiments, VTH-<NUM> - VTH-<NUM> may be at least <NUM> volts. In other embodiments, VTH-<NUM> - VTH-<NUM> may be at least <NUM> volts. In still other embodiments, VTH-<NUM> - VTH-<NUM> may be at least <NUM> volts. In still other embodiments, VTH-<NUM> - VTH-<NUM> may be at least <NUM> volts or be between <NUM>-<NUM> volts. In contrast, the unit cell transistors that are within a given region (e.g., the first region <NUM><NUM>) may each have substantially the same threshold voltage. For example, the unit cell transistors within each region may have threshold voltages that are within <NUM> volts of each other in some embodiments. In other embodiments, the unit cell transistors within each region may have threshold voltages that are within <NUM> volts of each other.

As shown in <FIG>, a multi-cell semiconductor device <NUM> according to further embodiments of the present invention may be similar to the semiconductor device <NUM> discussed above with reference to <FIG>, except that the semiconductor device <NUM> is divided into three regions <NUM><NUM>, <NUM><NUM>, <NUM><NUM> instead of two regions as in the case of semiconductor device <NUM>. In the first region <NUM><NUM>, unit cell transistors having gate fingers 216a may be disposed that each have a first threshold voltage value VTH-<NUM> along the width of each gate finger 216a. In the second region <NUM><NUM>, unit cell transistors having gate fingers 216b may be disposed that each have a second threshold voltage value VTH-<NUM> along the width of each gate finger 216b, where the second threshold voltage value VTH-<NUM> is greater than the first threshold voltage value VTH-<NUM>. In the third region <NUM><NUM>, unit cell transistors having gate fingers 216c may be disposed that each have a third threshold voltage value VTH-<NUM> along the width of each gate finger 216c, where the third threshold voltage value VTH-<NUM> is greater than the second threshold voltage value VTH-<NUM>. Elements of semiconductor device <NUM> that are the same as the corresponding elements of semiconductor device <NUM> are identified by the same reference numerals and further description of these elements is omitted.

As shown in <FIG>, a multi-cell semiconductor device <NUM> according to embodiment not forming part of the present invention, may be similar to the semiconductor device <NUM>, <NUM> that are discussed above, except that the semiconductor device <NUM> is divided into N regions <NUM><NUM>, <NUM><NUM>,. <NUM>N instead of two regions as in the case of device <NUM> or three regions as in the case of device <NUM>. Each of the N regions <NUM><NUM>, <NUM><NUM>,. <NUM>N includes a single unit cell transistor <NUM> that has a gate finger <NUM>. Each unit cell transistor <NUM> may be configured to have a threshold voltage value that is different from the threshold voltage values of all other of the unit cell transistors <NUM>. The threshold voltage values for the unit cell transistors <NUM> may increase monotonically from left to right in <FIG> so that the semiconductor device <NUM> will have unit cell transistors <NUM> having threshold voltage values as shown in <FIG> that range from VTH-<NUM> to VTH-N. Elements of semiconductor device <NUM> that are the same as the corresponding elements of semiconductor device <NUM> are identified by the same reference numerals and further description of these elements is omitted.

<FIG> and <FIG> illustrate semiconductor device designs where different unit cell transistors have different threshold voltage values in order to provide semiconductor devices <NUM>, <NUM>, <NUM> that have variable threshold voltages that are different in different locations within the respective devices. In other embodiments, the threshold voltage may instead be made to vary within individual unit cell transistors by configuring the unit cells so that the threshold voltage varies along the gate width of at least some of the individual gate fingers (as noted above, the "width" of a gate finger refers to the distance that the gate finger extends in parallel between the source and drain contacts, and is often longer than the "length" of the gate finger). For example, <FIG> and <FIG> are plan views of multi-cell semiconductor devices according to further embodiments not forming part of the present invention, that have threshold voltage values that vary discretely along the width of each gate finger (where, as discussed above, the "width" of the gate finger is the distance that the gate finger extends in the y-direction in the figures).

In particular, <FIG> is a plan view of a multi-cell semiconductor device <NUM>. The semiconductor device <NUM> is designed to have two different threshold voltage values along the width of each gate finger <NUM> thereof. In other words, the threshold voltage value may vary within each unit cell transistor <NUM>. In the embodiment of <FIG>, a first half <NUM>-<NUM> of each unit cell transistor <NUM> may have a first threshold voltage value VTH-<NUM> and the second half <NUM>-<NUM> of each unit cell transistor <NUM> may have a second threshold voltage value VTH-<NUM>. In the depicted embodiment, the first half <NUM>-<NUM> of each unit cell transistor <NUM> is the half closest to the gate bus <NUM>, and the second half <NUM>-<NUM> of each unit cell transistor <NUM> is the half that is remote from the gate bus <NUM>. The second threshold voltage value VTH-<NUM> may be either less than or greater than the first threshold voltage VTH-<NUM>. In <FIG> (as well as in the embodiments of <FIG> and <FIG>) the source bus <NUM> is shown in outline form to reveal the underlying metal layers in better detail.

<FIG> is a plan view of a multi-cell semiconductor device <NUM> that has three different threshold voltage values along the width of each gate finger <NUM> thereof. In particular, an initial third <NUM>-<NUM> of each unit cell transistor <NUM> may have a first threshold voltage value VTH-<NUM>, a middle third <NUM>-<NUM> of each unit cell transistor <NUM> may have a second threshold voltage value VTH-<NUM>, and an end third <NUM>-<NUM> of each unit cell transistor <NUM> may have a third threshold voltage value VTH-<NUM>. The first, second and third threshold voltage values may be different from each other.

<FIG> are graphs illustrating the transconductance and the third order transconductance as a function of the gate-to-source voltage differential for multi-cell semiconductor devices having the designs discussed above with respect to <FIG> and <FIG>, respectively (see the dotted lines). The graphs of <FIG> and <FIG> also include the transconductance and the third order transconductance as a function of the gate-to-source voltage differential for the conventional semiconductor device of <FIG> as a point of reference (see the solid lines).

As shown in <FIG> and <FIG>, the peak value of the third order transconductance may be reduced significantly by varying the threshold voltage along the width of each gate finger. By varying the threshold voltage, different portions of the device may turn-on at different applied gate voltages. As a result the device may have improved linearity. As shown, the more discrete levels of threshold voltage provided within the device the greater the improvement in the reduction in the third order transconductance. In particular, the conventional semiconductor device exhibited a peak third order transconductance value of -<NUM>. As shown in <FIG>, by designing the device to have two different threshold voltage values in different regions thereof, the peak third order transconductance value is reduced to -<NUM>, or by about <NUM>%. As shown in <FIG>, by designing the device to have three different threshold voltage values in different regions thereof, the peak third order transconductance value is reduced to -<NUM>, or by about <NUM>%. In each case, the non-linearities in the third order transconductance extends over a greater voltage range, but the peak value, which is what generally creates issues, may be substantially reduced.

<FIG> is a cross-sectional diagram taken along line 8A-8A of <FIG> that shows a portion of a cross-section of the multi-cell semiconductor device <NUM>. The semiconductor device <NUM> includes a semiconductor structure <NUM> including a substrate <NUM>, which may, for example, include <NUM>-SiC or <NUM>-SiC. A channel layer <NUM> is formed on the substrate <NUM>, and a barrier layer <NUM> is formed on the channel layer <NUM>. The channel layer <NUM> and the barrier layer <NUM> may include Group III-nitride based materials, with the material of the barrier layer <NUM> having a higher bandgap than the material of the channel layer <NUM>. For example, the channel layer <NUM> may comprise GaN, while the barrier layer <NUM> may comprise AlGaN. In some embodiments, either or both the channel layer <NUM> and the barrier layer <NUM> may not be intentionally doped layers. The channel layer <NUM> and the barrier layer <NUM> may have the same conductivity type (e.g., n-type). As shown in <FIG>, the metal contact structures including the gate fingers <NUM>, the source contacts <NUM>, the drain contacts <NUM>, the source bus <NUM> and the source contact plugs <NUM> may be formed in one or more interlayer insulating layers <NUM>, <NUM> that are formed on the barrier layer <NUM>, as may the other metal contact structures shown in <FIG>. The interlayer insulating layers <NUM>, <NUM> may include a dielectric material, such as SiN, SiO<NUM>, etc..

Due to the difference in bandgap between the barrier layer <NUM> and the channel layer <NUM> and piezoelectric effects at the interface between the barrier layer <NUM> and the channel layer <NUM>, a two dimensional electron gas (2DEG) is induced in the channel layer <NUM> at a junction between the channel layer <NUM> and the barrier layer <NUM>. The 2DEG acts as a highly conductive layer that allows conduction between the source and drain regions of the device that are beneath a source contact segment <NUM> and a drain contact <NUM>, respectively. The source contact <NUM> and the drain contact <NUM> are formed on the barrier layer <NUM>. A gate finger <NUM> is formed on the barrier layer <NUM> between the drain contact <NUM> and the source contact <NUM>. The source bus <NUM> extends over the source contacts <NUM>, drain contacts <NUM> and gate fingers <NUM>. The source contacts <NUM> physically and electrically connect to the source bus <NUM> through respective vertical contact plugs <NUM> that penetrate the first interlayer insulating layer <NUM>.

The material of the gate fingers <NUM> may be chosen based on the composition of the barrier layer <NUM>. In certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, W and/or WSiN. The drain contacts <NUM> and source contacts <NUM> may, for example, include a metal, such as TiAlN, that can form an ohmic contact to GaN and/or AlGaN.

While cross-sectional diagrams are not provided for various of the other semiconductor devices according to embodiments of the present invention that are disclosed herein, it will be appreciated that each of those devices may have the same general semiconductor structure <NUM> as shown in <FIG>. Particular embodiments may have specific variations, such as changes in doping concentrations or recesses in the barrier layer <NUM>, as described herein. It will also be appreciated that any of the disclosed embodiments may include additional layers such as, for example, buffer layers or the like that are not shown in <FIG>.

<FIG> is a cross-sectional diagram taken along line 8B-8B of <FIG> that shows a cross-section of the multi-cell semiconductor device <NUM> of <FIG> taken in the y-direction. The semiconductor device <NUM> includes the above-described semiconductor structure <NUM> that includes a substrate <NUM>, a channel layer <NUM>, and a barrier layer <NUM>. The gate finger <NUM> extends along the semiconductor structure in the y-direction. As shown in <FIG>, the upper surface of the barrier layer <NUM> may be recessed on the right side of the semiconductor structure <NUM>. The gate finger <NUM> may have a consistent thickness in the z-direction. However, because of the recess <NUM> in the barrier layer <NUM>, a height of the bottom surface of the first half <NUM>-<NUM> of gate finger <NUM> may be closer to the channel layer <NUM> than is a bottom surface of the second half <NUM>-<NUM> of gate finger <NUM>. As a result, the threshold voltage value VTH-<NUM> for the first half <NUM>-<NUM> of each gate finger <NUM> may be less than the threshold voltage value VTH-<NUM> for the second half <NUM>-<NUM> of each gate finger <NUM>.

The barrier layer <NUM> may be recessed so that a top surface of the portion of the barrier layer <NUM> that is under the first half <NUM>-<NUM> of each gate finger <NUM> may be lower in the z-direction than the top surface of the portion of the barrier layer <NUM> that is under the second half <NUM>-<NUM> of each gate finger <NUM> by, for example, between <NUM> and <NUM>. This distance may be referred to herein as the "depth" of the recess <NUM>. The depth of the recess <NUM> may be chosen to obtain a desired amount of difference between the first and second threshold voltage values VTH-<NUM>, VTH-<NUM>.

<FIG> is a schematic plan view of a multi-cell semiconductor device <NUM> according to further embodiments of the present invention. The semiconductor device <NUM> combines aspects of the semiconductor device <NUM> of <FIG> and the semiconductor device <NUM> of <FIG>. As shown in <FIG>, the semiconductor device <NUM> includes a plurality of gate fingers <NUM>. The gate fingers <NUM> may include first gate fingers 716a and second gate fingers 716b. The gate fingers 716a may be in a first region <NUM><NUM> of the semiconductor structure <NUM>, and the gate fingers 716b may be in a second region <NUM><NUM> of the semiconductor structure <NUM>. The gate fingers 716a may each be part of a unit cell transistor 740a, and the gate fingers 716b may each be part of a unit cell transistor 740b. Each unit cell transistor 740a is designed to have two different threshold voltage values along the width thereof. In particular, a first half <NUM>-<NUM> of each unit cell transistor 740a may have a first threshold voltage value VTH-<NUM> and the second half <NUM>-<NUM> of each unit cell transistor 740a may have a second threshold voltage value VTH-<NUM>.

In the second region <NUM><NUM>, each unit cell transistor 740b is similarly designed to have two different threshold voltage values along the width thereof. In particular, a first half <NUM>-<NUM> of each unit cell transistor 740b may have a third threshold voltage value VTH-<NUM> and the second half <NUM>-<NUM> of each unit cell transistor 740b may have a fourth threshold voltage value VTH-<NUM>. The first through fourth threshold voltage values VTH-<NUM> through VTH-<NUM> may comprise different threshold voltage values.

It will be appreciated that which particular unit cell transistors, and/or portions thereof, that have the different threshold voltage values may be arbitrarily selected. Thus, while the graphs of <FIG> and the plan views of <FIG>, <FIG> and <FIG> illustrate multi-cell semiconductor devices that have unit cell transistors with threshold voltages that monotonically increase (either discretely or continuously) along the x-direction in the figures, embodiments of the present invention are not limited thereto. This is shown schematically with reference to <FIG>, which are schematic graphs illustrating the threshold voltage variation in multi-cell semiconductor devices according to further embodiments of the present invention.

As shown in <FIG>, in an embodiment in accordance with the present invention, a first subset of the unit cell transistors are designed to have a first threshold voltage value VTH-<NUM>, a second subset of the unit cell transistors are designed to have a second threshold voltage value VTH-<NUM>, and a third subset of the unit cell transistors are designed to have a third threshold voltage value VTH-<NUM>. The first subset of the unit cell transistors is on the left hand side of the transistor, the second subset of the unit cell transistors is in the middle of the transistor, and the third subset of the unit cell transistors is on the right hand side of the transistor. As shown in <FIG>, the first threshold voltage value VTH-<NUM> is the highest value, the second threshold voltage value VTH-<NUM> is the lowest threshold voltage value, and the third threshold voltage value VTH-<NUM> is an intermediate threshold voltage value.

Referring next to <FIG>, it can be seen that in another example embodiment that does not form part of the present invention, a similar approach may be taken in a multi-cell semiconductor device in which every unit cell transistors has a different threshold voltage value. In the embodiment of <FIG>, the unit cell transistors are divided into three subsets of adjacent unit cell transistors, where each subset of unit cell transistors has monotonically increasing threshold voltage values. While <FIG> shows that the unit cell transistors may be divided into three subsets of adjacent unit cell transistors, it will be appreciated that more or fewer subsets may be provided.

Referring next to <FIG>, in yet another example embodiment that does not form part of the present invention, a multi-cell semiconductor device may have subsets of adjacent unit cell transistors that have monotonically increasing threshold voltage values as well as subsets of adjacent unit cell transistors that have monotonically decreasing threshold voltage values.

It will be appreciated that <FIG> show three of many possible designs. In the extreme, a semiconductor device may have a large number of unit cell transistors (e.g., <NUM>), each of which has a different threshold voltage value, where the unit cell transistors are randomly distributed throughout the device. It will also be appreciated that the same sorts of variation may be done along the width of each unit cell transistor.

As discussed above with reference to <FIG>, one technique for varying the threshold voltage in different regions of the transistors according to embodiments of the present invention is to change the thickness of the barrier layer under portions of some or all of the gate fingers. This technique may be used, for example, to form the semiconductor devices <NUM> and <NUM> of <FIG> and <FIG>, respectively. Similarly, the thickness of the barrier layer may be varied underneath different subsets of the unit cell transistors. Such a technique may be used to form the semiconductor devices <NUM>, <NUM> and <NUM> of <FIG>, respectively. These two techniques may be combined to form the semiconductor device <NUM> of <FIG>. It will be appreciated, however, that other techniques may be used to vary the threshold voltage in different regions of the semiconductor devices according to embodiments of the present invention.

For example, referring to <FIG>, according to further embodiments that do not form part of the present invention, the threshold voltage may be varied by using different metals or metal alloys to form different gate fingers and/or different portions of the same gate finger <NUM>. As shown in <FIG>, a gate finger <NUM> is formed on the barrier layer <NUM>. The gate finger <NUM> extends along the y-direction, and is formed using three different metals or metal alloys <NUM>, <NUM>, <NUM>. The different metals may be selected to achieve a desired variation in the threshold voltages under the three different sections of the gate finger <NUM>.

Referring next to <FIG>, in another approach, portions of the channel layer <NUM> may be doped to change the threshold voltage under different portions of the gate fingers <NUM>. As shown in <FIG>, portions <NUM>, <NUM>, <NUM> of the channel layer <NUM> that are under different portions of one or more of the gate fingers <NUM> may have different dopant concentrations. The doping concentrations (e.g., n-type dopants which may be, for example, silicon if the channel layer <NUM> comprises a gallium nitride based channel layer) may be selected to achieve a desired variation in the threshold voltages under the three different sections of the gate finger <NUM>. In some embodiments, p-type dopants could be used instead or a combination of n-type dopants in some portions and p-type dopants in other portions. It may be possible to achieve the same effect by doping sections of the barrier layer <NUM>.

Referring to <FIG>, in yet another approach, different portions of the barrier layer <NUM> may have different material compositions. For example, the barrier layer may comprise an AlxGa<NUM>-xN layer. The value of "x" may be different in each of various portions <NUM>, <NUM>, <NUM> of the barrier layer <NUM> that are under different portions of the gate fingers <NUM> in order to vary the threshold voltage value.

While, <FIG> and <FIG> show several example ways for varying the threshold voltage in different regions of a multi-gate finger transistor, it will be appreciated that embodiments of the present disclosure are not limited to these techniques. For example, in yet another approach, insulating layers having different thicknesses may be formed between the barrier layer between respective subsets of the gate fingers to provide unit cell transistors having different threshold voltage values. The same technique may be used along the width of the gate fingers to provide unit cell transistors that have varied threshold voltage values.

Referring next to <FIG>, a semiconductor wafer <NUM> is schematically illustrated that includes a plurality of multi-cell semiconductor devices <NUM> formed thereon. As shown in <FIG>, a large number of multi-cell semiconductor devices <NUM> may be formed on wafer <NUM>. In the depicted embodiment, approximately forty multi-cell semiconductor devices <NUM> fit along the diameter of the wafer <NUM>. More or fewer multi-cell semiconductor devices <NUM> may be provided. Moreover, while the individual multi-cell semiconductor devices <NUM> are illustrated in <FIG> as being square, it will be appreciated that more commonly each multi-cell semiconductor devices has a generally rectangular shape, with the length of adjacent sides varying by perhaps a factor of ten in example embodiments.

Due to variations in semiconductor growth and processing techniques, there typically is some variation in the threshold voltage across a semiconductor wafer. For example, a typical variation may be in the range of <NUM> to <NUM> volts. However, given the large number of multi-cell semiconductor devices <NUM> formed on the wafer <NUM>, the variation in threshold voltage due to processing variations within the footprint of any particular multi-cell semiconductor device will be much smaller, such as in the range of <NUM> to <NUM> volts. Such small variations do essentially nothing to spread out the device turn-on. As discussed above, pursuant to embodiments of the present invention, larger variations in the threshold voltage values may be deliberately engineered into the device design, such as variations on the order of <NUM> to <NUM> volts. Such variations may be used to spread out the threshold voltages over which different portions of a multi-cell semiconductor device turn on, thereby significantly lowering the peak third order transconductance values in order to provide improved linearity.

<FIG> is a schematic circuit diagram of the multi-cell semiconductor device <NUM> of <FIG>. As shown in <FIG>, the semiconductor device <NUM> includes a plurality of unit cell transistors <NUM>. The unit cell transistors <NUM> are electrically connected in parallel. A first subset of the unit cell transistors <NUM> may have a first threshold voltage value VTH-<NUM> while a second subset of the unit cell transistors <NUM> may have a second threshold voltage value VTH-<NUM> that is different than the first threshold voltage value VTH-<NUM>.

While engineering the threshold voltage is one way of improving the linearity of a multi-cell semiconductor device, it will be appreciated that the same effect may be achieved by applying different gate voltages to different portions of the device. <FIG> schematically illustrates this approach.

In particular, as shown in <FIG>, according to further embodiments of the present invention, different threshold voltages may be applied to different portions of a semiconductor device in order to smooth out the third order transconductance at device turn-on in order to provide improved linearity. As shown in <FIG>, a semiconductor device <NUM> according to embodiments of the present invention may include a conventional semiconductor device such as the semiconductor device <NUM> of <FIG>. As described above with reference to <FIG>, and as shown in circuit diagram format in <FIG>, the conventional semiconductor device <NUM> may include a plurality of unit cell transistors <NUM> that are formed on a common semiconductor structure and that are electrically connected in parallel. Each unit cell transistor <NUM> may include a gate finger. The threshold voltage may be the same along the width of each gate finger, and each unit cell transistor <NUM> may have the same threshold voltage.

As described above, the conventional semiconductor device <NUM> may exhibit large third order transconductance values at device turn-on as all of the unit cell transistors <NUM> will turn on to the same degree in response to application of a threshold voltage. In order to avoid this, the semiconductor device <NUM> further includes a voltage divider circuit <NUM>. The voltage divider circuit <NUM> may receive a voltage signal at an input thereof and may output a plurality of output voltage signals in response thereto. Each output voltage signal may have a different value. In the depicted embodiment, the voltage divider <NUM> has two outputs, but the voltage divider <NUM> may have more than two outputs in other embodiments.

As is also shown in <FIG>, each output of the voltage divider <NUM> may be coupled to a subset of the unit cell transistors <NUM> and applied to the gate fingers thereof. Thus, the gate fingers of a first subset of the unit cell transistors <NUM> receive the first output voltage signal from the voltage divider <NUM>, and the gate fingers of a second subset of the unit cell transistors <NUM> receive the second output voltage signal from the voltage divider <NUM>. The first and second output voltage signals of the voltage divider <NUM> may differ, for example, by at least <NUM> volts. In some embodiments, the first and second output voltage signals of the voltage divider <NUM> may differ, for example, by at least <NUM> volts. In other embodiments, the first and second output voltage signals of the voltage divider <NUM> may differ, for example, by at least <NUM> volts. In still other embodiments, the first and second output voltage signals of the voltage divider <NUM> may differ, for example, by between <NUM> and <NUM> volts. Since the gate fingers of he first and second subsets of unit cell transistors <NUM> receive different voltages, the unit cell transistors <NUM> in these subsets may turn on at different degrees. As described above, by spreading the turn-on voltage for various groups of unit cell transistors, the peak third order transconductance value may be reduced. If the voltage divider <NUM> has more than two outputs, then the unit cell transistors <NUM> of semiconductor device <NUM> may be divided into more than two subgroups, with each subgroup receiving one of the outputs of the voltage divider.

<FIG> is a graph illustrating the transconductance and the third order transconductance as a function of the applied threshold voltage for the semiconductor device <NUM> of <FIG> (the dotted lines in <FIG>) as compared to a conventional device (the solid lines in <FIG>). As shown in <FIG>, the peak third order transconductance value is reduced in half as compared to the conventional device.

<FIG> is a circuit diagram that schematically illustrates how a voltage divider may be implemented on the wafer in order to implement a semiconductor device <NUM>' that is similar to the semiconductor device <NUM> of <FIG>. As shown in <FIG>, a voltage divider circuit <NUM>' may be implemented using a series of resistors <NUM> that are disposed between the gate fingers of the unit cell transistors <NUM> of the semiconductor device <NUM> of <FIG>. The resistors <NUM> may be sized to create differences in the voltage applied to the gate fingers of adjacent unit cell transistors <NUM> in response to application of a voltage to the gate. In the embodiment of <FIG>, a total of four unit cell transistors <NUM> are shown by way of example, and the voltage divider <NUM>'. As a result, a different voltage will be applied to the gate fingers of the respective unit cell transistors <NUM> in response to application of a voltage to the gate (i.e., in the embodiment of <FIG>, every unit cell transistor <NUM> receives a different gate voltage). It will be appreciated that in other embodiments subsets of the gate fingers may receive the same gate voltages. For example, in another embodiment, each unit cell transistor <NUM> in <FIG> could be replaced with a two, three, four or more unit cell transistors <NUM> that are disposed in parallel. In such a device, the unit cell transistors <NUM> would turn-on at four different rates (degrees) in response to application of a gate voltage.

Inductors <NUM> may be provided for DC coupling and by-pass capacitors <NUM> may be added for RF decoupling. The resistors <NUM> may be formed on wafer by, for example, depositing conductive materials that have a different (higher) resistance than the remainder of the conductive lines or by changing the properties of selected portions of the conductive lines (e.g., by oxidization). Such techniques for forming on-wafer resistors are well-known in the art. The inductors <NUM> may also be implemented on wafer. For example, the inductors <NUM> may be implemented as meandered conductive lines on the wafer. In the depicted embodiment, the capacitors <NUM> are formed off of the wafer.

<FIG> is a schematic circuit diagram of a semiconductor device <NUM>" according to further embodiments that do not form part of the present invention, that includes a voltage divider that is partially implemented on-wafer. As shown in <FIG>, the semiconductor device <NUM>" is very similar to the semiconductor device <NUM>' of <FIG>, except that the inductors <NUM> of the voltage divider <NUM>" of semiconductor <NUM>" are implemented off the wafer. Such an implementation may be advantageous in some embodiments because the size of the necessary inductance may be large in some cases, which may make it difficult to implement on the wafer, and/or because the associated loss may be reduced if the inductors <NUM> are implemented separately off the wafer (as are the capacitors <NUM>). As the semiconductor device <NUM>" otherwise is identical to the semiconductor device <NUM>' of <FIG>, further description thereof will be omitted.

Embodiments of the present invention may be particularly well suited for use in connection with Group III-nitride based high electron mobility transistor (HEMT) devices. As used herein, the term "Group III nitride" refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements.

In particular embodiments that do not form part of the present invention, the substrate <NUM> may be a semi-insulating silicon carbide (SiC) substrate that may be, for example, <NUM> polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, <NUM>, and 15R polytypes.

Optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate <NUM> beneath the channel layer <NUM>. For example, an AlN buffer layer may be included to provide an appropriate crystal structure transition between the silicon carbide substrate and the remainder of the device. Additionally, strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned <CIT>, and entitled "Strain Balanced Nitride Hetrojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," the disclosure of which is incorporated herein by reference as if set forth fully herein. Moreover, one or more capping layers, such as SiN capping layers, may be provided on the barrier layer <NUM>.

Silicon carbide has a much closer crystal lattice match to Group III nitrides than does sapphire (Al<NUM>O<NUM>), which is a very common substrate material for Group III nitride devices. The closer lattice match of SiC may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a very high thermal conductivity so that the total output power of Group III nitride devices on silicon carbide is, typically, not as limited by thermal dissipation of the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance. Appropriate SiC substrates are manufactured by, for example, Cree, Inc. , of Durham, N. , the assignee of the present invention.

Although silicon carbide may be used as a substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed.

In some embodimenta that do not form part of the present invention, the channel layer <NUM> is a Group III-nitride, such as AlxGa<NUM>-xN where <NUM>≦x<<NUM>, provided that the energy of the conduction band edge of the channel layer <NUM> is less than the energy of the conduction band edge of the barrier layer <NUM> at the interface between the channel and barrier layers. In certain embodiments of the present invention, x=<NUM>, indicating that the channel layer <NUM> is GaN. The channel layer <NUM> may also be other Group III-nitrides such as InGaN, AlInGaN or the like. The channel layer <NUM> may be undoped or unintentionally doped and may be grown to a thickness of greater than about <NUM>Å. The channel layer <NUM> may also be a multilayer structure, such as a superlattice or combinations of GaN, AlGaN or the like.

The channel layer <NUM> may have a bandgap that is less than the bandgap of the barrier layer <NUM>, and the channel layer <NUM> may also have a larger electron affinity than the barrier layer <NUM>. In certain embodiments that do not form part of the present invention, the barrier layer <NUM> is AlN, AlInN, AlGaN or AlInGaN. In particular embodiments of the present invention, the barrier layer <NUM> is thick enough and has a high enough Al composition and doping to induce a significant carrier concentration at the interface between the channel layer <NUM> and the barrier layer <NUM>.

The barrier layer <NUM> may be a Group III-nitride and has a bandgap larger than that of the channel layer <NUM> and a smaller electron affinity than the channel layer <NUM>. Accordingly, in embodiments that do not form part of the present invention, the barrier layer <NUM> may include AlGaN, AlInGaN and/or AlN or combinations of layers thereof. The barrier layer <NUM> may, for example, be from about <NUM> to about <NUM> thick. In certain embodiments that do not form part of the present invention, the barrier layer <NUM> is undoped or doped with an n-type dopant to a concentration less than about <NUM><NUM> cm-<NUM>. In some embodiments that do not form part of the present invention, the barrier layer <NUM> is AlxGa<NUM>-xN where <NUM><x<<NUM>. In particular embodiments, the aluminum concentration is about <NUM>%. However, in other embodiments that do not form part of the present invention, the barrier layer <NUM> comprises AlGaN with an aluminum concentration of between about <NUM>% and about <NUM>%. In specific embodiments that do not form part of the present invention, the aluminum concentration is greater than about <NUM>%.

While embodiments of the present invention are illustrated with reference to a gallium nitride based HEMT structure, the present disclosure is not limited to such devices. Thus, embodiments of the present invention may be suitable for use in any field effect transistor, and can be used in devices that do or do not have unit cell structures. It will likewise be appreciated that the techniques disclosed herein may also be used in material systems other than gallium nitride based material systems.

It will be appreciated that features of the above-described embodiments may be combined in any way to create a plurality of additional embodiments.

Embodiments of the present invention are described above with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments described herein and/or pictured in the drawings. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

It will be further understood that the terms "comprises" "comprising," "includes" and/or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present.

Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

Claim 1:
A method of increasing the linearity of a semiconductor device (<NUM>), the method comprising:
forming a semiconductor device (<NUM>) that includes a plurality of unit cell (<NUM>) transistors on a common semiconductor structure (<NUM>), the unit cell (<NUM>) transistors electrically connected in parallel, and each of the unit cell (<NUM>) transistors includes a respective gate finger (<NUM>),
applying one or more voltage signals to the respective gate fingers (<NUM>) of the unit cell (<NUM>) transistors in order to turn on different portions of a 2DEG channel of the semiconductor device (<NUM>) at respective different levels of current flow,
wherein the semiconductor structure (<NUM>) includes a gallium nitride based channel layer (<NUM>) and a gallium nitride based barrier layer (<NUM>) on the gallium nitride based channel layer (<NUM>), and
wherein the gate fingers (<NUM>) extend in parallel to one another,
wherein the unit cell (<NUM>) transistors are divided into a plurality of groups (<NUM><NUM>, <NUM><NUM>), each of the groups includes at least five unit cell (<NUM>) transistors, wherein the threshold voltages of the unit cell (<NUM>) transistors within each of the groups are within <NUM> volts of each other, and,
wherein each of the groups includes the same number of unit cell (<NUM>) transistors.