Patent Description:
A semiconductor device having a semiconductor chip such as a metal oxide semiconductor field effect transistor (MOSFET) is used for applications such as power conversion. For example, when semiconductor device described above is a vertical MOSFET, a source electrode provided on an upper surface of a semiconductor chip is connected to a connector provided on MOSFET, for example. Prior art is disclosed in <CIT>.

Note that in the following description, the same members and the like are denoted by the same reference numerals, and description of members and the like once described is appropriately omitted.

In this specification, in order to illustrate the positional relationship of parts and the like, the upward direction of the drawings may be referred to as "upper", and the downward direction of the drawings may be referred to as "lower". Here, the terms "up" and "down" do not necessarily indicate a relationship with the direction of gravity.

A semiconductor device of embodiments includes: a first connector including a first plate having a first upper surface and a first terminal connected to the first plate, a first plate including a second plate and a third plate, a plate thickness of the second plate being thinner than a plate thickness of the third plate, the third plate being provided between the second plate and the first terminal; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip; a second connector provided on the semiconductor chip, a third connector, the first plate being provided between the first terminal and the third connector; a second bonding material provided between the second connector and the semiconductor chip; and a third bonding material provided between the second connector and the third connector.

<FIG> is a schematic top view of a semiconductor device <NUM> according to the embodiment. <FIG> is a schematic cross-sectional view of the semiconductor device <NUM> of the embodiment. <FIG> is a schematic view of a cross section taken along line A-A' in <FIG>.

With reference to <FIG> and <FIG>, the semiconductor device <NUM> of the embodiment is explained.

A drain connector (die pad, an example of the first connector) <NUM> is a member containing a conductive material such as Cu (copper), and a semiconductor chip <NUM> is disposed on the drain connector <NUM>. The drain connector <NUM> has a first plate (an example of a plate) <NUM> and drain terminals (the drain terminal is an example of a first terminal) <NUM>. The first plate <NUM> has a bottom surface <NUM> and a first upper surface <NUM>. The drain terminal <NUM> is connected to the first plate <NUM>. The drain terminal <NUM> is used to connect the semiconductor chip <NUM> and an external circuit (not shown).

Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The bottom surface <NUM> and the first upper surface <NUM> are disposed parallel to the XY plane. The drain terminal <NUM> is provided on the Y-direction side of the first plate <NUM>.

The first plate <NUM> has a first plate portion (an example of a second plate) 3a and a second plate portion (an example of a third plate) 3b. The second plate portion 3b is provided between the first plate portion 3a and the drain terminal <NUM>. A film thickness t<NUM> of the first plate portion 3a of the first plate <NUM> is thinner than a film thickness t<NUM> of the second plate portion 3b of the first plate <NUM>. Here, the film thickness t<NUM> and the film thickness t<NUM> are measured perpendicular to the first upper surface <NUM>.

For example, the first upper surface <NUM> has a slope <NUM> on the first upper surface <NUM>. The slope <NUM> is provided so as to be lower from the second plate portion 3b toward the first plate portion 3a. The slope <NUM> has a second upper surface <NUM>.

The angle θ formed by the second upper surface <NUM> and the first upper surface <NUM> is preferably <NUM> degrees or more and <NUM> degrees or less. In the figure of the embodiment, in order to illustrate slope <NUM> easily, it is illustrated with θ greater than <NUM> degrees.

The semiconductor chip <NUM> is provided on (above) the first upper surface <NUM> of the drain connector <NUM> or on the slope <NUM> of the drain connector <NUM>. The semiconductor chip <NUM> is, for example, a chip in which the vertical MOSFET or an IGBT (Insulated Gate Bipolar Transistor) or the like is provided on a semiconductor substrate such as a Si (silicon) substrate, an SiC (silicon carbide) substrate, a GaAs (gallium arsenide) substrate, or a GaN (gallium nitride) substrate.

As shown in <FIG>, the semiconductor chip <NUM> of the embodiment has a protrusion 11d. The semiconductor chip <NUM> of the embodiment has a convex shape on top. In the semiconductor device <NUM>, the protrusion 11d is disposed so as to be convex upward. In other words, the protrusion 11d has a convex shape on the second metal film (source electrode) <NUM> side. That is, the semiconductor chip <NUM> has a convex shape on the side where a second connector <NUM> is provided. Note that the semiconductor chip <NUM> which does not have an upwardly convex configuration can be preferably used in semiconductor device <NUM> of the embodiment.

The semiconductor chip <NUM> has a third upper surface 11a. The third upper surface 11a has a first side 11b and a second side 11c facing the first side 11b. When viewed from above, the first side 11b is provided between the second side 11c and the third connector <NUM>.

A first bonding material <NUM> is provided between the first upper surface <NUM> and the semiconductor chip <NUM>. When the first upper surface <NUM> has the slope <NUM>, the first bonding material <NUM> is provided between the slope <NUM> and the semiconductor chip <NUM>. The first bonding material <NUM> joins the first upper surface <NUM> or slope <NUM> and the semiconductor chip <NUM>. For example, when the semiconductor chip <NUM> is provided with the MOSFET, the first bonding material <NUM> joins the first upper surface <NUM> or the slope <NUM> and the drain electrode (not shown) of the semiconductor chip <NUM>.

The area of the slope <NUM> when viewed from above is preferably larger than the area of the semiconductor chip <NUM> when viewed from above.

Incidentally, the slope <NUM> may be provided on the entire surface on the first upper surface <NUM>, or the slope <NUM> may be provided on a portion of the first upper surface <NUM>.

The first bonding material <NUM> may have a void <NUM> in the first bonding material <NUM>. In <FIG>, a void 72a and a void 72b are shown.

The first metal film <NUM> is provided on the semiconductor chip <NUM>. The first metal film <NUM> includes, for example, Al (aluminum).

An insulating film <NUM> is provided on the first metal film <NUM>. For example, the insulating film <NUM> is provided on the end of the semiconductor chip <NUM> and on the end of the first metal film <NUM>. The insulating film <NUM> includes insulating materials such as polyimides.

A second metal film <NUM> is provided on the first metal film <NUM>. The second metal film <NUM> is surrounded by the insulating film <NUM> on the first metal film <NUM>. The second metal film <NUM> includes, for example, Ni and Au.

For example, when the semiconductor chip <NUM> is provided with the MOSFET, the first metal film <NUM> and the second metal film <NUM> correspond to the source electrode of the MOSFET.

A third connector (an example of a first post) <NUM> has a second plate <NUM> and source terminals (the source terminal is an example of a second terminal) <NUM>. The third connector <NUM> includes a conductive material such as Cu. The third connector <NUM> is used for connecting the semiconductor chip <NUM> and an external circuit (not shown). Here, the first plate <NUM> is provided between the drain terminal <NUM> and the source terminal <NUM>. Further, the second plate <NUM> is, for example, provided between the source terminal <NUM> and the first plate <NUM>.

A fourth connector (an example of a second post) <NUM> has a third plate <NUM> and a gate terminal <NUM>. The fourth connector <NUM> includes a conductive material such as Cu. The fourth connector <NUM> is used for connecting the semiconductor chip <NUM> and an external circuit (not shown).

The second connector <NUM> includes a first end 51a and a second end 51b. The second connector <NUM> includes, for example, a conductive material such as Cu. Incidentally, the surface of the second connector <NUM> may be plated by a material containing, for example, Sn. The first end 51a is provided above the first metal film <NUM>. The second end 51b is provided on the second plate <NUM>.

A second bonding material <NUM> is provided on the second metal film <NUM>. The second bonding material <NUM> is provided between the second metal film <NUM> and the first end 51a. The second bonding material <NUM> joins the first end 51a and the second metal film <NUM>.

The second bonding material <NUM> may have a void (bubble) <NUM> in the second bonding material <NUM>. In <FIG>, a void 22a and a void 22b are shown.

The diameter of the void <NUM> is preferably <NUM> or less. It is further preferable that the void <NUM> has a diameter of 500pm or less.

The third bonding material <NUM> is provided between the second plate <NUM> and the second end 51b. The third bonding material <NUM> joins the second plate <NUM> and the second end <NUM>.

The fifth connector <NUM> has a third end 61a and a fourth end 61b. The fifth connector <NUM> includes, for example, a conductive material such as Cu. Incidentally, the surface of the fifth connector <NUM> may be plated by a material containing, for example, Sn. The third end 61a is electrically connected to the semiconductor chip <NUM> via a fourth bonding material <NUM> provided on the semiconductor chip <NUM>. Below the fourth bonding material <NUM>, for example, a gate electrode (not shown) of the semiconductor chip <NUM> is provided.

The fifth bonding material <NUM> is provided between the third plate <NUM> and the fourth end 61b. The fifth bonding material <NUM> joins the third plate <NUM> and the fourth end 61b.

When the semiconductor chip <NUM> has the protrusion 11d, the film thickness of the first bonding material <NUM> near the center of the semiconductor chip <NUM> is thick. On the other hand, the film thickness of the first bonding material <NUM> near the end of the semiconductor chip <NUM> is thin. Here, the film thickness of the first bonding material <NUM> is measured perpendicular to the first upper surface <NUM>.

When the semiconductor chip <NUM> has the protrusion 11d, the film thickness of the second bonding material <NUM> near the center of the semiconductor chip <NUM> is thin. On the other hand, the film thickness of the second bonding material <NUM> near the end of semiconductor chip <NUM> is thick. Here, the film thickness of the second bonding material is measured perpendicular to the first upper surface <NUM>.

As the first bonding material <NUM>, the second bonding material <NUM>, the third bonding material <NUM>, the fourth bonding material <NUM>, and the fifth bonding material <NUM>, for example, solder containing Pb (lead) and Sn (tin), solder containing Pb, Ag (silver), and Sn (tin), solder containing Sn and Sb (antimony), solder containing Au (gold) and Sn, solder containing Au and Si, or solder containing Au and Ge (germanium) can be preferably used.

<FIG> are schematic cross-sectional views of main portions of the semiconductor device according to the embodiment.

As shown in <FIG>, the distance L<NUM> between the first side 11b and the bottom surface <NUM> is shorter than the distance L<NUM> between the second side 11c and the bottom surface <NUM>. <FIG> shows that a film thickness t<NUM> of the second bonding material <NUM> in the vicinity of the first side 11b is thinner than a film thickness t<NUM> of the second bonding material <NUM> in the vicinity of the second side 11c. <FIG> shows that the film thickness t<NUM> of the second bonding material <NUM> in the vicinity of the first side 11b is thicker than the film thickness t<NUM> of the second bonding material <NUM> in the vicinity of the second side 11c. Both cases above can be preferably used as the semiconductor device <NUM> of the embodiment. Here, the film thickness t<NUM> and the film thickness t<NUM> are measured perpendicular to the first upper surface <NUM>.

The manufacturing method of the semiconductor device <NUM> of the embodiment is described. First, the drain connector <NUM>, the third connector <NUM>, and the fourth connector <NUM> are disposed on the reflow plate. Then, a cream solder to be the first bonding material <NUM> is applied on the drain connector <NUM>. Next, the semiconductor chip <NUM> is disposed on the cream solder to be the first bonding material <NUM>. Next, on the semiconductor chip <NUM>, a creamed solder to be the second bonding material <NUM> is applied. Next, on the second plate <NUM> of the third connector <NUM>, a cream solder to be the third bonding material <NUM> is applied. Next, on the gate electrode of the semiconductor chip <NUM>, a cream solder to be the fourth bonding material <NUM> is applied. Next, on the third plate <NUM> of the fourth connector <NUM>, a cream solder to be the fifth bonding material <NUM> is applied. Next, the first end 51a of the second connector <NUM> is disposed on the cream solder to be second bonding material <NUM>. Next, the second end 51b of the second connector <NUM> is disposed on the cream solder to be the third bonding material <NUM>. Next, the third end 61a of the fifth connector <NUM> is disposed on the cream solder to be the fourth bonding material <NUM>. Next, the fourth end 61b of the fifth connector <NUM> is disposed on the cream solder to be the fifth bonding material <NUM>. Next, the cream solders are heated by a vacuum reflow heat treatment and melted. Next, the cream solders are solidified by cooling. Thus, the first bonding material <NUM>, the second bonding material <NUM>, the third bonding material <NUM>, the fourth bonding material <NUM>, and the fifth bonding material <NUM> are formed. Thus, the semiconductor device <NUM> of the embodiment is obtained. The manufacturing method of the semiconductor device <NUM> of the embodiment are not limited to those described above.

Next, the operation and effects of semiconductor device of the embodiment will be described.

<FIG> is a schematic sectional view of a semiconductor device <NUM> as a first comparative embodiment of the embodiment. The semiconductor chip <NUM> does not include the protrusion 11d. Further, in the semiconductor device <NUM>, the slope <NUM> is not provided.

<FIG> is a schematic sectional view of a semiconductor device <NUM> as a second comparative embodiment of the embodiment. The semiconductor chip <NUM> has the protrusion 11d. Further, in the semiconductor device <NUM>, the slope <NUM> is not provided.

It is preferable to reduce the film thickness of the semiconductor chip. For example, if the semiconductor chip is provided with a vertical MOSFET, it is preferable that the film thickness of the semiconductor chip is thin in order to reduce the on-resistance of MOSFET. However, in this case, the film thickness of the drain electrode provided on the bottom surface of the semiconductor chip and the film thickness of the source electrode provided on the upper surface of the semiconductor chip becomes relatively thick. Therefore, the semiconductor chip becomes susceptible to the effects of the stress of the drain electrode and the source electrode. In particular, the semiconductor chip often warps upwards convexly. Therefore, how to connect the connectors to such semiconductor chip has become an issue.

In addition, during the production of the semiconductor device, the cream solder is melted and solidified by vacuum-reflow heat treatment. Here, when the cream solder melts, bubbles (void) may enter the inside of the cream solder. The part with such void is more thermally resistive than the part of the surrounding bonding material. Therefore, how to remove the void has become an issue.

Since the third connector <NUM> is provided, evacuation conductance between the semiconductor chip <NUM> and the third connector <NUM> is reduced in the vacuum-reflow, and the void 22a of the second bonding material <NUM> near the third connector <NUM> is hardly pulled out. In particular, when the semiconductor chip <NUM> has a protrusion 11d, the gap between the semiconductor chip <NUM> and the second connector <NUM> in the side close to the third connector <NUM> is narrowed. Thus, the void is hardly pulled out further.

Further, when the semiconductor chip <NUM> has the protrusion 11d, compared with the case when the semiconductor chip <NUM> does not have the protrusion 11d, the film thickness of the first bonding material <NUM> and the film thickness of the second bonding material <NUM> become uneven. As described above, when the thickness of the bonding material is uneven, the bonding material is easily cracked due to thermal cycling applied to the semiconductor device <NUM> due to heating and cooling of the semiconductor device <NUM>.

Therefore, in the semiconductor device <NUM>, the drain connector <NUM> whose plate thickness of the first plate portion 3a of first plate <NUM> is thinner than the plate thickness of the second plate portion 3b provided between the first plate portion 3a and the drain connector <NUM> is used. Thus, it is possible to equalize the gap between the semiconductor chip <NUM> and the second connector <NUM> more. Therefore, when performing vacuum-reflow, the void formed in the second bonding material <NUM> is likely to come off.

Further, since the heat capacity of the first plate portion 3a is smaller than the heat capacity of the second plate portion 3b, the second bonding material <NUM> provided on the side of the first plate portion 3a is melted earlier than the second bonding material <NUM> provided on the side of the second plate portion 3b. This makes it difficult to form the void on the side of the first plate portion 3a of the second bonding material <NUM>, that is, on the side close to the third connector <NUM>.

In addition, variations in the thickness of the second bonding material <NUM> can be reduced, and the thickness of the second bonding material <NUM> can be made more uniform. Therefore, cracks in the second bonding material <NUM> hardly enter.

The slope <NUM> can be easily and accurately formed using a mold. Further, the slope <NUM> can hold the semiconductor chip stably via the first bonding material <NUM>. Therefore, the slope <NUM> is preferably used in the semiconductor device <NUM> of the embodiment.

The area of the slope <NUM> when viewed from above is preferably larger than the area of the semiconductor chip <NUM> when viewed from above. This is because it is possible to hold the semiconductor chip <NUM> stably when the area of the slope <NUM> is larger.

The angle θ between the second upper surface <NUM> and the first upper surface <NUM> is preferably <NUM> degrees or more and <NUM> degrees or less. If θ is less than <NUM> degrees, since the gap between the semiconductor chip <NUM> and the second connector <NUM> is not sufficiently uniform, the void <NUM> formed within the second bonding material <NUM> is hardly pulled out. On the other hand, if θ is greater than <NUM> degrees, the film thickness of the second bonding material <NUM> closer to the drain terminal <NUM> becomes too thin, and it is difficult to pull out the void <NUM>.

The diameter of the void <NUM> is preferably <NUM> or less, in order to reduce the thermal resistance of semiconductor device <NUM> as much as possible.

<FIG> is a schematic cross-sectional view of a semiconductor device <NUM> as a third comparative embodiment of the embodiment. It is considered to make the thickness of the second bonding material <NUM> more uniform by connecting the connector extension <NUM> to the second end 51b. However, the cross-sectional area of the connector extension <NUM> in a plane parallel to the XY plane is small. Therefore, as in the semiconductor device <NUM> of the embodiment, it is preferable that the plate thickness of the first plate portion 3a of the first plate <NUM> is thinner than the plate thickness of the second plate portion 3b of the first plate <NUM> provided between the first plate portion 3a and the drain terminal <NUM>. This is because it is possible to ensure a larger cross-sectional area by using such drain connector <NUM>. Further, it is possible to improve the contact with the semiconductor chip <NUM>. Therefore, it is possible to reduce the thermal resistance of the semiconductor device.

Claim 1:
A semiconductor device (<NUM>), comprising:
a first connector (<NUM>) including a first plate (<NUM>) having a first upper surface (<NUM>) and a first terminal (<NUM>) connected to the first plate (<NUM>), a first plate (<NUM>) including a second plate (3a) and a third plate (3b), a plate thickness of the second plate (3a) being thinner than a plate thickness of the third plate(3b), the third plate (3b) being provided between the second plate (3a) and the first terminal (<NUM>);
a semiconductor chip (<NUM>) provided on the first upper surface (<NUM>);
a first bonding material (<NUM>) provided between the first upper surface (<NUM>) and the semiconductor chip (<NUM>);
a second connector (<NUM>) provided on the semiconductor chip (<NUM>),
a third connector (<NUM>), the first plate (<NUM>) being provided between the first terminal (<NUM>) and the third connector (<NUM>);
a second bonding material (<NUM>) provided between the second connector (<NUM>) and the semiconductor chip (<NUM>); and
a third bonding material (<NUM>) provided between the second connector (<NUM>) and the third connector (<NUM>).