Patent Description:
Integrated Photonics is considered to be one of the most important key technologies for a broad range of applications in many fields, such as health, environmental monitoring, telecom, datacom, transport, manufacturing, etc. Innovative products benefit from highly integrated photonic circuits comprising light sources (lasers), detectors and sensors as well as integrated electronics for driving those photonic components or processing the acquired signals. These integration efforts come together with a constant need for higher switching frequencies, especially in telecom.

One of the main obstacles to the dense and advanced integration of photonic and related electronic components into a single photonic integrated circuit (PIC) is the parasitic and detrimental thermal crosstalk effects between the integrated devices.

It is known by those skilled in the art, to realize thermal management of EIC-INTEGRATED PICs by means of a smart micro-thermoelectric coolers (pTECs) integrated circuit (TEIC) layer, sitting above a functional layer containing advanced electronic integrated circuits (EICs), allowing smaller footprint PIC and lower energy consumption.

Thus, considering the foregoing, there is growing interest in a smart thermal management solution consisting in a new approach. Documents <CIT>"Silicon photonics for terabit/s communication in data centers and exascale computers" and <CIT> give examples of photonic assemblies.

Various embodiments provide apparatuses to remedy some or all the disadvantages of the above identified prior art.

The embodiments and features described in this specification which, if any, would fall outside the scope of the claims are to be interpreted as useful examples for understanding the various embodiments.

The claimed invention provides an apparatus integrating an Electronic Integrated Circuit (EIC) and at least one photonic-integrated circuit (PIC), said apparatus further comprising:.

This apparatus allows the design and implementation of a common technology platform for various photonic integrated circuits (PICs) for various application areas such as fibre optic environmental sensing and very high-speed transceivers for the telecommunications and data communications industries, using either the coherent format or other wavelength division multiplexing systems (also called WDM systems).

Advantageously, the apparatus may further comprise an array of heat-dissipating fins (<NUM>) situated on the top side of the top wall of the lid.

Advantageously, the lid and, if applicable, the heat-dissipating fins may be made of a thermally conductive material, preferably consisting of a metal or silicon.

Advantageously, the Electronic Integrated circuit may further comprise at least one heat generating component that is an electric or electronic component from the Electronic Integrated Circuit (EIC), that is either positioned on the top side of the first substrate (i.e. the glass substrate) or on the bottom side of the first substrate.

The at least one heat generating component from the photonic-integrated circuit may be selected among usual III-V-based devices (such as laser active sections, SOAs, photodiodes or phase modulators) and Si-based devices (phase modulators, ring-resonators, Ge-based PDs).

Advantageously, the at least one heat generating component from the photonic-integrated circuit may comprise a III-V-based device.

Advantageously, according to a first specific embodiment of the claimed invention, said at least one photonic integrated circuit may comprise:.

The at least electrical interconnection plane may be a RF and/or DC inputs/outputs plane positioned on the upper side of said first substrate and/or said second electrical interconnection plane may be a RF and/or DC inputs/outputs plane.

Advantageously, the apparatus may further comprise an organic substrate being positioned beneath the first substrate.

Advantageously, according to a second specific embodiment of the claimed invention, the Electronic Integrated circuit may further comprise at least one heat generating component being an electric or electronic component from the Electronic Integrated Circuit (EIC)being positioned on the bottom side of the first substrate and electrically connected to said electrical interconnection plane by means of Through-Glass-Vias traversing the first substrate.

Some example embodiments are now described, by way of example only, and with reference to the accompanying drawings in which:.

The same reference number represents the same element or the same type of element on all drawings, unless stated otherwise.

<FIG> are described in more detail in the description which follows, given by way of indication. <FIG> illustrate various example embodiments of the apparatus, but without limiting the scope thereof.

It should be understood, however, that there is no intent to limit example embodiments to the forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

In the following description of the figures, schematic representations are non-limiting and serve only for the understanding.

<FIG> show several variant basic architectures of an apparatus integrating an electronic integrated circuit and at least one photonic integrated circuit.

In particular, <FIG> schematically represent two views of the apparatus according <NUM> to a first specific embodiment in which:.

The III-V-based die <NUM> from the PIC <NUM> and electric or electronic component <NUM> from the EIC are flip-chip bonded on the glass platform <NUM> through the pads (also called flip-chip balls) contacting the electrical interconnection plane <NUM>.

It is to be remarked that also other types of PICs can be part of such apparatus, e.g. PICs for transceiver applications, containing many types of photonic devices, including lasers (DFB, extended cavity tunable lasers, frequency combs etc.), optical amplifiers (SOAs), modulators (electro-absorption modulators, Mach-Zehnder modulators, ring-resonator modulators, etc.), photodetectors (any type of photodiodes), on top of passive devices (single mode waveguides, wave couplers, multimode interferometer couplers (MMIs), mode transition tapers, Bragg grating couplers or edge couplers for optical in/outs, etc.); PICs for quantum applications, containing many of the above mentioned photonic devices, plus high finesse optical filters, variable optical attenuators, cascaded ring resonators, etc.; PICs for optical switching and routing, containing many of the above-mentioned photonic devices, plus optical switches, passive waveguide crossings, etc. The above-mentioned PIC types are not exhaustive.

The lid <NUM> defines a lidded cavity <NUM> comprised between the top wall <NUM>, the side wall <NUM> and the SOI layer <NUM>, such that the III-V-based die <NUM>, the Si-based optical modulator and the EIC are inside this cavity, and the optical inputs/outputs <NUM> and the electrical inputs/outputs of the apparatus on the electrical interconnection plane <NUM> are outside the lidded cavity <NUM>,.

The lid <NUM> and the heat-dissipating fins <NUM> are preferably made of a thermally conductive material, such as a metal or silicon.

Metal vias <NUM> consisting of Through-Substrate-Vias hereinafter designated by TSV, traverse the silicon-on-insulator (SOI) layer <NUM> for electrically connecting the III-V-based device <NUM> and the Si-based optical modulator <NUM> to the EIC <NUM> via the electrical interconnection plane <NUM>.

Furthermore, the III-V laser die <NUM> is also electrically connected via such TSV metal vias. <FIG> depicts more in detail how secondary vias <NUM> traversing said III-V laser die <NUM> may be further needed to this end.

In addition an organic substrate <NUM> is present on the bottom surface of the glass platform <NUM>, to which it is attached by means of regularly spaced bumps or an underfill.

As one can observe from <FIG>, the apparatus according <NUM> to the first specific embodiment further comprises:.

As earlier mentioned, secondary vias <NUM> traversing said III-V laser die <NUM> are present for electrically connecting the III-V laser die to the TGV metal vias <NUM>.

A thermal conductive, yet electrical insulating thin layer (such as AlN) <NUM> may be positioned between this thermal management layer <NUM> (TEC) and the functional layer.

In some embodiments, the TEC may be needed to be electrically driven, via further electrical contacts and interconnections between the TEC <NUM> and the electrical interconnection layer on the upper surface of the glass platform <NUM>.

As to the electric or electronic component <NUM> from the EIC <NUM>, the apparatus according <NUM> to this first specific embodiment further comprises a third thermal interface (TIM) <NUM> being positioned between the bottom side of the top wall <NUM> of the lid <NUM> and the electric or electronic component <NUM>.

<FIG> schematically represent two views of the apparatus according to a second specific embodiment that differs from the first one (shown in <FIG>) in that it further comprises a second electrical interconnection plane <NUM>', in this embodiment used for providing the DC inputs/outputs, while the first interconnection plane is merely serving to guide the RF electrical input/output signals. The second interconnection plane <NUM>' is positioned on the bottom side of said first substrate <NUM> and electrically connected to the first interconnection plane for providing DC signals to the components by means of Through-Glass-Vias <NUM> traversing the glass platform <NUM>.

The TGVs <NUM> may be drilled in the glass substrate <NUM>. Since ordinary glass is used, cylindrical holes <NUM> can be drilled and filled with metal in order to provide DC signals to circuits from the second interconnection plane <NUM>' on the rear (down) side of the glass platform <NUM>.

This variant has the advantage of doubling the surface for electrical routing, which can help the decrease the overall footprint of the integrated circuits system. Indeed, due to larger (and increasing) number of devices in PICs and EICs, electrical routing fan-out and the global size of the integrated system is bounded by the peripheral electrical I/O pad distribution. Providing this pad distribution on two levels (at both sides of the glass platform) instead of only one level (only the upper surface as in the previous embodiment) does have the advantage of decreasing the global horizontal footprint of the whole system. For practical and obvious reasons, it is better to use the upper surface for RF routing and I/O pads <NUM> since this reduces the RF line length.

<FIG> schematically represent two views of the apparatus according to a third specific embodiment that differs from the first one (shown in <FIG>) in that an electric or electronic component <NUM> from the Electronic Integrated Circuit (EIC) is positioned on the bottom side of glass platform <NUM> (the thickness of which is comprised between <NUM> and <NUM> pm) and electrically connected to the electrical interconnection plane <NUM> by means of Through-Glass-Vias <NUM> traversing glass platform <NUM>.

In that configuration, the interconnection layer is a RF and DC inputs/outputs plane that is set on the upper side of the glass platform <NUM> to benefit from the low RF propagation loss. This configuration can present other advantages as the heat generating EICs <NUM> are further away from the temperature sensitive devices on the PIC <NUM>, the heat insulation is better in this third embodiment, than in the first and second embodiments. In this third embodiment, the SOI thickness is comprised between <NUM> and <NUM>.

Claim 1:
An apparatus (<NUM>) integrating an Electronic Integrated Circuit, EIC, (<NUM>) and at least one photonic-integrated circuit, PIC (<NUM>), said apparatus (<NUM>) further comprising:
• a first substrate (<NUM>) made of glass;
• an electrical interconnection plane (<NUM>) positioned on the upper side of said first substrate (<NUM>), for enabling electrical interconnection of the at least one PIC and the EIC with each other;
• at least one heat generating component (<NUM>, <NUM>) from the at least one photonic-integrated circuit (<NUM>), said at least one photonic-integrated circuit (<NUM>) being situated on top of a silicon-on-insulator SOI, layer (<NUM>), said photonic integrated circuit (<NUM>) being coupled to optical inputs/outputs (<NUM>) on top of said silicon-on-insulator, SOI, layer (<NUM>);
• metal vias (<NUM>) traversing the silicon-on-insulator, SOI, layer (<NUM>) electrically connecting the at least one heat generating component (<NUM>, <NUM>) of the photonic-integrated circuit (<NUM>) to the electrical interconnection plane (<NUM>);
the apparatus being characterized in further comprising - a lid (<NUM>) comprising a top wall (<NUM>) and a side wall (<NUM>) being in contact with the silicon-on-insulator, SOI, layer (<NUM>), said top wall (<NUM>) comprising an upper surface and a lower surface, said lid (<NUM>) defining a lidded cavity (<NUM>) comprised between the top wall (<NUM>), the side wall (<NUM>) and the SOI layer wherein said lid (<NUM>) is positioned on the silicon-on-insulator, SOI, layer (<NUM>) such that the optical inputs/outputs (<NUM>) of the at least one photonic integrated circuit (<NUM>) and electrical inputs/outputs of the electrical interconnection plane (<NUM>) are outside the lidded cavity (<NUM>), and said at least one heat generating component (<NUM>, <NUM>) from the at least one photonic-integrated circuit (<NUM>) is encapsulated within the lidded cavity (<NUM>).