Patent Description:
Semiconductor memory devices may be classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Non-volatile semiconductor memory devices retain data even when power is no longer supplied. Data stored in non-volatile semiconductor memory devices may be permanent or reprogrammable. Non-volatile semiconductor memory devices are used for storage of user data and storage of programs and microcode in a wide range of applications, such as computers, avionics, telecommunications, and consumer electronics.

A multi-step program operation may be performed to program data to memory cells. The multi-step program operation performs a plurality of program operations to narrow the distribution of threshold voltages corresponding to data values to be stored. That is, the multi-step program operation includes a coarse program operation that performs a multi-bit program operation that roughly forms a threshold voltage distribution, and a fine program operation that precisely collects the threshold voltage distribution formed by the coarse program operation. However, it may be difficult to read data without errors when only the coarse program operation is performed.

<CIT> discloses a method of operating a semiconductor memory system which includes: programming LSB data into a memory cell of a selected word line included in a memory block; storing MSB data to be programmed into the memory cell of the selected word line, from a controller into a page buffer; reading the programmed LSB data from the memory cell of the selected word line; performing an error correction code (ECC) operation on the read LSB data when a difference between a reference amount and an amount of bit line current, which flows through bit lines included in the memory block, does not fall in a predetermined range from a first current amount to a second current amount; and programming the MSB data stored in the page buffer into the memory cell of the selected word line based on the ECC-corrected LSB data.

According to an aspect of the present invention there is provided a method of operating a memory system according to claim <NUM>.

According to an aspect of the present invention there is provided a memory system according to claim <NUM>.

Optional features of the present invention are defined according to the dependent claims.

A memory system is disclosed herein that processes a read request even when only a first program operation is performed, and a method of operating the memory system.

Furthermore, a memory system is disclosed herein that provides a program speed that is faster than a coarse-fine program operation, and a method of operating such a memory system is also disclosed.

Features of the invention are set out in the claims.

Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Hereinafter, various embodiments will be described with reference to the accompanying drawings.

<FIG> is a diagram illustrating a memory system <NUM> according to an embodiment.

Referring to <FIG>, the memory system <NUM> may include a memory device <NUM> and a memory controller <NUM>.

The memory device <NUM> may include a memory cell array <NUM>, a control logic circuit <NUM>, a page buffer circuit <NUM>, and an error detector <NUM> (e.g., a logic circuit).

The memory cell array <NUM> includes word lines, bit lines, and memory cells each connected to each of the word lines and each of the bit lines. The memory cells may store data of at least one bit. A memory cell storing <NUM> bit may be referred to as a single level cell (SLC), a memory cell storing <NUM> bits may be referred to as a multi level cell (MLC), a memory cell storing <NUM> bits may be referred to as a triple level cell (TLC), and a memory cell storing <NUM> bits may be referred to as a quad level cell (QLC). The memory cells may be implemented as a non-volatile memory that stores data regardless of whether power is supplied thereto or a volatile memory that stores data while power is supplied thereto. A method of physically fuse-cutting using a laser or a method of electrically programming may be used to store data. For example, a memory implemented by memory cells may be dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), or resistive RAM (RRAM or ReRAM). In this case, the memory cell array <NUM> may be implemented in two dimensions or three dimensions. Memory cells connected to one word line may be referred to as a physical page, and data stored in the physical page may be referred to as a logical page. Because each memory cell may store a plurality of bits, a plurality of logical pages may be stored in one physical page. For example, when only one logical page is programmed into a physical page, the memory cell included in the physical page may be an SLC, and when only two logical pages are programmed into a physical page, the memory cell included in the physical page may be an MLC.

The page buffer circuit <NUM> may store data to be programmed into the memory cell array <NUM> or data read from the memory cell array <NUM>. The page buffer circuit <NUM> may include a plurality of page buffers respectively connected to a plurality of bit lines. Each of the plurality of page buffers may include a plurality of latches, and the plurality of latches may store data to be programmed into the memory cell array <NUM>.

The control logic circuit <NUM> may control all operations of the memory device <NUM>. According to an embodiment, the control logic circuit <NUM> performs a multi-step program operation. Hereinafter, a two-step program operation is mainly described, but a three-step or more program operation may be similarly performed. Also, hereinafter, a QLC program (or QLC programming operation), in which four logical pages are programmed into the memory cell array <NUM> through a two-step program operation, is described, but embodiments of the inventive concept are not limited thereto and may include an operation in which two, three, or five or more logical pages are programmed into the memory cell array <NUM>.

The control logic circuit <NUM> may perform a two-step program operation to store four logical pages in the memory cell array <NUM>. For example, during a first program operation, the control logic circuit <NUM> may perform a TLC program operation on three logical pages. The first program operation may be a fine program operation. During a second program operation, the control logic circuit <NUM> may perform a QLC program operation on four logical pages. The second program operation may be a fine program operation. Also, during the second program operation, the control logic circuit <NUM> may read, from the memory cell array <NUM>, three logical pages programmed by the first program operation. Furthermore, the control logic circuit <NUM> may program four logical pages into the memory cell array <NUM> based on three logical pages read into the page buffer circuit <NUM> and one logical page received from the memory controller <NUM>.

According to an embodiment, because three logical pages are obtained from the memory cell array <NUM> during the second program operation, a separate buffer memory to store the three logical pages may not be required. Accordingly, the size of a write buffer in the memory controller <NUM> or the memory device <NUM> may be reduced.

Furthermore, because only three logical pages are programmed during the first program operation, a faster program speed may be provided compared to a coarse-fine program method in which four logical pages are programmed in each of the first program operation and the second program operation.

Also, in the first program operation, because a fine program operation for three logical pages is performed, a read request for three logical pages may be processed even when only the first program operation has completed. When the first program operation is a coarse program operation, a distribution width of a threshold voltage distribution may be wide, and the number of errors in read data may increase due to overlap between distributions. Accordingly, a read request may not be processed. According to an embodiment, there is no need to wait until the second program operation has completed to process a read request, and thus, read performance may be improved.

The error detector <NUM> may detect an error in data stored in the page buffer circuit <NUM>. For example, the error detector <NUM> may include an error correction code (ECC) circuit, a cyclic redundancy check (CRC) circuit, or a checksum circuit.

In an embodiment, three logical pages are read from the memory cell array <NUM> to perform a second program operation. However, there may be an error in the three read logical pages. Accordingly, the error detector <NUM> may detect errors in one or more of the three logical pages and may correct the errors, thereby increasing the reliability of the two-step program operation. When the number of detected errors is greater than a reference number, the read three logical pages may be transferred to the memory controller <NUM>.

The memory controller <NUM> may control the operation of the memory device <NUM> by providing a command, data, or an address to the memory device <NUM>. The memory controller <NUM> according to an embodiment controls the memory device <NUM> to perform a two-step program operation on four logical pages. Specifically, the memory controller <NUM> may provide three logical pages to the memory device <NUM>, and may provide the remaining one logical page to the memory device <NUM> after a delay time elapses.

When receiving three logical pages from the memory device <NUM>, the memory controller <NUM> may perform error correction on the three logical pages to generate three error-corrected logical pages and transmit the three error-corrected logical pages to the memory device <NUM>.

According to an embodiment, because the memory device <NUM> includes the error detector <NUM>, when the number of errors in the three logical pages read from the memory cell array <NUM> is less than or equal to a reference number, the error detector <NUM> may correct the errors. Accordingly, the amount of data transmitted between the memory controller <NUM> and the memory device <NUM> for error correction may be reduced.

<FIG> and <FIG> are diagrams illustrating a two-step program operation according to an embodiment. Specifically, <FIG> illustrates an embodiment in which an error detector <NUM> corrects error bits (or bit errors) in three logical pages read from a memory cell array <NUM>, and <FIG> illustrates an embodiment in which the error detector <NUM> does not correct error bits in three logical pages read from the memory cell array <NUM>.

Referring to <FIG>, a memory controller <NUM> transmits three logical pages to a memory device <NUM> for a first program operation, and the three logical pages may be stored in a page buffer circuit <NUM> (Operation ①). For example, it may be the intent of the memory controller <NUM> to program four or more logical pages even though it only initially transmits three logical pages to the memory device <NUM>.

The three logical pages stored in the page buffer circuit <NUM> are programmed into the memory cell array <NUM> by the first program operation under control by a control logic circuit (i.e., the control logic circuit <NUM> in <FIG>) (Operation ②). The first program operation may be a fine program operation. The first program operation may program the three logical pages into a single physical page. In an embodiment, the first program operation is a multi-step program operation including a coarse program operation and a fine program operation. As a result of the first program operation, a threshold voltage distribution formed by the threshold voltages of memory cells into which the three logical pages are programmed may have a narrower distribution width than a threshold voltage distribution cause by performance of only a coarse program for the three logical pages.

The three logical pages stored in the memory cell array <NUM> are read into the page buffer circuit <NUM> (Operation ③). In an embodiment, when a first delay time elapses after three logical pages are programmed into the memory cell array <NUM>, the three logical pages are read from the memory cell array <NUM> to the page buffer circuit <NUM>. For example, a delay may be present between Operation ② and Operation ③.

The error detector <NUM> may detect a number of errors in the three read logical pages (Operation ④). For example, the error detector <NUM> may perform an operation to determine whether errors are present in the read logical pages and a count of these errors. When the number of detected errors is less than or equal to a reference number, the error detector <NUM> may correct the errors to generate three corrected logical pages. In an embodiment, the three read logical pages stored in the page buffer circuit <NUM> are overwritten with the three corrected logical pages.

The memory controller <NUM> transmits the remaining one logical page to the memory device <NUM> for a second program operation, and the one logical page may be stored in the page buffer circuit <NUM> (Operation ⑤). That is, three logical pages read from the memory cell array <NUM> and one logical page received from the memory controller <NUM> may be stored in the page buffer circuit <NUM>. In an embodiment, the remaining one logical page is transferred to the memory device <NUM> when a second delay time elapses after the three logical pages are transferred to the memory device <NUM>. For example, the three logical pages may be transferred together to the memory device <NUM>, the second delay time elapses, and then the remaining logical page may be transferred to the memory device <NUM>. In an embodiment, Operation ⑤ occurs after Operations ①, ②, and ③ complete or after Operations ①, ②, ③, and ④ complete. For example, when the original intent of the memory controller <NUM> was to program four logical pages, there is only one remaining logical page to transfer. However, had the memory controller <NUM> intended to program five logical pages, then Operation ⑤ would have caused the memory controller <NUM> to transfer a remaining two logical pages to the memory device.

The four logical pages stored in the page buffer circuit <NUM> are programmed into the memory cell array <NUM> by the second program operation under control by the control logic circuit <NUM> (Operation ⑥). The second program operation may be a fine program operation. The second program operation may program the four logical pages into a single physical page (e.g. the same page as programmed in the first program operation). In an embodiment, the second program operation is a multi-step program operation including a coarse program operation and a fine program operation. As a result of the second program operation, a threshold voltage distribution formed by the threshold voltages of memory cells into which four logical pages are programmed may have a narrower distribution width than a threshold voltage distribution by only a coarse program for the four logical pages.

According to an embodiment, because the memory controller <NUM> does not need to store three logical pages after the first program operation, a QLC program operation may be possible even when the capacity of a write buffer in the memory controller <NUM> is small.

Referring to <FIG>, because Operations ①, ②, and ③ have been described with reference to <FIG>, descriptions thereof are omitted.

In <FIG>, the error detector <NUM> detects the number of errors in the three read logical pages (Operation ④). In <FIG>, when the detected number of errors exceeds the reference number, the three logical pages stored in the page buffer circuit <NUM> are transferred to the memory controller <NUM> (Operation ⑤).

In <FIG>, the ECC circuit <NUM> included in the memory controller <NUM> performs error correction on the three logical pages to generate three error-corrected pages and transmits the three error-corrected logical pages to the memory device <NUM> (Operation ⑥).

In <FIG>, the memory controller <NUM> transmits the remaining one logical page to the memory device <NUM> for the second program operation, and the one logical page may be stored in the page buffer circuit <NUM> (Operation ⑦). That is, three logical pages error-corrected by the ECC circuit <NUM> and one logical page received from the memory controller <NUM> may be stored in the page buffer circuit <NUM>. In an embodiment, the remaining one logical page is transferred to the memory device <NUM> when a second delay time elapses after the three logical pages are transferred to the memory device <NUM>. For example, the memory controller <NUM> may transmit three error corrected logical pages to the memory device <NUM>, delay for a delay time, and then transmit a single logical page to the memory device <NUM> after the delay time. The memory device <NUM> may store the received logical pages in the page buffer circuit <NUM>.

The four logical pages stored in the page buffer circuit <NUM> may be programmed into the memory cell array <NUM> by the second program operation under control by the control logic circuit <NUM> (Operation ⑧).

<FIG> is a block diagram of a memory device <NUM> according to an embodiment.

Referring to <FIG>, the memory device <NUM> may include a memory cell array <NUM>, a control logic circuit <NUM>, a page buffer circuit <NUM>, an error detector <NUM> (e.g., a logic circuit), a voltage generator <NUM>, and a row decoder <NUM> (e.g., a logic circuit). Although not shown in <FIG>, the memory device <NUM> may further include a pre-decoder, a temperature sensor, a command decoder, a column decoder, an address decoder, and the like.

The memory cell array <NUM> may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The memory cell array <NUM> may be connected to the page buffer circuit <NUM> through bit lines BL, and may be connected to the row decoder <NUM> through word lines WL, string select lines SSL, and ground select lines GSL. Memory cells connected to one word line WL may be referred to as a physical page. Data programmed into one physical page may be referred to as a logical page. A plurality of logical pages may be programmed into one physical page.

In an embodiment, the memory cell array <NUM> may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines stacked vertically on a substrate like the 3D memory cell arrays disclosed in <CIT>, <CIT>, <CIT>, <CIT>, and <CIT>. In an embodiment, the memory cell array <NUM> may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

The control logic circuit <NUM> may generally control various operations in the memory device <NUM>. The control logic circuit <NUM> may output various control signals in response to a command CMD and/or an address ADDR. For example, the control logic circuit <NUM> may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The page buffer circuit <NUM> may include a plurality of page buffers, and the plurality of page buffers may be respectively connected to memory cells through a plurality of bit lines BL. The page buffer circuit <NUM> may select at least one bit line among the bit lines BL in response to the control of the control logic circuit <NUM>. The page buffer circuit <NUM> may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer circuit <NUM> may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer circuit <NUM> may sense data stored in a memory cell by sensing the current or voltage of the selected bit line.

According to an embodiment, the page buffer circuit <NUM> may apply bit line voltages respectively corresponding to three logical pages during a first program operation. When a second delay time elapses after the first program operation has completed, the page buffer circuit <NUM> may detect three logical pages from the memory cell array <NUM>. For example, the programmed three logical pages may be read from the memory cell array <NUM> into the page buffer circuit <NUM>. The error detector <NUM> may detect errors in the three detected or read logical pages. The error detector <NUM> may compare the number of errors with a reference number and correct the errors when the number of errors is less than or equal to the reference number. When the number of errors is greater than the reference number, the three logical pages may be transferred to the memory controller <NUM>. The page buffer circuit <NUM> may apply bit line voltages respectively corresponding to four logical pages during a second program operation. For example, the four logical pages may include three logical pages corrected by the memory controller <NUM> or the error detector <NUM>, and an additional logical page sent by the memory controller <NUM>.

The voltage generator <NUM> may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator <NUM> may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, etc. as word line voltages VWL.

The row decoder <NUM> may select one of the plurality of word lines WL in response to the row address X-ADDR and may select one of the plurality of string select lines SSL. For example, during a program operation, the row decoder <NUM> may apply a program voltage and a program verify voltage to a selected word line, and during a read operation, the row decoder <NUM> may apply a read voltage to the selected word line.

The error detector <NUM> may detect an error in data stored in the page buffer circuit <NUM>. For example, the error detector <NUM> may detect an error by comparing the number of error bits included in three logical pages stored in the page buffer circuit <NUM> with a reference number. When the number of error bits is less than or equal to the reference number, the error detector <NUM> may correct the error. When the number of error bits is greater than the reference number, the three logical pages stored in the page buffer circuit <NUM> may be transferred to the memory controller <NUM>. The page buffer circuit <NUM> may receive three logical pages corrected by the memory controller <NUM>.

<FIG> is a diagram illustrating an error correction method according to an embodiment.

Referring to <FIG>, a page may be classified into first to third partial pages, and the first to third partial pages may correspond to first to third parities, respectively. The first to third parities may be used to detect whether the first to third partial pages have errors, respectively. For example, the first parity may represent <NUM> when the number of <NUM>'s among bits constituting the first partial page is even, and may represent <NUM> when the number of <NUM>'s among the bits constituting the first partial page is odd. Accordingly, when there is one error in the first partial page, the number of <NUM>'s in the bits constituting the first partial page changes, and thus, whether the first partial page has an error may be detected through the first parity.

However, because it is difficult to detect a plurality of errors by using one parity, a plurality of errors in a page may be detected through parities of a plurality of partial pages. For example, the length of the page may be pL, and the length of each of the first to third partial pages may be ppL. Because an error included in the first to third partial pages may be detected by the first to third parities, a plurality of errors in the page may be detected. The number of partial pages and the length ppL of each of the partial pages may be adjusted to increase error detection. In an embodiment, each of the partial pages overlaps at least one of the other partial pages. For example, the first partial page may include a first part of the page and the second partial page may include the same first part. For example, the second partial page may include the first part and a second part of the page, and the third partial page may include the same second part.

<FIG> is a diagram illustrating a 3D vertical NAND structure according to an embodiment. Each of the plurality of memory blocks of <FIG> may be represented by an equivalent circuit as shown in <FIG>. A memory block BLKi illustrated in <FIG> represents a 3D memory block formed on a substrate in a 3D structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to <FIG>, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2,. , and MC8, and a ground select transistor GST. In <FIG>, each of the plurality of memory NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1, MC2 ,. , and MC8, but is not limited thereto.

The string select transistor SST may be connected to a string select line SSL1, SSL2, or SSL3 corresponding thereto. The plurality of memory cells MC1, MC2,. , and MC8 may be respectively connected to gate lines GTL1, GTL2,. , and GTL8 corresponding thereto. The gate lines GTL1, GTL2,. , and GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2,. , and GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to a ground select line GSL1, GSL2, or GSL3 corresponding thereto. The string select transistor SST may be connected to the bit line BL1, BL2, or BL3 corresponding thereto, and the ground select transistor GST may be connected to the common source line CSL.

Word lines (e.g., WL1) of the same height may be commonly connected, and the ground selection lines GSL1, GSL2, and GSL3 and the string select lines SSL1, SSL2, and SSL3 may be separated from each other. In <FIG>, the memory block BLKi is illustrated as being connected to eight gate lines GTL1, GTL2,. , and GTL8 and three bit lines BL1, BL2, BL3. However, the inventive concept is not necessarily limited thereto.

The 3D non-volatile memory device may be implemented as a charge trap flash (CTF). In this case, an initial verify shift (IVS), in which charges trapped in a programmed CTF are redistributed over time and lost, may occur. A multi-step program operation may be performed to overcome this distribution deterioration phenomenon. According to an embodiment, for a <NUM>-bit program, a <NUM>-bit fine program operation is performed during a first program operation and a <NUM>-bit fine program operation is performed during a second program operation.

<FIG> is a diagram illustrating the distribution of a threshold voltage of a memory cell according to a program method. In <FIG>, it is assumed that a <NUM>-bit program operation is performed on the memory cell for convenience of description. Accordingly, the memory cell is programmed with at least one of <NUM> threshold voltage distributions.

Referring to <FIG>, the threshold voltage distribution of the memory cell may be programmed in at least one of an erase state E2 and program states P1 to P15 during a one-step program operation. The program states P1 to P15 are final states for storing <NUM>-bit data.

Referring back to <FIG>, in a multi-step program operation, a first program operation (<NUM>st PGM) is performed on the memory cell, and then, a second program operation (<NUM>nd PGM) is performed on the memory cell. Here, the first program operation may be a <NUM>-bit program operation, and the second program operation may be a <NUM>-bit program operation. Furthermore, both the first program operation and the second program operation may be fine-program operations.

During the first program operation, the threshold voltage distribution of the memory cell may be programmed in at least one of an erase state E1 and program states P21 to P27. During the second program operation, the threshold voltage distribution of the memory cell may be programmed in at least one of the erase state E2 and the program states P1 to P15. During the second program operation, the erase state E2 and the program state P1 may be formed based on the erase state E1 of the first program operation. The program states P2 and P3 may be formed based on the program state P21. The program states P4 and P5 may be formed based on the program state P22. The program states P6 and P7 may be formed based on the program state P23. The program states P8 and P9 may be formed based on the program state P24. The program states P10 and P11 may be formed based on the program state P25. The program states P12 and P13 may be formed based on the program state P26. The program states P14 and P15 may be formed based on the program state P27. In an embodiment, the threshold voltage distribution as a result of the first program operation has fewer states than the threshold voltage distribution as a result of the second program operation.

<FIG> is a diagram illustrating a logical page corresponding to a program state according to an embodiment.

Referring to <FIG>, a memory cell may be programmed in an erase state E2 or one of program states P1 to P15. The memory cell may be a QLC that stores four bits, and the erase state E2 and the program states P1 to P15 may correspond to four logical pages.

Referring to <FIG>, the erase state E2 and the program state P1 may be distinguished from each other by a fourth logical page. That is, in the erase state E2 and the program state P1, first to third logical page values may be respectively equal to <NUM>, <NUM>, and <NUM>, but fourth logical page values may be different from each other. In other words, referring to both <FIG> and <FIG>, the erase state E2 and the program state P1 may be formed based on the erase state E1 corresponding to three bits <NUM>, <NUM>, and <NUM>. Similarly, the program states P2 to P15 may be distinguished from one another by neighboring program states and the fourth logical page.

<FIG> is a diagram illustrating a multi-step program operation performed using address scrambling. Here, a delay time between the first program operation (<NUM>st PGM) and the second program operation (<NUM>nd PGM) may be determined by address scrambling. According to the address scrambling, the first program operation and the second program operation of each of the plurality of word lines may be discontinuously performed.

Referring to <FIG>, the horizontal axis of a table indicating the address scrambling indicates first to fourth string select lines SSL1 to SSL4, and the vertical axis of the table indicates first to fourth word lines WL1 to WL4. Points at which one string select line is related to one word line indicate addresses of memory cells. For example, a position A means the position of memory cells at a point at which the first string select line SSL1 is related to the first word line WL1, and a position B means the position of memory cells at a point at which the fourth string select line SSL4 is related to the third word line WL3. A coarse program operation and a fine program operation may be sequentially performed on memory cells located at respective addresses.

In <FIG>, for convenience of description, it is assumed that first to eighth operations ①, ②, ③, ④, ⑤, ⑥, ⑦, and ⑧ are sequentially performed for the first to fourth word lines WL1 to WL4. That is, after a first program operation on the first word line WL1 is completed in the first operation ①, a first program operation on the second word line WL2 is completed in the second operation ②. Thereafter, in the third operation ③, a second program operation on the first word line WL1 is performed, and in the fourth operation ④, a first program operation on the third word line WL3 is performed. Also, in the fifth operation ⑤, a second program operation on the second word line WL2 is performed.

A delay time between the first program operation and the second program operation at the position A may be a time during which seven first program operations (<NUM> to <NUM>) are performed. A delay time between the first program operation and the second program operation at the position B may be a time during which seven second program operations (<NUM> to <NUM> and <NUM> to <NUM>) and four first program operations (<NUM> to <NUM>) are performed. That is, delay times may vary for each position of the memory cells.

<FIG> is a view illustrating a method of operating a memory system <NUM>, according to an embodiment. Referring to <FIG>, the method of operating the memory system <NUM> may include a plurality of operations (operations S910 to S990). In an embodiment, when the operations performed are described in units of bits, N logical pages, K logical pages and N-K logical pages may correspond to N bit data, K bit data and N-K bit data, respectively.

In operation S910, the memory controller <NUM> transmits K (K is a positive integer) logical pages to the memory device <NUM>. The K logical pages may be stored in the page buffer circuit <NUM>. The memory controller <NUM> may also transmit, to the memory device <NUM>, a command instructing a program of N (N is a positive integer greater than K) logical pages. For example, even though the command instructs programming of N logical pages, the memory controller <NUM> may initially only transfer K logical pages to the memory device <NUM>.

In operation S920, the memory device <NUM> programs the K logical pages stored in the page buffer circuit <NUM> into the memory cell array <NUM>. A program operation for the K logical pages may be referred to as a first program operation. The first program operation may be performed as a fine program operation.

In operation S930, when a first delay time td1 elapses after the first program operation is completed, the memory device <NUM> reads the K logical pages programmed into the memory cell array <NUM>.

In operation S940, the memory device <NUM> detects error bits in the K read logical pages and compares the number of error bits with a reference number. For example, the memory device <NUM> may detect the number of error bits in the K read logical pages based on parity bits corresponding to partial pages included in each of the K read logical pages. When the number of error bits is greater than the reference number, operation S950 is performed, and when the number of error bits is less than or equal to the reference number, operation S980 is performed.

In operation S950, the memory device <NUM> transmits the K read logical pages to the memory controller <NUM>.

In operation S960, the memory controller <NUM> performs error correction on the K logical pages to generate K corrected logical pages. For example, the ECC circuit <NUM> may perform error correction on the K logical pages through an ECC operation.

In operation S970, the memory controller <NUM> transmits the K corrected logical pages to the memory device <NUM>.

In operation S980, the memory controller <NUM> transmits N-K logical pages to the memory device <NUM>. In an embodiments, operation S980 is performed when a second delay time td2 has elapsed after operation S910 is performed.

In operation S990, the memory device <NUM> performs a second program operation on the N logical pages, based on the K logical pages and the N-K logical pages. The second program operation may be a fine program operation.

<FIG> is a block diagram of a host-memory system <NUM> according to an embodiment.

The host-memory system <NUM> may include a host <NUM> and a memory system <NUM>. Also, the memory system <NUM> may include a memory controller <NUM> and a memory device <NUM>. Also, according to an embodiment, the host <NUM> may include a host controller <NUM> and a host memory <NUM>. The host memory <NUM> may function as a buffer memory for temporarily storing data to be transmitted to the memory system <NUM> or data transmitted from the memory system <NUM>.

The memory system <NUM> may include storage media for storing data according to a request from the host <NUM>. As an example, the memory system <NUM> may include at least one of a solid state drive (SSD), an embedded memory, and a detachable external memory. When the memory system <NUM> is an SSD, the memory system <NUM> may be a device conforming to a non-volatile memory express (NVMe) standard. When the memory system <NUM> is an embedded memory or an external memory, the memory system <NUM> may be a device conforming to a universal flash storage (UFS) or an embedded multi-media card (eMMC) standard. The host <NUM> and the memory system <NUM> may each generate and transmit a packet according to an adopted standard protocol.

When the memory device <NUM> of the memory system <NUM> includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the memory system <NUM> may include various other types of non-volatile memories. For example, the memory system <NUM> may include MRAM, spin-transfer torque MRAM, CBRAM, FeRAM, PRAM, RRAM, and/or other type of memory.

According to an embodiment, the host controller <NUM> and the host memory <NUM> may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller <NUM> and the host memory <NUM> may be integrated in the same semiconductor chip. As an example, the host controller <NUM> may be any one of a plurality of modules or devices included in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory <NUM> may be an embedded memory provided in the application processor or a non-volatile memory or a memory module disposed outside the application processor.

The host controller <NUM> may manage an operation of storing data (e.g., write data) of a buffer region of the host memory <NUM> in the memory device <NUM> or storing data (e.g., read data) of the memory device <NUM> in the buffer region.

The memory controller <NUM> may include a host interface <NUM>, a memory interface <NUM>, and a central processing unit (CPU) <NUM>. In addition, the memory controller <NUM> may further include a flash translation layer (FTL) <NUM>, a packet manager <NUM>, a buffer memory <NUM>, an ECC circuit <NUM>, and an advanced encryption standard (AES) circuit <NUM>. The memory controller <NUM> may further include a working memory (not shown) into which the FTL <NUM> is loaded, and the CPU <NUM> may execute the FTL <NUM> to control data write and read operations on the memory device <NUM>.

The host interface <NUM> may transmit and receive packets to and from the host <NUM>. A packet transmitted from the host <NUM> to the host interface <NUM> may include a command or data to be written to the memory device <NUM>, and a packet transmitted from the host interface <NUM> to the host <NUM> may include a response to the command or data read from the memory device <NUM>. The memory interface <NUM> may transmit, to the memory device <NUM>, data to be written to the memory device <NUM> or receive data read from the memory device <NUM>. The memory interface <NUM> may be implemented to comply with a standard protocol, such as Toggle or open NAND flash interface (ONFI).

The FTL <NUM> may perform various functions, such as address mapping, wear-leveling, and garbage collection. The address mapping operation may be an operation of converting a logical address received from the host <NUM> into a physical address used to actually store data in the memory device <NUM>. The wear-leveling may be a technique for preventing excessive deterioration of a specific block by allowing blocks in the memory device <NUM> to be uniformly used. For example, the wear-leveling may be implemented using a firmware technique for balancing erase counts of physical blocks. The garbage collection may be a technique for securing usable capacity in the memory device <NUM> by copying valid data of an existing block to a new block and then erasing the existing block.

The packet manager <NUM> may generate a packet according to a protocol of an interface with the host <NUM> or parse various types of information from the packet received from the host <NUM>.

The buffer memory <NUM> may temporarily store data to be written to or read from the memory device <NUM>. The buffer memory <NUM> may be a component provided in the memory controller <NUM>, but may be outside the memory controller <NUM>. According to an embodiment, three logical pages are temporarily stored in the buffer memory <NUM> during a first program operation, and one logical page is temporarily stored in the buffer memory <NUM> during a second program operation. That is, among four logical pages for the second program operation, three logical pages are read from the memory cell array <NUM> in the memory device <NUM>, and thus, only one logical page need be stored in the buffer memory <NUM>. Accordingly, a QLC program operation may be performed using the buffer memory <NUM> having a small capacity. In some embodiments, when the three logical pages read from the memory cell array <NUM> include a greater number of error bits than a reference number, the three read logical pages may be transferred to the buffer memory <NUM>. The ECC circuit <NUM> may perform error correction on the three logical pages stored in the buffer memory <NUM>.

The ECC circuit <NUM> may perform an error detection and correction function on read data read from the memory device <NUM>. More specifically, the ECC circuit <NUM> may generate parity bits for write data to be written into the memory device <NUM>, and the generated parity bits may be stored in the memory device <NUM> together with the write data. When reading data from the memory device <NUM>, the ECC circuit <NUM> may correct an error in the read data by using parity bits read from the memory device <NUM> together with the read data to generate error-corrected read data and output the error-corrected read data.

The AES circuit <NUM> may perform at least one of an encryption operation and a decryption operation on data input to the memory controller <NUM> using a symmetric-key algorithm.

<FIG> is a flowchart illustrating a multi-step program operation method for programming N logical pages, according to an embodiment. The multi-step program operation method may include a plurality of operations S1110 to S1140.

In operation S1110, the memory device <NUM> performs a first program operation on K logical pages. For example, K may be a positive integer of <NUM> or greater. The first program operation may be a fine program operation.

In operation S1120, the memory device <NUM> reads the K programmed logical pages from the memory cell array <NUM> in response to a read command. Because the first program operation is a fine program operation, the reliability of the K read logical pages may be relatively high. According to an embodiment, the memory device <NUM> may receive the read command from the memory controller <NUM> before a first delay time td1 elapses.

In operation S1130, the memory device <NUM> performs error correction on the K read logical pages to generate K corrected logical pages and then outputs the K corrected logical pages to the memory controller <NUM>.

In operation S1140, the memory device <NUM> receives N-K logical pages from the memory controller <NUM> and reads K logical pages from the memory cell array <NUM>, thereby performing a second program operation on the N logical pages, where N is greater than K. For example, if N is <NUM> and K is <NUM>, then the memory device <NUM> receives two logical pages from the memory controller <NUM>. The second program operation may be a fine program operation. According to an embodiment, the second program operation is performed when a third delay time elapses after the first program operation is performed.

According to an embodiment, because a fine program for K logical pages is performed during the first program operation, the memory device <NUM> may process a read request for the K logical pages before completing the second program operation.

<FIG> is a flowchart illustrating a first program operation method of a memory device according to an embodiment. Referring to <FIG>, the first program operation method may include a plurality of operations S1210 to S1240.

In operation S1210, the memory device <NUM> performs a program operation on K logical pages. In an embodiment, the K logical pages are programmed in the memory cell array <NUM> using a fine programming method. The K logical pages may be received from the memory controller <NUM>. The K logical pages may be stored in the page buffer circuit <NUM> included in the memory device <NUM>. That is, the K logical pages stored in the page buffer circuit <NUM> may have higher reliability than data read from the memory cell array <NUM>.

In operation S1220, the memory device <NUM> reads a first logical page among the K logical pages. In an embodiment, the memory device <NUM> may read a first logical page among the K logical pages from the memory cell array <NUM> before the first delay time td1 elapses. The first logical page may be a logical page in which an error is highly likely to occur among the K logical pages. For example, the first logical page may be a logical page for discriminating the highest program state from among the K logical pages. Referring to <FIG>, when K is <NUM>, the highest program state may be the program state P27. Referring to <FIG>, the program state P27 is formed based on three logical page bits <NUM>, <NUM>, and <NUM> and is distinguished from the program state P26 through a third logical page Page <NUM>, and thus, a first logical page may be the third logical page Page <NUM>. The read first logical page may be stored in a latch that does not store the K logical pages from among latches included in the page buffer circuit <NUM>. The embodiment is not limited thereto, and the memory device <NUM> may read some or all of the K logical pages.

In operation S1230, the memory device <NUM> may detect an error bit of the read first logical page by comparing the read first logical page with the first logical page stored in the page buffer circuit <NUM>. However, embodiments of the inventive concept are not limited thereto, and the memory device <NUM> may detect error bits of the K logical pages by comparing some or all of the read K logical pages with some or all of the K logical pages stored in the page buffer circuit <NUM>.

In operation S1240, the memory device <NUM> may store, in a buffer memory, information indicating whether error correction for the K logical pages is possible, based on a comparison result between the number of error bits and a reference number. For example, when the number of error bits is greater than the reference number, the information indicating that error correction for the K logical pages is not possible is stored in the buffer memory; when the number of error bits is less than or equal to the reference number, the information indicating that error correction for the K logical pages is possible is stored in the buffer memory. The buffer memory may be included in the memory device <NUM>. The buffer memory may be implemented as a non-volatile memory, a volatile memory, or a register.

<FIG> is a flowchart illustrating a second program operation method of a memory device according to an embodiment. Referring to <FIG>, the second program operation method may include a plurality of operations S1310 to S1360.

In operation S1310, the memory device <NUM> reads K logical pages from the memory cell array <NUM>. The read K logical pages may be stored in the page buffer circuit <NUM>. In an embodiment, operation S1310 is performed when a first delay time elapses after the first program operation is completed.

In operation S1320, the memory device <NUM> determines whether the read K logical pages are correctable pages, based on information stored in the buffer memory. When the K logical pages are correctable pages, operation S1350 is performed, and when the K logical pages are non-correctable pages, operation S1330 is performed.

In operation S1330, the memory device <NUM> transmits the K logical pages read from the memory cell array <NUM> to the memory controller <NUM>.

In operation S1340, the memory device <NUM> receives corrected K logical pages from the memory controller <NUM>. The corrected K logical pages may be stored in the page buffer circuit <NUM>.

In operation S1350, the memory device <NUM> receives N-K logical pages from the memory controller <NUM>. In an embodiment, operation S1350 is performed when a second delay time elapses after the memory device <NUM> receives K logical pages from the memory controller <NUM> in operation S1210 of <FIG>.

In operation S1360, the memory device <NUM> performs a program operation on N logical pages, based on the N-K logical pages and the K logical pages. The program operation on the N logical pages may be a fine program operation. In an embodiment, operation S1360 is performed when a third delay time elapses after the memory device <NUM> performs a program operation on K logical pages in operation S1210 of <FIG>.

<FIG> is a flowchart illustrating a first program operation method of a memory device according to an embodiment. Referring to <FIG>, the first program operation method may include a plurality of operations S1410 to S1440. Operations S1410 to S1430 may correspond to operations S1210 and S1230 of <FIG>, respectively.

In operation S1440, when the number of error bits is greater than a reference number, the memory device <NUM> stores K logical pages stored in the page buffer circuit <NUM> in a buffer memory. For example, when operation S1430 determines that the number of error bits is greater than a reference number, operation S1440 may be performed. The memory device <NUM> may store addresses of memory cells, into which the K logical pages are programmed, in the buffer memory. The buffer memory may be included in the memory device <NUM>. The buffer memory may be implemented as a non-volatile memory, a volatile memory, or a register.

<FIG> is a flowchart illustrating a second program operation method of a memory device according to an embodiment. Referring to <FIG>, the second program operation method may include a plurality of operations S1510 to S1560.

In operation S1510, the memory device <NUM> determines whether K logical pages are stored in the buffer memory, based on the addresses of the memory cells to be programmed. When the K logical pages are stored in the buffer memory, operation S1520 is performed, and when the K logical pages are not stored in the buffer memory, operation S1530 is performed.

In operation S1520, the memory device <NUM> reads K logical pages from the buffer memory. The read K logical pages may include no errors or a number of error bits that may be corrected in the memory device <NUM>.

In operation S1530, the memory device <NUM> reads K logical pages from the memory cell array <NUM> and transmits the read K logical pages to the memory controller <NUM>. The K logical pages may include a number of error bits that cannot be corrected in the memory device <NUM>.

In operation S1540, the memory device <NUM> receives corrected K logical pages from the memory controller <NUM>.

In operation S1550, the memory device <NUM> receives N-K logical pages from the memory controller <NUM>. In an embodiments, operation S1550 is performed when a second delay time elapses after the memory device <NUM> receives K logical pages from the memory controller <NUM> in operation S1410 of <FIG>.

In operation S1560, the memory device <NUM> performs a program operation on N logical pages based on the N-K logical pages and the K logical pages. The program operation on the N logical pages may be a fine program operation. In an embodiment, operation S1560 is performed when a third delay time elapses after the memory device <NUM> performs a program operation on K logical pages in operation S1410 of <FIG>.

Claim 1:
A method of operating a memory system (<NUM>) including a memory device (<NUM>) and a memory controller (<NUM>), the method comprising:
programming (S920), by the memory device (<NUM>), K logical pages stored in a page buffer circuit (<NUM>) of the memory device (<NUM>) into a memory cell array (<NUM>) of the memory device (<NUM>);
reading (S930), by the memory device (<NUM>), the K logical pages programmed into the memory cell array (<NUM>) into the page buffer circuit (<NUM>) after a first delay time (td1) elapses;
comparing a number of error bits in the read K logical pages with a reference number;
responsive to the number of error bits in the read K logical pages being less than or equal to the reference number, performing, by an error detector (<NUM>) of the memory device (<NUM>), error correction on the read K logical pages to generate corrected K logical pages;
responsive to the number of error bits in the read K logical pages exceeding the reference number, performing steps i) to iii):
i) transmitting (S950), by the memory device (<NUM>), the read K logical pages to the memory controller (<NUM>);
ii) correcting (S960), by the memory controller (<NUM>), errors in the read K logical pages; and
iii) transmitting (S970), by the memory controller (<NUM>), the corrected K logical pages to the memory device (<NUM>);
transmitting (S980), by the memory controller (<NUM>), N-K logical pages to the memory device (<NUM>); and
programming (S990), by the memory device (<NUM>), N logical pages into the memory cell array (<NUM>), based on the corrected K logical pages and the N-K logical pages,
wherein K is a positive integer and N is a positive integer greater than K.