Patent Description:
Aspects of the present disclosure relate generally to buffers, and more particularly, to tracking and controlling the output swing of a buffer.

In a wireless communication system (e.g., a millimeter wave (mmWave) system), a local oscillator (LO) network may be used to distribute an LO signal from an LO to mixers in the system. The LO network may include buffers for driving the mixers with the LO signal. The buffers may each include a driver with a transformer as the load to improve power efficiency.

Attention is drawn to <CIT> disclosing amplifiers with noise splitting to improve noise figure. In an exemplary design, an apparatus includes a plurality of amplifier circuits and at least one interconnection circuit. The amplifier circuits receive an input radio frequency (RF) signal. The interconnection circuit(s) are coupled between the plurality of amplifier circuits. Each interconnection circuit is closed to short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. The plurality of amplifier circuits may include a plurality of gain circuits coupled to a plurality of current buffers, one gain circuit and one current buffer for each amplifier circuit. Each amplifier circuit provides an output current, which may include a portion of the current from each of the plurality of gain circuits when the plurality of amplifier circuits are enabled.

Further attention is drawn to <CIT> disclosing an N-stage inductor-less local oscillator (LO) buffer including N-<NUM> non-final stages and a final stage. The final stage includes a gain circuit, a common-mode feedback circuit connected to the gain circuit, and a replica bias circuit that provides a predetermined voltage to the common-mode feedback circuit. The inductor-less LO buffer can advantageously reduce a power budget for its downstream mixer as well as provide a compact footprint.

Further attention is drawn to <CIT> disclosing a system or method for controlling a voltage controlled oscillator (VCO) or LO buffer include an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer. Further attention is drawn to <CIT> disclosing a power amplifier arrangement comprising a first control circuit for keeping the power dissipated by its transistors below or equal, for any excitation level, to a limit fixed in dependence upon the required reliability level and a second control circuit for completely exploring the zone of available linear characteristics of the transistors in dependence upon the load conditions, the ambient temperature and parameters specific to the transistors.

Further attention is drawn to <CIT> disclosing an A-class power amplifier where no power source noise is outputted. By instantaneously switching a power source voltage in accordance with an absolute value of the output signal voltage, it is possible to significantly suppress the power consumption upon a non-signal or a low-level reproduction which occupies the most of a music composition reproduction time while maintaining the state not causing generation of a noise or degradation of audio quality. <CIT> discloses a signal buffer for a square-wave oscillator that achieves a constant amplitude output signal by using a feedback loop.

The present invention a method, and apparatus is set forth in the independent claims, respectively.

The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

A first aspect relates to an apparatus for buffering an input signal. The apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on the input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.

A second aspect relates to a method for controlling an output voltage swing of a buffer. The buffer includes a transformer and a driver, the transformer includes an input inductor and an output inductor, the input inductor is driven by the driver, and the input inductor is magnetically coupled to the output inductor. The method includes detecting the output voltage swing at the output inductor, and controlling a regulated voltage at the input inductor based on the detected output voltage swing.

A third aspect relates to an apparatus for buffering an input signal. The apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on the input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, and control a bias current of the driver based on the detected output voltage swing.

A fourth aspect relates to an apparatus for buffering an input signal. The apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes means for driving the input inductor based on the input signal, means for detecting an output voltage swing at the output inductor, means for generating a regulated voltage at the input inductor, and means for controlling the regulated voltage based on the detected output voltage swing.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects.

In a wireless communication system (e.g., a mmWave system), a local oscillator (LO) network may be used to distribute an LO signal from an LO to mixers in the system. The LO network may include buffers for driving the mixers with the LO signal. The buffers may be used to drive the mixers, for example, when the LO lacks the drive capability to directly drive the mixers. In addition, the buffers may provide the LO with high isolation from loads (e.g., mixer loads) in the LO network to prevent the loads from degrading the performance of the LO. For example, the buffers may provide the LO with high isolation from load changes in the LO network to prevent the load changes from causing a large shift in the oscillator frequency of the LO, which can degrade the LO signal.

<FIG> shows an example of a buffer <NUM> according to certain aspects of the present disclosure. The buffer <NUM> includes a transconductance driver <NUM> and a transformer <NUM>, in which the transformer <NUM> is used as the load for the transconductance driver <NUM> to increase output impedance and improve power efficiency. The transformer <NUM> includes an input inductor <NUM> and an output inductor <NUM>, in which the input inductor <NUM> is magnetically coupled to the output inductor <NUM>.

The transconductance driver <NUM> drives the input inductor <NUM> based on an input signal. In one example, the input signal is a differential input voltage (Vin+ and Vin-). In this example, the transconductance driver <NUM> converts the differential input voltage (Vin+ and Vin-) into a drive current to drive the input inductor <NUM>. The drive current is converted into a differential output voltage (Vp and Vm) at the output inductor <NUM>, which is output to another device (e.g., mixer). In the example in <FIG>, a center tap <NUM> of the input inductor <NUM> is coupled to a voltage supply rail.

<FIG> shows an exemplary implementation of the transconductance driver <NUM> according to certain aspects of the present disclosure. In this example, the transconductance driver <NUM> has a differential input configured to receive the differential input voltage (Vin+ and Vin-). The differential input includes a first input <NUM> and a second input <NUM>, in which the first input <NUM> receives voltage Vin+ and the second input <NUM> receives voltage Vin-. In this example, the transconductance driver <NUM> includes a first transistor <NUM> and a second transistor <NUM> forming a differential pair. The first and second transistors <NUM> and <NUM> may be implemented with n-type field effect transistors (NFETs), although it may be possible in certain implementations to use other transistor types. In this example, the drain of the first transistor <NUM> is coupled to a first end <NUM> of the input inductor <NUM>, the source of the first transistor <NUM> is coupled to ground, and the gate of the first transistor <NUM> is coupled to the first input <NUM> via a first coupling capacitor <NUM>. The drain of the second transistor <NUM> is coupled to a second end <NUM> of the input inductor <NUM>, the source of the second transistor <NUM> is coupled to ground, and the gate of the second transistor <NUM> is coupled to the second input <NUM> via a second coupling capacitor <NUM>. The input inductor <NUM> is coupled between the drains of the first and second transistor <NUM> and <NUM>.

In operation, the first and second transistors <NUM> and <NUM> convert the differential input voltage into a drive current that drives the input inductor <NUM>. The transconductance driver <NUM> also includes a bias circuit <NUM> coupled to the gates of the first and second transistors <NUM> and <NUM>. The bias circuit <NUM> is configured to bias the gates of the first and second transistors <NUM> and <NUM> with a gate bias voltage.

In this example, the input of the buffer <NUM> corresponds to the differential input <NUM> and <NUM> of the transconductance driver <NUM> and the output of the buffer <NUM> corresponds to the two ends <NUM> and <NUM> of the output inductor <NUM>. The buffer <NUM> may be used to provide high isolation (e.g., <NUM> dB or higher) between the input and the output of the buffer <NUM>. In one example, the buffer <NUM> may be used to provide high isolation between an LO coupled to the input of the buffer <NUM> and a mixer coupled to the output of the buffer <NUM>.

In certain aspects, the buffer <NUM> is used as a buffer in a local oscillator (LO) path that provides an LO signal from an LO (not shown) to a mixer <NUM>. In these aspects, the buffer <NUM> drives the mixer <NUM> with the LO signal (e.g., a sinusoidal signal). As shown in <FIG> and <FIG>, the LO signal is a differential voltage Vin+ and Vin- at the input of the buffer <NUM> and a differential voltage Vp and Vm at the output of the buffer <NUM>. The mixer <NUM> is configured to mix the LO signal with an input signal <NUM> to frequency shift the input signal <NUM>. For example, the mixer <NUM> may be used in a receiver to frequency downconvert a radio frequency (RF) input signal <NUM> into an intermediate-frequency output signal <NUM>. In another example, the mixer <NUM> may be used in a transmitter to frequency upconvert an intermediate-frequency input signal <NUM> into an RF output signal <NUM>. In the example shown in <FIG> and <FIG>, the LO signal is differential. The input signal <NUM> and the output signal <NUM> may also be differential.

The buffer <NUM> is capable of operating at very-high frequencies (e.g., tens of gigahertz) in the millimeter wave (mmWave) band. This makes the buffer <NUM> suitable for mmWave systems, which are used, for example, in fifth generation (<NUM>) wireless communications. However, a challenge with using the buffer <NUM> is that the output voltage swing of the buffer <NUM> can vary (e.g., by more than <NUM> dB) across process-voltage-temperate (PVT) corners. This is because the output voltage swing is current limited, not voltage limited. The negative impact of the output voltage swing variation may include one or more of the following: excess power consumption, signal path gain variation, increased LO leakage, and reliability issues.

With regard to excess power consumption, the mixer <NUM> may require a minimum LO swing to drive the mixer <NUM>. To ensure that the minimum LO swing requirement is met across PVT corners, a bias current of the transconductance driver <NUM> may be set so that the output voltage swing of the buffer <NUM> meets the minimum LO swing requirement for the worst-case PVT corner. However, this approach may cause the output voltage swing to be significantly higher than the minimum LO swing requirement for some PVT corners. Consequently, for these PVT corners, the LO swing may be significantly higher than needed to drive the mixer <NUM>, resulting in large excess power consumption for these PVT corners.

With regard to signal path gain variation, the signal path gain may vary with the LO swing at the mixer <NUM>. As a result, variation in the output voltage swing of the buffer <NUM> across PVT corners may lead to variation in the signal path gain across PVT corners. In this case, signal path gain calibration may have a difficult time calibrating the signal path gain for variation in the LO swing across temperature.

With regard to LO leakage, a portion of the LO signal at the mixer <NUM> leaks into the output of the mixer <NUM>. The output voltage swing (and hence LO swing at the mixer <NUM>) may significantly increase (e.g., by <NUM> dB) for some PVT corners, which worsens LO leakage.

With regard to reliability, the large output voltage swing (and hence large LO swing at the mixer <NUM>) for some PVT corners can cause devices to fail (e.g., by exceeding tolerances for these devices). This may force a designer to avoid using the most effective approach in terms of performance if a less effective approach has a higher tolerance of large LO swing.

To reduce the swing variation discussed above, aspects of the present disclosure track and control the output voltage swing of the buffer <NUM>. In some implementations, a feedback circuit detects the output voltage swing of the buffer <NUM> (e.g., using a peak detector), and adjusts the output voltage swing based on the detected output voltage swing to keep the output voltage swing close to a target voltage swing (i.e., approximately equal to the target voltage swing). To keep the output voltage swing close to the target voltage swing, the feedback circuit may decrease the output voltage swing when the detected output voltage swing is above the target voltage swing to move the output voltage swing closer to the target voltage swing, and increase the output voltage swing when the detected output voltage swing is below the target voltage swing to move the output voltage swing closer to the target voltage swing. The feedback circuit may adjust the output voltage swing of the buffer <NUM> by adjusting a parameter of the buffer <NUM> affecting the output voltage swing. The parameter may include a voltage at the input inductor <NUM> and/or a bias current of the transconductance driver <NUM>, as discussed further below.

<FIG> shows an example of a feedback circuit <NUM> for tracking and controlling the output voltage swing of the buffer <NUM> according to certain aspects of the present disclosure. In this example, the feedback circuit <NUM> controls the output voltage swing by controlling a regulated voltage <NUM> at the input inductor <NUM> (e.g., center tap <NUM> of the input inductor <NUM>). The output voltage swing at the differential output of the buffer <NUM> is approximately a linear function of the regulated voltage <NUM>, in which the output voltage swing increases when the regulated voltage <NUM> is increased and decreases when the regulated voltage <NUM> is decreased. Thus, the feedback circuit <NUM> is able to control the output voltage swing of the buffer <NUM> by controlling the regulated voltage <NUM>.

In certain aspects, the feedback circuit <NUM> is configured to detect the output voltage swing at the output inductor <NUM>, generate the regulated voltage <NUM> at the input inductor <NUM> (e.g., center tap <NUM> of the input inductor <NUM>), and control the regulated voltage <NUM> based on the detected output voltage swing. In these aspects, the feedback circuit <NUM> may control the regulated voltage <NUM> based on the detected output voltage swing by comparing the detected output voltage swing with a target voltage swing, and adjusting the regulated voltage <NUM> in a direction that reduces the difference between the output voltage swing and the target voltage swing. For example, if the detected output voltage swing is above the target voltage swing, then the feedback circuit <NUM> may decrease the regulated voltage <NUM> to decrease the output voltage swing. If the detected output voltage swing is below the target voltage swing, then the feedback circuit <NUM> may increase the regulated voltage <NUM> to increase the output voltage swing. In this way, the feedback circuit <NUM> adjusts the regulated voltage <NUM> based the detected output voltage swing to keep the output voltage swing of the buffer <NUM> close to the target voltage swing.

In the example shown in the <FIG>, the feedback circuit <NUM> includes a peak detector <NUM>, a control circuit <NUM>, and a voltage regulator <NUM> coupled in a feedback loop <NUM>. The peak detector <NUM> is configured to detect the output voltage swing, the voltage regulator <NUM> is configured to generate the regulated voltage <NUM>, and the control circuit <NUM> is configured to control the regulated voltage <NUM> generated by the voltage regulator <NUM> based on the detected output voltage swing, as discussed further below.

The peak detector <NUM> has a differential input coupled to the differential output of the buffer <NUM>. The peak detector <NUM> is configured to detect the output voltage swing at the differential output of the buffer <NUM>, and generate a swing detection signal <NUM> based on the detected output voltage swing. The output voltage swing may be approximately equal to the peak difference between the voltage Vp at the positive output the buffer <NUM> and the voltage Vm at the minus output of the buffer <NUM>. In certain aspects, the swing detection signal <NUM> may be a voltage that is related (e.g., proportional) to the output voltage swing of the buffer <NUM>, as discussed further below.

The control circuit <NUM> is configured to receive the swing detection signal <NUM> from the peak detector <NUM>, and generate a control signal <NUM> based on the swing detection signal <NUM>. The control signal <NUM> is input to the voltage regulator <NUM> to control the regulated voltage <NUM> generated by the voltage regulator <NUM>.

The voltage regulator <NUM> is coupled to the input inductor <NUM>. In certain aspects, the voltage regulator <NUM> is coupled to the center tap <NUM> of the input inductor <NUM> (although there may be possible implementations where other tap points may be used). The voltage regulator <NUM> is configured to generate the regulated voltage <NUM> from the supply voltage, and apply the regulated voltage <NUM> to the the input inductor <NUM> (e.g., at the center tap <NUM>). The regulated voltage <NUM> generated by the voltage regulator <NUM> is controlled by the control signal <NUM> from the control circuit <NUM>.

In certain aspects, the control circuit <NUM> generates the control signal <NUM> by comparing the swing detection signal <NUM> with a target reference signal corresponding to the target voltage swing, and generating the control signal <NUM> based on the comparison. In these aspects, the target reference signal provides a reference point with which the swing detection signal <NUM> is compared to assess whether the output voltage swing is above or below the target voltage swing. In one example, the output voltage swing is approximately equal to the target voltage swing when the swing detection signal <NUM> is approximately equal to the reference target signal. In this example, the reference target signal indicates the value (e.g., voltage) that the swing detection signal <NUM> should have when the output voltage swing is equal to the target voltage swing. If the swing detection signal <NUM> is above the reference target signal, then the output voltage swing is above the target voltage swing, and, if the swing detection signal <NUM> is below the reference target signal, then the output voltage swing is below the target voltage swing. In this example, the control circuit <NUM> keeps the output voltage swing close to the target voltage swing by adjusting the regulated voltage <NUM> in a direction that reduces the difference between the swing detection signal <NUM> and the target reference signal.

Thus, the feedback circuit <NUM> adjusts the regulated voltage <NUM> based on feedback of the output voltage swing to keep the output voltage swing of the buffer <NUM> close to the target voltage swing. The feedback circuit <NUM> is able to keep the output voltage swing close to the target voltage swing across PVT corners, thereby significantly reducing variation in the output voltage swing across PVT corners compared with systems that do not use feedback to control the output voltage swing. The reduced variation in the output voltage swing across PVT corners mitigates the excess power consumption, signal path gain variation, increased LO leakage, and/or reliability issues discussed above with reference to <FIG> and <FIG>.

For the example in which the buffer <NUM> is used in an LO path that provides an LO signal from an LO to the mixer <NUM>, the target voltage swing may be set close to a minimum LO swing requirement for driving the mixer <NUM> (e.g., to minimize power consumption). In this example, the feedback circuit <NUM> keeps the output voltage swing of the buffer <NUM> close to the minimum LO swing across PVT corners. This helps prevent the output voltage swing from being significantly higher than the minimum LO swing for some PVT corners, which can lead to the excess power consumption, increased LO leakage and/or reliability issues discussed above.

The LO path from the LO to the mixer <NUM> may include one or more other devices in addition to the buffer <NUM>. The one or more other devices may include an amplifier, another buffer, a phase shifter and/or a vector modulator. In this example, the buffer <NUM> may be placed at the end of the LO path (also referred to as an LO chain) right before the mixer <NUM>. Placing the buffer <NUM> at the end of the LO path allows the feedback circuit <NUM> to control the LO swing at the mixer <NUM>. By controlling the LO swing at the end of the LO path, the feedback circuit <NUM> is able to clean up swing variation caused by one or more others devices in the LO path preceding the buffer <NUM>. This is because the feedback circuit <NUM> keeps the output voltage swing of the buffer <NUM> close to the target voltage swing, which helps prevent swing variation caused by the one or more preceding devices in the LO path from propagating to the mixer <NUM>. In this example, the swing variation from the one or more preceding devices in the LO path may include amplitude modulation (AM) noise, swing variation due to PVT variations in the one or more preceding devices, and/or non-idealities in the one or more preceding devices.

The feedback circuit <NUM> adjusts the regulated voltage <NUM> at the input inductor <NUM> based on feedback of the output voltage swing to keep the output voltage swing of the buffer <NUM> close to the target voltage swing. Thus, in this example, the regulated voltage <NUM> at the input inductor <NUM> is the parameter of the buffer <NUM> that is adjusted to control the output voltage swing. As discussed above, the output voltage swing of the buffer <NUM> is approximately a linear function of the regulated voltage <NUM> at the input inductor <NUM>. The approximately linear relationship between the regulated voltage <NUM> and the output voltage swing helps provide good loop stability for the feedback loop <NUM>.

<FIG> shows exemplary implementations of the peak detector <NUM>, the control circuit <NUM> and the voltage regulator <NUM> according to certain aspects of the present disclosure. In the example in <FIG>, the peak detector <NUM> includes a first transistor <NUM>, a second transistor <NUM>, a current source <NUM> and a hold capacitor <NUM>. The first and second transistors <NUM> and <NUM> may be implemented with n-type field effect transistors (NFETs), although p-type or other types of transistors may be possible in certain implementations. In this example, the drain of the first transistor <NUM> is coupled to the voltage supply rail, the source of the first transistor <NUM> is coupled to node <NUM>, and the gate of the first transistor <NUM> coupled to the positive output of the buffer <NUM> through a first coupling capacitor <NUM>. The gate of the first transistor <NUM> is DC biased by a bias voltage (labeled "Vbias") through a first bias resistor (labeled "Rb1"). The drain of the second transistor <NUM> is coupled to the voltage supply rail, the source of the second transistor <NUM> is coupled to node <NUM>, and the gate of the second transistor <NUM> is coupled to the minus output of the buffer <NUM> through a second coupling capacitor <NUM>. The gate of the second transistor <NUM> is DC biased by the bias voltage Vbias through a second bias resistor (labeled "Rb2"). The current source <NUM> is coupled between node <NUM> and ground, and the hold capacitor <NUM> is coupled between node <NUM> and ground.

The first and second transistors <NUM> and <NUM> are configured as source followers, in which the positive output Vp of the buffer <NUM> is input to the gate of the first transistor <NUM>, the minus output Vm of the buffer <NUM> is input to the gate of second transistor <NUM>, and the output of the peak detector <NUM> is coupled to the sources of the first and second transistors <NUM> and <NUM> at node <NUM>. In this configuration, the first and second transistors <NUM> and <NUM> function as rectifiers that, in combination with the hold capacitor <NUM>, produce a sense voltage (labeled "Vsen") at node <NUM> that is related (e.g., proportional) to the output voltage swing of the buffer <NUM>. The hold capacitor <NUM> holds the sense voltage Vsen at the output of the peak detector <NUM>. In one example, the sense voltage Vsen and the output voltage swing are related by a ratio that is a function of the bias voltage Vbias. In this example, the sense voltage Vsen is higher for a higher output voltage swing and lower for a lower output voltage swing within an output voltage swing range. Thus, the sense voltage Vsen tracks changes in the output voltage swing. The sense voltage Vsen varies slowly relative to the frequency of the LO signal, and thus may be considered approximately a DC voltage with respect to the LO signal. In this example, the sense voltage Vsen corresponds to the swing detection signal <NUM> discussed above, and is generated based on the bias voltage Vbias and the output voltage swing of the buffer <NUM>.

The current source <NUM> provides bias current for the first and second transistors <NUM> and <NUM>. The current source <NUM> also helps the peak detector <NUM> track changes in the output voltage swing of the buffer <NUM>. For example, if the output voltage swing decreases, the current source <NUM> discharges some of the charge on the hold capacitor <NUM> to allow the sense voltage Vsen to decrease to reflect the decrease in the output voltage swing.

In the example in <FIG>, the control circuit <NUM> includes an operational amplifier <NUM>, and a replica circuit <NUM>. The replica circuit <NUM> may have the same structure or substantially the same structure as the peak detector <NUM>. As discussed further below, the replica circuit <NUM> is used to set the target voltage swing of the feedback circuit <NUM>, and cancel out variation in the sense voltage Vsen due to PVT conditions in the peak detector <NUM>.

<FIG> shows an exemplary implementation of the replica circuit <NUM> according to certain aspects. In this example, the replica circuit <NUM> includes a first transistor <NUM>, a second transistor <NUM>, a current source <NUM> and a hold capacitor <NUM>. The drain of the first transistor <NUM> is coupled to the voltage supply rail, the source of the first transistor <NUM> is coupled to node <NUM>, and the gate of the first transistor <NUM> is biased by a target voltage (labeled "Vtarget"). The drain of the second transistor <NUM> is coupled to the voltage supply rail, the source of the second transistor <NUM> is coupled to node <NUM>, and the gate of the second transistor <NUM> is biased by the target voltage Vtarget. The current source <NUM> is coupled between node <NUM> and ground, and the hold capacitor <NUM> is coupled between node <NUM> and ground.

The replica circuit <NUM> is structurally similar to the peak detector <NUM> in which the first transistor <NUM>, the second transistor <NUM>, the current source <NUM> and the hold capacitor <NUM> of the replica circuit <NUM> correspond to the first transistor <NUM>, the second transistor <NUM>, the current source <NUM> and the hold capacitor <NUM> of the peak detector <NUM>, respectively. Unlike the peak detector <NUM>, the gates of the first and second transistors <NUM> and <NUM> of the replica circuit <NUM> are not coupled to the differential output of the buffer <NUM>. The gates of the first and second transistors <NUM> and <NUM> are biased by the target voltage Vtarget, which is used to set the target voltage swing, as discussed further below. The replica circuit <NUM> generates a DC reference voltage Vref at node <NUM> based on the target voltage Vtarget. In this example, the reference voltage Vref corresponds to the target reference signal discussed above.

Referring back to <FIG>, the sense voltage Vsen is input to the minus input of the amplifier <NUM>, and the reference voltage Vref is input to the positive input of the amplifier <NUM>. The output of the amplifier <NUM> provides the control signal <NUM> to the voltage regulator <NUM>.

In operation, the amplifier <NUM> adjusts the control signal <NUM> in a direction that reduces the difference between the sense voltage Vsen and the reference voltage Vref input to the amplifier <NUM>. For example, if the sense voltage Vsen is below the reference voltage Vref, then the amplifier <NUM> adjusts the control signal <NUM> in a direction that causes the voltage regulator <NUM> to increase the regulated voltage <NUM>. The increase in the regulated voltage <NUM> increases the output voltage swing of the buffer <NUM>, which, in turn, increases the sense voltage Vsen. If the sense voltage Vsen is above the reference voltage Vref, then the amplifier <NUM> adjusts the control signal <NUM> in a direction that causes the voltage regulator <NUM> to decrease the regulated voltage <NUM>. The decrease in the regulated voltage <NUM> decreases the output voltage swing of the buffer <NUM>, which, in turn, decreases the sense voltage Vsen.

Thus, the amplifier <NUM> forces the sense voltage Vsen to be approximately equal to the reference voltage Vref (i.e., approximately balances Vsen and Vref). This occurs when the output voltage swing of the buffer <NUM> is approximately equal to the target voltage Vtarget minus the bias voltage Vbias (i.e., Vtarget - Vbias). As a result, the feedback circuit <NUM> adjusts the regulated voltage <NUM> such that the output voltage swing of the buffer <NUM> is approximately equal to Vtarget - Vbias. Thus, in this example, the target voltage swing of the feedback circuit <NUM> is approximately equal to Vtarget - Vbias.

Therefore, the target voltage swing may be set by setting the bias voltages of the peak detector <NUM> and the replica circuit <NUM> (i.e., Vbias and Vtarget) according to the desired target voltage swing. For example, for a given bias voltage Vbias, the target voltage swing may be set by setting the target voltage Vtarget at the replica circuit <NUM> such that Vtarget - Vbias equals the desired target voltage swing. In this regard, the bias voltage Vbias and the target voltage Vtarget may be generated by a voltage generator <NUM>. The voltage generator <NUM> may be configured to set the voltage levels of the bias voltage Vbias and the target voltage Vtarget such that Vtarget - Vbias equals the desired target voltage swing.

As discussed above, the replica circuit <NUM> is also used to cancel out variation in the sense voltage Vsen due to PVT conditions in the peak detector <NUM>. In this regard, the replica circuit <NUM> may be integrated on the same chip (i.e., die) as the peak detector <NUM>. In certain aspects, the replica circuit <NUM> may be located in close proximity to the peak detector <NUM> so that the replica circuit <NUM> is subjected to approximately the same PVT conditions as the peak detector <NUM>. As a result, the variation in the reference voltage Vref due to PVT conditions is approximately the same as the variation in the sense voltage Vsen due to PVT conditions. Since the amplifier <NUM> takes the difference of the sense voltage Vsen and the reference voltage Vref at its inputs, the variation in the reference voltage Vref due to PVT conditions approximately cancels out the variation in the sense voltage Vsen due to PVT conditions. This reduces the PVT effect on the control signal <NUM>, resulting in more accurate control of the output voltage swing.

In the example in <FIG>, the voltage regulator <NUM> is implemented with a transistor <NUM> (e.g., NFET) having a drain coupled to the voltage supply rail, a source coupled to the input inductor <NUM> (e.g., at the center tap <NUM>), and a gate coupled to the control signal <NUM>. In this example, the transistor <NUM> provides current from the voltage supply rail to the input inductor <NUM>. The regulated voltage <NUM> is approximately equal to the voltage at the supply rail minus the voltage drop across the transistor <NUM>. In this example, the control circuit <NUM> controls the regulated voltage <NUM> by controlling the channel conductance of the transistor <NUM>, which, in turn, controls the voltage drop across the transistor <NUM>. For example, to increase the regulated voltage <NUM>, the control circuit <NUM> increases the channel conductance of the transistor <NUM> (i.e., decreases the resistance of the transistor <NUM>). The increased channel conductance reduces the voltage drop across the transistor <NUM>, thereby raising the regulated voltage <NUM>. To decrease the regulated voltage <NUM>, the control circuit <NUM> decreases the channel conductance of the transistor <NUM> (i.e., increases the resistance of the transistor <NUM>). The decreased channel conductance increases the voltage drop across the transistor <NUM>, thereby lowering the regulated voltage <NUM>.

For the example in which the transistor <NUM> is implemented with an NFET (shown in the example in <FIG>), the control circuit <NUM> increases the channel conductance of the transistor <NUM> by increasing the voltage level of the control signal <NUM> and decreases the channel conductance of the transistor <NUM> by decreasing the voltage level of the control signal <NUM>. For the exemplary implementation of the control circuit <NUM> shown in <FIG>, the control signal <NUM> is provided by the output of the operational amplifier <NUM>.

As discussed above, the buffer <NUM> may be used in an LO path that provides an LO signal to a mixer <NUM>. In certain aspects, multiple instances (i.e., copies) of the buffer <NUM> may be used in an LO network that distributes an LO signal to multiple mixers. In this regard, <FIG> shows an example of an LO network that distributes an LO signal from an LO (not shown) to a first mixer <NUM>-<NUM> and a second mixer <NUM>-<NUM>. Although two mixers are shown in the example in <FIG>, it is to be appreciated that the LO network may distribute the LO signal to more than two mixers. In this example, the LO network includes a first buffer <NUM>-<NUM> configured to buffer the LO signal for the first mixer <NUM>-<NUM> and a second buffer <NUM>-<NUM> configured to buffer the LO signal for the second mixer <NUM>-<NUM>. Each of the buffers <NUM>-<NUM> and <NUM>-<NUM> is a separate instance of the buffer <NUM> shown in <FIG>, and includes a respective transconductance driver <NUM>-<NUM> and <NUM>-<NUM> and a respective transformer <NUM>-<NUM> and <NUM>-<NUM>.

In an example, the first mixer <NUM>-<NUM> is used in a transmitter to frequency upconvert an intermediate-frequency signal into an RF signal for transmission, and the second mixer <NUM>-<NUM> is used in a receiver to frequency downconvert a received RF signal into an intermediate-frequency signal. In this example, the receiver and transmitter may be part of a transceiver that switches between transmitting and receiving (e.g., half duplex), but does not transmit and receive simultaneously. Thus, in this example, only one of the first and second mixer <NUM>-<NUM> and <NUM>-<NUM> is used at a given time.

<FIG> shows an example of a feedback circuit for tracking and controlling the output voltage swings of the first and second buffers <NUM>-<NUM> and <NUM>-<NUM> one at a time. In this example, the feedback circuit includes first and second peak detectors <NUM>-<NUM> and <NUM>-<NUM>, first and second replica circuits <NUM>-<NUM> and <NUM>-<NUM>, a multiplexer <NUM>, an operational amplifier <NUM>, and a voltage regulator <NUM>. In this example, the operational amplifier <NUM> and the regulator <NUM> are common to the first and second buffers <NUM>-<NUM> and <NUM>-<NUM>. The feedback circuit is able to use the same operational amplifier <NUM> and regulator <NUM> for the first and second buffers <NUM>-<NUM> and <NUM>-<NUM> since only one of the first and second mixers <NUM>-<NUM> and <NUM>-<NUM> is used at a time. The first and second peak detectors <NUM>-<NUM> and <NUM>-<NUM> may each be implemented using the exemplary peak detector <NUM> shown in <FIG>, and the first and second replica circuits <NUM>-<NUM> and <NUM>-<NUM> may each be implemented using the exemplary replica circuit <NUM> shown in <FIG>.

The first peak detector <NUM>-<NUM> is configured to detect the output voltage swing of the first buffer <NUM>-<NUM>, and generate a first sense voltage (labeled "Vsen_1") based on the detected output voltage swing. The first replica circuit <NUM>-<NUM> is configured to generate a first reference voltage (labeled "Vref_1") based on the target voltage. The second peak detector <NUM>-<NUM> is configured to detect the output voltage swing of the second buffer <NUM>-<NUM>, and generate a second sense voltage (labeled "Vsen_2") based on the detected output voltage swing. The second replica circuit <NUM>-<NUM> is configured to generate a second reference voltage (labeled "Vref_2") based on the target voltage.

The first and second sense voltages Vsen_1 and Vsen_2 and the first and second references voltages Vref_1 and Vref_2 are input to the multiplexer <NUM>. The multiplexer <NUM> selects one of the sense voltages and one of the reference voltages depending on which one of the mixers <NUM>-<NUM> and <NUM>-<NUM> is being used at a given time. For example, if the first mixer <NUM>-<NUM> is currently being used, then the multiplexer <NUM> selects the first sense voltage Vsen_1 and the first reference voltage Vref_1. The multiplexer <NUM> couples the selected sense voltage to the minus input of the amplifier <NUM>, and couples the selected reference voltage to the positive input of the amplifier <NUM>. In this regard, the multiplexer <NUM> may receive a select signal (labeled "Sel") indicating one of the sense voltages and one of the reference voltages, and select the sense voltage and the reference voltage indicated by the select signal Sel.

The operational amplifier <NUM> generates a control signal <NUM> based on a comparison of the selected sense voltage and reference voltage, and outputs the control signal <NUM> to the regulator <NUM>. The control signal <NUM> controls a regulated voltage <NUM> generated by the regulator <NUM>, in which the regulated voltage <NUM> is provided to the input inductor of the first buffer <NUM>-<NUM> (e.g., at the center tap of the input inductor of the first buffer <NUM>-<NUM>) and the input inductor of the second buffer <NUM>-<NUM> (e.g., at the center tap of the input inductor of the second buffer <NUM>-<NUM>).

In operation, the feedback circuit adjusts the regulated voltage <NUM> based on feedback of the output voltage swing of the buffer <NUM>-<NUM> or <NUM>-<NUM> corresponding to the mixer <NUM>-<NUM> or <NUM>-<NUM> that is currently being used such that the output voltage swing is approximately equal to the target voltage swing. In the example in <FIG>, each of the peak detectors <NUM>-<NUM> and <NUM>-<NUM> is biased by the bias voltage Vbias, each of the replica circuits <NUM>-<NUM> to <NUM>-<NUM> is biased by the target voltage Vtarget, and the target voltage swing is approximately equal to the target voltage Vtarget minus the bias voltage Vbias (i.e., Vtarget - Vbias).

Although <FIG> shows an example in which the feedback circuit includes separate replica circuits <NUM>-<NUM> and <NUM>-<NUM> for the first and second buffers <NUM>-<NUM> and <NUM>-<NUM>, it is to be appreciated that the present disclosure is not limited to this example. For example, <FIG> shows an example in which the feedback circuit includes a common replica circuit <NUM> for the first and second buffers <NUM>-<NUM> and <NUM>-<NUM> instead of the separate replica circuits <NUM>-<NUM> and <NUM>-<NUM> shown in <FIG>. In this example, the reference voltage (labeled "Vref") generated by the replica circuit <NUM> is coupled to the positive input of the amplifier <NUM>. Similar to the multiplexer <NUM> in <FIG>, the multiplexer <NUM> selects one of the sense voltages (labeled "Vsen_1" and "Vsen_2") based on the select signal (labeled "Sel"), and couples the selected sense voltage to the minus input of the amplifier <NUM>. In this example, the multiplexer <NUM> does not need to select between the reference voltages (labeled "Vref_1" and "Vref_2") shown in <FIG> since the buffers <NUM>-<NUM> and <NUM>-<NUM> share the replica circuit <NUM> in this example.

<FIG> shows another example in which the feedback circuit includes a common peak detector <NUM> for the buffers <NUM>-<NUM> and <NUM>-<NUM>. In this example, the sense voltage generated by the peak detector <NUM> is coupled to the minus input of the amplifier <NUM>. In this example, the feedback circuit includes a multiplexer <NUM> configured to selectively couple the differential output of one of the first and second buffers <NUM>-<NUM> and <NUM>-<NUM> to the peak detector <NUM> at a time. The multiplexer <NUM> includes a first differential input coupled to the differential output of the first buffer <NUM>-<NUM>, a second differential input coupled to the differential output of the second buffer <NUM>-<NUM>, and a differential output coupled to the differential input of the peak detector <NUM>. In operation, the multiplexer <NUM> selects the differential output of one of the first and second buffers <NUM>-<NUM> and <NUM>-<NUM> based on the select signal (labeled "Sel"), and couples the selected differential output to the peak detector <NUM>. In certain aspects, the select signal selects the differential output of the buffer corresponding to the mixer that is currently being used.

<FIG> shows an exemplary implementation of the bias circuit <NUM> in the transconductance driver <NUM> according to certain aspects of the present disclosure. In this example, the bias circuit <NUM> includes a current source <NUM> and a current-mirror transistor <NUM> (e.g., NFET) for setting the bias current of the transconductance driver <NUM>. The current source <NUM> is configured to source a current (e.g., a DC current). The current source <NUM> is coupled between the supply rail and the drain of the current-mirror transistor <NUM>. The drain and gate of the current-mirror transistor <NUM> are tied together, and the source of the current-mirror transistor <NUM> is coupled to ground. The gate of the current-mirror transistor <NUM> is coupled to the gate of the first transistor <NUM> through a first gate resistor (labeled "Rg1") and the gate of the second transistor <NUM> through a second gate resistor (labeled "Rg2"). The current-mirror transistor <NUM> forms a current mirror with the first and second transistors <NUM> and <NUM>, in which the current mirror biases the gates of the first and second transistors <NUM> and <NUM> such that the current flowing into the current-mirror transistor <NUM> from the current source <NUM> is mirrored at the first and second transistors <NUM> and <NUM>.

In operation, the current of the current source <NUM> flows into the current-mirror transistor <NUM>, and is mirrored at the first and second transistors <NUM> and <NUM>. As a result, the bias current at the first transistor <NUM> is equal to or proportional to the current sourced by the current source <NUM>, and the bias current at the second transistor <NUM> that is equal to or proportional to the current sourced by the current source <NUM>. Thus, in this example, the bias current of the transconductance driver <NUM> is set by the current of the current source <NUM>. As discussed further below, the current source <NUM> may have an adjustable current to enable adjustment of the bias current of the transconductance driver <NUM>.

<FIG> shows another example of a feedback circuit <NUM> for tracking and controlling the output voltage swing of the buffer <NUM> according to certain aspects of the present disclosure. The feedback circuit <NUM> adjusts the output voltage swing of the buffer <NUM> by adjusting the bias current of the transconductance driver <NUM>. Thus, in this example, the bias current of the transconductance driver <NUM> is the parameter that is adjusted to control the output voltage swing instead of the regulated voltage <NUM> at the input inductor <NUM>.

In the example in <FIG>, the center tap <NUM> of the input inductor <NUM> is coupled to the voltage supply rail. Also, the current source <NUM> in the transconductance driver <NUM> has an adjustable current that allows the feedback circuit <NUM> to electrically adjust the bias current of the transconductance driver <NUM>, as discussed further below. In the example in <FIG>, the current source <NUM> is implemented with a current-source transistor <NUM> (e.g., NFET), in which the drain of the current-source transistor <NUM> is coupled to the supply rail, and the source of the current-source transistor <NUM> is coupled to the drain of the current-mirror transistor <NUM>. In this example, the current of the current source <NUM> is controlled by the gate voltage of the current-source transistor <NUM>. Since the current of the current source <NUM> is mirrored at the first and second transistors <NUM> and <NUM> by the current-mirror transistor <NUM>, the gate voltage of the current-source transistor <NUM> controls the bias current at the first and second transistors <NUM> and <NUM>. In this example, the current bias may increase when the gate voltage is increased, and decrease when the gate voltage is decreased.

In certain aspects, the feedback circuit <NUM> is configured to detect the output voltage swing at the output inductor <NUM>, and control the bias current of the transconductance driver <NUM> based on the detected output voltage swing. In these aspects, the feedback circuit <NUM> may control the bias current based on the detected output voltage swing by comparing the detected output voltage swing with a target voltage swing, and adjusting the bias current in a direction that reduces the difference between the output voltage swing and the target voltage swing. In the example in <FIG>, the feedback circuit <NUM> controls the bias current of the transconductance driver <NUM> by controlling the gate voltage of the current-source transistor <NUM>, as discussed above.

In the example in <FIG>, the feedback circuit <NUM> includes a peak detector <NUM> and a control circuit <NUM> coupled in a feedback loop <NUM>. The peak detector <NUM> has a differential input coupled to the differential output of the buffer <NUM>. The peak detector <NUM> is configured to detect the output voltage swing at the differential output of the buffer <NUM>, and generate a swing detection signal <NUM> based on the detected output voltage swing. The output voltage swing may be approximately equal to the peak difference between the voltage Vp at the positive output the buffer <NUM> and the voltage Vm at the minus output of the buffer <NUM>. In certain aspects, the swing detection signal <NUM> may be a voltage that is related (e.g., proportional) to the output voltage swing of the buffer <NUM>.

The control circuit <NUM> is configured to receive the swing detection signal <NUM> from the peak detector <NUM>, and generate a control signal <NUM> based on the swing detection signal <NUM>. The control signal <NUM> is input to the transconductance driver <NUM> to control the current bias of the transconductance driver <NUM>. For the example in which the current source <NUM> is implemented with the current-source transistor <NUM>, the control signal <NUM> is input to the gate of the current-source transistor <NUM> and controls the current of the current-source transistor <NUM> by controlling the gate voltage of the current-source transistor <NUM>. Since the current of the current-source transistor <NUM> is mirrored at the first and second transistors <NUM> and <NUM>, the control signal <NUM> controls the bias current at the first and second transistors <NUM> and <NUM>.

In certain aspects, the control circuit <NUM> generates the control signal <NUM> by comparing the swing detection signal <NUM> with a target reference signal corresponding to the target voltage swing, and generating the control signal <NUM> based on the comparison. In these aspects, the target reference signal provides a reference point with which the swing detection signal <NUM> is compared to assess whether the output voltage swing is above or below the target voltage swing. In one example, the output voltage swing is approximately equal to the target voltage swing when the swing detection signal <NUM> is approximately equal to the reference target signal. In this example, the reference target signal indicates the value (e.g., voltage) that the swing detection signal <NUM> should have when the output voltage swing is equal to the target voltage swing. If the swing detection signal <NUM> is above the reference target signal, then the output voltage swing is above the target voltage swing, and, if the swing detection signal <NUM> is below the reference target signal, then the output voltage swing is below the target voltage swing. In this example, the control circuit <NUM> adjusts the output voltage swing to be closer to the target voltage swing by adjusting the bias current of the transconductance driver <NUM> in a direction that reduces the difference between the swing detection signal <NUM> and the target reference signal.

Thus, the feedback circuit <NUM> adjusts the bias current of the transconductance driver <NUM> based on feedback of the output voltage swing to keep the output voltage swing of the buffer <NUM> close to the target voltage swing. The feedback circuit <NUM> is able to keep the output voltage swing close to the target voltage swing across PVT corners, thereby significantly reducing variation in the output voltage swing across PVT corners. The reduced swing variation across PVT corners mitigates the excess power consumption, signal path gain variation, increased LO leakage, and/or reliability issues discussed above with reference to <FIG>. Further, when the buffer <NUM> is placed at the end of an LO path, the feedback circuit <NUM> is able to clean up swing variation caused by one or more others devices (e.g., amplifier, phase shifter, etc.) in the LO path preceding the buffer <NUM>, as discussed above.

The output voltage swing of the buffer <NUM> may increase exponentially with bias current, causing the loop gain of the feedback loop <NUM> to vary drastically, especially at low output swing. As a result, it may be more difficult to achieve good loop stability for the feedback loop <NUM> compared with the feedback loop <NUM>, in which the approximately linear relationship between the regulated voltage <NUM> and the output voltage swing provides better loop stability.

<FIG> shows exemplary implementations of the peak detector <NUM> and the control circuit <NUM> according to certain aspects of the present disclosure. In the example in <FIG>, the peak detector <NUM> includes a peak detector <NUM> implemented using the exemplary peak detector <NUM> shown in <FIG>. Accordingly, the description of the exemplary peak detector <NUM> in <FIG> applies to the peak detector <NUM> in <FIG>, and is therefore not repeated here for brevity. The peak detector <NUM> generates the sense voltage Vsen at node <NUM> based on the output voltage swing. As discussed above, the sense voltage Vsen is related to the output voltage swing (e.g., by a ratio that depends on the bias voltage Vbias).

In this example, the peak detector <NUM> also includes an operational amplifier <NUM> and a replica circuit <NUM>. The operational amplifier <NUM> and the replica circuit <NUM> are used to reduce the PVT effect on the sense voltage Vsen to generate a more accurate swing detection signal <NUM>, as discussed further below. The replica circuit <NUM> may be implemented with the exemplary replica circuit <NUM> shown in <FIG>. However, in this example, the gates of the first and second transistors <NUM> and <NUM> (shown in <FIG>) are coupled to the output <NUM> of the operational amplifier <NUM> instead of being biased by the target voltage Vtarget. The replica circuit <NUM> generates the reference voltage Vref based on the output voltage of the operational amplifier <NUM>. Note that the replica circuit <NUM> in this example in not used to set the target voltage swing.

The sense voltage Vsen is input to the minus input of the operational amplifier <NUM>, and the reference voltage Vref is input to the positive input of the operation amplifier <NUM>. The output <NUM> of the operational amplifier <NUM> provides the swing detection signal <NUM> discussed above. The output <NUM> of the operational amplifier <NUM> is also coupled to the gates of the first and second transistors <NUM> and <NUM> (shown in <FIG>) of the replica circuit <NUM>.

As discussed above, the replica circuit <NUM> is used to cancel out variation in the sense voltage Vsen due to PVT conditions. In this regard, the replica circuit <NUM> may be integrated on the same chip (i.e., die) as the peak detector <NUM>. In an aspect, the replica circuit <NUM> may be located in close proximity to the peak detector <NUM> so that the replica circuit <NUM> is subjected to approximately the same PVT conditions as the peak detector <NUM>. As a result, the variation in the reference voltage Vref due to PVT conditions is approximately the same as the variation in the sense voltage Vsen due to PVT conditions. Since the operational amplifier <NUM> takes the difference of the sense voltage Vsen and the reference voltage Vref at its inputs, variation in the reference voltage Vref due to PVT conditions approximately cancels out the variation in the sense voltage Vsen due to PVT conditions. This reduces the PVT effect on the output voltage <NUM> of the operational amplifier <NUM>. The output <NUM> of the operational amplifier <NUM> provides the swing detection signal <NUM> discussed above, in which the PVT effect is reduced on the swing detection signal <NUM> using the replica circuit <NUM>.

The control circuit <NUM> includes a control amplifier <NUM> (e.g., an operational amplifier). The output voltage <NUM> of the operational amplifier <NUM> is input to the minus input of the control amplifier <NUM>, and the target voltage Vtarget is input to the positive input of the control amplifier <NUM>. The output of the control amplifier <NUM> provides the control signal <NUM> to the current source <NUM> of the transconductance driver <NUM>. In this example, the target voltage Vtarget corresponds to the target reference signal discussed above.

In operation, the control amplifier <NUM> adjusts the control signal <NUM> in a direction that reduces the difference between the output voltage <NUM> of the operational amplifier <NUM> and the target voltage Vtarget (i.e., adjusts the output voltage <NUM> to be closer to the target voltage Vtarget). As a result, the control amplifier <NUM> forces the output voltage <NUM> of the operational amplifier <NUM> to be approximately equal to the target voltage Vtarget. This occurs when the output voltage swing of the buffer <NUM> is approximately equal to alpha*(Vtarget-Vbias), where alpha is a linear coefficient. As a result, the feedback circuit <NUM> adjusts the bias current such that the output voltage swing of the buffer <NUM> is approximately equal to alpha*(Vtarget - Vbias). Thus, in this example, the target voltage swing of the feedback circuit <NUM> is approximately equal to alpha*(Vtarget - Vbias).

Therefore, for a given bias voltage Vbias, the target voltage swing may be set by setting the target voltage Vtarget input to the control amplifier <NUM> according to the desired target voltage swing. The bias voltage Vbias and the Vtarget may be generated by the voltage generator <NUM> shown in <FIG>. The voltage generator <NUM> may be configured to set the voltage levels of the bias voltage Vbias and the target voltage Vtarget such that alpha*(Vtarget - Vbias) equals the desired target voltage swing. Alpha may be determined by running simulations and/or performing measurements on the feedback circuit <NUM> and buffer <NUM>.

Note that in the example in <FIG>, the reference voltage Vref is used for canceling out the PVT effect on the sense voltage Vsen. In the example in <FIG>, the reference voltage Vref is used for both setting the target voltage swing and canceling out the PVT effect.

<FIG> shows an exemplary method <NUM> for controlling an output voltage swing of a buffer according to certain aspects of the present disclosure. The buffer (e.g., buffer <NUM>) includes a transformer (e.g., transformer <NUM>) and a driver (e.g., transconductance driver <NUM>), the transformer includes an input inductor (e.g., input inductor <NUM>) and an output inductor (e.g., output inductor <NUM>), the input inductor is driven by the driver, and the input inductor is magnetically coupled to the output inductor. The method <NUM> may be performed by the feedback circuit <NUM>.

At block <NUM>, the output voltage swing is detected at the output inductor. For example, the output voltage swing may be detected using a peak detector (e.g., peak detector <NUM>).

At block <NUM>, a regulated voltage at the input inductor is controlled based on the detected output voltage swing. The regulated voltage (e.g., regulated voltage <NUM>) may be applied to a center tap of the input inductor.

In certain aspects, controlling the regulated voltage based on the detected output voltage swing may include comparing the detected output voltage swing with a target voltage swing, and controlling the regulated voltage based on the comparison. Controlling the regulated voltage based on the comparison may include adjusting the regulated voltage in a direction that reduces a difference between the output voltage swing and the target voltage swing.

Buffers according to aspects of the present disclosure may be employed in a wireless communication device (e.g., a wireless mobile device, a base station, customer premises equipment (CPE), etc.) to buffer one or more LO signals distributed to mixers in the device. In certain aspects, the wireless communication device (e.g., a <NUM> device) includes a phased antenna array that allows the device to receive and/or transmit signals with high directivity using beamforming for increased range. In these aspects, the mixers may be used in a receiver and/or a transmitter for the phased antenna array.

In this regard, <FIG> shows an example of a receiver <NUM> configured to receive signals from antennas <NUM>-<NUM> to <NUM>-n in a phased antenna array. In this example, the receiver <NUM> includes multiple receive chains <NUM>-<NUM> to <NUM>-n, in which each of the receive chains <NUM>-<NUM> to <NUM>-n is coupled to a respective one of the antennas <NUM>-<NUM> to <NUM>-n. Each of the receive chains <NUM>-<NUM> to <NUM>-n includes a respective low noise amplifier (LNA) <NUM>-<NUM> to <NUM>-n and a respective mixer <NUM>-<NUM> to <NUM>-n. In each receive chain <NUM>-<NUM> to <NUM>-n, the respective LNA <NUM>-<NUM> to <NUM>-n is configured to amplify the signal from the respective antenna <NUM>-<NUM> to <NUM>-n in the array, and the respective mixer <NUM>-<NUM> to <NUM>-n is configured to mix the signal from the respective LNA <NUM>-<NUM> to <NUM>-n with a respective LO signal to downconvert the frequency of the signal. In this example, the LO signal to each mixer <NUM>-<NUM> to <NUM>-n is phase shifted by a respective phase shift prior to mixing to set the receive direction of the phased antenna array using beamforming. For each mixer <NUM>-<NUM> to <NUM>-n, the phase shift of the respective LO signal may be set based on a desired receive direction for the phased antenna array. It is to be appreciated that each receive chain may include one or more additional components (not shown).

The receiver <NUM> also includes a combiner <NUM> and a combined receive circuit <NUM>. The combiner <NUM> is configured to combine the output signals of the receive chains <NUM>-<NUM> to <NUM>-n into a combined signal. The combiner <NUM> outputs the combined signal to the combined receive circuit <NUM>, which processes the combined signal. Processing performed by the combined receive circuit <NUM> may include amplification, filtering, analog-to-digital conversion, etc. The combined receive circuit <NUM> outputs the processed combined signal to a baseband processor <NUM>, which may process the signal from the combined receive circuit <NUM> to recover data from the signal. The recovered data may be stored in a memory on the wireless communication device and/or sent to another processor (e.g., a central processing unit (CPU)) for further processing.

<FIG> shows an example of an LO network for providing the LO signal to the mixer <NUM>-<NUM> in receive chain <NUM>-<NUM>. In this example, the LO network includes an LO <NUM>, a phase shifter <NUM>, and a buffer <NUM> coupled to the mixer <NUM>-<NUM>. The output voltage swing of the buffer <NUM> may be controlled using the exemplary feedback circuit <NUM> shown in <FIG> or the exemplary feedback circuit <NUM> shown in <FIG>. In this example, the LO <NUM> is coupled to the phase shifter <NUM>, and the phase shifter <NUM> is coupled to the input of the buffer <NUM>. In operation, the LO <NUM> generates an LO signal, and the phase shifter <NUM> shifts the phase of the LO signal based on a desired receive direction for the phased antenna array. The buffer <NUM> receives the phase-shifted LO signal from the phase shifter <NUM> and drives the mixer <NUM>-<NUM> based on the phase-shifted LO signal. It is to be appreciated that the LO network may include one or more additional components (not shown) in the LO path between the LO <NUM> and the mixer <NUM>-<NUM>.

It is to be appreciated that the LO signal for each of the other mixers <NUM>-<NUM> to <NUM>-n shown in <FIG> may be provided by a respective LO network similar to the one shown in <FIG>. In one example, the LO networks may share a common LO <NUM>, in which each LO network phase shifts the LO signal from the LO <NUM> by a respective phase shift based on the desired receive direction for the phased antenna array.

<FIG> shows another example of a receiver <NUM> configured to receive signals from the antennas <NUM>-<NUM> to <NUM>-n in the phased antenna array. In this example, the frequency conversion is performed after signal combining, as discussed further below. In this example, the receiver <NUM> includes multiple receive chains <NUM>-<NUM> to <NUM>-n, in which each of the receive chains <NUM>-<NUM> to <NUM>-n is coupled to a respective one of the antennas <NUM>-<NUM> to <NUM>-n. Each of the receive chains <NUM>-<NUM> to <NUM>-n includes a respective LNA <NUM>-<NUM> to <NUM>-n and a respective phase shifter <NUM>-<NUM> to <NUM>-n. In each receive chain <NUM>-<NUM> to <NUM>-n, the respective LNA <NUM>-<NUM> to <NUM>-n is configured to amplify the signal from the respective antenna <NUM>-<NUM> to <NUM>-n in the array, and the respective the phase shifter <NUM>-<NUM> to <NUM>-n is configured shift the phase of the signal from the respective LNA <NUM>-<NUM> to <NUM>-n by a respective phase shift. The phase shift for each phase shifter <NUM>-<NUM> to <NUM>-n may be set based on a desired receive direction for the phased antenna array using beamforming. It is to be appreciated that each receive chain may include one or more additional components (not shown).

The receiver <NUM> also includes a combiner <NUM>, a mixer <NUM>, and a combined receive circuit <NUM>. The combiner <NUM> is configured to combine the output signals of the receive chains <NUM>-<NUM> to <NUM>-n into a combined signal. The combiner <NUM> outputs the combined signal to the mixer <NUM>. The mixer <NUM> mixes the combined signal with an LO signal to downconvert the frequency of the combined signal. The mixer <NUM> outputs the frequency downconverted signal to the combined receive circuit <NUM>, which processes the combined signal. Processing performed by the combined receive circuit <NUM> may include amplification, filtering, analog-to-digital conversion, etc. The combined receive circuit <NUM> outputs the combined signal to a baseband processor <NUM>, which may process the combined signal from the combined receive circuit <NUM> to recover data from the signal. The recovered data may be stored in a memory on the wireless communication device and/or sent to another processor (e.g., a CPU) for further processing.

<FIG> shows an example of an LO network for providing the LO signal to the mixer <NUM> in the receiver <NUM>. In this example, the LO network includes an LO <NUM>, and a buffer <NUM> coupled to the mixer <NUM>. The output voltage swing of the buffer <NUM> may be controlled using the exemplary feedback circuit <NUM> shown in <FIG> or the exemplary feedback circuit <NUM> shown in <FIG>. In this example, the LO <NUM> is coupled to the input of the buffer <NUM>. In operation, the LO <NUM> generates an LO signal, which is input to the input of the buffer <NUM>. The buffer <NUM> receives the LO signal and drives the mixer <NUM> based on the LO signal. It is to be appreciated that the LO network may include one or more additional components (not shown) in the LO path between the LO <NUM> and the mixer <NUM>.

<FIG> shows an example of a transmitter <NUM> for a phased antenna array according to aspects of the present disclosure. In this example, the transmitter <NUM> includes a transmit circuit <NUM>, a splitter <NUM>, and multiple transmit chains <NUM>-<NUM> to <NUM>-n. Each of the transmit chains <NUM>-<NUM> to <NUM>-n has an input coupled to the splitter <NUM> and an output coupled to a respective one of the antennas <NUM>-<NUM> to <NUM>-n in the phased antenna array.

In operation, a baseband processor <NUM> outputs a signal to the transmit circuit <NUM>. The transmit circuit <NUM> processes the received signal for transmission. Processing performed by the transmit circuit <NUM> may include digital-to-analog conversion, amplification, etc. The transmit circuit <NUM> outputs the processed signal to the splitter <NUM>. The splitter <NUM> splits the signal from the transmit circuit <NUM> into multiple signals, and inputs each of the multiple signals to a respective one of the transmit chains <NUM>-<NUM> to <NUM>-n.

Each of the transmit chains <NUM>-<NUM> to <NUM>-n includes a respective mixer <NUM>-<NUM> to <NUM>-n and a respective power amplifier (PA) <NUM>-<NUM> to <NUM>-n. In each transmit chain <NUM>-<NUM> to <NUM>-n, the respective mixer <NUM>-<NUM> to <NUM> mixes the respective signal from the splitter <NUM> with a respective LO signal, and the respective PA <NUM>-<NUM> to <NUM>-n amplifies the signal from the respective mixer. The output signal of each transmit chain <NUM>-<NUM> to <NUM>-n is fed to the respective antenna <NUM>-<NUM> to <NUM>-n in the phased antenna array. In this example, the LO signal to each mixer <NUM>-<NUM> to <NUM>-n is phase shifted by a respective phase shift prior to mixing to set the transmit direction of the phased antenna array using beamforming. For each mixer <NUM>-<NUM> to <NUM>-n, the phase shift of the respective LO signal may be set based on a desired transmit direction for the phased antenna array. It is to be appreciated that each receive chain may include one or more additional components (not shown).

<FIG> shows an example of an LO network for providing the LO signal to the mixer <NUM>-<NUM> in transmit chain <NUM>-<NUM>. In this example, the LO network includes an LO <NUM>, a phase shifter <NUM>, and a buffer <NUM> coupled to the mixer <NUM>-<NUM>. The output voltage swing of the buffer <NUM> may be controlled using the exemplary feedback circuit <NUM> shown in <FIG> or the exemplary feedback circuit <NUM> shown in <FIG>. In this example, the LO <NUM> is coupled to the phase shifter <NUM>, and the phase shifter <NUM> is coupled to the input of the buffer <NUM>. In operation, the LO <NUM> generates an LO signal, and the phase shifter <NUM> shifts the phase of the LO signal based on a desired transmit direction for the phased antenna array. The buffer <NUM> receives the phase-shifted LO signal from the phase shifter <NUM> and drives the mixer <NUM>-<NUM> based on the phase-shifted LO signal. It is to be appreciated that the LO network may include one or more additional components (not shown) in the LO path between the LO <NUM> and the mixer <NUM>-<NUM>.

It is to be appreciated that the LO signal for each of the other mixers <NUM>-<NUM> to <NUM>-n shown in <FIG> may be provided by a respective LO network similar to the one shown in <FIG>. In one example, the LO networks may share a common LO <NUM>, in which each LO network shifts the LO signal from the LO <NUM> by a respective phase shift based on the desired transmit direction for the phased antenna array.

<FIG> shows another example of a transmitter <NUM> for a phased antenna array according to aspects of the present disclosure. In this example, frequency upconversion is performed before signal splitting, as discussed further below. The transmitter <NUM> includes a transmit circuit <NUM>, a mixer <NUM>, a splitter <NUM>, and multiple transmit chains <NUM>-<NUM> to <NUM>-n. Each of the transmit chains <NUM>-<NUM> to <NUM>-n has an input coupled to the splitter <NUM> and an output coupled to a respective one of the antennas <NUM>-<NUM> to <NUM>-n in the phased antenna array.

In operation, a baseband processor <NUM> outputs a signal to the transmit circuit <NUM>. The transmit circuit <NUM> processes the received signal for transmission. Processing performed by the transmit circuit <NUM> may include digital-to-analog conversion, amplification, etc. The transmit circuit <NUM> outputs the processed signal to the mixer <NUM>, which mixes the processed signal with an LO signal to upconvert the frequency of the processed signal. The mixer <NUM> outputs the frequency upconverted signal to the splitter <NUM>. The splitter <NUM> splits the signal from the mixer <NUM> into multiple signals, and inputs each of the multiple signals to a respective one of the transmit chains <NUM>-<NUM> to <NUM>-n.

Each of the transmit chains <NUM>-<NUM> to <NUM>-n includes a respective phase shifter <NUM>-<NUM> to <NUM>-n and a respective power amplifier (PA) <NUM>-<NUM> to <NUM>-n. In each transmit chain <NUM>-<NUM> to <NUM>-n, the respective phase shifter <NUM>-<NUM> to <NUM>-n shifts the phase of the respective signal from the splitter <NUM> by a respective phase shift, and the respective PA <NUM>-<NUM> to <NUM>-n amplifies the signal from the respective phase shifter. The phase shift for each phase shifter <NUM>-<NUM> to <NUM>-n may be set based on a desired transmit direction for the phased antenna array. The output signal of each transmit chain <NUM>-<NUM> to <NUM>-n is fed to the respective antenna <NUM>-<NUM> to <NUM>-n in the phased antenna array.

<FIG> shows an example of an LO network for providing the LO signal to the mixer <NUM> in the transmitter <NUM>. In this example, the LO network includes an LO <NUM>, and a buffer <NUM> coupled to the mixer <NUM>. The output voltage swing of the buffer <NUM> may be controlled using the exemplary feedback circuit <NUM> shown in <FIG> or the exemplary feedback circuit <NUM> shown in <FIG>. In this example, the LO <NUM> is coupled to the input of the buffer <NUM>. In operation, the LO <NUM> generates an LO signal, which is input to the input of the buffer <NUM>. The buffer <NUM> receives the LO signal and drives the mixer <NUM> based on the LO signal. It is to be appreciated that the LO network may include one or more additional components (not shown) in the LO path between the LO <NUM> and the mixer <NUM>.

The control circuits <NUM> and <NUM> discussed above may be implemented with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. A processor may perform the functions described herein by executing software comprising code for performing the functions. The software may be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and/or a magnetic disk.

Any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

The term "coupled" is used herein to refer to the direct or indirect electrical coupling between two structures. As used herein, two values (e.g., voltages) are "approximately" equal if one of the values is within <NUM> percent to <NUM> percent of the other value. As used herein, controlling the regulated voltage <NUM> is understood to mean controlling the voltage level of the regulated voltage <NUM>.

Claim 1:
An apparatus for buffering an input signal, comprising:
a transformer (<NUM>) including an input inductor (<NUM>) and an output inductor (<NUM>), wherein the input inductor (<NUM>) is magnetically coupled to the output inductor (<NUM>);
a transconductance driver (<NUM>) configured to drive the input inductor (<NUM>) based on the input signal; and
a feedback circuit (<NUM>) configured to:
detect an output voltage swing at the output inductor (<NUM>);
generate a regulated voltage at the input inductor (<NUM>); and
control the regulated voltage based on a comparison of the detected output voltage swing with a target voltage swing;
wherein said control comprises: comparing the detected output voltage swing with a target voltage swing; and adjusting the regulated voltage based on the comparison in a direction that reduces a difference between the output voltage swing and the target voltage swing.