Patent Description:
<CIT> discloses a semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a first encapsulant covering at least a portion of each of the inactive surface and side surfaces of the semiconductor chip, and having one or more recessed portions recessed towards the inactive surface of the semiconductor chip; a metal layer disposed on the first encapsulant, and filling at least a portion of each of the recessed portions; and an interconnect structure disposed on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. A surface of the metal layer in contact with the first encapsulant has a surface roughness greater than a surface roughness of a surface of the metal layer spaced apart from the first encapsulant.

<CIT> discloses a semiconductor chip package includes a substrate; a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on an active surface of the semiconductor die, and a passivation layer covering perimeter of the bond pad, wherein a bond pad opening in the passivation layer exposes a central area of the bond pad; a conductive paste post printed on the exposed central area of the bond pad; and a bonding wire secured to a top surface of the conductive paste post. The conductive paste post preferably comprises copper paste.

<CIT> discloses a semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

A conventional chip package structure has a recognition code printed on a top side of an encapsulant thereof. However, the recognition code is not coplanar with the top side of the encapsulant, such that the recognition code can easily suffer damage that may cause it to become unrecognizable.

In response to the above-referenced technical inadequacy, the present disclosure provides a chip package structure as defined in claim <NUM>. Said chip package structure effectively improves the issues associated with conventional chip package structures.

In one aspect, the present disclosure provides a chip package structure, which includes a substrate, a chip module, an encapsulant, and a recognition contrast layer. The substrate has a first board surface and a second board surface that is opposite to the first board surface. The substrate has a plurality of conductive portions arranged on the second board surface. The chip module is mounted on the first board surface and is electrically coupled to the conductive portions. The encapsulant is formed on the first board surface. The chip module is embedded in the encapsulant. The encapsulant has a patterned trench that is recessed in a top surface thereof and that corresponds in shape to a predetermined two-dimensional (2D) code pattern. The recognition contrast layer is filled in the patterned trench. The recognition contrast layer and the top surface of the encapsulant respectively have different colors that conform to grade A or grade B in the ISO/IEC <NUM> standard. The recognition contrast layer is coplanar with the top surface of the encapsulant so as to jointly form the predetermined 2D code pattern having a planar shape. The patterned trench has a plurality of slots that are separate from each other, and each of the slots has a depth within a range from <NUM> to <NUM>. The chip module includes at least one chip and a plurality of passive components, and wherein the at least one chip and the passive components are mounted on the first board surface, and a top side of the at least one chip is exposed from at least one of the slots and is covered by the recognition contrast layer.

Therefore, the chip package structure of the present disclosure is provided with the predetermined 2D code pattern that is formed by a structural cooperation of the encapsulant and the recognition contrast layer, so that the predetermined 2D code pattern not only provides for high recognition accuracy, but also has a planar shape that is not easily damaged.

Specifically, in the chip package structure provided by the present disclosure, the recognition contrast layer covers inner walls of the slots, thereby effectively preventing the at least one chip from being affected by the external environment.

These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the scope of the appended claims.

Referring to <FIG>, a first embodiment of the present disclosure provides a chip package structure <NUM> preferably being a system in package (SiP). The chip package structure <NUM> includes a substrate <NUM> having a flat shape, a chip module <NUM> mounted on the substrate <NUM>, and a package module <NUM> that is formed on the substrate <NUM>.

It should be noted that the package module <NUM> in the present embodiment is described in cooperation with the substrate <NUM> and the chip module <NUM>. For example, in other embodiments of the present disclosure not shown in the drawings, the package module <NUM> can be used in cooperation with other components.

In the present embodiment, the substrate <NUM> has a first board surface <NUM> and a second board surface <NUM> that is opposite to the first board surface <NUM>, and the substrate <NUM> has a plurality of conductive portions <NUM> arranged on the second board surface <NUM>. The conductive portions <NUM> are metal pads that can be used in a surface mount technology (SMT) manner, but in other embodiments of the present disclosure not shown in the drawings, the conductive portions <NUM> can be other structures (e.g., insertion pins).

The chip module <NUM> is electrically coupled to the conductive portions <NUM> of the substrate <NUM>. The chip module <NUM> includes at least one chip <NUM> and a plurality of passive components <NUM>, and the at least one chip <NUM> and the passive components <NUM> are mounted on the first board surface <NUM>. The connection manner between the at least one chip <NUM> (or the passive components <NUM>) and the substrate <NUM> can be a flip chip manner or a wire bonding manner, but the present disclosure is not limited thereto.

Moreover, the type of the at least one chip <NUM> can be adjusted or changed according to design requirements. For example, the chip <NUM> can be a radio frequency identification (RFID) chip, a mobile payment chip, a machine-to-machine (M2M) chip, a wireless sensor chip, or a communication chip that is formed in other types.

The package module <NUM> includes an encapsulant <NUM> and a recognition contrast layer <NUM> that is formed on a part of the encapsulant <NUM>. It should be noted that any package module provided without directly forming a recognition contrast layer on an encapsulant is different from the package module <NUM> of the present embodiment.

In the present embodiment, the encapsulant <NUM> is a molding compound for being accurately formed in a predetermined shape, but the present disclosure is not limited thereto. The encapsulant <NUM> is formed on the first board surface <NUM> of the substrate <NUM>, and the chip module <NUM> is embedded in the encapsulant <NUM>. In addition, in other embodiments of the present disclosure not shown in the drawings, the encapsulant <NUM> can further extend to cover a surrounding lateral side of the substrate <NUM> and the second board surface <NUM>, but the conductive portions <NUM> need to be exposed from the encapsulant <NUM>.

Furthermore, the encapsulant <NUM> has a patterned trench <NUM> that is recessed in a top surface <NUM> thereof and that corresponds in shape to a predetermined two-dimensional (2D) code pattern. The predetermined 2D code pattern in the present embodiment is a QR code, but the predetermined 2D code pattern can be adjusted or changed according to design requirements. For example, the predetermined 2D code pattern can be a data matrix, an aztec code, a PDF417, a micro PDF, a GS1 databar, or a pharmacode.

Specifically, the patterned trench <NUM> in the present embodiment has a plurality of slots <NUM> that are separate from each other, and each of the slots <NUM> is preferably a laser engraving slot and has a depth D313 within a range from <NUM> to <NUM>. The depths D313 of the slots <NUM> in the present embodiment are the same, but the present disclosure is not limited thereto. For example, in other embodiments of the present disclosure not shown in the drawings, the slots <NUM> can have depths D313 that are slightly different from one another according to design requirements.

In the present embodiment, the slots <NUM> include an outer square slot <NUM>, at least one inner square slot <NUM>, and a plurality of irregular slots <NUM>. An area surrounded by the outer square slot <NUM> substantially occupies at least <NUM>% of an area of the top surface <NUM> of the encapsulant <NUM>, and four corners of the outer square slot <NUM> are respectively spaced apart from four corners of the top surface <NUM> by a same interval. The at least one inner square slot <NUM> and the irregular slots <NUM> are arranged at an inner side of the outer square slot <NUM>, and the at least one inner square slot <NUM> corresponds in position to at least one of the four corners of the outer square slot <NUM>.

In addition, a top side <NUM> of the at least one chip <NUM> is embedded in the encapsulant <NUM> and is spaced apart from at least one of the slots <NUM> adjacent thereto by a distance D211 within a range from <NUM> to <NUM>, but the present disclosure is not limited thereto. In other words, the depth (or the distance D211) of the top side <NUM> of the at least one chip <NUM> with respect to the encapsulant <NUM> is reduced due to an adjacent one of the slots <NUM>, such that a probability of the at least chip <NUM> being affected by the external environment may be increased.

The recognition contrast layer <NUM> and the top surface <NUM> of the encapsulant <NUM> respectively have different colors that conform to grade A or grade B in the ISO/IEC <NUM> standard. In the present embodiment, each of the recognition contrast layer <NUM> and the encapsulant <NUM> is of a single color (e.g., the recognition contrast layer <NUM> is a white toner layer, and the color of the encapsulant <NUM> is black), but the present disclosure is not limited thereto. For example, in other embodiments of the present disclosure not shown in the drawings, the recognition contrast layer <NUM> can be made of a material other than toner.

Specifically, the recognition contrast layer <NUM> is filled in the patterned trench <NUM> and is coplanar with the top surface <NUM> of the encapsulant <NUM>, so that the recognition contrast layer <NUM> and the top surface <NUM> of the encapsulant <NUM> jointly form the predetermined 2D code pattern having a planar shape.

Accordingly, the chip package structure <NUM> of the present embodiment is provided with the predetermined 2D code pattern that is formed by a structural cooperation of the encapsulant <NUM> and the recognition contrast layer <NUM>, so that the predetermined 2D code pattern not only has a high recognition, but also has a planar shape that is not easily damaged. Moreover, the recognition contrast layer <NUM> of the chip package structure <NUM> is provided to cover inner walls of the slots <NUM>, thereby effectively preventing the at least one chip <NUM> from being affected by the external environment.

Furthermore, any 2D code not having a planar shape or not conforming to grade A or grade B in the ISO/IEC <NUM> standard is different the predetermined 2D code pattern of the present embodiment that is formed in a planar shape through the recognition contrast layer <NUM> and the top surface <NUM> of the encapsulant <NUM>.

Referring to <FIG> and <FIG>, a second embodiment of the present disclosure, which is similar to the first embodiment of the present disclosure, is provided. For the sake of brevity, descriptions of the same components in the first and second embodiments of the present disclosure will be omitted herein, and the following description only discloses different features between the first and second embodiments.

In the present embodiment, the chip package structure <NUM> further includes a transparent protective layer <NUM> arranged on an outer side thereof (e.g., the transparent protective layer <NUM> covers the predetermined 2D code pattern having the planar shape), thereby providing a dust-proof effect, a moisture-proof effect, and an anti-corrosion effect to the chip package structure <NUM> (or the predetermined 2D code pattern) through the transparent protective layer <NUM>.

Referring to <FIG> and <FIG>, a third embodiment of the present disclosure, which is similar to the first and second embodiments of the present disclosure, is provided. For the sake of brevity, descriptions of the same components in the first to third embodiments of the present disclosure will be omitted herein, and the following description only discloses different features among the first to third embodiments.

In the present embodiment, a top side <NUM> of the at least one chip <NUM> is exposed from at least one of the slots <NUM> and is covered by the recognition contrast layer <NUM>. In other words, the top side <NUM> of the at least one chip <NUM> forms a bottom of the at least one of the slots <NUM> adjacent thereto. Moreover, the top side <NUM> of the at least one chip <NUM> exposed from the encapsulant <NUM> is covered by the recognition contrast layer <NUM>, thereby effectively preventing the at least one chip <NUM> from being exposed in an external environment through an adjacent one of the slots <NUM>.

Referring to <FIG>, a fourth embodiment of the present disclosure, which is similar to the first to third embodiments of the present disclosure, is provided. For the sake of brevity, descriptions of the same components in the first to fourth embodiments of the present disclosure will be omitted herein, and the following description only discloses different features among the first to fourth embodiments.

In the present embodiment, the encapsulant <NUM> is of a single color (e.g., the color of the encapsulant <NUM> is black), and the recognition contrast layer <NUM> has a plurality of regions 32a, 32b, 32c, 32d respectively having different colors according to design requirements (e.g., the regions 32a, 32b, 32c, 32d can be toner layers having different colors). Any one of the different colors of the recognition contrast layer <NUM> and the color of the encapsulant <NUM> are provided by conforming to grade A or grade B in the ISO/IEC <NUM> standard, thereby allowing the predetermined 2D code pattern to have different appearances.

In conclusion, any one of the chip package structure and the package module of the present disclosure is provided with the predetermined 2D code pattern that is formed by a structural cooperation of the encapsulant and the recognition contrast layer, so that the predetermined 2D code pattern not only provides for high recognition accuracy, but also has a planar shape that is not easily damaged.

Moreover, in the chip package structure provided by the present disclosure, the recognition contrast layer can include different colors according to design requirements, thereby allowing the predetermined 2D code pattern to have different appearances.

Claim 1:
A chip package structure (<NUM>), comprising:
a substrate (<NUM>) having a first board surface (<NUM>) and a second board surface (<NUM>) that is opposite to the first board surface (<NUM>), wherein the substrate (<NUM>) has a plurality of conductive portions (<NUM>) arranged on the second board surface (<NUM>);
a chip module (<NUM>) mounted on the first board surface (<NUM>) and electrically coupled to the conductive portions (<NUM>);
an encapsulant (<NUM>) formed on the first board surface (<NUM>), wherein the chip module (<NUM>) is embedded in the encapsulant (<NUM>), and wherein the encapsulant (<NUM>) has a patterned trench (<NUM>) that is recessed in a top surface (<NUM>) thereof and that corresponds in shape to a predetermined two-dimensional (2D) code pattern; and
a recognition contrast layer (<NUM>) filled in the patterned trench (<NUM>), the chip package structure is characterized in that
the recognition contrast layer (<NUM>) and the top surface (<NUM>) of the encapsulant (<NUM>) respectively have different colors that conform to grade A or grade B in ISO/IEC <NUM> standard;
wherein the recognition contrast layer (<NUM>) is coplanar with the top surface (<NUM>) of the encapsulant (<NUM>) so as to jointly form the predetermined 2D code pattern having a planar shape;
wherein the patterned trench (<NUM>) has a plurality of slots (<NUM>) that are separate from each other, and each of the slots has a depth (D313) within a range from <NUM> to <NUM>;
wherein the chip module (<NUM>) includes at least one chip (<NUM>) and a plurality of passive components (<NUM>), and wherein the at least one chip (<NUM>) and the passive components (<NUM>) are mounted on the first board surface (<NUM>), and a top side (<NUM>) of the at least one chip (<NUM>) is exposed from at least one of the slots (<NUM>) and is covered by the recognition contrast layer (<NUM>).