Patent Description:
Group III nitride semiconductors are important semiconductor materials, including AlN, GaN, InN and compounds of these materials, such as AlGaN, InGaN, AlInGaN and the like. Due to their advantages of direct band gap, wide forbidden band and high breakdown electric field intensity, Group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics and radio frequency devices.

Unlike conventional non-polar semiconductor materials such as Si, Group III nitride semiconductors have polarity. In other words, they are polar semiconductor materials. Polar semiconductors have many unique properties. Particularly importantly, fixed polarized charges are present at a surface of the polar semiconductor or at an interface of two different polar semiconductors. These fixed polarized charges may attract movable electrons or hole carriers, thus forming a two-dimensional electron gas 2DEG or a two-dimensional hole gas 2DHG. The generation of the two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG does not require an additional electric field, nor does it depend on a doping effect in the semiconductor. They are spontaneously generated. The two-dimensional electron gas or two-dimensional hole gas at the interface of the polar semiconductors may have a high surface charge density. Meanwhile, since doping is not required, ion scattering and other effects that the two-dimensional electron gas or the two-dimensional hole gas is subjected to are greatly reduced, and thus the mobility is high. The higher surface charge density and mobility enable the two-dimensional electron gas or hole gas spontaneously generated at such interface to have good conductivity and very high response speed.

In combination with advantages such as high breakdown electric field inherent to the nitride semiconductor itself, such two-dimensional electron gas or two-dimensional hole gas may be used to fabricate a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT), the performances of which in high energy, high voltage or high frequency applications are significantly better than those made of traditional Si or GaAs devices. However, existing structures have many defects, which seriously restrict application ranges thereof. <CIT> discloses a three dimensional vertically structured electronic device, such as a vertical FET comprising a vertical 2DHG formed at a vertical AlGaN/GaN interface. A nonplanar transistor is also disclosed in <CIT>.

Subject-matter falling outside the scope of the claims may be disclosed but is not according to the invention.

In view of the problems in the related art, the present disclosure provides a high hole mobility transistor (HHMT), comprising: a substrate having a higher surface and a lower surface, the higher and lower surfaces forming a step-shape structure; a vertical interface located between the higher and lower surfaces; a channel layer disposed outside of the vertical interface; a channel supply layer at least partially covering a first side of the channel layer, wherein in the channel layer a vertical two-dimensional hole gas (2DHG) is formed adjacent to an interface between the channel layer and the channel supply layer; a first electrode configured to be electronically connected to the vertical two-dimensional hole gas; a second electrode configured to be electronically connected to the vertical two-dimensional hole gas; and a gate electrode disposed outside of the channel supply layer; wherein the first side is a (<NUM>-<NUM>) plane of Group III nitride semiconductor; the vertical interface is formed between the substrate and the channel layer, or between the substrate and a nucleation layer if the nucleation layer is present; the first electrode, the second electrode, and the gate electrode are positioned on only one side of the vertical two-dimensional hole gas.

In the high hole mobility transistor as described in the above, the Group III nitride semiconductor is GaN.

In the high hole mobility transistor as described in the above, the vertical interface is a (<NUM>) plane of the substrate being a Si substrate, a Al2O3 (<NUM>) plane of the substrate being a sapphire Al<NUM>O<NUM> substrate, a (<NUM>) plane or a (<NUM>-<NUM>) of the substrate being a SiC substrate, or (<NUM>) plane of the substrate being a GaN intrinsic substrate.

In the high hole mobility transistor as described in the above, the first electrode or the second electrode form an ohmic contact with the channel supply layer.

In the high hole mobility transistor as described in the above, the first electrode, the second electrode, and the gate electrode have the same horizontal height.

In the high hole mobility transistor as described in the above, the first electrode is a drain.

In the high hole mobility transistor as described in the above, the second electrode is a source.

In the high hole mobility transistor as described in the above, it further comprises a nucleation layer on the vertical interface of the substrate.

In the high hole mobility transistor as described in the above, it further comprises a buffer layer positioned between the nucleation layer and the channel layer.

In the high hole mobility transistor as described in the above, it further comprises a screening layer formed on the side of the channel layer away from the two-dimensional hole gas 2DHG.

In the high hole mobility transistor as described in the above, it further comprises an insulating layer extending under the channel layer and the channel supply layer.

In the high hole mobility transistor as described in the above, it further comprises a gate insulating layer between the channel supply layer and the gate electrode.

In another aspect of the present disclosure, it provides a method of manufacturing a high hole mobility transistor, comprising: forming a vertical interface on a substrate, the substrate having a higher surface and a lower surface, the higher and lower surfaces forming a step-shape structure, the vertical interface being formed between the higher and lower surfaces; forming a channel layer outside of the vertical interface; and forming a channel supply layer at least partially covering a first side of the channel layer, wherein the first side is a (<NUM>-<NUM>) plane of Group III nitride semiconductor, a vertical two-dimensional hole gas is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer; and forming a first electrode and a second electrode being electrically connected with the two-dimensional hole gas and a gate electrode outside of the channel supply layer; wherein the vertical interface is formed between the substrate and the channel layer, or between the substrate and a nucleation layer if the nucleation layer is present; the first electrode, the second electrode, and the gate electrode are formed on only one side of the vertical two-dimensional hole gas.

In the method as described in the above, the Group III nitride semiconductor is GaN.

In the method as described in the above, the vertical interface is formed on a substrate.

In the method as described in the above, a gate insulating layer is included between the channel supply layer and the gate electrode.

In the method as described in the above, it further comprises transversely etching the channel supply layer or the channel supply layer and a part of the channel layer before forming a first electrode and a second ohmic contacted electrode.

In the method as described in the above, it further comprises forming a nucleation layer on the vertical interface, wherein Chlorine gas is aerated while forming a nucleation layer.

In order that the objects, technical solutions and advantages of the embodiments of the present disclosure will become clearer, technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. All the other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts will fall within the scope of the present disclosure.

In the following detailed description, reference may be made to various drawings which constitute a part of the present application and serve to explain the present application. In the drawings, similar reference signs denote substantially similar components in different figures. The individual specific embodiments of the present application will be described in sufficient detail below to enable those of ordinary knowledge and skills in the art to carry out the technical solutions of the present application. It is understood that other embodiments may be utilized, or structural, logical or electrical changes may be made to the embodiments of the present application.

The present disclosure provides a high hole mobility transistor having vertical channel structure. <FIG> is a schematic diagram of a high hole mobility transistor according to an embodiment of the present disclosure. As shown, the semiconductor device <NUM> includes a substrate <NUM>. The substrate <NUM> includes two regions <NUM> and <NUM> having different heights, thereby forming a stepped structure. Thereby, a vertical interface <NUM> is formed between the two regions <NUM> and <NUM>.

It is advantageous to forming the vertical surface <NUM> on the substrate <NUM> for design of manufacturing processes. However, the present disclosure is not limited to this implementation. In some embodiment, the vertical surface may not be formed on the substrate. For example, it is possible to form the vertical surface by vertical crystal growth or etching of existing structure on the substrate.

The lattice of the vertical surface has hexagonal symmetry. For example, the vertical surface may be a (<NUM>) plane of Si, a (<NUM>) plane of sapphire Al<NUM>O<NUM>, a (<NUM>-<NUM>), or (<NUM>) plane of SiC, or a (<NUM>) plane of intrinsic GaN. Further, when the vertical surface is formed on a substrate, the corresponding substrate may be a Si substrate, a sapphire Al<NUM>O<NUM> substrate, a SiC substrate, or an intrinsic GaN substrate.

The HHMT <NUM> further comprises a channel layer <NUM> and a channel supply layer <NUM> outside of the vertical surface <NUM>. The channel layer <NUM> is closer to the vertical surface <NUM>. In some embodiment, the channel layer <NUM> may be higher than the vertical surface <NUM>. The channel supply layer <NUM> is grown outside of the channel layer <NUM>. The two-dimensional electron gas 2DHG <NUM> is formed on the interface in the channel layer <NUM> adjacent to the channel supply layer <NUM>. In some embodiments, the channel supply layer <NUM> is formed on a specific first side of the channel layer <NUM> to obtain 2DHG <NUM>.

As described without limitation, the channel layer <NUM> and the channel supply layer <NUM> are crystal having polarity. A heterojunction is formed on the interface therebetween: a sudden change on lattice makes accumulation of polarized charges. If the polarized charges are positive, free electrons likely compensate those polarized charge. In case the interface is well, two-dimensional electron gas 2DEG is formed at the place adjacent to the interface. As the same, If the polarized charges are negative, two-dimensional hole gas 2DHG is formed at the place adjacent to the interface. As described without limitation, the polarized charges on the complementary heterogeneous surfaces of the heterojunction are in opposite polarities. Taking GaN as an example, 2DEG is formed on the heterojunction interface of the (<NUM>) plane of GaN and AlGaN; and 2DHG formed on the heterojunction interface of the (<NUM>-<NUM>) plane of GaN and AlGaN.

The first side is a (<NUM>-<NUM>) plane of Group III nitride semiconductor. In some embodiments, the first side is (<NUM>-<NUM>) plane of the GaN. Of course, other crystals other than GaN which can produce heterojunction can also be applied in the present disclosure.

In some embodiment, the HHMT <NUM> further includes a nucleation layer <NUM>. The nucleation layer <NUM> is grown on the vertical interface <NUM>. For example, the nucleation layer <NUM> may be AlN. In some embodiment, the HHMT <NUM> further includes a buffer layer <NUM> which is grown on the nucleation layer <NUM>. For example, the buffer layer <NUM> may be in structure of one layer or multiple layers, including one or more of AlN, GaN, AlGaN, InGaN, AlInGaN. The channel layer <NUM> is grown on the nucleation layer <NUM> or the buffer layer <NUM>.

The HHMT <NUM> comprises a first electrode <NUM>, a second electrode <NUM> and a third electrode <NUM>. The first electrode <NUM> and the second electrode <NUM> have ohmic contract with the channel layer <NUM> or channel supply layer <NUM>, and thereby is electronically connected with the 2DHG <NUM>.

In some embodiment, the first electrode <NUM>, as a drain, is provided on one side of the channel layer <NUM> or channel supply layer <NUM> adjacent to the substrate <NUM>. The second electrode <NUM>, as a source, is provided on one side of the channel layer <NUM> or channel supply layer <NUM> away from the substrate <NUM>. In general, the first electrode, as the drain, is connected with high voltage; and the second electrode, as the source, is away from the first electrode, which is advantageous for increase of withstanding voltage and reduction of loss.

The third electrode <NUM>, as a gate, is provided outside of the channel supply layer <NUM>. The third electrode <NUM>, also called the gate electrode, controls current intensity in the channel area between the first electrode <NUM> and the second electrode <NUM>. In some embodiment, the third electrode <NUM> forms a Schottky contact with the channel supply layer <NUM>. In some embodiments, the third electrode <NUM> also include other layers, for example a cap layer, a gate insulating layer, etc. The third electrode is contacted with the cap layer or the gate insulating layer, but is not directly contacted with the channel supply layer <NUM>. The voltage of third electrode <NUM> may control the depth of heterojunction potential well formed by the channel layer-channel supply layer and the surface charge density of 2DHG in the potential well, and thereby control working current between the first electrode <NUM> and the second electrode <NUM> in the HHMT <NUM>.

Preferably, the third electrode <NUM> is between the first electrode <NUM> and the second electrode <NUM>, more adjacent to the second electrode <NUM>. In the condition that the first electrode <NUM>, as the drain, is connected with high voltage, such arrangement increases the distance between the drain and the gate, which can effectively increase the withstanding voltage of the high hole mobility transistor.

<FIG> shows an arrangement of the three electrodes of the HHMT <NUM>. The first electrode <NUM> is positioned below, the third electrode <NUM> is positioned above the first electrode <NUM>, and the second electrode <NUM> is positioned above the second electrode <NUM>. That is, they have the same upright position. Only the second electrode <NUM> can be observed when viewed from the top of the substrate. This arrangement can maximumly reduce chip area and increase integrity. In some embodiment, the first electrode <NUM>, and the second electrode <NUM>, and the third electrode <NUM> are arranged horizontally and having the same level height. This arrangement may facilitate the lead connection. Either the first electrode <NUM> or the second electrode <NUM> may be the drain or source.

As shown in <FIG>, the first electrode <NUM> and the second electrode <NUM> are positioned outside of the channel layer <NUM>.

In some embodiments, a first spacing layer <NUM> is included between the substrate <NUM> and the channel layer <NUM> and channel supply layer <NUM>. The spacing layer <NUM> extend horizontally and its material may be insulating material such as SiO<NUM> and so on. The spacing layer <NUM> has the HHMT <NUM> spaced from the substate <NUM>, which can avoid influence on the device from the substate <NUM> and make the capability of increasing withstanding voltage and reducing dark current of the device obviously improved.

In some embodiments, a second spacing layer <NUM> is included between the substrate <NUM> and the other structure other than the substrate <NUM>. The second spacing layer <NUM> extend horizontally and its material may be insulating material such as SiO<NUM> and so on. The second spacing layer <NUM> has the HHMT <NUM> spaced from the substate <NUM>, which can avoid influence on the device from the substate <NUM> and make the capability of increasing withstanding voltage and reducing dark current of the device obviously improved.

In some embodiments, a screening layer <NUM> is included on the second side of the channel layer <NUM> away from the 2DHG <NUM>. The first and second sides of the channel layer <NUM> are opposite and the first side is adjacent to the 2DHG <NUM>. The existence of the screening layer <NUM> makes no two-dimensional electron gas 2DEG on this side of the channel layer <NUM>. In some embodiments, the screening layer <NUM> occupied most or all of the area on the side of the channel layer <NUM> away from the 2DHG <NUM> between the first electrode <NUM> and the second electrode <NUM> and thereby has the channel layer <NUM> spaced from the substrate <NUM> on the horizontal direction. This may further avoid the influence on the device performance by the substate <NUM>.

In some embodiments, the screening layer <NUM> may envelop or partially envelop the channel layer <NUM> and channel supply layer <NUM>. For example, the screening layer <NUM> may extend on the top of the channel layer <NUM> and channel supply layer <NUM>. Or, the screening layer <NUM> may further cover the channel layer <NUM> and channel supply layer <NUM>. This will further have the HHMT <NUM> spaced and reduce the influence of other environment materials. In some embodiments, the screening layer <NUM> may be insulating material such as SiO<NUM> and so on. It is of obvious helpful to have the HHMT <NUM> spaced by the screening layer <NUM> on capability of increasing withstanding voltage and reducing dark current.

In some embodiments, a gate insulating layer <NUM> is included between the channel supply layer <NUM> and the third electrode <NUM>. The gate insulating layer <NUM> has the third electrode <NUM> spaced from the channel supply layer <NUM>, which may reduce leak current between the third electrode <NUM> and the first electrode <NUM>. Meanwhile, the gate insulating layer <NUM> may passivate the surface of the channel supply layer <NUM> and make the high hole mobility transistor working more steadily.

In some embodiments, a cap layer (for example AlN or GaN) is included between the channel supply layer <NUM> and the third electrode <NUM>. In some embodiments, a passivation layer <NUM> may be included on the channel supply layer <NUM>. For example, the passivation layer <NUM> may occupy a portion covering the channel supply layer <NUM> between the first electrode <NUM> and the second electrode <NUM> and a portion covering the third electrode <NUM> and thereby provide protection to the internal channel layer <NUM> and channel supply layer <NUM>. In some embodiments, the outer insulating layer <NUM> may be insulating material such as SiN, SiO<NUM> and so on. The cap layer and the passivation layer are helpful to reduce drain current collapse and maintain 2DHG produced by polarity. Meanwhile, they can also reduce a leak current of the gate, avoid cracking during the temperature decrease after growth of the channel supply layer <NUM> and increase ohmic contacts of the source and drain and breakdown voltage.

According to an embodiment of the present disclosure, the substrate <NUM> material may be Si, SiC, intrinsic GaN or sapphire Al<NUM>O<NUM>. In some embodiments, the Si substrate is selected with a more mature process and lower cost than other materials. Si in the substrate will have a melt-back effect with GaN in channel layer <NUM>, which will affect the growth of channel layer <NUM>. Therefore, the nucleation layer <NUM>, whose material can be AlN, is introduced to cover the vertical interface <NUM> of the Si substrate <NUM>, so as to avoid the direct contact between Si in the Si substrate <NUM> and GaN in channel layer <NUM>. The nucleation layer <NUM> may also exist but is not required when the substrate is a non-Si material.

In some embodiments, when the substrate <NUM> is a non-intrinsic GaN substrate, a buffer layer <NUM> is preferably introduced to reduce the impact of lattice differences. Buffer layer <NUM> can be one or more of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN, which can reduce the impacts of lattice constant and thermal expansion coefficient between the substrate <NUM> and channel layer <NUM>, and effectively avoid nitride epitaxial layer cracking and other conditions. The buffer layer <NUM> is also an optional structure for the HHMT <NUM>.

According to an embodiment of the present disclosure, the material of channel layer <NUM> may be GaN. According to an embodiment of the present disclosure, the material of the channel supply layer <NUM> may be AlGaN. The channel layer <NUM> and channel supply layer <NUM> may also be other materials as understood by persons skilled in the art as mentioned in the background, which is not repeated here.

Due to spontaneous polarization and piezoelectric polarization effects, there are strong polarization charges at the interface between channel layer <NUM> and channel supply layer <NUM>. Those polarized charges attract and cause generation of 2DHG at the interface. In some embodiments, the vertical interface <NUM> is the (<NUM>) plane of Si substrate, and the (<NUM>) plane of GaN, etc. The channel layer is GaN and the channel supply layer <NUM> is only formed on the left of the channel layer <NUM>, i.e. the (<NUM>-<NUM>) plane of the GaN. This will form the HHMT <NUM> only having 2DHG <NUM>. For example, the vertical surface <NUM> is the (<NUM>) plane of Si, the (<NUM>) plane of GaN, etc. The channel supply layer <NUM> is formed on both left and right sides of the channel layer <NUM>. The high hole mobility transistor having 2DHG and other structures is formed on the left and the high electron mobility transistor having 2DEG and other structures is formed on the right. As understood by persons skilled in the art, these changes are all within scope of the.

In some embodiments, it is more advantageous to implement a HHMT that includes only 2DHG. For example, in the structure shown in <FIG>, removal of 2DEG will prevent 2DEG from responding to potential changes at respective electrodes, makes no increase in parasitic capacitance and leakage channels, and reduces leakage current of the HHMT. Therefore, the HHMT <NUM> with the structure described in <FIG> has better working stability. In some embodiments, in order to manufacture this structure, the stepped structure formed by substrate <NUM> and shield <NUM> can be made high enough to manufacture the nucleation layer <NUM>, buffer layer <NUM>, channel layer <NUM>, channel supply layer <NUM> and so on.

In some embodiments, the material of the spacing layer <NUM>, the second spacing layer <NUM>, the gate insulation layer <NUM> and outer insulating layer <NUM> may be formed from at least one kind of insulating material such as silicon oxide, silicon nitride oxide or silicon nitride and may also have a single-layer or multi-layer structure.

As shown in some embodiments of the present disclosure, a HHMT comprising a 2DHG formed in the vertical direction has a number of excellent properties. First of all, the voltage withstanding capacity of HHMT is greatly improved. Even using a Si substrate with lower cost and more mature technology, the voltage withstanding capacity of HHMTs is close to that of HHMTs on the intrinsic GaN substrate. Secondly, the contact area between the vertical channel device of the present disclosure and the substrate is comparably small, which may keep the influence of the substrate small and make it easy to overcome the problems such as the epitaxial layer cracking of the traditional planar device. Furthermore, by increasing arrangement density of the vertical channels, the conductive area of the device can be increased, and the substrate area can be used more adequately.

To the knowledge of persons skilled in the art, the above description is only an illustrative embodiment of the structure of the HHMT. The HHMT also have a variety of other structures or modifications, changes, or variants on these structures to provide different properties or functions. These structures and their improvement, alteration or variation may also be applied to the scheme of the disclosure under the technical conception of the disclosure.

The disclosure also provides a manufacturing method for a HHMT. <FIG> are flow charts of a method of manufacturing a HHMT according to an embodiment of the present disclosure. In this embodiment, the device manufactured on an Si substrate is taken as an example. Similar structures can be achieved with other substrates such as intrinsic GaN, Al<NUM>O<NUM> (sapphire), SiC, etc., as understood by persons skilled in the art.

As shown in the figures, HHMT manufacturing method <NUM> comprises the following steps: in step <NUM>, forming a vertical interface <NUM> on the substrate <NUM> as shown in <FIG>. Accordingly, a first area <NUM> and a second area <NUM> of different height are formed on the substrate <NUM>. The vertical interface <NUM> is between the first area <NUM> and the second area <NUM>.

In step <NUM>, a protective layer is grown on the substrate to cover the vertical surface <NUM>, as shown in <FIG>. In some embodiments, SiN is grown on substrate <NUM> using techniques such as LPCVD to cover substrate <NUM>. Then, through vertically oriented etching technique, only SiN at the vertical interface 221is retained, forming the protective layer <NUM>. The protective layer <NUM> covers the vertical interface of the substrate.

In step <NUM>, a second spacing layer <NUM> and a spacing layer <NUM> are formed above the substrate <NUM>, as shown in <FIG>. The substrate is covered with the second spacing layer <NUM> and the spacing layer <NUM>. In some embodiments, SiO<NUM> can be grown by oxidation techniques to form an insulating layer over the substrate <NUM>. Since the vertical interface <NUM> of substrate <NUM> is covered with a protective layer <NUM>, the vertical interface <NUM> of substrate <NUM> has virtually no isolation layer <NUM> and shielding layer <NUM> growing on it. The insulation layer above the first area <NUM> is then covered with a mask, and the insulation layer on the second area <NUM> is partially etched by photolithography to reduce the height of the insulation layer on the second area <NUM>, while ensuring that the insulation layer is still covered on the second area <NUM>. This results in a higher isolation layer <NUM> and a lower shielding layer <NUM> on the substrate <NUM>. Persons skilled in the art should understand that other methods of forming the second spacing layer and the spacing layer can also be applied here.

In Step <NUM>, the protective layer is removed as shown in <FIG>. In some embodiments, SiN on the vertical interface <NUM> was removed by selective etching Therefore the vertical interface <NUM> on substrate <NUM> is exposed and the second spacing layer <NUM> and the spacing layer <NUM> are retained on substrate <NUM>.

Persons skilled in the art should understand that there are other techniques to form isolation and shielding layers on the substrate and expose the vertical interface of the substrate. For example, an insulating layer can be grown on horizontal substrates. Then, a portion of the insulating layer is covered with a mask, and the insulating layer and substrate are etched by photolithography so that the first area <NUM> and the second area <NUM> of the substrate is formed, wherein area <NUM> is covered by the insulating layer and the second area <NUM> and the vertical interface <NUM> are exposed. A protective layer is then formed over all exposed surfaces. The protective layer on the second area <NUM> is then etched in an anisotropic etching manner and the protective layer on the vertical interface <NUM> is retained. Another insulating layer is then formed on the surface of the second area <NUM>, and then selectively etched the protective layer. This will expose the vertical interface <NUM> with the first area <NUM> and the second area <NUM> covered by the insulating layer respectively.

In Step <NUM>, a nucleation layer <NUM> is formed on the exposed vertical surface <NUM> of the substrate <NUM>, as shown in <FIG>. For the Si substrate, AlN is used in the nucleation layer <NUM> due to the melt-back effect of Ga atoms. As is known to persons skilled in the art, GaN can be directly nucleated at Al<NUM>O<NUM> (sapphire), SiC or intrinsic GaN, but crystal quality control is difficult. Therefore, the nucleation layer <NUM> in general is introduced processes. In some cases, the nucleation layer <NUM> such as low temperature GaN or AlN in step <NUM> may not be necessary to introduce.

The capacity of regional selective growth of AlN is weak. As a result, there may be some growth in the second spacing layer <NUM> and the spacing layer <NUM>, which will have an adverse effect on the semiconductor devices. In some embodiments, the wafer can be taken out after AlN is grown. The AlN nucleation layer on the vertical surface can be retained by etching with anisotropy, while the AlN in other places can be removed, for example, by dry etching using vertical downward ion bombardment. Since the AlN on the vertical surface is less bombarded by ions and the AlN on other surfaces is more bombarded, only AlN on the vertical surface preserved can be achieved.

In some embodiments, the desire to remove AlN from the second spacing layer <NUM> and the spacing layer <NUM> may also lead to aeration of corrosive gases, such as chlorine or chlorinated gas, during the formation of the nucleation layer. Due to the amorphous or polycrystalline structure of the second spacing layer <NUM> and the spacing layer <NUM>, AlN is more difficult to nucleate at the second spacing layer <NUM> and the spacing layer <NUM> in a chlorine atmosphere. In addition, even if AlN attachment appears in the second spacing layer <NUM> and the spacing layer <NUM>, the AlN attached to the second spacing layer <NUM> and the spacing layer 203are also amorphous or polycrystalline. The chlorine gas has a strong corrosive effect on them and the AlN attached will be etched away by chlorine gas. The AlN of the nucleation layer is a single crystal structure, which is weakly corroded by chlorine. The AlN of the nucleation layer can grow well under the chlorine atmosphere. Therefore, this method can also realize the selective growth of the nucleated layer.

In Step <NUM>, a buffer layer is formed on the nucleation layer, as shown in <FIG>. The buffer layer <NUM> is formed by epitaxial growth on nucleation layer <NUM>. As mentioned in the above, the buffer layer is not necessary in the structure of some semiconductor devices of the present disclosure. In essence, the buffer layer and the channel layer are very similar in nature and can even be the same material. In other words, the basic structure is the channel layer/channel supply layer, and there can be a buffer layer between the channel layer and the nucleation layer.

In Step <NUM>, a screening layer is formed on the substrate, as shown in <FIG>. An insulating layer is entirely covered the formed structure by growth of SiO<NUM> with film deposition technology. Then, a part of the insulating layer is removed by selective etching and only the part on the right of the vertical surface is retained, which forming the screening layer <NUM>. In some embodiments, the retained screening layer <NUM> is higher than the buffer layer <NUM>.

Because of hexagonal symmetry of the vertical surface, directly growth of the channel layer and the channel supply layer will make the device including both 2DEG and 2DHG inside. Forming the screening layer on one side above the substrate may avoid undesired 2DEG or 2DHG formed inside. In some embodiments, there are other ways to forming the screening layer. For example, a screening layer is formed at first on one side of the vertical surface before removal of the protective layer, the protective layer is then removed to expose the vertical surface of the substrate, and the nucleation layer and the buffer layer are formed.

In Step <NUM>, a channel layer is formed on the buffer layer, as shown in <FIG>. In some embodiments, the channel layer <NUM> is lower than the screening layer <NUM>. For example, the channel layer <NUM> is formed by epitaxial growth on buffer layer <NUM>. Because the right side of the channel layer is blocked by the screening layer <NUM>, only the vertical surface on the left is exposed. In some embodiments, the exposed vertical surface is the (<NUM>-<NUM>) plane of the GaN.

In Step <NUM>, a channel supply layer is formed on the channel layer, as shown in <FIG>. For example, the channel supply layer <NUM> is formed by epitaxial growth on the channel layer <NUM>. The channel supply layer <NUM> covers the top surface of the channel layer 206and the left exposed vertical surface of the channel layer <NUM>. On the right, there is no channel supply layer grown because of blocking by the screening layer <NUM>.

Basically, the most critical thing is the formation of channels. Channels are generated at the interface of nitride semiconductor with narrow/wide band gap width. They are located in the channel layer with low band gap width and near the interface of channel layer/channel supply layer. The most common example is the GaN/AlGaN interface. That is, the channel layer <NUM> is GaN and the channel supply layer <NUM> is AlGaN. Because the left of the channel layer is the GaN (<NUM>-<NUM>) plane, the carriers formed in the channel are holes. The holes flow mainly in the channel and have high mobility and charge density, which forms two-dimensional hole gas 2DHG.

In step <NUM>, the first electrode <NUM> is formed on the insulating layer <NUM>, as shown in <FIG>. In some embodiments, the channel supply layer <NUM> and part of the channel layer <NUM> which is defined as drain area may be etched and the first electrode <NUM> may then be formed in the exposed area. Electrode deposition methods may be used, such as electron beam evaporation physical deposition or electrochemical deposition methods. The first electrode <NUM> is in ohmic contact with channel layer <NUM> and can be electrically connected with 2DHG. In some embodiments, partial etching may not be required. The first electrode <NUM> is formed on the part of the channel supply layer <NUM> that defines the drain area. The first electrode <NUM> is in ohmic contact with the channel supply layer <NUM> and can also be electrically connected with 2DHG.

Usually, the material of the first electrode is metal. In some embodiments, in addition to the deposition at the bottom, a small amount of deposition on the side may occur during the deposition of the first electrode. The undesired deposition of the metal layer on the side wall may be removed by isotropic etching.

In step <NUM>, a passivation layer <NUM> is formed, covering the channel supply layer <NUM> and first electrode <NUM>, as shown in <FIG>. Besides the channel supply layer <NUM>, an insulating layer <NUM> can be formed on the channel supply layer <NUM> by means of material deposition, for example the SiO<NUM> growing by CVD technology.

In Step <NUM>, the passivation layer <NUM> above the gate electrode area is removed as shown in <FIG>. In some embodiments, the passivation layer above the gate electrode area can be completely removed, exposing the channel supply layer <NUM> above the gate electrode area. In other embodiments, a part of the passivation layer may be retained without exposing the channel supply layer <NUM>. After the formation of the gate electrode, the passivated layer between the channel supply layer <NUM> and the gate electrode becomes a gate insulation layer.

In Step <NUM>, a third electrode <NUM> is formed on the passivation layer <NUM>, as shown in <FIG>. The third electrode <NUM> is provided as a gate outside of the channel supply layer <NUM>. The Schottky contact is formed between the third electrode <NUM> and the gate insulating layer or channel supply layer <NUM>. A third electrode may be formed by, such as, the electron beam evaporation physical deposition or by electrochemical method.

The material of the third electrode is usually metal. In some embodiments, in addition to the deposition at the bottom, there may be a small amount of deposition on the side during the deposition of the third electrode. The undesired metal layer deposition on the side wall may be removed by the isotropic corrosion.

In Step <NUM>, a passivated layer <NUM> is formed, covering the third electrode, as shown in <FIG>. In some embodiments, the passivated layer <NUM> can be formed by CVD deposition, such as SiO<NUM> growing by CVD deposition, covering the third electrode.

In Step <NUM>, the passivation layer <NUM> above the location of the first electrode area is removed, as shown in <FIG>. Similar to Step <NUM>, the selective etching is used to exposes the passivation layer above the location of the first electrode area, while retaining a part of the insulation layer outside of the channel supply layer.

In Step <NUM>, a second electrode <NUM> is formed on the passivation layer <NUM>, as shown in <FIG>. Similar to Step <NUM>, the passivation layer <NUM> and the channel supply layer <NUM> or a part of the channel layer <NUM> at the position corresponding to the source electrode are etched, and the second electrode <NUM> can be formed outside of the exposed channel layer <NUM>. Electrode formation methods, such as electron beam evaporation physical deposition or electrochemical methods, may be used. The second electrode <NUM> has ohmic contact with channel <NUM> and can be electrically connected with 2DHG.

The second electrode material is usually metal. In some embodiments, in addition to the deposition at the bottom, there may be a small amount of deposition on the side during the deposition of the second electrode. The undesired deposition on the side wall may be removed by the isotropic corrosion.

In step <NUM>, a passivation layer <NUM> is formed and the second electrode <NUM> is coated, as shown in <FIG>. In some embodiments, the passivated layer <NUM> may be formed by CVD deposition, such as, SiO<NUM> growing by CVD deposition.

In some embodiments, when an insulating layer is formed over a channel supply layer, it may be formed in-situ in the same growth device after the epitaxial growth of a nitride semiconductor, such as, the SiN insulating layer may be grown in situ. Alternatively, the growing may be done after the wafer is taken out.

<FIG> is a schematic diagram of a HHMT according to an embodiment of the present disclosure. In the embodiment in <FIG>, The 2DEG is also formed on the other side of the channel layer. As shown, the HHMT <NUM> includes a substrate <NUM>, a nucleation layer <NUM>, a buffer layer <NUM>, a channel layer <NUM>, a channel supply layer <NUM>, an second spacing layer <NUM>, and a spacing layer <NUM>, etc. The first electrode <NUM> and the second electrode <NUM> in ohmic contact with 2DHG <NUM> and the third electrode <NUM> in Schottky contact with channel supply layer <NUM> are formed on one side of the channel supply layer <NUM>. The structures similar to the HHMT shown in <FIG> will not be repeated here. In the embodiment shown in <FIG>, the HHMT is formed on the left of channel layer <NUM>. However, compared with the structure in <FIG>, the preparation process of the structure shown in <FIG> may be simpler.

<FIG> is a schematic diagram of a HHMT according to an embodiment of the present disclosure. In the embodiment shown in <FIG>, the substrate may be GaN intrinsic substrate. The structure and manufacturing process are relatively simple.

As shown in the figure, the HHMT <NUM> includes a substrate <NUM> and a vertical interface formed on the substrate <NUM>, resulting in a step-shape substrate structure. The HHMT <NUM> comprises a channel layer <NUM> and a channel supply layer <NUM>. The channel layer <NUM> is outside of the vertical interface of substrate <NUM>. The channel supply layer <NUM> is formed outside of the channel layer <NUM> and covers the channel layer <NUM>. Within the channel layer <NUM>, 2DHG <NUM> and 2DEG <NUM> are formed near the interface of the channel supply layer <NUM>. The first electrode <NUM> and the second electrode <NUM> in ohmic contact with the 2DHG are formed on the channel supply layer <NUM>, and the third electrode <NUM> is formed on the channel supply layer <NUM> and is in Schottky contact with the channel supply layer <NUM>. In some other embodiments, the substrate material may also be SiC or sapphire Al<NUM>O<NUM>.

The different arrangements of the three HHMT electrodes are shown in embodiments of <FIG> and <FIG>. <FIG> is a top view of a vertical configuration of the electrodes of a HHMT according to an embodiment of the present disclosure; <FIG> is a solid view of a vertical configuration of the electrodes of a HHMT according to an embodiment of the present disclosure. As shown in the figures, HHMT <NUM> includes: a channel layer <NUM>, a channel supply layer <NUM>, a 2DEG <NUM>, a 2DHG <NUM>, a first electrode <NUM>, a second electrode <NUM> and a third electrode <NUM>. As shown in <FIG>, the first electrode <NUM>, the second electrode <NUM> and the third electrode <NUM> are arranged vertically, while only the second electrode <NUM> can be seen in <FIG>. This arrangement is advantageous to reduce the wafer area occupied.

<FIG> is a top view of a HHMT and <FIG> is a solid view of the HHMT according to an embodiment of the present disclosure.

As shown in the figures, the HHMT <NUM> includes a channel layer <NUM>, a channel supply layer <NUM>, a 2DEG <NUM>, a 2DHG <NUM>, a first electrode <NUM>, a second electrode <NUM>, and a third electrode <NUM>. In combination with the structure shown in <FIG>, the embodiments in <FIG> show that the first electrode <NUM>, the second electrode <NUM> and the third electrode <NUM> are arranged laterally and have the same horizontal height.

To the knowledge of persons skilled in the art, the above description is only an illustrative embodiment of the structure of HHMT. The HHMT also have a variety of other structures or modifications, changes, or variants on these structures to provide different properties or functions. These structures and their improvement, alteration or variation may also be applied to the scheme of the disclosure under the technical conception of the disclosure.

<FIG> shows other structures of the one-side HHMT. <FIG> is a schematic diagram of a one-side HHMT according to an embodiment of the present disclosure. Like the structure of the <FIG> embodiment, the HHMT <NUM> comprises a substrate <NUM>, a channel layer <NUM>, and a channel supply layer <NUM>. As shown, after the growth of channel supply layer <NUM> outside of the channel layer <NUM>, the channel supply layer <NUM> in the left part is removed. Thus, only 2DHG <NUM> exists on the left side, resulting in a HHMT having 2DHG on one side. In some embodiments, the top surface of the channel layer <NUM> may retain a part of the channel supply layer. In some embodiments an insulating layer <NUM> may be introduced to cover the channel layer <NUM>.

<FIG> is a schematic diagram of a one-side HHMT according to an embodiment of the present disclosure. Like the structure of the <FIG> embodiment, the HHMT <NUM> comprises a substrate <NUM>, a channel layer <NUM>, and a channel supply layer <NUM>. As shown, after the channel layer <NUM> is grown, the insulating layer <NUM> is grown, and then the insulating layer <NUM> on the right side of channel layer <NUM> is etched, and the channel supply layer <NUM> is then grown. That is, after the channel layer is generated, an insulating layer is used to protect the channel layer, and then the channel supply layer is grown. Thus, only 2DHG <NUM> exists on the left side, resulting in a HHMT having 2DHG on one side.

<FIG> is a schematic diagram of a HHMT according to an embodiment of the present disclosure. Like the structure of the embodiment in <FIG>, the HHMT <NUM> comprises a substrate <NUM>, a spacing layer <NUM>, a screening layer <NUM>, the nucleation layer <NUM>, a buffer layer <NUM>, a channel layer <NUM>, a channel supply layer <NUM>, a first electrode <NUM>, a second electrode <NUM>, and a third electrode <NUM>.

As shown, a right-high-left-low stepped structure is formed on the substrate before the nucleation layer <NUM> grows. Meanwhile, a recess structure is included in the high-low stepped structure. Then, an insulating layer is grown and a part of the insulating layer adjacent to the vertical interface within the recess is etched off to expose the vertical interface of the substrate. Then, the nucleation <NUM>, the buffer layer <NUM>, the channel layer <NUM> and channel supply layer <NUM> are respective grown. Thus, only 2DHG <NUM> on the left exists, resulting in a HHMT having 2DHG on one side. Similarly, if the left-high-right-low stepped structure including the recess structure therein is formed and then the channel layer <NUM> and channel supply layer <NUM> are grown, a one-side 2DEG HEMT can also obtained.

<FIG> is a schematic diagram of a HHMT according to an embodiment of the present disclosure, not forming part of the invention. Like the structure of the embodiment in <FIG>, the HHMT <NUM> comprises a substrate <NUM>, a spacing layer <NUM>, a screening layer <NUM>, a channel layer <NUM>, a channel supply layer <NUM>, a first electrode <NUM>, a second electrode <NUM>, and a third electrode <NUM>.

As shown, after the channel layer <NUM> grown reaches a certain height, a third electrode <NUM> is formed above the channel layer, but part of the channel layer <NUM> is still exposed. Then, the channel layer <NUM> continues to grow on exposed channel layer <NUM>, covering part of the third electrode <NUM>. The channel supply layer <NUM> is grown, but only the left channel was reserved to obtain one-side 2DHG <NUM>. The screening layer <NUM> is formed on the right side of channel layer <NUM> and channel supply layer <NUM>, resulting in a HHMT with a third electrode <NUM> on the right and a first electrode and a third electrode on the left.

<FIG> is a schematic diagram of an embodiment of the present disclosure, HHMT, not forming part of the invention. As shown in the Fig, HHMT <NUM> includes: a channel layer <NUM>, a channel supply layer <NUM>, a 2DHG <NUM>, a screening layer <NUM>, a first electrode <NUM>, a second electrode <NUM> and a third electrode <NUM>. Unlike the structure of other embodiments, the first electrode <NUM> extends under the channel layer <NUM> and the channel supply layer <NUM>. In some embodiments, the first electrode <NUM> is disposed on a substrate. After completing preparation of the structure above the first electrode <NUM>, the substrate below may still remain. In some embodiments, the substrate under the first electrode <NUM> may be partially or completely removed. In this way, the first electrode <NUM> can be lined out from the bottom to realize electrical connection. The second electrode <NUM> and the third electrode <NUM> are still lined out from the top to realize electrical connection. In comparison with the structures in which all electrodes are electrically connected from the top, the high voltage of the first electrode requires a large insulation distance, which is adverse for reducing the size of the device; while in the structure shown in <FIG>, the second electrode and the third electrode with low potential are lined out from the top of the device, and the first electrode is lined out from the bottom of the device, which can effectively save space, reduce parasitic capacitance inductance, and also facilitate subsequent device packaging. Furthermore, the structure shown in <FIG> reduces the thermal resistance of the device by removing the silicon substrate. The heat can be effectively derived from both sides, especially the first electrode which can be directly connected to the thermal conductivity device, which can greatly reduce the thermal resistance.

In preparing the HHMT shown in <FIG>, the second and third electrodes can be formed first. After removing most or all of the silicon substrate to expose 2DHG <NUM>, the first electrode <NUM> is then formed. In some embodiments, it is preferable to add a support structure to the wafer prior to the removal of the silicon substrate because the mechanical strength of the wafer is significantly reduced after substrate removal.

Claim 1:
A high hole mobility transistor (HHMT, <NUM>), comprising:
a substrate (<NUM>) having a higher surface and a lower surface, the higher and lower surfaces forming a step-shape structure;
a vertical interface (<NUM>) located between the higher and lower surfaces;
a channel layer (<NUM>) disposed outside of the vertical interface (<NUM>);
a channel supply layer (<NUM>) at least partially covering a first side of the channel layer (<NUM>), wherein in the channel layer (<NUM>) a vertical two-dimensional hole gas (2DHG, <NUM>) is formed adjacent to an interface between the channel layer (<NUM>) and the channel supply layer (<NUM>);
a first electrode (<NUM>) configured to be electronically connected to the vertical two-dimensional hole gas (<NUM>);
a second electrode (<NUM>) configured to be electronically connected to the vertical two-dimensional hole gas (<NUM>); and
a gate electrode (<NUM>) disposed outside of the channel supply layer (<NUM>);
wherein the first side is a (<NUM>-<NUM>) plane of Group III nitride semiconductor,
wherein the vertical interface (<NUM>) is formed between the substrate (<NUM>) and the channel layer (<NUM>), or between the substrate (<NUM>) and a nucleation layer (<NUM>) if the nucleation layer (<NUM>) is present;
wherein the first electrode (<NUM>), the second electrode (<NUM>), and the gate electrode (<NUM>) are positioned on only one side of the vertical two-dimensional hole gas (<NUM>).