Patent Description:
Integrated circuit devices traverse a broad range of electronic devices including memory devices, which are often referred to simply as memory. Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

NAND flash memory is a common type of flash memory, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor.

Further, current NAND memory devices provide various methods to reset the memory if it becomes unresponsive. Certain commands may be used to reset an entire memory device, for example, but such commands are often processed via memory control circuitry and/or firmware controllers that are also used in the memory operations. Other techniques are provided to reset erase or program operations, as opposed to the overall memory device, yet such techniques also typically require internal control circuitry and/or firmware. These techniques are not useful if the control circuitry and/or firmware controllers that process the reset instructions also become unresponsive, which can occur with brownout, illegal sequences, etc. As such, users may have no recourse when memory devices become unresponsive in this manner, as powering-down in not an option in actual systems and operation. Updating memory design to avoid such drawbacks is also a challenge, as the addition of another, dedicated pin to perform such reset independent of the control circuitry and firmware is also not viable, due to the cost and complexity of adding an extra pin to the package.

<CIT> discloses a flash memory device comprising a reset connection to receive an external signal for triggering an initialisation operation.

The invention is defined by appended independent device claim <NUM> and independent method claim <NUM>. Advantageous embodiments are defined in dependent claims <NUM> - <NUM> and <NUM> - <NUM>.

The disclosed embodiments provide improved technical solutions regarding the above-noted drawbacks and/or otherwise remedy or overcome the above and other deficiencies of existing semiconductor memories.

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments as illustrated in the accompanying drawings, in which reference characters refer to the same parts throughout the various views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating principles of the disclosure.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term "semiconductor" used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term "conductive" as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term "connecting" as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

Various embodiments will be discussed using the example of a NAND memory device. However, it should be understood that the concepts disclosed herein may also be applied to other forms of semiconductor memory.

As explained in more detail, below, systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are provided. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, as well as reset circuitry including a special timeout circuit. The reset circuitry may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state. The timeout circuit may be configured with a timeout delay value based on parameters and conditions of the particular memory device. Once enabled, the timeout circuit can reset an entire memory device without requiring any of the internal memory control circuitry or firmware controllers of the memory, i.e., the components that may be or could become unresponsive, to process the relevant reset instructions.

<FIG> is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device) <NUM>, in communication with a second apparatus, in the form of a processor <NUM>, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones and the like. The processor <NUM>, e.g., a controller external to the memory device <NUM>, may be a memory controller or other external host device.

Memory device <NUM> includes an array of memory cells <NUM> logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown in <FIG>) of at least a portion of array of memory cells <NUM> are capable of being programmed to one of at least two data states.

A row decode circuitry <NUM> and a column decode circuitry <NUM> are provided to decode address signals. Address signals are received and decoded to access the array of memory cells <NUM>. Memory device <NUM> also includes input/output (I/O) control circuitry <NUM> to manage input of commands, addresses and data to the memory device <NUM> as well as output of data and status information from the memory device <NUM>. An address register <NUM> is in communication with I/O control circuitry <NUM> and row decode circuitry <NUM> and column decode circuitry <NUM> to latch the address signals prior to decoding. A command register <NUM> is in communication with I/O control circuitry <NUM> and control logic <NUM> to latch incoming commands. A count register <NUM> may be in communication with the control logic <NUM> to store count data, such as data representative of respective numbers of read cycles for different portions of the array of memory cells <NUM>. Although depicted as a separate storage register, count register <NUM> may represent a portion of the array of memory cells <NUM>.

A controller (e.g., the control logic <NUM> internal to the memory device <NUM>) controls access to the array of memory cells <NUM> in response to the commands and generates status information for the external processor <NUM>, i.e., control logic <NUM> is configured to perform access operations (e.g., read operations, program operations and/or erase operations) in accordance with embodiments described herein. The control logic <NUM> is in communication with row decode circuitry <NUM> and column decode circuitry <NUM> to control the row decode circuitry <NUM> and column decode circuitry <NUM> in response to the addresses.

Control logic <NUM> is also in communication with a cache register <NUM>. Cache register <NUM> latches data, either incoming or outgoing, as directed by control logic <NUM> to temporarily store data while the array of memory cells <NUM> is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data is passed from the cache register <NUM> to data register <NUM> for transfer to the array of memory cells <NUM>; then new data is latched in the cache register <NUM> from the I/O control circuitry <NUM>. During a read operation, data is passed from the cache register <NUM> to the I/O control circuitry <NUM> for output to the external processor <NUM>; then new data is passed from the data register <NUM> to the cache register <NUM>. A status register <NUM> is in communication with <NUM>/O control circuitry <NUM> and control logic <NUM> to latch the status information for output to the processor <NUM>.

Memory device <NUM> receives control signals at control logic <NUM> from processor <NUM> over a control link <NUM>. The control signals might include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP# <NUM>. Memory device <NUM> may also generate output signals, such as ready/busy R/B# <NUM>. Control signals and output signals may be applied to or present on specified pins of the memory package, as shown further in connection with <FIG>, below. Additional or alternative control signals (not shown) may be further received over control link <NUM> depending upon the nature of the memory device <NUM>. Memory device <NUM> receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor <NUM> over a multiplexed input/output (I/O) bus <NUM> and outputs data to processor <NUM> over I/O bus <NUM>.

For example, the commands are received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and are written into command register <NUM>. The addresses are received over input/output (I/O) pins [<NUM>:<NUM>] of I/O bus <NUM> at I/O control circuitry <NUM> and are written into address register <NUM>. The data are received over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device at I/O control circuitry <NUM> and are written into cache register <NUM>. The data are subsequently written into data register <NUM> for programming the array of memory cells <NUM>. For another embodiment, cache register <NUM> may be omitted, and the data are written directly into data register <NUM>. Data are also output over input/output (I/O) pins [<NUM>:<NUM>] for an <NUM>-bit device or input/output (I/O) pins [<NUM>:<NUM>] for a <NUM>-bit device.

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device <NUM> of <FIG> has been simplified. It should be recognized that the functionality of the various block components described with reference to <FIG> may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of <FIG>. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of <FIG>.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations, numbers and/or specific ones of I/O pins may be used in the various embodiments.

<FIG> is a simplified diagram showing an exemplary memory device package and associated pin assignment, according to some embodiments of the disclosure. Referring to <FIG>, a top view of an exemplary pin assignment for a memory device package, illustrating some input and output pins of a memory device, is shown. For example, the pin assignment of <FIG> shows pins for Vcc, Vss, CLE (command latch enable), ALE (address latch enable), WE# (write enable), WP# (write protect) <NUM>, R/B# (ready/busy) <NUM>, as well as various NC (no care), DNU (do not use), and other pins. As described in more detail, below, embodiments herein may re-purpose the write protect WP# pin to provide a mechanism for the overall memory device to be reset, i.e., if the entire device becomes unresponsive. Further, some embodiments may utilize a time duration of a low signal on the ready/busy output or pin in calculating a timeout delay value that a timeout circuit uses to reset the memory device.

<FIG> is a block diagram illustrating an exemplary reset and memory control circuitry, according to some embodiments of the disclosure. The illustrative circuitry of <FIG> involved in embodiments of the disclosed technology may include a first logic circuit <NUM>, a timeout circuit <NUM>, a power-up circuit, a second logic circuit, and a controller <NUM>, which may be control circuitry, control logic <NUM>, a firmware controller, and the like. Referring to <FIG>, the signals being processed may include a write protect signal <NUM> coming from the write protect pin <NUM>, a (reset) input of the timeout circuit <NUM>, and output <NUM> of the timeout circuit <NUM>, an output <NUM> of the power-up circuit <NUM>, an output (global reset signal <NUM>), which may be low (e.g. Lowvcc) or high (e.g. Vcc), of the second logic circuit <NUM>, and an output of the controller, which may be a busy signal <NUM> such as ready/busy signal RB#, of the controller <NUM>.

Referring to the example embodiment shown in <FIG>, the busy signal <NUM> being provided as output from the controller <NUM> is fed back in a loop to be provided along with the write protect signal <NUM> as part of the control signals used to enable the timeout circuit via its reset input <NUM>. Here, the timeout circuit <NUM> may be enabled, e.g. via first logic circuit <NUM>, when the write protect is kept low and the busy signal <NUM> is also high, indicating that that the memory device is unresponsive. Such logic may be implanted using an OR gate, as shown, though various other logic may be utilized. This example implementation is further beneficial in that it allows continued use of the write protect WP# pin and functionality for its original purpose, which will not trigger the hardware reset disclosed herein. Here, for example, the normal aborting of program and erase operations will cause the busy signal <NUM> to switch back to a low state and reset the timeout circuit <NUM>. In contrast, the special hardware reset herein only occurs if the memory device is still not responsive (i.e., busy signal <NUM> is high) after the write protect <NUM> is kept low and the busy signal <NUM> is maintained high beyond the duration of the full timeout delay value or 'fixed delay' calculated for use by the timeout circuit <NUM>.

In some embodiments, the timeout delay value may be calculated based on the greater of (i) the necessary time that the write protect signal is held low to reset erase/program operations, i.e., when the memory becomes unresponsive during erase or program, (ii) the worst-case time that is desired for the busy signal to be high, i.e., the worst-case time for the memory device to be busy, indicating it is in an unresponsive state. With regard to the first time, (i), implementations herein may determine, for the memory device, this first time that a write protect signal is held low during an erase operation or a program operation to perform this reset. The time needed to perform such reset operation (often referred to as tRST) may be provided in the datasheet for a given memory device, e.g., as the tRST spec. Here, for example, if the memory device were to become unresponsive during erase or program, reset is performed by keeping the write protect signal active (e.g., low) for greater than this reset time, tRST, to see if the memory device's busy signal transitions from the busy or unresponsive state to the ready state. With regard to the second time, (ii), implementations herein may also set the timeout delay value equal to, or just above, a second time that the busy signal is held high, if such second time is greater than the first time, (i). Here, for example, this second time may be established by determining the worst-case busy high time for any memory operation of the memory device. Further, the reset circuitry may factor-in this second time with some margin added. As such, by comparing these two times and using the greater of the two, the timeout circuit is not triggered until after such worst-case time period has elapsed. Accordingly, then, if the write protect signal is held low for this entire, worst-case time delay value, the reset circuitry is configured to provide a reset signal to transition the control circuitry and/or memory device out of an unresponsive state. Operation involving such timeout delay value or fixed delay is shown and described further, below, in connection with <FIG>. Additional conditions associated with the hardware reset herein may also be added as part of triggering the timeout delay. For example, the hardware reset may be conditioned on things such as the NAND failing initialization, the NAND failing certain number of program/erase operations, and the like.

<FIG> is a is a generic wave diagram demonstrating timeout reset circuitry behavior and associated delay, according to some embodiments of the disclosure. Referring to <FIG>, example waveforms corresponding to the busy signal <NUM>, the write protect signal <NUM>, and the global reset signal <NUM> set forth above in connection with <FIG>. As shown in <FIG>, the memory may first be operating normally with the global reset signal <NUM> in a high (Vcc) state and write protect <NUM> off (high), when the busy signal <NUM> goes high upon the memory device entering an unresponsive state. Thereafter, the write protect signal <NUM> may be transitioned to active (low), which may begin a customary period of application of such low signal for a period of time, tRST, sufficient to reset unresponsive erase or program operations. However, once the write protect signal <NUM> is maintained past both this initial reset attempt period, tRST, and the full period of fixed delay <NUM> (the 'timeout delay value'), a reset consistent with the disclosed technology may then be provided, e.g., to activate the global reset signal <NUM> provided to reset the memory. This resets the memory circuitry and memory device, yield a hardware-based timeout reset, at <NUM>. Upon completion of the powering-down and associated reset of the memory circuitry, the global reset signal <NUM> to the memory circuitry is returned to high (Vcc) and the busy signal returns to the low (ready) state, at <NUM>. As such, hardware reset herein may be configured to occur only when the memory device is still not responsive after the write protect is kept low and the ready/busy signal stays low beyond a duration of the timeout delay <NUM>. Accordingly, embodiments herein may repurpose an existing circuit and pin, such as an existing write protect pin, and combine such use with the disclosed reset and timeout circuitry to provide the capability of resetting a non-responsive memory device without access or processing by circuit components that may be inactive (unresponsive) due to the non-responsive state of the memory device.

Furthermore, the subject matter disclosed above may be embodied in a variety of different forms and, therefore, covered or claimed subject matter is intended to be construed as not being limited to any example embodiments set forth herein; example embodiments are provided merely to be illustrative. Likewise, a reasonably broad scope for claimed or covered subject matter is intended. Among other things, for example, subject matter may be embodied as methods, devices, components, or systems. Accordingly, embodiments may, for example, take the form of hardware, software, firmware or any combination thereof (other than software per se). The following detailed description is, therefore, not intended to be taken in a limiting sense.

Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase "in one embodiment" as used herein does not necessarily refer to the same embodiment and the phrase "in another embodiment" as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter may include, within the scope of the appended claims, combinations of example embodiments in whole or in part.

Claim 1:
A memory device (<NUM>) comprising:
control circuitry (<NUM>) configured to control operation of the memory device (<NUM>), the control circuitry (<NUM>) comprising:
an output providing a busy signal (<NUM>) indicating that the memory device (<NUM>) is busy;
reset circuitry coupled to the control circuitry (<NUM>) and configured to reset the memory device (<NUM>), the reset circuitry comprising timeout circuitry and logic, wherein the reset circuitry is configured to generate a global reset signal (<NUM>) in response to a determination that the timeout circuitry has been activated for longer than a predetermined period;
wherein the timeout circuitry is configured to activate in response to a write protect signal (<NUM>) and in response to the busy signal (<NUM>), the write protect signal (<NUM>) configured to reset an erase or program operation of the memory device (<NUM>);
wherein the global reset signal (<NUM>) is configured to power-down and power-up the control circuitry (<NUM>) to reset the memory device (<NUM>).