Patent Description:
A storage device may include a nonvolatile memory device and a controller to control the nonvolatile memory device. The controller may communicate with an external host device based on a given communication protocol. As association technologies develop, a speed at which the controller communicates with the external host device may increase.

As the speed at which the controller communicates with the external host device increases, the amount of power consumption according to the communication of the storage device is increasing. Accordingly, the overall power consumption of the storage device is increasing. The increase of power consumption may cause the reduction of quality of the storage device.

<CIT> discloses: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

<CIT> discloses: An interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Embodiments of the present disclosure provide a system comprising a host device and a storage device reducing power consumption according to a communication while communicating with the host device at an improved communication speed.

The above and other aspects of the present disclosure will become apparent by describing in detail example embodiments thereof with reference to the accompanying drawings:.

Below, example embodiments will be described in detail and clearly to such an extent that one skilled in the art easily implements the present disclosure.

<FIG> illustrates a host device <NUM> and a storage device <NUM> according to an embodiment. Referring to <FIG>, the host device <NUM> may be implemented with one of various electronic devices such as a computer, a notebook computer, a smartphone, a smart pad, and a smart watch. The host device <NUM> includes a clock generator <NUM>, a central processing unit (CPU) <NUM>, and a random access memory <NUM>.

The clock generator <NUM> may generate a first clock signal CLK1. The first clock signal CLK1 may be supplied to the central processing unit <NUM>.

The central processing unit <NUM> includes a clock multiplier <NUM>, a core <NUM>, a memory controller <NUM>, and an interface circuit <NUM>. The clock multiplier <NUM> may receive the first clock signal CLK1. The clock multiplier <NUM> generates a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, and a reference clock signal CREF through frequency multiplication of the first clock signal CLK1.

The core <NUM> may receive the second clock signal CLK2 from the clock multiplier <NUM>. The core <NUM> may operate in response to the second clock signal CLK2. The core <NUM> may control operations of the central processing unit <NUM> and may execute an operating system and applications. The core <NUM> may include two or more cores.

The memory controller <NUM> may receive the third clock signal CLK3 from the clock multiplier <NUM>. Depending on a request of the core <NUM>, the memory controller <NUM> may access the random access memory <NUM> based on the third clock signal CLK3. For example, the memory controller <NUM> may transmit a command and address CA and the fourth clock signal CLK4 to the random access memory <NUM>. The memory controller <NUM> may exchange a data signal DQ with the random access memory <NUM>.

The interface circuit <NUM> receives the fourth clock signal CLK4 and the reference clock signal CREF from the clock multiplier <NUM>. The interface circuit <NUM> provides the reference clock signal CREF to the storage device <NUM>. The interface circuit <NUM> may establish a link LINK with the storage device <NUM>. Depending on a request of the core <NUM>, the interface circuit <NUM> may exchange a signal with the storage device <NUM> through the link LINK.

The random access memory <NUM> may be used as a working memory of the host device <NUM>. The central processing unit <NUM> may load codes for executing the operating system or the applications onto the random access memory <NUM>. The central processing unit <NUM> may store data of the random access memory <NUM> in the storage device <NUM> or may load data read from the storage device <NUM> onto the random access memory <NUM>.

The storage device <NUM> includes a nonvolatile memory device <NUM> and a controller <NUM>. The nonvolatile memory device <NUM> may be implemented with at least one of various nonvolatile memory devices such as a NAND flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device. The nonvolatile memory device <NUM> may include a first area <NUM> and a second area <NUM>.

The controller <NUM> receives the reference clock signal CREF from the external host device <NUM>. The controller <NUM> includes a clock multiplier <NUM>. The clock multiplier <NUM> generates an internal clock signal through frequency multiplication of the reference clock signal CREF. For example, a frequency of the internal clock signal may be the same as a frequency of the fourth clock signal CLK4. The controller <NUM> may establish the link LINK with the host device <NUM> by using the internal clock signal. The controller <NUM> accesses the nonvolatile memory device <NUM> depending on a request transmitted from the host device <NUM> through the link LINK or depending on an internally defined schedule.

The controller <NUM> may access the nonvolatile memory device <NUM> through a first channel CH1 and a second channel CH2. For example, the controller <NUM> may transmit a command and an address to the nonvolatile memory device <NUM> through the first channel CH1. The controller <NUM> may exchange data with the nonvolatile memory device <NUM> through the first channel CH1.

The controller <NUM> may transmit a first control signal to the nonvolatile memory device <NUM> through the second channel CH2. The controller <NUM> may receive a second control signal from the nonvolatile memory device <NUM> through the second channel CH2.

The controller <NUM> may use the first area <NUM> to perform a high-speed write operation. The controller <NUM> may use the second area <NUM> to perform a normal write operation. A write speed of the first area <NUM> may be higher than a write speed of the second area <NUM>. For example, the controller <NUM> may use memory cells of the first area <NUM> as single level cells (SLCs), and may use memory cells of the second area <NUM> as multi-level cells (MLCs), triple level cells (TLCs), quadruple level cells (QLCs), or k-th level cells (k being an integer more than <NUM>).

In an example embodiment, the controller <NUM> may open the second area <NUM> to the host device <NUM> as a storage capacity of the storage device <NUM>. The first area <NUM> may not open the first area <NUM> to the host device <NUM> as a storage capacity of the storage device <NUM>. When write data are received from the host device <NUM> together with a write request, the controller <NUM> may first write the write data into the first area <NUM>. During an idle time where a request is not received from the host device <NUM>, the controller <NUM> may allow the data written in the first area <NUM> to migrate to the second area <NUM>.

In the case where a free capacity of the first area <NUM> is filled with the write data transmitted from the host device <NUM>, the controller <NUM> may directly write the write data into the second area <NUM>. As described above, a speed at which write data are written into the second area <NUM> may be slower than a speed at which write data are written into the first area <NUM>. In the case of writing write data into the second area <NUM>, that is, in response to an operating speed (or an access speed) decrease, the controller <NUM> may make a transmission rate of the link LINK for the communication with the host device <NUM> low, and thus, power consumption of the link LINK may decrease.

In an example embodiment, the communication between the host device <NUM> and the storage device <NUM> may establish the link LINK based on one of various communication protocols such as a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-e) protocol, a nonvolatile memory-express (NVM-e) protocol, an advanced technology attachment (ATA) protocol, a serial advanced technology attachment (SATA) protocol, a serial attached SCSI (SAS), a universal flash storage (UFS) protocol, a universal serial bus (USB) protocol, an embedded multimedia card (eMMC) protocol, a small computer small interface (SCSI) protocol, a secure digital (SD) card protocol, a multi-media card (MMC) protocol, an embedded UFS (eUFS) protocol, and a compact flash card protocol.

<FIG> illustrates the controller <NUM> of the storage device <NUM> of <FIG>. Referring to <FIG> and <FIG>, the controller <NUM> receives the reference clock signal CREF and may establish the link LINK with the external host device <NUM>. The controller <NUM> receives various requests for writing data in the nonvolatile memory device <NUM> or reading data from the nonvolatile memory device <NUM>, from the external host device <NUM> through the link LINK.

The controller <NUM> may access the nonvolatile memory device <NUM> through the first channel CH1 and the second channel CH2. For example, the controller <NUM> may transmit a command and an address to the nonvolatile memory device <NUM> through the first channel CH1. The controller <NUM> may exchange data with the nonvolatile memory device <NUM> through the first channel CH1.

In an example embodiment, the controller <NUM> may be configured to control two or more nonvolatile memory devices. The controller <NUM> may provide first different channels and second different channels to two or more nonvolatile memory devices.

For another example, the controller <NUM> may provide one first channel so as to be shared by two or more nonvolatile memory devices. The controller <NUM> may provide a part of second channels so to be shared by two or more nonvolatile memory devices and may separately provide the remaining part thereof.

The controller <NUM> may include a bus <NUM>, a host interface circuit <NUM>, an internal buffer <NUM>, a processor <NUM>, a memory manager <NUM>, and an error correction code (ECC) block <NUM>.

The bus <NUM> may provide communication channels between components in the controller <NUM>. The host interface circuit <NUM> may receive various requests from the external host device <NUM> and may parse the received requests. The host interface circuit <NUM> may store the parsed requests in the internal buffer <NUM>. Also, the host interface circuit <NUM> may store data received from the external host device <NUM> in the internal buffer <NUM>. The host interface circuit <NUM> may transmit data stored in the internal buffer <NUM> to the external host device <NUM>.

The host interface circuit <NUM> may transmit various responses to the external host device <NUM>. The host interface circuit <NUM> may exchange signals with the external host device <NUM> in compliance with a given communication protocol. The host interface circuit <NUM> may include the clock multiplier <NUM>. The clock multiplier <NUM> generates an internal clock signal for establishing the link LINK and communicating with the host device <NUM>, based on the reference clock signal CREF.

The internal buffer <NUM> may include a random access memory. For example, the internal buffer <NUM> may include a static random access memory or a dynamic random access memory.

The processor <NUM> may drive an operating system or firmware for driving the controller <NUM>. The processor <NUM> may read the parsed requests stored in the internal buffer <NUM> and may generate commands and addresses for controlling the nonvolatile memory device <NUM>. The processor <NUM> may provide the generated commands and addresses to the memory manager <NUM>.

The processor <NUM> may store various metadata for managing the storage device <NUM> in the internal buffer <NUM>. The processor <NUM> may temporarily store data, which are received from the host device <NUM> and are to be written in the nonvolatile memory device <NUM>, or data, which are read from the nonvolatile memory device <NUM> and are to be transmitted to the host device <NUM>, in the internal buffer <NUM>.

The processor <NUM> may control the host interface circuit <NUM> such that the data stored in the internal buffer <NUM> are transmitted to the external host device <NUM>. The processor <NUM> may control the memory manager <NUM> such that data received from the nonvolatile memory device <NUM> are stored in the internal buffer <NUM>. The processor <NUM> may control the host interface circuit <NUM> such that data received from the external host device <NUM> are stored in the internal buffer <NUM>.

The error correction code block <NUM> may perform error correction encoding on data to be transmitted to the nonvolatile memory device <NUM> by using an error correction code ECC. The error correction code block <NUM> may perform error correction decoding on data received from the nonvolatile memory device <NUM> by using the error correction code ECC.

<FIG> illustrates a host interface circuit <NUM>. Referring to <FIG>, <FIG>, and <FIG>, the host interface circuit <NUM> may correspond to the host interface circuit <NUM> of <FIG>.

The host interface circuit <NUM> may include a locking circuit <NUM>, a receiver <NUM>, a deserializer <NUM>, a decoder <NUM>, receiver logic <NUM>, transmitter logic <NUM>, an encoder <NUM>, a serializer <NUM>, and a driver <NUM>. The host interface circuit <NUM> includes a clock multiplier <NUM>.

The locking circuit <NUM> receives the reference clock signal CREF and outputs an internal reference clock signal iCREF synchronized with the reference clock signal CREF. For example, the locking circuit <NUM> may include a delay locked loop or a phase locked loop.

The clock multiplier <NUM> receives the internal reference clock signal iCREF from the locking circuit <NUM>. The clock multiplier <NUM> generates a fifth clock signal CLK5 through frequency multiplication of the internal reference clock signal iCREF. The clock multiplier <NUM> may correspond to the clock multiplier <NUM> of <FIG> and <FIG>.

The receiver <NUM> may receive a signal from the host device <NUM> through the link LINK. The receiver <NUM> may receive a signal in synchronization with the fifth clock signal CLK5. The signal received by the receiver <NUM> may be a signal of a first type (e.g., a serial type). The signal received by the receiver <NUM> may be a portion of a packet or a portion of a symbol. The receiver <NUM> may amplify the received signal and may provide the amplified signal to the deserializer <NUM>.

The deserializer <NUM> may receive a signal from the receiver <NUM>. The deserializer <NUM> may deserialize the received signal. The deserializer <NUM> may provide the decoder <NUM> with a deserialized signal of a second type (e.g., a parallel type).

The decoder <NUM> may receive a signal of the second type from the deserializer <NUM>. The decoder <NUM> may perform decoding on the signal of the second type. For example, the decoder <NUM> may perform symbol decoding to extract bits from a symbol. The decoder <NUM> may extract <NUM>-bit data from a <NUM>-bit symbol. Alternatively, the decoder <NUM> may extract <NUM>-bit data from a <NUM>-bit symbol. The decoder <NUM> may provide the decoded signal to the receiver logic <NUM>.

The receiver logic <NUM> may receive the decoded signal from the decoder <NUM>. The receiver logic <NUM> may perform pattern check on the decoded signal to determine compliance. For example, the receiver logic <NUM> may determine whether the decoded signal coincides with a communication protocol (e.g., a PCIe); when the decoded signal coincides with the communication protocol (e.g., a PCIe), the receiver logic <NUM> may determine which generation corresponds to a generation of the communication protocol coinciding with the decoded signal. When the pattern check is successful, the receiver logic <NUM> may provide the decoded signal to the processor <NUM> through the bus <NUM>.

The transmitter logic <NUM> may receive a signal of the second type (e.g., a parallel type) from the processor <NUM> through the bus <NUM>. The transmitter logic <NUM> may combine the signal of the second type and a pattern. For example, the pattern may indicate which generation corresponds to the communication protocol (e.g., a PCIe). The transmitter logic <NUM> may provide the combined signal to the encoder <NUM>.

The encoder <NUM> may receive the combined signal from the transmitter logic <NUM>. The encoder <NUM> may perform encoding on the combined signal. For example, the encoder <NUM> may perform symbol encoding to generate a symbol from bits of the combined signal. The encoder <NUM> may generate a <NUM>-bit symbol from <NUM>-bit data. Alternatively, the encoder <NUM> may generate a <NUM>-bit symbol from <NUM>-bit data. The encoder <NUM> may provide the encoded signal to the serializer <NUM>.

The serializer <NUM> may receive the encoded signal from the encoder <NUM>. The serializer <NUM> may receive the fifth clock signal CLK5 from the clock multiplier <NUM>. The serializer <NUM> may generate a signal of the first type (e.g., a serial type) by performing serialization on the encoded signal based on the fifth clock signal CLK5. The serializer <NUM> may provide the signal of the first type to the driver <NUM>.

The driver <NUM> may receive the signal of the first type from the serializer <NUM>. The driver <NUM> may transmit the signal of the first type to the host device <NUM>.

The interface circuit <NUM> of the host device <NUM> and the host interface circuit <NUM> of the controller <NUM> in the storage device <NUM> may match a frequency multiplication ratio at which the clock multiplier <NUM> generates the fourth clock signal CLK4 and a frequency multiplication ratio at which the clock multiplier <NUM> or <NUM> generates the fifth clock signal CLK5. For example, depending on a generation version of the communication protocol (e.g., a PCIe), a frequency multiplication ratio may be selected as a value including <NUM> times, <NUM> times, <NUM> times, <NUM> times, or <NUM> times.

As a frequency multiplication ratio increases, the power consumption of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may increase. As a frequency multiplication ratio decreases, the power consumption of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may decrease.

In response to an operating speed decrease, the storage device <NUM> according to an example embodiment may request the host device <NUM> to decrease the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>. In the case of an operating speed decrease, even though the host device <NUM> transmits data to the storage device <NUM> at a high speed, a speed at which the storage device <NUM> processes the received data may be low. An example of the storage device <NUM> processing data being low is performing a background operation (e.g., an urgent background operation) such as a migration operation of data from the first area <NUM> to the second area <NUM>, from the second area <NUM> to the first area <NUM>, inside the first area <NUM> or inside the second area, a garbage collection operation, a scrubbing operation, etc. Another example of the storage device <NUM> processing data being low may be described below. That is, an actual speed at which data are processed may place a limit on an operating speed of the storage device <NUM>.

Accordingly, by decreasing the frequency multiplication ratios as an operating speed decreases, the power consumption of the host device <NUM> and the storage device <NUM> may be reduced while processing data at an optimum speed.

<FIG> illustrates a first example of an operating method of the storage device <NUM> according to an example embodiment. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, in operation S110, the controller <NUM> may receive a write request from the host device <NUM>. In operation S120, the controller <NUM> may write write-requested data into the first area <NUM> of the nonvolatile memory device <NUM>.

In operation S130, the controller <NUM> may determine whether a free capacity of the first area <NUM> is smaller than or equal to a first threshold value TV1. For example, the first threshold value TV1 may be determined as a ratio of a total capacity of the first area <NUM>. The first threshold value TV1 may be variously determined, for example, as <NUM>%, <NUM>%, <NUM>%, <NUM>%, etc..

The determination that the free capacity of the first area <NUM> (faster area) is smaller than or equal to the first threshold value TV1 may lead to the following congestion event. The congestion event is that additional data received from the host device <NUM> cause a direct write operation to the second area <NUM> (slower area). A write speed of the second area <NUM> may be slower than a write speed of the first area <NUM>. That is, when the free capacity of the first area <NUM> is smaller than or equal to the first threshold value TV1, a write speed at which the controller <NUM> writes data into the nonvolatile memory device <NUM> may decrease, a speed at which the controller <NUM> accesses the nonvolatile memory device <NUM> may decrease, and an operating speed of the storage device <NUM> may decrease. Thus, the congestion event causes the operating speed of the storage device <NUM> to decrease.

In response to the operating speed of the storage device <NUM> decreasing (congestion event), in operation S140, the controller <NUM> may request the host device <NUM> to decrease a link speed. For example, the controller <NUM> may request the host device <NUM> to decrease the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>. In an example embodiment, the adjustment of multiplication ratios may be requested such that a data transfer rate of the link LINK is similar to a speed at which the controller <NUM> writes data into the second area <NUM> (slower area).

That is, the controller <NUM> may detect the reduction of an operating speed in response to the free capacity of the first area <NUM> decreasing. In response to the operating speed decrease, the controller <NUM> may request the host device <NUM> to decrease a link speed. Accordingly, the power consumption of the host device <NUM> and the storage device <NUM> may be reduced to a state in which a speed of processing write data is not hindered.

<FIG> illustrates an example of a register of the controller <NUM>. The register illustrated in <FIG> may be, for example, a link control register for a control of the link LINK. In <FIG>, the bits of the register are labelled from right to left (<NUM>,<NUM>), <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, (<NUM>,<NUM>), and (<NUM>,<NUM>). Parentheses are used to indicate where two bits together are used for control or configuration of something. Also, the three bits (<NUM>, <NUM>, and <NUM>) jointly form a control configuration. The roles of the register bits are described below.

Referring to <FIG> and <FIG>, a <NUM>-th bit and a first bit of the register may be used for active state power management (ASPM) control. A third bit of the register may be used for read completion boundary. A fourth bit of the register may be used for link disable. A fifth bit of the register may be used to retrain the link LINK. A retrain may refer to redoing some parts of a transmitter equalization process of the link LINK.

A sixth bit of the register may be used for common clock configuration. A seventh bit of the register may be used for extended synch. An eighth bit of the register may be used to enable clock power management. A ninth bit of the register may be used for hardware autonomous width disable.

A tenth bit of the register may be used for a link bandwidth management interrupt enable. An eleventh bit of the register may be used for a link autonomous bandwidth interrupt enable. A fourteenth bit and a fifteenth bit of the register may be used for device readiness status (DRS) signaling control.

A second bit, a twelfth bit, and a thirteenth bit of the register may be used for dynamic link control. The dynamic link control may include a technical feature that the storage device <NUM> requests the host device <NUM> to change a transmission rate of the link LINK in response to a change of an operating speed. The dynamic link control may be a feature of the example embodiments described above and the example embodiments described below.

At least one of the second bit, the twelfth bit, and the thirteenth bit of the register may be used to indicate an enable or disable of the dynamic link control. When an operating speed does not decrease, the controller <NUM> may set at least one of the second bit, the twelfth bit, and the thirteenth bit of the register to a first value (e.g., "<NUM>").

In response to an operating speed decrease, the controller <NUM> may set at least one of the second bit, the twelfth bit, and the thirteenth bit of the register to a second value (e.g., "<NUM>"). Also, in response to the operating speed decrease, the controller <NUM> may request a retrain operation from the host device <NUM> by setting the fifth bit of the register to a specific value.

In an example embodiment, in response to at least one of the second bit, the twelfth bit, and the thirteenth bit of the register being set to the second value and the fifth bit of the regulator being set to the specific value, the controller <NUM> may transmit an interrupt to the host device <NUM>. The host device <NUM> may read the register in response to the interrupt. Afterwards, the host device <NUM> and the storage device <NUM> may decrease multiplication ratios through the retrain operation.

For another example, the host device <NUM> may perform polling to read the register periodically. After reading the register, the host device <NUM> and the storage device <NUM> may decrease multiplication ratios through the retrain operation.

<FIG> illustrates a process in which the storage device <NUM> establishes the link LINK with the host device <NUM>. Referring to <FIG> and <FIG>, an initial state may be a detect state. In the detect state, when a connection with any other device (e.g., the host device <NUM>) is detected, the storage device <NUM> may enter a polling state.

In the polling state, a generation version of a protocol (e.g., a PCIe) of the host device <NUM> and a generation version of a protocol (e.g., a PCIe) of the storage device <NUM> may be checked, and a data transfer rate may be determined based on the highest generation version compatible with each other. Also, in the polling state, the controller <NUM> may set a bit lock, a symbol lock, a block lock, and a lane polarity. In the polling state, the controller <NUM> may transmit TS1 and TS2 being an ordered set at a transmission rate of <NUM> GT/s (gigatransfers per second). A transfer may refer to one data transfer event in a given data-transfer channel.

After the polling state, the storage device <NUM> may enter a configuration state. In the configuration state, the controller <NUM> may set the number of lanes of the link LINK, that is, a link width. Also, in the configuration state, the controller <NUM> may exchange TS1 and TS2 with the host device <NUM> at a transmission rate of <NUM> GT/s. The controller <NUM> may allocate a lane number and may check and calibrate a lane reversal. The controller <NUM> may de-skew a lane-to-lane timing difference (reduce a time skew between lanes).

After the configuration state, the controller <NUM> may enter an L0 state. The L0 state may be a normal state. In the L0 state, the controller <NUM> may communicate with the host device <NUM> through the link LINK.

An L0s state may be an ASPM state. The controller <NUM> may reduce power consumption in the L0s state until the controller <NUM> enters the L0 state. An L1 state may be a power saving state in which power consumption is reduced more than in the L0s state. In an L2 state, a voltage low enough to detect a wake-up event may be used.

Entering a disabled state may be made when the controller <NUM> disables the link LINK. A loopback state may be a state that the controller <NUM> uses for test and fault isolation. A hot reset state may be used when the controller <NUM> resets the link LINK through in-band signaling.

A recovery state is used for the controller <NUM> to adjust a data transfer rate. In the recovery state, the controller <NUM> adjusts the frequency multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>. A recovery may occur if an error occurs on the link LINK and it is necessary to re-initialize the link LINK so that transfers can resume. After the recovery, the link LINK may be said to be recovered. If the link LINK is operating at a first operating speed and an error occurs, recovery may be performed. The first operating speed may then be said to be a recovered operating speed. Also see the discussion of <FIG> below, in which a transition is made from a recovery state to the normal state L0.

By, for example, setting the dynamic link control bit of the link control register in the L0 state and requesting the retrain operation, the controller <NUM> adjusts the frequency multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>.

As the retrain operation is requested, the controller <NUM> may enter the recovery state and adjusts the frequency multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>. Afterwards, the controller <NUM> may return to the L0 state, may return to the configuration state, or may return to the detect state. Alternatively, the controller <NUM> may return to the detect state through the hot reset state.

<FIG> illustrates a second example of an operating method of the storage device <NUM>. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, in operation S210, the controller <NUM> may allow data written in the first area <NUM> of the nonvolatile memory device <NUM> to migrate to the second area <NUM>. For example, the data that migrate to the second area <NUM> may be removed from the first area <NUM>. That is, the free capacity of the first area <NUM> may increase.

In operation S220, the controller <NUM> may determine whether the free capacity of the first area <NUM> is greater than or equal to a second threshold value TV2. For example, the second threshold value TV2 may be determined as a ratio of a total capacity of the first area <NUM>. The second threshold value TV2 may be variously determined, for example, as <NUM>%, <NUM>%, <NUM>%, <NUM>%, etc..

The determination that the free capacity of the first area <NUM> (faster area) is greater than or equal to the second threshold value TV2 may indicate the following speed-up opportunity. Recognizing the speed-up opportunity improves operating speed when additional data is received from the host device <NUM>, the additional data causing a write operation to the first area <NUM>. Specifically, A write speed of the first area <NUM> may be higher than a write speed of the second area <NUM> (slower area). That is, when the free capacity of the second area <NUM> is greater than or equal to the second threshold value TV2, a write speed at which the controller <NUM> writes data into the nonvolatile memory device <NUM> may increase (or may be recovered), a speed at which the controller <NUM> accesses the nonvolatile memory device <NUM> may increase (or may be recovered), and an operating speed of the storage device <NUM> may increase (or may be recovered). Thus, making use of the speed-up opportunity allows the operating speed of the storage device <NUM> to increase.

In response to the operating speed of the storage device <NUM> increasing (or being recovered), in operation S230, the controller <NUM> may increase (or recover) a data transfer rate of the link LINK. For example, the controller <NUM> may increase a link speed. The controller <NUM> may request an increase of a link speed by setting (or recovering) the dynamic link control bit of the register to the first value and requesting the retrain operation as described with reference to <FIG>.

As described above, the host device <NUM> may read the register in response to an interrupt from the controller <NUM> or based on the polling. As described with reference to <FIG>, the host device <NUM> and the controller <NUM> may increase (or recover) a link speed through the recovery state.

In an example embodiment, the operating speed of the storage device <NUM> may stepwise decrease. The nonvolatile memory device <NUM> may include three or more areas having different access (or write) speeds. When an access to a specific area (or a write operation for the specific area) is requested, the controller <NUM> may stepwise increase or decrease a data transfer rate of the link LINK. That is, multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may be stepwise adjusted.

For example, as an operating speed decreases to a first step, the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM>.

of the storage device <NUM> may decrease to a first step. As the operating speed decreases to a second step, the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may decrease to a second step.

As the operating speed is recovered to the first step, the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may be recovered to the first step. As the operating speed is recovered to the second step, the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM> may be recovered to the second step.

<FIG> illustrates an example of the link LINK established between the interface circuit <NUM> of the host device <NUM> and the host interface circuit <NUM> of the storage device <NUM>. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the link LINK may include at least one lane LANE.

For example, the link LINK may include lanes LANE, the number of lanes corresponds to a number selected from numbers of <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In an example embodiment, it is assumed that four lanes LANE are included in the link LINK. The lanes LANE may transmit or receive signals at the same time. The lanes LANE may correspond to parallel signal lines. For example, each lane may contain two pairs of wires, one pair to send and one pair to receive. A link including one lane is thus made up of four wires. The lanes LANE may be set to have the same link speed.

A data transfer rate of the link LINK may be determined by a product of the number of lanes LANE included in the link LINK, that is, a link width and a link speed of each of the lanes LANE. To adjust a data transfer rate of the link LINK, the storage device <NUM> according to an example not covered by the claims may adjust a link width, that is, the number of lanes LANE included in the link LINK.

Each of the lanes LANE may include a transmit channel and a receive channel. The transmit channel of the host interface circuit <NUM> may correspond to a dotted arrow facing toward the interface circuit <NUM> from the host interface circuit <NUM>. The receive channel of the host interface circuit <NUM> may correspond to a dotted arrow facing toward the host interface circuit <NUM> from the interface circuit <NUM>. Each of the transmit channel and the receive channel may include complementary signal lines.

<FIG> illustrates a third example of an operating method of the storage device <NUM>. Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, in operation S310, the controller <NUM> may receive a write request from the host device <NUM>. In operation S320, the controller <NUM> may write write-requested data into the first area <NUM> of the nonvolatile memory device <NUM>.

In operation S330, the controller <NUM> may determine whether a free capacity of the first area <NUM> is smaller than or equal to the first threshold value TV1. For example, the first threshold value TV1 may be determined as a ratio of a total capacity of the first area <NUM>. The first threshold value TV1 may be variously determined, for example, as <NUM>%, <NUM>%, <NUM>%, <NUM>%, etc..

When the free capacity of the first area <NUM> is smaller than or equal to the first threshold value TV1, a write speed at which the controller <NUM> writes data in the nonvolatile memory device <NUM> may decrease, a speed at which the controller <NUM> accesses the nonvolatile memory device <NUM> may decrease, and an operating speed of the storage device <NUM> may decrease (a congestion event).

In response to the operating speed of the storage device <NUM> decreasing, in operation S340, in an example not covered by the claims, the controller <NUM> may request the host device <NUM> to decrease a link width, that is, the number of lanes LANE included in the link LINK. In an example, the adjustment of the number of lanes LANE (e.g., the number of enabled lanes and the number of disabled lanes) may be requested such that a data transfer rate of the link LINK is similar to a speed at which the controller <NUM> writes data into the second area <NUM> (slower area).

That is, in an example not covered by the claims, the controller <NUM> may detect the reduction of an operating speed in response to the free capacity of the first area <NUM> decreasing. In response to the operating speed decrease, the controller <NUM> may request the host device <NUM> to decrease a link width. Accordingly, the power consumption of the host device <NUM> and the storage device <NUM> may be reduced while a speed at which write data are processed by the storage device <NUM> is not hindered.

In an example not covered by the claims, as described with reference to <FIG> and <FIG>, the controller <NUM> may adjust the number of enabled lanes of the link LINK (or the number of disabled lanes thereof) by setting the dynamic link control bit of the register in the L0 state and requesting the retrain operation.

<FIG> illustrates an example not covered by the claims in which a width of the link LINK is reduced compared to <FIG>. Referring to <FIG>, a width of the link LINK may decrease from <NUM> to <NUM>. In an example embodiment, the interface circuit <NUM> and the host interface circuit <NUM> may maintain two of four lanes at a disable state and may set the remaining lanes, that is, two lanes to an enable state so as be included in the link LINK. <FIG> illustrates that a host and storage device may be physically connected by a fixed number of wires which generally do not change with time. Also, in <FIG> the number of wires in an enable state can be configured dynamically; that is the number of wires in an enable state can be generally changed at different times. The expression "LINK" refers to a configuration of wires in an enable state at a given point in time.

<FIG> illustrates a fourth example of an operating method of the storage device <NUM>. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, in operation S410, the controller <NUM> may allow data written into the first area <NUM> of the nonvolatile memory device <NUM> to migrate to the second area <NUM>. For example, the data that migrate to the second area <NUM> may be removed from the first area <NUM>. That is, the free capacity of the first area <NUM> may increase.

In operation S420, the controller <NUM> may determine whether the free capacity of the first area <NUM> is greater than or equal to the second threshold value TV2. For example, the second threshold value TV2 may be determined as a ratio of a total capacity of the first area <NUM>. The second threshold value TV2 may be variously determined, for example, as <NUM>%, <NUM>%, <NUM>%, <NUM>%, etc..

That is, when the free capacity of the second area <NUM> is greater than or equal to the second threshold value TV2, a write speed at which the controller <NUM> writes data into the nonvolatile memory device <NUM> may increase (or may be recovered), a speed at which the controller <NUM> accesses the nonvolatile memory device <NUM> may increase (or may be recovered), and an operating speed of the storage device <NUM> may increase (or may be recovered).

In response to the operating speed of the storage device <NUM> increasing (or being recovered), in operation S430, the controller <NUM> may increase (or recover) a data transfer rate of the link LINK. For example, the controller <NUM> may increase a link speed. The controller <NUM> may request an increase of a link speed by setting (or recovering) the dynamic link control bit of the register to the first value and requesting the retrain operation as described with reference to <FIG>.

In an example embodiment, the operating speed of the storage device <NUM> may stepwise decrease. The nonvolatile memory device <NUM> may include three or more areas having different access (or write) speeds. When an access to a specific area (or a write operation for the specific area) is requested, the controller <NUM> may stepwise increase or decrease a data transfer rate of the link LINK. That is, in an example not covered by the claims, the number of enabled lanes of the link LINK and the number of disabled lanes of the link LINK may be stepwise adjusted.

In an example not covered by the claims, as an operating speed decreases to a first step, the number of disabled lanes of the link LINK may decrease to the first step. As the operating speed decreases to a second step, the number of disabled lanes of the link LINK may decrease to the second step.

As the operating speed is recovered to the first step, the number of enabled lanes of the link LINK may be recovered to the first step. As the operating speed is recovered to the second step, the number of enabled lanes of the link LINK may be recovered to the second step.

<FIG> illustrates a storage device <NUM>' according to another embodiment establishing the link LINK with the host device <NUM>. Referring to <FIG>, the host device <NUM> corresponds to the host device <NUM> of <FIG>. Thus, additional description will be omitted to avoid redundancy. The storage device <NUM>' includes the same components as the storage device <NUM> of <FIG> except that the storage device <NUM>' further includes a temperature sensor <NUM>. Thus, additional description will be omitted to avoid redundancy.

The controller <NUM> may receive temperature information indicating a current temperature (e.g., an internal temperature or a case temperature) of the storage device <NUM>' from the temperature sensor <NUM>. The controller <NUM> may perform dynamic temperature throttling based on a temperature that the temperature information indicates.

For example, as a temperature increases, the controller <NUM> may decrease a frequency of a clock signal used in the processor <NUM> or the bus <NUM>. That is, in response to a temperature increase, the controller <NUM> may decrease an operating speed of the storage device <NUM>'. In response to the operating speed decrease of the storage device <NUM>', the controller <NUM> may decrease a data transfer rate of the link LINK.

<FIG> illustrates a first example of an operating method of the storage device <NUM>' according to an example embodiment. Referring to <FIG>, <FIG>, <FIG>, <FIG> and <FIG>, in operation S510, the controller <NUM> may receive temperature information from the temperature sensor <NUM>. In operation S520, the controller <NUM> may determine whether a temperature is greater than or equal to a third threshold value TV3.

When the temperature is greater than or equal to the third threshold value TV3, an operating speed of the storage device <NUM>' may be decreased (dynamic temperature throttling). In response to the operating speed decrease of the storage device <NUM>', in operation S530, the controller <NUM> may request the host device <NUM> to decrease a link speed or a link width.

For example, the controller <NUM> may request the host device <NUM> to decrease multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>'. Alternatively, in an example not covered by the claims, the controller <NUM> may request the host device <NUM> to decrease the number of lanes LANE included in the link LINK.

That is, the controller <NUM> may detect the reduction of an operating speed in response to a temperature increase. In response to the operating speed decrease, the controller <NUM> may request the host device <NUM> to decrease a link speed. Accordingly, the power consumption of the host device <NUM> and the storage device <NUM>' may be reduced in a state where a speed at which write data are processed is not hindered.

In an embodiment, as described with reference to <FIG> and <FIG>, the controller <NUM> adjusts the multiplication ratios of the clock multiplier <NUM> of the host device <NUM> and the clock multiplier <NUM> or <NUM> of the storage device <NUM>'. In an alternative example not covered by the claims, the controller <NUM> adjusts the number of enabled lanes of the link LINK (or the number of disabled lanes thereof). Both adjustments may be by setting the dynamic link control bit of the register in the L0 state and requesting the retrain operation.

As described above, the host device <NUM> may read the register in response to an interrupt from the controller <NUM> or based on the polling. As described with reference to <FIG>, the host device <NUM> and the controller <NUM> may decrease a link speed or, in an example not covered by the claims, a link width through the recovery state.

<FIG> illustrates a second example of an operating method of the storage device <NUM>'. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, in operation S610, the controller <NUM> may receive temperature information from the temperature sensor <NUM>. In operation S620, the controller <NUM> may determine whether a temperature is smaller than or equal to a fourth threshold value TV4. For example, the fourth threshold value TV4 may be the same as or different from the third threshold value TV3.

When the temperature is smaller than or equal to the fourth threshold value TV4, the controller <NUM> may release the dynamic temperature throttling. That is, when the temperature is smaller than or equal to the fourth threshold value TV4, a write speed at which the controller <NUM> writes data into the nonvolatile memory device <NUM> may be increased (or may be recovered), a speed at which the controller <NUM> accesses the nonvolatile memory device <NUM> may be increased (or may be recovered), and an operating speed of the storage device <NUM>' may be increased (or may be recovered).

In response to the operating speed increase of the storage device <NUM>' (or operating speed recovery), in operation S630, the controller <NUM> may increase (or recover) a data transfer rate of the link LINK. For example, the controller <NUM> may increase a link speed or, in an example not covered by the claims, a link width. The controller <NUM> may request an increase of a link speed or, in an example not covered by the claims, a link width by setting (or recovering) the dynamic link control bit of the register to the first value and requesting the retrain operation as described with reference to <FIG>.

As described above, the host device <NUM> may read the register in response to an interrupt from the controller <NUM> or based on the polling. As described with reference to <FIG>, the host device <NUM> and the controller <NUM> may increase (or recover) a link speed or, in an example not covered by the claims, a link width through the recovery state.

In an example embodiment, the operating speed of the storage device <NUM>' may stepwise decrease. The controller <NUM> may compare a temperature with two or more different threshold values and may stepwise adjust a link speed or, in an example not covered by the claims, a link width based on the different threshold values.

For example, as an operating speed decreases to a first step, a data transfer rate of the link LINK may decrease to the first step. As the operating speed decreases to a second step, the data transfer rate of the link LINK may decrease to the second step. As the operating speed is recovered to the first step, the data transfer rate of the link LINK may be recovered to the first step. As the operating speed is recovered to the second step, the data transfer rate of the link LINK may be recovered to the second step.

In an example embodiment, the embodiment of the storage device <NUM> of <FIG> and the embodiment of the storage device <NUM>' of <FIG> may be combined. The storage device <NUM>' may adjust a data transfer rate of the link LINK based on a free capacity of the first area <NUM> and/or based on a temperature.

Also, the storage device <NUM> or <NUM>' selectively adjusts a link speed and a link width for the purpose of adjusting a data transfer rate. The controller <NUM> selects at least the adjustment of a link speed among the adjustment of a link speed and the adjustment of a link width. The controller <NUM> selects at least the adjustment of a link speed among the adjustment of a link speed and the adjustment of a link width depending on a desired decrease step of an operating speed.

In an example embodiment, the storage device <NUM> of <FIG> and the storage device <NUM>' of <FIG> may further include a buffer memory disposed outside the nonvolatile memory device <NUM> and the controller <NUM>. The controller <NUM> may write data provided from the host device <NUM> into the buffer memory and may write the data written into the buffer memory into the nonvolatile memory device <NUM>.

<FIG> illustrates a storage device <NUM>" according to another embodiment establishing the link LINK with the host device <NUM>. Referring to <FIG>, the host device <NUM> is the same as the host device <NUM> of <FIG>. Thus, repeated description will be omitted. The storage device <NUM>" includes the same components as the storage device <NUM> of <FIG> except that the storage device <NUM>" further includes a buffer memory <NUM>. Thus, repeated description will be omitted.

The controller <NUM> may store data received from the host device <NUM> in the buffer memory <NUM>. The controller <NUM> may support a write-back scheme to report a write completion to the host device <NUM> when the data are written into the buffer memory <NUM>.

When a free capacity of the buffer memory <NUM> is insufficient, the controller <NUM> may perform a flush operation of writing data stored in the buffer memory <NUM> into the nonvolatile memory device <NUM>. While the flush operation is performed, the controller <NUM> may not process a request of the host device <NUM>. That is, the performance of operation of the storage device <NUM>" may be reduced. In response to an operating speed of the storage device <NUM>" decreasing, the controller <NUM> may decrease a data transfer rate of the link LINK.

For example, the controller <NUM> may decrease a data transfer rate of the link LINK in response to the free capacity of the buffer memory <NUM> being smaller than or equal to a fifth threshold value. The controller <NUM> may perform the flush operation in response to the free capacity of the buffer memory <NUM> being smaller than or equal to a sixth threshold value. The fifth threshold value may be greater than the sixth threshold value. That is, when a decrease of an operating speed of the storage device <NUM>" is expected, the controller <NUM> may decrease a data transfer rate of the link LINK.

As described with reference to <FIG>, the storage device <NUM>" may further include the temperature sensor <NUM>. The storage device <NUM>" may be further configured to adjust a data transfer rate of the link LINK in response to the dynamic temperature throttling being enabled.

The example embodiments are described mainly with reference to the PCIe protocol. However, various protocols such as NVMe, SATA, SAS, USB, and UFS may be applicable to the embodiments.

In the above example embodiments, components according to the present disclosure are described by using the terms "first", "second", "third", and the like. However, the terms "first", "second", "third", and the like may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", and the like do not involve an order or a numerical meaning of any form.

In the above example embodiments, components according to embodiments are described by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits enrolled as intellectual property (IP).

Claim 1:
A system comprising:
a host device (<NUM>) comprising a clock multiplier (<NUM>) configured to generate a first clock signal (CREF), and
a storage device (<NUM>) comprising:
a nonvolatile memory device (<NUM>); and
a controller (<NUM>) configured to:
access the nonvolatile memory device (<NUM>) based on a request from the host device (<NUM>),
receive the first clock signal (CREF) from the host device (<NUM>),
generate a second clock signal (CLK5) through frequency multiplication of the first clock signal (CREF), and
communicate with the host device (<NUM>) based on the second clock signal (CLK5),
the controller (<NUM>) is configured to adjust a multiplication ratio for the frequency multiplication of the first clock signal (CREF) and a multiplication ratio of the clock multiplier (<NUM>).