Patent Description:
One or more embodiments can be applied to circuits for monitoring a health state of transistors.

Health monitoring of electronic components is the prognosis of potential failures of such components and consists in measuring the deviation of electrical parameters that can be correlated with the physical degradation of such components.

Health monitoring is of great importance as electronic components are widely used in most systems and their failures may lead to breakdowns and/or shutdowns of such systems, so preventing such failures may increase the robustness and reliability of systems.

Specifically, health monitoring is of relevance in the automotive field wherein preventing hazards may increase passenger safety.

In fact, ISO26262, which is the actual international standard considered for the functional safety of electrical and/or electronic systems that are installed in serial production road vehicles, defines a minimum requirement for safety which is measured using the Automotive Safety Integrity Level (ASIL) that is a safety level determined through hazard analysis and risk assessment.

Therefore, failures prediction and health monitoring of vehicle's electrical components may increase the ASIL safety level of a vehicle, allowing preemptive maintenance or replacement of electronic components considered at risk.

To satisfy ISO26262 requirements, safety critical environments such as automotive power distribution environments may use E-Fuses ("Electronic Fuses") with a high ASIL safety level. Such E-Fuses are integrated power path protection devices used to limit circuit currents and/or voltages to safe levels during fault conditions.

Usually, such E-Fuses may perform an inrush current control using a Power MOSFET. In certain failure conditions, such Power MOSFET may be affected by short circuit failures, i.e., failures wherein the Power MOSFET cannot be controlled through its gate to be turned off, lowering the reliability of E-Fuses and, consequently, leading to a safety-critical situation.

Such short circuit failures in Power MOSFETs may be generated by physical degradations of the gate structure, such as:.

In particular, this last condition may result in a reduction of the threshold voltage of a Power MOSFET, such threshold voltage corresponding to the voltage needed for switching the state of such Power MOSFET from a non-conductive state ("OFF") to a conductive state ("ON").

Such reduction may continue until the Power MOSFET, and consequently the corresponding device, i.e., the corresponding E-Fuse, remains normally in a conductive ON state, for instance, if the value of the threshold voltage of the Power MOSFET decreases to zero or to a negative value so that such Power MOSFET cannot be controlled through its gate to be turned off, i.e., to be switched to a non-conductive state.

For example, <FIG> illustrates an E-Fuse structure <NUM> showing the effects of the physical degradation of a Power MOSFET <NUM>.

In <FIG> gate capacitance CDG, i.e., between a drain terminal D and a gate terminal G of the Power MOSFET <NUM>, and CGS, i.e., between the gate terminal G and a source terminal S of the Power MOSFET <NUM>, of the Power MOSFET <NUM> are represented as a drain-gate capacitor <NUM> of value equal to CDG and a gate-source capacitor <NUM> of value equal to CGS respectively.

A controller <NUM> is configured to send to a gate driver <NUM> an ON command CON or an OFF command COFF, in order to set the state of the Power MOSFET <NUM> to an ON state, i.e., a conductive state, or to an OFF state, i.e., a non-conductive state, respectively.

The gate driver <NUM> is configured to vary the value of a gate-source voltage VGS between the gate terminal G and the source terminal S of the Power MOSFET <NUM> in response to the reception of a command from the controller <NUM>.

In particular, in response to the ON command CON, the gate driver <NUM> is configured to set the value of the gate-source voltage VGS to a first value that is higher than a threshold voltage VTH of the Power MOSFET <NUM> in order to set the state of such Power MOSFET <NUM> to the conductive ON state.

Conversely, in response to the OFF command COFF, the gate driver <NUM> is configured to set the value of the gate-source voltage VGS to a second value that is lower than such threshold voltage VTH of the Power MOSFET <NUM>, for instance, to zero, in order to set the state of the Power MOSFET <NUM> to the non-conductive OFF state.

A blocking diode <NUM> is coupled between the source S and the drain D of the Power MOSFET <NUM> to protect the Power MOSFET <NUM> against reverse polarity connections.

In <FIG>, the controller <NUM> is configured to send the OFF command COFF to the gate driver <NUM> that, in response to the reception of such OFF command COFF, is configured to set the value of the gate-source voltage VGS to the second value, i.e., to a value lower than the threshold voltage VTH of the Power MOSFET <NUM>, for instance, to zero.

In such a case, if the physical structure of the gate G of the Power MOSFET <NUM> is degraded, for instance, resulting in a relevant reduction of the value of the threshold voltage VTH, for instance, if the current value of the threshold voltage VTH is a negative value, both the Power MOSFET <NUM> and the corresponding E-Fuse <NUM> remain in a conductive ON state even after the reception of an OFF command COFF, thus, a current IDS flows between the drain terminal D and the source terminal S of the Power MOSFET <NUM> even after the reception of such OFF command COFF.

Therefore, the E-Fuse <NUM> remains in a conductive ON state even if the controller <NUM> has sent a command for requesting a switch of such E-Fuse to a non-conductive OFF state, thus, generating a short circuit failure characterized by an uncontrolled conduction.

Such short circuit failures strongly compromise safety requirements imposed by ISO26262, since the Power MOSFET <NUM> and the corresponding device, i.e., the corresponding E-Fuse <NUM>, cannot be controlled and switched off if required, i.e., such E-Fuse <NUM> with a corresponding Power MOSFET <NUM> failed in short circuit cannot limit currents and/or voltages to safe levels when required.

In fact, in an E-Fuse <NUM> with a corresponding Power MOSFET <NUM> failed in short circuit, the current IDS flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM> cannot be interrupted, and, consequently, a circuit to be protected coupled to the drain terminal D and/or to the source terminal S of such Power MOSFET <NUM> cannot be interrupted, i.e., its over-currents and/or over-voltages cannot be limited, thus, the protection fails.

In addition, the uncontrolled ON state of a Power MOSFET <NUM> may generate high power dissipation, resulting in high temperatures, for instance, rising the temperature of an ECU ("Electronic Control Unit") wherein a corresponding E-Fuse <NUM> with a Power MOSFET <NUM> failed in short circuit is installed, leading to fire hazards.

Prior art document <CIT> teaches an arrangement for monitoring a MOSFET, wherein the FET is biased in sub-threshold, and a free-wheeling current from an inductor is injected into its source in order to identify a Vgs-th degraded FET.

Solutions that facilitate the health monitoring of such devices to prevent short circuit failures would be beneficial in order to have an early prognosis on the degradation of such devices and to prevent potential failures resulting in uncontrolled conduction.

An object of one or more embodiments is to contribute in providing solutions that facilitate the health monitoring of MOSFETs, preventing short circuit failures in order to have an early prognosis on the degradation of both such MOSFETs and corresponding devices, for instance, E-Fuses, and to prevent potential failures resulting in uncontrolled conduction.

According to one or more embodiments, that object is achieved via a circuit having the features set forth in the claims that follow.

One or more embodiments concern a corresponding method.

The claims are an integral part of the technical teaching provided in respect of the embodiments.

Solutions as described herein include a circuit for monitoring an actual threshold voltage value of a Power MOSFET comprising:.

wherein such control unit is further configured to, according to such received test mode signal, select the status of coupling or decoupling of such current source to/from the source terminal of the Power MOSFET,.

In various embodiments, if such test mode signal indicates a first test mode such control unit is configured to:.

while if such test mode signal indicates a second mode such control unit is further configured to:.

In various embodiments, such test mode signal is configured to indicate a first submode of such first test mode and a second submode of such first mode, wherein in the first submode mode such given time period is shorter than the period in the second mode.

In various embodiments, such circuit is coupled to an external load through the source terminal of the Power MOSFET, and.

In various embodiments, such MOSFET is a Power MOSFET.

In various embodiments, such plurality of voltage value comprises a first voltage value and a second voltage value, such first voltage value being retrieved at the beginning of the given time period while such second voltage value being retrieved at the end of the given time period, and
such compute operation to obtain the voltage variation as a function of such plurality of voltage value comprises subtracting such second voltage value from such first voltage value.

In various embodiments, such detection unit comprises:.

In various embodiments, such alarm generation unit comprises:.

In various embodiments, such circuit further comprises:.

In various embodiments, such circuit further comprises an additional switch configured to decouple a gate driver from the gate terminal of the Power MOSFET in response to the reception of a signal from the control unit indicating to start the monitoring of such actual threshold voltage value, and to couple the gate driver to the gate terminal of the Power MOSFET in response to the reception of a signal from the control unit indicating to end the monitoring of such actual threshold voltage value.

In various embodiments, such test voltage is fixed, or such test voltage is dynamic and such control unit is further configured to:.

In various embodiments, such circuit is further coupled with a temperature monitoring unit, such temperature monitoring unit being configured to:.

In various embodiments such circuit comprises a further switch, configured to couple or decouple such voltage generator to the gate terminal of the Power MOSFET in response to the reception of a signal from the control unit issued as a function of such test mode signal, and in such first and second mode such voltage generator is maintained coupled from the gate terminal of the Power MOSFET.

In various embodiments, such first and second mode such voltage generator is decoupled from the gate terminal of the Power MOSFET if a test enable signal mode is not set.

Solutions as described herein facilitate achieving the health monitoring of devices, for instance, E-Fuses, through the monitoring of corresponding MOSFETs so as to prevent short circuit failures in such MOSFETs. In this way, it may be possible to have an early prognosis on the degradation of both such MOSFETs and corresponding devices, i.e., E-Fuses, and to prevent potential failures resulting in uncontrolled conduction.

The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description.

Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

For simplicity and ease of explanation, throughout this description, and unless the context indicates otherwise, like parts or elements are indicated in the various figures with like reference signs, and a corresponding description will not be repeated for each and every figure.

In particular, in the following figures, parts, elements and/or components which have already been described with reference to <FIG> are denoted by the same references previously used in such figure, therefore, the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

As previously described, it would be beneficial to find solutions that facilitate the health monitoring of MOSFETs, preventing short circuit failures in order to have an early prognosis on the degradation of both such MOSFETs and corresponding devices, i.e., E-Fuses, and to prevent potential failures resulting in uncontrolled conduction.

According to embodiments of the present disclosure, a diagnostic as explained above, i.e., the health monitoring of MOSFETs and corresponding devices, may be done by monitoring the value of a threshold voltage VTH of a Power MOSFET <NUM> while such Power MOSFET <NUM> is coupled to a given circuit to be protected, i.e., while it is coupled to a given load.

It is noted that even if the following description is mainly focused on solutions using a Power MOSFET, for instance, an N-channel Power MOSFET or a P-channel Power MISFET, solutions as described herein may also be implemented considering GaN transistors or SiC Power MOSFET.

It is to be noted that even if the following description is mainly focused on the application of proposed solutions in the automotive sector, solutions as described herein may be used also in other application contexts wherein it is needed to measure and/or monitor a threshold voltage of a Power MOSFET with a coupled load, for instance, a resistive and/or capacitive load.

In many application contexts, standard threshold voltage VTH measurements cannot be used, for instance, as an E-Fuse <NUM>, i.e., a corresponding MOSFET, may be always coupled to a resistive and/or capacitive load, i.e., to a circuit to be protected. In addition, such an E-Fuse <NUM> may be configured to have the corresponding Power MOSFET <NUM> set by default to a conductive ON state (such Power MOSFET <NUM> may switch to a non-conductive OFF state only in case of over-currents and/or over-voltages detected in such circuit to be protected), so, in most cases, threshold voltage VTH measurements should be performed during the conductive ON state of such Power MOSFET <NUM>.

<FIG> illustrates a solution <NUM> for measuring the value of a threshold voltage VTH in a Power MOSFET <NUM>.

The Power MOSFET <NUM> of <FIG> is configured to:.

As illustrated in <FIG>, with such a structure <NUM> the drain-source voltage VDS, i.e., the voltage between the drain terminal D and the source terminal S, is equal to the gate-source voltage VGS, i.e., the voltage between the gate terminal G and the source terminal S, as both the drain terminal D and the gate terminal G are at the same voltage level VS.

Therefore, in the conditions of <FIG>, the drain-source voltage VDS is equal to the gate-source voltage VGS, and both of these voltages are equal to the value of the threshold voltage VTH of the Power MOSFET <NUM>.

Hence, the value of the threshold voltage VTH of the Power MOSFET <NUM> may be evaluated as a function of the value of the test current ITEST generated by the current source <NUM>.

Nevertheless, such a solution <NUM> cannot be used when a load is coupled to the source terminal S of the Power MOSFET <NUM>.

To this regard, <FIG> illustrates the solution <NUM> of <FIG> for measuring the value of the threshold voltage VTH in a Power MOSFET <NUM> as coupled to an external device <NUM>, i.e., represented by any capacitive load CLOAD, e.g., a load capacitor, and/or resistive load RLOAD, e.g., a load resistor.

It is noted that, although <FIG> shows a load <NUM> comprising a resistive load RLOAD and capacitive load CLOAD, such load <NUM> may present only a substantial resistive behaviour, i.e., may correspond to or may be modeled with only the resistive load component RLOAD, only capacitive, i.e., may correspond to or be modeled with only the capacitive load component CLOAD, or both resistive component RLOAD and capacitive component CLOAD.

As exemplified in <FIG>, when a load <NUM>, for instance, an ECU, is coupled to the source terminal S of the Power MOSFET <NUM>, the value of the test current ITEST generated by the current source <NUM> cannot be defined and set to a chosen value as its value is influenced by the given load <NUM>, i.e., by the voltage of the source terminal S that is determined by the voltage VLOAD on the load <NUM>, which may also be a variable voltage.

For example, this may be the case of an automotive environment wherein the load <NUM> may represent an ECU, i.e., an Electronic Control Unit, that may be modeled as a both resistive load RLOAD and capacitive (i.e., wherein the capacitor may be a bulk capacitor with a value of about <NUM> mF) CLOAD load.

Considering the structure illustrated in <FIG>, it is noted that the threshold voltage VTH may be measured if the load <NUM> comprises only a capacitive component CLOAD, for instance, if the load <NUM> is an ECU in a standby mode Sb modeled as a capacitor CLOAD. In such a case, a measurement of the value of the threshold voltage VTH may be done by closing the switch <NUM> and waiting for a charging time CTCLOAD, i.e., until the capacitor CLOAD is charged by the selected test current ITEST.

A drawback is that the capacitive component CLOAD delays for a charging time CCLOAD, i.e., for a time equal to <MAT>, the measurement of the threshold voltage VTH since the test current ITEST, for instance, a current of <NUM> mA, has to flow in the capacitive component CLOAD until the drain-source voltage VDS remains stable to the threshold voltage VTH value.

For instance, if the capacitive load CLOAD is about <NUM> mF, the test current ITEST is about <NUM> mA, and the threshold voltage VTH is about <NUM> V, the charging time CTCLOAD is about <NUM>, which is not negligible.

<FIG> is a time diagram illustrating the behavior of signals in the solution <NUM> of <FIG>.

A current signal IRLOAD indicates the current flowing within the resistive component RLOAD of the load <NUM>.

When the current signal IRLOAD value is zero, for instance, when a corresponding ECU enters in a standby mode Sb, the only remaining component of the load <NUM> is the capacitive component CLOAD, therefore, the threshold voltage VTH may be measured.

In response to the value of the current signal IRLOAD reaching zero, a switch control signal SON/OFF commutes, for instance, from a low logic level to a high logic level, in order to command the closure of the switch <NUM>, and, in response to the closure of such switch <NUM>, the test current ITEST starts flowing in the capacitive component CLOAD of the load <NUM>, charging such capacitive component CLOAD until the voltage VDS remains substantially stable to the threshold voltage VTH value, i.e., after the charging time TCCLOAD.

Solutions that simplify and increase the precision of the monitoring of threshold voltages VTH in transistors, allowing such monitoring even when loads are coupled therewith, would be beneficial in order to have an early prognosis of degradation of devices and to prevent potential failure resulting in uncontrolled conduction.

<FIG> is a block diagram <NUM> of a monitoring circuit MC for measuring the value of a threshold voltage VTH in a Power MOSFET <NUM> which is coupled to an external device <NUM>, i.e., a load <NUM>, according to embodiments of the present description.

It is noted that such monitoring circuit MC may be embedded, for instance, in a power actuator, in an electric fuse, or similar.

The gate driver <NUM> is configured to vary the value of a gate-source voltage VGS, i.e., the voltage between the gate terminal G and the source terminal S, of the Power MOSFET <NUM> in response to the reception of a command CON/OFF from the controller <NUM> (previously described and not shown in <FIG>).

To this purpose, the gate driver <NUM> has a first output terminal that is configured to be coupled to the gate terminal G of the Power MOSFET <NUM>, for instance, through the first switch <NUM>, and a second output terminal that is configured to be coupled to the source terminal S of the Power MOSFET <NUM>.

Therefore, in response to the ON command CON, the gate driver <NUM> is configured to set the value of the gate-source voltage VGS to a first value that is higher than the value of the threshold voltage VTH of the Power MOSFET <NUM> in order to set the state of such Power MOSFET <NUM> to the conductive ON state.

Conversely, in response to the OFF command COFF, the gate driver <NUM> is configured to set the value of the gate-source voltage VGS to a second value that is lower than the value of the threshold voltage VTH, for instance, to zero, in order to set the state of the Power MOSFET <NUM> to the non-conductive OFF state.

The first switch <NUM> is configured to couple the first output terminal of the gate driver <NUM> to the gate terminal G of the Power MOSFET <NUM>, such coupling being enabled in response to the reception of a disconnect gate driver signal DGD from a timing block <NUM>, for instance, a microcontroller, a control logic, or other types of processing units, indicating to couple the gate driver <NUM> to the Power MOSFET <NUM>.

In fact, the first switch <NUM> is further configured to receive a disconnect gate driver signal DGD from the timing block <NUM> and to change its state, i.e., to open or close, in response to such disconnect gate driver signal DGD.

Therefore, if the disconnect gate driver signal DGD indicates to couple the gate driver <NUM> to the Power MOSFET <NUM>, such first switch <NUM> is configured to close.

Conversely, the first switch <NUM> is configured to remain open in response to the disconnect gate driver signal DGD indicating to decouple the gate driver <NUM> from the Power MOSFET <NUM>.

The current source <NUM>, for instance, a current generator, is configured to be coupled to the source terminal S of the Power MOSFET <NUM>, for instance, through the third switch <NUM>, and to generate a test current ITEST flowing through the load <NUM> and/or the source terminal S of the Power MOSFET <NUM>.

The third switch <NUM> is configured to couple such current source <NUM> to the source terminal S of the Power MOSFET <NUM> and to the load <NUM>, such coupling being enabled in response to the reception of a connect load test signal CLTEST from the timing block <NUM> indicating to couple the current source <NUM> to such MOSFET <NUM> and such load <NUM>.

In fact, the third switch <NUM> is further configured to receive a connect load test signal CLTEST from the timing block <NUM> and to change its state, i.e., to open or close, in response to such connect load test signal CLTEST.

Therefore, if the connect load test signal CLTEST indicates to couple the current source <NUM> to the Power MOSFET <NUM> and to the load <NUM>, such third switch <NUM> is configured to close.

Conversely, the third switch <NUM> is configured to remain open in response to the connect load test signal CLTEST indicating to decouple the current source <NUM> from the Power MOSFET <NUM> and the load <NUM>.

The voltage generator <NUM> is configured to supply a test voltage of value VTEST between the gate terminal G and the source terminal S of the Power MOSFET <NUM>, thus, controlling the gate-source voltage VGS value.

To this purpose, such voltage generator <NUM> is configured to be coupled to the second output terminal of the gate driver <NUM>, i.e., to the source terminal S of the Power MOSFET <NUM>, and to the gate terminal G of the Power MOSFET <NUM>, for instance, through the second switch <NUM>.

Such test voltage of value VTEST supplied by the voltage generator <NUM> is a voltage that diverges from a nominal value of the threshold voltage NVTH of a chosen amount VGAP, that can be set according to the application considered and to the safety level that is to be respected.

Therefore, being the value of the test voltage VTEST smaller than the nominal threshold voltage NVTH of a given amount VGAP, when such test voltage VTEST is applied between the gate terminal G and the source terminal S of the Power MOSFET <NUM> the corresponding MOSFET <NUM> is expected to remain in a non-conductive OFF state.

It is noted that if the actual threshold voltage AVTH is shifted from the nominal one NVTH, for instance, because of physical degradations of the gate structure, of an amount equal to or higher than the chosen value VGAP, i.e., so that the actual threshold voltage AVTH is equal to or lower than the voltage VTEST, it may be possible that in response to the application of the test voltage VTEST between the gate terminal G and the source terminal S of the Power MOSFET <NUM>, such MOSFET <NUM> may shift to a conductive ON state, i.e., a current IDS starts flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM>.

In response to the current IDS starting flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM>, a variation of the voltage VLOAD on the load <NUM> may be observed.

Therefore, the load <NUM> may be used as a current sensor to check if a current IDS is flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM>, independently from the circuitry of the load itself and/or from the circuity of a power actuator wherein embodiments of the proposed solutions may be embedded.

It may be noted that, generally, the Power MOSFET <NUM> may contain a current mirror referred to as FET, therefore, such current mirror may be used as the current sensor itself.

Nevertheless, using such current mirror as current sensor may not be reliable since a drift in the threshold voltage VTH may change the current ratio between a current IDS flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM> and a current flowing in such current mirror, making a sensed current obtained using such current mirror internal to such MOSFET <NUM> unreliable.

In various embodiments, the test voltage VTEST and, as a consequence, the chosen value VGAP, may be fixed. In such cases, the monitoring circuit MC of <FIG> is configured to raise an alarm if the actual threshold voltage AVTH reaches the test voltage VTEST (i.e., is equal to or lower than the voltage VTEST). Such a condition may be identified by detecting an unexpected variation of the voltage VLOAD on the load <NUM> in response to the test voltage VTEST being applied to the Power MOSFET <NUM> and causing a switch of such MOSFET <NUM> from a non-conductive OFF state to a conductive ON state, i.e., generating a current IDS that flows between the drain terminal D and the source terminal S.

In various embodiments, the test voltage VTEST and, as a consequence, the chosen value VGAP, may be dynamic. In such cases, the following operations are performed by the monitoring circuit MC of <FIG>:.

Therefore, in embodiments with a dynamic test voltage VTEST the actual threshold voltage AVTH may be measured since such actual threshold voltage AVTH corresponds to the chosen voltage VTEST.

It is noted that such measurement of the actual threshold voltage AVTH may be retrieved if the current flowing in the load <NUM> is compatible with a measurable currents range of the load <NUM>, wherein such measurable currents range depends on a minimum measurable voltage and on the value of the resistive component RLOAD of the load <NUM>.

The second switch <NUM> is configured to couple such voltage generator <NUM> to the gate terminal G of the Power MOSFET <NUM>, such coupling being enabled in response to the reception of a voltage equality signal VEQ from the timing block <NUM> indicating to couple the voltage generator <NUM> to the Power MOSFET <NUM>, in order to set the value of the gate-source voltage VGS to a value substantially equal (i.e., considering a given tolerance range) to the voltage VTEST.

In fact, the second switch <NUM> is further configured to receive a voltage equality signal VEQ from the timing block <NUM> and to change its state, i.e., to open or close, in response to such voltage equality signal VEQ.

Therefore, if the voltage equality signal VEQ indicates to couple the voltage generator <NUM> to the Power MOSFET <NUM>, such second switch <NUM> is configured to close.

Conversely, the second switch <NUM> is configured to remain open in response to the voltage equality signal VEQ indicating to decouple the voltage generator <NUM> from the Power MOSFET <NUM>.

The timing block <NUM> is configured to receive at least a test enable signal TE, indicating if a test of the value of the threshold voltage VTH of the Power MOSFET <NUM> is to be performed using the monitoring circuit MC of <FIG>, and a test mode signal TM, indicating which test mode in a plurality of test mode is to be used for a current test of the value of the threshold voltage VTH of the Power MOSFET <NUM> using such monitoring circuit MC of <FIG>.

For instance, the plurality of test mode may include at least:.

Such first mode may further comprise at least:.

As a function of such test enable signal TE and such test mode signal TM, the timing block <NUM> is further configured to generate a plurality of control signals, such plurality of control signals comprising at least the following signals:.

A sensing block <NUM> is configured to have a sensing terminal coupled to the source terminal S of the Power MOSFET <NUM> and to the load <NUM>, and an output terminal coupled to the first sample and hold block <NUM> and to the second sample and hold block <NUM>.

Such sensing block <NUM> is further configured to:.

The first sample and hold block <NUM> is configured to receive the sensed value of the voltage VLOAD from the sensing block <NUM> and the first load voltage sampling signal SVLOAD,T0 from the timing block <NUM>, and, in response to the reception of such first load voltage sampling signal SVLOAD,T0 indicating to sample the received signal, is further configured to sample the received sensed value of the voltage VLOAD and to hold its value for a given time, for instance, a time longer than a selected time period Td, while providing it to a subtracting block <NUM>.

Similarly, the second sample and hold block <NUM> is configured to receive the sensed value of the voltage VLOAD from the sensing block <NUM> and the second load voltage sampling signal SVLOAD,Td from the timing block <NUM>, and, in response to the reception of such second load voltage sampling signal SVLOAD,Td indicating to sample the received signal, is further configured to sample the received sensed value of the voltage VLOAD and to hold its value for a given time, for instance, a time longer or shorter than the selected time period Td, while providing it to the subtracting block <NUM>.

The subtracting block <NUM> is configured to receive sensed value of the voltage VLOAD from both the first sample and hold block <NUM> and the second sample and hold block <NUM>, to subtract the sensed value received from the second sample and hold block <NUM> from the sensed value received from the first sample and hold block <NUM>, and to provide the result of such subtraction to a first input terminal of a comparator <NUM>.

In various embodiments, the functions that are performed by the sensing block <NUM>, the first sample and hold block <NUM>, the second sample and hold block <NUM>, and the subtracting block <NUM> may be performed by a detection unit <NUM>-<NUM> that is configured to:.

In fact, such functions that are performed by the sensing block <NUM>, the first sample and hold block <NUM>, the second sample and hold block <NUM>, and the subtracting block <NUM> may be performed by different real implementations, for instance, such functions may be implemented without using a first and a second sample and hold blocks <NUM>-<NUM>.

In such a case, the reference voltage generator <NUM> and the comparator <NUM> may be coupled to a ground terminal GND for the first test mode and to the voltage of value VS for the second test mode. Then the voltage variation may be obtained by monitoring the output of the comparator <NUM>, for instance, after a delay Td.

A reference voltage generator <NUM> is configured to supply a second input terminal of the comparator <NUM> with a reference voltage of value VREF.

In various embodiments, such reference voltage value VREF generated by the reference voltage generator <NUM> may be determined according to the current test mode considered, i.e., according to the current value of the test mode signal TM.

The comparator <NUM>, for instance, implemented through an operational amplifier, is configured to receive at its first input terminal the result of the subtraction from the subtracting block <NUM> or the voltage variation provided by the detection unit <NUM>-<NUM> and at its second input terminal the reference voltage VREF from the reference voltage generator <NUM>.

Such comparator <NUM> is further configured to compare the voltage values received at its first and second input terminals, and, if the result of such comparison is unsuccessful, the comparator <NUM> is configured to raise an alarm signal ALVTH, indicating that the corresponding circuit may be at risk of short circuit failures.

In particular, the result of such comparison may be considered as unsuccessful if the output of the comparison does not correspond to a predetermined output condition, such predetermined output condition may depend on the current test mode considered, for instance:.

In various embodiments, the reference voltage generator <NUM> and the comparator <NUM> may be comprised in the alarm generation unit <NUM>-<NUM> that is configured to:.

To summarize, the circuit MC for monitoring an actual threshold voltage value AVTH of a MOSFET <NUM>, i.e., the current value of the threshold voltage VTH of the MOSFET <NUM>, comprises:.

wherein said control unit <NUM> is further configured to, according to said received test mode signal TM, select the status of coupling or decoupling of said current source <NUM> to/from the source terminal S of the MOSFET <NUM>,.

<FIG> is a time diagram illustrating the behavior of signals in the monitoring circuit MC of <FIG> according to embodiments of the present description.

In particular, <FIG> illustrates the behavior of signals received by or generated from the timing block <NUM>.

In response to the reception of the test enable signal TE indicating, for instance, by switching from a low logic level to a high logic level, to perform a test of the value of the threshold voltage VTH of the Power MOSFET <NUM> using the monitoring circuit MC of <FIG>, the timing block <NUM> is configured to indicate, for instance, by sending a pulse on the first load voltage sampling signal SVLOAD,T0 or by switching it to a high logic level, to the first sample and hold block <NUM> to sample the sensed value of the voltage VLOAD before any changes in the operation of the circuit.

In response to the first sample and hold block <NUM> sampling the sensed value of the voltage VLOAD, the timing block <NUM> is configured to modify the operation of the monitoring circuit MC of <FIG> indicating, for instance, by setting the voltage equality signal VEQ to a high logic level, to couple the voltage generator <NUM> to the gate terminal G of the Power MOSFET <NUM>, setting the value of the gate-source voltage VGS to a value substantially equal to the voltage VTEST.

Then, after a given time equal to Td, the timing block <NUM> is further configured to indicate, for instance, by sending a pulse on the second load voltage sampling signal SVLOAD,Td or by switching it to a high logic level, to the second sample and hold block <NUM> to sample the sensed value of the voltage VLOAD that may have been changed after the setting of the gate-source voltage VGS to the voltage VTEST, thus, the voltage VLOAD is sampled after changes in the operation of the circuit.

In this way, the subtracting block <NUM> may subtract the sensed voltage VLOAD received from the second sample and hold block <NUM>, i.e., the sensed voltage VLOAD after the setting of the gate-source voltage VGS to the voltage VTEST, from the sensed voltage VLOAD received from the first sample and hold block <NUM>, i.e., before any changes in the operation of the circuit.

The available test modes in the plurality of test modes are chosen in order to avoid interferences with the operations of a coupled load <NUM>, for instance, an ECU.

To this purpose, the monitoring circuit MC may advantageously be activated, for instance, by setting the test enable signal TE to a high logic level, only in specific working conditions, for instance, when the coupled load <NUM> is in an OFF state or in a standby mode, in particular:.

Therefore, in various embodiments, the monitoring circuit MC may be activated when the coupled load <NUM> is in an OFF state, i.e., there is no current flowing within such load <NUM>, for instance, a case when a power actuator directly activates a load that is resistive and/or capacitive.

In such cases, when the coupled load <NUM> is in an OFF state, the voltage VLOAD on the load <NUM> is a very low voltage, for instance, a voltage close to zero, thus, the corresponding gate-source voltage VGS of the Power MOSFET <NUM> is substantially equal to zero.

<FIG> is a time diagram illustrating the behavior of signals in the monitoring circuit MC of <FIG> when the coupled external device <NUM>, i.e., the coupled load <NUM>, is in an OFF state and may be modeled as a resistive RLOAD load according to embodiments of the present description.

As illustrated in <FIG>, the connect load test signal CLTEST supplied by the timing block <NUM> to the third switch <NUM> is set, for instance, to a low logic level, indicating to such third switch <NUM> to open in order to decouple the current source <NUM> from the source terminal S of the Power MOSFET <NUM>. Therefore, the test current ITEST is not flowing within the load <NUM>.

In such a condition, if a test is enabled, for instance, by setting the test enable signal TE to a high logic level, the timing block <NUM> is configured to indicate, for instance, by sending a pulse on the first load voltage sampling signal SVLOAD,T0 or by switching it to a high logic level, to the first sample and hold block <NUM> to sample the sensed value of the voltage VLOAD before any changes in the operation of the monitoring circuit MC, i.e., when the gate-source voltage VGS of the Power MOSFET <NUM> is substantially equal to zero and the load is in a non-conductive OFF state.

As previously described, in response to the first sample and hold block <NUM> sampling the sensed value of the voltage VLOAD, the timing block <NUM> is configured to indicate, for instance, by setting the voltage equality signal VEQ to a high logic level, to the second switch <NUM> that the voltage generator <NUM> is to be coupled to the gate terminal G of the Power MOSFET <NUM>, to modify the value of the gate-source voltage VGS, setting its value to a value substantially equal to the voltage VTEST.

It is noted that, in various embodiments, for instance, in the embodiment of <FIG>, the voltage equality signal VEQ may be set to a voltage level equal to the test voltage VTEST supplied by the voltage generator <NUM> in order to indicate to the second switch <NUM> to couple the voltage generator <NUM> to the Power MOSFET <NUM>.

Therefore, when the second switch <NUM> couples the voltage generator <NUM> with the gate terminal G of the Power MOSFET <NUM>, such voltage generator <NUM> supplies the test voltage VTEST between the gate terminal G and the source terminal S of the Power MOSFET <NUM>, thus, modifying the value of the gate-source voltage VGS.

If the actual threshold voltage AVTH is higher than the test voltage VTEST supplied by the voltage generator <NUM>, the Power MOSFET <NUM> remains in a non-conductive OFF state, thus, there is no current ILOAD flowing within the load <NUM> and the voltage VLOAD on the load <NUM> remains of the same value that has been previously sampled by the first sample and hold block <NUM>.

In such a case, the sensed value of the voltage VLOAD sampled by the second sample and hold block <NUM> will be substantially equal to the one sampled by the first sample and hold block <NUM>. Thus, the result of the subtraction from the subtracting block <NUM> or the voltage variation provided by the detection unit <NUM>-<NUM> will result in a value that is substantially equal to zero.

Conversely, as previously described, if the actual threshold voltage AVTH is shifted from the nominal threshold voltage NVTH, for instance, because of physical degradations of the gate structure, so that the actual threshold voltage AVTH is equal to or lower than the test voltage VTEST supplied by the voltage generator <NUM> (as shown in <FIG>), the Power MOSFET <NUM> may change its state from a non-conductive OFF state to a conductive ON state, since the voltage applied between its gate terminal G and its source terminal S, i.e., the test voltage VTEST, is higher than the actual threshold voltage AVTH value.

In response to the Power MOSFET <NUM> changing its state to a conductive ON state, a current IDS starts flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM> and, as a consequence, within the load <NUM>, i.e., a resistive load.

Thus, as illustrated in <FIG>, a variation of both the voltage VLOAD on the load <NUM> and of the current ILOAD within the load <NUM> are observed, in particular, the value of such current ILOAD may be obtained using the following formula: <MAT> wherein GM is the transconductance of the Power MOSFET, and the value of such voltage VLOAD on the load <NUM> may be obtained using the formula: <MAT>.

Therefore, the resistive load <NUM>, which is composed only of a resistive component RLOAD, may be used as a current sensor to check if the Power MOSFET <NUM> has changed its state from a non-conductive OFF state to a conductive ON state.

Independently from the value of the actual threshold voltage AVTH, after a given time equal to Td, the timing block <NUM> is further configured to indicate, for instance, by sending a pulse on the second load voltage sampling signal SVLOAD,Td or by switching it to a high logic level, to the second sample and hold block <NUM> to sample the sensed value of the voltage VLOAD.

After such time Td from the setting of the gate-source voltage VGS to the voltage VTEST, the Power MOSFET <NUM> may have changed its state from a non-conductive OFF state to a conductive ON state and a variation of both the voltage VLOAD on the load <NUM> and of the current ILOAD within the load <NUM> may have been observed.

In particular, if the actual threshold voltage AVTH is higher than the test voltage VTEST supplied by the voltage generator <NUM>, the sensed value of the voltage VLOAD sampled by the second sample and hold block <NUM> is substantially equal to the one sampled by the first sample and hold block <NUM>.

Conversely, if the actual threshold voltage AVTH is equal to or lower than the test voltage VTEST supplied by the voltage generator <NUM>, the sensed value of the voltage VLOAD sampled by the second sample and hold block <NUM> is different from, i.e., higher than, the one sampled by the first sample and hold block <NUM> and equal to VLOAD = ILOAD * RLOAD.

Thus, the subtracting block <NUM> may subtract the sensed voltage VLOAD received from the second sample and hold block <NUM>, i.e., the voltage VLOAD sensed after such time Td from the setting of the gate-source voltage VGS to the voltage VTEST ,i.e., when such load <NUM> may have changed its state to a conductive state, from the sensed voltage VLOAD received from the first sample and hold block <NUM>, i.e., the voltage VLOAD sensed before any modification in the operation of the monitoring circuit MC, i.e., with such load <NUM> in a non-conductive off state, obtaining a value indicative of the voltage variation on the load <NUM> during such period of time Td.

If the actual threshold voltage AVTH is equal to or lower than the test voltage VTEST supplied by the voltage generator <NUM>, such value indicative of the voltage variation on the load <NUM> indicates a voltage variation between a conductive state of such load <NUM> and a non-conductive off state of such load <NUM>.

It is noted that such value indicative of the voltage variation on the load <NUM> may indicate if a current ILOAD was flowing within the load <NUM> during the time period Td.

In fact, if the value of the voltage variation is substantially zero, the voltage VLOAD on the load <NUM> remains substantially stable during the whole time period Td, therefore, the actual threshold voltage AVTH is higher than the test voltage VTEST and a current ILOAD did not flow within such load <NUM> during such time Td.

Conversely, if the value of the voltage variation is different from zero, the voltage VLOAD on the load <NUM> varies during the time period Td, therefore, the actual threshold voltage AVTH is equal to or lower than the test voltage VTEST and a current ILOAD flowed within such load <NUM> during such time Td.

If the reference voltage generator <NUM> is correctly configured to supply a reference voltage VREF (as illustrated in <FIG>) whose value is:.

the comparator <NUM> may raise an alarm signal ALVTH, indicating that the Power MOSFET <NUM> and the corresponding device, for instance, an E-Fuse, may be at risk of short circuit failures if the value of an obtained voltage variation is higher than such correctly defined reference voltage VREF.

In various embodiments, if the first mode or the second mode are selected, the reference voltage VREF may be a voltage referred to a ground terminal GND since the Power MOSFET is initially in a non-conductive OFF state. In such case, for instance, the reference voltage VREF may be illustrated, as in <FIG> and <FIG>, with a double arrow between a first level indicating a corresponding ground voltage, i.e., with a value that is substantially zero, and a second level indicating a voltage value that satisfy the two conditions described above for configuring correctly the reference voltage generator.

A criterion for dimensioning such time Td is described in the following.

<FIG> is a time diagram illustrating the behavior of signals in the monitoring circuit MC of <FIG> when the coupled external device <NUM> is in an OFF state and may be modeled as a capacitive/resistive load according to embodiments of the present description.

Most of the signals illustrated in <FIG> behave as the corresponding ones, i.e., the ones denoted by the same references, represented and already described in <FIG>. For this reason, a description of the behavior and timing of such signals is not repeated in the following in order not to overburden the present detailed description.

Differences between the behavior of signals in <FIG> with the behavior of signals in <FIG> are obtained by the addition of a capacitive component in the load <NUM>.

If the actual threshold voltage AVTH is higher than the test voltage VTEST supplied by the voltage generator <NUM>, the behavior of the signals obtained using the test mode illustrated in <FIG> is equal to that obtained using the test mode illustrated in <FIG>, therefore, a detailed description for such a case is not described again in the following to not overburden the present description.

Even in embodiments as shown in <FIG>, if the actual threshold voltage AVTH is shifted from the nominal threshold voltage NVTH until it reaches a value that is equal to or lower than the test voltage VTEST supplied by the voltage generator <NUM>, the Power MOSFET <NUM> changes its state from a non-conductive OFF state to a conductive ON state, with a consequent variation of both the voltage VLOAD on the load <NUM> and of the current ILOAD within the load <NUM>.

In response to the addition of such capacitive component CLOAD in the load <NUM>, the voltage VLOAD on the load <NUM> slowly variates its value as the capacitive component CLOAD of the load <NUM> is charged (illustrated in <FIG>).

In particular, the value of such current ILOAD may be obtained using again the formula: <MAT> while the value of such voltage VLOAD on the load <NUM> may be obtained using the formula: -t <MAT>.

Therefore, even in embodiments using the test mode illustrated in <FIG>, the load <NUM> may be used as a current sensor to check if the Power MOSFET <NUM> has changed its state from a non-conductive OFF state to a conductive ON state, on condition that the time Td used as a delay between the first sampling and the second sampling of the sensed voltage VLOAD is dimensioned in order to allow a complete charging of the capacitive component CLOAD of the load <NUM> before the second sampling operation.

Hence, in various embodiments wherein the load <NUM> may include a capacitive component CLOAD, the time Td used as a delay between the first sampling and the second sampling of the sensed voltage VLOAD is dimensioned in order to allow the current ILOAD flowing within such coupled load <NUM> to charge such capacitive component CLOAD.

In various embodiments wherein the load <NUM> is not configured to include a capacitive component CLOAD but only a resistive component RLOAD , even if a time Td used as a delay between the first sampling and the second sampling of the sensed voltage VLOAD is still required, such time Td may be much shorter than that of embodiments wherein the load <NUM> may include a capacitive component CLOAD , as the voltage VLOAD on a load <NUM> comprising only a resistive component RLOAD varies much faster than on a load <NUM> comprising also a capacitive component CLOAD.

In various embodiments, the monitoring circuit MC may be activated when the load <NUM> is in a standby mode, i.e., when there is a supply voltage VFUSE provided to the load <NUM> but there is no current flowing within such load <NUM>, for instance, a case when an electronic fuse guarantees a supply voltage VFUSE to the load <NUM> while such load <NUM> is in a standby mode and no current is flowing through it.

Usually, in automotive applications, the load <NUM> may include a bulk capacitor placed in parallel with an automotive load and a corresponding quiescent current, i.e., a current flowing within an integrated circuit when such circuit is in a quiescent state, for example, in a standby mode, has a very low value such that the load <NUM> may be modeled with a pure capacitive load, neglecting the resistive component.

Therefore, the embodiments of <FIG> and <FIG> are described considering a pure capacitive load, i.e., a load <NUM> containing only a capacitive component CLOAD.

In embodiments wherein the load <NUM> may be modeled as a pure capacitive load, the Power MOSFET <NUM>, or a corresponding device, for instance, an E-Fuse, can be turned off for a short time, i.e., for a time equal to a delay Td, and during such short time a low test current ITEST can be sink from such load <NUM>, for instance, by using a dummy load as the current generator <NUM>. If such test current ITEST is sufficiently low, the capacitive component, for instance, a bulk capacitance, discharging is low enough to avoid an undervoltage condition on such load <NUM>.

<FIG> and <FIG> are time diagrams illustrating the behavior of signals in the monitoring circuit MC of <FIG> when the coupled external device <NUM>, modeled as a pure capacitive load, is in an ON state and in a standby mode according to embodiments of the present description.

In particular, <FIG> illustrates the behavior of signals in the monitoring circuit MC of <FIG> when coupled to an external device <NUM>, modeled as a pure capacitive load, that is in an ON state and in a standby mode, and the actual value of the threshold voltage AVTH is smaller than or equal to the test voltage VTEST, and, as a consequence, of the nominal value of the threshold voltage NVTH.

As shown in <FIG>, if a test is enabled, for instance, by setting the test enable signal TE to a high logic level, the timing block <NUM> is configured to indicate, for instance, by sending a pulse on the first load voltage sampling signal SVLOAD,T0 or by switching it to a high logic level, to the first sample and hold block <NUM> to sample the sensed value of the voltage VLOAD before any changes in the operation of the circuit, i.e., when the gate-source voltage VGS of the Power MOSFET <NUM> is substantially equal to zero and the load <NUM> is in a standby mode, i.e., there is a supply voltage VFUSE provided to the load <NUM> but there is no current flowing within such load <NUM>.

In response to the first sample and hold block <NUM> sampling the sensed value of the voltage VLOAD, the connect load test signal CLTEST supplied by the timing block <NUM> to the third switch <NUM> is switched, for instance, from a low logic level to a high logic level, indicating to such third switch <NUM> to close in order to couple the current source <NUM> to the source terminal S of the Power MOSFET <NUM>. In this way, the test current ITEST start flowing within the load <NUM>, discharging the capacitive component of such load <NUM>.

In addition, again in in response to the first sample and hold block <NUM> sampling the sensed value of the voltage VLOAD, the timing block <NUM> is configured to indicate, for instance, by setting the voltage equality signal VEQ to a high logic level, to the second switch <NUM> that the voltage generator <NUM> is to be coupled to the gate terminal G of the Power MOSFET <NUM>, to modify the value of the gate-source voltage VGS, setting its value to a value substantially equal to the voltage VTEST.

Even in embodiments as the one shown in <FIG>, it is noted that, for instance, the voltage equality signal VEQ may be set to a voltage level equal to the test voltage VTEST supplied by the voltage generator <NUM> in order to indicate to the second switch <NUM> to couple the voltage generator <NUM> to the Power MOSFET <NUM>.

As illustrated in <FIG>, if the actual threshold voltage AVTH is shifted from the nominal threshold voltage NVTH of an amount so that the actual threshold voltage AVTH is equal to or lower than the test voltage VTEST supplied by the voltage generator <NUM>, the Power MOSFET <NUM> changes its state from a non-conductive OFF state to a conductive ON state, as the voltage applied between its gate terminal G and its source terminal S, i.e., the test voltage VTEST, is higher than the actual threshold voltage AVTH value.

In response to the Power MOSFET <NUM> changing its state from a non-conductive OFF state to a conductive ON state, a current IDS starts flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM>, such current IDS substantially corresponding to the test current ITEST generated by the current source <NUM>.

Since the test current ITEST generated by the current source <NUM> flows mainly within the Power MOSFET <NUM>, the voltage VLOAD on the corresponding load <NUM> may change of an amount that is smaller than a given threshold, for instance, smaller than a value selected for the reference voltage VREF generated by the reference voltage generator <NUM>.

Therefore, such reference voltage VREF generated by the reference voltage generator <NUM> may be considered as a threshold and used to check if the Power MOSFET <NUM> has changed its state from a non-conductive OFF state to a conductive ON state.

In fact, if the voltage VLOAD on the load <NUM> changes of an amount that is smaller than the value of such threshold, i.e., of such reference voltage VREF, the corresponding Power MOSFET <NUM> is characterized by an actual threshold voltage AVTH value that is smaller than the test voltage VTEST supplied by the voltage generator <NUM>, i.e., is smaller than a selected minimum value and may be at risk of short circuit failures.

Then, after a given time equal to Td, the timing block <NUM> is further configured to indicate, for instance, by sending a pulse on the second load voltage sampling signal SVLOAD,Td or by switching it to a high logic level, to the second sample and hold block <NUM> to sample the sensed value of the voltage VLOAD after the setting of the gate-source voltage VGS to the voltage VTEST, thus, when the Power MOSFET <NUM> has changed its state from a non-conductive OFF state to a conductive ON state and the test current ITEST generated by the current source <NUM> is flowing within such MOSFET <NUM>.

In this way, the subtracting block <NUM> may subtract the sensed the voltage VLOAD received from the second sample and hold block <NUM>, i.e., the voltage VLOAD sensed after the Power MOSFET <NUM> changes its state from a non-conductive OFF state to a conductive ON state, from the sensed the voltage VLOAD received from the first sample and hold block <NUM>, i.e., the voltage VLOAD sensed before any change in the operations of the monitoring circuit MC of <FIG>, obtaining a value indicative of the voltage variation on the load <NUM> during the time Td.

Such value indicative of the voltage variation on the load <NUM> during the time Td may indicate if a current ILOAD equal to the test current ITEST was flowing within the load <NUM> during the time Td.

In fact, if the value of the voltage variation is smaller than the selected threshold, i.e., the reference voltage VREF, the voltage VLOAD on the load <NUM> decreased by an amount that is smaller than such selected threshold during the time Td, thus, a current ILOAD of value equal to the test current ITEST flows within the Power MOSFET <NUM> and not within such load <NUM> during such time Td.

Conversely, <FIG> illustrates the behavior of signals in the monitoring circuit MC of <FIG> when coupled to an external device <NUM>, modeled as a pure capacitive load , that is in an ON state and in a standby mode, and wherein the actual value of the threshold voltage AVTH is comprised in a range between the test voltage VTEST and the nominal value of the threshold voltage NVTH (for instance, without losing generality for the following description, in <FIG> the actual value of the threshold voltage AVTH is considered equal to the nominal value of the threshold voltage NVTH).

It is noted that a description for signals of <FIG> that behave as the corresponding ones, i.e., the ones denoted by the same references, represented and already described in <FIG> is not repeated in the following in order not to overburden the present detailed description.

In such a condition, the Power MOSFET <NUM> do not change its state into a conductive ON state in response to the connect load test signal CLTEST indicating to close the third switch <NUM>, coupling the current source <NUM> to the source terminal S of the Power MOSFET <NUM>, and the voltage equality signal VEQ indicating to close the second switch <NUM>, coupling the voltage generator <NUM> to the gate terminal G of the Power MOSFET <NUM>.

Even in this case, the gate-source voltage VGS of the Power MOSFET <NUM> is set to the test voltage VTEST but since the actual threshold voltage AVTH is higher than such test voltage VTEST the Power MOSFET <NUM> remains in a non-conductive OFF state.

Thus, a current IDS is not flowing between the drain terminal D and the source terminal S of the Power MOSFET <NUM> and the test current ITEST generated by the current source <NUM> discharge the capacitive component of the load <NUM>, lowering the value of the voltage VLOAD on the load <NUM>.

In response to the discharging of the capacitive component of the load <NUM> by the test current ITEST, the voltage VLOAD on the load <NUM> decrease over time of an amount that is higher than a given threshold, for instance, higher than the selected value for the reference voltage VREF generated by the reference voltage generator <NUM>.

Therefore, if the voltage VLOAD on the load <NUM> changes of an amount that is higher than such threshold, i.e., than such reference voltage VREF, the corresponding Power MOSFET <NUM> is characterized by an actual threshold voltage AVTH value that is higher than the test voltage VTEST supplied by the voltage generator <NUM>, i.e., is higher than the selected minimum value and is not at risk of short circuit failures.

In embodiments as illustrated in <FIG>, the value of the voltage variation provided by the subtracting block <NUM> is higher than the selected threshold, i.e., the reference voltage VREF, as the voltage VLOAD on the load <NUM> decreased of an amount that is higher than such selected threshold during the time Td, thus, a current ILOAD of value equal to the test current ITEST flowed within such load <NUM> during such time Td, discharging the capacitive component of such load <NUM>.

Therefore, if the reference voltage generator <NUM> is correctly configured to supply a reference voltage VREF (as illustrated in <FIG>) whose value is:.

the comparator <NUM> may raise an alarm signal ALVTH, indicating that the Power MOSFET <NUM> and the corresponding device, for instance, an E-Fuse, may be at risk of short circuit failures if the value of an obtained voltage variation is smaller than such correctly defined reference voltage VREF (as illustrated in <FIG>).

Otherwise, if the comparator <NUM> detects that the value of an obtained voltage variation is higher than such correctly defined reference voltage VREF, the alarm signal ALVTH is not set, for instance, remaining to a low logic level (as illustrated in <FIG>).

In various embodiments, if the third mode is selected, the reference voltage VREF may be a voltage referred to the voltage VS since the Power MOSFET is initially in a conductive ON state. In such case, for instance, the reference voltage VREF may be illustrated, as in <FIG> and <FIG>, with a double arrow between a first level indicating such voltage VS and a second level indicating a voltage value that satisfy the two conditions described above for configuring correctly the reference voltage generator.

In the embodiments illustrated in <FIG> and <FIG>, to correctly set the value of the reference voltage VREF generated by the reference voltage generator <NUM> the following equation may be considered: <MAT> wherein <MAT> is the voltage variation over the time period Td provided by the subtracting block <NUM> or the detection unit <NUM>-<NUM>.

In various embodiments wherein the load <NUM> may be modeled as a pure capacitive component, as in embodiments of <FIG> and <FIG>, the time Td used as a delay between the first sampling and the second sampling of the sensed voltage VLOAD may be shorter than that of embodiments wherein the load <NUM> may include both a resistive component and a capacitive component, as in embodiments of <FIG>.

In fact, in embodiments of <FIG> and <FIG> the voltage variation measured on the load <NUM> that may allow detecting an anomaly is much smaller than the one in embodiments of <FIG>, as the capacitive component is to be partially, and not fully, discharged/charged, thus, needing for a shorter time period Td.

<FIG> is a system <NUM> comprising the monitoring circuit MC of <FIG> and a temperature variation monitoring unit <NUM>-<NUM> according to embodiments of the present description.

The threshold voltage VTH of a Power MOSFET <NUM> decreases in response to increasing temperatures. Therefore, in various embodiments, the test voltage VTEST supplied by the voltage generator <NUM> is to be compensated for the temperature effects, i.e., in order to maintain a same chosen gap amount VGAP between such test voltage VTEST and the nominal value of the threshold voltage NVTH which changes with temperature values.

The compensation of the drift of the threshold voltage VTH resulting from a temperature variation is done by using a thermal sensor <NUM> that is configured to monitor the temperature of the Power MOSFET <NUM> junction (dashed arrow), and to send the sensed temperature values to a compensation block <NUM>.

Such compensation block <NUM> is configured to receive the sensed temperature values from the thermal sensor <NUM> and to compute as a function of such sensed temperature values a corresponding value for the test voltage VTEST that is to be generated by the voltage generator <NUM> of a monitoring circuit <NUM>, corresponding to the monitoring circuit MC of <FIG>.

In this way, the computed value for the test voltage VTEST may be updated dynamically according to the temperature changes of the Power MOSFET <NUM> in order to keep a gap of constant value VGAP between the nominal threshold voltage NVTH and the test voltage VTEST.

Such compensation block <NUM> is further configured to provide such computed value for the test voltage VTEST to the monitoring circuit <NUM>, in particular, to the voltage generator <NUM>.

The monitoring circuit <NUM>, corresponding to the monitoring circuit MC of <FIG>, and, in particular, the voltage generator <NUM> is configured to generate a voltage of a value equal to the computed value for the test voltage VTEST received from the compensation block <NUM>.

In various embodiments, the monitoring circuit <NUM> may further receive current feedback and/or voltage feedback through an ammeter <NUM> and a voltmeter <NUM> respectively.

In various embodiments, the monitoring circuit <NUM> may be coupled to a communication interface <NUM>, for instance, to receive the test enable signal TE and the test mode signal TM from an external unit.

In various embodiments, the thermal sensor <NUM> and the compensation block <NUM> may be integrated within the same unit, for instance, within a smart power actuator that comprises a thermal sensor integrated inside the structure of the Power MOSFET.

In various embodiments, the system <NUM> may be used for automotive applications, for instance, by coupling an upper pin <NUM> to an automotive power distribution source, for instance, a battery, and a lower pin <NUM> to a vehicle utility system or to an ECU.

In various embodiments, the system <NUM> may be used for automotive applications in contexts of vehicle diagnostic and monitoring systems, multiple and backup power systems, redundant braking systems, redundant electrical power steering system, and/or the like.

In various embodiments, the monitoring circuit MC of <FIG> may be embedded inside a power actuator or an E-Fuse.

Solutions as described herein facilitate obtaining monitoring circuits for an early detection of short circuit failures in MOSFETs. This may be achieved by measuring the actual threshold voltage value of a given MOSFET while such MOSFET is coupled with a corresponding load.

Thus, solutions as described herein facilitate achieving the health monitoring of devices, for instance, E-Fuses, through the monitoring of corresponding MOSFETs so as to prevent short circuit failures in such MOSFETs. In this way, it may be possible to have an early prognosis on the degradation of both such MOSFETs and corresponding devices and to prevent potential failures resulting in uncontrolled conduction.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the scope of the embodiments.

Claim 1:
Circuit (MC) for monitoring an actual threshold voltage value of a MOSFET (<NUM>) comprising:
- a current source (<NUM>), configured to be coupled to a source terminal (S) of the MOSFET (<NUM>) and to generate a test current (ITEST),
- a voltage generator (<NUM>), configured to be coupled between a gate terminal (G) of the MOSFET (<NUM>) and the source terminal (S) of the MOSFET (<NUM>), and to generate a test voltage (VTEST), said test voltage (VTEST) being lower than a nominal threshold voltage value (NVTH) of the MOSFET (<NUM>),
- a detection unit (<NUM>-<NUM>), configured to sample a plurality of voltage value (VLOAD) at the source terminal (S) of the MOSFET (<NUM>) during time, to compute as a function of said plurality of voltage value (VLOAD) at least a value of voltage variation over time, in particular over a given time period (Td), of said voltage value (VLOAD) at the source terminal (S) of the MOSFET (<NUM>), and to provide said computed at least a value of voltage variation to an alarm generation unit (<NUM>-<NUM>),
- the alarm generation unit (<NUM>-<NUM>) being configured to receive said computed voltage variation from the detection unit (<NUM>-<NUM>), to compare said computed voltage variation with a reference voltage (VREF), and to raise an alarm (ALVTH) if the output of said comparison does not correspond to a predetermined output condition, and
- a control unit (<NUM>), configured to receive a test mode signal (TM), indicative of an operation mode,
wherein said control unit (<NUM>) is further configured to, according to said received test mode signal (TM), select the status of coupling or decoupling of said current source (<NUM>) to/from the source terminal (S) of the MOSFET (<NUM>),
- determine the value of said reference voltage (VREF),
- set said output condition of said comparison, and
- signal to the detection unit (<NUM>-<NUM>) to perform a plurality of said sampling operation.