Patent Description:
In a conventional electric-power-steering motor control apparatus, a motor control circuit of a motor control unit transmits a control signal to a motor driving unit; in according with the control signal, the motor control unit supplies a motor with a current. In this case, there is provided an interlock circuit for cutting off the connection between the motor control circuit and the motor driving unit in the case where an abnormal state in each of the motor driving unit and the motor control circuit is monitored and any abnormality is detected. The motor control unit includes the motor control circuit and the interlock circuit. The motor control apparatus includes the motor control unit and the motor driving unit. The interlock circuit is provided independently from the motor control circuit. The motor control circuit receives a signal from the interlock circuit and then cuts off the connection between the motor control circuit and the motor driving unit (e.g., refer to <CIT>).

Relevant motor control devices are also known from <CIT>, <CIT> and <CIT>.

In a conventional motor control apparatus, there is provided an interlock circuit for cutting off the connection between the motor control circuit and the motor driving unit in the case where an abnormal state in each of the motor driving unit and the motor control circuit is monitored and any abnormality is determined. There has been a problem that because in order to provide such an interlock circuit independently from the motor control circuit, a monitoring circuit and a cutoff circuit are provided, the respective circuits of the motor control unit and the motor driving unit become complicated and large-scaled, which results in upsizing of the motor control apparatus and increase in the weight and the cost thereof.

The objective of a technology according to the present disclosure is to obtain a motor control apparatus that requires no complicated and large-scaled circuit, that determines whether or not any one of the motor driving unit and the motor control circuit is abnormal, based on the output of the motor control unit, and that can cut off the connection between the motor control circuit and the motor driving unit, when an abnormality is determined.

In addition, the objective thereof is to obtain an electric power steering apparatus that requires no complicated and large-scaled circuit, that determines whether or not any one of the motor driving unit and the motor control circuit is abnormal, and that can cut off the motor driving unit, when an abnormality is determined.

The subject-matter of claim <NUM> solves the technical problem. The dependent claims describe further preferred embodiments, and this description discloses how the present invention may be carried out.

Neither a motor control apparatus nor an electric power steering apparatus according to the present disclosure requires a large-scaled circuit such as an interlock circuit and can determine an abnormality from an output of a motor control unit and can cut off the connection between the motor control unit and a motor driving unit, when an abnormality is determined. As a result, it is made possible to obtain an apparatus having an effective cutoff circuit, while suppressing the motor control apparatus from being upsized, increasing its weight, and increasing its cost.

Hereinafter, a motor control apparatus and an electric power steering apparatus according to the present disclosure will be explained with reference to the drawings.

Hereinafter, a motor control apparatus <NUM> according to Embodiment <NUM> will be explained with reference to the drawings. <FIG> is a configuration diagram of the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a hardware configuration diagram of the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of main processing by a cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of initialization processing by the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of short-circuit determination processing and wrong-output determination processing by the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of excess-current determination processing by the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of cutoff processing by the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a configuration diagram of a motor control apparatus <NUM> according to a conventional example.

The motor control apparatus <NUM> according to a conventional example includes a motor driving unit <NUM> and a motor control unit <NUM> having a computing processing unit <NUM>, a motor control circuit <NUM>, and an interlock circuit <NUM>. An input signal from the outside is inputted to the computing processing unit <NUM> (unillustrated). Based on the input signal, the computing processing unit <NUM> calculates a current to be supplied to a motor <NUM>, outputs a command to a motor control circuit <NUM>, and then outputs a control signal to the motor driving unit <NUM> by way of the motor control circuit <NUM>. In accordance with the control signal received from the motor control circuit <NUM>, the motor driving unit <NUM> supplied a current to the motor <NUM> through motor connection terminals <NUM> and <NUM>.

The motor driving unit <NUM> in <FIG> incorporates positive-polarity field-effect transistors <NUM> and <NUM> (hereinafter, referred to as positive-polarity FETs <NUM> and <NUM>) and negative-polarity FETs <NUM> and <NUM>. The positive-polarity FET <NUM> and the negative-polarity FET <NUM> are connected in series with each other between a positive-polarity power source and a negative-polarity power source; the connection point is connected with the motor connection terminal <NUM>. The positive-polarity FET <NUM> and the negative-polarity FET <NUM> are connected in series with each other between the positive-polarity power source and the negative-polarity power source; the connection point is connected with the motor connection terminal <NUM>. The motor connection terminals <NUM> and <NUM> are connected with the motor <NUM>. The motor driving unit <NUM> is connected with the positive-polarity power source and the negative-polarity power source; however, the negative-polarity power source is connected with the motor driving unit <NUM> through a resistor of a current detection circuit.

When supplying a current so as to drive the motor <NUM>, the motor driving unit <NUM> turns on the positive-polarity FET <NUM>, turns off the negative-polarity FET <NUM>, turns off the positive-polarity FET <NUM>, and turns on the negative-polarity FET <NUM> so as to pour the current into the motor <NUM> through the motor connection terminal <NUM> and to suck the current out of the motor through the motor connection terminal <NUM>. Alternatively, the motor driving unit <NUM> turns off the positive-polarity FET <NUM>, turns on the negative-polarity FET <NUM>, turns on the positive-polarity FET <NUM>, and turns off the negative-polarity FET <NUM> so as to pour the current into the motor <NUM> through the motor connection terminal <NUM> and to suck the current out of the motor through the motor connection terminal <NUM>. Accordingly, there exists neither the case where both the positive-polarity FET <NUM> and the positive-polarity FET <NUM> are regularly and concurrently turned on nor the case where both the negative-polarity FET <NUM> and the negative-polarity FET <NUM> are regularly and concurrently turned on. It can be determined that such an output is wrong and abnormal.

In parallel with the motor control circuit <NUM>, the interlock circuit <NUM> receives the contents of a command that is issued to the motor control circuit <NUM> by the computing processing unit <NUM>. In the case where the contents of the command are wrong, the interlock circuit <NUM> determines an abnormality and then outputs a cutoff signal to the motor control circuit <NUM>. For example, in the case where the computing processing unit <NUM> outputs a command for concurrently turning on the positive-polarity FET <NUM> and the positive-polarity FET <NUM> of the motor driving unit <NUM> or in the case where the computing processing unit <NUM> outputs a command for concurrently turning on the negative-polarity FET <NUM> and the negative-polarity FET <NUM> of the motor driving unit <NUM>, the interlock circuit <NUM> determines that the command of the computing processing unit <NUM> is wrong. In this case, the interlock circuit <NUM> outputs the cutoff signal to the motor control circuit <NUM> so as to disconnect the motor control unit <NUM> from the motor driving unit <NUM>.

In addition, even when the computing processing unit <NUM> outputs a correct signal for driving the motor <NUM>, the interlock circuit <NUM> determines whether or not the current flowing in the motor driving unit <NUM> corresponds to an excessive current, based on an output voltage of a current detection circuit <NUM>. In the case where the output voltage of the current detection circuit <NUM> exceeds an excessive-current determination voltage, the interlock circuit <NUM> determines that an excessive current is flowing in the motor driving unit <NUM> and then outputs the cutoff signal to the motor control circuit <NUM>.

In such a manner as described above, the interlock circuit <NUM> can determine an abnormality in the motor control apparatus <NUM> independently from the motor control circuit <NUM>, can output the cutoff signal to the motor control circuit <NUM>, and can disconnect the motor control unit <NUM> from the motor driving unit <NUM>. As a result, the motor driving unit <NUM> and the motor <NUM> can be prevented from failing and deteriorating.

However, in order to monitor whether or not the command outputted to the motor control circuit <NUM> by the computing processing unit <NUM> is wrong, the interlock circuit <NUM> requires a circuit configuration for separately receiving a command value from the computing processing unit <NUM>. Moreover, in order to monitor an excessive current in the motor driving unit <NUM>, it is required to provide the current detection circuit <NUM>, a wiring lead from the current detection circuit <NUM>, and a comparison circuit for a detection value. Furthermore, it is required to provide a cutoff circuit for transfer the cutoff signal from the interlock circuit <NUM> to the motor control circuit <NUM> and for cutting off the connection between the motor control circuit <NUM> and the motor driving unit <NUM>.

Therefore, providing the interlock circuit <NUM> poses a problem that because in order to provide the interlock circuit <NUM> independently from the motor control circuit <NUM>, a monitoring circuit and a cutoff circuit are provided, the respective circuits of the motor control unit <NUM> and the motor driving unit <NUM> become complicated and large-scaled, which results in upsizing of the motor control apparatus <NUM> and increase in the weight and the cost thereof.

<FIG> is a configuration diagram of the motor control apparatus <NUM> according to Embodiment <NUM>. The motor control apparatus <NUM> in <FIG> includes a motor control unit <NUM> having the computing processing unit <NUM> and a motor control circuit <NUM>, the cutoff apparatus <NUM>, and the motor driving unit <NUM>. The motor control apparatus <NUM> in <FIG> is different from the conventional example in <FIG> in that there exists no interlock circuit <NUM> and in that the cutoff apparatus <NUM> is inserted between the motor control circuit <NUM> and the motor driving unit <NUM>.

An input signal from the outside is inputted to the computing processing unit <NUM> (unillustrated). Based on the input signal, the computing processing unit <NUM> calculates a current to be supplied to the motor <NUM>, outputs a command to the motor control circuit <NUM>, and then outputs a control signal to the motor driving unit <NUM> by way of the motor control circuit <NUM>. The motor control circuit <NUM> transfers a control signal to the motor driving unit <NUM> by way of the cutoff apparatus <NUM>. In accordance with the control signal received from the motor control circuit <NUM>, the motor driving unit <NUM> supplied a current to the motor <NUM> through the motor connection terminals <NUM> and <NUM>.

The motor driving unit <NUM> in <FIG> is the same as the motor driving unit <NUM> according to the conventional example in <FIG>. The cutoff apparatus <NUM> receives the output of the motor control circuit <NUM>; in the case where no abnormality exists, the output is directly transferred to the motor driving unit <NUM>. In the case where any abnormality exists in the output of the motor control circuit <NUM>, the cutoff apparatus <NUM> cuts off the output of the motor control circuit <NUM> and does not transfer the output to the motor driving unit <NUM>. In addition, it may be allowed that the input and the output of the cutoff apparatus <NUM> are connected with each other through an electronic component, such as an FET, a bipolar transistor, a thyristor, or an IC (Integrated Circuit), included in a semiconductor switch and that in the case where the cutoff is required, the connection between the motor control unit <NUM> and the motor driving unit <NUM> is cut off. It may be allowed that the input and the output of the cutoff apparatus <NUM> are connected with each other through a mechanical component such as a relay and that in the case where the cutoff is required, the connection between the motor control unit <NUM> and the motor driving unit <NUM> is cut off by turning off the relay.

The motor driving unit <NUM> in <FIG> incorporates the positive-polarity FETs <NUM> and <NUM> and the negative-polarity FETs <NUM> and <NUM>. The positive-polarity FET <NUM> and the negative-polarity FET <NUM> are connected in series with each other between the positive-polarity power source and the negative-polarity power source; the connection point is connected with the motor connection terminal <NUM>. The positive-polarity FET <NUM> and the negative-polarity FET <NUM> are connected in series with each other between the positive-polarity power source and the negative-polarity power source; the connection point is connected with the motor connection terminal <NUM>. The motor connection terminals <NUM> and <NUM> are connected with the motor <NUM>.

There exists neither the case where both the positive-polarity FET <NUM> and the positive-polarity FET <NUM> of the motor driving unit <NUM> are concurrently turned on nor the case where both the negative-polarity FET <NUM> and the negative-polarity FET <NUM> thereof are concurrently turned on. It can be determined that such an output is wrong and abnormal. The cutoff apparatus <NUM> monitors the control signal received from the motor control circuit <NUM>; in the case where the control signal is wrong, the cutoff apparatus <NUM> determines an abnormality and cuts off the output of the motor control circuit <NUM>, but does not transfer the control signal to the motor driving unit <NUM>.

In addition, both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> that are connected in series with each other are turned off; alternatively, only one of thereof is turned on and the other thereof is turned off. When both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> are concurrently turned on, the motor <NUM> is not driven, and a large current flows in the positive-polarity FET <NUM> and the negative-polarity FET <NUM> that are directly connected with each other between the positive-polarity power source and the negative-polarity power source; thus, the motor driving unit <NUM> is caused to fail. Similarly, both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> that are connected in series with each other are turned off; alternatively, only one of thereof is turned on and the other thereof is turned off. When both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> are concurrently turned on, the motor <NUM> is not driven, and a large current flows in the positive-polarity FET <NUM> and the negative-polarity FET <NUM> that are directly connected with each other between the positive-polarity power source and the negative-polarity power source; thus, the motor driving unit <NUM> is caused to fail.

When the motor control unit <NUM> is normal, there exists neither the case where both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> of the motor driving unit <NUM> are regularly and concurrently turned on nor the case where both the positive-polarity FET <NUM> and the negative-polarity FET <NUM> thereof are concurrently turned on. In such a case, an excessive current caused by the direct connection flows in the motor driving unit; thus, in the case where the motor control unit <NUM> outputs such a control signal, it is made possible that the cutoff apparatus <NUM> determines an abnormality caused by a direct-connection excessive current, cuts off the output of the motor control circuit <NUM>, and prevents the motor driving unit <NUM> from failing.

As described above, by monitoring the control signal outputted by the motor control unit <NUM>, the cutoff apparatus <NUM> can determine a wrong-output abnormality and a direct-connection excessive-current abnormality that causes a large current to flow, and can cut off the output of the motor control circuit <NUM> so as to prevent the motor driving unit <NUM> from failing. In this situation, there are not required a large-scaled circuit such as the interlock circuit <NUM> in the conventional technology, wiring of a signal line from the computing processing unit <NUM>, wiring of a signal line from the current detection circuit <NUM> of the motor driving unit <NUM>, the cutoff circuit for the motor control circuit <NUM>, and wiring of a signal line to the cutoff circuit for the motor control circuit <NUM>. The adoption of the cutoff apparatus <NUM> makes it possible to obtain a motor control apparatus having a cutoff circuit that is effective while suppressing upsizing, weight increase, and cost increase.

Although in <FIG>, there has been described an example where as the switching device of the motor driving unit, an FET is utilized, it may be allowed that the motor driving unit is configured by use of a bipolar transistor, a thyristor, or a relay.

With regard to driving of the motor <NUM>, the driving current is often controlled by duty-driving the FETs <NUM> through <NUM> of the motor driving unit <NUM>. In this situation, although each of the FETs <NUM> through <NUM> repeats on/off-control, the cutoff apparatus <NUM> can calculate a motor energization current Im from the ON-time of a duty-control period. In the case where the calculated motor energization current Im exceeds a preliminarily determined excessive-current determination value Iov, the cutoff apparatus <NUM> considers that an excessive current has flowed and then makes an abnormality determination. In the case where the cutoff apparatus <NUM> makes an excessive-current abnormality determination, the output of the motor control circuit <NUM> is cut off, so that the motor driving unit <NUM> and the motor <NUM> can be prevented from failing.

Moreover, by accumulating the respective ON-times of the FETs <NUM> through <NUM> of the motor driving unit <NUM> for an average-value calculation time Tav and then dividing the accumulated ON-time by the average-value calculation time Tav, the cutoff apparatus <NUM> can calculate an average motor energization current Ima for the average-value calculation time Tav. In the case where the average motor energization current Ima exceeds a predetermined average-current excess determination value Iova, the cutoff apparatus <NUM> considers that an excessive current has continued flowing for the average-value calculation time Tav, determines an abnormality, cuts off the output of the motor control circuit <NUM>, so that the motor driving unit <NUM> can be prevented from failing. By specifying a determination value satisfying the equation "Iova < Iov", a value smaller than the excessive-current determination value Iov that should not be instantaneously exceeded can be designated as the average-current excess determination value Iova that should not be continuously exceeded. As a result, the motor driving unit <NUM> and the motor <NUM> can be prevented from failing and deteriorating due to an overheating state. Each of Iova and Iov may be obtained through a calculation based on the performance of a FET device to be utilized and the impedance and reactance of the motor <NUM> or can be obtained through an experiment.

As described above, by monitoring the control signal outputted by the motor control unit <NUM>, the cutoff apparatus <NUM> can calculate the motor energization current Im to be supplied by the motor driving unit <NUM>. In the case where the motor energization current Im exceeds the excessive-current determination value Iov, the cutoff apparatus <NUM> considers that an excessive current has flowed and then makes an abnormality determination, so that the output of the motor control circuit <NUM> can be cut off. Moreover, the cutoff apparatus <NUM> calculates the average motor energization current Ima for the average-value calculation time Tav; in the case where the average motor energization current Ima exceeds the average-current excess determination value Iova, the cutoff apparatus <NUM> considers that an excessive current has continued flowing for the average-value calculation time Tav and then determines an abnormality, so that the output of the motor control circuit <NUM> can be cut off. The adoption of the cutoff apparatus <NUM> makes it possible to obtain a motor control apparatus having a cutoff circuit that requires none of a large-scaled circuit such as the interlock circuit <NUM>, provision of the current detection circuit <NUM>, and wiring of a connection line and that is effective, while suppressing upsizing, weight increase, and cost increase.

<FIG> is a hardware configuration diagram of a control apparatus <NUM> according to Embodiment <NUM>. In the present embodiment, the hardware configuration of the control apparatus <NUM> is applied to the motor control unit <NUM> and the cutoff apparatus <NUM> of the motor control apparatus <NUM>. Respective functions of the control apparatus <NUM> are realized by processing circuits provided in the control apparatus <NUM>. Specifically, as illustrated in <FIG>, the control apparatus <NUM> includes, as the processing circuits, a computing processing unit (computer) <NUM> such as a CPU (Central Processing Unit), storage apparatuses <NUM> that exchange data with the computing processing unit <NUM>, an input circuit <NUM> that inputs external signals to the computing processing unit <NUM>, an output circuit <NUM> that outputs signals from the computing processing unit <NUM> to the outside, and the like.

It may be allowed that as the computing processing unit <NUM>, an ASIC (Application Specific Integrated Circuit), an IC, a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), each of various kinds of logic circuits, each of various kinds of signal processing circuits, or the like is provided. In addition, it may be allowed that as the computing processing unit <NUM>, two or more computing processing units of the same type or different types are provided and respective processing items are executed in a sharing manner. As the storage apparatuses <NUM>, there are provided a RAM (Random Access Memory) that can read data from and write data in the computing processing unit <NUM>, a ROM (Read Only Memory) that can read data from the computing processing unit <NUM>, a flash memory, and the like. The input circuit <NUM> is connected with various kinds of sensors and switches and is provided with an A/D converter and the like for inputting output signals from the sensors and the switches to the computing processing unit <NUM>. The output circuit <NUM> is connected with electric loads and is provided with a driving circuit and the like for converting and outputting a control signal from the computing processing unit <NUM> to the electric loads.

The computing processing unit <NUM> runs software items (programs) stored in the storage apparatus <NUM> such as a ROM and collaborates with other hardware devices in the control apparatus <NUM>, such as the storage apparatus <NUM>, the input circuit <NUM>, and the output circuit <NUM>, so that the respective functions provided in the control apparatus <NUM> are realized. Setting data items such as a threshold value and a determination value to be utilized in the control apparatus <NUM> are stored, as part of software items (programs), in the storage apparatus <NUM> such as a ROM.

It may be allowed that the respective functions included in the control apparatus <NUM> in <FIG> are configured with either software modules or combinations of software and hardware.

It may be allowed that each of the motor control unit <NUM> and the cutoff apparatus <NUM> is configured with a separate control apparatus <NUM>. It may be allowed that the motor control unit <NUM> and the cutoff apparatus <NUM> are configured as separate modules in one and the same control apparatus. It may be allowed that the cutoff apparatus <NUM> is not provided with the computing processing unit <NUM> and the storage apparatus <NUM> but is configured with only hardware items such as a logic circuit, an amplifier, an integrator, a sampling/hold device, and a comparator.

Hereinafter, there will be explained software processing to be executed in the case where as the hardware configuration of the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>, the configuration of the control apparatus <NUM> is utilized.

<FIG> is a flowchart of main processing executed by the computing processing unit <NUM> of the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. The main processing of the control is executed every predetermined time (for example, every <NUM>). In the present embodiment, there has been explained an example where the main processing is executed every predetermined time; however, it may be allowed that the main processing is executed by utilizing, as a trigger, a specific signal such as a rotation-angle signal of the motor.

The computing processing unit <NUM> starts the processing in the step S301, and executes initialization processing in the step S400. The processing contents of the step S400 are represented in the steps S401 through S419 in <FIG>.

Next, in the step S500, the computing processing unit <NUM> executes direct-connection abnormality determination processing and wrong-output abnormality determination processing. The processing contents of the step S500 are represented in the steps S501 through S519 in <FIG>.

Next, in the step S600, the computing processing unit <NUM> executes excess-current determination processing. The processing contents of the step S600 are represented in the steps S601 through S619 in <FIG>.

Next, the computing processing unit <NUM> executes cutoff processing in the step S700 and ends the processing in the step S309. The processing contents of the step S700 are represented in the steps S701 through S719 in <FIG>.

<FIG> is a flowchart representing the contents of the initialization processing. The steps S401 through S419 in <FIG> are details of the step S400 of the flowchart in <FIG>.

The computing processing unit <NUM> starts the processing in the step S401 and then determines in the step S402 whether or not the present timing is immediately after the power source of the cutoff apparatus <NUM> has been turned on. In the case where the present timing is immediately after the power source of the cutoff apparatus <NUM> has been turned on, the computing processing unit <NUM> executes the steps S403 through S410 and then initializes counters and flags. In the step S403, the computing processing unit <NUM> clears a direct-connection abnormality counter C_shrt ("<NUM>" is set). In the step S404, the computing processing unit <NUM> clears a wrong-output abnormality counter C_ng. In the step S405, the computing processing unit <NUM> clears an excessive-current counter C_Iov. In the step S406, the computing processing unit <NUM> clears an average-current excess counter. In the step S407, the computing processing unit <NUM> clears a direct-connection abnormality flag f_shrt. In the step S408, the computing processing unit <NUM> clears a wrong-output abnormality flag f_ng. In the step S409, the computing processing unit <NUM> clears an excessive-current flag f_Iov. Then, in the step S410, the computing processing unit <NUM> clears an average-current excess flag f_Iova and ends the processing in the step S419.

In the case where in the step S402, the present timing is not immediately after the power source of the cutoff apparatus <NUM> has been turned on, the computing processing unit <NUM> initializes neither the counters nor the flags, and then ends the processing in the step S419.

<FIG> is a flowchart representing the contents of the direct-connection abnormality determination processing and the wrong-output abnormality determination processing. The flowchart for the steps S501 through S519 represents the details of the step S500 of the flowchart in <FIG>.

The computing processing unit <NUM> starts the processing in the step S501 and determines in the step S502 whether or not the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the signal is an abnormal signal for making the FET <NUM> and the FET <NUM> directly connect the positive-polarity power source and the negative-polarity power source of the motor driving unit <NUM> and causes a direct-connection excessive current, the step S502 is followed by the step S510, where the direct-connection abnormality counter C_shrt is incremented; then, in the step S519, the processing is ended.

In the case where in the step S502, the control signal is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S502 is followed by the step S503. In the step S503, it is determined whether or not the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>, it is determined that there exists a direct-connection abnormality; then, the step S503 is followed by the step S510. In the case where the control signal outputted by the motor control unit <NUM> is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S503 is followed by the step S505.

In the step S505, it is determined whether or not the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the FET <NUM> and the FET <NUM>, the step S505 is followed by the step S506. In the case where both the FET <NUM> and the FET <NUM> are off, the step S505 is followed by the step S507.

In the step S506, it is determined whether or not the control signal is a signal for turning on any one of the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the FET <NUM> and the FET <NUM>, it is determined that no abnormality exists; then, the step S506 is followed by the step S508. In the case where the control signal is a signal for turning off all of the FET <NUM> and the FET <NUM>, it is determined that a wrong-output abnormality exists, because although a current is poured into the motor <NUM>, no current is sucked out of the motor; in the step S511, the wrong-output abnormality counter C_ng is incremented; then, in the step S519, the processing is ended.

In the step S507, it is determined whether or not the control signal is a signal for turning on any one of the FET <NUM> and the FET <NUM>. In the case where the control signal is a signal for turning on any one of the FET <NUM> and the FET <NUM>, it is determined that a wrong-output abnormality exists, because the signal is for the state where although no current is poured into the motor <NUM>, a current is sucked out of the motor; then, the step S507 is followed by the step S511. In the case where the control signal is a signal for turning off all of the FET <NUM> and the FET <NUM>, it is determined that no abnormality exists; then, the step S507 is followed by the step S508.

In the step S508, the direct-connection abnormality counter C_shrt is cleared. In the step S509, the wrong-output abnormality counter C_ng is cleared. Then, the processing is ended in the step S519.

<FIG> is a flowchart representing the contents of the excess-current determination processing. The flowchart for the steps S601 through S619 represents the details of the step S600 of the flowchart in <FIG>.

In the step S601, the processing is started; in the step S602, the motor energization current Im to be supplied by the motor driving unit <NUM> is calculated from the control signal outputted by the motor control unit <NUM>. With regard to driving of the motor <NUM>, the driving current is often controlled by duty-driving the FETs <NUM> through <NUM> of the motor driving unit <NUM>. In this situation, although each of the FETs <NUM> through <NUM> repeats on/off-control, the cutoff apparatus <NUM> can calculate the motor energization current Im from the ON-time of a duty-control period. In the step S603, the newest calculated motor energization current Im(n) is stored in the storage apparatus <NUM>. The main processing is executed every millisecond; thus, by sequentially storing the motor energization currents obtained every millisecond Im(<NUM>), Im(<NUM>), Im(<NUM>), ---, Im(n), an average motor energization current Ima, which is the average value of the motor energization current Im per average-value calculation time Tav can be obtained. The storage areas can circulatively be utilized by use of a ring buffer as the storage apparatus <NUM>; thus, the averaging processing can be implemented within a limited storage area. With regard to the averaging, the moving average in the immediately previous average-value calculation time Tav is obtained each time the processing is executed (every millisecond). Alternatively, an interval average value may be obtained every average-value calculation time Tav.

Next, in the step S <NUM>, it is determined whether or not the motor energization current Im is larger than the excessive-current determination value Iov. In the case where the motor energization current Im is larger than the excessive-current determination value Iov, the step S <NUM> is followed by the step S608, where the excessive-current counter C_Iov is incremented; then, the processing is ended in the step S619.

In the case where the motor energization current Im is not larger than the excessive-current determination value Iov, the step S <NUM> is followed by the step S605. In the step S605, the motor energization current Im in the immediately previous average-value calculation time Tav is accumulated and then is divided by the average-value calculation time Tav, so that the average motor energization current Ima is calculated. In this example, the average motor energization current Ima is calculated through moving averaging or through interval averaging during the average-value calculation time Tav. However, the average motor energization current Ima may be calculated every average-value calculation time Tav through a first-order lag calculation utilizing the equation "Ima(n) ← K × Im + (<NUM>-K) × Ima(n-<NUM>)". Here, K is a constant (<NUM> < K < <NUM>); the present average motor energization current Ima(n) is obtained every average-value calculation time Tav, by use of the immediately previous average motor energization current Ima(n-<NUM>) and the newest motor energization current Im. The necessary memory usage amount in the storage apparatus <NUM> can be reduced by utilizing the first-order lag calculation.

Next, in the step S <NUM>, it is determined whether or not the average motor energization current Ima is larger than the average-current excess determination value Iova. In the case where the average motor energization current Ima is larger than the average-current excess determination value Iova, the step S <NUM> is followed by the step S609, where the average-current excess counter C_Iova is incremented; then, the processing is ended in the step S619.

In the case where in the step S606, the average motor energization current Ima is not larger than the average-current excess determination value Iova, the motor energization current Im is not an excessive current and the average motor energization current Ima does not exceed the average current; therefore, the excessive-current counter C_Iov is cleared in the step S607 and the average-current excess counter C_Iova is cleared in the step S608; then, the processing is ended in the step S619.

<FIG> is a flowchart representing the contents of the cutoff processing. The flowchart for the steps S701 through S719 represents the details of the step S700 of the flowchart in <FIG>.

The processing is started in the step S701; in the step S702, it is determined whether or not the value of the direct-connection abnormality counter C_shrt is larger than a direct-connection abnormality determination time T_shrt. In the case where the value of the direct-connection abnormality counter C_shrt is larger than the direct-connection abnormality determination time T_shrt, a direct-connection abnormality is determined, and the step S702 is followed by the step S706, where the direct-connection abnormality flag f_shrt is set ("<NUM>" is inputted). Then, there is set a direct-connection abnormality storage flag f_shrtM, which is not cleared in the initialization processing, provided in a nonvolatile storage apparatus. After that, in the step S710, the motor driving unit <NUM> is cut off from the motor control unit <NUM>; then, the processing is ended in the step S719.

In the case where in the step S702, the value of the direct-connection abnormality counter C_shrt is not larger than the direct-connection abnormality determination time T_shrt, the step S702 is followed by the step S703. In the step S703, it is determined whether or not the value of the wrong-output abnormality counter C_ng is larger than a wrong-output abnormality determination time T_ng. In the case where the value of the wrong-output abnormality counter C_ng is larger than a wrong-output abnormality determination time T_ng, a wrong-output abnormality is determined, and the step S703 is followed by the step S707. In the step S707, the wrong-output abnormality flag f_ng is set. Then, there is set a wrong-output abnormality storage flag f_ngM, which is not cleared in the initialization processing, provided in a nonvolatile storage apparatus; then, the step S707 is followed by the step S710.

In the case where in the step S703, the value of the wrong-output abnormality counter C_ng is not larger than the wrong-output abnormality determination time T_ng, the step S703 is followed by the step S704. In the step S704, it is determined whether or not the value of the excessive-current counter C_Iov is larger than an excessive-current determination time T_Iov. In the case where the value of the excessive-current counter C_Iov is larger than the excessive-current determination time T_Iov, an excessive-current determination is settled, and the step S704 is followed by the step S708. In the step S708, the excessive-current flag f_Iov is set. Then, there is set an excessive-current storage flag f_IovM, which is not cleared in the initialization processing, provided in an nonvolatile storage apparatus; then, the step S708 is followed by the step S710.

In the case where in the step S704, the value of the excessive-current counter C_Iov is not larger than the excessive-current determination time T_Iov, the step S704 is followed by the step S705. In the step S705, it is determined whether or not the value of the average-current excess counter C_Iova is larger than an average-current excess time T_Iova. In the case where the value of the average-current excess counter C_Iova is larger than the average-current excess time T_Iova, an average-current excess determination is settled, and the step S705 is followed by the step S709. In the step S709, the average-current excess flag f_Iova is set. Then, there is set an average-current excess storage flag f_IovaM, which is not cleared in the initialization processing, provided in a nonvolatile storage apparatus; then, the step S709 is followed by the step S710.

In the case where in the step S705, the value of the average-current excess counter C_Iova is not larger than the average-current excess time T_Iova, the step S705 is followed by the step S719, where the processing is ended. As far as the respective values of the direct-connection abnormality determination time T_shrt, the wrong-output abnormality determination time T_ng, the excessive-current determination time T_Iov, and the average-current excess time T_Iova are concerned, a time suitable for determining each of the respective abnormalities can be set through an experiment or a desktop calculation.

Such a configuration makes it possible to realize the function of the cutoff apparatus <NUM> by means of software. As a result, it is made possible to obtain the effective cutoff apparatus <NUM>, while suppressing the motor control apparatus <NUM> from being upsized, increasing its weight, and increasing its cost. In addition, in the case where when the cutoff processing is executed, flags indicating the causes of the cutoffs are stored in a nonvolatile storage apparatus, the postliminary investigation is facilitated.

A motor control apparatus <NUM> according to Embodiment <NUM> will be explained with reference to the drawings. <FIG> is a configuration diagram of the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of main processing by a cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>. <FIG> is a flowchart of short-circuit determination processing and wrong-output determination processing by the cutoff apparatus <NUM> in the motor control apparatus <NUM> according to Embodiment <NUM>.

In Embodiment <NUM>, the motor <NUM> connected with the two connection terminals <NUM> and <NUM> has been exemplarily represented; however, the number of the connection terminals to be connected with the motor is not limited to two. In Embodiment <NUM>, as shown in <FIG>, there is represented an example where the motor control apparatus <NUM> is applied to the three-phase AC motor <NUM> connected with three connection terminals <NUM>, <NUM>, and <NUM>. In contrast to the configuration diagram in <FIG>, in <FIG>, a motor driving unit <NUM> has six FETs <NUM> through <NUM> and currents are supplied to the three-phase AC motor <NUM> through the three connection terminals <NUM>, <NUM>, and <NUM>. In response to a command from the computing processing unit <NUM>, a motor control circuit <NUM> outputs a control signal to the six FETs <NUM> through <NUM>.

The cutoff apparatus <NUM> is provided between a motor control unit <NUM> and the motor driving unit <NUM> and outputs the control signal, received from the motor control unit <NUM>, to the motor driving unit <NUM>. The cutoff apparatus <NUM> detects various kinds of abnormalities from the control signal and cuts off the motor driving unit <NUM> from the motor control unit <NUM> at a time when an abnormality exists.

There will be explained software processing to be executed at a time when the configuration of the control apparatus <NUM> is applied to the configuration of the cutoff apparatus <NUM>.

The computing processing unit <NUM> starts the processing in the step S901, and executes initialization processing in the step S400. The processing contents of the step S400 are the same as those in Embodiment <NUM> and are represented in the steps S401 through S419 in <FIG>.

Next, in the step S1000, the computing processing unit <NUM> executes direct-connection abnormality determination processing and wrong-output abnormality determination processing. The processing contents of the step S1000 are represented in the steps S1001 through S1019 in <FIG>.

Next, in the step S600, the computing processing unit <NUM> executes excess-current determination processing. The processing contents of the step S600 are the same as those in Embodiment <NUM> and are represented in the steps S601 through S619 in <FIG>.

Next, the computing processing unit <NUM> executes cutoff processing in the step S700 and ends the processing in the step S909. The processing contents of the step S700 are the same as those in Embodiment <NUM> and are represented in the steps S701 through S719 in <FIG>.

<FIG> is a flowchart representing the contents of the direct-connection abnormality determination processing and the wrong-output abnormality determination processing. The flowchart for the steps S1001 through S1019 represents the details of the step S1000 of the flowchart in <FIG>.

The flowchart in <FIG> is different from the flowchart in <FIG> according to Embodiment <NUM> in that the step S1004 is added to the steps S501 through S519 because the number of the FETs has increased from <NUM> to <NUM> and in that the number of the FETs in each of the steps S1005, S1006, and S1007 has increased by <NUM> from the number of the FETs in each of the steps S505, S506, and S507.

The computing processing unit <NUM> starts the processing in the step S1001 and determines in the step S1002 whether or not the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the signal is an abnormal signal for making the FET <NUM> and the FET <NUM> directly connect the positive-polarity power source and the negative-polarity power source of the motor driving unit <NUM> and causes a direct-connection excessive current, the step S1002 is followed by the step S1010, where the direct-connection abnormality counter C_shrt is incremented; then, in the step S1019, the processing is ended.

In the case where in the step S1002, the control signal is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S1002 is followed by the step S1003. In the step S1003, it is determined whether or not the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>, it is determined that there exists a direct-connection abnormality; then, the step S1003 is followed by the step S1010. In the case where the control signal outputted by the motor control unit <NUM> is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S1003 is followed by the step S1004.

In the case where in the step S1003, the control signal is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S1003 is followed by the step S1004. In the step S1004, it is determined whether or not the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for concurrently turning on the FET <NUM> and the FET <NUM>, it is determined that there exists a direct-connection abnormality; then, the step S1004 is followed by the step S1010. In the case where the control signal outputted by the motor control unit <NUM> is not a signal for concurrently turning on the FET <NUM> and the FET <NUM>, the step S1004 is followed by the step S1005.

In the step S1005, it is determined whether or not the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the positive-polarity FETs <NUM>, <NUM> and <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the FETs <NUM>, <NUM>, and <NUM>, the step S1005 is followed by the step S1006. In the case where all of the FETs <NUM>, <NUM>, and <NUM> are off, the step S1005 is followed by the step S1007.

In the step S1006, it is determined whether or not the control signal is a signal for turning on any one of the FETs <NUM>, <NUM>, and <NUM>. In the case where the control signal outputted by the motor control unit <NUM> is a signal for turning on any one of the FETs <NUM>, <NUM>, and <NUM>, it is determined that no abnormality exists; then, the step S1006 is followed by the step S1008. In the case where the control signal is a signal for turning off all of the FETs <NUM>, <NUM>, and <NUM>, it is determined that a wrong-output abnormality exists; then, in the step S1011, the wrong-output abnormality counter C_ng is incremented; after that, the processing is ended in the step S1019.

In the step S1007, it is determined whether or not the control signal is a signal for turning on any one of the FETs <NUM>, <NUM>, and <NUM>. In the case where the control signal is a signal for turning on any one of the FETs <NUM>, <NUM>, and <NUM>, it is determined that a wrong-output abnormality exists; then, the step S1007 is followed by the step S1011. In the case where the control signal is a signal for turning off all of the FETs <NUM>, <NUM>, and <NUM>, it is determined that no abnormality exists; then, the step S1007 is followed by the step S1008.

In the step S1008, the direct-connection abnormality counter C_shrt is cleared. In the step S1009, the wrong-output abnormality counter C_ng is cleared. Then, the processing is ended in the step S1019.

As described above, the case where the motor <NUM> is a three-phase AC motor has been explained. Even when the motor is connected with terminals, the number of which is other than two or three, of the motor driving unit, even when the motor has phases, the number of which is other than two or three, or even when the motor is not an AC motor but a DC motor, the control-signal abnormality determination and the cutoff processing by the cutoff apparatus according to the present disclosure can be utilized.

A motor control apparatus <NUM> according to Embodiment <NUM> will be explained with reference to the drawings. <FIG> is a hardware configuration diagram of the motor control apparatus <NUM> according to Embodiment <NUM>.

<FIG> represents a configuration where the cutoff apparatus <NUM> is added to the motor control apparatus <NUM> in <FIG> according to the conventional example. The hardware configuration in <FIG> is different from the conventional example in that the cutoff apparatus <NUM> is provided between the motor driving unit <NUM> and the motor control unit <NUM> having the interlock circuit <NUM>.

The configuration of the conventional example is not changed but only the cutoff apparatus <NUM> is added thereto, so that the redundancy of the cutoff function is expanded for an abnormality in the motor control apparatus. Such a configuration makes it possible to perform double monitoring with regard to detection of an abnormality in the motor control apparatus <NUM> and cutoff of the motor control apparatus <NUM>. As described above, the cutoff apparatus <NUM> can additionally be provided without changing the existing motor control apparatus; thus, this method is very significant because the redundancy can readily be expanded in a small-scale, lightweight, and low-cost manner.

<FIG> is a configuration diagram of an electric power steering apparatus <NUM> according to Embodiment <NUM>. In <FIG>, there will be explained an example in which the motor control apparatus <NUM> and the motor <NUM> are applied to the electric power steering apparatus <NUM> to be mounted in a vehicle. The electric power steering apparatus <NUM> in <FIG> is an example of a rack-type electric power steering apparatus. Even when instead of the motor control apparatus <NUM>, the motor control apparatus <NUM> or <NUM> is utilized in the electric power steering apparatus <NUM> according to Embodiment <NUM>, the same effect is provided.

When a driver makes the steering mechanism of a vehicle generate steering torque by means of a steering wheel <NUM>, a torque sensor <NUM> detects the steering torque and then outputs it to the motor control apparatus <NUM>. In addition, a speed sensor <NUM> detects the traveling speed of the vehicle and then outputs it to the motor control apparatus <NUM>. Based on the inputs from the torque sensor <NUM> and the speed sensor <NUM>, the motor control apparatus <NUM> drives the motor <NUM> so as to generate auxiliary torque for supplementing the steering torque and then supplies it to the steering mechanism of front wheels <NUM> of the vehicle. In <FIG>, illustration of the torque sensor <NUM> and the speed sensor <NUM> is omitted. It may be allowed that the motor control apparatus <NUM> generates auxiliary torque based on inputs other than the inputs from the torque sensor <NUM> and the speed sensor <NUM>.

Claim 1:
A motor control apparatus (<NUM>) comprising:
a motor (<NUM>);
a motor driving unit (<NUM>) comprising:
two or more positive-polarity switching devices (<NUM>,<NUM>) connected with a positive-polarity side of a DC power source,
two or more negative-polarity switching devices (<NUM>,<NUM>) connected with a negative-polarity side of the DC power source, and
an output terminal (<NUM>,<NUM>) provided for each connection point at which one of the positive-polarity switching devices (<NUM>,<NUM>) and one of the negative-polarity switching devices (<NUM>,<NUM>) are connected in series with each other,
wherein the motor driving unit (<NUM>) is configured to supply a current to the motor (<NUM>) through the output terminals (<NUM>,<NUM>);
a motor control unit (<NUM>) configured to transmit a control signal that controlls the current supplied by the motor driving unit (<NUM>) through duty control that turns on and off each of the positive side switching element and the negative side switching element of the motor drive unit (<NUM>); and
a cutoff apparatus (<NUM>) disposed between the motor control unit (<NUM>) and the motor driving unit (<NUM>)
characterized in that the cutoff apparatus (<NUM>) is configured to calculate a current value flowing from the motor driving unit (<NUM>) to the motor (<NUM>) based on the on time of the duty control cycle of the control signal, and cut off the control signal transmitted from the motor control unit (<NUM>) to the motor driving unit (<NUM>), when a calculated current value exceeds an excessive-current determination value.