Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Embodiments of 3D memory devices with deposited semiconductor plugs and methods for forming the same are disclosed herein. A three-dimensional memory device according to the invention is presented in claim <NUM>.

In one example, a 3D memory device includes a substrate, a memory deck, and a memory string. The memory deck includes a plurality of interleaved conductor layers and dielectric layers on the substrate. The memory string extends vertically through the memory deck. A bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers intersects with and contacts the memory string.

In another example, a 3D memory device includes a substrate, a memory stack, and a memory string. The memory stack includes a plurality of memory decks each having a plurality of interleaved conductor layers and dielectric layers over the substrate. The memory string includes a plurality of memory sub-strings extending vertically through the memory stack, each memory deck having a respective memory sub-string. A bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers intersects with and contacts the memory string.

In still another example, a method for forming a 3D memory device includes the following operations. First, a bottom sacrificial layer is formed over a substrate. A dielectric deck having a plurality of interleaved sacrificial layers and dielectric layers is formed over the bottom sacrificial layer. A memory string is then formed extending through the dielectric deck and the bottom sacrificial layer and contacting the substrate. A support pillar is formed extending through the dielectric deck and the bottom sacrificial layer to contact the substrate. Further, the bottom sacrificial layer is replaced with a bottom dielectric layer between the dielectric deck and the substrate. A source structure is then formed extending through the dielectric deck and into the substrate.

In a further example, a method for forming a 3D memory device includes the following operations. First, a bottom sacrificial layer is formed over a substrate. A first dielectric deck having a plurality of first interleaved sacrificial layers and dielectric layers is formed over the bottom sacrificial layer. A first memory string is formed extending through the first dielectric deck and the bottom sacrificial layer and contacting the substrate. A second dielectric deck having a plurality of second interleaved sacrificial layers and dielectric layers is then formed over the first dielectric deck. A second memory string is formed extending through the second dielectric deck and conductively connecting with the first memory string. The bottom sacrificial layer is replaced with a bottom dielectric layer between the first dielectric deck and the substrate. The plurality of first and second sacrificial layers is then replaced with a plurality of conductors to form a first and a second memory decks. A source structure is formed extending through the first and the second memory decks and into the substrate.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

As used herein, the term "3D memory device" refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate.

In some 3D memory devices, such as 3D NAND memory devices, a semiconductor plug is typically formed at one end of a memory string. The semiconductor plug acts as a channel of a transistor when combined with a gate conductor layer formed surrounding it. In fabricating 3D NAND memory devices with advanced technologies, such as having <NUM> or more levels, a dual-deck architecture is usually used, which requires removal of a sacrificial layer (e.g., polysilicon) that fills the lower channel hole in the lower deck above the semiconductor plug. The semiconductor plug is often a selective epitaxial growth (SEG) structure formed by epitaxially growing a semiconductor (e.g., silicon) on the substrate at the lower portion of a channel hole. The SEG structure is conductively connected to a semiconductor channel of the memory string and a heavy P-well in the substrate when the memory string is formed. The "erase" operation of a 3D memory device is based on Fowler-Nordheim (FN) tunneling.

The fabrication of SEG structures can cause issues in a 3D memory device. For example, the thicknesses of SEG structures may vary in different memory strings due to factors such as the etching profile of channel holes and growth condition of the SEG structures. The growth of SEG structures can be sensitive to the pattern loading of channel holes and/or support pillar holes. These can cause threshold voltages of the memory strings to vary. Also, the etching of the bottoms of channel holes to expose the substrate before the formation of SEG structures can cause damages to the channel holes and layers deposited on the sidewall of the channel holes. The damage can even exacerbate when the 3D memory device has more than one memory deck stacking together if the semiconductor channels in adjacent memory decks are not precisely aligned. That is, a multi-deck memory device with SEG structures often requires semiconductor channels in adjacent memory decks to have high alignment precision (e.g., small upper-to-lower deck overlay) to avoid or reduce damages to the sidewall of the channel hole during the formation of the SEG structures.

To avoid such issues caused by SEG structures, some 3D memory devices have "SEG-free" structures. In these memory devices, a lower portion of a semiconductor channel is often conductively connected to a source line that is buried between the memory deck and the substrate. The "erase" operation of the 3D memory device is mainly based on gate-induced drain leakage (i.e., GIDL) current induced erase of majority carriers. The mobility of the majority carriers in the semiconductor channel (e.g., holes) can be affected by the minority carriers (e.g., electrons) in the source line, causing the "erase" operation in the memory cells formed by the semiconductor channel to have a slower speed. In a 3D memory device with more than one memory deck stacking together, the speed can be even slower compared to a single stack memory device.

Various embodiments in accordance with the present disclosure provide 3D memory devices without SEGs (i.e., "SEG-free" structures) while maintaining the connection between the memory string and the heavy wells in the substrate. The 3D memory devices of the present disclosure may not have SEG structures at the lower portions of memory strings. Instead, the 3D memory devices include semiconductor plugs formed by depositing a semiconductor material at bottoms of channel holes. To form the semiconductor plugs, a bottom sacrificial layer can be formed between a memory deck and the substrate. Plug openings can be formed in the bottom sacrificial layer to expose the substrate after channel holes are formed. A semiconductor material is deposited into the plug openings and the remaining of the bottom sacrificial layer can be replaced with a suitable dielectric material. The top surface of the semiconductor plug is lower than the top surface of the bottom conductor layer of the memory deck, which can contact the semiconductor channel and function as a bottom select gate electrode. The support pillars can be formed separately (e.g., in a separate fabrication process) than the semiconductor channels.

The disclosed structures and methods can have several benefits over existing structures and methods. For example, the bottom dielectric layer, functioning as a bottom select gate dielectric layer, can be formed by transforming the bottom sacrificial layer (e.g., an etch stop layer) into a dielectric layer or replacing the bottom sacrificial layer with a dielectric layer. This can minimize the damage (e.g., caused by the etching of plug openings) to the channel holes during the fabrication of semiconductor plugs, allowing semiconductor plugs of more uniform thicknesses to be formed and thus improving the uniformity of threshold voltages of memory cells. For a 3D memory device with multiple memory decks, the overlay control of the alignment between semiconductor channels of adjacent memory decks can be easier. By using the disclosed structures and methods, semiconductor channels can be connected to the heavy wells in substrate while the "erase" operation can be based on FN tunneling, maintaining the speed of the "erase" operation.

<FIG> illustrates a cross-sectional view of a memory device <NUM> (e.g., a 3D memory device), according to some embodiments of the present disclosure. Memory device <NUM> may include a memory stack <NUM>, which includes a plurality of memory decks. For ease of illustration, two memory decks 104A and 104B are depicted and described in <FIG>. <FIG> illustrates a fabrication process of one memory deck (e.g., 104A), according to some embodiments of the present disclosure. <FIG> illustrates a fabrication process of a memory string having a semiconductor plug in a memory deck (e.g., 104A), according to some embodiments of the present disclosure. <FIG> is a flowchart of the fabrication process illustrated in <FIG>, according to some embodiments of the present disclosure. <FIG> illustrates a flowchart of a fabrication process for forming a dual-deck memory device (e.g., memory device <NUM>), according to some embodiments of the present disclosure.

As shown in <FIG>, memory device <NUM> includes a substrate <NUM>, a bottom dielectric layer <NUM> over substrate <NUM>, and memory stack <NUM> over bottom dielectric layer <NUM>. Memory deck <NUM> may include two memory decks 104A (e.g., a lower memory deck) and 104B (e.g., an upper memory deck) stacking together along a direction (e.g., the vertical direction or the z-direction) perpendicular to a top surface of substrate <NUM>. Each memory deck (e.g., 104A or 104B) includes a plurality of interleaved dielectric layers 110a and conductor layers 110b extending along a direction (e.g., a lateral direction or the x-y plane) parallel to the top surface of substrate <NUM>. A thickness (e.g., along the vertical direction) of bottom dielectric layer <NUM> may be about <NUM> to about <NUM>, such as between <NUM> and <NUM>, (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values).

Memory deck <NUM> includes a plurality of memory strings <NUM> each extending vertically through memory stack <NUM> and bottom dielectric layer <NUM>, to connect to substrate <NUM>, which includes a heavy doped region, e.g., a heavy P-well (not shown in <FIG>) at a top portion of substrate <NUM>, conductively connected to memory strings <NUM>. Memory string <NUM> may include a plurality of (e.g., two) memory sub-strings (e.g., <NUM>-<NUM> and <NUM>-<NUM>), each extending through the respective memory deck (e.g., 104A and 104B). The adjacent memory sub-strings (e.g., <NUM>-<NUM> and <NUM>-<NUM>) may be aligned along the vertical direction (e.g., extending direction of memory strings <NUM>) and may be conductively connected by a channel plug 108f, which includes a conductive material such as poly-silicon or amorphous silicon. Memory string <NUM> may include a top channel plug <NUM> at an upper portion of memory string <NUM>, a top doped region <NUM> in top channel plug <NUM>, and a semiconductor plug <NUM> at a lower portion of memory string <NUM>. Top channel plug <NUM> and top doped region <NUM> may form conductive connection to other devices/circuits such as peripheral devices. Semiconductor plug <NUM> may form conductive connection to the heavy doped region in substrate <NUM>. Memory string <NUM> may include a channel structure that includes a blocking layer 108a, a memory layer 108b, a tunneling layer 108c, a semiconductor layer 108d (e.g., also referred to as a semiconductor channel 108d), and a dielectric core 108e, sequentially arranged from a sidewall to a center of memory string <NUM>. A semiconductor channel (not shown) is formed in the semiconductor layer, conductively connected to semiconductor plug <NUM> and top channel plug <NUM>, for carrier transport when memory device <NUM> is in operation.

Memory deck <NUM> may also include a source structure <NUM> extending vertically through memory stack <NUM> and bottom dielectric layer <NUM> and into substrate <NUM>. Source structure <NUM> may include a doped semiconductor region 106a, an insulating structure 106b extending through memory stack <NUM> and covering conductor layers 110b, and a source conductor 106c extending in insulating structure 106b and being conductively connected to doped semiconductor region 106a. Source structure <NUM> may also include a source plug <NUM> in an upper portion of source conductor 106c for conductively connecting to other devices/circuits (e.g., peripheral devices).

Memory device <NUM> can be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., memory strings) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate <NUM>) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., memory strings) for hybrid bonding. It is understood that in some embodiments, the memory array device substrate (e.g., substrate <NUM>) is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate (e.g., substrate <NUM>) can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the backside of the thinned memory array device substrate.

Substrate <NUM> can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some embodiments, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, substrate <NUM> includes a heavy doped region such as a heavy P-well that includes doped silicon, in the upper portion of substrate <NUM> and contacting memory strings <NUM>.

In some embodiments, memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of memory strings <NUM> (e.g., memory strings) extending vertically above substrate <NUM>. The memory array device can include memory strings <NUM> that extend through a plurality of pairs each including a conductor layer 110b and a dielectric layer 110a (referred to herein as "conductor/dielectric layer pairs"). The stacked conductor/dielectric layer pairs are also referred to herein as a "memory deck" <NUM>. The number of the conductor/dielectric layer pairs in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) determines the number of memory cells in memory device <NUM>. Memory stack <NUM> includes a plurality of interleaved conductor layers 110b and dielectric layers 110a. Conductor layers 110b and dielectric layers 110a in memory stack <NUM> can alternate in the vertical direction. Conductor layers 110b can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Dielectric layers 110a can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The numbers of conductor/dielectric layer pairs in each of lower and upper memory decks 104A and 104B can be the same or different.

As shown in <FIG>, memory string <NUM> can include a channel structure extending vertically through memory stack <NUM>. The channel structure can include a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel 108d) and dielectric material(s) (e.g., as blocking layer 108a, memory layer 108b, and tunneling layer 108c). In some embodiments, semiconductor channel 108d includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. The remaining space of the channel structure can be partially or fully filled with dielectric core 108e including dielectric materials, such as silicon oxide. The channel structure can have a cylinder shape (e.g., a pillar shape). Dielectric core 108e, semiconductor channel 108d, tunneling layer 108c, memory layer 108b, and blocking layer 108a are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. Tunneling layer 108c can include silicon oxide, silicon oxynitride, or any combination thereof. Memory layer 108b can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer 108a can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, tunneling layer 108c/memory layer 108b/blocking layer 108a can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, conductor layer 110b (each being part of a word line) in memory stack <NUM> functions as a gate conductor of memory cells in memory string <NUM>. Conductor layer 110b can include multiple control gates of multiple memory cells and can extend laterally as a word line ending at the edge of memory stack <NUM> (e.g., in a staircase structure of memory stack <NUM>). In some embodiments, memory cell transistors in memory string <NUM> include gate conductors (i.e., parts of conductor layers 110b that abut the channel structure) made from W, adhesion layers (not shown) including titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), gate dielectric layers (not shown) made from high-k dielectric materials, and the channel structure including polysilicon. Bottom conductor layer 110b (e.g., conductor layer 110b that is closest to substrate <NUM>) functions as a bottom select gate and intersects and contacts the channel structure (e.g., memory string <NUM>).

In some embodiments, memory string <NUM> further includes semiconductor plug <NUM> in a lower portion (e.g., at the lower end) of memory string <NUM>. As used herein, the "upper end" of a component (e.g., memory string <NUM>) is the end farther away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., memory string <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of memory device <NUM>. Semiconductor plug <NUM> includes poly-silicon or amorphous silicon, which is deposited on substrate <NUM> in any suitable directions. In some embodiments, the top surface of semiconductor plug <NUM> is lower, e.g., along the vertical direction, than the top surface of bottom conductor layer 110b. Semiconductor plug <NUM> can function as a channel controlled by a source select gate of memory string <NUM>. In some embodiments, conductor layers 110b (e.g., bottom conductor layer 110b) intersect and contact memory string <NUM>.

In some embodiments, memory string <NUM> further includes a top channel plug <NUM> in an upper portion (e.g., at the upper end) of memory string <NUM>. Top channel plug <NUM> can be in contact with the upper end of semiconductor channel 108d. Top channel plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductive materials (e.g., metals). In some embodiments, top channel plug <NUM> includes an opening filled with Ti/TiN or Ta/TaN as an adhesion layer and tungsten as a conductor. By covering the upper end of the channel structure during the fabrication of memory device <NUM>, top channel plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in the channel structure, such as silicon oxide and silicon nitride. In some embodiments, top channel plug <NUM> also functions as the drain of memory string <NUM>. In some embodiments, when top channel plug <NUM> includes polysilicon, a top doped region <NUM> is formed in top channel plug <NUM> to increase conductivity.

As shown in <FIG>, source structure <NUM> may extend vertically through memory stack <NUM> and be conductively connected to substrate <NUM>. Doped semiconductor region 106a may be conductively connected to a heavy doped region/well (e.g., a heavy P-well in substrate <NUM>, not shown) so source conductor 106c can be conductively connected to memory strings <NUM>. Source conductor 106c can include any suitable conductive material such as W, Co, Al, Cu, polysilicon, and/or silicide. Insulating structure 106b can include any suitable dielectric materials such as silicon oxide. In some embodiments, when source conductor 106c includes polysilicon, source plug <NUM> (e.g., a doped region) is formed in the upper portion of source conductor 106c to increase conductivity of source conductor 106c with other devices/circuits.

<FIG> illustrate an exemplary fabrication process to form a lower memory deck, and <FIG> illustrates an exemplary fabrication process to form a memory string with a "SEG-free" semiconductor plug in structures depicted in <FIG>. <FIG> illustrates a flowchart of an exemplary method <NUM> for forming the lower memory deck. <FIG> illustrates a flowchart of an exemplary method <NUM> for forming memory device <NUM>. The fabrication processes are now described in view of the structures shown in <FIG> and <FIG>. It is understood that the operations shown in methods <NUM> and <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>, <FIG>, <FIG> and <FIG>.

As shown in <FIG>, at the beginning of the process, a bottom sacrificial layer is formed over a substrate and a dielectric deck is formed over the bottom sacrificial layer. The dielectric deck includes a plurality of interleaved sacrificial layers and dielectric layers (Operations <NUM> and <NUM>). <FIG> illustrate corresponding structures.

As shown in <FIG>, an initial bottom sacrificial layer <NUM> may be formed over a substrate <NUM>, and an initial dielectric deck <NUM> may be formed over initial bottom sacrificial layer <NUM>. In some embodiments, substrate <NUM> can be a silicon substrate that includes a plurality of doped wells such at the upper portion of substrate <NUM>. For example, the doped wells can include a heavy P-well (HVPW), a deep N-well (DNW), and a heavy N-well (HVNW), as shown in <FIG>. In some embodiments, the HVPW is located under the subsequently-formed memory strings formed in the dielectric deck. In some embodiments, the doped wells can be formed by respective ion implantation processes on substrate <NUM>.

In some embodiments, initial bottom sacrificial layer <NUM> includes a suitable material different from the material of the sacrificial layers of initial dielectric deck <NUM>. The material of initial bottom sacrificial layer <NUM> may have sufficiently high etching selectivity over initial dielectric deck <NUM>. In some embodiments, initial bottom sacrificial layer <NUM> functions as an etch stop layer to stop the etching of initial dielectric deck <NUM>. In some embodiments, initial bottom sacrificial layer <NUM> includes one or more of W, Co, Al, and Cu. Initial bottom sacrificial layer <NUM> may be formed by any suitable deposition process such as sputtering, electron beam evaporation, chemical vapor deposition (CVD), and/or physical vapor deposition (PVD). Optionally, initial bottom sacrificial layer <NUM> can be planarized (e.g., by recess etch and/or chemical mechanical polishing (CMP)) to ensure desirable flatness for initial dielectric deck <NUM> to be formed thereon.

Initial dielectric deck <NUM> can include a first plurality of interleaved initial dielectric layers 210a and initial sacrificial layers 210b. An initial sacrificial layer 210b and its respective initial dielectric layer 210a (e.g., dielectric layer 210a over or under it) can together be referred to herein as an "initial dielectric layer pair. " Initial dielectric layers 210a and initial sacrificial layers 210b can be alternatively deposited on initial bottom sacrificial layer <NUM> to form initial dielectric deck <NUM>. In some embodiments, each initial dielectric layer 210a includes a layer of silicon oxide, and each initial sacrificial layer 210b includes a layer of silicon nitride. In some embodiments, each initial dielectric layer 210a and each initial sacrificial layer 210b have nominally the same thicknesses along the vertical direction. The thickness of initial bottom sacrificial layer <NUM> may be similar to or in a similar range (e.g., between <NUM> and <NUM>). In some embodiments, the thicknesses of initial dielectric layer 210a, initial sacrificial layer 210b, and initial bottom sacrificial layer <NUM> may have nominally the same thickness. Initial dielectric deck <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, atomic layer deposition (ALD), or any combination thereof. In some embodiments, initial bottom sacrificial layer <NUM> and initial dielectric deck <NUM> covers the area of the HVPW on substrate <NUM>.

As shown in <FIG>, a dielectric deck <NUM> can be formed over initial bottom sacrificial layer <NUM>. Dielectric deck <NUM> can be formed by, e.g., repetitively etching the initial dielectric layer pairs along the vertical direction and lateral directions. In some embodiments, an etch mask, e.g., a photoresist layer (not shown), can be patterned over the top surface of initial dielectric deck <NUM>. The etch mask can be repetitively trimmed (e.g., etched) laterally (e.g., along various directions parallel to the lateral/x-y plane) and vertically to expose portions of initial dielectric deck <NUM>. A suitable isotropic etching process (e.g., a wet etch) may be performed to repetitively remove the exposed portions of initial dielectric deck <NUM> along various directions. In some embodiments, initial bottom sacrificial layer <NUM> functions as an etch stop layer such that the etching rate of initial dielectric deck <NUM> is sufficiently higher than the etching rate of initial bottom sacrificial layer <NUM>. When the etching of initial dielectric deck <NUM> is completed, dielectric deck <NUM> may be formed over initial bottom sacrificial layer <NUM>. In some embodiments, dielectric deck <NUM> includes a staircase structure. Initial dielectric layer pairs can be etched to form dielectric layer pairs that each includes a dielectric layer 220a and a sacrificial layer 220b.

As shown in <FIG>, the portion of initial bottom sacrificial layer <NUM> exposed by dielectric deck <NUM> may be removed to form bottom sacrificial layer <NUM> and expose substrate <NUM>. The removal of the exposed portion of initial bottom sacrificial layer <NUM> can include any suitable etching process such as a wet etch or wet clean process. A dielectric filling material can then be deposited over substrate <NUM> and dielectric deck <NUM> and planarized to form a dielectric filling structure <NUM>.

Referring back to <FIG>, a memory string is formed. The memory string extends through the dielectric deck and the bottom sacrificial layer, and contacts the substrate (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures.

As shown in <FIG>, a plurality of openings <NUM> (e.g., channel holes) can be formed to extend through dielectric deck <NUM> to expose bottom sacrificial layer <NUM>, and a layer of a blocking material 230a, a layer of a memory material 230b, a layer of a tunneling material 230c, and a layer of a semiconductor material 230d can be sequentially deposited over a sidewall of opening <NUM>. Because bottom sacrificial layer <NUM> functions as an etch stop layer, a bottom surface of opening <NUM> may expose bottom sacrificial layer <NUM>. Opening <NUM> may be formed by a suitable etching process using a patterned etch mask that exposes areas corresponding to opening <NUM> over dielectric deck <NUM>. In some embodiments, the etching process includes dry etch. Any suitable deposition processes, e.g., CVD, PVD, ALD, and/or sputtering, can be performed to deposit the layers of blocking material 230a, memory material 230b, tunneling material 230c, and semiconductor material 230d.

As shown in <FIG>, a memory string <NUM> can be formed from an opening <NUM> and channel-forming layers (e.g., 230a, 230b, 230c, and 230d) deposited in opening <NUM>. Memory string <NUM> may include a blocking layer 240a, a memory layer 240b, a tunneling layer 240c, a semiconductor layer 240d, and a dielectric core 240e arranged sequentially from the sidewall to the center of opening <NUM>. Memory string <NUM> may also include a channel plug 240f over and conductively connected to these layers, and a semiconductor plug <NUM> at the bottom of memory string <NUM>, conductively connected to these layers and substrate <NUM>. In some embodiments, memory string <NUM> is similar to or the same as memory sub-string <NUM>-<NUM>. The fabrication process of memory string <NUM> is described in detail as follows in view of <FIG>.

Referring back to <FIG>, a support pillar is formed. The support pillar extends through the dielectric deck and the bottom sacrificial layer to contact the substrate (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures.

As shown in <FIG>, a plurality of support pillars <NUM> are formed to extend through dielectric deck <NUM>, dielectric filling structure <NUM> and bottom dielectric layer <NUM>, to contact substrate <NUM>. A support pillar <NUM> includes a pillar hole that extends through dielectric deck <NUM>, dielectric filling structure <NUM>, and bottom dielectric layer <NUM> to expose substrate <NUM>, and a pillar material (e.g., a dielectric material such as silicon oxide) filled in the pillar hole. In some embodiments, a lateral dimension (e.g., diameter) of support pillar <NUM> is less than a lateral dimension (e.g., diameter) of memory string <NUM>. Support pillars <NUM> can be formed by performing a suitable etching process (e.g., a dry etch) using a patterned etch mask that exposes areas corresponding to the pillar holes. In some embodiments, an initial slit structure <NUM> is formed by the same etching process that forms the pillar holes. Initial slit structure <NUM> may extend through dielectric deck <NUM>, dielectric filling structure <NUM> and bottom dielectric layer <NUM> to expose substrate <NUM>. A suitable dielectric material can be deposited to fill up the pillar holes with any suitable deposition process such as CVD, PVD, and/or ALD. A layer of the pillar-filling dielectric material <NUM> can be deposited over a bottom surface and a sidewall of initial slit structure <NUM> and on dielectric deck <NUM>.

Referring back to <FIG>, the bottom sacrificial layer is replaced with an initial bottom dielectric layer that is between the dielectric deck and the substrate (Operation <NUM>). <FIG> illustrates a corresponding structure.

As shown in <FIG>, the portions of pillar-filling dielectric material <NUM> on the sidewall and on the bottom surface of initial slit structure <NUM> can be removed to expose substrate <NUM> and the remaining portion of bottom dielectric layer <NUM> (i.e., the portion of bottom dielectric layer <NUM> retained from the formation of initial slit structure <NUM>). The remaining portion of bottom dielectric layer <NUM> can then be removed. An initial bottom dielectric layer <NUM> can be formed between dielectric deck <NUM> and substrate <NUM>. In some embodiments, initial bottom dielectric layer <NUM> fills up the space between dielectric deck <NUM> and substrate <NUM>, and forms a layer at the bottom of initial slit structure <NUM>.

The portions of pillar-filling dielectric material <NUM> on the sidewall and bottom surface of initial slit structure <NUM> can be removed by covering the top surface of dielectric deck <NUM> with a protective layer and perform a suitable etching process to remove the portions of pillar-filling dielectric material <NUM> on the sidewall and bottom surface of initial slit structure <NUM>. In some embodiments, the protective layer includes polymer, and the etching process includes a dry etch.

A suitable wet etch can be performed to remove bottom sacrificial layer <NUM>. In some embodiments, the wet etch has sufficiently high etching selectivity of bottom sacrificial layer <NUM> over dielectric deck <NUM> and support pillars <NUM> so that little or no damage is formed on the sidewall of initial slit structure <NUM> (or dielectric deck <NUM>). In some embodiments, support pillars <NUM> remain through dielectric filling structure <NUM> and dielectric deck <NUM> to substrate <NUM> after bottom sacrificial layer <NUM> is removed. That is, support pillars <NUM> may support dielectric deck <NUM> on substrate <NUM> during and after the etching of bottom sacrificial layer <NUM>.

After bottom sacrificial layer <NUM> is removed, an initial bottom dielectric layer <NUM> is formed between dielectric deck <NUM> and substrate <NUM>. Initial bottom dielectric layer <NUM> can be formed in a suitable process such as one or more of a "native oxide" method, an "in-situ steam generated (ISSG) oxidation" method, and a silane oxidation method. In some embodiments, the native oxide method includes an oxidation process involving oxygen gas and substrate <NUM> to form a native oxide (e.g., silicon oxide) of substrate <NUM> along the vertical direction until the space formed by the removal of bottom sacrificial layer <NUM> is filled with the native oxide. In some embodiments, the ISSG oxidation method includes a thermal oxidation process involving reactant gases of hydrogen, oxygen, and substrate <NUM> to form silicon oxide along the vertical direction until the space formed by the removal of bottom sacrificial layer <NUM>. In some embodiments, the silane oxidation method includes a thermal oxidation process involving reactant gases of silane (SiH<NUM>) and oxygen to form silicon oxide along the vertical direction until the space formed by the removal of bottom sacrificial layer <NUM>. In some embodiments, initial bottom dielectric layer <NUM> may extend along the top surface of substrate <NUM> and under dielectric deck <NUM>.

Referring back to <FIG>, a source structure is formed to extend through the dielectric deck and into the substrate (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures.

As shown in <FIG>, an initial memory deck <NUM> can be formed. Initial memory deck <NUM> may include a slit structure <NUM> extending through initial memory deck <NUM> and exposing initial bottom dielectric layer <NUM>, a plurality of recessed conductor layers 270b extending laterally on the sidewall of slit structure <NUM>, and a doped semiconductor region <NUM> in the portion of HVPW that is under slit structure <NUM>. In some embodiments, sacrificial layers 220b of dielectric deck <NUM> are replaced with a plurality of conductor layers extending laterally, and a slit structure <NUM> may be formed by performing a recess etch on the conductor layers exposed in initial slit structure <NUM>. In some embodiments, a suitable etching process (e.g., a wet etch) is performed to remove sacrificial layers 220b to form a plurality of lateral recesses on the sidewall of initial slit structure <NUM>, and a suitable deposition process (e.g., CVD, PVD, ALD, and/or sputtering) is performed to deposit a conductive material to fill up the lateral recesses and form a plurality of conductor layers. The conductor layers can include one or more of W, Co, Al, and Cu. In some embodiments, an adhesive layer including Ti and/or TiN can be formed prior to the deposition of the conductor layers between adjacent dielectric layers 220a to increase the adhesion between the conductor layers and adjacent dielectric layers 220b. The recess etch can be performed on the conductor layers to form the plurality of recessed conductor layers 270b.

A plurality of recessed conductor layers 270b and a plurality of recesses 276a abutting the sidewall of slit structure <NUM> are formed by etching parts of the conductor layers of dielectric deck <NUM> that abut the sidewall of initial slit structure <NUM>. In some embodiments, recesses 276a are formed by applying etchants to the conductor layers through initial slit structure <NUM> to completely remove part of the conductor layers along the sidewall of initial slit structure <NUM> and further etch parts of the conductor layers in the lateral recesses. Recessed conductor layers 270b, slit structure <NUM>, and initial memory deck <NUM> can be formed. The dimension of recess 276a can be controlled by the etching rate (e.g., based on the etchant temperature and concentration) and/or etching time. Recessed conductor layers 270b can subsequently function as the gate lines of memory device <NUM>.

Doped semiconductor region <NUM> can be formed by performing an ion implantation process on the portion of initial bottom dielectric layer <NUM> exposed by slit structure <NUM> before or after the formation of recessed conductor layers 270b. Doped semiconductor region <NUM> can subsequently function as a common source of the surrounded memory strings <NUM>. Doped semiconductor region <NUM> may be conductively connected to the surrounded memory strings <NUM> through the HVPW.

As shown in <FIG>, a source structure <NUM> is formed in slit structure <NUM> and a memory deck <NUM> can be formed. Source structure <NUM> may include an insulating structure 286b (e.g., a spacer) along a sidewall of slit structure <NUM> to cover recessed conductor layers 270b and electrically separate recessed conductor layers 270b of the memory stack. In some embodiments, insulating structure 286b includes a dielectric material is formed along the sidewall of slit structure <NUM> and in recesses 276a using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Insulating structure 286b can include a single or composite layer of dielectric materials, such as silicon oxide and silicon nitride. By covering the sidewall of slit structure <NUM> as well as filling in recesses 276a with insulating structure 286b, recessed conductor layers 270b (e.g., gate lines) of memory deck <NUM> can be electrically separated by insulating structures 286b.

A source contact 286a is formed in insulating structure 286b and through initial bottom dielectric layer <NUM> in slit structure <NUM>. Source contact 286a may be in contact with doped semiconductor region <NUM> and may be conductively connected to the surrounded memory strings <NUM> through doped semiconductor region <NUM>. A suitable etching process (e.g., dry etch) can be performed to remove a portion of initial bottom dielectric layer <NUM> to expose doped semiconductor region <NUM>. Source contact 286a can be formed by depositing a suitable conductive material over insulating structure 286b. The conductive materials may include, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Source contact 286a can act as an array common source (ACS) contact electrically connected to the channel structures of surrounded memory strings <NUM>. Source structure <NUM> including insulating structure 286b and source contact 286a can thereby be formed in slit structure <NUM>, surrounded by a plurality of memory strings <NUM>. In some embodiments, a planarization process (e.g., CMP and/or recess etch) can be performed to remove any excessive conductive material that forms source contact 286a and/or dielectric material that forms insulating structure 286b. An insulating cap layer <NUM> can be formed over memory deck <NUM>. In some embodiments, insulating cap layer <NUM> provides the base for other devices/structures (e.g., another memory deck) to be formed over memory deck <NUM>.

<FIG> illustrates operations A-H for forming a memory string <NUM> with a semiconductor plug <NUM>, according to some embodiments. For ease of illustration, layers of tunneling material and semiconductor material, i.e., 230c and 230d, are shown as one single layer in operations A-E, and tunneling layer 240c and semiconductor layer 240d are shown as one single layer in operations F-H. In some embodiments, a layer of semiconductor material 230d is deposited over layer of tunneling material 230c, and semiconductor layer 240d is over tunneling layer 240c.

As shown in <FIG>, in operation A, channel-forming layers, e.g., a layer of a blocking material 230a, a layer of a memory material 230b, a layer of a tunneling material 230c, and a layer of a semiconductor material 230d may be sequentially deposited over the sidewall of opening <NUM> in dielectric deck <NUM>. In operation B, an initial plug opening 234a may be formed through layers of blocking material, memory material, tunneling material, and semiconductor material (i.e., 230a, 230b, 230c, and 230d) to expose bottom sacrificial layer <NUM>. A suitable dry etching process can be performed to remove portions of the channel-forming layers. In operation C, a plug opening <NUM> can be formed. Plug opening <NUM> can be formed by enlarging or expanding initial plug opening 234a to vertically and laterally remove materials surrounding initial plug opening 234a. Plug opening <NUM> can be through bottom sacrificial layer <NUM> and can expose the HVPW under bottom sacrificial layer <NUM>. In some embodiments, a suitable etching process (e.g., wet etch) is performed to remove lower portions of layers of blocking material, memory material, tunneling material, and semiconductor material (i.e., 230a, 230b, 230c, and 230d) and the portion of bottom sacrificial layer <NUM> under initial plug opening 234a. The etching process may be isotropic so that the materials surrounding initial plug opening 234a are removed vertically and laterally until the desired dimensions of plug opening <NUM> are reached and/or the HVPW is exposed. In some embodiments, plug opening <NUM> is under layers of blocking material, memory material, tunneling material, and semiconductor material (i.e., 230a, 230b, 230c, and 230d) and exposing HVPW of substrate <NUM>. In some embodiments, the sidewalls of plug opening <NUM> laterally expands into layer of blocking material 230a. In some embodiments, a top surface of plug opening <NUM> is below a top surface of the initial bottom sacrificial layer 210b (i.e., the sacrificial layer directly above and in contact of bottom sacrificial layer <NUM>). In operation D, another layer of the semiconductor material (e.g., polysilicon) can be deposited over a layer of semiconductor material 230d and fill up plug opening <NUM>. Semiconductor plug <NUM> can be formed. Any suitable deposition process, e.g., CVD, PVD, ALD, and/or sputtering, can be employed to form semiconductor plug <NUM>. Optionally, the deposition process can form air gaps <NUM> in semiconductor plug <NUM>. Semiconductor plug <NUM> may be conductively connected to a layer of semiconductor material 230d and HVPW.

At operation E, a layer of a dielectric core material 230e can be deposited, employing any suitable deposition methods such as CVD, PVD, ALD, and/or sputtering, to fill up opening <NUM>. At operation F, a suitable planarization process (e.g., CMP and/or recess etch) can be performed to remove layers of the dielectric core material 230e, and layers of semiconductor material 230d and tunneling material 230c so that layer of memory material 230b can be exposed. At operation G, upper portions of layers of memory material, tunneling material, semiconductor material, and dielectric core material (i.e., 230b, 230c, 230d, and 230e) can be removed to form a channel-plug opening, e.g., by a suitable etching process (e.g., dry etch and/or wet etch), and a layer of conductive material <NUM> is deposited to fill up the channel-plug opening. Layer of conductive material <NUM> may be deposited using any suitable deposition methods such as CVD, PVD, ALD, and/or sputtering. The etched layers of memory material, tunneling material, semiconductor material, and dielectric core material (i.e., 230b, 230c, 230d, and 230e) can then form memory layer 240b, tunneling layer 240c, semiconductor layer 240d, and dielectric core 240e. The layer of blocking material 230a can form blocking layer 240a. At operation H, a planarization process (e.g., CMP and/or recess etch) can be performed to remove excess portions of conductive material <NUM> over dielectric deck <NUM> to form channel plug 240f. Memory string <NUM>, including blocking layer 240a, memory layer 240b, tunneling layer 240c, semiconductor layer 240d, channel plug 240f, and semiconductor plug <NUM>, can be formed. A layer of insulating material can be deposited to cover memory string <NUM>. A planarization process (e.g., CMP and/or recess etch) can be performed to remove excessive portions of the insulating material and form insulating cap layer <NUM> over dielectric deck <NUM>.

<FIG> illustrates a flowchart to form an exemplary 3D memory device (e.g., memory device <NUM>) having a plurality of memory decks stacking along the vertical direction, according to some embodiments. For ease of illustration, the fabrication process of memory device <NUM>, having a lower memory deck (e.g., a first memory deck) and an upper memory deck (e.g., a second memory deck), is described as an example. The operations described in <FIG> and <FIG> illustrate the fabrication process to form the lower memory deck 104A (e.g., first memory deck) from a first dielectric deck <NUM>. The operations described in <FIG> illustrate the fabrication process to form an upper memory deck 104B (e.g., the second memory deck) from a second dielectric deck. The operations to form more memory decks over the upper memory deck should be similar to the processes to form the lower and the upper memory decks and are not repeated herein. As used herein, the lower and upper memory decks can each be referred to as a memory deck of memory device <NUM>, and the memory strings (e.g., <NUM>-<NUM> and <NUM>-<NUM>) in each memory deck can each be referred to as memory sub-strings.

At the beginning of the fabrication process, at operations <NUM> and <NUM>, a bottom sacrificial layer may be formed over a substrate, and a first dielectric deck having a plurality of interleaved sacrificial layers and dielectric layers can be formed over the bottom sacrificial layer. The fabrication process can be similar to or the same as the fabrication process illustrated in <FIG>. In some embodiments, the first dielectric deck is fabricated to subsequently form first memory deck 104A. At operation <NUM>, a first memory string, extending through the first dielectric deck and the bottom sacrificial layer and contacting the substrate, can be formed. The fabrication process can be similar to or the same as the fabrication process illustrated in <FIG> and <FIG>. In some embodiments, the first memory string (e.g., a memory sub-string) corresponds to memory sub-string <NUM>-<NUM> and includes a channel plug (e.g., 108f) at the upper portion, a semiconductor plug <NUM> at the lower portion and conductively connected to the substrate, and a semiconductor channel conductively connected to semiconductor plug <NUM> and channel plug 108f.

At operation <NUM>, a second dielectric deck having a plurality of second interleaved sacrificial layers and dielectric layers can be formed over the first dielectric deck. The formation of the second dielectric deck can be the same as or similar to the formation of the first dielectric deck. In some embodiments, the second dielectric deck is fabricated to subsequently form second memory deck 104B. At operation <NUM>, a second memory string, extending through the second dielectric deck and connecting with the first memory string, can be formed. In some embodiments, the second memory string corresponds to memory sub-string <NUM>-<NUM>, which is aligned with memory sub-string <NUM>-<NUM> along the vertical direction. The fabrication process can be similar to or the same as the fabrication process illustrated in <FIG>. Different from the fabrication process shown in <FIG>, no semiconductor plug is formed in second memory deck 104B, and the semiconductor channel of the second memory string is conductively connected to the channel plug of the first memory string.

At operation <NUM>, the bottom sacrificial layer can be replaced with a bottom dielectric layer between the first dielectric deck and the substrate. The fabrication process can be similar to or the same as the fabrication process illustrated in <FIG>. In some embodiments, an initial slit structure is formed extending through the first and second dielectric decks to expose the substrate, e.g., for the replacement of bottom sacrificial layer and subsequent operations. At operation <NUM>, a source structure, extending through the first and the second memory decks and into the substrate, can be formed. In some embodiments, the plurality of first and second sacrificial layers are replaced with a plurality of conductor layers before the formation of the source structure. The first dielectric deck and the second dielectric deck can respectively form the first memory deck (e.g., 104A) and the second memory deck (e.g., 104B). The fabrication process to form the conductor layers, the first and the second memory decks, and the source structure can be similar to or the same as the fabrication process illustrated in <FIG>. In some embodiments, a top doped region (e.g., <NUM>) and/or a source plug (e.g., <NUM>) are respectively formed in the upper portions of channel plug (e.g., <NUM>) and source plug <NUM> by a suitable ion implantation and/or a deposition of a conductive material in a recessed portion of the channel plug and the source conductor.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional, 3D, memory device (<NUM>), comprising:
a substrate (<NUM>);
(i) a memory deck (104A) comprising a plurality of interleaved conductor layers (110b) and dielectric layers (110a) on top of the substrate (<NUM>); and a memory string (<NUM>) extending vertically through the memory deck (104A),
or
(ii) a memory stack (<NUM>) comprising a plurality of memory decks (104A, 104B) each having a plurality of interleaved conductor layers (110b) and dielectric layers (110a) over the substrate (<NUM>); and a memory string (<NUM>) having a plurality of memory sub-strings (<NUM>-<NUM>, <NUM>-<NUM>) extending vertically through the memory stack (<NUM>), each memory deck (104A, 104B) having a respective memory sub-string (<NUM>-<NUM>, <NUM>-<NUM>),
and wherein according to (i) or (ii):
- a bottom conductor layer (110b) of the plurality of interleaved conductor layers (110b) and dielectric layers (110a) that is a layer of conductive material closest to the substrate (<NUM>) intersects with and contacts the memory string (<NUM>) and serves as a bottom select gate of the memory string (<NUM>);
- a semiconductor plug (<NUM>) is connected to the substrate (<NUM>) at a lower portion of the memory string (<NUM>), wherein the memory string (<NUM>) comprises a semiconductor channel (108d) along a sidewall of the memory string (<NUM>) and extending along the memory string (<NUM>) to contact the semiconductor plug (<NUM>);
wherein a top surface of the semiconductor plug (<NUM>) is lower than a top surface of the bottom conductor layer (110b);
wherein the semiconductor plug (<NUM>) is a deposited poly-silicon or amorphous silicon plug.