Patent Description:
A bipolar junction transistor is a three-terminal electronic device that includes an emitter, a collector, and an intrinsic base defining respective junctions with the emitter and collector. In a PNP bipolar junction transistor, the emitter and collector are comprised of p-type semiconductor material, and the intrinsic base is comprised of n-type semiconductor material. In an NPN bipolar junction transistor, the emitter and collector are comprised of n-type semiconductor material, and the intrinsic base is comprised of p-type semiconductor material. In operation, the base-emitter junction is forward biased, the base-collector junction is reverse biased, and the collector-emitter current may be controlled with the base-emitter voltage.

A heterojunction bipolar transistor is a variant of a bipolar junction transistor in which the semiconductor materials have different energy bandgaps, which creates heterojunctions. For example, the collector and emitter of a heterojunction bipolar transistor may be constituted by silicon, and the intrinsic base of a heterojunction bipolar transistor may be constituted by silicon-germanium, which is characterized by a narrower band gap than silicon. Heterojunction bipolar transistors may exhibit improvements in high frequency performance as a result of the introduction of heterojunctions.

A resistive random-access memory device provides one type of embedded non-volatile memory technology. A bitcell of a resistive random-access memory device includes a resistive memory element and an access transistor that controls operations used to write, erase, and read the resistive memory element. Because resistive memory elements are non-volatile, bits of data are retained as stored content by the resistive memory elements when the resistive random-access memory device is not powered. The non-volatility of a resistive random-access memory device contrasts with volatile memory technologies, such as a static random-access memory device in which the stored content is eventually lost when unpowered and a dynamic random-access memory device in which the stored content is lost unless periodically refreshed.

Field-effect transistors are commonly used as access transistors in a resistive random-access memory device. Reliable operation of the bitcell of a resistive random-access memory device imposes restrictions on the field-effect transistors. For example, the minimum voltage and drive current requirements imposed on the field-effect transistors restrict the ability to shrink the bitcell dimensions. As a result, the scalability of the bitcell is restricted.

<CIT> describes a memory device comprising programmable resistive elements which are connected to an emitter or a collector of corresponding bipolar transistors. Further, <CIT> describes a memory device comprising programmable resistance elements which are coupled to heterojunction bipolar transistors. Further, <CIT> describes a memory device comprising memory stack, collector, base and emitter layers that are patterned into pillars. Further, <CIT> describes a phase change memory device comprising a plurality of unit memory cells, wherein each unit memory cell comprises a resistance variable element and a diode as switching element. Still further, <CIT> describes a device structure comprising a vertically arranged high performance and a vertically arranged high breakdown transistor.

Improved structures that include bipolar junction transistors and methods of forming such structures are needed.

According to an embodiment of the invention, a structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

The structure further comprises a first well in the substrate, and a second well in the substrate, wherein the first collector is a portion of the first well, and the second collector is a portion of the second well. Moreover, the first trench isolation region of the structure may be positioned in the substrate between the first well and the second well.

The structure further comprises a third well in the substrate. The third well has an opposite conductivity type from the first well and the second well, wherein the first well and the second well are positioned between the third well and the top surface of the substrate, and the first trench isolation region penetrates into the third well. Optionally, the first well may adjoin the third well, and the second well may adjoin the third well.

The first well, the second well, the first emitter, and the second emitter of the structure may have p-type conductivity. The first base layer may have n-type conductivity. Additionally or alternatively, the first base layer may be a strip comprising a semiconductor material, and the first well and the second well may be longitudinally aligned orthogonal to the strip.

The above structure may further comprise a second trench isolation region in the substrate; and a second base layer on the top surface of the substrate, the second base layer extending across the second trench isolation region.

The above structure may further comprise: a third bipolar junction transistor including a third collector in the substrate and a third emitter on a first portion of the second base layer, the first portion of the second base layer positioned between the third collector and the third emitter; and/or a fourth bipolar junction transistor including a fourth collector in the substrate and a fourth emitter on a second portion of the second base layer, the second portion of the second base layer positioned between the fourth collector and the fourth emitter.

The first base layer may be a first strip comprising a semiconductor material, the second base layer may be a second strip comprising the semiconductor material, and the second strip may be longitudinally aligned parallel to the first strip. Additionally, the first base layer and the second base layer may comprise silicon-germanium including an n-type dopant.

The first well may be aligned orthogonal to the first base layer and the second base layer, and the second well may be aligned orthogonal to the first base layer and the second base layer.

The above structure may further comprise: a first memory element connected to the first emitter of the first bipolar junction transistor; and a second memory element connected to the second emitter of the second bipolar junction transistor. Optionally, the first memory element and the second memory element may each include a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode.

Additionally, the structure may further comprise an interconnect structure over the first bipolar junction transistor and the second bipolar junction transistor. The interconnect structure may include a plurality of dielectric layers in a layer stack. The first memory element and the second memory element may be positioned in the interconnect structure.

The first trench isolation region of the structure may be coplanar with the top surface of the substrate. Additionally or alternatively, the first base layer may include a third portion longitudinally arranged between the first portion and the second portion, and the third portion of the first base layer may overlap with the first trench isolation region. Optionally, the third portion of the first base layer may directly contact the first trench isolation region.

According to an embodiment of the invention, a method comprises forming a first well and a second well in a substrate; forming a third well in the substrate, the third well having an opposite conductivity type from the first well and the second well, wherein the first well and the second well are positioned between the third well and a top surface of the substrate; forming a trench isolation region in the substrate, wherein the trench isolation region penetrates into the third well, and forming a base layer on the top surface of the substrate. The base layer extends across the trench isolation region. The method further comprises forming a first bipolar junction transistor including a first collector in the substrate and a first emitter on a first portion of the base layer, and forming a second bipolar junction transistor including a second collector in the substrate and a second emitter on a second portion of the base layer. The first portion of the base layer is positioned between the first collector and the first emitter, and the second portion of the base layer is positioned between the second collector and the second emitter, and the first collector is a portion of the first well, and the second collector is a portion of the second well.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

With reference to <FIG>, <FIG>, <FIG>, <FIG> and in accordance with embodiments of the invention, a structure <NUM> for a resistive random-access memory device includes an array of bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> that may be fabricated using a substrate <NUM>. The substrate <NUM> may be comprised of a semiconductor material, such as silicon, and the substrate <NUM> may be lightly doped with a p-type dopant. In an embodiment, the substrate <NUM> may be a hybrid region of a silicon-on-insulator substrate from which the device layer and buried oxide layer have been removed. Field-effect transistors (not shown) may be formed using the device layer in a region of the silicon-on-insulator substrate different from the region including the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>.

Wells <NUM>, <NUM> may be formed as doped regions in the substrate <NUM>. In an embodiment, the wells <NUM>, <NUM> may be located adjacent to a top surface <NUM> of the substrate <NUM>. In an embodiment, the wells <NUM>, <NUM> may longitudinally extend as stripes of doped semiconductor material, and the wells <NUM>, <NUM> may be aligned along respective longitudinal axes <NUM>, <NUM>, which may be oriented parallel to each other. The wells <NUM>, <NUM> may be contacted at an edge of the transistor array.

The wells <NUM>, <NUM> may be formed in the substrate <NUM> by introducing a dopant by, for example, ion implantation with given implantation conditions. A patterned implantation mask may be formed to define selected areas that are exposed for the implantation of ions. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form openings exposing the selected areas and determining, at least in part, the location and horizontal dimensions of the wells <NUM>, <NUM>. The implantation mask has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the wells <NUM>, <NUM>. In an embodiment, the wells <NUM>, <NUM> may be doped with a concentration of a p-type dopant (e.g., boron) such that the wells <NUM>, <NUM> have p-type conductivity.

A well <NUM> may be positioned in the substrate <NUM> beneath the wells <NUM>, <NUM>. The wells <NUM>, <NUM> may be positioned in a vertical direction between the well <NUM> and the top surface <NUM> of the substrate <NUM>. The well <NUM> may have an opposite conductivity type from the wells <NUM>, <NUM>, and may electrically isolate the wells <NUM>, <NUM> from the portion of the substrate <NUM> beneath the well <NUM>. In an embodiment, the well <NUM> may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the well <NUM> has n-type conductivity.

The well <NUM> may be formed by introducing a dopant by, for example, ion implantation into the substrate <NUM>. A patterned implantation mask may be formed to define a selected area on the top surface <NUM> of the substrate <NUM> that is exposed for the implantation of ions. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form an opening exposing the selected area on the top surface <NUM> of the substrate <NUM> and determining, at least in part, the location and horizontal dimensions of the well <NUM>. The implantation mask has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the well <NUM>.

Trench isolation regions <NUM> may be positioned in the substrate <NUM>. In an embodiment, the trench isolation regions <NUM> have a top surface that may be coplanar or substantially coplanar with the top surface <NUM> of the substrate <NUM>. The trench isolation regions <NUM> may be formed by patterning shallow trenches with lithography and etching processes, depositing a dielectric material, such as silicon dioxide, to fill the shallow trenches, and planarizing and/or recessing the dielectric material. One of the trench isolation regions <NUM> is positioned between the well <NUM> and the well <NUM> to electrically isolate the well <NUM> from the well <NUM>. The trench isolation regions <NUM> may penetrate into the well <NUM>.

Base layers <NUM>, <NUM> are formed on the substrate <NUM> and the trench isolation regions <NUM>. In an embodiment, the base layers <NUM>, <NUM> may be laterally-spaced strips that are longitudinally aligned orthogonal to the wells <NUM>, <NUM> and intersect the wells <NUM>, <NUM> at different locations. The base layers <NUM>, <NUM> may extend across the trench isolation region <NUM> between the wells <NUM>, <NUM>. The bipolar junction transistor <NUM> includes an intrinsic base represented by a portion of the base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the underlying adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The bipolar junction transistor <NUM> includes an intrinsic base represented by a portion of the base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the underlying adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The bipolar junction transistor <NUM> includes an intrinsic base represented by a portion of the base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the underlying adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The bipolar junction transistor <NUM> includes an intrinsic base represented by a portion of the base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the underlying adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The base layers <NUM>, <NUM> may be contacted at an edge of the transistor array. The portions of the base layers <NUM>, <NUM> and the respective adjoined portions of the wells <NUM>, <NUM> may define p-n junctions.

A portion of the base layer <NUM> may overlap with the trench isolation region <NUM> that is longitudinally positioned along the length of the base layer <NUM> between the respective portions of the base layer <NUM> representing the intrinsic bases of the bipolar junction transistor <NUM> and the bipolar junction transistor <NUM>. In an embodiment, this portion of the base layer <NUM> may directly contact the trench isolation region <NUM>. A portion of the base layer <NUM> may overlap with the trench isolation region <NUM> that is longitudinally positioned along the length of the base layer <NUM> between the respective portions of the base layer <NUM> representing the intrinsic bases of the bipolar junction transistor <NUM> and the bipolar junction transistor <NUM>. In an embodiment, this portion of the base layer <NUM> may directly contact the trench isolation region <NUM>.

The base layers <NUM>, <NUM> may be formed depositing and patterning a semiconductor layer with lithography and etching processes to define strips of semiconductor material. In an embodiment, the base layers <NUM>, <NUM> may be comprised of a semiconductor material that is doped to have an opposite conductivity type from the doped regions providing the wells <NUM>, <NUM>. In an embodiment, the base layers <NUM>, <NUM> may be comprised of silicon. In an embodiment, the base layers <NUM>, <NUM> may be comprised of silicon-germanium. In an embodiment, the base layers <NUM>, <NUM> may be comprised of silicon-germanium containing a germanium content of less than or equal to than <NUM> atomic percent and the balance silicon. In an embodiment, the base layers <NUM>, <NUM> may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the base layers <NUM>, <NUM> have n-type conductivity. The base layers <NUM>, <NUM> may be aligned along respective longitudinal axes <NUM>, <NUM>, which may be oriented parallel to each other and orthogonal to the longitudinal axes <NUM>, <NUM> of the wells <NUM>, <NUM>.

The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins a portion of the base layer <NUM> along an interface defining a p-n junction. The adjoined underlying portion of the base layer <NUM> is positioned between the well <NUM> and the emitter <NUM>. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins a portion of the base layer <NUM> along an interface defining a p-n junction. The adjoined underlying portion of the base layer <NUM> is positioned between the well <NUM> and the emitter <NUM>. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins a portion of the base layer <NUM> along an interface defining a p-n junction. The adjoined underlying portion of the base layer <NUM> is positioned between the well <NUM> and the emitter <NUM>. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins a portion of the base layer <NUM> along an interface defining a p-n junction. The adjoined underlying portion of the base layer <NUM> is positioned between the well <NUM> and the emitter <NUM>.

The emitters <NUM>, <NUM>, <NUM>, <NUM> may be respectively formed as raised semiconductor layers on the base layers <NUM>, <NUM> at the intersections between the base layers <NUM>, <NUM> and the wells <NUM>, <NUM>. Respective portions of the base layers <NUM>, <NUM> defining the intrinsic bases are positioned in a vertical direction between the portions of the wells <NUM>, <NUM> defining the collectors and the emitters <NUM>, <NUM>, <NUM>, <NUM>. The emitters <NUM>, <NUM>, <NUM>, <NUM> may be formed by epitaxially growing semiconductor material with a non-selective epitaxial growth process and patterning the semiconductor material with lithography and etching processes. In an embodiment, the semiconductor material of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be doped to have the same conductivity type as the wells <NUM>, <NUM> and an opposite conductivity type from the base layers <NUM>, <NUM>. In an embodiment, the semiconductor material of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be doped with a concentration of a p-type dopant (e.g., boron) such that the emitters <NUM>, <NUM>, <NUM>, <NUM> have p-type conductivity. In an embodiment, the emitters <NUM>, <NUM>, <NUM>, <NUM> may have respective lower portions adjacent to the base layers <NUM>, <NUM> that are lightly doped and respective upper portions that are heavily doped.

Spacers <NUM> may be arranged on sidewalls of the emitters <NUM>, <NUM>, <NUM>, <NUM> and the base layers <NUM>, <NUM>. The spacers <NUM> may be formed by conformally depositing a layer comprised of a dielectric material and etching the deposited layer with an anisotropic etching process. The spacers <NUM> may be comprised of a dielectric material that is an electrical insulator, such as silicon nitride or a low-k dielectric material characterized by a dielectric constant less than the dielectric constant of silicon nitride. Caps <NUM>, which be sections of a hardmask used to pattern the emitters <NUM>, <NUM>, <NUM>, <NUM>, may be positioned on the top surface of each of the emitters <NUM>, <NUM>, <NUM>, <NUM>. The caps <NUM> may be comprised of a dielectric material, such as silicon nitride, that is an electrical insulator.

Raised semiconductor layers <NUM> are formed on the sections of the base layers <NUM>, <NUM> that are not covered by the emitters <NUM>, <NUM>, <NUM>, <NUM> and spacers <NUM>. The raised semiconductor layers <NUM> may be formed by epitaxially growing a semiconductor material (e.g., single-crystal silicon) and then patterning the semiconductor material. In an embodiment, the semiconductor material of the raised semiconductor layers <NUM> may be doped to have the same conductivity type as the base layers <NUM>, <NUM>. In an embodiment, the semiconductor material of the raised semiconductor layers <NUM> may be doped (e.g., heavily doped) with a concentration of an n-type dopant (e.g., phosphorus or arsenic) such that the semiconductor layers <NUM> have n-type conductivity. A silicide layer (not shown) may be formed on the raised semiconductor layers <NUM>, as well as on the emitters <NUM>, <NUM>, <NUM>, <NUM> after removing the caps <NUM>.

The structure <NUM> may formed in a BiCMOS process flow with a minimal number of added masks. For example, the formation of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be shared with the formation of the gates of field-effect transistors formed on the same chip as the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. The bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>, which have a vertical arrangement of p-n junctions, may have a more compact size than field-effect transistors, which may permit downward scaling in the dimensions of an associated resistive random-access memory device due to the elimination of field-effect transistors as access transistors.

With reference to <FIG>, <FIG> in which like reference numerals refer to like features in <FIG> and at a fabrication stage subsequent to <FIG>, an interconnect structure may be formed over the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. The interconnect structure may include dielectric layers <NUM>, <NUM>, <NUM> arranged in a layer stack defining multiple metallization levels. The dielectric layers <NUM>, <NUM>, <NUM> may be comprised of a dielectric material that is an electrical insulator, such as silicon dioxide or a low-k dielectric material. The dielectric material of the dielectric layer <NUM> may fill the space between the base layers <NUM>, <NUM> and the spaces around the emitters <NUM>, <NUM>, <NUM>, <NUM>.

Resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may be formed as representative non-volatile memory elements in the interconnect structure. The resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> are respectively coupled to the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> to define different bitcells of the resistive random-access memory device, and the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> provide access transistors for accessing the bitcells. The well <NUM> may define a word line of the resistive random-access memory device for accessing the bipolar junction transistors <NUM>, <NUM>, and the well <NUM> may define another word line of the resistive random-access memory device for accessing the bipolar junction transistors <NUM>, <NUM>. The wells <NUM>, <NUM> may be connected by a bus to peripheral circuits that include, for example, word line drivers. The base layers <NUM>, <NUM> may define bit lines of the resistive random-access memory device. The base layers <NUM>, <NUM> may be connected by a bus to peripheral circuits that include, for example, bit line drivers, a multiplexer, and a sense amplifier. The bit lines defined by the base layers <NUM>, <NUM> may be aligned orthogonal to the word lines defined by the wells <NUM>, <NUM>, which enables connections to be established at edges of the array to the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> for reading, writing, and erasing the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>.

The resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may arranged in an array that is characterized by rows and columns and that may be spatially coordinated with the array of bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. Each of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> includes a bottom electrode <NUM>, a top electrode <NUM>, and a switching layer <NUM> positioned between the bottom electrode <NUM> and the top electrode <NUM>. The bottom electrodes <NUM> may define respective cathodes of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>, and the top electrodes <NUM> may define respective anodes of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>. Each bottom electrode <NUM> comprised of a metal, such as tantalum, titanium nitride, tantalum nitride, or a combination thereof. Each switching layer <NUM> may be comprised of a metal oxide, such as hafnium oxide, magnesium oxide, tantalum oxide, titanium oxide, or aluminum oxide, or a dielectric material, such as silicon nitride or silicon dioxide. Each top electrode <NUM> may be comprised of a metal, such as tungsten, titanium nitride, tantalum nitride, or platinum. The interconnect structure may include vertical interconnections <NUM> defined by a stack of contacts, via plugs, and metal features that physically and electrically connect the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, and the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>. The vertical interconnections <NUM> may also include contacts coupled to the wells <NUM>, <NUM> at an edge of the array and contacts coupled to the silicide layer on the raised semiconductor layers <NUM> on the base layers <NUM>, <NUM> at another edge of the array.

The structure <NUM> for the resistive random-access memory device may be expanded to include additional bipolar junction transistors and additional resistive memory elements. In that regard, the expanded array may include additional wells arranged adjacent to the wells <NUM>, <NUM>, additional base lines arranged adjacent to the base layers <NUM>, <NUM>, and additional emitters at the intersections of the additional base lines and additional wells. The number of resistive memory elements in the expanded array may be increased commensurate with the increased number of bipolar junction transistors. In an alternative embodiment, the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may be replaced by different non-volatile memory elements, such as magnetoresistive memory elements.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/- <NUM>% of the stated value(s).

References herein to terms such as "vertical", "horizontal", etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction in the frame of reference within the horizontal plane.

A feature "connected" or "coupled" to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or with another feature if intervening features are absent. A feature may be "indirectly connected" or "indirectly coupled" to or with another feature if at least one intervening feature is present. A feature "on" or "contacting" another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be "directly on" or in "direct contact" with another feature if intervening features are absent. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present. Different features may "overlap" if a feature extends over, and covers a part of, another feature.

Claim 1:
A structure (<NUM>) comprising:
a substrate (<NUM>) having a top surface (<NUM>);
a first trench isolation region (<NUM>) in the substrate (<NUM>);
a first base layer (<NUM>, <NUM>) on the top surface (<NUM>) of the substrate (<NUM>), the first base layer (<NUM>, <NUM>) extending across the first trench isolation region (<NUM>);
a first bipolar junction transistor (<NUM>, <NUM>, <NUM>, <NUM>) including a first collector in the substrate (<NUM>) and a first emitter (<NUM>, <NUM>, <NUM>, <NUM>) on a first portion of the first base layer (<NUM>, <NUM>), the first portion of the first base layer (<NUM>, <NUM>) positioned between the first collector and the first emitter (<NUM>, <NUM>, <NUM>, <NUM>);
a second bipolar junction transistor (<NUM>, <NUM>, <NUM>, <NUM>) including a second collector in the substrate (<NUM>) and a second emitter (<NUM>, <NUM>, <NUM>, <NUM>) on a second portion of the first base layer (<NUM>, <NUM>), the second portion of the first base layer (<NUM>, <NUM>) positioned between the second collector and the second emitter (<NUM>, <NUM>, <NUM>, <NUM>);
a first well (<NUM>, <NUM>) in the substrate (<NUM>), and a second well (<NUM>, <NUM>) in the substrate (<NUM>), wherein the first collector is a portion of the first well (<NUM>, <NUM>),
and the second collector is a portion of the second well (<NUM>, <NUM>); and
a third well (<NUM>) in the substrate (<NUM>), the third well (<NUM>) having an opposite conductivity type from the first well (<NUM>) and the second well (<NUM>),
wherein the first well (<NUM>, <NUM>) and the second well (<NUM>, <NUM>) are positioned between the third well (<NUM>) and the top surface (<NUM>) of the substrate (<NUM>), and the first trench isolation region (<NUM>) penetrates into the third well (<NUM>).