Patent Description:
Embodiments of the present disclosure relate to an array substrate and a display device.

In a display panel, for example, in a liquid crystal display panel of an ADS display mode, in order to better avoid the influence of signal lines such as data lines and gate lines on the operation of pixel electrodes, an insulating layer for example is added between the pixel electrodes and the signal lines such as the data lines and the gate lines; the insulating layer is usually required to have a certain thickness for the purpose of reducing the above-mentioned influence, and this increases a thickness of the display panel, and is disadvantageous for thinning the display panel and a display device. <CIT> provides an array substrate; the array substrate includes a substrate, a plurality of data lines on the substrate, a plurality of scan lines on the substrate, a pixel electrode on the substrate, a shielding common electrode on the substrate, a data test part on the substrate and a shielding common electrode pad on the substrate; the pixel electrode is in a region defined by the data and scan lines adjacent to each other; the shielding common electrode surrounds the pixel electrode; the data test part applies test data voltage to the data lines; a shielding common voltage that has different level from the test data voltage is applied to the shielding common electrode through the shielding common electrode pad. <CIT> provides a display device. The display device includes: a gate line; first and second adjacent data lines intersecting the gate line; a first sub-pixel electrode between the first and second data lines; a second sub-pixel electrode between the first gate line and the first sub-pixel electrode; a first switching element connected to the first gate line, the first data line and the first sub-pixel electrode; a second switching element connected to the first gate line, the first data line and the second sub-pixel electrode; a connection electrode connecting the first sub-pixel electrode and the first switching element; a first dummy electrode between the first data line and the second sub-pixel electrode; and a second dummy electrode extending from the connection electrode and disposed closer to the first data line than the second data line. End portions of the first and second dummy electrodes face each other. <CIT> provides a liquid crystal display device. The liquid crystal display device includes: a first substrate; a shielding electrode disposed on the first substrate and extends in a first direction; a pixel electrode disposed on a same layer as the shielding electrode and insulated from the shielding electrode; a common electrode which overlaps the shielding electrode and the pixel electrode in a thickness direction of the first substrate; and a liquid crystal layer interposed between the common electrode and the pixel and shielding electrodes. The liquid crystal layer includes a first liquid crystal molecule disposed in a first region between the shielding electrode and the pixel electrode, and the first liquid crystal molecule is pre-tilted to have an azimuthal angle in a range of about zero degree to about +<NUM> degrees or in a range of about -<NUM> degrees to about zero degree, based on the first direction. <CIT> provides a liquid display device. The liquid crystal display device includes a first base substrate; a first signal line disposed on the first base substrate and extended in a first direction; a second signal line disposed on the first base substrate, extended in a second direction intersecting the first direction, and insulated from the first signal line; a thin film transistor disposed on the first base substrate and electrically connected to the first signal line and the second signal line; a pixel electrode electrically connected to the thin film transistor; and a shield pattern disposed on a same layer as but spaced apart from the pixel electrode, overlapped with the thin film transistor, and including a material same as a material of the pixel electrode. <CIT> discloses an array substrate and a display device.

It is an object of the present invention to provide an array substrate and a display device, which may solve one or more problems in the art.

The object is achieved by the features of independent claim <NUM>. Further embodiments are defined in the respective dependent claims <NUM>-<NUM>.

In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative of the disclosure. In the following description, it will be referred to "embodiments of the disclosure" a plurality of times, it should be noted however that only <FIG> illustrates an embodiment according to the claimed invention requiring hollow regions (<NUM>) included in at least one of the plurality of strip portions of the auxiliary conductive structure (<NUM>). Therefore, only the embodiment illustrated in <FIG> and described in par. [<NUM>]-[<NUM>] falls under the scope of the invention as claimed.

<NUM> - base substrate; <NUM> - opposite substrate; <NUM> - pixel unit; <NUM> - first pixel unit; <NUM> - second pixel unit; <NUM> - pixel electrode; <NUM>/<NUM> - first pixel electrode; <NUM>/<NUM> - second pixel electrode; <NUM> - auxiliary conductive structure; <NUM> - first strip portion; <NUM> - second strip portion; <NUM> - signal line; <NUM> - gate line; <NUM> - data line; <NUM> - gate driver element; <NUM> - data driver element; <NUM> - grounding terminal; <NUM> - thin film transistor; <NUM> - shield component; <NUM> - color filter film; <NUM> - passivation layer; <NUM> - planarization layer; <NUM> - array substrate; <NUM> - hollow region; <NUM> - protrusion; <NUM> - common electrode; <NUM> - display panel; <NUM> - gate insulating layer; <NUM> - display device; <NUM> - leading wire; <NUM> - liquid crystal layer.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," etc., which are used in the description and the claims of the present application for invention, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms "comprise," "comprising," "include," "including," etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases "connect", "connected", etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. "On," "under," "right," "left" and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.

The drawings in the present disclosure are not drawn strictly according to actual scale, the amount of pixel units is not limited to the amount shown in the drawings, and the specific size and amount of each structure may be determined according to actual needs. The drawings described in the present disclosure are merely schematic structural views.

At least one embodiment of the present disclosure provides an array substrate, and the array substrate includes a base substrate and includes a pixel array and an auxiliary conductive structure which are disposed on the base substrate. The pixel array includes a plurality of pixel units distributed in an array and a plurality of pixel electrodes, and each of the plurality of pixel units includes at least one of the plurality of pixel electrodes; the auxiliary conductive structure surrounds at least one of the plurality of pixel electrodes, and the auxiliary conductive structure is insulated from the plurality of pixel electrodes. For example, the array substrate is a display substrate and is used in a display device.

Illustratively, <FIG> is a schematic plan view of the array substrate provided by at least one embodiment of the present disclosure, <FIG> is a cross-sectional view taken along a line A-A' in <FIG>, and <FIG> is a cross-sectional view taken along a line B-B' in <FIG>. As shown in <FIG>, the array substrate <NUM> includes the base substrate <NUM> and includes the pixel array and the auxiliary conductive structure <NUM> which are disposed on the base substrate <NUM>. The pixel array includes the plurality of pixel units <NUM> distributed in an array and the plurality of pixel electrodes <NUM>, each of the plurality of pixel units <NUM> includes one of the plurality of pixel electrodes <NUM>. For example, the array substrate <NUM> includes a plurality of auxiliary conductive structures <NUM>. Each auxiliary conductive structure <NUM> surrounds one of the plurality of pixel electrodes <NUM> and is insulated from the plurality of pixel electrodes <NUM>. For example, a gap is between the auxiliary conductive structure <NUM> and the pixel electrodes <NUM> to insulate the auxiliary conductive structure <NUM> from the pixel electrodes <NUM>. As such, the auxiliary conductive structure <NUM> receives and conducts interfering charges around the pixel electrodes <NUM>, so that the interfering charges are kept away from the pixel electrodes <NUM>, and thereby the interference of the interfering charges on the pixel electrodes <NUM> is prevented or reduced; in a situation where the array substrate <NUM> is applied to a display device, a more accurate and stable display effect of the display device is achieved.

For example, a material of the auxiliary conductive structure <NUM> has a resistivity that is less than or equal to a resistivity of a material of the pixel electrode <NUM>. In a situation where the resistivity of the auxiliary conductive structure <NUM> is smaller than the resistivity of the pixel electrode <NUM>, the auxiliary conductive structure <NUM> is more easily to adsorb the interfering charges surrounding the pixel electrode <NUM> than the pixel electrode <NUM>, and thereby is more advantageous for preventing or reducing the interference of the interfering charges on the pixel electrode <NUM>.

For example, the material of the pixel electrode <NUM> is a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) and has the resistivity of about <NUM>×<NUM>-<NUM> ~ <NUM>×<NUM>-<NUM> (Ω·m); and the material of the auxiliary conductive structure is, for example, at least one selected from the group consisting of aluminum, silver, platinum, copper, grapheme, indium tin oxide (ITO) and the like and has a resistivity smaller than or equal to that of indium tin oxide (ITO). For example, the resistivity of silver is about <NUM>×<NUM>-<NUM> (Ω·m), the resistivity of platinum is about <NUM>×<NUM>-<NUM> (Ω·m), the resistivity of copper is about <NUM>×<NUM>-<NUM> (Ω·m); the resistivity of iron is about <NUM> × <NUM>-<NUM> (Ω·m), the resistivity of aluminum is about <NUM> × <NUM>-<NUM> (Ω·m), and the resistivity of graphene is about (<NUM> ~ <NUM>) × <NUM>-<NUM> (Ω·m). In at least one embodiment, the material of the auxiliary conductive structure <NUM> and the material of the pixel electrode <NUM> are the same.

For example, as shown in <FIG>, the array substrate <NUM> further includes a plurality of signal lines <NUM>. For example, the plurality of signal lines <NUM> include a plurality of gate lines <NUM> and a plurality of data lines <NUM>, and the plurality of gate lines <NUM> and the plurality of data lines <NUM> are disposed on the base substrate <NUM> and cross each other to define the plurality of pixel units <NUM>. For example, each auxiliary conductive structure <NUM> includes a plurality of strip portions extending along an extension direction of the plurality of gate lines <NUM> and an extension direction of the plurality of data lines <NUM>, respectively. For example, the plurality of strip portions include first strip portions <NUM> and second strip portions <NUM>. The first strip portion <NUM> extends in the extension direction of the gate line <NUM>, and the second strip portion <NUM> extends in the extension direction of the data line <NUM>. As such, the plurality of strip portions of the auxiliary conductive structure <NUM> receive and conduct the interfering charges from the gate lines <NUM> and the data lines <NUM> and around the pixel electrodes <NUM>, cause the interfering charges to be kept away from the pixel electrodes <NUM>, and have an electrostatically shielding effect on the pixel electrodes <NUM>, so as to prevent or reduce the interference of these interfering charges on the pixel electrodes <NUM> to achieve a more accurate and stable display effect.

For example, in the embodiment shown in <FIG>, each auxiliary conductive structure <NUM> is located in the pixel unit <NUM> in which the pixel electrode <NUM> surrounded by the auxiliary conductive structure <NUM> is located, to make full use of the spare space of the pixel unit; and, in this case, the auxiliary conductive structure <NUM> is closer to the pixel electrode <NUM>, and more effectively receives and disperses the interfering charges around the pixel electrode <NUM>. For example, each auxiliary conductive structure <NUM> surrounds one of the plurality of pixel electrodes <NUM>, that is, each pixel electrode <NUM> corresponds to one auxiliary conductive structure <NUM> to obtain a larger arrangement density of the auxiliary conductive structures <NUM>, so as to achieve an effect that each pixel electrode <NUM> in the working region of the array substrate is prevented from being interfered by the interfering charges around it.

For example, a planar shape, viewed in a direction perpendicular to the base substrate <NUM>, of the auxiliary conductive structure <NUM> includes a closed loop surrounding at least one of the plurality of pixel electrodes. For example, the planar shape of the auxiliary conductive structures <NUM> includes a plurality of closed loops respectively surrounding the plurality of pixel electrodes. Illustratively, as shown in <FIG>, the planar shape of the auxiliary conductive structures <NUM> includes the plurality of closed loops, and each closed loop surrounds one of the plurality of pixel electrodes <NUM>. The planar shape of the auxiliary conductive structure <NUM> includes the closed loop, which allows the auxiliary conductive structure to simultaneously shield the interfering charges around the entire pixel electrode, for example, simultaneously shielding the static electricity from the gate lines <NUM> and the data lines <NUM> surrounding the pixel electrode. For example, in <FIG>, the plurality of closed loops have a same shape and a same size to facilitate patterning during the process of forming the auxiliary conductive structures. In other embodiments of the present disclosure, the shapes and sizes of the plurality of closed loops may be different from each other.

For example, as shown in <FIG> and <FIG>, the auxiliary conductive structure <NUM> and the plurality of pixel electrodes <NUM> are in a same layer. In this way, it is not necessary to add an additional layer for providing the auxiliary conductive structure <NUM>, which is advantageous for thinning of the array substrate <NUM> and simplification of the manufacturing process of the array substrate <NUM>. For example, the auxiliary conductive structure <NUM> and the plurality of pixel electrodes <NUM> are formed simultaneously, which is advantageous for simplifying the manufacturing process of the array substrate <NUM>. It should be noted that the auxiliary conductive structure and the plurality of pixel electrodes being in the same layer refers to that no other layer is between the auxiliary conductive structure and the plurality of pixel electrodes in a direction perpendicular to the base substrate <NUM>. For example, the auxiliary conductive structure and the plurality of pixel electrodes contact a same layer, and the same layer is, for example, a planarization layer <NUM> shown in <FIG>.

For example, as shown in <FIG>, the plurality of strip portions of the auxiliary conductive structure <NUM> do not overlap the plurality of gate lines <NUM> and do not overlap the plurality of data lines <NUM> in the direction perpendicular to the base substrate <NUM>, so as to prevent that a parasitic capacitance is formed, due to the auxiliary conductive structure <NUM> overlapping the gate line <NUM> and the data line <NUM>, to interfere with the operation of the pixel electrodes <NUM>.

For example, each of the plurality of pixel units <NUM> further includes a thin film transistor <NUM> connected with one of the plurality of pixel electrodes <NUM>; for example, the thin film transistor <NUM> is connected with the pixel electrode <NUM> in the pixel unit <NUM> in which the thin film transistor <NUM> is located. For example, the pixel electrode <NUM> is electrically connected with a drain electrode of the thin film transistor <NUM>; for example, the pixel electrode <NUM> is electrically connected with the drain electrode of the thin film transistor <NUM> through a via hole (not shown in figures), and those skilled in the art may design according to actual requirements. For example, the auxiliary conductive structure <NUM> is not transparent and covers at least a portion of the thin film transistor <NUM>, to better shield a channel region of the thin film transistor <NUM>, and thereby to prevent that a semiconductor material of the channel region of the thin film transistor <NUM> is exposed to light to generate a leakage current.

The array substrate <NUM> further includes a shield component <NUM> between adjacent pixel units among the plurality of pixel units <NUM>; in the direction perpendicular to the base substrate <NUM>, the plurality of strip portions of the auxiliary conductive structure <NUM> do not overlap the shield component <NUM>. For example, in the embodiments illustrated in <FIG>, the shield component <NUM> is a black matrix located between adjacent pixel units. The array substrate <NUM> further includes a color filter film <NUM> in each pixel unit <NUM>, the black matrix spaces the color filter films <NUM> in the adjacent pixel units <NUM> apart from each other, so as to prevent crosstalk of light in the adjacent pixel units <NUM>.

For example, the array substrate further includes a color filter film array including a plurality of color filter films <NUM>, and each of the plurality of pixel units <NUM> includes one of the plurality of color filter films <NUM>. For example, in the at least one embodiment shown in <FIG>, the shield component <NUM> is a stack formed by overlapping the color filter films <NUM> in the adjacent pixel units <NUM>, to prevent crosstalk of light in the adjacent pixel units <NUM>. The embodiments of the present disclosure do not limit the specific type of the shield component <NUM>.

It should be understood that the shield component <NUM> may be the black matrix or may be the stack of two adjacent color filter films of the plurality of color filter films <NUM>; or the shield component <NUM> may include the black matrix and the stack of two adjacent color filter films <NUM>. For example, the auxiliary conductive structure <NUM> is located between two adjacent black matrixes; for example, the auxiliary conductive structure <NUM> is located between two stacks of the color filter films <NUM>.

For example, the array substrate <NUM> further includes a gate insulating layer <NUM> covering the gate lines <NUM>, a passivation layer <NUM> covering the thin film transistor <NUM> and the data lines <NUM>, and the planarization layer <NUM> covering the color filter films <NUM> and the shield component <NUM>. A surface which is included by the planarization layer <NUM> and is away from the base substrate <NUM> is a planar surface, and the pixel electrodes <NUM> and the auxiliary conductive structure <NUM> are disposed on the planar surface.

For example, in other embodiments of the present disclosure, not every pixel electrode corresponds to one auxiliary conductive structure. In other embodiments of the present disclosure, for example, one closed auxiliary conductive structure <NUM> surrounds several pixel electrodes <NUM>, that is, the several pixel electrodes <NUM> share one auxiliary conductive structure <NUM>.

<FIG> is another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure. As shown in <FIG>, the array substrate <NUM> is different from the array substrate of <FIG> in that not every pixel electrode <NUM> corresponds to one auxiliary conductive structure <NUM>, but a part of the pixel electrodes <NUM> are surrounded by the auxiliary conductive structures <NUM>. For example, the pixel electrodes <NUM> in the pixel units <NUM> of odd-numbered columns of the pixel array are respectively surrounded by the auxiliary conductive structures <NUM>, and the pixel electrodes <NUM> in the pixel units <NUM> of even-numbered columns of the pixel array are not surrounded by the auxiliary conductive structures <NUM>. Other features of the array substrate <NUM> shown in <FIG> may be the same as those of the array substrate in <FIG>, please refer to the previous descriptions. It should be understood that the auxiliary conductive structures <NUM> in <FIG> and <FIG> may be electrically insulated from each other, or a part of or all of the auxiliary conductive structures <NUM> may be electrically connected with each other. For example, the auxiliary conductive structures <NUM> corresponding to the pixel units <NUM> of the m-th column are connected with each other; the auxiliary conductive structures <NUM> corresponding to the pixel units <NUM> of the n-th column are connected with each other (m is not equal to n, and n is a natural number). The following embodiments are similar and will not be described again.

<FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure. As shown in <FIG>, the array substrate <NUM> is different from the array substrate in <FIG> in that the planar shape, vied in the direction perpendicular to the base substrate <NUM>, of the auxiliary conductive structure <NUM> includes the closed loop surrounding two or more of the plurality of pixel electrodes. For example, the auxiliary conductive structures <NUM> includes a plurality of closed loops, and each closed loop surrounds the pixel electrodes <NUM> in two adjacent pixel units <NUM>. In other embodiments of the present disclosure, the amount of the pixel electrodes <NUM> surrounded by each auxiliary conductive structure <NUM> is not limited to two. Other features of the array substrate <NUM> shown in <FIG> are the same as those of the array substrate in <FIG>, please refer to the previous description.

For example, <FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure, <FIG> is a cross-sectional view taken along a line A-A' in <FIG>, and <FIG> is a cross-sectional view taken along a line B-B' in <FIG>. In <FIG>, the array substrate <NUM> is different from the array substrate of <FIG> in that the auxiliary conductive structure <NUM> includes a plurality of closed loops, each closed loop surrounds the pixel electrodes <NUM> in four adjacent pixel units <NUM>; in the direction perpendicular to the base substrate <NUM>, the plurality of strip portions of the auxiliary conductive structure <NUM> respectively overlap a part of the plurality of gate lines <NUM> and a part of the plurality of data lines <NUM> to facilitate better reception and conduction of the interfering charges from the gate lines and the data lines, thereby better preventing or reducing the interference of these interfering charges on the pixel electrodes. In the embodiments of the present disclosure, for example, the plurality of strip portions of the auxiliary conductive structure <NUM> respectively overlap a part or all of the plurality of gate lines <NUM> and the plurality of data lines <NUM>. Other features of the array substrate <NUM> shown in <FIG> are the same as those of the array substrate in <FIG>, please refer to the previous description.

<FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure, <FIG> is a cross-sectional view taken along a line A-A' in <FIG>, and <FIG> is a cross-sectional view taken along a line B-B' in <FIG>. In <FIG>, the array substrate <NUM> is different from the array substrate of <FIG> in that the auxiliary conductive structure <NUM> includes the plurality of strip portions, the plurality of strip portions are respectively along the extension direction of the plurality of gate lines <NUM> and the extension direction of the plurality of data lines <NUM>, and the plurality of strip portions of the auxiliary conductive structure <NUM> are located in the non-display region between the adjacent pixel units <NUM>, which facilitates better receiving and conducting of the interfering charges from the gate lines and data lines while reducing the influence on the aperture ratio, so as to better prevent or reduce the interference of these interfering charges on the pixel electrodes.

For example, in <FIG> and <FIG>, in the direction perpendicular to the base substrate <NUM>, the plurality of strip portions of the auxiliary conductive structure <NUM> respectively overlap the plurality of gate lines <NUM> and the plurality of data lines <NUM>, so that it is advantageous to better receive and conduct the interfering charges from the gate lines and the data lines, thereby better preventing or reducing the interference of these interfering charges on the pixel electrodes. For example, the gate line <NUM> and the data line <NUM> are respectively electrically connected with the thin film transistor <NUM>; the plurality of strip portions of the auxiliary conductive structure <NUM> include the first strip portions <NUM> and the second strip portions <NUM>, the first strip portions <NUM> extend along the extension direction of the plurality of gate lines <NUM>, and the second strip portions <NUM> extend along the extension direction of the plurality of data lines <NUM>. For example, in the at least one embodiment illustrated in <FIG>, the first strip portion <NUM> partially overlaps the gate line <NUM>; the second strip portion <NUM> partially overlaps the data line <NUM>. A width L1 of the first strip portion <NUM> in a direction perpendicular to the extension direction of the first strip portion <NUM> is larger than a width L2 of the second strip portion <NUM> in a direction perpendicular to the extension direction of the second strip portion <NUM>. A portion of the gate line <NUM> corresponds to the channel region of the thin film transistor, thus it is advantageous for the first strip portion <NUM> to more fully shield the channel region of the thin film transistor <NUM>, thereby preventing or reducing the leakage current generated due to exposure of the semiconductor material of the channel region in the thin film transistor <NUM> to light.

For example, in at least one embodiment of the present disclosure, distances from the first strip portion to two pixel electrodes adjacent to the first strip portion among the plurality of pixel electrodes are not equal. Similarly, distances from the second strip portion to two pixel electrodes adjacent to the second strip portion among the plurality of pixel electrodes are not equal. Illustratively, as shown in <FIG>, the distances from the first strip portion <NUM> to the two pixel electrodes adjacent to the first strip portion <NUM> among the plurality of pixel electrodes <NUM> arc X1 and X2, respectively, and X1 and X2 are not equal.

For example, distances from two adjacent first strip portions to the same pixel electrode located between the two adjacent first strip portions are not equal, or distances from two adjacent second strip portions to the same pixel electrode located between the two adjacent second strip portions are not equal. At least one of the first strip portions and the second strip portions have an unequal distance to the same pixel electrode. For example, the distances from the two adjacent first strip portions <NUM> to the same pixel electrode located between the two adjacent first strip portions <NUM> are S<NUM> and S<NUM>, respectively, and S<NUM> and S<NUM> are not equal. For example, the distances from the two adjacent second strip portions <NUM> to the same pixel electrode located between the two adjacent second strip portions <NUM> are D<NUM> and D<NUM>, respectively, and D<NUM> and D<NUM> are not equal. For example, D<NUM>, D<NUM>, S<NUM> and S<NUM> are unequal. For example, D<NUM>>D<NUM>>S<NUM>>S<NUM>. For example, D<NUM> is greater than D<NUM> and S<NUM> is greater than S<NUM>. The embodiments of the present disclosure do not limit the relationships between D<NUM>, D<NUM>, S<NUM> and S<NUM>.

For example, as shown in <FIG> and <FIG>, the array substrate <NUM> further includes a leading wire <NUM>, and the auxiliary conductive structure <NUM> is grounded or is applied with a fixed voltage through the leading wire <NUM>, so that a voltage applied to the auxiliary conductive structure <NUM> is zero or the fixed voltage. For example, the array substrate <NUM> further includes a driver element configured for controlling the operation of the pixel units. For example, the driver element is a drive circuit. The auxiliary conductive structure <NUM> is connected with a grounded terminal of the drive circuit through the leading wire <NUM>, so that the voltage applied to the auxiliary conductive structure <NUM> is zero; or, in the array substrate <NUM>, the auxiliary conductive structure <NUM> receives the fixed voltage from the drive circuit through the leading wire <NUM>, and for example, the fixed voltage is a common voltage (which is a voltage applied to a common electrode in a situation where the array substrate further includes the common electrode), in which case, the voltage applied to the auxiliary conductive structure <NUM> is the same as the voltage applied to the common electrode <NUM>. For example, in the at least one embodiment shown in <FIG>, the auxiliary conductive structure <NUM> is separated from the common electrode, and the auxiliary conductive structure <NUM> and the common electrode <NUM> are respectively applied with the common voltage. In another embodiment, the auxiliary conductive structure <NUM> and the common electrode are disposed in the same layer, and for example, the common electrode and the auxiliary conductive structure <NUM> are integral with each other.

It should be noted that, in <FIG>, the array substrate <NUM> for example further includes the leading wire. For example, the array substrate <NUM> includes a plurality of leading wires, each of the plurality of leading wires respectively corresponds to one of the auxiliary conductive structures <NUM>, and the auxiliary conductive structure <NUM> is grounded or is applied with the fixed voltage through the corresponding leading wire.

<FIG> is another schematic cross-sectional view taken along the line A-A' in <FIG>, and <FIG> is another cross-sectional view taken along the line B-B' in <FIG>. The at least one embodiment shown in <FIG> and <FIG> differs from the at least one embodiment shown <FIG> in that the array substrate <NUM> further includes the shield component <NUM> and the color filter film <NUM>. The auxiliary conductive structure <NUM> overlaps the shield component <NUM> and a width of the auxiliary conductive structure <NUM> is smaller than a width of the shield component <NUM>, to allow the auxiliary conductive structure <NUM> to be located in a non-display region, so that in the situation where the array substrate <NUM> is applied to the display device, the aperture ratio of the display device is not affected even the auxiliary conductive structure adopts an opaque conductive material. The shield component <NUM> and the color filter film <NUM> are the same as that in the previous embodiments, please refer to the previous description.

<FIG> is another schematic cross-sectional view taken along the line A-A' in <FIG>. The at least one embodiment shown in <FIG> differs from the at least one embodiment shown in <FIG> and <FIG> in that the array substrate <NUM> further includes protrusions <NUM>, and the protrusions <NUM> are disposed on the auxiliary conductive structure <NUM> and protrude toward a direction away from the base substrate <NUM>. For example, the array substrate <NUM> is applied to the display device, the protrusions <NUM> are spacers; for example, the spacers are strip spacers or column spacers. Thus, it is not necessary to separately provide a support layer for the protrusions <NUM>, and thus the structures of the array substrate and the structure of the display device are simplified. For example, in the direction perpendicular to the base substrate <NUM>, the protrusion <NUM> overlaps the thin film transistor <NUM> and the protrusion <NUM> is located in the non-display region, which is advantageous for better shielding the channel region of the thin film transistor <NUM> and improving the aperture ratio of the display device.

<FIG> is a schematic plan view of the pixel unit of the array substrate provided by at least one embodiment of the present invention, and <FIG> is another schematic plan view of the pixel unit of the array substrate provided by at least one embodiment of the present disclosure. For example, in the array substrate provided by at least one embodiment of the present disclosure, each pixel unit is as shown in <FIG>, or each of a part of the pixel units is as shown in <FIG>. As shown in <FIG>, each of the plurality of pixel units <NUM> includes a start position O close to the thin film transistor <NUM> and includes at least one strip portion among the plurality of strip portions of the auxiliary conductive structure <NUM>; taking the case that the at least one strip portion is the second strip portion <NUM> as an example, each of the plurality of pixel units <NUM> includes an end position T away from the start position O in the extension direction of the second strip portion <NUM> and includes an intermediate position M at a midpoint of a connecting line between the start position O and the end position T. The second strip portion <NUM> includes a first portion <NUM> extending from the start position O of the pixel unit <NUM> to the intermediate position M of the pixel unit <NUM> and includes a second portion <NUM> extending from the intermediate position M of the pixel unit <NUM> to the end position T of the pixel unit <NUM>; the first portion <NUM> has a first width W<NUM> in a direction perpendicular to the extension direction of the second strip portion <NUM>, the second portion <NUM> has a second width W<NUM> in the direction perpendicular to the extension direction of the second strip portion <NUM>, and the width W<NUM> is greater than the second width W<NUM>. On one hand, the first width W<NUM> is greater than the second width W<NUM>, so as to facilitate the first portion <NUM> to effectively shield the thin film transistor <NUM>, and thus to prevent that the semiconductor material of the channel region of the thin film transistor <NUM> is exposed to light to generate leakage current; on the other hand, the above protrusion for example is provided at the position of the start position O, and the first width W<NUM> of the first portion <NUM> of the strip portion at the position of the start position O is relatively large, which facilitates the stability of the structure of the protrusion and avoids manufacturing process errors. For example, as shown in <FIG>, taking the case that the at least one strip portion is the second strip portion <NUM> as an example, the second strip portion <NUM> includes a first portion <NUM>, a second portion <NUM> and a third portion <NUM> which extend and are sequentially arranged in a direction from the start position O of the pixel unit <NUM> to the end position T of the pixel unit; a width W<NUM> of the first portion <NUM> in the direction perpendicular to the extension direction of the second strip portion <NUM>, a width W<NUM> of the second portion <NUM> in the direction perpendicular to the extension direction of the second strip portion <NUM>, and a width W<NUM> of the third portion in the direction perpendicular to the extension direction of the second strip portion <NUM> are sequentially decreased, that is, W<NUM> > W<NUM> > W<NUM>. In other embodiments of the present disclosure, it is not limited to the case that the second strip portion <NUM> includes the first portion, the second portion and the third portion, for example it is possible that the first strip portion <NUM> includes the first portion, the second portion and the third portion. Also, for example, at least one of the plurality of strip portions includes a plurality of portions which extend and are sequentially arranged in the direction from the start position O of the pixel unit <NUM> to the end position T of the pixel unit, and the plurality of portions are not limited to three portions; widths of the plurality of portions arranged in the direction from the start position O of the pixel unit <NUM> to the end position T of the pixel unit are sequentially decreased; it is not limited that the first portion starts from the start position O, but it is possible that the first portion starts from any point in the direction from the start position O of the pixel unit <NUM> to the end position T of the pixel unit. The embodiments are also applicable to the case where one pixel unit includes two or more pixel electrodes.

<FIG> is still another schematic plan view of the pixel unit of the array substrate provided by at least one embodiment of the present disclosure. As shown in <FIG>, the planar shape, viewed in the direction perpendicular to the base substrate <NUM>, of the pixel electrode <NUM> has a groove <NUM>, the auxiliary conductive structure <NUM> includes a protrusion portion <NUM>, and the protrusion portion <NUM> is located on a side of the strip portion (for example, the second strip portion <NUM>) facing the pixel electrode <NUM> and is corresponding to the groove <NUM>. The protrusion portion <NUM> being corresponding to the groove <NUM> means that, a shape of the protrusion portion <NUM> is substantially complementary to a shape of the groove <NUM>, such that an outline shape of the side of the strip portion of the auxiliary conductive structure <NUM> facing the pixel electrode <NUM> is arranged according to an outline of the pixel electrode <NUM>, so as to better prevent the interfering charges around the pixel electrode <NUM>. In another embodiment, for example, the auxiliary conductive structure includes the groove on the side of the strip portion facing the pixel electrode, the planar shape of the pixel electrode has the protrusion portion corresponding to the groove, and the protrusion portion is complementary to the groove. For example, in the array substrate provided by at least one embodiment of the present disclosure, each of the pixel units has the groove as shown in <FIG>, or each of a part of the pixel units has the groove as shown in <FIG>.

For example, as shown in <FIG>, the protrusion portion <NUM> and the at least one (for example, the second strip portion <NUM>) of the plurality of strip portions are integral with each other. That is, in the present embodiment, the protrusion portion <NUM> and the second strip portion <NUM> are formed of a same material through a same process to simplify the structure of the array substrate and simplify the manufacturing process.

<FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure, and <FIG> is a schematic cross-sectional view taken along a line A-A' in <FIG>. As shown in <FIG> and <FIG>, the array substrate <NUM> has the following differences from the array substrate shown in <FIG>. At least one of the plurality of strip portions of the auxiliary conductive structure <NUM> includes a plurality of hollow regions <NUM> which are spaced apart from each other and penetrate through the at least one strip portion. As shown in <FIG>, for example, the array substrate <NUM> further includes the common electrode <NUM> disposed in a layer different from a layer where the plurality of pixel electrodes <NUM> are located, and the hollow regions <NUM> overlap at least a part of at least one of the gate lines <NUM>, the data lines <NUM> and the common electrodes <NUM> in the direction perpendicular to the base substrate <NUM>. It should be noted that the common electrode disposed in the layer different from the layer where the plurality of pixel electrodes <NUM> are located means that another layer exists between the common electrode and the plurality of pixel electrodes in the direction perpendicular to the base substrate.

For example, as shown in <FIG>, a width d<NUM> of each of the plurality of hollow regions <NUM> is smaller than the width d<NUM> of the at least one strip portion in the direction perpendicular to the extension direction of the at least one strip portion. For example, each first strip portion <NUM> includes the plurality of the above-described hollow regions <NUM>; thus, the area of the portion which is included by the auxiliary conductive structure <NUM> and overlaps the gate lines <NUM> is reduced, thereby reducing the parasitic capacitance generated due to the overlapping of the auxiliary conductive structure <NUM> and the gate lines <NUM>. Moreover, d<NUM><d<NUM> maintains the electrical conduction of the auxiliary conductive structure <NUM> around the pixel electrodes, so that the auxiliary conductive structure <NUM> is grounded or is applied with the fixed voltage via one leading wire <NUM>, which is advantageous for simplifying the structure of the array substrate. Similarly, in other embodiments of the present disclosure, the auxiliary conductive structure for example is provided with the hollow regions in a region overlapping other structures except for the gate lines and the data lines. For example, in the case where the auxiliary conductive structure <NUM> overlaps the common electrode line, the auxiliary conductive structure <NUM> is provided with the hollow regions in an overlapping region where the auxiliary conductive structure <NUM> overlaps the common electrode line.

For example, planar shapes, viewed in the direction perpendicular to the base substrate <NUM>, of the plurality of hollow regions <NUM> are the same, and distances between adjacent hollow regions <NUM> among the plurality of hollow regions <NUM> are equal. Thus, for the interference of the interfering charges on the pixel electrodes <NUM> and the parasitic capacitance caused by the overlapping of the auxiliary conductive structure <NUM> and the gate lines <NUM>, a relatively uniform improvement effect is obtained in the entire working region of the array substrate <NUM>, and for example, a uniform display effect is obtained in an entire display region in the situation where the array substrate is applied to the display device.

For example, as shown in <FIG>, the array substrate <NUM> further includes the driver element and the leading wire <NUM>. The driver element includes gate driver elements <NUM> and data driver elements <NUM>. The gate driver elements <NUM> are connected with the gate lines <NUM> to control the turning on and turning off of the pixel units <NUM> in operation. The driver element is a drive circuit. The data driver elements <NUM> are connected with the data lines <NUM> to supply the pixel units <NUM> with data signals. For example, the gate driver elements <NUM> are gate drive circuits, and the data driver elements <NUM> are data drive circuits. For example, the drive circuit further includes a grounding terminal <NUM>, and the auxiliary conductive structure <NUM> is connected with the grounding terminal <NUM> of the drive circuit through the leading wire <NUM>, so that the voltage applied to the auxiliary conductive structure <NUM> is zero; or, in the array substrate <NUM>, the auxiliary conductive structure <NUM> is applied with the fixed voltage in the drive circuit through the leading wire <NUM>, and for example, the fixed voltage is the common voltage (the voltage applied to the common electrode in the situation where the array substrate further includes the common electrode), in which case the voltage applied to the auxiliary conductive structure <NUM> is same as the voltage applied to the common electrode <NUM>. For example, at least one leading wire <NUM> is located between adjacent data driver elements <NUM> or adjacent gate driver elements <NUM>.

<FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure, and <FIG> is still another schematic plan view of the array substrate provided by at least one embodiment of the present disclosure. For example, as shown in <FIG> and <FIG>, the plurality of pixel units include a first pixel unit <NUM> and a second pixel unit <NUM>, and the first pixel unit <NUM> is adjacent to the second pixel unit <NUM>; the first pixel unit <NUM> includes a first pixel electrode <NUM> and a second pixel electrode <NUM>; the second pixel unit <NUM> includes a first pixel electrode <NUM> and a second pixel electrode <NUM>. The planar shape of the auxiliary conductive structure <NUM> includes the closed loop surrounding the second pixel electrode <NUM> located in the first pixel unit <NUM> and the first pixel electrode <NUM> located in the second pixel unit <NUM>. As such, in the case where one pixel unit includes two pixel electrodes, it is also possible to allow that the interfering charges around the pixel electrodes are kept away from the pixel electrodes by the auxiliary conductive structure, thereby preventing or reducing the interference of the interfering charges on the pixel electrodes.

For example, in the array substrate shown in <FIG> and <FIG>, the thin film transistors (not shown in the figures) in the first pixel unit <NUM> are respectively connected with the first pixel electrode <NUM> and the second pixel electrode <NUM> in the first pixel unit <NUM>, and the thin film transistors (not shown in the figures) in the second pixel unit <NUM> are respectively electrically connected with the first pixel electrode <NUM> and the second pixel electrode <NUM> in the second pixel unit <NUM>. In at least one embodiment of the present disclosure, the gate electrodes of the two thin film transistors respectively connected to the two pixel electrodes in the same pixel unit are connected with the same gate line. Taking the first pixel unit <NUM> as an example, for example, each first pixel unit <NUM> includes two thin film transistors, which are a first thin film transistor and a second thin film transistor. The drain electrode of the first thin film transistor is electrically connected with the first pixel electrode <NUM>, and the drain electrode of the second thin film transistor is electrically connected with the second pixel electrode <NUM>. The gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are connected with the same gate line <NUM> among the plurality of gate lines. The source electrode of the first thin film transistor and the source electrode of the second thin film transistor are both electrically connected with the same data line <NUM> among the plurality of data lines.

For example, as shown in <FIG>, the plurality of closed loops are connected with each other by the first strip portions <NUM>. Alternatively, as shown in <FIG>, the auxiliary conductive structure <NUM> further includes a connecting portion <NUM>, and the plurality of closed loops are connected with each other through the connecting portion <NUM>. Features that are not described again with respect to the array substrate in <FIG> and <FIG> are the same as those in the previous embodiments, and the previous description can be referred to.

At least one embodiment of the present disclosure further provides a display panel, which includes the array substrates provided by any one of the embodiments of the present disclosure.

For example, <FIG> is a schematic diagram of the display panel provided by at least one embodiment of the present disclosure. As shown in <FIG>, the display panel <NUM> includes the array substrates <NUM> provided by any one of the embodiments of the present disclosure. In the display panel <NUM> provided by at least one embodiment of the present disclosure, the auxiliary conductive structure <NUM> receives and conducts the interfering charges around the pixel electrodes, so as to allow the interfering charges to be kept away from the pixel electrodes, thereby preventing or reducing the interference of the interfering charges on the pixel electrodes, so that the display panel <NUM> achieves a more accurate and stable display. For example, the display panel <NUM> is a liquid crystal display panel.

<FIG> is a schematic cross-sectional view of the display panel provided by at least one embodiment of the present disclosure. For example, as shown in <FIG>, the display panel <NUM> is the liquid crystal display panel. In this case, the display panel <NUM> further includes an opposite substrate <NUM>, a liquid crystal layer <NUM> and the common electrode <NUM>. The opposite substrate <NUM> is opposite to the array substrate <NUM>; the liquid crystal layer <NUM> is disposed between the array substrate <NUM> and the opposite substrate <NUM>; and the common electrode <NUM> belongs to the array substrate <NUM>. The common electrode <NUM> and the plurality of pixel electrodes <NUM> form an electric field that controls deflection of liquid crystal molecules in the liquid crystal layer <NUM>. For example, a common voltage signal is applied to both the common electrode <NUM> and the auxiliary conductive structure <NUM> by the drive circuit, in which case the electric signal applied to the auxiliary conductive structure <NUM> is the same as the electric signal applied to the common electrode <NUM>.

For example, in the display panel shown in <FIG>, the color filter film <NUM> and the shield component <NUM> (the shield component is, for example, the black matrix in the liquid crystal display panel) are included by the array substrate. For example, the protrusion <NUM> has a required height for supporting the opposite substrate <NUM>, maintaining a liquid crystal cell gap of the display panel and spacing the liquid crystals corresponding to the respective pixel units. The protrusion <NUM> is disposed on the auxiliary conductive structure <NUM>, and the auxiliary conductive structure <NUM> raises the protrusion <NUM>, so that it is not necessary to separately provide the supporting layer for the protrusion <NUM>, thereby simplifying the structure of the display panel.

<FIG> is another schematic cross-sectional view of the display panel provided by at least one embodiment of the present disclosure. For example, in the display panel shown in <FIG>, the common electrode <NUM> is included by the opposite substrate <NUM>. For example, the common electrode <NUM> is a structure in a one-piece form to cover the plurality of pixel units.

<FIG> is still another cross-sectional view of the display panel provided by at least one embodiment of the present disclosure. For example, in the display panel shown in <FIG>, the common electrode <NUM>, the color filter film <NUM> and the covering <NUM> are included by the opposite substrate <NUM>.

At least one embodiment of the present disclosure further provides a display device including the display panel provided by any one of the embodiments of the present disclosure.

For example, <FIG> is a schematic diagram of the display device provided by at least one embodiment of the present disclosure. As shown in <FIG>, the display device <NUM> includes the display panel <NUM> provided by any one of the embodiments of the present disclosure. In the display device <NUM> provided by at least one embodiment of the present disclosure, the auxiliary conductive structure <NUM> receives and conducts the interfering charges around the pixel electrodes, so as to allow the interfering charges to be kept away from the pixel electrodes, thereby preventing or reducing the interference of the interfering charges on the pixel electrodes, so that the display device <NUM> achieves a more accurate and stable display effect. For example, the display device <NUM> is a liquid crystal display device. For example, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Claim 1:
An array substrate (<NUM>), comprising:
a base substrate (<NUM>), a pixel array and an auxiliary conductive structure (<NUM>) which are on the base substrate (<NUM>);
wherein the pixel array comprises a plurality of pixel units (<NUM>) distributed in an array and a plurality of pixel electrodes (<NUM>), and each of the plurality of pixel units (<NUM>) comprises at least one of the plurality of pixel electrodes (<NUM>);
the auxiliary conductive structure (<NUM>) surrounds at least one of the plurality of pixel electrodes (<NUM>) and is insulated from the plurality of pixel electrodes (<NUM>), and a planar shape, viewed in a direction perpendicular to the base substrate (<NUM>), of the auxiliary conductive structure (<NUM>) comprises a closed loop surrounding the at least one of the plurality of pixel electrodes (<NUM>);
the array substrate (<NUM>) further comprises: a plurality of gate lines (<NUM>) and a plurality of data lines (<NUM>), provided on the base substrate (<NUM>) and crossing each other to define the plurality of pixel units (<NUM>), and the auxiliary conductive structure (<NUM>) comprises a plurality of strip portions respectively extending along an extension direction of the plurality of data lines (<NUM>) and an extension direction of the plurality of gate lines (<NUM>);
the plurality of strip portions of the auxiliary conductive structure (<NUM>) overlap at least a part of the plurality of gate lines (<NUM>) and/or overlap at least a part of the plurality of data lines (<NUM>) in a direction perpendicular to the base substrate (<NUM>);
the array substrate (<NUM>) further comprises a common electrode (<NUM>) in a layer different from a layer where the plurality of pixel electrodes (<NUM>) are located, characterized in that:
at least one strip portion among the plurality of strip portions of the auxiliary conductive structure (<NUM>) comprises a plurality of hollow regions (<NUM>) which are spaced apart from each other and penetrate through the at least one strip portion; and
each of the plurality of hollow regions (<NUM>) overlaps at least a part of at least one of the plurality of gate lines (<NUM>), the plurality of data lines (<NUM>) and the common electrode (<NUM>) in the direction perpendicular to the base substrate (<NUM>).