Patent Description:
A flat panel display device is used as a display device replacing a cathode ray in a display device, due to characteristics such as light weight and thinness. Representative examples of such flat panel display devices are a liquid crystal display device ("LCD") and an organic light emitting display device ("OLED").

The display device may include a module-corresponding area in which a functional module is disposed, and a display area surrounding the module-corresponding area and in which emission structures are disposed. Here, the functional module may be disposed on a lower surface of a substrate included in the display device. A display device capable of displaying an image by arranging emission structures in the module-corresponding area has been developed.

<CIT> relates to a display panel having a phase compensation layer.

Embodiments provide a display device with improved display quality.

An embodiment of a display device includes a substrate including a (functional) module-corresponding area, a display area adjacent to the module-corresponding area, and a pixel circuit area at a side of the display area, an inorganic insulating layer in the display area on the substrate, a (light) phase compensation layer in the module-corresponding area, on the substrate, and including a same material as the inorganic insulating layer, a signal line in the module-corresponding area, on the phase compensation layer and extending from the module-corresponding area to the pixel circuit area, and an organic insulating layer on the inorganic insulating layer and extending from the display area to the module-corresponding area to cover the signal line and the phase compensation layer.

In an embodiment, the display device may further include an etch stop layer in the module-corresponding area, between the substrate and the phase compensation layer, and including a transparent material.

In an embodiment, an etch rate of the etch stop layer may be smaller than an etch rate of the phase compensation layer.

In an embodiment, the etch stop layer may include indium gallium zinc oxide ("IGZO") or amorphous silicon.

In an embodiment, the etch stop layer may be in an entirety of the module-corresponding area.

In an embodiment, the etch stop layer may be a pattern which overlaps each of the phase compensation layer and the signal line.

In an embodiment, the signal line may include a conductive metal oxide or a transparent conductive material.

In an embodiment, the transparent conductive material may include indium tin oxide ("ITO"), indium zinc oxide ("IZO") or indium gallium oxide ("IGO").

In an embodiment, the inorganic insulating layer may include silicon oxide or silicon nitride.

In an embodiment, a refractive index of the organic insulating layer may be greater than a refractive index of the phase compensation layer and smaller than a refractive index of the signal line.

In an embodiment, a refractive index of the signal line may be about <NUM> or more in a visible light region.

In an embodiment, the display device may further include a functional module in the module-corresponding area, on a lower surface of the substrate.

In an embodiment, the functional module may include a camera module, a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module or an illuminance sensor module.

In an embodiment, the display device may further include a pixel circuit structure in the pixel circuit area, on the substrate, and including a semiconductor element, and an emission structure in the module-corresponding area, on the substrate.

In an embodiment, the signal line may electrically connect the pixel circuit structure and the emission structure.

An embodiment of a display device includes a substrate including a module-corresponding area, a display area adjacent to the module-corresponding area, and a pixel circuit area at a side of the display area, a first inorganic insulating layer in the display area and the module-corresponding area, on the substrate, a second inorganic insulating layer in the display area, on the first inorganic insulating layer, a (light) phase compensation layer in the module-corresponding area, on the substrate, and including a same material as the second inorganic insulating layer, a signal line in the module-corresponding area, on the phase compensation layer, and extending from the module-corresponding area to the pixel circuit area, and an organic insulating layer on the second inorganic insulating layer and extending from the display area to the module-corresponding area to cover the signal line and the phase compensation layer.

In an embodiment, the display device may further include an etch stop layer in the module-corresponding area, on the first inorganic insulating layer, and including a transparent material.

In an embodiment, the etch stop layer may include indium gallium zinc oxide or amorphous silicon.

In an embodiment, each of the first inorganic insulating layer and the second inorganic insulating layer may include silicon oxide or silicon nitride.

In one or more embodiments of a display device, as a light phase compensation layer including an inorganic insulating material is in a functional module area, an occurrence of a flare phenomenon may be reduced.

In addition, as a etch stop layer including a transparent material is in the functional module area between the substrate and the phase compensation layer, a non-uniformity of a thickness of the phase compensation layer in a large-area display device may be improved.

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

It will be understood that when an element is referred to as being related to another element such as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being related to an element such as being "directly on" another element, there are no intervening elements present.

Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of embodiments.

<FIG> are perspective views illustrating an embodiment of a display device <NUM>. <FIG> is a plan view illustrating the display device <NUM> of <FIG>.

Referring to <FIG>, and <FIG>, the display device <NUM> may include a display area <NUM>, a module-corresponding area <NUM> (e.g., functional module area), and a pixel circuit area <NUM>.

The display area <NUM> is adjacent to the module-corresponding area <NUM> and may surround at least a portion of the module-corresponding area <NUM>. The pixel circuit area <NUM> may be positioned at one side of the display area <NUM>. In addition, the pixel circuit area <NUM> may be adjacent to one side of the module-corresponding area <NUM>. That is, first to third sides of the module-corresponding area <NUM> may be adjacent to the display area <NUM>, and a fourth side of the module-corresponding area <NUM> may be adjacent to the pixel circuit area <NUM>, so as to be surrounded by the display area <NUM> together with the pixel circuit area <NUM>.

The display device <NUM> may be divided into (or include) a first surface S1 and a second surface S2. The first surface S1 may correspond to a surface on which an image is displayed (e.g., display surface). The second surface S2 may correspond to a surface on which an image is not displayed. The module-corresponding area <NUM> may be in and form a part of the display area <NUM>. An image may be displayed and/or light may be emitted at the module-corresponding area <NUM>, without being limited thereto.

The display device <NUM> may include a functional module FM. The functional module FM may be disposed to overlap (or correspond to) the module-corresponding area <NUM>, on the second surface S2. In an embodiment, an image may be displayed at both a portion of the first surface S1 overlapping the module-corresponding area <NUM> and a portion of the first surface S1 overlapping the display area <NUM>. In an embodiment, for example, the functional module FM may provide a function to the display device <NUM> and may include a camera module, a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, an illuminance sensor module, and the like. In an embodiment, the functional module FM may include the camera module. In this case, the functional module FM may capture an image by capturing external light incident to the display device <NUM> through a portion of the first surface S1 overlapping the module-corresponding area <NUM>, to provide an image-capturing function to the display device <NUM>.

However, although a shape of the functional module FM is shown as having a rectangular planar shape, the planar shape of the functional module FM is not limited thereto. In an embodiment, for example, the functional module FM may have a triangular planar shape, a rhombus planar shape, a polygonal planar shape, a track-type planar shape, a circular planar shape, or an elliptical planar shape. In addition, when a planar shape of the functional module FM is changed, a planar shape of the module-corresponding area <NUM> may also be changed according to an outer shape of the functional module FM.

<FIG> and <FIG> are partially enlarged plan views illustrating embodiments of area 'A' of <FIG>.

Referring to <FIG>, the display area <NUM> may include (or correspond to) a second pixel area <NUM>, and the module-corresponding area <NUM> may include a transparent area <NUM> and a first pixel area <NUM>. In addition, the pixel circuit area <NUM> may include a first pixel circuit area <NUM> provided in plural including a plurality first pixel circuit areas <NUM> and a second pixel circuit area <NUM> provided in plural including a plurality of second pixel circuit areas <NUM>.

The second pixel area <NUM> may include a plurality of second sub-pixel areas <NUM>, <NUM>, and <NUM> emitting light of different colors. The first pixel area <NUM> may include a plurality of first sub-pixel areas <NUM>, <NUM>, and <NUM> emitting light of different colors. The lights of different colors may be used to display an image within the display area <NUM>, without being limited thereto. The pixel area (or sub-pixel area) may otherwise be referred to as a light emission area.

In an embodiment, for example, the second sub-pixel areas <NUM>, <NUM>, and <NUM> may include a second red pixel area <NUM> in which a red emission structure R (e.g., a second emission structure <NUM> of <FIG>) emitting red light is disposed, a second green pixel area <NUM> in which a green emission structure G emitting green light is disposed, and a second blue pixel area <NUM> in which a blue emission structure B emitting blue light is disposed. In addition, the first sub-pixel areas <NUM>, <NUM>, and <NUM> may include a first red pixel area <NUM> in which a red emission structure R (e.g., a first emission structure <NUM> of <FIG>) emitting red light is disposed, a first green pixel area <NUM> in which a green emission structure G emitting green light is disposed, and a first blue pixel area <NUM> in which a blue emission structure B emitting blue light is disposed.

The plurality of second sub-pixel areas <NUM>, <NUM>, and <NUM> may be repeatedly arranged in the display area <NUM>. The plurality of first sub-pixel areas <NUM>, <NUM>, and <NUM> may be repeatedly arranged in the module-corresponding area <NUM>. That is, the emission structures R, G, and B may be repeatedly arranged in the display area <NUM>, and the emission structures R, G, and B may be repeatedly arranged in the module-corresponding area <NUM>.

In the module-corresponding area <NUM>, a portion other than the plurality of first sub-pixel areas <NUM>, <NUM>, and <NUM> (e.g., remaining portion of the module-corresponding area <NUM>) may be defined as the transparent area <NUM>. An opening OP may be positioned in the transparent area <NUM>. In addition, the functional module FM may collect light incident from an outside through the opening OP.

The first pixel circuit areas <NUM> may be positioned adjacent to a first portion (e.g., the display area <NUM> positioned to a left of the module-corresponding area <NUM> in <FIG>) of the display area <NUM> in the pixel circuit area <NUM>, and may be arranged along a first direction D1. The second pixel circuit areas <NUM> may be positioned adjacent to a second portion (e.g., the display area <NUM> positioned to a right of the module-corresponding area <NUM> in <FIG>) of the display area <NUM> in the pixel circuit area <NUM>, and may be arranged along the first direction D1. The pixel circuit area <NUM> may be adjacent to both the display area <NUM> and the module-corresponding area <NUM> along a second direction D2 crossing the first direction D1. A thickness direction of the display device <NUM> and various components and layers thereof, may be defined along a third direction which crosses each of the first direction D1 and the second direction D2.

A pixel circuit structure (e.g., a first pixel circuit structure <NUM> of <FIG>) electrically connected to an emission structure disposed in the module-corresponding area <NUM> may be disposed in the first and second pixel circuit areas <NUM> and <NUM>. A pixel circuit structure (e.g., a second pixel circuit structure <NUM> of <FIG>) electrically connected to an emission structure disposed in the display area <NUM> may be disposed in the display area <NUM>. That is, a pixel circuit structure electrically connected to the emission structure disposed in the module-corresponding area <NUM> may not be disposed in the module-corresponding area <NUM> (e.g., may be excluded from the module-corresponding area <NUM>).

Referring to <FIG>, the second pixel circuit structure <NUM> may be disposed in the display area <NUM>. The second pixel circuit structure <NUM> may include at least one semiconductor element <NUM> (see <FIG>), at least one capacitor, and the like. The second pixel circuit structure <NUM> may drive the emission structure (e.g., the second emission structure <NUM> of <FIG>). The second pixel circuit structure <NUM> may be disposed to overlap the emission structure and be under the emission structure along a thickness direction of the display device <NUM>.

The first pixel circuit structure <NUM> may be disposed in the first and second pixel circuit areas <NUM> and <NUM>. The first pixel circuit structure <NUM> may include at least one semiconductor element, at least one capacitor, and the like. The first pixel circuit structure <NUM> may drive the emission structure (e.g., the first emission structure <NUM> of <FIG>). The first pixel circuit structure <NUM> and the emission structure may be electrically connected through a signal line <NUM>.

<FIG> is a cross-sectional view taken along lines I-I' and II-II' of <FIG>.

Referring to <FIG>, the display device <NUM> may include a functional module FM, a substrate <NUM>, a buffer layer <NUM>, a semiconductor element <NUM>, a first gate insulating layer <NUM>, a second gate insulating layer <NUM>, an interlayer insulating layer <NUM>, a phase compensation layer <NUM>, a signal line <NUM>, an etch stop layer <NUM>, a planarization layer <NUM>, a pixel defining layer <NUM>, a first emission structure <NUM>, a second emission structure <NUM> and a thin film encapsulation structure <NUM>.

Here, the semiconductor element <NUM> may include an active layer <NUM>, a first gate electrode <NUM>, a second gate electrode <NUM>, a source electrode <NUM>, and a drain electrode <NUM>. The first emission structure <NUM> may include a first lower electrode <NUM>, a first emission layer <NUM> and an upper electrode <NUM>. The second emission structure <NUM> may include a second lower electrode <NUM>, a second emission layer <NUM> and the upper electrode <NUM>. In addition, the thin film encapsulation structure <NUM> may include a first inorganic thin film encapsulation layer <NUM>, an organic thin film encapsulation layer <NUM>, and a second inorganic thin film encapsulation layer <NUM>.

As described in <FIG>, as the display device <NUM> includes the display area <NUM>, the module-corresponding area <NUM> and the pixel circuit area <NUM>, the substrate <NUM> may also include the display area <NUM>, the module-corresponding area <NUM> and the pixel circuit area <NUM> corresponding to those described above. That is, various components and layers of the display device <NUM> may also include the display area <NUM>, the module-corresponding area <NUM> and the pixel circuit area <NUM> corresponding to those described above for the display device <NUM>.

The substrate <NUM> may include a transparent material or an opaque material. In an embodiment, for example, the substrate <NUM> may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, an F-doped quartz substrate, and a soda-lime glass. It may include a glass substrate, a non-alkali glass substrate, and the like. These may be used alone or in combination with each other. In an embodiment, the substrate <NUM> may be formed of (or include) a flexible transparent resin substrate. In an embodiment, for example, the substrate <NUM> may have a structure in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. Each of the first barrier layer and the second barrier layer may include an inorganic material such as silicon oxide. Each of the first organic layer and the second organic layer may include an organic insulating material such as a polyimide-based resin, and may have flexibility.

However, although the substrate <NUM> has been described as having four layers, the configuration of the substrate <NUM> is not limited thereto. In an embodiment, for example, the substrate <NUM> may have a single layer or a plurality of layers.

The functional module FM may be disposed in the module-corresponding area <NUM>, on the lower surface of the substrate <NUM> which is furthest from the various emission structures. The functional module FM may directly contact the lower surface of the substrate <NUM>. As being in direct contact, elements may form an interface or boundary therebetween, without being limited thereto. In an embodiment, for example, the functional module FM may include the camera module. The camera module may collect light incident from outside of the display device <NUM>, and the display device <NUM> may obtain an image from the camera module.

The buffer layer <NUM> may be disposed on the substrate <NUM>. That is, the buffer layer <NUM> may be disposed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The buffer layer <NUM> may prevent diffusion of metal atoms or impurities from the substrate <NUM> to the semiconductor element <NUM>. In addition, when a surface of the substrate <NUM> is not uniform, the buffer layer <NUM> may serve to improve the flatness of the surface of the substrate <NUM>. In an embodiment, for example, the buffer layer <NUM> may include silicon oxide (SiOx), silicon nitride (SiNx), and the like. These may be used alone or in combination with each other. In an embodiment, the buffer layer <NUM> may be disposed only in the display area <NUM> and may not be disposed in the module-corresponding area <NUM>.

The active layer <NUM> may be disposed in the display area <NUM>, on the buffer layer <NUM>. Specifically, the active layer <NUM> may be disposed in the second pixel area <NUM> included in the display area <NUM>. The active layer <NUM> may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon) or an organic semiconductor. The active layer <NUM> may have a source region, a drain region, and a channel region positioned between the source region and the drain region in a direction along the substrate <NUM>.

In an embodiment, the etch stop layer <NUM> may be disposed in the module-corresponding area <NUM>, on the buffer layer <NUM>. The etch stop layer <NUM> may be disposed in an entirety of the module-corresponding area <NUM>. In addition, the etch stop layer <NUM> may be disposed on the same layer as the active layer <NUM>. That is, the etch stop layer <NUM> may include the same material as the active layer <NUM>. As being on a same layer, elements may be in a same layer as each other as respective portions of a same material layer, may form an interface with a same underlying or overlying layer, etc., without being limited thereto.

The etch stop layer <NUM> may include a transparent material. In an embodiment, the etch stop layer <NUM> may include indium gallium zinc oxide ("IGZO"), amorphous silicon, and the like. These may be used alone or in combination with each other. However, the material included in the etch stop layer <NUM> is not limited thereto, and the etch stop layer <NUM> may include other transparent materials.

In an embodiment, an etch rate of the etch stop layer <NUM> may be smaller than an etch rate of the phase compensation layer <NUM>, which will be described later.

At least one inorganic insulating layer (e.g., the first gate insulating layer <NUM>) may be disposed in the display area <NUM> on the buffer layer <NUM>. The first gate insulating layer <NUM> may cover the active layer <NUM> in the display area <NUM> and may not be disposed in the module-corresponding area <NUM>. In an embodiment, for example, the first gate insulating layer <NUM> may sufficiently cover the active layer <NUM> on the buffer layer <NUM>, and may have a substantially flat top surface without creating a step around the active layer <NUM>. In an embodiment, the first gate insulating layer <NUM> may cover the active layer <NUM> on the buffer layer <NUM>, and may be disposed along a profile of the active layer <NUM> with a uniform thickness.

The first gate insulating layer <NUM> may include an inorganic insulating material. In an embodiment, for example, the first gate insulating layer <NUM> may include silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), and the like. These may be used alone or in combination with each other.

The first gate electrode <NUM> may be disposed in the display area <NUM> on the first gate insulating layer <NUM>. Specifically, the first gate electrode <NUM> may be disposed in the second pixel area <NUM> included in the display area <NUM>. The first gate electrode <NUM> may overlap the channel region of the active layer <NUM>. In an embodiment, for example, the first gate electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

At least one inorganic insulating layer (e.g., the second gate insulating layer <NUM>) may be disposed in the display area <NUM> on the first gate insulating layer <NUM>. The second gate insulating layer <NUM> may cover the first gate electrode <NUM> in the display area <NUM> and may not be disposed in the module-corresponding area <NUM>. In an embodiment, for example, the second gate insulating layer <NUM> may sufficiently cover the first gate electrode <NUM> on the first gate insulating layer <NUM> and may have a substantially flat top surface without generating a step difference around the first gate electrode <NUM>. In an embodiment, the second gate insulating layer <NUM> may cover the first gate electrode <NUM> on the first gate insulating layer <NUM> and may be disposed along a profile of the first gate electrode <NUM> with a uniform thickness.

The second gate insulating layer <NUM> may include an inorganic insulating material. In an embodiment, for example, the second gate insulating layer <NUM> may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, and the like. These may be used alone or in combination with each other.

The second gate electrode <NUM> may be disposed in the display area <NUM>, on the second gate insulating layer <NUM>. Specifically, the second gate electrode <NUM> may be disposed in the second pixel area <NUM> included in the display area <NUM>. The second gate electrode <NUM> may overlap the first gate electrode <NUM>. The first gate electrode <NUM> and the second gate electrode <NUM> may function together as a capacitor. In an embodiment, for example, the second gate electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

The interlayer insulating layer <NUM> may be disposed in the display area <NUM>, on the second gate insulating layer <NUM>. The interlayer insulating layer <NUM> may cover the second gate electrode <NUM> in the display area <NUM>. In an embodiment, for example, the interlayer insulating layer <NUM> may sufficiently cover the second gate electrode <NUM> on the second gate insulating layer <NUM> and may have a substantially flat top surface without creating a step around the second gate electrode <NUM>. In an embodiment, the interlayer insulating layer <NUM> may cover the second gate electrode <NUM> on the second gate insulating layer <NUM> and may be disposed along the profile of the second gate electrode <NUM> with a uniform thickness.

The interlayer insulating layer <NUM> may include an inorganic insulating material. In an embodiment, for example, the insulating interlayer <NUM> may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, and the like. These may be used alone or in combination with each other. Here, the interlayer insulating layer <NUM> may be referred to as an inorganic insulating layer.

In a conventional display device, a phase difference between a first light L1 passing through a portion overlapping with a signal line <NUM>, and a second light L2 passing through a portion not overlapping with the signal line <NUM>, among the lights incident on a conventional module-corresponding area in which a functional member (e.g., a camera module) is disposed may occur. In this case, a flare phenomenon in which an image photographed by the camera module appears blurry may occur.

According to the invention, the phase compensation layer <NUM> is disposed in the module-corresponding area <NUM>, on the etch stop layer <NUM>. Specifically, the phase compensation layer <NUM> may be disposed in the transparent area <NUM> included in the module-corresponding area <NUM>. The phase compensation layer <NUM> (e.g., light phase compensation layer) serves to compensate for the phase difference between a first light L1 passing through a portion overlapping the signal line <NUM>, and a second light L2 passing through a portion not overlapping the signal line <NUM> (e.g., adjacent to or spaced apart from the signal line <NUM>), among the lights incident on the module-corresponding area <NUM> (e.g., external light). Accordingly, an occurrence of the flare phenomenon may be reduced.

The phase compensation layer <NUM> includes the same material as the interlayer insulating layer <NUM>. That is, the phase compensation layer <NUM> includes an inorganic insulating material. In an embodiment, the phase compensation layer <NUM> may include silicon oxide, silicon nitride, and the like. When the phase compensation layer <NUM> includes silicon oxide, a refractive index of the phase compensation layer <NUM> may be about <NUM> in a visible light region. When the phase compensation layer <NUM> includes silicon nitride, a refractive index of the phase compensation layer <NUM> may be about <NUM> to about <NUM> in a visible light region.

The source electrode <NUM> and the drain electrode <NUM> may be disposed in the display area <NUM>, on the interlayer insulating layer <NUM>. Specifically, the source electrode <NUM> and the drain electrode <NUM> may be disposed in the second pixel area <NUM> included in the display area <NUM>. The source electrode <NUM> may be connected to the source region of the active layer <NUM> through a first contact hole formed by (or provided by) removing first portions of the first gate insulating layer <NUM>, the second gate insulating layer <NUM> and the interlayer insulating layer <NUM>. The drain electrode <NUM> may be connected to the drain region of the active layer <NUM> through a second contact hole formed by removing second portions of the first gate insulating layer <NUM>, the second gate insulating layer <NUM> and the interlayer insulating layer <NUM>. Each of the source electrode <NUM> and the drain electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

The signal line <NUM> is disposed on the phase compensation layer <NUM>. The signal line <NUM> overlaps the phase compensation layer <NUM>. As shown in <FIG>, the signal line <NUM> may be electrically connected to the first lower electrode <NUM> through a contact hole formed by removing a portion of the planarization layer <NUM> positioned in the module-corresponding area <NUM>. The signal line <NUM> may extend from the module-corresponding area <NUM> to the pixel circuit area <NUM>, to be electrically connected to the first pixel circuit structure <NUM>. That is, the signal line <NUM> connects the first emission structure <NUM> to the pixel circuit area <NUM>.

A thickness of the signal line <NUM> along the thickness direction, may be smaller than a thickness of each of the source electrode <NUM> and the drain electrode <NUM>. In an embodiment, for example, the signal line <NUM> may be substantially transparent.

The signal line <NUM> may include a conductive metal oxide, a transparent conductive material, and the like. Examples of materials that can be used for the signal line <NUM> may be indium tin oxide ("ITO"), indium zinc oxide ("IZO"), indium gallium oxide ("IGO"), tin oxide ("SnO<NUM>"), zinc oxide ("ZnO"), and the like. These may be used alone or in combination with each other. In an embodiment, the signal line <NUM> may include indium tin oxide. When the signal line <NUM> includes indium tin oxide, the refractive index of the signal line <NUM> may be about <NUM> or more in a visible light region.

The planarization layer <NUM> may be disposed on the source electrode <NUM> and drain electrode <NUM> disposed in the display area <NUM> and on the etch stop layer <NUM> disposed in the module-corresponding area <NUM>. That is, the planarization layer <NUM> may extend from the display area <NUM> to the module-corresponding area <NUM>. The planarization layer <NUM> may cover the source electrode <NUM> and the drain electrode <NUM> in the display area <NUM>, and may cover the phase compensation layer <NUM> and the signal line <NUM> in the module-corresponding area <NUM>. The planarization layer <NUM> may have a relatively large thickness. The planarization layer <NUM> may include an organic insulating material or an inorganic insulating material. In an embodiment, the planarization layer <NUM> may include an organic insulating material. Examples of the organic insulating material that can be used for the planarization layer <NUM> may be a photoresist, a polyacrylic resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. These may be used alone or in combination with each other. Where the planarization layer <NUM> includes a substantially transparent siloxane-based resin, the planarization layer <NUM> may be referred to as an organic insulating layer.

In an embodiment, a refractive index of the planarization layer <NUM> may be greater than a refractive index of the phase compensation layer <NUM> and less than that of the signal line <NUM>. In an embodiment, for example, a refractive index of the planarization layer <NUM> may be about <NUM> in a visible light region. In this case, the phase compensation layer <NUM> may include silicon oxide, and the signal line <NUM> may include indium tin zinc oxide.

The second lower electrode <NUM> may be disposed in the display area <NUM>, on the planarization layer <NUM>. Specifically, the second lower electrode <NUM> may be disposed in the second pixel area <NUM> included in the display area <NUM>. The second lower electrode <NUM> may be connected to the drain electrode <NUM> through a contact hole formed by removing a portion of the planarization layer <NUM>. The second lower electrode <NUM> may be electrically connected to the semiconductor element <NUM>. The second lower electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. For example, the second lower electrode <NUM> may have a stacked structure of ITO/Ag/ITO.

The first lower electrode <NUM> may be disposed in the module-corresponding area <NUM>, on the planarization layer <NUM>. Specifically, the first lower electrode <NUM> may be disposed in the first pixel area <NUM> included in the module-corresponding area <NUM>. As described above, the first lower electrode <NUM> may be connected to the signal line <NUM> through a contact hole formed by removing a portion of the planarization layer <NUM> (see <FIG>). The first lower electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In addition, the first lower electrode <NUM> may have the same structure as the second lower electrode <NUM>. In an embodiment, the first lower electrode <NUM> may have a structure different from a structure of the second lower electrode <NUM>.

The pixel defining layer <NUM> may be disposed on a portion of the display area <NUM> and a portion of the module-corresponding area <NUM>, on the planarization layer <NUM>. That is, the pixel defining layer <NUM> may not be disposed in the transparent area <NUM>. The pixel defining layer <NUM> may expose a portion of the second lower electrode <NUM> in the display area <NUM> to outside the pixel defining layer <NUM>, and may expose a portion of the first lower electrode <NUM> in the module-corresponding area <NUM> to outside the pixel defining layer <NUM>. In addition, an opening OP exposing layers in the transparent area <NUM> to outside the pixel defining layer <NUM> may be formed in (or defined by) the pixel defining layer <NUM>. The pixel defining layer <NUM> may include an organic insulating material or an inorganic insulating material. In an embodiment, the pixel defining layer <NUM> may include an organic insulating material.

The second emission layer <NUM> may be disposed on the second lower electrode <NUM>. The first emission layer <NUM> may be disposed on the first lower electrode <NUM>. Each of the first emission layer <NUM> and the second emission layer <NUM> may be formed using at least one of emission materials that emit different color lights (e.g., red light, green light, blue light, and the like) according to sub-pixels.

The upper electrode <NUM> may be disposed in an entirety of the display area <NUM> and the module-corresponding area <NUM>, on the substrate <NUM>. The upper electrode <NUM> may be disposed along the profile of the first emission layer <NUM>, the second emission layer <NUM>, and the pixel defining layer <NUM>. The upper electrode <NUM> may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

The first inorganic thin film encapsulation layer <NUM> may be disposed on the upper electrode <NUM>. The first inorganic thin film encapsulation layer <NUM> may be disposed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The first inorganic thin film encapsulation layer <NUM> may prevent (or reduce) the first emission structure <NUM> and the second emission structure <NUM> from being deteriorated due to penetration of moisture, oxygen, and the like. In addition, the first inorganic thin film encapsulation layer <NUM> may also function to protect the first emission structure <NUM> and the second emission structure <NUM> from external impact. In an embodiment, for example, the first inorganic thin film encapsulation layer <NUM> may include an inorganic insulating material having flexibility.

The organic thin film encapsulation layer <NUM> may be disposed on the first inorganic thin film encapsulation layer <NUM>. The organic thin film encapsulation layer <NUM> may be disposed in an entirety of the display area <NUM> and the module-corresponding area <NUM>. The organic thin film encapsulation layer <NUM> may improve the flatness of the display device <NUM>, and may protect the first emission structure <NUM> and the second emission structure <NUM> together with the first inorganic thin film encapsulation layer <NUM>. The organic thin film encapsulation layer <NUM> may include an organic insulating material having flexibility.

The second inorganic thin film encapsulation layer <NUM> may be disposed on the organic thin film encapsulation layer <NUM>. The second inorganic thin film encapsulation layer <NUM> may be disposed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The second inorganic thin film encapsulation layer <NUM> may be used together with the first inorganic thin film encapsulation layer <NUM> to prevent the first emission structure <NUM> and the second emission structure <NUM> from being deteriorated due to penetration of moisture, oxygen, and the like.

In addition, the second inorganic thin film encapsulation layer <NUM> may also perform a function to protect the first emission structure <NUM> and the second emission structure <NUM> together with the first inorganic thin film encapsulation layer <NUM> and the organic thin film encapsulation layer <NUM> from external impact. In an embodiment, for example, the second inorganic thin film encapsulation layer <NUM> may include an inorganic insulating material having flexibility.

In one or more embodiments of the display device <NUM>, as the phase compensation layer <NUM> including an inorganic insulating material is disposed in the module-corresponding area <NUM>, on the etch stop layer <NUM>, an occurrence of the flare phenomenon may be reduced.

However, in a relatively large area display device, in the process of patterning the phase compensation layer <NUM>, a thickness of the phase compensation layer <NUM> may become non-uniform.

In one or more embodiments of the display device <NUM>, as the etch stop layer <NUM> including a transparent material is disposed in the module-corresponding area <NUM>, between the substrate <NUM> and the phase compensation layer <NUM>, a thickness non-uniformity of the phase compensation layer <NUM> in the large area display device may be improved.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views illustrating embodiments of structures in a method of manufacturing (or providing) the display device <NUM> of <FIG>.

Referring to <FIG>, the substrate <NUM> including a transparent material may be formed on a rigid glass substrate <NUM> (e.g., a base layer). The substrate <NUM> may be formed using a flexible transparent resin substrate. In an embodiment, the substrate <NUM> may be formed using a quartz substrate, a synthetic quartz substrate, a glass substrate, and the like. In this case, the rigid glass substrate <NUM> may be omitted.

In an embodiment, for example, when the substrate <NUM> includes a transparent material, since the substrate <NUM> is thin and flexible, the substrate <NUM> may be formed on the rigid glass substrate <NUM> to support the formation of the semiconductor element <NUM>, the first emission structure <NUM>, the second emission structure <NUM>, and the thin film encapsulation structure <NUM>, and the like. As will be described later, after the thin film encapsulation structure <NUM> is formed, the rigid glass substrate <NUM> may be removed.

The substrate <NUM> may include the display area <NUM>, the module-corresponding area <NUM>, and the pixel circuit area <NUM>.

The buffer layer <NUM> may be formed on the substrate <NUM>. The buffer layer <NUM> may be formed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. According to the type of the substrate <NUM>, two or more buffer layers <NUM> may be formed on the substrate <NUM> or the buffer layer <NUM> may not be formed. The buffer layer <NUM> may be formed using silicon oxide, silicon nitride, and the like.

The active layer <NUM> may be formed in the display area <NUM> on the buffer layer <NUM>. The active layer <NUM> may be formed using a metal oxide semiconductor, an inorganic semiconductor, or an organic semiconductor. The active layer <NUM> may include a source region, a drain region, and a channel region positioned between the source region and the drain area.

Referring to <FIG>, the etch stop layer <NUM> may be formed in the module-corresponding area <NUM>, on the buffer layer <NUM>. That is, the etch stop layer <NUM> may be formed on the same layer as the active layer <NUM>. In addition, the etch stop layer <NUM> may be formed in an entirety of the module-corresponding area <NUM>. In an embodiment, for example, the etch stop layer <NUM> may be formed using a transparent material. In an embodiment, the etch stop layer <NUM> may be formed using indium gallium zinc oxide, amorphous silicon, and the like.

The etch stop layer <NUM> may be formed in the same process as the active layer <NUM>. That is, the etch stop layer <NUM> may be simultaneously formed using the same material as the active layer <NUM>. In an embodiment, the etch stop layer <NUM> may be formed in a process different from a process of the active layer <NUM>. In an embodiment, for example, after the active layer <NUM> is formed, the etch stop layer <NUM> may be formed. In this case, the etch stop layer <NUM> may be formed using a material different from a material of the active layer <NUM>.

Referring to <FIG>, the first gate insulating layer <NUM> may be formed on the buffer layer <NUM>. The first gate insulating layer <NUM> may cover the active layer <NUM> in the display area <NUM> and may extend to the module-corresponding area <NUM>. That is, the first gate insulating layer <NUM> may be formed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The first gate insulating layer <NUM> may be formed using silicon oxide, silicon nitride, silicon oxynitride, and the like.

The first gate electrode <NUM> may be formed in the display area <NUM> on the first gate insulating layer <NUM>. The first gate electrode <NUM> may be formed to overlap the channel region of the active layer <NUM>. The first gate electrode <NUM> may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like.

The second gate insulating layer <NUM> may be formed on the first gate insulating layer <NUM>. The second gate insulating layer <NUM> may cover the first gate electrode <NUM> in the display area <NUM> and may extend to the module-corresponding area <NUM>. That is, the second gate insulating layer <NUM> may be formed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The second gate insulating layer <NUM> may be formed using silicon oxide, silicon nitride, silicon oxynitride, and the like.

Referring to <FIG>, the first gate insulating layer <NUM> and the second gate insulating layer <NUM> disposed in the module-corresponding area <NUM> may be removed. Removal of the first gate insulating layer <NUM> and the second gate insulating layer <NUM> from the module-corresponding area <NUM> exposes the etch stop layer <NUM> to outside the first gate insulating layer <NUM> and the second gate insulating layer <NUM>.

Referring to <FIG>, the second gate electrode <NUM> may be formed in the display area <NUM>, on the second gate insulating layer <NUM>. The second gate electrode <NUM> may overlap the first gate electrode <NUM>. The second gate electrode <NUM> may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like.

The interlayer insulating layer <NUM> may be disposed on the second gate insulating layer <NUM>. The interlayer insulating layer <NUM> may cover the second gate electrode <NUM> in the display area <NUM> and may extend to the module-corresponding area <NUM>. That is, the interlayer insulating layer <NUM> may be formed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. The interlayer insulating layer <NUM> may be formed using silicon oxide, silicon nitride, silicon oxynitride, and the like.

Referring to <FIG>, the source electrode <NUM> and the drain electrode <NUM> may be formed in the display area <NUM> on the interlayer insulating layer <NUM>. The source electrode <NUM> may be connected to the source region of the active layer <NUM> through a first contact hole formed by removing a first portion of each of the first gate insulating layer <NUM>, the second gate insulating layer <NUM> and the interlayer insulating layer <NUM>. The drain electrode <NUM> may be connected to the drain region of the active layer <NUM> through a second contact hole formed by removing a second portion of each of the first gate insulating layer <NUM>, the second gate insulating layer <NUM> and the interlayer insulating layer <NUM>. Each of the source electrode <NUM> and the drain electrode <NUM> may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like.

Accordingly, the semiconductor element <NUM> including the active layer <NUM>, the first gate electrode <NUM>, the second gate electrode <NUM>, the source electrode <NUM> and the drain electrode <NUM>, may be formed in the second pixel area <NUM>.

A conductive film <NUM> may be formed in the module-corresponding area <NUM>, on the interlayer insulating layer <NUM>. The conductive film <NUM> may be formed using a conductive metal oxide, a transparent conductive material, and the like. In an embodiment, for example, the conductive film <NUM> may be formed using ITO, IZO, IGO, SnO<NUM>, ZnO, and the like.

Referring to <FIG> and <FIG>, the signal line <NUM> may be formed by patterning the conductive film <NUM> (e.g., signal line material layer). In an embodiment, the signal line <NUM>, the source electrode <NUM>, and the drain electrode <NUM> may be formed on the same layer, but is not limited thereto, and may be formed in different processes using different materials from each other. In an embodiment, for example, after the source electrode <NUM> and the drain electrode <NUM> are formed, the signal line <NUM> may be formed.

Referring to <FIG> and <FIG>, the phase compensation layer <NUM> may be formed by patterning the interlayer insulating layer <NUM> disposed in the module-corresponding area <NUM>. Specifically, the phase compensation layer <NUM> may be formed at a location corresponding to the signal line <NUM>, using the signal line <NUM> as a mask. That is, after the phase compensation layer <NUM> (e.g., phase compensation pattern) is formed, an upper surface of the etch stop layer <NUM> that does not overlap the signal line <NUM> in the module-corresponding area <NUM>, may be exposed to outside the interlayer insulating layer <NUM> (or the phase compensation pattern) and the signal line <NUM>. However, in an embodiment, a portion of the interlayer insulating layer <NUM> that does not overlap the signal line <NUM> may remain in the module-corresponding area <NUM>.

In an embodiment, for example, the phase compensation layer <NUM> may be formed using silicon oxide, silicon nitride, and the like. That is, the phase compensation layer <NUM> may be formed using the same material as the interlayer insulating layer <NUM>.

Referring to <FIG>, the planarization layer <NUM> may be formed on the interlayer insulating layer <NUM> and the etch stop layer <NUM>. That is, the planarization layer <NUM> may cover the source electrode <NUM> and the drain electrode <NUM> in the display area <NUM> and may extend to the module-corresponding area <NUM>. The planarization layer <NUM> may cover the phase compensation layer <NUM> and the signal line <NUM> in the module-corresponding area <NUM>. The planarization layer <NUM> may be formed using a photoresist, a polyacrylic resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. The planarization layer <NUM> may be formed using a substantially transparent siloxane-based resin.

Referring to <FIG>, the second lower electrode <NUM> may be formed in the display area <NUM>, on the planarization layer <NUM>. The first lower electrode <NUM> may be formed in the module-corresponding area <NUM>, on the planarization layer <NUM>. The second lower electrode <NUM> may be connected to the drain electrode <NUM> through a contact hole formed by removing a portion of the planarization layer <NUM>. The first lower electrode <NUM> may be connected to the signal line <NUM> through a contact hole formed by removing a portion of the planarization layer <NUM> (see box surrounding 'x' in <FIG>). Each of the first lower electrode <NUM> and the second lower electrode <NUM> may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. In an embodiment, for example, each of the first lower electrode <NUM> and the second lower electrode <NUM> may have a stacked structure of ITO/Ag/ITO.

The pixel defining layer <NUM> may be formed in the display area <NUM> and a portion of the module-corresponding area <NUM>, on the planarization layer <NUM>. The pixel defining layer <NUM> may expose a portion of the second lower electrode <NUM> in the display area <NUM>, and may expose a portion of the first lower electrode <NUM> in the module-corresponding area <NUM>. In addition, the opening OP exposing layers in the transparent area <NUM> may be formed in the pixel defining layer <NUM>. The pixel defining layer <NUM> may be formed using an organic insulating material.

The second emission layer <NUM> may be formed on the second lower electrode <NUM>, and the first emission layer <NUM> may be formed on the first lower electrode <NUM>. Each of the first emission layer <NUM> and the second emission layer <NUM> may be formed using at least one of light emitting materials capable of emitting light of different colors according to sub-pixels.

The upper electrode <NUM> may be formed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM> on the substrate <NUM>. The upper electrode <NUM> may be formed along the profile of the first emission layer <NUM>, the second emission layer <NUM>, and the pixel defining layer <NUM>. The upper electrode <NUM> may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like.

Accordingly, the second emission structure <NUM> including the second lower electrode <NUM>, the second emission layer <NUM> and the upper electrode <NUM> may be formed in the second pixel area <NUM>, and the first emission structure <NUM> including the first lower electrode <NUM>, the first emission layer <NUM> and the upper electrode <NUM> may be formed in the first pixel area <NUM>.

The first inorganic thin film encapsulation layer <NUM> may be formed in the display area <NUM> and the module-corresponding area <NUM>, on the upper electrode <NUM>. In an embodiment, for example, the first inorganic thin film encapsulation layer <NUM> may be formed using an inorganic insulating material having flexibility. The organic thin film encapsulation layer <NUM> may be formed in the display area <NUM> and the module-corresponding area <NUM>, on the first inorganic thin film encapsulation layer <NUM>. In an embodiment, for example, the organic thin film encapsulation layer <NUM> may be formed using an organic insulating material having flexibility. The second inorganic thin film encapsulation layer <NUM> may be formed on the organic thin film encapsulation layer <NUM>. The second inorganic thin film encapsulation layer <NUM> may be formed using an inorganic insulating material having flexibility.

Accordingly, the thin film encapsulation structure <NUM> including the first inorganic thin film encapsulation layer <NUM>, the organic thin film encapsulation layer <NUM>, and the second inorganic thin film encapsulation layer <NUM> may be formed. After the thin film encapsulation structure <NUM> is formed, the glass substrate <NUM> may be removed from the substrate <NUM> to expose a lower surface of the substrate <NUM>.

Referring back to <FIG>, the functional module FM may be formed in the module-corresponding area <NUM>, on the lower surface of the substrate <NUM>. In an embodiment, for example, the functional module FM may include the camera module and the like.

Accordingly, the display device <NUM> shown in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> may be provided.

<FIG> is a cross-sectional view illustrating an embodiment of a display device <NUM>.

Referring to <FIG>, the display device <NUM> may include a functional module FM, a substrate <NUM>, a buffer layer <NUM>, a semiconductor element <NUM>, a first gate insulating layer <NUM>, a second gate insulating layer <NUM>, an interlayer insulating layer <NUM>, a phase compensation layer <NUM>, a signal line <NUM>, an etch stop layer <NUM>, a planarization layer <NUM>, a pixel defining layer <NUM>, a first emission structure <NUM>, a second emission structure <NUM> and a thin film encapsulation structure <NUM>. The display device <NUM> of <FIG> may be substantially the same as or similar to the display device <NUM> described with reference to <FIG> except for the etch stop layer <NUM>. Hereinafter, overlapping descriptions will be omitted.

The etch stop layer <NUM> may be disposed in the module-corresponding area <NUM>, on the buffer layer <NUM>. In an embodiment, the etch stop layer <NUM> may be patterned to define an etch stop pattern which overlaps each of the phase compensation layer <NUM> and the signal line <NUM>. In this case, the etch stop layer <NUM> may include amorphous silicon. The buffer layer <NUM> may be exposed to outside the phase compensation layer <NUM>, the signal line <NUM> and the etch stop layer <NUM>, within the module-corresponding area <NUM>.

Although the etch stop layer <NUM> and the active layer <NUM> are formed on the same layer, the invention is not limited thereto, and the etch stop layer <NUM> and the active layer <NUM> may be formed using different materials and in different processes. In an embodiment, for example, after the active layer <NUM> is formed, the etch stop layer <NUM> may be formed. Specifically, after the phase compensation layer <NUM> is patterned to provide a phase compensation pattern, the etch stop layer <NUM> may be patterned to provide an etch stop pattern.

Referring to <FIG>, the display device <NUM> may include a functional module FM, a substrate <NUM>, a buffer layer <NUM>, a semiconductor element <NUM>, a first gate insulating layer <NUM>, a second gate insulating layer <NUM>, an interlayer insulating layer <NUM>, a phase compensation layer <NUM>, a signal line <NUM>, an etch stop layer <NUM>, a planarization layer <NUM>, a pixel defining layer <NUM>, a first emission structure <NUM>, a second emission structure <NUM>, a thin film encapsulation structure <NUM>. The display device <NUM> of <FIG> may be substantially the same as or similar to the display device <NUM> described with reference to <FIG> except for the first gate insulating layer <NUM> and the second gate insulating layer <NUM> disposed in the module-corresponding area <NUM>. Hereinafter, overlapping descriptions will be omitted.

At least one inorganic insulating layer (e.g., the first gate insulating layer <NUM>, the second gate insulating layer <NUM>, and the like) may be disposed on the buffer layer <NUM>. In an embodiment, for example, the first gate insulating layer <NUM> may be disposed on the buffer layer <NUM>, and the second gate insulating layer <NUM> may be disposed on the first gate insulating layer <NUM>. In an embodiment, the first gate insulating layer <NUM> and the second gate insulating layer <NUM> may be disposed in an entirety of the display area <NUM> and an entirety of the module-corresponding area <NUM>. That is, the first gate insulating layer <NUM> and the second gate insulating layer <NUM> in the module-corresponding area <NUM> may remain on the substrate <NUM>, without being removed. In an embodiment, each of the first gate insulating layer <NUM> and the second gate insulating layer <NUM> may have a multilayer structure including a plurality of insulating layers.

The etch stop layer <NUM> may be disposed in the module-corresponding area <NUM>, on the second gate insulating layer <NUM>. In addition, the etch stop layer <NUM> may be disposed in an entirety of the module-corresponding area <NUM> to face the substrate with both the first gate insulating layer <NUM> and the second gate insulating layer <NUM> therebetween.

In an embodiment, the etch stop layer <NUM> may be formed in a process different from a process of the active layer <NUM>. In an embodiment, for example, after the active layer <NUM> is formed, the etch stop layer <NUM> may be formed. In this case, the etch stop layer <NUM> and the active layer <NUM> may include different materials.

Referring to <FIG>, the display device <NUM> may include a functional module FM, a substrate <NUM>, a buffer layer <NUM>, a semiconductor element <NUM>, a first gate insulating layer <NUM>, and a second gate insulating layer <NUM>, an interlayer insulating layer <NUM>, a phase compensation layer <NUM>, a signal line <NUM>, an etch stop layer <NUM>, a planarization layer <NUM>, a pixel defining layer <NUM>, a first emission structure <NUM>, a second emission structure <NUM> and a thin film encapsulation structure <NUM>. The display device <NUM> of <FIG> may be substantially the same as or similar to the display device <NUM> described with reference to <FIG> except for the etch stop layer <NUM> disposed in the module-corresponding area <NUM>. Hereinafter, overlapping descriptions will be omitted.

The etch stop layer <NUM> may be disposed in the module-corresponding area <NUM>, on the second gate insulating layer <NUM>. In addition, referring back to <FIG>, the etch stop layer <NUM> may be patterned to overlap each of the phase compensation layer <NUM> and the signal line <NUM>.

One or more embodiment of the present disclosure can be applied to various display devices that may include an image-generating device. In an embodiment, for example, the present disclosure can be applied to high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, in-vehicle navigation systems, televisions, computer monitors, notebook computers, and the like.

Claim 1:
A display device (<NUM>, <NUM>, <NUM>, <NUM>) comprising:
a display area (<NUM>), a pixel circuit area (<NUM>) adjacent to the display area (<NUM>), and a functional module area (<NUM>) between the display area (<NUM>) and the pixel circuit area (<NUM>);
an inorganic insulating layer (<NUM>) in the display area (<NUM>);
a light phase compensation layer (<NUM>) in the functional module area (<NUM>) and including a same material as the inorganic insulating layer (<NUM>) of the display area (<NUM>);
a signal line (<NUM>) corresponding to the light phase compensation layer (<NUM>), in the functional module area (<NUM>), and extending from the functional module area (<NUM>) to the pixel circuit area (<NUM>); and
an organic insulating layer (<NUM>) facing the inorganic insulating layer (<NUM>), in the display area (<NUM>), and extending from the display area (<NUM>) to the functional module area (<NUM>) to face the light phase compensation layer (<NUM>) with the signal line (<NUM>) therebetween,
wherein the light phase compensation layer (<NUM>) compensates for the phase difference between a first light (L1) passing through a portion overlapping the signal line (<NUM>), and a second light (L2) passing through a portion not overlapping the signal line (<NUM>),
wherein both the first light (L1) and second light (L2) are external light, incident to the functional module area (<NUM>), and
wherein the signal line (<NUM>) overlaps the light phase compensation layer (<NUM>).