Patent Description:
Conventionally, a column analog to digital converter (ADC) system in which an ADC is arranged for every column outside a pixel array section and pixel signals are sequentially read row by row has been used in a solid-state imaging element for the purpose of miniaturizing pixels. In this column ADC system, when exposure is performed by a rolling shutter system in which exposure is started row by row, there is a possibility that rolling shutter distortion occurs. Thus, proposed is a solid-state imaging element in which a pair of capacitors is provided for each pixel to hold a reset level and a signal level in the capacitors in order to achieve a global shutter system in which exposure is simultaneously started in all pixels (see, for example, Non-Patent Document <NUM>). The pair of capacitors is connected in series to a source follower circuit via a node, and the reset level and the signal level are sequentially read by the source follower circuit.

<CIT> discloses a solid-state imaging device in which a signal retaining part is provided with a first sampling part and a second sampling part, each of which is formed by one sampling transistor and one sampling capacitor. The coupling node between the two sampling parts is a retaining node, which is used as a bidirectional port. With such a configuration, the solid-state imaging device is configured as a solid-state imaging element that has a global shutter function that achieves substantially the same signal amplitude as in the differential reading scheme with four transistors.

<CIT> discloses an amplification-type solid state imaging device with a pixel array that is formed from a plurality of pixels, and a control circuit. Each pixel is provided with: a light receiving element; a first amplification transistor which amplifies and outputs a signal from the light receiving element; capacities which maintain the signal from the first amplification transistor; capacity-switch transistors which control the input and output of the capacities; and a second amplification transistor which amplifies and outputs the signal from the capacities. After sequentially turning on the capacity-switch transistors, and sequentially entering a signal from the first amplification transistor into the capacities, the control circuit sequentially turns on the capacity-switch transistors, and sequentially reads out the signals entered in the capacities.

In the above-described conventional technology, the global shutter system in the column ADC system is achieved by holding the reset level and the signal level in the pair of capacitors for every pixel. However, when a transistor in the source follower circuit initializes the node connected to the capacitor, there is a problem that kTC noise (in other words, reset noise) at a level corresponding to the capacitor is generated so that image quality of image data is degraded by the noise.

The present technology has been made in view of such a situation, and an object thereof is to improve image quality in a solid-state imaging element that simultaneously performs exposure in all pixels.

According to an aspect, the present invention provides a solid-state imaging element in accordance with independent claim <NUM>. The preferred embodiment of the invention is shown in <FIG> and described as the first modification of the first embodiment in paragraphs <NUM> to <NUM> below. Any further embodiment, example, aspect, or modification in the description may include some but not all features as literally defined in the claims and is present for illustration purposes only. Further aspects are set forth in the dependent claims, the drawings and the following description.

The present technology has been made to solve the above-described problem, and a first aspect thereof relates to a solid-state imaging element and a method for controlling the same, the solid-state imaging element including: first and second capacitive elements; an upstream circuit that sequentially generates a reset level and a signal level corresponding to an exposure amount and causes each of the first and second capacitive elements to hold the reset level and the signal level; a selection circuit that sequentially performs control to connect one of the first and second capacitive elements to a predetermined downstream node, control to disconnect both the first and second capacitive elements from the downstream node, and control to connect another of the first and second capacitive elements to the downstream node; a downstream reset transistor that initializes a level of the downstream node when both the first and second capacitive elements are disconnected from the downstream node; and a downstream circuit that sequentially reads the reset level and the signal level from the first and second capacitive elements via the downstream node and outputs the reset level and the signal level. This brings about an effect that kTC noise is reduced.

Furthermore, in the first aspect, an upstream selection transistor that opens and closes a path between the upstream circuit and a predetermined upstream node and an upstream reset transistor that initializes a level of the upstream node may be further provided, and the first and second capacitive elements may respectively have first ends connected in common to the upstream node and second ends connected to the selection circuit. This brings about an effect that noise from the upstream circuit is blocked.

Furthermore, in the first aspect, the upstream selection transistor may transition to a closed state over a period in which the upstream circuit causes each of the first and second capacitive elements to hold the reset level and the signal level, and the upstream reset transistor may initialize the level of the upstream node in a period in which the downstream circuit sequentially reads the reset level and the signal level from the first and second capacitive elements. This brings about an effect that a potential of the upstream node is fixed at the time of reading.

Furthermore, in the first aspect, the upstream circuit may include: a photoelectric conversion element; an upstream transfer transistor that transfers a charge from the photoelectric conversion element to a floating diffusion; a first reset transistor that initializes the floating diffusion; and an upstream amplification transistor that amplifies a voltage of the floating diffusion and outputs the amplified voltage to a predetermined upstream node, and the first and second capacitive elements may respectively have first ends connected in common to the upstream node and second ends connected to the selection circuit. This brings about an effect that a signal corresponding to a potential of the floating diffusion is supplied to the upstream node.

Furthermore, in the first aspect, a switching section that adjusts a source voltage to be supplied to a source of the upstream amplification transistor may be further provided, the upstream circuit may further include a current source transistor connected to a drain of the upstream amplification transistor, and the current source transistor may transition from an on state to an off state after an exposure period ends. This brings about an effect that a source follower in the upstream stage is in the off state at the time of reading.

Furthermore, in the first aspect, the switching section may supply a predetermined power supply voltage as the source voltage in the exposure period, and supplies a generation voltage, different from the power supply voltage, as the source voltage after the exposure period ends. This brings about an effect that a source voltage of the source follower in the upstream stage is adjusted.

Furthermore, in the first aspect, a difference between the power supply voltage and the generation voltage may substantially match a sum of a variation amount caused by reset feedthrough of the first reset transistor and a gate-source voltage of the upstream amplification transistor. This brings about an effect that the potential of the upstream node is equalized between the time of exposure and the time of reading.

Furthermore, in the first aspect, the upstream transfer transistor may transfer the charge to the floating diffusion and the first reset transistor may initialize the photoelectric conversion element together with the floating diffusion at a predetermined exposure start timing, and the upstream transfer transistor may transfer the charge to the floating diffusion at a predetermined exposure end timing. This brings about an effect that a pixel signal corresponding to the exposure amount is generated.

Furthermore, in the first aspect, the upstream circuit may further include a discharge transistor that discharges the charge from the photoelectric conversion element. This brings about an effect that the photoelectric conversion element is initialized.

Furthermore, in the first aspect, the first reset transistor may initialize the floating diffusion, and the discharge transistor discharges the charge from the photoelectric conversion element before a predetermined exposure start timing, and the upstream transfer transistor may transfer the charge to the floating diffusion at a predetermined exposure end timing. This brings about an effect that an extremely short exposure period is achieved.

Furthermore, in the first aspect, a control circuit that controls a reset power supply voltage of the upstream circuit is further provided, the first reset transistor may initialize a voltage of the floating diffusion to the reset power supply voltage, and the control circuit may set the reset power supply voltage to a voltage different from a voltage during an exposure period in a reading period in which the reset level and the signal level are read. This brings about an effect that photo response non-uniformity is improved.

Furthermore, in the first aspect, a difference between the reset power supply voltage in the reading period and the reset power supply voltage in the exposure period may substantially match a variation amount caused by reset feedthrough of the first reset transistor. This brings about an effect that photo response non-uniformity is improved.

Furthermore, in the first aspect, a first reset signal may be input to a gate of the first reset transistor, and an amplitude of the first reset signal may be a value obtained by adding a predetermined margin to a value corresponding to a dynamic range. This brings about an effect that a blackening phenomenon is suppressed.

Furthermore, in the first aspect, a digital signal processing section that adds a pair of consecutive frames may be further provided, and the upstream circuit may cause one of the first and second capacitive elements to hold the reset level in an exposure period of one of the pair of frames and then cause another of the first and second capacitive elements to hold the signal level, and cause the another of the first and second capacitive elements to hold the reset level in an exposure period of another of the pair of frames and then cause the one of the first and second capacitive elements to hold the signal level. This brings about an effect that photo response non-uniformity is improved.

Furthermore, in the first aspect, an analog-to-digital converter that sequentially converts the output reset level and the output signal level into digital signals may be further provided. This brings about an effect that digital image data is generated.

Furthermore, in the first aspect, the analog-to-digital converter may include: a comparator that compares a level of a vertical signal line that transmits the reset level and the signal level with a predetermined ramp signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted and outputs the digital signal indicating the count value. This brings about an effect that analog-digital conversion is achieved by a simple configuration.

Furthermore, in the first aspect, the comparator may include: a comparison unit that compares levels of a pair of input terminals and outputs a comparison result; and an input-side selector that selects any of the vertical signal line and a node with a predetermined reference voltage and connects the selected vertical signal line or node to one of the pair of input terminals, and the ramp signal may be input to the one of the pair of input terminals. This brings about an effect that a blackening phenomenon is suppressed.

Furthermore, the first aspect may be further provided with: a control section that determines whether or not illuminance is higher than a predetermined value on the basis of the comparison result and outputs a determination result; a correlated double sampling (CDS) processing section that performs correlated double sampling processing on the digital signal; and an output-side selector that outputs either the digital signal subjected to the correlated double sampling processing or a digital signal having a predetermined value on the basis of the determination result. This brings about an effect that a blackening phenomenon is suppressed.

Furthermore, in the first aspect, a vertical scanning circuit that performs control to control a plurality of rows in each of which a predetermined number of pixels are arrayed to simultaneously start exposure may be further provided, and the first and second capacitive elements, the upstream circuit, the selection circuit, the downstream reset transistor, and the downstream circuit may be arranged in each of the pixels. This brings about an effect that miniaturization of a pixel is facilitated.

Furthermore, in the first aspect, the vertical scanning circuit may further perform control to control the plurality of rows to sequentially start the exposure. This brings about an effect that miniaturization of a pixel is facilitated.

Furthermore, in the first aspect, the upstream circuit may be provided on a first chip, and the first and second capacitive elements, the selection circuit, the downstream reset transistor, and the downstream circuit may be provided on a second chip. This brings about an effect that miniaturization of a pixel is facilitated.

Furthermore, in the first aspect, an analog-to-digital converter that sequentially converts the output reset level and the output signal level into digital signals may be further provided, and the analog-to-digital converter may be provided on the second chip. This brings about an effect that miniaturization of a pixel is facilitated.

Furthermore, in the first aspect, an analog-to-digital converter that sequentially converts the output reset level and the output signal level into digital signals may be further provided, and the analog-to-digital converter may be provided on a third chip. This brings about an effect that miniaturization of a pixel is facilitated.

Furthermore, a second aspect of the present technology relates to a solid-state imaging element including: a photoelectric conversion section that converts incident light into a charge; a first amplification transistor that converts the charge into a voltage; a signal line that outputs a pixel signal; a first capacitive element having a first end connected to a first node which is an output destination of the first amplification transistor; a second capacitive element provided in parallel with the first capacitive element between the first amplification transistor and the signal line, the second capacitive element having a first end connected to the first node; a first selection transistor connected to the first capacitive element at a second end of the first capacitive element; a second selection transistor connected to the second capacitive element at a second end of the second capacitive element; a reset transistor of which a source or a drain is connected to a second node to which the first and second selection transistors are connected; and a second amplification transistor that has a gate connected to the second node and outputs the pixel signal. This brings about an effect that image data with reduced kTC noise is generated.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.

<FIG> is a block diagram depicting a configuration example of an imaging device <NUM> in a first embodiment of the present technology. The imaging device <NUM> is a device that images image data, and includes an imaging lens <NUM>, a solid-state imaging element <NUM>, a recording unit <NUM>, and an imaging control section <NUM>. As the imaging device <NUM>, a digital camera or an electronic device (a smartphone, a personal computer, or the like) having an imaging function is assumed.

The solid-state imaging element <NUM> images image data under the control of the imaging control section <NUM>. The solid-state imaging element <NUM> supplies the image data to the recording unit <NUM> via a signal line <NUM>.

The imaging lens <NUM> collects light and guides the light to the solid-state imaging element <NUM>. The imaging control section <NUM> controls the solid-state imaging element <NUM> to image the image data. The imaging control section <NUM> supplies, for example, an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element <NUM> via a signal line <NUM>. The recording unit <NUM> records the image data.

Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and a periodic signal of a constant frequency (such as <NUM> hertz) is used as the vertical synchronization signal VSYNC.

Incidentally, the imaging device <NUM> records the image data, the image data may be transmitted to the outside of the imaging device <NUM>. In this case, an external interface configured to transmit the image data is further provided. Alternatively, the imaging device <NUM> may further display the image data. In this case, a display section is further provided.

<FIG> is a block diagram depicting a configuration example of the solid-state imaging element <NUM> in the first embodiment of the present technology. The solid-state imaging element <NUM> includes a vertical scanning circuit <NUM>, a pixel array section <NUM>, a timing control circuit <NUM>, a digital to analog converter (DAC) <NUM>, a load MOS circuit block <NUM>, and a column signal processing circuit <NUM>. In the pixel array section <NUM>, a plurality of pixels <NUM> is arrayed in a two-dimensional lattice pattern. Furthermore, each of the circuits in the solid-state imaging element <NUM> is provided on, for example, a single semiconductor chip.

Hereinafter, a set of the pixels <NUM> arrayed in the horizontal direction is referred to as a "row", and a set of the pixels <NUM> arrayed in a direction perpendicular to the row is referred to as a "column".

The timing control circuit <NUM> controls an operation timing of each of the vertical scanning circuit <NUM>, the DAC <NUM>, and the column signal processing circuit <NUM> in synchronization with the vertical synchronization signal VSYNC from the imaging control section <NUM>.

The DAC <NUM> generates a ramp signal of a sawtooth wave shape by digital-to-analog (DA) conversion. The DAC <NUM> supplies the generated ramp signal to the column signal processing circuit <NUM>.

The vertical scanning circuit <NUM> sequentially selects and drives rows and outputs analog pixel signals. The pixel <NUM> photoelectrically converts incident light to generate the analog pixel signal. This pixel <NUM> supplies the pixel signal to the column signal processing circuit <NUM> via the load MOS circuit block <NUM>.

In the load MOS circuit block <NUM>, a MOS transistor that supplies a constant current is provided for every column.

The column signal processing circuit <NUM> executes signal processing, such as AD conversion processing and CDS processing, on the pixel signal for each column. The column signal processing circuit <NUM> supplies image data including the processed signal to the recording unit <NUM>. Incidentally, the column signal processing circuit <NUM> is an example of a signal processing circuit described in the claims.

<FIG> is a circuit diagram depicting a configuration example of the pixel <NUM> in the first embodiment of the present technology. The pixel <NUM> includes an upstream circuit <NUM>, capacitive elements <NUM> and <NUM>, a selection circuit <NUM>, a downstream reset transistor <NUM>, and a downstream circuit <NUM>.

The upstream circuit <NUM> includes a photoelectric conversion element <NUM>, a transfer transistor <NUM>, a floating diffusion (FD) reset transistor <NUM>, an FD <NUM>, an upstream amplification transistor <NUM>, and a current source transistor <NUM>.

The photoelectric conversion element <NUM> generates a charge by photoelectric conversion. The transfer transistor <NUM> transfers the charge from the photoelectric conversion element <NUM> to the FD <NUM> in accordance with a transfer signal trg from the vertical scanning circuit <NUM>.

The FD reset transistor <NUM> extracts and initializes the charge from the FD <NUM> in accordance with an FD reset signal rst from the vertical scanning circuit <NUM>. The FD <NUM> accumulates the charge and generates a voltage corresponding to a charge amount. The upstream amplification transistor <NUM> amplifies a level of the voltage of the FD <NUM> and outputs the amplified voltage to an upstream node <NUM>. Incidentally, the FD reset transistor <NUM> is an example of a first reset transistor described in the claims. Furthermore, the upstream amplification transistor <NUM> is an example of a first amplification transistor described in the claims.

Furthermore, sources of the FD reset transistor <NUM> and the upstream amplification transistor <NUM> are connected to a power supply voltage VDD. The current source transistor <NUM> is connected to a drain of the upstream amplification transistor <NUM>. The current source transistor <NUM> supplies a current id1 under the control of the vertical scanning circuit <NUM>.

The capacitive elements <NUM> and <NUM> have one ends connected in common to the upstream node <NUM> and the other ends connected to the selection circuit <NUM>. Incidentally, the capacitive elements <NUM> and <NUM> are examples of first and second capacitive elements described in the claims.

The selection circuit <NUM> includes a selection transistor <NUM> and a selection transistor <NUM>. The selection transistor <NUM> opens and closes a path between the capacitive element <NUM> and a downstream node <NUM> in accordance with a selection signal Φr from the vertical scanning circuit <NUM>. The selection transistor <NUM> opens and closes a path between the capacitive element <NUM> and the downstream node <NUM> in accordance with a selection signal Φs from the vertical scanning circuit <NUM>.

The downstream reset transistor <NUM> initializes a level of the downstream node <NUM> to a predetermined potential Vreg in accordance with a downstream reset signal rstb from the vertical scanning circuit <NUM>. As the potential Vreg, a potential (for example, a potential lower than VDD) different from the power supply potential VDD is set.

The downstream circuit <NUM> includes a downstream amplification transistor <NUM> and a downstream selection transistor <NUM>. The downstream amplification transistor <NUM> amplifies the level of the downstream node <NUM>. The downstream selection transistor <NUM> outputs a signal at the level amplified by the downstream amplification transistor <NUM> to a vertical signal line <NUM> as a pixel signal in accordance with a downstream selection signal selb from the vertical scanning circuit <NUM>. Incidentally, the downstream amplification transistor is an example of a second amplification transistor described in the claims.

Incidentally, for example, n-channel metal oxide semiconductor (nMOS) transistors are used as various transistors (the transfer transistors <NUM> and the like) in the pixel <NUM>.

The vertical scanning circuit <NUM> supplies the high-level FD reset signal rst and the transfer signal trg to all the pixels when exposure starts. Therefore, the photoelectric conversion element <NUM> is initialized. Hereinafter, this control is referred to as "PD reset".

Then, the vertical scanning circuit <NUM> supplies the high-level FD reset signal rst over a pulse period while setting the downstream reset signal rstb and the selection signal Φr to a high level for all the pixels immediately before the exposure ends. Therefore, the FD <NUM> is initialized, and a level corresponding to the level of the FD <NUM> at that time is held in the capacitive element <NUM>. This control is hereinafter referred to as "FD reset".

The level of the FD <NUM> at the time of the FD reset and the level (the level held in the capacitive element <NUM> and the level of the vertical signal line <NUM>) corresponding to the level are hereinafter collectively referred to as a "P phase" or a "reset level".

When the exposure ends, the vertical scanning circuit <NUM> supplies the high-level transfer signal trg over a pulse period while setting the downstream reset signal rstb and the selection signal Φs to the high level for all the pixels. Therefore, a signal charge corresponding to an exposure amount is transferred to the FD <NUM>, and a level corresponding to the level of the FD <NUM> at that time is held in the capacitive element <NUM>.

The level of the FD <NUM> when the signal charge is transferred and the level (the level held in the capacitive element <NUM> and the level of the vertical signal line <NUM>) corresponding to the level are hereinafter collectively referred to as a "D phase" or a "signal level".

Such exposure control in which the exposure is started and ended simultaneously for all the pixels is called a global shutter system. This exposure control causes the upstream circuits <NUM> of all the pixels sequentially generate the reset level and the signal level. The reset level is held in the capacitive element <NUM>, and the signal level is held in the capacitive element <NUM>.

After the exposure ends, the vertical scanning circuit <NUM> sequentially selects a row and sequentially outputs the reset level and the signal level of the row. When the reset level is to be output, the vertical scanning circuit <NUM> supplies the high-level selection signal Φr over a predetermined period while setting the FD reset signal rst and the downstream selection signal selb of the selected row to the high level. Therefore, the capacitive element <NUM> is connected to the downstream node <NUM> so that the reset level is read.

After the reset level is read, the vertical scanning circuit <NUM> supplies the high-level downstream reset signal rstb over a pulse period while keeping the FD reset signal rst and the downstream selection signal selb of the selected row at the high level. Therefore, the level of the downstream node <NUM> is initialized. At this time, both the selection transistor <NUM> and the selection transistor <NUM> are in an open state, and the capacitive elements <NUM> and <NUM> are disconnected from the downstream node <NUM>.

After the downstream node <NUM> is initialized, the vertical scanning circuit <NUM> supplies the high-level selection signal Φs over a predetermined period while keeping the FD reset signal rst and the downstream selection signal selb of the selected row at the high level. Therefore, the capacitive element <NUM> is connected to the downstream node <NUM> so that the signal level is read.

Under the above-described reading control, the selection circuit <NUM> of the selected row sequentially performs control to connect the capacitive element <NUM> to the downstream node <NUM>, control to disconnect the capacitive elements <NUM> and <NUM> from the downstream node <NUM>, and control to connect the capacitive element <NUM> to the downstream node <NUM>. Furthermore, when the capacitive elements <NUM> and <NUM> are disconnected from the downstream node <NUM>, the downstream reset transistor <NUM> of the selected row initializes the level of the downstream node <NUM>. Furthermore, the downstream circuit <NUM> of the selected row sequentially reads the reset level and the signal level from the capacitive elements <NUM> and <NUM> via the downstream node <NUM>, and outputs the reset level and the signal level to the vertical signal line <NUM>.

<FIG> is a block diagram depicting a configuration example of the load MOS circuit block <NUM> and the column signal processing circuit <NUM> in the first embodiment of the present technology.

In the load MOS circuit block <NUM>, the vertical signal line <NUM> is wired for every column. When the number of columns is I (I is an integer), I vertical signal lines <NUM> are wired. Furthermore, a load MOS transistor <NUM> that supplies a constant current id2 is connected to each of the vertical signal lines <NUM>.

In the column signal processing circuit <NUM>, a plurality of ADCs <NUM> and a digital signal processing section <NUM> are arranged. The ADC <NUM> is arranged for every column. When the number of columns is I, I ADCs <NUM> are arranged.

The ADC <NUM> converts an analog pixel signal from a corresponding column into a digital signal using a ramp signal Rmp from the DAC <NUM>. The ADC <NUM> supplies the digital signal to the digital signal processing section <NUM>. For example, a single-slope ADC including a comparator and a counter is arranged as the ADC <NUM>.

The digital signal processing section <NUM> performs predetermined signal processing such as CDS processing on each of the digital signals for every column. The digital signal processing section <NUM> supplies image data including the processed digital signal to the recording unit <NUM>.

<FIG> is a timing chart depicting an example of a global shutter operation in the first embodiment of the present technology. The vertical scanning circuit <NUM> supplies the high-level FD reset signals rst and transfer signal trg to all the rows (in other words, all the pixels) from a timing T0 immediately before the exposure start to a timing T1 after a lapse of a pulse period. Therefore, all the pixels are subjected to the PD reset, and the exposure is simultaneously started in all the rows.

Here, rst_[n] and trg_[n] in the drawing indicate signals with respect to pixels in the n-th row among N rows. N is an integer indicating the total number of rows, and n is an integer from one to N.

Then, the vertical scanning circuit <NUM> supplies the high-level FD reset signal rst over a pulse period while setting the downstream reset signal rstb and the selection signal Φr to the high level in all the pixels at a timing T2 immediately before the end of an exposure period. Therefore, all the pixels are subjected to the FD reset, and the reset level is sampled and held. Here, rstb_[n] and Φr_[n] in the drawing indicate signals with respect to pixels in the n-th row.

At a timing T3 after the timing T2, the vertical scanning circuit <NUM> returns the selection signal Φr to a low level.

At an exposure end timing T4, the vertical scanning circuit <NUM> supplies the high-level transfer signal trg over a pulse period while setting the downstream reset signal rstb and the selection signal Φs to the high level in all the pixels. Therefore, the signal level is sampled and held. Furthermore, a level of the upstream node <NUM> decreases from the reset level (VDD - Vsig) to the signal level (VDD - Vgs - Vsig). Here, VDD represents the power supply voltage, and Vsig represents a net signal level obtained by CDS processing. Vgs represents a gate-source voltage of the upstream amplification transistor <NUM>. Furthermore, Φs_[n] in the drawing indicates a signal with respect to the pixel in the n-th row.

At a timing T5 after the timing T4, the vertical scanning circuit <NUM> returns the selection signal Φs to the low level.

Furthermore, the vertical scanning circuit <NUM> controls the current source transistors <NUM> of all the rows (all the pixels) to supply the current id1. Here, id1_[n] in the drawing indicates the current of the pixel in the n-th row. When a current id is large, IR drop becomes large, and thus, the current id1 needs to be on the order of several nanoamperes (nA) to several tens of nanoamperes (nA). On the other hand, the load MOS transistors <NUM> of all the columns are in the OFF state, and the current id2 is not supplied to the vertical signal line <NUM>.

<FIG> is a timing chart depicting an example of a reading operation in the first embodiment of the present technology. The vertical scanning circuit <NUM> sets the FD reset signal rst and the downstream selection signal selb of the n-th row to the high level in the reading period of the n-th row from a timing T10 to a timing T17. Furthermore, the downstream reset signals rstb of all the rows are controlled to the low level in the reading period. Here, selb_[n] in the drawing indicates a signal with respect to the pixels in the n-th row.

The vertical scanning circuit <NUM> supplies the high-level selection signal Φr to the n-th row over a period from a timing T11 immediately after the timing T10 to a timing T13. The potential of the downstream node <NUM> becomes the reset level Vrst.

The DAC <NUM> gradually increases a ramp signal Rmp over a period from the timing T12 to the timing T13 after the timing T11. The ADC <NUM> compares the ramp signal Rmp with a level Vrst' of the vertical signal line <NUM>, and counts a count value until a comparison result is inverted. Therefore, a P-phase level (reset level) is read.

The vertical scanning circuit <NUM> supplies a high-level downstream reset signal rstb to the n-th row over a pulse period from the timing T14 immediately after the timing T13. Therefore, when a parasitic capacitance exists in the downstream node <NUM>, a history of a previous signal held in the parasitic capacitance can be erased.

The vertical scanning circuit <NUM> supplies the high-level selection signal Φs to the n-th row over a period from a timing T15 immediately after the initialization of the downstream node <NUM> to a timing T17. The potential of the downstream node <NUM> becomes the signal level Vsig. Although the signal level is lower than the reset level at the time of exposure, the signal level is higher than the reset level at the time of reading since the downstream node <NUM> is used as a reference. A difference between the reset level Vrst and the signal level Vsig corresponds to a net signal level from which reset noise and offset noise of the FD have been removed.

The DAC <NUM> gradually increases a ramp signal Rmp over a period from the timing T16 to the timing T17 after the timing T15. The ADC <NUM> compares the ramp signal Rmp with a level Vrst' of the vertical signal line <NUM>, and counts a count value until a comparison result is inverted. Therefore, a D-phase level (signal level) is read.

Furthermore, the vertical scanning circuit <NUM> controls the current source transistor <NUM> of the n-th row to be read over a period from the timing T10 to the timing T17 to supply the current id1. Furthermore, the timing control circuit <NUM> controls the load MOS transistors <NUM> of all columns to supply the current id2 in a reading period of all the rows.

Incidentally, the solid-state imaging element <NUM> reads the signal level after the reset level, but is not limited to this order. As illustrated in <FIG>, the solid-state imaging element <NUM> can also read the reset level after the signal level. In this case, the vertical scanning circuit <NUM> supplies the high-level selection signal Φr after the high-level selection signal Φs as illustrated in the drawing. Furthermore, it is necessary to reverse an inclination of a slope of the ramp signal in this case.

<FIG> is a circuit diagram depicting a configuration example of a pixel in a comparative example. In this comparative example, no selection circuit <NUM> is provided, and a transfer transistor is inserted between an upstream node <NUM> and an upstream circuit. Furthermore, capacitors C1 and C2 are inserted instead of the capacitive elements <NUM> and <NUM>. The capacitor C1 is inserted between the upstream node <NUM> and a ground terminal, and the capacitor C2 is inserted between the upstream node <NUM> and a downstream node <NUM>.

Exposure control and reading control of the pixel in this comparative example are described in Figure <NUM>. <NUM> of Non-Patent Document <NUM>, for example. Assuming that a capacitance value of each of the capacitors C1 and C2 is C in this comparative example, a level Vn of kTC noise at the time of exposure and reading is expressed by the following formula.

In the above formula, k is a Boltzmann constant, and the unit is, for example, Joule per Kelvin (J/K). T is an absolute temperature, and the unit is, for example, Kelvin (K). Furthermore, the unit of Vn is, for example, volt (V), and the unit of C is, for example, farad (F).

<FIG> is a diagram depicting examples of states of the pixel at the time of reading the reset level and at the time of initializing the downstream node in the first embodiment of the present technology. In the drawing, a indicates the state of the pixel <NUM> at the time of reading the reset level, and b in the drawing indicates the state of the pixel <NUM> at the time of initializing the downstream node <NUM>. Furthermore, in the drawing, the selection transistor <NUM>, the selection transistor <NUM>, and the downstream reset transistor <NUM> are represented by graphical symbols of switches for convenience of the description.

As illustrated in a of the drawing, the vertical scanning circuit <NUM> sets the selection transistor <NUM> in a closed state and sets the selection transistor <NUM> and the downstream reset transistor <NUM> in the open state. Therefore, the reset level is read via the downstream circuit <NUM>.

After reading the reset level, the vertical scanning circuit <NUM> sets the selection transistor <NUM> and the selection transistor <NUM> in the open state and sets the downstream reset transistor <NUM> in the closed state as illustrated in b of the drawing. Therefore, the capacitive elements <NUM> and <NUM> are disconnected from the downstream node <NUM>, and the level of the downstream node <NUM> is initialized.

A capacitance value of a parasitic capacitance Cp of the downstream node <NUM> in the state of being disconnected from the capacitive elements <NUM> and <NUM> in this manner is set to be extremely smaller than those of the capacitive elements <NUM> and <NUM>. For example, assuming that the parasitic capacitance Cp is several femtofarads (fF), the capacitive elements <NUM> and <NUM> are on the order of several tens of femtofarads.

<FIG> is a diagram depicting an example of a state of the pixel <NUM> at the time of reading the signal level in the first embodiment of the present technology.

After the initialization of the downstream node <NUM>, the vertical scanning circuit <NUM> sets the selection transistor <NUM> in the closed state and sets the selection transistor <NUM> and the downstream reset transistor <NUM> in the open state. Therefore, the signal level is read via the downstream circuit <NUM>.

Here, kTC noise at the time of exposing the pixel <NUM> is considered. At the time of exposure, the kTC noise occurs in each of sampling of the reset level and sampling of the signal level immediately before the exposure end. Assuming that a capacitance value of each of the capacitive elements <NUM> and <NUM> is C, the level Vn of the kTC noise at the time of exposure is expressed by the following formula.

Furthermore, the downstream reset transistor <NUM> is driven at the time of reading as illustrated in <FIG> and <FIG>, and thus, the kTC noise occurs at that time. However, the capacitive elements <NUM> and <NUM> are disconnected at the time of driving the downstream reset transistor <NUM>, and the parasitic capacitance Cp at that time is small. Therefore, the kTC noise at the time of reading can be ignored as compared with the kTC noise at the time of exposure. Therefore, the kTC noise at the time of exposure and reading is expressed by Formula <NUM>.

From Formulas <NUM> and <NUM>, the kTC noise in the pixel <NUM> in which the capacitor is disconnected at the time of reading is smaller than that in the comparative example in which the capacitor is not disconnectable at the time of reading. Therefore, the image quality of image data can be improved.

<FIG> is a flowchart depicting an example of an operation of the solid-state imaging element <NUM> in the first embodiment of the present technology. This operation is started, for example, when a predetermined application for imaging image data is executed.

The vertical scanning circuit <NUM> exposes all the pixels (step S901). Then, the vertical scanning circuit <NUM> selects a row to be read (step S902). The column signal processing circuit <NUM> reads the reset level of the row (step S903), and then reads the signal level (step S904).

The solid-state imaging element <NUM> determines whether or not reading of all rows has been completed (step S905). In a case where the reading of all the rows has not been completed (Step S905: No), the solid-state imaging element <NUM> repeats Step S902 and the subsequent steps. On the other hand, in a case where the reading of all the rows has been completed (step S905: Yes), the solid-state imaging element <NUM> executes CDS processing or the like, and ends the operation for imaging. In a case where a plurality of pieces of image data is continuously imaged, steps S901 to S905 are repeatedly executed in synchronization with the vertical synchronization signal.

In this manner, the downstream reset transistor <NUM> initializes the downstream node <NUM> when the selection circuit <NUM> disconnects the capacitive elements <NUM> and <NUM> from the downstream node <NUM> in the first embodiment of the present technology. Since the capacitive elements <NUM> and <NUM> are disconnected, a level of reset noise caused by driving thereof becomes a level corresponding to a parasitic capacitance smaller than capacitances thereof. This noise reduction can improve the image quality of image data.

Although the upstream circuit <NUM> reads a signal in the state of being connected to the upstream node <NUM> in the first embodiment described above, it is difficult to block noise from the upstream node <NUM> at the time of reading in this configuration. The pixel <NUM> of a first modification of the first embodiment is different from that of the first embodiment in that a transistor is inserted between the upstream circuit <NUM> and the upstream node <NUM>.

<FIG> is a circuit diagram depicting a configuration example of the pixel <NUM> in the first modification of the first embodiment of the present technology. The pixel <NUM> of the first modification of the first embodiment is different from that of the first embodiment in terms of further including an upstream reset transistor <NUM> and an upstream selection transistor <NUM>. Furthermore, a power supply voltage for the upstream circuit <NUM> and the downstream circuit <NUM> of the first modification of the first embodiment is VDD1.

The upstream reset transistor <NUM> initializes a level of the upstream node <NUM> with a power supply voltage VDD2. The power supply voltage VDD2 is desirably set to a value satisfying the following formula.

In the above formula, Vgs represents a gate-source voltage of the upstream amplification transistor <NUM>.

When the value satisfying Formula <NUM> is set, it is possible to reduce a potential variation between the upstream node <NUM> and the downstream node <NUM> in the dark. Therefore, photo response non-uniformity (PRNU) can be improved.

The upstream selection transistor <NUM> opens and closes a path between the upstream circuit <NUM> and the upstream node <NUM> in accordance with an upstream selection signal sel from the vertical scanning circuit <NUM>.

<FIG> is a timing chart depicting an example of a global shutter operation in the first modification of the first embodiment of the present technology. The timing chart of the first modification of the first embodiment is different from that of the first embodiment in that the vertical scanning circuit <NUM> further supplies an upstream reset signal rsta and an upstream selection signal sel. In the drawing, rsta_[n] and sel_[n] indicate signals with respect to pixels of the n-th row.

The vertical scanning circuit <NUM> supplies the high-level upstream selection signal sel to all the pixels from a timing T2 immediately before the end of exposure to a timing T5. The upstream reset signal rsta is controlled to a low level.

<FIG> is a timing chart depicting an example of a reading operation in the first modification of the first embodiment of the present technology. At the time of reading each row, the upstream selection signal sel is controlled to the low level. This control causes the upstream selection transistor <NUM> to transition to an open state, and the upstream node <NUM> is disconnected from the upstream circuit <NUM>. Therefore, it is possible to block noise from the upstream node <NUM> at the time of reading.

Furthermore, in a reading period of the n-th row from a timing T10 to a timing T17, the vertical scanning circuit <NUM> supplies the high-level upstream reset signal rsta to the n-th row.

Furthermore, the vertical scanning circuit <NUM> controls the current source transistors <NUM> of all the pixels to stop supply of the current id1 at the time of reading. The current id2 is supplied similarly to the first embodiment. In this manner, the control of the current id1 is simplified as compared with the first embodiment.

In this manner, the upstream selection transistor <NUM> transitions to the open state at the time of reading, and the upstream circuit <NUM> is disconnected from the upstream node <NUM>, so that noise from the upstream circuit <NUM> can be blocked according to the first modification of the first embodiment of the present technology.

Although the circuits in the solid-state imaging element <NUM> are provided on the single semiconductor chip in the first embodiment described above, there is a possibility that the elements do not fit in the semiconductor chip when the pixel <NUM> is miniaturized in this configuration. The solid-state imaging element <NUM> of a second modification of the first embodiment is different from that of the first embodiment in that circuits in the solid-state imaging element <NUM> are dispersedly arranged on two semiconductor chips.

<FIG> is a diagram depicting an example of a stacked structure of the solid-state imaging element <NUM> in the second modification of the first embodiment of the present technology. The solid-state imaging element <NUM> in the second modification of the first embodiment includes a lower pixel chip <NUM> and an upper pixel chip <NUM> stacked on the lower pixel chip <NUM>. These chips are electrically connected by, for example, Cu-Cu bonding. Incidentally, the connection can be made by a via or a bump other than the Cu-Cu bonding.

An upper pixel array section <NUM> is arranged on the upper pixel chip <NUM>. A lower pixel array section <NUM> and the column signal processing circuit <NUM> are arranged on the lower pixel chip <NUM>. For each pixel in the pixel array section <NUM>, a part thereof is arranged in the upper pixel array section <NUM>, and the remaining part is arranged in the lower pixel array section <NUM>.

Furthermore, the vertical scanning circuit <NUM>, the timing control circuit <NUM>, the DAC <NUM>, and the load MOS circuit block <NUM> are also arranged on the lower pixel chip <NUM>. These circuits are not illustrated in the drawing.

Furthermore, the upper pixel chip <NUM> is manufactured, for example, by a pixel-dedicated process, and the lower pixel chip <NUM> is manufactured, for example, by a complementary MOS (CMOS) process. Incidentally, the upper pixel chip <NUM> is an example of a first chip described in the claims, and the lower pixel chip <NUM> is an example of a second chip described in the claims.

<FIG> is a circuit diagram depicting a configuration example of the pixel <NUM> in the second modification of the first embodiment of the present technology. In the pixel <NUM>, the upstream circuit <NUM> is arranged on the upper pixel chip <NUM>, and the other circuits and elements (such as the capacitive elements <NUM> and <NUM>) are arranged on the lower pixel chip <NUM>. Incidentally, the current source transistor <NUM> can be further arranged on the lower pixel chip <NUM>. Since the elements in the pixel <NUM> are dispersedly arranged on the stacked upper pixel chip <NUM> and lower pixel chip <NUM> as illustrated in the drawing, the area of a pixel can be reduced, and miniaturization of the pixel is facilitated.

In this manner, since the circuits and elements in the pixel <NUM> are dispersedly arranged on the two semiconductor chips according to the second modification of the first embodiment of the present technology, the miniaturization of the pixel is facilitated.

In the second modification of the first embodiment described above, a part of the pixel <NUM> and a peripheral circuit (such as the column signal processing circuit <NUM>) are provided on the lower pixel chip <NUM> on the lower side. However, in this configuration, the arrangement area of the circuits and elements on the lower pixel chip <NUM> side is larger than that of the upper pixel chip <NUM> by the peripheral circuit, and there is a possibility that an unnecessary space including no circuit and element is generated in the upper pixel chip <NUM>. The solid-state imaging element <NUM> of a third modification of the first embodiment is different from that of the second modification of the first embodiment in that circuits in the solid-state imaging element <NUM> are dispersedly arranged on three semiconductor chips.

<FIG> is a diagram depicting an example of a stacked structure of the solid-state imaging element <NUM> in the third modification of the first embodiment of the present technology. The solid-state imaging element <NUM> of the third modification of the first embodiment includes an upper pixel chip <NUM>, a lower pixel chip <NUM>, and a circuit chip <NUM>. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Incidentally, the connection can be made by a via or a bump other than the Cu-Cu bonding.

An upper pixel array section <NUM> is arranged on the upper pixel chip <NUM>. The lower pixel array section <NUM> is arranged on the lower pixel chip <NUM>. For each pixel in the pixel array section <NUM>, a part thereof is arranged in the upper pixel array section <NUM>, and the remaining part is arranged in the lower pixel array section <NUM>.

Furthermore, the column signal processing circuit <NUM>, the vertical scanning circuit <NUM>, the timing control circuit <NUM>, the DAC <NUM>, and the load MOS circuit block <NUM> are arranged on the circuit chip <NUM>. Circuits other than the column signal processing circuit <NUM> are not illustrated in the drawing.

Incidentally, the upper pixel chip <NUM> is an example of a first chip described in the claims, and the lower pixel chip <NUM> is an example of a second chip described in the claims. The circuit chip <NUM> is an example of a third chip described in the claims.

Since the three-layer configuration as illustrated in the drawing is adopted, it is possible to reduce the unnecessary space and further miniaturize a pixel as compared with the two-layer configuration. Furthermore, the lower pixel chip <NUM> on the second layer can be manufactured by a dedicated process for a capacitor or a switch.

In this manner, since the circuits in the solid-state imaging element <NUM> are dispersedly arranged on the three semiconductor chips in the third modification of the first embodiment of the present technology, the pixel can be further miniaturized as compared with a case where the circuits are dispersedly arranged on two semiconductor chips.

Although the reset level is sampled and held in the exposure period in the first embodiment described above, it is difficult to set the exposure period to be shorter than a sample-and-hold period of the reset level in this configuration. The solid-state imaging element <NUM> of a second embodiment is different from that of the first embodiment in that an exposure period is further shortened by adding a transistor that discharges a charge from a photoelectric conversion element.

<FIG> is a circuit diagram depicting a configuration example of the pixel <NUM> in the second embodiment of the present technology. The pixel <NUM> of the second embodiment is different from that of the first embodiment in that a discharge transistor <NUM> is further provided in the upstream circuit <NUM>.

The discharge transistor <NUM> functions as an overflow drain that discharges a charge from the photoelectric conversion element <NUM> in accordance with a discharge signal ofg from the vertical scanning circuit <NUM>. As the discharge transistor <NUM>, for example, an nMOS transistor is used.

In the configuration in which the discharge transistor <NUM> is not provided as in the first embodiment, blooming may occur when the charge is transferred from the photoelectric conversion element <NUM> to the FD <NUM> for all pixels. Then, potentials of the FD <NUM> and the upstream node <NUM> decrease at the time of FD reset. Following the potential decrease, a current for charging and discharging the capacitive elements <NUM> and <NUM> continues to be generated, and IR drop of the power supply or the ground changes from a steady state where no blooming occurs.

On the other hand, when the signal levels of all the pixels are sampled and held, there is no charge in the photoelectric conversion element <NUM> after the transfer of the signal charge, so that the blooming does not occur, and the IR drop of the power supply or the ground is turned into the steady state where no blooming occurs. Streaking noise is generated due to a difference in the IR drop between the time of sampling and holding the reset level and at the time of sampling and holding the signal level.

On the other hand, the charge of the photoelectric conversion element <NUM> is discharged to the overflow drain side in the second embodiment in which the discharge transistor <NUM> is provided. Therefore, substantially the same IR drop occurs at the time of sampling and holding the reset level and at the time of sampling and holding the signal level, and the streaking noise can be suppressed.

<FIG> is a timing chart depicting an example of a global shutter operation in the second embodiment of the present technology. At a timing T0 before an exposure start timing, the vertical scanning circuit <NUM> supplies high-level FD reset signals rst to all the pixels over a pulse period while setting the discharge signals ofg of all the pixels to a high level. Therefore, PD reset and FD reset are performed on all the pixels. Furthermore, the reset level is sampled and held. Here, ofg_[n] in the drawing indicates a signal with respect to the pixel of the n-th row among the N rows.

Then, the vertical scanning circuit <NUM> returns the discharge signals ofg of all the pixels to a low level at the exposure start timing T1. Then, the vertical scanning circuit <NUM> supplies high-level transfer signals trg to all the pixels over a period from a timing T2 immediately before the exposure end to an exposure end timing T3. Therefore, the signal level is sampled and held.

In the configuration in which the discharge transistor <NUM> is not provided as in the first embodiment, both the transfer transistor <NUM> and the FD reset transistor <NUM> need to be turned on at the start of the exposure (that is, at the time of the PD reset). In this control, it is necessary to reset the FD <NUM> at the same time at the time of the PD reset. Therefore, it is necessary to perform the FD reset again in an exposure period and to sample and hold the reset level, and it is difficult to set the exposure period to be shorter than the sample-and-hold period of the reset level. When the reset levels of all the pixels are sampled and held, a certain waiting time is required until a voltage or a current settles and for example, the sample-and-hold period of several microseconds (µs) to several tens of microseconds (µs) is required.

On the other hand, the PD reset and the FD reset can be individually performed in the second embodiment in which the discharge transistor <NUM> is provided. Therefore, the reset level can be sampled and held by performing the FD reset before cancellation of the PD reset (exposure start) as illustrated in the drawing. Therefore, the exposure period can be set to be shorter than the sample-and-hold period of the reset level.

Incidentally, the first to third modifications of the first embodiment can also be applied to the second embodiment.

In this manner, since the discharge transistor <NUM> that discharges the charge from the photoelectric conversion element <NUM> is provided according to the second embodiment of the present technology, it is possible to sample and hold the reset level by performing the FD reset before the exposure starts. Therefore, the exposure period can be set to be shorter than the sample-and-hold period of the reset level.

Although the FD <NUM> is initialized by the power supply voltage VDD in the first embodiment described above, but there is a possibility that photo response non-uniformity (PRNU) deteriorates due to variations in the capacitive elements <NUM> and <NUM> or parasitic capacitance in this configuration. The solid-state imaging element <NUM> of a third embodiment is different from that of the first embodiment in terms of improving the PRNU by decreasing the power supply of the FD reset transistor <NUM> at the time of reading.

<FIG> is a circuit diagram depicting a configuration example of the pixel <NUM> in the third embodiment of the present technology. The pixel <NUM> of the third embodiment is different from that of the first embodiment in that the power supply of the FD reset transistor <NUM> is disconnected from the power supply voltage VDD of the pixel <NUM>.

A drain of the FD reset transistor <NUM> of the third embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit <NUM>. Incidentally, the timing control circuit <NUM> is an example of a control circuit described in the claims.

Here, the deterioration of the PRNU in the pixel <NUM> of the first embodiment will be considered with reference to <FIG> and <FIG>. In the first embodiment, a potential of the FD <NUM> decreases due to reset feedthrough of the FD reset transistor <NUM> at a timing T0 immediately before exposure starts as illustrated in <FIG>. Such a variation amount is Vft.

Since the power supply voltage of the FD reset transistor <NUM> is VDD in the first embodiment, the potential of the FD <NUM> varies from VDD to VDD - Vft at the timing T0. Furthermore, a potential of the upstream node <NUM> at the time of exposure is VDD - Vft - Vsig.

Furthermore, the FD reset transistor <NUM> transitions to an on state at the time of reading, and the FD <NUM> is fixed to the power supply voltage VDD in the first embodiment as illustrated in <FIG>. The variation amount Vft of the FD <NUM> causes the potentials of the upstream node <NUM> and the downstream node <NUM> at the time of reading to be shifted higher by about Vft. However, an amount of voltage to be shifted varies every pixel due to variations in capacitance values of the capacitive elements <NUM> and <NUM> or the parasitic capacitance, which causes the deterioration of the PRNU.

A shift amount of the upstream node <NUM> in a case where the downstream node <NUM> is shifted by Vft is expressed by, for example, the following formula.

In the above formula, Cs is a capacitance value of the capacitive element <NUM> on the signal level side, and δCs is a variation in Cs. Cp is a capacitance value of the parasitic capacitance of the downstream node <NUM>.

Formula <NUM> can be approximated by the following formula.

From Formula <NUM>, a variation in the downstream node <NUM> can be expressed by the following formula.

Assuming that (δCs/Cs) is <NUM>-<NUM>, (Cp/Cs) is <NUM>-<NUM>, and Vft is <NUM> millivolts (mV), the PRNU is <NUM>µVrms, which is a relatively large value, according to Formula <NUM>.

In particular, it is necessary to increase a charge-to-voltage conversion efficiency of the FD <NUM> when kTC noise at the time of sampling and holding a capacitance converted for input is to be reduced. Although it is necessary to reduce the capacitance of the FD <NUM> in order to increase the charge-to-voltage conversion efficiency, as the capacitance of the FD <NUM> is reduced, the variation amount Vft increases and may become several hundred millivolts (mV). In this case, the influence of the PRNU may be at a non-negligible level according to Formula <NUM>.

<FIG> is a timing chart depicting an example of voltage control in the third embodiment of the present technology.

In a period in which reading is performed row by row after a timing T9, the timing control circuit <NUM> controls the reset power supply voltage VRST to a value different from that in an exposure period.

For example, in the exposure period, the timing control circuit <NUM> sets the reset power supply voltage VRST to the same value as the power supply voltage VDD. On the other hand, in the reading period, the timing control circuit <NUM> decreases the reset power supply voltage VRST to VDD - Vft. That is, in the reading period, the timing control circuit <NUM> decreases the reset power supply voltage VRST by an amount substantially matching the variation amount Vft caused by reset feedthrough. This control enables the reset level of the FD <NUM> to be equalized between the time of exposure and the time of reading.

The control of the reset power supply voltage VRST enables reduction in the voltage variation amount between the FD <NUM> and the upstream node <NUM> as illustrated in the drawing. Therefore, it is possible to suppress the deterioration of the PRNU due to the variations in the capacitive elements <NUM> and <NUM> or the parasitic capacitance.

Incidentally, the first to third modifications of the first embodiment and the second embodiment can also be applied to the third embodiment.

In this manner, since the timing control circuit <NUM> decreases the reset power supply voltage VRST by the variation amount Vft caused by the reset feedthrough at the time of reading according to the third embodiment of the present technology, it is possible to equalize the reset level between the exposure and reading. Therefore, the deterioration of the photo response non-uniformity (PRNU) can be suppressed.

Although the signal level is read subsequently to the reset level for each frame, but in this configuration in the first embodiment described above, there is a possibility that photo response non-uniformity (PRNU) deteriorates due to variations in the capacitive elements <NUM> and <NUM> or parasitic capacitance. The solid-state imaging element <NUM> of a fourth embodiment is different from that of the first embodiment in that the PRNU is improved by switching a level held in the capacitive element <NUM> and a level held in the capacitive element <NUM> for each frame.

The solid-state imaging element <NUM> of the fourth embodiment continuously images a plurality of frames in synchronization with a vertical synchronization signal. An odd-numbered frame is referred to as an "odd frame", and an even-numbered frame is referred to as an "even frame". Incidentally, the odd frame and the even frame are examples of a pair of frames described in the claims.

<FIG> is a timing chart depicting an example of a global shutter operation of the odd frame in the fourth embodiment. The upstream circuit <NUM> in the solid-state imaging element <NUM> sets a selection signal Φs to a high level subsequently to a selection signal Φr in an exposure period of the odd frame, thereby causing the capacitive element <NUM> to hold the reset level, and then causing the capacitive element <NUM> to hold the signal level.

<FIG> is a timing chart depicting an example of a reading operation of the odd frame in the fourth embodiment of the present technology. The downstream circuit <NUM> in the solid-state imaging element <NUM> sets the selection signal Φs to the high level subsequently to the selection signal Φr to read the signal level subsequently to the reset level in the reading period of the odd frame.

<FIG> is a timing chart depicting an example of a global shutter operation of the even frame in the fourth embodiment. The upstream circuit <NUM> in the solid-state imaging element <NUM> sets the selection signal Φr to the high level subsequently to the selection signal Φs in an exposure period of the even frame, thereby causing the capacitive element <NUM> to hold the reset level, and then causing the capacitive element <NUM> to hold the signal level.

<FIG> is a timing chart depicting an example of a reading operation of the even frame in the fourth embodiment of the present technology. The downstream circuit <NUM> in the solid-state imaging element <NUM> sets the selection signal Φr to the high level subsequently to the selection signal Φs to read the signal level subsequently to the reset level in the reading period of the even frame.

As illustrated in <FIG> and <FIG>, the levels to be held in the capacitive elements <NUM> and <NUM> are reversed between the even frame and the odd frame. Therefore, a polarity of the PRNU is also reversed between the even frame and the odd frame. The column signal processing circuit <NUM> in the downstream stage obtains an average by adding the odd frame and the even frame. Therefore, it is possible to cancel out the PRNUs having opposite polarities.

This control is control that is effective in imaging a moving image and adding frames. Furthermore, it is unnecessary to add an element to the pixel <NUM>, and this control can be achieved only by changing a driving system.

Incidentally, the first to third modifications of the first embodiment and the second and third embodiments can also be applied to the fourth embodiment.

In this manner, since the level held in the capacitive element <NUM> and the level held in the capacitive element <NUM> are reversed between the odd frame and the even frame in the fourth embodiment of the present technology, the polarity of the PRNU can be reversed between the odd frame and the even frame. Since the column signal processing circuit <NUM> adds the odd frame and the even frame, deterioration of the PRNU can be suppressed.

In the first embodiment described above, the column signal processing circuit <NUM> obtains the difference between the reset level and the signal level for each column. In this configuration, however, when light with extremely high illuminance is incident on a pixel, there is a possibility that a blackening phenomenon occurs in which brightness decreases to be blackened due to overflowing of the charge from the photoelectric conversion element <NUM>. The solid-state imaging element <NUM> of a fifth embodiment is different from that of the first embodiment in that whether or not the blackening phenomenon has occurred is determined for each pixel.

<FIG> is a circuit diagram depicting a configuration example of the column signal processing circuit <NUM> in the fifth embodiment of the present technology. In the column signal processing circuit <NUM> of the fifth embodiment, a plurality of ADCs <NUM> and a digital signal processing section <NUM> are arranged. Furthermore, a plurality of CDS processing sections <NUM> and a plurality of selectors <NUM> are arranged in the digital signal processing section <NUM>. The ADC <NUM>, the CDS processing section <NUM>, and the selector <NUM> are provided for each column.

Furthermore, the ADC <NUM> includes a comparator <NUM> and a counter <NUM>. The comparator <NUM> compares a level of the vertical signal line <NUM> with a ramp signal Rmp from the DAC <NUM>, and outputs a comparison result VCO. The comparison result VCO is supplied to the counter <NUM> and the timing control circuit <NUM>. The comparator <NUM> includes a selector <NUM>, capacitive elements <NUM> and <NUM>, auto-zero switches <NUM> and <NUM>, and a comparison unit <NUM>.

The selector <NUM> connects any of the vertical signal line <NUM> of a corresponding column and a node with a predetermined reference voltage VREF to a non-inverting input terminal (+) of the comparison unit <NUM> via the capacitive element <NUM> according to an input-side selection signal selin. The input-side selection signal selin is supplied from the timing control circuit <NUM>. Incidentally, the selector <NUM> is an example of an input-side selector described in the claims.

The comparison unit <NUM> compares the respective levels of the non-inverting input terminal (+) and an inverting input terminal (-), and outputs the comparison result VCO to the counter <NUM>. The ramp signal Rmp is input to the inverting input terminal (-) via the capacitive element <NUM>.

The auto-zero switch <NUM> short-circuits the non-inverting input terminal (+) and an output terminal of the comparison result VCO in accordance with an auto-zero signal Az from the timing control circuit <NUM>. The auto-zero switch <NUM> short-circuits the inverting input terminal (-) and the output terminal of the comparison result VCO in accordance with the auto-zero signal Az.

The counter <NUM> counts a count value until the comparison result VCO is inverted, and outputs a digital signal CNT_out indicating the count value to the CDS processing section <NUM>.

The CDS processing section <NUM> performs CDS processing on the digital signal CNT_out. The CDS processing section <NUM> calculates a difference between the digital signal CNT_out corresponding to a reset level and the digital signal CNT_out corresponding to a signal level, and outputs the difference to the selector <NUM> as CDS_out.

The selector <NUM> outputs either the digital signal CDS_out after the CDS processing or a full-code digital signal FULL as pixel data of the corresponding column in accordance with an output-side selection signal selout from the timing control circuit <NUM>. Incidentally, the selector <NUM> is an example of an output-side selector described in the claims.

<FIG> is a timing chart depicting an example of a global shutter operation in the fifth embodiment of the present technology. A method for controlling a transistor at the time of global shutter of the fifth embodiment is similar to that of the first embodiment.

Here, it is assumed that light with extremely high illuminance is incident on the pixel <NUM>. In this case, a charge of the photoelectric conversion element <NUM> becomes full, the charge overflows from the photoelectric conversion element <NUM> to the FD <NUM>, and a potential of the FD <NUM> after FD reset decreases. An alternate long and short dash line in the drawing indicates a potential variation of the FD <NUM> when weak sunlight that causes a relatively small amount of overflowing charge is incident. A dotted line in the drawing indicates a potential variation of the FD <NUM> when strong sunlight that causes a relatively large amount of overflowing charge is incident.

When the weak sunlight is incident, the reset level decreases at a timing T3 when the FD reset is completed, but the level is not completely lowered at this time.

On the other hand, when the strong sunlight is incident, the reset level is completely lowered at a timing T3. In this case, the signal level becomes the same as the reset level, and a potential difference therebetween is "<NUM>", so that the digital signal after the CDS processing becomes the same as that in a dark state to be blackened. In this manner, a phenomenon in which the pixel becomes black even though the light with extremely high illuminance, such as sunlight, is incident is called the blackening phenomenon or blooming.

Furthermore, when a level of the FD <NUM> of a pixel in which the blackening phenomenon has occurred is too low, it is difficult to secure an operating point of the upstream circuit <NUM>, and the current id1 of the current source transistor <NUM> varies. Since the current source transistors <NUM> of the respective pixels are connected to a common power supply or ground, when the current varies in a certain pixel, a variation of IR drop of the pixel affects a sample level of another pixel. A pixel in which the blackening phenomenon occurs becomes an aggressor, and a pixel in which the sample level varies due to the pixel becomes a victim. Therefore, streaking noise is generated.

Incidentally, in a case where the discharge transistor <NUM> is provided as in the second embodiment, the overflowing charge is discarded to the discharge transistor <NUM> side in a pixel with blackening (blooming), so that the blackening phenomenon is less likely to occur. However, even if the discharge transistor <NUM> is provided, a part of the charge is likely to flow to the FD <NUM>, and there is a possibility that the blackening phenomenon is not completely solved. Moreover, there is also a disadvantage that a ratio of an effective area to a charge amount for each pixel decreases due to the addition of the discharge transistor <NUM>. Therefore, it is desirable to suppress the blackening phenomenon without using the discharge transistor <NUM>.

Two methods are conceivable as a method for suppressing the blackening phenomenon without using the discharge transistor <NUM>. A first method is adjustment of a clip level of the FD <NUM>. A second method is a method of determining whether or not the blackening phenomenon occurs at the time of reading and replacing an output with the full code when the blackening phenomenon occurs.

In the first method, a high level of an FD reset signal rst (in other words, a gate of the FD reset transistor <NUM>) in the drawing corresponds to a power supply voltage VDD, and a low level thereof corresponds to the clip level of the FD <NUM>. In the first embodiment, a difference between the high level and the low level (that is, the amplitude) is set to a value corresponding to a dynamic range. On the other hand, the value is adjusted to a value obtained by further adding a margin to the value in the fifth embodiment. Here, the value corresponding to the dynamic range corresponds to a difference between the power supply voltage VDD and the potential of the FD <NUM> when the digital signal becomes the full code.

It is possible to prevent the FD <NUM> from being excessively lowered due to the blooming to damage the operating point of the upstream amplification transistor <NUM> by lowering a gate voltage (the low level of the FD reset signal rst) in an off state of the FD reset transistor <NUM>.

Incidentally, the dynamic range varies depending on an analog gain of the ADC. A large dynamic range is required when the analog gain is low, and conversely, a small dynamic range is sufficient when the analog gain is high. Therefore, the gate voltage in the off state of the FD reset transistor <NUM> can also be changed in accordance with the analog gain.

<FIG> is a timing chart depicting an example of a reading operation in the fifth embodiment of the present technology. When a selection signal Φr becomes the high level at a timing T11 immediately after a reading start timing T10, a potential of the vertical signal line <NUM> varies in a pixel on which sunlight is incident. An alternate long and short dash line in the drawing indicates a potential variation of the vertical signal line <NUM> when weak sunlight is incident. A dotted line in the drawing indicates a potential variation of the vertical signal line <NUM> when strong sunlight is incident.

In an auto-zero period from the timing T10 to a timing T12, the timing control circuit <NUM> supplies, for example, the input-side selection signal selin of "<NUM>", and connects the comparison unit <NUM> to the vertical signal line <NUM>. In this auto-zero period, the timing control circuit <NUM> performs auto-zeroing by an auto-zero signal Az.

Regarding the second method, the timing control circuit <NUM> supplies, for example, the input-side selection signal selin of "<NUM>" in a determination period from the timing T12 to a timing T13. In accordance with the input-side selection signal selin, the comparison unit <NUM> is disconnected from the vertical signal line <NUM> and connected to the node with the reference voltage VREF. The reference voltage VREF is set to an expected value of a level of the vertical signal line <NUM> when no blooming has occurred. For example, when a gate-source voltage of the downstream amplification transistor <NUM> is Vgs2, Vrst corresponds to Vreg - Vgs2. Furthermore, the DAC <NUM> decreases a level of the ramp signal Rmp from Vrmp_az to Vrmp_sun in the determination period.

Furthermore, in a case where no blooming has occurred in the determination period, the reset level Vrst of the vertical signal line <NUM> is substantially the same as the reference voltage VREF, and a potential of the inverting input terminal (+) of the comparison unit <NUM> does not change much from that at the time of auto-zero. On the other hand, the non-inverting input terminal (-) has been lowered from Vrmp_az to Vrmp_sun, and thus, the comparison result VCO becomes the high level.

Conversely, in a case where the blooming has occurred, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and the comparison result VCO becomes the low level when the following formula is satisfied.

That is, the timing control circuit <NUM> can determine whether or not the blooming has occurred based on whether or not the comparison result VCO becomes the low level in the determination period.

Incidentally, it is necessary to secure a large margin for sun determination (the right side of Formula <NUM>) to some extent not to cause erroneous determination due to variations in threshold voltage of the downstream amplification transistor <NUM>, an IR drop difference of Vregs in a plane, and the like.

After a timing T13 after the lapse of the determination period, the timing control circuit <NUM> connects the comparison unit <NUM> to the vertical signal line <NUM>. Furthermore, when a P-phase settling period from the timing T13 to a timing T14 elapses, the P phase is read in a period from the timing T14 to a timing T15. When a D phase settling period from the timing T15 to a timing T19 elapses, the D phase is read in a period from the timing T19 to a timing T20.

In a case where it is determined that no blooming has not occurred in the determination period, the timing control circuit <NUM> controls the selector <NUM> by the output-side selection signal selout to output the digital signal CDS_out after the CDS processing without any change.

On the other hand, in a case where it is determined that the blooming has occurred in the determination period, the timing control circuit <NUM> controls the selector <NUM> by the output-side selection signal selout to output the full code FULL instead of the digital signal CDS_out after the CDS processing. Therefore, the blackening phenomenon can be suppressed.

Incidentally, the first to third modifications of the first embodiment and the second to fourth embodiments can also be applied to the fifth embodiment.

In this manner, since the timing control circuit <NUM> determines whether or not the blackening phenomenon has occurred on the basis of the comparison result VCO and outputs the full code when the blackening phenomenon has occurred according to the fifth embodiment of the present technology, the blackening phenomenon can be suppressed.

In the above-described first embodiment, the vertical scanning circuit <NUM> performs the control (that is, global shutter operation) to simultaneously expose all rows (all pixels). However, in a case where the simultaneity of exposure is unnecessary and low noise is required at the time of conducting a test, at the time of performing analysis, or the like, it is desirable to perform a rolling shutter operation. The solid-state imaging element <NUM> of a sixth embodiment is different from that of the first embodiment in that the rolling shutter operation is performed at the time of conducting a test or the like.

<FIG> is a timing chart depicting an example of the rolling shutter operation in the sixth embodiment of the present technology. The vertical scanning circuit <NUM> performs control to sequentially select a plurality of rows and start exposure. This drawing illustrates exposure control of the n-th row.

During a period from a timing T0 to a timing T2, the vertical scanning circuit <NUM> supplies a high-level downstream selection signal selb, selection signal Φr, and selection signal Φs to the n-th row. Furthermore, at the exposure start timing T0, the vertical scanning circuit <NUM> supplies high-level FD reset signal rst and downstream reset signal rstb to the n-th row over a pulse period. At the exposure end timing T1, the vertical scanning circuit <NUM> supplies a transfer signal trg to the n-th row. The rolling shutter operation in the drawing enables the solid-state imaging element <NUM> to generate image data with low noise.

Incidentally, during normal imaging, the solid-state imaging element <NUM> of the sixth embodiment performs a global shutter operation similarly to the first embodiment.

Furthermore, the first to third modifications of the first embodiment and the second to fifth embodiments can also be applied to the sixth embodiment.

In this manner, since the vertical scanning circuit <NUM> performs the control (that is, rolling shutter operation) to sequentially select the plurality of rows and start exposure according to the sixth embodiment of the present technology, it is possible to generate the image data with low noise.

In the first embodiment described above, a source of a source follower (the upstream amplification transistor <NUM> and the current source transistor <NUM>) in the upstream stage is connected to the power supply voltage VDD, and reading is performed row by row in a state where the source follower is turned on. In such a driving method, however, there is a possibility that circuit noise of the source follower in the upstream stage at the time of performing the reading row by row propagates to the downstream stage so that random noise increases. The solid-state imaging element <NUM> of a seventh embodiment is different from that of the first embodiment in that noise is reduced by turning off a source follower in the upstream stage at the time of reading.

<FIG> is a block diagram depicting a configuration example of the solid-state imaging element <NUM> in the seventh embodiment of the present technology. The solid-state imaging element <NUM> of the seventh embodiment is different from that of the first embodiment in terms of further including a regulator <NUM> and a switching section <NUM>. Furthermore, a plurality of effective pixels <NUM> and a predetermined number of dummy pixels <NUM> are arrayed in the pixel array section <NUM> of the seventh embodiment. The dummy pixels <NUM> are arrayed around a region where the effective pixels <NUM> are arrayed.

Furthermore, a power supply voltage VDD is supplied to each of the dummy pixels <NUM>, and the power supply voltage VDD and a source voltage Vs are supplied to each of effective pixels <NUM>. A signal line for supplying the power supply voltage VDD to the effective pixel <NUM> is omitted in the drawing. Furthermore, the power supply voltage VDD is supplied from a pad <NUM> outside the solid-state imaging element <NUM>.

The regulator <NUM> generates a constant generation voltage Vgen on the basis of an input potential Vi from the dummy pixel <NUM> and supplies the generation voltage to the switching section <NUM>. The switching section <NUM> selects either the power supply voltage VDD from the pad <NUM> or the generation voltage Vgen from the regulator <NUM>, and supplies the selected voltage to each of columns of the effective pixels <NUM> as a source voltage Vs.

<FIG> is a circuit diagram depicting a configuration example of the dummy pixel <NUM>, the regulator <NUM>, and the switching section <NUM> in the seventh embodiment of the present technology. In the drawing, a is a circuit diagram of the dummy pixel <NUM> and the regulator <NUM>, and b in the drawing is a circuit diagram of the switching section <NUM>.

As illustrated in a of the drawing, the dummy pixel <NUM> includes a reset transistor <NUM>, an FD <NUM>, an amplification transistor <NUM>, and a current source transistor <NUM>. The reset transistor <NUM> initializes the FD <NUM> in accordance with a reset signal RST from the vertical scanning circuit <NUM>. The FD <NUM> accumulates a charge and generates a voltage corresponding to a charge amount. The amplification transistor <NUM> amplifies a level of the voltage of the FD <NUM> and supplies the amplified voltage to the regulator <NUM> as the input voltage Vi.

Furthermore, sources of the reset transistor <NUM> and the amplification transistor <NUM> are connected to the power supply voltage VDD. The current source transistor <NUM> is connected to a drain of the amplification transistor <NUM>. The current source transistor <NUM> supplies a current id1 under the control of the vertical scanning circuit <NUM>.

The regulator <NUM> includes a low-pass filter <NUM>, a buffer amplifier <NUM>, and a capacitive element <NUM>. The low-pass filter <NUM> allows passage, as an output voltage Vj, of a component in a low-frequency band lower than a predetermined frequency out of a signal of the input voltage Vi.

The output voltage Vj is input to a non-inverting input terminal (+) of the buffer amplifier <NUM>. An inverting input terminal (-) of the buffer amplifier <NUM> is connected to the output terminal thereof. The capacitive element <NUM> holds a voltage of the output terminal of the buffer amplifier <NUM> as Vgen. This Vgen is supplied to the switching section <NUM>.

As illustrated in a of the drawing, the switching section <NUM> includes an inverter <NUM> and a plurality of switching circuits <NUM>. The switching circuit <NUM> is arranged for each column of the effective pixels <NUM>.

The inverter <NUM> inverts a switching signal SW from the timing control circuit <NUM>. The inverter <NUM> supplies the inverted signal to each of the switching circuits <NUM>.

The switching circuit <NUM> selects one of the power supply voltage VDD and the generation voltage Vgen and supplies the selected voltage to the corresponding column in the pixel array section <NUM> as the source voltage Vs. The switching circuit <NUM> includes switches <NUM> and <NUM>. The switch <NUM> opens and closes a path between a node with the power supply voltage VDD and the corresponding column in accordance with the switching signal SW. The switch <NUM> opens and closes a path between a node with the generation voltage Vgen and the corresponding column in accordance with the inverted signal of the switching signal SW.

<FIG> is a timing chart depicting an example of the operation of the dummy pixel <NUM> and the regulator <NUM> in the seventh embodiment of the present technology. At a timing T10 immediately before reading of a certain row, the vertical scanning circuit <NUM> supplies the reset signal RST at a high level (here, the power supply voltage VDD) to each of the dummy pixels <NUM>. A potential Vfd of the FD <NUM> in the dummy pixel <NUM> is initialized to the power supply voltage VDD. Then, when the reset signal RST becomes a low level, reset feedthrough causes a variation as VDD - Vft.

Furthermore, the input voltage Vi decreases to VDD - Vgs - Vsig after reset. After passing through the low-pass filter <NUM>, Vj and Vgen become substantially constant voltages.

After a timing T20 immediately before reading of the next row, similar control is performed for each row, and the constant generation voltage Vgen is supplied.

<FIG> is a circuit diagram depicting a configuration example of the effective pixel <NUM> in the seventh embodiment of the present technology. A circuit configuration of the effective pixel <NUM> is similar to that of the pixel <NUM> of the first embodiment except that the source voltage Vs from the switching section <NUM> is supplied to a source of the upstream amplification transistor <NUM>.

<FIG> is a timing chart depicting an example of a global shutter operation in the seventh embodiment of the present technology. In the seventh embodiment, when exposure is performed simultaneously in all pixels, the switching section <NUM> selects the power supply voltage VDD and supplies the power supply voltage as the source voltage Vs. Furthermore, a voltage of an upstream node decreases from VDD - Vgs - Vth to VDD - Vgs - Vsig at a timing T4. Here, Vth is a threshold voltage of the transfer transistor <NUM>.

<FIG> is a timing chart depicting an example of a reading operation in the seventh embodiment of the present technology. In the seventh embodiment, the switching section <NUM> selects the generation voltage Vgen and supplies the generation voltage as the source voltage Vs at the time of reading. The generation voltage Vgen is adjusted to VDD - Vgs - Vft. Furthermore, the vertical scanning circuit <NUM> controls the current source transistors <NUM> of all the rows (all the pixels) to stop the supply of the current id1 in the seventh embodiment.

<FIG> is a diagram for describing an effect in the seventh embodiment of the present technology. In the first embodiment, a source follower (the upstream amplification transistor <NUM> and the current source transistor <NUM>) of the pixel <NUM> to be read is turned on when reading is performed row by row. In such a driving method, however, there is a possibility that circuit noise of the source follower in the upstream stage propagates to the downstream stage (the capacitive element, the downstream source follower, or the ADC) so that reading noise increases.

For example, in the first embodiment, kTC noise generated in the pixel during the global shutter operation is <NUM> (µVrms) as illustrated in the drawing. Furthermore, noise generated in the source follower (the upstream amplification transistor <NUM> and the current source transistor <NUM>) in the upstream stage at the time of reading for every row is <NUM> (µVrms). Noise generated after the source follower in the downstream stage is <NUM> (µVrms). Therefore, the total noise is <NUM> (µVrms). In this manner, the contribution of the noise of the source follower in the upstream stage in the total value of the noise becomes relatively large in the first embodiment.

In order to reduce the noise of the source follower in the upstream stage, the voltage (Vs) that can be adjusted is supplied to the source of the source follower in the upstream stage in the seventh embodiment as described above. The switching section <NUM> selects the power supply voltage VDD and supplies the power supply voltage as the source voltage Vs during the global shutter (exposure) operation. Then, the switching section <NUM> switches the source voltage Vs to VDD - Vgs - Vft after the exposure ends. Furthermore, the timing control circuit <NUM> turns on the current source transistor <NUM> in the upstream stage during the global shutter (exposure) operation, and turns off the current source transistor <NUM> after the exposure ends.

The above-described control enables the potential of the upstream node to be equalized between the time of performing the global shutter operation and the time of reading for every row, and the PRNU can be improved as illustrated in <FIG> and <FIG>. Furthermore, since the source follower in the upstream stage is in the off state at the time of reading for every row, the circuit noise of the source follower is not generated and becomes zero (µVrms) as illustrated in <FIG>. Incidentally, the upstream amplification transistor <NUM> in the source follower in the upstream stage is in an on state.

In this manner, since the source follower in the upstream stage is in the off state at the time of reading according to the seventh embodiment of the present technology, the noise generated in the source follower can be reduced.

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

<FIG> is a block diagram depicting a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. Furthermore, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section <NUM> can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

In addition, the microcomputer <NUM> can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM> or the in-vehicle information detecting unit <NUM>.

Furthermore, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information regarding the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display and a head-up display.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of imaging ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

Claim 1:
A solid-state imaging element comprising:
first and second capacitive elements (<NUM>, <NUM>);
an upstream circuit (<NUM>) configured to sequentially generate a reset level and a signal level corresponding to an exposure amount and cause each of the first and second capacitive elements (<NUM>, <NUM>) to hold the reset level and the signal level;
an upstream selection transistor (<NUM>) configured to open and close a path between the upstream circuit (<NUM>) and a predetermined upstream node (<NUM>);
an upstream reset transistor (<NUM>) configured to initialize a level of the upstream node (<NUM>);
a selection circuit (<NUM>) configured to sequentially perform control to connect one of the first and second capacitive elements (<NUM>, <NUM>) to a predetermined downstream node (<NUM>), control to disconnect both the first and second capacitive elements (<NUM>, <NUM>) from the downstream node (<NUM>), and control to connect another of the first and second capacitive elements (<NUM>, <NUM>) to the downstream node (<NUM>);
a downstream reset transistor (<NUM>) configured to initialize a level of the downstream node (<NUM>) when both the first and second capacitive elements (<NUM>, <NUM>) are disconnected from the downstream node (<NUM>); and
a downstream circuit (<NUM>) configured to sequentially read the reset level and the signal level from the first and second capacitive elements (<NUM>, <NUM>) via the downstream node (<NUM>) and output the reset level and the signal level;
wherein the first and second capacitive elements (<NUM>, <NUM>) respectively have first ends connected in common to the upstream node (<NUM>) and second ends connected to the selection circuit (<NUM>); and
wherein the upstream circuit (<NUM>) includes:
a photoelectric conversion element (<NUM>);
an upstream transfer transistor (<NUM>) configured to transfer a charge from the photoelectric conversion element (<NUM>) to a floating diffusion (<NUM>);
a first reset transistor (<NUM>) configured to initialize the floating diffusion (<NUM>); and
an upstream amplification transistor (<NUM>) configured to amplify a voltage of the floating diffusion (<NUM>) and output the amplified voltage to the upstream node (<NUM>).