Patent Description:
Memory devices are used to store data and are categorized into volatile memory devices and non-volatile memory devices. In response to the demand for increased capacity and miniaturization of non-volatile memory devices, a 3D memory device including a plurality of vertical channel structures extending in a vertical direction on a substrate has been developed. In order to further improve the degree of integration of a 3D memory device, as the number of a plurality of word lines vertically stacked on a substrate increases, the length of each vertical channel structure may increase. As the length of the vertical channel structure increases, a channel recovery degradation phenomenon in which a bit line voltage is not properly transmitted throughout a channel region may occur.

<CIT> discloses: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.

The invention is defined in the independent claim. Specific embodiments are defined in the dependent claims. The inventive concepts provide non-volatile memory devices capable of improving performance by smoothly performing channel recovery throughout a channel region despite an increase in the length or the resistance of the channel region of the non-volatile memory device.

According to an aspect of the inventive concepts, there is provided non-volatile memory devices including a memory cell array including a plurality of cell strings, each cell string extending in a vertical direction above a substrate and each cell string including a plurality of memory cells respectively connected to a plurality of word lines and a string select transistor connected to a string select line; a page buffer circuit including a plurality of page buffers connected to the memory cell array, each page buffer including a forcing latch configured to store forcing information and each page buffer is connected to a selected cell string through a bit line; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string through the bit line, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

<FIG> is a block diagram showing a memory system <NUM> according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory system <NUM> may include a memory device <NUM> and a memory controller <NUM>, and the memory device <NUM> may include a memory cell array <NUM>, a control logic circuit <NUM>, and a page buffer circuit <NUM>. The memory device <NUM> may be a nonvolatile memory device, and, in this specification, the term "memory device" will refer to a "nonvolatile memory device".

The memory controller <NUM> may control the memory device <NUM> to read data stored in the memory device <NUM> or program data to the memory device <NUM> in response to a read/write request from a host HOST. In detail, the memory controller <NUM> may provide an address ADDR, a command CMD, and a control signal CTRL to the memory device <NUM>, thereby controlling a program operation, a read operation, and an erase operation for the memory device <NUM>. Also, data DATA to be programmed and read data DATA may be transmitted and received between the memory controller <NUM> and the memory device <NUM>.

The memory cell array <NUM> may include a plurality of memory cells. For example, the memory cells may be flash memory cells. Hereinafter, example embodiments of the inventive concepts will be described in detail based on an example case where the memory cells are NAND flash memory cells. However, the inventive concepts are not limited thereto, and, in some example embodiments, the memory cells may be resistive memory cells like resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, and magnetic RAM (MRAM) cells.

The control logic circuit <NUM> may receive a command CMD, an address ADDR, and a control signal CTRL from the memory controller <NUM> and control the overall operation of the memory device <NUM> based on the command CMD, the address ADDR, and the control signal CTRL. The page buffer circuit <NUM> may include a plurality of page buffers (e.g., PB <NUM> to PBm of <FIG>). In some example embodiments, each page buffer may include a forcing latch (e.g., <NUM> of <FIG>) that stores bit line forcing information (hereinafter referred to as "forcing information"). In some example embodiments, each page buffer may further include a bit line shut-off transistor (e.g., NM1 of <FIG>).

In some example embodiments, when the command CMD is a program command, the control logic circuit <NUM> may control a string select line voltage applied to a string select line corresponding to the address ADDR from among string select lines (e.g., SSL1 to SSL3 of <FIG>) connected to the memory cell array <NUM>, in response to the program command. In detail, during a program operation on a selected word line corresponding to the address ADDR, a program execution interval may be divided into a first interval (e.g., INT1 of <FIG>) before a bit line forcing operation is performed, a second interval (e.g., INT2 of <FIG>) in which a bit line forcing operation is performed, and a third interval (e.g., INT3 of <FIG>) after a bit line forcing operation is performed. In this case, the control logic circuit <NUM> may individually control a string select line voltage for each of first to third intervals. Therefore, initial channel recovery for a bit line forcing operation may be smoothly performed in the first interval.

In some example embodiments, the control logic circuit <NUM> may differently control a string select line voltage for at least one of the first to third intervals according to the position of a selected word line. For example, a plurality of word lines may include a first word line relatively close to a substrate (that is, a bottom word line) and a second word line relatively far from the substrate (that is, a top word line). In this case, a string select line voltage in a first interval of a program execution period for the top word line and a string select line voltage in a first period of a program execution period for the bottom word line may have different voltage levels. Therefore, it is possible to smoothly perform channel recovery for a bit line forcing operation even during a program operation on the bottom word line relatively far from a bit line.

In some example embodiments, when the command CMD is a program command, the control logic circuit <NUM> may control the waveform of a bit line shut-off signal for driving a bit line shut-off transistor included in each page buffer of the page buffer circuit <NUM>, in response to the program command. In detail, during a program operation on a selected word line corresponding to the address ADDR, the control logic circuit <NUM> may control the waveform of a bit line shut-off signal for performing a bit line forcing operation according to the position of the selected word line. Therefore, channel recovery for a bit line forcing operation may be smoothly performed, thereby improving the performance of a memory device.

<FIG> is a block diagram showing the memory device <NUM> according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory device <NUM> may include a memory cell array <NUM>, a control logic circuit <NUM>, a page buffer circuit <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. Although not shown, the memory device <NUM> may further include an interface circuit, and the interface circuit may include a data input/output circuit, a command/address input/output circuit, etc. Also, the memory device <NUM> may further include a temperature sensor.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz, where z is a positive integer. The memory blocks BLK1 to BLKz may each include a plurality of pages, and the pages may each include a plurality of memory cells. For example, a memory block may be an erase unit, and a page may be a write/read unit. Each memory cell may store one or more bits, and more particularly, each memory cell may be used as a single level cell (SLC), a multi level cell (MLC), a triple level cell (TLC), or a quadruple level cell (QLC).

The memory cell array <NUM> may be connected to a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, and a plurality of bit lines BL. The memory cell array <NUM> may be connected to the row decoder <NUM> through the word lines WL, the string select lines SSL, and the ground select lines GSL and may be connected to the page buffer circuit <NUM> through the bit lines BL. In some example embodiments, the memory cell array <NUM> may be further connected to erase control lines (e.g., GIDL_SS1 to GIDL_SS3a and/or GIDL_GS1 to GIDL_GS3 of <FIG>).

In some example embodiments, the memory cell array <NUM> may include a <NUM>-dimensional memory cell array, and the <NUM>-dimensional memory cell array may include a plurality of cell strings or a plurality of NAND strings. Each cell string may include memory cells connected to word lines vertically stacked on a substrate, respectively. In this respect it is referred to <CIT>, <CIT>, <CIT>, <CIT>, and <CIT> for further details.

The control logic circuit <NUM> may output various control signals for writing data to the memory cell array <NUM> or reading data from the memory cell array <NUM> based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller <NUM>. Therefore, the control logic circuit <NUM> may overall control various operations within the memory device <NUM>. In detail, the control logic circuit <NUM> may provide a voltage control signal CTRL_vol to the voltage generator <NUM>, provide a row address X ADDR to the row decoder <NUM>, and provide a column address Y_ ADDR to the page buffer circuit <NUM>. However, the inventive concepts are not limited thereto, and the control logic circuit <NUM> may further provide other control signals to the voltage generator <NUM>, the row decoder <NUM>, and the page buffer circuit <NUM>.

In some example embodiments, the control logic circuit <NUM> may control a string select line voltage to be relatively high in a first period before a bit line forcing operation is performed during a program execution interval, thereby facilitating initial channel recovery. In some example embodiments, during a program operation on the bottom word line, the control logic circuit <NUM> may controls the string select line voltage in the first interval to be higher than the string select line voltage in the first interval during a program operation on the top word line, and thus a bit line voltage may be smoothly transferred to a channel region relatively far from a bit line.

For example, the control logic circuit <NUM> may control a string select line voltage before a bit line forcing operation to be higher than a string select line voltage during a bit line setup operation. For example, the control logic circuit <NUM> may control a string select line voltage before a bit line forcing operation to be higher than a string select line voltage during the bit line forcing operation. For example, the control logic circuit <NUM> may control a string select line voltage during a bit line forcing operation to be higher than a string select line voltage after the bit line forcing operation.

In some example embodiments, in a program execution interval, the control logic circuit <NUM> may control the waveform of a bit line shut-off signal for driving a bit line shut-off transistor included in each page buffer of the page buffer circuit <NUM>. In detail, the control logic circuit <NUM> may control a bit line shut-off voltage corresponding to a bit line shut-off signal for performing a bit line forcing operation according to the position of a selected word line. For example, the control logic circuit <NUM> may control a delay interval in which a bit line shut-off voltage maintains the ground voltage during a program operation on the bottom word line to be longer than a delay interval of a bit line shut-off voltage during a program operation on the top word line.

In some example embodiments, the control logic circuit <NUM> may control a step waveform in which the bit line shut-off voltage rises from the ground voltage to a bit line forcing voltage during a program operation. For example, the step waveform may include a plurality of steps, and the control logic circuit <NUM> may control cycle respectively corresponding to maintenance intervals of the respective steps. For example, the step waveform may include a plurality of steps, and the control logic circuit <NUM> may control at least one of steps corresponding to voltage differences between the steps.

The voltage generator <NUM> may generate various types of voltages for performing a program operation, a read operation, and an erase operation based on a voltage control signal CTRL_vol. In detail, the voltage generator <NUM> may generate a word line voltage V_WL, a string select line voltage V_SSL, and a ground select line voltage V_GSL and provide the word line voltage V_WL, the string select line voltage V_SSL, and the ground select line voltage V_GSL to the row decoder <NUM>. Also, the voltage generator <NUM> may further generate a bit line shut-off voltage V_BLSHF applied to a bit line shut-off transistor and provide the bit line shut-off voltage V_BLSHF to the page buffer circuit <NUM>.

For example, the voltage generator <NUM> may generate a program voltage, a pass voltage, a read voltage, a program verify voltage, or an erase voltage as the word line voltage V_WL. For example, the voltage generator <NUM> may generate a selection voltage or a non-selection voltage as the string select line voltage V_SSL. For example, the voltage generator <NUM> may generate a selection voltage or a non-selection voltage as the ground select line voltage V_GSL. Also, the voltage generator <NUM> may further generate a bit line voltage, a common source line voltage, etc..

In some example embodiments, based on a voltage control signal CTRL_vol, the voltage generator <NUM> may generate a selection voltage corresponding to the string select line voltage V_SSL as one of first to fourth voltages (V1 to V4 of <FIG>). In some example embodiments, the voltage generator <NUM> may generate the bit line shut-off voltage V_BLSHF to have a step waveform that increases step-by-step based on the voltage control signal CTRL_vol. In this case, the bit line shut-off voltage V_BLSHF may include a plurality of steps, and the voltage generator <NUM> may generate the bit line shut-off voltage V_BLSHF, such that cycles of the respective steps and/or voltage differences between the steps are different from one another, according to the voltage control signal CTRL_vol.

The row decoder <NUM> may select one from among the word lines WL in response to a row address X_ADDR and may select one from among the string select lines SSL. For example, during a program operation, the row decoder <NUM> may apply a program voltage (e.g., VPGM of <FIG>) to a selected word line in a program execution interval and apply a program verify voltage to the selected word line in a program verify interval. Also, in a program execution interval, the row decoder <NUM> may apply a first voltage V1 to a selected string select line in a first interval (e.g., INT1 of <FIG>) before a bit line forcing operation, apply a second voltage V2 to the selected string select line in a second interval (e.g., INT2 of <FIG>) during the bit line forcing operation, and apply a third voltage V3 to the selected string select line in a third interval (e.g., INT3 of <FIG>) after the bit line forcing operation. For example, during a read operation, the row decoder <NUM> may apply a read voltage to a selected word line.

The page buffer circuit <NUM> may select at least one bit line BL from among the bit lines BL in response to a column address Y_ADDR. The page buffer circuit <NUM> may operate as a write driver or a sense amplifier depending on an operation mode. The page buffer circuit <NUM> may include a plurality of page buffers PB1 to PBm, where m is a positive integer. For example, m may correspond to the number of the bit lines BL, and the page buffers PB1 to PBm may be respectively connected to the bit lines BL. For example, the bit lines BL may be grouped into a plurality of bit line groups, and bit lines included in each of the bit line groups may share a page buffer.

<FIG> is a circuit diagram showing a memory block BLK according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory block BLK may correspond to one of the memory blocks BLK1 to BLKz of <FIG>. The memory block BLK may be connected to bit lines BL1 to BL3, erase control lines GIDL_SS1 to GIDL_SS3, string select lines SSL1 to SSL3, word lines WL, ground select lines GSL1 to GSL3, and erase control lines GIDL_GS1 to GIDL_GS3 and may include NAND strings (or cell strings) NS11 to NS33 extending in a vertical direction VD. Here, the number of cell strings, the number of word lines, the number of bit lines, the number of ground select lines, the number of string select lines, and the number of erase control lines may vary according to some example embodiments.

The bit lines BL1 to BL3 may extend in a first direction or a first horizontal direction HD1, and word lines WL1 to WLn may extend in a second direction or a second horizontal direction HD2, where n is a positive integer. cell strings NS11, NS21, and NS31 may be provided between a first bit line BL1 and a common source line CSL, cell strings NS12, NS22, and NS32 may be provided between a second bit line BL2 and the common source line CSL, and cell strings NS13, NS23, and NS33 may be provided between a third bit line BL3 and the common source line CSL.

For example, a cell string NS11 may include an erase control transistor GDT, a string select transistor SST, a plurality of memory cells MCs, a ground select transistor GST, and an erase control transistor GDT_GS connected in series. The erase control transistor GDT may be connected to a corresponding first bit line BL1 and a corresponding first erase control line GIDL_SS1. The string select transistor SST may be connected to a corresponding string select line SSL1, and the memory cells MCs may be respectively connected to corresponding word lines WL1 to WLn.

The ground select transistor GST may be connected to a corresponding ground select line GSL1. The erase control transistor GDT_GS may be connected to a corresponding erase control line GIDL_GS1 and the common source line CSL. Hereinafter, the erase control lines GIDL_GS1 to GIDL_GS3 arranged below the ground select lines GSL1 to GSL3 will be referred to as "ground erase control lines", and the erase control transistor GDT_GS will be referred to as a "ground erase control transistor".

As the number of word lines WL1 to WLn increases, the length of each cell string may increase. Therefore, during a program operation on the bottom word line relatively far from the bit lines BL1 to BL3, a channel recovery degradation phenomenon in which a bit line voltage is not smoothly transferred to a channel region may occur. Also, as the erase control lines GIDL_SS1 to GIDL_SS3 are added, the erase control lines GIDL_SS1 to GIDL_SS3 may serve as resistance components, and thus channel recovery degradation may become more significant.

<FIG> is a circuit diagram showing a memory block BLK' according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory block BLK' may correspond to one of the memory blocks BLK1 to BLKz of <FIG>. The memory block BLK' corresponds to a modified example of the memory block BLK of <FIG>, and hereinafter, differences from the memory block BLK of <FIG> will be mainly described. The memory block BLK' may be connected to the bit lines BL1 to BL3, upper erase control lines GIDL_SSU1 to GIDL_SSU3, lower erase control lines GIDL_SSD1 to GIDL_SSD3, upper string select lines SSLU1 to SSLU3, lower string select lines SSLD1 to SSLD3, the word lines WL, upper ground select lines GSLU1 to GSLU3, lower ground select lines GSLD1 to GSLD3, upper ground erase control lines GIDL_GSUI1 to GIDL_GSU3, and lower ground erase control lines GIDL_GSD1 to GIDL_GSD3 and may include the cell strings NS11 to NS33 extending in the vertical direction VD.

For example, the cell string NS11 may include an upper erase control transistor GDTU, a lower erase control transistor GDTD, an upper string select transistor SSTU, a lower string select transistor SSTD, the memory cells MCs, an upper ground select transistor GSTU, a lower ground select transistor GSTD, an upper ground erase control transistor GDT_GSU, and a lower ground erase control transistor GDT_GSD that are connected in series. The upper erase control transistor GDTU may be connected to a corresponding bit line BL1 and a corresponding erase control line GIDL _SSU1, and the lower erase control transistor GDTD may be connected to a corresponding erase control line GIDL_SSD1.

The upper string select transistor SSTU may be connected to a corresponding upper string select line SSLU1, and the lower string select transistor SSTD may be connected to a corresponding lower string select line SSLD1. The upper ground select transistor GSTU may be connected to a corresponding upper ground select line GSLU1, and the lower ground select transistor GSTD may be connected to a corresponding lower ground select line GSLD1. The upper ground erase control transistor GDT_GSU may be connected to a corresponding upper erase control line GIDL_GSU1, and the lower ground erase control transistor GDT_GSD may be connected to a corresponding lower erase control line GIDL_GSD1 and the common source line CSL.

<FIG> is a circuit diagram showing a memory block BLK" according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory block BLK" may correspond to one of the memory blocks BLK1 to BLKz of <FIG>. The memory block BLK" corresponds to a modified example of the memory block BLK of <FIG>, and hereinafter, differences from the memory block BLK of <FIG> will be mainly described. The memory block BLK" may be connected to bit lines BL1 to BL3, erase control lines GIDL_SS1 to GIDL_SS3, string select lines SSL1 to SSL3, word lines WL, and ground select lines GSL1 to GSL3 and may include the cell strings NS11 to NS33 extending in the vertical direction VD. Compared to the memory block BLK of <FIG>, the memory block BLK" may not include a ground erase control line GIDL_GS, and each cell string may not include the ground erase control transistor GDT_GS.

<FIG> is a perspective view of a memory block BLKa according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory block BLKa may correspond to one of the memory blocks BLK1 to BLKz of <FIG>. The memory block BLKa is formed in the vertical direction VD with respect to a substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type) and the common source line CSL extends in the second horizontal direction HD2 on the substrate SUB. In some example embodiments, the common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided to the substrate SUB. In some example embodiments, the substrate SUB may be implemented by using polysilicon, and a plate-type common source line CSL may be disposed on the substrate SUB. On the substrate SUB, a plurality of insulation layers IL extending in the second horizontal direction HD2 are sequentially provided in the vertical direction VD, and the insulation layers IL are spaced apart from one another by a certain distance in the vertical direction VD. For example, the insulation films IL may include an insulating material like silicon oxide.

A plurality of pillars P, which are sequentially arranged in the first horizontal direction HD1 and penetrate through the insulation layers IL in the vertical direction VD, are provided on the substrate SUB. For example, the pillars P will contact the substrate SUB by penetrating through the insulation films IL. In detail, a surface layer S of each pillar P may include a silicon-based material doped with impurities of the first conductivity type and function as a channel region. Therefore, in some example embodiments, a pillar P may be referred to as a channel structure or a vertical channel structure. On the other hand, an internal layer I of each pillar P may include an insulating material like silicon oxide or an air gap.

A charge storage layer CS is provided along exposed surfaces of the insulation layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulation layer (also referred to as a 'tunneling insulation layer'), a charge trapping layer, and a blocking insulation layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, on an exposed surface of the charge storage layer CS, gate electrodes GE like the ground erase control line GIDL_GS, the ground select line GSL, word lines WL1 to WL8, the string select line SSL, and an erase control line GIDL_SS are provided. The numbers of the ground erase control line GIDL_GS, the ground select line GSL, the word lines WL1 to WL8, the string select line SSL, and the erase control line GIDL_SS may vary according to some example embodiments.

Drain contacts or drains DR are provided on the pillars P, respectively. For example, the drains DR may include a silicon-based material doped with impurities of the second conductivity type. The bit lines BL1 to BL3 extending in a first horizontal direction HD1 and being a certain distance apart from one another in the second horizontal direction HD2 may be provided on the drain contacts DR.

<FIG> is a perspective view of a memory block according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory block BLKb may correspond to one of the memory blocks BLK1 to BLKz of <FIG>. Also, the memory block BLKb corresponds to a modified example of the memory block BLKa of <FIG>, and the descriptions given above with reference to <FIG> may also be applied to some example embodiments. The memory block BLKb is formed in the vertical direction VD with respect to the substrate SUB. The memory block BLKb may include a first memory stack ST1 and a second memory stack ST2 stacked in the vertical direction VD. However, the inventive concepts are not limited thereto, and the memory block BLKb may include three or more memory stacks.

<FIG> shows a connection relationship between the memory cell array <NUM> and the page buffer circuit <NUM> according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory cell array <NUM> includes a plurality of cell strings NS11 to NS1m, and the cell strings NS11 to NS1m may each correspond to a vertical cell string extending in a vertical direction with respect to a substrate. The page buffer circuit <NUM> may include a plurality of page buffers PB1 to PBm. The cell strings NS11 to NS1m may be respectively connected to the page buffers PB1 to PBm through a plurality of bit lines BL1 to BLm. Although <FIG> shows the cell strings NS11 to NS1m for convenience of explanation, the memory cell array <NUM> may, for example, as shown in <FIG>, further include cell strings NS21, NS31, NS22, NS32, NS23, and NS33, wherein cell strings NS21 and NS31 may be connected to a page buffer PB1 through a bit line BL1, cell strings NS22 and NS32 may be connected to a page buffer PB2 through a bit line BL2, and cell strings NS23 and NS33 may be connected to a page buffer PB3 through a bit line BL3.

<FIG> shows a page buffer PB according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, the page buffer PB may correspond to one of the page buffers PB1 to PBm of <FIG>, and the bit line BL may correspond to one of the bit lines BL1 to BLm of <FIG>. The page buffer PB may include a bit line selection circuit <NUM>, a switching circuit <NUM>, a sensing latch <NUM>, and a forcing latch <NUM>. However, the inventive concepts are not limited thereto, and the page buffer PB may further include a data latch like an upper bit latch or a lower bit latch, a cache latch, and a pre-charge circuit.

The bit line selection circuit <NUM> may include a bit line shut-off transistor NM1, which is disposed between the bit line BL and a sensing node SO and is driven by a bit line shut-off signal BLSHF. The control logic circuit <NUM> may control the bit line shut-off signal BLSHF for each of a program operation, a read operation, and an erase operation, and the voltage generator <NUM> may provide a voltage corresponding to the bit line shut-off signal BLSHF.

When the bit line shut-off signal BLSHF is at an enable level (e.g., a logic '<NUM>'), the bit line shut-off transistor NM1 is turned on, and thus the bit line BL and the page buffer PB may be electrically connected. In other words, the bit line BL and the sensing node SO may be connected. For example, the enable level may correspond to a bit line setup voltage (e.g., V_BS of <FIG>) or a bit line forcing voltage (e.g., V_BF of <FIG>). On the other hand, when the bit line shut-off signal BLSHF is at a disable level (e.g., a logic '<NUM>'), the bit line shut-off transistor NM1 is turned off, and thus the bit line BL and the page buffer PB may not be electrically connected. In other words, the bit line BL and the sensing node SO may not be connected.

The switching circuit <NUM> may include a sensing transistor NM2 and a forcing transistor NM3. The sensing transistor NM2 may be disposed between the sensing node SO and the sensing latch <NUM> and may be driven by the sensing latch selection signal SS. For example, in a bit line setup interval (e.g., <NUM> of <FIG>), the control logic circuit <NUM> may control the sensing latch selection signal SS to an enable level. Therefore, the sensing transistor NM2 may be turned on, and the sensing latch <NUM> may be electrically connected to the bit line BL through the sensing node SO.

The forcing transistor NM3 may be disposed between the sensing node SO and the forcing latch <NUM> and may be driven by a forcing latch selection signal SF. For example, in a bit line forcing interval (e.g., <NUM> of <FIG>), the control logic circuit <NUM> may control the forcing latch selection signal SF to an enable level. Therefore, the forcing transistor NM3 may be turned on, and the forcing latch <NUM> may be electrically connected to the bit line BL through the sensing node SO.

The sensing latch <NUM> may store bit line setup information BLSU (e.g., Lch1 of <FIG>) and transfer the bit line setup information BLSU to a selected cell string through the bit line BL in a bit line setup interval. For example, the bit line setup information BLSU may correspond to a program bit line voltage or a program inhibit voltage. As such, the sensing latch <NUM> may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. Also, the sensing latch <NUM> may store data stored in a memory cell or a result of sensing a threshold voltage of a memory cell during a read operation or a program verification operation.

The forcing latch <NUM> may store bit line forcing information BLFC (e.g., Lch2 of <FIG>) and transfer the bit line forcing information BLFC to a selected cell string through the bit line BL in a bit line forcing interval. In detail, the bit line forcing information BLFC may correspond to forcing data or force data. The force data may be initially set to '<NUM>' and then inverted to '<NUM>' when the threshold voltage of a memory cell enters a forcing region that is less than a target region. By using the force data, it is possible to control a bit line voltage during a program execution operation and form a narrower program threshold voltage distribution. As such, the forcing latch <NUM> may be utilized to improve threshold voltage distribution during a program operation.

<FIG> is a graph showing a threshold voltage distribution of memory cells according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG>, the sensing latch <NUM> may store first latch information Lch1 corresponding to a verify level Lver. In some example embodiments of the inventive concepts, memory cells having threshold voltages of voltage levels higher than the verify level Lver may be inhibit cells. In this case, the sensing latch <NUM> may store '<NUM>' as the first latch information Lch1. Also, memory cells having threshold voltages of voltage levels lower than the verify level Lver may be program cells. In this case, the sensing latch <NUM> may store '<NUM>' as the first latch information Lch1.

The forcing latch <NUM> may include second latch information Lch2 corresponding to a forcing level Lfc, as forcing information for a bit line forcing operation. The forcing level Lfc may be a voltage level lower than the verify level Lver. In some example embodiments of the inventive concepts, memory cells having threshold voltages of voltage levels that are higher than the forcing level Lfc and lower than the verify level Lver may be forcing cells. When the voltage level of a threshold voltage is higher than the forcing level Lfc, the forcing latch <NUM> may store '<NUM>' as the second latch information Lch2. Also, for program cells other than forcing cells having threshold voltages of voltage levels lower than the forcing level Lfc, the forcing latch <NUM> may store '<NUM>' as the second latch information Lch2. The page buffer PB may apply different voltages Vap to respective cells by using the first latch information Lch1 and the second latch information Lch2.

The page buffer PB may perform a program operation including a bit line forcing operation by using a two-step verification method. When programming is performed on the program cells at only one voltage level, voltage distribution may be widened. Therefore, based on the forcing level Lfc, the page buffer PB of the inventive concepts may perform a first program operation on cells not to be forced with a bit line program voltage and perform a second program operation on cells to be forced with a bit line forcing voltage V_BF. In detail, the page buffer PB may apply the bit line forcing voltage V_BF, which is higher than a bit line program voltage and lower than a bit line inhibit voltage, to cells to be forced to perform a bit line forcing operation.

In some example embodiments, the bit line program voltage may be a ground voltage GND, the bit line inhibit voltage may be a power voltage VDD, and the bit line forcing voltage V_BF may have a voltage level between that of the power voltage VDD and that of the ground voltage GND. Therefore, the page buffer PB may distinguish inhibit target cells, forcing cells, and program cells not to be forced based on the first latch information Lch1 and the second latch information Lch2. In detail, the page buffer PB may distinguish program cells and an inhibit cells by using the first latch information Lch1 in a bit line setup operation and distinguish cells to be forced and program cells not to be forced by using the second latch information Lch2 in a bit line forcing operation.

Therefore, the page buffer PB may apply a bit line inhibit voltage to cells to be inhibited, apply the bit line forcing voltage V_BF to cells to be forced, and apply a bit line program voltage to program cells not to be forced. Therefore, the first latch information Lch1 may be referred to as "bit line setup information" and the second latch information Lch2 may be referred to as "bit line forcing information".

<FIG> is a timing diagram showing a program operation of a memory device according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, a bit line setup interval <NUM> is an interval from t0 to t1 and may be defined as an interval in which the bit line shut-off voltage V_BLSHF corresponding to the bit line shut-off signal BLSHF maintains a voltage level corresponding to a bit line setup voltage V_BS. In the bit line setup interval <NUM>, an erase control voltage V_GIDL_SS applied to an erase control line GILD_SS may rise to a bias voltage VBIAS, and the string select line voltage V_SSL applied to the string select line SSL may rise to a fourth voltage V4.

In a program execution interval <NUM>, a selected word line voltage V_WLsel applied to a selected word line may correspond to a program voltage VPGM, and an unselected word line voltage V_WLunsel applied to an unselected word line may correspond to a pass voltage VPASS. The program execution interval <NUM> may be divided into a first interval INT1 from t1 to t2, a second interval INT2 from t2 to t3, and a third interval INT3 from t3 to t4.

The second interval INT2 may be defined as an interval in which the bit line shut-off voltage V_BLSHF maintains a voltage level corresponding to the bit line forcing voltage V_BF and may be referred to as a "bit line forcing interval". In the second interval INT2, a voltage applied to the bit line BL may be varied according to a value stored in the forcing latch <NUM> (e.g., forcing information), during program execution. The first interval INT1 may correspond to an interval before a bit line forcing interval of the program execution interval <NUM>, and the third interval INT3 may correspond to an interval after the bit line forcing interval of the program execution interval <NUM>.

In some example embodiments, in the program execution interval <NUM>, the string select line voltage V_SSL may be controlled for each of first to third intervals INT1, INT2, and INT3. For example, the string select line voltage V_SSL may be controlled to the first voltage V1 in the first interval INT1, the string select line voltage V_SSL may be controlled to the second voltage V2 in the second interval INT2, and the string select line voltage V_SSL may be controlled to the third voltage V3 in the third interval INT3. In this case, at least two of first to third voltages V1, V2, and V3 may have different voltage levels.

As such, the bit line setup interval <NUM> and the program execution interval <NUM> shown in <FIG> may correspond to an N-th loop of a program operation, where N is a positive integer equal to or greater than <NUM>. In detail, since forcing information may be stored in the forcing latch <NUM> according to a result of a first loop of a program operation, the bit line setup interval <NUM> and the program execution interval <NUM> may respond to a second loop or later loops. Although not shown, the program execution interval <NUM> may be followed by a program verify interval.

<FIG> is a diagram schematically showing a memory device 100a according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory device 100a may include the common source line CSL and the bit line BL extending in the first horizontal direction HD1 and may include a memory stack ST extending in the vertical direction VD. In this case, the stack ST may be connected to the bit line BL through a drain DR. For example, the memory device 100a may correspond to the example of <FIG>, wherein the memory stack ST may correspond to the pillar P of <FIG> and may also correspond to a first cell string NS11 of <FIG>.

The memory device 100a may further include the word lines WL1 to WLn stacked in the vertical direction VD, the ground select line GSL may be disposed between the common source line CSL and a word line WL1, and the string select line SSL may be disposed between the bit line BL and a word line WLn. Although not shown, an erase control line (e.g., GIDL_SS of <FIG>) may be further disposed between the string select line SSL and the bit line BL, and an erase control line (e.g., GIDL_GS of <FIG>) may be further disposed between the ground select line GSL and the common source line CSL.

In some example embodiments, the word lines WL1 to WLn may be grouped into a plurality of groups including a first group GRa and a second group GRb. The first group GRa may include word lines (e.g., WL1 to WLk) relatively close to a substrate and the second group GRb may include word lines (e.g., WLk+<NUM> to WLn) relatively far from the substrate, wherein k is a positive integer between <NUM> and n. According to some example embodiments, the word lines WL1 to WLn may be grouped into three or more groups.

<FIG> is a table showing voltages applied to a string select line according to selected word lines during a program operation of the memory device 100a of FIG. 10A according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, in a bit line setup interval BLSETUP, when a selected word line corresponds to one of the word lines WL1 to WLk of the first group GRa, a fourth voltage V4a may be applied to the string select line. Meanwhile, in the bit line setup interval BLSETUP, when the selected word line corresponds to one of the word lines WLk+<NUM> to WLn of the second group GRb, a fourth voltage V4b may be applied to the string select line.

In a program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WL1 to WLk of the first group GRa, a first voltage V1a may be applied to the string select line in the first interval INT1, a second voltage V2a may be applied to the string select line in the second interval INT2, and a third voltage V3a may be applied to the string select line in the third interval INT3. Meanwhile, in the program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WLk+<NUM> to WLn of the second group GRb, a first voltage V1b may be applied to the string select line in the first interval INT1, a second voltage V2b may be applied to the string select line in the second interval INT2, and a third voltage V3b may be applied to the string select line in the third interval INT3.

<FIG> is a diagram schematically showing a memory device 100b according to some example embodiments of the inventive concepts.

Referring to <FIG>, the memory device 100b may include the common source line CSL and the bit line BL extending in the first horizontal direction HD1 and may include the first memory stack ST1 and the second memory stack ST2 extending in the vertical direction VD. In this case, the first memory stack ST1 is disposed on the common source line CSL, and the second memory stack ST2 is disposed on the first memory stack ST1 and may be connected to the bit line BL through the drain DR. For example, the memory device 100b may corresponds to the example of <FIG>, and the first memory stack ST1 and the second memory stack ST2 may correspond to the first memory stack ST1 and the second memory stack ST2 of <FIG>, respectively.

The memory device 100b may further include the word lines WL1 to WLn stacked in the vertical direction VD, the ground select line GSL may be disposed between the common source line CSL and a word line WL1, and the string select line SSL may be disposed between the bit line BL and a word line WLn. Also, the memory device 100b may further include first and second junction dummy word lines CDL1 and CDL2 corresponding to the junction of the first memory stack ST1 and the second memory stack ST2. However, the inventive concepts are not limited thereto, and the number of junction dummy word lines corresponding to the junction may vary according to some example embodiments. Also, according to some example embodiments, no junction dummy word line may be provided.

In some example embodiments, the word lines WL1 to WLn may be grouped into a plurality of groups including the first group GRa, the second group GRb, a third group GRc, and a fourth group GRd. The first group GRa and the second group GRb may include word lines connected to the first memory stack ST1, and the third group GRc and the fourth group GRd may include word lines connected to the second memory stack ST2. The first group GRa may include word lines (e.g., WL1 to WLa) relatively close to a substrate, and the second group GRb may include word lines (e.g., WLa+<NUM> to WLb) farther from the substrate as compared to the word lines of the first group GRa. Here, a and b are positive integers between <NUM> and n, and a is smaller than b. The third group GRc may include word lines (e.g., WLb+<NUM> to WLc) farther from the substrate as compared to the word lines of the second group GRb, and the fourth group GRd may include word lines (e.g., WLc+<NUM> to WLn) farther from the substrate as compared to the word lines of the third group GRc, where c is a positive integer between b and n. According to some example embodiments, the word lines WL1 to WLn may be grouped into five or more groups.

In some example embodiments, the memory device may include three or more memory stacks, and, as the number of memory stacks increases, the number of groups corresponding to a plurality of word lines may also increase. For example, when the memory device includes three memory stacks, a plurality of word lines may be grouped into six groups, but the inventive concepts are not limited thereto.

<FIG> is a table showing voltages applied to a string select line according to selected word lines during a program operation of the memory device 100b of <FIG> according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, in a bit line setup interval BLSETUP, when a selected word line corresponds to one of the word lines WL1 to WLa of the first group GRa, the fourth voltage V4a may be applied to the string select line. Meanwhile, in the bit line setup interval BLSETUP, when the selected word line corresponds to one of the word lines WLa+<NUM> to WLb of the second group GRb, the fourth voltage V4b may be applied to the string select line. In the bit line setup interval BLSETUP, when the selected word line corresponds to one of the word lines WLb+<NUM> to WLc of the third group GRc, a fourth voltage V4c may be applied to the string select line. In the bit line setup interval BLSETUP, when the selected word line corresponds to one of the word lines WLc+<NUM> to WLn of the fourth group GRd, a fourth voltage V4d may be applied to the string select line.

In a program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WL1 to WLa of the first group GRa, a first voltage V1a may be applied to the string select line in the first interval INT1, a second voltage V2a may be applied to the string select line in the second interval INT2, and a third voltage V3a may be applied to the string select line in the third interval INT3. In the program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WLa+<NUM> to WLb of the second group GRb, a first voltage V1b may be applied to the string select line in the first interval INT1, a second voltage V2b may be applied to the string select line in the second interval INT2, and a third voltage V3b may be applied to the string select line in the third interval INT3. In the program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WLb+<NUM> to WLc of the third group GRc, a first voltage V1c may be applied to the string select line in the first interval INT1, a second voltage V2c may be applied to the string select line in the second interval INT2, and a third voltage V3c may be applied to the string select line in the third interval INT3. In the program execution interval PGMEXE, when the selected word line corresponds to one of the word lines WLc+<NUM> to WLn of the fourth group GRd, a first voltage V1d may be applied to the string select line in the first interval INT1, a second voltage V2d may be applied to the string select line in the second interval INT2, and a third voltage V3d may be applied to the string select line in the third interval INT3.

<FIG> is a timing diagram showing a voltage applied to a string select line during a program operation for the first group GRa according to some example embodiments of the inventive concepts.

Referring to <FIG>, when a selected word line corresponds to one of word lines of the first group GRa, the string select line voltage V_SSL may be controlled to the first voltage V1a having a voltage level higher than that of the fourth voltage V4a in the first interval INT1 before a bit line forcing operation. In this case, the voltage level of the first voltage V1a may be higher than the voltage level of the fourth voltage V4a by a first offset OSa. Therefore, initial channel recovery may be efficiently performed.

In particular, during a program operation on a bottom word line, by setting the voltage level of the first voltage V1a to be relatively high, initial channel recovery may be smoothly performed. For example, in top to bottom (T2B) programming in which the program sequence is in the direction from the string select line SSL to the ground select line GSL, programming of memory cells connected to the top word line is already completed, the first voltage V1a may be set to be relatively high during a program operation on memory cells connected to the bottom word line. For example, in bottom to top (B2T) programming in which the program sequence is a direction from the ground select line GSL to the string select line SSL, a channel region corresponding to the bottom word line is relatively far from a bit line. Therefore, the voltage level of the first voltage V1a may be set to be relatively high, thereby facilitating initial channel recovery.

During the second interval INT2 in which the bit line forcing operation is performed, the string select line voltage V_SSL may be controlled to the second voltage V2a. For example, the voltage level of the second voltage V2a may correspond to a voltage level between the voltage level of the first voltage V1a and the voltage level of the third voltage V3a, but the inventive concepts are not limited thereto. During the third interval INT3 after the bit line forcing operation, the string select line voltage V_SSL may be controlled to the third voltage V3a. For example, the voltage level of the third voltage V3a may be lower than the voltage level of the first voltage V1a and the voltage level of the second voltage V2a, but the inventive concepts are not limited thereto. For example, the voltage level of the third voltage V3a may be the same as the voltage level of the fourth voltage V4a, but the inventive concepts are not limited thereto.

<FIG> is a timing diagram showing a voltage applied to a string select line during a program operation for the second group GRb according to some example embodiments of the inventive concepts.

Referring to <FIG>, when a selected word line corresponds to one of word lines of the second group GRb, the string select line voltage V_SSL may be controlled to the first voltage V1b having a voltage level higher than that of the fourth voltage V4b in the first interval INT1 before a bit line forcing operation. In this case, the voltage level of the first voltage V1b may be higher than the voltage level of the fourth voltage V4b by a second offset OSb. In this case, the second offset OSb may be smaller than the first offset OSa.

During the second interval INT2 in which the bit line forcing operation is performed, the string select line voltage V_SSL may be controlled to the second voltage V2b. For example, the voltage level of the second voltage V2b may correspond to a voltage level between the voltage level of the first voltage V1b and the voltage level of the third voltage V3b, but the inventive concepts are not limited thereto. During the third interval INT3 after the bit line forcing operation, the string select line voltage V_SSL may be controlled to the third voltage V3b. For example, the voltage level of the third voltage V3b may be lower than the voltage level of the first voltage V1b and the voltage level of the second voltage V2b, but the inventive concepts are not limited thereto. For example, the voltage level of the third voltage V3b may be the same as the voltage level of the fourth voltage V4b, but the inventive concepts are not limited thereto.

<FIG> is a timing diagram showing a program operation for a memory device according to some example embodiments of the inventive concepts.

Referring to <FIG>, the program execution interval <NUM> may be divided into first to third intervals INT1, INT2, and INT3, the program execution interval <NUM> may correspond to an interval after a bit line setup interval (e.g., FIG. <NUM> of <NUM>), and the program execution interval <NUM> may be followed by a program verify interval. Also, the program execution interval <NUM> may be included in an N-th loop during a program operation of the memory device, where N is a positive integer greater than <NUM>.

The string select line voltage V_SSL may be controlled for each of the first to third intervals INT1, INT2, and INT3. For example, the string select line voltage V_SSL may be controlled to the first voltage V1 in the first interval INT1, may be controlled to the second voltage V2 in the second interval INT2, and may be controlled to the third voltage V3 in the third interval INT3. According to some example embodiments, at least two of first to third voltages V1 to V3 may have different voltage levels. However, the inventive concepts are not limited thereto, and, in some example embodiments, all of the first to third voltages V1 to V3 may have the same voltage level. Also, the control logic circuit <NUM> may not individually control the string select line voltage V_SSL for each of the first to third intervals INT1, INT2, and INT3.

The selected word line voltage V_WLsel applied to a selected word line may rise to the program voltage VPGM in the program execution interval <NUM>. For example, the selected word line voltage V_WLsel may rise from the power voltage VDD to the program voltage VPGM at t2 and may fall from the program voltage VPGM to the ground voltage GND at t4. However, the inventive concepts are not limited thereto, and the timing at which the selected word line voltage V_WLsel rises to the program voltage VPGM may vary according to example embodiments.

The unselected word line voltage V_WLunsel applied to an unselected word line may rise from the ground voltage GND to the pass voltage VPASS in the program execution interval <NUM>. For example, the unselected word line voltage V _WLunsel may rise from the ground voltage GND to the pass voltage VPASS at t2 and may fall from the pass voltage VPASS to the ground voltage GND at t4. However, the inventive concepts are not limited thereto, and the timing at which the unselected word line voltage V_WLunsel rises to the pass voltage VPASS may vary according to example embodiments.

According to some example embodiments, the waveform of a bit line shut-off voltage corresponding to the bit line shut-off signal BLSHF may be controlled according to the position of a selected word line on which a program operation is performed. For example, when the selected word line is a normal word line, the second interval INT2 in which a bit line forcing operation is performed may correspond to an interval from t2 to t3. Here, the bit line shut-off voltage V_BLSHFn may be the ground voltage GND in the first interval INT1, may maintain a voltage level corresponding to a bit line forcing voltage V_FC in the second interval INT2, and may fall back to the ground voltage GND. Here, the normal word line may be referred to as a reference word line.

When the selected word line corresponds to one of the word lines WL1 to WLk of a first group (e.g., GRa of <FIG>), a delay interval in which a bit line shut-off voltage V_BLSHFa maintains a voltage level corresponding to the ground voltage GND before a bit line forcing operation may be increased by a first delay Ta as compared to a bit line shut-off voltage V_BLSHFn. Therefore, as compared to the bit line shut-off voltage V_BLSHFn, the first interval INT1 for the bit line shut-off voltage V_BLSHFa may increase to t2a, and the second interval INT2 may be reduced from t2a to t3.

Meanwhile, when the selected word line corresponds to one of the word lines WLk+<NUM> to WLn of a second group (e.g., GRb of <FIG>), a delay interval in which a bit line shut-off voltage V_BLSHFb maintains a voltage level corresponding to the ground voltage GND before a bit line forcing operation may be increased by a second delay Tb as compared to the bit line shut-off voltage V_BLSHFn. Therefore, as compared to the bit line shut-off voltage V_BLSHFn, the first interval INT1 for the bit line shut-off voltage V_BLSHFb may increase to t2b, and the second interval INT2 may be reduced from t2b to t3.

<FIG> shows a voltage waveform of a bit line shut-off signal during a program operation of a memory device according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, the horizontal axis represents time and the vertical axis represents the bit line shut-off voltage V_BLSHF. A bit line shut-off voltage <NUM> represents a voltage waveform controlled for a bit line forcing operation according to some example embodiments and, for example, may correspond to the bit line shut-off voltage V_BLSHFa or the bit line shut-off voltage V_BLSHFb of <FIG>. A bit line shut-off voltage <NUM> represents a voltage waveform controlled for a bit line forcing operation according to a comparative example and, for example, may correspond to the bit line shut-off voltage V_BLSHFn of <FIG>.

The bit line shut-off voltage <NUM> may be generated as a ramp waveform having a certain slope and may rise from the ground voltage to the bit line forcing voltage V_BF. On the contrary, the bit line shut-off voltage <NUM> may be generated as a step waveform having a plurality of steps and may rise from the ground voltage to the bit line forcing voltage V_BF. The control logic circuit <NUM> may control the voltage level of a bit line shut-off signal (e.g., the bit line shut-off voltage <NUM>) to a step waveform before a bit line forcing operation for transferring forcing information to a selected cell string through a bit line is performed during a program operation on a selected word line.

In some example embodiments, when during a program operation on the selected word line, the control logic circuit <NUM> may control a delay interval in which the voltage level of a bit line shut-off voltage (e.g., the bit line shut-off voltage <NUM>) maintains a voltage level corresponding to the ground voltage, before a bit line forcing operation is performed. The control logic circuit <NUM> may delay a start time of application of the bit line forcing voltage V_BF from t2 to t2' by a certain delay. In this case, the control logic circuit <NUM> may differently control the delay according to the position of the selected word line.

In some example embodiments, the control logic circuit <NUM> may control a maintenance interval (e.g., a cycle) of each of a plurality of steps for performing a bit line forcing operation. In this case, the control logic circuit <NUM> may differently control the cycle according to the position of the selected word line. In some example embodiments, the control logic circuit <NUM> may control a rising voltage (e.g., a step) of each of a plurality of steps for performing a bit line forcing operation. In this case, the control logic circuit <NUM> may differently control the step according to the position of the selected word line. In some example embodiments, the control logic circuit <NUM> may control the number of a plurality of steps for performing a bit line forcing operation. In this case, the control logic circuit <NUM> may differently control the number of the steps according to the position of the selected word line.

<FIG> shows an operation of controlling a bit line shut-off signal according to a selected word line during a program operation of a memory device according to some example embodiments of the inventive concepts.

Referring to <FIG>, <FIG>, and <FIG> together, in a program execution interval, when a selected word line corresponds to one of the word lines WL1 to WLk of the first group GRa, the bit line shut-off voltage V_BLSHF corresponding to the bit line shut-off signal BLSHF may be generated to have the first delay Ta, a first step Va, and a first cycle T'a. Meanwhile, in the program execution interval, when the selected word line corresponds to one of the word lines WLk+<NUM> to WLn of the second group GRb, the bit line shut-off voltage V_BLSHF corresponding to the bit line shut-off signal BLSHF may be generated to have the second delay Tb, a second step Vb, and a second cycle T'b.

In some example embodiments, the first delay Ta may be longer than the second delay Tb, and thus a time point for applying the bit line shut-off voltage V_BLSHF for a bit line forcing operation during a program operation on a bottom word line may be later than a time point for applying the bit line shut-off voltage V_BLSHF for a bit line forcing operation during a program operation on a top word line.

In some example embodiments, the first step Va may be greater than the second step Vb, and thus each step of a step waveform corresponding to the bit line shut-off voltage V_BLSHF for the bit line forcing operation during the program operation on the bottom word line may be greater than each step of a step waveform corresponding to the bit line shut-off voltage V_BLSHF for the bit line forcing operation during the program operation on the top word line. In some example embodiments, the first cycle T'a may be shorter than the second cycle T'b, and thus a time for maintaining each step of the step waveform corresponding to the bit line shut-off voltage V_BLSHF for the bit line forcing operation during the program operation on the bottom word line may be shorter than a time for maintaining each step of the step waveform corresponding to the bit line shut-off voltage V_BLSHF for the bit line forcing operation during the program operation on the bottom word line.

In some example embodiments, the word lines WL1 to WLn may be grouped into three or more groups, and the control logic circuit <NUM> may individually control a delay, a step, and a cycle of the bit line shut-off voltage V_BLSHF for each of the three or more groups. For example, at least one of the delay, the step, and the cycle of the bit line shut-off voltage V_BLSHF may be different for each of the three or more groups.

In some example embodiments, the memory device may include a plurality of memory stacks, for example, as shown in <FIG> or <FIG>. The control logic circuit <NUM> may group word lines corresponding to each memory stack into two or more groups and may control at least one of the delay, the step, and the cycle of the bit line shut-off voltage V_BLSHF for different groups.

<FIG> shows a memory device <NUM> having a cell over peri (COP) structure, according to some example embodiments of the inventive concepts.

Referring to <FIG> and <FIG> together, the memory device <NUM> may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked in the vertical direction VD with respect to the second semiconductor layer L2. In detail, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD. The memory device <NUM> of <FIG> may have a COP structure like the memory device <NUM>.

In some example embodiments, the memory cell array <NUM> may be formed on the first semiconductor layer L1, whereas the control logic circuit <NUM>, the page buffer circuit <NUM>, the voltage generator <NUM>, and the row decoder <NUM> may be formed on the second semiconductor layer L2. Therefore, the memory device <NUM> may have a structure in which the memory cell array <NUM> is disposed over some peripheral circuits, that is, the COP structure. The COP structure can effectively reduce a horizontal area and improve the degree of integration of the memory device <NUM>.

In some example embodiments, the second semiconductor layer L2 may include a substrate, and circuits may be formed on the second semiconductor layer L2 by forming semiconductor devices like transistors and patterns for distributing devices on the substrate. After circuits are formed on the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array <NUM> may be formed, and patterns for electrically connecting the word lines WL and bit lines BL of the memory cell array <NUM> to the circuits formed on the second semiconductor layer L2 may be formed.

<FIG> is a cross-sectional view of a memory device <NUM> having a bonding vertical NAND (B-VNAND) structure, according to some example embodiments of the inventive concepts. When a non-volatile memory included in a memory device is implemented as a B-VNAND type flash memory, the non-volatile memory may have the structure shown in <FIG>.

Referring to <FIG>, a cell region CELL of a memory device <NUM> may correspond to a first semiconductor layer L1, and a peripheral circuit region PERI may correspond to a second semiconductor layer L2. The peripheral circuit region PERI and the cell region CELL of the memory device <NUM> may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. For example, the word lines WL, the string select lines SSL, the ground select lines GSL, and the memory cell array <NUM> of <FIG> may be formed on the first semiconductor layer L1, whereas the control logic circuit <NUM>, the page buffer circuit <NUM>, the voltage generator <NUM>, and the row decoder <NUM> may be formed on the second semiconductor layer L2.

The peripheral circuit region PERI may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate <NUM>, first metal layers 630a, 630b, and 630c respectively connected to the plurality of circuit elements 620a, 620b, and 620c, and second metal layers 640a, 640b, and 640c formed on the first metal layers 630a, 630b, and 630c. In some example embodiments, the first metal layers 630a, 630b, and 630c may be formed of tungsten having relatively high resistivity, and the second metal layers 640a, 640b, and 640c may be formed of copper having relatively low resistivity.

In some example embodiments, although only the first metal layers 630a, 630b, and 630c and the second metal layers 640a, 640b, and 640c are shown and described, the example embodiments are not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 640a, 640b, and 640c. At least a portion of the one or more additional metal layers formed on the second metal layers 640a, 640b, and 640c may be formed of aluminum or the like having a lower resistivity than those of copper forming the second metal layers 640a, 640b, and 640c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> and cover the plurality of circuit elements 620a, 620b, and 620c, the first metal layers 630a, 630b, and 630c, and the second metal layers 640a, 640b, and 640c. The interlayer insulating layer <NUM> may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 671b and 672b may be formed on the second metal layer 640b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b in the peripheral circuit region PERI may be electrically bonded to upper bonding metals 571b and 572b of the cell region CELL. The lower bonding metals 671b and 672b and the upper bonding metals 571b and 572b may be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals 571b and 572b in the cell region CELL may be referred as first metal pads and the lower bonding metals 5271b and 5272b in the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate <NUM> and a common source line <NUM>. On the second substrate <NUM>, a plurality of word lines <NUM> to <NUM> (e.g., <NUM>) may be stacked in a vertical direction VD, perpendicular to an upper surface of the second substrate <NUM>. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines <NUM>, respectively, and the plurality of word lines <NUM> may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CHS may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate <NUM>, and pass through the plurality of word lines <NUM>, the at least one string select line, and the at least one ground select line. The channel structure CHS may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer 550c and a second metal layer 560c. For example, the first metal layer 550c may be a bit line contact, and the second metal layer 560c may be a bit line. In some example embodiments, the bit line 560c may extend in a second horizontal direction HD2, parallel to the upper surface of the second substrate <NUM>.

In some example embodiments, an area in which the channel structure CHS, the bit line 560c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 560c may be electrically connected to the circuit elements 620c providing a page buffer <NUM> in the peripheral circuit region PERI. The bit line 560c may be connected to upper bonding metals 571c and 572c in the cell region CELL, and the upper bonding metals 571c and 572c may be connected to lower bonding metals 671c and 672c connected to the circuit elements 620c of the page buffer <NUM>.

In the word line bonding area WLBA, the plurality of word lines <NUM> may extend in a first horizontal direction HD1, parallel to the upper surface of the second substrate <NUM>, and may be connected to a plurality of cell contact plugs <NUM> to <NUM> (e.g., <NUM>). The plurality of word lines <NUM> and the plurality of cell contact plugs <NUM> may be connected to each other in pads provided by at least a portion of the plurality of word lines <NUM> extending in different lengths in the second horizontal direction HD2. A first metal layer 550b and a second metal layer 560b may be connected to an upper portion of the plurality of cell contact plugs <NUM> connected to the plurality of word lines <NUM>, sequentially. The plurality of cell contact plugs <NUM> may be connected to the peripheral circuit region PERI by the upper bonding metals 571b and 572b of the cell region CELL and the lower bonding metals 671b and 672b of the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs <NUM> may be electrically connected to the circuit elements 620b providing a row decoder <NUM> in the peripheral circuit region PERI. In some example embodiments, operating voltages of the circuit elements 620b of the row decoder <NUM> may be different than operating voltages of the circuit elements 620c providing the page buffer <NUM>. For example, operating voltages of the circuit elements 620c providing the page buffer <NUM> may be greater than operating voltages of the circuit elements 620b providing the row decoder <NUM>.

A common source line contact plug <NUM> may be disposed in the external pad bonding area PA. The common source line contact plug <NUM> may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line <NUM>. A first metal layer 550a and a second metal layer 560a may be stacked on an upper portion of the common source line contact plug <NUM>, sequentially. For example, an area in which the common source line contact plug <NUM>, the first metal layer 550a, and the second metal layer 560a are disposed may be defined as the external pad bonding area PA.

Input-output pads <NUM> and <NUM> may be disposed in the external pad bonding area PA. A lower insulating film <NUM> covering a lower surface of the first substrate <NUM> may be formed below the first substrate <NUM>, and a first input-output pad <NUM> may be formed on the lower insulating film <NUM>. The first input-output pad <NUM> may be connected to at least one of the plurality of circuit elements 620a, 620b, and 620c disposed in the peripheral circuit region PERI through a first input-output contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating film <NUM>. In addition, a side insulating film may be disposed between the first input-output contact plug <NUM> and the first substrate <NUM> to electrically separate the first input-output contact plug <NUM> and the first substrate <NUM>.

An upper insulating film <NUM> covering the upper surface of the second substrate <NUM> may be formed on the second substrate <NUM>, and a second input-output pad <NUM> may be disposed on the upper insulating film <NUM>. The second input-output pad <NUM> may be connected to at least one of the plurality of circuit elements 620a, 620b, and 620c disposed in the peripheral circuit region PERI through a second input-output contact plug <NUM>.

According to some example embodiments, the second substrate <NUM> and the common source line <NUM> may not be disposed in an area in which the second input-output contact plug <NUM> is disposed. Also, the second input-output pad <NUM> may not overlap the word lines <NUM> in the vertical direction VD. The second input-output contact plug <NUM> may be separated from the second substrate <NUM> in a direction, parallel to the upper surface of the second substrate <NUM>, and may pass through an interlayer insulating layer of the cell region CELL to be connected to the second input-output pad <NUM>.

According to some example embodiments, the first input-output pad <NUM> and the second input-output pad <NUM> may be selectively formed. For example, the memory device <NUM> may include only the first input-output pad <NUM> disposed on the first substrate <NUM> or the second input-output pad <NUM> disposed on the second substrate <NUM>. Alternatively, the memory device <NUM> may include both the first input-output pad <NUM> and the second input-output pad <NUM>.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device <NUM> may include a lower metal pattern 673a, corresponding to an upper metal pattern 572a formed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 572a of the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 673a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals 671b and 672b may be formed on the second metal layer 640b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 671b and 672b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 571b and 572b of the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit line bonding area BLBA, an upper metal pattern <NUM>, corresponding to a lower metal pattern <NUM> formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern <NUM>, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern <NUM> formed in the uppermost metal layer of the cell region CELL.

<FIG> is a block diagram showing an SSD system to which a memory device according to some example embodiments of the inventive concepts are applied.

Referring to <FIG>, an SSD system <NUM> may include a host <NUM> and an SSD <NUM>. The SSD <NUM> exchanges signals SIG with the host <NUM> through a signal connector <NUM> and receives power PWR through a power connector <NUM>. The SSD <NUM> may include an SSD controller <NUM>, an auxiliary power supply device <NUM>, and a plurality of memory devices <NUM>, <NUM>, and 122n. The memory devices <NUM>, <NUM>, and 122n may be vertically stacked NAND flash memory devices. Here, the SSD <NUM> may be implemented according to the embodiments described above with reference to <FIG>.

The memory system <NUM> (or other circuitry, for example, the memory device <NUM>, control logic circuit <NUM>, page buffer circuit <NUM>, memory controller <NUM>, SSD system <NUM>, host <NUM>, SSD <NUM>, or SSD controller <NUM>) may include hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

Claim 1:
A non-volatile memory device (<NUM>) comprising:
a memory cell array (<NUM>) including a plurality of cell strings (NS11 - NS1m), each cell string extending in a vertical direction above a substrate (SUB) and each cell string including a plurality of memory cells (MC) respectively connected to a plurality of word lines (WL1 - WLn) and a string select transistor (SST) connected to a string select line (SSL);
a page buffer circuit (<NUM>) including a plurality of page buffers (PB1 - PBm) connected to the memory cell array (<NUM>), each page buffer (PB1 - PBm) including a forcing latch (<NUM>) configured to store forcing information and each page buffer (PB1 - PBm) is connected to a selected cell string through a bit line (BL1 - BLm); and
a control logic circuit (<NUM>)
characterised in that the control logic circuit is configured to, during a program operation on a selected word line, control at least two of a first voltage (V1) applied to the string select line (SSL) in a first interval (INT1) before a bit line forcing operation for transferring the forcing information to the selected cell string through the bit line (BL1 - BLm), a second voltage (V2) applied to the string select line (SSL) in a second interval (INT2) in which the bit line forcing operation is performed, and a third voltage (V3) applied to the string select line (SSL) in a third interval (INT3) after the bit line forcing operation is performed, to be different from each other.