Patent Description:
The following relates generally to memory devices and more specifically to thermal insulation for three-dimensional memory arrays.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.

Multiple types of memory devices exist, including magnetic hard disks, random access memory (RAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), read only memory (ROM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., PCM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. Improving memory devices may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.

PCM may be non-volatile and may offer improved read/write speeds and endurance compared to other memory devices. PCM may also offer increased memory cell density. For example, three-dimensional memory arrays may be possible with PCM.

Some memory types may generate heat during operation, for example, reading or writing a memory cell. For example, a PCM memory cell may be heated to high temperatures during a read or write operation. Other memory types or memory cell operations may generate heat as well. This heating may increase the temperature of neighboring memory cells, which may corrupt the stored data of the array. Such heating may make the array unreliable for data storage or place constraints on memory cell spacing, which may inhibit future cost savings or increases in memory array performance.

<CIT> relates to a method for manufacturing a three-dimensional resistive memory array. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer as constituent select transistor layers. By performing a plurality of processing steps on the repetitive sequence including the formation of elongated trenches through the repetitive sequence to form an elongated stack and the deposition of a resistive layer of a binary transition metal oxide on one of the side surfaces of the elongated stack, a three-dimensional resistive memory array is obtained.

<CIT> relates to a three-dimensional flash memory using a fringing effect and a method of manufacturing the same. A through hole is formed through a plurality of gate electrodes vertically stacked on a substrate, and the interior of the through hole is filled with a tunneling insulating layer or an active region. Therefore, a charge storage layer is not formed in the through hole, but is formed outside of the through hole. The charge storage layer is formed in an intercell insulating layer filling a gap between the gate electrodes. When a fringing electric field is applied, the electric charges of the active region are trapped in the charge storage layer through the intercell insulating layer.

The disclosure herein refers to and includes the following figures:.

Thermal effects between and among memory cells of an array may significantly limit the performance of the memory array. Reducing negative thermal effects between memory cells of an array may thus allow for increased capacity, reliability, and cost-effectiveness of the array.

Decreased manufacturing costs and increased performance of memory arrays may depend on increasing memory cell density by forming memory cells close to one another on a planar substrate. Three-dimensional (3D) memory arrays have given rise to another dimension for memory arrays expand, significantly increasing memory cell density for a given planar substrate. These 3D architectures may also enable reduction in component size and increased memory cell density. As memory cells are packed more closely together, however, their operation may affect neighboring memory cells.

In some memory technologies, including phase change memory (PCM), reading or writing the logic state of the memory cell may result in the heating of the memory cell. Logic states in PCM may be set by controlling the electrical resistance of a memory cell. This may include melting and then cooling a material of the memory cell to create a high resistance state. In other cases, a memory cell may be heated to moderately high temperatures to create a low electrical resistance state. Heating one memory cell, however, may affect neighboring cells. As the heat diffuses away, the neighboring cell may increase in temperature. This may transform the material of the neighboring cell and ultimately change or corrupt the stored data. This so-called "thermal disturb" may become increasingly problematic as memory cells are packed more closely together. In some cases, thermal disturb may limit further reduction in memory cell spacing.

Thus, as described herein, a three-dimensional memory array according to a first aspect is recited in Claim <NUM>, and a method of forming a three-dimensional memory array according to a second aspect is recited in Claim <NUM>. Memory cells are separated by thermally insulating regions. These regions include at least two sublayers to create one or more interfaces, which may increase the thermal resistance of the region. The interfaces may be formed in a number of ways, including layering different materials upon on another or adjusting the deposition parameters of a material during deposition. In some embodiments, the interfaces may be substantially parallel to a substrate and, thus, may be created by cost-effective planar thin-film deposition techniques.

Features and techniques introduced above are further described below in the context of a memory array. Specific examples are then described for three-dimensional memory arrays with thermally insulating layers that minimize thermal disturb of adjacent memory cells. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to reduced thermal disturb in three-dimensional memory arrays. Although the present disclosure is discussed in terms of PCM, it may apply to other memory types. For example, other memory types that use increased temperatures to read or write a memory cell. Or, in other examples, where the operation of the memory device generates heat that may disturb memory cells.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various embodiments of the present disclosure. Memory array <NUM> may also be referred to as an electronic memory apparatus. Memory array <NUM> includes memory cells <NUM> that are programmable to store different states. Each memory cell <NUM> may be programmable to store two states, denoted a logic <NUM> and a logic <NUM>. In some cases, memory cell <NUM> is configured to store more than two logic states.

A memory cell <NUM> may include a material, which may be referred to as a memory element, that has a variable and configurable electrical resistance that is representative of the logic states. For example, a material with a crystalline or an amorphous atomic configuration may have different electrical resistances. A voltage applied to the memory cell <NUM> may thus result in different currents depending on whether the material is in a crystalline or an amorphous state, and the magnitude of the resulting current may be used to determine the logic state stored by memory cell <NUM>. In some cases, the memory cell <NUM> may have a combination of crystalline and amorphous areas that may result in intermediate resistances, which may correspond to different logic states (i.e., states other than logic <NUM> or logic <NUM>) and may allow memory cells <NUM> to store more than two different logic states. As discussed below, the logic state of a memory cell <NUM> may be set by heating, including melting, the memory element.

Memory array <NUM> may be a 3D memory array, where two-dimensional (2D) memory arrays are formed on top of one another. This may increase the number of memory cells that may be placed or created on a single die or substrate as compared with 2D arrays, which in turn may reduce production costs or increase the performance of the memory array, or both. According to the example depicted in <FIG>, Memory array <NUM> includes three levels; however, the number of levels is not limited to three. The levels may be separated by an electrically insulating material. In some cases, the electrically insulating material may be thermally insulating as well and may contain multiple sublayers to increase the thermal resistance between each level. Each level may be aligned or positioned so that memory cells <NUM> may be approximately aligned with one another across each level, forming a memory cell stack <NUM>.

Each row of memory cells <NUM> is connected to a word line <NUM>, and each column of memory cells <NUM> is connected to a bit line <NUM>. Thus, one memory cell <NUM> may be located at the intersection of a word line <NUM> and a bit line <NUM>. This intersection may be referred to as a memory cell's address. In some cases, a bit line <NUM> may be referred to as a digit line. References to word lines and bit lines, or their analogues, are interchangeable without loss of understanding or operation. Word lines and bit lines may also be known as access lines. In some cases, word lines <NUM> and bit lines <NUM> may be substantially perpendicular to one another to create an array.

In a 3D array, each level in a row may have a word line <NUM>. In some cases, memory cell stack <NUM> may have an electrode common to the memory cells <NUM> in memory cell stack <NUM>. For example, a conductive extension may be coupled to a bit line <NUM> and commonly connected to memory cells <NUM> in memory cell stack <NUM>. The term electrode may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell <NUM>-a. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory array <NUM>.

Operations such as reading and writing may be performed on memory cells <NUM> by activating or selecting a word line <NUM> and bit line <NUM>, which may include applying a voltage or a current to the respective line. Word lines <NUM> and bit lines <NUM> may be made of conductive materials, such as metals (e.g., copper, aluminum, gold, tungsten, titanium, etc.), metal alloys, carbon, or other conductive materials, alloys, or compounds. Upon selecting a memory cell <NUM>, the resulting signal may be used to determine the stored logic state. For example, a voltage may be applied and the resulting current may be used to differentiate between the electrically resistive states of the phase change material. In some cases, reading, writing, or resetting the memory cell <NUM> may increase its temperature, which may thermally disturb, or corrupt, data stored in neighboring memory cells <NUM>. As discussed herein, forming multiple thermally insulating layers between memory cells <NUM> may thermally insulate neighboring memory cells <NUM> and minimize thermal disturb.

Accessing memory cells <NUM> may be controlled through a row decoder <NUM> and a column decoder <NUM>. For example, a row decoder <NUM> may receive a row address from the memory controller <NUM> and activate the appropriate word line <NUM> based on the received row address. Similarly, a column decoder <NUM> receives a column address from the memory controller <NUM> and activates the appropriate bit line <NUM>. Thus, by activating a word line <NUM> and a bit line <NUM>, a memory cell <NUM> may be accessed.

Upon accessing, a memory cell <NUM> may be read, or sensed, by sense component <NUM>. For example, sense component <NUM> may be configured to determine the stored logic state of memory cell <NUM> based on a signal generated by accessing memory cell <NUM>. The signal may include a voltage or electrical current, and sense component <NUM> may include voltage sense amplifiers, current sense amplifiers, or both. For example, a voltage may be applied to a memory cell <NUM> (using the corresponding word line <NUM> and bit line <NUM>) and the magnitude of the resulting current may depend on the electrical resistance of the memory cell <NUM>. Likewise, a current may be applied to a memory cell <NUM> and the magnitude of the voltage to create the current may depend on the electrical resistance of the memory cell <NUM>. In some cases, sensing may depend on a threshold voltage; that is, sensing may depend on a voltage at which point a current begins to flow. Sense component <NUM> may include various transistors or amplifiers in order to detect and amplify a signal, which may be referred to as latching. The detected logic state of memory cell <NUM> may then be output as output <NUM>. In some cases, sense component <NUM> may be a part of column decoder <NUM> or row decoder <NUM>. Or sense component <NUM> may connected to or in electronic communication with column decoder <NUM> or row decoder <NUM>.

A memory cell <NUM> may be set, or written, by similarly activating the relevant word line <NUM> and bit line <NUM>-i.e., a logic value may be stored in the memory cell <NUM>. Column decoder <NUM> or row decoder <NUM> may accept data, for example input <NUM>, to be written to the memory cells <NUM>. In the case of phase change memory, a memory cell <NUM> is written by heating the memory element, for example, by passing a current through the memory element. This process is discussed in more detail below. As with reading memory cell <NUM>, writing memory cell <NUM> may increase its temperature-e.g., the temperature of memory cell <NUM> may be increased above its melting temperature-which may corrupt data stored in neighboring memory cells <NUM>. This type of inter-cell thermal effect that tends to have a corruptive effect may be referred to as thermal disturb. As discussed herein, forming multiple thermally insulating layers between memory cells <NUM> may minimize thermal disturb of neighboring memory cells <NUM>.

In some memory architectures, accessing the memory cell <NUM> may degrade or destroy the stored logic state and re-write or refresh operations may be performed to return the original logic state to memory cell <NUM>. In DRAM, for example, the logic-storing capacitor may be partially or completely discharged during a sense operation, corrupting the stored logic state. So the logic state may be re-written after a sense operation. Additionally, activating a single word line <NUM> may result in the discharge of all memory cells in the row; thus, all memory cells <NUM> in the row may need to be re-written. But in non-volatile memory, such as PCM, accessing the memory cell <NUM> may not destroy the logic state and, thus, the memory cell <NUM> may not require re-writing after accessing.

Some memory architectures, including DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery. As discussed below, non-volatile PCM cells may have beneficial properties that may result in improved performance relative to other memory architectures. For example, PCM may offer comparable read/write speeds as DRAM but may be non-volatile and allow for increased cell density.

The memory controller <NUM> may control the operation (read, write, re-write, refresh, etc.) of memory cells <NUM> through the various components, for example, row decoder <NUM>, column decoder <NUM>, and sense component <NUM>. In some cases, one or more of the row decoder <NUM>, column decoder <NUM>, and sense component <NUM> may be co-located with the memory controller <NUM>. Memory controller <NUM> may generate row and column address signals in order to activate the desired word line <NUM> and bit line <NUM>. Memory controller <NUM> may also generate and control various voltage potentials or currents used during the operation of memory array <NUM>. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating memory array <NUM>. Furthermore, one, multiple, or all memory cells <NUM> within memory array <NUM> may be accessed simultaneously; for example, multiple or all cells of memory array <NUM> may be accessed simultaneously during a reset operation in which all memory cells <NUM>, or a group of memory cells <NUM>, are set to a single logic state.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various embodiments of the present disclosure. Memory array <NUM> may be an example of memory array <NUM> with reference to <FIG>. As depicted in <FIG>, memory array <NUM> includes multiple levels of memory cells <NUM>-a stacked in a vertical direction, relative to a substrate, to create memory cell stacks <NUM>-a, which may be examples of a memory cell <NUM> and memory cell stack <NUM>, as described with reference to <FIG>. Memory array <NUM> may thus be referred to as a 3D memory array. Memory array <NUM> also includes word lines <NUM>-a and bit lines <NUM>-a, which may be examples of a word line <NUM> and bit line <NUM>, as described with reference to <FIG>. Memory array <NUM> includes insulating layers <NUM>, vias <NUM>, substrate <NUM>, and electrode <NUM>. Electrode <NUM> may be in electronic communication with bit line <NUM>-a. Insulating layers <NUM> may be both electrically and thermally insulating. As described above, various logic states may be stored by programming the electrical resistance of memory cells <NUM>-a. In some cases, this includes passing a current through memory cell <NUM>-a, heating memory cell <NUM>-a, or melting the material of memory cell <NUM>-a wholly or partially. Insulating layers <NUM> may be composed of multiple sublayers, creating one or more interfaces between memory cells <NUM>-a that increase the thermal resistance between memory cells <NUM>-a within memory cell stack <NUM>-a.

Memory array <NUM> may include an array of memory cell stacks <NUM>-a, and each memory cell stack <NUM>-a may include multiple memory cells <NUM>-a. Memory array <NUM> may be made by forming a stack of conductive layers, such as word lines <NUM>-a, where each conductive layer is separated from an adjacent conductive layer by electrically insulating layers <NUM>. The electrically insulating layers may include oxide or nitride materials, such as silicon oxide, silicon nitride, or other electrically insulating materials. In some cases, electrically insulating layers <NUM> may be thermally insulating and may include one or more sublayers. The layers of memory array <NUM> may be formed on a substrate <NUM>, such as a silicon wafer, or any other semiconductor or oxide substrate. Vias <NUM> may be formed by removing material from the stack of layers through etching or mechanical techniques, or both. Memory elements <NUM>-a may be formed by removing material from the conductive layer to create a recess adjacent to via <NUM> and then forming the variable resistance material in the recess. For example, material may be removed from the conductive layer by etching, and material may be deposited in the resulting recess to form a memory element <NUM>. Each via <NUM> may be filled with an electrical conductor to create electrode <NUM>, which may be coupled to bit line <NUM>-a. In other words, memory cells <NUM>-a in a memory cell stack <NUM>-a may have a common electrode. Thus, each memory cell <NUM>-a may be coupled to a word line <NUM>-a and a bit line <NUM>-a.

A selection component (e.g., as shown in <FIG>) may, in some cases, be connected in series between a memory cell <NUM>-a and at least one access line, e.g., a word line <NUM>-a or a bit line <NUM>-a. The selection component may aid in selecting a particular memory cell <NUM>-a or may help prevent stray currents from flowing through non-selected memory cells <NUM>-a adjacent a selected memory cell <NUM>-a. The selection component may include an electrically non-linear component (e.g., a non-ohmic component), such as a metal-insulator-metal (MIM) junction, an ovonic threshold switch (OTS), or a metal-semiconductor-metal (MSM) switch, among other types of two-terminal select device such as a diode. In some cases, the selection component is a chalcogenide film.

Various techniques may be used to form materials or components on a substrate <NUM>. These may include, for example, chemical vapor deposition (CVD), metal-organic vapor deposition (MOCVD), physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), among other thin film growth techniques. Material may be removed using a number of techniques, which may include, for example, chemical etching (also referred to as "wet etching"), plasma etching (also referred to as "dry etching"), or chemical-mechanical planarization.

As discussed above, memory cells <NUM>-a of <FIG> may include a material with a variable resistance. Variable resistance materials may refer to various material systems, including, for example, metal oxides, chalcogenides, and the like. Chalcogenide materials are materials or alloys that include at least one of the elements sulfur (S), selenium (Se), or tellurium (Te). Many chalcogenide alloys may be possible-for example, a germanium-antimony-tellurium alloy (Ge-Sb-Te) is a chalcogenide material. Other chalcogenide alloys not expressly recited here may also be employed.

Phase change memory exploits the large resistance contrast between crystalline and amorphous states in phase change materials, which may be chalcogenide materials. A material in a crystalline state may have atoms arranged in a periodic structure, which may result in a relatively low electrical resistance. By contrast, material in an amorphous state with no or relatively little periodic atomic structure may have a relatively high electrical resistance. The difference in resistance values between amorphous and crystalline states of a material may be significant; for example, a material in an amorphous state may have a resistance one or more orders of magnitude greater than the resistance of the material in its crystalline state. In some cases, the material may be partially amorphous and partially crystalline, and the resistance may be of some value between the resistances of the material in a wholly crystalline or wholly amorphous state. So a material may be used for other than binary logic applications-i.e., the number of possible states stored in a material may be more than two.

To set a low-resistance state, a memory cell <NUM>-a may be heated by passing a current through the memory cell. Heating caused by electrical current flowing through a material that has a finite resistance may be referred to as Joule or ohmic heating. Joule heating may thus be related to the electrical resistance of electrodes or phase change material. Heating the phase change material to an elevated temperature (but below its melting temperature) may result in the phase change material crystallizing and forming the low-resistance state. In some cases, a memory cell <NUM>-a may be heated by means other than Joule heating, for example, by using a laser.

To set a high-resistance state, the phase change material may be heated above its melting temperature, for example, by Joule heating. The amorphous structure of the molten material may be quenched, or locked in, by abruptly removing the applied current to quickly cool the phase change material.

In some examples, a reset operation may include a first heating cycle that melts the phase change material followed by a second heating cycle that crystallizes the phase change material, where the second heating cycle uses a temperature less than the first heating cycle. This reset operation, which includes two heating steps, may disturb nearby memory cells.

As described herein, regions separating memory cells <NUM>-a, for example, insulating layers <NUM>, may include one or more interfaces that may increase the thermal resistance of insulating layer <NUM> by altering the temperature gradient. In some examples, the interfaces separate memory cells <NUM>-a stacked in the vertical direction. In other words, memory cells <NUM>-a may be stacked one on top of the other and separated from one another by the interfaces. Interfaces may also reduce thermal phonon transport, for example, by scattering phonons. This may reduce thermal transport and increase the thermal resistance. This, in turn, may help prevent the corruption of data stored in memory cells <NUM>-a when neighboring memory cells <NUM>-a are heated during a read or write operation. For example, the increased thermal resistance may increase the number of cycles a memory cell <NUM>-a may be written before corrupting a neighboring memory cell <NUM>-a. This is discussed in more detail below.

The one or more interfaces associated with the insulating layers may result from a change in material composition or stoichiometry. For example, two or more layers may be formed on top of one another, where neighboring layers have different chemical compositions, such as alternating layers of an oxide material (for example, SiO<NUM>) and a nitride material (for example, SiN). An interface may also be formed by a change in a material's chemical proportions or stoichiometry. For example, instead of a <NUM>-to-<NUM> atomic ratio of SiN, the atomic ratio may be varied, such as <NUM>-to-<NUM>, <NUM>-to-<NUM>, etc., for adjacent layers. In some cases, the stoichiometry may be varied by adjusting the deposition parameters during material deposition. For example, the relative concentrations of reactants may be varied during deposition, among other techniques.

In some embodiments, metal layers may be used to provide thermal insulation. Metals are generally good thermal conductors and may aid in removing heat from the area surrounding a memory cell <NUM>-a. For example, insulating layer <NUM> may include multiple sublayers, where at least one sublayer is metallic. Metal layers or sublayers may be electrically insulated from electrodes <NUM> or access lines (e.g., word line <NUM>-a or bit line <NUM>-a) by, for example, placing electrically insulating material between them.

The memory cells <NUM> discussed herein are not limited to phase change materials. Other types of memory cells may be affected similarly by thermal disturb, for example, resistive memory or resistive RAM. In some cases, resistive RAM uses metal oxide materials whose electrical resistance is varied by controlling the ionic state of atoms in the material or by controlling the number or location of atomic vacancies, i.e., missing atoms, in the material. Such materials and processes may be heat-sensitive and may thus benefit from the thermal insulation techniques described herein.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various embodiments of the present disclosure. Memory array <NUM> may be an example of memory array <NUM> or <NUM> with reference to <FIG> and <FIG>. As depicted in <FIG>, memory array <NUM> includes memory cells <NUM>-b and <NUM>-c, word lines <NUM>-b and <NUM>-c, via <NUM>-a, and electrode <NUM>-a,which may be examples of a memory cell <NUM>, word line <NUM>, via <NUM>, and electrode <NUM> as described with reference to <FIG> and <FIG>. Memory array <NUM> also includes insulating sublayers <NUM>, <NUM>-a, and <NUM>-b. A combination of a memory cell <NUM> and an adjacent electrode (e.g., word line <NUM>) may be referred to as a layer of memory array <NUM>; likewise groups of adjacent sublayers may be referred to as a layer of memory array <NUM>. Thus, memory array <NUM> may include layers <NUM>, <NUM>, and <NUM>. Layer <NUM> may consist of various sublayers, such as sublayers <NUM>, <NUM>-a, and <NUM>-b. Insulating sublayers <NUM>, <NUM>-a, and <NUM>-b may be different materials and may form interfaces that increase the thermal resistance between memory cells <NUM>-b and <NUM>-c. In some cases, electrode <NUM>-a may be a bit line <NUM> or it may be another material that is in electronic communication with a bit line <NUM>, as discussed with reference to <FIG>.

As discussed above, reading or writing memory cell <NUM>-b may be performed by heating memory cell <NUM>-b. For example, a current may be applied and may flow through word line <NUM>-b, memory cell <NUM>-b, and electrode <NUM>-a, causing one or more of word line <NUM>-b, memory cell <NUM>-b, or electrode <NUM>-a to increase in temperature due to Joule heating. In some cases, this process may heat memory cell <NUM>-b to high temperatures, including above its melting temperature in some cases. The surroundings of memory cell <NUM>-b, including memory cell <NUM>-c, may thus increase in temperature. The heating of memory cell <NUM>-c may transform and corrupt the data stored in memory cell <NUM>-c. For example, if memory cell <NUM>-c is in an amorphous state, there may be a thermodynamic driving force for it to crystallize, which may change its electrical resistance and thus change the stored logic state.

Although a thermodynamic driving force exists to transform from amorphous to crystalline, the structure may not transform without sufficient kinetic energy. This kinetic energy may be provided thermally. Thus, at low enough temperatures, the stored state may be maintained. At elevated temperatures, however, the amorphous material may crystallize. This may occur at temperatures much lower than the material's melting temperature, for example, on the order of a few hundred degrees Celsius. In general, the time spent at an elevated temperature may determine when memory cell <NUM>-c switches states. So for a given temperature, memory cell <NUM>-c may be corrupted after a certain number of read or write cycles of memory cell <NUM>-b. That is, each read or write cycle of memory cell <NUM>-b may heat memory cell <NUM>-c for some period of time, and after some number of cycles, memory cell <NUM>-c may experience an elevated temperature for a sufficient time such that it transforms and becomes corrupted.

In order to minimize thermal disturb of memory cells <NUM>, the thermal resistance between memory cell <NUM>-b and <NUM>-c may be increased by adding one more interfaces between them. That is, interfaces may be placed between memory cells <NUM> that are stacked vertically. For example, as depicted in <FIG>, a first layer <NUM>, may include a first memory cell <NUM>-b coupled to a first electrode, such as word line <NUM>-b. In some cases, a memory cell <NUM> may be referred to as a memory element <NUM>. A second layer <NUM> may include a second memory cell <NUM>-c coupled to a second electrode, such as word line <NUM>-c. A third layer <NUM> may include a stack of at least two sublayers, such as sublayers <NUM> and <NUM>-a. Although depicted with three sublayers in <FIG>, two sublayers may be used. More than three sublayers may also be used. Layer <NUM> may be positioned between layers <NUM> and <NUM>, where layers <NUM>, <NUM>, and <NUM> are each substantially parallel to one another. Additionally, a third electrode, such as electrode <NUM>-a, may be coupled to memory elements <NUM>-b and <NUM>-c, and electrode <NUM>-a may be substantially perpendicular to layers <NUM>, <NUM>, and <NUM>. In some cases, memory elements <NUM>-b and <NUM>-c may be coaxial with electrode <NUM>-a, that is, they may share the same axis of revolution. For example, electrode <NUM>-a may be cylindrical and memory elements <NUM>-b and <NUM>-c may be annular and surround electrode <NUM>-a. In other examples, the architecture of memory array <NUM> may have a configuration that does not include circular symmetric components.

In some cases, sublayers <NUM> and <NUM>-a may be electrical and thermal insulators. For example, they may be oxide materials. Sublayers <NUM> and <NUM>-a may each be materials with a different composition or stoichiometry from each other, thus resulting in an interface between them. In some cases, the thermally insulating region within layer <NUM> may include a third sublayer, such as sublayer <NUM>-b, which may be positioned between sublayers <NUM> and <NUM>-a. In some cases, sublayer <NUM>-b may be electrically and thermally insulating, such as an oxide material. In other cases, sublayer <NUM>-b may be a thermal conductor, for example, a metal, metal alloy, carbon, or a compound comprising silicon and nitrogen. In such cases, sublayers <NUM> and <NUM>-a may be electrical insulators in order to electrically insulate sublayer <NUM>-b from word lines <NUM>-b and <NUM>-c and memory elements <NUM>-b and <NUM>-c. In some cases, sublayer <NUM>-b may be electrically insulated from electrode <NUM>-a as well.

Word lines <NUM>-b and <NUM>-c and electrode <NUM>-a may each be composed of at least one of tungsten, tungsten nitride, aluminum, titanium, titanium nitride, silicon, doped polycrystalline silicon, or carbon, or any combination thereof. Memory elements <NUM>-b and <NUM>-c may be materials with a programmable resistivity. They may be chalcogenide materials or phase change materials, or both.

As depicted in <FIG>, the interfaces formed by sublayers <NUM> and <NUM>-a may be substantially parallel to the substrate or die, for example, substrate <NUM> shown in <FIG>. This orientation may have a number of benefits. For example, it may increase the thermal resistance between memory cells <NUM>-b and <NUM>-c when they are positioned in the 3D, vertical architecture shown in <FIG>. Additionally, forming sublayers <NUM> and <NUM>-a may be achieved by simple, planar thin-film deposition processes. For example, physical vapor deposition, which is a line-of-sight deposition process, may produce planar thin-films parallel to the substrate. Such deposition techniques may not be used to produce thin-films extending perpendicular to the substrate.

Memory array <NUM> may be created by forming a stack comprising a set of conductive layers, where each conductive layer of the set is separated from an adjacent conductive layer of the set by a thermally insulating region. For example, layer <NUM> may be formed by depositing a conductive material. Layer <NUM> may be formed on top of layer <NUM>, where layer <NUM> may include at least two insulating sublayers, e.g., sublayers <NUM> and <NUM>-a, which may be different electrically insulating materials. This process may be repeated to form a stack, for example, layers <NUM>, <NUM>, and <NUM> may comprise the stack, although more layers are possible.

Interfaces may be formed in layer <NUM> by varying the deposited material. For example, sublayer <NUM>-b may be a material different from that of sublayer <NUM> and <NUM>-a, thus forming interfaces between the sublayers. Sublayers <NUM>, <NUM>-a, and <NUM>-b may be one of an oxide material, a compound containing nitrogen (for example, SiN), a metal, metal alloy, or carbon. In other cases, sublayers <NUM>, <NUM>-a, and <NUM>-b are the same material but may have a different stoichiometry from one another. This may be achieved by varying the deposition parameters during formation. For example, sublayer <NUM>-a may be formed according to one set of deposition parameters and sublayer <NUM>-b may be formed according to another set of deposition parameters.

Via <NUM>-a may be formed through the stack, where at least a portion of via <NUM>-a passes through each conductive layer (for example, layers <NUM> and <NUM>) of the set of conductive layers. Via <NUM>-a may be formed by removing material from the stack, for example, by etching. In some cases, a photolithography process may be used to define the opening of via <NUM>-a and constrain subsequent etching to the defined region. A recess may be formed in at least one conductive layer (for example, layers <NUM> or <NUM>) of the set of conductive layers, and the recess may be adjacent to via <NUM>-a. A memory element <NUM>-b or <NUM>-c may be formed in the recess.

By way of example, materials or components in memory array <NUM> may be formed by depositing material using chemical vapor deposition, metal-organic chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Material may be removed by etching, such as chemical or plasma etching.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various embodiments of the present disclosure. Memory array <NUM> may be an example of memory array <NUM>, <NUM>, or <NUM> with reference to <FIG>. Memory array <NUM> includes memory cells <NUM>-d, word lines <NUM>-d, via <NUM>-b, electrode <NUM>-b, and insulating sublayers <NUM>-c, which may be examples of memory cells <NUM>, word line <NUM>, via <NUM>, and electrode <NUM> with reference to <FIG>, and insulating sublayers <NUM> with reference to <FIG>. In some cases, electrode <NUM>-b may be a bit line <NUM> or it may be an extension from a bit line <NUM> that is in electronic communication with a bit line <NUM>. Memory array <NUM> also includes buffer material <NUM> and selection component <NUM>.

As depicted in <FIG>, more than two memory cells <NUM> may be stacked on one another. For example, three memory cells <NUM>-d are shown; however, more than three memory cells <NUM> may be stacked in some examples. Furthermore, five insulating sublayers <NUM>-c are depicted in <FIG>, resulting in six interfaces between each memory element <NUM>-d.

As discussed above, selection component <NUM> may aid in selecting a particular memory cell <NUM>-d or may help prevent stray currents flowing through non-selected memory cells <NUM> adjacent a selected memory cell <NUM>. Selection component <NUM> may include an electrically non-linear component (i.e., a non-ohmic component) such as a bipolar junction, a metal-insulator-metal (MIM) junction, an ovonic threshold switch (OTS), or a metal-semiconductor-metal (MSM) switch, among other types of two-terminal select device such as a diode. Selection component <NUM> may also be a field-effect transistor. In some cases, selection component <NUM> may be a chalcogenide film. In other cases, selection component <NUM> may be a material alloy containing selenium, arsenic, and germanium.

Selection component <NUM> may be located between an electrode, such as a conductive bit line <NUM> or word line <NUM>-d, and a memory cell <NUM>-d. For example, electrode <NUM>-b may be an extension of a bit line <NUM>, and selection component <NUM> may be coupled to electrode <NUM>-b and buffer material <NUM>, separating electrode <NUM>-b and buffer material <NUM>, where buffer material <NUM> may be coupled to a memory cell <NUM>-d.

Buffer material <NUM> may enhance the chemical separation of selection component <NUM> and memory element <NUM>-d. For example, buffer material <NUM> may prevent the chemical mixing of selection component <NUM> and memory element <NUM>-d when, for instance, memory element <NUM>-d is melted. Buffer material <NUM> may be a thin oxide material that may electrically conduct by tunneling. In other cases, buffer material <NUM> may be an electrically conductive material, such as an electrode material.

Memory array <NUM> may be formed in a similar manner as discussed in <FIG>. After forming via <NUM>-b and memory elements <NUM>-d, buffer material <NUM> may be formed on the surface of via <NUM>-b, and buffer material <NUM> may be coupled to memory elements <NUM>-d. Selection component <NUM> may be formed on the surface of buffer material <NUM> in via <NUM>-b, where selection component <NUM> may be coupled to buffer material <NUM>. Electrode <NUM>-b may be formed, where electrode <NUM>-b may fill a remainder of via <NUM>-b and may be coupled to selection component <NUM>.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various aspects of the present disclosure. Memory array <NUM> may be an example of memory array <NUM>, <NUM>, <NUM>, or <NUM> with reference to <FIG>. Memory array <NUM> includes memory cells <NUM>-e, word lines <NUM>-e, via <NUM>-c, electrode <NUM>-c, insulating sublayers <NUM>-d, selection component <NUM>-a, and buffer material <NUM>-a, which may be examples of memory cells <NUM>, word line <NUM>, via <NUM>, electrode <NUM>, insulating sublayers <NUM>, selection component <NUM>, and buffer material <NUM> with reference to <FIG>. In some cases, electrode <NUM>-c may be a bit line <NUM> or it may be an extension from a bit line <NUM> that is in electronic communication with a bit line <NUM>.

Selection component <NUM>-a may be located between an electrode, such as a conductive bit line <NUM>, and a memory cell <NUM>-e. For example, electrode <NUM>-c may be an extension of a bit line <NUM>, which may be a conductive line, and selection component <NUM>-a may be coupled to electrode <NUM>-c, separating electrode <NUM>-c and a memory element <NUM>-e. In some cases, buffer material <NUM>-a separates selection component <NUM>-a and a memory element <NUM>-e. Buffer material <NUM>-a may enhance the chemical separation of selection component <NUM>-a and memory element <NUM>-e. For example, buffer material <NUM>-a may prevent the chemical mixing of selection component <NUM>-a and memory element <NUM>-e when, for instance, memory element <NUM>-e is melted. Buffer material <NUM>-a may be an oxide material that is thin enough such that it may electrically conduct by tunneling. In other cases, buffer material <NUM>-a may be an electrically conductive material.

Memory array <NUM> may be formed in a similar manner as discussed in <FIG>. After forming via <NUM>-c, a recess may be formed in word line <NUM>-e. A memory cell <NUM>-e may be formed in the recess. Buffer material <NUM>-a may be formed on memory cell <NUM>-e. In some cases, both the buffer material <NUM>-a and the memory cell <NUM>-e are within the recess. Selection component <NUM>-a may be formed on the surface of via <NUM>-c, where selection component <NUM>-a may be coupled to buffer material <NUM>-a, and buffer material <NUM>-a separates selection component <NUM>-a and memory element <NUM>-e. Electrode <NUM>-c may be formed, where electrode <NUM>-c may fill a remainder of via <NUM>-c and may be coupled to selection component <NUM>-a.

<FIG> illustrates an example memory array <NUM> that supports thermal insulation for three-dimensional memory arrays in accordance with various aspects of the present disclosure. Memory array <NUM> may be an example of memory array <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> with reference to <FIG>. Memory array <NUM> includes memory cells <NUM>-f, word lines <NUM>-f, via <NUM>-d, electrode <NUM>-d, insulating sublayers <NUM>-e, and selection component <NUM>-b which may be examples of memory cells <NUM>, word line <NUM>, via <NUM>, electrode <NUM>, insulating sublayers <NUM>, and selection component <NUM> with reference to <FIG>.

Memory array <NUM> may be formed in a similar manner as discussed in <FIG>, where electrode <NUM>-d fills an entirety of via <NUM>-d and may be coupled to memory elements <NUM>-f. Selection component <NUM>-b may be formed at one end of electrode <NUM>-d and may be coupled to electrode <NUM>-d. For example, selection component <NUM>-b may be positioned between electrode <NUM>-d and a bit line <NUM> (not shown), which may be a conductive line, such that they are coupled. In some cases, selection component <NUM>-b may be formed below the memory array, i.e., at the bottom of via <NUM>-d. In some examples, selection component <NUM>-b may be planar with the top or bottom of via <NUM>-d, that is, it may be planar with the top or bottom insulating sublayers <NUM>-e.

<FIG> shows a block diagram <NUM> of a memory array <NUM>-a that supports thermal insulation for three-dimensional memory arrays in accordance with various aspects of the present disclosure. Memory array <NUM>-a may be referred to as an electronic memory apparatus and may be an example of memory array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> described in <FIG>. Memory array <NUM>-a includes memory controller <NUM>-a and memory cell <NUM>-g, which may be examples of memory controller <NUM> described with reference to <FIG>, and a memory cell <NUM> as described with reference to <FIG>. Memory controller <NUM>-a may include biasing component <NUM> and timing component <NUM> and may operate memory array <NUM>-a as described in <FIG>. Memory controller <NUM>-a may be in electronic communication with word line <NUM>-g, bit line <NUM>-b, and sense component <NUM>-a, which may be examples of word line <NUM>, bit line <NUM>, and sense component <NUM>, described with reference to <FIG> or <FIG>. Memory array <NUM>-a may also include latch <NUM>. The components of memory array <NUM>-a may be in electronic communication with one another and may perform the functions described with reference to <FIG>. In some cases, sense component <NUM>-a and latch <NUM> may be components of memory controller <NUM>-a.

Memory controller <NUM>-a may be configured to activate word line <NUM>-g or bit line <NUM>-b by applying voltages or currents to those various nodes. For example, biasing component <NUM> may be configured to apply a voltage to operate memory cell <NUM>-g to read or write memory cell <NUM>-g as described above. The applied voltage may be based on a desired current as well as the resistance of memory cell <NUM>-g and any electrodes. In some cases, memory controller <NUM>-a may include a row decoder, column decoder, or both, as described with reference to <FIG>. This may enable memory controller <NUM>-a to access one or more memory cells <NUM>-g. Biasing component <NUM> may also provide voltages to operate sense component <NUM>-a.

In some cases, memory controller <NUM>-a may perform its operations using timing component <NUM>. For example, timing component <NUM> may control the timing of the various word line or bit line selections, including timing for switching and voltage application to perform the memory functions, such as reading and writing, discussed herein. In some cases, timing component <NUM> may control the operations of biasing component <NUM>.

Sense component <NUM>-a may include voltage or current sense amplifiers to determine the stored logic state in memory cell <NUM>-g. Upon determining the logic state, sense component <NUM>-a may then store the output in latch <NUM>, where it may be used in accordance with the operations of an electronic device using memory array <NUM>-a.

<FIG> shows a diagram of a system <NUM> that supports three-dimensional memory arrays with thermal insulation in accordance with various embodiments of the present disclosure. System <NUM> may include a device <NUM>, which may be or include a printed circuit board to connect or physically support various components. Device <NUM> may include a memory array <NUM>-b, which may be an example of memory array <NUM>, <NUM>-a, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> described in <FIG>. Memory array <NUM>-b may contain memory controller <NUM>-b and memory cell(s) <NUM>-h, which may be examples of memory controller <NUM> described with reference to <FIG> and <FIG> and memory cells <NUM> described with reference to <FIG>. Device <NUM> may also include a processor <NUM>, BIOS component <NUM>, peripheral component(s) <NUM>, and input/output controller component <NUM>. The components of device <NUM> may be in electronic communication with one another through bus <NUM>.

Processor <NUM> may be configured to operate memory array <NUM>-b through memory controller <NUM>-b. In some cases, processor <NUM> performs the functions of memory controller <NUM>-b described with reference to <FIG> and <FIG>. In other cases, memory controller <NUM>-b may be integrated into processor <NUM>. Processor <NUM> may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components, and processor <NUM> may perform various functions described herein, including reading or writing memory cells <NUM>-h separated by thermally insulating layers. Processor <NUM> may, for example, be configured to execute computer-readable instructions stored in memory array <NUM>-b to cause device <NUM> perform various functions or tasks.

BIOS component <NUM> may be a software component that includes a basic input/output system (BIOS) operated as firmware, which may initialize and run various hardware components of system <NUM>. BIOS component <NUM> may also manage data flow between processor <NUM> and the various components, e.g., peripheral components <NUM>, input/output controller component <NUM>, etc. BIOS component <NUM> may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component(s) <NUM> may be any input or output device, or an interface for such devices, that is integrated into device <NUM>. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input/output controller component <NUM> may manage data communication between processor <NUM> and peripheral component(s) <NUM>, input <NUM>, or output <NUM>. Input/output controller component <NUM> may also manage peripherals not integrated into device <NUM>. In some cases, input/output controller component <NUM> may represent a physical connection or port to the external peripheral.

Input <NUM> may represent a device or signal external to device <NUM> that provides input to device <NUM> or its components. This may include a user interface or interface with or between other devices. In some cases, input <NUM> may be a peripheral that interfaces with device <NUM> via peripheral component(s) <NUM> or may be managed by input/output controller component <NUM>.

Output <NUM> may represent a device or signal external to device <NUM> configured to receive output from device <NUM> or any of its components. Examples of output <NUM> may include data or signals sent to a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output <NUM> may be a peripheral that interfaces with device <NUM> via peripheral component(s) <NUM> or may be managed by input/output controller component <NUM>.

The components of memory controller <NUM>-b, device <NUM>, and memory array <NUM>-b may be made up of circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein.

<FIG> shows a flowchart illustrating a method <NUM> of forming a three-dimensional memory array with thermal insulation in accordance with various embodiments of the present disclosure. The formation methods may include those described with reference to <FIG>. For example, materials or components may be formed through various combinations of material deposition and removal. In some cases, material formation or removal may include one or more photolithography steps not explicitly recited or described.

At block <NUM>, the method may include forming a stack comprising a set of conductive layers, where each conductive layer of the set is separated from an adjacent conductive layer of the set by a thermally insulating region, as described with reference to <FIG>.

At block <NUM>, the method may include forming a set of insulating layers within each thermally insulating region, where the set of insulating layers comprises at least two layers that comprise electrically insulating material as described with reference to <FIG>. In some cases, the method may include forming a first electrically insulating layer that comprises a first material and forming a second electrically insulating layer positioned on top of the first electrically insulating layer, where the second electrically insulating layer comprises a second material that is different from the first material. In other cases, the method may include forming a first electrically insulating layer according to a first set of formation parameters and forming a second electrically insulating layer according to a second set of formation parameters that is different from the first set of formation parameters, where the first insulating layer and the second insulating layer comprise a same material.

In some examples, the method at block <NUM> may include forming a first electrically insulating layer that comprises a first material, forming a second layer positioned on top of the first electrically insulating layer, where the second layer comprises a second material different from the first material, and forming a third layer positioned on top of the second layer, where the first and third layer comprise a same material. In some cases, the first and third materials may be different. In some instances, the second material comprises at least one of a metal, a metal alloy, carbon, or a compound comprising silicon and nitrogen.

At block <NUM>, the method may include forming a via through the stack, where at least a portion of the via passes through each conductive layer of the set of conductive layers as described with reference to <FIG>.

At block <NUM>, the method may include forming a recess in at least one conductive layer of the set of conductive layers, where the recess is adjacent the via as described with reference to <FIG>.

At block <NUM>, the method may include forming a memory element within the recess as described with reference to <FIG>. In some cases, the memory element may be a chalcogenide material or a phase change material.

The method may also include forming a first conductive element on a surface of the via, where the first conductive element is coupled to the memory element, forming a selection component on a surface of the first conductive element in the via, where the selection component is coupled to the first conductive element, and forming a second conductive element, where the second conductive element fills a remainder of the via and is coupled to the selection component. In some examples, the conductive elements, conductive layers, or electrodes may each comprise one of tungsten, tungsten nitride, aluminum, titanium, titanium nitride, silicon, doped polycrystalline silicon, or carbon, or any combination thereof.

In another embodiment, the method may include forming a buffer material on the memory element, where both the buffer material and the memory element are within the recess, forming a selection component on a surface of the via, where the selection component is coupled to the buffer material and the buffer material separates the selection component and the memory element, and forming a conductive element, where the conductive element fills a remainder of the via and is coupled to the selection component.

In yet another embodiment, the method may include forming a conductive element in the via, where the conductive element fills an entirety of the via and is coupled to the memory element, and forming a selection component at an end of the conductive element and coupled to the conductive element. In some cases, the selection component comprises one of a diode, a bipolar junction device, an ovonic threshold selector, a field effect transistor, or a chalcogenide material.

Thus, method <NUM> may be methods of forming a 3D memory array with thermal insulation. It should be noted that method <NUM> describes possible implementations, and the operations and steps may be rearranged or otherwise modified such that other implementations are possible.

The description herein provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the invention as defined by the claims.

The terms "example," "exemplary," and "embodiment," as used herein, mean "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other examples.

When the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

As used herein, "coupled to" indicates components that are substantially in contact with one another. In some cases, two components may be coupled even if a third material or component physically separates them. This third component may not substantially alter the two components or their functions. Instead, this third component may aid or enable the connection of the first two components. For example, some materials may not strongly adhere when deposited on a substrate material. Thin (e.g., on the order of a few nanometers or less) layers, such as lamina layers, may be used between two materials to enhance their formation or connection. In other cases, a third material may act as a buffer to chemically isolate two components.

The term "layer" used herein refers to a stratum or sheet of a geometrical structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover some or all of a surface below. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration. Those skilled in the art will, however, recognize that the layers are three-dimensional in nature.

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough so as to achieve the advantages of the characteristic.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory array <NUM>.

The term "photolithography," as used herein, may refer to the process of patterning using photoresist materials and exposing such materials using electromagnetic radiation. For example, a photoresist material may be formed on a base material by spin-coating the photoresist on the base material. A pattern may be created in the photoresist by exposing the photoresist to radiation. The pattern may be defined by, for example, a photomask that spatially delineates where the radiation exposes the photoresist. Exposed photoresist areas may then be removed, for example, by chemical treatment, leaving behind the desired pattern. In some cases, the exposed regions may remain and the unexposed regions may be removed.

The term "electronic communication" refers to a relationship between components that supports electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication may be actively exchanging elections or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

The devices discussed herein, including memory array <NUM>, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. A portion or cut of a substrate contain a memory array or circuit may be referred to as a die.

Chalcogenide materials may be materials or alloys that include at least one of the elements sulfur (S), selenium (Se), and tellurium (Te). Phase change materials discussed herein may be chalcogenide materials. Chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular compound or alloy and is intended to represent all stoichiometries involving the indicated elements. For example, Ge-Te may include GexTey, where x and y may be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxide including two or more metals, e.g., transition metals, alkaline earth metals, and/or rare earth metals. Embodiments are not limited to a particular variable resistance material or materials associated with the memory elements of the memory cells. For example, other examples of variable resistance materials can be used to form memory elements and may include chalcogenide materials, colossal magnetoresistive materials, or polymer-based materials, among others.

Transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. Likewise, if the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The various illustrative blocks, components, and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

Claim 1:
A three-dimensional memory array, comprising:
a first layer (<NUM>) comprising a first memory element (<NUM>, <NUM>-a, <NUM>-b, <NUM>-d, <NUM>-e, <NUM>-f) coupled to a first electrode (<NUM>, <NUM>-a, <NUM>-b, <NUM>-d, <NUM>-e, <NUM>-f);
a second layer (<NUM>) comprising a second memory element (<NUM>, <NUM>-a, <NUM>-c, <NUM>-d, <NUM>-e, <NUM>-f) coupled to a second electrode (<NUM>, <NUM>-a, <NUM>-c, <NUM>-d, <NUM>-e, <NUM>-f);
a third layer (<NUM>, <NUM>) comprising a stack of at least two sublayers (<NUM>, <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d, <NUM>-e), the third layer (<NUM>, <NUM>) positioned between the first and second layers (<NUM>, <NUM>) and separating the first memory element (<NUM>, <NUM>-a, <NUM>-b, <NUM>-d, <NUM>-e, <NUM>-f) from the second memory element (<NUM>, <NUM>-a, <NUM>-c, <NUM>-d, <NUM>-e, <NUM>-f), wherein the first, second, and third layers (<NUM>, <NUM>, <NUM>, <NUM>) are each substantially parallel to one another; and
a third electrode (<NUM>, <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d) coupled to the first and second memory elements (<NUM>, <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d, <NUM>-e, <NUM>-f), wherein the third electrode (<NUM>, <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d) is substantially perpendicular to the first, second, and third layers (<NUM>, <NUM>, <NUM>, <NUM>).