Patent Description:
A superjunction transistor device usually includes a plurality of pn-junctions between one or more drift regions and a plurality of compensation regions, and a control structure with one or more gate electrodes. The control structure is configured to control an operating state of the transistor device.

<CIT> discloses a transistor device with a source region, a drift region, and a drain region of a first doping type, and with a body region of a second doping type complementary to the first doping type. The body region is arranged between the source region and the drift region. Furthermore, the transistor device includes a gate electrode that is arranged in a gate trench and is dielectrically insulated from the body region by a first dielectric. Furthermore, the transistor device includes a field electrode that is arranged in the gate trench and is dielectrically insulated from the body region by a second dielectric. The field electrode is either connected to the gate electrode or is connected to a source electrode of the transistor device.

<CIT> discloses a transistor arrangement with a plurality of transistors that are integrated in the same semiconductor body. Each of the transistor devices includes a control terminal and a load path, wherein the load paths of the transistor devices are connected in parallel. Some of the plurality of transistors are configured to receive a control signal that adjusts an activation state of these transistors.

There is a need for an improved superjunction transistor device.

One example relates to a transistor device. The transistor device includes a semiconductor body, a drift region in the semiconductor body, a plurality of transistor cells, a gate node and a source node. Each of the plurality of transistor cells includes a first trench electrode insulated from the semiconductor body by a first dielectric layer, a second trench electrode insulated from the semiconductor body by a second dielectric layer, a source region and a body region in a first mesa region between the first trench electrode and the second trench electrode, and a compensation region. The compensation region adjoins the body region, the first dielectric layer and the second dielectric layer, and forms a pn-junction with the drift region. From the first trench electrode and the second trench electrode at least the first trench electrode is connected to the gate node.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

<FIG> shows a vertical cross sectional view of one section of a superjunction transistor device. More specifically, <FIG> shows a vertical cross sectional view of a semiconductor body <NUM> in which active regions of the superjunction transistor device are integrated. The semiconductor body <NUM> has a first surface <NUM>, which may also be referred to as first main surface. <FIG> shows the semiconductor body <NUM> in a vertical section plane, wherein this vertical section plane is essentially perpendicular to the first surface <NUM>. The semiconductor body <NUM> may include a conventional semiconductor material, such as, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like.

Referring to <FIG>, the transistor device includes a drift region <NUM> of a first doping type (conductivity type) and a plurality of transistor cells <NUM>, wherein in <FIG> two of the transistor cells <NUM> are illustrated. Each of these transistor cells <NUM> includes two trench electrodes, a first trench electrode <NUM>, and a second trench electrode <NUM>. The first trench electrode <NUM> is arranged in a first trench and is dielectrically insulated from the semiconductor body <NUM> by a first dielectric layer <NUM>, which is briefly referred to as first dielectric in the following. The second trench electrode <NUM> is arranged in a second trench and is dielectrically insulated from the semiconductor body <NUM> by a second dielectric layer <NUM>, which is briefly referred to as second dielectric in the following. Each of the first trench and the second trench extends from the first surface <NUM> into the semiconductor body <NUM>.

The first trench electrode <NUM> and the second trench electrode <NUM> are spaced apart from each other in a first lateral direction x, wherein the first lateral direction x is essentially parallel to the first surface <NUM> of the semiconductor body <NUM>. A region of the semiconductor body <NUM> between the first trench and the second trench is referred to as first mesa region <NUM> in the following.

Each transistor cell <NUM> further includes a compensation region <NUM> of the second doping type (conductivity type), a source region <NUM> of a second doping type complementary to the first doping type, and a body region <NUM> of the second doping type. The source region <NUM> and the body region <NUM> are arranged between the first trench and the second trench, that is, each of the source region <NUM> and the body region <NUM> is arranged in the first mesa region <NUM>. The body region <NUM> is arranged between the source region <NUM> and the compensation region <NUM> and separates the source region <NUM> from the compensation region <NUM>. According to one example, the body region <NUM>, adjoins both the first dielectric <NUM> and the second dielectric <NUM>, and the source region <NUM> adjoins both the first dielectric <NUM> and the second dielectric <NUM>.

Furthermore, the compensation region <NUM> adjoins the body region <NUM>. One portion of the compensation region <NUM> is arranged in the first mesa region <NUM>, that is, between the first and second trench and adjoins the first and second trench. A further portion of the compensation region <NUM>, in a vertical direction z of the semiconductor body <NUM>, extends beyond bottoms of the first and second trenches towards a second surface <NUM> of the semiconductor body <NUM> and adjoins the at least one drift region <NUM> so that a pn junction is formed between the compensation region <NUM> and the drift region <NUM>. The "vertical direction" z of the semiconductor body <NUM> is a direction perpendicular to the first surface <NUM> of the semiconductor body <NUM>. The second surface <NUM> of the second semiconductor is opposite the first surface <NUM> and is spaced apart from the first surface <NUM> in the vertical direction z of the semiconductor body <NUM>.

Referring to <FIG>, the first and second trenches are spaced apart from the second surface <NUM> and both the drift region <NUM> and the compensation regions <NUM> extend beyond bottoms of the trenches towards the second surface <NUM>. According to one example, a vertical dimension of the compensation regions <NUM> below the trench bottoms is at least <NUM>%, at least <NUM>%, or at least <NUM>% of a vertical dimension of the drift region <NUM> below the trench bottoms.

The drift region <NUM> of the transistor device is connected to a drain node D. According to one example, the transistor device further includes a drain region <NUM> (illustrated in dashed line) of the first doping type, wherein the drain region <NUM> is either connected to the drain node D or forms the drain node D of the transistor device. A doping concentration of the drain region <NUM> is higher than a doping concentration of the drift region <NUM>. The drift region <NUM> may adjoin the drain region <NUM>. According to another example, a buffer region <NUM> of the first doping type is arranged between the drift region <NUM> and the drain region <NUM>, wherein the buffer region <NUM> has a doping concentration that is different from the doping concentration of the drift region <NUM> and lower than a doping concentration of the drain region <NUM>. According to one example, the doping concentration of the buffer region <NUM> is lower than the doping concentration of the drift region <NUM>. The buffer region <NUM> can be spaced apart from the compensation regions <NUM> (as illustrated), so that a section of the drift region <NUM> is arranged between the compensation regions <NUM> and the buffer region <NUM>, or the buffer region <NUM> may adjoin the compensation regions <NUM> (not illustrated). In the first example, the drift region <NUM> is a continuous semiconductor region that adjoins each of the plurality of compensation regions <NUM>. In the second example, the drift region <NUM> includes a plurality of drift region sections, wherein each of these drift region sections may be arranged between two compensation regions <NUM>.

From the first trench electrode <NUM> and the second trench electrode <NUM> of each transistor cell <NUM> at least the first trench electrode <NUM> is connected to the gate node G. The source regions <NUM> and the body regions <NUM> of the transistor cells are connected to the source node S. The second trench electrode <NUM> is connected to the gate node G, is connected to the source node S, or is floating. This is explained in detail herein further below.

The transistor device can be implemented as an n-type transistor device or as a p-type transistor device. In an n-type transistor device, the drift region <NUM>, the source regions <NUM>, the optional drain region <NUM> and the optional buffer region <NUM> are n-type (n-doped) regions and the compensation regions <NUM> and the body regions <NUM> are p-type (p-doped) regions. In a p-type transistor device, the doping types of the individual active device regions <NUM>-<NUM> are complementary to the doping types in an n-type transistor device.

According to one example, the semiconductor body <NUM> includes monocrystalline silicon and the individual active device regions are implemented such that a respective doping concentration is in a range as outlined in the following:.

The superjunction transistor device, which may also be referred to as superjunction MOSFET, can be operated in the same way as a conventional superjunction transistor device. The transistor device conducts a current between the drain node D and the source node S when a voltage (drain-source voltage) is applied between a drain node D and the source node S that forward biases the pn junction between the compensation regions <NUM> of the transistor cells <NUM> and the drift region <NUM>. In an n-type transistor device, the pn junction between the compensation regions <NUM> and the drift region <NUM> is forward biases when a positive voltage is applied to the source node S in relation to the drain node D. In this case, a current flows from the source node S via the body region <NUM> and the compensation region <NUM> of each transistor cell <NUM>, and the drift region <NUM> to the drain node D. An operating state of the transistor device in which the pn junctions between the compensation regions <NUM> and the drift region <NUM> are forward biased so that a current flows between the source node S and the drain node D is referred to as reverse biased state or reverse conducting state in the following.

When a voltage is applied between the drain node D and the source node S that reverse biases the pn junctions between the drift region <NUM> and the compensation regions <NUM> the transistor device can be switched on or switched off by applying a suitable voltage (gate-source voltage) between the gate node G and the source node S. The transistor device is in the on-state, when the gate-source voltage is such that a conducting channel is generated by field-effect in the body region <NUM> and the compensation region <NUM> along the first dielectric <NUM>, so that a current can flow between the source region <NUM> and the drift region <NUM> via this conducting channel along the first dielectric <NUM>.

The transistor device is in the off-state, when the conducting channel in the body region <NUM> and the compensation region <NUM> along the first dielectric <NUM> is interrupted. In the off-state, when a voltage level of the voltage (drain-source voltage) between the drain node D and the source node S increases, depletion regions (space charge regions) expand in the drift region <NUM> and the compensation regions <NUM>, wherein these depletion regions further expand as the drain-source voltage increases. According to one example, doping concentrations of the drift region <NUM> and the compensation regions <NUM> are such that these regions <NUM>, <NUM> can completely be depleted of charge carriers.

Unlike a conventional superjunction transistor device, the compensation region <NUM> adjoins the first and second dielectric <NUM>, <NUM> below the body region <NUM>, so that in the on-state of the transistor device there is a conducting channel along the first dielectric <NUM> not only in the body region <NUM> but also the compensation region <NUM>. Implementing the compensation region <NUM> such that it adjoins first and second dielectric <NUM>, <NUM> may help to improve the short-circuit robustness of the transistor device and offers further degrees of freedom with regard to the design of the overall transistor device.

Referring to <FIG>, the transistor cells <NUM> are spaced apart from each other in the first lateral direction x, so that a second mesa region <NUM> is arranged between two neighboring transistor cells <NUM>. The second mesa region <NUM> is arranged between one of the first and second trenches of one of the two neighboring transistor cells <NUM> and one of the first and second trenches of the other one of the neighboring transistor cells <NUM>.

The second mesa regions <NUM> may be implemented in various ways, wherein some examples are explained in the following. It should be noted that the transistor device can be implemented with only one type of second mesa region <NUM>. According to another example, one or more different types of second mesa regions <NUM> are combined in one transistor device.

According to one example, illustrated in <FIG>, one or more of the second mesa regions <NUM> include a section of the drift region <NUM> that extends to the first surface <NUM>. In this example, the first dielectric <NUM> is adjacent the drift region section arranged in the second mesa region <NUM> and is dielectrically insulated from the drift region <NUM> by the first dielectric <NUM>. A transistor device of this type has a relatively high gate-drain-capacitance, which is a capacitance between the gate node G and the drain node D. The gate-drain capacitance influences a switching behavior of the transistor device. The gate-drain-capacitance, for example, has an effect on how fast the transistor device switches on or off when a voltage level of the gate-source voltage changes, wherein the switching speed decreases as the gate-drain-capacitance increases. Such decrease of the switching speed is desirable in various applications.

The first trench electrodes <NUM> are gate electrodes of the transistor device, and the first dielectrics <NUM> are gate dielectrics. Referring to the above, the second trench electrodes <NUM> are connected to the gate node G, are connected to the source node S or are floating. The latter includes that the second trench electrodes are not connected to any terminal having a defined electric potential. A second trench electrode <NUM> connected to the gate node G operates in the same way as the first trench electrode <NUM> and forms a further gate electrode, so that, in the on-state of the transistor device a conducting channel is generated in the body region <NUM> and the compensation region <NUM> along the second dielectric <NUM>. Further, in this case, the second dielectric <NUM> forms a further gate dielectric.

When the second trench electrode <NUM> is connected to the source node S or is floating and when the transistor device is in the on-state, no such channel is generated in the body region <NUM> and the compensation region <NUM> along the second dielectric <NUM>. In this case, the source region <NUM> may be implemented such that it is spaced apart from the second dielectric <NUM>. That is, the source region <NUM> may be implemented such that it adjoins the first dielectric <NUM> (the gate dielectric) but, in the first lateral direction x, does not extend to the second dielectric <NUM>.

In the following, a transistor cell <NUM> in which both the first trench electrode <NUM> and the second trench electrode <NUM> are connected to the gate node G is referred to as first type transistor cell 10a, and a transistor cell <NUM> in which the first trench electrode <NUM> is connected to the gate node G and the second trench electrode <NUM> is either connected to the source node S or is floating is referred to as second type transistor cell 10b.

According to one example, the transistor cells <NUM> are elongated transistor cells. A horizontal cross sectional view of a transistor device of the type shown in <FIG> that includes elongated transistor cells <NUM> is shown in <FIG> shows a horizontal cross sectional view of the semiconductor body <NUM> in a horizontal section plane A-A that cuts through the first and second trench electrodes <NUM>, <NUM> and the first and second mesa regions <NUM>, <NUM>. The elongated transistor cells <NUM> of the type shown in <FIG> may also be referred to as stripe cells. In these transistor cells, the first and second trench electrodes <NUM>, <NUM> are elongated in a second lateral direction y of the semiconductor body <NUM>, wherein the second lateral direction y is essentially perpendicular to the first lateral direction x, in which the first and second trench electrodes <NUM>, <NUM> are spaced apart from each other. According to one example, "elongated" means that a dimension of the first and second trench electrodes <NUM>, <NUM> in the second lateral direction y is significantly greater than a dimension of the first and second trench electrodes <NUM>, <NUM> in the first lateral direction x. The dimension of the first and second trench electrodes <NUM>, <NUM> in the first lateral direction x may also be referred to as width, and the dimension in the second lateral direction y may also be referred to as length. According to one example, the length is at least <NUM> times, at <NUM> times, or at least <NUM> times the width. According to one example, a width of the first and second trenches is between <NUM> nanometers (nm) and <NUM> micrometers (µm), for example. Each of the first mesa regions <NUM> and the second mesa regions <NUM> has a width, which is a dimension of the respective mesa region <NUM>, <NUM> in the first lateral direction x. The width of the first mesa region <NUM> is the (shortest) distance between the first trench with the first trench electrode <NUM> and the second trench with the second trench electrode <NUM> of one transistor cell <NUM>. The width of the second mesa region <NUM> is the (shortest) distance in the first lateral direction x between the two trenches of neighboring transistor cells that adjoin the mesa region <NUM>. According to one example, the first mesa regions <NUM> essentially have the same width. Furthermore, the second mesa regions <NUM> may have the same width. According to one example, the widths of the first mesa regions <NUM> and the widths of the second mesa regions <NUM> are essentially the same. According to another example, the widths of the first mesa regions <NUM> and the widths of the second mesa regions <NUM> are different. According to one example, the widths of the first and second mesa regions are between <NUM> nanometers (nm) and <NUM> micrometers (µm), in particular between <NUM> and <NUM>.

<FIG> illustrates one example of a first transistor cell 10a, that is, a transistor cell in which both the first trench electrode <NUM> and the second trench electrode <NUM> are connected to the gate node.

<FIG> illustrates one example of a section of the transistor device in which two second type transistor cells 10b are arranged. In this example, the second type transistor cells 10b are orientated such that the first trench of one of the two transistor cells 10b and the second trench of the other one of the two transistor cells 10b adjoin the mesa region <NUM> arranged between the two transistor cells 10b.

According to another example illustrated in <FIG>, the second type transistor cells 10b are orientated such that, form the two second type transistor cells 10b, the second trenches <NUM> adjoin the second mesa region <NUM> arranged between the two transistor cells 10b.

According to another example illustrated in <FIG>, the second type transistor cells 10b are orientated such that the first trenches adjoin the mesa region <NUM> arranged between the two transistor cells 10b.

It should be noted that the topology of the first type transistor cells 10a and the second type transistor cells 10b inside the semiconductor body <NUM> is identical. Whether a transistor cell <NUM> is a first type transistor cell 10a or a second type transistor cell 10b is only dependent on where the second trench electrode <NUM> is connected to. In the first type transistor cell 10a, the second trench electrode <NUM> is connected to the gate node G, so that both the first trench electrode <NUM> and the second trench electrode <NUM> are connected to the gate node G. In the second type transistor cells 10b, the second trench electrode <NUM> is connected to the source node S and the first trench electrode <NUM> is connected to the gate node G. Referring to the above, by suitably selecting the number of first type transistor cells 10a and the second type transistor cells 10b, the gate-drain capacitance of the transistor device can be adjusted. By implementing the first type transistor cells 10a and the second type transistor cells 10b, such that they have the same topology inside the semiconductor body <NUM>, the semiconductor bodies of various kinds of transistor devices can be manufactured in the same way, wherein the properties of the transistor device, such as the gate-drain capacitance, can be adjusted by suitably wiring the first and second trench electrodes <NUM>, <NUM> using at least one metallization layer (that is, one or more metallization layers) formed on top of the first surface <NUM>. Examples for wiring the first and second trench electrodes <NUM>, <NUM> are explained herein further below.

According to one example, the transistor device, in addition to at least one of the first type transistor cells 10a and the second type transistor cells 10b, may include at least one third type transistor cell 10c. One example of a third type transistor cell 10c is illustrated in <FIG>. In this third type transistor cell 10c, both, the first trench electrode <NUM> and the second trench electrode <NUM> are connected to the source node S or are floating. It is also possible that one of the first trench electrode <NUM> and the second trench electrode <NUM> is connected to the source node S and the other one of the first trench electrode <NUM> and the second trench electrode <NUM> is floating.

Thus, in the on-state of the transistor device, there is no conducting channel along the first and second dielectrics <NUM>, <NUM> of the first type transistor cell 10c. The source region <NUM> is optional in this type of transistor cell, because the source region <NUM> does not have a technical effect in this type of transistor cell. However, the third type transistor cell 10c may include a source region <NUM> (because whether or not the transistor cell is a third type transistor cell is only dependent on which of the gate node G and the source node S, the first and second trench electrodes <NUM>, <NUM> are connected to). In addition to one or more third type transistor cells 10c, the transistor device may include (i) only first type transistor cells, (ii) only second type transistor cells, or (iii) both first type transistor cells and second transistor cells.

<FIG> shows one example of the transistor device in greater detail. In this example, the transistor device includes a source metallization <NUM>. The source metallization <NUM> is formed on top of an insulation layer <NUM>, wherein the insulation layer <NUM> is formed on top of the first surface <NUM> of the semiconductor body <NUM>. The source metallization <NUM> is connected to the source node S or forms the source node S of the transistor device.

Referring to <FIG>, electrically conducting vias <NUM> extend from the metallization layer <NUM> through the insulation layer <NUM> to the semiconductor body <NUM> or into the semiconductor body <NUM> and are electrically connected to the source regions <NUM> and the body regions <NUM> of the individual transistor cells <NUM>. "Electrically connected" in this case may include that the electrically conducting vias <NUM> are ohmically connected to the source regions <NUM> and the body regions <NUM>. While a doping concentration of the source regions <NUM> may be high enough to form an ohmic contact between the source regions <NUM> and the conducting vias <NUM>, a doping concentration of the body regions <NUM> may be too low to form such ohmic contacts. In this case, the body regions <NUM> may include contact regions <NUM> of the second doping type, wherein these contact regions <NUM> adjoin the electrically conducting vias <NUM> and have a doping concentration that is high enough to form ohmic contacts between the body regions <NUM> and the electrically conducting vias <NUM>.

The electrically conducting vias <NUM> may be elongated in the second lateral direction y. According to another example, the source region <NUM> and the body region <NUM> of one transistor cell <NUM> may be connected to the source metallization <NUM> by two or more contact vias that are spaced apart from each other in the second lateral direction y.

<FIG> shows a top view of one example of a transistor device of the type shown in <FIG> shows a top view of the overall transistor device, wherein the position of the first trench electrodes <NUM> in the semiconductor body <NUM> are illustrated in dotted lines. In this example, the first trench electrodes <NUM> are elongated trench electrodes, wherein at least one lateral end of these trench electrodes <NUM> extends beyond the source metallization <NUM>. In a region of this at least one lateral end, each first trench electrodes <NUM> is electrically connected to a gate runner <NUM>. The gate runner <NUM> is spaced apart from the source metallization <NUM> and is electrically connected to a gate pad <NUM>. The gate pad <NUM> forms the gate node G of the transistor device or is connected to the gate node G.

The first trench electrodes <NUM>, in the vertical direction z, are arranged below the gate runner <NUM> and are electrically connected to the gate runner <NUM> by electrically conducting vias. The position of these vias is schematically illustrated by black dots in the example shown in <FIG>.

Referring to the above, at least one lateral end of each first trench electrode <NUM> may extend beyond the source metallization <NUM>. That is, one lateral end may extend beyond the source metallization <NUM> and be connected to the gate runner. Alternatively, as illustrated in <FIG>, the first trench electrodes <NUM> may extend beyond the source metallization <NUM> on opposite ends, so that each first trench electrode <NUM> has a first end and an opposite second end connected to the gate runner <NUM>. In <FIG>, the second trench electrodes <NUM> are not illustrated. Second trench electrodes <NUM> that are connected to the gate node G may be connected to the gate runner <NUM> in the same way as the first trench electrodes <NUM> illustrated in <FIG>. Connecting the second trench electrodes <NUM> to the source metallization <NUM> in second type transistor cells 10b or third type transistor cells can be achieved in the same way as connecting the source and body regions <NUM>, <NUM> to the source metallization <NUM>.

<FIG> shows one example of a second type transistor cell 10b in greater detail. In this example, the second trench electrode <NUM> is connected to the source metallization <NUM> through a further electrically conducting via <NUM>. This further electrically conducting via <NUM> extends from the source metallization <NUM> through the insulation layer <NUM> to the second trench electrode <NUM>.

<FIG> shows a modification of the transistor device shown in <FIG>. In the transistor device shown in <FIG>, a doped region <NUM> of the second doping type is arranged in at least one of the second mesa regions <NUM>. According to one example, each of the second mesa regions <NUM> includes a doped region <NUM> of the second doping type. According to another example, less than each of the second mesa regions <NUM> includes a doped region <NUM> of the second doping type, wherein the remainder of the second mesa regions <NUM> may be implemented as explained with reference to <FIG>. According to one another example (not illustrated), one second mesa region <NUM> includes several doped regions <NUM> of the second doping type, wherein these several doped regions <NUM> of the second doping type are spaced apart from each other in the second lateral direction y, wherein a respective section of the drift region <NUM> is arranged between two neighboring doped regions <NUM> of the second doping type.

According to one example, a vertical dimension (depths) of the at least one doped region <NUM> of the second doping type essentially equals the vertical dimension (depths) of the body regions <NUM>. The "vertical dimension" is the dimension in the vertical direction z. According to one example, a doping concentration of the doped region <NUM> of the second doping type essentially equals the doping concentration of the body regions <NUM>.

According to one example, the doped region <NUM> of the second doping type is electrically connected to the source node S. An electrical connection between the doped region <NUM> and the source node S is schematically illustrated in dashed lines in <FIG>. In this example, the doped region <NUM> of the second doping type, which may also be referred to as diode region, and the drift region <NUM> form a diode between the source node S and the drain node D. For ohmically connecting the diode region <NUM> to the source node S, the transistor device may include a contact region <NUM> of the second doping type. The contact region <NUM> adjoins the doped region <NUM>, is connected to the source node S and has a doping concentration that is high enough in order to achieve an ohmic contact between the contact region <NUM> and the source node S. The diode region <NUM> and the optional contact region <NUM> may be connected to the source node S in the same way as the body regions <NUM>. That is, in a transistor device that includes a source metallization of the type shown in <FIG>, the diode region <NUM> may be connected to the source metallization through an electrically conducting via. The at least one diode region <NUM> adjoins the drift region <NUM>, so that a pn junction is formed between the diode region <NUM> and the drift region <NUM>. Thus, a diode is formed between the source node S and the drain node D by the diode region <NUM> and the drift region <NUM>.

According to another example the doped region <NUM> of the second doping type is floating. That is, this region is not electrically connected to the source node S. The contact region <NUM> may be omitted in this case.

<FIG> shows a modification of the transistor device shown in <FIG>. In the transistor device shown in <FIG>, a Schottky metal <NUM> is formed on top of the second mesa regions <NUM> (as illustrated) or in the second mesa regions <NUM> (not illustrated), wherein the Schottky metal <NUM> is electrically connected to the source node S. A Schottky contact is formed between the Schottky metal layer <NUM> and the drift region <NUM> in the second mesa regions <NUM>, so that a Schottky diode is formed between the drain node D and the source node S of the transistor device. This Schottky diode may have a lower forward voltage than a body diode formed by the body regions <NUM>, the compensation regions <NUM> and the drift region <NUM>. Thus, when the transistor device is in the reverse biased state, the Schottky diode <NUM> may conduct a reverse current and keep the drain-source voltage on a voltage level that is too low for the body diode to conduct. In this way, the generation of a charge carrier plasma that includes first type charge carriers (electrons or holes) and second type charge carriers (holes or electrons) may be prevented. This may be useful with regard to reducing switching losses of the transistor device.

<FIG> shows a further modification of the transistor device shown in <FIG>. In the transistor device shown in <FIG>, the drift region <NUM> in the second mesa regions <NUM> is electrically connected to a further circuit node Q of the transistor device. This further circuit node Q is also referred to as bias node in the following. The drift region <NUM> may be connected to the bias node Q via a contact region <NUM> of the first doping type, wherein a doping concentration of this contact region <NUM> is high enough to provide an ohmic contact between the drift region <NUM> and the bias node Q.

The transistor device shown in <FIG> includes four terminals or circuit nodes, the gate node G, the drain node D, the source node S, and the bias node Q. A circuit symbol of this transistor device is shown in <FIG>. This circuit symbol is based on the circuit symbol of a MOSFET and additionally includes the bias node Q. Just for the purpose of illustration, with regard to the circuit symbol shown in <FIG>, it is assumed that the transistor device is an n-type transistor device.

Referring to the above, in the reverse operating state of the transistor device, the body diode may become forward biased so that, in the reverse direction of the transistor device, a current flows between the source node S and the drain node D. Forward biasing the body diode includes generating a charge carrier plasma with first and second type charge carriers in the drift region <NUM> and the compensation regions <NUM>. When the transistor device switches from the reversed biased state to the off-state (the operating state in which the transistor device is forward biased and the conducting channels are interrupted), this charge carrier plasma is removed from the semiconductor body <NUM> and an internal output capacitance of the transistor device is charged. Removing the charge carrier plasma and charging the output capacitance is associated with a current, which may also be referred to as discharging current. This discharging current is associated with losses. Basically, the higher the voltage across a current path in which the discharging current flows, the higher the losses associated with removing the charge carrier plasma from the device. If, for example, the transistor device forms one of two electronic switches in a half-bridge, the discharging current may flow via a current path across which a supply voltage of the half-bridge is available. This supply voltage may be in the range of several hundred volts, such as <NUM> V, in power converter applications, so that losses associated with removing the charge carrier plasma may be significant.

The bias node Q can be used to provide a discharging current path that offers lower switching losses. Referring to <FIG>, a series circuit with a bias voltage source that provides a bias voltage VDEP and a switch SWDEP may be connected between the bias node Q and the source node S. When the switch SWDEP is closed, the bias voltage VDEP reverse biases the pn junctions between the drift region <NUM> and the compensation region <NUM> and the switch SWDEP and the bias voltage source form a current path for removing the charge carrier plasma (and a large share of the output charges associated with charging the output capacitance). The bias voltage VDEP is between <NUM> V and <NUM> V, for example, and, according to one example, is significantly lower than a voltage blocking capability of the transistor device.

<FIG> shows a vertical cross sectional view of a superjunction transistor device according to another example. In this example, the source regions <NUM> and the body regions <NUM> are arranged in the second mesa regions <NUM>. The compensation regions <NUM> are either directly connected to the source node S or are connected to the source node S via connection regions <NUM> of the second doping type. A doping concentration and a depth (in the vertical direction) of these connection regions <NUM> may correspond to a depth and a doping concentration of the body regions <NUM>. The connection regions <NUM> or the compensation region <NUM> are ohmically connected to the source node S. In this example, each of the transistor cells <NUM> includes a section of the second mesa region <NUM>.

<FIG> shows a modification of the transistor device shown in <FIG>. This transistor device is a combination of the transistor device shown in <FIG> and the transistor device shown in <FIG> and includes the source regions <NUM> and the body regions <NUM> in both the first mesa regions <NUM> and the second mesa regions <NUM>. Thus, transistor cells are formed in both the first and second mesa regions <NUM>, <NUM>, wherein the transistor cells in the second mesa regions <NUM> have a shorter channel length than the transistor cells in the first mesa regions. The channel length of a transistor cell in the second mesa regions <NUM> is essentially given by a shortest distance between the source regions <NUM> and the drift region <NUM> along the gate dielectric <NUM>. The channel length of a transistor cell in the first mesa regions <NUM> is essentially given by a length of a path along the gate dielectric <NUM> from the source region <NUM> through the body region <NUM> and the compensation region <NUM> to the drift region <NUM>.

<FIG> shows a modification of the transistor device shown in <FIG>. The transistor device shown in <FIG> is a depletion transistor. That is, the drift region <NUM>, in the second mesa regions <NUM>, adjoins the source region <NUM> and source regions in the first mesa regions <NUM> are omitted. Optionally, a doped region <NUM> of the first doping type that has a doping concentration that is different from the doping concentration of the drift region <NUM> is arranged in the second mesa regions <NUM> between the drift region <NUM> and the source region <NUM>. By suitably selecting the doping concentration of this doped region <NUM>, the pinch-off voltage of the transistor device can be adjusted.

<FIG> shows a modification of the transistor device shown in <FIG>. The transistor device shown in <FIG> includes both depletion transistor cells of the type illustrated in <FIG> and transistor cells of the type illustrated in <FIG>. The source region <NUM> in the second mesa <NUM> may also be electrically connected to a further circuit node Q.

In each of the first type transistor cells 10a and the second type transistor cells 10b, the conducting channel, in the on-state of the transistor device, is formed along the gate dielectric in the body region <NUM> and the compensation region <NUM>. Referring to the above, the "gate dielectric" is the first dielectric <NUM> and, when the second trench electrode <NUM> is connected to the gate node G, also the second dielectric <NUM>. As illustrated in <FIG>, <FIG>, and <FIG> - 4D, for example, the compensation region <NUM> may adjoin sidewalls and bottoms of the trenches with the first and second trench electrodes <NUM>, <NUM>. Thus, the conducting channel, in the compensation region <NUM>, is formed along a corner of the gate dielectric formed between a sidewall and a bottom of the respective trench.

One example of such corner of the gate dielectric in a region that adjoins the compensation region <NUM> is illustrated in <FIG>. Just for the purpose of illustration, the gate dielectric is a first dielectric <NUM> in this example. According to one example, in order to prevent a voltage breakdown at the corner and in order to prevent that the conducting channel has a locally increased resistance in the region of the corner, the gate dielectric <NUM> has a rounded corner <NUM>'. According to one example, an inner radius r22 of the gate dielectric <NUM> in the corner region <NUM>' is at least <NUM>% of a thickness d22 of the gate dielectric <NUM>, r22 > <NUM>*d22. The "inner radius" is the radius of the gate dielectric <NUM> in a region where the gate dielectric <NUM> adjoins the gate electrode (first trench electrode) <NUM>.

Claim 1:
A transistor device, comprising:
a semiconductor body (<NUM>);
a drift region (<NUM>) in the semiconductor body (<NUM>);
a plurality of transistor cells (<NUM>); and
a gate node (G) and a source node (S);
wherein each of the plurality of transistor cells (<NUM>) comprises:
a first trench electrode (<NUM>) insulated from the semiconductor body (<NUM>) by a first dielectric layer (<NUM>);
a second trench electrode (<NUM>) insulated from the semiconductor body (<NUM>) by a second dielectric layer (<NUM>);
a source region (<NUM>) and a body region (<NUM>) in a first mesa region (<NUM>) between the first trench electrode (<NUM>) and the second trench electrode (<NUM>); and
a compensation region (<NUM>),
wherein the compensation region (<NUM>) adjoins the body region (<NUM>), the first dielectric layer (<NUM>), and the second dielectric layer (<NUM>),
wherein the drift region (<NUM>) is a region of a first doping type and the compensation region (<NUM>) is a region of a second doping type complementary to the first doping type and forms a pn-junction with the drift region (<NUM>), and
wherein from the first trench electrode (<NUM>) and the second trench electrode (<NUM>) at least the first trench electrode (<NUM>) is connected to the gate node (G).