Patent Description:
In certain electronic environments, data must be transferred between two different clock domains, which will be referred to herein as a destination clock domain and a source clock domain. Each clock domain corresponds to a collection of components or circuits that are driven by the same clock signal, or by a group of clock signals that are related to each other (e.g., a group of clock signals derived from the same source or root clock signal). Clock domain crossings where data signals must be transferred between a source clock domain and destination clock domain may present metastability, data loss, and data coherency issues.

Clock domain crossing circuitry for synchronizing data signals between the source and destination clock domains may include double buffers in the source clock domain to increase the bandwidth of the interface provided by the clock domain crossing circuitry. In this situation, the destination clock domain must be able to determine the proper one of the double buffers to transfer data to or from to ensure data coherency and to ensure data transfer requests from the source clock domain are not missed in the destination clock domain. While conventional clock domain crossing circuitry includes synchronization circuitry for synchronizing data transfer requests (i.e., read and write requests) generated in the source clock domain and associated with one of the double buffers, these conventional synchronization circuits may not properly order (i.e., preserve the order of) the data transfer requests in the destination clock domain.

US Patent Application <IMG> <CIT>describes a method of controlling a ping-pong buffer and a system clock synchronization circuitry comprised of two flip-flops.

This may result in the wrong one of the double buffers being utilized (i.e., data incoherency) or the loss entirely of a data transfer request from the source clock domain (data loss). Improved clock domain crossing circuits and methods are accordingly needed for such electronic environments.

In accordance with one embodiment of the present disclosure, a method includes generating a destination domain current buffer signal in a destination clock domain, the destination domain current buffer signal having a value indicating which one of a first data buffer and a second data buffer in a source clock domain is a current buffer to be utilized during a current data transfer cycle. The method includes synchronizing the destination domain current buffer signal in the source clock domain to generate a synchronized destination domain current buffer signal and generating a source domain current buffer signal based on the synchronized destination domain current buffer signal. The generated source domain current buffer signal has a value indicating the current buffer. The method further includes generating a source data transfer request signal in the source clock domain based on the source domain current buffer signal, where the source data transfer request signal is associated with the current buffer indicated by the source domain current buffer signal. The source data transfer request signal is synchronized in the destination clock domain to thereby generate a destination domain data transfer request signal and the method includes delaying the transfer of data between a FIFO memory in the destination clock domain to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

In accordance with another embodiment of the present disclosure, a clock domain crossing synchronization circuit includes a destination current buffer generator in a destination clock domain. The destination current buffer generator is configured to generate a destination domain current buffer signal having a value indicating whether a first data buffer or a second data buffer is a current buffer to be utilized in a current data transfer cycle. A first synchronization circuit is configured to receive the destination current buffer signal and to generate a corresponding synchronized destination current buffer signal in a source clock domain. A source current buffer generator configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, where the source domain current buffer signal has a value indicating the current buffer. A source data transfer request generator is configured to receive the source domain current buffer signal and to generate a source data transfer request signal in the source clock domain based on the source domain current buffer signal. The generated source data transfer request signal associated with the current buffer indicated by the source domain current buffer signal. A second synchronization circuit configured to receive the source data transfer request signal and to generate a corresponding synchronized destination domain data transfer request signal in the destination clock domain. A destination data transfer request and delay generator in the destination clock domain and configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal. The destination data transfer request and delay generator is configured to delay the transfer of data between a memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

In accordance with a further embodiment of the present disclosure, an electronic system includes the clock domain crossing synchronization circuit, a first in, first out (FIFO) memory forming the memory in the destination clock domain, and a double buffer including the first data buffer and the second data buffer in the source clock domain. The source clock domain may be a secure digital (SD) clock domain and the destination clock domain an advanced hardware (AHB) bus clock domain.

In the following description one or more specific details are illustrated, aimed at providing an understanding of examples of embodiments.

The references used herein are provided merely for convenience and hence do not define the scope of protection or the scope of the embodiments.

Electronic systems can be implemented as a System on a Chip (SoC) that is an integrated circuit including all of required components of a system, often including, for example, components associated with different and asynchronous clock domains. A clock domain crossing occurs when data is transferred across clock domains, such as from a flip-flop (a source flip-flop) driven by a source domain clock to a flip-flop (a destination flip-flop) driven by a destination domain clock. Depending on the relationship between the clocks, problems may arise in the data transfer between the source flip-flop and the destination flip-flop. As an example, if a transition at output of the source flip-flop occurs very close to the active edge of the second clock, a setup or hold violation at the destination flip-flop may occur. This may lead to the output of the second flip-flop to oscillate, become unstable, and may not settle down to a stable value before the next active edge of the second clock. This condition is referred to as metastability, and is potential issue at a clock domain crossing, along with data incoherency and data loss issues that also may arise at a clock domain crossing.

<FIG> is a functional block diagram illustrating an example environment <NUM> of an electronic system <NUM> in which clock domain crossing synchronization circuits according to embodiments of the present disclosure may be implemented. The specific example environment <NUM> of the electronic system <NUM> in <FIG> is the secure digital (SD) environment where a source clock domain SCD is an SD clock domain and a destination clock domain DCD is an advanced hardware bus (AHB) clock domain. Secure digital (SD) is a proprietary format for various types of memory cards utilized in mobile devices, and SD input/output (SDIO) cards are an extension of this standard and include IO functionality in addition to memory storage, as well as a built-in controller that allows them to communicate with a host device HST and provide expanded functionality beyond mere memory storage.

In the SDIO environment <NUM>, the electronic system <NUM> may be part of an intellectual property (IP) core <NUM> of an SDIO slave in an SDIO card <NUM>, where the SDIO card may include multiple SDIO slaves and where the IP core is a functional block of reusable electronic circuitry. The IP core <NUM> of each SDIO slave, which may be referred to as an SDIO slave IP core <NUM>, includes additional electronic circuitry <NUM> along with the electronic system <NUM>. This additional electronic circuitry <NUM>, including the electronic system <NUM>, may be formed through suitable hardware, firmware, or software, and combinations thereof. The additional electronic circuitry <NUM> contained in each SDIO slave IP core <NUM> processes requests, such as data transfer requests like read and write requests, received from the host device HST. More specifically, an SDIO master controller <NUM> in the hose device HST supplies requests, such as data transfer requests like read and write requests, over an SDIO bus <NUM> to the SDIO slave IP core <NUM> in the SDIO card <NUM>. The additional electronic circuitry <NUM> in the SDIO slave IP core <NUM> processes the data transfer request from the host device HST and generates signals that are supplied to control operation of the electronic system <NUM> in handling the transfer of data component of the request. The signals generated by the SDIO slave IP core <NUM> include a start new data transfer request signal SNDT and a data transfer current buffer signal DTCB, which will be described in more detail with reference to the embodiments of <FIG>.

<FIG> is a more detailed functional block diagram of the electronic system <NUM> of <FIG> according to one embodiment of the present disclosure. The electronic system <NUM> has a source clock domain SCD and a destination clock domain DCD, with a vertical dashed line <NUM> representing the border or crossing between these two clock domains. The SDIO environment <NUM> of <FIG> is an example of an environment in where the electronic system <NUM> includes a memory, which is a first in, first out (FIFO) memory <NUM> embodiment of <FIG>. The FIFO memory <NUM> is in the destination clock domain DCD and is utilized to communicate data to the source clock domain SCD through double buffers WRDB, RDDB in the source clock domain.

In this environment, utilization of the single FIFO memory <NUM> reduces the size of the required clock domain crossing synchronization circuitry for interfacing the SD and AHB clock domains. The clock domain crossing synchronization circuitry utilizes the double buffers WRDB, RDDB in an alternate or "ping-pong" manner to transfer data between the SCD and AHB domains and in this way the double buffers increase the bandwidth of the data transfer interface between the two clock domains.

In operation, the host device HST (<FIG>) sends host data transfer requests in the form of host read requests and host write requests over the SDIO bus <NUM> to the SDIO card <NUM>. The additional electronic circuitry <NUM> processes the request and generates signals, including the SNDT, DTCB signals shown in <FIG>, to thereby control operation of the electronic system <NUM> in handling the received request. More specifically, the additional electronic circuitry <NUM> provides data transfer control signals DTCS to a controller <NUM> of the electronic system <NUM> in the source clock domain SCD, where the data transfer control signals include write control signals WRCS and read control signals RDCS. The host device HST and controller <NUM> operate in the source clock domain SCD.

The controller <NUM> includes a receive (RX) submodule <NUM> for processing the write control signals WRCS generated by the additional electronic circuitry <NUM> in response to a write request received from the host device HST. The controller <NUM> also includes a transmit (TX) submodule <NUM> for processing the read control signals RDCS generated by the additional electronic circuitry <NUM> in response to a read request received from the host device HST. The write double buffer WRDB is contained in the RX submodule <NUM> and the read double buffer RDDB contained in the TX submodule <NUM>. Each double buffer WRDB, RDDB includes two data buffers, which are designated data buffers B0 and B1 in <FIG>. The submodules <NUM>, <NUM> in the source clock domain SCD are clocked by a source domain clock signal SCK while controllers <NUM>, <NUM> and the FIFO memory <NUM> in the destination domain clock domain DCD are clocked by a destination domain clock signal DCK.

In processing a host write request, the SDIO card <NUM> (<FIG>) receives the write request via SDIO bus <NUM> from the host device HST. The SDIO bus <NUM> (<FIG>) is connected directly between the RX submodule <NUM> and TX submodule <NUM>, and the host write request includes write data WR_DATA from the host device HST. The write data WR_DATA from the host device HST is supplied over the SDIO bus <NUM> to the RX submodule <NUM> as seen in <FIG>. The additional electronic circuitry <NUM> supplies the WRCS signals to the RX submodule <NUM> to indicate to the RX submodule that it will be receiving write data WR-DATA and will need to process that write data as part of the write request. In response to the WRCS signal, the RX submodule <NUM> issues an internal write request WR-REQ along with write data WR-DATA from the one of the buffers B0, B1 of the double buffer WRDB that is designated as the current buffer during a given data transfer cycle. The operation of the data buffers B0, B1 of the write double buffer WRDB, as well as the read data buffer RDDB, will be described in more detail below. The internal write request WR-REQ and write data WR-DATA are issued in the SCD clock domain to a FIFO write controller <NUM> in the destination clock domain DCD (e.g., AHB clock domain). The FIFO write controller <NUM> processes the internal WR-REQ request and write data WR-DATA, and handles writing the WR-DATA data from the current buffer B0 or B1 of the write double buffer WRDB into the FIFO memory <NUM>. The FIFO read controller <NUM> processes received read data as part of a read request, as will now be described in more detail below.

Similarly, in processing a host read request, the SDIO card <NUM> receives a read request via SDIO bus <NUM> from the host device HST. The host read request includes read data RD_DATA from the host device HST. The read data RD_DATA from the host device HST is supplied over the SDIO bus <NUM> (<FIG>) to the TX submodule <NUM> as seen in <FIG>. The additional electronic circuitry <NUM> supplies the RDCS signals to the TX submodule <NUM> to indicate to the TX submodule that it will be receiving read data RD_DATA and will need to process that read data as part of the read request. In response to the RDCS signals, the RX submodule <NUM> issues an internal read request RD-REQ from the SCD clock domain to the FIFO read controller <NUM> in the DCD clock domain, and the FIFO read controller processes the internal RD-REQ request and accesses read RD-DATA in the FIFO memory <NUM> and provides this read data to the one of the buffers B0, B1 of the read double buffer RDDB in the TX submodule <NUM> which is the current buffer. The TX submodule <NUM> thereafter provides the read data RD-DATA for transfer from the SDIO card <NUM> over the SDIO bus <NUM> to the host device HST.

In transferring data signals between the SD and AHB clock domains, synchronization techniques must be implemented to prevent metastability, data loss, and data coherency issues as mentioned above. Recall, in the SD environment the SD clock domain is the source clock domain SCD and the AHB clock domain is the destination clock domain. Thus, both write requests WR-REQ and read requests RD-REQ from the submodules <NUM>, <NUM> in the SD clock domain must be resynchronized in the AHB clock domain to ensure proper operation. Accordingly, while not expressly shown in <FIG>, each of the RX, TX submodules <NUM>, <NUM> and FIFO write controller <NUM>, FIFO read controller <NUM> include portions of clock domain crossing synchronization circuitry that function to resynchronize signals being communicated between the SD and AHB clock domains. Additional submodules SM, such as additional submodules RX submodule <NUM> and TX submodule <NUM>, may be connected to each of the FIFO write controller <NUM> and FIFO read controller <NUM>.

<FIG> is a signal timing diagram illustrating the loss of proper ordering of data transfer requests that may occur with conventional synchronization techniques implemented by conventional clock domain crossing circuits in the electronic system <NUM> of <FIG>. Although not shown in <FIG>, each of the write request WR-REQ and read request RD-REQ signal from the submodules <NUM>, <NUM> in the SD clock domain is directed to the current buffer of the buffers B0, B1. <FIG> illustrates a write request by way of example. The RX submodule <NUM> generates the write request WR-REQ that includes a source domain write first buffer signal SDWRB0 and a source domain write second buffer signal SDWRB1. The RX submodule <NUM> activates only the buffer signal WRB0, WRB1 for the one of the buffers B0, B1 that is the current buffer. In the example of <FIG>, the source domain write first buffer signal SDWRB0 is activated first at a time t0 when the buffer B0 is indicated as being the current buffer in the source clock domain SCD. The source domain write second buffer signal SDWRB1 is then activated later at a time t1 when the buffer B1 is indicated as being the current buffer in the source clock domain SCD.

Conventional clock domain synchronization circuitry in the FIFO write controller <NUM> resynchronize the SDWRB0, SDWRB1 signals in the destination clock domain as synchronized source domain write buffer signals SDWRB0-SYNC, SDWRB1-SYNC in the destination clock domain, but the proper order of the SDWRB0, SDWRB1 signals is not guaranteed with such conventional clock domain synchronization circuitry. This conventional clock domain synchronization circuitry FIFO write controller <NUM> then generates destination domain write buffer signals DDWRB0, DDWRB1 from, or in response to, the synchronized source domain write buffer signals SDWRB0-SYNC, SDWRB1-SYNC. The FIFO write controller <NUM> thereafter applies the DDWRB0, DDWRB1 signals to the FIFO memory <NUM> to store write data contained in the current buffer B0, B1 of the write double buffer WRDB in the FIFO memory.

As illustrated in <FIG>, conventional clock domain crossing circuitry in the FIFO write controller <NUM> may not properly keep the order of the generated source domain write buffer signals SDWRB0-SYNC, SDWRB1-SYNC in the destination clock domain DCD. This, in turn, results in improper generation of the DDWRB0, DDWRB1 signals as well. <FIG> illustrates a possible scenario where both the synchronized source domain write buffer signal SDWRB0 and synchronized source domain write buffer signal SDWRB1-SYNC occur at a same time t2 in the destination clock domain DCD. Signals in the destination clock domain DCD are synchronized with the destination domain clock signal DCK, but due to both the DDWRB0, DDWRB1 signals occurring at time t2, proper operation will not occur. The write operation associated with one of the DDWRB0, DDWRB1 signals and write data stored in the corresponding data buffer B0, B1 may be lost, or the order write operations may reversed.

Embodiments of the present disclosure are directed to clock domain crossing synchronization circuits and methods that ensure the proper ordering of signals and operation in electronic environments such as that of the electronic system <NUM> of <FIG> in which data is transferred between the FIFO memory <NUM> in the destination clock domain DCD and a current buffer in the source clock domain SCD. The current buffer is the one of the data buffers B0, B1 in double buffer WRDB, RDDB that is being utilized to transfer data during or in a current data transfer cycle. Embodiments of the present disclosure, at the start of a data transfer, communicate the current buffer in the destination clock domain DCD to the source clock domain SCD to thereby set the current buffer in the source clock domain to be equal to that in the destination clock domain. Thereafter, when a read or write data transfer request signal is communicated from the source clock domain SCD to the destination clock domain DCD, the synchronization circuit detects whether the communicated data transfer request signal is associated with the current buffer in the destination clock domain. If the data transfer request signal is associated with the current buffer, then the data transfer is performed in the current data transfer cycle. When the data transfer request signal is not associated with the current buffer in the destination clock domain, the data transfer request signal for the associated data buffer B0, B1 is delayed until a subsequent data transfer cycle, and the data transfer associated performed during this subsequent data transfer cycle.

<FIG> is a functional block diagram of a clock domain crossing synchronization circuit <NUM> according to an embodiment of the present disclosure. Portions of the synchronization circuit <NUM> would be contained in the RX submodule <NUM>, TX submodule <NUM>, FIFO write controller <NUM>, and FIFO read controller <NUM> in the electronic system <NUM> in some embodiments of the present disclosure. The synchronization circuit <NUM> includes a destination current buffer generator <NUM> in a destination clock domain DCD. The destination current buffer generator <NUM> is configured to generate a destination domain current buffer signal DCB having a value indicating whether a first data buffer BO or a second data buffer B1 of a double buffer DB in a source clock domain SCD is a current buffer to be utilized in a current data transfer cycle or operation. The destination current buffer generator <NUM> also toggles, or changes a level or state, of the DCB signal in response a data transfer request signal DTR that is applied to a FIFO memory <NUM> during a data transfer cycle of the synchronization circuit <NUM>, as will be described in more detail below. Components of the synchronization circuit <NUM> in the destination clock domain DCD are clocked by a destination domain clock signal DCK and components in the source clock domain SCD clocked by a source domain clock signal SCK. The clock signals DCK, SCK are shown as being applied to only selected components in the synchronization circuit of <FIG> merely to simplify the figure.

A first synchronization circuit <NUM> receives the destination current buffer signal DCB and generates a corresponding synchronized destination current buffer signal DCB-SYNC in the source clock domain. The DCB-SYNC signal is applied to a source current buffer generator <NUM>, which is configured to generate a source domain current buffer signal SCB based on the synchronized destination current buffer signal DCB-SYNC. The source current buffer signal SCB has a first value indicating the first data buffer B0 is the current buffer and a second value indicating the second data buffer B1 is the current buffer. The source current buffer generator <NUM> further receives the start new data transfer signal SNDT supplied by the additional electronic circuitry <NUM> contained in the SDIO slave IP core <NUM> of the SDIO card <NUM> containing the electronic system <NUM>, as previously described above with reference to <FIG>. In response to the SNDT signal going active to indicate the start of new data transfer cycle or operation of the synchronization circuit <NUM>, the source current buffer generator <NUM> sets the source current buffer signal SCB to a value corresponding to the same current buffer indicated by the synchronized destination current buffer signal SCD-SYNC. In this way, at the start of a data transfer operation, the SCB signal is set to indicate the same current buffer as the DCB signal so that the circuitry in both clock domains DCD and SCD are starting with the same current buffer, either data buffer B0 or data buffer B1.

After the start of a data transfer operation, the source current buffer generator <NUM> changes or toggles the value of the source current buffer signal SCB each data transfer cycle of the data transfer operation in response to the data transfer current buffer signal DTCB indicating the other data buffer B0, B1 should be utilized. Referring back to <FIG>, each of the RX submodule <NUM> and TX submodule <NUM> utilizes the DTCB signal to switch between the two data buffers B0, B1. The additional electronic circuitry <NUM> activates the DTCB, causing the corresponding submodule <NUM>, <NUM> to switch the current buffer B0, B1, either when the current buffer is full (i.e., all of the corresponding data is stored in the current buffer), or if the last byte of the data being transferred to the current buffer has been received or sent. The DTCB signal includes a write current buffer signal WCB and read current buffer signal RCB that are utilized by write clock domain crossing synchronization circuitry and read clock domain crossing synchronization circuitry, respectively, as will be discussed in more detail below with reference to <FIG>, <FIG> and <FIG>, <FIG>.

The value of SCB signal toggles between the first and second values to alternately indicate the first data buffer B0 or second data buffer B1 is the current buffer. The current buffer signal SCB accordingly alternately changes each data transfer cycle of a data transfer operation. A source data transfer request generator <NUM> receives the source current buffer signal SCB and generates a source data transfer request signal SDTR in the source clock domain SCD based on the source current buffer signal. The source data transfer request signal SDTR is associated with the current buffer indicated by the source current buffer signal SCB. In the embodiment of <FIG>, the source data transfer request signal SDTR includes a first buffer source data transfer request signal SDTR-BO and a second buffer source data transfer request signal SDTR-B1. When the first buffer B0 is the current buffer, the source data transfer request generator <NUM> activates the SDTR-BO signal, and when the second buffer B1 is the current buffer the source data transfer request generator activates the SDTR-B1 signal. Only one of the source data transfer request signals SDTR-B0, SDTR-B1 is activated at a time in the source clock domain SCD.

A second synchronization circuit <NUM> receives the source data transfer request signals SDTR-B0, SDTR-B1 and generates a corresponding synchronized source data transfer request signal in the destination clock domain. In the example embodiment of <FIG>, the synchronized source data transfer request signal includes a first buffer synchronized source data transfer request signal SDTR-Bo-SYNC and a second buffer synchronized source data transfer request signal SDTR-B1-SYNC in the destination clock domain. Although only one of the source data transfer request signals SDTR-B0, SDTR-B1 is activated at a time in the source clock domain SCD, both the SDTR-BO-SYNC, SDTR-B1-SYNC signals could be activated or switch at the same time in the destination clock domain DCD due to the proper ordering of these signals not being guaranteed by the synchronization circuit <NUM>.

A destination data transfer request and delay generator <NUM> in the destination clock domain receives the synchronized source data transfer request signals SDTR-BO-SYNC, SDTR-B1-SYNC and the destination domain current buffer signal DCB. In operation, the destination data transfer request and delay generator <NUM> utilizes the DCB signal to determine which one the synchronized source data transfer request signals SDTR-BO-SYNC, SDTR-B1-SYNC to utilize during a current data transfer cycle and which one of these signals to delay to a subsequent data transfer cycle. The delay data transfer request and delay generator <NUM> delays the transfer of data between the FIFO memory <NUM>, or other type of memory in other embodiments, and the one of the data buffers B0, B1 that is the current buffer to a subsequent data transfer cycle when the current buffer indicated by or associated with the destination domain data transfer request signal SDTR-BO-SYNC, SDTR-B1-SYNC does not correspond to the current buffer indicated by the destination domain current buffer signal DCB. When the destination domain current buffer signal DCB has a value indicating the same current buffer as associated with the activated SDTR-B0-SYNC, SDTR-B1-SYNC signal, the destination data transfer request and delay generator <NUM> provides the data transfer request signal DTR to the FIFO memory <NUM> to thereby transfer data between the FIFO memory and the current buffer in the current data transfer cycle.

In operation of the synchronization circuit <NUM>, a data transfer operation starts in response to the additional electronic circuitry <NUM> of the SDIO slave IP core <NUM> (see <FIG>) activating the start new data transfer signal SNDT applied to the source current buffer generator <NUM>. Each data transfer operation includes one or more data transfer cycles. In response to the SNDT signal going active, the source current buffer generator <NUM> drives the source current buffer signal SCB to the same level or value to indicate the same current buffer as the synchronized destination current buffer signal DCB-SYNC provided by the first synchronization circuit <NUM>. The DCB-SYNC signal indicates the current value of the destination current buffer signal DCB generated by the destination current buffer generator <NUM> and thereby the current buffer in the destination clock domain. In this way, the components in the source clock domain SCD determine the current buffer to be used to start the data transfer operation.

The source data transfer request generator <NUM> thereafter activates the one of the first buffer source data transfer request signal SDTR-BO and second buffer source data transfer request signal SDTR-B1 that corresponds to the current buffer. Assume for the present example data operation being described, the initial current buffer is data buffer B0 so that the request generator <NUM> actives the SDTR-BO signal. The synchronization circuit <NUM> then resynchronizes the SDTR-BO signal to activate the synchronized source data transfer request signal SDTR-B0-SYNC in the destination clock domain DCD. At this point, the destination data transfer request and delay generator <NUM> takes one of two actions depending on whether the current buffer, which is buffer B0 in the present example, corresponds to the current buffer indicated by the destination domain current buffer signal DCB. When the DCB signal indicates the current buffer is buffer B0, the destination data transfer request and delay generator <NUM> activates the data transfer signal DTR supplied to the FIFO memory <NUM> to thereby transfer data between the current buffer B0 and the FIFO memory <NUM> in the current data transfer cycle. In response to the activated DTR signal, the destination current buffer generator <NUM> increments or toggles the DCB signal to indicate the other data buffer B1 it the current buffer during a subsequent data transfer cycle. In the source clock domain SCD, the source current buffer generator <NUM> also increments or toggles the SCB signal in response to the additional electronic circuitry <NUM> in the SDIO slave IP core <NUM> (<FIG>) driving the DTCB signal to indicate either the current data buffer B0, B1 is full (i.e., all of the corresponding data is stored in the current buffer) or the last byte of the data being transferred to the current buffer has been received or sent.

During a data transfer cycle, it is possible that the value of the DCB signal has changed state by the time the SDTR-BO signal is applied to the destination data transfer request and delay generator <NUM>. Thus, if in the present example the DCB signal indicates the current buffer is buffer B1 and not buffer Bo, the destination data transfer request and delay generator <NUM> delays the transfer of data between the current buffer B0 and the FIFO memory <NUM> until a subsequent data transfer cycle. In this situation, data is first transferred between the buffer B1 and the FIFO memory <NUM> during the current data transfer cycle. As soon as the destination current buffer signal DCB changes state responsive to the activated DTR signal for this transfer, the DCB signal will once again indicate the buffer B0 is the current buffer and at this point the destination data transfer request and delay generator <NUM> immediately activates the DTR signal to transfer data between the FIFO memory <NUM> and the buffer B0. In this way, no data transfers between the clock domains are lost, but transfers may merely be delayed until a subsequent data transfer cycle where the current buffer associated with a transfer does not match between the source and destination clock domains SCD, DCD.

<FIG> is a more detailed functional block diagram of a write clock domain crossing synchronization circuit <NUM> according to an embodiment of the present disclosure. The clock domain crossing synchronization circuit <NUM> of <FIG> includes the write clock domain crossing synchronization circuit <NUM> of <FIG> as well as a read clock domain crossing synchronization circuit <NUM> as shown in <FIG> to provide synchronization for both read and write data transfers between the source clock domain SCD and destination clock domain DCD.

Referring to <FIG>, the write clock domain crossing synchronization circuit <NUM> includes a destination current buffer generator <NUM> to generate the destination current buffer signal DCB. The generator <NUM> includes a flip-flop <NUM> having an input and an output and is clocked by a destination domain clock signal DCK. A multiplexer <NUM> having a first input coupled to the output of the flip-flop, a second input receiving the output of the flip-flop through an inverter <NUM>, an output coupled to the input of the flip-flop. A control input of the multiplexer <NUM> is coupled to receive a write request signal WR-REQ, where the write request signal is part of the data transfer request signal DTR discussed above with reference the synchronization circuit <NUM> of <FIG>.

In operation, the destination current buffer generator <NUM> toggles the DCB signal each time the WR-REQ signal goes active to transfer data into a FIFO memory <NUM>. The FIFO memory <NUM> corresponds to the FIFO memory in the destination clock domain DCD as discussed above with reference to the embodiments of <FIG> and <FIG>. When the WR-REQ signal is asserted or activated, the multiplexer <NUM> supplies the complement of the DCB signal from the inverter <NUM> to the input of the flip-flop <NUM> so that when the flip-flop is clocked complement of the current value of the DCB signal is output by the flip-flop. In this way the generator <NUM> toggles the DCB signal responsive to the WR-REQ signal being activated. When the WR-REG signal is not active, the multiplexer <NUM> outputs the feedback DCB signal to the input of the flip-flop <NUM> so that the current value of the DCB signal is maintained whenever the flip-flop is clocked.

The write clock domain crossing synchronization circuit <NUM> further includes a first synchronization circuit <NUM> including first and second series-connected flip-flops <NUM> and <NUM> that are clocked by a source domain clock signal SCK. The series-connected flip-flops <NUM>, <NUM> function in a conventional manner to synchronize the DCB signal in the source clock domain SCD and provide a synchronized DCB signal SCB-SYNC. A source domain current buffer generator <NUM> includes a first multiplexer <NUM> having a first input coupled to receive the SCB-SYNC signal and a control input coupled to receive the start new data transfer signal SNDT provided by additional electronic circuitry <NUM>, as described above in relation to <FIG> and <FIG>. A flip-flop <NUM> has an input coupled to the output of the first multiplexer <NUM> and has an output on which a source domain current buffer signal SCB is provided. A second multiplexer <NUM> receives the SCB signal on a first input and the complement of the SCB signal on a second input in the form of the SCB signal applied through an inverter <NUM>. An output of the second multiplexer <NUM> is coupled to a second input of the first multiplexer <NUM>. A control input of the second multiplexer <NUM> is coupled to receive the write current buffer signal WCB provided by the additional electronic circuitry 16where the WCB signal is one of the signals corresponding to the DTCB signal discussed above with reference to <FIG> and <FIG>.

In operation of the source domain current buffer generator <NUM>, at the start of a data transfer operation the additional electronic circuitry <NUM> contained in the SDIO slave IP core <NUM> of the SDIO card <NUM> (<FIG>) asserts or activates the SNDT signal and deactivates the WCB signal. The activated SNDT signal causes the multiplexer <NUM> to provide the DCB-SYNC signal to the input of the flip-flop <NUM>. The flip-flop <NUM> is then clocked by the SCK signal to output the SCB signal having a value corresponding to the value of the DCB-SYNC signal. After a sufficient time for the value of the DCB-SYNC signal to be clocked into the flip-flop <NUM>, the additional electronic circuitry <NUM> deactivates the SNDT signal, which causes the multiplexer to provide the output of the multiplexer <NUM> to the input of the flip-flop <NUM>. When the WCB signal is deactivated, the multiplexer <NUM> provides the SCB signal on its so that the current value of the SCB signal if fed back through the multiplexers <NUM> and <NUM> to the input of flip-flop <NUM> to maintain the current value of the SCB signal when the flip-flop is clocked. When the WCB signal is activated, the multiplexer <NUM> provides the complement of the SCB signal from the invert <NUM> on its output and this complement is thereafter supplied through the multiplexer <NUM> to the input of flip-flop <NUM>. In this situation, when the flip-flop <NUM> is clocked the flip-flop toggles or drives to the complementary state the SCB signal. The additional electronic circuitry <NUM> activates the WCB signal whenever write data has been loaded into the current buffer and is ready for transfer to the FIFO memory <NUM>, as will be described in more detail below.

The clock domain crossing synchronization circuit <NUM> further includes a source data transfer request generator <NUM> that generates a source data transfer request signal in the form of a first buffer source write request signal SWR-B0 and a second buffer source write request signal SWR-B1. In embodiments of the circuit <NUM>, each of the SWR-BO, SWR-B1 signals may be an NRZ signal, and in the present description such an NRZ signal may be described as "going active" or being an "active signal. " In this context, "going active" or "active signal" corresponds to a transition or edge of such an NRZ signal. The source data transfer request generator <NUM> includes a first flip-flop <NUM> and second flip-flop <NUM> that generate the SWR-B0 and SWR-B1 signals on respective outputs. The source data transfer request generator <NUM> further includes logic circuitry <NUM> that receives the WCB signal and the SCB signal and is coupled to the inputs of the flip-flops <NUM>, <NUM>. The logic circuitry <NUM> is configured to provide an active signal to an input of the first flip-flop <NUM> in response to WCB signal going active and the SCB signal indicating a first data buffer B0 is the current buffer. The logic circuitry <NUM> is further configured to provide an active signal to an input of the second flip-flop <NUM> in response to WCB signal going active and the SCB signal indicating the second data buffer B1 is the current buffer. Finally, the logic circuitry <NUM> is further configured to provide an inactive signal on the input of each of the first and second flip-flop <NUM>, <NUM> in response to the first buffer source write request signal SWR-B0 and second buffer source write request signal SWR-B1 going active, respectively.

In the embodiment of <FIG>, the logic circuitry <NUM> includes an inverter <NUM> having an input coupled to receive the SCB signal and having an output coupled to a first input a first AND gate <NUM>. The first AND gate <NUM> has a second input that receives the WCB signal and has an output coupled to a first input of a multiplexer <NUM>. The output of the multiplexer <NUM> is applied to the input of flip-flop <NUM> and output of this flip-flop is coupled directly and through an inverter <NUM> to a first and a second input, respectively, of the multiplexer. The logic circuitry <NUM> further includes a second AND gate <NUM>, multiplexer <NUM>, and inverter <NUM> coupled to the flip-flop <NUM> in the same was as just described for the components <NUM>, <NUM>, <NUM> for the flip-flop <NUM>. In contrast to the first AND gate <NUM>, however, the second AND gate <NUM> receives the SCB signal directly on an input.

In operation, the source data transfer request generator <NUM> activates the one of the SWR-BO, SWR-B1 signals corresponding to the current buffer indicated by the SCB signal whenever the additional electronic circuitry <NUM> activates the WCB signal. As mentioned above, the WCB signal is activated in relation to write data WR-DATA being stored in the current buffer B0 or B1 and being ready for transfer to the FIFO memory <NUM>. Initially, assume the SCB signal is high indicating the buffer B1 is the current buffer and the WCB signal is inactive low. The high SCB signal enables the AND gate <NUM>, but this AND gate initially provides a low output to the multiplexer <NUM> due to the low WCB signal. The low output from AND age <NUM> causes the multiplexer <NUM> to provide the SWR-B1 signal at the output of the flip-flop <NUM> to the input of this flip-flop. In this situation, the flip-flop <NUM> maintains the current state of the SWR-B1 signal if clocked by source clock domain signal SCD. When the WCB signal is activated (i.e., driven high in this embodiment), the AND gate <NUM> applies a high output to multiplexer <NUM> which, in turn, couples the complement of the output of flip-flop <NUM> to the input of the flip-flop <NUM>, where the complement of the output of flip-flop <NUM> is the complement of the SWR-B1 signal output by the inverter <NUM>.

When the flip-flop <NUM> is thereafter clocked by the source domain clock signal SCK, the flip-flop drives the SWR-B1 signal active, assuming both the SCB and WCB signals are a logic <NUM>. Whenever both the SCB and WCB signals are a logic <NUM>, the SWR-B1 signal provided by the flip-flop <NUM> changes value when clocked by the SCK signal. In this way, SWR-B1 signal maintains its current value (logic <NUM> or <NUM>) until the next switch to the current buffer B1. The activated SWR-B1 signal is a non-return to zero (NRZ) signal in the embodiment of <FIG>. When the flip-flop <NUM> drives the SWR-B1 signal active, this active signal is fed back through inverter <NUM> to provide the complement of the SWR-B1 signal to the corresponding input of the multiplexer <NUM> which, in turn, provides this complement to the input of the flip-flop <NUM>. As a result, when the flip-flop <NUM> is again clocked by the SCK signal, the selection signal supplied to the multiplexer <NUM> from AND gate <NUM> is a logic <NUM>, causing the flip-flip to maintain the value of the SWR-B1 signal when the flip-flop is next clocked by the SCK signal. In this way the flip-flop <NUM> generates an active NRZ signal for the SWR-B1 signal. The components <NUM>, <NUM>, <NUM> and <NUM> coupled to flip-flop <NUM> operate in the same way to cause this flip-flop to generate an active NRZ signal for the SWR-B0 signal when the SCB signal is low, indicating the current buffer is the buffer B0.

The clock domain crossing synchronization circuit <NUM> of <FIG> further includes a second synchronization circuit <NUM> including two pairs of series-connected flop-flops. More specifically, the synchronization circuit <NUM> includes first and second series-connected flip-flops <NUM>, <NUM> that are clocked by the destination domain clock signal DCK. These series-connected flip-flops <NUM>, <NUM> function in a conventional manner to synchronize the SWR-B0 signal in the destination clock domain DCD and provide a synchronized first buffer source write request signal SWR-BO-SYNC. The synchronization circuit <NUM> further includes series-connected flip-flops <NUM>, <NUM> that are clocked by the DCK signal and function to synchronize the SWR-B1 signal in the destination clock domain to provide a synchronized second buffer source write request signal SWR-B1-SYNC.

In the embodiment of <FIG>, the clock domain crossing synchronization circuit <NUM> further includes a destination data transfer request and delay generator <NUM> that receives the SWR-BO-SYNC and SWR-B1-SYNC signals from the second synchronization circuit <NUM>. The SWR-BO-SYNC and SWR-B1-SYNC are part of the SDTR-B0-SYNC and SDTR-B1-SYNC signals in the embodiment of <FIG>, and may also be referred to as write first buffer signal SWR-BO-SYNC and write second buffer signal SWR-B1-SYNC in the present description. The destination data transfer request and delay generator <NUM> includes a first pulse generator <NUM> including a flip-flop <NUM> that receives the SWR-BO-SYNC signal on an input and has an output coupled to one input of an XOR gate <NUM>. A second input of the XOR gate <NUM> is coupled to receive the SWR-BO-SYNC signal directly and the XOR gate generates a write first buffer pulse signal WR-BO on an output. A second pulse generator <NUM> includes a flip-flop <NUM> that receives the SWR-B1-SYNC signal on an input and has an output coupled to one input of an XOR gate <NUM>. A second input of the XOR gate <NUM> is coupled to receive the SWR-B1-SYNC signal directly and the XOR gate generates a write second buffer pulse signal WR-BO on an output.

In operation, each pulse generator <NUM>, <NUM> generates an active pulse signal for the WR-BO, WR-B1 signal in response to corresponding SWR-BO-SYNC , SWR-B1-SYNC signal going active. For example, assume the output of flip-flop <NUM> is initially low along with the SWR-BO-SYNC signal. At this point, the XOR gate <NUM> drives the WR-BO signal inactive low. In response to the SWR-BO-SYNC signal going active high, the XOR gate <NUM> drives the WR-BO signal active high since the XOR gate now receives the high SWR-Bo-SYNC signal and the low output signal from the flip-flop <NUM>. When the flip-flip <NUM> is next clocked by the DCK signal, the flip-flop drives its output high so that the XOR gate <NUM> then deactivates the WR-BO signal. In this way the pulse generator <NUM> generates a pulse signal for WR-B0 signal. The operation of pulse generator <NUM> is the same in relation to generation of a pulse signal for the WR-B1 signal.

The destination data transfer request and delay generator <NUM> further includes a first transfer request delay circuit <NUM> having a first input coupled to receive the destination domain current buffer signal DCB and a second input coupled to receive the write first buffer pulse signal WR-BO. The first transfer request delay circuit <NUM> is configured to drive a delayed write first buffer signal D-WR-BO active in response to the write first buffer pulse signal WR-BO going active and the destination domain current buffer signal DCB indicating the second buffer B1 is the current buffer in the destination clock domain DCD. In the embodiment of <FIG>, the first transfer request delay circuit <NUM> includes an AND gate <NUM> having a first input coupled to receive the DCB signal and a second input coupled to an output of an OR gate <NUM> receiving the WR-BO signal on a first input and the D-WR-BO signal on a second input. An output of the AND gate <NUM> is supplied to an input of a flip-flop <NUM> that generates the D-WR-BO signal on an output.

In operation, when either the WR-BO signal or D-WR-BO signal is active high, the OR gate <NUM> enables AND gate <NUM>. When AND gate <NUM> is enabled and the DCB signal is high, indicating the current buffer is buffer B1, and the WR-BO signal is active indicating the buffer B0 is to be written to, the AND gate <NUM> drives its output high. When the flip-flop <NUM> is clocked, this high output of the AND gate <NUM> is latched by the flip-flop, driving the D-WR-BO signal active high. The D-WR-Bo signal will thereafter be utilized to write data associated with the WR-BO signal during a subsequent data transfer cycle, as will be described in more detail below. The OR gate <NUM> functions to cause the flip-flop <NUM>, when clocked, to maintain the D-WR-BO signal high (i.e., a logic <NUM>) when the DCB signal is high indicating the current buffer is buffer B1 and not buffer B0.

A second transfer request delay circuit <NUM> includes an AND gate <NUM>, OR gate <NUM>, and flip-flop <NUM> coupled in the same way as in the corresponding components <NUM>, <NUM>, <NUM> in the first transfer request delay circuit <NUM>, except the DCB signal is applied through an inverter <NUM> to one input of the AND gate <NUM>. The second transfer request delay circuit <NUM> operates in the same way as described for the first transfer request delay circuit <NUM> except in relation to the buffer B1. When the DCB signal is low, indicating the current buffer is buffer B0, and the WR-B1 signal goes high indicating the buffer B1 is to be written to, the AND gate <NUM> drives its output high. When the flip-flop <NUM> is clocked this high output of the AND gate <NUM> is latched by the flip-flop, driving the D-WR-B1 signal high. The D-WR-B1 signal will thereafter be utilized to write data associated with the WR-B1 signal during a subsequent data transfer cycle, as will be also described in more detail below. The OR gate <NUM> functions to cause the flip-flop <NUM>, when clocked, to maintain the D-WR-B1 signal high (i.e., a logic <NUM>) when the DCB signal is low indicating the current buffer is buffer B0 and not buffer B1.

The destination data transfer request and delay generator <NUM> further includes output logic <NUM> coupled to the first and second pulse generators <NUM>, <NUM> to receive the write first buffer pulse signal WR-BO and write second buffer pulse signal WR-B1. The output logic <NUM> is further coupled to the first and second transfer request delay circuits <NUM>, <NUM> to receive the delayed write first buffer signal D-WR-BO and delayed write second buffer signal D-WR-B1. The output logic <NUM> generates a first buffer write request pulse signal WR-B0-REQ in response to either the WR-BO or D-WR-BO signal going active. The output logic <NUM> generates a second buffer write request pulse signal WR-B1-REQ in response to either the WR-B1 or D-WR-B1 signal going active. In the embodiment of <FIG>, the output logic <NUM> includes a first OR gate <NUM> receiving the WR-BO and D-WR-BO signals and generating the WR-B0-REQ in response to these signals. A second OR gate <NUM> receives the WR-B1 and D-WR-B1 signals and generating the WR-B1-REQ in response to these signals.

The destination data transfer request and delay generator <NUM> further includes a first selection circuit in the form of a multiplexer <NUM> in the embodiment of <FIG>. The multiplexer <NUM> has inputs coupled to the output logic <NUM>, or more specifically the outputs of OR gates <NUM>, <NUM> to receive the WR-B0-REQ and WR-B1-REQ signals. A control input of the multiplexer491 receives the destination domain current buffer signal DCB. When DCB signal is low indicating the first buffer B0 is the current buffer, the multiplexer <NUM> outputs the WR-B0-REQ signal as a write request signal WR-REQ to the FIFO memory <NUM> to transfer write data from the current buffer (buffer B0) as indicated by the DCB signal to the FIFO memory. When the DCB signal is high indicating the second buffer B1 is the current buffer, the multiplexer <NUM> provides the WR-B1-REQ signal as the write request signal WR-REQ to the FIFO memory <NUM> to transfer write data from the current buffer (buffer B1) as indicated by the DCB signal to the FIFO memory.

In addition to the above operation, the destination data transfer request and delay generator <NUM> also operates to ensure that desired write data transfers (i.e., WR-BO and WR-B1) are not dropped or missed. The destination data transfer request and delay generator <NUM> does this by generating the WR-REQ signal to transfer write data to the FIFO memory <NUM> in situations where the current buffer as indicated by the DCB signal does not correspond to the buffer associated with activated WR-BO or WR-B1 signal. This is accomplished through the delayed write first and second buffer signals D-WR-BO, D-WR-B1 generated by the circuit <NUM>. The D-WR-BO signal is set to active when a WR-BO signal has been generated to transfer write data from buffer B0 to the FIFO memory <NUM>, but the DCB signal indicates the current buffer is buffer B1. In this situation, as soon as the DCB signal transitions to indicate the current buffer is buffer B0, the active D-WR-BO signal causes OR gate <NUM> to activate the WR-B0-REQ signal which, in turn, is provided through multiplexer <NUM> as the WR-REQ signal to FIFO memory <NUM> to thereby write data from the buffer B0 into the FIFO memory. Thus, even though the DCB signal indicates a different current buffer than the buffer associated with the write request signal (WR-B0 or WR-B1) coming from the source clock domain SCD, this write request is not lost but instead is delayed until a subsequent data transfer cycle in which the DCB signal corresponds to the current buffer associated with this write request. The operation of the destination data transfer request and delay generator <NUM> operates in an analogous way with regard to the D-WR-B1 and the WR-B1 signals in relation to the buffer B1.

Finally, the destination data transfer request and delay generator <NUM> includes a selection circuit <NUM>, which is a multiplexer in the embodiment of <FIG>. The multiplexer has a first input coupled to receive first buffer write data B0-WR-DATA from the data buffer B0 and a second input coupled to receive second buffer write data B1-WR-DATA from the data buffer B1. The data buffers B0 and B1 are part of a double buffer DB in the source clock domain SCD, as described above with reference to the embodiment of <FIG>. In operation, the multiplexer <NUM> supplies the write data B0-WR-DATA stored in data buffer B0 to the FIFO memory <NUM> when the DCB signal indicates the first data buffer B0 is the current buffer. When the DCB signal indicates that the second data buffer B1 is the current buffer, the multiplexer <NUM> supplies the write data B1-WR-DATA stored in data buffer B1 to the FIFO memory <NUM>.

Finally, in the embodiment of <FIG> the clock domain crossing synchronization circuit <NUM> further includes a data selection circuit <NUM> coupled to the data buffers B0, B1 of the double buffer DB and further coupled receive write data WR-DATA from the host HST. In response to the SCB signal, the data selection circuit <NUM> supplies the write data WR-DATA from the host HST to the first data buffer B0 for storage when the DCB signal indicates the first data buffer B0 is the current buffer. When the DCB signal indicates the second data buffer B1 is the current buffer, the data selection circuit <NUM> supplies the write data WR-DATA from the host HST to the second data buffer B1 for storage.

The data selection circuit <NUM> includes a first AND gate <NUM> having a first input coupled to receive the WR-DATA from the host HST, and a second input coupled to receive the SCB signal applied through an inverter <NUM>. A second AND gate has a first input coupled to receive the WR-DATA from the host HST and a second input coupled to receive the SCB signal. When the SCB signal is low, indicating the data buffer B0 is the current buffer, the low SCB signal is applied through inverter <NUM> to enable AND gate <NUM> and thereby provide WR-DATA from the host HST to the first data buffer B0 for stored in the first data buffer. Conversely, when the SCB signal is high, indicating the data buffer B1 is the current buffer, the high SCB signal enables AND gate <NUM> to thereby provide WR-DATA from the host HST to the second data buffer B1 for stored in the second data buffer. The write data WR-DATA includes a plurality of signals or bit, although not expressly shown in <FIG>. Thus, although only two single AND gates <NUM> and <NUM> are shown, a bank of such AND gates would actually be included in the data selection circuit <NUM>, one AND gate for each bit of the WR-DATA. This is more clearly illustrated for the depiction of the data buffers B0, B1 in <FIG>, where each buffer is shown to include a plurality of flip-flops, one flip-flop for each bit of the WR-DATA to be stored in the buffer.

<FIG> is a signal timing diagram illustrating the operation of the write clock domain crossing synchronization circuit <NUM> of <FIG>. The signal timing diagram illustrates, more specifically, the operation of the destination data transfer request and delay generator <NUM> in delaying a write data transfer from the source clock domain SCD when the data buffer B0, B1 associated with the request does not correspond to the current buffer indicated in the destination clock domain DCD. <FIG> illustrates an example in which the write data from the first data buffer B0 is written first and thereafter write data from the data buffer B1 is written using the D-WR-B1 signal generated for this write transfer. The operation will now be described with reference to <FIG> and <FIG>.

At a time t0, the source data transfer request generator <NUM> generates the first buffer source write request signal SWR-B0 associated with a write data transfer to be performed with the data buffer B0 as the current buffer. At a later time t1, the source data transfer request generator <NUM> generates the second buffer source write request signal SWR-B1 associated with a write data transfer to be performed with the data buffer B1 as the current buffer. At a time t2, corresponding signals generated in the destination clock domain DCD based on the SWR-B0 and SWR-B1 signals from the source clock domain SCD are shown. More specifically, the SWR-BO-SYNC and SWR-B1-SYNC signals from the synchronization circuit <NUM>, along with the write first and second buffer pulse signals WR-BO, WR-B1 from the destination data transfer request and delay generator <NUM>, are shown as transitioning in the destination clock domain DCD. The proper order has been lost with these signals, with the transitions for all the signals occurring at approximately t2. Thus, although edges or transitions of the SWR-B0 and SWR-B1 signals are spaced apart at times t0 and t1 in the source clock domain SCD, the corresponding transitions occur at substantially the same time t2 in the destination clock domain.

In a conventional synchronization circuit, the loss of proper ordering and occurrence of multiple transitions at time t2 may result in improper operation, such as loss of one of the write transfers issued from the source clock domain SCD in the form of the SWR-B0 and SWR-B1 signals. In the example of <FIG>, the write data transfer associated with the SWR-B0 signal is processed first in the destination clock domain DCD to transfer write data from the data buffer Bo to the FIFO memory <NUM>. This is seen in the signal timing diagram as the write first buffer pulse signal WR-BO is asserted from time t2 to time t3. This signal is associated with or corresponds to a write transfer with first data buffer B0, and during this time the DCB signal indicates the first data buffer B0 is the current buffer. Thus, this write transfer associated with buffer B0 is processed first. In addition, the transition of the WR-B1 signal while the DCB signal indicates the current buffer is data buffer B0 results in generation of the active delayed write second buffer signal D-WR-B1 at time t3. As a result, when the value of the DCB signal changes state at time t3 to indicate the current buffer is data buffer B1, the write transfer associated with the SWR-B1 signal is performed. Thus, both the write transfers associated with the SWR-B0 and SWR-B1 signals are performed notwithstanding the loss synchronization of the associated signals in the destination clock domain DCD.

<FIG> is a signal timing diagram illustrating operation of the write clock domain crossing synchronization circuit <NUM> of <FIG> in a second example of delaying a write data transfer request. The example of <FIG> is similar to that just described for <FIG> except the DCB signal initially indicates the current buffer is the data buffer B1 instead of buffer B0. The source data transfer request generator <NUM> initially, at a time t0, generates the second buffer source write request signal SWR-B1 associated with a write data transfer to be performed with the data buffer B1, and thereafter at a time t1 generates the first buffer source write request signal SWR-B0. At a time t2, corresponding signals generated in the destination clock domain DCD based on the SWR-B0 and SWR-B1 signals from the source clock domain SCD are shown, specifically the SWR-BO-SYNC and SWR-B1-SYNC signals from the synchronization circuit <NUM>, along with the write first and second buffer pulse signals WR-BO, WR-B1 from the destination data transfer request and delay generator <NUM>. Once again, synchronization has been lost with these signals, with the transitions for all the signals occurring at approximately t2.

In the example of <FIG>, the write data transfer associated with the SWR-B1 signal is processed first in the destination clock domain DCD to transfer write data from the data buffer B1 to the FIFO memory <NUM>. This is seen in the signal timing diagram as the write first buffer pulse signal WR-B1 is asserted from time t2 to time t3. This signal is associated with or corresponds to a write transfer with first data buffer B1, and during this time the DCB signal indicates the first data buffer B1 is the current buffer. Thus, this write transfer associated with buffer B1 is processed first. In addition, the transition of the WR-BO signal while the DCB signal indicates the current buffer is data buffer B1 results in generation of the active delayed write second buffer signal D-WR-BO at time t3. As a result, when the value of the DCB signal changes state at time t3 to indicate the current buffer is data buffer B0, the write transfer associated with the SWR-B0 signal is performed. Thus, both the write transfers associated with the SWR-B0 and SWR-B1 signals are one again performed, albeit in a reverse order when compared to the example of <FIG>. Both write transfers are once again performed notwithstanding the loss synchronization of the associated signals in the destination clock domain DCD.

<FIG> is a more detailed functional block diagram of a read clock domain crossing synchronization circuit <NUM> according to an embodiment of the present disclosure. The clock domain crossing synchronization circuit <NUM> of <FIG> includes the write clock domain crossing synchronization circuit <NUM> of <FIG> as well as a read clock domain crossing synchronization circuit <NUM> as shown in <FIG> to provide synchronization for both read and write data transfers between the source clock domain SCD and destination clock domain DCD. The read clock domain crossing synchronization circuit <NUM> includes components <NUM>-<NUM>, which substantially correspond to components <NUM>-<NUM> in the write clock domain crossing synchronization circuit <NUM> of <FIG>. Once skilled in the art will understand the operation of synchronization circuit <NUM> in view of the above description of the synchronization circuits <NUM><NUM>, and thus, for the sake of brevity, the detailed operation of the synchronization circuit <NUM> will not be described in detail herein.

Claim 1:
A method comprising:
generating (<NUM>) a destination domain current buffer signal (DCB) in a destination clock domain (DCD), the destination domain current buffer signal (DCB) having a value indicating which one of a first data buffer (B0) and a second data buffer (B1) in a source clock domain (SCD) is a current buffer to be utilized during a current data transfer cycle;
synchronizing (<NUM>) the destination domain current buffer signal (DCB) in the source clock domain (SCD) to generate a synchronized destination domain current buffer signal;
generating (<NUM>) a source domain current buffer signal (SCB) based on the synchronized destination domain current buffer signal, the generated source domain current buffer signal having a value indicating the current buffer;
generating (<NUM>) a source data transfer request signal (SDTR) in the source clock domain (SCD) based on the source domain current buffer signal (SCB), the source data transfer request signal (SDTR) being associated with the current buffer indicated by the source domain current buffer signal (SCB);
synchronizing (<NUM>) the source data transfer request signal (SDTR) in the destination clock domain (DCD) to thereby generate a destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC); and
delaying (<NUM>) the transfer of data between a memory in the destination clock domain (DCD) and the current buffer to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal (SDTR-BO-SYNC, SDTR-B1-SYNC) does not correspond to the current buffer indicated by the destination domain current buffer signal (DCB).