Patent Description:
A memory device may include various circuits for generating, processing, or storing data. For example, the memory device may include various circuits for storing or outputting data based on electrical signals such as a command, an address, a clock signal, a data clock signal, and data. The data clock signal may be directly involved in storing or outputting data, and a frequency of the data clock signal may be higher than a frequency of a clock signal.

As the amount of data to be processed in the memory device increases, the frequency of the data clock signal may increase, thereby causing an increase in power consumption of the memory device. To reduce power consumption, the memory device may selectively enable synchronization of the data clock signal. When data processing has completed, the synchronization of the data clock signal is disabled, and the memory device again enables the synchronization of the data clock signal for the purpose of processing next data. However, since it takes time to again enable synchronization of the data clock signal, a next data processing is delayed.

<CIT> discloses apparatuses and methods including memory commands for semiconductor memories. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing commands and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

<CIT> discloses a semiconductor memory device including a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

At least one embodiment of the present disclosure provides an operating method of a memory device for extending synchronization of a data clock signal, and an operating method of an electronic device including the memory device.

According to an embodiment, an operating method of a system comprising a memory device in communication with a memory controller is provided as defined in claim <NUM>.

The first command may include mode register setting information and the second command may indicate initiation of synchronization of a data clock signal, changing settings of a mode register based on the mode register setting information, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock signal toggling at the reference frequency and being extended according to a reference cycle count of the changed settings.

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one skilled in the art may implement the present disclosure. Below, for convenience of description, like components are expressed by using the same or like reference numerals.

<FIG> is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring to <FIG>, an electronic device <NUM> includes a memory controller <NUM> (e.g., a control circuit) and a memory device <NUM>. The electronic device <NUM> may be a device that stores data or outputs the stored data. For example, the electronic device <NUM> may be used to store data in the following devices: a computer, a tablet, a laptop, a notebook computer, a personal digital assistant (PDA), a mobile computing device, a smartphone, and an Internet home appliance.

The memory controller <NUM> may communicate with the memory device <NUM>. The memory controller <NUM> may control the memory device <NUM>. The memory controller <NUM> may store data in the memory device <NUM> or may read data stored in the memory device <NUM>. The memory controller <NUM> may include a command generator <NUM> (e.g., a circuit). The command generator <NUM> may generate a command CMD.

The memory controller <NUM> may generate the command CMD, an address ADD, a clock signal CK, and a data clock signal WCK. The memory controller <NUM> may output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device <NUM>. The memory controller <NUM> may output data to the memory device <NUM> or may receive the data from the memory device <NUM>.

The memory device <NUM> may receive the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK from the memory controller <NUM>. The memory device <NUM> may output the data to the memory controller <NUM> or may receive the data from the memory controller <NUM>. That is, the memory device <NUM> may be a device that stores data. For example, the memory device <NUM> may be volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), or a static random access memory (SRAM), but the present disclosure is not limited thereto.

The memory device <NUM> may include a synchronization circuit <NUM>. The synchronization circuit <NUM> may control synchronization of the data clock signal WCK. The synchronization of the data clock signal WCK may mean that the data clock signal WCK toggles at a timing synchronized with the clock signal CK for the purpose of reading or writing data. The toggling may mean that a logical state transitions from low (L) to high (H) or transitions from H to L.

The command CMD may be a signal indicating an operation to be performed by the memory device <NUM>. For example, the command CMD may include read, write, refresh, precharge, mode register, column address strobe CAS, deselect DES, etc., but the present disclosure is not limited thereto. For example, the command CMD may vary depending on the specification that is applied to the memory device <NUM>.

In an embodiment, the CAS that is a command accompanied before the read command or the write command may be a command for initiating the synchronization of the data clock signal WCK in the LPDDR5 (Low Power Double Data Rate <NUM>). In an embodiment, the DES may be a command indicating that the memory device <NUM> is to perform no operation.

In an embodiment, the memory controller <NUM> may be connected with the memory device <NUM> through a command/address bus (i.e., a CA bus) including a plurality of command pins. The memory controller <NUM> may output command/address signals (hereinafter referred to as "CAs") to the plurality of command pins of the CA bus, and a combination of the CAs may correspond to the command CMD or the address ADD. The memory device <NUM> may determine the command CMD based on the CAs received through the plurality of command pins and a command truth table.

In an embodiment, the command generator <NUM> generates a command defined by a user. In an embodiment, the command generator <NUM> generates a command for changing settings (e.g., mode register settings) of the memory device <NUM>. This will be described in more detail with reference to <FIG>.

The address ADD may be a signal indicating a location of a memory rank, a memory bank, a memory cell, etc. of the memory device <NUM>, at which an operation is to be performed. For example, the address ADD may include a row address and a column address of a memory cell of a memory bank in a selected memory rank.

The clock signal CK may be a signal that toggles periodically. For example, the clock signal CK may be an electrical signal having a logical high level and a logical low level that are periodically repeated. The clock signal CK may be used to determine a timing being a reference of communication with the memory device <NUM> or an internal operation of the memory device <NUM>. In an embodiment, the clock signal CK includes complementary clock signals CK_t and CK_c.

The data clock signal WCK may be a signal that is used in reading or writing data. A frequency of the data clock signal WCK may be higher than a frequency of the clock signal CK. For example, the data clock signal WCK may be a signal that toggles at a high frequency for data processing. In an embodiment, the data clock signal WCK includes complementary clock signals WCK_t and WCK_c.

In an embodiment, to reduce power consumption of the memory device <NUM>, the synchronization circuit <NUM> temporarily performs synchronization of the data clock signal WCK only when a request is received from the memory controller <NUM>. After a given time period passes, the synchronization of the data clock signal WCK may be disabled. In the case where there is a need to process next data, the synchronization circuit <NUM> may again perform synchronization of the data clock signal WCK depending on the request of the memory controller <NUM>. This will be described in more detail with reference to <FIG>.

In an embodiment, the memory controller <NUM> and the memory device <NUM> exchange data with each other. For example, when the command CMD is the write command, the memory controller <NUM> may output data to the memory device <NUM>. For example, when the command CMD is the read command, the memory controller <NUM> may receive data from the memory device <NUM>. The data may be at least a portion of a computer program or application, or may be at least a portion of user data such as an image, a video, a voice, or a text.

In an embodiment, the communication between the memory controller <NUM> and the memory device <NUM> may comply with the specification defined in the LPDDR5.

<FIG> is a block diagram illustrating a memory controller of <FIG>, according to an embodiment of the present disclosure. Referring to <FIG> and <FIG>, the memory controller <NUM> may communicate with a host and the memory device <NUM>. For example, the memory controller <NUM> may output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device <NUM> and may communicate with the memory device <NUM>.

The memory controller <NUM> may include the command generator <NUM>, a mode register setting module <NUM> (e.g., a circuit), an address generator <NUM> (e.g., a circuit), a CMD/ADD transmitter <NUM>, a clock generator <NUM> (e.g., a signal generator), a CK transmitter <NUM>, a WCK transmitter <NUM>, a write data queue <NUM>, a write data transmitter <NUM>, a read data receiver <NUM>, a read data queue <NUM>, a host interface <NUM> (e.g., an interface circuit), and a bus <NUM>.

The command generator <NUM> may generate the command CMD. The command generator <NUM> may output the command CMD to the CMD/ADD transmitter <NUM>.

In an embodiment, the command generator <NUM> generates a column address strobe lengthened CASL, which is defined by the user, based on communication with the host and outputs the command CMD including the CASL. The CASL may be a command that is similar to the CAS in terms of initiating the synchronization of the data clock signal WCK but is defined independently of the CAS to extend the synchronization of the data clock signal WCK. The CASL will be described in more detail with reference to <FIG> and <FIG> together.

In an embodiment, the command generator <NUM> receives mode register setting information MRS from the mode register setting module <NUM>. The command generator <NUM> may output a command CMD including the mode register setting information MRS. The mode register setting information MRS may be information for changing mode register settings of the memory device <NUM>. The mode register setting information MRS will be described in more detail with reference to <FIG> and <FIG> together.

The mode register setting module <NUM> may generate the mode register setting information MRS defined by the user, based on communication with the host. The mode register setting module <NUM> may output the mode register setting information MRS to the command generator <NUM>.

The address generator <NUM> may generate the address ADD. The address generator <NUM> may output the address ADD to the CMD/ADD transmitter <NUM>. The CMD/ADD transmitter <NUM> may receive the command CMD from the command generator <NUM>. The CMD/ADD transmitter <NUM> may receive the address ADD from the address generator <NUM>. The CMD/ADD transmitter <NUM> may output the command CMD and the address ADD to the memory device <NUM>.

The clock generator <NUM> may generate the clock signal CK and the data clock signal WCK. The clock generator <NUM> may output the clock signal CK to the CK transmitter <NUM>. The clock generator <NUM> may output the data clock signal WCK to the WCK transmitter <NUM>. The CK transmitter <NUM> may output the clock signal CK to the memory device <NUM>. The WCK transmitter <NUM> may output the data clock signal WCK to the memory device <NUM>.

The write data queue <NUM> may store data to be written in the memory device <NUM>. For example, data stored in the write data queue <NUM> may be data provided from the host. The write data queue <NUM> may output the data to the write data transmitter <NUM>. The write data transmitter <NUM> may output the data to the memory device <NUM>. For example, the write data transmitter <NUM> may output, to the memory device <NUM>, a data signal DQ and a data mask inversion signal DMI for a write operation. The data signal DQ may be a signal indicating actual information of data. The data mask inversion signal DMI may be a signal for data mask and data bus inversion.

The read data receiver <NUM> may receive data from the memory device <NUM>. For example, the read data receiver <NUM> may receive the data signal DQ and the data mask inversion signal DMI for a read operation from the memory device <NUM>. The read data receiver <NUM> may output the data to the read data queue <NUM>. The read data queue <NUM> may store the data read from the memory device <NUM>. The read data queue <NUM> may provide the host with the data corresponding to a request (e.g., a read request) of the host.

The host interface <NUM> may communicate with the host. The host interface <NUM> may receive the mode register setting information MRS and the CASL from the host and may output the mode register setting information MRS and the CASL to the command generator <NUM>. The host interface <NUM> may receive data for the write operation from the host and may output the data to the write data queue <NUM>. The host interface <NUM> may receive data associated with the read operation from the read data queue <NUM> and may output the data to the host.

The bus <NUM> may electrically connect the command generator <NUM>, the mode register setting module <NUM>, the address generator <NUM>, the CMD/ADD transmitter <NUM>, the clock generator <NUM>, the CK transmitter <NUM>, the WCK transmitter <NUM>, the write data queue <NUM>, the write data transmitter <NUM>, the read data receiver <NUM>, the read data queue <NUM>, and the host interface <NUM>.

<FIG> is a block diagram illustrating a memory device of <FIG>, according to an embodiment of the present disclosure. Referring to <FIG> and <FIG>, the memory device <NUM> may communicate with the memory controller <NUM>. For example, the memory device <NUM> may receive the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK from the memory controller <NUM> and may communicate with the memory controller <NUM>.

The memory device <NUM> includes a CMD/ADD receiver <NUM>, a CMD/ADD circuit <NUM>, a mode register <NUM>, a row decoder <NUM> (e.g., a decoder circuit), a column decoder <NUM> (e.g., a decoder circuit), the synchronization circuit <NUM>, a CK receiver <NUM>, a WCK receiver <NUM>, an internal clock circuit <NUM>, an input/output (I/O) control circuit <NUM>, a write data receiver <NUM>, a read data transmitter <NUM>, and a plurality of memory ranks <NUM>.

The CMD/ADD receiver <NUM> may receive the command CMD and the address ADD from the memory controller <NUM> through the CA bus. The CMD/ADD receiver <NUM> may receive the clock signal CK from the CK receiver <NUM>. The CMD/ADD receiver <NUM> may output the command CMD and the address ADD to the CMD/ADD circuit <NUM>.

The CMD/ADD circuit <NUM> may include a CMD decoder (e.g., a decoder circuit) and an ADD demultiplexer. The CMD decoder may decode the command CMD. The ADD demultiplexer may demultiplex the address ADD. The CMD/ADD circuit <NUM> may control the mode register <NUM> based on a decoding result of the CMD decoder.

In an embodiment, when the command CMD is determined as the CAS by the CMD decoder, the CMD/ADD circuit <NUM> controls the mode register <NUM> and/or the synchronization circuit <NUM> to initiate synchronization. In an embodiment, when the decoding result of the CMD decoder indicates that the command CMD includes the mode register setting information MRS, the CMD/ADD circuit <NUM> changes settings of the mode register <NUM>.

The CMD/ADD circuit <NUM> may control the row decoder <NUM> and the column decoder <NUM> based on a demultiplexing result of the ADD demultiplexer. For example, the ADD demultiplexer may demultiplex the address ADD to obtain a row address and a column address. The CMD/ADD circuit <NUM> may output the row address to the row decoder <NUM>. The CMD/ADD circuit <NUM> may output the column address to the column decoder <NUM>.

The mode register <NUM> may be connected with the CMD/ADD circuit <NUM>. In an embodiment, settings of the mode register <NUM> may be changed based on the mode register setting information MRS decoded by the CMD/ADD circuit <NUM>. In an embodiment, the mode register <NUM> outputs a synchronization initiation signal SYI to the synchronization circuit <NUM> under control of the CMD/ADD circuit <NUM>. The synchronization initiation signal SYI may be a signal that triggers the synchronization of the data clock signal WCK.

The row decoder <NUM> may be connected to the plurality of memory ranks <NUM>. The column decoder <NUM> may be connected to the plurality of memory ranks <NUM>. A location of a memory cell in the plurality of memory ranks <NUM> may be specified by the row decoder <NUM> and the column decoder <NUM>. For example, the row decoder <NUM> may specify a row of a memory rank based on the row address and the column decoder <NUM> may specify a column of the memory rank based on the column address.

The CK receiver <NUM> may receive the clock signal CK from the memory controller <NUM>. The CK receiver <NUM> may output the clock signal CK to the CMD/ADD receiver <NUM> and the synchronization circuit <NUM>. The clock signal CK may provide a timing being a reference in overall operations of the memory device <NUM>.

The WCK receiver <NUM> may receive the data clock signal WCK from the memory controller <NUM>. The WCK receiver <NUM> may output the data clock signal WCK to the synchronization circuit <NUM>.

The synchronization circuit <NUM> may receive the synchronization initiation signal SYI from the mode register <NUM>. The synchronization circuit <NUM> may receive the clock signal CK from the CK receiver <NUM>. The synchronization circuit <NUM> may receive the data clock signal WCK from the WCK receiver <NUM>. The synchronization circuit <NUM> may perform synchronization of the data clock signal WCK based on the clock signal CK, in response to the synchronization initiation signal SYI. The synchronization circuit <NUM> may output a synchronized data clock signal SWCK to the internal clock circuit <NUM>.

The synchronization of the data clock signal WCK may mean matching a timing of the data clock signal WCK with the clock signal CK and allowing the data clock signal WCK to toggle at a reference frequency, such that data are processed within the memory device <NUM>. The reference frequency may be a frequency of the data clock signal WCK in a normal state, which is determined to read or write data in units of a bit. The reference frequency may be higher than a frequency of the clock signal CK. The synchronization of the data clock signal WCK will be described in more detail with reference to <FIG> together.

The internal clock circuit <NUM> may receive the synchronized data clock signal SWCK from the synchronization circuit <NUM>. The internal clock circuit <NUM> may output an internal clock signal to the I/O control circuit <NUM> based on the synchronized data clock signal SWCK. The internal clock signal may be used for the read operation and the write operation in the I/O control circuit <NUM>. In an embodiment, the internal clock circuit <NUM> includes a four-phase converter. The four-phase converter will be described in more detail with reference to <FIG> and <FIG> together.

The I/O control circuit <NUM> may be connected with the write data receiver <NUM>, the read data transmitter <NUM>, the internal clock circuit <NUM>, and the plurality of memory ranks <NUM>. The I/O control circuit <NUM> may be a circuit that controls the read operation and the write operation with the plurality of memory ranks <NUM>. For example, the I/O control circuit <NUM> may receive data from the write data receiver <NUM>. The I/O control circuit <NUM> may output data to the memory rank <NUM> through a write driver. For example, the I/O control circuit <NUM> may receive data from the memory rank <NUM> through a sense amplifier. The I/O control circuit <NUM> may output the data to the read data transmitter <NUM>.

Each of the plurality of memory ranks <NUM> may be connected with the row decoder <NUM>, the corresponding column decoder <NUM>, and the corresponding write driver, and the corresponding sense amplifier. Each of the plurality of memory ranks <NUM> may include a plurality of memory banks. Each of the plurality of memory banks may include a plurality of memory cells. Each of the plurality of memory cells may have a row address and a column address and may store data in the form of logical high or logical low. How data are processed in the plurality of memory ranks <NUM> will be described in more detail with reference to <FIG>, <FIG>, and <FIG> together.

<FIG> are timing diagrams illustrating synchronization of a data clock signal of <FIG>, according to an embodiment of the present disclosure. For better understanding of the present invention, a case where the synchronization of a data clock signal is not extended will be described with reference to <FIG>, and a case where the synchronization of the data clock signal is extended will be described with reference to <FIG>.

<FIG> describes a method for processing a data stream depending on the CAS and the write command. Referring to <FIG>, waveforms of CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In <FIG>, a horizontal axis represents a time. CK_t and CK_c may correspond to the clock signal CK of <FIG>. A command/address signal CA may correspond to the command CMD and the address ADD of <FIG>. A chip select signal CS may be a signal for activating the CA. The CMD may be determined based on a command truth table of the CA. WCK_t and WCK_c may correspond to the data clock signal WCK of <FIG>. DQ and DMI may correspond to data of <FIG> (e.g., DQ and DMI for a write operation). To provide a better understanding of the present disclosure, the timing diagram of <FIG> will be described with reference to <FIG> and <FIG>.

At time tp1, the memory device <NUM> detects toggling of the clock signal CK. For example, the memory device <NUM> may detect a transition of CK_t from logical low to logical high and/or a transition of CK_c from logical high to logical low. The memory device <NUM> may determine the CA in response to the toggling of the clock signal CK. The command CMD corresponding to the determined CA may be the CAS. At time tp1, WCK_t, WCK_c, DQ, and DMI may be in a don't care state.

The memory device <NUM> initiates the synchronization of the data clock signal WCK in response to the command CMD being determined as the CAS. For example, time tp1 may be a start point of a time period tWCK_SYNC indicating a period associated with the synchronization of the data clock signal WCK. For example, time tp1 may be a start point of a preparation time period tSYNC_Prepare indicating a period of preparing the synchronization of the data clock signal WCK.

In an embodiment, immediately after receiving the CAS, the memory device <NUM> may receive the command CMD corresponding to a write operation. For example, the memory device <NUM> may sequentially receive the CAS and the command CMD corresponding to the write operation. In an embodiment, a time period from when a command corresponding to the write operation is applied to when the data DQ and DMI are processed may be determined in advance depending on the specification applied to the memory device <NUM>.

At time tp2, the memory device <NUM> determines that a time period tENL passes from time tp1 when the CAS is determined. The time period tENL may indicate a period where the data clock signal WCK is in the don't care state. The memory device <NUM> may maintain the data clock signal WCK in a given logical state from time tp2. For example, the memory device <NUM> may maintain WCK_t at logical low and may maintain WCK_c at logical high.

At time tp3, the memory device <NUM> determines that a time period tPRE_Static passes from time tp2 when the data clock signal WCK is maintained in the given logical state. The time period tPRE_Static may indicate a period where the data clock signal WCK is maintained in the given logical state. The memory device <NUM> may perform pre-toggling of the data clock signal WCK after time tp3. The pre-toggling may mean that the data clock signal WCK toggles at a frequency lower than the reference frequency. For example, the memory device <NUM> may allow the data clock signal WCK to toggle at a frequency, which is lower than the reference frequency by as much as two times, during a time period tPRE _Toggle from time tp3. However, the present disclosure is not limited thereto. For example, according to an embodiment, the memory device <NUM> allows the data clock signal WCK to toggle at the reference frequency in the time period tPRE_Toggle.

At time tp4, the memory device <NUM> determines that the time period tPRE_Toggle passes from time tp3 when the data clock signal WCK pre-toggles at a frequency lower than the reference frequency. The time period tPRE_Toggle may indicate a period where the data clock signal WCK pre-toggles at the frequency lower than the reference frequency. In an embodiment, the memory device <NUM> allows the data clock signal WCK to toggle at the reference frequency after time tp4. The reference frequency that is a frequency used to read or write data in units of a bit may be a frequency of the data clock signal WCK in a normal state. For example, the reference frequency may correspond to a frequency of the DQ.

At time tpd1, the memory device <NUM> may initiate processing of a data stream. The data stream may indicate a set of DQs corresponding to valid data. For example, the memory device <NUM> may store the DQ based on the data clock signal WCK from time tpd1.

In an embodiment, the memory device <NUM> processes a data stream from time tpd1 when a time period tDQI passes from time tp4. The time period tDQI may be a margin that is set to cope with an abnormal operation (e.g., the situation where a frequency of the data clock signal WCK does not yet converge to the reference frequency). In an embodiment, the time period tDQI is omitted or may be decreased or increased.

At time tpd2, the memory device <NUM> completes the processing of the data stream. The data clock signal WCK that toggles after time tpd2 may be irrelevant to the processing of the data stream. In the case where processing of another data stream is not required, the toggling of the data clock signal WCK after time tpd2 may cause unnecessary power consumption.

At time tp5, the memory device <NUM> may disable the synchronization of the data clock signal WCK. To disable the synchronization may mean that the data clock signal WCK does not toggle or that the data clock signal WCK is in the don't care state without solving a skew with the clock signal CK. After time tp5, since the synchronization of the data clock signal WCK is disabled, power consumption of the memory device <NUM> may be reduced. In the case of a mobile device in which a power supply is limited, disabling the synchronization of the data clock signal WCK when data processing is not required may be useful for power management.

In an embodiment, time tp5 when the synchronization of the data clock signal WCK is disabled may be determined as a time when a time period tWCK_Toggle passes from time tp4 when the data clock signal WCK toggles. The time period tWCK _Toggle may comply with settings in the mode register <NUM> of the memory device <NUM>. Time tp5 may be an end point of the time period tWCK_SYNC.

As described above, the synchronization of the data clock signal WCK corresponding to the CAS and the write command is described with reference to <FIG>. The time period tWCK_SYNC associated with the synchronization of the data clock signal WCK may be a time period from tp1 to tp5. The time period tWCK_SYNC may include the preparation time period tSYNC _Prepare and the time period tWCK _Toggle. The preparation time period tSYNC _Prepare may include the time period tENL, the time period tPRE_Static, and the time period tPRE _Toggle. The time period tWCK_Toggle may indicate a period where the data clock signal WCK toggles at the reference frequency. After the time period tDQI passes from time tp4 being a start point of the time period tWCK _Toggle, a data stream may be processed.

<FIG> describes a method for processing a data stream depending on the CAS and the read command. Referring to <FIG>, waveforms of CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In <FIG>, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device <NUM> are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy. The timing diagram of <FIG> will be described with reference to <FIG> and <FIG>.

Even in the case of processing the read command as well as the write command, the memory device <NUM> may process data based on the synchronization of the data clock signal WCK. For example, the memory device <NUM> may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC _Prepare and may then process a data stream within the time period tWCK_Toggle.

In more detail, based on the CAS and the read command being sequentially received, the memory device <NUM> may maintain the data clock signal WCK in the don't care state during the time period tENL, may maintain the data clock signal WCK in the given logical state during the time period tPRE_Static, and may perform pre-toggling of the data clock signal WCK at a frequency lower than the reference frequency during the time period tPRE _Toggle. After the time period tDQI for margin passes from time tp4 being a start point of the time period tWCK Toggle, the memory device <NUM> may output the data stream depending on the read command.

As described above, the method for processing the data stream in the write operation is described with reference to <FIG>, and the method for processing the data stream in the read operation is described with reference to <FIG>. After the data stream is processed, the synchronization of the data clock signal WCK may be disabled, and thus, power consumption of the memory device <NUM> may be reduced. However, after the synchronization of the data clock signal WCK is disabled, when another read command or a write command is received, the memory device <NUM> may again perform the synchronization of the data clock signal WCK. This will be more fully described with reference to <FIG>.

<FIG> describes a method for processing a plurality of data streams. Referring to <FIG>, waveforms of CK_t, CK_c, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In <FIG>, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device <NUM> are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy. The timing diagram of <FIG> will be described with reference to <FIG> and <FIG>.

The memory device <NUM> may process a plurality of data streams. For example, the memory device <NUM> may process a first data stream during a time period 1st tWCK_SYNC. Afterwards, the memory device <NUM> may process a second data stream during a time period 2nd tWCK SYNC.

The time period 1st tWCK_SYNC may be a time period from tp1 to tp5. Time tp1 may be a time at which the CAS corresponding to a first write command is determined. Time tp5 may be a time at which the toggling of the data clock signal WCK for a first write operation ends. The time period 1st tWCK_SYNC may include a time period 1st tValid_Data. The time period 1st tValid _Data may be a time period from time tp1 when a command associated with the first data stream is determined to time tpd2 when processing of the first data stream is completed.

The time period 1st tWCK_SYNC may include a preparation time period 1st tSYNC_Prepare and a time period 1st tWCK Toggle. The preparation time period 1st tSYNC_Prepare may be a time period from time tp1 when the command associated with the first data stream is determined to time tp4 when the data clock signal WCK toggles at the reference frequency. The preparation time period 1st tSYNC _Prepare may include a time period in which the data clock signal WCK is in the don't care state, a time period in which the data clock signal WCK is maintained in the given logical state, and a time period in which the data clock signal WCK pre-toggles at a frequency lower than the reference frequency.

The time period 1st tWCK_Toggle may be a time period from time tp4 when the data clock signal WCK toggles at the reference frequency to time tp5 when the synchronization of the data clock signal WCK is disabled. In the time period 1st tWCK _Toggle, the memory device <NUM> may start to process the first data stream from time tpd1 when the time period tDQI passes from time tp4. At time tpd2, the memory device <NUM> may complete the processing of the first data stream.

The time period 2nd tWCK_SYNC may be a time period from tp6 to tp10. Time tp6 may be a time at which the CAS corresponding to a second write command is determined. Time tp10 may be a time at which the toggling of the data clock signal WCK for a second write operation ends. The time period 2nd tWCK_SYNC may include a time period 2nd tValid_Data. The time period 2nd tValid _Data may be a time period from time tp6 when a command associated with the second data stream is determined to time tpd4 when processing of the second data stream is completed.

The time period 2nd tWCK_SYNC may include a preparation time period 2nd tSYNC _Prepare and a time period 2nd tWCK Toggle. The preparation time period 2nd tSYNC _Prepare may be a time period from time tp6 when the command associated with the second data stream is determined to time tp9 when the data clock signal WCK toggles at the reference frequency. The preparation time period 2nd tSYNC _Prepare may include a time period in which the data clock signal WCK is in the don't care state, a time period in which the data clock signal WCK is maintained in the given logical state, and a time period in which the data clock signal WCK pre-toggles at a frequency lower than the reference frequency.

The time period 2nd tWCK Toggle may be a time period from time tp9 when the data clock signal WCK toggles at the reference frequency to time tp10 when the synchronization of the data clock signal WCK is disabled. In the time period 2nd tWCK _Toggle, the memory device <NUM> may start to process the second data stream from time tpd3 when the time period tDQI passes from time tp9. At time tpd4, the memory device <NUM> may complete the processing of the second data stream.

As described above, in the memory device <NUM>, the synchronization of the data clock signal WCK may be disabled to reduce power consumption after data processing is completed. However, in the case where a new write command or a new read command is received later, the memory device <NUM> again performs the synchronization of the data clock signal WCK, thereby causing a delay of data processing. Accordingly, there is required a method for extending the synchronization of the data clock signal WCK in the memory device <NUM>. This will be more fully described with reference to <FIG> together.

<FIG> is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring to <FIG>, an electronic device <NUM> includes a memory controller 100a and a memory device 200a. The memory controller 100a includes the command generator <NUM>, the address generator <NUM>, the CMD/ADD transmitter <NUM>, the CK transmitter <NUM>, the WCK transmitter <NUM>, the write data transmitter <NUM>, and the read data receiver <NUM>. The memory device 200a includes the CMD/ADD receiver <NUM>, the CMD/ADD circuit <NUM>, the mode register <NUM>, the synchronization circuit <NUM>, the CK receiver <NUM>, the WCK receiver <NUM>, the I/O control circuit <NUM>, the write data receiver <NUM>, the read data transmitter <NUM>, and the memory rank <NUM>. Lower level components of the electronic device <NUM> are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, the electronic device <NUM> extends the synchronization of the data clock signal WCK based on the CASL defined by the user. The CASL may be a command defined by the user. The CASL may define a clock section that indicates initiation of the synchronization of the data clock signal WCK and corresponds to the synchronization. In an embodiment, the clock section defined in the CASL is longer than a clock section defined in the CAS of the LPDDR5.

According to an embodiment of the present disclosure, the command generator <NUM> may include the CASL being the defined command. The CASL may be provided from the host. To extend the synchronization, the command generator <NUM> may output the CASL to the CMD/ADD transmitter <NUM>. The CMD/ADD transmitter <NUM> may output the CASL to the CMD/ADD receiver <NUM> in the form of the command CMD. The CMD/ADD receiver <NUM> may output the command CMD including the CASL to the CMD/ADD circuit <NUM>. The CMD/ADD circuit <NUM> may decode the command CMD to obtain the CASL. The CMD/ADD circuit <NUM> may output the CASL to the mode register <NUM>.

The mode register <NUM> may receive the CASL from the CMD/ADD circuit <NUM>. The mode register <NUM> may determine the clock section for the synchronization, based on the CASL. In this case, the determined clock section may be longer than the clock section corresponding to the CAS. The mode register <NUM> may output a synchronization initiation signal SYIa to the synchronization circuit <NUM>. For example, the mode register <NUM> may output the synchronization initiation signal SYIa in response to receiving the CASL. The synchronization initiation signal SYIa may include information about the clock section according to the CASL.

The synchronization circuit <NUM> may receive the synchronization initiation signal SYIa from the mode register <NUM>. The synchronization circuit <NUM> may perform the synchronization of the data clock signal WCK during an extended clock section, based on the synchronization initiation signal SYIa.

<FIG> is a timing diagram illustrating a data clock signal in which the synchronization in <FIG> is extended, according to an embodiment of the present disclosure. A timing diagram indicating synchronization in the case of using the CAS and a timing diagram indicating synchronization in the case of using the CASL are illustrated in <FIG>. For example, the case of using the CAS may correspond to the memory device <NUM> of <FIG>, and the case of using the CASL may correspond to the memory device 200a of <FIG>. In <FIG>, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

Referring to <FIG> associated with the case of using the CAS and <FIG>, in response to the command CMD being determined as the CAS, the memory device <NUM> may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC _Prepare and may allow the data clock signal WCK to toggle during the time period tWCK Toggle. In this case, the time period tWCK_Toggle may correspond to a clock section.

Referring to <FIG> associated with the case of using the CASL and <FIG>, in response to the command CMD being determined as the CASL, the memory device 200a prepares the toggling of the data clock signal WCK during the preparation time period tSYNC _Prepare and allows the data clock signal WCK to toggle during the time period tWCK Toggle. In this case, the time period tWCK _Toggle corresponds to the clock section defined in the CASL.

That is, in the case of using the CAS, the clock section corresponding to the time period tWCK_Toggle may be from tp4 to tp5. In the case of using the CASL, the clock section corresponding to the time period tWCK _Toggle may be from tp4 to tpa. As the clock section corresponding to the time period tWCK _Toggle is extended based on the defined CASL, the time period tWCK _Toggle may be extended as much as a time period from tp5 to tpa.

<FIG> is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring to <FIG>, an electronic device <NUM> includes a memory controller 100b and a memory device 200b. The memory controller 100b includes the command generator <NUM>, the mode register setting module <NUM>, the address generator <NUM>, the CMD/ADD transmitter <NUM>, the CK transmitter <NUM>, the WCK transmitter <NUM>, the write data transmitter <NUM>, and the read data receiver <NUM>. The memory device 200b includes the CMD/ADD receiver <NUM>, the CMD/ADD circuit <NUM>, the mode register <NUM>, the synchronization circuit <NUM>, the CK receiver <NUM>, the WCK receiver <NUM>, the I/O control circuit <NUM>, the write data receiver <NUM>, the read data transmitter <NUM>, and the memory rank <NUM>. Lower level components of the electronic device <NUM> are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, the electronic device <NUM> may extend the synchronization of the data clock signal WCK by changing settings of the mode register <NUM>, based on a command including the mode register setting information MRS. The mode register setting information MRS may be set by the user. In an embodiment, the mode register setting information MRS includes a reference cycle count (or number) of the data clock signal WCK. The reference cycle count (or number) may indicate the number of times that the data clock signal WCK toggles in the synchronization of the data clock signal WCK. For example, the reference cycle count (or number) that is the number of times defined by the user may be greater than the number of times that the data clock signal WCK normally toggles, which is defined in the mode register <NUM>.

According to an embodiment of the present disclosure, the mode register setting module <NUM> may determine the mode register setting information MRS. Alternatively, the mode register setting information MRS may be received from the host. The mode register setting module <NUM> may output the mode register setting information MRS to the command generator <NUM>. The command generator <NUM> may output the mode register setting information MRS to the CMD/ADD transmitter <NUM>. The CMD/ADD transmitter <NUM> may output the command CMD including the mode register setting information MRS to the CMD/ADD receiver <NUM>. The CMD/ADD receiver <NUM> may output the command CMD including the mode register setting information MRS to the CMD/ADD circuit <NUM>. The CMD/ADD circuit <NUM> may decode the command CMD to obtain the mode register setting information MRS. The CMD/ADD circuit <NUM> may output the mode register setting information MRS to the mode register <NUM>.

Settings of the mode register <NUM> may be changed based on the mode register setting information MRS. For example, based on the mode register setting information MRS, the mode register <NUM> may determine the number of times that the data clock signal WCK toggles in the time period tWCK_Toggle, as the reference cycle count (or number). In an embodiment, the reference cycle count (or number) is greater than the number of times that the data clock signal WCK normally toggles in the time period tWCK_Toggle. The mode register <NUM> may output a synchronization initiation signal SYIb to the synchronization circuit <NUM>. For example, the mode register <NUM> may output a synchronization initiation signal SYIb in response to receiving the mode register setting information MRS.

The synchronization circuit <NUM> may receive the synchronization initiation signal SYIb from the mode register <NUM>. The synchronization circuit <NUM> may extend the synchronization of the data clock signal WCK, based on the synchronization initiation signal SYIb.

<FIG> is a timing diagram illustrating a data clock signal in which the synchronization in <FIG> is extended, according to an embodiment of the present disclosure. A timing diagram indicating synchronization performed depending on a conventional mode register setting and a timing diagram indicating synchronization performed depending on a changed mode register setting are illustrated in <FIG>. For example, the case of the conventional mode register setting may correspond to the memory device <NUM> of <FIG>, and the case of the changed mode register setting may correspond to the memory device 200b of <FIG>. In <FIG>, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

Referring to <FIG> associated with the conventional mode register setting and <FIG>, in response to the command CMD being determined as the CAS, the memory device <NUM> may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC _Prepare and may allow the data clock signal WCK to toggle during the time period tWCK Toggle. The number of times that the data clock signal WCK toggles in the time period tWCK_Toggle may comply with a setting in the mode register <NUM>. For example, during the time period tWCK_Toggle, the data clock signal WCK may toggle by as much as a default cycle count (or number).

Referring to <FIG> associated with the changed mode register setting and <FIG>, the memory device 200b may receive the mode register setting information MRS before time tp1. The mode register <NUM> of the memory device 200b may change settings based on the mode register setting information MRS. For example, with regard to the synchronization of the data clock signal WCK, the mode register <NUM> may determine the number of times that the data clock signal WCK toggles in the time period tWCK _Toggle, as the reference cycle count (or number) instead of using the default cycle count (or number). At time tp1, in response to the command CMD being determined as the CAS, the memory device 200b may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC _Prepare and may allow the data clock signal WCK to toggle during the time period tWCK_Toggle. In this case, the number of times that the data clock signal WCK toggles in the time period tWCK _Toggle may comply with the changed setting in the mode register <NUM>. For example, during the time period tWCK Toggle, the data clock signal WCK may toggle by as much as the reference cycle count (or number). In an embodiment, the reference cycle count (or number) is greater than the default cycle count (or number).

That is, a frequency of the data clock signal WCK may be uniform during the time period tWCK _Toggle, and the time period tWCK _Toggle that is based on the data clock signal WCK toggling by as much as the default cycle number may be from tp4 to tp5. The time period tWCK _Toggle that is based on the data clock signal WCK toggling by as much as the reference cycle number may be from tp4 to tpb. As the number of times that the data clock signal WCK toggles increases during the time period tWCK _Toggle, the time period tWCK _Toggle may be extended by as much as a time period from tp5 to tpb.

<FIG> is a timing diagram illustrating data streams that are processed based on a data clock signal in which synchronization is extended, according to an embodiment of the present disclosure. A method for processing a plurality of data streams based on the extended data clock signal WCK will be described with reference to <FIG>. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy. The timing diagram of <FIG> may correspond to the synchronization in the memory device 200a of <FIG> or the synchronization in the memory device 200b of <FIG>.

In an embodiment, at time tp1, a command may be determined as the CASL. In an embodiment, the command CMD for changing settings of a mode register before time tp1 is received, and the number of times that the data clock signal WCK toggles is determined as the reference cycle count (or number) and at time tp1, a command may be determined as the CAS.

During the preparation time period tSYNC _Prepare from time tp1, a memory device prepares toggling of the data clock signal WCK. During the time period tWCK_Toggle from time tp4, the memory device allows the data clock signal WCK to toggle. In this case, the time period tWCK _Toggle may be a time period extended based on the CASL or the setting change of the mode register. For example, the time period tWCK_Toggle may be longer than the first time period 1st tWCK Toggle of <FIG>. In an embodiment, the first time period 1st tWCK Toggle has a first duration and the duration of the time period tWCK_Toggle is a sum of the first duration and a second duration of the clock section indicated by the CASL or the setting change. Thus, the duration of the time period tWCK_Toggle is extended by the second duration.

At time tp5, the data clock signal WCK may continuously toggle. Because the synchronization of the data clock signal WCK is not disabled, a command for initiation of the synchronization may not be required. For example, because the toggling of the data clock signal WCK is maintained at time tp5, the CAS for a second write operation may not be required. Since one cycle where the command CMD for the CAS is received is omitted, the time period 2nd tValid _Data may be shortened. As such, processing of the second data stream may quicken. For example, a time tpd4c when the processing of the second data stream is completed may be earlier than a time tpd4 of <FIG>, at which the processing of the second data stream is completed.

In an embodiment, a command received immediately before the second write command is not the CAS command in the LPDDR5. For example, the CA received at time tp6 may be determined as a write command based on the command truth table, and the CA received at time tp5 may be determined as the DES (i.e., as not being the CAS) based on the command truth table.

As described above, according to an embodiment of the present disclosure, there is provided a method for improving a speed, at which data are processed in a memory device, by extending the synchronization of the data clock signal WCK.

<FIG> is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring to <FIG>, an electronic device <NUM> includes a memory controller 100c and a memory device 200c. The memory device 200c includes the I/O control circuit <NUM>, a first memory rank 240a, and a second memory rank 240b. Each of the first memory rank 240a and the second memory rank 240b may include a plurality of memory banks. The memory controller 100c may output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device 200c. The memory controller 100c may exchange data with the memory device 200c. The clock signal CK, the data clock signal WCK, and data are similar to the clock signal CK, the data clock signal WCK, and the data in <FIG>, and thus, additional description will be omitted to avoid redundancy.

The memory device 200c may receive the command CMD and the address ADD from the memory controller 100c. The command CMD includes CMD_R1 and CMD_R2. CMD_R1 may indicate a command to be performed in the first memory rank 240a. CMD_R2 may indicate a command to be performed in the second memory rank 240b. CS_R1 may indicate a signal indicating whether to select the first memory rank 240a. CS_R2 may indicate a signal indicating whether to select the second memory rank 240b.

The I/O control circuit <NUM> may control the first memory rank 240a based on CS_R1 and CMD_R1. For example, the I/O control circuit <NUM> may select the first memory rank 240a based on CS_R1, and based on CMD_R1, the I/O control circuit <NUM> may write data in the first memory rank 240a or may read data from the first memory rank 240a.

The I/O control circuit <NUM> may control the second memory rank 240b based on CS_R2 and CMD_R2. For example, the I/O control circuit <NUM> may select the second memory rank 240b based on CS_R2, and based on CMD_R2, the I/O control circuit <NUM> may write data in the second memory rank 240b or may read data from the second memory rank 240b.

In an embodiment, the I/O control circuit <NUM> independently controls the first memory rank 240a and the second memory rank 240b. For example, while the I/O control circuit <NUM> writes data in the first memory rank 240a, the I/O control circuit <NUM> may read data from the second memory rank 240b. Alternately, while the I/O control circuit <NUM> writes data in the second memory rank 240b, the I/O control circuit <NUM> may read data from the first memory rank 240a.

<FIG> is a timing diagram illustrating data streams that are processed according to an embodiment of the present disclosure. A method for processing a plurality of data streams in a memory device where the synchronization of the data clock signal WCK is not extended will be described with reference to <FIG>.

Referring to <FIG>, waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In <FIG>, a horizontal axis represents a time. In CK_t, CK_c, WCK_t, WCK_c, DQ, and DMI, meanings and a correspondence relationship with a memory device are similar to those described with reference to <FIG>, and CS_R1, CMD_R1, CS_R2, and CMD_R2 are similar to those described with reference to <FIG>. Thus, additional description will be omitted to avoid redundancy. The timing diagram of <FIG> will be described with reference to <FIG> and <FIG>.

The memory device 200c may process the first data stream through the first memory rank 240a and may process the second data stream through the second memory rank 240b. For example, the memory device 200c may process the first data stream during the time period 1st tWCK_SYNC. Afterwards, the memory device 200c may process the second data stream during the time period 2nd tWCK_SYNC.

At time tp4, the memory device 200c may allow the data clock signal WCK to toggle at the reference frequency. After the time period 1st tWCK_Toggle passes from time tp4, the synchronization of the data clock signal WCK may be disabled at time tp5. After the synchronization of the data clock signal WCK is disabled, processing of the second data stream may be requested. To again perform the synchronization of the data clock signal WCK, the memory device 200c may again prepare the toggling of the data clock signal WCK during the preparation time period 2nd tSYNC _Prepare, based on a new CAS (e.g., the CAS determined at time tp6). As such, processing of the second data stream may be delayed.

<FIG> is a timing diagram illustrating data streams that are processed based on a data clock signal in which synchronization is extended, according to an embodiment of the present disclosure. A method for processing a plurality of data streams in a memory device where the synchronization of the data clock signal WCK is extended will be described with reference to <FIG>.

Referring to <FIG>, waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In each waveform, the meaning and a correspondence relationship of a memory device are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy. The timing diagram of <FIG> will be described with reference to <FIG> and <FIG>.

In an embodiment, at time tp1, a command may be determined as the CASL. In an embodiment, the command CMD for changing settings of a mode register before time tp1 may be received, and the number of times that the data clock signal WCK toggles may be determined as the reference cycle count (or number) (e.g., greater than the default cycle count (or number)) and at time tp1, a command may be determined as the CAS. As such, the synchronization of the data clock signal WCK of the memory device 200c may be extended. For example, the time period tWCK_Toggle corresponding to the synchronization of the data clock signal WCK may be from tp4 to tp10x, and the time period tWCK_Toggle may be longer than the time period 1st tWCK Toggle in <FIG>.

In an embodiment, the memory device 200c processes the first data stream and the second data stream in parallel, based on the extended synchronization of the data clock signal WCK. For example, the memory device 200c may process the first data stream during the time period 1st tValid_Data. Before the processing of the first data stream is completed, at time tp6x, the memory device 200c may determine a write command for the second data stream. In this case, because the toggling of the data clock signal WCK is maintained, the memory device 200c may process the second data stream without the CAS for a write operation of the second data stream. At time tpd4x, the memory device 200c may complete the processing of the second data stream based on the toggling of the data clock signal WCK thus extended.

As described above, the memory device 200c may process the first data stream and the second data stream in parallel based on the extended synchronization of the data clock signal WCK, thus improving a data processing speed. For example, a time tpd4x when the processing of the second data stream is completed may be earlier than a time tpd4 of <FIG>, at which the processing of the second data stream is completed.

<FIG> is a block diagram illustrating a memory device according to an embodiment of the present disclosure. Referring to <FIG>, a memory device 200d includes the CMD/ADD receiver <NUM>, the CMD/ADD circuit <NUM>, the mode register <NUM>, the synchronization circuit <NUM>, the CK receiver <NUM>, the WCK receiver <NUM>, the internal clock circuit <NUM>, the I/O control circuit <NUM>, the write data receiver <NUM>, the read data transmitter <NUM>, and the plurality of memory ranks <NUM>.

The CMD/ADD receiver <NUM>, the CMD/ADD circuit <NUM>, the mode register <NUM>, the synchronization circuit <NUM>, the CK receiver <NUM>, the WCK receiver <NUM>, the I/O control circuit <NUM>, the write data receiver <NUM>, the read data transmitter <NUM>, and the plurality of memory ranks <NUM> are similar to those described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

In an embodiment, the internal clock circuit <NUM> may receive the synchronized data clock signal SWCK from the synchronization circuit <NUM>. The internal clock circuit <NUM> may output an internal clock signal to the I/O control circuit <NUM> based on the synchronized data clock signal SWCK.

In an embodiment, the internal clock signal is a four-phase clock signal. For example, the internal clock circuit <NUM> may include a four-phase converter. The four-phase converter may generate a four-phase clock signal based on the synchronized data clock signal SWCK. The four-phase clock may include a first phase clock signal WCK0, a second phase clock signal WCK90, a third phase clock signal WCK180, and a fourth phase clock signal WCK270.

Phases of the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 may be different from one another. For example, a phase of the first phase clock signal WCK0 may be the same as a phase of the synchronized data clock signal SWCK. A phase of the second phase clock signal WCK90 may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as <NUM> degrees. A phase of the third phase clock signal WCK180 may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as <NUM> degrees. A phase of the fourth phase clock signal WCK270 may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as <NUM> degrees.

The first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 may be used to process different data. For example, when processing of a data stream including first to fourth data is requested, the memory device 200d may process the first data of the data stream based on the first phase clock signal WCK0. The memory device 200d may process the second data of the data stream based on the second phase clock signal WCK90. The memory device 200d may process the third data of the data stream based on the third phase clock signal WCK180. The memory device 200d may process the fourth data of the data stream based on the fourth phase clock signal WCK270.

<FIG> is a timing diagram illustrating data clock signals and a data signal of <FIG>, according to an embodiment of the present disclosure. Referring to <FIG>, waveforms of WCK_t, WCK_c, WCK0, WCK90, WCK180, WCK270, and DQ are illustrated by way of example. In <FIG>, a horizontal axis represents a time. WCK_t and WCK_c may correspond to the data clock signal WCK or the synchronized data clock signal SWCK of <FIG>. WCK0, WCK90, WCK180, and WCK270 may correspond to the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 of <FIG>, respectively. DQ may correspond to data DQ for a write operation of <FIG> or data DQ for a read operation of <FIG>. DQ may indicate a data stream including a plurality of data D1 to D10.

Referring to <FIG> and <FIG>, the memory device 200d may generate the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 based on the synchronized data clock signal SWCK. The first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 may have phase differences of <NUM> degrees, <NUM> degrees, <NUM> degrees, and <NUM> degrees with respect to the synchronized data clock signal SWCK. Cycles (or periods) of the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270 may be the same. For example, a cycle may correspond to a time period from tp1f to tp5f.

At time tp1f, the memory device 200d may process the first data D1 of the data stream corresponding to the DQ in response to a rising edge of the first phase clock signal WCK0. The rising edge may mean that a logical state of a clock signal changes from logical low to logical high. At time tp2f, the memory device 200d may process the second data D2 of the data stream corresponding to the DQ in response to a rising edge of the second phase clock signal WCK90. At time tp3f, the memory device 200d may process the third data D3 of the data stream corresponding to the DQ in response to a rising edge of the third phase clock signal WCK180. At time tp4f, the memory device 200d may process the fourth data D4 of the data stream corresponding to the DQ in response to a rising edge of the fourth phase clock signal WCK270. At time tp5f, the memory device 200d may process the fifth data D5 of the data stream corresponding to the DQ in response to a rising edge of the first phase clock signal WCK0 and the process repeats for each of the remaining data D6 to D10 using the relevant phase clock signals.

<FIG> is a timing diagram illustrating data streams that are processed based on a data clock signal selectively extended, according to an embodiment of the present disclosure. A graph of data streams that are processed when a processing interval is longer than or equal to a reference interval is illustrated in <FIG>. Also, a graph of data streams that are processed when the processing interval is shorter than the reference interval is illustrated.

The processing interval may mean a time interval between processing commands (e.g., read commands or write commands). The reference interval may be a time interval being a reference for determining whether to extend synchronization of a data clock signal. In each time and each waveform, the meaning and a correspondence relationship of a memory device are similar to those described with reference to <FIG> and <FIG>, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, an electronic device may include a memory device and a memory controller controlling the memory device. The memory controller may include information about a time interval (i.e., a processing interval) between consecutive processing commands.

In an embodiment, when the processing interval is longer than or equal to the reference interval, the memory controller may determine that it is inefficient to extend the synchronization of the data clock signal. For example, when the processing interval is longer than or equal to the reference interval, the memory controller may determine that the extension of the synchronization of the data clock signal causes an increase in power consumption due to maintaining the synchronization of the data clock signal, which is less desirable than improving a data processing speed by omitting the CAS command.

In an embodiment, when the processing interval is shorter than the reference interval, the memory controller may determine that it is efficient to extend the synchronization of the data clock signal. For example, when the processing interval is shorter than the reference interval, the memory controller may determine that the extension of the synchronization of the data clock signal improves a data processing speed, which is more desirable than increasing power consumption due to maintaining the synchronization of the data clock signal.

In <FIG>, referring to an embodiment of a first processing interval, the memory device may determine a first write command at time tpra1 and may determine a second write command at time tpra2. A time interval from time tpra1 when the first write command is determined to time tpra2 when the second write command is determined may be referred to as a "first process interval". The memory controller may store information about the first process interval.

In an embodiment, the memory controller determines whether the first process interval is longer than or equal to the reference interval. When the first process interval is longer than or equal to the reference interval, it may be inefficient to extend the synchronization of the data clock signal. The memory device does not extend the synchronization of the data clock signal under control of the memory controller. For example, at time tp5, the memory device <NUM> terminates the synchronization of the data clock signal WCK. A time interval from tp5 to tp6r may be long. At time tp6r, the memory device may determine the CAS command. At time tp9r, the memory device may again perform the synchronization of the data clock signal WCK.

In <FIG>, referring to an embodiment of a second process interval, the memory device may determine the first write command at time tprb1 and may determine the second write command at time tprb2. A time interval from time tprb1 when the first write command is determined to time tprb2 when the second write command is determined may be referred to as a "second process interval". The memory controller may store information about the second process interval.

In an embodiment, the memory controller determines whether the second process interval is shorter than the reference interval. When the second process interval is shorter than the reference interval, it may be efficient to extend the synchronization of the data clock signal. The memory device may extend the synchronization of the data clock signal under control of the memory controller.

For example, the memory controller may generate a command (e.g., the CASL) that indicates initiation of the synchronization of the data clock signal and defines a clock section corresponding to the synchronization. Alternatively, the memory controller may generate a command including mode register setting information for changing the number of times of toggling of the data clock signal to the reference cycle count (or number). The number of times of toggling of the data clock signal therefore may be changed to the reference cycle count (or number). As such, the data clock signal may continuously toggle from time tp4 to time tp5r. For better understanding of the present disclosure, the processing interval may be illustrated as being between the first write command and the second write command, but the present disclosure is not limited thereto. For example, the first write command may be changed to a first read command, and the second write command may be changed to a second read command.

<FIG> is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure. An operating method of a memory device will be described with reference to <FIG>. The memory device may correspond to at least one of the memory device <NUM> of <FIG>, the memory device 200a of <FIG>, the memory device 200c of <FIG>, and the memory device 200d of <FIG>. The memory device may communicate with a memory controller.

In operation S110, the memory device may receive a command from the memory controller. The command may define a clock section that indicates initiation of synchronization of a data clock signal and corresponds to the synchronization. For example, the command may be the CASL being a defined command.

In an embodiment, the clock section defined by the command in operation S110 is longer than a clock section corresponding to the synchronization of the data clock signal, which is performed based on the CAS command in the LPDDR5.

In an embodiment, in operation S110, after receiving the command indicating the initiation of the synchronization of the data clock signal and defining the clock section, the memory device further receives a first processing command for processing a first data stream and a second processing command for processing a second data stream. For example, the first processing command may be a write command or a read command for the first data stream. The second processing command may be a write command or a read command for the second data stream. In an embodiment, a command received immediately before the second processing command is not the CAS and is not the CASL.

In operation S120, the memory device prepares toggling of the data clock signal during a preparation time period. In an embodiment, the preparation time period sequentially includes a first time period in which the data clock signal is in the don't care state, a second time period in which the data clock signal is maintained in a given logical state, and a third time period in which the data clock signal pre-toggles at a frequency lower than a reference frequency. The pre-toggling of the data clock signal may be performed by toggling the data clock signal at the frequency lower than the reference frequency.

In operation S130, the memory device processes the first data stream based on the data clock signal toggling at the reference frequency. In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fourth time period and then processes the first data stream. In an embodiment, the memory device generates a four-phase clock signal based on the data clock signal and processes the first data stream based on the four-phase clock signal.

In operation S140, the memory device processes the second data stream based on the data clock signal toggling at the reference frequency within the defined clock section. For example, unlike operation S130 in which the first data stream is processed, the second data stream may be processed within a time period where the synchronization of the data clock signal is extended by the CASL.

In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fifth time period and then processes the second data stream. In an embodiment, the memory device generates the four-phase clock signal based on the data clock signal and then processes the second data stream based on the four-phase clock signal. In this case, the four-phase clock signal may continuously toggle from when the first data stream is processed in operation S130 to when the second data stream is processed.

In an embodiment, the memory device processes a plurality of data streams through a plurality of memory ranks. For example, in operation S130, the memory device may process the first data stream through a first memory rank. In operation S140, the memory device may process the second data stream through a second memory rank. In this case, a time at which the processing of the second data stream starts may be earlier than a time at which the processing of the first data stream is completed.

<FIG> is a flowchart illustrating an operating method of a memory device according to some embodiments of the present disclosure. An operating method of a memory device will be described with reference to <FIG>. The memory device may correspond to at least one of the memory device <NUM> of <FIG>, the memory device 200b of <FIG>, the memory device 200c of <FIG>, and the memory device 200d of <FIG>. The memory device may communicate with a memory controller.

In operation S210, the memory device receives a first command and a second command from the memory controller. The first command includes mode register setting information. The second command indicates initiation of synchronization of a data clock signal. For example, the first command may include the mode register setting information for extending the synchronization of the data clock signal. The second command may be the CAS command in the LPDDR5.

In an embodiment, in operation S210, after receiving the first command and the second command, the memory device may further receive a first processing command for processing a first data stream and a second processing command for processing a second data stream. In an embodiment, a command received immediately before the second processing command is not the CAS and is not the CASL.

In operation S215, the memory device changes settings of a mode register based on the mode register setting information. For example, the memory device may decode the first command received in operation S210 to obtain the mode register setting information. Based on the mode register setting information, the memory device may determine the number of times that the data clock signal toggles with regard to the synchronization, as a reference cycle count (or number). In this case, the reference cycle count (or number) may be greater than a default cycle count (or number) by which the data clock signal toggles, which is defined in the LPDDR5.

In operation S220, the memory device prepares toggling of the data clock signal during a preparation time period. In an embodiment, the preparation time period sequentially includes a first time period in which the data clock signal is in the don't care state, a second time period in which the data clock signal is maintained in a given logical state, and a third time period in which the data clock signal pre-toggles at a frequency lower than a reference frequency.

In operation S230, the memory device processes the first data stream based on the data clock signal toggling at the reference frequency. In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fourth time period and then processes the first data stream. In an embodiment, the memory device generates a four-phase clock signal based on the data clock signal and processes the first data stream based on the four-phase clock signal.

In operation S240, the memory device processes the second data stream based on the data clock signal toggling at the reference frequency and the changed settings of the mode register. For example, unlike operation S230 in which the first data stream is processed, the second data stream may be processed within a time period that is extended based on the changed settings of the mode register.

In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fifth time period and then processes the second data stream. In an embodiment, the memory device generates the four-phase clock signal based on the data clock signal and processes the second data stream based on the four-phase clock signal. In an embodiment, the memory device processes a plurality of data streams through a plurality of memory ranks.

<FIG> is a flowchart illustrating an operating method of an electronic device according to an embodiment of the present disclosure. The operating method of the electronic device will be described with reference to <FIG>. The electronic device may include a memory controller and a memory device. The electronic device may correspond to at least one of the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, and an electronic device including the memory device 200d of <FIG>.

In operation S310, the memory controller of the electronic device issues a command. The command is for extending synchronization of a data clock signal. For example, the command may be the CASL being a defined command. Alternatively, the command may include mode register setting information for extending the synchronization of the data clock signal.

In operation S320, the memory device of the electronic device prepares a toggling of the data clock signal during a preparation time period. In operation S330, the memory device of the electronic device processes a first data stream based on the data clock signal toggling at the reference frequency. In operation S340, the memory device of the electronic device processes a second data stream based on the data clock signal toggling at the reference frequency. A time at which the second data stream is processed may be included in a synchronization period of the data clock signal that is extended based on the command in operation S310.

<FIG> is a flowchart illustrating an operating method of an electronic device according to an embodiment of the present disclosure. The operating method of the electronic device will be described with reference to <FIG>. The electronic device may include a memory controller and a memory device. The electronic device may correspond to at least one of the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, and an electronic device including the memory device 200d of <FIG>. As in the embodiment of <FIG>, the electronic device may compare a processing interval and a reference interval to determine whether to extend synchronization of a data clock signal.

In operation S410, the electronic device determines whether the processing interval is shorter than the reference interval. For example, a memory controller of the electronic device may determine whether a processing interval between a first processing command and a second processing command is shorter than the reference interval.

The first processing command may be a first read command for a first data stream or a first write command for the first data stream. The second processing command may be a second read command for a second data stream or a second write command for the second data stream. The reference interval may be a time interval being a reference for determining whether to extend the synchronization of the data clock signal.

When it is determined in operation S410 that the processing interval is shorter than the reference interval, the electronic device performs operation S415. In operation S415, the memory controller of the electronic device generates an extension command for extending the synchronization of the data clock signal.

In an embodiment, the extension command is a defined command (e.g., the CASL). For example, the defined command may indicate the initiation of the synchronization of the data clock signal and may define a clock section that corresponds to the synchronization.

In an embodiment, the extension command includes a mode register change command including mode register setting information and an initiation command (e.g., the CAS in the LPDDR5) indicating the initiation of the synchronization of the data clock signal.

In operation S420, the memory device of the electronic device prepares toggling of the data clock signal during a preparation time period, based on the extension command. In operation S430, the memory device processes the first data stream corresponding to the first processing command based on the data clock signal toggling at the reference frequency. In operation S440, the memory device of the electronic device processes the second data stream corresponding to the second processing command based on the data clock signal toggling at the reference frequency. In this case, the toggling of the data clock signal may be extended based on the extension command in operation S415, and the toggling of the data clock signal may be continuously maintained while both the first data stream and the second data stream are processed.

When it is determined in operation S410 that the processing interval is longer than or equal to the reference interval, the electronic device performs operation S450. In operation S450, the memory controller of the electronic device generates a first initiation command and a second initiation command. For example, the first initiation command may be a command indicating the initiation of the synchronization of the data clock signal for the purpose of processing the first processing command. The second initiation command may be a command indicating the initiation of the synchronization of the data clock signal for the purpose of processing the second processing command. In an embodiment, each of the first initiation command and the second initiation command are the CAS command in the LPDDR5.

In operation S460, the memory device of the electronic device processes the first data stream based on the first initiation command. For example, the memory device of the electronic device may process the first data stream corresponding to the first processing command based on the data clock signal toggling based on the first initiation command.

In an embodiment, operation S460 may include preparing, by the memory device, toggling of the data clock signal during a preparation time period based on the first initiation command, processing, by the memory device, the first data stream based on the data clock signal toggling at the reference frequency, and terminating, by the memory device, the toggling of the data clock signal after the processing of the first data stream (i.e., terminating the synchronization of the data clock signal).

In operation S470, the memory device of the electronic device processes the second data stream based on the second initiation command. For example, the memory device of the electronic device may process the second data stream corresponding to the second processing command based on the data clock signal toggling based on the second initiation command. In this case, unlike the case of processing the second data stream in operation S440, after toggling is terminated in operation S460, the data clock signal in operation S470 may again toggle based on the second initiation command.

In an embodiment, operation S470 include preparing, by the memory device, toggling of the data clock signal during a preparation time period based on the second initiation command, processing, by the memory device, the second data stream based on the data clock signal toggling at the reference frequency, and terminating, by the memory device, the toggling of the data clock signal after the processing of the second data stream (i.e., terminating the synchronization of the data clock signal).

<FIG> is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Referring to <FIG>, an electronic system <NUM> includes an electronic device <NUM>. The electronic device <NUM> may correspond to at least one of the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>, and an electronic device including the memory device 200d of <FIG>. An operating method of the electronic device <NUM> may correspond to the flowchart of <FIG>. The electronic device <NUM> may include the memory device <NUM>. An operating method of the memory device <NUM> may correspond to at least one of the flowchart of <FIG> and the flowchart of <FIG>.

The electronic system <NUM> may be a mobile system such as a mobile phone, a smartphone, a tablet PC, a wearable device, a health care device, or an Internet of things (IoT) device. However, the electronic system <NUM> is not limited to the mobile system. For example, the electronic system <NUM> may be a system such as a personal computer, a laptop, a server, a media player, or an automotive device such as a navigation device.

The electronic system <NUM> may include a main processor <NUM>, the electronic device <NUM>, and storage devices 1300a and 1300b, and may further include one or more of an optical input device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control overall operations of the electronic system <NUM>. For example, the main processor <NUM> may control operations of the remaining components of the electronic system <NUM> implementing the electronic system <NUM>. The main processor <NUM> may be implemented with a general-purpose processor, a special-purpose processor, or an application processor.

The main processor <NUM> may include one or more CPU cores <NUM>, and may further include a controller <NUM> for controlling the electronic device <NUM> and/or the storage devices 1300a and 1300b. In some embodiments, the main processor <NUM> may further include an accelerator <NUM> being a dedicated circuit for high-speed data computation such as artificial intelligence (AI) data computation. The accelerator <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU) and may be implemented with a separate chip physically independent of any other component of the main processor <NUM>.

The electronic device <NUM> may be a volatile memory such as a DRAM and/or an SRAM. The electronic device <NUM> may be implemented within the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may function as a nonvolatile storage device that stores data regardless of whether power is supplied, and may have a relatively high capacity compared to the electronic device <NUM>. The storage device 1300a may include a storage controller 1310a and a flash memory 1320a storing data under control of the storage controller 1310a, and the storage device 1300b may include a storage controller 1310b and a flash memory 1320b storing data under control of the storage controller 1310b. Each of the flash memories 1320a and 1320b being non-volatile memories may include a flash memory of a two-dimensional (2D) structure or a vertical not-AND V-NAND flash memory of a three-dimensional structure or may include a different kind of nonvolatile memory such as a phase-change random-access memory PRAM and/or a resistive random-access memory RRAM.

The storage devices 1300a and 1300b may be included in the electronic system <NUM> in a state of being physically separated from the main processor <NUM> or may be implemented within the same package as the main processor <NUM>. Also, the storage devices 1300a and 1300b may have a shape identical to that of a solid state drive (SSD) or a memory card so as to be removable from any other components of the electronic system <NUM> through an interface such as the connecting interface <NUM> to be described later. The storage devices 1300a and 1300b may include a device to which the standard such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) is applied, but is not limited thereto.

The optical input device <NUM> may photograph (or capture) a still image or a moving image and may include a camera, a camcorder, and/or a webcam.

The user input device <NUM> may receive various types of data input by a user of the electronic system <NUM> and may include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may detect various types of physical quantities capable of being obtained from the outside of the electronic system <NUM> and may convert the detected physical quantities to electrical signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device <NUM> may communicate with external devices of the electronic system <NUM> in compliance with various communication protocols. The communication device <NUM> may be implemented to include an antenna, a transceiver, and/or a MODEM.

The display <NUM> and the speaker <NUM> may each function as an output device that outputs, respectively, visual information and auditory information to the user of the electronic system <NUM>.

The power supplying device <NUM> may appropriately convert a power supplied from a battery (not illustrated) embedded in the electronic system <NUM> and/or an external power source so as to be supplied to each component of the electronic system <NUM>.

The connecting interface <NUM> may provide a connection between the electronic system <NUM> and an external device. The connecting interface <NUM> may be implemented with various interfaces such as an ATA (Advanced Technology Attachment) interface, an SATA (Serial ATA) interface, an e-SATA (external SATA) interface, an SCSI (Small Computer Small Interface) interface, an SAS (Serial Attached SCSI) interface, a PCI (Peripheral Component Interconnection) interface, a PCIe (PCI express) interface, an NVMe (NVM express) interface, an IEEE <NUM> interface, an USB (Universal Serial Bus) interface, an SD (Secure Digital) card interface, an MMC (Multi-Media Card) interface, an eMMC (embedded Multi-Media Card) interface, an UFS (Universal Flash Storage) interface, an eUFS (embedded Universal Flash Storage) interface, and a CF (Compact Flash) card interface.

According to at least one embodiment of the present disclosure, an operating method of a memory device for extending synchronization of a data clock signal, and an operating method of an electronic device including the memory device are provided.

Also, according to at least one embodiment of the present disclosure, since synchronization of a data clock signal is extended based on a defined command or a setting change of a mode register, a memory device is provided that is capable of skipping additional synchronization of the data clock signal and improving a data processing speed.

Claim 1:
An operating method of a system comprising a memory device (<NUM>) and a memory controller (<NUM>), the memory device (<NUM>) in communication with the memory controller (<NUM>), the method comprising:
at the memory controller (<NUM>):
including information about a processing interval between consecutive processing commands;
determining whether a first processing interval between a command (read/write) for processing the first data stream and a command (read/write) for processing the second data stream is shorter than a reference interval; and
when it is determined that the first processing interval is shorter than the reference interval, outputting a first command (CASL) to the memory device (<NUM>); and
at the memory device (<NUM>):
receiving the first command (CASL) from the memory controller (<NUM>), the first command (CMD) indicating initiation of synchronization of a data clock signal (WCK) with a clock signal (CK) and defining a period (tWCK_SYNC) of a first clock section corresponding to the synchronization;
preparing a toggling of the data clock signal (WCK) during a preparation time period (tSYNC_Prepare);
processing a first data stream based on the data clock signal (WCK) toggling at a reference frequency (tWCK_Toggle); and
processing a second data stream based on the data clock signal (WCK) toggling at the reference frequency (tWCK Toggle) during the period (tWCK_SYNC) of the first clock section such that the toggling of the data clock signal (tWCK_Toggle) is maintained from when the first data stream is processed to when the second data stream is processed.