Patent Description:
A power semiconductor module is a semiconductor device that implements a circuit switching function, and is usually packaged by power semiconductor chips bridged by using a specific circuit. The power semiconductor chip usually includes an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a diode (Diode), a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a thyristor, a triode, and the like. The power semiconductor module is a core component of a motor driver (Motor Control Unit, MCU) and a most important heat emitting component. A heat dissipation capability of a package of the power semiconductor module plays a decisive role in a performance parameter index of a product.

Currently, the package of the power semiconductor module is divided into two structures: single side cooling and double side cooling. A difference between the two structures mainly lies in whether heat is unidirectionally transferred mainly from a single surface of the device to a cooling medium or bidirectionally transferred from two surfaces of the device to the cooling medium. Under a same process condition, the double side cooling package has a stronger heat dissipation capability, which helps bring performance of the power semiconductor chip into full play, improve product power density, and reduce product costs. For the power semiconductor module with the double side cooling package, the power semiconductor package is usually placed between two heat sinks, and a thermal conductive interface material (thermal conductive silicone grease, a graphite film, silica gel, a phase change material, and the like are commonly used in the industry) is disposed between the power semiconductor package and the heat sinks, and the two heat sinks are pressed and connected by using a mechanical structure (such as screws and bolts), to clamp the power semiconductor package and the thermal conductive interface material.

However, it is difficult to ensure uniform stress on all parts of the power semiconductor module by using the mechanical structure to press the heat sinks, so that the power semiconductor module may be damaged due to stress generated by the power semiconductor module in a process of assembling the entire motor driver, and the entire motor driver is scrapped. In addition, thermal conductive silicone grease is easy to dry and fall off after being used for a period of time, and the heat dissipation capability of the power semiconductor module is reduced. <CIT> discloses a thermal conductive layer disposed between a power semiconductor package and a heat sink. <CIT> discloses a double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies.

<CIT> discloses a semiconductor device having a first heat sink, a second heat sink, a semiconductor element, a first hollow tube, and a sealing material.

<CIT> discloses a laminated double-sided liquid cooling radiator for a new energy automobile inverter.

This application provides a power semiconductor module and a manufacturing method thereof, a motor driver, a powertrain, and a vehicle. A solid-state thermal conductive layer that has a fastening function and is not easy to fall off is formed between a heat sink and a power semiconductor package, so that all parts of the power semiconductor module are subject to uniform stress, and a risk of damage caused by stress generated by the power semiconductor module in a process of assembling the entire motor driver is reduced. In addition, integrated processing of the power semiconductor package and the heat sink and helium inspection of the power semiconductor module can be implemented before the entire motor driver is assembled, thereby avoiding a risk of scrapping the entire motor driver due to water leakage of the heat sink during a test of the entire motor driver.

According to a first aspect, an embodiment of this application provides a power semiconductor module in accordance with appended claim <NUM>.

The thermal conductive layer is configured as the thermal conductive material having metal bonding wires on a surface, so that bonding (bond) connections are implemented between the metal bonding wires of the thermal conductive layer and the heat sink and between the metal bonding wires of the thermal conductive layer and the power semiconductor package through heating and pressing, and binding force having molecular bonding force is formed between the heat sink and the thermal conductive layer and between the power semiconductor package and the thermal conductive layer. In addition, integrated processing of the power semiconductor package and the heat sink and helium inspection of the power semiconductor module can be implemented, so that a defective product, that is, a heat sink with air leakage, can be screened out in advance, and a qualified power semiconductor module can be directly applied to the assembly of the entire motor driver. This improves an automation level and a processing speed of the assembly of the entire motor driver, improves a yield of secondary processing of the entire motor driver, and avoids a risk of scrapping the entire motor driver due to water leakage of the heat sink during a helium test of the entire motor driver.

In a possible implementation of the first aspect, the binding force having molecular bonding force or embedding force is formed between the thermal conductive layer and the heat sink, and between the thermal conductive layer and the power semiconductor package.

The molecular bonding force or the embedding force is strong mutual binding force, and the molecular bonding force or the embedding force formed between the thermal conductive layer and the heat sink and between the thermal conductive layer and the power semiconductor package can firmly fasten the heat sink to the power semiconductor package.

The thermal conductive layer includes a metal thermal conductive sheet and the metal bonding wires disposed on a surface of the metal thermal conductive sheet.

In a possible implementation of the first aspect, the metal thermal conductive sheet is a copper foil, an aluminum foil, a silver foil, or a gold leaf, and the metal bonding wire is a nano copper wire, a nano aluminum wire, a nano silver wire, or a nano gold wire.

The metal bonding wires and a copper layer or an aluminum layer on surfaces of the heat sink and the power semiconductor package are heated and pressed, to form molecular bonding force for intermetallic fusion, which can firmly fasten the heat sink to the power semiconductor package. In addition, the nano copper wire, the nano aluminum wire, the nano silver wire, the nano gold wire, the copper foil, the aluminum foil, the silver foil or the gold leaf all have good heat conductivity, and can greatly improve a heat dissipation capability of the power semiconductor module.

In a possible implementation of the first aspect, the thermal conductive layer further includes thermal conductive adhesive, and the thermal conductive adhesive is distributed in a gap between adjacent metal bonding wires.

The thermal conductive adhesive is disposed to closely adhere the thermal conductive layer to the heat sink and the power semiconductor package. In this way, when the heat sink, the power semiconductor package, and the thermal conductive layer are fastened under conditions of heating and pressing, under the action of the thermal conductive adhesive, good fastening effect can be achieved between the heat sink and the thermal conductive layer and between the power semiconductor package and the thermal conductive layer under process conditions of a lower temperature and lower pressure. Therefore, the thermal conductive adhesive is disposed, so that the temperature and pressure for performing heating and pressing processing on the heat sink, the power semiconductor package, and the thermal conductive layer are reduced, which helps improve a production yield of the process.

In a possible implementation of the first aspect, there are two heat sinks, the two heat sinks are respectively a first heat sink and a second heat sink that are opposite to each other, the power semiconductor package is disposed between the first heat sink and the second heat sink, and the thermal conductive layer is disposed between the power semiconductor package and the first heat sink and between the power semiconductor package and the second heat sink.

The power semiconductor package is disposed between the first heat sink and the second heat sink to form the power semiconductor module with a double side cooling structure, and heat can be bidirectionally transferred from two surfaces of the power semiconductor package to the first heat sink and the second heat sink. Compared with a single side cooling structure, the double side cooling structure has a stronger heat dissipation capability under a same process condition, which helps bring performance of a power semiconductor chip into full play, improve product power density, and reduce product costs.

In a possible implementation of the first aspect, one end of the first heat sink and one end of the second heat sink are connected by using a connecting plate, and the other end of the first heat sink and the other end of the second heat sink are connected by using a fastener.

A heat dissipation structure formed by connecting one end of the first heat sink and one end of the second heat sink by using the connecting plate, and by connecting the other end of the first heat sink and the other end of the second heat sink by using the fastener is applicable to a heat dissipation manner in which heat dissipation water channels are connected in series.

Alternatively, two ends of the first heat sink and the second heat sink are connected by using a connecting pipe, and two ends of the first heat sink and the second heat sink are connected by using a connecting pipe.

A heat dissipation structure formed by separately connecting one end of the first heat sink and one end of the second heat sink and the other end of the first heat sink and the other end of the second heat sink by using the connecting pipes is applicable to a heat dissipation manner in which the heat dissipation water channels are connected in parallel.

In a possible implementation of the first aspect, a heat dissipation water channel is disposed inside the first heat sink and a heat dissipation water channel is disposed inside the second heat sink, the heat dissipation water channel in the first heat sink and the heat dissipation water channel in the second heat sink are connected in series by using the connecting plate, and a water inlet and a water outlet that communicate with the heat dissipation water channels are respectively disposed at the other end of the first heat sink and the other end of the second heat sink.

The heat dissipation water channel inside the first heat sink communicates with the heat dissipation water channel inside the second heat sink through a heat dissipation water channel inside the connecting plate, to form a heat dissipation structure in which the heat dissipation water channels are connected in series. The water inlet and the water outlet are located on a same side of the heat sinks, and a coolant enters the heat dissipation water channel inside the first heat sink from the water inlet to absorb heat of the first heat sink. Then, the coolant flows into the heat dissipation water channel of the second heat sink through the heat dissipation water channel in the connecting plate to absorb heat of the second heat sink, and finally flows out of the water outlet to take away all the heat.

Alternatively, a heat dissipation water channel is disposed inside the first heat sink and a heat dissipation water channel is disposed inside the second heat sink, the heat dissipation water channel in the first heat sink and the heat dissipation water channel in the second heat sink are connected in parallel by using the connecting pipes, and a water inlet is disposed at one end of the first heat sink, and a water outlet is disposed at one end that is of the second heat sink and that is away from the water inlet.

The heat dissipation water channel inside the first heat sink communicates with the heat dissipation water channel inside the second heat sink by using the connecting pipes located between the first heat sink and the second heat sink, and the connecting pipes are located at two ends of the two heat sinks, to form a heat dissipation structure in which the heat dissipation water channels are connected in parallel. The water inlet and the water outlet are respectively located at two sides of the heat sinks, the coolant enters the heat dissipation water channel inside the first heat sink from the water inlet, a part of the coolant flows along the heat dissipation water channel to absorb the heat of the first heat sink, and enters the water outlet by using the connecting pipe adjacent to the water outlet side to take away the heat. The other part of the coolant enters the heat dissipation water channel inside the second heat sink by using the connecting pipe adjacent to the water inlet side, flows along the heat dissipation water channel to absorb the heat of the second heat sink, and then enters the water outlet to take away the heat.

In a possible implementation of the first aspect, each power semiconductor package at least includes a first substrate, a second substrate, and at least one chip, and the chip is fastened between the first substrate and the second substrate; and the at least one chip is electrically connected to the first substrate and the second substrate. In this way, a circuit is formed between the chip and the first substrate, and between the chip and the second substrate.

The thermal conductive layer is disposed between the heat sink and the first substrate and/or between the heat sink and the second substrate, and is configured to transfer heat generated by the power semiconductor package to the heat sink.

In a possible implementation of the first aspect, the chip includes an IGBT chip and a diode chip.

Alternatively, the chip includes a silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET).

In a possible implementation of the first aspect, the power semiconductor package further includes at least one conductive pad, and the conductive pad conducts electricity and supports the first substrate and the second substrate.

The conductive pad is located between the chip and the first substrate; and two ends of the conductive pad are respectively connected to the chip and the first substrate by using conductive connecting layers.

In a possible implementation of the first aspect, the first substrate has a first conductive area and a second conductive area that are insulated from each other and arranged side by side.

The second substrate has a third conductive area and a fourth conductive area that are insulated from each other and arranged side by side, the first conductive area is opposite to the third conductive area, and the second conductive area is opposite to the fourth conductive area.

A part of the chip is located between the first conductive area and the third conductive area, and a part of the chip is located between the second conductive area and the fourth conductive area.

In addition, the first conductive area is connected to the fourth conductive area, or the second conductive area is connected to the third conductive area.

In this way, the first conductive area and the third conductive area are connected by using the chip, the second conductive area and the fourth conductive area are connected by using the chip, and the first conductive area and the fourth conductive area are connected, so that the third conductive area, the first conductive area, the fourth conductive area, and the second conductive area are connected.

Alternatively, the second conductive area is connected to the third conductive area, so that the first conductive area, the third conductive area, the second conductive area, and the fourth conductive area form a circuit.

In a possible implementation of the first aspect, both the first substrate and the second substrate are conductive plates.

In addition, the first substrate includes a first conductive plate and a second conductive plate that are insulated from each other and arranged side by side, the first conductive plate has the first conductive area, and the second conductive plate has the second conductive area.

The second substrate includes a third conductive plate and a fourth conductive plate that are insulated from each other and arranged side by side, the third conductive plate has the third conductive area, and the fourth conductive plate has the fourth conductive area.

In addition, the heat sink is disposed to be insulated from the conductive plate, to avoid a connection between the conductive plate and the heat sink.

In a possible implementation of the first aspect, the first substrate includes a first conductive layer and a first insulation plate, and the first conductive layer is located on a surface that is of the first insulation plate and that faces the chip.

The second substrate includes a second conductive layer and a second insulation plate, and the second conductive layer is located on a surface that is of the second insulation plate and that faces the chip.

In addition, the first conductive layer at least includes the first conductive area and the second conductive area, and the second conductive layer at least includes the third conductive area and the fourth conductive area.

The first insulation plate and the second insulation plate are respectively configured to prevent the first conductive layer and the second conductive layer from being connected to the heat sink.

In a possible implementation of the first aspect, the first substrate further includes a first copper layer, and the first copper layer plays a role in protection and heat conduction. The first copper layer is located on a surface that is of the first insulation plate and that faces the thermal conductive layer, and the first copper layer is configured to protect the first insulation plate, prevents the first insulation plate from breaking, and has a heat conduction function.

The second substrate further includes a second copper layer, and the second copper layer plays a role in protection and heat conduction. The second copper layer is located on a surface that is of the second insulation plate and that faces the thermal conductive layer, and the second copper layer is configured to protect the second insulation plate, prevents the second insulation plate from breaking, and has a heat conduction function.

The thermal conductive layer is disposed between the heat sink and the first copper layer and/or between the heat sink and the second copper layer.

In a possible implementation of the first aspect, the power semiconductor package further includes a wiring terminal, one end of the wiring terminal has a first terminal and a second terminal, one of the first terminal and the second terminal is electrically connected to the first conductive area, and the other of the first terminal and the second terminal is electrically connected to the fourth conductive area, so that the first conductive area is connected to the fourth conductive area.

Alternatively, one of the first terminal and the second terminal is electrically connected to the second conductive area, and the other of the first terminal and the second terminal is electrically connected to the third conductive area, so that the second conductive area is connected to the third conductive area.

Alternatively, both the first terminal and the second terminal are electrically connected to the third conductive area or both the first terminal and the second terminal are electrically connected to the fourth conductive area.

In a possible implementation of the first aspect, the power semiconductor package further includes a first electrode terminal and a second electrode terminal, one of the first electrode terminal and the second electrode terminal is a positive terminal, and the other of the first electrode terminal and the second electrode terminal is a negative terminal.

One of the first electrode terminal and the second electrode terminal is electrically connected to the first conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the fourth conductive area.

Alternatively, one of the first electrode terminal and the second electrode terminal is electrically connected to the second conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the third conductive area.

In a possible implementation of the first aspect, the power semiconductor package further includes a first conductive column and a second conductive column, and the first conductive column and the second conductive column are separately located between the first substrate and the second substrate.

The second substrate further has a fifth conductive area, and the fifth conductive area is disposed to be insulated from both the third conductive area and the fourth conductive area.

Both the first terminal and the second terminal of the wiring terminal are electrically connected to the fourth conductive area, two ends of the first conductive column are electrically connected to the first conductive area and the fourth conductive area respectively, and two ends of the second conductive column are electrically connected to the second conductive area and the fifth conductive area respectively.

One of the first electrode terminal and the second electrode terminal is electrically connected to the third conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the fifth conductive area.

The third conductive area, the first conductive area, the fourth conductive area, the second conductive area, and the fifth conductive area form a circuit by using the first conductive column and the second conductive column, and form a conductive loop with the first electrode terminal and the second electrode terminal.

In a possible implementation of the first aspect, the power semiconductor package further includes a packaging layer, and the first substrate, the second substrate, and the at least one chip are located in the packaging layer. Components such as the first substrate, the second substrate, and the chip are fastened and sealed by using the packaging layer, so that the components form the power semiconductor package. At least a part of an area that is of the packaging layer and that is opposite to at least one of the first substrate and the second substrate is an exposed area, and a surface that is of the at least one of the first substrate and the second substrate and that faces the thermal conductive layer is exposed in the exposed area. In this way, blocking of the packaging layer is eliminated, and contact between the substrate and the thermal conductive layer is closer, which is beneficial to heat transfer.

In a possible implementation of the first aspect, the power semiconductor package further includes a signal terminal, one end of the signal terminal is located in the packaging layer and is electrically connected to the chip, and the other end of the signal terminal is located outside the packaging layer.

In a possible implementation of the first aspect, the power semiconductor package further includes a bonding wire, one end of the bonding wire is in a bonding connection to the chip, and the other end of the bonding wire is in a boding connection to the signal terminal, so that the chip is connected to the signal terminal.

Alternatively, a soldering pad is disposed at one end of the second substrate, the other end of the bonding wire is in a bonding connection to the soldering pad, and one end of the signal terminal is electrically connected to the soldering pad, so that the chip is electrically connected to the signal terminal.

Alternatively, a soldering pad is disposed at one end of the second substrate, the chip is electrically connected to the soldering pad, and one end of the signal terminal is electrically connected to the soldering pad, so that the chip is electrically connected to the signal terminal.

According to a second aspect, an embodiment of this application provides a motor driver, including a capacitor and at least one power semiconductor module described above, and an electrode terminal of the power semiconductor module is electrically connected to the capacitor.

According to a third aspect, an embodiment of this application provides a powertrain, including a motor and the motor driver connected to the motor.

According to a fourth aspect, an embodiment of this application provides a vehicle, including wheels, a motor, and the motor driver connected to the motor, and the motor is connected to the wheels by using a transmission component.

According to a fifth aspect, an embodiment of this application provides a method for manufacturing a power semiconductor module in accordance with appended claim <NUM>.

In a possible implementation of the fifth aspect, before the separately disposing an interface material on a top surface and/or a bottom surface of the power semiconductor package, the method further includes the following steps:.

The deoxidation treatment makes the top surface and the bottom surface of the power semiconductor package expose a metal element, and the metal plating layer formed on the surface that is of the heat sink and that faces the power semiconductor package can prevent generation of an oxidized layer, so that the metal bonding wires and metal materials on surfaces of the heat sink and the power semiconductor package are respectively bonded through heating and pressing, and binding force having molecular bonding force is separately formed between the interface material and the surface of the heat sink and between the interface material and the surface of the power semiconductor package.

If the metal plating layer is not applied to the surface that is of the heat sink and that faces the power semiconductor package, the deoxidation treatment may also be performed on the surface to expose the metal element. This can also ensure that the metal material can form, between the heat sink and the power semiconductor package, the solid-state thermal conductive layer having the molecular bonding force or embedding force.

Terms used in implementations of this application are merely used to explain specific embodiments of this application, but are not intended to limit this application.

In the conventional technology, for a power semiconductor module with a double side cooling package, the power semiconductor package is usually placed between two heat sinks, and the two heat sinks are pressed and connected by using a mechanical structure. However, a disadvantage of pressing the heat sinks by using the mechanical structure lies in that it is not easy to ensure that all positions of the power semiconductor module are subject to uniform stress. For example, when the heat sinks are fastened, by using a plurality of bolts distributed between the upper and lower heat sinks, to the power semiconductor module assembled by the power semiconductor package, fastening force at a position close to the bolt is usually greater than fastening force at a position far away from the bolt, and fastening force applied by bolts located in different positions cannot be ensured to be equal. In addition, it is difficult to ensure that fastening surfaces of the heat sinks and the power semiconductor package are completely flat, and coating thicknesses of a thermal conductive interface material may also be different. Therefore, stress is easily generated in a process of fastening the heat sinks and the power semiconductor package, and the power semiconductor module is easily damaged in a process of assembling an entire motor driver. In addition, to avoid a loss and a failure of the thermal conductive interface material, the power semiconductor module is usually assembled on site while the entire motor driver is assembled, so that assembly difficulty is great and processing efficiency is low, and the power semiconductor module cannot be inspected in advance. It is difficult to determine whether the power semiconductor module is damaged during assembly. If a water leakage occurs in the heat sink of the power semiconductor module due to damage during a test of the entire motor driver, there is a risk that the entire motor driver is scrapped.

Based on this, embodiments of this application provide a power semiconductor module, a motor driver, a powertrain, and a method for manufacturing a power semiconductor module. A thermal conductive material having metal bonding wires on a surface is used in the power semiconductor module provided in this application, and a solid-state thermal conductive layer that has a fastening function and is not easy to fall off is formed between a heat sink and a power semiconductor package. The power semiconductor package and the heat sink are fastened by using the solid-state thermal conductive layer, so that all parts of the power semiconductor module are subject to uniform stress, and a risk of damage caused by stress generated by the power semiconductor module in a process of assembling the entire motor driver is reduced. In addition, integrated processing of the power semiconductor package and the heat sink and helium inspection of the power semiconductor module can be implemented before the entire motor driver is assembled, and a qualified power semiconductor module is directly applied to the assembly of the entire motor driver. This avoids on-site assembly work of the power semiconductor module during the assembly of the entire motor driver, reduces a risk of scrapping the entire motor driver due to water leakage of the heat sink during a test of the entire motor driver and difficulty in assembling the entire motor driver, and improves an automation level and a processing speed of the assembly of the entire motor driver. The following describes a specific structure of the power semiconductor module by using different embodiments as examples.

As shown in <FIG>, an embodiment of this application provides a power semiconductor module. The power semiconductor module may include at least one heat sink <NUM>. For example, <FIG> includes two heat sinks: a first heat sink <NUM> and a second heat sink <NUM>. As shown in <FIG>, the power semiconductor module further includes at least one power semiconductor package <NUM>. For example, in <FIG>, there are three power semiconductor packages <NUM>, and the three power semiconductor packages <NUM> are spaced apart between the first heat sink <NUM> and the second heat sink <NUM> in an X direction in <FIG>. Terminals of each power semiconductor package <NUM> extend outward from between the first heat sink <NUM> and the second heat sink <NUM> in a Y direction and a -Y direction in <FIG>. Certainly, in some examples, a quantity of power semiconductor packages <NUM> includes but is not limited to three, and may also be two or more than three.

As shown in <FIG> and <FIG>, the power semiconductor module further includes a thermal conductive layer <NUM> (refer to <FIG>) located between the heat sink <NUM> and the power semiconductor package <NUM>. For example, in the power semiconductor module shown in <FIG>, as shown in <FIG>, in a Z direction are the second heat sink <NUM>, the thermal conductive layer <NUM>, the power semiconductor package <NUM>, the thermal conductive layer <NUM>, and the first heat sink <NUM> (as shown in <FIG>).

It should be noted that <FIG> is an exploded partial view of the power semiconductor module shown in <FIG> sectioned in the Y direction in <FIG>.

In this embodiment of this application, the thermal conductive layer <NUM> is a thermal conductive material having metal bonding wires <NUM> (refer to <FIG>) on a surface, Binding force having molecular bonding force or embedding force is separately formed between the power semiconductor package <NUM> and the thermal conductive layer <NUM> and between the heat sink <NUM> and the thermal conductive layer <NUM>, so that the power semiconductor package <NUM> and the heat sink <NUM> form the power semiconductor module.

The thermal conductive layer <NUM> is configured as the thermal conductive material having metal bonding wires <NUM> on a surface, so that bonding (bond) connections are implemented between the metal bonding wires <NUM> of the thermal conductive layer <NUM> and the heat sink <NUM> and between the metal bonding wires <NUM> of the thermal conductive layer <NUM> and the power semiconductor package <NUM> through heating and pressing, and the binding force having molecular bonding force is formed between the heat sink and the thermal conductive layer and between the power semiconductor package and the thermal conductive layer. In this way, the thermal conductive layer between the power semiconductor package and the heat sink has a fastening function and is not easy to fall off, so that stress between the heat sink <NUM> and the power semiconductor package <NUM> is uniform, and a risk of damage caused by stress generated by the power semiconductor module in a process of assembling an entire motor driver is reduced. In addition, integrated processing of the power semiconductor package <NUM> and the heat sink <NUM> and helium inspection of the power semiconductor module can be implemented, so that a qualified power semiconductor module can be directly applied to the assembly of the entire motor driver. This avoids on-site assembly work of the power semiconductor module during the assembly of the entire motor driver, improves an automation level and a processing speed of the assembly of the entire motor driver, and reduces a risk of scrapping the entire motor driver due to water leakage of the heat sink during a test of the entire motor driver.

In this embodiment of this application, the thermal conductive layer <NUM> is specifically described by using an example in which the thermal conductive layer <NUM> is the thermal conductive material having metal bonding wires <NUM> (refer to <FIG>) on a surface. For example, as shown in <FIG>, the thermal conductive layer <NUM> includes a metal thermal conductive sheet <NUM> and the metal bonding wires <NUM> disposed on surfaces of the metal thermal conductive sheet <NUM>. As shown in <FIG>, the metal bonding wires <NUM> are disposed on both the upper and lower surfaces of the metal thermal conductive sheet <NUM>. The metal bonding wires <NUM> are arranged vertically on the metal thermal conductive sheet <NUM>, and there may be a gap between adjacent metal bonding wires <NUM>.

When the thermal conductive layer <NUM> is located between the heat sink <NUM> and the power semiconductor package <NUM>, to implement the fastening function of the thermal conductive layer to the heat sink <NUM> and the power semiconductor package <NUM> separately, the heat sink <NUM> and the power semiconductor package <NUM> need to be processed under conditions of heating and pressing. Under the conditions of heating and pressing, the metal bonding wires <NUM> are pressed and are in bonding connections to a copper layer or an aluminum layer on surfaces of the heat sink <NUM> and the power semiconductor package <NUM>, so that metal in the metal bonding wires <NUM> diffuses into the copper layer or the aluminum layer on the surfaces of the heat sink <NUM> and the power semiconductor package <NUM>. In this way, the binding force having molecular bonding force is formed between the thermal conductive layer <NUM> and the heat sink <NUM> and between the thermal conductive layer <NUM> and the power semiconductor package <NUM>, and the heat sink <NUM> and the power semiconductor package <NUM> are firmly connected under the action of the thermal conductive layer <NUM>.

In this embodiment of this application, the metal thermal conductive sheet <NUM> may be a copper foil, an aluminum foil, a silver foil, or a gold leaf. Certainly, the metal thermal conductive sheet <NUM> may alternatively be another metal foil. The metal bonding wire <NUM> is a nano copper wire, a nano aluminum wire, a nano silver wire, or a nano gold wire. Certainly, the metal bonding wires <NUM> may alternatively be another nano metal wire. In this embodiment of this application, specifically, an example in which the metal thermal conductive sheet <NUM> is the copper foil and the metal bonding wire <NUM> is the nano copper wire is used for description.

When the metal thermal conductive sheet <NUM> is the copper foil, and the metal bonding wire <NUM> is the nano copper wire, the thermal conductive layer formed by the copper foil and the nano copper wire is also referred to as a nano hook-and-loop fastener. In this way, copper in the nano copper wire diffuses into the surfaces of the heat sink <NUM> and the power semiconductor package <NUM>, and forms molecular bonding force with strong binding force with the copper layer or the aluminum layer on the surfaces of the heat sink <NUM> and the power semiconductor package <NUM>, which can firmly fasten the heat sink <NUM> to the power semiconductor package <NUM>. In addition, both the copper foil and the nano copper wire have good heat conductivity, and can greatly improve a heat dissipation capability of the power semiconductor module.

When the metal bonding wires <NUM> are disposed on the metal thermal conductive sheet <NUM>, the metal bonding wires <NUM> may be grown on the metal thermal conductive sheet <NUM> by using a nano copper wire growth process. For example, in this embodiment of this application, when the metal bonding wire <NUM> is the nano copper wire, and when the metal thermal conductive sheet <NUM> is the copper foil, the nano copper wire may be grown on upper and lower surfaces of the copper foil by using a chemical vapor deposition method.

In this embodiment of this application, when the thermal conductive layer <NUM> is the thermal conductive material having metal bonding wires <NUM> (refer to <FIG>) on a surface, the heat sink <NUM> and the power semiconductor package <NUM> usually need to be placed at a high temperature and face high pressure applied, so that the metal bonding wires <NUM> are in the bonding connections to the copper layer or the aluminum layer on the surfaces of the heat sink <NUM> and the power semiconductor package <NUM>, thereby implementing good fastening effect between the heat sink <NUM> and the thermal conductive layer <NUM> and between the power semiconductor package <NUM> and the thermal conductive layer <NUM>.

However, the high temperature and high pressure make it more difficult to assemble the power semiconductor module. Therefore, in this embodiment of this application, to reduce the temperature and pressure required for combining the heat sink <NUM>, the power semiconductor package <NUM>, and the thermal conductive layer <NUM>, as shown in <FIG>, the thermal conductive layer <NUM> further includes thermal conductive adhesive <NUM>, and the thermal conductive adhesive <NUM> is distributed in a gap between adjacent metal bonding wires <NUM>. In this way, the thermal conductive adhesive <NUM> helps closely adhere the thermal conductive layer <NUM> to the heat sink <NUM> (for example, the first heat sink <NUM> and the second heat sink <NUM>) and the power semiconductor package <NUM>. In this way, when the heat sink <NUM>, the power semiconductor package <NUM>, and the thermal conductive layer <NUM> are fastened under the conditions of heating and pressing, under the action of the thermal conductive adhesive <NUM>, the good fastening effect can be achieved between the heat sink <NUM> and the thermal conductive layer <NUM> and between the power semiconductor package <NUM> and the thermal conductive layer <NUM> under process conditions of a lower temperature and lower pressure. Therefore, the thermal conductive adhesive is disposed, so that the temperature and pressure for performing heating and pressing processing on the heat sink <NUM>, the power semiconductor package <NUM>, and the thermal conductive layer <NUM> are reduced, which helps improve a yield of the process.

It should be noted that the thermal conductive adhesive <NUM> may be in a colloidal or liquid state. Therefore, when the thermal conductive adhesive <NUM> is distributed between the metal bonding wires <NUM>, the thermal conductive adhesive <NUM> may be in contact with the metal thermal conductive sheet <NUM>. Alternatively, as shown in <FIG>, when the heating or pressing processing is not performed, the thermal conductive adhesive <NUM> is distributed between adjacent metal bonding wires <NUM>, but is not in contact with the metal thermal conductive sheet <NUM>. When the thermal conductive layer <NUM>, the heat sink <NUM>, and the power semiconductor package <NUM> are heated or pressed, the thermal conductive adhesive <NUM> is in close contact with the metal thermal conductive sheet <NUM>, thereby implementing rapid heat transmission.

In this embodiment of this application, a type of the thermal conductive adhesive <NUM> is not limited, and any adhesive that has a heat conduction function and can be adhered to the heat sink <NUM> and the power semiconductor package <NUM> to implement fastening may be selected for use.

In this embodiment of this application, as shown in <FIG>, there may be two heat sinks <NUM>, and the two heat sinks <NUM> are respectively the first heat sink <NUM> and the second heat sink <NUM> that are opposite to each other. The power semiconductor package <NUM> is disposed between the first heat sink <NUM> and the second heat sink <NUM>, the thermal conductive layer <NUM> is disposed between the power semiconductor package <NUM> facing the first heat sink <NUM> and the first heat sink <NUM>, and the thermal conductive layer <NUM> is disposed between the power semiconductor package <NUM> facing the second heat sink <NUM> and the second heat sink <NUM>.

The power semiconductor package <NUM> is disposed between the first heat sink <NUM> and the second heat sink <NUM> to form the power semiconductor module with a double side cooling structure, and heat can be bidirectionally transferred from the two surfaces of the power semiconductor package <NUM> to the first heat sink <NUM> and the second heat sink <NUM>. Compared with a single side cooling structure, the double side cooling structure has a stronger heat dissipation capability under a same process condition, which helps bring performance of a power semiconductor chip into full play, improve product power density, and reduce product costs.

Certainly, in some examples, one heat sink <NUM> may also be disposed to cool a single side of the power semiconductor package <NUM>.

In this embodiment of this application, as shown in <FIG>, one end of the first heat sink <NUM> and one end of the second heat sink <NUM> are connected by using a connecting plate <NUM>, and the other end of the first heat sink <NUM> and the other end of the second heat sink <NUM> are connected by using a fastener. Certainly, in some examples, the other end of the first heat sink <NUM> and the other end of the second heat sink <NUM> may be connected without using a fastener.

In an implementation, as shown in <FIG>, a connected heat dissipation water channel <NUM> is disposed inside each of the first heat sink <NUM>, the second heat sink <NUM>, and the connecting plate <NUM>, and a water inlet <NUM> and a water outlet <NUM> that communicate with the heat dissipation water channels <NUM> are respectively disposed at the other end of the first heat sink <NUM> and the other end of the second heat sink <NUM>.

The heat dissipation water channel <NUM> inside the first heat sink <NUM> communicates with the heat dissipation water channel <NUM> inside the second heat sink <NUM> through the heat dissipation water channel (not shown) inside the connecting plate <NUM>, and the heat dissipation water channels <NUM> inside the first heat sink <NUM> and the second heat sink <NUM> form the heat dissipation water channels connected in series.

As shown in <FIG>, the water inlet <NUM> and the water outlet <NUM> may be located on a same side of the heat sinks <NUM>, and a coolant enters the heat dissipation water channel <NUM> inside the first heat sink <NUM> from the water inlet <NUM> to absorb heat of the first heat sink <NUM>. Then, the coolant flows into the heat dissipation water channel <NUM> of the second heat sink <NUM> through the heat dissipation water channel in the connecting plate <NUM> to absorb heat of the second heat sink <NUM>, and finally flows out of the water outlet <NUM> to take away all the heat.

It should be noted that, in this embodiment of this application, the water inlet <NUM> is disposed on the first heat sink <NUM>, and the water outlet <NUM> is disposed on the second heat sink <NUM>. Certainly, in some examples, the water inlet <NUM> may alternatively be disposed on the second heat sink <NUM>, and the water outlet <NUM> is disposed on the first heat sink <NUM>. In addition, positions of disposing the water inlet <NUM> and the water outlet <NUM> include but are not limited to the positions shown in <FIG>.

In an implementation, as shown in <FIG> and <FIG>, each power semiconductor package <NUM> includes at least a first substrate <NUM>, a second substrate <NUM>, and at least one chip. The chip may include an IGBT chip <NUM> and a diode chip <NUM>. Alternatively, in some examples, the chip may alternatively be a silicon (Si) metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) or a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET).

A circuit is formed among the IGBT chip <NUM>, the first substrate <NUM>, and the second substrate <NUM>, a circuit is formed among the diode chip <NUM>, the first substrate <NUM>, and the second substrate <NUM>, and a parallel circuit is formed between the IGBT chip <NUM> and the diode chip <NUM>.

In this embodiment of this application, the thermal conductive layer <NUM> is disposed between the heat sink <NUM> and the first substrate <NUM> and/or between the heat sink <NUM> and the second substrate <NUM>, and the thermal conductive layer <NUM> is configured to transfer heat generated by the power semiconductor package <NUM> to the heat sink <NUM>.

When the chip is the silicon metal-oxide-semiconductor field-effect transistor or the silicon carbide metal-oxide-semiconductor field-effect transistor, for disposing of the chip, refer to the manners of disposing the IGBT chip <NUM> and the diode chip <NUM>.

An example in which the chip includes the IGBT chip <NUM> and the diode chip <NUM> is mainly used for description below.

In an implementation, as shown in <FIG>, the power semiconductor package <NUM> further includes at least one conductive pad, and the conductive pad is configured to electrically connect the chip to the first substrate <NUM>. For example, as shown in <FIG>, the power semiconductor package <NUM> includes at least one first conductive pad <NUM> and at least one second conductive pad <NUM>, and the conductive pad conducts electricity and supports the first substrate <NUM> and the second substrate <NUM>.

The first conductive pad <NUM> is located between the IGBT chip <NUM> and the first substrate <NUM>, and two sides of the first conductive pad <NUM> are respectively connected to the IGBT chip <NUM> and the first substrate <NUM> by using conductive connecting layers <NUM>.

The second conductive pad <NUM> is located between the diode chip <NUM> and the first substrate <NUM>, and two sides of the second conductive pad <NUM> are respectively connected to the diode chip <NUM> and the first substrate <NUM> by using conductive connecting layers <NUM>.

In this embodiment of this application, the conductive connecting layer <NUM> is a solder layer or a sintering layer that has electricity conductivity.

In an implementation, as shown in <FIG> and <FIG>, the first substrate <NUM> has a first conductive area <NUM> and a second conductive area <NUM> that are insulated from each other and arranged side by side, the second substrate <NUM> has a third conductive area <NUM> and a fourth conductive area <NUM> that are insulated from each other and arranged side by side, and the first conductive area <NUM> is opposite to the third conductive area <NUM>, and the second conductive area <NUM> is opposite to the fourth conductive area <NUM>.

A part of the IGBT chip <NUM> and a part of the diode chip <NUM> are located between the first conductive area <NUM> and the third conductive area <NUM>, and the other part of the IGBT chip <NUM> and the other part of the diode chip <NUM> are located between the second conductive area <NUM> and the fourth conductive area <NUM>.

The first conductive area <NUM> and the third conductive area <NUM> are connected by using the IGBT chip <NUM> and the diode chip <NUM>, and the second conductive area <NUM> and the fourth conductive area <NUM> are connected by using the IGBT chip <NUM> and the diode chip <NUM>. To enable the first conductive area <NUM>, the second conductive area <NUM>, the third conductive area <NUM>, and the fourth conductive area <NUM> to be connected, the first conductive area <NUM> of the first substrate <NUM> is connected to the fourth conductive area <NUM> of the second substrate <NUM>. In this way, the third conductive area <NUM>, the first conductive area <NUM>, the fourth conductive area <NUM>, and the second conductive area <NUM> are connected. The IGBT chip <NUM> and the diode chip <NUM> are connected in parallel. In this way, after one of the conductive areas in the first substrate <NUM> is electrically connected to a positive electrode of an electrode terminal, and one of the conductive areas in the second substrate <NUM> is electrically connected to a negative electrode of an electrode terminal, the third conductive area <NUM>, the first conductive area <NUM>, the fourth conductive area <NUM>, and the second conductive area <NUM> form a loop with the two electrode terminals, and may simultaneously supply power to a plurality of IGBT chips and a plurality of diode chips <NUM>.

Alternatively, to enable the first conductive area <NUM>, the second conductive area <NUM>, the third conductive area <NUM>, and the fourth conductive area <NUM> to be connected, the second conductive area <NUM> and the third conductive area <NUM> may be connected, and the first conductive area <NUM>, the third conductive area <NUM>, the second conductive area <NUM>, and the fourth conductive area <NUM> may be connected.

In this embodiment of this application, specifically, an example in which the first conductive area <NUM> and the fourth conductive area <NUM> are connected is used for description. The connection manner between the first conductive area <NUM> and the fourth conductive area <NUM> is described in detail below.

In an implementation, as shown in <FIG>, the first substrate <NUM> includes a first conductive layer <NUM> and a first insulation plate <NUM>, and the first conductive layer <NUM> is located on a surface that is of the first insulation plate <NUM> and that faces the IGBT chip <NUM>.

The second substrate <NUM> includes a second conductive layer <NUM> and a second insulation plate <NUM>, and the second conductive layer <NUM> is located on a surface that is of the second insulation plate <NUM> and that faces the IGBT chip <NUM>.

The first conductive layer <NUM> at least includes the first conductive area <NUM> and the second conductive area <NUM>, and the second conductive layer <NUM> at least includes the third conductive area <NUM> and the fourth conductive area <NUM>.

The first insulation plate <NUM> and the second insulation plate <NUM> are respectively configured to prevent the first conductive layer <NUM> and the second conductive layer <NUM> from being connected to the heat sink <NUM>.

In an implementation, as shown in <FIG>, the first substrate <NUM> further includes a first copper layer <NUM>, and the first copper layer <NUM> plays a role in protection and heat conduction. The first copper layer <NUM> is located on a surface that is of the first insulation plate <NUM> and that faces the thermal conductive layer <NUM>. For example, as shown in <FIG>, the first insulation plate <NUM> is located between the first copper layer <NUM> and the first conductive layer <NUM>, and the first copper layer <NUM> is configured to protect the first insulation plate <NUM>, prevents the first insulation plate <NUM> from breaking, and has a heat conduction function.

The second substrate <NUM> further includes a second copper layer <NUM>, and the second copper layer <NUM> plays a role in protection and heat conduction. The second copper layer <NUM> is located on a surface that is of the second insulation plate and that faces the thermal conductive layer <NUM>. For example, as shown in <FIG>, the second insulation plate <NUM> is located between the second copper layer <NUM> and the second conductive layer <NUM>. The second copper layer <NUM> is configured to protect the second insulation plate <NUM>, prevents the second insulation plate <NUM> from breaking, and has a heat conduction function.

The second insulation plate <NUM> and the first insulation plate <NUM> may be made of ceramic materials. In this way, the first substrate <NUM> formed by the first insulation plate <NUM>, the first copper layer <NUM>, and the first conductive layer <NUM>, and the second substrate <NUM> formed by the second insulation plate <NUM>, the second copper layer <NUM>, and the second conductive layer <NUM> are both direct bonding copper (Direct Bonding Copper, DBC) substrates.

Certainly, materials of the second insulation plate <NUM> and the first insulation plate <NUM> include but are not limited to the ceramic materials, and may alternatively be plates made of other insulation materials.

The thermal conductive layer <NUM> is disposed between the heat sink <NUM> and the first copper layer <NUM> and/or between the heat sink <NUM> and the second copper layer <NUM>. For example, as shown in <FIG>, when there are two heat sinks <NUM>, the thermal conductive layer <NUM> is disposed between one heat sink <NUM> (for example, the first heat sink <NUM>) and the first copper layer <NUM>, and the thermal conductive layer <NUM> is also disposed between the other heat sink <NUM> (for example, the second heat sink <NUM>) and the second copper layer <NUM>. When there is one heat sink <NUM>, the thermal conductive layer <NUM> is disposed between the heat sink <NUM> and the first copper layer <NUM> or between the heat sink <NUM> and the second copper layer.

It should be noted that, when the first copper layer <NUM> and the second copper layer <NUM> are disposed, and when the thermal conductive layer <NUM> is the nano copper hook-and-loop fastener, the copper in the nano copper wire on the surface of the nano copper hook-and-loop fastener can diffuse into the first copper layer <NUM> and/or the second copper layer <NUM> and form molecular bonding force of Cu-Cu metallic bonding with copper in the first copper layer <NUM> and/or the second copper layer <NUM>. Therefore, stronger binding force between the thermal conductive layer <NUM> and the first copper layer <NUM> and/or between the thermal conductive layer <NUM> and the second copper layer <NUM> is obtained, and a problem that heat conduction effect is reduced by delamination between the thermal conductive layer <NUM> and the first substrate <NUM> and/or between the thermal conductive layer <NUM> and the second substrate <NUM> is not easy to occur.

In an implementation, as shown in <FIG>, the power semiconductor package <NUM> further includes a wiring terminal <NUM>, one end of the wiring terminal <NUM> has a first terminal <NUM> and a second terminal <NUM>, one of the first terminal <NUM> and the second terminal <NUM> is electrically connected to the first conductive area <NUM>, and the other of the first terminal <NUM> and the second terminal <NUM> is connected to the fourth conductive area <NUM>, so that the first conductive area <NUM> is connected to the fourth conductive area <NUM> by using the first terminal <NUM> and the second terminal <NUM> of the wiring terminal <NUM>.

Alternatively, one of the first terminal <NUM> and the second terminal <NUM> is electrically connected to the second conductive area <NUM>, and the other of the first terminal <NUM> and the second terminal <NUM> is electrically connected to the third conductive area <NUM>, so that the second conductive area <NUM> is connected to the third conductive area <NUM> by using the first terminal <NUM> and the second terminal <NUM> of the wiring terminal <NUM>.

In this embodiment of this application, specifically, an example in which the first terminal <NUM> is electrically connected to the first conductive area <NUM>, and the second terminal <NUM> is electrically connected to the fourth conductive area <NUM> is used for description.

In an implementation, as shown in <FIG>, the power semiconductor package <NUM> further includes a first electrode terminal <NUM> and a second electrode terminal <NUM>, one of the first electrode terminal <NUM> and the second electrode terminal <NUM> is a positive terminal, and the other of the first electrode terminal <NUM> and the second electrode terminal <NUM> is a negative terminal.

One of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the first conductive area <NUM>, and the other of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the fourth conductive area <NUM>.

Alternatively, one of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the second conductive area <NUM>, and the other of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the third conductive area <NUM>.

In this embodiment of this application, specifically, an example in which the first electrode terminal <NUM> is the positive terminal, and is electrically connected to the third conductive area <NUM>; and the second electrode terminal <NUM> is the negative terminal, and is electrically connected to the second conductive area <NUM> is used for description.

In an implementation, as shown in <FIG>, the power semiconductor package <NUM> further includes a packaging layer <NUM>, and the first substrate <NUM>, the second substrate <NUM>, at least one IGBT chip <NUM>, and at least one diode chip <NUM> are located in the packaging layer <NUM>. Components such as the first substrate <NUM>, the second substrate <NUM>, the IGBT chip <NUM>, and the diode chip <NUM> are packaged into a sealed overall structure by using the packaging layer <NUM>, so that the chips in the formed power semiconductor package <NUM> are not easily damaged by water vapor or liquid.

When the thermal conductive layer <NUM> uses the nano copper hook-and-loop fastener, to generate the molecular bonding force on a bonding surface between the thermal conductive layer <NUM> and the power semiconductor package <NUM>, surfaces that are of the first substrate <NUM> and the second substrate <NUM> and that face the thermal conductive layer <NUM> need to be exposed at the packaging layer <NUM>, so that the nano copper hook-and-loop fastener is enabled to be in contact with the copper layer on the surfaces of the first substrate <NUM> and the second substrate <NUM>. For example, as shown in <FIG>, at least a part of an area that is of the packaging layer <NUM> and that is opposite to the first substrate <NUM> and the second substrate <NUM> is an exposed area (for example, may be a hollow area), and the surfaces that are of the first substrate <NUM> and the second substrate <NUM> and that respectively face the thermal conductive layer <NUM> are exposed in the exposed area. In this way, blocking of the packaging layer <NUM> is eliminated, and the first substrate <NUM> and the second substrate <NUM> are respectively in direct contact with the thermal conductive layer <NUM>, which is beneficial to heat transfer and close contact with the thermal conductive layer <NUM>.

Certainly, in some examples, when there is one heat sink <NUM>, at least a part of a surface that is of the packaging layer <NUM> and that is opposite to the heat sink <NUM> may be set as the exposed area. For example, at least a part of an area that is of the first substrate <NUM> and that is opposite to the packaging layer <NUM> may be set as the exposed area, the thermal conductive layer is disposed between the first substrate <NUM> and the heat sink <NUM>, and an area that is of the packaging layer <NUM> and that is opposite to the second substrate <NUM> is a closed area.

It should be noted that structures of the power semiconductor module shown in <FIG> and <FIG> are partial structural views of the structures of the power semiconductor module. The packaging layer <NUM> is not shown in <FIG> and <FIG>. However, in an actual product, the packaging layer <NUM> of the power semiconductor module may be shown in <FIG>.

In this embodiment of this application, as shown in <FIG>, there may be two IGBT chips <NUM> and three diode chips <NUM> between the first conductive area <NUM> and the third conductive area <NUM> and between the second conductive area <NUM> and the fourth conductive area <NUM>. Certainly, in some examples, a quantity of IGBT chips <NUM> and a quantity of diode chips <NUM> include but are not limited to the foregoing quantities.

In an implementation, as shown in <FIG>, <FIG>, and <FIG>, the power semiconductor package <NUM> further includes a signal terminal <NUM>, one end of the signal terminal <NUM> is located in the packaging layer <NUM> and is electrically connected to the IGBT chip <NUM>, and the other end of the signal terminal <NUM> is located outside the packaging layer <NUM> (as shown in <FIG>).

In an implementation, as shown in <FIG> and <FIG>, the power semiconductor package <NUM> further includes a bonding wire <NUM>, and the bonding wire <NUM> may be, for example, a lead. A soldering pad <NUM> is disposed at one end of the second substrate <NUM>, one end of the bonding wire <NUM> is electrically connected to the soldering pad <NUM> in a bonding manner, and the other end of the bonding wire <NUM> may also be electrically connected to the IGBT chip <NUM> in a bonding manner. One end of the signal terminal <NUM> is electrically connected to the soldering pad <NUM>, so that the IGBT chip <NUM> is connected to the signal terminal <NUM>.

It should be noted that the bonding manner is an existing manner of connecting the metal wire to the soldering pad, and specifically, the metal wire is closely welded to the soldering pad by using heat, pressure, or ultrasonic energy. Certainly, in some other examples, the two ends of the bonding wire <NUM> may be electrically connected to the soldering pad <NUM> and the IGBT chip <NUM> in another manner, for example, the connection is performed by using conductive adhesive or through welding.

It should be noted that, as shown in <FIG>, the soldering pad <NUM> and the second conductive layer <NUM> of the second substrate <NUM> are disposed at a spacing, to ensure that the soldering pad <NUM> and the second conductive layer <NUM> of the second substrate <NUM> are insulated from each other.

<FIG> is a schematic diagram of another structure of a power semiconductor module according to an embodiment of this application.

A difference between this embodiment of this application and Embodiment <NUM> lies in that: In this embodiment of this application, as shown in <FIG>, two ends of the first heat sink <NUM> and the second heat sink <NUM> are connected through connecting pipes. For example, as shown in <FIG>, one end of the first heat sink <NUM> communicates with one end of the second heat sink <NUM> by using a connecting pipe 11b, and the other end of the first heat sink <NUM> communicates with one end of the second heat sink <NUM> by using a connecting pipe 11a. The heat dissipation water channel <NUM> (refer to <FIG>) is disposed both inside the first heat sink <NUM> and the second heat sink <NUM>, the heat dissipation water channels <NUM> in the first heat sink <NUM> and the second heat sink <NUM> are connected in parallel by using the connecting pipe 11a and the connecting pipe 11b, and the water inlet <NUM> is disposed at one end of the first heat sink <NUM>, and the water outlet <NUM> is disposed at one end that is of the second heat sink <NUM> and that is away from the water inlet <NUM>.

During cooling, as shown by arrows in <FIG>, a coolant enters the heat dissipation water channel <NUM> (as shown in <FIG>) inside the first heat sink <NUM> from the water inlet <NUM>, a part of the coolant flows along solid line arrows in <FIG> on the heat dissipation water channel <NUM> of the first heat sink <NUM> to absorb heat of the first heat sink <NUM>, and enters the water outlet <NUM> by using the connecting pipe 11a adjacent to the water outlet <NUM> side to take away the heat. The other part of the coolant enters the heat dissipation water channel <NUM> inside the second heat sink <NUM> along dashed line arrows in <FIG> by using the connecting pipe 11b adjacent to the water inlet <NUM> side, flows along the heat dissipation water channel <NUM> (as shown in <FIG>) of the second heat sink to absorb heat of the second heat sink <NUM>, and then enters the water outlet <NUM> to take away the heat.

In this way, the coolant in the first heat sink <NUM> cools one side of the power semiconductor package <NUM> and is discharged from the water outlet <NUM>, and a part of the coolant entering the water inlet <NUM> directly enters the second heat sink <NUM> to cool the other side of the power semiconductor package <NUM>. The heat dissipation water channels <NUM> in the two heat sinks are disposed in parallel by using the connecting pipe 11b and the connecting pipe 11a. In this way, good heat dissipation effect is implemented on the two sides of the power semiconductor package <NUM>, and a good heat dissipation capability of the power semiconductor module is ensured.

<FIG> is a schematic diagram of another structure of a power semiconductor module according to an embodiment of this application, and <FIG> is a schematic diagram of a sectional structure of a power semiconductor module obtained after the power semiconductor module in <FIG> is assembled.

A difference between this embodiment of this application and the foregoing embodiments lies in that: In the foregoing embodiments, the IGBT chip <NUM> and the diode chip <NUM> are assembled in a face-up manner, that is, front faces of the IGBT chip <NUM> and the diode chip <NUM> face upward. However, in this embodiment of this application, as shown <FIG> and <FIG>, the IGBT chip <NUM> and the diode chip <NUM> are assembled in a flip-chip manner, that is, the front faces of the IGBT chip <NUM> and the diode chip <NUM> face downwards. The soldering pad <NUM> is disposed at one end of the second substrate <NUM>, and as shown in <FIG>, the IGBT chip <NUM> is electrically connected to the soldering pad <NUM> (for example, electrically connected in a welding manner), that is, the IGBT chip <NUM> is not electrically connected to the soldering pad <NUM> by using the bonding wire <NUM> (as shown in <FIG>). One end of the signal terminal <NUM> is electrically connected to the soldering pad <NUM>, so that the IGBT chip <NUM> is finally connected to the signal terminal <NUM>.

In this embodiment of this application, the soldering pad <NUM> and the second conductive layer <NUM> of the second substrate <NUM> are disposed at a spacing, to ensure that the soldering pad <NUM> and the second conductive layer <NUM> of the second substrate <NUM> are disposed to be insulated from each other.

The manner of connecting the IGBT chip <NUM> to the first conductive pad <NUM> and the manner of connecting the diode chip <NUM> to the second conductive pad <NUM>, and another structure are the same as those in the foregoing embodiments. For details, refer to the foregoing embodiments, and details are not described in this embodiment.

<FIG> is a schematic diagram of another structure of a power semiconductor module according to an embodiment of this application, and <FIG> is a schematic diagram of a structure obtained after the parts in <FIG> are assembled.

A difference between this embodiment of this application and the foregoing embodiments lies in that: In this embodiment of this application, as shown in <FIG> and <FIG>, the power semiconductor package <NUM> further includes a first conductive column <NUM> and a second conductive column <NUM>, and the first conductive column <NUM> and the second conductive column <NUM> are separately located between the first substrate <NUM> and the second substrate <NUM>.

The second substrate <NUM> further has a fifth conductive area <NUM>, and as shown in <FIG> and <FIG>, the fifth conductive area <NUM> is disposed at a distance from the third conductive area <NUM> and the fourth conductive area <NUM>, to ensure that the fifth conductive area <NUM>, the third conductive area <NUM>, and the fourth conductive area <NUM> are disposed to be insulated from each other.

Both the first terminal <NUM> and the second terminal <NUM> of the wiring terminal <NUM> are electrically connected to the fourth conductive area <NUM>, two ends of the first conductive column <NUM> are electrically connected to the fourth conductive area <NUM> and the first conductive area <NUM> respectively, and two ends of the second conductive column <NUM> are electrically connected to the second conductive area <NUM> and the fifth conductive area <NUM> respectively. In this way, the first conductive area <NUM>, the second conductive area <NUM>, the third conductive area <NUM>, the fourth conductive area <NUM>, and the fifth conductive area <NUM> are connected by using the first conductive column <NUM> and the second conductive column <NUM>.

One of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the third conductive area <NUM>, and the other of the first electrode terminal <NUM> and the second electrode terminal <NUM> is electrically connected to the fifth conductive area <NUM>. For example, in <FIG>, the first electrode terminal <NUM> is electrically connected to the third conductive area <NUM>, and the second electrode terminal <NUM> is electrically connected to the fifth conductive area <NUM>.

The third conductive area <NUM>, the first conductive area <NUM>, the fourth conductive area <NUM>, the second conductive area <NUM>, and the fifth conductive area <NUM> are connected by using the first conductive column <NUM> and the second conductive column <NUM>, and form a conductive loop with the first electrode terminal <NUM> and the second electrode terminal <NUM>.

For another structure in this embodiment of this application, refer to the connection manner in the foregoing embodiments, and details are not described again in this embodiment of this application.

An embodiment of this application further provides a motor driver, including a capacitor and at least one power semiconductor module connected to the capacitor in any one of the foregoing embodiments. The capacitor is specifically electrically connected to the first electrode terminal <NUM> and the second electrode terminal <NUM> in the power semiconductor module. For a structure and a working principle of the power semiconductor module in this embodiment of this application, refer to the descriptions in the foregoing embodiments, and details are not described again in this embodiment of this application.

The motor driver provided in this embodiment of this application includes the power semiconductor module, so that a risk of damage caused by stress generated by the power semiconductor module in a process of assembling an entire motor driver is reduced. Integrated processing of a power semiconductor package and a heat sink and helium inspection of the power semiconductor module can be implemented before the entire motor driver is assembled, so that a defective product, that is, a heat sink with air leakage, can be screened out in advance. However, in the conventional technology, the power semiconductor package and the heat sink are usually mounted in the entire motor driver first, and then, helium detection is performed on the entire motor driver. In this case, if air leakage occurs in the heat sink, the entire motor driver is scrapped, which greatly increases costs. In this embodiment of this application, the helium detection may be performed on the power semiconductor module in advance. In this case, if air leakage occurs in the heat sink, only the power semiconductor module needs to be replaced, and the entire motor driver is not scrapped. Therefore, in this embodiment of this application, a secondary processing yield of the entire motor driver is improved.

An embodiment of this application further provides a powertrain, including a motor and the motor driver connected to the motor in Embodiment <NUM>. For a structure and a working principle of a power semiconductor module in the motor driver, refer to the descriptions in the foregoing embodiments, and details are not described again in this embodiment of this application.

The powertrain provided in this embodiment of this application includes the power semiconductor module, so that a risk of damage caused by stress generated by the power semiconductor module in a process of assembling an entire motor driver is reduced. Integrated processing of a power semiconductor package and a heat sink and helium inspection of the power semiconductor module can be implemented before the entire motor driver is assembled, thereby avoiding a risk of scrapping the entire motor driver due to water leakage of the heat sink during a test of the entire motor driver.

An embodiment of this application further provides a vehicle, including wheels, a motor, and the motor driver connected to the motor in Embodiment <NUM>, and the motor is connected to the wheels by using a transmission component.

In this embodiment of this application, the vehicle may be an electric vehicle/electric vehicle (EV), a pure electric vehicle/battery electric vehicle (PEV/BEV), a hybrid electric vehicle (HEV), a range extended electric vehicle (REEV), a plug-in hybrid electric vehicle (PHEV), a new energy vehicle (New Energy Vehicle), or the like.

For a structure and a working principle of a power semiconductor module in the motor driver, refer to the descriptions in the foregoing embodiments, and details are not described again in this embodiment of this application.

The vehicle provided in this embodiment of this application includes the power semiconductor module, so that a risk of damage caused by stress generated by the power semiconductor module in a process of assembling an entire motor driver is reduced. Integrated processing of a power semiconductor package and a heat sink and helium inspection of the power semiconductor module can be implemented before the entire motor driver is assembled, thereby avoiding a risk of scrapping the entire motor driver due to water leakage of the heat sink during a test of the entire motor driver.

As shown in <FIG>, an embodiment of this application further provides a method for manufacturing a power semiconductor module, and the method includes the following steps:.

For example, as shown in <FIG>, the interface material may be disposed on a top surface of the power semiconductor package <NUM>. The interface material is a thermal conductive material having metal bonding wires on a surface, so that the top surface of the power semiconductor package <NUM> and the heat sink <NUM> form an overall structure by using the interface material. Alternatively, the interface material may be disposed on a bottom surface of the power semiconductor package <NUM>, so that the bottom surface of the power semiconductor package <NUM> and the heat sink <NUM> form an overall structure by using the interface material. Alternatively, the interface material may be disposed on the top surface and the bottom surface of the power semiconductor package <NUM> separately, so that the top surface and the bottom surface of the power semiconductor package <NUM> and the heat sink <NUM> (for example, the first heat sink <NUM> and the second heat sink <NUM> in <FIG>) respectively form an overall structure by using the interface material.

S103: Press-fit, for preset time at a preset temperature and preset pressure, the power semiconductor package <NUM> on which the interface material is disposed with the heat sink <NUM>, to form the power semiconductor module, where the interface material forms a solid-state thermal conductive layer between power semiconductor package <NUM> and the heat sink <NUM>.

Before separately disposing the interface material on the top surface and the bottom surface of the power semiconductor package <NUM>, the method further includes the following steps:.

The deoxidation treatment makes the top surface and the bottom surface of the power semiconductor package <NUM> expose a metal element, and the metal plating layer formed on the surface that is of the heat sink <NUM> and that faces the power semiconductor package <NUM> can prevent generation of an oxidized layer, to enable a metal material to form, between the heat sink <NUM> and the power semiconductor package <NUM>, a solid-state thermal conductive layer having molecular bonding force.

If the metal plating layer is not applied to the surface that is of the heat sink <NUM> and that faces the power semiconductor package <NUM>, the deoxidation treatment may also be performed on the surface to expose the metal element. This can also ensure that the metal material can form, between the heat sink <NUM> and the power semiconductor package <NUM>, the solid-state thermal conductive layer having the molecular bonding force.

In the descriptions of embodiments of this application, it should be noted that, unless otherwise clearly specified and limited, terms "mounted", "connected", and "connection" should be understood in a broad sense. For example, the terms may be used for a fastened connection, may be an indirect connection through an intermediate medium, may be an internal connection between two elements, or an interaction relationship between two elements. For a person of ordinary skill in the art, specific meanings of the foregoing terms in embodiments of this application may be understood based on a specific situation.

Claim 1:
A power semiconductor module, comprising:
a power semiconductor package (<NUM>) and a first heat sink (<NUM>);
a thermal conductive layer (<NUM>) located between the first heat sink (<NUM>) and the power semiconductor package (<NUM>) to combine the power semiconductor package (<NUM>) and the first heat sink (<NUM>) to form the power semiconductor module;
wherein the thermal conductive layer (<NUM>) comprises a metal thermal conductive sheet (<NUM>) and metal bonding wires (<NUM>) are disposed on a surface of the metal thermal conductive sheet (<NUM>).