Patent Description:
Semiconductor memory devices include volatile memory devices and non-volatile memory devices. While read and write speeds of the volatile memory devices are high, the volatile memory devices may lose the stored contents when a power supply is turned off. In contrast, since the non-volatile memory devices retain the stored contents even when the power supply is turned off, the non-volatile memory devices are used to store the contents to be retained regardless of the presence or absence of the power supply.

For example, the volatile memory devices include one or more of a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like. The non-volatile memory devices retain the stored contents even when the power supply is turned off. For example, the non-volatile memory devices include one or more of a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like. The flash memory may be classified into a NOR type flash memory and a NAND type flash memory.

An initialization operation may be performed after the power supply is turned on the volatile memory device. When manufacturers use the volatile memory device by attaching the volatile memory device to a product, it is necessary/desirable to check the condition of the volatile memory device and perform debugging thereof. At this time, there is a need or desire for a real-time monitoring method for the volatile memory device in which the initialization operation has been performed. <CIT> discloses a nonvolatile semiconductor memory device. The semiconductor memory device can include a first memory cell array and a second memory cell array acting in parallel each other, the first memory cell array including a plurality of first blocks and the second memory cell array including a plurality of second blocks, and each of the blocks being an erase unit, a plurality of flag resistors configured to correspond to each of the first blocks and each of the second blocks, a flag data is capable of being written to the flag resistors by selecting block address, a control circuit reading out the flag data in the flag resistor corresponding to the first block and the flag data in the flag resistor corresponding to the second block in parallel fashion, a first counter resistor storing a counting value of the flag data in the flag resistors corresponding to the first blocks of the first memory cell array, and a second counter resistor storing a counting value of the flag data in the flag resistors corresponding to the second blocks of the second memory cell array.

According to an aspect of the present invention there is a memory storage device according to claim <NUM>.

According to an aspect of the present invention there is an operation method according to claim <NUM>.

Further preferred embodiments are provided in the dependent claims.

These and/or other aspects will become apparent and more readily appreciated from the following description of various example embodiments of the present disclosure, taken in conjunction with the accompanying drawings in which:.

Hereinafter, embodiments according to the technical idea of inventive concepts will be described referring to the accompanying drawings.

<FIG> is a block diagram of a memory storage device according to some example embodiments.

Referring to <FIG>, a memory storage device <NUM> may include a memory device <NUM> and a memory controller <NUM>.

The memory controller <NUM> may generally control the operation of the memory device <NUM>. For example, the memory controller <NUM> may control a data exchange between an external host and the memory device <NUM>. For example, the memory controller <NUM> may control the memory device <NUM> in response to a request from the host, and may write data and/or read the data accordingly. In some example embodiments, the memory controller <NUM> may be or may include a processor such as a central processing unit (CPU); however, example embodiments are not limited thereto.

The memory controller <NUM> and the memory device <NUM> may communicate with each other through a memory interface MEM I/F. Further, the memory controller <NUM> and the external host may communicate with each other through a host interface HOST I/F. For example, the memory controller <NUM> may mediate a signal between the memory device <NUM> and the host. The memory controller <NUM> may control the operation of the memory device <NUM> by applying a command CMD for controlling the memory device <NUM>. Here, the memory device <NUM> may include dynamic memory cells. For example, the memory device <NUM> may include one or more of a dynamic random access memory (DRAM), a double data rate <NUM> (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDR4) SDRAM, an LPDDR5 SDRAM, or the like. However, the example according to of inventive concepts are not limited thereto, and the memory device <NUM> may alternatively or additionally include a non-volatile memory device.

The memory controller <NUM> may transmit a clock signal CLK, a command CMD, an address ADDR, or the like to the memory device <NUM>. The memory controller <NUM> may provide the data DQ to the memory device <NUM> and may receive the data DQ from the memory device <NUM>. The memory device <NUM> may include a memory cell array <NUM> in which data DQ is stored, a control logic circuit <NUM>, a data I/O buffer <NUM>, and the like.

In some example embodiments, the memory controller <NUM> may include a processor <NUM>, an initialization circuit/module <NUM>, a read-only memory <NUM>, and a status indicating circuit/module <NUM>.

The processor <NUM> may generally control the operation of the memory controller <NUM>. For example, the processor <NUM> may process and output the data received from the host or the memory device <NUM>. Further, the processor <NUM> may read data from the read-only memory <NUM> and execute the program when the memory storage device <NUM> is powered on.

The initialization module <NUM> may perform the initialization operation on the memory storage device <NUM>. For example, when the memory storage device <NUM> is powered on, the initialization module <NUM> may perform specific, such as necessary and/or desirable operations before operating the memory storage device <NUM>. Alternatively or additionally, at least some functions of the initialization module <NUM> may be replaced by or performed by the processor <NUM>. The initialization module <NUM> may read data from the read-only memory <NUM> and may execute a program. For example, the initialization module <NUM> may perform the initialization operation in response to the power-on of the memory storage device <NUM>. The read-only memory <NUM> corresponds to or may include a non-volatile memory and may provide the stored data to the configurations of the memory controller <NUM>. Here, the data stored in the read-only memory <NUM> may correspond to the data generated and stored at the time of fabricating the memory controller <NUM>. The initialization module <NUM> may perform the initialization operation, using the data that is output from the read-only memory <NUM>. For example, the initialization operation may include one or more of a memory storage device reset operation, an impedance calibration operation, a mode register setting value write operation, a training operation, a DCM/DCA calibration operation, a write leveling operation, a read calibration operation, a write calibration operation, and the like. However, example embodiments of inventive concepts are not limited thereto, and the initialization operation may include more diverse types.

The status indicating module <NUM> may display and/or store and/or indicate the overall status of the memory storage device <NUM>. For example, the status indicating module <NUM> outputs a signal to the status of the memory storage device <NUM> in which the initialization operation is performed by the initialization module <NUM>. An external device may monitor the signal that is output from the status indicating module <NUM>. The status indicating module <NUM> may receive the signal from the initialization module <NUM>, and may output a status signal to the memory storage device <NUM> on the basis of the received signal. For example, the initialization module <NUM> may indicate the status of the memory storage device <NUM> in real time. In particular, the initialization module <NUM> may indicate the status of the memory storage device <NUM> of a result of performing the initialization operation. A more detailed description thereof will be given later.

<FIG> is a block diagram of the memory device of <FIG>.

Referring to <FIG>, the memory device <NUM> includes a control logic circuit <NUM>, an address register <NUM>, a bank control logic circuit <NUM>, a row address multiplexer <NUM>, a refresh counter <NUM>, a column address latch <NUM>, a row decoder <NUM>, a column decoder <NUM>, a memory cell array <NUM>, a sense amplifier <NUM>, an I/O gating circuit <NUM>, an ECC engine <NUM>, a data I/O buffer <NUM>, and the like.

The memory cell array <NUM> may include a plurality of bank arrays. The row decoder <NUM> may be connected to the plurality of bank arrays. The column decoder <NUM> may be connected to the plurality of bank arrays. The sense amplifier <NUM> may be connected to each of the plurality of bank arrays. The memory cell array <NUM> may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersection points between the word lines and the bit lines.

The address register <NUM> may be provided with the address ADDR from the memory controller <NUM>. The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR, a column address COL_ADDR, and the like. The address register <NUM> may provide the bank address BANK_ADDR to the bank control logic circuit <NUM>. The address register <NUM> may provide the row address ROW_ADDR to the row address multiplexer <NUM>. The address register <NUM> may provide the column address COL_ADDR to the column address latch <NUM>.

The bank control logic circuit <NUM> may generate a bank control signal in response to the bank address BANK_ADDR. The bank row decoder <NUM> may be activated in response to the bank control signal. Further, the column decoder <NUM> may be activated in response to the bank control signal corresponding to the bank address BANK_ADDR.

The row address multiplexer <NUM> may receive the row address ROW_ADDR from the address register <NUM>, and may receive the refresh row address REF_ADDR from the refresh counter <NUM>. The row address multiplexer <NUM> may select either the row address ROW_ADDR or the refresh row address REF_ADDR and may output the selected address to the row address RA. The row address RA may be transmitted to the row decoder <NUM>.

The refresh counter <NUM> may sequentially output the refresh row address REF_ADDR according to the control of the control logic circuit <NUM>.

The row decoder <NUM> activated by the bank control logic circuit <NUM> may decode the row address RA that is output from the row address multiplexer <NUM> and may activate the word line corresponding to the row address RA. For example, the row decoder <NUM> may apply a word line driving voltage to the word line corresponding to the row address RA.

The column address latch <NUM> may receive the column address COL_ADDR from the address register <NUM> and temporarily store the received column address COL_ADDR. The column address latch <NUM> may gradually increase the column address COL_ADDR received in a burst mode. The column address latch <NUM> may provide the column decoder <NUM> with the temporarily stored column address COL_ADDR and/or the gradually increased column address COL_ADDR.

Among the column decoders <NUM>, the column decoder <NUM> activated by the bank control logic circuit <NUM> may activate the sense amplifier <NUM> corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the corresponding I/O gating circuit <NUM>.

The I/O gating circuit <NUM> may include a circuit for gating the I/O data, an input data mask logic, read data latches for storing data that is output from the memory cell array <NUM>, and write drivers for writing data to the memory cell array <NUM>.

A code word CW that is read from the bank array of the memory cell array <NUM> may be sensed by the sense amplifier <NUM> corresponding to the bank array. Further, the code word CW may be stored in the read data latch. The code word CW stored in the read data latch may perform ECC decoding by the ECC engine <NUM>, and the data DQ subjected to the ECC decoding may be provided to the memory controller <NUM> through the data I/O buffer <NUM>.

The data I/O buffer <NUM> may provide the data DQ to the ECC engine <NUM> on the basis of the clock signal CLK in the write operation. The data I/O buffer <NUM> may provide the memory controller <NUM> with the data DQ provided from the ECC engine <NUM> on the basis of the clock signal CLK in the read operation.

Hereinafter, the status indicating module <NUM> according to inventive concepts will be described referring to <FIG>.

<FIG> is a block diagram of a memory controller according to some example embodiments. <FIG> is a diagram for explaining the status indicating module of <FIG>.

Referring to <FIG>, the memory controller <NUM> may include a host interface (HOST I/F), a processor <NUM>, an initialization module <NUM>, a read-only memory <NUM>, and a status indicating module <NUM>. The initialization module <NUM> may communicate with the processor <NUM> and the read-only memory <NUM>. The initialization module <NUM> may receive data from the read-only memory <NUM>, and may perform the initialization operation on the memory storage device <NUM>, using the received data. For example, the initialization module <NUM> may perform the initialization operation in response to the power-on or turn-on operation of the memory storage device <NUM>. The initialization module <NUM> may sequentially perform a plurality of initialization operations, using data. However, example embodiments are not limited thereto, and the initialization module <NUM> may perform a plurality of initialization operations in any order. Furthermore, although <FIG> illustrates some one-way connections between various components, this is for illustrative purposes only and example embodiments are not limited thereto. For example, any individual component in <FIG> may engage in one-way or two-way communication with any other component in <FIG>.

The status indicating module <NUM> may receive the signal from the initialization module <NUM>. The status indicating module <NUM> may indicate the status of the memory storage device <NUM>, using a signal including the result in which the initialization module <NUM> performs the initialization operation. For example, the status indicating module <NUM> may output the status of the memory storage device <NUM> in which the initialization operation is performed. The memory status information MSI of the memory storage device <NUM> that is output by the status indicating module <NUM> may be output through the post interface HOST I/F. The memory status information MSI may change in real time as the signal transmitted from the initialization module <NUM> changes.

Referring to <FIG>, the status indicating module <NUM> may include a plurality of transistors TR1 to TR8 and a plurality of resistors R1 to R8. Here, a plurality of resistors R1 to R8 may be connected in parallel. Furthermore, although eight transistors and eight resistors are illustrated, example embodiments are not limited thereto, and the number of transistors and/or resistors may be greater than or less than eight. Still further although <FIG> illustrates that the transistors are each NMOS transistors, example embodiments are not limited thereto, and one or more of the transistors may be PMOS transistors.

A first source/ drain of the first transistor TR1 is connected to a terminal voltage Vterm, and a second source/ drain is connected to one end of a first resistor R1. The other end of the first resistor R1 is connected to a node ND. A gate of the first transistor receives the first status parameter STP1. The first transistor TR1 operates on the basis of the first status parameter STP1. The first transistor TR1 is turned on, on the basis of the toggling of the first status parameter STP1.

The first status parameter STP1 may correspond to the signal transmitted from the initialization module <NUM>. The initialization module <NUM> may perform the first initialization operation in response to the power-on of the memory storage device <NUM>. When the status of the memory storage device <NUM> that has performed the first initialization operation is normal, the initialization module <NUM> may toggle the first status parameter STP1. For example, the initialization module <NUM> may convert the logic value of the first status parameter STP1 from "<NUM>" to "<NUM>". If the status of the memory storage device <NUM> that has performed the first initialization operation is not normal, the initialization module <NUM> may not toggle the first status parameter STP1. For example, the value of the first status parameter STP1 that is output from the initialization module <NUM> may be changed, depending on the status of the memory storage device <NUM> that has performed the first initialization operation. If the first status parameter STP1 is not toggled, the first transistor TR1 may be turned off, and a resistance value of the first resistor R1 in series with the first transistor TR1 that is monitored from the node ND may be large, e.g., infinite. If the first status parameter STP1 is toggled, the first transistor TR1 may be turned on, and the resistance value of the first resistor R1 monitored from the node ND may correspond to a first resistor value. For example, if the status of the memory storage device <NUM> that has performed the first initialization operation is normal, the resistance value of the first resistor R1 monitored from the node ND in series with the first transistor TR1 may be the first resistor value. Here, the memory status information MSI that is output from the node ND may include a resistance value of the first resistor R1.

In some example embodiments, the initialization operation of the memory storage device <NUM> performed by the initialization module <NUM> may be sequentially performed from the first initialization operation to another initialization operation, e.g., an eighth initialization operation. However, example embodiments are not limited thereto, and the first to eighth initialization operations may be performed in any order. As described below, for clarity it is assumed that the first to eighth initialization operations are sequentially performed.

Second to eighth transistors TR2 to TR8 may be arranged in parallel with the first transistor TR1. Further, the second to eighth resistors R2 to R8 may be arranged in parallel with the first resistor R1. The first to eighth resistors R1 to R8 are commonly connected to the node ND.

Gates of each of the second to eighth transistors TR2 to TR8 receive the respective second to eighth status parameters STP2 to STP8. The second to eighth transistors TR2 to TR8 operate on the basis of the second to eighth status parameters STP2 to STP8. Here, the second to eighth status parameters STP2 to STP8 may be toggled sequentially. However, when one of the second to eighth status parameters STP2 to STP8 is not toggled, the remaining status parameters may also not be toggled.

The second to eighth status parameters STP2 to STP8 may indicate the status of the memory storage device <NUM> in which the second to eighth initialization operations are performed. For example, when the status of the memory storage device <NUM> in which the second initialization operation is performed is normal, the second status parameter STP2 may be toggled, and when the status of the memory storage device <NUM> in which the second initialization operation is performed is not normal, the second status parameter STP2 may not be toggled.

The first source/drain of each of the second to eighth transistors TR2 to TR8 is connected to the terminal voltage Vterm. The second source/drain of each of the second to eighth transistors TR2 to TR8 is connected to one end of each of the second to eighth resistors R2 to R8. The other ends of the second to eighth resistors R2 to R8 is connected to the node ND.

Since a part of the second to eighth transistors TR2 to TR8 is turned on, the resistance value monitored between the terminal voltage Vterm and the node ND may include resistance values of the second to eighth resistors R2 to R8. For example, when the first and second transistors TR1 and TR2 are turned on, the resistance values monitored between the terminal voltage Vterm and the node ND may include the resistance values of the first and second resistors R1 and R2. In this case, the first resistor R1 and the second resistor R2 may be connected in parallel. For example, the memory status information MSI that is output from the node ND may correspond to the resistance values of the first resistor R1 and the second resistor R2 connected in parallel. The memory status information MSI may be an analog signal or a digital signal, and may correspond to a resistance between the terminal voltage Vterm. The equivalent resistance between the terminal voltage Vterm and the node ND may decrease depending on the status of the status parameters STP1 to STP8.

In summary, the status indicating module <NUM> may change the memory status information MSI including the resistance value that is output from the node ND on the basis of the plurality of status parameters STP1 to STP8 received from the initialization module <NUM>. For example, the status indicating module <NUM> may express the status of the memory storage device <NUM> subjected to the plurality of initialization operations as the resistance values of the plurality of resistors R1 to R8.

<FIG> is a diagram for explaining an example in which a test is performed on a memory storage device using the test apparatus.

Referring to <FIG>, a motherboard/main board MB may include a connecting pin CP and a test pin TP. The memory storage device <NUM> may also include the counterpart connecting pin CP and the test pin TP. The connecting pin CP and the test pin TP of the main board MB may be connected to correspond to the connecting pin CP and the test pin TP of the memory storage device <NUM>. Here, the memory storage device <NUM> and the main board MB may be connected by soldering; however, example embodiments are not limited thereto.

The test apparatus TA may be connected to the memory storage device <NUM> through the test pin TP of the main board MB. A probe PB of the test apparatus TA may be connected to the main board MB. The test apparatus TA may monitor the status of the memory storage device <NUM> in real time through the probe PB. For example, the signal including the status of the memory storage device <NUM> transmitted to the test apparatus TA may change with a change in the status of the memory storage device <NUM>. Here, the application processor may not be connected to the main board MB. For example, the memory storage device <NUM> may not communicate with the application processor, while the real-time monitoring is being performed by the test apparatus TA. However, example embodiments are not limited thereto.

<FIG> is a flowchart for explaining the test method of the memory storage device according to some example embodiments. <FIG> is a timing diagram of the operation of the memory storage device according to some example embodiments. <FIG> is a flowchart for explaining the test method of the memory storage device according to some example embodiments.

Referring to <FIG>, the main board MB and the memory storage device <NUM> may be connected (S500). As described referring to <FIG>, the main board MB and the memory storage device <NUM> may be connected through the connecting pin CP and the test pin TP.

The memory storage device <NUM> may be powered on and may perform the initialization operation (S501). The memory storage device <NUM> may be turned on, using the power supply voltage received from the main board MB. Further, in response to the power-on of the memory storage device <NUM>, the memory storage device <NUM> may perform a plurality of initialization operations. At this time, the initialization module <NUM> may output the status of the memory storage device <NUM> subjected to the plurality of initialization operations as the plurality of status parameters STP1 to STP8. For example, at least one of the plurality of status parameters STP1 to STP8 may be toggled depending on the status of the memory storage device <NUM>.

Zero or more of the plurality of transistors TR1 to TR8 may be turned on in response to the plurality of status parameters STP1 to STP8 (S502). For example, when the first status parameter STP1 is toggled, the first transistor TR1 may be turned on. As the first transistor TR1 is turned on, the first resistor R1 may be connected to the terminal voltage Vterm. However, when the second status parameter STP2 is not toggled, the second transistor TR2 may not be turned on. Accordingly, the second resistor R2 may not be connected to the terminal voltage Vterm.

The test apparatus TA may measure the resistance of the node ND (S503), e.g., the resistance of the node ND with respect to another node such as a ground node. As the plurality of transistors TR1 to TR8 are turned on or off, the resistance values monitored from the node ND may be changed. For example, the resistance values monitored from the node ND when the first and second status parameters STP1 and STP2 are toggled may be the resistance values of the first resistor R1 in parallel with the second resistor R2. For example, the resistance value monitored from the node ND may correspond to the resistance values of the first resistor R1 and the second resistor R2 connected in parallel. Accordingly, the test apparatus TA may check that the first and second initialization operations are performed normally, and may check that the third to eighth initialization operations are not performed normally. However, example embodiments inventive concepts are not limited thereto.

Subsequently, the status indicating module <NUM> may output the memory status information MSI (S504). Here, the memory status information MSI may include or correspond to a resistance value monitored from the node ND. Alternatively or additionally, the memory status information MSI may include information about changed resistance values. The test apparatus TA may perform debugging, using the memory status information MSI (S505). For example, the test apparatus TA may grasp a problematic initialization operation through the memory status information MSI and may take measures to normally perform the initialization operation. For example, the test apparatus TA may change the signal to be input to the memory storage device <NUM> and/or change a passive element connected to the memory storage device <NUM>. Even when communication is not performed through the application processor, efficient debugging may be performed, by monitoring the status of the memory storage device <NUM> through the test apparatus TA.

Referring to <FIG> and <FIG>, the first to eighth status parameters STP1 to SPT8 and the memory status information MSI may appear. Here, the first to eighth status parameters STP1 to SPT8 may be output from the initialization module <NUM>, and the memory status information MSI may be output from the status indicating module <NUM>.

Before a first time t1, the initialization module <NUM> may perform the first initialization operation on the memory storage device <NUM>. When the status of the memory storage device <NUM> that has performed the first initialization operation is normal, the first status parameter STP1 may be toggled. For example, the logic value of the first status parameter STP1 may be converted from "<NUM>" to "<NUM>" at the first time t1. Accordingly, the first transistor TR1 may be turned on, and the memory status information MSI may correspond to the resistance value of the first resistor R1 in a time interval between the first time t1 and a second time t2. However, in the time interval between the first time t1 and the second time t2, the second to eighth transistors TR2 to TR8 may be turned off.

More specifically, the initialization module <NUM> may determine whether the memory storage device <NUM> subjected to a nth initialization operation is normal (S510). When the memory storage device <NUM> subjected to the nth initialization operation is normal (S510-Y), the initialization module <NUM> may toggle an nth status parameter STPn (S511). When the memory storage device <NUM> subjected to the nth initialization operation is not normal (S510-Y), the initialization module <NUM> may not toggle the nth status parameter STPn (S511). For example, the initialization module <NUM> may toggle the first status parameter STP1 at the first time t1, but may not toggle the fourth status parameter STP4 at a fourth time t4. However, example embodiments of inventive concepts are not limited thereto.

Subsequently, the test apparatus TA may measure the resistance of the node ND (S512), e.g., with respect to another node such as a ground node and/or the terminal voltage Vterm. For example, when the first resistor R1 is connected to the terminal voltage Vterm through the first transistor TR1 at the first time t1, the test apparatus TA may measure the resistance value of first resistor R1 connected to the node ND. When the second resistor R2 is connected to the terminal voltage Vterm through the second transistor TR2 at the second time t2, the test apparatus TA may measure the resistance values corresponding to the first resistor R1 and the second resistor R2 connected in parallel to the node ND. Here, the resistance value to be measured may be resistance values of the first resistor R1 and the second resistor R2 connected in parallel. Further, when the third resistor R3 is connected to the terminal voltage Vterm through a third transistor TR3 at the third time t3, the test apparatus TA may measure the resistance values corresponding to the first resistor R1, the second resistor R2 and the third resistor R3 connected to the node ND in parallel. Here, the resistance value to be measured may be resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 that are each connected in parallel. For example, the memory status information MSI may be inversely proportional to the resistance values of the first to third resistors R1 to R3 arranged in parallel. That is, the resistance value included in the memory status information MSI may decrease as time increases.

The status indicating module <NUM> may determine whether the measured resistance value changes (S513). When the measured resistance value changes (S513-Y), the status indicating module <NUM> may perform monitoring on an (n+<NUM>st) initialization operation (S514). For example, when the resistance value included in the memory status information MSI changes at the second time t2, the status indicating module <NUM> may monitor the third initialization operation. For example, the initialization module <NUM> may perform the third initialization operation following the second initialization operation, and the status indicating module <NUM> may monitor the status of the memory storage device <NUM> in which the third initialization operation is performed.

When the measured resistance value does not change (S513-N), the status indicating module <NUM> may output the memory status information MSI (S516). For example, when the resistance value included in the memory status information MSI does not change at the fourth time t4, the status indicating module <NUM> may perform a fifth initialization operation, but the status indicating module <NUM> may not monitor the status of the memory storage device <NUM> in which the fifth initialization operation is performed. Alternatively, the status indicating module <NUM> may output the memory status information MSI including information that the status of the memory storage device <NUM> due to the fourth initialization operation is not normal. For example, the test apparatus TA may grasp or determine or receive the status of the memory storage device <NUM> in which a specific initialization operation is performed on the basis of that memory status information MSI. The test apparatus TA may perform debugging, using the memory status information MSI.

However, example embodiments are not limited thereto, and at least one of the fifth to eighth status parameters STP5 to STP8 may be toggled after the fourth time t4. Therefore, the resistance value of the memory status information MSI may also be changed. In summary, the status indicating module <NUM> may output a plurality of resistances operated by a plurality of status parameters that are output as a result of performing the plurality of initialization operations, and resistance values that change through the plurality of transistors, and the test apparatus TA may monitor the changed resistance value and perform debugging.

<FIG> is a diagram for explaining the test apparatus which performs the debugging according to some example embodiments.

Referring to <FIG>, the test apparatus TA may perform debugging on a host <NUM> and a passive element <NUM> on the basis of the memory status information MSI. For example, if the memory status information MSI indicates that the status of the memory storage device <NUM> due to the initialization operation after the third initialization operation is abnormal, the test apparatus TA may perform debugging on the host <NUM> and the passive element <NUM> on the basis of that information. For example, the setting value to be input to the host <NUM> and the configuration of the passive element <NUM> may be changed to modify the initialization operation, except the first to third initialization operations. Here, the host <NUM> may correspond to the application processor AP, and the passive element <NUM> may include a resistor, a capacitor, an inductor, and the like. Debugging of the memory storage device <NUM> may be performed efficiently, by monitoring the status due to the initialization operation of the memory storage device <NUM> in real time.

Hereinafter, a status indicating module 240a according to some other embodiments will be described referring to <FIG> and <FIG>.

<FIG> is a diagram of the status indicating module according to some example embodiments. <FIG> is a timing diagram of the operation of the status indicating module of <FIG>. For convenience of explanation, repeated parts of contents explained above using.

<FIG> will be briefly described or omitted.

Referring to <FIG> and <FIG>, a status indicating module 240a may include a plurality of resistors R1 to R8, and a plurality of transistors TR1 to TR8. Here, at least some of the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8 may be connected in series. While the plurality of resistors R1 to R8 of the status indicating module <NUM> described referring to <FIG> are connected in parallel, the status indicating module 240a may include a plurality of resistors R1 to R8 connected in series. Additionally, although <FIG> illustrates that the plurality of transistors TR1 to TR8 are NMOS transistors, example embodiments are not limited thereto, and one or more of the plurality of transistors TR1 to TR8 may be PMOS transistors. Additionally or alternatively, although <FIG> illustrates that there are eight transistors, example embodiments are not limited thereto, and there may be more than eight transistors or less than eight transistors.

A source drain of the first transistor TR1 may be connected to the first resistor R1 and the second resistor R2. A first voltage V1 may be applied to the source drain of the first transistor TR1. A first status parameter STP1 may be input to the gate of the first transistor TR1. The first transistor TR1 may be turned on as the first status parameter STP1 is toggled.

The source drain of the second transistor TR2 may be connected to the second resistor R2 and the third resistor R3, and a second voltage V2 may be applied to the source drain of the second transistor TR2. A second status parameter STP2 may be input to the gate of the second transistor TR2. A source drain of the third transistor TR3 may be connected to the third resistor R3 and the fourth resistor R4, and a third voltage V3 may be applied to the source drain of the third transistor TR3. A third status parameter STP3 may be input to the gate of the third transistor TR3. Subsequently, the fourth to eighth resistors R4 to R8 and the fourth to eighth transistors TR4 to TR8 may be connected in series.

At the first time t1, the first status parameter STP1 may be toggled. Accordingly, the first voltage V1 may be applied to the first resistor R1. In this case, the memory status information MSI that is output through the status indicating module 240a may correspond to the resistance value of the first resistor R1. At the second time t2, the second status parameter STP2 may be toggled. Accordingly, the second voltage V2 may be applied to the first resistor R1 and the second resistor R2. In this case, the memory status information MSI that is output through the status indicating module 240a may correspond to the resistance values of the first resistor R1 and the second resistor R2. For example, the memory status information MSI during the time interval between the second time t2 and the third time t3 may be a sum of the resistance value of the first resistor R1 and the resistance value of the second resistor R2.

The third status parameter STP3 may be toggled at the third time t3. Accordingly, the third voltage V3 may be applied to the first resistor R1, the second resistor R2, and the third resistor R3. The memory status information MSI that is output from the status indicating module 240a may correspond to a sum of the resistance value of the first resistor R1, the resistance value of the second resistor R2, and the resistance value of the third resistor R3. After the fourth time t4, the fourth to eighth status parameters STP4 to STP8 may not be toggled, and the memory status information MSI may be maintained as the memory status information MSI during the time interval between the third time t3 and the fourth time t4.

For example, while the resistance value of the memory status information MSI that is output from the status indicating module <NUM> described referring to <FIG> decreases with toggling of the status parameters, the resistance value of the memory status information MSI that is output from the status indicating module 240a may increase with toggling of the status parameters. The test apparatus TA may perform debugging by referring to the memory status information MSI.

Hereinafter, a status indicating module 240b according to some example embodiments will be described referring to <FIG>.

<FIG> is a diagram of the status indicating module according to some embodiment. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG>, the status indicating module 240b may include first to eighth resistors R1 to R8. Here, the first to eighth resistors R1 to R8 may have different resistance values from each other, e.g., may have resistances that are orders of magnitude different from one another. For example, the resistance value of the first resistor R1 may be <NUM> mega-ohms (<NUM><NUM>Ω), the resistance value of the second resistor R2 may be one mega-ohm (<NUM><NUM>Ω), the resistance value of the third resistor R3 may be <NUM> kilo-ohms <NUM><NUM>Ω, the resistance value of the fourth resistor R4 may be ten kilo-ohms (<NUM><NUM>Ω), the resistance value of the fifth resistor R5 may be one kilo-ohm (<NUM><NUM>Ω), the resistance value of the sixth resistor R6 may be one hundred ohms (<NUM><NUM>Ω), the resistance value of the seventh resistor R7 may be ten ohms (10Q), and the resistance value of the eighth resistor R8 may be one ohm (1Ω).

The first to eighth status parameters STP1 to STP8 may be toggled sequentially, but may be toggled in any order. For example, the third status parameter STP3 may be toggled after the first status parameter STP1 is toggled. The memory status information MSI when the first status parameter STP1 is toggled may correspond to <NUM><NUM>Ω which is the resistance value of the first resistor R1. After that, the memory status information MSI when the third status parameter STP3 is toggled may correspond to <NUM><NUM>Ω, which is the resistance value of the first resistor R1 and the third resistor R3 connected in parallel. For example, by connecting the resistors having different resistance values from each other, it may be possible to determine which initialization operation has an abnormality through the memory status information MSI to be output. However, example embodiments are not limited thereto.

Hereinafter, a status indicating module 240c according to some other embodiments will be described referring to <FIG>.

<FIG> is a diagram of the status indicating module according to some embodiment. <FIG> is a diagram of a test apparatus that receives a signal from the status indicating module of <FIG>. <FIG> is a flowchart for explaining a test method of the memory storage device according to <FIG> and <FIG>. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG> and <FIG>, the status indicating module 240c may include a multiplexer <NUM>. Here, the multiplexer <NUM> may be placed between the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8. For example, the multiplexer <NUM> may connect the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8. The multiplexer <NUM> may selectively connect the plurality of resistors R1 to R8 with the plurality of transistors TR1 to TR8. For example, unlike the example in which the plurality of resistors R1 to R8 match with the plurality of transistors TR1 to TR8 in the status indicating module 240c described referring to <FIG>, the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8 of the status indicating module 240c may be selectively connected through the multiplexer <NUM>. The multiplexer <NUM> may connect the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8, using the multiplexer selection data MSD. Further, the multiplexer <NUM> may output the multiplexer selection data MSD and provide it to the test apparatus TA. The test apparatus TA receives the multiplexer selection data MSD and the memory status information MSI, and may monitor the status of the memory storage device <NUM>, using them.

Referring to <FIG>, the multiplexer <NUM> may connect the resistors and the transistors on the basis of the multiplexer selection data MSD and output the multiplexer selection data MSD (S520). For example, the multiplexer <NUM> may connect one of the plurality of transistors TR1 to TR8 to one of the plurality of resistors R1 to R8. Further, the multiplexer selection data MSD for the data in which the resistors and the transistors are connected may be provided to the test apparatus TA.

The memory storage device <NUM> may be powered on and perform the initialization operation (S521). The plurality of transistors TR1 to TR8 may be turned on in response to the plurality of status parameters STP1 to STP8 (S522). Subsequently, the test apparatus TA may measure the resistance of the node ND (S523). The status indicating module <NUM> may output the memory status information MSI (S524).

The test apparatus TA may perform debugging, using the memory status information MSI and the multiplexer selection data MSD (S525). For example, the connection status between the plurality of resistors R1 to R8 and the plurality of transistors TR1 to TR8 may be monitored, using the multiplexer selection data MSD, and the change of the resistance value may be monitored, using the memory status information MSI. For example, even if the order of the initialization operations of the initialization module <NUM> is changed or omitted, the test apparatus TA may monitor the memory storage device <NUM>, using the multiplexer selection data MSD. However, example embodiments are not limited thereto.

Hereinafter, a method of monitoring the memory storage device <NUM> according to some other embodiments will be described referring to <FIG> and <FIG>.

<FIG> and <FIG> are diagrams for explaining a test apparatus that performs a test on a memory storage device that communicates with the host according to some example embodiments. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG>, the memory storage device <NUM> and the host <NUM> may be mounted on the main board MB. Here, the host <NUM> may be connected to the memory storage device <NUM> through the main board MB. The host <NUM> and the memory storage device <NUM> may communicate with each other through the main board MB. Further, the monitoring apparatus MA may be connected to the main board MB through the probe PB. Here, the probe PB may be connected to the memory storage device <NUM> through the test pin TP. The monitoring apparatus MA may receive memory status information MSI' from the memory storage device <NUM>. The monitoring apparatus MA may monitor the status of the memory storage device <NUM> on the basis of the memory status information MSI'. While the monitoring apparatus MA performs monitoring, the host <NUM> and the memory storage device <NUM> may communicate with each other.

Referring to <FIG>, the host <NUM> may transmit the clock signal CLK, the command CMD, and the address ADDR to the memory storage device <NUM>. Further, the host <NUM> may send and receive the data DQ to and from the memory storage device <NUM>. Further, the memory storage device <NUM> may operate on the basis of the signal received from the host <NUM>. For example, the memory storage device <NUM> may perform a plurality of operations. The memory controller <NUM> may perform a plurality of operations, and the processor <NUM> provides the status indicating module <NUM> with a status parameter STPX of the status of the memory storage device <NUM> that has performed the plurality of operations. The status indicating module <NUM> may change the resistance value measured by the monitoring apparatus MA on the basis of the status parameter STPX.

For example, when the status of the memory storage device <NUM> in which the first operation is performed is normal, the resistance value of the memory status information MSI' that is output from the status indicating module <NUM> may change. However, when the status of the memory storage device <NUM> in which the second operation following the first operation is performed is not normal, the resistance value of the memory status information MSI' that is output from the status indicating module <NUM> may not change. For example, even when communication between the host <NUM> and the memory storage device <NUM> is performed and the memory storage device <NUM> operates on the basis of the signal from the host <NUM>, the monitoring apparatus MA may monitor the memory storage device <NUM>, using the memory status information MSI'. However, example embodiments are not limited thereto.

Hereinafter, a memory storage device 1a and a memory storage device 1b according to some other embodiments will be described referring to <FIG> and <FIG>.

<FIG> is a block diagram of the memory storage device according to some example embodiments. <FIG> is a block diagram of the memory storage device according to some example embodiments. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG>, a memory device <NUM> of a memory storage device 1a may include a status indicating module <NUM>. Unlike the example in which the memory controller <NUM> of the memory storage device <NUM> described referring to <FIG> includes the status indicating module <NUM>, the status indicating module <NUM> may be placed inside the memory device <NUM> in the present embodiment. The status indicating module <NUM> may output information about the status of the memory storage device 1a.

Referring to <FIG>, a memory storage device 1b may include a memory device <NUM>, a memory controller <NUM>, and a status indicating module <NUM>. Here, the status indicating module <NUM> may be placed separately from the memory device <NUM> and the memory controller <NUM>. For example, the status indicating module <NUM> may be placed outside/external to the memory device <NUM> and the memory controller <NUM>. The status indicating module <NUM> may output information about the status of the memory storage device 1b, by receiving and processing the status parameter from the memory controller <NUM>.

Hereinafter, a memory storage device <NUM> according to some example embodiments will be described referring to <FIG>.

<FIG> is a diagram of the memory storage device according to some example embodiments. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG>, the memory storage device <NUM> may be mounted in a memory slot SLT. Here, the memory slot SLT may be placed on the main board MB. The memory storage device <NUM> may be connected to the main board MB through the memory slot SLT, and may be connected to the monitoring apparatus MA. The memory slot SLT may be called a memory socket.

The memory storage device <NUM> may be a dual in-line memory module (DIMM). The memory storage device <NUM> may include a plurality of memory devices 400a. Here, the plurality of memory devices 400a may be arranged in a row and connected to each other. Here, the memory device 400a may correspond to the memory device <NUM> described referring to <FIG>.

The memory storage device <NUM> may include a substrate <NUM>, a register clock driver <NUM>, a plurality of memory devices 400a, and a connecting pin <NUM>. The register clock driver <NUM>, the plurality of memory devices 400a, and the connecting pin <NUM> may be mounted on the substrate <NUM>. Further, the register clock driver <NUM>, the plurality of memory devices 400a, and the connecting pin <NUM> may be electrically connected by the connecting devices included in the substrate <NUM>. The substrate <NUM> may include a plate made of an insulator such as plastic, and connecting devices connected to the register clock driver <NUM>, the plurality of memory devices 400a and the connecting pin <NUM>.

The connecting pin <NUM> may be placed along the lower part of the substrate <NUM>, and may be placed so that the upper side of the connecting pin <NUM> is exposed. The connecting pin <NUM> may include a data pin 403a, a command address pin 403b, and a test pin 403c. The test pin 403c may be connected to the monitoring apparatus MA through the probe PB.

The register clock driver <NUM> (RCD) may be mounted on the substrate <NUM>. The register clock driver <NUM> may be connected to the memory device 400a and the connecting pin <NUM> through wirings on the substrate <NUM>.

The register clock driver <NUM> may receive the clock signal CLK, the command CMD, the address ADDR, and the like through the command address pin 403b. The register clock driver <NUM> may provide the clock signal CLK, the command CMD, the address ADDR, and the like to the plurality of memory devices 400a. Here, the memory storage device <NUM> including the register clock driver <NUM> may operate on the basis of the RDIMM (registered DIMM). The register clock driver <NUM> in this embodiment may correspond to the memory controller <NUM> described referring to <FIG>. For example, the register clock driver <NUM> may include a status indicating module <NUM> that monitors the status of the memory storage device <NUM>. The monitoring apparatus MA may receive the memory status information that is output from the status indicating module <NUM> of the register clock driver <NUM> through the test pin 403c, and monitor the status of the memory storage device <NUM>.

Hereinafter, a vehicle <NUM> including an electronic control device <NUM> and a memory storage device <NUM> according to some other embodiments will be described referring to <FIG>.

<FIG> is a diagram of a vehicle including a memory storage device according to some example embodiments. For convenience of explanation, repeated parts of contents explained above using <FIG> will be briefly described or omitted.

Referring to <FIG>, the vehicle <NUM> may include a plurality of electronic control units (ECU) <NUM> and a memory storage device <NUM>. At this time, the electronic control device <NUM> may correspond to the host <NUM> described above, and the memory storage device <NUM> may correspond to the memory storage device <NUM>. For example, the memory storage device <NUM> may include the status indicating module <NUM>.

Each or at least some of the electronic control device of the plurality of electronic control devices <NUM> is electrically, mechanically, and/or communicatively connected to at least one of the plurality of devices provided in the vehicle <NUM>, and may control the operation of at least one device on the basis of any one function execution command.

Here, the plurality of devices may include an acquisition device <NUM> that acquires information required to perform at least one function, and a driving unit <NUM> that performs at least one function.

For example, the acquisition device <NUM> may include various detection units and image acquisition units, and the driving unit <NUM> may include a fan and a compressor of an air conditioner, a fan of a ventilation device, an engine and a motor of a power unit, a motor of a steering device, a motor and a valve of a braking device, opening and closing devices of a door or a tailgate, and the like.

The plurality of electronic control devices <NUM> may communicate with the acquisition device <NUM> and the driving unit <NUM> using, for example, at least one of an Ethernet, a low voltage differential signaling (LVDS) communication, and a LIN (Local Interconnect Network) communication.

The plurality of electronic control devices <NUM> determine whether there is a need to or a desire to perform the function on the basis of the information acquired through the acquisition device <NUM>, and when it is determined that there is a need to perform the function, the plurality of electronic control devices <NUM> controls the operation of the driving unit <NUM> that performs the function, and may control an amount of operation on the basis of the acquired information. At this time, the plurality of electronic control devices <NUM> may store the acquired information in the memory storage device <NUM>, or may read and use the information stored in the memory storage device <NUM>.

The plurality of electronic control devices <NUM> is able to control the operation of the driving unit <NUM> that performs the function on the basis of the function execution command that is input through the input unit <NUM>, and is also able to control the operation of the driving unit <NUM> that checks the setting amount corresponding to the information that is input through the input unit <NUM> and performs the function on the basis of the checked setting amount.

Each electronic control device <NUM> may control any one function independently, or may control any one function in cooperation with other electronic control devices.

For example, when a distance to an obstacle detected through a distance detection unit is within a reference distance, an electronic control device of a collision prevention device may output a warning sound for a collision with an obstacle through a speaker.

An electronic control device of an autonomous driving control device may receive navigation information, road image information, and distance information to obstacles in cooperation with the electronic control device of the vehicle terminal, the electronic control device of the image acquisition unit, and the electronic control device of the collision prevention device, and control the power device, the braking device, and the steering device using the received information, thereby performing the autonomous driving.

A connectivity control unit (CCU), <NUM> is electrically, mechanically, and communicatively connected to each of the plurality of electronic control devices <NUM>, and communicates with each of the plurality of electronic control devices <NUM>.

For example, the connectivity control unit <NUM> is able to directly communicate with a plurality of electronic control devices <NUM> provided inside the vehicle, is able to communicate with an external server, and is also able to communicate with an external terminal through an interface.

Here, the connectivity control unit <NUM> may communicate with the plurality of electronic control devices <NUM>, and may communicate with the server <NUM>, using an antenna (not shown) and a RF communication.

Further, the connectivity control unit <NUM> may communicate with the server <NUM> by wireless communication. At this time, wireless communication between the connectivity control unit <NUM> and the server <NUM> may be performed through various wireless communication methods such as one or more of a GSM (global System for Mobile Communication), a CDMA (Code Division Multiple Access), a WCDMA (Wideband Code Division Multiple Access), a UMTS (universal mobile telecommunications system), a TDMA (Time Division Multiple Access), and an LTE (Long Term Evolution), in addition to a Wi-Fi module and a Wireless broadband module.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc..

Claim 1:
A memory storage device (<NUM>) comprising:
a memory controller (<NUM>); and
a status indicating circuit (<NUM>),
wherein the memory controller (<NUM>) is configured to perform a first and a second initialization operation in response to turning-on of the memory storage device (<NUM>), to generate a first status parameter regarding a status of the memory storage device (<NUM>) in which the first initialization operation has been performed, and to generate a second status parameter regarding the status of the memory storage device (<NUM>) in which the second initialization operation has been performed,
the status indicating circuit (<NUM>) includes,
a first transistor (TR1) which is configured to operate on the basis of the first status parameter,
a first resistor (R1) connected to the first transistor (TR1),
a second transistor (TR2) which is configured to operate on the basis of the second status parameter, and
a second resistor (R2) connected to the second transistor (TR2),
wherein a gate of the first transistor (TR1)receives the first status parameter, a first source/drain of the first transistor (TR1) is connected to a terminal voltage (Vterm), a second source/drain of the first transistor (TR1) is connected to one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to a node (ND), and
wherein a gate of the second transistor (TR2)receives the second status parameter, a first source/drain of the second transistor (TR2) is connected to the terminal voltage (Vterm), a second source/drain of the second transistor (TR2) is connected to one end of the second resistor (R2), and the other end of the second resistor (R2) is connected to the node (ND).