Patent Description:
Typically, in integrated circuit design flip chip (FC) bonding to laminate is used to reduce antenna array inaccuracies. Multiple semiconductor chips are FC-bonded to a laminate antenna array. For mmWave signals, and in particular for <NUM> applications, the tolerances of laminate are insufficient, so fan-out package technology is used to reduce tolerances. Fan-out packages are generally made in large formats and cut into single packages for yield reasons. For beam-forming of mmWave signals, the antenna array required can become too big for one package, so it is known to place two or more packages close together on a printed circuit board, each package comprising an antenna sub-array, to form a larger antenna array. This may be referred to as a multi-package module.

The two (or more) packages are usually surface mounted to a printed circuit board (PCB). The accuracy of package-to-package connections depends on the solder alignment. Any gaps, discontinuities, or irregularities between the antenna sub-arrays results in RF losses and reduced performance of the semiconductor device. For example, surface waves can create a pointing error that leads to non-optimal antenna performance. In order to have optimum antenna performance both array regularity as well as discontinuity between the sub-arrays (or packages) should ideally be minimised.

It is known to minimise the package dimensions in such way that by surface mounting the packages will automatically align in a grid, due to the high amount of solder ball per package.

Generally, no grounding is provided between the two packages. Instead, each package is separately grounded via the customer PCB.

<CIT> describes a method of operation for a hierarchically elaborated phased-array antenna. Within a plurality of front end modules a phased-array processing die individually transforms phase and gain according to a register array. A phased-array panel contains a number of front end modules, ball grid array (BGA) mounted onto a main PCB.

<CIT> describes a system and method for an array antenna. A first printed circuit board antenna tile comprises a repeating pattern of antenna element units. A second first printed circuit board antenna tile comprises the repeating pattern. The first printed circuit board antenna tile and the second first printed circuit board antenna tile can be attached such that the antenna elements maintain the same spacing in an X-Y plane associated with the repeating pattern across a boundary of the first printed circuit board antenna tile and the second first printed circuit board antenna tile.

Aspects of the present disclosure are set out in the accompanying independent and dependent claims.

According to an aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch that is the same as the pitch of the first antenna sub-array and the second antenna sub-array.

Optionally, the antenna array (formed of the first antenna sub-array and the second antenna sub-array) comprises a plurality of antenna elements and each of the antenna elements is the same size and shape.

The first and second integrated circuit packages may be referred to as antenna-in-package (AiP) packages.

The term 'package' may be used interchangeably with 'integrated circuit package' throughout this disclosure. The first and second integrated circuit packages may also be referred to as tiles which combine to form the multi-package module.

The first antenna sub-array and the second antenna sub-array may be patch antenna arrays. The antenna array may be referred to as an active phased array antenna.

The antenna array may be controlled integrally by a processor, or a CPU.

The first antenna sub-array and the second antenna sub-array may each comprise a grid of antenna elements separated by shielding walls. Thus, the antenna array of the multi-package module may comprise a grid of antenna elements separated by shielding walls. Each antenna element may comprise a patch antenna. Each antenna element may have the same size and shape. When mounted on the substrate, the spacing between each antenna element may be equal.

Throughout this disclosure 'antenna element' refers to the square of the antenna grid containing the patch antenna, not to the patch antenna itself.

Optionally, the spacing between the final column of antenna elements in the first antenna sub-array and the first (or adjacent) column of antenna elements in the second antenna sub-array may be the same as the spacing between adjacent antenna elements in the first and second antenna sub-arrays.

The first antenna sub-array may comprise a first N x M sub-array. The second antenna sub-array may comprise a second N x M sub-array. The number of rows or columns in the second antenna sub-array does not necessarily match the number of rows or columns in the first antenna sub-array.

In some embodiments, the first antenna sub-array and/or the second antenna sub-array may comprise an N x N antenna grid (e.g. a square antenna sub-array).

The first and second packages may be positioned such that the antenna array of the multi-package module comprises an N x <NUM> antenna array, or a 2N x M array.

The present disclosure is not limited to the use of two packages. The multi-package module may comprise a plurality of integrated circuit packages (e.g. three or more packages). The packages may be arranged to form an (Y·N) x (X·M) array.

Optionally, a plurality of multi-package modules may be provided, wherein each multi-package module comprises at least two packages. The multi-package modules may be positioned adjacent to each other on the substrate.

The substrate may be a printed circuit board (PCB).

The first integrated circuit package and the second integrated circuit package may be surface-mounted to the substrate by a plurality of solder bumps.

Optionally, there is a gap between the first integrated circuit package and the second integrated circuit package when mounted on the substrate. Thus, the first integrated circuit package may not be in direct contact with the second integrated circuit package when mounted on the substrate.

In some examples, the first integrated circuit package and the second integrated circuit package are integrally formed. Thus, the first integrated circuit package and the second integrated circuit package may be formed as a single unit, rather than being separated. The multi-package may be referred to as a duo antenna-in-package (DUO AiP) package, or a dual antenna-in-package (Dual AiP).

The first integrated circuit package is connected (directly or indirectly) to the second integrated circuit package when mounted on the substrate.

The first integrated circuit package may be connected to the second integrated circuit package on the substrate by a joint. The joint may be a solder joint.

The joint is configured to provide an electrical connection or grounding between the first integrated circuit and the second integrated circuit. This may be referred to as package-to-package grounding. The joint may be referred to as the grounding connection between the packages.

The joint comprises an upper portion and a lower portion. The upper portion is disposed between the first antenna sub-array and the second antenna sub-array and the lower portion is disposed adjacent to the substrate. The lower portion of the joint may be narrower than the upper portion of the join.

The upper portion of the joint comprises an electrically conductive material. The lower portion of the joint comprises an electrically insulating material, or an electrically non-conductive material.

An underfill material may be disposed between a base (or underside) of the multi-package module and the substrate. The underfill may fill in any gaps between the solder bumps that mount the packages to the substrate.

Optionally, the electrically conductive material has a melting point which is lower than the melting point of the solder bumps used to surface-mount the packages to the substrate. Optionally, the electrically conductive material has a melting point which is higher than the melting point of the underfill material.

Optionally, the electrically conductive material has a melting point of <NUM> or less. In some embodiments, the electrically conductive material has a melting point of between <NUM> and <NUM>.

The electrically conductive material may comprise a conductive glue or solder material. For example, the electrically conductive material may be a glue comprising metallic particles such as silver particles or the electrically conductive material may be a tin-based solder material, but it is not limited to these materials. It will be appreciated that a combination of different electrically conductive materials may be used.

Optionally, the semiconductor device may comprise a first multi-package module and a second multi-package module stacked adjacent to the first multi-package module. The first and second multi-package module may be as described in any of the above embodiments or examples.

According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising providing a first integrated circuit package comprising a first antenna sub-array having a uniform pitch, providing a second integrated circuit package comprising a second antenna sub-array having a uniform pitch, positioning the second integrated circuit package adjacent to the first integrated circuit package on a substrate to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch that is the same as the pitch of the first and second sub-arrays, and mounting the first integrated circuit package and the second integrated circuit package on the substrate.

The first and second integrated circuit packages may be as defined in any of the above embodiments or examples of the disclosure.

Optionally, positioning the second integrated circuit package adjacent to the first integrated circuit package may comprise minimising a gap between the second integrated circuit package and the first integrated circuit package. In other words, the second integrated circuit package may be positioned as close as possible to the first integrated circuit package on the substrate to reduce signal losses.

Mounting the first integrated circuit package and the second integrated circuit package may comprise surface-mounting (SMT mounting) the first integrated circuit package and the second integrated circuit package on the substrate with a plurality of solder bumps. Thus, the method may include reflowing the solder bumps (sometimes just called reflowing). The substrate may be a printed circuit board (PCB).

Positioning the second integrated circuit package may include rotating the second integrated circuit package relative to the first integrated circuit package (or vice versa). However, this is not essential, as some packages may not require rotation. Optionally, the method may include rotating the second package <NUM>°, or <NUM>°, or <NUM>° relative to the first package.

The first integrated circuit package may comprise a first end and a second end. The second integrated circuit package may also comprise a first end and a second end. Positioning the second integrated circuit package adjacent to the first integrated circuit package may comprise positioning the second end of the second integrated circuit package proximate and adjacent to the second end of the first integrated circuit package. Alternatively, positioning the second integrated circuit package adjacent to the first integrated circuit package may comprise positioning the first end of the second integrated circuit package proximate and adjacent to the second end of the first integrated circuit package.

The first antenna sub-array may comprise a first N x M sub-array. The second antenna sub-array may comprise a second N x M sub-array. The first and second packages may be positioned such that the antenna array of the multi-package module comprises an N x <NUM> antenna array, or a 2N x M array.

Optionally, the method may include cutting the first integrated circuit package and/or the integrated circuit package to ensure that the antenna array has a uniform pitch when the second integrated circuit package is positioned adjacent to the first integrated circuit package.

The cutting step may remove a portion of the first integrated circuit package and/or the second integrated circuit package.

The cutting step may comprise cutting off a first end portion of the first integrated circuit package and cutting off a second end portion of the second integrated circuit package.

In some embodiments, the method may comprise cutting (or sawing) off a portion of the first or second end of both the first integrated circuit package and the second integrated circuit package, then placing the cut surface of the second integrated circuit package proximate and adjacent to the cut surface of the first integrated circuit package.

The cut surface of the first and/or second integrated circuit package may have a conductive edge. Optionally, the conductive edge may be contacted to provide an electrical connection (grounding) between two or more packages. This electrical connection may be achieved by a plating, flux or adding a conductive material.

The first antenna sub-array and the second antenna sub-array may each comprise a grid of antenna elements separated by shielding walls. Optionally, the cutting step comprises cutting through the first integrated circuit package and/or the second integrated circuit package lengthwise along one of the shielding walls.

In some embodiments, the cutting step may comprise cutting (or sawing) down the middle of the final shielding wall (e.g. the (M+<NUM>)th shielding wall column in an N x M sub-array) on both the first and second integrated circuit packages. The cut surface of the second integrated circuit package may then be placed proximate and adjacent to the cut surface of the first integrated circuit package before mounting the packages on the substrate.

The method includes providing grounding or an electrical connection between the first integrated circuit package and the second integrated circuit package. This may be referred to as providing package-to-package grounding.

There is a gap between the first integrated circuit and the second integrated circuit package when mounted on the substrate. Providing package-to-package grounding comprises inserting an electrically insulating material into a lower portion of the gap disposed adjacent to the substrate, and inserting an electrically conductive material into an upper portion of the gap between the first antenna sub-array and the second antenna sub-array.

The method may include melting or curing the electrically insulating material. The method may include melting the electrically conductive material such that it flows into the gap between the packages, for example during a reflow process.

Optionally, the electrically conductive material may have a melting point that is lower than the melting point of the solder bumps used to mount the first and second packages to the substrate. This may prevent the solder bumps from melting (or reflowing) during reflow of the electrically conductive material.

Optionally, the melting or curing of the electrically conductive material may be at a temperature of <NUM> or less. Optionally, the melting or curing of the electrically conductive material may be at a temperature of between <NUM> and <NUM>.

Optionally, the electrically conductive material may be plated or dispensed over and/or into the upper portion of the gap. This may be done after the first and second packages have been mounted to the substrate. The electrically conductive material may be a solder material, or a conductive glue, such as a glue comprising metallic particles, but is not limited to these materials.

Optionally, the method may include removing excess electrically insulating material from the upper portion of the gap before dispensing or before melting the electrically conductive material.

Optionally, providing grounding between the packages comprises the initial step of expanding the upper portion of the gap by partially cutting the first package and the second package. This may be done before mounting the first and second integrated circuit packages on the substrate. This may involve creating a step cut at an edge of each package, wherein the step-cut edge of the packages are positioned adjacent to each other in the multi-package module.

The method may include underfilling, or dispensing and curing an underfill material between a base of the multi-package module and the substrate. The curing may be at a temperature of <NUM> or less. Optionally, the underfill material is an organic resin.

Illustrative embodiments of this disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:.

Embodiments of this disclosure are described in the following with reference to the accompanying drawings. It will be appreciated that the drawings are schematic illustrations and are not drawn to scale.

The example shown in <FIG> does not fall within the scope of the claims.

<FIG> show a prior art multi-package module formed of a first integrated circuit package <NUM> and a second integrated circuit package <NUM>. For yield reasons, the first and second packages <NUM>, <NUM> are cut into separate packages during the manufacturing process. The packages <NUM>, <NUM> are surface mounted (SMT mounted) by a plurality of solder bumps <NUM> to a substrate, typically a printed circuit board <NUM>, as shown in <FIG>. There is a gap <NUM> between the packages when mounted. The spacing <NUM> between the packages <NUM>, <NUM> is typically larger than <NUM> package to package. A gap <NUM> of around <NUM> between packages is currently industry standard. The performance of the multi-package module depends on the accuracy of the solder alignment. There is no grounding between the packages <NUM>, <NUM>. Each package <NUM>, <NUM> is separately grounded via the PCB <NUM>.

The first integrated circuit package <NUM> comprises a first antenna sub-array <NUM> and the second integrated circuit package <NUM> comprises a second antenna sub-array <NUM>, shown in <FIG>. Thus, the first and second packages <NUM>, <NUM> are antenna-in-package (AiP) packages. The sub-arrays <NUM>, <NUM> are positioned adjacent to each other to form an overall antenna array <NUM>.

The first and second antenna sub-arrays <NUM>, <NUM> are disposed on separate packages <NUM>, <NUM>. The gap between the two sub-arrays is wider than the gap <NUM> between the packages. Each sub-array <NUM>, <NUM> comprises a grid of antenna elements <NUM>, <NUM> separated by shielding walls <NUM>. Each antenna element <NUM>, <NUM> (or square of the grid) comprises a patch antenna (not shown). For simplicity, in <FIG> the first and second antenna sub-arrays <NUM>, <NUM> are shown as 3x4 arrays. However, in practice the sub-arrays can be any size.

As shown in <FIG>, the sub-arrays <NUM>, <NUM> are asymmetrical, as the antenna elements do not have a uniform size and shape across the sub-arrays <NUM>, <NUM>. Instead, the column of antenna elements <NUM> adjacent to the gap <NUM> between the first and second packages <NUM>, <NUM> are narrower than the other antenna elements <NUM> in the sub-arrays, as depicted by the solid arrows in <FIG>. Thus, the pitch is not the same across each individual sub-array <NUM>, <NUM>. The pitch of an antenna array is the distance from the centre of an antenna element (e.g. the centre of the patch antenna) to the centre of the adjacent antenna element. If the pitch is not uniform across an antenna array or sub-array this leads to discontinuity and reduced antenna array performance. In <FIG> (which is not drawn to scale) the pitch is shown by the dotted arrows. Thus, the antenna elements <NUM> are made narrower to account for the gap <NUM> between the sub-arrays <NUM>, <NUM>, so that the pitch from package-to-package over the gap <NUM> can be the same as the pitch between the antenna elements <NUM> within the packages. However, the irregularity in the antenna size can result in increased RF noise. To achieve optimum performance of the antenna array <NUM>, both array and sub-array irregularity (e.g. asymmetry) and discontinuity between sub-arrays should be minimised.

An antenna sub-array according to an embodiment of the present disclosure is shown in <FIG>. The sub-array is part of a package <NUM> or <NUM> and comprises an N x M grid of antenna elements <NUM> separated by shielding walls <NUM>. For simplicity only, a <NUM> x <NUM> antenna sub-array is shown, however the present disclosure is not limited to square arrays and the arrays could be of any size. Each antenna element <NUM> (or antenna grid square) comprises a centrally positioned patch antenna <NUM>. Although the patch antennae <NUM> are not shown in any subsequent figures, they are present in each antenna sub-array <NUM>, <NUM>. As shown in <FIG>, the antenna elements <NUM> are a uniform or equal size across the antenna sub-array. However, the antenna elements are not limited to square or rectangular shapes. The pitch is also uniform across the sub-array. The spacing between each patch antenna <NUM> and the shielding walls <NUM> is also uniform or equal across the sub-array. Thus, the sub-array is symmetrical.

A first antenna sub-array <NUM> as shown in <FIG> is mounted to (or part of) a first integrated circuit package <NUM>, and a second antenna sub-array <NUM> as shown in <FIG> is mounted to (or part of) a second integrated circuit package <NUM>. The packages <NUM>, <NUM> each have a first end <NUM> and a second end <NUM>. To prepare the packages <NUM>, <NUM> for forming the multi-package module <NUM>, a portion of the second end <NUM> of each package <NUM>, <NUM> may be removed. This allows the packages to be positioned closer together. In other embodiments, a portion of the second end <NUM> of the first package <NUM> and a portion of the first end <NUM> of the second package may be removed, or vice versa. Optionally, the step of removing an end portion of the first and second packages <NUM>, <NUM> may form part of the package singulation process (e.g. the separation of the first package <NUM> from the second package <NUM>).

In the embodiments shown in <FIG>, the packages <NUM>, <NUM> are cut or sawn with a blade such that (if cutting from the bottom of the page) the left-hand side of the blade runs along line A. Optionally, the thickness of the blade may be around <NUM>. As shown, line A passes through the shielding wall column <NUM> adjacent the second end <NUM>, or the (M+<NUM>)th shielding wall column <NUM> of the N x M sub-array. In some embodiments the shielding wall column <NUM> may be cut in half lengthwise. The second package <NUM> is then rotated <NUM>° relative to the first package <NUM>, as shown in <FIG>. It will be appreciated that in other embodiments the second package <NUM> may not require rotation relative to the first package <NUM>, or the angle of rotation may be different such as <NUM>° or <NUM>°.

The second package <NUM> and the first package <NUM> are then moved in the directions indicated by the arrows in <FIG>, such that the second package <NUM> is positioned proximate and adjacent to the first package <NUM>. The cut surfaces of the distal ends <NUM> of the packages, along lines A, are placed close together. The cut surfaces (e.g. along line A) each have a conductive edge, which can be contacted if electrical connection between the two or more packages is desired (e.g. package-to-package grounding). This electrical connection can be achieved by a plating, flux or adding a conductive material.

As shown in <FIG>, the N x M antenna sub-arrays <NUM>, <NUM> combine to form an overall N x <NUM> antenna array <NUM>, wherein the pitch is uniform across each individual sub-array <NUM>, <NUM> and the pitch is also uniform across the array <NUM>. In other embodiments, the sub-arrays <NUM>, <NUM> may be positioned to form an overall 2N x M antenna array <NUM>. The packages <NUM>, <NUM> are then surface (SMT) mounted to a substrate <NUM> by a plurality of solder bumps <NUM> to form a multi-package module <NUM> comprising the antenna array <NUM>. Reflow soldering may be used to complete the connection between the packages <NUM>, <NUM> and the substrate <NUM>. The substrate <NUM> may be a printed circuit board (PCB).

In some embodiments, there may be a gap <NUM> between the first and second packages <NUM>, <NUM> when mounted on the substrate, as in <FIG>. Thus, the packages may not be directly connected. This gap <NUM> may be minimised to reduce discontinuity and losses across the antenna array <NUM>. The gap <NUM> may be the same width between the sub-arrays <NUM>, <NUM> as it is between the packages <NUM>, <NUM>.

In the present disclosure, there is no gap <NUM> in the finished multi-package module. The packages <NUM>, <NUM> are at least partially connected by a joint. The joint provides grounding or an electrical connection between the packages. Methods of providing package-to-package grounding are shown in <FIG>.

It will be appreciated that the present disclosure is not limited to the use of just two packages. In some embodiments, the multi-package module <NUM> may comprise three or more packages positioned adjacent to each other or formed into an array. The packages may be referred to as tiles combining to form the multi-package module.

As shown in <FIG>, a plurality of multi-package modules may be mounted on the substrate <NUM>, each multi-package module <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> comprising at least two packages <NUM>, <NUM> as described above. In <FIG>, the multi-package modules <NUM>-<NUM> form a <NUM> x <NUM> array. Another embodiment is shown in <FIG>, in which the multi-package modules <NUM>-<NUM> are arranged in a <NUM> x <NUM> array. It will be appreciated that the multi-package modules <NUM>-<NUM> may be arranged in any format, not just a <NUM> x <NUM> array or a <NUM> x <NUM> array as shown. Alternatively, <FIG> may illustrate a single multi-package module mounted on the substrate <NUM>, wherein features <NUM>-<NUM> correspond to the integrated circuit packages forming the multi-package module.

An example is shown in <FIG> wherein the first and second packages are integrally formed (i.e. not separated during the manufacturing process). This example is not an embodiment of the present disclosure. Thus, in this example the multi-package module may be formed as a single integral unit <NUM>, comprising a continuous N x <NUM> antenna array <NUM> (or 2N x M array). The antenna array <NUM> comprises a grid of antenna elements <NUM> separated by shielding walls <NUM>, wherein each antenna element <NUM> is the same size and shape and the pitch is uniform across the array <NUM>. By keeping the two packages intact any RF noise between the two sub-arrays should be minimised or eliminated.

<FIG> shows a step in a process of providing package-to-package grounding according to an embodiment of the disclosure. Providing grounding (or an electrical connection) between the packages <NUM>, <NUM>, rather than relying on grounding each package via the substrate <NUM>, may reduce losses and improve RF performance of the multi-package module.

Before the packages <NUM>, <NUM> are mounted to the substrate <NUM> (e.g. at the stage shown in <FIG> before solder reflow) the first antenna sub-array <NUM> and the second antenna sub-array <NUM> may be partially cut to expand the gap <NUM> between the packages. This may form an upper portion <NUM> of the gap which is wider than the lower portion <NUM> of the gap. This may be done by partially sawing or otherwise cutting each of the packages <NUM>, <NUM> (e.g. creating a step cut), also referred to as creating a trench between the packages. In some embodiments, the upper portion of the gap may be around <NUM> or less and the bottom portion of the gap may be around <NUM> or less. The thickness of the blade used to cut the packages <NUM>, <NUM> and the dimensions of the antenna sub-array <NUM>, <NUM> must be taken into account when making the cut. For example, (referring to <FIG>) if cutting from the bottom of the page, the left-hand side of the blade may be aligned between line A and the edge of the shielding wall <NUM> to make the partial cut.

The lower portion <NUM> of the gap may remain unchanged. It should be noted that the gap <NUM> is not shown to scale in <FIG>. The expansion of the gap <NUM> does not destroy the symmetry and regularity of the antenna array <NUM>. For example, the gap <NUM> may remove a further portion the shield walls <NUM> adjacent to the gap <NUM>, as shown in the top view of <FIG>. The shield walls <NUM> are not completely removed even though they are not visible in <FIG>. Typically, the shield walls <NUM> adjacent to the gap <NUM> are cut to become less than half of the original wall thickness.

The packages <NUM>, <NUM> may then be mounted to the substrate <NUM>, as described above. The next step in the grounding process may be to dispense and cure an electrically non-conductive material <NUM> into the lower (narrow) portion <NUM> of the gap, as shown in <FIG>. The electrically non-conductive (or electrically insulating) material <NUM> may avoid any shorts between the solder bumps <NUM> and the electrically conductive material that will be inserted into the upper portion of the gap. If excess electrically non-conductive material <NUM> extends into the upper portion <NUM> of the gap, this may optionally be removed, for example by cutting or sawing.

An electrically conductive material <NUM> may then be dispensed or plated over the upper portion of the gap <NUM>, as shown in <FIG>. The electrically conductive material <NUM> may then be melted or cured. The electrically conductive material <NUM> flows into the upper portion <NUM> of the gap to form an electrical connection between the packages <NUM>, <NUM>, as shown in <FIG>. The electrically conductive material <NUM> may form a meniscus <NUM>, preferably below the top surface of the packages <NUM>, <NUM>.

The electrically conductive material <NUM> may have a melting point which is lower than the melting point of the solder bumps <NUM>. For example, the electrically conductive material <NUM> may be a solder material having a melting point of less than <NUM>. This may prevent the solder bumps <NUM> from re-melting during reflow of the electrically conductive material <NUM>, as a lower temperature can be used than for reflowing the solder bumps <NUM>.

Finally, an underfill material <NUM> may be dispensed between an underside of the multi-package module and the substrate <NUM>, as shown in <FIG>. The underfill material <NUM> may fill the spaces between the solder bumps <NUM>. The underfill material <NUM> may be cured at a temperature of less than <NUM>. The underfill material <NUM> is typically used to improve the board level reliability of the device, as it helps to protect the solder bumps <NUM> from thermal stresses and reduce package warpage. Optionally, the non-conductive material <NUM> may be underfill material <NUM>, as capillary action may be used to force the underfill into the lower portion <NUM> of the gap.

Alternatively, the packages <NUM>, <NUM> may be surface-mounted to the substrate <NUM> before beginning the process of providing package-to-package grounding. In some embodiments, the electrically conductive material <NUM> may then be deposited over the gap <NUM>. The trench may then be created to expand the upper portion of the gap <NUM> (as described above in relation to <FIG>) which removes the central portion of the electrically conductive material, as shown in <FIG>. Thus, electrically conductive material <NUM> can be applied on a panel level after partial cutting of the topside of the package <NUM>, <NUM> or after board mount on a PCB <NUM>. The grounding process may continue as shown in <FIG>, with the dispensing and curing of the electrically insulating material <NUM> to close the bottom portion <NUM> of the gap.

The two remaining portions of the electrically conductive material <NUM> may then be melted to reflow the electrically conductive material <NUM> into the upper portion of the gap <NUM>, as shown in <FIG>. In some embodiments, additional electrically conductive material <NUM> may be dispensed into the gap <NUM>. Underfill material <NUM> may then be added, as in <FIG>.

Accordingly, there has been described a semiconductor device comprising: a substrate (such as a printed circuit board), a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array, a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array, wherein the second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, and wherein the antenna array has a uniform pitch which is the same as the pitch of the first and second sub-arrays.

Also described is a method of manufacturing a multi-package module which has a uniform pitch across the antenna sub-arrays and the antenna array. The method includes providing grounding between a first integrated circuit package and a second integrated circuit package. The method may include expanding an upper portion of a gap between the first integrated circuit package and the second integrated circuit package, dispensing an electrically non-conductive material into a lower portion of the gap, dispensing an electrically conductive material onto or into an upper portion of the gap and melting the electrically conductive material such that it joins the first integrated circuit package to the second integrated circuit package.

The term 'antenna' or 'antenna element' refers to the square of an antenna grid surrounded by shielding walls. Equivalently, the term 'antenna' used above means the patch antenna and the space between the patch antenna and the surrounding shielding walls of the antenna array.

Claim 1:
A semiconductor device comprising:
a substrate (<NUM>);
a first integrated circuit package (<NUM>) mounted on the substrate (<NUM>), the first integrated circuit package (<NUM>) comprising a first antenna sub-array (<NUM>), wherein the first antenna sub-array (<NUM>) has a uniform pitch;
a second integrated circuit package (<NUM>) mounted on the substrate (<NUM>), the second integrated circuit package (<NUM>) comprising a second antenna sub-array (<NUM>), wherein the second antenna sub-array (<NUM>) has a uniform pitch;
wherein the second integrated circuit package (<NUM>) is mounted adjacent to the first integrated circuit package (<NUM>) to form a multi-package module having an antenna array (<NUM>) formed of the first antenna sub-array (<NUM>) and the second antenna sub-array (<NUM>), wherein the antenna array (<NUM>) has a uniform pitch that is the same as the pitch of the first antenna sub-array (<NUM>) and the second antenna sub-array (<NUM>); and
wherein the first integrated circuit package (<NUM>) is connected to the second integrated circuit package (<NUM>) on the substrate by a joint, wherein the joint is configured to provide grounding or an electrical connection between the first integrated circuit package (<NUM>) and the second integrated circuit package (<NUM>);
wherein the joint comprises an upper portion (<NUM>) and a lower portion (<NUM>), wherein:
the upper portion (<NUM>) is disposed between the first antenna sub-array (<NUM>) and the second antenna sub-array (<NUM>) and comprises an electrically conductive material (<NUM>); and
the lower portion (<NUM>) is disposed adjacent to the substrate (<NUM>) and comprises an electrically insulating material (<NUM>).