Patent Description:
The present disclosure relates to a display device, and more particularly, to a stretchable display device with an improved reliability of connection lines.

Display devices employed by the monitor of a computer, a TV, a mobile phone or the like include an organic light emitting display (OLED) device that emits light by itself, and a liquid crystal display (LCD) device that requires a separate light source.

As the display devices have been increasingly applied to diverse fields such as a computer monitor, a TV, and a personal mobile device, display devices having a large active area and a reduced volume and weight have been studied.

Recently, a stretchable display device in which display elements, lines, etc. are formed on a flexible substrate made of flexible plastic and which can be stretched in a specific direction and manufactured in various shapes has attracted attention as a next-generation display device. <CIT> describes a stretchable display device, comprising: a lower substrate made of a stretchable insulating material and having an active area and a non-active area adjacent to the active area; a plurality of individual substrates spaced apart from each other and disposed in the active area of the lower substrate; pixels disposed on the plurality of individual substrates respectively; and a plurality of connecting lines disposed between the plurality of individual substrates on the lower substrate, and electrically connecting corresponding pads disposed within the plurality of individual substrates respectively. The modulus of the plurality of individual substrates is higher than that of the lower substrate. <CIT> also describes a stretchable display device. According to an example, a stretchable display device includes: a lower substrate comprising a plurality of first areas on which a plurality of sub-pixels is defined and spaced apart from one another, a plurality of second areas in which a plurality of connection lines connecting between adjacent ones of the first areas is disposed, and a plurality of third areas other than the first areas and the second areas; a plurality of additional sub-pixels disposed in the third areas, respectively; and a plurality of piezoelectric patterns electrically connected to the additional sub-pixels, respectively. The stretchable display device can suppress deterioration of image quality when it is stretched. <CIT> describes a method for manufacturing an electronic device. The method includes testing a plurality of first light-emitting units on a first substrate to select one of the plurality of first light-emitting unit that is to be replaced; removing the one of the plurality of first light-emitting units from the first substrate so that the first substrate has a vacant position; transferring a second light-emitting unit to a second substrate; and transferring at least part of the plurality of first light-emitting units that are not replaced from the first substrate to the second substrate. The vacant position on the first substrate corresponds to the second light-emitting unit. An electronic device manufactured by the method is also provided. <CIT> describes a display device which includes a thin-film transistor substrate, a conductive pad disposed on the thin-film transistor substrate, and an adhesion film disposed on the conductive pad. The adhesion film includes a plurality of conductive particles. The display device also includes a light-emitting component disposed on the adhesion film. The light-emitting component includes a connection feature. The display device also includes a protection layer partially surrounding the light-emitting component.

An object to be achieved by the present disclosure is to provide a display device which can be manufactured while minimizing tearing-off of a pad during a process of repairing a light emitting diode misaligned when the light emitting diode is transferred.

Another object to be achieved by the present disclosure is to provide a display device which can be manufactured while suppressing misalignment of a light emitting diode caused by movement of an adhesive layer that bonds the light emitting diode when the light emitting diode is transferred.

Another object to be achieved by the present disclosure is to provide a display device which can be manufactured while suppressing the occurrence of a dark spot caused by misalignment of a light emitting diode and a short circuit between a power line and a common connection pad.

Another object to be achieved by the present disclosure is to provide a display device which can be manufactured while suppressing the occurrence of a short or open of a light emitting diode caused by non-uniform distribution of conductive balls in an adhesive layer that bonds the light emitting diode when the light emitting diode is transferred.

Another object to be achieved by the present disclosure is to provide a display device which can be manufactured while suppressing a transfer efficiency decrease and defective driving of a light emitting diode caused by non-uniform placement of an adhesive layer that bonds the light emitting diode when the light emitting diode is transferred.

Objects of the present disclosure are not limited to the above-mentioned objects, but the present invention is defined by the appended claims.

At least one of the objects is solved by the features of the independent claim.

According to an aspect of the present disclosure, the display device includes: a lower substrate and a plurality of pixel substrates disposed on the lower substrate. The display device also includes a plurality of transistors disposed on the plurality of pixel substrates and a planarization layer disposed on the plurality of pixel substrates to cover upper portions of the plurality of transistors. The display device further includes a plurality of individual connection pads and a common connection pad disposed on the planarization layer. The display device also includes a plurality of light emitting diodes disposed on the plurality of individual connection pads and the common connection pad. At least one of the plurality of individual connection pads and the common connection pad has a multilayer structure wherein the common connection pad includes a lower common connection pad disposed on the planarization layer and an upper common connection pad disposed on the lower common connection pad.

According to an example of the present disclosure, the display device includes: a plurality of pixel substrates which is disposed on a lower substrate and in which a plurality of light emitting diodes is disposed. The display device also includes a planarization layer covering upper portions of the plurality of pixel substrates. The display device further includes a plurality of individual connection pads disposed on the planarization layer so as to correspond to the plurality of light emitting diodes, respectively. The display device also includes a common connection pad disposed on the planarization layer and electrically connected to all of the plurality of light emitting diodes. The display device further includes an adhesive layer electrically connecting the plurality of individual connection pads and the common connection pad to the plurality of light emitting diodes. At least one of the plurality of individual connection pads and the common connection pad has a lower pad and an upper pad disposed on an edge of the lower pad.

According to yet another example which is not part of the present invention, the display device includes: a plurality of pixel substrates which is disposed on a lower substrate and on which a plurality of light emitting diodes is disposed. The display device also includes a planarization layer covering upper portions of the plurality of pixel substrates. The display device further includes a plurality of individual connection pads disposed on the planarization layer and corresponding to the plurality of light emitting diodes, respectively. The display device also includes a common connection pad disposed on the planarization layer and electrically connected to all of the plurality of light emitting diodes. The display device may further includes an adhesive layer electrically connecting the plurality of individual connection pads and the common connection pad to the plurality of light emitting diodes and disposed to cover the entire upper surface of the planarization layer.

According to still another example which is not part of the present invention, the method of manufacturing a display device includes: a process of placing an adhesive layer, which includes a base member and a plurality of conductive balls dispersed in the base member, on a first transfer substrate. The method of manufacturing a display device also includes a process of bringing the first transfer substrate close to an upper portion of a substrate, on which a planarization layer covering upper portions of a plurality of transistors is disposed, and bonding the adhesive layer to an upper portion of the planarization layer. The method of manufacturing a display device further includes a process of bringing a second transfer substrate, on which a plurality of light emitting diodes is disposed, close to an upper portion of the adhesive layer and bonding the plurality of light emitting diodes to the upper portion of the adhesive layer.

The abvove mentioned aspects of the present disclosure may be also equipped or include one or more of the following optional features.

The upper common connection pad may be made of a material having a higher adhesiveness to electrodes of the plurality of light emitting diodes than the lower common connection pad.

The lower common connection pad may be made of copper (Cu).

The upper common connection pad may be made of gold (Au), titanium (Ti), aluminum (Al) or molybdenum (Mo).

The upper common connection pad may be disposed on an edge of the lower common connection pad.

The upper common connection pad may be further disposed on the lower common connection pad corresponding to a space between the plurality of individual connection pads.

The upper common connection pad may be disposed in a mesh form on the lower common connection pad.

The plurality of individual connection pads may include a lower individual connection pad disposed on the planarization layer and an upper individual connection pad disposed on the lower individual connection pad.

The upper individual connection pad may have a shape corresponding to the upper common connection pad and is disposed on the lower individual connection pad.

The display device may further comprise a power line disposed on the planarization layer and an insulating layer disposed on the power line.

The insulating layer may include a plurality of insulating patterns disposed on the power line.

The insulating layer, a portion relatively adjacent to the common connection pad may have a smaller height than a portion relatively far from the common connection pad.

The insulating layer may be disposed to cover a side surface of the power line adjacent to the common connection pad.

A distance between the plurality of individual connection pads and the common connection pad may be greater than a distance between the common connection pad and the power line.

The upper pad may be made of a different material from the lower pad.

The upper pad may be disposed in a mesh form on the lower pad.

The display device may further comprise, a high-potential power line disposed on the planarization layer.

The display device may further comprise an insulating layer disposed on the high-potential power line.

The common connection pad may be disposed between the plurality of individual connection pads and the high-potential power line.

The insulating layer may be disposed to cover a side surface of the high-potential power line.

The adhesive layer may include a plurality of conductive balls and a base member.

The plurality of conductive balls may be disposed in a single layer as being dispersed in the base member.

The plurality of conductive balls may be spaced apart from each other and may not be electrically connected to each other.

The plurality of conductive balls may electrically connect the plurality of individual connection pads and the common connection pad to the plurality of light emitting diodes.

A thickness of the adhesive layer may be equal to or smaller than that of the planarization layer.

Other detailed matters of the exemplary embodiments are included in the detailed description and the drawings.

According to the present disclosure, it is possible to minimize the occurrence of a defect caused by damage to a pad during a process of repairing an area where a light emitting diode is misaligned.

According to the present disclosure, it is possible to minimize misalignment of a light emitting diode which may occur when an adhesive layer for electrically connecting the light emitting diode and a pad is moved.

According to the present disclosure, it is possible to suppress the occurrence of a dark spot caused by an electrical connection between a pad and a power line by an electrode of a light emitting diode when the light emitting diode is transferred.

According to the present disclosure, a plurality of conductive balls for electrically connecting an electrode of a light emitting diode and a pad is spaced apart from each other in a single layer. Therefore, it is possible to suppress the occurrence of a short or open of a light emitting diode.

According to the present disclosure, an adhesive layer for electrically connecting a light emitting diode and a pad is disposed on the entire upper surface of a planarization layer. Therefore, it is possible to reduce or minimize a transfer efficiency decrease and defective driving of the light emitting diode caused by non-uniform placement of the adhesive layer.

According to the present disclosure, it is possible to simplify a manufacturing process by bonding an adhesive layer on the entire upper surface of a planarization layer. Also, it is possible to reduce or minimize manufacturing time and cost.

Advantages and characteristics of the present disclosure and a method of achieving the advantages and characteristics will be clear by referring to exemplary embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure. Therefore, the present disclosure will be defined only by the scope of the appended claims.

The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Further, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "including," "having," and "consist of" used herein are generally intended to allow other components to be added unless the terms are used with the term "only". Any references to singular may include plural unless expressly stated otherwise.

Hereinafter, a stretchable display device according to exemplary embodiments of the present disclosure will be described in detail with reference to accompanying drawings.

A stretchable display device may be referred to as a display device capable of displaying an image even when bent or stretched. The stretchable display device may have higher flexibility than conventional typical display devices. Thus, a user may bend or stretch the stretchable display device, and the shape of the display device may be freely changed in response to a manipulation of the user. For example, when the user seizes an end of the stretchable display device and pulls the stretchable display device, the stretchable display device may be stretched by a force of the user. When the user places the stretchable display device on an uneven wall surface, the stretchable display device may be bent along the shape of the wall surface. Also, when a force applied by the user is removed, the display device may be restored to its original shape.

<FIG> is an exploded perspective view of a display device according to an exemplary embodiment of the present disclosure. Referring to <FIG>, a display device <NUM> includes a lower substrate <NUM>, a plurality of pixel substrates <NUM>, a plurality of connection members <NUM>, a plurality of non-pixel substrates <NUM>, a Chip on Film (COF) <NUM>, a printed circuit board <NUM> and an upper substrate US.

The lower substrate <NUM> is a substrate for supporting and protecting various components of the display device <NUM>. The lower substrate <NUM> is a ductile substrate and may be made of a bendable or stretchable insulating material. For example, the lower substrate <NUM> may be made of silicone rubber such as polydimethylsiloxane (PDMS) and an elastomer such as polyurethane (PU), or polytetrafluoroethylene (PTFE). Thus, the lower substrate <NUM> may have flexible properties. However, a material of the lower substrate <NUM> is not limited thereto.

The lower substrate <NUM> is a ductile substrate and may be reversibly expandable and/or contractible. Further, the lower substrate <NUM> may have an elastic modulus in the range of several to hundreds of MPa, for example, <NUM> MPa to <NUM> MPa.

The lower substrate <NUM> may have an active area AA and a non-active area NA surrounding the active area AA.

The active area AA is an area where an image is displayed on the display device <NUM>. In the active area AA, one or more display elements and various driving elements for driving the one or more display elements are disposed. In the active area AA, a plurality of pixels including a plurality of sub-pixels is disposed. The plurality of pixels is disposed in the active area AA and includes a plurality of display elements. Each of the plurality of sub-pixels may be connected to various lines. For example, each of the plurality of sub-pixels may be connected to various lines such as a gate line, a data line, a high-potential power line, a low-potential power line and a reference voltage line.

The non-active area NA may be an area disposed adjacent to the active area AA. The non-active area NA may be an area disposed adjacent to the active area AA and at least partly or fully surrounding or enclosing the active area AA. The non-active area NA is an area where an image is not displayed. In the non-active area NA, lines and circuit units may be formed. For example, in the non-active area NA, a plurality of pads may be disposed. Each of the pads may be connected to one or more of the plurality of sub-pixels disposed in the active area AA.

The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> are disposed on the lower substrate <NUM>. The plurality of pixel substrates <NUM> may be disposed in the active area AA of the lower substrate <NUM>, and the plurality of non-pixel substrates <NUM> may be disposed in the non-active area NA of the lower substrate <NUM>. Although <FIG> illustrates that the plurality of non-pixel substrates <NUM> is disposed on the upper and left sides of the active area AA in the non-active area NA, the present disclosure is not limited thereto. The plurality of non-pixel substrates <NUM> may be disposed in an arbitrary or any area of the non-active area NA.

The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> are rigid substrates. The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> are spaced apart from each other to be independently disposed on the lower substrate <NUM>. The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be more rigid than the lower substrate <NUM>. That is, the lower substrate <NUM> may be more ductile than the plurality of pixel substrates <NUM> and/or the plurality of non-pixel substrates <NUM>. Also, the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be more rigid than the lower substrate <NUM>. The plurality of pixel substrates <NUM> are spaced apart from each other in the display area AA. The plurality of non-pixel substrates <NUM> are spaced apart from each other in the non display area NA. Thus, a certain distance is provided between the plurality of pixel substrates <NUM> and between the plurality of non-pixel substrates <NUM>.

The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM>, which are rigid substrates, may be made of a plastic material having flexibility. For example, the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be made of polyimide (PI), polyacrylate, polyacetate, or the like. Here, the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be made of the same material, but are not limited thereto. The plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may also be made of different materials from each other.

The moduli of the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be <NUM> times or more higher than that of the lower substrate <NUM>, but is not limited thereto. For example, elastic moduli of the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be <NUM> GPa to <NUM> GPa depending on a transparency. More specifically, when the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> are transparent, the elastic moduli may be <NUM> GPa. Also, when the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> are opaque, the elastic moduli may be <NUM> GPa, but the present disclosure is not limited thereto. Accordingly, the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> may be a plurality of rigid substrates having rigidity as compared with the lower substrate <NUM>.

The COF <NUM> is a film on which various components are disposed on a base film <NUM> having ductility and which supplies signals to the one or more sub-pixels of the active area AA. The COF <NUM> may be bonded to a plurality of pads of the plurality of non-pixel substrates <NUM> disposed in the non-active area NA. Also, the COF <NUM> supplies at least one of a power voltage, a data voltage, a gate voltage or the like to the plurality of sub-pixels of the active area AA through the pads. The COF <NUM> includes the base film <NUM> and a driving IC <NUM>. Further, various components may be additionally disposed thereon.

The base film <NUM> serves to support the driving IC <NUM> of the COF <NUM>. The base film <NUM> may be made of an insulating material. For example, the base film <NUM> may be made of an insulating material having flexibility.

The driving IC <NUM> is configured to process data for displaying an image and a drive signal for processing the data. <FIG> illustrates that the driving IC <NUM> is mounted by a method of the COF <NUM>, but the present disclosure is not limited thereto. The driving IC <NUM> may also be mounted by a Chip On Glass (COG) method, a Tape Carrier Package (TCP) method, or the like.

<FIG> illustrates that a non-pixel substrate <NUM> is disposed in the non-active area NA on an upper side of the active area AA so as to correspond to the pixel substrates <NUM> in a row disposed in the active area AA. Also, <FIG> illustrates that a COF <NUM> is disposed for a non-pixel substrate <NUM>. However, the present disclosure is not limited thereto. That is, a non-pixel substrate <NUM> and a COF <NUM> may be disposed so as to correspond to pixel substrates <NUM> in a plurality of rows.

In the printed circuit board <NUM>, a control unit such as an IC chip, a circuit, or the like may be mounted. Further, in the printed circuit board <NUM>, a memory, a processor, or the like may also be mounted. The printed circuit board <NUM> is configured to transmit a signal for driving a display element from the control unit to the display element. Although <FIG> illustrates that three COFs <NUM> are used, the number of COFs <NUM> is not limited thereto.

Hereinafter, the display device <NUM> according to an exemplary embodiment of the present disclosure will be described in more detail with reference to <FIG> and <FIG>.

<FIG> is an enlarged plan view of the display device according to an exemplary embodiment of the present disclosure. <FIG> is a schematic cross-sectional view of a sub-pixel of <FIG>. For the convenience of description, <FIG> will also be referred to hereinafter.

Referring to <FIG> and <FIG>, the plurality of pixel substrates <NUM> is disposed on the lower substrate <NUM> in the active area AA. The plurality of pixel substrates <NUM> is disposed to be spaced apart from each other on the lower substrate <NUM>. For example, the plurality of pixel substrates <NUM> may be disposed in a matrix form on the lower substrate <NUM> as shown in <FIG> and <FIG>, but is not limited thereto.

Referring to <FIG> and <FIG>, a plurality of sub-pixels SPX constituting a plurality of pixels PX may be disposed in the plurality of pixel substrates <NUM>. Also, gate drivers GD may be mounted on the non-pixel substrates <NUM> located at the left side of the active area AA among the plurality of non-pixel substrates <NUM>. The gate drivers GD may be formed on the non-pixel substrates <NUM> in a Gate In Panel (GIP) manner when various components on the pixel substrates <NUM> are manufactured. Accordingly, various circuit components, such as various transistors, capacitors and lines, constituting the gate drivers GD may be disposed on the plurality of non-pixel substrates <NUM>. However, the present disclosure is not limited thereto. The gate drivers GD may also be mounted in a Chip on Film (COF) manner. The plurality of non-pixel substrates <NUM> may also be disposed in the non-active area NA located on the right side of the active area AA. Further, the gate drivers GD may also be mounted on the plurality of non-pixel substrates <NUM> located on the right side of the active area AA.

Referring to <FIG>, the plurality of non-pixel substrates <NUM> may have a greater size than the plurality of pixel substrates <NUM>. Specifically, each of the plurality of non-pixel substrates <NUM> may have a greater size than each of the plurality of pixel substrates <NUM>. As described above, the gate driver GD is disposed on each of the plurality of non-pixel substrates <NUM>. For example, one stage of the gate driver GD may be disposed on each of the plurality of non-pixel substrates <NUM>. Accordingly, since an area occupied by various circuit components constituting one stage of the gate driver GD is relatively greater than an area of the pixel substrate <NUM> on which the pixel PX is disposed, the size of each of the plurality of non-pixel substrates <NUM> may be greater than the size of each of the plurality of pixel substrates <NUM>.

Referring to <FIG> and <FIG>, the plurality of connection members <NUM> is disposed between the plurality of pixel substrates <NUM>, between the plurality of non-pixel substrates <NUM>, or between the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM>. The plurality of connection members <NUM> serves to connect the pixel substrates <NUM> adjacent to each other, the non-pixel substrates <NUM> adjacent to each other, or the pixel substrates <NUM> and the non-pixel substrates <NUM> adjacent to each other. The plurality of connection members <NUM> may also be referred to as connection substrates. The plurality of connection members <NUM> may be made of the same material as the pixel substrates <NUM> and/or the non-pixel substrates <NUM>. They may be formed integrally with the pixel substrates <NUM> and/or the non-pixel substrates <NUM> at the same time. However, the present disclosure is not limited thereto.

Referring to <FIG>, the plurality of connection members <NUM> has a curved shape. For example, as shown in <FIG>. The plurality of connection members <NUM> may have a sine wave shape. However, the shape of the plurality of connection members <NUM> is not limited thereto. The plurality of connection members <NUM> may have various shapes. For example, the plurality of connection members <NUM> may be extended in a zigzag manner, or a plurality of diamond-shaped substrates may be extended by being connected to each other at their vertices. The number and shape of the plurality of connection members <NUM> shown in <FIG> are provided by way of example. The number and shape of the plurality of connection members <NUM> may vary depending on the design.

Referring to <FIG>, a plurality of connection lines <NUM> is disposed in straight lines on the plurality of pixel substrates <NUM>. Specifically, each of a plurality of first connection lines <NUM> and a plurality of second connection lines <NUM> may be continuously formed on the plurality of connection members <NUM> to connect one end to the other end of the plurality of pixel substrates <NUM>.

Referring to <FIG> and <FIG>, the plurality of connection lines <NUM> on the plurality of connection members <NUM> has a shape corresponding to the plurality of connection members <NUM>. That is, the plurality of connection lines <NUM> may have a sine wave shape. The plurality of connection lines <NUM> electrically connects the pads <NUM> disposed on the pixel substrates <NUM> adjacent to each other among the plurality of pixel substrates <NUM>. Each of plurality of connection lines <NUM> is extended in a curved shape rather than a straight line between the pads <NUM>. However, for example, as shown in <FIG>, the shape of the plurality of connection lines <NUM> is not limited thereto. The plurality of connection lines <NUM> may have various shapes. For example, the plurality of connection lines <NUM> may be extended in a zigzag manner, or a plurality of diamond-shaped lines <NUM> may be extended by being connected to each other at their vertices.

Referring to <FIG>, a plurality of inorganic insulating layers is disposed on the plurality of pixel substrates <NUM>. For example, the plurality of inorganic insulating layers may include a buffer layer <NUM>, a gate insulating layer <NUM> and an interlayer insulating layer <NUM>. However, the present disclosure is not limited thereto. Various inorganic insulating layers may be further disposed on the plurality of pixel substrates <NUM>. One or more of the buffer layer <NUM>, the gate insulating layer <NUM> and the interlayer insulating layer <NUM> may be omitted.

Referring to <FIG>, the buffer layer <NUM> is disposed on the plurality of pixel substrates <NUM>. The buffer layer <NUM> is formed on the plurality of pixel substrates <NUM> to protect various components of the display device <NUM> against permeation of moisture (H<NUM>O) and oxygen (O<NUM>) from the outside of the lower substrate <NUM> and the plurality of pixel substrates <NUM>. The buffer layer <NUM> may be made of an insulating material. For example, the buffer layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or the like. However, the buffer layer <NUM> may be omitted depending on the structure or characteristics of the display device <NUM>.

In this case, the buffer layer <NUM> may be formed only in an area overlapping with the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM>. As described above, the buffer layer <NUM> may be made of an inorganic material. Thus, the buffer layer <NUM> may be easily damaged, such as easily cracked, while the display device <NUM> is stretched. Therefore, the buffer layer <NUM> may not be formed in areas between the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM>. The buffer layer <NUM> may be patterned into the shapes of the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> and formed only on upper portions of the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM>. Accordingly, in the display device <NUM> according to an exemplary embodiment of the present disclosure, the buffer layer <NUM> is formed only in the area overlapping with the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> which are rigid substrates. Thus, it is possible to suppress damage to the buffer layer <NUM> even when the display device <NUM> is deformed, such as bent or stretched.

Referring to <FIG>, a transistor <NUM> including a gate electrode <NUM>, an active layer <NUM>, a source electrode <NUM> and a drain electrode <NUM> is formed on the buffer layer <NUM>.

Referring to <FIG>, the active layer <NUM> is disposed on the buffer layer <NUM>. For example, the active layer <NUM> may be made of an oxide semiconductor. Alternatively, the active layer <NUM> may be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.

The gate insulating layer <NUM> is disposed on the active layer <NUM>. The gate insulating layer <NUM> is configured to electrically insulate the gate electrode <NUM> from the active layer <NUM>. Further, the gate insulating layer <NUM> may be made of an insulating material. For example, the gate insulating layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The gate electrode <NUM> is disposed on the gate insulating layer <NUM>. The gate electrode <NUM> is disposed to overlap with the active layer <NUM>. The gate electrode <NUM> may be made of any one of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, the gate electrode <NUM> may be made of an alloy of two or more of them, or a plurality of layer thereof, but is not limited thereto.

The interlayer insulating layer <NUM> is disposed on the gate electrode <NUM> to cover the gate electrode <NUM>. The interlayer insulating layer <NUM> serves to insulate the gate electrode <NUM> from the source electrode <NUM> and the drain electrode <NUM>. The interlayer insulating layer <NUM> may also be made of an inorganic material like the buffer layer <NUM>. For example, the interlayer insulating layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The source electrode <NUM> and the drain electrode <NUM>, each of which is in contact with the active layer <NUM>, are disposed on the interlayer insulating layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> are disposed to be spaced apart from each other on the same layer. The source electrode <NUM> and the drain electrode <NUM> may be electrically connected to the active layer <NUM> to be in contact with the active layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> may be made of any one of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, the source electrode <NUM> and the drain electrode <NUM> may be made of an alloy of two or more of them, or a plurality of layers thereof, but are not limited thereto.

Also, the gate insulating layer <NUM> and the interlayer insulating layer <NUM> may be patterned and formed only in an area overlapping with the plurality of pixel substrates <NUM>. The gate insulating layer <NUM> and the interlayer insulating layer <NUM> may also be made of an inorganic material like the buffer layer <NUM>. Thus, the gate insulating layer <NUM> and the interlayer insulating layer <NUM> may be easily damaged, such as easily cracked, while the display device <NUM> is stretched. Therefore, the gate insulating layer <NUM> and the interlayer insulating layer <NUM> may not be formed in areas between the plurality of pixel substrates <NUM>. The gate insulating layer <NUM> and the interlayer insulating layer <NUM> may be patterned into the shapes of the plurality of pixel substrates <NUM> and formed only on upper portions of the plurality of pixel substrates <NUM>.

For the convenience of description, <FIG> illustrates only a driving transistor <NUM> among various transistors which may be included in the display device <NUM>. However, a switching transistor, a capacitor and the like may also be included in the display device <NUM>. Further, in the present disclosure, the transistor <NUM> is described as having a coplanar structure, but various types of transistors having a staggered structure or the like may also be used.

Referring to <FIG>, a power pad <NUM> among the plurality of pads <NUM> is disposed on the interlayer insulating layer <NUM>. The power pad <NUM> serves to transmit a power signal to the plurality of sub-pixels SPX. The power signal may be transmitted from the power pad <NUM> to a pixel circuit through a line formed on the pixel substrate <NUM>. The power pad <NUM> may be formed of the same material on the same layer as the source electrode <NUM> and the drain electrode <NUM>, but is not limited thereto.

Referring to <FIG>, a data pad <NUM> among the plurality of pads <NUM> is disposed on the interlayer insulating layer <NUM>. The data pad <NUM> serves to transmit a data signal to the plurality of sub-pixels SPX. The data signal may be transmitted from the data pad <NUM> to the source electrode <NUM> or the drain electrode <NUM> through a data line formed on the pixel substrate <NUM>. The data pad <NUM> may be formed of the same material on the same layer as the source electrode <NUM> and the drain electrode <NUM>, but is not limited thereto.

Referring to <FIG>, a planarization layer <NUM> is formed on the transistor <NUM> and the interlayer insulating layer <NUM>. The planarization layer <NUM> serves to flatten an upper portion of the transistor <NUM>. The planarization layer <NUM> may be formed as a single layer or a plurality of layers and may be made of an organic material. Thus, the planarization layer <NUM> may also be referred to as an organic insulating layer. For example, the planarization layer <NUM> may be made of an acrylic organic material, but is not limited thereto.

Referring to <FIG>, the planarization layer <NUM> is disposed between the plurality of pixel substrates <NUM> and the first connection lines <NUM> so as to cover upper surfaces and side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. Further, the planarization layer <NUM> surrounds the buffer layer <NUM>, the gate insulating layer <NUM> and the interlayer insulating layer <NUM> together with the plurality of pixel substrates <NUM>. Specifically, the planarization layer <NUM> may be disposed to cover an upper surface and a side surface of the interlayer insulating layer <NUM>, a side surface of the gate insulating layer <NUM>, a side surface of the buffer layer <NUM> and a part of upper surfaces of the plurality of pixel substrates <NUM>. Thus, the planarization layer <NUM> between the plurality of pixel substrates <NUM> and the plurality of first connection lines <NUM> may compensate for steps between the side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. Also, the planarization layer <NUM> may enhance adhesion strength between the planarization layer <NUM> and the first connection lines <NUM> disposed on a side surface of the planarization layer <NUM>.

Meanwhile, an incline angle of the side surface of the planarization layer <NUM> may be smaller than those of the side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. However, the present disclosure is not limited thereto.

In some exemplary embodiments, a passivation layer may be formed between the transistor <NUM> and the planarization layer <NUM>. That is, the passivation layer covering the transistor <NUM> may be formed to protect the transistor <NUM> against permeation of moisture and oxygen. The passivation layer may be made of an inorganic material and formed as a single layer or a plurality of layers, but is not limited thereto.

Referring to <FIG> and <FIG>, the connection lines <NUM> refer to lines that electrically connect the pads <NUM> disposed on the plurality of pixel substrates <NUM> or the plurality of non-pixel substrates <NUM>. The connection lines <NUM> are disposed on the pixel substrates <NUM> and the plurality of connection members <NUM>.

The connection lines <NUM> include the first connection lines <NUM> and the second connection lines <NUM>. The first connection lines <NUM> and the second connection lines <NUM> are disposed on the plurality of pixel substrates <NUM> and the plurality of connection members <NUM>. Specifically, the first connection lines <NUM> refer to lines disposed on the connection members <NUM> extended in an X-axis direction, which is a first direction, among the plurality of connection members <NUM> and the plurality of pixel substrates <NUM>. The second connection lines <NUM> refer to lines disposed on the connection members <NUM> extended in a Y-axis direction, which is a second direction, among the plurality of connection members <NUM> and the plurality of pixel substrates <NUM>. The connection lines <NUM> may be made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo). Otherwise, the connection lines <NUM> may have a laminated structure of metal materials such as copper/molybdenum-titanium (Cu/MoTi), titanium/aluminum/titanium (Ti/Al/Ti) or the like, but are not limited thereto.

Referring to <FIG> and <FIG>, the first connection lines <NUM> may connect pads on two pixel substrates <NUM> disposed side by side among the pads on the plurality of pixel substrates <NUM> disposed adjacent to each other in the X-axis direction. Each first connection line <NUM> may serve as a gate line, a light emission signal line, a high-potential power line, or a low-potential power line, but is not limited thereto. For example, the first connection lines <NUM> may serve as power lines for transmitting a high-potential voltage among power voltages as shown in <FIG>. Also, the first connection lines <NUM> may electrically connect the power pads <NUM> on the two pixel substrates <NUM> disposed side by side in the X-axis direction.

Referring to <FIG>, the second connection lines <NUM> may connect two pixel substrates <NUM> disposed side by side among the plurality of pixel substrates <NUM> disposed adjacent to each other in the Y-axis direction. Each second connection line <NUM> may serve as a data line, a high-potential power line, a low-potential power line, or a reference voltage line, but is not limited thereto. For example, the second connection lines <NUM> may serve as data lines and may electrically connect the data lines on the two pixel substrates <NUM> disposed side by side in the Y-axis direction.

Referring to <FIG>, the connection lines <NUM> may further include lines that connect the pads on the plurality of pixel substrates <NUM> and the plurality of non-pixel substrates <NUM> or connect pads on two non-pixel substrates <NUM> disposed side by side among the pads on the plurality of non-pixel substrates <NUM> disposed adjacent to each other in the Y-axis direction.

Each first connection line <NUM> may be in contact with an upper surface and the side surface of the planarization layer <NUM> disposed on the pixel substrate <NUM> and may be extended to an upper surface of the connection member <NUM>. Also, each second connection line <NUM> may be extended from the pixel substrate <NUM> to the connection member <NUM> and an upper surface of an inorganic insulating layer.

Referring to <FIG>, an individual connection pad CP1 and a common connection pad CP2 are disposed on the planarization layer <NUM>. The individual connection pad CP1 and the common connection pad CP2 serve to transmit signals to a plurality of light emitting diodes (LEDs) <NUM>.

Referring to <FIG> and <FIG>, a plurality of individual connection pads CP1 is disposed on the planarization layer <NUM>. The plurality of individual connection pads CP1 may be connected to the transistor <NUM> and may transmit voltages to the plurality of LEDs <NUM>. Thus, the plurality of individual connection pads CP1 may serve as an anode.

The plurality of individual connection pads CP1 may be formed on the planarization layer <NUM> through the same process as the connection lines <NUM>. That is, the plurality of individual connection pads CP1 may be formed of the same material and disposed on the same layer as the connection lines <NUM>, but is not limited thereto.

The number of the plurality of individual connection pads CP1 disposed on one pixel substrate <NUM> may be equal to the number of the plurality of LEDs <NUM> disposed on one pixel substrate <NUM>. For example, if three LEDs <NUM> are disposed on a pixel substrate <NUM> as shown in <FIG>, three individual connection pads CP1 may be disposed on one pixel substrate <NUM> to apply a separate voltage to each of the LEDs <NUM>.

Referring to <FIG> and <FIG>, the common connection pad CP2 is disposed on the planarization layer <NUM>. The common connection pad CP2 may be connected to the first connection line <NUM> and may transmit a voltage to the plurality of LEDs <NUM>. Thus, the common connection pads CP2 may serve as a cathode.

The number of common connection pads CP2 disposed on one pixel substrate <NUM> may be one regardless of the number of the plurality of LEDs <NUM> disposed on one pixel substrate <NUM>. For example, if three LEDs <NUM> are disposed on one pixel substrate <NUM> as shown in <FIG>, the common connection pad CP2 just needs to equally apply low-potential power to the three LEDs <NUM>. Thus, a single common connection pad CP2 may be disposed on one pixel substrate <NUM> and may be electrically connected to the three LEDs <NUM>.

A distance d1 between the individual connection pad CP1 and the common connection pad CP2 may be determined based on a distance between an n-electrode <NUM> and a p-electrode <NUM> of the LED <NUM>. The p-electrode <NUM> of the LED <NUM> needs to be electrically connected to the individual connection pad CP1, and the n-electrode <NUM> of the LED <NUM> needs to be electrically connected to the common connection pad CP2. Any one of the n-electrode <NUM> and the p-electrode <NUM> of the LED <NUM> should not be electrically connected to both the individual connection pad CP1 and the common connection pad CP2. Thus, the distance d1 between the individual connection pad CP1 and the common connection pad CP2 may be determined in consideration of the distance between the n-electrode <NUM> and the p-electrode <NUM> in the LED <NUM>.

A distance d2 between the first connection line <NUM> that is adjacent to the common connection pad CP2 and transmits a high-potential voltage and the common connection pad CP2 may be set to be minimized. Referring to <FIG> and <FIG>, the first connection line <NUM> that transmits a high-potential voltage may be disposed on the planarization layer <NUM> on the lower side of the common connection pad CP2 in the Y-axis direction. As the display device <NUM> is developed to have high resolution, the size of each pixel substrate <NUM> needs to be minimized. Thus, a distance between components disposed on the pixel substrate <NUM> also needs to be minimized in consideration of a process margin or the like. Accordingly, the distance d2 between the first connection line <NUM> that is adjacent to the common connection pad CP2 and transmits a high-potential voltage and the common connection pad CP2 may be designed to a minimum in consideration of a process margin.

Meanwhile, although not illustrated in <FIG>, a bank may be disposed on the individual connection pad CP1, the common connection pad CP2, the connection lines <NUM> and the planarization layer <NUM>. The bank may serve to distinguish the sub-pixels SPX adjacent from each other.

Referring to <FIG>, the LED <NUM> is disposed on the individual connection pad CP1 and the common connection pad CP2. The LED <NUM> includes an n-type layer <NUM>, an active layer <NUM>, a p-type layer <NUM>, the n-electrode <NUM> and the p-electrode <NUM>. The LED <NUM> of the display device <NUM> according to an exemplary embodiment of the present disclosure has a flip-chip structure in which the n-electrode <NUM> and the p-electrode <NUM> are formed on one surface thereof.

The n-type layer <NUM> may be formed by injecting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer <NUM> may be disposed on a separate base substrate which is made of a light emitting material.

The active layer <NUM> is disposed on the n-type layer <NUM>. The active layer <NUM> is a light emitting layer that emits light in the LED <NUM> and may be made of a nitride semiconductor, for example, indium gallium nitride (InGaN). The p-type layer <NUM> is disposed on the active layer <NUM>. The p-type layer <NUM> may be formed by injecting p-type impurities into gallium nitride (GaN).

As described above, the LED <NUM> according to an exemplary embodiment of the present disclosure is manufactured by sequentially laminating the n-type layer <NUM>, the active layer <NUM>, and the p-type layer <NUM>, and then, etching a predetermined area of the layers to thereby form the n-electrode <NUM> and the p-electrode <NUM>. In this case, the predetermined area is a space to separate the n-electrode <NUM> and the p-electrode <NUM> from each other and is etched to expose a part of the n-type layer <NUM>. In other words, a surface of the LED <NUM> on which the n-electrode <NUM> and the p-electrode <NUM> are to be disposed may not be even and may have different levels of height.

As described above, the n-electrode <NUM> is disposed on the etched area, i.e., on the n-type layer <NUM> exposed by etching. The n-electrode <NUM> may be made of a conductive material. Further, the p-electrode <NUM> is disposed on a non-etched area, i.e., on the p-type layer <NUM>. The p-electrode <NUM> may also be made of a conductive material. For example, the p-electrode <NUM> may be made of the same material as the n-electrode <NUM>.

An adhesive layer AD is disposed on upper surfaces of the individual connection pad CP1 and the common connection pad CP2 and between the individual connection pad CP1 and the common connection pad CP2. Thus, the LED <NUM> may be bonded onto the individual connection pad CP1 and the common connection pad CP2. In this case, the n-electrode <NUM> may be disposed on the common connection pad CP2 and the p-electrode <NUM> may be disposed on the individual connection pad CP1.

The adhesive layer AD may be a conductive adhesive layer formed by dispersing conductive balls CB in a base member BR. Thus, when heat or pressure is applied to the adhesive layer AD, the conductive balls CB are electrically connected to have conductive properties in a portion of the adhesive layer AD to which heat or pressure is applied.

The conductive balls CB mixed in the base member BR may serve to electrically connect an electrode of the LED <NUM> to the common connection pad CP2 and the individual connection pad CP1 when the electrode of the LED <NUM> is bonded to the common connection pad CP2 and the individual connection pad CP1. The conductive balls CB may be made of a conductive metal, such as gold (Au), having ductility inside a material, such as nickel (Ni), but is not limited thereto. Also, the conductive balls CB may have a diameter of about <NUM> before bonding, but the present disclosure is not limited thereto. When the electrode of the LED <NUM> is bonded to the connection pads, the material covering the inner conductive metal may be damaged by heat and pressure and the inner conductive metal may be cooled down and hardened. Thus, the electrode of the LED <NUM> may be electrically connected to the connection pads.

The base member BR may be an adhesive member having adhesiveness and insulating properties. The base member BR may be, for example, a thermosetting adhesive, but is not limited thereto.

Referring to <FIG>, for example, the n-electrode <NUM> is electrically connected to the common connection pad CP2 through the adhesive layer AD. Also, the p-electrode <NUM> is electrically connected to the individual connection pad CP1 through the adhesive layer AD. The adhesive layer AD with the conductive balls CB mixed therein may be applied to upper surfaces of the individual connection pad CP1 and the common connection pad CP2 by an inkjet method or the like. Then, the LED <NUM> may be transferred onto the adhesive layer AD. Thereafter, the LED <NUM> may be pressed and heated to thereby electrically connect the individual connection pad CP1 to the p-electrode <NUM> and the common connection pad CP2 to the n-electrode <NUM> through the conductive balls CB. Here, the conductive balls CB may be guided to be disposed only between the n-electrode <NUM> and the common connection pad CP2 and between the p-electrode <NUM> and the individual connection pad CP1. Meanwhile, other portions of the adhesive layer AD excluding a portion of the adhesive layer AD between the n-electrode <NUM> and the common connection pad CP2 and a portion where the conductive balls CB of the adhesive layer AD are disposed between the p-electrode <NUM> and the individual connection pad CP1 have insulating properties. Meanwhile, the adhesive layer AD may also be separately disposed on each of the individual connection pad CP1 and the common connection pad CP2.

As described above, the display device <NUM> according to an exemplary embodiment of the present disclosure has a structure in which the LED <NUM> is disposed on the lower substrate <NUM> on which the transistor <NUM> has been disposed. Thus, when the display device <NUM> is turned on, different levels of voltages applied to each of the individual connection pad CP1 and the common connection pad CP2 are transmitted to the n-electrode <NUM> and the p-electrode <NUM>, respectively. Accordingly, the LED <NUM> emits light.

Referring to <FIG>, an upper substrate US is disposed on the LED <NUM> and the lower substrate <NUM>.

The upper substrate US serves to support various components disposed under the upper substrate US. Specifically, the upper substrate US may be formed by coating and hardening a material of the upper substrate US on the lower substrate <NUM> and the pixel substrate <NUM>. Thus, the upper substrate US may be disposed to be in contact with the lower substrate <NUM>, the pixel substrate <NUM>, the connection member <NUM> and the connection lines <NUM>.

The upper substrate US is a ductile substrate and may be made of a bendable or stretchable insulating material. The upper substrate US is a ductile substrate and may be reversibly expandable and contractible. Also, the upper substrate US may have an elastic modulus in the range of several to hundreds of MPa. Further, the upper substrate US may have a ductile breaking rate of <NUM>% or more. The upper substrate US may have a thickness of <NUM> to <NUM>, but is not limited thereto.

The upper substrate US may be made of the same material as the lower substrate <NUM>. For example, the upper substrate US may be made of silicone rubber such as polydimethylsiloxane (PDMS) and an elastomer such as polyurethane (PU), and polytetrafluoroethylene (PTFE). Thus, the upper substrate US may have flexibility. However, a material of the upper substrate US is not limited thereto.

Meanwhile, although not shown in <FIG>, a polarizing layer may also be disposed on the upper substrate US. The polarizing layer may serve to polarize light incident from the outside of the display device <NUM> and reduce reflection of external light. Further, instead of the polarizing layer, other optical films or the like may be disposed on the upper substrate US.

Hereinafter, the common connection pad CP2 will be described in more detail with reference to <FIG> as well as <FIG>.

<FIG> is a schematic enlarged plan view of a pixel substrate of the display device according to an exemplary embodiment of the present disclosure.

Referring to <FIG> and <FIG>, the common connection pad CP2 includes a lower common connection pad CP21 and an upper common connection pad CP22. That is, the common connection pad CP2 has a multilayer structure.

The lower common connection pad CP21 of the common connection pad CP2 is disposed on the planarization layer <NUM>. The lower common connection pad CP21 may be electrically connected to the first connection line <NUM> and the plurality of LEDs <NUM>.

The lower common connection pad CP21 may be formed through the same process as the first connection line <NUM>. That is, the lower common connection pad CP21 may be formed of the same material on the same layer as the first connection line <NUM>, but is not limited thereto. Here, the lower common connection pad CP21 may be formed integrally with a first connection line <NUM> for transmitting low-potential power among the first connection lines <NUM>. However, the plurality of LEDs <NUM> needs to be disposed on the lower common connection pad CP21 and electrically connected. Therefore, the common connection pad CP2 may have a greater width than the first connection line <NUM>. The lower common connection pad CP21 may be made of, for example, copper (Cu) or the like, but is not limited thereto. A material of the lower common connection pad CP21 may vary depending on the design. Here, the lower common connection pad CP21 may have a thickness of from about <NUM>Å to about <NUM>Å, but is not limited thereto.

The upper common connection pad CP22 of the common connection pad CP2 is disposed on the lower common connection pad CP21. Here, the upper common connection pad CP22 may be disposed on an edge of the lower common connection pad CP21. That is, as shown in <FIG>, the upper common connection pad CP22 may be disposed in a closed curve on the edge of the lower common connection pad CP21. However, the present disclosure is not limited thereto. The upper common connection pad CP22 may also be disposed in a plurality of patterns on the edge of the lower common connection pad CP21. Although <FIG> illustrates that the upper common connection pad CP22 has a rectangular cross-sectional shape, the cross-sectional shape of the upper common connection pad CP22 is not limited thereto.

The upper common connection pad CP22 may be made of a different material from the lower common connection pad CP21. Here, the upper common connection pad CP22 may be made of a material whose adhesiveness to electrodes of the plurality of LEDs <NUM> is higher than its adhesiveness to the lower common connection pad CP21. Thus, the upper common connection pad CP22 may be easily separated from the lower common connection pad CP21 during a process of repairing the plurality of LEDs <NUM>.

For example, if the lower common connection pad CP21 is made of copper (Cu) and the electrodes of the plurality of LEDs <NUM> are made of gold (Au), the upper common connection pad CP22 may be made of gold (Au). That is, a material of the upper common connection pad CP22 may be different from a material of the lower common connection pad CP21 and may be the same as a material of the electrodes of the plurality of LEDs <NUM>. Accordingly, due to a high adhesiveness between the homogeneous materials, the upper common connection pad CP22 may have a higher adhesiveness to the electrodes of the plurality of LEDs <NUM> than the lower common connection pad CP21. The upper common connection pad CP22 may be made of, for example, gold (Au), titanium (Ti), aluminum (Al) or molybdenum (Mo), but is not limited thereto. Here, the upper common connection pad CP22 may have a thickness of about <NUM>Å, but is not limited thereto.

While the display device <NUM> is manufactured, if misalignment occurs during a transfer process for electrically connecting the individual connection pad CP1 and the common connection pad CP2 to the plurality of LEDs <NUM>, a repair process for removing a misaligned LED <NUM> and transferring a new LED <NUM> may be added. Here, if the adhesiveness between the common connection pad CP2 bonded to the plurality of LEDs <NUM> and the electrodes of the plurality of LEDs <NUM> is too high, the common connection pad CP2 may be torn off from the lower substrate <NUM> together with the plurality of LEDs <NUM> while the LED <NUM> is removed. That is, the common connection pad CP2 is removed with a misaligned LED <NUM> as described above. In this case, even if a new LED <NUM> is transferred, it cannot be driven. Therefore, the entire display device <NUM> becomes defective.

Accordingly, in the display device <NUM> according to an exemplary embodiment of the present disclosure, the common connection pad CP2 has a multilayer structure including the lower common connection pad CP21 and the upper common connection pad CP22. Thus, during a repair process, the plurality of LEDs <NUM> may be easily removed from the common connection pad CP2. Specifically, the upper common connection pad CP22 made of a material whose adhesiveness to electrodes of the plurality of LEDs <NUM> is higher than its adhesiveness to the lower common connection pad CP21 is disposed on the lower common connection pad CP21. Therefore, during a repair process, the upper common connection pad CP22 may be easily separated from the lower common connection pad CP21 together with the plurality of LEDs <NUM>. Also, in some processes, all the upper common connection pad CP22 and the lower common connection pad CP21 may be disposed on the side of the lower substrate <NUM> and only the LEDs <NUM> may be separated. Thus, in the display device <NUM> according to an exemplary embodiment of the present disclosure, when a misaligned LED <NUM> is repaired, tearing-off of the common connection pad CP2 with the LED <NUM> from the lower substrate <NUM> may be minimized.

Also, while the display device <NUM> is manufactured, the adhesive layer AD for bonding and electrically connecting the plurality of LEDs <NUM> to the individual connection pad CP1 and the common connection pad CP2 at the same time is used during the transfer process for electrically connecting the individual connection pad CP1 and the common connection pad CP2 to the plurality of LEDs <NUM>. The adhesive layer AD may be formed in a liquid state on the individual connection pad CP1 and the common connection pad CP2 and then hardened by heat and/or pressure. Thus, while the adhesive layer AD is in a liquid state, the plurality of LEDs <NUM> may be moved along with movement of the adhesive layer AD. Therefore, misalignment of the plurality of LEDs <NUM> in relation to the individual connection pad CP1 and the common connection pad CP2 may occur. Also, when the adhesive layer AD is moved, an LED <NUM> may be misaligned between the common connection pad CP2 having a relatively small distance and the first connection line <NUM> for transmitting a high-potential voltage. Thus, the common connection pad CP2 and the first connection line <NUM> may be electrically connected by the electrode of the LED <NUM>. In this case, a dark spot may occur in a sub-pixel SPX including the LED <NUM>.

Accordingly, in the display device <NUM> according to the present invention, the common connection pad CP2 has a multilayer structure including the lower common connection pad CP21 and the upper common connection pad CP22. Thus, it is possible to minimize misalignment of an LED <NUM> caused by movement of the adhesive layer AD. Specifically, the upper common connection pad CP22 may be disposed on the edge of the lower common connection pad CP21 along the edge of the lower common connection pad CP21, and the common connection pad CP2 may have a step difference. Therefore, even if the adhesive layer AD is moved, movement of the conductive balls CB in the adhesive layer AD and the electrodes of the LEDs <NUM> may be restricted by the upper common connection pad CP22. Accordingly, in the display device <NUM> according to an exemplary embodiment of the present disclosure, the common connection pad CP2 having a step structure may be used to suppress the occurrence of misalignment of the LEDs <NUM> and the occurrence of a dark spot caused by misalignment.

<FIG> is a schematic cross-sectional view of one pixel substrate of a display device according to another exemplary embodiment of the present disclosure. <FIG> is an enlarged plan view of one pixel substrate of the display device according to another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> and <FIG> is substantially the same as the display device <NUM> shown in <FIG> except for the individual connection pad CP1. Thus, a redundant description thereof will be omitted.

Referring to <FIG> and <FIG>, the individual connection pad CP1 of the display device <NUM> according to another exemplary embodiment of the present disclosure includes a plurality of lower individual connection pads CP11 and a plurality of upper individual connection pads CP12. An upper individual connection pad CP12 may be disposed on a lower individual connection pad CP11. Also, the upper individual connection pad CP12 may be formed in a shape corresponding to the upper common connection pad CP22 and disposed on the lower individual connection pad CP11. Thus, the upper individual connection pad CP12 may be disposed on an edge of the lower individual connection pad CP11, and the plurality of upper individual connection pads CP12 may be in partial contact with the electrodes of the plurality of LEDs <NUM>.

In the multilayer structure of the individual connection pad CP1, the plurality of lower individual connection pads CP11 is disposed on the planarization layer <NUM>. The plurality of lower individual connection pads CP11 may be electrically connected to the first connection line <NUM> and the plurality of LEDs <NUM>.

The plurality of lower individual connection pads CP11 may be formed through the same process as the lower common connection pad CP21. That is, the plurality of lower individual connection pads CP11 may be formed of the same material on the same layer as the lower common connection pad CP21, but is not limited thereto. The plurality of lower individual connection pads CP11 may be made of, for example, copper (Cu) or the like, but is not limited thereto. A material of the plurality of lower individual connection pads CP11 may vary depending on the design. Here, the plurality of lower individual connection pads CP11 may have a thickness of from about <NUM>Å to about <NUM>Å, but is not limited thereto.

The upper individual connection pad CP12 is disposed on the lower individual connection pad CP11. Here, the upper individual connection pad CP12 may be disposed on an edge of the lower individual connection pad CP11. That is, as shown in <FIG>, the upper individual connection pad CP12 may be disposed in a closed curve on the edge of the lower individual connection pad CP11. However, the present disclosure is not limited thereto. The upper individual connection pad CP12 may also be disposed in a plurality of patterns on the edge of the lower individual connection pad CP11. The upper individual connection pad CP12 with the plurality of patterns corresponding to those of the upper common connection pad CP22 may be disposed on the lower individual connection pad CP11.

The upper individual connection pad CP12 may be made of a different material from the lower individual connection pad CP11. Here, the upper individual connection pad CP12 may be made of a material whose adhesiveness to electrodes of the plurality of LEDs <NUM> is higher than its adhesiveness to the lower individual connection pad CP11. Thus, the upper individual connection pad CP12 may be easily separated from the lower individual connection pad CP11 during a process of repairing the plurality of LEDs <NUM>.

For example, if the lower individual connection pad CP11 is made of copper (Cu) and the electrodes of the plurality of LEDs <NUM> are made of gold (Au), the upper individual connection pad CP12 may be made of gold (Au). That is, a material of the upper individual connection pad CP12 may be different from a material of the lower individual connection pad CP11 and may be the same as a material of the electrodes of the plurality of LEDs <NUM>. Accordingly, due to a high adhesiveness between the homogeneous materials, the upper individual connection pad CP12 may have a higher adhesiveness to the electrodes of the LEDs <NUM> than the lower individual connection pad CP11. The upper individual connection pad CP12 may be made of, for example, gold (Au), titanium (Ti), aluminum (Al) or molybdenum (Mo), but is not limited thereto. Here, the upper individual connection pad CP12 may have a thickness of about <NUM>Å, but is not limited thereto.

In the display device <NUM> according to another exemplary embodiment of the present disclosure, the plurality of individual connection pads CP1 has a multilayer structure including the plurality of lower individual connection pads CP11 and the plurality of upper individual connection pads CP12. Thus, during a repair process, the plurality of LEDs <NUM> may be easily removed from the plurality of individual connection pads CP1. Specifically, the upper individual connection pad CP12 made of a material whose adhesiveness to electrodes of the plurality of LEDs <NUM> is higher than its adhesiveness to the lower individual connection pad CP11 is disposed on the lower individual connection pad CP11. Therefore, during a repair process, the upper individual connection pad CP12 may be easily separated from the lower individual connection pad CP11 together with the plurality of LEDs <NUM>. Also, in some processes, all the plurality of upper individual connection pads CP12 and the plurality of lower individual connection pads CP11 may be disposed on the side of the lower substrate <NUM> and only the LEDs <NUM> may be separated. Thus, in the display device <NUM> according to another exemplary embodiment of the present disclosure, when a misaligned LED <NUM> is repaired, tearing-off of the individual connection pad CP1 with the LED <NUM> from the lower substrate <NUM> may be minimized.

Also, in the display device <NUM> according to another exemplary embodiment of the present disclosure, the plurality of individual connection pads CP1 has a multilayer structure including the plurality of lower individual connection pads CP11 and the plurality of upper individual connection pads CP12. Thus, it is possible to minimize misalignment of an LED <NUM> caused by movement of the adhesive layer AD. Specifically, the upper individual connection pad CP12 may be disposed on the edge of the lower individual connection pad CP11 along the edge of the lower individual connection pad CP11, and the individual connection pad CP1 may have a step difference. Therefore, even if the adhesive layer AD is moved, movement of the conductive balls CB in the adhesive layer AD and the electrodes of the LEDs <NUM> may be restricted by the plurality of upper individual connection pads CP12. Accordingly, in the display device <NUM> according to another exemplary embodiment of the present disclosure, the plurality of individual connection pads CP1 having a step structure may be used to suppress the occurrence of misalignment of the LEDs <NUM> and the occurrence of a dark spot caused by misalignment.

<FIG> is an enlarged plan view of one pixel substrate of a display device according to yet another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> and <FIG> except for a shape of the upper common connection pad CP22. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, the upper common connection pad CP22 of the display device <NUM> according to yet another exemplary embodiment of the present disclosure may be further disposed on the lower common connection pad CP21 corresponding to a space between the plurality of individual connection pads CP1. Accordingly, the upper common connection pad CP22 may be further disposed in a space between the plurality of LEDs <NUM>.

In the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the upper common connection pad CP22 is further disposed on the lower common connection pad CP21 corresponding to the space between the plurality of individual connection pads CP1. Thus, a frictional force may be supplied to the electrodes of the plurality of LEDs <NUM>. Accordingly, the electrodes of the plurality of LEDs <NUM> may not deviate from an area where the upper common connection pad CP22 is located. For example, even if the plurality of LEDs <NUM> slides in the left and right directions from the state shown in <FIG>, they may be guided to move within an area defined by the upper common connection pad CP22. Thus, it is possible to suppress deviation of the plurality of LEDs <NUM> from the upper common connection pad CP22. Therefore, even if the adhesive layer AD is moved, movement of the conductive balls CB in the adhesive layer AD and the electrodes of the LEDs <NUM> may be restricted by the upper common connection pad CP22. Accordingly, in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the upper common connection pad CP22 is further disposed at a position corresponding to the space between the plurality of individual connection pads CP1. Thus, it is possible to suppress the occurrence of misalignment of the LEDs <NUM>.

<FIG> is an enlarged plan view of one pixel substrate of a display device <NUM> according to still another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> except for a shape of the upper common connection pad CP22. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, the upper common connection pad CP22 of the display device <NUM> according to still another exemplary embodiment of the present disclosure may have a mesh form. That is, the upper common connection pad CP22 may be disposed in a mesh form on the lower common connection pad CP21. Here, the upper common connection pad CP22 may be extended on the lower common connection pad CP21 in a vertical direction and the left and right directions from the state shown in <FIG>. For example, the upper common connection pad CP22 may include a portion disposed on the lower common connection pad CP21 to be parallel with the extension direction of the common connection pad CP2. Also, the upper common connection pad CP22 may include a portion disposed on the lower common connection pad CP21 to be perpendicular to the extension direction of the common connection pad CP2. The upper common connection pad CP22 of the display device <NUM> according to still another exemplary embodiment of the present disclosure is disposed in a mesh form on the lower common connection pad CP21. Thus, a greater frictional force may be supplied to the electrodes of the plurality of LEDs <NUM>. Accordingly, the electrodes of the plurality of LEDs <NUM> may not deviate from an area where the upper common connection pad CP22 is located. For example, even if the plurality of LEDs <NUM> slides, the conductive balls CB may be caught in holes of a mesh pattern of the upper common connection pad CP22. Thus, the plurality of LEDs may be moved within an area defined by the upper common connection pad CP22, and it is possible to suppress deviation of the plurality of LEDs <NUM> from the common connection pad CP2. Therefore, even if the adhesive layer AD is moved, movement of the conductive balls CB in the adhesive layer AD and the electrodes of the LEDs <NUM> may be restricted by the upper common connection pad CP22. Accordingly, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the upper common connection pad CP22 is disposed in a mesh form on the lower common connection pad CP21. Thus, it is possible to suppress the occurrence of misalignment of the LEDs <NUM>.

<FIG> is a schematic cross-sectional view of one pixel substrate of a display device according to still another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> and <FIG> except for a placement of an insulating layer IL1. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, the display device <NUM> according to still another exemplary embodiment of the present disclosure may include the insulating layer IL1. The insulating layer IL1 may be disposed on the first connection line <NUM>. Specifically, the insulating layer IL1 may be disposed on a power line PL for transmitting high-potential power among the first connection lines <NUM>.

The insulating layer IL1 may be made of a material having insulating properties. The insulating layer IL1 may be an inorganic layer of, for example, silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. A material of the insulating layer IL1 may vary depending on the design. Here, the insulating layer IL1 may have a thickness of from about <NUM>Å to about <NUM>Å, but is not limited thereto.

The insulating layer IL1 may include a plurality of insulating patterns. The plurality of insulating patterns of the insulating layer IL1 may have various shapes such as a pillar shape, a line shape, or a mesh shape.

The distance between the plurality of insulating patterns of the insulating layer IL1 may be smaller than the size of a conductive ball CB in the adhesive layer AD. For example, the distance between the plurality of insulating patterns of the insulating layer IL1 may be smaller than the radius or diameter of a conductive ball CB in the adhesive layer AD.

In the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL1 including the plurality of insulating patterns is disposed on the first connection line <NUM> serving as a high-potential power line. Thus, it is possible to minimize the occurrence of misalignment of the LEDs <NUM>. Specifically, if the LEDs <NUM> are moved toward the first connection line <NUM> for transmitting high-potential power by movement of the adhesive layer AD, an insulating pattern disposed most adjacent to the common connection pad CP2 among the plurality of insulating patterns may primarily suppress movement of the LEDs <NUM>. Also, all the plurality of insulating patterns supply a frictional force when the LEDs <NUM> are moved on the insulating layer IL1 and thus may restrict movement of the LEDs <NUM>. Accordingly, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, it is possible to suppress the occurrence of misalignment of the LEDs <NUM> caused by movement of the adhesive layer AD.

Further, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL1 is disposed on the first connection line <NUM> serving as a high-potential power line PL. Thus, even if the plurality of LEDs <NUM> is misaligned, it is possible to suppress connection of the LEDs <NUM> to the first connection line <NUM> serving as a power line for transmitting high-potential power. Even if the LEDs <NUM> are disposed on the first connection line <NUM> serving as a power line for transmitting high-potential power by movement of the adhesive layer AD, the LEDs <NUM> may not be connected to the first connection line <NUM> serving as a power line for transmitting high-potential power by the insulating layer IL1 disposed on the first connection line <NUM>. Accordingly, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL1 may be used to suppress the occurrence of a dark spot caused by connection of the LEDs <NUM> to both the common connection pad CP2 and the first connection line <NUM> serving as a power line for transmitting high-potential power.

<FIG> is a schematic cross-sectional view of one pixel substrate of a display device according to still another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> except for an insulating layer IL2. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, the display device <NUM> according to still another exemplary embodiment of the present disclosure may include the insulating layer IL2. The insulating layer IL2 may be disposed on the first connection line <NUM>. Specifically, the insulating layer IL2 may be disposed on a power line for transmitting high-potential power among the first connection lines <NUM>.

The insulating layer IL2 may have a stepped upper surface. That is, in the insulating layer IL2, a portion relatively adjacent to the common connection pad CP2 may have a smaller height than a portion relatively far from the common connection pad CP2. However, the present disclosure is not limited thereto. The insulating layer IL2 may have an inclined upper surface. In this case, the insulating layer IL2 may have an inclined upper surface whose height gradually increases as the distance from the common connection pad CP2 increases.

In the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL2 is disposed on the first connection line <NUM> serving as a high-potential power line. Thus, it is possible to minimize the occurrence of misalignment of the LEDs <NUM>. Specifically, if the LEDs <NUM> are moved toward the first connection line <NUM> for transmitting high-potential power by movement of the adhesive layer AD, a portion of the insulating layer IL2 which is relatively adjacent to the common connection pad CP2 may primarily suppress movement of the LEDs <NUM>. Also, if the LEDs <NUM> are moved onto the portion of the insulating layer IL2 which is relatively adj acent to the common connection pad CP2, a portion of the insulating layer IL2 which is relatively far from the common connection pad CP2 and has a greater height may secondarily suppress movement of the LEDs <NUM>. Accordingly, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, it is possible to suppress the occurrence of misalignment of the LEDs <NUM> caused by movement of the adhesive layer AD.

Further, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL2 is disposed on the first connection line <NUM> serving as a high-potential power line. Thus, even if the plurality of LEDs <NUM> is misaligned, it is possible to suppress connection of the LEDs <NUM> to the first connection line <NUM> serving as a power line for transmitting high-potential power. That is, even if the LEDs <NUM> are disposed on the first connection line <NUM> serving as a power line for transmitting high-potential power by movement of the adhesive layer AD, the LEDs <NUM> may not be connected to the first connection line <NUM> serving as a power line for transmitting high-potential power by the insulating layer IL2 disposed on the first connection line <NUM>. Accordingly, it is possible to suppress the occurrence of a dark spot caused by connection of the LEDs <NUM> to both the common connection pad CP2 and the first connection line <NUM> serving as a power line for transmitting high-potential power.

<FIG> is a schematic cross-sectional view of one pixel substrate of a display device according to still another exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> except for an insulating layer IL3. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, the display device <NUM> according to still another exemplary embodiment of the present disclosure may include the insulating layer IL3. The insulating layer IL3 may be disposed on the first connection line <NUM>. Specifically, the insulating layer IL3 may be disposed on a power line for transmitting high-potential power among the first connection lines <NUM>.

The insulating layer IL3 may be disposed to cover an upper surface and a side surface of the first connection line <NUM> serving as a power line PL for transmitting high-potential power. Specifically, the insulating layer IL3 may be disposed to cover the upper surface of the first connection line <NUM> serving as a power line PL for transmitting high-potential power and the side surface of the first connection line <NUM> adjacent to the common connection pad CP2. That is, the insulating layer IL3 may insulate the LEDs <NUM> from the upper surface and the side surface of the first connection line <NUM> serving as a power line for transmitting high-potential power.

In the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL3 is disposed on the upper surface and the side surface of the first connection line <NUM> serving as a high-potential power line. Thus, it is possible to minimize the occurrence of misalignment of the LEDs <NUM>. Specifically, if the LEDs <NUM> are moved toward the first connection line <NUM> serving as a power line for transmitting high-potential power by movement of the adhesive layer AD, the insulating layer IL3 may suppress movement of the LEDs <NUM>. Accordingly, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, it is possible to suppress the occurrence of misalignment of the LEDs <NUM> caused by movement of the adhesive layer AD.

Further, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the insulating layer IL3 is disposed on the upper surface and the side surface of the first connection line <NUM> serving as a high-potential power line. Thus, even if the plurality of LEDs <NUM> is misaligned, it is possible to suppress connection of the LEDs <NUM> to the first connection line <NUM> serving as a power line for transmitting high-potential power. That is, even if the LEDs <NUM> are moved toward the first connection line <NUM> serving as a power line for transmitting high-potential power by movement of the adhesive layer AD, the LEDs <NUM> may not be connected to the first connection line <NUM> serving as a power line for transmitting high-potential power by the insulating layer IL3 disposed on the upper surface of the first connection line <NUM> and the side surface of the first connection line <NUM> adjacent to the common connection pad CP2. Accordingly, it is possible to suppress the occurrence of a dark spot caused by connection of the LEDs <NUM> to both the common connection pad CP2 and the first connection line <NUM> serving as a power line for transmitting high-potential power.

<FIG> is a schematic cross-sectional view illustrating that an upper common connection pad has been removed through a repair process of a display device according to an exemplary embodiment of the present disclosure. A display device <NUM> shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG> except that the upper common connection pad CP22 is removed. Thus, a redundant description thereof will be omitted.

Referring to <FIG>, in the display device <NUM> corresponding to the display device <NUM> shown in <FIG> after a repair process, the upper common connection pad CP22 of the common connection pad CP2 is removed together with the LEDs <NUM>. Thus, the common connection pad CP2 may have a monolayer structure.

In some of the plurality of sub-pixels SPX of the display device <NUM> after a repair process, the common connection pad CP2 may be a single layer as shown in <FIG>. However, in other sub-pixels SPX, only the LEDs <NUM> are removed during a repair process and the upper common connection pad CP22 remains. Thus, these sub-pixels SPX may be put in a state as shown in <FIG>.

Also, in some of the plurality of sub-pixels SPX of the display device <NUM> after a repair process, only a part of the upper common connection pad CP22 may be removed together with the LEDs <NUM> and the other part may remain.

<FIG> is an enlarged plan view of one pixel substrate of a display device according to still another embodiment which is not part of the invention. <FIG> is a schematic cross-sectional view of one pixel substrate of the display device according to still another embodiment which is not part of the invention. A display device <NUM> shown in <FIG> and <FIG> is substantially the same as the display device <NUM> shown in <FIG> except that the upper common connection pad CP22 is removed, and the adhesive layer AD is disposed differently. Thus, a redundant description thereof will be omitted.

Referring to <FIG> and <FIG>, the adhesive layer AD is used to electrically connect the plurality of individual connection pads CP1 and the common connection pad CP2 to the plurality of LEDs <NUM>.

The adhesive layer AD is disposed to cover the entire upper surface of the planarization layer <NUM>. The adhesive layer AD is disposed on the entire upper surface of the planarization layer <NUM> as well as on the upper surfaces of the individual connection pads CP1 and the common connection pad CP2. Thus, the LEDs <NUM> can be bonded onto the individual connection pads CP1 and the common connection pad CP2. Here, the n-electrode <NUM> may be disposed on the common connection pad CP2, and the p-electrode <NUM> may be disposed on the individual connection pads CP1.

The adhesive layer AD includes the plurality of conductive balls CB and the base member BR. The adhesive layer AD may be a conductive adhesive layer formed by dispersing the plurality of conductive balls CB in the base member BR. plurality of conductive balls CB dispersed in the base member BR may serve to electrically connect an electrode of the LED <NUM> to the common connection pad CP2 and the individual connection pad CP1 when the electrode of the LED <NUM> is bonded to the common connection pad CP2 and the individual connection pad CP1.

In some cases, the plurality of conductive balls CB is disposed in a single layer. As shown in <FIG>, the conductive balls CB are dispersed in the base member BR. The conductive balls CB are spaced apart at a predetermined distance from each other in the single layer. For example, the distance between the conductive balls CB may be from <NUM> to <NUM> but is not limited thereto. Herein, the distance between the conductive balls CB refers to the shortest distance between a conductive hall CB and another conductive hall CB.

Since the plurality of conductive balls CB is spaced apart from each other, the plurality of conductive balls CB is not electrically connected to each other. That is, the plurality of conductive balls CB is spaced apart from each other in parallel with the upper surface of the planarization layer <NUM> and thus is not electrically connected to each other. Also, the plurality of conductive balls CB electrically connects the plurality of individual connection pads CP1 and the common connection pad CP2 to the plurality of LEDs <NUM>. That is, the plurality of conductive balls CB is in contact with the electrodes of the LEDs <NUM> and the connection pads in a direction perpendicular to the upper surface of the planarization layer <NUM>. Thus, the plurality of conductive balls CB may electrically connect the electrodes of the LEDs <NUM> to the connection pads.

The base member BR may be an adhesive member having adhesiveness and insulating properties. The adhesive layer AD except a portion where the conductive balls CB are disposed has insulating properties. The base member BR is coated on the entire upper surface of the planarization layer <NUM> so that the plurality of LEDs <NUM> can be fixed in position.

The adhesive layer AD has a smaller thickness or height H1 than the thickness or height H2 of the planarization layer <NUM> (see for example, <FIG>). If the adhesive layer AD has a greater thickness than the planarization layer <NUM>, the adhesive layer AD may flow down to the outside of the upper surface of the planarization layer <NUM>. Thus, misalignment of the LEDs <NUM> may occur. That is, movement of the adhesive layer AD may be regulated by a step of the planarization layer <NUM> and a thickness of the adhesive layer AD. Also, the adhesive layer AD may be disposed on the entire upper surface of the planarization layer <NUM> so that the edges of the upper surface of the planarization layer <NUM> coincide with the edges of the adhesive layer AD. Meanwhile, a side surface of the adhesive layer AD may be perpendicular to the upper surface of the planarization layer <NUM> or inclined to the upper surface of the planarization layer <NUM> but is not limited thereto.

In the display device <NUM> according to still another embodiment which is not part of the invention, the plurality of conductive balls CB included in the adhesive layer AD is spaced apart from each other in a single layer. Thus, it is possible to suppress the occurrence of a short or open of the LED <NUM>. Also, in the display device <NUM> according to still another embodiment which is not part of the invention, the adhesive layer AD is disposed on the entire upper surface of the planarization layer <NUM> instead of being selectively disposed only on the connection pads overlapping with the plurality of LEDs <NUM>. Thus, it is possible to minimize a transfer efficiency decrease of the LED <NUM> and defective driving of the LED <NUM> caused by non-uniform placement of the adhesive layer AD.

Hereinafter, a method of manufacturing the display device <NUM> will be described with reference to <FIG>.

<FIG> are schematic cross-sectional views illustrating a method of manufacturing the display device. The display device shown in <FIG> is substantially the same as the display device <NUM> shown in <FIG>. Thus, a redundant description thereof will be omitted.

First, referring to <FIG>, a first transfer substrate <NUM>, on which the adhesive layer AD including the base member BR and the plurality of conductive balls CB dispersed in the base member BR is disposed, is prepared.

Then, the first transfer substrate <NUM> is brought close to an upper portion of the lower substrate <NUM>, on which the planarization layer <NUM> is disposed, and the adhesive layer AD is placed on an upper portion of the planarization layer <NUM>. Here, the first transfer substrate <NUM> may be in the form of a film but is not limited thereto While the first transfer substrate <NUM> and the lower substrate <NUM> are kept in a flat state, the adhesive layer AD is pressed for a predetermined period of time to be bonded onto the planarization layer <NUM>.

Then, referring to <FIG>, the first transfer substrate <NUM> is separated from the adhesive layer AD. Only a portion of the first transfer substrate <NUM>, on which the planarization layer <NUM> is disposed, is locally heated so that the adhesive layer AD is bonded only onto the planarization layer <NUM>. For example, a heating bar is brought into contact with an area corresponding to the planarization layer <NUM> while being pressed thereto to separate only the adhesive layer AD bonded to the upper surface of the planarization layer <NUM> from the first transfer substrate <NUM>. However, the present disclosure is not limited thereto. Then, when the first transfer substrate <NUM> is removed, the adhesive layer AD is disposed only on the planarization layer <NUM>.

Then, referring to <FIG>, a second transfer substrate <NUM>, on which the plurality of LEDs <NUM> is disposed, is brought close to an upper portion of the adhesive layer AD and the plurality of LEDs <NUM> is bonded to the upper portion of the adhesive layer AD. For example, the plurality of LEDs <NUM> is transferred in a state where the plurality of LEDs <NUM> is bonded by an adhesive member on the second transfer substrate <NUM>. The plurality of LEDs <NUM> disposed on the second transfer substrate <NUM> is bonded to the upper portion of the adhesive layer AD so that the plurality of LEDs <NUM> is located above the connection pads of the lower substrate <NUM>. When a laser is irradiated to the plurality of LEDs <NUM>, the adhesive member is removed, and the plurality of LEDs <NUM> is separated from the second transfer substrate <NUM> and fixed onto the connection pads by the adhesive layer AD.

Then, referring to <FIG>, the upper substrate US may be formed by coating and hardening a bendable or stretchable insulating material on the plurality of LEDs <NUM>. Thus, the upper substrate US may be disposed to be in contact with the lower substrate <NUM>, the pixel substrate <NUM>, the connection member <NUM> and the connection lines <NUM>. As a result, the display device <NUM> shown in <FIG> can be manufactured.

In general, when an adhesive layer is transferred, an inkjet printing process is used to selectively transfer the adhesive layer only onto an area where an electrode of a light emitting diode is disposed or a connection pad disposed on a planarization layer. However, if the adhesive layer is transferred through the inkjet printing process, the transfer is limited due to a high viscosity of the adhesive layer. Also, the inkjet printing process is a complicated process and requires a costly device.

However, according to the method of manufacturing the display device <NUM>, the adhesive layer AD is bonded onto the planarization layer <NUM> and then the LEDs is bonded thereto. Thus, it is possible to simplify a manufacturing process and reduce manufacturing time and cost. That is, an adhesive layer has been disposed only on a part of a planarization layer, whereas the adhesive layer AD is disposed on the entire upper surface of the planarization layer <NUM> in a greater area. Therefore, the adhesive layer AD can be more easily bonded, and the LEDs <NUM> can be easily fixed in position by the adhesive layer AD. Also, the adhesive layer AD is evenly coated on the planarization layer <NUM>. Therefore, it is possible to improve a transfer efficiency of the LEDs <NUM>, reduce manufacturing time and minimize defective driving of the LEDs <NUM>.

Claim 1:
A display device, comprising:
a lower substrate (<NUM>);
a plurality of pixel substrates (<NUM>) disposed on the lower substrate (<NUM>);
a plurality of transistors (<NUM>) disposed on the plurality of pixel substrates (<NUM>);
a planarization layer (<NUM>) disposed on the plurality of pixel substrates (<NUM>) to cover upper portions of the plurality of transistors (<NUM>);
a plurality of individual connection pads (CP1) and a common connection pad (CP2) disposed on the planarization layer (<NUM>); and
a plurality of light emitting diodes (<NUM>) each comprising two electrodes (<NUM>,<NUM>) disposed on the plurality of individual connection pads (CP1) and the common connection pad (CP2),
characterized in that
at least one of the plurality of individual connection pads (CP1) and the common connection pad (CP2) has a multilayer structure, wherein the common connection pad (CP2) includes a lower common connection pad (CP21) disposed on the planarization layer (<NUM>) and an upper common connection pad (CP22) disposed on the lower common connection pad (CP21).