Patent Description:
Prior art nanowires and FinFET-based multigate devices are interesting device architectures for biosensing applications. Such devices show a high sensitivity, since the binding of biological molecules at the surface thereof can significantly affect the conduction path in these devices, does influencing measurement results. They sense biomolecules at a surface (captured from a solution) by exposing the gate of the device to a solution comprising the charged biomolecules.

A FinFET device acts as a transducer, translating and amplifying the difference in charge to a difference in conductance. The gate often comprises antibodies which are able to bind with particular biomolecules. In order to increase the sensitivity, these devices are often operated in the sub-threshold regime by applying a voltage on a back gate. In the sub-threshold regime the current through the drain is exponentially dependent on the voltage of the gate and therefore in this region the sensitivity is increased.

So far, the use of nanowires, both silicon and non-silicon based, has been limited to label-free sensing of biomolecules. Nowadays, there is also an increasing need for techniques that can sequence DNA in a very quick and cheap way. Sequencing involves determining the order of the bases Adenine, Cytosine, Guanine and Thymine in a gene or on a chromosome. Typically optics-based sequencing methods are used. These methods, although considered to have a very high accuracy, are very expensive, and hence are to be avoided if possible. Single-molecule sequencing technologies, such as nano-pores, can potentially be used to sequence long strands of DNA without labels or amplification. The main challenge is to distinguish the different nucleobases, as typically the difference is very small and for that purpose the controllability and reproducibility of nanopores is key.

<CIT> and <CIT> disclose FET sensors for biosensing applications. In <CIT> a FET sensor is described which comprises a gate biasing electrode in a fluid path of said sensor. This gate biasing electrode may be located near the FET sensor and allows to bias the FET into the subthreshold region.

<CIT> discloses a FET wherein a nanopore is etched through the channel region. Moving DNA through the nanopore results in a modulation of the source-drain current, based on which DNA sequencing can be done.

<CIT> discloses a FET comprising a control gate not overlapping the channel, and a nanopore that is formed next to the channel. DNA may move through the nanopore, which may be detected by the FET.

<NPL> describes a FET device comprising a gate stack only partially overlapping the channel region of the FET device. The FET device comprises an underlap region between the gate stack and the source region or between the gate stack and the drain region of the FET device. Experiments indicate that direct contact between biomolecules and the underlap region is possible.

In view of these applications (DNA and protein sequencing and in general biomolecule sensing) there is a need for good biosensing devices, i.e. biosensing devices with good sensitivity, which are preferably inexpensive.

It is an object of embodiments of the present invention to provide sensitive chips for biosensing.

In a first aspect, the present invention provides a method for producing a semiconductor chip for bio- sensing as set forth in claim <NUM>.

It is an advantage of embodiments of the present invention that sensitive chips for biosensing can be produced. The biosensing chips are highly sensitive, and allow to sense the presence of a small amount of biomolecules, which may be present only very locally. It is an advantage of embodiments of the present invention that a direct contact between the biomolecules and the underlap region is possible. It is thus an advantage of embodiments of the present invention that the underlap region is capable of sensing biomolecules. The presence of biomolecules changes the gate - source or gate - drain underlap, and therefore changes the drain current. Changing the gate - source or gate - drain underlap changes the external resistance in the source and/or drain by whether or not having an overlap between gate and source and/or gate and drain. It is an advantage of embodiments of the present invention that large scale manufacturing of semiconductor chips according to embodiments of the present invention is possible. It is an advantage of embodiments of the present invention that these devices can be integrated with CMOS read-out circuits.

In a method according to embodiments of the present invention, providing a doped source region and/or providing a doped drain region in or on the substrate, such that there is an underlap region between the gate stack and the source region or such that there is an underlap region between the gate stack and the drain region may include performing a tilted implantation.

It is an advantage of embodiments of the present invention that no deposition of further materials is required. The height of the gate stack and the tilt of the implant define the dimensions of the underlap region. By applying the doping in a tilted way, the drain region can be made overlapping with the gate stack.

In a method according to embodiments of the present invention, providing a doped source region and providing a doped drain region in or on the substrate such that there is an underlap region between the gate stack and the source region and/or such that there is an underlap region between the gate stack and the drain region includes, may comprise, before actually providing the doped source region, providing a spacer next to the gate stack at the side oriented towards the source region and/or a spacer next to the gate stack at the side oriented towards the drain region.

It is an advantage of embodiments of the present invention that a spacer can be used to block doping material from entering the semiconductor layer. Afterwards the spacer material can be removed such that the bio-molecules have direct access to the undoped channel. The spacer width defines the dimensions of the underlap region.

Providing a doped source region and/or providing a doped drain region in or on the substrate may comprise growing an in-situ doped semiconductor layer. By growing an in-situ doped semiconductor layer, defects may be minimized.

Alternatively, providing a doped source region and/or providing a doped drain region in or on the substrate may comprise depositing doped spin on glass, and outdiffusing the dopants into the source and/or drain region. This way, the number of defects in the source and drain areas can be limited or reduced.

A method according to embodiments of the present invention may furthermore comprise, after provision of the doped source region and of the doped drain region, removing the spacer at the side of the gate stack oriented towards the source region and/or removing the spacer at the side of the gate stack oriented towards the drain region.

A method according to embodiments of the present invention may further comprise BEOL processing of the semiconductor chip.

In a method according to embodiments of the present invention, providing a doped drain region may include covering the source side such that the source side of the substrate is not doped. It is an advantage of embodiments of the present invention that only the drain side of the substrate may be doped, such that an undoped part is obtained in the source to modulate the resistance there.

In a second aspect, the present invention provides a semiconductor chip for bio-sensing as set forth in claim <NUM>.

It is an advantage of embodiments of the present invention that the presence of biomolecules at the open side of the channel changes the effective overlapping between the gate stack and the channel. The proximity between the sensor and the biomolecule is advantageous in view of the sensitivity of the semiconductor.

In a semiconductor chip according to embodiments of the present invention, a spacer may be present between the gate stack and the drain on the substrate.

In a semiconductor chip according to embodiments of the present invention, the gate stack may be overlapping the drain.

A semiconductor chip according to embodiments of the present invention may moreover comprise a reference FET for which the gate stack is completely overlapping the channel. The reference FET can be used to compensate for drift occurring in both the reference FET and the FET with partially covered channel.

In a semiconductor chip according to embodiments of the present invention, the FET may comprise a backgate. It is an advantage of embodiments of the present invention that the sub-threshold sweep can be modified by adjusting the backgate voltage of the FET.

In a semiconductor chip according to embodiments of the present invention, the channel region may have an increased body factor. It is an advantage of embodiments of the present invention that the sub-threshold swing can be lowered by using the parasitic bipolar transistor of the FET. For that purpose the body factor of the channel region is increased. The steepness of the sub-threshold slope can be increased by using the parasitic bipolar transistor in the FET device.

In a further aspect, the present invention provides the use of a semiconductor chip according to any of the embodiments of the second aspect of the present invention, for biomolecule sensing. It is an advantage of embodiments of the present invention that sensitive measurements of biomolecules can be done. The semiconductor chip may comprise a backgate and the sub-threshold sweep may be adjusted by adjusting the voltage of the backgate. It is an advantage of embodiments of the present invention that the semiconductor chip can be biased in the sub-threshold regime; this increases the sensitivity of the semiconductor chip for the presence of bio-molecules. It is an advantage of embodiments of the present invention that the voltage range and sub-threshold slope can be changed by the back bias voltage. It is an advantage of embodiments of the present invention that the biasing scheme can be adjusted to the kind of sensing needed: for example label-free sensing of biomolecules but also possibly DNA sequencing where small differences in the order of µV and mV need to be sensed.

Particular and preferred aspects of the invention are set out in the accompanying dependent claims.

In a first aspect, the present invention relates to a method <NUM> for producing a semiconductor chip <NUM>. Such chip <NUM>, as for instance illustrated in top view in <FIG> and in cross-sectional view in <FIG>, can be used for bio-sensing applications. The method <NUM> according to embodiments of the present invention is applicable to FET devices, such as for instance FinFET devices like bulk FinFET devices or silicon on insulator (SOI) FinFET devices, or tunnel FET (TFET) devices. The different method steps in accordance with embodiments of the present invention are illustrated in <FIG>.

The method <NUM> comprises a step <NUM> wherein a substrate comprising at least one semiconductor layer is obtained. In embodiments of the present invention, the term "substrate" may include any underlying material or materials (underlying substrate) that may be used, or upon which at least one semiconductor layer may be provided. In particular embodiments, this "substrate" may include a semiconductor substrate such as e.g. a doped or undoped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The "substrate" may include, for example, an insulating layer such as a SiO<NUM> or a Si<NUM>N<NUM> layer in addition to a semiconductor substrate portion. Thus, the term substrate also includes semiconductor-on-glass (e.g. silicon-on-glass), semiconductor-on-sapphire (e.g. silicon-on sapphire) substrates. The term "substrate" is thus used to define generally the elements for layers that underlie a layer or portions of interest. Also, the "substrate" may be any other base on which a semiconductor layer is formed, for example a glass or metal layer.

In the following, aspects of the present invention will be explained referring to the manufacturing of a FinFET device; the present invention, however, not being limited thereto. In alternative embodiments of the present invention, other types of FET devices may be manufactured as biosensing devices, for instance TFET devices.

After obtaining <NUM> the substrate with the semiconductor layer, optionally, in the particular case of manufacturing a FinFET, the present invention not limited thereto, at least one fin <NUM> may be patterned <NUM> in the semiconductor layer. The at least one fin has a length dimension I and a width dimension w in the plane of the semiconductor layer, as illustrated in <FIG>. <FIG> shows a schematic drawing of a (part of a) semiconductor chip after patterning <NUM> two fins <NUM> in the semiconductor layer. <FIG> shows a vertical cross-section of the same semiconductor chip along the AA' line shown in <FIG>. It shows the semiconductor fins <NUM>, e.g. silicon fins, on top of a dielectric layer <NUM>, e.g. an oxide layer, on top of an underlying substrate <NUM>, for instance a further silicon layer. In an exemplary embodiment, the substrate, comprising the underlying substrate <NUM>, the dielectric layer <NUM> and the semiconductor layer of which the fins <NUM> are manufactured, may be of the silicon-on-insulator (SOI) type, more specifically of the ultra-thin buried oxide (UTBOX) SOI type.

The method <NUM> comprises a next step <NUM> wherein a gate stack <NUM>, comprising gate dielectric and a gate electrode, is provided on the substrate. In case at least one fin <NUM> was patterned during the optional previous method step <NUM>, the gate stack <NUM> is provided over the at least one fin <NUM>, such that the gate stack120 partially covers the fin <NUM> in its length dimension I. Providing a gate stack <NUM> on the substrate may include depositing a layer of gate dielectric material and a layer of gate electrode material over the complete substrate, and patterning the gate stack such that gate (dielectric and electrode) material is removed from places where it should not be present. <FIG> shows a schematic top view of a semiconductor chip after providing <NUM> a gate stack <NUM> over the two fins <NUM>. <FIG> shows a cross-section of the same semiconductor chip as in <FIG> along the AA' line shown in <FIG>. The gate stack <NUM> partially covers the fin <NUM> in its length dimension I, and where present, completely covers the fin <NUM> in its width direction w. In fact, the gate stack <NUM> is provided such that it covers three sides of the fin <NUM>. In the embodiment of the present invention illustrated in the drawings, the gate stack <NUM> is crossing the fins <NUM> orthogonally.

In alternative embodiments, not illustrated in the drawings, where rather than FinFET devices, other types of FET devices, such as TFET devices, are manufactured, the substrate may comprise a semiconductor layer with a dielectric layer on top, and the gate electrode may be provided on top of the dielectric layer, which forms the gate dielectric. The gate electrode and the gate dielectric together form the gate stack.

After providing <NUM> the gate stack <NUM>, doped regions are provided. A doped drain region <NUM> is provided <NUM> in and/or on the substrate and a doped source region <NUM> is provided <NUM> in and/or on the substrate. Both are provided such that an underlap region <NUM> is present between the gate stack <NUM> and the source region <NUM> and/or between the gate stack <NUM> and the drain region <NUM>. In <FIG>, the underlap region <NUM> is illustrated to be present at the side of the source region <NUM>. The underlap region <NUM> is provided such that it is suitable for sensing biomolecules. This includes that the underlap region <NUM> has dimensions suitable for sensing biomolecules.

Providing the doped regions <NUM>, <NUM> may comprise different substeps. The doped drain region <NUM>, <NUM> may be provided in and/or on the substrate, for instance in and/or on the fin <NUM>. In the embodiment illustrated in <FIG>, the doped drain region <NUM> is provided in the fin <NUM>. In an alternative embodiment as for example illustrated in <FIG>, the drain region <NUM>, <NUM> is provided partly in the fin <NUM> (part <NUM> of the drain region), and partly on top thereof (part <NUM> of the drain region), as will be explained below in more detail. In yet alternative embodiments, the drain region may formed on top of the fin. In still alternative embodiments, no fin may be present, and the drain region may be formed in, on, or partly in and partly on the substrate.

Similarly, the doped source region <NUM>, <NUM> may be provided in and/or on substrate, for instance in and/or on the fin <NUM>. In the embodiment illustrated in <FIG>, the doped source region <NUM> is provided in the fin <NUM>. In an alternative embodiment as for example illustrated in <FIG>, the source region <NUM> is provided on top of the fin <NUM>, as will be explained below in more detail. In yet alternative embodiments, the source region may be a combination of a part formed in the fin, and a part formed on top of the fin. In still alternative embodiments, no fin may be present, and the source region may be formed in, on, or partly in and partly on the substrate.

In embodiments of the present invention the doped source region and/or the doped drain region may be provided <NUM>, <NUM> using tilted implantation <NUM>. <FIG> illustrates tilted implantation <NUM> for providing <NUM> the doped source region and for providing <NUM> the doped drain region. During the tilted implantation <NUM>, the gate stack <NUM> blocks a part of the underlying substrate, for instance the fin <NUM>, from being hit by the implantation elements. This way, the doped region formed by the implantation elements, in the embodiment illustrated in <FIG> the doped source region <NUM>, is thus not contiguous with the gate stack <NUM>, there being an underlap region <NUM> between both. The angle of the tilted implantation and the height of the gate stack <NUM> define the underlap region <NUM> between the gate stack <NUM> and the source region <NUM>.

In alternative embodiments of the present invention, as illustrated in <FIG>, providing a doped drain region <NUM> includes covering <NUM> the source side such that the source side in the substrate/fin is not doped with the drain region <NUM>. <FIG> show a method step <NUM> whereby the source side is covered before providing <NUM> a doped drain region <NUM> in the fin <NUM>. This prevents doping the source side <NUM> in the fin <NUM> when providing a doped drain region <NUM>. The cover <NUM> is shown in <FIG> and in <FIG>. The cover can be made of any suitable material which prevents dopant elements to travel there through and into a layer underneath, such as for instance amorphous carbon, nitride, oxide or a combination of nitride and oxide. The cover material can be selectively deposited onto the regions to be protected from dopants, or can be deposited as a blanket layer over substantially the whole substrate, and can be selectively removed thereafter, so as to only remain on one or more areas to be protected from dopant implantations. After the dopant implantation in the drain region <NUM>, the cover <NUM> may be completely removed again.

In embodiments of the present invention, in the embodiment illustrated where an underlap <NUM> will be provided between source region <NUM> and gate stack <NUM>, at least a spacer <NUM> is provided <NUM> next to the gate stack <NUM> at the side oriented towards the source region <NUM>. Furthermore, a further spacer <NUM> may be provided <NUM>, but does not need to be provided, next to the gate stack oriented towards the drain region <NUM>. The spacers <NUM>, if present, are provided before actually providing <NUM> the doped source region, e.g. before the actual implantation step. <FIG> illustrates an intermediate semiconductor chip after providing <NUM> the spacers <NUM>, <NUM> next to the gate stack <NUM>. In this example the spacers are provided after having provided <NUM> the doped drain region <NUM>. When actually providing the doped source region, for instance by dopant implantation, the spacer <NUM> located at the side where the source region <NUM> has to come, protects the underlying substrate, e.g. fin <NUM>, from source dopants. When thereafter removing the spacer <NUM>, a gap is left between the gate stack <NUM> and the source region <NUM>, resulting in an underlap region <NUM>. The width of the underlap region <NUM> is equal to the width of the spacer <NUM> which has been removed from next to the gate stack at the side oriented towards the source <NUM>.

In embodiments of the present invention, spacers <NUM>, <NUM> may be provided before providing <NUM> the doped source region <NUM> and before providing <NUM> the doped drain region <NUM>. This way, an underlap region may be created, both between the gate stack <NUM> and the source region <NUM>, and between the gate stack <NUM> and the drain region <NUM>. After providing the doped source region <NUM> and the doped drain region <NUM>, for instance by means of one or more dopant implantation steps, the spacer <NUM> next to the gate stack <NUM> at the side oriented towards the source and/or the spacer <NUM> next to the gate stack <NUM> oriented towards the drain region <NUM> might be removed. Removing the spacer between the gate stack <NUM> and the source region <NUM> results in an underlap region <NUM> between the gate stack <NUM> and the source region <NUM>. The width of the underlap region <NUM> is equal to the width of the spacer <NUM> next to the gate stack at the side oriented towards the source <NUM>. In embodiments of the present invention the width of the underlap region <NUM> is larger than <NUM>, for instance between <NUM> and <NUM>, e.g. between <NUM> and <NUM>. An exemplary embodiment of the present invention which is produced by providing <NUM> at least one spacer next to the gate stack <NUM>, and removing it at the side of the source region, is illustrated in <FIG>, and will be discussed in more detail below.

In a method <NUM> according to embodiments of the present invention, providing <NUM> the doped source region <NUM> and or providing <NUM> the doped drain region <NUM> may comprise a step <NUM> wherein, rather than performing an implantation step or besides an implantation step, an in-situ doped semiconductor layer is grown. In embodiments of the present invention, this way, a doped drain region or part thereof and/or a doped source region or part thereof are provided on or in the substrate, for instance on or in the fin <NUM>, next to the spacer. An exemplary embodiment of the present invention is illustrated in <FIG>. These figures show a semiconductor chip as in <FIG>, but which has a source pad <NUM> and a drain pad <NUM> on top of the fins <NUM>. The source pad <NUM> is located on top of the fins <NUM> and next to the spacer <NUM> at the source side. The drain pad <NUM> is located on top of the fins <NUM> and next to the spacer <NUM>. As can be seen, in the embodiment illustrated in <FIG>, the drain is formed by a combination of drain region <NUM> and drain pad <NUM>. The source is formed solely by the source pad. In alternative embodiments, also the source could be formed by a combination of a previously implanted doped region and a deposited doped region, and/or the drain could be formed solely by a deposited doped region.

In embodiments of the present invention, providing <NUM> the doped source region and/or providing the doped drain region may comprise, instead of dopant implantation or growing of doped semiconductor layers, applying spin-on-glass, and outdiffusing <NUM> dopants into the source and/or drain regions.

In embodiments of the present invention, after having provided the doped source and drain regions, back end of line (BEOL) processing is applied to the semiconductor chip. An example thereof is illustrated in <FIG> and <FIG> wherein a conductive contact <NUM>, for instance a metal contact such as e.g. an aluminum contact, is deposited on top of the source, for instance on top of the source pad <NUM>, and wherein a conductive contact <NUM>, for instance a metal contact such as e.g. an aluminum contact, is deposited on top of the drain, for instance on top of the drain pad <NUM>. After depositing the conductive contacts <NUM>, <NUM>, an insulating layer <NUM> is deposited on top of the semiconductor chip <NUM>.

In embodiments of the present invention, the insulating layer <NUM> is opened above the channel, i.e. that part of the semiconductor layer of the substrate provided between the source and the drain, for instance a portion of the fin <NUM>, at the source side of the semiconductor chip <NUM>, for example above the spacer <NUM> located next to the gate stack <NUM> at the source side of the semiconductor chip <NUM>. An example thereof is illustrated in <FIG> and <FIG>. The opening in the insulating layer <NUM> permits contact with the spacer <NUM> (or in case no spacer would be present, directly with the channel <NUM>).

In case the opening in the insulating layer <NUM> provides access to a spacer <NUM>, <NUM>, this spacer <NUM>, <NUM> may be removed <NUM>. This way, a portion of the channel <NUM> is revealed and uncovered. This uncovered portion provides the underlap <NUM> between source and gate stack and/or between drain and gate stack. This allows biomolecules to be in direct contact with the channel <NUM> portion between the gate stack <NUM> and the source and/or between the gate stack <NUM> and the drain, when the sensing device is in use. An example thereof is illustrated in <FIG> and <FIG>. By removing <NUM> the spacer, for instance the spacer <NUM> at the source side, the substrate, e.g. the fins <NUM>, become visible in the gap, e.g. at the bottom of the gap, in the insulating layer <NUM>. In embodiments of the present invention the spacer <NUM> may be removed by using any suitable product, for instance an etchant for removing the spacer, such as e.g. phosphoric acid. In the example of <FIG> and <FIG> the fins <NUM> at the source side are not doped. As illustrated in <FIG> the biomolecules have direct access to the channel <NUM>.

The direct access of biomolecules to the channel <NUM> is only illustrated in the drawings in <FIG> for the embodiment where the underlap is provided by means of a spacer <NUM>; however, the present invention is not limited thereto. Also in the embodiment of <FIG>, an underlap region <NUM> is created, this time by means of tilted implantation of dopant elements, and at this underlap region <NUM> there is a direct access of biomolecules to the channel <NUM>.

In a second aspect, the present invention relates to a semiconductor chip <NUM> for bio-sensing. The semiconductor chip <NUM> comprises at least one FET device. This may for example be a FinFET device or a TFET device. The FET device comprises a source, a drain, a gate stack <NUM> and a channel region <NUM> between the source and the drain. The gate stack <NUM> is only partially overlapping the channel region <NUM> at the source side and/or at the drain side, such that there is an underlap region <NUM> between the source and the gate stack and/or between the drain and the gate stack.

In the particular case of a FinFET device, the FET device comprises a semiconductor fin <NUM> and a gate stack <NUM> whereby the gate stack <NUM> partially overlaps the semiconductor fin <NUM>. In embodiments of the present invention a channel <NUM> is implemented in the fin <NUM>, and a drain <NUM>, <NUM> and a source <NUM>, <NUM> are implemented in and/or on the fin <NUM>. The gate stack <NUM> is only partially overlapping the channel <NUM> at the source side and/or at the drain side. The non-overlapped channel region <NUM> at the source side and/or drain side is suitable for sensing biomolecules. <FIG> is a schematic illustration of the top view of a an exemplary embodiment of the present invention. <FIG> shows the cross-section AA' of the same exemplary embodiment. The figures show a semiconductor chip <NUM> for biosensing. The semiconductor chip comprises a FinFET. The FinFET comprises two silicon fins <NUM> and a gate stack <NUM> partially overlapping the semiconductor fin <NUM>. In this exemplary embodiment, each fin <NUM> comprises a source <NUM>, a channel <NUM>, and a drain <NUM>. The gate stack <NUM> is only partially overlapping the channel <NUM>, such that part of the channel <NUM> at the source side is not overlapped by the gate stack. The region <NUM> of the channel which is not overlapped by the gate stack is suitable for sensing biomolecules. In this exemplary embodiment the fins <NUM> may be made of silicon and they may be located on an oxide layer <NUM>, the oxide layer being on top of a silicon substrate <NUM>.

In embodiments of the present invention a spacer <NUM> may be present between the gate stack <NUM> and the drain <NUM> on the fin <NUM>. An example thereof is illustrated in <FIG> also illustrates an embodiment of the present invention whereby the gate stack <NUM> is overlapping the drain <NUM>. In alternative embodiments of the present invention, not illustrated in the drawings, a spacer may be present between the gate stack and the source, and the uncovered part of the channel may be present at the drain side.

Embodiments of the present invention may comprise a reference FET device, for instance a reference FinFET. The channel of the reference FET device, for example the reference FinFET, may be completely overlapped by the gate stack. The reference FET device, e.g. the reference FinFET, has no opening through which the biomolecules have direct access to the channel <NUM>. The reference FET device, e.g. the reference FinFET, allows to increase the sensitivity of the semiconductor chip even more by comparing the FET measurements, e.g. FinFET measurements, with the reference FET measurements, e.g. reference FinFET measurements.

In embodiments of the present invention the FET device may comprise a backgate.

In embodiments of the present invention the fin <NUM> of a FinFET device may have an increased body factor. This can for example be obtained by using triangular shaped fins instead of rectangular shaped fins.

In a third aspect the present invention relates to the use of a semiconductor chip <NUM> for biomolecule sensing.

Semiconductor chips according to the present invention have a gate stack <NUM> which is not completely overlapping the channel <NUM>. The free part <NUM> of the channel may for instance be located at the source side and is suitable for sensing biomolecules. The free part of the channel is preferably located at the source side because there it has the highest impact. The impact of the underlap at the source side, and thus the impact of the source resistance Rs, is the largest for short gate lengths; for longer channel devices the channel resistance is dominant. Changing the amount of biomolecules at the uncovered part (underlap region) of the channel has the same effect as changing the gate source overlap. Changing the amount of biomolecules at the uncovered part of the channel changes the parasitic series resistance at the source side and therefore changes the drain current.

In embodiments of the present invention the semiconductor chip <NUM> may be controlled by applying a voltage at the backgate of the semiconductor chip <NUM> for biasing the semiconductor chip in the sub-threshold region. By adjusting the backgate voltage, the sub-threshold sweep can be modified to increase the sensitivity of the bio-sensing measurements. Lowering the sub-threshold swing by frontgate/backgate coupling can only be done if the channel <NUM> is undoped. The subthreshold swing is defined as <NUM>/subthreshold slope; so the lower the subthreshold swing, the steeper the characteristic and as such a small variation in voltage can change the current over a large range.

In embodiments of the present invention the steepness of the sub-threshold swing is decreased by using the parasitic bipolar transistor in the FET device, for instance a FinFET device. For that purpose the FET devices, for instance FinFET devices, may be made on a UTBOX substrate. By doing so, the back substrate can be used as a second gate (back gate). By decreasing the thickness of the BOX the capacitance of this backgate is higher and as such lower bias conditions can be used e.g. <NUM>-2V instead of <NUM>-30V in the case of a thick BOX. In embodiments of the present invention the body factor of the fin <NUM> is increased.

Scaled semiconductor devices have the disadvantage that they are sensitive to random telegraphy noise (RTN). This leads to noisy current measurements and to problems in distinguishing the current variations induced by the biomolecules. The RTN can be reduced by reducing the number of defects as these are capturing and releasing the charges. Therefore the RTN can be reduced by removing implants (e.g. an undoped channel, gentle doping of the source and drain areas). The RTN can also be reduced by reducing the number of defects in the gate dielectric (interface states). This can be done by using SiO<NUM> dielectrics. In embodiments of the present invention the RTN is minimized by minimizing the number of impurity atoms in the source and the drain by using solid state doping to make the source <NUM> and/or drain <NUM>. This can be done by applying a doped SOG (spin-on-glass) layer and afterwards applying outdiffusion of the doped SOG layer into the fin at the source and/or drain regions. The SOG might for example be doped with dopant elements such as B, P, or As. It is an advantage of embodiments of the present invention that the RTN can be lowered, for instance by a factor <NUM> to <NUM>, by minimizing the number of impurity atoms. By lowering the variations in the current caused by RTN, the semiconductor chip <NUM> becomes more sensitive for variations in the current caused by changing the number of biomolecules at the open side of the channel <NUM>.

Claim 1:
A method (<NUM>) for producing a semiconductor chip (<NUM>) for bio-sensing, the method comprising:
- obtaining (<NUM>) a substrate comprising at least one semiconductor layer,
- providing (<NUM>) a gate stack (<NUM>) on the substrate,
- providing (<NUM>) a doped drain region (<NUM>) in and/or on the substrate, and
- providing (<NUM>) a doped source region (<NUM>) in and/or on the substrate, wherein the gate stack, the doped drain region and the doped source region are provided such that the gate stack (<NUM>) is only partially overlapping a channel region between the source and the drain and that there is an underlap region (<NUM>) between the gate stack (<NUM>) and the source region (<NUM>) and/or between the gate stack (<NUM>) and the drain region (<NUM>), such that a direct contact between biomolecules and the underlap region (<NUM>) is possible,
characterized in that the doped drain region (<NUM>) and the doped source region (<NUM>) are provided after providing the gate stack (<NUM>).