Patent Description:
Electricity generated by solar cells is a sustainable clean energy source. Structure of solar cells is known, for example, from "<NPL>), which discloses a structure of a POLO-IBC solar cell. By virtue of a photovoltaic effect of a semiconductor p-n junction, sunlight can be converted into electric energy. Conversion efficiency is an important indicator of the performance of solar cells. In an interdigitated back contact (IBC) cell, a positive/negative electrode is designed on a back side of the cell, so that a front surface is not at all shielded by a metal gate line, thereby completely eradicating an optical loss caused by the shielding of the metal gate line. In addition, a width of the electrode may be designed wider than a conventional electrode, so that a series resistance loss is reduced, thereby significantly improving the conversion efficiency. In addition, since the front side is designed with no electrodes, a product has a more beautiful appearance, and is applicable to a plurality of application scenarios.

In a conventional passivated IBC cell with doped polysilicon, the doped polysilicon is isolated from a silicon substrate by using a tunneling layer, forming a passivated contact structure in a stacked form of doped polysilicon-tunneling layer (an insulation layer)-silicon substrate. A thickness of the tunneling layer has a very large impact on a tunneling resistance. In order to form a desirable resistivity, the thickness of the tunneling layer is required to be small enough. However, in order to realize a desirable passivation effect, the thickness of the tunneling layer is required to be large enough. Therefore, the thickness range of the tunneling layer is required to be strictly controlled. During production, the accuracy of the thickness of the tunneling layer is difficult to control. Therefore, at present, scale production is unavailable. In addition, requirements are also imposed for a thermal process in a follow-up production process. Therefore, the conversion efficiency of the cell is limited.

The invention provides the solar cell set out in claim <NUM>. The dependent claims define further particulars of the invention. The solar cell according to claim <NUM> is provided with a doped region structure of a solar cell, to resolve the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for a thickness of a conventional tunneling layer.

A doped region structure of a solar cell includes
a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence.

The passivation layer is a porous structure comprising a hole region, and the first doped layer and/or the second doped layer are disposed in the hole region.

Further, the first doped layer and the second doped layer have a same doping polarity.

Further, a pore size of the porous structure is less than <NUM>.

Further, the pore size of the porous structure is less than <NUM>.

Further, the pore size of the porous structure is less than <NUM>. A hole is designed as a nano-level hole having a pore size less than <NUM>, and a surface hole density may be designed up to <NUM><NUM>-<NUM><NUM>/cm<NUM>. It may be understood that the arrangement of nano-level hole having the pore size less than <NUM> greatly reduces the overall contact area between the second doped layer and the silicon substrate, thereby not only reducing the resistance, but also greatly reducing the recombination.

Further, a non-hole region of the porous structure includes a dopant having a same doping type as the first doped layer and/or the second doped layer.

Further, a part of the hole region of the porous structure includes the first doped layer and/or the second doped layer.

Further, a ratio of an area of the hole region of the porous structure to an entire area of the porous structure is less than <NUM>%.

Further, a thickness of the passivation layer is in a range of <NUM>-<NUM>.

Further, the thickness of the passivation layer is in a range of <NUM>-<NUM>.

Further, the passivation layer is an oxide layer, a silicon carbide layer, an amorphous silicon layer, or a combination thereof.

Further, the oxide layer comprises a silicon oxide layer, an aluminum oxide layer, or a combination thereof.

Further, the silicon carbide layer in the passivation layer includes a hydrogenated silicon carbide layer.

Further, a doping concentration of the first doped layer is between a doping concentration of the silicon substrate and a doping concentration of the second doped layer.

Further, a junction depth of the first doped layer is less than <NUM>.

Further, the first doped layer is a monocrystalline silicon doped layer doped with a group-III or group-V element.

Further, the second doped layer includes a polysilicon doped layer, a silicon carbide doped layer, or an amorphous silicon doped layer.

Further, the silicon carbide doped layer in the second doped layer comprises at least one silicon carbide doped film.

Further, the refractive indexes of the silicon carbide doped films decrease from the silicon substrate toward outside.

Further, the silicon carbide doped layer in the second doped layer includes a hydrogenated silicon carbide doped layer, a conductivity of the hydrogenated silicon carbide doped layer is greater than <NUM>·cm, and a thickness of the hydrogenated silicon carbide doped layer is greater than <NUM>.

The invention is intended to provide a solar cell. The solar cell is recited in claim <NUM> and includes:.

The first doped region and the second doped region use the doped region structure described above.

Further, in a comparative example, not forming part of the invention, one of the first doped region and the second doped region uses the doped region structure described above, and the other of the first doped region and the second doped region is a third doped layer disposed on the back side of the silicon substrate.

Further, the third doped layer is a monocrystalline silicon doped layer doped with a group-III or group-V element.

Further, grooves spaced apart are provided on the back side of the silicon substrate, and the first doped region and the second doped region are alternately disposed in the grooves.

Further, grooves spaced apart are provided on the back side of the silicon substrate, one of the first doped region and the second doped region is disposed in one of the grooves, and the other of the first doped region and the second doped region is disposed outside the groove.

Further, a trench is provided between the first doped region and the second doped region.

Further, the first doped region and/or the second doped region are/is disposed in a part of regions inside and outside the groove.

Further, the first dielectric layer and the second dielectric layer each are an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer, or a combination thereof.

Further, the first dielectric layer and/or the second dielectric layer include(s) the aluminum oxide layer and the silicon carbide layer, or the silicon oxide layer and silicon carbide layer; and
a thickness of the first dielectric layer is greater than <NUM>, and a thickness of the second dielectric layer is greater than <NUM>.

Further, a thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer is less than <NUM>, a thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than <NUM>, and a thickness of the silicon carbide layer in the first dielectric layer and/or in the second dielectric layer is greater than <NUM>.

Further, the silicon carbide layer in the first dielectric layer and/or in the second dielectric layer comprises at least one silicon carbide film.

Further, the refractive indexes of the silicon carbide films decrease from the silicon substrate toward outside.

Further, a magnesium fluoride layer is further disposed outside the first dielectric layer and/or the second dielectric layer.

Further, the first conductive layer and the second conductive layer are TCO transparent conductive films and/or metal electrodes.

Further, the metal electrodes each include a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, or a silver-coated copper electrode.

Further, the copper electrode is electroplated copper prepared by using an electroplating process or the copper electrode prepared by means of physical vapor deposition.

Further, an electric field layer or a floating junction is disposed between the front side of the silicon substrate and the first dielectric layer.

Further, one of the first doped region and the second doped region is a P-type doped region, the other of the first doped region and the second doped region is an N-type doped region, and a thickness of a passivation layer in the P-type doped region is greater than a thickness of a passivation layer in the N-type doped region.

In accordance with the present invention, one of the first doped region and the second doped region is a P-type doped region, the other of the first doped region and the second doped region is an N-type doped region, and a hole density of a passivation layer in the P-type doped region is greater than a hole density of a passivation layer in the N-type doped region.

A comparative example, not forming part of the invention, is intended to provide a solar cell. The solar cell according to the comparative example includes:.

In the solar cell according to the comparative example, the doped region structure and the fourth doped layer have opposite polarities.

The invention also provides a cell assembly. The cell assembly includes one of the solar cells recited in the appended claims.

The invention also provides a photovoltaic system. The photovoltaic system includes the cell assembly describe above.

According to the doped region structure of the solar cell provided in the embodiments of the disclosure, the first doped layer, the passivation layer, and the second doped layer are disposed in sequence, the passivation layer is arranged as a porous structure, and the hole region has the first doped layer and/or the second doped layer. Therefore, a conductive channel is formed in the hole region of the passivation layer, so that a desirable resistivity of the passivation layer is formed. In this way, a thickness of the passivation layer has a less impact on the resistance, and the control requirements for the thickness of the passivation layer are lowered. Thus, more methods are applicable to preparation of the passivation layer compared with the prior art. In an embodiment, the hole is designed as a nano-level hole having a pore size less than <NUM>, so that the surface hole density is as high as <NUM><NUM>-<NUM><NUM>/cm<NUM>. It may be understood that the arrangement of nano-level hole having the pore size less than <NUM> greatly reduces the overall contact area between the second doped layer and the silicon substrate, thereby not only reducing the resistance, but also greatly reducing the recombination. The first doped layer is disposed between the silicon substrate and the passivation layer to form a separation electric field capable of enhancing surface electron holes, so that the field passivation effect is enhanced. Since a Fermi level of the first doped layer is different from a Fermi level of the silicon substrate, the Fermi level of the first doped layer is changed. A solid concentration of impurities (transition metals) is increased, so that an additional impurity gettering effect is achieved. In addition, in the porous structure, the second doped layer is connected to the silicon substrate through the doped hole region and the first doped layer, so that the overall resistance of the prepared cell is further reduced, and the conversion efficiency of the cell is improved. In this way, the difficulty in production and the limitation on the conversion efficiency as a result of precise requirements for the thickness of the conventional tunneling layer are resolved.

To make the objectives, technical solutions and advantages of the disclosure clearer and more comprehensible, the disclosure is further described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely used to explain the disclosure, but are not intended to limit the disclosure.

In the disclosure, unless otherwise explicitly specified or defined, the terms such as "mount", "install", "connect", "connection", and "fix" should be understood in a broad sense. For example, the connection may be a fixed connection, a detachable connection, or an integral connection; or the connection may be a mechanical connection or an electrical connection; or the connection may be a direct connection, an indirect connection through an intermediary, or internal communication between two components. A person of ordinary skill in the art may understand specific meanings of the foregoing terms in the disclosure according to specific situations. The term "and/or" used in this specification includes any and all combinations of one or more related listed items.

In the disclosure, a first doped layer, a passivation layer, and a second doped layer are disposed in sequence, the passivation layer is arranged as a porous structure, and a hole region has the first doped layer and/or the second doped layer. Therefore, a conductive channel is formed in the hole region of the passivation layer, so that a desirable resistivity of the passivation layer is formed. In this way, a thickness of the passivation layer has a less impact on the resistance, and the control requirements for the thickness of the passivation layer are lowered. Thus, more methods are applicable to preparation of the passivation layer compared with the prior art. The first doped layer is disposed between the silicon substrate and the passivation layer to form a separation electric field capable of enhancing surface electron holes, so that the field passivation effect is enhanced. Since a Fermi level of the first doped layer is different from a Fermi level of the silicon substrate, the Fermi level of the first doped layer is changed. A solid concentration of impurities (transition metals) is increased, so that an additional impurity gettering effect is achieved. In addition, in the porous structure, the second doped layer is connected to the silicon substrate through the doped hole region and the first doped layer, so that the overall resistance of the prepared cell is further reduced, and the conversion efficiency of the cell is improved. In this way, the difficulty in production and the limitation on the conversion efficiency as a result of precise requirements for the thickness of the conventional tunneling layer are resolved.

An embodiment of the disclosure provides a doped region structure of a solar cell. For ease of description, only parts related to this embodiment of the disclosure are shown. Referring to <FIG>, the doped region structure of the solar cell provided in this embodiment of the disclosure includes:
a first doped layer <NUM>, a passivation layer <NUM>, and a second doped layer <NUM> that are disposed on a silicon substrate <NUM> in sequence.

The passivation layer <NUM> is a porous structure having the first doped layer <NUM> and/or the second doped layer <NUM> in a hole region.

In an embodiment of the disclosure, the silicon substrate <NUM> has a front side facing the sun during normal operation and a back side opposite to the front side. The front side is a light-receiving surface. The back side is opposite to the front side and disposed on an other side of the silicon substrate <NUM>. That is to say, the front side and the back side are located on different and opposite sides of the silicon substrate <NUM>. In this embodiment, the silicon substrate <NUM> is an N-type monocrystalline silicon wafer. It may be understood that, in other embodiments, the silicon substrate <NUM> may also be silicon wafers of other types, such as a polysilicon wafer, a quasi-monocrystalline silicon wafer, or the like. The silicon substrate <NUM> may also be designed as a P type. The silicon substrate <NUM> may be designed according to actual use requirements, which is not specifically limited herein.

In an embodiment of the disclosure, the passivation layer <NUM> is preferably an oxide layer, a silicon carbide layer, an amorphous silicon layer, or a combination thereof. In some examples of the disclosure, the passivation layer <NUM> may include a single material such as an oxide layer, a plurality of types of materials such as a combination of an oxide layer and an amorphous silicon layer, or a single material such as a combination of a plurality of amorphous silicon layers each having a specific refractive index. In addition, the first passivation layer <NUM> may also be a silicon oxynitride layer, a silicon nitride layer, or the like. It may be understood that, the specific structure of the passivation layer <NUM> includes but is not limited to the above. The passivation layer <NUM> may be correspondingly designed according to actual use requirements, which is not specifically limited herein. Further, a thickness of the passivation layer <NUM> is in a range of <NUM>-<NUM>. In a preferable embodiment of the disclosure, the thickness of the passivation layer <NUM> is in a range of <NUM>-<NUM>. The thickness of the passivation layer <NUM> may be designed as a thickness of a tunneling layer in the prior art or a thickness larger than the thickness of the conventional tunneling layer. The thickness may be designed according to actual use requirements, which is not specifically limited herein.

In a preferable embodiment of the disclosure, specifically, the passivation layer <NUM> includes the oxide layer and the silicon carbide layer. The oxide layer and the silicon carbide layer are arranged in sequence from the silicon substrate <NUM> toward outside. The oxide layer is in contact with the first doped layer <NUM> located inside, and the silicon carbide layer is in contact with the second doped layer <NUM> located outside. Further, the oxide layer preferably comprises a silicon oxide layer, an aluminum oxide layer, or a combination thereof. Therefore, the passivation layer <NUM> may also be a combination of the silicon oxide layer and the aluminum oxide layer in the oxide layer. The silicon carbide layer in the passivation layer <NUM> includes a hydrogenated silicon carbide layer. Hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate <NUM> under a diffusion mechanism and a thermal effect, so that a dangling bond for neutralizing the back side of the silicon substrate <NUM> passivates defects of the silicon substrate <NUM>. Therefore, mitigating dangling bonds in a forbidden band increases the probability that a carrier enters the second doped layer <NUM> through the passivation layer <NUM>.

Further, in an embodiment of the disclosure, the passivation layer <NUM> is a porous structure. The porous structure may be prepared by means of additional chemical corrosion, dry etching, or thermal diffusion impact, or the like. The porous structure is performed according to actual use requirements, which is not specifically limited herein. It should be noted that, the porous structure is in a top view of the passivation layer <NUM>. In a cross-sectional view of the passivation layer <NUM>, a multichannel structure is shown. The porous structure has holes extending through the passivation layer <NUM>. The porous structure also has grooves/openings not extending through the passivation layer <NUM> on a surface of the passivation layer <NUM>. A pore size of the porous structure is less than <NUM>. Specifically, an average pore size of the holes is less than <NUM>, or pore sizes of <NUM>% of all of the holes are less than <NUM>. Further, the pore size of the porous structure is less than <NUM>. Further, the pore size of the porous structure is less than <NUM>. In this case, a hole is designed as a nanolevel hole having a pore size less than <NUM>, and a surface hole density may be designed up to <NUM><NUM>-<NUM><NUM>/cm<NUM>. It may be understood that the arrangement of nano-level hole having the pore size less than <NUM> greatly reduces the overall contact area between the second doped layer and the silicon substrate, thereby not only reducing the resistance, but also greatly reducing the recombination. A ratio of an area of the hole region of the porous structure to an entire area of the porous structure is less than <NUM>%, that is, the holes are sparsely distributed on the passivation layer <NUM>.

In an embodiment of the disclosure, the hole region of the porous structure includes the first doped layer <NUM> and/or the second doped layer <NUM>. That is to say, the hole region may be inlaid with the first doped layer <NUM> or the second doped layer <NUM> alone, or may be inlaid with a mixture of the first doped layer <NUM> and the second doped layer <NUM>. It needs to be noted that, in an actual production and preparation process, a part of the hole region of the porous structure may include the first doped layer <NUM> and/or the second doped layer <NUM>, and other parts that are not filled with the first doped layer <NUM> and/or the second doped layer <NUM> are gap regions. It needs to be further noted that, in addition to the first doped layer <NUM> and/or the second doped layer <NUM> filled in the hole region, impurities (such as hydrogen, oxygen, and various metal elements) formed in a thermal process (the production of solar cells may include a plurality of high temperature processes according to different processes) or generated during segregation are allowed to exist in the hole region.

Further, in an embodiment of the disclosure, a non-hole region of the porous structure includes a dopant having a same doping type as the first doped layer <NUM> and/or the second doped layer <NUM>. For example, when the first doped layer <NUM> and the second doped layer <NUM> are N-type doped layers (such as a phosphorus doped layer), the non-hole region of the passivation layer <NUM> includes a diffused N-type dopant.

In an embodiment of the disclosure, the first doped layer <NUM> is located between the silicon substrate <NUM> and the passivation layer <NUM>. The first doped layer <NUM> may be a doped layer directly formed on the silicon substrate <NUM> by means of ion implantation or the like. In this case, the first doped layer <NUM> is located on the silicon substrate <NUM>. Correspondingly, the passivation layer <NUM> is prepared on the first doped layer <NUM>. The first doped layer <NUM> may also be a doped layer formed on the silicon substrate <NUM> after a doping source directly penetrates the passivation layer <NUM> or the holes in the porous structure during preparation of the second doped layer <NUM>. In this case, the first doped layer <NUM> is located in the silicon substrate <NUM>. Correspondingly, the passivation layer <NUM> is directly prepared on the silicon substrate <NUM>. Therefore, during the preparation of the second doped layer <NUM>, the passivation layer is thermally diffused into the silicon substrate <NUM>, so that a part of the silicon substrate <NUM> is transformed into the first doped layer <NUM> through diffusion. A doping concentration of the first doped layer <NUM> is between a doping concentration of the silicon substrate <NUM> and a doping concentration of the second doped layer <NUM>. In a preferred embodiment of the disclosure, the first doped layer <NUM> and the second doped layer <NUM> have a same doping polarity. For example, when the second doped layer <NUM> is an N-type doped layer, the first doped layer <NUM> is correspondingly preferably an N-type doped layer. It needs to be noted that, the doping polarities of the first doped layer <NUM> and the second doped layer <NUM> may be different from a doping polarity of the silicon substrate <NUM>. For example, in this embodiment, the silicon substrate <NUM> is an N-type monocrystalline silicon, and the first doped layer <NUM> and the second doped layer <NUM> may be P-type doped layers.

Preferably, a material of the first doped layer <NUM> is preferably designed as same as the silicon substrate <NUM>. That is to say, when the silicon substrate <NUM> is a monocrystalline silicon wafer, the first doped layer <NUM> is also preferably designed as the monocrystalline silicon wafer. The first doped layer <NUM> is a monocrystalline silicon doped layer doped with a group-III or group-V element. When the second doped layer <NUM> is the N-type doped layer, the first doped layer <NUM> is a monocrystalline silicon doped layer doped with group-V elements such as nitrogen, phosphorus, and arsenic. When the second doped layer <NUM> is the P-type doped layer, the first doped layer <NUM> is a monocrystalline silicon doped layer doped with group-III elements such as boron, aluminum, and gallium. It may be understood that, when the silicon substrate <NUM> is designed as silicon wafers of other types, the first doped layer <NUM> may also be correspondingly designed as doped silicon wafers of other types doped with a group-III or group-V element.

Further, in an embodiment of the disclosure, the first doped layer <NUM> is in a discrete or continuous distribution. The first doped layer may be completely continuously disposed between the silicon substrate <NUM> and the passivation layer <NUM>, or locally discretely distributed near each hole region of the passivation layer <NUM>. The distribution of the first doped layer <NUM> may be controlled by using a doping process. A doping amount increases over a doping time, so that the first doped layer <NUM> is more continuous, until the first doped layer <NUM> fully covering the silicon substrate <NUM> is formed thereon. Further, a junction depth of the first doped layer <NUM> is less than <NUM>.

In an embodiment of the disclosure, the second doped layer <NUM> includes a polysilicon doped layer, a silicon carbide doped layer, or an amorphous silicon doped layer. The silicon carbide doped layer in the second doped layer <NUM> comprises at least one silicon carbide doped film each having a specific refractive index. The refractive indexes of the silicon carbide doped films decrease from the silicon substrate <NUM> toward the outside. It needs to be noted that, thicknesses and the refractive indexes of the silicon carbide doped films may be designed according to actual use requirements, provided that the refractive indexes decrease from the silicon substrate <NUM> toward the outside, which are not specifically limited herein. Since silicon carbide has a wide optical band gap and a low absorption coefficient, parasitic absorption can be reduced, and a short-circuit current density can be effectively increased. Further, the silicon carbide doped layer in the second doped layer <NUM> includes a hydrogenated silicon carbide doped layer. A conductivity of the hydrogenated silicon carbide doped layer is greater than <NUM>·cm, and a thickness of the hydrogenated silicon carbide doped layer is greater than <NUM>. Correspondingly, the conductivity and the thickness may also be set to other values, provided that a requirement for the of the second doped layer <NUM> can be met by controlling the conductivity and the thickness of the hydrogenated silicon carbide doped layer, which are not specifically limited herein. It needs to be noted that, the first doped layer <NUM> and the second doped layer <NUM> may have a same material or different materials. For example, the first doped layer <NUM> and the second doped layer <NUM> both include doped polysilicon. Alternatively, the first doped layer <NUM> may include doped monocrystalline silicon, and the second doped layer <NUM> may include doped silicon carbide.

Different from the passivated contact structure in the prior art, in this embodiment, the first doped layer, the passivation layer, and the second doped layer are disposed in sequence, the passivation layer is arranged as a porous structure, and the hole region has the first doped layer and/or the second doped layer. Therefore, a conductive channel is formed in the hole region of the passivation layer, so that a desirable resistivity of the passivation layer is formed. In this way, a thickness of the passivation layer has a less impact on the resistance, and the control requirements for the thickness of the passivation layer are lowered. Thus, more methods are applicable to preparation of the passivation layer compared with the prior art. The first doped layer is disposed between the silicon substrate and the passivation layer to form a separation electric field capable of enhancing surface electron holes, so that the field passivation effect is enhanced. Since a Fermi level of the first doped layer is different from a Fermi level of the silicon substrate, the Fermi level of the first doped layer is changed. A solid concentration of impurities (transition metals) is increased, so that an additional impurity absorption effect is achieved. In addition, in the porous structure, the second doped layer is connected to the silicon substrate through the doped hole region and the first doped layer, so that the overall resistance of the prepared cell is further reduced, and the conversion efficiency of the cell is improved. In this way, the difficulty in production and the limitation on the conversion efficiency as a result of precise requirements for the thickness of the conventional tunneling layer are resolved.

A second embodiment of the disclosure provides a solar cell. For ease of description, only parts related to this embodiment of the disclosure are shown. Referring to <FIG>, the solar cell provided in this embodiment of the disclosure includes:.

The first doped region <NUM> and/or the second doped region <NUM> use(s) the doped region structure described in the above embodiments.

Thus, in an embodiment of the disclosure, the first doped region <NUM> and the second doped region <NUM> in the solar cell both may use the doped region structure described in the above embodiments. Referring to <FIG>, <FIG>, and <FIG>, since the first doped region <NUM> and the second doped region <NUM> have opposite polarities, a first doped layer and a second doped layer in the first doped region <NUM> and a first doped layer and a second doped layer in the second doped region <NUM> also have opposite polarities. For example, when the first doped layer and the second doped layer in the first doped region <NUM> are P-type doped layers, the first doped layer and the second doped layer in the second doped region <NUM> are N-type doped layers having opposite doping polarities. In this case, the first doped region <NUM> is a P-type doped region, and the second doped region <NUM> is an N-type doped region. Definitely, the first doped region <NUM> may also be the N-type doped region, and the second doped region <NUM> may also be the P-type doped region. Therefore, when one of the first doped region <NUM> and the second doped region <NUM> is the P-type doped region, the other of the first doped region and the second doped region is the N-type doped region.

Definitely, alternatively, one of the first doped region <NUM> and the second doped region <NUM> in the solar cell uses the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region uses a conventional structure (such as a passivated contact structure or a diffusion structure). In this embodiment, preferably, the other one is a third doped layer disposed in the back side of the silicon substrate <NUM>. That is to say, the other one uses the conventional diffusion structure, as shown in <FIG>, <FIG>, <FIG>, which relates to comparative examples, not forming part of the invention. Definitely, optionally, the other one may also use the conventional passivated contact structure. The passivated contact structure includes a tunneling layer and a doped region (not shown in the figure). It needs to be noted that, the third doped layer is also a monocrystalline silicon doped layer doped with a group-III or group-V element. For a specific structure of the third doped layer, refer to the description of the first doped layer in the above embodiments. It needs to be further noted that, since the first doped region <NUM> and the second doped region <NUM> have opposite polarities, and the first doped layer and the second doped layer have the same doping polarity, the first doped layer and the third doped layer are respectively doped with an element of a different group. That is to say, when the first doped layer is doped with a group-III element, the third doped layer is doped with a group-V element. When the first doped layer is doped with a group-V element, the third doped layer is doped with a group-III element.

When the first doped region <NUM> and the second doped region <NUM> both use the doped region structure described in the above embodiments, a material and a thickness selected for each layer structure in the first doped region <NUM> may be same as or different from those selected for each layer structure in the second doped region <NUM>. For example, when a passivation layer in the first doped region <NUM> is specifically selected as a silicon oxide layer and a silicon carbide layer, a passivation layer in the second doped region <NUM> may be selected to be the same as the passivation layer in the first doped region <NUM>, or may be selected as a material different from the passivation layer in the first doped region <NUM>, such as an aluminum oxide layer and a silicon carbide layer.

A thickness of the passivation layer in the first doped region <NUM> may be designed same as or different from a thickness of the passivation layer in the second doped region <NUM>. Preferably, regardless of whether the material of the passivation layer in the first doped region <NUM> is the same as the material of the passivation layer in the second doped region <NUM>, the thickness of the passivation layer corresponding to the first doped layer doped with the group-III element is designed to be larger, and the thickness of the passivation layer corresponding to the first doped layer doped with the group-V element is designed to be smaller. That is to say, the thickness of the passivation layer in the P-type doped region is greater than the thickness of the passivation layer in the N-type doped region. A main reason lies in that the P-type doped region requires a process such as boron doping and a higher temperature, and requires a thicker passivation layer due to a requirement for a plurality of heat treatment processes. In this embodiment, the material and the thickness of each layer structure in the first doped region <NUM> and in the second doped region <NUM> are correspondingly designed according to actual use requirements, which are not specifically limited herein.

In accordance with the present invention, a hole density of the passivation layer in the P-type doped region is greater than a hole density of the passivation layer in the N-type doped region. The hole density means a quantity of holes per unit area. That is to say, in a same unit area, the passivation layer in the P-type doped region has more holes than the passivation layer in the N-type doped region. A main reason lies in that a conductivity of the P-type doped region is relatively poor, and the thickness of the passivation layer in the P type doped region is relatively large. Therefore, more holes are required to enhance the conductivity.

In an embodiment of the disclosure, the first dielectric layer <NUM> and the second dielectric layer <NUM> each are an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer, or a combination thereof. The first dielectric layer <NUM> and the second dielectric layer <NUM> achieve a passivation effect. The first dielectric layer <NUM> and the second dielectric layer <NUM> each are designed as a structure having at least one layer. Refractive indexes of the first dielectric layer and the second dielectric layer decrease from the silicon substrate <NUM> toward the outside, so that a film layer close to the silicon substrate <NUM> achieves the passivation effect, and a film layer away from the silicon substrate <NUM> achieves an antireflection effect, thereby enhancing the antireflection effect. In this way, the silicon substrate <NUM> absorbs and uses light more effectively, and the short-circuit current density is increased. Each film layer in the first dielectric layer <NUM> and in the second dielectric layer <NUM> that has a different structure comprises a plurality of films each having a specific refractive index. According to the above, the film layers are arranged such that the refractive indexes of the film layers decrease from the silicon substrate <NUM> toward the outside. For example, the silicon oxide layer in the first dielectric layer <NUM> comprises a plurality of silicon oxide films having refractive indexes decreasing from the silicon substrate <NUM> toward the outside.

It should be noted that, the first dielectric layer <NUM> and the second dielectric layer <NUM> may have a same structural arrangement or different structural arrangements. The film layer structures in the first dielectric layer <NUM> and in the second dielectric layer <NUM> may be correspondingly designed according to actual use requirements, which are not specifically limited herein. Preferably, the first dielectric layer <NUM> and the second dielectric layer <NUM> are designed same, so that the first dielectric layer <NUM> and the second dielectric layer <NUM> may be prepared on the front side and the back side of the silicon substrate <NUM> respectively by using a same process.

In a preferred embodiment of the disclosure, the first dielectric layer <NUM> and/or the second dielectric layer <NUM> include/includes a double-layer structure of an aluminum oxide layer and a silicon carbide layer or a double-layer structure of a silicon oxide layer and a silicon carbide layer. In this case, an entire thickness of the first dielectric layer <NUM> is greater than <NUM>, and an entire thickness of the second dielectric layer <NUM> is greater than <NUM>. It may be understood that, the specific structural arrangements of the first dielectric layer <NUM> and the second dielectric layer <NUM> include but are not limited to the specific examples listed above.

Further, in an embodiment of the disclosure, a thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer <NUM> is less than <NUM>. A thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer <NUM> is less than <NUM>. A thickness of the silicon carbide layer in the first dielectric layer <NUM> and/or in the second dielectric layer <NUM> is greater than <NUM>. The silicon carbide layer in the first dielectric layer <NUM> and/or in the second dielectric layer <NUM> can not only provide a hydrogen passivation effect, but also reduce parasitic light absorption by virtue of a large optical band gap and a small absorption coefficient.

It needs to be noted that, the multi-layer structure in this embodiment of the disclosure conforms to an arrangement sequence from the silicon substrate <NUM> toward the outside. For example, when the above first dielectric layer <NUM> includes the aluminum oxide layer and the silicon carbide layer, the aluminum oxide layer is close to the silicon substrate <NUM>, and the silicon carbide layer is close to the outside. It needs to be further noted that, in the drawings, <FIG> only show the first dielectric layer <NUM> and the second dielectric layer <NUM> as double-layer structures. However, it may be understood that, the first dielectric layer <NUM> and the second dielectric layer <NUM> may also include other quantities of layers. Respective specific structures may be designed according to actual needs, and are not completely limited to the drawings. It needs to be further noted that, each drawing of the disclosure is merely used to describe the specific structural distribution in the solar cell, but does not correspond to an actual size of each structure. The drawings do not completely correspond to specific actual sizes in this embodiment, and the actual size of each structure needs to conform to specific parameters provided in this embodiment.

Further, the silicon carbide layer in the first dielectric layer <NUM> and/or in the second dielectric layer <NUM> comprises at least one silicon carbide film. The refractive indexes of the silicon carbide films decrease from the silicon substrate <NUM> toward the outside. Optionally, the refractive indexes of the above material may be generally selected as follows: the refractive index of monocrystalline silicon is <NUM>, the refractive index of amorphous silicon is in a range of <NUM>-<NUM>, the refractive index of polysilicon is <NUM>, the refractive index of silicon carbide is in a range of <NUM>-<NUM>, the refractive index of silicon nitride is in a range of <NUM>-<NUM>, the refractive index of silicon oxynitride is in a range of <NUM>-<NUM>, the refractive index of silicon oxide is <NUM>, and the refractive index of aluminum oxide is <NUM>. It may be understood that, the refractive indexes of the above materials may also be set to other values according to actual use requirements, which are not specifically limited herein.

Further, in an embodiment of the disclosure, a magnesium fluoride layer is further disposed outside the first dielectric layer <NUM> and/or the second dielectric layer <NUM>. That is to say, in addition to one or a combination of more of the aluminum oxide layer, the silicon nitride layer, the silicon oxynitride layer, the silicon carbide layer, the amorphous silicon layer, and the silicon oxide layer selected for the first dielectric layer <NUM> and the second dielectric layer <NUM>, a magnesium fluoride layer may be further disposed outside the first dielectric layer <NUM> and/or the second dielectric layer <NUM>. The magnesium fluoride layer is required to have a lowest refractive index. Generally, the refractive index is set to <NUM>. The magnesium fluoride layer has an optical effect of enhancing antireflection.

Further, in an embodiment of the disclosure, an electric field layer or a floating junction is disposed between the front side of the silicon substrate <NUM> and the first dielectric layer <NUM>. Specifically, the electric field layer is prepared by means of phosphorus diffusion on the silicon substrate <NUM>, or the floating junction is prepared by means of boron diffusion. The electric field layer or the floating junction is used as a front surface electric field of the solar cell.

In an embodiment of the disclosure, the first conductive layer <NUM> and/or the second conductive layer <NUM> are/is a TCO transparent conductive film and/or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, or a silver-coated copper electrode. Further, the copper electrode is electroplated copper prepared by using an electroplating process or the copper electrode prepared by means of physical vapor deposition. A nickel electrode, a chromium electrode, a titanium electrode, or a tungsten electrode is used as a seed layer or a protective layer of the electroplated copper. It needs to be noted that, the first conductive layer <NUM> and the second conductive layer <NUM> may select a same electrode or different electrodes. For example, the first conductive layer <NUM> and the second conductive layer <NUM> both select the aluminum electrode. Alternatively, the first conductive layer <NUM> selects the silver electrode, and the second conductive layer <NUM> selects the aluminum electrode.

Further, in an embodiment of the disclosure, a texturing process is further performed before the first dielectric layer <NUM> is prepared on the front side of the silicon substrate <NUM>. A shape formed on the front side includes but is not limited to an alkali polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape ranging among the above shapes. The surface shape formed on the front side of the silicon substrate <NUM> helps reduce the reflection of sunlight on the front side, thereby improving the conversion efficiency of the solar cell.

Further, in an embodiment of the disclosure, the second dielectric layer <NUM> may cover only a region between the first doped region <NUM> and the second doped region <NUM> on the silicon substrate <NUM>, or may extend to cover the first doped region <NUM> and/or the second doped region <NUM>. When the second dielectric layer <NUM> covers only the region between the first doped region <NUM> and the second doped region <NUM> on the silicon substrate <NUM>, the first conductive layer <NUM> covers an entire back side of the first doped region <NUM> for electric connection, and the second conductive layer <NUM> covers an entire back side of the second doped region <NUM> for electric connection. When the second dielectric layer <NUM> extends to cover the first doped region <NUM> and/or the second doped region <NUM>, the first conductive layer <NUM> covers a back surface of a remaining part that not covered by the second dielectric layer <NUM> in the first doped region <NUM> for achieve electric connection, and the second conductive layer <NUM> covers a back surface of a remaining part not covered by the second dielectric layer <NUM> in the second doped region <NUM> for electric connection. When the second dielectric layer <NUM> covers the entire back side, the first conductive layer <NUM> penetrates the second dielectric layer <NUM> through perforations or the like to be electrically connected to the first doped region <NUM>, and the second conductive layer <NUM> penetrates the second dielectric layer <NUM> through perforations or the like to be electrically connected to the second doped region <NUM>. The conductive polarities of the first conductive layer <NUM> and the second conductive layer <NUM> are determined according to the polarities of the first doped region <NUM> and the second doped region <NUM>, which are not specifically limited herein.

In an embodiment of the disclosure, referring to <FIG> and <FIG>, the first doped region <NUM> and the second doped region <NUM> are alternately disposed on the back side of the silicon substrate <NUM>. In order to avoid undesirable phenomena such as electric leakage caused by unobstructed connection between the first doped region <NUM> and the second doped region <NUM>, a trench is provided between the first doped region <NUM> and the second doped region <NUM>. The trench separates the first doped region <NUM> from the second doped region <NUM>. Correspondingly, the second dielectric layer <NUM> covers the trench. It needs to be noted that, a surface shape of the trench that is in contact with the silicon substrate <NUM> may further have a rough texture structure disposed thereon. The rough texture structure is usually formed by means of texturing, and includes but is not limited to an alkali polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape ranging among the above shapes. An irregular hemispherical texture may be formed by means of acid texturing, a pyramid-shaped texture may be formed by means of alkali texturing, or the pyramid-shaped texture may be formed first by means of alkali texturing and then smoothing is performed on a top of a pyramid-shaped by means of acid texturing. In this way, the surface shape formed at the trench on the back side of the silicon substrate <NUM> helps the silicon substrate <NUM> absorb and reuse light more effectively, and the short-circuit current density is increased, thereby enhancing the conversion efficiency of the solar cell.

In another embodiment of the disclosure, referring to <FIG> and <FIG>, grooves spaced apart are provided on the back side of the silicon substrate <NUM>. The first doped region <NUM> and the second doped region <NUM> are alternately disposed in the grooves. The grooves may be formed by means of laser ablation or by using a combination of a mask (such as a hard mask, a silicon oxide mask, a silicon nitride mask, or a photoresist mask) and wet/dry etching. By means of the grooves spaced apart on the back side of the silicon substrate <NUM>, a region between two adjacent grooves of the silicon substrate <NUM> is generally formed into a protrusion shape. Therefore, the blocking between the first doped region <NUM> and the second doped region <NUM> disposed in the grooves can be realized by the protrusion structure between the grooves of the silicon substrate <NUM>. Definitely, optionally, a trench may be further disposed between the first doped region <NUM> and the second doped region <NUM>. In this case, a trench may be provided in the protrusion structure or the groove, so that double isolation between the first doped region <NUM> and the second doped region <NUM> can be realized by the protrusion structure between the grooves of the silicon substrate <NUM> and the trench structure.

The first doped region <NUM> and the second doped region <NUM> include at least the doped region structure described in the above embodiments. It needs to be noted that, the passivation layer in the doped region structure may cover only a bottom wall of the grooves, or may extend to cover sidewalls of the groove. Preferably, the passivation layer covers the bottom wall and the sidewalls of the groove. In this case, the first doped layer is correspondingly disposed on the bottom wall and the sidewalls of the groove. Therefore, carriers generated on the silicon substrate <NUM> are easily separated by using the passivation layer on the sidewalls of the groove and selectively collected in the corresponding second doped layer. In this way, multidimensional collection of the carriers in the bottom wall and the sidewalls of the groove can be realized. It needs to be noted that, the first doped region <NUM> and the second doped region <NUM> may be respectively disposed in partial regions in the corresponding grooves.

Further, in an embodiment of the disclosure, the groove is in a circular arc shape, a trapezoidal shape, or a square shape. The groove is preferably designed as the circular arc shape or the trapezoidal shape. When the groove is designed as the circular arc shape or the trapezoidal shape, inner walls of the groove can reflect light more desirably, and a surface area of the passivation layer of the doped region structure that is contact with the first doped layer can be further increased. Definitely, when the groove is designed as the square shape, an actual production process is much simpler. It needs to be further noted that, the grooves may have a same shape or different shapes. For example, the groove of the first doped region <NUM> and the groove of the second doped region <NUM> are designed as the square shape, or the groove of the first doped region <NUM> is designed as the square shape, and the groove of the second doped region <NUM> is designed as the circular arc shape, or the like. Thus, the shapes of the grooves may be designed according to actual use requirements, which are not specifically limited herein. Further, a width and a depth of each groove may be designed same or differently, and may be designed according to actual use requirements, which are not specifically limited herein.

Further, in an embodiment of the disclosure, a total thickness of the first doped region <NUM> and/or a total thickness of the second doped region <NUM> may be greater than, less than, or equal to the depth of the groove. When the total thickness of the first doped region <NUM> and/or the total thickness of the second doped region <NUM> are/is less than or equal to the depth of the groove, the first doped region <NUM> and/or the second doped region <NUM> do/does not extend out of the groove. Therefore, the blocking of the first doped region <NUM> and/or the second doped region <NUM> is realized directly by the protrusion structure between the grooves. When the total thickness of the first doped region <NUM> and/or the total thickness of the second doped region <NUM> are/is greater than the depth of the groove, the first doped region <NUM> and/or the second doped region <NUM> may extend to protrusion regions among the grooves. That is to say, for example, the first doped region <NUM> may extend to a partial or entire region between the grooves, but does not come into contact with the adjacent second doped region <NUM>.

Further, in an embodiment of the disclosure, the back side of the silicon substrate <NUM> in the protrusion regions among the grooves has a rough texture structure. The rough texture structure is usually formed by means of texturing, and includes but is not limited to an alkali polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape ranging among the above shapes. An irregular hemispherical texture may be formed by means of acid texturing, a pyramid-shaped texture may be formed by means of alkali texturing, or the pyramid-shaped text e may be formed first by means of alkali texturing and then smoothing is performed on a top of a pyramidshaped by means of acid texturing. It may be understood that, the rough texture structure may also be arranged on the entire back side of the silicon substrate <NUM>.

In still another embodiment of the disclosure, referring to <FIG>, <FIG>, grooves spaced apart are provided on the back side of the silicon substrate <NUM>. One of the first doped region <NUM> and the second doped region <NUM> is disposed in one of the grooves, and the other of the first doped region and the second doped region is disposed outside the groove. In order to realize the blocking between the first doped region <NUM> and the second doped region <NUM>, a trench may be further provided between the first doped region <NUM> and the second doped region <NUM>. The first doped region <NUM> is separated from the second doped region <NUM> by the trench, as shown in <FIG> and <FIG>. The first doped region <NUM> and the second doped region <NUM> may also be disposed in partial regions inside and outside the groove, so that the silicon substrate <NUM> inside and outside the groove that is not covered by the first doped region <NUM> and the second doped region <NUM> realizes the separation of the first doped region <NUM> from the second doped region <NUM>, as shown in <FIG>. Definitely, the non-contact between the first doped region <NUM> and the second doped region <NUM> may also be realized by setting the depth of the groove. For other specific descriptions of the groove and the first doped region <NUM> and the second doped region <NUM> disposed inside and outside the groove, refer to the above descriptions, and details are not described herein again.

Therefore, in an embodiment of the disclosure, the first doped region <NUM> and the second doped region <NUM> both may be disposed on the back side of the silicon substrate <NUM>, or both may be disposed on the grooves spaced apart on the silicon substrate <NUM>, or may be respectively disposed inside and outside the grooves spaced on the silicon substrate <NUM>. The first doped region <NUM> and the second doped region <NUM> include at least the doped region structure described in the above embodiments, and include a diffusion structure comprising the third doped layer or a passivated contact structure comprising the tunneling layer and the doped region. Thus, the prepared solar cell may be as follows.

Cell I: The first doped region <NUM> and the second doped region <NUM> are both disposed on the back side of the silicon substrate <NUM>. The first doped region <NUM> and the second doped region <NUM> have the doped region structure described in the above embodiments. A trench is provided between the first doped region <NUM> and the second doped region <NUM>.

Cell II: The first doped region <NUM> and the second doped region <NUM> are both disposed on the back side of the silicon substrate <NUM>. One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the diffusion structure comprising the third doped layer. A trench is provided between the first doped region <NUM> and the second doped region <NUM>.

Cell III: The first doped region <NUM> and the second doped region <NUM> are both disposed on the back side of the silicon substrate <NUM>. One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the passivated contact structure comprising the tunneling layer and the doped region. A trench is provided between the first doped region <NUM> and the second doped region <NUM>.

Cell IV: The first doped region <NUM> and the second doped region <NUM> are alternately disposed in the grooves of the silicon substrate <NUM>. The first doped region <NUM> and the second doped region <NUM> both have the doped region structure described in the above embodiments.

Cell V: The first doped region <NUM> and the second doped region <NUM> are alternately disposed in the grooves of the silicon substrate <NUM>. One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the diffusion structure comprising the third doped layer.

Cell VI: The first doped region <NUM> and the second doped region <NUM> are alternately disposed in the grooves of the silicon substrate <NUM>. One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the passivated contact structure comprising the tunneling layer and the doped region.

Cell VII: The first doped region <NUM> is disposed in the groove, and the second doped region <NUM> is disposed on the protrusion. The first doped region <NUM> and the second doped region <NUM> both have the doped region structure described in the above embodiments. A trench may be provided between the first doped region <NUM> and the second doped region <NUM>.

Cell VIII: One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the diffusion structure comprising the third doped layer. The doped region structure is disposed on the protrusion, and the diffusion structure is disposed in the groove. A trench may be provided between the first doped region <NUM> and the second doped region <NUM>.

Cell IX: One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the diffusion structure comprising the third doped layer. The doped region structure is disposed in the groove, and the diffusion structure is disposed on the protrusion. A trench may be provided between the first doped region <NUM> and the second doped region <NUM>.

Cell X: One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the passivated contact structure comprising the tunneling layer and the doped region. The doped region structure is disposed on the protrusion, and the passivated contact structure is disposed in the groove. A trench may be provided between the first doped region <NUM> and the second doped region <NUM>.

Cell XI: One of the first doped region <NUM> and the second doped region <NUM> has the doped region structure described in the above embodiments, and the other of the first doped region and the second doped region has the passivated contact structure comprising the tunneling layer and the doped region. The doped region structure is disposed in the groove, and the passivated contact structure is disposed on the protrusion. A trench may be provided between the first doped region <NUM> and the second doped region <NUM>.

Different from the passivated contact structure in the prior art, in this embodiment, the doped region structure is disposed, the passivation layer in the doped region structure is arranged as a porous structure, and the hole region has the first doped layer and/or the second doped layer. Therefore, a conductive channel is formed in the hole region of the passivation layer, so that a desirable resistivity of the passivation layer is formed. In this way, a thickness of the passivation layer has a less impact on the resistance, and the control requirements for the thickness of the passivation layer are lowered. Thus, more methods are applicable to preparation of the passivation layer compared with the prior art. The first doped layer is disposed between the silicon substrate and the passivation layer to form a separation electric field capable of enhancing surface electron holes, so that the field passivation effect is enhanced. Since a Fermi level of the first doped layer is different from a Fermi level of the silicon substrate, the Fermi level of the first doped layer is changed. A solid concentration of impurities (transition metals) is increased, so that an additional impurity gettering effect is formed. In addition, in the porous structure, the second doped layer is connected to the silicon substrate through the doped hole region and the first doped layer, so that the overall resistance of the prepared cell is further reduced, and the conversion efficiency of the cell is improved. In this way, the difficulty in production and the limitation on the conversion efficiency as a result of precise requirements for the thickness of the conventional tunneling layer are resolved.

A third embodiment of the disclosure provides a solar cell. For ease of description, only parts related to this embodiment of the disclosure are shown. Referring to <FIG>, the solar cell provided in this comparative example, not forming part of the invention, includes:.

The doped region structure <NUM> and the fourth doped layer <NUM> have opposite polarities.

The fourth doped layer <NUM> is a monocrystalline silicon doped layer doped with a group-III or group-V element. For details of the fourth doped layer, refer to the description of the first doped layer in the doped region structure <NUM> in the above embodiments. It needs to be further noted that, since the doped region structure <NUM> and the fourth doped layer <NUM> have opposite polarities, the first doped layer and the fourth doped layer <NUM> are respectively doped with an element of a different group. That is to say, when the first doped layer is doped with a group-III element, the fourth doped layer <NUM> is doped with a group-V element. When the first doped layer is doped with a group-V element, the fourth doped layer <NUM> is doped with a group-III element.

In an embodiment of the disclosure, the third dielectric layer <NUM> and the fourth dielectric layer <NUM> each are an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, a silicon oxide layer, or a combination thereof. The third dielectric layer <NUM> and the fourth dielectric layer <NUM> achieve a passivation effect. The third dielectric layer <NUM> and the fourth dielectric layer <NUM> each are designed as a structure having at least one layer. Refractive indexes of the third dielectric layer and the fourth dielectric layer decrease from the silicon substrate <NUM> toward the outside, so that a film layer close to the silicon substrate <NUM> achieves the passivation effect, and a film layer away from the silicon substrate <NUM> achieves an antireflection effect, thereby enhancing the anti- reflection effect. In this way, the silicon substrate <NUM> absorbs and uses light more effectively, and the short-circuit current density is increased. Each film layer in the third dielectric layer <NUM> and in the fourth dielectric layer <NUM> that has a different structure comprises a plurality of films each having a specific refractive index. According to the above, the film layers are arranged such that the refractive indexes of the film layers decrease from the silicon substrate <NUM> toward the outside. For example, the silicon oxide layer in the third dielectric layer <NUM> comprises a plurality of silicon oxide films having refractive indexes decreasing from the silicon substrate <NUM> toward the outside.

It should be noted that, the third dielectric layer <NUM> and the fourth dielectric layer <NUM> may have a same structural arrangement or different structural arrangements. The film layer structures in the third dielectric layer <NUM> and the fourth dielectric layer <NUM> may be correspondingly designed according to actual use requirements, which are not specifically limited herein. Preferably, the third dielectric layer <NUM> and the fourth dielectric layer <NUM> are designed same, so that the fourth dielectric layer <NUM> and the third dielectric layer <NUM> may be prepared on the front side and the back side of the silicon substrate <NUM> respectively by using a same process.

In a preferred embodiment of the disclosure, the third dielectric layer <NUM> and/or the fourth dielectric layer <NUM> include/includes a double-layer structure of an aluminum oxide layer and a silicon carbide layer or a double-layer structure of a silicon oxide layer and a silicon carbide layer. An entire thickness of the third dielectric layer <NUM> is greater than <NUM>, and an entire thickness of the fourth dielectric layer <NUM> is greater than <NUM>. It may be understood that, the specific structural arrangements of the third dielectric layer <NUM> and the fourth dielectric layer <NUM> include but are not limited to the specific examples listed above.

Further, in an embodiment of the disclosure, a thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer <NUM> is less than <NUM>. A thickness of the aluminum oxide layer or the silicon oxide layer in the fourth dielectric layer <NUM> is less than <NUM>. A thickness of the silicon carbide layer in the third dielectric layer <NUM> and/or in the fourth dielectric layer <NUM> is greater than <NUM>. The silicon carbide layer in the third dielectric layer <NUM> and/or in the fourth dielectric layer <NUM> can not only provide a hydrogen passivation effect, but also reduce parasitic light absorption by virtue of a large optical band gap and a small absorption coefficient.

It needs to be noted that, the multi-layer structure in this embodiment of the disclosure conforms to an arrangement sequence from the silicon substrate <NUM> toward the outside. For example, when the above third dielectric layer <NUM> includes the aluminum oxide layer and the silicon carbide layer, the aluminum oxide layer is close to the silicon substrate <NUM>, and the silicon carbide layer is close to the outside. It needs to be further noted that, in the drawings, <FIG> only shows the third dielectric layer <NUM> and the fourth dielectric layer <NUM> as double-layer structures. However, it may be understood that, the third dielectric layer <NUM> and the fourth dielectric layer <NUM> may also include other quantities of layers. Respective specific structures may be designed according to actual needs, and are not completely limited to the drawings. It needs to be further noted that, each drawing of the disclosure is merely used to describe the specific structural distribution in the solar cell, but does not correspond to an actual size of each structure. The drawings do not completely correspond to specific actual sizes in this embodiment, and the actual size of each structure needs to conform to specific parameters provided in this embodiment.

Further, the silicon carbide layer in the third dielectric layer <NUM> and/or in the fourth dielectric layer <NUM> comprises at least one silicon carbide film. The refractive indexes of the silicon carbide films decrease from the silicon substrate <NUM> toward the outside. Optionally, the refractive indexes of the above material may be generally selected as follows: the refractive index of monocrystalline silicon is <NUM>, the refractive index of amorphous silicon is in a range of <NUM>-<NUM>, the refractive index of polysilicon is <NUM>, the refractive index of silicon carbide is in a range of <NUM>-<NUM>, the refractive index of silicon nitride is in a range of <NUM>-<NUM>, the refractive index of silicon oxynitride is in a range of <NUM>-<NUM>, the refractive index of silicon oxide is <NUM>, and the refractive index of aluminum oxide is <NUM>. It may be understood that, the refractive indexes of the above materials may also be set to other values according to actual use requirements, which are not specifically limited herein.

Further, in an embodiment of the disclosure, a magnesium fluoride layer is further disposed outside the third dielectric layer <NUM> and/or the fourth dielectric layer <NUM>. That is to say, in addition to one or a combination of more of the aluminum oxide layer, the silicon nitride layer, the silicon oxynitride layer, the silicon carbide layer, the amorphous silicon layer, and the silicon oxide layer selected for the third dielectric layer <NUM> and the fourth dielectric layer <NUM>, a magnesium fluoride layer may be further disposed outside the third dielectric layer <NUM> and/or the fourth dielectric layer <NUM>. The magnesium fluoride layer is required to have a lowest refractive index. Generally, the refractive index is set to <NUM>. The magnesium fluoride layer has an optical effect of enhancing antireflection.

In an embodiment of the disclosure, the third conductive layer <NUM> and/or the fourth conductive layer <NUM> are/is a TCO transparent conductive film and/or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, or a silver-coated copper electrode. Further, the copper electrode is electroplated copper prepared by using an electroplating process or the copper electrode prepared by means of physical vapor deposition. A nickel electrode, a chromium electrode, a titanium electrode, or a tungsten electrode is used as a seed layer or a protective layer of the electroplated copper. It needs to be noted that, the third conductive layer <NUM> and the fourth conductive layer <NUM> may select a same material or different materials. For example, the third conductive layer <NUM> and the fourth conductive layer <NUM> both select the aluminum electrode, or the third conductive layer <NUM> selects the silver electrode, and the fourth conductive layer <NUM> selects the aluminum electrode. Further, the third conductive layer <NUM> penetrates the third dielectric layer <NUM> through perforations or the like to be electrically connected to the doped region structure <NUM>. The fourth conductive layer <NUM> penetrates the fourth dielectric layer <NUM> through perforations or the like to be electrically connected to the fourth doped layer <NUM>. The conductive polarities of the third conductive layer <NUM> and the fourth conductive layer <NUM> are determined according to the polarities of the doped region structure <NUM> and the fourth doped layer <NUM>, which are not specifically limited herein.

Further, in an embodiment of the disclosure, a texturing process is further performed before the fourth dielectric layer <NUM> is prepared on the front side of the silicon substrate <NUM>. A shape formed on the front side is not limited to an alkali polished surface, a mechanically polished surface, a random pyramid shape, an inverted pyramid shape, a spherical cap shape, a V-shaped groove, and a shape ranging among the above shapes. The surface shape formed on the front side of the silicon substrate <NUM> helps reduce the reflection of sunlight on the front side, thereby improving the conversion efficiency of the solar cell.

A fourth embodiment of the disclosure further provides a cell assembly. The cell assembly includes the solar cell described in Example <NUM>.

A fifth embodiment of the disclosure further provides a photovoltaic system. The photovoltaic system includes the cell assembly described in Example <NUM>.

A sixth embodiment of the disclosure further provides a cell assembly. The cell assembly includes the solar cell described in Example <NUM>.

A seventh embodiment of the disclosure further provides a photovoltaic system. The photovoltaic system includes the cell assembly described in Example <NUM>.

Claim 1:
A solar cell, comprising:
a silicon substrate (<NUM>);
a first doped region (<NUM>) and a second doped region (<NUM>), alternately disposed on a back side of the silicon substrate (<NUM>) and having opposite polarities;
a first dielectric layer (<NUM>), disposed on a front side of the silicon substrate (<NUM>);
a second dielectric layer (<NUM>), disposed between the first doped region (<NUM>) and the second doped region (<NUM>); and
a first conductive layer (<NUM>) and a second conductive layer (<NUM>), respectively disposed in the first doped region (<NUM>) and the second doped region (<NUM>);
wherein:
the first doped region (<NUM>) and the second doped region (<NUM>) use a doped region structure, the doped region structure comprising a first doped layer (<NUM>), a passivation layer (<NUM>), and a second doped layer (<NUM>) that are disposed on the silicon substrate (<NUM>) in sequence;
wherein:
the passivation layer (<NUM>) is a porous structure comprising a hole region, and the first doped layer (<NUM>) and/or the second doped layer (<NUM>) are disposed in the hole region; and
the second doped layer (<NUM>) is connected to the silicon substrate (<NUM>) through the doped hole region and the first doped layer (<NUM>);
one of the first doped region (<NUM>) and the second doped region (<NUM>) is a P-type doped region, and the other of the first doped region (<NUM>) and the second doped region (<NUM>) is an N-type doped region; and the first doped layer (<NUM>) and the second doped layer (<NUM>) in the P-type doped region are P-type doped layers, and the first doped layer (<NUM>) and the second doped layer (<NUM>) in the N-type doped region are N-type doped layers
characterized in that
a hole density of a passivation layer in the P-type doped region is greater than a hole density of a passivation layer in the N-type doped region.