Patent Description:
Processor cores are placed in a powered-down state (which can be referred to as a C6 or CC6 state) to reduce leakage current when the processor cores are not actively performing operations such as executing instructions. The caches that store state information for the processor cores are flushed and then powered-down prior to placing the corresponding processor cores in the powered-down state. For example, entries in the TLB of a processor core are lost when the processor core is powered-down. For another example, cache entries in the L1 cache or L2 cache associated with a processor core are flushed to an L3 cache or an external memory such as a dynamic random access memory (DRAM) or a disk drive. The cache entries are then lost from the L1 or L2 caches when power is removed from the processor core and the L1 or L2 caches. The absence of up-to-date information in the caches reduces the performance of the processor core when it exits the powered-down state.

<CIT> discloses flushing a cache to a higher level cache when the processor enters a low power mode. <CIT> discloses copying cache contents to a buffer when the processor enters a low power mode.

At least in part to accelerate the performance of a processor core when it exits a powered-down state and to maintain cache coherence during the powered-down state, entries in a cache associated with the powered-down processor core are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. The processor core enters the powered-down state after the copies of entries are stored in the retention region. Information that indicates invalidation of one or more entries in the cache is stored while the processor core is in the powered-down state. The cache is restored based on the stored copies of the entries and the stored invalidation information. Restoring is performed in response to the processor core initiating an exit from the powered-down state. The retention region is implemented in a portion of the memory hierarchy that remains powered-up and running concurrently with the processor core being in the powered-down state. The retention region can include a higher-level cache in the cache hierarchy, an external memory such as a dynamic random access memory (DRAM), or using storage elements in the processor core that are powered by a power supply that continues to be energized while the processor core is powered down. For example, the retention region can use the storage elements of the cache itself, i.e., the data in the cache can be retained in situ if the cache is provided with a power supply that continues to be energized while the rest of the core is in a powered-down state.

In some embodiments, the cache is a translation lookaside buffer (TLB) that caches virtual-to-physical address translations for use by the processor core. Entries in the TLB are stored in a retention region in response to the processor core entering a powered-down state. Information indicating requests to invalidate entries in the TLB is stored while the corresponding processor core is powered down, e.g., individual requests are stored in a queue or a bit is set to a value to indicate that one or more entries of the TLB have been invalidated. The stored TLB entries and the invalidation information are used to restore the TLB by repopulating the entries in response to the processor core powering up. For example, after the TLB entries are repopulated from the retention region, the TLB invalidation requests are replayed to invalidate entries in the TLB. In the case of a queue overflow, the entire TLB is invalidated because all the information needed to restore the TLB is no longer available in the queue. For another example, the entire TLB is invalidated if the bit has a value that indicates that one or more of the TLB entries have been invalidated while the processor core was powered down. In some embodiments, instead of storing entries in the TLB in response to powering down the processor core, a list of virtual addresses in the TLB is stored in the retention region. The virtual addresses are prefetched to preemptively initiate page table walks that populate the entries in the TLB when the processor core powers up.

In some embodiments, the cache is a lower-level cache in an inclusive cache hierarchy such as an L1 cache or an L2 cache in a cache hierarchy. The retention region can include a higher-level cache such as an L3 cache or an external memory such as a DRAM that receives a retention voltage while the processor core is powered down. The retention region can also be implemented in the cache itself by providing a retention power supply to storage elements of the cache. Modified, or dirty, values in the cache are written to the higher-level cache or external memory in response to the processor core entering the powered-down state, e.g., by rinsing the cache to write out modified values of cache entries or by flushing all the entries in the cache. Information indicating invalidation of cache entries in the cache is stored while the processor core is powered-down. Some embodiments of the higher-level cache include shadow tags that store physical addresses of the cache entries associated with a lower-level cache of the powered-down processor core along with information indicating whether the entry is valid and clean. The shadow tags can also store information indicating whether the entry was invalidated while the processor core was powered down. If the retention region is implemented in the cache itself, then the cache does not need to be repopulated in order to be restored. If the retention region is not implemented in the cache itself, the cache is repopulated using the information in the shadow tags in response to the processor core powering up. For example, the valid entries for the lower-level cache are prefetched based on the corresponding physical addresses stored in the shadow tags.

Some embodiments implement a probe queue that stores information indicating the probes received while the processor core is powered-down. If the processor core includes a shadow tag, the probe queue only records the probes that hit on an address in the shadow tag. The probe queue may also be implemented by adding a field to each entry of the shadow tags indicating that the corresponding lower-level cache line is to be invalidated in response to powering up the processor core. The probes stored in the probe queue are sent to the cache in response to the processor core powering up. In the case of a probe queue overflow, the processor core is powered-up to service the probes in the probe queue or the entire cache is invalidated when the processor core powers up. Other approaches to maintaining cache coherence while the processor core is powered-down can also be used. In some cases, the cache is powered-up in response to receiving a probe, which allows the cache to invalidate the entry indicated by the probe and then power back down. This approach consumes significant overhead. Each cache level could also be provided with an "always on" clock that allows the cache to clock up and down to service probes. In some embodiments, other mechanisms such as bloom filters are used to identify probes that could possibly hit in the lower-level cache and therefore must be recorded in the probe queue.

<FIG> is a block diagram of a processing system <NUM> according to some embodiments. The processing system <NUM> includes or has access to a memory <NUM> or other storage component that is implemented using a non-transitory computer readable medium such as a dynamic random access memory (DRAM). However, the memory <NUM> can also be implemented using other types of memory including static random access memory (SRAM), nonvolatile RAM, and the like. The memory <NUM> is referred to as an external memory since it is implemented external to the processing units implemented in the processing system <NUM>. The processing system <NUM> also includes a bus <NUM> to support communication between entities implemented in the processing system <NUM>, such as the memory <NUM>. Some embodiments of the processing system <NUM> include other buses, bridges, switches, routers, and the like, which are not shown in <FIG> in the interest of clarity.

The processing system <NUM> includes a graphics processing unit (GPU) <NUM> that is configured to render images for presentation on a display <NUM>. For example, the GPU <NUM> renders objects to produce values of pixels that are provided to the display <NUM>, which uses the pixel values to display an image that represents the rendered objects. Some embodiments of the GPU <NUM> are used for general purpose computing. In the illustrated embodiment, the GPU <NUM> implements multiple processor cores <NUM>, <NUM>, <NUM> (collectively referred to herein as "the processor cores <NUM>-<NUM>") that are configured to execute instructions concurrently or in parallel. The processor cores <NUM>-<NUM> are also referred to as shader engines.

The GPU <NUM> also includes a memory management unit (MMU) <NUM> that is used to support communication with the memory <NUM>. In the illustrated embodiment, the MMU <NUM> communicates with the memory <NUM> over the bus <NUM>. However, some embodiments of the MMU <NUM> communicate with the memory <NUM> over a direct connection or via other buses, bridges, switches, routers, and the like. The GPU <NUM> executes instructions stored in the memory <NUM> and the GPU <NUM> stores information in the memory <NUM> such as the results of the executed instructions. For example, the memory <NUM> stores a copy <NUM> of instructions from a program code that is to be executed by the GPU <NUM>. The MMU <NUM> includes a translation lookaside buffer (TLB) <NUM>, which is a cache that stores virtual-to-physical address translations used by the processor cores <NUM>-<NUM>. For example, the processor core <NUM> transmits a memory access request including a virtual address to the MMU <NUM>, which translates the virtual address to a physical address using a corresponding entry in the TLB <NUM>. The MMU <NUM> can then transmit a memory request (e.g., to the memory <NUM>) using the physical address.

The GPU <NUM> includes a cache hierarchy <NUM> that includes one or more levels of caches that are used to cache instructions or data for relatively low latency access by the processor cores <NUM>-<NUM>. The instructions that are dispatched to the processor cores <NUM>-<NUM> include one or more prefetch instructions that are used to prefetch information such as instructions or data into the cache hierarchy <NUM>. For example, a prefetch instruction executed on the processor core <NUM> prefetches an instruction from the copy <NUM> so that the instruction is available in the cache hierarchy <NUM> prior to the processor core <NUM> executing the instruction. Although the cache hierarchy <NUM> is depicted as external to the processor cores <NUM>-<NUM>, some embodiments of the processor cores <NUM>-<NUM> incorporate corresponding caches (such as L1 caches) that are interconnected to the cache hierarchy <NUM>.

The processing system <NUM> also includes a central processing unit (CPU) <NUM> that implements multiple processor cores <NUM>, <NUM>, <NUM>, which are collectively referred to herein as "the processor cores <NUM>-<NUM>. " The processor cores <NUM>-<NUM> are configured to execute instructions concurrently or in parallel. The CPU <NUM> is connected to the bus <NUM> and therefore communicates with the GPU <NUM> and the memory <NUM> via the bus <NUM>. The CPU <NUM> includes an MMU <NUM> to support communication with the memory <NUM>. The MMU <NUM> includes a TLB <NUM> that stores virtual-to-physical address translations used by the processor cores <NUM>-<NUM>. The CPU <NUM> executes instructions such as program code <NUM> stored in the memory <NUM> and the CPU <NUM> stores information in the memory <NUM> such as the results of the executed instructions. The CPU <NUM> is also able to initiate graphics processing by issuing draw calls to the GPU <NUM>.

Some embodiments of the CPU <NUM> include a cache hierarchy <NUM> that includes one or more levels of caches that are used to cache instructions or data for relatively low latency access by the processor cores <NUM>-<NUM>. Although the cache hierarchy <NUM> is depicted as external to the processor cores <NUM>-<NUM>, some embodiments of the processor cores <NUM>-<NUM> incorporate corresponding caches that are interconnected to the cache hierarchy <NUM>. In some embodiments, the instructions that are dispatched to the processor cores <NUM>-<NUM> include one or more prefetch instructions that are used to prefetch information such as instructions or data into the cache hierarchy <NUM>. For example, a prefetch instruction executed by a wave on the processor core <NUM> can prefetch an instruction from the program code <NUM> so that the instruction is available in the cache hierarchy <NUM> prior to the processor core <NUM> executing the instruction.

An input/output (I/O) engine <NUM> handles input or output operations associated with the display <NUM>, as well as other elements of the processing system <NUM> such as keyboards, mice, printers, external disks, and the like. The I/O engine <NUM> is coupled to the bus <NUM> so that the I/O engine <NUM> is able to communicate with the memory <NUM>, the GPU <NUM>, or the CPU <NUM>. In the illustrated embodiment, the I/O engine <NUM> is configured to read information stored on an external storage component <NUM>, which is implemented using a non-transitory computer readable medium such as a compact disk (CD), a digital video disc (DVD), and the like. The I/O engine <NUM> can also write information to the external storage component <NUM>, such as the results of processing by the GPU <NUM> or the CPU <NUM>.

As discussed herein, conventional processing systems do not provide a mechanism for maintaining cache coherence between powered-up caches and information that is stored in caches that are powered down in conjunction with corresponding processors entering a powered-down state. As used herein, the term "powered-down" refers to a state in which the power supplied to the processor core and related entities such as caches is reduced to below a level required to maintain the functionality of the processor core or other entity. For example, a powered-down processor core is not able to execute instructions. For another example, a powered-down cache is not supplied with sufficient power to maintain stored bit values, e.g., by maintaining the states of the transistors that are used to construct the bit storage elements of the cache.

Conventional processing systems are unable to account for invalidation of cache entries in a powered-down cache while the processor core is in the powered-down state. At least in part to address this drawback in the conventional practice, the processing system <NUM> stores information representing entries in the TLB <NUM>, <NUM> or the cache hierarchies <NUM>, <NUM> in a retention region in response to a corresponding one of the processor cores <NUM>-<NUM>, <NUM>-<NUM> initiating entry into a powered-down state. The retention region receives a retention voltage concurrently with the processor core being in the powered-down state. The processing system <NUM> monitors invalidation requests or cache probes that are issued while the processor core is in the powered-down state and the TLB <NUM>, <NUM> or the cache hierarchies <NUM>, <NUM> are then selectively repopulated with entries that were not invalidated while the processor core was in the powered-down state.

Multiple options are available for storing and restoring the entries in the TLB <NUM>, <NUM> or the cache hierarchies <NUM>, <NUM> in some embodiments of the processing system <NUM>. While the processor cores <NUM>-<NUM>, <NUM>-<NUM> are in the powered-down state, probes (or other invalidation requests) are recorded. The probes are checked against a shadow tag, a bloom filter, or other information that identifies potential hits in the cached information in the retention region that is kept at the retention voltage. Probes that miss have no further effect. Probes that hit in the cached information, probes that are potential hits as indicated by a bloom filter, or probes where the hit status cannot be determined are recorded in a probe queue or the corresponding shadow tag. In either case, an overflow bit is set if a probe hit (or potential probe hit) cannot be recorded in the probe queue or the shadow tag. Selective repopulation is performed in response to the processor cores <NUM>-<NUM>, <NUM>-<NUM> powering up based on whether the lower-level cache was kept at a retention voltage. If so, the lower-level cache retained its previous entries. Recorded probe hits (or potential hits) are replayed against the lower-level cache to invalidate corresponding entries and restore the cache. If the overflow bit is set, the entire lower-level cache is invalidated. If the lower-level cache was not kept at retention voltage, physical addresses in the shadow tags are used to prefetch (and thereby restore) the lower-level cache. Physical addresses in the shadow tags that that were hit by probes during the powered-down state are not prefetched.

<FIG> is a block diagram of a portion <NUM> of a processing system that includes a translation lookaside buffer (TLB) <NUM> and an external memory hierarchy <NUM> according to some embodiments. The portion <NUM> is used to implement some embodiments of the processing system <NUM> shown in <FIG>. For example, the external memory hierarchy <NUM> can include the memory <NUM>, an L3 cache in the cache hierarchies <NUM>, <NUM>, and the external storage component <NUM> shown in <FIG>. The TLB <NUM> is used to cache virtual-to-physical address translations that are utilized by a processor core <NUM>. Each virtual-to-physical address translation is stored in an entry <NUM> (only one entry indicated by a reference in the interest of clarity). The TLB <NUM> and the processor core <NUM> are in the same power domain <NUM>. The TLB <NUM> and the processor core <NUM> therefore receive power using the same power supply system. In some embodiments, the TLB <NUM> and the processor core <NUM> also receive a clock signal from the same clock mesh. The TLB <NUM> is therefore powered down when the processor core <NUM> is in the powered-down state.

At least a portion of the external memory hierarchy <NUM> receives power independently of the power supplied to the power domain <NUM>. The independently powered portion of the external memory hierarchy <NUM> therefore receives a retention voltage while the processor core <NUM> is in the powered-down state and is used to implement a retention region for storing information representative of the entries <NUM> in the TLB <NUM>. In the illustrated embodiment, the retention region stores a copy <NUM> of the entries <NUM> in the TLB <NUM>. However, in other embodiments, the retention region stores other information representative of the entries <NUM> such as the virtual addresses associated with the entries <NUM>. The information representative of the entries <NUM> is stored in the external memory hierarchy <NUM> in response to the processor core <NUM> initiating entry into a powered-down state. For example, the copy <NUM> of the entries <NUM> is written to the external memory hierarchy <NUM> in response to a signal indicating that the processor core <NUM> is going to power down.

Entries <NUM> in the TLB <NUM> are invalidated while the processor core <NUM> is in the powered-down state. The processing system therefore monitors invalidation requests such as TLB shoot downs that invalidate entries <NUM> in the TLB <NUM>. Some embodiments of the external memory hierarchy <NUM> implement a queue <NUM> to store the invalidation requests that are received concurrently with the processor core <NUM> being in the powered-down state. The queue <NUM> has a finite length and overflows if a number of invalidation requests received while the processor core <NUM> is in the powered-down state exceeds the number of available slots in the queue <NUM>. Some embodiments of the external memory hierarchy <NUM> store the information representative of the invalidation requests in other formats. For example, the external memory hierarchy <NUM> stores single bit that is set to a first value (e.g., <NUM>) to indicate that no invalidation requests have been received for the TLB <NUM> and a second value (e.g., <NUM>) to indicate that one or more invalidation requests have been received for the TLB <NUM>.

In response to the processor core <NUM> initiating an exit from the powered-down state, e.g., in response to the processor core <NUM> powering up, the TLB <NUM> is populated using the information representative of the entries <NUM> that is stored in the retention region of the external memory hierarchy <NUM>. For example, entries in the TLB copy <NUM> are written back to the TLB <NUM> to repopulate the entries <NUM>. The state of the TLB <NUM> is then updated on the basis of any invalidation requests that were received while the processor core <NUM> was in the powered-down state. For example, the invalidation requests in the queue <NUM> are replayed to invalidate corresponding entries <NUM> and generate the correct state of the TLB <NUM>. For another example, if the external memory hierarchy <NUM> stored virtual addresses associated with the entries <NUM>, the virtual addresses are prefetched to trigger page table walks that repopulate the entries <NUM> in the TLB <NUM>. In this example, new page table walks are done to populate the TLB <NUM> and consequently no entries in the TLB <NUM> need to be invalidated to keep the TLB <NUM> coherent with the rest of the system. For yet another example, if the external memory hierarchy <NUM> stored a single bit indicating whether any invalidation requests were received, all of the entries <NUM> in the TLB <NUM> are invalidated if the bit indicates that one or more invalidation requests were received.

In some embodiments, instead of repopulating and then invalidating, the entries <NUM> of the TLB <NUM> are restored by conditionally repopulating the entries depending on the invalidation requests that were received while the processor core <NUM> was in the powered-down state. For example, only the entries in the TLB copy <NUM> that were not invalidated (as indicated by information in the queue <NUM>) are written back into the TLB <NUM> in response to the processor core <NUM> powering up. For another example, if the external memory hierarchy <NUM> stores a single bit that is set to a value that indicates that one or more invalidation requests were received, the TLB copy <NUM> is not written back to the TLB <NUM>, which is invalidated based on the bit value.

<FIG> is a flow diagram of a method <NUM> of storing information representative of entries in a TLB in a retention region prior to powering down a processor core associated with the TLB according to some embodiments. The method <NUM> is implemented in some embodiments of the processing system <NUM> shown in <FIG> and the portion <NUM> of the processing system shown in <FIG>.

At block <NUM>, the processing system initiates power down of the processor core. For example, the processor core initiates entry into a powered-down state in response to an absence of instructions being dispatched to the processor core for execution or a prediction that no instructions will be dispatched to the processor core for execution during a subsequent time interval that exceeds a threshold for powering down.

At block <NUM>, information representative of the entries in the TLB are stored to an external memory that implements a retention region that retains power while the processor core is in the powered-down state. Some embodiments of the external memory are implemented using an L3 cache, a DRAM, and external storage such as a disk drive. The information includes copies of the entries in the TLB or virtual addresses for the entries in the TLB.

At block <NUM>, the processor core is powered down. Powering down of the processor core occurs after the information representative of the entries in the TLB has been stored to the external memory to prevent loss of this information when the TLB loses power.

At block <NUM>, information representative of invalidation requests that are received for the TLB are stored in the retention region. For example, the retention region can implement a queue that stores the invalidation requests while the processor core is in the powered-down state. For another example, the retention region can implement a bit that is set to a first value (e.g., <NUM>) to indicate that no invalidation requests have been received for the TLB and a second value (e.g., <NUM>) to indicate that one or more invalidation requests have been received for the TLB.

<FIG> is a flow diagram of a method <NUM> of repopulating entries in a TLB using information stored in a retention region prior to powering down a processor core associated with the TLB according to some embodiments. The method <NUM> is implemented in some embodiments of the processing system <NUM> shown in <FIG> and the portion <NUM> of the processing system shown in <FIG>.

At block <NUM>, the processing system initiates powering up of the processor core. For example, exit from the powered-down state is initiated in response to a dispatcher in the processing system dispatching an instruction for execution on the processor core.

At decision block <NUM>, the processing system determines whether a queue that stores invalidation requests has overflowed in response to receiving a number of invalidation requests that exceeds the number of slots available in the queue. If so, the method <NUM> flows to block <NUM> and all the entries in the TLB are invalidated because the queue does not hold all the information that is necessary to reconstruct the state of the TLB. If the queue has not overflowed, the method <NUM> flows to block <NUM>.

At block <NUM>, the TLB is repopulated using information representative of the entries in the TLB. For example, copies of the entries are written from the retention region into the TLB. For another example, addresses of the entries that are stored in the retention region are prefetched to trigger a page table walk that populates the entries in the TLB.

At block <NUM>, the state of the TLB is modified based on invalidation requests that were received while the processor core was in the powered-down state. For example, invalidation requests stored in the queue are replayed to invalidate entries in the TLB. For another example, if the retention region only stores a single bit to indicate whether any invalidation requests were received while the processor core was in the powered-down state, all of the entries in the TLB are invalidated if the value of the bit indicates that one or more invalidation requests were received.

<FIG> is a block diagram of a cache hierarchy <NUM> according to some embodiments. The cache hierarchy <NUM> is used to implement some embodiments of the cache hierarchy <NUM> in the GPU <NUM> and some embodiments of the cache hierarchy <NUM> in the CPU <NUM> shown in <FIG>. The cache hierarchy <NUM> caches information such as instructions or data for processor cores <NUM>, <NUM>, <NUM>, <NUM>, which are collectively referred to herein as "the processor cores <NUM>-<NUM>. " The processor cores <NUM>-<NUM> are used to implement some embodiments of the processor cores <NUM>-<NUM>, <NUM>-<NUM> shown in <FIG>.

The cache hierarchy <NUM> includes three levels of caches: a first level including L1 caches <NUM>, <NUM>, <NUM>, <NUM> (collectively referred to herein as "the L1 caches <NUM>-<NUM>"), a second level including L2 caches <NUM>, <NUM>, <NUM>, <NUM> (collectively referred to herein as "the L2 caches <NUM>-<NUM>"), and a third level including an L3 cache <NUM>. However, some embodiments of the cache hierarchy <NUM> include more or fewer levels of caches. Although the L1 caches <NUM>-<NUM> are depicted as separate hardware structures that are interconnected to the corresponding processor cores <NUM>-<NUM>, some embodiments of the L1 caches <NUM>-<NUM> are incorporated into the hardware structures that implement the processor cores <NUM>-<NUM>.

The L1 caches <NUM>-<NUM> are used to cache information for access by the corresponding processor cores <NUM>-<NUM>. For example, the L1 cache <NUM> is configured to cache information for the processor core <NUM>. The processor core <NUM> therefore issues memory access requests to the L1 cache <NUM>. The requested information is returned if the memory access request hits in the L1 cache <NUM>. The L1 cache <NUM> forwards the memory access request to the next higher cache level (e.g., the L2 cache <NUM>) if the memory access request misses in the L1 cache <NUM>. The information cached in the L1 cache <NUM> is not typically accessible by the other processor cores <NUM>-<NUM>.

The L2 caches <NUM>-<NUM> are also configured to cache information for the processor cores <NUM>-<NUM>. In the illustrated embodiment, the L2 caches <NUM>-<NUM> are inclusive of the corresponding L1 caches <NUM>-<NUM>. For example, the L2 cache <NUM> caches information that includes the information cached in the L1 cache <NUM>. However, the L2 caches <NUM>-<NUM> are typically larger than the L1 caches <NUM>-<NUM> and so the L2 caches <NUM>-<NUM> also store other information that is not stored in the corresponding L1 caches <NUM>-<NUM>. As discussed above, if one of the processor cores <NUM>-<NUM> issues a memory access request that misses in the corresponding L1 cache <NUM>-<NUM>, the memory access request is forwarded to the corresponding L2 cache <NUM>-<NUM>. The requested information is returned to the requesting processor core <NUM>-<NUM> if the memory access request hits in the L2 cache <NUM>-<NUM>. The L2 caches <NUM>-<NUM> forward memory access requests to the next higher-level of the cache (e.g., the L3 cache <NUM>) if the memory access request misses in the L2 cache <NUM>-<NUM>. In some embodiments, L2 caches <NUM>-<NUM> are shared between multiple L1 caches <NUM>-<NUM> and corresponding processor cores <NUM>-<NUM>.

The L3 cache <NUM> is configured as a global cache for the processor cores <NUM>-<NUM>. Memory access requests from the processor cores <NUM>-<NUM> that miss in the L2 caches <NUM>, <NUM> are forwarded to the L3 cache <NUM>. The requested information is returned to the requesting processor core <NUM>-<NUM> if the memory access request hits in the L3 cache <NUM>. The L3 cache <NUM> forwards the memory access request to a memory system such as a DRAM <NUM> if the memory access requests misses in the L3 cache <NUM>.

In the illustrated embodiment, the processor cores <NUM>-<NUM>, the L1 caches <NUM>-<NUM>, and the L2 caches <NUM>-<NUM> are implemented in the power domains <NUM>, <NUM>, <NUM>, <NUM>, which are collectively referred to herein as "the power domains <NUM>-<NUM>. " Power is independently supplied to the power domains <NUM>-<NUM> and so the entities in the power domains <NUM>-<NUM> are independently or separately powered up or powered down. For example, the processor core <NUM> can be placed in the powered-down state concurrently with the processor cores <NUM>-<NUM> remaining in the powered-up state. However, removing power from a processor core <NUM>-<NUM> also removes power from the corresponding L1 caches <NUM>-<NUM> and L2 caches <NUM>-<NUM>, which therefore lose any stored information when the corresponding processor core <NUM>-<NUM> enters the powered-down state.

Information representative of the entries in the L1 caches <NUM>-<NUM> or L2 caches <NUM>-<NUM> is stored in a retention region in response to the corresponding processor core <NUM>-<NUM> initiating entry into the powered-down state. The retention region continues to receive a retention voltage during the powered-down state of one or more of the processor cores <NUM>-<NUM>. The retention region can be implemented in the DRAM <NUM> or the L3 cache <NUM>. The retention region can also be implemented in the L1 caches <NUM>-<NUM> or L2 caches <NUM>-<NUM> if a retention voltage is supplied while the processor core <NUM>-<NUM> is in the powered-down state. The information representative of the entries can include copies of the entries or physical addresses of the information stored in the entries. For example, the information representative of the entries in the L2 cache <NUM> is rinsed by writing modified (or dirty) entries from the L2 cache <NUM> to a retention region implemented in the L3 cache <NUM>. For another example, the information representative of the entries in the L2 cache <NUM> is flushed by writing all of the entries in the L2 cache <NUM> to the retention region implemented in the L3 cache <NUM>.

The retention region also stores information representing invalidating signals such as cache probes that are received while one or more of the processor cores <NUM>-<NUM> are in the powered-down state. In some embodiments, the information is stored in shadow tags associated with entries in a cache. For example, the L3 cache <NUM> stores shadow tags for entries in the L2 caches <NUM>-<NUM>. The shadow tags include information indicating whether the corresponding entry includes clean data or whether the entry is for a cache that has been powered down in conjunction with one of the processor cores <NUM>-<NUM> entering a powered-down state. The shadow tags also include one or more bits indicating whether the entry is valid, e.g., whether a cache probe has been received for the corresponding entry. For another example, the retention region implements a bit that is set to a first value (e.g., <NUM>) to indicate that no cache probes have been received for the entry and a second value (e.g., <NUM>) to indicate that one or more cache probes have been received for the entry. Some embodiments of the shadow tags include a physical address of the information stored in the entry. Some embodiments of the retention region implement a queue to hold cache probes for subsequent playback. The queue is implemented in addition to the cache probe bits in the shadow tags or instead of implementing the cache probe bits.

The information in the retention region is used to restore the caches in response to the corresponding processor core <NUM>-<NUM> initiating exit from the powered-down state. For example, copies of entries in the L2 cache <NUM> are written back from the L3 cache <NUM> in response to the processor core <NUM> initiating exit from the powered-down state. For another example, values of the entries in the L2 cache <NUM> are prefetched using the physical addresses in the shadow tags that are stored in the L3 cache <NUM>. The information that represents the invalidating signals is used to modify the cache entries. For example, values of bits in the shadow tags for the entries in the L2 cache <NUM> are used to invalidate the entries if the bit values indicate that a cache probe was received for the entry. Physical addresses of invalidated entries in the shadow tags are not prefetched. For another example, the cache probes are played back from the queue to modify the entries in the L2 cache <NUM>.

<FIG> is a block diagram of a portion <NUM> of a cache hierarchy including an L2 cache <NUM> and an L3 cache <NUM> according to some embodiments. The L2 cache <NUM> caches information for a processor core such as one of the processor cores <NUM>-<NUM> shown in <FIG>. The L3 cache <NUM> is used to implement a retention region for the L2 cache <NUM> because the L3 cache <NUM> continues to receive power while the processor core associated with the L2 cache <NUM> is in the powered-down state. In some embodiments, copies of the entries in the L2 cache <NUM> are written back to the L3 cache <NUM> by rinsing or flushing the L2 cache <NUM>.

The retention region in the L3 cache <NUM> stores shadow tags <NUM> associated with the L2 cache <NUM>. The shadow tags <NUM> include physical addresses <NUM> of the values that are cached in the entries of the L2 cache <NUM>. Bit values <NUM> indicate whether the entry includes unmodified (clean) data (a value of <NUM> indicates clean data), bit values <NUM> indicate whether the entry is associated with a cache that is in the powered-down state (a value of <NUM> indicates association with a powered-down cache), and bit values <NUM> indicate whether the entry is valid (a value of <NUM> indicates invalidity). The bit values <NUM> are modified in response to a probe hit to the corresponding entry, e.g., a bit value <NUM> is set to a value of <NUM> to indicate that the entry has been invalidated by a probe hit. The shadow tags <NUM> shown in <FIG> indicate that all of the entries include clean data associated with a cache that is in the powered-down state and a cache probe has invalidated the cache entry associated with the physical address P_ADDR_2.

In response to the processor core associated with the L2 cache <NUM> initiating exit from the powered-down state, the entries in the L2 cache <NUM> are repopulated using information stored in the L3 cache <NUM>. For example, the physical addresses of the valid entries stored in the shadow tags <NUM> are prefetched into the entries of the L2 cache <NUM>. For another example, if the L3 cache <NUM> stores copies of the values stored in the entries of the L2 cache <NUM>, the values are written back to the L2 cache <NUM>. The bit value <NUM> is then used to invalidate entries that received cache probes while the processor core was in the powered-down state.

Some embodiments of the retention region include a probe queue <NUM> that stores information indicating the probes that are received while the processor core is in the powered-down state. The probes stored in the probe queue <NUM> are sent to the L2 cache <NUM> in response to the processor core powering up after the L2 cache <NUM> has been repopulated using the information representative of the cache entries that is stored in the L3 cache <NUM>. Replaying the probes stored in the probe queue <NUM> invalidates the entries indicated by the probes to place the L2 cache <NUM> in the appropriate state. In the case of an overflow of the probe queue <NUM>, the processor core is powered-up to service the probes in the probe queue <NUM> or the entire L2 cache <NUM> is invalidated when the processor core powers up.

<FIG> is a flow diagram of a method <NUM> of storing information representative of entries in a lower-level cache in a retention region prior to powering down a processor core associated with the lower-level cache according to some embodiments. The method <NUM> is implemented in some embodiments of the processing system <NUM> shown in <FIG>, the cache hierarchy <NUM> shown in <FIG>, and the portion <NUM> of the processing system shown in <FIG>.

At block <NUM>, the processor core is powered up and in a normal operating mode. In the illustrated embodiment, shadow tags in a higher-level cache are used as a probe filter for cache lines in a lower-level cache used by the processor core. The probe filter prevents probes for cache lines that are not stored in the lower-level cache associated with the processor core from being sent to the processor core. The shadow tags are therefore maintained while the processor core is operating in the powered-up mode.

At block <NUM>, modified or dirty entries in the lower-level cache are written back to a higher-level cache that implements a retention region that receives a retention voltage while the processor core is in the powered-down state. For example, dirty entries in an L2 cache can be written back to an L3 cache. Shadow tags in the L3 cache associated with entries in the L2 cache are also updated. In other examples, information representing entries in other caches (such as L1 caches) can also be stored in a retention region. Moreover, the retention region could be implemented in other entities including an external memory such as a DRAM, other caches, or the lower-level cache if a retention voltage is provided to the lower-level cache multiprocessor core is in the powered-down state.

At block <NUM>, the processor core is powered down. Powering down of the processor core occurs after the information representative of the entries in the lower-level cache has been stored to the external memory to prevent loss of this information when the lower-level cache loses power.

At block <NUM>, shadow tags in the retention region are modified in response to cache probes that are received while the processor core is in the powered-down state. For example, a bit in a shadow tag of an entry that indicates whether the entry is valid is set to a value that indicates that the entry is invalid in response to receiving a cache probe of the entry. For another example, the cache probe is added to a probe queue that it is implemented in the retention region.

<FIG> is a flow diagram of a method <NUM> of restoring entries in a lower-level cache using information stored in a retention region in response to a processor core initiating exit from a powered-down state according to some embodiments. The method <NUM> is implemented in some embodiments of the processing system <NUM> shown in <FIG>, the cache hierarchy <NUM> shown in <FIG>, and the portion <NUM> of the processing system shown in <FIG>.

At block <NUM>, a lower-level cache associated with the processor core is restored. In some embodiments, the lower-level cache is repopulated using physical addresses stored in shadow tags in a retention region. For example, an L2 cache is repopulated by prefetching physical addresses of valid entries in shadow tags of an L3 cache. In this case, there is no need to subsequently modify the information in the L2 cache because only valid entries are prefetched and invalid entries in the shadow tags of the L3 cache are not prefetched into the L2 cache. For another example, an L2 cache is repopulated by writing copies of entries from the L3 cache into the L2 cache. Some embodiments of the lower-level cache are provided with a retention voltage while the processor core is in the powered-down mode. In that case, the entries in the lower-level cache do not need to be repopulated in order to restore the lower-level cache. For example, if the storage elements of the L2 cache receive a retention voltage while the core is powered down, the L2 cache entries are retained in situ in the L2 cache and the L2 cache is restored based on the invalidation information.

In embodiments of the retention region that implement a probe queue, the information that is provided to the lower-level cache in response to the processor core initiating an exit from the powered-down state is modified (at block <NUM>) based on the cache probes stored in the probe queue. For example, the cache probes stored in the probe queue are replayed to invalidate corresponding entries in the repopulated L2 cache. The block <NUM> is therefore optional (this is as indicated by the dotted lines) and is not performed in some embodiments of the method <NUM>.

At block <NUM>, the processor core is powered up and begins executing instructions on the basis of the repopulated lower-level cache.

In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing system described above with reference to <FIG>. Electronic design automation (EDA) and computer aided design (CAD) software tools may be used in the design and fabrication of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices so as to perform at least a portion of a process to design or adapt a manufacturing system to fabricate the circuitry. This code can include instructions, data, or a combination of instructions and data. The software instructions representing a design tool or fabrication tool typically are stored in a computer readable storage medium accessible to the computing system. Likewise, the code representative of one or more phases of the design or fabrication of an IC device may be stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

A computer readable storage medium may include any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and/or data to the computer system.

The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium.

Claim 1:
A method comprising:
in response to powering down a processor core (<NUM>) associated with a first cache (<NUM>), storing information representing a set of entries (<NUM>) of the first cache in a retention region (<NUM>) of a processing system that receives a retention voltage while the processor core is in a powered-down state;
storing, in the retention region, information indicating at least one entry of the set of entries of the first cache (<NUM>) has been invalidated while the processor core is in a powered-down state;
implementing, at the retention region, a probe queue to store cache probes that are received while the processor core is powered down; and
in response to the processor core initiating exit from the powered-down state, selectively repopulating the first cache with entries that were not invalidated while the processor core (<NUM>) was in the powered-down state using the stored information representing the set of entries, the cache probes stored in the probe queue, and the stored information indicating the at least one invalidated entry.