Patent Description:
US patent <CIT> relates to a memory system that includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

US patent <CIT> relates to a system and method that are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the.

Us patent <CIT> discloses a DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:.

Embodiments of memory devices, controllers, associated methods and integrated circuits are disclosed herein. One embodiment of a memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh rates. Refresh logic refreshes each segment in accordance with the corresponding per-segment value. By non-uniformly varying the per-segment refresh rates based on acceptable error rates associated with the data stored in each segment, significant power savings attributable to refresh operations may be realized.

Specific embodiments described herein provide apparatus and methods that vary refresh rates on a per-segment basis, and in accordance with pre-specified error criteria associated with data stored in each segment. Refresh rates may thus be increased or decreased to correspondingly refresh storage cells in a manner that tightens or loosens read data errors attributable to refresh operations.

With reference to <FIG>, a memory system, generally designated <NUM>, is shown that includes a memory controller <NUM> coupled to a memory device <NUM> via bus <NUM>. For one embodiment, the memory controller is a DRAM controller, with the memory device realized as a dynamic random access (DRAM) memory device. In some embodiments, the memory controller and memory device may be embodied as integrated circuits, or chips. Other embodiments may employ the memory controller as a circuit in a general purpose processor. Specific embodiments for the DRAM memory controller and memory device may be compliant with various DRAM standards, including double data rate (DDR) variants, low power (LPDDR) versions, and graphics (GDDR) types. Other embodiments may include multi-chip modules that, for example, employ stacked memory die, or stacked packages. Such embodiments may be used with memory modules. Additional embodiments may stack memory die and logic die together in a common package, or in separate packages stacked upon each other.

Further referring to <FIG>, the memory controller <NUM> includes a controller interface <NUM> for transferring data, command and control signals between the memory controller and the memory device <NUM>. Command generation circuitry <NUM> generates read/write and mode register write (MRW) commands for transmission to the memory device. For one embodiment, explained below, the command generation circuitry <NUM> generates MRW commands for storing values associated with per-segment refresh rates into a mode register on the memory device. A physical memory allocator <NUM> determines bank and segment addresses for physical memory corresponding to memory requested by a Host/Processor <NUM>. The memory controller may also include auto-refresh logic <NUM> to generate refresh commands that are externally applied to the DRAM memory device during auto-refresh operations. Auto-refresh occurs while the memory system is in an active state to support an actively operating electronic device.

With continued reference to <FIG>, the Host/Processor <NUM> may take the form of a general purpose processor that responds to instructions generated by Operating System (OS) <NUM>. The OS, in turn, allocates logical memory in response to memory requested by a given Application <NUM>, and for one embodiment, generates tags for allocated memory as more fully described below.

Further referring to <FIG>, the memory device <NUM> includes an array of volatile storage cells that are, in one embodiment, organized into banks <NUM> and <NUM>. Each bank, in turn, is organized into multiple addressable segments <NUM>. For one embodiment, each memory device includes eight banks, with each bank having eight segments. The memory device may include any memory integrated circuit (IC) chip having volatile storage cells that maintain a given charge state through periodic refresh operations.

With continued reference to <FIG>, to carry out refresh operations on a per-segment basis, one embodiment of the memory device incorporates refresh logic <NUM>. Refresh logic <NUM> controls the internal DRAM operation for self-refresh, auto refresh or both. In one embodiment, refresh logic <NUM> contains a refresh counter that keeps track of the next address to be refreshed. Mode register circuitry <NUM> provides register storage for per-segment refresh rate values based on the acceptable data error thresholds or BERs generated by the Application <NUM> and OS <NUM>. The refresh logic <NUM> accesses the register values when carrying out per-segment non-uniform self-refresh operations.

Further referring to <FIG>, the memory device <NUM> includes a memory interface <NUM> that receives data, command and control signals from the memory controller <NUM>. As noted above, for one embodiment, the controller interface <NUM> on the memory controller transfers each per-segment refresh rate value for a given segment to the memory interface <NUM> with an accompanying mode register write (MRW) command. In response to the MRW commands, the per-segment refresh rate values are loaded and stored in the mode register circuitry <NUM>.

For some embodiments, the memory device <NUM> may employ temperature detection circuitry <NUM> such as a temperature sensor to operate consistent with Temperature Compensated Self-Refresh (TCSR) techniques to assist in the per-segment non-uniform self-refresh operations described herein. Other embodiments may employ the temperature detection circuitry on the memory controller <NUM>. For one embodiment, a global refresh rate for the memory device segments may be established via the TCSR methodology, with per-segment non-uniform refresh rate multipliers stored in the mode register circuitry <NUM> as the per-segment refresh rate values selectively applied to the global refresh rate for finer refresh rate control.

In operation, "per-segment non-uniform refresh" operations are managed by the memory system of <FIG>, in both self-refresh and auto-refresh situations, although most of the discussion herein focuses on embodiments that vary refresh rates on a per-segment basis during self-refresh operations. Generally, auto-refresh takes place during active operation of an electronic device, while self-refresh takes place while the electronic device is in a "sleep" or inactive mode to reduce power dissipation. Self-refresh is timed by the DRAM itself independent of the memory controller using, for example, a ring oscillator and counter to generate row addresses on chip. Auto-refresh is triggered on a per command basis by the controller where each auto-refresh command would indicate to the DRAM to refresh one or more rows.

An electronic device that utilizes the memory system of <FIG> generally runs one or more Applications for a user. Prior to actual operation, a pre-configuration procedure is carried out to initialize and optimize memory system settings for the Application. A given Application may need to load different types of data into the memory device <NUM>, such as program code and/or bulk data utilized by the Application. In some situations, it may be desirable to have a very low error threshold, such as a bit-error-rate (BER), associated with the program code data to ensure proper program execution. Bulk data such as image or audio data, on the other hand, may in some occasions be managed with higher error rates while still enabling acceptable use of the Application.

Referring now to <FIG>, in one embodiment, to manage classifying different types of data with different acceptable BER parameters, the OS <NUM> and Application <NUM> cooperate to classify requested memory during memory allocation according to an acceptable data error threshold, such as a BER, at <NUM>, and tag the requested memory according to the classification, at <NUM>. The memory controller <NUM> receives the allocation information from the Host/Processor <NUM>, and generates physical memory assignments in terms of banks and segment addresses, at <NUM>. The memory controller also writes mode register bit information for non-uniform refresh operations in the memory device mode register, at <NUM>. The memory controller also issues auto-refresh commands during operation at <NUM>. In one embodiment, the rate of the memory controller issuing auto-refresh commands is the same as when used without non-uniform refresh (NUR), in another embodiment the memory controller uses a different rate of issuing auto refresh commands when using NUR.

<FIG> illustrates an exemplary mode register decoder diagram for mode register bits that are engaged in per-segment refresh operations in accordance with one embodiment. The diagram is organized into rows that represent eight segments, labeled S0 - S7, and columns that represent eight banks, labeled B0 - B7. Each bank and segment includes a set of mode bits to indicate a refresh parameter value, such as an absolute refresh rate, or a modifier value to modify a global refresh rate. For one embodiment, the bank/segment bits are set according to the following code:.

Where both bank and segment bits show a code specifying a refresh rate other than the nominal rate, the bank bit code supercedes the segment code. While a two-bit coding is shown and described herein for one specific embodiment, additional bits may be provided to provide even finer granularity. For example, additional bits may specify additional refresh rates/modifiers and/or specify individual segments.

Further referring to <FIG>, as an example, a first portion of the diagram, at <NUM>, shows a segment code of "<NUM>" for the fifth segment S4. A nominal code of "<NUM>" for bank B0, at <NUM>, specifies a refresh rate of <NUM> for segments S0-S3, and S5-S7 of bank B0, while the refresh rate for segment S4, at <NUM>, is specified as <NUM>. The code for bank B1, <NUM>, supercedes the segment S4 code of <NUM>, and thus specifies a refresh rate of <NUM> (shown at <NUM>) for all eight of the segments of bank B1. While <FIG> shows a decoder chart that specifies absolute settings with reference to a nominal value, the codes may alternatively represent per-segment multiplier factors to apply to a global refresh setting, such as that associated with a temperature compensated self-refresh scheme (TCSR).

Generally, TCSR provides a way to reduce power consumption while the memory device is operating under self-refresh conditions. The ambient temperature of the memory device is detected by the temperature detection circuitry <NUM>, with global refresh rate changes carried out in response to the detected temperature. The refresh rate increase/decrease generally compensates for increased/decreased leakage rates in the volatile storage cells at different temperatures. In such an embodiment, the temperature detection circuitry <NUM> detects an operating temperature of the memory device <NUM>, generates corresponding temperature information, and provides the temperature information to the refresh logic <NUM>. The refresh logic may then apply an appropriate global refresh rate setting (stored in the mode register circuitry <NUM>) based on the temperature, and apply per-segment multipliers for non-uniform refresh rates between various segments based on the non-uniform bits stored in the mode register circuitry.

In one embodiment, the memory controller issues auto-refresh commands at the same rate as when NUR is not used. The refresh logic on the DRAM periodically skips execution of a refresh when the refresh counter points to a row in a segment with a longer refresh time assigned by the NUR bits in the mode register. As an example, when the assigned refresh rate for a segment is <NUM> while the memory controller issues auto-refresh commands every <NUM>, the refresh logic skips every second refresh of that segment.

At the memory controller, an alternative form of per-segment refresh may be employed by the auto-refresh controller for auto-refresh operations. As noted above, auto-refresh generally occurs during active operation of an electronic device. With knowledge of acceptable bit error rates for differently allocated areas of memory, variable per-segment refresh rates may be carried out by the auto-refresh controller on the memory controller by, for example, skipping appropriate segments when an external global refresh command is issued.

The memory system, device, and method described above provides finer-granularity per-segment non-uniform refresh that allows for more efficient power savings achievable by the memory system. The embodiments described herein lend themselves well to mobile device applications where power efficiency is a key concern.

When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

Claim 1:
An integrated circuit IC memory device (<NUM>) comprising:
an array of storage cells configured into multiple banks (<NUM>, <NUM>), each bank including multiple segments (<NUM>);
register storage to store per-segment values representing per-segment refresh rates; and and refresh logic (<NUM>) to refresh each segment (<NUM>) in accordance with the corresponding per-segment value,
the integrated circuit being characterized in that
the refresh rates are determined based on error thresholds associated with the type of data loaded into the memory device (<NUM>).