Patent Description:
Neuromorphic networks are widely used in pattern recognition and classification, with many potential applications from fingerprint, iris, and face recognition to target acquisition, etc. The parameters (e.g. among them, 'synaptic weights') of the neuromorphic networks may be adaptively trained on a set of patterns during a learning process, following which the neuromorphic network is able to recognize or classify patterns of the same kind.

Neurons and synapses are two basic computational units in the brain.

A neuron can integrate inputs coming from other neurons, in some cases with further inputs, for example from sensory receptors, and generates output signals known as "action potentials" or "spikes", when the integrated input exceeds a threshold value. In the following functions or operations that are performed by a neuron are denoted as neuron functionality.

Synapses change their connection strength because of neuronal activity, and updating the weight of this connection is referred as the training of the network. Synapses typically outnumber neurons by a significant factor (approximately <NUM>,<NUM> in the case of the human brain). A key challenge in neuromorphic computation technology is the development of compact devices that emulate the plasticity of biological synapses. Functions or operations that are performed by a synapse are denoted as synapse functionality.

An example of an integrated optical circuit is <NPL>. It discloses the development of a hardware synapse, implemented entirely in the optical domain via a photonic integrated-circuit approach. The synapse uses phase-change materials combined with integrated silicon nitride waveguides.

According to a first aspect, the invention is embodied as an integrated optical circuit for an optical neural network. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal as a function of the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. The integrated optical circuit comprises a reference waveguide configured to carry an optical reference signal and a plurality of input waveguides configured to receive the plurality of phase-encoded optical input signals. Phase differences between the optical reference signal and the optical input signals represent the respective phase-encoded input signal. The integrated optical circuit further comprises an output waveguide and an optical interferometer system. The optical interferometer system is configured to superimpose the plurality of optical input signals and the optical reference signal into a plurality of first interference signals. The optical interferometer system is further configured to superimpose the plurality of first interference signals into a second interference signal. The integrated optical circuit further comprises a phase-shifting device configured to provide the phase-encoded optical output signal in dependence on the second interference signal.

Such an embodied optical circuit uses the phase to encode information in the optical domain.

According to embodiments of the first aspect, the circuit emulates a neuron functionality when producing the phase encoded output signal depending on the sum of phases for the plurality of phase-encoded optical input signals.

This offers advantages in terms of signal restoration. In particular, the phase is decoupled from propagation losses and remains constant. Furthermore, a reduced amplitude of optical mode decays due to propagation losses can be amplified again to restore the signal.

According to such an embodiment, the phase-encoded optical output signal comprises a phase shift relative to the reference signal which depends on the sum of the input states of the optical input signals within a non-vanishing time window. The dependence may be in particular non-linear. The second interference signal corresponds to a summation signal.

With such a summation emulated by means of the interference system and a subsequent non-linear function emulated by the phase-shifting device, a neuron function may be efficiently approximated/emulated in the optical domain.

The reference signal is fed in parallel to the interferometer system and to the phase shifting device. The interferometer system converts the reference signal and the plurality of phase-encoded optical input signals into a second interference signal having an amplitude that depends on the phase shift between the reference signal and the plurality of phase-encoded input signals. The amplitude of the second interference signal is then converted into the phase encoded output signal.

According to a further embodiment, the integrated optical circuit comprises a plurality of first interferometers. Each of the first interferometers is configured to receive the optical reference signal and one of the plurality of optical input signals and to superimpose the optical reference signal and the respective optical input signal into the plurality of first interference signals. A second interferometer is configured to receive the plurality of first interference signals from the plurality of first interferometers and to superimpose the plurality of first interference signals into the second interference signal.

Such a two-stage approach may provide an efficient and reliable implementation of a summation function of the neuron circuit.

According to embodiments, the optical interferometer system comprises one or more single-mode interferometers. Such multi-mode interferometers provide the advantage of power efficiency.

According to embodiments, the optical interferometer system comprises one or more multi-mode interferometers. Such multi-mode interferometers provide the advantage of an easier design.

According to an embodiment, the phase-encoded optical output signal comprises a phase shift within a predefined range relative to the optical reference signal. Preferably the predefined range is a range between <NUM>° and <NUM>°. This ensures an unambiguous coding of the phase encoded output signal.

According to a further embodiment, the phase-shifting device comprises a non-linear optical material with a non-linear power-to-refractive-index conversion.

Nonlinear optical materials may be defined as materials in which the dielectric polarization P responds nonlinearly to the electric field E of incident light. The nonlinearity depends on the intensity/amplitude of the light. According to embodiments, the nonlinear material may be e.g. BaTiO3, LiNbO3, ferroelectric perovskites, polymers with non-linear optical properties, chalcogenides or III-V compound semiconductors.

According to a further embodiment, the phase shifting device comprises a phase change material. Such a phase change material changes its material state in dependence on the incident optical power. According to a preferred embodiment, materials with metal-insulator transitions may be used. Such materials may be in particular correlated oxides materials, in particular Vanadium Dioxide (VO<NUM>). The transition temperature between the insulating phase state and the metallic phase state of VO<NUM> is approximately in a range between <NUM> and <NUM> which makes VO<NUM> a preferred choice. At room temperature, VO<NUM> is still well below the transition temperature and hence in the insulating state. And with some heating as a result of an incident optical power, VO<NUM> can efficiently be brought above the transition temperature, thereby transition it to the metallic state.

According to other embodiments, the phase change material may be V<NUM>O<NUM>, V<NUM>O<NUM>, V<NUM>O<NUM>, V<NUM>O<NUM>, V<NUM>O<NUM>, VO, V<NUM>O<NUM>, NbO<NUM>, Ti<NUM>O<NUM>, LaCoO<NUM>, Ti<NUM>O<NUM>, SmNiO<NUM>, NdNiO<NUM>, PrNiO<NUM>, Fe<NUM>O<NUM> or chalcogenides such as GeTe or GeSbTe.

According to a further embodiment, the phase shifting device is a plasma dispersion modulator. The plasma dispersion effect is related to the density of free carriers in a semiconductor, which changes both the real and imaginary parts of the refractive index. This may be described by the Drude-Lorenz equations that relate the concentration of electrons and holes to the absorption coefficient and refractive index.

According to a further embodiment, the phase shifting device comprises an optical cavity comprising a non-linear optical material. A gate waveguide is coupled to the optical cavity and configured to guide the second interference signal to the optical cavity. The gate waveguide is further configured to change the refractive index of the non-linear optical material in dependence on the optical power of the second interference signal.

The optical cavity is further configured to receive the optical reference signal, to induce a phase shift in the optical reference signal and to provide the phase-encoded optical output signal.

According to an embodiment, the optical cavity may be formed by a waveguide. Such an embodied optical cavity provides refractive index changes based on the optical power of the optical signal in the gate waveguide.

Another aspect of the invention relates to an optical neural network comprising a plurality of integrated optical circuits according to neurons as claimed in any of the claims <NUM> to <NUM>. The optical neural network comprises a plurality of further integrated optical circuits as synapse circuits. The synapse circuits are configured to process a phase-encoded optical input signal and to provide a phase-encoded optical output signal. The phase-encoded optical output signal emulates a synapse functionality with respect to the phase-encoded optical input signal.

With such an embodied neural network the neuron as well as the synapse functionalities can be implemented in the optical domain. Another aspect of the invention relates to a method for emulating a neuron functionality. The method comprises steps of providing an integrated optical circuit and processing, by the integrated optical circuit, a phase-encoded optical input signal. The method comprises further steps of emulating, by the integrated optical circuit, a neuron functionality with respect to the phase-encoded optical input signal and providing, by the integrated optical circuit, a phase-encoded optical output signal. The method comprises steps of carrying, by a reference waveguide, an optical reference signal and receiving, by a plurality of input waveguides, the plurality of phase-encoded optical input signals. The method comprises further steps of superimposing, by an optical interferometer system, the plurality of optical input signals and the optical reference signal into a plurality of first interference signals and superimposing, by the optical interferometer system, the plurality of first interference signals into a second interference signal. A further step comprises providing, by a phase-shifting device, the phase-encoded optical output signal in dependence on the second interference signal.

Embodiments of the invention will be described in more detail below with reference to the accompanying drawings.

<FIG> shows an optical neural network <NUM> according to an embodiment of the invention. The optical neural network <NUM> comprises an input layer <NUM>, a hidden layer <NUM> and an output layer <NUM>. The input layer <NUM> comprises a plurality of input nodes <NUM>, which are configured to receive phase encoded optical input signals and to provide the optical input signals to the hidden layer <NUM>. The output layer <NUM> comprises a plurality of output nodes <NUM> which are configured to provide phase encoded optical output signals.

The hidden layer <NUM> comprises a plurality of integrated optical circuits. More particularly, the hidden layer <NUM> comprises integrated optical circuits <NUM> and integrated optical circuits <NUM>. The integrated optical circuits <NUM> are embodied as neurons and may be in the following also denoted as neuron circuits <NUM>. The integrated optical circuits <NUM> are embodied as synapses and may be in the following also denoted as synapse circuits <NUM>.

The integrated optical circuits <NUM> are configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals.

The integrated optical circuits <NUM> are configured to process a phase-encoded optical input signal and to provide a phase-encoded optical output signal. The phase-encoded optical output signal emulates a synapse functionality with respect to the phase-encoded optical input signal.

Accordingly, the optical neural network <NUM> operates in the phase domain.

According to embodiments, weights of the synapse circuits <NUM> of the optical neural network <NUM> may be trained with a training process. The adjustment of the weights of the optical synapse circuits <NUM> may be done in software or hardware according to embodiments.

<FIG> shows a schematic diagram of an information encoding scheme according to an embodiment of the invention. The x-axis denotes the phase of the phase-encoded optical input signals and the phase of the phase-encoded optical output signals of the neuron circuits <NUM> and of the synapse circuits <NUM>. The y-axis denotes a corresponding information value. The phase of the phase-encoded optical input and output signals operates in a predefined range between <NUM>° and <NUM>° and the corresponding information value is in a range between <NUM> and <NUM>.

<FIG> shows schematically an enlarged view <NUM> of a section of an optical neural network according to an embodiment of the invention, e.g. of the optical neural network <NUM>. The enlarged view <NUM> shows <NUM> synapse circuits <NUM> and a neuron circuit <NUM>. The neuron circuit <NUM> comprises or is coupled to a reference waveguide <NUM>. The reference waveguide <NUM> is configured to carry an optical reference signal Sr providing a reference phase ϕr. The neuron circuit <NUM> further comprises a plurality of input waveguides <NUM> configured to receive a plurality of phase-encoded optical input signals, in this example the neuron input signals Nin1,.

Nin2 and Nin3. The phase difference between the optical reference signal Sr and the neuron input signals Nin1, Nin2 and Nin3 represent the respective phase of the phase encoded optical input signals. More particularly, the neuron input signals Nin1, Nin2 and Nin3 have a phase ϕn1, ϕn2 and ϕn3 respectively with respect to the phase ϕr of the reference signal Sr.

The neuron circuit <NUM> processes the neuron input signals Nini, Nin2 and Nin3 and the reference signal Sr and provides a phase encoded optical output signal Nout having a phase ϕnout.

<FIG> shows an enlarged and more detailed view of the components of the neuron circuit <NUM> according to an embodiment of the invention.

The neuron circuit <NUM> comprises an optical interferometer system <NUM>. The optical interferometer system <NUM> comprises a plurality of first interferometers 14a. Each of the first interferometers 14a is configured to receive the optical reference signal Sr and one of the plurality of optical input signals Nin1, Nin2 or Nin3 and to superimpose the optical reference signal Sr and one of the respective optical input signals Nin1, Nin2 or Nin3 into a plurality of first interference signals I<NUM>, I<NUM> and I<NUM> respectively. The plurality of first interference signals I<NUM>, I<NUM> and I<NUM> form a plurality of amplitude-encoded signals. In other words, the respective amplitude of the first interference signals I<NUM>, I<NUM> and I<NUM> represents the information of the first interference signals I<NUM>, I<NUM> and I<NUM>.

In addition, the optical interferometer system <NUM> comprises a device 14b for a further processing of the first interference signals I<NUM>, I<NUM> and I<NUM>. According to an embodiment, the device 14b may be implemented as second interferometer 14b. According to such an embodiment the second interferometer 14b is configured to receive the plurality of first interference signals I<NUM>, I<NUM> and I<NUM> and to superimpose the plurality of first interference signals I<NUM>, I<NUM> and I<NUM> into a second interference signal I<NUM>. According to another embodiment, the device 14b may be implemented as amplitude-integration device, e.g. as a photodetector. According to such an embodiment, the amplitude-integration device 14b performs an integration/summation of the plurality of first interference signals, in this example of the first interference signals I<NUM>, I<NUM> and I<NUM> and provides a summation signal I<NUM> that emulates a summation/integration of the plurality of first interference signals I<NUM>, I<NUM> and I<NUM>.

The neuron circuit <NUM> further comprises a phase-shifting device <NUM> configured to provide a phase-encoded optical output signal Nout in dependence on the second interference signal I<NUM>. According to embodiments, the phase shifting device <NUM> performs a non-linear conversion of the second interference signal I<NUM> into the phase-encoded optical output signal Nout.

The phase shifting device <NUM> may comprise a non-linear material providing a non-linear power-to-refractive-index conversion. According to embodiments, the nonlinear material may be in particular BaTiO<NUM>. According to yet other embodiments, the phase shifting device <NUM> may comprise a phase change material such as VO<NUM> or chalcogenide-based materials. According to yet other embodiments, the phase shifting device <NUM> may be embodied as a plasma dispersion modulator.

The neuron circuit <NUM> further comprises a power normalization unit <NUM> configured to perform a normalization of the output power of the phase-encoded optical output signal Nout.

According to embodiments, the power normalization unit <NUM> comprises an amplifier 16a and a saturated absorber 16b.

<FIG> shows an enlarged and more detailed view of the components of a synapse circuit <NUM> according to an embodiment of the invention.

The synapse circuit <NUM> comprises a reference waveguide <NUM> configured to carry an optical reference signal Sr and an input waveguide <NUM> configured to receive a phase-encoded optical input signal Sin. A phase difference (pin between the phase ϕr of the optical reference signal and the phase of the optical input signal represents the phase ϕin of the phase encoded optical input signal Sin. In addition, the synapse circuit <NUM> comprises an output waveguide <NUM> and an optical interferometer <NUM>. The optical interferometer <NUM> is configured to convert the optical reference signal Sr and the optical input signal Sin into an interference signal I by superimposition. The interference signal I forms an amplitude-encoded signal. In other words, the amplitude of the interference signal I carries the information. Furthermore, the synapse circuit <NUM> comprises a tunable attenuator <NUM> configured to perform a weighting of the interference signal I into a weighted interference signal IW. The weighted interference signal IW may also be denoted as weighted amplitude-encoded signal. A phase-shifting device <NUM> is configured to convert the weighted interference signal IW into a phase-encoded optical output signal Sout. More particularly, the phase-shifting device <NUM> induces a phase shift in the optical reference signal Sr in dependence on the weighted interference signal IW. The induced phase shift may have a linear or a non-linear dependence on the weighted interference signal IW.

The synapse circuit <NUM> further comprises a power normalization unit <NUM> configured to perform a normalization of the output power of the phase-encoded optical output signal Sout.

The power normalization unit <NUM> comprises an amplifier 26a and a saturated absorber 26b.

<FIG> illustrates schematically an example of a plurality of optical input signals as well as a corresponding reference signal. More particularly, <FIG> shows optical input signals Nin1, Nin2 and Nin3 of the neuron circuit <NUM> as illustrated in <FIG> and optical input signals Sin1, Sin2 and Sin3 of the synapse circuit <NUM> as illustrated in <FIG>. In addition, a corresponding reference signal Sr is shown and illustrated with a dotted line.

The input signals Nin3, Sin3 are in phase with the reference signal Sr, corresponding to an input phase ϕ=<NUM>°. The input signals Nin2, Sin2 have a <NUM> degree phase shift with respect to the reference signal Sr and hence an input phase ϕ=<NUM>°. The input signals Nin1, Sin1 have a <NUM>° degree phase shift with respect to the reference signal Sr and hence an input phase ϕ=<NUM>°.

<FIG> illustrates schematically the superimposition of the plurality of optical input signals Nin1, Nin2 and Nin3 and Sin1, Sin2 and Sin3 respectively with the reference signal Sr.

This results in a set of interference signals, namely in this example in the set comprising the interference signals I<NUM>, I<NUM> and I<NUM>.

The interference signal I<NUM> of the input signals Nin3, Sin3 and the reference signal Sr has the highest amplitude A3 as both superimposed signals are in-phase. The interference signal I<NUM> of the input signals Nin2, Sin2 and the reference signal Sr has a medium amplitude A2. The interference signal I<NUM> of the input signals Nin1, Sin1 and the reference signal Sr has a zero amplitude due to the opposite phase of the input signals Nin1, Sin1 and the reference signal Sr.

According to an embodiment, the phase difference of <NUM> degree may be mapped to an information value V = "<NUM>", the phase difference of <NUM> degree to an information value V = "<NUM>" and the phase difference of <NUM> degree to an information value of V = "<NUM>".

According to another example, the phase difference of <NUM> degree may be mapped to an information value V = "<NUM>", the phase difference of <NUM> degree to an information value V = "<NUM>" and the phase difference of <NUM> degree to an information value V = "<NUM>".

<FIG> shows an enlarged and more detailed view of an embodiment of a phase shifting device <NUM> of the neuron circuit <NUM> according to an embodiment of the invention.

The phase shifting device <NUM> comprises according to this embodiment an optical cavity <NUM> comprising a non-linear optical material <NUM>. The optical cavity <NUM> is formed by a plurality of reflectors <NUM>. Furthermore, a gate waveguide <NUM> is provided and coupled to the optical cavity <NUM>. The phase shifting device <NUM> is configured to guide the second interference signal I<NUM> of the output of the second interferometer 14b via the gate waveguide <NUM> to the optical cavity <NUM>. The phase shifting device <NUM> is further configured to change the refractive index of the non-linear material <NUM> in dependence on the optical power of the second interference signal I<NUM>. More particularly, the optical cavity <NUM> is configured to receive the optical reference signal Sr via a waveguide <NUM> and to induce a phase shift in the optical reference signal Sr. As a result, the phase shifting device <NUM> provides the phase-encoded optical output signal Sout having a phase ϕout at an output waveguide <NUM>.

<FIG> shows an enlarged and more detailed view of an embodiment of a phase shifting device <NUM> of the synapse circuit <NUM> according to an embodiment of the invention.

The phase shifting device <NUM> comprises an optical cavity <NUM> comprising a non-linear optical material <NUM>. The optical cavity <NUM> is formed by a plurality of reflectors <NUM>. Furthermore, a gate waveguide <NUM> is provided and coupled to the optical cavity <NUM>. The phase shifting device <NUM> is configured to guide the weighted interference signal IW from the tunable attenuator <NUM> (see <FIG>) via the gate waveguide <NUM> to the optical cavity <NUM>. The phase shifting device <NUM> is further configured to change the refractive index of the non-linear material <NUM> in dependence on the optical power of the weighted interference signal IW. More particularly, the optical cavity <NUM> is configured to receive the weighted interference signal IW and to induce a phase shift in the optical reference signal Sr. As a result, the phase shifting device <NUM> provides the phase-encoded optical output signal Sout having a phase ϕout at an output waveguide <NUM>.

<FIG> shows a block diagram of an exemplary design flow <NUM> used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow <NUM> includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown e.g. in <FIG>. The design structures processed and/or generated by design flow <NUM> may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).

Design flow <NUM> may vary depending on the type of representation being designed. For example, a design flow <NUM> for building an application specific IC (ASIC) may differ from a design flow <NUM> for designing a standard component or from a design flow <NUM> for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

<FIG> illustrates multiple such design structures including an input design structure <NUM> that is preferably processed by a design process <NUM>. Design structure <NUM> may be a logical simulation design structure generated and processed by design process <NUM> to produce a logically equivalent functional representation of a hardware device. Design structure <NUM> may also or alternatively comprise data and/or program instructions that when processed by design process <NUM>, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure <NUM> may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure <NUM> may be accessed and processed by one or more hardware and/or software modules within design process <NUM> to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in <FIG>. As such, design structure <NUM> may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process <NUM> preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in <FIG> to generate a Netlist <NUM> which may contain design structures such as design structure <NUM>. Netlist <NUM> may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist <NUM> may be synthesized using an iterative process in which netlist <NUM> is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist <NUM> may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.

Design process <NUM> may include hardware and software modules for processing a variety of input data structure types including Netlist <NUM>. Such data structure types may reside, for example, within library elements <NUM> and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, <NUM>, <NUM>, <NUM>, etc.). The data structure types may further include design specifications <NUM>, characterization data <NUM>, verification data <NUM>, design rules <NUM>, and test data files <NUM> which may include input test patterns, output test results, and other testing information. Design process <NUM> may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process <NUM> without deviating from the scope and spirit of the invention. Design process <NUM> may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc..

Design process <NUM> employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure <NUM> together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure <NUM>. Design structure <NUM> resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure <NUM>, design structure <NUM> preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in <FIG>. In one embodiment, design structure <NUM> may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in <FIG>.

Design structure <NUM> may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure <NUM> may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in <FIG>. Design structure <NUM> may then proceed to a stage <NUM> where, for example, design structure <NUM>: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc..

<FIG> shows method steps of a method for emulating a neuron functionality. The method provides an integrated optical circuit. The integrated optical circuit processes a phase-encoded optical input signal, emulates a neuron functionality with respect to the phase-encoded optical input signal and provides a phase-encoded output signal.

More particularly, the method starts at a step <NUM>.

At a step <NUM>, a reference waveguide carries an optical reference signal.

At a step <NUM>, a plurality of input waveguides receive a plurality of phase-encoded optical input signals.

At a step <NUM>, an optical interferometer system superimposes the plurality of optical input signals and the optical reference signal into a plurality of first interference signals.

At a step <NUM>, the optical interferometer system superimposes the plurality of first interference signals into a second interference signal.

And at a step <NUM>, a phase-shifting device provides a phase-encoded optical output signal in dependence on the second interference signal.

Claim 1:
An integrated optical circuit (<NUM>) for an optical neural network (<NUM>), the optical circuit (<NUM>) being configured:
to process a plurality of phase-encoded optical input signals (Nin); and
to provide a phase-encoded optical output signal (Nout) as a function of the phase-encoded optical input signals (Nin), the phase-encoded optical output signal (Nout) emulating a neuron functionality with respect to the plurality of phase-encoded optical input signals (Nin);
the integrated optical circuit (<NUM>) comprising:
a reference waveguide (<NUM>) configured to carry an optical reference signal (Sr);
a plurality of input waveguides (<NUM>) configured to receive the plurality of phase-encoded optical input signals (Nin), wherein phase differences (ϕ) between the optical reference signal (Sr) and the optical input signals (Nin) represent the respective phase of the respective phase-encoded optical input signal (Nin);
an output waveguide (<NUM>);
an optical interferometer system (<NUM>) configured:
to superimpose the plurality of optical input signals (Nin) and the optical reference signal (Sr) into a plurality of first interference signals (I, I<NUM>, I<NUM>); and
to superimpose the plurality of first interference signals (I, I<NUM>, I<NUM>) into a second interference signal (I<NUM>); and
a phase-shifting device (<NUM>) configured to provide the phase-encoded optical output signal (Nout) as a function of the second interference signal (I<NUM>).