Patent Description:
The statements herein are intended for the mere purpose of providing background information related to the present invention and do not necessarily constitute prior art. Nowadays, display technology is widely used in the display of televisions, mobile phones and the display of public information. There are a variety of display panels for displaying pictures, and they can display colorful pictures. More and more display panels, such as Thin Film Transistor-Liquid Crystal Displays (TFT-LCD), Organic Light Emitting Diode (OLED) displays, etc., need to use Gate Driver on Array (GOA) technology, in which the GOA circuits are integrated onto the array substrate in the display panel to realize the scanning and driving of the display panel, so that the product costs can be reduced in terms of materials cost and manufacturing process. Typically, when manufacturing a GOA circuit, the source, drain and source leads in a thin film transistor are disposed in the same layer and formed by etching at the same time, but the problem of uneven etching is prone to occur during the etching process. Furthermore, as the degree of integration of GOA circuits is getting increasingly higher, the distance between the source and the drain is getting smaller and smaller, so when the etching is not uniform, the source lead will be connected to both the source and the drain, resulting in a short circuit between the source and the drain. One of prior art documents referring to a control switch of a drive circuit, an array substrate and a display panel is <CIT>.

The present invention provides a control switch of a drive circuit, an array substrate, and a display panel, which can prevent the occurrence of a short circuit between a source electrode and a drain electrode caused by uneven etching of the drive circuit.

The present invention is as defined in claim <NUM>. The preferred embodiments are set out in the appended set of dependent claims. The present invention provides a control switch of a drive circuit, the control switch including a thin film transistor. The drive circuit further includes a source lead connected to the thin film transistor. The thin film transistor includes a source electrode, a drain electrode and a gate electrode, where the source electrode includes at least two source branches arranged in parallel, and a source trunk connecting the at least two source branches. The drain electrode is arranged in the same layer as the source electrode, and includes at least one drain branch and a drain trunk connecting the at least one drain branch together. The at least one drain branch and the at least two source branches are arranged in parallel and alternately to form channels, and the gate is arranged corresponding to the source electrode and the drain electrode. The source branch directly connected to the source lead is a first source branch, and the source branch not directly connected to the source lead is a second source branch. A channel width between the first source branch and the adjacent drain branch is greater than the channel width between the second source branch and the adjacent drain branch.

The present invention further discloses an array substrate that includes a drive circuit, a source lead, and a scan line driven by the drive circuit. The drive circuit includes a control switch, the control switch including a thin film transistor that is connected to the source lead. The thin film transistor includes a source electrode, a drain electrode and a gate electrode. The source electrode includes at least two source branches arranged in parallel, and a source trunk connecting the at least two source branches. The drain electrode is arranged in the same layer as the source electrode, and includes at least one drain branch and a drain trunk connecting the at least one drain branch. The at least one drain branch and the at least two source branches are arranged in parallel and alternately to form channels, and the gate is arranged corresponding to the source electrode and the drain electrode. The source branch directly connected to the source lead is a first source branch, and the source branch not directly connected to the source lead is a second source branch. A channel width between the first source branch and the adjacent drain branch is greater than the channel width between the second source branch and the adjacent drain branch.

The present invention further discloses a display panel, comprising an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. The array substrate includes a drive circuit, a source lead and a scan line driven by the drive circuit. The drive circuit includes a control switch, the control switch including a thin film transistor that is connected to the source lead. The thin film transistor includes a source electrode, a drain electrode and a gate electrode. The source electrode includes at least two source branches arranged in parallel, and a source trunk connecting the at least two source branches. The drain electrode is arranged in the same layer as the source electrode, and includes at least one drain branch and a drain trunk connecting the at least one drain branch. The at least one drain branch and the at least two source branches are arranged in parallel and alternately to form channels, and the gate is arranged corresponding to the source electrode and the drain electrode. The source branch directly connected to the source lead is a first source branch, and the source branch not directly connected to the source lead is a second source branch. A channel width between the first source branch and the adjacent drain branch is greater than the channel width between the second source branch and the adjacent drain branch.

Compared with the current solution in which the channel width between every two adjacent source branch and drain branch in the thin film transistor is set equal, the present invention increases the channel width between the first source branch that is connected to the source lead and the adjacent drain branch in the thin film transistor. When etching the entire metal layer where the source electrode, the drain electrode and the source lead are located, if unevenness of etching occurs such that the ends of the source lead are not cleanly etched causing the end of the source lead to protrude from the first source branch, the end of the source lead still will not reach and intersect the drain so that no short circuit will be caused between the source and the drain due to the increased channel width between the first source branch and the adjacent drain branch. Such arrangement is therefore beneficial to improve the product's production yield.

The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention, constitute a part of the specification, are used to illustrate the embodiments of the present invention, and together with the written description, serve to explain the principles of the present invention. Obviously, the drawings used in the following description merely depict some embodiments of the present invention, and for those having ordinary skill in the art, other drawings can also be obtained from these drawings without investing creative effort. In the drawings:.

It should be understood that the terminology used herein, the specific structural and functional details disclosed are intended for the mere purpose of describing specific embodiments and are representative, but the present invention may be embodied in many alternative forms and should not be construed as limited only the embodiments set forth herein.

In the description of this invention, the terms "first" and "second" are merely used for description purposes, and cannot be understood as indicating relative importance, or implicitly indicating the number of indicated technical features. Thus, unless otherwise specified, features defined as "first" and "second" may expressly or implicitly include one or more of the features; "plurality" means two or more. The terms "including", "comprising", and any variations thereof are intended to mean a non-exclusive inclusion, namely one or more other features, integers, steps, operations, units, components and/or combinations thereof may be present or added.

In addition, terms such as "center", "transverse", "lateral", "above", "on", "under", "below", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicative of orientations or positional relationships are described based on the orientations or relative positional relationships illustrated in the drawings, and are intended for the mere purpose of convenience of simplified description of the present invention, rather than indicating that the device or element referred to must have a specific orientation or be constructed, and operate in a particular orientation. Thus, these terms should not be construed as limiting the present invention.

In addition, unless otherwise expressly specified and defined, terms "installed on", "connected to", and "coupled to" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, or may also be an electrical connection; it may be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components. For those having ordinary skill in the art, the specific meanings of the above terms in this invention can be understood depending on specific contexts.

The present invention will be described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, should no conflict be present, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

<FIG> show schematic plan views of an array substrate. A scan line <NUM> is disposed in a display area of the array substrate <NUM>, and a drive circuit <NUM> is disposed in a non-display area of the array substrate <NUM>, which may specifically be an array substrate gate drive circuit. The drive circuit <NUM> includes a frame start signal line <NUM>, a gate voltage control line <NUM>, a clock signal line <NUM> and a plurality of gate drive units <NUM>. The input ends of the gate drive unit <NUM> are respectively connected to STV, VGL and CKV, and the output end of the gate drive circuit <NUM> is connected to the scan line <NUM> to drive the scan line <NUM>.

In particular, the gate drive unit <NUM> includes a first thin film transistor <NUM>, a second thin film transistor <NUM>, a third thin film transistor <NUM> and a fourth thin film transistor <NUM>. The source electrode <NUM> of the first thin film transistor <NUM> is connected to the gate voltage control line <NUM> and to the source electrode <NUM> of the second thin film transistor <NUM> through two source leads <NUM>, respectively. The drain electrode <NUM> of the first thin film transistor <NUM> is connected to the source electrode <NUM> of the third thin film transistor <NUM> and to the gate electrode <NUM> of the fourth thin film transistor <NUM>, and the gate electrode <NUM> of the first thin film transistor <NUM> is connected to the gate <NUM> of the second thin film transistor <NUM>. The drain electrode <NUM> of the second thin film transistor <NUM> is connected to the source electrode <NUM> of the fourth thin film transistor <NUM>, and the gate electrode <NUM> of the second thin film transistor <NUM> is connected to the gate electrode <NUM> of the fourth thin film transistor <NUM>. The drain <NUM> of the third thin film transistor <NUM> is connected to the frame start signal line <NUM>.

The drain <NUM> of the fourth thin film transistor <NUM> is connected to the clock signal line <NUM>.

In the gate drive unit <NUM> shown in <FIG>, there are four thin film transistors connected to each other and other wirings. It can be seen in <FIG> that there are three blank areas, namely area A, area B and area C; between area B and area C, two thin film transistors <NUM> are connected through a source lead <NUM>. Before the metal layer is etched into the source electrode <NUM>, the drain electrode <NUM> and other metal line patterns, an etching stop layer needs to be formed on the source electrode <NUM>, the drain electrode <NUM> and other metal line patterns, and then a developer is used to form the stop layer pattern. Since the area B and the area C are relatively large, more developer needs to be consumed, so that the developing energy consumed by the area D and the area E is reduced, and so the stop layers corresponding to the area D and the area E cannot be easily completely etched, hence the problem of uneven etching occurs when etching the metal layer pattern, resulting in the short circuit of the source electrode <NUM> and the drain electrode <NUM> at the region D and the region E.

<FIG> show partial schematic diagrams of two exemplary GOAs. When the metal patterns corresponding to the regions D and E are not uniformly etched, the source leads <NUM> in <FIG> will extend into the channel of the source <NUM> of the thin film transistor <NUM>, or even connect with the drain electrode <NUM>, resulting in a short circuit between the source electrode <NUM> and the drain electrode <NUM>.

<FIG> are schematic diagrams respectively based on <FIG> under ideal conditions, but they needs to consume a lot of developer to ensure that the stop layers corresponding to the regions D and E are completely etched, so that when the metal pattern is subsequently etched, the source lead <NUM> does not protrude from the source electrode <NUM> and extend into the channel of the source electrode <NUM>.

In view of this, the present invention provides a control switch of a drive circuit <NUM> that does not cause a short circuit between the source electrode <NUM> and the drain electrode <NUM> even when the etching is uneven. As illustrated in <FIG>, <FIG>, the control switch includes a thin film transistor <NUM>, and the drive circuit <NUM> further includes a source lead <NUM> connected to the thin film transistor <NUM>. The thin film transistor <NUM> includes a source electrode <NUM>, a drain electrode <NUM> and a gate electrode <NUM>. The source electrode <NUM> includes at least two source branches <NUM> arranged in parallel, and a source trunk <NUM> connecting the at least two source branches <NUM>. The drain electrode <NUM> is disposed in the same layer as the source electrode <NUM>, and includes at least one drain branch <NUM>, and a drain trunk <NUM> connecting the at least one drain branch <NUM> together. The at least one drain branch <NUM> and the at least two source branches <NUM> are arranged in parallel and alternately to form channels. The gate electrode <NUM> is arranged corresponding to the source electrode <NUM> and the drain electrode <NUM>. The source branch <NUM> directly connected to the source lead <NUM> is a first source branch <NUM>, and the source branch <NUM> not directly connected to the source lead <NUM> is a second source branch <NUM>. A channel width between the first source branch <NUM> and the adjacent drain branch <NUM> is greater than the channel width between the second source branch <NUM> and the adjacent drain branch <NUM>.

It should be noted that when there is only one drain branch <NUM>, then the drain trunk <NUM> is a part of the drain branch <NUM> and is connected to other structures in the drive circuit <NUM>. The gate electrode <NUM> may be disposed above the source electrode <NUM> and the drain electrode <NUM>, or may be disposed below the source electrode <NUM> and the drain electrode <NUM>.

Compared with the current solution in which the channel widths between the source branches <NUM> and the drain branches <NUM> of the thin film transistor <NUM> are set equal, the present invention increases the width of the outer channels of the thin film transistor <NUM>, namely the distance between the first source branch <NUM> and the adjacent drain branch <NUM>. In the process of etching the metal layer where the source electrode <NUM>, the drain electrode <NUM> and the source electrode lead <NUM> are located, since the blank areas of the region B and the region C are relatively large and require more etchant needs, the etchant in area D and area E is insufficient, resulting in uneven etching of the metal patterns in area D and area E. However, with the above design proposed by the present invention, even if the source lead <NUM> is not etched cleanly such that the end of the source lead <NUM> protrudes from the first source branch <NUM>, the end of the source lead <NUM> will not reach and intersect the drain <NUM> and so the source <NUM> and the drain <NUM> will not be short-circuited because the gap between the first source branch <NUM> and the adjacent drain branch <NUM> is increased. Which is beneficial to improve the product's production yield.

As illustrated in <FIG>, in one embodiment, the thin film transistor <NUM> needs to be connected to two source leads <NUM>, and in this case, the number of the first source branches <NUM> is two, and the two first source branches <NUM> are respectively connected to both ends of the source trunk <NUM>, and the two source leads <NUM> are respectively connected to the two first source branches <NUM>. The second source branch <NUM> is arranged in parallel between the two first source branches <NUM>, and is connected to the source trunk <NUM>. Correspondingly, the drain <NUM> includes a first drain branch <NUM> and a second drain branch <NUM> arranged in parallel, and a drain trunk <NUM> connecting the first drain branch <NUM> and the second drain branch <NUM>. The first drain branch <NUM> and the second drain branch <NUM> are respectively connected to two ends of the drain trunk <NUM>. The first drain branch <NUM> is disposed between the first source branch <NUM> and the second source branch <NUM>, and the second drain branch <NUM> is disposed between the other first source branch <NUM> and the second source branch <NUM>.

In this embodiment, there is only one second source branch <NUM>, one first drain branch <NUM> and one second drain branch <NUM>, the source electrode <NUM> is similar to a W structure, and the drain <NUM> is similar to a U structure. In this case, the channel width between the first drain branch <NUM> and the second source branch <NUM> is equal to the channel width between the second drain branch <NUM> and the second source branch <NUM>, but both widths are less than the channel width between the first source branch <NUM> and the first drain branch <NUM>, and are also smaller than the distance between the first source branch <NUM> and the second drain branch <NUM>. In this embodiment, by increasing the channel width between the outer source branch <NUM> and the drain branch <NUM> of the thin film transistor <NUM>, the problem is prevented that the end of the source lead <NUM> is not etched cleanly due to uneven etching such that the source lead <NUM> protrudes from the first source branch <NUM> and reaches and intersects the source <NUM> and the drain <NUM>, resulting in a short circuit between the source <NUM> and the drain <NUM>. In addition, in this embodiment, not all channels in the thin film transistor <NUM> are widened at the same time, so that it will not lead to an increase in the volume of the thin film transistor <NUM>, nor will the increase of the distance between the source electrode <NUM> and the drain electrode <NUM> cause the performance of the thin film transistor <NUM> to deteriorate.

Of course, this embodiment is also applicable to more complex thin film transistor <NUM> structures. As illustrated in <FIG>, there is shown another type of thin film transistor <NUM>. The source electrode <NUM> of the thin film transistor <NUM> includes at least two second source branches <NUM>, and the drain electrode <NUM> of the thin film transistor includes at least two drain branches <NUM>. In this case, the thin film transistor <NUM> contains more than four channels, but the widths of the other channels are equal except that the two outermost channels have wider widths.

As illustrated in <FIG>, in another embodiment, the source electrode <NUM> of the thin film transistor <NUM> does not include the second source branch <NUM>; that is, the source electrode <NUM> has only two first source branches <NUM> and one source trunk <NUM>, and so the source electrode <NUM> is U-shaped. In this case, the drain <NUM> has only one drain branch <NUM>, and there are only two channels in the thin film transistor <NUM>. In this embodiment, on the basis of the existing channel width, the width of the channel is increased to prevent the problem of uneven etching when the metal layer where the source electrode <NUM>, the drain electrode <NUM> and the source lead <NUM> are located is etched. That is, due to the small width of the channel, the source lead <NUM> easily extends into the channel to connect with the drain branch <NUM>, so that the source electrode <NUM> and the drain electrode <NUM> are short-circuited.

In the above embodiments, the thin film transistor <NUM> is connected to two source leads <NUM> at the same time, and the two source leads <NUM> are respectively vertically connected to the first source branches <NUM> on both sides of the thin film transistor <NUM>, and the two source leads <NUM> is not on the same line. In connection with <FIG>, in the drive circuit <NUM>, one source lead <NUM> is closer to the area B, and one source lead <NUM> is closer to the area C, so that the spaces of the area B and the area C are closer, the uniformity of the etchant distribution is improved, which is conducive to the uniform effect of the metal layer etching in the area D and the area E.

Furthermore, in this embodiment, the thin film transistor <NUM> is located between the region B and the region C, and its channel width is larger than the channel widths of the thin film transistor in other positions in the gate drive unit <NUM>, more particularly larger than the channel width of the thin film between the region A and the region B.

In the embodiments portrayed in <FIG>, one thin film transistor <NUM> is connected to two source leads <NUM> at the same time, and their difference lies in the different types of thin film transistors <NUM>. In the subsequent embodiments, however, one thin film transistor <NUM> is connected to one source lead <NUM>, and the difference also lies in that the types of thin film transistors <NUM> are different. The drive circuits <NUM> in these different embodiments can be combined and matched depending on different usage environments and usage requirements, so that the drive circuit <NUM> is less prone to short-circuit problems while satisfying the requirement of small occupied space.

As illustrated in <FIG>, as another embodiment of the present invention, the thin film transistor <NUM> is only connected to one source lead <NUM>. The thin film transistor <NUM> includes a source electrode <NUM> and a drain electrode <NUM>. The source electrode <NUM> includes a first source branch <NUM> and a second source branch <NUM> arranged in parallel, and the first source branch <NUM> and the second source branch <NUM> are respectively connected to two ends of the source trunk <NUM>. The source electrode <NUM> is U-shaped, and the source lead <NUM> is connected to the first source branch <NUM>. The drain <NUM> includes a first drain branch <NUM> disposed between the first source branch <NUM> and the second source branch <NUM> and respectively form two channels with the first source branch <NUM> and the second source branch <NUM>. The channel width between the first source branch <NUM> and the first drain branch <NUM> is greater than the channel width between the second source branch <NUM> and the first drain branch <NUM>.

This embodiment is aimed at the case where the thin film transistor <NUM> is connected to only one source lead <NUM>. By increasing the channel width adjacent to the source lead <NUM>, the safety performance of the thin film transistor <NUM> is improved, the situation is avoided where the source lead <NUM> is connected to the drain <NUM> when the etching is uneven such that the source <NUM> and the drain <NUM> are short-circuited. Of course, on the basis of this embodiment, the number of channels can also be increased; that is, the number of the second source branches <NUM> can be increased to two or more, and one or more second drain branches <NUM> can be added, so that the performance of the thin film transistor <NUM> is improved.

Further, in the above embodiment, the channel width between the first source branch <NUM> and the adjacent drain branch <NUM> is <NUM>-<NUM> times the channel width between the second source branch <NUM> and the adjacent drain branch <NUM>. That is to say, let the channel width between the second source branch <NUM> and the adjacent drain branch <NUM> be L, and the channel width between the first source branch <NUM> and the adjacent drain branch <NUM> be L+X, then X is <NUM>-<NUM> times L. Further, the channel width between the second source branch <NUM> and the adjacent drain branch <NUM> is <NUM>-<NUM>, and the channel width between the first source branch <NUM> and the adjacent drain branch <NUM> is <NUM>-<NUM>.

When etching the metal film layer where the source and drain electrodes are located, it is needed to first lay a metal layer on the surface of the entire array substrate, then form a photoresist on the metal layer, and then use a mask to illuminate the photoresist to form a photoresist pattern. The metal film layer is etched by means of the photoresist pattern to form scanning lines in the display area and gate drive circuits in the non-display area of the array substrate. The minimum gap of a typical half-tone mask in the gate driver circuit of the array substrate is <NUM>, and the minimum gap in the display area is <NUM>. In contrast, the minimum gap of a single slit mask (SSM) in the GOA area is <NUM>, and the minimum gap in the display area is <NUM>.

Since the thickness of the mask needs to be reduced by <NUM>-800A for every compensation of <NUM> of mask gap, it can be compensated with respect to different phenomena. In the present invention, the width compensation is performed on the regions D and E, where the drive circuit is prone to short circuit, to increase the widths of the outer channels of the thin film transistor, namely to increase the distance between the first source branch <NUM> and the adjacent drain branch. Due to the limitations of the process, the inventor has found through many experiments that when the exposure amount in the region D and the region E is increased by <NUM>-<NUM> MJ, the thickness of the mask is reduced by <NUM>-2000A, the channel width between the first source branch <NUM> and the adjacent drain branch is increased by <NUM>-<NUM>, and the original channel width is supplemented by <NUM> times. As such, the short-circuit problem in area D and area E can be effectively overcome, the yield of GOA is greatly improved, and the energy consumed in the process of exposure and development is not high, which is beneficial to production.

In this invention, all source branches <NUM> and drain branches <NUM> are strip-shaped structures, which can be rectangular, oval or other shapes. The extension direction of the source branch <NUM> and the extension direction of the source trunk <NUM> are perpendicular to each other, and the extension direction of the drain branch <NUM> and the extension direction of the drain trunk <NUM> are also perpendicular to each other. However, the extension direction of the source branch <NUM> and the extension direction of the source trunk <NUM> may form an acute angle, and the extension direction of the drain branch <NUM> and the extension direction of the drain trunk <NUM> may also form an acute angle. Moreover, the widths of the source branches <NUM>, the source trunk <NUM>, the drain branches <NUM> and the drain trunk <NUM> are all equal, and the channel widths between the second source branches <NUM> and the adjacent drain branches <NUM> are also equal, thereby increasing the conductivity of the thin film transistor <NUM>.

In addition, the present invention can improve the charging efficiency of the thin film transistor <NUM> by widening the width of the source lead <NUM>. According to the resistance formula, under the condition that the material and length of the source lead <NUM> do not change, the resistance of the entire source lead <NUM> can be reduced by increasing the width of the source lead <NUM>. Since the width of the source lead <NUM> is increased, in the case of uneven etching, the area of the portion of the source lead <NUM> protruding from the first source branch <NUM> may be larger. However, since the present invention has widened the channel width between the first source branch <NUM> and the drain branch <NUM>, even if the width of the source lead <NUM> is widened, it is not easy to cause the source lead <NUM> to be connected to the drain <NUM>. Therefore, under the condition of improving the charging efficiency of the thin film transistor <NUM> in the present invention, even if the problem of uneven etching occurs, the source and drain electrodes <NUM> and <NUM> will not be short-circuited. In particular, the maximum width of the source lead <NUM> can be the same as the length of the first source branch <NUM>, so that the source lead <NUM> can cover the first source branch <NUM>.

<FIG> shows a schematic diagram of a display panel. As another embodiment of the present invention, a display panel <NUM> is further disclosed. The display panel <NUM> includes the array substrate <NUM> illustrated in <FIG>, a color filter substrate <NUM> disposed opposite to the array substrate <NUM>, and a liquid crystal layer <NUM> disposed between the array substrate <NUM> and the color filter substrate <NUM>. The non-display area of the array substrate <NUM> includes the above-mentioned drive circuit <NUM>. In addition, the thin film transistor <NUM> in any embodiment of the present invention is not only applicable to the control switches of the drive circuit <NUM> in the non-display area, but also applicable to the active switches in the display area of the array substrate <NUM>.

The technical solutions of the present invention may be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, and MVA (Multi-Domain Vertical Alignment) display panels. Of course, the above solutions are also applicable to other types of display panels.

Claim 1:
A control switch of a drive circuit (<NUM>), the control switch comprising a thin film transistor (<NUM>), the drive circuit (<NUM>) further comprising a source lead (<NUM>) connected to the thin film transistor (<NUM>), the thin film transistor (<NUM>) comprising:
a source electrode (<NUM>), comprising at least two source branches (<NUM>) arranged in parallel, and a source trunk (<NUM>) connecting the at least two source branches (<NUM>) together;
a drain electrode (<NUM>), disposed in a same layer as the source electrode (<NUM>), and comprising at least one drain branch (<NUM>) and a drain trunk (<NUM>) connecting the at least one drain branch (<NUM>) together, wherein the at least one drain branch (<NUM>) and the at least two source branches (<NUM>) are arranged in parallel and alternately to form channels; and
a gate electrode (<NUM>), arranged corresponding to the source electrode (<NUM>) and the drain electrode (<NUM>);
each source branch (<NUM>) directly connected to the source lead (<NUM>) is a first source branch (<NUM>), and each source branch (<NUM>) not directly connected to the source lead (<NUM>) is a second source branch (<NUM>); characterized in that
a channel width between the first source branch (<NUM>) and an adjacent drain branch (<NUM>) of the at least one drain branch is greater than a channel width between the second source branch (<NUM>) and the adjacent drain branch (<NUM>) of the at least one drain branch.