Patent Description:
A semiconductor processing device typically includes conductive pads or pins to electrically connect the processing device to components external to the device. The connections allow signals to be communicated electronically between the processor and the external components. The conductive pads/pins are connected to input/output (I/O) circuitry in the processor that provide an interface to components in the processor. Depending on the application, a microcontroller's I/O circuitry may comprise a primary interface to external circuitry or may be just one type of output used among several, such as analog signals, counter/timer, and serial communication. Multi-Purpose I/O (MPIO) circuitry in a semiconductor processing device has no predefined purpose and may be assigned for whatever use is needed.

In automotive applications, Multi-Purpose Output (MPO) circuits can be used to communicate signals for purposes such as turning on a warning lamp, driving an actuator, and reading wheel speed, among others. Since the I/O circuitry is coupled to external components, the circuitry may be subject to electrical stresses such as direct power injection. The I/O circuitry may also generate emissions that affect other circuits.

Accordingly, it is desirable to provide MPO circuitry with improved electromagnetic compatibility that is both immune to electrical stress as well as avoids affecting operation of other circuits.

<CIT> describes a switching element drive circuit that may provide useful background to the present disclosure. <CIT> describes a local interconnect network (LIN) driver circuit that may provide useful background to the present disclosure.

Embodiments disclosed herein provide multi-purpose output (MPO) circuitry with features that increase immunity to electrical stress from direct power injection and reduce emissions that may affect other circuitry. To achieve these improvements, filters are used to redirect signals of selected frequencies. A first filter with a high cutoff frequency is added near current sources to prevent an output transistor from being switched ON during direct power injection when the transistor should be switched OFF. A second filter with a lower cutoff frequency is added to remove noise at the input to an output driver. In addition, a stronger pull-down device is implemented in the driver to maintain input and output at a low level to insure the voltage at the control gate of the output transistor is low enough to avoid turning the transistor ON in an OFF state. These and other features and advantages are further described hereinbelow.

<FIG> illustrates a block diagram of integrated circuit <NUM> that includes multi-purpose output (MPO) circuitry in accordance with selected embodiments of the present invention that includes a system on chip with MPO circuitry <NUM> having output contact <NUM> coupled to a load represented by resistor <NUM> at battery voltage VBAT and load capacitor <NUM>. In the embodiment shown, MPO circuitry <NUM> includes current sources <NUM>, low pass filter <NUM> with high cutoff frequency, slew rate capacitor <NUM>, low pass filter <NUM> with medium cutoff frequency, driver buffer <NUM> with pull-down device <NUM>, output power switch <NUM>, sense resistor <NUM>, and multi-purpose output contact <NUM>. High cutoff frequency low pass filter <NUM> includes resistor <NUM> and capacitor <NUM>. Medium cutoff frequency low pass filter <NUM> includes resistor <NUM> and capacitor <NUM>. The SoC may also include other components such as one or more processing cores coupled to MPO circuitry, direct memory access controllers, memory devices, interconnects, peripheral and network interfaces, and other suitable components.

Current sources <NUM> receive digital output data and control signals from a processor core or other suitable component. A first terminal of resistor <NUM> is coupled to the output of current sources <NUM>, and a second terminal of resistor <NUM> is coupled to a first terminal of resistor <NUM> in medium cutoff frequency low pass filter <NUM> at node OUT. A second terminal of resistor <NUM> is coupled to the input of driver circuit <NUM>. Capacitor <NUM> includes a first terminal coupled to the first terminal of resistor <NUM> and a second terminal coupled to ground. Capacitor <NUM> includes a first terminal coupled to the second terminal of resistor <NUM> and a second terminal coupled to ground. Driver circuit <NUM> includes an input coupled to the output of medium cutoff frequency low pass filter <NUM> and an output coupled to a control gate of output power switch <NUM>. A first electrode of power switch <NUM> is coupled to node MPO_OUT and a second electrode of power switch <NUM> is coupled to a first terminal of resistor <NUM>. A second terminal of resistor <NUM> is coupled to ground. Slew rate capacitor <NUM> includes a first terminal coupled to output contact <NUM> and a second terminal coupled to the connection between high cutoff frequency low pass filter <NUM> and medium cutoff frequency low pass filter <NUM>. Node MPO_OUT is also coupled to output contact <NUM>.

Current sources <NUM> can be implemented using a digital to analog converter (DAC) or other suitable device. Digital data and control signals are provided as input to current sources <NUM>, and depending on the type of current sources <NUM> being used, the control signals can include a clock signal, a synchronization signal, and/or other suitable signals. The digital data can include a number of bits, based on the data word length. Current sources <NUM> generate an analog current or voltage representative of the digital data. The output from current sources <NUM> is provided to the input of high cutoff frequency low pass filter <NUM>. The output of high cutoff frequency low pass filter <NUM> is provided to the input of medium cutoff frequency low pass filter <NUM>. The output of medium cutoff frequency low pass filter <NUM> is provided to the input of driver circuit <NUM>. The output of driver circuit <NUM> is provided to a control electrode of power switch <NUM>.

A slew rate control function using capacitor <NUM> can be used to control emissions of output contact <NUM> to not disturb external devices. Emission control is done by controlling a current inside capacitor <NUM> between node OUT and output contact <NUM>. Capacitor <NUM> can, however, create a new perturbation path for electro-magnetic perturbations between output contact <NUM> and the input to driver circuit <NUM> and the output of current sources <NUM>. The perturbation, referred to as direct power injection (DPI), can occur at any time at output contact <NUM>, and can create a dysfunction while output power switch <NUM> is OFF. While load capacitor <NUM> can be used to absorb some of the perturbation, capacitor <NUM> can be used to control slew rate on an external MPO pin, and create a new path for DPI perturbation. In this way, the rectification due to diode effects in power switch <NUM> can be limited, with the DPI perturbation being conducted through slew rate capacitor <NUM>. Using capacitor <NUM> does, however, direct the DPI perturbation toward current sources <NUM> and driver circuit <NUM>, which can cause other problems at certain frequencies. For example, at higher frequencies, a noisy signal from current sources <NUM> caused by the DPI perturbation can cause power switch <NUM> to turn ON when power switch <NUM> is intended to be OFF. In addition, medium frequency perturbation can affect the output of driver circuit <NUM> and thus the output signal used to control the operation of power switch <NUM>. The problems caused by the DPI perturbation being conducted through capacitor <NUM> to current sources <NUM> and driver circuit <NUM> can be overcome using high cutoff frequency low pass filter <NUM> and medium cutoff frequency low pass filter <NUM>, however, as further explained herein.

Output driver circuit <NUM> can be implemented with an operational amplifier or other suitable component. In some implementations, voltage at output contact <NUM> is expected to be close to 0V when MPO circuitry <NUM> is ON and at battery voltage (e.g., 14V) when MPO circuitry <NUM> is OFF. For DPI perturbations at certain low frequencies and amplitude, for example, frequencies between <NUM>-<NUM> and <NUM> dBm amplitude, MPO circuitry <NUM> may be unable to remain OFF as the perturbation voltage at the input to driver circuit <NUM> causes the output of driver circuit <NUM> to be at a level that causes power switch <NUM> to turn ON and pull the voltage at node MPO_OUT to ground. To solve this issue, a pull-down device <NUM> can be implemented at an input stage of driver circuit <NUM> that is strong enough to help ensure power switch <NUM> remains OFF when MPO circuitry <NUM> is supposed to be OFF. Pull-down device <NUM> can be implemented with an NMOS or N-type channel transistor with a source electrode coupled to ground and a drain electrode coupled to a voltage source and to control operation of power switch <NUM>. Other suitable components can be used to maintain the input and output of driver circuit <NUM> at a level that prevents power switch <NUM> from being turned ON when MPO circuitry <NUM> is supposed to be OFF.

In addition to problems caused by DPI perturbations at low frequencies, DPI perturbations at medium frequencies, for example, <NUM>-<NUM> at an amplitude of <NUM> dBm, can also cause the input voltage at driver circuit <NUM> to be higher than desired to provide an output that turns power switch <NUM> ON when power switch <NUM> and therefore MPO circuitry <NUM> are supposed to be OFF. To help solve this problem, medium cutoff frequency low pass filter <NUM> can be implemented between capacitor <NUM> to remove medium frequency perturbation at the input to driver circuit <NUM>.

DPI perturbation may also have relatively high frequency components, for example, frequency between <NUM>-<NUM> at an amplitude of <NUM> dBm. If high cutoff frequency low pass filter <NUM> is not implemented, the DPI perturbation may be sufficient to increase the voltage at the input of driver circuit <NUM> to a level that will cause power switch <NUM> to turn ON unexpectedly. For example, during an OFF phase of MPO circuitry <NUM>, power switch <NUM> is typically not in a conductive mode. The OUT_CURRENT voltage from current sources <NUM> can be sufficiently noisy that, when added to the DPI perturbation, power switch <NUM> will be turned ON instead of OFF. High cutoff frequency low pass filter <NUM> at the output of current sources <NUM> can remove high frequency voltage from the output of capacitor <NUM> at node OUT that can otherwise affect the output of current sources <NUM>. MPO circuitry <NUM> can thus be prevented from turning ON unintentionally due to high frequency DPI perturbation.

Power switch <NUM> can be implemented with a MOS transistor or other suitable device. For example, in the embodiment shown, power switch <NUM> is implemented with an NMOS transistor, however, power switch <NUM> can be implemented with a PMOS transistor with other components of driver circuit <NUM> adjusted to take into account the opposite logic.

Referring to <FIG> and <FIG> illustrates a set of curves of an example of performance of multi-purpose output circuitry <NUM> with DPI perturbation at output pin <NUM> without design improvements disclosed herein. Curve <NUM> shows the required level of amplitude versus frequency while curves <NUM> through <NUM> show performance of MPO circuitry <NUM> at different levels of capacitance values for load capacitor <NUM>. The requirement curve <NUM> begins with a ramp starting at <NUM> with a <NUM> dBm amplitude and ending at <NUM> at an amplitude of <NUM> dBm. At <NUM>, requirement curve <NUM> remains at an amplitude of <NUM> dBm to a frequency of <NUM>. Curve <NUM> shows a target level of amplitude of <NUM> dBm over the range of frequencies from <NUM> to <NUM> and <NUM> Watts power. Curve <NUM> shows, for load capacitor with a value of <NUM> nF, amplitude at <NUM> dBm over the range of frequencies from <NUM> to <NUM> except a small dip in amplitude to <NUM> dBm between <NUM> and <NUM>, and a larger dip in amplitude to <NUM> dBm between <NUM> and <NUM>. Curve <NUM> shows, for a slew rate capacitor with a value of <NUM> nF, a level of amplitude of <NUM> dBm over the range of frequencies from <NUM> to <NUM>, except a large dip in amplitude to <NUM> dBm between <NUM> and <NUM>. Curve <NUM> shows, for a slew rate capacitor with a value of <NUM> nF, a level of amplitude of <NUM> dBm over the range of frequencies from <NUM> to <NUM>, except a large dip in amplitude to <NUM> dBm between <NUM> and <NUM>.

As can be seen from <FIG>, larger capacitance values for load capacitor <NUM> achieve better performance than lower capacitance values up to frequencies between <NUM> and <NUM>. Smaller capacitance values for load capacitor <NUM> achieve better performance than higher capacitance values below <NUM>. Thus, these two problem areas are addressed with medium cutoff frequency low pass filter <NUM> and high cutoff frequency low pass filter <NUM> in MPO circuit <NUM> (<FIG>), as shown in <FIG>, which illustrates a set of curves of an example of performance of multi-purpose output circuitry <NUM> with design improvements disclosed herein. The requirement curve <NUM> is the same as shown in <FIG>, beginning with a ramp starting at <NUM> with a <NUM> dBm amplitude and ending at <NUM> at an amplitude of <NUM> dBm. At <NUM>, requirement curve <NUM> remains at an amplitude of <NUM> dBm to a frequency of <NUM>. Curve <NUM> shows a target level of amplitude of <NUM> dBm over the range of frequencies from <NUM> to <NUM>. Curve <NUM> shows, for a load capacitor with a value of <NUM> nF, amplitude at <NUM> dBm over the range of frequencies from <NUM> to <NUM> with no dips in amplitude at the lower or higher frequencies. Thus, medium cutoff frequency low pass filter <NUM> and high cutoff frequency low pass filter <NUM> remove the noise in the DPI perturbation that could otherwise cause power switch <NUM> to be turned ON when MPO circuit <NUM> is supposed to be OFF.

<FIG> illustrates a simplified block diagram of components of processing system (which can also be referred to as an integrated circuit) <NUM> in which multi-purpose output circuit <NUM> with improved electromagnetic immunity in accordance with selected embodiments of the present invention can be included. Processing system <NUM> can include one or more bus masters in the form of processor cores <NUM>, <NUM>, <NUM>, other bus masters <NUM> such as direct memory access controllers, one or more levels of cache memory <NUM>, <NUM>, <NUM> associated with one or more of the processor cores <NUM>, <NUM>, <NUM>, interconnect <NUM>, internal memory device <NUM>, peripheral bridge <NUM> coupled to peripherals <NUM>, <NUM>, power management circuit <NUM>, analog I/O circuitry <NUM>, and other components such as network ports (not shown).

Analog I/O circuitry <NUM> can include various components such as power regulators, analog-to-digital converters, reference voltage circuits, input/output buffers and other circuits with electrostatic discharge protection, and fault detection circuit <NUM>. Multipurpose output circuit <NUM> can be included in analog I/O <NUM>. Other suitable components may be included in analog and input/output circuitry <NUM>.

Processing cores <NUM>, <NUM>, <NUM> include computer processor circuitry capable of performing functions that may be implemented as software instructions, hardware circuitry, firmware, or a combination of software, hardware and/or firmware. Operations and functions may be performed under the control of an operating system. One or more instances of software application code may be executed at the same time. Application code being executed by processing cores <NUM>, <NUM>, <NUM> may access data and instructions in memory device <NUM> via interconnect <NUM>. Processing cores <NUM>, <NUM>, <NUM> may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. In addition or in the alternative, processing cores <NUM>, <NUM>, <NUM> may be one or more special-purpose processors such as an application specific integrated circuit (ASIC), a cellular or baseband processor, a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, a graphics processor, a network processor, a communications processor, a cryptographic processor, a co-processor, or an embedded processor. Any other type of bus master logic <NUM>, such as a direct memory access controller, capable of initiating or responding to requests, may also be included in processing system <NUM>.

Processing system <NUM> can also include one or more network ports (not shown) configurable to connect to one or more networks, which may likewise accessible to one or more remote nodes. The remote nodes can include other applications processors, devices or sensors that can exchange information with processing system <NUM>.

Interconnect <NUM> routes requests and responses between bus masters <NUM>, <NUM>, <NUM>, <NUM> and power management circuit <NUM>, peripheral bridge <NUM>, one or more internal memory devices <NUM>, and analog I/O circuitry <NUM>.

Peripheral bridge <NUM> is communicatively coupled to interconnect <NUM>. Peripheral bridge <NUM> can include, for example, circuitry to perform power management, flash management, interconnect management, USB, and other PHY type tasks. A variety of peripheral devices <NUM>, <NUM> such as sensors, field programmable gate arrays, external integrated circuits, a mouse, keyboard, printer, display monitor, external memory drives, cameras, and lights, among others, can be coupled to processing system <NUM> via peripheral bridge <NUM>.

Cache memory devices <NUM>-<NUM> are typically implemented using random-access memory (RAM) and can be used to hold instructions and data that are frequently accessed by a corresponding bus master <NUM>-<NUM>. Information that is no longer used or less frequently used may be swapped out for information that has become more frequently accessed. Cache memory devices <NUM>-<NUM> can have different levels from each other. For example, cache memory devices <NUM> and <NUM> can be level one cache, and cache memory device <NUM> can be a level two cache. Other levels of cache memory can be included. Level one cache is typically faster and smaller in size than level two or three cache.

Internal memory device <NUM> may include one or more volatile storage (or memory) devices such as random-access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of volatile storage devices. In addition or in the alternative, internal memory device <NUM> may include nonvolatile memory, such as read only memory (ROM), electrically erasable programmable ROM, flash memory, magnetic RAM, resistive RAM, write once memory such as fuses, or the like. Additionally, tightly coupled memory may be connected directly to bus masters <NUM>-<NUM> with no connection to interconnect <NUM>, or be connected between a respective one of bus masters <NUM>-<NUM> and interconnect <NUM>, similar to cache memory devices <NUM>-<NUM>. In whatever form, internal memory device <NUM> may store information including sequences of instructions that are executed by the processing device or any other device, information to configure processing system <NUM>, and other data, instructions or information. For example, executable code and/or data, including but not limited to an operating system, device drivers, firmware (e.g., input output basic system or BIOS), and/or applications can be loaded in the memory and executed by processor cores <NUM>, <NUM>, <NUM>.

Power management circuit <NUM> can include a processor core and can send and receive signals to control various operating power modes for bus masters <NUM>-<NUM>, cache memory <NUM>-<NUM>, internal memory <NUM>, analog input/output (I/O) circuitry <NUM>, and peripheral components <NUM>, <NUM> through peripheral bridge <NUM>. The power modes may include normal operation, sleep, or other power saving modes, and power down, as well as to supply proper levels of voltage to various components in processing system <NUM>.

By now it should be appreciated that there has been provided an MPO circuit <NUM> that solves several different problem behaviors with solutions that address frequency dependencies. Two resistors <NUM>, <NUM> are used in both directions to rebalance AC currents between high impedance at the input of driver circuit <NUM> and low impedance at the output of current sources <NUM>. Appropriate values for capacitors <NUM> and <NUM> can be used in medium cutoff frequency low pass filter <NUM> and high cutoff frequency low pass filter <NUM> with different cut off frequencies to filter high frequency noise for current sources <NUM> and medium frequency noise for the input to driver circuit <NUM>. Additionally, a strong pull-down device <NUM> can be used in driver circuit <NUM> to maintain the voltage at the control electrode of power switch <NUM> at 0V when MPO circuit <NUM> is to remain OFF. Further, body diode effects of power switch <NUM> act as a capacitor to help prevent power switch <NUM> from turning ON unintentionally due to DPI perturbation at high frequency above high cutoff frequency filter <NUM>. Note also that MPO circuit <NUM> requires only one power switch <NUM> and one driver circuit <NUM>, thereby allowing the size of MPO circuit <NUM> to be reduced compared to MPO circuits that require two power devices and two driver circuits.

In some embodiments, an integrated circuit can comprise an output terminal, (<NUM>), a power transistor (<NUM>) having a first current electrode coupled to the output terminal and a second current electrode coupled to a power supply terminal (e.g. GND), a driver having an output coupled to a control electrode of the power switch, a capacitor (CSR) having a first terminal coupled to the output terminal and a second terminal coupled to a circuit node, a first low pass filter (<NUM>) coupled between the circuit node and an input of the driver, the first low pass filter having a first cut off frequency, a set of current sources, and a second low pass filter (<NUM>) coupled between the circuit node and an output of the set of current sources, the second low pass filter having a second cut off frequency, higher than the first cut off frequency.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

Although the disclosure has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.

Moreover, the terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Semiconductor and other types of electronic devices are often encapsulated wholly or partly in plastic resin to provide environmental protection and facilitate external connection to the devices. For convenience of explanation and not intended to be limiting, the present invention is described for semiconductor devices, but persons of skill in the art will understand that the present invention applies to any type of electronic device that is substantially in chip form. Accordingly, such other types of devices including the non-limiting examples given below, are intended to be included in the terms "device", "electronic device", "semiconductor device" and "integrated circuit" whether singular or plural, and the terms "device", "die" and "chip" are intended to be substantially equivalent. Non-limiting examples of suitable devices are semiconductor integrated circuits, individual semiconductor devices, piezoelectric devices, magnetostrictive devices, solid state filters, magnetic tunneling structures, integrated passive devices such as capacitors, resistors and inductors, and combinations and arrays of any and all of these types of devices and elements. Further, the present invention does not depend upon the types of die or chips being used nor the materials of which they are constructed provided that such materials withstand the encapsulation process.

Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an.

Claim 1:
An integrated circuit (<NUM>), comprising:
an output terminal (<NUM>);
a power transistor (<NUM>) having a first current electrode coupled to the output terminal (<NUM>) and a second current electrode coupled to a power supply terminal;
a driver (<NUM>) having an output coupled to a control electrode of the power transistor (<NUM>);
a capacitor (<NUM>) having a first terminal coupled to the output terminal (<NUM>) and a second terminal coupled to a circuit node;
a first low pass filter (<NUM>) coupled between the circuit node and an input of the driver (<NUM>), the first low pass filter (<NUM>) having a first cut off frequency;
a set of current sources (<NUM>) having an output; and
a second low pass filter (<NUM>) coupled between the circuit node and the output of the set of current sources, the second low pass filter (<NUM>) having a second cut off frequency, higher than the first cut off frequency.