Patent Description:
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., a light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, or power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, can be produced more efficiently, and have higher performance. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for increasing the density of devices on printed circuit boards and reducing the size of end products. A smaller die size may be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

Semiconductor devices are known to be susceptible to damage from electrostatic discharge (ESD), electrical overstress (EOS), and electrical fast transients (EFT), collectively referred to as ESD events. When electrostatic charges accumulate on a human body for instance, a high static potential is formed with respect to ground. If the human body electrically contacts a semiconductor device, the static potential of the human body discharges an electrical current through the semiconductor device, which can damage the active and passive circuits of the semiconductor device given a sufficiently large electrical current. If a breakdown voltage of an individual circuit element is exceeded, then the semiconductor device can be rendered defective well before its useful life expectancy.

Semiconductor devices may contain a protection circuit for ESD events. The protection circuit has limited capability to discharge the current from the ESD event. To increase the protection capability, the semiconductor package is typically made larger to include more die area and handle a higher electric current. However, increasing semiconductor package size is inconsistent with the goal of smaller packages and end products. Many applications simply do not allow for larger semiconductor packages, even in situations that require greater ESD protection. <CIT> discloses a semiconductor device having through-silicon vias for high current, high frequency and heat dissipation. The device includes a semiconductor chip encapsulated in a protective compound and a two-dimensional area array of contact pads. At least some vias are formed as electronically shielded vias suitable to transmit high frequency signals. Some vias are designed with short traces to circuit inputs/outputs to effectively discharge to ground potential any electrostatic overcharge and overstress events. Any place along its extension and especially the top chip surface (actually the surface of the protective overcoat), a via has one or more connections or routing traces (preferably copper) to one or more particular transistors or other circuit components. Traces may be direct connections, or they may be connections by detours using other chip metallization levels. On the bottom chip surface, via may have a metal terminal (preferably copper with a bondable surface) together with a metal stud. At least some vias may be formed as electrically shielded vias suitable to transmit high frequency signals. In addition, some vias may be designed with short traces to circuit inputs/outputs to effectively discharge to ground potential any electrostatic overcharge in overstress events. The electrical path from the second pad surface through stud, the via, and the connection to the transistor has minimum electrical resistance and inductance for electrical power and ground potential, and minimum thermal resistance for heat dissipation. Further, the path offers itself to effective discharge of electrostatic overcharge to ground potential. On the other hand, when the vias are electrical shielded, the path from the second pad surface through the stud, via, and connection offers itself the high frequency signal transmission. An encapsulation compound covers the chip, the wire connections, and the first pad surfaces. The aligned vias are interconnected by metal studs. The stacked chips, the bonding wires, and the top surface of pads are protected by encapsulation compound. <CIT> discloses an electrostatic discharge protection for three dimensional integrated circuits. <CIT> discloses a stacked semiconductor device including ESD protection circuits.

It is therefore the object of the present invention to provide an improved method of making an electrostatic discharge protection semiconductor package and a corresponding semiconductor device.

The examples in the following detailed description are useful for understanding the present invention. The present invention is defined by the subject matter of the claims but not by the following examples unless expressly presented as an embodiment of the present invention.

The present invention is described in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, those skilled in the art will appreciate that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and the claims' equivalents as supported by the following disclosure and drawings.

<FIG> illustrates electronic device <NUM> having a chip carrier substrate or PCB <NUM> with a plurality of semiconductor packages mounted on a surface of PCB <NUM>. Electronic device <NUM> can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in <FIG> for purposes of illustration.

Electronic device <NUM> can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device <NUM> can be a subcomponent of a larger system. For example, electronic device <NUM> can be part of a tablet, cellular phone, digital camera, or other electronic device. Alternatively, electronic device <NUM> can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), microelectromechanical systems (MEMS), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

In <FIG>, PCB <NUM> provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces <NUM> are formed over a surface or within layers of PCB <NUM> using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces <NUM> provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces <NUM> also provide power and ground connections to each of the semiconductor packages.

<FIG> shows a semiconductor wafer <NUM> with a base substrate material <NUM>, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support. A plurality of semiconductor die or components <NUM> is formed on wafer <NUM> separated by a non-active, inter-die wafer area or saw street <NUM> as described above. Saw street <NUM> provides cutting areas to singulate semiconductor wafer <NUM> into individual semiconductor die <NUM>. In one embodiment, semiconductor wafer <NUM> has a width or diameter of <NUM>-<NUM> millimeters (mm) and thickness of <NUM> micrometers (µm). In another embodiment, semiconductor wafer <NUM> has a width or diameter of <NUM>-<NUM>.

<FIG> shows a cross-sectional view of a portion of semiconductor wafer <NUM>. Each semiconductor die <NUM> has a back or non-active surface <NUM> and an active surface <NUM> containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. Semiconductor wafer <NUM> has a high resistivity, on the order of <NUM> ohms/cm or greater. Active surface <NUM> can be implanted with oxide to suppress surface conduction.

A plurality of blind vias is formed partially through base substrate material <NUM> using laser drilling, mechanical drilling, deep reactive ion etching (DRIE), or other suitable process. The through vias are filled with aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction vertical interconnect structures or conductive through silicon vias (TSV) <NUM>.

An electrically conductive layer <NUM> is formed over active surface <NUM> using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer <NUM> includes a surface coplanar with active surface <NUM>. In another example, conductive layer <NUM> is formed partially or completely over active surface <NUM>.

Conductive layer <NUM> includes one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material or combination thereof. Conductive layer <NUM> operates as contact pads electrically connected to the circuits on active surface <NUM>, as well as conductive TSV <NUM>. Conductive layer <NUM> is formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die <NUM>, as shown in <FIG>. Alternatively, conductive layer <NUM> is formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die. In an embodiment of the invention according to the claims, semiconductor die <NUM> is a discrete transient voltage suppression (TVS) diode, and only two contact pads <NUM> are provided for the two diode terminals.

Portions of conductive layer <NUM> are electrically common or electrically isolated depending on the routing design and function of semiconductor die <NUM>. In some examples, conductive layer <NUM> operates as a redistribution layer (RDL) to extend electrical connection from conductive TSV <NUM> and laterally redistribute electrical signals to other areas of semiconductor die <NUM>. In another example, conductive layer <NUM> operates as a wire bondable pad or layer for electrical interconnection to and from conductive TSV <NUM>.

In <FIG>, back surface <NUM> of semiconductor wafer <NUM> undergoes a backgrinding operation with grinder <NUM> or other suitable mechanical, chemical, or etching process to remove a portion of base material <NUM>. The backgrinding operation reduces the thickness of semiconductor wafer <NUM> including semiconductor die <NUM> and reveals conductive TSV <NUM>. In one example, semiconductor die has a post-grinding thickness of <NUM>-<NUM>. After the backgrinding operation, TSV <NUM> include surfaces coplanar with the new back surface <NUM> of semiconductor die <NUM>.

In <FIG>, an electrically conductive bump material is deposited over conductive layer <NUM> using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material includes Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer <NUM> using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps <NUM>. In some applications, bumps <NUM> are reflowed a second time to improve electrical contact to conductive layer <NUM>. The bumps can also be compression bonded to conductive layer <NUM>. Bumps <NUM> represent one type of interconnect structure that is formed over conductive layer <NUM>. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect. Bumps <NUM> or other interconnect structures are optional and can be formed after singulation of semiconductor wafer <NUM>.

In <FIG>, semiconductor wafer <NUM> is singulated through saw street <NUM> using a saw blade or laser cutting tool <NUM> into individual semiconductor die <NUM>. In another example, semiconductor wafer <NUM> is singulated into individual semiconductor die <NUM> using DRIE.

Semiconductor die <NUM> operates with semiconductor packages <NUM>-<NUM> on PCB <NUM> to provide protection from an ESD event. When electrostatic charge accumulates on a human body, a high static voltage potential is formed with respect to ground. If the human body electrically contacts the semiconductor device, the static potential injects large currents and discharges through the device, which can damage the active and passive circuits on the device.

In one example not included in the claims, semiconductor die <NUM> is dedicated to ESD protection. For example, semiconductor die <NUM> includes one or more transistors, diodes, and other circuit elements formed within active surface <NUM> to implement an ESD protection circuit, which provides fifty amps or more of peak current discharge or dissipation. In an embodiment of the invention according to the claims, each semiconductor die <NUM> is a discrete TVS diode that conducts electricity from terminal 140a to terminal 140b when a voltage across the terminals exceeds a threshold. When the voltage potential across terminals 140a and 140b is below the threshold, the TVS diode of semiconductor die <NUM> approximates an open circuit between the terminals.

<FIG> shows TVS diode or protection circuit <NUM> of semiconductor die <NUM>. An input of protection circuit <NUM> is commonly coupled to conductive layer 134a, conductive TSV 132a, and bump 140a. An output of protection circuit <NUM> is commonly coupled to conductive layer 134b, conductive TSV 132b, and bump 140b. Bump 140a of semiconductor die <NUM> is connected to a circuit node on PCB <NUM>, common with one or more semiconductor packages <NUM>-<NUM>, on which the ESD event may occur. Bump 140b is coupled to a ground potential node.

In normal operation with say <NUM> volts, protection circuit <NUM> is non-active and electrical signals flow to semiconductor packages <NUM>-<NUM> on PCB <NUM>. During an ESD event, a voltage spike or transient condition on the circuit node of PCB <NUM> is also incident to bump 140a and activates protection circuit <NUM> (or turns on TVS <NUM>). When activated, protection circuit <NUM> discharges the current spike associated with the ESD event through conductive layer 134b and bump 140b to ground. For example, the ESD event could be caused by a human body containing an electrostatic charge contacting one or more semiconductor packages <NUM>-<NUM> on PCB <NUM>. Protection circuit <NUM> detects the resulting voltage transient at bump 140a and discharges the high current through semiconductor die <NUM> to ground.

Protection circuit <NUM> can be implemented with a voltage clamping circuit connected to bump 140a and containing one or more transistors with sufficient rating to discharge or dissipate a large ESD current of <NUM> amps or more. Semiconductor packages <NUM>-<NUM> are protected from the ESD event by electrical current being shunted through semiconductor die <NUM> rather than through the packages on PCB <NUM>. Other bumps <NUM> of other semiconductor die <NUM> are connected to other circuit nodes on PCB <NUM> that are susceptible to an ESD event.

The space available on PCB <NUM> for ESD protection is limited. <FIG> illustrates a device with increased ESD current discharge capability and a small semiconductor package size. As described in <FIG>, semiconductor die <NUM> undergo backgrinding to reduce die thickness. A plurality of semiconductor die <NUM> are stacked on substrate or leadframe <NUM> to form semiconductor package <NUM>. Semiconductor die 124c, as singulated from semiconductor wafer <NUM> in <FIG>, is disposed over leadframe <NUM> with bumps <NUM> bonded to terminals 160a and 160b. Bumps <NUM> of semiconductor die 124c are within a footprint of an individual leadframe contact 160a and 160b, and between an individual leadframe contact and semiconductor die 124c. Bumps <NUM> of semiconductor die 124c are reflowed to mechanically and electrically couple semiconductor die 124c to leadframe <NUM> through the bumps.

Semiconductor die 124b, as also singulated from semiconductor wafer <NUM>, is disposed over semiconductor die 124c with bumps <NUM> of semiconductor die 124b bonded to conductive TSV <NUM> of semiconductor die 124c. Semiconductor die 124a, as singulated from semiconductor wafer <NUM>, is disposed over semiconductor die 124b with bumps <NUM> of semiconductor die 124a bonded to conductive TSV <NUM> of semiconductor die 124b. Accordingly, semiconductor die 124a-124c are stacked and electrically connected in parallel between leadframe contacts 160a and 160b through the interconnect structure comprising conductive layer <NUM>, conductive TSVs <NUM>, and bumps <NUM>. While each active surface <NUM> of each semiconductor die <NUM> is oriented in a common directions, many TVS diode embodiments are symmetrical and may be stacked face-to-face or back-to-back at the die or wafer level.

The interconnect structure between semiconductor die 124a-124c can also be implemented with wire bonds, stud bumps, conductive paste, direct die attach, or other electrical interconnect structures. For example, protection circuit <NUM> in each semiconductor die 124a-124c are commonly connected with wire bonds. Alternatively, the thickness of semiconductor package <NUM> can be further reduced by bonding conductive layer 134a of semiconductor die 124c directly to terminals 160a-160b, i.e., without bumps <NUM>. Conductive layer 134a of semiconductor die 124b is bonded directly to conductive TSV 132a of semiconductor die 124c, and conductive layer 134a of semiconductor die 124a is bonded directly to conductive TSV 132a of semiconductor die 124b. Direct metal-to-metal bonding of contact pads 134a to terminals 160a-160b, or to conductive vias <NUM>, is done using thermocompression bonding on one embodiment.

An encapsulant or molding compound <NUM> is deposited over semiconductor die 124a-124c and leadframe <NUM> as an insulating material using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant <NUM> includes polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with proper filler. Encapsulant <NUM> is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

<FIG> illustrates semiconductor package <NUM> with protection circuits <NUM> coupled between input terminals <NUM>-<NUM> and a load circuit <NUM> to protect the load circuit from ESD events on input terminals <NUM>. Load circuit <NUM> represents semiconductor packages or other electrical circuits of electronic device <NUM> for which ESD protection is desired. Input terminals <NUM>-<NUM> represent electrical power and ground inputs to electronic device <NUM>. In other examples, input terminals <NUM>-<NUM> represent analog or digital inputs or outputs of electronic device <NUM>, e.g., a headphone jack or universal serial bus port of a cell phone or tablet computer. Semiconductor package <NUM> is coupled between input terminal <NUM> and input terminal <NUM>, which operates as a ground node for signal transmission.

In normal operation with a voltage of say <NUM> volts, protection circuits <NUM> on semiconductor die 124a-124c are non-active and electrical signals flow to semiconductor packages <NUM>-<NUM> on PCB <NUM>. The electrical signals to semiconductor packages <NUM>-<NUM> are coupled to package <NUM> so that, during an ESD event, a voltage spike or transient condition on a circuit node of PCB <NUM> is also incident on bump 140a. With the die stacking and common interconnect structure for protection circuits <NUM> on semiconductor die 124a-124c, the voltage spike is simultaneously incident on conductive layer 134a and conductive TSV 132a of each semiconductor die 124a-124c.

Protection circuits <NUM> on each semiconductor die 124a-124c are coupled in parallel between an electrical signal and a ground voltage node. Each semiconductor die <NUM> senses the voltage transient condition simultaneously and activates to collectively discharge electrical charge from the ESD event as a relatively high electrical current through conductive layer 134b, conductive TSVs 132b, and bumps 140b to ground. For example, the ESD event could be caused by a human body containing an electrostatic charge contacting one or more semiconductor packages <NUM>-<NUM> on PCB <NUM>. Protection circuits <NUM> on semiconductor die 124a-124c detect or are activated by the resulting voltage spike and discharge electric current through conductive layer 134b, conductive TSVs 132b, and bumps 140b to ground.

In embodiments where semiconductor die <NUM> contain a discrete TVS diode, the ESD event exceeds the turn-on voltage of the TVS diodes of each semiconductor die coupled in parallel. Electrical current from the ESD event is routed through each semiconductor die <NUM> in parallel to a ground voltage node. Semiconductor packages <NUM>-<NUM> are thus isolated from the ESD event. Multiple semiconductor packages <NUM> can be used to couple multiple ESD sensitive circuit nodes on PCB <NUM> to ground when an ESD event occurs on the particular node.

The stacked nature and common electrical connection of protection circuits <NUM> on semiconductor die 124a-124c increases the ESD protection capability of semiconductor package <NUM> without a significant increase in the package footprint. Electrically connecting multiple semiconductor die <NUM> in parallel within package <NUM> causes electric current from an ESD event to be routed through any number of parallel protection circuits <NUM>. While a single protection circuit <NUM> may only be rated to route say one-hundred milliamps of current, connecting three semiconductor die <NUM> in parallel within package <NUM> creates a package that can handle three times the current, or up to three-hundred milliamps.

The increased ESD protection capability is thanks to the parallel semiconductor die <NUM> distributing the high ESD current among the multiple protection circuits <NUM> of the stacked semiconductor die. Protection circuits <NUM> on the stacked semiconductor die 124a-124c operate collectively to increase the total silicon surface area allocated for discharge or dissipation of the ESD current spike through conductive layer 134b, conductive TSVs 132b, and bumps 140b to ground. The increase in current-handling capability occurs without a significant increase in package footprint because the additional current-handling capability is provided by additional semiconductor die <NUM> stacked within the same footprint as other semiconductor die.

Semiconductor package <NUM> in <FIG> contains three stacked semiconductor die 124a-124c, each having a protection circuit <NUM> commonly connected through the interconnect structures comprising conductive layer <NUM>, conductive TSVs <NUM>, and bumps <NUM>. The high ESD protection capability for semiconductor package <NUM> is achieved in a small package size by nature of minimizing the thickness of semiconductor die 124a-124c, as described in <FIG>, and then stacking the thinned semiconductor die, as shown in <FIG>. In one example, the length and width dimensions of each semiconductor die <NUM> is <NUM> x <NUM> with a thickness of <NUM>-<NUM>. The number of stacked semiconductor die <NUM> in semiconductor package <NUM> can vary depending on the protection requirements. Semiconductor package <NUM> can contain as many semiconductor die <NUM> stacked and electrically coupled in parallel as practical and necessary to realize the target ESD protection capability, e.g., <NUM>-<NUM> stacked semiconductor die are used in some examples.

In addition to protection circuit <NUM>, active surface <NUM> may include analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. In one example, active surface <NUM> contains a MEMS, such as an accelerometer, gyroscope, strain gauge, microphone, or other sensor responsive to various external stimuli. Semiconductor die <NUM> may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for signal processing or conditioning.

<FIG> illustrate another examples with the singulated semiconductor die <NUM> from <FIG> mounted over semiconductor die <NUM> of semiconductor wafer <NUM>. Semiconductor wafer <NUM> follows a similar construction as semiconductor wafer <NUM>. Conductive layer <NUM>, conductive TSV <NUM>, and bumps <NUM> are formed for semiconductor die <NUM>, similar to <FIG>. Semiconductor die <NUM> and <NUM> each contain protection circuit <NUM>, e.g., a TVS diode. In <FIG>, after backgrinding semiconductor wafer <NUM>, similar to <FIG>, semiconductor die <NUM> are picked and placed in alignment with corresponding semiconductor die <NUM>. Bumps <NUM> of semiconductor die <NUM> are bonded to conductive TSV <NUM> in semiconductor die <NUM>.

In <FIG>, semiconductor wafer <NUM> is singulated using a saw blade or laser cutting tool <NUM> into individual stacks of semiconductor die <NUM> and <NUM>. <FIG> shows semiconductor package <NUM> with stacked semiconductor die <NUM> and <NUM> mounted to substrate or leadframe <NUM> and covered with encapsulant <NUM>, similar to <FIG>. Semiconductor package <NUM> provides increased ESD protection capability, due to a plurality of protection circuits <NUM> coupled in parallel in a small semiconductor package as described for semiconductor package <NUM>.

<FIG> illustrate another embodiment with semiconductor wafer <NUM> mounted over semiconductor wafer <NUM>. Semiconductor wafer <NUM> and <NUM> follow a similar construction as semiconductor wafer <NUM>. Conductive layer <NUM>, conductive TSV <NUM>, and bumps <NUM> are formed for semiconductor die <NUM>, similar to <FIG>. Likewise, conductive layer <NUM>, conductive TSV <NUM>, and bumps <NUM> are formed for semiconductor die <NUM>. Semiconductor die <NUM> and <NUM> each contain protection circuit <NUM>. In <FIG>, after backgrinding semiconductor wafers <NUM> and <NUM>, similar to <FIG>, semiconductor wafer <NUM> is mounted to semiconductor wafer <NUM> with semiconductor die <NUM> aligned to semiconductor die <NUM>. Bumps <NUM> of semiconductor die <NUM> are bonded to conductive TSV <NUM> in semiconductor die <NUM>.

In <FIG>, semiconductor wafers <NUM> and <NUM> are singulated using a saw blade or laser cutting tool <NUM> into individual stacked semiconductor die <NUM> and <NUM>. <FIG> shows semiconductor package <NUM> with stacked semiconductor die <NUM> and <NUM> mounted to substrate or leadframe <NUM> and covered with encapsulant <NUM>, similar to <FIG>. Semiconductor package <NUM> provides high ESD protection capability, as described for semiconductor package <NUM>, in a small semiconductor package.

<FIG> illustrate wafer-to-wafer bonding of protection devices, while <FIG> illustrate die-to-wafer bonding. In some examples, wafer-to-wafer bonding is combinable with die-to-wafer bonding. For instance, semiconductor die <NUM> from <FIG> can be bonded over semiconductor wafer <NUM> in <FIG> before or after semiconductor wafer <NUM> is bonded to semiconductor wafer <NUM>.

<FIG> illustrate forming a conductive layer <NUM> over back surface <NUM> of semiconductor die <NUM> after backgrinding semiconductor wafer <NUM> in <FIG>. In <FIG>, conductive layer <NUM> forms contact pads over each conductive via <NUM> for improved bonding of bumps <NUM> to back surface <NUM> of the semiconductor die. In other examples, conductive layer <NUM> includes conductive traces for redistribution of electrical signals to alternative locations on back surface <NUM>. Conductive layer <NUM> is formed in a similar manner to conductive layer <NUM>.

In <FIG>, an optional insulating or passivation layer <NUM> is formed over back surface <NUM> around conductive layer <NUM>. Insulating layer <NUM> is formed using PVD, CVD, printing, lamination, spin coating or spray coating. Insulating layer <NUM> contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (Al203), solder resist, or other material having similar insulating and structural properties. A portion of insulating layer <NUM> is removed by etching or laser direct ablation (LDA) to form openings in the insulating layer and expose conductive layer <NUM> for subsequent electrical interconnect. In some examples, a portion of insulating layer <NUM> is removed by backgrinding to expose conductive layer <NUM> from the insulating layer and create a surface of the insulating layer that is coplanar with a surface of the conductive layer.

In <FIG>, a plurality of conductive wafers <NUM> with conductive layer <NUM> are stacked and connected through conductive bumps <NUM>. Conductive bumps <NUM> are reflowed between contact pads <NUM> of one semiconductor wafer <NUM> and contact pads <NUM> of a second semiconductor wafer to mechanically bond and electrically couple the wafers to each other. Any desired number of semiconductor wafers <NUM> can be stacked and connected in parallel. The semiconductor wafers <NUM> are then singulated into individual devices by saw blade or laser cutting tool <NUM>. Semiconductor die <NUM> with conductive layer <NUM> can also be stacked die-to-die after singulating or die-to-wafer.

The singulated units of stacked semiconductor die <NUM> singulated in <FIG> are disposed over leadframe <NUM> and connected to contacts 160a-160b through bumps <NUM> of semiconductor die 124b in <FIG>. Encapsulant <NUM> is deposited over leadframe <NUM> and semiconductor die <NUM> for electrical isolation and environmental protection. Semiconductor die 124a and 124b are coupled in parallel between terminals 160a and 160b. Generally, leadframe <NUM> is provided as a relatively large sheet and many units of stacked semiconductor die <NUM> are disposed over a single leadframe and encapsulated together. Encapsulant <NUM> extends between each semiconductor die <NUM> and between leadframe <NUM> and semiconductor die 124b. Leadframe <NUM> is normally on a carrier while encapsulant <NUM> is deposited, resulting in a lower surface of encapsulant <NUM> that is coplanar with the bottom of leadframe <NUM>.

After encapsulation, the plurality of TVS packages <NUM> are singulated through leadframe <NUM> and encapsulant <NUM> to separate the individual packages. Singulation cuts through leadframe <NUM> and creates new side surfaces or flanks of terminals 160a-160b that are exposed from encapsulant <NUM>. TVS package <NUM> is disposed on PCB <NUM> in <FIG>, and terminals 160a and 160b are soldered to conductive pads or traces on the PCB to protect a circuit element from ESD events. The exposed side surfaces of terminals 160a-160b are wettable by solder and increase the surface area for solder between TVS package <NUM> and PCB <NUM>.

<FIG> illustrate stacking a plurality of semiconductor wafers <NUM> with the wafers mechanically and electrically connected to each other by thermocompression or diffusion bonding. <FIG> illustrates wafer <NUM> with contact pads <NUM> and without conductive bumps <NUM> or insulating layer <NUM>. In <FIG>, a plurality of wafers <NUM> from <FIG> are stacked between a bottom plate <NUM> and a top plate <NUM> of a thermocompression fixture. Plates <NUM> and <NUM> are used to apply force and heat to semiconductor wafers <NUM>. The heat and pressure between contact pads <NUM> and contact pads <NUM> causes metal atoms within aligned contact pads to diffuse into each other.

After wafers <NUM> are bonded together by thermocompression, the stacked wafers are singulated and mounted onto leadframe <NUM> using conductive bumps <NUM>. The stacked semiconductor die <NUM> are coupled to leadframe <NUM> by thermocompression without conductive bumps <NUM> in other examples. Thermocompression of wafers <NUM> to leadframe <NUM> can be in a common thermocompression step with the bonding of wafers <NUM> to each other, or performed as another thermocompression step. Thermocompression can be wafer-to-wafer, die-to-wafer, or die-to-die. Encapsulant <NUM> is deposited over semiconductor die <NUM> and leadframe <NUM> to form a panel, and then the panel is singulated to separate TVS packages <NUM> from each other. Using thermocompression bonding reduces the overall thickness of TVS package <NUM> by eliminating the thickness of conductive bumps <NUM> between some or all device layers.

<FIG> illustrates another example with leadframe <NUM> having a die pad <NUM> in addition to leads <NUM>. Any of the previously disclosed semiconductor die stacks are disposed on die pad <NUM> with an optional adhesive layer <NUM>. Stacks of semiconductor die <NUM> can be disposed over die pad <NUM> with active surfaces <NUM> oriented either toward or away from the die pad. In some examples, active surfaces <NUM> of semiconductor die <NUM> are oriented in opposite directions. Adhesive layer <NUM> provides electrical isolation between semiconductor die <NUM> and die pad <NUM> in examples where desired. Contact pads <NUM> or <NUM>, depending on the orientation of the top semiconductor die <NUM>, are coupled to leads <NUM> by bond wires <NUM>. Bond wires <NUM> are mechanically and electrically coupled to contact pads <NUM> and terminals <NUM> by thermocompression bonding, ultrasonic bonding, wedge bonding, stitch bonding, ball bonding, or other suitable bonding technique. Bond wires <NUM> include a conductive material such as Cu, Al, Au, Ag, a combination thereof, or another suitable conductive material.

Encapsulant <NUM> is deposited over semiconductor die <NUM>, leadframe <NUM>, and bond wires <NUM> to form a sheet of encapsulated devices. The sheet is singulated by a saw blade or laser cutting tool to produce individual TVS devices <NUM>. TVS device <NUM> increases protection capability by coupling a plurality of thinned protection devices in parallel without significantly increasing device size.

Claim 1:
A method of making an electrostatic discharge protection semiconductor package, comprising:
providing a first semiconductor die (124c) including a first protection circuit (<NUM>), wherein the first semiconductor die is a first discrete transient voltage suppression, TVS, diode with only two contact pads;
disposing a second semiconductor die (124b) including a second protection circuit (<NUM>) over the first semiconductor die with a first conductive via (132a) of the first semiconductor die aligned to a second conductive via (132a) of the second semiconductor die, wherein the second semiconductor die is a second discrete TVS diode with only two contact pads;
providing an interconnect structure (140a) between the first conductive via and second conductive via;
disposing the first semiconductor die and second semiconductor die over a leadframe with the first protection circuit and second protection circuit electrically coupled in parallel between a first terminal (160a) of the leadframe and a second terminal (160b) of the leadframe; and
depositing an encapsulant (<NUM>) over the first semiconductor die and the second semiconductor die with the first terminal and second terminal exposed from the encapsulant;
wherein the electrostatic discharge protection semiconductor package is configured to protect a separate semiconductor package from electrostatic discharge events using both the first protection circuit and second protection circuit in parallel.