Patent Description:
Transistor packages are widely used as electronic switches in a variety of electronic circuits. Higher efficiency, increased power density, lower switching losses, faster switching times, lower device parasitics and lower cost are among the key goals for next generation transistor package design.

The transistor switching performance is limited by parasitic elements from the transistor package and the board. In particular, the parasitic common source inductance causes switching losses.

Conventional approaches to reduce device parasitics for fast switching and to improve thermal behavior are to use leadless packages and/or to use clips for connecting the load electrodes of a semiconductor transistor chip to the respective terminals of the transistor package.

Existing package solutions use an additional pin for a source Kelvin connection as a reference potential for the gate driving voltage. However, the presence of a source Kelvin pin and source Kelvin connection degrades the package inductance and package resistance.

Document <CIT> discloses the preamble of independent claim <NUM>.

According to an aspect of the disclosure, a transistor package for a power transistor chip includes the power transistor chip having a first side and a second side opposite the first side. The first side comprises a source electrode metallization, a drain electrode metallization and a gate electrode metallization. The package further includes a multi-layer laminate substrate to which the power transistor chip is connected. The multi-layer laminate substrate comprises a first structured metal layer facing the first side of the power transistor chip and being electrically connected to the source electrode metallization, the drain electrode metallization and the gate electrode metallization, a second structured metal layer comprising a source package terminal pad, a source sense package terminal pad, a drain package terminal pad and a gate package terminal pad, at least one insulating layer disposed between the first structured metal layer and the second structured metal layer, and a plurality of vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer. The first structured metal layer, the second structured metal layer and the plurality of vias are designed such that a gate-source current path between the power transistor chip and the source sense package terminal pad is provided only on one of the first and second structured metal layers while a drain-source current path between the source electrode metallization of the power transistor chip and the source package terminal pad is at least on the other structured metal layer of the multi-layer laminate substrate.

In the drawings, like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other and/or can be selectively omitted if not described to be necessarily required. Embodiments are depicted in the drawings and are exemplarily detailed in the description which follows.

As used in this specification, the terms "electrically connected" or "electrically coupled" or similar terms are not meant to mean that the elements are directly contacted together; intervening elements may be provided between the "electrically connected" or "electrically coupled" elements, respectively. However, in accordance with the disclosure, the above-mentioned and similar terms may, optionally, also have the specific meaning that the elements are directly contacted together, i.e. that no intervening elements are provided between the "electrically connected" or "electrically coupled" elements, respectively.

Further, the words "over" or "beneath" with regard to a part, element or material layer formed or located or arranged "over" or "beneath" a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) "directly on" or "directly under", e.g. in direct contact with, the implied surface. The word "over" or "beneath" used with regard to a part, element or material layer formed or located or arranged "over" or "beneath" a surface may, however, either be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) "indirectly on" or "indirectly under" the implied surface, with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer.

Referring to <FIG>, a transistor package <NUM> includes a power transistor chip <NUM>. The power transistor chip <NUM> has a first side (not visible in <FIG>) and a second side 120B opposite the first side.

The semiconductor transistor chip <NUM> is a lateral device, i.e. the first side comprises a source electrode metallization, a drain electrode metallization and a gate electrode metallization. The metallizations are all disposed on the same (first) side of the semiconductor transistor chip <NUM>. In other words, the lateral semiconductor transistor chip <NUM> is implemented in the transistor package <NUM> in a flip-chip orientation.

The power transistor chip <NUM> may be, e.g., capable of switching high currents and/or medium or high voltages (e.g. more than <NUM> V or <NUM> V or <NUM> V or <NUM> V blocking voltage). In particular, exemplary transistor packages as disclosed herein may operate in the medium voltage (MV) range, in which the blocking voltage is equal to or greater than or less than <NUM> V or <NUM> V or <NUM> V or <NUM> V.

The power transistor chip <NUM> may be of different types. Examples described herein are, in particular, directed, e.g., to HEMT (high electron mobility transistor) devices. More specifically, the semiconductor transistor chip <NUM> referred to herein may, e.g., be a III-V compound semiconductor chip having, e.g., a high band gap. The power transistor chip <NUM> may, e.g., be a GaN chip. In this case, the GaN chip <NUM> may be a lateral GaN-on-substrate device such as a GaN-on-Si device or a GaN-on-SiC device or a GaN-on-sapphire device, for example.

The transistor package <NUM> may include a multi-layer laminate substrate (will be described further below) to which the power transistor chip <NUM> is connected (e.g. mounted).

The source, drain and gate electrode metallizations of the power transistor chip <NUM> are connected via a first structured metal layer (will be described further below) of the multi-layer laminate substrate to a second structured metal layer <NUM> of multi-layer laminate substrate. The second structured metal layer <NUM> may be exposed at the bottom of the transistor package <NUM> and includes a source package terminal pad 144_1 also denoted by S, a drain package terminal pad 144_2 also denoted by D, and a gate package terminal pad 144_3 also denoted by G, see, e.g., the exemplary footprints of transistor packages <NUM> shown in <FIG>.

As illustrated in the semi-transparent representation of <FIG>, the power transistor chip <NUM> may be embedded in a mold compound <NUM>. The mold compound <NUM> may cover the multi-layer laminate substrate to which the power transistor chip <NUM> is connected. A periphery of the mold compound <NUM> is denoted by reference sign 180A.

The second structured metal layer <NUM>, providing for the package terminals, further includes a source sense package terminal pad 144_1S also denoted by SS. The source sense package terminal pad 144_1S, which is also referred to as Kelvin sense terminal pad in the art, may, e.g., be implemented either as an separate (insular) package terminal pad (<FIG>) or as a terminal pad which is continuous with the source package terminal 144_1 (<FIG>). As will be described in the following, both variants (<FIG>: separate source sense package terminal pad 144_1S; or <FIG>: integral source sense package terminal pad 144_1S) can be designed to provide low device parasitics and therefore fast switching of transistor packages <NUM> described herein.

<FIG> is a partial plan view illustration a portion of an exemplary layout of source, drain and gate electrode metallizations at the first side 120A of the power transistor <NUM>. The layout is shown from top, i.e. as it would be seen through the power transistor chip <NUM>.

A source electrode metallization 122_1 may include a plurality of source contact pads (S), and a drain electrode metallization 122_2 may include a plurality of drain contact pads (D). Further, a gate electrode metallization 122_3 is provided.

The plurality of source contact pads (S) may, e.g., be arranged in a number of (horizontal) rows parallel to the longitudinal side of the power transistor chip <NUM>. Likewise, the plurality of drain contact pads (D) may be arranged in a number of (horizontal) rows parallel with the rows of the source contact pads (S). In the example shown in <FIG>, the rows of source contact pads (S) and the rows of drain contact pads (D) are interleaved (or alternating). Further, the source contact pads (S) and the drain contact pads D) are offset from each other in the longitudinal (horizontal) direction. The gate electrode metallization 122_3 may be arranged at a corner of the power transistor chip <NUM> and may, e.g., be formed by as single gate contact pad (G).

The contact pad layout at the first side 120A of the power transistor chip <NUM> may, e.g., not include a source sense pad. That is, the multi-layer laminate substrate <NUM> (but, e.g., not an integrated circuitry of the power transistor chip <NUM>) may provide the internal package interconnects between the source contact pads (S) of the power transistor chip <NUM> and the source package terminal pad 144_1 and the source sense package terminal pad 144_1S, respectively, of the transistor package <NUM>.

The (exemplary) layout of the source, drain and gate metallization 122_1, 122_2, 122_3 of the power transistor chip <NUM> apparently needs to be re-routed by a package-internal interconnect in order to provide for a layout of package terminal pads 144_1, 144_2, 144_3 and 144_1S as, e.g., shown in Figures 1A or <FIG>. Re-routing is carried out by the multi-layer laminate substrate <NUM>.

<FIG> illustrate a first example of a multi-layer laminate substrate <NUM>, referred to as multi-layer laminate substrate 140_1 in the following. The multi-layer laminate substrate 140_1 includes a first structured metal layer <NUM>, also referred to as L1 metal, and the second structured metal layer <NUM>, also referred to as L2 metal.

The first structured metal layer <NUM> faces the first side 120A of the power transistor chip <NUM>. The first structured metal layer <NUM> may, e.g., include a multi-finger source segment 142_1, wherein fingers 142_1f of the multi-finger source segment 142_1 are connected to the source contact pads (S) of the source electrode metallization 122_1 of the power transistor chip <NUM>. Further, the first structured metal layer <NUM> may, e.g., include a multi-finger drain segment 142_2 having fingers 142_2f connected to the drain contact pads (D) of the drain electroe metallization 122_2 of the power transistor chip <NUM>. The fingers 142_1f and the fingers 142_2f may, e.g., be interdigitated so as to allow to separately connect to the source contact pads (S) and the drain contact pads (S) at the first side 120A of the power transistor chip <NUM> (see, e.g., <FIG>).

Further, the first structured metal layer <NUM> may include a gate segment 142_3 which connects to the gate contact pad 122_3 of the power transistor chip <NUM>.

It is to be noted that a variety of different layouts of the source (S), drain (D) and gate (G) contact pads of the metallizations 122_1, 122_2, 122_3 at the first side 120A of the power transistor chip <NUM> is possible. Correspondingly, the layout of the first structured metal layer <NUM>, which is adapted to the layout of the source (S), drain (D) and gate (G) contact pads of the metallizations 122_1, 122_2, 122_3 of the power transistor chip <NUM>, may be designed in a variety of different patterns.

In many examples the layout of the first structured metal layer <NUM> is chosen to route the drain and source currents to different (e.g. opposite) sides of the transistor package <NUM>. In the specific example shown in <FIG>, this separation of drain and source current is carried out by the fingers 142_1f, 142_2f of the multi-finger source and drain segments 142_1, 142_2, respectively. To this end, the fingers 142_1f or at least a part thereof (as in the example shown) may be connected to a rail portion 142_1r of the multi-finger source segment 142_1. Likewise, the fingers 142_2f of the multi-finger drain segment 142_2 may be connected to a rail portion 142_2r of the multi-finger drain segment 142_2, wherein the rail portions 142_1r and 142_2r may be located at opposite sides of the transistor package <NUM>.

The rail portions 142_1r and 142_2r may, e.g., be parallel with each other and may, e.g., extend in X-direction. The fingers 142_1f, 142_2f may, e.g., be parallel with each other and may, e.g., extend in Y-direction, which is perpendicular to the X-direction.

<FIG> is a plan view of the second structured metal layer <NUM>. The second structured metal layer <NUM> includes the source (S) package terminal pad 144_1, the drain (D) package terminal pad 144_2 and the gate (G) package terminal pad 144_3. Further, a source sense (SS) package terminal pad 144_1S is provided.

In a first example, the source sense (SS) package terminal pad 144_1S and the source (S) package terminal pad 144_1 are formed by a continuous metal segment of the second structured metal layer <NUM>.

At least one insulating layer <NUM> is disposed between the first structured metal layer <NUM> (L1) and the second structured metal layer <NUM> (L2). A plurality of vias V is running through the insulating layer <NUM>. The vias V connect segments of the first structured metal layer (L1) <NUM> to the terminal pads 144_1, 144_2, 144_3, 144_1S of the second structured metal layer <NUM> (L2). Vias V are indicated in <FIG> by circles.

In <FIG> the drain-source current path DS and the gate-source current path GS are indicated by arrows. The (large) drain-source current is flowing along the drain-source current path DS, while the (small) gate-source current is flowing along the gate-source current path GS.

As apparent from <FIG>, the drain-source current path DS between the source electrode metallization 122_1 of the power transistor chip <NUM> and the source (S) package terminal pad 144_1 flows on (at least) two structured layers of the multi-layer laminate substrate 140_1, namely on the first structured metal layer <NUM> (L1) and on the second structured metal layer <NUM> (L2). On the other hand, the gate-source current path GS between the source electrode metallization 122_1 of the power transistor chip <NUM> and the source sense (SS) package terminal pad 144_1S is provided only on one of the first and second structured metal layers <NUM> (L1), <NUM> (L2), namely on the second structured metal layer <NUM> (L2).

For example, the drain-source current path DS on the first and second structured metal layers <NUM>, <NUM> is in the lateral Y-direction and the gate-source current path GS on the second structured metal layer <NUM> (L2) only is in the lateral X-direction, wherein the lateral Y-direction and the lateral X-direction are different from each other and, e.g., perpendicular to each other.

In other words, while the drain-source current flows on two layers L1, L2 of the transistor package <NUM> in the Y-direction, the gate-source current only flows on one of those two layers (here: layer L2) in the X-direction, thereby partly decoupling the two current paths DS and GS.

Further, the gate segment 142_3 which connects the gate contact metallization 122_3 of the power transistor chip <NUM> through vias V to the gate (G) package terminal pad 144_3 of the transistor package <NUM> may be designed, e.g., to allow the gate (G) package terminal pad 144_3 to be located at a side of the transistor package <NUM> oriented in Y direction (this is also referred to as a "center gate layout"). That is, the source package terminal pad 144_1 may be arranged along a first side of the transistor package <NUM>, the drain package terminal pad 144_2 may be arranged along a second side opposite the first side of the transistor package <NUM> and the gate package terminal pad 144_3 may be arranged at a third side of the transistor package in a region spaced apart from a corner of the first or second side of the transistor package <NUM>.

<FIG> illustrate a second example of a multi-layer laminate substrate <NUM>, referred to as multi-layer laminate substrate 140_2 in the following. The multi-layer laminate substrate 140_2 may be used in a transistor package in accordance with the first variant (see <FIG>). In other words, the source sense (SS) package terminal pad 144_1S and the source (S) package terminal pad 144_1 are formed by separate metal segments of the second structured metal layer <NUM> (L2).

As illustrated in <FIG>, the drain-source current path DS is on the first and second structured metal layers <NUM> (L1) and <NUM> (L2), whereas the gate-source current path GS is only on the first structured metal layer <NUM> (L1). The drain-source current path DS on the first and second structured metal layers <NUM> (L1) and <NUM> (L2) is, e.g., in the lateral Y-direction. The gate-source current path GS on the first structured metal layer <NUM> is also, at least partially, in the Y-direction. Further, gate-source current path GS may be (partially) in the X-direction along the rail 142_1r to a dedicated via dV through which the separate source sense (SS) package terminal pad 144_1S is connected to the first metal layer <NUM> (L1). No drain-source current is flowing through the dedicated via dV.

In other words, in the second example of a transistor package <NUM> the drain-source current flows on two metal layers L1, L2 of the multi-layer laminate substrate <NUM> in the Y-direction, while the gate-source current only flows on one (namely L1) of those two metal layers L1, L2 in (at least partially) the Y-direction and utilizes the dedicated via dV to connect to the insular source sense (SS) package terminal pad 144_1S at the package footprint.

Further, the gate segment 142_3 which connects the gate contact metallization 122_3 of the power transistor chip <NUM> through vias V to the gate (G) package terminal pad 144_3 of the transistor package <NUM> may be, e.g., designed to allow the gate (G) package terminal pad 144_3 to be located at a corner of the transistor package <NUM> (this is also referred to as a "corner gate layout"). For example, the source package terminal pad 144_1 may be arranged along a first side of the transistor package <NUM>, the drain package terminal pad 144_2 may be arranged along a second side opposite the first side of the transistor package <NUM> and the gate package terminal pad 144_3 may be arranged at a corner of the first side of the transistor package <NUM>.

<FIG> illustrate a third example of a transistor package <NUM> which includes a third example of a multi-layer laminate substrate <NUM>, referred to as multi-layer laminate substrate 140_3 in the following. Similar to the multi-layer laminate substrate 140_2, the semiconductor package uses a dedicated via dV connecting to an insular source sense (SS) package terminal pad 144_1S. Differently stated, the source sense (SS) package terminal pad 144_1S and the source (S) package terminal pad 144_1 are formed by separate metal segments of the second structured metal layer <NUM>. However, the third example of a transistor package (<FIG>) distinguishes from the second example (<FIG>) in that the drain-source current path DS is only on the second structured metal layer <NUM> (L2) and the gate-source current path GS is only on the first structured metal layer <NUM> (L1). The multi-layer laminate substrate 140_3 provides fully decoupled drain-source and gate-source current paths DS and GS.

For example, the drain-source current path DS on the second structured metal layer <NUM> (L2) is in the Y-direction, and the gate-source current path GS on the first structured metal layer <NUM> (L1) is also, at least partially, in the Y-direction.

Further, the gate segment 142_3 which connects the gate contact metallization 122_3 of the power transistor chip <NUM> through vias V to the gate (G) package terminal pad 144_3 of the transistor package <NUM> may, e.g., designed to allow the gate (G) package terminal pad 144_3 to be located at a corner of the transistor package <NUM> ("corner gate layout"). Reference is made to the above description of a "corner gate layout" to avoid reiteration.

The various implementations according the first, second and third examples disclosed above are summarized in Table <NUM>.

While examples <NUM> and <NUM> (multi-layer laminate substrates 140_1 and 140_2, respectively) provide for partial decoupling of the drain-source current and the gate-source current, the example <NUM> fully decouples the drain-source current path DS and the gate-source current pat GS. In all examples <NUM> to <NUM> the source sense (SS) terminal pad 144_1S ("Kelvin source pad") for the gate-source current is connected to the power transistor chip <NUM> on only one of the metal layers L1, L2, and the at least one other metal layer L2 or L1, respectively, is used to provide an alternate path for the drain-source current between the source electrode metallization 122_1 of the power transistor chip <NUM> and the (power) source package terminal pad 144_1 of the transistor package <NUM>. Further, it is to be noted that a dedicated via dV can be used either in a partially decoupled implementation (e.g. ex. <NUM>, 140_2) or a fully decoupled implementation (e.g. ex. <NUM>, 140_3). Moreover, center gate or corner gate layouts may be used in any of the implementations as disclosed.

<FIG> is a perspective top view of detail DT of <FIG>. The semi-transparent representation shows the dedicated via dV connecting to the insular source sense (SS) package terminal pad 144_1S (SS). Reference is made to <FIG> and <FIG> in which implementations in line with such footprint layout are presented, for example.

Due to the face-down orientation of the semiconductor transistor chip <NUM>, the transistor packages <NUM> disclosed herein allow to achieve low parasitics for fast switching and high thermal connectivity. In all examples, the array of vias V provides a vertical connection structure of low parasitic inductance in the multi-layer laminate structure <NUM> to connect the source electrode metallization 122_1 of the power transistor chip <NUM> to the source package terminal pad 144_1 of the transistor package <NUM>. In addition, the partially or fully decoupling of the (large) load DS and the (small) source sense GS currents allows to offer a source Kelvin IO pin (i.e. the source sense package terminal pad 144_1S) with minimum parasitic inductance. In particular, a dedicated via dV connecting the source electrode metallization 122_1 of the power transistor chip <NUM> to the source sense (SS) package terminal pad 144_1S of the transistor package <NUM> may improve the switching frequency.

Further, for example given a GaN semiconductor transistor chip <NUM> is used, the face-down orientation of the GaN transistor chip <NUM> in combination with the multi-layer laminate substrate <NUM>, which can be used as a routable base of the transistor package <NUM>, allows to align the transistor package footprint with the footprints of common MOSFET (Metal Oxide Semiconductor Field Effect Transistor) packages which, however, cannot fulfill the fast switching requirements of the transistor package <NUM> described herein.

The multi-layer laminate substrate <NUM> may be represented by a variety of different structures and formed by a variety of different methods of manufacturing. For example, the multi-layer laminate substrate <NUM> may comprise or be a separate PCB (Printed Circuit Board) on which the power transistor chip <NUM> chip is mounted. In other examples, the multi-layer laminate substrate may be generated at wafer level by, e.g., embedded wafer level packaging techniques, also known as eWLP in the art. In eWLP, the transistor packages <NUM> are separated from an "artificial wafer" in which an array of power transistor chips <NUM> is embedded in a continuous mold compound wafer structure.

Claim 1:
A transistor package for a power transistor chip, the transistor package comprising:
the power transistor chip (<NUM>) having a first side (120A) and a second side opposite the first side (120A), the first side (120A) comprising a source electrode metallization (122_1), a drain electrode metallization (122_2) and a gate electrode metallization (122_3); and
a multi-layer laminate substrate (<NUM>) to which the power transistor chip (<NUM>) is connected, the multi-layer laminate substrate (<NUM>) comprising
a first structured metal layer (<NUM>) facing the first side (120A) of the power transistor chip (<NUM>) and being electrically connected to the source electrode metallization (122_1), the drain electrode metallization (122_2) and the gate electrode metallization (122_3);
a second structured metal layer (<NUM>) comprising a source package terminal pad (144_1), a source sense package terminal pad (144_1S), a drain package terminal pad (144_2) and a gate package terminal pad (144_3);
at least one insulating layer (<NUM>) disposed between the first structured metal layer (<NUM>) and the second structured metal layer (<NUM>); and
a plurality of vias (V) running through the insulating layer (<NUM>) and connecting segments of the first structured metal layer (<NUM>) to the terminal pads of the second structured metal layer (<NUM>); characterized in that
the first structured metal layer (<NUM>), the second structured metal layer (<NUM>) and the plurality of vias (V) are designed such that a gate-source current path (GS) between the power transistor chip (<NUM>) and the source sense package terminal pad (144_1S) is provided only on one of the first and second structured metal layers (<NUM>, <NUM>) while a drain-source current path (DS) between the source electrode metallization (122_1) of the power transistor chip (<NUM>) and the source package terminal pad (144_1) is at least on the other structured metal layer of the multi-layer laminate substrate (<NUM>).