Patent Description:
Semiconductor processing for the fabrication of integrated circuit chips continues to evolve towards increasing device-density : higher numbers of active devices (mainly transistors) of ever decreasing device dimensions are placed on a given surface of semiconductor material.

In advanced CMOS devices, electronic circuits are designed and realized as combinations of so-called standard cells : combinations of n- and p-MOS devices organized in rectangular cells bound on two sides by respectively a supply and a reference (usually ground) power supply track, coupled to voltages which are usually labelled Vdd and Vss respectively. These power supply tracks are traditionally connected to metal traces higher in the back end of line metal stack, collecting all the currents from the small pitches at transistor level to the large pitches at power and ground level. With continued device scaling, the resistance of the metal tracks at the standard cell level have become a bottleneck for the power supply, resulting in large voltage drops of the supply current and reducing overall potential device performance.

One known solution to this problem is to use so-called buried power rails. Basically, the tracks used for Vdd and Vss that are typically horizontal (broad & thin) are now realized vertically (narrow/heigh) and recessed ("buried") between the fins or nano-sheets onto which the active devices in advance CMOS standard cells are built.

To further improve the power supply to the devices, it is proposed in patent publication document <CIT> to connect these buried power rails from the back side of the wafer onto which the CMOS processing takes place. After thinning of the wafer, small Through Silicon Via connections (often called "nano"-TSVs) are realized from the thinned wafer backside, contacting the buried power rails. On the back side, parallel power delivery tracks form a pattern of alternating Vdd and Vss-coupled lines with narrow pitch. As the standard cell is expected to scale down to the <NUM> regime, the TSVs have to be realized without contacting adjacent power rails, setting a limit to the width of these TSVs that takes into account the minimal spacing to the neighbouring Vdd or Vss track and the expected overlay tolerance when patterning the TSVs from the wafer backside. At the same time, the TSV width needs to exceed the width of the power rails. However, the area where the TSV is landing on the Vdd and Vss rails cannot be used for placement of regular standard cells. Therefore, to minimize the area overhead of the TSVs, the distance between TSVs contacting the same buried rail is made relatively high, which makes it difficult to decrease the contact resistance between the backside Vdd and Vss metal traces and the buried rails. It is furthermore known that processed wafers exhibit wafer distortions after wafer-to-wafer bonding. This requires extensive use of metrology and litho corrections to result in minimal overlay errors.

Some of the problems of the above-described 'TSV-last' approach have been solved by the method described in patent publication document <CIT>, that describes a 'TSV-first' approach for producing the TSVs. An adequate way of reducing or controlling the contact resistance to the backside Vdd and Vss tracks is however still not available on the basis of this disclosure. Also, wafer distortions are still limiting the overlay tolerance applied when patterning back side power delivery tracks relative to the TSVs.

The invention aims to provide a way of contacting buried interconnect rails that is scalable beyond the above-described limitations. This is achieved by an integrated circuit chip in accordance with the appended claims and by a method for producing the IC chip. An IC chip according to the invention comprises a semiconductor substrate comprising active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to said power rails by a plurality of Through Semiconductor Via connections, TSVs, which run from the power rails to the back of the substrate. According to the invention, the TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and the power delivery track or tracks directly adjacent to said power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. The staggered arrangement of the TSVs enables a more relaxed overlay tolerance in the patterning steps required to form the power delivery tracks on the back side, while still allowing a very dense interconnectivity of the TSVs, thereby also ensuring that a low resistive path is formed from the power supply to the active devices at the front of the substrate.

The invention is also related to a method for producing an IC chip according to the invention, characterised in that the slit-shaped TSVs are produced before the buried power rails, thereby enabling a shorter connection from the TSVs to the active devices.

The invention is in particular related to an integrated circuit chip comprising:.

According to an embodiment, all TSVs of the staggered pattern have essentially the same length, and the distance between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is essentially the same across the staggered pattern.

According to an embodiment, the distance between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is smaller than or equal to the length of the TSVs.

According to an embodiment, the distance between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is essentially equal to the length of the TSVs, and all the power delivery tracks have essentially the same width and are configured by an essentially constant distance between directly adjacent power delivery tracks.

According to an embodiment, the width of the power delivery tracks is essentially equal to the distance between directly adjacent power delivery tracks.

According to an embodiment, the power rails are buried only in said dielectric layer and not in the substrate.

According to an embodiment, the active devices are fin-based devices or nano-sheet based devices and wherein the power rails run parallel to the fins or to the nano-sheets.

According to an embodiment, the power delivery tracks are essentially perpendicular to the buried power rails.

The invention is also related to a method for producing an IC chip according to the invention, the method comprising the steps of :.

According to an embodiment of the method of the invention, the device wafer comprises a base wafer, an etch stop layer on the base wafer, and said semiconductor layer on the etch stop layer, wherein the etch stop function of the etch stop layer is related to stopping an etch process applied during said step of thinning the device wafer.

According to an embodiment of the method of the invention, the power delivery tracks are essentially perpendicular to the power rails.

The enclosed figures are illustrating the main features of the invention. They are not drawn to scale and should not be regarded as technical drawings of real structures.

In the following detailed description, an embodiment of an integrated circuit chip according to the invention is described. The IC chip is produced by processing a CMOS layout of finFET transistors arranged in standard cells on a semiconductor device wafer. However, the invention is not limited to this particular application field. As the invention is related also to a specific method for producing the chip according to the invention, this method is described first on a step-by-step basis, with reference to <FIG>.

<FIG> shows a small portion of a device wafer, comprising a monocrystalline Si layer <NUM>, into which a number of fins <NUM> and <NUM>' have been produced by a known lithography and etch technique, applying etch masks <NUM>. The width of the fins may be in the order of <NUM> or less. The two different types of hatching indicate different doping types (referred to also by respective references <NUM> and <NUM>'), typically p-type and n-type doping. In the embodiment shown, the Si layer <NUM> is a p-type layer, implanted with n-type dopants in consecutive well-areas <NUM>. The well-areas <NUM> reach about half the depth of the Si layer <NUM> but could also reach to the back surface of the Si layer. The image is merely a schematic indication of the fact that adjacent p- and n-areas are created on the device wafer. This layout is typically used for producing pMOS and nMOS transistors arranged in multiple standard cells. In this example, alternate pairs of <NUM> p-type fins <NUM> and <NUM> n-type fins <NUM>' are arranged with equal distances between the fins. This could also be groups of more than <NUM> p-type fins alternating with groups of more than <NUM> n-type fins. In the plane view of <FIG>, it is seen that the fin lengths differ and that the fins are arranged according to a pattern. The pattern shown is a random example of a possible fin pattern.

The Si layer <NUM> is a monocrystalline top layer of a multi-layer device wafer comprising a base wafer <NUM>, typically a Si wafer, and a thin etch stop layer <NUM>, which could be a SiGe layer. The Si layer <NUM> (including the fins) preferably has a thickness less than <NUM>, for example about <NUM>. The etch stop layer <NUM> may be a SiGe layer of about <NUM> thick for example. Its function as an etch stop layer is to stop the etching of the base wafer <NUM> for the removal of said base wafer from the back side, as will be explained later in this description. The SiGe layer <NUM> and the monocrystalline Si layer <NUM> may be produced on a Si base wafer <NUM> by techniques well known in the art, preferably by epitaxial growth methods. An alternative would be to use a silicon-on-insulator (SOI) wafer, wherein the insulator layer plays the part of etch stop layer later in the process. The fins <NUM>, <NUM>' are embedded in a layer <NUM> of dielectric material. Typically, this is a layer of silicon oxide (SiO<NUM>), also referred to as 'shallow trench isolation' oxide. We will hereafter refer to this layer as the STI layer <NUM>.

As shown in <FIG>, a plurality of slits <NUM> is produced through the STI layer <NUM> and through the Si layer <NUM>, stopping in the SiGe layer <NUM>. This is done by lithography and anisotropic etching, using a suitable etch technique known in the art. The slits <NUM> are formed between fins of the same type (n or p) and no slits are formed between any p-type fin and its directly adjacent n-type fin. The slits <NUM> are formed in a staggered pattern : the slits <NUM> formed between the n-type fins <NUM>' are shifted in the longitudinal direction of the slits, with respect to the slits <NUM> formed between the p-type fins <NUM>. This pattern is repeated across a given area of the wafer as illustrated in the plane view in <FIG>.

In the embodiment shown, the etching of the slits <NUM> is stopped inside the SiGe layer <NUM>. The slits <NUM> could also stop at the upper surface of the SiGe layer <NUM>, or be etched fully through the SiGe layer <NUM> and slightly into the base substrate <NUM>. In any case, the slits <NUM> are formed essentially through the complete thickness of the Si layer <NUM>. The width of the slits <NUM> is shown in the drawings to be in the same order of magnitude as the width of the fins <NUM>,<NUM>', but may in reality exceed this width to some degree, whilst remaining in the order of tens of nanometres. Possibly, the spacing between the fins of the same type may be larger than shown in the drawings, to accommodate the processing of the slits <NUM>. The length of the slits <NUM> is considerably higher than the width and may be in the order of several hundreds of nanometres. In the embodiment shown, the spacing between each pair of two aligned slits <NUM> is the same as the length of the slits. It is seen also that in the embodiment shown, two mutually staggered slits <NUM> do not overlap in their length direction. A limited degree of overlap is however allowable as will be described later.

With reference to <FIG>, the slits <NUM> are then filled with an electrically conductive material <NUM>. This involves the deposition of a dielectric liner conformally in the slits <NUM> and possibly a conformal barrier layer before depositing the conductive material, preferably a metal, for example W, Ru or Mo. The conformal layers are not shown in the drawings. Techniques for producing these layers and for filling the slits <NUM> with the conductive material are well known in the art. The upper surface of the wafer is planarized by a suitable technique known in the art such as CMP (chemical mechanical polishing), removing the etch masks <NUM> and exposing the conductive material on the upper surface of the wafer, in the form of a staggered pattern of conductive slit-shaped volumes <NUM>'.

As seen in <FIG>, the volumes <NUM>' are etched back to thereby form reduced volumes <NUM>, which will play the part of the TSV connections in the final IC, so from now on we will refer to them as TSVs <NUM>. The abbreviation TSV is commonly understood as Through Silicon Via, but in the context of the present invention, the term is not limited to silicon, and may be understood as 'Through Semiconductor Via'.

The areas formed above the TSVs <NUM> (and limited in length to the length of the TSVs) are then filled with a dielectric material <NUM>, possibly SiO<NUM>, followed by another planarization step. Then a number of well-known CMOS front end of line process steps is performed, of which the result is illustrated in a simplified way in <FIG>. This is the processing of source or drain (S/D) contacts <NUM> on the fins <NUM>,<NUM>', in accordance with a given layout of standard cells arranged between the TSVs <NUM>. The source or drain contacts <NUM> are schematically drawn on top of the fins. In reality, the STI layer <NUM> is etched back to expose the top of the fins, and the S/D contacts are formed thereon by epitaxial techniques well known in the art. As this technology is known and not the subject of the present invention however, the drawings have been simplified, showing S/D contacts on top of the fins <NUM>,<NUM>' and embedded in a dielectric layer <NUM>. The S/D contacts <NUM> are also visible in the plane view in <FIG>. The depicted distribution of these contacts <NUM> is not intended to represent a realistic layout, and merely illustrates a random arrangement of S/D contacts relative to the fin arrangement.

In a characteristic step of the method according to the invention, buried contact rails <NUM> are now produced, as shown in <FIG>. To this aim, trenches aligned to each line of mutually aligned TSVs <NUM> are first formed by lithography and etching, through the dielectric layers <NUM> and <NUM>, until reaching the top of the TSVs <NUM>. These trenches may be somewhat narrower than the TSVs <NUM>, as illustrated in the drawings. The trenches are filled (possibly after conformal deposition of a dielectric liner and barrier layer) with an electrically conductive material, preferably the same material as used for the TSVs <NUM>. After filling the trenches, the top surface of the wafer is planarized. The result is a set of parallel rails <NUM>, each rail interconnecting a set of TSVs <NUM> which are mutually aligned along their longitudinal direction. The rails <NUM> are destined to become connected alternately to the IC's supply voltage (hereafter referred to as Vdd) and to the reference voltage (hereafter referred to a Vss), so that two adjacent rails <NUM> are configured to supply power to standard cells arranged between a Vdd rail and a Vss rail. The rails are therefore equivalent to the buried power rails described for example in <CIT> and <CIT>, where these rails are however formed prior to the formation of the S/D contacts and extend deeper into the device wafer, being buried in the Si layer <NUM> itself, whereas in the embodiment shown in <FIG>, the rails <NUM> are not buried in the Si layer <NUM>, only in the dielectric materials present between two adjacent fins.

Before or after producing the rails <NUM>, further front end of line processing is performed, including the formation of gates and gate contacts in between pairs of source and drain contacts. These elements are not shown in the drawings but well-known to the skilled reader. The result is the 'front end of line portion' of the IC chip, indicated generally as layer <NUM> in <FIG> and subsequent figures. The '{' is merely an indicative sign of the location of the FEOL portion <NUM>, without meaning to define an exact border. In the FEOL portion <NUM>, the STI layer <NUM> will play the well-known part of isolating active devices from each other.

Then the so-called M0 metal layer is formed, see <FIG>. This is the formation of metal conductors <NUM> which connect some of the source or drain contacts <NUM> to the buried rails <NUM>, in accordance once more with a given standard cell arrangement. As the rails <NUM> are not buried deep in the Si layer <NUM>, the M0 conductors <NUM> may be formed so as to contact the upper surface of the rails <NUM> directly, as shown in the section view of <FIG>, by first planarizing the wafer to expose the S/D contacts <NUM> and the rails <NUM>, followed by a single damascene-type process for producing the conductors <NUM>. This is advantageous compared to the more traditional deep buried rails, which require the formation of a narrow contact via between the rail and the M0 conductor.

After this, as illustrated in <FIG>, the back end of line process is performed, resulting in the BEOL portion <NUM> of the IC. As well-known in the art, this BEOL portion is a stack of interconnects comprising several metallization levels (M1,M2 etc), including a passivation layer on top (not shown). The conductors <NUM> are indicated as part of the front end of line portion <NUM> in the drawings. They could however be regarded as part of the BEOL portion <NUM>. This distinction has no bearing on the characterising features of the present invention.

Back side processing is now performed, after flipping the wafer and bonding it to a carrier wafer <NUM>, preferably applying dielectric bonding layers <NUM> (shown as one bonded layer in the drawings) to the carrier <NUM> and to the BEOL stack <NUM>, as illustrated in <FIG>.

The base wafer <NUM> is removed by a thinning sequence that may comprise etching and/or grinding steps, ending with a highly selective etch step, preferably a wet etch in the case of a SiGe etch stop layer <NUM>, that effectively stops when reaching the SiGe layer <NUM>. Such highly selective etch recipes are well known for the selective etch of Si relative to SiGe as well as for other material combinations. Following this, the etch stop layer <NUM> itself is removed, resulting in the situation illustrated in <FIG>, preferably with the TSVs <NUM> slightly protruding outward from the back surface of the Si layer <NUM>. If necessary, the material of the Si layer <NUM> is slightly recessed in order to obtain this result. The plane view of <FIG> is in this case an actual top view, showing only what is visible on this back surface, namely the staggered pattern of TSVs <NUM>. It is seen that this pattern comprises at least one pair of rows R1 and R2 of TSVs <NUM>, extending in the direction perpendicular to the TSVs <NUM> and the power rails <NUM> and with the TSVs <NUM> of the second row R2 in a staggered position relative to the TSVs of the first row R1, i.e. the two rows comprise mutually staggered TSVs. Most ICs according to the invention will of course comprise many of such 'pairs of a first row and a second row of TSVs'. In the embodiment shown, a next pair of rows R1, R2 (only R1 is shown) follows under the first pair, and so on. In addition, the TSVs of all the 'first rows' R1 are aligned to each other, and the TSVs of all the 'second rows' R2 are aligned to each other and shifted with respect to the first rows by the same distance A indicated in <FIG>, corresponding to the pitch of the array of parallel power rails <NUM>. The length LTSV of the TSVs is preferably the same across the complete pattern.

With reference to <FIG>, a dielectric layer <NUM> (for example an oxide or nitride) is then deposited on the back surface of the Si layer <NUM>, followed by a planarization, exposing the TSVs <NUM>, as illustrated in <FIG>. Finally, as shown in <FIG>, electrically conductive power delivery tracks <NUM> are formed on the back side by a single damascene process, possibly using copper as the material for the tracks <NUM>. The tracks are arranged transversely, in practice this will be essentially perpendicularly, with respect to the TSVs <NUM>. As seen in the drawings, the tracks <NUM> are arranged in pairs T1, T2 of mutually parallel tracks, respectively overlapping and contacting two rows R1, R2 of mutually staggered TSVs.

In the language of appended claim <NUM>, it is thereby seen that the TSVs <NUM> are arranged in a staggered pattern, configured so that any one of the power delivery tracks <NUM> is connected to a first row of mutually parallel TSVs <NUM>, and any power delivery track (<NUM>) directly adjacent to said power delivery track (i.e. the tracks on either side of the first track or on one side only, if the first one is located at the edge of the array of tracks <NUM>) is connected to a second row of mutually parallel TSVs which are staggered relative to the TSVs of the first row, the second row being directly adjacent the first row.

In the finished IC, the tracks <NUM> are alternately coupled to Vdd and Vss, i.e. every T1 coupled to Vdd and every T2 coupled to Vss, to thereby deliver these voltages alternately to the parallel rails <NUM>, and to the standard cells arranged between each pair of rails <NUM>. On top of the tracks <NUM>, further processing is done to produce a full power delivery network on the back side, connected to terminals of the finished IC that are configured to be coupled to external Vdd and Vss supply lines. These processing steps which are similar to BEOL processing are well known and therefore not described here in detail. At the end of the process, the wafer is singulated to form separate IC chips for example by cutting or sawing. The singulated portion of the Si layer <NUM> is then the semiconductor substrate of the chip, indicated by the same reference numeral <NUM> in the appended claims, with active devices mounted on the front surface of the substrate <NUM>, and a power delivery network on the back surface.

The arrangement of the TSVs <NUM> as slit-shaped volumes of length LTSV aligned to the power rails <NUM> in a staggered pattern offers several advantages over the prior art solutions. It is a via-first approach, i.e. etching TSVs from the back side is not applied and the TSVs are aligned to the power rails <NUM>, having a width that is essentially equal to or that only slightly exceeds the width of the power rails <NUM>. This eliminates the problems related to wafer distortion and area overhead, as far as the processing and distribution of TSVs is concerned. In the direction of the rails <NUM>, the distance between two adjacent TSVs can be shortened compared to the TSVs produced by the TSV-last approach, because the area of the TSVs no longer has an influence on the available area for the active devices.

Importantly, the staggered pattern allows to combine a dense front side metal grid (power rails <NUM> close together), with a coarser back side power track arrangement, with relaxed overlay tolerance for patterning the back side power delivery tracks <NUM> relative to the TSVs <NUM>. The staggered pattern of TSVs allows adapting the length of the TSVs to a chosen width and pitch of the tracks <NUM> on the back side. <FIG> are schematic images of two staggered TSV configurations. In both images, the TSVs <NUM> are now drawn horizontally and the tracks <NUM> vertically. The references R1,R2 and T1, T2 are again included to indicate the pairs of rows R1,R2 of TSVs and the corresponding pairs of tracks T1,T2. In the embodiment of <FIG>, the length LTSV of the TSVs is larger than the distance STSV between two adjacent TSVs, so that TSVs of R1 and R2 partially overlap with respect to each other, and with respect to the neighbouring row of TSVs. This is allowed, with the condition that a sufficient TSV length can be contacted by each track <NUM>. In the embodiment of <FIG>, the TSVs of R1 and R2 do not overlap each other nor the TSVs of neighbouring rows and the length LTSV is equal to the distance STSV. Likewise, the width WBM of the tracks <NUM> is equal to the distance SBM between two adjacent tracks. This embodiment enables the highest interconnect density. In <FIG> the back to front overlay tolerance Δ is the overlay tolerance applied when processing the tracks <NUM> relative to the staggered pattern of the TSVs. This tolerance ensures that one track (T1 or T2) effectively contacts one row (R1 or R2), without contacting the TSVs of an adjacent row. In the processed IC, the position of the tracks may be shifted within this tolerance with respect to the ideal position shown in the drawings.

We will illustrate hereafter that a very relaxed overlay tolerance for patterning the back side power delivery tracks <NUM> can be applied, while still allowing a dense interconnect configuration. The following relations can be derived from the dimensions indicated in <FIG> :.

For example, if the backside tracks <NUM> have a width of <NUM> and a pitch of <NUM>, and an overlay tolerance of <NUM> is applied for producing these backside tracks <NUM>, the required length of the TSVs is <NUM> in the embodiment of <FIG>. Supposing that the width of the TSVs is <NUM>, the resulting volume of the TSVs enables a high conductivity of the TSVs, ensuring - together with the fact that the TSVs are closer together than in the TSV-last approach - a low resistive path from the back side of the IC to the active devices in the FEOL. This is achieved with the relaxed overlay tolerance of <NUM>, whereas in prior art methods, a more severe overlay tolerance was required.

Another way of producing an IC in accordance with the invention is described hereafter, with reference to <FIG>. According to this embodiment, and as illustrated in <FIG>, trenches <NUM> are produced at the locations where the buried power rails are to be formed, before producing the TSVs. These trenches <NUM> are not etched through the complete thickness of the Si layer <NUM>, but the etch is stopped before reaching the back surface of this layer <NUM>. The trenches <NUM> are formed along the complete length of a given fin pattern (said length being measured in the longitudinal direction of the fins). After this, as illustrated in <FIG>, the trenches <NUM> are further deepened to form elongate slits <NUM> at the TSV locations by a self-aligned etch, until reaching the back surface of the Si layer <NUM>. The steps of etching the trenches <NUM> and locally deepening these trenches typically involves substeps of depositing a dielectric liner on the walls and bottom of the trenches <NUM>, planarizing the wafer, forming a lithographic mask defining the TSV locations, removing the liner from the bottom of the trenches, and depositing a liner in the slits <NUM>. These steps are described in more detail in <CIT>, incorporated herein by reference. After forming a liner also at the bottom of the slits <NUM>, an electrically conductive material is deposited in the slits <NUM> and in the trenches <NUM> in a single deposition step (see <FIG>), followed by etching back the conductive material in the trenches and depositing a dielectric <NUM>. This results in the formation of buried power rails <NUM> and TSVs <NUM>, the latter being arranged in the staggered pattern described above. After this, further steps for producing the IC are known as such, and include the formation of the source and drain contacts and further FEOL processing, M0 processing, BEOL processing and back side processing for producing the power delivery tracks <NUM>. One difference with the method described earlier is that the power rails <NUM> are now buried deeper into the Si layer <NUM>. This may require the formation of narrow via connections between the buried power rails <NUM> and the M0 conductors <NUM>.

This approach for forming the staggered TSVs is a via-first approach, as basically described in <CIT>. The advantages of the staggered pattern as such and as described above for example in terms of the overlay tolerances, are however applicable regardless of the method by which the pattern has been produced.

The invention is not limited to an IC comprising fin-based devices. The staggered pattern of TSVs can be applied in combination with any type of known active devices on the front surface of the Si layer <NUM>. The devices could be nano-sheet based devices, well known in the art, wherein stacks of nano-sheets are processed on the front surface of the Si layer <NUM>, said stacks have a similar profile to the fins <NUM> and <NUM>' shown in the drawings.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims.

It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways, and is therefore not limited to the embodiments disclosed. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.

Claim 1:
An integrated circuit chip comprising :
- a semiconductor substrate (<NUM>) having a front surface and a back surface,
- active devices on the front surface of the substrate (<NUM>), isolated from each other by a dielectric layer (<NUM>),
- mutually parallel power rails (<NUM>) extending in one direction and buried in the substrate (<NUM>) and/or in said dielectric layer (<NUM>),
- through semiconductor via connections (<NUM>), hereafter referred to as TSVs, connecting the power rails (<NUM>) to the back surface of the substrate (<NUM>),
- power delivery tracks (<NUM>) on the back surface of the substrate, oriented transversely with respect to the power rails (<NUM>), and connected to the power rails by said TSVs (<NUM>),
wherein :
- the power delivery tracks (<NUM>) are part of a power delivery network configured to be coupled to a supply voltage and to a reference voltage,
- the power delivery tracks (<NUM>) are configured to be alternately connected to the supply voltage and to the reference voltage,
- the TSVs (<NUM>) are arranged so that the power rails (<NUM>) are equally configured to be alternately connected to the supply voltage and the reference voltage,
characterised in that :
- the TSVs (<NUM>) are formed as elongate slit-shaped volumes aligned to the power rails (<NUM>),
- the TSVs (<NUM>) are arranged in a staggered pattern, so that any one of the power delivery tracks (<NUM>) is connected to a first row of mutually parallel TSVs, and any power delivery track (<NUM>) directly adjacent to said power delivery track is connected to a second row of mutually parallel TSVs which are staggered relative to the TSVs of the first row, the second row being directly adjacent the first row.