Patent Description:
The disclosure relates to the technical field of semiconductors, and relates, to a semiconductor structure, a method for forming the same and a layout structure.

At present, dynamic random access memories (DRAMs) are mostly manufactured by using a 6F<NUM> layout mode and a buried word line process. However, with this process, the miniaturization of DRAMs becomes very difficult. The performance of the DRAMs may be improved by using new materials. However, this undoubtedly increases the process complexity and the manufacturing cost of DRAMs.

On this basis, in a related art, a DRAM with a 4F<NUM> layout is manufactured by using a gate-all-around or dual-gate process, and the DRAM with a 4F<NUM> layout needs to form a bit line staircase or a word line staircase. However, the bit line staircase has great sensing noise when the DRAM is operated, and the word line staircase has the problem of word line coupling and the problem that the interconnection of word lines on the same plane in the process are difficult to realize for a multi-layer stack. Background may be found in <CIT>.

In the drawings (which are not necessarily drawn to scale), similar reference signs may describe similar parts in different views. Similar reference signs with different letter suffixes may represent different examples of similar parts. The drawings generally illustrate the various embodiments discussed herein by way of examples rather than limitation.

Reference signs in the drawings are described as follows. <NUM>-semiconductor substrate; <NUM>-stacked structure; <NUM>-the first semiconductor layer; <NUM>-the second semiconductor layer; <NUM>-initial active layer; <NUM>-T-shaped active pillar; <NUM>-first active pillar; <NUM>-second active pillar; <NUM>-third active pillar; <NUM>-fourth active pillar; <NUM>-fifth active pillar; <NUM>-first sub-pillar; <NUM>-second sub-pillar; <NUM>-third sub-pillar; <NUM>-first sacrificial layer; <NUM>-second sacrificial layer; <NUM>-supporting structure; <NUM>-first supporting layer; <NUM>-second supporting layer; <NUM>-concave groove; <NUM>-isolating layer; <NUM>-T-shaped gate structure; <NUM>-gate dielectric layer; <NUM>-gate conductive layer; <NUM>-bit line structure; <NUM>-bit line groove; <NUM>-capacitor structure; <NUM>-first electrode layer; <NUM>-dielectric layer; <NUM>-second electrode layer; <NUM>-conductive layer; <NUM>-word line stairs; <NUM>-word line; <NUM>-third semiconductor layer; <NUM>-protective layer; <NUM>-semiconductor structure; and <NUM>-layout structure.

Exemplary implementation modes of the disclosure will be described below in more detail with reference to the drawings. Although the exemplary implementation modes of the disclosure are shown in the drawings, it should be understood that, the disclosure may be implemented in various forms and should not be limited by the specific implementation modes elaborated herein. On the contrary, these implementation modes are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

In the following description, a large number of details are given to provide a more thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the disclosure may be implemented without one or more of these details. In other examples, in order to avoid confusion with the disclosure, some technical features known in the art are not described. That is, all the features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

In the drawings, the dimensions of layers, areas, and elements and their relative dimensions may be exaggerated for clarity. Throughout, the same reference signs represent the same elements.

It is to be understood that description that an element or layer is "on", "adjacent to", "connected to", or "coupled to" another element or layer may refer to that the element or layer is directly on, adjacent to, connected to or coupled to the other element or layer, or there may be an intermediate element or layer. On the contrary, description that an element is "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer refers to that there is no intermediate element or layer. It is to be understood that, although various elements, components, areas, layers, and/or parts may be described with terms first, second, third, etc., these elements, components, areas, layers, and/or parts should not be limited to these terms. These terms are used only to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, a first element, component, area, layer, or part discussed below may be represented as a second element, component, area, layer, or part without departing from the teaching of the disclosure. However, when second element, component, area, layer, or part is discussed, it does not mean that the first element, component, area, layer, or part must exist in the disclosure.

The terms used herein are intended only to describe specific embodiments and are not a limitation of the disclosure. As used herein, singular forms "a/an", "one", and "said/the" may also be intended to include the plural forms, unless otherwise specified types in the context. It is also to be understood that, when terms "composed of" and/or "comprising/including" are used in this specification, the presence of the features, integers, steps, operations, elements, and/or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups is also possible. As used herein, terms "and/or" includes any and all combinations of the related listed items.

Before introducing the embodiments of the disclosure, three directions for describing the three-dimensional structure that may be used in the following embodiments are defined first. Taking a Cartesian coordinate system as an example, the three directions may include an X-axis direction, a Y-axis direction, and a Z-axis direction. The base may include a top surface located on a front side and a bottom surface located on a back side opposite to the front side. The direction perpendicular to the top surface and the bottom surface of the base is defined as the third direction in a case of ignoring the flatness of the top surface and the bottom surface. In the direction of the top surface and the bottom surface (that is, the plane on which the base is located) of the base, two directions that intersect each other (e.g., perpendicular to each other) are defined. For example, a word line extending direction may be defined as the first direction, a capacitor structure extending direction may be defined as a second direction, and a plane direction of the base may be determined on the basis of the first direction and the second direction. Here, the first direction, the second direction, and the third direction are perpendicular to one another. In the embodiments of the disclosure, the first direction is defined as an X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

Embodiments of the disclosure provide a method for forming a semiconductor structure. <FIG> illustrates a schematic flowchart of a method for forming a semiconductor structure provided by the embodiments of the disclosure. As shown in <FIG>, the method for forming the semiconductor structure includes the following operations.

At S101, a base is provided. The base includes a first area and a second area arranged in sequence in a second direction, and T-shaped active structures located in the first area and the second area and arranged in an array in a first direction and a third direction.

In the embodiments of the disclosure, the base at least includes a semiconductor substrate. The semiconductor substrate may be a silicon substrate. The semiconductor substrate may also include other semiconductor elements such as germanium (Ge), or semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP) and/or indium gallium arsenide phosphide (GaInAsP), or a combination thereof.

In the embodiments of the disclosure, the first area and the second area are respectively arranged to form different functional structures. The first area is arranged to form a gate structure, a bit line structure and a stair-shaped word line structure. The second area is arranged to form a capacitor structure.

At S102, T-shaped gate structures located on surfaces of the T-shaped active structures and bit line structures extending in the third direction are formed in the first area. A plurality of T-shaped gate structures located in the first direction are interconnected.

In the embodiments of the disclosure, some of the T-shaped gate structures are dual-gate structures, and some of the T-shaped gate structures are four-gate all around structures. The T-shaped gate structure covers a first surface and a second surface, in the third direction, of each T-shaped active pillar, a surface in the first direction of the T-shaped active pillar, and a surface in a second direction of the T-shaped active pillar.

Each of the bit line structures and each of the T-shaped gate structures are formed on the surfaces of one corresponding T-shaped active pillar, thus the bit line structure is connected to the T-shaped gate structure through the T-shaped active pillar.

In the embodiments of the disclosure, each word line may be formed on an outer side of the T-shaped gate structures subsequently, so that not only the interconnection of the word lines in the same plane of a multi-layer stacked structure can be realized, but also the dimension of the word line can be controlled, thereby reducing a coupling effect between word line stairs.

At S103, capacitor structures extending in the second direction are formed in the second area. Both the bit line structures and the capacitor structures are connected to the T-shaped gate structures.

The capacitor structure formed in the embodiments of the disclosure extends in the second direction. That is to say, the capacitor structure formed in the embodiments of the disclosure is arranged horizontally, and the horizontal capacitor structure can reduce the risk of tipping or breaking, so that the stability of the capacitor structure can be improved. In addition, a plurality of horizontal capacitor structures and T-shaped gate structures may be stacked to form a three-dimensional semiconductor structure, and the integration degree of the semiconductor structure can be improved, and the miniaturization can be realized.

<FIG> and <FIG> illustrate schematic structural diagrams showing a process for forming a semiconductor structure provided by an embodiment of the disclosure. The process for forming the semiconductor structure provided by the embodiments of the disclosure will be further described below in detail with reference to <FIG> and <FIG>.

Reference may be made to <FIG>. In S101, a base is provided. The base includes a first area and a second area arranged in sequence in a second direction, and T-shaped active structures located in the first area and the second area and arranged in arrays in a first direction and a third direction. <FIG> is a three-dimensional view. <FIG> are top views or sectional views along a-a', b-b' and c-c' in the process for forming a semiconductor structure.

In some embodiments, the T-shaped active structures may be formed by the following operations. A semiconductor substrate <NUM> is provided. A stacked structure <NUM> located in the first area A and the second area B is formed on a surface of the semiconductor substrate <NUM>. Herein, the stacked structure <NUM> includes first semiconductor layers <NUM> and second semiconductor layers <NUM> stacked alternately in the third direction. The first semiconductor layers <NUM> in the first area A are removed to expose the second semiconductor layers <NUM> in the first area A. Thinning processing is performed on the exposed second semiconductor layers <NUM> to form initial active layers <NUM>. The initial active layers <NUM> are processed to form the T-shaped active structures <NUM>.

As shown in <FIG> and <FIG>, a stacked structure <NUM> located in the first area A and the second area B is formed on the surface of the semiconductor substrate <NUM>. The stacked structure <NUM> includes first semiconductor layers <NUM> and second semiconductor layers <NUM> stacked alternately in the third direction.

In the embodiments of the disclosure, the material of the first semiconductor layer <NUM> may be Ge, SiGe, or SiC, or may be silicon-on-insulator (SOI) or a germanium-on-insulator (GOI). The second semiconductor layer <NUM> may be a silicon layer, or may also include other semiconductor elements such as germanium, or include semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, or include other semiconductor alloys such as silicon germanium, arsenic gallium phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, or indium gallium arsenide phosphate, or a combination thereof.

In the embodiments of the disclosure, the material of the first semiconductor layer <NUM> and the material of the second semiconductor layer <NUM> are different since the first semiconductor layer <NUM> needs to be removed and the second semiconductor layer <NUM> needs to be remained subsequently. Therefore, the first semiconductor layer <NUM> has a higher etching selectivity relative to the second semiconductor layer <NUM>. For example, the etching selective ratio of the first semiconductor layer <NUM> relative to the second semiconductor layer <NUM> may be <NUM>-<NUM>, so that the first semiconductor layer <NUM> is etched and removed more easily relative to the second semiconductor layer <NUM> during etching.

In the embodiments of the disclosure, the thickness of the first semiconductor layer <NUM> may be <NUM> to <NUM>, such as <NUM> or <NUM>. The thickness of the second semiconductor layer <NUM> may be <NUM> to <NUM>, such as <NUM> or <NUM>. The number of the first semiconductor layers <NUM> and the number of the second semiconductor layers <NUM> in the stacked structure <NUM> may be set according to the required capacitor density (or storage density). The greater the numbers of the first semiconductor layers <NUM> and the second semiconductor layers <NUM>, the higher the integration degree of the formed semiconductor structure and the greater the capacitor density.

In the embodiments of the disclosure, the first semiconductor layers <NUM> and the second semiconductor layers <NUM> may be formed by any one of the following deposition processes: an epitaxial process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, a coating process, or a thin-film process.

As shown in <FIG>, the first semiconductor layers <NUM> in the first area A are removed, so as to expose the second semiconductor layers <NUM> in the first area A.

In the embodiments of the disclosure, the first semiconductor layers <NUM> in the stacked structure <NUM> may be removed by a wet etching process (for example, etching with a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching process. The first semiconductor layers <NUM> have higher etching selectivity relative to the second semiconductor layers <NUM>, so that the second semiconductor layers <NUM> are not damaged when the first semiconductor layers <NUM> are removed.

As shown in <FIG>, thinning processing is performed on the exposed second semiconductor layers <NUM>, so as to form the initial active layers <NUM>.

In the embodiments of the disclosure, each of the second semiconductor layers <NUM> may be subjected to the thinning processing with the following two modes, so as to form the initial active layers <NUM>.

Mode <NUM>: The second semiconductor layers <NUM> are directly subjected to dry etching, and the etching is stopped when the required thickness is formed.

Mode <NUM>: The second semiconductor layers <NUM> are oxidized in-situ to oxidize part of each second semiconductor layer <NUM> into a silicon oxide layer, and the silicon oxide layer is removed by the wet etching or dry etching processes.

In the embodiments of the disclosure, the second semiconductor layers <NUM> are thinned to <NUM> to <NUM> to form the initial active layers <NUM>. For example, the thickness of each formed initial active layer <NUM> may be <NUM>. Thus, channel areas formed by fully depleted semiconductor layers may be formed. At this moment, holes are easily recombined in the source area without accumulation, so that a floating body effect can be improved. In addition, since the gap between two adjacent initial active layers <NUM> becomes large, a larger space is reserved for the formation of the gate structures and the subsequent word line structures, thereby reducing a word line coupling effect, and the preparation process complexity and the manufacturing cost of the gate structures and the word line structures.

It is to be noted that, in other embodiments, the second semiconductor layers <NUM> may not be subjected to the thinning processing. After the first semiconductor layers <NUM> in the first area A are removed, the exposed second semiconductor layers <NUM> may be directly used as the initial active layer <NUM>.

In some embodiments, the operation that the initial active layers <NUM> are processed to form the T-shaped active structures <NUM> may include the following operations. A sacrificial layer <NUM> and a first supporting layer <NUM> are formed on a surface of each initial active layer <NUM> in sequence. Herein the first supporting layers <NUM> fill between the sacrificial layers <NUM>. Part of each first supporting layer <NUM>, part of each sacrificial layer <NUM>, and part of each initial active layer <NUM> in the first area A and part of the stacked layer structure <NUM> in the second area are removed, so as to form a plurality of concave grooves <NUM> arranged at intervals in the first direction. Part of each initial active layer in the second direction is removed to form a first space, and the remaining initial active layer forms the T-shaped active pillar.

As shown in <FIG> and <FIG>, a first sacrificial layer <NUM> and a first supporting layer <NUM> are formed in a sequence on each of the initial active layers <NUM>. Part of the first supporting layer <NUM>, part of the first sacrificial layer <NUM>, and part of the initial active layer <NUM> in the first area A, and part of the stacked structure from second area <NUM> are removed, so as to form a plurality of concave grooves <NUM> arranged at intervals in the X-axis direction.

In the embodiments of the disclosure, the material of the sacrificial layers <NUM> may be silicon oxide or other suitable materials. The material of the first supporting layers <NUM> may be silicon oxide or other suitable materials. Here, the material of the first sacrificial layer <NUM> and the material of the first supporting layer <NUM> should be different, and have different etching selectivity under the same etching conditions. For example, the etching selective ratio of the first sacrificial layer <NUM> to the semiconductor substrate <NUM> is greater than the etching selective ratio of the first supporting layer <NUM> to the semiconductor substrate <NUM>. The first sacrificial layer <NUM> and the first supporting layer <NUM> may be formed by any suitable deposition process, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, a coating process or a furnace tube process.

In the embodiments of the disclosure, the first supporting layers <NUM> are formed to support the second semiconductor layers <NUM>. Since the T-shaped gate structure needs to be formed on the surface of each second semiconductor layer <NUM> subsequently, the first supporting layers <NUM> can also be used to support the T-shaped gate structures. Thus, the stability of the formed semiconductor structure can be improved and the collapse of the formed semiconductor structure can be prevented.

In the embodiments of the disclosure, part of each first supporting layer <NUM>, part of each first sacrificial layer <NUM>, and part of each initial active layer <NUM> in the first area A, and part of the stacked structure <NUM> in the second area B may be removed by a dry etching technology, so as to form a plurality of concave grooves <NUM> arranged at intervals in first direction.

In the embodiments of the disclosure, each T-shaped active pillar will form a memory cell. Two adjacent memory cells in the X-axis direction are isolated by one concave groove <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, after forming the concave grooves <NUM>, the method for forming a semiconductor structure further includes an operation that an isolating material is filled in each concave groove <NUM>, so as to form an isolating layer <NUM>. The isolating material may be a low-dielectric constant (Low K) material, such as SiCON.

In the embodiments of the disclosure, the etching selective ratio of the isolation layer <NUM> to the semiconductor substrate <NUM> is greater than the etching selective ratio of the first sacrificial layer <NUM> to the semiconductor substrate <NUM>. That is, the isolating layer <NUM> is etched and removed more easily than the first sacrificial layer <NUM> under the same etching condition.

In the embodiments of the disclosure, the Low K material is used as the isolating material, which can reduce the parasitic capacitance of the semiconductor structure, so as to reduce the capacitance resistance delay and improve the response time of the semiconductor structure.

As shown in <FIG> and <FIG>, part of each initial active layer <NUM> along the Y-axis direction is removed to form a first space C, and the remaining initial active layer <NUM> forms the T-shaped active pillar <NUM>.

In the embodiments of the disclosure, part of the initial active layer <NUM> is laterally etched by using a wet etching process, so as to form a T-shaped active pillar <NUM>. An etching solution for the wet etching may be hydrofluoric acid solution, or may be a mixed solution of diluted hydrofluoric acid and aqueous ammonia.

In some embodiments, each T-shaped active pillar located in the first area A includes a first active pillar and a second active pillar extending in the second direction, as well as a third active pillar and a fourth active pillar extending in the first direction. The first active pillar is connected with the third active pillar.

<FIG> is a schematic diagram of a three-dimensional structure of one T-shaped active pillar <NUM> in the first area A. As shown in <FIG> and <FIG>, the first active pillar <NUM>, the second active pillar <NUM>, the third active pillar <NUM> and the fourth active pillar <NUM> may be formed by the following operations. Part of each first sacrificial layer <NUM> is removed along the X-axis direction and the Y-axis direction to expose part of each initial active layer <NUM> and form a second space D. Herein, the parts extending in the X-axis direction and the Y-axis direction of the exposed part of each initial active layer <NUM> respectively constitute the first active pillar <NUM> and the third active pillar <NUM> (as shown in <FIG>). The parts extending in the first direction and in the second direction of the un-exposed part of each initial active layer <NUM> respectively constitute the second active pillar <NUM> and the fourth active pillar <NUM> (as shown in <FIG>). The second space D includes the first space C.

In the embodiments of the disclosure, since the T-shaped gate structure and the word line structure will be formed in the second space D subsequently, the interconnection of word lines on the same plane of a multi-layer stacked structure can be realized through side-connected word lines.

Then, in S102, with reference to <FIG>, T-shaped gate structures located on surfaces of the T-shaped active structures and bit line structures extending in the third direction are formed in the first area A. A plurality of T-shaped gate structures located in the first direction are interconnected. <FIG> and <FIG>, and <FIG> are top views or sectional views showing the process for forming a semiconductor structure in a-a', b-b' and c-c', and <FIG> is a three-dimensional view of one T-shaped gate structure <NUM>.

As shown in <FIG>, the T-shaped gate structure <NUM> may be formed by the following operations. A gate dielectric layer <NUM> and a gate conductive layer <NUM> are formed on surfaces of the first active pillar <NUM> and the third active pillar <NUM>, so as to form the T-shaped gate structure <NUM>. The gate conductive layer <NUM> fills the second space D.

In the embodiments of the disclosure, the material of the gate dielectric layer <NUM> may be silicon oxide or other suitable materials. The material of the gate conductive layer <NUM> may include one of polysilicon, a metal (e.g., tungsten, copper, aluminum, titanium, tantalum, ruthenium, etc.), a metal alloy, a metal silicide, a titanium nitride, or any combination thereof.

In the embodiments of the disclosure, the gate dielectric layer <NUM> may be formed by an in-situ steam generation (ISSG) process. The thickness of the gate dielectric layer <NUM> may be <NUM> to <NUM>, such as <NUM> or <NUM>. The gate conductive layer <NUM> may be formed by any suitable deposition process, such as the CVD process, the PVD process or the ALD process.

Continuing to refer to <FIG>, in the embodiments of the disclosure, in the Y-axis direction, a part of the gate metal layer <NUM>-<NUM> located at a first end of the T-shaped gate structure <NUM> may be used as part of a word line structure that connects to T-shaped gate structures of the same layer subsequently.

In some embodiments, as shown in <FIG>, the bit line structure <NUM> may be formed by the following operations. Part of the first sacrificial layer <NUM> and part of the isolating layer <NUM> on sidewall of each fourth active pillar <NUM> are removed to form a bit line groove <NUM>. The bit line groove <NUM> exposes one end, far away from the third active pillar <NUM>, of the fourth active pillar <NUM>, and part of the isolating layer <NUM> is retained between two adjacent ones of the T-shaped active structures <NUM> in the X-axis direction. A bit line metal material fills in the bit line grooves <NUM> to form bit line structures <NUM> extending in the Z-axis direction.

In the embodiments of the disclosure, the bit line metal material may be any material with a good electrical conductivity, such as tungsten, cobalt, copper, aluminum, titanium, titanium nitride, platinum, palladium, molybdenum, a titanium-containing metal layer, polysilicon or any combination thereof.

In the embodiments of the disclosure, the bit line metal material is in direct contact with the second semiconductor layer <NUM>. Subsequently, the metal material may directly react with the second semiconductor layer <NUM> in-situ to form a metal silicide through a rapid thermal annealing process. Since the metal silicide has a low resistance value, the contact resistance between the bit line structure and the fourth active pillar can be reduced, thereby further reducing the power consumption of the semiconductor structure.

As shown in <FIG> and <FIG>, after forming the bit line structures <NUM> and before forming the capacitor structures, the method for forming the semiconductor structure further includes the following operations. The isolating layers <NUM> and the first semiconductor layers <NUM> located in the second area B are removed to expose the second semiconductor layers <NUM> in the second area B. Thinning processing is performed on the second semiconductor layers <NUM> in the second area B to form fifth active pillars <NUM>. Each fifth active pillar <NUM> is connected to one corresponding second active pillar <NUM>.

Continuing to refer to <FIG>, in the embodiments of the disclosure, each fifth active pillar <NUM> includes a first sub-pillar <NUM>, a second sub-pillar <NUM>, and a third sub-pillar <NUM> arranged in sequence in the Y-axis direction.

In the embodiments of the disclosure, the isolating layer <NUM> may be removed by a dry etching process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process) or a wet etching process (e.g., etching by using a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid). The gas used for the dry etching may be one of trifluoromethane (CHF<NUM>), carbon tetrafluoride (CF<NUM>), difluoromethane (CH<NUM>F<NUM>), hydrobromic acid (HBr), chlorine (Cl<NUM>) or sulfur hexafluoride (SF<NUM>), or a combination thereof. In the embodiments of the disclosure, the first semiconductor layers <NUM> have higher etching selectivity relative to the second semiconductor layers <NUM>, so that the second semiconductor layers <NUM> may not be damaged when the first semiconductor layers <NUM> are removed.

In the embodiments of the disclosure, there are two modes of performing thinning processing on the second semiconductor layer <NUM> in the second area B as follows.

Mode <NUM>: The second semiconductor layer <NUM> is directly subjected to dry etching, and the etching is stopped when the required thickness is formed.

Mode <NUM>: The second semiconductor layers <NUM> are oxidized in-situ to oxidize part of each second semiconductor layer <NUM> into a silicon oxide layer, and the silicon oxide layer is removed by a wet etching or dry etching technologies.

In the embodiments of the disclosure, the gap between two adjacent fifth active pillars <NUM> becomes large by performing the thinning processing on the second semiconductor structures <NUM> to form the fifth active pillars <NUM>. Thus, the effective area between the electrodes of the formed capacitor structures can be improved, so as to improve the capacitance of the formed capacitor structure.

It is to be noted that, in other embodiments, the second semiconductor layers <NUM> may also not be subjected to the thinning processing.

Finally, reference may be made to <FIG> to perform S103. Capacitor structures extending in the second direction in the second area are formed. The bit line structures and the capacitor structures are connected to the T-shaped gate structures. <FIG> are top views or sectional views showing a process for forming the semiconductor structure in a-a', b-b' and c-c', and <FIG> is a three-dimensional view of the formed T-shaped gate structure.

As shown in <FIG>, each capacitor structure <NUM> may be formed by the following operations. A second supporting layer <NUM> is formed on a surface of the first sub-pillar <NUM>; and a second sacrificial layer <NUM> is formed on a surface of the second sub-pillar <NUM>.

In the embodiment of the disclosure, the second supporting layer <NUM> fills between the first sub-pillars <NUM>. The material of the second supporting layer <NUM> may be silicon nitride or silicon carbonitride. The first supporting layer <NUM> and the second supporting layer <NUM> jointly form a supporting structure <NUM> of the semiconductor structure.

In the embodiments of the disclosure, the second sacrificial layer <NUM> fills between the second sub-pillars <NUM>. The material of the second sacrificial layer <NUM> may be silicon nitride or silicon carbonitride.

As shown in <FIG> and <FIG>, a third semiconductor layer <NUM> is formed on a surface of each third sub-pillar <NUM>. A first electrode layer <NUM> is formed on surfaces of the third semiconductor layers <NUM> and a sidewall of the second sacrificial layer <NUM>. A protective layer <NUM> is formed on the surface of the first electrode layer <NUM> and fills up the gaps formed between the first electrode layer <NUM>.

In the embodiments of the disclosure, the third semiconductor layer <NUM> may be a metal silicide layer. During implementation, a layer of metal material, such as anyone of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd), may be deposited on each second sub-pillar <NUM>. After that, the metal material interacts with the third sub-pillar <NUM> through rapid thermal annealing, so that metal silicide is formed on the surface of the second sub-pillar <NUM>. The metal silicide has low resistance, so the contact resistance between a lower electrode and a drain can be reduced, thereby reducing the power consumption of the semiconductor structure.

In the embodiments of the disclosure, the first electrode layer <NUM> may be formed by any one of the following deposition processes: a selective atomic layer deposition process, a CVD process, a PVD process and a spin coating process. The material of the first electrode layer <NUM> may include metal or metal nitride, such as ruthenium (Ru) or titanium nitride.

In some embodiments, the material of the protective layer <NUM> may be silicon nitride or any other suitable material. The protective layer <NUM> is for protection of the first electrode layer <NUM> from being damaged when the second sacrificial layer <NUM> is subsequently removed. Therefore, the etching selective ratio of the second sacrificial layer <NUM> to the second sub-pillar <NUM> needs to be set to be greater than the etching selective ratio of the protective layer <NUM> to the second sub-pillar <NUM>.

As shown in <FIG> and <FIG>, the second sacrificial layer and part of the first electrode layer <NUM> located on the side wall of the second sub-pillars <NUM> are removed to expose the second sub-pillars <NUM> and the sidewall of the second supporting layer <NUM>. The protective layer <NUM> is removed to expose the remaining first electrode layer <NUM>. Dielectric layers <NUM> are formed on the surfaces of the second sub-pillars <NUM> and the first electrode layer <NUM>. A second electrode layer <NUM> is formed on the sidewall of the second supporting layer <NUM> and the surfaces of the dielectric layers <NUM>, and the first electrode layer <NUM>, the dielectric layer <NUM> and the second electrode layer <NUM> form the capacitor structure <NUM>.

In the embodiments of the disclosure, the protective layer <NUM> is removed by a wet etching technology (for example, etching by using a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching technology.

In the embodiments of the disclosure, the dielectric layers <NUM> and the second electrode layer <NUM> may be formed by any one of the following deposition processes: a selective atomic layer deposition process, a CVD process, a PVD process, and a spin coating process. The material of the second electrode layer <NUM> may include metal or metal nitride, such as ruthenium (RU) or titanium nitride. The material of the dielectric layer <NUM> may include a high-K dielectric material, for example, one of lanthanum oxide (La<NUM>O<NUM>), aluminum oxide (Al<NUM>O<NUM>), hafnium oxide (HfO<NUM>), hafnium oxynitride (HfON), hafnium silicate (HfSiOx) or zirconium oxide (ZrO<NUM>), or any combination thereof. In other embodiments, the material of the first electrode layers and the second electrode layer may also be polysilicon.

In the embodiments of the disclosure, the capacitor structures <NUM> extend in the Y-axis direction. That is to say, each capacitor structure <NUM> is parallel to the semiconductor structure. The capacitor structures <NUM> are horizontal. On one hand, compared with vertical capacitor structures <NUM> with a high aspect ratio (that is, the ratio of height to width or diameter), the horizontal capacitor structures <NUM> can reduce the risk of tipping or breaking, so that the stability of the capacitor structures <NUM> can be improved. On the other hand, the stacked structure formed by stacking a plurality of capacitor structures in a vertical direction can form a three-dimensional semiconductor structure, so that the integration degree of the semiconductor structure can be improved, and miniaturization can be realized.

In some embodiments, as shown in <FIG> and <FIG>, the method for forming the semiconductor structure further includes an operation that a conductive layer <NUM> is formed on a surface of the second electrode layer <NUM>, and the conductive layer <NUM> fills between adjacent third sub-pillars <NUM>.

In the embodiments of the disclosure, the material of the conductive material <NUM> may be polysilicon, or may also be any other suitable conductive material, such as doped polysilicon.

In some embodiments, as shown in <FIG>, after the formation of the T-shaped gate structures <NUM>, the method for forming the semiconductor structure further includes an operation that word line stairs <NUM> stacked in sequence in the Z-axis direction are formed, in which each layer of the word lines <NUM> in the word line stairs <NUM> are electrically connected to the corresponding plurality of the T-shaped gate structures <NUM> arranged in the X-axis direction.

In some embodiments, the word line stairs <NUM> may be formed by the following operations. Firstly, a photoresist layer with a first opening is formed on the surface of the first area A, the first opening exposes one end of the first region A, and part of the first area A is etched through the photoresist layer with the first opening to form a first stair structure. Secondly, a photoresist layer with a second opening is formed on the surface of the first stair structure, the second opening exposes part of the first stair structure, and the first stair structure is etched through the photoresist layer with the second opening to form a second stair structure. Herein the dimension of the second opening in the first direction is larger than the dimension of the first opening. Thirdly, a photoresist layer with a third opening is formed on the surface of the second stair structure, the third opening exposes part of the second stair structure, and the second stair structure is etched through the photoresist layer of the third opening to form a third stair structure. Herein the dimension of the third opening in the first direction is larger than the dimension of the second opening. The abovementioned operations are repeated, and the word line stairs <NUM> are finally formed after the multiple etching processes. The word line stairs <NUM> have gradually decreased lengths from bottom to top in the Z-axis direction.

In other embodiments, the word line stairs <NUM> may also be formed by the following operations. Firstly, a first word line with the first length is formed on the surface of the base in the first area A. Herein the first word line is electrically connected to the T-shaped gate structures <NUM> in the X-axis direction at the bottommost layer. Secondly, a first isolating unit with a second length is formed on a surface of the first word line, a second word line with the second length is formed on a surface of the first isolating unit, and the second word line is electrically connected to the T-shaped gate structures <NUM> in the first direction at the second layer from the bottom. Herein the first length is greater than the second length, and the first isolating unit is configured to isolate the adjacent first word line and second word line. Thirdly, a second isolating unit with a third length is formed on a surface of the second word line, and a third word line with the third length is formed on a surface of the second isolating unit. Herein the third word line is electrically connected to the T-shaped gate structures <NUM> in the X-axis direction at the third layer from bottom to top. Herein the second length is greater than the third length, and the second isolating unit is configured to isolate the adjacent second word line and third word line. The abovementioned operation is repeated, and a plurality of word lines are thus formed to form the word line stairs <NUM> through multiple forming processes.

In the embodiments of the disclosure, the T-shaped gate structures are formed, and the side-connecting method of the word lines is adopted, which not only solves the problem that it is difficult for a multi-layer stack to interconnect the word lines on the same plane, and the word line coupling effect can also be reduced by controlling the dimensions of a side-connected word lines.

The embodiments of the disclosure further provide a semiconductor structure. The semiconductor structure is formed by the method for forming a semiconductor structure provided by the above mentioned embodiments. <FIG> are schematic structural diagrams of a semiconductor structure provided by an embodiment of the disclosure. <FIG> is a three-dimensional view of the semiconductor structure. <FIG> is a three-dimensional view of a T-shaped active pillar. <FIG> is a three-dimensional view of the T-shaped gate structure. <FIG> is a top view of <FIG>. <FIG> is a sectional view of <FIG> along a-a'.

As shown in <FIG>, the semiconductor structure <NUM> at least includes: a semiconductor substrate <NUM> and T-shaped active structures <NUM> located on the surface of the semiconductor substrate <NUM>, in which the T-shaped active structures <NUM> are arranged in an array in the X-axis direction and the Z-axis direction; T-shaped gate structures located on surfaces of part of each T-shaped active pillar <NUM>, in which a plurality of T-shaped gate structures <NUM> in the X-axis direction are interconnected; bit line structures <NUM> extending in the Z-axis direction; and capacitor structures <NUM> extending in the Y-axis direction, in which both the bit line structures <NUM> and the capacitor structures are connected to the T-shaped gate structures <NUM>.

In some embodiments, as shown in <FIG>, the semiconductor structure <NUM> further includes: a first area A and a second area B arranged in the Y-axis direction in sequence. Each T-shaped active pillar <NUM> includes a first active pillar <NUM> and a second active pillar <NUM> located in the first area A and extend in the Y-axis direction, and a third active pillar <NUM> and a fourth active pillar <NUM> located in the first area A and extend in the X-axis direction. The first active pillar <NUM> is connected to the third active pillar <NUM>. The bit line structure <NUM> is formed on part of the fourth active pillar <NUM>.

In some embodiments, as shown in <FIG>, one T-shaped gate structure <NUM> includes a gate dielectric layer <NUM> located on the surfaces of the first active pillar <NUM> and the third active pillar <NUM>, and a gate conductive layer <NUM> located on a surface of the gate dielectric layer <NUM>.

In the embodiments of the disclosure, projections of the first active pillar <NUM> and the third active pillar <NUM> on the surface of the semiconductor substrate <NUM> are T-shaped.

In some embodiments, continuing to refer to <FIG>, the T-shaped active pillar <NUM> further includes a fifth active pillar <NUM> located in the second area B. The capacitor structure <NUM> is located on part of the fifth active pillar <NUM>.

As shown in <FIG>, the capacitor structure <NUM> includes a first electrode layer <NUM>, a dielectric layer <NUM>, and a second electrode layer <NUM> located on the fifth active pillar <NUM>.

In some embodiments, continuing to refer to <FIG> and <FIG>, the semiconductor structure <NUM> further includes: a conductive layer <NUM> located between the second electrode layer <NUM> and on the surfaces of the second electrode layer <NUM>, and a third semiconductor layer <NUM> located between the first electrode layer <NUM> and the fifth active pillar <NUM>.

In some embodiments, the third semiconductor layer <NUM> may be a metal silicide layer. The third semiconductor layer <NUM> is arranged to reduce the contact resistance between the capacitor structure <NUM> and the fifth active pillar <NUM>.

In some embodiments, continuing to refer to <FIG>, there is a concave groove <NUM> between two adjacent ones of the T-shaped active structures in the X-axis direction.

In some embodiments, continuing to refer to <FIG>, <FIG>, and <FIG>, the semiconductor structure <NUM> further includes: a supporting structure <NUM>. The supporting structure <NUM> includes a first supporting layer <NUM> and a second supporting layer. The first supporting layer <NUM> is located on a surface of part of the second active pillar <NUM> located between the bit line structure <NUM> and the T-shaped gate structure <NUM>. The second supporting layer <NUM> is located on a surface of part of the fifth active pillar <NUM> located between the capacitor structure and the T-shaped gate structure <NUM>.

In some embodiments, referring to <FIG>, the semiconductor structure <NUM> further includes: word line stairs <NUM>. The word line stairs <NUM> are sequentially stacked along the Z-axis direction, and each layer of word lines <NUM> in the word line stairs <NUM> is electrically connected to the corresponding plurality of T-shaped gate structures <NUM> arranged along the X-axis direction.

The semiconductor structure provided by the embodiments of the disclosure is similar to the semiconductor structure formed with the method provided by the above mentioned embodiments. The technical features not disclosed in detail in the embodiment of the disclosure can be referred to the above mentioned embodiments for understanding, and will not be elaborated herein.

The semiconductor structure provided by the embodiments of the disclosure has the T-shaped gate structures, and the word lines led out through the outer side of the T-shaped gate structures, so that not only the interconnection of the word lines in the same plane of a multi-layer stacked structure can be realized, but also the dimensions of the word lines can be controlled, thereby reducing a coupling effect between word line stairs.

<FIG> illustrate schematic diagrams of plane structures of semiconductor structures provided by embodiments of the disclosure. As shown in <FIG>, a semiconductor structure <NUM> includes: T-shaped gate structures <NUM>, bit line structures <NUM>, and capacitor structures <NUM> arranged in an array in the X-axis direction and the Z-axis direction. The bit line structures <NUM> and the capacitor structures <NUM> are connected to the T-shaped gate structures <NUM>.

In the embodiments of the disclosure, one T-shaped gate structure <NUM> and one capacitor structure <NUM> constitute a memory cell. Adjacent memory cells in the X-axis direction have the same layout (as shown in <FIG>, <FIG> and <FIG>), or adjacent memory cells in the X-axis direction are axisymmetric (as shown in <FIG>).

In some embodiments, continuing to refer to <FIG>, the semiconductor structure <NUM> further includes word line stairs <NUM> extending in the X-axis direction. Each layer of word lines in the word line stairs are connected to a plurality of corresponding T-shaped gate structures <NUM> arranged in the X-axis direction.

In the embodiments of the disclosure, each layer of word lines in the word line stairs <NUM> may be rectangular (as shown in <FIG>), or may also be serrated (as shown in <FIG>).

The embodiments of the disclosure further provide a layout structure. 6D and <FIG> are plane layouts of layout structures provided by embodiments of the disclosure. A layout structure <NUM> includes: the above mentioned semiconductor structures <NUM> arranged at intervals in the Y-axis direction.

As shown in <FIG> and <FIG>, each semiconductor structure <NUM> includes memory cells arranged in an array in the X-axis direction and the Z-axis direction. Each memory cell includes a T-shaped gate structure <NUM> and a capacitor structure <NUM>. Two adjacent memory cells arranged along the Y-axis direction are centrosymmetric, and projection regions, along the X-axis direction, of the capacitor structures <NUM> of the two adjacent memory cells arranged along the Y-axis direction are at least partially overlapped.

In some embodiments, continuing to refer to <FIG> and <FIG>, the semiconductor structure <NUM> further includes bit line structures <NUM> and word line stairs <NUM>.

In some embodiments, continuing to refer to <FIG>, two adjacent memory cells in the X-axis direction have the same layout.

In some embodiments, continuing to refer to <FIG>, two adjacent memory cells in the X-axis direction are axisymmetric.

The layout structure provided by the embodiments of the disclosure can effectively utilize the space of each semiconductor structure to realize the miniaturization of the semiconductor structure.

In several embodiments provided by the disclosure, it is to be understood that the disclosed device and method may be implemented in a non-target mode. The above described device embodiments are only schematic. For example, the division of the units is only logical function division. In actual implementation, there may be other division modes, for example, a plurality of units or components may be combined, or may be integrated into another system, or some features may be ignored or not implemented.

The characteristics disclosed in several method or device embodiments provided in the disclosure may be freely combined without conflicts to obtain new method embodiments or device embodiments.

The abovementioned descriptions are only some implementation modes of the disclosure, but the scope of protection of the disclosure is solely defined by the appended claims.

Claim 1:
A method for forming a semiconductor structure (<NUM>) of DRAM device, comprising:
providing a base, wherein the base comprises a first area (A) and a second area (B) arranged in sequence in a second direction, and T-shaped active structures (<NUM>) located in the first area (A) and the second area (B) and arranged in an array in a first direction and a third direction, the first direction, the second direction and the third direction are perpendicular to one another, and the first direction and the second direction are parallel to a surface of the base;
forming T-shaped gate structures (<NUM>) located on surfaces of the T-shaped active structures (<NUM>) and bit line structures (<NUM>) extending in the third direction in the first area (A), wherein a plurality of the T-shaped gate structures (<NUM>) located in the first direction are interconnected;
forming word line stairs (<NUM>) stacked in sequence in the third direction in the first area (A), wherein each
layer of word lines (<NUM>) of the word line stairs (<NUM>) are electrically connected to the corresponding T-shaped gate structures (<NUM>) arranged in the first direction; and
forming capacitor structures (<NUM>) extending in the second direction in the second area (B), wherein the bit line structures (<NUM>) and the capacitor structures (<NUM>) are connected to the T-shaped active structures (<NUM>), and wherein the bit line structures (<NUM>) and the capacitor structures (<NUM>) are located at a same side of the word line stairs (<NUM>).