Patent Description:
In the drawings, which are not necessarily drawn to scale, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes represent different instances of substantially similar components.

Reference will now be made in detail to certain embodiments of the disclosed subject matter, examples of which are illustrated in part in the accompanying drawings. While the disclosed subject matter will be described in conjunction with the enumerated claims, it will be understood that the exemplified subject matter is not intended to limit the claims to the disclosed subject matter.

Throughout this document, values expressed in a range format should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. For example, a range of "about <NUM>% to about <NUM>%" or "about <NUM>% to <NUM>%" should be interpreted to include not just about <NUM>% to about <NUM>%, but also the individual values (e.g., <NUM>%, <NUM>%, <NUM>%, and <NUM>%) and the sub-ranges (e.g., <NUM>% to <NUM>%, <NUM>% to <NUM>%, <NUM>% to <NUM>%) within the indicated range. The statement "about X to Y" has the same meaning as "about X to about Y," unless indicated otherwise. Likewise, the statement "about X, Y, or about Z" has the same meaning as "about X, about Y, or about Z," unless indicated otherwise.

In this document, the terms "a," "an," or "the" are used to include one or more than one unless the context clearly dictates otherwise. The term "or" is used to refer to a nonexclusive "or" unless otherwise indicated. The statement "at least one of A and B" has the same meaning as "A, B, or A and B. " In addition, it is to be understood that the phraseology or terminology employed herein, and not otherwise defined, is for the purpose of description only and not of limitation. Any use of section headings is intended to aid reading of the document and is not to be interpreted as limiting; information that is relevant to a section heading may occur within or outside of that particular section.

In the methods described herein, the acts may be carried out in any order without departing from the principles of the disclosure, except when a temporal or operational sequence is explicitly recited. Furthermore, specified acts may be carried out concurrently unless explicit claim language recites that they be carried out separately. For example, a claimed act of doing X and a claimed act of doing Y may be conducted simultaneously within a single operation, and the resulting process will fall within the literal scope of the claimed process.

The term "about" as used herein may allow for a degree of variability in a value or range, for example, within <NUM>%, within <NUM>%, or within <NUM>% of a stated value or of a stated limit of a range, and includes the exact stated value or range.

The term "substantially" as used herein refers to a majority of, or mostly, as in at least about <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, or at least about <NUM>% or more, or <NUM>%.

<FIG> schematically illustrates a cross-section side view of an example integrated circuit (IC) package assembly <NUM>, in accordance with some embodiments. In some embodiments, the IC package assembly <NUM> may include one or more dies (hereinafter "die <NUM>") electrically and/or physically coupled with a package substrate <NUM>. In some embodiments, the package substrate <NUM> may be electrically coupled with a circuit board <NUM>, as may be seen.

The die <NUM> may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like used in connection with forming complementary metal-oxide-semiconductor (CMOS) devices. In some embodiments, the die <NUM> may be, include, or be a part of a processor, memory, SoC, or ASIC.

In some embodiments, an underfill material <NUM> (sometimes referred to as an "encapsulant") may be disposed between the die <NUM> and the package substrate <NUM> to promote adhesion and/or protect features of the die <NUM> and package substrate <NUM>. The underfill material <NUM> may be composed of an electrically insulative material and may encapsulate at least a portion of the die <NUM> and/or die-level interconnect structures <NUM>, as may be seen. In some embodiments, the underfill material <NUM> is in direct contact with the die-level interconnect structures <NUM>.

The die <NUM> may be attached to the package substrate <NUM> according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate <NUM> in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, S1, of the die <NUM> including active circuitry is attached to a surface of the package substrate <NUM> using die-level interconnect structures <NUM> such as bumps, pillars, or other suitable structures that may also electrically couple the die <NUM> with the package substrate <NUM>. The active side S <NUM> of the die <NUM> may include transistor devices, and an inactive side, S2, may be disposed opposite to the active side S1, as may be seen. Other configurations besides a flip-chip configuration are possible.

Die <NUM> may generally include a semiconductor substrate 102a, one or more device layers (hereinafter "device layer 102b"), and one or more interconnect layers (hereinafter "interconnect layer 102c"). The semiconductor substrate 102a may be substantially composed of a bulk semiconductor material such as, for example, silicon, in some embodiments. The device layer 102b may represent a region where active devices such as transistor devices are formed on the semiconductor substrate 102a. The device layer 102b may include, for example, structures such as channel bodies and/or source/drain regions of transistor devices. The interconnect layer 102c may include interconnect structures that are configured to route electrical signals to or from the active devices in the device layer 102b. For example, the interconnect layer 102c may include trenches and/or vias to provide electrical routing and/or contacts.

In some embodiments, the die-level interconnect structures <NUM> may be configured to route electrical signals between the die <NUM> and other electrical devices. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die <NUM>. In some embodiments, the die-level interconnect structures <NUM> may include solder bumps formed according to techniques described herein.

In some embodiments, the package substrate <NUM> is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. In other embodiments, the package substrate <NUM> may be a circuit board such as, for example, a printed circuit board (PCB) formed using any suitable PCB technique. The package substrate <NUM> may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The package substrate <NUM> may include electrical routing features configured to route electrical signals to or from the die <NUM>. The electrical routing features may include, for example, pads <NUM>/<NUM>, traces 114A and vias <NUM> disposed on one or more surfaces of the package substrate <NUM> and/or internal routing features such as, for example, trenches, vias, or other interconnect structures such as traces <NUM> to route electrical signals through the package substrate <NUM>. For example, in some embodiments, the package substrate <NUM> may include electrical routing features such as pads (not shown) configured to receive the respective die-level interconnect structures <NUM> of the die <NUM>.

The circuit board <NUM> may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board <NUM> may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant <NUM> (FR-<NUM>), FR-<NUM>, cotton paper, and epoxy materials such as CEM-<NUM> or CEM-<NUM>, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures <NUM> such as traces, trenches, or vias may be formed through the electrically insulating layers to route the electrical signals of the die <NUM> through the circuit board <NUM>. The circuit board <NUM> may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board <NUM> is a motherboard.

Package-level interconnects such as, for example, solder balls <NUM> or bumps may be coupled to one or more pads (hereinafter "pads <NUM>") on the package substrate <NUM> and/or on the circuit board <NUM> to form corresponding solder joints that are configured to further route the electrical signals between the package substrate <NUM> and the circuit board <NUM>. Pads <NUM> may be composed of any suitable electrically conductive material, such as metal, including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple the package substrate <NUM> with the circuit board <NUM> may be used in other embodiments.

In some embodiments, circuit board <NUM> may include one or more traces <NUM> to route electrical signals on one or more surfaces of the circuit board <NUM> and/or through the circuit board <NUM>. The one or more traces <NUM> may include copper traces formed according to techniques described herein, according to various embodiments.

The IC package assembly <NUM> may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die <NUM> and other components of the IC package assembly <NUM> may be used in some embodiments.

As shown in <FIG>, conductive elements such as traces <NUM> are at least partially embedded within the dielectric material. This is shown further in <FIG>, which is a schematic sectional diagram showing layer <NUM> of traces <NUM> embedded within substrate <NUM>. Substrate <NUM> may include a suitable build-up dielectric film material, <NUM>, such as Ajinomoto Build-up Film (ABF). Whichever dielectric material is used, it may be an epoxy based resin with a balance material (e.g. epoxy or silica) ranging from about <NUM> wt% to about <NUM> wt% of dielectric layer <NUM>, about <NUM> wt% to about <NUM> wt% of dielectric layer <NUM>, less than equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or 95wt% of dielectric layer <NUM>. Although shown as a single layer, dielectric layer <NUM> may include a plurality of individual layers of the dielectric material. In examples where dielectric layer <NUM> includes a plurality of individual layers, those individual layers of the dielectric material may include different dielectric materials or the same dielectric material.

As described herein, traces <NUM> include an electrically conductive material such as a metal or an alloy thereof. As shown the conductive material is a metal. The metal may range from about <NUM> wt% to about <NUM> wt% of the conductive material, about <NUM> wt% to about <NUM> wt% of the conductive material, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> wt% of the conductive material. As shown in <FIG>, the metal is copper.

<FIG> is a schematic sectional view of substrate <NUM>. As shown, substrate <NUM> includes traces, or metallic transmission lines, 114A, 114B, and 114C. Trace 114A includes a first region which defines via <NUM> as well as a second region, which carries the electrical signal in the x or y direction. Via <NUM> projects in the z-direction. Via <NUM> has first end <NUM> and second end <NUM>. Second end <NUM> may be in electrical communication with another trace (not shown) or a solder ball that is connected to die <NUM> (not shown).

<FIG> is a schematic side view of trace 114A isolated from dielectric layer <NUM> and rotated <NUM> degrees with respect to <FIG>. <FIG> is a schematic top view of transmission line 114A. As shown in <FIG>, via <NUM> and traces 114A, 114B, or 114C have different z-direction heights and x or y direction widths. For example, as shown with respect to <FIG>, via <NUM> has first height H<NUM>. Trace 114B, which is adjacent via <NUM>, has a second height H<NUM> which is different than the first height. A second region of trace 114A, shown in <FIG> and <FIG>, has a height substantially equivalent to second height Hz. While not so limited, the first height may range from about <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. While not so limited, the second height may range from <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. As compared to each other, the first height may range from about <NUM> times to about <NUM> times greater than the second height, about <NUM> times to about <NUM> times greater than the second height, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> times greater than the second height.

While not so limited, a first width W<NUM> of via <NUM> in an x or y direction may range from about <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. Additionally, while not so limited, a second width W<NUM> in an x or y direction of adjacent trace 114B, or second region of trace 114A, may range from about <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. As compared to each other, the first width may range from about <NUM> times to about <NUM> times greater than the second width, about <NUM> times to about <NUM> times greater than the second width, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> times greater than the second width. Via <NUM> may be connected to a trace of a second conductive layer.

As shown in <FIG>, and <FIG>, via <NUM> has a constant cross-sectional shape. The shape may be any suitable shape. Non-limiting examples of suitable shapes include a circle, an oval, a triangle, a square, a rectangle, a pentagon, a hexagon, a heptagon, and an octagon. Regardless of the choice of shape, via <NUM> via has a substantially non-tapered profile in a z-direction. The non-tapered profile may result from dielectric layer <NUM> not being laser drilled in order to form via <NUM>. This may lead to several benefits in that via <NUM> may be a "self-aligned via". As used herein the term "self-aligned via" refers to a via that is not positioned on a via capture pad having a diameter larger than the via. As generally understood in some substrate manufacturing methods, where a via is laser drilled or even lithographically defined, a capture pad is formed so that the via may fully land on the pad to accommodate laser/litho alignment tolerances. In some non-limiting examples, the capture pad may have to be <NUM> to <NUM> larger than the minimum diameter of the via. However, because vias <NUM> have a constant cross-sectional shape and are not formed through a method involving laser drilling or lithographic patterning, there is no need for a capture pad that is larger than a minimum diameter of via <NUM>. Thus, where via <NUM> is located, the minimum diameter of via <NUM> is the same as the diameter or width of trace <NUM>. To the extent that any portion of via <NUM> may be considered to include a portion functioning as a capture pad, there is no interface therebetween. Thus via <NUM> is a monolithic structure.

In some embodiments this may be beneficial in that substrate <NUM> may have an increased density of traces as compared to a corresponding substrate having a via capture pad. As an example, <FIG> shows a top sectional view of substrate <NUM>. As shown, traces 114Band 114D divert around via <NUM>. Without an oversized via capture pad, traces 114B and 114D may be much closer to via <NUM>, thereby opening up additional space for additional traces <NUM>. Thus more traces <NUM>, and thereby increased input/output density, may be present in substrate <NUM>. <FIG> is a schematic diagram illustrating method <NUM> of forming substrate <NUM>. In operation <NUM>, an electrolytic copper layer which acts as a seed layer for subsequent electroplated copper traces and vias is formed on the dielectric layer <NUM>. In some embodiments, the seed layer may be sputtered. After seed layer <NUM> is deposited on dielectric layer <NUM>, a dry film resist that is photo-definable is formed on the seed layer which is then patterned using a lithography process to define the openings on seed layer <NUM> at operation <NUM>. In some embodiments, the DFR portions 206A-206D may be laminated, deposited, etched, and/or formed according to some other process. In some embodiments, the DFR portions 206A-206D may be laminated onto the seed layer, then masked and photo-defined. Pads 114A, vias <NUM> and traces 114B-114C are then formed in the DFR openings. In embodiments, the pads, vias and traces may be formed via a plating process such as electrolytic plating. In embodiments, the Pads 114A, vias <NUM> and traces 114B-114C may be formed from copper. In some embodiments, the Pads 114A, vias <NUM> and traces 114B-114C may be formed from the same material or a different material from the seed layer <NUM>.

The growth of vias <NUM> having a first height hi as opposed to traces <NUM> having second height h<NUM>, may be accomplished by controlling the electrolytic bath components and maintaining adjacent dry film resist elements <NUM> dispersed on the seed layer <NUM> at specific distances and with respect to each other. Electroplated copper that forms the pads 114A, vias <NUM> and traces <NUM> B-114C is deposited from a bath that has a source for Cu, which may include any suitable mixture of components dispersed or dissolved in water. For example, electrolytic copper composition <NUM> may include a copper salt. While not so limited, the copper salt may range from about <NUM> wt% to about <NUM> wt% of electrolytic copper composition <NUM>, about <NUM> wt% to about <NUM> wt%, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 70wt% of electrolytic copper composition <NUM>. Non-limiting examples of the copper salt include cupric sulfate, copper chloride, or a mixture thereof.

Electrolytic copper bath <NUM> may further include a rate controlling agent such as an accelerator or suppressor. The rate controlling agent may range from about <NUM> wt% to about <NUM> wt% of electrolytic copper composition <NUM>, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> wt% of electrolytic copper composition <NUM>. The rate controlling additive may include one or more compounds that are capable of suppressing the deposition rate of copper metal in certain portions of the substrate while increasing the deposition rate of the copper metal in other portions of the substrate. This may be necessary to fill high aspect ratio features. For example, a bottom-up fill process (also known as superfill) may be used to fill high-aspect features by suppressing the copper deposition rate at the surface of the substrate (often referred to as the "field"), while simultaneously increasing the copper deposition rate within the narrow trenches and vias.

In some examples, certain rate controlling additives may function to both increase the copper deposition rate within the features while suppressing the copper deposition rate on the field. For instance, certain polymeric additives, such as PEG, may become anchored to the field by techniques that are well known in the art, such as the use of a metal catalyst as an anchoring agent. The anchored polymeric additive substantially prevents copper from depositing on at least portions of the field, thereby suppressing the copper deposition rate at the surface of the substrate. Suppressing metal deposition on the field forces the metal to travel down into the narrow trenches where the metal deposits and fills the gap. The polymeric additive generally does not inhibit metal deposition within the features, such as the narrow trenches and vias, because the size of the high molecular weight polymer substantially prevents it from entering such features. The polymeric additive therefore increases copper deposition within the features by suppressing copper deposition on the top surface.

In some examples, certain rate controlling additives may be used to suppress the copper deposition rate in areas while other rate controlling additives may be used to increase the copper deposition rate in other areas. For instance, rate controlling additives that may be used to suppress the copper deposition rate on the field include, but are not limited to, polyethers such as polyethylene glycol (PEG), polypropylene glycol (PPG), nitrogen bearing heterocyclic or non-heterocyclic aromatic compounds, large molecular weight polyoxy-alkyl type compounds, and other high molecular weight polymers. Furthermore, rate controlling additives that may be used primarily to increase the copper deposition rate within high-aspect features include, but are not limited to, sulfur-based organic molecules such as bis (sodiumsulfopropyl) disulfide (SPS), other disulfides, and surfactants.

In some examples, a high molecular weight polymer may be used as a grain refining additive as well as a rate controlling additive. For instance, in some implementations, PEG may be used as both a grain refining additive and a rate controlling additive.

In addition to promoting superfill, the use of rate controlling additives allows the nucleation time to be controlled without having to rely on adjustments to the pH level and/or temperature of the electrolytic plating bath, as is done in conventional processes.

Electrolytic copper composition <NUM> may further include a grain refining additive. The grain refining additive may range from about <NUM> wt% to about <NUM> wt% of electrolytic copper composition <NUM>, about <NUM> wt% to about <NUM> wt%, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> wt% of electrolytic copper composition <NUM>. The grain refining additive may be a high molecular weight compound that is capable of reducing the grain size of the plated copper metal. By reducing the grain size of the copper, the copper metal may more readily enter high aspect features and reach the bottom of the features while minimizing issues such as obstructing the trench gap or forming a trench overhang. In implementations of the inventive subject matter, materials that may be used as the grain refining additive include, but are not limited to, polyethylene glycol (PEG), ethylene diamine, propionitrile (also known as ethyl cyanide), and ethylene glycol (EG). Some of these materials may be available in polymeric form, such as PEG, which may be available as PEG <NUM>, PEG <NUM>, PEG <NUM>, etc. In accordance with implementations of the disclosure, the grain refining additive may have a molecular weight that ranges from <NUM>,<NUM> to <NUM>,<NUM>. As will be appreciated by those of skill in the art, alternative high molecular weight compounds capable of reducing the grain size of the plated copper metal may be used.

In some examples, electrolytic copper composition <NUM> may further include a buffering agent. The buffering agent may range from about <NUM> wt% to about <NUM> wt% of electrolytic copper composition <NUM>, about <NUM> wt% to about <NUM> wt%, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> wt% of electrolytic copper composition <NUM>. In embodiments of the invention, buffering agents that may be used include ethylene diamine tetraacetic acid (EDTA), hydroxyethylene diamine triacetic acid (HEDTA), Rochelle salt (also known as potassium sodium tartarate), an organic acid (e.g., citric acid, tartaric acid, etc.), ammonium citrate, lactate, triethanolamine (TEA), and ethylene diamine. Alternate buffering agents not mentioned here may be used as well.

In some examples, electrolytic coper composition <NUM> may further include a bath stabilizing agent. The bath stabilizing agent ranges from about <NUM> wt% to about <NUM> wt% of electrolytic copper composition <NUM>, <NUM> wt% to about <NUM> wt% of the electrolytic copper composition <NUM>, less than, equal to, or greater than about <NUM> wt%, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> wt% of electrolytic copper composition <NUM>. In some examples, the bath stabilizing agent may include one or more compounds that are capable of stabilizing the bath against the formation of undesired cuprous oxide particles for electrolytic plating processes having relatively long nucleation times. The long nucleation times help to completely fill features with high aspect ratios. In some implementations, the bath stabilizing agent may further function as a leveling agent to produce mirror-like plated surfaces. In some examples, bath stabilizing agents that may be used include, but are not limited to, thiourea, dypiridil, mercaptobenzothiazole (MBT), benzotriazole, Janus Green B (JGB), cyanide, vanadium pentoxide (V<NUM>O<NUM>), as well as certain high molecular weight polymers.

As discussed herein, the growth of vias <NUM> having a first height H<NUM> as opposed to traces <NUM> having second height h<NUM>, may be accomplished by controlling the electrolytic bath components and maintaining adjacent dry film resist elements <NUM> dispersed on the seed layer <NUM> at specific distances and with respect to each other to form patterned regions. For example as shown, dry film resist elements 206A and 206B are spaced apart at a first distance di and dry film resist elements 206A and 206C are spaced apart at a second distance d<NUM>. The first distance is greater than the second distance. As non-limiting examples, the first distance may range from about <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. The second distance may range from about <NUM> to about <NUM>, about <NUM> to about <NUM>, less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. D<NUM> may also be about <NUM> times to about <NUM> times greater than D<NUM>, about <NUM> times greater to about <NUM> times greater, or less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> times greater than D<NUM>. It is understood that the distance between dry film resist elements 206A and 206B may vary along the x- or y-direction depending on whether it is desired to form a via. The distance between dry film resist elements 206B and 206C may vary similarly.

At operation <NUM>, the Pads (114A), vias <NUM> and traces 114B-114C are electroplated applying voltage thereto. The distance between dry film resist elements <NUM> may determine, at least in part, whether a high aspect ratio via <NUM> or lower aspect ratio trace <NUM> is formed. Greater distances between dry film resist elements <NUM> may result in higher aspect ratio (height to width) features such as vias <NUM>, whereas comparatively smaller distances between dry film resist elements <NUM> may result in lower aspect ratio (height to width) features of trace <NUM>.

Moreover, electrolytic bath copper composition may be altered in terms of the amount of inhibitor or accelerator to produce desired heights for the Pads (114A), vias <NUM> and traces (114B-114C). Without intending to be bound to any theories, the inventors believe that the inclusion of predetermined levels of rate controlling agents may selectively produce an inhibitor in a space having a limited area, which may result in slower plating in smaller areas than larger areas. For example, and without limitation, the inventors have found that differential growth rates leading to taller vias and shorter traces due to the presence of a by-product of a rate control agent such as an accelerator by-product, which acts as a plating inhibitor. Even if less of the rate controlling agent is present, due to a lack of efficient circulation in a relatively narrow space (e.g., a <NUM> wide space), a lower aspect ratio (height to width) trace will form. Contrarily, due the relatively more efficient circulation in a comparatively wider space (e.g., a <NUM> wide space) the inhibitor by-product will be more efficiently circulated, and therefore less effective, leading to the formation of higher aspect ratio (height to width) vias during plating, even if more of the rate controlling agent is present.

Thus a different rate in plating may exist between dry film resist elements 206A and 206B than between 206B and 206C. Accordingly, electrolytic plating in a first region defined between dry film resist elements 206A and 206B may occur at a faster rate than electrolytic plating in a second region defined between dry film resist elements 206B and 206C.

At operation <NUM>, dry film resist elements 206A-206D are removed. Via <NUM> and traces 114A, 114B and 114C are optionally roughed or an adhesion promoter is applied thereto. At operation <NUM>, second dielectric layer <NUM> is laminated over via <NUM> and traces <NUM>. At operation <NUM>, any excess dielectric material of the second dielectric layer <NUM> is removed for the subsequent routing layer formation. The removal of the dielectric material may be accomplished by etching (physical or chemical), grinding, or Chemical Mechanical Polish (CMP). Excess dielectric material may refer to dielectric material extending in a z-direction beyond trace 114A. The operations of method <NUM> may be repeated to form additional vias <NUM> and traces.

<FIG> illustrates a system level diagram, according to an embodiment of the invention. For instance, <FIG> depicts an example of an electronic device (e.g., system) including IC package assembly <NUM>; <FIG> is included to show an example of a higher level device application for the present inventive subject matter. In an embodiment, system <NUM> includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system <NUM> is a system on a chip (SOC) system.

In an embodiment, processor <NUM> has one or more processing cores <NUM> and 712N, where 712N represents the Nth processor core inside processor <NUM> where N is a positive integer. In an embodiment, system <NUM> includes multiple processors including <NUM> and <NUM>, where processor <NUM> has logic similar or identical to the logic of processor <NUM>. In some embodiments, processing core <NUM> includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, and the like. In some embodiments, processor <NUM> has a cache memory <NUM> to cache instructions and/or data for system <NUM>. Cache memory <NUM> may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor <NUM> includes a memory controller <NUM>, which is operable to perform functions that enable the processor <NUM> to access and communicate with memory <NUM> that includes a volatile memory <NUM> and/or a non-volatile memory <NUM>. In some embodiments, processor <NUM> is coupled with memory <NUM> and chipset <NUM>. Processor <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals. In an embodiment, the wireless antenna <NUM> operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory <NUM> includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory <NUM> includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory <NUM> stores information and instructions to be executed by processor <NUM>. In an embodiment, memory <NUM> may also store temporary variables or other intermediate information while processor <NUM> is executing instructions. In the illustrated embodiment, chipset <NUM> connects with processor <NUM> via Point-to-Point (PtP or P-P) interfaces <NUM> and <NUM>. Chipset <NUM> enables processor <NUM> to connect to other elements in system <NUM>. In some embodiments of the invention, interfaces <NUM> and <NUM> operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset <NUM> is operable to communicate with processor <NUM>, 705N, display device <NUM>, and other devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. Chipset <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals.

Chipset <NUM> connects to display device <NUM> via interface <NUM>. Display device <NUM> may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor <NUM> and chipset <NUM> are merged into a single SOC. In addition, chipset <NUM> connects to one or more buses <NUM> and <NUM> that interconnect various elements <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Buses <NUM> and <NUM> may be interconnected together via a bus bridge <NUM>. In an embodiment, chipset <NUM> couples with a non-volatile memory <NUM>, a mass storage device(s) <NUM>, a keyboard/mouse <NUM>, and a network interface <NUM> via interface <NUM> and/or <NUM>, smart TV <NUM>, consumer electronics <NUM>, etc..

In an embodiment, mass storage device <NUM> includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In an embodiment, network interface <NUM> is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In an embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

While the modules shown in <FIG> are depicted as separate blocks within the system <NUM>, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory <NUM> is depicted as a separate block within processor <NUM>, cache memory <NUM> (or selected aspects of cache memory <NUM>) may be incorporated into processing core <NUM>.

The following examples of substrates and methods of manufacturing substrates are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

An example provides a substrate for an integrated circuit. The substrate includes a dielectric layer and a conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. The conductive layer further includes a trace adjacent to the via and having a second height in the z-direction that is different than the first height.

An example provides the substrate of other examples, wherein the dielectric layer includes a dielectric material.

An example provides the substrate of other examples, wherein the dielectric material ranges from about <NUM> wt% to about <NUM> wt% of the dielectric layer.

An example provides the substrate of other examples, wherein the dielectric material is chosen from an epoxy laminate, polytetrafluoroethylene, phenolic cotton paper, woven glass, or mixtures thereof.

An example provides the substrate of other examples, wherein the dielectric layer includes a plurality of individual layers of the dielectric material.

An example provides the substrate of other examples, wherein the individual layers of the dielectric material include different dielectric materials.

An example provides the substrate of other examples, wherein the individual layers of the dielectric material include the same dielectric material.

An example provides the substrate of other examples, wherein the conductive layer includes a metal.

An example provides the substrate of other examples, wherein the metal ranges from about <NUM> wt% to about <NUM> wt% of the conductive layer.

An example provides the substrate of other examples wherein the metal ranges from about <NUM> wt% to about <NUM> wt% of the conductive layer.

An example provides the substrate of other examples, wherein the metal is copper.

An example provides the substrate of other examples, wherein the constant cross-sectional shape is chosen from a circle, an oval, a triangle, a square, a rectangle, a pentagon, a hexagon, a heptagon, and an octagon.

An example provides the substrate of other examples, wherein the via has a substantially a substantially constant width.

An example provides the substrate of other examples, wherein the first height ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein a width of the via in an x or y direction ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein the second height ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein a width of the trace in an x or y direction ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein the first height ranges from about <NUM> times to about <NUM> times greater than the second height.

An example provides the substrate of other examples, wherein a width of the via ranges from about <NUM> times to about <NUM> times greater than a width of the trace.

An example provides the substrate of other examples, further including a second conductive layer including a second trace coupled to the via.

An example provides a substrate for an integrated circuit. The substrate includes a dielectric layer and a metallic transmission line. The metallic transmission line includes a first region having a first width in an x or y direction and a first height in a z-direction, and a second region having a second width in the x or y direction and a second height in the z-direction. The first height is greater than the second height and the first region has a constant cross-sectional shape in the z-direction.

An example provides the substrate of other examples, wherein the dielectric material is chosen from an epoxy laminate, polytetrafluoroethylene, phenolic cotton pater, woven glass, or mixtures thereof.

An example provides the substrate of other examples, wherein the first region has a substantially non-tapered profile.

An example provides the substrate of other examples, wherein a width of the first region in an x or y direction ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein a width of the second region in an x or y direction ranges from about <NUM> to about <NUM>.

An example provides the substrate of other examples, wherein a width of the first region ranges from about <NUM> times to about <NUM> times greater than a width of the second region.

An example provides the substrate of other examples, wherein the first region is a via and the second region is a trace.

An example provides a method for forming a substrate. The method includes contacting a first patterned region with an electrolytic copper composition including a copper salt and a rate controlling agent. The method further includes contacting a second patterned region with the electrolytic copper composition including a copper salt and a rate controlling agent. A first quantity of the rate controlling agent in the first region differs from second quantity of the rate controlling agent in the second region and the first and second regions are defined by plurality of dry film resist elements. A first distance in an x or y direction in the first region between a first pair of adjacent dry film resist elements is greater than a second distance in the x or y direction in the second region between a second pair of adjacent dry film resist elements. The method further includes applying a voltage to the electrolytic copper composition to plate a copper layer in the patterned regions, removing the dry film resist elements, and laminating a second dielectric layer on the copper layer.

An example provides the method of other examples, wherein the copper salt ranges from about <NUM> wt% to about <NUM> wt% of the electrolytic copper composition.

An example provides the method of other examples, wherein the copper salt is chosen from cupric sulfate, copper chloride, or a mixture thereof.

An example provides the method of other examples, wherein the rate controlling agent ranges from about <NUM> wt% to about <NUM> wt% of the electrolytic copper composition.

An example provides the method of other examples, wherein the rate controlling agent is chosen from polyethers, polyethylene glycol, polypropylene glycol, nitrogen bearing heterocyclic aromatic compounds, nitrogen bearing non-heterocyclic aromatic compounds, large molecular weight polyoxy-alkyl type compounds, high molecular weight polymers, sulfur-based organic molecules, SPS, disulfides, and surfactants.

An example provides the method of other examples, wherein the electrolytic copper composition further includes a grain refining additive.

An example provides the method of other examples, wherein the grain refining additive ranges from about <NUM> wt% to about <NUM> wt% of the electrolytic copper composition.

An example provides the method of other examples, wherein the grain refining additive is chosen from polyethylene glycol, ethylene diamine, propionitrile, ethylene glycol, or a mixture thereof.

An example provides the method of other examples, wherein the electrolytic copper composition further includes a buffering agent.

An example provides the method of other examples, wherein the buffering agent ranges from about <NUM> wt% to about <NUM> wt% of the electrolytic copper composition.

An example provides the method of other examples, wherein the buffering agent is chosen from ethylene diamine tetraacetic acid, hydroxyethylene diamine triacetic acid, potassium sodium tartarate, an organic acid, ammonium citrate, lactate, triethanolamine, ethylene diamine, or a mixture thereof.

An example provides the method of other examples, wherein the organic acid is chosen from citric acid, tartaric acid, or a mixture thereof.

An example provides the method of other examples, wherein the electrolytic copper composition further includes a bath stabilizing agent.

An example provides the method of other examples, wherein the bath stabilizing agent ranges from about <NUM> wt% to about <NUM> wt% of the electrolytic copper composition.

An example provides the method of other examples, wherein the bath stabilizing agent is chosen from thiourea, dypiridil, mercaptobenzothiazole, benzotriazole, cyanide, V<NUM>O<NUM>, or a mixture thereof.

An example provides the method of other examples, wherein the first distance ranges from about <NUM> to about <NUM>.

An example provides the method of other examples, wherein the second distance ranges from about <NUM> to about <NUM>.

An example provides the method of other examples, wherein plating the electrolytic copper composition in the first patterned region occurs at a faster rate than plating the electrolytic copper composition in the second patterned region.

An example provides the method of other examples, further including removing the dry film resist elements.

An example provides the method of other examples, further including roughening at least a portion of the copper layer.

An example provides the method of other examples, further including forming an adhesion promoting layer over at least a portion of the copper layer.

An example provides the method of other examples, wherein a first portion of the copper layer formed in the first patterned region has a first height and a second portion of the copper layer formed in the second patterned region has a second height that is different than the first height.

An example provides the method of other examples, wherein the first height ranges from about <NUM> to about <NUM>.

An example provides the method of other examples, wherein the second height ranges from about <NUM> to about <NUM>.

An example provides the method of other examples, wherein the first height ranges from about <NUM> times to about <NUM> times greater than the second height.

An example provides the method of other examples, wherein the first distance ranges from about <NUM> times to about <NUM> times greater than the second distance.

An example provides the method of other examples, wherein the dielectric layers include a dielectric material.

An example provides the method of other examples, wherein the dielectric material ranges from about <NUM> wt% to about <NUM> wt% of the dielectric layer.

An example provides the method of other examples, wherein the dielectric material is chosen from an epoxy laminate, polytetrafluoroethylene, phenolic cotton pater, woven glass, or mixtures thereof.

An example provides the method of other examples, wherein the dielectric layer includes a plurality of individual layers of the dielectric material.

An example provides the method of other examples, wherein the individual layers of the dielectric material include different dielectric materials.

An example provides the method of other examples, wherein the first and second layers of the dielectric material include the same dielectric material.

An example provides the method of other examples, wherein the copper layer includes elemental copper.

An example provides the method of other examples, wherein the elemental copper ranges from about <NUM> wt% to about <NUM> wt% of the copper layer.

An example provides the method of other examples, wherein the copper ranges from about <NUM> wt% to about <NUM> wt% of the copper layer.

An example provides the method of other examples, wherein the copper layer formed in the first patterned region has a substantially non-tapered profile.

Claim 1:
A substrate (<NUM>) for an integrated circuit, the substrate comprising:
a dielectric layer (<NUM>); and
a conductive layer extending in an x or y direction and at least partially embedded within the dielectric layer (<NUM>), the conductive layer comprising:
a via (<NUM>) having a first end (<NUM>) and an opposite second end (<NUM>), wherein the via (<NUM>) has a first height (H1) in a z-direction and a constant cross-sectional shape between the first end (<NUM>) and the second end (<NUM>), and
a trace (114B) adjacent to the via (<NUM>) and having a second height (H2) in the z-direction that is different than the first height,
characterized in that
the via (<NUM>) has a non-tapered profile in the z-direction.