Patent Description:
In a field of display, organic light-emitting diode (OLED) display panels have the characteristics of self-illumination, high contrast, low energy consumption, wide viewing angle, fast response speed, being applicable to a flexible panel, wide temperature range of use, simple manufacture, and the like, and have broad development prospects.

<CIT> discloses a display device including a substrate having a pixel area and a peripheral area, a plurality of pixels disposed on the substrate in the pixel area, a plurality of data lines that supply a plurality of data signals to the pixels, a plurality of scan lines that supply a plurality of scan signals to the pixels, a plurality of power supply lines that supply a first voltage to the pixels, and first through third insulating layers. The first insulating layer is disposed on the substrate, the second insulating layer is disposed on the first insulating layer, and the third insulating layer is disposed on the second insulating layer. The scan lines are disposed below the third insulating layer on the substrate in the pixel area, and are disposed on the third insulating layer in the peripheral area.

<CIT> discloses an OLED device including: a substrate; a thin film transistor (TFT) over the substrate, the TFT including a semiconductor layer and a gate electrode overlapping the semiconductor layer; a conductive layer between the substrate and the semiconductor layer of the TFT; an insulating layer between the conductive layer and the TFT; a passivation layer covering the TFT; a pixel electrode over the passivation layer, the pixel electrode being electrically connected to the TFT via a contact hole defined in the passivation layer; an emission layer over the pixel electrode; and an opposite electrode over the emission layer, the opposite electrode being electrically connected to the conductive layer.

<CIT> discloses a display apparatus including a plurality of pixel electrodes, a plurality of circuit units in one-to-one correspondence with the plurality of pixel electrodes, respectively, each of the plurality of circuit units being electrically connected to a corresponding one of the plurality of pixel electrodes, a plurality of lower power supply lines extending in one direction so as to be electrically connected to some circuit units from among the plurality of circuit units, the some circuit units being along the one direction, and a plurality of upper power supply lines extending in the one direction, the upper power supply lines being over the plurality of lower power supply lines, and electrically connected to the plurality of lower power supply lines.

<CIT> discloses a pixel structure disposed in a display region which includes a light-emitting region and a non-light-emitting region. The pixel structure has a first active device, a second active device, a light emitting device and an auxiliary electrode layer. The first active device is electrically connected with a scan line and a data line. The second active device is electrically connected with the first active device and a power line. The light emitting device is disposed in the light-emitting region and includes a first electrode layer electrically connected with the second active device, a light emitting layer disposed on the first electrode layer and a second electrode layer disposed on the light emitting layer. The auxiliary electrode layer is electrically connected with the power line.

<CIT> discloses a display device including a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires is in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.

It is an object of the present invention to provide a display panel and a display device.

The object is achieved by the features of the respective independent claims. Further embodiments are defined in the corresponding dependent claims.

In order to clearly illustrate the technical solutions of the embodiments of the disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the disclosure and thus are not limitative to the disclosure.

The technical solutions of the embodiments will be described in a clearly and fully understandable way below in connection with the accompanying drawings, referring to the non-limiting exemplary embodiments illustrated in the accompanying drawings and detailed in the following description, the exemplary embodiments of the present disclosure and their various features and advantageous details are more fully described. It should be noted that, the features shown in figures are not necessarily to be drawn in a real scale. The description of the known material(s), component(s) and process technology can be omitted in the present disclosure, so that the exemplary embodiments of the present disclosure are not obscured. The examples provided are merely intended to be beneficial for understanding the implementation of the exemplary embodiments of the present disclosure, and further enable one of ordinary skill in the art to which the present disclosure belongs to implement the exemplary embodiments. Therefore, the examples should not be construed as a limitation of the scope of the embodiments of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms such as "a," "an," etc., are not intended to limit the amount, but indicate the existence of at least one. The terms "comprise," "comprising," "include," "including," etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases "connect", "connected", etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. "On," "under," "right," "left" and the like are only used to indicate relative position relationship, and when the absolute position of the object which is described is changed, the relative position relationship may be changed accordingly. In addition, in respective embodiments of the present disclosure, the same or similar reference numerals denote the same or similar components.

As display products become more and more widely used, consumers are increasingly demanding the display quality such as the display uniformity and the resolution. For example, reasons for the display unevenness is as follows: a voltage input end terminal of a wire has a significant voltage drop (IR drop) effect compared with a voltage input start terminal, which is likely to cause a problem of signal delay, resulting in uneven display of the display panel. For example, increasing the size of the wire is a simple method to improve the display uniformity, however increasing the size of the wire is disadvantageous to the resolution improvement. A method of improving the resolution is to reduce the size of the circuit structure, such as reducing the line width, however, reducing the line width will aggravate the display unevenness, meanwhile, reducing the line width also results in a decrease in process yield. Currently, a circuit structure of an OLED is more complicated than a circuit structure of a liquid crystal display (LCD), and the resolution improvement space is limited. Therefore, a new design needs to be provided to meet the requirements of high resolution and display uniformity.

A display panel provided by at least one embodiment of the present disclosure can improve the display uniformity of the display panel and improve the resolution of the display panel.

<FIG> is a top schematic diagram of a display panel provided by at least one embodiment of the present disclosure. The display panel comprises: a substrate <NUM> and a plurality of pixel units <NUM>. The substrate <NUM> comprises a display area <NUM> and a peripheral area <NUM> on at least one side of the display area <NUM>, the plurality of pixel units <NUM> are located in the display area <NUM>. <FIG> shows the setting mode that the peripheral area <NUM> surrounds the display area <NUM>, but the present disclosure is not limited thereto. The number and arrangement of the pixel units <NUM> are not limited to those shown in the drawings.

<FIG> is a schematic diagram of a pixel unit in a display panel provided by at least one embodiment of the present disclosure. As shown in <FIG>, each pixel unit <NUM> comprises a light-emitting unit <NUM> and a pixel circuit structure <NUM> for providing a driving current to the light-emitting unit <NUM>, and the light-emitting unit <NUM> can be an electroluminescent element, for example, an organic electroluminescent element, such as an organic light-emitting diode (OLED). For example, a driving principle of the electroluminescent element is as follows: the electroluminescent element is driven by current, and the magnitude of the current determines the display grayscale, therefore, in a case where different pixels are controlled under the same driving signal, the voltage drops of the functional signal lines of the pixels at different positions are different, so as to cause a current difference, and the current difference may cause the display unevenness.

<FIG> is a schematic diagram of signal lines for providing signals for each pixel unit in a display panel provided by at least one embodiment of the present disclosure. <FIG> shows a gate line <NUM>, a data line <NUM>, a first power line <NUM>, a second power line <NUM>, and an initialization signal line <NUM>. For example, the gate line <NUM> is configured to provide a scan signal Scan to the pixel circuit structure <NUM>, the data line <NUM> is configured to provide a data signal Data to the pixel circuit structure <NUM>, the first power line <NUM> is configured to provide a constant first voltage signal ELVDD to the pixel circuit structure <NUM>, the second power line <NUM> is configured to provide a constant second voltage signal ELVSS to the pixel circuit structure <NUM>, and the first voltage signal ELVDD is larger than the second voltage signal ELVSS. The initialization signal line <NUM> is configured to provide an initialization signal Vint to the pixel circuit structure <NUM>. The initialization signal Vint is a constant voltage signal, a magnitude of the initialization signal Vint may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but the present disclosure is not limited thereto, for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, signal lines such as the first power line <NUM>, the second power line <NUM>, and the initialization signal line <NUM> may have the above signal delay problem.

<FIG> is a top schematic diagram of a display panel provided by at least one embodiment of the present disclosure. The display panel further comprises a functional signal line <NUM>. The functional signal line <NUM> is connected with the pixel circuit structure <NUM> of each pixel unit <NUM> and provides a common voltage signal for the pixel circuit structure <NUM>. For example, the common voltage signal may be a constant voltage signal.

As shown in <FIG>, the display panel further comprises a first conductive structure <NUM>. The first conductive structure <NUM> is connected in parallel with the functional signal line <NUM> and is located at a layer different from that of the functional signal line <NUM>. For example, the arrangement mode that the first conductive structure <NUM> and the functional signal line are at different layers may facilitate a case where the first conductive structure <NUM> and the functional signal line are connected in parallel via holes.

In the display panel provided by the embodiment of the present disclosure, the first conductive structure <NUM> is connected in parallel with the functional signal line <NUM> to reduce the resistance of the functional signal line, so that the signal delay problem caused by the resistance problem of the functional signal line is weakened. Meanwhile, because the first conductive structure <NUM> and the functional signal line <NUM> are connected in parallel to weaken the signal delay problem, the functional signal line with a larger width may not need to be used, which can help to improve the resolution. Therefore, the display panel provided in the embodiment of the present disclosure can improve both the display uniformity and the resolution, thereby improving the display quality.

As shown in <FIG>, the plurality of pixel units <NUM> extend along a row direction and a column direction to form a plurality of rows of pixel units and a plurality of columns of pixel units. <FIG> shows three rows of pixel units and three columns of pixel units, and the embodiment of the present disclosure will be described by taking this case as an example. For example, the row direction is a horizontal direction, and the column direction is a vertical direction. The functional signal line <NUM> comprises a first signal line <NUM> extending along a first direction D1, and the first signal line <NUM> extends along a row of pixel units. For example, the first signal line <NUM> is located in the display area <NUM>.

As shown in <FIG>, in order to further reduce the resistance, the functional signal line <NUM> further comprises a second signal line <NUM> extending along a second direction D2, the second signal line <NUM> is located in the peripheral area <NUM>, the second signal line <NUM> is connected with the first signal line <NUM>, and the second direction D2 intersects the first direction D1. Furthermore, for example, the second direction D2 is perpendicular to the first direction D1. As shown in <FIG>, the first signal line <NUM> and the second signal line <NUM> are disposed in different layers, and are electrically connected by a via hole penetrating an insulation layer. In an example, not forming part of the claimed invention, the first signal line <NUM> and the second signal line <NUM> can also be disposed in the same layer.

As shown in <FIG>, the first conductive structure <NUM> comprises a first conductive line <NUM> extending along the first direction D1, and the first conductive line <NUM> extends along a row of pixel units. For example, the first conductive line <NUM> is located in the display area.

For example, as shown in <FIG>, in order to further reduce the resistance, the first conductive structure <NUM> further comprises a second conductive line <NUM> extending along the second direction D2, the second conductive line <NUM> is located in the peripheral area <NUM>, and the second conductive line <NUM> is connected with the first conductive line <NUM>. As shown in <FIG>, the first conductive line <NUM> and the second conductive line <NUM> are disposed in the same layer. Of course, the first conductive line <NUM> and the second conductive line <NUM> may also be disposed in different layers and are electrically connected through a via hole penetrating an insulation layer.

An insulation layer is disposed between different conductive pattern layers. As shown in <FIG>, the display panel further comprises an insulation layer (not shown in <FIG>, referring to <FIG>), and the insulation layer is located between the first conductive structure <NUM> and the functional signal line <NUM>, and the first conductive structure <NUM> and the functional signal line <NUM> are connected by a via hole V penetrating the insulation layer.

As shown in <FIG>, the via hole V comprises at least one of a display area via hole V1 in the display area and a peripheral area via hole V2 in the peripheral area.

As shown in <FIG>, in the top view of the display panel, the first signal line <NUM> and the first conductive line <NUM> have a first overlapping area OL1, the display area via hole V1 is located in the first overlapping area OL1, and the first signal line <NUM> and the first conductive line <NUM> are connected through the display area via hole V1. It should be noted that, in the embodiment of the present disclosure, "in the top view of the display panel" may also be regarded as being in a direction perpendicular to the substrate <NUM>.

For example, in the embodiment of the present disclosure, the direction perpendicular to the substrate <NUM> may be a thickness direction of the substrate <NUM> or a direction perpendicular to a main surface of the substrate <NUM>. For example, the top view of the display panel is a view obtained by performing orthographic projection on the display panel from the top to the bottom of the display panel.

For example, as shown in <FIG>, in order to further reduce the resistance of the functional signal line, the number of the display area via holes V1 is plural, and at least one display area via hole V1 is provided for each pixel unit <NUM>. For example, the number of the display area via holes V1 may be at least the same as the number of the pixel units. For example, the number of the display area via holes may be at least one time (such as, twice) the number of the pixel units.

For example, as shown in <FIG>, in the top view of the display panel, the second signal line <NUM> and the second conductive line <NUM> have a second overlapping area OL2, the peripheral area via hole V2 is in the second overlapping area OL2, and the second signal line <NUM> and the second conductive line <NUM> are connected through the peripheral area via hole V2.

For example, as shown in <FIG>, in order to further reduce the resistance of the functional signal line, the number of peripheral area via holes V2 is plural. For example, every two of the plurality of peripheral area via holes V2 corresponds to a row of pixel units.

In <FIG>, a case that the first conductive structure <NUM> and the functional signal line <NUM> are connected in parallel through the display area via hole V1 and the peripheral area via hole V2 is taken as an example to describe. It should be noted that, the first conductive structure <NUM> and the functional signal line <NUM> may be connected in parallel only through the display area via hole V1, or, in an example not being part of the claimed invention, the first conductive structure <NUM> and the functional signal line <NUM> may be connected in parallel only through the peripheral area via hole V2. Also, the arrangement of the display area via hole V1 and the peripheral area via hole V2 is not limited to the case shown in <FIG>.

As shown in <FIG>, in order to be compatible with the patterning process and to reduce the difficulty in fabricating the via holes, the first conductive line <NUM> is connected with the first signal line <NUM> through a transfer pattern <NUM>, the first signal line <NUM> and the transfer pattern <NUM> are connected by a via hole V11 penetrating through an insulation layer located between the first signal line <NUM> and the transfer pattern <NUM>, and the transfer pattern <NUM> and the first conductive line <NUM> are connected by a via hole V12 penetrating through an insulation layer located between the transfer pattern <NUM> and the first conductive line <NUM> (also referring to <FIG>).

<FIG> is a cross-sectional view taken along a line M-N in <FIG>. As shown in <FIG>, the functional signal line <NUM> comprises a first signal line <NUM> and a second signal line <NUM>, the first signal line <NUM> and the second signal line <NUM> are electrically connected by a via hole V0 penetrating through an interlayer insulation layer <NUM>. In the peripheral area, the second conductive line <NUM> and the second signal line <NUM> are electrically connected by a via hole V2 penetrating through an insulation layer <NUM> located between the second conductive line <NUM> and the second signal line <NUM> (functional signal line <NUM>). In the display area, the transfer pattern <NUM> and the first signal line <NUM> are connected by a via hole V11 penetrating through an interlayer insulation layer <NUM> located between the first signal line <NUM> and the transfer pattern <NUM>, and the second conductive line <NUM> and the transfer pattern <NUM> are electrically connected by a via hole V12 penetrating the insulation layer <NUM> located between the second conductive line <NUM> and the transfer pattern <NUM>. <FIG> also shows the substrate <NUM> and a buffer layer <NUM> thereon. <FIG> also shows the first overlapping area OL1 and the second overlapping area OL2.

<FIG> are top schematic diagrams of each of four conductive pattern layers of <FIG>, respectively. Please refer to <FIG> and <FIG>, the display panel comprises a first conductive pattern layer <NUM>, a second conductive pattern layer <NUM>, a third conductive pattern layer <NUM>, and a fourth conductive pattern layer <NUM>.

As shown in <FIG>, the first conductive pattern layer <NUM> comprises the gate line <NUM>, the light-emitting control signal line <NUM>, and the reset control signal line <NUM>.

As shown in <FIG>, the second conductive pattern layer <NUM> comprises the first signal line <NUM>. As shown in <FIG>, an extending direction of the first signal line <NUM> is the same as an extending direction of the gate line <NUM>. A plurality of first signal lines <NUM> are spaced apart from each other. For example, each of the first signal lines <NUM> may correspond to a row of pixel units.

As shown in <FIG>, the third conductive pattern layer <NUM> comprises the second signal line <NUM>, the data line <NUM>, the first power line <NUM>, and the transfer pattern <NUM>. For example, an extending direction of the second signal line <NUM> is the same as an extending direction of the data line <NUM>. For example, the data line <NUM> may corresponds to a column of pixel units, and the first power line <NUM> may corresponds to a column of pixel units.

As shown in <FIG>, the fourth conductive pattern layer <NUM> comprises the first conductive structure <NUM>, the first conductive structure <NUM> comprises the first conductive line <NUM> and the second conductive line <NUM> that are electrically connected. For example, the first conductive line <NUM> and the second conductive line <NUM> may be formed in the same layer, of course, may also be in different layers and be electrically connected through a via hole penetrating an insulation layer. For example, in an embodiment, the first conductive line <NUM> and a first electrode <NUM> (referring to <FIG>) are in the same layer, and the second conductive line <NUM> and a portion of the initialization signal line <NUM> located in the peripheral area are in the same layer.

For example, the functional signal line <NUM> in <FIG> may be the initialization signal line <NUM> in the pixel circuit structure. The functional signal line <NUM> may also be the first power line <NUM>, which will be described in detail in <FIG>, in an example not forming part of the claimed invention. The initialization signal line <NUM> may comprise a portion located in the display area (which may correspond to the first signal line <NUM>) and a portion located in the peripheral area (which may be correspond to the second signal line <NUM>).

<FIG> is a schematic diagram of a connection between a functional signal line and a signal input circuit in a display panel provided by an embodiment of the present disclosure. As shown in <FIG>, the second signal line <NUM> is connected with a signal input circuit <NUM>. As shown in <FIG>, the second signal line <NUM> and the first signal line <NUM> are located in different layers, and are connected through a via hole V2.

As shown in <FIG>, a portion of the functional signal line <NUM> close to the signal input circuit <NUM> may be a voltage input start terminal, and a portion of the functional signal line <NUM> away from the signal input circuit <NUM> may be a voltage input end terminal, because, in the embodiment of the present disclosure, the first conductive structure <NUM> is connected in parallel with the functional signal line <NUM>, the signal delay problem caused by the voltage drop effect between the voltage input end terminal and the voltage input start end can be reduced. Meanwhile, because the signal delay problem can be reduced, so that the signal line with a larger width may not need to be used, thereby being advantageous to improve the resolution of the display panel, and thus being advantageous to improve the display quality.

<FIG> is a top schematic diagram of a display panel provided by another embodiment of the present disclosure, not being part of the claimed invention. As shown in <FIG>, the first signal line <NUM> extends along a column of pixel units, the first conductive line <NUM> extends along a column of pixel units, and every four of the plurality of peripheral area via holes V2 correspond to a column of pixel units. As shown in <FIG>, the second signal line <NUM> extends along a row of pixel units, and the second conductive line <NUM> extends along a row of pixel units.

<FIG> is a cross-sectional view taken along a line X-Y in <FIG>. As shown in <FIG>, the first signal line <NUM> and the second signal line <NUM> are electrically connected with each other through the via hole V0 of the interlayer insulation layer <NUM> therebetween to constitute the functional signal line <NUM>. The first conductive line <NUM> and the first signal line <NUM> are electrically connected by the display area via hole V1 penetrating through the insulation layer <NUM> therebetween. The transfer pattern <NUM> and the second signal line <NUM> are electrically connected by a via hole V21 (the peripheral area via hole V2) penetrating through the interlayer insulation layer <NUM> located therebetween. The second conductive line <NUM> and the transfer pattern <NUM> are electrically connected by a via hole V22 (the peripheral area via hole V2) penetrating through the insulation layer <NUM> located therebetween.

<FIG> is a schematic diagram of a fourth conductive pattern layer in a display panel provided by an embodiment of the present disclosure. For example, as shown in <FIG>, each light-emitting unit (for example, an organic electroluminescent diode) comprises a first electrode <NUM>, first electrodes <NUM> of different light-emitting units are insulated from each other, and the first conductive structure <NUM> and the first electrode <NUM> are is in the same layer. The first conductive structure <NUM> comprises the first conductive line <NUM> and the second conductive line <NUM> which are electrically connected and in the same layer.

<FIG> is a schematic diagram of a first conductive line in a display panel provided by an embodiment of the present disclosure. As shown in <FIG>, the first conductive line <NUM> extends in a gap between first electrodes <NUM> of adjacent rows of pixel units <NUM>. Of course, similarly, the first conductive line <NUM> may also extend in a gap between first electrodes <NUM> of adjacent columns of pixel units <NUM>. As shown in <FIG>, the first conductive line <NUM> and the second conductive line <NUM> are in different layers. For example, one of the first conductive line <NUM> and the second conductive line <NUM> may be in the same layer as the first electrode <NUM>, and the other of the first conductive line <NUM> and the second conductive line <NUM> may be disposed in the same layer as the other conductive structures, but the present disclosure is not limited thereto.

<FIG> is a top schematic diagram of a first signal line and channel regions of thin film transistors in a display panel provided by an embodiment of the present disclosure.

For example, the first conductive line <NUM> comprises a first portion <NUM> having a first width and a second portion <NUM> having a second width, the first width d1 is smaller than the second width d2, in the top view of the display panel, the second portion <NUM> may overlap at least one of a channel region T1a of a drive transistor, a channel region T2a of a data writing transistor, and a channel region T3a of a threshold compensation transistor. The drive transistor, the data writing transistor, and the threshold compensation transistor here can be referred to a drive transistor T1, a data writing transistor T2, and a threshold compensation transistor T3 (for example, as shown in <FIG>) described below. The channel region T1a of the drive transistor, the channel region T2a of the data writing transistor and the channel region T3a of the threshold compensation transistor can also be referred to <FIG>. The second portion of the first conductive line is used to block the channel region of the thin film transistor, so as to further improve the stability of the thin film transistor and reduce the leakage current. In <FIG>, in the top view of the display panel, a case that the second portion <NUM> overlaps with the channel region T1a of the drive transistor, the channel region T2a of the data writing transistor and the channel region T3a of the threshold compensation transistor is taken as an example to describe. In the embodiment of the present disclosure, the second portion <NUM> may also overlap with one or two of the channel region T1a of the drive transistor, the channel region T2a of the data writing transistor and the channel region T3a of the threshold compensation transistor.

<FIG> is a cross-sectional schematic view of a display panel provided by an embodiment of the present disclosure. As compared with the display panel shown in <FIG>, the display panel further comprises a fifth conductive pattern layer <NUM>. The fifth conductive pattern layer <NUM> may be located between the third conductive pattern layer <NUM> and the fourth conductive pattern layer <NUM>. The fifth conductive pattern layer <NUM> may comprise a second conductive structure <NUM>, in this embodiment, the functional signal line <NUM> is the initialization signal line <NUM>, and the second conductive structure <NUM> is connected in parallel with the first power line <NUM>. For example, in the top view of the display panel, the second conductive structure <NUM> may be in a grid shape.

As shown in <FIG>, the fifth conductive pattern layer <NUM> may further comprise transfer patterns <NUM> and <NUM>, to facilitate to be compatible with the patterning process and to reduce the difficulty in fabricating the via holes. <FIG> also shows an insulation layer <NUM> between the fifth conductive pattern layer <NUM> and the fourth conductive pattern layer <NUM>.

The pixel circuit structure will be specifically described below. For example, the functional signal line may be one of the initialization signal line, the first power line, and the second power line. The above embodiment is described by taking a case that the functional signal line is the initialization signal line and/or the first power line as an example. It should be noted that the embodiments of the present disclosure are not limited thereto, and any signal line that provides a common voltage signal to the pixel circuit structure may be the functional signal line.

<FIG> is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure; and <FIG> is a schematic plane diagram of a display panel provided by an embodiment of the present disclosure. Referring to <FIG>, the display panel <NUM> comprises a plurality of pixel units <NUM> arranged in a matrix, each of the pixel units <NUM> comprises a pixel circuit structure <NUM>, a light-emitting element <NUM>, a gate line <NUM>, a data line <NUM>, and a voltage signal line. The light-emitting element <NUM> is an organic light-emitting element OLED, and the light-emitting element <NUM> emits red light, green light, blue light, or white light, etc., under the driving of a corresponding pixel circuit structure <NUM>. The voltage signal line can be one or plural. For example, as shown in <FIG>, the voltage signal line comprises at least one of the first power line <NUM>, the second power line <NUM>, the light-emitting control signal line <NUM>, the initialization signal line <NUM>, and the reset control signal line <NUM>.

For example, the first power line <NUM> is configured to provide a constant first voltage signal ELVDD to the pixel circuit structure <NUM>, the second power line <NUM> is configured to provide a constant second voltage signal ELVSS to the pixel circuit structure <NUM>, and the first voltage signal ELVDD is larger than the second voltage signal ELVSS. The light-emitting control signal line <NUM> is configured to provide a light-emitting control signal EM to the pixel circuit structure <NUM>. The initialization signal line <NUM> and the reset control signal line <NUM> are respectively configured to provide an initialization signal Vint and a reset control signal Reset to the pixel circuit structure <NUM>, the initialization signal Vint is a constant voltage signal, the magnitude of the initialization signal Vint may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, however the present disclosure is not limited thereto, for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.

As shown in <FIG>, the pixel circuit structure <NUM> comprises a drive transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst. The drive transistor T1 is electrically connected with the light-emitting element <NUM>, and outputs a driving current under the control of signals, such as the scan signal Scan, the data signal Data, the first voltage signal ELVDD, and the second voltage signal ELVSS, and the like, to drive the light-emitting element <NUM> to emit light.

In the pixel unit of the organic light-emitting diode display panel, a drive transistor is connected with an organic light-emitting element, and output a driving current under the control of signals, such as a data signal, a scan signal and the like, to the organic light-emitting element, thereby driving the organic light-emitting element to emit light. Because the magnitude of the gate voltage of the drive transistor is directly related to the magnitude of the driving current in the organic light-emitting element, the stabilization of the gate signal is an important factor for achieving stable light emitting of the organic light-emitting element and the display stability of the display panel.

In research, the inventors found that when the data signal is transmitted on the data line, the fluctuation of the data signal easily interferes with the gate signal of the drive transistor, for example, the data signal interferes with the gate signal through a parasitic capacitor formed between the data line and the gate electrode of the drive transistor, thereby affecting the stability of the gate signal.

As shown in <FIG>, the pixel circuit structure <NUM> further comprise a first stabilization capacitor C1 located between the data line <NUM> and the first power line <NUM>. In a case where the data signal Data on the data line <NUM> changes, the first stabilization capacitor C1 can reduce the interference of the parasitic capacitor between the data line <NUM> and the gate electrode of the drive transistor T1 on the gate signal of the drive transistor T1.

In a practical case, for example, a capacitance value of the first stabilization capacitor C1 may be designed to be greater than <NUM> times a capacitance value of the parasitic capacitor between the data line <NUM> and the gate electrode of the drive transistor T1. In a case where the capacitance value of the parasitic capacitor can be negligible compared to the first stabilization capacitor C1, the influence of the data signal Data on the gate signal through the parasitic capacitor can also be negligible.

The first stabilization capacitor C1 can have various setting modes. For example, the first stabilization capacitor may comprise a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is electrically connected with the first power line <NUM>, and the second capacitor electrode is electrically connected with the data line <NUM>. It should be noted that, the first capacitor electrode may be a part of the first power line <NUM> or an electrode that is separately provided to be electrically connected with the first power line, and these two cases are included in the range of "the first capacitor electrode is electrically connected with the first power line <NUM>". Similarly, the second capacitor electrode may be a part of the data line <NUM> or an electrode that is separately provided to be electrically connected with the data line <NUM>, and these two cases are included in the range of "the second capacitor electrode is electrically connected with the data line <NUM>".

For example, in the manufacturing process, the pixel circuit structure, which comprises a circuit layer, an insulation layer, and the like which are stacked, is prepared on a substrate of the display panel <NUM> by a semiconductor process. The first capacitor electrode and the second capacitor electrode may overlap each other in a direction perpendicular to the substrate of the display panel <NUM>, and are spaced apart from each other by an insulation layer (dielectric layer), thereby constituting a capacitor. In an actual design, the capacitance value of the first stabilization capacitor C1 can be adjusted by designing a distance between the first capacitor electrode and the second capacitor electrode, a material (i.e., a dielectric constant) of the insulation layer between the first capacitor electrode and the second capacitor electrode, and an overlapping area between the first capacitor electrode and the second capacitor electrode.

As shown in <FIG>, a first electrode of the storage capacitor Cst is electrically connected with the first power line <NUM>, and a second electrode of the storage capacitor Cst is electrically connected with a second electrode of the threshold compensation transistor <NUM>. A gate electrode of the data writing transistor T2 is electrically connected with the gate line <NUM>, a first electrode and a second electrode of the data writing transistor T2 are electrically connected with the data line <NUM> and a first electrode of the drive transistor T1, respectively. A gate electrode of the threshold compensation transistor T3 is electrically connected with the gate line <NUM>, and a first electrode and a second electrode of the threshold compensation transistor T3 are electrically connected with a second electrode and a gate electrode of the drive transistor T1, respectively.

As shown in <FIG>, a gate electrode of the first light-emitting control transistor T4 is electrically connected with the light-emitting control signal line <NUM>, a first electrode and a second electrode of the first light-emitting control transistor T4 are electrically connected with the first power line <NUM> and the first electrode of the drive transistor T1, respectively. A gate electrode of the second light-emitting control transistor T5 is electrically connected with the light-emitting control signal line <NUM>, a first electrode and a second electrode of the second light-emitting control transistor T5 are electrically connected with the second electrode of the drive transistor T1 and a first electrode of the light-emitting element <NUM>, respectively. A gate electrode of the first reset transistor T6 is electrically connected with the reset control signal line <NUM>, and a first electrode and a second electrode of the first reset transistor T6 are electrically connected with the initialization signal line <NUM> and the gate electrode of the drive transistor T1, respectively. A gate electrode of the second reset transistor T7 is electrically connected with the reset control signal line <NUM>, and a first electrode and a second electrode of the second reset transistor T7 are electrically connected with the initialization signal line <NUM> and the first electrode (which may be a pixel electrode, such as an anode, of the OLED) of the light-emitting element <NUM>, respectively. A second electrode (which may be a common electrode, such as a cathode, of the OLED) of the light-emitting element <NUM> is electrically connected with the second power line <NUM>.

It should be noted that, transistors used in the embodiment of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the like characteristics. A source electrode and a drain electrode of the transistor used herein may be symmetrical in structure, so the source electrode and the drain electrode of the transistor may have no difference in structure. In the embodiments of the present disclosure, in order to distinguish two electrodes of the transistor apart from a gate electrode, one of the two electrodes is directly referred to as a first electrode, and the other of the two electrodes is referred to as a second electrode, and therefore the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure are interchangeable as required. For example, the first electrode of the transistor described in the embodiment of the present disclosure may be the source electrode, and the second electrode may be the drain electrode; alternatively, the first electrode of the transistor may be the drain electrode, and the second electrode may be the source electrode.

In addition, the transistors may be classified into N-type transistors and P-type transistors according to the characteristics of the transistors. The embodiments of the present disclosure illustrate the technical solution of the present disclosure in detail by taking the transistors as P-type transistors as an example. Based on the description and teaching of the implementations of the present disclosure, one of ordinary skill in the art can easily think of an implementation in which at least some of the transistors in the pixel circuit structure of the embodiment of the present disclosure adopt N-type transistors, that is, an implementation of using an N-type transistor or a combination of an N-type transistor and a P-type transistor, without any inventive work, therefore, these implementations are also within the scope of the present disclosure.

For example, the active layer of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polycrystalline silicon (such as low temperature poly-silicon), or metal oxide semiconductor material (such as, IGZO, AZO, etc.). In an example, the transistors are all P-type LTPS (low temperature poly-silicon) thin film transistors. In another example, the threshold compensation transistor T3 and the first reset transistor T6 that are directly connected with the gate electrode of the drive transistor T1 may be metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (such as, IGZO, AZO, etc.), the metal oxide semiconductor thin film transistor has a low leakage current and can help to reduce the leakage current of the gate electrode of the drive transistor T1.

For example, the transistors used in the embodiments of the present disclosure may comprise various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure. In an example, the threshold compensation transistor T3 and the first reset transistor T6 that are directly connected with the gate electrode of the drive transistor T1 are double-gate thin film transistors, so as to help to reduce the leakage current of the gate electrode of the drive transistor T1.

For example, as shown in <FIG>, the display panel <NUM> provided by the embodiment of the present disclosure further comprises: a data driver <NUM>, a scan driver <NUM>, and a controller <NUM>. The data driver <NUM> is configured to provide the data signal Data to the pixel unit <NUM> according to an instruction of the controller <NUM>; the scan driver <NUM> is configured to provide the light-emitting control signal EM, the scan signal Scan, the reset control signal Reset, and the like to the pixel unit <NUM> according to instruction of the controller <NUM>. For example, the scan driver <NUM> is a GOA (Gate on Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel. For example, different drivers may be adopted to provide the light-emitting control signal EM and the scan signal Scan, respectively. For example, the display panel <NUM> further comprises a power source (not shown) to provide the above voltage signals, the power source may be a voltage power source or a current power source as needed, and the power source is configured to provide the first power voltage ELVDD, the second power voltage ELVSS, the initialization signal Vint, and the like to the pixel unit <NUM> through the first power line <NUM>, the second power line <NUM>, and the initialization signal line <NUM>, respectively.

<FIG> is a timing signal diagram of a pixel unit in a display panel provided by an embodiment of the present disclosure. A driving method of a pixel unit in the display panel provided by the embodiment of the present disclosure will be described below with reference to <FIG>.

As shown in <FIG>, in a display period of one frame, the driving method of the pixel unit comprises a reset phase t1, a data writing and threshold compensation phase t2, and a light-emitting phase t3.

In the reset phase t1, the light-emitting control signal EM is set to be a turn-off voltage, the reset control signal Reset is set to be a turn-on voltage, and the scan signal Scan is set to be a turn-off voltage.

In the data writing and threshold compensation phase t2, the light-emitting control signal EM is set to be a turn-off voltage, the reset control signal Reset is set to be a turn-off voltage, and the scan signal Scan is set to be a turn-on voltage.

In the light-emitting phase t3, the light-emitting control signal EM is set to be a turn-on voltage, the reset control signal Reset is set to be a turn-off voltage, and the scan signal Scan is set to be a turn-off voltage.

For example, the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can make a first electrode and a second electrode of a corresponding transistor be turned on, and the turn-off voltage refers to a voltage that can make the first electrode and the second electrode of the corresponding transistor be turned off. In a case where the transistor is a P-type transistor, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V); in a case where the transistor is a N-type transistor, the turn-on voltage is a high voltage (for example, 5V), and the turn-off voltage is a low voltage (for example, 0V). The driving waveforms shown in <FIG> are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V).

Please refer to <FIG> and <FIG> together, in the reset phase t1, the light-emitting control signal EM is a turn-off voltage, the reset control signal Reset is a turn-on voltage, and the scan signal Scan is a turn-off voltage. In this case, the first reset transistor T6 and the second reset transistor T7 are both in a turn-on state, and the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, and the second light-emitting control transistor T5 are all in a turn-off state. An initialization signal (an initialization voltage) Vint is transmitted to the gate electrode of the drive transistor T1 by the first reset transistor T6 and then is stored by the storage capacitor Cst, so as to reset the drive transistor T1 and eliminate the data stored during emitting light in the last time (a previous frame), and the second reset transistor T7 transmits the initialization signal Vint to the first electrode of the light-emitting element <NUM> to reset the light-emitting element <NUM>.

In the data writing and threshold compensation phase t2, the light-emitting control signal EM is a turn-off voltage, the reset control signal Reset is a turn-off voltage, and the scan signal Scan is a turn-on voltage. In this case, the data writing transistor T2 and the threshold compensation transistor T3 are in a turn-on state, and the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6 and the second reset transistor T7 are all in a turn-off state. At this time, the data writing transistor T2 transmits the data signal voltage Vdata to the first electrode of the drive transistor T1, that is, the data writing transistor T2 receives the scan signal Scan and the data signal Data and writes the data signal Data to the first electrode of the drive transistor T1 according to the scan signal Scan. The threshold compensation transistor T3 is turned on to connect the drive transistor T1 into a diode structure, therefore, the gate electrode of the drive transistor T1 can be charged. After the charging is completed, the gate voltage of the drive transistor T1 is Vdata+Vth, where Vdata is the data signal voltage, and Vth is a threshold voltage of the drive transistor T1, that is, the threshold compensation transistor T3 receives the scan signal Scan and performs threshold voltage compensation on the gate voltage of the drive transistor T1 according to the scan signal Scan. In this stage, a voltage difference between two ends of the storage capacitor Cst is ELVDD-Vdata -Vth.

In the light-emitting phase t3, the light-emitting control signal EM is a turn-on voltage, the reset control signal Reset is a turn-off voltage, and the scan signal Scan is a turn-off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in a turn-on state, and the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are all in a turn-off state. The first power signal ELVDD is transmitted to the first electrode of the drive transistor T1 through the first light-emitting control transistor T4, the gate voltage of the drive transistor T1 is maintained at Vdata+Vth, a light-emitting current I flows into the light-emitting element <NUM> through the first light-emitting control transistor T4, the drive transistor T1, and the second light-emitting control transistor T5, and the light-emitting element <NUM> emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM, and control the light-emitting element <NUM> to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:
<MAT>
where, <MAT>, µn is a channel mobility of the drive transistor, Cox is a channel capacitance per unit area of the drive transistor T1, W and L are a channel width and a channel length of the drive transistor T1, respectively, and Vgs is a voltage difference between the gate electrode and the source electrode (that is, the first electrode of the drive transistor T1 in the embodiment) of the drive transistor T1.

It can be seen from the above equation that the current flowing through the light-emitting element <NUM> is independent of the threshold voltage of the drive transistor T1. Therefore, the pixel circuit structure is very well compensated for the threshold voltage of the drive transistor T1.

For example, in the pixel array of the display panel, in order to facilitate wiring, the reset control signal line <NUM> can be set as the scan line of the pixel units in the previous row, that is, the reset control signal line is the scan signal Scan(n-<NUM>) of the pixel units in the previous row, thereby reducing the number of wirings and signals.

For example, the ratio of the length of time of the light-emitting phase t3 to the display period of one frame can be adjusted. In this way, the luminescence brightness can be controlled by adjusting the ratio of the length of time of the light-emitting phase t3 to the display period of one frame. For example, the ratio of the length of time of the light-emitting phase t3 to the display period of one frame is adjusted by controlling the scan driver <NUM> in the display panel or an additionally provided driver.

For example, in other examples, the first stabilization capacitor C1 may also be disposed between the data line <NUM> and other signal line that provides a constant voltage signal. For example, the first stabilization capacitor C1 is disposed between the data line <NUM> and the second power line <NUM>, or, the first stabilization capacitor C1 is disposed between the data line <NUM> and the initialization signal line <NUM>. In other examples, the first light-emitting control transistor T4 or the second light-emitting control transistor T5 may not be provided, or the first reset transistor T6 or the second reset transistor T7 may not be provided, or the like, that is, the embodiment of the present disclosure is not limited to the specific pixel circuit shown in <FIG>, other pixel circuit capable of achieving to compensate for the drive transistor can be adopted. Based on the description and teachings of the implementations of the present disclosure, other arrangements that can be easily conceived by those skilled in the art without any inventive work are within the scope of the present disclosure.

<FIG> is a schematic diagram of a display panel provided by another embodiment of the present disclosure. As shown in <FIG>, a difference between the display panel provided by this embodiment and the display panel in <FIG> is that the display panel <NUM> further comprises a second stabilization capacitor C2 and/or a third stabilization capacitor C3, the second stabilization capacitor C2 is disposed between the data line <NUM> and the first electrode of the drive transistor T1, and the third stabilization capacitor C3 is disposed between the first power line <NUM> and the first electrode of the drive transistor T1. Due to the presence of the second stabilization capacitor C2, the interference of the parasitic capacitance between the data line <NUM> and the gate electrode of the drive transistor T1 to the gate signal of the drive transistor T1 is further reduced. Due to the presence of the third stabilization capacitor C3, the interference of the parasitic capacitance between the first power line <NUM> and the gate electrode of the drive transistor T1 to the gate signal of the drive transistor T1 is reduced.

<FIG> is a schematic diagram (exemplary layout) of an exemplary plane structure of a display panel <NUM> shown in <FIG>. For the sake of clarity, only the structures of the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the storage capacitor Cst, and the first stabilization capacitor C1 are shown in the figure, and the structures of other transistors are not shown. <FIG> is a cross-sectional view of the display panel in <FIG> taken along a line I-I', and <FIG> is a cross-sectional view of the display panel in <FIG> taken along a line II-II'. The display panel <NUM> provided by the embodiment of the present disclosure will be exemplarily described below with reference to <FIG>.

It should be understood herein that in the present disclosure, "same layer" refers to a layer structure formed by a film layer for forming a specific pattern by the same film forming process and then by one patterning process using the same mask. Depending on the different specific patterns, the same patterning process may comprise several exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. For example, in the embodiment of the present disclosure, a pattern of a plurality of components/elements can be disposed in the same layer, which cannot increase the number of the film layers, reduce the thickness of the display panel, and simplify the manufacturing process.

It should also be noted that the electrical connection between A and B referred to in the present disclosure comprises the case where A is a part of B and the case where B is a part of A.

For convenience of description, in the figures and the following description, T1g, T1s, T1d, T1a respectively indicate the gate electrode, the first electrode, the second electrode, and the channel region of the drive transistor T1. T2g, T2s, T2d, T2a respectively indicate the gate electrode, the first electrode, the second electrode, and the channel region of the data writing transistor T2. T3g, T3s, T3d, T3a respectively indicate the gate electrode, the first electrode, the second electrode, and the channel region of the threshold compensation transistor T3, and Csa and Csb respectively denote the first electrode and the second electrode of the storage capacitor Cst.

As shown in the figures, the display pane <NUM> comprises a substrate <NUM> and a semiconductor pattern layer <NUM>, a first insulation layer <NUM>, a first conductive pattern layer <NUM>, a second insulation layer <NUM>, a second conductive pattern layer <NUM>, an interlayer insulation layer <NUM>, and a third conductive pattern layer <NUM> which are sequentially stacked on the substrate <NUM>.

For example, the semiconductor pattern layer <NUM> comprises an active layer T1a of the drive transistor T1, an active layer T2a of the data writing transistor T2, and an active layer T3a of the threshold compensation transistor T3.

For example, the first conductive pattern layer <NUM> comprises a gate line <NUM>, a second electrode Csb of the storage capacitor Cst, a gate electrode T1g of the drive transistor T1, a gate electrode T2g of the data writing transistor, and a gate electrode T3g of the threshold compensation transistor.

For example, the second conductive pattern layer <NUM> comprises a first electrode Cst of the storage capacitor Cst.

For example, the first electrode Csa of the storage capacitor Cst and the gate electrode T1g of the drive transistor T1 overlap each other in a direction perpendicular to the substrate <NUM>.

For example, the third conductive pattern layer <NUM> comprises a data line <NUM> and a first power line <NUM>.

As shown in <FIG>, the gate line <NUM> extends in a first direction D1, and the data line <NUM> and the first power line <NUM> extend in a second direction D2 and are disposed in the same layer. For example, the first direction D1 and the second direction D2 are substantially perpendicular to each other.

In the present embodiment, the first stabilization capacitor C1 comprises a first capacitor electrode <NUM> that is separately provided and is electrically connected with the first power line <NUM>, and a second capacitor electrode of the first stabilization capacitor Cl is served by a portion of the data line <NUM> itself. In other embodiments, the second capacitor electrode of the first stabilization capacitor C1 may also separately provided as an electrode connected with the data line <NUM>.

For example, as shown in <FIG> and <FIG>, the first capacitor electrode <NUM> is disposed on a side of the data line <NUM> close to the substrate <NUM>, and is disposed in the same layer as the first electrode Csa of the storage capacitor Cst. The first capacitor electrode <NUM> is electrically connected with the first power line <NUM> through a first via hole <NUM> penetrating the interlayer insulation layer <NUM>. The first capacitor electrode <NUM> and the data line <NUM> overlap each other in the direction perpendicular to the substrate <NUM>, thereby forming the first stabilization capacitor C1.

For example, in the manufacturing process of the display panel <NUM>, the semiconductor pattern layer <NUM> is subject to a treatment to turn it to be conductive by using a self-alignment process with the first conductive pattern layer <NUM> as a mask, for example, the semiconductor pattern layer <NUM> is heavily doped by ion implantation, so that a portion of the semiconductor pattern layer <NUM> not covered by the first conductive pattern layer <NUM> is made to be conductive, to form a source region (first electrode T1s) and a drain region (second electrode T1d) of the drive transistor T1, a source region (first electrode T2s) and a drain region (second electrode T2d) of the data writing transistor T2, and a source region (first electrode T3s) and a drain region (second electrode T3d) of the threshold compensation transistor T3. A portion of the semiconductor pattern layer <NUM> covered by the first conductive pattern layer <NUM> retains semiconductor characteristics, to form channel regions T1a, T2a and T3a of the respective transistors.

For example, as shown in <FIG> and <FIG>, the display panel <NUM> further comprises a first connection electrode <NUM>, and the first connection electrode <NUM> is configured to connect the drain region of the threshold compensation transistor T3 and the gate electrode T1g of the drive transistor T1, thereby electrically connecting the second electrode T3d of the threshold compensation transistor T3 and the gate electrode T1g of the drive transistor T1.

For example, the first connection electrode <NUM> is disposed in the same layer as the data line <NUM>, and an extending direction of the first connection electrode <NUM> is the same as an extending direction of the data line <NUM>.

Referring to <FIG> and <FIG>, because the parasitic capacitance is between the data line <NUM> and the first connection electrode <NUM> or between the data line <NUM> and the second electrode T3d of the threshold compensation transistor T3, by disposing the first capacitor electrode <NUM> on a side of the data line <NUM> close to the substrate <NUM>, the first capacitor electrode <NUM> can function to raise the data line, and can increase the distance between the data line <NUM> and the first connection electrode <NUM> and the distance between the data line <NUM> and the side of the second electrode T3d of the threshold compensation transistor T3, thereby reducing the parasitic capacitance. For example, because the second electrode T3d of the threshold compensation transistor T3 is directly connected with the gate electrode of the drive transistor T1, reducing the parasitic capacitance helps to reduce the interference of the data line to the gate signal of the drive transistor T1.

For example, an orthographic projection of the first connection electrode <NUM> on the layer where the first capacitor electrode <NUM> is located (i.e., the second conductive pattern layer <NUM>) and the first capacitor electrode <NUM> overlaps each other in a direction (that is, the first direction D1) perpendicular to the direction in which the data line <NUM> extends.

For example, referring to <FIG>, an orthographic projection of the first connection electrode <NUM> on the layer where the first capacitor electrode <NUM> is located (i.e., the second conductive pattern layer <NUM>) and the first capacitor electrode <NUM> overlaps each other in a direction (that is, the first direction D1) perpendicular to the direction in which the data line <NUM> extends.

For example, an opening <NUM> is disposed in the first electrode Csa of the storage capacitor Cst, the first connection electrode <NUM> is electrically connected with the gate electrode of the drive transistor T1 (that is, the second electrode Csb of the storage capacitor Cst) through the opening <NUM> and a second via hole <NUM> penetrating the second insulation layer <NUM> and the interlayer insulation layer <NUM>.

For example, the first connection electrode <NUM> is electrically connected with the second electrode T3d of the threshold compensation transistor T3 through a third via hole <NUM> penetrating through the first insulation layer <NUM>, the second insulation layer <NUM>, and the interlayer insulation layer <NUM>.

For example, the first power line <NUM> is electrically connected with the first electrode Csa of the storage capacitor Cst through a fourth via hole <NUM> penetrating the interlayer insulation layer <NUM>.

For example, referring to <FIG>, the first electrode Csa of the storage capacitor Cst and the data line <NUM> overlap each other in a direction perpendicular to the substrate, thereby constituting a fourth stabilization capacitor C4. Because the first electrode Csa of the storage capacitor Cst is electrically connected with the first power line <NUM>, the fourth stabilization capacitor C4 is also formed between the first power line and the data line, thus further reducing the interference of the parasitic capacitance between the data line <NUM> and the gate electrode of the drive transistor T1 on the gate signal of the drive transistor T1. For example, materials of the first insulation layer <NUM>, the second insulation layer <NUM>, and the interlayer insulation layer <NUM> may comprise inorganic insulation materials such as silicon nitride, silicon oxynitride, or the like, or aluminum oxide, titanium nitride, or the like. For example, the insulation materials may further comprise organic insulation materials such as acrylic acid, polymethyl methacrylate (PMMA), or the like. For example, the insulation layer may be a single layer structure or a multilayer structure.

For example, materials of the first conductive pattern layer <NUM>, the second conductive pattern layer <NUM>, the third conductive pattern layer <NUM>, the fourth conductive pattern layer <NUM>, the functional signal line, the first conductive structure, and the second conductive structure comprise gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and an alloy material obtained by combining the above metals; or a conductive metal oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc oxide aluminum (AZO), and the like.

For example, the display panel <NUM> further comprise a buffer layer <NUM> disposed between the substrate <NUM> and the semiconductor pattern layer <NUM>. For example, the substrate <NUM> is a glass substrate, and the buffer layer <NUM> is silicon dioxide and is used to prevent impurities (metal ions) in the substrate <NUM> from diffusing into the pixel circuit structure.

In the embodiment of the present disclosure, the functional signal line may comprise at least one of the initialization signal line <NUM>, the light-emitting control signal line <NUM>, the reset control signal line <NUM>, the first power line <NUM>, and the second power line <NUM>.

For example, in an embodiment, the array substrate sequentially comprises: a substrate, a polysilicon layer, a first gate insulation layer, a first conductive pattern layer (comprising a gate line, gate electrodes, a second electrode of a storage capacitor), a second gate insulation layer, a second conductive pattern layer (comprising an initialization signal line, a first electrode of the storage capacitor, a first connection electrode), an interlayer insulation layer, a third conductive pattern layer (comprising a data line, a first power line of the display area), a passivation layer, a planarization layer, a fourth conductive pattern layer (comprising a first electrode, a first conductive structure, the first electrode may be an anode of the OLED), a light emitting layer, a second electrode (which may be a cathode of the OLED). The functional signal line is the first power line, and the first conductive structure and the first electrode are disposed in the same layer, and the first conductive structure is connected in parallel with the first power line.

In the embodiments of the present disclosure, the first conductive structure <NUM> may also be disposed separately. For example, the array substrate comprises a substrate, a polysilicon layer, a first gate insulation layer, a first conductive pattern layer (comprising a gate line, gate electrodes, a second electrode of a storage capacitor), a second gate insulation layer, a second conductive pattern layer (comprising an initialization signal line, a first electrode of the storage capacitor, a first connection electrode), an interlayer insulation layer, a third conductive pattern layer (comprising a data line, a first power line of the display area), an organic insulation layer, a passivation layer, a fourth conductive pattern layer (comprising a first conductive structure), a second planarization layer, an anode layer of the OLED, a light emitting layer, a cathode layer of the OLED. The organic insulation layer and the passivation layer are interposed between the fourth conductive pattern layer and the third conductive pattern layer, and the passivation layer is directly under the fourth conductive pattern layer, which can ensure that the layer where the first conductive structure is located is completely etched, and the organic insulation layer can provide as much planarization as possible. In the embodiment, the functional signal line is the first power line, and the first conductive structure is connected in parallel with the first power line.

The pixel circuit structure in the display panel provided by the embodiment of the present disclosure is not limited to the case shown in <FIG>, and a pixel circuit structure of other structures may also be used. For example, at least one of the first stabilization capacitor C1, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, and the second reset transistor T6 may be not provided.

For example, the display panel provided by the embodiment of the present disclosure can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. For example, the display panel is an organic light-emitting diode display panel.

An embodiment of the present disclosure further provides a display device, comprising the above display panel. For example, the display device may be an electronic device, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, to which the display panel is applied. For example, the display device is an organic light-emitting diode display device.

Claim 1:
A display panel, comprising:
a substrate (<NUM>), comprising a display area (<NUM>) and a peripheral area (<NUM>) on at least one side of the display area (<NUM>);
a plurality of pixel units (<NUM>), in the display area (<NUM>), each pixel unit (<NUM>) comprising a light-emitting unit (<NUM>) and a pixel circuit structure (<NUM>) for providing a driving current to the light-emitting unit (<NUM>), and the light-emitting unit (<NUM>) being an electroluminescent element;
a functional signal line (<NUM>), connected with the pixel circuit structure (<NUM>) of each pixel unit (<NUM>) and providing a common voltage signal for the pixel circuit structure (<NUM>); and
a first conductive structure (<NUM>), connected in parallel with the functional signal line (<NUM>) and located at a layer different from that of the functional signal line (<NUM>),
wherein the plurality of pixel units (<NUM>) extend along a row direction and a column direction to form a plurality of rows of pixel units (<NUM>) and a plurality of columns of pixel units (<NUM>), the functional signal line (<NUM>) comprises a first signal line (<NUM>) extending along a first direction, and the first signal line (<NUM>) extends along a row of pixel units (<NUM>) or a column of pixel units (<NUM>),
wherein the functional signal line (<NUM>) comprises a second signal line (<NUM>) extending along a second direction, the second signal line (<NUM>) is in the peripheral area (<NUM>), the second signal line (<NUM>) is connected with the first signal line (<NUM>), and the second direction intersects the first direction, ,
wherein the first conductive structure (<NUM>) comprises a first conductive line (<NUM>) extending along the first direction, and the first conductive line (<NUM>) extends along a row of pixel units (<NUM>) or a column of pixel units (<NUM>),
characterized in that:
the first conductive line (<NUM>) is connected with the first signal line (<NUM>) through a transfer pattern (<NUM>),
the first conductive line (<NUM>) and the transfer pattern (<NUM>) are connected by a via hole penetrating through an insulation layer located between the first conductive line (<NUM>) and the transfer pattern (<NUM>),
the transfer pattern (<NUM>) and the first signal line (<NUM>) are connected by a via hole penetrating through an insulation layer located between the transfer pattern (<NUM>) and the first signal line (<NUM>), and
the transfer pattern (<NUM>) is in a same layer as the second signal line (<NUM>).