Patent Description:
Along with systems becoming increasingly complicated and growing in size, some proposed systems include a plurality of System-on-Chips (SoCs).

To consolidate the security of information equipment, there are conventionally proposed techniques where a memory unit stores therein encrypted data and instruction code and a processor decrypts the encrypted instruction code and carries out instructions.

<CIT> discloses that boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its boot code partition in accordance with the boot code sequence and signals to a next processor the successful and uncompromised execution of its boot code partition. If any of the processors does not signal successful completion and/or uncompromised execution of its boot code partition, the boot operation fails. The processors may be arranged, with regard to the boot operation, in a daisy chain, ring, or master/slave arrangement, for example.

To ensure the reliability of a system including a plurality of SoCs, it is considered effective, for example, to provide each of the SoCs with a non-volatile memory device for storing encrypted boot code and a controller on a different chip connected thereto for decrypting the boot code. This, however, creates the problem of increased number of elements (e.g. chips) included in the system, which leads to increasing costs.

According to the processing apparatus including a plurality of semiconductor integrated circuits disclosed herein, it is possible to enhance its reliability with a simple configuration.

These and other objects, features and advantages of the present invention will become apparent from the following detailed description , which is to be read in connection with the accompanying drawings.

The present invention will be described below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

<FIG> illustrates an exemplary processor.

A processor <NUM> includes semiconductor integrated circuits <NUM>, <NUM>, and <NUM>, a memory unit <NUM>, and a network <NUM>.

Each of the semiconductor integrated circuits <NUM> to <NUM> is, for example, a single SoC. The processor <NUM> of <FIG> has three semiconductor integrated circuits <NUM> to <NUM>; however, the processor <NUM> only needs to include two or more semiconductor integrated circuits, and the applicable scope of the technology is not limited to this example. Note that the processor <NUM> may be implemented with a single SoC including two or more semiconductor integrated circuits thereon.

The semiconductor integrated circuit <NUM> includes a control circuit 11a, a memory circuit 11b, a decryption processing circuit 11c, a secure communication circuit 11d, and a power supply control circuit 11e, which are all connected to a system bus 11f.

The control circuit 11a is, for example, a microcontroller or central processing unit (CPU), and controls each element of the semiconductor integrated circuit <NUM> via the system bus 11f.

The memory circuit 11b may be volatile semiconductor memory such as random access memory (RAM), or a non-volatile storage device such as flash memory. The memory circuit 11b stores therein programs to be executed by the control circuit 11a (boot code of the control circuit 11a) and various data.

The decryption processing circuit 11c decrypts encrypted boot code 20a and route information 21a which indicates a delivery route of the boot code 20a, read from the memory unit <NUM>. Note that an example of the decryption and encryption processes is described later.

The secure communication circuit 11d has a function of encrypting data and transmitting it to a destination (the semiconductor integrated circuit <NUM>) via the network <NUM>. The secure communication circuit 11d encrypts again the boot code 20a and the route information 21a decrypted by the decryption processing circuit 11c, to thereby generate boot code 20b and route information 21b and then transmits encrypted data 22a including the generated boot code 20b and route information 21b, as illustrated in <FIG>. Further, upon receiving, from the destination, an acknowledgement signal indicating receipt completion, the secure communication circuit 11d notifies the control circuit 11a of the completion of data receipt at the destination. Then, upon receiving, from the control circuit 11a, a signal instructing start-up of individual control circuits of the semiconductor integrated circuits <NUM> and <NUM> (e.g. a control circuit 12a in the case of the semiconductor integrated circuit <NUM>), the secure communication circuit 11d transmits a boot instruction signal to the semiconductor integrated circuits <NUM> and <NUM>.

The power supply control circuit 11e provides, via the system bus 11f, power supply and control over turning on and off individual elements of the semiconductor integrated circuit <NUM>, to thereby decide whether to start up each of the elements.

The semiconductor integrated circuit <NUM> includes the control circuit 12a, a memory circuit 12b, a secure communication circuit 12c, and a power supply control circuit 12d, which are all connected to a system bus 12e.

The control circuit 12a is, for example, a microcontroller or CPU, and controls each element of the semiconductor integrated circuit <NUM> via the system bus 12e, as with the control circuit 11a of the semiconductor integrated circuit <NUM>.

The memory circuit 12b may be volatile semiconductor memory such as RAM, or a non-volatile storage device such as flash memory. The memory circuit 12b stores therein boot code 20c to be executed by the control circuit 12a and various types of data.

The secure communication circuit 12c receives the encrypted data 22a via the network <NUM> and decrypts the encrypted boot code 20b and route information 21b. The secure communication circuit 12c encrypts again the decrypted boot code 20b and route information 21b, to thereby generate boot code 20c and route information 21c, as illustrated in <FIG>. Subsequently, the secure communication circuit 12c transmits encrypted data 22b including the boot code 20c and the route information 21c to a destination (the semiconductor integrated circuit <NUM>) via the network <NUM>. Further, the secure communication circuit 12c transmits an acknowledgement signal indicating the completion of receiving the encrypted data 22a, to the semiconductor integrated circuit <NUM> via the network <NUM>. In addition, upon receiving a boot instruction signal transmitted by the semiconductor integrated circuit <NUM>, the secure communication circuit 12c notifies the power supply control circuit 12d of the receipt of the boot instruction signal.

The power supply control circuit 12d provides, via the system bus 12e, power supply and control over turning on and off individual elements of the semiconductor integrated circuit <NUM>, to thereby decide whether to start up each of the elements. For example, at power-on of the processor <NUM>, the power supply control circuit 12d starts up the secure communication circuit 12c. Then, upon receiving notice of receipt of a boot instruction signal from the secure communication circuit 12c, the power supply control circuit 12d starts up the control circuit 12a.

The semiconductor integrated circuit <NUM> also includes similar elements to those of the semiconductor integrated circuit <NUM> although <FIG> omits representation of such elements.

The memory unit <NUM> is, for example, a non-volatile storage device such as flash memory, and stores therein the encrypted boot code 20a used in boot processes of the semiconductor integrated circuits <NUM> and <NUM> and the encrypted route information 21a indicating a delivery route of the boot code 20a. Note that the memory unit <NUM> may be provided in the semiconductor integrated circuit <NUM>. The boot code 20a may be common boot code shared between the semiconductor integrated circuits <NUM> and <NUM>, or may include different boot code modules each dedicated to the individual semiconductor integrated circuits <NUM> and <NUM>. The route information 21a may be unencrypted.

The network <NUM> is used for secure boot code delivery and monitoring the internal state of the processor <NUM>, and not connected to the outside of the processor <NUM>. For example, Ethernet (registered trademark) may be used as the network <NUM>.

In the above-described processor <NUM>, the semiconductor integrated circuit <NUM> serves as a master while the semiconductor integrated circuits <NUM> and <NUM> serve as slaves. When the processor <NUM> is powered on, the power supply control circuits 11e and 12d start up (N. a power supply control circuit (not illustrated) of the semiconductor integrated circuit <NUM> also starts up).

Then, the power supply control circuit 11e first starts up the control circuit 11a. The power supply control circuit 11e (or the control circuit 11a) starts up the decryption processing circuit 11c and the secure communication circuit 11d. Herewith, under the control of the control circuit 11a, the decryption processing circuit 11c reads the encrypted boot code 20a and route information 21a from the memory unit <NUM> and decrypts them, and then supplies the decrypted data to the system bus 11f. Next, the secure communication circuit 11d encrypts again the decrypted data obtained from the boot code 20a and the route information 21a by the decryption processing circuit 11c, to thereby generate the boot code 20b and the route information 21b. Note that the route information 21b may be unencrypted.

In the case where the boot code 20a includes different boot code modules each dedicated to the individual semiconductor integrated circuits <NUM> and <NUM>, the boot code 20b may include different boot code modules each dedicated to the individual semiconductor integrated circuits <NUM> and <NUM>, or may include only the boot code module dedicated to the semiconductor integrated circuit <NUM> without including the boot code module for the semiconductor integrated circuit <NUM>. On the other hand, in the case where the boot code 20a includes common boot code shared between the semiconductor integrated circuits <NUM> and <NUM>, the boot code 20b includes the common boot code.

Then, the secure communication circuit 11d identifies a destination (the semiconductor integrated circuit <NUM> in the example of <FIG>) based on the data obtained by decrypting the route information 21a, and transmits the encrypted data 22a including the boot code 20b and the route information 21b to the identified destination via the network <NUM>. Note that, at this time, the control circuit 11a may determine whether the decrypted boot code is appropriate.

On the other hand, in the semiconductor integrated circuit <NUM>, after the power supply control circuit 12d starts up, the power supply control circuit 12d starts up the secure communication circuit 12c without starting up the control circuit 12a. Upon receiving the encrypted data 22a, the secure communication circuit 12c decrypts the encrypted boot code 20b and route information 21b. Then, the secure communication circuit 12c stores, in the memory circuit 12b, the boot code 20c obtained from the decryption.

Further, the secure communication circuit 12c transmits, to the semiconductor integrated circuit <NUM>, an acknowledgement signal indicating the receipt completion of the encrypted data 22a. In addition, if determining, based on the data obtained by decrypting the route information 21b, that a delivery route ahead of the semiconductor integrated circuit <NUM> is designated, the secure communication circuit 12c encrypts again data obtained by decrypting the boot code 20b and the route information 21b to thereby generate the encrypted data 22b including the encrypted boot code 20c and route information 21c, and then transmits the encrypted data 22b to a destination. In the example of <FIG>, the semiconductor integrated circuit <NUM> is the transmission destination of the semiconductor integrated circuit <NUM>. Note that the route information 21c may be unencrypted.

In the case where the boot code 20a includes different boot code modules each dedicated to the individual semiconductor integrated circuits <NUM> and <NUM>, the boot code 20c needs to include only the boot code module dedicated to the semiconductor integrated circuit <NUM> and need not include the boot code module dedicated to the semiconductor integrated circuit <NUM>. On the other hand, in the case where the boot code 20a includes common boot code shared between the semiconductor integrated circuits <NUM> and <NUM>, the boot code 20c includes the common boot code.

Upon receiving the encrypted data 22b, the semiconductor integrated circuit <NUM> undergoes a similar process to that described above for the semiconductor integrated circuit <NUM>.

Upon receiving an acknowledgement signal indicating the receipt completion, transmitted from each of the semiconductor integrated circuits <NUM> and <NUM>, the secure communication circuit 11d of the semiconductor integrated circuit <NUM> notifies the control circuit 11a of the receipt of the acknowledgement signals. When determining, based on the notice from the secure communication circuit 11d, that the receipt of the encrypted data 22a and 22b has been completed at the semiconductor integrated circuits <NUM> and <NUM>, respectively, the control circuit 11a sends a notice that prompts the secure communication circuit 11d to instruct the start-up of the individual control circuits of the semiconductor integrated circuits <NUM> and <NUM>. Upon receiving the notice, the secure communication circuit 11d transmits a boot instruction signal to the semiconductor integrated circuits <NUM> and <NUM>.

Upon receiving the boot instruction signal, the secure communication circuit 12c of the semiconductor integrated circuit <NUM> notifies the power supply control circuit 12d of the receipt of the boot instruction signal. Upon receiving the notice, the power supply control circuit 12d starts up the control circuit 12a, which subsequently executes a boot process based on the boot code stored in the memory circuit 12b.

A similar boot process to that described above for the semiconductor integrated circuit <NUM> takes place in the semiconductor integrated circuit <NUM> in response to receiving the boot instruction signal.

As has been described above, the semiconductor integrated circuit <NUM> transmits the encrypted data 22a including the encrypted boot code 20b and the encrypted route information 21b that indicates a delivery route of the boot code 20b. Then, upon receiving an acknowledgement signal indicating the completion of receiving the encrypted data 22a, the semiconductor integrated circuit <NUM> transmits a boot instruction signal. On the other hand, the semiconductor integrated circuit <NUM> receives the encrypted data 22a from the semiconductor integrated circuit <NUM> and transmits the acknowledgement signal to the semiconductor integrated circuit <NUM> via the network <NUM>. In addition, the semiconductor integrated circuit <NUM> generates the boot code 20c by decrypting the boot code 20b included in the encrypted data 22a, and then executes a boot process based on the boot code 20c upon receiving the boot instruction signal.

According to the processor <NUM> described above, because the semiconductor integrated circuit <NUM> supplies the encrypted boot code 20b to the semiconductor integrated circuit <NUM>, there is no need to connect a memory unit for storing boot code to the semiconductor integrated circuit <NUM>. That is, the semiconductor integrated circuit <NUM> need not manage boot code. In addition, because decryption of the encrypted boot code 20b takes place within the semiconductor integrated circuit <NUM>, there is no need to connect a controller on a different chip thereto. Thus, it is possible to enhance the reliability of the processor <NUM> with a simple configuration, which in turn is likely to reduce the cost.

In addition, the semiconductor integrated circuit <NUM> serving as a slave encrypts again decrypted boot code and route information and transmits the encrypted data to a destination (the semiconductor integrated circuit <NUM> in the example of <FIG>) based on the route information, to thereby lighten the workload of the semiconductor integrated circuit <NUM> serving as a master.

Note that the semiconductor integrated circuits <NUM> and <NUM> may encrypt data other than boot code and then transmit it.

A processor <NUM> of <FIG> includes a master <NUM> and slaves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, which are connected to networks <NUM> and <NUM>. In addition, a non-volatile memory device <NUM> is connected to the master <NUM>.

Each of the master <NUM> and the slaves <NUM> to <NUM> is, for example, a single SoC.

The network <NUM> is connected to the outside of the processor <NUM>. On the other hand, the network <NUM> is provided independently of the network <NUM>, and not connected to the outside of the processor <NUM>. For example, Ethernet (registered trademark) may be used as the network <NUM>.

The non-volatile memory device <NUM> is, for example, flash memory and stores therein boot code to be executed to start up the slaves <NUM> to <NUM>. Note that the non-volatile memory device <NUM> may be provided in the master <NUM>.

Next described are examples of hardware of the master <NUM> and the slaves <NUM> to <NUM>. Note that the following description is directed to elements engaged in a secure communication process using the network <NUM> while omitting those engaged in a communication process using the network <NUM>.

The master <NUM> has functions similar to those of the semiconductor integrated circuit <NUM> of the processor <NUM> according to <FIG>. The master <NUM> includes a microcontroller unit (MCU) 31a, a read only memory (ROM) 31b, a RAM 31c, a power supply control circuit 31d, an encryption/decryption processing circuit 31e, and a secure communication circuit 31f, which are all connected to a system bus <NUM>.

The MCU 31a controls, based on a program stored in the ROM 31b, each element of the master <NUM> via the system bus <NUM>. Note that a processor like a CPU may be used in place of the MCU 31a.

The ROM 31b is a non-volatile storage device such as flash memory and stores therein programs to be executed by the MCU 31a (e.g. boot code of the MCU 31a) and various types of data. The RAM 31c temporarily stores at least part of programs to be executed by the MCU 31a. The RAM 31c also stores therein various types of data to be used by the MCU 31a for its processing.

The power supply control circuit 31d provides, via the system bus <NUM>, power supply and control over turning on and off individual elements of the master <NUM>, to thereby decide whether to start up each of the elements.

The encryption/decryption processing circuit 31e encrypts, for example, boot code of MCUs of the slaves <NUM> to <NUM> and route information indicating a delivery route of the boot code, and preliminarily stores these in the non-volatile memory device <NUM>. Further, the encryption/decryption processing circuit 31e decrypts encrypted boot code and route information read from the non-volatile memory device <NUM>.

The secure communication circuit 31f encrypts again the boot code and route information and transmits encrypted data including the encrypted boot code and route information to a destination (one of the slaves <NUM> to <NUM>). Further, upon receiving, from the destination, an acknowledgement signal indicating the receipt of the encrypted data, the secure communication circuit 31f notifies the MCU 31a of the successful data receipt at the destination. Then, upon receiving, from the MCU 31a, a signal which indicates instructing start-up of the MCUs of all the slaves <NUM> to <NUM>, the secure communication circuit 31f transmits a boot instruction signal to the slaves <NUM> to <NUM>.

Note that the secure communication circuit 31f may encrypt and then transmit data other than the encrypted boot code and route information.

<FIG> illustrates an exemplary encryption/decryption processing circuit.

The encryption/decryption processing circuit 31e includes a control circuit 31e1 and an encryption/decryption circuit 31e2.

The control circuit 31e1 controls an encryption/decryption process using the encryption/decryption circuit 31e2.

The encryption/decryption circuit 31e2 performs an encryption/decryption process on data exchanged with the non-volatile memory device <NUM>. The following describes an example of the encryption/decryption process using a hardware key and a common encryption key.

For example, at initial startup of the master <NUM>, the encryption/decryption circuit 31e2 encrypts, using a common encryption key, boot code of the slaves <NUM> to <NUM> and route information indicating a delivery route of the boot code, supplied from the ROM 31b or the RAM 31c via the system bus <NUM>. Further, the encryption/decryption circuit 31e2 encrypts the common encryption key using the hardware key.

Based on an address designated by the MCU 31a (a write address) via the system bus <NUM>, the control circuit 31e1 stores, in the non-volatile memory device <NUM>, the boot code and route information encrypted with the common encryption key and the common encryption key encrypted with the hardware key.

At each start-up after the initial time, the control circuit 31e1 reads, based on an address designated by the MCU 31a (a read address), the encrypted common encryption key, boot code, and route information from the non-volatile memory device <NUM>. Then, under the control of the control circuit 31e1, the encryption/decryption circuit 31e2 decrypts the common encryption key with the hardware key and decrypts the boot code and the route information with the decrypted common encryption key.

Note that, instead of providing the encryption/decryption circuit 31e2, the above-described boot code, route information, and common encryption key may be encrypted in advance by a system different from the processor <NUM> and then stored in the non-volatile memory device <NUM>.

<FIG> illustrates an exemplary secure communication circuit.

The secure communication circuit 31f includes a direct memory access (DMA) processing circuit 31f1, a packet processing circuit 31f2, an encryption/decryption circuit 31f3, a hardware key setting circuit 31f4, and a media access controller 31f5.

Based on a command supplied from the MCU 31a or the packet processing circuit 31f2, the DMA processing circuit 31f1 transmits data to the RAM 31c of the master <NUM> via the system bus <NUM>, or, to the non-volatile memory device <NUM> via the system bus <NUM> and the encryption/decryption processing circuit 31e. Also, based on a command supplied from the MCU 31a or the packet processing circuit 31f2, the DMA processing circuit 31f1 receives data from the RAM 31c of the master <NUM> via the system bus <NUM>, or, from the non-volatile memory device <NUM> via the system bus <NUM> and the encryption/decryption processing circuit 31e.

Upon receiving, from the DMA processing circuit 31f1, information stored in the RAM 31c (e.g. boot code and route information), the packet processing circuit 31f2 generates a packet based on the information and then transmits the packet to the encryption/decryption circuit 31f3. Further, upon receiving an encrypted packet from the encryption/decryption circuit 31f3, the packet processing circuit 31f2 supplies the encrypted packet to the media access controller 31f5. Upon receiving an encrypted packet from the media access controller 31f5, the packet processing circuit 31f2 transmits the encrypted packet to the encryption/decryption circuit 31f3. Further, upon receiving a decrypted packet from the encryption/decryption circuit 31f3, the packet processing circuit 31f2 supplies the decrypted packet to the DMA processing circuit 31f1.

The encryption/decryption circuit 31f3 performs, using the hardware key, encryption and decryption of a packet and hash calculation.

The hardware key is set in the hardware key setting circuit 31f4. One Time Programmable-ROM (OTP-ROM), such as an electric fuse (E-Fuse), may be used as the hardware key setting circuit 31f4.

The media access controller 31f5 exchanges, using media access control (MAC) addresses, encrypted packets with the slaves <NUM> to <NUM> via the network <NUM>.

Note that <FIG> depicts an example of the slave <NUM> amongst the slaves <NUM> to <NUM>; however, each of the remaining slaves <NUM> to <NUM> may be implemented by a similar circuit. The slave <NUM> has similar functions to those of the semiconductor integrated circuit <NUM> provided in the processor in <FIG>.

The slave <NUM> includes an MCU 32a, a RAM 32b, an application processor (AP) 32c, a power supply control circuit 32d, and a secure communication circuit 32e, which are all connected to a system bus 32f.

The MCU 32a executes a program stored in the RAM 32b, to thereby control each element of the slave <NUM> via the system bus 32f. Note that a processor such as a CPU may be used in place of the MCU 32a.

The RAM 32b stores therein, for example, boot code of the MCU 32a and boot code of the application processor 32c, received by the secure communication circuit 32e.

The application processor 32c is a processor for performing processes of various applications, different from processes handled by the MCU 32a. The application processor 32c starts up, for example, based on boot code stored in the RAM 32b.

The power supply control circuit 32d provides, via the system bus 32f, power supply and control over turning on and off individual elements of the slave <NUM>, to thereby decide whether to start up each of the elements.

The secure communication circuit 32e receives encrypted data via the network <NUM> and decrypts encrypted boot code and route information. In addition, the secure communication circuit 32e encrypts again the decrypted boot code and route information and then transmits, via the network <NUM>, encrypted data including the encrypted boot code and route information to a destination designated in the route information. Further, the secure communication circuit 32e transmits an acknowledgement signal indicating the receipt of the encrypted data to the master <NUM> via the network <NUM>. Upon receiving a boot instruction signal transmitted by the master <NUM>, the secure communication circuit 32e notifies, via the system bus 32f, the power supply control circuit 32d of the receipt of the boot instruction signal.

The secure communication circuit 32e may be built with a similar hardware configuration as the secure communication circuit 31f in <FIG>.

Note that the slaves <NUM> to <NUM> may be provided with elements equivalent to the ROM 31b and the encryption/decryption processing circuit 31e of the master <NUM>, to thereby cause them serve as masters while allowing the master <NUM> to serve as a slave.

Next described is an example of route information stored in the non-volatile memory device <NUM>.

<FIG> illustrates an exemplary file format of route information.

In the route information file format, the top item (Item No. <NUM>) is associated with data representing the total number of slaves. The second and subsequent items (Item Nos. <NUM> to <NUM>) are associated with data representing slave information of the slaves <NUM> to <NUM>, respectively. The information of each of the slaves <NUM> to <NUM> includes, for example, data of five items: slave MAC address; source MAC address; reception data storage beginning address; data size; and transmission data storage beginning address.

The slave MAC address is the MAC address of the corresponding one of the slaves <NUM> to <NUM>. For example, the slave MAC address included in the slave information of the slave <NUM> is the MAC address of the slave <NUM>.

The source MAC address is the MAC address of a route information delivery source (the master <NUM> or one of the slaves <NUM> to <NUM>). For example, the source MAC address included in the slave information of the slave <NUM> is the MAC address of the master <NUM>.

The reception data storage beginning address is the beginning address of a memory area for storing data received by the corresponding one of the slaves <NUM> to <NUM>. For example, the reception data storage beginning address included in the slave information of the slave <NUM> is the beginning address of a memory area in the RAM 32b, where received boot code is stored.

The data size indicates the data size of the boot code stored in the RAM 32b.

The transmission data storage beginning address is associated with a delivery source of the boot code (the master <NUM> or one of the slaves <NUM> to <NUM>), and indicates the beginning address of a memory area where the boot code is stored within the delivery source. For example, the transmission data storage beginning address included in the slave information of the slave <NUM> indicates the beginning address of a memory area, within the non-volatile memory device <NUM>, where the boot code is stored.

<FIG> illustrates an example of data included in slave information.

The example of <FIG> depicts data included in the slave information of the slave <NUM>. MACS0, which is a slave MAC address, is set in the secure communication circuit 32e of the slave <NUM>, and MACM, which is a source MAC address, is set in the secure communication circuit 31f of the master <NUM>, for example.

A reception data storage beginning address add2 indicates the beginning address of a memory area, within the RAM 32b, where data (boot code) is stored. A transmission data storage beginning address add1 indicates the beginning address of a memory area, within the non-volatile memory device <NUM>, where data (encrypted boot code) is stored. A data size size1 indicates the size of the data stored in the non-volatile memory device <NUM>.

Next described is an example of an operation carried out by the processor <NUM> of <FIG>.

<FIG> is a sequence diagram illustrating an exemplary operation flow performed by a processor of <FIG>. The operation flow depicted in <FIG> takes place to start up the MCU 32a of the slave <NUM> based on boot code delivered from the master <NUM>.

When the processor <NUM> is powered on, the power supply control circuit 31d of the master <NUM> starts up (T1), and the power supply control circuit 32d of the slave <NUM> starts up (T2). The power supply control circuit 32d of the slave <NUM> initializes the secure communication circuit 32e (for example, sets up registers) (T3) and then starts up the secure communication circuit 32e. A similar operation takes place in the remaining slaves <NUM> to <NUM> although <FIG> omits the representation.

The power supply control circuit 31d of the master <NUM> starts up the MCU 31a (T4), and the MCU 31a initializes the encryption/decryption processing circuit 31e and the secure communication circuit 31f (T5, T6) and then starts up them. Alternatively, the power supply control circuit 31d may initialize the encryption/decryption processing circuit 31e and the secure communication circuit 31f. The MCU 31a issues a delivery start instruction to the secure communication circuit 31f (T7).

The encryption/decryption processing circuit 31e reads encrypted route information, for example, from an address in the non-volatile memory device <NUM>, designated in the initialization implemented by the MCU 31a, and decrypts the encrypted route information (T8).

The secure communication circuit 31f reads the decrypted route information from the encryption/decryption processing circuit 31e (T9), and transmits a packet to the slave <NUM> based on the route information, to thereby make a location confirmation inquiry (T10).

Upon receiving the location confirmation inquiry, the secure communication circuit 32e of the slave <NUM> transmits a response packet to the master <NUM>, to thereby provide a response to the location confirmation inquiry (T11).

The encryption/decryption processing circuit 31e of the master <NUM> reads encrypted boot code, for example from an address in the non-volatile memory device <NUM>, designated in the initialization implemented by the MCU 31a, and decrypts the encrypted boot code (T12).

The secure communication circuit 31f reads the decrypted boot code from the encryption/decryption processing circuit 31e (T13) and performs an encryption process to thereby encrypt the boot code and route information (T14), and then transmits the encrypted data to the slave <NUM> (T15).

The secure communication circuit 32e of the slave <NUM> receives the encrypted data and performs a decryption process to obtain the boot code and root information (T16). Then, the secure communication circuit 32e stores the route information in a storage unit (not illustrated), e.g. a register, provided in the secure communication circuit 32e, and also stores the boot code in the RAM 32b (T17). Then, the secure communication circuit 32e transmits an acknowledgement signal to the master <NUM> to thereby notify the master <NUM> of the completion of data receipt (T18).

Upon receiving notice of the receipt of the encrypted data from all the slaves <NUM> to <NUM> via the secure communication circuit 31f, the MCU 31a of the master <NUM> causes the secure communication circuit 31f to transmit a boot instruction signal for instructing start-up of the individual MCUs of all the slaves <NUM> to <NUM> (T19).

Upon receiving the boot instruction signal from the secure communication circuit 31f of the master <NUM>, the secure communication circuit 32e of the slave <NUM> notifies the power supply control circuit 32d accordingly (T20). Upon receiving, from the secure communication circuit 32e, a signal indicating the receipt of the boot instruction signal, the power supply control circuit 32d starts up the MCU 32a (T21). Although not illustrated in <FIG>, the MCU 32a subsequently performs a boot process based on the boot code stored in the RAM 32b.

Note that, although not illustrated in <FIG>, in the case of transmitting encrypted data from the slave <NUM> to a different slave, the secure communication circuit 32e of the slave <NUM> makes a location confirmation inquiry to the destination slave based on the route information. Subsequently, upon receiving a response to the location confirmation inquiry, the secure communication circuit 32e reads the boot code from the RAM 32b and encrypts the route information and the boot code, and then transmits the encrypted data to the destination slave.

Note that the processor <NUM> is able to deliver boot code of the application processors of the slaves <NUM> to <NUM> (e.g. the application processor 32c in the case of the slave <NUM>) in a similar manner as described above.

Note that the encrypted data including boot code and route information may be transmitted from a single master or slave to a plurality of slaves.

<FIG> illustrates an exemplary delivery route for encrypted data.

According to the delivery route for encrypted data illustrated in <FIG>, the slave <NUM> having received encrypted data transmitted by the master <NUM> transmits the encrypted data to the slaves <NUM>, <NUM>, and <NUM>. Then, the slave <NUM> transmits the encrypted data to the slaves <NUM> and <NUM>. The slave <NUM> transmits the encrypted data to a single slave, i.e., the slave <NUM>, and the slave <NUM> transmits the encrypted data to a single slave, i.e., the slave <NUM>. Note that the delivery of the encrypted data to a plurality of slaves takes place in a predetermined order based on route information, and not simultaneously.

Route information indicating such a delivery route is represented as follows.

<FIG> illustrates exemplary route information.

In the route information, the second and subsequent items (Item Nos. <NUM> to <NUM>) are associated with data representing information of the slaves <NUM> to <NUM>, respectively, which is arranged according to subtree units of the tree-structured delivery route.

For example, because the delivery route of <FIG> includes a subtree designating the delivery of encrypted data in the order of the slaves <NUM>, <NUM>, <NUM>, and <NUM>, the information of the slaves <NUM>, <NUM>, <NUM>, and <NUM> is arranged in the stated order. Further, the delivery route includes a subtree designating the delivery of encrypted data from the slave <NUM> to the slave <NUM>, a subtree designating the delivery of encrypted data from the slave <NUM> to the slave <NUM> and then the slave <NUM>, and a subtree designating the delivery of encrypted data from the slave <NUM> to the slave <NUM>. Therefore, the information of the slaves <NUM>, <NUM>, <NUM>, and <NUM> is arranged according to these subtree units.

<FIG> illustrates exemplary slave information.

In the example of <FIG>, the following MAC addresses are assigned to the individual devices: MACM to the master <NUM>; MACS0 to the slave <NUM>; MACS1 to the slave <NUM>; MACS2 to the slave <NUM>; MACS3 to the slave <NUM>; MACS4 to the slave <NUM>; MACS5 to the slave <NUM>; MACS6 to the slave <NUM>; and MACS7 to the slave <NUM>.

Also, <FIG> depicts an example where boot code with a data size of S1, stored, within the non-volatile memory device <NUM>, in a memory area with a beginning address of Add0 is stored, within the RAM of each of the slaves <NUM> to <NUM>, in a memory area with a beginning address of Add1.

To deliver encrypted data using such route information, the secure communication circuit 31f of the master <NUM> performs the following procedure.

The secure communication circuit 31f transmits, to a slave represented by the top slave information included in the route information, boot code and route information corresponding to a set of slave information, starting with the top slave information up to slave information immediately preceding next slave information with the MAC address of the master <NUM> set as the source MAC address. In the case where there is a plurality of pieces of slave information whose source MAC address is set to the MAC address of the master <NUM>, a similar operation is repeatedly performed. Specifically, in the second round, the secure communication circuit 31f transmits, for example, boot code and route information corresponding to a set of slave information, starting with the second slave information whose source MAC address is set to the MAC address of the master <NUM> up to slave information immediately preceding the third slave information whose source MAC address is set to the MAC address of the master <NUM>.

In the example of <FIG>, the slave information of the slave <NUM> is the only slave information whose source MAC address is set to MACM, which is the MAC address of the master <NUM>. Therefore, route information including the slave information of all the slaves <NUM> to <NUM> is transmitted to the slave <NUM>.

The secure communication circuit of each of the slaves <NUM> to <NUM> (e.g. the secure communication circuit 32e in the case of the slave <NUM>) disregards the first slave information included in the received route information because it is associated with its own slave, and instead regards the second slave information as the top slave information. Then, the secure communication circuit of each of the slaves <NUM> to <NUM> transmits, to a slave represented by the top slave information, boot code and route information corresponding to a set of slave information, starting with the top slave information up to slave information immediately preceding one with its own MAC address set as the source MAC address. In the case where there is a plurality of pieces of slave information whose source MAC address is set to its own MAC address, a similar operation is repeatedly performed.

Note that each of the slaves <NUM> to <NUM> ends the delivery process if the received route information includes only a single piece of slave information since there is no destination for the slave to transmit the route information. Also, if there is no slave information piece to be transmitted, each of the slaves <NUM> to <NUM> ends the delivery process.

In the example of <FIG>, the slave <NUM> transmits, to the slave <NUM>, boot code and route information corresponding to a set of slave information, starting with the slave information associated with the item No. <NUM> (i.e., the slave information of the slave <NUM>) up to slave information immediately preceding the nearest slave information down the list, whose source MAC address is set to its own MAC address, i.e., the slave information associated with the item No. <NUM>. The slave <NUM> also transmits, to the slave <NUM>, boot code and route information corresponding to a set of slave information, starting with the slave information associated with the item No. <NUM> (i.e., the slave information of the slave <NUM>) up to slave information immediately preceding the nearest slave information down the list, whose source MAC address is set to its own MAC address, i.e., the slave information associated with the item No. <NUM>. Further, the slave <NUM> transmits, to the slave <NUM>, the slave information associated with the item No. <NUM> (i.e., the slave information of the slave <NUM>) as route information, together with boot code.

As described above, if there is a plurality of destinations, the master <NUM> and the slaves <NUM> to <NUM> individually create route information to be transmitted to each of the destinations by leaving out information on delivery routes (pieces of slave information) associated with the remaining destinations. This reduces the amount of information transmitted, which in turn cuts the time needed to deliver boot code.

Note that the master <NUM> and the slaves <NUM> to <NUM> may individually delete the top slave information from route information and then transmit the resultant route information to each destination slave.

The master <NUM> of the processor <NUM> of <FIG> described above may collect, from the slaves <NUM> to <NUM>, status information indicating the status of each slave.

<FIG> illustrates an exemplary process of collecting status information.

Status information of each of the slaves <NUM> to <NUM> in operation is transmitted from the secure communication circuit of the slave to the master <NUM> via the network <NUM>. The transmission of the status information to the master <NUM> takes place periodically.

<FIG> illustrates status information being transmitted from a slave to a master.

A slave <NUM> is configured by adding, to the slave <NUM> of <FIG>, a status register <NUM> for holding status information therein. For example, a flag bit indicating the operation status of the application processor 32c is written in the status register <NUM> as status information. The slave <NUM> may have a function of detecting an abnormality. In such a case, information indicating the presence or absence of an abnormality is written in the status register <NUM> as status information.

The secure communication circuit 32e has, for example, a timer, and periodically reads the status information stored in the status register <NUM>. Then, the secure communication circuit 32e encrypts the read status information and transmits it to the master <NUM> via the network <NUM>. Note that the secure communication circuit 32e may periodically read the status information stored in the status register <NUM>, for example, under the control of the MCU 32a or the power supply control circuit 32d.

Upon receiving the encrypted status information, the secure communication circuit 31f of the master <NUM> performs a decryption process and stores decrypted status information in the RAM 31c. The MCU 31a of the master <NUM> refers to the status information stored in the RAM 31c to thereby determine whether an abnormality is present in the slave <NUM>.

According to the processor <NUM> of <FIG> described above, the master <NUM>, serving as a starting point, delivers boot code of the slaves <NUM> to <NUM> to the slaves <NUM> to <NUM>. This eliminates the need to provide each of the slaves <NUM> to <NUM> with a non-volatile memory device connected thereto for storing the boot code. In addition, the secure communication circuit of each of the slaves <NUM> to <NUM> (e.g. the secure communication circuit 32e in the case of the slave <NUM>) decrypts encrypted boot code. This eliminates the need to provide each of the slaves <NUM> to <NUM> with a controller on a different chip connected thereto to handle the decryption process and the like. As a result, even if the number of slaves increases, it is possible to prevent a rise in the number of chips and non-volatile memory devices for storing boot code. This enhances the reliability of the processor <NUM> with a simple configuration, which in turn is likely to reduce the cost.

In addition, the slaves <NUM> to <NUM> individually encrypt again decrypted boot code and route information and then transmit the encrypted data to each destination based on the route information. This results in reduced workload of the master <NUM>.

Claim 1:
A first semiconductor integrated circuit (<NUM>) of a processing apparatus, the first semiconductor integrated circuit (<NUM>) comprising:
a communication circuit (11d), a control circuit (11a), connected with a system bus (11f);
the communication circuit (11d) configured to:
generate a second boot code (20b) by encrypting a first boot code (20a), wherein the first boot code (20a) comprises:
a third boot code to be used by a second semiconductor integrated circuit (<NUM>) of the processing apparatus to perform a boot process, and
a fourth boot code to be used by a third semiconductor integrated circuit (<NUM>) of the processing apparatus to perform a boot process, the fourth boot code to be encrypted by the second semiconductor integrated circuit (<NUM>) and transmitted to the third semiconductor integrated circuit (<NUM>) from the second semiconductor integrated circuit (<NUM>),
transmit, based on first route information (21a) indicating a delivery route of the second boot code (20b), first data (22a) including the second boot code (20b) and the first route information (21b) to the second semiconductor integrated circuit (<NUM>) via a first network (<NUM>), and
receive, from the second semiconductor integrated circuit (<NUM>), an acknowledgement signal indicating that receipt of the first data (22a) is completed;
receive, from the third semiconductor integrated circuit (<NUM>), an acknowledgement signal indicating that receipt of the first data (22b) is completed; and
the control circuit (11a) configured to be connected to the communication circuit (11d) via the system bus (11f), and cause, when the communication circuit (11d) receives the acknowledgement signal, the communication circuit (11d) to transmit, to the second semiconductor integrated circuit (<NUM>) and the third semiconductor integrated circuit (<NUM>) via the first network (<NUM>), a boot instruction signal instructing the second semiconductor integrated circuit (<NUM>) and the third semiconductor integrated circuit (<NUM>) to perform a boot process based on the first boot code (20a).