Patent Description:
Configurable input blocks and output blocks and associated physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses required.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, published as <CIT>. The non-volatile memory arrays operate as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cells used in the analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

One challenge in vector by matrix multiplication (VMM) systems is the ability to quickly and accurately deliver an output from a VMM as an input to another VMM, and to do so while efficiently utilizing the physical space within a semiconductor die.

What is needed are configurable input blocks and output blocks and physical layouts for analog neural memory systems that utilize non-volatile memory cells. What is further needed are systems and methods for compensating for leakage and offset in the input blocks and output blocks for such systems.

<CIT> refers to a memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.

<NPL>" refers to a memristive neural network computing engine based on CMOS-compatible charge-trap transistor (CTT). The proposed memristive computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces.

<CIT>discloses an A/D converter which offset compensation by memorising previously the amplifier output into the A/D converter when the amplifier input is zero and then subtracting the memorised value from the A/D conversion value of the input signal.

<CIT> discloses numerical value conversion of a digital input value having temperature compensation using temperature-dependent coefficients stored in a look-up table.

<CIT> discloses an analog neural non-volatile memory cell array comprising analog-to-digital conversion output circuitry.

<CIT> discloses a method for soft data generation for memory devices based on a performance factor adjustment.

The present invention is defined in appended claim <NUM>. Any embodiment in the description that does not fall within the scope of the claims shall be regarded as an example for understanding the present invention.

Claim <NUM> reads: a calibration method of operating an output circuit block for analog neural network non-volatile memory array cells, comprises performing leakage or offset calibration, measuring leakage of the analog neural network non-volatile memory array cells using analog-to-digital conversion or measuring offset from the analog neural network non-volatile memory array cells using analog-to-digital conversion, and storing the measured digital outputs in a register; and converting a neuron output by counting up digital output bits from the neuron and then subtracting the stored measured digital outputs.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the source region <NUM> towards the drain region <NUM>. The electrons will accelerate and become heated when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) <NUM>. Control gate <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line <NUM> to a positive voltage and biasing control gate <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). The erase, programming, and read operations operate in a similar manner to that described previously for memory cell <NUM>.

The methods and means described herein may apply to other non-volatile memory technologies such as SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and volatile synapse cell, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of an array that can be used for that purpose. Vector-by-matrix multiplication (VMM) system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> includes VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing opamp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of positive weight and negative weight.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory system. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers. Furthermore, the different layers can use different combinations of n-bit memory cells (different cells supporting multiple different levels) including <NUM>-level memory cells (meaning only <NUM> levels, '<NUM>' and `<NUM>').

Here, the inputs to VMM array <NUM> are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array <NUM> emerges on the source lines (SL0, SL1). The current placed on each source line (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT> where w = e (- Vth)/nVt
where Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T temperature in Kelvin, and q electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) where Cdep = capacitance of depletion layer, and Cox is capacitance of the gate oxide layer; and Io is the memory cell current at gate voltage equal to threshold voltage. Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are the width and length of memory cell, respectively.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current into an input voltage: <MAT> Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely<MAT> <MAT> Here, wa = w of each memory cell in the memory array.

Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> where Wt and L are the width and length respectively of the transistor <MAT> meaning weight W is proportional to (Vgs-Vth).

Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> W = α (Vgs-Vth)<NUM>, meaning weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the flash memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation).

Other embodiments for VMM array <NUM> of <FIG> are described in <CIT>. As described in that application, a sourceline or a bitline can be used as the neuron output (current summation output).

Here, the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation.

Second, memory array <NUM> effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 - BLN, and will be the input to the next layer or input to the final layer. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output emerges on the bitlines (BL0 - BLN) during a read operation.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as FG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

In VMM array <NUM>, the inputs INPUT<NUM>. , INPUTN are received on bit lines BL<NUM>,. BLN, respectively, and the outputs OUTPUT<NUM>, OUTPUT<NUM>, OUTPUT<NUM>, and OUTPUT<NUM> are generated on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively.

In this example, the inputs INPUT<NUM>, INPUT<NUM>, INPUT<NUM>, and INPUTs are received on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTn are received on vertical control gate lines CG<NUM>,. , CGN, respectively, and the outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SLi.

In this example, the inputs INPUT<NUM>,. , INPUTN are received on the gates of bit line control gates <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(N-<NUM>), and <NUM>-N, respectively, which are coupled to bit lines BL<NUM>,. , BLN, respectively. Exemplary outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SLi.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, and the outputs OUTPUT<NUM>,. , OUTPUTN are generated on bit lines BL<NUM>,. , BLN, respectively.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical source lines SL<NUM>,. , SLN, respectively, where each source line SLi is coupled to the source line terminals of all memory cells in column i.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical bit lines BL<NUM>,. , BLN, respectively, where each bit line BLi is coupled to the bit line terminals of all memory cells in column i.

The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.

<FIG> depicts an exemplary LSTM <NUM>. LSTM <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an LSTM with four cells is merely an example.

<FIG> depicts an exemplary implementation of an LSTM cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>. LSTM cell <NUM> receives input vector x(t), cell state vector c(t-<NUM>) from a preceding cell, and output vector h(t-<NUM>) from a preceding cell, and generates cell state vector c(t) and output vector h(t).

LSTM cell <NUM> comprises sigmoid function devices <NUM>, <NUM>, and <NUM>, each of which applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. LSTM cell <NUM> also comprises tanh devices <NUM> and <NUM> to apply a hyperbolic tangent function to an input vector, multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, and addition device <NUM> to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

<FIG> depicts an LSTM cell <NUM>, which is an example of an implementation of LSTM cell <NUM>. For the reader's convenience, the same numbering from LSTM cell <NUM> is used in LSTM cell <NUM>. Sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation circuit blocks <NUM>. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems. The multiplier devices <NUM>, <NUM>, and <NUM> and the addition device <NUM> are implemented in a digital manner or in an analog manner. The activation function blocks <NUM> can be implemented in a digital manner or in an analog manner.

An alternative to LSTM cell <NUM> (and another example of an implementation of LSTM cell <NUM>) is shown in <FIG>. In <FIG>, sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. LSTM cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, tanh device <NUM> (which comprises activation circuit block <NUM>), register <NUM> to store the value i(t) when i(t) is output from sigmoid function block <NUM>, register <NUM> to store the value f(t) * c(t-<NUM>) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to store the value i(t) * u(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to store the value o(t) * c~(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and multiplexor <NUM>.

Whereas LSTM cell <NUM> contains multiple sets of VMM arrays <NUM> and respective activation function blocks <NUM>, LSTM cell <NUM> contains only one set of VMM arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of LSTM cell <NUM>. LSTM cell <NUM> will require less space than LSTM <NUM>, as LSTM cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to LSTM cell <NUM>.

It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient.

An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.

<FIG> depicts an exemplary GRU <NUM>. GRU <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an GRU with four cells is merely an example.

<FIG> depicts an exemplary implementation of a GRU cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> of <FIG>. GRU cell <NUM> receives input vector x(t) and output vector h(t-<NUM>) from a preceding GRU cell and generates output vector h(t). GRU cell <NUM> comprises sigmoid function devices <NUM> and <NUM>, each of which applies a number between <NUM> and <NUM> to components from output vector h(t-<NUM>) and input vector x(t). GRU cell <NUM> also comprises a tanh device <NUM> to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, an addition device <NUM> to add two vectors together, and a complementary device <NUM> to subtract an input from <NUM> to generate an output.

<FIG> depicts a GRU cell <NUM>, which is an example of an implementation of GRU cell <NUM>. For the reader's convenience, the same numbering from GRU cell <NUM> is used in GRU cell <NUM>. As can be seen in <FIG>, sigmoid function devices <NUM> and <NUM>, and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation function blocks <NUM>. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems. The multiplier devices <NUM>, <NUM>, <NUM>, the addition device <NUM>, and the complementary device <NUM> are implemented in a digital manner or in an analog manner. The activation function blocks <NUM> can be implemented in a digital manner or in an analog manner.

An alternative to GRU cell <NUM> (and another example of an implementation of GRU cell <NUM>) is shown in <FIG>. In <FIG>, GRU cell <NUM> utilizes VMM arrays <NUM> and activation function block <NUM>, which when configured as a sigmoid function applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. In <FIG>, sigmoid function devices <NUM> and <NUM> and tanh device <NUM> share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. GRU cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, complementary device <NUM> to subtract an input from <NUM> to generate an output, multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) * r(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) *z(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to hold the value h^(t) * (<NUM>-z(t)) when that value is output from multiplier device <NUM> through multiplexor <NUM>.

Whereas GRU cell <NUM> contains multiple sets of VMM arrays <NUM> and activation function blocks <NUM>, GRU cell <NUM> contains only one set of VMM arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of GRU cell <NUM>. GRU cell <NUM> will require less space than GRU cell <NUM>, as GRU cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to GRU cell <NUM>.

It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient.

The input to the VMM arrays can be an analog level, a binary level, or digital bits (in this case a DAC is needed to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, or digital bits (in this case an output ADC is needed to convert output analog level into digital bits).

For each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W = W+ - W-). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM> (which can be based on any of the VMM array designs discussed previously, such as VMM array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM><NUM>, and <NUM> or other VMM array designs), low voltage row decoder <NUM>, high voltage row decoder <NUM>, column decoder <NUM>, column driver <NUM>, control logic <NUM>, bias circuit <NUM>, neuron output circuit block <NUM>, input VMM circuit block <NUM>, algorithm controller <NUM>, high voltage generator block <NUM>, analog circuit block <NUM>, and control logic <NUM>.

Input circuit block <NUM> serves as interface from an external input to the input terminals of the memory array <NUM>. Input circuit block <NUM> can comprise a DAC (Digital-to-Analog Converter), DPC (Digital-to-Pulse Converter), APC (Analog-to-Pulse Converter), IVC (Current-to-Voltage Converter), AAC (Analog-to-Analog Converter, such as a voltage-to-voltage scaler), or FAC (Frequency-to-Analog Converter), without limitation. Neuron output block <NUM> serves as an interface from the memory array output to an external interface (not shown). Neuron output block <NUM> can comprise an ADC (Analog-to-Digital Converter), APC (Analog-to-Pulse Converter), DPC (Digital-to-Pulse Converter), IVC (Current-to-Voltage Converter), or IFC (Current-to-Frequency Converter), without limitation. Neuron output block <NUM> may include activation functions, normalization circuitry, and/or re-scaling circuitry, without limitation.

<FIG> depicts VMM system <NUM>, which comprises VMM arrays <NUM>, <NUM>, <NUM>, and <NUM>; high voltage row decoders <NUM> and <NUM>; low voltage row decoders <NUM> and <NUM>; input blocks <NUM> and <NUM> (each similar to input block <NUM> in <FIG>); and output blocks <NUM> and <NUM>. In this configuration, VMM arrays <NUM> and <NUM> share a set of bit lines as well as output block <NUM>, and VMM arrays <NUM> and <NUM> share a set of bit lines as well as output block <NUM>. VMM arrays <NUM> and <NUM> can be read at the same time, which effectively would combine them into a single, larger array, or they can be read at different times. Output blocks <NUM> and <NUM> (similar to output block <NUM> in <FIG>) are configurable to be able to handle read operations from one array at a time (such as reading from array <NUM> or <NUM> only) or from multiple arrays (such as reading from both arrays <NUM> and <NUM>) at a time.

<FIG> depicts VMM system <NUM>, which comprises VMM arrays <NUM>, <NUM>, and <NUM>; shared global high voltage row decoder <NUM>; local high voltage row decoders <NUM> and <NUM>; shared low voltage row decoder <NUM>; and input block <NUM>. In this configuration, VMM arrays <NUM>, <NUM>, and <NUM> share input block <NUM>. VMM arrays <NUM>, <NUM>, and <NUM> can receive inputs (e.g., voltages or pulses on word lines, control gate lines, erase gate lines, or source lines) through input block <NUM> at the same time, which effectively combines them into a single, larger VMM array, or they can receive inputs through input block <NUM> at different times, which effectively operates them as three distinct VMM arrays with same input block. Input block <NUM> is configurable to be able to provide inputs to one array at a time or to multiple arrays at a time.

<FIG> depicts VMM system <NUM>, which comprises VMM arrays <NUM>, <NUM>, <NUM>, and <NUM>; global high voltage decoder <NUM>; local high voltage row decoders <NUM>, <NUM>, and <NUM>; shared low voltage row decoder <NUM>; and input block <NUM>. In this configuration, VMM arrays <NUM>, <NUM>, <NUM>, and <NUM> share input block <NUM>. VMM arrays <NUM>, <NUM>, <NUM>, and <NUM> can receive inputs (e.g., voltages or pulses on word lines, control gate lines, erase gate lines, or source lines) through input block <NUM> at the same time, which effectively combines them into a single, larger array, or they can receive inputs through input block <NUM> at different times, which effectively operates them as three distinct VMM arrays with same input block <NUM>. Input block <NUM> is configurable to be able to provide inputs to one array at a time or to multiple arrays at a time. For example, input block <NUM> of <FIG> is configured to provide inputs to <NUM> arrays and input block <NUM> is configured to provide inputs for <NUM> arrays.

<FIG> depicts VMM system <NUM>, which comprises horizontal set <NUM> and horizontal set <NUM>. Horizontal set <NUM> comprises VMM arrays <NUM> and <NUM>; shared global high voltage row decoder <NUM>; local high voltage row decoder <NUM>; shared low voltage row decoder <NUM>; and input block <NUM>. VMM arrays <NUM> and <NUM> share input block <NUM>. Input block <NUM> is configurable to be able to provide inputs to one array at a time or multiple arrays at a time.

Horizontal set <NUM> comprises VMM arrays <NUM> and <NUM>; shared global high voltage decoder <NUM>; local high voltage row decoders <NUM>; shared low voltage row decoder <NUM>; and input block <NUM>. VMM arrays <NUM> and <NUM> share input block <NUM>. Input block <NUM> is configurable to be able to provide inputs to one array at a time or to multiple arrays at a time.

In a first configuration, horizontal set <NUM> utilizes output blocks <NUM> and <NUM>, and horizontal set <NUM> utilizes output blocks <NUM> and <NUM>. Output blocks <NUM>, <NUM>, <NUM>, and <NUM> can output currents, digital pulses, or digitals bits as the output. In one embodiment where digital bits are output, output blocks <NUM>, <NUM>, <NUM>, and <NUM> each output <NUM> digital output bits.

In a second configuration, output blocks <NUM> and <NUM> are disabled, and VMM arrays <NUM> and <NUM> share output block <NUM> and VMM arrays <NUM> and <NUM> share output block <NUM>. VMM arrays <NUM> and <NUM> can be read at the same time, which effectively combines them into a single, larger vertical array (meaning more rows per bitline), or they can be read at different times. If VMM arrays <NUM> and <NUM> are read at the same time, then in one embodiment where each output block would output an <NUM> bit range of values when coupled to only one array, then output blocks <NUM> and <NUM> each will output a <NUM> bit range of values. This is due to the dynamic range of the output neuron which has been doubled by the use of <NUM> arrays as a single large array. In this case the output may need to re-scaled or normalized (e.g., scaled down from <NUM> bits to <NUM> bits) if the next array only needs <NUM> bits of dynamic range. In another embodiment, the number of output bits can be kept the same when increasing the number of vertical arrays.

Similarly, VMM arrays <NUM> and <NUM> can be read at the same time, which effectively combines them into a single, larger array, or they can be read at different times. Output blocks <NUM> and <NUM> are configurable to be able to handle read operations from one array at a time or from multiple arrays at a time.

In VMM systems <NUM>, <NUM>, <NUM>, and <NUM>, when the system is configurable to utilize different numbers of arrays with each input block and/or output block, then the input block or output block itself must also be configurable. For example, in VMM system <NUM>, if output blocks <NUM>, <NUM>, <NUM>, and <NUM> each output an <NUM>-bit output when coupled to a single array, then output blocks <NUM> and <NUM> each will need to be configured to output a <NUM>-bit output when it is coupled to two arrays (e.g., arrays <NUM> and <NUM>, and arrays <NUM> and <NUM>, respectively). If those outputs are then to be provided to the input block of another VMM system, the output will need to first be normalized if the input block is expecting an <NUM>-bit input instead of a <NUM>-bit input. Numerous analog and digital techniques are known for converting an N-bit value into an M-bit value. In the preceding example, N would be <NUM> and M would be <NUM>, although one of ordinary skill in the art will appreciate that N and M can be any positive integers.

Additional arrays can be coupled to input blocks and output blocks in VMM systems <NUM>, <NUM>, <NUM>, and <NUM>. For example, in VMM system <NUM>, more than two arrays can be coupled to input block <NUM> and more than two arrays can be coupled to input block <NUM>; in VMM system <NUM>, more than three arrays can be coupled to input block <NUM>; in VMM system <NUM> more than four arrays can be coupled to input block <NUM>; and in VMM system <NUM>, more than two arrays can be coupled to input block <NUM>, more than two arrays can be coupled to input block <NUM>, more than two arrays can be coupled to output block <NUM>, and more than two arrays can be coupled to output block <NUM>. In those situations, the relevant input block and output block need to be further configured to accommodate the additional arrays.

Output blocks <NUM> and <NUM> in VMM system <NUM> and output blocks <NUM> and <NUM> need to be configurable for the a verify operation following a programming operation, a verify operation will be affected by the number of arrays connected to the output block. Furthermore, for program/erase verification (used for tuning, meaning to produce a specific electrical charge on the floating gate of the memory to produce a desired cell current), accuracy of the output block circuit (e.g.,<NUM> bits) needs to be greater than the accuracy required for inference reading (e.g. <NUM> bits). For example, verification accuracy > inference accuracy by >=<NUM> bits, e.g. by <NUM>-<NUM> bits. This is required to ensure sufficient margin between one level to the next, such as for verification result distribution, data retention drift, temperature or variation, without limitation.

In addition, input blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and output blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, <FIG>, <FIG>, and <FIG> need to be configurable for calibration processes, as calibration will be impacted by the number of arrays connected to the output block. Examples of calibration processes include processes to compensate for offset, leakage, fabrication process, and changes due to temperature changes.

In the next section, various adjustable components are disclosed for use in input blocks and output blocks to enable the input blocks and output blocks to be configured based on the number of arrays coupled to the input block or output block.

<FIG> depicts integrating dual-mixed slope analog-to-digital converter (ADC) <NUM>, which can be used in an output block such as output blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG> and <FIG>, where output neuron, INEU <NUM>, is an output current from the VMM array received by the output block. Integrating dual-mixed slope analog-to-digital converter (ADC) <NUM> converts INEU <NUM> into a series of digital/analog pulses or digital output bits. <FIG> depicts the operation waveform for the integrating ADC <NUM> in <FIG>. Output waveforms <NUM>, <NUM>, and <NUM> are for one current level. Output waveforms <NUM>, <NUM>, and <NUM> are for another, higher current level. Waveforms <NUM> and <NUM> have pulse widths proportional to the value of the output current. Waveforms <NUM> and <NUM> have their number of pulses proportional to the value of the output current. Waveforms <NUM> and <NUM> have digital output bits proportional to the value of the output current.

In one embodiment, ADC <NUM> converts INEU <NUM>, (which is an analog output current received by an output block from a VMM array) into a digital pulse whose width varies in proportion to the magnitude of the analog output current in the neuron output block, as shown in the examples depicted in <FIG>. ADC <NUM> comprises an integrator constituted of integrating op-amp <NUM> and adjustable integrating capacitor <NUM> integrates INEU <NUM> versus an adjustable reference current IREF <NUM>. Optionally, IREF <NUM> can comprise a bandgap filter with a temperature coefficient of <NUM> or with a temperature coefficient that tracks the neuron current, INEU <NUM>. The latter optionally can be obtained from a reference array containing values determined during a testing phase. During an initialization phase, switch <NUM> is closed. Vout <NUM> and the input to the negative terminal of operational amplifier <NUM> then will become equal to VREF value. Thereafter, switch <NUM> is opened and during a fixed time period tref, switch S1 is closed and the neuron current INEU <NUM> is up-integrated. During the fixed time period tref, Vout rises, and its slope changes as neuron current changes. Thereafter, during a period tmeas, a constant reference current IREF is down integrated for a time period tmeas (during which period Vout falls) by opening switch S1 and closing switch S2, where tmeas is the time required to down integrate Vout to VREF.

Output EC <NUM> will be high when VOUT > VREFV and will be low otherwise. EC <NUM> therefore generates a pulse whose width reflects the period tmeas, which in turn is proportional to the current INEU <NUM> (pulses <NUM> and <NUM> in <FIG>).

Optionally, the output pulse EC <NUM> can be converted into a series of pulses of uniform period for transmission to the next stage of circuitry, such as the input block of another VMM array. At the beginning of period tmeas, output EC <NUM> is input into AND gate <NUM> with reference clock <NUM>. The output will be pulse series <NUM> (where the frequency of the pulses in pulse series <NUM> is the same as the frequency of clock <NUM>) during the period when VOUT > VREF. The number of pulses is proportional to the period tmeas, which is proportional to the current INEU <NUM> (waveforms <NUM> and <NUM> in <FIG>).

Optionally, pulse series <NUM> can be input to counter <NUM>, which will count the number of pulses in pulse series <NUM> and will generate count value <NUM>, which is a digital count of the number of pulses in pulse series <NUM>, which is directly proportional to neuron current INEU <NUM>. Count value <NUM> comprises a set of digital bits (waveforms <NUM> and <NUM> in <FIG>).

In another embodiment, integrating dual-slope ADC <NUM> can convert neuron current INEU <NUM> into a pulse where the width of the pulse is inversely proportionally to the magnitude of neuron current INEU <NUM>. This inversion can be done in a digital or analog manner, and converted into a series of pulses, or digital bits for output to follow on circuitry.

Adjustable integrating capacitor <NUM> and adjustable reference current IREF <NUM> are adjusted in response to the number of arrays, N, connected to integrating dual-mixed slope analog-to-digital converter (ADC) <NUM>. For example, when N arrays are connected to integrating dual-mixed slope analog-to-digital converter (ADC) <NUM>, adjustable integrating capacitor <NUM> is adjusted by <NUM>/N, or adjustable reference current IREF <NUM> is adjusted by N.

Optionally, a calibration step can be performed while the VMM array and ADC <NUM> are at, or above, operating temperature to offset any leakage current that is present within the VMM array or a control circuit, and that offset value thereafter can be subtracted from Ineu in <FIG>. The calibration step can also be performed to compensate for the process or voltage supply variation in addition to temperature variation.

A method of operation of the output circuit blocks comprises first performing calibration for offset and voltage supply variation compensation. Next, output conversion is performed (such as converting the neuron current into pulse or digital bits), and then data normalization is performed to align the output range to the input range of the next VMM array. The data normalization may include data compression or output data quantization (such as to reduce the number of bits says from <NUM> bits to <NUM> bits). The activation may be performed after the output conversion or after the data normalization, compression or quantization. Examples of calibration algorithms are discussed below with reference to <FIG>, <FIG>, <FIG>, and <FIG>, discussed below.

<FIG> depicts current-to-voltage converter <NUM>, which optionally can be used to convert a neuron output current into a voltage, that for example, can be applied as an input (for example, on a WL or a CG line) of the VMM memory array. Thus, current-to-voltage converter <NUM> can be used in input blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, <FIG>, <FIG>, and <FIG> when those blocks are receiving analog currents (as opposed to pulses or digital data) as inputs.

Current-to-voltage converter <NUM> comprises op amp <NUM>, adjustable capacitor <NUM>, switch <NUM>, switch <NUM>, and current source <NUM> that here represents the neuron current INEU received by the input block. During current to voltage operation, switch <NUM> will be open, and switch <NUM> will be closed. The output, Vout, will increase in amplitude in proportion to the magnitude of the neuron current INEU <NUM>.

<FIG> depicts digital data-to-voltage converter <NUM>, which optionally can be used to convert digital data, received as signal DIN, into a voltage that, for example, can be applied as an input (for example, on a WL or a CG line) of the VMM memory array. When switch <NUM> is closed, the data input of signal DIN will enable the IREF_u reference current <NUM> into the capacitor <NUM>, creating a voltage on its terminal. Thus, digital data-to-voltage converter <NUM> can be used in input blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, <FIG>, <FIG>, and <FIG> when those blocks are receiving digital data (as opposed to pulses or analog currents) as inputs. In addition, the digital data-to-voltage converter <NUM> can be configured so that the digital data received at the input as signal DIN feeds directly through to the output OUT by opening switches <NUM> and <NUM> and closing switch <NUM>. Switches <NUM>, <NUM> and <NUM> are thus configured to enable the output OUT to either to receive the voltage on the capacitor <NUM> or to receive the digital data received as signal DIN directly. In the embodiment shown, signal DIN is received as data pulses.

Digital data-to-voltage pulse converter <NUM> comprises adjustable reference current <NUM>, switch <NUM>, variable capacitor <NUM>, switch <NUM>, and switch <NUM>. Adjustable reference current <NUM> and variable capacitor <NUM> can be configured with different values to adjust for the difference in size of the array to which digital data-to-voltage pulse converter <NUM> is attached. During operation, the digital data controls switch <NUM>, such that switch <NUM> closes whenever the digital data is high. When switch closes, adjustable reference current <NUM> will charge variable capacitor <NUM>. Switch <NUM> is closed whenever it is desired to provide the output at node OUT, such as when an array is ready to be read. In the alternative, switch <NUM> can be opened and switch <NUM> can be closed and the data input can be passed through as the output.

<FIG> depicts configurable analog to digital converter <NUM>, which optionally can be used to convert analog neuron current into digital data. Configurable analog to digital converter <NUM> can be used in an output block such as output blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG> and <FIG>, where output neuron, INEU <NUM>, is an output current received by the output block.

Configurable analog to digital converter <NUM> comprises current source <NUM>, variable resistor <NUM>, and analog-to-digital converter <NUM>. The current INEU <NUM> drops across the variable resistor <NUM> Rneu to produce a voltage Vneu = Ineu*Rneu. The ADC <NUM> (such as integrating ADC, SAR ADC, flash ADC, or SigmaDelta ADC, without limitation) converts this voltage into digital bits.

<FIG> depicts configurable current-to-voltage converter <NUM>, which optionally can be used to convert analog neuron current into a voltage that can be applied as an input (for example, on a WL or a CG line) of the VMM memory array. Thus, configurable current-to-voltage converter <NUM> can be used in input blocks <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, <FIG>, <FIG>, and <FIG> when those blocks are receiving analog current (as opposed to pulses or digital data) as inputs. Configurable current-to-voltage converter <NUM> comprises adjustable resistor Rin <NUM> and receives input current Iin <NUM> (which is the received input current) and generates Vin <NUM>, = Iin*Rin.

<FIG> depict digital bits-to-pulse width converter <NUM> to be used within an input block, row decoder, or output block. The pulse width output from digital bits-to-pulse width converter <NUM> is proportional to the value of the digital bits.

Digital bits-to-pulse width converter comprises binary counter <NUM>. The state Q [N:<NUM>] of binary counter <NUM> can be loaded by serial or parallel data in a loading sequence. Row control logic <NUM> outputs a voltage pulse WLEN with a pulse-width that is proportional to the value of the digital data inputs provided from blocks such as integrating ADC in <FIG>.

<FIG> shows the waveform for the output pulse width where the width is proportional to the digital bit values. First, the data in the received digital bits is inverted, and the inverted digital bits are loaded either serially or in parallel into counter <NUM>. Then, the row pulse-width is generated by row control logic <NUM> as shown in waveform <NUM> by counting in a binary manner until it reaches the maximum counter value.

An example using <NUM>-bit values for DIN is shown in Table No. <NUM>:.

Optionally, a pulse series-to-pulse converter can be used to convert the output comprising a pulse series into a single pulse whose width varies in proportion to the number of pulses in the pulse series to be used as an input to a VMM array that will be applied to wordline or control gates within the VMM array. An example of a pulse series-to-pulse converter is a binary counter with control logic.

Another embodiment utilizes an up binary counter and digital comparison logic. Namely, the output pulse width is generated by counting using an up binary counter until the digital outputs of the binary counter is same as the digital input bits.

Another embodiment utilizes a down binary counter. First, the down binary counter is loaded serially or in parallel with the digital data input pattern. Next, the output pulse width is generated by counting down the down binary counter until the digital outputs of the binary counter reaches minimum value, namely a '<NUM>' logic state.

<FIG> depicts digital data-to-pulse row converter <NUM>, which comprises binary indexed pulse stages <NUM>-i, where i ranges from <NUM> to N (i.e. least significant bit LSB to most significant bit MSB). The row converter <NUM> is used to provide row input to the arrays. Each stage <NUM>-i comprises latch <NUM>-i, switch <NUM>-i, and row digital binary indexed pulse input <NUM>-i (RDIN_Ti). For example, the binary indexed pulse input <NUM>-<NUM> (RDIN_T0) has pulse width equal to one time unit, i.e. <NUM>*tpls1unit. The binary indexed pulse input <NUM>-<NUM> (RDIN_T1) has width equal to two time units, i.e. <NUM>*tpls1unit. The binary indexed pulse input <NUM>-<NUM> (RDIN_T2) has width equal to four time units, i.e. <NUM>*tpls1unit. The binary indexed pulse input <NUM>-<NUM> (RDIN_T3) has width equal to eight time units, i.e. <NUM>*tpls1unit. The digital data in pattern DINi (from a neuron output) for each row is stored in the latches <NUM>-i. If the output Qi of the latch <NUM>-i is a ` <NUM>' it will transfer, through the switch <NUM>-i, the binary indexed pulse input <NUM>-i (RDIN_Ti) to time summation converter node <NUM>. Each time summation converter node <NUM> is connected to a respective input of NAND gate <NUM>, and the output of NAND gate <NUM> generates the output of the row converter WLIN/CGIN <NUM> through level shifting inverter <NUM>. The time summation converter node <NUM> sums up the binary indexed pulse inputs <NUM>-i sequentially in time responsive to the common clocking signal CLK, because the binary index pulse input <NUM>-i (RDIN_Ti) is enabled in a sequential manner one digital bit at a time, for example from LSB to MSB, or from MSB to LSB, or any random bit pattern.

<FIG> depicts exemplary waveforms <NUM>. Shown here are example signals for row digital binary indexed pulse input <NUM>-i, specifically, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>, and example outputs from level shifting inverter <NUM>, labeled as WL0 and WL3, where WL0 and WL3 are generated from row converter <NUM> circuit. In this example, WL0 is generated by row digital input <NUM>-<NUM> and <NUM>-<NUM> of its row decoder being asserted (WL0: Q0 =' <NUM>', Q3 =' <NUM>'), and WL3 is generated by row digital input <NUM>-<NUM> and <NUM>-<NUM> of its row decoder being asserted (WL3: Q1 ='<NUM>', Q2 =' <NUM>'). If none of the row digital input <NUM>-x is asserted, there is no pulse on WL0 or WL3 (control logic for this is not shown in <FIG>). Inputs from other rows of digital-to-pulse row converter <NUM>, i.e. other inputs to NAND gate <NUM>, are assumed to be high during this period.

<FIG> depicts row digital pulse generator <NUM>, which generates row digital binary indexed pulse inputs <NUM>-i (RDIN_Ti), where the width of the pulse is proportional to the binary value of the digital bit as described in above in relating to <FIG>.

<FIG> depicts ramp analog-to-digital converter <NUM>, which comprises current source <NUM> (which represents a received neuron current, Ineu), switch <NUM>, variable configurable capacitor <NUM>, and comparator <NUM>, which receives the voltage developed across variable configurable capacitor <NUM>, denoted Vneu, as the non-inverting input and configurable reference voltage Vreframp as the inverting input and generates output Cout. Vreframp is ramped up in discrete levels with each comparison clock cycle. Comparator <NUM> compares Vneu against Vreframp, and as a result output Cout will be "<NUM>" when Vneu>Vreframp and will be "<NUM>" otherwise. Thus, output Cout will be a pulse, whose width varies in response to Ineu. A larger Ineu will cause Cout to be "<NUM>" for a longer period of time, resulting in a wider pulse for output Cout. A digital counter <NUM> converts each pulse of output Cout into digital output bits as shown in <FIG> for two different Ineu currents, denoted OT1A and OT2A, respectively. Alternatively ramp voltage Vreframp is a continuous ramp voltage <NUM> as shown in graph <NUM> of <FIG>. A multi-ramp embodiment is shown in <FIG> for reducing the conversion time by utilizing a coarse-fine ramp conversion algorithm. First coarse reference ramp reference voltage <NUM> is ramped in a fast manner to figure out the sub range for each Ineu. Next, fine reference ramp reference voltages <NUM>, i.e. Vreframp1 and Vreframp2, are used respectively for each sub-range for converting Ineu. currents within the respective sub-range. As shown there are two sub-ranges for fine reference ramp voltages. More than two coarse/fine steps or two sub-ranges are possible.

<FIG> depicts comparator <NUM> for optional use in place of comparators <NUM> and <NUM> in <FIG> and <FIG>. Comparator <NUM> can be a static comparator (which does not necessarily utilize a clock signal) or a dynamic comparator (which does utilize a comparison clock signal). If comparator <NUM> is a dynamic comparator, it can comprise a clocked cross coupled inverter comparator, a StrongARM comparator, or other known dynamic comparator. Comparator <NUM> operates as a coarse comparator when coarse enable <NUM> is asserted, and comparator <NUM> operates as a fine comparator when fine enable <NUM> is asserted. Select signal <NUM> optionally can be used to indicate coarse comparator mode or fine enable mode, or it optionally can be used to configure comparator <NUM> to operate as a static comparator or a dynamic comparator. For instances where comparator <NUM> acts as a dynamic comparator, comparator <NUM> receives clock signal <NUM>. When operating as a dynamic comparator, comparison clock signal <NUM> will be a first clock signal of a first frequency when comparator is a coarse comparator, and clock signal <NUM> will be a second clock signal of a second frequency, greater than the first frequency, when comparator is a fine comparator. Comparator <NUM>, when operated as a coarse comparator, will have lower accuracy and a slower speed but will use less power compared to the situation where comparator <NUM> operates as a fine comparator. Thus, a dynamic comparator used for coarse comparison can utilize a slow comparison clock while a dynamic comparator use for fine comparison can utilize a fast comparison clock during the conversion ramping period.

Comparator <NUM> compares array output <NUM> against reference voltage <NUM>, as was the case with comparators <NUM> and <NUM> in <FIG> and <FIG>, and generates output <NUM>. When comparator <NUM> is operating as coarse comparator, reference voltage <NUM> can be an offset voltage.

During the conversion period that generates the digital output bits such as shown in <FIG> and <FIG>, comparator <NUM> can act as a coarse comparator and as a fine comparator during a coarse comparison period and a fine comparison period, respectively. At the beginning of this digital out bit conversion, a fine or hybrid coarse-fine (coarse in parallel with fine) comparison period is executed for a fixed time period. Next, a coarse comparison period is executed, then finally fine comparison is executed to complete the conversion.

<FIG> depicts algorithmic analog-to-digital output converter <NUM>, which comprises switch <NUM>, switch <NUM>, sample-and-hold (S/H) circuit <NUM>, <NUM> bit analog-to-digital converter (ADC) <NUM>, <NUM> bit digital-to-analog converter (DAC) <NUM>, summer <NUM>, and gain of two residue operational amplifier (2x opamp) <NUM>. Algorithmic analog-to-digital output converter <NUM> generates conversion digital output <NUM> in response to analog input Vin and control signals applied to switches <NUM> and <NUM>. An input received at analog input Vin (e.g. Vneu in <FIG>) is sampled first by the S/H circuit <NUM> by the switch <NUM>, then conversion is performed in N clock cycles for N bits. For each conversion clock cycle, the <NUM>-bit ADC <NUM> compares the S/H voltage <NUM> against a reference voltage (e.g., VREF/<NUM>, with VREF is full scale voltage for N bits) and outputs a digital bit (e.g., a "<NUM>" if input <=VREF/<NUM> and a "<NUM>" if input > VREF/<NUM>). This digital bit, which is the Digital Output signal <NUM>, is in turn converted into an analog voltage by the <NUM>-bit DAC <NUM> (e.g. to either VREF/<NUM> or 0V) and feed to the summer <NUM> to be subtracted from the S/H voltage <NUM>. The 2x residue opamp <NUM> then amplifies the summer difference voltage output into a conversion residue voltage <NUM> which is fed to the S/H circuits <NUM> through the switch <NUM> for next clock cycle. Instead of this <NUM>-bit (i.e., <NUM> levels) algorithmic ADC, a <NUM>-bit (i.e., <NUM> levels) algorithmic ADC can be used to reduce the effect of offset such as from ADC <NUM> and residue opamp <NUM>. A <NUM>-bit or <NUM>-bit (i.e., <NUM> levels)DAC is required for the <NUM>-bit algorithmic ADC.

<FIG> shows successive approximation register (SAR) analog-to-digital converter <NUM> applied to an output neuron to convert a cell current representing an output neuron into digital output bits. SAR ADC <NUM> comprises SAR <NUM>, digital-to-analog converter <NUM>, and comparator <NUM>. The cell current can be dropped across a resistor to generate a voltage VCELL, which is applied to the inverting input of comparator <NUM>. Alternatively, the cell current can charge a sample-and-hold capacitor to generate the voltage VCELL (such as Vneu as shown in <FIG>). A binary search is then used by SAR <NUM> to compute each bit starting from MSB bit (most significant bit) to LSB bit (least significant bit). Based on the digital bits (DN to D0) from SAR <NUM>, DAC <NUM> is used to set an appropriate analog reference voltage to comparator <NUM>. The output of the comparator <NUM> in turns feeds back to SAR <NUM> to choose the next analog level for the analog reference voltage to comparator <NUM>. As shown in <FIG>, for the example of <NUM>-bit digital output bits, there are <NUM> evaluation periods: a first pulse to evaluate DOUT3 by setting an analog level for the analog reference voltage to comparator <NUM> at a mid-point of the range, then a second pulse to evaluate DOUT2 by setting an analog level for the analog reference voltage to comparator <NUM> half way from the mid-point of the range to the maximum point of the range or half way from the mid-point of the range to the minimum point of the range. This is followed by further steps, each step further refining the analog reference voltage level to comparator <NUM>. The successive outputs of SAR <NUM> are the output digital bits. An alternative SAR ADC circuit is a switched cap (SC) circuit with only one reference level and local SC ratios to successively generate the ratioed reference level for successive comparisons.

<FIG> shows sigma delta analog-to-digital converter <NUM> applied to an output neuron to convert a cell current <NUM> (ICELL or Ineu) into digital output bits <NUM>. An integrator comprising op-amp <NUM> and configurable capacitor <NUM> (Cint) integrates the summation of current from cell current <NUM> and a configurable reference current resulting from <NUM>-bit current DAC <NUM>, which converts digital outputs <NUM> into a current. Comparator <NUM> compares the integrated output voltage Vint from comparator <NUM> against a reference voltage VREF2, and the output of comparator <NUM> is fed to the D input of clocked DFF <NUM>. The clocked DFF <NUM> provides digital output streams <NUM> responsive to the output of the comparator <NUM>. The digital output stream <NUM> may be fed to a digital filter before being output as digital output bits <NUM>. The clock period for clocked DFF <NUM> is configurable for different Ineu ranges.

Calibration methods <NUM>, <NUM><NUM>, and <NUM> will now be discussed with reference to <FIG>, <FIG>, <FIG>, and <FIG>, respectively. Methods <NUM>, <NUM>, <NUM>, and <NUM> compensate for leakage and/or offset.

<FIG> depicts calibration method <NUM> to compensate for leakage and/or offset. A leakage and/or offset calibration step is performed (step <NUM>). The leakage and/or offset is measured and the measured amounts are stored as leakage_value and/or offset_value (step <NUM>). The LSB is determined using the formula: LSB = leakage_value and/or offset_value + deltaLmin. Optionally, deltaLMin is a current value that compensates for variation between levels due process, temperature, noise, or usage degradation and that ensures that the separation between levels is adequate. deltaLmin optionally can be determined from a sample data characterization. (step <NUM>). The MSB is determined using the formula: MSB = LSB + (N-<NUM>) * deltaL, where N is the number of levels and deltaL is a delta level amount that is equal to an average or ideal difference between two consecutive levels. (step <NUM>). In one embodiment, DeltaL is equal to the LSB. In another embodiment, DeltaL is determined from a sample data characterization. DeltaL may have uniform or non-uniform values for different pairings of consecutive levels.

For example for a <NUM>-bit memory cell, there are <NUM> levels of currents, with each level relating to a weight in a neural network application, where N=<NUM>. A minimal offset current may be injected in this step during the calibration and during the measuring steps to create a baseline value.

Table <NUM> contains exemplary values for a <NUM>-bit cell:.

<FIG> depict calibration method <NUM>, which comprises one or more of real-time calibration method <NUM> and background calibration method <NUM>.

In real-time calibration method <NUM>, a leakage and/or offset calibration is performed, comprising measuring the leakage and/or offset and storing the measured values as leakage_value and/or offset_value (step <NUM>). The LSB is determined using the following formula: LSB level = leakage_value and/or offset_value plus deltaLmin. (step <NUM>). The MSB is determined using the following formula: MSB = LSB + (N-<NUM>)*deltaL, where N is the number of levels (step <NUM>) The description of deltaLmin and deltaL as to <FIG> applies in <FIG> as well. A numerical example is as follows: leakage and offset = 200pA, deltaLmin = 300pA, LSB = 500pA, deltaL = 400pA, N=<NUM>, then MSB = 500pA + (<NUM>-<NUM>)*400pA = 6500pA.

In background calibration method <NUM>, offset_value and/or leakage_value + temperature data are stored in fuses (e.g. a look-up-table for offset and/or leakage vs. temperature) (step <NUM>). This is done once or periodically in a background calibration step. The offset_value and/or leakage_value + temperature data is recalled (step <NUM>). A temperature adjustment for offset_value and/or leakage_value is performed as a per look-up-table or by device transistor equation (step <NUM>). The LSB is then determined using the following formula: LSB level = offset_value and/or leakage_value + deltaLmin (step <NUM>). The MSB is determined using the following formula: MSB = LSB + (N-<NUM>)*deltaL (step <NUM>). The description of deltaLmin and deltaL as to <FIG> applies in <FIG> as well. The temperature adjustment can be done by a look-up-table or extrapolated from device equation (e.g., sub-threshold, linear, or saturation equation).

<FIG> depicts calibration and conversion method with automatic leakage and/or offset cancellation <NUM>. A leakage and/or offset calibration is performed (step <NUM>). The leakage and/or offset is measured such as by ADC conversion, and the measured digital outputs are stored in a counter (step <NUM>). The conversion of neuron output is enabled, and a count down is performed in the counter until the counter reaches zero (which compensates for the leakage and/or offset that was initial stored in the counter), then a count up is performed on the digital output bits (step <NUM>).

<FIG> depicts a calibration and conversion method with automatic leakage and/or offset cancellation <NUM>, which is a variation of method <NUM> and falls within the scope of protection of appended claim <NUM>. A leakage and/or offset calibration is performed (step <NUM>). The leakage and/or offset is measured such as by ADC conversion, and the measured digital outputs are stored in a register (step <NUM>). The conversion of neuron output is enabled, and a count up is performed on the digital output bits and then the stored digital outputs are subtracted (step <NUM>).

Claim 1:
A calibration method (<NUM>) of operating an output circuit block for analog neural network non-volatile memory array cells, comprising:
performing leakage or offset calibration (<NUM>);
measuring leakage of the analog neural network non-volatile memory array cells using analog-to-digital conversion or measuring offset from the analog neural network non-volatile memory array cells using analog-to-digital conversion, and storing the measured digital outputs in a register (<NUM>); and
converting a neuron output by counting up digital output bits from the neuron and then subtracting the stored measured digital outputs (<NUM>).