Patent Description:
<CIT> discloses a semiconductor package including a semiconductor die having redistributed pads and a protective layer covering the semiconductor die and the carrying base.

It is known to enclose semiconductor devices comprising a single die or a plurality of reciprocally coupled dice in a housing or package of insulating material, typically of resin or composite material. These packages may be configured differently, according to the intended type of mounting. Furthermore, in case the device is designed to work at high voltage and/or current, these packages usually comprise structures capable of dissipating heat on one or more sides.

Hereinafter, reference will be made to packages providing dual side cooling, for surface mounting, having input/output (I/O) pads arranged on the bottom side of the device.

For example, <CIT> describes different surface mounting package structures, designed to reduce the risk of die/dice breakdown during lamination of the housing material. In these known package structures, a conductive base, typically of metal, has a cavity accommodating a die and a protective layer passed by conductive vias.

A package structure of the type described in the aforementioned patent may be formed, for example, using the process shown in <FIG> and described hereinafter.

<FIG> shows a conductive base <NUM> of metal, such as copper or other metal or metal alloy, having a top surface 1A and a bottom surface 1B.

The top surface 1A is shaped and has a plurality of accommodation cavities <NUM>, surrounded by a separation cavity <NUM>. The accommodation cavities <NUM> may have a substantially parallelepiped shape, with a bottom surface 2A connected to side walls 2B. The side walls 2B are defined by projections <NUM> of the conductive base <NUM>.

The conductive base <NUM> may be formed, for example, from a metal band, processed to remove the metal in the cavities <NUM> and <NUM>.

With reference to <FIG>, dice <NUM> are bonded to the accommodation cavities <NUM> through conductive adhesive regions <NUM>, for example of a conductive gel or an epoxy layer.

The dice <NUM> may integrate single power components or integrated circuits including power components, processing components and electrical connections, schematically shown in the figures and connected to the outside by pads <NUM> arranged on the front side of the dice <NUM>.

The dice <NUM> are bonded to the bottom surface 2A of the respective accommodation cavity <NUM> on their back side.

Subsequently, <FIG>, a protective layer <NUM> is deposited on the conductive base <NUM> and on the dice <NUM>, for example using a lamination technique. The protective layer <NUM> is, for example, of polyamide (so-called prepeg). The protective layer <NUM> is deposited in a fluid state so as to penetrate into the accommodation cavities <NUM>, between the side walls 2B and the dice <NUM>, as well as within the separation cavity <NUM>, and completely covers the dice <NUM> with a portion 10A extending above the accommodation cavities 2A.

In <FIG>, vias <NUM> are formed in the protective layer <NUM>, for example by laser drill, possibly after covering the protective layer <NUM> through a thin anti-reflective layer (not shown), for example of copper. The vias <NUM> extend for the entire thickness of the portion 10A of the protective layer <NUM> up to the pads <NUM> which are thus exposed. Furthermore, the vias <NUM> are also formed on the projections <NUM>.

In <FIG>, a conductive layer <NUM> is formed on the protective layer <NUM> and fills the vias <NUM>. The conductive layer <NUM> may be of copper or an alloy thereof.

In <FIG>, the conductive layer <NUM> is patterned, for example by etching, to form connection regions <NUM>, each in electrical contact with a respective pad <NUM> or with the respective projection <NUM> of the conductive base <NUM>.

In <FIG>, a first insulating layer <NUM>, for example an insulating alloy or solder, is formed and shaped above and between the connection regions <NUM>. The first insulating layer <NUM> has first openings <NUM> at the connection regions <NUM>.

Furthermore, a second insulating layer <NUM> is formed and shaped on the bottom surface 1B of the conductive base <NUM>. The second insulating layer <NUM> has second openings <NUM>, for example one for each die <NUM>, underlying the respective die <NUM>.

In <FIG>, top outer pads <NUM> are formed in the first openings <NUM> of the first insulating layer <NUM> and bottom outer pads <NUM> are formed in the second openings <NUM> on the bottom surface 1B of the conductive base <NUM>. The outer pads <NUM> and <NUM> are of electrically conductive material and are formed, for example, through an ENIG (Electroless Nickel Immersion Gold) process, that is by galvanic nickel growth and formation of a thin gold layer obtained by immersion, to improve the possibility of soldering and the non-oxidability.

The connection regions <NUM> and the top outer pads <NUM> form top terminals of the device; the bottom outer pads <NUM> form bottom terminals as well as thermal dissipation surfaces of the devices (not yet separated).

In a not-shown manner, connection elements, such as solder balls, not shown, may be formed on the outer pads <NUM> and <NUM>.

Hereinafter, <FIG>, the conductive base <NUM> is cut along scribe lines passing through the protective layer <NUM> arranged in the separation cavity <NUM>, forming single packaged devices <NUM> (one shown). For example, in <FIG>, the packaged device <NUM> comprises a single die <NUM> arranged in an own accommodation cavity <NUM>.

In <FIG>, the packaged device <NUM> is flipped over and bonded to a board <NUM>, for example of a printed circuit, through solder zones <NUM> of conductive material, such as solder, applied at the top outer pads <NUM> and soldered to contacts <NUM> formed on the board <NUM> (see also the lateral view of <FIG> and the enlarged cross-section of <FIG>).

Returning to <FIG>, the bottom outer pad <NUM> remains here exposed and may be used for the electrical connection of the conductive base <NUM>, in a not-shown manner.

The package shown in <FIG> provides good protection and high dissipation, but may be improved.

In fact, it does not allow a simple inspection of the solder zones <NUM> which electrically connect the front outer pads <NUM> to the board <NUM>, since they are arranged hidden under the device <NUM>, as may be seen from <FIG>. Consequently, their integrity may not be ensured, reducing the Board Level Integrity (BLR).

On the other hand, more and more applications, such as automotive, have high reliability and quality requirements, which are not obtainable with the described packaging.

The aim of the present invention is to provide a package which overcomes the drawbacks of the prior art.

According to the present invention, a packaged electronic device and the manufacturing method thereof are provided, as defined in the accompanying claims.

For a better understanding of the present invention, embodiments thereof are now described, purely by way of nonlimiting example, with reference to the accompanying drawings, wherein:.

<FIG> shows a carrying base <NUM>, typically of metal, such as copper or other metal or alloy, having a top surface 30A and a bottom surface 30B.

The top surface 30A is shaped and has a plurality of accommodation cavities <NUM>, surrounded by a separation cavity <NUM>.

The separation cavity <NUM> has, for example, a grid shape and extends along first lines passing through the drawing plane (parallel to a first axis Y of a Cartesian reference system XYZ) and along second lines parallel to a second axis X of the Cartesian reference system XYZ.

The accommodation cavities <NUM> may have a substantially parallelepiped, cubic, generally polyhedral or even cylindrical shape, provided with a bottom surface 32A connected to side walls 32B. The side walls 32B are formed by projections <NUM> of the carrying base <NUM>.

The carrying base <NUM> may be formed, for example, from a metal band, which is processed to remove the metal in the cavities <NUM> and <NUM>.

The dice <NUM> may integrate single power components or integrated circuits including power components, processing components and electrical connections, schematically shown in the figures and connected to the outside through die pads <NUM> arranged on the front side of the dice <NUM>.

The dice <NUM> are bonded to the bottom surface 32A of the respective accommodation cavity <NUM> with their back side.

Subsequently, <FIG>, a protective layer <NUM> is deposited on the carrying base <NUM> and on the dice <NUM>, for example by using a lamination technique. The protective layer <NUM> is, for example, of polyamide (so-called prepeg). The protective layer <NUM> is deposited in a fluid state so as to penetrate into the accommodation cavities <NUM>, between the side walls 2B and the dice <NUM>, as well as within the separation cavity <NUM> (where it forms a filling portion <NUM> having the grid shape of the separation cavity <NUM>). The protective layer <NUM> also completely covers the dice <NUM> with a covering portion 40A extending above the accommodation cavities 32A and the filling portion <NUM>.

The covering portion 40A of the protective layer <NUM> may have a thickness comprised between <NUM> and <NUM>.

In <FIG>, first and second vias 43A, 43B are formed through the covering portion 40A of the protective layer <NUM>, for example by laser drill, possibly after covering the protective layer <NUM> through a thin anti-reflective layer (not shown), for example of copper. The first vias 43A extend along the whole thickness of the covering portion 40A of the protective layer <NUM> up to the die pads <NUM>, which are thus exposed; the second vias 43B extend on the projections <NUM> of the carrying base <NUM>.

Furthermore, grooves <NUM> are formed in the filling portion <NUM> of the separation cavity <NUM>. The grooves <NUM> may have depths equal to the vias 43A, 43B (as shown in <FIG>) or different depth, typically greater, up to half the thickness of the carrying base <NUM> or even more if desired. For example, according to the package type, they may have depths of at least <NUM>, typically <NUM>-<NUM>, but they may reach <NUM> in the case of <NUM>-thick packages. However, they may also have a smaller thickness, e.g. <NUM>-<NUM>, in the case of standard MLP/QFN packages.

The grooves <NUM> also have a minimum width of <NUM> or, in any case, so that they may be coated in the successive plating step, as described hereinafter with reference to <FIG>, without being filled.

The grooves <NUM> may be formed by laser ablation, by blade/saw surface cutting, by shallow dicing or even by etching, in predetermined positions, at the vias 43A, 43B (hereinafter generically referred to as vias <NUM>, if it is not necessary to distinguish them) or along the lines of the separation cavity <NUM>, as shown in <FIG> (practically forming a single grid-shaped groove).

When the grooves <NUM> are formed by laser ablation or etching, they may be formed simultaneously with the vias <NUM>.

The grooves <NUM> may have vertical walls, in particular when formed by blade/saw cutting, or slightly inclined walls (<NUM>-<NUM>°), if formed by laser ablation.

If the grooves <NUM> are formed by blade/saw cutting, they have non-perfectly smooth walls, which may be useful in helping sticking in the successive plating step (as described hereinafter with reference to <FIG>).

In <FIG>, a conductive layer <NUM> is formed on the protective layer <NUM> and fills the vias <NUM>. The conductive layer <NUM> also coats the bottom and flanks of the grooves <NUM>. The conductive layer <NUM> may be of copper or an alloy thereof and have a thickness of <NUM>-<NUM>, also according to the width of the grooves <NUM>, and may be galvanically deposited (copper plating).

In <FIG>, the conductive layer <NUM> is defined or patterned, for example by etching, to form connection regions <NUM> for the electrical connection of the die pads <NUM> and of the carrying base <NUM>.

Each connection region <NUM> has a connecting portion 45A extending in a respective via <NUM>; a surface portion 46A, extending above the protective layer <NUM>, and a vertical portion 46B, extending on the flank of the adjacent groove <NUM>.

In <FIG>, a first insulating layer <NUM>, for example an alloy or an insulating solder, is formed above the intermediate structure of <FIG>. The first insulating layer <NUM> is then patterned, so as to have first openings <NUM> at the connection regions <NUM>.

Furthermore, a second insulating layer <NUM> is formed and patterned on the bottom surface 30B of the carrying base <NUM>. The second insulating layer <NUM> has second openings <NUM>, for example one for each die <NUM>, underlying the respective die <NUM>.

In general, the first and the second insulating layers <NUM>, <NUM> are of the same material and may be deposited and patterned in two different steps.

In <FIG>, front outer connections are formed in the first openings <NUM> of the first insulating layer <NUM>, on the connection regions <NUM>; and back outer connections <NUM> are formed in the second openings <NUM> on the bottom surface 30B of the carrying base <NUM>. The back outer connections <NUM> also form thermal dissipation surfaces.

In particular, in <FIG>, the front outer connections <NUM> have top portions <NUM> extending on the front side of the dice <NUM>, directly on the surface portions 46A of the connection regions <NUM>; side portions <NUM> extending on the vertical portions 46B of the connection regions <NUM>; and bottom portions <NUM> extending on the bottom sections 46C of the connection regions <NUM>.

The outer connections <NUM> and <NUM> are of high electrical conductivity material and are, for example, formed through ENIG (Electroless Nickel Immersion Gold) process, that is by galvanic growth of nickel and formation of a thin gold layer obtained by immersion.

In this step, the vertical portions 46B and the side portions <NUM>, facing each other, of two different dice <NUM>, may still be connected to each other through the bottom sections 46C and the bottom portions <NUM> at the bottom of the groove <NUM> (e.g. as shown in <FIG>) and are subsequently separated during the cutting step, as explained hereinafter.

Alternatively, as shown in <FIG>, the vertical portions 46B and the side portions <NUM>, facing each other, of different dice <NUM>, may be separated from each other, with smaller bottom sections 46C and bottom portions <NUM> that are not connected in pairs.

Hereinafter, <FIG>, the intermediate structure of <FIG> is cut along scribe lines passing through the filling portions <NUM> of the protective layer <NUM>, forming single packaged devices <NUM> (one shown). For example, in <FIG>, the packaged device <NUM> comprises a single die <NUM> arranged in an own accommodation cavity <NUM>.

In practice, the scribe lines pass through the bottom portions <NUM> of the front outer pads <NUM>, removing them almost completely and the side portions <NUM> of the front outer connections <NUM> are exposed along the side of the packaged device <NUM>.

Following the cut, each packaged device <NUM> has a front surface 57A, a back surface 57B, opposite to the front surface, and a side surface 57C extending between the front surface and the back surface.

In this manner, after cutting, the connection regions <NUM> and the front outer connections <NUM> form I/O terminals <NUM> of the packaged devices <NUM>. In particular, the I/O terminals <NUM> are formed by first connection portions in the vias <NUM>, in electrical contact with the die pads <NUM> (formed by the connecting portions 45A of the connection regions <NUM>); by second connection portions, comprising the vertical portions 46B of the connection regions <NUM> and the side portions <NUM> of the front outer connections <NUM> extending above the protective layer <NUM>, along the side surface 57C of the packaged device <NUM>; and by third connection portions, comprising the surface portions 46A of the connection regions <NUM> and the top portions <NUM> of the front outer connections <NUM>, extending above the protective layer <NUM>, along the front surface 57A of the packaged device <NUM>.

Remarkably, the shape of the surface portions 46A of the connection regions <NUM> and the top portions <NUM> of the front outer connections <NUM> is designed to electrically connect the die pads <NUM> and the projections <NUM> according to the desired configuration, in a manner that is obvious to a person skilled in the art. For example, <FIG> shows an embodiment where the front outer connections <NUM> do not extend above the first vias 43A.

Then, <FIG>, the packaged device <NUM> is flipped over and bonded to a board <NUM>, for example of a printed circuit. To this end, the board <NUM> has contacts <NUM> arranged at the I/O terminals <NUM> and precisely at the top portions <NUM> of the front outer connections <NUM>; and solder regions <NUM> of conductive material, e.g. solder, have been previously applied to the contacts <NUM> on the board <NUM> or to the I/O terminals <NUM>. The solder regions <NUM> may be applied by screen printing and heat treatment, according to techniques known to the person skilled in the art.

In particular, as visible in the cross-section of <FIG>, in the packaged device <NUM> the solder regions <NUM> may adhere both to the top portions <NUM> and to the side portions <NUM> of the front outer connections <NUM>.

Consequently, the packaged device <NUM> has a wettable flank package, as desired in some applications wherein high Board Level Reliability (BLR) of the soldering is desired, for example in the automotive field.

In fact, in this manner, the solder area considerably increases; furthermore, the side portions <NUM> of the front outer connections <NUM> are optically inspectable in a simple manner, both by human operators and automatically, allowing the solder integrity to be easily verified (reliable and inspectable meniscus).

These advantages are all the more evident as deeper are the grooves <NUM> and thus the greater is the height of the side portions <NUM> of the front outer connections <NUM> (and of the respective underlying vertical portions 46B of the connection regions <NUM>) which, as said, may reach half the thickness of the carrying base <NUM> (as a first approximation, equal to the thickness of the packaged device <NUM>).

Furthermore, the packaged device <NUM> thus obtained has comparable and only slightly higher manufacturing costs with respect to known devices, since it includes only one additional operating step, for forming the grooves <NUM>.

Claim 1:
A packaged device (<NUM>) having a front surface (57A), a back surface (57B), opposite to the front surface, and a side surface (57C) extending between the front surface and the back surface, the packaged device comprising:
a carrying base (<NUM>);
an accommodation cavity (<NUM>) in the carrying base;
a semiconductor die (<NUM>) in the accommodation cavity (<NUM>), the semiconductor die having die pads (<NUM>);
a protective layer (<NUM>), covering the semiconductor die and the carrying base;
first vias (43A) in the protective layer, at the die pads (<NUM>); and
connection terminals (<NUM>) of conductive material, the connection terminals having first connection portions (45A) in the first vias (43A), in electrical contact with the die pads (<NUM>), characterized by second connection portions (46B, <NUM>), extending on the protective layer (<NUM>), along the side surface (57C) of the packaged device.