Patent Description:
Boost converters are widely used in battery-powered portable electronic devices for a step up of the supply voltage of a battery to a stabilized higher output voltage, which in turn can allow for a reduced antenna and coil size which can reduce the footprint of a mobile electronic device so that it may be small and lightweight. In order to extend the battery life and assure the display quality, high efficiency and fast dynamic response are required.

Modern boost converters preferably operate where single current pulses occur. The time between pulses varies with the load, but should be uniformly distributed. In a burst mode, multiple pulses rapidly follow each other, with no idling time in between. The burst mode is caused by delays in the feedback loop and results in a high ripple on the output voltage and higher switching losses.

<CIT> describes a voltage converter that includes a converting circuit having an inductor connected to a switching node, a first switch element connected between the switching node and a ground voltage, and a second switch element connected between the switching node and an output node; and a switching control circuit configured to adjust a feedback voltage divided from an output voltage of the output node based on a current state of the inductor, and configured to generate switching control signals for charging the inductor with an input voltage and discharging a voltage charged in the inductor, based on a sensing signal based on a current of the inductor and the adjusted feedback voltage.

<CIT> describes an inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a 'ramp' signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the 'off' time, an emulated current generator circuit produces the 'ramp' signal during both 'off' and 'on' times, a comparator circuit compares the 'ramp' signal with at least one threshold voltage which varies with the sensed current and toggles an output when the 'ramp' exceeds the thresholds, and a feedback circuit produces an output which adjusts the 'ramp' signal each time the comparator circuit output toggles until the 'ramp' signal no longer exceeds the threshold voltages.

<CIT> describes an apparatus that comprises a buck-boost converter circuit, a ripple emulator circuit, a ripple based controller circuit, and a switch control circuit. The buck-boost converter circuit includes a plurality of switches to be coupled to an inductor, and is configured to generate a regulated output voltage responsive to an input voltage. The ripple emulator circuit is configured to emulate inductor current ripple for a buck phase and a boost phase of the buck-boost converter to provide an emulated inductor current ripple. The ripple based controller circuit is configured to generate a hysteretic control signal responsive to the emulated inductor current ripple and the output voltage. The switch control circuit is configured to generate control signals for driving the plurality of switches responsive to the hysteretic control signal and a clock signal.

Japanese Patent Application Publication <CIT> discloses a buck converter with a control circuit performing hysteretic control, using synthetic ripple signals which are generated based on the voltage sensed at the switching node of the buck converter.

A conventional boost converter voltage loop circuit typically includes a comparator, a reference, and a feedback divider. A conventional approach to reducing instability is to add an equivalent series resistance (ESR) to an output capacitor in parallel with the feedback divider coupled to the feedback node of the comparator, which has a relevant influence on system stability. However, an insufficient ESR value may result in a high output ripple, while a larger value of the output capacitor consumes a significant circuit area. In addition, an on-chip sense-FET current sensor at the power stage of the converter may be required to reduce the power consumption that further increases the circuit footprint.

Another conventional approach is to provide an RC network across the inductor for stabilizing the inductor current. However, an RC network is larger on silicon because of the capacitors and can require additional integration complexities to the need for the RC network to insert a zero in the feedback loop for providing an additional phase margin.

In accordance with a first aspect of the present disclosure, a boost converter is provided, as defined in claim <NUM>. This first aspect provides a solution to the problem of to provide a boost converter that does not require an RC network or current sensor for stability.

In brief overview, embodiments of the present inventive concept include a boost converter that does not require an RC network or current sensor for stability, but instead relies on sawtooth-shape voltage signals generated by on time and off time control circuits, respectively, and provided to a voltage loop circuit that allows system stability to be achieved. In particular, the sawtooth-shape voltage signals are received at the two voltage inputs of a comparator circuit or the like, or more specifically, an off-time sawtooth wave of the voltage signals may act on a reference node or non-inverting input and an on-time sawtooth wave of the voltage signals may act on the feedback node or inverting input of a comparator circuit. The "on-time" and "off-time" are well-known periods of the boost converter's duty cycle, where the "on-time" pertains to the amount of time that the loop circuit is turned on in the cycle, and the "off-time" pertains to the amount of time that the loop circuit is turned off.

The difference of the two voltage signals acts similar to a synthetic ripple. This synthetic ripple will emulate a zero in the feedback loop, similar to the RC network, but without the need for the added complexity provided by external or high-voltage components. The zero in the feedback loop provides sufficient phase margin to prevent the burst mode.

<FIG> is a block diagram of a constant on-time boost converter <NUM> at which embodiments of the present inventive concepts can be practiced.

The boost converter <NUM> can be constructed and arranged to produce from an input voltage Vin coupled to a power stage inductor (not shown) a step up voltage that is output as an output voltage Vout from a power stage circuit <NUM>. The boost converter <NUM> can be implemented in general wireless systems of various industrial, commercial, or automotive applications, for example, providing power management for portable devices including mobile products having Li-ion batteries. Unlike other hysteretic power converters, the constant on-time boost converter <NUM> can offer a simple architecture and favorable dynamic response.

As shown in <FIG>, the boost converter <NUM> may comprise a voltage loop circuit <NUM>, a logic circuit <NUM>, a power stage circuit <NUM>, an off-time control circuit <NUM>, and an on-time control circuit <NUM>.

The voltage loop circuit <NUM> may include a comparator or related closed loop error amplifier <NUM> that controls a feed-forward voltage in a DC/DC, DCM, or CCM operation, depending on the configuration and intended features of the amplifier <NUM>. The voltage loop circuit <NUM> may also include a feedback divider, one or more capacitors, reference voltage source, and so on, for example, shown in <FIG>. In some embodiments, the voltage loop comparator <NUM> may have a first input <NUM> that receives an off-time sawtooth wave and a second input <NUM> or feedback node e.g., an inverting input that receives an on-time sawtooth wave. The voltage signals forming the sawtooth waves may be provided by an off-time (Toff) timer <NUM> and an on-time (Ton) timer <NUM>, respectively. The comparator <NUM> may have an output port <NUM> configured to output a trigger signal (vout cmp), i.e., an on trigger signal and/or an off trigger signal generated in response to the receipt by the comparator <NUM> of the received on and off-time sawtooth waves of the sawtooth-type voltage signals, respectively.

The logic circuit <NUM> can be electrically coupled to the output of the voltage loop circuit <NUM> and may determine the duty cycle of the converter, and in doing so may generate a pulse width modulation (PWM) signal or the like for regulating the output voltage of a power converter switching stage including the power stage circuit <NUM>. The logic circuit <NUM> can include a combination of digital logic devices such as a combination of AND OR gate circuits, flip-flips, and so on. In some embodiments, the flip-flop can be a Set-Reset (SR) type flip-flop. The output of the logic circuit <NUM>, e.g., the output (Q) of the SR-type flip-flop, can provide a drive signal to drive an inductor <NUM> (see <FIG>) of the power stage circuit <NUM>. In response to an on-trigger signal, the logic circuit <NUM> can provide a control signal such that the period Ton and/or Toff is controlled to be constant. In one embodiment, the logic circuit <NUM> has at least two RS flip-flops (not shown), each having a set terminal (S), a reset terminal (R) and an output terminal (Q), wherein the set terminal (S) communicates with the output terminal of the comparator <NUM> to receive the trigger signal. The reset terminal (R) of a first flip-flop can be coupled to the output terminal of the on-time control circuit <NUM> and the reset terminal (R) of a second flip-flop can be coupled to the output terminal of the off-time control circuit <NUM>. The output terminals (Q) of the flip-flops may be coupled to the power stage circuit <NUM>.

As shown in <FIG>, the power stage circuit <NUM> may be constructed and arranged as a half-bridge with an inductor <NUM>, for example, a 1µH inductor but not limited thereto.

The power stage circuit <NUM> may include a gate drive circuit <NUM> or the like that receives an input signal from the logic circuit <NUM> of <FIG>. In some embodiments, the logic circuit <NUM> includes first and second SR-type flip-flops (not shown) that output differential signals to a P gate input and a N gate input of the gate driver, respectively, to determine the duty cycle and provide the drive signal to a first switch <NUM>, e.g., an PMOS circuit, and/or a second switch <NUM>, e.g., a NMOS circuit, in communication with a first side of the inductor <NUM>. A second side of the inductor <NUM> is coupled to an input voltage source Vin. The first and second switches <NUM>, <NUM> can be connected in series. In some embodiments, the second switch <NUM> is a NMOS transistor having a source coupled to a ground reference.

Accordingly, the power stage circuit <NUM> is constructed and arranged to include two power devices in series, the first power device driving the inductor <NUM> with an output voltage level and the second power device driving the inductor <NUM> with a ground. During operation, the inductor current can increase linearly when the second switch <NUM> is in a conducting state since the input voltage Vin is at one side of the inductor <NUM> opposite the side of the inductor <NUM> at which the power stage circuit <NUM> is coupled. In particular, the inductor current can increase linearly when the NMOS transistor <NUM> or other switch element is conducting, since the input voltage Vin is connected across the inductor <NUM>.

At the end of the on-time period, the NMOS transistor <NUM> enters an open state and the PMOS transistor <NUM> enters a closed state, thereby connecting the output voltage Vout to the inductor <NUM>. Since Vout > Vin, the inductor current will decrease linearly.

The boost converter <NUM> may operate in either a Continuous Conduction Mode (CCM) or a Discontinuous Current Mode (DCM), or Pulse Frequency Mode (PFM).

In a CCM state, the inductor current increases and decreases with the switching frequency and duty cycle, but the inductor current is not <NUM> Amps during the duty cycle. However, in a DCM, the inductor current returns to <NUM> Amps, and remains at <NUM> Amps for part of the period. The DCM therefore has an on-time (Ton), an off-time (Toff), and an idle time. In CCM, for high load currents, the idle time disappears and the inductor current does not return to <NUM> Amps and instead becomes continuous. Accordingly, when operating in a CCM environment, the control loop including the comparator <NUM> can manage the duty cycle and in doing so can control the on-time Ton (shown in <FIG>) for a constant frequency.

As shown in <FIG>, the on-time control circuit <NUM> may include a capacitor <NUM> that is charged with a current source <NUM> that provides a current (i) that is proportional to the output voltage Vout (e. g, I = k* Vout) until a voltage level Vt proportional to Vout - Vin is reached. The capacitor <NUM> is charged and discharged to form the corresponding sawtooth wave. The sawtooth wave according to the voltage signal Vout - Vin can be provided to the feedback node of the voltage loop comparator <NUM>.

As shown in <FIG>, the off-time control circuit <NUM> may have a same or similar construction as the on-time control circuit <NUM>, i.e., a same or similar current source <NUM> and capacitor <NUM>, except that the comparator voltage trip level Vt is equal to the input voltage Vin. The sawtooth wave according to the voltage signal Vin can be provided to the reference node of the voltage loop comparator <NUM>. It is well-known that the control loop of the converter can permit the synthetic ripple signal to be fed to the comparator <NUM>, which is required to properly switch the comparator <NUM> and to determine the charge and discharge timing of the inductor. A minimum off-time signal value may be required to prevent a deadlock situation during a startup operation. Here, the minimum off-time signal value may be used during startup due to a <NUM>% duty cycle and high inductor current while no power is transferred to the output. In some embodiments, to allow for the control loop to function properly, the minimum off-time should be lower than the steady-state off time. Accordingly, the minimum off-time may be configured to be a fraction of the nominal off-time, for example, <NUM>% of the nominal off-time which may be achieved by applying Vin/<NUM> instead of the input voltage Vin to the comparator input node.

As described above, the difference between the on-time control circuit <NUM> and the off-time control circuit <NUM> is the comparator trip level of each, namely, (Vout - Vin) for an on-time signal value output from the on-time control circuit <NUM> and Vin for an off-time signal value output from the off-time control circuit <NUM>.

<FIG> is a schematic representation of a voltage loop circuit <NUM> of a boost converter, in accordance with an embodiment. The voltage loop circuit <NUM> includes a reference voltage source <NUM> and a feedback circuit <NUM>. In some embodiments, the feedback circuit <NUM> may include a feedback divider <NUM> comprising a combination of resistors, capacitors, and the like.

As shown in <FIG>, the on-time and off-time sawtooth voltages applied to the inputs of the voltage loop comparator <NUM> are active alternately so that one of the on-time circuit and off-time circuit at a time provides a sawtooth voltage signal, which prevents or eliminates mutual influencing, or noise, at the electrical components, for example, the input ports, with respect to each other. In some embodiments, the off-time sawtooth wave received from the Toff timer <NUM> can act on a reference voltage from the reference voltage source <NUM> applied to the reference node of the voltage loop comparator <NUM>. The on-time sawtooth wave received from the Ton timer <NUM> can act on the feedback signal from the node (FB point) of the feedback circuit <NUM> applied to the feedback (inverting input) node of the voltage loop comparator <NUM>. If the on-time sawtooth wave increases, then the feedback voltage at the feedback node increases which reduces the on-time. The current source in the on-time generator depends on the voltage Vout and the current will then increase, resulting in a shorter on-time. On the other hand, the longer the off-time, the larger the voltage of the off-time sawtooth. This will increase the output voltage but reduce the off-time.

The combination of the on-time and off-time voltage signals received and processed by the voltage loop comparator <NUM> can provide a synthetic ripple, for example, shown in <FIG>, which can emulate the inductor current or the voltage across an output capacitor <NUM> in order to regulate the output voltage at the inductor <NUM> at a desired level. More specifically, the positive slope of the ripple corresponds to the off-time voltage signal in response to a charging of the capacitor during the off-time. The off-time sawtooth is fed to the feedback node of the voltage loop comparator <NUM>. The negative slope of the ripple corresponds to the on-time, i.e., discharge of the capacitor occurs during the on-time, and is provided to the reference node. Separating the slopes of the ripple in this manner negates the need for a subtraction operation where the voltages are subtracted from the positive sawtooth and the result is fed to the feedback node. As shown in <FIG>, the sawtooth waves can be generated by identical current sources <NUM>, <NUM> and capacitors <NUM>, <NUM> to provide a reliable operation.

Accordingly, the boost converter may act as a hysteretic converter with respect to the ripple voltages <NUM> at the comparator inputs producing voltage waves similar to those of the inductor currents, as shown in <FIG>. In particular, the waves <NUM> have a similar polarity and phase, and can therefore reduce system instability while providing high reliability. Here, the displayed voltage differential includes a difference of the feedback voltage (Vfb) and the reference voltage (Vref). Any DC error that is introduced is insignificant because it is constant over the range of input voltages and can be compensated.

In other embodiments, a ripple voltage generated by the on-time control circuit <NUM> is not processed by the boost converter <NUM>, since it has no impact at the moment of switch-off. In particular, the state of the feedback comparator at the end of the off-time determines if a next cycle will start. Any ripple inserted during the on-time only is not present during the off-time and may not have an influence on the speed of the feedback comparator. Ripple during the off-time may occur before a next cycle may or may not be started and has much more influence. If the control loop including the loop comparator <NUM> detects the start of a new switching cycle, it can be during the off-time. The output of the on-time control circuit <NUM> is not active, so it has no influence on the generated synthetic ripple. Accordingly, the resistor <NUM> shown in <FIG> in the signal path from the on-time control circuit <NUM> to the voltage loop comparator <NUM> can be omitted.

<FIG> are graphs <NUM>, <NUM> illustrating comparative results between a burst mode of a conventional boost converter and the boost converter of <FIG>. In particular, <FIG> illustrates a synthetic ripple produced by the voltage loop circuit <NUM> to prevent the burst mode shown in <FIG>.

Claim 1:
A boost converter (<NUM>), comprising:
a power stage circuit (<NUM>) configured to generate an output voltage (Vout) in response to a trigger signal;
a comparator circuit (<NUM>), including a first input port and a second input port, the comparator circuit (<NUM>) configured to compare a voltage applied to the first input port and the voltage applied to the second input port to generate said trigger signal by an output port;
a reference voltage source (<NUM>) configured to provide a reference voltage (Vref);
a feedback circuit (<NUM>) comprising a feedback divider configured to generate a feedback voltage signal (VFB) proportional to said output voltage (Vout);
an off-time timer (<NUM>) configured to provide a voltage signal to form an off-time sawtooth voltage wave;
an on-time timer (<NUM>) configured to provide a voltage signal to form an on-time sawtooth voltage wave;
a voltage loop circuit (<NUM>) comprising said comparator circuit (<NUM>), the voltage loop circuit (<NUM>) configured to couple the off-time sawtooth voltage and the reference voltage (Vref) to the first input port of the comparator circuit (<NUM>), and to couple the feedback voltage (VFB) and the on-time sawtooth voltage to the second input port of the comparator circuit (<NUM>);
wherein the on-time sawtooth voltage and the off-time sawtooth voltage are active alternately; and
wherein the slopes of the off-time sawtooth voltage and the on-time sawtooth voltage are proportional to the output voltage, the maximum value of the on-time sawtooth voltage is equal to the difference between the output voltage and an input voltage of the boost converter (<NUM>), and the maximum value of the off-time sawtooth voltage is equal to the input voltage, such that a combination of the off-time sawtooth voltage waveform and the on-time sawtooth voltage waveform provides a synthetic ripple voltage.