Patent Description:
Gallium nitride (gallium nitride, GaN) has advantages of a large width of forbidden band and high mobility, and is widely used in a power electronic device and a radio frequency device, especially in a high electron mobility transistor (high electron mobility transistor, HEMT). The HEMT has a heterostructure that can generate two-dimensional electron gas and also has features of high mobility and high breakdown field strength, and therefore becomes an ideal substitute for a next-generation power electronic device and radio frequency device.

In a structural design of the HEMT, a breakdown voltage is an important design parameter, which basically determines maximum output power of a power device. Specifically, in a structure of a HEMT as shown in <FIG>, the HEMT has a substrate <NUM>, and a GaN buffer layer <NUM>, a barrier layer <NUM>, and a P-type GaN layer <NUM> that are epitaxially formed on the substrate <NUM>, to ensure a longitudinal breakdown voltage of the GaN buffer layer <NUM>. Certainly, the HEMT further includes a source <NUM>, a drain <NUM>, an isolation layer <NUM> that are disposed on the barrier layer <NUM>, and a gate <NUM> disposed on the P-type GaN layer <NUM>. The drain <NUM> separates the isolation layer <NUM> into a first isolation portion <NUM> and a second isolation portion <NUM>, and the first isolation portion <NUM> is in contact with the substrate <NUM> after extending towards a side of the substrate <NUM> to penetrate through the barrier layer <NUM> and the nitride buffer layer <NUM>. During operation of the HEMT, if a source-drain voltage is larger than a breakdown voltage, the transistor is prone to be broken down, and consequently the transistor permanently fails. Therefore, gate-drain spacing is usually increased to nearly double a withstanding voltage, to prevent the transistor from being broken down. However, the increase in the gate-drain spacing undoubtedly enlarges an area occupied by a single device, which causes manufacturing costs to increase.

Document <CIT> describes structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS).

Document <CIT> describes a nitride semiconductor device including a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

This application provides a nitride semiconductor transistor and an electronic device, to provide a current discharge channel when a transistor is broken down, thereby improving security and reliability of a power device. The present invention is defined in the independent claim and the dependent claims define the advantages embodiments thereof.

According to a first aspect, this application provides a nitride semiconductor transistor. The nitride semiconductor transistor may be applied to an electronic device, and provides higher security assurance for the electronic device during operation. Specifically, a structure of the nitride semiconductor transistor includes a substrate structure, a nitride epitaxial structure, and a functional electrode layer that are successively disposed from bottom to up. The substrate structure includes a two-layer structure including a heavily doped P-type substrate and a lightly doped P-type epitaxial layer, and a side that is of the lightly doped P-type epitaxial layer and that is away from the heavily doped P-type substrate extends towards the heavily doped P-type substrate to form an N-type region, which is equivalent to forming a PN-type diode at the bottom of the entire transistor. Because doping concentration of P-type ions in the heavily doped P-type substrate is greater than doping concentration of P-type ions in the lightly doped P-type epitaxial layer, the heavily doped P-type substrate and the lightly doped P-type epitaxial layer enable a current to present unidirectional conductivity of being conducted in one direction from the heavily doped P-type substrate to the lightly doped P-type epitaxial layer, to prevent the current from being conducted to the heavily doped P-type substrate, thereby improving voltage withstanding of the transistor. The nitride epitaxial structure includes a nitride buffer layer, a barrier layer, and a P-type nitride layer that are successively formed on the lightly doped P-type epitaxial layer. The barrier layer is disposed on the nitride buffer layer in a fully covered form, and the P-type nitride layer is disposed only at a specified location on the barrier layer. The functional electrode layer includes a source, a drain, a gate, and an isolation layer. The gate is disposed on the P-type nitride layer, and the source and the drain are disposed on the barrier layers on both sides of the P-type nitride layer. The drain separates the isolation layer into a first isolation portion and a second isolation portion. The first isolation portion herein corresponds to the N-type region to penetrate through the barrier layer and the nitride buffer layer to be in contact with the lightly doped P-type epitaxial layer. A metal connector is formed in the first isolation portion, and the metal connector penetrates through the first isolation portion to connect the drain and the N-type region. During operation, if a source-drain voltage is relatively large, the N-type region is connected to the drain through the metal connector, which is equivalent to providing a discharge channel for a current, to ensure that the transistor is not broken down. Even if a surge phenomenon occurs in use of the transistor, a device is protected from being damaged, to improve device reliability. In addition, gate-drain spacing is not increased in this structure, so that a design redundancy value of a breakdown voltage can be reduced, device density can be improved, and production costs can be decreased.

Based on the foregoing structure, a protection ring combination surrounding the N-type region is further formed on the lightly doped P-type epitaxial layer, to improve an inverse characteristic of the PN-type diode formed by using the heavily doped P-type substrate, the lightly doped P-type epitaxial layer, and the N-type region, thereby enhancing device reliability. Certainly, the protection ring combination specifically includes at least one protection ring using the N-type region as a center, and a quantity of protection rings is not limited.

The heavily doped P-type substrate and the lightly doped P-type epitaxial layer form the substrate structure of the transistor. The lightly doped P-type epitaxial layer may improve controllability and uniformity of a near-surface silicon layer. In a specific implementation, a substrate in the heavily doped P-type substrate may be made of any material in silicon (silicon, Si), silicon carbide (silicon carbide, SiC), silicon nitride (Silicon nitride, SiN), GaN, and sapphire. Certainly, a material of a substrate in the lightly doped P-type epitaxial layer may also be made of any material in Si, SiC, SiN, GaN, and sapphire. In addition, resistivity of the heavily doped P-type substrate is set to be less than <NUM>Ω/mm, and resistivity of the lightly doped P-type epitaxial layer is set to <NUM>Ω/mm to <NUM>Ω/mm. Herein, a thickness of the lightly doped P-type epitaxial layer usually ranges from <NUM> to <NUM>, and a thickness of the heavily doped P-type substrate is not limited. The thickness of the heavily doped P-type substrate may be adjusted based on a thickness of the entire substrate.

Nitride in the nitride epitaxial structure may be one or a combination of several of GaN, aluminum nitride (aluminum nitride, AlN), indium nitride (indium nitride, InN), aluminum gallium nitride (aluminum gallium nitride, AlGaN), indium aluminum nitride (indium aluminum nitride, InAlN), indium gallium nitride (indium gallium nitride, InGaN), and indium aluminum gallium nitride (indium aluminum gallium nitride, InAlGaN). In addition, a material of the metal connector may be tungsten.

According to a second aspect, this application further provides an electronic device, including a device body and any nitride semiconductor transistor that is according to the foregoing technical solutions and that is disposed on the device body. Based on that the nitride semiconductor transistor has higher security and reliability, a service life of the electronic device may be prolonged.

The following clearly and completely describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application.

First, an application scenario of this application is described: A breakdown voltage is an important parameter in a structural design of a HEMT. If a source-drain voltage is greater than the breakdown voltage during operation of the HEMT, the transistor is broken down, and consequently the transistor permanently fails. Currently, a method for improving this condition is to increase gate-drain spacing. However, in this method, a device occupation area is enlarged, device density is reduced, and device costs are increased.

Based on the foregoing application scenario, this application provides a nitride semiconductor transistor, to avoid an adverse effect on a device volume while the foregoing problem that the source-drain voltage is excessively large to break down the device is resolved.

Referring to <FIG>, a structure of the nitride semiconductor transistor includes a substrate structure <NUM>, a nitride epitaxial structure <NUM>, and a functional electrode layer <NUM> that are successively disposed from bottom to up. The substrate structure <NUM> includes a heavily doped P-type substrate <NUM> and a lightly doped P-type epitaxial layer <NUM> that are disposed through stacking. Existence of the lightly doped P-type epitaxial layer <NUM> may improve controllability and uniformity of a near-surface silicon layer. A side that is of the lightly doped P-type epitaxial layer <NUM> and that is away from the heavily doped P-type substrate <NUM> extends towards the heavily doped P-type substrate <NUM> to form an N-type region <NUM>. In this case, it is equivalent to that the heavily doped P-type substrate <NUM>, the lightly doped P-type epitaxial layer <NUM>, and the N-type region <NUM> form a PN-type diode. The nitride epitaxial structure <NUM> is disposed on the lightly doped P-type epitaxial layer <NUM>, and specifically includes a nitride buffer layer <NUM>, a barrier layer <NUM>, and a P-type nitride layer <NUM> that are disposed through stacking. The barrier layer <NUM> herein fully covers the nitride buffer layer <NUM>, and the P-type nitride layer <NUM> is disposed at a specified location on the barrier layer <NUM>, to reserve a part of the barrier layer <NUM> for disposing another structure. The functional electrode layer <NUM> includes a source <NUM>, a drain <NUM>, a gate <NUM>, and an isolation layer <NUM>. The gate <NUM> is disposed on the P-type nitride layer <NUM>, and the source <NUM> and the drain <NUM> are disposed on the barrier layers <NUM> on both sides of the P-type nitride layer <NUM>. In other words, it is equivalent to that the gate <NUM> is disposed between the source <NUM> and the drain <NUM>. The isolation layer <NUM> covers the source <NUM>, the P-type nitride layer <NUM>, and the gate <NUM>, and the drain <NUM> separates the isolation layer <NUM> into a first isolation portion <NUM> and a second isolation portion <NUM>. As shown in <FIG>, the first isolation portion <NUM> corresponds to the N-type region <NUM>, and the first isolation portion <NUM> extends towards the heavily doped P-type substrate <NUM>, and successively penetrates through the barrier layer <NUM> and the nitride buffer layer <NUM> to be in contact with the lightly doped P-type epitaxial layer <NUM>. In addition, a metal connector <NUM> that penetrates through the first isolation portion <NUM> is formed in the first isolation portion <NUM> to connect the drain <NUM> and the N-type region <NUM>, to provide a discharge channel for a current. During operation of the transistor, if a source-drain voltage is relatively large, the foregoing discharge channel provides a channel for the current, so that the transistor can be prevented from being burnt, a surge problem also can be resisted, thereby improving safety and reliability of the transistor. Still referring to the structure of the nitride semiconductor transistor in <FIG>, it can be learned that compared with that in the conventional technology, gate-drain spacing is not increased in this structure, so that a design redundancy value of a breakdown voltage can be reduced, and device density can be improved, to decrease production costs.

Certainly, doping concentration of P-type ions in the heavily doped P-type substrate <NUM> is greater than doping concentration of P-type ions in the lightly doped P-type epitaxial layer <NUM>, so that the heavily doped P-type substrate <NUM> and the lightly doped P-type epitaxial layer <NUM> present unidirectional conductivity. It can be predicted that a current is conducted in one direction from the heavily doped P-type substrate <NUM> to the lightly doped P-type epitaxial layer <NUM>, to prevent the current from flowing to the heavily doped P-type substrate <NUM>, thereby improving voltage withstanding of the transistor. Herein, resistivity of the heavily doped P-type substrate <NUM> may be set to be less than <NUM>Ω/mm, and correspondingly, resistivity of the lightly doped P-type epitaxial layer <NUM> may be set to <NUM>Ω/mm to <NUM>Ω/mm.

In addition, a thickness of the lightly doped P-type epitaxial layer <NUM> usually ranges from <NUM> to <NUM>, and a thickness of the heavily doped P-type substrate <NUM> is not limited. The thickness of the heavily doped P-type substrate <NUM> may be adjusted based on a bottom thickness of the entire transistor.

A material of a substrate in the heavily doped P-type substrate <NUM> may be any one of Si, SiC, GaN, and sapphire. Certainly, a material of a substrate in the lightly doped P-type epitaxial layer <NUM> may also be any one of Si, SiC, GaN, and sapphire. Nitride in the nitride epitaxial structure <NUM> may be one or a combination of several of GaN, AlN, InN, AlGaN, InAlN, InGaN, and InAlGaN. A material of the metal connector <NUM> may be tungsten, and certainly may be other materials with good conductivity (for example copper and copper alloy).

According to the invention, a protection ring combination surrounding the N-type region <NUM> is formed on the side that is of the lightly doped P-type epitaxial layer <NUM> and that is away from the heavily doped P-type substrate <NUM> in the nitride semiconductor transistor shown in <FIG>, to obtain a nitride semiconductor transistor shown in <FIG>. The protection ring combination includes at least one protection ring <NUM>, and each protection ring <NUM> uses the N-type region <NUM> as a center. <FIG> is a top view of the substrate structure <NUM> of this nitride semiconductor transistor. It may be understood that only a protection ring <NUM> closest to the N-type region <NUM> and a protection ring furthest from the N-type region <NUM> are shown in <FIG> and <FIG>. The protection ring combination may improve an inverse characteristic of the PN-type diode formed by using the heavily doped P-type substrate <NUM>, the lightly doped P-type epitaxial layer <NUM>, and the N-type region <NUM>, thereby enhancing device reliability.

It may be understood that the two nitride semiconductor transistor structures shown in <FIG> are merely examples, and a partial structure of the nitride semiconductor transistor is shown by using the N-type region <NUM> as a center. In practical application, the structures shown in <FIG> exist in a continuous manner.

Taking the nitride semiconductor transistor structure shown in <FIG> as an example, for a method for manufacturing the nitride semiconductor transistor, refer to the following steps.

S1: Manufacture a PN junction on a substrate structure <NUM>. The substrate structure <NUM> herein includes a heavily doped P-type substrate <NUM> and a lightly doped P-type epitaxial layer <NUM>, where resistivity of the heavily doped P-type substrate <NUM> is set to be less than <NUM>Ω/mm, and resistivity of the lightly doped P-type epitaxial layer <NUM> is set to <NUM>Ω/mm to <NUM>Ω/mm.

Specifically, the lightly doped P-type epitaxial layer <NUM> of <NUM> to <NUM> is epitaxially formed on the heavily doped P-type substrate <NUM> through chemical vapor deposition or magnetron sputtering, thereby obtaining a structure shown in <FIG>. Then, an alignment mark is etched on the lightly doped P-type epitaxial layer <NUM> for positioning in a subsequent process, and an N-type impurity such as phosphorus is implanted into the lightly doped P-type epitaxial layer <NUM> by using an ion to form an N-type region <NUM> and at least one protection ring <NUM>, thereby obtaining a structure shown in <FIG>.

S2: Manufacture a nitride epitaxial structure <NUM>. The nitride epitaxial structure <NUM> herein refers to a nitride buffer layer <NUM>, a barrier layer <NUM>, and a P-type nitride layer <NUM> that are successively disposed through stacking on the lightly doped P-type epitaxial layer <NUM>, to implement a functional structure of a HEMT. For a structure of the HEMT, refer to <FIG>.

S3: Manufacture a functional electrode layer <NUM> on the nitride epitaxial structure <NUM>. The functional electrode layer <NUM> herein may specifically include a source <NUM>, a drain <NUM>, a gate <NUM>, and an isolation layer <NUM>.

Specifically, corresponding to a region in which the N-type region <NUM> is located, the P-type nitride layer <NUM>, the barrier layer <NUM>, and the nitride buffer layer <NUM> are etched to expose the N-type region <NUM> on the lightly doped P-type epitaxial layer <NUM>, thereby obtaining a structure shown in <FIG>. The P-type nitride layer <NUM> is etched, so that only a part for disposing the gate <NUM> is left, and the other part of the P-type nitride layer <NUM> is etched to expose the barrier layer <NUM>, thereby obtaining a structure shown in <FIG>. The gate <NUM> is disposed on the P-type nitride layer <NUM>, the source <NUM> and the drain <NUM> are separately disposed on the barrier layers <NUM> on both sides of the gate <NUM>, and the isolation layer <NUM> is disposed, so that the drain <NUM> separates the isolation layer <NUM> into a first isolation portion <NUM> and a second isolation portion <NUM>. The first isolation portion <NUM> corresponds to the N-type region <NUM>, thereby obtaining a structure shown in <FIG>. For a top view of the structure shown in <FIG>, refer to <FIG>. A through hole <NUM> extending to the N-type region <NUM> is formed on the first isolation portion <NUM>, thereby obtaining a structure shown in <FIG>. The through hole <NUM> is filled with tungsten metal to form a metal connector <NUM>, thereby obtaining a structure as shown in <FIG>. The drain <NUM> is extended to be connected to the metal connector <NUM>, to implement connection between the drain <NUM> and the N-type region <NUM>, thereby obtaining the nitride semiconductor transistor shown in <FIG>.

Claim 1:
A nitride semiconductor transistor, comprising a substrate structure (<NUM>), a nitride epitaxial structure (<NUM>), and a functional electrode layer (<NUM>), wherein
the substrate structure (<NUM>) comprises a heavily doped P-type substrate (<NUM>) and a lightly doped P-type epitaxial layer (<NUM>) that are disposed through stacking, and an N-type region (<NUM>) extending from a side that is of the lightly doped P-type epitaxial layer and that is away from the heavily doped P-type substrate towards the heavily doped P-type substrate ;
the nitride epitaxial structure (<NUM>) comprises a nitride buffer layer (<NUM>), a barrier layer (<NUM>), and a P-type nitride layer (<NUM>) that are successively formed on the lightly doped P-type epitaxial layer (<NUM>);
the functional electrode layer (<NUM>) comprises a source (<NUM>), a drain (<NUM>), a gate (<NUM>), and an isolation layer (<NUM>), the source and the drain are disposed on the barrier layer (<NUM>), the gate is disposed on the P-type nitride layer (<NUM>), and the isolation layer covers the source, the gate, the barrier layer, and the P-type nitride layer; and
the drain (<NUM>) separates the isolation layer (<NUM>) into a first isolation portion (<NUM>) and a second isolation portion (<NUM>), the first isolation portion penetrates through the barrier layer (<NUM>) and the nitride buffer layer (<NUM>) to be in contact with the lightly doped P-type epitaxial layer (<NUM>) and the N-type region (<NUM>), a metal connector (<NUM>) is formed in the first isolation portion, and the metal connector penetrates through the first isolation portion to connect the drain and the N-type region,
wherein a protection ring combination surrounding the N-type region (<NUM>) is formed on the lightly doped P-type epitaxial layer (<NUM>), and
wherein the protection ring combination comprises at least one protection ring (<NUM>) and said at least one protection ring is N-type.