Patent Description:
The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof.

As a semiconductor device commonly used in an electronic device such as a computer, a dynamic random access memory (DRAM) includes a plurality of memory cells, and each of the memory cells usually includes a transistor and a capacitor. The transistor has a gate being electrically connected to a word line, a source being electrically connected to a bit line, and a drain being electrically connected to the capacitor. A word line voltage on the word line can control on and off of the transistor, such that data information stored in the capacitor can be read through the bit line or data information can be written into the capacitor through the bit line.

The semiconductor structure such as a DRAM with a transistor on capacitor (TOC) structure is not compatible with peripheral circuits due to the structural limitation, and leakage easily occurs between a capacitor and a substrate. In addition, the manufacturing process of DRAM and other semiconductor structure is complex and has high manufacturing cost.

Therefore, how to improve the performance of the semiconductor structure and reduce the difficulty of the semiconductor manufacturing process is an urgent technical problem to be solved. Related technology is known from <CIT>, <CIT>, <CIT>, <CIT>, and <CIT>.

A semiconductor structure and a forming method thereof provided by some embodiments of the present disclosure are used to improve the performance of the semiconductor structure and reduce the difficulty of the semiconductor manufacturing process. The invention is defined by the independent claim and its dependent claims.

In the semiconductor structure and the forming method thereof provided by some embodiments of the present disclosure, the transistor structure is arranged above the capacitive structure, and the bit line structure is arranged above the transistor structure, to form a semiconductor structure having a TOC structure. It is unnecessary to form a bit line structure below the transistor structure through a deep hole etching process, thereby reducing the manufacturing difficulty of bit lines, and reducing the manufacturing cost of the semiconductor structure. Moreover, because the bit line structure is located above the transistor structure, the bit line may be manufactured using various materials (such as a metal material), which helps reduce the resistance of the bit line and improve the performance of the semiconductor structure, such that the bit line is more compatible with a subsequent peripheral circuit process.

Specific implementations of a semiconductor structure and a forming method thereof provided in the present disclosure are described in detail below with reference to the accompanying drawings.

The specific implementation provides a semiconductor structure. <FIG> is a schematic structural diagram of a semiconductor structure according to a specific implementation of the present disclosure. In the specific implementation, the semiconductor structure may be, but is not limited to, a DRAM. As shown in <FIG>, the semiconductor structure in the specific implementation includes:.

Specifically, the substrate <NUM> may be, but is not limited to, a silicon substrate. This specific implementation is described by taking the substrate being the silicon substrate as an example. In other examples, the substrate <NUM> may be a semiconductor substrate such as a gallium nitride substrate, a gallium arsenide substrate, a gallium carbide substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. The substrate <NUM> is configured to support device structures thereon. A top surface of the substrate <NUM> refers to a surface of the substrate <NUM> on which the capacitive structure is formed.

The capacitive structure includes the plurality of capacitors arranged in a two-dimensional array along the first direction D1 and the second direction D2. Each of the capacitors extends along a third direction D3, where the third direction D3 is a direction perpendicular to the top surface of the substrate <NUM>. The transistor structure is located above the capacitive structure, and the transistor structure includes the plurality of active pillars <NUM> arranged in a two-dimensional array along the first direction D1 and the second direction D2. The active pillar <NUM> includes a channel region, and a drain region and a source region arranged on two opposite sides of the channel region along the third direction D3. The capacitor is in contact with and electrically connected to the drain region. The transistor structure further includes a plurality of word lines <NUM>, and a word line isolation layer <NUM> located between adjacent ones of the word lines <NUM>. The word line <NUM> extends along the second direction D2, and continuously cover the active pillars <NUM> arranged at intervals along the second direction D2, to form the word line <NUM> of a channel-all-around structure. The bit line structure includes the plurality of bit lines <NUM>. The bit line <NUM> is located above the transistor structure, such that the bit line <NUM> can be formed by using a metal material such as tungsten, thereby reducing the resistance of the bit lines and manufacturing difficulty of the bit lines. Moreover, by arranging the bit line <NUM> above the transistor structure, the bit line is compatible with peripheral circuit processes such as a processor core (CORE), a sense amplifier (SA), and input/output (I/O).

In some embodiments, the capacitor includes:.

Specifically, the bottom electrode in the capacitor includes the conductive pillar <NUM> extending along the third direction D3 and the conductive layer <NUM> covering a sidewall of the conductive pillar <NUM>. The dielectric layer <NUM> covers a sidewall of the conductive layer <NUM>, a surface of the substrate isolation layer <NUM>, and a bottom surface of the word line isolation layer <NUM>. The top electrode <NUM> covers the surface of the dielectric layer <NUM>.

In some embodiments, the dielectric layer <NUM> is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer <NUM> and the top electrode <NUM> each are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

Specifically, the dielectric layer <NUM> may be made of a strontium titanate (STO) material with a high dielectric constant (HK); the conductive layer <NUM> and the top electrode <NUM> may be made of ruthenium or ruthenium oxide, etc., thereby reducing the height of the capacitor along the third direction D3, and reducing the etching depth during etching if the capacitor hole for forming the capacitor, to further reduce the process difficulty. In other examples, the dielectric layer <NUM> may be made of any one or more of aluminum oxide, zirconium oxide, and hafnium oxide; accordingly, the conductive layer <NUM> and the top electrode <NUM> are made of TiN, etc., to reduce the manufacturing cost of the semiconductor layer structure.

In some embodiments, a material of the conductive pillar <NUM> is a silicide material including first dopant ions, to enhance the conductivity of the conductive pillar <NUM>. In an embodiment, the drain region includes second dopant ions. The second dopant ions and the first dopant ions are of a same type, to further reduce the contact resistance between the conductive pillar <NUM> and the drain region.

In some embodiments, the semiconductor structure further includes:
a substrate isolation layer <NUM>, located between the substrate <NUM> and the capacitive structure.

Specifically, a material of the substrate isolation layer <NUM> may be, but is not limited to, an insulation material such as an oxide (such as silicon dioxide). The substrate isolation layer <NUM> is formed between the substrate <NUM> and the capacitive structure to isolate an electrical leakage channel from the bottom of the capacitor to the substrate <NUM>, thereby reducing the electrical leakage between the capacitor and the substrate <NUM>.

In some embodiments, the substrate isolation layer <NUM> includes:.

Specifically, the substrate isolation layer <NUM> includes the first substrate isolation sub-layer continuously distributed below the plurality of conductive pillars <NUM> and the second substrate isolation sub-layer covering the surface of the first substrate isolation sub-layer, such that the forming process of the substrate isolation layer can be carried out while the capacitor hole is formed, to ensure that the substrate isolation layer is directly formed below the capacitor, thereby ensuring that the substrate isolation layer can be fully aligned with the bottom of the capacitor. This simplifies a manufacturing process of the semiconductor structure and reduces process difficulty of the semiconductor structure, and can further improve an effect of electrical isolation between the capacitor and the substrate.

In other examples, the substrate isolation layer <NUM> may also be a single-layer structure. For example, the substrate isolation layer <NUM> is a single oxide layer located between the substrate <NUM> and the capacitive structure.

In some embodiments, each of the active pillars <NUM> includes a channel region, and a drain region and a source region that are arranged on two opposite sides of the channel region along a direction perpendicular to the top surface of the substrate <NUM>.

Moreover, along the first direction D1 and the second direction D2, a width of the source region is greater than a width of the channel region, and a width of the drain region is greater than the width of the channel region.

Specifically, along the third direction D3, the drain region is located below the channel region, the source region is located above the channel region, and the drain region is electrically connected to the bottom electrode of the capacitor. Along the first direction D1 and the second direction D2, the widths of the source region and the drain region are both greater than the width of the channel region, thereby providing a larger space for forming the word line <NUM>, which not only helps simplify the manufacturing process of the semiconductor structure, but also helps further reduce the size of the semiconductor structure, to adapt to application requirements of different fields.

In some embodiments, the plurality of word lines <NUM> are arranged at intervals along the first direction D1; and the transistor structure further includes:
a word line isolation layer <NUM>, located between adjacent ones of the word lines <NUM>.

In some embodiments, the transistor structure further includes:
a protective layer <NUM>, located between the word line isolation layer <NUM> and the active pillar <NUM> and covering a sidewall of the source region, and along the first direction D1, an edge of the protective layer <NUM> is flush with an edge of the word line <NUM>.

Specifically, a material of the protective layer <NUM> may be, but is not limited to, an insulating material such as nitride (e.g., silicon nitride). The protective layer <NUM> not only can be used to electrically isolate two adjacent source regions, but also can be used as mask layer during forming of the word line <NUM>, thereby reducing the number of masks and further reducing the manufacturing cost of the semiconductor structure.

In some embodiments, the transistor structure further includes source electrodes <NUM> located on top surfaces of the active pillars <NUM>; and the bit line structure further includes:
a bit line plug <NUM>, where a bottom surface of the bit line plug <NUM> is in contact with and connected to the source electrode <NUM>, and a top surface of the bit line plug <NUM> is electrically connected to the bit line <NUM>.

Specifically, the bit line plug <NUM> has one end electrically connected to the source electrode <NUM> and another end electrically connected to the bit line <NUM>. The bit line <NUM> extends along the first direction D1, and the plurality of bit lines <NUM> are arranged at intervals along the second direction D2. Each of the bit lines <NUM> is electrically connected, through the bit line plug <NUM>, to the plurality of source electrodes <NUM> arranged at intervals along the first direction D1. A material of the bit line plug <NUM> may be the same as a material of the bit line <NUM>, for example, the material is tungsten or molybdenum.

The specific implementation further provides a method of forming a semiconductor structure. <FIG> is a flowchart of a method of forming a semiconductor structure according to a specific implementation of the present disclosure. <FIG> are schematic structural diagrams of main processes for forming a semiconductor structure according to a specific implementation of the present disclosure. For the schematic diagram of a semiconductor structure formed in the specific implementation, refer to <FIG>. As shown in <FIG>, the method of forming a semiconductor structure includes the following steps:
Step S21: Provide an initial substrate <NUM>, as shown in <FIG>.

Specifically, the initial substrate <NUM> may be, but is not limited to, a silicon substrate. This specific implementation is described by using an example in which the initial substrate <NUM> is the silicon substrate. In other examples, the initial substrate <NUM> may be a semiconductor substrate such as a gallium nitride substrate, a gallium arsenide substrate, a gallium carbide substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate.

Step S22: Form, in the initial substrate <NUM>, a substrate <NUM> and a capacitive structure located on a top surface of the substrate <NUM>, where the capacitive structure includes a plurality of capacitors arranged in an array along a first direction D1 and a second direction D2, the first direction D1 and the second direction D2 are each parallel to the top surface of the substrate <NUM>, and the first direction D1 intersects with the second direction D2, as shown in <FIG> and <FIG>.

According to the invention, the step of forming, in the initial substrate <NUM>, a substrate <NUM> and a capacitive structure located on a top surface of the substrate <NUM> specifically includes:.

In some embodiments, the step of forming a plurality of semiconductor pillars <NUM> arranged in an array along the first direction D1 and the second direction D2, etching holes <NUM> each located between adjacent ones of the semiconductor pillars <NUM>, and a plurality of recesses <NUM> in communication with the plurality of etching holes <NUM> in a one-to-one manner and located below the etching holes <NUM> specifically includes:.

In some embodiments, the step of forming the recess <NUM> which is wider than the second etching groove <NUM> specifically includes:
etching the initial substrate <NUM> at the bottom of the second etching groove <NUM> by using a Bosch etching process, to form the recess <NUM>.

Specifically, the initial substrate <NUM> is etched along the third direction D3 by using a lithography process, to form a plurality of first etching grooves <NUM> that do not penetrate the initial substrate <NUM>, where each of the first etching grooves <NUM> extends along the first direction D1, and the plurality of first etching grooves <NUM> are arranged at intervals along the second direction D2. The first etching groove <NUM> has a depth of <NUM> to <NUM> along the third direction D3. Next, a material such as an oxide (such as silicon dioxide) to fill up the first etching groove <NUM>, to form the first medium layer <NUM>, as shown in <FIG>. The first medium layer <NUM> is configured to support the initial substrate <NUM>, to prevent the initial substrate <NUM> from tipping or collapsing during the process of forming the second etching groove <NUM>. After the first medium layer <NUM> is formed, the initial substrate <NUM> may be etched again along the third direction D3 by using a lithography process, to form a plurality of second etching grooves <NUM> not penetrating the initial substrate <NUM>, where each of the second etching grooves <NUM> extends along the second direction D2, and the plurality of second etching grooves <NUM> are arranged at intervals along the first direction D1. A depth of the second etching groove <NUM> along the third direction D3 may be less than that of the first etching groove <NUM>, to facilitate subsequent forming of the recess <NUM> below the second etching groove <NUM>. After the second etching groove <NUM> is formed, the initial substrate <NUM> is at the bottom of the second etching groove <NUM> is etched by using the Bosch etching process, to form the recess <NUM> that is in communication with the second etching groove <NUM> and has an inner diameter greater than that of the second etching groove <NUM>, as shown in <FIG>. The inner diameter of the recess <NUM> is greater than the inner diameter of the second etching groove <NUM>. Therefore, in the first direction D1, a width of the semiconductor pillar <NUM> between adjacent ones of the second etching grooves <NUM> is greater than a width of the semiconductor pillar <NUM> between adjacent ones of the recesses <NUM>.

In this specific implementation, the recess <NUM> is formed by using the Bosch etching process after the second etching groove <NUM> is formed, so as to simplify a forming process of the semiconductor structure. In other specific implementations, those skilled in the art can also select another etching process as needed to form the second etching groove <NUM> and the recess <NUM> connected to the second etching groove <NUM>.

In some embodiments, the step of forming, in the initial substrate <NUM>, a substrate <NUM> and a capacitive structure located on a top surface of the substrate <NUM> specifically further includes:.

Specifically, after the recess <NUM> is formed, an oxide (such as silicon dioxide) is deposited in the second etching groove <NUM> and the recess <NUM> to form a second medium layer filling up the second etching groove <NUM> and the recess <NUM>. The first medium layer <NUM> and the second medium layer jointly form the sacrificial layer <NUM>. Then, a part of the sacrificial layer <NUM> is etched back to expose the upper portion of the semiconductor pillar <NUM>, as shown in <FIG>. The exposed semiconductor pillar <NUM> may have a height of <NUM> to <NUM> along the third direction D3. Next, a support material is deposited on the top surface of the sacrificial layer <NUM> to form the support layer <NUM> covering the exposed semiconductor pillar <NUM>. After the support layer <NUM> is planarized, the first mask layer <NUM> is formed on the top surface of the support layer <NUM>, as shown in <FIG>. The support material may be, but is not limited to, a nitride material (such as silicon nitride). A material of the first mask layer <NUM> may be, but is not limited to, a hard mask material such as polysilicon. On one hand, the support layer <NUM> protects the upper portion of the semiconductor pillar <NUM>, to prevent the subsequent process of forming the capacitor from damaging the upper portion of the semiconductor pillar <NUM>. On the other hand, the support layer <NUM> is further configured to support the semiconductor pillar <NUM>, to prevent the semiconductor pillar <NUM> from tipping after the sacrificial layer <NUM> is removed subsequently.

In some embodiments, after the forming, on a top surface of the sacrificial layer <NUM>, a support layer <NUM> covering the exposed semiconductor pillar <NUM>, the method further includes the following steps:.

Specifically, the first mask layer <NUM> is patterned by using a lithography process, to form, in the first mask layer <NUM>, a plurality of first openings that penetrate the first mask layer <NUM> and expose the support layer <NUM>. The first mask layer <NUM> is patterned by using a mask in which the first etching grooves <NUM> and the second etching grooves <NUM> are formed, such that the positions of the formed plurality of first openings are aligned with the plurality of etching holes respectively. The support layer <NUM> is etched downward along the first opening, to form, in the support layer <NUM>, the second opening <NUM> exposing the sacrificial layer <NUM>. After the first mask layer <NUM> is removed, the sacrificial layer <NUM> is removed by etching along the second opening <NUM>, to obtain the structure as shown in <FIG>.

After the sacrificial layer <NUM> is removed, in-situ oxidation may be performed on the semiconductor pillar <NUM> below the support layer <NUM>. For example, the semiconductor pillar <NUM> below the support layer <NUM> is oxidized by using an in-situ steam generation method. The inner diameter of the recess <NUM> is greater than the inner diameter of the second etching groove <NUM>. Therefore, in the first direction D1, a width of the semiconductor pillar <NUM> between adjacent ones of the second etching grooves <NUM> is greater than a width of the semiconductor pillar <NUM> between adjacent ones of the recesses <NUM>. Therefore, oxidation parameters (for example, oxidation time and an oxidant dosage) can be controlled to completely oxidize the second semiconductor pillar <NUM> between adjacent ones of the recesses <NUM> and oxidize the surface of the semiconductor pillar <NUM> between adjacent ones of the etching holes <NUM>, so as to form the first substrate isolation sub-layer <NUM> covering the sidewall of the etching hole <NUM>, located between the adjacent ones of the recesses <NUM>, and covering the bottom surface of the recess <NUM>. After that, the second substrate isolation sub-layer <NUM> is deposited along the second opening <NUM>, to form the structure as shown in <FIG>. Next, back etching is performed to remove the first substrate isolation sub-layer <NUM> and the second substrate isolation sub-layer <NUM> that are located in the etching hole <NUM>, where the remaining first substrate isolation sub-layer <NUM> and second substrate isolation sub-layer <NUM> are jointly used as the substrate isolation layer <NUM>, as shown in <FIG>.

In some embodiments, the etching hole <NUM> located between the substrate isolation layer <NUM> and the support layer <NUM> is used as a capacitor hole, and a material of the initial substrate <NUM> is silicon; and the step of forming a capacitor in the etching hole <NUM> specifically includes:.

Specifically, after the first substrate isolation sub-layer <NUM> and the second substrate isolation sub-layer <NUM> in the etching hole <NUM> are removed through back etching, the first dopant ions (such as N-type ions) are implanted to the semiconductor pillar <NUM> between adjacent ones of the capacitor holes by using a plasma implantation or vapor diffusion method, to form an initial conductive pillar, to enhance the conductivity of the initial conductive pillar. Then, a metal material such as nickel is deposited on the surface of the initial conductive pillar through an atomic layer deposition process; next, the conductive pillar <NUM> made of metal silicide is formed through thermal processing, to further enhance the conductivity of the conductive pillar <NUM>. Then, the conductive layer <NUM> covering the sidewall of the conductive pillar <NUM>, the dielectric layer <NUM> covering the sidewall of the conductive layer <NUM>, and the top electrode <NUM> covering the surface of the dielectric layer <NUM> are sequentially formed, to form the capacitor including the conductive pillar <NUM>, the conductive layer <NUM>, the dielectric layer <NUM>, and the top electrode <NUM>.

To reduce the etching steps and further simplify the manufacturing process of the semiconductor structure, in some embodiments, the step of forming a conductive layer <NUM> covering a sidewall of the conductive pillar <NUM> specifically includes:
directly forming, by using a selective atomic layer deposition process, the conductive layer <NUM> covering only the sidewall of the conductive pillar <NUM>.

In some embodiments, the dielectric layer <NUM> is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer <NUM> and the top electrode each are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

Step S23: Form, in the initial substrate <NUM>, a transistor structure located above the capacitive structure, where the transistor structure includes a plurality of active pillars <NUM> and a plurality of word lines <NUM>, the active pillars <NUM> are electrically connected to the capacitors, and the word lines <NUM> extend along the second direction D2 and continuously cover the active pillars <NUM> arranged at intervals along the second direction D2, as shown in <FIG>.

In some embodiments, the step of forming, in the initial substrate <NUM>, a transistor structure located above the capacitive structure specifically includes:.

In some embodiments, the step of reducing widths of the channel region along the first direction D1 and the second direction D2 specifically includes:.

Specifically, after the protective layer <NUM> is formed, a part of the filling layer <NUM> is further etched back to form the channel region <NUM> in the active pillar <NUM>. In the back etching process, to avoid penetration of the filling layer <NUM>, a one-step etching process or a two-step etching process may be used and appropriate etching parameters (for example, a temperature or a pressure) are selected, such that a particular thickness of the first initial isolation layer can be retained. Specifically, the sidewall of the source region in the active pillar <NUM> is covered by the protective layer <NUM>, and the sidewall of the drain region is covered by the initial isolation layer. Therefore, the modification processing on the channel region <NUM> does not cause damage to the source region and the drain region. In this specific implementation, the modification processing is performed on the sidewall of the channel region <NUM>, such that there is a relatively high etch selectivity (for example, an etch selectivity greater than <NUM>) between the sidewall of the channel region <NUM> and the interior of the channel region <NUM> surrounded by the sidewall of the channel region <NUM>. In this way, the modified sidewall of the channel region <NUM> can be subsequently removed through selective etching, thereby reducing the width of the channel region <NUM> and enlarging the gap between adjacent ones of the channel regions <NUM>, to reserve a larger space for subsequent forming of the word lines <NUM>.

Because a thermal oxidation processing operation process is relatively simple, in some embodiments, the modification processing is thermal oxidation processing, and the modified layer is an oxide layer.

After the widths of the channel region <NUM> along the first direction D1 and the second direction D2 are reduced, the sidewall of the channel region is oxidized, to form the gate dielectric layer <NUM>. Then, the word line <NUM> only extending along the second direction D2 is directly formed by using the selective atomic layer deposition process. Next, a second initial isolation layer is deposited between adjacent ones of the active pillars <NUM>, to form the word line isolation layer <NUM> including the first initial isolation layer and the second initial isolation layer.

In other examples, after a word line material is deposited by using an atomic layer deposition process, the word line material is etched back, to form the word line <NUM> only extending along the second direction D2.

In some embodiments, after the forming the word lines <NUM> extending along the second direction D2 and continuously covering the plurality of channel regions that are arranged at intervals along the second direction D2, the method further includes:
implanting second dopant ions to the source region, the channel region, and the drain region, where the second dopant ions and the first dopant ions are of a same ion type.

In some embodiments, after the implanting second dopant ions to the source region, the channel region, and the drain region, the method further includes the following step:
depositing a metal material on a surface of the source region to form a source electrode <NUM> whose material includes a silicide, as shown in <FIG>.

Step S24: Form a bit line structure above the transistor structure, where the bit line structure includes a plurality of bit lines <NUM>, and the bit line <NUM> extends along the first direction D1 and are electrically connected to the active pillars <NUM> arranged at intervals along the first direction D1, as shown in <FIG>.

In some embodiments, the step of forming a bit line structure above the transistor structure specifically includes:.

In the semiconductor structure and the forming method thereof provided by some embodiments of the specific implementation, the transistor structure is arranged above the capacitive structure, and the bit line structure is arranged above the transistor structure, to form a semiconductor structure having a TOC structure. It is unnecessary to form a bit line structure below the transistor structure through a deep hole etching process, thereby reducing the manufacturing difficulty of bit lines, and reducing the manufacturing cost of the semiconductor structure. Moreover, because the bit line structure is located above the transistor structure, the bit line may be manufactured using various materials (such as a metal material), which helps reduce the resistance of the bit line and improve the performance of the semiconductor structure, such that the bit line is more compatible with a subsequent peripheral circuit process.

Claim 1:
A method of forming a semiconductor structure, characterized by comprising:
providing an initial substrate (<NUM>) (S21);
forming, in the initial substrate (<NUM>), a substrate (<NUM>) and a capacitive structure located on a top surface of the substrate (<NUM>), wherein the capacitive structure comprises a plurality of capacitors arranged in an array along a first direction (D1) and a second direction (D2), the first direction (D1) and the second direction (D2) are each parallel to the top surface of the substrate (<NUM>), and the first direction (D1) intersects with the second direction (D2) (S22);
forming, in the initial substrate (<NUM>), a transistor structure located above the capacitive structure, wherein the transistor structure comprises a plurality of active pillars (<NUM>) and a plurality of word lines (<NUM>), the active pillar (<NUM>) is electrically connected to the capacitor, and the word line (<NUM>) extends along the second direction (D2) and continuously cover the active pillars (<NUM>) arranged at intervals along the second direction (D2) (S23); and
forming a bit line structure above the transistor structure, wherein the bit line structure comprises a plurality of bit lines (<NUM>), and the bit line (<NUM>) extends along the first direction (D1) and are electrically connected to the active pillars (<NUM>) arranged at intervals along the first direction (D1) (S24);
wherein the forming, in the initial substrate (<NUM>), a substrate (<NUM>) and a capacitive structure located on a top surface of the substrate (<NUM>) specifically comprises:
etching the initial substrate (<NUM>), and forming a plurality of semiconductor pillars (<NUM>) arranged in an array along the first direction (D1) and the second direction (D2), etching holes (<NUM>) each located between adjacent ones of the semiconductor pillars (<NUM>), and a plurality of recesses (<NUM>) in communication with the plurality of etching holes (<NUM>) in a one-to-one manner and located below the etching holes (<NUM>);
forming a substrate isolation layer (<NUM>) connecting adjacent ones of the recesses (<NUM>) and filling up the recesses (<NUM>), and using the remaining initial substrate (<NUM>) below the substrate isolation layer (<NUM>) as the substrate (<NUM>); and
forming a capacitor in the etching hole (<NUM>).