Patent Description:
Numerous embodiments for performing precision tuning of a page or word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits and programming sequences used during the precision tuning process are also disclosed.

<CIT> discloses an artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

<CIT> discloses that the present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

<CIT> discloses that a non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

<CIT> discloses a synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes the artificial neural network adaptive to inputs and capable of learning. Typically, artificial neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical artificial neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.

Examples of different non-volatile memory cells that can be used in VMMs will now be discussed.

Various types of known non-volatile memory cells can be used in the VMM arrays. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the drain region <NUM> towards the source region <NUM> (source line terminal). The electrons will accelerate and become energized (heated) when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM> in the channel region next to the drain region <NUM>, and erasing is performed using by Fowler-Nordheim electron tunneling from floating gate <NUM> to substrate <NUM>. The read operations operate in a similar manner to that described previously for memory cell <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

<FIG> depicts twin split-gate memory cell <NUM>. Memory cell <NUM> comprises floating gate (FG) <NUM> disposed over and insulated from the substrate <NUM>, a control gate <NUM> (CG) disposed over and insulated from the floating gate <NUM>, an erase gate <NUM> (EG) disposed adjacent to and insulated from the floating and control gates <NUM>/<NUM> and disposed over and insulated from the substrate <NUM>, where the erase gate <NUM> is created with a T shape such that a top corner of the control gate CG faces the inside corner of the T shaped erase gate to improve erase efficiency, and a drain region <NUM> (DR) in the substrate adjacent the floating gate <NUM> (with a bit line contact <NUM> (BL) connected to the drain diffusion regions <NUM> (DR)). The memory cells are formed as pairs of memory cells (A on the left and B on the right), sharing a common erase gate <NUM>. This cell design differs from that the memory cells discussed above with reference to <FIG> at least in that it lacks a source region under the erase gate EG, lacks a select gate (also referred to as a word line), and lacks a channel region for each memory cell. Instead, a single continuous channel region <NUM> extends under both memory cells (i.e. extends from the drain region 16A of one memory cell to the drain region 16B of the other memory cell). To read or program one memory cell, the control gate <NUM> of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate <NUM> there between (e.g. to read or program cell A, the voltage on FGB 20B is raised via voltage coupling from CGB 28B to turn on the channel region portion under FGB 20B). Erasing is performed using Fowler Nordheim electron tunneling from floating gate <NUM> to erase gate <NUM>. Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM>. Alternatively programming is performed using Fowler Nordheim electron tunneling from erase gate <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM>. Alternatively programming is performed using Fowler Nordheim electron tunneling from channel <NUM> to floating gate <NUM>, in this case the condition is similar to PROGRAM <NUM> except the substrate <NUM> is biased at a low voltage or negative voltage while erase gate <NUM> is biased at a low positive voltage.

Table No. <NUM> depicts typical voltage ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations. In this Table, it is assumed that cell A (with terminals EG, CGA, and BLA) is selected for a read, program, or erase operation in each row.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, 3D flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and other volatile synapse cells, without limitation.

SO is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer SO to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of a system that can be used for that purpose. VMM system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> comprises VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation. Weights of a filter (kernel) are mapped across one or multiple bitlines (columns) or one or multiple rows across single or multiple VMM arrays <NUM>.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital timing pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level (e.g., current, voltage, or charge), binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

As described herein for neural networks, the non-volatile memory cells of VMM array <NUM> are preferably configured to operate in a sub-threshold region.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT> where <MAT> where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is the (effective or equivalent) threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT> Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely <MAT> <MAT> <MAT> Here, wa = W of each memory cell in the memory array. Vthp is the (equivalent or effective) threshold voltage of reference memory cell (or peripheral memory cell or transistor) and Vtha is the (equivalent or effective) threshold voltage of the array memory cell.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> <MAT> meaning weight W in the linear region is proportional to (Vgs-Vth).

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> Wα (Vgs-Vth)<NUM>, meaning weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.

The target reference levels are provided by a reference mini-array matrix (not shown) or from a bandgap based reference circuit.

Here, the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BLO - BLN during a read (inference) operation. The current placed on each of the bit lines BLO - BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.

Second, memory array <NUM> effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to the control gates (CGO, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BLO - BLN, and will be the input to the next layer or input to the final layer.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

VMM array <NUM> is similar to VMM array <NUM>, except that VMM array <NUM> implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate vertical EG lines. The current output (neuron) is in the bitlines BLO - BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bitline.

The input to the VMM arrays can be an analog level, a binary level, timing pulses, or digital bits and the output can be an analog level, a binary level, timing pulses, or digital bits (in this case an output ADC is needed to convert output analog level current or voltage into digital bits).

For each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> or more cells). In the differential cell case, two memory cells are needed to implement a weight w as a differential weight (w = w+ - w-). In the two blend memory cells, two memory cells are needed to implement a weight w as an average of two cells.

It imperative to accurately and precisely program and erase non-volatile memory cells to ensure that the correct amount of charged is placed on the floating gates to store the correct weight in the cell.

What is needed is a VMM system that allows for precise tuning on a word or page basis, where a word typically comprises <NUM>-<NUM> memory cells each storing multiple logical bits (i.e., multi-level cells, each storing, for example, <NUM>-<NUM> bits) and a page comprises <NUM> memory cells each storing multiple logical bits. What is further needed are high voltage circuits to generate the required voltages. What is further needed are improved programming sequences to minimize the occurrence of undesired effects such as erase gate disturb and control gate disturb.

Programming sequences of a word of non-volatile memory cells in an array of non-volatile memory cells for the application of the voltages to the terminals of the non-volatile memory cells to minimize the occurrence of disturbances during precision tuning are disclosed.

The present invention is defined by a method of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a control gate terminal, a source line terminal and an erase gate terminal, the method comprises ramping up a voltage on the control gate terminals of the word of non-volatile memory cells to an intermediate voltage during a first time period; ramping up a voltage on the source line terminals of the word of non-volatile memory cells during a second time period after the first time period; ramping up a voltage on the erase gate line terminals of the word of non-volatile memory cells during a third time period after the second time period; and further ramping up the voltage on the control gate terminals of the word of non-volatile memory cells during a fourth time period after the third time period.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements bi-directional tuning for a page of non-volatile memory cells. Here, exemplary page <NUM> comprises two words, each in a different row. A word includes a plurality of memory cells, e.g. <NUM>-<NUM>. A special word may include just one cell or a few cells. Pairs of adjacent rows share a source line, such as SL0 or SL1. All cells in page <NUM> share a common erase gate line that is controlled by erase gate enable transistor <NUM>, which controls the provision of a voltage to the erase gate terminals EGW of all cells in exemplary page set <NUM>. Here, all cells in page <NUM> can be erased at the same time. Thereafter, cells in page <NUM> can be bi-directionally tuned through program and erase operations and some cells in page <NUM> can be uni-directionally tuned through program operation. The program operations can include the precision programming techniques described below with reference to <FIG> and <FIG>. If too much electron charge is placed on a floating gate (which would cause an incorrect current value to be stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements bi-directional tuning for a word of non-volatile memory cells. Here, exemplary word <NUM> comprises a plurality of cells in a row. All cells in word <NUM> share a common erase gate line that is controlled by erase gate enable transistor <NUM>, which controls the provision of a voltage to the erase gate terminals of all cells in word <NUM>. Here, all cells in word <NUM> can be erased at the same time. Thereafter, cells in word <NUM> can be bi-directionally tuned through program and erase operations. The program operations can include the precision programming techniques described below. If too much electron charge is placed on a floating gate (such that an incorrect current value is stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements bi-directional tuning for a word of non-volatile memory cells. Here, exemplary word <NUM> comprises two half words of cells. Each half word belongs to a row that shares an erase gate. All cells in word <NUM> share a common erase gate line connected to erase gate terminal EGW. Unlike in VMM array <NUM> and <NUM>, there is no erase gate enable transistor. Here, all cells in word <NUM> can be erased at the same time. Thereafter, cells in word <NUM> can be bi-directionally tuned through program and erase operations. The program operations can include the precision programming techniques described below. If too much electron charge is placed on a floating gate (such that an incorrect current value is stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

Although not shown in <FIG>, <FIG>, and <FIG>, source line pulldown bitlines, tuning bitlines (used for ultra fine programming), dummy bitlines, and redundant bitlines can be used, as described in <CIT>, and titled, "Ultra-Precise Tuning of Analog Neural Memory Cells In A Deep Learning Artificial Neural Network".

<FIG> depicts tuning page/word algorithm <NUM>, which can be applied to VMM arrays <NUM>, <NUM>, or <NUM> in <FIG>.

First, the word or page is erased (step <NUM>). Second, deep programming is performed on the un-used cells (step <NUM>). Deep programming is used to program the cells into a state (or target level) that has insignificant cell current during a read operation, for example <pA range. Third, coarse programming is performed on the cells within the word or page (step <NUM>). Coarse programming is used to program the cells into a coarse target level, for example within <NUM>-<NUM>% of the target with large (coarse) increment voltage and/or program current and/or program timing. Fourth, fine programming is performed on the cells within the word or page (step <NUM>). Fine programming is used to program the cells into a fine target level, for example within +/- <NUM>-<NUM>% of the target with small (fine) increment program voltage and/or program current and/or program timing. Fifth, ultrafine programming optionally is performed on the cells within the word or page (step <NUM>). Ultrafine programming is used to program the cells into final target level with precise very small increment voltage and/or program current and/or program timing. The percentage achieved within the final target level in coarse/fine/ultrafine programming is traded off versus the magnitude of the increment level and/or program timing to minimize noise such as from program quantization noise (increment magnitude), disturb noise, various coupling noise, FG-FG coupling noise etc..

<FIG> depicts tuning page/word algorithm <NUM>, which can be applied to VMM arrays <NUM>, <NUM>, or <NUM> in <FIG>. Tuning page/word algorithm <NUM> is similar to tuning/page word algorithm <NUM> in <FIG>, except that tuning page/word algorithm <NUM> further includes steps for handling fast or slow bits. Steps <NUM>-<NUM> occur as in <FIG>. In step <NUM> or alternatively in step <NUM>, a determination is made whether the word or page contains any fast-bits or slow-bits (step <NUM>). A fast bit is a bit that requires a shorter period of programming to reach a desired level than a normal bit, and a slow bit is a bit that requires a longer period of programming to reach a desired level than a normal bit. The fast bit can be detected by monitoring the program rate (program speed ) of the cells such by my measuring delta Ir/ delta tprog (current change over time, for example current change over K consecutive pulses) > a pre-determined R factor, for example K=<NUM> pulses. The slow bit can be detected by monitoring the program rate delta Ir/ delta tprog < a pre-determined R factor. If no, then the algorithm stops. If yes, then the fast-bit or slow-bit cells are identified and flagged. Thereafter, any programming of that word or page will utilize fastbit or slowbit algorithms, as discussed below with reference to <FIG> and <FIG>.

Applicant previously disclosed various techniques for performing coarse programming, fine programming, and ultrafine programming in <CIT>, and titled, "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network".

<FIG> depicts fast-bit algorithm <NUM>. This is performed if a word or page has been determined to contain one or more fast-bit cells, also known as fast-bits. First, the word or page is erased or partially erased (step <NUM>). Second, the fast-bits are programmed and verified (step <NUM>). This is for example done with smaller than the default (or constant) voltage increment and/or smaller than the default program current and/or smaller than the default timing. Next the normal bits, i.e. all bits not flagged as fast-bits or slow-bits, are programmed and verified (step <NUM>). This is for example done with default setting of coarse/fine/ultrafine voltage increment and/or program current and/or timing.

<FIG> depicts slowbit algorithm <NUM>. This is performed if a word or page has been determined to contain one or more slow-bit cells. First, the word or page is erased or partially erase (step <NUM>). Second, the slow-bit cells are programmed and verified (step <NUM>). This is for example done with larger than the default voltage increment and/or larger than the default program current and/or larger than the default timing. Next the normal bits, i.e. all bits not flagged as slow-bits or fast-bits, are programmed and verified (step <NUM>). This is for example done with default setting of coarse/fine/ultrafine voltage increment and/or program current and/or timing.

In one embodiment, the slow-bit cells are tuned first to avoid disturb to other cells in the same page/word, then fast-bit cells are tuned, and then normal-bit cells are tuned.

In one embodiment, the slow-bit cells are tuned first (to avoid disturb to other cells in the same page/word), then normal-bit cells are tuned, and then fast-bit cells are tuned.

<FIG> depicts a block diagram of VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, row decoders <NUM>, high voltage decoders <NUM>, column decoders <NUM>, bit line drivers <NUM>, input circuit <NUM>, output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. VMM system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. VMM system <NUM> further comprises (program/erase, or aka weight tuning) algorithm controller <NUM>, analog circuitry <NUM>, control logic <NUM>, and test control logic <NUM>. The systems and methods described below can be implemented in VMM system <NUM>.

The input circuit <NUM> may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), AAC (analog to analog converter, such as a current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit <NUM> may implement normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit <NUM> may implement a temperature compensation function for input. The input circuit <NUM> may implement an activation function such as ReLU or sigmoid. The output circuit <NUM> may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter), APC (analog to pulse(s) converter), or any other type of converters. The output circuit <NUM> may implement an activation function such as ReLU or sigmoids. The output circuit <NUM> may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit <NUM> may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.

<FIG> depicts high voltage generation block <NUM>, which is an embodiment of high voltage generation block <NUM> from <FIG>. High voltage generation block <NUM> comprises charge pump <NUM> and charge pump regulator <NUM>, which generate a variety of high voltages and are controlled by an enable signal here labeled as EN_CP. Charge pump <NUM> and charge pump regulator <NUM> provide the requisite high voltages to control gate high voltage generator <NUM>, erase gate high voltage generator <NUM>, and source line high voltage generator <NUM>, which are controlled by enable signals labeled EN_CGGEN, EN_EGGEN, and EN_SLGEN, respectively, and which provide high voltage signals to control gate lines, erase gate lines, and source lines, respectively, as needed during program, erase, or read operations within a VMM array.

<FIG> depicts a high voltage maximum circuit, used to supply the high voltage power supply, which identifies the voltage that is highest between a first high voltage HV1 and a second high voltage HV2 and outputs the highest voltage. Comparator <NUM> receives HV1div and HV2div, which are level-shifted, divided down (i.e. low voltage) versions of HV1 and HV2, respectively. Comparator <NUM> outputs a high signal on line COMPO if HV1 is greater than HV2, and it outputs a low signal on line COMPO if HV1 is less than HV2. The output of comparator <NUM> on line COMPO is provided to high voltage level shifter <NUM> and high voltage level shifter <NUM>. If the output of comparator <NUM> is low, then high voltage level shifter <NUM> outputs a low signal on line 2402B and high voltage level shifter <NUM> outputs a low signal on line 2403A. If the output of comparator <NUM> is high, then high voltage level shifter <NUM> outputs a low signal on line 2402A and high voltage level shifter <NUM> outputs a low signal on the line 2403B. PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are configured as shown, i.e. with their gate coupled to a respective one of lines 2402A, 2402B, 2403A and 2403B. If high voltage level shifter <NUM> outputs a low signal on the line 2402B and high voltage level shifter <NUM> outputs a low signal on the line 2403A, then high voltage output <NUM> will be equivalent to HV2, less any voltage drop across PMOS transistors <NUM>, <NUM>. If high voltage level shifter <NUM> outputs a low signal on the line 2402A and high voltage level shifter <NUM> outputs a low signal on the line 2403B, then high voltage output <NUM> will be equivalent to HV1, less any voltage drop across PMOS transistors <NUM>, <NUM>.

<FIG> depicts high voltage generation block <NUM>, which is another embodiment of high voltage generation block <NUM>. Here, high voltage generation block <NUM> comprises charge pump and regulator <NUM> enabled by signal EN_CP, high voltage increment reference generator <NUM>, and high voltage buffer operational amplifier <NUM>. The voltage of the output of charge pump regulator <NUM> can be controlled based on the signals sent to the gates of the MOS transistors in high voltage increment reference generator <NUM>, by trimming the portion of the output voltage HVSUP output by charge pump <NUM> fed to the input of high voltage op-amp HVOPA.

<FIG> depicts high voltage generator block <NUM>, which is another embodiment of high voltage generation block <NUM>. High voltage generation block <NUM> receives input VIN (a low voltage signal) and generates output HV Output (a high voltage signal), and comprises operational amplifier <NUM>, variable resistor <NUM>, and variable resistor <NUM>, where the gain (of operational amplifier <NUM> is dependent on the values of variable resistor <NUM> and/or variable resistor <NUM>. The high voltage increment value is hence controlled by the value of the variable resistor <NUM> and/or resistor <NUM>.

<FIG> depicts ramp down control circuit <NUM>, which comprises clamp PMOS transistor <NUM>, enabling NMOS transistor <NUM>, and current bias NMOS transistor <NUM>, configured as shown. Ramp down circuit <NUM> receives voltage HV to be ramped down at the source of PMOS transistor <NUM> and generates output signal VHV_DET at the drain of PMOS transistor <NUM>, which will have a peak value of HV and will ramp down toward ground in response to signal ENRMP, fed to the gate of enabling NMOS transistor <NUM>, changing from low to high. Output signal VHV_DET will be ramped down from HV value to Vcas+Vt PH value by a current controlled by the current bias NMOS transistor <NUM> when ENRMP equals to high.

<FIG> shows another ramp down control circuit <NUM>, which comprises cascoding NMOS transistor <NUM>, shunt NMOS transistor <NUM> (provide ramp current), enabling NMOS transistor <NUM>, current source <NUM>, and capacitor <NUM>. The HV node ramp down rate is controlled by I/C (=I or reference current source <NUM>/ capacitance of capacitor <NUM>).

<FIG> depicts ramp up circuit <NUM>, which comprises NMOS cascoding transistor <NUM>, enabling NMOS transistor <NUM>, current shunt NMOS transistor <NUM>, current source <NUM>, and capacitor <NUM>, configured as shown. Ramp up circuit <NUM> controls the ramping rate of the HV node by the ratio of I/C (= I reference current source <NUM>/capacitance of capacitor <NUM>) by shunting the current through the NMOS transistor <NUM>. The ramp rate on the HV node is such that the current injected through the capacitor <NUM> is equal to the current source <NUM>.

<FIG> depict VMM high voltage decode circuits, comprising word line decoder circuit <NUM>, source line decoder circuit <NUM>, and high voltage level shifter <NUM>, which are appropriate for use with memory cells of the type shown in <FIG>.

In <FIG>, word line decoder circuit <NUM> comprises PMOS select transistor <NUM> (controlled by signal HVO_B) and NMOS de-select transistor <NUM> (controlled by signal HVO_B) configured as shown. HVSUP is high voltage supply such as supplied from a charge-pump and regulator. WLSUP provides voltage supply for wordline WL when HVO_B is enabled.

In <FIG>, source line decoder circuit <NUM> comprises NMOS monitor transistors <NUM> (controlled by signal HVO), driving transistor <NUM> (controlled by signal HVO), and de-select transistor <NUM> (controlled by signal HVO_B), configured as shown. When signal HVO is high, the voltage appearing on line SLSUP is passed through to line SL, and appears on monitoring line SL_MON. When signal HVO_B is high, line SL is pulled down.

In <FIG>, high voltage level shifter <NUM> receives enable signal EN and outputs high voltage signal HVO and its complement HVO_B between HVSUP, e.g., 12V, and HVSUP_LOW supply, e.g., 0V (when HVSUP is for example equal to an intermediate level ~5V) or <NUM>. 5V (when HVSUP is for example 12V). For example HVO can be 5V and HVO_B can be 0V, or HVO can be 12V and HVO_B can be <NUM>.

<FIG> depict VMM high voltage decode circuits, comprising erase gate decoder circuit <NUM>, control gate decoder circuit <NUM>, source line decoder circuit <NUM>, and high voltage level shifter <NUM>, which are appropriate for use with memory cells of the type shown in <FIG>.

In <FIG>, erase gate decoder circuit <NUM> and control gate decoder circuit <NUM> use the same design as word line decoder circuit <NUM> in <FIG>.

In <FIG>, source line decoder circuit <NUM> uses the same design as source line decoder circuit <NUM> in <FIG>.

In <FIG>, high voltage level shifter <NUM> uses the same design as high voltage level shifter <NUM> in <FIG>.

<FIG> depict programming sequences of voltages applied to a control gate terminal, source line terminal, and erase gate terminal of one or more non-volatile memory cells during a program operation.

<FIG> depicts program sequence <NUM>, where the control gate voltage CG ramps up during a first period, then the source line voltage SL ramps up during a second period, and then the erase gate voltage EG ramps up during a third period. All three voltages plateau at their peak values during a fourth period, and then the ramping sequence is reversed, erase gate voltage EG ramps down during a fifth period, source line voltage SL ramps down during a sixth period, and control gate voltage CG ramps down during a seventh period. Program sequence <NUM> minimizes erase gate disturb occurrences.

<FIG> depicts program sequence <NUM>, where the control gate voltage CG ramps up during a first period to an intermediate value, then the source line voltage SL ramps up during a second period to its peak value, and then the erase gate voltage EG ramps up to a third period to its peak value, and then the control gate voltage CG ramps up during a fourth period to its peak value. All three voltages plateau at their peak values during a fifth period, and then control gate voltage CG ramps down during a sixth period to an intermediate value, erase gate voltage EG ramps down during a seventh period, source line voltage SL ramps down during an eighth period, and control gate voltage CG then ramps down to ground during a ninth period.

<FIG> depicts program sequence <NUM>, where first the control gate voltage CG ramps up to a first intermediate value during a first period and then during a second period the source line voltage SL ramps up to a second intermediate value. Then, during a third period, the control gate voltage CG ramps up to a third intermediate value while the source line voltage SL ramps up to its peak voltage and the erase gate voltage EG ramps to its peak voltage. Finally, during a fourth period, the control gate voltage CG ramps up to its peak voltage. Then all three voltages plateau at their peak values during a fifth period. Then during a sixth period the control gate voltage CG ramps down to the third intermediate value, then during a seventh period the source line voltage SL ramps down to the second intermediate value, then during an eighth period the control gate voltage CG ramps down to the first intermediate value, then during a ninth period the erase gate voltage EG ramps down to ground, then during a tenth period the source line voltage SL ramps down to ground, and then during an eleventh period the control gate voltage CG ramps down to ground.

<FIG> depicts program sequence <NUM>, where the source line voltage SL ramps up during a first period to a peak value, and then during a second period the control gate line voltage CG ramps up to its peak value while the erase gate voltage EG ramps up to its peak value. Then during a third period all three voltages plateau at their peak values. Then the control gate line voltage CG ramps down during a fourth period while the erase gate voltage EG ramps down, and then during a fifth period the source line voltage SL ramps down. Program sequence <NUM> minimizes control gate disturb occurrences.

<FIG> depicts erase sequence <NUM>, where the inhibit control gate or inhibit source line (CG-inh or SL-inh, to be applies to unselected cells during an operation) ramps up during a first period, and then erase gate voltage EG ramps up during a second period. Then all voltage plateau at their peak values during a third period. Then the erase gate voltage EG ramp down during a fourth period, and then the inhibit control gate or inhibit source line (CG-inh or SL-inh) ramps down during a fifth period. This sequence is for example suitable for arrays that are suitable for bi-directional tuning such as <FIG>, <FIG>, <FIG>, <FIG>.

<FIG> depict a high voltage decoder <NUM> that utilizes the decoding sub circuit blocks <NUM> (EG dec), <NUM> (CG dec), <NUM> (SL dec) in <FIG>. Different arrangement of sub circuit blocks are done as shown to optimize for different configurations and optimizations.

<FIG> shows circuit decoder block <NUM> that comprises circuit decoder block <NUM>. The circuit decoder block <NUM> includes EG dec that provides one EG decoding signal, CG dec that provides two CG decoding signals, and SL dec that provides one SL decoding signal.

<FIG> shows circuit decoder block <NUM> that comprises circuit decoder block <NUM>. The circuit decoder block <NUM> includes EG dec that provides one EG decoding signal, CG dec that provides four CG decoding signals, and SL dec that provides one SL decoding signal.

<FIG> shows circuit decoder block <NUM> that comprises circuit decoder block <NUM>. The circuit decoder block <NUM> t includes EG dec that provides two EG decoding signals, CG dec that provides eight CG decoding signals, and SL dec that provides one SL decoding signal.

<FIG> depicts high voltage latch circuit <NUM>. High voltage latch circuit <NUM> comprises a cross coupled high voltage transistor inverter formed by PMOS transistors <NUM> and <NUM> and NMOS transistors <NUM> and <NUM> and enabling transistors <NUM> and <NUM>. The enabling signals ENB <NUM> and EN <NUM> are logic signals (e.g., 0V/Vdd) when VHVSUP <NUM> is at an intermediate voltage (e.g. ~<NUM>-5V) and are at another intermediate voltage (e.g., both signals EN <NUM> = ENB <NUM> = Vdd = <NUM>. 8V) when VHVSUP <NUM> is at voltage greater than an intermediate HV voltage (e.g., > 5V) and when VHVSUP_LOW <NUM> is at an intermediate level such as <NUM>. Output HVOUT <NUM> and complementary signal HVOUTB <NUM> are generated.

Claim 1:
A method (<NUM>, <NUM>) of programming a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns and forming an analog neural memory, each non-volatile memory cell comprising a control gate terminal, a source line terminal, and an erase gate terminal, the method comprising:
ramping up a voltage on the control gate terminals of the word of non-volatile memory cells during a first time period;
ramping up a voltage on the source line terminals of the word of non-volatile memory cells during a second time period after the first time period; and
ramping up a voltage on the erase gate line terminals of the word of non-volatile memory cells during a third time period after the second time period; and
further ramping up the voltage on the control gate terminals of the word of non-volatile memory cells during a fourth time period after the third time period.