Patent Description:
The present invention relates generally to quantum and classical digital superconducting circuits, and specifically to inverting phase-mode logic (PML) D flip-flops.

In the field of digital logic, extensive use is made of well known and highly developed complimentary metal-oxide semiconductor (CMOS) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions (JJs), with typical signal power of around <NUM> nanowatts (nW), at a typical data rate of <NUM> gigabits per second (Gb/s) or greater, and operating temperatures of around <NUM> kelvins.

A flip-flop is a bistable multivibrator, a two-stable-state circuit that can therefore be used to store state information and to change state by signals applied to one or more control inputs. In modern computing and communications electronics, flip-flops are the basic storage element in sequential logic. An inverting flip-flop is one that delivers the inverse logic state that would otherwise be expected from a noninverting flip-flop, i.e., the output is an inverted version of the clocked input. A conventional inverting D flip-flop, e.g., one implemented in CMOS, has two binary inputs, a data input D and a clock input, and at least one output, Q. The D flip-flop captures the value of the D input at a definite portion of an input clock cycle, e.g., a rising edge or a falling edge, known as the capture time. That captured value is inverted to become the Q output. The output Q does not change except at the capture time (or some small propagation delay thereafter). In practical implementations it is required that a data input D be stable for some setup time prior to the capture time and for some hold time after the capture time for the input to be reliably captured, inverted, and propagated to the output.

Phase-mode logic allows digital values to be encoded as superconducting phases of one or more Josephson junctions. For example, a logical "<NUM>" may be encoded as a high phase and a logical "<NUM>" may be encoded as a low phase. For example, the values may be encoded as a superconducting phase of zero radians (meaning, e.g., logical "<NUM>") or as a superconducting phase of 2π radians (meaning, e.g., logical "<NUM>"). These values persist across RQL AC clock cycles because there is no requirement for a reciprocal pulse to reset the Josephson junction phase each AC clock cycle. <CIT> proposes a reciprocal quantum logic (RQL) latch system.

The invention is defined as set forth in independent apparatus claim <NUM> and corresponding independent method claim <NUM>.

This disclosure relates generally to quantum and classical digital superconducting circuits, and specifically to an inverting D flip-flop for use in reciprocal quantum logic (RQL) phase-mode logic (PML) circuits. The RQL phase-mode inverting flip-flop can be implemented, for example, in a memory system (e.g., a quantum computing memory system) to store a logic state of an addressed memory cell. This disclosure provides an inverting version of the PML flip-flop described in <CIT>, entitled "RQL Phase-Mode Flip-Flop, that is more efficient than simply attaching an inverter to the output of that flip-flop. The inputs and the output can each be provided via a Josephson transmission line (JTL), such as in an RQL superconducting circuit.

An inverting RQL phase-mode flip-flop can include a stacked Josephson junction and a comparator. For example, such a flip-flop can include a stacked Josephson junction in series with an output Josephson junction that forms part of the comparator. As used herein, "stacked Josephson junction" means a Josephson junction that is between another Josephson junction and its bias source such that the two junctions are biased in series and the triggering of one junction can change the DC bias of the other. An output of the flip-flop can be connected, for example, to an output amplifying Josephson transmission line (JTL) so as to propagate the output signal to other gates in the RQL system or other parts of the RQL circuit. A data input, which can be provided as a positive or negative single flux quantum (SFQ) pulse, can trigger or untriggers the stacked Josephson junction to change a bias condition in the flip-flop, e.g., to reverse a DC bias applied to the output Josephson junction, thereby priming the output Josephson junction to pass pulses from a logical clock input signal to the output, or to suppress such pulses, based, for example, on the direction of the DC biasing. In this manner, an inverted version of the data input can be captured to the output upon the receipt of a logical clock SFQ reciprocal pulse pair to the comparator, when, for example, one of the pulses in the pair can cause the output Josephson junction to preferentially trigger over an escape Josephson junction in the comparator, owing to the output Josephson junction having been appropriately biased by the triggering of the stacked Josephson junction.

<FIG> is a block diagram of an example inverting RQL phase-mode flip-flop <NUM> having data input D, logical clock input LCLK, and output Q. One or more bias network(s) can provide DC and AC bias, or DC (only) bias to the flip-flop. The flip-flop <NUM> includes a stacked Josephson junction <NUM> and a comparator <NUM>. Stacked Josephson junction <NUM> can be configured to receive a data input signal on a data input line D as a positive or a negative SFQ pulse, and to reverse a DC bias current flowing in the flip-flop based on the data input signal. Comparator <NUM> can be configured to receive a logical clock input signal provided on logical clock input line LCLK and to either transmit the logical clock input signal on an output line as an output signal of the flip-flop, the output signal being a logical inversion of the data input signal, or to suppress such transmission, based on the direction of the DC bias and a logical output state of the flip-flop. The D and LCLK inputs and Q output follow the traditional inverting flip-flop nomenclature, with logical clock input LCLK being the equivalent of clock CLK in a CMOS flip-flop. Logical clock input LCLK can provide an SFQ signal, e.g., as positive-negative reciprocal pulse pairs, and should not be confused with an RQL AC clock.

<FIG> is a block diagram of another example inverting RQL phase-mode flip-flop <NUM>, similar to flip-flop <NUM> shown in <FIG>. Flip-flop <NUM> likewise has data and logical clock inputs D and LCLK, and output Q, as well as one or more bias network(s), as described above. Flip-flop <NUM> also includes a stacked Josephson junction <NUM>, which can function as described above, and a comparator <NUM>, which can be made of either an escape Josephson junction <NUM> or a small dissipating resistor <NUM>, and an output Josephson junction <NUM>. As shown, the logical clock signal can be provided through the escape Josephson junction <NUM> or dissipating resistor <NUM>, and output Josephson junction <NUM> is connected to the flip-flop's output. Comparator <NUM> can be configured such that only one of the escape Josephson junction <NUM> or the output Josephson junction <NUM> triggers in response to an SFQ pulse received at logical clock input LCLK. In particular, comparator <NUM> can be configured such that output Josephson junction <NUM> preferentially triggers to generate the output signal based on a negative bias condition of output Josephson junction <NUM> resulting from a triggering of stacked Josephson junction <NUM>, reversing the DC bias current in response to the data input signal supplied at data input D. Inverting flip-flop <NUM> combines the use of the stacked Josephson junction <NUM> to reverse the direction of DC bias to output Josephson junction <NUM> with the comparator <NUM> to provide an inverted flip-flop <NUM>.

For example, SFQ pulses arriving at input D can consist of alternating positive and negative SFQ pulses consistent with RQL phase-mode data encoding. Flip-flops <NUM> and <NUM> can each be configured, e.g., by a circuit initialization, such that if a negative data input pulse is received at data input D, on the next logical clock input signal received at logical clock input LCLK, output Q is asserted to its logical "<NUM>" value; and, by contrast, is a positive data input pulse is received at data input D, on the next logical clock input signal received at logical clock input LCLK, output Q is de-asserted to its logical "<NUM>" value. In such an example, any other combination of signals will have no effect on the logical state of output Q. Thus, for example, any pulses received at logical clock input LCLK, whether positive or negative, will not change the logical state of output Q absent a data input pulse received at input D that is different in polarity from the last received data input pulse. The aforementioned initialization can comprise provision of a reciprocal pulse pair to logical clock input LCLK.

Owing to their respective configurations, both omitting any kind of second signal-inversion stage, flip-flops <NUM> and <NUM> can be made very efficient in terms of component count and very fast in terms of output propagation speed. As examples, these flip-flops can be made with only three or four Josephson junctions, and can provide an output within one AC cycle as supplied by bias network(s). In some examples, the inverting flip-flops described herein involve less than ten picoseconds of delay from the application of a pulse at a logical clock input LCLK to a new output being generated, with it taking only a little over half an AC cycle to fully evaluate a new output when a reciprocal pair applied at LCLK to evaluate all possible transitions are about one half of an AC cycle apart.

The logic value of flip-flops <NUM> or <NUM> can be stored, for example, as the superconducting phase of a Josephson junction. For example, the logic value of flip-flop <NUM> can be stored as the phase of output Josephson junction <NUM>. As an example, a <NUM> radian superconducting phase of output Josephson junction <NUM> can encode a logic "<NUM>" value and a 2π radian superconducting phase of output Josephson junction <NUM> can encode a logic "<NUM>" value, but other combinations can work equally well depending on the surrounding logic.

<FIG> is a circuit schematic of an example RQL phase-mode inverting D flip-flop circuit <NUM> that can correspond to either of flip-flops <NUM> or <NUM>. Flip-flop <NUM> has two logical inputs DI, LCLKI and one output QNO, each configured to receive or transmit SFQ pulses as inputs or outputs. A data signal consisting of positive and negative SFQ pulses can be provided on data input DI via data input inductor L6b, while a logical clock signal consisting of reciprocal SFQ pulse pairs can be provided on logical clock input LCLKI via logical clock input inductor L6a.

An AC and DC bias, labeled bias_1, can be provided to the circuit via AC and DC bias inductor L2. A DC bias can also be applied via a transformer coupling grounded inductor L8. As an example, AC and DC bias bias_1 can provide Φ<NUM>/<NUM> worth of direct current plus an AC waveform signal (e.g., a sinusoidal signal), while the DC bias provided through inductor L8 can provide Φ<NUM>/<NUM> worth of direct current. As used herein, Φ<NUM> is one single flux quantum, equal to approximately <NUM> mA-pH. When a reciprocal pulse pair is applied at logical clock input LCLKI, the output QNO takes on the inverted value of the data input signal most recently applied at data input DI. Flip-flop <NUM> can include four Josephson junctions J2, J3, J4, J5, and five inductors L2, L6a, L6b, L7, L8, the latter of which is a transformer-coupled inductor. Alternate examples, described herein, can include one fewer inductor (eliminating inductor L8) and/or can eliminate one Josephson junction by including a resistor.

Inverting D flip-flop <NUM> is a "phase-mode" flip-flop inasmuch as the logic value of flip-flop <NUM> is stored as the superconducting phase of output Josephson junction J4, either <NUM> or 2π radians, where Josephson junction superconducting phase is defined as the time integral of voltage at every node. In accordance with flip-flop <NUM> being a "phase-mode" flip-flop, for any single reciprocal pulse pair provided to logical clock LCLKI, at most only a single pulse will be observed at inverting output QNO. To improve the operating margins of circuit <NUM>, data input Josephson junction J2, along with data input inductor L6b and inductor L7, provides some isolation between the JTL (not shown) driving the data input DI and the remainder of circuit <NUM> (as illustrated) that performs the logic operation. As such, in some examples, data input inductor L6bdata input Josephson junction J2, and inductor L7 can be considered as not a part of circuit <NUM> but rather as a part of the aforementioned data input driving JTL. D flip-flop <NUM> is therefore highly efficient in terms of its use of devices, requiring only three or four Josephson junctions and only three to five inductors, apart from any devices used for race condition avoidance phasing of input signals, and notably without requiring a separate dedicated signal inversion circuit stage.

As discussed below with regard to <FIG> and <FIG>, the DC transformer and its associated grounded inductor L8 can be omitted in some implementations, provided that the DC and AC mix provided by DC and AC bias bias_1 can be appropriately adjusted. Typical RQL circuits are designed with DC and AC bias lines that provide a certain DC and AC bias mix via transformer coupling to a grounded bias inductor, and because flip-flop <NUM> uses a different mix than ordinarily found in RQL circuits, DC bias transformer including inductor L8 can be advantageously included to provide a different mix while still making use of the more readily available bias from DC and AC bias source bias_1.

Although a more detailed description of the circuit's functioning is given below, a summary of the functioning of inverting flip-flop <NUM> is as follows. As can be seen, for example, in <FIG>, the triggering of stacked Josephson junction J3 in flip-flop <NUM> drives one Φ0 worth of current in all directions, including up into the two bias networks, i.e., through inductors L2 and L8, and the return path for this current is up from ground through output Josephson junction J4. Thus, for example, if DC and AC bias bias_1 and DC bias inductor L8 together provide Φ<NUM>/<NUM> of positive DC bias current flowing down into circuit <NUM> through inductor L2 and Josephson junctions J3 and J4 to ground at the bottom of the circuit, the triggering of Josephson junction J3, putting Φ<NUM> of current flowing in the opposite direction reverses that whole loop, such that -Φ<NUM>/<NUM> worth of bias current is seen by output Josephson junction J4.

Escape Josephson junction J5 and output Josephson junction J4 in circuit <NUM> together form a comparator, and depending on the direction of the DC bias through output Josephson junction J4, when a reciprocal pulse pair is introduced on logical clock input LCLKI, escape Josephson junction J5 either rejects the positive one of the logical clock pulses and allows the negative pulse to be passed through to the output QNO, or vice versa, with the caveat that the pulse is only passed to the output QNO provided that the output QNO is not already in the state implied by such pulse. In the case that the output QNO is already in the state that would be suggested by the passed pulse, escape Josephson junction J5 rejects both pulses of the logical clock reciprocal pulse pair. Because Josephson junction J3 is stacked with output Josephson junction J4 and triggers to reverse the bias current seen by output Josephson junction J4, the data input DI effectively applies an opposite bias to output Josephson junction J4, such that a positive pulse applied to data input DI triggers stacked Josephson junction J3 positively, and biases output Josephson junction J4 negatively. Thus, a positive input at DI allows a negative pulse to transition from logical clock input LCLKI to output QNO.

The default state of circuit <NUM> with respect to the DC biases provided from bias_1 and transformer-coupled inductor L8, as shown in <FIG>, is such that DC bias currents are provided in the positive direction, flowing from source bias_1 down through inductor L2, stacked Josephson junction J3, and output Josephson junction J4. In the circuit's default state shown in <FIG> and prior to a circuit initialization described below, circuit <NUM> is in "phase mode zero": as shown in <FIG>, all of the Josephson junctions attached to output QNO (J3, J4, J5) have no dot on the output side, and the phase of the output QNO is at <NUM> radians.

<FIG> illustrate the functioning of circuit <NUM> starting from the default biasing state of <FIG>. In these illustrations, a dot placed next to a Josephson junction indicates that that Josephson junction has been triggered, and the side on which said dot is placed indicates the direction of triggering. In the convention used in these illustrations, dots placed at both sides of a Josephson junction indicate successive triggering and untriggering of the Josephson junction (i.e., triggering in one direction followed by triggering in the opposite direction), which is equivalent to no dots.

Operation of flip-flop circuit <NUM> can include an initial reciprocal pulse pair at logical clock input LCLKI to initialize the circuit. This initializing pulse pair can consist, for example, of a positive SFQ pulse followed by a negative SFQ pulse, as illustrated in <FIG>, but the circuit functions equivalently if the pulse pair consists of a negative SFQ pulse followed by a positive SFQ pulse. In <FIG>, a positive SFQ pulse <NUM> is applied to the logical clock input LCLKI. This positive clock pulse triggers output Josephson junction J4 positively and also negatively triggers stacked Josephson junction J3, as indicated by the dots next to those junctions in <FIG>. The triggering sends a positive output pulse <NUM>, shown in <FIG>, to output QNO, thereby asserting the output and initializing it to a logical "high" state, which can correspond, for example, to a logical "<NUM>" in a larger digital logic device or scheme, such as a memory.

The negative triggering of stacked Josephson junction J3 means that the triggering of Josephson junction J4 does not reverse the bias in the ground-to-bias-network loop as would be the case in most other RQL circuits. In a typical RQL circuit, a single biased Josephson junction would go to a coupled transformer that applied DC and AC and would eventually reach ground, and that would form an inductive loop; a triggering of the single Josephson junction would drive one Φ<NUM> worth of current up into that loop, reversing the biasing seen by the single Josephson junction from +Φ<NUM>/<NUM> to -Φ<NUM>/<NUM>. In the case of circuit <NUM>, the presence of two Josephson junctions in the biasing loop, J3 and J4, and the triggering of J3 upon the triggering of J4, means that the current is not reversed in the loop. Thus, in flip-flop <NUM>, the DC bias seen by output Josephson junction J4 is not reversed at this point, i.e., in <FIG>, because stacked Josephson junction J3 has also been triggered, and from the perspective of the ground-to-bias-network loop, the triggering of both of these Josephson junctions cancels out what would otherwise be a bias-reversing effect. Plotted in terms of phase, the node between Josephson junctions J3 and J4 is at 2π radians while both of the nodes on the opposite sides of these Josephson junctions is at <NUM> radians.

In <FIG>, the negative SFQ pulse <NUM> of the logical clock reciprocal pulse pair is applied at logical clock input LCLKI. Because the DC bias of output Josephson junction J4 is still positive, inhibiting a negative triggering at output Josephson junction J4, negative pulse <NUM> is unable to trigger output Josephson junction J4, and instead triggers escape Josephson junction J5 negatively, as shown in <FIG> by the dot to the right of escape Josephson junction J5. Consequently, the introduction of negative pulse <NUM> causes no change in the output. Thus, as shown in <FIG>, no pulse is propagated out of output QNO. In other words, <FIG> shows that negative logical clock pulse <NUM> has been rejected by the triggering of escape Josephson junction J5. From both of the initializing pulses <NUM>, <NUM> provided to logical clock input LCKLI, only one pulse <NUM> has been propagated out of output QNO. The initialization being complete with the provision of both pulses of a first reciprocal pulse pair at the logical clock input LCLKI, circuit <NUM> is placed in "phase mode one": as shown in <FIG>, all of the Josephson junctions attached to output QNO (J3, J4, J5) have one dot on the output side, and the phase of the output QNO is at 2π radians.

With no input pulses applied at data input DI, any subsequent logical clock reciprocal pulse pairs arriving at logical clock input LCKLI will only trigger escape Josephson junction J5 and will have no effect on the output QNO, as shown in <FIG>. Thus, for example, <FIG> shows the arrival of the positive pulse <NUM> of a second or subsequent logical clock pulse pair at logical clock input LCLKI, in the absence of any input at data input DI. <FIG> shows that this pulse <NUM> triggers escape Josephson junction J5 in the opposite direction (i.e., untriggers escape Josephson junction J5), as illustrated by dots on both sides of escape Josephson junction J5, which dots are both erased in the next drawing, <FIG>, consistent with the notation convention that dots on both sides of a Josephson junction are equivalent to no dots at all.

In <FIG>, the negative pulse <NUM> of the second or subsequent logical clock pulse pair arrives at logical clock input LCLKI, still in the absence of any input at data input DI. <FIG> shows that this pulse <NUM> triggers escape Josephson junction J5 negatively, because the DC bias of output Josephson junction J4 is still positive, such that negative pulse <NUM> is unable to trigger output Josephson junction J4. Thus, circuit <NUM> is in the same state in <FIG> after arrival of second or subsequent negative logical clock pulse <NUM> as it was in <FIG> after the arrival of first negative logical clock pulse <NUM>. As long as the logical clock continues to clock with reciprocal pulse pairs with no data input to DI, circuit <NUM> sits in the same phase mode value and no output pulse is issued out of inverting output QNO.

<FIG> shows a positive SFQ pulse <NUM> being applied at data input DI. As shown in <FIG>, positive data input pulse <NUM> triggers input Josephson junction J2 positively, propagating pulse <NUM>, which in turn causes stacked Josephson junction J3 to trigger positively, as shown in <FIG>. As discussed previously, triggering stacked Josephson junction J3 drives one Φ<NUM> worth of current into the two bias networks (i.e., up toward DC and AC source bias_1 through inductor L2 and also toward L8 as well), thereby reversing the DC bias seen by output Josephson junction J4, because the return path for both of those loops is through output Josephson junction J4. In this way, the triggering of stacked Josephson junction J3 ends up negatively biasing output Josephson junction J4, thereby obtaining the inversion effect of circuit <NUM>.

In this new bias state, when a reciprocal pulse pair is applied to the logical clock input LCLKI, as shown in <FIG>, the positive logical clock pulse <NUM>, shown in <FIG>, triggers escape Josephson junction J5, as shown by the additional dot next to escape Josephson junction J5 in <FIG>, and causes no change in the output QNO. However, the subsequent negative logical clock pulse <NUM>, which is also shown in <FIG>, triggers output Josephson junction J4 negatively, as shown in <FIG>, thus propagating negative output pulse <NUM>, deasserting the output QNO and resetting it to a logical "low" state ("phase mode zero"). This can correspond, for example, to a logical "<NUM>" in a larger digital logic device or scheme, such as a memory. Negative output pulse <NUM> in <FIG> corresponds to positive data input pulse <NUM> in <FIG>, as clocked in by negative logical clock input pulse <NUM>. The conversion of the positive input pulse <NUM> into the negative output pulse <NUM> demonstrates the inverting functionality of flip-flop circuit <NUM>. This inversion is achieved without the requirement of passing any pulse through an inverter circuit stage.

It may be noted that <FIG> includes a dot over stacked Josephson junction J3, indicating a phase change of that Josephson junction as compared to <FIG>. Every time output Josephson junction J4 triggers, stacked Josephson junction J3 also triggers in the opposite direction, which is why the DC bias does not reverse. When output Josephson junction J4 previously triggered positively (i.e., as the result of pulse <NUM>), output Josephson junction J4 received a dot on top (as seen in <FIG>) while stacked Josephson junction J3 triggered negatively at the same time and received a dot on the bottom (also as seen in <FIG>). Here, in <FIG>, when output Josephson junction J4 triggers negatively to receive a dot on the bottom (effectively canceling out the previous dot on top of output Josephson junction J4), stacked Josephson junction J3 triggers positively, thus receiving a dot on top.

<FIG> and <FIG> illustrate how a subsequent negative data input pulse <NUM> applied at data input DI can negatively trigger input Josephson junction J2 and, subsequently, stacked Josephson junction J3. This undoes the effects of the positive pulse <NUM> on data input DI and, as shown in <FIG>, returns the DC biases seen by output Josephson junction J4 to the initial state, i.e., the same state shown in <FIG>, wherein output Josephson junction J4 is biased positively with bias current flowing down from the bias networks at the top and right of circuit <NUM> to the ground at the bottom. The next received logical clock pulse pair will therefore restore the circuit to "phase mode one" in the same manner as shown in <FIG>, outputting a positive SFQ pulse, like pulse <NUM> in <FIG>, corresponding to negative data input pulse <NUM> shown in <FIG>.

If, after introducing a positive pulse <NUM> to data input DI to produce negative output pulse <NUM> (as shown in <FIG>), further clocking of the circuit is done by provision of additional reciprocal pulse pairs to logical clock input LCLKI in the absence of pulses to data input DI, no phase mode change to circuit <NUM> will be obtained and no pulses will issue from output QNO. The only product of such additional clocking will be additional triggering and untriggering of escape Josephson junction J5 (similar to, but the inverse of, the behavior illustrated in <FIG>). After circuit initialization, output Josephson junction J4 will only trigger when the circuit is directed to put a new state to the output by provision of an appropriate pulse to data input DI.

Inverting flip-flop <NUM> uses reciprocal pulse pairs at logical clock input to fully evaluate its data inputs into its outputs. When the data input changes, on the next logical clock pulse pair, one or the other logical clock pulse will be allowed through to the output, depending on which logical state change is demanded by the circuit's previous logical state and the data input. In contrast to the functioning of many other RZ-data-encoded RQL circuits, the two logical clock pulses of a pulse pair are not required to both come within one AC cycle of the biasing network bias_1, but generally speaking, having both pulses of a reciprocal pair come within one AC cycle is advantageous, because separating them further in time would only make circuit <NUM> operate more slowly. The data input can advantageously be provided at DI so as not to change between the two pulses of any one logical clock reciprocal pulse pair, because, in effect, both pulses of a pulse pair supplied to logical clock input LCLKI sample the data value supplied at data input DI. Relative timing of data and logical clock pulses can be enforced by logic outside of the inverting flip-flop <NUM>, i.e., elsewhere in the system of which flip-flop <NUM> is a part.

<FIG> is a circuit schematic of another example implementation <NUM> of an RQL PML inverting D flip-flop circuit, similar in structure to circuit <NUM>, but with the elimination of transformer-coupled grounded inductor L8. RQL biasing is usually implemented via transformer coupling to a grounded inductor. Therefore, by reducing the size of bias inductor L2REDUCED in circuit <NUM> as compared to inductor L2 in circuit <NUM> and reducing the AC component of DC and AC bias bias_1_ac_reduced in circuit <NUM> as compared to the AC component of DC and AC bias bias_1 in circuit <NUM>, this DC and AC bias source can effectively be combined in parallel with the DC bias source that would otherwise be supplied by now-eliminated grounded inductor L8, resulting in a smaller circuit. In the DC and AC bias source labeled in bias_1 in circuit <NUM>, there is additional inductance LSOURCE (not shown in the drawings) that is part of the transformers that inject direct and alternating current. This additional inductance LSOURCE is an inductance to ground. Inductor L8 to be eliminated is also an inductance to ground. Thus, the size of L2REDUCED is set by the formula L8∥(L2 + LSOURCE) = L2REDUCED + LSOURCE, or, equivalently, L2REDUCED = L8∥L2 + L8∥LSOURCE - LSOURCE. In circuit <NUM> as compared to circuit <NUM>, so that DC and AC bias source bias_1 can provide Φ<NUM>/<NUM> DC and reduced. amplitude AC, the amount of AC power coupled in the AC transformer (not shown) associated with bias_1_ac_reduced is modified so that the total AC bias level provided to Josephson junctions J3 and J4 is still the same in circuit <NUM> as in circuit <NUM>. The operation of circuit <NUM> is otherwise the same as previously described for circuit <NUM>. D flip-flop <NUM> is therefore extremely efficient in terms of its use of devices, requiring only three or four Josephson junctions and only two to four inductors, apart from any devices used for race condition avoidance phasing of input signals, and notably without requiring a separate dedicated signal inversion circuit stage.

<FIG> is a circuit schematic of another example implementation <NUM> of an RQL PML inverting D flip-flop circuit, similar in structure to circuit <NUM>, but with the substitution of resistor R1 for escape Josephson junction J5. In circuit <NUM>, operating margins are significantly more affected by variations in the size of escape Josephson junction J5 than by variation in sizes of other components in the circuit. In circuit <NUM>, therefore, escape Josephson junction J5 is replaced by a small passive resistor R1. The operation of circuit <NUM> is substantially the same as previously described for circuit <NUM>, except as follows. In circuit <NUM>, a logical clock input pulse that fails to trigger output Josephson junction J4 is dissipated by triggering escape Josephson junction. <NUM>, as shown, for example, in <FIG>, <FIG>, and <FIG> (corresponding to dissipated pulses <NUM>, <NUM>, and <NUM>, respectively). By contrast, in circuit <NUM>, any such pulse is dissipated gradually in resistor R1 (e.g., into heat). Resistor R1 can be sized such that the L/R time constant of the loop comprising logical clock input inductor L6a, dissipation resistor R1, output Josephson junction J4, and a logical clock input driving Josephson junction (not shown, but located between LCLKI and ground in <FIG>) allows the loop to dissipate one Φ<NUM> worth of current in less than one half of an AC cycle period as supplied by DC and AC bias bias_1, such that the pulse being dissipated does not interfere with the arrival of the next logical clock pulse. For example, the value of resistor R1 can be between about one ohm and about ten ohms, e.g., between about two ohms and about five ohms. As with circuit <NUM>, in circuit <NUM>, AC and DC bias source bias_1 can provide Φ<NUM>/<NUM> worth of direct current plus an AC waveform signal (e.g., a sinusoidal signal), while the DC bias provided through inductor L8 can provide Φ<NUM>/<NUM> worth of direct current. D flip-flop <NUM> is therefore highly efficient in terms of its use of devices, requiring only two or three Josephson junctions, one resistor, and only three to five inductors, apart from any devices used for race condition avoidance phasing of input signals, and notably without requiring a separate dedicated signal inversion circuit stage.

<FIG> is a circuit schematic of another example implementation <NUM> of an RQL PML inverting D flip-flop circuit, similar in structure to circuit <NUM>, but with both the elimination of transformer-coupled grounded inductor L8, as in circuit <NUM>, and the substitution of resistor R1 for escape Josephson junction J5, as in circuit <NUM>. Accordingly, the size of bias inductor L2 is reduced in circuit <NUM> as compared to circuit <NUM> and the AC component of AC and DC bias bias_1 is reduced in circuit <NUM> as compared to circuit <NUM>, as described above with regard to circuit <NUM>. The operation of circuit <NUM> is otherwise the same as previously described for circuit <NUM>. D flip-flop <NUM> is therefore extremely efficient in terms of its use of devices, requiring only two or three Josephson junctions, one resistor, and only two to four inductors, apart from any devices used for race condition avoidance phasing of input signals, and notably without requiring a separate dedicated signal inversion circuit stage.

<FIG> is a flow chart illustrating a method <NUM> of operating (e.g., writing and reading a logical value to and from) an inverting RQL phase-mode D flip-flop. The flip-flop can be like those described with reference to <FIG>, <FIG>, <FIG>, or <FIG>. An inverting RQL flip-flop is initialized <NUM> with logical clock reciprocal pulse pair to set the flip-flop (i.e., its output) to a phase mode corresponding to a logical "<NUM>" value. A positive SFQ pulse is then provided <NUM> to a data input of the inverting RQL flip-flop. A stacked Josephson junction in the flip-flop is triggered <NUM> to reverse the direction of a DC bias current flowing through an output Josephson junction in the flip-flop. Another reciprocal SFQ pulse pair is then provided <NUM> to a logical clock input of the flip-flop. Only the negative pulse of the logical clock pulse pair is passed <NUM> to the flip-flop output, based on reversed DC bias. The positive pulse of the logical clock pulse pair is absorbed <NUM> using either an escape Josephson junction or resistor to absorb that pulse. Thus, the flip-flop is reset <NUM> to a phase mode corresponding to a logical "<NUM>" value. This method can correspond, for example, to the functioning shown in <FIG> and <FIG>.

<FIG> is a flow chart illustrating a method <NUM> of operating (e.g., writing and reading a logical value to and from) an inverting RQL phase-mode D flip-flop, that can continue from the method <NUM> of <FIG>. A negative SFQ pulse can be provided <NUM> to the data input of the inverting RQL flip-flop. This, in turn, untriggers <NUM> the stacked Josephson junction in the flip-flop to restore the (e.g., previously reversed) direction of the DC bias current flowing through the output Josephson junction in the flip-flop. Then, still another reciprocal SFQ pulse pair can be provided <NUM> to the logical clock input of the flip-flop. Now, only the positive pulse of the reciprocal pulse pair is passed <NUM> to the flip-flop output, based on the restored DC bias, while the negative pulse of the pulse pair is absorbed <NUM> with either an escape Josephson junction or a resistor. The flip-flop is thereby set <NUM> to a phase mode corresponding to a logical "<NUM>" value. This method can correspond, for example, to the functioning shown in <FIG> and <FIG>.

The present disclosure provides a flip-flop with an inverted output that improves design efficiency by reducing the need for discrete inverters. The inverting flip-flop described herein is both smaller (in terms of part count and chip area required for implementation) and faster (in terms of signal propagation time) than implementations that combine a flip-flop and an inverter. These efficiency improvements lead to smaller die area and a lower cost per die.

Claim 1:
An inverting reciprocal quantum logic, RQL, phase-mode flip-flop (<NUM>, <NUM>, <NUM>) comprising:
a stacked Josephson junction (<NUM>, <NUM>, J3) configured to receive a data input signal (D) on a data input line as a positive or a negative single flux quantum, SFQ, pulse and to reverse a DC bias current flowing in the flip-flop (<NUM>, <NUM>, <NUM>) based on the data input signal (D); and
a comparator (<NUM>, <NUM>) configured to receive a logical clock input signal (LCLK) and to either transmit the logical clock input signal (LCLK) on an output line as an output signal (Q) of the flip-flop (<NUM>, <NUM>, <NUM>), the output signal (Q) being a logical inversion of the data input signal (D), or to suppress such transmission, based on the direction of the DC bias current and a logical output state of the flip-flop (<NUM>, <NUM>, <NUM>), the comparator (<NUM>, <NUM>) comprising an output Josephson junction (<NUM>, J4) and either an escape Josephson junction (<NUM>, J5) or a dissipating resistor (R1), the output Josephson junction (<NUM>, J4) being coupled between the output line and a circuit ground;
wherein the stacked Josephson junction (<NUM>, <NUM>, J3) is coupled between the output Josephson junction (<NUM>, J4) and a bias source of the DC bias current such that the stacked Josephson junction (<NUM>, <NUM>, J3) and the output Josephson junction (<NUM>, J4) are biased in series as series Josephson junctions and the triggering of one of the series Josephson junctions can change the DC bias of the other of the series Josephson junctions.