Patent Description:
As a core device in an electronic circuit, a power semiconductor component may be used to implement efficient transmission and conversion of electric energy, and implement efficient utilization of electric energy.

The power semiconductor component may be integrated into the power semiconductor chip. To prevent external water vapor and movable ions (for example, sodium) from affecting the power semiconductor component inside the power semiconductor chip, a passivation layer is usually covered on a part of a metal layer which is located in a terminal area of the power semiconductor chip, and the passivation layer is used to block the water vapor.

However, in some scenarios, when a reliability test such as a temperature cycle test (TCT) or a thermal shock test (TS) is performed on a semiconductor component, because thermal expansion coefficients of the metal layer and the passivation layer mismatch, stress is generated between the metal layer and the passivation layer due to mutual extrusion, and excessive stress causes a crack on the passivation layer at a step of the metal layer. Consequently, the water vapor enters an active area of the power semiconductor chip from the crack on the passivation layer, and erodes the power semiconductor component, affecting reliability of the power semiconductor component.

<CIT> discloses: a chip, divided into a main functional area, a transition area, and a protection area, wherein the transition area is located between the main functional area and the protection area; the chip comprises a field oxide, a metal layer, and a passivation layer that are sequentially stacked on a semiconductor substrate, wherein the field oxide and the passivation layer are located in the transition area and the protection area, and the metal layer is located in the main functional area and the transition area; and in the transition area, the field oxide comprises a primary field oxide and at least one secondary field oxide that are disposed at intervals, wherein the secondary field oxide is located on a side of the primary field oxide facing the main functional area, the metal layer extends from the main functional area to a side of the primary field oxide facing away from the semiconductor substrate, and the passivation layer extends from a side of the metal layer facing away from the semiconductor substrate to a side of the metal layer facing away from the main functional area.

To resolve the foregoing technical problem, this application provides a chip and an electronic device, to reduce a cracking risk of a passivation layer and improve reliability of the chip. The claimed invention is described in independent product claim <NUM> and its dependent claims <NUM>-<NUM>.

Reference numerals:
<NUM>: semiconductor substrate; <NUM>: field plate; <NUM>: field oxide; <NUM>: primary field oxide; <NUM>: secondary field oxide; <NUM>: passivation layer; <NUM>: main junction; <NUM>: metal layer; <NUM>: first metal layer; <NUM>: second metal layer; <NUM>: first part; and <NUM>: second part.

To make the objectives, technical solutions, and advantages of this application clearer, the following clearly and completely describes the technical solutions of this application with reference to the accompanying drawings in embodiments of this application. It is clear that the described embodiments are merely a part rather than all of embodiments of this application. All other embodiments obtained by a person of ordinary skill in the art based on embodiments of this application without creative efforts shall fall within the protection scope of this application.

In this specification, embodiments, claims, and accompanying drawings of this application, terms "first", "second", and the like are merely intended for distinguishing and description, and shall not be understood as an indication or implication of relative importance or an indication or implication of an order. The term "and/or" is used for describing an association relationship between associated objects, and represents that three relationships may exist. For example, "A and/or B" may represent the following three cases: Only A exists, only B exists, and both A and B exist, where A and B may be singular or plural. The character "/" usually indicates an "or" relationship between associated objects. "Installation", "connection", "being connected to", and the like should be understood in a broad sense, for example, may be a fixed connection, a detachable connection, or an integral connection; or may be a direct connection, an indirect connection through an intermediate medium, or internal communication between two elements. In addition, the terms "include", "have", and any variant thereof are intended to cover non-exclusive inclusion, for example, include a series of steps or units. Methods, systems, products, or devices are not necessarily limited to those steps or units that are literally listed, but may include other steps or units that are not literally listed or that are inherent to such processes, methods, products, or devices. "On", "below", "left", "right", and the like are used only relative to the orientation of the components in the accompanying drawings. These directional terms are relative concepts, are used for relative descriptions and clarifications, and may change accordingly as positions at which the components in the accompanying drawings are placed change.

An embodiment of this application provides an electronic device. The electronic device may be an electronic device that requires a chip, such as a mobile phone, a computer, a tablet computer, an automobile, or a wearable device. Certainly, the electronic device may alternatively be another device. A specific form of a terminal is not limited in this embodiment of this application. The foregoing chip may be any chip, including but not limited to a power semiconductor chip. For ease of description, unless otherwise specified, the following uses an example in which the chip is a power semiconductor chip for description.

Most of the electric energy generated by hydropower, thermal power, wind power, or a chemical battery cannot be directly applied to an electronic device. More than <NUM>% of the electric energy can be applied to the electronic device only after being converted by a power semiconductor component.

As shown in <FIG>, an automobile is used as an example. A battery, a switch, and a direct current (DC)/alternating current (AC) device are integrated in the automobile. The battery can provide direct current voltage for the automobile, but the automobile needs to be started under the control of alternating current voltage. Therefore, the power semiconductor component may be used as a switch, so that the DC/AC device is turned on, and the received direct current voltage is converted into the alternating current voltage by using the DC/AC device, so that the automobile is started under the control of the alternating current voltage.

As mentioned above, the passivation layer located in the terminal area is prone to cracks under stress. As a result, the water vapor enters the active area, affecting the reliability of the power semiconductor component.

Specifically, as shown in <FIG>, a chip may include a main functional area, a transition area, and a protection area. The transition area and the protection area are located at a periphery of the main functional area, and the transition area is located between the main functional area and the protection area. The main functional area of the chip may correspond to an active area of a power semiconductor chip, and the transition area and the protection area of the chip may correspond to a terminal area of the power semiconductor chip. The terminal area may be of a field limiting ring (FLR) structure, a junction terminal extension (JTE) structure, a variation lateral doping (VLD) structure, various derived composite terminal structures, and the like.

For example, a structure of the transition area and a structure of the protection area are FLR structures. As shown in <FIG>, in the main functional area, the power semiconductor chip includes the power semiconductor component disposed on the semiconductor substrate. For example, the power semiconductor component may include a diode, a transistor, a thyristor, and the like disposed on a semiconductor substrate <NUM>. The power semiconductor component includes a metal layer <NUM>, and the metal layer <NUM> may extend from the main functional area to the transition area. In addition, the power semiconductor chip includes a main junction <NUM>, a field oxide <NUM>, an metal layer <NUM>, and a passivation layer <NUM> that are sequentially stacked on the semiconductor substrate <NUM>. The main junction <NUM> may be located in the main functional area, the transition area, and the protection area. The field oxide <NUM> is located in the transition area and the protection area. The metal layer <NUM> is located in the protection area. The passivation layer is located in the transition area and the protection area, and may cover a part of the metal layer <NUM> located in the transition area and cover the metal layer <NUM>, to block water vapor and prevent the water vapor from entering the main functional area. The metal layer <NUM> and the metal layer <NUM> that are disposed in the transition area and the protection area may play a role such as modulating electric field distribution.

A pattern of the main junction <NUM> and some film layers in the power semiconductor component may be prepared by using a same semiconductor process. For example, the pattern of the main junction <NUM> and an active layer in the power semiconductor component are prepared by using a same semiconductor process, and a pattern of the metal layer <NUM> and the metal layer <NUM> in the power semiconductor component are prepared by using a same semiconductor process. In this way, a chip preparation process can be simplified.

In addition, in the transition area, the field oxide <NUM> is disposed between the metal layer <NUM> and the metal layer <NUM> adjacent to the metal layer <NUM>, and the metal layer <NUM> extends from the main functional area to a side of the field oxide <NUM> facing away from the semiconductor substrate <NUM>. In the protection area, the field oxide <NUM> is further disposed between adjacent metal layers <NUM>, and each metal layer <NUM> extends from a surface of the field oxide <NUM> facing away from the semiconductor substrate <NUM> to a surface of a field oxide <NUM> that is adjacent to the field oxide <NUM> and that faces away from the semiconductor substrate <NUM> through an exposed surface on a side of the main junction <NUM> facing away from the semiconductor substrate <NUM>. Adjacent metal layers <NUM> are disposed at intervals along a direction from the main functional area to the protection area.

In the transition area, the passivation layer <NUM> is disposed between adjacent metal layers <NUM> and the metal layer <NUM> adjacent to the metal layer <NUM>, and extends from a surface of the metal layer <NUM> facing away from the semiconductor substrate <NUM> to a surface of an metal layer <NUM> that is adjacent to the metal layer <NUM> and that faces away from the semiconductor substrate <NUM>. In the protection area, the passivation layer <NUM> is further disposed between adjacent metal layers <NUM>, and each passivation layer <NUM> extends from a surface of the metal layer <NUM> facing away from the semiconductor substrate <NUM> to a surface of an metal layer <NUM> and that is adjacent to the metal layer <NUM> and that faces away from the semiconductor substrate <NUM>. Adjacent passivation layers <NUM> are disposed at intervals along a direction from the main functional area to the protection area.

However, for a chip whose structure of the transition area and structure of the protection area are the JTE structure and the VLD structure, in the terminal area, the power semiconductor chip also includes the main junction <NUM>, the field oxide <NUM>, and the passivation layer <NUM> that are sequentially stacked on the semiconductor substrate <NUM>. In addition, the metal layer <NUM> may also extend from the main functional area to the transition area. However, the chip of the JTE structure and the chip of the VLD structure may not include a field plate <NUM>.

For the JTE structure, as shown in <FIG>, the protection area may include a plurality of junction terminal extension areas, and a plurality of main junctions <NUM> are respectively located in the plurality of junction terminal extension areas. In a direction away from the main functional area, doping concentration of the plurality of main junctions <NUM> gradually decreases, and doping depth gradually becomes shallower.

For the VLD structure, as shown in <FIG>, the main junction <NUM> may extend from the main functional area to the protection area, but along the direction away from the main functional area, the doping concentration of the main junction <NUM> gradually decreases, and thickness of the main junction <NUM> also gradually decreases.

As shown in <FIG>, in the transition area, because the metal layer <NUM> has a specific pattern, and thickness of a part of the metal layer <NUM> located in the transition area is, for example, the same as thickness of a part of the metal layer <NUM> located in the main functional area, to meet a design requirement of bonding or welding of the power semiconductor component, the metal layer <NUM> is usually relatively thick, and a thickness range may reach [<NUM>, <NUM>]. When a reliability test such as TCT or TS is performed on the semiconductor component, stress on the metal layer <NUM> with a relatively large size is conducted to the passivation layer <NUM>, the passivation layer <NUM> may crack because stress at a step of the metal layer <NUM> which is climbed by the passivation layer <NUM> is excessively large. Consequently, the water vapor enters the main functional area of the power semiconductor chip from a crack on the passivation layer <NUM>, and erodes the power semiconductor component, affecting the reliability of the power semiconductor component.

In addition, it should be noted that material of the passivation layer <NUM> is not limited in this embodiment of this application. Optionally, material with relatively good waterproof effect may be selected as the material of the passivation layer <NUM>. For example, the material of the passivation layer <NUM> may include an inorganic insulation material, and the inorganic insulation material may be silicon nitride (SiN).

For the semiconductor substrate <NUM>, the semiconductor substrate <NUM> may include a substrate. If material of the substrate includes silicon (Si), the semiconductor substrate <NUM> may include only the substrate. If the material of the semiconductor substrate <NUM> includes silicon carbide (SiC), the semiconductor substrate <NUM> may further include an epitaxial layer disposed between the substrate and a structure such as the field oxide <NUM>.

Based on the foregoing problem, in this application, the structure of the field oxide <NUM> is improved to reduce the stress conducted by the metal layer <NUM> to the passivation layer <NUM> and reduce the cracking risk of the passivation layer <NUM>.

The following describes a specific structure of the chip in detail with reference to the accompanying drawings.

As shown in <FIG>, for a chip whose structure of the transition area and structure of the protection area are the JTE structure and the VLD structure, the chip includes the field oxide <NUM>, the metal layer <NUM>, and the passivation layer <NUM> that are sequentially stacked on the semiconductor substrate <NUM>. The field oxide <NUM> and the passivation layer <NUM> are located in the transition area and the protection area. The metal layer <NUM> is located in the main functional area and the transition area. In the transition area, the field oxide <NUM> includes a primary field oxide <NUM> and at least one secondary field oxide <NUM> that are disposed at intervals. The secondary field oxide <NUM> is located on a side of the primary field oxide <NUM> facing the main functional area. The metal layer <NUM> extends from the main functional area to a side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>. The passivation layer <NUM> extends from a side of the metal layer <NUM> facing away from the semiconductor substrate <NUM> to a side of the metal layer <NUM> facing away from the main functional area.

It should be noted herein that, as shown in <FIG>, the metal layer <NUM> extends from the main functional area to the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM> means that the metal layer <NUM> that extends from the main functional area to the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM> is of a continuous structure. In addition, because the secondary field oxide <NUM> is located on the side of the primary field oxide <NUM> facing the main functional area, the continuous metal layer <NUM> not only covers a surface of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>, but also covers all surfaces of the secondary field oxide <NUM> facing away from the semiconductor substrate <NUM>.

In some possible implementations, in this application, the existing field oxide <NUM> may be divided into the primary field oxide <NUM> and the at least one secondary field oxide <NUM>; or in this application, the at least one secondary field oxide <NUM> may be added on the basis of the existing field oxide <NUM>.

In the solution of this application, in the transition area, the existing field oxide <NUM> is divided into the primary field oxide <NUM> and the at least one secondary field oxide <NUM>, or the at least one secondary field oxide <NUM> is added on the basis of the existing primary field oxide <NUM>, and the primary field oxide <NUM> and the at least one secondary field oxide <NUM> are disposed at intervals. In this way, the at least one secondary field oxide <NUM> may provide buffer effect, to prevent stress that extends from the main functional area to a metal layer <NUM> on the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM> from being transmitted to the passivation layer <NUM>, thereby effectively reducing stress between a large-sized metal layer <NUM> and the passivation layer <NUM>, reducing the cracking risk of the passivation layer <NUM>, and preventing the water vapor from entering the main functional area of the chip through a crack on the passivation layer <NUM>, which may affect functions of components in the main functional area.

In some possible implementations, as shown in <FIG>, to prevent the water vapor from entering the main functional area through the field oxide <NUM>, the passivation layer <NUM> further extends from the side of the metal layer <NUM> facing away from the main functional area to a side of the primary field oxide <NUM> facing away from the main functional area. In this case, as shown in <FIG>, the metal layer <NUM> covers a part of a surface on the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>; or as shown in <FIG>, the metal layer <NUM> completely covers a surface on the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>.

As shown in <FIG>, in the transition area, the metal layer <NUM> covers the part of the surface on the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>. In this way, along a direction from the semiconductor substrate <NUM> to the metal layer <NUM>, the passivation layer <NUM> first climbs from the side of the primary field oxide <NUM> facing away from the main functional area to the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM>; and then climb from the side of the metal layer <NUM> facing away from the main functional area to the side of the metal layer <NUM> facing away from the semiconductor substrate <NUM>. Therefore, the passivation layer <NUM> is prevented from simultaneously climbing at a step of the primary field oxide <NUM> and a step of the metal layer <NUM>, and a total height of steps that need to be climbed by the passivation layer <NUM> is increased, so that the cracking risk of the passivation layer <NUM> may be reduced.

In some possible implementations, as shown in <FIG> and <FIG>, there may be one secondary field oxide <NUM>; or as shown in <FIG>, there may be a plurality of secondary field oxides <NUM>. A quantity of the secondary field oxides <NUM> is related to a size of the secondary field oxide <NUM>, a size of the primary field oxide <NUM>, spacing between the secondary field oxide <NUM> and the primary field oxide <NUM>, spacing between adjacent secondary field oxides <NUM>, and a size of the chip. This is not limited in this embodiment of this application.

It should be noted herein that when there are a plurality of secondary field oxides <NUM>, and the plurality of secondary field oxides <NUM> are disposed at intervals.

Optionally, as shown in <FIG>, there may be three secondary field oxides <NUM>. Along a direction from the main functional area to the protection area, a length range of each secondary field oxide <NUM> is [<NUM>, <NUM>], and a spacing range between adjacent secondary field oxides <NUM> is [<NUM>, <NUM>].

For example, as shown in <FIG>, a distance L from a side that is closest to the main functional area and that is of the secondary field oxide facing the main functional area to the side of the primary field oxide facing away from the main functional area is <NUM>. Along the direction from the main functional area to the protection area, a length L1 of the primary field oxide <NUM> may be <NUM>, and a length L2 of each secondary field oxide <NUM> may be <NUM>, the spacing between the adjacent secondary field oxides <NUM> and the spacing between the primary field oxide <NUM> and the secondary field oxide <NUM> may be <NUM>. In this case, there may be three secondary field oxides <NUM>.

In some possible implementations, whether there is one or more secondary field oxides <NUM>, both the primary field oxide <NUM> and the at least one secondary field oxide <NUM> that are located in the transition area may be prepared by using the same semiconductor process.

For example, the primary field oxide <NUM> and the at least one secondary field oxide <NUM> may be formed by using the following steps: first, a thin film and a first photoresist are sequentially formed on the semiconductor substrate <NUM>. Then, exposure is performed on the first photoresist, and a first photoresist pattern is obtained after development. The first photoresist pattern covers the to-be-formed primary field oxide <NUM> and the at least one secondary field oxide <NUM>, and exposes an area of the thin film other than the area occupied by the to-be-formed primary field oxide <NUM> and the at least one secondary field oxide <NUM>. Then, under protection of the first photoresist pattern, the thin film is etched to obtain the primary field oxide <NUM> and the at least one secondary field oxide <NUM>. The thin film may be, for example, a silicon dioxide (SiO<NUM>) thin film.

Certainly, another process may alternatively be used to form the primary field oxide <NUM> and the at least one secondary field oxide <NUM>. This is not limited in this embodiment of this application. Provided that a finally obtained structural relationship between the primary field oxide <NUM> and the at least one secondary field oxide <NUM> is the same as that described above, a process of forming the primary field oxide <NUM> and the at least one secondary field oxide <NUM> falls within the protection scope of this application. In addition, the field oxide <NUM> located in the protection area and the field oxide <NUM> located in the transition area may also be prepared by using a same semiconductor process.

The foregoing embodiment describes the chip whose structure of the transition area and structure of the protection area are the JTE structure and the VLD structure. For the chip whose structure of the transition area and structure of the protection area are the FLR structures, the chip may further include an metal layer <NUM>. As shown in <FIG>, which does not fall within the scope of the claimed invention, the metal layer <NUM> is located in the protection area. In the protection area, the metal layer <NUM> extends from the side of the primary field oxide <NUM> facing away from the semiconductor substrate <NUM> to the side of a primary field oxide <NUM> that is adjacent to the primary field oxide <NUM> and that faces away from the semiconductor substrate <NUM>. In addition to covering the metal layer <NUM>, the passivation layer <NUM> further extends from a side of the metal layer <NUM> facing away from the semiconductor substrate <NUM> to a side of an metal layer <NUM> that is adjacent to the metal layer <NUM> and that faces away from the semiconductor substrate <NUM>. In this way, not only the metal layer <NUM> can be used to provide an isopotential function, but also the passivation layer <NUM> can be used to cover the metal layer <NUM>, to prevent the water vapor from entering the main functional area.

As mentioned above, the thickness of the part of the metal layer <NUM> located in the main functional area is the same as the thickness of the part of the metal layer <NUM> is located in the transition area. However, to meet a design requirement of the metal layer <NUM>, the metal layer <NUM> is usually relatively thick. Consequently, the height of the step at the metal layer <NUM> which needs to be climbed by the passivation layer <NUM> is relatively high, and under stress, the passivation layer <NUM> easily cracks at the step.

Based on this, in some embodiments, which do not fall within the scope of the claimed invention but are useful for understanding the invention, as shown in <FIG>, the metal layer <NUM> may include a first part <NUM> and a second part <NUM>. The first part <NUM> is located in at least the main functional area, and the second part <NUM> is located in the transition area. Along a direction from the metal layer <NUM> to the semiconductor substrate <NUM>, thickness of the first part <NUM> is greater than thickness of the second part <NUM>.

In this application, by reducing the thickness of the second part <NUM>, stress conducted from the first part <NUM> with a relatively large size to the second part <NUM> can be reduced, to reduce the stress between the metal layer <NUM> (or the second part) and the passivation layer <NUM>, reduce the cracking risk of the passivation layer <NUM>, and prevent the water vapor from entering the main functional area of the chip through the crack on the passivation layer <NUM>, which may affect the functions of the components in the main functional area.

In some possible implementations, a thickness range of the first part <NUM> and a thickness range of the second part <NUM> are not limited in this embodiment of this application, provided that the second part <NUM> can provide the isopotential function, and the first part <NUM> can meet a design requirement of components located in the main functional area.

Optionally, the thickness range of the second part <NUM> may be [<NUM>, <NUM>]. For example, the thickness of the second part <NUM> may be <NUM>, <NUM>, <NUM>, or <NUM>. The thickness range of the first part <NUM> may be [<NUM>, <NUM>]. For example, the thickness of the metal layer <NUM> may be <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>.

In some possible implementations, as shown in <FIG>, in addition to being located in the main functional area, the first part <NUM> may further extend from the main functional area to the transition area. In other words, in addition to a part of the first part <NUM> being disposed in the main functional area, other parts of the first part <NUM> may further be disposed in the transition area, to prevent a phenomenon that in a process of preparing components in the main functional area, the first part <NUM> cannot be in good contact with another component in the main functional area due to inaccurate alignment process which may affect the performance of the components in the main functional area. In addition, by locating the part of the first part <NUM> located in the transition area on a side of the secondary field oxide <NUM> facing the main functional area, on the basis that the at least one secondary field oxide <NUM> is used to buffer the stress, it can be further avoided that relatively large stress is still conducted to the passivation layer <NUM> after the metal layer <NUM> with relatively large thickness passes through the at least one secondary field oxide <NUM>.

In some possible implementations, a process of preparing the first part <NUM> and the second part <NUM> is not limited in this embodiment of this application. For example, the first part <NUM> and the second part <NUM> that are of the metal layer <NUM> may be prepared in the following several manners.

In a first case, as shown in <FIG>, a first metal layer <NUM> is formed on a side of the field oxide <NUM> facing away from the semiconductor substrate <NUM> by using a same semiconductor process. Thickness of the first metal layer <NUM> is the same as thickness of the second part <NUM>, and the first metal layer <NUM> is located in the main functional area and the transition area. Then, as shown in <FIG>, a second metal layer <NUM> is formed on a side of the first metal layer <NUM> facing away from the semiconductor substrate <NUM> by using a photo-lithographic process, and the second metal layer <NUM> is located in at least the main functional area. In this case, material of the first metal layer <NUM> may be the same as or different from material of the second metal layer <NUM>.

For an area in which the first metal layer <NUM> and the second metal layer <NUM> are disposed in a stacked manner, the first metal layer <NUM> and the second metal layer <NUM> may form the first part <NUM> of the metal layer <NUM>. A thickness range of the first metal layer <NUM> may be [<NUM>, <NUM>], and a thickness range of the second metal layer <NUM> may be [<NUM>, <NUM>], to ensure that a total thickness range of the first part <NUM> is [<NUM>, <NUM>].

In a second case, as shown in <FIG>, the second part <NUM> is first formed in the transition area by using the photo-lithographic process. Then, as shown in <FIG>, the first part <NUM> is formed in the main functional area (or the main functional area and the transition area) by using the photo-lithographic process. In this case, material of the first metal layer <NUM> may be the same as or different from material of the second metal layer <NUM>.

Certainly, the first part <NUM> may be first formed in the main functional area (or the main functional area and the transition area), and then the second part <NUM> is formed in the transition area. This is not limited in this embodiment of this application.

In a third case, a metal thin film and a second photoresist may be first sequentially formed on a side of the field oxide <NUM> facing away from the semiconductor substrate <NUM>. Then, half exposure is performed on the second photoresist, and a second photoresist pattern is obtained after development. The second photoresist pattern includes a fully-reserved area, a half-reserved area, and a fully-exposed area. The fully-reserved area corresponds to a to-be-formed metal layer <NUM>, the half-reserved area corresponds to a to-be-formed second part <NUM>, and the fully-exposed area corresponds to another area. Then, as shown in <FIG>, under protection of the second photoresist pattern, the metal thin film is etched for a first time to obtain a metal pattern <NUM>. Then, exposure is further performed on the second photoresist pattern, and a third photoresist pattern is obtained after the development. The third photoresist pattern corresponds to a to-be-formed first part <NUM>. Then, under protection of the third photoresist pattern, the metal pattern <NUM> is etched to obtain the first part <NUM> and the second part <NUM> that are of the metal layer <NUM> shown in <FIG> or <FIG>. In this case, material of the first metal layer <NUM> is the same as material of the second metal layer <NUM>.

Certainly, the first part <NUM> and the second part <NUM> that are of the metal layer <NUM> may be formed by using another process. This is not limited in this embodiment of this application. Provided that a finally obtained structural relationship between the first part <NUM> and the second part <NUM> is the same as that described above, a process of forming the first part <NUM> and the second part <NUM> that are of the metal layer <NUM> falls within the protection scope of this application.

In addition, for the chip whose transition area and protection area are of the FLR structures, the metal layer <NUM> and the first part <NUM> or the second part <NUM> of the metal layer <NUM> may be formed by using a same semiconductor process. To be specific, when the first part <NUM> is formed, the metal layer <NUM> may be formed by using the same semiconductor process; or when the second part <NUM> is formed, the metal layer <NUM> may be formed by using the same semiconductor process.

In some embodiments, as shown in <FIG>, a surface on the side of the metal layer <NUM> facing away from the main functional area may be a slant surface; and along the direction from the metal layer <NUM> to the semiconductor substrate <NUM>, the distance between the slant surface and the main functional area gradually increases.

In this application, the surface on the side of the metal layer <NUM> facing away from the main functional area is disposed as the slant surface, so that when a height of a step which is climbed by the passivation layer <NUM> remains unchanged, the slant surface can be used to buffer the passivation layer <NUM>, thereby resolving a problem that the passivation layer <NUM> easily cracks at the step, and preventing the water vapor from entering the active area of the power semiconductor chip from the crack on the passivation layer <NUM> and eroding the power semiconductor component, which may affect the reliability of the power semiconductor component.

Claim 1:
A chip, divided into a main functional area, a transition area, and a protection area, wherein the transition area is located between the main functional area and the protection area;
the chip comprises a field oxide (<NUM>), a metal layer (<NUM>), and a passivation layer (<NUM>) that are sequentially stacked on a semiconductor substrate (<NUM>), wherein the field oxide (<NUM>) and the passivation layer (<NUM>) are located in the transition area and the protection area, and the metal layer (<NUM>) is located in the main functional area and the transition area; and
in the transition area, the field oxide (<NUM>) comprises a primary field oxide (<NUM>) and at least one secondary field oxide (<NUM>) that are disposed at intervals, wherein the secondary field oxide (<NUM>) is located on a side of the primary field oxide (<NUM>) facing the main functional area, the metal layer (<NUM>) extends from the main functional area to a side of the primary field oxide (<NUM>) facing away from the semiconductor substrate (<NUM>), and the passivation layer (<NUM>) extends from a side of the metal layer (<NUM>) facing away from the semiconductor substrate (<NUM>) to a side of the metal layer (<NUM>) facing away from the main functional area,
wherein in the transition area, the passivation layer (<NUM>) further extends from the side of the metal layer (<NUM>) facing away from the main functional area to a side of the primary field oxide (<NUM>) facing away from the main functional area; and
the metal layer (<NUM>) covers a part of a surface on the side of the primary field oxide (<NUM>) facing away from the semiconductor substrate (<NUM>), and the passivation layer (<NUM>) extends from the side of the metal layer (<NUM>) facing away from the semiconductor substrate (<NUM>) through the side of the primary field oxide (<NUM>) facing away from the semiconductor substrate (<NUM>) to the side of the primary field oxide (<NUM>) facing away from the main functional area.