Patent Description:
A fifty percent (<NUM>%) duty cycle describes a current flow through the LED <NUM>% of the time and no current flow through the LED the other <NUM>% of the time. A <NUM> % duty cycle describes a current flow through the LED <NUM>% of the time and no current flow <NUM>% of the time. A <NUM>% duty cycle describes a current flow through the LED <NUM>% of the time and no current flow <NUM>% of the time. The PWM signal can have a duty cycle to control the current flow and the brightness of the LED.

Although the controlling pulse width modulated signal may have a well-defined <NUM>% duty cycle of on and off times, unequal capacitances in the circuits implementing the flow of current through the LEDs may cause unequal turn on and turn off times of the current, and produce other than a <NUM>% duty cycle of the LEDs.

While some integrated circuit LED controllers contain an integrated power transistor to drive external power to the LEDs, some applications use an integrated circuit to drive an external power transistor to drive external power to the LEDs. <CIT> describes a constant current LED driver for a SSL device using a HV-DMOS device. <CIT> describes a controller for controlling dimming of a LED light source. <CIT> describes an LED driver with PWM dimming. <CIT> describes an electronic device with display circuitry including a display timing controller, a backlight driver, a light source and other associated backlight structures.

In <FIG>, circuit <NUM> provides a series connection between a power lead <NUM> supplying a voltage such as from a battery, Vbat, and a field ground lead <NUM> of a current sense resistor <NUM>, a power field effect transistor (FET) <NUM>, and three LEDs <NUM>, <NUM>, and <NUM>. Transistor <NUM> has a drain <NUM>, a gate <NUM>, and a source <NUM>. Transistor <NUM> also presents a gate to drain capacitance Cgd <NUM> and a gate to source capacitance Cgs <NUM>, both indicated in dotted lines.

Integrated circuit controller <NUM> includes gate driver circuit <NUM>, an Idrive output pin <NUM>, and a PWM input pin <NUM>. The Idrive output pin <NUM> is connected to the gate <NUM> of transistor <NUM> by external lead <NUM>. Gate driver <NUM> includes switching circuit <NUM> connected between a power source and a ground and operates under control of a PWM signal received at pin <NUM> to turn on transistor <NUM> by sourcing charge to the gate <NUM> of transistor <NUM> and to turn off transistor <NUM> by removing charge from the gate <NUM>. Turning on the transistor <NUM> conducts a current Iled from the power lead <NUM> through the resistor <NUM> and the LEDs <NUM>, <NUM>, and <NUM> to ground lead <NUM>. Turning off the transistor <NUM> blocks current from the power lead <NUM> through the resistor <NUM> and the LEDs <NUM>, <NUM>, and <NUM> to ground lead <NUM>.

In some applications, such as an automotive application, the resistor <NUM>, power transistor <NUM>, and LEDs <NUM>, <NUM>, and <NUM> are separate from the integrated circuit controller <NUM>. In these applications, a problem exists in turning the current Iled through transistor <NUM> on and off in equal periods of time after state changes in the PWM signals. In large power FET transistors, the capacitances Cgd and Cgs are usually very large.

The current in the power FET transistors depends on the overdrive voltage Vov, which is the voltage difference between VGS and transistor GATE-SOURCE threshold voltage Vth. VOV_10% is the overdrive voltage when LED current reaches <NUM>% of full current, VOV_90% is the overdrive voltage when LED current reaches <NUM>% of full current, VOV_FULL is the overdrive voltage when LED has full current. The turn-on delay time Ton_delay depends on the time need to charge the capacitance Cgs from 0V to Vth+VOV_10%. The turn-off delay time Toff_delay depends on the time need to discharge the capacitance Cgs from VOV_FULL to VOV_90%. Typically the voltage difference between VOV_FULL-VOV_90% is much less than the difference between Vth+VOV_10% and 0V. This means that the turn-on delay time Ton_delay and the Toff_delay time of the transistor <NUM> will be different even with equal Idrive gate currents.

In <FIG>, PWM signal turns on at time <NUM> and turns off at time <NUM>. An Idrive current turns on at time <NUM> and turns off at time <NUM>. Due to the capacitance Cgs <NUM>, the voltage on the gate Vgs increases slowly to turn on the transistor <NUM> at time <NUM>, effecting a Ton_delay between times <NUM> and <NUM>. At time <NUM>, the PWM signal turns off and the Idrive signal removes charge from gate <NUM>, to turn off the transistor <NUM> at time <NUM>, effecting a Toff_delay between times <NUM> and <NUM>.

A constant current Idrive is used to drive the transistor <NUM> in order to control the LED current slew rate during a rising and falling phase. For electromagnetic compatibility (EMC) considerations, a low slew rate (<NUM>~10mA/us) of the LED current is preferred. This means that the drive current cannot be very large. This results in the Ton_delay being long due to the limited drive current and a large Cgs of transistor <NUM> of about several hundred microseconds. The Toff_delay at time is very small, about several microseconds. A big gap between Ton_delay and Toff_delay exists, which causes Iled current duty cycle loss.

The invention relates to a light emitting diode controller integrated circuit according to the appended claim <NUM> and to a process, according to the appended claim <NUM>, of operating such light emitting diode controller integrated circuit. Additional features are disclosed in the dependent claims.

An integrated circuit comprises a clock signal input pin; a pulse width modulated signal input pin; a gate drive signal output pin; and a sense input pin. The integrated circuit is coupled to a series connection between a power lead supplying a voltage and a field ground lead of a sense resistor, a power field effect transistor having a control input, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor and the gate drive signal output pin is coupled to the control input of the transistor.

A process of operating a light emitting diode controller integrated circuit of claim <NUM> is disclosed in claim <NUM>.

In <FIG>, circuit <NUM> includes the series connection between the power lead <NUM> and the field ground lead <NUM> of the current sense resistor <NUM> acting as a sense resistor Rsns, the power field effect transistor (FET) <NUM>, and the three LEDs <NUM>, <NUM>, and <NUM>. Circuit <NUM> also includes an integrated circuit controller <NUM>.

Controller <NUM> has the Idrive or gate output pin <NUM>, the PWM signal input pin <NUM>, an Isn sense input pin <NUM> connected by an external lead 65to between the resistor <NUM> and drain <NUM> of transistor <NUM>, a clock input pin <NUM>, and switching circuit <NUM> having an output connected to the Idrive pin <NUM>.

A detector circuit <NUM> includes a comparator having a non-inverting input connected to a reference voltage Vbat-Vref, an inverting input connected to the Isn sense pin <NUM>, and a Vcomp output.

A compensation timer circuit <NUM> includes an inverter <NUM> having an input connected to the Vcomp output of the comparator <NUM> and an output. An AND gate <NUM> has an input connected to the output of the inverter, an input connected to the PWM pin <NUM>, and an output. An inverter <NUM> has an input connected to the PWM pin <NUM> and an output. A counter <NUM> has an input connected to the clock pin <NUM>, an enable +<NUM> input connected to the output of the And gate <NUM>, an enable -<NUM> input connected to the output of inverter <NUM>, and a count output <NUM> providing a count signal on lead <NUM>.

A drive control circuit <NUM> has an internal logic circuit <NUM> with an input connected to the count output <NUM> on lead <NUM> and an output <NUM>. The logic circuit <NUM> provides a logic <NUM> state output signal if the count signal from counter <NUM> is greater than <NUM> and provides a logic state output signal if the count signal from counter <NUM> equals <NUM>. An OR gate <NUM> has one input connected to the output <NUM> of the logic circuit <NUM>, an input connected to the PWM pin <NUM>, and an enable channel output on lead <NUM>. Switching circuit <NUM> in driver circuit <NUM> has an input connected to lead <NUM> and an output connected to the gate of transistor <NUM> through lead <NUM>.

Also referring to <FIG>, in operation, detector <NUM> detects any voltage drop on external sense resistor Rsns <NUM> to monitor the LED current, Iled, passing though transistor <NUM> to the LEDs <NUM>, <NUM>, and <NUM>. The output of comparator <NUM>, Vcomp, will be a logic <NUM> at time <NUM> when voltage Vgs starts to charge the gate of transistor <NUM> and will be a logic <NUM> at time <NUM> when the gate of transistor <NUM> is fully charged and Iled current starts flowing through the transistor <NUM>.

The counter <NUM> starts increment counting from a start number at the rising edge of the PWM signal on pin <NUM> at time <NUM> and stops counting at a stop number at the rising edge of Vcomp at time <NUM>. The counter <NUM> starts decrement counting from the stop number at the falling edge of PWM at time <NUM> and stops counting when it returns to the start number at time <NUM>. In this example, the increment and decrement counting occurs on the rising edges of the clock signal on clock pin <NUM>. The increment and decrement counting provides a Ton_delay time <NUM> equal to a Toff_delay time <NUM>.

In this example, the start number is zero and the stop number will be determined by the characteristics of the power FET transistor <NUM>. Because the stop count is determined by the characteristics of the external power transistor <NUM> and not by the characteristics of the controller <NUM>, the characteristics of the integrated circuit controller <NUM> do not have to be changed for different power transistors. This provides for wide selection of power transistors.

The driver control output on lead <NUM> is high when the PWM signal goes high and stays high until the counter signal goes to zero. The driver current Idrive charges the gate <NUM> of the external power transistor <NUM> when the output on lead <NUM> is high and discharges the gate <NUM> when the output on lead <NUM> is low.

In operation, the disclosed circuits start a timer at a rising edge of the PWM signal and stop the counter when an external power FET is turned on and is detected by a sensing circuit. This records a Ton_delay. The disclosed circuit postpones a falling edge of drive current Idrive by the Ton_delay to compensate for a Toff delay. With this compensation Ton_delay=Toff_delay, and the current through the LEDs has the same duty cycle as the PWM signal.

As long as the clock signal supplied to the timer is fast enough, the accuracy of LED current duty cycle will be very high. For example, using <NUM> clock signal, the disclosed circuit can achieve +/- <NUM>% tolerance for LED current duty cycle during <NUM>, <NUM>% PWM dimming. Again, the disclosed circuit and process is independent on the external FET transistor type. The disclosed circuit and process is suitable for an external FET with different Cgs, Cds and Vth.

Other implementations of the above example are possible based on the disclosed examples. For example, the detector <NUM> could detect current instead of voltage and could detector a different comparison voltage than Vbat-Vref. The timer <NUM> could use different gating to turn on and turn off the counter <NUM>. The counter <NUM> could start counting from any number and could start decrement counting instead of increment counting. The count signal could be binary count signals on parallel leads instead of being one signal on lead <NUM>. The logic circuit <NUM> could be implemented in any desired gating to attain the desired output signals in response to the count signal or signals. The switching circuit <NUM> can use desired switches, such as transistors that my contribute their own unequal capacitances to the turn on and turn off times of the power transistor.

Claim 1:
A light emitting diode controller integrated circuit (<NUM>) comprising:
(a) a detector circuit (<NUM>) having a sense input (<NUM>) adapted to be coupled to a sense resistor (<NUM>) connected in series with a light emitting diode (<NUM>, <NUM>. <NUM>), a reference voltage input (VBAT-VREF), and a comparator output (Vcomp) of a first comparator (<NUM>);
(b) a compensation timer circuit (<NUM>) having a comparator input of an AND gate (<NUM>) connected to the comparator output (Vcomp) of the first comparator, an input of an inverter (<NUM>) coupled to a pulse width modulated input signal (PWM), a clock signal input (CLK), and a count output (<NUM>);
(c) a driver control circuit (<NUM>) having an input connected to the count output (<NUM>), an input coupled to the pulse width modulated input signal (PWM), and a driver output; and
(d) a driver circuit (<NUM>) having an input connected with the driver output and having a control output signal adapted to be coupled to a control input of a power transistor (<NUM>) connected in series with the light emitting diode (<NUM>, <NUM>, <NUM>); and
characterized in that the compensation timer circuit (<NUM>) includes a gating circuit having the comparator input of the AND gate (<NUM>), the input of the inverter (<NUM>) coupled to the pulse width modulated input signal (PWM), an increment count output, and a decrement count output, and the compensation timer circuit (<NUM>) includes a counter (<NUM>) having an increment input connected to the increment output, a decrement input connected to the decrement output, the clock signal input, and the count output, the driver control circuit (<NUM>) including a logic circuit having the input connected to the count output (<NUM>), the input coupled to the pulse width modulated input signal (PWM), and the driver output.