Patent Description:
A wireless communication system may use error correcting codes to facilitate reliable transmission of digital messages over noisy channels. A block code is one type of error correcting code. In a typical block code, an information message or sequence is split up into blocks, and an encoder at the transmitting device mathematically adds redundancy to the information message. Exploitation of this redundancy in the encoded information message improves the reliability of the message, enabling correction for bit errors that may occur due to the noise. That is, a decoder at the receiving device can take advantage of the redundancy to reliably recover the information message even though bit errors may occur, in part, due to the addition of noise by the channel. Examples of error correcting block codes include Hamming codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and turbo codes among others. Many existing wireless communication networks utilize such block codes, such as 3GPP LTE networks, which utilize turbo codes, and IEEE <NUM>. 11n Wi-Fi networks.

To further improve communication performance (e.g., in wireless communication systems), a retransmission scheme such a hybrid automatic repeat request (HARQ) scheme may be used. In a HARQ scheme, coded blocks are retransmitted if the first transmission is not decoded correctly. In some cases, several retransmissions may be needed to achieve a desired level of communication performance. As a result, the overhead associated with a HARQ scheme may be relatively high. Accordingly, there is a need for error correction techniques that can provide a high level of performance (e.g., with low overhead). Prior art document <CIT> relates to a system and method for transmitting high speed data on fixed rate and for variable rate channels. The system and method provides the flexibility of adjusting the data rate, the coding rate, and the nature of individual retransmissions. Further, the system and method supports partial soft combining of retransmitted data with previously transmitted data, supports parity bit selection for successive retransmissions, and supports various combinations of data rate variations, coding rate variations, and partial data transmissions. Prior art document <CIT> relates to a communication method in a receiving node in a wireless communication system including receiving, at a receiving node, a first coded message block that includes a plurality of parts distributed over a plurality of components. The method further includes detecting a decoding error associated with decoding the received first coded message block and, in response to detecting the decoding error, identifying a part of the first coded message block for which retransmission will be requested and a suggested retransmission setting. The suggested retransmission setting includes one or more of a component selection setting, a link adaptation setting, a power control setting, and a scheduling setting. The method also includes feeding back to the sending node feedback information indicating that the first coded message block could not be correctly decoded. The feedback information indicates the identified part of the first coded message block and the suggested retransmission settings.

The claimed invention is defined by the independent claims. Further embodiments of the claimed invention are described in the dependent claims.

These and other aspects of the disclosure will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and implementations of the disclosure will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific implementations of the disclosure in conjunction with the accompanying figures. While features of the disclosure may be discussed relative to certain implementations and figures below, all implementations of the disclosure can include one or more of the advantageous features discussed herein. In other words, while one or more implementations may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various implementations of the disclosure discussed herein. In similar fashion, while certain implementations may be discussed below as device, system, or method implementations it should be understood that such implementations can be implemented in various devices, systems, and methods.

The accompanying drawings are presented to aid in the description of aspects of the disclosure and are provided solely for illustration of the aspects and not limitations thereof.

Various aspects of the disclosure relate to encoding and decoding techniques. In some aspects, the disclosure relates to decoding for Polar codes with HARQ. For example, if a transmitter's first transmission fails, the transmitter retransmits information bits associated with a lower quality channel. The receiver decodes this information using an SC list (SCL) decoder. For example, the receiver may use the retransmitted decoded bits to decode the signal received in the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. As another example, soft-combining of the decoded retransmitted bits and the original corresponding (low quality channel) bits may be used to decode the signal received in the first transmission. In various implementations, cyclic redundancy check (CRC) bits may be used, not used, or split (e.g., equally) between the first transmission and the second transmission. In some aspects, the disclosed techniques for list decoding of Polar codes with HARQ may improve communication performance and reduce the CRC overhead.

Moreover, alternate configurations may be devised without departing from the scope of the disclosure. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.

For example, the 3rd Generation Partnership Project (3GPP) is a standards body that defines several wireless communication standards for networks involving the evolved packet system (EPS), frequently referred to as long-term evolution (LTE) networks. Evolved versions of the LTE network, such as a fifthgeneration (<NUM>) network, may provide for many different types of services or applications, including but not limited to web browsing, video streaming, VoIP, mission critical applications, multi-hop networks, remote operations with real-time feedback (e.g., tele-surgery), etc. Thus, the teachings herein can be implemented according to various network technologies including, without limitation, <NUM> technology, fourth generation (<NUM>) technology, third generation (<NUM>) technology, and other network architectures. Also, the techniques described herein may be used for a downlink, an uplink, a peer-to-peer link, or some other type of link.

The actual telecommunication standard, network architecture, and/or communication standard used will depend on the specific application and the overall design constraints imposed on the system. For purposes of illustration, the following may describe various aspects in the context of a <NUM> system and/or an LTE system. It should be appreciated, however, that the teachings herein may be used in other systems as well. Thus, references to functionality in the context of <NUM> and/or LTE terminology should be understood to be equally applicable to other types of technology, networks, components, signaling, and so on.

<FIG> illustrates an example of a wireless communication system <NUM> where a user equipment (UE) can communicate with other devices via wireless communication signaling. For example, a first UE <NUM> and a second UE <NUM> may communicate with a transmit receive point (TRP) <NUM> using wireless communication resources managed by the TRP <NUM> and/or other network components (e.g., a core network <NUM>, an internet service provider (ISP) <NUM>, peer devices, and so on). In some implementations, one or more of the components of the system <NUM> may communicate with each other directedly via a device-to-device (D2D) link <NUM> or some other similar type of direct link.

Communication of information between two or more of the components of the system <NUM> may involve encoding the information. For example, the TRP <NUM> may encode data or control information that the TRP <NUM> sends to the UE <NUM> or the UE <NUM>. As another example, the UE <NUM> may encode data or control information that the ZiE <NUM> sends to the TRP <NUM> or the UE <NUM>. The encoding may involve block coding such as Polar coding. In accordance with the teachings herein, one or more of the UE <NUM>, the UE <NUM>, the TRP <NUM>, or some other component of the system <NUM> may include an encoder and/or decoder <NUM> that may, for example, optionally include CRC from a first transmission in a second transmission and/or decode a first transmission based on a second transmission.

The components and links of the wireless communication system <NUM> may take different forms in different implementations. For example, and without limitation, UEs may be cellular devices, Internet of Things (IoT) devices, cellular IoT (CloT) devices, LTE wireless cellular devices, machine-type communication (MTC) cellular devices, smart alarms, remote sensors, smart phones, mobile phones, smart meters, personal digital assistants (PDAs), personal computers, mesh nodes, and tablet computers.

In some aspects, a TRP may refer to a physical entity that incorporates radio head functionality for a particular physical cell. In some aspects, the TRP may include <NUM> new radio (NR) functionality with an air interface based on orthogonal frequency division multiplexing (OFDM). NR may support, for example and without limitation, enhanced mobile broadband (eMBB), mission-critical services, and wide-scale deployment of IoT devices. The functionality of a TRP may be similar in one or more aspects to (or incorporated into) the functionality of a CIoT base station (C-BS), a NodeB, an evolved NodeB (eNodeB), radio access network (RAN) access node, a radio network controller (RNC), a base station (BS), a radio base station (RBS), a base station controller (BSC), a base transceiver station (BTS), a transceiver function (TF), a radio transceiver, a radio router, a basic service set (BSS), an extended service set (ESS), a macro cell, a macro node, a Home eNB (HeNB), a femto cell, a femto node, a pico node, or some other suitable entity. In different scenarios (e.g., NR, LTE, etc.), a TRP may be referred to as a gNodeB (gNB), an eNB, a base station, or referenced using other terminology.

Various types of network-to-device links and D2D links may be supported in the wireless communication system <NUM>. For example, D2D links may include, without limitation, machine-to-machine (M2M) links, MTC links, vehicle-to-vehicle (V2V) links, and vehicle-to-anything (V2X) links. Network-to-device links may include, without limitation, uplinks (or reverse links), downlinks (or forward links), and vehicle-to-network (V2N) links.

<FIG> is a schematic illustration of a wireless communication system <NUM> that includes a first wireless communication device <NUM> and a second wireless communication device <NUM> that may use the teachings herein. In some implementations, the first wireless communication device <NUM> or the second wireless communication device <NUM> may correspond to the UE <NUM>, the UE <NUM>, the TRP <NUM>, or some other component of <FIG>.

In the illustrated example, the first wireless communication device <NUM> transmits a message over a communication channel <NUM> (e.g., a wireless channel) to the second wireless communication device <NUM>. One issue in such a scheme that may be addressed to reliably communicate the message is to take into account noise <NUM> introduced in the communication channel <NUM>.

Block codes or error correcting codes are frequently used to provide reliable transmission of messages over noisy channels. In a typical block code, an information message or sequence from an information source <NUM> at the first (transmitting) wireless communication device <NUM> is split up into blocks, each block having a length of K bits. An encoder <NUM> mathematically adds redundancy to the information message, resulting in codewords having a length of N, where N > K. Here, the code rate R is the ratio between the message length and the block length (i.e., R = K / N). Exploitation of this redundancy in the encoded information message is a key to reliably receiving the transmitted message at the second (receiving) wireless communication device <NUM>, whereby the redundancy enables correction for bit errors that may occur due to the noise <NUM> imparted on the transmitted message. That is, a decoder <NUM> at the second (receiving) wireless communication device <NUM> can take advantage of the redundancy to reliably recover the information message provided to an information sink <NUM> even though bit errors may occur, in part, due to the addition of the noise <NUM> in the channel <NUM>.

Many examples of such error correcting block codes are known to those of ordinary skill in the art, including Hamming codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and turbo codes, among others. Some existing wireless communication networks utilize such block codes. For example, 3GPP LTE networks may use turbo codes. However, for future networks, a new category of block codes, called Polar codes, presents a potential opportunity for reliable and efficient information transfer with improved performance relative to other codes.

The disclosure relates in some aspects, to the use of hybrid automatic repeat request (HARQ) with Polar codes (described below). For example, the encoder <NUM> may include a module for encoding a message for a first transmission <NUM>, where the message may include cyclic redundancy check (CRC) information. A transmitter (not shown) of the first wireless communication device <NUM> sends the first transmission to the second wireless communication device <NUM>.

A receiver (not shown) of the second wireless communication device <NUM> receives the first transmission. If the decoder <NUM> (e.g., a module for decoding the first transmission <NUM>) is not able to correctly decode the first transmission, the second wireless communication device <NUM> may send NAK feedback (not shown) to the first wireless communication device <NUM>.

In response to NAK feedback, the encoder <NUM> may encode a message for a second transmission (which may be referred to as a retransmission), where the message optionally includes at least a portion of the CRC information for the first transmission. To this end, the encoder <NUM> includes a module for encoding a message for a second transmission <NUM>. The first wireless communication device <NUM> then sends the second transmission to the second wireless communication device <NUM>.

The decoder <NUM> also includes a module for decoding the second transmission <NUM>. In some aspects, the decoding (e.g., list decoding) for the first transmission (performed by the module for decoding the first transmission <NUM>) may be based on the result of the decoding (e.g., list decoding) for the second transmission. For example, the decoding for the first transmission may use one or more candidate vectors generated by the decoding for the second transmission.

Turning now to <FIG> and <FIG>, several aspects of Polar codes and HARQ schemes will be described in more detail. It should be appreciated that these examples are presented for purposes of explanation and that the teachings herein may be applicable to other types of coding and retransmission schemes.

Polar codes are linear block error correcting codes where channel polarization is generated with a recursive algorithm that defines polar codes. Polar codes are the first explicit codes that achieve the channel capacity of symmetric binary-input discrete memoryless channels. That is, polar codes achieve the channel capacity (the Shannon limit) or the theoretical upper bound on the amount of error-free information that can be transmitted on a discrete memoryless channel of a given bandwidth in the presence of noise. This capacity can be achieved with a simple successive cancellation (SC) decoder.

A typical encoder structure <NUM> of Polar codes is depicted in <FIG>. The Polar code sub-channels are allocated into two subsets, best sub-channels and worst sub-channels, based on the corresponding error probability associated with each subchannel. The information bits <NUM> are then put on the best sub-channels while frozen bits <NUM> (with zero values) are put on the worst sub-channels. A bit-reversal permutation <NUM> is used to provide the output bits of the decoder in a desired sequence. The encoding is performed after multiplying by a Hadamard matrix <NUM>. The generator matrices of Polar codes are made up of the rows of a Hadamard matrix. The rows corresponding to low error probabilities of an SC decoder are selected for information bits while the remaining rows are for frozen bits.

It may thus be seen that the Polar codes are one type of block codes (N, K), where N is the codeword length and K is the number of information bits. With polar codes, the codeword length N is a power-of-two (e.g., <NUM>, <NUM>, <NUM>, etc.) because the original construction of a polarizing matrix is based on the Kronecker product of <MAT>.

HARQ incremental redundancy (HARQ-IR) schemes are widely used in wireless communication systems to improve transmission efficiency. In a HARQ scheme, the coded blocks will be retransmitted if the first transmission is not decoded correctly. The maximum number of transmissions in a typical application is <NUM>. However, some applications may use a different retransmission limit.

An example of a HARQ-IR scheme <NUM> for Polar codes is depicted in <FIG>. For simplification, only a first transmission and a second transmission (a retransmission) are shown. In the µ domain <NUM> of the first transmission, the information bits are allocated into two sub-blocks denoted as A and B. The F block is for frozen bits with a value of zero. After bit-reversal permutation and encoding, a coded block in the X domain is obtained. If the first transmission (1TX) <NUM> is decoded correctly at the receiver, the transmission ends.

However, if the first transmission (1TX) <NUM> is not decoded correctly, the transmitter will generate a new codeword in the µ domain <NUM> with B information bits. After bit-reversal permutation and encoding, the transmitter invokes a second transmission (2TX) <NUM> to send a corresponding coded block in the X2 domain. If the receiver does not decode the B information for the second transmission (2TX) <NUM> correctly, a third transmission may be invoked, and so on.

If the B information in the second transmission (2TX) <NUM> is decoded correctly by the receiver, the B information in first transmission will be set as frozen bits and the A information in first transmission will be decoded accordingly. In this case, this is equivalent to obtaining the low rate for the A information in the first transmission.

From a performance standpoint, the algorithm of <FIG> may be equivalent to existing (e.g., non-Polar coding) HARQ-IR schemes in terms of coding gain. In <FIG>, the equivalent coding rate after two transmissions is half of the first transmission with a block size of the first transmission.

<FIG> depicts an example structure <NUM> of a CRC-aided SCL (CA-SCL) decoder. For simplification, a list size of <NUM> is assumed and all bits are unfrozen. Other configurations (e.g., different list sizes) could be used in other implementations. In the path structure <NUM> of <FIG>, there are at most <NUM> nodes with paths that continue downward at each level. At the initial stage, the first unfrozen bit can be either <NUM> or <NUM> and two paths are obtained. Then, the second unfrozen bit can be either <NUM> or <NUM> and two paths are generated for each. Thus, there are a total of <NUM> paths and, since there are not more than <NUM> paths, it is not necessary to prune the paths. However, there are <NUM> decoding paths <NUM> for the third unfrozen bits. Thus, the <NUM> paths are pruned into the <NUM> most promising paths since the list size is set to <NUM>. For the following unfrozen bits, the <NUM> active paths will continue to double to <NUM> paths and the <NUM> paths will be pruned to the <NUM> best paths again. In this way, there are only <NUM> active paths <NUM> which are kept to the last unfrozen bits. Finally, the <NUM> candidate paths <NUM> will be sorted <NUM> and the best path will be selected <NUM> as a decision for the SCL algorithm. To further improve the performance, CRC pruning <NUM> can be used whereby CRC is used to check the candidate paths, and the path with CRC passing will be selected <NUM>. In this algorithm of CA-SCL, CRC may be checked from the best candidate paths to the worse candidate paths.

The disclosure relates in some aspects to a decoding algorithm that uses list decoding for Polar codes with HARQ. Three techniques are described. The first two techniques are for single CRC while the third technique is for split CRC. For simplification, the following describes a scenario with the maximum number of transmissions equal to <NUM>. It should be appreciated, however, that the techniques taught herein are applicable to different numbers of transmissions (e.g., <NUM>, <NUM>, or more).

An example decoder <NUM> using single CRC for Polar codes with HARQ is depicted in <FIG>. In the decoder <NUM>, the bits of a first received transmission (1TX) include a first subset of bits A <NUM>, a second subset of bits B <NUM>, frozen bits F <NUM>, and CRC bits <NUM>. The bits of a received second transmission (2TX) include the second subset of bits B <NUM>' and frozen bits F <NUM>. The CRC bits <NUM> are included in the first transmission (1TX) but not in the second transmission (2TX) to reduce the CRC overhead.

To decode the first transmission, the decoder <NUM> uses a CRC-aided SCL decoding algorithm <NUM>. If the result is not correct, a second transmission (e.g., a retransmission) will be initiated (e.g., via a HARQ process). In this case, a transmitter (not shown in <FIG>) will encode and transmit the information bits of block B for the second transmission (received at the decoder <NUM> as block B <NUM>').

The decoder <NUM> uses SCL decoding <NUM> to decode the received signal for the second transmission. The output L candidate vectors <NUM> for the bits of block B <NUM>' are then provided to the decoding algorithm <NUM> for final decoding of the signal received in the first transmission. For example, the bits of block B <NUM> for the first transmission may be initialized with <NUM> (e.g., replaced with) the list of L candidate vectors <NUM> from the second transmission. For each candidate vector, CRC may be applied for pruning <NUM> the candidate paths obtained in the SCL decoder. Via this process, the bits of block A may be recovered such that the signal received in the first transmission is thereby decoded.

An example decoder <NUM> that uses single CRC for systematic Polar codes with HARQ is depicted in <FIG>. In the decoder <NUM>, the bits of a first received transmission (1TX) include a first subset of bits A <NUM>, a second subset of bits B <NUM>, frozen bits F <NUM>, and CRC bits <NUM>. The bits of a received second transmission (2TX) include the second subset of bits B <NUM>' and frozen bits F <NUM>. The CRC bits <NUM> are included in the first transmission (1TX) but not in the second transmission (2TX) to reduce the CRC overhead.

Because a systematic code is generated in both the first transmission and the second transmission, the decoder <NUM> can use soft-combining <NUM> of the log-likelihood ratio (LLR) of the bits in block B of both the first transmission (block B <NUM>) and the second transmission (block B <NUM>'). The decoder <NUM> uses SCL decoding <NUM> to decode the combined received signal for the second transmission (after the soft-combining). The performance of the SCL decoding <NUM> may thus be improved by the soft-combining. The output L candidate vectors <NUM> for the bits in B are then provided to the decoding algorithm <NUM> for final decoding of the signal received in the first transmission. For example, each bit in B in the first transmission may be initialized <NUM> with the L candidate list from the second transmission. For each candidate vector, CRC will be applied for pruning <NUM> the candidate paths obtained in the SCL decoder. Via this process, the bits of block A may be recovered such that the signal received in the first transmission is thereby decoded.

An example decoder <NUM> that uses split CRC for Polar codes with HARQ is depicted in <FIG>. In this case, CRC bits are split (e.g., equally) between a first subset of bits A <NUM> and a second subset of bits B <NUM>. Thus, in the decoder <NUM>, the bits of a first received transmission (1TX) include the first subset of bits A <NUM>, the second subset of bits B <NUM>, frozen bits F <NUM>, CRC1 808A of the first subset of bits A <NUM>, and CRC2 808B of the second subset of bits B <NUM>. For the first transmission, the decoder <NUM> applies a CRC-aided SCL decoding algorithm <NUM> that uses CRC1 808A and CRC2 808B. If the result is not correct, the second transmission will be requested (e.g., via a HARQ process). Consequently, the transmitter (not shown in <FIG>) will encode and transmit the information bits of block B (received at the decoder <NUM> as block B <NUM>'). Because the bits of CRC2 are included in the second transmission in this case (received at the decoder <NUM> as CRC2 808B'), CRC2 bits can be used to prune <NUM> the candidate paths from the SCL decoding algorithm <NUM> for the second transmission. If no candidate path passes the CRC2 check, the best path will be selected as the hard decision <NUM> for block B. This path will then be provided to the decoding algorithm <NUM> for final decoding of the signal received in first transmission. In this case, the bits in B in the first transmission will be taken as frozen bits <NUM> when the received signal in first transmission is decoded. In addition, the CRC1 will be applied for pruning the candidate paths <NUM> obtained in SCL decoder for the first transmission. Via this process, the bits of block A may be recovered such that the signal received in the first transmission is thereby decoded.

<FIG> depicts an example encoder <NUM> that uses HARQ with Polar Codes in accordance with the teachings herein. In some aspects, the encoder <NUM> may be used to provide the encoded information used by the decoder <NUM> of <FIG>. In the µ domain <NUM>, the information bits are denoted as D and the frozen bits with a value of zero are denoted as F. Thus, the block D in <FIG> may generally correspond to the A and B blocks of <FIG>. Systematic Polar encoding <NUM> of these bits creates a so-called mother code <NUM> that includes a block denoted as D (encoded data) and a block denoted as P <NUM> (encoded parity check bits). Thus, the mother code <NUM> is a systematic Polar code in this example. Coding and CRC <NUM> are then applied to provide a set of bits for a first transmission <NUM>. Based on the selected coding rate, some of the bits of the mother code <NUM> are punctured. The resulting first transmission <NUM> thus corresponds to the first transmission (1TX) described in <FIG>.

If the decoder (e.g., the decoder <NUM> of <FIG>) does not successfully decode the first transmission <NUM> (e.g., a NAK <NUM> is received at the encoder <NUM>), a second transmission (e.g., a retransmission) is invoked. Coding and CRC <NUM> are then applied to the bits of block B from the first transmission <NUM> to provide a set of encoded bits for the second transmission <NUM> (e.g., a retransmission).

<FIG> is an illustration of an apparatus <NUM> that may provide decoding according to one or more aspects of the disclosure. The apparatus <NUM> could embody or be implemented within a UE, a TRP, a gNB, a base station, or some other type of device that uses decoding. In various implementations, the apparatus <NUM> could embody or be implemented within an access terminal, an access point, or some other type of device. In various implementations, the apparatus <NUM> could embody or be implemented within a mobile phone, a smart phone, a tablet, a portable computer, a server, a network entity, a personal computer, a sensor, an alarm, a vehicle, a machine, an entertainment device, a medical device, or any other electronic device having circuitry.

The apparatus <NUM> includes a communication interface <NUM> (e.g., at least one transceiver), a storage medium <NUM>, a user interface <NUM>, a memory device <NUM>, and a processing circuit <NUM> (e.g., at least one processor). These components can be coupled to and/or placed in electrical communication with one another via a signaling bus or other suitable component, represented generally by the connection lines in <FIG>. The signaling bus may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The signaling bus links together various circuits such that each of the communication interface <NUM>, the storage medium <NUM>, the user interface <NUM>, and the memory device <NUM> are coupled to and/or in electrical communication with the processing circuit <NUM>. The signaling bus may also link various other circuits (not shown) such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The communication interface <NUM> may be adapted to facilitate wireless communication of the apparatus <NUM>. For example, the communication interface <NUM> may include circuitry and/or programming adapted to facilitate the communication of information bi-directionally with respect to one or more communication devices in a network. Thus, in some implementations, the communication interface <NUM> may be coupled to one or more antennas <NUM> for wireless communication within a wireless communication system. In some implementations, the communication interface <NUM> may be configured for wire-based communication. For example, the communication interface <NUM> could be a bus interface, a send/receive interface, or some other type of signal interface including drivers, buffers, or other circuitry for outputting and/or obtaining signals (e.g., outputting signal from and/or receiving signals into an integrated circuit). The communication interface <NUM> can be configured with one or more standalone receivers and/or transmitters, as well as one or more transceivers. In the illustrated example, the communication interface <NUM> includes a transmitter <NUM> and a receiver <NUM>.

The memory device <NUM> may represent one or more memory devices. As indicated, the memory device <NUM> may maintain coding-related information <NUM> along with other information used by the apparatus <NUM>. In some implementations, the memory device <NUM> and the storage medium <NUM> are implemented as a common memory component. The memory device <NUM> may also be used for storing data that is manipulated by the processing circuit <NUM> or some other component of the apparatus <NUM>.

The storage medium <NUM> may represent one or more computer-readable, machine-readable, and/or processor-readable devices for storing programming, such as processor executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. The storage medium <NUM> may also be used for storing data that is manipulated by the processing circuit <NUM> when executing programming. The storage medium <NUM> may be any available media that can be accessed by a general purpose or special purpose processor, including portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying programming.

By way of example and not limitation, the storage medium <NUM> may include a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The storage medium <NUM> may be embodied in an article of manufacture (e.g., a computer program product). By way of example, a computer program product may include a computer-readable medium in packaging materials. In view of the above, in some implementations, the storage medium <NUM> may be a nontransitory (e.g., tangible) storage medium.

The storage medium <NUM> may be coupled to the processing circuit <NUM> such that the processing circuit <NUM> can read information from, and write information to, the storage medium <NUM>. That is, the storage medium <NUM> can be coupled to the processing circuit <NUM> so that the storage medium <NUM> is at least accessible by the processing circuit <NUM>, including examples where at least one storage medium is integral to the processing circuit <NUM> and/or examples where at least one storage medium is separate from the processing circuit <NUM> (e.g., resident in the apparatus <NUM>, external to the apparatus <NUM>, distributed across multiple entities, etc.).

Programming stored by the storage medium <NUM>, when executed by the processing circuit <NUM>, causes the processing circuit <NUM> to perform one or more of the various functions and/or process operations described herein. For example, the storage medium <NUM> may include operations configured for regulating operations at one or more hardware blocks of the processing circuit <NUM>, as well as to utilize the communication interface <NUM> for wireless communication utilizing their respective communication protocols. In some aspects, the storage medium <NUM> may be a nontransitory computer-readable medium storing computer-executable code, including code to perform operations as described herein.

The processing circuit <NUM> is generally adapted for processing, including the execution of such programming stored on the storage medium <NUM>. As used herein, the terms "code" or "programming" shall be construed broadly to include without limitation instructions, instruction sets, data, code, code segments, program code, programs, programming, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

The processing circuit <NUM> is arranged to obtain, process and/or send data, control data access and storage, issue commands, and control other desired operations. The processing circuit <NUM> may include circuitry configured to implement desired programming provided by appropriate media in at least one example. For example, the processing circuit <NUM> may be implemented as one or more processors, one or more controllers, and/or other structure configured to execute executable programming. Examples of the processing circuit <NUM> may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may include a microprocessor, as well as any conventional processor, controller, microcontroller, or state machine. The processing circuit <NUM> may also be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, an ASIC and a microprocessor, or any other number of varying configurations. These examples of the processing circuit <NUM> are for illustration and other suitable configurations within the scope of the disclosure are also contemplated.

According to one or more aspects of the disclosure, the processing circuit <NUM> may be adapted to perform any or all of the features, processes, functions, operations and/or routines for any or all of the apparatuses described herein. For example, the processing circuit <NUM> may be configured to perform any of the steps, functions, and/or processes described with respect to <FIG> and <FIG>. As used herein, the term "adapted" in relation to the processing circuit <NUM> may refer to the processing circuit <NUM> being one or more of configured, used, implemented, and/or programmed to perform a particular process, function, operation and/or routine according to various features described herein.

The processing circuit <NUM> may be a specialized processor, such as an application specific integrated circuit (ASIC) that serves as a means for (e.g., structure for) carrying out any one of the operations described in conjunction with <NUM> - <NUM> and <NUM> - <NUM>. The processing circuit <NUM> may serve as one example of a means for transmitting and/or a means for receiving. In various implementations, the processing circuit <NUM> may provide and/or incorporate the functionality of the second wireless communication device <NUM> (e.g., the decoder <NUM>) of <FIG> or the decoder <NUM> of <FIG>.

According to at least one example of the apparatus <NUM>, the processing circuit <NUM> may include one or more of a circuit/module for decoding <NUM>, a circuit/module for receiving <NUM>, a circuit/module for communicating <NUM>, a circuit/module for soft-combining <NUM>, or a circuit/module for pruning <NUM>. In various implementations, the circuit/module for decoding <NUM>, the circuit/module for receiving <NUM>, the circuit/module for communicating <NUM>, the circuit/module for soft-combining <NUM>, or the circuit/module for pruning <NUM> may provide and/or incorporate, at least in part, the functionality described above for the second wireless communication device <NUM> (e.g., the decoder <NUM>) of <FIG> or the decoder <NUM> of <FIG>.

As mentioned above, programming stored by the storage medium <NUM>, when executed by the processing circuit <NUM>, causes the processing circuit <NUM> to perform one or more of the various functions and/or process operations described herein. For example, the programming may cause the processing circuit <NUM> to perform the various functions, steps, and/or processes described herein with respect to <FIG> and <FIG>. As shown in <FIG>, the storage medium <NUM> may include one or more of code for decoding <NUM>, code for receiving <NUM>, code for communicating <NUM>, code for soft-combining <NUM>, or code for pruning <NUM>. In various implementations, the code for decoding <NUM>, the code for receiving <NUM>, the code for communicating <NUM>, the code for soft-combining <NUM>, or the code for pruning -<NUM> may be executed or otherwise used to provide the functionality described herein for the circuit/module for decoding <NUM>, the circuit/module for receiving <NUM>, the circuit/module for communicating <NUM>, the circuit/module for soft-combining <NUM>, or the circuit/module for pruning <NUM>.

The circuit/module for decoding <NUM> may include circuitry and/or programming (e.g., code for decoding <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, decoding information. In some aspects, the circuit/module for decoding <NUM> (e.g., a means for decoding) may correspond to, for example, a processing circuit.

In some aspects, the circuit/module for decoding <NUM> may execute a decoding algorithm. For example, the circuit/module for decoding <NUM> may perform a list decoding algorithm. In some aspects, the circuit/module for decoding <NUM> may perform the encoding operations described herein conjunction with <FIG>. The circuit/module for decoding <NUM> may then output the resulting decoded information (e.g., to the circuit/module for pruning <NUM>, the memory device <NUM>, the communication interface <NUM>, or some other component) or use the results internally.

The circuit/module for receiving <NUM> may include circuitry and/or programming (e.g., code for receiving <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, receiving information. In some scenarios, the circuit/module for receiving <NUM> may obtain information (e.g., from the communication interface <NUM>, the memory device, or some other component of the apparatus <NUM>) and process (e.g., decode) the information. In some scenarios (e.g., if the circuit/module for receiving <NUM> is or includes an RF receiver), the circuit/module for receiving <NUM> may receive information directly from a device that transmitted the information. In either case, the circuit/module for receiving <NUM> may output the obtained information to another component of the apparatus <NUM> (e.g., the circuit/module for decoding <NUM>, the memory device <NUM>, or some other component).

The circuit/module for receiving <NUM> (e.g., a means for receiving) may take various forms. In some aspects, the circuit/module for receiving <NUM> may correspond to, for example, an interface (e.g., a bus interface, a /receive interface, or some other type of signal interface), a communication device, a transceiver, a receiver, or some other similar component as discussed herein. In some implementations, the communication interface <NUM> includes the circuit/module for receiving <NUM> and/or the code for receiving <NUM>. In some implementations, the circuit/module for receiving <NUM> and/or the code for receiving <NUM> is configured to control the communication interface <NUM> (e.g., a transceiver or a receiver) to receive information.

The circuit/module for communicating <NUM> may include circuitry and/or programming (e.g., code for communicating <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, communicating information. In some implementations, the communication involves receiving the information. In some implementations, the communication involves sending (e.g., transmitting) the information.

In some implementations where the communicating involves receiving information, the circuit/module for communicating <NUM> receives information (e.g., from the communication interface <NUM>, the receiver <NUM>, the memory device <NUM>, some other component of the apparatus <NUM>, or some other device), processes (e.g., decodes) the information, and outputs the information to another component of the apparatus <NUM> (e.g., the circuit/module for decoding <NUM>, the memory device <NUM>, or some other component). In some scenarios (e.g., if the circuit/module for communicating <NUM> includes a receiver), the communicating involves the circuit/module for communicating <NUM> receiving information directly from a device that transmitted the information (e.g., via radio frequency signaling or some other type of signaling suitable for the applicable communication medium).

In some implementations where the communicating involves sending information, the circuit/module for communicating <NUM> obtains information (e.g., from the memory device <NUM> or some other component of the apparatus <NUM>), processes (e.g., encodes for transmission) the information, and outputs the processed information. In some scenarios, the communicating involves sending the information to another component of the apparatus <NUM> (e.g., the transmitter <NUM>, the communication interface <NUM>, or some other component) that will transmit the information to another device. In some scenarios (e.g., if the circuit/module for communicating <NUM> includes a transmitter), the communicating involves the circuit/module for communicating <NUM> transmitting the information directly to another device (e.g., the ultimate destination) via radio frequency signaling or some other type of signaling suitable for the applicable communication medium.

The circuit/module for communicating <NUM> (e.g., a means for communicating) may take various forms. In some aspects, the circuit/module for communicating <NUM> may correspond to, for example, an interface (e.g., a bus interface, a send/receive interface, or some other type of signal interface), a communication device, a transceiver, a transmitter, a receiver, or some other similar component as discussed herein. In some implementations, the communication interface <NUM> includes the circuit/module for communicating <NUM> and/or the code for communicating <NUM>. In some implementations, the circuit/module for communicating <NUM> and/or the code for communicating <NUM> is configured to control the communication interface <NUM> (e.g., a transceiver, a receiver, or a transmitter) to communicate the information.

The circuit/module for soft-combining <NUM> may include circuitry and/or programming (e.g., code for soft-combining <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, soft-combining information. In some aspects, the circuit/module for soft-combining <NUM> (e.g., a means for soft-combining) may correspond to, for example, a processing circuit.

In some aspects, the circuit/module for soft-combining <NUM> may execute a soft-combining algorithm. For example, the circuit/module for soft-combining <NUM> may perform the soft-combining operations described herein conjunction with <FIG>. The circuit/module for soft-combining <NUM> may then output the resulting information (e.g., to the circuit/module for decoding <NUM>, the memory device <NUM>, the communication interface <NUM>, or some other component).

The circuit/module for pruning <NUM> may include circuitry and/or programming (e.g., code for pruning <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, soft-combining information. In some aspects, the circuit/module for pruning <NUM> (e.g., a means for pruning) may correspond to, for example, a processing circuit.

In some aspects, the circuit/module for pruning <NUM> may execute a pruning algorithm. For example, the circuit/module for pruning <NUM> may perform the pruning operations described herein conjunction with <FIG>. The circuit/module for pruning <NUM> may then output the resulting information (e.g., to the circuit/module for decoding <NUM>, the memory device <NUM>, the communication interface <NUM>, or some other component).

<FIG> illustrates a process <NUM> for communication in accordance with some aspects of the disclosure. The process <NUM> may take place within a processing circuit (e.g., the processing circuit <NUM> of <FIG>), which may be located in an access terminal, a base station, or some other suitable apparatus (e.g., that includes a decoder). Of course, in various aspects within the scope of the disclosure, the process <NUM> may be implemented by any suitable apparatus capable of supporting signaling-related operations.

At block <NUM>, an apparatus (e.g., a device that includes a decoder) decodes a first set of bits from a first transmission. In some aspects, the first set of bits may correspond to a first subset of bits and a second subset of bits. In some aspects, the bits may be Polar coded bits. In some aspects, the bits may be systematic Polar coded bits.

In some implementations, the circuit/module for decoding <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for decoding <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus receives a second transmission associated with the first transmission, the second transmission including a second set of bits without cyclic redundancy check (CRC) information, and the second set of bits corresponding to the second subset of bits.

In some implementations, the circuit/module for receiving <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for receiving <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus decodes the second set of bits. The bits may take different forms in different implementations. In some aspects, the first set of bits and the second set of bits may be systematic coded bits. In some aspects, the first set of bits and the second set of bits may be Polar coded bits.

At block <NUM>, the apparatus decodes the first set of bits using the decoded second set of bits.

The decoding may take different forms in different implementations. In some aspects, the decoding may include list decoding.

In some aspects, the decoding of the first set of bits may involve decoding the second subset of bits; and the decoding of the first set of bits using the decoded second set of bits may include using candidate vectors from the decoding of the second set of bits instead of candidate vectors from the decoding of the second subset of bits.

In some aspects, the decoding of the first set of bits may involve generating a decoded second subset of bits; the decoding of the second set of bits may involve generating a decoded second set of bits; and the decoding of the first set of bits using the decoded second set of bits may include: soft-combining the decoded second subset of bits and the decoded second set of bits to generate soft-combined bits, and recovering the first set of bits based on the soft-combined bits. In some aspects, the soft-combining may include generating candidate vectors; and the decoding of the first set of bits using the decoded second set of bits may be based on the candidate vectors.

In some aspects, a process may include any combination of the aspects described above.

At block <NUM>, an apparatus (e.g., a device that includes a decoder) decodes a first set of bits from a first transmission. In some aspects, the first set of bits may correspond to a first subset of bits and to a second subset of bits that includes cyclic redundancy check (CRC) information. In some aspects, the bits may be Polar coded bits. In some aspects, the bits may be systematic Polar coded bits.

At block <NUM>, the apparatus receives a second transmission associated with the first transmission, the second transmission including a second set of bits with the cyclic redundancy check (CRC) information, and the second set of bits corresponding to the second subset of bits.

In some aspects, the first subset of bits may include other CRC information; and the CRC information of the second subset of bits may be independent of the other CRC information of the first subset of bits.

In some aspects, the decoding of the first set of bits using the decoded second set of bits may include: pruning candidate vectors from the decoding of the second set of bits through use of the CRC information; and recovering the first set of bits based on the pruned candidate vectors.

<FIG> illustrates a process <NUM> for communication in accordance with some aspects of the disclosure. One or more aspects of the process <NUM> may be used in conjunction with (e.g., in addition to or as part of) the process <NUM> of <FIG> and/or the process <NUM> of <FIG>. The process <NUM> may take place within a processing circuit (e.g., the processing circuit <NUM> of <FIG>), which may be located in an access terminal, a base station, or some other suitable apparatus (e.g., that includes a decoder). Of course, in various aspects within the scope of the disclosure, the process <NUM> may be implemented by any suitable apparatus capable of supporting signaling-related operations.

At block <NUM>, an apparatus (e.g., a device that includes a decoder) receives a first transmission including a first set of bits, the first set of bits including a first subset of bits and a second subset of bits.

At block <NUM>, the apparatus decodes the first set of bits.

At block <NUM>, the apparatus receives a second transmission including a second set of bits.

At block <NUM>, the apparatus decodes the second set of bits.

At block <NUM>, the apparatus soft-combines the decoded second subset of bits and the decoded second set of bits to generate soft-combined bits.

In some implementations, the circuit/module for soft-combining <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for soft-combining <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus decodes the first set of bits using the soft-combined bits.

At block <NUM>, an apparatus (e.g., a device that includes a decoder) receives a first transmission including a first set of bits, the first set of bits including a first subset of bits and a second subset of bits that includes CRC information.

At block <NUM>, the apparatus receives a second transmission including a second set of bits that includes the CRC information.

At block <NUM>, the apparatus prunes candidate vectors from the decoding of the second set of bits through use of the CRC information.

In some implementations, the circuit/module for pruning <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for pruning <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus decodes the first set of bits using the pruned candidate vectors.

<FIG> illustrates a block diagram of an example hardware implementation of an apparatus <NUM> configured to provide encoding according to one or more aspects of the disclosure. The apparatus <NUM> could embody or be implemented within a UE, a TRP, a gNB, a base station, or some other type of device that supports encoding as taught herein. In various implementations, the apparatus <NUM> could embody or be implemented within an access terminal, an access point, or some other type of device. In various implementations, the apparatus <NUM> could embody or be implemented within a mobile phone, a smart phone, a tablet, a portable computer, a server, a network entity, a personal computer, a sensor, an alarm, a vehicle, a machine, an entertainment device, a medical device, or any other electronic device having circuitry.

The apparatus <NUM> includes a communication interface (e.g., at least one transceiver) <NUM>, a storage medium <NUM>, a user interface <NUM>, a memory device <NUM> (e.g., storing coding information <NUM>), and a processing circuit (e.g., at least one processor) <NUM>. In various implementations, the user interface <NUM> may include one or more of: a keypad, a display, a speaker, a microphone, a touchscreen display, of some other circuitry for receiving an input from or sending an output to a user. The communication interface <NUM> may be coupled to one or more antennas <NUM>, and may include a transmitter <NUM> and a receiver <NUM>. In general, the components of <FIG> may be similar to corresponding components of the apparatus <NUM> of <FIG>.

The processing circuit <NUM> may be a specialized processor, such as an application-specific integrated circuit (ASIC) that serves as a means for (e.g., structure for) carrying out any one of the operations described in conjunction with <FIG> and <NUM>. The processing circuit <NUM> serves as one example of a means for transmitting and/or a means for receiving. In various implementations, the processing circuit <NUM> may provide and/or incorporate the functionality of the first wireless communication device <NUM> (e.g., the encoder <NUM>) of <FIG> or the encoder <NUM> of <FIG>.

According to at least one example of the apparatus <NUM>, the processing circuit <NUM> may include one or more of a circuit/module for encoding <NUM>, a circuit/module for transmitting <NUM>, a circuit/module for determining <NUM>, or a circuit/module for generating CRC information <NUM>. In various implementations, the circuit/module for encoding <NUM>, the circuit/module for transmitting <NUM>, the circuit/module for determining <NUM>, or the circuit/module for generating CRC information <NUM> may provide and/or incorporate, at least in part, the functionality described above for the first wireless communication device <NUM> (e.g., the encoder <NUM>) of <FIG>. or the encoder <NUM> of <FIG>.

As mentioned above, programming stored by the storage medium <NUM>, when executed by the processing circuit <NUM>, causes the processing circuit <NUM> to perform one or more of the various functions and/or process operations described herein. For example, the programming may cause the processing circuit <NUM> to perform the various functions, steps, and/or processes described herein with respect to <FIG> and <FIG> in various implementations. As shown in <FIG>, the storage medium <NUM> may include one or more of code for encoding <NUM>, code for transmitting <NUM>, code for determining <NUM>, or code for generating CRC information <NUM>. In various implementations, the code for encoding <NUM>, the code for transmitting <NUM>, the code for determining <NUM>, or the code for generating CRC information <NUM> may be executed or otherwise used to provide the functionality described herein for the circuit/module for encoding <NUM>, the circuit/module for transmitting <NUM>, the circuit/module for determining <NUM>, or the circuit/module for generating CRC information <NUM>.

The circuit/module for encoding <NUM> may include circuitry and/or programming (e.g., code for encoding <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, encoding information. In some aspects, the circuit/module for encoding <NUM> (e.g., a means for encoding) may correspond to, for example, a processing circuit.

In some aspects, the circuit/module for encoding <NUM> may execute an encoding algorithm. For example, the circuit/module for encoding <NUM> may perform a block coding algorithm or a Polar coding algorithm. In some aspects, the circuit/module for encoding <NUM> may perform the encoding operations described herein conjunction with <FIG>. The circuit/module for encoding <NUM> then outputs the resulting encoded information (e.g., to the circuit/module for transmitting <NUM>, the memory device <NUM>, the communication interface <NUM>, or some other component).

The circuit/module for transmitting <NUM> may include circuitry and/or programming (e.g., code for transmitting <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, transmitting (e.g., sending) information. In some implementations, the circuit/module for transmitting <NUM> may obtain information (e.g., from the circuit/module for encoding <NUM>, the memory device <NUM>, or some other component of the apparatus <NUM>) and process the information (e.g., encode the information for transmission). In some scenarios, the circuit/module for transmitting <NUM> sends the information to another component (e.g., the transmitter <NUM>, the communication interface <NUM>, or some other component) that will send the information to another device. In some scenarios (e.g., if the circuit/module for transmitting <NUM> includes a transmitter), the circuit/module for transmitting <NUM> transmits the information directly to another device (e.g., the ultimate destination) via radio frequency signaling or some other type of signaling suitable for the applicable communication medium.

The circuit/module for transmitting <NUM> (e.g., a means for outputting, a means for sending, a means for transmitting, etc.) may take various forms. In some aspects, the circuit/module for transmitting <NUM> may correspond to, for example, a processing circuit as discussed herein. In some aspects, the circuit/module for transmitting <NUM> may correspond to, for example, an interface (e.g., a bus interface, a send interface, or some other type of signal interface), a communication device, a transceiver, a transmitter, or some other similar component as discussed herein. In some implementations, the communication interface <NUM> includes the circuit/module for transmitting <NUM> and/or the code for transmitting <NUM>. In some implementations, the circuit/module for transmitting <NUM> and/or the code for transmitting <NUM> is configured to control the communication interface <NUM> (e.g., a transceiver or a transmitter) to transmit information.

The circuit/module for determining <NUM> may include circuitry and/or programming (e.g., code for determining <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, determining whether to perform a second transmission. In some aspects, the circuit/module for determining <NUM> (e.g., a means for determining) may correspond to, for example, a processing circuit.

In some scenarios, the circuit/module for determining <NUM> may obtain feedback information. For example, the circuit/module for determining <NUM> may obtain an ACK or NAK (e.g., from the communication interface <NUM>, the memory device <NUM>, or some other component of the apparatus <NUM>). The circuit/module for determining <NUM> may elect to retransmit if the feedback is a NAK or some other similar value. The circuit/module for determining <NUM> may then output an indication of the determination (e.g., to the circuit/module for transmitting <NUM>, the memory device <NUM>, or some other component).

The circuit/module for generating CRC information <NUM> may include circuitry and/or programming (e.g., code for generating CRC information <NUM> stored on the storage medium <NUM>) adapted to perform several functions relating to, for example, generating CRC information for different subsets of bits. In some aspects, the circuit/module for generating CRC information <NUM> (e.g., a means for generating) may correspond to, for example, a processing circuit.

In some aspects, the circuit/module for generating CRC information <NUM> may perform a CRC algorithm based on obtained input information. The circuit/module for generating CRC information <NUM> then outputs the resulting CRC (e.g., to the circuit/module for encoding <NUM>, the memory device <NUM>, the communication interface <NUM>, or some other component).

<FIG> illustrates a process <NUM> for communication in accordance with some aspects of the disclosure. The process <NUM> may take place within a processing circuit (e.g., the processing circuit <NUM> of <FIG>), which may be located in an access terminal, a base station, or some other suitable apparatus (e.g., that includes an encoder). Of course, in various aspects within the scope of the disclosure, the process <NUM> may be implemented by any suitable apparatus capable of supporting signaling-related operations.

At block <NUM>, an apparatus (e.g., a device that includes an encoder) encodes a first set of bits, wherein the first set of bits corresponds to a first subset of bits including first CRC information and a second subset of bits including second CRC information. In some aspects, the encoding of the first set of bits may include Polar coding. In some aspects, the encoding of the first set of bits may include systematic encoding. In some aspects, the first CRC information may be independent of the second CRC information.

In some implementations, the circuit/module for encoding <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for encoding <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus transmits the encoded first set of bits.

In some implementations, the circuit/module for transmitting <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for transmitting <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus determines that a second transmission is needed.

In some implementations, the circuit/module for determining <NUM> of <FIG> performs the operations of block <NUM>. In some implementations, the code for determining <NUM> of <FIG> is executed to perform the operations of block <NUM>.

At block <NUM>, the apparatus encodes a second set of bits including the second CRC information, wherein the second set of bits corresponds to the second subset of bits.

At block <NUM>, the apparatus transmits the encoded second set of bits.

<FIG> illustrates an example encoder <NUM> and an example decoder <NUM> constructed in accordance with the teachings herein. In some aspects, the encoder <NUM> and the decoder <NUM> may correspond to the encoder <NUM> and the decoder <NUM> of <FIG>, respectively.

The encoder <NUM> encodes data <NUM> to generate encoded data <NUM>. In accordance with the teachings herein, the encoder <NUM> may include a module for Polar coding optionally including CRC from a first transmission in a second transmission <NUM>.

The decoder <NUM> decodes the encoded data <NUM> (e.g., after transmission over a communication channel, not shown) to provide recovered data <NUM>. In accordance with the teachings herein, the decoder <NUM> may include a module for decoding a first transmission based on a second transmission <NUM>.

In some implementations, the encoder <NUM> may include an interface <NUM>, an interface <NUM>, or both. Such an interface may include, for example, an interface bus, bus drivers, bus receivers, other suitable circuitry, or a combination thereof. For example, the interface <NUM> may include receiver devices, buffers, or other circuitry for receiving a signal. As another example, the interface <NUM> may include output devices, drivers, or other circuitry for sending a signal. In some implementations, the interfaces <NUM> and <NUM> may be configured to interface one or more other components of the encoder <NUM> (other components not shown in <FIG>).

In some implementations, the decoder <NUM> may include an interface <NUM>, an interface <NUM>, or both. Such an interface may include, for example, an interface bus, bus drivers, bus receivers, other suitable circuitry, or a combination thereof. For example, the interface <NUM> may include receiver devices, buffers, or other circuitry for receiving a signal. As another example, the interface <NUM> may include output devices, drivers, or other circuitry for sending a signal. In some implementations, the interfaces <NUM> and <NUM> may be configured to interface one or more other components of the decoder <NUM> (other components not shown in <FIG>).

The encoder <NUM> and the decoder <NUM> may take different forms in different implementations. In some cases, the encoder <NUM> and/or the decoder <NUM> may be an integrated circuit. In some cases, the encoder <NUM> and/or the decoder <NUM> may be included in an integrated circuit that includes other circuitry (e.g., a processor and related circuitry).

The examples set forth herein are provided to illustrate certain concepts of the disclosure. Those of ordinary skill in the art will comprehend that these are merely illustrative in nature, and other examples may fall within the scope of the disclosure and the appended claims.

As those skilled in the art will readily appreciate, various aspects described throughout this disclosure may be extended to any suitable telecommunication system, network architecture, and communication standard. By way of example, various aspects may be applied to wide area networks, peer-to-peer network, local area network, other suitable systems, or any combination thereof, including those described by yet-to-be defined standards.

Many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits, for example, central processing units (CPUs), graphic processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or various other types of general purpose or special purpose processors or circuits, by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein.

For example, data, instructions, commands, inforrnation, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.

One or more of the components, steps, features and/or functions illustrated in above may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. The apparatus, devices, and/or components illustrated above may be configured to perform one or more of the methods, features, or steps described herein.

The methods, sequences or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. An example of a storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.

Likewise, the term "aspects" does not require that all aspects include the discussed feature, advantage or mode of operation.

The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the aspects. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word "or" has the same meaning as the Boolean operator "OR," that is, it encompasses the possibilities of "either" and "both" and is not limited to "exclusive or" ("XOR"), unless expressly stated otherwise. It is also understood that the symbol "/" between two adjacent words has the same meaning as "or" unless expressly stated otherwise. Moreover, phrases such as "connected to," "coupled to" or "in communication with" are not limited to direct connections unless expressly stated otherwise.

Any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be used there or that the first element must precede the second element in some manner. Also, unless stated otherwise a set of elements may comprise one or more elements. In addition, terminology of the form "at least one of a, b, or c" or "a, b, or c, or any combination thereof" used in the description or the claims means "a or b or c or any combination of these elements. " For example, this terminology may include a, or b, or c, or a and b, or a and c, or a and b and c, or 2a, or 2b, or 2c, or 2a and b, and so on.

For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

Claim 1:
A method of communication, comprising:
decoding a first set of bits from a first transmission, wherein the first set of bits includes a first subset of bits (<NUM>, <NUM>, <NUM>) and a second subset of bits (<NUM>, <NUM>, <NUM>);
receiving a second transmission associated with the first transmission, the second transmission including a second set of bits without cyclic redundancy check, CRC, information, and the second set of bits corresponding to the second subset of bits;
decoding the second set of bits; and
decoding the first set of bits using the decoded second set of bits, wherein the decoding comprises list decoding.