Patent Description:
Numerical computations frequently waste power by performing unnecessarily precise computations, even though many applications including neural networks and signal processing applications can tolerate some loss of precision. The operational time interval of a battery in a computing device can therefore be extended by performing some arithmetic operations at lower precision. For example, a programmer can specify that some operations are to be performed at half-precision instead of double precision. However, the precision of arithmetic operations is typically determined when code is compiled for execution by the computing device. The precision of arithmetic operations in the compiled code cannot be modified while the code is executing.

The operational time interval of a power supply such as a battery in a computing device can be extended by dynamically modifying the precision of arithmetic operations performed by the computing device. To support dynamic modification of arithmetic precision, operands are converted from a conventional number system that represents each binary number as one bit to a redundant number system (RNS) that represents each binary number as a plurality of bits, which allows computations to be performed in a direction from the most significant bit (MSB) to the least significant bit (LSB). Each of the RNS operands is associated with a dynamic precision that is represented by a number of bits corresponding to target accuracies of operations performed on the RNS operand. In some embodiments, the dynamic precision is determined based on a data type (e.g., data types that represent graphics objects or primitives include video, RGB color, scene depth, or vertex position data) or statistics that represent data values (e.g., statistical measures that indicate that the data values cluster around the value such as <NUM> or <NUM>, the data values are in a particular range, or the data values have a mean or median value that is above or below a threshold value). The dynamic precision can also be varied at runtime, e.g., in response to changes in a battery level, changes in the target accuracy, and the like. In some embodiments, the dynamic precision is different for each RNS operand. The dynamic precision for each RNS operand is indicated in a data structure that includes the dynamic precision and the value of the RNS operand.

Arithmetic operations are performed on the binary numbers in the RNS operands in a direction from the most significant bit (MSB) to the least significant bit (LSB) for the number of binary numbers indicated by the dynamic precision of the RNS operand. This is referred to as "MSB-first" arithmetic, in contrast to conventional "LSB-first" arithmetic that performs operations on bits proceeding in a direction from the LSB to the MSB. An arithmetic logic unit that performs MSB-first arithmetic includes separate hardware components (referred to herein as bit slices) to perform arithmetic operations on each binary number in the RNS operand. Enable signals are provided to turn on the bit slices corresponding to a portion of the RNS operand indicated by the dynamic precision. Power or clock signals can then be gated for the bit slices that operate on the binary numbers that are less significant than the portion of the RNS operand indicated by the dynamic precision. Performing the arithmetic operations on the RNS operands prevents more than one bit of ripple between the bit slices, e.g., a carry-in bit received by a bit slice from a less significant bit slice does not determine a value of a carry-out bit provided by the bit slice to a more significant bit slice. In some embodiments, conversion of conventional binary numbers to RNS operands and the dynamic modification of the precision of arithmetic operations performed on the RNS operands are selectively performed based on a comparison of the overhead needed to perform the conversion and the expected power savings produced by the dynamic modification of the precision.

<FIG> is a block diagram of a computing device <NUM> according to some embodiments. The computing device <NUM> includes a set of hardware components <NUM> that are configured to convert conventional binary numbers into RNS operands and perform arithmetic operations on the RNS operands using MSB-first arithmetic. Examples of arithmetic operations that can be performed by the hardware components <NUM> include addition, subtraction, multiplication, and division. Furthermore, more complex functions including transcendental functions can be implemented based on the addition, subtraction, multiplication, and division functions. The hardware components <NUM> are therefore able to perform the more complex functions using MSB-first arithmetic. Some embodiments of the hardware components <NUM> are implemented using processing units such as central processing units (CPUs), graphics processing units (GPUs), or accelerated processing units (APUs) that are fabricated on a substrate or die. The hardware components <NUM> can also be implemented as application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), or other combinations of hardware components such as transistors, capacitors, resistors, traces, wires, and the like.

The hardware components <NUM> are configured to receive one or more operands <NUM> that are formatted according to a conventional numbering system (CNS). Some embodiments of the operands <NUM> are represented in a binary format using a sequence of binary numbers such as <NUM>, <NUM>, <NUM>, <NUM>,. Each binary number in the operand <NUM> is represented as a single bit and the values of the bits indicate the value of the operand. For example, an operand <NUM> having a value of one can be represented as <NUM> in the CNS.

A conversion unit <NUM> is implemented in the hardware components <NUM> and configured to convert conventional operands into RNS operands in which each binary number is represented by a plurality of bits. For example, a redundant binary representation of the operands <NUM> can represent each binary number as two bits and the values of the binary numbers can be determined using a translation table such as Table <NUM>. An operand having a value of one can be represented as an RNS operand using different values for the binary numbers including <NUM>-<NUM>-<NUM>-<NUM> (<NUM>+<NUM>+<NUM>+<NUM>=<NUM>), <NUM>-<NUM>-<NUM>-<NUM> (<NUM>+<NUM>+<NUM>+<NUM>=<NUM>), <NUM>-<NUM>-<NUM>-<NUM> (<NUM>+<NUM>+<NUM>-<NUM>=<NUM>), or <NUM>-<NUM>-<NUM>-<NUM> (<NUM>-<NUM>-<NUM>-<NUM>=<NUM>). Other embodiments of the conversion unit <NUM> can convert conventional operands into RNS operands using different redundant numbering systems.

Conversion of conventional operands into RNS operands allows computations to be performed on the RNS operands in a direction from the most significant bit (MSB) to the least significant bit (LSB). Arithmetic operations can also be performed faster on RNS operands. However, conversion of the operands <NUM> into RNS operands by the conversion unit <NUM> incurs overhead such as additional processing time and power that is needed to perform the conversion. Some embodiments of the conversion unit <NUM> therefore selectively perform the conversion of the operands <NUM> based on a comparison of the incurred overhead and the benefits of performing the arithmetic operations on the RNS operands. For example, the resources needed to perform the conversion can be compared to the resources that are saved by speeding up the arithmetic operations. For another example, the resources needed to perform the conversion can be compared to the resources that are saved by only performing arithmetic operations on a set of most significant binary numbers in the RNS operands, and bypassing performing the arithmetic operations on a complementary set of less significant binary numbers in the RNS operands. In some embodiments, a completion detection circuit such as a configurable delay line is included in the hardware components <NUM> and used to detect completion of arithmetic operations that are stopped or terminated prior to operating on all of the binary numbers in the RNS operands, as discussed herein.

The hardware components <NUM> are able to perform a set of arithmetic operations <NUM>, <NUM>, <NUM> on the RNS operands generated by the conversion unit <NUM>. The arithmetic operations <NUM>, <NUM>, <NUM> can be performed in sequence, e.g., the result of the arithmetic operation <NUM> becomes an input for the arithmetic operation <NUM>. The arithmetic operations <NUM>, <NUM>, <NUM> can also represent operations that are performed on different, overlapping, or partially overlapping sets of the RNS operands. In some embodiments, the arithmetic operations <NUM>, <NUM>, <NUM> are performed by an arithmetic logic unit (not shown in <FIG>) that is implemented in the hardware components <NUM>. The arithmetic operations <NUM>, <NUM>, <NUM> can also be performed by different arithmetic logic units or other hardware configured to perform MSB-first arithmetic.

The arithmetic operations <NUM>, <NUM>, <NUM> are performed using MSB-first arithmetic on RNS operands, as indicated by the left pointing arrows <NUM> (only one indicated by a reference numeral in the interest of clarity). Thus, each of the arithmetic operations <NUM>, <NUM>, <NUM> begins by performing the arithmetic operation on the bits that represent the most significant binary number in the RNS operands. The arithmetic operations <NUM>, <NUM>, <NUM> then perform the arithmetic operation on the bits that represent the next most significant binary number. Each iteration of the arithmetic operation therefore monotonically increases the accuracy of the results of the arithmetic operation. In an RNS arithmetic operation, the arithmetic operations <NUM>, <NUM>, <NUM> can proceed to perform the arithmetic operations on less significant binary numbers until the arithmetic operation had been performed on all of the binary numbers in the RNS operands.

However, as discussed herein, not all applications require the highest level of accuracy provided by the arithmetic operations <NUM>, <NUM>, <NUM>. Performing the arithmetic operations on all of the binary numbers in the RNS operands can therefore unnecessarily consume power, which may be a limited resource for the hardware components <NUM>. The hardware components <NUM> are therefore configured to stop, terminate, or interrupt the arithmetic operations <NUM>, <NUM>, <NUM> prior to performing the arithmetic operation on a target binary number that is indicated by a dynamic precision. The target binary number represents a threshold significance, such that arithmetic operations are not performed on binary numbers that are less significant than the threshold significance. Interrupting the arithmetic operations <NUM>, <NUM>, <NUM> reduces the accuracy of the results of the arithmetic operations <NUM>, <NUM>, <NUM>, but also reduces the power consumption of the hardware components <NUM>.

The dynamic precision associated with an RNS operand or arithmetic operation can be modified at runtime and may be different for different RNS operands or arithmetic operations <NUM>, <NUM>, <NUM>. For example, the lines <NUM>, <NUM>, <NUM> represent the target binary number for the corresponding arithmetic operations <NUM>, <NUM>, <NUM>. The arithmetic operation <NUM> therefore achieves the highest accuracy (and consumes the largest fraction of the total power that would be consumed if the operation <NUM> was performed on all the binary numbers in the RNS operand), the arithmetic operation <NUM> achieves the next highest accuracy (and consumes the next largest fraction of the total power that would have been consumed by the operation <NUM> if performed on all the binary numbers in the RNS operand), and the arithmetic operation <NUM> achieves the lowest accuracy (but consumes the lowest fraction of the total power that would have been consumed by the operation <NUM> if performed on all the binary numbers in the RNS operand).

The hardware components <NUM> also include a conversion unit <NUM> for converting the RNS operands into operands <NUM> that are represented according to a conventional numbering system (CNS). For example, some or all of the arithmetic operations <NUM>, <NUM>, <NUM> can provide results in the RNS format to the conversion unit <NUM>, which converts the RNS results into the operands <NUM>. In some embodiments, the conversion unit <NUM> selectively converts the operands <NUM> into RNS operands based in part on the overhead required to convert the RNS results back into CNS operands <NUM>.

<FIG> is a block diagram of a computing device <NUM> that includes an arithmetic logic unit (ALU) <NUM> that is configured to perform arithmetic operations on RNS operands <NUM>, <NUM> using MSB-first arithmetic according to some embodiments. The arithmetic logic unit <NUM> is implemented in some embodiments of the hardware components <NUM> shown in <FIG>. The arithmetic logic unit <NUM> can therefore be used to perform one or more arithmetic operations including addition, subtraction, multiplication, or division on the RNS operands <NUM>, <NUM>. Furthermore, some embodiments of the arithmetic logic unit <NUM> are configured to perform complex functions including transcendental functions on the RNS operands <NUM>, <NUM> using MSB-first arithmetic. Although the arithmetic logic unit <NUM> shown in <FIG> receives two RNS operands <NUM>, <NUM>, some embodiments of the arithmetic logic unit <NUM> can receive and operate on more than two RNS operands.

The RNS operands <NUM>, <NUM> are associated with respective dynamic precisions <NUM>, <NUM>. In the illustrated embodiment, the values of the RNS operands <NUM>, <NUM> and the respective dynamic precisions <NUM>, <NUM> are provided to the arithmetic logic unit <NUM> in corresponding data structures <NUM>, <NUM>. For example, the data structures <NUM>, <NUM> can be a specifically defined instruction word, such as a variation of a very long instruction word, that is configured to hold values of the RNS operands <NUM>, <NUM> and the respective dynamic precisions <NUM>, <NUM>. However, in some embodiments, the RNS operands <NUM>, <NUM> and the respective dynamic precisions <NUM>, <NUM> are provided to the arithmetic logic unit <NUM> in different data structures. Furthermore, in some embodiments, the dynamic precisions <NUM>, <NUM> are not provided directly to the arithmetic logic unit <NUM> or the control unit <NUM>. Instead, hints that indicate the dynamic precisions <NUM>, <NUM> are provided to the arithmetic logic unit <NUM>. The hints can be defined to include less information than the dynamic precisions <NUM>, <NUM> and the hints can be selectively used in place of the full dynamic precisions <NUM>, <NUM> in operating modes such as low power modes of the computing device <NUM>. The hints can be provided by an application using an interface between the application and the hardware that is used to implement the arithmetic logic unit <NUM> and the control unit <NUM>.

A control unit <NUM> accesses values of the dynamic precisions <NUM>, <NUM> and, in some cases, values of the RNS operands <NUM>, <NUM>. The control unit <NUM> then provides control signaling to the arithmetic logic unit <NUM> that is generated responsive to the values of the dynamic precisions <NUM>, <NUM>, and, in some cases, the values of the RNS operands <NUM>, <NUM>. The control signaling instructs the arithmetic logic unit <NUM> to perform an arithmetic operation on the binary numbers represented by the values of the RNS operands <NUM>, <NUM> using MSB-first arithmetic, e.g., by performing the arithmetic operations in a direction from a most significant bit (MSB) to a least significant bit (LSB).

The control unit <NUM> also provides control signaling that instructs the arithmetic logic unit <NUM> to stop performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by the dynamic precisions <NUM>, <NUM> associated with the RNS operands <NUM>, <NUM>. For example, if the RNS operands <NUM>, <NUM> are provided to the arithmetic logic unit <NUM> in single precision floating point format (e.g., represented by <NUM> bits in the conventional binary numbering system and <NUM> binary numbers represented by multiple bits in RNS) and the dynamic precisions <NUM>, <NUM> indicate that the <NUM> most significant binary numbers provide sufficient precision, the control unit <NUM> instructs the arithmetic logic unit to stop performing the arithmetic operation prior to performing the arithmetic operation on the <NUM>-st binary number in order from most significant to least significant. In some embodiments, the control unit <NUM> selectively instructs the arithmetic logic unit <NUM> to stop performing the arithmetic operation at the target binary number based on a power consumption status of the computing device <NUM>. For example, the control unit <NUM> can be configured to bypass instructing the arithmetic logic unit <NUM> to stop performing the arithmetic operation in response to the computing device <NUM> being in a power consumption mode that does not require power conservation. For another example, the control unit <NUM> can be configured to instruct the arithmetic logic unit <NUM> to stop performing the arithmetic operations in response to the computing device being in a power consumption mode that requires power conservation, such as a mode that is triggered by a battery level falling below a threshold.

In some embodiments, the computing device <NUM> includes a configurable delay line <NUM> that is dynamically configured to measure the execution time of the arithmetic operations performed by the arithmetic logic unit <NUM> based on the dynamic precisions <NUM>, <NUM>. For example, the control unit <NUM> can transmit a pulse (or edge) into the configurable delay line <NUM> in response to the arithmetic logic unit <NUM> initiating the arithmetic operation on the RNS operands <NUM>, <NUM>. The control unit <NUM> then determines that the arithmetic operation has completed in response to the pulse (or edge) appearing on the output of the configurable delay line <NUM>. The control unit <NUM> configures the configurable delay line <NUM> based on the dynamic precisions <NUM>, <NUM> so that the time interval required for the pulse (or edge) to propagate through the configurable delay line <NUM> and return to the control unit <NUM> is equal to the time interval required for the arithmetic logic unit <NUM> to perform the arithmetic operation on the RNS operands <NUM>, <NUM> to the precision indicated by the dynamic precisions <NUM>, <NUM>.

Some embodiments of the control unit <NUM> determine the values of the dynamic precisions <NUM>, <NUM> based on characteristics of the data stored in the RNS operands <NUM>, <NUM>. For example, the dynamic precisions <NUM>, <NUM> can be determined based on a data type so that different levels of precision are utilized for data types that represent graphics objects or primitives that include video, RGB color, scene depth, or vertex position data. For another example, the dynamic precisions <NUM>, <NUM> can be determined based on statistics that represent properties of the binary numbers in the RNS operands <NUM>, <NUM>, as well as other RNS operands that were previously received by the arithmetic logic unit <NUM>. The statistics can include statistical measures that indicate that the binary numbers cluster around a value such as <NUM> or <NUM>, the binary numbers have a mean or a median value that is in a particular range, the binary numbers have a mean or median value that is above or below a threshold value, and the like.

Some embodiments of the control unit <NUM> determine or modify the dynamic precisions <NUM>, <NUM> at runtime. For example, the control unit <NUM> can modify one or more of the dynamic precisions <NUM>, <NUM> in response to changes in a battery level, changes in the target accuracy, and the like. Increasing the dynamic precisions <NUM>, <NUM> typically leads to increased power consumption and is therefore performed in response to an increase in a battery level. Decreasing the dynamic precisions <NUM>, <NUM> typically leads to decreased power consumption and is therefore performed in response to a decrease in a battery level, e.g., below a threshold that indicates a low battery level. In some embodiments, the dynamic precisions <NUM>, <NUM> are different for the RNS operand <NUM>, <NUM>.

The arithmetic logic unit <NUM> can also be configured to determine or modify precisions in response to performing arithmetic operations on the RNS operands <NUM>, <NUM>. Some embodiments of the arithmetic logic unit <NUM> generate dynamic precisions <NUM> for RNS results <NUM> of the arithmetic operations performed on the RNS operands <NUM>, <NUM>. For example, the arithmetic logic unit <NUM> can set the dynamic precision <NUM> to the lower of the dynamic precisions <NUM>, <NUM>. The dynamic precision <NUM> and the RNS result <NUM> are then output from the arithmetic logic unit <NUM>, e.g., in a data structure <NUM>.

<FIG> is a block diagram of a computing device <NUM> that implements an arithmetic logic unit <NUM> that is selectively enabled based on a dynamic precision <NUM> according to some embodiments. The arithmetic logic unit <NUM> includes a plurality of bit slices <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (collectively referred to herein as "the bit slices <NUM>-<NUM>") that operate on different binary numbers of RNS operands. The bit slices <NUM>-<NUM> shown in <FIG> are arranged in order of significance of the bits in the associated binary numbers from the most significant bit (at the left) to the least significant bit (at the right). The dynamic precision <NUM> encodes the precision using a thermometer code that sets a number of most significant bits to a value (such as "<NUM>") to represent the precision and sets the remainder of less significant bits to a complementary value (such as "<NUM>").

Each of the bit slices <NUM>-<NUM> includes a hardware component (S) configured to perform an arithmetic operation (such as a sum) on the corresponding binary numbers of the RNS operands received by the arithmetic logic unit <NUM>. Each of the bit slices <NUM>-<NUM> also includes a hardware component (C) that is configured to generate a carry bit that is provided to the next most significant bit slice. The carry bit is referred to as a carry-out bit when it is provided from a bit slice and a carry-in bit when it is received by the bit slice. The hardware components (S) utilize the value of the carry-in bit to perform the arithmetic operation. However, the bit slices <NUM>-<NUM> are configured to prevent more than one bit of ripple between the bit slices <NUM>-<NUM>, e.g., a carry-in bit received by a bit slice from a less significant bit slice does not determine a value of a carry-out bit generated by the hardware component (C) and provided by the bit slice to a more significant bit slice.

The bit slices <NUM>-<NUM> are selectively enabled to perform arithmetic operations based on the dynamic precision <NUM>, which is represented by values of a series of bits. Enable signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (collectively referred to herein as "the enable signals <NUM>-<NUM>") are generated on the basis of the values of the bits in the dynamic precision <NUM> and provided to the corresponding bit slices <NUM>-<NUM>. In the illustrated embodiment, a value of "<NUM>" in a bit of the dynamic precision <NUM> indicates that the corresponding bit slice is enabled to perform the arithmetic operation and a value of "<NUM>" in a bit indicates that the corresponding bit slice is disabled and therefore not used to perform the arithmetic operation on the corresponding binary number. For example, enable signals <NUM>-<NUM> are provided to the corresponding bit slices <NUM>-<NUM> to enable the bit slices <NUM>-<NUM> to perform arithmetic operations on binary numbers of an RNS operand. Enable signals <NUM>, <NUM> are not provided to the corresponding bit slices <NUM>, <NUM> and so the bit slices <NUM>, <NUM> do not perform arithmetic operations on the corresponding binary numbers. In some embodiments, the hardware component (C) of the most significant of the disabled bit slices (e.g., the bit slice <NUM> shown in <FIG>) generates a carry-out bit to support rounding operations even though the hardware component (S) of the disabled bit slice does not perform the arithmetic operation on the binary number. Selectively enabling or disabling the bit slices <NUM>-<NUM> reduces the power consumption of the computing device <NUM> by reducing the amount of power consumed by the disabled bit slices.

The computing device <NUM> includes a power supply <NUM> to supply power to the arithmetic logic unit <NUM> and a clock signal generator <NUM> to provide a clock signal to the arithmetic logic unit <NUM>. Gate logic <NUM> is implemented in the computing device <NUM> using transistors, switches, routers, and the like and operates under the control of a control unit such as the control unit <NUM> shown in <FIG>. The gate logic <NUM> selectively gates the power supplied to the bit slices <NUM>-<NUM> by the power supply <NUM> or the clock signal supplied by the clock signal generator <NUM> based on the dynamic precision <NUM>. For example, the gate logic <NUM> provides power and clock signals to the enabled bit slices <NUM>-<NUM> and gates the power or clock signals for the disabled bit slices <NUM>, <NUM> so that the disabled bit slices <NUM>, <NUM> do not receive power or clock signals from the power supply <NUM> or the clock signal generator <NUM>, respectively. Selectively gating the power or clock signals provided to the bit slices <NUM>-<NUM> based on the dynamic precision <NUM> further reduces the power consumption of the computing device <NUM> by further reducing the amount of power consumed by the disabled bit slices.

<FIG> is a block diagram of a computing device <NUM> that propagates errors associated with RNS operands according to some embodiments. The computing device <NUM> is implemented in some embodiments of the computing device <NUM> shown in <FIG> or the computing device <NUM> shown in <FIG>. The computing device <NUM> includes a plurality of arithmetic logic units <NUM>, <NUM>, <NUM> that are collectively referred to herein as "the arithmetic logic units <NUM>-<NUM>. " The arithmetic logic units <NUM>-<NUM> shown in <FIG> can represent three distinct hardware components of the computing device <NUM> or they can represent a single hardware component of the computing device <NUM> that is used to perform three separate arithmetic operations. Furthermore, the number of arithmetic logic units <NUM>-<NUM> or the number of hardware components used to implement the arithmetic logic units <NUM>-<NUM> (or other arithmetic logic units) in the computing device <NUM> can be larger or smaller than the number shown in <FIG>.

The arithmetic logic units <NUM>-<NUM> receive input RNS operands and information indicating the accumulated error associated with the RNS operand. For example, the arithmetic logic unit <NUM> receives the input RNS operands <NUM>, <NUM> and the corresponding accumulated errors <NUM>, <NUM> and the arithmetic logic unit <NUM> receives the input RNS operands <NUM>, <NUM> and the corresponding accumulated errors <NUM>, <NUM>. In some embodiments, the accumulated errors <NUM>, <NUM>, <NUM>, <NUM> are used to establish a dynamic precision for the arithmetic operations performed by the arithmetic logic units <NUM>, <NUM>. The arithmetic logic units <NUM>, <NUM> (or a corresponding controller <NUM>) can configure the dynamic precision used by the arithmetic logic units <NUM>, <NUM> to perform arithmetic operations on the input RNS operands <NUM>, <NUM>, <NUM>, <NUM> so that the dynamic precision of the arithmetic operations is not more precise than necessary for the associated accumulated errors <NUM>, <NUM>, <NUM>, <NUM>. For example, if the accumulated errors <NUM>, <NUM>, <NUM>, <NUM> for the input RNS operands <NUM>, <NUM>, <NUM>, <NUM> are less than or equal to a value indicated by the four least significant binary numbers in the input RNS operands <NUM>, <NUM>, <NUM>, <NUM>, the dynamic precisions for the input RNS operands <NUM>, <NUM>, <NUM>, <NUM> are set to correspond to the binary numbers that are more significant than the fourth least significant binary number.

The arithmetic logic units <NUM>-<NUM> generate output RNS operands <NUM>, <NUM>, <NUM> and corresponding accumulated errors <NUM>, <NUM>, <NUM>. For example, the output RNS operands <NUM>, <NUM> are generated by performing the arithmetic operations on the input RNS operands <NUM>, <NUM>, <NUM>, <NUM> and the accumulated errors <NUM>, <NUM> are determined based on the arithmetic operations using conventional error estimation/accumulation techniques. The output RNS operands <NUM>, <NUM> and the corresponding accumulated errors <NUM>, <NUM> are provided as input values to the arithmetic logic unit <NUM>, which performs arithmetic operations on the RNS operands <NUM>, <NUM> to generate the output RNS operand <NUM>. The arithmetic logic unit <NUM> also uses conventional error estimation/accumulation techniques to determine the accumulated error <NUM> based on the input accumulated errors <NUM>, <NUM>. In some embodiments, the accumulated error <NUM> is used to determine the dynamic precision used to determine the value of the output RNS operand <NUM>.

<FIG> is a flow diagram of a method <NUM> of performing dynamic variable precision arithmetic operations on RNS operands according to some embodiments. The method <NUM> is performed by arithmetic logic units that are implemented in some embodiments of the computing device <NUM> shown in <FIG>, the computing device <NUM> shown in <FIG>, the computing device <NUM> shown in <FIG>, and the computing device <NUM> shown in <FIG>. The method <NUM> begins at start block <NUM>.

At block <NUM>, the arithmetic logic unit performs an arithmetic operation on the most significant binary number in the input RNS operands. As discussed herein, examples of the arithmetic operations include addition, subtraction, multiplication, and division, as well as more complex functions including transcendental functions that can be implemented based on the addition, subtraction, multiplication, and division functions.

At decision block <NUM>, the arithmetic logic unit determines whether there are more binary numbers in the RNS operands that have not yet been used to perform arithmetic operations. If not, the method <NUM> flows to block <NUM> and determines a dynamic precision of the result of performing the arithmetic operation on the input RNS operand. The method <NUM> then flows to end block <NUM> and the method <NUM> ends because there are no more binary numbers to operate on and the arithmetic operation is complete. If the arithmetic logic unit determines that there are more binary numbers in the RNS operands, the method flows to decision block <NUM>.

At decision block <NUM>, the arithmetic logic unit determines whether the next binary number, i.e., a binary number that is less significant than the binary number that was previously operated on, is more significant than a threshold significance indicated by the dynamic precision associated with the RNS operands. For example, as discussed herein, the dynamic precision can be represented using a thermometer encoded array of bits that each correspond to a binary number in the RNS operands. Bit slices in the arithmetic logic unit that operate on binary numbers that are more significant than the threshold significance (or target binary number indicated by the dynamic precision) are enabled and bit slices that operate on binary numbers that are less significant than the threshold significance are disabled.

If the dynamic precision indicates (at decision block <NUM>) that the next binary number is more significant than the threshold significance, the method <NUM> flows to block <NUM> and the arithmetic logic unit performs the arithmetic operation on the next most significant binary number in the RNS operands. The method <NUM> then flows to decision block <NUM>. If the dynamic precision indicates (at decision block <NUM>) that the next binary number is less significant than the threshold significance, the method <NUM> flows to block <NUM> and determines a dynamic precision of the RNS result of performing the arithmetic operation on the input RNS operand. The method <NUM> then flows to end block <NUM>, thereby stopping the arithmetic operation prior to performing the arithmetic operation on a binary number that is less significant than the threshold significance.

In some embodiments, the apparatus and techniques described above are implemented in a system comprising one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the computing device described above with reference to <FIG>. Electronic design automation (EDA) and computer aided design (CAD) software tools may be used in the design and fabrication of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs comprise code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices so as to perform at least a portion of a process to design or adapt a manufacturing system to fabricate the circuitry. This code can include instructions, data, or a combination of instructions and data. The software instructions representing a design tool or fabrication tool typically are stored in a computer readable storage medium accessible to the computing system. Likewise, the code representative of one or more phases of the design or fabrication of an IC device may be stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

A computer readable storage medium may include any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and/or data to the computer system.

Claim 1:
An apparatus [<NUM>] comprising:
a conversion unit [<NUM>] to convert operands [<NUM>] from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands [<NUM>, <NUM>] that represent each binary number as a plurality of bits; and
an arithmetic logic unit [<NUM>] to perform an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB) and to stop the arithmetic operation prior to performing the arithmetic operation on a target binary number of the RNS operands indicated by a dynamic precision associated with the RNS operands, wherein the dynamic precision associated with the RNS operands is variable at runtime.