Patent Description:
An image capture device has been proposed that has a structure in which a photoelectric conversion layer is arranged at an upper side of a semiconductor substrate at which a CCD (charge-coupled device) circuit or a CMOS (complementary metal-oxide semiconductor) circuit is formed. The image capture device that has the photoelectric conversion layer at the upper side of the semiconductor substrate is called a laminate-type image capture device. For example, a solid-state imaging device having such a laminate-type structure is disclosed in patent document <CIT>.

In the laminate-type image capture device, charge generated by photoelectric conversion is accumulated in a charge accumulation region, and a readout circuit including a CCD circuit or a CMOS circuit reads out the accumulated charge. The photoelectric conversion layer is generally arranged on an insulating layer that covers a semiconductor substrate in which the readout circuit is formed. The photoelectric conversion layer on the insulating layer is electrically connected to the readout circuit via a connection portion provided in the insulating layer.

Patent document <CIT> discloses an imaging device with a semiconductor substrate; pixels arranged thereon; and a signal line through which a signal from a pixel is transferred, the pixel includes a photoelectric converter generating a charge, a region accumulating the charge, an amplification transistor having a gate electrically connected to the region, a first capacitor having a first terminal electrically connected to the region and a second terminal, a second capacitor having a third terminal electrically connected to the second terminal and a fourth terminal supplied with a voltage, a feedback transistor a source or a drain of which is electrically connected to the second terminal, and a feedback circuit forming a path through which an output from the amplification transistor is negatively fed back to the region. A similar device is also disclosed in patent document <CIT>.

Partent document <CIT> discloses a capacitor for a memory device, wherein the capacitor comprises a trench-shaped portion.

It is an object of the present invention to provide an imaging device with reduced noise.

This is achieved by the features of the independent claim. Preferred embodiments are the subject matter of the dependent claims.

Any references to embodiments that do not fall under the scope of the claims are to be understood as examples useful for understanding the invention.

These general or specific aspects may be implemented by an element, a device, a system, an integrated circuit, or a method. Also, these general or specific aspects may be implemented by an arbitrary combination of an element, a device, an apparatus, a system, an integrated circuit, and a method. Advantageous Effects of Invention.

One aspect of the present disclosure provides an imaging device that can further reduce noise.

Non-limiting and exemplary embodiments of the present disclosure provides the followings.

An imaging device according to one aspect of the present disclosure comprises a semiconductor substrate and pixels. Each of the pixels includes a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has a first electrical contact point electrically connected to a first electrical element and a second electrical contact point electrically connected to a second electrical element different from the first electrical element. The first capacitive element includes at least one trench portion having a trench shape.

Thus, since the first capacitive element is provided with two or more electrical contact points, it is possible to increase the degree of freedom of a layout of wires that provide electrical connection between the first capacitive element and the electrical elements. Thus, for example, since wires can be provided so that a parasitic capacitance between wires becomes less likely to occur even in a small pixel region, noise can be reduced. Thus, it is possible to realize an imaging device that can further reduce noise. Also, since an increase in the degree of freedom of the layout of the wires can reduce the pixel area, miniaturization of the imaging device is realized.

Also, for example, at least one of the first electrical contact point and the second electrical contact point may be provided at the at least one trench portion. Also, for example, the at least one of the first electrical contact point and the second electrical contact point may be provided at a bottom surface of the at least one trench portion. Also, for example, the first electrical contact point may be provided at the at least one trench portion, and the second electrical contact point may be provided at a portion other than the at least one trench portion.

As described above, the bottom surface or a side surface of the trench portion can be used to establish electrical connection with the electrical elements. That is, since the electrical contact points can be provided not only at a planar portion of the first capacitive element but also at a portion other than the planar portion, it is possible to enhance the degree of freedom of the wire layout.

Also, for example, the at least one trench portion may include a plurality of trench portions, and the plurality of trench portions may include a trench portion where the first electrical contact point and the second electrical contact point are not provided.

This makes it possible to increase the capacitance value of the first capacitive element, while suppressing an increase in the area occupied by the first capacitive element in a plan view. That is, the first capacitive element having a large capacitance value can be provided in a small pixel area.

Also, for example, the first electrode may be provided closer to the semiconductor substrate than the second electrode and may have the first electrical contact point and the second electrical contact point.

Thus, for example, vias or exposed portions of wiring portions can be exposed to plasma during formation of trenches, and the exposed portions can be activated. When the exposed portions and the first electrode of the first capacitive element are connected at the contact points, it is possible to reduce the contact resistance between the vias or the wiring portions and the first electrode. A reduction in the contact resistance can reduce variations in contact resistances among the pixels, thus making it possible to suppress roughness in an image generated by the imaging device. Thus, it is possible to realize an imaging device that can further reduce noise.

Also, for example, the second electrode may be provided farther from the semiconductor substrate than the first electrode and may have the first electrical contact point and the second electrical contact point.

Thus, since the electrode provided with the electrical contact points is not limited to the first electrode, it is possible to further enhance the degree of freedom of the wire layout.

Also, for example, the first electrode and the second electrode may contain TiN or TaN.

This makes it possible to form a first electrode and a second electrode having low surface roughness. Accordingly, since variations in the distance between the first electrode and the second electrode are suppressed, it is also possible to suppress variations in the capacitance value of the first capacitive element.

Also, for example, the imaging device according to one aspect of the present disclosure may further comprise a plurality of wiring layers provided at an upper side of the semiconductor substrate. Of the plurality of wiring layers, the number of wiring layers located at an upper side of the first capacitive element may be larger than the number of wiring layers located at a lower side of the first capacitive element.

In many cases, impurity regions that serve as parts of photoelectric converting portions for accumulating signal charge generated by charge accumulation portions are formed at a semiconductor substrate. Since the number of wiring layers that are close to the semiconductor substrate can be reduced, it is possible to suppress variations in the potentials of the charge accumulation portions, the variations being caused by parasitic capacitance components in the wiring layers. Accordingly, it is possible to realize an imaging device that can further reduce noise.

Also, for example, both the first electrical contact point and the second electrical contact point may be connected to vias.

Thus, for example, when upper ends of the vias are exposed to plasma during formation of the trenches, the upper ends of the vias are activated. This facilitates metal coupling between the upper ends of the vias and the electrodes of the first capacitive element, thus making it possible to reduce contact resistances between the vias and the electrodes of the first capacitive element.

Also, for example, each of the pixels may further include a photoelectric converting portion and an impurity region electrically connected to the photoelectric converting portion and provided in the semiconductor substrate. In a plan view, the first capacitive element may overlap at least a part of the impurity region.

Thus, when the first electrode or the second electrode is formed using material having a light-shielding property, the first capacitive element can suppress light incident on the imaging device reaching the impurity region. Thus, it is possible to suppress generation of unwanted charge in the impurity region, thus making it possible to further reduce noise.

Also, for example, each of the pixels may further include: a photoelectric converting portion; an impurity region electrically connected to the photoelectric converting portion and provided in the semiconductor substrate; a transistor electrically connected to the impurity region; and a second capacitive element. The transistor may be one of the first electrical contact point and the second electrical contact point, and the second capacitive element may be the other of the first electrical contact point and the second electrical contact point. Also, for example, the transistor may be a reset transistor that resets charge generated by the photoelectric converting portion and accumulated in the impurity region.

Thus, the first electrode or the second electrode can be made to have the same potential as the potential of one electrode of the second capacitive element and the potential of a source region or a drain region of the transistor. For example, the first electrode or the second electrode, one electrode of the second capacitive element, and the source region or the drain region of the transistor can be utilized as reset drain nodes.

Also, for example, the second capacitive element may be electrically connected to the impurity region via the first electrode or the second electrode.

Thus, the first electrode or the second electrode of the first capacitive element can be utilized as a part of a wire. Thus, since a dedicated wire that is needed for electrical connection can be reduced, the space in each pixel can be increased, thus making it possible to further increase the degree of freedom of layout of other wires.

Also, for example, each of the pixels may further include: a photoelectric converting portion; and an impurity region electrically connected to the photoelectric converting portion and provided in the semiconductor substrate. The first electrode may be provided closer to the semiconductor substrate than the second electrode and may be electrically connected to the impurity region, and the second electrode may be electrically connected to a pad to which a predetermined voltage value is applied.

This allows the potential of the first capacitive element to be adjusted with the voltage applied to the pad.

Also, for example, the imaging device may further include a sensitivity adjustment line for adjusting sensitivity of the imaging device, the sensitivity adjustment line electrically connecting to the pad and the second electrode.

This allows the sensitivity to be adjusted according to the amount of light that is incident on the imaging device, and thus the dynamic range of the imaging device can be increased ranging from dark scenes to bright scenes.

Embodiments will be described below in detail with reference to the accompanying drawings.

The embodiments described below each present a general or specific example. Numerical values, shapes, materials, constituent elements, the arrangement positions and connection forms of constituent elements, steps, the order of steps, and so on described in the embodiments below are merely examples and are not intended to limit the present disclosure. Also, of the constituent elements in the embodiments below, constituent elements not set forth in the independent claims will be described as optional constituent elements.

Also, the drawings are schematic diagrams and are not necessarily strictly illustrated. Accordingly, for example, scales and so on do not necessarily match in each drawing. Also, in the individual drawings, substantially the same constituent elements are denoted by the same reference numerals, and redundant descriptions are omitted or are briefly given.

Also, herein, the terms "parallel", "orthogonal", and so on representing relationships between elements, terms representing element shapes, and the ranges of numerical values are not expressions representing only exact meanings and are expressions representing substantially equivalent ranges, for example, expressions meaning that they include differences of about several percent.

Also, herein, the terms "upper side", "top", and "upper" and the terms "lower side", "bottom", and "lower" do not refer to an upper direction (a vertically upper side) and a lower direction (a vertically lower side) in absolute spatial recognition and are used as terms defined by relative positional relationships based on the order of laminated layers in a laminate configuration. Also, the terms "upper side" and "lower side" apply not only to cases in which two constituent elements are arranged with a gap therebetween and a constituent element exists between the two constituent elements but also to cases in which two constituent elements are arranged to adhere to each other and the two constituent elements contact each other.

Also, herein, the "plan view" refers to a view in a direction orthogonal to a major surface of a semiconductor substrate.

<FIG> is a diagram showing an exemplary circuit configuration of an imaging device <NUM> according to a present embodiment. As shown in <FIG>, the imaging device <NUM> comprises a plurality of pixels <NUM> and peripheral circuitry. The pixels <NUM> are, for example, two-dimensionally arrayed to form a pixel region RA. For simplicity, in <FIG>, four pixels <NUM> extracted from the plurality of pixels <NUM> are illustrated, and illustration of the other pixels <NUM> is omitted.

For example, when the imaging device <NUM> complies with a VGA (Video Graphics Array) standard, the imaging device <NUM> comprises about three-hundred thousand pixels <NUM> arrayed in a matrix. Also, when the imaging device <NUM> complies with an <NUM> standard, the imaging device <NUM> comprises about <NUM> million pixels <NUM> arrayed in a matrix. The above-described peripheral circuitry is arranged in a peripheral region outside the pixel region RA.

Needless to say, the number of pixels <NUM> and the arrangement thereof are not limited to this example. The array of the pixels <NUM> may be one-dimensional. In this case, the imaging device <NUM> can be used as a line sensor.

The individual pixels <NUM> are connected to power-supply wires <NUM>. During operation of the imaging device <NUM>, a predetermined power-supply voltage AVDD is applied to the individual pixels <NUM> through the power-supply wires <NUM>. Accumulation control lines <NUM> are connected to the individual pixels <NUM>. As will be described later in detail, each of the pixels <NUM> includes a photoelectric converting portion that photoelectrically converts incident light and a signal detection circuit that detects a signal generated by the photoelectric converting portion. In a typical embodiment, the accumulation control lines <NUM> apply a predetermined voltage to all the photoelectric converting portions in the pixels <NUM>.

In the configuration illustrated in <FIG>, the peripheral circuitry of the imaging device <NUM> includes a vertical scanning circuit <NUM>, a plurality of load circuits <NUM>, a plurality of column signal processing circuits <NUM>, a plurality of inverting amplifiers <NUM>, and a horizontal signal readout circuit <NUM>. The load circuit <NUM>, the column signal processing circuit <NUM>, and the inverting amplifier <NUM> are arranged for each column of the pixels <NUM> that are arrayed two-dimensionally. The vertical scanning circuit is also called a row scanning circuit. The column signal processing circuits are also called row signal accumulation circuits. The horizontal signal readout circuit is also called a column scanning circuit.

Address signal lines <NUM> and reset signal lines <NUM> are connected to the vertical scanning circuit <NUM>. The vertical scanning circuit <NUM> applies a predetermined voltage to the address signal lines <NUM> to thereby select, for each row, the pixels <NUM> arranged in the row. As a result of selecting the pixels <NUM> for each row, readout of signal voltages of the selected pixels <NUM> and reset of signal charge described below are executed.

In the illustrated example, feedback control lines <NUM> and sensitivity adjustment lines <NUM> are further connected to the vertical scanning circuit <NUM>. The vertical scanning circuit <NUM> applies a predetermined voltage to the feedback control lines <NUM> to thereby form feedback loops for negatively feeding back outputs of the pixels <NUM>. Also, the vertical scanning circuit <NUM> can supply a predetermined voltage to the pixels <NUM> via the sensitivity adjustment lines <NUM>.

The imaging device <NUM> has vertical signal lines <NUM> provided for the respective columns of the pixels <NUM>. The load circuits <NUM> are electrically connected to the vertical signal lines <NUM>, respectively. The pixels <NUM> are electrically connected to the column signal processing circuits <NUM> through the corresponding vertical signal lines <NUM>.

The column signal processing circuits <NUM> perform noise suppression signal processing typified by correlated double sampling, analog-to-digital conversion, and so on. The horizontal signal readout circuit <NUM> is electrically connected to the column signal processing circuits <NUM> provided corresponding to the respective columns of the pixels <NUM>. The horizontal signal readout circuit <NUM> sequentially reads out signals from the column signal processing circuits <NUM> to a horizontal common signal line <NUM>.

As shown in <FIG>, the power-supply wires <NUM>, feedback lines <NUM>, and the vertical signal lines <NUM> extend in upper and lower directions in <FIG>, that is, in column directions of the pixels <NUM>. Each of the feedback lines <NUM> and each of the vertical signal lines <NUM>, the feedback lines <NUM> and the vertical signal lines <NUM> being provided for the corresponding columns of the pixels <NUM>, have connections with corresponding two or more pixels <NUM> that are arranged along the column directions. Meanwhile, the accumulation control lines <NUM>, the reset signal lines <NUM>, the feedback control lines <NUM>, the address signal lines <NUM>, and the sensitivity adjustment lines <NUM> extend, for example, in row directions of the pixels <NUM>. These signal lines are connected to each of the pixels <NUM> arranged in the row directions. The accumulation control lines <NUM> and the sensitivity adjustment lines <NUM> may extend in the column directions of the pixels <NUM>. The accumulation control lines <NUM> and the sensitivity adjustment lines <NUM> may be connected to the individual pixels <NUM> arranged in the column directions.

In the configuration illustrated in <FIG>, the inverting amplifiers <NUM> are provided corresponding to the respective columns of the pixels <NUM>. A negative-side input terminal of each inverting amplifier <NUM> is connected to the corresponding vertical signal line <NUM>, and a predetermined voltage Vref is supplied to a positive-side input terminal of each inverting amplifier <NUM>. The voltage Vref is, for example, a positive voltage of <NUM> V or around <NUM> V. An output terminal of each inverting amplifier <NUM> is connected to the pixels <NUM> having connections with the negative-side input terminal of the inverting amplifier <NUM> through one of the feedback lines <NUM> provided corresponding to the columns of the pixels <NUM>. Each inverting amplifier <NUM> constitutes a part of the feedback circuit for negatively feeding back outputs from the pixels <NUM>. The inverting amplifiers <NUM> may be called feedback amplifiers.

<FIG> is a diagram showing one example of the circuit configuration of each of the pixels <NUM> comprised by the imaging device <NUM> according to the present embodiment. In the present embodiment, the pixels <NUM> comprised by the imaging device <NUM> have configurations that are the same.

As shown in <FIG>, each pixel <NUM> includes a photoelectric converting portion <NUM> and a signal detection circuit SC. In the configuration illustrated in <FIG>, the imaging device <NUM> includes a feedback circuit FC for negatively feeding back outputs of the signal detection circuit SC.

The photoelectric converting portion <NUM> has a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c, which serves as a pixel electrode. The first electrode 15a of the photoelectric converting portion <NUM> is connected to the accumulation control line <NUM>. The second electrode 15c of the photoelectric converting portion <NUM> is connected to a charge accumulation node <NUM>. Controlling the potential of the first electrode 15a through the accumulation control line <NUM> allows the second electrode 15c to collect charge having one of the polarities of positive (specifically, holes) charge and negative charge (specifically, electrons) generated in the photoelectric conversion layer 15b by photoelectric conversion. For example, when holes are used as the signal charge, it is sufficient that the potential of the first electrode 15a be made higher than the potential of the second electrode 15c. A case in which holes are used as the signal charge will be described below by way of example. For example, a voltage of about <NUM> V is applied to the first electrode 15a through the accumulation control line <NUM>. As a result, signal charge is accumulated at the charge accumulation node <NUM>. Electrons may also be used as the signal charge.

The signal detection circuit SC includes a signal detection transistor <NUM>, which amplifies a signal generated by the photoelectric converting portion <NUM> and outputs the signal, and a first capacitive element <NUM>. In the illustrated example, the signal detection circuit SC further includes a reset transistor <NUM>, a feedback transistor <NUM>, a second capacitive element <NUM> having a capacitance value smaller than that of the first capacitive element <NUM>, and an address transistor <NUM>. As described above, in the present embodiment, each of the pixels <NUM> has one or more capacitive elements therein. Since the first capacitive element <NUM> has a relatively large capacitance value, for example, kTC noise can be effectively reduced, as will be described later in detail. An example in which N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors) are used as transistors, such as the signal detection transistor <NUM>, will be described below.

A gate of the signal detection transistor <NUM> is connected to the charge accumulation node <NUM>. In other words, a gate of the signal detection transistor <NUM> is connected to the second electrode 15c. A drain of the signal detection transistor <NUM> is connected to the power-supply wire <NUM>, which serves as a source-follower power supply, and a source of the signal detection transistor <NUM> is connected to the vertical signal line <NUM> via the address transistor <NUM>. The signal detection transistor <NUM> and the load circuit <NUM> (see <FIG>), which is not shown in <FIG>, constitute a source follower circuit.

In the example illustrated in <FIG>, the address transistor <NUM> is connected between the source of the signal detection transistor <NUM> and the vertical signal line <NUM>. A gate of the address transistor <NUM> is connected to the address signal line <NUM>. When signal charge is accumulated in the charge accumulation node <NUM>, a voltage corresponding to the amount of the accumulated signal charge is applied to the gate of the signal detection transistor <NUM>. The signal detection transistor <NUM> amplifies the voltage applied to the gate. When the address transistor <NUM> is turned on, the voltage amplified by the signal detection transistor <NUM> is selectively read out as a signal voltage. The address transistor <NUM> may be connected between the drain of the signal detection transistor <NUM> and the power-supply wire <NUM>. That is, the drain of the signal detection transistor <NUM> may be connected to the power-supply wire <NUM> via the address transistor <NUM>.

In the configuration illustrated in <FIG>, one of a pair of electrodes of the first capacitive element <NUM> is connected to the sensitivity adjustment line <NUM>. A pad is connected to the sensitivity adjustment line <NUM>, and the potential of the sensitivity adjustment lines <NUM> is adjusted with a voltage applied to the pad. For example, during operation of the imaging device <NUM>, the potential of the sensitivity adjustment line <NUM> is fixed to a certain potential, such as <NUM> V. The sensitivity adjustment line <NUM> can be used to control the potential of the charge accumulation node <NUM>. The other of the pair of electrodes of the first capacitive element <NUM> is connected to one of a pair of electrodes of the second capacitive element <NUM>. A node including a connection point of the first capacitive element <NUM> and the second capacitive element <NUM> may hereinafter be referred to as a "reset drain node <NUM>".

The other of the pair of electrodes of the second capacitive element <NUM> is connected to the charge accumulation node <NUM>. That is, of the pair of electrodes of the second capacitive element <NUM>, the electrode that is not connected to the reset drain node <NUM> has electrical connection with the second electrode 15c of the photoelectric converting portion <NUM>. In the example illustrated in <FIG>, the reset transistor <NUM> is connected in parallel with the second capacitive element <NUM>. A gate of the reset transistor <NUM> is connected to the reset signal line <NUM>.

In the configuration illustrated in <FIG>, the pixel <NUM> includes the feedback transistor <NUM>. As shown, one of a source and a drain of the feedback transistor <NUM> is connected to the reset drain node <NUM>. The other of the source and the drain of the feedback transistor <NUM> is connected to the feedback line <NUM>. A gate of the feedback transistor <NUM> is connected to the feedback control line <NUM>.

Next, one example of the device structure of each pixel <NUM> will be described with reference to <FIG>.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by the imaging device <NUM> according to the present embodiment. <FIG> is a schematic plan view showing one example of a layout of elements included in each pixel <NUM> comprised by the imaging device <NUM> according to the present embodiment. <FIG> schematically shows a cross section along line III-III shown in <FIG>.

In <FIG>, hatching indicating a cross section is not applied to insulating layers 4a, 4b, 4c, 4d, 4e, and 4f included in an interlayer insulating layer <NUM>. The same applies to <FIG>, <FIG> and <FIG>, and <FIG>, which are described below.

As shown in <FIG>, the imaging device <NUM> has a semiconductor substrate <NUM>. For example, a silicon substrate can be used as the semiconductor substrate <NUM>. The semiconductor substrate <NUM> is not limited to a substrate that is entirely made of semiconductor material. For example, the semiconductor substrate <NUM> may be an insulating substrate provided with a semiconductor layer on its surface. In this case, a p-type silicon substrate will be described as the semiconductor substrate <NUM> by way of example.

The pixels <NUM> are each formed at the semiconductor substrate <NUM>. An element isolation region 2t formed in the semiconductor substrate <NUM> electrically isolate each of the pixels <NUM> from the other pixels <NUM>. The element isolation region 2t is formed, for example, by acceptor ion-implantation under a predetermined implantation condition.

In the example illustrated in <FIG>, the interlayer insulating layer <NUM> that covers the semiconductor substrate <NUM> is arranged between the semiconductor substrate <NUM> and the photoelectric converting portion <NUM>. The interlayer insulating layer <NUM> has a laminated structure of the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f. Each of the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f is an insulating layer formed of, for example, silicon dioxide. In this example, the photoelectric converting portion <NUM> is located on the insulating layer 4f that is located farthest from the semiconductor substrate <NUM>.

Impurity regions 2a, 2b, and 2c are formed in the semiconductor substrate <NUM>. All the impurity regions 2a, 2b, and 2c are, for example, regions where N-type dopants are diffused. A gate insulating layer <NUM> and a gate electrode 36e of the reset transistor <NUM> are provided in that order in a region located on a major surface of the semiconductor substrate <NUM> and between the impurity regions 2a and 2b. Also, a gate insulating layer <NUM> and a gate electrode 38e of the feedback transistor <NUM> are provided in that order in a region located on the major surface of the semiconductor substrate <NUM> and between the impurity regions 2b and 2c. The major surface of the semiconductor substrate <NUM> is a surface that is included in a plurality of surfaces of the semiconductor substrate <NUM> and at which the interlayer insulating layer <NUM> and the photoelectric converting portion <NUM> are provided. The major surface of the semiconductor substrate <NUM> is covered by the insulating layer 4a in the interlayer insulating layer <NUM>.

The impurity region 2a functions as one of a drain region and a source region of the reset transistor <NUM>. The impurity region 2b functions as the other of the drain region and the source region of the reset transistor <NUM>. In the example shown in <FIG>, the reset transistor <NUM> and the feedback transistor <NUM> share the impurity region 2b and are thereby electrically connected to each other. That is, the impurity region 2b also functions as one of a drain region and a source region of the feedback transistor <NUM>.

The impurity region 2c functions as the other of the drain region and the source region of the feedback transistor <NUM>. The impurity region 2c is connected to the feedback line <NUM>, which extends across two or more of the pixels <NUM>, through a plug, a via, and a wiring layer arranged in the interlayer insulating layer <NUM>. As shown in <FIG>, the feedback line <NUM> is a signal line that extends to outside of the pixel region RA.

In the configuration illustrated in <FIG>, a portion included in the feedback line <NUM> and located in one pixel <NUM> of interest is included in a wiring layer <NUM> located between the second electrode 15c of the photoelectric converting portion <NUM> and the semiconductor substrate <NUM>. Also, a wiring layer <NUM> located in the same layer as the wiring layer <NUM> also includes a portion included in the vertical signal line <NUM> and located in the pixel <NUM> of interest. That is, in this example, in the pixel <NUM>, the vertical signal line <NUM> and the feedback line <NUM> are located in the same layer. Similarly to the feedback line <NUM>, the vertical signal line <NUM> is also a signal line that extends to outside of the pixel region RA.

The "same layer" means being located on a common insulating layer. In this case, when the common insulating layer is a planarization film, heights from the major surface of the semiconductor substrate <NUM> become substantially equal to each other.

Also, the signal lines that extend to outside of the pixel region RA include not only the vertical signal line <NUM> and the feedback line <NUM> but also the reset signal line <NUM>, the feedback control line <NUM>, the address signal line <NUM>, and the sensitivity adjustment line <NUM>. At least one of the wiring layers <NUM> and <NUM> may include parts of the reset signal line <NUM>, the feedback control line <NUM>, the address signal line <NUM>, or the sensitivity adjustment line <NUM>, each of which being a control line for driving two or more pixels.

A gate insulating layer <NUM> and a gate electrode 34e of the signal detection transistor <NUM> are further provided on the major surface of the semiconductor substrate <NUM> in that order. As can be understood with reference to <FIG>, a drain region and a source region of the signal detection transistor <NUM> are located at the front side and the back side, respectively, of the plane of <FIG>. In the example illustrated in <FIG>, a pair of the reset transistor <NUM> and the feedback transistor <NUM> and a pair of the signal detection transistor <NUM> and the address transistor <NUM> (not shown in <FIG>) are isolated by an element isolation region 2u. Similarly to the element isolation region 2t, the element isolation region 2u can be formed, for example, by acceptor ion-implantation under a predetermined implantation condition. Each of the element isolation regions 2t and 2u may be an insulation region formed by an STI (Shallow Trench Isolation) process. The element isolation regions 2t and 2u are integrally formed in the pixel region.

As shown in <FIG>, each pixel <NUM> has, in the interlayer insulating layer <NUM>, a connection portion <NUM> that electrically connects the impurity region 2a in the semiconductor substrate <NUM> to the second electrode 15c of the photoelectric converting portion <NUM>. The impurity region 2a is one example of an impurity region electrically connected to the photoelectric converting portion <NUM>. The impurity region 2a functions as at least one part of a charge accumulation region in which signal charge generated by the photoelectric converting portion <NUM> is accumulated.

The connection portion <NUM> includes plugs P1 and plug P2 and a wiring portion 50a. A lower end of the plug P1 is connected to the impurity region 2a in the semiconductor substrate <NUM>, and an upper end of the plug P1 is connection to the wiring portion 50a. A lower end of the plug P2 is connected to the gate electrode 34e of the signal detection transistor <NUM>, and an upper end of the plug P2 is connected to the wiring portion 50a. The wiring portion 50a provides mutual connection between the plug P1 and the plug P2. The plugs P1 and P2 and the wiring portion 50a provide electrical interconnection between the impurity region 2a and the gate electrode 34e. That is, the impurity region 2a, which functions as the drain region or the source region of the reset transistor <NUM>, and the gate electrode 34e of the signal detection transistor <NUM> are electrically connected to the second electrode 15c of the photoelectric converting portion <NUM> via the connection portion <NUM>.

The plugs P1 and P2 and the wiring portion 50a are formed using electrically conductive material. For example, the plugs P1 and P2 and the wiring portion 50a are formed using polysilicon given electrical conductivity by impurity doping. At least one of the plugs P1 and P2 and the wiring portion 50a may be formed using metal material, such as copper.

The connection portion <NUM> further includes wiring layers 50b and 50c and vias 50d, 50e, and 50f. The via 50d, the wiring layer 50b, the via 50e, the wiring layer 50c, and the via 50f are provided between the wiring portion 50a and the second electrode 15c in that order from the semiconductor substrate <NUM>. The wiring layers 50b and 50c and the vias 50d, 50e, and 50f are formed, for example, using metal material, such as copper. Alternatively, the wiring layers 50b and 50c and the vias 50d, 50e, and 50f may be formed using electrically conductive material, such as polysilicon given electrical conductivity, other than metal material.

As shown in <FIG>, the wiring layer 50b is located in the same layer as the wiring layers <NUM> and <NUM>. For example, the wiring layer 50b, the wiring layer <NUM>, and the wiring layer <NUM> can be formed at the same time. In this case, the wiring layer 50b, the wiring layer <NUM>, and the wiring layer <NUM> are the same in thickness and material. Accordingly, the wiring layers <NUM> and <NUM> may also be formed of metal, such as copper.

The number of wiring layers arranged in the interlayer insulating layer <NUM> and the number of insulating layers in the interlayer insulating layer <NUM> are not limited to the example illustrated in <FIG> and ca be set arbitrarily.

The photoelectric converting portion <NUM> supported by the semiconductor substrate <NUM> includes the first electrode 15a, the photoelectric conversion layer 15b, and the second electrode 15c. The photoelectric converting portion <NUM> has a structure in which the photoelectric conversion layer 15b is sandwiched between the first electrode 15a and the second electrode 15c.

The first electrode 15a of the photoelectric converting portion <NUM> is provided at a side on which light from a subject is incident. The first electrode 15a is formed of transparent electrically conductive material, such as ITO (indium tin oxide). The first electrode 15a may be formed directly on the photoelectric conversion layer 15b or another layer may be arranged between the first electrode 15a and the photoelectric conversion layer 15b.

In response to incidence of light, the photoelectric conversion layer 15b causes positive and negative charge, specifically, hole-electron pairs, to be generated. The photoelectric conversion layer 15b is formed of organic material or inorganic material, such as amorphous silicon. The photoelectric conversion layer 15b may include a layer composed of organic material and a layer composed of inorganic material.

The second electrode 15c is located closer to the semiconductor substrate <NUM> than the first electrode 15a and the photoelectric conversion layer 15b. The second electrodes 15c are provided separately for the respective pixels <NUM>. Specifically, each second electrode 15c is spatially isolated from the second electrodes 15c in other adjacent pixels <NUM>, so that the second electrode 15c is electrically isolated therefrom. The second electrode 15c collects charge generated by photoelectric conversion in the photoelectric conversion layer 15b. The second electrode 15c is formed of, for example, metal such as aluminum or copper, metal nitride, polysilicon, or the like given electrical conductivity by impurity doping.

The first electrode 15a and the photoelectric conversion layer 15b are formed, for example, through two or more pixels <NUM>. Alternatively, similarly to the second electrode 15c, at least one of the first electrode 15a and the photoelectric conversion layer 15b in one pixel <NUM> may be spatially isolated from the at least one electrode in another pixel <NUM>.

In the present embodiment, the first capacitive element <NUM> is provided in the interlayer insulating layer <NUM> between the photoelectric converting portion <NUM> and the semiconductor substrate <NUM>. Specifically, the first capacitive element <NUM> is located between the wiring layers <NUM> and <NUM>, which include at least parts of signal lines connected to two or more pixels <NUM>, and the semiconductor substrate <NUM>. In the configuration illustrated in <FIG>, the first capacitive element <NUM> is located between the wiring layer <NUM>, which includes a part of the vertical signal line <NUM>, and the wiring layer <NUM>, which includes a part of the feedback line <NUM>, and the semiconductor substrate <NUM>. In other words, in the present embodiment, the first capacitive element <NUM> has an arrangement such that it is located closer to the semiconductor substrate <NUM> than the wiring layers including parts of the signal lines connected to two or more pixels <NUM>. That is, in the present embodiment, of the wiring layers comprised by the imaging device <NUM>, the number of wiring layers located at an upper side of the first capacitive elements <NUM> is larger than the number of wiring layers located at a lower side of the first capacitive elements <NUM>. A wiring layer does not have to be provided at the lower side of the first capacitive elements <NUM>.

Each first capacitive element <NUM> has a top electrode 41a, a bottom electrode 41c, and a dielectric layer 41b arranged between the top electrode 41a and the bottom electrode 41c. The top electrode 41a is one example of a second electrode and is located between the wiring layer <NUM> and the semiconductor substrate <NUM> in the sectional view shown in <FIG>. The bottom electrode 41c is one example of a first electrode and is located between the top electrode 41a and the semiconductor substrate <NUM>.

The bottom electrode 41c, the dielectric layer 41b, and the top electrode 41a are laminated in that order from the semiconductor substrate <NUM>. The dielectric layer 41b is in contact with the bottom electrode 41c to cover the entire bottom electrode 41c. The bottom electrode 41c is covered by the dielectric layer 41b and is thus not exposed to outside. The top electrode 41a is in contact with the dielectric layer 41b to cover the dielectric layer 41b. The top electrode 41a and the bottom electrode 41c are not in contact with each other, since the dielectric layer 41b is arranged therebetween.

The first capacitive element <NUM> is a trench capacitor. Specifically, the first capacitive element <NUM> includes at least one trench portion. In the example shown in <FIG>, the first capacitive element <NUM> includes a planar portion 41d and two trench portions 41e and 41f. The two trench portions 41e and 41f are provided so as to sandwich the connection portion <NUM> therebetween in sectional view.

The planar portion 41d is a portion that is included in the first capacitive element <NUM> and that is located on an upper surface of the insulating layer 4c. The trench portion 41e is a portion that is included in the first capacitive element <NUM> and that is located in a trench 4t provided in the insulating layer 4c. The trench portion 41f is a portion that is included in the first capacitive element <NUM> and that is located in a trench 4u provided in the insulating layer 4c. In each of the planar portion 41d and the trench portions 41e and 41f, the bottom electrode 41c and the dielectric layer 41b are formed with a generally uniform film thickness. The top electrode 41a is provided so as to fill insides of the trenches 4t and 4u. Alternatively, the top electrode 41a may also be formed with a generally uniform film thickness.

With this configuration, not only the planar portion 41d but also the trench portions 41e and 41f contribute to a capacitance value of the first capacitive element <NUM>. Compared with a parallel flat plate capacitor that does not have the trench portions 41e and 41f, the first capacitive element <NUM> has a capacitance value increased by an amount corresponding to the surface areas of wall surfaces of the trenches 4t and 4u. Thus, since the first capacitive element <NUM> includes the trench portions 41e and 41f, it is possible to increase the capacitance value, while suppressing an increase in the area occupied in plan view. The first capacitive element <NUM> may have only one of the trench portions 41e and 41f.

In the present embodiment, at least one of the bottom electrode 41c and the top electrode 41a has two or more electrical contact points. The two or more electrical contact points are electrically connected to different electrical elements, respectively. In the example shown in <FIG>, the bottom electrode 41c has two contact points <NUM> and <NUM>. The two contact points <NUM> and <NUM> are provided at the trench portions 41e and 41f, respectively.

Specifically, the contact point <NUM> is provided at a bottom surface of the trench portion 41e. The bottom surface refers to a surface (specifically, a lower surface) of the trench portion 41e, the surface being adjacent to the semiconductor substrate <NUM>. The contact point <NUM> is a point of contact with a via v1 at the bottom surface of the trench portion 41e. The via v1 is coupled to the impurity region 2b via a plug P3. That is, the contact point <NUM> is electrically connected to the reset transistor <NUM> and the feedback transistor <NUM>. Each of the reset transistor <NUM> and the feedback transistor <NUM> is one example of an electrical element to which the contact point <NUM> is electrically connected. As described above, one contact point included in the first capacitive element may be connected to a plurality of electrical elements.

The contact point <NUM> is provided at a bottom surface of the trench portion 41f. The contact point <NUM> is a point of contact with a via v2 at the bottom surface of the trench portion 41f. The via v2 is coupled to an electrode 42a. The electrode 42a overlaps the gate electrode 34e with an insulating film 42b being interposed therebetween. That is, the electrode 42a and the gate electrode 34e constitute the second capacitive element <NUM>. The second capacitive element <NUM> is one example of an electrical element to which the contact point <NUM> is electrically connected. As described above, the contact point <NUM> and the contact point <NUM> are respectively connected to the electrical elements that are different from each other.

A desired capacitance value can be realized for a capacitance value of the second capacitive element <NUM> by adjusting the material or the thickness of the insulating film 42b or the area where the electrode 42a and the gate electrode 34e overlap each other.

Although a method for forming the first capacitive element <NUM> is described later, providing the contact points <NUM> and <NUM> of the bottom electrode 41c at the bottom surfaces of the trench portions 41e and 41f makes it possible to reduce the value of contact resistance between the bottom electrode 41c and the vias v1 and v2. This makes it possible to suppress variations in the value of the contact resistance in each pixel <NUM>.

The bottom electrode 41c of the first capacitive element <NUM>, the via v1, the plug P3, the via v2, and the electrode 42a constitute parts of the reset drain node <NUM>. As shown in <FIG>, the charge accumulation node <NUM> is electrically coupled with the reset drain node <NUM> via the second capacitive element <NUM>. Thus, the potential of the charge accumulation node <NUM> can vary upon a potential variation in the reset drain node <NUM>.

That is, even when the contact resistance between the bottom electrode 41c and the vias v1 and v2 vary among the pixels <NUM>, this variation leads to a fluctuation of the potential of the reset drain node <NUM>. For example, even when light with the same amount of light is incident on the individual pixels <NUM>, and the same amounts of charge are generated from the photoelectric converting portions <NUM>, the potentials of the charge accumulation nodes <NUM> do not become the same among the pixels <NUM> when the potentials of the reset drain nodes <NUM> vary. Thus, an image that is acquired looks like noise (also called roughness) is occurring.

In the present embodiment, reducing the resistance values of the reset drain nodes <NUM> makes it possible to bring the potentials of the reset drain nodes <NUM> in all the pixels <NUM> close to a constant potential.

The top electrode 41a of the first capacitive element <NUM> can be a part of the wiring layers located between the second electrode 15c of the photoelectric converting portion <NUM> and the gate electrode 34e of the signal detection transistor <NUM>. The top electrode 41a is electrically connected to a pad not shown in <FIG>. The pad is, for example, a portion to which a predetermined voltage is applied. For example, the pad is connected to the top electrode 41a through the sensitivity adjustment line <NUM>. As shown in <FIG>, the top electrode 41a extends in a plane that is parallel to the major surface of the semiconductor substrate <NUM>. The same applies to the bottom electrode 41c and the dielectric layer 41b.

Each of the top electrode 41a and the bottom electrode 41c is formed using electrically conductive material, such as metal or a metal compound. A metal simple substance, such as titanium (Ti), aluminum (Al), gold (Au), or platinum (Pt), or a metal alloy of two or more types thereof is used as the electrically conductive material. Alternatively, electrically conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or hafnium nitride (HfN), may be used as the electrically conductive material. The top electrode 41a and the bottom electrode 41c may be formed using the same type of material or may be formed using types of material that are different from each other.

The dielectric layer 41b is formed using a so-called high-k material having a higher dielectric constant than silicon oxide. Specifically, the dielectric layer 41b contains hafnium (Hf) or zirconium (Zr) oxide of as a main component.

As described above, the first capacitive element <NUM> has a "MIM (metal-insulator-metal) structure" in which a dielectric body is sandwiched between two electrodes formed of metal or a metal compound. In this case, in order to equalize the potentials of the reset drain nodes <NUM> in the pixels <NUM>, it is desirable that leakage current that flows between the top electrode 41a and the bottom electrode 41c be reduced as much as possible. This is because, when leakage current is large, the charge of the reset drain node <NUM> flows through the sensitivity adjustment line <NUM> connected to the top electrode 41a.

In theory, there should be no leakage current that flows via the dielectric layer 41b located between the top electrode 41a and the bottom electrode 41c. However, in the present embodiment, a high-k material having a high refractive index is used for the dielectric layer 41b in order to increase the capacitance value of the first capacitive element <NUM>. Thus, the bandgap of the dielectric layer 41b is reduced. Also, for the same purpose, the film thickness of the dielectric layer 41b is reduced in a range of about <NUM> or more and about <NUM> or less. For these reasons, in practice, the leakage current tends to increase.

In order to suppress the leakage current, surface roughness of the top electrode 41a and the bottom electrode 41c may be reduced. The leakage current and the surface roughness of each electrode have a relationship in which the leakage current increases as the surface roughness increases. For example, when the surface roughness of the top electrode 41a and the bottom electrode 41c is high, the thickness of the dielectric layer 41b becomes uneven. Since an electric field tends to be concentrated at a portion where the dielectric layer 41b is thin, the leakage current is likely to increase.

In contrast, in the present embodiment, for example, TiN or TaN is used as the electrically conductive material of which the top electrode 41a and the bottom electrode 41c are formed. Thus, since TiN or TaN allows the surface roughness to be reduced when it is deposited, the leakage current of the first capacitive element <NUM> can be suppressed. Also, making the surface roughness of the bottom electrode 41c of the top electrode 41a uniform can also contribute to suppressing variations in the capacitance value of the first capacitive element <NUM> in each pixel <NUM>. Also, since TiN or TaN has a low sheet resistance, it is possible to reduce resistance components that occur at the reset drain node <NUM>.

<FIG> is a schematic plan view showing one example of the shapes and the arrangements of the first capacitive element <NUM> and the trench portions 41e and 41f included in each pixel <NUM> comprised by the imaging device <NUM> according to the present embodiment. Specifically, <FIG> shows one example of positional relationships of the top electrode 41a, the trench portions 41e and 41f, the vias v1 and v2, the impurity regions 2b and 2c, and the second capacitive element <NUM>, excluding the photoelectric converting portion <NUM> from the pixel <NUM>, when viewed in a normal direction of the major surface of the semiconductor substrate <NUM>.

In the example illustrated in <FIG>, the vias v1 and v2 are formed at approximately centers of the respective trench portions 41e and 41f. The outer shapes of the trench portions 41e and 41f are denoted by thick solid lines. The via v1 is located immediately above the impurity region 2b to which it is connected. The via v2 is located immediately above the electrode 42a. The arrangements and the shapes of the trench portions 41e and 41f are not particularly limited.

As illustrated in <FIG>, according to the present embodiment, the first capacitive element <NUM> in one pixel <NUM> has two or more trench portions 41e and 41f. As shown in <FIG>, the contact points <NUM> and <NUM> are provided at respective bottom surfaces of the trench portions 41e and 41f. Since the contact points <NUM> and <NUM> obtain electrical connections with the respective different electrical elements, the reset drain node <NUM> can be designed with a shortest path and in accordance with a circuit diagram. Also, the reset drain node <NUM> is formed in a layer at a lower side of the wiring layer <NUM> including the feedback line <NUM> provided through two or more pixels <NUM> and the wiring layer <NUM> including the vertical signal line <NUM>. Thus, the reset drain node <NUM> has a structure that is less vulnerable to influences of noise, thus making it possible to reduce influences of parasitic capacitance.

As shown in <FIG>, the first capacitive element <NUM> is provided so as to occupy a majority portion of the pixels <NUM> in plan view. The plan-view shape of the first capacitive element <NUM> is generally rectangle, and an opening AP is provided at a center thereof. The plan-view shape of the first capacitive element <NUM> is substantially the same as the plan-view shape of the top electrode 41a. The opening AP is a through-hole for passage of the connection portion <NUM>. The position where the opening AP is provided is not particularly limited.

Also, in the present embodiment, as can be understood with reference to <FIG>, the first capacitive element <NUM> overlaps at least a part of the impurity region 2a in plan view. Specifically, at least one of the top electrode 41a and the bottom electrode 41c overlaps the impurity region 2a. For example, both the top electrode 41a and the bottom electrode 41c cover the entire impurity region 2a. That is, in plan view, the entire impurity region 2a is located inside the top electrode 41a and the bottom electrode 41c.

Each of the top electrode 41a and the bottom electrode 41c has a light-shielding property. Thus, light that is incident on the imaging device <NUM> and that travels in the interlayer insulating layer <NUM> without being photoelectrically converted by the photoelectric converting portion <NUM> is shielded by the top electrode 41a or the bottom electrode 41c. This makes it possible to suppress light that reaches the impurity region 2a. When light is incident on the impurity region 2a, charge is generated, which can cause noise. Suppression of light that reaches the impurity region 2a makes it possible to reduce noise.

Subsequently, a manufacturing method for the imaging device <NUM> according to the present embodiment, particularly, a process for manufacturing the first capacitive element <NUM>, will be described using <FIG> are sectional views for describing a plurality of processes included in a process for manufacturing the first capacitive element <NUM>. Although a description will be given below while paying attention to one trench portion 41e, the same description also applies to the trench portion 41f.

First, as shown in <FIG>, the vias v1 and v3 are formed in the insulating layer 4b deposited at an upper side of the semiconductor substrate <NUM> (not illustrated). In this case, although not shown in <FIG>, the via v2 is formed at the same time. Specifically, first, a plasma CVD (Chemical Vapor Deposition) method or the like is used to form a silicon oxide film as the insulating layer 4b. Thereafter, the deposited insulating layer 4b is patterned by photolithography and etching to thereby form contact holes h1 and h3. Next, a vapor deposition method, a sputtering method, a CVD method, plating, or the like is used to fill the contact holes h1 and h3 with metal material, such as tungsten (W) or copper (Cu), to thereby form the vias v1 and v3.

The via v1 is, for example, an electrically conductive via connected to the bottom electrode 41c of the first capacitive element <NUM>. In the example shown in <FIG>, the via v3, in addition to the via v1, is formed at the same time. The via v3 is a part of the via 50d included in the connection portion <NUM> connected to the second electrode 15c of the photoelectric converting portion <NUM>.

Next, as shown in <FIG>, an insulating layer <NUM> and the insulating layer 4c are sequentially formed on an entire surface of the insulating layer 4b by a plasma CVD method. The insulating layer <NUM> is, for example, a silicon carbon nitride film (SiCN film). The insulating layer 4c is, for example, a silicon oxide film. The silicon carbon nitride film makes it possible to suppress diffusion of metal included in the vias v1 and v3. Illustration of the insulating layer <NUM> is omitted in <FIG>. Also, the formation of the insulating layer <NUM> is not essential and may be omitted.

Next, as shown in <FIG>, the trench 4t that penetrates the insulating layer <NUM> and the insulating layer 4c is formed by dry etching. The trench 4t is a through-hole for exposing the via v1. When the first capacitive element <NUM> includes two or more trench portions, the trenches are formed at the same time. For example, the trenches 4t and 4u are formed at the same time.

Next, as shown in <FIG>, the bottom electrode 41c is formed. Specifically, first, an electrically conductive thin film, such as a titanium nitride film, is deposited. The titanium nitride film is formed, for example, by an ALD (Atomic Layer Deposition) method or a plasma CVD method. Next, after a resist mask is formed on the deposited electrically conductive thin film, for example, a part of the electrically conductive thin film is removed by dry etching using chlorine (Cl<NUM>) gas, and the resist mask is removed by oxygen ashing processing. As a result, the bottom electrode 41c patterned to have a predetermined shape is formed, as shown in <FIG>.

Continuously performing the formation process of the trench 4t and the deposition process of the electrically conductive thin film that constitutes the bottom electrode 41c makes it possible to reduce a contact resistance between the bottom electrode 41c and the via v1. In the process of forming the trench 4t, since a surface of the via v1 needs to be exposed to plasma, the state of the surface at which the via v1 is exposed is activated. In addition, forming the electrically conductive thin film facilitates that metal coupling is formed between the electrically conductive thin film and the via v1, thus making it possible to suppress the contact resistance.

Next, as shown in <FIG>, the dielectric layer 41b is formed. Specifically, first, a dielectric film is deposited on an entire surface of the insulating layer 4c so as to cover the bottom electrode 41c. The dielectric film is, for example, a hafnium oxide film. The hafnium oxide film is formed, for example, by an ALD method or a plasma CVD method. Next, after a resist mask is formed on the deposited dielectric film, for example, a part of the dielectric film is removed by dry etching using chlorine gas, and the resist mask is removed by oxygen ashing processing. As a result, as shown in <FIG>, the dielectric layer 41b patterned to have a predetermined shape is formed. At this point in time, leaving the dielectric layer 41b larger than the bottom electrode 41c allows the dielectric layer 41b to entirely cover the bottom electrode 41c so that an end portion of the bottom electrode 41c is not exposed.

Next, as shown in <FIG>, the top electrode 41a is formed. Specifically, first, an electrically conductive thin film, such as a titanium nitride film, is deposited on an entire surface of the insulating layer 4c so as to cover the dielectric layer 41b. The titanium nitride film is formed, for example, by an ALD method or a plasma CVD method. Next, after a resist mask is formed on the deposited electrically conductive thin film, for example, a part of the electrically conductive thin film is removed by dry etching using chlorine gas. As a result, as shown in <FIG>, the top electrode 41a patterned to have a predetermined shape is formed. At this point in time, leaving the top electrode 41a larger than the dielectric layer 41b allows the top electrode 41a to entirely cover the dielectric layer 41b so that an end portion of the dielectric layer 41b is not exposed.

After the bottom electrode 41c is formed, the dielectric film and the electrically conductive thin film may be deposited continuously. After the dielectric film and the electrically conductive thin film are deposited continuously, the electrically conductive thin film, and the dielectric film may be sequentially patterned to thereby form the top electrode 41a and the dielectric layer 41b having predetermined shapes. In this case, an end portion of the top electrode 41a and an end portion of the dielectric layer 41b are generally flush with each other, so that the plan-view shapes of the top electrode 41a and the dielectric layer 41b become generally the same.

Through the above-described processes, the first capacitive element <NUM> including the planar portion 41d and the trench portion 41e is formed.

Next, as shown in <FIG>, the insulating layer 4d is deposited on an entire surface so as to cover the top electrode 41a of the first capacitive element <NUM>. The insulating layer 4d is, for example, a silicon oxide film.

Next, as shown in <FIG>, vias v4 and v5, the wiring layer 50b, and a wiring layer <NUM> are formed. The formation of the vias v4 and v5 is performed in the same manner as the vias v1 and v3. That is, after contact holes are formed by photolithography and etching, the formed contact holes are filled with metal material to thereby form the vias v4 and v5.

The via v4 is a part of the via 50d included in the connection portion <NUM>. Although not shown in <FIG>, the via v5 and the wiring layer <NUM> are portions that provide electrical connection between the top electrode 41a of the first capacitive element <NUM> and the sensitivity adjustment line <NUM>. In <FIG>, although the via v5 is provided so as to penetrate the top electrode 41a, the via v5 may be in contact with an upper surface of the top electrode 41a.

In addition, formation of the insulating layer 4e and formation of the via 50e, a via v6, the wiring layer 50c, and a wiring layer <NUM> are performed, as shown in <FIG>. Specific formation methods are analogous to the formation method of the insulating layer 4d and the formation method of the vias v4 and v5 and the wiring layers 50b and <NUM>.

Repeating the formation of the insulating layer, the vias, and the wiring layer makes it possible to form the interlayer insulating layer <NUM> having a desired number of laminated layers. This allows various signal lines including the sensitivity adjustment lines <NUM> to be drawn out of the pixel region.

Now, a modification of the first embodiment will be described with reference to <FIG>.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by an imaging device according to this modification. As shown in <FIG>, an electrical contact point 41i is provided at a side surface of the trench portion 41f in the first capacitive element <NUM>. Specifically, the bottom electrode 41c of the first capacitive element <NUM> has the electrical contact point 41i. The electrical contact point 41i is a coupling portion of the bottom electrode 41c and a wiring layer <NUM>.

In this modification, the trench portion 41f is provided so as to penetrate the insulating layer 4c and an insulating layer <NUM>. The insulating layer <NUM> is an insulating layer located between the insulating layer 4b and the insulating layer 4c. Since the trench portion 41f is provided so as to penetrate the plurality of insulating layers 4c and <NUM>, the wiring layer <NUM> can be provided between the insulating layer 4c and the insulating layer <NUM>. Thus, the contact point 41i can be formed at the side surface of the trench portion 41f.

The number of insulating layers penetrated by the trench portion 41f is not limited to two and may be three or more. This allows a plurality of electrical contact points to be provided at different heights at the side surface of the trench portion 41f.

The wiring layer <NUM> is electrically connected to an upper end of the via v2. The wiring layer <NUM> is formed so as to be exposed at a side surface of the trench 4u provided in the insulating layers 4c and <NUM>. Thus, forming the bottom electrode 41c along the side surface of the trench 4u allows the wiring layer <NUM> and the bottom electrode 41c to be electrically connected to each other. The first capacitive element <NUM> is connected to the electrode 42a of the second capacitive element <NUM> through the electrical the contact point 41i of the bottom electrode 41c, the wiring layer <NUM>, and the via v2.

As described above, the electrical contact point of the bottom electrode 41c of the first capacitive element <NUM> does not have to be provided at a bottom portion of the trench portion 41f and may be provided at the side surface of the trench portion 41f. Also, an electrical contact point of the bottom electrode 41c may be provided at the planar portion 41d of the first capacitive element <NUM>.

Subsequently, a second embodiment will be described.

Compared with the imaging device according to the first embodiment, an imaging device according to the second embodiment differs in the number of trench portions included in a first capacitive element. Hereinafter, points that differ from the first embodiment will be mainly described, and descriptions of common points will be omitted or briefly given.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by the imaging device according to the present embodiment. <FIG> is a schematic plan view showing one example of the shapes and the arrangements of a first capacitive element <NUM> and trench portions included in each pixel <NUM> comprised by the imaging device according to the present embodiment.

Compared with the pixel <NUM> according to the first embodiment, the pixel <NUM> differs in that it comprises the first capacitive element <NUM> instead of the first capacitive element <NUM>, as shown in <FIG>. The first capacitive element <NUM> includes three or more trench portions. Specifically, as shown in <FIG>, the first capacitive element <NUM> includes six trench portions 41e, 41f, 141a, 141b, 141c, and 141d.

As shown in <FIG>, the trench portions 41e and 41f are provided with electrical contact points <NUM> and <NUM>, as in the first embodiment. The trench portions 141a, 141b, 141c, and 141d are not provided with electrical contact points. A bottom surface and a side surface of the trench portion 141a are respectively in contact with the insulating layers 4b and 4c and are covered thereby. As shown in <FIG>, a vias that overlaps the trench portion 141a in plan view is not provided. The same also applies to the trench portions 141b, 141c, and 141d.

Thus, in the present embodiment, since the first capacitive element <NUM> includes a large number of trench portions, the capacitance value can be increased. A specification value of the capacitance value of the first capacitive element <NUM>, in many cases, varies depending on the type of image sensor. For example, when a bright scene is shot, the reset transistor <NUM> is put into an on state, and not only the charge accumulation node <NUM> but also the reset drain node <NUM> can be used as a charge accumulation portion. In this case, the larger the capacitance value of the first capacitive element <NUM> is, the less likely a gate potential of the signal detection transistor <NUM> increases, even when a large amount of charge is accumulated. Thus, a conversion gain can be switched, so that an image in which highlight clipping does not occur can be provided even for a bright scene.

The number of trench portions that are not provided with electrical contact points is not limited to four. The number of trench portions that are not provided with electrical contact points may be only one, may be two or three, or may be five or more. Also, the number of trench portions that are provided with electrical contact points is not limited to two, may be only one, or may be three or more.

In the present embodiment, as shown in <FIG> and <FIG>, the wiring layers <NUM> and <NUM> are provided at an upper side of the first capacitive element <NUM>. As described above, in one example, the wiring layers <NUM> and <NUM> include the vertical signal line <NUM>, the feedback line <NUM>, and so on.

In this case, parasitic capacitances occur between the top electrode 41a of the first capacitive element <NUM> and the wiring layers <NUM> and <NUM>. In particular, the potentials of the vertical signal line <NUM> and the feedback line <NUM> vary with time in accordance with the corresponding pixel <NUM>. Thus, parasitic capacitance components are detected as noise components in the vertical signal line <NUM> and the feedback line <NUM>.

A parasitic capacitance value is proportional to a dielectric constant of an insulating film between the wiring layers <NUM> and <NUM> and the top electrode 41a and to a difference voltage that occurs therebetween. In contrast, in order to reduce the parasitic capacitance value, the top electrode 41a of the first capacitive element <NUM> and the wiring layers <NUM> and <NUM> may be arranged so as not to overlap each other, as shown in <FIG>. This makes it possible to suppress noise components based on the parasitic capacitance. <FIG> is a schematic plan view showing one example of the shapes and the arrangements of the first capacitive element <NUM> and trench portions included in each pixel <NUM> comprised by an imaging device according to a modification of the second embodiment.

In this modification, as can be understood from comparison between <FIG> and <FIG>, the area that the first capacitive element <NUM> occupies in the pixel in plan view is reduced. Thus, the capacitance value of the planar portion 41d of the first capacitive element <NUM> decreases.

Meanwhile, in order for the first capacitive element <NUM> to achieve a desired capacitance value, the first capacitive element <NUM> needs to ensure a certain electrode area in plan view. Ensuring the electrode area and suppressing overlap with the wiring layers are in a trade-off relationship. That is, when the electrode area is increased, it is difficult to avoid overlap with the wiring layers.

In contrast, in the first capacitive element <NUM> according to this modification, providing the plurality of trench portions 41e, 41f, 141a, 141b, 141c, and 141d while avoiding overlap with the wiring layers in plan view makes it possible to obtain an electrode area by utilizing the sidewalls of the trench portions. This makes it possible to increase the capacitance value of the first capacitive element <NUM> while suppressing noise components caused by parasitic capacitance.

Subsequently, a third embodiment will be described.

In an imaging device according to the third embodiment, the circuit configuration thereof differs compared with the imaging devices according to the first and second embodiments. Hereinafter, points that differ from the first and second embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

<FIG> is a diagram showing one example of a circuit configuration of each pixel <NUM> comprised by the imaging device according to the present embodiment. As shown in <FIG>, compared with the pixel <NUM> according to the first embodiment, the pixel <NUM> differs in that it does not comprise the second capacitive element <NUM> and the feedback transistor <NUM>. In the pixel <NUM>, the reset drain node <NUM> is not provided. Also, in the pixel <NUM>, the reset transistor <NUM> is provided between one of a pair of electrodes of the first capacitive element <NUM> and the feedback line <NUM>. That is, the reset transistor <NUM> is provided at the same position as the feedback transistor <NUM> according to the first embodiment.

As shown in <FIG>, the charge accumulation node <NUM> is connected to one of the pair of electrodes of the first capacitive element <NUM>. Thus, the first capacitive element <NUM> functions as a charge accumulation portion. That is, signal charge generated in the photoelectric converting portion <NUM> is also accumulated in the first capacitive element <NUM>. This makes it possible to increase the amount of signal charge accumulated in the pixel <NUM>, thus making it possible to suppress occurrence of highlight clipping even in a bright scene.

<FIG> is a schematic sectional view of the pixel <NUM> comprised by the imaging device according to the present embodiment. As shown in <FIG>, the reset transistor <NUM>, instead of the feedback transistor <NUM> illustrated in <FIG>, is provided at the same position as the feedback transistor <NUM>. That is, the impurity region 2b is one of a source region and a drain region of the reset transistor <NUM>. The impurity region 2c is the other of the source region and the drain region of the reset transistor <NUM>.

Also, as shown in <FIG>, the pixel <NUM> comprises a connection portion <NUM> instead of the connection portion <NUM>. The connection portion <NUM> does not comprise the plug P1 and the wiring portion 50a shown in <FIG>. The connection portion <NUM> provides electrical connection between the second electrode 15c of the photoelectric converting portion <NUM> and the gate electrode 34e of the signal detection transistor <NUM>.

The gate electrode 34e is connected to the via v2 through a plug P4 and a wiring portion 250a. The via v2 is connected to the bottom electrode 41c of the first capacitive element <NUM>, as in the first embodiment. With this configuration, as shown in <FIG>, the second electrode 15c of the photoelectric converting portion <NUM> is connected to the impurity region 2b through the connection portion <NUM>, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the bottom electrode 41c of the first capacitive element <NUM>, the via v1, and the plug P3. That is, the second electrode 15c, the connection portion <NUM>, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the bottom electrode 41c of the first capacitive element <NUM>, the via v1, the plug P3, and the impurity region 2b serve as the charge accumulation node <NUM>.

As described above, in the present embodiment, since the capacity of the charge accumulation portion in which the signal charge generated by the photoelectric converting portion <NUM> is accumulated can be increased, it is possible to suppress occurrence of highlight clipping even in a bright scene.

Subsequently, a fourth embodiment not part of the invention will be described.

Compared with the imaging device according to each of the first to third embodiments, an imaging device according to the fourth embodiment differs in that an electrical contact point is provided at the top electrode. Hereinafter, points that differ from the first to third embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by the imaging device. As shown in <FIG>, compared with the pixel <NUM> according to the first embodiment, the pixel <NUM> comprises a connection portion <NUM> instead of the connection portion <NUM>.

The connection portion <NUM> includes a plug P5, a wiring portion 350a, an electrode 342a, vias v7, 350d, 50e, and 50f, and the wiring layers 50b and 50c. The connection portion <NUM> provides electrical connection between the second electrode 15c of the photoelectric converting portion <NUM> and the gate electrode 34e of the signal detection transistor <NUM>. Also, although not shown in <FIG>, the gate electrode 34e is electrically connected to the impurity region 2a.

Also, as shown in <FIG>, the pixel <NUM> comprises a first capacitive element <NUM> and a second capacitive element <NUM>, instead of the first capacitive element <NUM> and the second capacitive element <NUM>, compared with the pixel <NUM> according to the first embodiment. The first capacitive element <NUM> has a top electrode 341a, the dielectric layer 41b, and the bottom electrode 41c.

The top electrode 341a of the first capacitive element <NUM> has an electrode portion 342b. The electrode portion 342b is a portion provided so as to extend from the top electrode 341a onto the upper surface of the insulating layer 4c. Specifically, in plan view, the electrode portion 342b overlaps a part of the electrode 342a included in the connection portion <NUM>. Thus, the electrode portion 342b and the part of the electrode 342a form the second capacitive element <NUM>.

Also, the top electrode 341a of the first capacitive element <NUM> has contact points <NUM> and <NUM>. The contact points <NUM> and <NUM> are provided at portions that are included in the top electrode 341a and that extend onto the insulating layer 4c.

The contact point <NUM> is provided at a bottom surface of the top electrode 341a. The contact point <NUM> is connected to a via v8 and is connected to the impurity region 2b through the via v8 and the plug P3. That is, the contact point <NUM> is connected to the reset transistor <NUM> and the feedback transistor <NUM>. In the present embodiment, each of the reset transistor <NUM> and the feedback transistor <NUM> is one example of an electrical element to which the contact point <NUM> is electrically connected, as in the first embodiment.

The contact point <NUM> is a connection portion of the top electrode 341a and the electrode portion 342b. That is, the contact point <NUM> is connected to the second capacitive element <NUM>. In the present embodiment, the second capacitive element <NUM> is one example of an electrical element to which the contact point <NUM> is electrically connected.

In the example illustrated in <FIG>, the bottom electrode 41c is also provided with the contact point <NUM>. The contact point <NUM> is connected to the via v1. Although not shown in <FIG>, the contact point <NUM> is connected to the sensitivity adjustment line <NUM> through the via v1.

As described above, in the imaging device according to the present embodiment, two contact points <NUM> and <NUM> are provided at the top electrode 341a of the first capacitive element <NUM>. Also, the contact points <NUM> and <NUM> are provided at portions other than the trench portion 41e in the first capacitive element <NUM>. Also, the contact points <NUM> and <NUM> may be provided at an upper surface of the top electrode 341a. That is, the via provided on the first capacitive element <NUM> and the top electrode 341a may be electrically connected.

Also, at least one contact point may be provided at the top electrode 341a of the trench portion 41e. For example, although, in <FIG>, the top electrode 341a is provided so as to fill the trench 4t, the top electrode 341a may also be configured with a uniform film thickness in the trench 4t and may have a shape that is curved along a bottom surface and a side surface of the trench 4t, similarly to the dielectric layer 41b and the bottom electrode 41c. In this case, a contact point may be provided at an inner bottom surface of the top electrode 341a in the trench portion 41e. Alternatively, the contact point may be provided at an inner side surface of the top electrode 341a in the trench portion 41e.

Subsequently, a fifth embodiment not part of the invention will be described.

Compared with the imaging device according to each of the first to fourth embodiments, an imaging device according to the fifth embodiment differs in that the photoelectric converting portion is provided in the semiconductor substrate. Hereinafter, points that differ from the first to fourth embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by the imaging device.

As shown in <FIG>, the pixel <NUM> comprises a photodiode PD instead of the photoelectric converting portion <NUM>. The photodiode PD is one example of a photoelectric converting portion and is, for example, a photodiode having a P-N junction. The photodiode PD is formed by an impurity region or the like formed in the semiconductor substrate <NUM>.

The imaging device according to the present embodiment is a backside-illuminated CMOS image sensor. The backside refers to one of two major surfaces of the semiconductor substrate <NUM> and is a surface opposite to the major surface at which the interlayer insulating layer <NUM> is provided. In the imaging device according to the present embodiment, light is incident from the backside of the semiconductor substrate <NUM>, that is, from an upper side in the plane of <FIG>.

Also, the imaging device according to the present embodiment has a chip-stack structure. Specifically, the imaging device comprises a first chip 410a and a second chip 410b. The first chip 410a and the second chip 410b are arranged one on another, that is, are stacked, in vertical directions.

As shown in <FIG>, the first chip 410a comprises the semiconductor substrate <NUM> and the interlayer insulating layer <NUM>. The second chip 410b comprises a semiconductor substrate <NUM> and an interlayer insulating layer <NUM>. After the first chip 410a and the second chip 410b are respectively manufactured, they are arranged one on another to thereby form the imaging device comprising the pixels <NUM>. Specifically, the interlayer insulating layer <NUM> formed on a major surface of the semiconductor substrate <NUM> and the interlayer insulating layer <NUM> formed on the major surface of the semiconductor substrate <NUM> are bonded to each other.

<FIG>, the bonding plane is schematically denoted by a dashed-and-dotted line. In the present embodiment, the interlayer insulating layer <NUM> comprises five insulating layers 4a, 4b, 4c, 4d, and 4e. The interlayer insulating layer <NUM> comprises two insulating layers 404a and 404b. The numbers of layers in the interlayer insulating layer <NUM> and the interlayer insulating layer <NUM> are not limited to those numbers.

In the example illustrated in <FIG>, the first chip 410a is provided with the reset transistor <NUM>, the feedback transistor <NUM>, and the first capacitive element <NUM>. The second chip 410b is provided with the signal detection transistor <NUM> and the address transistor <NUM>. The second capacitive element <NUM> may be provided in the interlayer insulating layer <NUM> or may be provided in the interlayer insulating layer <NUM>. The elements included in the signal detection circuit SC in the pixel <NUM> may be provided in any of the first chip 410a and the second chip 410b.

As shown in <FIG>, the insulating layer 4e, which is the uppermost layer (the layer at a lower side in the plane of the figure) in the interlayer insulating layer <NUM>, is provided with an electrically conductive terminal portion <NUM>. Similarly, the insulating layer 404b, which is the uppermost layer in the interlayer insulating layer <NUM>, is provided with an electrically conductive terminal portion <NUM>. Since the terminal portion <NUM> and the terminal portion <NUM> are connected in contact with each other, the elements provided at the semiconductor substrate <NUM> and the elements provided at the semiconductor substrate <NUM> can be electrically connected to each other.

In the present embodiment, the contact point <NUM> is provided at the bottom surface of the trench portion 41e in the first capacitive element <NUM>. The contact point <NUM> is connected to the reset transistor <NUM> through the via v1.

Also, the contact point <NUM> is provided at the bottom surface of the trench portion 41f in the first capacitive element <NUM>. Although not illustrated in <FIG>, the contact point <NUM> is electrically connected to the second capacitive element <NUM>. The second capacitive element <NUM> is provided, for example, in the first chip 410a. As described above, two or more electrical elements to which two or more electrical contact points of the first capacitive element <NUM> are connected are provided in the first chip 410a in which the first capacitive element <NUM> is provided.

The two or more electrical elements to which the two or more electrical contact points of the first capacitive element <NUM> are connected do not have to be provided in the first chip 410a. At least one electrical element or all electrical elements may be connected to the second chip 410b.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by the imaging device according to this modification. In the pixel <NUM> shown in <FIG>, the reset transistor <NUM> and the first capacitive element <NUM> are provided in the first chip 410a. The feedback transistor <NUM> is provided in the second chip 410b. The signal detection transistor <NUM>, the address transistor <NUM>, and the second capacitive element <NUM> may be provided in the first chip 410a or may be provided in the second chip 410b.

As shown in <FIG>, the pixel <NUM> comprises the first capacitive element <NUM>. The top electrode 341a of the first capacitive element <NUM> comprises the contact points <NUM> and 341i. The contact point <NUM> is electrically connected to the reset transistor <NUM>. That is, the reset transistor <NUM> is one example of an electrical element. The contact point 341i is electrically connected to the feedback transistor <NUM>. That is, the feedback transistor <NUM> is one example of an electrical element.

Two or more electrical elements to which two or more contact points of the first capacitive element <NUM> are connected may be respectively provided in the first chip 410a and the second chip 410b. That is, the first chip 410a and the second chip 410b may be stacked to thereby cause the contact points and the electrical elements to be electrically connected to each other.

Although the imaging devices according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to those embodiments. Modes obtained by making various modifications conceived by those skilled in the art to the embodiments and modes constructed by combining the constituent elements in different embodiments are also encompassed by the scope of the present disclosure, as long as such modes do not depart from the spirit of the present disclosure.

<FIG> is a schematic sectional view of each pixel <NUM> comprised by an imaging device according to another modification of the first embodiment. As shown in <FIG>, in the pixel <NUM>, the top electrode 41a of the first capacitive element <NUM> is electrically connected to the sensitivity adjustment line <NUM> through a via. The sensitivity adjustment line <NUM> extends from inside of the pixel region to outside of the pixel region. In a region outside the pixel region, the sensitivity adjustment line <NUM> is electrically connected to a pad <NUM> through a via. Accordingly, the top electrode 41a is electrically connected to the pad <NUM> through the sensitivity adjustment line <NUM>.

For example, in the embodiments described above, the numbers of insulating layers and wiring layers included in the interlayer insulating layer in the imaging device are not particularly limited. Also, the position of the capacitive element in the interlayer insulating layer is not particularly limited.

Also, for example, the number of trench portions included in the first capacitive element may be only one. No electrical contact point may be provided in any of the trench portion included in the first capacitive element. In this case, two or more electrical contact points may be provided at the top electrode at the planar portion of the first capacitive element or may be provided at the bottom electrode at the planar portion. The electrical contact points may be provided at any of the upper surface and the lower surface of the top electrode or the bottom electrode.

Also, for example, the dielectric layer 41b may be an insulating film, such as a silicon oxide film or a silicon nitride film, not a thin film using a high-k material.

Also, for example, each transistor included in the signal detection circuit SC in the imaging device may be a P-channel MOSFET. Also, each transistor may be a bipolar transistor, not an FET.

Also, various changes, replacements, additions, omissions, and so on within the scope recited in the claims and a scope equivalent thereto can be made to each embodiment described above.

Claim 1:
An imaging device comprising:
a semiconductor substrate (<NUM>) and pixels (<NUM>), wherein
each of the pixels (<NUM>) includes
a first capacitive element (<NUM>),
a photoelectric converting portion (<NUM>) that converts light into charge,
an impurity region (2a) electrically connected to the photoelectric converting portion (<NUM>) and provided in the semiconductor substrate (<NUM>),
a transistor (<NUM>) electrically connected to the impurity region (2a), and
a third electrode (42a),
the first capacitive element (<NUM>) includes
a first electrode (41c) provided above the semiconductor substrate (<NUM>),
a second electrode (41a) provided above the semiconductor substrate (<NUM>), and
a dielectric layer (41b) located between the first electrode (41c) and the second electrode (41a),
at least one of the first electrode (41c) and the second electrode (41a) has a first electrical contact point (<NUM>) electrically connected to the transistor (<NUM>) and a second electrical contact point (<NUM>) electrically connected to the third electrode (42a),
the first capacitive element (<NUM>) includes a first trench portion (41e) and a second trench portion (41f) each having a trench shape,
the impurity region (2a) is configured to accumulate the charge,
the first electrical contact point (<NUM>) is provided at the first trench portion (41e), and
the second electrical contact point (<NUM>) is provided at the second trench portion (41f).