Patent Description:
Electronic circuits comprise terminals to communicate with other entities, for example to receive supply voltages, to receive input signals or to output output signals. In case the circuit is provided in a package, such terminals may be provided as pins of the package.

Such terminals like pins are usually protected against electrostatic discharge (ESD) by ESD protection circuits, which may be realized by diodes coupled between the respective terminals and a reference potential. In normal operation, the diodes are non-conducting. In case of an electrostatic discharge leading to a high voltage, the diodes become conducting, thus sinking the charge generated by the electrostatic discharge to the reference potential.

One kind of terminals are configuration terminals which are used to configure the circuit. For example, using such configuration terminals, operation modes for the circuit may be selected, or an address may be provided for the circuit in case a plurality of circuits is connected to a common communication environment like a bus.

To give a more specific example, for radio frequency (RF) circuits like power amplifiers, low noise amplifiers and radio frequency switches, such configuration terminals may be used to set or configure a current mode or one or more low power modes, or provide a logic address like an USID (unique slave identification) in an MIPI radio frequency frontend (RFFE). However, in some cases in normal operation the configuration terminals and associated ESD circuits may disturb the normal operation. For example, in radio interface circuit, if a pad associated with the configuration terminal is close to high amplitude radio frequency pin with high overlap capacitance to the configuration terminal the ESD circuit and readout logic associated with the configuration terminal may cause a spurious radiation of non-linear signals. This is at least in part caused by a rectification of radio frequency signals at diodes of the ESD circuit and may result in harmonics of higher order. This in turn may cause violations of radio frequency specification, and the rectified radio frequency signal also causes an increase in current consumption.

Various approaches have been made to overcome this problem which may have various drawbacks.

<CIT> discloses a circuit according to the preamble of claim <NUM>.

Further approaches where circuit elements are decoupled are disclosed in <CIT>, <CIT> or <CIT>.

A circuit as defined in claim <NUM> and a method as defined in claim <NUM> are provided. The dependent claims define further embodiments.

According to an embodiment, a circuit is provided, comprising:.

According to another embodiment, a method is provided, comprising:.

The above summary is merely intended to give a brief overview over some embodiments and is not to be construed as limiting in any way.

In the following, various embodiments will be described in detail referring to the attached drawings. These embodiments are to be taken as illustrative examples only and are not to be construed as limiting. For example, while embodiments may be described as comprising numerous features, in other embodiments, some of these features may be omitted or may be replaced by alternative features. In addition to the features explicitly shown in the drawings or described herein, additional features, for example features provided in conventional circuits, may be provided.

For instance, embodiments described in the following relate to the coupling and decoupling of a configuration terminal to and from other parts of a circuit, like an internal node. Apart from the coupling and decoupling described and circuitry associated therewith, in some embodiments the circuit may be implemented in a conventional manner, and may include additional terminals, additional circuit parts etc. used for providing various functions.

Variations and modifications described with respect to one of the embodiments may also be applied to other embodiments and will therefore not be described repeatedly. Features from different embodiments may be combined to form further embodiments.

Configuration, as used herein, refers to a process where a circuit is configured prior to normal operation or also in configuration phases between phases of normal operation to adjust certain functionalities. For example, values may be written to configuration registers, which then are used in normal operation. As mentioned previously, such a configuration may be used to set certain modes for the normal operation like a current mode or a low power mode or to set an address for communication via a bus. These are merely some examples, and any kind of configuration may be used. Normal operation, in contrast thereto, refers to any operation where the circuit provides the functionality it is designed for, for example functionality as a power amplifier, low noise amplifier, radio frequency switch etc..

A terminal, as used herein, is a point of contact where the circuit interfaces with the outside world, for example with other circuits. In case of integrated circuits provided in packages, such terminals may be realized as pins. Such terminals are often associated with electrostatic discharge (ESD) protection circuitry to prevent or mitigate damage to the circuit in case of an electrostatic discharge, which may for example be caused by a human being touching the circuit.

Some embodiments use switches. Switches may be implemented using one or more transistors like field effect transistors, insulated gate bipolar transistors or bipolar junction transistors. A switch is referred to as open or off when it is essentially non-conducting (apart from possible leakage currents, which may occur depending on switch implementation), and is referred to as closed or on if it provides a low ohmic electrical connection.

<FIG> illustrates a circuit <NUM> which is not a claimed embodiment taken alone in a configuration phase, and <FIG> illustrates normal operation of circuit <NUM>.

As shown in <FIG>, circuit <NUM> may be provided in a package like a chip housing indicated by a dashed line <NUM>. A configuration terminal <NUM> enables a configuration of circuit <NUM> during a configuration phase. Configuration terminal <NUM> may be a configuration pin. Configuration terminal <NUM> is coupled to an internal node <NUM> via a switch <NUM>. In the configuration phase of <FIG>, switch <NUM> is closed. Furthermore, internal node <NUM> is coupled to a reference potential via a switch <NUM>. In the example of <FIG>, the reference potential is ground (GND). In the configuration phase illustrated in <FIG>, switch <NUM> is open, such that internal node <NUM> is decoupled from the reference potential.

In other embodiments, switch <NUM> and the coupling of internal node <NUM> to ground may be omitted.

Internal node <NUM> is coupled to ESD protection circuitry <NUM> and to readout circuitry/further internal circuitry <NUM> of circuit <NUM>. ESD protection circuitry <NUM> may be implemented in any conventional manner, for example using diodes coupling internal node <NUM> to reference potential like ground and/or a positive reference potential, and protect circuitry <NUM> against electrostatic discharge on configuration terminal <NUM> by deviating the electrostatic discharge to the reference potential(s). Circuitry <NUM> reads out signals at configuration terminal <NUM> and configures internal circuitry of circuit <NUM> accordingly. This configuration may be done in any conventional manner and may be a configuration as discussed above.

In some embodiments, furthermore control circuitry <NUM> may be provided as part of circuit <NUM> to control switching of switches <NUM>, <NUM>, or in other words, to switch the circuit <NUM> between the configuration phase shown in <FIG> and the normal operation discussed further below with reference to <FIG>. In other embodiments, switches <NUM>, <NUM> may be controlled by applying control signals to additional terminals, for example additional pins (not shown in <FIG>).

Reference numeral <NUM> indicates a further terminal of circuit <NUM>, which may be a radio frequency (RF) terminal where RF signals with high signal swing may be applied. Radio frequency, in this respect, may refer to frequencies above <NUM>, for example <NUM> or more or in the gigahertz range. High signal swing may for example mean a signal swing of up to 14V for a 50Ω loaded GSM (Global System for Mobile Communications) signal and up to 100V for antenna tuning applications. These values are merely examples, and in other application other values may apply.

The configuration phase of <FIG> may for example be applied at startup of circuit <NUM> to configure circuit <NUM> at startup.

<FIG> illustrates circuit <NUM> in a normal operation, for example after startup. In <FIG>, only the parts of <FIG> are represented where a change occurs between configuration phase and normal operation. In normal operation, switch <NUM> is open, and switch <NUM> is closed. Therefore, configuration terminal <NUM> is decoupled from circuit <NUM> (by opening switch <NUM>), and internal node <NUM> and therefore switch <NUM> is coupled to the reference potential, for example ground, by closing switch <NUM>.

In some embodiments, the decoupling by switch <NUM> reduces disturbances which may for example be caused by radio frequency signals being applied to terminals adjacent to terminal <NUM> like terminal <NUM> and may help to fulfil radio frequency specifications and may reduce current consumption. Further, by closing switch <NUM>, remaining voltages which may be caused by and stored in parasitic capacitances of switch <NUM> may be shorted to ground. In the embodiment shown in <FIG> switch <NUM> is coupled between internal node <NUM> and ground for discharging the remaining voltages. In other embodiments switch <NUM> may be coupled between terminal <NUM> and ground. In some implementations, the coupling as shown between internal node <NUM> and ground may reduce current flow compared to an implementation where switch <NUM> is coupled between terminal <NUM> and ground if a voltage is applied to terminal <NUM> while switch <NUM> is open and switch <NUM> is closed.

<FIG> is a circuit diagram illustrating an embodiment. In order to avoid repetitions, when describing the embodiment of <FIG> reference will be made to the previous description of the embodiment of <FIG>.

The circuit of <FIG> comprises a configuration terminal <NUM> which is coupled to an internal node <NUM> via a transmission gate formed by a PMOS transistor <NUM> and an NMOS transistor <NUM>. Configuration terminal <NUM> may be a configuration pin of a packaged circuit, as explained with reference to <FIG>. Internal node <NUM> may be coupled to ESD protection circuitry and readout circuity and internal configuration circuits as described for internal node <NUM> of <FIG>.

PMOS transistor <NUM> is controlled by a signal PFC, and NMOS transistor <NUM> is controlled by a signal NFC. In a configuration phase, transistors <NUM>, <NUM> are turned on, such that configuration terminal <NUM> is electrically coupled to internal node <NUM>. Therefore, the transmission gate formed by transistors <NUM>, <NUM> is an example implementation for switch <NUM> of <FIG> and serves a similar function.

Furthermore, internal node <NUM> is coupled to a reference potential SS_ANA (analog ground) via an NMOS transistor <NUM>. NMOS transistor <NUM> is controlled by a signal NFPDC. In configuration phase, NMOS transistor <NUM> is turned off.

NMOS transistor <NUM> is an example implementation of switch <NUM> of <FIG>.

Signals PFC, NFC and NFPDC may be generated by an internal control circuitry like control circuitry <NUM> of <FIG>, or may be supplied externally via corresponding terminals. In some embodiments, signals PFC and NFC may be generated based on a common control signal, as PMOS transistor <NUM> and NMOS transistor <NUM> are switched on and off simultaneously.

In normal operation, as has been explained with reference to <FIG>, transistors <NUM>, <NUM> are then turned off, and NMOS transistor <NUM> is turned on. By turning NMOS transistor <NUM> on, any remaining voltage caused by parasitic capacitances of transistors <NUM>, <NUM> at internal node <NUM> is shorted to the reference potential.

In some embodiments, such parasitic capacitances of transistors <NUM>, <NUM> may be comparatively high, as for protection against electrostatic discharge (ESD). Transistors <NUM>, <NUM> may have a comparatively high gate width and may use Salicide Blocking (SABL). The salicide process is a conventional process to reduce gate resistances in MOS transistors. In ESD devices this process is blocked to get a higher "pre"-resistance so that the voltage spreading gets more homogenous and avoid hot spots. Such a design allows self-conduction of transistors <NUM>, <NUM> during an ESD pulse. This self-conduction limits the voltage at configuration terminal <NUM> and therefore the drain gate voltages of transistors <NUM>, <NUM>. Example gate widths may be of the order of <NUM> for NMOS transistor <NUM> and about <NUM> for PMOS transistor <NUM>. It should be noted that the transistor implementations of <FIG> serve merely as an example, and other switches may also be used.

Additionally, in the circuit of <FIG>, a capacitor <NUM> couples the configuration terminal <NUM> to the reference potential SS_ANA. In some embodiments, this may help to suppress radio frequency signals of very high frequency. Very high frequency may refer to frequencies in the GHz range, for example above ~<NUM>, where the shunt transistor <NUM> is limited by the inductance of the SS_ANA line. Using high external capacitors instead may lead to self-resonances, whereas small internal capacitors like capacitor <NUM> inside the chip may be more effective for avoiding self-resonances. Furthermore, in case of a triple well implementation of the transistors shown, additional RC filters comprising capacitors <NUM> and a resistor <NUM> for the PMOS transistors and a capacitor <NUM> and resistor <NUM> for the NMOS transistor for the respective wells (well _VP and well_VN in <FIG>) may be provided. In this respect, VSSN is the negative bias voltage for the RF switch transistors <NUM>, <NUM>, well-VP is the RC filtered positive supply voltage and well-NP the RC filtered VSSN. Numerals <NUM>, <NUM> and <NUM> denote diodes, and an additional terminal, e.g. RF terminal, via an element <NUM> is shown in <FIG>.

<FIG> is a flowchart illustrating a method according to an embodiment. The method of <FIG> may be implemented using the circuit of <FIG> or the circuit of <FIG>, and will be described referring thereto, but may also be implemented in other circuits.

At <NUM>, the method comprises coupling a configuration terminal to an internal node during a configuration phase, for example startup. For example, this coupling is effected in <FIG> by closing switch <NUM> and in <FIG> by turning on transistors <NUM>, <NUM> of the transmission gate.

Claim 1:
A circuit (<NUM>), comprising:
a configuration terminal (<NUM>; <NUM>) configured to receive configuration signals in a configuration phase of the circuit (<NUM>),
an internal node (<NUM>; <NUM>) coupled to internal circuitry (<NUM>) of the circuit (<NUM>) and
a switch (<NUM>; <NUM>, <NUM>) coupled between the configuration terminal (<NUM>; <NUM>) and the internal node (<NUM>; <NUM>), wherein the switch (<NUM>; <NUM>, <NUM>) is configured to couple the configuration terminal (<NUM>) with the internal node (<NUM>) during the configuration phase and to decouple the configuration terminal (<NUM>) from the internal node (<NUM>) during normal operation of the circuit (<NUM>),
characterized in that the circuit further comprises a capacitor (<NUM>) directly coupled between the configuration terminal (<NUM>; <NUM>) and a reference potential,
and characterized in that the circuit (<NUM>) further comprises a further switch (<NUM>; <NUM>) directly coupled between the internal node (<NUM>; <NUM>) and a reference potential (GND),
wherein the further switch (<NUM>; <NUM>) is configured to couple the internal node (<NUM>; <NUM>) to the reference potential (GND) during the normal mode of operation and to decouple the internal node (<NUM>) from the reference potential (GND) in the configuration phase.