Patent Description:
Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for the development of reduced size system in package components.

<CIT> discloses a system comprising a bridge chip for proximity communication.

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to an interconnect hub, which may also be referred to as a vertical interconnect hub, to provide connectivity to a plurality of tiled dies. In embodiments, the interconnect hub provides a high density die-to-die interconnect path for tiled die complexes.

In embodiments, the interconnect hub for tiled dies, which may be top mounted on the dies, provides a centralized interconnect implementation for adjacent and diagonal die-to-die, which may also be referred to as chip-to-chip, routing. This in turn provides more flexible and direct communication channels between dies that are in proximity to each other. Embodiments may reduce the number of die-to-die interconnects required for a tiled die complex. For example, legacy embedded bridge tiling implementations may utilize a bridge die (e.g. EMIB) for each die-to-die communication channel with no routing channels for direct communication between diagonally positioned surface mount dies. Other legacy implementations may use a silicon interposer that consists of a large silicon die base positioned under the full die tiling complex. Silicon interposer based solutions require the base die to be larger than the tiled die complex.

Legacy implementations, for example EMIB die-to-die conductivity, is limited to short, direct connections between two adjacent die on a shared embedded bridge. The limitations of legacy die-to-die communication within dies of the tiled die complex create IO overhead and latency when two nonadjacent dies need to communicate. Legacy silicon interposer-based die-to-die interconnects allows more flexibility for die-to-die connectivity than EMIB, but require a large interposer size that encompasses the entire tiled die complex. The large interposer size is limited by the maximum reticle size of that fabrication process (~<NUM>-<NUM><NUM>). Reticle stitching can be used to increase the effective maximum interposer size but this has limitations on connectivity across the stitch line and increases fabrication cost. Large interposers can be cost prohibitive due to poor wafer utilization and the larger area increasing the likelihood of defects. Another consideration is that very large silicon based die complexes are prone to higher warpage which can lead to a decrease in assembly yield.

Embodiments of techniques described herein may be useful for homogeneous die complexes with cell-like repeating tiles that through high bandwidth hub based interconnects can be networked together to act like one monolithic active die. In particular, this benefits products utilizing the leading edge process nodes where die yield on larger die sizes are a significant concern due to the immature die process technology. For example, graphics and/or artificial intelligence (AI) chip die complexes would benefit from scalable tile based die complexes where the key metric is die area based as opposed to package input/output (IO) counts.

Embodiments described herein may also address fabrication challenges with next generation silicon fabrication processes, including die complexes which use smaller active die tiles. First, having a single die-to-die port within the vertical hub solution could reduce die IO circuit area, power requirements and clocking overhead, by utilizing a single localized controller on each die as opposed to having multiple instances of the same chip to chip PHY. Embodiments may achieve direct die-to-die communication between the diagonal dies and thus reduces communication latency between the dies.

Second, when compared to EMIB, embodiments offer better pitch scaling due to the direct die-to-die interconnect and improved power delivery with current flow unencumbered by embedded bridge. Embodiments described herein may significantly reduce the number of interconnect structures between dies, which can increase die yields and reduce overall chip cost.

Third, embodiments may avoid high speed IO from the tiled dies having to pass through a passive interposer and/or through silicon vias (TSVs). This direct active die to package first level interconnect avoids the TSV pad capacitance and resistance impacts to signal loss and enables a more direct power delivery path to the tiled die.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced.

The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.

As used herein, the term "module" may refer to, be part of, or include an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

Various figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.

<FIG> illustrate an example of legacy implementations for providing high-speed connections between a plurality of dies, in accordance with embodiments. <FIG> shows package 100a of an example legacy implementation of four dies <NUM>, <NUM>, <NUM>, <NUM> in a tiled formation that are coupled for high-speed data transfer using EMIBs <NUM>, <NUM>, <NUM>, <NUM>. A single EMIB <NUM> couples die <NUM><NUM> and die <NUM><NUM>, but cannot be used to directly couple with any other die such as die <NUM><NUM> or die <NUM><NUM> respectively. A second EMIB <NUM> may be used to couple die <NUM><NUM> with die <NUM><NUM>. However, in this implementation, die <NUM><NUM> has no direct communication path with die <NUM><NUM>.

An EMIB <NUM>, <NUM>, <NUM>, <NUM> may include a substrate with a small silicon based interconnect embedded into the organic substrate to connect a host chip (e.g. die <NUM><NUM>) and a secondary chiplet (e.g. die <NUM><NUM>) with a high bandwidth data path along the shared die edge.

<FIG> includes package 100b that shows an example legacy implementation using an interposer <NUM> used to couple the dies <NUM>, <NUM>, <NUM>, <NUM>. The interposer <NUM> may be a silicon interposer that serves as a large silicon die in place for routing purposes between the dies. In embodiments, the dies <NUM>, <NUM>, <NUM>, <NUM> may be attached to one side of the interposer <NUM> and provide conductivity paths <NUM>, <NUM>, <NUM>, <NUM> between the dies. The interposer <NUM> provides another high density architecture that uses a large passive silicon die positioned under the full die complex.

As shown, the conductivity paths <NUM>, <NUM>, <NUM>, <NUM> do not provide a direct communication path between all of the dies. For example, die <NUM><NUM> does not have a direct communication path with die <NUM><NUM>. As discussed above, using a legacy implementation of a silicon interposer <NUM> increase costs, and faced fabrication size limitation and assembly yield risks that come with larger base dies.

<FIG> illustrates an example of a top-down view of a package assembly using an interconnect hub to interconnect a plurality of dies, in accordance with embodiments of the invention. <FIG> shows package <NUM> that includes four dies <NUM>, <NUM>, <NUM>, <NUM> that are connected by a interconnect hub <NUM>. The interconnect hub <NUM> overlaps a corner of each of the dies <NUM>, <NUM>, <NUM>, <NUM> and physically and/or electrically couples with electronics of at least a subset of each of the dies.

This interconnect hub <NUM> may include a passive or an active silicon bridge that intersects a corner, respectively, of the four tiled surface mount dies <NUM>, <NUM>, <NUM>, <NUM>.

The die-to-die communication flow <NUM> shows possible communication paths that may be facilitated by the interconnect hub <NUM>. In embodiments, each of the individual flows may be implemented by high-bandwidth, high-speed data connection that may exist in one or more layers within the interconnect hub <NUM>. For example, using the interconnect hub <NUM> die <NUM><NUM> may communicate directly with die <NUM><NUM>, die <NUM><NUM>, and/or die <NUM><NUM>.

In embodiments, each of the dies <NUM>, <NUM>, <NUM>, <NUM> may be different types of dies, including dies from different manufacturers, that are communicatively coupled by the interconnect hub <NUM>. In embodiments, the dies may be a same die that may have communications circuitry designed in a particular corner area of the die. When the dies <NUM>, <NUM>, <NUM>, <NUM> are tiled, they may be positioned in a clockwise layout, where each die is rotated <NUM>° such that the particular corner area having the communications circuitry is proximate to the other dies and may be electrically coupled with interconnect hub <NUM>.

<FIG> illustrates examples of attaching an interconnect hub to a plurality of dies, in accordance with embodiments. Attachment embodiments may be configured in a different connectivity solutions. <FIG> show an example of configurations that position the interconnect hub mounted on top of the tiled dies. This allows for a direct tiled die to package connection for more direct power delivery and high speed IO routing. There are two variants with this architecture depending the performance requirements for die-to-die interconnections and signaling requirement for the tiling die going through a package substrate.

<FIG> shows tiled dies 302a and 304a, which may be similar to dies <NUM> and <NUM> of <FIG>, that have their respective active circuitry 302a1, 304a1 facing upwards toward the interconnect hub 318a. When the dies 302a, 304a are connected to the interconnect hub 318a, data will transfer in the various paths 319a from the active circuitry 302a1 of the first die 302a through the interconnect hub 318a and to the active circuitry 304a1 of the second die 304a, and vice versa. The respective active circuitries of the dies 302a1, 304a1 may be coupled with respective ball grid arrays 302a2, 304a2, using through TSVs 302a3, 304a3 to provide an electrical connection with a substrate (not shown).

The embodiment implementation shown in <FIG> avoids inserting TSVs between respective active circuitry 302a1, 304a1 communication. These embodiments have die-to-die bandwidth and latency advantages. The IO and power supplies that route out through the package must transition through TSVs 302a3, 304a3 which can potentially have higher power delivery loop inductance, increase high speed signaling loss and generate higher cross talk for signals going through the package.

<FIG> shows tiled dies 302b and 304b, which may be similar to dies <NUM> and <NUM> of <FIG>, that have their respective active circuitry 302b1, 304b1 facing downward away from the interconnect hub 318b. When the dies 302b, 304b are connected to the interconnect hub 318b, data will transfer in the various paths 319b from the active circuitry 302b1, 304b1 of the dies 302b, 304b through the interconnect hub 318b using vias 302b3, 304b3. The respective active circuitries of the dies 302b1, 304b1 may be coupled with respective ball grid arrays 302b2, 304b2 to provide an electrical connection with a substrate (not shown).

The embodiment of <FIG> only utilizes TSVs for the die-to-die interconnect, so all other IO and power delivery on the active circuitry 302b1, 304b1 can avoid TSVs. For improved mechanical reliability and better heat dissipation, "dummy" dies <NUM> can be added on top of the active tile dies 302b, 304b to make a uniform top for the die complex. These "dummy" dies <NUM> create a direct silicon based path for heat dissipation from the base tile to thermal solution above. Mechanically, the die complex would benefit from having a more uniform rectangular cross-section with smaller stress singularities. The "dummy" die <NUM> can be passive silicon with no metal features or passive silicon with simple passive metal features such as capacitors and/or inductors with a direct die to die interconnect to the base tile. The dummy tile can also be active silicon with additional logic circuity or memory such as SRAM.

<FIG> shows a side view of an interconnect hub 318c, which is similar to interconnect hub <NUM> of <FIG>. The interconnect hub 318c is in position between the tiled dies 302c, 304c and the substrate (not shown). Copper pillars <NUM> may connect the respective dies 302c, 304c to a ball grid array <NUM> that made the physically coupled to the substrate (not shown). In this configuration, die-to-die connectivity 319c may be achieved without requiring TSVs in the interconnect hub 318c or the dies 302c, 304c. In addition, this configuration provides a uniform top die plane from the dies 302c, 304c to a thermal solution without the need for "dummy" die <NUM>. The interconnect hub 318c standoff may create a vertical gap between the tiled die bumps and the package first level interconnect which can be closed by using copper pillars <NUM> or by using another high density, for example <NUM>-<NUM> pitch, vertical conductivity implementation.

<FIG> illustrates an example of a legacy implementation for interconnecting a <NUM> x <NUM> die tile using EMIB structures. As shown, dies <NUM>, which may be similar to die <NUM> of <FIG>, are tiled in a <NUM> x <NUM> pattern and are interconnected in a legacy implementation by <NUM> EMIBs <NUM> dies. As shown in and as discussed with respect to <FIG>, an EMIB <NUM> may only directly connect a die <NUM> with another die that is immediately above, below, left, or right of the die <NUM>. Thus, a larger number of EMIB <NUM> structures are needed to achieve less die <NUM> interconnectivity as compared to embodiments described herein.

<FIG> illustrates an example of a four vertical interconnect hub architecture for interconnecting a <NUM> x <NUM> die tile, in accordance with embodiments of the invention. Dies <NUM>, which may be similar to die <NUM> of <FIG>, are tiled in a <NUM> x <NUM> pattern and are interconnected using interconnect hubs <NUM>, which may be similar to interconnect hub <NUM> of <FIG>. As shown, only four interconnect hubs <NUM> are used, and yet this technique provides greater interconnect coverage than the <NUM> EMIB dies <NUM> shown for a similar die tiling pattern in <FIG>.

The tiling and interconnect hub architecture shown in <FIG> may be extended hierarchically for larger tile complexes while reducing inter-die area overhead, using fewer connections, and increasing bandwidth between connected dies <NUM>. For example, <FIG> illustrates an example of a five interconnect hub architecture for interconnecting a <NUM> x <NUM> die tile, in accordance with embodiments. The tiled dies <NUM> may be coupled using five interconnect hubs <NUM>, which may be similar to interconnect hubs <NUM> of <FIG>.

<FIG> illustrates an example of a vertical interconnect hub for interconnecting a <NUM> x <NUM> die tile, in accordance with embodiments. Dies <NUM>, which may be similar to die <NUM> of <FIG>, are tiled in a <NUM> x <NUM> pattern. Instead of using five smaller hub bridges <NUM> as shown in <FIG>, where die to die conductivity is limited to four tiles per hub, <FIG> shows an architecture of one large hub <NUM> that intersects and interconnects all of the base tiled dies <NUM>.

<FIG> illustrates an example of a process for using a vertical interconnect hub to interconnect three or more dies in a tiled formation, in accordance with embodiments. In embodiments, the process elements described in association with <FIG>, <FIG>, and <FIG>.

At block <NUM>, the process includes positioning three or more dies in a tiled formation within a plane. The three or more dies correspond to tiled dies <NUM>, <NUM>, <NUM>, <NUM> of <FIG>, dies 302a, 304a, 302b, 304b, 302c, 304c of <FIG>, tiled dies <NUM> of <FIG>, tiled dies <NUM> of <FIG>, and tiled dies <NUM> of <FIG>.

At block <NUM>, the process includes electrically coupling a side of an interconnect hub to a side of the three or more dies, wherein the plane of the interconnect hub is substantially parallel to the plane of the dies in the tiled formation to facilitate high-speed data transfer between the dies. The interconnect hub corresponds to interconnect hub <NUM> of <FIG>, interconnect hub 318a, 318b, 318c of <FIG>, interconnect hubs <NUM> of <FIG>, and interconnect hubs <NUM> of <FIG>.

<FIG> schematically illustrates a computing device, in accordance with embodiments. The computer system <NUM> (also referred to as the electronic system <NUM>) as depicted can embody an interconnect hub for dies, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system <NUM> may be a mobile device such as a netbook computer. The computer system <NUM> may be a mobile device such as a wireless smart phone. The computer system <NUM> may be a desktop computer. The computer system <NUM> may be a hand-held reader. The computer system <NUM> may be a server system. The computer system <NUM> may be a supercomputer or high-performance computing system.

In an embodiment, the electronic system <NUM> is a computer system that includes a system bus <NUM> to electrically couple the various components of the electronic system <NUM>. The system bus <NUM> is a single bus or any combination of busses according to various embodiments. The electronic system <NUM> includes a voltage source <NUM> that provides power to the integrated circuit <NUM>. In some embodiments, the voltage source <NUM> supplies current to the integrated circuit <NUM> through the system bus <NUM>.

The integrated circuit <NUM> is electrically coupled to the system bus <NUM> and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit <NUM> includes a processor <NUM> that can be of any type. As used herein, the processor <NUM> may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor <NUM> includes, or is coupled with, an interconnect hub for dies, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit <NUM> are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit <NUM> for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit <NUM> includes on-die memory <NUM> such as static random-access memory (SRAM). In an embodiment, the integrated circuit <NUM> includes embedded on-die memory <NUM> such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the integrated circuit <NUM> is complemented with a subsequent integrated circuit <NUM>. Useful embodiments include a dual processor <NUM> and a dual communications circuit <NUM> and dual on-die memory <NUM> such as SRAM. In an embodiment, the dual integrated circuit <NUM> includes embedded on-die memory <NUM> such as eDRAM.

In an embodiment, the electronic system <NUM> also includes an external memory <NUM> that in turn may include one or more memory elements suitable to the particular application, such as a main memory <NUM> in the form of RAM, one or more hard drives <NUM>, and/or one or more drives that handle removable media <NUM>, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory <NUM> may also be embedded memory <NUM> such as the first die in a die stack, according to an embodiment.

In an embodiment, the electronic system <NUM> also includes a display device <NUM>, an audio output <NUM>. In an embodiment, the electronic system <NUM> includes an input device such as a controller <NUM> that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system <NUM>. In an embodiment, an input device <NUM> is a camera. In an embodiment, an input device <NUM> is a digital sound recorder. In an embodiment, an input device <NUM> is a camera and a digital sound recorder.

Claim 1:
A system comprising:
a substrate;
three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>); and
an interconnect hub (318c; <NUM>; <NUM>; <NUM>) physically coupled to the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>), the interconnect hub (318c; <NUM>; <NUM>; <NUM>) comprising:
a first side;
a second side opposite the first side to couple with the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>), and wherein the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>) to another of the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>);
wherein the electrical couplings are to facilitate data transfer between at least a subset of the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>);
wherein a corner of the second side of the interconnect hub (318c; <NUM>; <NUM>; <NUM>) is to physically couple with a corner of the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>);
wherein the three or more dies (<NUM>, <NUM>, <NUM>, <NUM>; 302c, 304c; <NUM>; <NUM>; <NUM>) are tiled dies; and
characterized in that
the interconnect hub (318c; <NUM>; <NUM>; <NUM>) is positioned between the tiled dies and the substrate.