Patent Description:
Integrated circuit technology has achieved great strides in advancing computing power through miniaturization components such as semiconductor transistors. The progression of semiconductors have progressed from bulk substrates and planar CMOS, FinFETs, nanowires or nanoribbons, FinFET 3D stacking to nanowire or nanoribbon 3D stacking. The semiconductor technologies have largely been based on silicon. However, fabrication of transistors based on silicon may be problematic when it comes to further reduction in scaling, e.g., to few nanometers.

Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional devices including the methods, system and apparatus provided herein. Attention is drawn to document <CIT> which relates to CFET devices having a gate-all-around structure. Attention is also drawn to document <CIT> which relates to a transistor including a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Further embodiments of the invention are defined by the appended dependent claims. The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.

An exemplary complementary field effect transistor (CFET) structure is disclosed. The CFET structure may comprise a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer. The CFET structure may also comprise a lower gate-all-around (GAA) gate region in the IMD layer between the lower source and drain contacts. The lower GAA gate region may be a first conductivity type and may comprise one or more lower channel structures. Each lower channel structure may comprise a lower transition metal dichalcogenide (TMD) channel electrically coupled with the lower source contact and with the lower drain contact. Each lower channel structure may also comprise first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel. The CFET structure may further comprise an upper source contact and an upper drain contact in the IMD layer above the lower source and drain contacts. The CFET structure may yet comprise an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source and drain contacts. The upper GAA gate region may be a second conductivity type opposite the first conductivity type and may comprise one or more upper channel structures. Each upper channel structure may comprise an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact. Each upper channel structure may also comprise first and second upper gate oxide layers respectively on upper and lower surfaces of the upper TMD channel. The CFET structure may yet further comprise a common gate in the IMD layer between the lower source and drain contacts and between the upper source and drain contacts. The common gate may be configured to apply a common voltage to the lower and upper channel structures.

A method of fabricating a complementary field effect transistor (CFET) structure is disclosed. The method may comprise forming a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer. The method may also comprise forming a lower gate-all-around (GAA) gate region in the IMD layer between the lower source and drain contacts. The lower GAA gate region may be a first conductivity type and may comprise one or more lower channel structures. Each lower channel structure may comprise a lower transition metal dichalcogenide (TMD) channel electrically coupled with the lower source contact and with the lower drain contact. Each lower channel structure may also comprise first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel. The method may further comprise forming an upper source contact and an upper drain contact in the IMD layer above the lower source and drain contacts. The method may yet comprise forming an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source and drain contacts. The upper GAA gate region may be a second conductivity type opposite the first conductivity type and may comprise one or more upper channel structures. Each upper channel structure may comprise an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact. Each upper channel structure may also comprise first and second upper gate oxide layers respectively on upper and lower surfaces of the upper TMD channel. The method may yet further comprise forming a common gate in the IMD layer between the lower source and drain contacts and between the upper source and drain contacts. The common gate may be configured to apply a common voltage to the lower and upper channel structures.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternate aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the illustrative embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

In certain described example implementations, instances are identified where various component structures and portions of operations can be taken from known, conventional techniques, and then arranged in accordance with one or more exemplary embodiments. In such instances, internal details of the known, conventional component structures and/or portions of operations may be omitted to help avoid potential obfuscation of the concepts illustrated in the illustrative embodiments disclosed herein.

As indicated above, transistor scaling beyond FinFET and nanowires - e.g., down to single digit nanometers - is a challenge. In this regard, it is proposed to fabricate transistors using two dimensional (2D) materials for transistor fabrication. The 2D-materials may also be referred to as transition metal dichalcogenide (TMD) having a MX<NUM> as a generic molecular formula. Here, 'M' designates a transition metal (e.g., titanium (Ti), molybdenum(Mo), tungsten (W), etc.) and 'X' designates a chalgogen (e.g., sulfue (S), selenium (Se), tellurium (Te), etc.). Thus, examples of TMDs include molybdenum disulfide (MoS<NUM>), tungsten disulfide (WS<NUM>) and tungsten diselenide (WSe<NUM>). Note that there can be well over <NUM> different combinations of MX<NUM> TMDs.

In one or more aspects, it is proposed to stack the 2D TMDs to arrive at a 3D transistor configuration. Relative to transistors with silicon (Si) based channels between source and drain, technical advantages of 2D stacked TMDs as transistors include better drive current and lower switching capacitance. In short, 2D enables scaling resulting in better performance and lower energy.

<FIG> illustrates an example of a complementary field effect transistor (CFET) structure <NUM> using gate-all-around (GAA) TMD channels. In this instance, the CFET structure <NUM> is configured as an inverter (NOT logic). But as will be seen further below, the CFET structures may be configured for other purposes. It is envisioned that the proposed 3D GAA TMDs channel CFET integration may be a roadmap for future technology shrink below one <NUM>.

In <FIG>, the proposed CFET structure <NUM> may be formed in multiple intermetal dielectric (IMD) layers. Here, <NUM> represents the main IMD layer - layer (x), <NUM> represents an IMD (x-<NUM>), and <NUM> represents IMD layer (x+<NUM>). For ease of description, the main IMD layer <NUM> may simply be referred to as "IMD layer". As seen, the IMD layers <NUM> and <NUM> may respectively be below and above the IMD layer <NUM>. Hence, also for ease of description, layer <NUM> may be referred to as the "lower IMD layer" and layer <NUM> may be referred to as the "upper IMD layer". It should be noted that there may be other IMD layers below the lower IMD layer <NUM> and/or above the upper IMD layer <NUM>.

Before proceeding further, the following should also be recognized. Terms such as "above", "below", "left", "right", and so on are terms used for convenience of description. Thus, unless explicitly indicated otherwise, such terms are not meant to limit aspects to a specific direction or orientation.

Within the IMD layer <NUM>, a lower and an upper transistors may be formed. The lower transistor may comprise a lower source contact <NUM>, a lower drain contact <NUM>, and a lower GAA gate region <NUM>, and the upper transistor may comprise an upper source contact <NUM>, an upper drain contact <NUM>, and an upper GAA gate region <NUM>. In an aspect, the lower GAA gate region <NUM> may be of a first conductivity type (e.g., P-type), and the upper GAA gate region <NUM> may be of a second conductivity type (e.g., N-type), which is opposite the first conductivity type. Hence, the lower and upper transistors may form complementary transistors. Details of the lower and upper GAA gate regions <NUM>, <NUM> will be described further below.

The lower and upper source and drain contacts <NUM>, <NUM>, <NUM>, <NUM> may be conductive. In an aspect, these contacts <NUM>, <NUM>, <NUM>, <NUM> may be formed from materials including palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), among others. Each contact <NUM>, <NUM>, <NUM>, <NUM> may be formed from any combination of such materials. Also, it is not required that all of the contacts <NUM>, <NUM>, <NUM>, <NUM> be made the same. That is, each of the contacts <NUM>, <NUM>, <NUM>, <NUM> may be formed materials independent of other contacts <NUM>, <NUM>, <NUM>, <NUM>.

A common gate <NUM> and spacers <NUM> may be formed in the IMD layer <NUM>. The common gate <NUM> may be between the between the lower source and drain contacts <NUM>, <NUM> and between the upper source and drain contacts <NUM>, <NUM>. The common gate <NUM> may be electrically conductive. For example, the common gate <NUM> may be formed from metals such as tungsten (W), titanium nitride (TiN), etc. On the other hand, the spacers <NUM> may be electrically insulative, e.g., may be formed from oxides, silicon nitride, alumina oxide, etc..

For ease of reference, the spacer <NUM> left of the common gate <NUM> (between the upper source contact <NUM> and the common gate <NUM> and also between the lower source contact <NUM> and the common gate <NUM>) may be referred to as the source spacer. Conversely, the spacer <NUM> right of the common gate <NUM> (between the upper drain contact <NUM> and the common gate <NUM> and also between the lower drain contact <NUM> and the common gate <NUM>) may be referred to as the drain spacer. In an aspect, the source spacer may be in contact with any of the common gate <NUM>, the lower source contact <NUM>, and/or the upper source contact <NUM>. Similarly, the drain spacer may be in contact with any of the common gate <NUM>, the lower drain contact <NUM>, and/or the upper drain contact <NUM>. In another aspect, the common gate <NUM> and/or the spacers <NUM> may vertically span an entire height of the IMD layer <NUM>, i.e., from an upper surface to a lower surface of the IMD layer <NUM>.

<FIG> illustrates an example embodiment of the lower GAA gate region <NUM>. As seen, the lower GAA gate region <NUM> may include one or more lower channel structures <NUM> spaced apart from each other. Each lower channel structures <NUM> may comprise a lower TMD channel <NUM>. In an aspect, the lower TMD channel <NUM> may be a 2D-material described above. For example, the lower TMD channel <NUM> may be formed from tungsten diselenide (WSe<NUM>). The lower TMD channel <NUM> may be very thin. As an example, the lower TMD channel <NUM> may be formed from one or two layers of the 2D-material (e.g., one or two layers of WSe<NUM>). The thickness of the lower TMD channel <NUM> may range between <NUM> and <NUM>. Also, adjacent lower TMD channels <NUM> may be spaced apart from each other by about ~<NUM>-<NUM>.

Gate oxide layers <NUM> may be formed on both lower and upper surfaces of the lower TMD channel <NUM>. In an aspect, the gate oxide layers <NUM> may physically contact the lower and/or the upper surfaces of the lower TMD channel <NUM>. For ease of reference, the gate oxide layer <NUM> on the lower and upper surfaces of the lower TMD channel <NUM> may respectively be referred to as "first lower gate oxide layer" and "second lower gate oxide layer". The first and/or the second lower gate oxide layers <NUM> may be high-k dielectric layers. Each gate oxide layer <NUM> may be a combination of hafnium oxide (HfO<NUM>) and aluminum oxide (Al<NUM>O<NUM>) or a combination of hafnium (Hf), HfO<NUM>, and Al<NUM>O<NUM>. The thickness of each gate oxide layer <NUM> may range between <NUM> and <NUM>.

Work function layers <NUM> may also be formed below and above the lower TMD channel <NUM>, e.g., below the first lower gate oxide layer and above the second lower gate oxide layer. In an aspect, the work function layers <NUM> may physically contact the lower surface of the first lower gate oxide layer and/or the upper surface of the second lower gate oxide layer. For ease of reference, the work function layer <NUM> on the lower surface of the first lower gate oxide layer may be referred to as "first lower work function layer" and the work function layer <NUM> on the upper surface of the second lower gate oxide layer may be referred to as "second lower work function layer". The work function layer <NUM> may be formed from metal, such as TiN, titanium alumina (TiAl), or both. The thickness of each work function layer <NUM> may range between <NUM> and <NUM>.

In an aspect, adjacent lower channel structures <NUM> may be spaced apart from each other by about <NUM> to <NUM>. This represents the thickness of the common gate <NUM> visible in <FIG> between the adjacent lower channel structures <NUM>.

<FIG> illustrates an example embodiment of the upper GAA gate region <NUM>. As seen, the upper GAA gate region <NUM> may include one or more upper channel structures <NUM> spaced apart from each other. Each upper channel structures <NUM> may comprise an upper TMD channel <NUM>. The upper TMD channel <NUM> may also be a 2D-material described above. For example, the upper TMD channel <NUM> may be formed from molybdenum disulfide (MoS<NUM>). The upper TMD channel <NUM> may be very thin. As an example, the upper TMD channel <NUM> may be formed from one or two layers of the 2D-material (e.g., one or two layers of MoS<NUM>). The thickness of the upper TMD channel <NUM> may range between <NUM> and <NUM>. Also, adjacent upper TMD channels <NUM> may be spaced apart from each other by about ~<NUM>-<NUM>.

Gate oxide layers <NUM> may be formed on both upper and upper surfaces of the upper TMD channel <NUM>. In an aspect, the gate oxide layers <NUM> may physically contact the upper and/or the upper surfaces of the upper TMD channel <NUM>. For ease of reference, the gate oxide layer <NUM> on the lower and upper surfaces of the upper TMD channel <NUM> may respectively be referred to as "first upper gate oxide layer" and "second upper gate oxide layer". The first and/or the second upper gate oxide layers <NUM> may be high-k dielectric layers. Each gate oxide layer <NUM> may be a combination of hafnium oxide (HfO<NUM>) and aluminum oxide (Al<NUM>O<NUM>) or a combination of hafnium (Hf), HfO<NUM>, and Al<NUM>O<NUM>. The thickness of each gate oxide layer <NUM> may range between <NUM> and <NUM>.

Work function layers <NUM> may also be formed below and above the upper TMD channel <NUM>, e.g., below the first upper gate oxide layer and above the second upper gate oxide layer. In an aspect, the work function layers <NUM> may physically contact the lower surface of the first upper gate oxide layer and/or the upper surface of the second upper gate oxide layer. For ease of reference, the work function layer <NUM> on the lower surface of the first upper gate oxide layer may be referred to as "first upper work function layer" and the work function layer <NUM> on the upper surface of the second upper gate oxide layer may be referred to as "second upper work function layer". The work function layer <NUM> may be formed from metal, such as TiN. The thickness of each work function layer <NUM> may range between <NUM> and <NUM>.

In an aspect, adjacent upper channel structures <NUM> may be spaced apart from each other by about <NUM> to <NUM>. This represents the thickness of the common gate <NUM> visible in <FIG> between the adjacent upper channel structures <NUM>.

Referring back to <FIG>, note that the lower TMD channels <NUM> (not numbered in <FIG>) may be electrically coupled with the lower source contact <NUM> and with the lower drain contact <NUM>. For example, the lower TMD channels <NUM> may be in physical contact with the lower source and drain contacts <NUM>, <NUM>. Similarly, the upper TMD channels <NUM> (not numbered in <FIG>) may be electrically coupled with the upper source contact <NUM> and with the upper drain contact <NUM>. For example, the upper TMD channels <NUM> may be in physical contact with the upper source and drain contacts <NUM>, <NUM>.

The common gate <NUM> may be configured to apply a common voltage to the lower and upper channel structures <NUM>, <NUM> to induce conductive paths in the lower TMD channels <NUM> between the lower source and drain contacts <NUM>, <NUM> and to induce conductive paths in the upper TMD channels <NUM> between the upper source and drain contacts <NUM>, <NUM>. In an aspect, upper surfaces of the upper source contact <NUM>, the spacers <NUM>, and common gate <NUM>, and the upper drain contact <NUM> may be planar with the upper surface of the IMD layer <NUM>.

The CFET structure <NUM> may include a lower source terminal <NUM> and a lower drain terminal <NUM> in the lower IMD layer <NUM>. The lower source terminal <NUM> and/or the lower drain terminal <NUM> may be formed form conductive materials such as highly doped silicon and metals (e.g., copper (Cu)). The lower source terminal <NUM> and/or the lower drain terminal <NUM> may be exposed at an upper surface of the lower IMD layer <NUM>. For example, upper surfaces of the terminals <NUM>, <NUM> and the lower IMD layer <NUM> may be planar. The lower source terminal <NUM> may be electrically coupled with the lower source contact <NUM> and the lower drain terminal <NUM> may be electrically coupled with the lower drain contact <NUM>. For example, the lower source terminal <NUM> may physically contact the lower source contact <NUM> and/or the lower drain terminal <NUM> may physically contact the lower drain contact <NUM>.

The CFET structure <NUM> may include an upper source terminal <NUM>, an upper drain terminal <NUM>, and an upper gate terminal <NUM> in the upper IMD layer <NUM>. The upper source terminal <NUM>, the upper drain terminal <NUM>, and/or the upper gate terminal <NUM> may be formed form conductive materials such as highly doped silicon and metals (e.g., copper (Cu)). The upper source terminal <NUM>, the upper drain terminal <NUM>, and/or the upper gate terminal <NUM> may be exposed at an upper surface of the upper IMD layer <NUM>. For example, upper surfaces of the terminals <NUM>, <NUM>, <NUM> and the upper IMD layer <NUM> may be planar.

The upper source terminal <NUM>, the upper drain terminal <NUM>, and the upper gate terminal <NUM> may be electrically coupled with the upper source contact <NUM>, the upper drain contact <NUM>, and common gate <NUM>. In an aspect, a source via <NUM> may be formed in the upper IMD layer <NUM> to electrically couple the upper source terminal <NUM> with the upper source contact <NUM>. Alternatively or in addition thereto, a drain via <NUM> may be formed in the upper IMD layer <NUM> to electrically couple the upper drain terminal <NUM> with the upper drain contact <NUM>. Still alternatively or in addition there to, a drain via <NUM> may be formed in the upper IMD layer <NUM> to electrically couple the upper drain terminal <NUM> with the upper drain contact <NUM>. When present, lower surfaces of the source, the drain, and gate vias <NUM>, <NUM>, <NUM> may be planar with the lower surface of the upper IMD layer <NUM>.

In an aspect, the CFET structure <NUM> may include a lower protection layer <NUM> and an upper protection layer <NUM>. The lower protection layer <NUM> may be between the lower IMD layer <NUM> and the IMD layer <NUM>, and the upper protection layer <NUM> may be on a top surface of the upper IMD layer <NUM>. One or both of the lower and upper protections layers <NUM>, <NUM> may be formed from silicon carbon nitride (SiCN).

Note that the CFET structure <NUM> of <FIG> includes a tail via <NUM> in the lower IMD layer <NUM> and in the IMD layer <NUM>. In particular, the tail via <NUM> electrically couples the lower drain terminal <NUM> with the upper drain terminal <NUM> (e.g., may be in physical contact with the lower drain terminal <NUM> and/or with the upper drain terminal <NUM>). In this configuration, the CFET structure may function as an inverter, i.e., as a NOT logic. That is, the Vout voltage (at the drain terminals <NUM>, <NUM>) may be logically opposite to a voltage applied at the gate <NUM>.

However, the GAA TMDs may be configured in other CFET structures to perform other functions. <FIG> illustrates an example C112FET structure <NUM> configured to perform a two-input NAND logic. As seen, the CFET structure <NUM> is shown to include the components of the structure in <FIG> - the lower source and drain terminals <NUM>, <NUM> in the lower IMD layer <NUM>; the upper source, drain and gate terminals <NUM>, <NUM>, <NUM> along with source, drain and gate vias <NUM>, <NUM>, <NUM> in the upper IMD layer <NUM>; and the lower source and drain contacts <NUM>, <NUM>, the upper source and drain contacts <NUM>, <NUM>, the lower and upper GAA gate regions <NUM>, <NUM>, the spacers <NUM>, and the common gate <NUM>. It may be assumed that the descriptions of these components provided with respect to <FIG> may also apply with respect to <FIG>.

As seen, the CFET structure <NUM> may also include second spacers <NUM>, a second common gate <NUM>, a second lower source contact <NUM>, a second lower drain contact <NUM>, a second lower GAA gate region <NUM>, a second upper source contact <NUM>, a second upper drain contact <NUM>, and a second upper GAA gate region <NUM>. The formation of the second contacts <NUM>, <NUM>, <NUM>, <NUM> may be similar to the contacts <NUM>, <NUM>, <NUM>, <NUM> (e.g., formed from any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, among others.

The second lower and upper GAA gate regions <NUM>, <NUM> may also be similar to the lower and upper GAA gate regions <NUM>, <NUM>. That is, the second lower GAA gate region <NUM> may be of the first conductivity type and the second upper GAA gate region <NUM> may be of the second conductivity type (e.g., see <FIG>). The second lower GAA gate region <NUM> may comprise one or more lower channel structures <NUM> (see <FIG>), and the second upper GAA gate region <NUM> may comprise one or more upper channel structures <NUM> (see <FIG>). For differentiation purposes, the components associated with the second lower and upper GAA gate regions <NUM>, <NUM> will be prefaced with "second". Thus, each second lower channel structure <NUM> of the second lower GAA gate region <NUM> may comprise a second lower TMD channel <NUM>, second-first and second-second lower gate oxide layers <NUM>, and second-first and second-second work function layers <NUM>. Similarly, each second upper channel structure <NUM> of the second upper GAA gate region <NUM> may comprise a second upper TMD channel <NUM>, second-first and second-second upper gate oxide layers <NUM>, and second-first and second-second work function layers <NUM>.

In the lower IMD layer <NUM>, a second lower source terminal <NUM> and a second lower drain terminal <NUM> may be formed. The second lower source terminal <NUM> may be electrically coupled with the second lower source contact <NUM>, and the second lower drain terminal <NUM> may be electrically coupled with the second lower drain contact <NUM>.

In the upper IMD layer <NUM>, a second upper drain terminal <NUM> and a second upper gate terminal <NUM> may be formed. The second upper drain terminal <NUM> may be electrically coupled (e.g., through a second drain via <NUM>) with the second upper drain contact <NUM>. The second upper gate terminal <NUM> may be electrically coupled (e.g., through a second gate via <NUM>) with the second common gate <NUM>. A second upper source terminal <NUM> electrically coupled (e.g., through second source via <NUM>) may also be formed. But in an aspect, the second source terminal <NUM> and the drain terminal <NUM> may be common, i.e., one and the same.

Note that the tail via <NUM> electrical couple the second lower drain terminal <NUM> with the second upper drain terminal <NUM>. In this configuration, the CFET structure <NUM> may perform a NAND logic of the inputs provided to the upper gate terminal <NUM> and to the second upper gate terminal <NUM>.

<FIG> illustrates an example CFET structure <NUM> configured to perform a two-input NOR logic. As seen, the CFET structure <NUM> is shown to include the components of the structure in <FIG> - the lower source and drain terminals <NUM>, <NUM> in the lower IMD layer <NUM>; the upper source, drain and gate terminals <NUM>, <NUM>, <NUM> along with source, drain and gate vias <NUM>, <NUM>, <NUM> in the upper IMD layer <NUM>; and the lower source and drain contacts <NUM>, <NUM>, the upper source and drain contacts <NUM>, <NUM>, the lower and upper GAA gate regions <NUM>, <NUM>, the spacers <NUM>, and the common gate <NUM>. It may be assumed that the descriptions of these components provided with respect to <FIG> may also apply with respect to <FIG>.

As seen, the CFET structure <NUM> may also include third spacers <NUM>, a third common gate <NUM>, a third lower source contact <NUM>, a third lower drain contact <NUM>, a third lower GAA gate region <NUM>, a third upper source contact <NUM>, a third upper drain contact <NUM>, and a third upper GAA gate region <NUM>. The formation of the third contacts <NUM>, <NUM>, <NUM>, <NUM> may be similar to the contacts <NUM>, <NUM>, <NUM>, <NUM> (e.g., formed from any one or more of Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, among others.

The third lower and upper GAA gate regions <NUM>, <NUM> may also be similar to the lower and upper GAA gate regions <NUM>, <NUM>. That is, the third lower GAA gate region <NUM> may be of the first conductivity type and the third upper GAA gate region <NUM> may be of the second conductivity type (e.g., see <FIG>). The third lower GAA gate region <NUM> may comprise one or more lower channel structures <NUM> (see <FIG>), and the third upper GAA gate region <NUM> may comprise one or more upper channel structures <NUM> (see <FIG>). For differentiation purposes, the components associated with the third lower and upper GAA gate regions <NUM>, <NUM> will be prefaced with "third". Thus, each third lower channel structure <NUM> of the third lower GAA gate region <NUM> may comprise a third lower TMD channel <NUM>, third-first and third-second gate oxide layers <NUM>, and third-first and third-second work function layers <NUM>. Similarly, each third upper channel structure <NUM> of the third upper GAA gate region <NUM> may comprise a third upper TMD channel <NUM>, third-first and third-second gate oxide layers <NUM>, and third-first and third-first work function layers <NUM>.

In the lower IMD layer <NUM>, a third lower drain terminal <NUM> electrically coupled with the third lower drain contact <NUM> may be formed. A third lower source terminal <NUM> may also be formed. But in an aspect, the lower drain terminal and the third lower source terminal <NUM> may be common.

In the upper IMD layer <NUM>, a third upper source terminal <NUM>, a third upper drain terminal <NUM>, and a third upper gate terminal <NUM> may be formed. The third upper source terminal <NUM> may be electrically coupled (e.g., through a third source via <NUM>) with the third upper source contact <NUM>. The third upper drain terminal <NUM> may be electrically coupled (e.g., through a third drain via <NUM>) with the third upper drain contact <NUM>. The third upper gate terminal <NUM> may be electrically coupled (e.g., through a third gate via <NUM>) with the third common gate <NUM>.

Note that the tail via <NUM> electrical couple the third lower drain terminal <NUM> with the third upper drain terminal <NUM>. In this configuration, the CFET structure <NUM> may perform a NOR logic of the inputs provided to the upper gate terminal <NUM> and to the third upper gate terminal <NUM>.

<FIG> illustrates another example of a CFET structure <NUM> in accordance with one or more aspects of the disclosure. The CFET structure <NUM> the is much like CFET structure <NUM> of <FIG> in that both include many of the same elements. The like numbered elements may be assumed to behave same in both structures. Thus, the differences between <FIG> and <FIG> will be described.

One difference is that the CFET structure <NUM> is shown may include a lower GAA gate region <NUM> and an upper GAA gate region <NUM> (instead of the lower and upper GAA gate regions <NUM>, <NUM>). The lower GAA gate region <NUM> may be of a first conductivity type and the upper GAA gate region <NUM> may be of a second conductivity type opposite the first conductivity type.

As seen in in <FIG>, the lower GAA gate region <NUM> may include one or more lower channel structures <NUM>. Each lower channel structure <NUM> may comprise a lower TMD channel <NUM>. The lower TMD channel <NUM> may be formed from 2D-materials. In an aspect, the lower TMD channel <NUM> may be formed from one of WSe<NUM> and MoS<NUM>. The lower TMD channel <NUM> may be very thin. As an example, the lower TMD channel <NUM> may be formed from one or two layers of the 2D-material. The thickness of the lower TMD channel <NUM> may range between <NUM> and <NUM>. Also, adjacent lower TMD channels <NUM> may be spaced apart from each other by about ~<NUM>-<NUM>.

Each lower channel structure <NUM> may also include first and second lower gate oxide layers <NUM> (e.g., below and above the lower TMD channel <NUM>). The first and second lower gate oxide layers <NUM> may be similar to the first and second lower gate oxide layers <NUM> of <FIG>. Each lower channel structure <NUM> may further include first and second lower work function layers <NUM>. The first and second lower work function layers <NUM> may be similar to the first and second lower work function layers <NUM> of <FIG>.

As seen in in <FIG>, the upper GAA gate region <NUM> may include one or more upper channel structures <NUM>. Each upper channel structure <NUM> may comprise an upper TMD channel <NUM>. The upper TMD channel <NUM> may be formed from 2D-materials. In an aspect, the upper TMD channel <NUM> may be formed from the other one of WSe<NUM> and MoS<NUM>. The upper TMD channel <NUM> may be very thin. As an example, the upper TMD channel <NUM> may be formed from one or two layers of the 2D-material. The thickness of the upper TMD channel <NUM> may range between <NUM> and <NUM>. Also, adjacent upper TMD channels <NUM> may be spaced apart from each other by about ~<NUM>-<NUM>.

Each upper channel structure <NUM> may also include first and second upper gate oxide layers <NUM> (e.g., below and above the upper TMD channel <NUM>). The first and second upper gate oxide layers <NUM> may be similar to the first and second upper gate oxide layers <NUM> of <FIG>. Each upper channel structure <NUM> may further include first and second upper work function layers <NUM>. The first and second upper work function layers <NUM> may be similar to the first and second upper work function layers <NUM> of <FIG>.

Referring back to <FIG>, another difference is that the CFET structure <NUM> may also include a lower inner source contact <NUM> and a lower outer drain contact <NUM>. The lower inner source contact <NUM> may be between the lower source contact <NUM> and the lower GAA gate region <NUM>, and the lower inner drain contact <NUM> may be between the lower GAA gate region <NUM> and the lower drain contact <NUM>. The lower inner source and drain contacts <NUM>, <NUM> may be conductive. In an aspect, the contacts <NUM>, <NUM> may me formed from materials similar to those of contacts <NUM>, <NUM>. The lower source contact <NUM> may be shifted to the left so as to be laterally outside of the upper source contact <NUM>. Alternatively or in addition thereto, the lower drain contact <NUM> may be shifted to the right so as to be laterally outside of the upper drain contact <NUM>.

Note that the lower source contact <NUM> may be electrically coupled with the lower TMD channels <NUM> (not numbered in <FIG>), e.g., through the lower inner source contact <NUM>. Also, the lower drain contact <NUM> may be electrically coupled with the lower TMD channels <NUM>, e.g., through the lower inner drain contact <NUM>. In an aspect, the lower inner source contact <NUM> may physically contact the lower source contact <NUM> and the lower TMD channels <NUM>. Alternatively or in addition thereto, the lower inner drain contact <NUM> may physically contact the lower drain contact <NUM> and the lower TMD channels <NUM>.

As seen, the lower TMD channels <NUM> may extend into the lower inner source contact <NUM> and/or into the lower inner drain contact <NUM>. Alternatively or in addition thereto, the lower TMD channels <NUM> may also extend into the lower source contact <NUM> and/or into the lower drain contact <NUM>. Further alternatively or in addition thereto, the upper TMD channels <NUM> (not numbered in <FIG>) may extend into the upper source and/or drain contacts <NUM>, <NUM>. When the lower and/or upper TMD chnnels <NUM>, <NUM> extend into the contacts <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, the contact area is increased. This can reduce the contact resistance, which is beneficial.

The CFET structure <NUM> includes tail via <NUM> in the lower IMD layer <NUM> and in the IMD layer <NUM>. Thus, like the CFET structure <NUM> (of <FIG>), the CFET structure <NUM> is also configured to perform a NOT logic.

<FIG> illustrates a CFET structure <NUM> configured to perform a NAND logic like the CFET structure <NUM> (of <FIG>). The following are some of the differences between <FIG> and <FIG>. First, the CFET structure <NUM> can include the lower inner source contact <NUM>, the lower inner drain contact <NUM>, the second lower inner source contact <NUM>, and the second lower inner drain contact <NUM>. Also, the second lower TMD channels <NUM> (not numbered in <FIG>) may respectively extend into the second lower inner source contact <NUM> and/or into the second lower inner drain contact <NUM>. Further, the second upper TMD channels <NUM> (not numbered in <FIG>) may respectively extend into the second upper source contact <NUM> and/or into the second upper drain contact <NUM>. Note that the CFET structure <NUM> may include second lower and upper GAA gate regions <NUM>, <NUM>.

<FIG> illustrates a CFET structure <NUM> configured to perform a NOR logic like the CFET structure <NUM> (of <FIG>). The following are some of the differences between <FIG> and <FIG>. First, the CFET structure <NUM> can include the lower inner source contact <NUM>, the lower inner drain contact <NUM>, the third lower inner source contact <NUM>, and the third lower inner drain contact <NUM>. Also, the third lower TMD channels <NUM> (not numbered in <FIG>) may respectively extend into the third lower inner source contact <NUM> and/or into the third lower inner drain contact <NUM>. Further, the third upper TMD channels <NUM> (not numbered in <FIG>) may respectively extend into the third upper source contact <NUM> and/or into the third upper drain contact <NUM>. Note that the CFET structure <NUM> may include third lower and upper GAA gate regions <NUM>, <NUM>.

<FIG> illustrate examples of stages of fabricating a CFET structure - such as the CFET structures <NUM>, <NUM>, <NUM> - in accordance with one or more aspects of the disclosure.

<FIG> illustrates a stage in which fabrication starts from a back-end-of-line (BEOL) IMD layer (x-<NUM>) - i.e., the lower IMD layer <NUM>. Here, metal layer x-<NUM> may be deposited and patterned to form the lower source terminal <NUM> and the lower drain terminal <NUM>. The lower protection layer <NUM> may be formed on the lower IMD layer <NUM> by depositing and patterning (e.g., polishing) protection material (e.g., SiCn).

<FIG> illustrates a stage in which multiple oxide/ HfO<NUM>/2D film (e.g., WSe<NUM>) layers are deposited for first conductivity type transistor (e.g., P-type). The active and oxide films may be patterned at the gate area while keeping the 2D film materials. Spacer material (e.g., SiN) may be deposited and etched to form the spacers <NUM>. In short, the lower TMD channels <NUM> and HfO<NUM> layers <NUM> (which is temporary) may be formed. Note that the spacers <NUM> are partial at this stage.

<FIG> illustrates a stage in which an IMD oxide material may be deposited and planarized (e.g., through chemical-mechanical polishing (CMP)) to form the IMD layer <NUM>. The gate area may be opened and the oxide in the gate area may be removed. The IMD layer <NUM> is partial at this stage.

<FIG> illustrates a stage in which previous HfO<NUM> layers <NUM> are removed. Then HfO<NUM>/Al<NUM>O<NUM> or Hf/ HfO<NUM>/Al<NUM>O<NUM> may be deposited (e.g., through atomic layer deposition (ALD)) to form the lower gate oxide layers <NUM>. The lower working function layers <NUM> may be formed (e.g., by ALD deposition of TiN). Also, common gate <NUM> may be formed (e.g., by depositing W and polishing). Note that the common gate <NUM> is partial at this stage.

<FIG> illustrates a stage in which the lower GAA gate region <NUM> is formed. Here, the lower source and drain contacts <NUM>, <NUM> may be formed by patterning the IMD layer <NUM> and the lower protection layer <NUM> and depositing conductive materials (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned area. The deposited materials may then be polished (e.g., CMP).

<FIG> illustrates a stage in which multiple oxide/HfO<NUM>/2D film (e.g., MoS<NUM>) layers are deposited for second conductivity type transistor (e.g., N-type). The active and oxide films may be patterned at the gate area while keeping the 2D film materials. Spacer material (e.g., SiN) may be deposited and etched to further form the spacers <NUM>. In short, the upper TMD channels <NUM> and HfO<NUM> layers <NUM> (which is temporary) may be formed. Note that the spacers <NUM> may be at full height at this stage.

<FIG> illustrates a stage in which more IMD oxide may be deposited and planarized (e.g., through CMP) to further form the IMD layer <NUM>. The gate area may be opened and the oxide in the gate area may be removed. The IMD layer <NUM> may be at full height at this stage.

<FIG> illustrates a stage in which illustrates a stage in which previous HfO<NUM> layers <NUM> are removed. Then HfO<NUM>/Al<NUM>O<NUM> or Hf/ HfO<NUM>/Al<NUM>O<NUM> may be deposited (e.g., through ALD) to form the upper gate oxide layers <NUM>. The upper working function layers <NUM> may be formed (e.g., by ALD deposition of TiN). Also, common gate <NUM> may be further formed (e.g., by depositing W and polishing). Note that the common gate <NUM> can at full height at this stage.

<FIG> illustrates a stage in which the upper GAA gate region <NUM> is formed. Here, the areas for the upper source and drain contacts <NUM>, <NUM> may be patterned in the IMD layer <NUM>. The patterned areas may be deposited with conductive materials (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., CMP).

<FIG> illustrates a stage in which more IMD oxide layer may be deposited and patterned to form the upper IMD layer <NUM>. Here, metal layer x+<NUM> may be deposited and patterned to form the upper source terminal <NUM>, upper drain terminal <NUM>, and the upper gate terminal <NUM>. The source, drain, and gate vias <NUM>, <NUM>, <NUM> may also be formed. Further, the lower protection layer <NUM>, the IMD layer <NUM>, and the upper IMD layer <NUM> may be patterned, and conductive material may be deposited in the patterned area to form the tail via <NUM>. The upper protection layer <NUM> may be formed on the upper IMD layer <NUM> by depositing and patterning (e.g., polishing) protection material (e.g., SiCN).

<FIG> illustrates a stage in which fabrication starts from a back-end-of-line (BEOL) IMD layer (x-<NUM>) - i.e., the lower IMD layer <NUM>. Here, metal layer x-<NUM> may be deposited and patterned to form the lower source terminal <NUM> and the lower drain terminal <NUM>. The lower protection layer <NUM> may be formed on the lower IMD layer <NUM> by depositing and patterning (e.g., polishing) protection material (e.g., SiCN).

<FIG> illustrates a stage in which multiple oxide/ HfO<NUM>/2D film (e.g., one of MoS<NUM> and WSe<NUM>) layers are deposited for first conductivity type transistor (e.g., P-type). The active and oxide films may be patterned at the gate area while keeping the 2D film materials. Spacer material (e.g., SiN) may be deposited and etched to form the spacers <NUM>. In short, the lower TMD channels <NUM> and HfO<NUM> layers <NUM> (which is temporary) may be formed. Note that the lower TMD channels <NUM> are wider than the lower TMD channels <NUM> (of <FIG>). For example, the lower TMD channels <NUM> may extend beyond the spacers <NUM>. Also note that the spacers <NUM> are partial at this stage.

<FIG> illustrates a stage in which an IMD oxide material may be deposited and planarized (e.g., through (CMP) to form the IMD layer <NUM>. The gate area may be opened and the oxide in the gate area may be removed. The IMD layer <NUM> is partial at this stage.

<FIG> illustrates a stage in which previous HfO<NUM> layers <NUM> are removed. Then HfO<NUM>/Al<NUM>O<NUM> or Hf/ HfO<NUM>/Al<NUM>O<NUM> may be deposited (e.g., through ALD) to form the lower gate oxide layers <NUM>. The lower working function layers <NUM> may be formed (e.g., by ALD deposition of TiN). Also, common gate <NUM> may be formed (e.g., by depositing W and polishing). Note that the common gate <NUM> is partial at this stage.

<FIG> illustrates a stage in which the lower GAA gate region <NUM> is formed. Here, the lower inner source and drain contacts <NUM>, <NUM> may be formed by patterning the IMD layer <NUM> and depositing conductive materials (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned area. Also, the lower source and drain contacts <NUM>, <NUM> may be formed by patterning the IMD layer <NUM> and the lower protection layer <NUM> and depositing conductive materials (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) in the patterned area. The deposited materials for the inner source and drain contacts <NUM>, <NUM> and for the lower source and drain contacts <NUM>, <NUM> may be polished (e.g., CMP).

<FIG> illustrates a stage in which multiple oxide/ HfO<NUM>/2D film (e.g., MoS<NUM>) layers are deposited for second conductivity type transistor (e.g., N-type). The active and oxide films may be patterned at the gate area while keeping the 2D film materials. Spacer material (e.g., SiN) may be deposited and etched to further form the spacers <NUM>. In short, the upper TMD channels <NUM> and HfO<NUM> layers <NUM> (which is temporary) may be formed. Note that the spacers <NUM> may be at full height at this stage.

<FIG> illustrates a stage in which illustrates a stage in which previous HfO<NUM> layers <NUM> are removed. Then HfO<NUM>/Al<NUM>O<NUM> or Hf/ HfO<NUM>/Al<NUM>O<NUM> may be deposited (e.g., through ALD) to form the upper gate oxide layers <NUM>. The upper working function layers <NUM> may be formed (e.g., by ALD deposition of TiN). Also, common gate <NUM> may be further formed (e.g., by depositing W and polishing). Note that the upper TMD channels <NUM> are wider than the upper TMD channels <NUM> (of <FIG>). For example, the upper TMD channels <NUM> may extend beyond the spacers <NUM>. Also note that the common gate <NUM> can at full height at this stage.

<FIG> illustrates a stage in which the upper GAA gate region <NUM> is formed. Here, the areas for the upper source and drain contacts <NUM>, <NUM> may be pattemed in the IMD layer <NUM>. The patterned areas may be deposited with conductive materials (e.g., Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, etc.) and polished (e.g., CMP).

<FIG> illustrates a flow chart of an example method <NUM> of manufacturing a CFET structure (e.g., CFET structures <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) in accordance with at one or more aspects of the disclosure. In block <NUM>, a lower source contact (e.g., lower source contact <NUM>) and a lower drain contact (e.g., lower drain contact <NUM>) may be formed in an intermetal dielectric (IMD) layer (e.g., IMD layer <NUM>). Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a lower gate-all-around (GAA) gate region (e.g., a lower GAA gate region <NUM>) may be formed in the IMD layer between the lower source and drain contacts (e.g., lower source and drain contact <NUM>, <NUM>). The lower GAA gate region may be a first conductivity type (e.g., P-type) and may comprise one or more lower channel structures (e.g., lower channel structures <NUM>, <NUM>). Each lower channel structure may comprise a lower transition metal dichalcogenide (TMD) channel (e.g., lower TMD channel <NUM>, <NUM>). The lower TMD channel may be electrically coupled with the lower source contact and with the lower drain contact. The lower TMD channel may also comprise first and second lower gate oxide layers (e.g., lower gate oxide layers <NUM>, <NUM>) respectively on lower and upper surfaces of the lower TMD channel. The lower channel structure may further comprise first and second lower work function layers (e.g., lower work function layers <NUM>, <NUM>) respectively on a lower surface of the first lower gate oxide layer and on an upper surface of the second lower gate oxide layer. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, an upper source contact (e.g., upper source contact <NUM>) and an upper drain contact (e.g., upper drain contact <NUM>) may be formed in the IMD layer above the lower source and drain contacts. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, an upper gate-all-around (GAA) gate region (e.g., an upper GAA gate region <NUM>) may be formed in the IMD layer between the upper source and drain contacts. The upper GAA gate region may be a second conductivity type (e.g., N-type) opposite the first conductivity type and may comprise one or more upper channel structures (e.g., upper channel structures <NUM>, <NUM>). Each upper channel structure may comprise an upper transition metal dichalcogenide (TMD) channel (e.g., upper TMD channel <NUM>, <NUM>). The upper TMD channel may be electrically coupled with the upper source contact and with the upper drain contact. The upper TMD channel may also comprise first and second upper gate oxide layers (e.g., upper gate oxide layers <NUM>, <NUM>) respectively on lower and upper surfaces of the upper TMD channel. The upper channel structure may further comprise first and second upper work function layers (e.g., upper work function layers <NUM>, <NUM>) respectively on an upper surface of the first upper gate oxide layer and on an upper surface of the second upper gate oxide layer. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a common gate (e.g., common gate <NUM>) may be formed in the IMD layer between the lower source and drain contacts and between the upper source and drain contacts. The common gate may be configured to apply a common voltage to the lower and upper channel structures to induce conductive paths in the lower TMD channels between the lower source and drain contacts and to induce conductive paths in the upper TMD channels between the upper source and drain contacts. Block <NUM> may correspond to the stages illustrated in <FIG>, <FIG>, <FIG>, and <FIG>.

<FIG> illustrates a flow chart of an example method <NUM> of manufacturing a CFET structure (e.g., CFET structures <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) in accordance with at one or more aspects of the disclosure. <FIG> may be view as being more comprehensive than <FIG>.

Thus, blocks <NUM> - <NUM> may be similar to blocks <NUM> - <NUM>. Therefore, detailed descriptions of blocks <NUM> - <NUM> will be omitted for sake of brevity.

In block <NUM>, lower inner contacts may be formed in the IMD layer. <FIG> illustrates a flow chart of an example process to implement block <NUM>. In block <NUM>, a lower inner source contact (e.g., lower inner source <NUM>) may be formed between the lower outer source contact and the lower GAA gate region. Block <NUM> may correspond to the stage illustrated in <FIG>.

In block <NUM>, a lower inner drain contact (e.g., lower inner contact <NUM>) may be formed between the lower GAA gate region and the lower outer drain contact. Block <NUM> may also correspond to the stage illustrated in <FIG>.

Referring back to <FIG>, in block <NUM>, spacers may be formed in the IMD layer. <FIG> illustrates a flow chart of an example process to implement block <NUM>. In block <NUM>, a source spacer (e.g., left spacer <NUM>, <NUM>) may be formed between the lower source contact and the common gate and between the upper source contact and the common gate. The source spacer may span from the upper surface of the IMD layer to the lower surface of the IMD layer. Block <NUM> may correspond to the stages illustrated in <FIG>, <FIG>, <FIG>, and <FIG>.

In block <NUM>, a drain spacer (e.g., right spacer <NUM>, <NUM>) may be formed between the lower drain contact and the common gate and between the upper drain contact and the common gate <NUM>. The drain spacer may span from the upper surface of the IMD layer to the lower surface of the IMD layer. Block <NUM> may also correspond to the stages illustrated in <FIG>, <FIG>, <FIG>, and <FIG>.

Referring back to <FIG>, in block <NUM>, terminals may be formed in the upper and lower IMD layers (e.g., upper IMD layer <NUM>, lower IMD layer <NUM>). <FIG> illustrates a flow chart of an example process to implement block <NUM>. In block <NUM>, a lower source terminal (e.g., lower source terminal <NUM>) may be formed in the lower IMD layer. The lower source terminal may be electrically coupled with the lower source contact. The lower IMD layer may be on a lower surface of the IMD layer. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a lower drain terminal (e.g., lower drain terminal <NUM>) may be formed in the lower IMD layer. The lower drain terminal may be electrically coupled with the lower source contact. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, an upper source terminal (e.g., upper source terminal <NUM>) may be formed in the upper IMD layer. The upper source terminal may be electrically coupled with the upper source contact. The upper IMD layer may be on an upper surface of the IMD layer. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a source via (e.g., source via <NUM>) may be formed in the upper IMD layer. The source via may electrically couple the upper source terminal with the upper source contact. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, an upper drain terminal (e.g., upper drain terminal <NUM>) may be formed in the upper IMD layer. The upper drain terminal may be electrically coupled with the upper drain contact. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a drain via (e.g., drain via <NUM>) may be formed in the upper IMD layer. The drain via may electrically couple the upper drain terminal with the upper drain contact. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, an upper gate terminal (e.g., upper gate terminal <NUM>) may be formed in the upper IMD layer. The upper gate terminal may be electrically coupled with the common gate. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

In block <NUM>, a gate via (e.g., gate via <NUM>) may be formed in the upper IMD layer. The gate via may electrically couple the upper gate terminal with the common gate. Block <NUM> may correspond to the stages illustrated in <FIG> and <FIG>.

It will be appreciated that the foregoing fabrication processes and related discussion are provided merely as a general illustration of some of the aspects of the disclosure and is not intended to limit the disclosure or accompanying claims. Further, many details in the fabrication process known to those skilled in the art may have been omitted or combined in summary process portions to facilitate an understanding of the various aspects disclosed without a detailed rendition of each detail and/or all possible process variations. Further, it will be appreciated that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of the inductors, the metallization structure may have more or less conductive and insulating layers, the cavity orientation, size, whether it is formed of multiple cavities, is closed or open, and other aspects may have variations driven by specific application design features, such as the number of antennas, antenna type, frequency range, power, etc. Accordingly, the forgoing illustrative examples and associated figures should not be construed to limit the various aspects disclosed and claimed herein.

<FIG> illustrates various electronic devices <NUM> that may be integrated with any of the aforementioned devices in accordance with various aspects of the disclosure. For example, a mobile phone device <NUM>, a laptop computer device <NUM>, and a fixed location terminal device <NUM> may each be considered generally user equipment (UE) and may include one or more CFET structures (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) as described herein. The devices <NUM>, <NUM>, <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also include the RF filter including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), an Internet of things (IoT) device or any other device that stores or retrieves data or computer instructions or any combination thereof.

The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products may include semiconductor wafers that are then cut into semiconductor die and packaged into an antenna on glass device. The antenna on glass device may then be employed in devices described herein.

Implementation examples are described in the following numbered clauses:.

As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communications device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal ," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variants thereof may interchangeably refer to any suitable mobile or stationary device that can receive wireless communication and/or navigation signals. These terms include, but are not limited to, a music player, a video player, an entertainment unit, a navigation device, a communications device, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an automotive device in an automotive vehicle, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices which communicate with another device that can receive wireless communication and/or navigation signals such as by short-range wireless, infrared, wireline connection, or other connection, regardless of whether satellite signal reception, assistance data reception, and/or position-related processing occurs at the device or at the other device. In addition, these terms are intended to include all devices, including wireless and wireline communication devices, that are able to communicate with a core network via a radio access network (RAN), and through the core network the UEs can be connected with external networks such as the Internet and with other UEs. Of course, other mechanisms of connecting to the core network and/or the Internet are also possible for the UEs, such as over a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE <NUM>, etc.) and so on. UEs can be embodied by any of a number of types of devices including but not limited to printed circuit (PC) cards, compact flash devices, external or internal modems, wireless or wireline phones, smartphones, tablets, tracking devices, asset tags, and so on. A communication link through which UEs can send signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which the RAN can send signals to UEs is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein the term traffic channel (TCH) can refer to either an uplink / reverse or downlink / forward traffic channel.

The wireless communication between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), <NUM> New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE <NUM> (WiFi), and IEEE <NUM>. <NUM> (Zigbee/Thread) or other protocols that may be used in a wireless communications network or a data communications network. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group intended to provide considerably reduced power consumption and cost while maintaining a similar communication range. BLE was merged into the main Bluetooth standard in <NUM> with the adoption of the Bluetooth Core Specification Version <NUM> and updated in Bluetooth <NUM>.

" Any details described herein as "exemplary" is not to be construed as advantageous over other examples. Likewise, the term "examples" does not mean that all examples include the discussed feature, advantage or mode of operation. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described herein can be configured to perform at least a portion of a method described herein.

It should be noted that the terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are "connected" or "coupled" together via the intermediate element unless the connection is expressly disclosed as being directly connected.

Any reference herein to an element using a designation such as "first," "second," and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements can comprise one or more elements.

Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques.

Nothing stated or illustrated depicted in this application is intended to dedicate any component, action, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, action, feature, benefit, advantage, or the equivalent is recited in the claims.

In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples have more features than are explicitly mentioned in the respective claim. Rather, the disclosure may include fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that-although a dependent claim can refer in the claims to a specific combination with one or one or more claims-other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.

It should furthermore be noted that methods, systems, and apparatus disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective actions and/or functionalities of the methods disclosed.

Furthermore, in some examples, an individual action can be subdivided into one or more sub-actions or contain one or more sub-actions. Such sub-actions can be contained in the disclosure of the individual action and be part of the disclosure of the individual action.

Claim 1:
A complementary field effect transistor, CFET, structure, comprising:
a lower source contact (<NUM>) and a lower drain contact (<NUM>) in an intermetal dielectric, IMD, layer (<NUM>);
a lower gate-all-around, GAA, gate region (<NUM>) in the IMD layer (<NUM>) between the lower source and drain contacts (<NUM>, <NUM>), the lower GAA gate region (<NUM>) being a first conductivity type and comprising one or more lower channel structures, each lower channel structure (<NUM>) comprising:
a lower transition metal dichalcogenide, TMD, channel (<NUM>) electrically coupled with the lower source contact (<NUM>) and with the lower drain contact (<NUM>); and
first and second lower gate oxide layers (<NUM>) respectively on lower and upper surfaces of the lower TMD channel (<NUM>);
an upper source contact (<NUM>) and an upper drain contact (<NUM>) in the IMD layer (<NUM>) above the lower source and drain contacts (<NUM>, <NUM>);
an upper GAA gate region (<NUM>) in the IMD layer (<NUM>) above the lower GAA gate region (<NUM>) and between the upper source and drain contacts (<NUM>, <NUM>), the upper GAA gate region (<NUM>) being a second conductivity type opposite the first conductivity type and comprising one or more upper channel structures, each upper channel structure (<NUM>) comprising:
an upper TMD channel (<NUM>) electrically coupled with the upper source contact and with the upper drain contact (<NUM>, <NUM>); and
first and second upper gate oxide layers (<NUM>) respectively on lower and upper surfaces of the upper TMD channel (<NUM>); and
a common gate (<NUM>) in the IMD layer (<NUM>) between the lower source and drain contacts (<NUM>, <NUM>) and between the upper source and drain contacts (<NUM>, <NUM>), the common gate (<NUM>) being configured to apply a common voltage to the lower and upper channel structures (<NUM>, <NUM>).