Patent Description:
The present invention generally relates to voltage measurements, and more specifically to, an improved accuracy for voltage measurement over extended operating conditions.

Operating conditions on aircraft can include a temperature range between -<NUM> to +<NUM>. With these extended operating conditions, components utilized for tasks such as measuring voltages from sensors and other devices can have a higher associated costs due to the need for the component having a larger temperature operating range. For example, analog-to-digital converters (ADCs) increase in cost for larger temperature operating ranges. Designing systems for wide temperature ranges while decreasing costs can present a challenge in design. One methodology is to design systems that do not require the use of certain components that drive up the costs while maintaining accuracy of the systems.

Prior art <CIT> teaches a device for detecting the peak value of a signal using a filtered pwm signal as reference for a comparator. Further, <CIT> teaches a device for detecting the peak value of a signal using a counter and DAC as reference for a comparator. Even further, <CIT> exemplifies the use of a microprocessor pwm output as a reference for a comparator, wherein the duty cycle is iteratively changed to match the signal amplitude and then taken as a measure of it.

Embodiments of the present invention are directed to a voltage measurement system. According to the invention the voltage measurement system includes a comparator having a positive input terminal and a negative input terminal, a processor configured to supply a reference voltage signal to the negative input terminal of the comparator, wherein the positive input terminal of the comparator receives an input voltage, setting the reference voltage signal to a zero voltage signal, determine a line frequency of the input voltage based on a timing signal from an output of the comparator and determining a first pulse width of the input signal based on the timing signal, set the reference voltage to a pulse width modulation signal with a fixed duty cycle, receive the timing signal from the output of the comparator, determine a rising edge and a falling edge associated with the input voltage based on the timing signal, and determine a peak value of the input voltage based on a second pulse width between the rising edge and falling edge of the input voltage.

In addition to or as an alternative to any prior system, determining the line frequency of the input voltage based on a timing signal from the output of the comparator and determining a pulse width associated with the timing signal can include: determining a second rising edge associated with the input voltage based on the timing signal; determining a second falling edge associated with the input voltage based on the timing signal; and calculating the pulse width based on an output of the comparator between the second rising edge and the second falling edge.

In addition to or as an alternative to any prior system, determining the peak value of the input voltage based on the second pulse width between the rising edge and falling edge of the input voltage can include: determining a delta between the first pulse width and the second pulse width; and calculating the peak value of the input voltage based on the delta and the line frequency.

In addition to or as an alternative to any prior system, the first pulse width can be larger than the second pulse width.

In addition to or as an alternative to any prior system, the input voltage can be scaled prior to be received by the comparator.

In addition to or as an alternative to any prior system, the input voltage can be a voltage reading taken from a component on an aircraft.

In addition to or as an alternative to any prior system, the system can further include: a resistor capacitor (RC) circuit connected between a reference signal output of the processor and the negative input terminal of the comparator.

In addition to or as an alternative to any prior system, the system can further include: a buffer circuit connected between the RC circuit and the reference signal output of the processor, wherein the buffer circuit includes a reference voltage supply voltage.

In addition to or as an alternative to any prior system, the system can further include: a digital isolation circuit connected between the buffer circuit and the reference signal output of the processor.

In addition to or as an alternative to any prior system, the system can further include: a digital isolation circuit coupled between the output of the comparator and the processor.

Embodiments of the present invention are directed to a method. According to the invention the method includes providing, by a processor, a reference voltage signal to a negative input terminal of a comparator, wherein a positive input terminal of the comparator receives an input voltage, setting, by the processor, the reference voltage signal to a zero voltage signal, determining, by the processor, a line frequency of the input voltage based on a timing signal from an output of the comparator and determining a first pulse width of the input signal based on the timing signal, setting, by the processor, the reference voltage to a pulse width modulation signal with a fixed duty cycle, receiving the timing signal from the output of the comparator, determining a rising edge and a falling edge associated with the input voltage based on the timing signal, and determining a peak value of the input voltage based on a second pulse width between the rising edge and falling edge of the input voltage.

In additional to or as an alternative to any prior method, determining the line frequency of the input voltage based on a timing signal from the output of the comparator and determining a pulse width associated with the timing signal can include: determining a second rising edge associated with the input voltage based on the timing signal; determining a second falling edge associated with the input voltage based on the timing signal; and calculating the pulse width based on an output of the comparator between the second rising edge and the second falling edge.

In additional to or as an alternative to any prior method, determining the peak value of the input voltage based on the second pulse width between the rising edge and falling edge of the input voltage can include: determining a delta between the first pulse width and the second pulse width; and calculating the peak value of the input voltage based on the delta and the line frequency.

In additional to or as an alternative to any prior method, the first pulse width can be larger than the second pulse width.

In additional to or as an alternative to any prior method, the input voltage may be scaled prior to be received by the comparator.

In additional to or as an alternative to any prior method, the input voltage may be a voltage reading taken from a component on an aircraft.

In additional to or as an alternative to any prior method, a resistor capacitor (RC) circuit may be connected between a reference signal output of the processor and the negative input terminal of the comparator.

In additional to or as an alternative to any prior method, a buffer circuit can be connected between the RC circuit and the reference signal output of the processor.

In additional to or as an alternative to any prior method, a digital isolation circuit is connected between the buffer circuit and the reference signal output of the processor.

In additional to or as an alternative to any prior method, a digital isolation circuit may be coupled between the output of the comparator and the processor.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term "coupled" and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.

<FIG> illustrates an example of a commercial aircraft <NUM> having aircraft engines <NUM> that may embody aspects of the teachings of this disclosure. The aircraft <NUM> includes two wings <NUM> that each include one or more slats <NUM> and one or more flaps <NUM>. The aircraft further includes ailerons <NUM>, spoilers <NUM>, horizontal stabilizer trim tabs <NUM>, rudder <NUM> and horizontal stabilizer <NUM>. The term "control surface" used herein includes but is not limited to either a slat or a flap or any of the above described. It will be understood that the slats <NUM> and/or the flaps <NUM> can include one or more slat/flap panels that move together. The aircraft <NUM> also includes an system <NUM> (described in greater detail in <FIG>) which allows AC voltage measurement without the need for analog to digital converters to be utilized for various instrumentation on board the aircraft <NUM>.

Turning now to an overview of technologies that are more specifically relevant to aspects of the disclosure, in aircraft applications, meeting the required resolution, accuracy of AC voltage measurement over the extended operating temperature (-<NUM> to +<NUM>) can present challenges. Conventional designs for measuring an AC voltage typically use commercial off the shelf analog to digital converters (ADC) to sample and digitize an input AC voltage. For a given resolution and accuracy, selecting the correct ADC with a wide operating temperature presents challenges. Because of the need for more resolution and accuracy within these temperature ranges, AC voltage measurement systems have been utilizes premium ADC parts that have associated premium costs with fewer suppliers for supplying these premium ADC parts. Further, these premium ADC parts place a computational burden on the computational engine (e.g., FPGA, DSP, etc.) for the specified mathematical accuracy and logic consumption. Use of available premium ADCs in safety critical applications can lead to more scrutiny for verification and final certification. In many cases, the ADC will be multiplexed to measure different parameters, detecting the faults on the AC measurements some times increases ADC sampling requirements with a lower response time. Finally, one engineering practice is to design a system with dissimilar designs to meet particular safety requirements to remove common mode failures.

Aspects of the present disclosure address the above described issues by providing a system for AC voltage measurement without using an ADC and utilizing the computational engine core capabilities. Exemplary computational engines include, but are not limited to, field programmable gate arrays (FPGAs) and digital signal processors (DSPs).

<FIG> depicts a block diagram of a system for measuring voltages according to one or more embodiments. The system <NUM> includes an intelligence engine <NUM>. In one or more embodiments, the intelligence engine <NUM> can be an FPGA, microcontroller, or DSP, for example. In one or more embodiments, the intelligence engine <NUM> is configured to execute an AC peak voltage computation algorithm <NUM> which calculates an AC peak voltage of a scaled AC input voltage <NUM>. To achieve this calculation, the intelligence engine <NUM> utilizes the remaining components of the system <NUM> that includes a comparator <NUM>, two digital isolation circuits <NUM>, a clock <NUM>, a buffer <NUM>, and an RC circuit <NUM>.

In one or more embodiments, an AC input voltage can be received from a component on an aircraft, for example, that requires an AC voltage to be measured. The AC input voltage is scaled <NUM> before being input into the comparator <NUM>. The comparator <NUM> compares the scaled AC input voltage <NUM> to a reference voltage (Vref) <NUM> which is a pulse width modulation (PWM) reference voltage <NUM> from the intelligence engine <NUM> after travelling through the digital isolation circuit <NUM>, the buffer <NUM>, and the RC circuit <NUM>. The comparator <NUM> converts the scaled AC input voltage <NUM> into a digital PWM signal. The digital PWM signal is fed into the intelligence engine <NUM> through another digital isolation circuit <NUM> for further computation.

In one or more embodiments, the intelligence engine <NUM> can execute the AC peak voltage computation algorithm <NUM> which is described in further detail with reference to <FIG> depicts voltage graphs at various locations in the voltage measurement system according to one or more embodiments. The first graph <NUM> shows the scaled AC input voltage (<NUM> from <FIG>) which is an input to the comparator (<NUM> from <FIG>). The second graph <NUM> shows the Vref duty cycle (<NUM> from <FIG>) which is supplied from the intelligence engine (<NUM> from <FIG>). The third graph <NUM> is the reference voltage (<NUM> from <FIG>) which is an input to the comparator (<NUM> from <FIG>). The fourth graph <NUM> shows the timing input into the intelligence engine (labeled as FPGA here). In one or more embodiments, during power ON, the intelligence sets the Vref PWM to <NUM>% which results in the Vref being 0V inputted into the comparator <NUM>. The third graph <NUM> shows the Vref as broken out into two parts showing a Vref1 and Vref2. Vref1 set at 0V in the third graph <NUM> gets compared to the scaled AC input voltage shown in the first graph <NUM>. This results in the output of the comparator shown in the fourth graph <NUM> which is a pulse width shown as T1. This pulse width results because the comparator is comparing the positive input voltage from graph one <NUM> to the 0V reference voltage in graph three <NUM> resulting in a high output from the comparator. In one or more embodiments, the intelligence engine <NUM> can calculate the line frequency F as this corresponds to a zero crossing of the input AC voltage. The line frequency equation is shown below as equation [<NUM>].

The output of the comparator shown in the fourth graph <NUM> shows the determination of frequency of the AC input voltage because for a rising edge and falling edge comparison, a width of half the duty cycle of the input voltage is shown. Hence, doubling the pulse width T1 and taking the inverse will result in the frequency. After the falling edge of the first pulse width T1, the Vref PWM duty cycle is set to an initial duty cycle %. As the Vref PWM signal travels through the buffer <NUM> and RC circuit <NUM>, there is a charge up period as shown in graph three <NUM> and depicted as Vref2. Vref2 is high during the negative half cycle of the AC input voltage. As the positive half cycle of the AC input voltage begins, the comparator output provides a new pulse width T2 which is lesser than the first pulse width T1. The difference in the two pulse widths (ΔT) can be utilized for determining the input AC voltage peak by using equations <NUM> & <NUM> below. <MAT> <MAT>.

The AC Voltage peak value is calculated from equation [<NUM>] where the Vref2 from graph three <NUM> is known and the ΔT is calculated as the difference between the first pulse width T1 and the second pulse width T2.

All the components used in this approach are COTs parts as they are easier to get in extended operating temperature range. Replacing the ADC with comparator from the demodulation approach eases the verification and certification aspects.

<FIG> depicts a flow diagram of a method for determining an AC voltage peak according to one or more embodiments. The method <NUM> includes providing, by a processor, a reference voltage signal to a negative input of a comparator, wherein a positive input of the comparator receives an input voltage, as shown in block <NUM>. At block <NUM>, the method <NUM> includes setting, by the processor, the reference voltage signal to a zero voltage signal. Also, the method <NUM> includes determining, by the processor, a line frequency of the input voltage based on a timing signal from the output of the comparator and determining a first pulse width of the input signal based on the timing signal, as shown at block <NUM>. And, at block <NUM>, the method <NUM> includes setting, by the processor, the reference voltage to a pulse width modification signal with a first duty cycle. Also, the method <NUM>, at block <NUM>, includes receiving the timing signal from the output of the comparator. The method <NUM> includes determining a rising edge and a falling edge associated with the input voltage based on the timing signal, as shown at block <NUM>. And at block <NUM>, the method <NUM> includes determining a peak value of the input voltage based on a second pulse width between the rising edge and falling edge of the input voltage. The method at block <NUM> include setting the reference voltage to zero volts thus resulting in a <NUM>% duty cycle. The <NUM>% duty cycle then resets this method <NUM> for the reference voltage.

Claim 1:
A voltage measurement system (<NUM>) comprising:
a comparator (<NUM>) having a positive input terminal and a negative input terminal;
a processor (<NUM>) configured to:
supply a reference voltage signal (<NUM>) to the negative input terminal of the comparator, wherein the positive input terminal of the comparator receives an input voltage (<NUM>);
setting the reference voltage signal (<NUM>) to a zero voltage signal;
determine a line frequency of the input voltage based on a timing signal from an output of the comparator and determining a first pulse width of the input signal based on the timing signal;
set the reference voltage (<NUM>) to a pulse width modulation signal with
a fixed duty cycle (<NUM>);
receive the timing signal from the output of the comparator;
determine a rising edge and a falling edge associated with the input voltage based on the timing signal; and
determine a peak value of the input voltage based on a second pulse width between the rising edge and falling edge of the input voltage.