Patent Description:
Conventionally, there is an image sensor that performs global shutter type imaging in which all pixels simultaneously transfer charges from a photodiode (PD) to a floating diffusion (FD).

Normally, it is known that kTC noise is generated at reset when driving an image sensor.

On the other hand, for example, Patent Document <NUM> discloses an image sensor that performs a global shutter type imaging including a charge holding unit different from the FD and feeding a signal potential including the kTC noise back to the FD to reduce the kTC noise. Further solid-state imaging elements are known from <CIT> and <CIT>.

In the configuration of Patent Document <NUM>, since the kTC noise is reduced by the capacitance distribution of the coupling capacitance between the charge holding unit and the FD, it is necessary to increase the capacitance of the charge holding unit, but Patent Document <NUM> does not disclose any specific configuration for increasing the capacitance of the charge holding unit.

The present disclosure has been made in view of such a situation, and is intended to increase the capacitance of the charge holding unit.

The above objects are achieved by the claimed matter according to the independent claims.

The solid-state imaging element of the present disclosure is a solid-state imaging element including: a pixel including a photodiode, an FD that accumulates charges generated in the photodiode, and a charge holding unit that is connected in parallel with the FD, in which the charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential.

The electronic device of the present disclosure is an electronic device including: a solid-state imaging element including a pixel including a photodiode, an FD that accumulates charges generated in the photodiode, and
a charge holding unit that is connected in parallel with the FD, in which the charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential.

According to the present disclosure, a pixel includes a photodiode, an FD that accumulates charges generated in the photodiode, and a charge holding unit that is connected in parallel with the FD, in which the charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential.

Modes for carrying out the present disclosure (hereinafter, the embodiments) are described below. Note that description will be presented in the following order.

<FIG> is a diagram showing a configuration example of a solid-state imaging element <NUM> to which the technology according to the present disclosure is applied.

The solid-state imaging element <NUM> includes a pixel array unit <NUM>, a vertical drive unit <NUM>, a column signal processing unit <NUM>, a standard signal supply unit <NUM>, and a reference signal generation unit <NUM>.

The pixel array unit <NUM> generates an image signal according to incident light. The pixel array unit <NUM> includes pixels <NUM> having a photoelectric conversion unit in a two-dimensional matrix.

In the pixel array unit <NUM>, a control line <NUM> for transmitting a control signal to the pixel <NUM> and a vertical signal line <NUM> for transmitting an image signal generated by the pixel <NUM> are wired in an X-Y matrix.

The control line <NUM> is wired for each row of a plurality of pixels <NUM>. The control line <NUM> is commonly wired to the pixels <NUM> arranged in one row. That is, control signals different with respect to each row are input to the pixels <NUM>, and a common control signal is input to the pixels <NUM> arranged in one row.

On the other hand, the vertical signal line <NUM> is wired for each column of the plurality of pixels <NUM>. The vertical signal line <NUM> is commonly wired to the pixels <NUM> arranged in one column. That is, an image signal of the pixels <NUM> arranged in one column is transmitted via the common vertical signal line <NUM>.

The vertical drive unit <NUM> generates a control signal and outputs it to the pixel array unit <NUM> via the control line <NUM>.

The column signal processing unit <NUM> processes the image signal output from the pixel array unit <NUM>. The image signal processed by the column signal processing unit <NUM> corresponds to an output signal of the solid-state imaging element <NUM>, and is output to the outside of the solid-state imaging element <NUM>.

The standard signal supply unit <NUM> generates a standard signal. The standard signal is a signal that serves as a standard of the image signal generated by the pixel <NUM>, and is, for example, a signal having a voltage corresponding to a black level image signal. The generated standard signal is supplied to the column signal processing unit <NUM> via a standard signal line <NUM>.

The reference signal generation unit <NUM> generates a reference signal. The reference signal is a signal serving as a standard for analog-to-digital conversion of the image signal generated by the pixel <NUM>. As the reference signal, for example, a signal whose voltage drops like a lamp can be adopted. The generated reference signal is output to the column signal processing unit <NUM> via a reference signal line <NUM>.

<FIG> is a diagram showing a configuration example of the pixel <NUM> to which the technology described above according to the present disclosure is applied.

The pixel <NUM> includes a photodiode (PD) <NUM>, a transfer transistor <NUM>, a floating diffusion (FD) <NUM>, a reset transistor <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM>.

A MOS transistor can be used for each pixel transistor: the transfer transistor <NUM>, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM>.

The control line <NUM> and the vertical signal line <NUM> described above are wired to the pixel <NUM>. Among the above, the control line <NUM> includes a control line transfer gate (TRG), a control line reset (RST), and a control line select (SEL). These control lines are connected to the gate of the MOS transistor and transmit the control signal described in <FIG>. When a voltage equal to or higher than a threshold voltage between the gate and the source of the MOS transistor is input to these control lines, the corresponding MOS transistor becomes conductive.

The control line TRG transmits a signal for controlling on/off of the transfer transistor <NUM>. The control line RST transmits a signal for controlling the reset of the FD <NUM>. The control line SEL transmits a signal for selecting the pixel <NUM>.

Moreover, a power line Vdd is wired to the pixel <NUM>. The power line Vdd supplies power with positive polarity.

The anode of the PD <NUM> is grounded and the cathode is connected to the source of the transfer transistor <NUM>. The gate of the transfer transistor <NUM> is connected to the control line TRG, and the drain is connected to one end of the FD <NUM>, the gate of the amplification transistor <NUM>, and the source of the reset transistor <NUM>. Another end of the FD <NUM> is grounded.

The drain of the reset transistor <NUM> is connected to the power line Vdd and the gate is connected to the control line RST. The drain of the amplification transistor <NUM> is connected to the power line Vdd and the source is connected to the drain of the selection transistor <NUM>. The gate of the selection transistor <NUM> is connected to the control line SEL and the source is connected to the vertical signal line <NUM>.

The PD <NUM> generates a charge according to the emitted incident light by photoelectric conversion.

The transfer transistor <NUM> transfers the charge generated by the PD <NUM> to the FD <NUM>. The transfer transistor <NUM> transfers the charge by causing the PD <NUM> and the FD <NUM> to be conductive.

The FD <NUM> accumulates the charge generated in the PD <NUM>. The FD <NUM> is formed in a diffusion layer of a semiconductor substrate such as a Si substrate and the like.

The reset transistor <NUM> resets the charge accumulated in the FD <NUM>. The reset transistor <NUM> applies a power voltage to the FD <NUM> by conducting the power line Vdd and the FD <NUM>, and resets the FD <NUM>.

The amplification transistor <NUM> detects a signal corresponding to the charge held in the FD <NUM> as a pixel signal.

The selection transistor <NUM> outputs the image signal detected by the amplification transistor <NUM>. The selection transistor <NUM> outputs an image signal by causing the amplification transistor <NUM> and the vertical signal line <NUM> to be conductive.

With the above configuration, the FD <NUM> is reset and the charge is transferred from the PD <NUM> to the FD <NUM> at the same time for all pixels. That is, the solid-state imaging element <NUM> can perform global shutter type imaging.

The pixel <NUM> further includes charge holding units <NUM>, <NUM>.

The charge holding units <NUM>, <NUM> are electrically connected in parallel with the FD <NUM> and accumulate charges generated in the PD <NUM> apart from the FD <NUM>.

One end of the charge holding unit <NUM> is connected to the drain of the transfer transistor <NUM>, the gate of the amplification transistor <NUM>, and the source of the reset transistor <NUM>, and another end is connected to a node A having a predetermined potential. Furthermore, one end of the charge holding unit <NUM> is connected to the node A, and another end is grounded.

Here, the charge holding units <NUM>, <NUM> can be formed by the wiring capacitance.

<FIG> is a plan view showing an example of a wiring layout for forming the charge holding units <NUM>, <NUM>.

<FIG> shows the layout of a part of each of a wiring <NUM> connected to the node A, a FD wiring <NUM> connecting the drain of the transfer transistor <NUM> and the gate of the amplification transistor <NUM>, and a fixed potential line <NUM> connected to the fixed potential Vss different from the node A. Here, the fixed potential Vss is assumed to be a ground potential (GND).

As shown in <FIG>, the wiring <NUM>, the FD wiring <NUM>, and the fixed potential line <NUM> are laid out side by side so as to extend in the same direction (right-and-left direction in the drawing). In the following, the fact that wirings X, Y are laid out side by side means that the wirings X, Y run in parallel.

In the example of <FIG>, the wiring <NUM> and the FD wiring <NUM> run in parallel to form the charge holding unit <NUM>, and the wiring <NUM> and the fixed potential line <NUM> run in parallel to form the charge holding unit <NUM>.

With such a wiring layout, it is possible to increase the capacitance of the charge holding units <NUM>, <NUM>.

Note that, in the example of <FIG>, the wiring <NUM>, the FD wiring <NUM>, and the fixed potential line <NUM> have only a straight portion extending in one direction (hereinafter referred to as an extending portion), and have a portion bending or branching in a predetermined direction (hereinafter referred to as a bent portion). The bent portion can be formed in any of an L-shape, a T-shape, a U-shape, and a cross shape.

In this case, the two wirings may run in parallel, for example, such that the bent portion of each of the two wirings is bent in the same direction or the bent portion of another wiring is bent so as to surround at least a part of one wiring.

<FIG> is a diagram showing a configuration example of a pixel <NUM> according to the first embodiment of the present disclosure.

The pixel <NUM> of <FIG> differs from the pixel <NUM> of <FIG> in that it includes a feedback transistor <NUM>.

A MOS transistor can be used as the feedback transistor <NUM>.

A control line feedback (FB) is further wired as a control line <NUM> to the pixel <NUM> of <FIG>. The control line FB transmits a signal for controlling the supply of a reset voltage. The reset voltage is a voltage input to the pixel <NUM> when the pixel <NUM> is reset.

The source of the feedback transistor <NUM> is connected to the drain of the reset transistor <NUM> and the node <NUM> at a predetermined potential. The drain of the feedback transistor <NUM> is connected to the column signal processing unit <NUM>, and the gate is connected to the control line FB.

A node <NUM> corresponds to the node A of the pixel <NUM> of <FIG>. Furthermore, in the pixel <NUM> of <FIG>, charge holding units <NUM>, <NUM> corresponding to the charge holding units <NUM>, <NUM> of the pixel <NUM> of <FIG> are formed.

The feedback transistor <NUM> causes the charge holding unit <NUM> to hold the reset voltage output from the column signal processing unit <NUM>.

The charge holding unit <NUM> holds the reset voltage output from the feedback transistor <NUM>.

In the example of <FIG>, the reset transistor <NUM> applies a reset voltage to the FD <NUM> by conducting the charge holding unit <NUM> and the FD <NUM>, and resets the FD <NUM>.

The charge holding unit <NUM> transmits the reset voltage held by the charge holding unit <NUM> to the FD <NUM>.

Normally, the kTC noise remains in the FD <NUM> at the time of reset. The kTC noise is noise caused by the operation of the reset transistor <NUM>, and is generated when the reset transistor <NUM> shifts from the conductive state to the nonconductive state. Then, a part of it remains in the FD <NUM>. It is known that the kTC noise can be reduced by reducing the electrostatic capacitance of the FD <NUM>.

In the pixel <NUM> of <FIG>, the charge holding units <NUM>, <NUM> are connected in parallel with the FD <NUM>, and the capacitance of the FD <NUM> is distributed to the charge holding units <NUM>, <NUM>. Therefore, the kTC noise can be reduced.

Therefore, in the pixel <NUM> of <FIG>, it is necessary to increase the capacitance of the charge holding units <NUM>, <NUM> in order to reduce the kTC noise. Thus, with the pixel <NUM> of the present embodiment, the capacitance of the charge holding units <NUM>, <NUM> is increased by the wiring layout.

<FIG> are plan views showing an example of the wiring layout of the wiring layers of the first layer to the fourth layer corresponding to the pixel <NUM> of <FIG>.

<FIG> shows the wiring layout of a wiring layer M1 of the first layer directly above the Si substrate on which the PD <NUM> and each pixel transistor are formed.

The PD <NUM> is arranged substantially in the center of the Si substrate shown in <FIG>, and the transfer transistor <NUM> is formed in the upper left part thereof. The amplification transistor <NUM> and the selection transistor <NUM> are formed side by side above the transfer transistor <NUM> in the drawing. The reset transistor <NUM> and the feedback transistor <NUM> are formed side by side on the upper right side of the PD <NUM> in the drawing.

Note that the reset transistor <NUM> and the feedback transistor <NUM> are pixel transistors constituting a pixel <NUM> corresponding to a PD <NUM>, which is not shown, which is adjacent to the right side of the PD <NUM> shown in <FIG>. Therefore, a reset transistor <NUM> and a feedback transistor <NUM> constituting the pixel <NUM> corresponding to the PD <NUM> shown in <FIG> are formed on the left side of the PD <NUM>, which is not shown.

In <FIG>, the wiring pattern of the wiring layer M1 is shown as a diagonal grid pattern.

A FD wiring <NUM>-<NUM> connecting the transfer transistor <NUM> and the amplification transistor <NUM> is formed in the wiring layer M1. In the wiring layer M1, directly above the PD <NUM>, a large area pattern <NUM> for improving the sensitivity of the PD <NUM> by reflection of incident light is formed.

Furthermore, in the wiring layer M1, on the left side of the FD wiring <NUM>-<NUM> in the drawing, a control line <NUM>-<NUM> for supplying a control signal to the gate of the transfer transistor <NUM> is formed.

The control line <NUM>-<NUM> is formed so that the extending portion and the bent portion, which are a part of the control line <NUM>-<NUM>, run in parallel with the FD wiring <NUM>-<NUM>.

Moreover, in the wiring layer M1, at a position sandwiched between the reset transistor <NUM> and the feedback transistor <NUM>, a wiring <NUM>-<NUM> for transmitting the potential of the node <NUM> to the wiring layer above the second layer is formed.

<FIG> shows the wiring layout of the wiring layer M2 of the second layer.

In <FIG>, the wiring pattern of the wiring layer M2 is shown as a dot pattern.

In the wiring layer M2, a wiring <NUM>-<NUM> that is electrically connected to the wiring <NUM>-<NUM> through a via is formed from the position corresponding to the wiring <NUM>-<NUM> of the wiring layer M1. The wiring <NUM>-<NUM> is generally formed in an L shape.

In the wiring layer M2, a fixed potential line <NUM>-2a connected to a fixed potential Vss (GND) is formed above the wiring <NUM>-<NUM> in the drawing. The fixed potential line <NUM>-2a is formed by combining an extending portion and a plurality of L-shaped, T-shaped, and U-shaped bent portions along the upper side of the wiring <NUM>-<NUM> in the drawing.

The fixed potential line <NUM>-2a is formed so that the extending portion and the bent portion, which are a part of the fixed potential line <NUM>-2a, run in parallel with the wiring <NUM>-<NUM>. Therefore, the wiring capacitance is formed between the wiring <NUM>-<NUM> connected to the node <NUM> and the fixed potential line <NUM>-2a connected to GND.

In the wiring layer M2, an FD wiring <NUM>-<NUM> electrically connected to the FD wiring <NUM>-<NUM> of the wiring layer M1 through a via is formed below the wiring <NUM>-<NUM> in the drawing. The FD wiring <NUM>-<NUM> is formed by combining an extending portion and a plurality of L-shaped, T-shaped, and U-shaped bent portions.

The FD wiring <NUM>-<NUM> is formed so that the extending portion, which is a part of the FD wiring <NUM>-<NUM>, runs in parallel with the wiring <NUM>-<NUM>. Therefore, the wiring capacitance (coupling capacitance with the FD <NUM>) is formed between the wiring <NUM>-<NUM> connected to the node <NUM> and the FD wiring <NUM>-<NUM> connected to the FD <NUM>. Note that, in the example of <FIG>, the wiring <NUM>-<NUM> and the FD wiring <NUM>-<NUM> are wirings corresponding to a pixel <NUM>, which is not shown, adjacent to the right side of the pixel <NUM> shown in <FIG>.

In this way, by the wiring capacitance formed by the wiring <NUM>-<NUM>, the fixed potential line <NUM>-2a, and the FD wiring <NUM>-<NUM> running in parallel in the wiring layer M2, a high capacitance of the charge holding units <NUM>, <NUM> can be realized, and eventually the kTC noise can be reduced.

Furthermore, in the wiring layer M2, a fixed potential line <NUM>-2b connected to the fixed potential Vss is formed below the FD wiring <NUM>-<NUM> in the drawing. The fixed potential line <NUM>-2b is formed by combining an extending portion and a plurality of L-shaped and U-shaped bent portions along the left side, the upper side, and the right side of the FD wiring <NUM>-<NUM> in the drawing.

Moreover, in the upper right part of the wiring layer M2 in the drawing, a control line <NUM>-<NUM> that is electrically connected to the control line <NUM>-<NUM> of the wiring layer M1 through a via is formed. The control line <NUM>-<NUM> is generally formed in an L shape.

The FD wiring <NUM>-<NUM> is formed so that the extending portion and the bent portion, which are a part of the FD wiring <NUM>-<NUM>, run in parallel with the fixed potential line <NUM>-2b and the control line <NUM>-<NUM>. Therefore, a wiring capacitance is also formed between the FD wiring <NUM>-<NUM> connected to the FD <NUM> and the fixed potential line <NUM>-2b and the control line <NUM>-<NUM>.

Here, as shown in <FIG>, the wiring <NUM>-<NUM> and the FD wiring <NUM>-<NUM>, which are the signal lines connected to the FD <NUM> and the charge holding units <NUM>, <NUM> that accumulate charges, which become pixel signals, are preferably surrounded by the fixed potential lines <NUM>-2a, <NUM>-2b and the control line <NUM>-<NUM> so as to be shielded from signal lines of adjacent pixels.

<FIG> shows the wiring layout of the wiring layer M3 of the third layer.

In <FIG>, the wiring pattern of the wiring layer M3 is shown as an upward-sloping diagonal pattern. As shown in <FIG>, the wiring pattern of the wiring layer M3 is mainly formed so as to extend in the right-and-left direction in the drawing.

In the wiring layer M3, a wiring <NUM>-3a that is electrically connected to the wiring <NUM>-<NUM> of the wiring layer M2 through a via is formed at the position corresponding to the substantially left half of the PD <NUM>. The wiring <NUM>-3a is formed by combining an extending portion and a plurality of T-shaped and cross-shaped bent portions.

Similarly, in the wiring layer M3, a wiring <NUM>-3b that is electrically connected to the wiring <NUM>-<NUM> of the wiring layer M2 through a via is formed at the position corresponding to the substantially right half of the PD <NUM>. The wiring <NUM>-3b is formed by combining an extending portion and a plurality of L-shaped, T-shaped, and U-shaped bent portions.

Furthermore, in the wiring layer M3, a fixed potential line <NUM>-<NUM> connected to the fixed potential Vss is formed. The fixed potential line <NUM>-<NUM> is formed by combining an extending portion and a plurality of L-shaped, T-shaped, and cross-shaped bent portions so as to surround each of the four sides of the wiring <NUM>-3a, <NUM>-3b.

In particular, the wirings <NUM>-3a, <NUM>-3b and the fixed potential line <NUM>-<NUM> are formed in a comb shape in which a part thereof faces each other.

Moreover, in the wiring layer M3, above the wirings <NUM>-3a, <NUM>-3b and the fixed potential line <NUM>-<NUM> in the drawing, a control line <NUM>-<NUM> that is electrically connected to the control line <NUM>-<NUM> of the wiring layer M2 through a via is formed. The control line <NUM>-<NUM> is formed in a straight line extending in the right-and-left direction in the drawing.

As described above, also in the wiring layer M3, the fixed potential line <NUM>-<NUM> is formed so that the extending portion and the bent portion, which are a part of the fixed potential line <NUM>-<NUM>, run in parallel with the wirings <NUM>-3a, <NUM>-3b. Therefore, the wiring capacitance is formed between the wirings <NUM>-3a, <NUM>-3b connected to the node <NUM> and the fixed potential line <NUM>-<NUM> connected to GND.

Also here, as shown in <FIG>, the wirings <NUM>-3a, <NUM>-3b, which are the signal lines connected to the charge holding units <NUM>, <NUM> that accumulate charges, which become pixel signals, are preferably surrounded by the fixed potential line <NUM>-<NUM> and the control line <NUM>-<NUM> so as to be shielded from signal lines of adjacent pixels.

<FIG> shows the wiring layout of the wiring layer M4 of the fourth layer.

In <FIG>, the wiring pattern of the wiring layer M4 is shown as a grid pattern.

In the wiring layer M4, fixed potential lines <NUM>-<NUM> connected to the fixed potential Vss are formed as a plurality of shielded wirings. A plurality of shielded fixed potential lines <NUM>-<NUM> is formed side by side in the right-and-left direction so as to extend in a straight line in the up-and-down direction in the drawing. Therefore, crosstalk between the signal lines connected to the FD <NUM> and the charge holding units <NUM>, <NUM> that accumulate charges, which become pixel signals, is suppressed.

Note that the pixel <NUM> includes the configuration in which a wiring capacitance is formed by wirings running in parallel in the same wiring layer, and also includes the configuration in which a wiring capacitance is formed between different wiring layers.

<FIG> is a diagram showing an example of a cross section of a wiring layer of the pixel <NUM>.

<FIG> shows cross sections of a Si substrate <NUM> and wirings in the wiring layers M1 to M3.

On the Si substrate <NUM>, an N-type diffusion layer <NUM> serving as the node <NUM> is formed within a large P-type diffusion layer formed. The diffusion layer <NUM> formed on the Si substrate <NUM> and the wiring <NUM>-<NUM> of the wiring layer M1 are connected by a contact <NUM>. Furthermore, the wiring <NUM>-<NUM> of the wiring layer M1 and the wiring <NUM>-<NUM> of the wiring layer M2 are connected by a via <NUM>.

In the example of <FIG>, within the wiring layer M2, the wiring <NUM>-<NUM> having a predetermined potential, the fixed potential line <NUM>-<NUM>, and the FD wiring <NUM>-<NUM> run in parallel. Furthermore, within the wiring layer M3, the wiring <NUM>-<NUM> having a predetermined potential and the fixed potential line <NUM>-<NUM> run in parallel.

Moreover, in the example of <FIG>, between the wiring layer M2 and the wiring layer M3, the wiring <NUM>-<NUM> having a predetermined potential and the fixed potential line <NUM>-<NUM> run in parallel, and the fixed potential line <NUM>-<NUM> and the wiring <NUM>-<NUM> having a predetermined potential run in parallel.

As described above, in the pixel <NUM> of the present embodiment, the wiring capacitance is formed by running the wirings in parallel not only within the same wiring layer but also between different wiring layers.

According to the above configuration, the high capacitance of the charge holding unit connected in parallel with the FD can be realized by the wiring capacitance formed by the wiring connected to the node having a predetermined voltage, the fixed potential line, and the FD wiring running in parallel, and eventually the kTC noise can be reduced.

Note that it is desirable that the wiring patterns of the wiring layers M1 to M4 described above are formed in the same wiring layout for all the pixels <NUM>. Therefore, the sensitivity non-uniformity between the pixels <NUM> can be reduced.

In a solid-state imaging element that performs global shutter type imaging, a read circuit cannot be shared between pixels. Therefore, it has been necessary to reduce the voltage amplitude of the pixel signal so that the pixel signal can be received in the subsequent circuit. For that purpose, it has been necessary to intentionally lower the conversion efficiency by increasing the capacitance of the FD.

However, when the pixel size becomes small, the FD wiring routing area becomes narrow, so that it becomes difficult to increase the FD capacitance, and it becomes difficult to realize the intended conversion efficiency.

On the other hand, in order to increase the quantum efficiency of the PD formed on the Si substrate in a case where the wavelength to be captured is a long wavelength, in the above-described embodiment, as described with reference to <FIG>, the large area pattern <NUM> for improving the sensitivity of PD by the reflection of incident light is formed directly above the PD.

In the present embodiment, instead of the large area pattern, wirings running in parallel are formed directly above the PD.

<FIG> is a plan view showing another example of the wiring layout of the wiring layer M1 of the first layer corresponding to the pixel <NUM>.

In the example of <FIG>, in the wiring layer M1, the wiring <NUM>-<NUM> having a predetermined potential, the FD wiring <NUM>-<NUM>, and the fixed potential line <NUM>-<NUM> are formed directly above the PD <NUM>.

Directly above the PD <NUM>, the wiring <NUM>-<NUM> having a comb shape and a part of the FD wiring <NUM>-<NUM> having an L-shape are formed to run in parallel, and the fixed potential line <NUM>-<NUM> having a comb shape is formed to surround the wiring <NUM>-<NUM> and the FD wiring <NUM>-<NUM>. In particular, the wiring <NUM>-<NUM> and the fixed potential line <NUM>-<NUM> are formed so that the comb-shaped portions face each other.

The wiring <NUM>-<NUM>, the FD wiring <NUM>-<NUM>, and the fixed potential line <NUM>-<NUM> directly above the PD <NUM> are formed so that the L/S (line width of the pattern and the distance between the patterns) becomes narrower than the wavelength to be captured.

With such a configuration, even in a case where the pixel size is small, it is possible to improve the sensitivity of the PD by reflection of incident light and increase the capacitance of the FD and the charge holding unit.

Note that, also in the example of <FIG>, it is desirable that the wiring pattern of the wiring layer M1 is formed in the same wiring layout for all the pixels <NUM>. Therefore, the sensitivity non-uniformity between the pixels <NUM> can be reduced.

<FIG> is a diagram showing another example of the cross section of the wiring layer of the pixel <NUM>.

In the example of <FIG>, a high-k film <NUM> having a high dielectric constant is provided as an insulating film between the wirings forming the wiring capacitance in the wiring layers M2, M3.

Therefore, it is possible to increase the wiring capacitance formed by the wirings running in parallel.

Note that, by not using a high-k film as an insulating film for a wiring layer (for example, wiring layer M4) in which wirings running in parallel are not formed (where it is not necessary to form a wiring capacitance), an unintended increase in wiring capacitance can be suppressed.

<FIG> is a diagram showing still another example of the cross section of the wiring layer of the pixel <NUM>.

In the example of <FIG>, a diffusion layer <NUM>' is formed on the Si substrate <NUM> instead of the diffusion layer <NUM>. The diffusion layer <NUM>' is formed to have a larger area than the diffusion layer <NUM> forming the pixel transistor.

Moreover, the diffusion layer <NUM>' may be formed by implanting ions having a concentration higher than that of the diffusion layer <NUM> forming the pixel transistor.

Therefore, it is possible to increase the capacitance of the charge holding unit with a configuration other than running the wirings in parallel.

<FIG> is a diagram explaining removal of kTC noise in the pixel <NUM> that performs the global shutter operation.

First, as shown in A of <FIG>, when the reset transistor (RST) is turned on, the potential of the FD is reset.

Next, as shown in B of <FIG>, when the reset transistor (RST) is turned off, kTC noise (ΔVkTC) remains in the FD.

Thereafter, as shown in C of <FIG>, when the feedback transistor (FB) is turned on, the potential of the FD and the standard signal are balanced, and the kTC noise remaining in the FD is removed.

Moreover, as shown in D of <FIG>, when the feedback transistor (FB) is turned off, kTC noise (ΔV) remains in the FD again. However, the kTC noise is reduced by the capacitance distribution of the coupling capacitance between capacitance CFB of the charge holding unit and the capacitance of the FD.

Although the kTC noise at the time of reset can be reduced by the above operation, the potential of the FD becomes shallower than that of a normal pixel, and a transfer failure occurs.

Therefore, in the wiring layer M1 of <FIG>, the FD wiring <NUM>-<NUM> and the control line <NUM>-<NUM> that supplies the control signal to the gate of the transfer transistor <NUM> are formed to run in parallel.

Furthermore, in the wiring layer M2 of <FIG>, the FD wiring <NUM>-<NUM> and the control line <NUM>-<NUM> connected to the control line <NUM>-<NUM> are formed to run in parallel.

Therefore, when the transfer transistor <NUM> is turned on, the potential of the FD can be boosted by the coupling, and the transfer failure due to the potential of the FD being shallower can be improved.

<FIG> is a plan view showing an example of the wiring layout of adjacent wiring layers.

On the left side in <FIG>, a wiring <NUM>-N having a predetermined potential and a fixed potential line <NUM>-N are shown as wirings formed in the wiring layer of the Nth layer.

The wiring <NUM>-N is formed in a comb shape extending in the right-and-left direction in the drawing, and the fixed potential line <NUM>-N is formed to have a comb-shaped portion facing the wiring <NUM>-N and surround the wiring <NUM>-N.

On the right side in <FIG>, a wiring <NUM>-M having a predetermined potential and a fixed potential line <NUM>-M are shown as wirings formed in the wiring layer of the N+1th or N-1th layer adjacent to the wiring layer of the Nth layer.

The wiring <NUM>-M is formed in a comb shape extending in the up-and-down direction in the drawing, and the fixed potential line <NUM>-M is formed to have a comb-shaped portion facing the wiring <NUM>-M and surround the wiring <NUM>-M.

That is, the extension directions of the wiring <NUM>-N and the fixed potential line <NUM>-N of the wiring layer of the Nth layer and the wiring <NUM>-M and the fixed potential line <NUM>-M of the wiring layer of the N+1th or N-1th layer are perpendicular.

For example, in a case where the extension directions of the wirings running in parallel are set to be the same direction between adjacent wiring layers, the capacitance fluctuation in wiring capacitance formed by the wirings between the wiring layers becomes large when the wiring layout varies due to process variations.

On the other hand, as shown in <FIG>, by making the extension directions of the wirings running in parallel perpendicular between the adjacent wiring layers, it is possible to reduce the capacitance fluctuation when the wiring layout varies due to process variations.

<FIG> is a diagram showing still another example of the cross section of the wiring layer of the pixel <NUM>. Furthermore, <FIG> is a plan view showing an example of the wiring layout of the wiring layer of <FIG>.

In the examples of <FIG> and <FIG>, the wiring <NUM>-<NUM>, the fixed potential line <NUM>-<NUM>, and the like running in parallel are formed, and a solid wiring <NUM> is formed in the wiring layer M3, which is a layer above the wiring layer M2. Moreover, a solid wiring <NUM> connected to the fixed potential Vss is formed in the wiring layer M4, which is a layer above the wiring layer M3.

Therefore, in addition to increasing the capacitance of the charge holding unit, it is possible to improve the sensitivity of the PD by reflection of incident light with the solid wiring.

<FIG> is a diagram showing another configuration example of the pixel <NUM>.

The pixel <NUM> of <FIG> is different from the pixel <NUM> of <FIG> in that it includes a conversion efficiency switching switch <NUM> and a capacitance <NUM> instead of the charge holding units <NUM>, <NUM>.

A MOS transistor can be used for the conversion efficiency switching switch <NUM>.

One end of the conversion efficiency switching switch <NUM> is connected to the drain of the transfer transistor <NUM>, the gate of the amplification transistor <NUM>, and the source of the reset transistor <NUM>, and another end is connected to a node <NUM> having a predetermined potential.

The conversion efficiency switching switch <NUM> functions as a switch for switching the conversion efficiency. Furthermore, the capacitance <NUM> is formed by the wiring capacitance.

The additional capacitance of the FD <NUM> is enabled or disabled by turning the conversion efficiency switching switch <NUM> on or off. In a case where the conversion efficiency switching switch <NUM> is turned on, the additional capacitance including the capacitance of the conversion efficiency switching switch <NUM> itself, the diffusion capacitance, and the wiring capacitance (capacitance <NUM>) becomes enabled. On the contrary, in a case where the conversion efficiency switching switch <NUM> is turned off, the additional capacitance becomes disabled.

The wiring layout according to the technology of the present disclosure can also be applied to the pixel <NUM> shown in <FIG>. Therefore, it becomes possible to increase the capacitance of the capacitance <NUM>.

For example, the aforementioned solid-state imaging element <NUM> can be applied to various types of electronic device including an imaging system, e.g., a digital still camera or a digital video camera, a mobile phone with an imaging function, and other device with an imaging function.

<FIG> is a block diagram showing a configuration example of an imaging apparatus, which is an electronic device to which the present disclosure has been applied.

As shown in <FIG>, an imaging apparatus <NUM> includes an optical system <NUM>, a solid-state imaging element <NUM>, and a digital signal processor (DSP) <NUM>, and the DSP <NUM>, a display apparatus <NUM>, an operation system <NUM>, a memory <NUM>, a recording apparatus <NUM>, and a power system <NUM> are connected via a bus <NUM>, enabling capturing of still images and moving images.

The optical system <NUM> includes one or a plurality of lenses and guides imaging light (incident light) from an object to the solid-state imaging element <NUM> to form an image on the light receiving surface (sensor unit) of the solid-state imaging element <NUM>.

As the solid-state imaging element <NUM>, a solid-state imaging element <NUM> having pixels <NUM> of any of the above-described configuration examples is applied. Electrons are accumulated in the solid-state imaging element <NUM> for a certain period of time according to the image formed on the light receiving surface through the optical system <NUM>. Then, a signal corresponding to the electrons accumulated in the solid-state imaging element <NUM> is supplied to the DSP <NUM>.

The DSP <NUM> performs various signal processing on the signal from the solid-state imaging element <NUM> to acquire an image and causes the memory <NUM> to temporarily store the data of the image. The data of the image stored in the memory <NUM> is recorded in the recording apparatus <NUM> or supplied to and displayed on the display apparatus <NUM>. Furthermore, the operation system <NUM> receives various operations by the user and supplies an operation signal to each block of the imaging apparatus <NUM>, and the power system <NUM> supplies the electric power required for driving each block of the imaging apparatus <NUM>.

Claim 1:
A solid-state imaging element (<NUM>) comprising:
a pixel (<NUM>) including
a photodiode (<NUM>),
an FD (<NUM>) that accumulates charges generated in the photodiode (<NUM>), and
a charge holding unit (<NUM>, <NUM>) that is connected in parallel with the FD (<NUM>), wherein
the charge holding unit (<NUM>, <NUM>) includes a wiring capacitance formed by parallel running of a first wiring (<NUM>) connected to a first potential and a second wiring (<NUM>, <NUM>, <NUM>, <NUM>-<NUM>, <NUM>-<NUM>) connected to a second potential different from the first potential, characterised in that, in a plan view,
the first wiring (<NUM>) and the second wiring (<NUM>, <NUM>, <NUM>, <NUM>-<NUM>, <NUM>-<NUM>) have an extending portion extending in one direction and a bent portion bending in a predetermined direction.