Patent Description:
Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and speed in comparison to alternative types of memory.

Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modern memory architectures, and to develop memory array architectures suitable for utilizing such new memory cell configurations.

Document <CIT> discloses a dynamic random access memory comprising a plurality of dummy cells 32b arranged between reference cells 31b and main (data) cells 30b for separating the plate electrode VP of the main cells 30b and the plate electrode VPref of the reference cells 31b. The dummy cells 32b include a plurality of switching transistors controlled by dummy wordlines WLdum and corresponding capacitors.

Some embodiments include memory arrays which include bitlines having a first comparative bitline component and a second comparative bitline component. Data states of memory cells along the bitlines may be ascertained by comparing one or more electrical properties of the first comparative bitline component with electrical properties of the second comparative bitline component, which can omit reference bitlines utilized in other memory configurations (for instance 1T-1C configurations). The memory arrays may include capacitive units interspersed with memory cells, and such capacitive units may be used to reduce or eliminate parasitic capacitance between adjacent bitlines. These and other aspects of the invention are described below with reference to <FIG>.

<FIG> and <FIG> illustrate example memory cells which may be utilized in arrangements comprising first and second comparative bitline components. Specifically, <FIG> illustrates an example configuration having two transistors and <NUM> capacitor (a so-called 2T-1C configuration), and <FIG> illustrates an example configuration having two transistors and <NUM> capacitors (a so-called 2T-2C configuration).

Referring to <FIG>, the example 2T-1C memory cell configuration is schematically illustrated as a memory cell <NUM> according to the prior art. The two transistors are labeled as T1 and T2.

A source/drain region of T1 connects with a first node of the capacitor (CAP), and the other source/drain region of T1 connects with a first comparative bitline component (BL-<NUM>). A gate of T1 connects with a wordline (WL). A source/drain region of T2 connects with a second node of the capacitor (CAP), and the other source/drain region of T2 connects with a second comparative bitline component BL-<NUM>. A gate of T2 connects with the wordline (WL).

The comparative bitline components BL-<NUM> and BL-<NUM> extend to circuitry <NUM> which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell <NUM>.

Referring to <FIG>, the example 2T-2C memory cell configuration is schematically illustrated as a prior art memory cell <NUM>. The two transistors of the memory cell are labeled as T1 and T2, and the two capacitors are labeled as CAP-<NUM> and CAP-<NUM>.

A source/drain region of the first transistor T1 connects with a node of the first capacitor (CAP-<NUM>), and the other source/drain region of T1 connects with a first comparative bitline component (BL-<NUM>). A gate of T1 connects with a wordline (WL). A source/drain region of the second transistor T2 connects with a node of the second capacitor (CAP-<NUM>), and the other source/drain region of T2 connects with a second comparative bitline component BL-<NUM>. A gate of T2 connects with the wordline (WL). Each of the first and second capacitors (CAP-<NUM> and CAP-<NUM>) has a node electrically coupled with a common plate (CP). The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC). In some applications the common plate is at a voltage of about one-half VCC (i.e., about VCC/<NUM>).

The comparative bitline components BL-<NUM> and BL-<NUM> extend to the circuitry <NUM> which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell <NUM>.

The 2T-1C configuration of <FIG> and the 2T-2C configuration of <FIG> may be utilized in DRAM (dynamic random access memory) arrays and/or other types of memory arrays. A region of an example memory array <NUM> is shown in <FIG>.

The memory array <NUM> includes a series of bitlines (BLa-BLd), with the bitlines defining columns of the memory array. The memory array would also comprise a series of wordlines (not shown); with the wordlines defining rows of the memory array. The bitlines (i.e., the columns of the memory array) extend in a first direction along an illustrated axis <NUM>. The wordlines (i.e., the rows of the memory array, which are not shown in <FIG>) would extend in a second direction which intersects the first direction, and in some embodiments may extend in a direction substantially orthogonal to the direction of the bitlines.

Each of the bitlines comprises first and second comparative bitline components. Specifically, the comparative components of bitline BLa are labeled as BL-1a and BL-2a; the comparative components of bitline BLb are labeled as BL-1b and BL-2b; the comparative components of bitline BLc are labeled as BL-1c and BL-2c; and the comparative components of bitline BLd are labeled as BL-1d and BL-2d. The comparative bitline components extend to circuitry <NUM> of the type described above with reference to <FIG> and <FIG>. Such circuitry is not shown in <FIG> in order to simplify the drawing.

Memory cells <NUM> are between the comparative bitline components and along the columns of the memory array <NUM>. The memory cells may comprise any suitable configurations; and in some embodiments may be 2T-1C configurations of the type described in <FIG> or 2T-2C configurations of the type described in <FIG>. Each memory cell may be uniquely addressed by the combination of a bitline and a wordline within the memory array <NUM>.

<FIG> show top and bottom views, respectively, of the bitlines and illustrate problematic parasitic capacitance that may occur during operation of the memory array <NUM>. The parasitic capacitance is diagrammatically illustrated with schematic representations of capacitors <NUM> forming between adjacent bitlines during operation of the memory array. For instance, if bitline BLb is activated during a READ operation, such may problematically lead to parasitic capacitance between the bitline component BL-1b and the adjacent bitline components BL-1a and BL-1c; and/or may problematically lead to parasitic capacitance between the bitline component BL-2b and the adjacent bitline components BL-2a and BL-2c. Similarly, operations associated with other bitlines may lead to similar parasitic capacitance between active bitlines and adjacent bitlines.

The parasitic capacitance becomes increasingly problematic with increasing integration and associated tighter packing of bitlines within a memory array. The parasitic capacitance may problematically impede operability of a memory array by leading to undesired crosstalk between adjacent bitlines, and/or otherwise creating undesired effects, such as noise, during operation of the array. Accordingly, it is desired to alleviate, and preferably prevent, such parasitic capacitance.

<FIG> shows memory array <NUM> of <FIG> containing modifications in accordance with an example embodiment. Specifically, some of the memory cells <NUM> along the bitlines BLa-BLd are replaced with capacitive units <NUM>. Such capacitive units are interspersed with the memory cells along the columns of the memory array, and may be utilized for tailoring electrical properties of the bitlines in order to alleviate or prevent the problematic parasitic capacitance described above with reference to <FIG>. Wordlines (not shown in <FIG>) may extend orthogonally to the bitlines, as described below with reference to <FIG>.

The capacitive units <NUM> of <FIG> may be utilized to adjust voltage or other electrical properties along the bitlines to alleviate parasitic capacitance between adjacent bitlines of the memory array, while still enabling suitable differences to remain between the comparative bitline components of the individual bitlines so that memory states of the memory cells are maintained and may be appropriately ascertained during a READ operation. In some embodiments the capacitive units may be passive and maintained in an "on" (i.e. "powered" or "operative") state whenever power is provided to the memory array. In other embodiments the capacitive units may be selectable so that they are maintained in an operative state only during particular operations. For instance, the capacitive units along a particular bitline may be powered only during activation (i.e. reading) of memory cells, and may be non-powered during writing to the memory cells. It may be advantageous to have the capacitive units along a bitline non-powered during writing of the memory cells associated with the bitline if it is found that the capacitive units otherwise interfere with the writing operation. Alternatively, if it is found that the capacitive units do not interfere with the writing operation when the capacitive units are powered, it may be advantageous to have the capacitive units throughout a memory array continuously "on" whenever power is provided to the memory array as such may simplify fabrication and/or operation of the memory array. Specific operative configurations are described below with reference to <FIG>.

Continuing the description of <FIG>, the illustrated embodiment shows that every column of the memory array has a capacitive unit <NUM>, with the capacitive units being in a common row as one another. In some embodiments, columns of the memory array may have two or more of the capacitive units, with a same number of capacitive units being provided along each of the individual columns of the memory array and with the capacitive units being arranged in rows analogous to the row shown in <FIG>.

The capacitive units <NUM> may have any suitable configuration. In some embodiments the capacitive units may have identical components as the memory cells <NUM>, and may differ from the memory cells only in a method of operation. Such may simplify fabrication of the capacitive units in that the capacitive units may be fabricated identically to the memory cells. For instance, in some embodiments the memory cells <NUM> may be 2T-1C memory cells, and the capacitive units may each comprise two transistors and a capacitor in a same configuration as the memory cells, as described with reference to <FIG>.

<FIG> shows a region of the bitline BLa of memory array <NUM> in an example embodiment in which each of the memory cells <NUM> comprises a first transistor T1, a second transistor T2, and a capacitor CAP. The bitline BLa is shown in a same configuration as in <FIG>, and accordingly has a capacitive unit <NUM> and three memory cells <NUM>. The memory cells are labeled as <NUM>, 12o and 12p in order to distinguish the memory cells from one another. The capacitive unit <NUM> is between the memory cells <NUM> and 12o, and like the memory cells comprises a capacitor CAP between first and second transistors T1 and T2.

The capacitors of the memory cells <NUM>, 12o and 12p are labeled as capacitors CAP-m, CAP-o and CAP-p, respectively; and the capacitor of capacitive unit <NUM> is labeled as capacitor CAP-n. The first transistors of memory cells <NUM>, 12o and 12p are labeled as transistors T1m, T1o and T1p, respectively; and the first transistor of capacitive unit <NUM> is labeled as T1n. The second transistors of memory cells <NUM>, 12o and 12p are labeled as transistors T2m, T2o and T2p, respectively; and the second transistor of capacitive unit <NUM> is labeled as T2n. The memory cell <NUM> comprises the transistors T1m and T2m along a wordline WL-<NUM>, the capacitive unit <NUM> comprises the transistors T1n and T2n along a wordline WL-<NUM>, the memory cell 12o comprises the transistors T1o and T2o along a wordline WL-<NUM>, and memory cell 12p comprises the transistors T1p and T2p along a wordline WL-<NUM>.

The memory cells <NUM>, 12o and 12p all have a common configuration as one another, and the capacitive unit <NUM> shares such common configuration. In some embodiments, the memory cells <NUM>, 12o and 12p, and the capacitive unit <NUM>, may be referred to as being substantially identical to one another, with the term "substantially identical" meaning that the memory cells and the capacitive unit are identical to one another within reasonable tolerances of fabrication and measurement. Particular components of the memory cells are described and labeled with reference to the cell <NUM>, and it is to be understood that the same components may be utilized in the other memory cells and the capacitive unit.

The capacitor CAP-m comprises a first node <NUM>, a second node <NUM> and capacitor dielectric material <NUM> between the first and second nodes. The first node <NUM> is shown to be container-shaped, and the second node <NUM> is shown to extend within such container shape. In other embodiments the first and second nodes may have other configurations. For instance, the first and second nodes may have planar configurations, with the capacitor dielectric material <NUM> being a planar configuration provided between the planar first and second nodes. In the illustrated configuration the first node <NUM> may be referred to as an outer node and the second node <NUM> may be referred to as an inner node.

A semiconductor pillar <NUM> extends from comparative bitline component BL-2a to the outer node <NUM> of capacitor CAP-m, and a semiconductor pillar <NUM> extends from the comparative bitline component BL-1a to the inner node <NUM> of the capacitor. Such semiconductor pillars may comprise any suitable semiconductor materials including, for example, one or both of silicon and germanium.

The transistor T1m has a first source/drain region <NUM> extending to the first node <NUM> of capacitor CAP-m, a second source/drain region <NUM> extending to comparative bitline BL-2a, and a channel region <NUM> between the first and second source/drain regions. A transistor gate <NUM> is along the channel region and offset from the channel region by gate dielectric material <NUM>.

The transistor T2 has a third source/drain region <NUM> extending to the second node <NUM> of capacitor CAP-m, a fourth source/drain region <NUM> extending to the comparative bitline component BL-1a, and a channel region <NUM> between the third and fourth source/drain regions. A transistor gate <NUM> is along the channel region and offset from the channel region by gate dielectric material <NUM>.

The wordline WL-<NUM> is common to the first and second transistors T1m and T2m, and comprises the gates <NUM>/<NUM>. The wordline WL-<NUM> (and the wordlines WL-<NUM>, WL-<NUM> and WL-<NUM>) may comprise any suitable electrically conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc. The bitline BLa may comprise a same conductive material was the wordlines, or may comprise a different conductive material.

The gate dielectric materials <NUM> and <NUM> may comprise any suitable compositions or combinations of compositions; including, for example, silicon dioxide, silicon nitride, high-K dielectric material, ferroelectric material, etc..

The source/drain regions and channel regions of the T1 and T2 transistors may be doped with any suitable dopants. In some embodiments, the source/drain regions may be n-type majority doped, and in other embodiments may be p-type majority doped.

The first and second transistors (T1 and T2) of the memory cells and capacitive unit may be considered to be vertically displaced relative to one another, and the capacitors of the memory cells and capacitive unit are vertically between the first and second transistors (for instance, the transistors T1m and T2m of memory cell <NUM> are vertically displaced relative to one another, and the capacitor CAP-m is vertically between such transistors). In the illustrated embodiment, each of the individual memory cells and the individual capacitive unit has the transistors and capacitor in a common vertical plane (for instance, the capacitive unit <NUM> has the transistors T1n/T2n and capacitor CAP-n in a common vertical plane as one another). In other embodiments, the transistors and capacitors of the memory cells and/or capacitive units may have other configurations.

The illustrated capacitors CAP-m, CAP-n, CAP-o and CAP-p in the embodiment of <FIG> may be replaced with other capacitive structures in other embodiments. For instance, any of the capacitors may be replaced with a capacitive structure having two or more capacitors in combination.

The memory array <NUM> is shown to be supported by a base <NUM>. The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. The base is shown to be spaced from components of array <NUM> to indicate that other circuitry or components may be between array <NUM> and the base. For instance, circuitry <NUM> may be between the memory array <NUM> and the base <NUM> in some embodiments. Circuitry <NUM> may be incorporated into the base <NUM> as a sense amplifier together with other electrical circuits that may be used to access to the array <NUM> to read or write data from or into the array <NUM>. In some embodiments, in applications where an interlayer insulating film intervenes between the array <NUM> and the base <NUM>, a plurality of vias are formed in the interlayer insulating film to electrically connect wordlines WL-<NUM>, WL-<NUM>, WL-<NUM> and WL-<NUM> and bitlines BL-1a and BL-2a of the array <NUM> to the circuits such as the sense amplifiers <NUM>, that are formed in the base <NUM>.

The illustrated memory array configuration of <FIG> utilizes 2T-1C memory cells. In other embodiments analogous configurations may utilize other types of memory cells, such as, for example, 2T-2C memory cells.

The illustrated memory array configuration of <FIG> utilizes a capacitive unit <NUM> which is substantially identical to the memory cells (<NUM>, 12o and 12p). In other embodiments the capacitive unit may be different from the memory cells. Regardless of whether the capacitive unit is substantially identical to memory cells or not, a difference between the capacitive unit and the memory cells is that the capacitive unit is not utilized for data storage during operation of the memory array. Instead, the capacitive unit is utilized for reducing parasitic coupling between adjacent bitlines.

In the illustrated embodiment of <FIG> the capacitive unit <NUM> may be operated (i.e., placed in an "on" state) by powering the wordline WL-<NUM> and thereby powering both of the transistors T1n and T2n (i.e., placing both of transistors T1n and T2n in an "on" state).

<FIG> shows a top view of a portion of a memory array <NUM> comprising columns corresponding to bitlines BLa, BLb, BLc and BLd, and comprising wordlines corresponding to the wordlines WL-<NUM>, WL-<NUM>, WL-<NUM> and WL-<NUM>. The column corresponding to bitline BLa is identical to the column shown in <FIG>, and comprises the memory cells <NUM>, 12o and 12p together with the capacitive unit <NUM>. The other columns also comprise memory cells <NUM> and capacitive units <NUM>.

The memory array of <FIG> may be operated in any suitable manner. In some embodiments at least some of the capacitive units <NUM> associated with the memory array may be maintained in the "on" state whenever any region of the memory array <NUM> is utilized for any operation, and may be considered to be "passive" in that the capacitive units are not controlled other than simply powering them on when the memory array is utilized. In some embodiments at least some of the capacitive units associated with a memory array may be selectively activated during particular operations, and otherwise left in an "off' state, and in such embodiments the capacitive units may be considered to be "active" or "selectable". For instance, in some embodiments capacitive units may be maintained in an "on" state during READ operations associated with memory cells of the array, and otherwise the capacitive units are in an "off" state. Selectively utilizing capacitive units during READ operations associated with memory cells of a memory array, and leaving the capacitive units "off" during WRITE operations associated with the memory cells, may be advantageous in some embodiments in that such may alleviate problematic parasitic capacitance during the READ operations and yet avoid possible interference the capacitive units may create during WRITE operations. Example operative arrangements of capacitive units are described with reference to <FIG>.

Referring to <FIG>, a portion of the memory array <NUM> of <FIG> is shown in top view. The memory array is powered, but none of the columns BLa, BLb, BLc or BLd is being utilized in a READ operation. Yet, all of the capacitive units <NUM> are powered (i.e., in an "on" state), as diagrammatically illustrated by a dashed-boxes <NUM> being provided around the capacitive units. One or more of the columns BLa, BLb, BLc or BLd may be being utilized in a programming operation at the operational stage of <FIG>, but regardless are not being utilized in a READ operation.

<FIG> shows the portion of memory array <NUM> in an operation in which memory cells <NUM> along the bitline BLc are part of a READ operation, as indicated by a dashed box <NUM> around the bitline BLc. The capacitive unit <NUM> associated with bitline BLc is powered (as indicated by dashed box <NUM>). The other capacitive units along wordline WL-<NUM> are also powered due to power being provided along WL-<NUM>. It is noted that having the capacitive units <NUM> in columns immediately adjacent BLc (i.e., columns BLb and BLd) in the "on" state may assist in reducing parasitic coupling between column BLc and the immediately adjacent columns during the reading of memory cells along BLc.

The structures and architectures described above may be incorporated into memory (e.g., DRAM, SRAM, etc.) and/or otherwise may be utilized in electronic systems. Such electronic systems may be any of a broad range of systems, such as, for example, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

Both of the terms "dielectric" and "electrically insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "electrically insulative" in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

When a structure is referred to above as being "on" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present. When a structure is referred to as being "connected" or "coupled" to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being "directly connected" or "directly coupled" to another structure, there are no intervening structures present.

Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells.

Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Individual memory cells comprise first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, has a second node electrically coupled with a source/drain region of the second transistor, and has capacitor dielectric material between the first and second nodes. The first and second transistors are coupled to a common wordline. Capacitive units are along the columns of the memory array. Individual capacitive units comprise identical components as the individual memory cells but not being utilized for data storage during operation of the memory array. An individual capacitive unit along an individual column being maintained in an "on" state when said individual column is utilized in a READ operation.

Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Individual memory cells comprise first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, has a second node electrically coupled with a source/drain region of the second transistor, and has capacitor dielectric material between the first and second nodes. The first and second transistors are coupled to a common wordline. Capacitive units are along the columns of the memory array. Individual capacitive units comprise identical components as the individual memory cells but are not utilized for data storage during operation of the memory array. An individual capacitive unit is maintained in an "on" state whenever power is provided to the memory array.

Claim 1:
A memory array (<NUM>), comprising:
a series of bitlines (BLa-BLd), each of the bitlines (BLa-BLd) having a first comparative bitline component (BL-<NUM>) and a second comparative bitline component (BL-<NUM>); the bitlines (BLa-BLd) defining columns of the memory array (<NUM>);
memory cells (<NUM>) along the columns of the memory array (<NUM>);
capacitive units (<NUM>) along the columns of the memory array (<NUM>) and interspersed amongst the memory cells (<NUM>); and
wherein the capacitive units (<NUM>) comprise the same configuration of components as the memory cells (<NUM>), the configuration of components being either i) two transistors (T1, T2) and a capacitor (CAP), or, ii) two transistors (T1, T2) and two capacitors (CAP-<NUM>, CAP-<NUM>), wherein the memory array (<NUM>) is operable to maintain the transistors (T1, T2) of the capacitive units (<NUM>) in an "on" state during READ operations associated with the memory cells (<NUM>); and
wherein the two transistors (T1, T2) are vertically displaced relative to one another and the one or two capacitors (CAP, CAP-<NUM>, CAP-<NUM>) are positioned vertically between the transistors (T1, T2).