Patent Description:
The present application relates to the technical field of semiconductors, and in particular to method for forming a semiconductor structure.

An existing memory usually includes a data memory cell and a control transistor for controlling the data memory cell. The integration level of the transistor restricts the storage density of the memory. For a planar transistor, the related art reduces the size of the transistor by reducing the channel size of the transistor, thereby improving the storage density of the memory.

However, as the channel size of the transistor reduces, the narrow channel effect and the short channel effect cause the performance of the transistor to decline, so that the performance of the memory is affected, and the further improvement of the size of the transistor and the storage density of the memory is restricted.

How to reduce the planar size of the transistor and improve the storage density of the memory without reducing the performance of the transistor is an urgent problem to be solved at present.

<CIT> discloses a structure in which lower source/drain regions of vertical field effect transistors, VFETs of memory cells in a memory array are aligned above and electrically connected to buried bit lines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bit line, which has the same or a narrower width than the lower source/drain region and which includes a pair of bit line sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. <CIT> also discloses a method that ensures that bit lines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bit line coupling. Related technologies are also known from <CIT>.

The technical problem to be solved by the present application is to provide a semiconductor structure, a method for forming the semiconductor structure, a memory, and a method for forming the memory, which further improve the storage density of the memory.

In order to solve the above problems, the present application provides a method for forming a semiconductor structure. The method includes: a substrate is provided, where a sacrificial layer and an active layer located on a surface of the sacrificial layer are formed on the substrate; the active layer and the sacrificial layer are etched up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along a first direction; an opening located between two adjacent one of the active lines is filled to form a first isolating layer; an end of the active lines is etched to form an opening hole exposing the surface of the substrate, a side wall of the opening holes exposing the sacrificial layer; the sacrificial layer is removed along the opening hole to form a gap between a bottom of the active lines and the substrate; a conductive material is filled in the gap to form a bit line extending along the first direction; the active lines are patterned to form a plurality of separate active pillars that are arrayed along the first direction and a second direction; and semiconductor pillars are formed on top surfaces of respective ones of the active pillars.

The method further includes the following operations.

A conductive material is filled in the opening hole to form a bit-line-connection line in the opening hole. A bottom of the bit-line-connection line is connected to a respective bit line.

The bit-line-connection line and the bit line are formed in a same process.

A first doped region is formed in the active pillars. A channel region above the first doped region and a second doped region above the channel region are formed in the semiconductor pillars. A gate structure surrounding the channel region is formed.

A second isolating layer covering the gate structure and the second doped region is formed.

An interconnect structure connected to the bit-line-connection line through the second isolating layer is formed.

Optionally, the opening holes are formed at both ends of each of the active lines, and the opening holes on the end of the active lines at a same side are spaced apart from each other.

Optionally, the operation that the first doped region is formed includes the following operation. Ions are implanted in the active pillars to form the first doped region in the active pillars. The operation that the second doped region is formed includes the following operation. Ions are implanted in the semiconductor pillars to form the second doped region on a top of the semiconductor pillars.

Optionally, the operation that the first doped region is formed includes the following operations. The active layer is doped using an in-situ doping process to form a first doped layer during formation of the active layer through an epitaxial growth process. The first doped layer is patterned into the first doped region after the active pillars are formed by patterning the active layer.

Optionally, the operation that the channel region and the second doped region are formed includes the following operation. The semiconductor pillars are in-situ doped using an in-situ doping process during formation of the semiconductor pillars through an epitaxial growth process, to sequentially form the channel region and the second doped region.

Optionally, the method further includes the following operation. An isolating dielectric layer filling openings between the active pillars is formed.

Optionally, the operation that the semiconductor pillars are formed includes the following operations. A protective layer is formed on the first isolating layer and the isolating dielectric layer. Epitaxial through holes are formed in the protective layer, where a bottom of the epitaxial through holes exposes a top surface of a respective one of the active pillars. A semiconductor material is epitaxially grown on the top surfaces of the active pillars to form the semiconductor pillars in respective ones of the epitaxial through holes. The protective layer is removed.

Optionally, after a semiconductor material is epitaxially grown on a top surface of the active pillars, the semiconductor material is etched to form the semiconductor pillars on top surfaces of respective ones of the active pillars.

Optionally, the operation that the gate structure is formed includes the following operations. A gate dielectric layer and a gate layer are sequentially formed on the semiconductor pillars, the first isolating layer, and the isolating dielectric layer. The gate dielectric layer and the gate layer are patterned to form the gate structure that is located on the surfaces of the first isolating layer and the isolating dielectric layer and surrounds a part of the semiconductor pillars at a height, and to expose a top region of the semiconductor pillars.

Optionally, a plurality of the gate electrodes surrounding on the surfaces of respective ones of the semiconductor pillars arranged along the second direction in the same straight line are connected with each other.

According to the method for forming a semiconductor structure of the present application, a sacrificial layer and an active layer located on the surface of the sacrificial layer are formed on a substrate. The position of the sacrificial layer is replaced by bit lines, so that buried bit lines are formed. Therefore, a vertical transistor can be formed subsequently, and a source/drain at the bottom of the vertical transistor can be led out through the bit lines. Moreover, according to the method for forming the semiconductor structure of the present application, the thickness of the active layer is low, and then a semiconductor pillar is formed on the top of an active pillar formed by patterning the active layer, so that the risk of pattern collapse after the active layer is patterned can be reduced.

Further, the vertical transistor occupies a small layout size, and the channel width is determined by the thickness of the active layer, so that the area of the transistor can be reduced without reducing the channel width or the like, thereby improving the integration level of the semiconductor structure.

In order to describe the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings required in the embodiments of the present application. It is apparent to those of ordinary skill in the art that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without involving any inventive effort.

In order to clarify the purpose, technical means, and effects of the present application, the present application will be further described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are only a portion of the embodiments of the present application, not all embodiments, and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without involving any inventive effort are within the scope of protection of the present application.

Referring to <FIG>, schematic diagrams of a forming process of a semiconductor structure according to an embodiment of the present application are shown.

Referring to <FIG>, a substrate <NUM> is provided. A sacrificial layer <NUM> and an active layer <NUM> located on a surface of the sacrificial layer <NUM> are formed on a surface of the substrate <NUM>.

The substrate <NUM> may be made of various semiconductor materials such as single crystal silicon, germanium, and SiC. The substrate <NUM> may be a single-layer structure, or may be a composite structure. For example, the substrate <NUM> includes, but is not limited to, a semiconductor base and a dielectric layer formed on the surface of the semiconductor base.

The sacrificial layer <NUM> and the active layer <NUM> may be sequentially formed on the surface of the substrate <NUM> by a deposition process. The active layer <NUM> adopts a semiconductor material, such as one or more semiconductor materials of Si, Ge, SiC or SiG. The material of the sacrificial layer <NUM> is different from that of the substrate <NUM> and the active layer <NUM>, so that the influence on the substrate <NUM> and the active layer <NUM> is reduced during the subsequent removal of the sacrificial layer <NUM>.

In the present embodiment, the substrate <NUM> is a silicon substrate, the sacrificial layer <NUM> is a SiGe layer, and the active layer <NUM> is a silicon layer. After the sacrificial layer <NUM> is epitaxially formed on the surface of the substrate <NUM> by an epitaxial growth process, the active layer <NUM> is formed on the surface of the sacrificial layer <NUM> by an epitaxial process.

In practice, the material of the sacrificial layer <NUM> is different from the materials of the substrate <NUM> and the active layer <NUM>, and there is a higher etching selection ratio between the sacrificial layer <NUM> and the substrate <NUM> and there is a higher etching selection ratio between the sacrificial layer <NUM> and the active layer <NUM> during the removal of the sacrificial layer <NUM>.

In some embodiments, the substrate <NUM>, the sacrificial layer <NUM>, and the active layer <NUM> may be an SOI substrate, and a buried oxide layer in the SOI substrate serves as the sacrificial layer <NUM>.

In other embodiments, a doped layer may be formed inside a bulk silicon substrate to serve as the sacrificial layer <NUM> by implanting ions in the bulk silicon substrate. For example, Ge is implanted in the bulk silicon, and a SiGe layer is formed inside the bulk silicon to serve as the sacrificial layer <NUM> by controlling the implantation depth of Ge. A silicon layer below the doped layer serves as the substrate <NUM>, and a silicon layer above the doped layer serves as an active layer. In other embodiments, the doped layer may be formed by implanting other elements, such as C, O, and N. The etching rate of the doped layer is different from that of material layer above the doped layer and that of the material layer below the doped layer, thereby forming the sacrificial layer <NUM>. Preferably, the material of the sacrificial layer <NUM> may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc..

The active layer <NUM> is configured to form a bottom doped region, i.e., a source/drain, of a vertical transistor. The sacrificial layer <NUM> is configured to be replaced subsequently to form a bit line. The thicknesses of the sacrificial layer <NUM> and the active layer <NUM> are reasonably set according to the size of the vertical transistor to be formed and the size of the bit line. In one embodiment, the sacrificial layer <NUM> may have a thickness of <NUM>-<NUM>, and the active layer <NUM> may have a thickness of <NUM>-<NUM>. In the present embodiment, the bottom doped region of the transistor is formed separately from an upper channel region and a top doped region, so that the thickness of the active layer <NUM> can be reduced, and the probability that a formed active pattern collapses after the active layer <NUM> is patterned can be reduced.

Referring to <FIG>, the active layer <NUM> and the sacrificial layer <NUM> are etched up to the surface of the substrate <NUM> to form a plurality of active lines <NUM> arranged in parallel and extending along a first direction.

In the present embodiment, the operation that the active lines <NUM> are formed further includes the following operations. A patterned mask layer (not shown) is formed on the surface of the active layer <NUM>. An opening pattern extending along the first direction is provided in the patterned mask layer. The active layer <NUM> and the sacrificial layer <NUM> are etched by taking the patterned mask layer as a mask to form elongated active lines <NUM> and elongated sacrificial layers 120a.

In the present embodiment, the first direction is a y-direction. The active layer <NUM> and the sacrificial layer <NUM> are etched by adopting a dry etching process. A corresponding etching gas is selected at a corresponding etching stage to etch the active layer <NUM> and the sacrificial layer <NUM>.

Referring to <FIG>, a first isolating layer <NUM> filling the spacing between the active lines <NUM> is formed on the surface of the substrate <NUM>. An end of the active lines <NUM> is etched to form an opening hole <NUM> exposing the surface of the substrate <NUM>, and a side wall of the opening holes <NUM> exposes the sacrificial layer 120a.

The material of the first isolating layers <NUM> is different from that of the sacrificial layer 120a, and the material of the first isolating layers <NUM> is a dielectric material for providing electrical isolation between the active lines <NUM>. In the present embodiment, the material of the first isolating layers <NUM> is silicon oxide. In the present embodiment, the first isolating layer <NUM> is formed by a chemical vapor deposition process. After an isolating material filling the spacing between the adjacent active lines <NUM> and covering the tops of the active lines <NUM> is formed on the surface of the substrate <NUM>, the first isolating layer <NUM> is formed by planarizing the isolating material. In the present embodiment, the top of the first isolating layer <NUM> is flush with the top of the active line <NUM>. In other embodiments, a patterned mask layer for patterning the active layer to form the active line is retained at the top of the active line <NUM>, and the first isolating layer <NUM> is flush with the patterned mask layer. In other embodiments, the patterned masking layer has been removed prior to forming the first isolating layer <NUM>. The first isolating layer <NUM> also covers the top of the active line. In the subsequent process, the top of the active line <NUM> may be protected.

After forming the first isolating layer <NUM>, the end of the active lines <NUM> is etched to form an opening hole <NUM>. A side wall of the opening holes <NUM> exposes the sacrificial layer 120a. Specifically, the opening holes <NUM> are formed on the ends of the active lines at the same side, or the opening holes are formed on the ends of the active lines at both sides. Moreover, the opening hole is formed on only one end of the active line, and the opening holes on the end at the same side are spaced apart from each other to reduce the density of the opening holes in a local region and increase a process window.

Referring to <FIG>, the sacrificial layer 120a is removed along the opening hole <NUM>, and a gap <NUM> is formed between the bottom of the active line <NUM> and the substrate <NUM>.

The sacrificial layer 120a is removed by a wet etching process. Those skilled in the art would be able to select a suitable etching solution according to the material of the sacrificial layer 120a, so that during the wet etching process, there is a higher etching selection ratio between the sacrificial layer 120a and the active line <NUM> as well as a higher etching selection ratio between the sacrificial layer 120a and the first isolating layer <NUM>, so as to reduce the influence on the active line <NUM> and the first isolating layer <NUM> during the removal of the sacrificial layer 120a.

After the sacrificial layer 120a is removed, the active line <NUM> is supported by the first isolating layer <NUM> and suspended above the substrate <NUM>, and a gap <NUM> is formed between the active line <NUM> and the substrate <NUM>.

Referring to <FIG>, the gap <NUM> is filled with a conductive material to form bit lines <NUM> extending along the first direction. <FIG> is a cross-sectional schematic diagram taken along a secant line A-A' in <FIG>. <FIG> is a cross-sectional schematic diagram taken along a secant line B-B' in <FIG>.

A conductive material such as polysilicon or a metal material such as W, Co, Ag, or Al may be formed in the gap <NUM> by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The conductive material may also be a multilayer material, such as a combination of TiN and W.

The conductive material fills the gap <NUM> to form bit lines <NUM> at the bottoms of the active lines <NUM>. The conductive material also fills the opening holes <NUM>, and covers the tops of the first isolating layer <NUM> and the active line <NUM>. The conductive material on the top of the first isolating layer <NUM> and the top of the active line <NUM> is removed subsequently through an etching back or planarization process. The opening hole <NUM> is filled with the conductive material to form a bit-line-connection line <NUM> in each opening hole <NUM>. The bottom of the bit-line-connection line <NUM> is connected to the bit line <NUM> for leading out the bit line <NUM> buried below the active lines <NUM> so as to apply a control signal to the bit line <NUM>. Each bit line <NUM> is located below a respective one of the active lines <NUM>, forms an electrical connection with the active line <NUM>, and extends along an extending direction of the active line <NUM>. In the present embodiment, the bit line <NUM> and the bit-line-connection line <NUM> are simultaneously formed in the same process to save process cost.

Referring to <FIG>, the active lines <NUM> are patterned to form a plurality of separate active pillars <NUM>.

In the present embodiment, both the active lines <NUM> and the first isolating layers <NUM> are patterned to form elongated openings extending along an x-direction. The active lines <NUM> are patterned to form active pillars <NUM>. The active pillars <NUM> are arrayed along the first direction (y-direction) and the second direction (x-direction). When the active line <NUM> is patterned, only the active lines <NUM> are etched up to the surfaces of the bit lines <NUM> so that the bit lines <NUM> at the bottoms of the active pillars <NUM> arranged along the y direction in the same straight line are continuous with each other.

In other embodiments, only the active lines <NUM> may be patterned by a selective etch process to form a plurality of active pillars <NUM> while keeping the first isolating layer <NUM> unpatterned.

In the present embodiment, an angle between the first direction and the second direction is <NUM>°. In other embodiments, the angle between the first direction and the second direction is comprised between <NUM>° and <NUM>°.

Referring to <FIG>, an isolating dielectric layer <NUM> is filled in openings located between adjacent active pillars <NUM> and adjacent first isolating layers 500a. Ions are implanted in the active pillars <NUM> to form first doped regions <NUM>.

In other embodiments, the first doped regions <NUM> may also be formed by a diffusion process. Specifically, a transition layer with doping elements is formed on the surface of the substrate <NUM> between the adjacent active lines <NUM> (referring to <FIG>). At least a part of doping elements in the transition layer <NUM> with doping atoms are diffused into the active lines <NUM> by a diffusion process to form doped active lines, and the doped active lines are patterned to form the first doped regions <NUM>. In other embodiments, a transition layer with doping elements may be formed on the surface of the substrate between the active pillars <NUM> (referring to <FIG>), and the doping elements are diffused into the active pillars <NUM> by a diffusion process to form the first doped regions <NUM>.

After a transition layer material is deposited on the surface of the substrate <NUM>, a transition layer with a certain thickness may be formed by etching back the transition layer material. The thickness of the transition layer may be adjusted according to the size requirements of a source/drain region of a transistor to be formed. In some embodiments, the thickness of the transition layer is equal to the height of the active line <NUM> or the active pillar <NUM>. In some embodiments, the transition layer may also cover the tops of the active lines <NUM> or the active pillars <NUM> to ensure that all regions of the entire active lines <NUM> or active pillars <NUM> are doped.

The material of the transition layer is different from that of the active line, and may be a material for facilitating impurity diffusion, such as polysilicon, or other dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. The operation that the transition layer with doping elements is formed includes the following operations. After a certain thickness of undoped transition layer is formed on the surface of the semiconductor substrate <NUM>, the transition layer is doped by ion implantation. At this moment, the top of the active line <NUM> or the active pillar <NUM> is covered with a patterned mask layer, and the transition layer can only be doped through the ion implantation by controlling the energy of the ion implantation. N-type or P-type ions, or atomic clusters with N-type or P-type ions are implanted into the transition layer according to the type of the transistor to be formed. The doping elements in the transition layer may be in the form of ions, atoms, compound molecules, or clusters. In other embodiments, the transition layer with doping elements may also be formed directly during the formation of the transition layer through an in-situ doping process by adding a doping gas with doping elements to a deposition process gas.

The diffusion process may be a thermal annealing process. An annealing process with suitable parameters is selected according to the diffusion efficiency of doping atoms, so that the doping elements in the transition layer are diffused into the active line <NUM> or the active pillar <NUM> to form the first doped region <NUM>. The doping concentration in the first doped region formed after the diffusion process may be adjusted by adjusting parameters such as the concentration of the doping elements in the transition layer, diffusion process time, and temperature.

In other embodiments, an in-situ doping process may be used to dope the active layer <NUM> during the formation of the active layer <NUM> by deposition through an epitaxial process. After the active layer <NUM> is patterned, the first doped region <NUM> is formed.

The diffusion or in-situ doping can reduce damage to the surface of the active pillar <NUM> (first doped region <NUM>) as compared to forming the first doped region <NUM> by ion implantation.

Referring to <FIG>, semiconductor pillars <NUM> are formed on the top surfaces of the first doped regions <NUM>.

In the present embodiment, a semiconductor material is epitaxially grown on a top surface of the active pillars by a selective epitaxial process to form semiconductor pillars <NUM> on the top surfaces of respective ones of the active pillars. As a result of the selective epitaxial process, the semiconductor material will only be epitaxially grown on the active pillars, i.e., on the top surfaces of the first doped regions <NUM>. The material of the first doped region <NUM> is the same as the material of the active pillar, i.e. Si. In other embodiments, the material of the semiconductor pillars <NUM> may also be other semiconductor materials such as SiGe. After semiconductor material with a certain thickness is epitaxially grown, the semiconductor material may be etched to form semiconductor pillars <NUM> with a smoother surface appearance.

In other embodiments, the operation that the semiconductor pillars are formed includes the following operations. A protective layer is formed on the first isolating layers and the isolating dielectric layer. Epitaxial through holes are formed in the protective layer. The bottom of each epitaxial through hole exposes a top surface of a respective one of the active pillars. A semiconductor material is epitaxially grown on the top surface of the active pillars to form semiconductor pillars in the epitaxial through holes. The protective layer is removed. Through the epitaxial through hole, the growth size and position of the semiconductor pillars are limited, and the appearance is not required to be finished by etching. The problems of collapse of the semiconductor pillars in the growth process or the finishing process, etc. can be avoided.

In other embodiments, a semiconductor material layer covering the surface of a structure shown in <FIG> may also be formed by a conventional deposition process, such as a CVD deposition process, and then the semiconductor material layer is patterned to form semiconductor pillars on the surfaces of the first doped regions <NUM>.

Referring to <FIG>, channel regions located on the surfaces of the first doped regions <NUM> and gate structures <NUM> surrounding the channel regions are formed in the semiconductor pillars <NUM>.

In the embodiments of the present application, channel ion implantation is performed on the semiconductor pillars <NUM> by ion implantation, channel regions may be formed on the first doped regions <NUM>, and parameters such as a threshold voltage of a transistor to be formed may be adjusted by the channel ion implantation.

In other embodiments, channel doping may be performed at corresponding positions in the channel regions by an in-situ doping process during formation of the semiconductor pillars <NUM>.

A gate dielectric layer and a gate layer are sequentially formed on the surfaces of the semiconductor pillars <NUM>, the first isolating layers 500a, and the isolating dielectric layers <NUM>. The gate dielectric layer and the gate layer are patterned to form gate structures <NUM> that surround the channel regions of the semiconductor pillars <NUM> and expose top regions of the semiconductor pillars <NUM>.

The gate dielectric layer may be a gate dielectric material such as silicon oxide, hafnium oxide, or aluminum oxide. The material of the gate layer may be a conductive material such as polysilicon, tungsten, copper, or aluminum. The gate dielectric layer and the gate layer which cover the surface of a structure in <FIG> may be sequentially formed through a deposition process. The gate structures <NUM> are then formed by patterning the gate dielectric layer and the gate layer through an etching process. The gate structures <NUM> surround the channel regions of the active pillars <NUM>. The gate structure <NUM> includes a gate dielectric layer and a gate electrode covering the gate dielectric layer. Only the gate electrode in the gate structure <NUM> is shown in <FIG>.

In the present embodiment, gate electrodes of the gate structures <NUM> surrounding on the surfaces of respective ones of the semiconductor pillars <NUM> arranged along the second direction (x direction) in the same straight line are connected with each other to form a word line.

In other embodiments, the gate structures <NUM> on the semiconductor pillars <NUM> may also be independent of each other.

In order to electrically isolate the gate structures <NUM> from one another, after the gate structures <NUM> are formed, an isolating dielectric layer <NUM> is filled between the adjacent gate structures <NUM>. In other embodiments, the isolating dielectric layers <NUM> may be formed, the isolating dielectric layers <NUM> may then be patterned to form openings, and the gate structures <NUM> may be formed in the openings.

Referring to <FIG>, after the gate structure <NUM> is formed, ions are implanted in the top regions of the semiconductor pillars <NUM> to form second doped regions <NUM>.

The doping type of the second doped region <NUM> is the same as that of the first doped region <NUM>. The second doped regions <NUM> and the first doped regions <NUM> serve as a source or a drain of a vertical transistor, respectively. In other embodiments, the second doped regions <NUM> may also be formed by suitable in-situ doping, diffusion, or implantation in the operations previously described, which is not described herein.

Referring to <FIG>, a second isolating layer <NUM> covering the gate structures <NUM> and the second doped regions <NUM> is formed. The second isolating layer <NUM> exposes a top surface of each second doped region <NUM>.

The material of the second isolating layer <NUM> may be an insulating dielectric material such as silicon oxide and silicon oxynitride. The second isolating layer <NUM> forms an isolating layer between vertical transistors together with the first isolating layer 500a, the isolating dielectric layer <NUM>, and the isolating dielectric layer <NUM>, and provides a planar surface for forming other semiconductor structures or material layers above the vertical transistors.

An interconnect structure connected to the bit-line-connection line <NUM> through the second isolating layer <NUM> is formed.

According to the above method, a vertical transistor is formed on the substrate, and a buried bit line is formed between a lower portion of the first doped region at the bottom of the vertical transistor and the substrate, so that the area of the transistor can be reduced, and the problem of how to apply a bit line signal is solved.

The embodiments of the present application also provide a semiconductor structure.

Referring to <FIG>, schematic diagrams of a semiconductor structure according to an embodiment of the present application are shown.

The semiconductor structure includes: a substrate <NUM>; a vertical transistor on the substrate <NUM>, including a first doped region <NUM>, a channel region <NUM>, a second doped region <NUM>, and a gate structure <NUM> surrounding the channel region <NUM>, which are disposed sequentially upwards from the surface of the substrate <NUM>; and a bit line <NUM>, connected to the first doped region <NUM> and located between the bottom of the first doped region <NUM> and the substrate <NUM>.

A plurality of vertical transistors are formed on the semiconductor structure and arrayed along a first direction (y direction) and a second direction (x direction). The first doped regions <NUM> at the bottoms of the vertical transistors arranged along the first direction in the same straight line are connected to the same bit line <NUM>. The gate structures <NUM> of the vertical transistors arranged along the second direction in the same straight line are connected with each other.

The semiconductor structure further includes: an isolating layer located on the substrate <NUM> and formed between the vertical transistors. The isolating layer includes a first isolating layer 500a and an isolating dielectric layer <NUM> between the adjacent bit lines <NUM> and between the adjacent first doped regions <NUM>, an isolating dielectric layer <NUM> located between the adjacent gate structures <NUM> and located on the surfaces of the first isolating layer 500a and the isolating dielectric layer <NUM>, and a second isolating layer <NUM> located between the adjacent second doped regions <NUM> and located on the surface of the isolating dielectric layer <NUM>.

The semiconductor structure further includes opening holes penetrating through the first isolating layers 500a. A bit-line-connection line <NUM> is formed in each opening hole. The bottom of each bit-line-connection line <NUM> is connected to a respective one of the bit lines <NUM>. In the present embodiment, the bit-line-connection line <NUM> is located at one side edge of a transistor array. One bit-line-connection line <NUM> is formed at one side of each row of transistors arranged along the y direction to be connected to the bit line <NUM> below the row of transistors. Specifically, the opening holes are formed on the ends of the active lines at the same side, or the opening holes are formed on the ends of the active lines at both sides. Moreover, the opening hole is formed on only one end of the active line, and the opening holes on the end at the same side are spaced apart from one another to reduce the density of the opening holes in a local region and increase a process window.

In the present embodiment, the channel region <NUM> and the second doped region <NUM> of each vertical transistor are formed in the semiconductor pillars on the surface of the first doped region <NUM>. A semiconductor layer in which the channel region <NUM> and the second doped region <NUM> are located and the semiconductor pillars are not integrally formed but are separately formed. In other embodiments, the first doped region <NUM>, the channel region <NUM>, and the second doped region <NUM> of each vertical transistor are located in the same active pillar that is integrally formed. The first doped region <NUM>, the channel region <NUM>, and the second doped region <NUM> are formed by doping.

Doping ions in the first doped region <NUM> and/or the second doped region <NUM> are formed by diffusion or ion implantation.

The embodiments of the present application also provide a memory and a method for forming the memory.

First, a semiconductor structure as shown in <FIG> is provided. The detailed description of the semiconductor structure will be given with reference to the above-described embodiments and will be omitted herein.

Referring to <FIG>, a memory cell <NUM> is formed above each vertical transistor. The memory cell <NUM> is connected to the second doped region <NUM> of the vertical transistor.

In one embodiment, the memory is a DRAM. The memory cell <NUM> is a metal capacitor including an upper electrode, a lower electrode, and a capacitive dielectric layer between the upper electrode and the lower electrode. The structure of the capacitor may be a planar capacitor, a cylindrical capacitor, etc. Those skilled in the art would be able to select a capacitor with a suitable structure as a memory cell as required. In <FIG>, the memory cell <NUM> is merely an example and does not represent an actual structure of the capacitor. In the present embodiment, the second doped region <NUM> of each transistor is connected to one memory cell to form a 1T1C storage structure. The memory cell may include one capacitor, or more than two capacitors in parallel.

In other embodiments, in order to reduce the connection resistance between the second doped region <NUM> and the memory cell <NUM>, a metal contact layer may also be formed on the surface of the second doped region <NUM>, and then the memory cell may be formed on the surface of the metal contact layer.

The memory cell <NUM> is formed in a dielectric layer (not shown). An interconnect structure connecting the bit-line-connection line <NUM> and the gate structure <NUM> may also be formed in the dielectric layer to connect the bit line and a word line to an external circuit.

In other embodiments of the present application, the memory cell may also be any one of a magnetic memory cell, a ferroelectric memory cell, a phase change memory cell, or a resistive memory cell.

Referring to <FIG>, a schematic diagram of a memory according to an embodiment of the present application is shown.

The memory is a FeRAM. A ferroelectric memory cell <NUM> is formed above the second doped region <NUM> of each vertical transistor of the semiconductor structure shown in <FIG>.

The ferroelectric memory cell includes a lower electrode connected to the second doped region <NUM>, an upper electrode located above the lower electrode, and a ferroelectric capacitor formed by a ferroelectric material layer between the upper electrode and the lower electrode. The material of the ferroelectric material layer may be lead zirconate titanate (PZT) or strontium barium titanate (SBT). The ferroelectric memory cell <NUM> in <FIG> is only schematic and does not represent the structure of an actual ferroelectric memory cell. Those skilled in the art should be able to combine as required to form the ferroelectric memory cell <NUM> with a corresponding structure, which is not limited herein.

For the ferroelectric memory cells <NUM>, it is also necessary to form plate lines <NUM> connected to the upper electrodes above the ferroelectric memory cells <NUM>. In the present embodiment, ferroelectric memory cells arranged along the second direction (x direction) in the same straight line are connected to the same plate line <NUM>. Bidirectional pressurization of the ferroelectric memory cells <NUM> may be realized by the plate line <NUM> and the vertical transistor, thereby implementing data storage using the properties of the ferroelectric material layer.

In other embodiments, a magnetic memory cell may also be formed on the second doped region <NUM> of the vertical transistor. The magnetic memory cell includes a magnetic tunnel junction including a fixed layer, a free layer, and a dielectric layer between the fixed layer and the free layer. The fixed layer is connected to the second doped region <NUM>.

In other embodiments, memory cells with other structures or types may be formed to form corresponding memories.

According to the memory and the method for forming the memory, vertical transistors are used as a control transistors connected to the memory cells, and buried bit lines connected to the control transistors are used, so that the storage density of the memory may be improved.

Claim 1:
A method for forming a semiconductor structure, comprising:
providing a substrate (<NUM>), wherein a sacrificial layer (<NUM>) and an active layer (<NUM>) located on a surface of the sacrificial layer (<NUM>) are formed on the substrate (<NUM>);
etching the active layer (<NUM>) and the sacrificial layer (<NUM>) up to a surface of the substrate (<NUM>) to form a plurality of active lines (<NUM>) arranged in parallel and extending along a first direction (y);
filling an opening located between two adjacent ones of the active lines (<NUM>) to form a first isolating layer (<NUM>);
etching an end of the active lines (<NUM>) to form an opening hole (<NUM>) exposing the surface of the substrate (<NUM>), a side wall of the opening holes (<NUM>) exposing the sacrificial layer (<NUM>);
removing the sacrificial layer (<NUM>) along the opening hole (<NUM>), to form a gap (<NUM>) between a bottom of the active lines (<NUM>) and the substrate (<NUM>);
filling a conductive material in the gap (<NUM>) to form a bit line (<NUM>) extending along the first direction (y);
patterning the active lines (<NUM>) to form a plurality of separate active pillars (<NUM>) that are arrayed along the first direction (y) and a second direction (x); and
forming semiconductor pillars (<NUM>) on top surfaces of respective ones of the active pillars (<NUM>),
characterized in that the method further comprises:
filling a conductive material in the opening hole (<NUM>) to form a bit-line-connection line (<NUM>) in the opening hole (<NUM>), a bottom of the bit-line-connection line (<NUM>) being connected to the bit line (<NUM>), wherein the bit-line-connection line (<NUM>) and the bit line (<NUM>) are formed in a same process;
forming a first doped region (<NUM>) in the active pillars (<NUM>); forming a channel region (<NUM>) above the first doped region (<NUM>) and a second doped region (<NUM>) above the channel region (<NUM>) in the semiconductor pillars (<NUM>); and forming a gate structure (<NUM>) surrounding the channel region (<NUM>);
forming a second isolating layer (<NUM>) covering the gate structure (<NUM>) and the second doped region (<NUM>); and
forming an interconnect structure connected to the bit-line-connection line (<NUM>) through the second isolating layer (<NUM>).