Patent Description:
Known high power semiconductor devices have a junction arranged in an active region of a semiconductor wafer. To avoid electric field crowding at an edge of a main contact resulting in breakdown of the device at a relatively low breakdown voltage VBR, these power semiconductor devices require an efficient junction termination. For silicon-based power semiconductor devices known junction termination techniques include single-side single negative bevel, single positive bevel, double positive bevel, combined positive-negative bevel, or a planar junction termination such as junction termination extension (JTE), variation of lateral doping (VLD) and floating field ring terminations (FFR) with and without field plate extensions. A passivation layer made of an insulating material such as silicon oxide, silicon nitride or diamond like carbon (DLC) is formed on the semiconductor wafer in a circumferential edge for surface passivation and electrical insulation of the junction termination. In addition to a relatively thin passivation layer made from silicon oxide, silicon nitride or diamond like carbon (DLC) or any other appropriate inorganic material, an organic silicone rubber is arranged to cover the edge of the semiconductor wafer and to overlap the main contact such that a distance between top and bottom electrodes (creepage distance) is prolonged and ionization of housing inner atmosphere or surface material (sparking) is avoided.

A common packaging technology for the high power semiconductor devices is a press-pack type packaging, in which a semiconductor wafer is clamped between two copper pole pieces under pressure to obtain proper thermal and electric contact between the semiconductor wafer and the copper pole pieces acting as external electrodes. Usually a pressure in a range between <NUM> N/mm<NUM> and <NUM> N/mm<NUM> is applied. During operation of the high power semiconductor device heat is generated resulting in operating temperatures up to <NUM> or even higher for a short period of time. Because of the difference between the coefficient of thermal expansion of the semiconductor wafer and that of the copper pole pieces, the copper pole pieces cannot be directly attached to the semiconductor wafer. Molybdenum has a coefficient of thermal expansion that is close to that of silicon and also has a great hardness. Therefore, molybdenum disks sandwiched between the two copper pole pieces and the semiconductor wafer, respectively, are used to compensate for the difference between the coefficient of thermal expansion of the semiconductor wafer and that of the copper pole pieces. In application the press-pack comprising the semiconductor wafer, the molybdenum disks and the copper pole pieces are inserted between coolers to remove the heat generated by the semiconductor wafer during operation.

For obtaining a good thermal and electric contact between the semiconductor wafer and the molybdenum disk it is common practice to bond the semiconductor wafer to the molybdenum disk by soldering, by low temperature bonding (LTB) and nano-LTB using nano-silver or nano-copper paste or foil, or by brazing. Also with the molybdenum disk firmly bonded to the semiconductor wafer by the LTB process bowing of the semiconductor wafer is minimized when applying inhomogeneous pressure onto both sides of the semiconductor wafer in a press-pack, which is the case when different sized molybdenum disks are used for the top and the bottom side of the device, for example. Without bonding the molybdenum disk to the semiconductor wafer, the semiconductor wafer easily breaks when it is sandwiched between different sized molybdenum disks under pressure in a press-pack. On the other side any bonding, brazing or soldering process involves the risk of wafer bow or deformation.

In the publication "<NPL>, it is discussed a low temperature joining technique for bonding a silicon wafer to a molybdenum disk which reduces the thermomechanical stress between the bonded materials. This LTJ-technique is based on pressure sintering of silver powder.

From the publication "<NPL>) it is known a housing less fast recovery diode (HL-FRD), in which a rubber protection of a junction termination is replaced by a mold compound polymer which serves as a hermetic protection of a surface passivation by diamond like carbon (DLC). In this prior art the semiconductor wafer is sandwiched between two molybdenum disks, which have a different diameter. The larger molybdenum disk is bonded to the backside of the semiconductor wafer. However, bonding the molybdenum disk to the semiconductor wafer involves the risk to generate conductive particles on the wafer in the area of the junction termination and increases the manufacturing costs.

<CIT> discloses a semiconductor power device in which a semiconductor wafer is clamped between two molybdenum disks, wherein the molybdenum disks are not bonded to the wafer. It is pointed out in this prior art document that it is necessary that the two molybdenum disks must have the same size to avoid breakage of the semiconductor wafer due to inhomogeneous pressure application. In <CIT> the two molybdenum disks have both a smaller diameter than the semiconductor wafer. This results in a relatively bad removal of heat generated in the circumferential edge region of the wafer which is not in contact with the molybdenum disks.

From <CIT> it is known a thyristor, which comprises a semiconductor wafer that is arranged within a hermetically sealed housing, wherein the housing comprises two parallel, disc-like electrodes. The semiconductor wafer is arranged between two molybdenum disks without bonding the molybdenum disks to the semiconductor wafer. The stack of molybdenum disks and the wafer is held between the electrodes by pressure.

Both molybdenum disks have the same diameter smaller than that of the wafer. As for the above prior art this results in a relatively bad removal of heat generated during device operation, in particular in the circumferential edge region of the wafer which is not in contact with the molybdenum disks.

From <CIT> it is known press-pack wherein a molybdenum disk is glued to a semiconductor wafer by a silicone rubber. To prevent the silicone rubber from entering the gap between the molybdenum disk and the wafer, an O-ring is arranged between the wafer and the molybdenum disk along the circumferential edge of the wafer. Accordingly, also in this prior art, heat dissipation is bad, because heat is not efficiently removed from a circumferential edge region of the semiconductor wafer.

From <CIT> it is known a thyristor device comprising a semiconductor element having opposing first and second contact faces, compensating elements 40a and 40b and a silicone passivation covering the edge oft he semiconductor element and lateral faces of the compensating elements.

From <CIT> it is known a semiconductor device, which comprises a wafer sandwiched between two electrodes. A molybdenum layer is interposed between the lower electrode and the wafer. The molybdenum layer clamped between the wafer and the lower electrode. A rubber ring covers a rim of the wafer and the side of the wafer. According to <CIT> a power device comprises a wafer, a molybdenum or tungsten reinforcing disc, a lower electrode and an upper electrode. The wafer is sandwiched between the lower and upper electrode. The molybdenum or tungsten reinforcing disc is hardsoldered to the lower surface of the wafer and arranged between the lower terminal electrode and the wafer. A metal layer, which is liquid during the operation of the device, is interposed between the lower terminal electrode and the reinforcing disc.

<CIT> discloses a power semiconductor device, comprising a semiconductor wafer having a first main side, a second main side opposite to the first main side, a lateral side connecting the first main side and the second main side, at least one junction and a junction termination laterally surrounding the at least one junction; a protection layer covering the lateral side of the semiconductor wafer and covering the second main side at least in an area of the junction termination, a first metal disk which has a lateral size that is the same as or larger than a lateral size of the semiconductor wafer, wherein the first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer, wherein the first metal disk is a molybdenum or tungsten disk.

From <CIT> it is known a hollow cylindrical semiconductor device, in which a cylindrical semiconductor form is concentrically positioned between copper cylinders. The radial spaces between the semiconductor form and the copper cylinders are filled with mercury volumes to insure a good electrical and thermal contact of the inner and outer surfaces of the semiconductor form to the copper cylinders.

In view of the above disadvantages in the prior art it is an object of the invention to provide a power semiconductor device in which heat dissipation is efficient while wafer breakage can be avoided and the risk of device failure due to conductive particles on a junction termination of a semiconductor wafer can be reduced.

The object is attained by a power semiconductor device according to claim <NUM>. Further developments of the invention are specified in the dependent claims.

In the invention the first metal disk arranged on a first main side of the semiconductor wafer has a lateral size that is the same as or larger than a lateral size of the semiconductor wafer to cover the first main side of the semiconductor wafer. Wafer breakage during application of pressure in a press-pack can surprisingly be avoided due to the relatively large lateral size of the first metal disk, which is the same or larger than a lateral size of the semiconductor wafer, even if the semiconductor wafer is sandwich between the first metal disk and a second metal disk having a smaller lateral size than the semiconductor wafer under pressure. Moreover the lateral size of the first metal disk which is the same or larger than a lateral size of the semiconductor wafer ensures an efficient removal of heat from the semiconductor wafer in particular in a circumferential edge region of the semiconductor wafer.

In the power semiconductor device of the invention the interface between the first metal disk and the semiconductor wafer is a free floating interface, i.e. the first metal disk is neither bonded nor brazed nor soldered to the first main side of the semiconductor wafer so that the first metal disk can slide along the first main side when laterally expanding due to heating up during operation of the power semiconductor device. This can reduce the compressive or tensile stress generated in the first metal disk and in the semiconductor wafer during a temperature change. Avoiding any bonding, brazing or soldering process can avoid wafer bow or deformation. Also, avoiding any bonding, brazing or soldering process can avoid the risk of particle generation on the semiconductor wafer in the junction termination area. Accordingly, the risk of device failure due to conductive particles on a junction termination of a semiconductor wafer can be reduced.

In the invention the first metal disk is a molybdenum or tungsten disk. Molybdenum and tungsten have a coefficient of thermal expansion that is close to the coefficient of thermal expansion of common semiconductor materials such as silicon or silicon carbide.

In the invention a metal layer is sandwiched between the first metal disk and the semiconductor wafer, the metal layer having a melting point below <NUM>, exemplarily below <NUM>, exemplarily below <NUM>. Such metal layer improves the thermal and electrical coupling (i.e. it boosts the interface conductivity) between the semiconductor wafer and the first metal disk to reduce on-state losses and improve removal of heat during device operation.

In an exemplary embodiment the material of the protection layer is a thermosetting polymer material. A thermosetting polymer can be molded by transfer molding. Transfer molding has the advantage compared to other molding techniques that the viscosity of the thermosetting polymer during the transfer molding process is relatively high so that the thermosetting polymer does not easily enter into a gap between the first main side of the semiconductor wafer and the first metal disk. Other advantages of transfer molding compared to other molding techniques, such as injection molding, are relatively low molding equipment costs, short cycle time, and low tool maintenance costs.

In an exemplary embodiment the material of the protection layer is an epoxy or a hybrid epoxy imide compound polymer. Such materials have a low shrinkage, low water absorption, good adhesion to diamond like carbon (DLC), nickel (Ni), ruthenium (Ru), silicon (Si) surfaces, small elastic modulus, low coefficient of thermal expansion close to that of silicon and molybdenum resulting in a low build-in stress after the manufacturing process. These properties allow the protection layer to hermetically seal and protect a wafer surface of the junction termination.

In another exemplary embodiment the protection layer is made of a rubber, exemplarily a silicone rubber. Rubber and in particular silicone rubber has good electrical insulation effect and is resistant against high operation temperatures.

In an exemplary embodiment the power semiconductor device comprises a passivation layer formed on the second main side to cover the junction termination, wherein the protection layer hermetically seals the passivation layer.

In an exemplary embodiment the first metal disk is fixed to the semiconductor wafer by the protection layer, which is fixed to the semiconductor wafer and to the first metal disk. Fixing the first metal disk to the semiconductor wafer by the protection layer, which is fixed to the semiconductor wafer and to the first metal disk, is a reliable fixing technique. In an exemplary embodiment the protection layer seals the interface between semiconductor wafer and the first metal disk against an atmosphere surrounding the power semiconductor device. Exemplarily the protection layer is fixed or glued to a side surface of first metal disk and/or to a circumferential edge portion of an upper surface of the first metal disk, wherein the upper surface of the first metal disk faces towards the semiconductor wafer.

In an exemplary embodiment the power semiconductor device comprises a second metal disk arranged on the second main side of the semiconductor wafer, wherein an interface between the second metal disk and the semiconductor wafer is a free floating interface, i.e. the second metal disk is neither bonded nor brazed nor soldered to the second main side of the semiconductor wafer so that the second metal disk can slide along the second main side when laterally expanding due to heating up during device operation. As discussed above for the free floating interface between the first metal disk and the semiconductor wafer, the free floating interface between the second metal disk and the semiconductor wafer can likewise reduce compressive or tensile stress generated in the second metal disk and in the semiconductor wafer during a temperature change. Avoiding any bonding, brazing or soldering process can avoid wafer bow or deformation. Also, avoiding any bonding, brazing or soldering process can avoid the risk of particle generation on the semiconductor wafer in the junction termination area, and reduce the manufacturing costs. Accordingly, the risk of device failure due to conductive particles on a junction termination of a semiconductor wafer can be further reduced.

In an exemplary embodiment the second metal disk is a molybdenum or tungsten or silver disk. Molybdenum and tungsten have a coefficient of thermal expansion that is close to the coefficient of thermal expansion of common semiconductor materials such as silicon or silicon carbide, while silver has a relatively high electrical conductivity.

In an exemplary embodiment the metal layer may be a layer of an eutectic alloy based on Gallium (Ga), which eutectic alloy remains liquid at room temperature (e.g. <NUM>) and under device operation, for example an eutectic alloy of GaIn, GaInSn. and GaInZn. The metal layer may also be a layer of any one of gallium (Ga), indium (In) (not falling within the scope of the claimed invention), cesium (Cs), rubidium (Rb) and their alloys, likewise the metal layer may be a layer of any alloy of tin (Sn), bismuth (Bi), lead (Pb) and cadmium (Cd), or any alloy of aluminum (Al), gallium (Ga), indium (In), thallium, (Tl), or mixtures and alloys thereof.

In an exemplary embodiment a thickness of the metal layer is in a range from <NUM> to <NUM>, exemplarily from <NUM> to <NUM>.

In an exemplary embodiment of a method for manufacturing a power semiconductor device according to the invention the protection layer may exemplarily be formed by transfer molding.

Detailed embodiments will be explained below with reference to the accompanying figures, in which:.

The reference signs used in the figures and their meanings are summarized in the list of reference signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention. It is to be note that only the second embodiment is described with all features of the claimed invention, whereas the other embodiments describe not all features of the invention but only aspects of the claimed invention. In particular the first, and third to sixth embodiment are described without the metal layer <NUM>.

In the following a power semiconductor device <NUM> according to a first embodiment is described with reference to <FIG>. The power semiconductor device <NUM> according to the first embodiment is a press-pack type device comprising a semiconductor wafer <NUM>, a first metal disk <NUM>, a second metal disk <NUM>, a first pole piece <NUM>, a second pole piece <NUM> and a housing <NUM>. The semiconductor wafer <NUM> has a first main side <NUM>, a second main side <NUM> opposite to the first main side <NUM>, and a lateral side <NUM> connecting the first main side <NUM> and the second main side <NUM>.

In an orthogonal projection onto a plane parallel to the first main side <NUM>, the semiconductor wafer <NUM> has an active region AR in a central area of the semiconductor wafer <NUM> and a junction termination region TR that extends along a circumferential edge of the semiconductor wafer <NUM> to laterally surround the active region AR. Therein, any direction parallel to the first main side is a lateral direction. At least one junction <NUM> is formed in the active region AR of the semiconductor wafer <NUM>. Depending on the type of the power device that is implemented by the semiconductor wafer, the at least one junction <NUM> may include a pn junction and/or a Schottky junction. In the termination region TR a junction termination is formed at the second main side <NUM> of the semiconductor wafer <NUM>. The semiconductor wafer may be made of any semiconductor material appropriate for power semiconductor devices, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminium nitride (AlN), aluminium gallium nitride (AlGaN) or the like.

In the first example illustrated in <FIG> the junction termination is exemplarily shown as a single-side single negative bevel. A passivation layer <NUM> which is exemplarily made of an insulating material, such as silicon oxide, silicon nitride, aluminium oxide, polyimide, or, which is made of a semi-insulating material like diamond like carbon (DLC), is formed on the semiconductor wafer <NUM> in a circumferential edge for surface passivation of the semiconductor wafer in the area of the junction termination. In addition to a relatively thin passivation layer made from silicon oxide, silicon nitride or diamond like carbon (DLC), for example, a protection layer <NUM> made of a molded material that is arranged to cover the lateral side <NUM> and the second main side <NUM> at least in the termination region TR of the semiconductor wafer <NUM>. The protection layer <NUM> is arranged to overlap a metallization layer (not shown) acting as first main contact that is arranged on the second main side <NUM> of the semiconductor wafer <NUM> in the active region AR, such that the junction termination including the passivation layer <NUM> is hermetically sealed from the surrounding atmosphere.

The material of the protection layer <NUM> may exemplarily be a thermosetting polymer, an epoxy or a hybrid epoxy imide compound polymer, or a rubber such as a silicone rubber. The epoxy mold compound material may be made out of multifunctional resins such as multi-aromatic ring resin (MAR) and biphenyl aralkyl structures, naphthalen and fluorene structures, or alternative resins and co-polymer systems, such as bismaleimide, cyanate ester, polyimide or silicone.

In the first example the first metal disk <NUM> is fixed or glued to the semiconductor wafer <NUM> by the protection layer <NUM> which is fixed or glued to the lateral side <NUM> of the semiconductor wafer <NUM> and to the second main side <NUM> in the termination region TR of the semiconductor wafer <NUM>, and also to a lateral side surface <NUM> of the first metal disk <NUM>. Likewise, the second metal disk <NUM> is fixed or glued to the semiconductor wafer <NUM> by the protection layer <NUM> which is fixed or glued to the lateral side surface <NUM> of the second metal disk <NUM>. With the protection layer <NUM>, which is fixed or glued to the semiconductor wafer <NUM> and to the lateral side surface <NUM> of the first metal disk <NUM>, the protection layer <NUM> seals the interface between semiconductor wafer <NUM> and the first metal disk <NUM> efficiently against an atmosphere surrounding the power semiconductor device <NUM>.

The first metal disk <NUM> and the second metal disk <NUM> are exemplarily molybdenum (Mo) or tungsten (W) disks, which have a coefficient of thermal expansion close to that of common semiconductor materials such as silicon (Si) or silicon carbide (SiC). The first metal disk <NUM> from Mo can be eventually combined with the second metal disk <NUM> from silver (Ag), which has the highest electrical conductivity. In an orthogonal projection onto a plane parallel to the first main side <NUM>, the semiconductor wafer <NUM>, the first metal disk <NUM> and the second metal disk <NUM> have a circular shape. The first and the second metal disks may be covered by an oxidation protection layer such as a ruthenium (Ru) layer. In the first example the first metal disk <NUM> has a diameter d<NUM>, which is a lateral size of the first metal disk <NUM>, that is the same as a diameter dW of the semiconductor wafer <NUM>, which diameter dW is a lateral size of the semiconductor wafer <NUM>. The first metal disk <NUM> is arranged on the first main side <NUM> to cover the first main side <NUM> of the semiconductor wafer <NUM>, i.e. to overlap in an orthogonal projection onto a plane parallel to the first main side <NUM> with the whole first main side <NUM> of the semiconductor wafer <NUM>.

The interface between the first metal disk <NUM> and the semiconductor wafer <NUM> is a free floating interface, i.e. the first metal disk <NUM> is neither bonded nor brazed nor soldered to the first main side <NUM> of the semiconductor wafer <NUM> so that the first metal disk <NUM> can slide along the second main side <NUM> when laterally expanding due to heating up during operation of the power semiconductor device <NUM>. In the first example the first metal disk <NUM> (which may include an oxidation protection layer as discussed above) may be in direct electrical and physical contact with a metallization layer on the first main side <NUM> of the semiconductor wafer <NUM>, which metallization layer acts as a second main contact.

The power semiconductor device <NUM> according to the first example comprises a housing <NUM> including a ceramic housing portion 6a.

In the following a power semiconductor device <NUM> according to a second example is described with reference to <FIG>. Due to the many similarities between the first and the second example, only differences between these two examples will be described.

With regard to all other features it is referred to the above discussion of the first example. In particular, elements having the same reference sign shall refer to elements having the same characteristics and features as the elements described above for the first example.

The power semiconductor device <NUM> according to the second example differs from that according to the first example in that a metal layer <NUM> is sandwiched between the first metal disk <NUM> and the semiconductor wafer <NUM>, the metal layer <NUM> having a melting point below <NUM>, exemplarily below <NUM>, more exemplarily below <NUM>. The metal layer <NUM> may include any one of Liquid Metal Thermal Interfaces (LMTI). It can be an eutectic alloy based on Gallium (Ga), for example eutectics of GaIn, GaInSn. and GaInSnZn. It can also be gallium (Ga), indium (In) (not falling within the scope of the claimed invention), cesium (Cs), rubidium (Rb) and their alloys likewise the alloys of tin (Sn), bismuth (Bi), lead (Pb) and cadmium (Cd), or alloys of aluminum (Al), gallium (Ga), indium (In), thallium, (Tl), or mixtures and alloys thereof. A thickness of the metal layer <NUM> is in a range from <NUM> to <NUM>, exemplarily from <NUM> to <NUM>. The metal layer <NUM> improves the thermal and electrical contact between the first metal disk <NUM> and the semiconductor wafer <NUM> resulting in a more efficient heat removal and lower on-state losses of the power semiconductor device <NUM>, while during operation the metal layer <NUM> may be in a liquid state to reduce compressive or tensile stress in the semiconductor wafer <NUM> and the first metal disk <NUM> due to different coefficients of thermal expansion of the semiconductor wafer <NUM> and the first metal disk <NUM>. With the protection layer <NUM> being fixed or glued to the semiconductor wafer <NUM> and to the lateral side surface <NUM> of the first metal disk <NUM>, the protection layer <NUM> efficiently encapsulates the metal layer <NUM> and prevents any leakage of material of the metal layer <NUM> in a liquid state.

In the following a power semiconductor device <NUM> according to a third example is described with reference to <FIG>. Due to the many similarities between the first and the third example, only differences between these two embodiments will be described in the following. With regard to all other features it is referred to the above discussion of the first example. The power semiconductor device <NUM> differs from the power semiconductor device <NUM> in that first metal disk <NUM> is not fixed or glued to the semiconductor wafer <NUM> by the protection layer <NUM>. Accordingly, the protection layer <NUM> differs from the protection layer <NUM> in that it is not fixed or glued to the lateral side surface <NUM> of the first metal disk <NUM>. In <FIG> this difference is reflected by a gap 28a between the lateral side surface <NUM> of the first metal disk <NUM> and the protection layer <NUM>. Likewise, in contrast to the power semiconductor device <NUM>, the protection layer <NUM> is also not fixed or glued to the lateral side surface <NUM> of the second metal disk <NUM>, which is separated from the protection layer <NUM> by a gap 28b in <FIG>. With regard to all other characteristics or features, the protection layer <NUM> may be the same as the above discussed protection layer <NUM> in the first example.

The power semiconductor <NUM> is most suitable for a power device that requires ion and/or electron irradiation after a device processing including forming the protection layer is completed.

In the following a power semiconductor device <NUM> according to a fourth example is explained with reference to <FIG>. Due to the many similarities between the first and the fourth example, only differences between these two examples will be described in the following. With regard to all other features it is referred to the above discussion of the first example.

The power semiconductor device <NUM> differs from the above discussed power semiconductor device <NUM> in that the protection layer <NUM> is fixed or glued only to a portion 23a of the lateral side surface <NUM> of the first metal disk <NUM> as shown in <FIG>. A lower portion 23b of the lateral side surface <NUM> of the first metal disk <NUM> is not fixed or glued to the protection layer <NUM>. In all other aspects the protection layer <NUM> is the same as the protection layer <NUM> of the power semiconductor device <NUM> shown in <FIG>.

In the following a power semiconductor device <NUM> according to a fifth example is explained with reference to <FIG>. Due to the many similarities between the first and the fifth example, only differences between these two examples will be described in the following. With regard to all other features it is referred to the above discussion of the first example.

The power semiconductor device <NUM> differs from the above discussed power semiconductor device <NUM> in that the first metal disk <NUM> has a diameter d<NUM>', which is a lateral size of the first metal disk <NUM>, that is larger than a diameter dW of the semiconductor wafer <NUM>, which is a lateral size of the semiconductor wafer <NUM>. Likewise, also the first pole piece <NUM> has a larger diameter in the fifth example than that of the first pole piece <NUM> in the first example. Due to the larger diameter d<NUM>' of the first metal disk <NUM> compared to that of the semiconductor wafer <NUM>, the protection layer <NUM> is fixed or glued not only to a lateral side surface <NUM> of the first metal disk <NUM> but also to a circumferential edge portion of an upper side <NUM> of the first metal disk <NUM>. The larger diameter d<NUM>' > dW improves the removal of heat during operation of the power semiconductor device <NUM>. The other characteristics and features of the first metal disk <NUM>, the first pole piece <NUM> and the protection layer <NUM> are the same as that of the first metal disk <NUM>, the first pole piece <NUM> and the protection layer <NUM> in the first example, respectively.

In the following a power semiconductor device <NUM> according to a sixth example is explained with reference to <FIG>. Due to the many similarities between the fifth and the sixth example, only differences between these two examples will be described in the following. With regard to all other features it is referred to the above discussion of the fifth example.

Like in the above discussed power semiconductor device <NUM> the power semiconductor device <NUM> has a first metal disk <NUM> that has a diameter d<NUM>", which is a lateral size of the first metal disk <NUM>, that is larger than a diameter dW of the semiconductor wafer <NUM>, which is a lateral size of the semiconductor wafer <NUM>. Likewise, also the first pole piece <NUM> has a larger diameter in the sixth example than that of the first pole piece <NUM> in the first example.

Contrary to the protection layer <NUM> in the fifth example, the protection layer <NUM> in the sixth example is fixed or glued only to a circumferential edge portion of an upper side <NUM> of the first metal disk <NUM>, but not to a lateral side surface <NUM> of the first metal disk <NUM>. The relatively large diameter d<NUM>" > dW improves the removal of heat during operation of the power semiconductor device <NUM>. The other characteristics and features of the first metal disk <NUM>, the first pole piece <NUM> and the protection layer <NUM> are the same as that of the first metal disk <NUM>, the first pole piece <NUM> and the protection layer <NUM> in the fifth embodiment, respectively.

In another comparative example which is also not covered by the appended claims a power semiconductor device is provided that is the same as the power semiconductor device according to the sixth example except that the first metal disk <NUM> is bonded to the semiconductor wafer <NUM> by bonding or brazing.

In an exemplary method for manufacturing a power semiconductor device <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> according to anyone of the above discussed examples, the protection layer <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be formed by transfer molding. In this case the protection layer <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be made of a thermosetting polymer. Transfer molding has the advantage compared to other molding techniques that the viscosity of the thermosetting polymer during the transfer molding process is relatively high.

Accordingly, the use of transfer molding is in particular advantageous for the manufacture of power semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM> where the first metal disk <NUM>, <NUM>, <NUM> and/or second metal disk <NUM> is fixed or glued to the protection layer <NUM>, <NUM>, <NUM>, <NUM> as in the above examples shown in <FIG>, <FIG>, and <FIG>. A high viscosity of the thermosetting polymer results in that the polymer does not easily enter into a gap between the first metal disk <NUM>, <NUM> and the semiconductor wafer <NUM> and/or into a gap between the second metal disk <NUM> and the semiconductor wafer <NUM> during the molding process. Other advantages of transfer molding compared to other molding techniques, such as injection molding, are relatively low molding equipment costs, short cycle time, and low tool maintenance costs.

In the above examples either the protection layer <NUM> is fixed or glued to none of the first metal disk <NUM> and the second metal disk <NUM> as in the third example shown in <FIG>, or the protection layer <NUM>, <NUM>, <NUM>, <NUM> is fixed or glued to both, to the first metal disk <NUM> and to the second metal disk <NUM> as in the remaining examples shown in <FIG>, <FIG>, and <FIG>. However, the protection layer may also be glued or fixed to only one of the first and the second metal disks.

In the above examples the power semiconductor device <NUM>, <NUM>, <NUM>, <NUM>, <NUM><NUM> included a housing <NUM>. However, the power semiconductor device may not include the housing. Exemplarily the power semiconductor may be a housing less power semiconductor device.

In the above examples the power semiconductor device included the first and the second pole piece and the second metal disk. However, each of these elements is an optional feature and the power semiconductor device may not include these elements.

In the above examples the semiconductor wafer <NUM>, the first metal disk <NUM>, <NUM>, <NUM> and the second metal disk <NUM> are described to have a circular shape (in an orthogonal projection onto a plane parallel to the first main side), respectively. Accordingly, a single diameter was used to characterize a lateral size of the first metal disk <NUM>, the second metal disk <NUM> and the semiconductor wafer <NUM>, respectively. However, the invention is not limited to such a specific shape of the semiconductor wafer <NUM>, the first metal disk <NUM> and the second metal disk <NUM>. In general the shape of first metal disk <NUM>, the second metal disk <NUM> and the semiconductor wafer <NUM> may be any shape, and the lateral size of the first metal disk <NUM>, the second metal disk <NUM> and the semiconductor wafer <NUM> may respectively depend on the lateral direction, i.e. may be different for two different lateral directions. In such generalized case the lateral dimension of the first metal disk <NUM> is the same or larger in any lateral direction. For example the shape of the semiconductor wafer and that of the first metal disk may be a rectangular shape having a short side and a long side, respectively, wherein the short side of the semiconductor wafer is parallel to the short side of the first metal disk and the long side of the semiconductor wafer is parallel to the long side of the first metal disk. In this exemplary case a length of the shorter side of the first metal disk shall be the same or larger than that of the semiconductor wafer, and a length of the longer side of the first metal disk shall be the same or larger than that of the semiconductor wafer.

In the above examples illustrated in <FIG> the junction termination is exemplarily shown as a single-side single positive bevel. However, the invention is not limited to any specific kind of junction termination as long as the junction termination is arranged along the circumferential edge of the semiconductor wafer. The junction termination may exemplarily include single-side single negative bevel, single positive bevel, double positive bevel, combined positive-negative bevel, or a planar junction termination such as junction termination extension (JTE), a variation of lateral doping (VLD) and floating field ring terminations (FFR) with and without field plate extensions.

In the above second example shown in <FIG> a metal layer <NUM> is sandwiched between the first metal disk <NUM> and the semiconductor wafer <NUM>. A metal layer having the same characteristics as the metal layer <NUM> may also be sandwiched between the second metal disk <NUM> and the semiconductor wafer <NUM> of each one of the above embodiments. Such metal layer sandwiched between the second metal disk <NUM> and the semiconductor wafer <NUM> could be encapsulated efficiently with the protection layer <NUM> being fixed or glued to the semiconductor wafer <NUM> and to the lateral side surface <NUM> of the second metal disk <NUM>, so that leakage of material of such metal layer in a liquid state could be prevented.

Claim 1:
A power semiconductor device, comprising:
a semiconductor wafer (<NUM>) having a first main side (<NUM>), a second main side (<NUM>) opposite to the first main side (<NUM>), a lateral side (<NUM>) connecting the first main side (<NUM>) and the second main side (<NUM>), at least one junction (<NUM>) and a junction termination laterally surrounding the at least one junction (<NUM>);
a protection layer (<NUM>; <NUM>; <NUM>; <NUM>; <NUM>) covering the lateral side (<NUM>) of the semiconductor wafer (<NUM>) and covering the second main side (<NUM>) at least in an area (TR) of the junction termination,
a first metal disk (<NUM>; <NUM>; <NUM>) which has a lateral size (d<NUM>; d<NUM>'; d<NUM>") that is the same as or larger than a lateral size (dW) of the semiconductor wafer (<NUM>), wherein the first metal disk (<NUM>; <NUM>; <NUM>) is arranged on the first main side (<NUM>) to cover the first main side (<NUM>) of the semiconductor wafer (<NUM>),
wherein the first metal disk (<NUM>; <NUM>; <NUM>) is a molybdenum or tungsten disk,
wherein an interface between the first metal disk (<NUM>; <NUM>; <NUM>) and the semiconductor wafer (<NUM>) is a free floating interface, and
wherein a metal layer (<NUM>) is sandwiched between the first metal disk (<NUM>; <NUM>; <NUM>) and the semiconductor wafer (<NUM>), the metal layer (<NUM>) having a melting point below <NUM>, exemplarily below <NUM>.