Patent Description:
Image sensors in solid-state imaging devices include photoelectric conversion elements generating a photocurrent in proportion to the received radiation intensity. The main function of a pixel circuit is to transform the small photocurrent generated by the photoelectric conversion element into a comparatively large output voltage which a downstream analog-to-digital converter converts into a digital signal. The current-to-voltage transformation can be done by integrating the photocurrent on an electrode of an integration capacitor during a fixed time period (integration time). The integration capacitor voltage at the end of the integration time is approximately proportional to the incident radiation. A DI pixel circuit further includes an injection transistor used as current buffer to pass the photocurrent to the integration capacitor. <CIT> discloses a pumped large full well pixel, <CIT> discloses a buffered direct injection pixel.

Today, solid-state imaging devices are increasingly integrated in a multitude of battery-powered application systems, e.g. electric vehicles, in which low power consumption of the solid-state imaging device is of high interest. The present disclosure has been made in view of the above circumstances, and it is therefore desirable to provide a pixel circuit and a solid-state imaging device combining low power consumption with high dynamic range.

According to an embodiment, a pixel circuit according to claim <NUM> includes a photoelectric conversion circuit, an integration capacitor and a supplementary circuit. The photoelectric conversion circuit is configured to generate and output a photocurrent. The integration capacitor includes a storage electrode and a reference electrode. The reference electrode is connected to a first supply potential. The integration capacitor is configured to integrate the photocurrent on the storage electrode in an integration period. The supplementary circuit is configured to pre-charge a working node between the photoelectric conversion circuit and the storage electrode to a pre-charge potential that differs from the first supply potential.

According to another embodiment, a solid-state imaging device according to claim <NUM> includes a pixel array unit that includes a plurality of pixel circuits, wherein each pixel circuit includes a photoelectric conversion circuit, an integration capacitor and a supplementary circuit. The photoelectric conversion circuit is configured to generate and output a photocurrent. The integration capacitor includes a storage electrode and a reference electrode. The reference electrode is connected to a first supply potential. The integration capacitor is configured to integrate the photocurrent on the storage electrode in an integration period. The supplementary circuit is configured to pre-charge a working node between the photoelectric conversion circuit and the storage electrode to a pre-charge potential that differs from the first supply potential.

In the following, a technology for increasing the dynamic range of pixel circuits without significant increase of power consumption is described in the context of certain types of active image sensors. The technology may also be used for other types of sensors.

<FIG> illustrates a configuration example of a solid-state imaging device <NUM> according to an embodiment of the present technology.

The solid-state imaging device <NUM> includes a pixel array unit <NUM>, a row decoder <NUM>, a row driver unit <NUM>, a pixel read-out unit <NUM>, a controller <NUM>, and a processing unit <NUM>.

The pixel array unit <NUM> includes a plurality of pixel circuits <NUM>. Each pixel circuit <NUM> includes a photoelectric conversion element PD and one or more FETs (field effect transistors) for controlling the output signal of the photoelectric conversion element PD. The photoelectric conversion elements PD may be arranged matrix-like in rows and columns.

The photoelectric conversion elements PD may be photodiodes capable of being operated in a proportional mode or APDs (avalanche photodiodes), i.e. photodiodes capable of being operated in an avalanche mode. Each pixel circuit <NUM> may be capable of operating the photoelectric conversion element PD as intensity output pixel, as DVS (dynamic vision sensor) pixel or as APD, e.g. as SPAD (single photon avalanche detection) pixel for event detection.

Each pixel circuit <NUM> may include at least one amplifying circuit and may generate one or more pixel output signals pix_out. A pixel output signal pix_out may contain a voltage signal proportional to the intensity of the radiation received by the photoelectric conversion element PD. Alternatively or in addition, the pixel output signal pix_out may indicate a change of the radiation intensity detected by the photoelectric conversion element PD. Alternatively or in addition, the pixel output signal pix_out may indicate an event detected by the pixel circuit <NUM>. For example, the pixel circuit <NUM> may be configured to be operated as the sensor side of a ToF (time-of-flight) sensor.

The row decoder <NUM> and the row driver unit <NUM> control selection and driving of the pixel circuits <NUM> in the pixel array unit <NUM>. That is, the row decoder <NUM> supplies a control signal for designating the pixel circuit <NUM> or a row of pixel circuits <NUM> to be driven or the like to the row driver unit <NUM> according to an address signal and/or a latch signal supplied from the controller <NUM>. The row driver unit <NUM> supplies and controls the FETs of the pixel circuit <NUM> according to driving timing signals supplied from the controller <NUM> and the control signals supplied from the row decoder <NUM>. Vertical signal lines VSL pass the pixel output signals of the pixel circuits <NUM> to the pixel read-out unit <NUM>, wherein each vertical signal line VSL may be connected to all pixel circuits <NUM> of one column of the pixel array unit <NUM>.

The pixel read-out unit <NUM> may facilitate frame-based imaging based on the use of a fixed capture interval. For frame-based imaging, a region of interest (ROI) of the pixel array or the entire array of pixels may be read out at every frame. Alternatively or in addition, the pixel read-out unit <NUM> may facilitate asynchronous readouts, which may also be referred to herein as event-driven readouts. Based on the pixel output signals received through the vertical signal lines VSL, the pixel readout unit <NUM> generates frame-based and/or event-based digital image information and outputs the digital image information to a signal processing unit <NUM>. The signal processing unit <NUM> may further process the digital image information and may pass the digital image information to another device.

<FIG> shows details of one of the pixel circuits <NUM> shown as part of the pixel array unit <NUM> of <FIG>.

The pixel circuit <NUM> includes a photoelectric conversion circuit <NUM>, an integration capacitor Cint, and a supplementary circuit <NUM>. The photoelectric conversion circuit <NUM> generates and outputs a photocurrent Iphoto. The integration capacitor Cint includes a storage electrode CintS and a reference electrode CintR. The storage electrode CintS integrates the photocurrent Iphoto in an integration period. In other words, the storage electrode CintS is charged or discharged in response to the photocurrent Iphoto, wherein the storage electrode CintS may be directly or capacitively coupled to the photocurrent Iphoto. In particular, the charge on the storage electrode CintS is a function, e.g. an approximately linear function of the photocurrent Iphoto.

The reference electrode CintR is connected to a first supply potential VSUP1. The supplementary circuit <NUM> precharges a working node WN between the photoelectric conversion circuit <NUM> and the storage electrode CintS to a pre-charge potential different from the first supply potential VSUP1.

The photoelectric conversion circuit <NUM> may include a photoelectric conversion element PD. The photoelectric conversion element PD may be a photodiode sensitive to electromagnetic radiation of a predetermined wavelength range, e.g. for a portion of the wavelength range for visible light and/or for infrared radiation. A supply electrode of the photoelectric conversion element PD is electrically connected to a second supply potential VSUP2. The photoelectric conversion circuit <NUM> may include further elements and/or circuits for stabilizing, buffering, and/or amplifying the photocurrent signal output by the photoelectric conversion element PD.

Each of the electrodes of the integration capacitor Cint may include a doped diffusion region formed in a semiconductor substrate, a metal structure, or a metal-like semiconductor structure of heavily doped semiconductor material.

The supplementary circuit <NUM> includes a circuit path electrically coupling the photoelectric conversion circuit <NUM> and the storage electrode CintS of the integration capacitor Cint, wherein the circuit path may include one or more elements electrically connected in series between the photoelectric conversion circuit <NUM> and the storage electrode CintS. In addition, the supplementary circuit <NUM> may include one or more elements with one side electrically connected to a supply voltage or to a reference voltage, by way of example. The supplementary circuit <NUM> is controllable through one or more supplementary control signals <NUM>.

An operation cycle of the pixel circuit <NUM> includes a pre-charge period and an integration period. The pre-charge period sets the potential at the storage electrode CintS to a predefined level with respect to the potential at the reference electrode CintR. In the integration period the photocurrent is integrated on the integration capacitor Cint. That is, the voltage across the integration capacitor Cint follows the photo current. The output voltage Vout across the integration capacitor Cint is a function of the photocurrent, which is proportional to the intensity of the received radiation, and of the integration time.

The dynamic range of the pixel circuit <NUM> is given by the maximum possible voltage swing for the output voltage Vout. The upper limit for the output voltage Vout is basically given by the difference between the first and second supply potentials VSUP1, VSUP2 and the required bias for operating the photoelectric conversion element PD. The lower limit is given by the minimum potential between the photoelectric conversion circuit <NUM> and the storage electrode CintS at the beginning of the integration period.

Conventionally, pre-charging includes discharging an integration capacitor Cint by short-circuiting the reference electrode CintR and the storage electrode CintS, wherein the storage-electrode is pre-charged with the first supply potential VSUP1.

By contrast, with the supplementary circuit <NUM> it is possible to pre-charge the working node WN between the photoelectric conversion element and the storage electrode CintS with a potential that differs from the first supply potential VSUP1.

This facilitates an increased voltage swing for the output voltage Vout. The increased voltage swing for the output voltage Vout increases the dynamic range of the pixel circuit <NUM>.

The pre-charge potential Vpre can be selected such that a first potential difference V1 between a second supply potential VSUP2 at a supply electrode of the photoelectric conversion circuit <NUM> and the pre-charge potential Vpre is greater than a second potential difference V2 between the second supply potential VSUP2 and the first supply potential VSUP1.

The polarity of the pre-charge potential Vpre with respect to the first supply potential VSUP1 depends on the way the photoelectric conversion circuit <NUM> and the integration capacitor Cint are connected between a positive and a negative supply potential.

In <FIG> the first supply potential VSUP1 at the reference electrode CintR is a supply reference potential GND, and the second supply potential VSUP2 at the supply electrode of the photoelectric conversion circuit <NUM> is defined by a positive supply voltage VDD with reference to the supply reference potential GND. The photoelectric conversion circuit <NUM> is in a high-side configuration with a supply electrode electrically connected to the positive supply voltage VDD. During the integration period Tint, the integration capacitor Cint integrates the photocurrent Iphoto at the storage electrode CintS. The pre-charge potential Vpre can be selected to be negative with respect to the supply reference potential GND.

The output voltage Vout is the effective voltage across the integration capacitor Cint. When the pixel circuit <NUM> is selected, a controllable pixel output circuit <NUM> may pass the output voltage Vout as pixel output signal pix_out to a vertical signal line VSL. The pixel output circuit <NUM> may buffer and/or amplify the output voltage Vout. For example, the pixel output circuit <NUM> may include an FET in source follower configuration. Alternatively or in addition, the pixel output circuit <NUM> may include a selection transistor. Alternatively or in addition, the pixel output circuit <NUM> may include an event detection circuit detecting a change between the current output voltage level against a previous output voltage level.

<FIG> shows the time chart for the voltage Vb at the working node WN of the pixel circuit <NUM> in <FIG>. Each operation cycle includes a pre-charge period Tpre and an integration period Tint directly following the pre-charge period Tpre.

At the end of the pre-charge period Tpre the voltage Vb at the working node WN is set to the pre-charge voltage Vpre, which can be more negative than the supply reference potential GND.

The supplementary circuit <NUM> may be configured such that during the integration period Tint the storage electrode CintS is capacitively coupled to the photocurrent Iphoto. In other words, the photocurrent Iphoto may charge/discharge the storage electrode CintS by capacitive coupling. Further components of the supplementary circuit <NUM> can be decoupled from the integration capacitor Cint in a way that the components of the supplementary circuit <NUM> do not affect the rise of the voltage Vb at the working node WN within the integration period Tint.

In <FIG>, the second supply potential VSUP2 at the supply electrode of the photoelectric conversion circuit <NUM> is a supply reference potential GND and the first supply potential VSUP1 at the reference electrode CintR is defined by a positive supply voltage VDD with reference to the supply reference potential GND. The photoelectric conversion circuit <NUM> is in a low-side configuration with a supply electrode electrically connected to the supply reference potential GND. The photocurrent gradually discharges the storage electrode CintS of the integration capacitor Cint in the integration mode. The pre-charge potential Vpre can be selected to be more positive than the positive supply voltage VDD.

<FIG> shows the time chart for the voltage Vb at the working node WN of the pixel circuit <NUM> in <FIG>. At the end of a pre-charge period Tpre the voltage Vb at the working node WN is set to the pre-charge voltage Vpre, which can be more positive than the supply voltage VDD.

The supplementary circuit <NUM> pre-charges the working node WN by capacitor switching. In other words, the supplementary circuit <NUM> includes a switched capacitor circuit including switches and capacitors. Each switch may be an electronic switch, e.g. an n-channel FET, a p-channel FET, or a transfer gate by way of example. Each capacitor may be or may include a parasitic capacitance and/or an explicit capacitor, wherein an explicit capacitor includes at least one electrode formed by a diffusion region, a metal structure, and/or a metal-like semiconductor structure serving no other purpose. A supplementary circuit <NUM> realized only or mainly by passive elements has only a low adverse effect on power consumption.

An auxiliary control unit may generate and drive one or more supplementary control signals for controlling the supplementary circuit <NUM>.

Referring again to <FIG>, the auxiliary control unit may be integrated in at least one of the row decoder <NUM>, the row driver, and the control unit <NUM> of the solid-state imaging device <NUM>. The supplementary control signals may address single supplementary circuits <NUM>, may address all supplementary circuits <NUM> of the same row at the same time, may address all supplementary circuits <NUM> of the same column at the same time, or may address the supplementary circuits <NUM> of all pixel circuits <NUM> at the same time.

<FIG> refer to an embodiment with a pixel circuit <NUM> of the (unbuffered) direct injection type, wherein the photoelectric conversion circuit <NUM> is in high-side configuration with the supply electrode connected to the positive supply voltage VDD.

In addition to the photoelectric conversion element PD that converts radiation into a photocurrent Iphoto, the photoelectric conversion circuit <NUM> includes a buffer transistor <NUM> with a load path electrically connected in series between the photoelectric conversion element PD and the working node WN.

The channel type of the buffer transistor <NUM> depends on the configuration of the photoelectric conversion element PD with respect to the integration capacitor Cint and the supply reference potential GND. In the illustrated example, the integration capacitor Cint is between the photoelectric conversion element PD and the supply reference potential GND such that the photoelectric conversion element PD is in a high-side configuration. The buffer transistor <NUM> is a pFET (p channel field effect transistor). In another example, the photoelectric conversion element PD may be in a low-side configuration with the integration capacitor Cint between the positive supply voltage VDD and the photoelectric conversion element PD. Then the buffer transistor <NUM> may be an nFET (n channel field effect transistor).

A fixed reference voltage VREF is supplied to the gate of the buffer transistor <NUM> which operates as current buffer to pass the photocurrent Iphoto to the integration capacitor Cint.

A voltage Vde at a detector node DE between the photoelectric conversion element PD and the load path of the buffer transistor <NUM> is equal to VREF reduced by the gate-to-source voltage VGS of the buffer transistor <NUM>. As a consequence, the bias across the photoelectric conversion element PD is not constant but depends on light intensity. On the other hand, the photoelectric conversion circuit <NUM> is comparatively compact and requires only little space and little electric power.

The supplementary circuit <NUM> includes an auxiliary capacitor Cb with a first electrode Cb1 and a second electrode Cb2. The first electrode Cb1 is electrically connected to the working node WN. The second electrode Cb2 of the auxiliary capacitor and the storage electrode CintS of the integration capacitor Cint are electrically connected to a center tap node CT. With the auxiliary capacitor Cb between the photoelectric conversion circuit <NUM> and the integration capacitor Cint, it is possible to shift the voltage swing at the working node WN with respect to the voltage swing for the output voltage Vout, which drops between the center tap node CT and the supply reference potential GND.

The supplementary circuit <NUM> is configured to pre-charge the working node WN by successively pre-charging, with the working node WN connected to the first supply voltage VSUP1 (e.g. supply reference potential GND), the center tap node with a tap potential, and connecting, with the working node WN disconnected from the first supply voltage VSUP1 (e.g., GND) the center tap node CT to the first supply voltage VSUP1 (e.g., GND). The tap potential may be positive with respect to the supply reference potential GND.

The tap potential may correspond to the positive supply voltage VDD at the supply electrode of the photoelectric conversion element PD or may correspond to a positive first auxiliary voltage VDDH that may be higher or lower than the positive supply voltage VDD at the supply electrode of the photoelectric conversion element PD.

The pre-charging of the center tap node CT with the tap potential generates a positive voltage across the auxiliary capacitor Cb in direction from the center tap node CT to the working node WN, which at the same time is on supply reference potential GND. By separating the working node WN from the supply reference potential GND and instead connecting the center tap node CT to the supply reference potential GND, the potential Vb at the working node is shifted to a potential lower than the supply reference potential GND by the tap potential and at the same time the output voltage Vout is initialized with the supply reference potential GND.

The supplementary circuit <NUM> may include a first switch <NUM> configured to electrically connect the working node WN and the reference electrode CintR in a first phase Tp1 of the pre-charge period Tpre, when the auxiliary capacitor Cb is charged with the center tap potential.

The first switch <NUM> is open in a second phase Tp2 of the pre-charge period Tpre when the reference potential for the auxiliary capacitor Cb is shifted. The first switch <NUM> is also open in the integration period Tint.

The supplementary circuit <NUM> may include a second switch <NUM> configured to electrically connect the center tap node CT to the second supply voltage VSUP2 in the first phase Tp1 of the pre-charge period. The second switch <NUM> is open in the second phase Tp2 of the pre-charge period Tpre, when the reference for the auxiliary capacitor Cb is shifted. The second switch <NUM> is also open in the integration period Tint.

The supplementary circuit <NUM> may include a third switch <NUM> configured to electrically connect the center tap node CT to the first supply voltage VSUP1 in the second phase Tp2 of the pre-charge period Tpre.

The third switch <NUM> is open in the first phase Tp1 of the pre-charge period and in the integration period.

The start of the second phase Tp2 may be slightly delayed with respect to the end of the first phase Tp1, in particular against the turn-off of the first switch <NUM>. In particular, a transition phase may separate the first phase Tp1 and the second phase Tp2, wherein the transition phase separates the switching edges of the first, second and third switches <NUM>, <NUM>.

<FIG> shows some signals for the pixel circuit <NUM> of <FIG>. Each operation cycle of the pixel circuit <NUM> includes a pre-charge period Tpre and an integration period Tint that may directly follow the pre-charge period Tpre.

A first phase Tp1 of the pre-charge period Tpre starts at t=t0. The first switch <NUM> and the second switch <NUM> are "on". The third switch <NUM> is "off". The potential Vb at the working node WN is set to the supply reference potential GND. The output voltage Vout between the storage electrode CintS and the supply reference potential GND is set to the first auxiliary voltage VDDH. The first phase Tp1 ends at t=t2.

A second phase Tp2 of the pre-charge period Tpre starts at t=t3. The first switch <NUM> and the second switch <NUM> are "off". The third switch <NUM> is "on". The potential Vb at the working node WN is shifted to below the supply reference potential by the first auxiliary voltage VDDH. The output voltage Vout between the storage electrode CintS and the supply reference potential GND is set to 0V.

The integration period Tint starts at t=t4 and ends at t=t0 of the next pre-charge period Tpre. The first switch <NUM>, the second switch <NUM>, and the third switch are "off". The equivalent capacitance at the working node WN is equal to Cint//Cb. The capacitance of Vout is equal to Cint. By accumulating the photocurrent with the effective capacitance, the voltage Vb between the wording node WN and the supply reference potential GND steadily increases starting from Vb = -VDDH. Accordingly the output voltage Vout steadily increases starting from Vout = 0V. Since the equivalent capacitance Cint//Cb at the working node WN is smaller than the capacitance of the integration capacitor Cint, the Vb slew rate is higher than the Vout slew rate. The output voltage Vout at the end of the integration period Tint is equal to (Iphoto*Tint)/Cint.

A capacitance of the auxiliary capacitor Cb may be approximately in same order of magnitude as the capacitance of the integration capacitor Cint. For example, the capacitance of the auxiliary capacitor Cb may be lower than the capacitance of the integration capacitor Cint. According to another example, the capacitance of the auxiliary capacitor Cb may be at least <NUM>% or at least <NUM>% of the capacitance of the integration capacitor Cint.

For a supply voltage VDD greater <NUM>. 0V, the capacitance of the auxiliary capacitor Cb may be at least as high as the capacitance of the integration capacitor Cint, e.g. at least twice as high.

For a supply voltage VDD below <NUM>. 2V, the capacitance of the auxiliary capacitor Cb may be at least <NUM>% the capacitance of the integration capacitor Cint, e.g. at least as high as the capacitance of the integration capacitor Cint.

The output voltage Vout voltage swing increases with increasing capacitance of the auxiliary capacitor Cb. At the same time, the capacitance of the integration capacitor Cint can be kept small and noise resulting from the integration capacitor Cint remains small.

<FIG> refer to buffered direct injection with the photoelectric conversion circuit <NUM> in high-side configuration.

The photoelectric conversion circuit <NUM> further includes an amplifier circuit <NUM> that controls the buffer transistor <NUM> to keep a bias voltage across the photoelectric conversion element PD constant for different photocurrents.

In particular, an inverting input of the amplifier circuit <NUM> may be electrically connected to an output of the photoelectric conversion element PD, a non-inverting input of the amplifier circuit <NUM> may be electrically connected to a reference voltage node VREF and an output of the amplifier circuit <NUM> controls the buffer transistor <NUM>. The amplifier circuit <NUM> may be or may include an operational amplifier.

In particular, by zeroing the input voltage between the inverting input and the non-inverting input, the amplifier circuit <NUM> biases the detector node DE between the photoelectric conversion element PD and the buffer transistor <NUM> via the virtual ground with the reference voltage VREF applied to the non-inverting input.

The time chart illustrated in <FIG> differs from the time chart in <FIG> in that the first phase Tp1 of the pre-charge period Tpre ends when the first switch <NUM> turns off at t=t1. In a transition phase separating the first phase Tp1 and the second phase Tp2 of the pre-charge period Tpre, the second switch <NUM> turns off at t=t2 after the first switch <NUM> has turned off and before the third switch <NUM> turns on at t=t3. The integration period Tint starts at t=t4 when the third switch <NUM> turns off.

Each of <FIG> shows the voltage Vde at the detector node DE, the voltage Vb at the working node WN and the output voltage Vout for a pixel circuit <NUM> as illustrated in <FIG>. The voltage reference VREF is selected such that a voltage across the reverse-biased photoelectric conversion element PD is <NUM>. The capacitance of the integration capacitor Cint is equal 10fF. The capacitance of the auxiliary capacitor Cb is equal 10fF. The photoelectric conversion element PD is irradiated at constant light intensity.

In <FIG> the supply voltage VDD is <NUM>. During the first phase Tp1 of the pre-charge period Tpre, the voltage Vb at the working node WN is 0V and the output voltage is approximately <NUM>. At the end of the second phase Tp2 of the pre-charge period Tpre, the voltage Vb at the working node WN is approximately -<NUM>. 7V and the output voltage is 0V.

As long as the combination of buffer transistor <NUM> and amplifier circuit <NUM> works properly within a predefined operating range, the voltage at the detector node DE is held at approximately 2V.

With start of the integration period Tint, the voltages Vb and Vout start to rise. At t=tX the voltage Vb at the working node reaches a level at which the buffer transistor <NUM> is no longer saturated such that the voltage at the detector node cannot longer be held at 2V. The bias across the photoelectric conversion element PD decreases and the detector node and the working node WN become increasingly shorted. The voltages Vb at the working node WN and the output voltage Vout increase at a reduced rate.

The output voltage Vout at t=tX is about <NUM>. The total voltage swing is about <NUM>.

In <FIG> the supply voltage VDD is <NUM>. Accordingly, during the first phase Tp1 of the pre-charge period Tpre, the voltage Vb at the working node WN is about 0V and the output voltage Vout is approximately <NUM>. At the end of the second phase Tp2 of the pre-charge period Tpre, the voltage Vb at the working node WN is approximately - <NUM>. 05V and the output voltage is about 0V.

As long as the combination of buffer transistor <NUM> and amplifier circuit <NUM> works properly within a predefined operating range, the voltage at the detector node DE is held at <NUM>.

When at t=tX the voltage Vb at the working node reaches a level at which the combination of buffer transistor <NUM> and amplifier circuit <NUM> cannot longer hold the voltage at the detector node at <NUM>. 35V, the output voltage Vout is approximately <NUM>. The total voltage swing is approximately <NUM>.

Each of <FIG> shows the voltage Vde at the detector node DE and the output voltage Vout for a comparative pixel circuit which differs from the pixel circuit <NUM> of <FIG> in that a direct connection between the storage electrode CintS of the integration capacitor Cint and the working node WN replaces the auxiliary capacitor Cb and in that a single switch short-circuits the electrodes of the integration capacitor Cint in the pre-charge period Tpre. The voltage reference VREF is selected such that voltage across the photoelectric conversion element PD is <NUM>. The capacitance of the integration capacitor Cint is 10fF. The photoelectric conversion element PD is irradiated at constant light intensity.

In <FIG> the supply voltage VDD is <NUM>. The output voltage Vout at t=tX is approximately <NUM>. The total voltage swing is approximately <NUM>.

In <FIG> the supply voltage VDD is <NUM>. The output voltage Vout at t=tX is approximately <NUM>. The total voltage swing is approximately <NUM>.

For a supply voltage VDD of <NUM>. 7V the supplementary circuit <NUM> increases the output voltage swing by about <NUM>%. For a supply voltage VDD of <NUM>. 05V the supplementary circuit <NUM> increases the output voltage swing by about <NUM>%. At the same time, the capacitance of the integration capacitor Cint can be kept small. Since noise increases with the size of the integration capacitor Cint, compared to a solution aiming at increasing the dynamic range by increasing the capacitance of the integration capacitor Cint, the supplementary circuit <NUM> does not or only to a lower degree increase the noise level.

<FIG> refer to buffered direct injection with the photoelectric conversion circuit <NUM> in low-side configuration, wherein a supply electrode of the photoelectric conversion circuit <NUM> is electrically connected to the supply reference potential GND.

The buffer transistor <NUM> is an nFET. The amplifier circuit <NUM> controls the buffer transistor <NUM> to keep a reverse bias voltage across the photoelectric conversion element PD constant for different photocurrent values. The reverse bias voltage may depend on type and material of the photoelectric conversion element PD and may be approximately <NUM>. 7V for a silicon photodiode, by way of example.

The reference electrode CintR of the integration capacitor Cint is electrically connected to the positive supply voltage VDD.

The supplementary circuit <NUM> includes an auxiliary capacitor Cb with a first electrode Cb1 and a second electrode Cb2. The first electrode Cb1 is electrically connected to the working node WN. The second electrode Cb2 of the auxiliary capacitor Cb and the storage electrode CintS of the integration capacitor Cint are electrically connected to a center tap node CT.

The supplementary circuit <NUM> is configured to pre-charge the working node WN by successively pre-charging, with the working node WN connected to a positive first auxiliary voltage VDDH, the center tap node CT with the supply reference potential, and then connecting, with the working node WN floating, the center tap node CT to a positive second auxiliary voltage VDD2. The first and second positive auxiliary voltages VDDH, VDD2 may be equal. At least one of the first and second positive auxiliary voltages VDDH, VDD2 may differ from the positive supply voltage VDD.

A first switch <NUM> electrically connects the working node WN to the positive first auxiliary voltage VDDH in a first phase Tp1 of the pre-charge period Tpre, when the auxiliary capacitor Cb is pre-charged with the positive first auxiliary voltage VDDH.

The first switch <NUM> is open in a second phase Tp2 of the pre-charge period Tpre when the reference potential for the auxiliary capacitor Cb is shifted. The first switch <NUM> is also open during the integration period Tint.

A second switch <NUM> electrically connects the center tap node CT to the supply reference potential GND in the first phase Tp1 of the pre-charge period Tpre. The second switch <NUM> is open in the second phase Tp2 of the pre-charge period Tpre, when the reference for the auxiliary capacitor Cb is shifted. The second switch <NUM> is also open in the integration period Tpre.

A third switch <NUM> electrically connects the center tap node CT to the positive second auxiliary voltage VDD2 in the second phase Tp2 of the pre-charge period Tpre. The third switch <NUM> is open in the first phase Tp1 of the pre-charge period Tpre and during the integration period Tint.

<FIG> shows some signals for the pixel circuit <NUM> of <FIG> for the case that the first and second auxiliary voltages VDDH and VDD2 are equal (VDD2=VDDH).

Each operation cycle of the pixel circuit <NUM> includes a pre-charge period Tpre and an integration period Tint that may directly follow the pre-charge period Tpre.

A first phase Tp1 of the pre-charge period Tpre starts at t=t0. The first switch <NUM> and the second switch <NUM> are "on". The third switch <NUM> is "off". The potential Vb at the working node WN is set by the positive first auxiliary voltage VDDH. The output voltage Vout between the storage electrode CintS and the supply reference potential GND is 0V.

A second phase Tp2 of the pre-charge period Tpre starts at t=t3. The first switch <NUM> and the second switch <NUM> are "off". The third switch <NUM> is "on". The potential Vb at the working node WN is increased by the positive second auxiliary voltage VDD2. With the first and second auxiliary voltages VDDH and VDD2 being equal, the potential Vb at the working node WN increases to <NUM>*VDDH and the output voltage Vout between the storage electrode CintS and the supply reference potential GND is set equal to the first auxiliary voltage VDDH.

The integration period Tint starts at t=t4 and ends at t=t0 of the next pre-charge period Tpre. The first switch <NUM>, the second switch <NUM>, and the third switch are "off". The equivalent capacitance at the working node WN is equal to Cint//Cb. The capacitance of Vout is equal to Cint. By integrating the photocurrent with the effective capacitance, the voltage Vb between the wording node WN and the supply reference potential GND steadily decreases starting from Vb = <NUM>*VDDH. Accordingly the output voltage Vout steadily decreases starting from Vout = VDDH. The output voltage Vout at the end of the integration period Tint changes by an amount that is equal to (Iphoto*Tint)/Cint.

<FIG> is a perspective view showing an example of a laminated structure of a solid-state imaging device <NUM> with a plurality of pixels arranged matrix-like in array form. Each pixel includes at least one photoelectric conversion element.

The solid-state imaging device <NUM> has the laminated structure of a first chip (upper chip) <NUM> and a second chip (lower chip) <NUM>.

The laminated first and second chips <NUM>, <NUM> may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip <NUM>.

The solid-state imaging device <NUM> may be formed to have the laminated structure in such a manner that the first and second chips <NUM> and <NUM> are bonded together at wafer level and cut out by dicing.

In the laminated structure of the upper and lower two chips, the first chip <NUM> may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, e.g., the photoelectric conversion elements arranged in array form.

For example, the first chip <NUM> may include only the photoelectric conversion elements of the pixel circuits as described above with reference to the preceding FIGS. Alternatively, the first chip <NUM> may include further elements of each pixel circuit. For example, the first chip <NUM> may include, in addition to the photoelectric conversion elements, at least the buffer transistor, the integration capacitor and/or the auxiliary transistor of the pixel circuits. Alternatively, the first chip <NUM> may include each element of the pixel circuit.

The second chip <NUM> may be mainly a logic chip (digital chip) that includes the elements complementing the elements on the first chip <NUM> to complete pixel circuits. The second chip <NUM> may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip <NUM> through the TCVs.

The second chip <NUM> may have one or more bonding pads BPD and the first chip <NUM> may have openings OPN for use in wire-bonding to the second chip <NUM>.

The solid-state imaging device <NUM> with the laminated structure of the two chips <NUM>, <NUM> may have the following characteristic configuration:
The electrical connection between the first chip <NUM> and the second chip <NUM> is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four corners of the solid-state imaging device <NUM>, by which a signal wiring area of the first chip <NUM> can be reduced.

<FIG> shows a possible allocation of elements of a BDI pixel circuit <NUM> across the first chip <NUM> and the second chip <NUM> of <FIG>.

The first chip <NUM> includes the photoelectric conversion element PD which is in high-side configuration. The second chip <NUM> includes the p-channel buffer transistor <NUM> and the amplifier circuit <NUM> of the photoelectric conversion element PD, the supplementary circuit <NUM> and the pixel output circuit <NUM>. One through contact via <NUM> per pixel circuit <NUM> passes the detector signal from the first chip <NUM> to the second chip <NUM>.

Typically, the first chip <NUM> includes a p-type substrate and formation of p-channel MOSFETs may imply the formation of n-doped wells separating the p-type source and drain regions of the p-channel MOSFETs from each other and from further p-type regions. Avoiding the formation of p-channel MOSFETs may therefore simplify the manufacturing process of the first chip <NUM>. By forming the photoelectric conversion element PD on the first chip <NUM> it is also possible to form the photoelectric conversion element PD from a semiconductor material other than the semiconductor material used for the other elements of the pixel circuit <NUM>.

<FIG> illustrates schematic configuration examples of solid- state imaging devices <NUM>, <NUM>.

The single-layer solid-state imaging device <NUM> illustrated in part A of <FIG> includes a single die (semiconductor substrate) <NUM>. Mounted and/or formed on the single die <NUM> are a pixel region <NUM> (photoelectric conversion elements), a control circuit <NUM> (readout circuit, threshold controller), and a logic circuit <NUM> (parts of pixel circuits, row driver). In the pixel region <NUM>, pixels are disposed in an array form. The control circuit <NUM> performs various kinds of control including control of driving the pixels. The logic circuit <NUM> performs signal processing.

Parts B and C of <FIG> illustrate schematic configuration examples of multi-layer solid-state imaging devices <NUM> with laminated structure. As illustrated in parts B and C of <FIG>, two dies (chips), namely a sensor die <NUM> (first chip) and a logic die <NUM> (second chip), are stacked in a solid-state imaging device <NUM>. These dies are electrically connected to form a single semiconductor chip.

With reference to part B of <FIG>, the pixel region <NUM> and the control circuit <NUM> are formed or mounted on the sensor die <NUM>, and the logic circuit <NUM> is formed or mounted on the logic die <NUM>. The logic circuit <NUM> may include at least parts of the pixel circuits as described with reference to the preceding FIGS. The pixel region <NUM> includes at least the photoelectric conversion elements.

With reference to part C of <FIG>, the pixel region <NUM> is formed or mounted on the sensor die <NUM>, whereas the control circuit <NUM> and the logic circuit <NUM> are formed or mounted on the logic die <NUM>.

According to another example (not illustrated), the pixel region <NUM> and the logic circuit <NUM>, or the pixel region <NUM> and parts of the logic circuit <NUM> may be formed or mounted on the sensor die <NUM>, and the control circuit <NUM> is formed or mounted on the logic die <NUM>.

<FIG> is a block diagram illustrating a configuration example of a ToF (time-of-flight) module <NUM> according to this embodiment of the present technology. The ToF module <NUM> may be an electronic apparatus that measures a distance by a time of flight method, and includes a light-emitting unit <NUM>, a control unit <NUM>, and a solid-state imaging device <NUM> with pixel circuits as described in the preceding FIGS.

The light-emitting unit <NUM> intermittently emits irradiation light to irradiate an object with the irradiation light. For example, the light-emitting unit <NUM> generates irradiation light in synchronization with a light-emission control signal of a rectangular wave. In addition, the light-emitting unit <NUM> may include a photodiode, and near infrared light and the like can be used as the irradiation light. Furthermore, the light-emission control signal is not limited to the rectangular wave as long as the light-emission control signal is a periodic signal. For example, the light-emission control signal may be a sinusoidal wave. In addition, the irradiation light may be visible light and the like without limitation to near infrared light.

The control unit <NUM> controls the light-emitting unit <NUM> and the solid-state imaging device <NUM>. The control unit <NUM> generates the light-emission control signal and may supply the light-emission control signal to the light-emitting unit <NUM> and the solid-state imaging device <NUM> through signal lines <NUM> and <NUM>. For example, a frequency of the light-emission control signal may be <NUM> megahertz (MHz). Furthermore, the frequency of the light-emission control signal may be <NUM> megahertz (MHz) and the like without limitation to <NUM> megahertz (MHz).

The solid-state imaging device <NUM> receives reflected light of the intermittent irradiation light and measures a distance from an object by the ToF method. The solid-state imaging device <NUM> may generate distance measurement data indicating a measured distance and may output the distance measurement data to an outer side. With the solid-state imaging device <NUM> including pixel circuits as described with reference to the preceding figures, the ToF module combines high dynamic range and low power consumption.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> imaging an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> may be or may include a solid-state imaging device with pixel circuits according to the embodiments of the present disclosure. In particular, with the solid-state imaging device <NUM> including the pixel circuits as described with reference to the preceding figures, the imaging section <NUM> combines high dynamic range and low power consumption. The light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit <NUM> detects information about the inside of the vehicle and may be or may include a solid-state imaging device and with pixel circuits according to the embodiments of the present disclosure. The driver state detecting section <NUM>, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display or a head-up display.

<FIG> is a diagram depicting an example of the installation position of the imaging section <NUM>, wherein the imaging section <NUM> may include imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the side view mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the side view mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including a solid-state imaging device according to the present disclosure.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying the pixel circuits according to the embodiments the dynamic range of the sensors, and the intensity resolution of the sensors can be enhanced.

The solid-state imaging device according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

Claim 1:
A pixel circuit (<NUM>), comprising:
a photoelectric conversion circuit (<NUM>) configured to generate and output a photocurrent (Iphoto);
an integration capacitor (Cint) comprising a storage electrode (CintS) and a reference electrode (CintR), wherein the reference electrode (CintR) is connected to a first supply potential (VSUP1), and wherein the integration capacitor (Cint) is configured to integrate the photocurrent on the storage electrode (CintS) in an integration period (Tint); and
a supplementary circuit (<NUM>) configured to pre-charge a working node (WN) between the photoelectric conversion circuit (<NUM>) and the storage electrode (CintS) to a pre-charge potential (Vpre) different from the first supply potential (VSUP1),
wherein the supplementary circuit (<NUM>) comprises an auxiliary capacitor (Cb) comprising a first electrode (Cb1) and a second electrode (Cb2), wherein the first electrode (Cb1) is electrically connected to the working node (WN), and wherein the second electrode (Cb2) and the storage electrode (CintS) of the integration capacitor (Cint) are electrically connected to a center tap node (CT), and
wherein the supplementary circuit (<NUM>) is configured to pre-charge the working node (WN) by successively (i) pre-charging, with the working node (WN) connected to the first supply voltage (VSUP1), the center tap node with a tap potential, and then (ii) connecting, with the working node (WN) disconnected from the first supply voltage (VSUP1), the center tap node (CT) to the first supply voltage (VSUP1).