Patent Description:
Out-of-band (OOB) signals may be part of communication systems. OOB signals may be used to send data regarding the strength, quality, or other status of a data signal and/or a data channel that carries the data signal. The data may be used to monitor the data signal and/or the data channel. Monitoring the data signal and/or the data channel may allow for adjustments to the data signal and/or the data channel to reduce power usage, increase signal-to-noise-ratio, among adjustments for other reasons.

The background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.

<CIT> discloses systems and methods for accessing the digital diagnostic data and controller data of a remote transceiver module via the diagnostic port of a local transceiver. The disclosure involves modulating high-speed data and out-of-band data as a double modulated signal, wherein the out-of-band data includes the remote transceiver controller and digital diagnostic data, which is subsequently accessible by an external user device from the diagnostic port of the local transceiver.

<CIT> discloses a method for performing put-of-band data communication of diagnostic and/or configuration data using transceivers in a data or communication network. A light beam or other carrier is modulated with high-speed data and out-of-band diagnostic and/or configuration data to create a double modulated data signal. A physical layer signal is created that includes modulations of the double modulated signal. The physical layer signal is transmitted onto a physical link.

The object and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the present disclosure, as claimed.

An embodiment described herein relates to an optical receiver comprising:a photodiode configured to generate an electrical signal based on a received optical out-of-band signal; a plurality of current mirror circuits configured to extract a voltage differential signal that represents a modulated out-of-band data signal based on the electrical signal; a limiting amplifier circuit configured to receive the voltage differential signal and to apply a gain to the voltage differential signal to generate an amplified signal that includes the modulated out-of-band data signal; and a demodulation circuit electrically coupled to the limiting amplifier circuit and configured to demodulate the modulated out-of-band data signal included in the amplified signal.

An embodiment described herein relates to an out-of-band signal detector for an optical receiver comprising: a first node configured to receive an alternating current "AC" portion and a direct current "DC" portion of an electrical signal based on an optical signal, wherein the AC portion includes modulated out-of-band data carried by the electrical signal;a current to voltage processing circuit configured to extract the AC portion of the electrical signal from the DC portion of the electrical signal by creating a voltage differential signal that represents the modulated out-of-band data;a limiting amplifier circuit electrically configured to receive the extracted voltage differential signal to generate an amplified signal including the modulated out-of-band data; and an analog-to-digital converter circuit configured to sample the amplified signal and to generate a digital sample that represents the modulated out-of-band data. Embodiments of the present disclosure will be explained with reference to the accompanying drawings.

<FIG> is a block diagram of an out-of-band (OOB) signal detection circuit <NUM>, arranged in accordance with some embodiments described in this disclosure. The OOB signal detection circuit <NUM> may include, but is not limited to, a node <NUM>, a current to voltage processing circuit <NUM>, a limiting amplifier circuit <NUM>, and a demodulation circuit <NUM>.

An electrical signal may be received by the node <NUM>. The electrical signal may include an electrical in-band signal and an electrical OOB signal. Some examples of data carried by and uses of an in-band signal may include electronic files or programs transmitted over a computer network, command and status signals transmitted between two buildings of a campus or transmitted voice or audio files. The OOB signal may include data relating to management and status of the in-band signal. Alternately or additionally, the OOB signal may include data relating to a condition or status of a communication channel carrying the in-band and OOB signals. For example, the OOB signal may include data indicating an intensity of an optical signal, a command to reduce intensity of an optical signal or a command to increase the intensity of an optical signal.

The in-band signal may be a high speed data signal and the OOB signal may be a low speed data signal. In some embodiments, the in-band signal may result in a high frequency modulated alternating current (AC) portion of the electrical signal. In these and other embodiments, the OOB signal may result in a low frequency modulated AC portion of the electrical signal. The OOB signal detection circuit <NUM> described in this disclosure may be configured to extract the low frequency modulated AC portion of the electrical signal.

The current to voltage processing circuit <NUM> may be electrically coupled to the node <NUM>. The current to voltage processing circuit <NUM> may be configured to receive a DC portion of the electrical signal and the low frequency modulated AC portion of the electrical signal. The current to voltage processing circuit <NUM> may also be configured to extract the low frequency modulated AC portion of the electrical signal. In some embodiments, the current to voltage processing circuit <NUM> may extract the low frequency modulated AC portion of the electrical signal by separating the low frequency modulated AC portion from the DC portion, by generating a signal representative of the low frequency modulated AC portion without the DC portion, or by using other extraction methods.

In some embodiments, to extract the low frequency modulated AC portion of the electrical signal, the current to voltage processing circuit <NUM> may generate a voltage differential signal that is representative of the low frequency modulated AC portion of the electrical signal. In these and other embodiments, the current to voltage processing circuit <NUM> may include multiple current mirror circuits. The multiple current mirror circuits may be configured to generate the voltage differential signal that is representative of the low frequency modulated AC portion. In these and other embodiments, a first of the multiple current mirror circuits may be configured to pass a first current based on the DC portion of the electrical signal. A second of the multiple current mirror circuits may be configured to pass a second current based on the low frequency modulated AC portion and the DC portion of the electrical signal. The first and second currents may result in first and second voltages in the current to voltage processing circuit <NUM>. The voltage differential signal may be generated based on a difference between the first voltage and the second voltage. The difference between the first voltage and the second voltage may represent the low frequency modulated AC portion of the electrical signal. In this manner, the low frequency modulated AC portion of the electrical signal may be extracted from the electrical signal. The current to voltage processing circuit <NUM> may provide the voltage differential signal to the limiting amplifier circuit <NUM>.

The limiting amplifier circuit <NUM> may be electrically coupled to the current to voltage processing circuit <NUM>. The limiting amplifier circuit <NUM> may be configured to apply a gain to the voltage differential signal and to generate an amplified signal. In some embodiments, the limiting amplifier circuit <NUM> may generate the amplified signal to be centered within a particular range of signal power levels. In particular, the limiting amplifier circuit <NUM> may be configured to transmit the amplified signal within a particular signal power level range regardless of the modulation technique used that results in the modulated AC portion of the electrical signal. In some embodiments, providing a signal with signal power within a particular signal power level range may reduce a complexity of other components in the OOB signal detection circuit <NUM>.

The limiting amplifier circuit <NUM> may transmit the amplified signal to the demodulation circuit <NUM>. The demodulation circuit <NUM> may be configured to demodulate the amplified signal to extract the data included within the low frequency modulated AC portion of the electrical signal.

For example, in some embodiments, the OOB signal detection circuit <NUM> may include additional circuits. For example, the OOB signal detection circuit <NUM> may include one or more of an analog-to- digital converter, a low-pass filter, a stabilizer circuit, among other circuits. As another example, in some embodiments the OOB signal detection circuit <NUM> may be part of an optical receiver or transceiver.

<FIG> is a block diagram of another out-of-band (OOB) signal detection circuit <NUM>, arranged in accordance with at least some embodiments described in this disclosure. The OOB signal detection circuit <NUM> may include, but is not limited to, an optical cable <NUM>, a photodiode <NUM>, a stabilizer circuit <NUM>, a current to voltage processing circuit <NUM>, a limiting amplifier circuit <NUM>, a low pass filter circuit <NUM>, an analog-to-digital convertor (ADC) circuit <NUM>, and a demodulation circuit <NUM>.

The optical cable <NUM> is configured to carry an optical signal. The optical cable <NUM> may be a fiber optic cable that includes one or more optical fibers or any other suitable device for carrying optical signals. The optical signal may include an in-band signal and an OOB signal. Some examples of data carried by and uses of an in-band signal may include electronic files or programs transmitted over a computer network, command and status signals transmitted between two buildings of a campus or servers in a server farm, or the transmission of voice or audio files. The OOB signal may include data related to the management and status of the optical signal and/or the optical channel that carries the optical signal. For example, the OOB signal may include data indicating an intensity of the optical signal, a command to reduce intensity of the optical signal, and/or a command to increase the intensity of an optical signal.

The optical cable <NUM> may be optically coupled to the photodiode <NUM>. The photodiode <NUM> may be configured to receive the optical signal and to generate an electrical signal based on the received optical signal.

In some embodiments, the optical signal may be modulated at both a high frequency and a low frequency. The high frequency modulation may carry in-band data by way of the in-band signal. In some embodiments, the high frequency modulation may be a first intensity modulation. The low frequency modulation may carry OOB data by way of the OOB signal. In some embodiments, the low frequency modulation may be a second intensity modulation that is smaller than the first intensity modulation. In these and other embodiments, the low frequency modulation may ride on top of the high frequency modulation.

In these and other embodiments, when the optical signal is converted to an electrical signal, the high speed signals may be converted to a high speed current signal and provided to another circuit for demodulation to extract the in-band signals from the optical signal. The photodiode <NUM> may further generate an electrical signal that includes a DC portion and a low frequency modulated AC portion. The low frequency modulated AC portion may be the second intensity modulations for the OOB data. The photodiode <NUM> may provide the electrical signal, with the DC portion and the low frequency modulated AC portion, to the stabilizer circuit <NUM>.

The stabilizer circuit <NUM> may be electrically coupled to the photodiode <NUM>. The stabilizer circuit <NUM> may be configured to stabilize a voltage on the photodiode <NUM> at a particular level. The stabilizer circuit <NUM> may provide the electrical signal to the current to voltage processing circuit <NUM>.

The current to voltage processing circuit <NUM> may be electrically coupled to the stabilizer circuit <NUM>. The current to voltage processing circuit <NUM> may be configured to receive the electrical signal. The current to voltage processing circuit <NUM> may also be configured to extract the low frequency modulated AC portion of the electrical signal. In some embodiments, the current to voltage processing circuit <NUM> may extract the low frequency modulated AC portion by generating a signal representative of the low frequency modulated AC portion without the DC portion of the electrical signal.

In some embodiments, the current to voltage processing circuit <NUM> may generate a voltage differential signal that is representative of the low frequency modulated AC portion of the electrical signal. In these and other embodiments, the current to voltage processing circuit <NUM> may include multiple current mirror circuits. The multiple current mirror circuits may be configured to generate the voltage differential signal that is representative of the low frequency modulated AC portion of the electrical signal. In these and other embodiments, a first of the multiple current mirror circuits may be configured to pass a first current based on the DC portion of the electrical signal. A second of the current mirror circuits may be configured to pass a second current based on the DC portion and the low frequency modulated AC portion of the electrical signal. The first and second currents may result in first and second voltages in the current to voltage processing circuit <NUM>. The voltage differential signal may be generated based on a difference between the first voltage and the second voltage. The difference between the first voltage and the second voltage may represent the low frequency modulated AC portion of the electrical signal. The current to voltage processing circuit <NUM> may provide the voltage differential signal to the limiting amplifier circuit <NUM>.

The limiting amplifier circuit <NUM> may be electrically coupled to the current to voltage processing circuit <NUM>. The limiting amplifier circuit <NUM> may be configured to apply a gain to the voltage differential signal to generate an amplified signal. In some embodiments, the amplified signal may have a power level that is limited to a particular power level range regardless of the input power level. In these and other embodiments, the gain may thus be greater than one, one, or less than one.

The low pass filter circuit <NUM> may be electrically coupled to the limiting amplifier circuit <NUM>. The low pass filter circuit <NUM> may be configured to receive the amplified signal. The low pass filter circuit <NUM> may also be configured to pass a filtered signal by blocking particular features of the amplified signal. For example, the low pass filter circuit <NUM> may block a portion of the amplified signal above a low frequency threshold frequency. The low pass filter circuit <NUM> may be configured to pass the filtered signal to the ADC circuit <NUM>.

The ADC circuit <NUM> may be configured to receive the filtered signal. The ADC circuit <NUM> may convert the filtered signal into one or more digital samples with digital values. In some embodiments, the ADC circuit <NUM> may periodically sample the voltage of the filtered signal and may create a digital sample based on the filtered signal. The ADC circuit <NUM> may have a particular range of signal power levels that may be processed. In these and other embodiments, the limiting amplifier circuit <NUM> may generate the amplified signal with a power level within the range of signal power levels that may be processed by the ADC circuit <NUM>.

The ADC circuit <NUM> may transmit the digital samples to the demodulation circuit <NUM>. The demodulation circuit <NUM> may be configured to demodulate the digital samples to extract the OOB data included within the low frequency modulated AC portion of the electrical signal.

For example, in some embodiments, the OOB signal detection circuit <NUM> may include fewer circuits. For example, the OOB signal detection circuit <NUM> may not include one or more of a low pass filter circuit <NUM>, a stabilizer circuit <NUM>, among other circuits. As another example, in some embodiments the OOB signal detection circuit <NUM> may be part of an optical receiver or transceiver.

<FIG> is block diagram of yet another out-of-band (OOB) signal detection circuit <NUM>, arranged in accordance with at least some embodiments described in this disclosure. The OOB signal detection circuit <NUM> may include, but is not limited to, a current to voltage processing circuit <NUM>, a voltage source <NUM>, a limiting amplifier circuit <NUM>, and an analog-to-digital convertor (ADC) circuit <NUM>.

The current to voltage processing circuit <NUM> may include, but is not limited to, a first current mirror circuit <NUM>, a biasing circuit <NUM>, a second current mirror circuit <NUM>, a first connection <NUM>, a second connection <NUM>, and a signal-to-noise ratio (SNR) improvement circuit <NUM>.

The current to voltage processing circuit <NUM> may be configured to receive an OOB signal. The OOB signal may be an electrical signal and may include a DC portion and a modulated AC portion. In some embodiments, the electrical signal may be derived from an optical signal.

The electrical signal may be received by the first current mirror circuit <NUM>. The first current mirror circuit <NUM> may pass a first current to the second current mirror circuit <NUM> along both the first connection <NUM> and the second connection <NUM>. The first current may be based on the DC portion and the modulated AC portion of the electrical signal. The voltage source <NUM> may provide a positive voltage to the first current mirror circuit <NUM>. The positive voltage may cause the first current mirror circuit <NUM> to pass the first current to the second current mirror circuit <NUM>. The first current may pass from the voltage source <NUM> to a signal ground through the second current mirror circuit <NUM> and the SNR improvement circuit <NUM>.

The second current mirror circuit <NUM> may be electrically coupled to the first current mirror circuit <NUM> by way of the first connection <NUM> and the second connection <NUM>. The second current mirror circuit <NUM> may be configured to receive the first current on the first connection <NUM>. The second current mirror circuit <NUM> may include a filter circuit <NUM> electrically coupled to the first connection <NUM> and configured to extract the modulated AC portion of the electrical signal. The remaining DC portion of the electrical signal may be used to control the current passed by the second current mirror circuit <NUM> that is received from the second connection <NUM>. Thus, in these and other embodiments, the second current mirror circuit <NUM> may pass a second current from the second connection <NUM> based on the DC portion of the electrical signal and not based on the modulated AC portion of the electrical signal. Furthermore, the second current mirror circuit <NUM> may pass the first current from the first connection <NUM> based on the DC portion of the electrical signal and on the modulated AC portion of the electrical signal. Because the currents passed by the second current mirror circuit <NUM> are different, each of the first connection <NUM> and the second connection <NUM> may have a different voltage. The different voltages may be used to generate a voltage differential signal that may be provided to the limiting amplifier circuit <NUM>.

Thus, in some embodiments, the current to voltage processing circuit <NUM> may be configured to extract the modulated AC portion by generating a voltage differential signal representative of the modulated AC portion without the DC portion and passing the voltage differential signal to the limiting amplifier circuit <NUM>.

The biasing circuit <NUM> may be electrically coupled between the first connection <NUM> and the second connection <NUM>. The biasing circuit <NUM> may be configured to control a voltage and/or a current in the first current mirror circuit <NUM> and the second current mirror circuit <NUM>. Controlling the voltage and/or current of the first current mirror circuit <NUM> and the second current mirror circuit <NUM> may increase the likelihood that the first current mirror circuit <NUM> and the second current mirror circuit <NUM> operate in a particular region of operation. For example, the first current mirror circuit <NUM> and the second current mirror circuit <NUM> may include multiple transistors. The particular region of operation may be a triode or a saturation region of the multiple transistors. In some embodiments, a transistor may pass a constant current when operating in the saturation region of an operational curve. In these and other embodiments, a transistor may pass a varying current when operating in the triode region of an operational curve.

The SNR improvement circuit <NUM> may be electrically coupled between the second current mirror circuit <NUM> and a signal ground. The SNR improvement circuit <NUM> may be configured to reduce noise in the second current mirror circuit <NUM>.

The limiting amplifier circuit <NUM> may be electrically coupled to the first current mirror circuit <NUM>, the second current mirror circuit <NUM>, and the biasing circuit <NUM>. The limiting amplifier circuit <NUM> may be configured to receive the voltage differential signal and apply a gain to the voltage differential signal to generate an amplified signal. In some embodiments, the amplified signal may have a power level that is limited to a particular range regardless of the input power level.

The ADC circuit <NUM> may be electrically coupled to the limiting amplifier circuit <NUM>. The ADC circuit <NUM> may be configured to receive the amplified signal. The ADC circuit <NUM> may convert the amplified signal into one or more digital samples with digital values. In some embodiments, the ADC circuit <NUM> may periodically sample, randomly sample, or otherwise sample the voltage of the amplified signal and create a digital sample based on the amplified signal. The ADC circuit <NUM> may have a particular range of signal power levels that may be processed. In these and other embodiments, the limiting amplifier circuit <NUM> may generate the amplified signal with a power level within the range of signal power levels that may be processed by the ADC circuit <NUM>.

For example, in some embodiments the OOB signal detection circuit <NUM> may be part of an optical receiver or transceiver. As another example, in some embodiments, the OOB signal detection circuit <NUM> may include fewer circuits. For example, the OOB signal detection circuit <NUM> may not include the SNR improvement circuit <NUM>.

<FIG> is a circuit drawing of an out-of-band (OOB) signal detection circuit <NUM>, arranged in accordance with at least some embodiments described in this disclosure. The OOB signal detection circuit <NUM> may include, but is not limited to, an optical cable <NUM>, a photodiode <NUM>, a stabilizer circuit <NUM>, a current to voltage processing circuit <NUM>, a limiting amplifier circuit <NUM>, a low pass filter circuit <NUM>, an analog-to-digital convertor (ADC) circuit <NUM>, and a demodulation circuit <NUM>.

The optical cable <NUM> may be configured to carry an optical signal that may include an optical in-band signal and an optical OOB signal. The optical cable <NUM> may be optically coupled to the photodiode <NUM>. The photodiode <NUM> may be configured to receive the optical signal and to generate an electrical signal that includes a DC portion and a modulated AC portion and may be based on the received optical signal. The photodiode <NUM> may provide the electrical signal including the DC portion and the modulated AC portion to the stabilizer circuit <NUM>.

In these and other embodiments, when the optical signal is converted to an electrical signal, the high speed signals may be converted to a high speed data <NUM> and provided to another circuit for demodulation to extract the in-band signals from the optical signal.

The stabilizer circuit <NUM> may include an operational amplifier <NUM>, a first transistor <NUM>, and a first capacitive circuit <NUM>. The first transistor may include a gate, a source, and a drain. Generally, with respect to the transistors illustrated in <FIG>, a transistor source may be a terminal with an arrow, a transistor gate may be a terminal with parallel horizontal lines, and a transistor drain may be the other terminal.

The operational amplifier <NUM> may have a positive input electrically coupled to a cathode of the photodiode <NUM>, the first capacitive circuit <NUM>, and the drain of the first transistor <NUM>. The operational amplifier <NUM> may have a voltage provided on a negative input. The first capacitive circuit <NUM> may be coupled between a signal ground and the cathode of the photodiode <NUM>, the drain of the first transistor <NUM>, and the positive input of the operational amplifier <NUM>. The gate of the first transistor <NUM> may be electrically coupled to an output of the operational amplifier <NUM>. The drain of the first transistor <NUM> may be
electrically coupled to the positive input of the operational amplifier <NUM>, the first capacitive circuit <NUM>, and the cathode of the photodiode <NUM>. The source of the first transistor <NUM> may be electrically coupled to a voltage source. The stabilizer circuit <NUM> may be configured to stabilize a voltage on the photodiode <NUM> at a particular level. The stabilizer circuit <NUM> may provide a stabilized signal to the current to voltage processing circuit <NUM> based on the stabilized voltage on the photodiode <NUM>.

The current to voltage processing circuit <NUM> may include a second transistor <NUM>, a third transistor <NUM>, a first resistive circuit <NUM>, a fourth transistor <NUM>, a second capacitive circuit <NUM>, a second resistive circuit <NUM>, a first diode <NUM>, a second diode <NUM>, and a fifth transistor <NUM>. Each of the transistors <NUM>, <NUM>, <NUM>, and <NUM> may include a gate, a source, and a drain.

The gate of the second transistor <NUM> may be electrically coupled to the gate of the first transistor <NUM> and the gate of the third transistor <NUM>. The second transistor <NUM> may be configured to receive the stabilized signal from the stabilizer circuit <NUM>. The source of the second transistor <NUM> may be electrically coupled to a voltage source. The drain of the second transistor <NUM> may be electrically coupled to the first resistive circuit <NUM>, the second resistive circuit <NUM>, the drain and gate of the fourth transistor <NUM>, and the limiting amplifier circuit <NUM>.

The gate of the third transistor <NUM> may be electrically coupled to the gate of the second transistor <NUM> and the stabilizer circuit <NUM>. The source of the third transistor <NUM> may be electrically coupled to a voltage source. The drain of the third transistor <NUM> may be electrically coupled to the first resistive circuit <NUM>, the drain of the fifth transistor <NUM>, and the limiting amplifier circuit <NUM>.

The drain of the fourth transistor <NUM> may be electrically coupled to the drain of the second transistor <NUM>, the first resistive circuit <NUM>, the second resistive circuit <NUM>, the gate of the fourth transistor <NUM>, and the limiting amplifier circuit <NUM>. The gate of the fourth transistor <NUM> may be electrically coupled to the first resistive circuit <NUM>, the second resistive circuit <NUM>, the drain of the second transistor <NUM>, and the drain of the fourth transistor <NUM>. The source of the fourth transistor <NUM> may be electrically coupled to an anode of the first diode <NUM>.

The drain of the fifth transistor <NUM> may be electrically coupled to the first resistive circuit <NUM>, the drain of the third transistor <NUM>, and the limiting amplifier circuit <NUM>. The gate of the fifth transistor <NUM> may be electrically coupled to the second resistive circuit <NUM> and the second capacitive circuit <NUM>. The source of the fifth transistor <NUM> may be electrically coupled to an anode of the second diode <NUM>.

A first end of the first resistive circuit <NUM> may be electrically coupled to the drain and gate of the fourth transistor <NUM>, the drain of the second transistor <NUM>, and the second resistive circuit <NUM>. A second end of the first resistive circuit <NUM> may be electrically coupled to the drain of the third transistor <NUM>, the drain of the fifth transistor <NUM>, and the limiting amplifier circuit <NUM>.

A first end of the second resistive circuit <NUM> may be electrically coupled to the gate and drain of the fourth transistor <NUM>, the drain of the second transistor <NUM>, the first resistive circuit <NUM>, and the limiting amplifier circuit <NUM>. A second end of the second resistive circuit <NUM> may be electrically coupled to the second capacitive circuit <NUM> and the gate of the fifth transistor <NUM>.

The second capacitive circuit <NUM> may be electrically coupled between a signal ground and the second resistive circuit <NUM> and the gate of the fifth transistor <NUM>. The first diode <NUM> may be electrically coupled between the source of the fourth transistor <NUM> and a signal ground. The second diode <NUM> may be electrically coupled between the source of the fifth transistor <NUM> and a signal ground. The current to voltage processing circuit <NUM> may be configured to extract the modulated AC portion of the electrical signal and provide the modulated AC portion to the limiting amplifier circuit <NUM>.

The first transistor <NUM> may provide a voltage to the gate of the second transistor <NUM> and the gate of the third transistor <NUM>. The voltage may be based on the DC portion and the modulated AC portion of the electrical signal. The voltage on the gate of the second transistor <NUM> and the gate of the third transistor <NUM> may cause the second transistor <NUM> to pass the first current to the fourth transistor <NUM> and the third transistor <NUM> to pass the first current. A voltage on the drain of the second transistor <NUM> may be provided to the limiting amplifier circuit <NUM>. The voltage on the drain of the second transistor <NUM> may be based on the DC portion and the modulated AC portion of the electrical and may be part of the voltage differential signal.

The voltage on the drain of the second transistor <NUM> may be provided to the gate of the fourth transistor <NUM>. The voltage on the gate of the fourth transistor <NUM> may be based on the DC portion and the modulated AC portion of the electrical signal and may cause the fourth transistor <NUM> to pass the first current. The second resistive circuit <NUM> and the second capacitive circuit <NUM> may average the voltage on the gate of the fourth transistor <NUM> and may provide a voltage to the gate of the fifth transistor <NUM> based on the DC portion of the electrical signal. The voltage on the gate of the fifth transistor <NUM> may cause the fifth transistor <NUM> to pass a second current that is different than the first current passed by the third transistor <NUM>. As a result, a voltage on the drain of the fifth transistor <NUM> may be different than the voltage on the drain of the second transistor <NUM>. The voltage on the drain of the fifth transistor <NUM> may be provided to the limiting amplifier circuit <NUM>. The voltage on the drain of the fifth transistor may be based on the DC portion of the electrical signal and not based on the modulated AC portion and may form the other part of the voltage differential signal.

The limiting amplifier circuit <NUM> may be configured to receive the voltage differential signal and to generate an amplified signal based on the voltage differential signal. The limiting amplifier circuit <NUM> may include, but is not limited to, a sixth transistor <NUM>, a seventh transistor <NUM>, an eighth transistor <NUM>, a ninth transistor <NUM>, a tenth transistor <NUM>, an eleventh transistor <NUM>, a twelfth transistor <NUM>, a thirteenth transistor <NUM>, and a current source <NUM>. Each of the transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may include a gate, a source, and a drain.

The gate of the eleventh transistor <NUM> may be electrically coupled to the drain of the second transistor <NUM>, the first resistive circuit <NUM>, the gate and drain of the fourth transistor <NUM> and the second resistive circuit <NUM>. The drain of the eleventh transistor <NUM> may be electrically coupled to the drain and gate of the sixth transistor <NUM>, and the gate of the seventh transistor <NUM>. The source of the eleventh transistor <NUM> may be electrically coupled to the source of the tenth transistor <NUM> and the current source <NUM>.

The gate of the tenth transistor <NUM> may be electrically coupled to the drain of the third transistor <NUM>, the drain of the fifth transistor <NUM>, and the first resistive circuit <NUM>. The drain of the tenth transistor <NUM> may be electrically coupled to the drain and gate of the eighth transistor <NUM> and the gate of the ninth transistor <NUM>. The source of the tenth transistor <NUM> may be electrically coupled to the source of the eleventh transistor <NUM> and the current source <NUM>.

The gate of the sixth transistor <NUM> may be electrically coupled to the gate of the seventh transistor <NUM>, the drain of the eleventh transistor <NUM>, and the drain of the sixth transistor <NUM>. The source of the sixth transistor <NUM> may be electrically coupled to a voltage source. The drain of the sixth transistor <NUM> may be electrically coupled to the gate of the seventh transistor <NUM>, the gate of the sixth transistor <NUM>, and the drain of the eleventh transistor <NUM>.

The gate of the seventh transistor <NUM> may be electrically coupled to the gate and drain of the sixth transistor <NUM> and the drain of the eleventh transistor <NUM>. The source of the seventh transistor <NUM> may be electrically coupled to a voltage source. The drain of the seventh transistor <NUM> may be electrically coupled to the drain of the thirteenth transistor <NUM> and the low pass filter circuit <NUM>.

The gate of the eighth transistor <NUM> may be electrically coupled to the gate of the ninth transistor <NUM>, the drain of the eighth transistor <NUM>, and the drain of the tenth transistor <NUM>. The source of the eighth transistor <NUM> may be electrically coupled to a voltage source. The drain of the eighth transistor <NUM> may be electrically coupled to the drain of the tenth transistor <NUM>, the gate of the eighth transistor <NUM>, and the gate of the ninth transistor <NUM>.

The gate of the ninth transistor <NUM> may be electrically coupled to the gate and drain of the eighth transistor <NUM> and the drain of the tenth transistor <NUM>. The source of the ninth transistor <NUM> may be electrically coupled to a voltage source. The drain of the ninth transistor <NUM> may be electrically coupled to the gate and drain of the twelfth transistor <NUM> and the gate of the thirteenth transistor <NUM>.

The gate of the twelfth transistor <NUM> may be electrically coupled to the gate of the thirteenth transistor <NUM>, the drain of the twelfth transistor <NUM>, and the drain of the ninth transistor <NUM>. The source of the twelfth transistor <NUM> may be electrically coupled to a signal ground. The drain of the twelfth transistor <NUM> may be electrically coupled to the gate of the thirteenth transistor <NUM>, the gate of the twelfth transistor <NUM>, and the drain of the ninth transistor <NUM>.

The gate of the thirteenth transistor <NUM> may be electrically coupled to the gate and drain of the twelfth transistor <NUM> and the drain of the ninth transistor <NUM>. The source of the thirteenth transistor <NUM> may be electrically coupled to a signal ground. The drain of the thirteenth transistor <NUM> may be electrically coupled to the drain of the seventh transistor <NUM> and the low pass filter circuit <NUM>. The current source <NUM> may be electrically coupled between a signal ground, the source of the tenth transistor <NUM>, and the source of the eleventh transistor <NUM>.

The low pass filter circuit <NUM> may be configured to receive the amplified signal from the limiting amplifier circuit <NUM>. The low pass filter circuit <NUM> may be configured to block particular features of the amplified signal and to pass a filtered signal to the ADC circuit <NUM>. The low pass filter circuit <NUM> may include, but is not limited to, a third resistive circuit <NUM>, a voltage source <NUM>, and second capacitive circuit <NUM>. The voltage source <NUM> may include a positive source and a negative source.

The third resistive circuit <NUM> may be electrically coupled to the positive source of the voltage source <NUM>, the second capacitive circuit <NUM>, the limiting amplifier circuit <NUM>, and the ADC circuit <NUM>. The second capacitive circuit <NUM> may be electrically coupled between a signal ground and the limiting amplifier circuit <NUM>, the third resistive circuit <NUM>, and the ADC circuit <NUM>. The voltage source <NUM> may be coupled between a signal ground and the third resistive circuit <NUM>.

The ADC circuit <NUM> may be electrically coupled to the low pass filter circuit <NUM>. The ADC circuit <NUM> may be configured to receive the filtered signal. The ADC circuit <NUM> may convert the filtered signal into one or more digital samples with digital values.

The ADC circuit <NUM> may transmit the digital samples to the demodulation circuit <NUM>. The demodulation circuit <NUM> may be configured to demodulate the digital samples to extract the data included within the modulated AC portion of the electrical signal.

For example, in some embodiments, the OOB signal detection circuit <NUM> may include fewer circuits. For example, the OOB signal detection circuit <NUM> may not include one or more of the low pass filter circuit <NUM> and the stabilizer circuit <NUM>, among other circuits. As another example, in some embodiments the OOB signal detection circuit <NUM> may be part of an optical receiver or transceiver.

<FIG> is a flowchart of an example method <NUM> of out-of-band (OOB) signal detection, in accordance with at least some embodiments described herein. The method <NUM> may be implemented, in some embodiments, by an OOB detection circuit, such as the OOB signal detection circuits <NUM>, <NUM>, <NUM>, and/or <NUM> of <FIG>, <FIG>, or <FIG> respectively. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

The method <NUM> may begin at block <NUM> where an electrical signal including an alternating current (AC) portion and a direct current (DC) portion may be received. The AC portion may include modulated OOB data carried by the electrical signal.

In block <NUM>, the modulated AC portion of the electrical signal may be extracted. In some embodiments, extracting the modulated AC portion of the electrical signal may include averaging a voltage based on a current that includes the modulated OOB data carried by the electrical signal. Alternately or additionally, extracting the modulated AC portion of the electrical signal may also include extracting a difference between the average voltage and a voltage of the electrical signal.

In block <NUM>, a gain may be applied to the extracted modulated AC portion of the electrical signal to generate an amplified signal. An amplitude of the amplified signal may be limited to a particular range and may vary based on the modulated AC portion of the electrical signal and not based on the DC portion of the electrical signal. In some embodiments, the particular range that the amplitude of the amplified signal is limited to may be based on a power range that may be received by an analog-to-digital convertor. In block <NUM>, the amplified signal may be sampled to generate a digital sample that represents the modulated OOB data.

One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Furthermore, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations. For instance, the method <NUM> may further include generating the electrical signal based on an optical signal.

<FIG> is a perspective view of an example optoelectronic module <NUM> (hereinafter "module <NUM>") that may include an out-of-band (OOB) signal detection circuit <NUM>, arranged in accordance with at least some embodiments described herein. The module <NUM> may be configured for use in transmitting and receiving optical signals in connection with a host device (not shown).

As illustrated, the module <NUM> may include, but is not limited to, a bottom housing <NUM>, a receive port <NUM>, and a transmit port <NUM>, both defined in the bottom housing <NUM>; a PCB <NUM> positioned within the bottom housing <NUM>, the PCB <NUM> having the OOB signal detection circuit <NUM> positioned thereon; and a receiver optical subassembly (ROSA) <NUM> and a transmitter optical subassembly (TOSA) <NUM> also positioned within the bottom housing <NUM>. An edge connector <NUM> may be located on an end of the PCB <NUM> to enable the module <NUM> to electrically interface with the host device. As such, the PCB <NUM> facilitates electrical communication between the host device and the ROSA <NUM> and the TOSA <NUM>.

The module <NUM> may be configured for optical signal transmission and reception at a variety of data rates including, but not limited to, <NUM> Gb/s, <NUM> Gb/s, <NUM> Gb/s, <NUM> Gb/s, <NUM>.

Gb/s, or higher. Furthermore, the module <NUM> may be configured for optical signal transmission and reception at various distinct wavelengths using wavelength division multiplexing (WDM) using one of various WDM schemes, such as Coarse WDM, Dense WDM, or Light WDM.

Furthermore, the module <NUM> may be configured to support various communication protocols including, but not limited to, Fibre Channel and High Speed Ethernet. In addition, although illustrated in a particular form factor in <FIG>, more generally, the module <NUM> may be configured in any of a variety of different form factors including, but not limited to, the Small Form-factor Pluggable (SFP), the enhanced Small Form-factor Pluggable (SFP+), the <NUM> Gigabit Small Form-factor Pluggable (XFP), the C Form-factor Pluggable (CFP), and the Quad Small Form-factor Pluggable (QSFP) multi-source agreements (MSAs).

The ROSA <NUM> may house one or more optical receivers, such as photodiodes, that are electrically coupled to an electrical interface <NUM>. The one or more optical receivers may be configured to convert optical signals received through the receive port <NUM> into corresponding electrical signals that are relayed to the host device through the electrical interface <NUM> and the PCB <NUM>. In some embodiments, the ROSA <NUM> may receive an optical signal. In these and other embodiments, the ROSA may convert the optical signal to an electrical signal that includes a direct current (DC) portion and a modulated alternating current (AC) portion. The AC portion may include modulated OOB data carried by the electrical signal. The modulated AC portion of the electrical signal may be extracted using an OOB signal detection circuit <NUM>, such as one of the OOB signal detection circuits <NUM>, <NUM>, <NUM>, or <NUM> of <FIG>, <FIG>, and <FIG>. The extracted modulated AC portion may be demodulated to capture OOB data regarding the optical signal and/or the optical channel that carries the optical signal.

The TOSA <NUM> may house one or more optical transmitters, such as lasers, that are electrically coupled to another electrical interface <NUM>. The one or more optical transmitters may be configured to convert electrical signals received from the host device by way of the PCB <NUM> and the electrical interface <NUM> into corresponding optical signals that are transmitted through the transmit port <NUM>.

The module <NUM> illustrated with respect to <FIG> is one architecture in which embodiments of the present disclosure may be employed. It should be understood that this specific architecture is only one of countless architectures in which embodiments may be employed. The scope of the present disclosure is not intended to be limited to any particular architecture or environment.

In some embodiments, an optical receiver that includes an out-of-band signal detector is disclosed. In these and other embodiments, the optical receiver may include a photodiode including an anode and a cathode. The photodiode may be configured to receive an optical in-band signal and an optical out-of-band signal from an optical cable and to generate an electrical signal based on the optical out-of-band signal. The optical receiver may include a current to voltage processing circuit that includes multiple current mirror circuits. The current to voltage processing circuit may be electrically coupled to the cathode and configured to extract a modulated out-of-band data signal from the electrical signal.

The optical receiver may further include a limiting amplifier circuit electrically coupled to the plurality of current mirror circuits and configured to receive the extracted modulated out-of-band data signal and to apply a gain to the extracted modulated out-of-band data signal to generate an amplified signal. The optical receiver may further include a demodulation circuit electrically coupled to the limiting amplifier circuit and configured to demodulate the modulated out-of-band data signal included in the amplified signal.

In some embodiments, the multiple current mirror circuits may include a first current mirror circuit with first and second transistors and a second current mirror circuit with third and fourth transistors. The gates of the first and second transistors may be electrically coupled to the cathode and drains of the first, second, third and fourth transistors are electrically coupled to the limiting amplifier circuit.

In some embodiments, the optical receiver may further include a biasing circuit electrically coupled between the drain of the fourth transistor and a gate and the drain of the third transistor. The biasing circuit may be configured to control a voltage and/or a current in the plurality of current mirror circuits. In these and other embodiments, the electrical signal may further include a direct current portion. In some embodiments, the current to voltage processing circuit may further include a filter circuit electrically coupled to the fourth transistor and the gate and the drain of the third transistor, the filter circuit being configured to extract the modulated out-of-band data signal.

In some embodiments, the optical receiver may further include a signal-to-noise-ratio (SNR) improvement circuit electrically coupled to the second current mirror circuit. In these and other embodiments, the SNR improvement circuit may be configured to increase a dynamic direct current input range of the optical receiver. In some embodiments, the SNR improvement circuit may include a first diode and a second diode. In these and other embodiments, the first diode is electrically coupled between a source of the third transistor and a signal ground and the second diode is electrically coupled between a source of the fourth transistor and the signal ground.

In some embodiments, the optical receiver may further include a first node electrically coupled to the drains of the first and third transistors, a gate of the third transistor, and the limiting amplifier circuit, a second node electrically coupled to the drains of the second and third transistors and the limiting amplifier circuit, a first resistive circuit electrically coupled between the first node and the second node, a second resistive circuit electrically coupled between the first node and a gate of the fourth transistor, and a capacitive circuit electrically coupled between the gate of the fourth transistor and a signal ground.

In some embodiments, the optical receiver may further include a stabilizer circuit electrically coupled between the cathode and the plurality of current mirror circuits. In these and other embodiments, the stabilizer circuit may be configured to stabilize a voltage on the cathode. In some embodiments, the optical receiver may further include an analog-to-digital convertor electrically coupled between the limiting amplifier circuit and the demodulation circuit. In these and other embodiments, the analog-to-digital convertor may be configured to sample the amplified signal.

In some embodiments, an out-of-band signal detector may include a first node configured to receive an alternating current (AC) portion and a direct current (DC) portion of an electrical signal. In these and other embodiments, the AC portion may include modulated out-of-band data carried by the electrical signal. The out-of-band signal detector may further include a current to voltage processing circuit electrically coupled to the first node and configured to extract the AC portion of the electrical signal, a limiting amplifier circuit electrically coupled to the current to voltage processing circuit and configured to receive the extracted AC portion and to generate an amplified signal based on the extracted AC portion, and an analog-to-digital convertor circuit electrically coupled to the limiting amplifier circuit and configured to sample the amplified signal and to generate a digital sample that represents the modulated out-of-band data.

The out-of-band signal detector may further include a digital demodulation circuit electrically coupled to the analog-to-digital convertor circuit. In these and other embodiments, the digital demodulation circuit may be configured to demodulate the modulated out-of-band data included in the amplified signal. In some embodiments, the limiting amplifier circuit may generate the amplified signal to be within a power range that can be received by the analog-to-digital convertor circuit.

The out-of-band signal detector may further include a biasing circuit configured to control a voltage and/or current in multiple current mirror circuits. In these and other embodiments, the multiple current mirror circuits may include a first current mirror circuit with first and second transistors and a second current mirror circuit with third and fourth transistors. In these and other embodiments, gates of the first and second transistors may be electrically coupled to the first node and drains of the first, second, third and fourth transistors are electrically coupled to the limiting amplifier circuit.

The out-of-band signal detector may further include a first node electrically coupled to the drains of the first and third transistors, a gate of the third transistor, and the limiting amplifier circuit, a second node electrically coupled to the drains of the second and third transistors and the limiting amplifier circuit, a first resistive circuit electrically coupled between the first node and the second node, a second resistive circuit electrically coupled between the first node and a gate of the fourth transistor, and a capacitive circuit electrically coupled between the gate of the fourth transistor and a signal ground.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. The illustrations presented in the present disclosure are not meant to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely idealized representations that are employed to describe various embodiments of the disclosure. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or all operations of a particular method.

Terms used herein and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to," etc.).

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and/or" is intended to be construed in this manner.

Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B.

However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations.

Additionally, the use of the terms "first," "second," "third," etc., are not necessarily used herein to connote a specific order or number of elements. Generally, the terms "first," "second," "third," etc., are used to distinguish between different elements as generic identifiers. Absence a showing that the terms "first," "second," "third," etc., connote a specific order, these terms should not be understood to connote a specific order. Furthermore, absence a showing that the terms first," "second," "third," etc., connote a specific number of elements, these terms should not be understood to connote a specific number of elements. For example, a first widget may be described as having a first side and a second widget may be described as having a second side. The use of the term "second side" with respect to the second widget may be to distinguish such side of the second widget from the "first side" of the first widget and not to connote that the second widget has two sides.

Claim 1:
An optical receiver comprising:
a photodiode (<NUM>, <NUM>) configured to generate an electrical signal based on a received optical out-of-band signal;
a plurality of current mirror circuits (<NUM>, <NUM>, <NUM>, <NUM>) configured to extract a voltage differential signal that represents a modulated out-of-band data signal based on the electrical signal;
a limiting amplifier circuit (<NUM>, <NUM>, <NUM>, <NUM>) configured to receive the voltage differential signal and to apply a gain to the voltage differential signal to generate an amplified signal that includes the modulated out-of-band data signal; and
a demodulation circuit (<NUM>, <NUM>) electrically coupled to the limiting amplifier circuit and configured to demodulate the modulated out-of-band data signal included in the amplified signal.