Patent Description:
RRAM is a type of non-volatile memory that has the advantages of small memory cell size, ultra-high-speed operation, low-power operation, high endurance, and compatibility with CMOS.

The main operating principle of RRAM is to change the resistance of the metal oxide by applying bias voltage so as to store data. The data stored in RRAM is read by detecting different resistances in each of RRAMs.

Traditionally, RRAM is inserted in the position of the via one of the local interconnection in the back-end process. However, by doing so, the top surface of the via one which has RRAM inserted therein becomes uneven, and shifts from the original design position. Therefore, it is necessary to use an additional planarization process to smooth the top surface of RRAM to keep the top surface of the via one at the original design position.

<CIT> relates to a RRAM device and method. <CIT> relates to a MOS device with memory function and a manufacturing method thereof. <CIT> relates to a method for making a resistive random access memory device. <CIT> relates to approaches for fabricating back end of line (BEOL)-compatible RRAM devices and the resulting structures.

In light of the above, the present invention provides a new method of manufacturing an RRAM structure, which prevents the RRAM from affecting the original horizontal position of the local interconnection without using any additional planarization process.

A fabricating method of a resistive random access memory structure according to the independent claim <NUM> includes providing a substrate, wherein a first transistor is disposed on the substrate, the first transistor includes a first gate structure, a first source and a first drain, a first drain contact plug contacts the first drain, an interlayer dielectric layer covers the substrate and the first transistor. Next, a metal interlayer dielectric layer is formed to cover the interlayer dielectric layer. Later, a first patterning process is performed to etch the metal interlayer dielectric layer to form a first trench. The first drain contact plug is exposed through the first trench. Subsequently, a metal oxide material layer and a top electrode material layer are formed in sequence to fill in the first trench and cover the metal interlayer dielectric layer. A second patterning process is performed to pattern the metal oxide material layer and the top electrode material layer to form a metal oxide layer and a top electrode, wherein the top electrode, the metal oxide layer and the first drain contact plug form an RRAM. After that, a metal layer is formed to fill in the first trench and cover the metal interlayer dielectric layer and the RRAM. Finally, a planarization process is performed to remove the metal oxide layer, the top electrode and the metal layer outside of the first trench.

<FIG> depict a fabricating method of a resistive random access memory structure according to a preferred embodiment of the present invention, wherein <FIG> depicts a top view of <FIG>, and <FIG> depicts a top view of <FIG>.

As shown in <FIG>, a substrate <NUM> is provided. The substrate <NUM> is divided into a memory cell region A and a logic element region B. A first transistor 12a and a second transistor 12b are disposed on the substrate <NUM>. The first transistor 12a is disposed within the memory cell region A, and the second transistor 12b is disposed within the logic element region B. The first transistor 12a includes a first gate structure 14a, a first source 18a and a first drain 16a. The second transistor 12b includes a second gate structure 14b, a second drain 18b and a second drain 16b. An interlayer dielectric layer <NUM> covers the substrate <NUM>, the first transistor 12a and the second transistor 12b. A first drain contact plug 22a, a first source contact plug 24a, a second drain contact plug 22b and a source contact plug 24b penetrate the interlayer dielectric layer <NUM>. Moreover, the first drain contact plug 22a contacts the first drain 16a. The first source contact plug 24a contacts the first source 18a. The second drain contact plug 22b contacts the second drain 16b. The second source contact plug 24b contacts the second source 18b. The first gate contact plug 26a penetrates the interlayer dielectric layer <NUM> to contact the first gate structure 14a. The second gate contact plug 26b penetrates the interlayer dielectric layer <NUM> to contact the second gate structure 14b. Next, an etching stop layer <NUM>, a metal interlayer dielectric layer <NUM> and a hard mask <NUM> are formed in sequence to cover the interlayer dielectric layer <NUM>. The etching stop layer <NUM> preferably includes silicon oxynitride, silicon carbide nitride or silicon nitride. The metal interlayer dielectric layer <NUM> can be oxide such as silicon oxide. The hard mask <NUM> can be titanium nitride or silicon nitride.

As shown in <FIG>, the hard mask <NUM> is patterned by taking the etching stop layer <NUM> as a stop layer. Next, a first patterning process is performed by taking the hard mask <NUM> after patterning as a mask to etch the metal interlayer dielectric layer <NUM> and the etching stop layer <NUM> to form a first trench 36a, a second trench 36b, a third trench 36c and a fourth trench 36d. The first drain contact plug 22a is exposed through the first trench 36a. The first source contact plug 24a is exposed through the fourth trench 36d. The second source contact plug 24b is exposed through the second trench 36b. The second drain contact plug 22b is exposed through the third trench 36c. The first drain contact plug 22a, the first source contact plug 24a, the second drain contact plug 22b and the second source contact plug 24b are preferably tungsten, copper or other metals. The first drain contact plug 22a, the first source contact plug 24a, the second drain contact plug 22b and the second source contact plug 24b are tungsten.

As shown in <FIG>, a metal oxide material layer <NUM> and a top electrode material layer <NUM> are formed in sequence to conformally fill into the first trench 36a, the second trench 36b, the third trench 36c and the fourth trench 36d, and to cover the metal interlayer dielectric layer <NUM>. The metal oxide material layer <NUM> includes tantalum oxide, hafnium oxide or titanium oxide. The top electrode material layer <NUM> includes titanium nitride or tantalum nitride. In this embodiment, the metal oxide material layer <NUM> is tantalum oxide. The top electrode material layer <NUM> is tantalum nitride. The metal oxide material layer <NUM> and the top electrode material layer <NUM> can be made by sputtering.

Please refer to <FIG> and <FIG>. A photoresist <NUM> is formed to cover a memory cell predetermined region M within the first trench 36a, expose a metal connection region N within the first trench 36a and expose the entire logic element region B. Please refer to <FIG>, <FIG> and <FIG>, a second patterning process <NUM> is performed to pattern the metal oxide material layer <NUM> and the top electrode material layer <NUM> by taking the photoresist <NUM> as a mask to form a metal oxide layer <NUM> and a top electrode <NUM>. The metal oxide layer <NUM> and the top electrode <NUM> are located within the memory cell predetermined region M. Now, the top electrode <NUM>, the metal oxide layer <NUM> and the first drain contact plug 22a form a resistive random access memory (RRAM) <NUM>. The first drain contact plug 22a serves as a bottom electrode of the RRAM <NUM>. The second patterning process <NUM> is preferably an etching process. During the etching process of the second patterning process <NUM>, the hard mask <NUM>, the first drain contact plug 22a, the first source contact plug 24a, the second drain contact plug 22b and the second source contact plug 24b serve as a stop layer. After the second patterning process <NUM>, the photoresist <NUM> is removed. While removing the photoresist <NUM>, the top electrode <NUM> can protect the metal oxide layer <NUM> from being damaged by cleaning solution used for removing the photoresist <NUM>.

As shown in <FIG>, a buffer layer <NUM> and a metal layer <NUM> are formed in sequence to fill in the first trench 36a, the second trench 36b, the third trench 36c and the fourth trench 36d, and cover the interlayer dielectric layer <NUM> and the RRAM <NUM>. As shown in <FIG>, a planarization process <NUM> is performed to remove the hard mask <NUM>, the metal oxide layer <NUM>, the top electrode <NUM>, the buffer layer <NUM> and the metal layer <NUM> outside of the first trench 36a, and to remove the hard mask <NUM>, the buffer layer <NUM> and the metal layer <NUM> outside of the second trench 36b, the third trench 36c and the fourth trench 36d. Now, the metal layer <NUM> within the first trench 36a serves as a bit line of the first transistor 12a. The metal layer <NUM> within the fourth trench 36d serves as a source line of the first transistor 12a. The metal layer <NUM> within the second trench 36b serves as a source line of the second transistor 12b. The metal layer <NUM> within the third trench 36c serves as a drain line of the second transistor 12b. Now, an RRAM structure <NUM> of the present invention is completed.

<FIG> depicts a RRAM structure not forming part of the invention. <FIG> shows a three-dimensional view of the RRAM structure in <FIG>. In order to show the RRAM structure clearly, the inlayer dielectric layer, the metal interlayer dielectric layer and all gate contact plugs are omitted in <FIG>.

Please refer to <FIG> and <FIG>. An RRAM structure <NUM> includes a substrate <NUM>. The substrate <NUM> is divided into a memory cell region A and a logic element region B. A first transistor 12a and a second transistor 12b are disposed on the substrate <NUM>. The first transistor 12a is disposed within the memory cell region A, and the second transistor 12b is disposed within the logic element region B. Numerous shallow trench isolations <NUM> are disposed within the substrate <NUM> and at two sides of the first transistor 12a and the second transistor 12b. The first transistor 12a includes a first gate structure 14a, a first source 18a and a first drain 16a. The second transistor 12b includes a second gate structure 14b, a second source 18b and a second drain 16b. An interlayer dielectric layer <NUM> covers the substrate <NUM>, the first transistor 12a and the second transistor 12b. A first drain contact plug 22a, a first source contact plug 24a, a second drain contact plug 22b and a source contact plug 24b penetrate the interlayer dielectric layer <NUM>. Moreover, the first drain contact plug 22a contacts the first drain 16a. The first source contact plug 24a contacts the first source 18a. The second drain contact plug 22b contacts the second drain 16b. The second source contact plug 24b contacts the second source 18b. The first gate contact plug 26a penetrates the interlayer dielectric layer <NUM> to contact the first gate structure 14a. The second gate contact plug 26b penetrates the interlayer dielectric layer <NUM> to contact the second gate structure 14b.

A metal interlayer dielectric layer <NUM> is disposed on the first drain contact plug 22a and covers the interlayer dielectric layer <NUM>. An RRAM <NUM> is disposed on the first drain 16a and within a first trench 36a within the metal interlayer dielectric layer <NUM>. The RRAM <NUM> includes the first drain contact plug 22a, the metal oxide layer <NUM> and the top electrode <NUM>. The first drain contact plug 22a serves as a bottom electrode of the RRAM <NUM>. The metal oxide layer <NUM> contacts the drain contact plug 22a and the top electrode <NUM> contacts the metal oxide layer <NUM>. Furthermore, a buffer layer <NUM> and a metal layer <NUM> are disposed within the first trench 36a. The buffer layer <NUM> is disposed between the metal layer <NUM> and top electrode <NUM>. The metal layer <NUM> and the buffer layer <NUM> are disposed within a fourth trench 36d within the metal interlayer dielectric layer <NUM>. The buffer layer <NUM> within the fourth trench 36d contacts the first source contact plug 24a. The metal layer <NUM> within the first trench 36a serves as a bit line of the first transistor 12a. The metal layer <NUM> within the fourth trench 36d serves as a source line of the first transistor 12a.

Moreover, the first trench 36a is divided into a memory cell predetermined region M and a metal connection region N. The RRAM <NUM> is disposed within the memory cell predetermined region M. In other words, the metal oxide layer <NUM> and the top electrode <NUM> are within the memory cell predetermined region M. However, the metal oxide layer <NUM> and the top electrode <NUM> are not within the metal connection region N, and the metal layer <NUM> and the buffer layer <NUM> are within the metal connection region N.

Moreover, a second trench 36b and a third trench 36c are disposed within the logic element region B. The metal layer <NUM> and the buffer layer <NUM> are also disposed within the second trench 36b and the third trench 36c. A top surface of the metal layer <NUM> within the first trench 36a, the second trench 36b, the third trench 36c and the fourth trench 36d is aligned with a top surface of the metal interlayer dielectric layer <NUM>. Moreover, the metal oxide layer <NUM> forms a U-shaped profile. The U-shaped profile includes two ends. The two ends are also aligned with the top surface of the metal interlayer dielectric layer <NUM>. The top surface of the buffer layer <NUM> and the top surface of the top electrode <NUM> are also aligned with the top surface of the metal interlayer dielectric layer <NUM>. The first drain contact plug 22a, the first source contact plug 24a, the second drain contact plug 22b and the second source contact plug 24b are preferably tungsten. The metal oxide layer <NUM> is tantalum oxide. The top electrode <NUM> is tantalum nitride. However, the top electrode <NUM> can be made of other conductive materials such as hafnium, zirconium, aluminum, tantalum, titanium, chromium, tungsten, copper, cobalt, palladium or platinum. The metal oxide layer <NUM> can be hafnium oxide, aluminum oxide, lanthanum oxide, yttrium oxide or zirconium oxide.

Claim 1:
A fabricating method of a resistive random access memory structure (<NUM>), comprising:
providing a substrate (<NUM>), wherein a first transistor (12a) is disposed on the substrate (<NUM>), the first transistor (12a) comprises a first gate structure (14a), a first source (18a) and a first drain (16a), a first drain contact plug (22a) contacts the first drain (16a), and an interlayer dielectric layer (<NUM>) covers the substrate (<NUM>) and the first transistor (12a);
forming a metal interlayer dielectric layer (<NUM>) covering the interlayer dielectric layer (<NUM>);
performing a first patterning process to etch the metal interlayer dielectric layer (<NUM>) to form a first trench (36a), and wherein the first drain contact plug (22a) is exposed through the first trench (36a);
forming a metal oxide material layer (<NUM>) and a top electrode material layer (<NUM>) in sequence to fill in the first trench (36a) and cover the metal interlayer dielectric layer (<NUM>);
performing a second patterning process (<NUM>) to pattern the metal oxide material layer (<NUM>) and the top electrode material layer (<NUM>) to form a metal oxide layer (<NUM>) and a top electrode (<NUM>), wherein the top electrode (<NUM>), the metal oxide layer (<NUM>) and the first drain contact plug (22a) form a resistive random access memory, RRAM, (<NUM>);
forming a metal layer (<NUM>) filling in the first trench (36a) and covering the metal interlayer dielectric layer (<NUM>) and the RRAM (<NUM>); and
performing a planarization process (<NUM>) to remove the metal oxide layer (<NUM>), the top electrode (<NUM>) and the metal layer (<NUM>) outside of the first trench (36a).