Patent Description:
Microprocessors, also known as "processors," perform computational tasks for a wide variety of applications. A conventional microprocessor includes one or more central processing units (CPUs) also known as processor cores. The processor is realized in a processor-based system that includes a memory system that is accessed to retrieve computer instructions that are executed by the processor to perform tasks. The memory system is also accessed to retrieve data that is used for execution of computer instructions. Results of the executed computer instructions can be stored as data in the memory system. The memory system includes a primary or system memory that is located on-chip or off-chip with the processor and is configured to retrieve and store data associated with a physical memory address also known as a physical address (PA) provided by the processor. The memory system may also include a cache memory system that includes one or more levels of cache memory that is faster memory than the system memory and is configured to store data for a subset of the PAs for data that is more often accessed by the processor for improved memory access performance.

Operating systems that execute processes on a processor may be configured to use virtual memory as a virtual memory system. In virtual memory systems, each process is given the impression that a larger number of memory addresses are available for retrieving and storing data than PAs in the memory system. For example, each CPU in a processor may have larger VA space of 0x00000000-0x7FFFFFFF that must be mapped to a smaller PA space of 0x00000000-0x00FFFFFF in the memory system for a given process. When a process requests access to data in memory, the process provides a memory address that is a virtual address (VA) based on the larger PA space. The VA must be mapped to an actual PA in the memory system where the data is to be stored or retrieved. In this regard, each CPU in a processor may contain a memory management unit (MMU) that is employed to translate VAs to PAs. Most processor architectures support an in-memory table called a "page table" to map VAs to PAs. A page table is the data structure that contains one page table entry (PTE) per memory page to map a VA to a PA. Most page tables have multiple levels that depend upon the base page size, the number of page table entries at each level, and the number of bits of VA space supported. <FIG> illustrates an example of a multiple level page table <NUM> that includes three (<NUM>) levels of level page tables <NUM>(<NUM>)-<NUM>(<NUM>) that is configured to be accessed to convert a VA <NUM> to a PA. The level page tables <NUM>(<NUM>)-<NUM>(<NUM>) are organized to provide for a base page size of <NUM> Kilobytes (KB) where the number of PTEs at each page table level is <NUM> (i.e., addressable by <NUM> bits) with a <NUM> bit VA space supported. The top level (level <NUM>) page table <NUM>(<NUM>) is at level <NUM> and is indexed by a level <NUM> index in bits <NUM>-<NUM> of the VA <NUM>. The page table entries (entry <NUM>-entry <NUM>) of the level <NUM> page table <NUM>(<NUM>) point to one of an 'X' number of level <NUM> page tables <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X), which is then indexed by a level <NUM> index in bits <NUM>-<NUM> of the VA <NUM>. The page table entries in the level <NUM> page table <NUM>(<NUM>) points to one of 'Y' number of level <NUM> page tables <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y), which is then indexed by a level <NUM> index in bits <NUM>-<NUM> of the VA <NUM>. In this example, page table entries accessed across the level page tables <NUM>(<NUM>)-<NUM>(<NUM>) in the page table <NUM> identify a PA of a <NUM> KB page in physical memory. The offset bits of PA for the VA <NUM> is the offset in the VA <NUM> in bits <NUM>-<NUM> in this example.

MMUs typically provide a hardware page table walker architecture to translate a VA to a PA. For a given VA, the page table walker walks the page table from the top and descends down the page table levels until it finds the leaf PTE that contains the PA for the VA. The page table walk involves memory references at each level of page table which can be time consuming. To address this page table walk inefficiency, MMUs typically include a high-speed cache memory called a translation lookaside buffer (TLB) to cache the most recent VA to PA translations. In response to a memory address request where a VA to PA translation is required, the MMU first accesses in the TLB based on the VA of memory access request. If the VA to PA translation is not present in the TLB, a TLB miss occurs and the MMU walks the page table until it finds the VA to PA translation which is also then loaded in the TLB for future accesses. If the VA to PA translation is present in the TLB, this is a TLB hit, and a page table walk of the page table is avoided. So, the hit rate to the TLB is a critical part of the memory access performance of a memory system in processor-based system.

When a workload is executed on a CPU, multiple processes and the operating system kernel compete for entries of the TLB in the MMU. A Least Recently Used (LRU) algorithm may be used by the MMU to evict older entries in the TLB as new entries are inserted in the TLB as a result of TLB misses and page table walks. As the stress of the workload on memory increases, the TLB can start to thrash, meaning TLB misses and resulting evictions and insertions occur frequently which degrades performance. At the MMU hardware level, there are two ways to address this issue. One solution is to increase the size of the TLB to make the TLB misses occur less frequently. A second solution is to provide a cache of intermediate page table pointers in the MMU. In this scenario, when a TLB miss occurs, the page table walker looks in this cache of intermediate page table pointers for a matching intermediate page table. On a cache hit, the page table walker starts the page table walk from the matching intermediate page table instead of from the top level page table to shorten the time to walk the page table. However, cost and complexity of the MMU hardware is increased by each of these solutions. Also, these solutions may only ultimately delay eventual TLB thrashing. This problem is also further exacerbated in virtual environments. When a guest virtual machine runs on a host computer, the guest virtual machine has its own page table that is used to translate guest VAs to guest PAs. The host computer also has its own page table that is used to translate guest PAs to host PAs. Since memory can only be accessed by a CPU using a host PA, every guest PA has to be translated by the CPU to its host PA. When a page table walker walks the guest page table, it needs to translate a guest PA to a host PA at every level of the guest page table in order to access the guest intermediate page table at that level. The translation overhead may be even greater for guests running on a nested hypervisor.

<CIT> describes a method of intercepting a guest software execution of a translation insertion operation, and performing the translation insertion operation using host software. For example, the host software may obtain a requested translation from a guest virtual address to a host physical address and provide it to memory management unit resources.

<CIT> describes a memory management unit (MMU). The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.

Aspects disclosed herein include process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system. The processor-based system includes a processor that has one or more central processing units (CPUs) each configured to execute computer software instructions for processes. The processor-based system also includes a memory system that includes a main physical memory that is addressable by a PA. The processor is a virtual memory system that employs virtual addressing to make available memory to a memory space greater than the number of physical memory space in the main system memory of the processor-based system. In certain examples, either a shared or dedicated MMU for each CPU is provided for converting VAs to PAs. The MMUs are associated with a TLB (the "MMU TLB") and a page table (which is a memory circuit) in a system memory. The system memory is a memory that is fully addressable by the PA space of the processor-based system. The MMU TLB is a cache memory associated with a MMU and is configured to cache page table entries in the page table to avoid the need to fully walk the page table if a page table entry in the page table for the VA to PA translation is contained in the MMU TLB.

In exemplary aspects disclosed herein, to augment an MMU TLB to reduce either having to walk the page table or perform a full page table walk to translate a VA to a PA, the processor-based system also supports an in-memory TLB allocated in the system memory. In this regard, in response to an MMU TLB miss for a VA to a PA translation, an in-memory TLB is accessed to determine if a page table entry for the VA to PA translation is contained in the in-memory TLB. If a page table entry for the VA to PA translation is contained in the in-memory TLB, the page table entry in the in-memory TLB is used to perform the VA to PA translation. In this manner, additional page table entries can be cached for VA to PA translation without having to expand the size of an MMU TLB. The in-memory TLB can be sized to provide a higher hit rate if desired. If a page table entry for the VA to PA translation is not contained in the in-memory TLB, the MMU walks its page table to perform the VA to PA translation.

In examples disclosed herein, a, dedicated in-memory TLB is supported in system memory for each process in the processor and which are not shared across processes, so that one process's cached page table entries do not displace another process's cached page table entries. In this regard, each CPU in the processor supports storing of pointer addresses to the in-memory TLBs in system memory so that the MMUs in the CPUs can access the dedicated in-memory TLB corresponding to a particular process. A dedicated in-memory TLB may also be supported for an operating system kernel and/or a hypervisor that supervises virtualization of guest processes executing on a host CPU in examples disclosed herein. When a process is scheduled to execute in a CPU, the in-memory TLB address stored for such process can be loaded into loaded into a designated register in the CPU. This allows the page table walker circuit of the MMU to access the dedicated in-memory TLB for the executing process for performing VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB for an executing process, the page table walker circuit of the MMU can walk the page table. Supporting dedicated in-memory TLBs per process also allows allocation of different sized in-memory TLBs for different processes, if desired, to have different sized in-memory TLBs, which may be based on their memory access patterns and the number of process threads sharing an in-memory TLB as examples. In another example, the in-memory TLBs being in system memory is direct memory-mapped to memory addresses, which can also simplify the cached page table entry replacement policy.

In other examples, the in-memory TLBs can be configured to cache different levels of page table entries in a page table into an MMU TLB. In another example, the in-memory TLBs can be configured to cache only certain levels of level page tables in a page table into an MMU TLB. For example, in-memory TLBs associated with a given MMU can be configured to cache page table entries from a higher level page table than the page table entries cached in the MMU TLB for enhanced performance. Thus, if a TLB hit occurs on any cached non-leaf page table entries in the MMU TLB, only a lower level page table will need to be walked by the page table walker circuit to translate a VA to a PA. If a TLB miss occurs in the MMU TLB, the page table walker circuit can consult the in-memory TLB for a matching page table entry to translate the VA to a PA.

In this regard, in one exemplary aspect, a memory management system in a CPU in a processor of a processor-based system is provided. The memory management system comprises a page table in a system memory of the processor-based system, the page table comprising at least one level page table each comprising a plurality of page table entries each addressable by a VA and configured to store a PA associated with the VA, an MMU TLB comprising a plurality of MMU TLB entries each configured to store a cached page table entry in the page table, an in-memory TLB in the system memory, the in-memory TLB comprising a plurality of in-memory TLB entries each configured to store a cached page table entry in the page table, a page table walker circuit configured to access the plurality of page table entries in the at least one level page table in the page table based on the VA, and an MMU circuit. The MMU circuit is configured to receive a memory access request comprising a VA based on a computer software instruction executed for a process in the CPU and determine if an MMU TLB entry in the MMU TLB contains a page table entry comprising a PA corresponding to the VA. In response to determining the MMU TLB does not contain an MMU TLB entry containing a page table entry directly corresponding to the VA, the MMU circuit is also configured to determine if a VA stored in an in-memory TLB entry corresponding to the VA in an in-memory TLB allocated to the process in the system memory in the processor-based system matches the VA of the memory access request, and in response to determining the VA stored in the in-memory TLB entry matches the VA of the memory access request, translate the VA to a PA based the accessed page table entry in the in-memory TLB entry corresponding to the VA.

In another exemplary aspect, a method of translating a VA to a PAin a CPU in a processor of a processor-based system is provided. The method comprises receiving a memory access request comprising a VA based on a computer software instruction executed for a process in the CPU and determining if an MMU translation lookaside buffer (TLB) entry in an MMU TLB comprising a plurality of MMU TLB entries each configured to store a cached page table entry in a page table contains a page table entry comprising a PA corresponding to the VA. The page table entry is contained in the page table comprising at least one level page table each comprising a plurality of page table entries each addressable by a VA and configured to store a PA associated with the VA. In response to determining the MMU TLB does not contain an MMU TLB entry containing a page table entry corresponding to the VA, the method further comprises determining if a VA stored in an in-memory TLB entry corresponding to the VA in an in-memory TLB in the system memory of the processor-based system that is allocated to the process in a system memory in the processor-based system matches the VA of the memory access request. In response to determining the VA stored in the in-memory TLB entry matches the VA of the memory access request, the method also comprises translating the VA to a PA based the accessed page table entry in the in-memory TLB entry corresponding to the VA.

In another exemplary aspect, processor-based system is provided. The processor-based system comprises a system memory and a processor comprising one or more CPUs each configured to execute computer instructions in an operating system software program and one or more processes. Each CPU among the one or more CPUs comprises a memory management system, comprising a page table in the system memory, the page table comprising a plurality of level page tables each comprising a plurality of page table entries each addressable by a VA and configured to store a PA associated with the VA, an MMU TLB comprising a plurality of MMU TLB entries each configured to store a cached page table entry in the page table, an in-memory TLB in the system memory, the in-memory TLB comprising a plurality of in-memory TLB entries each configured to store a cached page table entry in the page table, a page table walker circuit configured to access a page table entry in at least one level page table in the page table based on the VA, and an MMU circuit. The MMU circuit is configured to receive a memory access request comprising a VA based on a computer software instruction executed for a process among the one or more processes in a CPU among the one or more CPUs and determine if an MMU TLB entry in the MMU TLB contains a page table entry comprising a PA corresponding to the VA. In response to determining the MMU TLB does not contain an MMU TLB entry containing a page table entry corresponding to the VA, the MMU circuit is also configured to determine if a VA stored in an in-memory TLB entry corresponding to the VA in an in-memory TLB allocated to the process in the system memory in the processor-based system matches the VA of the memory access request. In response to determining the VA stored in the in-memory TLB entry matches the VA of the memory access request, the MMU circuit is also configured to translate the VA to a PA based the accessed page table entry in the in-memory TLB entry corresponding to the VA.

In examples disclosed herein, a, dedicated in-memory TLB is supported in system memory for each process in the processor and which are not shared across processes, so that one process's cached page table entries do not displace another process's cached page table entries. In this regard, each CPU in the processor supports storing of pointer addresses to the in-memory TLBs in system memory so that the MMUs in the CPUs can access the dedicated in-memory TLB corresponding to a particular process. A dedicated in-memory TLB may also be supported for an operating system kernel and/or a hypervisor that supervises virtualization of guest processes executing on a host CPU in examples disclosed herein. When a process is scheduled to execute in a CPU, the in-memory TLB address stored for such process can be loaded into an in-memory TLB register in the CPU. This allows the page table walker circuit of the MMU to access the dedicated in-memory TLB for the executing process for performing VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB for an executing process, the page table walker circuit of the MMU can walk the page table. Supporting dedicated in-memory TLBs per process also allows allocation of different sized in-memory TLBs for different processes, if desired, to have different sized in-memory TLBs, which may be based on their memory access patterns and the number of process threads sharing an in-memory TLB as examples. In another example, the in-memory TLBs being in system memory is direct memory-mapped to memory addresses, which can also simplify the cached page table entry replacement policy.

Before discussing examples of process dedicated mTLBs for augmenting an MMU TLB for translating VAs to PAs in a processor-based system, an exemplary processor-based system that includes a processor with one or more CPUs is first discussed with regard to <FIG>.

In this regard, <FIG> is a diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> configured to issue memory requests (i.e., data read and data write requests) to a memory system <NUM> that includes a cache memory system <NUM> and a system memory <NUM>. The system memory <NUM> is a memory that is fully addressable by the PA space of the processor-based system <NUM>. For example, the system memory <NUM> may be a dynamic random access memory (DRAM) provided in a separate DRAM chip. The processor <NUM> includes one or more respective CPUs <NUM>(<NUM>)-<NUM>(N), wherein 'N' is a positive whole number representing the number of CPUs included in the processor <NUM>. The processor <NUM> can be packaged in an integrated circuit (IC) chip <NUM>. The cache memory system <NUM> includes one or more cache memories <NUM>(<NUM>)-<NUM>(X) that may be at different hierarchies in the processor-based system <NUM> and that are logically located between the CPUs <NUM>(<NUM>)-<NUM>(N) and the system memory <NUM>, where 'X' is a positive whole number representing the number of CPUs included in the processor <NUM>. A memory controller <NUM> controls access to the system memory <NUM>. For example, a CPU <NUM>(<NUM>)-<NUM>(N) as a requesting device may issue a data request <NUM> to read data in response to processing a load instruction. The data request <NUM> includes a target address of the data to be read from memory. Using CPU <NUM>(<NUM>) as an example, if the requested data is not in a private cache memory <NUM>(<NUM>) (i.e., a cache miss to cache memory <NUM>(<NUM>)) which may be considered a level one (L1) cache memory, the private cache memory <NUM>(<NUM>) sends the data request <NUM> over an interconnect bus <NUM> in this example to a shared cache memory <NUM>(X) shared with all of the CPUs <NUM>(<NUM>)-<NUM>(N), which may be a level (<NUM>) cache memory. The requested data in the data request <NUM> is eventually either fulfilled in a cache memory <NUM>(<NUM>)-<NUM>(X) or the system memory <NUM> if not contained in any of the cache memories <NUM>(<NUM>)-<NUM>(X).

The processor-based system <NUM> in <FIG> is configured to support virtual addressing. In this regard, an operating system that executes processes on the processor <NUM> can use virtual memory as a virtual memory system by issuing VAs in memory access requests. In virtual memory systems, each process is given the impression that a larger number of memory addresses (i.e., VAs) are available in the memory system <NUM> for retrieving and storing data than PAs in the system memory <NUM>. When a process requests access to data in the memory system <NUM>, the process provides a memory address that is a VA. The VA must then be mapped to an actual PA in the memory system <NUM> where the data is to be stored or retrieved. In this regard, each CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG> may contain or have an associated an MMU <NUM>(<NUM>)-<NUM>(N) that is employed to translate VAs to PAs.

<FIG> is a schematic diagram of an exemplary memory management system <NUM> that includes an MMU circuit <NUM> associated with CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG> that translates a VA to a PA for memory access requests issued by a respective associated CPU <NUM>(<NUM>)-<NUM>(N). The memory management system 300includes a page table <NUM> and an MMU TLB <NUM> in system memory <NUM> that are accessed by the MMU circuit <NUM> for converting VAs to PAs. The page table <NUM> is a memory circuit that includes a number of page table entries <NUM>(<NUM>)-<NUM>(E) that are indexable based on the VA to provide information for translation from the PA to a VA. The page table <NUM> is accessed or "walked" by a page table walker circuit <NUM> in the MMU circuit <NUM> based on the incoming VA, in response to a TLB miss and in-memory TLB miss (discussed below), in response to a computer software instruction executed by a respective CPU <NUM>(<NUM>)-<NUM>(N) to determining if page table entries <NUM>(<NUM>)-<NUM>(E) containing information to translate the VA to a PA is present. If so, a "page table hit" <NUM> is issued by the page table <NUM>, and the MMU circuit <NUM> provides the PA for the memory access request to the MMU TLB <NUM>. The translated PA is also written as a "TLB write" <NUM> to the MMU TLB <NUM>. If the page table entries <NUM>(<NUM>)-<NUM>(E) in the page table <NUM> do not contain information to translate the VA to a PA, a "page table miss" <NUM> is issued by the page table <NUM>, and a memory management fault and trap occurs or an exception is communicated to the operating system to be processed. The page table <NUM> may include a number of page table levels that have to be "walked" by the page table walker circuit <NUM> to translate the incoming VA to a PA.

To increase performance in translating VAs to PAs, a VA translated by accessing the page table <NUM> and the PA information resulting from an issued "page table hit" <NUM> is also cached (i.e., written) in the MMU TLB <NUM>. The MMU TLB <NUM> is a cache memory that is faster memory than the page table <NUM> in this example. The MMU TLB <NUM> has a plurality of MMU TLB entries <NUM>(<NUM>)-<NUM>(T) that are each configured to store a PA associated with a given VA. The VA stored in the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) are tags that can be compared against an incoming VA in a received memory access request before accessing the page table <NUM> to determine if any MMU TLB entry <NUM>(<NUM>)-<NUM>(T) is present in the MMU TLB <NUM> that has the translated PA. If so, a "TLB hit" <NUM> is issued by the MMU TLB <NUM> without the page table <NUM> having to be walked, and the MMU circuit <NUM> provides the PA in the hit MMU TLB entry <NUM>(<NUM>)-<NUM>(T) for the memory access request. If the incoming VA in a received memory access request is not present in any MMU TLB entry <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM>, a "TLB miss" <NUM> is issued, and the VA can be used to walk the page table <NUM> to translate the incoming VA to the PA as discussed above.

When a workload is executed on a CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG>, multiple processes and the operating system kernel compete for access to the MMU TLB <NUM>. As the stress of the workload on memory system <NUM> increases, the MMU TLB <NUM> can start to thrash, meaning TLB misses and resulting evictions and insertions occur frequently, which degrades performance. In exemplary aspects disclosed herein, to augment the MMU TLB <NUM> to reduce the number of page table <NUM> walks to translate a VA to a PA, the memory management system <NUM> in <FIG> also supports in-memory TLBs <NUM>(<NUM>)-<NUM>(I) allocated in system memory <NUM>. In response to a TLB miss to the MMU TLB <NUM> for a VA to a PA translation, an in-memory TLB <NUM>(<NUM>)-<NUM>(I) can be accessed to determine if a page table entry in an in-memory TLB entry in the accessed in-memory TLB <NUM>(<NUM>)-<NUM>(I) is present to translate the VA to its PA. Each in-memory TLB <NUM>(<NUM>)-<NUM>(I) contains a plurality of in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) that are each configured to cache a page table entry <NUM>(<NUM>)-<NUM>(E) in the page table <NUM>. If a page table entry <NUM>(<NUM>)-<NUM>(E) for the VA to PA translation is contained in an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the accessed in-memory TLB <NUM>(<NUM>)-<NUM>(I), such page table entry <NUM>(<NUM>)-<NUM>(E) in the accessed in-memory TLB <NUM>(<NUM>)-<NUM>(I) is used to perform the VA to PA translation. In this manner, additional page table entries can be cached for VA to PA translations without having to expand the size of the MMU TLB <NUM>. System memory <NUM>, which is more abundant and cheaper for a given memory size, is allocated for the in-memory TLBs <NUM>(<NUM>)-<NUM>(I). If a page table entry for the VA to PA translation is not contained in the accessed in-memory TLB <NUM>(<NUM>)-<NUM>(I), the MMU circuit <NUM> causes the page table walker circuit <NUM> to walk the page table <NUM> as previously discussed above to perform the VA to PA translation.

As will be discussed in more detail below, the memory management system <NUM> in <FIG> is configured to support allocation of each in-memory TLB <NUM>(<NUM>)-<NUM>(I) in system memory <NUM> being dedicated to a specific process executed in the CPUs <NUM>(<NUM>)-<NUM>(N) and thus not shared between different processes. For example, in-memory TLB <NUM>(<NUM>) is dedicated for one process executed in the CPUs <NUM>(<NUM>)-<NUM>(N), whereas in-memory TLB <NUM>(X) is assigned to a different process executing in the CPUs <NUM>(<NUM>)-<NUM>(N). In this regard, each CPU <NUM>(<NUM>-<NUM>(N) in the processor <NUM> in <FIG> supports storing addresses of the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) in system memory <NUM> allocated to respective processes so that page table entries cached in in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(B) in the in-memory TLB <NUM>(<NUM>) for example, do not displace page table entries in in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(B) in in-memory TLB <NUM>(I). In this manner, the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) are not shared across processes. The in-memory TLBs <NUM>(<NUM>)-<NUM>(I) can be shared across multiple CPUs <NUM>(<NUM>)-<NUM>(N) as multiple CPUs <NUM>(<NUM>)-<NUM>(N) can execute the same process. A dedicated in-memory TLB may also be supported for an operating system kernel and/or a hypervisor in the processor <NUM> that supervises virtualization of guest processes executed on a host CPU <NUM>(<NUM>)-<NUM>(N) as examples.

When a process is scheduled to execute in CPU(s) <NUM>(<NUM>)-<NUM>(N), an in-memory TLB address stored for such process can be loaded into the MMU circuit <NUM> associated with the CPU <NUM>(<NUM>)-<NUM>(N). This allows the MMU circuit <NUM> to access the dedicated in-memory TLB <NUM>(<NUM>)-<NUM>(I) for executing the process for performing VA to PA translations in the event of a TLB miss to the MMU TLB <NUM> and a TLB hit to the in-memory TLB <NUM>(<NUM>)-<NUM>(I), which may avoid the page table walker circuit <NUM> having to walk the page table <NUM>. If a TLB miss occurs to the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for an executed process, the page table walker circuit <NUM> can walk the page table <NUM> as previously discussed. The memory management system <NUM> supporting the process dedicated in-memory TLBs <NUM>(<NUM>)-<NUM>(I) can also allow allocation of different sized in-memory TLBs <NUM>(<NUM>)-<NUM>(I) for different processes, if desired. It may be desired to provide different sized in-memory TLBs <NUM>(<NUM>)-<NUM>(I) based on their memory access patterns by respective processes and the number of process threads sharing an in-memory TLB <NUM>(<NUM>)-<NUM>(I) as examples. In another example, the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) being in system memory <NUM> allows the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) to be direct memory-mapped to memory addresses, which can also simplify the cached page table entry replacement policy. The examples discussed below explain in more exemplary detail operations of an MMU circuit like the MMU circuit <NUM> in <FIG> accessing its in-memory TLBs <NUM>(<NUM>)-<NUM>(I) for a given process being executed in the CPUs <NUM>(<NUM>)-<NUM>(N) to translate VAs to PAs in memory access requests issued as a result of executing the process.

In this non-limiting example, the bit size of the VA memory addresses supported by the processor-based system <NUM> in <FIG> is <NUM> bits. In this regard, <FIG> illustrates an exemplary bit format of an exemplary VA <NUM> supported by the processor-based system <NUM> that shows the bit assignment of bits <NUM>-<NUM>. Bits <NUM>-<NUM> are free bits that are unused or can be reserved for additional functionality. The address space of the VA <NUM> is <NUM> bits that spans bits <NUM>-<NUM> to support <NUM><NUM> virtual memory locations in the processor-based system. The bits of the VA <NUM> can be used to index a page table, which may be employed as the page table <NUM> in the memory management system <NUM> in <FIG>. <FIG> illustrates an exemplary page table <NUM> that can be provided in the MMU circuit <NUM> in <FIG>, wherein the page table <NUM> includes four (<NUM>) levels of level page tables <NUM>(<NUM>)-<NUM>(<NUM>) each containing page table entries addressable by the VA <NUM>. Each page table entry in the level page tables <NUM>(<NUM>)-<NUM>(<NUM>) is either a leaf page table entry that is not used to further access another page table entry and can be directly associated with a memory page in physical memory in the system memory <NUM>, or a non-leaf page table entry that is used to further access another page table entry to obtain the PA of a memory page in the system memory <NUM> and can be cached in this example.

With continuing reference to <FIG>, the level page tables <NUM>(<NUM>)-<NUM>(<NUM>) in the page table <NUM> are organized to provide for a base page size of <NUM> Kilobytes (KB) where the number of page table entries in each level page table <NUM>(<NUM>)-<NUM>(<NUM>) is <NUM> (i.e., addressable by <NUM> bits) with a <NUM> bit VA <NUM> address space supported. The level page table <NUM>(<NUM>) contains page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) and designed to not be cached in the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) of <FIG> in this example. The level <NUM> page table <NUM>(<NUM>) is at level <NUM> in the page table <NUM> and is indexed by a level <NUM> index <NUM>(<NUM>) in bits <NUM>-<NUM> of the VA <NUM>. Page table entries (<NUM> or <NUM><NUM> entries) <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) of the level <NUM> page table <NUM>(<NUM>) each point to one of an 'X' number of level <NUM> page tables <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X), which is then indexed by a level <NUM> index <NUM>(<NUM>) in bits <NUM>-<NUM> of the VA <NUM>. The page table entries (<NUM> or <NUM><NUM> entries) <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(X)(<NUM>) (i.e., level page table at level (<NUM>), <NUM>-X number of level <NUM> page table, and <NUM>-<NUM> entries per level page table) in each of the level <NUM> page tables <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X) points to one of 'Y' number of level <NUM> page tables <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y), which is then indexed by a level <NUM> index <NUM>(<NUM>) in bits <NUM>-<NUM> of the VA <NUM>. In this example, page table entries <NUM> accessed across the level page tables <NUM>(<NUM>), <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X), <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y) in the page table <NUM> identify a <NUM> KB page PA in the system memory <NUM> in the processor-based system <NUM> in <FIG>. The offset bits of PA for the VA <NUM> is the offset in the VA <NUM>, which is in bits <NUM>-<NUM> of the VA <NUM> in this example.

As an example, as will be discussed in more detail below, the memory management system <NUM> in <FIG> can be configured to cache different levels of level page tables <NUM>(<NUM>), <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X), <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y) in different memory structures. For example, the page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) of the level <NUM> page table <NUM>(<NUM>) may be cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I), whereas the page table entries <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(X)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X) may be cached in the MMU TLB <NUM> in the MMU circuit <NUM> in <FIG>. The page table entries <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y) are leaf page table entries that can be cached in the MMU TLB <NUM>.

As discussed above, a dedicated in-memory TLB <NUM>(<NUM>)-<NUM>(I) in the memory management system <NUM> in <FIG> can be provided per process executing in the CPUs <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG>. Thus, in an example, when a thread of a process is scheduled to execute on a CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM>, a mechanism is provided to indicate the particular in-memory TLB <NUM>(<NUM>)-<NUM>(I) allocated in system memory <NUM> to the process so that the MMU circuit <NUM> can know where in the system memory <NUM> to access a dedicated in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the process. In this regard, a CPU <NUM>(<NUM>)-<NUM>(N) <NUM> can include an in-memory TLB register that contains a memory address field configured to store a memory address pointing to a PA in system memory <NUM> to an in-memory TLB <NUM>(<NUM>)-<NUM>(I) corresponding to a current process to be executed in the CPU <NUM>(<NUM>)-<NUM>(N). An example of such an in-memory TLB register <NUM> is illustrated in <FIG>. As shown in <FIG>, the in-memory TLB register <NUM> includes a memory address field <NUM> that is configured to store a physical address pointing to an in-memory TLB <NUM>(<NUM>)-<NUM>(I) corresponding to a current process to be executed in the CPU <NUM>(<NUM>)-<NUM>(N). For a host that runs directly on a CPU <NUM>(<NUM>)-<NUM>(N), such as a host hypervisor, the memory address field <NUM> could be the host PA. For a guest that runs directly on a CPU <NUM>(<NUM>)-<NUM>(N), the memory address field <NUM> could be the guest PA. Also in this example, the in-memory TLB register <NUM> includes a number of TLB entries field <NUM> that is configured to store the number of in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the contained in-memory TLB <NUM>(<NUM>)-<NUM>(I). This is so that the in-memory TLB <NUM>(<NUM>)-<NUM>(I) will know the size in terms of number of in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) allocated in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) identified by the memory address in the memory address field <NUM>. In this example, the in-memory TLB register <NUM> also includes a cache level in page table field <NUM> that is configured to store a number to indicate which levels in the level page tables <NUM> of the page table <NUM> in <FIG> to cache in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) identified in the memory address field <NUM>. Also in this example, the in-memory TLB register <NUM> includes a cache level in MMU TLB field <NUM> that is configured to store a number indicate which levels in the level page tables <NUM> of the page table <NUM> to cache in the MMU TLB <NUM>.

<FIG> illustrates an exemplary in-memory TLB entry <NUM> that represents the architecture of the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in an in-memory TLB <NUM>(<NUM>)-<NUM>(I) in <FIG> as an example. As shown therein, the in-memory TLB entry <NUM> includes a leaf or non-leaf page table entry cached field <NUM> configured to store in the in-memory TLB entry <NUM> either a leaf or non-leaf page table entry. The in-memory TLB entry <NUM> also includes a lock indicator <NUM> configured to store a lock state as the in-memory TLB entry <NUM> being in a locked state or unlocked state. For example, a '<NUM>' bit could signify an unlocked state, and a '<NUM>' could signify a locked state. As discussed below, the lock indicator <NUM> can be edited by the MMU circuit <NUM> to indicate if a given in-memory TLB entry <NUM> in an in-memory TLB <NUM>(<NUM>)-<NUM>(I) is being used in case there are two page table walkers configured to race with each other to access the read or write the same in-memory TLB entry <NUM> in an in-memory TLB <NUM>(<NUM>)-<NUM>(I). The in-memory TLB entry <NUM> also includes a VA tag field <NUM> configured to store a VA corresponding to the in-memory TLB entry <NUM> that can be used by the MMU circuit <NUM> to compare against an incoming VA to be translated to a PA to determine if the in-memory TLB entry <NUM> can be used to translate the VA to its PA. The in-memory TLB entry <NUM> in this example also includes a generation number field <NUM> configured to store a generation number. As will be discussed in more detail below, the generation number stored in the generation number field <NUM> can be used to determine if in-memory TLB entry <NUM> is valid and to provide a way to invalidate the in-memory TLB entry <NUM>.

<FIG> is a flowchart illustrating an exemplary process <NUM> of the MMU circuit <NUM> in the memory management system <NUM> in <FIG> translating a VA to a PA and accessing a process dedicated in-memory TLB <NUM>(<NUM>)-<NUM>(I) in the system memory <NUM> to translate a VA to a PA. The process <NUM> in <FIG> is discussed in conjunction with the memory management system <NUM> in <FIG> and the page table <NUM> in <FIG>. In this regard, the MMU circuit <NUM> receives a memory access request comprising a VA <NUM> based on a computer software instruction executed for a process in the CPU <NUM>(<NUM>)-<NUM>(N) (block <NUM>). The MMU circuit <NUM> determines if the MMU TLB <NUM> contains an MMU TLB entry <NUM>(<NUM>)-<NUM>(T) containing the page table entry corresponding to the VA <NUM> (block <NUM>). If the MMU TLB <NUM> contains an MMU TLB entry <NUM>(<NUM>)-<NUM>(T) containing the page table entry corresponding to the VA <NUM> (block <NUM>), this is an MMU TLB hit, and the MMU circuit <NUM> uses the PA stored in the MMU TLB entry <NUM>(<NUM>)-<NUM>(T) corresponding to the VA <NUM> to translate the VA <NUM> into its PA (block <NUM>), and the process ends (block <NUM>). If however, the MMU TLB <NUM> does not contain an MMU TLB entry <NUM>(<NUM>)-<NUM>(T) containing the page table entry corresponding to the VA <NUM> (block <NUM>), this is an MMU TLB miss, and the MMU circuit <NUM> then determines if the VA <NUM> in the VA tag field <NUM> stored in an in-memory TLB entry <NUM>(<NUM>)(<NUM>))-<NUM>(I)(B) in an in-memory TLB <NUM>(<NUM>)-<NUM>(I) allocated to the process matches the VA <NUM> of the memory access request (block <NUM>). As discussed above, the MMU circuit <NUM> can use the memory address stored in the memory address field <NUM> of the in-memory TLB register <NUM> to access the corresponding in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the process.

If the VA stored in the VA tag field <NUM> in an in-memory TLB entry <NUM>(<NUM>)(<NUM>))-<NUM>(I)(B) in an in-memory TLB <NUM>(<NUM>)-<NUM>(I) allocated to the process matches the VA <NUM> of the memory access request, the MMU circuit <NUM> uses contents of the matching in-memory TLB entry <NUM>(<NUM>)(<NUM>))-<NUM>(I)(B) (block <NUM>). This is an in-memory TLB hit. If the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) contains a leaf page table entry, the MMU circuit <NUM> translates the VA <NUM> to a PA based on the accessed page table entry in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) having a VA in the VA tag field <NUM> matching the VA <NUM> (block <NUM>). If the in-memory TLB entry <NUM>(<NUM>)(<NUM>))-<NUM>(I)(B) contains a non-leaf page table entry, the page table walker circuit <NUM> uses the non-leaf page table entry to walk the page table <NUM>. Otherwise, for an in-memory TLB miss, if the VA stored in the VA tag field <NUM> in an in-memory TLB entry <NUM>(<NUM>)(<NUM>))-<NUM>(I)(B) in an in-memory TLB <NUM>(<NUM>)-<NUM>(I) allocated to the process does not match the VA <NUM> of the memory access request (block <NUM>), this is an in-memory TLB miss, and the MMU circuit <NUM> conducts a page table walk. The MMU circuit <NUM> causes the page table walker circuit <NUM> to access the level page tables <NUM>(<NUM>)-<NUM>(<NUM>) in the page table <NUM> indexed by the VA <NUM> of the memory access request (block <NUM>) and translate the VA <NUM> to the PA contained in a page table entry in the level page tables <NUM>(<NUM>)-<NUM>(<NUM>) corresponding to the VA <NUM> (block <NUM>), and the process ends (block <NUM>).

As an example, assuming the base page size that can be determined from the page table <NUM> in <FIG> is <NUM> KB, and each intermediate level page table <NUM>(<NUM>)-<NUM>(<NUM>) has <NUM> entries. Also assume that the in-memory TLB register <NUM> discussed in <FIG> for an in-memory TLB <NUM>(<NUM>)-<NUM>(I) has a memory address of its PA in system memory <NUM> in its memory address field <NUM>, <NUM> TLB entries in the number of TLB entries field <NUM>, levels cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) as level <NUM> (bitmap represented as '<NUM>') in the levels cached in the page table levels to cache field <NUM>, and levels cached in the MMU TLB <NUM> as level <NUM> (bitmap represented as '<NUM>') in the levels cached in the page table levels to cache field <NUM>. In this example, a level <NUM> leaf page table entry <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y) points to a 4KB memory page. A level <NUM> leaf page table entry <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X) points to a 2MB memory page. A level <NUM> leaf page table entry <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) points to a <NUM> GigaByte (GB) memory page. A level <NUM> non-leaf page table entry <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X) points to a level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(Y). A level <NUM> non-leaf page table entry <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) points to a level <NUM> page table <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(X). In this example, leaf page table entries can always be cached in the MMU TLB <NUM>, non-leaf page table entries <NUM>(<NUM>)(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>)(<NUM>) can be cached in the MMU TLB <NUM>, and leaf and non-leaf level <NUM> page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) can be cached in an in-memory TLB <NUM>(<NUM>)-<NUM>(I).

In this example, the span of a single in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is <NUM> GB. For a given incoming VA <NUM> to translate into a PA, the MMU circuit <NUM> calculates the index into the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the current process for the VA <NUM> as follows. The index is the (VA / <NUM> GB) % <NUM>. If an in-memory TLB miss occurs (e.g., block <NUM> in <FIG>), the MMU circuit <NUM> causes the page table walker circuit <NUM> to walk the page table <NUM> from the top level and find the leaf page table entry <NUM> for the VA <NUM>. The leaf page table entry <NUM> is then written into the MMU TLB <NUM>. If the leaf page table entry <NUM> corresponding to the VA <NUM> is above the level <NUM> page table <NUM>(<NUM>), no further caching is done. If the leaf page table entry <NUM> corresponding to the VA <NUM> is at the level <NUM> page table <NUM>(<NUM>), it is cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) and the MMU TLB <NUM>. If the leaf page table entry <NUM> corresponding to the VA <NUM> is at the level <NUM> or level <NUM> page table <NUM>(<NUM>), <NUM>(<NUM>), the non-leaf page table entry <NUM> in the level <NUM> page table <NUM>(<NUM>) is cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) and the MMU TLB <NUM>. When the page table entry <NUM> is cached into the in-memory TLB <NUM>(<NUM>)-<NUM>(I) as an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B), the VA bits of the VA <NUM> are truncated to a <NUM> GB boundary to be stored in the VA tag field <NUM> of the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). A current generation number that is discussed in more detail below is stored in the generation number field <NUM> of the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). In this manner, it can be precisely controlled which page table levels get cached into the MMU TLB <NUM> and cached in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) for a current process.

As discussed above, when an MMU TLB hit occurs (e.g., in block <NUM> in <FIG>), this means the leaf page table entry <NUM> for the VA <NUM> is found in the MMU TLB <NUM>, and no page table walk into the page table <NUM> is required. If the leaf page table entry <NUM> has been evicted from the MMU TLB <NUM>, but the level <NUM> page table entry is still present in the MMU TLB <NUM>, the page table walker circuit <NUM> can walk the page table <NUM> from the level <NUM> page table entry <NUM>. If the level <NUM> page table entry is not found in the MMU TLB <NUM>, the MMU circuit <NUM> consults the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the current process. If an in-memory TLB hit occurs, the MMU circuit <NUM> walks from the level <NUM> page table entry stored in the in-memory TLB <NUM>(<NUM>)-<NUM>(I).

Additional functionality and variations of the process <NUM> in <FIG> of an MMU circuit <NUM> translating a VA <NUM> to a PA can be performed. For example, in response to an MMU TLB miss (e.g., block <NUM> in <FIG>), the MMU circuit <NUM> may be configured to read the VA in the VA tag field <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) of the accessed in-memory TLB <NUM>(<NUM>)-<NUM>(I). If the lock indicator <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) indicates a locked state, this means another process is using the same in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B), and this is considered an in-memory TLB miss to perform page table <NUM> walk (e.g., blocks <NUM>, <NUM> in <FIG>). If however, the lock indicator <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) indicates an unlocked state, the MMU circuit <NUM> can set the lock indicator <NUM> to a locked state. For example, a compare-and-swap (CAS) instruction can be performed on the VA tag field <NUM> in the accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to set its lock indicator <NUM> to a locked state. If the CAS instruction fails, this is considered an in-memory TLB miss to perform page table <NUM> walk (e.g., blocks <NUM>, <NUM> in <FIG>).

The MMU circuit <NUM> can then check the VA in the VA tag field <NUM> of the locked state accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) (e.g., in block <NUM> in <FIG>) to determine if the VA in the VA tag field <NUM> matches the VA <NUM> of the memory access request. If it does not match (e.g., the NO path from block <NUM> in <FIG>), this is considered an in-memory TLB miss going to block <NUM> to perform page table <NUM> walk (e.g., blocks <NUM>, <NUM> in <FIG>). The lock indicator <NUM> of the accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is set to an unlocked state. If however, the VA in the VA tag field <NUM> of the locked state accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) matches the VA <NUM> of the memory access request (e.g., the YES path from block <NUM> in <FIG>), the MMU circuit <NUM> can check the generation number in the generation number field <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to determine if the generation number is stale. As will be discussed in more detail below, one way to invalidate a stale in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B), such as if a VA-to-PA mapping is changed in the operating system, is to update the generation number in the generation number field <NUM> of the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to be invalidated such that their generation numbers are not current. A stale in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is treated as an in-memory TLB miss. However, if both the VA in the VA tag field <NUM> of the locked state accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in block <NUM> matches the VA <NUM> of the memory access request, and the generation number in the generation number field <NUM> of the accessed in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is not stale, the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) can be read and used to translate the VA <NUM> to a PA from the level <NUM> page table <NUM>(<NUM>) which is then used as a starting PA to walk the page table <NUM> (e.g., block <NUM> in <FIG>). The PA is also written back into an MMU TLB entry <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM>, and the process ends (e.g., block <NUM> in <FIG>).

If an MMU TLB miss and in-memory TLB miss occur (e.g., the NO paths from blocks <NUM> and <NUM> in <FIG>), the page table walker circuit <NUM> walks the page table <NUM> as previously discussed (e.g., blocks <NUM>, <NUM> in <FIG>). If a page table entry <NUM> found on the page table <NUM> for the VA <NUM> does not need to be cached in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B), the process ends (e.g., block <NUM> in <FIG>). Otherwise, the lock indicator <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is set unless already in a locked state. If not already in a locked state, the VA in the VA tag field <NUM> of the available in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is set to the new VA value from the instruction being executed that includes a memory access found from the walk of the page table <NUM> and the lock indicator <NUM> is set to a locked state by performing a CAS instruction on the VA tag field <NUM>. If the CAS instruction fails, the process ends (e.g., block <NUM> in <FIG>). Otherwise, the current generation number is written into the generation number field <NUM> of the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) and the page table entry <NUM> found from the walk of the page table <NUM> is written into the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). The lock indicator <NUM> is then reset to an unlocked state. Memory barriers may be required in these steps to make sure that updates are seen in the correct sequence.

If the lock indicator <NUM> in the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) indicates a locked state, this means another process is editing the same in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B), and this is considered an in-memory TLB miss to perform page table <NUM> walk (e.g., blocks <NUM>, <NUM> in <FIG>). The process ends (block <NUM>) since at this point, the page table walk of the page table <NUM> has already been completed.

Other organizations of page tables can be employed as the page table <NUM> in the MMU circuit <NUM> in <FIG>. For example, <FIG> illustrates another example of a multiple level page table <NUM> that can be included as the page table <NUM> in the MMU circuit <NUM> in <FIG> to translate the VA <NUM> to point to a <NUM> MB physical memory page. For example, <NUM> levels of level page tables <NUM>(<NUM>)-<NUM>(<NUM>) are provided. The following caching scheme can be employed. Page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) can be leaf page table entries that always get cached in the MMU TLB <NUM>. The page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) are cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I). The page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) are above the level of the page table entries cached in the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I), and thus page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) are not cached.

<FIG> illustrates another example of a multiple level page table <NUM> that can be included as the page table <NUM> in the MMU circuit <NUM> in <FIG> to translate the VA <NUM> to point to a <NUM> GB physical memory page. For example, two (<NUM>) levels of level page tables <NUM>(<NUM>)-<NUM>(<NUM>) are provided. The following caching scheme can be employed. The leaf page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) always get cached in the MMU TLB <NUM>. The leaf page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) are cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I). The page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) in the level <NUM> page table <NUM>(<NUM>) are above the level of the page table entries cached in the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I), and thus page table entries <NUM>(<NUM>)(<NUM>)-<NUM>(<NUM>)(<NUM>) are not cached.

If a page table levels to cache field <NUM> in the in-memory TLB register <NUM> in <FIG> specifies that more than one page level should be cached in the identified in-memory TLB <NUM>(<NUM>)-<NUM>(I), the in-memory TLB <NUM>(<NUM>)-<NUM>(I) can be split or partitioned into sections in the system memory <NUM> in the processor-based system <NUM> in <FIG> such that the VAs are mapped to the split in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). When an in-memory TLB <NUM>(<NUM>)-<NUM>(I) is split into multiple levels, the MMU circuit <NUM> needs to search in each level of in-memory TLBs <NUM>(<NUM>)-<NUM>(I) starting from the lowest to the highest or in parallel. This is shown by example in <FIG>. As shown in <FIG>, a <NUM> entry in-memory TLB <NUM> can be split into respective top and bottom in-memory TLBs <NUM>(T), <NUM>(B) that each have respective <NUM> in-memory TLB entries <NUM>(<NUM>)-<NUM>(<NUM>), <NUM>(<NUM>)-<NUM>(<NUM>). For example, level <NUM> page table entries may be cached in the top in-memory TLBs <NUM>(T), and level <NUM> page table entries may be cached in the bottom in-memory TLB <NUM>(B). On an MMU TLB miss to the MMU TLB <NUM>, the MMU circuit <NUM> would first search the in-memory TLB entries <NUM>(<NUM>)-<NUM>(<NUM>) in the top in-memory TLBs <NUM>(T) for a matching level <NUM> page table entry. If that misses, the MMU circuit <NUM> would then search the in-memory TLB entries <NUM>(<NUM>)-<NUM>(<NUM>) in the bottom in-memory TLBs <NUM>(B) for a matching level <NUM> page table entry.

It may also be needed or desired to provide a mechanism to invalidate the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM> and the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) when no longer valid so that an incorrect VA to PA translation is not performed. For example, the VA-to-PA mapping may change when an operating system kernel executing in a CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG> performs an operation that changes the VA-to-PA mapping of a VA to a PA in system memory <NUM>. For example, an operating system kernel may perform functions that change VA-to-PA mapping, such as unmap operations, remapping operations, permission changes, protection changes, and other miscellaneous changes. In essence, when an attribute of a VA-to-PA mapping changes, it may be necessary to invalidate the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM> and/or the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLBs <NUM>(<NUM>)-<NUM>(I). The in-memory TLBs <NUM>(<NUM>)-<NUM>(I) are an extension of the MMU TLB <NUM>, and as such invalidations of any MMU TLB entries <NUM>(<NUM>)-<NUM>(T) will also need to be performed on in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the MMU TLB <NUM>.

For example, the MMU circuit <NUM> in <FIG> may receive an invalidation indicator for an execution process and/or from an operating system kernel as an example to request an invalidation of TLB entries. This is an internal invalidation request as the invalidation request is being initiated from a process and/or operating system kernel with the CPU <NUM>(<NUM>)-<NUM>(N) of the MMU circuit <NUM>. In response to receiving an invalidation indicator for a process, the MMU circuit <NUM> can be configured to flush one or more in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) allocated to the process based on any VA-to-PA remapping.

As another example, take the situation of process executing on an operating system kernel in a CPU <NUM>(<NUM>)-<NUM>(N) in the processor <NUM> in <FIG>. The process has an assigned in-memory TLB <NUM>(<NUM>)-<NUM>(I) as previously discussed. A pointer to the memory address of the in-memory TLB <NUM>(<NUM>)-<NUM>(I) in system memory <NUM> is stored in the in-memory TLB register <NUM> in <FIG> as previously discussed. When a thread of the process is context switched onto a CPU <NUM>(<NUM>)-<NUM>(N), the memory address of in-memory TLB <NUM>(<NUM>)-<NUM>(I) in the system memory <NUM> is loaded into the in-memory TLB register <NUM> so that the MMU circuit <NUM> and its page table walker circuit <NUM> can access the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for performing VA-to-PA translations in the event of a TLB miss to the MMU TLB <NUM>. Assume for this example, that the operating system kernel unmaps a range of memory addresses from the memory address space addressed by the process. This means that the page table entries in the unmapped address range that are stored in the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) may now be invalid. Several scenarios may be present. For example, if these page table entries affected by the unmapping are cached in the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) for the process are leaf or non-leaf page table entries, the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM> can be flushed without flushing the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I). However, if these page table entry affected by the unmapping are cached in the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) for the process, these page tables entries in the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) are flushed to be invalidated. Invalidation could involve the process of simply writing '<NUM>'s in the page table entry in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to be invalidated. In addition, the VA tag field <NUM> in an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) could be written with <NUM>'s as a way to invalidate a page table entry in an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). If the unmapped page table entry is at a level above the level page tables of page table entries cached in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the process, this means there could be page table entries that are cached from a lower table circuit levels in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) that are covered by the affected page table entry. In this case, all these page table entries in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) are invalidated. As one option, an operating system kernel could perform the invalidation by writing to the page table entries in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) directly without the MMU circuit <NUM> performing this task. As another option, an operating system kernel could schedule a task for the MMU circuit <NUM> to perform the invalidations. The operating system kernel could invalidate an entire in-memory TLB <NUM>(<NUM>)-<NUM>(I) for a process, for example, by erasing or zeroing out the memory address in the memory address field in the process structure. The operating system kernel can then erase or zero out the memory address in the memory address field <NUM> in the in-memory TLB register <NUM> in the current CPU <NUM>(<NUM>)-<NUM>(N) running the process. The operating system kernel can issue a cross call command to zero out the in-memory TLB register on other CPUs <NUM>(<NUM>)-<NUM>(N) where threads of the same process are running. The scheduled task could also invalidate an entire in-memory TLB <NUM>(<NUM>)-<NUM>(I) for a process by erasing or zeroing out for example, the memory address in the memory address field <NUM> in the in-memory TLB register <NUM>. As for running threads, the operating system kernel could issue a cross call command to the other CPUs <NUM>(<NUM>)-<NUM>(N) to cause these other CPUs <NUM>(<NUM>)-<NUM>(N) to erase the memory address in the memory address field <NUM> in the in-memory TLB register <NUM> in each CPU <NUM>(<NUM>)-<NUM>(N) pointing to the in-memory TLB <NUM>(<NUM>)-<NUM>(I) corresponding to the process that has remapped address space. Once the operating system kernel has taken actions to ensure that the in-memory TLB <NUM>(<NUM>)-<NUM>(I) to be invalidated is not being used, the operating system kernel can schedule the invalidation in-memory TLB <NUM>(<NUM>)-<NUM>(I) by a background task if desired.

As an example, one process that can be performed by an operating system kernel to internally invalidate an in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLB <NUM>(<NUM>)-<NUM>(I) is as follows. A first step could be to invalidate a page table entry in the page table <NUM>. A next step could be to invalidate an in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) of an in-memory TLB <NUM>(<NUM>)-<NUM>(I) to be invalidated so that the invalidation is globally visible in the processor <NUM>. This prevents future walks from loading the page table entry in in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) that is invalidated from being loaded for use. The VA tag field <NUM> in the page table entry of the in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to be invalidated is read and the lock indicator <NUM> read to determine if in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is being accessed by another MMU or process. Once the lock indicator <NUM> is in an unlocked state, the lock indicator <NUM> is set to the locked state using a CAS instruction. The page table entry in the page table entry cached field <NUM> is invalidated. The VA in the VA tag field <NUM> can also be invalidated, such as by storing all <NUM>'s in the VA tag field <NUM>. The lock indicator <NUM> is then reset to an unlocked state.

It may also be necessary to perform a mechanism to externally invalidate the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM> and the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) when no longer valid so that an incorrect VA-to-PA translation is not performed. For example, a host hypervisor executing in the processor <NUM> in <FIG> may choose to trap guest memory accesses. It can do this by removing access permissions in the host page table that translates guest process PAs to host process PAs. In this situation, all of the guest page table entries in the MMU TLB entries <NUM>(<NUM>)-<NUM>(T) in the MMU TLB <NUM> and in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) caching page entries for the host page table may need to be invalidated. However, there could be a number of in-memory TLBs <NUM>(<NUM>)-<NUM>(I) within the guest processes and the guest operating system. An external invalidation mechanism can be performed by use of a generation number as previous discussed. For example, the host hypervisor could maintain a set of generation numbers, one for each guest operating system. As previously discussed, in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) has a generation number field <NUM>. Thus, when the MMU circuit <NUM> caches a page table entry in an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in an in-memory TLBs <NUM>(<NUM>)-<NUM>(I), a copy of the current guest generation number is stored in the generation number field <NUM> of the cached in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B). Thus, when the MMU circuit <NUM> matches an in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in an in-memory TLB <NUM>(<NUM>) -<NUM>(I) for a given VA <NUM> to be translated, the generation number stored in the generation number field <NUM> of the matching in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is checked to see if it is current. If not current, the page table entry in the matching in-memory TLB entry <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) is not used by the MMU circuit <NUM> effectively meaning it is invalid. When the host hypervisor desires to invalidate all in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in an in-memory TLBs <NUM>(<NUM>)-<NUM>(I) for a guest operating system, the host hypervisor can simply increment the generation number stored in the generation number field <NUM> for all the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) to be invalidated.

It may also be desired to be able to change the size of an in-memory TLBs <NUM>(<NUM>)-<NUM>(I) dynamically to improve performance of VA-to-PA translation for a particular process. For example, it may be desired to provide a mechanism to allow an operating system kernel to dynamically change the size of an in-memory TLBs <NUM>(<NUM>)-<NUM>(I) for a process if the memory access requests for the process do not achieve the desired access time performance. However, the same in-memory TLBs <NUM>(<NUM>)-<NUM>(I) may be accessed by multiple threads of the same process at the same time. Thus, as an example, the operating system kernel may be configured to resize an in-memory TLB <NUM>(<NUM>)-<NUM>(I) by first invalidating (e.g., zeroing out) the memory address in the memory address field <NUM> in the process and on the current CPU <NUM>(<NUM>)-<NUM>(N) for an in-memory TLBs <NUM>(<NUM>)-<NUM>(I) to be resized. For running threads, the operating system kernel can be configured to send a cross call command to the other CPUs <NUM>(<NUM>)-<NUM>(N) that would cause the other CPUs <NUM>(<NUM>)-<NUM>(N) to invalidate the memory address field <NUM> in an in-memory TLB register <NUM> in a process for the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) so that the MMU circuit <NUM> in the CPUs <NUM>(<NUM>)-<NUM>(N) are effectively prevented from using the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) to be resized for VA-to-PA translations. Now that the operating system kernel can be sure that the in-memory TLB <NUM>(<NUM>)-<NUM>(I) for a process to be resized will not be used by a thread of that process, the operating system kernel can allocate a new in-memory TLB <NUM>(<NUM>)-<NUM>(I) for the process in the system memory <NUM> and initiate the in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) and setup the in-memory TLB register <NUM> corresponding to the resized in-memory TLB <NUM>(<NUM>)-<NUM>(I) to allow the resized in-memory TLB <NUM>(<NUM>)-<NUM>(I) to be used by MMU circuit <NUM> for VA-to-PA translations. A malicious guest may also be able to forge in-memory TLB entries <NUM>(<NUM>)(<NUM>)-<NUM>(I)(B) in an in-memory TLBs <NUM>(<NUM>)-<NUM>(I). Under special circumstances when a host hypervisor needs the guest process to walk a full page table, the host hypervisor could disable the use of in-memory TLBs <NUM>(<NUM>)-<NUM>(I) corresponding to the guest process. During later normal operation, the in-memory TLBs <NUM>(<NUM>)-<NUM>(I) can be re-enabled. If the forgery is done under normal operation of the guest host, it can only affect the guest process and not other guest processes or the host process.

<FIG> is a block diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> that can include a memory management system <NUM> with dedicated mTLBs <NUM> for augmenting an MMU TLB for translating VAs to PA, including but not limited to the memory management system <NUM> in <FIG> and its exemplary components in <FIG>, and <FIG>. The processor-based system <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server, or a user's computer. In this example, the processor-based system <NUM> includes the processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from execution of producer instructions. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions accessible by the memory management system <NUM>. Fetched or prefetched instructions from a memory, such as from a system memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The memory management system <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution.

The processor <NUM> and the system memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based system <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the system memory <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the system memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The system memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the system memory <NUM>, an external cache memory <NUM> as part of a cache memory system <NUM> that may include lower-level cache memories all of which are accessible by the processor <NUM>, one or more input device(s) <NUM>, one or more output device(s) <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based system <NUM> in <FIG> may include a set of instructions <NUM> to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the system memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of a non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the system memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes the computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that stores the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that causes the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is in no way intended that any particular order be inferred.

Claim 1:
A memory management system (<NUM>) for a central processing unit, CPU, (<NUM>) for a processor (<NUM>) of a processor-based system (<NUM>), comprising:
a page table (<NUM>) in a system memory (<NUM>) of the processor-based system (<NUM>), the page table (<NUM>, <NUM>, <NUM>) comprising a plurality of level page tables (<NUM>, <NUM>, <NUM>) each comprising a plurality of page table entries (<NUM>, <NUM>, <NUM>) each addressable by a virtual address, VA, and configured to store a physical address, PA, associated with the VA;
a memory management unit, MMU, translation lookaside buffer, TLB, (<NUM>) comprising a plurality of MMU TLB entries (<NUM>) each configured to store a cached page table entry (<NUM>, <NUM>, <NUM>) in the page table;
an in-memory TLB (<NUM>) in the system memory (<NUM>) wherein the in-memory TLB (<NUM>) is associated with the MMU TLB, the in-memory TLB (<NUM>) comprising a plurality of in-memory TLB entries (<NUM>) each configured to store a cached page table entry (<NUM>, <NUM>, <NUM>) in the page table and wherein the in-memory TLB (<NUM>) is configured to cache page table entries from a higher level page table than the page tables entries cached in the MMU TLB;
a page table walker circuit (<NUM>) configured to access the plurality of page table entries (<NUM>, <NUM>, <NUM>) in at least one level page table (<NUM>, <NUM>, <NUM>) in the page table (<NUM>, <NUM>, <NUM>) based on the VA; and
an MMU circuit (<NUM>) configured to:
receive a memory access request comprising a VA based on a computer software instruction executed for a process in the CPU (<NUM>);
determine if an MMU TLB entry (<NUM>) in the MMU TLB (<NUM>) contains a page table entry comprising a PA corresponding to the VA; and
in response to determining the MMU TLB (<NUM>) does not contain an MMU TLB entry (<NUM>) containing a page table entry directly corresponding to the VA:
determine if a VA stored in an in-memory TLB entry (<NUM>) corresponding to the VA in an in-memory TLB (<NUM>) allocated to the process in the system memory (<NUM>) in the processor-based system (<NUM>) matches the VA of the memory access request; and
in response to determining the VA stored in the in-memory TLB entry (<NUM>) matches the VA of the memory access request, translate the VA to a PA based the accessed page table entry in the in-memory TLB entry (<NUM>) corresponding to the VA.