Patent Description:
Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.

Programmable logic devices are a class of integrated circuits that can be programmed to perform a wide variety of operations. A programmable logic device may include programmable logic elements programmed by a form of memory known as configuration random access memory (CRAM). Thus, to program a circuit design into a programmable logic device, the circuit design may be compiled into a bitstream and programmed into CRAM cells. The values programmed into the CRAM cells define the operation of programmable logic elements of the programmable logic device.

The highly flexible nature of programmable logic devices makes them an excellent fit for accelerating many computing tasks. Thus, programmable logic devices are increasingly used as accelerators for machine learning, video processing, voice recognition, image recognition, and many other highly specialized tasks, particularly those that would be too slow or inefficient in software running on a processor. The circuit designs that define accelerator functions may benefit from access to a large amount of data stored in memory. Accessing an external memory device may be a relatively slow process, however, and so some programmable logic devices may include in-fabric memory in the form of arrays of local memory accessible to the programmable logic fabric.

The capacity of the in-fabric memory is space-limited, however, since the in-fabric memory may take up die space that would otherwise contain configuration memory for programmable logic elements. Increasing the amount of in-fabric memory may thus reduce the number of available programmable logic elements. As a consequence, accelerator designers may face a dilemma between faster operating times with lower-capacity in-fabric memory and slower operating times with higher-capacity external memory.

<CIT> discloses techniques for aligning and reducing skew in serial data signals. A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

<CIT> discloses a system, a method, and a computer program product for improving memory systems. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

<CIT> discloses a method and an apparatus for communicating data between vertically stacked integrated circuits. In some examples of this document, a method of configuring an integrated circuit which is a first die includes obtaining configuration data at configuration resources of the integrated circuit from a non-volatile memory on a second die through an integration tile of the integrated circuit, the second die being vertically stacked on the first die; storing the configuration data in at least one register as the configuration data is obtained by the configuration resources; and loading the configuration data from the at least one register to a configuration memory of the integrated circuit to configure programmable resources of the integrated circuit.

<CIT> relates to a configuration interface to stacked field-programmable gate array, FPGA. A semiconductor device includes a FPGA die having a frame address bus, a frame data bus, and a second integrated circuit, IC, die attached to the FPGA die. An inter-chip frame address bus couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts formed between the FPGA die and the second IC die.

The object of the present application is solved by the independent claims. Advantageous embodiments are described by the dependent claims.

It may be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it may be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" arc intended to mean that there arc one or more of the elements. Furthermore, the phrase A "based on" B is intended to mean that A is at least partially based on B. Moreover, unless expressly stated otherwise, the term "or" is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A "or" B is intended to mean A, B, or both A and B.

The highly flexible nature of programmable logic devices makes them an excellent fit for accelerating many computing tasks. Thus, programmable logic devices are increasingly used as accelerators for machine learning, video processing, voice recognition, image recognition, and many other highly specialized tasks, particularly those that would be too slow or inefficient in software running on a processor. The circuit designs that define an accelerator function may benefit from access to a large amount of data stored in memory. Since accessing an external memory device may be a relatively slow process, and the capacity of in-fabric memory may be limited, this disclosure describes a local memory that is neither directly within the programmable fabric nor external to the programmable logic device. In this disclosure, the memory is referred to as "sector-aligned memory," since the memory may have certain areas that are accessible to different respective areas of the programmable logic fabric.

In some cases, the programmable logic device may be composed of at least two separate die. The programmable logic device may include a first die that contains primarily programmable logic fabric, and a second die that contains fabric support circuitry to support the operation of the programmable logic fabric. For example, the second die may contain at least some fabric support circuitry that may operate the programmable logic fabric (e.g., the fabric support circuitry of the second die may be essential to the operation of the programmable logic fabric of the first die). Thus, the fabric support circuitry may include, among other things, a device controller (sometimes referred to as a secure device manager (SDM)), a sector controller (sometimes referred to as a local sector manager (LSM)), a network-on-chip (NOC), a configuration network on chip (CNOC), data routing circuitry, local (e.g., sectorized or sector-aligned) memory used to store and/or cache configuration programs (bitstreams) or data, memory controllers used to program the programmable logic fabric, input/output (I/O) interfaces or modules for the programmable logic fabric, external memory interfaces (e.g., for a high bandwidth memory (HBM) device), an embedded processor (e.g., an embedded Intel® Xeon® processor by Intel Corporation of Santa Clara, California) or an interface to connect to a processor (e.g., an interface to an Intel® Xeon® processor by Intel Corporation of Santa Clara, California), voltage control circuitry, thermal monitoring circuitry, decoupling capacitors, power clamps, or electrostatic discharge circuitry, to name just a few circuit elements that may be present on the second die. Indeed, in some embodiments, the first die may entirely or almost entirely contain programmable logic fabric, and the second die may contain all or almost all of the fabric support circuitry that controls the programmable logic fabric.

The fabric support circuitry may include the sector-aligned memory accessible to the programmable logic fabric. Since the sector-aligned memory may be located on a separate die from the programmable logic fabric, the sector-aligned memory may have a much larger capacity than a capacity of local in-fabric memory. Indeed, in some cases, the sector-aligned memory may have a capacity of one-thousand times or greater than the capacity of local in-fabric memory.

The sector-aligned memory may not only have a higher capacity than local in-fabric memory, but the sector-aligned memory may also have a higher bandwidth than an external memory device. The high bandwidth may be made possible by physically locating the sector-aligned memory near to the programmable logic fabric (e.g., in a base die vertically aligned with the fabric die) and/or by physically or logically dividing the sector-aligned memory into separate sectors that may transfer data in parallel to corresponding different sectors of the programmable logic fabric. This may also allow the sector-aligned memory to be secured from access by other sectors of the programmable logic fabric. Furthermore, depending on the physical arrangement of the first die that contains the programmable logic fabric and the second die that contains the fabric support circuitry (e.g., the sector-aligned memory), the sector-aligned memory may be pipelined into the programmable logic fabric, allowing for even faster data utilization.

With this in mind, <FIG> illustrates a block diagram of a system <NUM> that may employ a programmable logic device <NUM> that can rapidly access large amounts of local sector-aligned memory. Using the system <NUM>, a designer may implement a circuit design functionality on an integrated circuit, such as a reconfigurable programmable logic device <NUM>, such as a field programmable gate array (FPGA). The designer may implement a circuit design to be programmed onto the programmable logic device <NUM> using design software <NUM>, such as a version of Intel® Quartus® by Intel Corporation of Santa Clara, California. The design software <NUM> may use a compiler <NUM> to generate a low-level circuit-design defined by bitstream <NUM>, sometimes known as a program object file and/or configuration program, that programs the programmable logic device <NUM>. Thus, the compiler <NUM> may provide machine-readable instructions representative of the circuit design to the programmable logic device <NUM>. For example, the programmable logic device <NUM> may receive one or more configuration programs (bitstreams) <NUM> that describe the hardware implementations that should be stored in the programmable logic device <NUM>. A configuration program (e.g., bitstream) <NUM> may be programmed into the programmable logic device <NUM> as a configuration program <NUM>. The configuration program <NUM> may, in some cases, represent an accelerator function to perform for machine learning, video processing, voice recognition, image recognition, or other highly specialized task.

To carry out the systems and methods of this disclosure, the programmable logic device <NUM> may take any suitable form that includes a local memory having sufficient capacity and bandwidth to rapidly reprogram the programmable logic fabric (e.g., to rapidly reprogram the configurable random-access memory of the programmable logic fabric with a different configuration program (e.g., bitstream)). In some cases, the areas of the programmable logic fabric may be programmed in parallel by sector, from local memory associated with that sector, which is referred to in this disclosure as "sector-aligned memory. " Sector-aligned memory may be incorporated into the programmable logic device on an integrated circuit die that is separate from, but nearby, the integrated circuit die that holds the sector programmable logic fabric, as will be described further below. The sector-aligned memory may also be incorporated into an integrated circuit die containing the programmable logic fabric if the sector-aligned memory has the capacity to store all or part of configuration data (bitstream) for programming that sector of programmable logic fabric.

Thus, the programmable logic device <NUM> may have two separate integrated circuit die where at least some of the programmable logic fabric is separated from at least some of the fabric support circuitry that operates the programmable logic fabric, which may include local memory, such as sector-aligned memory. One example of the programmable logic device <NUM> is shown in <FIG>, but any suitable programmable logic device having local memory of sufficient bandwidth and capacity may be used. In the example of <FIG>, the programmable logic device <NUM> includes a fabric die <NUM> and a base die <NUM> that are connected to one another via microbumps <NUM>. Although the fabric die <NUM> and base die <NUM> appear in a one-to-one relationship in <FIG>, other relationships may be used. For example, a single base die <NUM> may attach to several fabric die <NUM>, or several base die <NUM> may attach to a single fabric die <NUM>, or several base die <NUM> may attach to several fabric die <NUM> (e.g., in an interleaved pattern along the x- and/or y- direction). Peripheral circuitry <NUM> may be attached to, embedded within, and/or disposed on top of the base die <NUM>, and heat spreaders <NUM> may be used to reduce an accumulation of heat on the programmable logic device <NUM>. The heat spreaders <NUM> may appear above, as pictured, and/or below the package (e.g., as a double-sided heat sink). The base die <NUM> may attach to a package substrate <NUM> via C4 bumps <NUM>. In the example of <FIG>, two pairs of fabric die <NUM> and base die <NUM> are shown communicatively connected to one another via a silicon bridge <NUM> (e.g., an embedded multi-die interconnect bridge (EMIB)) and microbumps <NUM> at a silicon bridge interface <NUM>.

In combination, the fabric die <NUM> and base die <NUM> may operate as a programmable logic device such as a field programmable gate array (FPGA). For example, the fabric die <NUM> and the base die <NUM> may operate in combination as an FPGA <NUM>, shown in <FIG>. It should be understood that the FPGA <NUM> shown in <FIG> is meant to represent the type of circuitry and/or a logical arrangement of a programmable logic device when the both the fabric die <NUM> and the base die <NUM> operate in combination. In other words, some of the circuitry of the FPGA <NUM> shown in <FIG> may be found in the fabric die <NUM> and some of the circuitry of the FPGA <NUM> shown in <FIG> may be found in the base die <NUM>. Moreover, for the purposes of this example, the FPGA <NUM> is referred to as an FPGA, though it should be understood that the device may be any suitable type of programmable logic device (e.g., an application-specific integrated circuit and/or application-specific standard product).

In the example of <FIG>, the FPGA <NUM> may include transceiver circuitry (HSSI) <NUM> for driving signals off of the FPGA <NUM> and for receiving signals from other devices. The transceiver circuitry (HSSI) may be part of the fabric die <NUM>, the base die <NUM>, or a separate die altogether. Interconnection resources <NUM> may be used to route signals, such as clock or data signals, through the FPGA <NUM>. The FPGA <NUM> of <FIG> is shown to be sectorized, meaning that programmable logic resources may be distributed through a number of discrete programmable logic sectors <NUM>. Each programmable logic sector <NUM> may include a number of programmable logic elements <NUM> having operations defined by configuration memory <NUM> (e.g., configuration random access memory (CRAM)). The programmable logic elements <NUM> may include combinational or sequential logic circuitry. For example, the programmable logic elements <NUM> may include look-up tables, registers, multiplexers, routing wires, and so forth. A designer may program the programmable logic elements <NUM> to perform a variety of desired functions. A power supply <NUM> may provide a source of voltage and current to a power distribution network (PDN) <NUM> that distributes electrical power to the various components of the FPGA <NUM>. Operating the circuitry of the FPGA <NUM> causes power to be drawn from the power distribution network <NUM>.

There may be any suitable number of programmable logic sectors <NUM> on the FPGA <NUM>. Indeed, while <NUM> programmable logic sectors <NUM> are shown here, it should be appreciated that more or fewer may appear in an actual implementation (e.g., in some cases, on the order of <NUM>, <NUM>, or <NUM> sectors or more). Each programmable logic sector <NUM> may include a sector controller (SC) <NUM> that controls the operation of the programmable logic sector <NUM>. Each sector controller <NUM> may be in communication with a device controller (DC) <NUM>. Each sector controller <NUM> may accept commands and data from the device controller <NUM>, and may read data from and write data into its configuration memory <NUM> based on control signals from the device controller <NUM>. In addition to these operations, the sector controller <NUM> and/or device controller <NUM> may be augmented with numerous additional capabilities. Such capabilities may include coordinating memory transactions between local in-fabric memory (e.g., local fabric memory or CRAM being used for data storage) and sector-aligned memory associated with that particular programmable logic sector <NUM>, decrypting configuration data (bitstreams) <NUM>, and locally sequencing reads and writes to implement error detection and correction on the configuration memory <NUM> and sequencing test control signals to effect various test modes.

The sector controllers <NUM> and the device controller <NUM> may be implemented as state machines and/or processors. For example, each operation of the sector controllers <NUM> or the device controller <NUM> may be implemented as a separate routine in a memory containing a control program. This control program memory may be fixed in a read-only memory (ROM) or stored in a writable memory, such as random-access memory (RAM). The ROM may have a size larger than would be used to store only one copy of each routine. This may allow each routine to have multiple variants depending on "modes" the local controller may be placed into. When the control program memory is implemented as random access memory (RAM), the RAM may be written with new routines to implement new operations and functionality into the programmable logic sectors <NUM>. This may provide usable extensibility in an efficient and easily understood way. This may be useful because new commands could bring about large amounts of local activity within the sector at the expense of only a small amount of communication between the device controller <NUM> and the sector controllers <NUM>.

Each sector controller <NUM> thus may communicate with the device controller <NUM>, which may coordinate the operations of the sector controllers <NUM> and convey commands initiated from outside the FPGA device <NUM>. To support this communication, the interconnection resources <NUM> may act as a network between the device controller <NUM> and each sector controller <NUM>. The interconnection resources may support a wide variety of signals between the device controller <NUM> and each sector controller <NUM>. In one example, these signals may be transmitted as communication packets.

The FPGA <NUM> may be electrically programmed. With electrical programming arrangements, the programmable elements <NUM> may include one or more logic elements (wires, gates, registers, etc.). For example, during programming, configuration data is loaded into the configuration memory <NUM> using pins <NUM> and input/output circuitry <NUM>. In one example, the configuration memory <NUM> may be implemented as configuration random-access-memory (CRAM) cells. The use of configuration memory <NUM> based on RAM technology is described herein is intended to be only one example. Moreover, configuration memory <NUM> may be distributed (e.g., as RAM cells) throughout the various programmable logic sectors <NUM> the FPGA <NUM>. The configuration memory <NUM> may provide a corresponding static control output signal that controls the state of an associated programmable logic element <NUM> or programmable component of the interconnection resources <NUM>. The output signals of the configuration memory <NUM> may configure the may be applied to the gates of metal-oxide-semiconductor (MOS) transistors that control the states of the programmable logic elements <NUM> or programmable components of the interconnection resources <NUM>.

As stated above, the logical arrangement of the FPGA <NUM> shown in <FIG> may result from a combination of the fabric die <NUM> and base die <NUM>. The circuitry of the fabric die <NUM> and base die <NUM> may be divided in any suitable manner. In one example, shown in block diagram form in <FIG>, the fabric die <NUM> contains primarily programmable logic fabric resources, such as the programmable logic elements <NUM> and configuration memory <NUM>. In some cases, this may also entail certain fabric control circuitry such as the sector controller (SC) <NUM> or device controller (DC) <NUM>. The base die <NUM> may include supporting circuitry to operate the programmable logic elements <NUM> and configuration memory <NUM>. Shown here, the base die <NUM> includes sector <NUM> support circuitry 70A and sector <NUM> support circuitry 70B to support two corresponding sectors of the programmable logic elements <NUM> and configuration memory <NUM> of the fabric die <NUM>. The base die <NUM> may also include support circuitry for other sectors of the fabric die <NUM>.

Thus, while the fabric die <NUM> may include primarily programmable logic fabric resources, such as the programmable logic elements <NUM> and configuration memory <NUM>, the base die <NUM> may include, among other things, a device controller (DC) <NUM>, a sector controller (SC) <NUM>, a network-on-chip (NOC), a configuration network on chip (CNOC), data routing circuitry, sector-aligned memory used to store and/or cache configuration programs (bitstreams) or data, memory controllers used to program the programmable logic fabric, input/output (I/O) interfaces or modules for the programmable logic fabric, external memory interfaces (e.g., for a high bandwidth memory (HBM) device), an embedded processor (e.g., an embedded Intel® Xeon® processor by Intel Corporation of Santa Clara, California) or an interface to connect to a processor (e.g., an interface to an Intel® Xeon® processor by Intel Corporation of Santa Clara, California), voltage control circuitry, thermal monitoring circuitry, decoupling capacitors, power clamps, and/or electrostatic discharge (ESD) circuitry, to name just a few elements that may be present on the base die <NUM>. It should be understood that some of these elements that may be part of the fabric support circuitry of the base die <NUM> may additionally or alternatively be a part of the fabric die <NUM>. For example, the device controller (DC) <NUM> and/or the sector controllers (SC) <NUM> may be part of the fabric die <NUM>.

While <FIG> represents an example where the fabric die <NUM> contains primarily programmable logic fabric, with most other components located in the base die <NUM>, the fabric die <NUM> may contain some of the other components to support the programmable logic fabric. Thus, in some embodiments, the fabric die <NUM> may include one or more of a device controller (DC) <NUM>, a sector controller (SC) <NUM>, a network-on-chip (NOC), a configuration network on chip (CNOC), data routing circuitry, sector-aligned memory used to store and/or cache configuration programs (bitstreams) or data, memory controllers used to program the programmable logic fabric, input/output (I/O) interfaces or modules for the programmable logic fabric, external memory interfaces (e.g., for a high bandwidth memory (HBM) device), an embedded processor (e.g., an embedded Intel® Xeon® processor by Intel Corporation of Santa Clara, California) or an interface to connect to a processor (e.g., an interface to an Intel® Xeon® processor by Intel Corporation of Santa Clara, California), voltage control circuitry, thermal monitoring circuitry, decoupling capacitors, power clamps, and/or electrostatic discharge (ESD) circuitry, and other elements may be disposed on the base die <NUM>.

One example physical arrangement of the fabric die <NUM> and the base die <NUM> is shown by <FIG> and <FIG>. In <FIG>, the fabric die <NUM> is shown to contain an array of fabric sectors <NUM> that include fabric resources <NUM> (e.g., programmable elements programmed by CRAM and/or certain fabric control circuitry such as the sector controller (SC) <NUM> or device controller (DC) <NUM>) and interface circuitry <NUM>. The interface circuitry <NUM> may include data routing and/or clocking resources, or may include an interface to data routing and/or clocking resources on the base die <NUM>. Thus, the interface circuitry <NUM> may connect with a micro-bump (ubump) interface to connect to the base die <NUM>.

<FIG> provides a complementary arrangement of the base die <NUM>. The base die <NUM> may represent an active interposer with several sectors <NUM> surrounded by peripheral circuitry <NUM> and the silicon bridge interface <NUM>. Each sector <NUM> may include a variety of fabric support circuitry, such as sector-aligned memory <NUM>, memory control circuitry <NUM>, non-user input control circuitry <NUM>, non-user output control circuitry <NUM>, a voltage regulator such as a fully integrated voltage regulator (FIVR) <NUM>, one or more thermal sensors <NUM>, data and configuration routers <NUM>, and/or data or configuration pathways <NUM>. The memory control circuitry <NUM> may be used to program the sector-aligned memory <NUM>, the CRAM of the fabric die <NUM>, or both. The non-user input control circuitry <NUM> and non-user output control circuitry <NUM> may allow the circuitry of the sectors <NUM> to exchange data and/or control signals (e.g., via configurable data routing network -on-chip (NOC) or a configuration network on chip (CNOC)). In one example, the non-user input control circuitry <NUM> and non-user output control circuitry <NUM> may operate as the sector controller (SC) <NUM> for a corresponding fabric sector <NUM> (as shown in <FIG>). The FIVR <NUM> and the one or more thermal sensors <NUM> may be used to provide a desired voltage to the corresponding fabric sector <NUM> (as shown in <FIG>), enabling the voltage to be selectively scaled up or down, or removed, depending on power and thermal specifications (e.g., based at least in part on temperature as measured by a thermal sensor <NUM> and/or in accordance with a dynamic voltage and frequency scaling (DVFS) scheme). Even though the thermal sensors <NUM> are in a separate die from that of the programmable logic fabric elements, when the base die <NUM> is directly adjacent to the fabric die <NUM> as in this example, the temperature measured by the thermal sensor <NUM> in the base die <NUM> may correspond well enough to the fabric die <NUM> to allow for temperature-based operations (e.g., turn off power to the corresponding fabric sector <NUM> to prevent a permanent-denial-of-service (PDOS) condition).

By vertically aligning the fabric die <NUM> and the base die <NUM>, memory located in the base die <NUM> may be accessible in parallel to fabric sectors <NUM> of the fabric die <NUM>. <FIG> shows an example in which sector-aligned memory <NUM> may be contained in the base die <NUM>. The sector-aligned memory <NUM> may be directly accessible to respective fabric sectors <NUM> of the fabric die <NUM>, and may contain user data (generated by or accessible by a circuit design programmed into the programmable logic fabric of the base die <NUM>) or configuration data that may be used to program the programmable logic fabric of the base die <NUM>. In this disclosure, "directly accessible" refers to a connection between a region of the sector-aligned memory <NUM> that is associated with a particular fabric sector <NUM> and that particular fabric sector <NUM>. In some embodiments, each respective region of the sector-aligned memory <NUM> associated with a particular fabric sector <NUM> may be directly accessible to that particular fabric sector <NUM>, thereby providing each fabric sector <NUM> with direct access to that region of the sector-aligned memory <NUM>. For example, there may be N regions of sector-aligned memory <NUM> that can be accessible by N corresponding fabric sectors <NUM> at the same time (e.g., in parallel). In some cases, the sector-aligned memory <NUM> may be accessible to more than one fabric sector <NUM> or multiple sectors of sector-aligned memory <NUM> may be accessible to a single fabric sector <NUM>. Thus, in some cases, the same region of sector-aligned memory <NUM> may be directly accessible to multiple fabric sectors <NUM>, while in other cases, a region of sector-aligned memory <NUM> may be directly accessible only to a single fabric sector <NUM>. In the example of <FIG>, the fabric sectors <NUM> may access specific regions of sector-aligned memory <NUM>. The sector-aligned memory <NUM> is shown in <FIG> as vertically stacked memory. This may allow a large amount of memory to be located within the base die <NUM>. However, the sector-aligned memory <NUM> may occupy a single plane of the base die <NUM> in some embodiments.

As shown in <FIG>, the sector-aligned memory <NUM> of the base die <NUM> may be accessible by the programmable logic fabric (e.g., programmable logic elements <NUM> and associated configuration memory <NUM>) of the fabric die <NUM> via a memory interface (I/F) <NUM>. There may be one or more memory interfaces (I/F) <NUM> for each fabric sector, allowing different fabric sectors to access their respective sectors of the sector-aligned memory <NUM> in parallel. The memory interface (I/F) <NUM> may occupy a row of a fabric sector <NUM> and may be made of hardened logic or soft logic, or both. In the example of <FIG>, the memory interface (I/F) <NUM> may occupy an outermost row of a fabric sector <NUM>. This may allow the memory interface (I/F) <NUM> to facilitate communication not just with rows of programmable logic elements <NUM> and associated configuration memory <NUM> in the fabric sector <NUM> where the memory interface (I/F) <NUM> is located, but also with rows of programmable logic elements <NUM> and associated configuration memory <NUM> in an adjacent fabric sector <NUM>.

The memory interface (I/F) <NUM> may receive or transmit data via a data path <NUM> to a memory data interface (I/F) <NUM> and may communicate control signals via a control signal path <NUM> to and from a memory control interface (I/F) <NUM>. The memory interface (I/F) <NUM> may receive control and/or data signals and route them through the rows of programmable logic elements <NUM> and associated configuration memory <NUM> to a particular memory address or logic element via routing circuitry <NUM>. The control signal path <NUM> and the data path <NUM> may represent a first physical connection between a first sector of programmable logic fabric and a first sector of the sector-aligned memory <NUM>. It should be understood that similar pathways may represent a second physical connection between a second sector of programmable logic fabric and a second sector of the sector-aligned memory <NUM>.

Regardless of its exact placement, the sector-aligned memory <NUM> may be located near enough to a particular area of the programmable logic fabric of the programmable logic device <NUM> to be able to provide very rapid data transfers. This may enable the sector-aligned memory <NUM> to be used for caching of data and/or configuration programs that may be programmed into the programmable logic fabric. One example of circuitry that may use the sector-aligned memory <NUM> appears in <FIG>. The various components shown in <FIG> may be located in a single die or may be distributed through several die (e.g., distributed through the fabric die <NUM> or the base die <NUM>). Indeed, when programmable logic device <NUM> includes the fabric die <NUM> and the base die <NUM>, each element of circuitry represented by the block diagram of <FIG> may be found in at least one of the fabric die <NUM> and the base die <NUM>, as desired. In many situations, however, the sector-aligned memory <NUM> may have a sufficiently high capacity that it may not fit in the fabric die <NUM>, and thus may be located in the base die <NUM>.

The circuitry shown in <FIG> includes the device controller (DC) <NUM> that may receive, among other things, a bitstream <NUM>. The bitstream <NUM> may represent data that may be received by the device controller (DC) <NUM>, such as configuration data that may program the configuration memory (CRAM) <NUM> of a particular sector of programmable logic elements (FPGA fabric) <NUM> and/or data that may be processed by the programmable logic fabric (e.g., in a request to accelerate a compute task). The device controller <NUM> may receive the bitstream <NUM> from an external data source, such as an external data storage device or external memory device, and may direct the bitstream <NUM> to the sector controller (SC) <NUM> of the particular sector via a configuration network on chip (CNOC) <NUM> or any other suitable pathway.

When the circuitry of <FIG> is used for configuring the programmable logic device elements <NUM> by programming the configuration memory (CRAM) <NUM>, routing circuitry <NUM> (e.g., a multiplexer) may provide the bitstream <NUM> to the sector controller (SC) <NUM> via a main signal path <NUM>. When directed by the bitstream <NUM>, when determined by a routine running on the sector controller (SC) <NUM>, and/or when directed by the circuit design programmed into the programmable logic elements <NUM>, the sector controller (SC) <NUM> may issue a selection signal over a selection pathway <NUM> to direct the routing circuitry <NUM> to receive the bitstream <NUM> from the CNOC <NUM> or to receive data from the sector-aligned memory <NUM>, and/or whether to cache the bitstream <NUM> into the sector-aligned memory <NUM>. Based on the selection signal on the selection pathway <NUM>, the routing circuitry <NUM> may provide either data on the CNOC <NUM> or on a data pathway <NUM> from the sector-aligned memory <NUM> to the sector controller (SC) <NUM>. A control pathway <NUM> may enable control communication between the sector controller (SC) <NUM> and the sector-aligned memory <NUM>. The sector controller (SC) <NUM> may use the control pathway <NUM> to cause the sector-aligned memory <NUM> to retrieve data from or store data into the sector-aligned memory <NUM>.

A configuration program <NUM> implemented in the programmable logic fabric, as defined by the configuration of programmable logic elements <NUM> programmed by the configuration memory (CRAM) <NUM>, may utilize the sector-aligned memory <NUM>. The configuration program <NUM> programmed into the programmable logic elements <NUM> may do so in several ways. In one example, the configuration program <NUM> may directly access (e.g., read from or write to) the sector-aligned memory via the control pathway <NUM> coupled to the control interface (CTRL I/F) <NUM> and the data pathway <NUM> coupled to the data interface (DATA I/F) <NUM> for direct data transfers between the programmable logic fabric and the sector-aligned memory <NUM>. The configuration program <NUM> may include a memory controller for the sector-aligned memory <NUM> implemented in the programmable logic elements <NUM>, which may be referred to as a memory controller implemented in soft logic, or a hardened memory controller may be accessible to the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>. In another example, the configuration program <NUM> may communicate control signals to the sector controller (SC) <NUM> via the control pathway <NUM> instructing the sector controller (SC) <NUM> to coordinate a data transfer to or from the sector-aligned memory <NUM>. The configuration program <NUM> thus may include a soft processor or soft state machine to communicate with the sector controller (SC) <NUM> in this way, or hardened control circuitry may be disposed among the programmable logic elements <NUM> to communicate with the sector controller (SC) <NUM>.

A memory address register / data register (AR/DR) <NUM> may program the configuration memory (CRAM) <NUM> and/or in-fabric memory <NUM> based on instructions from the sector controller (SC) <NUM> on a control pathway <NUM> and using data received on a data pathway <NUM>. In this way, the AR/DR <NUM> may rapidly program the CRAM <NUM> and/or in-fabric memory <NUM> with data, such as data from the bitstream <NUM> received on the CNOC <NUM> or directly from sector-aligned memory <NUM> when so instructed. This may take place much more quickly than the time involved in receiving the entire bitstream <NUM> via the CNOC <NUM>, which may face latencies due to accessing a memory device external to the programmable logic device <NUM>. In some cases, this may be <NUM>% faster, twice as fast, 5x as fast, 10x as fast, 20x as fast, 50x as fast, 100x as fast, 200x as fast, 500x as fast, 1000x as fast, or faster, to program the CRAM <NUM> and/or in-fabric memory <NUM> with data directly from the sector-aligned memory <NUM> than to program the CRAM <NUM> and/or in-fabric memory <NUM> with the bitstream <NUM> from the CNOC <NUM>. Here, it may also be noted that the amount of memory available in the in-fabric memory <NUM> may be much smaller than the amount of memory available in the sector-aligned memory <NUM>. In fact, the sector-aligned memory <NUM> may have a capacity many times that of the in-fabric memory <NUM> (e.g., 10x, 100x, 1000x, or more).

For even faster programming, the programming of the CRAM <NUM> and/or in-fabric memory <NUM> may be pipelined, as shown in <FIG>. A memory manager <NUM> may coordinate control of the AR/DR <NUM> via control pathways <NUM> and <NUM>. The memory manager <NUM> may be located in the fabric die <NUM> and/or in the base die <NUM>. The memory manager <NUM> may be implemented as a state machine and/or as a processor running software or firmware, and may control the data transfers to and/or from the sector-aligned memory <NUM> and the AR/DR <NUM> over a data pathway <NUM>. The data pathway <NUM> may communicate data more rapidly than may be provided over the CNOC <NUM>. The data pathway <NUM> may have a faster frequency and/or may carry data more widely, in parallel, than the CNOC <NUM>.

The sector controller (SC) <NUM> may coordinate with the AR/DR <NUM> and the memory manager <NUM> to receive the bitstream <NUM> via a data pathway <NUM> from the CNOC <NUM> or from the sector-aligned memory <NUM>. As mentioned above, the sector controller (SC) <NUM> may control whether to receive data of the bitstream <NUM> from the CNOC <NUM> or to get it from the sector-aligned memory <NUM>, and/or whether to cache or pre-cache (e.g., in a cache prefetch) the bitstream <NUM> into the sector-aligned memory <NUM>.

As with the circuitry of <FIG>, in the circuitry of <FIG>, a configuration program <NUM> implemented in the programmable logic fabric, as defined by the configuration of programmable logic elements <NUM> programmed by the configuration memory (CRAM) <NUM>, may utilize the sector-aligned memory <NUM>. The configuration program <NUM> programmed into the programmable logic elements <NUM> may do so in several ways. In one example, the configuration program <NUM> may directly access (e.g., read from or write to) the sector-aligned memory via the control pathway <NUM> coupled to the control interface (CTRL I/F) <NUM> and the data pathway <NUM> coupled to the data interface (DATA I/F) <NUM> for direct data transfers between the programmable logic fabric and the sector-aligned memory <NUM>. The configuration program <NUM> may include a memory controller for the sector-aligned memory <NUM> implemented in the programmable logic elements <NUM>, which may be referred to as a memory controller implemented in soft logic, or a hardened memory controller may be accessible to the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>. In another example, the configuration program <NUM> may communicate control signals to the sector controller (SC) <NUM> and/or the memory manager <NUM> via the control pathway <NUM>. The configuration program <NUM> may instruct the sector controller (SC) <NUM> and/or the memory manager <NUM> to coordinate a data transfer to or from the sector-aligned memory <NUM>. The configuration program <NUM> thus may include a soft processor or soft state machine to communicate with the sector controller (SC) <NUM> in this way, or hardened control circuitry may be disposed among the programmable logic elements <NUM> to communicate with the sector controller (SC) <NUM> and/or the memory manager <NUM>.

Data from the CNOC <NUM> or the sector-aligned memory <NUM> may be loaded into the AR/DR <NUM> and pipelined into the CRAM <NUM> and/or in-fabric memory <NUM> via pipelining circuitry <NUM>. The pipelining circuitry <NUM> may allow multiple cells of the configuration memory (CRAM) <NUM> to be programmed at once by pipelining multiple bits of data into registers of the AR/DR <NUM> before the AR/DR <NUM> programs multiple cells of the configuration memory (CRAM) <NUM> at once (e.g., instead of programming the configuration memory (CRAM) <NUM> one cell at a time). This may allow large quantities of data from the sector-aligned memory <NUM> to rapidly enter the CRAM <NUM> cells or the in-fabric memory <NUM>. As noted above, this may take place much more quickly than the time involved in receiving the entire bitstream <NUM> via the CNOC <NUM>. In some cases, it may be <NUM>% faster, twice as fast, 5x as fast, 10x as fast, 20x as fast, 50x as fast, 100x as fast, 200x as fast, 500x as fast, 1000x as fast, or faster, to program the CRAM <NUM> and/or in-fabric memory <NUM> with bitstream <NUM> directly from sector-aligned memory <NUM> than to program the CRAM <NUM> and/or in-fabric memory <NUM> with the bitstream <NUM> from the CNOC <NUM>.

In any suitable configuration that includes sector-aligned memory <NUM>, including but not limited to those shown in <FIG> and <FIG>, data may be transferred to or from the sector-aligned memory <NUM> and used by the programmable logic fabric (e.g., a circuit design implemented by the programmable logic elements). In one example, shown by a flowchart <NUM> of <FIG>, a circuit design such as the configuration program <NUM> may cause the control interface (CTRL I/F) <NUM> to issue a control signal on the control pathway <NUM> to the sector-aligned memory <NUM>, the sector controller (SC) <NUM>, and/or the memory manager <NUM> (block <NUM> of <FIG>). The control signal may request data transfer from local fabric memory, such as the in-fabric memory <NUM> or registers of the programmable logic elements <NUM>, to the sector-aligned memory <NUM>. Control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, the sector controller (SC) <NUM>, and/or the memory manager <NUM> may cause desired contents of the local fabric memory, such as the in-fabric memory <NUM> or registers of the programmable logic elements <NUM>, to be stored in the sector-aligned memory <NUM> (block <NUM> of <FIG>).

<FIG> represents an example of a data transfer from the in-fabric memory <NUM> to the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, and/or the sector controller (SC) <NUM> may coordinate data transfer from the in-fabric memory <NUM> to the sector-aligned memory <NUM>. The data from the in-fabric memory <NUM> may be downloaded into the AR/DR <NUM> under the direction of the sector controller (SC) <NUM>, and the AR/DR <NUM> may pass the data to the sector-aligned memory <NUM>.

<FIG> represents another example of a data transfer from the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> to the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, and/or the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM> may coordinate data transfer from the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> to the sector-aligned memory <NUM>. The data from the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> may be transferred from the data interface (DATA I/F) <NUM> to the sector-aligned memory <NUM> using the data pathway <NUM> under instruction from control signals on the control pathway <NUM> by the control interface (CTRL I/F) <NUM>.

<FIG> represents an example of a data transfer from the in-fabric memory <NUM> to the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, the sector controller (SC) <NUM> and/or the memory manager <NUM> may coordinate data transfer from the in-fabric memory <NUM> to the sector-aligned memory <NUM>. For example, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, and/or the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM> may instruct the sector controller (SC) <NUM> to cause the memory manager <NUM> to carry out the data transfer. The data from the in-fabric memory <NUM> may be downloaded into the AR/DR <NUM> in a pipelined manner using the pipelining circuitry <NUM>, under the control of the memory manager <NUM>, which may enable large amounts of data to be rapidly transferred from the in-fabric memory <NUM> to the sector-aligned memory <NUM>.

Data may also be transferred from the sector-aligned memory <NUM> to the in-fabric memory <NUM> and/or a configuration program <NUM> in the programmable logic fabric (e.g., a circuit design implemented by the programmable logic elements). In one example, shown by a flowchart <NUM> of <FIG>, a circuit design such as the configuration program <NUM> may cause the control interface (CTRL I/F) <NUM> to issue a control signal on the control pathway <NUM> to the sector-aligned memory <NUM>, the sector controller (SC) <NUM>, and/or the memory manager <NUM> (block <NUM> of <FIG>). The control signal may request data transfer to local fabric memory, such as the in-fabric memory <NUM> or registers of the programmable logic elements <NUM>, from the sector-aligned memory <NUM>. Control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, the sector controller (SC) <NUM>, and/or the memory manager <NUM> may cause desired contents of the sector-aligned memory <NUM> to be transferred to local fabric memory, such as the in-fabric memory <NUM> or registers of the programmable logic elements <NUM> (block <NUM> of <FIG>). The transferred data may be stored into the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> (block <NUM> of <FIG>).

<FIG> represents an example of a data transfer to the in-fabric memory <NUM> from the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, and/or the sector controller (SC) <NUM> may initiate a data transfer to the in-fabric memory <NUM> from the sector-aligned memory <NUM>. The data from the sector-aligned memory <NUM> may be uploaded into the AR/DR <NUM>, which may program the data into the in-fabric memory <NUM> under the direction of the sector controller (SC) <NUM>.

<FIG> represents another example of a data transfer to the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> from the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, and/or the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM> may coordinate data transfer to the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> from the sector-aligned memory <NUM>. The data from the sector-aligned memory <NUM> may be received on the data interface (DATA I/F) <NUM> and provided to the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM>, using the data pathway <NUM> under instruction from control signals on the control pathway <NUM> by the control interface (CTRL I/F) <NUM>.

<FIG> represents an example of a data transfer to the in-fabric memory <NUM> from the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM>, the sector controller (SC) <NUM> and/or the memory manager <NUM> may coordinate data transfer from the in-fabric memory <NUM> to the sector-aligned memory <NUM>. For example, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, and/or the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM> may instruct the sector controller (SC) <NUM> to cause the memory manager <NUM> to carry out the data transfer. The data from the sector-aligned memory <NUM> may be uploaded into the AR/DR <NUM> and programmed into the in-fabric memory <NUM> in a pipelined manner using the pipelining circuitry <NUM>, under the control of the memory manager <NUM>. This may enable large amounts of data to be rapidly transferred to the in-fabric memory <NUM> from the sector-aligned memory <NUM>.

<FIG> represents another example of a data transfer from the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> to the sector-aligned memory <NUM> using the circuitry described above with reference to <FIG>. As such, additional description of elements with the same numbering as those in <FIG> may be found in the text above. Here, the configuration program <NUM>, control circuitry such as a soft or hardened controller implemented in the programmable logic elements <NUM>, and/or the control interface (CTRL I/F) <NUM> and the data interface (DATA I/F) <NUM> may coordinate data transfer to the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM> from the sector-aligned memory <NUM>. The data from the sector-aligned memory <NUM> may be transferred to the data interface (DATA I/F) <NUM> to the sector-aligned memory <NUM> using the data pathway <NUM> under instruction from control signals on the control pathway <NUM> by the control interface (CTRL I/F) <NUM>, and subsequently programmed into the in-fabric memory <NUM> and/or registers of the programmable logic elements <NUM>.

The programmable logic device <NUM> may be, or may be a component of, a data processing system. For example, the programmable logic device <NUM> may be a component of a data processing system <NUM>, shown in <FIG>. The data processing system <NUM> includes a host processor <NUM>, memory and/or storage circuitry <NUM>, and a network interface <NUM>. The data processing system <NUM> may include more or fewer components (e.g., electronic display, user interface structures, application specific integrated circuits (ASICs)). The host processor <NUM> may include any suitable processor, such as an Intel® Xeon® processor or a reduced-instruction processor (e.g., a reduced instruction set computer (RISC), an Advanced RISC Machine (ARM) processor) that may manage a data processing request for the data processing system <NUM> (e.g., to perform machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or the like). The memory and/or storage circuitry <NUM> may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, or the like. The memory and/or storage circuitry <NUM> may be considered external memory to the programmable logic device <NUM>, and may hold data to be processed by the data processing system <NUM>. In some cases, the memory and/or storage circuitry <NUM> may also store configuration programs (bitstreams) for programming the programmable logic device <NUM>. The network interface <NUM> may allow the data processing system <NUM> to communicate with other electronic devices. The data processing system <NUM> may include several different packages or may be contained within a single package on a single package substrate.

In one example, the data processing system <NUM> may be part of a data center that processes a variety of different requests. For instance, the data processing system <NUM> may receive a data processing request via the network interface <NUM> to perform machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or some other specialized task. The host processor <NUM> may cause the programmable logic fabric of the programmable logic device <NUM> to be programmed with a particular accelerator related to requested task. For instance, the host processor <NUM> may instruct that configuration data (bitstream) stored on the memory / storage <NUM> or cached in sector-aligned memory of the programmable logic device <NUM> to be programmed into the programmable logic fabric of the programmable logic device <NUM>. The configuration data (bitstream) may represent a circuit design for a particular accelerator function relevant to the requested task. Due to the high density of the programmable logic fabric, the proximity of the substantial amount of sector-aligned memory to the programmable logic fabric, or other features of the programmable logic device <NUM> that are described here, the programmable logic device <NUM> may rapidly assist the data processing system <NUM> in performing the requested task. Indeed, in one example, an accelerator may assist with a voice recognition task less than a few milliseconds (e.g., on the order of microseconds) by rapidly accessing and processing large amounts of data in the accelerator using sector-aligned memory.

The methods and devices of this disclosure may be incorporated into any suitable circuit. For example, the methods and devices may be incorporated into numerous types of devices such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), and microprocessors, just to name a few.

Moreover, while the method operations have been described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of overlying operations is performed as desired.

Claim 1:
An integrated circuit device comprising:
programmable logic fabric (<NUM>, <NUM>, <NUM>) disposed on a first integrated circuit die (<NUM>), wherein the programmable logic fabric (<NUM>, <NUM>, <NUM>) comprises a first sector of programmable logic fabric (<NUM>, <NUM>, <NUM>) and a second sector of programmable logic fabric (<NUM>, <NUM>, <NUM>), wherein the first sector of programmable logic fabric (<NUM>, <NUM>, <NUM>) is configured to be programmed with a circuit design that operates on a first set of data; and
sector-aligned memory (<NUM>) disposed on a second integrated circuit die (<NUM>), wherein the sector-aligned memory (<NUM>) comprises a first sector of sector-aligned memory (<NUM>) directly accessible by the first sector of programmable logic fabric (<NUM>, <NUM>, <NUM>) and a second sector of sector-aligned memory (<NUM>) directly accessible by the second sector of programmable logic fabric (<NUM>, <NUM>, <NUM>), wherein the first sector of sector-aligned memory (<NUM>) is configured to store the first set of data,
wherein the first sector of programmable logic fabric (<NUM>, <NUM>, <NUM>) comprises in-fabric memory (<NUM>) configured to be written with data from the sector-aligned memory (<NUM>),
the first integrated circuit die (<NUM>) and the second integrated circuit die (<NUM>) are vertically stacked; and
the first sector of programmable logic fabric (<NUM>, <NUM>, <NUM>) is aligned with the first sector of sector-aligned memory (<NUM>).