Patent Description:
A GPU is an electronic subsystem (typically a chipset) designed to rapidly process images intended for output to a display device. GPUs are used in embedded systems, mobile phones, personal computers, workstations, digital cameras, game consoles, and other digital systems. The highly parallel structure of the GPU makes it more efficient than a general-purpose central processing unit (CPU) for certain tasks.

An image histogram is a typically two-dimensional data structure that describes the number of pixels of an image across a range of color values. Conventionally, the range of color values forms the x-axis, and the number of pixels forms the y-axis - with darker colors at the lower x-axis values. A large number of tasks in image processing (for example, thresholding) involve creating a histogram of image color values. In thresholding, each pixel in an image is replaced with a black pixel if the image intensity for the pixel is less than a fixed constant T, or a white pixel if the image intensity is greater than that constant. These sorts of histograms are most often used for tasks like edge detection, color correction, image segmentation, co-occurrence matrices, and black-and-white image conversion, which can be prerequisites for more complex image analysis tasks like object and text recognition.

As an example, the article <NPL> discloses a method for histogram computation using a GPU in shader programs.

The technology described herein includes a computer-implemented method according to claim <NUM>, a computer program according to claim <NUM>, and a system according to claim <NUM> to create grayscale histograms of input images.

In some examples for a hierarchical partition of the set of output image patches, wherein each hierarchical node has at least two children, the GPU sums from the lowest level to the highest level, each nth pixel value. In some such examples, each output image patch is a 16x16 pixel array and each parent other than the hierarch has four children.

The color value of each pixel in an output image patch is formatted in OpenGL RBGA unsigned integral format as a base <NUM> number with "R" as the least significant place, and "A" is the most significant place. In some such examples, "A" is formatted as a base <NUM> complement. In some such examples, each output image patch is a 16x16 pixel array.

In some examples, counting the number of pixels, creating the corresponding output image patch, and combining the output image patches into a single composite image is performed on the GPU using one or more fragment shaders.

Traditional methods for calculating histograms are prohibitively time consuming when performing image processing on a device with a GPU, particularly with the GPUs typically found in mobile devices. While there are approaches for generating an image histogram using a device's CPU, such approaches perform poorly on a GPU, for example, requiring <NUM> full scans of the entire input image for a grayscale image. Further, GPUs are typically tailored to processing image data structures, and not histograms.

Examples of the technology disclosed herein can generate image histograms on a GPU, in some instances in a small number O(log N) of fast GPU passes - where "O(*)" represents "on the order of" and "N" is the number of pixels processes. The results can be made available to other GPU-implemented processes of the image processing pipeline without having to copy the results between the GPU, CPU, and system memory. Such copying is a relatively expensive operation that may introduce undesirable latency in real-time image processing applications.

By using and relying on the methods and systems described herein, the technology disclosed herein can create image histograms on a device's GPU without relying on the device's CPU. As such, the technology may be employed to perform image processing tasks such as thresholding, edge detection, color correction, image segmentation, co-occurrence matrices, black-and-white image conversion, and obj ect/text recognition in a way that makes use of the computing device's resources more efficient.

<FIG> is a block diagram depicting a portion of a simplified communications and processing architecture <NUM> of a typical device offering a graphical user interface (GUI) in accordance with certain examples. While each element in shown in the architecture is represented by one instance of the element, multiple instances of each can be included. While certain aspects of operation of the present technology are presented in examples related to <FIG> to facilitate enablement of the claimed invention, additional features of the present technology, also facilitating enablement of the claimed invention, are disclosed elsewhere herein.

In such an architecture <NUM>, a central processing unit (CPU) <NUM> and a graphics processing unit (GPU) <NUM> share access to system memory <NUM> via a system memory bus <NUM>. The CPU <NUM> and the GPU <NUM> communicate messages and data over a bus <NUM> that may also connect to other processors, sensors, and interface devices (not shown). Each of CPU <NUM> and GPU <NUM> include local memory (CPU local memory <NUM>, GPU local memory <NUM>). Local memory can include cache memory. Cache memory stores data (or instructions, or both) so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewhere. A cache hit occurs when the requested data can be found in a cache, while a cache miss occurs when it cannot. Cache hits are served by reading data from the cache, which typically is faster than recomputing a result or reading from a slower data store such as system memory <NUM> or transfer between the CPU <NUM> and GPU <NUM>. Thus, the more requests that can be served from the cache, the faster the system performs. The GPU <NUM> typically operates on data from local memory to drive display subsystem <NUM>. Throughout the discussion of examples, it should be understood that the terms "data" and "information" are used interchangeably herein to refer to text, images, audio, video, or any other form of information that can exist in a computer-based environment.

The architecture <NUM> illustrated is an example, and other means of establishing a communications link between the functional blocks can be used. Moreover, those having ordinary skill in the art having the benefit of the present disclosure will appreciate that the elements illustrated in <FIG> may have any of several other suitable computer system configurations. For example, the architecture <NUM> may be embodied as a mobile phone or handheld computer and may not include all the components described above.

In examples the technology presented herein may be part of any type of computing machine such as, but not limited to, those discussed in more detail with respect to <FIG>. Furthermore, any modules associated with any of these computing machines, such as modules described herein or any other modules (scripts, web content, software, firmware, or hardware) associated with the technology presented herein may be any of the modules discussed in more detail with respect to <FIG>. The computing machines discussed herein may communicate with one another as well as other computer machines or communication systems over one or more networks. The network may include any type of data or communications network, including any of the network technology discussed with respect to <FIG>.

The example methods illustrated in the figures are described hereinafter with respect to the components of the example architecture <NUM>. The example methods also can be performed with other systems and in other architectures. The operations described with respect to any of the figures can be implemented as executable code stored on a computer or machine readable non-transitory tangible storage medium (e.g., floppy disk, hard disk, ROM, EEPROM, nonvolatile RAM, CD-ROM, etc.) that are completed based on execution of the code by a processor circuit implemented using one or more integrated circuits; the operations described herein also can be implemented as executable logic that is encoded in one or more non-transitory tangible media for execution (e.g., programmable logic arrays or devices, field programmable gate arrays, programmable array logic, application specific integrated circuits, etc.).

Referring to <FIG>, and continuing to refer to <FIG> for context, methods <NUM> to create image histograms are illustrated in accordance with certain examples. In such methods <NUM>, a GPU <NUM> receives an input image - Block <NUM>. The input image is composed of a two-dimensional array of pixel color values. For example, the color of a pixel can be represented by a vector having components for red, blue, and green color intensities of the pixel. Examples disclosed herein operated on input images of the OpenGL® "RGBA" format, but are not restricted to that format. OpenGL is a cross-language, cross-platform application programming interface (API) for rendering graphics. The API is typically used to interact with a GPU <NUM> to achieve hardware-accelerated rendering. OpenGL enables the use of programs called "shaders" to manipulated images. In addition to <NUM>-bit values for each of red, green, and blue, the OpenGL RGBA format uses an <NUM>-bit "A," or "alpha," component. The <NUM>-bit format provides <NUM> discrete values from "<NUM>" to "<NUM>" for each pixel. The alpha component is typically used to represent the transparency of a pixel.

In OpenGL, color values can be stored in one of three ways: normalized integers, floating-point, or integral. Both normalized integer and floating-point formats will resolve, in a shader, to a vector of floating-point values; whereas integral formats will resolve to a vector of integers. Examples presented herein use the integral format for each of "R," "B," "G," and "A. " While the OpenGL RGBA format can represent virtually any color of pixel, examples disclosed herein operate on "grayscale" images. In the OpenGL RGBA format, grayscale pixel values are represented by R=B=G, with any applicable A. For example, the pixel value (<NUM>, <NUM>, <NUM>, <NUM>) represents a solid (A = max, solid) medium gray, the pixel value (<NUM>, <NUM>, <NUM>, <NUM>) represents solid black, and the pixel value (<NUM>, <NUM>, <NUM>, <NUM>) represents solid white.

Referring to <FIG>, and continuing to refer to prior figures for context, an input grayscale image <NUM> is shown, in accordance with certain examples. In a continuing example, consider the <NUM> pixel high x <NUM> pixel wide grayscale image <NUM> of <FIG>. The image <NUM> consists of a pattern of vertical stripes - <NUM> pixels wide of solid HTML black (<NUM>, <NUM>, <NUM>, <NUM>) <NUM>, <NUM> pixels wide of solid HTML white (<NUM>, <NUM>, <NUM>, <NUM>) <NUM>, <NUM> pixels wide of solid HTML silver (<NUM>, <NUM>, <NUM>, <NUM>) <NUM>, and <NUM> pixels wide of solid HTML gray (<NUM>, <NUM>, <NUM>, <NUM>) <NUM>. Note that this (black <NUM>, white <NUM> , silver <NUM>, and gray <NUM>) pattern repeats four full times, and then only the black <NUM>, white <NUM>, and silver <NUM> stripes repeat one additional time. As a result, there are (64x4x5) = <NUM> black pixels, <NUM> white pixels, and <NUM> silver pixels - but only (64x4x4) = <NUM> gray pixels.

For each particular input patch of pixels of a set of input patches partitioning the input image, and in parallel for each particular grayscale value the range, the GPU <NUM> counts the number of pixels in the particular input patch having the particular grayscale value - Block <NUM>. TABLE <NUM> presents example pseudocode for performing this count.

Referring to <FIG>, and continuing to refer to prior figures for context, the input grayscale image is shown partitioned into input image patches <NUM> and <NUM>, in accordance with certain examples. In the continuing example, as shown in <FIG>, <NUM> pixel x <NUM> pixel input image patches are used as a basis. Each of four rows of such input image patches includes four full input image patches <NUM> and one <NUM> pixel high x <NUM> pixel wide final input image patch <NUM>. In some examples, uniformly dimensioned input image patches are used throughout without substantial changes to the technology.

The GPU uses OpenGL shaders to count the number of pixels of each of <NUM> grayscale values in each input patch. In the continuing example, all of the input patches have the same number of black, white and silver pixels - <NUM>. Sixteen of the twenty patches have <NUM> gray pixels, while the remaining four final input patches <NUM> have no gray pixels.

In parallel for each particular input patch of pixels of the set of input patches partitioning the input image, the shaders running on the GPU <NUM> create an output image patch as an ordered sequence of N pixels, with the color value of the nth pixel in each corresponding output patch representing the count of pixels in the particular input patch having the nth grayscale value - Block <NUM>. In the continuing example, N = <NUM> - the number of different grayscale values in the OpenGL RBGA scheme.

It is important to note that the position of a pixel in a <NUM> pixel x <NUM> pixel output image patch corresponds to a color in the OpenGL RBGA grayscale scheme. The value of the color of a given output image patch pixel corresponds to the count of pixels of that color in the input image. Note that a transformation has taken place - position in the output image patch corresponds to grayscale color, and color in the output image patch corresponds to count of input patch pixels of that grayscale color. Further, each output patch, including the output patches corresponding to <NUM> pixel x <NUM> pixel input patches, is <NUM> pixels x <NUM> pixels.

The shaders running on GPU <NUM> format the color value of each pixel in each output image patch in OpenGL RBGA unsigned integral format as a base <NUM> number with "R" as the least significant place, and "A" is the most significant place. However, to facilitate the use of the resulting output images in troubleshooting, the "A" place is formatted as the base <NUM> complement of its actual value in the count. Otherwise, in a typical use of "A," given that the "A" place is the most significant in the output image patch coding scheme, "A" will equal "<NUM>" (transparent) until well over <NUM>,<NUM>,<NUM> pixels of a given grayscale color are counted.

Referring to <FIG>, and continuing to refer to prior figures for context, an output patch <NUM> is shown as pixels <NUM> (i, j), where n = (i-<NUM>)*<NUM>+j, and as a histogram <NUM>, in accordance with examples of the present technology. In the output patch, the nth = <NUM>st pixel - (<NUM>, <NUM>, <NUM>, <NUM>) in four-place base <NUM> notation - corresponds to the <NUM>st grayscale value (<NUM>, <NUM>, <NUM>, <NUM> = complement<NUM> (<NUM>)) - black.

In the continuing example, there are <NUM> pixels of the input image with the color value (<NUM>, <NUM>, <NUM>, <NUM>) = black. The GPU sets the color value of the <NUM>st pixel in the output patch (an output patch position of the <NUM>st pixel in the <NUM>st row corresponding to black) to (<NUM>, <NUM>, <NUM>, <NUM>) - a shade of red. There are <NUM> pixels of the input image with the color value (<NUM>, <NUM>, <NUM>, <NUM>) = white. The GPU sets the color value of the <NUM>st pixel in the output patch (an output patch position corresponding to white) to (<NUM>, <NUM>, <NUM>, <NUM>) - as with the first pixel, the same shade of red. There are <NUM> pixels of the input image with the color value (<NUM>, <NUM>, <NUM>, <NUM>) = silver. The GPU sets the color value of the <NUM>rd pixel (the last pixel in the <NUM>th row of the output image patch) in the output patch (an output patch position corresponding to silver) to (<NUM>, <NUM>, <NUM>, <NUM>) - as with the first and second pixels, a shade of red. And finally, there are <NUM> pixels of the input image with the color value (<NUM>, <NUM>, <NUM>, <NUM>) = gray. The GPU sets the color value of the <NUM>rd pixel (the last pixel in the <NUM>th row of the output image patch) in the output patch (an output patch position corresponding to silver) to (<NUM>, <NUM>, <NUM>, <NUM>) - as with the previous pixels, a shade of red. Note that the width of each histogram column has been lightly exaggerated for visibility.

After representing the grayscale histograms for each input patch as an output patch as described above, the GPU combines the output image patches into a single composite output image of N pixels - Block <NUM>. The pixel value of the nth pixel in the single composite output image corresponding to the count of pixels in the input image having the nth grayscale value.

In the continuing example, for a hierarchical partition of the set of output image patches, wherein each hierarchical node has at least two children, the GPU sums, from the lowest level to the highest level, each nth pixel value. Referring to <FIG> and continuing to refer to prior figures for context, two views <NUM>, <NUM> of a histogram <NUM> are shown, in accordance with examples of the present technology. In the continuing example, consider pixel #<NUM> in each of output image patches 510a, 510b, 510c, and 510d. Each has the value (<NUM>, <NUM>, <NUM>, <NUM>) or <NUM><NUM> (since the "R" place is the least significant base<NUM> place. The GPU sums the color values of each <NUM> #<NUM> pixel from output image patches 510a, 510b, 510c, and 510d - giving <NUM>, or in the notation of the present technology (<NUM>, <NUM>, <NUM>, <NUM>), a very dark green. Histogram <NUM> reflects this count in the first histogram bar from the left. The GPU sums remaining groups of corresponding pixels from patches 510a, 510b, 510c, and 510d, resulting in the remaining bars shown in histogram <NUM>. The GPU performs a parallel accumulation for output image patch sets {510e, 510f, <NUM>, <NUM>}, {510i, 510j, <NUM>, <NUM>}, and {<NUM>, 510n, 510o, 510p}. The summing converts the digits to integers, adds the integers with carry, and then converts the integers back into floating point.

Though as can be seen in <FIG>, each of {510q, 510r, <NUM>, 510t} shows no count at pixel <NUM> (corresponding to gray) - as opposed to the value (<NUM>, <NUM>, <NUM>, <NUM>) at pixel <NUM> in output patch 510p. The missing bar at grayscale value <NUM> in the corresponding histogram <NUM> is another view of the results of accumulating corresponding pixel counts from <NUM> pixel x <NUM> pixel output patches {510q, 510r, <NUM>, 510t}.

Referring to <FIG>, and continuing to refer to prior figures for context, <NUM> illustrates the next-to-last <NUM> and last <NUM> stages of a histogram, in accordance with examples of the present technology. After the processes described in connection with <FIG> and <FIG> have been completed, the GPU is storing five (<NUM>) <NUM> pixel x <NUM> pixel patches, that the GPU sums in a pixel by pixel fashion to form histogram <NUM>. Referring to <FIG>, and continuing to refer to prior figures for context, <NUM> illustrates the last stages of the output image histogram in both an image and as the histogram represented by the image. In the continuing example, the <NUM> pixel x <NUM> pixel output image patch <NUM> represents the same histogram of the original complete grayscale input image <NUM>. The GPU assigns the pixels corresponding to black, silver, and white color values reflecting the count of each such color pixel from the original grayscale input image <NUM> - the blue color value (<NUM>, <NUM>, <NUM>, <NUM>), corresponding to the count <NUM>. The GPU assigns the pixel corresponding to the gray color value reflecting the count of each gray pixels from the original grayscale input image <NUM> - the blue color value (<NUM>, <NUM>, <NUM>, <NUM>), corresponding to the count <NUM>.

<FIG> depicts a computing machine <NUM> and a module <NUM> in accordance with certain examples. The computing machine <NUM> may correspond to any of the various computers, servers, mobile devices, embedded systems, or computing systems presented herein. The module <NUM> may comprise one or more hardware or software elements configured to facilitate the computing machine <NUM> in performing the various methods and processing functions presented herein. The computing machine <NUM> may include various internal or attached components such as a processor <NUM>, system bus <NUM>, system memory <NUM>, storage media <NUM>, input/output interface <NUM>, and a network interface <NUM> for communicating with a network <NUM>.

The computing machine <NUM> may be implemented as a conventional computer system, an embedded controller, a laptop, a server, a mobile device, a smartphone, a set-top box, a kiosk, a router or other network node, a vehicular information system, one or more processors associated with a television, a customized machine, any other hardware platform, or any combination or multiplicity thereof. The computing machine <NUM> may be a distributed system configured to function using multiple computing machines interconnected via a data network or bus system.

The processor <NUM> may be configured to execute code or instructions to perform the operations and functionality described herein, manage request flow and address mappings, and to perform calculations and generate commands. The processor <NUM> may be configured to monitor and control the operation of the components in the computing machine <NUM>. The processor <NUM> may be a general purpose processor, a processor core, a multiprocessor, a reconfigurable processor, a microcontroller, a digital signal processor ("DSP"), an application specific integrated circuit ("ASIC"), a graphics processing unit ("GPU"), a field programmable gate array ("FPGA"), a programmable logic device ("PLD"), a controller, a state machine, gated logic, discrete hardware components, any other processing unit, or any combination or multiplicity thereof. The processor <NUM> may be a single processing unit, multiple processing units, a single processing core, multiple processing cores, special purpose processing cores, co-processors, or any combination thereof. According to certain examples, the processor <NUM> along with other components of the computing machine <NUM> may be a virtualized computing machine executing within one or more other computing machines.

The system memory <NUM> may include non-volatile memories such as read-only memory ("ROM"), programmable read-only memory ("PROM"), erasable programmable read-only memory ("EPROM"), flash memory, or any other device capable of storing program instructions or data with or without applied power. The system memory <NUM> may also include volatile memories such as random access memory ("RAM"), static random access memory ("SRAM"), dynamic random access memory ("DRAM"), and synchronous dynamic random access memory ("SDRAM"). Other types of RAM also may be used to implement the system memory <NUM>. The system memory <NUM> may be implemented using a single memory module or multiple memory modules. While the system memory <NUM> is depicted as being part of the computing machine <NUM>, one skilled in the art will recognize that the system memory <NUM> may be separate from the computing machine <NUM> without departing from the scope of the subject technology. It should also be appreciated that the system memory <NUM> may include, or operate in conjunction with, a non-volatile storage device such as the storage media <NUM>.

The storage media <NUM> may include a hard disk, a floppy disk, a compact disc read only memory ("CD-ROM"), a digital versatile disc ("DVD"), a Blu-ray disc, a magnetic tape, a flash memory, other non-volatile memory device, a solid state drive ("SSD"), any magnetic storage device, any optical storage device, any electrical storage device, any semiconductor storage device, any physical-based storage device, any other data storage device, or any combination or multiplicity thereof. The storage media <NUM> may store one or more operating systems, application programs and program modules such as module <NUM>, data, or any other information. The storage media <NUM> may be part of, or connected to, the computing machine <NUM>. The storage media <NUM> may also be part of one or more other computing machines that are in communication with the computing machine <NUM> such as servers, database servers, cloud storage, network attached storage, and so forth.

The module <NUM> may comprise one or more hardware or software elements configured to facilitate the computing machine <NUM> with performing the various methods and processing functions presented herein. The module <NUM> may include one or more sequences of instructions stored as software or firmware in association with the system memory <NUM>, the storage media <NUM>, or both. The storage media <NUM> may therefore represent examples of machine or computer readable media on which instructions or code may be stored for execution by the processor <NUM>. Machine or computer readable media may generally refer to any medium or media used to provide instructions to the processor <NUM>. Such machine or computer readable media associated with the module <NUM> may comprise a computer software product. It should be appreciated that a computer software product comprising the module <NUM> may also be associated with one or more processes or methods for delivering the module <NUM> to the computing machine <NUM> via the network <NUM>, any signal-bearing medium, or any other communication or delivery technology. The module <NUM> may also comprise hardware circuits or information for configuring hardware circuits such as microcode or configuration information for an FPGA or other PLD.

The input/output ("I/O") interface <NUM> may be configured to couple to one or more external devices, to receive data from the one or more external devices, and to send data to the one or more external devices. Such external devices along with the various internal devices may also be known as peripheral devices. The I/O interface <NUM> may include both electrical and physical connections for operably coupling the various peripheral devices to the computing machine <NUM> or the processor <NUM>. The I/O interface <NUM> may be configured to communicate data, addresses, and control signals between the peripheral devices, the computing machine <NUM>, or the processor <NUM>. The I/O interface <NUM> may be configured to implement any standard interface, such as small computer system interface ("SCSI"), serial-attached SCSI ("SAS"), fiber channel, peripheral component interconnect ("PCI"), PCI express (PCIe), serial bus, parallel bus, advanced technology attached ("ATA"), serial ATA ("SATA"), universal serial bus ("USB"), Thunderbolt, FireWire, various video buses, and the like. The I/O interface <NUM> may be configured to implement only one interface or bus technology. Alternatively, the I/O interface <NUM> may be configured to implement multiple interfaces or bus technologies. The I/O interface <NUM> may be configured as part of, all of, or to operate in conjunction with, the system bus <NUM>. The I/O interface <NUM> may include one or more buffers for buffering transmissions between one or more external devices, internal devices, the computing machine <NUM>, or the processor <NUM>.

The I/O interface <NUM> may couple the computing machine <NUM> to various input devices including mice, touch-screens, scanners, electronic digitizers, sensors, receivers, touchpads, trackballs, cameras, microphones, keyboards, any other pointing devices, or any combinations thereof. The I/O interface <NUM> may couple the computing machine <NUM> to various output devices including video displays, speakers, printers, projectors, tactile feedback devices, automation control, robotic components, actuators, motors, fans, solenoids, valves, pumps, transmitters, signal emitters, lights, and so forth.

The computing machine <NUM> may operate in a networked environment using logical connections through the network interface <NUM> to one or more other systems or computing machines across the network <NUM>. The network <NUM> may include wide area networks (WAN), local area networks (LAN), intranets, the Internet, wireless access networks, wired networks, mobile networks, telephone networks, optical networks, or combinations thereof. The network <NUM> may be packet switched, circuit switched, of any topology, and may use any communication protocol. Communication links within the network <NUM> may involve various digital or an analog communication media such as fiber optic cables, free-space optics, waveguides, electrical conductors, wireless links, antennas, radio-frequency communications, and so forth.

The processor <NUM> may be connected to the other elements of the computing machine <NUM> or the various peripherals discussed herein through the system bus <NUM>. It should be appreciated that the system bus <NUM> may be within the processor <NUM>, outside the processor <NUM>, or both. According to certain examples, any of the processor <NUM>, the other elements of the computing machine <NUM>, or the various peripherals discussed herein may be integrated into a single device such as a system on chip ("SOC"), system on package ("SOP"), or ASIC device.

Examples may comprise a computer program that embodies the functions described and illustrated herein, wherein the computer program is implemented in a computer system that comprises instructions stored in a machine-readable medium and a processor that executes the instructions. However, it should be apparent that there could be many different ways of implementing examples in computer programming, and the examples should not be construed as limited to any one set of computer program instructions. Further, a skilled programmer would be able to write such a computer program to implement an example of the disclosed examples based on the appended flow charts and associated description in the application text. Therefore, disclosure of a particular set of program code instructions is not considered necessary for an adequate understanding of how to make and use examples. Further, those skilled in the art will appreciate that one or more aspects of examples described herein may be performed by hardware, software, or a combination thereof, as may be embodied in one or more computing systems. Moreover, any reference to an act being performed by a computer should not be construed as being performed by a single computer as more than one computer may perform the act.

Claim 1:
A computer-implemented method to create grayscale histograms of input images, comprising:
in a graphics processing unit (GPU):
receiving an input image comprising an array of pixels, each pixel having a grayscale value from a range of N grayscale values;
for each particular input patch of pixels of a set of input patches partitioning the input image:
in parallel for each particular grayscale value in the range, counting the number of pixels in the particular input patch having the particular grayscale value; and
creating an output image patch as an ordered sequence of N pixels, with the color value of the nth pixel in each corresponding output patch representing the count of pixels in the particular input patch having the nth grayscale value;
formatting the color value at each pixel of the output image patch in OpenGL RBGA unsigned integral format as a base <NUM> number with "R" as the least significant place, and "A" is the most significant place; and
combining the output image patches into a single composite output image of N pixels for output as a grayscale histogram, the pixel value of the nth pixel in the single composite output image corresponding to the count of pixels in the input image having the nth grayscale value.