Patent Description:
Various solutions have been proposed and used to reduce interactions between the solder material and the metal layers that are being bonded/connected. The solutions typically include barriers applied in layers to prevent diffusion from one layer into another. For example, coating contact areas for inhibiting diffusion or layering diffusion-inhibiting layers into the metal contacts have been proposed as diffusion barriers. However, application of the diffusion barrier layer on the front of the wafer may be ineffective because etching vias using Silicon Carbide (SiC) or GaN may continue to etch through the first two or three metal layers on the wafer frontside. In addition, the uneven topology of the via structure in SiC/GaN devices poses a challenge to cover with an evaporated or sputtered barrier layer. Furthermore, if a barrier layer is applied under a plated gold layer, the barrier layer may increase the series resistance between the frontside metal layer and the backside ground connection (i.e., backside metal layer). A semiconductor device containing a through hole is known from <CIT>. A semiconductor device is known from <CIT>.

In accordance with the present invention, there is provided a method and an integrated circuit as defined by claims <NUM> and <NUM>.

The details of one or more embodiments of the disclosure are outlined in the accompanying drawings and the description below.

The foregoing features may be more fully understood from the following description of the drawings in which:.

Relative descriptions used herein, such as left, right, up, and down, are with reference to the figures, are merely relative and not meant in a limiting sense. Additionally, for clarity, common items and circuitry, such as integrated circuits, resistors, capacitors, transistors, and the like, have not been included in the figures, as can be appreciated by those of ordinary skill in the pertinent art. Unless otherwise specified, the illustrated embodiments may be understood as providing illustrative features of varying detail of certain embodiments.

Additionally, the shapes and sizes of components are intended to be only illustrative and unless otherwise specified, can be altered without materially affecting or limiting the scope of the concepts sought to be protected herein.

Referring now to <FIG>, an exemplary figure showing damages from solder diffusion in a prior art integrated circuit is provided. For an integrated circuit (IC) that is coated on the backside with an Au (gold) layer, the ground attachment to the chip is conventionally made with a Gold-Tin (Au-Sn) eutectic solder. For some type of chips having higher power, the chips may run at higher temperatures which may result in an acceleration of Au-Sn diffusion. The diffusion may happen for both directions. First, Tin (Sn) in the solder material (Au-Sn) may diffuse (in-diffusion) to the gold layer. The gold (Au) in the gold layer may also diffuse (out-diffusion) towards the solder layer. The solder diffusion may cause distortion (e.g., metal protruding out of the frontside) <NUM> in the airbridge patterns at the frontside of the wafer. The distortion <NUM> may be visible from the frontside of the wafer. The diffusion may also form voids <NUM> in the thin frontside Au layer of the wafer.

Referring now to <FIG>, diffusion from solder may occur when solder material fills a via formed in a substrate. An integrated circuit (IC) package <NUM> includes a substrate <NUM>, a frontside gold layer <NUM>, and a backside gold layer <NUM>. When solder material (e.g., Au-Sn) <NUM> is applied to the backside gold layer <NUM>, excessive wetting of the solder may cause the solder material <NUM> to fill the via <NUM> formed in the substrate <NUM> where the sides of the via are covered by the backside gold layer <NUM>. In addition, the solder material <NUM> may diffuse into the backside gold layer <NUM>. In this case, the diffusion of the solder material <NUM> and the frontside gold layer <NUM> may cause damage to the IC <NUM> by creating a distortion <NUM> onto the frontside gold layer <NUM>. Additionally, the diffusion may cause voids <NUM> formed inside of the frontside gold layer <NUM> and/or the backside gold layer <NUM>. Additionally, the difference in thermal expansion between the solder material <NUM> and the substrate <NUM> may result in physical damage to the substrate <NUM> such as cracking when the integrated circuit package <NUM> is operated at an elevated temperature. The physical damage to the substrate <NUM> may be further increased when the solder material <NUM> fills the via <NUM>.

Referring now to <FIG>, the figures showing voids formed from solder diffusion in a conventional IC package are presented. <FIG> shows an example of minor voids formed in frontside and backside gold layers from solder diffusion. When solder material (e.g., <NUM> in <FIG>) fills a via and diffuse through the backside gold layer, Kirkendall void formation can occur in metal structures on the frontside of the wafer such as the source connected field plate <NUM> and <NUM>. For example, the solder material may affect a source connected field plate in the gate area <NUM>. The area <NUM> shows that small size voids are made in the area adjacent to where the source-connected field plate (SCFP) metal contacts the ohmic contact metal. <FIG> shows an example of severe damages caused by solder diffusion. Areas <NUM>, <NUM> show that voids are formed in the gold layer severe enough such that the gold layer is no longer functioning as a contact, which creates an isolated (i.e., disconnected) area at <NUM>.

Referring now to <FIG>, an integrated circuit (IC) package <NUM> having a diffusion barrier in accordance with example embodiments of the invention is presented. The IC <NUM> comprises a substrate or wafer <NUM>, a frontside metal layer <NUM>, a backside metal layer <NUM>, and a diffusion barrier <NUM>. In embodiments, the substrate <NUM> may comprise silicon carbide. The frontside metal layer <NUM> may be deposited on the substrate <NUM> as metal interconnects to connect active and passive components <NUM>. Gold (Au) may be used to form the frontside metal layer, but other suitable materials may be used. In embodiments, the frontside metal layer <NUM> in combination with other metals of the IC package may provide Schottky contacts or Ohmic contacts.

The connected active/passive components may form circuit areas <NUM> on the substrate <NUM>. When the fabrication of the frontside layer <NUM> is completed, the substrate <NUM> is further processed at the backside where one or more vias <NUM> are formed through the substrate to enable contact with frontside metal layer <NUM> for connection to ground, for example. In embodiments, the vias <NUM> may be formed by an etching process. In the one or more vias <NUM>, the backside metal layer <NUM> created by depositing a metal film on the backside of the substrate <NUM> and on the surface of the substrate in the vias <NUM>. At one end of the vias <NUM>, the backside metal layer <NUM> makes contact with the frontside metal layer <NUM>. The frontside and backside metal layers <NUM>, <NUM> may comprise gold, but any suitable material may be used. In some embodiments, the frontside metal layer may comprise Titanium (Ti), Gold (Au), Platinum (Pt), or Aluminum (Al). Alternately, Copper (Cu) or refractory metal such as Tantalum (Ta) and Tungsten (W) may be used in the frontside metal layer.

The backside metal layer <NUM> may substantially maintain the shape of the via <NUM>. In embodiments, the via <NUM> may have a tapered shape such that the bottom of the via <NUM> is smaller than the top of the via <NUM>. In some embodiments, a thin layer of other materials, for example, Titanium (Ti) or Titanium-Tungsten (TiW), can provide improved adhesion between the frontside layer <NUM> and the backside layer <NUM>, and the substrate <NUM>. In other embodiments, one or more layers of other materials to reduce electromigration between the layers <NUM>, <NUM> may be provided.

One or more breaks or solder-stops <NUM> may be formed in the backside metal layer <NUM>. The breaks <NUM> prevent a direct diffusion path in the backside metal layer <NUM>. In embodiments, the breaks <NUM> may be fabricated in the backside metal layer <NUM> by a patterning process. In embodiments, patterning the backside gold layer to have the breaks <NUM> may be done by using an Au-plating mask or an Au-etch mask. Herein, the diffusion barrier breaks <NUM> are positioned on the back of the wafer where the surface is flat, which is easier to cover and pattern than in the via <NUM>.

The diffusion barrier <NUM> may then be deposited on the backside metal layer <NUM> in the via <NUM> and at the top of the via and in the breaks <NUM>. The diffusion barrier <NUM> may substantially take on the shape of the vias <NUM>. The diffusion barrier <NUM> may comprise a metal which has a lower rate of diffusion of the solder material than the backside metal layer <NUM>. The diffusion barrier <NUM> may bridge the breaks <NUM> in the backside metal layer <NUM>. In addition, the breaks <NUM> may define locations of the boundaries for the diffusion barrier <NUM>. When the diffusion barrier <NUM> material has a lower rate of diffusion than soldering material (e.g., Au-Sn), damages caused by solder diffusion may be reduced or prevented. The material for the diffusion barrier <NUM> is selected such that the diffusion rate is reduced enough to prevent damage when the IC package is operated at its normal operating temperature for the predicted life of the product. In addition, the diffusion barrier <NUM> may prevent wetting of solder <NUM> such that the solder material does not fill the via <NUM> completely.

In embodiments, the diffusion barrier <NUM> may comprise Nickel (Ni). In other embodiments, the diffusion barrier may comprise Titanium Nitride (TiN), Tungsten Nitride (WN), Tantalum Nitride (TaN) or Chromium (Cr). In embodiments, the size of the break may be varied to the minimum to provide a sufficient barrier to diffusion while also minimizing the impact of added resistance between the backside metal layer <NUM> on the back of the wafer and the backside metal layer <NUM> in the via <NUM>. Any other suitable material that has a lower rate of diffusion and prevents wetting of solder material may also be used to form the diffusion barrier <NUM>. Herein, since the diffusion barrier <NUM> is deposited on the backside metal layer, the series resistance of the combined metal layers can be minimized since the resistance is averaged over a larger area than a diffusion barrier deposited between the metal layers.

In embodiments, the diffusion barrier <NUM> may be oxidized before the soldering material <NUM> is applied. Since oxidation of the barrier material contacting solder material prevents wetting of the soldering material, the diffusion barrier <NUM> may also function as a solder wetting barrier. In embodiments, the solder <NUM> on the diffusion barrier <NUM> does not have an excessive wetting condition and filling the via <NUM> with the soldering material <NUM> may be substantially prevented. In embodiments, some portion of the via <NUM> may be filled with the solder material <NUM>. Accordingly, the solder material <NUM> should not contact the backside metal layer <NUM> at the bottom of the via <NUM>. Thus, damages from the solder material <NUM>, such as voids in the metal layers (e.g., <NUM> in <FIG>) and distortions (e.g., <NUM> in <FIG>), may be further prevented. A ground plane <NUM> may be provided on top of the solder material <NUM>. The ground plane <NUM> may be connected to a ground terminal (not shown) and serve as a return path for current from different components on the IC chip.

Referring now to <FIG>, an illustrative flow diagram for fabricating an IC having a diffusion barrier is presented. In the figure, rectangular elements (typified by element <NUM> in <FIG>), herein denoted "processing blocks," represent instructions or groups of instructions. The processing blocks may represent steps performed in a process. The particular sequence of blocks described is illustrative only and can be varied without departing from the spirit of the concepts, structures, and techniques sought to be protected herein. Thus, unless otherwise stated, the blocks described below are unordered meaning that, when possible, the functions represented by the blocks can be performed in any convenient or desirable order.

In processing step <NUM>, a substrate or wafer is provided. In embodiments, the substrate (e.g., <NUM> in <FIG>) may comprise silicon carbide or a p-type substrate. In processing step <NUM>, on the frontside of the substrate, a frontside metal layer (e.g., <NUM> in <FIG>) is deposited. In embodiments, the frontside metal layer <NUM> may comprise a gold layer. In processing step <NUM>, a plurality of vias are formed in the substrate from the backside of the substrate. In embodiments, the vias may be formed by an etching process. In processing step <NUM>, a backside metal layer (e.g., <NUM> in <FIG>) is deposited in the vias. In embodiments, the backside metal layer may comprise a gold layer. The backside metal layer may conform to the shape of the via formed in the substrate. The backside metal layer also includes breaks (e.g., <NUM> in <FIG>) formed in the patterned backside metal layer.

In processing step <NUM>, a diffusion layer (e.g., <NUM> in <FIG>) may be deposited on the backside metal layer. In embodiments, the diffusion barrier may comprise nickel (Ni) or any other suitable material. The diffusion barrier may substantially maintain the shape of via.

According to the concepts described herein, combining a diffusion barrier break in the backside gold layer and covering the plated gold in the via with nickel (Ni) will reduce diffusion of Tin(Sn) of the solder material (Au-Sn) to the metal layers and also diffusion of Au towards the solder layer. In addition, the same plated Ni structure can be oxidized to further prevent the wetting of the Au-Sn solder in the vias.

Having described preferred embodiments, which serve to illustrate various concepts, structures and techniques, which are the subject of this patent, it will now become apparent that other embodiments incorporating these concepts, structures and techniques may be used. Accordingly, it is submitted that the scope of the patent should not be limited to the described embodiments but rather should be limited only by the scope of the following claims.

Claim 1:
A method for fabricating an integrated circuit, the method comprising:
providing (<NUM>) a substrate having a frontside and a backside;
depositing (<NUM>) a frontside metal layer on the frontside of the substrate;
forming (<NUM>) a via in the substrate;
depositing (<NUM>) a backside metal layer onto the backside of the substrate and into the via such that a portion of the backside metal layer is connected to a portion of the frontside metal layer;
depositing (<NUM>) a diffusion barrier layer onto the backside metal layer located in the via, the diffusion barrier substantially maintaining a shape of the via; and characterised in that
the backside metal layer comprises breaks proximate an end of the via corresponding to the backside of the substrate, and further including depositing the diffusion barrier into the breaks.