Patent Description:
An electronic device such as a smart phone or a tablet PC may perform various functions. For example, the electronic device may perform functions such as wireless communication, video recording, video playback, or music playback. The electronic device may be used while being connected to an accessory device wirelessly or in a wired manner. For example, the electronic device may be used while being connected to an earphone device via a connector. <CIT> discloses an electronic device including a connector comprising a plurality of terminals, the connector being configured to be connected with an external device; a circuit electrically connected to at least a subset of the plurality of terminals; and a processor electrically connected to the circuit, wherein the processor is configured to detect a connection of the external device through the connector, detect a first impedance of a first electrical path including a first terminal of the plurality of terminals, detect a second impedance of a second electrical path including a second terminal of the plurality of terminals, and determine a connection direction of the external device connected through the connector, based on the first impedance and the second impedance.

The electronic device may include a connector (e.g., a USB type-C connector) for charging the electronic device or connecting to an accessory device. The accessory device may be wiredly connected to the connector (e.g., the USB type-C connector) of the electronic device, and may receive a power signal and a data signal (e.g., a sound signal) from the electronic device. When the accessory device is an earphone device, the earphone device may output a sound through a speaker based on a sound signal received from the electronic device. For example, the earphone device may receive the sound signal as digital data of USB Audio Class (UAC) via a data pin (e.g., an USB Type-C D+/D- pin) and output the sound based on the sound signal.

When the earphone device is connected to the electronic device, current consumption of a battery may increase due to supply of a power signal. For example, the electronic device may boost a power signal (about <NUM>. 2V to about <NUM>. 5V) supplied from the battery to a power signal of about 5V and supply the power signal of about 5V to the earphone device. In this case, current consumption due to voltage boosting may increase and thus a battery discharge rate may increase.

Various embodiments of the disclosure may provide an electronic device that reduces current consumption based on recognition of an accessory device when the accessory device such as an earphone device is wiredly connected to a connector.

An electronic device is provided in accordance with claim <NUM>.

A method for supplying power from an electronic device to an external device is provided in accordance with claim <NUM>.

When the electronic device according to various embodiments disclosed in the disclosure recognizes the accessory device of a specified manufacturer via a device recognition pin (e.g., a CC pin) or a data pin (a D+ pin, a D- pin) of the connector, the electronic device may supply a power signal of a lower voltage than that of a power signal supplied via a power pin (e.g., VBUS pin) to the accessory device using the device recognition pin (e.g., a CC pin). Thus, unnecessary current consumption (or power consumption) may be reduced.

The electronic device according to various embodiments disclosed in the disclosure may allow the accessory device from being free of a circuit for power delivery (PD) communication, thereby reducing a manufacturing cost of the accessory device.

With regard to the description of the drawings, the same or similar reference numerals may be used for the same or similar elements.

Hereinafter, various embodiments of the disclosure are described with reference to the accompanying drawings. However, this is not intended to limit the invention as described in the disclosure to specific embodiments. It should be understood that the disclosure includes various modifications and/or alternatives of embodiments of the disclosure. In connection with the description of the drawings, like reference numerals may be used for like elements.

Referring to <FIG>, the electronic device <NUM> in the network environment <NUM> may communicate with an electronic device <NUM> via a first network <NUM> (e.g., a short-range wireless communication network), or at least one of an electronic device <NUM> or a server <NUM> via a second network <NUM> (e.g., a long-range wireless communication network). According to an embodiment, the electronic device <NUM> may include a processor <NUM>, memory <NUM>, an input module <NUM>, a sound output module <NUM>, a display module <NUM>, an audio module <NUM>, a sensor module <NUM>, an interface <NUM>, a connecting terminal <NUM>, a haptic module <NUM>, a camera module <NUM>, a power management module <NUM>, a battery <NUM>, a communication module <NUM>, a subscriber identification module (SIM) <NUM>, or an antenna module <NUM>. In some embodiments, at least one of the components (e.g., the connecting terminal <NUM>) may be omitted from the electronic device <NUM>, or one or more other components may be added in the electronic device <NUM>. In some embodiments, some of the components (e.g., the sensor module <NUM>, the camera module <NUM>, or the antenna module <NUM>) may be implemented as a single component (e.g., the display module <NUM>).

<FIG> shows an electronic device and an accessory device according to various embodiments.

Referring to <FIG>, an electronic device <NUM> (e.g., the electronic device <NUM> of <FIG>) may include a body (or a housing) <NUM> and a display <NUM>.

The display <NUM> and peripheral components (a camera, a physical button, and/or a sensor window) may be disposed in the body <NUM>. The body <NUM> may include components necessary for operating the electronic device <NUM>, such as a communication circuit, a processor, a memory, a printed circuit board, or a battery therein.

The display <NUM> may output image or text based content. For example, when a sound is output via an accessory device <NUM>, the display <NUM> may output a user interface (e.g., a user interface of a music playback app or a video playback app) related to the output sound.

In various embodiments, the body <NUM> may have a first connector (or a receptacle) <NUM> mounted therein which is connected to the accessory device <NUM> (e.g., an earphone) and transmits and receives a power signal or a data signal. In various embodiments, the power signal may mean electrical power. For example, the body <NUM> may receive therein the first connector <NUM> for transmitting and receiving the electrical power and/or the data signal used by the accessory device <NUM> (e.g., the earphone).

The first connector <NUM> may be connected to a second connector (or a plug) <NUM> of the accessory device <NUM>. The first connector <NUM> may include a plurality of pins for transmitting and receiving the power signal or the data signal. The plurality of pins included in the first connector <NUM> may contact pins included in the second connector <NUM> of the accessory device <NUM> to form a contact for transmitting and receiving the power signal or the data signal.

According to various embodiments, the first connector <NUM> may be a USB type-C connector specified in the USB standard. For example, the first connector <NUM> may be combined with the second connector <NUM> while a vertical insertion direction of the second connector <NUM> is not limited.

According to various embodiments, the first connector <NUM> may be a lightning connector or a thunderbolt connector. For example, the first connector <NUM> may supply power and/or signals to the second connector <NUM>.

According to various embodiments, the electronic device <NUM> may supply the power signal to the accessory device <NUM> using at least one of a power pin (e.g., a VBUS pin) or a recognition pin (e.g., a CC1 pin or a CC2 pin) included in the first connector <NUM>. The accessory device <NUM> may operate using the power signal provided via the power pin (e.g., a VBUS pin) or the recognition pin (e.g., a CC1 pin or a CC2 pin).

According to one embodiment, the electronic device <NUM> may transmit a first power signal via the power pin (e.g., a VBUS pin), and may supply a second power signal via the recognition pin (e.g., a CC1 pin or the CC2 pin). The first power signal may have a different voltage value (e.g., about 5V) from that (e.g., about <NUM>. 3V) of the second power signal.

According to one embodiment, when the second connector <NUM> of the accessory device <NUM> is connected to the first connector <NUM> of the electronic device <NUM>, the electronic device <NUM> may supply the first power signal and the second power signal to the accessory device <NUM> at the same time, and may cut off one power signal thereof according to a specified condition to reduce current consumption (or power consumption). For example, the specified condition may be a condition related to identification information of the accessory device <NUM> (see <FIG>).

According to an embodiment, the first connector <NUM> may include a first recognition pin (e.g., a CC1 pin) and a second recognition pin (e.g., a CC2 pin). One of the first recognition pin (e.g., a CC1 pin) and the second recognition pin (e.g., a CC2 pin) may be used to recognize the accessory device <NUM>, and the other thereof may be used to provide the second power signal (about <NUM>. 3V) to the accessory device <NUM>.

Hereinafter, a case in which the first recognition pin (e.g., a CC1 pin) is used to recognize the accessory device <NUM>, and the second recognition pin (e.g., a CC2 pin) is used to provide the second power signal to the accessory device <NUM> will be described. However, the disclosure is not limited thereto. For example, the second recognition pin (e.g., a CC2 pin) may be used to recognize the accessory device <NUM>, and the first recognition pin (e.g., a CC1 pin) may be used to provide the second power signal to the accessory device <NUM>.

Additional information related to transmission or cutting off of the first power signal and the second power signal may be described with reference to <FIG>.

The accessory device <NUM> may include a sound output device <NUM>, a user interface (or a control module) <NUM>, and the second connector (or the plug) <NUM>. The sound output device <NUM> may include a first speaker <NUM> and a second speaker <NUM>. The user interface (or control module) <NUM> may include buttons (e.g., a volume button, a call button) for user input, and may include a controller (e.g., a codec chip) therein. The second connector (or the plug) <NUM> may include a plurality of pins for transmitting and receiving the power signal or the data signal. The plurality of pins included in the second connector <NUM> may contact the pins included in the first connector <NUM> of the electronic device <NUM> to form a contact for transmitting and receiving the power signal or the data signal. Additional information about the second connector <NUM> may be provided with reference to <FIG>.

<FIG> is a block diagram of an electronic device according to various embodiments.

In <FIG>, components related to recognition or operation of the accessory device <NUM> are mainly shown. However, the disclosure is not limited thereto.

Referring to <FIG>, the first connector <NUM> may include a first sub-pin array 230a and a second sub-pin array 230b.

The first sub-pin array 230a may include a first power pin (e.g., a VBUS pin) (which may be a plurality of pins) 231a, a first data pin (e.g., a D+ pin, a D- pin) (which may be a plurality of pins) 232a, and a first recognition pin (e.g., a CC1 pin) 233a.

The second sub-pin array 230b may include a second power pin (e.g., a VBUS pin) (which may be a plurality of pins) 231b, a second data pin (e.g., a D+ pin, a D-pin) (which may be a plurality of pin) 232b, and a second recognition pin (e.g., a CC2 pin) 233b.

According to various embodiments, the electronic device <NUM> may include, as components for processing a signal transmitted and received via the first connector <NUM>, a processor <NUM> (e.g., the processor <NUM> of <FIG>), a device recognition circuit (or a connection configuration module) <NUM> (e.g., a power delivery integrated circuit (PDIC)), and a data processing circuit (a data module) <NUM>. The electronic device <NUM> may further include a power management module <NUM> (e.g., the power management module <NUM> in <FIG>) that supplies the first power signal or the second power signal via the first connector <NUM>.

According to various embodiments, the device recognition circuit <NUM> may be a device interface circuit. For example, the device recognition circuit <NUM> may be a USB interface circuit, a lightning interface circuit, or a thunderbolt interface circuit.

According to various embodiments, the processor <NUM> may execute computing or data processing related to control and/or communication of at least one further components of the electronic device <NUM>. The processor <NUM> may process a signal received via the data processing circuit <NUM>, and may control the device recognition circuit <NUM> or the power management module <NUM> in a specified communication scheme (e.g., i2c).

The device recognition circuit <NUM> (e.g., the power delivery integrated circuit (PDIC)) may recognize connection of an external device via a recognition pin (e.g., a configuration channel (CC) pin) 233a or 233b. According to one embodiment, the device recognition circuit <NUM> may be manufactured as a separate chip from the processor <NUM> or included in the processor <NUM>.

According to various embodiments, the device recognition circuit <NUM> may send a discovery identity message to an external electronic device via the recognition pin (e.g., the configuration channel (CC) pin) 233a or 233b of the first connector <NUM>. The device recognition circuit <NUM> may perform functions of device connection detection, identification of a cable type, interface configuration, and vendor defined messages.

According to various embodiments, the device recognition circuit <NUM> may perform power delivery (PD) communication with the accessory device <NUM> according to a protocol specified in the USB Type-C standard. For example, when the accessory device <NUM> includes the power delivery integrated circuit (PDIC), the device recognition circuit <NUM> may transmit and receive a power delivery (PD) message to and from the accessory device <NUM>. The PD message may be a communication protocol in a biphase marked code (BMC) scheme.

According to various embodiments, when the PD communication is available, the device recognition circuit <NUM> may receive identification information of the accessory device <NUM> via PD communication using the recognition pin (e.g., the CC (configuration channel) pin) 233a or 233b. For example, the device recognition circuit <NUM> may receive ID Header VDO via Power Delivery (PD) communication.

According to various embodiments, when the identification information of the accessory device <NUM> received via the PD communication is a specified value (e.g., VCONN-Powered USB Device (VPD)), the processor <NUM> or the device recognition circuit <NUM> may control the power management module <NUM> to block the first power signal and supply the second power signal to the accessory device <NUM> (see <FIG>).

The data processing circuit <NUM> may transmit data according to the type of the accessory device <NUM> connected to the first connector <NUM>. For example, the data processing circuit <NUM> may transmit data received from various communication circuits (e.g., a USB communication circuit, a UART communication circuit, an audio communication circuit, or a video communication circuit (e.g., HDMI, MHL)) inside the processor <NUM> according to the type of the accessory device <NUM> connected to the first connector <NUM> via the data pin 232a or 232b. According to one embodiment, the data processing circuit <NUM> may be manufactured as a separate chip from the processor <NUM> or included in the processor <NUM>.

According to various embodiments, the data processing circuit <NUM> may receive identification information of the accessory device <NUM> using USB enumeration. For example, the identification information of the accessory device <NUM> may include at least some of manufacturer identification information (Vendor ID (VID)), product identification information (Product ID (PID)), manufacturing information (Manufacture info), or product information (Product info).

According to various embodiments, when the identification information of the accessory device <NUM> received via the data pin 232a or 232b matches stored information, the processor <NUM> may control the power management module <NUM> to block the first power signal and supply the second power signal to the accessory device <NUM> (see <FIG>).

The power management module <NUM> may transmit the first power signal (e.g., about 5V) to at least one of the first power pin 231a or the second power pin 231b under control of the processor <NUM> or the device recognition circuit <NUM>. Further, the power management module <NUM> may transmit the second power signal (e.g., about <NUM>. 3V) to at least one of the first recognition pin 233a or the second recognition pin 233b under control of the processor <NUM> or the device recognition circuit <NUM>. The first power signal (e.g., about 5V) may be a signal obtained by boosting a power signal output via a terminal of the battery (e.g., the battery <NUM> of <FIG>) using a separate boosting circuit. The second power signal (e.g., about <NUM>. 3V) may be a power signal directly output via a terminal of the battery (e.g., the battery <NUM> in <FIG>) while not being subjected to the boosting using a separate boost circuit.

<FIG> shows a pin configuration of a first connector of an electronic device according to various embodiments.

Referring to <FIG>, the first connector <NUM> may include the first sub-pin array 230a and the second sub-pin array 230b implemented in a symmetrical arrangement and position with each other. For example, the first sub-pin array 230a may include first to twelfth pins (e.g., a power pin, a ground pin, a data pin (TX, RX, D), the CC1 pin) according to the USB standard. The second sub-pin array 230b may be symmetrical with the first sub-pin array 230a in terms of a position and an arrangement, and may include <NUM>-th to <NUM>-th pins (e.g., a power pin, a ground pin, a data pin (TX, RX, D), the CC2 pin) according to the USB standard.

When the second connector <NUM> of the accessory device <NUM> is connected to the first connector <NUM> of the electronic device <NUM>, the power pin 231a or 231b may transmit the first power signal to the accessory device <NUM>.

For example, when the first connector <NUM> is connected to the second connector <NUM> of the accessory device <NUM> such that a first resistor Rd (<NUM>) is connected to the first recognition pin (e.g., a CC1 pin) 233a, the first power signal (about 5V) may be supplied via the first power pin (e.g., a VBUS pin) 231a, and a separate power signal may not be supplied via the second power pin (e.g., a VBUS pin) 231b.

In another example, when the first connector <NUM> is connected to the second connector <NUM> of the accessory device <NUM> such that the first resistor Rd (<NUM>) is connected to the second recognition pin (e.g., a CC2 pin) 233b, the first power signal (about 5V) may be supplied via the second power pin (e.g., a VBUS pin) 231b, and a separate power signal may not be supplied via the first power pin (e.g., a VBUS pin) 231a.

The data pins (TX, RX, D) of the first sub-pin array 230a may include a D pin 232a, an RX pair pin 232a1, and a TX pair pin 232a2. The RX pair pin 232a1 may include an RX2- pin (A10 pin) and an RX2+ pin (A11 pin). The TX pair pin 232a2 may include a TX1+ pin (A2 pin) and a TX1- pin (A3 pin). The D pin 232a may include a D+ pin (A6 pin) and a D- pin (A7 pin). The RX pair pin 232a1 and the TX pair pin 232a2 may be data pins according to USB <NUM>, and the D pin 232a may be a data pin according to USB <NUM>.

The data pins (TX, RX, D) of the second sub-pin array 230b may include a D pin 232b, an RX pair pin 232b1, and a TX pair pin 232b2. The RX pair pin 232b1 may include an RX1- pin (B10 pin) and an RX1+ pin (B11 pin). The TX pair pin 232b2 may include a TX2+ pin (B2 pin) and a TX2- pin (B3 pin). The D pin 232b may include a D+ pin (B6 pin) and a D- pin (B7 pin). The RX pair pin 232b1 and the TX pair pin 232b2 may be data pins according to USB <NUM>, and the D pin 232b may be a data pin according to USB <NUM>.

According to various embodiments, the data pin 232a or 232b may receive the identification information of the accessory device <NUM> using USB enumeration. For example, the identification information may include at least some of manufacturer identification information (Vendor ID (VID)), product identification information (Product ID (PID)), manufacturing information (Manufacture info), or product information (Product info).

According to various embodiments, when the identification information of the accessory device <NUM> received via the data pin 232a or 232b matches the stored information, the electronic device <NUM> may be configured to cut off the supply of the first power signal to the accessory device <NUM> via the power pin 231a or 231b, and to maintain the supply of the second power signal to the accessory device <NUM> via the recognition pin (e.g., a CC1 or a CC2 pin) 233a or 233b.

For example, when recognizing the accessory device <NUM> via the first recognition pin (e.g., a CC1 pin) 233a (the resistor Rd is connected thereto), the electronic device <NUM> may supply the first power signal (e.g., about 5V) to the first power pin 231a, and may supply the second power signal (e.g., about <NUM>. 3V) to the second recognition pin (e.g., a CC2 pin) 233b. When the identification information of the accessory device <NUM> received via the first data pin 232a matches the stored information, the electronic device <NUM> may cut off the supply of the first power signal to the accessory device <NUM> via the first power pin 231a, and may maintain the supply of the second power signal to the accessory device <NUM> via the second recognition pin (e.g., a CC2 pin) 233b.

In another example, when recognizing the accessory device <NUM> via the second recognition pin (e.g., a CC2 pin) 233b (the resistor Rd is connected thereto), the electronic device <NUM> may supply the first power signal (e.g., about 5V) to the second power pin 231b, and may supply the second power signal (e.g., about <NUM>. 3V) to the first recognition pin (e.g., a CC1 pin) 233a. When the identification information of the accessory device <NUM> received via the second data pin 232b matches the stored information, the electronic device <NUM> may cut off the supply of the first power signal to the accessory device <NUM> via the second power pin 231b, and may maintain the supply of the second power signal to the accessory device <NUM> via the first recognition pin (e.g., a CC1 pin) 233a.

According to various embodiments, the data pin 232a or 232b may transmit a sound signal to the accessory device <NUM>. For example, the data pin 232a or 232b may transmit a sound signal of digital data using USB Audio Class (UAC).

The recognition pin (e.g., a CC1 or a CC2 pin) 233a or 233b may detect the connection of the accessory device <NUM> to the electronic device via the first connector <NUM>. The recognition pin <NUM> may be a configuration channel (CC) pin according to the USB Type-C™ standard.

For example, when the first resistor Rd (<NUM>) is connected to the first recognition pin (e.g., a CC1 pin) 233a and the second recognition pin (e.g., a CC2 pin) 233b is in an open state, the first power pin (e.g., a VBUS pin) 231a may supply the first power signal (e.g., about 5V). Further, simultaneously with the supply of the first power signal (or within a specified time), the second recognition pin (e.g., a CC2 pin) 233b may supply the second power signal (e.g., about <NUM>. Thereafter, one of the first power signal and the second power signal may be blocked based on the identification of the accessory device <NUM>.

In another example, when the first resistor Rd (<NUM>) is connected to the second recognition pin (e.g., a CC2 pin) 233b, and the first recognition pin (e.g., a CC1 pin) 233a is in an open state, the second power pin (e.g., a VBUS pin) 231b may supply the first power signal (e.g., about 5V). Further, simultaneously with the supply of the first power signal (or within a specified time), the first recognition pin (e.g., a CC1 pin) 233a may supply the second power signal (e.g., about <NUM>. Thereafter, one of the first power signal and the second power signal may be blocked based on the identification of the accessory device <NUM>.

According to various embodiments, the second power signal (e.g., VCONN, about <NUM>. 3V) supplied via the recognition pin (e.g., a CC1 or CC2 pin) 233a or 233b may be blocked when the number of times of no response to a Source Capability message is equal to or larger than a specified value (<NUM> or <NUM> times).

<FIG> is a configuration diagram of an accessory device according to various embodiments.

Referring to <FIG>, the accessory device <NUM> may include the second connector <NUM>, a first diode <NUM>, a second diode <NUM>, a first resistor <NUM>, a second resistor <NUM> and a controller (e.g., a codec chip) <NUM>.

The second connector <NUM> may include a first sub-pin array 250a and a second sub-pin array 250b. The first sub-pin array 250a may include a first power pin (e.g., a VBUS pin) (which may be a plurality of pins) 251a, a first data pin (e.g., a D+ pin, a D- pin) (which may be a plurality of pins) 252a, and a first recognition pin (e.g., a CC1 pin) 253a.

The second sub-pin array 250b may include a second recognition pin (e.g., a CC2 pin) 253b. The power pins or data pins of the second sub-pin array 250b may be provided and in an open state so as not to be substantially connected.

According to various embodiments, the first recognition pin (e.g., a CC1 pin) 253a may be connected to the first resistor (Rd, <NUM>) <NUM>. The recognition pin (e.g., the recognition pin 233a or 233b of <FIG>) of the first connector <NUM> may be connected to the first recognition pin (e.g., a CC1 pin) 253a of the second connector <NUM> so as to recognize the first resistor (Rd, <NUM>) <NUM>, the first power signal (e.g., about 5V) may be supplied via the first power pin (e.g., a VBUS pin) 251a, and the second power signal (e.g., about <NUM>. 3V) may be supplied via the second recognition pin (e.g., a CC2 pin) 253b. The first diode <NUM> may prevent reverse current of the first power signal, and the second diode <NUM> may prevent reverse current of the second power signal. The first power signal (e.g., about 5V) may be subjected to a voltage drop (e.g., a voltage drop from about 5V to about <NUM>. 3V) via the second resistor <NUM> and then may be supplied to the controller <NUM>.

When USB enumeration is in progress, the controller <NUM> may transmit the identification information of the accessory device <NUM> to the electronic device <NUM> via the first data pin (e.g., a D+ pin, a D- pin) 252a. For example, the identification information may include at least some of manufacturer identification information (Vendor ID (VID)), product identification information (Product ID (PID)), manufacturing information (Manufacture info), or product information (Product info).

When the identification information of the accessory device <NUM> matches the information stored inside the electronic device <NUM>, the supply of the first power signal (e.g., about 5V) via the first power pin (e.g., a VBUS pin) 251a may be blocked, and the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin (e.g., a CC2 pin) 253b may be maintained continuously.

When the identification information of the accessory device <NUM> does not match the information stored inside the electronic device <NUM>, the supply of the first power signal (e.g., about 5V) via the first power pin (e.g., a VBUS pin) 251a may be continuously maintained, and the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin (e.g., a CC2 pin) 253b may be blocked.

According to various embodiments, the accessory device <NUM> may further include a PDIC (not shown) connected to the first recognition pin (e.g., a CC1 pin) 253a. The PDIC may transmit and receive a PD (power delivery) message to and from the device recognition circuit <NUM> of the electronic device <NUM>. The PD message may be a communication protocol in a biphase marked code (BMC) manner.

According to various embodiments, the PDIC may transmit the identification information of the accessory device <NUM> to the electronic device <NUM> via the first recognition pin (e.g., a CC1 pin) 253a. For example, the PDIC may transmit ID Header VDO.

When the identification information of the accessory device <NUM> is a specified value (e.g., VCONN-Powered USB Device (VPD)), the supply of the first power signal (e.g., about 5V) via the first power pin (e.g., a VBUS pin) 251a may be blocked, and the second power signal (e.g., about <NUM>. 3V) may be supplied to the controller <NUM> via the second recognition pin (e.g., a CC2 pin) 253b.

The controller (e.g., a codec chip) <NUM> may transmit the identification information of the accessory device <NUM> in USB enumeration. Further, the controller (e.g., a codec chip) <NUM> may receive a sound signal and output the same via the sound output device <NUM>. The controller (e.g., a codec chip) <NUM> may be mounted inside the user interface <NUM>.

<FIG> is a flow chart of a power supply method using a data pin according to various embodiments.

Referring to <FIG>, in operation <NUM>, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may detect the connection of the accessory device <NUM> to the electronic device via the recognition pin (e.g., a CC (configuration channel) pin) 233a or 233b. The processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may identify whether the first resistor Rd (<NUM>) is connected to the first recognition pin 233a or the second recognition pin 233b. Hereinafter, a case in which the first resistor is connected to the first recognition pin 233a will be mainly discussed. However, the disclosure is not limited thereto.

In operation <NUM>, when the first resistor Rd (<NUM>) is connected to the first recognition pin 233a, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the first power signal (e.g., about 5V) via the first power pin 231a included in the first sub-pin array 230a including the first recognition pin 233a. For example, the first power signal (e.g., about 5V) may be a signal obtained by boosting a signal supplied from a battery using a boost circuit. Further, simultaneously with the supply of the first power signal (or within a specified time), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the second power signal (e.g., about <NUM>. 3V) having a voltage lower than that of the first power signal via the second recognition pin 233b. The second power signal (e.g., about <NUM>. 3V) may be a signal provided directly from the battery of the electronic device <NUM> while not being subjected to the voltage boosting using a separate boost circuit.

In operation <NUM>, the processor <NUM> may perform USB enumeration via the first data pin (e.g., a D+ pin, a D- pin) 232a of the first sub-pin array 230a including the first recognition pin 233a. USB enumeration may refer to a process of detecting, identifying and loading a driver for a USB device (see <FIG>).

In operation <NUM>, the processor <NUM> may receive first identification information of the accessory device <NUM> based on the USB enumeration. For example, the first identification information of the accessory device <NUM> may include at least some of manufacturer identification information (Vendor ID (VID)), product identification information (Product ID (PID)), manufacturing information (Manufacture info), or product information (Product info). The processor <NUM> may receive the first identification information via the first data pin (e.g., a D+ pin, a D- pin) 232a.

According to various embodiments, the accessory device <NUM> may be configured not to include a PDIC for PD communication. In this case, the processor <NUM> may not be able to receive the identification information of the accessory device <NUM> via the recognition pins 233a and 233b, and may receive the first identification information of the accessory device <NUM> based on the USB enumeration using the data pin (e.g., a D+ pin, a D- pin) 232a or 232b.

In operation <NUM>, the processor <NUM> may identify whether the first identification information matches second identification information stored inside the electronic device <NUM>. For example, the processor <NUM> may identify whether the accessory device <NUM> is manufactured by the same manufacturer as the manufacturer of the electronic device <NUM>. In another example, the process <NUM> may identify whether the accessory device <NUM> is manufactured by a company pre-agreed with the manufacturer of the electronic device <NUM>.

In operation <NUM>, when the first identification information and the second identification information match each other, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to cut off the supply the first power signal (e.g., about 5V) via the first power pin 231a, and to maintain the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b. Thus, current consumed due to the connection of the accessory device <NUM> to the electronic device may be reduced.

According to various embodiments, when the first identification information and the second identification information match each other, the processor <NUM> may identify whether the accessory device <NUM> is connected to the electronic device via a hub device. When the accessory device <NUM> is connected to the electronic device via the hub device, the processor <NUM> may control the power management module <NUM> to maintain the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to cut off the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b. Thus, a power supply state to an external device connected to the electronic device via the hub device may be maintained at the first power signal (e.g., about 5V).

In operation <NUM>, when the first identification information and the second identification information do not match each other, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to maintain the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to cut off the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b.

<FIG> shows USB enumeration in an accessory device according to various embodiments.

Referring to <FIG>, in an unattached state <NUM>, the second connector <NUM> of the accessory device <NUM> may not be connected to the first connector <NUM> of the electronic device <NUM>. The accessory device <NUM> (or the controller <NUM> of the accessory device <NUM>) may identify whether the first power signal (e.g., VBUS) is supplied to the first power pin 251a. When the first power signal is supplied to the first power pin 251a, the accessory device <NUM> may be brought into an attached state <NUM>.

In the attached state <NUM>, the accessory device <NUM> may identify whether the first power signal (e.g., VBUS) is greater than or equal to a specified voltage value (e.g., 5V). When the first power signal is greater than or equal to a specified voltage value (e.g., 5V), the accessory device <NUM> may be brought into a power supply state <NUM>.

In the power supply state <NUM>, the accessory device <NUM> may transmit a signal indicating availability of the first data pin 252a to the electronic device <NUM> as a host device (685a). The accessory device <NUM> may receive a reset command from the electronic device <NUM> as the host device via the first data pin 252a (685b). The accessory device <NUM> may perform a device reset in response to the reset command. When the device reset is completed, the accessory device <NUM> may be brought into a default state <NUM>.

In the default state <NUM>, the accessory device <NUM> may transmit a device descriptor to the electronic device <NUM> as the host device (691a). According to various embodiments, the device descriptor may include the identification information of the accessory device <NUM>. For example, the identification information of the accessory device <NUM> may include at least some of manufacturer identification information (Vendor ID (VID)), product identification information (Product ID (PID)), manufacturing information (Manufacture info), or product information (Product info). The accessory device <NUM> may receive an address command from the electronic device <NUM> as the host device (691b) and may be brought into an addressed step <NUM>.

According to various embodiments, when the identification information of the accessory device <NUM> matches the identification information stored inside the electronic device <NUM>, the electronic device <NUM> may cut off the supply of the first power signal (e.g., about 5V) via the first power pin 231a of the first connector <NUM>, and may maintain the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b of the first connector <NUM>. Thus, current consumed due to the connection of the accessory device <NUM> to the electronic device may be reduced.

In the addressed state <NUM>, the accessory device <NUM> may transmit an additional device descriptor to the electronic device <NUM> as the host device (693a). The accessory device <NUM> may receive a configuration command (693b) and may be brought into a configured state <NUM>.

In the configured state <NUM>, the accessory device <NUM> may output a sound signal transmitted from the electronic device <NUM> as the host device as a sound through a speaker.

<FIG> is a flowchart of a power supply method using PD communication according to various embodiments.

Referring to <FIG>, in operation <NUM>, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may detect the connection of the accessory device <NUM> to the electronic device via the recognition pin (e.g., a configuration channel (CC) pin) 233a or 233b. The processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may identify whether the first resistor Rd (<NUM>) is connected to the first recognition pin 233a or the second recognition pin 233b. Hereinafter, a case in which the first resistor is connected to the first recognition pin 233a will be mainly discussed. However, the disclosure is not limited thereto. Further, at least some of operations of the processor <NUM> may be performed by the device recognition circuit (e.g., PDIC) <NUM>.

In operation <NUM>, when the first resistor Rd (<NUM>) is connected to the first recognition pin (233a), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the first power signal (e.g., about 5V) via the first power pin 231a included in the first sub-pin array 230a including the first recognition pin 233a. For example, the first power signal (e.g., about 5V) may be a signal obtained by boosting a signal supplied from a battery using a boost circuit. Further, simultaneously with the supply of the first power signal (or within a specified time), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the second power signal (e.g., about <NUM>. 3V) having a lower voltage than that of the first power signal via the second recognition pin 233b. The second power signal (e.g., about <NUM>. 3V) may be a signal provided directly from the battery of the electronic device <NUM> while not being subjected to a voltage boosting using a separate boost circuit.

In operation <NUM>, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may identify whether PD communication using the first recognition pin 233a of the first connector <NUM> is available. When the accessory device <NUM> includes a PDIC connected to the first recognition pin (e.g., a CC1 pin) 253a of the second connector <NUM>, the PD communication may be available. The power delivery (PD) message may be a communication protocol in the biphase marked code (BMC) manner.

In operation <NUM>, when PD communication is available, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may receive the first identification information of the accessory device <NUM> via the first recognition pin 233a of the first connector <NUM>. For example, the first identification information may be an ID Header VDO (Vendor Define Object).

In operation <NUM>, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may identify whether the first identification information is a specified value. For example, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may identify whether a Vendor Define Object (VDO) is a VCONN-Powered USB Device (VPD).

In operation <NUM>, when the first identification information is the specified value, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to cut off the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to maintain the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b. Thus, current consumed due to the connection of the accessory device <NUM> to the electronic device may be reduced.

In operation <NUM>, when the PD communication is not available or when the first identification information is not the specified value, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to maintain the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to cut off the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b.

According to various embodiments, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may receive the manufacturer identification information (Vendor ID (VID)) or product identification information (Product ID (PID)) of the accessory device <NUM> via the first recognition pin 233a of the first connector <NUM>. In this case, before the USB enumeration is performed, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may cut off the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and may maintain the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b.

<FIG> is a flowchart of a power supply method using audio headset information according to various embodiments.

In operation <NUM>, when the first resistor Rd (<NUM>) is connected to the first recognition pin (233a), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the first power signal (e.g., about 5V) via the first power pin 231a included in the first sub-pin array 230a including the first recognition pin 233a. For example, the first power signal (e.g., about 5V) may be a signal obtained by boosting a signal supplied from a battery via a boost circuit. Further, simultaneously with the supply of the first power signal (or within a specified time), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to supply the second power signal (e.g., about <NUM>. 3V) having a lower voltage than that of the first power signal via the second recognition pin 233b. The second power signal (e.g., about <NUM>. 3V) may be a signal provided directly from the battery of the electronic device <NUM> while not being subjected to a voltage boosting using a separate boost circuit.

In operation <NUM>, the processor <NUM> may perform USB enumeration via the first data pin (e.g., a D+ pin, a D- pin) 232a of the first sub-pin array 230a including the first recognition pin 233a. USB enumeration may refer to a process of detecting, identifying and loading a driver for a USB device.

In operation <NUM>, when the accessory device <NUM> is an audio class device, the processor <NUM> may receive audio headset information of the accessory device <NUM> based on the USB enumeration. For example, the audio headset information may be an Audio Control Interface Descriptor.

In operation <NUM>, the processor <NUM> may identify whether the audio headset information is a specified value. For example, it may be identified whether the Audio Function Category Codes included in the bCategory Field of the Audio Control Interface Descriptor is HEADSET.

In operation <NUM>, when the audio headset information is the specified value, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to cut off the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to maintain the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b. Thus, current consumed due to the connection of the accessory device <NUM> to the electronic device may be reduced.

According to various embodiments, when the audio headset information is the specified value, the processor <NUM> may identify whether the accessory device <NUM> is connected to the electronic device via a hub device. When the accessory device <NUM> is connected thereto via the hub device, the processor <NUM> may control the power management module <NUM> to maintain the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to cut off the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b. Thus, a power supply state to an external device connected to the electronic device via the hub device may be maintained at the first power signal (e.g., about 5V).

In operation <NUM>, when the audio headset information is not the specified value, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may control the power management module <NUM> to maintain the supply of the first power signal (e.g., about 5V) via the first power pin 231a, and to cut off the supply of the second power signal (e.g., about <NUM>. 3V) via the second recognition pin 233b.

<FIG> is a graph of change in a first power signal or a second power signal according to various embodiments.

Referring to <FIG>, when the second connector <NUM> of the accessory device <NUM> is not connected to the first connector <NUM>, both the first power signal (VBUS) and the second power signal (VCNN) may be in a L state (e.g., about 0V) (before t1).

At time t1 when the first resistor Rd (<NUM>) is connected to the first recognition pin 233a, the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may change the first power signal (VBUS) supplied via the first power pin 231a included in the first sub-pin array 230a including the first recognition pin 233a to a H1 state (e.g., about 5V), and may change the second power signal (VCONN) supplied via the second recognition pin 233b to a H2 state (e.g., about <NUM>.

In a first graph <NUM>, when the identification information of the accessory device <NUM> is a specified value or matches the information stored in the electronic device <NUM> (time t2), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may change a state of the first power signal (VBUS) from the H1 state (e.g., about 5V) to the L state (e.g., about 0V), and may maintain a state of the second power signal (VCONN) at the H2 state (e.g., about <NUM>.

In a second graph <NUM>, when the identification information of the accessory device <NUM> is not the specified value or does not match the information stored in the electronic device <NUM> (time t3), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may maintain a state of the first power signal (VBUS) at the H1 state (e.g., about 5V), and may change a state of the second power signal (VCONN) from the H2 state (e.g., about <NUM>. 3V) to the L state (e.g., about 0V).

According to one embodiment, when the number of times of no response to a Source Capability message is equal to or larger than a specified value (e.g., <NUM> times), the processor <NUM> or the device recognition circuit (e.g., PDIC) <NUM> may change a stage of the second power signal (VCONN) from the H2 state (e.g., about <NUM>. 3V) to the L state (e.g., about 0V).

An electronic device (e.g., the electronic device <NUM> of <FIG>, the electronic device <NUM> of <FIG>) according to various embodiments may include a housing, a battery disposed inside the housing, a power management module (e.g., the power management module <NUM> in <FIG>, the power management module <NUM> in <FIG>) for controlling supply of power from the battery, a connector (e.g., the first connector <NUM> in <FIG>) disposed inside the housing, a device recognition circuit (e.g., the device recognition circuit <NUM> in <FIG>) for detecting a connected state of the connector (e.g., the first connector <NUM> in <FIG>), a memory, and a processor electrically connected to the memory, the power management module (e.g., the power management module <NUM> in <FIG>, the power management module <NUM> in <FIG>) or the device recognition circuit (e.g., the device recognition circuit <NUM> in <FIG>), wherein the connector (e.g., the first connector <NUM> in <FIG>) includes a first sub-pin array and a second sub-pin array arranged symmetrically with the first sub-pin array, wherein the first sub-pin array includes a first power pin, a first data pin, and a first recognition pin, wherein the second sub-pin array includes a second power pin, a second data pin, and a second recognition pin, wherein the first recognition pin and the second recognition pin are connected to the device recognition circuit (e.g., the device recognition circuit <NUM> in <FIG>), wherein the processor or the device recognition circuit (e.g., the device recognition circuit <NUM> of <FIG>) is configured to, when an external accessory device is connected to the connector (e.g., the first connector <NUM> of <FIG>) and a specified resistance value is detected in the first recognition pin, control the power management module to supply a first power signal to the first power pin and a second power signal to the second recognition pin, receive first identification information of the accessory device via the first recognition pin or the first data pin, and when the first identification information is a specified value or matches second identification information stored in the memory, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal.

According to various embodiments, the processor may be configured to perform USB enumeration using the first data pin to receive the first identification information.

According to various embodiments, the first identification information may include manufacturer information or product information of the accessory device.

According to various embodiments, the memory may store therein a list of the second identification information.

According to various embodiments, the processor may be configured to receive the first identification information using the first data pin in a default state of the USB enumeration.

According to various embodiments, the processor may be configured to receive audio headset information using the first data pin.

According to various embodiments, the processor may be configured to, when the audio headset information may be a specified code, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal.

According to various embodiments, the processor may be configured to, when the accessory device may be recognized as being connected to the connector (e.g., the first connector <NUM> of <FIG>) via a separate hub device, control the power management module to maintain the supply of the first power signal and cut off the supply of the second power signal.

According to various embodiments, the processor may be configured to transmit a sound signal to the accessory device via the first data pin.

According to various embodiments, the device recognition circuit (e.g., the device recognition circuit <NUM> of <FIG>) may be configured to receive the first identification information via the first recognition pin, and based on a message by power delivery (PD) communication.

According to various embodiments, the specified value may be a code set in a device operable based on the second power signal.

According to various embodiments, the first power signal may have a higher voltage value than a voltage value of the second power signal.

According to various embodiments, the connector may be a receptacle (e.g., the first connector <NUM> of <FIG>) for a USB Type-C.

An accessory device (e.g., the accessory device <NUM> in <FIG>) according to various embodiments may be wiredly connected to an external device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>) and may include a controller (e.g. the controller <NUM> in <FIG>), and a connector (e.g., the second connector <NUM> in <FIG>) connected to the external device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), wherein the connector (e.g., the second connector <NUM> in <FIG>) includes a first sub-pin array and a second sub-pin array arranged symmetrically with the first sub-pin array, wherein the first sub-pin array includes a first power pin, a first data pin, and a first recognition pin, wherein the first recognition pin is connected to a first resistor, wherein the second sub-pin array includes a second recognition pin, wherein the controller (e.g., the controller <NUM> of <FIG>) may receive a first power signal via the first power pin or may receive a second power signal via the second recognition pin.

According to various embodiments, the controller (e.g., the controller <NUM> of <FIG>) may transmit manufacturer information or product information of the accessory device via the first data pin.

According to various embodiments, the first power signal may be subjected to voltage-drop due to a second resistor and then may be supplied to the controller (e.g., the controller <NUM> of <FIG>).

A method for supplying power to an accessory device (e.g., the accessory device <NUM> of <FIG>) according to various embodiments may be performed by an electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), and may include detecting a specified resistance value of the accessory device (e.g., the accessory device <NUM> in <FIG>) connected to the electronic device via a first recognition pin of a first sub-pin array of a connector (e.g., the first connector <NUM> in <FIG>) of the electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), supplying a first power signal to a first power pin of the first sub-pin array and supplying a second power signal to a second recognition pin of a second sub-pin array of the connector (e.g., the first connector <NUM> in <FIG>), receiving first identification information of the accessory device (e.g., the accessory device <NUM> in <FIG>) via a first data pin of the first sub-pin array, determining whether the first identification information matches second identification information stored in a memory of the electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), and upon determination that the first identification information and the second identification information match each other, cutting off the supply of the first power signal and maintaining the supply of the second power signal.

According to various embodiments, the receiving of the first identification information may include performing USB enumeration.

A method for supplying power to an accessory device (e.g., the accessory device <NUM> of <FIG>) according to various embodiments may be performed in an electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), and may include detecting a specified resistance value of the accessory device (e.g., the accessory device <NUM> in <FIG>) connected to the electronic device via a first recognition pin of a first sub-pin array of a connector (e.g., the first connector <NUM> in <FIG>) of the electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), supplying a first power signal to a first power pin of the first sub-pin array and supplying a second power signal to a second recognition pin of a second sub-pin array of the connector (e.g., the first connector <NUM> in <FIG>), receiving first identification information of the accessory device (e.g., the accessory device <NUM> in <FIG>) via the first recognition pin, and when the first identification information is a specified value, cutting off the supply of the first power signal and maintaining the supply of the second power signal.

A method for supplying power to an accessory device (e.g., the accessory device <NUM> of <FIG>) according to various embodiments may be performed in an electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), and may include detecting a specified resistance value of the accessory device (e.g., the accessory device <NUM> in <FIG>) connected to the electronic device via a first recognition pin of a first sub-pin array of a connector (e.g., the first connector <NUM> in <FIG>) of the electronic device (e.g., the electronic device <NUM> in <FIG>, the electronic device <NUM> in <FIG>), supplying a first power signal to a first power pin of the first sub-pin array and supplying a second power signal to a second recognition pin of a second sub-pin array of the connector (e.g., the first connector <NUM> in <FIG>), receiving audio headset information of the accessory device (e.g., the accessory device <NUM> in <FIG>) via a first data pin of the first sub-pin array, and when the audio headset information is a specified value, cutting off the supply of the first power signal and maintaining the supply of the second power signal.

It should be appreciated that various embodiments of the present disclosure and the terms used therein are not intended to limit the technological features set forth herein to particular embodiments and include various changes, or replacements for a corresponding embodiment.

Claim 1:
An electronic device (<NUM>) comprising:
a battery (<NUM>);
a power management module (<NUM>) configured to control a power supplied from the battery (<NUM>) of a first power signal and of a second power signal;
a connector (<NUM>) comprising a first sub-pin array (230a) and a second sub-pin array (230b);
a device recognition circuit (<NUM>) configured to detect whether an external device is connected to the connector; and
a processor (<NUM>);
wherein the first sub-pin array (230a) comprises a first power pin (231a), a first data pin (232a), and a first recognition pin (233a),
wherein the second sub-pin array (230b) comprises a second power pin (231b), a second data pin (232b), and a second recognition pin (233b);
wherein the first recognition pin (233a) and the second recognition pin (233b) are connected to the device recognition circuit (<NUM>);
wherein the processor (<NUM>) is configured to:
based on a first resistance value detected in the first recognition pin (233a),control the power management module (<NUM>) to supply the first power signal to the first power pin (231a) and to supply the second power signal to the second recognition pin (233b),
receive first identification information of the external device via the first recognition pin or the first data pin (232a), and
based on the first identification information, control the power management module to cut off the supply of the first power signal and to maintain the supply of the second power signal,
wherein a first voltage value of the first power signal is higher than a second voltage value of the second power signal, and
wherein the first power signal is a signal obtained by boosting a power signal output via a terminal of the battery, and the second power signal is a power signal directly output via the terminal of the battery.