Patent Description:
The following description relates to processing of integrated circuits ("ICs"). More particularly, the following description relates to devices and techniques for processing IC dies and assemblies.

The demand for more compact physical arrangements of microelectronic elements such as integrated chips and dies has become even more intense with the rapid progress of portable electronic devices, the expansion of the Internet of Things, nano-scale integration, subwavelength optical integration, and more. Merely by way of example, devices commonly referred to as "smart phones" integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, a variety of sensors, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips and dies into a small space.

Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide. Chips and dies are commonly provided as individual, prepackaged units. In some unit designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB). Dies can be provided in packages that facilitate handling of the die during manufacture and during mounting of the die on the external substrate. For example, many dies are provided in packages suitable for surface mounting.

Numerous packages of this general type have been proposed for various applications. Most commonly, such packages include a dielectric element, commonly referred to as a "chip carrier" with terminals formed as plated or etched metallic structures on the dielectric. The terminals typically are connected to the contacts (e.g., bond pads) of the die by conductive features such as thin traces extending along the die carrier and by fine leads or wires extending between the contacts of the die and the terminals or traces. In a surface mounting operation, the package may be placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is generally provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or "reflow" the solder or otherwise activate the bonding material.

Many packages include solder masses in the form of solder balls that are typically between about <NUM> and about <NUM> (<NUM> and <NUM> mils) in diameter, and are attached to the terminals of the package. A package having an array of solder balls projecting from its bottom surface (e.g., surface opposite the front face of the die) is commonly referred to as a ball grid array or "BGA" package. Other packages, referred to as land grid array or "LGA" packages are secured to the substrate by thin layers or lands formed from solder. Packages of this type can be quite compact. Certain packages, commonly referred to as "chip scale packages," occupy an area of the circuit board equal to, or only slightly larger than, the area of the device incorporated in the package. This scale is advantageous in that it reduces the overall size of the assembly and permits the use of short interconnections between various devices on the substrate, which in turn limits signal propagation time between devices and thus facilitates operation of the assembly at high speeds.

Semiconductor dies can also be provided in "stacked" arrangements, wherein one die is provided on a carrier, for example, and another die is mounted on top of the first die. These arrangements can allow a number of different dies to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the dies. Often, this interconnect distance can be only slightly longer than the thickness of the die itself. For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., surfaces) of each die package (except, perhaps, for the topmost package). This has been done, for example, by providing contact pads or lands on both sides of the substrate to which the die is mounted, the pads being connected through the substrate by conductive vias or the like. Examples of stacked chip arrangements and interconnect structures are provided in <CIT>. In other examples, Through Silicon Vias (TSVs) are used for interconnection to be achieved within a stack of die packages. In some cases, dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques, such as ZiBond® or a hybrid bonding technique, such as DBI®, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc. ), an Xperi company (see for example, <CIT> and <CIT>).

Stacked die and wafer arrangements, including bonded arrangements, may also be used to form assembled components such as microelectromechanical systems (MEMS), sensors, and the like. See, for example, <CIT>. In many of these arrangements, it is desirable for the stacked dies and wafers to be sealed at their joined surfaces, for instance, to form a sensor cavity. In some cases, making such seals reliable and long-lasting can be problematic, particularly at the chip scale. <CIT> discloses a package comprising an enclosure on a substrate wafer with bondpads on the outside of said enclosure, wherein the top of said enclosure comprises a cap wafer, the sidewall of said enclosure is covered by a diffusion barrier, and said bondpads and edges of said substrate are not covered by said diffusion barrier.

For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternately, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure.

Various embodiments of techniques and devices for forming seals and sealed microelectronic devices are disclosed. Seals are disposed at joined (e.g., bonded, coupled, etc.) surfaces of stacked dies and wafers to seal (e.g., hermetically seal) the joined surfaces. The joined surfaces may be sealed to form sensor cavities, or the like, as part of the microelectronic devices. For instance, when a die with a recessed surface is bonded to another die with a flat surface or a recessed surface, a cavity can be formed between the two dies. In some applications, it may be desirable for this cavity to be hermetically sealed, to maintain a specific vacuum level inside the cavity and for predetermined leak rates to be maintained.

The leak rate of a sealed cavity can be looked at as a function of the cavity's volume. For example, if the volume of a cavity is less than or equal to <NUM><NUM>, generally, the leak rate is to be below 5E-<NUM> atm-cc/s (<NUM> * <NUM>-<NUM> Pa m<NUM> s-<NUM>) of air to consider the cavity hermetically sealed. If the volume of the cavity ranges between <NUM> and <NUM><NUM>, the leak rate is to be below 1E-<NUM>, and if the volume is greater than <NUM><NUM>, then the leak rate is to be below 1E-<NUM> for a hermetically sealed cavity (per MIL-STD-<NUM> Method <NUM>, MIL-STD-<NUM> Method <NUM>).

The integrity of a seal at the periphery of a stack of dies can be critical to maintain the application specific hermeticity and low leak rates of the package. Metals, ceramics, and glasses are the typical materials used to form the seal and to prevent water vapor or other gases (e.g. oxygen, etc.) from accessing components inside the package. A properly made hermetic seal with a sufficiently low leak rate can keep the interior of a package dry and moisture free for many years.

The techniques disclosed herein include forming seals of one or more metallic materials (for example) at a joint (e.g., a bond line, a seam, etc.) of at least two surfaces, which seals the joined surfaces at the joint. In various implementations, metallic materials may be deposited using electroless plating, or the like. In some embodiments, metallic materials may be deposited directly onto the joined surfaces at or around the joint. In other embodiments, one or more non-metallic materials may be deposited onto the joined surfaces, and metallic material can be deposited over the non-metallic material(s), sealing the j oint. The seal may include a continuous sealing ring formed completely around joined dies or wafers (e.g., a periphery of the devices) or one or more partial seals, as desired. However, according to the claimed invention the seal always comprises a channel extending continuously around an interior region of the bonded structure.

In various embodiments, the techniques disclosed can seal dies and wafers that are stacked and bonded using "ZIBOND®" techniques, which can benefit from the added seal. For example, at <FIG>, a cavity wafer <NUM> is bonded to a microelectromechanical system (MEMS) wafer <NUM> (or any other wafer) using a ZIBOND® technique, for example, to form a microelectronic device <NUM> such as a MEMS sensor device. A cavity wafer <NUM> (or a die) may have <NUM> or more cavities or recesses of the same or varying size. Especially-flat surfaces of the two wafers (<NUM> and <NUM>) are bonded together using a low temperature covalent bond between the two corresponding semiconductor and/or insulator layers. While the bond may be good, the seal may not be adequate as a hermetic seal, and the leak rates may not be as low as desired for the application. Further, the bond line width (P1) may not be optimal, since a relatively long bond line can unnecessarily increase the die size and can reduce the number of dies fabricated per wafer.

In another example, as shown at <FIG>, the seal may be improved by forming one or more metal-to-metal interconnections along the bonding seam using a Direct Bond Interconnect (DBI®) technique. Metallic lines <NUM> are deposited along each of the surfaces to be joined, so as to be aligned to each other, and form metal-to-metal bonds when set together using temperature and/or pressure. In some cases, the DBI lines <NUM> can help to reduce the bond line width (P2) while improving the hermeticity of the joint. However, the bond line width (P1) needed for utilizing a ZiBond method may not be adequate for the application (e.g., a <NUM> micron bond line width using Zibond may be reduced to tens of microns or less than <NUM> microns, using DBI for example). Further, such DBI bonds are not easy to achieve, potentially adding to the complexity and cost of the assembly.

<FIG> is a graphical flow diagram illustrating an example processing sequence <NUM> to form a stacked microelectronic device <NUM>. The process <NUM> and the stacked microelectronic device <NUM> form a background for discussing various sealing techniques and devices. In various embodiments, the process <NUM> described with reference to <FIG> may be modified to include the techniques and devices for hermetically sealing bonded components at the bond joints. <FIG> describes the process for a <NUM> die stack creating a hermetically sealed cavity <NUM> between top (and middle) and (middle and) bottom die. But a stack could also include only <NUM> dies with a cavity <NUM> between them, as depicted in <FIG>.

At block <NUM>, a recessed cavity wafer <NUM> is formed. Although one cavity <NUM> is shown in the illustration at block <NUM>, one or more cavities <NUM> of similar or different dimensions may be formed per die location, effectively forming several such recessed cavities <NUM> on a wafer (or die) <NUM>. At block <NUM>, the cavity wafer <NUM> is bonded to a MEMS wafer <NUM> (or any other wafer or die) closing the cavity <NUM> within. The cavity wafer <NUM> can be bonded to the MEMS wafer <NUM> using an intimate surface bonding technique, for example, a ZIBOND® technique, wherein insulating surfaces (e.g., SiOx - SiOx, etc.) are bonded. At block <NUM>, the MEMS wafer <NUM> may be thinned and patterned to form stand-offs. At block <NUM>, metallization <NUM> can be added to the patterned surface of the MEMS wafer <NUM>, including pads, contacts, traces, and so forth. In an alternate example, no metallization <NUM> is added to the surface of the MEMS wafer <NUM>. In the example, the microelectronic device <NUM> can be attached to another device, such as a logic device wafer, for example, using a Zibond technique (e.g., SiOx - SiOx bond) or the like at the bonded surfaces, or using other bonding techniques for dielectrics (such as a polymeric material, e.g. die attached film or paste) on one or both bonded surfaces.

At block <NUM>, openings are formed in the MEMS wafer <NUM>, accessing the cavity <NUM>, to define the characteristics of the microelectronic device <NUM>, based on the application. At block <NUM>, the microelectronic device <NUM> can be attached to a logic device wafer (or die) <NUM>, to provide logic/control (for example) for the microelectronic device <NUM>. Metallization layer <NUM> contact pads of the microelectronic device <NUM> are coupled to contacts <NUM> on the surface of the logic device <NUM>. At block <NUM>, portions of the microelectronic device <NUM> (such as portions of the cavity wafer <NUM>) are removed (e.g., etched, etc.) to provide access to other contact pads of the logic device wafer <NUM>, and so forth. In some instances, the Zibond or DBI interface between the cavity wafer <NUM> and the MEMS wafer <NUM> may provide an adequate resistance to the flow of fluids, such as gases and/or liquids. In other embodiments, one or more of the bond lines or coupling joints of the microelectronic device <NUM> can be sealed for hermeticity (e.g., a predetermined resistance to the flow of fluids, such as gases and/or liquids, and sufficiently low moisture vapor transmission rate, oxygen transmission rate, etc.), as discussed below.

To ensure a strong and hermetically sealed bond, the techniques disclosed herein include bonding insulator surfaces of the wafers (e.g., <NUM> and <NUM>), then adding a metallic seal at the bond line to improve the hermeticity, as discussed further below.

<FIG> shows example embodiments of sealing a microelectronic device <NUM>, such as the microelectronic device <NUM> formed with reference to <FIG>. As shown by the side view of the microelectronic device <NUM> at <FIG> and the top view at <FIG>, a metallic seal ring <NUM> can be formed surrounding the bonded joint of the cavity wafer <NUM> and the MEMS wafer <NUM>, and can also be extended to seal the logic device <NUM> to the MEMS wafer <NUM>. The seal ring <NUM> creates a hermetic seal around a periphery of the microelectronic components (e.g., <NUM>, <NUM>, and <NUM>), fully sealing the joints between the components. The seal ring <NUM> can be located to seal any or all of the joints between the microelectronic components (e.g., <NUM>, <NUM>, and <NUM>), as desired.

In various embodiments, the seal ring <NUM> is comprised of a metallic material (i.e., a metal such as copper, for example, an alloy, or a metallic composition). In some embodiments, two or more metallic materials may be used in layers (or other combinations) to form the seal ring <NUM>. In the various embodiments, the seal ring <NUM> is deposited using electroless plating, electrodeposition, mechanical printing, or various combinations thereof, or the like.

As shown at <FIG>, multiple seal rings <NUM> may be used to seal between multiple components (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) at different stacking levels in a stacked microelectronic arrangement <NUM>. Seal rings <NUM> may be used at any or all of the levels of the stacked arrangement <NUM>, as desired. While complete seal rings <NUM> are discussed and illustrated, partial seal rings <NUM> may also be used where desired to form seals at bond joints or between components (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) of a microelectronic device (e.g., <NUM>, <NUM>) or assembly.

<FIG> shows an example sealed microelectronic device <NUM>, according to another embodiment, using interior seals (e.g., <NUM> and <NUM>). Alternately or in addition to the exterior seal rings <NUM> shown in <FIG>, interior seals (e.g., <NUM> and <NUM>) are formed after drilling, etching, or otherwise forming a channel <NUM> (fully or partially) around an inside perimeter of the bonded components (e.g., <NUM>, <NUM>, and <NUM>). Two separate configurations of example seals are illustrated in <FIG>, a filled seal <NUM> and a conformal seal <NUM>. Both configurations are formed in channels <NUM>, drilled portions, or the like, as discussed further below. The filled seal ring <NUM> mostly or fully fills the channel <NUM> or drilled cavity with one or more metallic materials to form the hermetic seal at the bond joint. The conformal seal ring <NUM> plates the walls of the channel <NUM> or cavity with the one or more metallic materials to form the hermetic seal. In various implementations, either the filled seal <NUM> or the conformal seal <NUM> may be used to hermetically seal two or more components (e.g., <NUM>, <NUM>, and <NUM>), as desired. In various examples, multiple concentric seal rings (e.g., <NUM>, <NUM>, and <NUM>) may be used to seal two (or more) components (e.g., <NUM>, <NUM>, and <NUM>). The channel(s) <NUM> may extend through component <NUM> and to the interface with component <NUM> or, shown, into component <NUM>.

<FIG> is a graphical flow diagram illustrating an example processing sequence <NUM> to form a sealed microelectronic device <NUM>, according to an embodiment using interior seals (e.g., <NUM> and <NUM>). In various embodiments, the process <NUM> described with reference to <FIG> may be used to modify other assembly processes (e.g., the process <NUM> referred to at <FIG>, for example) that include bonding microelectronic components (e.g., <NUM>, <NUM>, <NUM>, etc.), to include techniques and devices for hermetically sealing the bonded microelectronic components (e.g., <NUM>, <NUM>, <NUM>, etc.) at the bond joints, as desired.

At block <NUM>, a recessed cavity wafer <NUM> is formed. A channel <NUM> (or "cavity ring," partly or fully surrounding the cavity <NUM>) is formed on the cavity-side surface of the wafer <NUM>. The channel <NUM> may be formed by etching, drilling, or otherwise removing material from the surface of the wafer <NUM>.

At block <NUM>, the cavity wafer <NUM> is bonded to a MEMS wafer <NUM> closing the cavity <NUM> within. The cavity wafer <NUM> can be bonded to the MEMS wafer <NUM> using an intimate surface bonding technique, for example, such as a ZIBOND® technique, wherein insulating surfaces (e.g., SiOx - SiOx, etc.) are bonded. In another example, the cavity wafer <NUM> can be bonded to the MEMS wafer <NUM> using another dielectric bonding technique (e.g. die attach film or paste, a polymeric material such as a silicone or epoxy, or the like, which may not provide a hermetic seal and may not improve or fix a hermetic seal).

At block <NUM>, the MEMS wafer <NUM> may be thinned and patterned to form stand-offs. In another case, the stand-offs are optional and may not be formed on the MEMS wafer <NUM>. In such a case, the standoffs can be formed on the logic wafer <NUM> or can be created by any other material (e.g. die attach film or paste, etc.). At block <NUM>, openings are formed in the MEMS wafer <NUM>, accessing the cavity <NUM>, to define the characteristics of the microelectronic device <NUM>, based on the application. Also, channels <NUM> are formed in the MEMS wafer <NUM> (and in the cavity wafer <NUM>, in some examples) for forming interior seals (e.g., <NUM> and <NUM>) to seal the bonding joint between the cavity wafer <NUM> and the MEMS wafer <NUM>. In one case the MEMS wafer <NUM> can be drilled to open an area in the MEMS wafer <NUM> that is aligned with the cavity ring channel <NUM> previously formed in the cavity wafer <NUM>. In an alternate case, the MEMS wafer <NUM> and the cavity wafer <NUM> can be drilled together to form the cavity ring channel <NUM> (e.g., the channel <NUM> in the cavity wafer <NUM> is formed at this step, while drilling the MEMS wafer <NUM>, rather than being pre-formed prior to bonding the cavity wafer <NUM> to the MEMS wafer <NUM>).

At block <NUM>, metallization <NUM> is added to the patterned surface of the MEMS wafer <NUM>, including pads, contacts, traces, and so forth. The cavity ring channel <NUM> can also be metallized at this time. The channel <NUM> can be partially or fully filled/plated to form a filled seal ring <NUM>, or the walls of the channel <NUM> can be metallized/plated to form a conformal seal ring <NUM>. Either the filled seal ring <NUM> or the conformal seal ring <NUM> (whichever is used) hermetically seal the bond joint between the cavity wafer <NUM> and the MEMS wafer <NUM>.

In another example, after bonding, the MEMS wafer <NUM> and the cavity wafer <NUM> can be drilled together to form the cavity ring channel <NUM>, which can be metallized and then the openings to the cavity <NUM> are formed in the MEMS wafer <NUM>.

At block <NUM>, the microelectronic device <NUM> may be attached to a logic device <NUM>, to provide logic/control (for example) for the microelectronic device <NUM>. Contact pads of the metallized layer <NUM> of the microelectronic device <NUM> can be coupled to contacts <NUM> on the surface of the logic device <NUM>. At block <NUM>, portions of the microelectronic device <NUM> may be removed (e.g., etched, etc.) to provide access to other contact pads of the logic device <NUM>, and so forth.

<FIG> illustrate example embodiments of seals <NUM>, <NUM>, and <NUM> and sealed microelectronic devices <NUM>, according to various embodiments. A first embodiment, illustrated at <FIG>, shows exterior seals <NUM> implemented as discussed above with reference to <FIG> and <FIG>. Each seal <NUM> forms a bead that covers one or more bonding or coupling joints between the microelectronic components <NUM>, <NUM>, and <NUM>, to hermetically seal the joints. The seals <NUM> can be comprised of a metallic material such as a metal, an alloy, or a metal composite, for example a combination of two or more metals, a metal-glass composite material, a metal-ceramic composite, or the like.

A second embodiment, illustrated at <FIG>, shows seals having a layered approach, where a polymer seal <NUM> is applied to the exterior of the joint first and a metallic material seal <NUM> is deposited over the polymer seal <NUM>, forming a hermetic seal. In alternate implementations, multiple polymer materials forming one or more polymer seals <NUM> and/or multiple metallic layers forming one or more metallic seals <NUM> may also be used to form a seal ring.

A third embodiment, illustrated at <FIG>, shows another exterior seal ring <NUM>, comprised of a sinterable conductive paste, a fritted glass composite, or the like. The metallic or glass components in the deposited seal <NUM> material provide the hermetic seal desired.

A fourth embodiment, illustrated at <FIG>, shows interior seals <NUM> and <NUM> as discussed above with reference to <FIG> and <FIG>. A channel <NUM> is formed through the MEMS wafer <NUM> and into the cavity wafer <NUM>, and the channel <NUM> is plated from the MEMS wafer <NUM> side with metallic material, either fully (e.g., <NUM>), partially (not shown) or conformal (e.g., <NUM>) to the channel <NUM> walls.

A fifth embodiment, illustrated at <FIG>, shows an example of forming a seal ring (e.g., <NUM>) through multiple components (e.g., <NUM>, <NUM>, and <NUM>). In this example, the logic wafer <NUM> (or the like) can be thinned and drilled through, similar to the MEMS wafer <NUM>. For example, the logic wafer <NUM>, MEMS wafer <NUM>, and cavity wafer <NUM> may be bonded in a process and then drilled together, or in separate steps to be aligned. Plating or filling the drilled channel <NUM> from the logic wafer <NUM> side forms a seal ring (e.g., <NUM>) that extends from the logic wafer <NUM>, through the MEMS wafer <NUM>, and into the cavity wafer <NUM>, hermetically sealing each of the bonding joints and the spaces between the components (e.g., <NUM>, <NUM>, and <NUM>). Alternately, the seal (e.g., <NUM>) may extend through only some of the layers/components as desired. In various embodiments, the metallization of the seals (e.g., <NUM>, <NUM>) may be electrically continuous with or coupled to one or more device pads, for grounding, or the like (which may also be electrically continuous with a ball terminal <NUM> (for example) on the package. While multiple types of metallization (conformal, nonconformal) are shown in <FIG> and elsewhere in this disclosure, only a single type of metallization may be used at a time to form a continuous or discontinuous shape for inhibiting fluid flow and, thus, improving hermeticity.

<FIG> illustrate example embodiments of seals <NUM> and <NUM> and sealed microelectronic devices <NUM>, according to further embodiments. In one embodiment, illustrated at <FIG>, an embedded metallic ring <NUM> is partially or fully embedded within the cavity wafer <NUM> (and/or the MEMS wafer <NUM>) and partially or fully surrounds the cavity <NUM>. The embedded metallic ring <NUM>, which may be disposed at or near the bond line, can aid in sealing the bond joint between the cavity wafer <NUM> and the MEMS wafer <NUM>. A via (not shown for the sake of simplicity) may extend through cavity wafer <NUM> and contact the metallic ring <NUM>. In another embodiment, illustrated at <FIG>, the microelectronic device <NUM> includes an embedded metallic ring <NUM> partially or fully surrounding the cavity <NUM>, as well as one or more interior seals <NUM> and/or <NUM>, as discussed above with reference to <FIG> and <FIG>. A channel <NUM> is formed through the MEMS wafer <NUM> and into the cavity wafer <NUM>, to the embedded metallic ring <NUM>, and the channel <NUM> is plated from the MEMS wafer <NUM> side with metallic material, either fully (e.g., <NUM>), partially (not shown) or conformal (e.g., <NUM>) to the channel <NUM> walls.

As shown in <FIG>, the interior seals <NUM> and/or <NUM> are landed on (e.g., are in contact with) the embedded metallic ring <NUM>. <FIG> show close detail views of two possible embodiments (of many) for this arrangement. For example, in <FIG>, the channel <NUM> has a relatively rectangular cross-section, and in <FIG>, the channel has a polygonal, or otherwise shaped cross-section (e.g., partially or fully elliptical, irregular, etc.). In various embodiments, the width of the cross-section of the channel <NUM> and the seal (<NUM> and/or <NUM>), where the seal (<NUM> and/or <NUM>) makes contact with the embedded metallic ring <NUM>, is less (e.g., <NUM>% or less) than the width of the cross-section of the embedded metallic ring <NUM>. The metallic fill for the seals <NUM> may be fully (as seen in <FIG>) or partially (as seen in <FIG>) lining the interior walls of the channel <NUM>, while making contact with (landed on) the embedded metallic ring <NUM>. In various embodiments, the shape of the channel <NUM> may be predetermined, or may be a product of the drilling techniques employed to form the channel <NUM>.

<FIG> is a graphical flow diagram illustrating an example processing sequence <NUM> to form a sealed microelectronic device <NUM>, according to another embodiment using interior seals (e.g., <NUM>). In various embodiments, the process <NUM> described with reference to <FIG> may be used to modify other assembly processes (e.g., the process <NUM> referred to at <FIG>, for example) that include bonding microelectronic components (e.g., <NUM>, <NUM>, <NUM>, etc.), to include techniques and devices for hermetically sealing the bonded microelectronic components (e.g., <NUM>, <NUM>, <NUM>, etc.) at the bond joints, as desired.

At block <NUM>, a recessed cavity wafer <NUM> is formed and prepared for bonding to a second wafer <NUM>. In various embodiments, the bonding surface of the second wafer <NUM> may include an added layer <NUM>, such as an insulating layer, a dielectric layer, a semiconductor layer, a metallic layer, and so forth.

At block <NUM>, the cavity wafer <NUM> is bonded to the second wafer <NUM>, closing the cavity <NUM> within. The cavity wafer <NUM> can be bonded to the second wafer <NUM> (and the layer <NUM>) using an intimate surface bonding technique, for example, such as a ZIBOND® technique, wherein insulating surfaces (e.g., SiOx - SiOx, etc.) are bonded. In another example, the cavity wafer <NUM> can be bonded to the second wafer <NUM> using another dielectric bonding technique (e.g. die attach film or paste, a polymeric material such as a silicone or epoxy, or the like, which may not provide a hermetic seal and may not improve or fix a hermetic seal).

At block <NUM>, the cavity wafer <NUM> and/or the second wafer <NUM> may be thinned based on the intended application. At block <NUM>, a coating or layer <NUM>, such as a dielectric layer or the like, may be applied to the exposed surface of the cavity wafer <NUM>. At block <NUM>, one or more channels <NUM> (or "cavity rings," partly or fully surrounding the cavities <NUM>) can be formed through portions of the cavity wafer <NUM>, portions of the second wafer <NUM>, and through one or both of the layers <NUM> and <NUM>. The channels <NUM> may be formed by etching, drilling, or otherwise removing material from the wafers <NUM> and <NUM>, and may be open to an outside surface of the cavity wafer <NUM> or the second wafer <NUM>.

At block <NUM>, the cavity ring channels <NUM> can be partially or fully filled/plated with a metallic material (e.g., copper) to form filled seal rings <NUM>. The filled seal rings <NUM> hermetically seal the bond joints between the cavity wafer <NUM> and the second wafer <NUM>, sealing the cavities <NUM>. In an implementation, the top exposed portion of the metallic seal rings <NUM> comprise a redistribution layer (RDL).

Referring to <FIG>, several embodiments of the sealed microelectronic device <NUM> are illustrated as examples. <FIG> shows a sealed microelectronic device <NUM> wherein the bottom portion of the one or more filled seal rings <NUM> is disposed within the layer <NUM> (which may be a dielectric layer, for example), and may or may not penetrate the second wafer <NUM>. An opposite end of the filled seal rings <NUM> (e.g., at the top of the cavity wafer <NUM>) may be exposed and contact a metal layer for electrical (and/or heat dissipation) function of the microelectronic device <NUM>, for example.

<FIG> shows another sealed microelectronic device <NUM> wherein the bottom portion of the filled seal rings <NUM> is disposed within the layer <NUM> (which may be a dielectric layer, for example), and may or may not penetrate the second wafer <NUM>. The top portion of the filled seal rings <NUM> forms a redistribution layer (RDL) over a portion of the exposed surface of the cavity wafer <NUM>. In the embodiment, the dielectric layer <NUM> is patterned so that the dielectric layer <NUM> is not covering over the one or more cavities <NUM>. <FIG> shows a further sealed microelectronic device <NUM> wherein the bottom portion of the filled seal rings <NUM> is disposed within the layer <NUM> (which may be a dielectric layer, for example), and may or may not penetrate the second wafer <NUM>. The top portion of the filled seal rings <NUM> forms a redistribution layer (RDL) over one or more portions of the exposed surface of the cavity wafer <NUM>. In the embodiment, the dielectric layer <NUM> is patterned so that the dielectric layer <NUM> is not covering over the one or more cavities <NUM>, however, a different layer <NUM> is arranged to cover over the cavities <NUM>. In various embodiments, the different layer <NUM> may comprise a substrate, a glass panel, a metallic layer, or the like.

At block <NUM>, the cavity wafer <NUM> and/or the second wafer <NUM> may be thinned based on the intended application. Further, the assembly featuring the cavity wafer <NUM> and the second wafer <NUM> may be flipped for processing from the second wafer <NUM> side. At block <NUM>, a coating or layer <NUM>, such as a dielectric layer or the like, may be applied to the exposed surface of the second wafer <NUM>. At block <NUM>, one or more channels <NUM> (or "cavity rings," partly or fully surrounding the cavities <NUM>) can be formed through portions of the second wafer <NUM>, portions of the cavity wafer <NUM>, and through one or both of the layers <NUM> and <NUM>. The channels <NUM> may be formed by etching, drilling, or otherwise removing material from the wafers <NUM> and <NUM>, and may be open to an outside surface of the second wafer <NUM> or the cavity wafer <NUM>. As discussed above, the channels may extend only the interface between wafers (or dies) <NUM> and <NUM> and may extend to one or more metallic features such as a pad or via on or within wafer <NUM>.

At block <NUM>, the cavity ring channels <NUM> can be partially or fully filled/plated with a metallic material (e.g., copper) to form filled seal rings <NUM>. The filled seal rings <NUM> hermetically seal the bond joints between the second wafer <NUM> and the cavity wafer <NUM>, sealing the cavities <NUM>. In an implementation, the top exposed portion of the metallic seal rings <NUM> may comprise a redistribution layer (RDL).

Referring to <FIG>, embodiments of the sealed microelectronic device <NUM> are illustrated as examples. <FIG> show sealed microelectronic devices <NUM> wherein the bottom portion of the filled seal rings <NUM> is disposed within the layer <NUM> (which may be a dielectric layer, for example), and may or may not penetrate the cavity wafer <NUM>. An opposite end of the filled seal rings <NUM> (e.g., at the top of the second wafer <NUM>) may be exposed and contact a metal layer for electrical function of the microelectronic device <NUM>, for example. In the embodiments, the dielectric layer <NUM> is patterned so that the dielectric layer <NUM> is not covering over the one or more cavities <NUM>, however, a different layer <NUM> is arranged to cover over the cavities <NUM>. In various embodiments, the different layer <NUM> may comprise a substrate, a glass panel, a metallic layer, or the like.

In various embodiments, as shown at <FIG>, the one or more cavities <NUM> extend into the second wafer <NUM> as well as the cavity wafer <NUM>. The filled seal rings <NUM> hermetically seal the bond joints between the second wafer <NUM> and the cavity wafer <NUM>, sealing the cavities <NUM>. Additionally, as shown in <FIG>, a metallic barrier layer <NUM> may be applied within one or more of the cavities <NUM> to further seal the one or more cavities <NUM>. The metallic barrier <NUM> can be disposed on the side walls, or on the side, top, and bottom walls, partially or fully covering the inside surfaces of the cavities <NUM>, as shown in <FIG>. In an implementation, the metallic barrier <NUM> may be applied to the inside surfaces of the cavities <NUM> prior to bonding the cavity wafer <NUM> to the second wafer <NUM>. The bonding process may include a metal-to-metal bonding (such as DBI, for instance), with or without a heated annealing, to bond the metallic barrier <NUM> disposed on the inside surfaces of the cavity wafer <NUM> to the metallic barrier <NUM> disposed on the inside surfaces of the second wafer <NUM>, forming a continuous metallic sealing barrier <NUM>.

At block <NUM>, a recessed cavity wafer <NUM> is formed and prepared for bonding to a second wafer <NUM> (which may or may not be a MEMS wafer, for example). In various embodiments, the bonding surface of the second wafer <NUM> may include an added layer <NUM>, such as an insulating layer, a dielectric layer, a semiconductor layer, a metallic layer, and so forth.

At block <NUM>, the cavity ring channels <NUM> can be partially filled/plated with a metallic material (e.g., copper) to form conformal seal rings <NUM>. The seal rings <NUM> hermetically seal the bond joints between the cavity wafer <NUM> and the second wafer <NUM>, sealing the cavities <NUM>. In various embodiments, the channels <NUM> can be filled/plated to form the conformal seal rings <NUM> while a metallic layer <NUM> is deposited onto at least a portion of the exposed surface of the cavity wafer <NUM>. Accordingly, in various embodiments, the channels <NUM> are filled in the same or in separate processes as the deposition of the metallic layer <NUM>.

Referring to <FIG>, several embodiments of the sealed microelectronic device <NUM> are illustrated as examples. <FIG> show sealed microelectronic devices <NUM> wherein the seal rings <NUM> are formed through the cavity layer <NUM>, and the bottom portion of the seal rings <NUM> is disposed through the layer <NUM> (which may be a dielectric layer, for example) and also penetrate the second wafer <NUM>. <FIG> show partially filled seal rings <NUM> (e.g., plated in a vacuum, for example), with the embodiment shown at <FIG> having a greater quantity of metal within the partially filled seal rings <NUM> than the embodiment shown at <FIG>. Annealing the substrates (bonded wafers <NUM> and <NUM>) in the partially filled condition at temperatures between <NUM> and 250C can enlarge the grain size of the plated metal (e.g., <NUM> and/or <NUM>). The process of producing the enlarged grain sizes can reduce impurities within the metal layer of the seal rings <NUM> and/or the metallic layer <NUM>. In an implementation, the grains have a general (e.g., average) diameter that is greater than <NUM> percent of the width dimension of the channel <NUM>.

<FIG> shows fully filled seal rings <NUM> within the channels <NUM>. In some embodiments, the annealed metal of the partially filled seal rings <NUM>, as shown in <FIG>, can be added to or coated with an additional metal layer to form the fully filled seal rings <NUM>. In an embodiment, the sealed microelectronic device <NUM> may be annealed again after deposition of the additional metal layer. In some cases, CMP may be used prior to the final annealing or afterwards, to form a desired surface for the filled seal rings <NUM>. One or more additional materials may be provided in the unfilled portion of the seal ring <NUM>, as needed, for reliability, robustness, performance, etc..

The top (e.g., exposed) end of the filled seal rings <NUM> (e.g., at the top surface of the cavity wafer <NUM>) may be exposed and contact a metal layer for electrical function of the microelectronic device <NUM>, for example, when bonded to another device.

The quantity of seal rings <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> shown in the illustrations of <FIG> are for example and discussion. In various embodiments, a sealed microelectronic device <NUM> or like assembly may include fewer, or a greater quantity of seal rings <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, and remain within the scope of the disclosure. Moreover, various implementations described herein may be combined to further enhance the improvement over conventional techniques of fabricating a MEMS device. For example, while seal rings are shown to extend into one surface from one side of the component, seal rings may be formed from both sides and may contact each other to form a metallic structure fully extending through the sealed microelectronic device <NUM>.

Claim 1:
A microelectronic assembly, comprising:
a first microelectronic component (<NUM>) bonded at a first insulating surface to a second insulating surface of a second microelectronic component (<NUM>), the first insulating surface and the second insulating surface forming a bond joint where the first insulating surface and the second insulating surface make contact; and
a seal (<NUM>) disposed over the bond joint, the seal comprising a metallic material and sealing the bond joint between the first microelectronic component (<NUM>) and the second microelectronic component (<NUM>), characterized by the seal comprising a channel (<NUM>) extending continuously around an interior region of the bonded structure, the channel (<NUM>) having sidewalls at least partially covered with metal, the sidewalls extending from a second surface of the first microelectronic component (<NUM>) into the first microelectronic component (<NUM>).