Patent Description:
<CIT> discloses instructions to convert to bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.

The invention is defined by an apparatus and a method according to the independent claims.

The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for converting FP16 to BF8 using a single instruction. To prepare higher-precision outputs to be used as the next operation's inputs, in some embodiments, those outputs need to be converted/rounded to BF8 numbers. Using <NUM>-bit floating-point format instead of single- precision in at least some matrix operations is expected to alleviate memory utilization and bandwidth issues while providing a non-trivial performance upside (e.g., on the order of 2X) even during the compute operation. Additionally, numerical accuracy studies have shown that the precision of the Deep Learning application is not compromised. However, extensive workload studies have shown, that from time to time its required to avoid classic round-to-nearest behavior during these down converts. Instead a stochastic rounding operation is needed.

Current experiments show bandwidth issues on the various cache levels and DRAM. So, as matrix compute capabilities speed up significantly (2X), the memory sub-systems capabilities only increase modestly due to reduce memory footprint. However, it has been found important to achieve convergence that FMAs accumulate into single-precision, IEEE float32. That means it may be important down-convert a result to BF8 after the operation completes.

Some processors offer float16 compute and int8/int16 compute stacks. To convert a number from IEEE float16 to BF8 requires the detour via various int8/int8 instructions as the bias term can be implemented this way, however its execution is very slow.

Embodiments detailed herein describe instructions and instructional support for performing this conversion/rounding using a bias term for rounding. In particular, a FP16 value is converted/rounded to a BF8 value. In particular, embodiments of an instruction to convert from FP16 to BF8 are detailed. One or more of these instructions, when executed, convert two vectors (up to <NUM><NUM>-bit elements in a <NUM>-bit register) to <NUM>-bit BF8 using bias terms from a third vector. Hardware-assisted conversion may also afford the opportunity to "hide" the conversion infrastructure from software (SW) and the operating system (OS), for example, by performing arithmetic on a converted vector while converting the next vector.

Execution of embodiments of the instruction is to cause a conversion, using a perelement biased rounding mechanism, of a plurality of packed FP16 values in two packed data source operands (e.g., a SIMD/packed data/vector registers or a memory location) having a plurality of FP16 data elements) using bias terms from a source/destination vector to a plurality of packed BF8 values and store those values in a packed data destination operand (e.g., a SIMD/packed data/vector register or memory location). In some embodiments, the instruction format utilizes a writemask or predicate, which is used to determine which data element positions of the destination are to be updated, zeroed, etc..

As such, a processor or core implementing the instruction will execute according to the opcode of the instruction a conversion of each of the elements of the sources from FP16 to BF8 using bias terms from the source/destination and store each converted element into a corresponding data element position of the specified source/destination vector. Note that the two sources are treated as being one large source for the purposes of data element positions. For example, for <NUM>-bit sources a first of the sources has data element positions <NUM>-<NUM> and the second of the sources has data element positions <NUM>-<NUM> with respect to the source/destination. In some embodiments, the conversion is to include truncation and rounding, as necessary.

In some embodiments, the FP16 to BF8 conversion instruction has a mnemonic of VCVTBIAS2PH2BF8 where VCVT indicates a convert, BIAS indicates using bias terms, 2PH indicates two packed FP16 sources, <NUM> indicates "to", and BF8 indicates the <NUM>-<NUM>-<NUM> version of BF8. An embodiment of a format for the second FP16 to BF8 conversion instruction is VCVTBIAS2PH2BF8{k1} SRCDST, SRC1, SR2. In some embodiments, VCVTNEPH2BF8 is the opcode mnemonic of the instruction. SRCDST indicates a packed data source/destination operand location and SRC1 and SRC2 indicate packed data source operand locations. Exemplary operand sizes include, but are not limited to <NUM>-bit, <NUM>-bit, <NUM>-bit, <NUM>-bit, and <NUM>-bit. For example, SRC1, SRC2, and SRCDST may be <NUM>-bit registers, where the SRC1 and SRC2 are to store <NUM> FP16 elements and the SRCDST has storage for <NUM> BF8 elements (after conversion) and <NUM> bias terms (to use during conversion). A benefit of VCVTBIAS2PH2BF8 is that the register space and cache ports are used efficiently as to max out their corresponding widths in some embodiments.

In some embodiments, k1 indicates the use of writemasking/predication. One or more of the operands may be a memory location. In some embodiments, the destination is encoded using one or more fields for ModRM:reg(w), the first source is encoded using one more fields from a prefix (e.g., vvvv(r)), and the second source is encoded using one or more fields for ModRM:r/m(r). In some embodiments, the instruction uses prefix <NUM>(C).

<FIG> illustrates an exemplary execution of a VCVTBIAS2PH2BF8 instruction. While this illustration is in little endian format, the principles discussed herein work in big endian format. In this example, writemasking/predication is not used.

As shown, each of the packed data sources <NUM> and <NUM> include N FP16 elements. Depending upon the implementation, the packed data source <NUM><NUM> and packed data source <NUM><NUM> are a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, etc. register), or a memory location.

A pre-execution packed data source/destination <NUM>(A) stores a plurality of packed biases (e.g., <NUM>-bit bias terms). The packed data source <NUM>, packed data source <NUM><NUM>, and the pre-execution packed data source/destination <NUM>(A) (acting as a source) are fed into execution circuitry <NUM> to be operated on. In particular, execution circuitry <NUM> performs the FP16 to BF8 conversion using FP16 to BF8 combinational logic <NUM>. Details of embodiments of operations of that combinational logic <NUM> are described as flow diagrams later.

Post-execution packed data source/destination <NUM> stores the results of the conversions of the FP16 data elements of packed data sources <NUM> and <NUM> in corresponding positions of the packed data destination <NUM>. For example, packed data source position <NUM> (far right) of packed data source <NUM><NUM> is stored in packed data destination position <NUM> (far right). While the most significant packed data element position of packed data source <NUM><NUM> is stored in the most significant packed data element position of the packed data destination <NUM>.

<FIG> illustrates embodiments of hardware to process an instruction such as the FP16 to BF8 (e.g., VCVTBIAS2PH2BF8) instruction. As illustrated, storage <NUM> stores a VCVTBIAS2PH2BF8 instruction <NUM> to be executed.

The instruction <NUM> is received by decode circuitry <NUM>. For example, the decode circuitry <NUM> receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and second sources, and a destination. In some embodiments, the sources and destination are registers, and in other embodiments one or more are memory locations.

More detailed embodiments of at least one instruction format will be detailed later. The decode circuitry <NUM> decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry <NUM>). The decode circuitry <NUM> also decodes instruction prefixes. In some embodiments, the decode circuitry <NUM> translates between instruction sets and then decodes the translated instruction(s).

In some embodiments, register renaming, register allocation, and/or scheduling circuitry <NUM> provides functionality for one or more of: <NUM>) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), <NUM>) allocating status bits and flags to the decoded instruction, and <NUM>) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).

Registers (register file) and/or memory <NUM> store data as operands of the instruction to be operated on by execution circuitry <NUM>. Exemplary register types include packed data registers, general purpose registers, and floating-point registers.

Execution circuitry <NUM> executes the decoded instruction. Exemplary detailed execution circuitry is shown in <FIG>, <FIG>, etc. The execution of the decoded instruction causes the execution circuitry to convert packed FP16 data elements to packed BF8 elements using bias terms.

In some embodiments, retirement/write back circuitry <NUM> architecturally commits the destination register into the registers or memory <NUM> and retires the instruction.

<FIG> illustrates an embodiment of method performed by a processor to process a VCVTBIAS2PH2BF8 instruction. For example, a processor core as shown in <FIG>, a pipeline as detailed below, etc. performs this method.

At <NUM>, a single VCVTBIAS2PH2BF8 instruction is fetched. The single VCVTBIAS2PH2BF8 includes one or more fields to identify two source operands (e.g., addressing field(s) <NUM>), one or more fields to identify a source/destination operand (e.g., addressing field(s) <NUM>), and one or more fields for an opcode (e.g., opcode <NUM>), the opcode to indicate that execution circuitry is to convert packed half-precision floating point data from the identified first and second sources to packed bfloat8 data using bias terms from the source/destination and store the packed bfloat8 data into corresponding data element positions of the identified source/destination. In some embodiments, the MOD R/M byte <NUM>, vvvv of prefix BPF01(C)m and/or SIB byte <NUM> provide the operand locations.

In some embodiments, the fetched instruction is translated into one or more instructions at <NUM>. For example, the fetched instruction is translated into one or more instructions of a different instruction set architecture.

The fetched instruction (or translated one or more instructions) is/are decoded at <NUM>. For example, the fetched VCVTBIAS2PH2BF8 instruction is decoded by decode circuitry such as that detailed herein.

Data values associated with the source operands of the decoded instruction are retrieved at <NUM>. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.

At <NUM>, the decoded single instruction is executed, or the translated one or more instructions are executed, by execution circuitry (hardware) such as that detailed herein. For the VCVTBIAS2PH2BF8 instruction, the execution will cause execution circuitry to convert packed half-precision floating point data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination and store the packed bfloat8 data into corresponding data element positions of the identified source/destination.

In some embodiments, the instruction is committed or retired at <NUM>.

<FIG> illustrates embodiments of method performed by a processor to process a VCVTBIAS2PH2BF8 instruction. In particular, the execution of the instruction is described. For example, a processor core as shown in <FIG>, a pipeline as detailed below, etc. performs this method. Recall that the first and second sources as essentially treated as a single source (e.g., a concatenation of the two sources) for the purposes of data element positions of the source/destination.

A plurality of actions may be applicable to each data element of the second source and include one or more of <NUM>-<NUM>. Note that the per element evaluation may be done serially or in parallel.

At <NUM> a determination of if a writemask applies. For example, was a writemask used? If so, was the corresponding bit position of the writemask or predicate set to allow a resulting conversion to be stored for the data element?.

When the writemask applies, a determination of if the second source is memory and single element broadcasting enabled is made <NUM> in some embodiments. In some embodiments, bit <NUM> of <NUM>(C) is used for the broadcasting setting.

When those conditions are true, a temporary value (t) is set to be a value stored in the initial element position of the source at <NUM> in some embodiments. When those conditions are not true, a temporary value (t) is set to be a value stored in the element position of the source at <NUM>. A conversion of the temporary value t from FP16 to BF8 using bias terms (as needed) from the source/destination is made at <NUM>. <FIG> illustrates how this conversion is made in some embodiments in a "convert_fp16_to_bfloat8_bias" function. The table below illustrates how t is converted according to some embodiments.

In some embodiments, a different function ("convert_to_fp16_bfloat8_RNO") is used. The table below illustrates how t is converted according to some embodiments.

The converted value is stored into a corresponding byte location in the destination at <NUM>. For example, source[<NUM>] is stored in destination[<NUM>].

If the writemask does not apply (e.g., not set), then a determination of if zeroing being used is made at <NUM>. When zeroing is used, no changes are made to a value in a corresponding byte location of the destination at <NUM>. When zeroing is not used (e.g., merge masking is used), a value in a corresponding byte location position of the destination is set to be zero at <NUM>.

The first source is evaluated at <NUM> and this evaluation may include several actions. At <NUM> a determination of if a writemask applies. For example, was a writemask used? If so, was the corresponding bit position of the writemask or predicate set to allow a resulting conversion to be stored for the data element?.

When the writemask applies, a temporary value (t) is set to be a value to be stored in the initial element position of the source at <NUM>. A conversion of the temporary value t from FP16 to BF8 using bias terms (as needed) from the source/destination at <NUM>. <FIG> illustrates how this conversion is made in some embodiments in a "convert_fp16_to_bfloat8_bias" function.

The table below illustrates how t is converted according to some embodiments.

The converted value is stored into a corresponding byte location in the destination at <NUM>. Note that this corresponding location needs to account for the storage from the second source. For example, source1[<NUM>] is stored in destination[N].

If the writemask does not apply (e.g., not set), then a determination of if is zeroing being used is made at <NUM>. When zeroing is used, no changes are made to a value in a corresponding byte location of the destination at <NUM>. When zeroing is not used (e.g., merge masking is used), a value in a corresponding byte location position of the destination is set to be zero at <NUM>.

<FIG> illustrates embodiments of pseudocode for performing the VCVTBIAS2PH2BF8 instruction.

The instructions detailed above may be used in a variety of computer architectures and environments, utilize one or more instruction formats, etc. Embodiments of exemplary architectures, formats, etc. are detailed below.

Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

<FIG> illustrates embodiments of an exemplary system. Multiprocessor system <NUM> is a point-to-point interconnect system and includes a plurality of processors including a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. In some embodiments, the first processor <NUM> and the second processor <NUM> are homogeneous. In some embodiments, first processor <NUM> and the second processor <NUM> are heterogenous.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units circuitry <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its interconnect controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via the point-to-point (P-P) interconnect <NUM> using P-P interface circuits <NUM>, <NUM>. IMCs <NUM> and <NUM> couple the processors <NUM>, <NUM> to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interconnects <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with a coprocessor <NUM> via a high-performance interface <NUM>. In some embodiments, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor <NUM>, <NUM> or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset <NUM> may be coupled to a first interconnect <NUM> via an interface <NUM>. In some embodiments, first interconnect <NUM> may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I/O interconnect. In some embodiments, one of the interconnects couples to a power control unit (PCU) <NUM>, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors <NUM>, <NUM> and/or co-processor <NUM>. PCU <NUM> provides control information to a voltage regulator to cause the voltage regulator to generate the appropriate regulated voltage. PCU <NUM> also provides control information to control the operating voltage generated. In various embodiments, PCU <NUM> may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU <NUM> is illustrated as being present as logic separate from the processor <NUM> and/or processor <NUM>. In other cases, PCU <NUM> may execute on a given one or more of cores (not shown) of processor <NUM> or <NUM>. In some cases, PCU <NUM> may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other embodiments, power management operations to be performed by PCU <NUM> may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other embodiments, power management operations to be performed by PCU <NUM> may be implemented within BIOS or other system software.

Various I/O devices <NUM> may be coupled to first interconnect <NUM>, along with an interconnect (bus) bridge <NUM> which couples first interconnect <NUM> to a second interconnect <NUM>. In some embodiments, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interconnect <NUM>. In some embodiments, second interconnect <NUM> may be a low pin count (LPC) interconnect. Various devices may be coupled to second interconnect <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit circuitry <NUM>. Storage unit circuitry <NUM> may be a disk drive or other mass storage device which may include instructions/code and data <NUM>, in some embodiments. In some embodiments, the instructions/code and data <NUM> include a binary translator or other emulation functionality. Further, an audio I/O <NUM> may be coupled to second interconnect <NUM>. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system <NUM> may implement a multi-drop interconnect or other such architecture.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> illustrates a block diagram of embodiments of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics. The solid lined boxes illustrate a processor <NUM> with a single core 702A, a system agent <NUM>, a set of one or more interconnect controller units circuitry <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores <NUM>(A)-(N), a set of one or more integrated memory controller unit(s) circuitry <NUM> in the system agent unit circuitry <NUM>, and special purpose logic <NUM>, as well as a set of one or more interconnect controller units circuitry <NUM>. Note that the processor <NUM> may be one of the processors <NUM> or <NUM>, or co-processor <NUM> or <NUM> of <FIG>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores <NUM>(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit circuitry), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

A memory hierarchy includes one or more levels of cache unit(s) circuitry <NUM>(A)-(N) within the cores <NUM>(A)-(N), a set of one or more shared cache units circuitry <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units circuitry <NUM>. The set of one or more shared cache units circuitry <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some embodiments ring-based interconnect network circuitry <NUM> interconnects the special purpose logic <NUM> (e.g., integrated graphics logic), the set of shared cache units circuitry <NUM>, and the system agent unit circuitry <NUM>, alternative embodiments use any number of well-known techniques for interconnecting such units. In some embodiments, coherency is maintained between one or more of the shared cache units circuitry <NUM> and cores <NUM>(A)-(N).

In some embodiments, one or more of the cores <NUM>(A)-(N) are capable of multithreading. The system agent unit circuitry <NUM> includes those components coordinating and operating cores <NUM>(A)-(N). The system agent unit circuitry <NUM> may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores <NUM>(A)-(N) and/or the special purpose logic <NUM> (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores <NUM>(A)-(N) may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores <NUM>(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In <FIG>, a processor pipeline <NUM> includes a fetch stage <NUM>, an optional length decode stage <NUM>, a decode stage <NUM>, an optional allocation stage <NUM>, an optional renaming stage <NUM>, a scheduling (also known as a dispatch or issue) stage <NUM>, an optional register read/memory read stage <NUM>, an execute stage <NUM>, a write back/memory write stage <NUM>, an optional exception handling stage <NUM>, and an optional commit stage <NUM>. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage <NUM>, one or more instructions are fetched from instruction memory, during the decode stage <NUM>, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or an link register (LR)) may be performed. In one embodiment, the decode stage <NUM> and the register read/memory read stage <NUM> may be combined into one pipeline stage. In one embodiment, during the execute stage <NUM>, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AHB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc..

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline <NUM> as follows: <NUM>) the instruction fetch <NUM> performs the fetch and length decoding stages <NUM> and <NUM>; <NUM>) the decode unit circuitry <NUM> performs the decode stage <NUM>; <NUM>) the rename/allocator unit circuitry <NUM> performs the allocation stage <NUM> and renaming stage <NUM>; <NUM>) the scheduler unit(s) circuitry <NUM> performs the schedule stage <NUM>; <NUM>) the physical register file(s) unit(s) circuitry <NUM> and the memory unit circuitry <NUM> perform the register read/memory read stage <NUM>; the execution cluster <NUM> perform the execute stage <NUM>; <NUM>) the memory unit circuitry <NUM> and the physical register file(s) unit(s) circuitry <NUM> perform the write back/memory write stage <NUM>; <NUM>) various units (unit circuitry) may be involved in the exception handling stage <NUM>; and <NUM>) the retirement unit circuitry <NUM> and the physical register file(s) unit(s) circuitry <NUM> perform the commit stage <NUM>.

<FIG> shows processor core <NUM> including front-end unit circuitry <NUM> coupled to an execution engine unit circuitry <NUM>, and both are coupled to a memory unit circuitry <NUM>.

The front end unit circuitry <NUM> may include branch prediction unit circuitry <NUM> coupled to an instruction cache unit circuitry <NUM>, which is coupled to an instruction translation lookaside buffer (TLB) <NUM>, which is coupled to instruction fetch unit circuitry <NUM>, which is coupled to decode unit circuitry <NUM>. In one embodiment, the instruction cache unit circuitry <NUM> is included in the memory unit circuitry <NUM> rather than the front-end unit circuitry <NUM>. The decode unit circuitry <NUM> (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit circuitry <NUM> may further include an address generation unit circuitry (AGU, not shown). In one embodiment, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuitry <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core <NUM> includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode unit circuitry <NUM> or otherwise within the front end unit circuitry <NUM>). In one embodiment, the decode unit circuitry <NUM> includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline <NUM>. The decode unit circuitry <NUM> may be coupled to rename/allocator unit circuitry <NUM> in the execution engine unit circuitry <NUM>.

The execution engine circuitry <NUM> includes the rename/allocator unit circuitry <NUM> coupled to a retirement unit circuitry <NUM> and a set of one or more scheduler(s) circuitry <NUM>. The scheduler(s) circuitry <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. In some embodiments, the scheduler(s) circuitry <NUM> can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry <NUM> is coupled to the physical register file(s) circuitry <NUM>. Each of the physical register file(s) circuitry <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical registerfile(s) unit circuitry <NUM> includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) unit(s) circuitry <NUM> is overlapped by the retirement unit circuitry <NUM> (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry <NUM> and the physical register file(s) circuitry <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units circuitry <NUM> and a set of one or more memory access circuitry <NUM>. The execution units circuitry <NUM> may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other embodiments may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry <NUM>, physical register file(s) unit(s) circuitry <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) unit circuitry, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some embodiments, the execution engine unit circuitry <NUM> may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AHB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry <NUM> is coupled to the memory unit circuitry <NUM>, which includes data TLB unit circuitry <NUM> coupled to a data cache circuitry <NUM> coupled to a level <NUM> (L2) cache circuitry <NUM>. In one exemplary embodiment, the memory access units circuitry <NUM> may include a load unit circuitry, a store address unit circuit, and a store data unit circuitry, each of which is coupled to the data TLB circuitry <NUM> in the memory unit circuitry <NUM>. The instruction cache circuitry <NUM> is further coupled to a level <NUM> (L2) cache unit circuitry <NUM> in the memory unit circuitry <NUM>. In one embodiment, the instruction cache <NUM> and the data cache <NUM> are combined into a single instruction and data cache (not shown) in L2 cache unit circuitry <NUM>, a level <NUM> (L3) cache unit circuitry (not shown), and/or main memory. The L2 cache unit circuitry <NUM> is coupled to one or more other levels of cache and eventually to a main memory.

The core <NUM> may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)), including the instruction(s) described herein.

<FIG> illustrates embodiments of execution unit(s) circuitry, such as execution unit(s) circuitry <NUM> of <FIG>. As illustrated, execution unit(s) circuity <NUM> may include one or more ALU circuits <NUM>, vector/SIMD unit circuits <NUM>, load/store unit circuits <NUM>, and/or branch/jump unit circuits <NUM>. ALU circuits <NUM> perform integer arithmetic and/or Boolean operations. Vector/SIMD unit circuits <NUM> perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store unit circuits <NUM> execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store unit circuits <NUM> may also generate addresses. Branch/jump unit circuits <NUM> cause a branch or jump to a memory address depending on the instruction. Floating-point unit (FPU) circuits <NUM> perform floating-point arithmetic. The width of the execution unit(s) circuitry <NUM> varies depending upon the embodiment and can range from <NUM>-bit to <NUM>,<NUM>-bit. In some embodiments, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two <NUM>-bit execution units are logically combined to form a <NUM>-bit execution unit).

<FIG> is a block diagram of a register architecture <NUM> according to some embodiments. As illustrated, there are vector/SIMD registers <NUM> that vary from <NUM>-bit to <NUM>,<NUM> bits width. In some embodiments, the vector/SIMD registers <NUM> are physically <NUM>-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some embodiments, the vector/SIMD registers <NUM> are ZMM registers which are <NUM> bits: the lower <NUM> bits are used for YMM registers and the lower <NUM> bits are used for XMM registers. As such, there is an overlay of registers. In some embodiments, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

In some embodiments, the register architecture <NUM> includes writemask/predicate registers <NUM>. For example, in some embodiments, there are <NUM> writemask/predicate registers (sometimes called k0 through k7) that are each <NUM>-bit, <NUM>-bit, <NUM>-bit, or <NUM>-bit in size. Writemask/predicate registers <NUM> may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given writemask/predicate register <NUM> corresponds to a data element position of the destination. In other embodiments, the writemask/predicate registers <NUM> are scalable and consists of a set number of enable bits for a given vector element (e.g., <NUM> enable bits per <NUM>-bit vector element).

The register architecture <NUM> includes a plurality of general-purpose registers <NUM>. These registers may be <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. and can be used for scalar operations. In some embodiments, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

In some embodiments, the register architecture <NUM> includes scalar floating-point register <NUM> which is used for scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating-point data using the x87 instruction set extension or as MMX registers to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

One or more flag registers <NUM> (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers <NUM> may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, the one or more flag registers <NUM> are called program status and control registers.

Segment registers <NUM> contain segment points for use in accessing memory. In some embodiments, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

Machine specific registers (MSRs) <NUM> control and report on processor performance. Most MSRs <NUM> handle system-related functions and are not accessible to an application program. Machine check registers <NUM> consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors.

One or more instruction pointer register(s) <NUM> store an instruction pointer value. Control register(s) <NUM> (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>) and the characteristics of a currently executing task. Debug registers <NUM> control and allow for the monitoring of a processor or core's debugging operations.

Memory management registers <NUM> specify the locations of data structures used in protected mode memory management. These registers may include a GDTR, IDRT, task register, and a LDTR register.

Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers.

An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

<FIG> illustrates embodiments of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes <NUM>, an opcode <NUM>, addressing information <NUM> (e.g., register identifiers, memory addressing information, etc.), a displacement value <NUM>, and/or an immediate <NUM>. Note that some instructions utilize some or all of the fields of the format whereas others may only use the field for the opcode <NUM>. In some embodiments, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other embodiments these fields may be encoded in a different order, combined, etc..

The prefix(es) field(s) <NUM>, when used, modifies an instruction. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xf2, 0xf3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xf3, etc.). Certain of these prefixes may be considered "legacy" prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the "legacy" prefixes.

The opcode field <NUM> is used to at least partially define the operation to be performed upon a decoding of the instruction. In some embodiments, a primary opcode encoded in the opcode field <NUM> is <NUM>, <NUM>, or <NUM> bytes in length. In other embodiments, a primary opcode can be a different length. An additional <NUM>-bit opcode field is sometimes encoded in another field.

The addressing field <NUM> is used to address one or more operands of the instruction, such as a location in memory or one or more registers. <FIG> illustrates embodiments of the addressing field <NUM>. In this illustration, an optional ModR/M byte <NUM> and an optional Scale, Index, Base (SIB) byte <NUM> are shown. The ModR/M byte <NUM> and the SIB byte <NUM> are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that each of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte <NUM> includes a MOD field <NUM>, a register field <NUM>, and R/M field <NUM>.

The content of the MOD field <NUM> distinguishes between memory access and nonmemory access modes. In some embodiments, when the MOD field <NUM> has a value of b11, a register-direct addressing mode is utilized, and otherwise register-indirect addressing is used.

The register field <NUM> may encode either the destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The content of register index field <NUM>, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some embodiments, the register field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing.

The R/M field <NUM> may be used to encode an instruction operand that references a memory address, or may be used to encode either the destination register operand or a source register operand. Note the R/M field <NUM> may be combined with the MOD field <NUM> to dictate an addressing mode in some embodiments.

The SIB byte <NUM> includes a scale field <NUM>, an index field <NUM>, and a base field <NUM> to be used in the generation of an address. The scale field <NUM> indicates scaling factor. The index field <NUM> specifies an index register to use. In some embodiments, the index field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. The base field <NUM> specifies a base register to use. In some embodiments, the base field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. In practice, the content of the scale field <NUM> allows for the scaling of the content of the index field <NUM> for memory address generation (e.g., for address generation that uses <NUM>scale * index + base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to <NUM>scale * index + base + displacement, index*scale+displacement, r/m + displacement, instruction pointer (RIP/EIP) + displacement, register + displacement, etc. The displacement may be a <NUM>-byte, <NUM>-byte, <NUM>-byte, etc. value. In some embodiments, a displacement field <NUM> provides this value. Additionally, in some embodiments, a displacement factor usage is encoded in the MOD field of the addressing field <NUM> that indicates a compressed displacement scheme for which a displacement value is calculated by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, the value of a b bit, and the input element size of the instruction. The displacement value is stored in the displacement field <NUM>.

In some embodiments, an immediate field <NUM> specifies an immediate for the instruction. An immediate may be encoded as a <NUM>-byte value, a <NUM>-byte value, a <NUM>-byte value, etc..

<FIG> illustrates embodiments of a first prefix <NUM>(A). In some embodiments, the first prefix <NUM>(A) is an embodiment of a REX prefix. Instructions that use this prefix may specify general purpose registers, <NUM>-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and/or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

Instructions using the first prefix <NUM>(A) may specify up to three registers using <NUM>-bit fields depending on the format: <NUM>) using the reg field <NUM> and the R/M field <NUM> of the Mod R/M byte <NUM>; <NUM>) using the Mod R/M byte <NUM> with the SIB byte <NUM> including using the reg field <NUM> and the base field <NUM> and index field <NUM>; or <NUM>) using the register field of an opcode.

In the first prefix <NUM>(A), bit positions <NUM>:<NUM> are set as <NUM>. Bit position <NUM> (W) can be used to determine the operand size, but may not solely determine operand width. As such, when W = <NUM>, the operand size is determined by a code segment descriptor (CS. D) and when W = <NUM>, the operand size is <NUM>-bit.

Note that the addition of another bit allows for <NUM> (<NUM><NUM>) registers to be addressed, whereas the MOD R/M reg field <NUM> and MOD R/M R/M field <NUM> alone can each only address <NUM> registers.

In the first prefix <NUM>(A), bit position <NUM> (R) may an extension of the MOD R/M reg field <NUM> and may be used to modify the ModR/M reg field <NUM> when that field encodes a general purpose register, a <NUM>-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when Mod R/M byte <NUM> specifies other registers or defines an extended opcode.

Bit position <NUM> (X) X bit may modify the SIB byte index field <NUM>.

Bit position B (B) B may modify the base in the Mod R/M R/M field <NUM> or the SIB byte base field <NUM>; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers <NUM>).

<FIG> illustrate embodiments of how the R, X, and B fields of the first prefix <NUM>(A) are used. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM><NUM> is not used for memory addressing. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM><NUM> is not used (register-register addressing). <FIG> illustrates R, X, and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> and the index field <NUM> and base field <NUM> when the SIB byte <NUM><NUM> being used for memory addressing. <FIG> illustrates B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> when a register is encoded in the opcode <NUM>.

<FIG> illustrate embodiments of a second prefix <NUM>(B). In some embodiments, the second prefix <NUM>(B) is an embodiment of a VEX prefix. The second prefix <NUM>(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector/SIMD registers <NUM>) to be longer than <NUM>-bits (e.g., <NUM>-bit and <NUM>-bit). The use of the second prefix <NUM>(B) provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A = A + B, which overwrites a source operand. The use of the second prefix <NUM>(B) enables operands to perform nondestructive operations such as A = B + C.

In some embodiments, the second prefix <NUM>(B) comes in two forms - a two-byte form and a three-byte form. The two-byte second prefix <NUM>(B) is used mainly for <NUM>-bit, scalar, and some <NUM>-bit instructions; while the three-byte second prefix <NUM>(B) provides a compact replacement of the first prefix <NUM>(A) and <NUM>-byte opcode instructions.

<FIG> illustrates embodiments of a two-byte form of the second prefix <NUM>(B). In one example, a format field <NUM> (byte <NUM><NUM>) contains the value C5H. In one example, byte <NUM> includes a "R" value in bit[<NUM>]. This value is the complement of the same value of the first prefix <NUM>(A). Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>] shown as vvvv may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the Mod R/M R/M field <NUM> to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the Mod R/M reg field <NUM> to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field <NUM> and the Mod R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate <NUM> are then used to encode the third source register operand.

<FIG> illustrates embodiments of a three-byte form of the second prefix <NUM>(B). in one example, a format field <NUM> (byte <NUM><NUM>) contains the value C4H. Byte <NUM><NUM> includes in bits[<NUM>:<NUM>] "R," "X," and "B" which are the complements of the same values of the first prefix <NUM>(A). Bits[<NUM>:<NUM>] of byte <NUM><NUM> (shown as mmmmm) include content to encode, as need, one or more implied leading opcode bytes. For example, <NUM> implies a 0FH leading opcode, <NUM> implies a 0F38H leading opcode, <NUM> implies a leading 0F3AH opcode, etc..

Bit[<NUM>] of byte <NUM><NUM> is used similar to W of the first prefix <NUM>(A) including helping to determine promotable operand sizes. Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field <NUM>, and the Mod R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate <NUM> are then used to encode the third source register operand.

<FIG> illustrates embodiments of a third prefix <NUM>(C). In some embodiments, the first prefix <NUM>(A) is an embodiment of an EVEX prefix. The third prefix <NUM>(C) is a four-byte prefix.

The third prefix <NUM>(C) can encode <NUM> vector registers (e.g., <NUM>-bit, <NUM>-bit, and <NUM>-bit registers) in <NUM>-bit mode. In some embodiments, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as <FIG>) or predication utilize this prefix. Opmask register allow for conditional processing or selection control. Opmask instructions, whose source/destination operands are opmask registers and treat the content of an opmask register as a single value, are encoded using the second prefix <NUM>(B).

The third prefix <NUM>(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with "load+op" semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support "suppress all exceptions" functionality, etc.).

The first byte of the third prefix <NUM>(C) is a format field <NUM> that has a value, in one example, of <NUM>. Subsequent bytes are referred to as payload bytes <NUM>-<NUM> and collectively form a <NUM>-bit value of P[<NUM>:<NUM>] providing specific capability in the form of one or more fields (detailed herein).

In some embodiments, P[<NUM>:<NUM>] of payload byte <NUM> are identical to the low two mmmmm bits. P[<NUM>:<NUM>] are reserved in some embodiments. Bit P[<NUM>] (R') allows access to the high <NUM> vector register set when combined with P[<NUM>] and the ModR/M reg field <NUM>. P[<NUM>] can also provide access to a high <NUM> vector register when SIB-type addressing is not needed. P[<NUM>:<NUM>] consist of an R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of <NUM> registers beyond the low <NUM> registers when combined with the ModR/M register field <NUM> and ModR/M R/M field <NUM>. P[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). P[<NUM>] in some embodiments is a fixed value of <NUM>. P[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

P[<NUM>] is similar to W of the first prefix <NUM>(A) and second prefix <NUM>(B) and may serve as an opcode extension bit or operand size promotion.

P[<NUM>:<NUM>] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers <NUM>). In one embodiment of the invention, the specific value aaa = <NUM> has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's content to directly specify the masking to be performed.

P[<NUM>] can be combined with P[<NUM>:<NUM>] to encode a second source vector register in a non-destructive source syntax which can access an upper <NUM> vector registers using P[<NUM>]. P[<NUM>] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/ rounding control specifier field (P[<NUM>:<NUM>]). P[<NUM>] indicates support for merging-writemasking (e.g., when set to <NUM>) or support for zeroing and merging-writemasking (e.g., when set to <NUM>).

Exemplary embodiments of encoding of registers in instructions using the third prefix <NUM>(C) are detailed in the following tables.

Program code may be applied to input instructions to perform the functions described herein and generate output information. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Em bodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using a first ISA compiler <NUM> to generate first ISA binary code <NUM> that may be natively executed by a processor with at least one first instruction set core <NUM>. The processor with at least one first ISA instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel® processor with at least one first ISA instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the first ISA instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one first ISA instruction set core, in order to achieve substantially the same result as a processor with at least one first ISA instruction set core. The first ISA compiler <NUM> represents a compiler that is operable to generate first ISA binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first ISA instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without a first ISA instruction set core <NUM>. The instruction converter <NUM> is used to convert the first ISA binary code <NUM> into code that may be natively executed by the processor without a first ISA instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first ISA instruction set processor or core to execute the first ISA binary code <NUM>.

References to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic.

Moreover, in the various embodiments described above, unless specifically noted otherwise, disjunctive language such as the phrase "at least one of A, B, or C" is intended to be understood to mean either A, B, or C, or any combination thereof (e.g., A, B, and/or C). As such, disjunctive language is not intended to, nor should it be understood to, imply that a given embodiment requires at least one of A, at least one of B, or at least one of C to each be present.

Claim 1:
An apparatus comprising:
decoder circuitry (<NUM>) to decode a single instruction (<NUM>), the single instruction (<NUM>) to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the source/destination operand comprises a plurality of <NUM>-bit bias terms, and wherein the opcode is to indicate that execution circuitry (<NUM>) is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using the <NUM>-bit bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and
execution circuitry (<NUM>) to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.