Patent Description:
Attempts have been made to mediate the effects of refresh operations on DRAM bandwidth. Known memory controllers adopt one of two processes for refreshing DRAM. In a first example the memory controller waits until no other accesses to the memory are pending, then the memory controller provides a refresh to the memory. These are called casual refreshes. In another example, when the memory controller has waited too long, and the memory is in critical need of a refresh, and the memory controller provides urgent refreshes. Each of the foregoing examples may result in memory transactions being stalled, consequently producing a penalty in memory performance.

<CIT> discloses a data processing system with a memory controller having a refresh logic circuit that generates refresh requests separate from normal read and write memory access requests, and an arbiter that arbitrates between normal read and write memory access requests stored in a command queue and the refresh requests generated by the refresh logic circuit. <CIT> discloses a memory controller having three sub-arbiters for different types of page statuses, and a final arbiter that selects between three sub-arbitration winners as well as a refresh operation from refresh logic that generates autorefresh commands periodically.

The invention provides a memory controller in accordance with claim <NUM>, a data processing system in accordance with claim <NUM>, and a method for managing refresh of a memory in a memory system in accordance with claim <NUM>.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word "coupled" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

As will be described below in one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory. The refresh logic circuit provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses. The ordering is based on the priority indicator.

In another form, a data processing system includes a memory accessing agent, a memory system, and a memory controller. The memory accessing agent provides memory access requests for a memory. The memory system is coupled to the memory accessing agent. The memory controller is coupled to the memory system and the memory accessing agent includes a command queue, an arbiter, and a final arbiter. The command queue stores memory access commands received from the memory accessing agent. The arbiter selectively picks memory accesses from the command queue according to a first type of access and a second type of access. Each type of access corresponds to a different page status of a bank in the memory. The final arbiter arbitrates based on input received from a refresh logic circuit. The refresh logic circuit generates a refresh command to the bank of the memory and provides a priority indicator to the refresh command. The value of the priority indicator is set according to a number of pending refreshes, to selectively order the refresh command with respect to a first type of access and a second type of access.

In yet another form, a method for managing refresh of a memory in a memory system via a memory controller. A plurality of memory access requests is received and stored in a command queue. The memory accesses requests are selectively picked from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and a second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. A refresh command is generated to a bank of the memory. A priority indicator is provided with the refresh command. The refresh command is selectively ordered with respect to memory access requests of the first type access and the second type access based on the priority indicator.

<FIG> illustrates in block diagram form a data processing system <NUM> according to some embodiments. Data processing system <NUM> includes generally a data processor <NUM> in the form of an accelerated processing unit (APU), a memory system <NUM>, a peripheral component interconnect express (PCIe) system <NUM>, a universal serial bus (USB) system <NUM>, and a disk drive <NUM>. Data processor <NUM> operates as the central processing unit (CPU) of data processing system <NUM> and provides various buses and interfaces useful in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connection to a PCIe link, a USB controller for connection to a USB network, and an interface to a Serial Advanced Technology Attachment (SATA) mass storage device.

Memory system <NUM> includes a memory channel <NUM> and a memory channel <NUM>. Memory channel <NUM> includes a set of dual inline memory modules (DIMMs) connected to a DDRx bus <NUM>, including representative DIMMs <NUM>, <NUM>, and <NUM> that in this example correspond to separate ranks. Likewise, memory channel <NUM> includes a set of DIMMs connected to a DDRx bus <NUM>, including representative DIMMs <NUM>, <NUM>, and <NUM>.

PCIe system <NUM> includes a PCIe switch <NUM> connected to the PCIe root complex in data processor <NUM>, a PCIe device <NUM>, a PCIe device <NUM>, and a PCIe device <NUM>. PCIe device <NUM> in turn is connected to a system basic input/output system (BIOS) memory <NUM>. System BIOS memory <NUM> can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), and the like.

USB system <NUM> includes a USB hub <NUM> connected to a USB master in data processor <NUM>, and representative USB devices <NUM>, <NUM>, and <NUM> each connected to USB hub <NUM>. USB devices <NUM>, <NUM>, and <NUM> could be devices such as a keyboard, a mouse, a flash EEPROM port, and the like.

Disk drive <NUM> is connected to data processor <NUM> over a SATA bus and provides mass storage for the operating system, application programs, application files, and the like.

Data processing system <NUM> is suitable for use in modem computing applications by providing a memory channel <NUM> and a memory channel <NUM>. Each of memory channels <NUM> and <NUM> can connect to state-of-the-art DDR memories such as DDR version four (DDR4), low power DDR4 (LPDDR4), graphics DDR version five (GDDR5), and high bandwidth memory (HBM), and can be adapted for future memory technologies. These memories provide high bus bandwidth and high speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptop computers, and also provide built-in thermal monitoring.

<FIG> illustrates in block diagram form an APU <NUM> suitable for use in data processing system <NUM> of <FIG>. APU <NUM> includes generally a central processing unit (CPU) core complex <NUM>, a graphics core <NUM>, a set of display engines <NUM>, a memory management hub <NUM>, a data fabric <NUM>, a set of peripheral controllers <NUM>, a set of peripheral bus controllers <NUM>, a system management unit (SMU) <NUM>, and a set of memory controllers <NUM>.

CPU core complex <NUM> includes a CPU core <NUM> and a CPU core <NUM>. In this example, CPU core complex <NUM> includes two CPU cores, but in other embodiments CPU core complex <NUM> can include an arbitrary number of CPU cores. Each of CPU cores <NUM> and <NUM> is bidirectionally connected to a system management network (SMN), which forms a control fabric, and to data fabric <NUM>, and is capable of providing memory access requests to data fabric <NUM>. Each of CPU cores <NUM> and <NUM> may be unitary cores, or may further be a core complex with two or more unitary cores sharing certain resources such as caches.

Graphics core <NUM> is a high performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, and the like in a highly integrated and parallel fashion. Graphics core <NUM> is bidirectionally connected to the SMN and to data fabric <NUM>, and is capable of providing memory access requests to data fabric <NUM>. In this regard, APU <NUM> may either support a unified memory architecture in which CPU core complex <NUM> and graphics core <NUM> share the same memory space, or a memory architecture in which CPU core complex <NUM> and graphics core <NUM> share a portion of the memory space, while graphics core <NUM> also uses a private graphics memory not accessible by CPU core complex <NUM>.

Display engines <NUM> render and rasterize objects generated by graphics core <NUM> for display on a monitor. Graphics core <NUM> and display engines <NUM> are bidirectionally connected to a common memory management hub <NUM> for uniform translation into appropriate addresses in memory system <NUM>, and memory management hub <NUM> is bidirectionally connected to data fabric <NUM> for generating such memory accesses and receiving read data returned from the memory system.

Data fabric <NUM> includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agent and memory controllers <NUM>. It also includes a system memory map, defined by BIOS, for determining destinations of memory accesses based on the system configuration, as well as buffers for each virtual connection.

Peripheral controllers <NUM> include a USB controller <NUM> and a SATA interface controller <NUM>, each of which is bidirectionally connected to a system hub <NUM> and to the SMN bus. These two controllers are merely exemplary of peripheral controllers that may be used in APU <NUM>.

Peripheral bus controllers <NUM> include a system controller or "Southbridge" (SB) <NUM> and a PCIe controller <NUM>, each of which is bidirectionally connected to an input/output (I/O) hub <NUM> and to the SMN bus. I/O hub <NUM> is also bidirectionally connected to system hub <NUM> and to data fabric <NUM>. Thus, for example a CPU core can program registers in USB controller <NUM>, SATA interface controller <NUM>, SB <NUM>, or PCIe controller <NUM> through accesses that data fabric <NUM> routes through I/O hub <NUM>.

SMU <NUM> is a local controller that controls the operation of the resources on APU <NUM> and synchronizes communication among them. SMU <NUM> manages power-up sequencing of the various processors on APU <NUM> and controls multiple off-chip devices via reset, enable and other signals. SMU <NUM> includes one or more clock sources not shown in <FIG>, such as a phase locked loop (PLL), to provide clock signals for each of the components of APU <NUM>. SMU <NUM> also manages power for the various processors and other functional blocks, and may receive measured power consumption values from CPU cores <NUM> and <NUM> and graphics core <NUM> to determine appropriate power states.

APU <NUM> also implements various system monitoring and power saving functions. In particular one system monitoring function is thermal monitoring. For example, if APU <NUM> becomes hot, then SMU <NUM> can reduce the frequency and voltage of CPU cores <NUM> and <NUM> and/or graphics core <NUM>. If APU <NUM> becomes too hot, then it can be shut down entirely. Thermal events can also be received from external sensors by SMU <NUM> via the SMN bus, and SMU <NUM> can reduce the clock frequency and/or power supply voltage in response.

<FIG> illustrates in block diagram form a memory controller <NUM> and an associated physical interface (PHY) <NUM> suitable for use in APU <NUM> of <FIG> according to some embodiments. Memory controller <NUM> includes a memory channel <NUM> and a power engine <NUM>. Memory channel <NUM> includes a host interface <NUM>, a memory channel controller <NUM>, and a physical interface <NUM>. Host interface <NUM> bidirectionally connects memory channel controller <NUM> to data fabric <NUM> over a scalable data port (SDP). Physical interface <NUM> bidirectionally connects memory channel controller <NUM> to PHY <NUM> over a bus that conforms to the DDR-PHY Interface Specification (DFI). Power engine <NUM> is bidirectionally connected to SMU <NUM> over the SMN bus, to PHY <NUM> over the Advanced Peripheral Bus (APB), and is also bidirectionally connected to memory channel controller <NUM>. PHY <NUM> has a bidirectional connection to a memory channel such as memory channel <NUM> or memory channel <NUM> of <FIG>. Memory controller <NUM> is an instantiation of a memory controller for a single memory channel using a single memory channel controller <NUM>, and has a power engine <NUM> to control operation of memory channel controller <NUM> in a manner that will be described further below.

<FIG> illustrates in block diagram form another memory controller <NUM> and associated PHYs <NUM> and <NUM> suitable for use in APU <NUM> of <FIG> according to some embodiments. Memory controller <NUM> includes memory channels <NUM> and <NUM> and a power engine <NUM>. Memory channel <NUM> includes a host interface <NUM>, a memory channel controller <NUM>, and a physical interface <NUM>. Host interface <NUM> bidirectionally connects memory channel controller <NUM> to data fabric <NUM> over an SDP. Physical interface <NUM> bidirectionally connects memory channel controller <NUM> to PHY <NUM>, and conforms to the DFI Specification. Memory channel <NUM> includes a host interface <NUM>, a memory channel controller <NUM>, and a physical interface <NUM>. Host interface <NUM> bidirectionally connects memory channel controller <NUM> to data fabric <NUM> over another SDP. Physical interface <NUM> bidirectionally connects memory channel controller <NUM> to PHY <NUM>, and conforms to the DFI Specification. Power engine <NUM> is bidirectionally connected to SMU <NUM> over the SMN bus, to PHYs <NUM> and <NUM> over the APB, and is also bidirectionally connected to memory channel controllers <NUM> and <NUM>. PHY <NUM> has a bidirectional connection to a memory channel such as memory channel <NUM> of <FIG>. PHY <NUM> has a bidirectional connection to a memory channel such as memory channel <NUM> of <FIG>. Memory controller <NUM> is an instantiation of a memory controller having two memory channel controllers and uses a shared power engine <NUM> to control operation of both memory channel controller <NUM> and memory channel controller <NUM> in a manner that will be described further below.

<FIG> illustrates in block diagram form a memory controller <NUM> according to some embodiments. Memory controller <NUM> includes a memory channel controller <NUM> and a power controller <NUM>. Memory channel controller <NUM> includes an interface <NUM>, a queue <NUM>, a command queue <NUM>, an address generator <NUM>, a content addressable memory (CAM) <NUM>, a replay queue <NUM>, a refresh logic circuit block <NUM>, a timing block <NUM>, a page table <NUM>, an arbiter <NUM>, an error correction code (ECC) check block <NUM>, an ECC generation block <NUM>, and a data buffer (DB) <NUM>.

Interface <NUM> has a first bidirectional connection to data fabric <NUM> over an external bus, and has an output. In memory controller <NUM>, this external bus is compatible with the advanced extensible interface version four specified by ARM Holdings, PLC of Cambridge, England, known as "AXI4", but can be other types of interfaces in other embodiments. Interface <NUM> translates memory access requests from a first clock domain known as the FCLK (or MEMCLK) domain to a second clock domain internal to memory controller <NUM> known as the UCLK domain. Similarly, queue <NUM> provides memory accesses from the UCLK domain to the DFICLK domain associated with the DFI interface.

Address generator <NUM> decodes addresses of memory access requests received from data fabric <NUM> over the AXI4 bus. The memory access requests include access addresses in the physical address space represented as a normalized address. Address generator <NUM> converts the normalized addresses into a format that can be used to address the actual memory devices in memory system <NUM>, as well as to efficiently schedule related accesses. This format includes a region identifier that associates the memory access request with a particular rank, a row address, a column address, a bank address, and a bank group. On startup, the system BIOS queries the memory devices in memory system <NUM> to determine their size and configuration, and programs a set of configuration registers associated with address generator <NUM>. Address generator <NUM> uses the configuration stored in the configuration registers to translate the normalized addresses into the appropriate format. Command queue <NUM> is a queue of memory access requests received from the memory accessing agents in data processing system <NUM>, such as CPU cores <NUM> and <NUM> and graphics core <NUM>. Command queue <NUM> stores the address fields decoded by address generator <NUM> as well other address information that allows arbiter <NUM> to select memory accesses efficiently, including access type and quality of service (QoS) identifiers. CAM <NUM> includes information to enforce ordering rules, such as write after write (WAW) and read after write (RAW) ordering rules.

Replay queue <NUM> is a temporary queue for storing memory accesses picked by arbiter <NUM> that are awaiting responses, such as address and command parity responses, write cyclic redundancy check (CRC) responses for DDR4 DRAM or write and read CRC responses for GDDR5 DRAM. Replay queue <NUM> accesses ECC check block <NUM> to determine whether the returned ECC is correct or indicates an error. Replay queue <NUM> allows the accesses to be replayed in the case of a parity or CRC error of one of these cycles.

Refresh logic circuit <NUM> includes state machines for various powerdown, refresh, and termination resistance (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from memory accessing agents. For example, if a memory rank is in precharge powerdown, it must be periodically awakened to run refresh cycles. Refresh logic circuit <NUM> generates auto-refresh commands periodically to prevent data errors caused by leaking of charge off storage capacitors of memory cells in DRAM chips. In addition, refresh logic circuit <NUM> periodically calibrates ZQ to prevent mismatch in on-die termination resistance due to thermal changes in the system. Refresh logic circuit <NUM> also decides when to put DRAM devices in different power down modes.

Arbiter <NUM> is bidirectionally connected to command queue <NUM> and is the heart of memory channel controller <NUM>. It improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus. Arbiter <NUM> uses timing block <NUM> to enforce proper timing relationships by determining whether certain accesses in command queue <NUM> are eligible for issuance based on DRAM timing parameters. For example, each DRAM has a minimum specified time between activate commands to the same bank, known as "tRC". Timing block <NUM> maintains a set of counters that determine eligibility based on this and other timing parameters specified in the JEDEC specification, and is bidirectionally connected to replay queue <NUM>. Page table <NUM> maintains state information about active pages in each bank and rank of the memory channel for arbiter <NUM>, and is bidirectionally connected to replay queue <NUM>.

In response to write memory access requests received from interface <NUM>, ECC generation block <NUM> computes an ECC according to the write data. DB <NUM> stores the write data and ECC for received memory access requests. It outputs the combined write data/ECC to queue <NUM> when arbiter <NUM> picks the corresponding write access for dispatch to the memory channel.

Power controller <NUM> includes an interface <NUM> to an advanced extensible interface, version one (AXI), an APB interface <NUM>, and a power engine <NUM>. Interface <NUM> has a first bidirectional connection to the SMN, which includes an input for receiving an event signal labeled "EVENT_n" shown separately in <FIG>, and an output. APB interface <NUM> has an input connected to the output of interface <NUM>, and an output for connection to a PHY over an APB. Power engine <NUM> has an input connected to the output of interface <NUM>, and an output connected to an input of queue <NUM>. Power engine <NUM> includes a set of configuration registers <NUM>, a microcontroller (µC) <NUM>, a self refresh controller (SLFREF/PE) <NUM>, and a reliable read/write training engine (RRW/TE) <NUM>. Configuration registers <NUM> are programmed over the AXI bus, and store configuration information to control the operation of various blocks in memory controller <NUM>. Accordingly, configuration registers <NUM> have outputs connected to these blocks that are not shown in detail in <FIG>. Self refresh controller <NUM> is an engine that allows the manual generation of refreshes in addition to the automatic generation of refreshes by refresh logic circuit <NUM>. Reliable read/write training engine <NUM> provides a continuous memory access stream to memory or I/O devices for such purposes as DDR interface read latency training and loopback testing.

Memory channel controller <NUM> includes circuitry that allows it to pick memory accesses for dispatch to the associated memory channel. In order to make the desired arbitration decisions, address generator <NUM> decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue <NUM> stores the predecoded information. Configuration registers <NUM> store configuration information to determine how address generator <NUM> decodes the received address information. Arbiter <NUM> uses the decoded address information, timing eligibility information indicated by timing block <NUM>, and active page information indicated by page table <NUM> to efficiently schedule memory accesses while observing other criteria such as QoS requirements. For example, arbiter <NUM> implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank. In particular during normal operation, arbiter <NUM> may decide to keeps pages open in different banks until they are required to be precharged prior to selecting a different page.

<FIG> illustrates a block diagram of a portion <NUM> of memory controller <NUM> of <FIG> according to some embodiments. Portion <NUM> includes arbiter <NUM>, refresh logic circuit <NUM>, and a set of control circuits <NUM> associated with the operation of arbiter <NUM>. Arbiter <NUM> includes a set of sub-arbiters <NUM> and a final arbiter <NUM>. Sub-arbiters <NUM> include a sub-arbiter <NUM>, a sub-arbiter <NUM>, and a sub-arbiter <NUM>. Sub-arbiter <NUM> includes a page hit arbiter <NUM> labeled "PH ARB", and an output register <NUM>. Page hit arbiter <NUM> has a first input connected to command queue <NUM>, a second input, and an output. Register <NUM> has a data input connected to the output of page hit arbiter <NUM>, a clock input for receiving the UCLK signal, and an output. Sub-arbiter <NUM> includes a page conflict arbiter <NUM> labeled "PC ARB", and an output register <NUM>. Page conflict arbiter <NUM> has a first input connected to command queue <NUM>, a second input, and an output. Register <NUM> has a data input connected to the output of page conflict arbiter <NUM>, a clock input for receiving the UCLK signal, and an output. Sub-arbiter <NUM> includes a page miss arbiter <NUM> labeled "PM ARB", and an output register <NUM>. Page miss arbiter <NUM> has a first input connected to command queue <NUM>, a second input, and an output. Register <NUM> has a data input connected to the output of page miss arbiter <NUM>, a clock input for receiving the UCLK signal, and an output. Final arbiter <NUM> has a first input connected to the output of page close predictor <NUM>, a second input connected to the output of refresh logic circuit <NUM>, a third input connected to the output of output register <NUM>, a fourth input connected to the output of output register <NUM>, a fifth input connected to the output of register <NUM>, and a first output for providing an arbitration winner to queue <NUM>.

The output of refresh logic circuit <NUM> provides a priority indicator with an associated refresh command. Refresh logic circuit <NUM> also has an input connected to the output of final arbiter <NUM>.

Control circuits <NUM> include timing block <NUM> and page table <NUM> as previously described with respect to <FIG>, and a page close predictor <NUM>. Timing block <NUM> has an input and an output connected to the first inputs of page hit arbiter <NUM>, page conflict arbiter <NUM>, and page miss arbiter <NUM>. Page table <NUM> has an input connected to an output of replay queue <NUM>, an output connected to an input of replay queue <NUM>, an output connected to the input of command queue <NUM>, an output connected to the input of timing block <NUM>, and an output connected to the input of page close predictor <NUM>. Page close predictor <NUM> has an input connected to one output of page table <NUM>, an input connected to the output of output register <NUM>, and an output connected to the second input of final arbiter <NUM>.

In operation, arbiter <NUM> selects memory access requests (commands) from command queue <NUM> and refresh logic <NUM> by taking into account the page status of each entry and the priority of each refresh command. The memory access priority is based on the intermediate refresh interval, but can be altered based on the page status of the memory access request and on a priority indicator status of the refresh command. Arbiter <NUM> includes three sub-arbiters that operate in parallel with refresh logic circuit <NUM> to address the mismatch between the processing and transmission limits of existing integrated circuit technology. The winners of the respective sub-arbitrations are presented to final arbiter <NUM> along with a refresh command having a priority indicator. Final arbiter <NUM> selects between these three sub-arbitration winners and a refresh operation from refresh logic <NUM> to output to queue <NUM>.

Each of page hit arbiter <NUM>, page conflict arbiter <NUM>, and page miss arbiter <NUM> has an input connected to the output of timing block <NUM> to determine timing eligibility of commands in command queue <NUM> that fall into these respective categories. Timing block <NUM> includes an array of binary counters that count durations related to the particular operations for each bank in each rank. The number of timers needed to determine the status depends on the timing parameter, the number of banks for the given memory type, and the number of ranks supported by the system on a given memory channel. The number of timing parameters that are implemented in turn depends on the type of memory implemented in the system. For example, GDDR5 memories require more timers to comply with more timing parameters than other DDRx memory types. By including an array of generic timers implemented as binary counters, timing block <NUM> can be scaled and reused for different memory types.

A page hit is a read or write cycle to an open page. Page hit arbiter <NUM> arbitrates between accesses in command queue <NUM> to open pages. A page conflict is an access to one row in a bank when another row in the bank is currently activated. Page conflict arbiter <NUM> arbitrates between accesses in command queue <NUM> to pages that conflict with the page that is currently open in the corresponding bank and rank. Page conflict arbiter <NUM> selects a sub-arbitration winner that causes the issuance of a precharge command. A page miss is an access to a bank that is in the precharged state. Page miss arbiter <NUM> arbitrates between accesses in command queue <NUM> to precharged memory banks. Arbiter <NUM> selectively picks accesses from command queue <NUM> according to the type of memory access. Each of page hit arbiter <NUM>, page conflict arbiter <NUM>, and page miss arbiter <NUM> outputs a first type of accesses or a second type of accesses.

The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. More specifically, page hit arbiter <NUM> outputs a first type access. Page conflict arbiter <NUM> and page miss arbiter <NUM> each output a second type access. After determining the relative priority among the three sub-arbitration winners, final arbiter <NUM> then determines whether the sub-arbitration winners conflict with the refresh command (i.e. whether they are directed to the same bank and rank). When there are no such conflicts and the refresh time interval is met, then final arbiter <NUM> selects the refresh command. When there are conflicts, then final arbiter <NUM> complies with the following rules. When the priority indicator for the refresh command is a first priority status (intermediate priority) and page hit arbiter <NUM> selects a pending page hit, then final arbiter <NUM> selects the access indicated by page hit arbiter <NUM>. When the priority indicator for the refresh command is a second priority status (urgent priority) and the sub-arbitration winner is from page hit arbiter <NUM>, final arbiter <NUM> selects the access indicated by refresh logic circuit <NUM>, thereby prioritizing the refresh command to execute instead of the page hit. In some cases refresh logic circuit <NUM> elevates the priority status of the refresh command to an urgent status, based on an urgent refresh count threshold.

Refresh logic circuit <NUM> provides a priority indicator with the refresh command to specify a priority status of the refresh command to final arbiter <NUM>. Refresh logic circuit <NUM> sets the value of the priority indicator according to a number of pending refreshes. Refresh logic circuit <NUM> assigns to the priority indicator a first priority status or a second priority status. Refresh logic <NUM> evenly spreads out a per bank refresh cycle based on a predetermined time period. The predetermined time period is an intermediate refresh interval that is a timing dependent refresh interval, that is based on refresh time interval (tREFI) and the number of memory banks that are assigned to the memory controller. The trigger of the intermediate refresh is dependent on a threshold of owed refreshes.

Within refresh logic circuit <NUM>, priority is initially set based on the number of pending refreshes. In general, refresh logic circuit <NUM> elevates the refresh command to execute between the first type of accesses and the second type of accesses. More specifically, final arbiter <NUM> sends the refresh command when there is no page hit transaction to the target memory banks. In response to the second priority status, final arbiter <NUM> elevates the refresh command above the first type of accesses and the second type of accesses. Thereby, in some cases, final arbiter <NUM> prioritizes the refresh command to execute instead of pending requests to the memory bank.

By using sub-arbiters for page hits, page conflicts, and page misses, arbiter <NUM> can selectively pick accesses based on sub-arbitrations, and categorize them as a first type of access and a second type of access. Final arbiter <NUM> can select refresh commands based on input received from refresh logic circuit <NUM> which generates the refresh command to bank <NUM> of memory <NUM> based on the number of pending refreshes. Final arbiter <NUM> orders the refresh command with respect to a first type of access and a second type of access. The intermediate refresh time interval is a time period that is less than tREFI. Ordering the refresh commands based on the types of memory accesses and according to the number of pending refreshes allows refresh commands to be sent at a higher frequency than the refresh time interval and in a sufficient amount of time to avoid penalties due to urgent refreshes.

In other embodiments, arbiter <NUM> could include a different number of sub-arbiters. For example, arbiter <NUM> could include two sub-arbiters, one arbiter for page hits and another arbiter for page conflicts and page misses. In this case, arbiter <NUM> is able to access page types based on the two sub-arbitrations.

In some embodiments, refresh logic circuit <NUM> generates the refresh command per bank in one tREFI so that during high workloads when some banks are refreshing, other transactions are utilizing other banks with memory <NUM> to more fully take advantage of bus bandwidth of memory <NUM>. In general, to send out the intermediate refresh command during transactions final arbiter <NUM> asserts an urgent refresh status to the intermediate refresh command having a first or second priority status when a predetermined clock cycle expires and the page of the bank is closed. This allows the intermediate refresh per bank command to be generated to memory <NUM> evenly and consistently. Final arbiter <NUM> arbitrates an intermediate refresh per bank command to generate to the bank between page hits and page misses. Elevating the priority of the intermediate refresh per bank command to generate between page hits and page misses further saves memory <NUM> from penalties that derive from closing the pages. Advantageously, intermediate refresh per bank command alleviates the clock cycles required between opening a row of memory and accessing columns within the row (trcd), and alleviates the clock cycles required between issuing the precharge command and opening the next row (trp).

In some embodiments, the arbiter <NUM> relegates the priority of the memory banks using a priority indicator. In response to simultaneously receiving a refresh command to at least two memory banks with an equivalent priority indicator, arbiter <NUM> relegates the memory bank that is a most recent recipient of the refresh command below the bank of memory that is the least recent recipient of the refresh command. In response to receiving an urgent refresh command from refresh logic circuit <NUM>, arbiter <NUM> blocks the activation of a row of the corresponding bank so that no new activity is started in the bank. After receiving an urgent refresh command for the bank, arbiter <NUM> sends the refresh request to the bank in two conditions. First, arbiter <NUM> sends the urgent refresh command to the bank right away if the refresh timing was met at the same time as the urgent refresh command was generated. Second, if the refresh timing was not met at the same time that the urgent refresh command was generated, arbiter <NUM> waits for the refresh timing to be met, and then sends a refresh request to the corresponding bank.

<FIG> illustrates a block diagram of a refresh logic circuit <NUM> that may be used for refresh logic circuit <NUM> of <FIG> and <FIG> according to some embodiments. Refresh logic circuit <NUM> includes generally a refresh internal timer <NUM>, a per-bank timer array <NUM>, a pending refresh queue <NUM>, an owed refresh counter <NUM>, a first comparator <NUM>, and a second comparator <NUM>.

Refresh internal timer <NUM> has an input connected to a clock source and an output for providing an incremental count to owed refresh counter <NUM>. Per-bank timer array <NUM> has an input for receiving a clock signal, and an output for providing a per-bank refresh to pending refresh queue <NUM>. Pending refresh queue <NUM> has a first input connected to per-bank timer array <NUM>, a second input, and an output for providing the refresh command to final arbiter <NUM>. Owed refresh counter <NUM> has a first input labeled "INC", a second input labeled "DEC" connected to the output of final arbiter <NUM>, and an output. The output of owed refresh counter <NUM> provides an owed refresh count to first comparator <NUM> and second comparator <NUM>. First comparator <NUM> also includes a second input for receiving a programmable urgent refresh limit, and an output for providing a priority indicator to the refresh command. Second comparator <NUM> also includes a second input for receiving a programmable intermediate refresh limit, and an output labeled "URGENT" for providing a priority indicator to final arbiter <NUM> with the refresh command signal. Final arbiter <NUM> provides a "refresh sent" signal to pending refresh queue <NUM> and owed refresh counter <NUM> to track the number of pending refreshes.

In operation, refresh logic circuit <NUM> receives a clock signal for tracking tREFI. Refresh logic circuit <NUM> determines the intermediate refresh time interval based on tREFI and provides a refresh command based on the clock signal and the total number of banks assigned to the memory controller. Each cycle an intermediate time period elapses without a refresh sent, refresh timer interval timer <NUM> signals to increment owed refresh counter <NUM>. Per-bank timer array <NUM> receives the clock signal and provides a refresh command to pending refresh queue <NUM> that corresponds to a respective memory bank. Pending refresh queue <NUM> provides the refresh command and priority indicator to final arbiter <NUM>. Refresh logic circuit <NUM> sets the value of the priority indicator according to a number of pending refreshes. First comparator <NUM> compares the number of owed refreshes to the urgent refresh limit and elevates the priority indicator for a pending refresh command when owed refresh counter <NUM> is above the urgent refresh limit. Second comparator <NUM> compares the number of owed refreshes to the intermediate refresh limit and sets the priority indicator to a first priority status when owed refresh counter <NUM> is above an intermediate refresh count threshold.

In some embodiments, refresh logic circuit <NUM> generates per two bank refresh commands. Refresh logic circuit <NUM> elevates a priority indicator for a pending refresh command for the paired bank when the priority indicator is a first priority status and a refresh timer is above a refresh timing interval. Accordingly, when one of the paired banks are page closed and the intermediate refresh interval has elapsed, the priority indicator is elevated to urgent refresh status for both paired banks. In response to pages being open in the target banks, final arbiter <NUM> precharges both banks.

By selecting indicating intermediate priority for per-bank refresh commands, refresh logic circuit <NUM> allows arbiter <NUM> to send most refreshes in time to avoid latency penalties due to urgent refreshes. Further, memory bandwidth is increased thereby enabling improved processor performance. In one example memory bandwidth utilization is increased by approximately <NUM>% for double data rate type six synchronous graphics random-access memory (GDDR6) when intermediate refresh per bank is used in comparison to when only a casual or urgent refresh per bank scheme is utilized.

The circuits of <FIG>, <FIG>, and <FIG> may be implemented with various combinations of hardware and software. For example, the hardware circuitry may include priority encoders, finite state machines, programmable logic arrays (PLAs), and the like, arbiter <NUM> could be implemented with a microcontroller executing stored program instructions to evaluate the relative timing eligibility of the pending commands. In this case some of the instructions may be stored in a non-transitory computer memory or computer readable storage medium for execution by the microcontroller. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid-state storage devices such as Flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.

APU <NUM> of <FIG> or memory controller <NUM> of <FIG> or any portions thereof, such as arbiter <NUM>, may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

Claim 1:
A memory controller (<NUM>), comprising:
a command queue (<NUM>) for receiving and storing memory access requests for a memory (<NUM>);
an arbiter (<NUM>) for selectively picking accesses from the command queue (<NUM>) and categorizing them as a first type of accesses or a second type of accesses, wherein the first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory;
a refresh logic circuit (<NUM>) for generating a refresh command to a bank of the memory (<NUM>), and providing a priority indicator with the refresh command whose value is set according to a number of pending per-bank refreshes, wherein the refresh logic circuit (<NUM>) assigns the priority indicator one of a first priority status and a second priority status; and
a final arbiter (<NUM>) for selectively ordering the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator, wherein the final arbiter prioritizes the refresh command to execute in an order between the first type of accesses and the second type of accesses when the priority indicator is the first priority status.