Patent Description:
The phase interpolator is a device for adjusting the phase of a circuit clock and has been widely used in the related field. The phase interpolator is a device capable of mixing two input periodic clocks with the same frequency and different phases in proportion to generate an output clock signal with the same frequency and the phase between the two input periodic clocks. In practice, a requirement will be imposed that gears of the phase interpolator need to be switched.

In the prior art, the conventional phase interpolator is a current steering phase interpolator. A clock at the middle phase of the two IQ clocks is obtained by selecting different current weights of two adjacent IQ clocks signals in the circuit, as shown in <FIG>. In a phase diagram representing the conventional phase interpolator shown in <FIG>, a1 and a2 refer to weights of two input phases, wherein ideal weighting factors a1 and a2 are indicated by dashed lines, and conventional weighting factors a1 and a2 are indicated by solid lines. <FIG> shows a relationship between the weighting factors a1 and a2 of the conventional phase interpolator and the phase angle ϕ. When the above-mentioned circuit is applied to a high-speed circuit, due to the fact that all of the circuits are driven by current, larger current is needed for the fast switch of signals at a high speed; in the meantime, only when an input signal is preferably a sinusoidal signal can a better result be obtained, and the cost is relatively high.

In addition, <CIT> describes an AC-coupling phase interpolator and DLL using the same.

In <CIT> is disclosed a duty cycle correction circuit for correcting the duty cycle.

Given that the foregoing problems exist in the prior art, the present invention provides a phase interpolator.

The technical solution is as follows:
A phase interpolator, comprising:.

Preferably, wherein the phase interpolator further comprises a low-pass filter circuit, an input end of the low-pass filter circuit is connected to an output end of the phase adjusting circuit, the low-pass filter circuit is configured to filter a high-frequency signal of the interpolation signal.

Preferably, wherein the phase interpolator further comprises a shaping circuit, an input end of the shaping circuit is connected to an output end of the low-pass filter circuit, the shaping circuit is configured to shape the interpolation signal output by the low-pass filter circuit, so as to output a required interpolation signal.

Preferably, both the first MOS transistor and the first switch transistor are P-type MOS transistors.

Preferably, both the second MOS transistor and the second switch transistor are N-type MOS transistors.

By adopting the above-mentioned technical solutions, the present invention has the beneficial effects that a phase interpolator is disclosed, by using a first phase adjustment module and a second phase adjustment module, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present disclosure, and, together with the description, serve to explain the principles of the present invention.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including" or "has" and/or "having" when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, "around", "about" or "approximately" shall generally mean within <NUM> percent, preferably within <NUM> percent, and more preferably within <NUM> percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term "around", "about" or "approximately" can be inferred if not expressly stated.

As used herein, the term "plurality" means a number greater than one.

Hereinafter, certain exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

In the prior art, the conventional phase interpolator is a current steering phase interpolator. A clock at the middle phase of the two IQ clocks is obtained by selecting different current weights of two adjacent IQ clocks signals in the circuit, as shown in <FIG>. As shown in <FIG>, when the above-mentioned circuit is applied to a high-speed circuit, due to the fact that all of the circuits are driven by current, larger current is needed for the fast switch of signals at a high speed; in the meantime, only when an input signal is preferably a sinusoidal signal can a better result be obtained, and the cost is relatively high.

Given that the foregoing problems exist in the prior art, the present invention provides a phase interpolator. With reference to <FIG>, the phase interpolator comprises:.

By adopting the above-mentioned technical solution, a phase interpolator is disclosed, comprising a phase adjusting circuit <NUM>. The phase adjusting circuit <NUM> consists of a first phase adjusting module <NUM> and a second phase adjusting module <NUM>.

By using the first phase adjustment module <NUM> and the second phase adjustment module <NUM>, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

In a preferred embodiment, the phase interpolator further comprises a low-pass filter circuit <NUM>, an input end of the low-pass filter circuit <NUM> is connected to an output end of the phase adjusting circuit <NUM>, the low-pass filter circuit <NUM> is configured to filter a high-frequency signal of the interpolation signal; and
the phase interpolator further comprises a shaping circuit <NUM>, an input end of the shaping circuit <NUM> is connected to an output end of the low-pass filter circuit <NUM>, the shaping circuit <NUM> is configured to shape the interpolation signal output by the low-pass filter circuit <NUM>, so as to output a required interpolation signal.

In particular, as shown in <FIG>, by using a first phase adjustment module <NUM> and a second phase adjustment module <NUM>, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal. Filter, by the low-pass filter circuit <NUM>, a high-frequency signal of the interpolation signal. The low-pass filter circuit <NUM> may consist of a first capacitor C1 and a third resistor R3, wherein the third resistor R3 is connected to the output end of the phase adjusting circuit <NUM>, and the first capacitor C1 is connected between the third resistor R3 and the ground GND. Shape, by the shaping circuit <NUM>, the interpolation signal output by the low-pass filter circuit <NUM>, so as to output a required interpolation signal. The shaping circuit <NUM> may consist of a second capacitor C2 and a shaping circuit <NUM>, wherein the second capacitor C2 is connected in series with the shaping circuit <NUM>, and is connected between the third resistor R3 and the output end of the phase adjusting circuit <NUM>. In this way, phase adjustment is achieved, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

Each of the first phase adjusting module <NUM> and the second phase adjusting module <NUM> comprises:.

In particular, as shown in <FIG>, circuit diagrams of the first phase adjusting module <NUM> and the second phase adjusting module <NUM> are symmetrically distributed. The circuit diagrams comprise the signal input end Input, the signal output end Output, the first MOS transistor M1, the first adjusting module A1, the second MOS transistor M2, the second adjusting module A2, wherein the first MOS transistor M1 is a P-type MOS transistor, and the second MOS transistor M2 is a N-type MOS transistor.

Furthermore, by adjusting the first adjusting module A1 and the second adjusting module A2, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

The first adjusting module A1 comprises a plurality of first adjusting circuits A10, each of which is connected between the first node Q1 and the signal output end Output;
each of the plurality of first adjusting circuits A10 comprises:.

In particular, as shown in <FIG>, the first adjusting module A1 comprises a plurality of first adjusting circuits A10, and each of the plurality of first adjusting circuits A10 comprises the first switch transistor T1 and the first resistor R1, the first switch transistor T1 is a P-type MOS transistor. Voltage weights of the first adjusting module A1 can be adjusted by selecting different resistance values of the first resistor R1 through the first switch transistor T1, so as to achieve the purpose of phase adjustment.

Furthermore, by adjusting the first switch transistor T1 of the first adjusting module A1, and selecting different resistance values of the first resistor R1, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

The second adjusting module A2 comprises a plurality of second adjusting circuits A20, each of which is connected between the second node Q2 and the signal output end Output;
each of the plurality of second adjusting circuits A2 comprises:.

In particular, as shown in <FIG>, the second adjusting module A2 comprises a plurality of second adjusting circuits A20, and each of the plurality of second adjusting circuits A20 comprises the second switch transistor T2 and the second resistor R2, and the second switch transistor T2 is a N-type MOS transistor. Voltage weights of the second adjusting module A2 can be adjusted by selecting different resistance values of the second resistor R2 through the second switch transistor T2, so as to achieve the purpose of phase adjustment.

Furthermore, by adjusting the second switch transistor T2 of the second adjusting module A2, and selecting different resistance values of the second resistor R2, a first clock signal and a second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation signal with the same frequency and the phase between the first clock signal and the second clock signal so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

Furthermore, in a further preferred embodiment, as shown in <FIG>, each of the first phase adjusting module <NUM> and the second phase adjusting module <NUM> comprises:.

In the above-mentioned technical solution, as shown in <FIG>, circuit diagrams of the first phase adjusting module <NUM> and the second phase adjusting module <NUM> are symmetrically distributed. The circuit diagrams comprise the signal input end Input, the signal output end Output, the first MOS transistor M1, the first adjusting module A1, the second MOS transistor M2, the second adjusting module A2, wherein the first MOS transistor M1 is a P-type MOS transistor, and the second MOS transistor M2 is a N-type MOS transistor.

In particular, as shown in <FIG>, the first adjusting module A1 comprises a plurality of third adjusting circuits A10, each of which is connected between the third node Q3 and VCC;
each of the plurality of first adjusting circuits A10 comprises:.

In particular, as shown in <FIG>, the first adjusting module A1 comprises a plurality of first adjusting circuits A10, and each of the plurality of first adjusting circuits A10 comprises the first switch transistor T1 and the first resistor R1, and the first switch transistor T1 is a P-type MOS transistor. Voltage weights of the first adjusting module A1 can be adjusted by selecting different resistance values of the first resistor R1 through the first switch transistor T1, so as to achieve the purpose of phase adjustment.

In particular, as shown in <FIG>, the second adjusting module A2 comprises a plurality of second adjusting circuits A20, each of which is connected between the fourth node Q4 and the ground (GND);
each of the plurality of second adjusting circuits A2 comprises:.

In the above-mentioned technical solution, as shown in <FIG>, the second adjusting module A2 comprises a plurality of second adjusting circuits A20, and each of the plurality of second adjusting circuits A20 comprises the second switch transistor T2 and the second resistor R2, and the second switch transistor T2 is a N-type MOS transistor. Voltage weights of the second adjusting module A2 can be adjusted by selecting different resistance values of the second resistor R2 through the second switch transistor T2, so as to achieve the purpose of phase adjustment.

Claim 1:
A phase interpolator, comprising:
a phase adjusting circuit (<NUM>) comprising a first phase adjusting module (<NUM>) and a second phase adjusting module (<NUM>), the first phase adjusting module (<NUM>) outputting a first clock signal, and the second phase adjusting module (<NUM>) outputting a second clock signal;
the first phase adjusting module (<NUM>) and the second phase adjusting module (<NUM>) are connected in parallel to output an interpolation signal wherein each of the first phase adjusting module (<NUM>) and the second phase adjusting module (<NUM>) comprises:
a signal input end;
a signal output end;
a first MOS transistor (M1), wherein a gate of the first MOS transistor (M1) is connected to the signal input end, a drain of the first MOS transistor (M1) is connected to a supply voltage (VCC),
and a source of the first MOS transistor (M1) is connected to a first node (Q1);
a first adjusting module (A1), connected between the first node (Q1) and the signal output end;
a second MOS transistor (M2), wherein a gate of the second MOS transistor (M2) is connected to the signal input end, a source of the second MOS transistor (M2) is connected to a ground (GND), and a drain of the second MOS transistor (M2) is connected to a second node (Q2); and
a second adjusting module (A2), connected between the second node (Q2) and the signal output end; wherein the first adjusting module (A1) comprises a plurality of first adjusting circuits (A10), each of which is connected between the first node (Q1) and the signal output end; and wherein the second adjusting module (A2) comprises a plurality of second adjusting circuits (A20), each of which is connected between the second node (Q2) and the signal output end, characterized in that,
each of the plurality of first adjusting circuits (A10) comprises:
a first switch transistor (T1), wherein a drain of the first switch transistor (T1) is connected to the first node (Q1); and
a first resistor (R1), connected between a source of the first switch transistor (T1) and the signal output end; wherein each of the plurality of second adjusting circuits (A20) comprises:
a second switch transistor (T2), wherein a source of the second switch transistor (T2) is connected to the second node (Q2); and a second resistor (R2), connected between a drain of the second switch transistor (T2) and the signal output end.