Patent Description:
Photolithography is widely used in the manufacturing of semiconductor devices and display devices, such as liquid crystal displays (LCDs). Large area substrates are often utilized in the manufacture of LCDs. LCDs, or flat panels, are commonly used for active matrix displays, such as computers, touch panel devices, personal digital assistants (PDAs), cell phones, television monitors, and the like. Generally, flat panels may include a layer of liquid crystal material forming pixels sandwiched between two plates. When power from the power supply is applied across the liquid crystal material, an amount of light passing through the liquid crystal material may be controlled at pixel locations enabling images to be generated. As higher resolution displays become more in demand, the pixel locations become smaller and smaller.

Microlithography techniques are generally employed to create electrical features incorporated as part of the liquid crystal material layer forming the pixels. According to this technique, a light-sensitive photoresist is typically applied to at least one surface of the substrate. Then, a pattern generator exposes selected areas of the light-sensitive photoresist as part of a pattern with light to cause chemical changes to the photoresist in the selective areas to prepare these selective areas for subsequent material removal and/or material addition processes to create the electrical features.

Document <CIT> describes a method of generating and displaying images or recording patterns that exhibit line edge placement resolution to a fraction of the pixel size of an image transducer. It is mentioned that by using several exposures and by shifting the position of an edge between exposures, a broader range of line-widths, i.e., smaller increments, can be achieved. Document <CIT> describes methods and apparatuses for performing direct-write lithography in a two-color photoresist layer. According to this document, square pixels are not necessarily the optimum arrangement for minimizing the light that can be transferred from a DMD micro-mirror to the center of the image of another DMD mirror. Document <CIT> relates to methods for patterning substrates, such as reticles, masks or wafers, wherein doses applied in passes of a multipass writing strategy are tuned.

In order to continue to provide higher resolution display devices and other devices to consumers at the prices demanded by consumers, new apparatuses, approaches, and systems are needed to precisely and cost-effectively create the ever smaller patterns on substrates, such as large area substrates used to produce high resolution displays.

As the foregoing illustrates, there is a need for an improved technique for generating smaller patterns.

This objective has been met by a method to enhance the resolution of maskless lithography in accordance with claim <NUM>, and by a corresponding computer system and a non-transitory computer-readable medium in accordance with claims <NUM> and <NUM>. In particular, an image resolution enhancing application relating to the ability to apply maskless lithography patterns to a substrate while maintaining a high image contrast in a manufacturing process is disclosed. The embodiments described herein relate to a software application platform, which enhances image patterns resolution on a substrate. The application platform method includes running an algorithm to provide different target polygons for forming a pattern on a target. A minimum feature size which may be formed by a DMD is determined, the minimum feature size being a function of a mirror size of the DMD and hardware optics. For each target polygons smaller than the minimum feature size determining to line bias or shot bias the one or more target polygons to achieve a predetermined exposure contrast at the target polygon boundary, wherein line biasing comprises increasing the size of the target polygon and shot biasing comprises increasing the number of electromagnetic radiation shots in the target polygon. The one or more target polygons smaller than the minimum feature size are biased to form a digitized pattern on the substrate. Electromagnetic radiation is delivered to reflect off of a first mirror of the DMD when the centroid for the first mirror is within the one or more target polygons.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may be applied to other equally effective embodiments.

Embodiments of the disclosure generally relate to a software application relating to the ability to apply maskless lithography patterns to a substrate in a manufacturing process is disclosed. The software application enhances the native resolution for maskless lithography while maintaining a high image contrast. The maskless lithography operation utilizes a method wherein the number of shots of electromagnetic energy reflected off a digital micro-mirror device (DMD) is biased or the target polygon size is biased to form features below the native resolution of the DMD. Advantageously, higher resolution can be extended to DMD's suitably arranged for forming lower resolution devices on the substrate without any hardware modification. For example, a lower resolution DMD suitable for forming <NUM> features can be extended to form higher resolution, i.e., smaller, features such as a <NUM> feature. This method can similarly be extended for forming <NUM> features or smaller. The size of the mirrors along with hardware optics determine the feature sizes the DMD can form. The method described below extends the capabilities of the DMD for forming features sized smaller than the hardware optics and mirrors sizes conventionally allow.

The term "user" as used herein includes, for example, a person or entity that owns a computing device or wireless device; a person or entity that operates or utilizes a computing device or a wireless device; or a person or entity that is otherwise associated with a computing device or a wireless device. It is contemplated that the term "user" is not intended to be limiting and may include various examples beyond those described.

<FIG> is a perspective view of a system 100A that may benefit from embodiments disclosed herein. The system 100A includes a base frame <NUM>, a slab <NUM>, two or more stages <NUM>, and a processing apparatus <NUM>. The base frame <NUM> may rest on the floor of a fabrication facility and may support the slab <NUM>. Passive air isolators <NUM> may be positioned between the base frame <NUM> and the slab <NUM>. The slab <NUM> may be a monolithic piece of granite, and the two or more stages <NUM> may be disposed on the slab <NUM>. A substrate <NUM> may be supported by each of the two or more stages <NUM>. A plurality of holes (not shown) may be formed in the stage <NUM> for allowing a plurality of lift pins (not shown) to extend therethrough. The lift pins may rise to an extended position to receive the substrate <NUM>, such as from a transfer robot (not shown). The transfer robot may position the substrate <NUM> on the lift pins, and the lift pins may thereafter gently lower the substrate <NUM> onto the stage <NUM>.

The substrate <NUM> may, for example, be made of quartz and be used as part of a flat panel display. In other embodiments, the substrate <NUM> may be made of other materials such as glass. In some embodiments, the substrate <NUM> may have a photoresist layer formed thereon. A photoresist is sensitive to radiation and may be a positive photoresist or a negative photoresist, meaning that portions of the photoresist exposed to radiation will be respectively soluble or insoluble to a photoresist developer applied to the photoresist after the pattern is written into the photoresist. The chemical composition of the photoresist determines whether the photoresist will be a positive photoresist or negative photoresist. For example, the photoresist may include at least one of diazonaphthoquinone, a phenol formaldehyde resin, poly(methyl methacrylate), poly(methyl glutarimide), and SU-<NUM>. In this manner, the pattern may be created on a surface of the substrate <NUM> to form the electronic circuitry.

The system 100A may further include a pair of supports <NUM> and a pair of tracks <NUM>. The pair of supports <NUM> may be disposed on the slab <NUM>, and the slab <NUM> and the pair of supports <NUM> may be a single piece of material. The pair of tracks <NUM> may be supported by the pair of the supports <NUM>, and the two or more stages <NUM> may move along the tracks <NUM> in the X-direction. In one embodiment, the pair of tracks <NUM> is a pair of parallel magnetic channels. As shown, each track <NUM> of the pair of tracks <NUM> is linear. In other embodiments, the track <NUM> may have a non-linear shape. An encoder <NUM> may be coupled to each stage <NUM> in order to provide location information to a controller <NUM> (Shown in <FIG>).

The processing apparatus <NUM> may include a support <NUM> and a processing unit <NUM>. The support <NUM> may be disposed on the slab <NUM> and may include an opening <NUM> for the two or more stages <NUM> to pass under the processing unit <NUM>. The processing unit <NUM> may be supported by the support <NUM>. In one embodiment, the processing unit <NUM> is a pattern generator configured to expose a photoresist in a photolithography process. In some embodiments, the pattern generator may be configured to perform a maskless lithography process. The processing unit <NUM> may include a plurality of image projection systems (shown in <FIG>) disposed in a case <NUM>. The processing apparatus <NUM> may be utilized to perform maskless direct patterning. During operation, one of the two or more stages <NUM> moves in the X-direction from a loading position, as shown in <FIG>, to a processing position. The processing position may refer to one or more positions of the stage <NUM> as the stage <NUM> passes under the processing unit <NUM>. During operation, the two or more stages <NUM> may be lifted by a plurality of air bearings <NUM> (shown in <FIG>) and may move along the pair of tracks <NUM> from the loading position to the processing position. A plurality of vertical guide air bearings (not shown) may be coupled to each stage <NUM> and positioned adjacent an inner wall <NUM> of each support <NUM> in order to stabilize the movement of the stage <NUM>. Each of the two or more stages <NUM> may also move in the Y-direction by moving along a track <NUM> for processing and/or indexing the substrate <NUM>.

<FIG> is a perspective view of a photolithography system 100B for a single substrate according to embodiments disclosed herein. As the generations increase to larger substrates, floor space becomes a problem. The photolithography system 100B for the single substrate utilizes less floor space then system 100A described above with respect to <FIG>. The system 100B includes a base frame <NUM>, a slab <NUM>, a stage <NUM>, and a processing apparatus <NUM>. The base frame <NUM> rests on the floor of a fabrication facility and supports the slab <NUM>. Passive air isolators <NUM> are positioned between the base frame <NUM> and the slab <NUM>. In one embodiment, the slab <NUM> is a monolithic piece of granite, and the stage <NUM> is disposed on the slab <NUM>. A substrate <NUM> is supported by the stage <NUM>. A plurality of holes (not shown) are formed in the stage <NUM> for allowing a plurality of lift pins (not shown) to extend therethrough. In some embodiments, the lift pins rise to an extended position to receive the substrate <NUM>, such as from one or more transfer robots (not shown). The one or more transfer robots are used to load and unload a substrate <NUM> from the stage <NUM>.

The substrate <NUM> comprises any suitable material, for example, quartz used as part of a flat panel display. In other embodiments, the substrate <NUM> is made of other materials. In some embodiments, the substrate <NUM> has a photoresist layer formed thereon. A photoresist is sensitive to radiation. A positive photoresist includes portions of the photoresist, which when exposed to radiation, will be respectively soluble to photoresist developer applied to the photoresist after the pattern is written into the photoresist. A negative photoresist includes portions of the photoresist, which when exposed to radiation, will be respectively insoluble to photoresist developer applied to the photoresist after the pattern is written into the photoresist. The chemical composition of the photoresist determines whether the photoresist will be a positive photoresist or negative photoresist. Examples of photoresists include, but are not limited to, at least one of diazonaphthoquinone, a phenol formaldehyde resin, poly(methyl methacrylate), poly(methyl glutarimide), and SU-<NUM>. In this manner, the pattern is created on a surface of the substrate <NUM> to form the electronic circuitry.

The system 100B includes a pair of supports <NUM> and a pair of tracks <NUM>. The pair of supports <NUM> are disposed on the slab <NUM>, and the slab <NUM> and the pair of supports <NUM> are a single piece of material. The pair of tracks <NUM> are supported by the pair of the supports <NUM>, and the stage <NUM> moves along the tracks <NUM> in the X-direction. In one embodiment, the pair of tracks <NUM> is a pair of parallel magnetic channels. As shown, each track <NUM> of the pair of tracks <NUM> is linear. In other embodiments, one or more track <NUM> is non-linear. An encoder <NUM> is coupled to the stage <NUM> in order to provide location information to a controller (not shown).

The processing apparatus <NUM> includes a support <NUM> and a processing unit <NUM>. The support <NUM> is disposed on the slab <NUM> and includes an opening <NUM> for the stage <NUM> to pass under the processing unit <NUM>. The processing unit <NUM> is supported by the support <NUM>. In one embodiment, the processing unit <NUM> is a pattern generator configured to expose a photoresist in a photolithography process. In some embodiments, the pattern generator is configured to perform a maskless lithography process. The processing unit <NUM> includes a plurality of image projection apparatus (shown in <FIG>). In one embodiment, the processing unit <NUM> contains as many as <NUM> image projection apparatus. Each image projection apparatus is disposed in a case <NUM>. The processing apparatus <NUM> is useful to perform maskless direct patterning.

During operation, the stage <NUM> moves in the X-direction from a loading position, as shown in <FIG>, to a processing position. The processing position is one or more positions of the stage <NUM> as the stage <NUM> passes under the processing unit <NUM>. During operation, the stage <NUM> is be lifted by a plurality of air bearings (not shown) and moves along the pair of tracks <NUM> from the loading position to the processing position. A plurality of vertical guide air bearings (not shown) are coupled to the stage <NUM> and positioned adjacent an inner wall <NUM> of each support <NUM> in order to stabilize the movement of the stage <NUM>. The stage <NUM> also moves in the Y-direction by moving along a track <NUM> for processing and/or indexing the substrate <NUM>. The stage <NUM> is capable of independent operation and can scan a substrate <NUM> in one direction and step in the other direction.

A metrology system measures the X and Y lateral position coordinates of each of the stage <NUM> in real time so that each of the plurality of image projection apparatus can accurately locate the patterns being written in a photoresist covered substrate. The metrology system also provides a real-time measurement of the angular position of each of the stage <NUM> about the vertical or Z-axis. The angular position measurement can be used to hold the angular position constant during scanning by means of a servo mechanism or it can be used to apply corrections to the positions of the patterns being written on the substrate <NUM> by the image projection apparatus <NUM>, shown in <FIG>. These techniques may be used in combination.

<FIG> is a cross-sectional side view of the system 100A of <FIG> according to one embodiment. As shown, each stage <NUM> includes a plurality of air bearings <NUM> for lifting the stage <NUM>. Each stage <NUM> may also include a motor coil (not shown) for moving the stage <NUM> along the tracks <NUM>. The two or more stages <NUM> and the processing apparatus <NUM> may be enclosed by an enclosure (not shown) in order to provide temperature and pressure control.

<FIG> is a perspective schematic view of a plurality of image projection systems <NUM> according to one embodiment. As shown in <FIG>, each image projection system <NUM> produces a plurality of write beams <NUM> that are directed onto a surface <NUM> of the substrate <NUM>. As the substrate <NUM> moves in the X-direction and Y-direction, the entire surface <NUM> may be patterned by the write beams <NUM>. The number of the image projection systems <NUM> may vary based on the size of the substrate <NUM> and/or the speed of stage <NUM>. In one embodiment, there are <NUM> image projection systems <NUM> in the processing apparatus <NUM>.

<FIG> is a perspective schematic view of an image projection apparatus <NUM> of the plurality of image projection devices of <FIG> according to one embodiment. In the embodiment shown, the image projection apparatus <NUM> uses one or more DMDs <NUM> as the spatial light modulator(s). The image projection apparatus <NUM> is part of an image projection system <NUM>, which includes a light source <NUM>, an aperture <NUM>, a lens <NUM>, a frustrated prism assembly <NUM>, one or more DMDs <NUM> (one is shown), and a light dump <NUM>, in addition to the alignment and inspection system <NUM> and the projection lens <NUM>. The light source <NUM> is any suitable light source, such as a light emitting diode (LED) or a laser, capable of producing a light having predetermined wavelength. In one embodiment, the predetermined wavelength is in the blue or near ultraviolet (UV) range, such as less than about <NUM>. The frustrated prism assembly <NUM> includes a plurality of reflective surfaces. The projection lens <NUM> is, as an example, a 10x objective lens. During operation of the image projection apparatus <NUM>, a light beam <NUM> having a predetermined wavelength, such as a wavelength in the blue range, is produced by the light source <NUM>. The light beam <NUM> is reflected to the DMD <NUM> by the frustrated prism assembly <NUM>. The DMD <NUM> includes a plurality of mirrors, and the number of mirrors corresponds to the number of pixels to be projected. The plurality of mirrors are individually controllable, and each mirror of the plurality of mirrors is at an "on" position or "off" position, based on the mask data provided to the DMD <NUM> by the controller (not shown). When the light beam <NUM> reaches the mirrors of the DMD <NUM>, the mirrors that are at "on" position reflect the light beam <NUM>, i.e., forming the plurality of write beams, to the projection lens <NUM>. The projection lens <NUM> then projects the write beams to the surface of the substrate. The mirrors that are at "off" position reflect the light beam <NUM> to the light dump <NUM> instead of the surface of the substrate.

<FIG> illustrates two mirrors <NUM>, <NUM> of the DMD <NUM> according to one embodiment. As shown, each mirror <NUM>, <NUM> of the DMD <NUM> is disposed on a tilting mechanism <NUM>, which is disposed on a memory cell <NUM>. The memory cell <NUM> may be a CMOS SRAM. During operation, each mirror <NUM>, <NUM> is controlled by loading the mask data into the memory cell. The mask data electrostatically controls the tilting of the mirror <NUM>, <NUM> in a binary fashion. When the mirror <NUM>, <NUM> is in a reset mode or without power applied, it may be set to a flat position, not corresponding to any binary number. Zero in binary may correspond to an "off" position, which means the mirror is tilted at -<NUM> degrees, -<NUM> degrees, or any other feasibly negative tilting degree. One in binary may correspond to an "on" position, which means the mirror is tilted at +<NUM> degrees, +<NUM> degrees, or any other feasibly positive tilting degree. As shown in <FIG>, the mirror <NUM> is at "off" position and the mirror <NUM> is at "on" position.

The beam <NUM> may be reflected by the two mirrors <NUM>, <NUM> of the DMD <NUM>, according to one embodiment. As shown, the mirror <NUM>, which is at "off" position, reflects the beam <NUM> generated from the light source <NUM> to the light dump <NUM>. The mirror <NUM>, which is at "on" position, forms the write beam <NUM> by reflecting the beam <NUM> to the projection lens <NUM>.

<FIG> illustrates a computer system configured for enhancing maskless lithography pattern resolution on a substrate in which embodiments of the disclosure may be practiced. As shown, the computing system <NUM> may include a plurality of servers <NUM>, a pattern resolution enhancement application (PREA) server <NUM>, and a plurality of controllers (i.e., computers, personal computers, mobile/wireless devices) <NUM> (only two of which are shown for clarity), each connected to a communications network <NUM> (for example, the Internet). The servers <NUM> may communicate with the database <NUM> via a local connection (for example, a Storage Area Network (SAN) or Network Attached Storage (NAS)) or over the Internet. The servers <NUM> are configured to either directly access data included in the database <NUM> or to interface with a database manager that is configured to manage data included within the database <NUM>.

The controller <NUM> is generally designed to facilitate the control and automation of the processing techniques described herein. The controller <NUM> may be coupled to or in communication with one or more of the processing apparatus <NUM>, the stages <NUM>, and the encoder <NUM>. The processing apparatus <NUM> and the stages <NUM> may provide information to the controller <NUM> regarding the substrate processing and the substrate aligning. For example, the processing apparatus <NUM> may provide information to the controller <NUM> to alert the controller that substrate processing has been completed. The encoder <NUM> may provide location information to the controller <NUM>, and the location information is then used to control the stages <NUM> and the processing apparatus <NUM>.

Each controller <NUM> may include conventional components of a computing device, for example, a processor, system memory, a hard disk drive, a battery, input devices such as a mouse and a keyboard, and/or output devices such as a monitor or graphical user interface, and/or a combination input/output device such as a touchscreen which not only receives input but also displays output. Each server <NUM> and the PREA server <NUM> may include a processor and a system memory (not shown), and may be configured to manage content stored in database <NUM> using, for example, relational database software and/or a file system. The servers <NUM> may be programmed to communicate with one another, the controllers <NUM>, and the PREA server <NUM> using a network protocol such as, for example, the TCP/IP protocol. The PREA server <NUM> may communicate directly with the controllers <NUM> through the communications network <NUM>. The controllers <NUM> are programmed to execute software <NUM>, such as programs and/or other software applications, and access applications managed by servers <NUM>.

In the embodiments described below, users may respectively operate the controllers <NUM> that may be connected to the servers <NUM> over the communications network <NUM>. Pages, images, data, documents, and the like may be displayed to a user via the controllers <NUM>. Information and images may be displayed through a display device and/or a graphical user interface in communication with the controller <NUM>.

It is noted that the controller <NUM> may be a personal computer, laptop mobile computing device, smart phone, video game console, home digital media player, network-connected television, set top box, and/or other computing devices having components suitable for communicating with the communications network <NUM> and/or the required applications or software. The controller <NUM> may also execute other software applications configured to receive content and information from the PREA server <NUM>.

<FIG> illustrates a more detailed view of the PREA server <NUM> of <FIG>. The PREA server <NUM> includes, without limitation, a central processing unit (CPU) <NUM>, a network interface <NUM>, memory <NUM>, and storage <NUM> communicating via an interconnect <NUM>. The PREA server <NUM> may also include I/O device interfaces <NUM> connecting I/O devices <NUM> (for example, keyboard, video, mouse, audio, touchscreen, etc.). The PREA server <NUM> may further include the network interface <NUM> configured to transmit data via the communications network <NUM>.

The CPU <NUM> retrieves and executes programming instructions stored in the memory <NUM> and generally controls and coordinates operations of other system components. Similarly, the CPU <NUM> stores and retrieves application data residing in the memory <NUM>. The CPU <NUM> is included to be representative of a single CPU, multiple CPU's, a single CPU having multiple processing cores, and the like. The interconnect <NUM> is used to transmit programming instructions and application data between the CPU <NUM>, I/O device interfaces <NUM>, storage <NUM>, network interface <NUM>, and memory <NUM>.

The memory <NUM> is generally included to be representative of a random access memory and, in operation, stores software applications and data for use by the CPU <NUM>. Although shown as a single unit, the storage <NUM> may be a combination of fixed and/or removable storage devices, such as fixed disk drives, floppy disk drives, hard disk drives, flash memory storage drives, tape drives, removable memory cards, CD-ROM, DVD-ROM, Blu-Ray, HD-DVD, optical storage, network attached storage (NAS), cloud storage, or a storage area-network (SAN) configured to store non-volatile data.

The memory <NUM> may store instructions and logic for executing an application platform <NUM> which may include pattern resolution enhancement application software <NUM>. The storage <NUM> may include a database <NUM> configured to store data <NUM> and associated application platform content <NUM>. The database <NUM> may be any type of storage device.

Network computers are another type of computer system that can be used in conjunction with the disclosures provided herein. Network computers do not usually include a hard disk or other mass storage, and the executable programs are loaded from a network connection into the memory <NUM> for execution by the CPU <NUM>. A typical computer system will usually include at least a processor, memory, and an interconnect coupling the memory to the processor.

<FIG> illustrates a controller <NUM> used to access the PREA server <NUM> and retrieve or display data associated with the application platform <NUM>. The controller <NUM> may include, without limitation, a central processing unit (CPU) <NUM>, a network interface <NUM>, an interconnect <NUM>, a memory <NUM>, storage <NUM>, and support circuits <NUM>. The controller <NUM> may also include an I/O device interface <NUM> connecting I/O devices <NUM> (for example, keyboard, display, touchscreen, and mouse devices) to the controller <NUM>.

Like CPU <NUM>, CPU <NUM> is included to be representative of a single CPU, multiple CPU's, a single CPU having multiple processing cores, etc., and the memory <NUM> is generally included to be representative of a random access memory. The interconnect <NUM> may be used to transmit programming instructions and application data between the CPU <NUM>, I/O device interface <NUM>, storage <NUM>, network interface <NUM>, and memory <NUM>. The CPU <NUM> may be one of any form of computer processors that are used in industrial settings for controlling various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor the processes (e.g., processing time and substrate position).

The network interface <NUM> may be configured to transmit data via the communications network <NUM>, for example, to transfer content from the PREA server <NUM>. Storage <NUM>, such as a hard disk drive or solid-state storage drive (SSD), may store non-volatile data. The storage <NUM> may contain a database <NUM>. The database <NUM> may contain data <NUM>, other content <NUM>, and an image process unit <NUM> having data <NUM> and control logic <NUM>.

The memory <NUM> is connected to the CPU <NUM>, and may be one or more of a readily available memory, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. Software instructions and data can be coded and stored within the memory for instructing the CPU <NUM>. The memory <NUM> may include an application interface <NUM>, which itself may display software instructions <NUM>, and/or store or display data <NUM>. The application interface <NUM> may provide one or more software applications which allow the controller to access data and other content hosted by the PREA server <NUM>.

The support circuits <NUM> connected to the CPU <NUM> for supporting the processor may include conventional cache <NUM>, power supplies <NUM>, clock circuits <NUM>, input/output circuitry <NUM>, subsystems <NUM>, and the like. A program (or computer instructions) readable by the controller <NUM> determines which tasks are performable on a substrate. The program may be software readable by the controller <NUM> and may include code to monitor and control, for example, the processing time and substrate position.

Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.

The present example also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flash memory, magnetic or optical cards, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, or any type of media suitable for storing electronic instructions, and each coupled to a computer system interconnect.

Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the required method operations. The structure for a variety of these systems will appear from the description above. In addition, the present examples are not described with reference to any particular programming language, and various examples may thus be implemented using a variety of programming languages.

The embodiments described herein relate to a software application platform, which enables the development of skinnier lines, i.e., smaller feature sizes, than the mirror size allows for a given mirror size when forming a lithography pattern on a substrate. <FIG> illustrates a method <NUM> to enhance the resolution of maskless lithography while maintaining a high image contrast. The method may be performed by the controller <NUM>, as shown in <FIG> or other suitable device. The method <NUM> begins at block <NUM>. At block <NUM>, an algorithm is run to provide different polygons for forming a pattern on a substrate. A computer generated pattern, i.e., polygons, provides boundary conditions for exposing photo-resist thereon a substrate. The pattern of polygons may generate lines between about <NUM> to about <NUM>, such as about <NUM>, to be exposed in the photo lithography process.

At block <NUM>, a minimum feature size which may be formed by the DMD is determined. As discussed above, the feature size limitation is a function of the DMD mirror size and the hardware lens. The hardware configuration of the DMD dictates the minimum standard feature which can be printed. For example, the DMD may be suitable for exposing at a resolution of about <NUM>. If there are <NUM> features to be exposed, then the method which follows provides for the DMD to form the smaller features without any hardware changes. If a standard recipe is to deposit <NUM> shots worth of light in all of our target polygons, a feature that is smaller than our <NUM> min feature size would receive less than <NUM> shots and would be under-exposed. Instead, the feature can be properly exposed through either a line bias or a multiplicity bias (shot bias) or both. For example, the number of shots may be increased by <NUM>%. Biasing will be further explained using <FIG>.

At block <NUM>,a line bias and/or a shot bias is determined to achieve a predetermined acceptable exposure contrast at the polygon boundary for polygons smaller than the minimum feature size. This results in the formation of the features on the substrate where a contrast of between about <NUM>% and about <NUM>%, such as about <NUM>% or greater is provided, i.e., where light energy has been directed on to the layer of material (photoresist) on the substrate in sufficient quantity to properly expose a feature. That is, each DMD exposes its own native resolution limit at a predetermined minimum contrast, such as about <NUM>%, wherein the contrast is a measure of (Imax-Imin)/(Imax+lmin). However, it should be appreciated that a number of variables may affect the minimum contrast interval such that a contrast of less than <NUM>%, or more than <NUM>%, may be adequate for exposure to form the desired feature. However, for ease of understanding the methods described herein, the remaining examples of exposure contrast will use a minimum contrast of about <NUM>%.

An exposure contrast can be increased by increasing the number of shots in the target polygon as well as increasing the width of the target polygon (line bias). The minimum feature boundary is established at the <NUM>% contrast interval, i.e., the areas having a contrast of less than <NUM>% is not adequately exposed to produce the feature. A <NUM> sub-resolution can be achieved by increasing the number of energy shots, i.e., multiplicity bias, in the target polygon and/or by line bias thinning the exposed polygon, i.e., making the target polygon width smaller, allowing smaller features to be produced than possible under native resolution techniques. For example, by increasing the number of exposure shots to <NUM> from <NUM> and applying a <NUM> line bias, the line resolution can be decreased from <NUM> to about <NUM> allowing for smaller features than possible under native resolution techniques.

At block <NUM>, the electromagnetic radiation shot or the polygon lines are biased for the polygons smaller than the minimum feature size for forming a digitized pattern on the substrate when exposing a photo-resist. The target polygons are biased prior to firing any shots of light. This requires no shot biasing. However, line biasing may also require shot biasing. Exposing the photoresist on the substrate is used to form a pattern, i.e., features, on the substrate.

At block <NUM>, a shot of electromagnetic radiation is reflected off of a first mirror of the DMD when a centroid for the first mirror is within the polygons in the pattern. The electromagnetic radiation may be in the form of light from a laser, such as a blue light laser, reflected off of the DMD mirrors. Each DMD mirror can be turned on or off, when reflecting a digitized pattern to ensure only electromagnetic radiation from the desired mirrors are directed to the target polygon and the areas outside the target polygon do not collect any residual electromagnetic radiation. In one embodiment the image projection system <NUM> may produce the electromagnetic radiation. The electromagnetic radiation may be visible light, for example, blue laser light emitted from the image projection system <NUM> and reflected off of the DMD <NUM>.

As exposure points accumulate in an area of the target, a uniform aerial image is formed in the photoresist on the target. Based on the resolution of the DMD, step size, the number of columns shaved, and the number of exposure shots, the fidelity of the exposed line for the feature polygons can vary widely. As the width of the exposed polygons decreases, the image contrast begins to decrease. Line and/or multiplicity biasing is used to obtain the minimum <NUM>% contrast at the line edge of the target polygon, for forming the critical dimensions of the features below the native resolution of the DMD on the substrate.

A discussion of the effect of no line or multiplicity (shot) biasing is provided here with respect to <FIG> and <FIG> together. The study illustrates a first feature <NUM>, a second feature <NUM> and a third feature <NUM>. The first feature <NUM> has a first target polygon <NUM> having a design width of <NUM>. The second feature <NUM> has a second target polygon <NUM> having a design width of <NUM>. The third feature <NUM> has a third target polygon <NUM> having a design width of <NUM>. A pitch <NUM> between the third target polygon <NUM> and the second target polygon <NUM> is an area where the exposure is ideally zero but should be less than <NUM>% contrast to prevent the formation of features in this area.

As the width of the exposed polygons decreases, the image contrast begins to decrease once the target polygon size is less than the minimum feature that can be resolved by the system. The first feature <NUM> has an exposed polygon <NUM> having a first width <NUM> of about <NUM>. The exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown are a <NUM>% interval <NUM>, a <NUM>% interval <NUM> and a <NUM>% interval <NUM>. As can be seen, the first width <NUM> of the exposed polygon <NUM> is a distance <NUM> smaller than a first target width <NUM> of the first target polygon <NUM>. The distance <NUM> is about (<NUM> - <NUM>) / <NUM>, i.e., <NUM> short for a single side of the feature design. As shown in the length along exposure (<FIG>), the threshold development <NUM> is less than <NUM>%, i.e., about <NUM>%, and thus complete formation of the first feature <NUM> is not obtained.

The second feature <NUM> has a second exposed polygon <NUM> having a second width <NUM> of about <NUM>. The second exposed polygon <NUM> resides in the area of the second feature <NUM> having a contrast greater than <NUM>%. The second width <NUM> of the second exposed polygon <NUM> is substantially similar to a second target width <NUM> of the second target polygon <NUM>. As shown in the length along exposure (<FIG>) the threshold development is greater than <NUM>% and less than %<NUM>, such as about <NUM>%. Thus complete formation of the second feature <NUM> is obtained.

The third feature <NUM> has a third exposed polygon <NUM> having a third width <NUM> of about <NUM>. The third feature <NUM> is substantially similar to the second feature <NUM> and has similar results in forming the feature.

<FIG> and <FIG> illustrates a study of the effects of line biasing without multiplicity biasing. That is, increasing or decreasing the design width of a feature to achieve a different dimension during processing. The study illustrates a first feature <NUM>, a second feature <NUM> and a third feature <NUM> formation on a substrate. The first feature <NUM> has a first target polygon <NUM> having a design width of <NUM> which is biased to <NUM>. The second feature <NUM> has a second target polygon <NUM> having a design width of <NUM>. The third feature <NUM> has a third target polygon <NUM> having a design width of <NUM>. A pitch <NUM> is shown between the third target polygon <NUM> and the second target polygon <NUM> having no formation of features therein.

The first feature <NUM> has an exposed polygon <NUM> having a first width <NUM> of about <NUM>. The exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown are a <NUM>% interval <NUM>, a <NUM>% interval <NUM> and a <NUM>% interval <NUM>. The first width <NUM> of the exposed polygon <NUM> is substantially the same as a first target width <NUM> of the first target polygon <NUM>. The length along exposure (<FIG>) shows a threshold development <NUM> greater than <NUM>%, such as about <NUM>%, and thus complete formation of the first feature <NUM> is obtained. By biasing the width of the first target polygon <NUM> by <NUM>, the exposed polygon <NUM> can be formed with the desired critical dimension of about <NUM>.

The second feature <NUM> has a second exposed polygon <NUM> having a second width <NUM> of about <NUM>. The second exposed polygon <NUM> has a contrast greater than <NUM>% which includes the contrast intervals there above, such as a <NUM>% interval <NUM>. The second width <NUM> of the second exposed polygon <NUM> is substantially similar to a second target width <NUM> of the second target polygon <NUM>. Unlike the first target polygon <NUM>, the second target polygon <NUM> was not biased when performing this operation. As shown in the length along exposure (<FIG>) the threshold development is greater than <NUM>% and less than %<NUM>, such as about <NUM>%. Thus complete formation of the second feature <NUM> is obtained.

<FIG> and <FIG> illustrate a study of the effects of multiplicity biasing without line biasing. That is, increasing the number of exposure shots where biased to do so. The study illustrates a first feature <NUM>, a second feature <NUM> and a third feature <NUM> formation on a substrate. The first feature <NUM> has a first target polygon <NUM> having a design width of <NUM>. The second feature <NUM> has a second target polygon <NUM> having a design width of <NUM>. The third feature <NUM> has a third target polygon <NUM> having a design width of <NUM>. A pitch <NUM> is shown between the third target polygon <NUM> and the second target polygon <NUM> having no formation of features therein. The number of exposure shots used to develop the exposed polygon for each of the first feature <NUM>, the second feature <NUM> and the third feature <NUM> is biased, i.e., increased, by two or three times over the original number of exposure shots. For example, the number of exposure shots to populate a feature may be about <NUM> shots evenly. If the <NUM> shots resulted in an exposed polygon with less than <NUM>% contrast at the target polygon boundary, the number of exposure shots can be increase <NUM> times to about <NUM>. A percentage increase, such as about <NUM>% where the exposure shots are now about <NUM>, would change the way the shots are populated across the exposure, i.e., it would be non-uniform. Multiples, such as <NUM>, are chosen as a multiplier of the original number of shots. The multiples may be a natural number, or even a real number, which achieves a desired number of shots. For example, a <NUM>-shot pattern may have a multiple applied to the pattern to achieve a <NUM>-shot pattern or even a <NUM>-shot pattern. In one embodiment, two distinct <NUM>-shot patterns overlay on top of each other, obtaining a net <NUM>-shot pattern while maintaining an even distribution for the exposure shots. Alternately, an increase in the percentage of exposure shots may be computed and to layout in an evenly distributed pattern within the target polygon. The first feature <NUM> has a first exposed polygon <NUM> having a first width <NUM> of about <NUM>. The first exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown are a <NUM>% interval <NUM>, a <NUM>% interval <NUM> and a <NUM>% interval <NUM>. The first width <NUM> of the first exposed polygon <NUM> is substantially the same as a first target width <NUM> of the first target polygon <NUM>. The length along exposure (<FIG>) shows a threshold development <NUM> greater than <NUM>%, such as about <NUM>%, and thus complete formation of the first feature <NUM> is obtained. By biasing the number of shots (multiplicity) on the first target polygon <NUM> by <NUM>%, the first exposed polygon <NUM> can be formed with the desired critical dimension of about <NUM>.

The second feature <NUM> has a second exposed polygon <NUM> having a second width <NUM> of about <NUM>. The second exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown in addition to those above are a <NUM>% interval <NUM> and an <NUM>% interval <NUM>. The second width <NUM> of the second exposed polygon <NUM> has a second distance <NUM> larger than a second target width <NUM> of the second target polygon <NUM>. The second distance <NUM> is between about <NUM> to about <NUM>, such as about <NUM>. Unlike the first exposed polygon <NUM>, the second exposed polygon <NUM> is larger than the design for the critical dimension of the second feature by about <NUM>%. As shown in the length along exposure (<FIG>) the threshold development is greater than %<NUM>. Thus, the second feature <NUM> is formed oversized.

The third feature <NUM> has a third exposed polygon <NUM> having a third width <NUM> of about <NUM>. The third feature <NUM> is substantially similar to the second feature <NUM> and has similar results for forming the feature.

<FIG> and <FIG> illustrate a study of the effects of multiplicity biasing and line biasing. That is, increasing the number of exposure shots and biasing the target polygon dimension to achieve a <NUM>% threshold at the edge of the target polygons and increasing or decreasing the line width where biased to do so. The study illustrates a first feature <NUM>, a second feature <NUM> and a third feature <NUM> formation on a substrate. The first feature <NUM> has a first target polygon <NUM> having a design width of <NUM>. The second feature <NUM> has a second target polygon <NUM> having a design width of <NUM> biased down to <NUM>. The third feature <NUM> has a third target polygon <NUM> having a design width of <NUM> biased down to <NUM>. A pitch <NUM> is shown between the third target polygon <NUM> and the second target polygon <NUM> having no formation of features therein. The number of exposure shots used to develop the exposed polygon for each of the first feature <NUM>, the second feature <NUM> and the third feature <NUM> is biased, i.e., increased, by about 2x.

The first feature <NUM> has an exposed polygon <NUM> having a first width <NUM> of about <NUM>. The exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown are a <NUM>% interval <NUM>, a <NUM>% interval <NUM> and a <NUM>% interval <NUM>. The first width <NUM> of the exposed polygon <NUM> is substantially the same as a first target width <NUM> of the first target polygon <NUM>. The length along exposure (<FIG>) shows a threshold development <NUM> greater than <NUM>%, such as about <NUM>%, and thus complete formation of the first feature <NUM> is obtained. By biasing the number of shots (multiplicity) on the first target polygon <NUM> by <NUM>%, the exposed polygon <NUM> can be formed with the desired critical dimension of about <NUM> (measure to be about <NUM>).

The second feature <NUM> has a second exposed polygon <NUM> having a second width <NUM> of about <NUM>. The second exposed polygon <NUM> has a contrast greater than <NUM>%. The contrast intervals shown in addition to those above are a <NUM>% interval <NUM> and an <NUM>% interval <NUM>. The second width <NUM> of the second exposed polygon <NUM> is substantially the same as a second target width <NUM> of the second target polygon <NUM>, i.e., a distance <NUM> between the second width <NUM> and the second target width <NUM> approaches zero. The second width <NUM> was biased down by about <NUM> to prevent the second feature <NUM> from being oversized due to the increase in the number of shots. As shown in the length along exposure (<FIG>) the threshold development is greater than <NUM>% and less than %<NUM>, such as <NUM>%. Thus, the second feature <NUM> can be correctly formed.

The third feature <NUM> has a third exposed polygon <NUM> having a third width <NUM> of about <NUM>. The third feature <NUM> is substantially similar to the second feature <NUM> and has similar results for forming the feature.

As discussed above with respect to <FIG>, by increasing the number of shots the large features become too big. By decreasing the dimension of the target polygon these features can be brought back to the target critical dimension. By mixing the line and multiplicity bias, each feature may be formed at the correct dimension when attempting to form features below the resolution of the hardware provided with the DMD. It should be appreciated that the line and multiplicity bias may be performed per feature and not all features may be biased. For example, a first feature may only have a line biased applied thereto, a second feature may only have a multiplicity bias (shot) applied thereto, a third feature may have both the line and multiplicity biased applied thereto while yet a fourth feature has no bias applied at all. It should also be appreciated that the number of shots a feature is biased may be different than another feature also biased in the number of shots. For example a first feature may have a multiplicity bias of 2x while a second feature have a multiplicity bias of 3x. Similarly, the line bias for a first feature may not be the same as that of a second feature. For example, the first feature may have a line bias of +<NUM> while a second feature is biased -<NUM>.

In one embodiment, the image projection system <NUM> may expose a substrate and deliver light to the surface of the substrate <NUM>. Each exposure may last between approximately about <NUM> microseconds and about <NUM> microseconds, for example between about <NUM> microseconds and about <NUM> microseconds.

In another embodiment, a computer system to enhance the resolution of maskless lithography while maintaining a high image contrast is provided. The computer system includes a processor and a memory. The memory stores instructions that, when executed by the processor, cause the computer system to enhance the resolution of maskless lithography while maintaining a high image contrast on a substrate. The steps include running an algorithm to provide different polygons with different multiplicity or line bias; ; determining a centroid grid for a plurality of mirrors in a DMD; shooting electromagnetic radiation to reflect off of a first mirror of the DMD; and reflecting the light to form a digitized pattern on the target to expose a photo-resist.

In yet another embodiment, a non-transitory computer-readable storage medium, storing instructions that, when executed by the processor, cause the computer system to enhance the resolution of maskless lithography while maintaining a high image contrast. The steps include running an algorithm to provide different polygons with different multiplicity or line bias; determining a centroid grid for a plurality of mirrors in a DMD; shooting electromagnetic radiation to reflect off of a first mirror of the DMD and reflecting the light to form a digitized pattern on the target to expose a photo-resist.

Benefits of the embodiments disclosed herein extending a high volume manufacturing (HVM) tool to a lower resolution through the method <NUM> discussed above. At the threshold value for the contrast, it can be shown that a DMD suitable for <NUM> sized pixels can generate pixels sized about <NUM>. Similarly, a DMD suitable for producing <NUM> sized pixels can be extended to generate <NUM> sized pixels. Additionally, a DMD suitable for generating <NUM> sized pixels can be extended to generate <NUM> sized pixels without changing any hardware.

While the foregoing is directed to embodiments described herein, other and further embodiments may be devised without departing from the basic scope thereof. For example, aspects of the present disclosure may be implemented in hardware or software or in a combination of hardware and software. One embodiment described herein may be implemented as a program product for use with a computer system. The program(s) of the program product define functions of the embodiments (including the methods described herein) and can be contained on a variety of computer-readable storage media. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (for example, read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (for example, floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the disclosed embodiments, are embodiments of the present disclosure.

Claim 1:
A method to enhance the resolution of maskless lithography while maintaining a high image contrast on a substrate, comprising:
running (<NUM>) an algorithm to provide different target polygons for forming a pattern on a target;
determining (<NUM>) a minimum feature size which may be formed by a DMD (<NUM>), wherein the minimum feature size is a function of a mirror size of the DMD and hardware optics;
determining (<NUM>) to line bias or shot bias the one or more target polygons to achieve an acceptable exposure contrast at the target polygon boundary for each target polygons smaller than the minimum feature size, wherein line biasing comprises increasing the size of the target polygon and shot biasing comprises increasing the number of electromagnetic radiation shots in the target polygon;
biasing (<NUM>) the one or more target polygons smaller than the minimum feature size to form a digitized pattern on the substrate; and
delivering (<NUM>) a shot of electromagnetic radiation to reflect off of a first mirror of the DMD (<NUM>) when a centroid for the first mirror is within the one or more target polygons.