Patent Description:
It is important in many electrical circuits that various current sources maintain stable and fixed current output relative to one another. In an example, a current steering digital to analog converter (DAC) includes a plurality of current sources. The relative mismatches between the current sources with varying operating conditions can directly affect linearity of the DAC. As used herein, a "current source" comprises an electrical circuit that delivers current (e.g., electric current), which is ideally independent of the voltage across it (i.e., the current source). In practice, current sources have non-idealities, such as finite internal resistance, which can cause the current source to deviate from ideal behavior. In general, active current sources may be implemented using active electronic components (e.g., transistors) having current-stable nonlinear output characteristics when driven by steady input current or voltage.

Mechanisms to decrease the mismatch between the various current sources can include a calibration technique that trims (e.g., calibrates, adjusts, regulates, etc.) all current sources to a reference current source using a trim circuit. In one example mechanism, the trim circuit includes a calibration DAC (CAL DAC), which injects a small correction current in parallel with the current source under calibration (or correction). The total current of the current source and the trim circuit is measured against a master reference current and the difference is forced to approach zero through a successive approximation register (SAR) logic circuit.

However, the output current generated by the CAL-DAC does not generally track environment changes, such as temperature and bias current changes. Bias current refers to a direct current (DC) that is made to flow between two points of an active electronic component for purposes of controlling its behavior. Assume that the current source comprises a metal oxide semiconductor field effect transistor (MOSFET), which can be either of NMOS type, or PMOS type. The bias current (I) to voltage (V) relationship of the current source follows a square law: <MAT> where µ is the electron or hole mobility (depending on the transistor type), Cox is gate capacitance of the transistors, W and L are width and length, respectively, of the gate, VGS is the voltage between the gate and source of the transistor, and VTH is the threshold voltage. The current mismatch ΔI between the reference current source and the current source to be calibrated can be expressed as follows: <MAT> where <MAT>, is transconductance of the transistor. In a general sense, transconductance is a ratio of a current change at an output port of the transistor (e.g., MOSFET) to a voltage change at an input port of the transistor.

In general, <MAT>, ΔVTH, I, and gm determine the current mismatch, where <MAT> and ΔVTH are device mismatches (e.g., caused due to processing and other factors) between the current source under calibration and the reference current source. In general, gm is temperature and bias current dependent (e.g., because mobility µ is a function of temperature, and gm varies with the bias current). Therefore, the current mismatch as a function of I and T can be expressed as: <MAT>.

The full scale current (e.g., maximum value of current) of currently existing CAL DACs is only proportional to bias current I. The output of the CAL DAC is a portion of the full scale current based on a fixed (e.g., constant) scale factor. Usually the current source is calibrated under a certain environment, including a specific temperature and bias current. When the environment such as the bias current and temperature change, the output current of the CAL-DAC trim circuit does not track the current source mismatch. As a result, although the current source may be calibrated to match the master reference current, the calibration can become erroneous with changes in temperature or bias current; consequently, the current sources fail to maintain stable and fixed current output relative to one another. Recalibration of each current source would be required in the changed environment.

<NPL>, discloses a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels.

<NPL>, presents a foreground DAC calibration method that is insensitive to temperature fluctuations and on-chip disturbances. In the proposed current cell, the same number of unit transistors is always used, guaranteeing matched response for all current cells. These transistors are divided in two groups: a fixed group and a configurable group. The unit transistors in the configurable group can be interchanged with additional redundant unit transistors, such that the mismatch errors of the configurable group compensate the mismatch errors of the fixed group. Together they generate the needed output current. <NPL>, presents a calibrated 14b current-steering DAC is fabricated in a <NUM> /spl mu/m digital CMOS process. <NPL>, presents a digitally enhanced strategy for current-steering digital-to-analog converters (DACs) applied to video systems. The linearity error introduced by the wittingly small current sources is evaluated by an on-chip built-in self-test scheme, which comprises a shared CaIDAC, a BiasDAC, and a digital controller. Two current tuning loops are involved for error detection and compensation. <NPL>, presents a <NUM>-b <NUM>-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity. The static linearity corresponding to the <NUM>-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. <NPL>, presents an on-chip low-power self-calibration apparatus implemented in a <NUM>-bit current-steering <NUM> CMOS DAC. The DAC core consists of a noncalibrated binary LSB part and a calibrated thermometer MSB part. The thermometer currents are generated by combining a coarse <NUM>-bit accurate current with a fine calibrating current provided by a small calibrating DAC (CALDAC). Patent application <CIT> relates to a circuit device for suppressing the dependence from temperature and production process variables of the transconductance of a differential transconductor stage incorporating a polarization circuit, particularly concerned with continuous-time monolithic filters. Patent application <CIT> relates continuous time integrated circuits, and is particularly directed to an improved on-chip filter circuit, comprised of at least one transconductance stage and an associated (passive) load component therefor (e.g. capacitor), with the transconductance stage containing a sampled data resistor (switched capacitor) component for defining the transconductance, so that the transfer function (in particular the corner frequency) of the filter is dependent only upon a readily controllable parameter - the switching frequency of the sampled data resistor - rather than a processed component (absolute capacitance), thereby making the behavior of the filter insensitive to processing variations. Patent application <CIT> relates to a transconductor tuning device, and more particularly, to a tuning device which tunes a transconductance of a transconductor using a current. Patent application <CIT> relates to an apparatus for stabilizing cut-off frequency using a transconductance, more specifically, to an apparatus for stabilizing cut-off frequency using a transconductance, capable of maintaining constant frequency characteristics regardless of changes in temperature, changes in power supply voltage and errors in fabrication.

The present disclosure relates generally to a trim circuit and a calibration method to facilitate current source calibration with changing temperatures and bias currents. In an example embodiment, a trim circuit is provided whose output current changes with the bias current and temperature, tracking current mismatch between two current sources (e.g., a reference current source and a current source under calibration) under varying environmental conditions (e.g., bias current and temperature).

In an example embodiment, the trim circuit may include a single CAL DAC whose output changes with bias current and temperature and tracks the current mismatch. In another example embodiment, the trim circuit can include multiple CAL DACs whose outputs change with bias current and temperature and tracks the current mismatch. In an example embodiment, the calibration method includes determining calibration settings of the CAL DACs through multiple measurements under different bias current and/or temperature conditions. Some embodiments may also include a circuit that generates current proportional to a product of transconductance of the current sources and a reference (e.g., internally generated) voltage.

According to a first aspect of the present invention, there is provided a circuit as set out in claim <NUM>.

The CAL DAC may include a plurality of cells, wherein each cell can be switched on or off, wherein current from the cell is aggregated into the output current of the trim circuit when the cell is switched on, wherein current from the cell is diverted away from the output current of the trim circuit when the cell is switched off.

The current generator may include an operational amplifier driving a voltage across a third resistor to be a bandgap voltage, wherein current across the another resistor is proportional to the bandgap voltage, wherein the third resistor has a substantially similar temperature coefficient to the two resistors.

Alternatively, the bias circuit may generate a gate voltage of yet another current source in the trim circuit, wherein the gate voltage causes a full scale current to the CAL DAC to be proportional to the transconductance.

The trim circuit may include a current mirror, wherein the current mirror is connected to a drain of the first current source and an output of the CAL DAC.

The trim circuit may include a voltage DAC connected to a gate of another current source, wherein the voltage DAC comprises a resistor string, wherein the voltage DAC generates a voltage proportional to a bandgap voltage, wherein an output current of the current source generates a current proportional to the transconductance and the bandgap voltage.

The voltage DAC may be driven by a current generator, wherein the current generator generates current proportional to the bandgap voltage.

The trim circuit may include a plurality of CAL DACs, wherein the output current of each CAL DAC changes with transconductance of the current source, wherein a sum of the output currents of the plurality of CAL DACs tracks the current mismatch under varying bias currents and temperatures.

Output pins of the plurality of CAL DACs may be connected to a drain of the current source.

Output pins of the plurality of CAL DACs may be connected to a drain of the current source through a current mirror.

The trim circuit may include at least a first CAL DAC and a second CAL DAC, wherein a first output current of the first CAL DAC varies with bias current only, and a second output current of the second CAL DAC varies with bias current and temperature.

output current of the second CAL DAC varies with bias current and temperature, wherein the output current of the trim circuit is a sum of the first output current and the second output current.

Multiple measurements with varying calibration settings of the first CAL DAC and the second CAL DAC may provide increased accuracy to track the current mismatch between the two current sources under disparate bias currents and temperatures.

Varying the calibration settings may comprise: setting the second output current to zero; varying calibration settings of the first CAL DAC to force the output current of the trim circuit to match the current mismatch; changing bias current; holding calibration settings of the first CAL DAC at the previously set values while varying calibration settings of the second CAL DAC to force the output current of the trim circuit to match the current mismatch; and sequentially varying calibration settings of the first CAL DAC and the second CAL DAC at different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under varying bias currents and temperatures.

The method may further include changing the temperature substantially simultaneously with the bias current.

The method may further include varying calibration settings of the first CAL DAC and the second CAL DAC under different temperatures until the output current of the trim circuit substantially accurately tracks the current mismatch between two current sources under disparate bias currents and temperatures.

The second output current may vary with transconductance of the current sources.

across the another resistor is proportional to the bandgap voltage, wherein the another resistor is substantially similar in type to the two resistors.

Clause <NUM>. The circuit of Clause <NUM>, wherein the bias circuit generates a gate voltage of yet another current source in the trim circuit, wherein the gate voltage causes a full scale current to the CAL DAC to be proportional to the transconductance.

Clause <NUM>. The circuit of Clause <NUM>, wherein the trim circuit includes a voltage DAC connected to a gate of another current source, wherein the voltage DAC comprises a resistor string, wherein the voltage DAC generates a voltage proportional to a bandgap voltage, wherein an output current of the current source generates a current proportional to the transconductance and the bandgap voltage.

Clause <NUM>. The circuit of Clause <NUM>, wherein the voltage DAC is driven by a current generator, wherein the current generator generates current proportional to the bandgap voltage.

Clause <NUM>. The circuit of Clause <NUM>, wherein at least one of the following applies:.

Clause <NUM>. The circuit of Clause <NUM>, wherein one or more of the following applies:.

Clause <NUM>. A method for calibrating a trim circuit comprising at least a first CAL DAC and a second CAL DAC, the method comprising:
varying calibration settings of the first CAL DAC and the second CAL DAC under different bias currents until an output current of the trim circuit substantially accurately tracks a current mismatch between two current sources under disparate bias currents and temperatures, wherein a first output current of the first CAL DAC varies with bias current only, and a second output current of the second CAL DAC varies with bias current and temperature, wherein the output current of the trim circuit is a sum of the first output current and the second output current.

Clause <NUM>. The method of Clause <NUM>, wherein one or more of the following applies:.

Clause <NUM>. The method of Clause <NUM>, wherein varying calibration settings comprises:.

Clause <NUM>. The method of Clause <NUM>, further comprising changing the temperature substantially simultaneously with the bias current.

Clause <NUM>. The method of Clause <NUM>, further comprising varying calibration settings of the first CAL DAC and the second CAL DAC under different temperatures until the output current of the trim circuit substantially accurately tracks the current mismatch between two current sources under disparate bias currents and temperatures.

<FIG> is a simplified block diagram illustrating a system <NUM> comprising a trim circuit <NUM> to facilitate current source calibration tracking temperature and bias current. Trim circuit <NUM> can generate an output current that tracks and compensates for current mismatch between current sources <NUM>(<NUM>) and a reference current source (not included in the figure) under varying environmental conditions. In an example embodiment, current source <NUM>(<NUM>) may represent a current source under calibration, which can comprise a cascode device <NUM>(<NUM>). Trim circuit <NUM> can include a current source <NUM> comprising an active electronic component (e.g., transistor). In an example embodiment, the gate voltage of current source <NUM> is not tied to the gate voltage of one of the external current sources (e.g., <NUM>(<NUM>)). A bias circuit <NUM> generates the gate voltage of current source <NUM> such that the full scale current of trim circuit <NUM> is proportional to the product of transconductance (gm) of current source <NUM> and an internally generated reference voltage Vref (e.g., gm(I, T)Vref). In one example Vref may be a constant factor of a bandgap voltage reference (e.g., temperature and load independent voltage, typically <NUM>.

Each cell <NUM> of trim circuit <NUM> may include a portion of a current splitter and a switch configured according to SAR logic (or other suitable logic) to direct the current from current source <NUM> to either the drain of current source <NUM>(<NUM>) (thereby increasing the output current of trim circuit <NUM>) or discarded to a common return current node <NUM> (e.g., which may be common to substantially all calibration DACs in system <NUM>). Cells <NUM> and current source <NUM> may collectively comprise a CAL DAC <NUM>. As used herein, a "CAL DAC" is any suitable digital to analog converter circuit that can be used to calibrate other circuits for various outputs (e.g., current mismatch between two current sources).

In some embodiments, each cell <NUM> can be switched on or off; current from each cell <NUM> is aggregated into the output current of trim circuit <NUM> when the cell is switched on, and current from the cell is diverted away from the output current of trim circuit <NUM> to return <NUM> when cell <NUM> is switched off. In some embodiments, SAR logic may be used to configure each cell to be turned on or off. The on or off position of each cell <NUM> may be collectively saved to a digital value, called the 'CAL DAC value. ' An output of CAL DAC <NUM> may be proportional to the CAL DAC value.

In many embodiments, trim circuit <NUM> may behave like a single DAC with its output current tracking transconductance (e.g., gm(I, T)ΔVTH), which is proportional to bias current and temperature. As temperature T and/or bias current I changes, the current mismatch between current sources <NUM>(<NUM>) and the reference current source may change. The output current of trim circuit <NUM> tracks the transconductance, which varies with temperature T and/or bias current I, and therefore the output current also changes accordingly. Thus, the output current can compensate for increased (or decreased) current mismatch between current sources <NUM>(<NUM>) and the reference current source due to varying temperature and/or bias current.

Thus, embodiments of system <NUM> include current source <NUM>(<NUM>) with calibrated trim circuit <NUM>, where an output current of trim circuit <NUM> varying with transconductance of current source <NUM>(<NUM>) and tracking a current mismatch between current source <NUM>(<NUM>) and another (e.g., reference) current source under varying bias currents and temperatures. In various embodiments, trim circuit <NUM> comprises CAL DAC <NUM> whose output current changes with transconductance of current source <NUM>(<NUM>) and tracks the current mismatch under varying bias currents and temperatures.

The bias circuit <NUM> comprises a current generator generating current proportional to a bandgap voltage; two substantially identical resistors causing a voltage drop proportional to the current; and a differential transistor pair coupled to the current generator and the two resistors, where gate voltages of the differential transistor pair differ by twice the voltage drop, and an output current of the differential transistor pair (which is a difference between the drain current of the differential transistor pair) is proportional to the transconductance. The current generator may comprise an operational amplifier driving a voltage across a resistor to be a bandgap voltage, such that current across the resistor is proportional to the bandgap voltage. The resistor of the current generator may be substantially similar in type to the two resistors of bias circuit <NUM>.

In some embodiments, bias circuit <NUM> may generate a gate voltage of current source <NUM> in trim circuit <NUM> that can cause a full scale current of CAL DAC <NUM> to be proportional to the transconductance. In some other embodiments, trim circuit <NUM> includes CAL DAC <NUM> connected to a current mirror, which may be connected to a drain of current source <NUM>(<NUM>). In a general sense, the "current mirror" is a circuit configured to copy a current through one active device by controlling the current in another active device, keeping the output current constant regardless of loading. In some yet other embodiments, trim circuit <NUM> may include a voltage DAC connected to a gate of current source <NUM>. The voltage DAC may comprise a plurality of resistors; the output of the voltage DAC may be based on an input digital code.

In some embodiments, trim circuit <NUM> may comprise a plurality of CAL DACs, where the output current of each CAL DAC changes with transconductance of the current source, where a sum of the output currents of the plurality of CAL DACs tracks the current mismatch under varying bias currents and temperatures. The output pins of the plurality of CAL DACs may be connected to a drain of current source <NUM>(<NUM>). In some embodiments, the plurality of CAL DACs may be connected to a drain of current source <NUM>(<NUM>) through a current mirror.

In some embodiments, trim circuit <NUM> may comprise a plurality of CAL DACs, where a portion of the plurality of CAL DACs may provide output currents varying only with bias current; and a remaining portion of the plurality of CAL DACs may provide output currents varying with the transconductance of the current source (e.g., varying with both bias current and temperature), where a sum of the output currents of the plurality of CAL DACs tracks the current mismatch under varying bias currents and temperatures.

In some embodiments, trim circuit <NUM> comprises at least a first CAL DAC and a second CAL DAC, where a first output current of the first CAL DAC varies with bias current only, and a second output current of the second CAL DAC varies with bias current and temperature. The CAL DAC values of the first and second CAL DACs can be determined through multiple measurements under different bias currents and or temperature. According to some embodiments, a method for calibrating such a trim circuit comprises repeatedly varying calibration settings (e.g., settings of switches in the CAL DAC circuit, for example, that specifies whether the switch is turned on or off) of the first CAL DAC and the second CAL DAC under varying bias currents until an output current of the trim circuit substantially accurately tracks a current mismatch between two current sources under varying bias currents and temperatures.

For example, the method may include setting the second output current to zero, varying calibration settings of the first CAL DAC to force the output current of the trim circuit to match the current mismatch, changing bias current, holding calibration settings of the first CAL DAC at the previously set values while varying calibration settings of the second CAL DAC to force the output current of the trim circuit to match the current mismatch, and sequentially varying calibration settings of the first CAL DAC and the second CAL DAC at different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under varying bias currents and temperatures.

In some embodiments, the method may further comprise changing the temperature substantially simultaneously with the bias current and varying calibration settings of the first CAL DAC and the second CAL DAC under varying temperatures until the output current of the trim circuit substantially accurately tracks the current mismatch between two current sources under varying bias currents and temperatures. SAR logic may be used to vary the calibration settings in some embodiments.

Turning to <FIG> is a simplified block diagram illustrating another embodiment of system <NUM>, wherein transistors, including current source <NUM>(<NUM>), cascode device <NUM>(<NUM>) and current source <NUM> comprise PMOS transistors. The operations of trim circuit <NUM> according to the embodiment are virtually identical when the transistors comprise NMOS transistors, as illustrated in the previous <FIG>.

Turning to <FIG> is a simplified block diagram illustrating example details of trim circuit <NUM> according to another embodiment of system <NUM>. Trim circuit <NUM> includes CAL DAC <NUM> (e.g., comprising switches and trim circuits that can be turned on according to SAR logic). CAL DAC <NUM> may be driven by a bias circuit (not shown) which can generate current proportional to transconductance (e.g., gmVref) of current source <NUM>(<NUM>). Thus, the full scale current of CAL DAC <NUM> may be proportional to transconductance. Trim circuit <NUM> also includes a current mirror <NUM>. Current mirror <NUM> is not limited to the simple circuit shown in the figure and can be any type of current mirror according to the broad scope of the embodiments. The CAL DAC value of CAL DAC <NUM> can be determined through generally known methods to be a suitable fraction of the full scale current. In some embodiments, the transistors of current mirror <NUM> can be configured (e.g., designed) to affect the current output from current source <NUM> within CAL DAC <NUM>, for example, based on the CAL DAC value.

Turning to <FIG> is a simplified block diagram illustrating example details of trim circuit <NUM> according to another embodiment of system <NUM>. Trim circuit <NUM> can include a plurality of CAL DACs <NUM>(<NUM>)-<NUM>(N), with each CAL DAC having a different environmental dependence. For the sake of simplicity, two CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>) are shown in the figure. CAL DAC <NUM>(<NUM>) may be driven by a bias circuit (not shown) which can generate current proportional to transconductance (e.g., gmVref) of current source <NUM>(<NUM>). Thus, the full scale output current of CAL DAC <NUM>(<NUM>) may be proportional to transconductance. In some embodiments, output current of CAL DAC <NUM>(<NUM>) may also vary with transconductance. In other embodiments, output current of CAL DAC <NUM>(<NUM>) may vary only with bias current. Various other environmental dependencies may be included within the broad scope of the embodiments.

Turning to <FIG> is a simplified block diagram illustrating example details of trim circuit <NUM> according to another embodiment of system <NUM>. Trim circuit <NUM> can include two CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>), and current mirror <NUM>. The full scale current of CAL DAC <NUM>(<NUM>) may be proportional to bias current I, for example, to track <MAT>, whereas the full scale current of CAL DAC <NUM>(<NUM>) may be proportional to gmVref, for example, to track gmΔVTH. In some embodiments, CAL DAC <NUM>(<NUM>) may be driven by bias circuit <NUM> (not shown) that generates current proportional to the transconductance. Current mirror <NUM> may feed a sum of output currents of CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>) to current source <NUM>. Current mirror <NUM> is not limited to the simple circuit shown in the figure and can be any type of current mirror according to the broad scope of the embodiments.

Turning to <FIG> is a simplified block diagram illustrating example details of a current generator <NUM> according to an embodiment of system <NUM>. VBC is the bandgap voltage generated by external circuitry (not shown). Voltage across resistor <NUM> (whose resistance is RI) is fixed to VBC by op amp <NUM>. Therefore, IR, current through resistor <NUM>, is VBG/RI. Note that although one example circuit and related components have been illustrated herein, various other circuits and components can be used to achieve the functionalities described herein within the broad scope of the embodiments.

Turning to <FIG> is a simplified block diagram illustrating a circuit <NUM> configured to generate output current proportional to gmVref according to an embodiment of system <NUM>. Current generator <NUM> generating current IR can be copied by a current mirror suitably, with a bias voltage Vb applied between the two current generators <NUM>. Resistors <NUM>(<NUM>) and <NUM>(<NUM>) may comprise a same type of resistor, having resistance R. In various embodiments, resistors <NUM>(<NUM>) and <NUM>(<NUM>) may comprise the same type of resistor as resistor <NUM>, which is used in current generator <NUM>. Thus, a ratio of resistances, namely R/RI may be invariant with temperature and a constant in various environments. In an example embodiment, the internally generated reference voltage Vref may be defined to be two times the bandgap voltage VBG and ratio of the resistances R and RI: <MAT>.

A differential transistor pair comprising transistors <NUM>(<NUM>) and <NUM>(<NUM>), along with an appropriate current mirror biasing stage <NUM> may be included in circuit <NUM>. Note that the differential transistor pair with its current-mirror biasing stage may be made from matched-pair devices to minimize imbalances from one side of the differential transistor pair to the other. The gate voltages of differential transistor pair <NUM>(<NUM>) and <NUM>(<NUM>) may be Vb - IRR and Vb + IRR, respectively, where Vb is the bias voltage. The output current, which may be accessed at current mirror <NUM>, is a difference between the drain current of the differential pair <NUM>(<NUM>) and <NUM>(<NUM>). The difference in drain current is gmVref, where gm is the transconductance of transistor <NUM>(<NUM>).

Turning to <FIG> is a simplified block diagram illustrating details of an example bias circuit <NUM> according to an embodiment of system <NUM>. Circuit <NUM> configured to generate output current proportional to gmVref may be connected to a diode <NUM> to generate a voltage (e.g., Vcal) that can force the output current of CAL DAC <NUM> to be proportional to transconductance and Vref(e.g., gmVref). Note that a body diode comprising a MOSFET is used for diode <NUM> in the figure; however, any suitable generic diode or other component that blocks current in one direction can be used within the broad scope of the embodiments. Current generator <NUM> may be included in circuit <NUM> with appropriate current mirrors <NUM> and other transistors suitably to supply current IR to differential transistor pair <NUM>(<NUM>) and <NUM>(<NUM>). Note that current proportional to gmVref flows out of bias circuit <NUM> according to the example embodiment shown herein. Various other combinations of components can also be used to achieve the functionalities described herein within the broad scope of the embodiments.

Turning to <FIG> is a simplified block diagram illustrating details of another example bias circuit <NUM> according to another embodiment of system <NUM>. Circuit <NUM> configured to generate output current proportional to gmVref may be connected to a diode <NUM> to generate a voltage (e.g., Vcal) that can force the output current of trim circuit <NUM> to be proportional to transconductance and Vref (e.g., gmVref), for example, when CAL DAC <NUM> is connected to current source <NUM> within trim circuit <NUM>, and the output therefrom is directly connected to the drain of current source <NUM>(<NUM>). Note that a body diode comprising a MOSFET is used for diode <NUM> in the figure; however, any suitable generic diode or other component that blocks current in one direction can be used within the broad scope of the embodiments.

Current generator <NUM> may be included in circuit <NUM> with appropriate current mirrors <NUM> and other transistors suitably to supply current IR to differential transistor pair <NUM>(<NUM>) and <NUM>(<NUM>). Note that the gate voltages of transistors <NUM>(<NUM>) and <NUM>(<NUM>) are swapped when compared to the embodiment described with reference to the previous figure. Note that current proportional to gmVref flows into bias circuit <NUM> according to the example embodiment shown herein. Various other combinations of components can also be used to achieve the functionalities described herein within the broad scope of the embodiments.

Turning to <FIG> is a simplified diagram illustrating an example CAL DAC <NUM> (and other details) according to an embodiment of system <NUM>. Trim circuit <NUM> may comprise a voltage DAC <NUM> driven by current generator <NUM>. The gate of transistor <NUM> may be connected to voltage DAC <NUM> whose output is a voltage based on a digital input. Voltage DAC <NUM> may comprise a resistor string including switches <NUM> and resistors <NUM>. Current generated by current generator <NUM> flowing through the resistor string may generates different voltages at each internal resistor's nodes. Therefore the voltage drop across the resistors may be proportional to the bandgap voltage (Vref) and may be constant. A digital input may control switch <NUM>, select a voltage and output the voltage (proportional to Vref). Therefore the current of transistor <NUM> may be gmVvoltage DAC. gm (where gm is transconductance of transistor <NUM>, and VvoltageDAC is the output voltage of voltage DAC <NUM>) is designed to be proportional to gm of current source <NUM>(<NUM>); thus trim circuit may generate a current proportional to gmVref.

Turning to <FIG> are simplified diagrams illustrating certain operational details of calibrating trim circuit <NUM> according to an embodiment of system <NUM>. If m CAL DAC values are to be determined, at least m data points may be required. At least m measurements may be performed under m different environments such as different temperature or bias current to obtain at least m data points. Changing temperature can be time consuming, costly and probably impractical for production test. Changing bias currents is more preferable for testing. Thus, the m CAL DAC values can be extracted from the m measurements.

Assume that trim circuit <NUM> comprises at least two CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>). Assume, merely as an example, and not as a limitation that the output current of CAL DAC <NUM>(<NUM>) varies with the bias current I, and the output current of CAL DAC <NUM>(<NUM>) varies with gmVref (and thus varies with both temperature and bias current). Thus, a unit current of CAL DAC <NUM>(<NUM>) is U<NUM> ∝ I, and a unit current of CAL DAC <NUM>(<NUM>) is U<NUM> ∝ gmVref. The current mismatch between the reference current source (e.g., <NUM>(<NUM>)) and the current source to be calibrated (e.g., <NUM>(<NUM>)) is <MAT> gm(I, T)ΔVTH and can be expressed as: <MAT> where <MAT> and <MAT>.

For example, assume that the unit current of CAL DAC <NUM>(<NUM>) U<NUM> ∝ I is 300nA and the unit current of CAL DAC <NUM>(<NUM>) U<NUM> ∝ gmVref is 200nA under certain operating conditions. Assume that the current mismatch, <MAT>, where <MAT> is <NUM>. 2uA and -gm(I, T)ΔVTH is 2uA. In various embodiments, the CAL DAC values may be configured to match with the current mismatch; thus, CAL DAC value of CAL DAC <NUM>(<NUM>) <MAT> and CAL DAC value of CAL DAC <MAT>.

The calibration method includes an initial cycle and n subsequent cycles n, which can be any number. Each cycle can include at least three steps (e.g., operations). Assume that C<NUM> and C<NUM> are CAL DAC values of CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>), respectively after the initial cycle and C1n and C2n are CAL DAC values of CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>), respectively after the n-th cycle. Assume further that a residue error of CAL DAC <NUM>(<NUM>) is defined as <MAT> after n-th cycle. After calibration, the CAL DAC values C1n and C2n may be equal to X<NUM> and X<NUM>, respectively and R2n may approach <NUM>.

In initial step <NUM> as indicated in <FIG>, C<NUM> is set to be <NUM> and only CAL DAC <NUM>(<NUM>) is calibrated to generate an output current equal to a target current mismatch. Note that C<NUM> is set to <NUM> merely for convenience; C<NUM> can be set to any suitable value based on particular needs. An example embodiment may implement SAR logic as a possible way for measurement. R<NUM> is <NUM>% after the initial cycle. CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI <NUM>(<NUM>) between current sources <NUM>(<NUM>) and <NUM>(<NUM>) is denoted as current contribution <NUM>(<NUM>) and CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI is denoted as current contribution <NUM>(<NUM>). The output current of trim circuit <NUM> may be denoted as Ical <NUM>(<NUM>). Ideally, Ical <NUM>(<NUM>) would be equal to current mismatch ΔI <NUM>(<NUM>), and when both CAL DAC <NUM>(<NUM>) and CAL DAC <NUM>(<NUM>) are calibrated appropriately to varying bias current and temperature, Ical <NUM>(<NUM>) may include appropriate contributions from CAL DAC <NUM>(<NUM>) and CAL DAC <NUM>(<NUM>). In initial cycle <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>), namely, C<NUM>, may be set (e.g., configured, determined, established, estimated, approximated, etc., based on SAR logic or other suitable logic) to obtain Ical <NUM>(<NUM>) while holding the output current of CAL DAC <NUM>(<NUM>) (C<NUM>) at <NUM>.

In next step <NUM> as shown in <FIG>, the current source bias current may change from I to Im and the temperature may be kept constant or ignored (e.g., temperature can vary without affecting the results). U<NUM>(I) and U<NUM>(I, T) can change differently (e.g., because of their different dependencies on bias current). As a result, CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI <NUM>(<NUM>) between current sources <NUM>(<NUM>) and <NUM>(<NUM>) may be changed to current contribution <NUM>(<NUM>) and CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI <NUM>(<NUM>) may be changed to current contribution <NUM>(<NUM>); Ical <NUM>(<NUM>) may also be reduced to C<NUM>U<NUM>(IM) and the may no longer be equal to Ical <NUM>(<NUM>). Assume that U<NUM>(IM) = α<NUM>U<NUM>(I) and U<NUM>(IM,TM) = α<NUM>U<NUM>(I, T), <MAT>. The difference between the current mismatch ΔI <NUM>(<NUM>) and the target mismatch Ical <NUM>(<NUM>) in step <NUM> is: <MAT>.

In next step <NUM>, as shown in <FIG>, CAL DAC value of CAL DAC <NUM>(<NUM>) may be held to be C<NUM>. Thus, contribution of CAL DAC <NUM>(<NUM>) to Ical <NUM>(<NUM>) may be indicated as 66A, and may remain equal to Ical <NUM>(<NUM>) from previous step <NUM>. Only CAL DAC <NUM>(<NUM>) may be used in the calibration measurement to force Ical <NUM>(<NUM>) to equal current mismatch ΔI <NUM>(<NUM>). For example, CAL DAC value of CAL DAC <NUM>(<NUM>) may be determined through SAR logic (or other suitable logic) to get an output current 66B, which when added to 66A, results in Ical <NUM>(<NUM>) being equal to current mismatch ΔI <NUM>(<NUM>). The CAL DAC value of CAL DAC <NUM>(<NUM>) is: <MAT> When α<NUM>=<NUM>/<NUM>, and α<NUM>=<NUM>/<NUM>, C<NUM> = <NUM>.

In next step <NUM>, as shown in <FIG>, the current source current may be restored to I. As a result, current mismatch ΔI <NUM>(<NUM>) may revert back to current mismatch ΔI <NUM>(<NUM>); CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI <NUM>(<NUM>) may revert back to current contribution <NUM>(<NUM>); and CAL DAC <NUM>(<NUM>)'s contribution to current mismatch ΔI <NUM>(<NUM>) may revert back to current contribution <NUM>(<NUM>). CAL DAC value of CAL DAC <NUM>(<NUM>) may be held to be C<NUM>, thereby fixing contribution of CAL DAC <NUM>(<NUM>) to Ical <NUM>(<NUM>) at 66B, from previous step <NUM>. Configuration settings of CAL DAC <NUM>(<NUM>) may be changed appropriately to obtain a CAL DAC value of 66A', which when added to 66B, results in Ical <NUM>(<NUM>) being equal to current mismatch ΔI <NUM>(<NUM>). The residue error of CAL DAC <NUM>(<NUM>) may be: <MAT> <MAT> <MAT>.

It can be observed that R<NUM> is reduced and C<NUM> and C<NUM> are closer to X<NUM> and X<NUM>. By repeating steps <NUM>, <NUM> and <NUM> for n cycles, residue error of CAL DAC <NUM>(<NUM>) may be reduced to: <MAT> which approaches <NUM> towards the n-th cycle; C<NUM>n and C<NUM>n approaches X<NUM> and X<NUM>.

In another example embodiment, CAL DAC <NUM>(<NUM>) and CAL DAC <NUM>(<NUM>) may be swapped in all steps. In some embodiments, the bias current I may be held at a constant value and only temperature T may be changed. In some embodiments, both bias current and temperature may be changes substantially simultaneously.

Turning to <FIG> is a simplified flow diagram illustrating example operations <NUM> that may be associated with a calibration method according to embodiments of system <NUM>. Assume that trim circuit <NUM> comprises at least two CAL DACs <NUM>(<NUM>) and <NUM>(<NUM>). Assume, merely as an example, and not as a limitation that the output current of CAL DAC <NUM>(<NUM>) varies with the bias current I, and the output current of CAL DAC <NUM>(<NUM>) varies with gmVref (and thus varies with both temperature and bias current). The operations may start at <NUM>. At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be set to zero. At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be determined (e.g., according to SAR logic, or other suitable logic) to force trim circuit output current (Ical) to equal current mismatch (ΔI) between current sources <NUM>(<NUM>) and <NUM>(<NUM>).

At <NUM>, current source bias current (and/or temperature in some embodiments) may be changed. At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be held at the previously determined value (at <NUM>). At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be determined (e.g., according to SAR logic, or other suitable logic) to force trim circuit output current (Ical) to equal current mismatch (ΔI) between current sources <NUM>(<NUM>) and <NUM>(<NUM>). At <NUM>, the current source bias current (and/or temperature) may be restored to original values. At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be held at the previously determined value (at <NUM>).

At <NUM>, the CAL DAC value of CAL DAC <NUM>(<NUM>) may be determined (e.g., according to SAR logic, or other suitable logic) to force trim circuit output current (Ica/) to equal current mismatch (ΔI) between current sources <NUM>(<NUM>) and <NUM>(<NUM>). At <NUM>, the bias current (and/or temperature) may be changed. A determination may be made at <NUM> if a predetermined number of iterations is over. If the predetermined number of iterations is over, the operations may end at <NUM>. Otherwise, the operations may loop back to <NUM>, and continue thereafter.

Note that in this Specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment", "example embodiment", "an embodiment", "another embodiment", "some embodiments", "various embodiments", "other embodiments", "alternative embodiment", and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

In the discussions of the embodiments above, the capacitors, clocks, DFFs, dividers, inductors, resistors, amplifiers, switches, digital core, transistors, and/or other components can readily be replaced, substituted, or otherwise modified in order to accommodate particular circuitry needs. Moreover, it should be noted that the use of complementary electronic chips, hardware, software, etc. offer an equally viable option for implementing the teachings of the present disclosure.

In one example embodiment, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic chip. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic chip and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc. Other components such as external storage, additional sensors, controllers for audio/video display, and other peripheral chips may be attached to the board as plug-in cards, via cables, or integrated into the board itself.

In another example embodiment, the electrical circuits of the FIGURES may be implemented as stand-alone modules (e.g., a chip with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic chips. Note that particular embodiments of the present disclosure may be readily included in a system on chip (SOC) package, either in part, or in whole. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the functionalities as described herein may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

It is also imperative to note that all of the specifications, dimensions, and relationships outlined herein (e.g., the number of components, logic operations, etc.) have only been offered for purposes of example and teaching only. The specifications apply only to one non-limiting example and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

Note that the activities discussed above with reference to the FIGURES are applicable to any integrated circuits that involve signal processing, particularly those that rely on synchronization signals to execute specialized software programs, or algorithms, some of which may be associated with processing digitized real-time data. Certain embodiments can relate to multi-DSP signal processing, floating point processing, signal/control processing, fixed-function processing, microcontroller applications, etc. In certain contexts, the features discussed herein can be applicable to medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be highly precise), and other digital-processing-based systems.

Moreover, certain embodiments discussed above can be provisioned in digital signal processing technologies for medical imaging, patient monitoring, medical instrumentation, and home healthcare. This could include pulmonary monitors, accelerometers, heart rate monitors, pacemakers, etc. Other applications can involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment and interior applications of any kind). Furthermore, powertrain systems (for example, in hybrid and electric vehicles) can apply the functionalities described herein in high-precision data conversion products in battery monitoring, control systems, reporting controls, maintenance activities, etc..

In yet other example scenarios, the teachings of the present disclosure can be applicable in the industrial markets that include process control systems that help drive productivity, energy efficiency, and reliability. In consumer applications, the teachings of the electrical circuits discussed above can be used for image processing, auto focus, and image stabilization (e.g., for digital still cameras, camcorders, etc.). Other consumer applications can include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. Yet other consumer applications can involve advanced touch screen controllers (e.g., for any type of portable media chip). Hence, such technologies could readily part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc..

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this Specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

The scope of the present invention is defined according to the embodiments of the appended independent claims.

Note that all optional features of the apparatus described above may also be implemented with respect to the method or process described herein and specifics in the examples may be used anywhere in one or more embodiments. In a first example, a system is provided (that can include any suitable circuitry, dividers, capacitors, resistors, inductors, ADCs, DFFs, logic gates, software, hardware, links, etc.) that can be part of any type of electronic device (e.g., computer), which can further include a circuit board coupled to a plurality of electronic components. The system can include means for calibrating a trim circuit comprising at least a first CAL DAC and a second CAL DAC, including means for varying calibration settings of the first CAL DAC and the second CAL DAC under varying bias currents until an output current of the trim circuit substantially accurately tracks a current mismatch between two current sources under varying bias currents and temperatures, wherein a first output current of the first CAL DAC varies with bias current only, and a second output current of the second CAL DAC varies with bias current and temperature, wherein the output current of the trim circuit is a sum of the first output current and the second output current.

The system can also include means for setting the second output current to zero; means for varying calibration settings of the first CAL DAC to force the output current of the trim circuit to match the current mismatch; means for changing bias current; means for holding calibration settings of the first CAL DAC at the previously set values while varying calibration settings of the second CAL DAC to force the output current of the trim circuit to match the current mismatch; and means for sequentially varying calibration settings of the first CAL DAC and the second CAL DAC at different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under varying bias currents and temperatures.

The system can also include means for changing the temperature substantially simultaneously with the bias current; and means for varying calibration settings of the first CAL DAC and the second CAL DAC under varying temperatures until the output current of the trim circuit substantially accurately tracks the current mismatch between two current sources under varying bias currents and temperatures.

Claim 1:
A circuit configured to track a change in current mismatch between a first current source and a reference current source under varying temperatures, the circuit comprising:
the first current source (<NUM>(<NUM>)), wherein the first current source comprises a first transistor having a first transconductance which varies with temperature, wherein the first current source is driven by a first bias voltage; and
a trim circuit (<NUM>) coupled to the first current source to supply an output current to the first current source for calibrating the first current source, the trim circuit comprising:
a bias circuit (<NUM>) configured to generate a bias current that varies with temperature, wherein the bias circuit comprises a differential transistor pair having a second transconductance which varies with temperature, wherein the variation of the second transconductance with temperature is proportional to the variation of the first transconductance with temperature, and wherein the bias current is a difference between the drain currents of the differential transistor pair and is proportional to the second transconductance of the differential transistor pair, wherein the bias circuit further comprises a current generator generating current proportional to a bandgap voltage, and two substantially identical resistors causing a voltage drop proportional to the current, wherein the differential transistor pair is coupled to the current generator and the two resistors, and wherein gate voltages of the differential transistor pair differ by twice the voltage drop; and
a calibration digital to analog converter, CAL DAC (<NUM>) configured to set the output current of the trim circuit, wherein a second bias voltage of the CAL DAC is independent of the first bias voltage and is derived from the bias current such that the output current of the trim circuit varies with temperature so as to track the change in current mismatch between the first current source and the reference current source under varying temperatures.