Patent Description:
In many conventional applications, an integrated circuit (IC) die of an electronic device is interconnected with other components of the electronic device using wire bonds. However, in certain high-current applications, the use of wire bonds may be impractical due to the number of wire bonds needed to carry the expected current load, which in turns increases the complexity involved in device assembly. Therefore, in such high-current applications, a clip interconnect may be used to provide for interconnection between the integrated circuit die and other components due to the high current carrying capacity of clip interconnects.

A cross section of a known electronic device <NUM> utilizing a clip interconnect is shown in <FIG>. The bottom face of an IC die <NUM> is bonded to a top surface of a die pad <NUM> of a leadframe through a die attach layer <NUM> (e.g., solder layer), and the top face of the IC die <NUM> is bonded to a bottom surface of a first portion 7a of a clip <NUM> through a solder layer <NUM>. The clip <NUM> has a second portion 7b extending from the first portion 7a at an angle thereto, with a bottom surface of the second portion 7b of the clip <NUM> being bonded to a top surface of a lead or leads <NUM> of the leadframe through a solder layer <NUM>.

During device assembly, a solder material is used to attach the bottom face of the IC die <NUM> to the top surface of the die pad <NUM>, the top face of the IC die <NUM> to the bottom surface of the first portion 7a of the clip <NUM>, and the top surface of the leads <NUM> to bottom surface of the section portion 7b of the clip <NUM>, after which point the electronic device <NUM> assembly is subjected to a controlled heating to form the solder layers <NUM>, <NUM>, and <NUM>. However, the solder material has volatile components (e.g., flux) therein that release bubbles of gas during solidification. If these bubbles of gas are trapped between the surfaces being bonded via the solder reflow process, voids within the solder layers, particularly solder layer <NUM>, are thereby formed. Shown in <FIG> is a cross sectional view of the solder layer <NUM>, including voids 6a formed therein. Such solder voids increase the thermal resistance between the layers, reducing heat dissipation capacity, creating local hot spots. Such solder voids also decrease the electrical conductivity between the layers, potentially degrading device performance.

In an attempt to ensure that such bubbles of gas are not trapped between the surfaces being bonded, the reflow process may be carefully optimized. However, this optimization is a trial and error process and grows in difficulty to perform as the IC die <NUM> and clip <NUM> increase in size.

Prior art is disclosed in documents <CIT>, <CIT> and <CIT>.

As such, further development into assembly techniques and clip designs is necessary.

Disclosed herein is an electronic device, including a first support substrate, with a second support substrate spaced apart from the first support substrate. An integrated circuit (IC) die has opposed first and second faces, the second face bonded to a first surface of the first support substrate. A conductive clip is formed by first and second portions each having opposed first and second surfaces, the first portion of the conductive clip being elongate and extending across the IC die, the first portion of the conductive clip having its second surface bonded to the first face of the IC die by a solder layer, the second portion of the conductive clip extending from the first portion away from the IC die toward the second support substrate such that its second surface is bonded to the first surface of the second support substrate.

The first surface of the conductive clip has a pattern formed therein, the pattern including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the first surface of the conductive clip from the depressed floor of the pattern to the second surface of the conductive clip. An encapsulating layer covers portions of the first support substrate, second support substrate, IC die, and conductive clip while leaving the first surface of the first portion of the conductive clip exposed to permit heat to radiate away therefrom.

The through-holes may be straight-cut, being equal in size and shape at the depressed floor of the pattern and at the second surface of the conductive clip.

The through-holes may expand in size from the depressed floor of the pattern through to the second surface of the conductive clip such that the size of the through-holes at the depressed floor is less than the size of the through-holes at the second surface of the conductive clip.

The through-holes may contract in size from the depressed floor of the pattern through to the second surface of the conductive clip such that the size of the through-holes at the depressed floor is larger than the size of the through-holes at the second surface of the conductive clip.

The through-holes may have cross sections that are circular in shape, or may have cross sections that are pill shaped.

The fins may extend upwardly from the depressed floor to a level of a highest point of the first surface of the first portion of the conductive clip.

The second surface of the first portion of the conductive clip may be planar.

The first support substrate may be a die pad of a leadframe, and the second support substrate may be at least one lead of a leadframe.

The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

Now described with reference to <FIG> is an electronic device <NUM> including a die pad <NUM> (e.g., part of a leadframe) and leads <NUM> (e.g., part of the leadframe) spaced apart from one another, with a conductive clip <NUM> (formed of e.g., copper) forming an interconnect therebetween. As will be explained below, the conductive clip <NUM> is specifically designed to alleviate concerns of the formation of solder voids during solder reflow.

In greater detail, the top surface of a die pad <NUM> is bonded to the bottom face of the IC <NUM> through a die attach layer <NUM> (e.g., a solder layer such as soft solder/Ag sintering). The conductive clip <NUM> includes a first portion <NUM> having a planar bottom surface bonded to the top face of the IC <NUM> through a die attach layer (e.g., a solder layer <NUM> such as soft solder/Ag sintering), and a second portion <NUM> extending from the first portion <NUM> laterally away from the IC <NUM> such that a planar bottom surface of the second portion <NUM> is bonded to the top surface of the leads <NUM> through a die attach layer <NUM> (e.g., a solder layer such as soft solder/Ag sintering). Observe that the second portion <NUM> of the conductive clip <NUM> has a stair-stepped shape defining a step down in height from the top face of the IC <NUM> to the top surface of the leads <NUM>. Observe also that the first portion <NUM> of the conductive clip <NUM> is elongate and extends across the IC <NUM>.

An encapsulation layer <NUM> extends from the top surfaces of the die pad <NUM> and leads <NUM> to be flush with a top surface of the first portion <NUM> of the conductive clip <NUM>, environmentally sealing the sides and bottom surface of the first portion <NUM>, environmentally sealing the IC <NUM>, and environmentally sealing the covered portion of the top surface of the die pad <NUM>, while leaving the top surface of the first portion <NUM> exposed. The encapsulation layer <NUM> also environmentally seals the second portion <NUM> and the covered portion of the top surface of the leads <NUM>. Notice that the encapsulation layer <NUM> also environmentally seals the gap between the die pad <NUM> and the leads <NUM>.

As has been explained above, during the solder reflow process, it is desired to prevent solder voids from forming in the solder <NUM> to the extent possible, thereby providing for more effective heat transfer from the IC <NUM> to the conductive clip <NUM>. To facilitate this, the first portion <NUM> of the conductive clip <NUM> has through-holes <NUM> defined therein. These through-holes <NUM> are shaped and positioned so as to permit the gasses released from volatile components during solder reflow to escape the solder layer <NUM> through the through-holes <NUM>, thereby eliminating the formation of solder voids by those gases and enhancing the cooling ability of the electronic device <NUM> as well as potentially enhancing the improving device performance by increasing electrical conductivity between the IC <NUM>, conductive clip <NUM>, and leads <NUM>.

The top surface of the first portion <NUM> of the conductive clip <NUM> being left exposed by the encapsulation layer <NUM> helps provide for the ability of heat in the clip <NUM> to radiate away from the clip <NUM> and dissipate. To enhance this effect, the top surface of the first portion <NUM> of the conductive clip <NUM> has its exposed surface area increased by a pattern <NUM> being defined thereon. The pattern <NUM> includes a depressed floor 25a defined by a plurality of interconnected a recesses or channels formed extending into the top surface of the first portion <NUM> of the conductive clip <NUM>, with projections or fins 25b (delimited by the recesses or channels) extending upwardly from the depressed floor 25a. The fins 25b may extend up to a level aligned with a highest point of other portions of the top surface of the first portion <NUM> of the conductive clip <NUM>, may extend to a level above the above the other highest point of other portions of the top surface of the first portion <NUM> of the conductive clip <NUM>, or may extend up to a level below a highest point of other portions of the top surface of the first portion <NUM> of the conductive clip <NUM>. By increasing the surface area of the top surface of the first portion <NUM> of the conductive clip <NUM>, heat can more easily radiate outwardly and away.

In the illustrative example of <FIG>, the through-holes <NUM> are circularly shaped and are uniform in diameter from the top surface of the first portion <NUM> of the conductive clip <NUM> through to the bottom surface of the first portion <NUM> of the conductive clip <NUM> (e.g., formed by a straight cut). However, the through-holes <NUM> may take other suitable shapes. For example, the through-holes <NUM>' may be elliptical in shape or may be pill shaped as shown in <FIG>. The through-holes <NUM>" may tapered in cut, wider at the top surface of the first portion <NUM> of the conductive clip <NUM> than at the bottom surface of the first portion <NUM> of the conductive clip <NUM>, as shown in <FIG>. The through-holes <NUM>‴ may instead be tapered in the cut in the opposite fashion, narrower at the top surface of the first portion <NUM> of the conductive clip <NUM> than at the bottom surface of the first portion <NUM> of the conductive clip <NUM>, as shown in <FIG>.

The spacing and pattern of the through-holes <NUM> may be adjusted depending upon the surface area of the top face of the IC <NUM> and the surface area of the top surface of the first portion <NUM> of the conductive clip <NUM>, depending upon the expected operating conditions of the IC <NUM>, and/or depending upon the specific composition of the solder layer <NUM>.

A method for making the electronic device <NUM> is now described. The method includes providing a substrate or leadframe carrying the die pad <NUM>, and bonding the bottom face of the IC <NUM> to the top surface of the die pad <NUM> through the solder layer <NUM>. The bottom surface of the first portion <NUM> of the conductive clip <NUM> is then bonded to the top face of the IC <NUM> through the solder layer <NUM>, and at this step, the bottom surface of the second portion <NUM> of the conductive clip <NUM> is bonded to the top surface of the leads <NUM> through the solder layer <NUM>. Thereafter, solder reflow is performed and the electronic device <NUM> is permitted to cool before the encapsulation layer <NUM> is deposited.

Claim 1:
An electronic device, comprising:
a first support substrate;
a second support substrate spaced apart from the first support substrate;
an integrated circuit (IC) die having opposed first and second faces, the second face bonded to a first surface of the first support substrate;
a conductive clip formed by first and second portions each having opposed first and second surfaces, the first portion of the conductive clip being elongate and extending across the IC die, the first portion of the conductive clip having its second surface bonded to the first face of the IC die by a solder layer, the second portion of the conductive clip extending from the first portion away from the IC die toward the second support substrate such that its second surface is bonded to the first surface of the second support substrate;
wherein the first surface of the conductive clip has a pattern formed therein, the pattern including a depressed floor with fins extending upwardly therefrom;
wherein through-holes extend through the first surface of the conductive clip from the depressed floor of the pattern to the second surface of the conductive clip; and
an encapsulating layer covering portions of the first support substrate, second support substrate, IC die, and conductive clip while leaving the first surface of the first portion of the conductive clip exposed to permit heat to radiate away therefrom.