Patent Description:
The embodiments of the disclosed devices and methods may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein. <CIT> describes a multi-display system and method for displaying tearing free video frames thereon. The present invention eliminates the conventional tearing defect by starting the pixel data updating of a display pattern after a last pixel of the display pattern has been displayed on a display device of the multi-display system having a lower refresh frequency, and pausing the pixel data updating of a specific pixel, which is not displayed on another display device of the multi-display system having a higher refresh frequency, until the specific pixel has been displayed. <CIT> describes an electronic device that includes a first display panel including a first clock generator and that generates a first signal according to the first clock generator in response to a screen update request signal, a second display panel including a second clock generator and that generates a second signal according to the second clock generator in response to a screen update request signal, and a controller that transmits the screen update request signal to the first display panel and the second display panel and that receives the first signal and the second signal and that compares the first signal and the second signal to adjust a clock of at least one of the first clock generator and the second clock generator. <CIT> describes a display apparatus, an electronic device including the same, and a method of operating the same are provided. The electronic device includes a display including a first region and a second region, a first driving module configured to generate processing information corresponding to a first image to be displayed in the first region of the display, and a second driving module configured to receive the processing information from the first driving module, and o compensate for a second image to be displayed in the second region of the display, based on the processing information. <CIT> describes that in an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state. <CIT> describes that a data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than <NUM>; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an ith virtual channel values Vci, an ith display driver executing corresponding operations in response to the command, while the rest n-<NUM> display drivers ignoring the command, wherein i is a natural number smaller than or equal to n. <CIT> describes that a processor for use in an electronic device is provided. The electronic device is capable of displaying and the processor has capability of switching a refresh rate for refreshing a display panel of the display device. The processor comprises: a refresh rate selection controller and a display controller. The refresh rate selection controller is configured to dynamically select one from a plurality refresh rates. The display controller is configured to control a driving device to refresh the display panel with the selected refresh rate and determine whether to adjust a data transmission rate over an interface between the processor and the driving device according to the selected refresh rate.

Described herein are devices and methods that synchronize multiple display panels. The synchronization may be achieved by varying blanking or timing between display frames. Without the synchronization, multiple display panels would operate asynchronously, presenting different timing requirements to a host processor. For instance, each display panel may have an integrated timing controller that would, in a single-display context, force the host processor to adapt a display rendering rate of the host processor to the clock or other timing specified by the timing controller. When two or more displays are connected to the same host, manufacturing variances lead to asynchronous operation of the displays. Left unaddressed, the asynchronous operation results in drift in the relative phase of the displays.

The devices and methods maintain the alignment of frames in a device having two or more asynchronously timed display panels. The synchronization provides for isochronous operation of the multiple display panels. Isochronous operation is achieved despite manufacturing variances or other offsets in clock or other refresh rates of the display controllers. The isochronous operation is also achieved without synchronizing clocks of the multiple timing controllers.

The synchronization uses timing indications provided by display controllers for the multiple display panels. The disclosed devices and methods delay a refresh of the multiple display panels until all of the timing indications are received, e.g., until the timing indication is received from each respective display controller of the device. Each timing indication is indicative of the display controller residing in a state ready for refresh of the corresponding display panel. In some cases, the timing indication is or includes a tearing effect (TE) or other timing signal provided by a display controller to prevent tearing on the corresponding display panel. The timing signal may be considered or configured as an anti-tearing timing signal. The anti-tearing or other timing signal may be used as part of a refresh delay technique, such as Adaptive Sync, directed to addressing the challenge presented by asynchronous host processor image data generation (e.g., rendering) and display refresh. The refresh delay technique allows an application processor to delay the writing of image data until the timing signal indicates that the display controller resides in the state ready for refresh. The refresh delay technique allows the timing controllers to insert extra blanking at the start or end of refresh timing of a display. The amount of extra blanking is controlled by the host processor, one or all of the display controllers, and/or another element, such as an external hardware element (e.g., a state machine), to provide host processor time to complete rendering of the content of a frame. In cases in which all of the display controllers implements instructions or otherwise controls the amount of extra blanking, one of the display controllers may be defined as a master or primary display controller. The master or primary display controller may be statically or dynamically configured during the operation of the device.

The disclosed devices and methods synchronize the multiple display panels by sending a refresh instruction. The instruction may be sent via a bus or other command interface, such as a Mobile Industry Processor Interface (MIPI) command mode serial interface. Alternatively or additionally, the disclosed devices and methods generate a trigger signal (e.g., a dedicated trigger signal) to maintain synchronization. The trigger signal may be useful when instructions or other data (e.g., data packets) are not being provided via the bus or other command interface. The bus or other interface may be disabled to save power. The interface may be disabled in connection with a host processor residing in a sleep or other reduced power state, such as when the host processor is not actively providing image data to the display controllers.

The disclosed devices and methods synchronize the multiple displays without forcing all displays to synchronize to a master clock. Avoiding a master clock declaration is useful. For instance, resorting to declaring that a particular display's clock is the master gives rise to complications when the particular display is not used, malfunctioning, etc. Without resorting to a master clock, any one or more of the displays of the disclosed devices may be enabled and disabled as desired without adversely affecting the synchronization.

The nature of the disclosed devices may vary considerably. For instance, the form factor of the devices may vary from handheld, worn, or other portable devices to desktop, wall-mounted, or other large scale devices. The devices may or may not be computing devices. For instance, the disclosed methods may be useful in connection with television monitors in addition to smartphones and tablets. The synchronization techniques described herein may be used with any dual- or multiple-display device. The disclosed devices may accordingly be considered or configured as systems.

<FIG> depicts a device <NUM> in which display synchronization is implemented in accordance with one example. The device <NUM> includes multiple displays. In this example, the multiple displays include two display panels <NUM>. Each display panel <NUM> may be configured as a thin-film transistor (TFT) panel. Each display panel <NUM> may be configured as, or include, a touchscreen. Each display panel <NUM> may accordingly include a touch sensor array disposed along a transparent cover or other layer of the display panel <NUM>. The device <NUM> may be or include any electronic device having the multiple display panels <NUM> display, including, for instance, a smartphone, tablet, notebook computer, or smart television or other monitor. The arrangement, size, shape, emission type, and other characteristics of the display panels <NUM> may vary accordingly. For example, the display panels <NUM> may or may not include a backlight unit. Additional display panels <NUM> may be included.

The display panels <NUM> may or may not be identical or similarly configured. In some cases, the display panels <NUM> are similarly configured but nevertheless exhibit differences arising from, for instance, manufacturing variances. The manufacturing variance may lead to a difference in a clock or refresh rates. For example, the internal clocks of display controllers for the display panels <NUM> may differ. The display panels <NUM> may nominally have a refresh rate of, for example, <NUM>. With the manufacturing variance, one display panel <NUM> may exhibit a refresh rate of about <NUM>. The other display panel <NUM> may exhibit a different refresh rate of about <NUM>. Left unaddressed, the difference in refresh rates results in asynchronous display refresh and eventually an offset between the display panels <NUM>.

The nature of, underlying reasons for, and other characteristics of the differences between the display panels <NUM> may vary. For instance, the difference(s) may arise from additional or alternative aspects of the display panels <NUM>. For example, the display panels <NUM> may exhibit different refresh rates due to different aging or usage profiles.

The arrangement of the display-related components of the device <NUM> may vary. For instance, the components of the device <NUM> for a particular one of the display panels <NUM> may be arranged in a respective display module. The components associated with one or more display panels <NUM> may be integrated to any desired extent. For example, a display controller for each panel <NUM> may be integrated with the display panel <NUM> in a display module and/or as a display unit.

The device <NUM> includes a host <NUM>. The host <NUM> may be a computer, computing unit, electronics unit, or other unit responsible for providing or generating image data for rendering on the display panels <NUM>. The host <NUM> includes a processor or processing unit <NUM>. The processor <NUM> is configured to generate the image data for rendering on the display panels <NUM>. In some cases, the processor <NUM> is configured as or otherwise includes an application processor.

The host <NUM> includes one or more memories <NUM>. The processor <NUM> may be configured via instructions and/or data provided via the memory <NUM>. Alternatively or additionally, the processor <NUM> includes integrated memory on which the instructions and/or other instructions are stored.

The processor <NUM> may be or include a general purpose, programmable processor. The memory <NUM> may be directly addressable by the processor <NUM>. Instructions and/or other data stored on the memory <NUM> may configure to the processor <NUM> to implement tasks and/or other operations. For instance, the operations may be directed to providing general graphics processing for the device <NUM>. The processor <NUM> thus generates or provides image data to be rendered on the display panels <NUM>. In some cases, the operations include implementing an operating system, and executing applications running with an environment established by the operating system. Alternative or additional operations may be implemented. For instance, the processor <NUM> may be configured to implement a number of background services for the device <NUM>, including, for instance, data communication services.

The processor <NUM> may include any number of processors, processing units, cores, or other elements. In the example of <FIG>, the processor <NUM> includes a central processing unit (CPU) <NUM> and a graphics processing unit (GPU) <NUM> integrated with one another as a system-on-a-chip (SOC). The extent of the integration may vary. For instance, the CPU <NUM> and the GPU <NUM> may be disposed on a separate integrated circuit (IC) chips in other cases. The GPU <NUM> (and/or other unit of the processor <NUM>) is configured to generate image data to support the general graphics processing for the device <NUM>. The image data may be representative of a variety of different types of images, including, for instance, any type of graphics, such as stylus strokes.

Instructions and/or other data for the processor <NUM> are stored on one or more storage units <NUM>. The storage unit <NUM> may be or include a flash storage or other drive or other non-volatile storage unit. Instructions or data are read from the storage device <NUM> and then written to the memory <NUM> for use by the processor <NUM>.

The memory <NUM> may be or include, for example, a random access memory (RAM) unit. Additional or alternative memories may be included. For instance, the device <NUM> may include one or more read-only memories (ROM) on which firmware and other instructions are stored.

The processor <NUM>, the memory <NUM>, and the storage unit <NUM> may be considered to be components of a computing system of the device <NUM>. These components may thus be referred to herein as system level components. System level components are involved in general processing, memory, storage, and control of various subsystems, or modules, of the device <NUM>. For instance, the computing system may be considered to include components involved in directing the display panels <NUM> and other input/output devices, modules, or units of the device <NUM>. In contrast, processing, memory, or other components directed to a specific function, such as display functionality, may be considered to be at a module level, as in components of the display module. The device <NUM> has a number of additional subsystems or modules (e.g., a respective subsystem for each input/output component, such as a touch subsystem), as opposed to a single system level.

The processor <NUM> may be configured to operate in one or more low power modes. Graphics functionality of the processor <NUM> may be suspended while the processor <NUM> resides in the low power mode. For instance, the processor <NUM> may discontinue the generation of image data while residing in a low power mode associated with the implementation of a panel self refresh routine. The low power modes may alternatively or additionally include one or more sleep modes in which the graphics functionality of the processor <NUM> is suspended. The suspension of operations in a sleep mode extends beyond the graphics functionality of the processor <NUM>. For instance, the processor <NUM> is deactivated to a greater extent in a sleep mode than the deactivation that occurs during, for example, implementation of a panel self refresh routine. Any number of general purpose operations of the processor <NUM> are also suspended.

The host <NUM> may include additional, fewer, or alternative components. For example, the host <NUM> may include a touch controller and/or digitizer to process data generated by a touch sensor array. Any number of processors, memories, and/or storage units may be included. The components of the host <NUM> may be integrated with one another and/or other elements of the device <NUM> to any desired extent.

The device <NUM> includes a display controller <NUM> for each display panel <NUM>. Each display controller <NUM> is configured to control a corresponding panel of the display panels <NUM>. The display controller <NUM> may be or include one or more integrated circuits, such as a display driver integrated circuit (DDIC). Each display controller <NUM> may be integrated with other components or elements of a display and/or display module that includes the corresponding display panel <NUM>. In the example of <FIG>, each display controller <NUM> is or includes a circuit or other unit discrete from the display panel <NUM>. In other cases, one or more aspects of each display controller <NUM> and the corresponding display panel <NUM> may integrated to any desired extent. Alternatively or additionally, one or more aspects of each display controller <NUM> may be integrated with the host <NUM>.

Each display controller <NUM> receives image data from the processor <NUM> for the images to be rendered on the corresponding display panel <NUM>. The image data may be provided by the processor <NUM> on a bus or other interface <NUM>. The interface <NUM> may accordingly be referred to as an image data interface. In some cases, the interface <NUM> is configured as a command interface, such as a MIPI command interface, via which instructions may also be provided to the display controller <NUM>. Other types of interfaces, and the corresponding protocols, may be used. For instance, each interface <NUM> may be configured in accordance with the embedded DisplayPort (eDP) protocol.

Each display controller <NUM> is configured to generate pixel control signals from the image data for the corresponding display panel <NUM>. The pixel control signals from each display controller <NUM> may be provided by a respective set of electrical connections <NUM> that connect the display controller <NUM> to the display panel <NUM>. The electrical connections <NUM> may be or include a ribbon cable, other flex cable, or other connector. In some cases, the pixel control signals are configured to direct one or more source (or data) drivers and one or more gate drivers of the display panel <NUM>. Together, the source and gate drivers send control signals to individually control the thin-film transistors of each pixel (or sub-pixel) of the display panel <NUM>. Alternatively or additionally, the display controller <NUM> may or may not include the source, gate, and/or other drivers.

Each display controller <NUM> may be configured to process the image data from the processor via a processing pipeline. The display controller <NUM> includes a number of components or elements disposed along the pipeline. In the example of <FIG>, the display controller <NUM> includes a receiver <NUM>, a memory controller <NUM>, and one or more pixel operations units <NUM>. The order of the elements along the pipeline may vary from the example shown. For instance, one or more of the pixel operations units <NUM> may be disposed before one of the other depicted elements. Additional, fewer or alternative elements may be included. For instance, the pipeline may include an ink rendering engine for incorporating image data associated with stylus and other touch events.

The receiver <NUM> may be configured to process the image data provided by the processor <NUM> via the interface <NUM>. In some cases, the image data is provided in packet form, e.g., via packetized data transmissions. For example, the image data may be provided in packets formatted and otherwise formed in accordance with the MIPI, eDP or other protocols. Other video interface standards or protocols may be used, such as the DisplayPort interface protocol.

The receiver <NUM> may be configured to generate pixel data from the image data provided by the processor <NUM>. For instance, the receiver <NUM> may convert the packets of the image data into respective data for each pixel of the display panel <NUM>. The pixel data may be assembled or arranged by the receiver <NUM> into respective frames (frame data) to be rendered concurrently (or effectively concurrently) on the display panel <NUM>. Alternatively, the frame data is assembled or otherwise derived from the image data by another component along the pipeline. For example, in some cases, the frame data is derived from the pixel data by the memory controller <NUM>.

The pixel data or the frame data is provided to the memory controller <NUM>. The memory controller <NUM> is configured to store the frame data derived from the image data in a memory <NUM>. For example, the frame data for each frame may be stored in the memory <NUM> as a respective dataset. The memory <NUM> may thus be configured as or otherwise considered a frame buffer. The memory <NUM> may include one or more random access memory (RAM) or other units. In some cases, the memory controller <NUM> and the memory <NUM> are configured to support and/or otherwise implement a panel self refresh routine via storage of the frame data in the memory <NUM>. Alternatively or additionally, the memory <NUM> is used to support other routines or procedures, such as frame rate control and overdrive procedures.

The pixel operation unit(s) <NUM> are configured to use the frame data to generate pixel control signals for the display panel <NUM>. The pixel control signals are configured for use by the source and gate drivers. The pixel control signals are representative of the timing involved in updating or otherwise refreshing the images rendered via the display panel <NUM>. The display controller <NUM> may determine or otherwise control the timing of the pixel control signals. The timing is determined to appropriately render the images representative of the image data received from the processor <NUM> given the refresh rate and other characteristics of the display <NUM>. For example, the timing established by the pixel operations unit(s) <NUM> may involve establishing the timing of raster refresh operations and vertical refresh operations for the display panel <NUM>. For these and other reasons, each display controller <NUM> may be considered to be, or include, or be referred to as, a timing controller (e.g., TCON) for the corresponding display panel <NUM>.

Alternative or additional pixel operations may be implemented by the pixel operation unit(s) <NUM>. For example, the pixel operations may include, without limitation, gamma correction, ambient color correction, color gamut mapping (e.g., through a three-dimensional lookup table), dithering, dynamic backlight control, and sub-pixel optimization (e.g. for Pentile displays).

Each display controller <NUM> may include fewer, additional, or alternative components. For instance, the display controller <NUM> may not include one or more of the pixel operation elements. In some cases, an ink rendering engine may be included for incorporating data representative of stylus strokes into the image data to be rendered. The additional elements may or may not be disposed along the pipeline.

Each display controller <NUM> may be realized on one or more IC chips. The functionality of the display controller <NUM> may be integrated to any desired extent. In some cases, the display controller <NUM> is implemented in a multi-component package. In still other cases, one or more aspects of the display controller <NUM> may be implemented on a printed circuit board or other circuit arrangement.

Each display controller <NUM> is configured to generate a timing indication to prevent tearing or other adverse effects of asynchronous operation of the display controller <NUM> and the processor <NUM>. The timing indication may be a signal or other indication that the respective display controller <NUM> resides in a state ready for refresh of the corresponding display panel <NUM>. In some cases, the timing indication is or includes a tearing effect (TE) signal, such as the TearEffect (TE) signal from a MIPI DDIC controller. The TE signal may be a dedicated voltage signal that toggles between two states, e.g., a zero state indicative of non-readiness and a non-zero state indicative of readiness. However, the timing indication may or may not be configured as a pulse. The timing indication may be any signal or other indication generated or provided once per frame when the display controller <NUM> is ready to receive new image data.

The TE signal or other timing indication may be generated and/or configured in accordance with techniques directed to preventing tearing. Further information regarding how the TE signal or other timing indication is used to prevent tearing is provided in connection with <FIG>.

The TE signal or other timing indication may be generated by one or more elements of the display controller <NUM>. In the example of <FIG>, the display controller <NUM> includes a clock <NUM> that increments one or more counters <NUM>. For instance, one counter <NUM> may control the duration of horizontal blanking and pixel charge time. This duration is associated with the rendering of each horizontal line. Another counter <NUM> counts the number of horizontal lines in a frame and any vertical blanking lines, which together constitute the duration of a display frame. The timing indication may be generated by or via either one or both of the counters <NUM>. For example, the timing indication may be a pulse or other indication generated by the counter(s) <NUM> once the counter(s) <NUM> reach a predetermined value indicative of the end of the frame. Alternatively or additionally, the timing indication may be generated by another element or component of the display controller <NUM>. For instance, the timing indication is or includes a signal generated by the memory controller <NUM>. For example, the memory controller <NUM> may generate a pulse or other signal in response to the counter(s) <NUM> and/or upon reaching the beginning, end, or other predetermined portion of a frame. Alternatively or additionally, the pixel operation unit(s) <NUM> is/are involved in generating the timing indication in response to the counter(s) <NUM>.

The processor <NUM> is coupled to the plurality of display controllers <NUM> to receive the TE signals or other timing indications. The manner in which the TE signal or other timing indication is provided to the processor <NUM> of the host <NUM> may vary. For instance, the timing indication may be provided on a dedicated signal line <NUM> between the display controller <NUM> and the host <NUM>, as shown in <FIG>. The signal line <NUM> may thus be separate from the interface <NUM>. Alternatively or additionally, the timing indication may be provided via the interface <NUM> or a different interface, bus, or other communication channel or connection. For example, the timing indication may be provided in or as a message (e.g., an in-band message) over a common bus (e.g., a bus coupling the host <NUM> and the display controller <NUM>), such as MIPI, HDMI, eDP or other bus. In such cases, the timing indication may be configured as a command or other instruction. The nature and other characteristics of the timing indication may vary accordingly. For instance, the timing indication may be provided in a data packet or other data package. In some cases, the device <NUM> may be configured to support multiple types of timing indications (e.g., both a message and a dedicated signal), and select one type for use based on current operating conditions or other factors.

The device <NUM> uses the TE signal or other timing indications from all of the display controllers <NUM> collectively. As a dedicated signal per display panel <NUM>, each TE signal is conventionally used to prevent tearing on a single display. Rather than use the timing indication solely for anti-tearing efforts in connection with a single display, the timing indications from all of the display controllers <NUM> are gathered by the device <NUM> for use collectively to synchronize the multiple display panels <NUM>. In the example of <FIG>, the host <NUM> (e.g., the processor <NUM>) receives the timing indication from each display controller <NUM>.

The processor <NUM> is configured to delay a refresh of the display panels <NUM> until the timing indication is received from each respective display controller <NUM> to synchronize the display panels <NUM>. The delay may be implemented via an Adaptive Sync or other technique responsive to the timing indication. Adaptive Sync is a Video Electronics Standards Association (VESA) standard that establishes a protocol or other procedure for delaying the refresh of a display panel asynchronously timed relative to the host. As described further in connection with the example of <FIG>, the host <NUM> may use the Adaptive Sync delay to delay the refresh of all of the display panels <NUM> until all of the display panels <NUM> are ready for refresh.

In the example of <FIG>, the processor <NUM> of the host <NUM> is configured to determine whether all of the display controllers are ready for refresh, as evidenced by receipt of the timing indications. Upon receipt of the timing indication from each display controller <NUM> (and thus all display panels <NUM>), the processor <NUM> directs all of the display controllers <NUM> to refresh their corresponding display panels <NUM> effectively concurrently. For example, the processor <NUM> may send a StartRefresh or other refresh instruction to all of the display controllers <NUM> effectively concurrently. The instructions may be sent via the command interfaces <NUM> between the display controllers <NUM> and the processor <NUM>.

The manner in which the refresh is delayed may vary. Other protocols or techniques may be used, including techniques established In connection with other proprietary standards, such as Nvidia G-Sync, AMD FreeSync, AMD FreeSync <NUM>, and Nvidia's Adaptive Vsync. Any technique that allows the processor <NUM> of the host <NUM> to control the delay of refresh of an asynchronous display/panel may be used.

The type, delivery mechanism, protocol, and other characteristics of the refresh instruction from the processor <NUM> may vary. For instance, the refresh instruction may be or include any type of message (e.g., an in-band message) over a common bus or other interface, such as a MIPI, HDMI, or eDP interface. The message may be configured in accordance with any protocol, including existing protocols, such as the StartMemoryWrite command of the MIPI protocol, or future protocols.

The refresh may be delayed and then collectively started without relying on the processor <NUM> of the host <NUM>. The timing indication may be provided to another processor of the device <NUM> to that end. In the example of <FIG>, the timing indications are provided to a signal processor <NUM>. The signal lines <NUM> may be tapped or otherwise accessed or otherwise provided to the signal processor <NUM>. The signal processor <NUM> is configured to determine whether all of the timing indications have been received. The signal processor <NUM> is thus also configured to determine whether all of the respective display controllers <NUM> reside in a ready-for-refresh state.

The signal processor <NUM> is configured to send a refresh trigger signal to each display controller <NUM> once the timing indication is received from each display controller <NUM>. In the example of <FIG>, the signal processor <NUM> is, includes, or is configured to implement, an AND operation on the TE signals (or other timing indications) generated by the display controllers <NUM>. In the example of <FIG>, the refresh trigger signal corresponds with the output of the AND operation. The signal processor <NUM> may include additional or alternative elements. For instance, the signal processor <NUM> may include a counter or timer to track the time elapsed since the last refresh. Further processing (e.g., processing of the output of the AND operation) may be implemented to generate the refresh trigger signal.

The refresh trigger signal is used by the display controllers <NUM> to synchronize a refresh of the display panels <NUM>. Each display controller <NUM> may respond to the refresh trigger signal from the signal processor <NUM> in a manner similar to the response to a refresh instruction via the command interface <NUM>. In contrast, the refresh trigger signal may be provided to each display controller <NUM> on a respective signal line <NUM> between the signal processor <NUM> and each display controller <NUM>. The signal lines <NUM> may be dedicated signal lines, as shown in <FIG>. Alternatively, the signal lines <NUM> may be integrated with other signal lines, interfaces, channels, or other connections to any desired extent.

Each display controller <NUM> is enabled to be responsive to the refresh trigger signal. For instance, the processor <NUM> may provide an enable instruction or other signal (e.g., EXT_TRIG_EN) to the display controllers <NUM> to control whether the display controllers <NUM> are responsive to the output from the signal processor <NUM> (e.g., the trigger signal indicative of the AND operation. In some cases, the enable signal is provided via the command interface <NUM>. Alternatively, the enable signal is provided via a dedicated signal line.

The enable signal may allow the device <NUM> to transition between an instruction mode and a signal mode. For example, the device <NUM> operates in the instruction mode when the display controllers <NUM> await a refresh instruction via the command interface <NUM>. The device <NUM> operates in a signal mode when the display controllers <NUM> await the refresh trigger signal.

The signal mode may be useful in circumstances in which deactivating the processor <NUM> and/or the interface <NUM> is warranted. For example, the processor <NUM> may be deactivated or inactive in the sense that image data is not being generated. Deactivating the processor <NUM> and/or the command interface <NUM> allows power to be saved. One example of a deactivation of the processor <NUM> involves a panel self refresh operation. The signal processor <NUM> is enabled to control the display controllers <NUM> when the display controllers <NUM> are operating in a panel self-refresh mode of operation. Non-graphics functionality of the processor <NUM> may remain operational during a panel self refresh operation or other deactivation of the processor <NUM>.

In some cases, the processor <NUM> is configured to determine whether to operate in the instruction mode or the signal mode. For instance, the processor <NUM> may select one of the modes based on a current operational condition. Additional or alternative circumstances may be taken into account. For instance, the processor <NUM> may select based upon the receipt of another command or instruction.

The signal processor <NUM> may be provided on a separate integrated circuit (IC) chip or other discrete component. In the example of <FIG>, the signal processor <NUM> is separate from the display controllers <NUM> and the host <NUM>. In other cases, the signal processor <NUM> may be integrated with one of the other components of the device <NUM> to any desired extent. For example, the signal processor <NUM> may be integrated with one or more of the display controllers <NUM>, as described below in connection with the example of <FIG>. The signal processor <NUM> is alternatively integrated with the processor <NUM> or a unit thereof.

<FIG> depicts an example of the synchronization of two display panels using the above-described technique. A first display panel, Display A, has a slow or slower refresh rate. A second display panel, Display B, has a fast or faster refresh rate. The difference in refresh rates may arise from a difference in the internal clocks of the display controllers (e.g., DDICs) and/or any other difference. In any case, the displays are asynchronously timed. So the displays finish processing frames at different times. In the example of <FIG>, a first frame N is processed in time periods <NUM>, <NUM> by the Displays A, B, respectively. The time period <NUM> is longer than the time period <NUM> by a time lag T. The Displays A, B provide timing indications (e.g., a TE or other timing signal) upon the conclusion of the time periods <NUM>, <NUM>.

The Displays A, B are not directed to begin a refresh until the conclusion of both of the time periods <NUM>, <NUM>, i.e., until the receipt of both of the timing indications. The refresh of the faster display panel, Display B, does not occur as quickly or early as the refresh otherwise would. Instead, the refresh of Display B waits until the conclusion of the time period <NUM>, as shown, after which a refresh direction is provided to the Displays A, B. The refresh direction may be or include one of the refresh instructions or refresh trigger signals described above. In either case, the display controllers of the Displays A, B may use Adaptive Sync (or another delay technique) to wait until receipt of the refresh direction to start the process again with another Frame N+<NUM>.

The refresh direction may be provided to the Displays A, B simultaneously or effectively simultaneously. As a result, the Displays A, B begin processing the Frame N+<NUM> at a common time S1. The simultaneous send of the instruction or signal results in the simultaneous start of the processing of the next frame. The simultaneous start allows the Displays A, B to remain synchronized. The Displays A, B may again finish processing the Frame N+<NUM> at different times, as shown by time periods <NUM>, <NUM>. The time periods <NUM>, <NUM> may or may not correspond with (or equal) the previous time periods <NUM>, <NUM>. Either way, the refresh direction is not provided until the conclusion of both of the time periods <NUM>, <NUM>.

Another refresh direction is provided upon the conclusion of both of the time periods <NUM>, <NUM>. Receipt of the refresh direction directs the Displays A, B to begin to process a Frame N+<NUM> at a common time S2. In this way, display frame synchronization is maintained between the two Displays A, B. The difference between the times S1 and S2 shows how the slower or slowest display effectively establishes the timing for the device.

The synchronization of the Displays A, B does not adversely affect or interfere with anti-tearing effect techniques, such as Adaptive Sync. A delay (e.g., extra blanking) to accommodate a slow processor may still occur. For instance, if the GPU or other processor of the host takes longer than one of the time periods <NUM>, <NUM> to prepare the image data for the subsequent frame (e.g., the Frame N+<NUM>), then the anti-tearing effect processing will give the processor additional time to generate the image data.

However, if a predetermined amount of time lapses, a pulse (or other aspect) of one or more of the TE or other timing indications from the Displays A, B may have ended. As a result, the Displays A, B may then self-refresh with the current frame (e.g., the previously stored Frame N). The TE signal or other timing indication continues to indicate that the displays are not ready to accept the image data for the next frame (e.g., the Frame N+<NUM>) until the self refresh processing is complete. Once the processing is complete, another pulse of both of the timing indications is provided, and the image data for the Frame N+<NUM> is then written to the display controllers of the Displays A, B for processing in time blocks <NUM>, <NUM>.

<FIG> depicts a device <NUM> configured to support multiple display synchronization in accordance with one example in which an external trigger signal is always used to start the processing of the next frame of image data. Like the examples described above, the trigger signal is external in the sense that the trigger signal is provided separately from a primary communication path between a host <NUM> and display controllers <NUM>. In this case, however, an instruction to start writing or processing is not provided by a processor <NUM> of the host <NUM> via a command or other interface <NUM> via which image data and other instructions are provided.

The device <NUM> may have a number of components, aspects, or other characteristics in common with the above-described examples. For instance, the display controllers <NUM> may have similar components. Other components or aspects may also be in common. For instance, the host <NUM> may have similar components. Other components, aspects, or elements of the device <NUM> are also similarly configured unless otherwise described below.

The device <NUM> differs from the above-described examples in connection with the manner in which timing indications from the display controllers <NUM> are provided and processed. In this example, a TE signal or other timing indication is provided by each timing controller <NUM> only to a signal processor <NUM>, rather than to both a signal processor and a host processor as in the example of <FIG>. The nature of the timing indication may vary as described herein. Once the timing indication is received from each display controller <NUM>, the signal processor <NUM> may provide a refresh trigger signal to each display controller <NUM> in a manner similar to the examples described above. For instance, the refresh trigger signal may be provided on a dedicated signal line <NUM> separate from the command interfaces <NUM>.

The signal processor <NUM> may differ from the above-described signal processor examples in one or more ways. In some cases, the signal processor <NUM> is or includes a state machine. The state machine may incorporate or include the AND operation functionality (e.g., solely an AND operation) to determine whether all of the timing indications have been provided. The state machine may include further functionality to address other circumstances presented during operation, such as startup. The state machine may be configured to determine how to initially align and direct the display controllers <NUM>. The state machine may also be configured to implement one or more recovery routines to address failure modes presented by the host processor <NUM> or other element of the device <NUM>. The state machine of the signal processor <NUM> may be configured to provide alternative or additional functionality, including, for instance, guaranteeing a minimum length of the refresh trigger signal, knowledge of which direction to change timing in circumstances in which the displays are not synchronized, and measuring the extent to which the displays are synchronized.

The reliance upon on the state machine of the signal processor <NUM> is useful because the state machine avoids the real-time demands on the instruction-based operations of the host processor <NUM>. The complexity of such instruction-based operations may lead to delays that adversely affect image data and other processing. The signal processor <NUM> trades off the flexibility of the instruction-based operations for the reliability of the hardware-based configuration of the state machine.

In the example of <FIG>, the signal processor <NUM> includes a counter <NUM> to address one or more conditions or circumstances presented during operation. The state machine may be configured to be responsive to the output of the counter <NUM> to determine whether to direct the display controllers <NUM> to implement a refresh. For instance, counter <NUM> may track the time elapsed since a last refresh. The state machine may be configured to determine if the elapsed time (e.g., the output of the counter <NUM>) crosses a timeout threshold. If yes, the signal processor <NUM> directs the display controllers <NUM> to implement a panel self refresh. The timeout threshold may be exceeded in circumstances in which the host processor <NUM> fails to generate the image data for the next frame sufficiently quickly. In this manner, the next frame of image data is allowed to be written to the display controllers <NUM> and otherwise processed as long as the image data is available before the timeout condition is reached.

The device <NUM> also differs from the above-described examples in connection with the manner in which the host processor <NUM> avoids tearing effects. In this case, the individual TE or other timing indications are not provided to the processor <NUM>. Instead, the signal processor <NUM> provides a collective TE or timing signal on a signal line <NUM>. The collective TE signal <NUM> may then be used by the processor <NUM> to avoid tearing effects as if the device <NUM> has only a single display controller. In the above-described examples, the host processor <NUM> of <FIG> (e.g., firmware thereof) controls the rate of panel refresh by delaying until all panels were ready. In this example, i.e., the device <NUM>, the signal processor <NUM>, which may be a hardware device or a separate dedicated or shared processing element, offloads the control of the rate of panel refresh from the host processor <NUM>. The signal processor <NUM> also controls the rate panel refresh by delaying until all panels are ready.

The timing signal on the signal line <NUM> is generated and provided separately from the trigger signal on the signal line <NUM> to provide flexibility in the anti-tearing effort. Having two different output signals allows the timing of the refresh within each refresh cycle to be customized or otherwise determined. For instance, the timing signal on the signal line <NUM> may be offset from the trigger signal to adjust when the image data will be written to the memory within each display controller <NUM> (e.g., the write pointer) relative to when the image data will be read from the memory (e.g., the read pointer). The alignment of the TE or other timing signal provided to the host processor <NUM> may thus be adjusted (e.g., from a first line of the frame to a line in the middle of the frame) to improve performance. This adjustment may allow the host processor <NUM> to offset writing of the frame buffer, thereby providing timing margin to prevent tearing.

<FIG> depicts an example in which two display controllers <NUM> include the above-described signal processing functionality. As described above, each display controller <NUM> may be realized as a discrete integrated circuit, such as a DDIC. In this case, the signal processing is integrated with other display controller processing. Incorporated into each display controller <NUM> is a signal processor <NUM> configured as a state machine.

The state machine <NUM> is configured to generate a trigger signal once the timing signal is received from each respective display controller <NUM>. To that end, the display controllers <NUM> may be cross-wired with one another. In this example, each display controller <NUM> includes an input port <NUM> at which the timing indication is received. Each display controller <NUM> includes an output port <NUM> at which the trigger signal is provided. The cross-wiring connects the input port <NUM> of one display controller <NUM> with the output port <NUM> of the other display controller <NUM>.

In the example of <FIG>, one of the display controllers <NUM> may be designated or configured as a primary display controller. The other display controller(s) <NUM> is then designated or configured as a secondary display controller. The designation may toggle or change during operation to address various circumstances or conditions.

The output of each secondary display controller may be indicative of its own state of readiness, i.e., an individual timing indication of whether that respective display controller is ready for refresh. That output is the provided to the input port <NUM> of the primary display controller. The primary display controller may then use its own timing indication in combination with the timing indication received at the input port <NUM> to implement the AND operation, i.e., determine whether each display controller is ready for refresh
Each display controller <NUM> may include another output port <NUM> to provide a collective timing indication to the host processor. The host processor may then operate, at least for tearing effect purposes, as if the device includes only a single display. Upon receipt of the collective timing indication, the host processor provides the image data for the next frame to each display controller <NUM> simultaneously. The simultaneous start maintains the synchronization of all of the displays, as described herein.

Only the output port <NUM> of the primary display controller is active. The output ports <NUM> of all of the display controllers may thus be tied to one another as shown.

Each port <NUM>, <NUM> may be or include a pin, pad, or other input/output node of the display controller <NUM>. Additional input ports <NUM> may be provided.

Other aspects of the integration or configuration of the above-described display controllers may vary. Each display controller may be integrated with the other display components to any desired extent. For instance, each display may or may not include the display controller. In some cases, each display includes an integrated timing controller or other display controller configured to provide the timing indication used for synchronization.

<FIG> depicts a method <NUM> of synchronizing a plurality of display panels of a device. The method <NUM> may be implemented by one of the above-described devices or another device. Alternatively or additionally, the method <NUM> may be implemented in whole or in part via the execution of instructions by one of the above-described processors, such as the processor <NUM> (<FIG>), the processor <NUM> (<FIG>), and/or another processor. The instructions may be stored on a memory of a host, a display controller, and/or another memory. One or more of the acts of the method <NUM> may be performed by a signal processor, such as the signal processor <NUM> (<FIG>), the signal processor <NUM> (<FIG>), the signal processor <NUM>, or another signal processor.

The order of the acts of the method <NUM> may vary from the example shown. For instance, some of the acts may be concurrently implemented. For example, detection of timing indications in act <NUM> may be concurrently implemented with the decision to whether enter a low power or other mode in block <NUM>. The acts may also be implemented in a different order. For instance, the block <NUM> may be implemented at times other than that shown in <FIG>.

The method <NUM> may begin with one or more acts directed to startup. For instance, the host may direct the display controllers to keep the display panels black until one or more startup conditions are met.

The method <NUM> is a recurring procedure with each refresh cycle. For ease in description, the method <NUM> is presented and described as if the image data for at least one frame is provided. For instance, the method <NUM> may include an act <NUM> in which the image data is generated and sent by the host processor for a previous frame. Such previous image data may be sent in accordance with the synchronization techniques described herein.

In the example of <FIG>, the method <NUM> then proceeds to a decision block <NUM> in which the host processor determines whether to enter a low power mode and/or signal mode. A low power mode may be one in which image data is not generated by the host processor. For example, the low power mode may result in the displays implementing a panel self refresh routine. The low power mode may additionally or alternatively involve entering a signal mode in which the display controllers are directed to respond to a refresh trigger signal rather than a refresh instruction. The low power mode and/or signal mode may accordingly involve deactivating a bus or other command interface between the host processor and the display controllers.

If the low power or signal mode is entered, control may proceed to an act <NUM> in which an enable signal is sent or otherwise made available to enable external triggering of the display controllers. The enable signal may be or include any indication that the display controllers should be responsive to the external refresh trigger signal. The enable signal may be provided to the display controllers and/or the signal processor that generates the trigger signal. In other cases, the display controllers are enabled by implication. For instance, the deactivation of the command interface may be detected by the display controllers as an effective or implicit enable signal.

The method <NUM> includes an act <NUM> in which timing indications from each display controller are detected. The detection may be performed by either the host processor or a signal processor. As described above, each timing indication is generated by a respective display controller to indicate whether the respective display controller resides in a state ready for refresh of the corresponding display panel. Each timing indication may be a signal (e.g., a TE signal), a message (e.g., a command bus message), or other indication.

In a decision block <NUM>, the processor determines whether all of the timing indications have been received. The block <NUM> is implemented via an AND operation. In the example of <FIG>, the block <NUM> also determines whether a timeout condition has occurred. For these and other reasons, the block <NUM> may be configured to implement a counter and/or other operations in addition to the AND operation.

Once all of the timing indications have been received, control passes to an act <NUM> in which the processor directs the display controllers to refresh their corresponding display panels. The refresh direction is provided simultaneously so that the display panels remain synchronized with one another. The method <NUM> may then return to the act <NUM> in which the image data is written or otherwise sent to the display controllers.

If the timeout condition occurs, then control passes to an act <NUM> in which a panel self refresh routine is implemented. The direction to implemented the panel self refresh routine may also be provided simultaneously to maintain synchronization.

The writing of image data by the host processor, such as in the act <NUM>, may be preceded by the sending of a start-write command or other refresh instruction in an act <NUM>. For example, a WriteMemoryStart command may be provided. The refresh instruction may prepare the display controllers for the receipt of the image data for the next frame. The image data may then be written to a frame buffer or other memory of the display controller in an act <NUM>.

Detection of the timing indications in the act <NUM> may include monitoring multiple TE or other signal lines in an act <NUM>. Each signal line may be a dedicated line separate from an image data interface via which the display controllers receive the image data. The monitoring may be performed by either the host processor or the above-described signal processors. In other cases, the timing indications are provided in the form of a message or other data packet.

The act <NUM> may include an act <NUM> in which the processor sends blanking while waiting for all of the timing indications to be received. The blanking may be sent to display controllers that have already indicated their readiness for refresh, i.e., already provided a timing indication.

A refresh trigger signal is generated in an act <NUM> via an AND operation of the signal processor.

The disclosed devices and methods achieve multiple-display synchronization via one or both of an in-band or other command or message (e.g., a StartRefresh command) and a dedicated trigger signal. The host processor may configure the display controller or panel to use the in-band or other message or command when the display is being actively updated. The host processor configures the display controller or the panel to use the dedicated trigger signal when the display controller is self refreshing the panel out of internal memory (e.g., a frame buffer). The availability of multiple refresh directions allows the host to power down the high speed interface (e.g., the command interface) to achieve system power savings.

In one aspect, a device includes a plurality of display panels, a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing indication, and a processor coupled to the plurality of display controllers to receive the timing indications from the plurality of display controllers. Each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel. The processor is configured to delay a refresh of the plurality of display panels until the timing indication is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels.

In another aspect, a device includes a plurality of display panels, a processor configured to generate image data for rendering on a plurality of display panels of the device, a plurality of display controllers coupled to the processor to receive the image data, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels of the device, each respective display controller of the plurality of display controllers being configured to generate a timing signal, and a signal processor configured to receive the timing signals from the plurality of display controllers. Each timing signal is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel. The signal processor is configured to generate a trigger signal once the timing signal is received from each respective display controller of the plurality of display controllers. The trigger signal is used by the plurality of display controllers to synchronize a refresh of the plurality of display panels.

In yet another aspect, a method of synchronizing a plurality of display panels of a device includes detecting, with a processor, a plurality of timing indications, each timing indication of the plurality of timing indications being generated by a respective display controller of a plurality of display controllers, each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, wherein each timing indication is indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel, and directing, with the processor, the plurality of display controllers to refresh the plurality of display panels once the timing indication from each respective display controller of the plurality of display controllers is detected to synchronize the plurality of display panels.

Claim 1:
A device (<NUM>, <NUM>) comprising:
a plurality of display panels (<NUM>);
a plurality of display controllers (<NUM>, <NUM>), each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing signal indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel;
a processor (<NUM>, <NUM>) coupled to the plurality of display controllers to receive the timing signals from the plurality of display controllers,
wherein the processor comprises a signal processor (<NUM>) configured to implement an AND operation on the timing signals generated by the plurality of display controllers and output a refresh trigger signal accordingly, and send the refresh trigger signal to each display controller of the plurality of display controllers upon receipt of the timing signal from each respective display controller of the plurality of display controllers such that the processor is configured to delay a refresh of the plurality of display panels until the timing signal is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels,
the device being characterized in that it comprises an application processor configured to generate image data to be rendered on the plurality of display panels of the device and to provide an enable signal to each display controller of the plurality of display controllers;
wherein each display controller of the plurality of display controllers is adapted to be enabled to be responsive to the refresh trigger signal according to the enable signal, and
wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data.