Patent Description:
A serial data transmitter and receiver TX/RX is used to transmit data over a channel. In one application an eye diagram can be used at the receiver end of the channel to monitor the signal integrity. For instance, a probe can be connected to the amplifier and an eye diagram can be observed graphically on a personal computer (PC) monitor. The observed pattern can appear as an eye or eye diagram, and the amount of eye opening can reflect the integrity of the equalized data.

Personal computers and laptops can use a serial data transmitter and receiver TX/RX in communicating data across serial ports to and from computer peripheral components.

In some applications an equalizer and limiting amplifier can be used to improve a data signal arriving at the receiver RX. The limiting amplifier can be used to compensate for losses and attenuation within the signal chain preceding the amplifier input.

<CIT> describes a variable gain amplifier provided with switch arrays that enables that enable activating and deactivating gain stages. "<NPL>et al. describe a current-mode circuit for realizing CMOS digitally controlled variable gain amplifier for ultra-wideband systems, comprising a transconductance stage and a current amplifier stage connected in series. "D-Band CMOS transmitter and receiver for multi-gigabit/sec wireless data link" describes a circuit wherein amplifier stages are connected in a cascading fashion, with a gain control switch system enabling or disabling feedback paths that adjust the gain of the system.

The invention is defined by the appended independent apparatus claim <NUM>. Preferred embodiments are defined by dependent claims <NUM>-<NUM>.

These drawings and the associated description herein are provided to illustrate specific embodiments of the invention and are not intended to be limiting.

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings in which like reference numerals may indicate identical or functionally similar elements.

In a serial data system, the direct transmission and reception of a binary signal can be used to avoid modulation or quantized data conversion. One method to compensate for high frequency signal loss in a transmission line is a passive equalizer (EQ). The passive EQ does not consume power; however, in balancing the signal amplitude over a frequency band, it can attenuate the lower frequency portion of the received signal. The goal of the receiver RX is to recover the transmitted signal from the transmitter TX for all frequencies of interest. This can become a more challenging task as data rates, and hence bandwidths, increase.

Eye diagrams are commonly used to evaluate the integrity of a received data signal. An eye diagram shows parametric information about a signal including jitter and distortion content, and data signals of high integrity present an open eye. Therefore, it can be useful to include an eye monitor within a receiver system to measure the received data signal. For instance, a data signal at the output of an equalizer, as described above would ideally have constant amplitude as a function of frequency and provide an open eye. From the eye diagram information, the equalizer can be conveniently calibrated and adjusted until an eye opening meets a system criterion or specification.

As data rates increase, the transmission losses within the transmission medium can become significant, causing a binary transmitter and receiver (TX/RX) system to become unwieldy. In order to compensate for channel losses and equalizer attenuation, one approach can be to arbitrarily increase the TX output level by an amount proportional to the attenuation in the channel. Unfortunately this approach is incongruous with present and future trends in device scaling which necessitate lower voltage swings. An alternative approach can be to use an amplifier in the RX path to amplify the equalizer output to a level which effectively captures the signal data. Unfortunately, this approach by itself can lead to unnecessarily high power dissipation. Therefore, there is a need for a balanced approach which uses a moderate signal from the TX path but also provides some gain in the RX channel. Because the required amount of amplification (gain) can depend in part upon the bandwidth and frequency, there is a need for signal-processing stages which are configurable. A configurable stage can be adjusted according to the physical characteristics of signals from the equalizer.

For instance a configurable stage can be used to provide adaptable gain to a limiting amplifier. As discussed above, an eye diagram can be used to monitor a data signal within the RX path (channel) and to determine signal integrity. In this way signals from the limiting amplifier can be monitored and a gain or characteristic of the limiting amplifier can be adjusted accordingly.

Unfortunately integrating eye diagram monitors within the stages of a signal-processing path, such as a path of a limiting amplifier system, can become area consuming and can unnecessarily load or perturb the output signals by presenting significant impedance such as interconnect capacitance. Accordingly, there is a need for signal-processing systems, including but not limited to limiting amplifiers, in an RX path which allow for monitoring a signal without significantly loading or affecting the behavior of the system.

Apparatus and methods for an adaptable receiver system are presented herein. An RX limiting amplifier, signal-processing system, or receiver with configurable stages can amplify or process data signals. Using a current to voltage converter to virtually observe an output signal from each stage, the signal-processing system can be virtually monitored with one eye monitor. Advantageously, the eye monitor can virtually monitor stages without loading the output of each stage. By monitoring the stages in succession, the number of stages can be selected and programmed based on the frequency and power requirements. Thus, the receiver can allow for a programmable and configurable design. Further, the stages are configurable and can be used and ported to multiple platforms and can be used in high speed serial data reception applications.

<FIG> is a schematic diagram of an embodiment of a data receiver system <NUM> not forming part of the claimed invention. In the illustrated embodiment, the data receiver system <NUM> includes an amplifier <NUM>, a signal monitor <NUM>, and an equalizer <NUM> (shown in dashed lines). However, it will be understood that the data receiver system <NUM> can include fewer or more components as desired. For example, in certain embodiments, the data receiver system <NUM> may include only one or any combination of amplifier <NUM>, a signal monitor <NUM>, and an equalizer <NUM>. As another example, the data receiver system <NUM> can include two or more equalizers and/or a flip-flop, etc. The data receiver system <NUM> can receive input signals INPUTS and provide an amplified output signal Vs. The amplifier <NUM> can include an amplifier input and an amplifier output. The equalizer <NUM> can receive the input signals INPUTS and provide an equalized output to the amplifier input. The equalized output can have a relatively constant gain as a function of frequency. Alternatively, the input signals INPUTS can be applied directly to the amplifier input without the use of the equalizer <NUM>. In this case the amplifier can receive data signals of variable amplitude as a function of frequency.

The amplifier <NUM> can be a limiting amplifier of an RX receiver in a serial data transmitter and receiver TX/RX system. Additionally the amplifier <NUM> can have programmable gain so as to be adaptable to the amplitude or power level of the input signals INPUTS. As shown in <FIG>, the signal monitor <NUM> can include an input port connected to the amplifier output to monitor the amplified output signal Vs. The signal monitor <NUM> can have a signal port communicatively coupled to the amplifier output and can present a small capacitance or loading at the amplifier output. Also as shown in <FIG>, the connection between the amplifier <NUM> and the signal monitor <NUM> can be virtually moved, as represented by the dashed wire. The virtual movement can be accomplished by a circuit or system approach which allows the signal monitor <NUM> to observe characteristics of data at the amplifier input. In some cases, the circuit can provide the virtual movement without loading (and/or avoiding, reducing, minimizing the load on) the amplifier input with capacitance or impedance. Additionally, the connection can be virtually moved to internal nodes within the amplifier <NUM> so as to monitor signals of intermediate signal strength between the amplifier input and the amplifier output; and the virtual movement can again be accomplished by a circuit or system approach which does not perturb (and/or avoids, reduces, or minimizes the perturbation of) the internal nodes with probe capacitance or impedance.

Information from the signal monitor <NUM> can be used to adjust the gain of the amplifier <NUM> to a target level for amplifying the input signals INPUTS so that an output signal Vs has a desired characteristic. The output signal Vs can be a voltage signal Vs, and an eye diagram from the signal monitor <NUM> can be used to adjust the gain. The gain can be adjusted until an eye opening, as observed on an eye diagram, becomes wide enough for data reconstruction. In this way the gain can be adjusted to a level which can be less than a maximum full power gain while providing adequate signal strength. Thus, the amplifier can operate at power levels lower than the maximum for an overall power savings.

Although the data receiver system <NUM> shows a configuration where the output signal is provided as Vs, other configurations including additional output components are possible. For instance, the data receiver system can include a clocked D-type flip flop (DFF) to receive the output signal Vs at a D input of the clocked DFF and to provide a clocked data signal at a Q output of the clocked DFF. A clock signal can be used to clock data of the output (voltage) signal Vs to the Q output of the clocked DFF. Also, the amplifier <NUM> can be a generalized amplifier and have signal-processing receiver stages, also referred to as stages or configurable stages, which can provide gain and/or equalization to the input signals INPUTS.

<FIG> is a schematic diagram of a data receiver system 200a with multiple signal-processing stages according to one embodiment not forming part of the claimed invention. In the illustrated embodiment, the data receiver system 200a has a signal detect and monitor circuit <NUM> which can augment the signal-processing stages to monitor characteristics, such as an eye opening, of output data signals. However, it will be understood that the data receiver system 200a can include fewer or more components as desired. For example, in some embodiments, the data receiver system 200a can include only one or any combination of the signal detect and monitor circuit <NUM> and amplifier <NUM>.

In the illustrated embodiment, the data receiver system 200a includes a first stage <NUM>, a second stage <NUM>, and an Nth stage <NUM> connected in cascade. Each stage can be a signal-processing stage such as an amplifier and/or an equalizer; and it will be understood that any number of stages can be included as desired.

The first stage <NUM> has an input port and a first output port connected to an input port of the second stage <NUM>. The second stage <NUM> has an input port and a first output port connected to an input port of the successive stage. As shown by the ellipses in <FIG>, successive stages can be cascaded in a similar manner from the second stage <NUM> to the Nth stage <NUM> which has an input port connected to a first output port of its preceding stage. The Nth stage <NUM> also has a first output port which is connected to a first chain input port of the signal detect and monitor circuit <NUM>. As a note, because the stages are connected in cascade or in succession, the Nth stage can also be referred to as the last stage or the final stage.

The first stage <NUM> receives the data input signals INPUT(s) at the first stage input port and processes the input signals INPUT(s) to provide a first cascade output signal at the first output port. The first cascade output signal is provided to the input port of the second stage <NUM> and processing can occur. As a non-limiting example, each successive stage can provide additional gain and/or equalization along the signal path between the input port of the first stage <NUM> and the first output port of the Nth stage <NUM>. For instance, the second stage <NUM> can be configured to provide additional gain and/or equalization to the first cascade output signal to provide a second cascade output signal. The second cascade output signal is provided at the first output port of the second stage <NUM>. The second cascade output signal can be further processed by successive stages until the Nth stage is reached. Also, the Nth stage can process a cascade output signal from the preceding stage so as to provide an Nth cascade output signal. In some embodiments, the Nth stage can omit the Nth cascade output signal and corresponding port.

Also as shown in <FIG>, the first through Nth stages <NUM>-<NUM> can each have a second output port. The second output port of the first stage <NUM>, the second stage <NUM>, and the Nth stage <NUM> are shown to be connected together to a multiplexed monitor input port of the signal detect and monitor circuit <NUM>. The common connection of the second output ports to the multiplexed monitor input port allows for virtual multiplexing or virtual movement of the connection between the amplifier <NUM> and the signal detect and monitor <NUM>. For example, in some embodiments, only one of the first through Nth stages <NUM>-<NUM> provides an active output signal to the common connection, while the remaining stages from the first through Nth stages <NUM>-<NUM> can operate as high impedance nodes. As will be further illustrated in the following figures, the selection of a stage from the first through Nth stage <NUM>-<NUM> to provide the active output signal can be used to program the gain. Thus, in the illustrated embodiment, the gain of the signal-processing stages can be programmed by multiplexing the outputs from the various stages.

The signal and detect monitor circuit <NUM> can be used to monitor one or more characteristics of signals of the multi-stage limiting amplifier. In <FIG> the signal detect and monitor circuit <NUM> is shown to receive the Nth cascade output signal at the first chain input port and the active output signal at the multiplexed monitor input port. The signal detect and monitor circuit <NUM> can provide the output signal at an output port. The output signal can have programmed gain based in part on an eye diagram.

The signal detect and monitor circuit <NUM> can be used in adjusting gain of the multi-stage limiting amplifier to provide a selectable gain. For instance, control or programmable enable signals (not shown) can be applied to the first through Nth stages <NUM>-<NUM> to test or compare an eye diagram opening based on which stage from the first through Nth stages <NUM>-<NUM> actively provides the active output signal. One or more control or enable signals (not shown) can first enable the first stage <NUM> to provide the active output signal from the second output port of the first stage <NUM>. If a resulting eye diagram is sufficiently open so that the first stage <NUM> provides satisfactory gain to the data signals INPUT(s), then the first stage <NUM> can become the stage selected to provide the active output signal. However, if the eye diagram is not sufficiently open or if the signal detect and monitor circuit <NUM> determines that the active output signal requires more gain, then the second stage <NUM> can be enabled to provide the active output signal from the second output port of the second stage <NUM>. The active output signal received from the second output port of the second stage <NUM> can have more gain than the active output signal received from the first output port of the first stage <NUM>.

If the above mentioned criteria are met for the second stage <NUM>, then the second stage <NUM> can be selected to provide the active output signal; and if the criteria are not met using the second stage <NUM>, then the programmed enable sequence can continue successively for each cascaded stage until either one or more signal criteria, such as an eye diagram opening characteristic, is met, or until the last or Nth stage <NUM> in the cascade is reached. In some embodiments, when a stage prior to the Nth stage <NUM> meets the criterion, then a power savings can be achieved by not activating one or more unselected stages, stages following the selected stage, and/or by only using the required number of stages to meet the eye opening characteristic.

Although the signal and detect monitor circuit <NUM> shows a configuration where the signal detect and monitor circuit <NUM> receives the common connection signal and only the Nth cascade output signal at the first chain input port, other configurations are possible, the signal and detect monitor circuit <NUM> can have additional inputs connecting to any one or an combination of the stages <NUM>-<NUM>. In general, the signal and detect monitor circuit <NUM> can have more than one chain input port to receive more than one cascade output signal from the first through Nth cascade output signals. For instance, the signal and detect monitor <NUM> can have a first through Nth chain input port to receive the first through Nth cascade output signals, respectively. In addition, in some cases, the signal detect and monitor circuit <NUM> may not receive any inputs from the stages <NUM>-<NUM> directly and/or may only receive an input from the common connection or common bus.

Also, although the data receiver system 200a shows an amplifier with a first, second, and Nth stage <NUM>-<NUM>, other configurations having greater or fewer stages are possible. For instance an amplifier having two stages connected in cascade can be implemented with just the first stage <NUM> and the second stage <NUM>. Additionally, while not shown in <FIG>, the data input signals INPUT(s) can also be multiplexed with the first through Nth cascade output signals. In this way the signal detect and monitor circuit can also determine if the data input signals INPUT(s) have sufficient strength or are sufficiently equalized to meet an eye opening or signal characteristic. When the input signals INPUT(s) already satisfy an eye opening criterion, then the signal-processing stages can be optionally operated in a low power mode.

Furthermore, it will be understood that other amplifier configurations are possible. For instance, a signal detect and monitor circuit <NUM> can be used with a multi-stage audio amplifier or a multi-stage low drop-out regulator (LDO) which can also benefit from having configurable stages.

<FIG> is a schematic diagram of a data receiver system 200b with multiple signal-processing stages according to an embodiment not forming part of the claimed invention. The data receiver system 200b is similar to that of the data receiver system 200a except that a multiplexer <NUM> is also shown. The multiplexer <NUM> can include a first input coupled to the input port of the first stage <NUM>, a second input coupled to the second output port of the first stage <NUM>, a third input coupled to the second output port of the second stage <NUM>, and an (N+<NUM>)th input coupled to the second output port of the Nth stage <NUM>. In this way the multiplexer <NUM> can include an input for each of the stages <NUM>, <NUM>, <NUM>. Also, the multiplexer <NUM> can include an output which can provide the active output signal as described above with reference to <FIG>. In some embodiments the second output for each stage can output a signal and in certain embodiments, unselected stages can be in a high impedance state as described in greater detail above with reference to <FIG>.

Control signals, CONTROL, can be provided to select which stage from the first through Nth stages <NUM>-<NUM> provides the active output signal; or alternatively, the control signals, CONTROL, can be provided to operate the first through Nth stages <NUM>-<NUM> in a high impedance state while selecting the INPUT(s) without amplification to bypass the stages.

<FIG> is a schematic diagram of a data receiver system 200c with multiple signal-processing stages <NUM>, <NUM>, <NUM> according to an embodiment not forming part of the claimed invention. The data receiver system 200c is similar to the data receiver system 200a of <FIG>. In the illustrated embodiment, the first stage <NUM> includes an input stage <NUM>, a switch <NUM>, a switch <NUM>, a resistor <NUM>, a resistor <NUM>, and an output stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a first output node of the input stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a second output node of the input stage. The second nodes of the resistors <NUM> and <NUM> are connected to a fixed bias node Vb. The first terminal of the resistor <NUM> is connected to an input port of the output stage <NUM>. An input node of the input stage <NUM> is the input port of the first stage <NUM>. The first terminal of the resistor <NUM> is the first output port of the first stage <NUM>, and an output node of the output stage <NUM> is the second output port of the first stage <NUM>.

The second stage <NUM> includes an input stage <NUM>, a switch <NUM>, a switch <NUM>, a resistor <NUM>, a resistor <NUM>, and an output stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a first output node of the input stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a second output node of the input stage. The second nodes of the resistors <NUM> and <NUM> are connected to the fixed bias node Vb. The first terminal of the resistor <NUM> is connected to an input port of the output stage <NUM>. An input node of the input stage <NUM> is the input port of the second stage <NUM>. The first terminal of the resistor <NUM> is the first output port of the second stage <NUM>, and an output node of the output stage <NUM> is the second output port of the second stage <NUM>.

The third stage <NUM> includes an input stage <NUM>, a switch <NUM>, a switch <NUM>, a resistor <NUM>, a resistor <NUM>, and an output stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a first output node of the input stage <NUM>. The switch <NUM> is connected between a first terminal of the resistor <NUM> and a second output node of the input stage. The second nodes of the resistors <NUM> and <NUM> are connected to the fixed bias node Vb. The first terminal of the resistor <NUM> is connected to an input port of the output stage <NUM>. An input node of the input stage <NUM> is the input port of the Nth stage <NUM>. The first terminal of the resistor <NUM> is the first output port of the Nth stage <NUM>, and an output node of the output stage <NUM> is the second output port of the Nth stage <NUM>.

As described above with respect to <FIG>, the data input signals INPUT(s) are received by the first stage <NUM> and the signal detect and monitor <NUM> can monitor signals of the multiple signal-processing stages to provide signal processing to the output signal. Description of the signal flow and operation of the receiver system 200c can be similar to that of the receiver system 200a. Furthermore, in some embodiments, the receiver system 200a can operate to provide programmable gain and to multiplex the active output signal as described in greater detail below.

Comparisons can be drawn between the receiver system 200a of <FIG> and the receiver system 200c. With respect to the first stage <NUM>, the input stage <NUM> receives the input data signals INPUT(s). By comparison to the receiver system 200a, the first stage <NUM> operates such that a signal Vy1 at the first terminal of the resistor <NUM> is the first cascade output signal. Also by comparison the second stage <NUM> operates such that a signal Vy2 at the first terminal of the resistor <NUM> is the second cascade output signal; and the Nth stage <NUM> operates such that a signal VyN at the first terminal of the resistor <NUM> is the Nth cascade output signal.

In some embodiments, programmable gain and virtual multiplexing can be achieved through the control of the switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. With respect to the first stage <NUM>, the operation of the input stage <NUM> can depend upon operation states of the switch <NUM> and the switch <NUM>. A stage monitor state can be defined where the switch <NUM> is closed, to operate as a short circuit or low impedance, and the switch <NUM> is open, to operate as a high impedance or open circuit. In the stage monitor state the input stage <NUM> amplifies the data input INPUT(s) to provide a signal Vx1 to the input node of the output stage <NUM>. The output stage <NUM> can further amplify, buffer, or convert the signal Vx1 to provide the active output signal to the output node of the output stage <NUM>. In this way the second output node of the first stage <NUM> provides the active output signal during the stage monitor state. Also, in the stage monitor state, the first cascade output signal Vy1 can be an AC (alternating current) ground and no signal (a null signal) can pass from the first output node of the first stage <NUM> to the input node of the second stage <NUM>.

A stage cascade state can be defined where the switch <NUM> is open and the switch <NUM> is closed. In the stage cascade state, the input stage <NUM> can amplify the data INPUT(s) to provide the signal Vy1, the first cascade output signal, so that the first cascade output signal can be applied to the input of the second stage <NUM>. Also, in the stage cascade state, the signal Vx1 can become an AC ground providing no signal to the input node of the output stage <NUM>. When no signal appears at the input node of the output stage <NUM>, the output node of the output stage <NUM> can operate as a high impedance. In this way the second output node of the first stage <NUM> can operate as a high impedance node during the stage cascade state.

A stage blocking state can also be defined where both the switch <NUM> and the switch <NUM> are open. In the stage blocking state both the signal Vx1 and Vy2 can be AC ground so that the first output node provides a null cascade output signal (Vy1) and so that the second output node provides a high impedance. In this context, providing high impedance can also mean the switches <NUM> and <NUM> are open circuit. An open circuit can represent a high DC impedance by breaking a path of current flow.

A similar analysis can be applied to each stage from the second to the Nth stage <NUM>-<NUM> of the cascade. A stage monitor state, a stage cascade state, and a stage blocking state can be defined for each stage with reference to the corresponding switches <NUM>, <NUM>, <NUM>, and <NUM> and with respect to the corresponding signals Vx2, Vy2, VxN, and VyN. Instead of receiving INPUT(s), the successive stages receive the cascade output signals from a preceding stage. For instance, the second stage <NUM> receives the cascade output signal Vy1 from the first stage <NUM> at the input port of the input stage <NUM>. By and large, the description of the operational behavior of each stage from the second to the Nth stage <NUM>-<NUM> can be similar to the description of the operational behavior of the first stage <NUM> as discussed above.

In the illustrated embodiment, the multiplexed monitor input port of the signal detect and monitor circuit <NUM> is connected to the second output ports of each of the stages <NUM>-<NUM> and can be used to monitor and observe the behavior of the multi-stage amplifier by programming or by sequencing the different switch states as defined above. For instance, the first stage <NUM> can first be programmed by control or enable signals (not shown) to operate in the stage monitor state while the second through Nth stages <NUM>-<NUM> can be programmed to operate in the stage blocking state. In this way the first stage <NUM> provides the active output signal while the remaining stages <NUM>-<NUM> operate with high impedance. Under these conditions the gain of the input stage <NUM> and the output stage <NUM> contribute to a total monitored gain.

Next, the first stage <NUM> can be programmed to operate in the stage cascade state while the second stage <NUM> is programmed to operate in the stage monitor state. Successive stages from the second stage <NUM> through the Nth stage <NUM> can be programmed to operate in the stage blocking state. In this way the second output node of the second stage <NUM> can provide the active output signal while the second output nodes of the first stage <NUM> and the successive stages through the Nth stage <NUM> operate with high impedance and/or can be powered off. Under these conditions the active output signal is associated with a gain determined by a gain of the first stage <NUM> cascaded with a gain of the input stage <NUM> and the output stage <NUM>.

The total monitored gain can be tested against a criterion for each of the first through Nth stages <NUM>-<NUM>. For instance, when the active output signal at the multiplexed monitor input port of the signal detect and monitor circuit <NUM> causes an eye diagram to meet an eye opening criterion, then the control signals can select the stage associated with the passing criterion. When the stage associated with the passing criterion is less than the maximum number of stages, N, then some of the stages can operate in a low quiescent state or powered off state for reduced power consumption. For instance, if it is determined that when the second stage is controlled to operate in the stage monitor state, the eye diagram is open and meets specification, then the control signals can be set to operate the first stage <NUM> in the stage cascade state, the second stage <NUM> in the stage monitor state, and the successive stages through the Nth stage <NUM> in the blocking state. Having some stages operating in the stage blocking state can advantageously reduce quiescent and power consumption.

While the data receiver system 200c of <FIG> shows the second output ports of the first through Nth stages as being connected to the multiplexed monitor input port of the signal detect and monitor circuit <NUM>, other configurations are possible. For instance, as described with reference to <FIG> and <FIG>, the multiplexed monitor input port can also receive the data input signals INPUT(s) at the multiplexed monitor input port. In this way the signal detect and monitor can also test INPUT(s) directly. For instance, the first through Nth stage <NUM>-<NUM> can be controlled to operate in the blocking state while the INPUT(s) are multiplexed to the multiplexed monitor input port of the signal detect and monitor circuit <NUM>. If the signal detect and monitor circuit <NUM> shows the INPUT(s), without amplification, meet the an eye diagram opening criterion, then the INPUT(s) can be directly used as the amplifier output, while the first through Nth stages <NUM>-<NUM> are controlled to operate in the blocking state.

<FIG> is a detailed schematic diagram of a data receiver system 300a with configurable multiple signal-processing stages <NUM>, <NUM>, <NUM> according to one embodiment. The data receiver system 300a also includes an equalizer (EQ) <NUM>, an EQ <NUM>, and a signal monitor <NUM>. Similar to the signal monitor <NUM> of <FIG>, the signal monitor <NUM> can be used to monitor an eye diagram. Also, it will be understood that the data receiver system 300a can include fewer or more components as desired. For example, in some embodiments, the data receiver system 300a can include only one or any combination of stages, the equalizers <NUM>, <NUM>, and the signal monitor <NUM>. In the illustrated embodiment, the amplifier <NUM> includes configurable multiple signal-processing stages and a current to voltage (I/V) converter <NUM>; the multiple signal-processing stages include a first stage <NUM>, a second stage <NUM>, and an Nth stage <NUM> arranged in a cascade connection.

In the illustrated embodiment, the first stage <NUM> includes an amplifier stage <NUM> and a transconductance stage <NUM>. The amplifier stage <NUM> can include a control terminal, a first input port, a second input port, and an output port connected to an input port of the transconductance stage <NUM>. The transconductance stage <NUM> additionally can include a control terminal. In the illustrated embodiment, the second stage <NUM> includes an amplifier stage <NUM> and a transconductance stage <NUM>. The amplifier stage <NUM> can include a control terminal, a first input port and an output port connected to an input port of the transconductance stage <NUM>. The transconductance stage <NUM> also can include a control terminal. In the illustrated embodiment, the Nth stage <NUM> can include an amplifier stage <NUM> and a transconductance stage <NUM>. The amplifier stage <NUM> can include a control terminal, a first input port and an output port connected to an input port of the transconductance stage <NUM>. Also, the transconductance stage <NUM> can include a control terminal.

The equalizer <NUM> can include an input port and an output port connected to the first input of the amplifier stage <NUM>. The equalizer <NUM> can include an input port and an output port connected to the second input of the amplifier stage <NUM>. By comparison to the first stage <NUM> of <FIG>, the output port of the amplifier <NUM> is the first output port of the first stage <NUM> while an output port of the transconductance stage <NUM> is the second output port of the first stage <NUM>. Also, the output port of the amplifier stage <NUM> can be the first output port of the second stage <NUM> while an output port of the transconductance stage <NUM> can be the second output port of the second stage <NUM>. Additionally, the output port of the amplifier stage <NUM> is the first output port of the Nth stage <NUM> while an output port of the transconductance stage <NUM> is the second output port of the Nth stage <NUM>.

Similar to multi-stage limiting amplifiers of the data receiver systems 200a-200c of <FIG>, the first through Nth stages <NUM>-<NUM> can be connected in cascade with multiple stages as implied by the ellipses. Also, as shown in <FIG>, the second output ports of the first through Nth stages <NUM>-<NUM> connect together to share a common current bus connecting to an input port of the I/V converter <NUM>, and an output port of the I/V converter <NUM> connects to an input port of the signal monitor <NUM>.

As shown in <FIG>, the data receiver system 300a can receive data input signals Dia and/or data input signals Dib. The data input signals Dia are received at the input port of the EQ <NUM>, and the data input signals Dib are received at the input port of the EQ <NUM>. The EQ <NUM> and the EQ <NUM> can equalize the data input signals Dia and Dib, respectively, to have constant gain as a function of frequency. The amplifier <NUM> can provide programmable gain to equalized data signals provided at the output ports of the EQ <NUM> and the EQ <NUM>, and select control signals (not shown) can control the amplifier <NUM> to amplify equalized data signals provided at the output port of the EQ <NUM> or the output port of the EQ <NUM>.

The first through Nth stages <NUM>-<NUM> are shown to also have enable signals. In the first stage <NUM> the control terminal of the amplifier stage <NUM> receives an enable signal eV1 and the control terminal of the transconductance stage <NUM> receives an enable signal egm1. The enable signals eV1 and egm1 can be applied so as to operate the stage <NUM> in either the stage monitor state, the stage cascade state, or the stage blocking state as introduced in the description of <FIG>. In the stage monitor state the enable signal eV1 controls the amplifier stage <NUM> to provide the first cascade output signal as a voltage signal to the input port of the transconductance stage <NUM>; and the enable signal egm1 controls the transconductance stage <NUM> to provide the active output signal by converting the voltage signal to a current signal which is received at the input port of the I/V converter <NUM>. In the stage cascade state, the enable signal eV1 controls the amplifier stage <NUM> to provide the first cascade output signal as a voltage signal to the input port of the next stage; and the enable signal egm1 controls the transconductance stage <NUM> to operate with a high impedance output so as to not load the input port of the I/V converter <NUM>. In the stage blocking state, the enable signal eV1 controls the amplifier stage <NUM> to provide a null cascade output signal and the transconductance stage <NUM> to operate as a high impedance node; in the stage blocking state the first stage <NUM> does not pass the cascade output signal nor the active output signal.

Control and operation of the successive stages including the <NUM>nd stage <NUM> through the Nth stage <NUM> with the enable signals eV2, egm2, eVN, and egmN is similar to the control and operation of the first stage <NUM> with the enable signals eV1 and egm1. Also, the description of operation of the receiver system 300a is similar to that of the receiver systems 200a-200c. However, unlike the receiver systems 200a-200c, the receiver system 300a uses the I/V converter <NUM> to converter the active output signal. The active output signal is a current signal from one of the transconductance stages <NUM>, <NUM> or <NUM> as described above, and the I/V converter <NUM> can convert the current signal to the voltage signal Vs. The voltage signal Vs is monitored by the signal monitor <NUM>.

Advantageously, the eye monitor is communicatively coupled to the low impedance output node of the I/V converter <NUM>; therefore, it does not load the first though Nth stage <NUM>-<NUM> with a parasitic impedance or probe capacitance. By having the enable signals eV1-eVN and egm1-egmN, the total gain of the amplifier <NUM> can be programmed by selectively changing which of the first through Nth stage <NUM>-<NUM> provides the active output signal. And in this way, the first through Nth stages are virtually tested or monitored to determine which combination of enable signals eV1-eVN and egm1-egmN provide the output signal Vs having an open eye diagram. Also, as described above, this can allow some of the stages to operate in a stage blocking state which can be a low power dissipation (power off) or low quiescent state.

<FIG> is a detailed schematic diagram of a data receiver system 300b with configurable signal-processing stages according to another embodiment. The data receiver system 300b is similar to the data receiver system 300a. Furthermore, the system 300b shows a realization having only a single input port receiving an output data signal from the EQ <NUM>. The EQ <NUM> receives the data input signals Din and the operation of the description of the connections and operation of the first through Nth stages <NUM>-<NUM> is similar to the description of the connections and operation of the first through Nth stages <NUM>-<NUM> of <FIG>; however, the first through Nth stages <NUM>-<NUM> within the multi-stage amplifier 300b are shown to have a modified signal flow topology.

In the first through Nth stages <NUM>-<NUM> of <FIG>, the amplifier stages and transconductance stages have an additional port connection. For instance in the first stage <NUM>, an amplifier stage <NUM> is shown to have a single input port and to have a first amplifier output port and a second amplifier output port. The first amplifier output port of the amplifier <NUM> is connected to the input port of the transconductance amplifier <NUM>, and the second amplifier output port of the amplifier <NUM> is connected to the input port of the second stage <NUM>. In this way the amplifier <NUM> of the first stage <NUM> of <FIG> is connected with a different signal flow topology than the amplifier stage <NUM> illustrated in <FIG>.

The signal flow of the cascade output signal and the active output signal of the first stage <NUM> is separated. The enable signal eV1 can control a signal Vx1 and Vy1 to be independent signals as previously discussed in the description of operation of the first stage <NUM> of <FIG>. The cascade output signal follows a path provided from the first output port of the amplifier <NUM>. The enable signal eV1 can control the amplifier <NUM> to provide the signal Vx1 to the input port of the transconductance stage and to provide null signal at the second amplifier output port when the stage <NUM> operates in the stage monitor state. Alternatively, the enable signal eV1 can control the amplifier <NUM> to provide the signal Vy1 to the input port of the second stage <NUM> and to provide a null signal at the first amplifier output port when the first stage <NUM> operates in the stage cascade state. Finally, the enable signal eV1 can control the amplifier <NUM> to provide null signals at both the first and second amplifier output nodes during the stage blocking state.

Description of the signal flow in the successive stages including the second through Nth stages <NUM>-<NUM> can be similar to that described above. The second stage <NUM> includes an amplifier <NUM> with a first and second amplifier output node providing a signal Vx2 and Vy2; and the final stage, the Nth stage <NUM>, is shown to have an amplifier <NUM> with only a first and second amplifier output node providing a signal VxN and VyN. The second amplifier output port provides an output signal VyN for connecting to a second input port of the signal monitor <NUM>.

<FIG> is a detailed schematic diagram of a data receiver system 300c with configurable signal-processing stages according to an embodiment. The data receiver system 300c is similar to the data receiver systems 300a of <FIG> and 300b of <FIG>. Furthermore, the system 300c shows a realization where the Nth stages <NUM>-<NUM> within the data receiver system 300c have a modified signal flow topology as compared to those of the data receiver systems 300b and 300c.

In the first through Nth stages <NUM>-<NUM> of <FIG>, amplifier stages and transconductance stages are shown, as well as input stages. For instance, the first stage <NUM> includes an input stage <NUM>, an amplifier stage <NUM>, and a transconductance stage <NUM>. The input stage <NUM> has a first and second input port connected to the output ports of the EQ <NUM> and <NUM>, respectively. An output port of the input stage <NUM> is connected to an input port of the transconductance stage <NUM> and the amplifier stage <NUM>. Similarly, the second stage <NUM> includes an input stage <NUM>, an amplifier stage <NUM>, and a transconductance stage <NUM>. The input stage <NUM> has an input port connected to the output port of the previous stage <NUM> and an output port connected to an input port of the transconductance stage <NUM> and an input port of the amplifier stage <NUM>. Successive stages can be constructed similarly, and also as shown in <FIG>, the Nth stage <NUM> includes an input stage <NUM>, a transconductance stage <NUM>, and an amplifier stage <NUM>. The input stage <NUM> has an input port connected to an output port of a previous stage as indicated by the ellipses. Also, the input stage <NUM> can include an output port connected to an input port of the transconductance stage <NUM> and to an input port of the amplifier stage <NUM>.

Similar to the stages of the first through Nth stages <NUM>-<NUM> of <FIG>, the stages of <FIG> are connected in cascade. In the illustrated embodiment, an output port of the amplifier stage <NUM> corresponds to the output port of the first stage <NUM>, which connects to the input port of the stage <NUM>. An output port of the amplifier stage <NUM> corresponds to the output port of the second stage <NUM>, which connects to the input port of the successive stage indicated by the ellipses. Also, an output port of the amplifier <NUM> corresponds to the output port of the Nth stage <NUM> which connects to a second input port of the signal monitor <NUM>.

Furthermore, the amplifier and transconductance stages of the first through Nth stages can receive the control signals eV1-eVN and/or egm1-egmN, which can control the individual amplifier/transconductance stage to operate in an on/off state. For example, the amplifier stage <NUM> can receive the control signal egm1 and/or eV1, which can control whether the amplifier stage <NUM> is in an on/off state. Similarly, the transconductance stage <NUM> can receive the control signal egm1 and/or eV1, which can control whether the transconductance stage <NUM> is in an on/off state. It will be understood that each of the stages can receive fewer or more control signals as desired. For example, the amplifier stage <NUM> may only receive the control signal eV1 and/or may receive all of the control signals eV1-eVN and/or egm1-egmN as desired.

Furthermore, the control signals can also be used to control the first through Nth stages <NUM>-<NUM> to operate in various states, such as, but not limited to a stage monitor state, a stage cascade stage, and/or a stage disable state. The description of operation can be similar to that presented above for the first through Nth stages <NUM>-<NUM> of <FIG> and <FIG>.

Although the different gain stages <NUM>, <NUM>, <NUM> are illustrated as including input stages <NUM>, <NUM>, <NUM>, transconductance stages <NUM>, <NUM>, <NUM>, and amplifier stages <NUM>, <NUM>, <NUM>, it will be understood that each stage can include fewer, more, or different components or stages. For example, rather than a transconductance stage and amplifier stage, the different gain stages <NUM>, <NUM>, <NUM>, can include one or more other processing stages (or sub-stages) that process the signal. As described above with reference to the transconductance stages <NUM>, <NUM>, <NUM>, and amplifier stages <NUM>, <NUM>, <NUM>, the one or more processing sub-stages within the gain stages <NUM>, <NUM>, <NUM> can receive control signals (and include control circuitry), which can control whether the individual processing sub-stages are in an on/off state.

<FIG> is a schematic diagram of a configurable stage 400a according to one embodiment. The configurable stage 400a can also be referred to more generally as a stage 400a and can represent a more detailed circuit representation of a stage from the first through Nth stages <NUM>-<NUM> of the previous figures. In the illustrated embodiment, the stage 400a includes an input stage <NUM>, an amplifier stage <NUM>, and a transconductance stage <NUM>.

In the illustrated embodiment, the input stage <NUM> includes the transconductance (Gm) devices <NUM>, <NUM>, the switches <NUM>, <NUM>, and the current source <NUM>; the amplifier stage <NUM> includes the transconductance device <NUM>, the current source <NUM>, the switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, the resistors <NUM>, <NUM>, <NUM>, <NUM>, and the transistors <NUM>, <NUM>; and the transconductance stage <NUM> includes the transconductance device <NUM>, the current source <NUM>, the switches <NUM>, <NUM>, <NUM>, the resistors <NUM>, <NUM>, and the transistors <NUM>, <NUM>. It will be understood that the input stage <NUM>, amplifier stage <NUM>, and/or the transconductance stage <NUM> can include fewer or more components as desired. For example, one of the transconductance devices <NUM>, <NUM> and corresponding switch <NUM>, <NUM> can be omitted, fewer or more resistors, transistors, and/or transconductance devices can be used, as desired. In some embodiments, the Gm devices <NUM>, <NUM>, <NUM>, <NUM> can be implemented using a differential pair, a folded cascade stage, and/or a differential stage, as desired. In some embodiments, the switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> can be implemented using one or more transistors, such as BJTs, FETS, MOS devices, such as MOSFETS, such as NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) FETs, etc. In certain embodiments, the transistors <NUM>, <NUM>, <NUM> can be implemented using BJTs, FETS, MOS devices, such as MOSFETS, or other types of switches.

The Gm devices <NUM>, <NUM>, <NUM>, and <NUM> each have a tail current port, a first and second input port, and a first and second output port. The switch <NUM> is connected between the tail current port of the Gm device <NUM> and a first terminal of the current source <NUM>, and the switch <NUM> is connected between the tail current port of the Gm device <NUM> and the first terminal of the current source <NUM>. A second terminal of the current source <NUM> is connected to ground. The first output port of the Gm device <NUM> is connected to the first output port of the Gm device <NUM>, and the second output port of the Gm device <NUM> is connected to the second output port of the Gm device <NUM>.

The transistor <NUM> is coupled to the second output port of the devices <NUM> and <NUM>, the resistor <NUM>, and the second terminal of the resistor <NUM>. In certain embodiments, such as when the transistor is a MOSFET, the source can be coupled to the second output port of the Gm devices <NUM>, <NUM>, the drain can be connected to the first terminal of the resistor <NUM> and the gate can be coupled to the second terminal of the resistor <NUM>. The transistor <NUM> has a source connected to the first output port of the Gm devices <NUM> and <NUM>, a drain connected to the first terminal of the resistor <NUM>, and a gate connected to the gate of the transistor <NUM>. The transistor <NUM> can be coupled to the second output port of the Gm devices <NUM> and <NUM> and the resistor <NUM>. In the illustrated embodiment, the transistor <NUM> has a source connected to the second output port of the Gm devices <NUM> and <NUM>, a drain connected to a first terminal of the resistor <NUM>, and a gate connected to the second terminal of the resistor <NUM>. The transistor <NUM> can be coupled to the first output port of the Gm devices <NUM> and <NUM>, the resistor <NUM>, the transistor <NUM>. In the illustrated embodiment, the transistor <NUM> has a source connected to the first output port of the Gm devices <NUM> and <NUM>, a drain connected to the first terminal of the resistor <NUM>, and a gate connected to the gate of the transistor <NUM>. Additionally, the second terminal of the resistor <NUM> is connected to the second terminal of the resistor <NUM>, and the second terminal of the resistor <NUM> is connected to the second terminal of the resistor <NUM>.

A first terminal of the current source <NUM> is connected to the tail current port of the Gm device <NUM>, and a second terminal of the current source <NUM> is connected to a first terminal of the switch <NUM>. A second terminal of the switch <NUM> is connected to ground. The first and second input ports of the Gm device <NUM> can be coupled to the transistors <NUM>, <NUM>. In the illustrated embodiment, the first and second input ports of the Gm device <NUM> are connected to the drain of the transistor <NUM> and the drain of the transistor <NUM>, respectively. The first output port of the Gm device <NUM> is connected to the first terminal of the resistor <NUM>, and the second output port of the Gm device <NUM> is connected to the first terminal of the resistor <NUM>. The second terminals of the resistors <NUM> and <NUM> are connected together.

A first terminal of the current source <NUM> is connected to the tail current port of the Gm device <NUM>, and a second terminal of the current source <NUM> is connected to a first terminal of the switch <NUM>. A second terminal of the switch <NUM> is connected to ground. The first and second input ports of the Gm device <NUM> can be coupled to the transistors <NUM>, <NUM>. In the illustrated embodiment, the first and second input ports of the Gm device <NUM> are connected to the drain of the transistor <NUM> and the drain of the transistor <NUM>, respectively. The second terminals of the resistors <NUM> and <NUM> are connected together.

The switch <NUM> is connected between ground and the second terminal of the resistors <NUM> and <NUM>. The switch <NUM> is connected between a supply Vdd and the second terminal of the resistors <NUM> and <NUM>. Also, the switch <NUM> is connected between ground and the second terminal of the resistors <NUM> and <NUM>; and the switch <NUM> is connected between the supply Vdd and the second terminal of the resistors <NUM> and <NUM>. Additionally, the switch <NUM> is connected between ground and the second terminal of the resistors <NUM> and <NUM>; and the switch <NUM> is connected between the supply Vdd and the second terminal of the resistors <NUM> and <NUM>.

A differential data signal DINA is provided across the first and the second input ports of the Gm device <NUM>, and a differential data signal DINB is provided across the first and the second input ports of the Gm device <NUM>. The switch <NUM> and the switch <NUM> be used to determine which of the Gm devices functionally operates within the stage 400a. The switches <NUM> and <NUM> are shown to be controlled by a control signal SelA and a control signal SelB, respectively. When the control signal SelA controls the switch <NUM> to close and to operate as a short while the control signal SelB controls the switch <NUM> to open and to operate as an open circuit, the Gm device <NUM> receives a tail current IT1 from the current source <NUM>. In this way the Gm device <NUM> can convert the differential data signal DINA to a differential cascode signal. The differential cascode signal appears across the first and the second output ports of the Gm device <NUM>. Alternatively, if the control signals SelA and SelB control the switch <NUM> to open and the switch <NUM> to close, then the Gm device <NUM> receives the tail IT1 and converts the differential data signal DINB to a differential cascode signal to appear across the first and the second output ports of the Gm device <NUM>.

The enable signal eV and the enable signal egm can be provided so as to control the stage 400a to operate in either a stage monitor state, a stage cascade state, or a stage blocking state. As shown in <FIG>, the switches <NUM>, <NUM>, <NUM>, and <NUM> receive and are controlled by the control signal eV, while the switches <NUM>, <NUM>, <NUM>, and <NUM> receive and are controlled by the control signal egm.

The stage monitor state can be realized when the control signal egm controls the switches <NUM>, <NUM>, <NUM>, and <NUM> to be closed. Furthermore, in some cases, to enter the stage monitor state, the control signal eV can control the switches <NUM>, <NUM>, <NUM>, and <NUM> to be open as well. Under these conditions transistors <NUM>-<NUM> with resistors <NUM>-<NUM> can operate as an active cascade, which provides a first amplified differential cascode signal across the first and second input ports of the Gm device <NUM>. The Gm device <NUM> receives a tail current IT2 and converts the first amplified differential cascode signal into a differential current signal Iout. The differential current signal Iout corresponds to the active output signal which is provided at the second output port of a stage such as the first through Nth stages <NUM>-<NUM> of <FIG>.

Also under the above described control conditions, the Gm device <NUM> receives no tail current while the first and the second input ports of the Gm device <NUM> are forced to ground potential by virtue of the signal path connection with the switch <NUM>. Additionally, the first and the second output ports of the Gm device <NUM> are forced to ground potential by virtue of the signal path connection with the switch <NUM>; therefore, by inspection the differential output voltage Vout across the first and the second output ports of the Gm device <NUM> is zero or null. In this way the Gm device <NUM> provides a null voltage, a null cascade output signal, at the first output port of a stage such as the first through Nth stages <NUM>-<NUM> of <FIG>.

The stage cascade state can be realized when the control signal egm controls the switches <NUM>, <NUM>, <NUM>, and <NUM> to be open and the control signal eV controls the switches <NUM>, <NUM>, <NUM>, and <NUM> to be closed. Under these conditions, transistors <NUM>-<NUM> with resistors <NUM>-<NUM> operate as an active cascode which provides a second amplified differential cascode signal across the first and second input ports of the Gm device <NUM>. The Gm device <NUM> receives a tail current IT3 and converts the second amplified differential cascode signal into a second differential current signal. The second differential current signal is converted to a differential voltage signal Vout through the resistors <NUM> and <NUM>. The differential voltage signal Vout corresponds to the cascade output signal which is provided at the first output port of a stage such as the first through Nth stages <NUM>-<NUM> of <FIG>. Also under the above described control conditions, the Gm device <NUM> receives no tail current while the first and the second input ports of the Gm device <NUM> are forced to ground by virtue of the signal path connection with the switch <NUM>. By inspection the first and the second output ports of the Gm device <NUM> present high impedance. In this way the Gm device <NUM> provides a high impedance at the second output port of a stage such as the first through Nth stages <NUM>-<NUM> of <FIG>.

The stage blocking state can be realized when the control signal egm controls the switches <NUM>, <NUM>, <NUM>, and <NUM> to be open and the control signal eV controls the switches <NUM>, <NUM>, <NUM>, and <NUM> to be open. Under these conditions the Gm device <NUM> provides a null voltage (Vout is zero) at the first output port and the Gm device <NUM> provides a high impedance at the second output port. This corresponds to providing a null cascade output signal at the first output port and to providing a high impedance at the second output port of a stage such as the first through Nth stages <NUM>-<NUM> of <FIG>.

Using the configurable stage 400a as part of a controllable and programmable multi-stage amplifier or limiting amplifier or other circuit, can offer additional advantages. For instance, the configurable stage 400a can offer a simplified RX design which in turn can reduce complexity and design time compared to using traditional amplifiers. In addition, cascading multiple configurable signal-processing stages can allow a wide gain range with small perturbations on a gain bandwidth product; thus, it can be easier to stabilize multiple signal-processing stages using the configurable stage <NUM> while adjusting gain.

<FIG> is a schematic diagram of a configurable stage 400b according to another embodiment. The configurable stage 400b is similar to the configurable stage 400a in some respects. By comparison to the configurable stage 400a, the configurable stage 400b provides the differential output voltage Vout across the drains of transistors <NUM> and <NUM> instead of at the output of a transconductance device <NUM>.

<FIG> is a schematic diagram of a configurable stage 400c according to another embodiment. The configurable stage 400c is similar to the configurable stage 400b, except it can operate as an equalizer to equalize the differential input given by the difference of a noninverting signal Vp and and inverting signal Vn and to provide the equalized signal at the differential output Vout.

The configurable stage 400c is similar to the configurable stage 400b except instead of including transconductance devices <NUM> and <NUM> with the current source <NUM>, it includes a transistor <NUM>, a transistor <NUM>, a capacitor <NUM>, a resistor <NUM>, a current source <NUM>, a current source <NUM>, and a switch <NUM>.

The transistors <NUM>, <NUM>, with the current sources <NUM>, <NUM>, and with resistor <NUM> and capacitor <NUM> form a source degenerated differential pair which can have a frequency dependent transconductance gm. The values of the resistor <NUM> and the capacitor <NUM> can be selected to control the equalization of a differential signal determined by the difference of the noninverting signal Vp at the gate of the transistor <NUM> and the inverting signal Vn at the gate of the transistor <NUM>.

The current source <NUM> provides tail current IT4 to the source degenerated transistor pair at the source of the transistor <NUM>, and the current source <NUM> provides tail current IT5 to the source degenerated transistor pair at the source of the transistor <NUM>.

The switch <NUM> is controlled by a control signal enAv to enable the configurable stage 400c to operate as a differential amplifier without degeneration when the switch <NUM> is closed. In this mode the operation of the configurable stage 400c is similar to that of 400b except with a single differential input signal determined by the difference of Vp and Vn. When the control signal enAv controls the switch <NUM> to be open, the configurable stage 400c operates as an equalizer allowing the equalized signal to either appear at the output of the Gm device <NUM> as the differential current output Iout or as a differential output voltage Vout at the output across the drains of transistors <NUM> and <NUM>. The operation transferring the equalized signal to either Iout or Vout can be similar to the operation described for the configurable stage 400a, which is based upon the state of the control signals eV and egm.

Although the different configurable stages 400a, 400b, 400c are illustrated as input stage <NUM>, an amplifier stage <NUM>, and a transconductance stage <NUM>, it will be understood that the configurable stages 400a, 400b, 400c can include fewer, more, or different components or stages. For example, rather than a transconductance stage <NUM> and amplifier stage <NUM>, the configurable stages 400a, 400b, 400c, can include one or more other processing stages (or sub-stages) that process the signal. For instance, in some embodiments the transconductance stage <NUM> can be derived with fewer components or without the Gm device <NUM>. For example, in certain embodiments, the differential current output Iout can be derived directly from the drains of transistors <NUM> and <NUM> allowing the Gm device <NUM>, the current source <NUM>, and the switch <NUM>, to be excluded. In this way the transconductance stage <NUM> can comprise the transistors <NUM>, <NUM> and the switches <NUM>, <NUM> with the drains of the transistors <NUM>, <NUM> providing the differential current output Iout. As described above with reference to the transconductance stage <NUM>, and amplifier stage <NUM>, the one or more processing sub-stages within the configurable stages 400a, 400b, 400c can include control circuitry, such as switches <NUM>, <NUM>, <NUM>, <NUM>, which can control whether the individual processing sub-stages are in an on/off state. When in an off state, the processing sub-stage can provide a null voltage and/or high impedance at the output port so as to not load the input port of another gain stage or signal monitor.

Devices employing the above described adaptable receiver amplifiers can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include circuits of optical networks or other communication networks. The consumer electronic products can include, but are not limited to, an automobile, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multifunctional peripheral device, etc. Further, the electronic device can include unfinished products, including those for industrial, medical and automotive applications.

The foregoing description and claims may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Claim 1:
A limiting amplifier comprising: :
a plurality of cascaded stages comprising a first stage and one or more subsequent stages, wherein each stage of the plurality of cascaded stages comprises:
an input stage (<NUM>) configured to amplify input signals;
a first stage output;
a second stage output coupled to a common bus;
an amplifier stage (<NUM>) coupled to the input stage (<NUM>) and the first stage output; and
a transconductance stage (<NUM>) coupled to the input stage (<NUM>) and to the second stage output, wherein at least one of the amplifier stage (<NUM>) or the transconductance stage (<NUM>) is configured to operate in a plurality of states, and wherein further:
the stage of the limiting amplifier is configured to operate in a plurality of states based at least in part on the state of at least one of the amplifier stage (<NUM>) or the transconductance stage (<NUM>);
an input port of the amplifier stage (<NUM>) is connected to an output port of the input stage (<NUM>) and the amplifier stage (<NUM>) provides a signal to the first stage output; and
an input port of the transconductance stage (<NUM>) is connected to an output port of the input stage (<NUM>) and an output port of the transconductance stage (<NUM>) is connected to the second output port,
wherein the input stage (<NUM>) of each of the one or more subsequent stages of the plurality of cascaded stages is coupled to the first stage output of a previous stage of the plurality of cascaded stages; and
a current-to-voltage converter (<NUM>) coupled to the common bus.