Patent Description:
MRAM is a type of non-volatile memory used in computers and other electronic devices to store data. Unlike conventional read-access memory (e.g., dynamic read-access memory (DRAM)), which stores data as electric charge or current flows (e.g., using capacitors), MRAM stores the data in magnetic domains using magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by an insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a magnetic tunnel junction and is one example structure for an MRAM cell. A memory device is built from an array of such "cells". <CIT>) discloses that a bit state in a supply-switched dual cell memory bitcell may be read by coupling a supply line to a common node of the bitcell to drive complementary currents through complementary resistance state storage cells for a pair of complementary bit line signal lines of the bitcell. The bit state of the bitcell may be read by sensing complementary bit state signals on the pair of first and second complementary bit line signal lines. In one embodiment, each resistance state storage cell has a resistance state ferromagnetic device such as a magnetic-tunneling junction (MTJ). In one embodiment, a supply-switched dual cell memory bitcell in accordance with the present description may lack a source or select line (SL) signal line. <CIT>) discloses a device including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.

The present invention is defined by a magnetoresistive random-access memory (MRAM) device according to independent claim <NUM> and a method of forming a two-bit MRAM device according to independent claim <NUM>.

Advantageous features are set out in the dependent claims.

The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention.

The drawings included in the present disclosure are incorporated into, and form part of, the specification. They illustrate embodiments of the present invention and, along with the description, serve to explain the principles of the invention. The drawings are only illustrative of typical embodiments and do not limit the invention.

Aspects of the present invention relate generally to the electrical, electronic, and computer fields, and in particular to two-bit magnetoresistive random-access memory (MRAM) cells having three transistors and methods of manufacturing the same. While the present invention is not necessarily limited to such applications, various aspects of the invention may be appreciated through a discussion of various examples using this context.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the present invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layer "C") is between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

For purposes of the description hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms "overlying," "atop," "on top," "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted, the term "selective to," such as, for example, "a first element selective to a second element," means that a first element can be etched, and the second element can act as an etch stop.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography.

Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing ("RTA"). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present invention, in general, a single-bit MRAM cell refers to any material or combination of materials capable of storing a value (e.g., bit of information) using magnetic storage elements. An MRAM cell value, which can be binary ('<NUM>' or '<NUM>') or analog (e.g., <NUM>), is stored in the memory cell as a function of the cell's electrical resistance, similar to how values are stored in resistive random-access memory (ReRAM or RRAM) cells and/or memristors. In other words, the relative orientation of the magnetization of the plates within the MRAM cell affects the electrical resistance of the MRAM cell. This electrical resistance can be measured by passing a current through the MRAM cell, and the measured electrical resistance can be converted into a value.

A substantial drawback of current single-bit MRAM device architecture is the use of one transistor for each MRAM cell to perform a write operation. This one-to-one ratio of transistors to MRAM cells is important for preventing interference with an unintended MRAM cell that shares a common transistor with the intended MRAM cell. The drawback of this one-to-one ratio is that the required number of transistors limits the bit density of the MRAM device. Moreover, the transistors must be large to support the required driving current for writing operations, further limiting bit density, and thus scaling.

Some attempts to increase the low bit density of MRAM devices have focused on creating multi-bit MRAM cells by using vertically stacked multi-bit cells. However, such solutions fail to address the need for a one-to-one transistor to MRAM cell ratio for read and write operations.

Embodiments of the present invention may overcome these and other drawbacks of current solutions by using a two-bit MRAM cell architecture that uses one shared transistor for two single-bit MRAM cells to perform a write operation. In other words, the two-bit MRAM cell architecture disclosed herein is an architecture for linking two single-bit MRAM cells together. Accordingly, it is also possible to refer to the two-bit MRAM cell disclosed herein as a two-bit MRAM device, wherein the two-bit MRAM device includes two separate single-bit MRAM cells that share a common transistor. This architecture is made possible by the incorporation of selector devices, for example selector switches or selector diodes, that prevent unintended access to the other MRAM cell connected to a shared transistor during a read or write operation. This architecture, described in more detail below, reduces by half the number of transistors required for read and write operations for each pair of MRAM cells. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory. Accordingly, halving the number of transistors reduces the density of transistors, which can enable inclusion of a greater number of MRAM cells and/or allow larger transistors to be developed, which provide higher drive current.

According to at least some embodiments of the present invention, each two-bit MRAM cell comprises a pair of single-bit MRAM cells. Each single-bit MRAM cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ). According to at least some embodiments of the present invention, each MTJ includes a free layer in contact with the top electrode, a reference layer in contact with the bottom electrode, and a tunnel barrier arranged between and in contact with the free layer and the reference layer. In other words, in each MTJ stack, the reference layer is separated from the free layer by the tunnel barrier.

The free layer of each single-bit MRAM cell can be programmed independently by passing 'write' current therethrough. Accordingly, by selectively activating the transistors and the selector devices associated with the two-bit MRAM cell, current can be allowed to flow through just one of the single-bit MRAM cells, thereby setting the magnetic orientation of each of the free layers independently. This allows each bit to be individually written to the two-bit MRAM cell.

The state of each single-bit MRAM cell is determined by passing 'read' current through the MTJ stack of the single-bit MRAM cell and measuring the associated resistance state of the corresponding MTJ stack. By selectively activating the transistors and the selector devices associated with the two-bit MRAM cell, current can be allowed to flow through the MTJ stack of just one of the single-bit MRAM cells, thereby reading the magnetic orientation of each of the single-bit MRAM cells independently. This allows the value of each bit of the two-bit MRAM cell to be read individually.

The incorporation of the selector devices in the two-bit MRAM cell architecture allows two single-bit MRAM cells to share a common transistor and allows each bit to be written and read independently while preventing unintended interference with the other bit. This results in a significant space saving for the two-bit MRAM cell. Because two single-bit MRAM cells can share a common transistor and the selective operation of the selective devices allows read and write operations to be performed on each single-bit MRAM cell independently, the number of transistors required for read and write operations for each two-bit MRAM cell is halved.

Additional embodiments of the present invention include a method of forming such a two-bit MRAM cell. In at least some embodiments, such a method includes forming a bottom electrode contact for each single-bit MRAM cell of a pair of single-bit MRAM cells, the bottom electrode contacts spaced apart from each other on a common landing pad. Such bottom electrode contacts can be formed, for example, by performing either a subtractive process or a damascene process.

In at least some embodiments, such a method further includes patterning the material of a selector device, such as a selector switch or a selector diode, along with the MRAM device using, for example, ion beam etch (IBE) or reactive ion etch (RIE) processes. The material of such selector devices can be, for example, SiOx, TiOx, AlOx, WOx, TiNOx, HfOx, TaOx, NbOx, or a material with similar characteristics. In particular, the material of such selector devices acts as an insulator unless a voltage above a particular threshold voltage is applied, in which case the material acts as a conductor. Additionally, the material of such selector devices is such that said conversion process happens reversibly. In particular, the material acts as an insulator again once the applied voltage is removed.

In at least some embodiments, such a method further includes forming metal lines connecting top electrode contacts of each single-bit MRAM cell of a pair of single-bit MRAM cells. In such embodiments, the metal lines can be formed by performing, for example, a damascene process.

It is to be understood that the aforementioned advantages are example advantages and should not be construed as limiting. Embodiments of the present invention can contain all, some, or none of the aforementioned advantages while remaining within the scope of the present invention.

Turning now to the figures, <FIG> depicts a block diagram of an example configuration of a two-bit MRAM cell <NUM>, in accordance with embodiments of the present invention. The MRAM cell <NUM> includes a first single-bit MRAM cell <NUM> and a second single-bit MRAM cell <NUM>. Each of the first and second single-bit MRAM cells <NUM>, <NUM> provides a single storage bit. Together, these single bits make up the pair of bits of the two-bit MRAM cell <NUM>.

The two-bit MRAM cell <NUM> can be utilized as part of a larger array of MRAM cells. For example, <FIG> depicts a second two-bit MRAM cell <NUM> that is substantially identical in structure and function to the MRAM cell <NUM> and is connected to the MRAM cell <NUM>. Accordingly, the second two-bit MRAM cell <NUM> includes a third single-bit MRAM cell <NUM> and a fourth single-bit MRAM cell <NUM> that are arranged and configured to function in a manner substantially identical to the first and second single-bit MRAM cells <NUM>, <NUM>, respectively.

The MRAM cells of the array are connected by word lines, such as first word line <NUM> and second word line <NUM>, and bit lines, such as first bit line <NUM> and second bit line <NUM>, to enable programming and reading the bits of information stored in the MRAM cells. The ellipses shown in <FIG> indicate that the array may continue with further MRAM cells, connected by further word lines and bit lines, beyond the those shown for illustrative purposes. As shown, the first MRAM cell <NUM> and the second MRAM cell <NUM> are connected by the first bit line <NUM> and the second bit line <NUM>.

The MRAM cell <NUM> further includes a first transistor <NUM>, which is connected to and associated with the first single-bit MRAM cell <NUM> by way of the first bit line <NUM>, a second transistor <NUM>, which is connected to and associated with the second single-bit MRAM cell <NUM> by way of the second bit line <NUM>, and a third transistor <NUM>, which is connected to and associated with both single-bit MRAM cells <NUM>, <NUM> by way of the first and second bit lines <NUM>, <NUM> and the first word line <NUM>.

In the embodiment shown, the first transistor <NUM> and the second transistor <NUM> are included in a multiplexer <NUM> which selects between multiple input signals and forwards the selected input to a single output line by operating the corresponding transistor. In alternative embodiments, the first and second transistors may not be part of a multiplexer, but still function in substantially the same manner described below. Similarly, in the embodiment shown, the first word line <NUM> and the second word line <NUM> are selectively operated by a row address decoder <NUM>. In alternative embodiments, the first and second word lines may not be selectively operated by a row address decoder, but still function in substantially the same manner described below. The ellipses shown in <FIG> indicate that the multiplexer <NUM> and row address decoder <NUM> may have connections to further bit lines and word lines, respectively, beyond the those shown for illustrative purposes.

The second MRAM cell <NUM> is considered to include the same first transistor <NUM>, which is connected to and associated with the third single-bit MRAM cell <NUM> by way of the first bit line <NUM>, and the same second transistor <NUM>, which is connected to and associated with the fourth single-bit MRAM cell <NUM> by way of the second bit line <NUM>. In lieu of the third transistor <NUM>, however, the second MRAM cell <NUM> includes a fourth transistor <NUM>, which is connected to and associated with both single-bit MRAM cells <NUM>, <NUM> by way of the first and second bit lines <NUM>, <NUM> and the second word line <NUM>.

The first and second transistors <NUM>, <NUM>, which are connected to the bit lines <NUM>, <NUM>, respectively, and which are shared by multiple two-bit MRAM cells in an array, can be referred to as being located in and/or operated in a "logic area" of a memory storage device. Transistors located in and/or operated in a logic area are used to switch on and off various bit lines and word lines of the array to allow read and write currents to travel to specific locations within the array. In contrast, the third transistor <NUM>, the fourth transistor <NUM>, and similar transistors in other two-bit MRAM cells of the array can be referred to as being located in and/or operated in a "memory area" of a memory storage device. A transistor located in and/or operated in a memory area is used to switch on and off a specific, individual MRAM cell to allow read and write currents to travel through the specific, individual corresponding MRAM cell within the array to perform read and write operations on that corresponding MRAM cell.

The MRAM cell <NUM> further includes a first selector device <NUM>, which is connected to and associated with the first single-bit MRAM cell <NUM>, and a second selector device <NUM>, which is connected to and associated with the second single-bit MRAM cell <NUM>. More specifically, the first single-bit MRAM cell <NUM> is connected to the third transistor <NUM> through the first selector device <NUM>. Similarly, the second single-bit MRAM cell <NUM> is connected to the third transistor <NUM> through the second selector device <NUM>.

Notably, in alternative embodiments of the present invention, it is possible for the first selector device <NUM> to be arranged on the opposite side of the first single-bit MRAM cell <NUM> such that the first single-bit MRAM cell <NUM> is not necessarily connected to the third transistor <NUM> through the first selector device <NUM>, but both the first selector device <NUM> and the first single-bit MRAM cell <NUM> are connected in series between the first bit line <NUM> and the third transistor <NUM>. Similarly, in alternative embodiments of the present invention, it is possible for the second selector device <NUM> to be arranged on the opposite site of the second single-bit MRAM cell <NUM> such that the second single-bit MRAM cell <NUM> is not necessarily connected to the third transistor <NUM> through the second selector device <NUM>, but both the second selector device <NUM> and the second single-but MRAM cell <NUM> are connected in series between the second bit line <NUM> and the third transistor <NUM>.

Likewise, the second MRAM cell <NUM> includes a third selector device <NUM> and a fourth selector device <NUM> arranged such that the third single-bit MRAM cell <NUM> is connected to the fourth transistor <NUM> through the third selector device <NUM> and the fourth single-bit MRAM cell <NUM> is connected to the fourth transistor <NUM> through the fourth selector device <NUM>.

In the embodiment shown in <FIG>, each of the selector devices <NUM>, <NUM>, <NUM>, and <NUM> is a selector switch. Each of the selector switches is configured to be closed by applying a voltage across the switch. In particular, to activate the selector switch (also referred to as "closing" or "turning on" the selector switch), a voltage across the switch must be at least as large as a particular switch threshold Vs. In accordance with at least some embodiments of the present invention, all of the selector switches have the same switch threshold Vs. As discussed in further detail below, however, it is possible in alternative embodiments to configure the selector switches to have switch thresholds that are different from one another.

Each of the transistors <NUM>, <NUM>, <NUM>, and <NUM> is a semiconductor device used as an electrically controlled switch. Thus, each of the transistors <NUM>, <NUM>, <NUM>, <NUM> is used to switch on and off the flow of electrical current therethrough. Each transistor conducts current only when a voltage is applied to its gate. In other words, when no voltage is applied to the transistor's gate, the switch is off and no current is conducted through the transistor. In contrast, when voltage is applied to the transistor, the switch is on and current is conducted through the transistor. In alternative embodiments, it may be possible for the transistors to operate in a different manner known to one of ordinary skill in the art or for a different type of transistor to be used.

As explained in further detail below, the inclusion, switch threshold voltages, and particular arrangement of the selector devices <NUM>, <NUM>, <NUM>, <NUM> enable the first and second single-bit MRAM cells <NUM>, <NUM> to share the common third transistor <NUM> while keeping operations pertaining to the first single-bit MRAM cell <NUM> separate from those pertaining to the second single-bit MRAM cell <NUM>.

Turning now to <FIG>, a schematic drawing of the first MRAM cell <NUM> in a side elevational view depicts the architecture of each single-bit MRAM cell in more detail. In particular, each single-bit MRAM cell <NUM>, <NUM> includes a top electrode <NUM>, which is arranged nearest to the respective bit line <NUM>, <NUM>, and a bottom electrode <NUM>, which is arranged nearest to the third transistor <NUM>. Each single-bit MRAM cell <NUM>, <NUM> further includes an MTJ <NUM> arranged between the top electrode <NUM> and the bottom electrode <NUM>. Each MTJ <NUM> includes a free layer <NUM>, arranged nearest to the top electrode <NUM>, a reference layer <NUM>, arranged nearest to the bottom electrode <NUM>, and a tunnel barrier layer <NUM>, arranged between the free layer <NUM> and the reference layer <NUM>.

As noted above, to program a single-bit MRAM cell, a write current is passed therethrough, altering the free layer therein. Accordingly, in the context of the two-bit MRAM cell <NUM>, to program a first of the two bits, the first single-bit MRAM cell <NUM> is selected by turning on the first transistor <NUM>, which activates the first bit line <NUM>, to which the first single-bit MRAM cell <NUM> is connected. Additionally, by applying a voltage to the first word line <NUM>, the third transistor <NUM> is turned on, which allows current to flow through the first single-bit MRAM cell <NUM> to a source line <NUM> as shown in <FIG>. In the embodiment shown in <FIG>, the source line <NUM> is shown as a ground. However, in alternative embodiments, the source line <NUM> can be a ground, a neutral, or another common line which completes the circuit. In accordance with at least some embodiments of the present invention, the source line <NUM> feeds the signal to a sense amplifier circuit to determine the bit value.

Importantly, while the first single-bit MRAM cell <NUM> is being programmed, the second transistor <NUM> is turned off. This prevents current from being passed along the second bit line <NUM> and through the second single-bit MRAM cell <NUM>, which would alter the free layer <NUM> of the second single-bit MRAM cell <NUM> while the first single-bit MRAM cell <NUM> is being programmed. Additionally, as explained in further detail below, the selector device <NUM>, in conjunction with selector devices <NUM>, <NUM>, prevents current from flowing into the free layer <NUM> of the second single bit MRAM cell <NUM>, which could happen even with the second transistor <NUM> being off (e.g., due to effects such as leakage and parasitic capacitances in the circuit, such as in the second transistor), as well as due to alternate paths through the array, as described below with respect to <FIG>.

Accordingly, while performing a write operation to program the first bit of the two-bit MRAM cell <NUM>, when the bit of the first single-bit MRAM cell <NUM> is to be programmed, the first transistor <NUM> is turned on, the second transistor <NUM> is turned off, and the third transistor <NUM> is turned on. In contrast, as explained in further detail below, when the bit of the second single-bit MRAM cell <NUM> is to be programmed, the first transistor <NUM> is turned off, the second transistor <NUM> is turned on, and the third transistor <NUM> is turned on.

Continuing with the example of programming the bit of the first single-bit MRAM cell <NUM>, to alter the free layer <NUM> in the first single-bit MRAM cell <NUM>, the write voltage must be above a particular write threshold Vw. Accordingly, the write current, which is passed along the first bit line <NUM> and through the first single-bit MRAM cell <NUM> has a voltage that is as least as large as the write threshold Vw. In the embodiments disclosed herein, the write threshold Vw is larger than the switch threshold Vs of the first selector switch <NUM>.

As shown in <FIG>, during an operation to program first single-bit MRAM cell <NUM>, the write current travels along the path which is indicated for illustrative purposes by the arrows <NUM>. The write current is driven by a voltage that is at least as large as the write threshold Vw, which is sufficient to alter the free layer <NUM> of the first single-bit MRAM cell <NUM>. Because, as mentioned above, write threshold Vw is larger than the switch threshold Vs of the first selector switch <NUM>, the write current is also sufficient to close (turn on) the first selector switch <NUM>. Accordingly, because the first transistor <NUM>, the first selector switch <NUM>, and the third transistor <NUM> are all turned on, the write current travels along the path <NUM> to the source line <NUM> and programs the first single-bit MRAM cell <NUM> as it passes therethrough.

Because the second transistor <NUM> is off, the path <NUM> is the preferred path (also referred to as the "primary path") for the write current through the two-bit MRAM cell <NUM> to the source line <NUM>. In contrast, <FIG> depicts an alternate path (also referred to as the "secondary path"), which is indicated for illustrative purposes by the arrows <NUM>, for the write current through the two-bit MRAM cell <NUM> to the source line <NUM>.

As shown in <FIG>, the secondary path <NUM> for the write current through the two-bit MRAM cell <NUM> to the source line <NUM> includes the first bit line <NUM>, the third single-bit MRAM cell <NUM>, the third selector switch <NUM>, the fourth selector switch <NUM>, the fourth single-bit MRAM cell <NUM>, the second bit line <NUM>, the second single-bit MRAM cell <NUM>, the second selector switch <NUM>, and the third transistor <NUM>. Accordingly, the secondary path <NUM> illustrates that it would be possible for a write current that is intended to program the first single-bit MRAM cell <NUM> to inadvertently impact the second single-bit MRAM cell <NUM>. A current which travels along this secondary path <NUM> and inadvertently impacts the unintended single-bit MRAM cell of the two-bit MRAM cell may be referred to as "sneak current" or "leak current.

To prevent the sneak current from passing through the second single-bit MRAM cell <NUM> during a write operation intended to program the first single-bit MRAM cell <NUM>, the secondary path <NUM> must be interrupted. To interrupt the secondary path <NUM>, each of the selector switches <NUM>, <NUM>, <NUM>, <NUM> is configured such that the switch threshold Vs is less than the write threshold Vw and such that the sum of three of the switch thresholds Vs is greater than the write threshold Vw. In other words, the selector switches <NUM>, <NUM>, <NUM>, <NUM> are configured such that Vs < Vw < 3Vs.

Because the third, fourth, and second selector switches <NUM>, <NUM>, <NUM> are connected in series along the secondary path <NUM>, their switch thresholds are cumulative. Accordingly, in order to complete the circuit such that passage of the write current along the secondary path <NUM> possible, the voltage of the write current must be larger than the switch thresholds of the third, fourth, and second selector switches <NUM>, <NUM>, <NUM> added together. By configuring the selector switches <NUM>, <NUM>, <NUM>, <NUM> such that Vw < 3Vs, the write current is insufficient to activate the third, fourth, and second selector switches <NUM>, <NUM>, <NUM>, and therefore the secondary path <NUM> is interrupted and the sneak current is prevented from unintentionally passing through the second single-bit MRAM cell <NUM>.

Accordingly, the inclusion and arrangement of the selector switches makes it possible to prevent the sneak current from passing through the second single-bit MRAM cell <NUM> by configuring the two-bit MRAM cell <NUM> such that the write current has a voltage that is sufficient to alter the free layer <NUM> of the first single-bit MRAM cell <NUM>, is sufficient to close the first selector switch <NUM>, and is insufficient to close all three of the third, fourth, and second selector switches <NUM>, <NUM>, <NUM> in series.

As one example, if the write threshold Vw is <NUM> millivolts, this could be achieved by configuring all of the selector switches <NUM>, <NUM>, <NUM>, <NUM> to have a switch threshold Vs of approximately <NUM> millivolts. This example satisfies the condition of Vs < Vw < 3Vs because <NUM> < <NUM> < <NUM>. In such an example, a write current of approximately <NUM> millivolts is sufficient to alter the free layer <NUM> of the first single-bit MRAM cell <NUM> and is sufficient to close the first selector switch <NUM>, but it is insufficient to close all three of the third, fourth, and second selector switches <NUM>, <NUM>, <NUM>.

In the foregoing illustrative discussion, the first single-bit MRAM cell <NUM> is the first of the two bits of the MRAM cell <NUM> to be programmed. It is possible, of course, for the second single-bit MRAM cell <NUM> to be the first of the two bits of the MRAM cell to be programmed instead. It is analogously possible to program the second single-bit MRAM cell <NUM> of the MRAM cell <NUM> in the same manner by turning off the first transistor <NUM>, turning on the second transistor <NUM>, and turning on the third transistor <NUM>. When the first transistor <NUM> is turned off and the second and third transistors <NUM>, <NUM> are turned on, the primary path for the write current travels along the second bit line <NUM>, through the second single-bit MRAM cell <NUM>, through the second selector switch <NUM>, through the third transistor <NUM>, and to the source line <NUM>. The secondary path for the write current travels along the second bit line <NUM>, through the fourth single-bit MRAM cell <NUM>, through the fourth selector switch <NUM>, through the third selector switch <NUM>, through the third single-bit MRAM cell <NUM>, through the first bit line <NUM>, through the first single-bit MRAM cell <NUM>, through the first selector switch <NUM>, and through the third transistor <NUM> to the source line <NUM>.

Accordingly, in substantially the same manner as described above, it is possible to prevent the write current intended to program the second single-bit MRAM cell <NUM> from sneaking along the secondary path and unintentionally altering the first single-bit MRAM cell <NUM> by configuring the MRAM cell <NUM> such that the switch thresholds relative to the write threshold satisfy the condition Vs < Vw < 3Vs.

As noted above, to determine the state of a two-bit MRAM cell, a read current is passed through the MTJ stack of each single-bit MRAM cell. Accordingly, in the context of the two-bit MRAM cell <NUM>, the value of each bit is read individually in a manner substantially similar to the write process described above.

To read the value of a bit without interfering with the value of the bit, a read current has a voltage that is less than that of a write current. Accordingly, the read current can be passed through the MTJ to determine the value of the free layer without altering the free layer. More specifically, to read the value stored by the MTJ, the read voltage must be above a particular read threshold Vr, and to prevent interfering with the value of the bit, the read voltage must be less than the write threshold Vw. Thus, the read threshold Vr is less than the write threshold Vw. In other words, Vr < Vw.

Moreover, analogously to the write operations described above, the read current must have a voltage that is at least as great as the read threshold Vr and that is less than three times the switch threshold Vs. In other words, Vs < Vr < 3Vs. Accordingly: Vs < Vr < Vw < 3Vs. Continuing with the example voltages provided above, if the write threshold Vw is approximately <NUM> millivolts and the switch threshold Vs is approximately <NUM> millivolts, the read threshold Vr could be, for example, approximately <NUM> millivolts. This example satisfies the condition of Vs < Vr < Vw < 3Vs because <NUM> < <NUM> < <NUM> < <NUM>.

During an operation to read a first of the two bits, the first transistor <NUM> is turned on, the second transistor <NUM> is turned off, and the third transistor <NUM> is turned on. Accordingly, the read current, which has a voltage of, for example approximately <NUM> millivolts, travels along the primary path <NUM> (shown in <FIG>) to read the value of the first single-bit MRAM cell <NUM>. Additionally, the third, fourth, and second selector switches <NUM>, <NUM>, <NUM>, each of which has an individual switch threshold of, for example <NUM> millivolts such that a combined switch threshold is, for example approximately <NUM> millivolts, prevent current leakage from traveling along the secondary path <NUM> (shown in <FIG>) and passing through the second single-bit MRAM cell <NUM>.

It should be understood that it is analogously possible to read the value stored by the second single-bit MRAM cell <NUM> of the MRAM cell <NUM> in the same manner by turning off the first transistor <NUM>, turning on the second transistor <NUM>, and turning on the third transistor <NUM>. When the first transistor <NUM> is turned off and the second and third transistors <NUM>, <NUM> are turned on, the primary path for the read current travels along the second bit line <NUM>, through the second single-bit MRAM cell <NUM>, through the second selector switch <NUM>, through the third transistor <NUM>, and to the source line <NUM>. The secondary path for the read current travels along the second bit line <NUM>, through the fourth single-bit MRAM cell <NUM>, through the fourth selector switch <NUM>, through the third selector switch <NUM>, through the third single-bit MRAM cell <NUM>, through the first bit line <NUM>, through the first single-bit MRAM cell <NUM>, through the first selector switch <NUM>, and through the third transistor <NUM> to the source line <NUM>.

Accordingly, in substantially the same manner as described above, it is possible to prevent the read current intended to determine the value stored by the second single-bit MRAM cell <NUM> from sneaking along the secondary path and unintentionally reading the first single-bit MRAM cell <NUM> by configuring the switch thresholds relative to the read threshold such that Vs < Vr < 3Vs. As noted above with respect to individually programming the single-bit MRAM cells <NUM>, <NUM>, it is possible to read the value stored by the single-bit MRAM cells <NUM>, <NUM> in either order.

In order for the selector switches to direct the read and write currents in the manner described above, each of the first and second selector switches <NUM>, <NUM> must be arranged between the junction where the primary path and the secondary path rejoin one another and the top electrode <NUM> of the corresponding single-bit MRAM cell.

For example, in the embodiment depicted in <FIG>, the first selector switch <NUM> is directly connected to the bottom electrode <NUM> of the first single-bit MRAM cell <NUM> such that the first selector switch <NUM> is arranged between the bottom electrode <NUM> and a shared bottom contact <NUM> where the primary path and the secondary path rejoin one another. In accordance with alternative embodiments of the present invention, it is possible for the first selector switch <NUM> to be arranged at another location between the respective bit line <NUM> and the shared bottom contact <NUM> where the primary path and the secondary path rejoin one another. For example, in accordance with an alternative embodiment of the present invention, it is possible for the first selector switch <NUM> to be arranged between the top electrode <NUM> and the MTJ <NUM>. In accordance with another embodiment of the present invention, it is possible for the first selector switch <NUM> to be arranged between two layers of the bottom electrode <NUM> or the top electrode <NUM>.

<FIG> depicts a flowchart of a method <NUM> of operating the two-bit MRAM cell <NUM>. The two-bit MRAM cell is operated by, or as part of, a memory system (also referred to herein as a memory storage device) which includes an array of two-bit MRAM cells such as the two-bit MRAM cells <NUM>, <NUM> shown in <FIG>. The method <NUM> may be performed by hardware, firmware, software executing on a processor, or any combination thereof. For example, the method <NUM> may be performed by a memory controller (e.g., in a processor).

At operation <NUM>, the system receives a write command to program a first bit or a read command to determine the value stored in a first bit. At operation <NUM>, the system determines that the first bit is to be stored or is stored in a particular MTJ. As an illustrative example, the system determines that the first bit is to be stored or is to be stored in the MTJ <NUM> (shown in <FIG>) of the first single-bit MRAM cell <NUM> of the two-bit MRAM cell <NUM>.

At operation <NUM>, the system selectively activates transistors to cause current to flow through the particular MTJ. As an illustrative example, the system selectively activates the first transistor <NUM> and the third transistor <NUM> (shown in <FIG>) to cause the write current or read current to flow through the MTJ <NUM> of the first single-bit MRAM cell <NUM> of the two-bit MRAM cell <NUM>.

Due to the arrangement of the transistors and the selector switches in the two-bit MRAM cell and the relative voltages and threshold voltages of the single-bit MRAM cells and selector switches, causing current to flow through the particular MTJ also causes current to flow through the selector device that corresponds to the particular MTJ. According to the illustrative example, causing current to flow through the MTJ <NUM> of the first single-bit MRAM cell <NUM> causes current to flow through the first selector switch <NUM>. As described above, this flow occurs because the read and write voltages of the first single-bit MRAM cell <NUM> are greater than the threshold voltage of the first selector switch <NUM>. Accordingly, causing current to flow through the particular MTJ includes causing current to flow through the corresponding selector device.

The illustrative example set forth above describes the method <NUM> when the method is used to program or to read the first single-bit MRAM cell <NUM>. In other words, the same method <NUM> is used to perform either a read operation or a write operation. Moreover, it is to be understood that the same method <NUM> is used to program or read either the first single-bit MRAM cell <NUM> or the second single-bit MRAM cell <NUM> when it is determined at operation <NUM> that the particular MTJ is the MTJ <NUM> of the second single-bit MRAM cell <NUM> of the two-bit MRAM cell <NUM>. This is done by simply changing which of the first and second transistor is activated.

As noted above, in the embodiments of the MRAM cells <NUM>, <NUM> shown in <FIG>, <FIG>, and <FIG>, the selector devices <NUM>, <NUM>, <NUM>, <NUM> are selector switches. In alternative embodiments, however, the selector devices <NUM>, <NUM>, <NUM>, <NUM> can be selector diodes. In further alternative embodiments, some of the selector devices may be selector switches and some may be selector diodes.

<FIG> depicts an embodiment of the present invention wherein the selector devices <NUM>, <NUM>, <NUM>, <NUM> are selector diodes. Each selector diode is configured to conduct current primarily in one direction, commonly referred to as the "forward" direction. Accordingly, embodiments of the MRAM cells <NUM>, <NUM> which include selector switches may be referred to as having "symmetric" selector devices while embodiments of the MRAM cells <NUM>, <NUM> which include selector diodes may be referred to as having "asymmetric" selector devices.

More specifically, a diode has a low resistance in the forward direction and a high resistance in the opposite direction, commonly referred to as the "reverse" direction. Each of the selector diodes in the MRAM cells <NUM>, <NUM> are configurable such that the voltage thresholds can be independently selected for current traveling in the forward direction relative to the diode and for current traveling in the reverse direction relative to the diode. Thus, using selector diodes in lieu of selector switches enables the two-bit MRAM cells <NUM>, <NUM> to be more finely tuned in terms of controlling current flow by more specifically selecting the voltage thresholds of each of the selector diodes.

In accordance with some embodiments of the present invention, it is possible for each selector diode to have forward and reverse threshold voltages that are the same as those of the other selector diodes. In accordance with some embodiments of the present invention, it is possible for the selector diodes to have forward and reverse threshold voltages that are different than those of other selector diodes. In accordance with some embodiments of the present invention, it is possible for a selector diode to have a forward threshold voltage that is the same as its reverse threshold voltage. In accordance with some embodiments of the present invention, it is possible for a selector diode to have a forward threshold voltage that is different than its reverse threshold voltage.

As shown in <FIG>, the arrangement of the two-bit MRAM cells <NUM>, <NUM> is identical to that of two-bit MRAM cells <NUM>, <NUM> shown and described above except that the selector switches <NUM>, <NUM>, <NUM>, <NUM> are replaced by selector diodes <NUM>, <NUM>, <NUM>, <NUM>. In the embodiment shown in <FIG>, each of the selector diodes <NUM>, <NUM>, <NUM>, <NUM> is arranged such that the forward direction of the diode points toward the respective shared transistor <NUM>, <NUM>. In some alternative embodiments, it may be possible to arrange at least some of the selector diodes such that the forward direction points away from the respective shared transistor as long as the functionality of the selector diodes, to enable the two single-bit MRAM cells of a two-bit MRAM cell to share a common transistor, is preserved.

As shown in <FIG>, in operation, the primary path <NUM> of a read or write current intended to perform a read or write operation on the first single-bit MRAM cell <NUM> travels along the bit line <NUM>, through the first single-bit MRAM cell <NUM>, through the first selector diode <NUM> in the forward direction, and through the third transistor <NUM> to the source line <NUM>.

As shown in <FIG>, in operation, the secondary path <NUM> of a read or write current intended to perform a read or write operation on the first single-bit MRAM cell <NUM> travels along the bit line <NUM>, through the third single-bit MRAM cell <NUM>, through the third selector diode <NUM> in the forward direction, through the fourth selector diode <NUM> in the reverse direction, through the fourth single-bit MRAM cell <NUM>, along the second bit line <NUM>, through the second single-bit MRAM cell <NUM>, through the second selector diode <NUM> in the forward direction, and through the third transistor <NUM> to the source line <NUM>.

Accordingly, in order to allow the read or write current to travel along the intended primary path <NUM> while preventing the read or write current from traveling along the unintended secondary path <NUM>, the relative threshold voltages can be selected in the following manner. The forward threshold voltage Vdf for each of the selector diodes is less than the voltage of the read current (Vr) and the voltage of the write current (Vw) such that the read and write currents are able to pass through the first selector diode <NUM> in primary path <NUM>. The sum of the forward threshold voltage Vdf of the third selector diode <NUM>, the reverse threshold voltage Vdr of the fourth selector diode <NUM>, and the forward threshold voltage Vdf of the fourth selector diode <NUM> is greater than each of the read and write currents. In other words, Vdf < Vr < Vw < (2Vdf + Vdr).

In one illustrative example, the forward threshold voltage Vdf to activate each of the selector diodes in the forward direction can be approximately <NUM> millivolts, the reverse threshold voltage Vdr to activate each of the selector diodes in the reverse direction can be approximately <NUM> millivolts, the voltage of the read current Vr can be approximately <NUM> millivolts, and the voltage of the write current Vw can be approximately <NUM> millivolts. This example satisfies the conditions Vdf < Vr < Vw < (2Vdf + Vdr) because <NUM> < <NUM> < <NUM> < <NUM>. In alternative embodiments, it is possible for the components to have different voltages so long as the conditions Vdf < Vr < Vw < (2Vdf + Vdr) remain satisfied. In at least one alternative embodiment, it is possible for the reverse threshold voltage Vdr to be significantly larger than the forward threshold voltage Vdf such that a read or write voltage would not be able to pass through a single diode oriented in the reverse direction.

<FIG> depicts a top plan view of the two-bit MRAM cells <NUM>, <NUM> (which could be <NUM>, <NUM> instead) as well as two further two-bit MRAM cells <NUM>, <NUM> in an array. In the manner described above, the first single-bit MRAM cell <NUM> and the second single-bit MRAM cell <NUM> share the common bottom contact <NUM>. The first single-bit MRAM cell <NUM> and the second single-bit MRAM cell <NUM> further share the third transistor, which is not visible in <FIG> because it is obscured by the bottom contact <NUM>. Additionally, the first single-bit MRAM cell <NUM> and the third single-bit MRAM cell <NUM> are both connected to the first bit line <NUM>, and the second single-bit MRAM cell <NUM> and the fourth single-bit MRAM cell <NUM> are both connected to the second bit line <NUM>. The further two-bit MRAM cells <NUM>, <NUM> are arranged and connected and function in substantially the same manner. For example, first and second single-bit MRAM cells of each of the two-bit MRAM cells <NUM>, <NUM> share bottom contacts and first and third single-bit MRAM cells are connected to a first bit line <NUM> and second and fourth single-bit MRAM cells are connected to a second bit line <NUM>. This arrangement can be formed by, for example, the method <NUM> shown in <FIG>.

<FIG> depicts an example method <NUM> for forming the above described arrangement, which can be used in a memory storage device. The method <NUM> begins at operation <NUM>, wherein the shared bottom contact, also referred to as a shared landing pad, is formed. In the context of the MRAM cell <NUM> shown in <FIG>, the shared landing pad is analogous to the shared bottom contact <NUM>. In particular, the shared landing pad is formed of a conductive material, for example, a metal such as ruthenium.

<FIG> depicts a schematic drawing of a partial side cross-sectional view of a memory storage device <NUM> following the performance of operation <NUM>. As shown, in at least some embodiments of the present invention, the shared landing pad <NUM> can be formed at the same time, as part of the same process, and/or of the same material as a metal line <NUM> in a logic area <NUM> of the memory storage device <NUM>. Moreover, in at least some embodiments of the present invention, the shared landing pad <NUM> of a memory area <NUM> and the metal line <NUM> of the logic area <NUM> are formed on an oxide layer <NUM>. Furthermore, the shared landing pad <NUM> is formed in direct contact with a contact <NUM> that is formed in, and otherwise isolated by, the oxide layer <NUM>. In the context of the MRAM cell <NUM> shown in <FIG>, this contact <NUM> is analogous to the contact which connects the shared bottom contact <NUM> with the third transistor <NUM>.

Additionally, <FIG> illustrates an interlayer dielectric (ILD) <NUM>, which can be used to separate the shared landing pad <NUM> from the metal line <NUM> and from shared landing pads of other MRAM cells in the array. In at least some embodiments of the present invention, the ILD can be formed of, for example, an ultra-low dielectric constant (ULK) material.

Additionally, <FIG> illustrates a mask <NUM> selectively formed on top of portions of the metal line <NUM> and shared landing pad <NUM>. As described in further detail below, the mask <NUM> facilitates subsequent operations in the fabrication process.

<FIG> depicts a schematic drawing of a partial top view of the memory area <NUM> of the memory storage device <NUM> shown in <FIG>. For illustrative purposes, the memory area <NUM> includes four two-bit MRAM cells <NUM> formed in the manner shown in <FIG> and by the operation <NUM> of method <NUM>.

<FIG>, and <FIG> illustrate the memory storage device <NUM> following the performance of further fabrication processes which form the shared bottom contact <NUM>. In other words, the further fabrication processes (the results of which are shown in <FIG>, and <FIG>) can be considered to be performed in the performance of operation <NUM> of method <NUM>. The fabrication operations shown in <FIG> can be performed using fabrication processes (e.g., ILD fill, CMP) that are known to those of ordinary skill in the art. In particular, <FIG> illustrates the result of forming the top via by etching the metal line <NUM> and the shared landing pad <NUM> using mask <NUM> and then performing an ILD fill process and a subsequent CMP process. The ILD fill process can be performed using the same material or a different material as the preexisting ILD <NUM>. <FIG> illustrates the result of forming an ILD recess <NUM> and a microstud <NUM> self-aligned with the shared landing pad <NUM>. <FIG> illustrates the result of performing a cap dielectric fill process and a subsequent CMP process. The cap dielectric fill process can be performed using a flowable dielectric material <NUM> such as, for example, SiCN(H).

Returning to <FIG>, the method <NUM> proceeds with operation <NUM>, wherein the first and second single-bit MRAM cells are formed on the shared bottom contact <NUM>. The MRAM cells may be formed using fabrication processes (e.g., deposition processes) that are known in the art. In at least some embodiments of the present invention, operation <NUM> can include depositing the layers of the MRAM cells by performing litho patterning and/or masking processes. More specifically, as illustrated by <FIG>, the performance of operation <NUM> can include the sequential formation of layers of material which form the selector devices, the bottom electrodes, the MTJs, and the top electrodes of the MRAM cells. In other words, in at least some embodiments of the present invention, forming the MRAM cells at operation <NUM> includes forming the selector devices that correspond to those MRAM cells. In such embodiments, forming the selector devices can include patterning a selector device material, for example, by performing an etch process. Furthermore, in such embodiments, the selector device material can include, for example, at least one of SiOx, TiOx, AlOx, WOx, TiNOx, HfOx, TaOx, and NbOx.

In the embodiment shown in <FIG>, the layer(s) of material(s) which form(s) the selector devices is/are indicated with reference numeral <NUM>, the layer(s) of material(s) which form(s) the bottom electrodes is/are indicated with reference numeral <NUM>, the layer(s) of material(s) which form(s) the MTJs is/are indicated with reference numeral <NUM>, the layer(s) of material(s) which form(s) the top electrodes are indicated with reference numeral <NUM>.

<FIG> further illustrates that the performance of operation <NUM> can include the formation of an oxide layer <NUM>, an OPL layer <NUM>, and a SiARC layer <NUM> on top of the top electrode. In at least some embodiments of the present invention, each of the top electrode and the bottom electrode can be formed of, for example, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, or Al.

In the embodiments shown in <FIG>, the layer(s) of material(s) <NUM> which form(s) the selector devices is/are formed between the shared bottom contact <NUM> and the layer(s) of material(s) <NUM> which form(s) the bottom electrodes of the MRAM cells. This arrangement illustrates one example embodiment of the present invention. Alternatively, in embodiments of the present invention wherein the selector devices are arranged in locations other than between the shared bottom contact <NUM> and the layer(s) of material(s) <NUM> which form(s) the bottom electrodes, the layer(s) of material(s) <NUM> which form(s) the selector devices is/are formed and arranged in a different order than is illustrated by <FIG>.

Returning to <FIG>, at operation <NUM>, metal lines are formed which connect the MRAM cells in an array in the memory area of the memory storage device and connect the memory area to the logic area of the memory storage device. The metal lines can include, for example, a first metal line which connects the first top electrode with a first transistor and a second metal line which connects the second top electrode with a second transistor. More specifically, the first metal line can be a first bit line (such as first bit line <NUM>) which connects the first MRAM cell (such as first single-bit MRAM cell <NUM>) with a first transistor (such as first transistor <NUM>) which is located in the logic area <NUM> of the memory storage device <NUM>. Similarly, the second metal line can be a second bit line (such as second bit line <NUM>) which connects the second MRAM cell (such as second single-bit MRAM cell <NUM>) with a second transistor (such as second transistor <NUM>) which is located in the logic area <NUM> of the memory storage device <NUM>.

Fabrication processes for forming the metal lines which connect the MRAM cells are known in the art. In at least some embodiments of the present invention, operation <NUM> can include performing a top electrode or hardmask etch procedure (the result of which is illustrated by <FIG>) using RIE or IBE, performing an IBE procedure (the result of which is illustrated by <FIG>), performing a dielectric encapsulation procedure (the result of which is illustrated by <FIG>), performing an encapsulation etch back procedure (the result of which is illustrated by <FIG>), performing an ILD deposition procedure (the result of which is illustrated by <FIG>), and forming the top electrode contacts <NUM> (the result of which is illustrated by <FIG>).

In at least one embodiment of the present invention, the dielectric encapsulation procedure can be performed using a dielectric material <NUM> such as, for example, SiN, SiCN(H), or another similar material. Such material is selected on the basis of its ability to provide a good hermetic seal which protects MRAM cells from exposure to ambient oxygen, moisture, and other chemicals from subsequent process steps. In at least one embodiment of the present invention, the ILD deposition procedure can be performed using the same material <NUM> as for the ILD <NUM>. In alternative embodiments, a different material can be used. In at least one embodiment of the present invention, the top electrode contacts <NUM> can be formed by performing a dual damascene procedure.

The procedures listed above provide an example of fabrication processes which may be used to form the metal lines in operation <NUM>. In alternative embodiments of the present invention, the results of the procedures listed above, which are illustrated in <FIG>, can be achieved by the performance of other known procedures.

Referring now to <FIG>, shown is a high-level block diagram of an example computer system <NUM> that may be used in implementing one or more of the methods, tools, and modules, and any related functions, described herein (e.g., using one or more processor circuits or computer processors of the computer), in accordance with embodiments of the present invention. In some embodiments, the major components of the computer system <NUM> may comprise one or more CPUs <NUM>, a memory subsystem <NUM>, a terminal interface <NUM>, a storage interface <NUM>, an I/O (Input/Output) device interface <NUM>, and a network interface <NUM>, all of which may be communicatively coupled, directly or indirectly, for inter-component communication via a memory bus <NUM>, an I/O bus <NUM>, and an I/O bus interface unit <NUM>.

The computer system <NUM> may contain one or more general-purpose programmable central processing units (CPUs) 1302A, 1302B, 1302C, and 1302D, herein generically referred to as the CPU <NUM>. In some embodiments, the computer system <NUM> may contain multiple processors typical of a relatively large system; however, in other embodiments the computer system <NUM> may alternatively be a single CPU system. Each CPU <NUM> may execute instructions stored in the memory subsystem <NUM> and may include one or more levels of on-board cache.

System memory <NUM> may include computer system readable media in the form of volatile memory, such as random access memory (RAM) <NUM> or cache memory <NUM>. Computer system <NUM> may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system <NUM> can be provided for reading from and writing to a non-removable, non-volatile magnetic media, such as a "hard drive. " Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), or an optical disk drive for reading from or writing to a removable, non-volatile optical disc such as a CD-ROM, DVD-ROM or other optical media can be provided. In addition, memory <NUM> can include flash memory, e.g., a flash memory stick drive or a flash drive. Memory devices can be connected to memory bus <NUM> by one or more data media interfaces. The memory <NUM> may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of various embodiments.

One or more programs/utilities <NUM>, each having at least one set of program modules <NUM> may be stored in memory <NUM>. The programs/utilities <NUM> may include a hypervisor (also referred to as a virtual machine monitor), one or more operating systems, one or more application programs, other program modules, and program data. Each of the operating systems, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules <NUM> generally perform the functions or methodologies of various embodiments.

Although the memory bus <NUM> is shown in <FIG> as a single bus structure providing a direct communication path among the CPUs <NUM>, the memory subsystem <NUM>, and the I/O bus interface <NUM>, the memory bus <NUM> may, in some embodiments, include multiple different buses or communication paths, which may be arranged in any of various forms, such as point-to-point links in hierarchical, star or web configurations, multiple hierarchical buses, parallel and redundant paths, or any other appropriate type of configuration. Furthermore, while the I/O bus interface <NUM> and the I/O bus <NUM> are shown as single respective units, the computer system <NUM> may, in some embodiments, contain multiple I/O bus interface units <NUM>, multiple I/O buses <NUM>, or both. Further, while multiple I/O interface units are shown, which separate the I/O bus <NUM> from various communications paths running to the various I/O devices, in other embodiments some or all of the I/O devices may be connected directly to one or more system I/O buses.

In some embodiments, the computer system <NUM> may be a multi-user mainframe computer system, a single-user system, or a server computer or similar device that has little or no direct user interface, but receives requests from other computer systems (clients). Further, in some embodiments, the computer system <NUM> may be implemented as a desktop computer, portable computer, laptop or notebook computer, tablet computer, pocket computer, telephone, smart phone, network switches or routers, or any other appropriate type of electronic device.

It is noted that <FIG> is intended to depict the representative major components of an exemplary computer system <NUM>. In some embodiments, however, individual components may have greater or lesser complexity than as represented in <FIG>, components other than or in addition to those shown in <FIG> may be present, and the number, type, and configuration of such components may vary. Furthermore, the modules are listed and described illustratively according to an embodiment and are not meant to indicate necessity of a particular module or exclusivity of other potential modules (or functions/purposes as applied to a specific module).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments. It will be further understood that the terms "includes" and/or "including," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In the previous detailed description of example embodiments of the various embodiments, reference was made to the accompanying drawings (where like numbers represent like elements), which form a part hereof, and in which is shown by way of illustration specific example embodiments in which the various embodiments may be practiced. These embodiments were described in sufficient detail to enable those skilled in the art to practice the embodiments, but other embodiments may be used and logical, mechanical, electrical, and other changes may be made without departing from the scope of the various embodiments. In the previous description, numerous specific details were set forth to provide a thorough understanding the various embodiments. But, the various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure embodiments.

As used herein, "a number of' when used with reference to items, means one or more items. For example, "a number of different types of networks" is one or more different types of networks.

When different reference numbers comprise a common number followed by differing letters (e.g., 100a, 100b, 100c) or punctuation followed by differing numbers (e.g., <NUM>-<NUM>, <NUM>-<NUM>, or <NUM>, <NUM>), use of the reference character only without the letter or following numbers (e.g., <NUM>) may refer to the group of elements as a whole, any subset of the group, or an example specimen of the group.

Further, the phrase "at least one of," when used with a list of items, means different combinations of one or more of the listed items can be used, and only one of each item in the list may be needed. In other words, "at least one of" means any combination of items and number of items may be used from the list, but not all of the items in the list are required. The item can be a particular object, a thing, or a category.

Claim 1:
A magnetoresistive random-access memory, MRAM (<NUM>) device, the MRAM device comprising:
a first cell (<NUM>) connected to a first bit line (<NUM>);
a second cell(<NUM>) connected to a second bit line (<NUM>);
a shared transistor (<NUM>) connected to the first cell and connected to the second cell;
a first selector device (<NUM>) corresponding to the first cell, the first selector device configured to permit current to flow through the first cell to the shared transistor when a first voltage applied to the first selector device is larger than a threshold activation voltage;
a second selector device (<NUM>) corresponding to the second cell, the second selector device configured to permit current to flow through the second cell to the shared transistor when a second voltage applied to the second selector device is larger than the threshold activation voltage;
a word line (<NUM>) connected to a gate of the shared transistor;
a first transistor (<NUM>) connected to and associated with the first cell by way of the first bit line;
a second transistor (<NUM>) connected to and associated with the second cell by way of the second bit line;
wherein the first cell comprises a first magnetic tunnel junction, MTJ (<NUM>), arranged between a first top electrode (<NUM>) and a first bottom electrode (<NUM>);
the first MTJ comprising a first reference layer (<NUM>), a first tunnel barrier layer (<NUM>), and a first free layer (<NUM>);
wherein the second cell includes a second magnetic tunnel junction, MTJ (<NUM>), arranged between a second top electrode (<NUM>) and a second bottom electrode (<NUM>);
the second MTJ comprising a second reference layer (<NUM>), a second tunnel barrier layer (<NUM>), and a second free layer (<NUM>); and wherein both bottom electrodes (<NUM>) are connected to a shared landing pad (<NUM>); and
at least one of the first selector device and the second selector device is arranged between the reference layer and the bottom electrode of the corresponding cell.