Patent Description:
As computer technology advances, more servers are being designed with multiple processors. These multiple processors are adapted on a single main circuit board, called a motherboard or baseboard. To enable high-speed communication between these processors, routing layers with processor-to-processor interconnects are provided within this baseboard. However, with increasing core counts and increasing memory requirements, processor-to-processor communication consumes an increasingly high number of socket pins, which are the interconnections that connect a processor socket to the baseboard, and which are adapted within a so-called keep-out zone.

As technology advances with ever-increasing core counts and memory requirements, greater numbers of these space-constrained socket pins are required for enabling multi-socket communication. As such, baseboards are designed with increasingly expensive materials and greater numbers of layers, which further complicate design including routing issues, and increase costs and power consumption.

<CIT> describes a board attached to substrate of a semiconductor chip package. <CIT> describes a plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above a printed circuit board. <CIT> describes a connector comprising a plurality of signal paths for routing signals from the first and second CPU packages.

In various embodiments, a multi-processor computing system such as a server computer may include an auxiliary circuit board to directly couple at least two processors of the multi-processor computing system. With embodiments, these processors communicate without use of interconnects of one or more layers of a main circuit board such as a baseboard, motherboard or so forth to which the processors are adapted. In this way, processor-to-processor communication may occur exclusively via this auxiliary circuit board. Thus fewer socket pins, solder balls or other interconnection members within a pin field of the processors are consumed. Instead, the multiple processors may have edge connection members to which the auxiliary circuit board may be adapted.

As a result, fewer signals pass through processor sockets, reducing the number of required socket pins, solder balls or other connection members located within a keep-out zone of a processor package. In addition, by moving high-speed processor-to-processor signaling onto a separate smaller auxiliary circuit board, the main baseboard is not burdened with the cost of ultra-low loss circuit board materials. And with an auxiliary circuit board as described herein, airflow in a manufactured system is not blocked by other interconnection members that would be required in other systems, such as thick cabling to couple between accelerator cards and the baseboard. Still further, by separating out processor-to-processor signaling onto this auxiliary circuit board, crosstalk between such signaling and other board components such as voltage regulators is reduced or completely avoided.

Referring now to <FIG>, shown is a block diagram of an auxiliary circuit board in accordance with an embodiment of the present invention. As shown in <FIG>, circuit board <NUM> may provide a high-speed link between multiple processors within a multi-processor computing system. As illustrated in <FIG>, circuit board <NUM> includes multiple connectors <NUM><NUM>,<NUM>, each adapted at a corresponding peripheral portion of circuit board <NUM>. As high-speed signaling is to occur between the processors via circuit board <NUM>, the circuit board may be formed of an ultra-low loss material, to improve signaling speeds. In the embodiment of <FIG>, note that there are no locations on circuit board <NUM> to which an integrated circuit may be adapted (such as by socket pins, solder balls or so forth). Instead circuit board <NUM> can only couple to processors via connectors <NUM>.

Circuit board <NUM>, which in different embodiments may be a multi-layer circuit board having between approximately <NUM> and <NUM> layers, can be formed of a printed circuit board (PCB) material having ultra-low loss properties similar to EM-<NUM>, IT-<NUM>, TU-<NUM>, TU-<NUM>+, MEG6, MEG7, etc. In embodiments, ultra-low loss materials may have a dielectric constant (Er) of approximately <NUM> and a dissipation factor (Df) of approximately <NUM> (at <NUM> gigahertz (GHz)). In contrast, a baseboard of a server system may be formed of a lower cost, lower speed material such as a glass-reinforced epoxy laminate material (e.g., FR-<NUM>) or the like. As a result, a manufacturer such as OEM may realize significantly reduced manufacturing costs by leveraging an auxiliary board to route high-speed inter-processor signaling. Of course, in other cases similar performance may be realizing using low loss materials (having higher dielectric constant and dissipation factor) and shorter traces. More generally in embodiments, an auxiliary circuit board may have more aggressive/higher cost loss mitigation techniques as compared to the larger/cheaper baseboard. Thus the main and much larger baseboard can be formed of a lower cost material.

In addition, by providing an auxiliary circuit board, the main baseboard can be formed with fewer layers, e.g., between approximately <NUM> and <NUM> layers, and which can be formed of a PCB material having higher loss properties similar to FR-<NUM>, 370HR, etc. In an embodiments, such materials may have a dielectric constant of approximately <NUM> and a dissipation factor of approximately <NUM> (at <NUM> gigahertz (GHz)). In contrast, without an embodiment the baseboard may require at least <NUM>-<NUM> additional layers, and further require manufacture with a higher cost material. While the above discussion assumes particular classes of materials for the different circuit boards.

To enable processors to couple to auxiliary board <NUM> without consuming socket pins, solder balls or so forth, processors in accordance with an embodiment may have packages that include edge connectors, in addition to such socket pins, solder balls or other interconnection members. In turn, these edge connectors or contact members provide coupling to corresponding connectors <NUM> of circuit board <NUM>. Referring now to <FIG>, shown is a block diagram of a processor package in accordance with an embodiment of the present invention. As shown in <FIG>, processor package <NUM> may be implemented as an integrated circuit package including one or more semiconductor die coupled to a package substrate. As illustrated in <FIG>, at a first edge portion <NUM> of package <NUM>, an edge connector <NUM> is formed directly on a substrate of package <NUM>.

In the embodiment shown in <FIG>, note that edge connector <NUM> may be formed as a stepped connector including two levels of finger contacts. In an embodiment these fingers may be implemented as gold-plated fingers to provide interconnection to internal routing lines of the one or more semiconductor die. Although shown with two levels of contacts in the embodiment of <FIG>, understand that in other embodiments a single level or more than two levels may be provided. Further, while <FIG> shows an embodiment having a single edge connector per processor package, understand that the scope of the present invention is not limited in this regard and in other cases, separate edge connectors may be provided on opposite sides of a package (and it is even possible to provide edge connectors on all sides of a package, in still further embodiments). The number of individual finger contacts of these edge connectors may vary in different embodiments. In typical use cases, between approximately <NUM>-<NUM> contacts may be provided.

Referring now to <FIG>, shown is a cross-sectional view of mating between a processor package and an edge connector of an auxiliary circuit board in accordance with an embodiment of the present invention. As shown in <FIG>, a processor has an edge contact member <NUM>, which more specifically is shown in the cross-section of <FIG> as fingers <NUM>, <NUM> of a first level and fingers <NUM>, <NUM> of a second level. In turn, when adapted within an edge connector <NUM> of an auxiliary circuit board, contact is made between these corresponding fingers and corresponding connector pins of a stepped pin assembly including pins <NUM>, <NUM> of a first level of connector pins and pins <NUM>, <NUM> of a second level of connector pins. Although shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible, and other connection mechanisms for interconnecting a processor package directly to an auxiliary circuit board without consuming socket pins, solder balls or so forth may be used.

Referring now to <FIG>, shown is a block diagram illustrating a server computer providing for interconnection of multiple processor sockets with an auxiliary circuit board in accordance with an embodiment. As shown in <FIG>, a server computer <NUM> includes a baseboard <NUM> to which multiple processor packages <NUM><NUM>,<NUM> are adapted. In different implementations, processor packages <NUM> may be implemented within sockets having socket pins that are connected to baseboard <NUM>. In another implementation, processor packages <NUM> may be adapted as a ball grid array package having solder balls that in turn connect to solder bumps on baseboard <NUM>.

In any case note that processor-to-processor communication is solely via an auxiliary circuit board <NUM> that directly couples processor packages <NUM> together. In different embodiments, such processor-to-processor communication may be according to a variety of different communication protocols. For example, some embodiments may be implemented by way of one or more of an Intel® Ultra Path Interconnect (UPI) communication protocol, an Intel® Quick Path Interconnect (QPI) communication protocol, and/or a given Compute Express Link (CXL) specification-based communication protocol such as in accordance with the CXL Specification version <NUM>. In yet other embodiments, processor-to-processor communication may be accordance with an IBM XBus protocol, or an Nvidia NVLink protocol, an AMD Infinity Fabric protocol, among many other such communication protocols.

As further illustrated in <FIG>, a plurality of memory modules <NUM>, which may be implemented as dual in-line memory modules (DIMMs), couple between and outwardly from processors <NUM>. With the implementation shown in <FIG>, processor-to-processor communication is not passed through socket pins or solder balls, reducing pin/ball count. In addition, such signaling is not exposed to crosstalk, e.g., from one or more voltage regulators adapted to baseboard <NUM>. Furthermore, a thinner baseboard may be realized, as fewer layers may be required, given this baseboard-external routing of processor-to-processor signaling.

In addition with adaptation of auxiliary circuit board <NUM>, system airflow is not blocked (as auxiliary circuit board <NUM> may be adapted horizontally (and parallel to baseboard <NUM>)). Thus airflow passing through system (such as in a vertical direction in the illustration of <FIG>) may flow directly across heatsinks adapted to processors <NUM> and not be blocked by auxiliary circuit board <NUM>. In addition, a variety of system cards may be adapted above and around auxiliary circuit board <NUM> in an unrestricted manner.

Although shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible. For example, while <FIG> shows an implementation in which processors <NUM> are adapted adjacent to each other in a width direction (in the illustration of <FIG>), it is also possible that processors <NUM> may be adapted adjacent each other in a length direction (in the illustration of <FIG>), such that an auxiliary circuit board may be formed as a substantially rectangular board to enable direct interconnection between multiple processors located one in front of the other. Such arrangement stands in contrast to the arrangement of circuit board <NUM> as a partial frame configuration (having two vertical portions and a single horizontal portion (as illustrated in <FIG>)). And of course other configurations and positioning of processors and corresponding auxiliary circuit boards are possible.

Still further, while the above embodiments describe an auxiliary circuit board to which no integrated circuits are adapted by way of pins, solder balls or another surface mount technology or board-based connectors (other than the edge connectors described above), in other cases, an auxiliary circuit board may also be used to attach devices such as accelerators and peripheral devices directly or via connectors to which cables can be attached. In such cases, the auxiliary circuit board may include interconnects sufficient to enable at least one Peripheral Component Interconnect Express (PCIe) interface, which may consume <NUM> interconnects/contacts. Where it is desired to provide for multiple PCIe interfaces, some multiple of <NUM> contacts may be provided by way of one or more edge connectors of a processor. And of course, other high speed links such as Intel® UPI and/or QPI links, CXL links, NVLinks and so forth.

Referring now to <FIG>, shown is a block diagram of a server computing system having an auxiliary circuit board in accordance with another embodiment of the present invention. As shown in <FIG>, server system <NUM> includes a baseboard <NUM>, processors <NUM><NUM>,<NUM>, an auxiliary circuit board <NUM>, and memory <NUM>. In the embodiment of <FIG>, auxiliary circuit board <NUM> may be larger than the above-described auxiliary circuit boards and may provide for multiple interconnection members to which I/O devices can be coupled to, e.g., by way of one or more connectors <NUM>. These I/O devices may take the form of add-in cards, such as accelerators, additional memory so forth. In addition, while card connectors are shown in the implementation of <FIG>, it is also possible to provide cable-based connectors, to enable coupling of other devices such as a graphics accelerator card or so forth by way of cable connection. In an example embodiment, assume that auxiliary circuit board <NUM> includes <NUM> sets of links per CPU (e.g., where each link includes <NUM> signal lines), one or more of these links may be used by one or more devices that couple to auxiliary circuit board <NUM> by way of connectors <NUM>.

With an embodiment as in <FIG>, further reductions in numbers of signals that extend through processor packages <NUM> (and any socket) through baseboard <NUM> may be realized, increasing advantages in such embodiments. In addition, with auxiliary circuit board <NUM> providing additional connectors as in <FIG>, greater OEM flexibility may be realized. That is, an OEM may design a single baseboard and provide multiple stock keeping units (SKUs) using this single baseboard. As an example for one SKU a basic auxiliary circuit board (as described above with regard to <FIG>) may be used, while for another SKU an auxiliary circuit board as in <FIG> may be used, to provide a server computer that enables inclusion of additional devices.

Referring now to <FIG>, shown is a block diagram of a multi-server computer system in accordance with an embodiment of the present invention. As shown in <FIG>, system <NUM> may be all or a portion of a system having at least two servers <NUM><NUM>,<NUM>, each adapted on a different baseboard <NUM><NUM>,<NUM>. As one example, system <NUM> maybe a rack-based server including many baseboards adapted in a frame such as a 42U height rack.

In any event, each server <NUM>, also referred to herein as a node, includes symmetric multi-processors, namely processors <NUM><NUM>,<NUM> and <NUM><NUM>,<NUM>, namely multicore processors. In some embodiments, all of these processors may be identical, or different processor types may be implemented in each server. To enable processor-to-processor communication internally to each server <NUM>, a set of interconnects <NUM> is provided to couple processors <NUM> and <NUM>. And in embodiments herein, understand that interconnects <NUM> may be implemented within an auxiliary circuit board as described herein, separate from baseboard <NUM>.

With further reference to the high level view shown in <FIG>, each server <NUM> further includes an I/O device <NUM><NUM>,<NUM>. Note that each I/O device <NUM> is directly coupled via another interconnect <NUM> to a corresponding local processor <NUM>. Thus the identification of processors as being local or remote is with respect to I/O device <NUM>, such that the processor to which it is directly coupled is the local processor, and the other symmetric processor is considered the remote processor. Although not shown for ease of illustration, understand that additional I/O devices or other components may be directly coupled to remote processor <NUM>.

In one embodiment, interconnects <NUM> may be implemented in an auxiliary circuit board (not shown in the logical view of <FIG>), and may carry processor-to-processor communication according to an Intel® UPI communication protocol, although other protocols are possible. In an embodiment, each interconnect <NUM> may be configured as an x16, x20 or x24 with ports that couple processors <NUM>, <NUM> together.

In an embodiment, interconnect <NUM> may carry communications according to a PCIe or other communication protocol. Understand that in some embodiments, an auxiliary circuit board (which includes interconnects <NUM>) may further include interconnects <NUM> in a manner separated from baseboard <NUM>. To this end, such auxiliary circuit board may take the form, e.g., as shown in <FIG>, such that I/O device <NUM> may be adapted within a connector of the auxiliary circuit board (or coupled by way of a cable connector), or otherwise directly coupled to the auxiliary circuit board.

Still referring to <FIG>, communication between servers <NUM> may be via a high speed fabric interconnect <NUM>. In different embodiments, interconnect <NUM> may be implemented using an InfiniBand or Ethernet-based protocol, and may be realized using Ethernet or optical cables that couple baseboards <NUM> together.

With the arrangement in <FIG>, remote processor <NUM><NUM> may communicate with remote processor <NUM><NUM> along a path including interconnects <NUM>, <NUM> and via I/O devices <NUM><NUM>,<NUM> and via interconnect <NUM>, and finally through interconnects <NUM>, <NUM> of baseboard <NUM><NUM> to remote processor <NUM><NUM>. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

<FIG> illustrates an example computing node arrangement <NUM>, according to various embodiments. The computing node <NUM> may include a manager <NUM> and one or more server nodes, such as server node <NUM> and server node <NUM>. The one or more server nodes may be communicatively coupled to the manager <NUM>, thereby allowing communication between the between the server nodes and the manager <NUM> (as illustrated by communication link <NUM> and communication link <NUM>). The manager <NUM> and each of the server nodes may be referred to as a computing node. The following description refers to the server node <NUM> and the server node <NUM>, however, it is to be understood that any of the server nodes within the one or more server nodes may include one or more of the feature of the server node <NUM>, the server node <NUM>, or some combination thereof.

The manager <NUM> may receive an operation <NUM> to be performed. The manager <NUM> may include one or more communication chips. The manager <NUM> may wirelessly receive or wiredly receive the operation <NUM> from a requesting device via the communication chips. The manager <NUM> may separate the operation <NUM> into one or more discrete operations and/or data groupings for storage.

The server node <NUM> may be a server rack. The server node <NUM> may include one or more drawers (which may also be referred to as sleds), such as drawer <NUM>, drawer <NUM>, drawer <NUM>, and drawer <NUM>. The server node <NUM> may be arranged in a pooled-by-node arrangement. In the pooled-by-node arrangement, each of the drawers of the server node <NUM> may include one or more components to provide a certain resource type. The resource types may include a network resource type, a storage resource type, and a compute resource type. For example, the drawer <NUM>, the drawer <NUM>, the drawer <NUM>, and the drawer <NUM> may each include components to provide a compute resource type.

In other embodiments, the server node <NUM> may be arranged in a pooled-by-drawer arrangement. In the pooled-by-drawer arrangement, each of the drawers may include one or more components to provide a certain resource type, but each of the drawers may include components to provide a different resource type than provided by the components within another one of the drawers of the server node <NUM>. For example, the drawer <NUM> may include components to provide a network resource type, the drawer <NUM> may include components to provide a storage resource type, and the drawer <NUM> may include components to provide a compute resource type.

Further, in other embodiments, the server node <NUM> may be arranged in a heterogeneous arrangement. In the heterogeneous arrangement, each of the drawers may include components to provide multiple resource types. Each of the drawers may include components to provide all the resource types or some portion of the resource types. For example, the drawer <NUM> may include components to provide a network resource type, components to provide a storage resource type, and components to provide a compute resource type.

In some embodiments, the server node <NUM> may be arranged in a combination of the pooled-by-drawer arrangement and the heterogeneous arrangement. In these embodiments, a first portion of the drawers of the server node <NUM> may be arranged in the pooled-by-drawer arrangement and a second portion of the drawers may be arranged in the heterogeneous arrangement.

The server node <NUM> may include one or more of the features of the server node <NUM>. The server node <NUM> may have a same arrangement as the server node <NUM> or may have a different arrangement than the server node <NUM>. For example, the server node <NUM> may be arranged in a pooled-by-node arrangement and the server node <NUM> may be arranged in a pooled-by-drawer arrangement. As stated above, the resource types may include the network resource type, the storage resource type, and the compute resource type. The network resource type may include one or more components that may provide networking capability. The storage resource type may include one or more components that may provide storage capability. The compute resource type may include one or more components that may provide computing capability.

In some embodiments, the resource types may include other resource types not described, but would be understood to be other resource types that may be provided by a server rack known to one having skill in the art. Further, in some embodiments, the resource types described may be divided into narrower resource types, where each of the narrower resource types may include some portion of the components described above in relation to the network resource type, the storage resource type, and the compute resource type.

After separating the operation <NUM> into one or more discrete operations and/or data groupings for storage, the manager <NUM> may direct each of the discrete operations and/or data groupings for storage to a corresponding drawer of the server node <NUM> and/or the server node <NUM> that provides the resource type to perform the discrete operation or store the data grouping. For example, the manager <NUM> may separate the operation <NUM> into a calculation operation and a group of data to be stored. The manager <NUM> may direct, via the communication link <NUM>, the calculation operation to the drawer <NUM> of the server node <NUM>, which may provide the compute resource type, and may direct, via the communication link <NUM>, the group of data to be stored to drawer <NUM> of the server node <NUM>, which may provide the storage resource type.

After directing the discrete operations and/or the data groupings for storage to the corresponding drawers, the manager <NUM> may retrieve the results of the discrete operations and/or the data groupings at a time when the results of the operation <NUM> are to be returned to the requesting device via the communication chips. The manager <NUM> may combine the results of the discrete operations and/or the data groupings to generate the results of the operation <NUM> and may return the results of the operation <NUM> to the requesting device via the communication chips.

In instances where the discrete operations are completed prior to the time when the results of the operation <NUM> are to be returned to the requesting device, the manager <NUM> may receive the results of the discrete operations and may direct the results of the discrete operations to a drawer providing the storage resource type for storage. The manager <NUM> may then retrieve the results of the discrete operations from the drawer providing the storage resource type at the time when the results of the operation <NUM> are to be returned to the requesting device.

In some embodiments, the manager <NUM> may be omitted from the computing node arrangement <NUM>. In these embodiments, one or more drawers of one of the server nodes may perform the operations of the manager <NUM>. For example, the drawer <NUM> of the server node <NUM> may perform the operations of the manager <NUM> and may direct the discrete operations and/or data groupings to other drawers within the server node <NUM> and/or within the server node <NUM>. Further, in these embodiments, the server node with the drawer that performs the operations of the manager <NUM> may be communicatively coupled to the other server nodes within the computing node arrangement <NUM> (as illustrated by communication link <NUM>).

One or more of the computing nodes within the computing node arrangement <NUM>, and/or the drawers within the computing nodes, may include, and/or may be, a computer device having multiple symmetric (or asymmetric) processors that are coupled together via one or more auxiliary circuit boards in accordance with an embodiment.

<FIG> illustrates an example computer device <NUM> that may employ the apparatuses and/or methods described herein, in accordance with various embodiments. As shown, computer device <NUM> may include a number of components, such as a plurality of processor and memory controller device(s) (hereafter CPUs) <NUM><NUM>,<NUM> and at least one communication chip <NUM>. In various embodiments, the CPUs <NUM> each may include one or more processor cores.

Further, in various embodiments, a system management device <NUM> (such as baseboard management controller (BMC)) may be coupled to the CPUs <NUM>. The system management device <NUM> may monitor the state of the computer device <NUM> via one or more sensors <NUM>. The one or more sensors <NUM> may sense the physical state of the computer device <NUM>, such as a temperature of the computer device <NUM>. In some embodiments, the system management device <NUM> may communicate with the CPUs <NUM> through an independent connection. Further, in some embodiments, the system management device <NUM> and/or the sensors <NUM> may be omitted.

In various embodiments, computer device <NUM> may include printed circuit board (PCB) <NUM>, which may be a baseboard. For these embodiments, the CPUs <NUM> (e.g., adapted in a socket <NUM><NUM>,<NUM>) and communication chip <NUM> may be disposed thereon. However, processor-to-processor signaling between CPUs <NUM> may occur via interconnects included in layers of auxiliary circuit board <NUM>. In alternate embodiments, the various components may be coupled without the employment of PCB <NUM>. Depending on its applications, computer device <NUM> may include other components that may or may not be physically and electrically coupled to the PCB <NUM>. These other components include, but are not limited to, main memory (e.g., volatile memory, non-volatile memory, and/or dynamic random access memory (DRAM) <NUM>), read-only memory (ROM) <NUM>, flash memory <NUM>, storage device <NUM> (e.g., a hard-disk drive (HDD)), an I/O controller <NUM>, a digital signal processor (not shown), a crypto processor (not shown), a system management device <NUM>, a display (not shown), a power conversion device <NUM>, an audio codec (not shown), a video codec (not shown), and a mass storage device (such as hard disk drive, a solid state drive, compact disk (CD), digital versatile disk (DVD)) (not shown), and so forth.

In various embodiments, the computer device <NUM> may include one or more fans <NUM>. The one or more fans <NUM> may be directed at and/or mounted to one or more of the components within the computer device <NUM>. In some embodiments, the one or more fans <NUM> may be coupled to the CPUs <NUM> and/or the system management device <NUM>, which may control operation of the one or more fans <NUM>.

In some embodiments, the CPUs <NUM>, flash memory <NUM>, and/or storage device <NUM> may include, stored in a non-transitory storage medium, associated firmware (not shown) storing programming instructions configured to enable computer device <NUM>, in response to execution of the programming instructions by one or more processor and memory controller device(s) <NUM>, to practice all or selected aspects of the methods described herein. In various embodiments, these aspects may additionally or alternatively be implemented using hardware separate from the one or more processor and memory controller device(s) <NUM>, flash memory <NUM>, or storage device <NUM>.

The communication chips <NUM> may enable wired and/or wireless communications for the transfer of data to and from the computer device <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to IEEE <NUM>, Long Term Evolution (LTE), LTE Advanced (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), Evolved High Speed Packet Access (HSPA+), Evolved High Speed Downlink Packet Access (HSDPA+), Evolved High Speed Uplink Packet Access (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The computer device <NUM> may include a plurality of communication chips <NUM>. For instance, a first communication chip <NUM> may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip <NUM> may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

In various implementations, the computer device <NUM> may be a server. In other implementations, the computer device <NUM> may be, or components of the computer device <NUM> may be implemented in, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a computer tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a printer, a scanner, a monitor, a set-top box, an entertainment control unit (e.g., a gaming console or automotive entertainment unit), a digital camera, an appliance, a portable music player, or a digital video recorder. In further implementations, the computer device <NUM> may be any other electronic device that processes data.

The following examples pertain to further embodiments.

In one example, an apparatus includes a circuit board comprising: a plurality of layers including interconnects to carry processor-to-processor signaling between a first processor and a second processor; a first connector adapted to a first peripheral portion of the circuit board to couple to a first contact member of the first processor and a second connector adapted to a second peripheral portion of the circuit board to couple to a first contact member of the second processor.

In an example, the interconnects of the circuit board are spatially separated from memory interconnects of a baseboard that couple between the first processor and a first portion of a system memory coupled to the first processor.

In an example, the circuit board is separate from the baseboard and is not adapted thereto.

In an example, the baseboard comprises at least one voltage regulator to power the first processor and the second processor, where the circuit board is to carry the processor-to-processor signaling without interference from the at least one voltage regulator.

In an example, the circuit board comprises an auxiliary circuit board.

In an example, the first contact member of the first processor comprises a stepped edge connector, and the first connector comprises a stepped pin assembly to mate with the stepped edge connector of the first processor.

In an example, the circuit board is formed of an ultra-low loss material.

In an example, the circuit board does not include keep-out zones for adaptation of integrated circuits.

In an example, the circuit board further comprises one or more additional connectors to mate with one or more accelerator devices, the circuit board comprising an auxiliary circuit board, where the first processor and the second processor are adapted to a baseboard.

In another example, an apparatus has a circuit board comprising: a plurality of layers including interconnects to carry processor-to-processor signaling between a first processor package and a second processor package; a first connector affixed to a first peripheral portion of the circuit board to mate with a first edge connector of the first processor package; and a second connector affixed to a second peripheral portion of the circuit board to mate with a first edge connector of the second processor package.

In an example, the circuit board comprises an auxiliary circuit board separate from a baseboard to which the first processor package and the second processor package are adapted, where the auxiliary circuit board is not adapted to the baseboard.

In an example, the auxiliary circuit board is formed of an ultra-low loss material and the baseboard is formed of an epoxy laminate material.

In an example, the circuit board does not include locations for adaption of integrated circuits.

In an example, the first edge connector of the first processor package comprises a stepped edge connector having at least two levels of contacts, and the first connector comprises a stepped pin assembly having at least two levels of contacts to mate with the stepped edge connector of the first processor package.

In a still further example, a system comprises: a first baseboard having a first processor package and a second processor package adapted thereto, the first baseboard further having a plurality of memory modules adapted thereto, where the first baseboard has one or more layers including first interconnects to carry processor-to-memory signaling between the first processor package and at least some of the plurality of memory modules and second interconnects to carry processor-to-memory signaling between the second processor package and at least some of the plurality of memory modules; and a first auxiliary board to carry processor-to processor signaling between the first processor package and the second processor package, where the first baseboard does not include interconnects to carry the processor-to-processor signaling between the first processor package and the second processor package.

In an example, the system comprises a symmetric multiprocessor server.

In an example, the first auxiliary board comprises a plurality of layers having second interconnects to carry the processor-to-processor signaling between the first processor package and the second processor package.

In an example, the plurality of layers further comprises third interconnects to carry signaling between at least one of the first processor package and the second processor package and a device adapted to the first auxiliary board.

In an example, the first baseboard further comprises a connector to provide interconnection between the first baseboard and a second baseboard having at least one other processor package.

In an example, the first processor package is to communicate with the second processor package via the first auxiliary circuit board and without use of socket pins or solder balls.

Understand that various combinations of the above examples are possible.

Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Claim 1:
A system comprising:
a first baseboard (<NUM>, <NUM>) having a first processor package (<NUM>, <NUM>) and a second processor package (<NUM>, <NUM>) respectively adapted thereto, the first baseboard (<NUM>, <NUM>) further having a plurality of memory modules (<NUM>, <NUM>) adapted thereto, wherein the first baseboard (<NUM>, <NUM>) has one or more layers including first interconnect means for carrying processor-to-memory signaling between the first processor package (<NUM>, <NUM>) and at least some of the plurality of memory modules (<NUM>, <NUM>) and second interconnect means for carrying processor-to-memory signaling between the second processor package (<NUM>, <NUM>) and at least some of the plurality of memory modules (<NUM>, <NUM>); and
a first auxiliary board (<NUM>, <NUM>) for carrying processor-to-processor signaling between the first processor package (<NUM>, <NUM>) and the second processor package (<NUM>, <NUM>) wherein the first auxiliary board (<NUM>, <NUM>) is directly coupled to the first processor package (<NUM>, <NUM>) and the second processor package (<NUM>, <NUM>), and wherein the first baseboard (<NUM>, <NUM>) does not include interconnect means for carrying the processor-to-processor signaling between the first processor package (<NUM>, <NUM>) and the second processor package (<NUM>, <NUM>).