Patent Description:
A power amplifier is an electronic device that can increase the power of a signal (a time-varying voltage or current). An RF amplifier amplifies a signal in the radio frequency range between <NUM> and <NUM>. High frequency RF power amplifiers require the device to be operated at high current density, biased at peak Gm (e.g., above <NUM>) or peak Fmax (e.g., ><NUM>). This, in turn, results in high heat generation and, in some instances, over-heating of the device/circuit. For example, the temperature rise of the power amplifier due to heat generated during circuit operations can degrade the power amplifier performance and can even impact circuitry at the proximity of the heat source. <CIT> discloses a structure, known from the prior art, comprising a substrate having an active layer overlying a buried insulator layer that in turn overlies a handle layer.

The subject-matter of the present invention is defined in claims <NUM>, <NUM> and <NUM>. In an aspect of the disclosure, a structure comprises: a semiconductor on insulator substrate; an insulator layer under the semiconductor on insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode partially in the first well. Additional features of the structure are set forth in dependent claims <NUM> to <NUM>.

In an aspect of the disclosure, a structure comprises: a heat generating device on a fully depleted semiconductor on insulator (FDSOI) substrate; a back-gate diode at least in a first well under the FDSOI substrate; and temperature sensing circuitry coupled to the back-gate diode configured to determine a temperature of the heat generating device. Additional features of the structure are set forth in dependent claims <NUM> to <NUM>.

In an aspect of the disclosure, a method comprises: establishing a temperature of a heat generating device in an off state; biasing a back-gate diode by applying a voltage to a well under the heat generating device; detecting a current at the back-gate diode during the biasing; and converting the current to a temperature reading of the heat generating device.

The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. In embodiments, the built-in temperature sensors may be provided in RF/mmW power amplifiers. The RF/mmW power amplifiers may be provided in fully-depleted semiconductor-on-insulator (FDSOI) technologies. For example, the built-in temperature sensors may include a back-gate diode or bipolar junction transistor (BJT) sensor in FDSOI. Advantageously, the built-in temperature sensors can provide in situ temperature monitoring at low cost, e.g., no additional masks needed, with little to no impact on device design.

In embodiments, the built-in temperature sensors monitor the temperature changes at the device level in order to characterize the heating behavior of a power amplifier. The built-in temperature sensors may be used in conjunction with additional temperature detection circuitry for sensing the temperature during circuit operation. The built-in temperature sensors may be, for example, a diode coupled to a biasing/sensing circuitry. In more specific embodiments, the built-in temperature sensors may be a diode formed in a substrate of a BJT, to in situ monitor the device temperature during device operations without impact on the device operation especially for RF performance.

The built-in temperature sensors of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the built-in temperature sensors of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the built-in temperature sensors uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material lines as is known in the art.

<FIG> shows a built-in temperature sensor and respective fabrication processes in accordance with aspects of the present disclosure. More specifically, the structure <NUM> of <FIG> includes substrate <NUM>. The substrate <NUM> may be a semiconductor-on-insulator (SOI) substrate. For example, the semiconductor-on-insulator (SOI) substrate <NUM> includes a handle substrate 12a composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. In embodiments, the handle substrate 12a may be a p-type substrate. An insulator layer 12b may be over the handle substrate <NUM>. The insulator layer 12b comprises any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and/or combinations thereof. An exemplary insulator layer 12b may be a buried oxide layer (BOX). A semiconductor substrate 12c may be provided over the insulator layer 12b. The semiconductor substrate 12c may be a fully depleted silicon-on-insulator (FDSOI) substrate, as an example. The handle substrate 12a provides mechanical support to the insulator layer 12b and the semiconductor substrate 12c.

An N-well <NUM> (e.g., back-gate well) and P-well <NUM> may be provided in the handle substrate 12a. The N-well <NUM> and P-well <NUM> may be formed by separate ion implantation processes as is known in the art. For example, the N-well <NUM> may be formed by introducing a concentration of an N-type dopant in the handle substrate 12a; whereas the P-well <NUM> may be formed by introducing a concentration of a P-type dopant in the handle substrate 12a. For example, the N-well <NUM> may be doped with n-type dopants, e.g., Arsenic (As), Phosphorus (P) and Antimony (Sb), among other suitable examples. In embodiments, the P-well <NUM> may be doped with p-type dopants, e.g., Boron (B).

In both implantation processes, a patterned implantation mask may be used to define selected areas exposed for the implantation. The implantation mask may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. An annealing process may be performed to drive in the dopant into the handle substrate 12a, e.g., into the wells <NUM>, <NUM>.

Still referring to <FIG>, shallow trench isolation structures <NUM> may be provided within the handle substrate 12a to separate or isolate the P-well <NUM> from the N-well <NUM>, and the N-well <NUM> from a device <NUM> (e.g., a transistor or other heat generating device, e.g., for a power amplifier). The shallow trench isolation structures <NUM> may extend partially through the N-well <NUM>, thereby resulting in a PN junction <NUM> between the P-well <NUM> and the N-well <NUM>. This configuration will effectively form a back-gate diode <NUM> within the handle substrate 12a at the PN junction <NUM>.

The shallow trench isolation structures <NUM> can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the handle substrate 12a is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern to the handle substrate 12a, forming one or more trenches in the handle substrate 12a. Following the resist removal by a conventional oxygen ashing process or other known stripants, insulator material (e.g., SiO<NUM>) material can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the handle substrate 12a can be removed by conventional chemical mechanical polishing (CMP) processes.

The device <NUM>, e.g., gate structure or other heat generating device of a power amplifier, may be formed on the semiconductor substrate 12c (e.g., FDSOI). In embodiments, the device <NUM> may be a BJT. In embodiments, the device <NUM> may comprise a polysilicon gate body 20a with adjacent source/drain regions 20b. The device <NUM>, e.g., gate structure, may include sidewall spacers which isolate the gate body 20a from the source/drain regions 20b. The gate structure <NUM> further includes a gate dielectric material, e.g., high-k or low-k dielectric material. The high-k gate dielectric material can be, e.g., HfO<NUM> Al<NUM>O<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, La<NUM>O<NUM>, SrTiO<NUM>, LaAlO<NUM>, ZrO<NUM>, Y<NUM>O<NUM>, Gd<NUM>O<NUM>, and combinations including multilayers thereof.

The source/drain regions 20b may be raised source/drain regions 20b fabricated using, for example, conventional epitaxial growth processes with an in-situ dopant, e.g., n-type dopant. In accordance with exemplary embodiments, epitaxy regions (e.g., raised source/drain regions 20b) may include SiGe or Si; although other III-V compound semiconductors or combinations thereof are contemplated herein. An annealing process may be performed to drive in the dopant.

Terminal connection <NUM> may be provided to the gate body 20a and wells <NUM>, <NUM>. The arrow adjacent the terminal connection 26a provides a current to the N-well <NUM> and, hence the back-gate diode <NUM>. On the other hand, the terminal connection 26b may be used to check leakage current from the P-well <NUM> as depicted by the arrow pointing away from the P-well <NUM> which is adjacent to the terminal connection 26b.

The terminal connections <NUM> may include a silicide and metal contacts, e.g., tungsten with a TaN or TiN liner or other conductive material. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over fully formed and patterned semiconductor devices (e.g., gate structure and wells <NUM>, <NUM>. After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active regions of the semiconductor device (e.g., source, drain, gate contact region) forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts. It should be understood by those of skill in the art that silicide contacts can also be provided on the source/drain regions 20b (but is not shown in this view).

<FIG> shows a built-in temperature sensor with a triple well, e.g., N-well <NUM> and additional P-well 16a. More specifically, the device 10a shows a deep N-well <NUM> in the handle substrate 12a underneath and contacting both the N-well <NUM> and P-well <NUM>. In this embodiment, the back-gate diode <NUM> may be provided within the handle substrate 12a formed by the junction of the deep N-well <NUM> and the P-well <NUM>. The N-well <NUM> and P-wells <NUM>, 16a and, in this embodiment, the deep N-well <NUM>, may be formed by an ion-implantation processes as is known in the art. The terminal connections <NUM> may be provided to the gate body 20a and wells <NUM>, <NUM>, 16a. A terminal connection 26c may provide current to an outer P-well 16a. As already described herein, the terminal connections <NUM> may include a silicide and metal contacts, e.g., tungsten with a TaN or TiN liner or other conductive material. The remaining features are similar to the structure <NUM> shown in <FIG>.

In operation and as shown schematically in the electrical schematic of <FIG>, the back-gate diode <NUM> can be exploited as a temperature sensor on FDSOI technology. For example, with in-situ monitoring, as the back-gate well <NUM> is applied a voltage (normally, it would be a reserve biasing), the current at the back-gate diode <NUM> can be recorded for estimating/evaluating ambient temperatures of the device according to the following equation: <MAT>
wherein: I and V are diode current and voltage, respectively; Io is the reverse saturation current; q is the charge on the electron; n is the ideality factor (n=<NUM> for indirect semiconductors (Si, Ge, etc.) and n=<NUM> for direct semiconductors (GaAs, InP, etc.)); k is Boltzmann's constant; T is temperature in Kelvin; and kT/q is thermal voltage.

In more specific embodiments, in the sequencing of monitoring the temperature, when a voltage is not applied to the back of the device <NUM>, e.g., back-gate voltage, the monitoring scheme may implement a sequence for device operation and temperature sensing. For example, once the device <NUM> is off, the back-gate diode <NUM> can be either forward biased or reserve biased to detect a current and hence a temperature. The resistor shown in <FIG> is representative of the resistance of the handle substrate 12a. In this embodiment (e.g., triple well device), both the diodes <NUM>, <NUM> are part of the device construction. Also, in <FIG>, the temperature sensor diode can be used as diode <NUM> while the diode <NUM> is not used during temperature sensing. (In the device <NUM> of <FIG>, there is no triple well and hence diode <NUM> would not be part of the device). It should also be understood that the operations described herein are also applicable to the device <NUM> of <FIG>.

As further shown in <FIG>, a transimpedance detection circuit <NUM>, ADC converter <NUM> and digital controller <NUM> may be provided outside of the device <NUM> (as represented by the dashed box). The transimpedance detection circuit <NUM> may detect a current drop during a biasing, e.g., forward biasing. The "forward biasing" in <FIG> refers to the case when the bias from the voltage source provides a positive voltage so that the diode <NUM> is ON. Thus, the ON current through diode <NUM> can flow into the transimpedance amplifier <NUM> and be converted to a voltage signal. Then such voltage signal can be translated into digital signal via the ADC <NUM>. which is provided to the digital controller <NUM>. The digital controller <NUM> may be used to provide a control feedback based on a temperature reading of the device 10a (or device <NUM>). An optional calibration step may be provided to record/establish the amplifier OFF temperature. In other words, the calibration step may be used to record the forward-biasing current before powering up the amplifier (e.g., device <NUM>). The benefit of such operation is that the monitoring has no impact/interruption on the circuit operations since the back-gate is normally applied to reserve bias the back-gate well <NUM>.

<FIG> shows a built-in temperature sensor and respective fabrication processes in accordance with a triple-well, similar to that described with respect to <FIG>. More specifically, the structure 10b of <FIG> includes the substrate <NUM> wherein, as in the previous embodiment, the substrate <NUM> may be a semiconductor on insulator (SOI) substrate which includes the handle substrate 12a, insulator layer 12b on the handle substrate 12a and the semiconductor substrate 12c. The semiconductor substrate 12c may be a fully depleted silicon-on-insulator (FDSOI) substrate, as an example. In this embodiment, the device <NUM> may be one or more transistors of a power amplifier as representatively shown in <FIG>, each of which are similar to that described with respect to <FIG> as an illustrative example.

An N-well <NUM> and P-wells <NUM>, 16a are provided in the handle substrate 12a. In this embodiment, the N-well <NUM> is isolated between the two P-wells <NUM>, 16a, with the P-well <NUM> under the device <NUM>. Accordingly, the P-well <NUM> may act as a back-gate well to the device <NUM>. A deep N-well <NUM> may be provided in the handle substrate 12a underneath and contacting both the N-well <NUM> and P-well <NUM>. In this embodiment, the back-gate diode <NUM> may be provided within the handle substrate 12a formed by the junction of the deep N-well <NUM> and the P-well <NUM>. As previously described, the N-well <NUM> and P-wells <NUM>, 16a and, in this embodiment, the deep N-well <NUM>, may be formed by an ion-implantation processes as is known in the art.

Similar to <FIG>, shallow trench isolation structures <NUM> may be provided within the handle substrate 12a to separate or isolate the P-wells 16a, <NUM> from the N-well <NUM>, and the P-well <NUM> from the device <NUM>. The terminal connections <NUM> may be provided to the gate body 20a and wells <NUM>, <NUM>, 16a. The arrow adjacent to the terminal connection 26a provides a current (voltage) to the P-well <NUM> and, hence the back-gate diode <NUM>. On the other hand, the contact 26b may be used to check leakage current from the N-well <NUM> as depicted by the arrow pointing away from the N-well <NUM> adjacent to the contact 26b. A terminal connection 26c may provide current to the outer P-well 16a. As already described herein, the terminal connections <NUM> may include a silicide and metal contacts, e.g., tungsten with a TaN or TiN liner or other conductive material.

<FIG> shows an electrical schematic diagram of the built-in temperature sensor of <FIG>, in operation during application of a back-gate bias. In this operation, an optional calibration step may be provided to record/establish the amplifier OFF temperature. In other words, the calibration step may be used to record the forward-biasing current before powering up the amplifier (e.g., device <NUM>). The voltage can be adjusted for the N-well <NUM> to forward bias the diode <NUM> as shown by the arrow in <FIG>. In this way, it is possible to detect the current to determine the temperature of the device <NUM>.

To save power consumption, the diode <NUM> does not have to be ON or forward-biased all the time (e.g., by adjusting the voltage of the N-well <NUM>); instead, the diode <NUM> can be ON only when the current needs to be detected. The temperature information during the amplifier operation can be fed back to control circuitry <NUM>, <NUM>, <NUM> as described above in to determine the temperature and adjust the biasing for cooling the device temperature.

<FIG> shows an electrical schematic diagram of the built-in temperature sensor of <FIG>, in operation when a back-gate bias is not used or the bias is set to zero. In this operation, the optional calibration step may be provided to record/establish the amplifier OFF temperature. For example, the amplifier (e.g., device <NUM>) can be turned OFF within a short amount of time and then the back-gate can forward-bias the diode <NUM> to detect the temperature of the device <NUM>. This is shown by the arrow in <FIG>. The temperature information during the amplifier operation can be fed back to control circuitry <NUM>, <NUM>, <NUM> as described above in to adjust the biasing for cooling the amplifier temperature.

<FIG> shows a chart simulating temperature conditions for a reverse bias operation. In <FIG>, the Y-axis is current and the X-axis is temperature. As shown in <FIG> during a reverse biasing, in operation, as temperature increases past <NUM>, the current also increases.

<FIG> shows a chart simulating temperature condition for a forward bias operation. In <FIG>, the Y-axis is current and the X-axis is temperature. As shown in <FIG> during a froward biasing, in operation, as temperature increases, the current also increases.

The built-in temperature sensors can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a "chip") that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.

The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

Claim 1:
A structure comprising:
a semiconductor on insulator substrate;
an insulator layer under the semiconductor on insulator substrate;
a handle substrate under insulator layer;
a first well of a first dopant type in the handle substrate;
a second well of a second dopant type in the handle substrate, adjacent to the first well; and
a back-gate diode partially in the first well.