Patent Description:
There are essentially two types of data memory devices used in electronic products, nonvolatile and volatile memory devices. Magnetic random access memory (MRAM) is a kind of nonvolatile memory technology. Unlike current industry-standard memory devices, MRAM uses magnetism instead of electrical charges to store data. In general, MRAM cells include a data layer and a reference layer. The data layer is composed of a magnetic material and the magnetization of the data layer can be switched between two opposing states by an applied magnetic field for storing binary information. The reference layer can be composed of a magnetic material in which the magnetization is pinned so that the strength of the magnetic field applied to the data layer and partially penetrating the reference layer is insufficient for switching the magnetization in the reference layer. During the read operation, the resistance of the MRAM cell is different when the magnetization alignments of the data layer and the reference layer are the same or not, and the magnetization polarity of the data layer can be identified accordingly.

The distance between adjacent MRAM cells is reduced as the density of the memory cell increases. Problems about related manufacturing processes and/or structures may occur when the MRAM cells are disposed too close to one another and have to be improved by design modification accordingly.

<CIT> relates to a magnetic tunnel junction (MTJ) device.

<CIT> relates to a semiconductor device and method for fabricating the same.

<CIT> relates to a semiconductor device and method for fabricated the same.

According to an embodiment of the present invention, a semiconductor device is provided. The present invention concerns a semiconductor device with two magnetic tunnel junctions according to the independent device claim <NUM>.

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The terms "on," "above," and "over" used herein should be interpreted in the broadest manner such that "on" not only means "directly on" something but also includes the meaning of "on" something with an intermediate feature or a layer therebetween, and that "above" or "over" not only means the meaning of "above" or "over" something but can also include the meaning it is "above" or "over" something with no intermediate feature or layer therebetween (i.e., directly on something).

The ordinal numbers, such as "first", "second", etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name.

The term "etch" is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. When "etching" a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is "removed", substantially all the material layer is removed in the process. However, in some embodiments, "removal" is considered to be a broad term and may include etching.

The term "forming" or the term "disposing" are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to <FIG> is a schematic drawing illustrating a semiconductor device <NUM> according to an embodiment of the present invention. As shown in <FIG>, the semiconductor device <NUM> includes a substrate <NUM>, a first magnetic tunnel junction (MTJ) structure 50A, a second MTJ structure 50B, and an interconnection structure CS. The first MTJ structure 50A, the second MTJ structure 50B, and the interconnection structure CS are disposed on the substrate <NUM>, and the interconnection structure CS is located between the first MTJ structure 50A and the second MTJ structure 50B in a first horizontal direction (such as a first direction D1 shown in <FIG>). The interconnection structure CS includes a first metal interconnection 40C and a second metal interconnection <NUM>. The second metal interconnection <NUM> is disposed on and contacts the first metal interconnection 40C. A material composition of the second metal interconnection <NUM> is different from a material composition of the first metal interconnection 40C. Related manufacturing problems when the interconnection structure between two adjacent MTJ structures is a single metal interconnection, such as a short circuit between the interconnection structure and a metal interconnection disposed corresponding to the MTJ structure, may be improved by the interconnection structure CS formed with the first metal interconnection 40C and the second metal interconnection <NUM> on the first metal interconnection 40C and formed between two adjacent MTJ structures, and the manufacturing yield may be enhanced accordingly.

In some embodiments, the substrate <NUM> may have a top surface TS and a bottom surface BS opposite to the top surface TS in a thickness direction of the substrate <NUM> (such as a third direction D3 shown in <FIG>), and the first MTJ structure 50A, the second MTJ structure 50B, and the interconnection structure CS described above may be disposed at a side of the top surface TS, but not limited thereto. A horizontal direction substantially orthogonal to the third direction D3 (such as the first direction D1 described above and a second direction D2 shown in <FIG>) may be substantially parallel with the top surface TS and/or the bottom surface BS of the substrate <NUM>, but not limited thereto. Additionally, in this description, a distance between the bottom surface BS of the substrate <NUM> and a relatively higher location and/or a relatively higher part in the vertical direction (such as the third direction D3) is greater than a distance between the bottom surface BS of the substrate <NUM> and a relatively lower location and/or a relatively lower part in the third direction D3. The bottom or a lower portion of each component may be closer to the bottom surface BS of the substrate <NUM> in the third direction D3 than the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surface BS of the substrate <NUM> in the third direction D3, and another component disposed under a specific component may be regarded as being relatively closer to the bottom surface BS of the substrate <NUM> in the third direction D3, but not limited thereto.

Specifically, the semiconductor device <NUM> may further include a third metal interconnection 70A, a fourth metal interconnection 70B, a fifth metal interconnection 40A, and a sixth metal interconnection 40B. The third metal interconnection 70A is disposed on and contacts the first MTJ structure 50A. The fourth metal interconnection 70B is disposed on and contacts the second MTJ structure 50B, the fifth metal interconnection 40A is disposed under and contacts the first MTJ structure 50A, and the sixth metal interconnection 40B is disposed under and contacts the second MTJ structure 50B. In other words, the third metal interconnection 70A and the fifth metal interconnection 40A may be disposed above and disposed under the first MTJ structure 50A in the third direction D3, respectively, and directly connected with the first MTJ structure 50A. The fourth metal interconnection 70B and the sixth metal interconnection 40B may be disposed above and disposed under the second MTJ structure 50B in the third direction D3, respectively, and directly connected with the second MTJ structure 50B. In addition, the first metal interconnection 40C in the interconnection structure CS may be disposed between the fifth metal interconnection 40A and the sixth metal interconnection 40B in the first direction D1, and the second metal interconnection <NUM> in the interconnection structure CS may be disposed between the third metal interconnection 70A and the fourth metal interconnection 70B in the first direction D1.

In some embodiments, the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B may be formed concurrently by the same manufacturing process, and the material composition of the second metal interconnection <NUM>, the material of the third metal interconnection 70A, and the material of the fourth metal interconnection 70B may be identical to one another accordingly, but not limited thereto. In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be formed concurrently by the same manufacturing process, and the material composition of the first metal interconnection 40C, the material of the fifth metal interconnection 40A, and the material of the sixth metal interconnection 40B may be identical to one another accordingly, but not limited thereto. In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be substantially disposed on the same plane. Therefore, a bottom surface BS3 of the first metal interconnection 40C, a bottom surface BS1 of the fifth metal interconnection 40A, and a bottom surface BS2 of the sixth metal interconnection 40B may be substantially coplanar. Additionally, a bottom surface of the second metal interconnection <NUM> may be lower than a bottom surface of the third metal interconnection 70A and a bottom surface of the fourth metal interconnection 70B in the third direction D3 because there is not any MTJ structure disposed between the first metal interconnection 40C and the second metal interconnection <NUM> of the interconnection structure CS, and the first metal interconnection 40C and the second metal interconnection <NUM> of the interconnection structure CS may be directly connected with each other. In some embodiments, an upper portion of the first metal interconnection 40C may be influenced and damaged by manufacturing processes. Therefore, and a top surface TS3 of the first metal interconnection 40C and the bottom surface of the second metal interconnection <NUM> may be slightly lower than a top surface TS1 of the fifth metal interconnection 40A and a top surface TS2 of the sixth metal interconnection 40B in the first direction D1, but not limited thereto. Additionally, in some embodiments, a bottom width of the second metal interconnection <NUM> (such as a width W2 shown in <FIG>) may be greater than a top width of the first metal interconnection 40C (such as a width W1 shown in <FIG>) for reducing negative influence of alignment shifting generated by process variations on the electrical connection between the second metal interconnection <NUM> and the first metal interconnection 40C, but not limited thereto.

In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be respectively regarded as a via conductor mainly elongated in the vertical direction (such as the third direction D3), and the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B may be respectively regarded as a trench conductor mainly elongated in a horizontal direction. In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may respectively include a barrier layer <NUM> and a metal layer <NUM>, but not limited thereto. The barrier layer <NUM> may include titanium (Ti), titanium nitride (TiN), or other suitable barrier materials, and the metal layer <NUM> may include tungsten (W), aluminium (Al), titanium aluminide (TiAl), or other suitable metallic materials. In some embodiments, the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B may respectively include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer as well. The metal layers in the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B may be a metallic material with low electrical resistivity and diffusion concern (such as copper) because the third metal interconnection 70A and the fourth metal interconnection 70B are disposed on the MTJ structure respectively and the barrier layer may be used to avoid the negative influence of the diffusion of the metal layer on the MTJ structure, but not limited thereto. Comparatively, it is not suitable to form the metal layer <NUM> with copper because the metal layers <NUM> in the fifth metal interconnection 40A and the sixth metal interconnection 40B directly contact the MTJ structure, and the material composition of the second metal interconnection <NUM> may be different from the material composition of the first metal interconnection 40C accordingly. For example, the metal layer <NUM> described above may be a tungsten layer and the corresponding barrier layer <NUM> may be titanium, titanium nitride, and/or a stacked layer of titanium and titanium nitride. The metal layer in the second metal interconnection <NUM> may be copper, and the corresponding barrier layer may be tantalum nitride (TaN) or other suitable barrier materials.

In some embodiments, the substrate <NUM> may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include a silicon substrate, a silicon germanium semiconductor substrate or a silicon-on-insulator (SOI) substrate, and the non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, but not limited thereto. For example, when the substrate <NUM> includes a semiconductor substrate, a plurality of silicon-based field effect transistors (not shown), a dielectric layer (such as a dielectric layer <NUM> and a dielectric layer <NUM> shown in <FIG>) covering the silicon-based field effect transistors, and metal interconnections <NUM> may be formed on the semiconductor substrate before the step of forming the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B described above. In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be electrically connected with some of the metal interconnections <NUM>, and the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be electrically connected downward to the silicon-based field effect transistor described above via some of the metal interconnections <NUM>, but not limited thereto. In some embodiments, each of the metal interconnections <NUM> may be regarded as a trench conductor mainly elongated in a horizontal direction. Additionally, in some embodiments, the substrate <NUM> may include a first region R1 and a second region R2. The first region R1 may be regarded as a memory cell region with MTJ structures formed thereon, the second region R2 located between two adjacent first region R1 may be regarded as a region corresponding to word lines, and the metal interconnection <NUM> disposed on the second region R2 and electrically connected with the first metal interconnection 40C may include a word line WL accordingly, but not limited thereto.

In some embodiments, the semiconductor device <NUM> may further include a stop layer <NUM>, a first inter-metal dielectric (IMD) layer <NUM>, a cap layer <NUM>, a second IMD layer <NUM>, an ultra-low dielectric constant (ULK) dielectric layer <NUM>, and an opening OP. The first IMD layer <NUM> may be disposed on the substrate <NUM> and located on the dielectric layer <NUM>. The stop layer <NUM> may be disposed between the first IMD layer <NUM> and the dielectric layer <NUM>. The cap layer <NUM> may be disposed on the first MTJ structure 50A, the second MTJ structure 50B, and the first IMD layer <NUM>, and the second IMD layer <NUM> may be disposed on the cap layer <NUM>. The opening OP may be located above the first metal interconnection 40C and penetrate through the second IMD layer <NUM> and the cap layer <NUM> in the third direction D3, and the second metal interconnection <NUM> may be disposed in the opening OP. In some embodiments, the ULK dielectric layer <NUM> may be disposed on the second IMD layer <NUM> and disposed in the opening OP, and at least a part of the ULK dielectric layer <NUM> may be located between the second metal interconnection <NUM> and the second IMD layer <NUM> in the first direction D1, but not limited thereto. In some embodiments, the first IMD layer <NUM> and the stop layer <NUM> may surround the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B in the horizontal direction; the cap layer <NUM> may be located on sidewalls of the first MTJ structure 50A and sidewalls of the second MTJ structure 50B; and the second IMD layer <NUM> may surround a part of the third metal interconnection 70A and a part of the fourth metal interconnection 70B in the horizontal direction, but not limited thereto.

In some embodiments, the second metal interconnection <NUM> may penetrate through the ULK dielectric layer <NUM> located in the opening OP in the third direction D3, the third metal interconnection 70A may penetrate through the second IMD layer <NUM> and the ULK dielectric layer <NUM> on the first MTJ structure 50A in the third direction D3, and the fourth metal interconnection 70B may penetrate through the second IMD layer <NUM> and the ULK dielectric layer <NUM> on the second MTJ structure 50B in the third direction D3. Additionally, in some embodiments, the substrate <NUM> may further include a third region R3, the semiconductor device <NUM> may further include a metal interconnection <NUM> disposed on the third region R3 and electrically connected with the metal interconnection <NUM> on the third region R3, and the third region R3 may be regarded as a logic region, but not limited thereto. In some embodiments, the metal interconnection <NUM> may include a via conductor 74A and a trench conductor 74B connected with the via conductor 74A for forming a dual damascene structure, but not limited thereto. In some embodiments, the metal interconnection <NUM> may be formed on the third region R3 with a single damascene structure or other suitable structures according to other design considerations.

In some embodiments, the structure of the metal interconnection <NUM> may be similar to that of the second metal interconnection <NUM> and include a barrier layer (shown) and a metal layer (not shown), but not limited thereto. In some embodiments, the dielectric layer <NUM>, the dielectric layer <NUM>, the first IMD layer <NUM> ad the second IMD layer <NUM> may respectively include silicon oxide, a low dielectric constant (low-k) dielectric material, or other suitable dielectric materials. The ULK dielectric layer <NUM> may include a dielectric material with a dielectric constant lower than <NUM>, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), hydrogenated silicon oxycarbide (SiOC-H), a porous dielectric material, or other suitable dielectric materials. The stop layer <NUM> may include nitrogen doped carbide (NDC), silicon nitride, silicon carbon-nitride (SiCN), or other suitable insulation materials. The cap layer <NUM> may include silicon nitride or other dielectric material different from the first IMD layer <NUM> and the second IMD layer <NUM>, and the cap layer <NUM> may be used as an etching stop layer accordingly, but not limited thereto.

In some embodiments, the semiconductor device <NUM> may include a plurality of metal interconnections <NUM>, a plurality of MTJ structures <NUM>, and a plurality of metal interconnections <NUM>. Each of the MTJ structures <NUM> may be disposed corresponding to and electrically connected with one of the metal interconnections <NUM> and one of the metal interconnections <NUM>. Two of the MTJ structures <NUM> adjacent to each other may be regarded as the first MTJ structure 50A and the second MTJ structure 50B described above, two of the metal interconnections <NUM> may be respectively regarded as the fifth metal interconnection 40A and the sixth metal interconnection 40B described above, and two of the metal interconnections <NUM> may be respectively regarded as the third metal interconnection 70A and the fourth metal interconnection 70B described above.

In some embodiments, each of the MTJ structures <NUM> may include a first electrode <NUM>, a pinned layer <NUM>, a first barrier layer <NUM>, a free layer <NUM>, a second barrier layer <NUM>, and a second electrode <NUM> disposed sequentially stacked in the third direction D3, but not limited thereto. In some embodiments, the MTJ structure <NUM> may include a stacked structure different from the materials layers described above and/or include other material layers. In some embodiments, the first electrode <NUM> and the second electrode <NUM> may include metallic materials, such as tantalum (Ta), platinum (Pt), ruthenium (Ru), a stack layer of the above-mentioned materials, an alloy of the above-mentioned materials, or other suitable conductive materials. The pinned layer <NUM> may include an antiferromagnetic layer and a reference layer. The antiferromagnetic layer may include antiferromagnetic materials such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), a cobalt/platinum (Co/Pt) multilayer, or other suitable antiferromagnetic materials. The free layer <NUM> and the reference layer in the pinned layer <NUM> may include ferromagnetic materials such as iron, cobalt, nickel, cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or other suitable ferromagnetic materials. The first barrier layer <NUM> and the second barrier layer <NUM> may include insulation materials such as magnesium oxide (MgO), aluminium oxide, or other suitable insulation materials. The above-mentioned material layers in the MTJ structure <NUM> may be formed by deposition processes, such as sputtering processes, but not limited thereto.

Please refer to <FIG> and <FIG> is a schematic drawing illustrating a top view of a semiconductor device according to an embodiment of the present invention. <FIG> may be regarded as a schematic drawing illustrating a top view of the first region R1 and the second region R2 shown in <FIG> without illustrating the third region R3, but not limited thereto. As shown in <FIG> and <FIG>, according to the present invention, the second metal interconnection <NUM> is elongated in the first horizontal direction (such as the first direction D1), the third metal interconnection 70A and the fourth metal interconnection 70B are elongated in a second horizontal direction (such as the second direction D2), respectively, and the first direction D1 and the second direction D2 are orthogonal. In some embodiments, the word line WL may be elongated in the second direction D2 and disposed parallel with the metal interconnection <NUM>, and the word line WL may be disposed corresponding to a plurality of the interconnection structures CS for avoiding the negative influence of a single second metal interconnection <NUM> with greater area and depth on the adjacent metal interconnections <NUM> and/or the MTJ structures <NUM>, such as the loading effect of an etching process for forming the corresponding trench, but not limited thereto. Therefore, the elongation direction of the second metal interconnection <NUM> in the interconnection structure CS may be different from the elongation direction of the metal interconnection <NUM>. In some embodiments, a length of the second metal interconnection <NUM> in the first direction D1 is greater than a length of the second metal interconnection <NUM> in the second direction D2, and a length of the metal interconnection <NUM> in the second direction D2 is greater than a length of the metal interconnection <NUM> in the first direction D1. Additionally, in some embodiments, a length of the first metal interconnection 40C in the first direction D1 may be less than the length of the second metal interconnection <NUM> in the first direction D1, and the length of the first metal interconnection 40C in the first direction D1 may be substantially equal to a length of the first metal interconnection 40C in the second direction D2, but not limited thereto.

Please refer to <FIG> and <FIG>. <FIG> are schematic drawings illustrating a manufacturing method of a semiconductor device according to an embodiment of the present invention, wherein <FIG> is a schematic drawing in a step subsequent to <FIG>, <FIG> is a schematic drawing in a step subsequent to <FIG>, <FIG> is a schematic drawing in a step subsequent to <FIG>, and <FIG> may be regarded as a schematic drawing in a step subsequent to <FIG>, but not limited thereto. As shown in <FIG>, the manufacturing method of the semiconductor device <NUM> in this embodiment may include the following steps. The first MTJ structure 50A, the second MTJ structure 50B, and the interconnection structure CS are formed on the substrate <NUM>. The interconnection structure CS is located between the first MTJ structure 50A and the second MTJ structure 50B in the first direction D1. The interconnection structure CS includes the first metal interconnection 40C and the second metal interconnection <NUM>. The second metal interconnection <NUM> is disposed on and contacts the first metal interconnection 40C. The material composition of the second metal interconnection <NUM> is different from the material composition of the first metal interconnection 40C. In addition, the third metal interconnection 70A and the fourth metal interconnection 70B may be formed on the substrate <NUM>. The third metal interconnection 70A is disposed on and contacts the first MTJ structure 50A, and the fourth metal interconnection 70B is disposed on and contacts the second MTJ structure 50B. The second metal interconnection <NUM> is elongated in the first direction D1, and the third metal interconnection 70A and the fourth metal interconnection 70B are elongated in the second direction D2, respectively.

Specifically, the manufacturing method of the semiconductor device in this embodiment may include but is not limited to the following steps. Firstly, as shown in <FIG>, the dielectric layer <NUM>, the dielectric layer <NUM>, the metal interconnections <NUM>, the stop layer <NUM>, the first IMD layer <NUM>, the metal interconnections <NUM>, the first metal interconnection 40C, the MTJ structures <NUM>, and the cap layer <NUM> are formed on the substrate <NUM>. In some embodiments, the MTJ structures <NUM> may be formed by performing an etching process for patterning material layers required in the MTJ structure <NUM>, and the etching process may include reactive ion etching (RIE) process and/or ion beam etching (IBE) process, but not limited thereto. Because of the characteristics of the IBE process, a part of the first IMD layer <NUM> may be removed by the process of forming the MTJ structures <NUM>, and a top surface of the remaining part of the first IMD layer <NUM> may include a recess surface, such as a concave curved surface. In some embodiments, the first metal interconnection 40C, the fifth metal interconnection 40A, and the sixth metal interconnection 40B may be formed with same material and formed concurrently by the same process. The first IMD layer <NUM> located between the fifth metal interconnection 40A and the sixth metal interconnection 40B may be influenced by the first metal interconnection 40C and has a relatively higher top surface, and the top surface of the first IMD layer <NUM> located between the fifth metal interconnection 40A and the sixth metal interconnection 40B may be higher than the concave surface of the first IMD layer <NUM> on other regions (such as the first IMD layer <NUM> on the third region R3), but not limited thereto. In addition, the cap layer <NUM> may be formed conformally on the first IMD layer <NUM>, the MTJ structures <NUM>, and the first metal interconnection 40C.

Subsequently, as shown in <FIG>, the second IMD layer <NUM> may be formed on the cap layer <NUM>. In some embodiments, an etching back process may be performed to the second IMD layer <NUM> for reducing the thickness of the second IMD layer <NUM>, but not limited thereto. As shown in <FIG>, a part of the second IMD layer <NUM> and a part of the cap layer <NUM> may be then removed for forming the opening OP, and the opening OP exposes the first metal interconnection 40C. In some embodiments, a part of the first metal interconnection 40C may be removed by the process of forming the opening OP (such as an etching process), and the top surface TS3 of the first metal interconnection 40C may be slightly lower than the top surface TS1 of the fifth metal interconnection 40A and the top surface TS2 of the sixth metal interconnection 40B in the third direction D3 accordingly. Additionally, the second IMD layer <NUM> and the cap layer <NUM> on the third region R3 may be removed for exposing the first IMD layer <NUM> on the third region R3. Subsequently, as shown in <FIG>, the ULK dielectric layer <NUM> may be formed, and the ULK dielectric layer <NUM> may be formed in the opening OP, on the second IMD layer <NUM>, and on the first IMD layer <NUM> above the third region R3.

In some embodiments, an etching back process may be performed to the ULK dielectric layer <NUM> for reducing the thickness of the ULK dielectric layer <NUM>, but not limited thereto. In addition, because of the influence of the MTJ structures <NUM>, it is difficult to form the ULK dielectric layer <NUM> with a flat surface. However, compared to the situation where the first metal interconnection 40C is not formed, the surface height difference of the ULK dielectric layer <NUM> may be improved by the arrangement of the first metal interconnection 40C. For example, in the situation where the first metal interconnection 40C is not formed, the bottom surface of the opening corresponding to the second region R2 and the surface of the fist IMD layer <NUM> above the third region R3 will be located at nearly the same level in the third direction D3, and the ULK dielectric layer <NUM> subsequently formed will be influenced and may be formed with a greater surface height difference.

As shown in <FIG> an <FIG>, the metal interconnections <NUM>, the second metal interconnection <NUM>, and the metal interconnection <NUM> may be formed. In some embodiments, the metal interconnections <NUM>, the second metal interconnection <NUM>, and the metal interconnection <NUM> may be formed with the same material and formed concurrently by the same process, but not limited thereto. For example, trenches corresponding to the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B, such as a trench penetrating through the ULK dielectric layer <NUM> on the first metal interconnection 40C and trenches penetrating through the ULK dielectric layer <NUM>, the second IMD layer <NUM>, and the cap layer <NUM> on the MTJ structures <NUM>, may be formed firstly. The trenches described above may then be filled with the corresponding metallic material, and a chemical mechanical polishing process may be performed to the metallic material for removing a part of the metallic material and forming the second metal interconnection <NUM>, the third metal interconnection 70A, and the fourth metal interconnection 70B. In the chemical mechanical polishing process described above, the surface flatness of the ULK dielectric layer <NUM> will affect the progress of the chemical mechanical polishing process. For example, the metallic material may remain on the ULK dielectric layer <NUM> when the surface height difference of the ULK dielectric layer <NUM> is too large, and the remaining metallic material on the ULK dielectric layer <NUM> may electrically connect the second metal interconnection <NUM> and the metal interconnection <NUM> that need to be electrically separated from each other in design. Therefore, the surface height difference of the ULK dielectric layer <NUM> may be reduced by the interconnection structure CS formed with the first metal interconnection 40C and the second metal interconnection <NUM> between two MTJ structures <NUM>, and the manufacturing yield of the semiconductor device may be improved accordingly.

To summarize the above descriptions, in the semiconductor device according to the present invention, the interconnection structure is formed with the first metal interconnection and the second metal interconnection and located between two adjacent magnetic tunnel junction structures for improving problems such as a short circuit between the interconnection structure and the magnetic tunnel junction structure when the magnetic tunnel junction structures are disposed too close to each another. Accordingly, the manufacturing yield of the semiconductor device may be improved.

Claim 1:
A semiconductor device (<NUM>), comprising:
a substrate (<NUM>);
a first magnetic tunnel junction, MTJ, structure (50A) disposed on the substrate (<NUM>);
a second MTJ structure (50B) disposed on the substrate (<NUM>); and
an interconnection structure (CS) disposed on the substrate (<NUM>), wherein the interconnection structure (CS) comprises:
a first metal interconnection (40C) and
a second metal interconnection (<NUM>) disposed on and contacting the first metal interconnection (40C), the first metal interconnection (40C) and the second metal interconnection (<NUM>) being located between the first MTJ structure (50A) and the second MTJ structure (50B) in a first horizontal direction (D1);
a third metal interconnection (70A) disposed on and contacting the first MTJ structure (50A); and
a fourth metal interconnection (70B) disposed on and contacting the second MTJ structure (50B);
characterized in that the second metal interconnection (<NUM>) is elongated in the first horizontal direction (D1), and the third metal interconnection (70A) and the fourth metal interconnection (70B) are elongated in a second horizontal direction (D2), respectively;
wherein the first horizontal direction (D1) is orthogonal to the second horizontal direction (D2), and the first horizontal direction (D1) and the second horizontal direction (D2) are orthogonal to a thickness direction (D3) of the substrate (<NUM>); and
wherein in a top view of the semiconductor device, a width of each of two end portions of the second metal interconnection (<NUM>) in the first horizontal direction (D1) is greater than a width of a middle portion of the second metal interconnection (<NUM>) located between the two end portions of the second metal interconnection (<NUM>).