Patent Description:
<FIG> is an example of one type of PoDL system where DC power and Ethernet differential data signals are provided over the same twisted wire pair. The Power Sourcing Equipment (PSE) is on the left side, and the Powered Device (PD) is on the right side.

A PHY <NUM> outputs differential data and receives differential data via a conventional Media Dependent Interface (MDI) connector <NUM> coupled to wires <NUM> and <NUM> of a twisted wire pair. The PHY <NUM> represents the physical layer in the OSI model and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is a term of art and is defined by various IEEE standards, depending on the particular application. The PHY <NUM> is typically an integrated circuit. A digital processor (not shown) is coupled to the PHY <NUM> for processing the data. For purposes of this disclosure, the PHY <NUM> is a digital, differential data transceiver.

The PHY <NUM> is connected to the MDI connector <NUM> via AC-coupling capacitors C1 and C2. The capacitors C1 and C1 prevent DC voltage being coupled to the PHY <NUM> inputs to avoid corrupting the differential data and also prevent the PSE power supply <NUM> being shorted out by the PHY <NUM>.

The PSE power supply <NUM> provides a suitable DC voltage across the wires <NUM> and <NUM>, such as 45VDC.

DC-coupling inductors L1 and L2 provide a high impedance to the data signals and a low impedance to the DC voltage, so the power supply <NUM> impedance does not load the data signals.

The PD side may be identical to the PSE side except that the DC voltage is coupled to a PD load <NUM> via the DC-coupling inductors L3 and L4. The AC-coupling capacitors C3 and C4 couple the differential data to the PHY <NUM>. An MDI <NUM> couples the wires <NUM> and <NUM> to the PD circuitry. The PD load <NUM> may be any powered device, such as a sensor, camera, etc..

PSE and PD controllers are not shown and perform a handshaking routine to ensure the PD is compatible with PoDL. If the PD is PoDL-compatible, the PSE controller closes a switch to supply the full DC voltage across the wires <NUM> and <NUM>.

Ceramic capacitors are commonly used in PoDL systems for AC-coupling due to their small size and other characteristics. It is well-known that the effective capacitance value of ceramic capacitors reduces as the DC voltage across the capacitor increases. Such a change in value is referred to as the DC bias characteristic of the capacitor or the capacitor's negative voltage coefficient. In some examples of ceramic capacitors used in PoDL systems, the nominal capacitance value (with 0V across it) is reduced by about <NUM>% when the full PSE voltage of about 45VDC is applied across it.

In the example of <FIG>, the capacitor C1 sees approximately the full DC voltage of VPSE across it, while the capacitor C2 sees about 0V across it. Therefore, the effective value of the capacitor C1 is about half that of the capacitor C2. The same applies to the PD capacitors C3 and C4.

As a result of this difference in effective capacitor values, the capacitors C1 and C2 produce non-symmetrical effects on the differential data signals and on common mode signals (e.g., noise signals). So the data paths are unbalanced. In an extreme instance, the differences could result in conversion of a common mode noise signal into a signal that the PHY <NUM> interprets as a data signal.

<FIG> illustrates another example of a PoDL system, where a center-tapped transformer <NUM> is used to galvanically isolate the PHY <NUM> from the wires <NUM> and <NUM>. The PHY signals are magnetically coupled to the wire pair. The secondary windings <NUM> are coupled to the line-side, and the primary winding <NUM> is coupled across the terminals of the PHY <NUM>. AC-coupling capacitors C1 and C2 are also present to prevent the secondary windings <NUM> of the transformer <NUM> from shorting out the PSE power supply <NUM>. Since the center-tap of the transformer <NUM> is grounded, the DC bias across capacitor C1 is approximately VPSE while the DC bias across the capacitor C2 is approximately 0V. As a result, the capacitor C1 capacitance is substantially less than the capacitor C2 capacitance, leading to the same problems mentioned regarding <FIG>.

What is needed is a technique whereby the AC-coupling capacitors in a PoDL system retain approximately equal effective values while blocking the DC voltage.

<CIT> discloses a PoDL system where the PHY has its input/output terminals coupled to a wire pair via an isolation transformer and a CMC and wherein the I/O terminals are directly coupled across the primary winding of the transformer. In the PoDL system of <CIT>, one end of the secondary winding of the transformer is directly coupled to one winding of the CMC. A DC power supply has one output terminal directly coupled to the other end of the secondary winding and has its other output terminal directly coupled to the other winding of the CMC. An AC-coupling capacitor is coupled between the two outputs of the power supply, so that the capacitor passes differential signals.

Various PoDL circuits are described where the AC-coupling capacitors have approximately equal effective values at any DC bias voltage. The capacitors have the same nominal value at 0V bias.

In one embodiment of the inventive PoDL circuit, a first AC-coupling capacitor has one terminal coupled to the full PSE voltage of VPSE, and a second AC-coupling capacitor has one terminal coupled to approximately ground or other reference voltage, similar to the prior art. In the prior art, the other ends of both capacitors would be coupled to a low voltage, so there would be very different DC bias voltages across the two capacitors, causing their effective values to be very different. The present inventive technique uses a resistor divider to create the voltage VPSE/<NUM>. This voltage of VPSE/<NUM> (instead of ground) is applied to the other ends of the capacitors, so both capacitors have VPSE/<NUM> across them. Hence, even though the capacitance values have lowered due to the VPSE/<NUM> bias, the capacitors' effective values remain equal. Therefore, the two data paths are balanced, resulting in more accurate data communication and higher efficiency.

In one example, the PoDL system uses a center-tapped transformer for isolation and to attenuate common mode noise. Instead of the center tap being coupled to ground, as in the prior art, the center tap is coupled to VPSE/<NUM>. In a related embodiment, the center tap is coupled to ground via an AC-coupling third capacitor to attenuate noise.

A common mode choke (CMC) may be added in series with the AC-coupling capacitors to further attenuate AC common mode noise.

In a example, the same technique is employed in termination RC networks used to prevent reflections of any common mode noise on the twisted wire pair. The termination circuitry is generally designed to match the common mode impedance of the wire pair for maximum energy absorption and minimum reflectance while preserving the differential mode impedance presented by the transceiver. In the prior art, identical capacitor/resistors networks are used to terminate the wires in the PoDL system. In the prior art, both capacitors are coupled to ground, so one capacitor sees a high DC bias and the other capacitor sees a zero DC bias. This difference in DC bias voltages causes the termination networks to have different characteristics, possibly leading to the conversion of common mode noise signals to differential signals, corrupting the Ethernet data. By using the present invention, the voltage VPSE/<NUM> is generated using a resistive divider, and the VPSE/<NUM> voltage is applied to the common terminals of the termination capacitors instead of ground. Therefore, both termination capacitors see a DC bias voltage of VPSE/<NUM>, and their effective capacitances remain equal. Conversion of common mode noise signals is thus prevented due to the balanced termination networks.

Elements in the various figures that are the same or equivalent are labelled with the same numerals.

<FIG> illustrates the PSE side of a PoDL system, similar to the PoDL system of <FIG>, but where the AC-coupling capacitors C1 and C2 have the same DC voltage across them so they have the same effective value. This results in a more balanced circuit so that the differential data on the wires <NUM> and <NUM> see the same impedances for more accurate data communications.

In <FIG>, a resistor divider is added, using equal value resistors R1 and R2, between the PSE power supply <NUM> output terminal (providing the voltage VPSE) and ground (i.e., the power supply's reference voltage). Thus, the voltage VPSE/<NUM> is output at the common node of the resistors R1 and R2. This voltage VPSE/<NUM> is applied to the center tap of the isolation transformer <NUM>.

The inductor L1 couples the power supply's VPSE voltage to one end of the capacitor C1 and the wire <NUM>, and the inductor L2 couples the ground voltage to one end of the capacitor C2 and the wire <NUM>. The secondary windings <NUM> (comprising the upper secondary winding 28A and the lower secondary winding 28B) couple the center-tap voltage VPSE/<NUM> to the other ends of the capacitors C1 and C2, resulting in both capacitors C1 and C2 having VPSE/<NUM> across them. Since the DC bias voltages across both capacitors C1 and C2 are the same, the capacitors C1 and C2 have the same effective value. Therefore, the impedances for both the upper and lower data paths are the same, resulting in a balanced circuit for the differential data. This avoids the conversion of common mode noise into differential signals, which may corrupt the data communications. The primary winding <NUM> is connected across the terminals of the PHY <NUM>.

Instead of a resistor divider, other forms of voltage dividers can be used. For example, equal value capacitors in series may form a suitable voltage divider.

<FIG> illustrates the PD side of the PoDL system, which also uses a center-tapped transformer <NUM> for galvanic isolation of the PHY <NUM> from the wires <NUM> and <NUM>. Inductors L3 and L4 perform DC-coupling of the DC voltage on the wires <NUM> and <NUM> to the PD load <NUM> for powering the PD load <NUM>. The PD load <NUM> may include a voltage regulator for generating a suitable voltage for circuitry within the PD load <NUM>. Although not shown, the received or regulated DC voltage is also coupled to the PHY <NUM> for powering the PHY <NUM> and any other circuits. The capacitors C3 and C4 perform AC-coupling of the differential data signals to the PHY <NUM> via the transformer <NUM>.

The DC voltage received at the MDI <NUM> is somewhat less than the full PSE voltage VPSE supplied by the PSE power supply <NUM> in <FIG> due to losses in the wires <NUM> and <NUM>. This DC voltage is coupled, via inductors L3 and L4, across the resistive divider, formed by the equal value resistors R3 and R4, to generate an intermediate voltage. Similar to <FIG>, one end of the capacitor C3 receives the full PSE voltage at the MDI <NUM> from the wire <NUM>, and the other end of the capacitor C3 receives the intermediate voltage at its other end, via the secondary winding <NUM>. Thus, approximately one-half of the full DC voltage is applied across the capacitor C3. One end of the other capacitor C4 receives the power supply reference voltage (e.g., ground voltage) from the wire <NUM>, and the other end of the capacitor C4 receives the intermediate voltage via the secondary winding <NUM>. Therefore, both capacitors C3 and C4 have the same DC voltage across them so they have equal effective values. As a result, the upper and lower data paths are balanced and there is no conversion of common mode noise to differential signals. Data accuracy is maintained even in a very noisy environment.

<FIG> illustrates the use of an AC-coupling capacitor C6 coupling the center tap of the transformer <NUM> to ground (or other system reference) to provide a low impedance AC path to ground. The capacitor C6 is a bypass capacitor that couples AC noise to ground. The capacitor C6 has no effect on the DC voltage. This is useful in noisy environments. A common mode choke (CMC) <NUM> is also inserted in series with the data path to also attenuate common mode noise. The CMC <NUM> is an in-line transformer with two windings, where each winding is in series with a wire <NUM> or <NUM>. As shown by the dots on the CMC <NUM> windings, the windings have the same polarity, so the magnetic fields generated by a differential mode signal are substantially cancelled out. Thus, the CMC <NUM> presents little inductance or impedance to differential-mode currents. Common mode currents, such as ambient noise in the wires <NUM> and <NUM>, however, see a high impedance due to the combined inductances of the windings. The CMC <NUM> ideally eliminates or greatly attenuates common mode RF noise while providing no loss for the differential data or DC voltage signals.

The operation of the circuit of <FIG> is the same as the operation of <FIG> regarding the AC-coupling capacitors C1 and C2 seeing the same DC voltage across them. The inductors L1 and L2, the windings of the CMC <NUM>, and the secondary windings <NUM> of the isolation transformer <NUM> conduct DC current so the capacitors C1 and C2 both have approximately one-half the full DC voltage across them, resulting in equal effective values.

<FIG> is identical to <FIG> except conventional RC termination networks are connected to the wires <NUM> and <NUM> to attenuate common mode noise. The wire <NUM> (carrying the voltage VPSE) is terminated by the series connection of the resistor R5 and the capacitor C7 to ground. The wire <NUM> (carrying the reference voltage) is terminated by the series connection of the resistor R6 and the capacitor C8 to ground. Thus, the capacitor C7 sees a high DC voltage (VPSE) across it, and the capacitor C8 sees a low DC voltage across it. As a result, the effective values of the capacitors C7 and C8 will be different, resulting in an unbalanced network. This may lead to conversion of common mode noise into differential signals that can corrupt the data.

<FIG> illustrates the application of the invention to the RC networks of a PoDL system. In <FIG>, a resistor divider, formed by the equal value resistors R7 and R8, is connected across approximately VPSE and ground to generate VPSE/<NUM> at their common node. This voltage VPSE/<NUM> is coupled to the common node of the capacitors C7 and C8 so approximately VPSE/<NUM> is across both capacitors C7 and C8. As a result, both capacitors C7 and C8 have the same effective value. An AC-coupling capacitor C9 couples the ends of capacitors C7 and C8 to ground. Due to the addition of the capacitor C9, the selection of the optimal values of the capacitors C7 and C8 needs to take into account the capacitance of the capacitor C9.

Although the inventive techniques have been primarily shown being applied to the PSE side of the PoDL system, the same techniques can also be applied to the PD side of the PoDL system, such as shown in <FIG>. These techniques can be applied to any PoDL circuit using AC-coupling capacitors.

Although the figures show various components directly connected to each other or connected to each other via other circuitry, all such components are said to be "coupled" to one another. Accordingly, the term "coupled" does not require direct coupling.

Any of the disclosed features may be combined for a particular application.

Claim 1:
A Power over Data Lines,PoDL, circuit comprising:
a DC power supply (<NUM>) having a first terminal DC-coupled to a first conductor (<NUM>) and a second terminal DC-coupled to a second conductor (<NUM>), wherein the first conductor (<NUM>) and second conductor (<NUM>) are for supplying DC power and differential data to a powered device,PD;
a first transceiver (<NUM>) having a first terminal and a second terminal, the first transceiver for transmitting differential data signals over the first conductor (<NUM>) and the second conductor (<NUM>) and receiving differential data signals from the first conductor (<NUM>) and the second conductor (<NUM>);
a center-tapped first transformer (<NUM>) having a primary winding (<NUM>) coupled across the first terminal and the second terminal of the first transceiver (<NUM>);
a first AC-coupling capacitor, C1, coupled in series with the first conductor (<NUM>), the first transformer (<NUM>) having a first secondary winding (28A) coupled between the first AC-coupling capacitor, C1, and a center tap of the first transformer (<NUM>);
a second AC-coupling capacitor, C2, coupled in series with the second conductor (<NUM>), the first transformer (<NUM>) having a second secondary winding(28B) coupled between the second AC-coupling capacitor, C2, and the center tap of the first transformer (<NUM>); and characterized by
a first voltage divider coupled to the DC power supply (<NUM>), the first voltage divider generating a first divided voltage of approximately one half of a voltage output by the DC power supply (<NUM>), wherein the first divided voltage is applied to the center tap of the first transformer (<NUM>).