Patent Description:
One or more embodiments may be applied to galvanic isolators.

In recent years, several applications have been taking advantage of galvanic isolation, e.g., to improve safety and reliability, especially in adverse environments. Galvanic isolation is a desirable feature in certain automotive applications (e.g., driver devices for electric and hybrid vehicles), in the industrial environment (e.g., motor control, automation, and the like), in medical equipment, in consumer products (e.g., home appliances), in gate drivers for power devices (e.g., power MOS, SiC or GaN devices), and even in communication networks. A galvanic isolator facilitates data transfer across a galvanic barrier and allows bidirectional communication between two isolated interfaces.

A conventional galvanically-isolated system <NUM> is exemplified in <FIG>, which is known from document <NPL> (Ragonese et al. hereinafter). An isolated system <NUM> may comprise a first device <NUM><NUM> and a second device <NUM><NUM>. The first device <NUM><NUM> may comprise, for instance, human/data interfaces, bus controllers, network controllers, microcontroller unit(s), and generally any component useful to provide an interface of the system <NUM> with the environment (e.g., a user). The second device <NUM><NUM> may comprise, for instance, sensor interfaces, gate drivers, medical devices, communication networks, and generally any component useful for operation of the system <NUM>, depending on the application. The first device <NUM><NUM> may be coupled between a first supply terminal <NUM><NUM> and a first reference terminal GND<NUM> (e.g., a ground or earth reference) to receive a first supply voltage VDD1, and the second device <NUM><NUM> may be coupled between a second supply terminal <NUM><NUM> and a second reference terminal GND<NUM> to receive a second supply voltage VDD2. The first device <NUM><NUM> and the second device <NUM><NUM> may be electrically isolated by a galvanic isolation barrier <NUM>, and may comprise means for transferring power <NUM> and/or data <NUM> between the two devices (i.e., across the isolation barrier <NUM>).

Known galvanic isolators are typically based on electromagnetic coupling (e.g., capacitive or inductive coupling) across a dielectric layer (i.e., the galvanic barrier). In certain cases, galvanic isolation can be obtained by providing package-scale isolation barriers. In other terms, packaging/assembling techniques and radio-frequency (RF) coupling between micro-antennas can be used to provide isolation and data communication. For instance, some RF galvanic isolators exploit wireless transmission between two stacked chips by means of silicon integrated near-field antennas, as disclosed by document <CIT> assigned to the Applicant of the instant application. To reduce the distance between stacked antennas, the dice can be also assembled face to face at the cost of fabricating through hole vias (THV) to have a rear side connection. However, the chip assembling complexity and package cost militate against a widespread adoption of this isolation technology. These drawbacks can be mitigated if the dice are placed side by side on the package substrate exploiting the magnetic coupling between coplanar antennas. In this case, the physical channel for data communication relies on the weak near-field coupling between two micro-antennas integrated on two side-by-side co-packaged chips, as illustrated in <FIG> (also known from document Ragonese et al. cited previously).

As exemplified in <FIG>, an isolated system <NUM> may comprise a first chip <NUM><NUM> and a second chip <NUM><NUM> arranged on respective electrically isolated die pads <NUM><NUM> and <NUM><NUM> in a (molded) package <NUM>. Each of the chips <NUM><NUM>, <NUM><NUM> comprises a respective planar micro-antenna <NUM><NUM>, <NUM><NUM>. In this approach, the distance through insulation (DTI), which determines the isolation rating, can be increased. Standard molding compounds have a dielectric strength (EM) of at least <NUM> V/µm, and therefore with a DTI of about <NUM> to <NUM>, an isolation rating higher than <NUM> kV can be achieved. Moreover, the intrinsic parasitic capacitance of the isolated channel can be reduced if compared with the ones of traditional chip-scale barriers (i.e., isolation capacitors or stacked transformers), thus reducing common mode (CM) currents produced by rapid ground shifts (i.e., CM transients).

<FIG> (also known from document Ragonese et al. cited previously) is a simplified circuit block diagram exemplary of an isolated data transfer channel of an isolated system (e.g., <NUM> or <NUM>), and <FIG> is exemplary of possible time behavior of electrical signals in the system.

Data transmission across a galvanic isolation barrier may rely on amplitude modulation of a radio-frequency (RF) carrier wave, in particular on on-off keying (OOK) pulse width modulation (PWM) of the RF carrier wave. A transmitting chip <NUM><NUM> comprises an input pin <NUM><NUM> for receiving an input digital signal IN carrying input data (e.g., a sequence of "<NUM>" or "<NUM>" bits), and a base-band interface <NUM><NUM> (e.g., a PWM modulator circuit) which receives the input digital signal IN and produces a corresponding input PWM signal PWMIN for driving a transmission front-end circuit <NUM><NUM>. For instance, the signal PWMIN may comprise periods with a low duty-cycle (e.g., <NUM>% or less) to encode a "<NUM>" bit value, and periods with a high duty-cycle (e.g., <NUM>% or more) to encode a "<NUM>" bit value, as exemplified in <FIG>. The transmission front-end circuit <NUM><NUM> modulates the amplitude of a radio-frequency carrier wave as a function of the PWM signal PWMIN (e.g., applying ASK modulation, in particular OOK modulation) to produce the transmission signal SRF which is then transmitted by a transmitting antenna <NUM><NUM> coupled to the transmission front-end circuit <NUM><NUM>. The receiving chip <NUM><NUM>, on the other side of the isolation barrier <NUM>, comprises a reception front-end circuit <NUM><NUM> coupled to the receiving antenna <NUM><NUM> to receive the transmission signal SRF therefrom. The reception front-end circuit <NUM><NUM> comprises an envelope detector circuit which detects the envelope of the transmission signal SRF to produce an output PWM signal PWMOUT. The output PWM signal PWMOUT is provided to a base-band interface <NUM><NUM> for data demodulation (e.g., a PWM demodulator circuit), which produces an output digital signal OUT at an output pin <NUM><NUM>.

Therefore, the front-end circuit <NUM><NUM> in the receiving chip <NUM><NUM> is configured to rectify (e.g., perform envelope detection) and amplify the low-level radio-frequency signal SRF received so as to convert it into a PWM low frequency signal PWMOUT, thereby allowing inter-chip data communication with two micro-antennas which transmit and receive, respectively, a carrier signal.

Document Ragonese et al. cited previously provides an example of such a receiving front-end circuit, as exemplified in <FIG> is a simplified circuit block diagram exemplary of an isolated data transfer channel, and <FIG> is a circuit block diagram exemplary of a portion of a corresponding receiving front-end circuit.

As exemplified in <FIG>, a receiving front-end circuit <NUM><NUM> may comprise a gain stage <NUM>, a mixer stage <NUM> coupled to the output of the gain stage <NUM>, and a low-pass filter stage <NUM> coupled to the output of the mixer stage <NUM>. The received radio-frequency signal SRF is first amplified at the gain stage <NUM> to obtain a signal having an amplitude suitable to drive the rectifier (e.g., amplifying the signal from about <NUM> mV amplitude to about <NUM> mV amplitude). The mixer stage <NUM> and the low-pass filter stage <NUM> (which together can be referred to as a rectifier stage in the context of the present description) then detect the envelope of the (amplified) input RF signal SRF and generate an envelope signal ENVOUT. The rectified (envelope) signal ENVOUT may be then compared to a threshold to generate the output PWM signal PWMOUT (the comparator circuit not being visible in the Figures annexed herein).

<FIG> is a circuit diagram exemplary of a rectifier stage as known from document Ragonese et al. cited previously: it consists of a differential amplifier with resistive load, with a double-balanced mixer based on a Gilbert cell. The output RC load of the mixer stage provides low-pass filtering to clean the RX signal envelope. Such a solution as disclosed by document Ragonese et al. cited previously is affected by a high current consumption due to both RF amplification and frequency limitations in the mixer-based rectifier.

Document <NPL>et al. hereinafter) discloses another example of an envelope detection circuit. However, that solution is not practical for use at low data rates, insofar as it cannot be fully integrated and needs external components.

Furthermore, envelope detection circuits according to the preamble of claim <NUM> are known from document<NPL>. Document <NPL> is similarly exemplary of the prior art.

Therefore, there is a need in the art to provide an envelope detector circuit capable of converting a low-level radio-frequency carrier signal in a low frequency PWM signal, particularly for low data rate applications.

An object of one or more embodiments is to contribute in providing such improved envelope detection circuits, e.g., for use in galvanic isolators, which can be fully integrated and operate at low data rates.

According to one or more embodiments, such an object can be achieved by means of a circuit (e.g., an envelope detection circuit) having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding receiver circuit.

One or more embodiments may relate to a corresponding galvanic isolator device.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

In one or more embodiments, a circuit may comprise a rectifier stage including a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load coupled between the intermediate node and a supply voltage node. The differential input transistor pair may be configured to receive a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal may be produced at the intermediate node. The circuit may comprise an amplifier stage coupled to the intermediate node to receive the rectified signal, and configured to produce at an output node an amplified rectified signal indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage may comprise a first resistive element coupled between the intermediate node and the supply voltage node in parallel to the load.

One or more embodiments may thus provide an envelope detector circuit which can operate at low data rates and can be fully integrated into a semiconductor chip.

Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

By way of introduction to the detailed description of exemplary embodiments, reference may first be made to <FIG>, which is a circuit diagram exemplary of a two-stage envelope detector circuit <NUM> suitable for use in an amplitude-shift keying (ASK) detector.

As exemplified in <FIG>, the envelope detector circuit <NUM> may comprise an input stage <NUM> and an output stage <NUM>.

The input stage <NUM> may comprise an input differential pair comprising two transistors (e.g., n-channel MOS transistors) M<NUM> and M<NUM>. The input radio-frequency signal SRF may be applied between the (gate) control terminals of the two transistors M<NUM> and M<NUM> of the differential pair. The transistors M<NUM>, M<NUM> may have their source terminals coupled to a reference voltage node GND and their drain terminals coupled to a common intermediate node <NUM>.

The input stage <NUM> may comprise a load coupled between the common intermediate node <NUM> and a supply node which provides a supply voltage Vcc. For instance, as exemplified in <FIG>, the load may comprise an active (e.g., self-biased) load including a transistor M<NUM> and a low-pass filter RF, CF. The transistor M<NUM> (e.g., a p-channel MOS transistor) may have its current path arranged between the common intermediate node <NUM> and the supply node Vcc. The low-pass filter may comprise a resistive element (e.g., a resistor RF) coupled between the common intermediate node <NUM> and the (gate) control terminal of the transistor M<NUM>, and a capacitive element (e.g., a capacitor CF) coupled between the (gate) control terminal of the transistor M<NUM> and the supply node Vcc.

The output stage <NUM> may comprise a common source or common emitter arrangement including a transistor M<NUM> and a resistive load RL, the transistor M<NUM> and the resistive load RL being coupled in series between the supply node Vcc and the reference voltage node GND. The transistor M<NUM> may have a (gate) control terminal coupled to the common intermediate node <NUM> (acting as the output node of the first stage <NUM>). An output node <NUM> intermediate the transistor M<NUM> and the resistive load RL may provide the envelope output signal ENVOUT. In particular, the transistor M<NUM> may be a p-channel MOS transistor having a source terminal coupled to the supply node Vcc and a drain terminal coupled to the output node <NUM>, and the resistive load RL may be coupled between the drain terminal of transistor M<NUM> and the reference voltage node GND.

Therefore, in an envelope detector circuit <NUM> as exemplified in <FIG>, the (on-off) modulated differential input signal SRF is first rectified and then amplified to produce an envelope signal ENVOUT. The output node <NUM> of the envelope detector circuit <NUM> may be coupled to a comparator circuit (not visible in the Figures annexed herein) so that the envelope signal ENVOUT is converted into a single-ended rail-to-rail PWM data signal PWMOUT.

It is noted that a circuit as exemplified in <FIG> can be fully integrated in a silicon die (only) for use in high data rate communications. The small-signal loop gain T and the loop gain-bandwidth product fGBW can be computed according to the equations below: <MAT> <MAT>.

Assuming, by way of example, a high data rate equal to fBR = <NUM> Mb/s, then fGBW = fBR/<NUM> = <NUM>, and assuming also RF = <NUM> kΩ this leads to CF = <NUM> pF which is a high value, but still feasible to integrate into a silicon die.

Assuming instead, again by way of example only, a low data rate equal to fBR = <NUM> kb/s, then fGBW = fBR/<NUM> = <NUM>, and assuming also RF = <NUM> kΩ this leads to CF = <NUM> nF which is a capacitance value too high to integrate into a silicon die.

Therefore, at low data rates an envelope detector circuit as exemplified in <FIG> may require an external component (e.g., an external capacitor CF).

One or more embodiments may thus relate to an improved envelope detector circuit suitable for use (also) at low data rates, as exemplified in <FIG>, which is a circuit diagram exemplary of a three-stage envelope detector circuit <NUM> suitable for use in an amplitude-shift keying (ASK) detector.

As exemplified in <FIG>, the envelope detector circuit <NUM> may comprise an input stage <NUM>, an intermediate stage <NUM> and an output stage <NUM>.

The input stage <NUM> may comprise an input differential pair comprising two transistors (e.g., n-channel MOS transistors) M<NUM> and M<NUM>. The input radio-frequency signal SRF may be applied between the (gate or base) control terminals of the two transistors M<NUM> and M<NUM> of the differential pair. The transistors M<NUM>, M<NUM> may have their source or emitter terminals coupled to a reference voltage node GND and their drain or collector terminals coupled to a common intermediate node <NUM>. The input stage <NUM> may further comprise a load coupled between the common intermediate node <NUM> and a supply node providing a supply voltage Vcc. For instance, as exemplified in <FIG>, the load may comprise an active (e.g., self-biased) load including a transistor M<NUM> and a low-pass filter RF, CF. The transistor M<NUM> (e.g., a p-channel MOS transistor) may have its current path arranged between the common intermediate node <NUM> and the supply node Vcc. The low-pass filter may comprise a resistive element (e.g., a resistor RF) coupled between the common intermediate node <NUM> and the (gate or base) control terminal of the transistor M<NUM>, and a capacitive element (e.g., a capacitor CF) coupled between the (gate or base) control terminal of the transistor M<NUM> and the supply node Vcc.

As exemplified in <FIG>, the input stage <NUM> may comprise a resistive element RL1 coupled in parallel to the active load, e.g., coupled between the common intermediate node <NUM> and the supply node Vcc. Arranging a further resistive element RL1 in the input stage <NUM> provides a further degree of freedom in the design of the envelope detector circuit <NUM>, so that the resistive element RF can be set (e.g., dimensioned) to reduce the loop gain-bandwidth product fGBW, which in turn facilitates implementing the capacitive element CF as an integrated component, while RL1 can be set (e.g., dimensioned) so as to determine the gain and output pole frequency of the input stage <NUM>, thus mitigating (e.g., avoiding) edge distortions on the output PWM signal.

The intermediate stage <NUM> may comprise a current matching circuit arrangement. As exemplified in <FIG>, the intermediate stage <NUM> may comprise a transistor M<NUM> (e.g., a p-channel MOS transistor) having a current path arranged between the supply node Vcc and a bias source <NUM>, and a control (gate or base) terminal coupled to the intermediate node <NUM> of the input stage <NUM>. A current I<NUM> flows through the transistor M<NUM>. For instance, the transistor M<NUM> may have a source or emitter terminal coupled to the supply node Vcc and a drain or collector terminal coupled to a further intermediate node <NUM>, and the bias source <NUM> may comprise a current generator arranged between the intermediate node <NUM> and the reference voltage node GND to sink a bias current Ib from the intermediate node <NUM> towards the reference voltage node GND.

Additionally, the intermediate stage <NUM> may comprise a resistive element RL2 coupled in parallel to the current path of transistor M<NUM>, e.g., coupled between the intermediate node <NUM> and the supply node Vcc. Arranging a resistive element RL2 in the intermediate stage <NUM> facilitates restoring the matching conditions between the first stage <NUM> (transistor M<NUM> and resistance RL1) and the second stage <NUM> (transistor M<NUM> and resistance RL2), thus improving the accuracy in the bias current I<NUM> of the output stage <NUM>.

The output stage <NUM> may comprise an amplifier stage, e.g., a folded amplifier stage. As exemplified in <FIG>, the output stage <NUM> may comprise a current mirror arrangement comprising a first transistor M<NUM> (e.g., a p-channel MOS transistor) and a second transistor M<NUM> (e.g., a p-channel MOS transistor). The first transistor M<NUM> may have a current path arranged between the supply node Vcc and the intermediate node <NUM>, through which a current I<NUM> = Ib - I<NUM> flows. The second transistor M<NUM> may be arranged in series to an output load RL3 (e.g., a resistive load) between the supply node Vcc and the reference voltage node GND, so that a copy of current I<NUM> flows through M<NUM> and RL3, thereby providing a single-ended output signal ENVOUT at the node <NUM> intermediate the transistor M<NUM> and the load RL3.

The folded amplifier comprising transistors M<NUM> and M<NUM> allows increasing the resistance value of the load RL3 and therefore the value of the second stage gain, insofar as the unipolar output signal ENVOUT becomes a positive voltage. Thus, the output bias voltage can be set to a value close to Vcc. Purely by way of non-limiting example, with Vcc = <NUM> V the resistance RL3 may be twice as big as the output load of a traditional configuration (e.g., RL in <FIG>), thereby providing an additional gain of about <NUM> dB.

The output node <NUM> of the envelope detector circuit <NUM> may be coupled to a comparator circuit (not visible in the Figures annexed herein) so that the envelope signal ENVOUT is converted into a single-ended rail-to-rail PWM data signal PWMOUT.

It is noted that one or more embodiments as exemplified in <FIG> can be fully integrated in a silicon die (also) for use in low data rate communications. The small-signal loop gain T and the loop gain-bandwidth product fGBW can be computed according to the equations below: <MAT> <MAT>.

Assuming, by way of example, a low data rate equal to fBR = <NUM> kb/s, then fGBW = fBR/<NUM> = <NUM>, and assuming also RF = <NUM> MΩ and RL1 = <NUM> kΩ this leads to CF = <NUM> pF which is a capacitance value which can be integrated into a silicon die.

One or more embodiments may be applied in a package-scale galvanic isolator device (e.g., as illustrated in <FIG>), where galvanic isolation can be implemented without using specific high voltage components, the inter-chip communication channel can be implemented by means of a wireless radio-frequency transmission, and appropriately choosing the distance between the two chips facilitates achieving high isolation rating (e.g., <NUM> to <NUM> kV for reinforced isolation) and/or higher common mode transient immunity, CMTI (e.g., higher than <NUM> kV).

However, those of skill in the art will understand that reference to a package-scale galvanic isolator device is made by way of example only, and that one or more embodiments may be generally applied to any kind of galvanic isolator device.

One or more embodiments have been disclosed herein with reference to specific implementations using complementary MOS technology. Those of skill in the art will understand that bipolar (BJT) technology can also be adopted as implementation technology for one or more embodiments, provided that it includes complementary transistors.

One or more embodiments may thus provide an envelope detector circuit which can be fully integrated in a single chip (also) for use at low data rates, e.g., without using passive discrete components to operate the circuit at low data rates. By way of example, such envelope detector circuits may operate at frequencies lower than <NUM> (e.g., in certain applications such as gate driver for motor control).

One or more embodiments may additionally provide one or more of the following advantages: high immunity to common mode transients, low current consumption, high gain, and low cost.

As exemplified herein, a circuit (e.g., <NUM>) may comprise a rectifier stage (e.g., <NUM>) including a differential input transistor pair (e.g., M<NUM>, M<NUM>) coupled between a reference voltage node (e.g., GND) and an intermediate node (e.g., <NUM>), and a load (e.g., M<NUM>, RF, CF) coupled between the intermediate node and a supply voltage node (e.g., Vcc). The differential input transistor pair may be configured to receive a radio-frequency amplitude modulated signal (e.g., SRF+, SRF-). A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal may be produced at the intermediate node. The circuit may comprise an amplifier stage (e.g., <NUM>; <NUM>) coupled to the intermediate node to receive the rectified signal and configured to produce at an output node (e.g., <NUM>) an amplified rectified signal (e.g., ENVOUT) indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage may further comprise a first resistive element (e.g., RL1) coupled between the intermediate node and the supply voltage node in parallel to the load.

As exemplified herein, the load may comprise an active load including a load transistor (e.g., M<NUM>) and a low-pass circuit arrangement (e.g., RF, CF).

As exemplified herein, the active load may comprise the load transistor having a current path coupled between the intermediate node and the supply voltage node, a second resistive element (e.g., RF) coupled between the intermediate node and a control terminal of the load transistor, and a capacitive element (e.g., CF) coupled between the control terminal of the load transistor and the supply voltage node.

As exemplified herein, the first resistive element may have a resistance value in the range of <NUM> kΩ to <NUM> kΩ, and the second resistive element may have a resistance value in the range of <NUM> MΩ to <NUM> MΩ. For instance, the first resistive element may be sized to correctly polarize the transistors M<NUM>, M<NUM> and together with the biasing current (e.g., <NUM>*Id1,<NUM> where Id is the current flowing through one of the transistors M<NUM>, M<NUM>) it may define the gain of the first stage. For instance, an amplitude gain in the range of <NUM> to <NUM> may be obtained.

As exemplified herein, the capacitive element may have a capacitance value in the range of <NUM> pF to <NUM> pF.

As exemplified herein, the differential input transistor pair may comprise a first input transistor (e.g., M<NUM>) and a second input transistor (e.g., M<NUM>) having the current paths therethrough arranged in parallel between the reference voltage node and the intermediate node, and the control terminals of the first input transistor and the second input transistor may be configured to receive the radio-frequency amplitude modulated signal therebetween.

As exemplified herein, the amplifier stage may comprise an output transistor (e.g., M<NUM>) arranged in a common source or common emitter configuration and an output load (e.g., RL3) coupled between a drain or collector terminal of the output transistor and the reference voltage node, and the output node may be intermediate the drain or collector terminal of the output transistor and the output load.

As exemplified herein, the amplifier stage may comprise:.

As exemplified herein, the control terminal of the current-mirroring transistor may be coupled to a control terminal of the output transistor.

As exemplified herein, the circuit may comprise a current-matching resistive element (e.g., RL2) coupled between the supply voltage node and the current control node.

As exemplified herein, the current-matching resistive element may have a resistance value in the range of <NUM> kΩ to <NUM> kΩ. For instance, the current-matching resistive element may be sized to correctly polarize the transistor M<NUM> and together with the biasing current Ib it may define the gain of the second stage.

As exemplified herein, the circuit may comprise a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse-width modulated output signal (e.g., PWMOUT) indicative of the envelope of the radio-frequency amplitude modulated signal.

As exemplified herein, a receiver circuit (e.g., <NUM><NUM>) may comprise:.

As exemplified herein, an isolator device (e.g., <NUM>) may comprise a transmitter circuit (e.g., <NUM><NUM>) configured to transmit a radio-frequency amplitude modulated signal, and a receiver circuit according to one or more embodiments, and the transmitter circuit and the receiver circuit may be isolated by a galvanic isolation barrier (e.g., <NUM>).

As exemplified herein, the transmitter circuit and the receiver circuit may be provided as separate chips arranged on respective electrically-isolated die pads (e.g., <NUM><NUM>, <NUM><NUM>), and the isolator device may further comprise a molded package (e.g., <NUM>) providing the galvanic isolation barrier.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

Claim 1:
A circuit (<NUM>), comprising:
a rectifier stage (<NUM>) including a differential input transistor pair (M<NUM>, M<NUM>) coupled between a reference voltage node (GND) and an intermediate node (<NUM>), and a load (M<NUM>, RF, CF) coupled between the intermediate node (<NUM>) and a supply voltage node (Vcc), the differential input transistor pair (M<NUM>, M<NUM>) being configured to receive a radio-frequency amplitude modulated signal (SRF+, SRF-), wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal (SRF+, SRF-) is produced at said intermediate node (<NUM>);
an amplifier stage (<NUM>; <NUM>) coupled to said intermediate node (<NUM>) to receive said rectified signal and configured to produce at an output node (<NUM>) an amplified rectified signal (ENVOUT) indicative of the envelope of said radio-frequency amplitude modulated signal (SRF+, SRF-),
wherein the rectifier stage (<NUM>) further comprises a first resistive element (RL1) coupled between said intermediate node (<NUM>) and said supply voltage node (Vcc) in parallel to said load (M<NUM>, RF, CF),
the circuit (<NUM>) being characterized in that said amplifier stage (<NUM>; <NUM>) comprises:
an output transistor (M<NUM>) arranged in a common source or common emitter configuration and an output load (RL3) coupled between a drain or collector terminal of said output transistor (M<NUM>) and said reference voltage node (GND), wherein said output node (<NUM>) is intermediate said drain or collector terminal of said output transistor (M<NUM>) and said output load (RL3);
a current-matching transistor (M<NUM>) having a current path arranged between said supply voltage node (Vcc) and a current control node (<NUM>), and a control terminal coupled to said intermediate node (<NUM>);
a bias source (<NUM>) coupled between said current control node (<NUM>) and said reference voltage node (GND) to sink a current (Ib) from said current control node (<NUM>); and
a current-mirroring transistor (M<NUM>) having a current path arranged between said supply voltage node (Vcc) and said current control node (<NUM>), and having a drain or collector terminal coupled to its control terminal,
and in that the control terminal of said current-mirroring transistor (M<NUM>) is coupled to a control terminal of said output transistor (M<NUM>).