Patent Description:
The following relates generally to memory array and more specifically to wear leveling for random access and ferroelectric memory.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory cell. For example, binary memory cells have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory cell. To store information, a component of the electronic device may write, or program, the state in the memory cell.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional (3D) cross-point memory (3D XPoint™ memory), 3D Not-AND (NAND) memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory devices, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. In some cases, however, limitations on memory cell reliability due to a limited program and erase cycling endurance capability may adversely impact performance and lifetime of the memory devices that customers experience.

<CIT> relates to an on-chip copy process which is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.

<CIT> relates to methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first "source" portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two. A second "target" portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using, for example, an address-scrambled reprogramming technique.

The disclosure herein refers to and includes the following figures:.

In a first aspect, the present invention provides a method as recited in claim <NUM>. In a second aspect, an electronic memory device as recited in claim <NUM> is provided.

Wear leveling may extend the usable life of non-volatile memory devices, e.g., FeRAM, that may exhibit a limited cycling capability. Wear leveling may distribute a number of program and erase cycles over a set of different memory cells (i.e., wear-leveling pool) to avoid causing a certain subset of memory cells corresponding to a logical address experiencing increased numbers of program and erase cycles when compared to the rest of the memory cells.

In wear-leveling application, the larger the wear-leveling pool, the more effective wear leveling may be. The wear-leveling pool may refer to a number of pages of an array that data circulates among. A page may refer to a number of data handled as a unit at various interfaces and may be related to a group of data associated with a word line common to a section of a memory array. For example, a typical size of a page in FeRAM may be <NUM> bytes. Other sizes of a page may be feasible, e.g., <NUM>, <NUM>, <NUM> bytes, etc. By way of example, if a wear-leveling pool is <NUM>,<NUM> pages, and if a customer hits one logical page continuously, those customer cycles may be spread over the <NUM>,<NUM> pages within the wear-leveling pool and thus the physical cycle counts each page experiences may be reduced by a factor of <NUM>,<NUM>. If on the other hand, the wear-leveling pool is <NUM>,<NUM> pages, then the physical cycle counts each page experiences may be reduced by a factor of <NUM>,<NUM>. Hence, there may be a motivation to facilitate wear leveling over a larger size of wear-leveling pool to mitigate risks associated with the limited cycling capability that non-volatile memory devices may exhibit.

In wear-leveling application, a page copy operation may be performed in which contents of one page (i.e., source page) is copied from a section of a memory array and moved to another page (i.e., destination page). During the page copy operation a set of sense components and latches that are common to the source and the destination pages may be used, which may necessitate that the source and the destination pages are restricted to be present in the same section configured with the common set of sense components and latches. Such restriction may limit a size of wear-leveling pool thereby inhibiting advantages of having a larger size of wear-leveling pool.

Another consideration in wear-leveling applications may relate to one or more error bits that may be present in contents of a source page. When contents of the source page including error bits is copied to a destination page, contents of the destination page may include the duplicated error bits, which in turn, may result in reduced error correction capacity allocated to the destination page. This issue may be referred to as an error propagation problem. A certain number of error bits associated with a page may be corrected by scrubbing contents of the page through error correction code (ECC) logic. ECC logic is present on a chip with a memory array. In some cases, ECC logic may be configured to perform ECC function to data sets from any section within a bank-level logic of the memory array. Hence, the contents of the source page may be brought beyond the set of sense components and latches associated with the section of the memory array for the ECC logic to correct the error bit(s) that may be present in the contents of the source page to avoid the error propagation problem.

Techniques are described herein that support wear leveling for random access and ferroelectric memory, which may provide advantage of expanding a size of wear-leveling pool while consuming less power and reducing certain delay times, e.g., row refresh time (tRFC). In addition, error correction may be accomplished while moving contents of a page from a source page to a destination page during wear-leveling applications. As used herein, the techniques are described using ferroelectric memory cells with three access lines, namely plate line, digit line, and word line in conjunction with other support circuitry components (e.g., sense components, latches, ECC logic, internal logic circuit, etc.). Some of the support circuitry components may be placed under multi-decks of array of ferroelectric memory cells, namely as a part of complementary metal oxide semiconductor (CMOS) under the array, in some examples.

Features of the disclosure introduced above are further described below in the context of memory device. Specific examples are then described for memory array and memory portions that relate to wear leveling for random access and ferroelectric memory. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to wear leveling for random access and ferroelectric memory.

<FIG> illustrates an example of a diagram of memory device <NUM> having an array of memory cells that supports wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. <FIG> is an illustrative schematic representation of various components and features of memory device <NUM>, and thus may not show other components. As such, it should be appreciated that the components and feature of memory device <NUM> are shown to illustrate functional interrelationships supporting wear leveling for random access and ferroelectric memory, not their actual physical positions within memory device100. Memory device <NUM> may also be referred to as an electronic memory apparatus. Memory device <NUM> includes an array of memory cells <NUM> that are programmable to store different states. The array of memory cells <NUM> may be referred to as memory array, memory core, and the like. Memory cell <NUM> is a ferroelectric memory cell that may include a capacitor with a ferroelectric material as the insulating material. In some cases, the capacitor may be referred to as a ferroelectric container. Each memory cell <NUM> may be programmable to store two states, denoted as a logic <NUM> and a logic <NUM>. Each memory cell <NUM> may be stacked on top of each other resulting in two-decks of memory cell <NUM>. Hence, the example in <FIG> may be an example that depicts two decks of memory array for illustrative purposes only. In some examples, single deck of memory array may support wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure.

In some cases, memory cells <NUM> are configured to store more than two logic states. A memory cell <NUM> may store a charge representative of the programmable states in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may commonly use such a design, and the capacitor employed may include a dielectric material with paraelectric or linear polarization properties as the insulator. By contrast, a ferroelectric memory cell may include a capacitor with a ferroelectric material as the insulating material. Different levels of charges of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have non-linear polarization properties; some details and advantages of a ferroelectric memory cell <NUM> are discussed below.

Operations such as reading and writing, which may be referred to as access operations, may be performed on memory cells <NUM> by activating or selecting word line <NUM> and digit line <NUM>. Word lines <NUM> may also be known as row lines, sense lines, or access lines. Digit lines <NUM> may also be known as bit lines, column lines, or access lines. References to word lines and digit lines, or their analogues, are interchangeable without loss of understanding or logical operation. Word lines <NUM> and digit lines <NUM> may be perpendicular (or nearly perpendicular) to one another to create an array of memory cells. Depending on the type of memory cell (e.g., FeRAM, RRAM, etc.), other access lines may be present (not shown), such as plate lines, for example. It should be appreciated that the exact operation of the memory device may be altered based on the type of memory cell and/or the specific access lines used in the memory device.

Activating or selecting a word line <NUM> or a digit line <NUM> may include applying a voltage to the respective line. Word lines <NUM> and digit lines <NUM> may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), metal alloys, carbon, conductively-doped semiconductors, or other conductive materials, alloys, compounds, or the like.

According to the example of <FIG>, each row of memory cells <NUM> is connected to a single word line <NUM>, and each column of memory cells <NUM> is connected to a single digit line <NUM>. By activating one word line <NUM> and one digit line <NUM> (e.g., applying a voltage to the word line <NUM> or digit line <NUM>), a single memory cell <NUM> may be accessed at their intersection. Accessing the memory cell <NUM> may include reading or writing the memory cell <NUM>. The intersection of a word line <NUM> and digit line <NUM> may be referred to as an address of a memory cell.

In some architectures, the logic storing device of a cell, e.g., a capacitor, may be electrically isolated from the digit line by a selector device. The word line <NUM> may be connected to and may control the selector device. For example, the selector device may be a transistor (e.g., thin-film transistor (TFT) or metal-oxide-semiconductor (MOS) transistor) and the word line <NUM> may be connected to the gate of the transistor. Activating the word line <NUM> results in an electrical connection or closed circuit between the capacitor of a memory cell <NUM> and its corresponding digit line <NUM>. The digit line may then be accessed to either read or write the memory cell <NUM>. In addition, as described below in <FIG>, access operation of ferroelectric memory cells may need an additional connection to a node of the ferroelectric memory cell, namely cell plate (CP) node via plate line.

Accessing memory cells <NUM> may be controlled through a row decoder <NUM> and a column decoder <NUM>. For example, a row decoder <NUM> may receive a row address from a memory controller <NUM> and activate the appropriate word line <NUM> based on the received row address. Similarly, a column decoder <NUM> receives a column address from the memory controller <NUM> and activates the appropriate digit line <NUM>. For example, memory device <NUM> may include multiple word lines <NUM>, labeled WL_1 through WL_M, and multiple digit lines <NUM>, labeled DL_1 through DL_N, where M and N depend on the array size. Thus, by activating a word line <NUM> and a digit line <NUM>, e.g., WL_2 and DL_3, the memory cell <NUM> at their intersection may be accessed. In addition, access operation of ferroelectric memory cells may need to activate a corresponding plate line for the memory cell <NUM>, associated with plate line decoder (not shown).

Upon accessing, a memory cell <NUM> may be read, or sensed, by sense component <NUM> to determine the stored state of the memory cell <NUM>. For example, after accessing the memory cell <NUM>, the ferroelectric capacitor of memory cell <NUM> may discharge onto its corresponding digit line <NUM>. Discharging the ferroelectric capacitor may result from biasing, or applying a voltage, to the ferroelectric capacitor. The discharging may cause a change in the voltage of the digit line <NUM>, which sense component <NUM> may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell <NUM>. For example, if digit line <NUM> has a higher voltage than the reference voltage, then sense component <NUM> may determine that the stored state in memory cell <NUM> was a logic <NUM> and vice versa. Sense component <NUM> may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. In some cases, latch <NUM> may store the logic state of memory cell <NUM> that sense component detects during wear-leveling operations in accordance with embodiments of the present disclosure. The detected logic state of memory cell <NUM> may then be output through column decoder <NUM> as output <NUM>. In some cases, sense component <NUM> may be part of a column decoder <NUM> or row decoder <NUM>. Or, sense component <NUM> may be connected to or in electronic communication with column decoder <NUM> or row decoder <NUM>.

A memory cell <NUM> may be set, or written, by similarly activating the relevant word line <NUM> and digit line <NUM>-i.e., a logic value may be stored in the memory cell <NUM>. Column decoder <NUM> or row decoder <NUM> may accept data, for example input/output <NUM>, to be written to the memory cells <NUM>. A ferroelectric memory cell <NUM> may be written by applying a voltage across the ferroelectric capacitor. This process is discussed in more detail below.

In some memory architectures, accessing the memory cell <NUM> may degrade or destroy the stored logic state and re-write or refresh operations may be performed to return the original logic state to memory cell <NUM>. In DRAM, for example, the capacitor may be partially or completely discharged during a sense operation, corrupting the stored logic state. So the logic state may be re-written after a sense operation. In some cases, the writing the logic state back to the memory cells <NUM> may be referred to as pre-charging. Additionally, activating a single word line <NUM> may result in the discharge of all memory cells in the row; thus, several or all memory cells <NUM> in the row may need to be re-written or pre-charged.

In some memory architectures, including DRAM, memory cells may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery. As discussed below, ferroelectric memory cells <NUM> may have beneficial properties that may result in improved performance relative to other memory architectures.

The memory controller <NUM> may control the operation (e.g., read, write, re-write, refresh, discharge, pre-charge, etc.) of memory cells <NUM> through the various components, for example, row decoder <NUM>, column decoder <NUM>, sense component <NUM>, and latch <NUM>. The memory controller <NUM> may also control operations associated with wear leveling and ECC function in conjunction with ECC logic during wear-leveling operations in accordance with embodiments of the present disclosure. The memory controller <NUM> may be an internal logic circuit present on the same substrate with the memory array. In some cases, one or more of the row decoder <NUM>, column decoder <NUM>, sense component <NUM>, and latch <NUM> may be co-located with the memory controller <NUM>. Memory controller <NUM> may generate row and column address signals in order to activate the desired word line <NUM> and digit line <NUM>. Memory controller <NUM> may also generate and control various voltages or currents used during the operation of memory device <NUM>. For example, it may apply discharge voltages to a word line <NUM> or digit line <NUM> after accessing one or more memory cells <NUM>.

In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating memory device <NUM>. Furthermore, one, multiple, or all memory cells <NUM> within memory device <NUM> may be accessed simultaneously; for example, multiple or all cells of memory device <NUM> may be accessed simultaneously during an access (or write or program) operation in which all memory cells <NUM>, or a group of memory cells <NUM>, are set or reset to a single logic state. It should be appreciated that the exact operation of the memory device may be altered based on the type of memory cell and/or the specific access lines used in the memory device. In some examples where other access lines e.g., plate lines, may be present (not shown), a corresponding plate line in collaboration with a word line and a digit line may need to be activated to access a certain memory cell <NUM> of the memory array. It should be appreciated that the exact operation of the memory device may vary based on the type of memory cell and/or the specific access lines used in the memory device.

<FIG> illustrates an example of a ferroelectric memory cell and circuit components that supports wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. Circuit <NUM> includes a memory cell <NUM>-a, word line <NUM>-a, digit line <NUM>-a, sense component <NUM>-a, ISO device <NUM>, and latch <NUM>-a, which may be examples of a memory cell <NUM>, word line <NUM>, digit line <NUM>, sense component <NUM>, and latch <NUM>, respectively, as described with reference to <FIG>. Memory cell <NUM>-a may include a logic storage component, such as capacitor <NUM> that has a first plate, cell plate <NUM>, and a second plate, cell bottom <NUM>. Cell plate <NUM> and cell bottom <NUM> may be capacitively coupled through a ferroelectric material positioned between them. The orientation of cell plate <NUM> and cell bottom <NUM> may be flipped without changing the operation of memory cell <NUM>-a. Circuit <NUM> also includes selector device <NUM> and reference line <NUM>. Cell plate <NUM> may be accessed via plate line <NUM> (PL) and cell bottom <NUM> may be accessed via digit line <NUM>-a (DL). As described above, various states may be stored by charging or discharging capacitor <NUM>.

The stored state of capacitor <NUM> may be read or sensed by operating various elements represented in circuit <NUM>. Capacitor <NUM> may be in electronic communication with digit line <NUM>-a. For example, capacitor <NUM> can be isolated from digit line <NUM>-a when selector device <NUM> is deactivated, and capacitor <NUM> can be connected to digit line <NUM>-a when selector device <NUM> is activated. Activating selector device <NUM> may be referred to as selecting memory cell <NUM>-a. In some cases, selector device <NUM> is a transistor (e.g., thin-film transistor (TFT) or metal-oxide-semiconductor (MOS) transistor) and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold voltage magnitude of the transistor. Word line <NUM>-a (WL) may activate selector device <NUM>; for example, a voltage applied to word line <NUM>-a is applied to the transistor gate, connecting capacitor <NUM> with digit line <NUM>-a.

In other examples, the positions of selector device <NUM> and capacitor <NUM> may be switched, such that selector device <NUM> is connected between plate line <NUM> and cell plate <NUM> and such that capacitor <NUM> is between digit line <NUM>-a and the other terminal of selector device <NUM>. In this embodiment, selector device <NUM> may remain in electronic communication with digit line <NUM>-a through capacitor <NUM>. This configuration may be associated with alternative timing and biasing for read and write operations.

Due to the ferroelectric material between the plates of capacitor <NUM>, and as discussed in more detail below, capacitor <NUM> may not discharge upon connection to digit line <NUM>-a. In one scheme, to sense the logic state stored by ferroelectric capacitor <NUM>, word line <NUM>-a may be biased to select memory cell <NUM>-a and a voltage may be applied to plate line <NUM>. In some cases, digit line <NUM>-a is virtually grounded and then isolated from the virtual ground, which may be referred to as "floating," prior to biasing plate line <NUM> and word line <NUM>-a. Biasing plate line <NUM> may result in a voltage difference (e.g., plate line <NUM> voltage minus digit line <NUM>-a voltage) across capacitor <NUM>. The voltage difference may yield a change in the stored charge on capacitor <NUM>, where the magnitude of the change in stored charge may depend on the initial state of capacitor <NUM>-e.g., whether the initial state stored a logic <NUM> or a logic <NUM>. This may cause a change in the voltage of digit line <NUM>-a based on the charge stored on capacitor <NUM>. Operation of memory cell <NUM>-a by varying the voltage to cell plate <NUM> may be referred to as "moving cell plate.

The change in voltage of digit line <NUM>-a may depend on its intrinsic capacitance. That is, as charge flows through digit line <NUM>-a, some finite charge may be stored in digit line <NUM>-a and the resulting voltage may depend on the intrinsic capacitance. The intrinsic capacitance may depend on physical characteristics, including the dimensions, of digit line <NUM>-a. Digit line <NUM>-a may connect many memory cells <NUM> so digit line <NUM>-a may have a length that results in a non-negligible capacitance (e.g., on the order of picofarads (pF)). The resulting voltage of digit line <NUM>-a may then be compared to a reference (e.g., a voltage of reference line <NUM>) by sense component <NUM>-a in order to determine the stored logic state in memory cell <NUM>-a. Other sensing processes may be used.

Sense component <NUM>-a may include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. Sense component <NUM>-a may include a sense amplifier that receives and compares the voltage of digit line <NUM>-a and reference line <NUM>, which may be a reference voltage. The sense amplifier output may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For instance, if digit line <NUM>-a has a higher voltage than reference line <NUM>, then the sense amplifier output may be driven to a positive supply voltage. In some cases, the sense amplifier may additionally drive digit line <NUM>-a to the supply voltage. Sense component <NUM>-a may then latch the output of the sense amplifier and/or the voltage of digit line <NUM>-a, which may be used to determine the stored state in memory cell <NUM>-a, e.g., logic <NUM>. Alternatively, if digit line <NUM>-a has a lower voltage than reference line <NUM>, the sense amplifier output may be driven to a negative or ground voltage. Sense component <NUM>-a may similarly latch the sense amplifier output to determine the stored state in memory cell <NUM>-a, e.g., logic <NUM>. The latched logic state of memory cell <NUM>-a may then be output, for example, through column decoder <NUM> as output <NUM> with reference to <FIG>. In some cases, latch <NUM>-a may include various transistors and other circuit elements to store the logic state of memory cell <NUM> that sense component <NUM>-a detects.

ISO device <NUM>, during wear-leveling operation for random access and ferroelectric memory in accordance with embodiments of the present disclosure, may isolate the digit line nodes of sense component <NUM> from digit line <NUM>-a (DL) of memory cell <NUM>-a. When the sense component <NUM> is isolated from the memory cell <NUM>-a, the memory cells may be programmed or pre-written to a logic state while other operations are on-going. Hence, when memory cells associated with a page are isolated, entire memory cells of the page may be pre-written to a single logic state during wear-leveling application. Memory cells may be pre-written a single logic state to reduce (or "hide," at least in part) the time delay involved when writing a cell or group of cells. The time delay reduction may be achieved due to an inherent asymmetric nature of cell programming or a reduced net amount of data to be programmed, or combination of both. For example, programing a logic state of <NUM> may be faster than programming a logic state of <NUM> in ferroelectric memory cells. In addition, a memory cell may need to be programmed only when the data (e.g., a logic state of <NUM>) to be stored in the memory cell is different than the pre-written data (e.g., a logic state of <NUM>). ISO device <NUM> enables at least two or more steps to operate in parallel during wear-leveling operation as described below.

To write memory cell <NUM>-a, a voltage may be applied across capacitor <NUM>. Various methods may be used. In one example, selector device <NUM> may be activated through word line <NUM>-a in order to electrically connect capacitor <NUM> to digit line <NUM>-a. A voltage may be applied across capacitor <NUM> by controlling the voltage of cell plate <NUM> by CP driver <NUM> (through plate line <NUM>) and cell bottom <NUM> (through digit line <NUM>-a). To write a logic <NUM>, cell plate <NUM> may be taken high, that is, a positive voltage may be applied to plate line <NUM> by CP driver <NUM> (through plate line <NUM>), and cell bottom <NUM> may be taken low, e.g., virtually grounding or applying a negative voltage to digit line <NUM>-a. The opposite process is performed to write a logic <NUM>, where cell plate <NUM> is taken low and cell bottom <NUM> is taken high.

<FIG> illustrates an example of non-linear electrical properties with hysteresis curves <NUM>-a and <NUM>-b for a ferroelectric memory cell that supports wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. Hysteresis curves <NUM>-a and <NUM>-b illustrate an example ferroelectric memory cell writing and reading process, respectively. Hysteresis curves <NUM> depict the charge, Q, stored on a ferroelectric capacitor (e.g., capacitor <NUM> of <FIG>) as a function of a voltage difference, V, across the ferroelectric capacitor.

A ferroelectric material is characterized by a spontaneous electric polarization, i.e., it maintains a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO<NUM>), lead titanate (PbTiO<NUM>), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electric polarization within a ferroelectric capacitor results in a net charge at the ferroelectric material's surface and attracts opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization may be maintained in the absence of an externally applied electric field for relatively long times, even indefinitely, charge leakage may be significantly decreased as compared with, for example, capacitors employed in DRAM arrays. This may reduce the need to perform refresh operations as described above for some DRAM architectures.

Hysteresis curves <NUM> may be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis curves <NUM> represent a voltage difference across the capacitor and are directional. For example, a positive voltage may be realized by applying a positive voltage to the terminal in question (e.g., a cell plate <NUM>) and maintaining the second terminal (e.g., a cell bottom <NUM>) at ground (or approximately zero volts (0V)). A negative voltage may be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal-i.e., positive voltages may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference shown in hysteresis curves <NUM>.

As depicted in hysteresis curve <NUM>, the ferroelectric material may maintain a positive or negative polarization with a zero voltage difference, resulting in two possible charged states: charge state <NUM> and charge state <NUM>. According to the example of <FIG>, charge state <NUM> represents a logic <NUM> and charge state <NUM> represents a logic <NUM>. In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating a memory cell.

A logic <NUM> or <NUM> may be written to the memory cell by controlling the electric polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying voltage. For example, applying a net positive voltage <NUM> across the capacitor results in charge accumulation until charge state <NUM>-a is reached. Upon removing voltage <NUM>, charge state <NUM>-a follows path <NUM> until it reaches charge state <NUM> at zero voltage. Similarly, charge state <NUM> is written by applying a net negative voltage <NUM>, which results in charge state <NUM>-a. After removing negative voltage <NUM>, charge state <NUM>-a follows path <NUM> until it reaches charge state <NUM> at zero voltage. Charge states <NUM>-a and <NUM>-a may also be referred to as the remnant polarization (Pr) values, i.e., the polarization (or charge) that remains upon removing the external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

To read, or sense, the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge, Q, changes, and the degree of the change depends on the initial charge state - i.e., the final stored charge (Q) depends on whether charge state <NUM>-b or <NUM>-b was initially stored. For example, hysteresis curve <NUM>-b illustrates two possible stored charge states <NUM>-b and <NUM>-b. Voltage <NUM> may be applied across the capacitor as discussed with reference to <FIG>. In other cases, a fixed voltage may be applied to the cell plate and, although depicted as a positive voltage, voltage <NUM> may be negative. In response to voltage <NUM>, charge state <NUM>-b may follow path <NUM>. Likewise, if charge state <NUM>-b was initially stored, then it follows path <NUM>. The final position of charge state <NUM>-c and charge state <NUM>-c depend on a number of factors, including the specific sensing scheme and circuitry.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if the capacitor is electrically connected to the digit line and voltage <NUM> is applied, the voltage of the digit line may rise due to its intrinsic capacitance. So a voltage measured at a sense component may not be equal to voltage <NUM> and instead may depend on the voltage of the digit line. The position of final charge states <NUM>-c and <NUM>-c on hysteresis curve <NUM>-b may thus depend on the capacitance of the digit line and may be determined through a load-line analysis-i.e., charge states <NUM>-c and <NUM>-c may be defined with respect to the digit line capacitance. As a result, the voltage of the capacitor, voltage <NUM> or voltage <NUM>, may be different and may depend on the initial state of the capacitor.

By comparing the digit line voltage to a reference voltage, the initial state of the capacitor may be determined. The digit line voltage may be the difference between voltage <NUM> and the final voltage across the capacitor, voltage <NUM> or voltage <NUM>-i.e., (voltage <NUM> - voltage <NUM>) or (voltage <NUM> - voltage <NUM>). A reference voltage may be generated such that its magnitude is between the two possible voltages of the two possible digit line voltages in order to determine the stored logic state-i.e., if the digit line voltage is higher or lower than the reference voltage. For example, the reference voltage may be an average of the two quantities, (voltage <NUM> - voltage <NUM>) and (voltage <NUM> - voltage <NUM>). Upon comparison by the sense component, the sensed digit line voltage may be determined to be higher or lower than the reference voltage, and the stored logic value of the ferroelectric memory cell (i.e., a logic <NUM> or <NUM>) may be determined.

As discussed above, reading a memory cell that does not use a ferroelectric capacitor may degrade or destroy the stored logic state. A ferroelectric memory cell, however, may maintain the initial logic state after a read operation. For example, if charge state <NUM>-b is stored, the charge state may follow path <NUM> to charge state <NUM>-c during a read operation and, after removing voltage <NUM>, the charge state may return to initial charge state <NUM>-b by following path <NUM> in the opposite direction. During wear-leveling operation in accordance with embodiments of the present disclosure, FeRAM memory cells may be pre-written a single logic state to reduce (or "hide" to a host or application) the time delay involved when writing a cell or group of cells. In some examples, FeRAM memory cells in a destination page may be pre-written with a logic state <NUM>. Subsequently, a FeRAM memory cell in the destination page may need to be programmed only when the data (e.g., a logic state of <NUM>) to be stored in the FeRAM memory cell is different than the pre-written data (e.g., a logic state of <NUM>) to accomplish a fast execution of wear-leveling operation with reduced energy consumption.

<FIG> illustrates diagrams of operations that support wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. Diagrams <NUM> includes memory tile <NUM>, sense part <NUM>, source page <NUM>, destination page <NUM>, and error correction code (ECC) logic <NUM>. Source page <NUM> and destination page <NUM> may or may not be present in a same memory tile.

Memory tile <NUM> may be configured to include various numbers of memory cells. In some cases, a memory tile <NUM> may include <NUM> x <NUM> memory cells arranged in two-dimensional matrix. Other configurations of a memory tile, e.g., <NUM> x <NUM> or <NUM> x <NUM> memory cells, may be feasible. In some cases, a horizontal arrangement of memory tile <NUM> may be referred to as a section of a memory array (not shown). In some cases, the horizontal direction may be in word line direction. In some cases, a vertical arrangement of the sections (i.e., a two-dimensional arrangement of tiles) may be referred to as a bank of memory array (not shown). In some cases, the vertical direction may be in digit line direction.

Sense part <NUM> may include a sense component and a latch. The sense component in the sense part <NUM> may be an example of sense component <NUM> as described with reference to <FIG> and <FIG>. The latch in the sense part <NUM> may be an example of latch <NUM> as describe with reference to <FIG> and <FIG>. In some cases, a sense part <NUM> may be associated with a section of a memory array. As an example, sense part <NUM>-e may be configured to sense a section associated with memory tile <NUM>-c and may not be configured to sense other sections of the memory array (e.g., memory tile <NUM>-d). Sense part <NUM> may be located on one side or both sides of memory tile <NUM> in vertical or digit line direction.

ECC logic <NUM> is located on a chip with a memory array. ECC logic <NUM> may include various transistors and other circuit elements that are configured to detect and correct a certain number of errors that may be present in a data set. ECC logic <NUM> may be configured to perform ECC function on data sets from any section of a bank-level logic of the memory array (e.g., memory tile <NUM>-c or memory tile <NUM>-d). In some cases, ECC logic <NUM> may be configured to perform ECC function on a subset of data from a page of data. The subset of data on which ECC logic <NUM> performs ECC function may be referred to as a code-word.

As shown in diagram <NUM>-a and <NUM>-b, both source page <NUM> and destination page <NUM> may be located within a same tile (e.g., memory tile <NUM>-a or <NUM>-b), hence the same section (not shown) of the memory array. Source page <NUM> may include memory cells (i.e., memory cells from which data is copied during wear-leveling operation) associated with a word line common to the memory cells. In some cases, source page <NUM> may include a row of <NUM> memory cells connected to a word line as described with reference to <FIG> and <FIG>. Each of the <NUM> memory cells may be associated with a digit line that may be connected to sense part <NUM> as described with reference to <FIG> and <FIG>. Destination page <NUM> may include the same number of memory cells (i.e., memory cells to which data is copied during wear-leveling operation) with source page (e.g., a row of <NUM> memory cells) associated with another word line commonly configured for the memory cells. Memory cells in source page <NUM> and memory cells in destination page <NUM> may be associated with common bit lines as described with reference to <FIG> and <FIG>.

Diagram <NUM>-a may illustrate an example of page copy operation performed during wear-leveling operation. Source page <NUM>-a may be activated (i.e., the word line and the digit lines associated with source page <NUM>-a are selected or turned on) to capture data stored in source page <NUM>-a at sense part <NUM>-a and/or <NUM>-b. Decoding, sensing and capturing of data may be performed according to procedures as described above with reference to <FIG>. Capturing of data from source page <NUM>-a to sense part <NUM>-a may be illustrated with path <NUM>-a. Capturing of data from source page <NUM>-a to sense part <NUM>-b is omitted for simplicity of illustration.

Based on capturing of the data from source page <NUM>-a in sense part <NUM>-a and/or <NUM>-b, for example, the word line and the digit lines associated with source page <NUM>-a may be deselected, or turned off. Based on turning off the word line and the digit lines associated with source page <NUM>-a, a word line and digit lines associated with destination page <NUM>-a may be selected or turned on. Based on turning on the word line and digit lines associated with destination page <NUM>-a, i.e., having destination page <NUM>-a enabled, the data stored or captured in sense part <NUM>-a and/or <NUM>-b may be written to memory cells in destination page <NUM>-a. In some cases, writing data from sense part <NUM>-a and/or <NUM>-b to destination page <NUM>-a may be referred to as pre-charging destination page <NUM>-a. Writing of data from sense part <NUM>-a to destination page <NUM>-a, i.e., pre-charging destination page <NUM>-a, may be illustrated with path <NUM>-a. Writing of data from sense part <NUM>-b to destination page <NUM>-a is omitted for simplicity of illustration.

The sequence described above may move data from source page <NUM>-a to destination page <NUM>-a during wear-leveling operation. Sense part <NUM>-a and/or <NUM>-b may facilitate the sequence of moving the data. The sequence avoids a particular physical page (e.g., the source page <NUM>-a) from being repeatedly cycled (e.g., programming and erasure of memory cells in source page <NUM>-a) by utilizing another physical page (e.g., memory cells in destination page <NUM>-a) so as to effectively spread the cycling events over a number of pages in a wear-leveling pool (e.g., <NUM> different physical page locations). A logical address of the data may remain the same regardless of a physical location of the page where the data actually reside within the wear-leveling pool. Due to absence of pre-charging of source page <NUM>-a after capturing the data therefrom, the data present in source page <NUM>-a may be no longer valid or reliable. In the wear-leveling application, the source page <NUM>-a may become a new spare page, i.e., a memory page available to serve as a destination page.

As illustrated in diagram <NUM>-a, utilizing sense part <NUM>-a and/or <NUM>-b may enable wear-leveling operation within a section but the wear-leveling pool may be restricted among the pages present in the section (e.g., <NUM> pages) because the sense part <NUM> is configured to be dedicated for the memory cells of the section.

Diagram <NUM>-b may illustrate the movement of data involved in the sequence described above during wear-leveling operation when error(s) may be present in source page <NUM>-b. Error(s) may be associated with contents of defective or erroneous memory cell(s) in a page. Error(s) is depicted as a symbol X in diagram <NUM>-b. Wear-leveling operation involves the same sequence as described above with reference to diagram <NUM>-a. Capturing of data including error(s) from source page <NUM>-b to sense part <NUM>-c may be illustrated with path <NUM>-b. Writing of data including error(s) from sense part <NUM>-c to destination page <NUM>-b, i.e., pre-charging destination page <NUM>-b, may be illustrated with path <NUM>-b. In the example of diagram <NUM>-b, the error(s) may be copied as a part of data from source page <NUM>-b to destination page <NUM>-b. Such propagation of error may consume error correction capability associated with destination page <NUM>-b because destination page <NUM>-b may have its own error(s) due to defective or erroneous memory cell(s). Error correction operation may have corrected the contents of defective or erroneous memory cell(s) in source page <NUM>-b prior to storing the contents of source page <NUM>-b to destination page <NUM>-b.

Diagram <NUM>-c may illustrate the movement of data involved in another sequence during wear-leveling operation in conjunction with ECC logic <NUM> to correct error(s) that may be present in source page <NUM>-c, as indicated by symbol X. After the data including error(s) from source page <NUM>-c is sensed and captured in sense part <NUM>-e, as indicated by path <NUM>-c, a subset of the data from source page <NUM>-c may be sent from sense part <NUM>-e to ECC logic <NUM> and "scrubbed" by ECC logic <NUM>, one at a time. In some cases, the subset may be a code-word (e.g., a part of a page). Scrubbing may mean processing each code-word through ECC logic <NUM> and correcting errors that may be present in the code-word, as indicated by path <NUM>-c. By way of example, if there were eight (<NUM>) code-words per page, each code-word may be brought out from sense part <NUM>-e, processed through ECC logic <NUM>. Hence, this portion of sequence performing ECC function via ECC logic <NUM> may be performed in a loop of eight sequences or operations.

Scrubbing the data captured in sense part <NUM>-e may involve processing each code-word through ECC logic <NUM>. This may limit the benefits associated with keeping a source page <NUM> and a destination page <NUM> within the same section (e.g., a tile <NUM>) as illustrated in diagrams <NUM>-a and <NUM>-b because of data traffic operations beyond a section level to reach ECC logic <NUM> that may be present in a bank-level logic of a memory array. However, a size of wear-leveling pool may be increased when a page copy operation may be achieved across different sections because the larger the wear-leveling pool, the more effective wear leveling may be. Thus, while scrubbing may be performed by processing each code-word through ECC logic <NUM>, each code-word scrubbed by ECC logic <NUM> may be saved at sense part <NUM>-g associated with tile <NUM>-d as indicated by path <NUM>-c.

Tile <NUM>-d may be a different tile including destination page <NUM>-c and associated with sense part <NUM>-g or <NUM>-h. Subsequently, the data in sense part <NUM>-g, which has been scrubbed by ECC logic <NUM>, may be saved in destination page <NUM>-c in tile <NUM>-d, as indicated by path <NUM>-c. As a result, the contents of source page <NUM>-c, with its errors corrected via ECC logic <NUM>, may be transferred to destination page <NUM>-c that may be present in a different section of memory array. Due to the error correction function performed by ECC logic <NUM>, the contents of data being stored in destination page <NUM>-c may be free from the errors, as indicated by absence of symbol X in destination page <NUM>-c. More details of wear-leveling operations as described with reference to diagram <NUM>-c in accordance with embodiments of the present disclosure are explained in <FIG> and <FIG> below.

<FIG> and <FIG> illustrate operations that support wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. Diagram <NUM> includes memory tiles <NUM>, sense parts <NUM>, source page <NUM>, destination page <NUM>, and ECC logic <NUM>.

Memory tiles <NUM> may be an example of memory tiles <NUM> as described with reference to <FIG>. As described above, in some cases, a horizontal arrangement of memory tiles <NUM> may be referred to as a section of a memory array (not shown). In some cases, the horizontal direction may be in word line direction. In some cases, a vertical arrangement of the sections (i.e., a two-dimensional arrangement of tiles) may be referred to as a bank of the memory array. In some cases, the vertical direction may be in digit line direction. Multiple memory tiles <NUM> are shown in <FIG> and <FIG> to illustrate moving data from a section of the memory array to another section because the sequence described with reference to <FIG> and <FIG> may not be restricted to source and destination pages within a same section of the memory array.

Sense part <NUM> may be an example of sense part <NUM> as described with reference to <FIG>. In some cases, sense part <NUM>-a and/or <NUM>-b may be associated with a tile <NUM>-a (or section that includes the tile <NUM>-a, not shown) of the memory array such that the sense part <NUM>-a and/or <NUM>-b may not be utilized to sense other tiles of a different section of the memory array, such as <NUM>-b, <NUM>-c, or <NUM>-d. Sense parts <NUM> may be located on one side or both sides of memory tiles <NUM> in vertical or digit line direction, as described above with reference to <FIG>.

ECC logic <NUM> may be an example of ECC logic <NUM> as described with reference to <FIG>. ECC logic <NUM> may be configured to perform ECC function for data sets from any sections within a bank-level of the memory array. Hence, ECC logic <NUM> may perform ECC function for data set from tiles <NUM>-a, <NUM>-b, <NUM>-c, or <NUM>-d.

Step <NUM> of diagram <NUM>-a may represent an activate (ACT) step. During the ACT step, source page <NUM>-a may be activated (i.e., the word line and the digit lines associated with source page <NUM>-a are selected or turned on) to sense and capture data stored in source page <NUM>-a to sense part <NUM>-a and/or <NUM>-b. Symbol X in source page <NUM>-a may represent error(s) present in the contents of data in source page <NUM>-a. Capturing of data from source page <NUM>-a to sense part <NUM>-a and/or <NUM>-b may be illustrated with path <NUM>-a and/or <NUM>-b.

Step <NUM> of diagram <NUM>-a may represent a HOLD step. During the HOLD step, the sense components of the sense part <NUM>-a and <NUM>-b may be shut down. In addition, selection circuitry for word lines and digit lines and other control circuits associated with the memory array may be deactivated except that the data from source page <NUM>-a may be still held in the latches of sense part <NUM>-a and <NUM>-b. Hence, the HOLD step may be viewed as an idle state except the latches of sense part <NUM>-a and <NUM>-b may retain the data therein. Symbol X in the sense part <NUM>-b may represent error(s) present in the contents of data propagated from source page <NUM>-a. In addition, the data in source page <NUM>-a may no longer be valid or reliable due to absence of pre-charging the data therein. As described above, source page <NUM>-a may become a new spare page, i.e., a memory page available to serve as a destination page during wear-leveling application.

Step <NUM> of diagram <NUM>-a may represent a Pre-Set step. During the Pre-Set step, some or all memory cells in destination page <NUM>-a in tile <NUM>-d, a tile located in a different section, may be programmed to a certain logic state. In some cases, the logic state may correspond to logic <NUM>. It should be appreciated that the destination page <NUM>-a may be present in a tile (or a section) different than the tile (or the section) where source page <NUM>-a is located, thereby expanding a wear-leveling pool size. During the Pre-Set step, ISO devices associated with the destination page <NUM>-a may be deactivated. As explained above with reference to <FIG>, ISO device, when deactivated, may isolate digit line nodes of sense components from digit lines of the memory array. Memory cells of destination page <NUM>-a may be pre-written to a single logic state while ISO devices associated with destination page <NUM>-a are deactivated. In some cases, the pre-written logic state may correspond to a logic state of <NUM>.

Step <NUM> of diagram <NUM>-b in FIG. 4B may represent operation of processing through all code-words of source page <NUM>-a stored in the latches of sense part <NUM>-a and/or <NUM>-b via ECC logic <NUM> to scrub the contents of source page <NUM>-a. Scrubbing of code-words by sending them from sense part <NUM>-a and/or <NUM>-b to ECC logic <NUM> may be illustrated as paths <NUM>-a and/or <NUM>-b. Each code-word then may be stored in the latches in sense part <NUM>-c and/or <NUM>-d associated with destination page <NUM>-a. Storing of the code-words from ECC logic <NUM> to the latch in sense part <NUM>-c and/or <NUM>-d may be illustrated as paths <NUM>-a and/or <NUM>-b. Absence of symbol X in the contents of data stored in sense part <NUM>-c and/or <NUM>-d associated with destination page <NUM>-a indicates that the data may be free from the error(s) in the contents of source page <NUM>-a due to ECC logic <NUM> performing ECC function.

It should be appreciated that the operations in step <NUM> may be performed concurrently with the operations in step <NUM>. ISO devices associated with tile <NUM>-d, when deactivated, separate sense part <NUM>-c and/or <NUM>-d from memory cells in tile <NUM>-d, hence memory cells of destination page <NUM>-a. The operations in step <NUM> and step <NUM> may be performed in parallel because the operations in step <NUM> (e.g., the Pre-Set step for the memory cells in destination page <NUM>-a) may be independent of the operations in step <NUM> (e.g., processing code-words through ECC logic and store the scrubbed code-words in the latches in sense part <NUM>-c and/or <NUM>-d) due to the deactivated ISO devices. Concurrent operation of steps <NUM> and <NUM> in parallel may reduce (or "hide," at least in part) the overall time associated with wear-leveling operation.

Step <NUM> of diagram <NUM>-b may represent operations associated closing of the latches in sense part <NUM>-a and/or <NUM>-b without pre-charging source page <NUM>-a. At the completion of step <NUM>, i.e., closing the latches of sense part <NUM>-a and/or <NUM>-b, sense part <NUM>-a and/or <NUM>-b no longer represents valid data from source page <NUM>-a. Also, pre-charging source page <NUM>-a may not be necessary because the source page <NUM>-a may serve as a spare page during wear-leveling operation. Omission of pre-charging source page <NUM>-a may reduce overall time and energy associated with wear-leveling applications.

Step <NUM> of diagram <NUM>-b may represent writing destination page <NUM>-a with the data stored in sense part <NUM>-c and/or <NUM>-d. In some cases, writing destination page <NUM>-a may be referred to as pre-charging destination page <NUM>-a. Pre-charging the data from sense part <NUM>-c and/or <NUM>-d to destination page <NUM>-a may be illustrated with path <NUM>-a and/or <NUM>-b. It should be appreciated that pre-charging the data to destination page <NUM>-a may include writing a subset of the data only to the memory cells in destination page <NUM>-a storing a different logic state than the pre-written logic state established in step <NUM> as described above. For instance, only the memory cells in destination page <NUM>-a to store a logic "<NUM>" may need to be programmed with the logic "<NUM>" when the memory cells are pre-written to a logic state "<NUM>. " Reducing the number of memory cells during pre-charging destination page <NUM>-a may reduce overall time and energy associated with wear-leveling applications.

The steps <NUM> through <NUM> described above with reference to <FIG> and <FIG> enable wear leveling with a larger wear-leveling pool size by avoiding restrictions on both source and destination pages to be within a same section of memory array. In addition, error correction may be performed to scrub contents of the source page to avoid consuming error correction capacity of the destination page due to error propagation problem. In addition, overall time and energy consumption may be reduced to realize an efficient wear-leveling operation.

<FIG> shows a block diagram <NUM> of a memory device <NUM>-a that supports wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. Memory device <NUM>-a may be referred to as an electronic memory apparatus and include memory controller <NUM>-a and memory cells <NUM>-b, which may be examples of memory controller <NUM> and memory cell <NUM> described with reference to <FIG>. Memory controller <NUM>-a may be an internal logic circuit present on the same substrate with array of memory cells <NUM>-b. The memory controller <NUM>-a may also control operations associated with wear leveling and ECC function in conjunction with ECC logic during wear-leveling operations in accordance with embodiments of the present disclosure. Memory controller <NUM>-a may include biasing component <NUM> and timing component <NUM> and may operate memory device <NUM>-a as described with reference to <FIG>. Memory controller <NUM>-a may be in electronic communication with word line <NUM>-b, digit line <NUM>-b, plate line <NUM>-a, and sense component <NUM>-b, which may be examples of word line <NUM>, digit line <NUM>, plate line <NUM>, and sense component <NUM> described with reference to <FIG> and <FIG>.

Memory device <NUM>-a may also include reference component <NUM>, latch <NUM>, and ECC logic <NUM>. Sense part <NUM> may include sense component <NUM>-b and latch <NUM>. Latch <NUM> may be an example of latch <NUM> described with reference to <FIG> and <FIG>. Also, memory device <NUM>-a may include ISO device <NUM> which may be an example of ISO device <NUM> described with reference to <FIG>. ISO device <NUM>, during wear-leveling operation in accordance with embodiments of the present disclosure, may isolate the digit line nodes of sense component <NUM>-b from digit line (DL) of memory cell <NUM>-b. ISO device <NUM> enables a concurrent execution of step <NUM> and step <NUM> as explained above with reference to <FIG> and <FIG> in accordance with embodiments of the present disclosure. The components of memory device <NUM>-a may be in electronic communication with each other and may perform the functions described with reference to <FIG>. In some cases, reference component <NUM>, sense component <NUM>-b, and latch <NUM> may be components of memory controller <NUM>-a.

Memory controller <NUM>-a may be configured to activate word line <NUM>-b, plate line <NUM>-a, or digit line <NUM>-b by applying voltages to those various nodes. For example, biasing component <NUM> may be configured to apply a voltage to operate memory cell <NUM>-b to read, write, or pre-charge memory cell <NUM>-b as described above. In some cases, memory controller <NUM>-a may include a row decoder, column decoder, or both, as described with reference to <FIG>. This may enable memory controller <NUM>-a to access one or more memory cells <NUM>. Biasing component <NUM> may also provide voltage potentials to reference component <NUM> in order to generate a reference signal for sense component <NUM>-b. Additionally, biasing component <NUM> may provide voltage potentials for the operation of sense component <NUM>-b.

In some cases, memory controller <NUM>-a may perform its operations using timing component <NUM>. For example, timing component <NUM> may control the timing of the various word line selections or plate line biasing, including timing for switching and voltage application to perform the memory functions, such as reading, writing, or pre-charging, discussed herein. In some cases, timing component <NUM> may control the operations of biasing component <NUM>.

Reference component <NUM> may include various components to generate a reference signal for sense component <NUM>-b. Reference component <NUM> may include circuitry configured to produce reference signals. In some cases, reference component <NUM> may include other ferroelectric memory cells <NUM>. In some examples, reference component <NUM> may be configured to output a voltage with a value between the two sense voltages, as described with reference to <FIG>. Or reference component <NUM> may be designed to output a virtual ground voltage (i.e., approximately 0V).

Sense component <NUM>-b may compare a signal from memory cell <NUM>-b (through digit line <NUM>-b) with a reference signal from reference component <NUM>. Upon determining the logic state, the sense component may then store the output in latch <NUM>, where it may be used in accordance with the operations of an electronic device that memory device <NUM>-a is a part.

An electronic memory device includes a memory array including a plurality of sections of ferroelectric memory cells, each section of the plurality associated with a set of sense components and a set of latches, an error correction circuit in a periphery outside of the memory array, and a controller in electronic communication with the memory array, the set of sense components, the set of latches, and the error correction circuit, where the controller is operable to cause a first set of latches to receive, a first set of data from a first section of the memory array, where the first set of latches is associated with the first section of the memory array, send the first set of data to a second set of latches through the error correction circuit, where the second set of latches is associated with a second section of the memory array, and send the first set of data to a second set of latches through the error correction circuit, where the second set of latches is associated with a second section of the memory array, and store the first set of data in the second section of the memory array.

In some cases, the controller may be operable to activate a row of memory cells of the first section, where the row of memory cells corresponds to the first set of data, sense the first set of data from the activated row of memory cells using a first set of sense components associated with the first section, and store the first set of data in the first set of latches. In some cases, the controller may be operable to deactivate the row of memory cells of the first section while holding the first set of data in the first set of latches. In some cases, the controller may be operable to isolate memory cells of the second section of the memory array based on deactivating isolation devices associated with the second section, and pre-write a row of the isolated memory cells of the second section to a first logic state.

In some cases, the controller may be operable to transfer the first set of data from the first set of latches to the error correction circuit, cause the error correction circuit to perform error correction operation on the first set of data, and transfer the first set of data from the error correction circuit to the second set of latches. In some cases, the controller may be operable to divide the first set of data into a plurality of subsets of data and send each subset of the plurality of subsets of data through the error correction circuit sequentially to the second set of latches.

In some cases, the controller may be operable to concurrently send the first set of data and pre-write the row of isolated memory cells of the second section. In some cases, the controller may be operable to close the first set of latches without pre-charging the row of the first section of the memory array. In some cases, the controller may be operable to pre-charge the pre-written row of the second section of the memory array with the first set of data in the second set of latches.

In some embodiments, an apparatus is described. The apparatus may include means for causing a first set of latches to receive, a first set of data from a first section of a memory array, where the first set of latches is associated with the first section of the memory array, means for sending the first set of data to a second set of latches through an error correction circuit, where the second set of latches is associated with a second section of the memory array, and means for storing the first set of data in the second section of the memory array. In some cases, the apparatus may further include means for activating a row of memory cells of the first section, where the row of memory cells corresponds to the first set of data, means for sensing the first set of data from the activated row of memory cells using a first set of sense components associated with the first section, and means for storing the first set of data in the first set of latches. In some cases, the apparatus may further include means for deactivating the row of memory cells of the first section while holding the first set of data in the first set of latches.

In some cases, the apparatus may further include means for isolating memory cells of the second section of the memory array based on deactivating isolation devices associated with the second section and means for pre-writing a row of the isolated memory cells of the second section to a first logic state. In some cases, the apparatus may further include means for transferring the first set of data from the first set of latches to the error correction circuit, means for causing the error correction circuit to perform error correction operation on the first set of data, and means for transferring the first set of data from the error correction circuit to the second set of latches.

In some cases, the apparatus may further include means for dividing the first set of data into a plurality of subsets of data and means for sending each subset of the plurality of subsets of data through the error correction circuit sequentially to the second set of latches. In some cases, the apparatus may further include means for concurrently sending the first set of data and pre-write the row of isolated memory cells of the second section. In some cases, the apparatus may further include means for closing the first set of latches without pre-charging the row of the first section of the memory array. In some cases, the apparatus may further include means for pre-charging the pre-written row of the second section of the memory array with the first set of data in the second set of latches.

In some cases, an electronic memory device may include a memory array including a plurality of sections of ferroelectric memory cells, each section of the plurality associated with a set of sense components and a set of latches, an error correction circuit in a periphery outside of the memory array, and a controller in electronic communication with the memory array, the set of sense components, the set of latches, and the error correction circuit, where the controller may be operable to activate a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of the memory array, the first section including the row of memory cells, deactivate the row of memory cells of the first section while holding the first set of data in the first set of latches, pre-write a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section, send the first set of data to a second set of latches through the error correction circuit, where the second set of latches is associated with the second section, close the first set of latches without pre-charging the row of memory cells of the first section, and pre-charge the pre-written row of memory cells of the second section with the first set of data in the second set of latches.

In some embodiments, an apparatus is described. The apparatus may include means for activating a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of a memory array, the first section including the row of memory cells, means for deactivating the row of memory cells of the first section while holding the first set of data in the first set of latches, means for pre-writing a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section, means for sending the first set of data to a second set of latches through an error correction circuit, where the second set of latches is associated with the second section, means for closing the first set of latches without pre-charging the row of memory cells of the first section, and means for pre-charging the pre-written row of memory cells of the second section with the first set of data in the second set of latches.

<FIG> shows a flowchart illustrating a method <NUM> for wear leveling for random access and ferroelectric memory in accordance with embodiments of the present disclosure. The operations of method <NUM> may be implemented by a memory controller <NUM> or its components as described herein. In some examples, a memory controller <NUM> may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller <NUM> may perform some or all of the functions described below using special-purpose hardware.

At block <NUM> the memory controller <NUM> receives, at a first set of latches, a first set of data from a first section of a memory array, where the first set of latches is associated with the first section of the memory array. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> sends the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with a second section of the memory array. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> stores the first set of data in the second section of the memory array. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

In some embodiments, a method for wear leveling for random access and ferroelectric memory, such as the method <NUM>, is disclosed. The method may include receiving, at a first set of latches, a first set of data from a first section of a memory array, where the first set of latches is associated with the first section of the memory array, sending the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with a second section of the memory array, and storing the first set of data in the second section of the memory array.

An apparatus for performing a method or methods, such as the method <NUM>, is described. The apparatus may include means for receiving, at a first set of latches, a first set of data from a first section of a memory array, where the first set of latches is associated with the first section of the memory array, means for sending the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with a second section of the memory array, and means for storing the first set of data in the second section of the memory array.

Another apparatus for performing a method or methods, such as the method <NUM>, is described. The apparatus may include a memory array and a memory controller in electronic communication with the memory array, where the memory controller may be operable to receive, at a first set of latches, a first set of data from a first section of a memory array, where the first set of latches is associated with the first section of the memory array, send the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with a second section of the memory array, and store the first set of data in the second section of the memory array.

In some examples of the method <NUM> and apparatuses described herein, the receiving may further include processes, features, means, or instructions for activating a row of memory cells of the first section, where the row of memory cells corresponds to the first set of data, sensing the first set of data from the activated row of memory cells using a first set of sense components associated with the first section, and storing the first set of data in the first set of latches. Some examples of the method <NUM> and apparatuses described herein may further include processes, features, means, or instructions for deactivating the row of memory cells of the first section while holding the first set of data in the first set of latches.

Some examples of the method <NUM> and apparatuses described herein may further include processes, features, means, or instructions for isolating memory cells of the second section of the memory array based on deactivating isolation devices associated with the second section and pre-writing a row of the isolated memory cells of the second section to a first logic state. In some examples of the method <NUM> and apparatuses described herein, the first logic state may correspond to a logic state of one (<NUM>). In some examples of the method <NUM> and apparatuses described herein, the sending may further include processes, features, means, or instructions for transferring the first set of data from the first set of latches to the error correction circuit, causing the error correction circuit to perform error correction operation on the first set of data, and transferring the first set of data from the error correction circuit to the second set of latches.

Some examples of the method <NUM> and apparatuses described herein may further include processes, features, means, or instructions for dividing the first set of data into a plurality of subsets of data and sending each subset of the plurality of subsets of data through the error correction circuit sequentially to the second set of latches. In some examples of the method <NUM> and apparatuses described herein, the sending the first set of data and the pre-writing the row of isolated memory cells of the second section may occur concurrently. Some examples of the method <NUM> and apparatuses described herein may further include processes, features, means, or instructions for closing the first set of latches without pre-charging the row of the first section of the memory array. Some examples of the method <NUM> and apparatuses described herein may further include processes, features, means, or instructions for pre-charging the pre-written row of the second section of the memory array with the first set of data in the second set of latches. In some examples of the method <NUM> and apparatuses described herein, the pre-charging the pre-written row of the second section may further include processes, features, means, or instructions for writing a second logic state when the first set of data is different than the pre-written first logic state. In some examples of the method <NUM> and apparatuses described herein, the second logic state may correspond to a logic state of zero (<NUM>).

At block <NUM> the memory controller <NUM> may activate a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of a memory array, the first section including the row of memory cells. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> may deactivate the row of memory cells of the first section while holding the first set of data in the first set of latches. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> may pre-write a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller sends the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with the second section. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> may close the first set of latches without pre-charging the row of memory cells of the first section. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

At block <NUM> the memory controller <NUM> may pre-charge the pre-written row of memory cells of the second section with the first set of data in the second set of latches. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>.

In some embodiments, a method for wear leveling for random access and ferroelectric memory, such as the method <NUM>, is disclosed. The method may include activating a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of a memory array, the first section including the row of memory cells, deactivating the row of memory cells of the first section while holding the first set of data in the first set of latches, pre-writing a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section, sending the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with the second section, closing the first set of latches without pre-charging the row of memory cells of the first section, and pre-charging the pre-written row of memory cells of the second section with the first set of data in the second set of latches.

An apparatus for performing a method or methods, such as the method <NUM>, is described. The apparatus may include means for activating a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of a memory array, the first section including the row of memory cells, means for deactivating the row of memory cells of the first section while holding the first set of data in the first set of latches, means for pre-writing a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section, means for sending the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with the second section, means for closing the first set of latches without pre-charging the row of memory cells of the first section, and means for pre-charging the pre-written row of memory cells of the second section with the first set of data in the second set of latches.

Another apparatus for performing a method or methods, such as the method <NUM>, is described. The apparatus may include a memory array and a memory controller in electronic communication with the memory array, where the memory controller may be operable to activate a row of memory cells corresponding to a first set of data, to receive the first set of data at a first set of latches, where the first set of latches is associated with a first section of a memory array, the first section including the row of memory cells, deactivate the row of memory cells of the first section while holding the first set of data in the first set of latches, pre-write a row of memory cells of a second section of the memory array with a first logic state after isolating memory cells of the second section based on deactivating isolation devices associated with the second section, send the first set of data to a second set of latches through an error correction circuit in a periphery outside of the memory array, where the second set of latches is associated with the second section, close the first set of latches without pre-charging the row of memory cells of the first section, and pre-charge the pre-written row of memory cells of the second section with the first set of data in the second set of latches.

In some examples of the method <NUM> and apparatuses described herein, the activating may further include processes, features, means, or instructions for sensing the first set of data from the activated row of memory cells using a first set of sense components associated with the first section and storing the first set of data in the first set of latches. In some cases, the sending may further include processes, features, means, or instructions for dividing the first set of data into a plurality of subsets of data, transferring each subset of the plurality sequentially to the error correction circuit, causing the error correction circuit to perform error correction operation on each subset of the plurality, and transferring each subset of the plurality from the error correction circuit to the second set of latches.

Some drawings may illustrate signals as a single signal; however, it may be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, where the bus may have a variety of bit widths.

As used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The terms "electronic communication" and "coupled" refer to a relationship between components that support electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough so as to achieve the advantages of the characteristic.

The term "isolated" refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

The devices discussed herein, including memory device <NUM>, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A transistor or transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Also, as used herein, the phrase "based on" may not be construed as a reference to a closed set of conditions. In other words, as used herein, the phrase "based on" may be construed in the same manner as the phrase "based at least in part on.

By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Claim 1:
A method, comprising:
receiving, at a first set of latches (<NUM>) and as part of a wear-leveling operation, a first set of data from a first section of a memory array, the first set of data associated with a logical address, wherein:
the first set of latches (<NUM>) is associated with the first section of the memory array; and
the memory array comprises a plurality of sections of ferroelectric memory cells (<NUM>);
sending the first set of data to a second set of latches (<NUM>) through an error correction circuit (<NUM>, <NUM>) on a chip with a memory array, the error correction circuit (<NUM>, <NUM>) located in a periphery outside of the memory array, wherein the second set of latches (<NUM>) is associated with a second section of the memory array; and
storing the first set of data in the second section of the memory array without changing the logical address associated with the first set of data,
wherein the first section of the memory array becomes a spare section of the memory array to be used as a destination section for copying data from another section of the memory array.