Patent Description:
In current processors, a virtual address is translated to a physical address using a set of page tables managed by the processor's address translation circuitry. A pointer stored in one or more control registers (e.g., a CR3 register) points to a base translation table and different portions of the virtual address are used to identify different levels of translation tables to generate the physical address.

In current implementations, translation information for less privileged and more privileged pages reside in the same page tables. As a result, it is possible for less privileged software to indirectly access translation information for more privileged pages, even speculatively. In addition, changing interpretation of page tables (e.g. from <NUM>-level to <NUM>-level paging) requires disabling paging protections within the operating system, opening time windows where the primary memory protection capability is disabled. Moreover, because the process context ID (PCID) is stored in the page table base register (e.g., CR3), it is limited to only <NUM> bits.

<CIT> describes that input-output memory management unit uses a reverse map table to ensure that address translations acquired from a nested page table are correct and that I0 devices are permitted to access pages in a memory when performing memory accesses in a computing device. <CIT> describes a method of memory management in a virtualized computing system including generating a page table hierarchy that includes address translations to first pages of memory that store kernel software and second pages of the memory that store user software.

In particular <CIT> discloses a CPU comprising a plurality of cores, a plurality of registers and a MMU. The registers include program execution registers for use by code executing on the cores and system/control registers for use by code to configure the CPU. Code is executed by the CPU on a core at a particular privilege level of a hierarchy of privilege levels. The fields of the registers include a hypervisor page table base field that stores a physical address of a base page table for use with the hypervisor translation scheme. The fields also include a supervisor/user page table base field that stores a physical address of a base page table for use with the supervisor/user translation scheme. The MMU controls address translation and access permissions for memory accesses made by the cores.

Finally, in current implementations, recursive page tables can only use the lower four entries of the <NUM>-entry page attribute table (PAT) because the upper bit of the PAT selector at the leaf level overlaps with the large page bit at the upper levels.

The dependent claims pertain to preferred embodiments.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, location of bits) to specify, among other things, the operation to be performed (opcode) and the operand(s) on which that operation is to be performed. Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format.

<FIG> are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention. <FIG> is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; while <FIG> is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format <NUM> for which are defined class A and class B instruction templates, both of which include no memory access <NUM> instruction templates and memory access <NUM> instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

While embodiments of the invention will be described in which the vector friendly instruction format supports the following: a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes) (and thus, a <NUM> byte vector consists of either <NUM> doubleword-size elements or alternatively, <NUM> quadword-size elements); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); and a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., <NUM> byte vector operands) with more, less, or different data element widths (e.g., <NUM> bit (<NUM> byte) data element widths).

The class A instruction templates in <FIG> include: <NUM>) within the no memory access <NUM> instruction templates there is shown a no memory access, full round control type operation <NUM> instruction template and a no memory access, data transform type operation <NUM> instruction template; and <NUM>) within the memory access <NUM> instruction templates there is shown a memory access, temporal <NUM> instruction template and a memory access, non-temporal <NUM> instruction template. The class B instruction templates in <FIG> include: <NUM>) within the no memory access <NUM> instruction templates there is shown a no memory access, write mask control, partial round control type operation <NUM> instruction template and a no memory access, write mask control, vsize type operation <NUM> instruction template; and <NUM>) within the memory access <NUM> instruction templates there is shown a memory access, write mask control <NUM> instruction template.

The generic vector friendly instruction format <NUM> includes the following fields listed below in the order illustrated in <FIG>1B.

Format field <NUM> - a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format.

Base operation field <NUM> - its content distinguishes different base operations.

Register index field <NUM> - its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g. 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).

Modifier field <NUM> - its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access <NUM> instruction templates and memory access <NUM> instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.

Augmentation operation field <NUM> - its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field <NUM>, an alpha field <NUM>, and a beta field <NUM>. The augmentation operation field <NUM> allows common groups of operations to be performed in a single instruction rather than <NUM>, <NUM>, or <NUM> instructions.

Scale field <NUM> - its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses <NUM>scale * index + base).

Displacement Field 162A- its content is used as part of memory address generation (e.g., for address generation that uses <NUM>scale * index + base + displacement).

Displacement Factor Field 162B (note that the juxtaposition of displacement field 162A directly over displacement factor field 162B indicates one or the other is used) - its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N) - where N is the number of bytes in the memory access (e.g., for address generation that uses <NUM>scale * index + base + scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field <NUM> (described later herein) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used for the no memory access <NUM> instruction templates and/or different embodiments may implement only one or none of the two.

Data element width field <NUM> - its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.

Write mask field <NUM> - its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field <NUM> allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described in which the write mask field's <NUM> content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field's <NUM> content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's <NUM> content to directly specify the masking to be performed.

Immediate field <NUM> - its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.

Class field <NUM> - its content distinguishes between different classes of instructions. With reference to <FIG>, the contents of this field select between class A and class B instructions. In <FIG>, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A 168A and class B 168B for the class field <NUM> respectively in <FIG>).

In the case of the non-memory access <NUM> instruction templates of class A, the alpha field <NUM> is interpreted as an RS field 152A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 152A. <NUM> and data transform 152A. <NUM> are respectively specified for the no memory access, round type operation <NUM> and the no memory access, data transform type operation <NUM> instruction templates), while the beta field <NUM> distinguishes which of the operations of the specified type is to be performed. In the no memory access <NUM> instruction templates, the scale field <NUM>, the displacement field 162A, and the displacement scale filed 162B are not present.

In the no memory access full round control type operation <NUM> instruction template, the beta field <NUM> is interpreted as a round control field 154A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field 154A includes a suppress all floating point exceptions (SAE) field <NUM> and a round operation control field <NUM>, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field <NUM>).

SAE field <NUM> - its content distinguishes whether or not to disable the exception event reporting; when the SAE field's <NUM> content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

Round operation control field <NUM> - its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field <NUM> allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's <NUM> content overrides that register value.

In the no memory access data transform type operation <NUM> instruction template, the beta field <NUM> is interpreted as a data transform field 154B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access <NUM> instruction template of class A, the alpha field <NUM> is interpreted as an eviction hint field 152B, whose content distinguishes which one of the eviction hints is to be used (in <FIG>, temporal 152B. <NUM> and non-temporal 152B. <NUM> are respectively specified for the memory access, temporal <NUM> instruction template and the memory access, non-temporal <NUM> instruction template), while the beta field <NUM> is interpreted as a data manipulation field 154C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access <NUM> instruction templates include the scale field <NUM>, and optionally the displacement field 162A or the displacement scale field 162B.

Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask.

Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

In the case of the instruction templates of class B, the alpha field <NUM> is interpreted as a write mask control (Z) field 152C, whose content distinguishes whether the write masking controlled by the write mask field <NUM> should be a merging or a zeroing.

In the case of the non-memory access <NUM> instruction templates of class B, part of the beta field <NUM> is interpreted as an RL field 157A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 157A. <NUM> and vector length (VSIZE) 157A. <NUM> are respectively specified for the no memory access, write mask control, partial round control type operation <NUM> instruction template and the no memory access, write mask control, VSIZE type operation <NUM> instruction template), while the rest of the beta field <NUM> distinguishes which of the operations of the specified type is to be performed. In the no memory access <NUM> instruction templates, the scale field <NUM>, the displacement field 162A, and the displacement scale filed 162B are not present.

In the no memory access, write mask control, partial round control type operation <NUM> instruction template, the rest of the beta field <NUM> is interpreted as a round operation field 159A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field 159A - just as round operation control field <NUM>, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 159A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's <NUM> content overrides that register value.

In the no memory access, write mask control, VSIZE type operation <NUM> instruction template, the rest of the beta field <NUM> is interpreted as a vector length field 159B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., <NUM>, <NUM>, or <NUM> byte).

In the case of a memory access <NUM> instruction template of class B, part of the beta field <NUM> is interpreted as a broadcast field 157B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field <NUM> is interpreted the vector length field 159B. The memory access <NUM> instruction templates include the scale field <NUM>, and optionally the displacement field 162A or the displacement scale field 162B.

With regard to the generic vector friendly instruction format <NUM>, a full opcode field <NUM> is shown including the format field <NUM>, the base operation field <NUM>, and the data element width field <NUM>. While one embodiment is shown where the full opcode field <NUM> includes all of these fields, the full opcode field <NUM> includes less than all of these fields in embodiments that do not support all of them. The full opcode field <NUM> provides the operation code (opcode).

The augmentation operation field <NUM>, the data element width field <NUM>, and the write mask field <NUM> allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths.

The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the invention). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments of the invention. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: <NUM>) a form having only instructions of the class(es) supported by the target processor for execution; or <NUM>) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code.

VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than <NUM> bits. The use of a VEX prefix provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A = A + B, which overwrites a source operand. The use of a VEX prefix enables operands to perform nondestructive operations such as A = B + C.

<FIG> illustrates an exemplary AVX instruction format including a VEX prefix <NUM>, real opcode field <NUM>, Mod R/M byte <NUM>, SIB byte <NUM>, displacement field <NUM>, and IMM8 <NUM>. <FIG> illustrates which fields from <FIG> make up a full opcode field <NUM> and a base operation field <NUM>. <FIG> illustrates which fields from <FIG> make up a register index field <NUM>.

VEX Prefix (Bytes <NUM>-<NUM>) <NUM> is encoded in a three-byte form. The first byte is the Format Field <NUM> (VEX Byte <NUM>, bits [<NUM>:<NUM>]), which contains an explicit C4 byte value (the unique value used for distinguishing the C4 instruction format). The second-third bytes (VEX Bytes <NUM>-<NUM>) include a number of bit fields providing specific capability. Specifically, REX field <NUM> (VEX Byte <NUM>, bits [<NUM>-<NUM>]) consists of a VEX. R bit field (VEX Byte <NUM>, bit [<NUM>] - R), VEX. X bit field (VEX byte <NUM>, bit [<NUM>] - X), and VEX. B bit field (VEX byte <NUM>, bit[<NUM>] - B). Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding VEX. X, and VEX. Opcode map field <NUM> (VEX byte <NUM>, bits [<NUM>:<NUM>] - mmmmm) includes content to encode an implied leading opcode byte. W Field <NUM> (VEX byte <NUM>, bit [<NUM>] - W) - is represented by the notation VEX. W, and provides different functions depending on the instruction. The role of VEX. vvvv <NUM> (VEX Byte <NUM>, bits [<NUM>:<NUM>]-vvvv) may include the following: <NUM>) VEX. vvvv encodes the first source register operand, specified in inverted (<NUM> complement) form and is valid for instructions with <NUM> or more source operands; <NUM>) VEX. vvvv encodes the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) VEX. vvvv does not encode any operand, the field is reserved and should contain 1111b. L <NUM> Size field (VEX byte <NUM>, bit [<NUM>]-L) = <NUM>, it indicates <NUM> bit vector; if VEX. L = <NUM>, it indicates <NUM> bit vector. Prefix encoding field <NUM> (VEX byte <NUM>, bits [<NUM>:<NUM>]-pp) provides additional bits for the base operation field <NUM>.

Real Opcode Field <NUM> (Byte <NUM>) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field <NUM> (Byte <NUM>) includes MOD field <NUM> (bits [<NUM>-<NUM>]), Reg field <NUM> (bits [<NUM>-<NUM>]), and R/M field <NUM> (bits [<NUM>-<NUM>]). The role of Reg field <NUM> may include the following: encoding either the destination register operand or a source register operand (the rrr of Rrrr), or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field <NUM> may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) - The content of Scale field <NUM> (Byte <NUM>) includes SS252 (bits [<NUM>-<NUM>]), which is used for memory address generation. The contents of SIB. xxx <NUM> (bits [<NUM>-<NUM>]) and SIB. bbb <NUM> (bits [<NUM>-<NUM>]) have been previously referred to with regard to the register indexes Xxxx and Bbbb.

The Displacement Field <NUM> and the immediate field (IMM8) <NUM> contain data.

<FIG> is a block diagram of a register architecture <NUM> according to one embodiment of the invention. In the embodiment illustrated, there are <NUM> vector registers <NUM> that are <NUM> bits wide; these registers are referenced as zmm0 through zmm31. The lower order <NUM> bits of the lower <NUM> zmm registers are overlaid on registers ymm0-<NUM>. The lower order <NUM> bits of the lower <NUM> zmm registers (the lower order <NUM> bits of the ymm registers) are overlaid on registers xmm0-<NUM>.

General-purpose registers <NUM> - in the embodiment illustrated, there are sixteen <NUM>-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) <NUM>, on which is aliased the MMX packed integer flat register file <NUM> - in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures. Detailed herein are circuits (units) that comprise exemplary cores, processors, etc..

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units <NUM>/<NUM> and a shared L2 cache unit <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core, along with its connection to the on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to embodiments of the invention. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> and vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core is stored in its L2 cache subset <NUM> and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset <NUM> and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is <NUM>-bits wide per direction in some embodiments.

<FIG> is an expanded view of part of the processor core in <FIG> according to embodiments of the invention. <FIG> includes an L1 data cache 506A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> is a <NUM>-wide vector processing unit (VPU) (see the <NUM>-wide ALU <NUM>), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 522A-B, and replication with replication unit <NUM> on the memory input.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 602A, a system agent <NUM>, a set of one or more bus controller units <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 602A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 602A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 602A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 602A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores 604A-N, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit <NUM> interconnects the integrated graphics logic <NUM>, the set of shared cache units <NUM>, and the system agent unit <NUM>/integrated memory controller unit(s) <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 602A-N are capable of multi-threading. The system agent <NUM> includes those components coordinating and operating cores 602A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 602A-N and the integrated graphics logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 602A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 602A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment, the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> is couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface, or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

In one embodiment, first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I/O interconnect bus, although the scope of the present invention is not so limited.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> in order to avoid obscuring other aspects of <FIG>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 102A-N, cache units 604A-N, and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using an first compiler <NUM> to generate a first binary code (e.g., x86) <NUM> that may be natively executed by a processor with at least one first instruction set core <NUM>. In some embodiments, the processor with at least one first instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The first compiler <NUM> represents a compiler that is operable to generate binary code of the first instruction set <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one first instruction set core <NUM> (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter <NUM> is used to convert the first binary code <NUM> into code that may be natively executed by the processor without an first instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code <NUM>.

Finally, in current implementations, recursive page tables can only use the lower four entries of the <NUM>-entry page attribute table (PAT) because the upper bit of the PAT selector at the leaf level overlaps with the large page bit at the upper levels.

<FIG> illustrates an exemplary processor <NUM> on which embodiments of the invention may be implemented including a plurality of cores <NUM>-N for simultaneously executing a plurality of instruction threads. While details of only a single core (Core <NUM>) are shown in <FIG>, it will be understood that each of the other cores of processor <NUM> may include the same or similar components.

The plurality of cores <NUM>-N may each include a memory management unit (MMU) <NUM> for performing memory operations (e.g., such as load/store operations). Address translation circuitry <NUM> of the MMU <NUM> performs the address translation techniques described herein to allow the core to access pages in memory <NUM> using pointers contained within a set of control/MSR registers <NUM>. In one embodiment, in response to an address translation request comprising a virtual address, the address translation circuitry <NUM> accesses the appropriate set of pages in system memory to identify the physical memory address associated with the virtual address. It may then cache the virtual-to-physical translation with a translation lookaside buffer (TLB) <NUM>.

The illustrated architecture also includes an execution pipeline which uses the address translations including an instruction fetch unit <NUM> for fetching instructions from system memory <NUM>, the level <NUM> (L1) instruction cache <NUM>, the L2 cache <NUM>, or the L3 cache <NUM>. The instruction fetch unit <NUM> also includes a next instruction pointer <NUM> for storing the address of the next instruction to be fetched from memory <NUM> (or one of the caches); an instruction translation look-aside buffer (ITLB) <NUM> for storing a map of recently used virtual-to-physical instruction addresses to improve the speed of address translation; a branch prediction unit <NUM> for speculatively predicting instruction branch addresses; and branch target buffers (BTBs) <NUM> for storing branch addresses and target addresses.

A decoder <NUM> decodes the fetched instructions into micro-operations or "uops" and an execution unit <NUM> executing the uops on a plurality of functional units. A writeback/retirement unit <NUM> retires the executed instructions and writes back the results to other elements of the execution pipeline.

The illustrated core architecture also includes a set of general purpose registers (GPRs) <NUM>, a set of vector registers <NUM>, and a set of mask registers <NUM>. In one embodiment, multiple vector data elements are packed into each vector register <NUM> which may have a <NUM> bit width for storing two <NUM> bit values, four <NUM> bit values, eight <NUM> bit values, sixteen <NUM> bit values, etc. However, the underlying principles of the invention are not limited to any particular size/type of vector data. In one embodiment, the mask registers <NUM> include eight <NUM>-bit operand mask registers used for performing bit masking operations on the values stored in the vector registers <NUM> (e.g., implemented as mask registers k0-k7 described herein). However, the underlying principles of the invention are not limited to any particular mask register size/type.

Each core <NUM>-N may include a dedicated Level <NUM> (L1) cache <NUM> and Level <NUM> (L2) cache <NUM> for caching instructions and data according to a specified cache management policy. As mentioned, the L1 cache <NUM> includes a separate instruction cache <NUM> for storing instructions and a separate data cache <NUM> for storing data. The instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., <NUM>, <NUM>, <NUM> Bytes in length).

<FIG> illustrates another embodiment which includes a system memory management unit (SMMU) <NUM> for performing system-level memory management operations on behalf of all of the cores and any other system-level components such as a graphics processor and a digital signal processor (DSP) which may be integrated on the same semiconductor chip as the processor <NUM>. The SMMU includes address translation circuitry <NUM> for performing virtual-to-physical translations as described herein and a TLB <NUM> for caching the system-level address translations, which may be synchronized with the translations in the TLBs <NUM> of each core.

In contrast to prior implementations in which translation entries assigned to different privilege levels are stored within the same translation tables, one embodiment of the invention allocates a different set of translation tables for each privilege level. <FIG> illustrates one particular embodiment which includes a first privilege level, referred to as the "supervisor" level and a second privilege level, referred to as the "user" level. In one embodiment, only certain types of software such as the operating system (OS) and/or Hypervisor (in a virtualized embodiment) is executed at the supervisor privilege level, while user applications are executed at the user privilege level.

While some embodiments of the invention are described herein within the context of two privilege levels (supervisor and user), other embodiments use one or more additional privilege levels at which different types of program code are executed. In these embodiments, each privilege level may be associated with its own set of address translation resources including TLB resources as described herein for the user and supervisor privilege levels.

Returning to <FIG>, in the illustrated embodiment the address translation circuitry <NUM> programs a first control register <NUM> (e.g., register CR3 in an x86 implementation) with a supervisor base translation table pointer (SBTTP) to identify a supervisor base translation table <NUM>. The address translation circuitry <NUM> will subsequently translate requests originating from program code running at a supervisor privilege level by using the SBTTP to identify the supervisor base translation table <NUM>. Similarly, the address translation circuitry <NUM> programs a second control register <NUM> (e.g., control register CR5) with a user base translation table pointer (UBTTP) <NUM> to identify a user base translation table <NUM>. For program code executing with a user-level privilege, the address translation circuitry <NUM> performs a page walk operation with the user base translation table <NUM> identified by the UBTTP.

The address translation circuitry <NUM> parses the various linear address blocks (LABs) <NUM>-<NUM> of the virtual/linear address <NUM> to walk the various levels of translation tables <NUM>-<NUM> to identify the associated physical address. In one embodiment, each LAB <NUM>-<NUM> comprises a set of virtual/linear address bits which identify a different entry in a different translation table <NUM>-<NUM>. In particular, in one embodiment, each LAB <NUM>-<NUM> is combined with a pointer to identify an entry in one of the supervisor-level translation tables <NUM>-<NUM> (if the request originated from supervisor-level program code as in <FIG>) or user-level translation tables <NUM>-<NUM> (if the request originated from user-level program code).

In <FIG>, the SBTTP identifies the supervisor base translation table <NUM> and the first LAB <NUM> identifies an offset from the base SBTTP value to identify an entry in the supervisor base translation table <NUM> containing a pointer to the base address of the second level translation table <NUM>. The second LAB <NUM> identifies an offset from the base address of the second level translation table <NUM> to identify an entry in the second level translation table <NUM> containing a pointer to the base address of the third level translation table <NUM>, and so on, until the final entry in the last level translation table <NUM> provides the physical address <NUM>.

In the invention, the address translation circuitry <NUM> programs a third control register <NUM> (e.g., control register CR6) with a process context ID (PCID) value to uniquely identify the context of the currently executing process. In one embodiment, the PCID value is updated on a context switch to identify the new context of the new process being swapped in. In contrast to prior implementations which limited the PCID value to <NUM> bits when stored in control register CR3, this embodiment provides a full <NUM>-bit process context ID (PCID) stored in a new control register <NUM>.

Each physical address <NUM> identified by accessing the page tables <NUM>-<NUM>, <NUM>-<NUM> as described above may be stored in an entry in the TLB <NUM> and associated with at least a portion of the virtual/linear address <NUM>. In addition, in one embodiment, each translation originating from user-level program code has the current PCID from the third control register <NUM> associated with it in the TLB <NUM> and each translation originating from supervisor-level program code has a fixed PCID identification value associated with it in the TLB <NUM> (e.g., a fixed value of <NUM> in one embodiment).

<FIG> illustrates an example TLB <NUM> comprising a set of entries, each of which is associated with a PCID value <NUM> to specify a particular context, a virtual address <NUM>, an associated physical address <NUM>, and one or more status/control bits <NUM>. In this particular example, the status bits indicate whether the TLB entry is valid (<NUM>) or invalid (<NUM>). In one embodiment, the current PCID value associated with a translation request <NUM> is used in combination with the virtual address to perform the TLB lookup so that a TLB hit will be generated only if a TLB entry <NUM> includes both the PCID value (or portion thereof) and the virtual address (or portion thereof). If both the PCID value and virtual address match, a TLB hit is returned with the associated physical address (PA) <NUM>. If a match is not found, a TLB miss is returned, causing the address translation circuitry <NUM> to performs a page walk (as described above) which will update an entry in the TLB with the resulting physical address.

In one embodiment, a TLB entry containing a PCID value associated with supervisor-level program code can only be accessed in response to a supervisor-level translation request <NUM>. In the example shown in <FIG>, the third TLB entry from the top includes a PCID value of <NUM> to indicate that it is an entry associated with supervisor-level program code. Thus, only a translation request originating from the supervisor-level program code (having a PCID value of <NUM>) will result in a TLB hit.

Different PCID value sizes and/or types may be used while still complying with the underlying principles of the invention. By way of example, and not limitation, <NUM>-bit PCID values are used in one embodiment but other embodiments may use <NUM>-bit, <NUM>-bit values, or any other set of values capable of distinguishing between contexts. In addition, a variety of additional fields may be included for each TLB entry such as page attribute bits specifying attributes for the associated memory page (e.g., uncacheable, write combining, write through, write protected, write back, etc).

In addition to translation requests <NUM>, TLB management operations <NUM> may use specific PCID values to identify only those TLB entries associated with a given context. For example, a TLB invalidate instruction may be executed to invalidate only those TLB entries associated with a particular PCID (e.g., in response to the process associated with that PCID being terminated). In addition, supervisor-level program code (e.g., system-level software) may include instructions to invalidate all TLB entries, to invalidate only entries having a particular virtual address or physical address, regardless of PCID, or to invalidate entries based on any other criteria.

By way of example, and not limitation, to flush all entries associated with a given application, an INVPCID instruction may be executed specifying the full <NUM>-bit PCID associated with the application. For supervisor pages, the fixed PCID value (<NUM>) may be used to accomplish the TLB flush. In either case, only those TLB entries associated with the given PCID will be flushed, retaining translations for other contexts.

Embodiments of the invention may allow more privileged (supervisor) software to access memory in less privileged (user) domains. For example, a particular control bit or set of control bits (e.g., the SMAP bit and AC bit in x86 architectures) may be set in one or more control registers (e.g., the CR4 and EFLAGS registers) to allow explicit supervisor-mode data accesses to user-mode pages. Whenever these flags are set in supervisor mode, all memory accesses may be directed to user space. Alternatively, or in addition, an instruction prefix may be used to indicate that a given instruction's memory accesses should be directed to user space. In either case, supervisor accesses directed to user space will use the UBTTP in control register <NUM> (e.g., CR5) for translation instead of the SBTTP in control register <NUM> (e.g., CR3).

As a result of the embodiments described herein, PCID changes no longer need to be simultaneous with changes to the page tables used, as the supervisor PCID never changes (which means it cannot change when the page tables change) and the user PCID can only be changed in supervisor mode, meaning the new PCID will not be used immediately, removing the risk of using the new page tables before the PCID is changed or vice-versa. In one embodiment, appropriate TLB management is performed when the page table base is changed without changing the PCID or when the PCID is changed.

As mentioned, the embodiments of the invention may be implemented with different types of address translation architectures including those which use <NUM>-level paging and <NUM>-level paging. By way of example, and not limitation, <FIG> illustrates an example of a <NUM>-level paging architecture and <FIG> illustrates an example of a <NUM>-level paging architecture.

In <FIG>, control register CR3 <NUM> stores the base address of a page map level <NUM> (PML4) table <NUM>. The address translation circuitry <NUM> uses this value and bits <NUM>:<NUM> of the virtual/linear address <NUM> to identify an entry which identifies the base of a page directory pointer table <NUM> in which an entry is identified using directory pointer bits <NUM>:<NUM> of the virtual/linear address <NUM>. The entry from the PDPT <NUM> points to the base of a page directory <NUM> and directory bits <NUM>:<NUM> from the virtual/linear address <NUM> identify a page directory entry (PDE) pointing to the base of a page table <NUM>. Table bits <NUM>:<NUM> identify a page table entry (PTE) which points to the base of page <NUM> and a particular physical address is identified using offset bits <NUM>:<NUM> from the virtual/linear address <NUM>.

The <NUM>-level paging implementation in <FIG> operates in substantially the same manner except that the value in control register CR3 points to a page map level <NUM> (PML5) table and PML5 bits <NUM>:<NUM> of the virtual/linear address identify a PML5 entry pointing to the base of the PML4 table <NUM>. The page directory pointer table <NUM>, page directory <NUM>, page table <NUM>, and page <NUM> containing the physical address are accessed in a similar manner as described above.

With the embodiments of the invention, the paging translation type may be switched between <NUM>-level and <NUM>-level paging (or any other group of paging types) by a single write to either control register <NUM>, control register <NUM>, or both. In particular, this write operation may include a first bit field to specify the number of page table levels (i.e., the translation "mode") and a second bit field to specify the base address of the page tables that support the target arrangement. There is no longer a need as in existing systems to disable paging in order to make these changes.

Some existing implementations store a user/supervisor bit in each page table entry to indicate whether the corresponding page is associated with a user-privileged program code or supervisor privileged program code. In addition, in these implementations, recursive page tables can only use the lower four entries of the <NUM>-entry page attribute table (PAT) used for memory typing because the upper bit of the PAT selector at the leaf level overlaps with the large page bit at upper levels.

Using the embodiments described herein, the user/supervisor bit is no longer required within individual page table entries and may therefore be used freed up for other purposes. In one particular embodiment, for systems which include a page attribute table (PAT) <NUM> (or other structure for storing page attribute information), the deprecated user/supervisor bit is repurposed as a third bit of a PAT index at all levels of the page table hierarchy, with the third bit defined for leaf entries today being returned to the reserved bit pool for other uses as needed. This implementation results in a consistent, full <NUM>-bit PAT index at all levels of the page tables, even when recursive tables are used.

The embodiments described herein also inherently prevent user-level software from indirectly accessing supervisor page translation information, since table used to translate user-level requests can be free of any supervisor-level translations. In addition, using these embodiments, paging does not need to be disabled when changing paging algorithms as a simple write to the relevant control register(s) <NUM>, <NUM> can be used to effect the change (e.g., <NUM>-level to <NUM>-level paging or vice-versa).

In addition, a full <NUM>-bit PCID as described herein allows software using up to <NUM> bit process identifiers to use the values directly as process context IDs.

While CR5 and CR6 are described as possibilities options for the new control registers <NUM>-<NUM>, the underlying principles of the invention are not limited to these specific details. For example, architectural machine status registers (MSRs) may also be used. In the examples which use control register CR5, this register may be formatted in the same manner as CR3, except that the least significant bit of CR5/CR6 may provides an enable for the use of the new registers.

The "supervisor" mode and "user" mode as described herein may represent any two privilege levels, with supervisor being the higher of the two levels. For example, in one implementation supervisor mode means that the current privilege level (CPL) is CPL0, CPL1, or CPL2 while user mode means CPL <NUM>.

A method in accordance with one embodiment is illustrated in <FIG>. The method may be implemented within the context of the processor architectures described above, but is not limited to any particular processor architecture.

At <NUM>, a first control register is programmed with a first base address and translation mode for first program code operating at a first privilege level. In some embodiments described above, the "supervisor" level is the first privilege level, the first control register comprises CR3, and the translation mode comprises a <NUM>-level or <NUM>-level translation architecture.

At <NUM>, a second control register is programmed with a second base address and translation mode for second program code operating at a second privilege level which is lower than the first privilege level. In some embodiments described above, the "user" level is the second privilege level, the first control register comprises CR5, and the translation mode comprises a <NUM>-level or <NUM>-level translation architecture. Note that the translation modes specified in the first and second control registers may be the same or may be different.

At <NUM>, a third control register is programmed with the context identifier associated with the second program code. In some embodiments described above, the context identifier comprises a PCID value associated with the second program code.

Upon receipt of a translation request at <NUM>, if the request originates from the second program code, then at <NUM> the TLB is initially queried using the context identifier from the third control register and the virtual/linear address. If the entry is located then the associated physical address is returned from the TLB. If not, then a page walk is performed using the second base address and translation mode to identify the physical address. The resulting physical address may then be stored in the TLB along with the virtual address and context identifier.

If the request originates from the first program code, then at <NUM> the TLB is initially queried using a fixed context identifier associated with the first privilege level (e.g., <NUM>) and the virtual/linear address. If the entry is located then the associated physical address is returned from the TLB. If not, then a page walk is performed using the first base address and translation mode to identify the physical address. The resulting physical address may then be stored in the TLB along with the virtual address and fixed context identifier.

Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

Claim 1:
A processor comprising:
a first control register (<NUM>) of a core of the processor to store a first base address associated with program code executed at a first privilege level;
a second control register (<NUM>) of the core to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and
address translation circuitry (<NUM>) of the core to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level, and
a third control register (<NUM>) to store a context identifier to identify a context for at least a portion of the program code executed at the second privilege level.