Patent Description:
The following relates generally to output drivers in a memory device and more specifically to an output driver for multi-level signaling.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.

<CIT> discloses apparatuses and methods for multi-level communication architectures. For example, an apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

<NPL> discloses that matching I/O driver output resistance to transmission line impedance is critical for high speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage and temperature variations, that same calibration circuitry may perform improperly. ESCH G ET AL presents an I/O driver design that is less sensitive to process, voltage and temperature variations. The proposed driver design provides a near linear, or flat, output resistance response verses output voltageMatching I/O driver output resistance to transmission line impedance is critical for high speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage and temperature variations, that same calibration circuitry may perform improperly. ESCH G ET AL presents an I/O driver design that is less sensitive to process, voltage and temperature variations. The proposed driver design provides a near linear, or flat, output resistance response verses output voltage.

<CIT> discloses impedance-matched output driver circuits that include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage [0005d] <CIT> discloses decoder circuits for selecting a word line in a semiconductor memory device which comprises a plurality of memory cell sectors including a plurality of word lines and bit lines and a plurality of memory cells which each is electrically erasable and programmable. The decoder circuits comprise a pull-up and pull-down transistors connected to global word lines which are connected to the word lines via connecting means, the decoder circuits turning on pull-down transistors before a high voltage according to an operation mode is supplied to one selected from the global word lines and pre-charging the gates of the pull-up transistors to the high voltage. The invention enables the decoder circuits to supply the word line drive voltage to the global word lines connected to memory cells by using the self-boosting method to thereby reduce the boosting load.

<CIT>discloses an integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than <NUM>, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver subcircuit, to reduce gds distortion in the signal.

<CIT> discloses long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL, SSTL, LVDS, MIPI, or MDDI interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present invention provide excellent solutions to support high performance interface while consuming much lower power.

<CIT> discloses an on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an output node for outputting an output signal and assigned with different resistance values; and a control signal generation block for generating a plurality of pull up and pull down control signals for turning on/off the plurality of output driver units in response to output signals of the decoding unit.

The present invention is set out in independent apparatus claim <NUM> and independent method claim <NUM>. Preferred aspects are defined in the dependent claims <NUM>-<NUM>, <NUM>-<NUM>.

In the following only embodiments or examples comprising all the features of independent claim <NUM> or of independent claim <NUM> fall under the conferred scope of protection.

According to a first aspect of the present invention, there is provided an electronic memory apparatus as set-out in claim <NUM>. According to a second aspect of the present invention, there is provided a method as set-out in claim <NUM>. Optional features of the invention are set-out in the dependent claims.

Some memory devices may use multi-level signaling to communicate data between components (e.g., high-bandwidth memory). For example, a pulse amplitude modulation (PAM) scheme such as PAM4 may be used to encode data into a signal. Some multi-level signals are more sensitive to noise than a binary-level signal because the margins between amplitude levels may be less. In addition, some noise may be introduced into a multi-level signal by a non-linear response of switching components of the driver over the range of output values.

A driver of a multi-level signaling interface is provided. The driver may be configured to reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.

Features of the disclosure introduced above are further described below in the context of a memory device. Specific examples are then described for a memory device that supports an output driver for multi-level signaling. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to multi-level signaling.

<FIG> illustrates an example memory device <NUM> in accordance with various examples of the present disclosure. The memory device <NUM> may also be referred to as an electronic memory apparatus. The memory device <NUM> may be configured to utilize multi-level signaling to communicate data between various components of the memory device <NUM>. Some examples of the multi-level signaling may include PAM signaling such as PAM4 signaling, PAM8 signaling, etc. The memory device <NUM> may include an array of memory cells <NUM>, a controller <NUM>, a plurality of channels <NUM>, signaling interfaces <NUM>, other components, or a combination thereof.

A memory device <NUM> may use multi-level signaling to increase an amount of information transmitted using a given bandwidth of frequency resources. In binary signaling, two symbols of a signal (e.g., two voltages levels) are used to represent up to two logic states (e.g., logic state '<NUM>' or logic state '<NUM>'). In multi-level signaling, a larger library of symbols may be used to represent data. Each symbol may represent more than two logic states (e.g., logic states with multiple bits). For example, if the signal is capable of four unique symbols, the signal may be used to represent up to four logic states (e.g., '<NUM>', '<NUM>', '<NUM>', and `<NUM>'). As a result, multiple bits of data may be compressed into a single symbol, thereby increasing the amount of data communicated using a given bandwidth.

In some cases of multi-level signaling, the amplitude of the signal may be used to generate the different symbols. For example, a first amplitude level may represent '<NUM>', a second amplitude level may represent '<NUM>', a third amplitude level may represent `<NUM>', and a fourth amplitude level may represent '<NUM>'. One drawback of some multi-level signaling schemes is that the symbols may be separated by a smaller voltage than symbols in a binary signaling scheme. The smaller voltage separation may make the multi-level signaling scheme more susceptible to errors caused by noise or other aspects. The voltage separation of symbols in the multi-level signaling scheme, however, may be expanded by increasing a peak-to-peak transmitted power of a transmitted signal. In some situations, however, such an increase to peak-to-peak transmitted power may not be possible or may be difficult due to fixed power supply voltages, fixed signal power requirements, or other factors. Consequently, to implement multi-level signaling a transmitter may utilize more power and/or a receiver may be susceptible to an increased error rate, when compared to a binary signaling scheme.

A multi-level signal (sometimes referred to as a multi-symbol signal) may be a signal that is modulated using a modulation scheme that includes three or more unique symbols to represent data (e.g., two or more bits of data). The multi-level signal may be an example of an M-ary signal that is modulated using a modulation scheme where M is greater than or equal to three, where M represents the number of unique symbols, levels, or conditions possible in the modulation scheme. A multi-level signal or a multi-level modulation scheme may be referred to as a non-binary signal or non-binary modulation scheme in some instances. Examples of multi-level (or M-ary) modulation schemes related to a multi-level signal may include, but are not limited to, pulse amplitude modulation (e.g., PAM4, PAM8), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and/or others.

A binary-level signal (sometimes referred to as a binary-symbol signal) may be a signal that is modulated using a modulation scheme that includes two unique symbols to represent one bit of data. The binary-level signal may be an example of an M-ary modulation scheme where M is less than or equal to <NUM>. Examples of binary-level modulation schemes related to a binary-level signal include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, PAM2, and/or others.

Each memory cell of the array of memory cells <NUM> may be programmable to store different states. For example, each memory cell may be programmed to store two or more logic states (e.g., a logic `<NUM>', a logic '<NUM>', a logic `<NUM>', a logic '<NUM>', a logic '<NUM>', a logic '<NUM>', etc.). A memory cell may store a charge representative of the programmable states in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. The memory cells of the array of memory cells <NUM> may use any number of storage mediums including DRAM, FeRAM, PCM, or other types of memory cells. A DRAM memory cell may include a capacitor with a dielectric material as the insulating material. For example, the dielectric material may have linear or para-electric electric polarization properties and a ferroelectric memory cell may include a capacitor with a ferroelectric material as the insulating material. In instances where the storage medium includes FeRAM, different levels of charge of a ferroelectric capacitor may represent different logic states.

The array of memory cells <NUM> may be or include a three-dimensional (3D) array, where multiple two-dimensional (2D) arrays or multiple memory cells are formed on top of one another. Such a configuration may increase the number of memory cells that may be formed on a single die or substrate as compared with 2D arrays. In turn, this may reduce production costs or increase the performance of the memory array, or both. Each level of the array may be aligned or positioned so that memory cells may be approximately aligned with one another across each level, forming a memory cell stack.

In some examples, the array of memory cells <NUM> may include a memory cell, a word line, a digit line, and a sense component. In some examples, the array of memory cells <NUM> may include a plate line (e.g., in the case of FeRAM). A memory cell of the array of memory cells <NUM> may include a selection component and a logic storage component, such as capacitor that includes a first plate, a cell plate, a second plate, and a cell bottom. The cell plate and cell bottom may be capacitively coupled through an insulating material (e.g., dielectric, ferroelectric, or PCM material) positioned between them.

The memory cell of the array of memory cells <NUM> may be accessed (e.g., during a read operation, write operation, or other operation) using various combinations of word lines, digit lines, and/or plate lines. In some cases, some memory cells may share access lines (e.g., digit lines, word lines, plate lines) with other memory cells. For example, a digit line may be shared with memory cells in a same column, a word line may be shared with memory cells in a same row, and a plate line may be shared with memory cells in a same section, tile, deck, or multiple decks. As described above, various states may be stored by charging or discharging the capacitor of the memory cell.

The stored state of the capacitor of the memory cell may be read or sensed by operating various elements. The capacitor may be in electronic communication with a digit line. The capacitor may be isolated from digit line when selection component is deactivated, and capacitor can be connected to digit line when selection component is activated (e.g., by the word line). Activating selection component may be referred to as selecting a memory cell. In some cases, the selection component may be a transistor and its operation may be controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. The word line may activate the selection component; for example, a voltage applied to a transistor gate of a word line may connect a capacitor of a memory cell with a digit line.

The change in voltage of a digit line may, in some examples, depend on its intrinsic capacitance. That is, as charge flows through the digit line, some finite charge may be stored in the digit line and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical characteristics, including the dimensions, of the digit line. The digit line may connect many memory cells of the array of memory cells <NUM> so digit line may have a length that results in a non-negligible capacitance (e.g., on the order of picofarads (pF)). The resulting voltage of the digit line may then be compared to a reference voltage (e.g., a voltage of a reference line) by a sense component in order to determine the stored logic state in the memory cell. Other sensing processes may be used.

The sense component may include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. The sense component may include a sense amplifier that receives and compares the voltage of the digit line and a reference line, which may be a reference voltage. The sense amplifier output may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For instance, if the digit line has a higher voltage than reference line, then the sense amplifier output may be driven to a positive supply voltage.

In some cases, the sense amplifier may drive the digit line to the supply voltage. The sense component may then latch the output of the sense amplifier and/or the voltage of the digit line, which may be used to determine the stored state in the memory cell (e.g., logic ` <NUM>'). Alternatively, for example, if the digit line has a lower voltage than reference line, the sense amplifier output may be driven to a negative or ground voltage. The sense component may similarly latch the sense amplifier output to determine the stored state in the memory cell (e.g., logic '<NUM>'). The latched logic state of the memory cell may then be output, for example, through a column decoder.

To write a memory cell, a voltage may be applied across the capacitor of the memory cell. Various methods may be used to write a memory cell. In one example, the selection component may be activated through a word line in order to electrically connect the capacitor to the digit line. A voltage may be applied across the capacitor by controlling the voltage of the cell plate (e.g., through a plate line) and the cell bottom (e.g., through a digit line). To write a logic `<NUM>', the cell plate may be taken high (e.g., a voltage level may be increased above a predetermined voltage that is a "high" voltage). That is, a positive voltage may be applied to plate line, and the cell bottom may be taken low (e.g., virtually grounding or applying a negative voltage to the digit line). The opposite process may be performed to write a logic ` <NUM>', where the cell plate is taken low and the cell bottom is taken high.

The controller <NUM> may control the operation (e.g., read, write, re-write, refresh, decharge, etc.) of memory cells in the array of memory cells <NUM> through the various components (e.g., row decoders, column decoders, and sense components). In some cases, one or more of the row decoder, column decoder, and sense component may be co-located with the controller <NUM>. Controller <NUM> may generate row and column address signals in order to activate the desired word line and digit line. In other examples, controller <NUM> may generate and control various voltages or currents used during the operation of memory device <NUM>. For example, controller <NUM> may apply discharge voltages to a word line or digit line after accessing one or more memory cells. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory device <NUM>. Further, one, multiple, or all memory cells within the array of memory cells <NUM> may be accessed simultaneously. For example, multiple memory cells or all memory cells of the array of memory cells <NUM> may be accessed simultaneously during a reset operation in which multiple memory cells or all memory cells may be set to a single logic state (e.g., logic '<NUM>').

Each of the plurality of channels <NUM> may be configured to couple the array of memory cells <NUM> with the controller <NUM>. In some examples, each of the plurality of channels <NUM> may be referred to as a plurality of legs. In some memory devices, the rate of data transfer between the memory device and a host device (e.g., a personal computer or other computing device) may be limited by the rate of data transferred across the plurality of channels <NUM>. In some examples, the memory device <NUM> may include a large number of high-resistance channels. By increasing the number of channels, the amount of data transferred in the memory device <NUM> may be increased without increasing the data rate of the transfer. In some examples, the plurality of channels <NUM> may be referred to as a wide system interface. Each of the plurality of channels <NUM> may be part of an interposer positioned between the array of memory cells <NUM> and the controller <NUM>. In some examples, one or more of the channels <NUM> may be unidirectional and in other examples, one or more of the channels <NUM> may be bidirectional.

In some examples, at least some (and in some cases, each) of the signaling interfaces <NUM> may generate and/or decode signals communicated using the plurality of channels <NUM>. A signaling interface <NUM> may be associated with each component that is coupled with the plurality of channels <NUM>. The signaling interface <NUM> may be configured to generate and/or decode multi-level signals, binary signals, or both (e.g., simultaneously). Each signaling interface <NUM> may include a driver <NUM> and a receiver <NUM>. In some examples, each driver <NUM> may be referred to as a multi-leg driver.

Each driver <NUM> may be configured to generate a multi-level signal based on a logic state that includes multiple bits. For example, driver <NUM> may use PAM4 signaling techniques (or other type of multi-level signaling techniques) to generate a signal having an amplitude that corresponds to the logic state. The driver <NUM> may be configured to receive data using a single input line. In some cases, the driver <NUM> may include a first input line for a first bit of data (e.g., most-significant bit), a second input line for a second bit of data (e.g., least-significant bit). In some circumstances, the driver <NUM> may be configured to generate a binary-level signal (e.g., a NRZ signal). In some cases, the driver <NUM> may use single-ended signaling to generate the multi-level signal. In such cases, the multi-level signal may be transmitted without a differential.

Each receiver <NUM> may be configured to determine a logic state represented by a symbol of the multi-level signal received using the plurality of channels <NUM>. In some cases, the receiver <NUM> may determine an amplitude of the received multi-level signal. Based on the determined amplitude, the receiver <NUM> may determine the logic state represented by the multi-level signal. The receiver <NUM> may be configured to output data using a single output line. In some cases, the receiver <NUM> may include a first output line for a first bit of data (e.g., most-significant bit), a second output line for a second bit of data (e.g., least-significant bit). In some circumstances, the receiver <NUM> may be configured to decode a binary-level signal (e.g., a NRZ signal). For example, each of receivers <NUM> may be coupled with a transmitter (not illustrated) via a plurality of channels <NUM>. Each of the channels <NUM> may be configured to output data that includes multiple bits, and the controller <NUM> may be configured to determine an output impedance offset between the data output. One or more transistors (not separately illustrated) may be configured to adjust a resistance level one or more of the pluralities of channels <NUM>. This adjustment may be based at least in part on the determined output impedance offset.

The receiver <NUM> may be configured to receive and/or decode a multi-level signal or a binary-level signal. For example, the receiver <NUM> of a connected component (e.g., an array of memory cells <NUM> or a controller <NUM> of a memory device <NUM>) may receive a signal using one or more plurality of channels (e.g., channels <NUM>). The receiver <NUM> may be configured to output one or more bits of data based on a received signal. The receiver <NUM> may include one or more comparators and a decoder.

The one or more comparators may be configured to compare the received signal to one or more reference voltages. The number of comparators may be related to a number of symbols (e.g., amplitude levels) that may be represented in the received signal. For example, if the received signal is a multi-level signal configured to have four symbols (e.g., a PAM4 signal), the receiver <NUM> may include three comparators and three reference voltages.

Each comparator may output a signal based on whether the received signal is greater than or less than the reference voltage. Said another way, the comparator may determine whether received signal satisfies a voltage threshold defined by the comparator and its associated reference voltage. For example, the comparator may output a high voltage if the received signal is greater than the associated reference signal and the comparator may output a low voltage if the received signal is less than the associated reference signal (or vice-versa). The decoder may receive the outputs of the comparators. The reference voltages may be selected to discriminate between the expected amplitude levels of the received signal. For example, reference voltages may be selected to be within an eye opening <NUM> of an eye in an eye diagram between two amplitude levels (e.g., amplitudes <NUM>-a and <NUM>-b).

The decoder may be configured to determine a logic state represented by a symbol of the received signal based on the outputs of the comparators. The combination of the outputs of the comparators may be used to determine an amplitude of the received signal. In some cases, the decoder may be an example of a look-up table that indexes the outputs of the comparators to logic states of the received signal.

In some examples, if the received signal is less than all of the reference voltages, the decoder may determine that a logic state '<NUM>' is represented by a symbol of the received signal. If the received signal is greater than one reference voltage but less than two of the reference voltages, the decoder may determine that a logic state '<NUM>' is represented by a symbol of the received signal. If the received signal is greater than two of the reference voltages but less than one of the reference voltages, the decoder may determine that a logic state ` <NUM>' is represented by a symbol of the received signal. If the received signal is greater than all of the reference voltages, the decoder may determine that a logic state '<NUM>' is represented by a symbol of the received signal. It should be appreciated that the mapping of logic states to amplitudes may be modified based on design choices.

In some cases, the receiver <NUM> may be configured to selectively decode binary signals (e.g., NRZ signaling) or multi-level signals (e.g., PAM4 or PAM8). In some cases, the receiver <NUM> or a connected component may be configured to select one or more channels or one or more groups of channels to listen for the received signal from another component of the memory device.

In some cases, each of the signaling interfaces <NUM> may be configured to selectively generate and/or decode different types of signals (e.g., NRZ signals, PAM4 signals, PAM8 signals, etc.). Different types of signals may be used based on the operational circumstances of the memory device <NUM>. For example, binary signaling may use less power than multi-level signaling and may be used when power consumption is driving consideration for performance. Other performance factors that may be used to determine which type of signaling should be used may include clock considerations, data strobe (DQS) considerations, circuit capabilities, bandwidth considerations, jitter considerations, or combinations thereof. In some cases, the controller <NUM> may be configured to select the type of signal, and the signaling interfaces <NUM> may be configured to implement the selection based on instructions received from the controller <NUM>. In some cases, each of the signaling interfaces <NUM> may be configured to implement coding functions such as error detection procedures, error correction procedures, data bus inversion procedures, or combinations thereof.

In some cases, the signaling interfaces <NUM> may be configured to communicate multi-level signals and binary signals simultaneously. In such cases, a signaling interface <NUM> may include more than one set of drivers <NUM> and receivers <NUM>. For example, a signaling interface <NUM> may be configured to communicate a first set of data (e.g., a control signal) using a binary-level signal using a first set of channels <NUM> at the same time that a second set of data (e.g., user information) is being communicated using a multi-level signal using a second set of channels <NUM>.

<FIG> illustrates an example of an eye diagram <NUM> representing a multi-level signal in accordance with various embodiments of the present disclosure. The eye diagram <NUM> may be used to indicate the quality of signals in high-speed transmissions and may represent four symbols of a signal (e.g., '<NUM>', '<NUM>', '<NUM>', or '<NUM>'). In some examples, each of the four symbols may be represented by a different voltage amplitude (e.g., amplitudes <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d). In other examples, the eye diagram <NUM> may represent a PAM4 signal that may be used to communicate data in a memory device (e.g., memory device <NUM> as described with reference to <FIG>). The eye diagram <NUM> may be used to provide a visual indication of the health of the signal integrity, and may indicate noise margins of the data signal. The noise margin may, for example, refer to an amount by which the signal exceeds the ideal boundaries of the amplitudes <NUM>.

To generate the eye diagram <NUM>, an oscilloscope or other computing device may sample a digital signal according to a sample period <NUM> (e.g., a unit interval or a bit period). The sample period <NUM> may be defined by a clock associated with the transmission of the measured signal. In some examples, the oscilloscope or other computing device may measure the voltage level of the signal during the sample period <NUM> to form a trace <NUM>. Noise and other factors can result in the traces <NUM> measured from the signal deviating from a set of ideal step functions. By overlaying a plurality of traces <NUM>, various characteristics about the measured signal may be determined. For example, the eye diagram <NUM> may be used to identify a number of characteristics of a communication signals such as jitter, cross talk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye may indicate a noisy and/or unpredictable signal.

In some examples, the eye diagram <NUM> may indicate a width <NUM>. The width <NUM> of an eye in the eye diagram <NUM> may be used to indicate a timing synchronization of the measured signal or jitter effects of the measured signal. In some examples, comparing the width <NUM> to the sample period <NUM> may provide a measurement of SNR of the measured signal. Each eye in an eye diagram may have a unique width based on the characteristics of the measured signal. Various encoding and decoding techniques may be used to modify the width <NUM> of the measured signal.

In other examples, the eye diagram <NUM> may indicate an ideal sampling time <NUM> for determining the value of a logic state represented by a symbol of the measured signal. For example, determining a correct time for sampling data (e.g., timing synchronization) of the measured signal may be important to minimize the error rate in detection of the signal. For example, if a computing device samples a signal during a transition time (e.g., a rise time <NUM> or a fall time <NUM>), many errors may be introduced by the decoder into the data represented by a symbol of the signal. Various encoding and decoding techniques may be used to modify the ideal sampling time <NUM> of the measured signal.

The eye diagram <NUM> may be used to identify a rise time <NUM> and/or a fall time <NUM> for transitions from a first amplitude <NUM> to a second amplitude <NUM>. The slope of the trace <NUM> during the rise time <NUM> or fall time <NUM> may indicate the signal's sensitivity to timing error. For example, the steeper the slope of the trace <NUM> (e.g., the smaller the rise time <NUM> and/or the fall time <NUM>), the more ideal the transitions between amplitudes <NUM> are. Various encoding and decoding techniques may be used to modify the rise time <NUM> and/or fall time <NUM> of the measured signal.

In some examples, the eye diagram <NUM> may be used to identify an amount of jitter <NUM> in the measured signal. Jitter <NUM> may refer to a timing error that results from a misalignment of rise and fall times. Jitter <NUM> occurs when a rising edge or falling edge occurs at a time that is different from an ideal time defined by the data clock. Jitter <NUM> may be caused by signal reflections, intersymbol interference, crosstalk, process-voltage-temperature (PVT) variations, random jitter, additive noise, or combinations thereof. Various encoding and decoding techniques may be used to modify the jitter <NUM> of the measured signal. In some cases, the jitter <NUM> for each signal level or each eye may be different.

In other examples, the eye diagram <NUM> may indicate an eye opening <NUM>, which may represent a peak-to-peak voltage difference between the various amplitudes <NUM>. The eye opening <NUM> may be related to a voltage margin for discriminating between different amplitudes <NUM> of the measured signal. The smaller the margin, the more difficult it may be to discriminate between neighboring amplitudes, and the more errors that may be introduced due to noise. In some cases, a receiver (e.g., receiver <NUM> as described with reference to <FIG>) of the signal may compare the signal to one or more threshold voltages positioned between the various amplitudes <NUM>. In other cases, the larger the eye opening <NUM>, the less likely it is that noise will cause the one or more voltage thresholds to be satisfied in error. The eye opening <NUM> may be used indicate an amount of additive noise in the measured signal, and may be used to determine a SNR of the measured signal. Various encoding and decoding techniques may be used to modify the eye opening <NUM> of the measured signal. In some cases, the eye opening <NUM> for each eye may be different. In such cases, the eyes of the multi-level signal may not be identical.

In other examples, the eye diagram <NUM> may indicate distortion <NUM>. The distortion <NUM> may represent overshoot and/or undershoot of the measured signal due to noise or interruptions in the signal path. As a signal settles into a new amplitude (e.g., amplitude <NUM>-b) from an old amplitude (e.g., an amplitude <NUM>-c), the signal may overshoot and/or undershoot the new amplitude level. In some examples, distortion <NUM> may be caused by this overshooting and/or undershooting, and may be caused additive noise in the signal or interruptions in the signal path. Each eye in an eye diagram may have a unique opening based on the characteristics of the measured signal. Various encoding and decoding techniques may be used to modify the distortion <NUM> of the measured signal. In some cases, the distortion <NUM> for each signal level or each eye may be different.

The locations of the characteristics of the eye diagram <NUM> shown in <FIG> are for illustrative purposes only. Characteristics such as width <NUM>, sampling time <NUM>, rise time <NUM>, fall time <NUM>, jitter <NUM>, eye opening <NUM>, and/or distortion <NUM> may occur in other parts of the eye diagram <NUM> not specifically indicated in <FIG>.

<FIG> illustrates an example of a transmission circuit <NUM> in accordance with various embodiments of the present disclosure. The transmission circuit <NUM> may be configured to generate a multi-level signal or a binary-level signal based on a one or more bits of data. The transmission circuit <NUM> may be an example of the driver <NUM> as described with reference to <FIG>. The transmission circuit <NUM> may include a driver <NUM>, a first-in first-out (FIFO) component <NUM>, a multiplexer <NUM>, and a pre-driver <NUM>.

The driver <NUM> may include a pull-up circuit <NUM> and a pull-down circuit <NUM>. The transmission circuit <NUM> may be configured to output a signal to a plurality of channels (e.g., channels <NUM> described with reference to <FIG>) based on a logic state received from the memory core <NUM>. In some examples, the transmission circuit <NUM> may be coupled with memory core <NUM>, which may be an example of a controller <NUM> or an array of memory cells <NUM> of memory cells as described with reference to <FIG>.

In some examples, the transmission circuit <NUM> may operate based on data received from memory core <NUM>. In some examples, the identified data may include one or more bits of information. In other examples, the transmission circuit <NUM> or the memory controller may identify a desired amplitude level based on the identified data. The transmission circuit <NUM> or the memory controller may identify a current amplitude level of the output signal of the transmission circuit <NUM> and, in some examples, the transmission circuit <NUM> or the memory controller may determine a set of instructions for the pull-up circuit <NUM> and/or the pull-down circuit <NUM> to transition from the current amplitude level to the desired amplitude level of the output signal. Additionally or alternatively, for example, the instructions may include characteristics of gate voltages (e.g., amplitude of gate voltages, timing of gate voltages, and/or pattern of gate voltage activation) to apply to one or more switching components that couple an output <NUM> of the driver <NUM> to two or more voltage sources. The instructions may be configured to cause the output signal to be "pulled-up" or "pulled down" to the desired amplitude level.

In some examples, memory core <NUM> may be coupled with the FIFO component <NUM>. For example, the data transmitted from memory core <NUM> may be routed through FIFO component <NUM>. FIFO component <NUM> may, for example, organize and/or manipulate the data transmitted from memory core <NUM>. In some examples, FIFO component <NUM> may manipulate and/or organize the data according to time and prioritization. Thus, FIFO component <NUM> may process data on a first-come, first-served basis. In some examples, FIFO component <NUM> may utilize a same clock as a memory controller (e.g., controller <NUM> as described with reference to <FIG>). In other examples, FIFO component <NUM> may utilize separate clocks for reading and writing operations.

In other examples, data transmitted from memory core <NUM> and through FIFO component <NUM> may be multiplexed via a multiplexer <NUM>. Multiplexer <NUM> may be coupled with both memory core <NUM> and FIFO component <NUM>. In some examples, the multiplexer <NUM> may select one of several input signals received from FIFO component <NUM>. Upon selecting an input signal, the multiplexer <NUM> may forward the signal to pre-driver <NUM>. Pre-driver <NUM>, for example, may be coupled with multiplexer <NUM> and may utilize a biasing circuit to generate a low-power signal. In some examples, the signal generated via pre-driver <NUM> may be transmitted to pull-up circuit <NUM> and/or pull-down circuit <NUM>. In some cases, the pre-driver <NUM> may include one or more invertors tied to the output of the multiplexer <NUM> to generate gate signals for switching components of the driver <NUM>.

The pull-up circuit <NUM> may be configured to bias an output signal of the driver <NUM> from a first amplitude to a second amplitude that is greater than the first amplitude. For example, if the output signal is at a first amplitude <NUM>-b as described with reference to <FIG>, the pull-up circuit <NUM> may be used to transition the output signal to either of amplitudes <NUM>-c or <NUM>-d. The pull-up circuit <NUM> may be coupled to a first voltage source using one or more switching components (e.g., a transistor). The first voltage source may have a greater voltage than a second voltage source associated with the pull-down circuit <NUM>.

The pull-down circuit <NUM> may be configured to bias an output signal of the driver <NUM> from a first amplitude to a second amplitude that is less than the first amplitude. For example, if the output signal is of a first amplitude <NUM>-b, as described with reference to <FIG>, the pull-down circuit <NUM> may be used to transition the output signal to amplitude <NUM>-a. The pull-down circuit <NUM> may be coupled to a second voltage source using one or more switching components (e.g., a transistor). The second voltage source may have a lesser voltage than the first voltage source associated with the pull-up circuit <NUM>. In some cases, the pull-down circuit <NUM> selectively couples the output of the driver <NUM> with a ground or virtual ground.

In some cases, the design of the pull-up circuit <NUM> and/or the pull-down circuit <NUM> may affect various characteristics of the output signal as represented by an eye diagram (e.g., eye diagram <NUM> as described with reference to <FIG>). For example, the design of the pull-up circuit <NUM> and/or the pull-down circuit <NUM> may affect eye width (e.g., width <NUM> as described with reference to <FIG>), eye opening (e.g., eye opening <NUM> as described with reference to <FIG>), distortion (e.g., distortion <NUM> as described with reference to <FIG>), jitter (e.g., jitter <NUM> as described with reference to <FIG>), the location of the amplitude(s), other characteristics, or combinations thereof.

In some cases, the transmission circuit <NUM> may be configured to selectively generate binary signals (e.g., NRZ signaling) or multi-level signals (e.g., PAM4 or PAM8). In other examples, the transmission circuit <NUM> may be configured to adjust a transmit power of the output signal of the driver <NUM>. Additionally or alternatively, for example, the transmission circuit <NUM> or a memory controller (e.g., controller <NUM> as described with reference to <FIG>) may be configured to select one or more channels or one or more groups of channels to communicate the output signal to another component of the memory device. In some cases, a plurality of drivers may be used to generate a multi-level signal (e.g., a PAM4 signal) across a channel. The plurality of drivers may be configured to cooperate to generate the multi-level signal based on commands received from a controller.

<FIG> illustrates an example of a driver <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The driver <NUM> is an example of a multi-level signal driver. The driver <NUM> includes a pull-up circuit <NUM> and a pull-down circuit <NUM>. The driver <NUM> shows examples of circuits <NUM>, <NUM> that include a first switching component <NUM> of a first polarity and a second switching component <NUM> of a second polarity that is opposite the first polarity. Using two switching components of opposite polarity in a multi-level driver <NUM> improves one or more characteristics of a multi-level signal output to one or more communication channels (e.g., channels <NUM>). The driver <NUM> is an example of drivers <NUM>, <NUM> described with reference to <FIG> and <FIG>. The pull-up circuit <NUM> is an example of the pull-up circuit <NUM> described with reference to <FIG>. The pull-down circuit <NUM> may be an example of the pull-down circuit <NUM> described with reference to <FIG>.

The driver <NUM> has an input <NUM> coupled with a connected component from which the driver <NUM> receives data (e.g., a plurality of bits) that is to be transmitted or commands for generating a multi-level signal based on a plurality of bits. The connected component is referred to a controller (e.g., controller <NUM>) or a different more granular component such as a pre-driver, a multiplexer, a FIFO component, a memory core, or a combination thereof. In some cases, the input <NUM> may receive gate signals for the switching components <NUM>, <NUM> from a controller. The driver <NUM> has an output <NUM> coupled with one or more communication channels (e.g., channels <NUM>) from which the driver <NUM> outputs a multi-level signal.

The pull-up circuit <NUM> includes a first switching component <NUM>-a having a first polarity and a second switching component <NUM>-a having a second polarity opposite the first polarity. For example, the first switching component <NUM>-a may be an example of a positive metal-oxide semiconductor (pmos) transistor and the second switching component <NUM>-a may be an example of a negative metal-oxide semiconductor (nmos) transistor.

The switching components <NUM>-a, <NUM>-a couple the output <NUM> of the driver <NUM> with a voltage source <NUM>. The switching components <NUM>-a, <NUM>-a are arranged in a parallel configuration such that the first switching component <NUM>-a is coupled with the output <NUM> and the voltage source <NUM> in parallel to the second switching component <NUM>-a. The voltage source <NUM> may be an example of a positive voltage source (e.g., Vdd) in the memory device.

The pull-up circuit <NUM> includes resistors <NUM> positioned in series with a switching component <NUM>-a, <NUM>-a between the voltage source <NUM> and the output <NUM>. In some cases, the values of the resistors <NUM> and/or the switching components <NUM>-a, <NUM>-a may be set or adjusted to vary characteristics of the multi-level signal output by the driver <NUM>. The resistors <NUM> may be positioned either between their respective switching component and the output <NUM> or between their respective switching component and the voltage source <NUM>.

The switching components <NUM>-a, <NUM>-a may include a gate <NUM> that receives a gate signal <NUM> from a controller or another connected component. In some cases, the gate signals <NUM> for each switching component <NUM>, <NUM> may be independently controlled. In some cases, the gate signals <NUM> for switching components <NUM> of the first polarity are independently controlled from the switching components <NUM> of the second polarity. In some cases, the gate signal <NUM>-b for the first switching component <NUM>-a may be the complement of the gate signal <NUM>-a for the second switching component <NUM>-a. In some cases, the first switching component <NUM>-a may be activated before or after the second switching component <NUM>-a is activated such that the timing of the two switching components is offset. In some cases, the first switching component <NUM>-a may be activated for a first time period that overlaps with the second time period during which the second switching component <NUM>-a is activated.

The pull-up circuit <NUM> may be configured to raise (or "pull-up") the amplitude of the multi-level signal from a current level to a target level higher than the current level. A controller may be configured to selectively activate the switching components <NUM>-a, <NUM>-a thereby coupling the voltage source <NUM> with the output <NUM>.

A controller or the driver <NUM> may identify data to be transmitted to another component of a memory device. Before generating the multi-level signal, the controller or the driver <NUM> may identify a target amplitude of the multi-level signal and/or a current amplitude level of the multi-level signal. The controller or the driver <NUM> may determine whether the current amplitude should be raised or lowered to reach the target amplitude. The controller or the driver <NUM> may determine one or more driver parameters for operating the driver <NUM> to generate the desired multi-level signal. Examples of the one or more driver parameters may include a timing for activating a pull-up circuit <NUM> or a pull-down circuit <NUM> or a combination of both, gate voltages for activating switching components of the pull-up circuit <NUM> and/or the pull-down circuit <NUM>, how many switching components <NUM>, <NUM> of each circuit <NUM>, <NUM> may be activated (e.g., less than all of the switching components may be activated in a given operation), independent control parameters for the first switching component(s) <NUM>-a of the first polarity and the second switching component(s) <NUM>-a of the second polarity (e.g., different switching components in the pull-up circuit <NUM> or the pull-down circuit <NUM> may be independently controlled), or a combination thereof.

In some cases, however, a relationship between an output voltage and an output current of the driver <NUM> may not be linear over the entire range of output values of the multi-level signal when using one or more switching components having a single polarity (e.g., see <FIG> and its related description). Non-linearity between the output voltage and the output current of the driver may generate unwanted characteristics of the multi-level signal output by the driver <NUM>. For example, a non-linear relationship create distortion in the multi-level signal, overshoot and/or undershoot in the multi-level signal, jitter in the multi-level signal, inconsistent margins between different amplitude levels in the multi-level signal (different eye opening size for each eye), narrower eye widths of each eye of the multi-level signal, varying rise times and/or fall times of the multi-level signal, other undesired effects, or a combination thereof (e.g., see <FIG> and its related description).

By coupling a first switching component <NUM>-a of an opposite polarity (e.g., pmos transistor) in parallel with the second switching component <NUM>-a (e.g., nmos transistor), one or more undesired characteristics of the multi-level signal may be mitigated. Some of this effect may be caused at least in part by the relationship between the output voltage and the output current becoming more linear across the range of output voltages of the multi-level signal.

The pull-down circuit <NUM> may also include a first switching component <NUM>-b having a first polarity and a second switching component <NUM>-b having a second polarity opposite the first polarity. For example, the first switching component <NUM>-b may be an example of a positive metal-oxide semiconductor (pmos) transistor and the second switching component <NUM>-b may be an example of a negative metal-oxide semiconductor (nmos) transistor.

The switching components <NUM>-b, <NUM>-b may couple the output <NUM> of the driver <NUM> with a ground <NUM>. In some cases, the ground <NUM> may be an example of a virtual ground or a voltage source having voltage level (e.g., Vss) that is less than a voltage level of the voltage source <NUM>. In some cases, the switching components <NUM>-b, <NUM>-b may be arranged in a parallel configuration such that the first switching component <NUM>-b may be coupled with the output <NUM> and the ground <NUM> in parallel to the second switching component <NUM>-b.

The pull-down circuit <NUM> may include one or more resistors <NUM> positioned in series with a switching component <NUM>-b, <NUM>-b between the voltage source <NUM> and the output <NUM>. In some cases, the values of the resistors <NUM> and/or the switching components <NUM>-b, <NUM>-b may be set or adjusted to vary characteristics of the multi-level signal output by the driver <NUM>. The resistors <NUM> may be positioned either between their respective switching component and the output <NUM> or between their respective switching component and the ground <NUM>.

The pull-down circuit <NUM> may be operated in a similar manner as the pull-up circuit <NUM>. As such a full description of the operation of the pull-down circuit <NUM> is not given here. It should be appreciated that operations of the pull-up circuit <NUM> may be modified when applied to the pull-down circuit <NUM>.

During some operations, the driver <NUM> may use both the pull-up circuit <NUM> and the pull-down circuit <NUM> to reach the target amplitude of the multi-level signal. In such cases, a controller or the driver <NUM> may determine relative timings for operating pull-up circuit <NUM> and the pull-down circuit <NUM> in the same procedure for generating an amplitude of the multi-level signal.

In some cases, a gate <NUM> of at least one switching component of the pull-up circuit <NUM> may be coupled to a gate <NUM> of at least one switching component of the pull-down circuit <NUM>. For example, the gate <NUM> of the first switching component <NUM>-a of the pull-up circuit <NUM> may be coupled with the gate <NUM> of the second switching component <NUM>-b of the pull-down circuit <NUM>. In such examples, the same gate signal <NUM> may be used to activate/deactivate both the switching components <NUM>-a, <NUM>-b. In some examples, the gate <NUM> of the second switching component <NUM>-a of the pull-up circuit <NUM> may be coupled with the gate <NUM> of the first switching component <NUM>-b of the pull-down circuit <NUM>. In such examples, the same gate signal <NUM> may be used to activate/deactivate both the switching components <NUM>-b, <NUM>-a.

In one example, a device or system may include an array of memory cells, a controller coupled with the array of memory cells, and a driver coupled with the controller and configured to generate a multi-level signal related to the array of memory cells, the driver including a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity.

In some examples of the device or system described above, the first switching component and the second switching component may be configured to generate a linear output current relative to an output voltage of the first switching component and the second switching component. In some examples of the device or system described above, the first switching component is an example of a pmos transistor and the second switching component is an example of an nmos transistor.

In some examples of the device or system described above, the first switching component and the second switching component may be coupled with a common voltage source and an output node of the driver in parallel.

In some examples of the device or system described above, the driver further includes a pull-down circuit including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity. In some examples of the device or system described above, the third switching component comprises a pmos transistor and the fourth switching component comprises an nmos transistor. In some examples of the device or system described above, the third switching component and the fourth switching component may be coupled with a common ground node and an output node of the driver in parallel.

Some examples of the device or system described above may also include a gate of the first switching component of the pull-up circuit may be coupled with a gate of the fourth switching component of the pull-down circuit. Some examples of the device or system described above may also include a gate of the second switching component of the pull-up circuit may be coupled with a gate of the third switching component of the pull-down circuit.

In some examples of the device or system described above, the multi-level signal may be encoded with information using a PAM modulation scheme, such as PAM4 or PAM8.

<FIG> illustrates an example of a driver <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The driver <NUM> may be an example of a multi-level signal driver. The driver <NUM> may include a pull-up circuit <NUM> and a pull-down circuit <NUM>. The driver <NUM> shows an example where one of the pull-up circuit <NUM> or the pull-down circuit <NUM> includes a first switching component <NUM>-a of a first polarity (e.g., nmos transistor) and a second switching component <NUM> of a second polarity that is opposite the first polarity (e.g., pmos transistor) and the other one of the pull-up circuit <NUM> or the pull-down circuit <NUM> only includes a first switching component <NUM>-b of the first polarity (e.g., nmos transistor). While the driver <NUM> illustrates the pull-up circuit <NUM> having one configuration and the pull-down circuit <NUM> having the other configuration, such configurations may be switched in other implementations. Such a configuration for the driver <NUM> may use less power and take less die space than the driver <NUM> while still achieving many of the same desired characteristics of multi-level signal achieved by the driver <NUM>.

The driver <NUM> may be an example of drivers <NUM>, <NUM>, <NUM> described with reference to <FIG> and <FIG>. The pull-up circuit <NUM> may be an example of the pull-up circuits <NUM>, <NUM> described with reference to <FIG>. The pull-down circuit <NUM> may be an example of the pull-down circuits <NUM>, <NUM> described with reference to <FIG>. As such, a full description of the driver <NUM>, the pull-up circuit <NUM>, the pull-down circuit <NUM>, and their various components is not repeated here.

In some case, a gate of the second switching component <NUM> of the pull-up circuit <NUM> may be coupled with a gate of the first switching component <NUM>-b of the pull-down circuit <NUM>. In such cases, the same gate signal may be used to activate/deactivate both the switching components <NUM>-b, <NUM>. In this manner, only one of the pull-up circuit <NUM> or the pull-down circuit <NUM> may be activated at a time.

<FIG> illustrates an example of a driver <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The driver <NUM> may be an example of a multi-level signal driver. The driver <NUM> may include a pull-up circuit <NUM> and a pull-down circuit <NUM>. The driver <NUM> shows an example where one of the pull-up circuit <NUM> or the pull-down circuit <NUM> includes a first switching component <NUM> of a first polarity (e.g., nmos transistor) and a second switching component <NUM>-a of a second polarity that is opposite the first polarity (e.g., pmos transistor) and the other one of the pull-up circuit <NUM> or the pull-down circuit <NUM> only includes a second switching component <NUM>-b of the second polarity (e.g., pmos transistor). While the driver <NUM> illustrates the pull-up circuit <NUM> having one configuration and the pull-down circuit <NUM> having the other configuration, such configurations may be switched in other implementations. Such a configuration for the driver <NUM> may use less power and take less die space than the driver <NUM> while still achieving many of the same desired characteristics of multi-level signal achieved by the driver <NUM>.

In some case, a gate of the first switching component <NUM> of the pull-up circuit <NUM> may be coupled with a gate of the second switching component <NUM>-b of the pull-down circuit <NUM>. In such cases, the same gate signal may be used to activate/deactivate both the switching components <NUM>, <NUM>-b. In this manner, only one of the pull-up circuit <NUM> or the pull-down circuit <NUM> may be activated at a time.

<FIG> illustrates an example of a driver component <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The driver component <NUM> may be an example of a pull-up circuit (e.g., pull-up circuits <NUM>, <NUM>, <NUM>, <NUM>) or a pull-down circuit (e.g., pull-down circuits <NUM>, <NUM>, <NUM>, <NUM>) of a driver (e.g., driver <NUM>, <NUM>, <NUM>, <NUM>, <NUM>). In each of the drivers <NUM>, <NUM>, <NUM> described with reference to <FIG>, the drivers included at most one switching component of a given polarity. The driver component <NUM> illustrates that a pull-up circuit or a pull-down circuit of a driver may include any number of switching components of a first polarity and any number of switching components of a second polarity.

The driver component <NUM> may include a first set <NUM> of switching components <NUM> having a first polarity and a second set <NUM> of switching components <NUM> having a second polarity different from the first polarity. In some cases, the first set <NUM> has an equal number of switching components as the second set <NUM>. In some cases, the first set <NUM> may have more or less switching components than the second set <NUM>.

In some cases, the gates of the first set <NUM> of switching components <NUM> may be coupled such that the first set <NUM> of switching components <NUM> may be controlled by a single gate signal <NUM> from a controller. In some cases, the gates of the second set <NUM> of switching components <NUM> may be coupled such that the second set <NUM> of switching components <NUM> may be controlled by a single gate signal <NUM> from a controller. In some cases, the gate signal <NUM> for the first set <NUM> may be the complement of the gate signal <NUM> for the second set <NUM>.

The switching components <NUM>, <NUM> may couple an output <NUM> of the driver to a source <NUM>. The source <NUM> may be a voltage source or ground depending on whether the driver component <NUM> is implemented as a pull-up circuit or a pull-down circuit. Various features of the driver component <NUM> may be implemented in a pull-up circuit and a pull-down circuit simultaneously.

In some cases, the number of switching components <NUM>, <NUM> in a pull-up circuit may be equal to a number of switching components in a pull-down circuit. In some examples, the number of switching components <NUM> in the first set <NUM> in a pull-up circuit may be equal to the number of switching components <NUM> in the second set <NUM> of the pull-down circuit. In such examples, each switching component <NUM> of a first polarity in a pull-up circuit may be paired with a switching component <NUM> of a second polarity in a pull-down circuit, or vice-versa. In some cases, the gates of the switching components <NUM> of a first polarity in a pull-up circuit may be coupled with the gates of the switching components <NUM> of a second polarity in a pull-down circuit, or vice-versa. In such cases, a single gate signal may drive at least one switching component <NUM> in the pull-up circuit and at least one switching component <NUM> in the pull-down circuit, or vice-versa. In some cases, the gate of each switching component <NUM>, <NUM> may be independently controlled.

<FIG> illustrates an example of an output graph <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The output graph <NUM> shows the relationships between output current and output voltage of a driver that includes a pull-up circuit or a pull-down circuit or a combination of the two.

The output graph <NUM> includes a first curve <NUM>, a second curve <NUM>, and a third curve <NUM>. The first curve shows an ideal linear case. In an ideal output signal, the relationship between output current and output voltage across the entire range of output values may be linear. The second curve <NUM> shows a relationship between output current and output voltage of a driver that includes switching components of a single polarity (e.g., nmos transistors). The third curve <NUM> shows a relationship between output current and output voltage of driver that includes switching components of a first polarity and switching components of a second polarity opposite the first polarity (e.g., nmos transistors and pmos transistors).

Switching components of the first polarity (e.g., nmos transistors) may have a linear response across a first range of output voltages and a non-linear response across a second rage of output voltages. Switching components of the second polarity (e.g., pmos transistors) may have a linear response across a third range of output voltages and a non-linear response across a fourth range of output voltages. In some cases, the first range and the third range positioned across at least partially different output voltages and the second range and the fourth range are positioned across at least partially different output voltages. In some cases, if a circuit of a driver includes both types of switching components the different types of switching components may cooperate to generate a more linear relationship across a broader range of output voltages than a circuit that includes only one type of switching component.

<FIG> illustrates examples of eye diagrams <NUM> that supports an output driver for multi-level signaling in accordance with various embodiments of the present disclosure. The eye diagrams <NUM> include an eye diagram <NUM> that represents a multi-level signal modulated using a first modulation scheme having at least three levels generated by a driver whose pull-up and pull-down circuits include switching components of a single polarity (e.g., a single type of transistor). More specifically, the eye diagram <NUM> represents a multi-level signal modulated using a first modulation scheme having at least three levels generated by a driver whose pull-up and pull-down circuits include only nmos transistors. The eye diagrams <NUM> also include an eye diagram <NUM> that represents a multi-level signal modulated using a first modulation scheme having at least three levels generated by a driver whose pull-up and pull-down circuits include switching components of a first polarity and switching components of a second polarity opposite the first polarity. More specifically, the eye diagram <NUM> represents a multi-level signal modulated using a first modulation scheme having at least three levels generated by a driver whose pull-up and pull-down circuits include nmos transistors and pmos transistors. For example, the eye diagram <NUM> may represent a signal generated by driver <NUM> described with reference to <FIG>.

As is illustrated by a comparison between the eye diagram <NUM> and the eye diagram <NUM> having a more linear relationship between output current and output voltage may have a number of desirable effects on a multi-level signal modulated using a first modulation scheme having at least three levels generated by the driver. The effects may include less distortion, less overshoot, less undershoot, more uniform eye openings for all eyes in the eye diagram <NUM> than eyes in the eye diagram <NUM> (some openings are smaller and some are bigger), the amplitude levels of the multi-level signal may be spaced more evenly to reduce errors, less jitter, more consistent rise times and/or fall times, wider eyes, other effects, or a combination thereof.

In some cases, the characteristics of the multi-level signal output by a driver may also be influenced by values of the components in the pull-up circuit and/or the pull-down circuit. For example, the characteristics and/or values of the switching components (whether of the first polarity or the second polarity) and/or the resistors (e.g., ohms) may affect the characteristics of the multi-level signal. In some cases, the values of the switching components and the/or the resistors may be designed to achieve desired effects.

<FIG> shows a block diagram <NUM> of a driver component <NUM> that supports an output driver for multi-level signaling in accordance with embodiments of the present disclosure. The driver component <NUM> may be an example of a pull-up circuit <NUM>, <NUM>, <NUM>, <NUM>, <NUM> or a pull-down circuit <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or both found in a signaling interface <NUM> described with reference to <FIG> and <FIG>.

Driver component <NUM> and/or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the driver component <NUM> and/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The driver component <NUM> and/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, driver component <NUM> and/or at least some of its various sub-components may be a separate and distinct component in accordance with various embodiments of the present disclosure. In other examples, driver component <NUM> and/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to an I/O component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof in accordance with various embodiments of the present disclosure.

The driver component <NUM> may include biasing component <NUM>, timing component <NUM>, information manager <NUM>, pull-up circuit <NUM>, multi-level signal manager <NUM>, pull-down circuit <NUM>, output manager <NUM>, timing manager <NUM>, and gate voltage manager <NUM>. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses). Information manager <NUM> may identify a set of information bits to be read from an array of memory cells.

Pull-up circuit <NUM> may generate a multi-level signal modulated using a first modulation scheme having at least three levels based on the set of information bits using a driver having a pull-up circuit <NUM> including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity and activate the second switching component during a second time period that overlaps with the first time period. In some cases, generating the multi-level signal further includes: activating the first switching component during a first time period.

Multi-level signal manager <NUM> may transmit the multi-level signal to a controller of a memory device, generate a linear output current relative to an output voltage of the first, second, third, and fourth switching components using the first switching component and the second switching component. In some cases, the first switching component and the third switching component are pmos transistors. In some cases, the second switching component and the fourth switching component are nmos transistors.

Pull-down circuit <NUM> may activate the fourth switching component during a fourth time period that overlaps with the third time period. In some cases, the driver includes a pull-down circuit <NUM> including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity. In some cases, generating the multi-level signal further includes: activating the third switching component during a third time period.

Output manager <NUM> may identify an output of the multi-level signal based on the set of information bits, where generating the multi-level signal is based on the identified output.

Timing manager <NUM> may determine a timing sequence for activating the pull-up circuit and a pull-down circuit of the driver based on the identified output, where generating the multi-level signal is based on the timing sequence.

Gate voltage manager <NUM> may determine a gate voltage for each of the switching components of the driver based on the identified output, where generating the multi-level signal is based on the gate voltage.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports an output driver for multi-level signaling in accordance with embodiments of the present disclosure. Device <NUM> may be an example of or include the components of controller <NUM> as described above, e.g., with reference to <FIG>. Device <NUM> may include components for bidirectional voice and data communications including components for transmitting and receiving communications, including driver component <NUM>, memory cells <NUM>, basic input/output system (BIOS) component <NUM>, processor <NUM>, I/O controller <NUM>, and peripheral components <NUM>. These components may be in electronic communication via one or more buses (e.g., bus <NUM>).

Memory cells <NUM> may store information (i.e., in the form of a logical state) as described herein.

BIOS component <NUM> be a software component that includes BIOS operated as firmware, which may initialize and run various hardware components. BIOS component <NUM> may also manage data flow between a processor and various other components, e.g., peripheral components, input/output control component, etc. BIOS component <NUM> may include a program or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting an output driver for multi-level signaling).

Peripheral components <NUM> may include any input or output device, or an interface for such devices. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input <NUM> may represent a device or signal external to device <NUM> that provides input to device <NUM> or its components. This may include a user interface or an interface with or between other devices. In some cases, input <NUM> may be managed by I/O controller <NUM>, and may interact with device <NUM> via a peripheral component <NUM>.

Output <NUM> may also represent a device or signal external to device <NUM> configured to receive output from device <NUM> or any of its components. Examples of output <NUM> may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output <NUM> may be a peripheral element that interfaces with device <NUM> via peripheral component(s) <NUM>. In some cases, output <NUM> may be managed by I/O controller <NUM>.

The components of device <NUM> may include circuitry designed to carry out their functions. This may include various circuit elements including, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein. Device <NUM> may be a computer, a server, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a wearable electronic device, a personal electronic device, or the like. Or device <NUM> may be a portion or aspect of such a device.

<FIG> shows a flowchart illustrating a method <NUM> for an output driver for multi-level signaling in accordance with embodiments of the present disclosure. The operations of method <NUM> may be implemented by a controller <NUM> or its components as described herein. For example, the operations of method <NUM> may be performed by a driver component as described with reference to <FIG>. In some examples, a controller <NUM> may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller <NUM> may perform aspects of the functions described below using special-purpose hardware.

At block <NUM> the controller <NUM> may identify a plurality of information bits to be read from an array of memory cells. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by an information manager as described with reference to <FIG>.

At block <NUM> the controller <NUM> may generate a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using a driver having a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a pull-up circuit as described with reference to <FIG>.

At block <NUM> the controller <NUM> may transmit the multi-level signal to a controller of a memory device. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a multi-level signal manager as described with reference to <FIG>.

In some cases, the method <NUM> may be at least partially executed by an apparatus. The apparatus may include means for identifying a plurality of information bits to be read from an array of memory cells, means for generating a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using a driver having a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity, and means for transmitting the multi-level signal to a controller of a memory device.

In some cases, the method <NUM> may be at least partially executed by another apparatus. The apparatus may include a processor, memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be operable to cause the processor to identify a plurality of information bits to be read from an array of memory cells, generate a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using a driver having a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity, and transmit the multi-level signal to a controller of a memory device.

In some cases, the method <NUM> may be at least partially executed by a non-transitory computer readable medium. The non-transitory computer-readable medium may include instructions operable to cause a processor to identify a plurality of information bits to be read from an array of memory cells, generate a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using a driver having a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity, and transmit the multi-level signal to a controller of a memory device.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the driver includes a pull-down circuit including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, generating the multi-level signal further comprises: activating the first switching component during a first time period. Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for activating the second switching component during a second time period that overlaps with the first time period.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, generating the multi-level signal further comprises: activating the third switching component during a third time period. Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for activating the fourth switching component during a fourth time period that overlaps with the third time period.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for generating a linear output current relative to an output voltage of the first, second, third, and fourth switching components using the first switching component and the second switching component.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the first switching component and the third switching component may be pmos transistors. In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the second switching component and the fourth switching component may be nmos transistors.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for identifying an output of the multi-level signal based at least in part on the plurality of information bits, wherein generating the multi-level signal may be based at least in part on the identified output.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for determining a timing sequence for activating the pull-up circuit and a pull-down circuit of the driver based at least in part on the identified output, wherein generating the multi-level signal may be based at least in part on the timing sequence.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for determining a gate voltage for each of the switching components of the driver based at least in part on the identified output, wherein generating the multi-level signal may be based at least in part on the gate voltage.

In one example, a device or system may include a driver having a pull-up circuit and a pull-down circuit, the pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity, the pull-down circuit including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity, an array of memory cells configured to: identify a plurality of information bits to be read from the array of memory cells, generate a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using the pull-up circuit and the pull-down circuit of the driver, and transmit the multi-level signal to the controller.

Further, embodiments from two or more of the methods may be combined.

As used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The term "electronic communication" and "coupled" refer to a relationship between components that support electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough so as to achieve the advantages of the characteristic.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory device <NUM>.

The term "photolithography," as used herein, may refer to the process of patterning using photoresist materials and exposing such materials using electromagnetic radiation. For example, a photoresist material may be formed on a base material by, for example, spin-coating the photoresist on the base material. A pattern may be created in the photoresist by exposing the photoresist to radiation. The pattern may be defined by, for example, a photo mask that spatially delineates where the radiation exposes the photoresist. Exposed photoresist areas may then be removed, for example, by chemical treatment, leaving behind the desired pattern. In some cases, the exposed regions may remain, and the unexposed regions may be removed.

The term "isolated" refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

As used herein, the term "shorting" refers to a relationship between components in which a conductive path is established between the components via the activation of a single intermediary component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) that are in electronic communication.

The devices discussed herein, including memory device <NUM>, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A transistor or transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of') indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claim 1:
An electronic memory apparatus (<NUM>), comprising:
an array of memory cells (<NUM>);
a controller (<NUM>) coupled with the array of memory cells (<NUM>);
a driver (<NUM>, <NUM>) coupled with the controller (<NUM>) and configured to generate a multi-level signal modulated using a first modulation scheme having at least three levels based on a plurality of information bits to be read from the array of memory cells, the driver (<NUM>, <NUM>) including a pull-up circuit (<NUM>) including a first switching component (<NUM>-a) having a first gate polarity, and a first resistor (<NUM>-b) wherein the first switching component (<NUM>-a) couples an output (<NUM>) of the driver (<NUM>) with a voltage source (<NUM>) and the first resistor (<NUM>-b) is positioned in series with the first switching component (<NUM>-a) between the voltage source (<NUM>) and the output (<NUM>), and the pull-up circuit (<NUM>) including a second switching component (<NUM>-a) having a second gate polarity different than the first gate polarity, and a second resistor (<NUM>-a), wherein the second switching component (<NUM>-a) couples the output (<NUM>) of the driver (<NUM>) with the voltage source (<NUM>) and the second resistor (<NUM>-a) is positioned in series with the second switching component (<NUM>-a) between the voltage source (<NUM>) and the output (<NUM>).