Patent Description:
In digital applications there is often a need to precisely divide an unknown period. For example a period determined by the rotation of a motor needs to be divided into <NUM> steps wherein each step indicates a rotation of one degree. Other signals such a power mains signal frequency of <NUM> or <NUM> may need a similar processing. In particular incoming "rotation" signals may provide one pulse per revolution or multiple pulses per revolution. In the latter case one period may be longer than the rest, for example when a double notched sensor wheel is used or a flywheel, for example, with a missing teeth for indicating a top dead center position.

US Patent Application Publication <CIT> discloses a method and device for measuring rotation speed of rotating equipment. German Patent Application Publication <CIT> discloses a method and arrangement for digital measurement of a velocity.

<CIT> discloses a method for determining the acceleration or deceleration of a moving object.

It is therefore an object of the present application to provide for method and arrangement capable of detecting a missing pulse. This and other objects can be achieved by a method and system as defined in the independent claims. Further enhancements are characterized in the dependent claims.

According to various embodiments, a digital period divider may be configured to generate a pulse train which divides a typical period/interval into a plurality of pulses and to detect when one interval exceeds a predefined threshold, for example by <NUM>% of a typical measured interval. The exception can be identified by a fixed amount of time, for example <NUM> milliseconds, or by comparison to previously measured intervals.

For example as mentioned above, with an engine flywheel, a detector emits a series of equally-spaced pulses, except one is missing. The missing pulse can be coincident with the "top-dead-center" (TDC) position of the engine rotation, so detection may be tantamount to locating TDC in time.

The detector is incorporated into an angular timer (a. Digital Period Divider), which provides the timer for measuring the pulse interval.

<FIG> shows a block diagram of a digital period divider <NUM> operational to generate an angle clock signal from an input signal. The period of the input signal is measured by measurement unit <NUM> and divided by R by unit <NUM>. A counter <NUM> operating at a higher frequency provided by timebase <NUM> counts out the angle duration. A user can select the angle parameter of the angle clock output signal. <FIG> shows associated timing diagram wherein the top signal represents pulses received that represent a full rotation. The bottom signal represents the angle clock, for example here a division by <NUM>° has been chosen. As stated above, the signal period is measured with a fast clock provided by a time base <NUM> as shown in <FIG>. Then, the measurement count is divided by a number of angles/revolution and a pulse train of equal intervals is generated.

According to an implementation as shown in <FIG>, a measured period may be represented by R*P, wherein R is the number of angles per revolution. Again, in the example shown in <FIG>, the period is divided into four angle sections each representing <NUM>°. <FIG> also shows a round off error which may depend on the resolution provided by the time base signal. <FIG> shows an associated block diagram of such a period divider.

The input signal is fed to a counter unit <NUM> which counts out a pre-scaled period. To this end, a time base clock is divided by R through divider <NUM>. The output signal from counter unit <NUM> is latched by latch <NUM>. A divider <NUM> receiving the time base clock divides the time base clock by the latched value to generate the output signal.

<FIG> shows typical output signals provided by various devices that can be used as an input signal of the digital period divider. The digital period divider may be programmable to be able to operate with any type of signal as shown in <FIG>. For example signal A in <FIG> represents the output of a zero-cross detector coupled with an AC mains signal. Signal B may be provided by a notched wheel. Signal C may be provided by a double-notched wheel and the signal D may be provided by a toothed flywheel, which has a missing tooth.

<FIG> explains how a digital period divider may detect missing pulses to be operable to use the input signals of the third and fourth type as shown in <FIG> (signals C and D). The short intervals are measured and their duration is stored to determine when a long interval occurs. As a hardware compromise, the full period may not be measured. Rather, the period is divided into multiples of the short interval. The missing pulse may be detected based on a user defined time. In other words when a predefined number of clock cycles provided by the time base occurs without a reset caused by the input signal, a missing pulse is determined and can be generated as shown in the top of <FIG>. The bottom diagram shows an adaptive measurement according to another embodiment, wherein a period time is determined by previously measured intervals. When a currently measured interval exceeds a predetermined amount, for example <NUM>%, then a missing pulse is determined and can be generated as shown in the bottom half of <FIG>.

<FIG> shows an angle counter <NUM> according to an embodiment and <FIG> shows associated input and output signals. The angle counter can be configured to count out the angles as discussed above. For example, a system as shown in <FIG> is used with an additional counter unit <NUM> operable to count out the angles. Unit <NUM> receives the input signal and the output signal of divider <NUM>. A capture & compare unit <NUM> receives the output value from counter unit <NUM> and a threshold value and generates an output signal as a result of the comparison. Thus, because it is known when the signal begins each angle is marked and a count value can be generated that is proportional to the angle. As shown in <FIG>, the capture & compare unit <NUM> is connected to the output signal that counts out the angles to perform this function.

<FIG> shows a block diagram of a digital period divider according to various embodiments. A first counter can be formed by two counters <NUM> and <NUM> wherein the first counter having P bits concatenates with a second counter <NUM> having R bits. Thus, counter <NUM> provides the most significant bits (MSB) and counter <NUM> the least significant bits (LSB). However, according to other embodiments a single counter having P+R bits may be used. In case two counters are used, the overflow of counter <NUM> clocks the input of counter <NUM>. A high frequency clock source <NUM> is provided, for example a <NUM> system clock, that provides the count clock input signal for the first counter <NUM>, <NUM>. The first counter (or the combined counters <NUM>, <NUM>) have a reset input that receives the unknown frequency X from a frequency source <NUM>. A latch <NUM> having P bits is coupled with counter <NUM> and therefore with the MSB of the first counter. The unknown frequency triggers the load input of latch <NUM>. A second counter <NUM> having P bits receives the clock signal of the system clock at its count input. A comparator <NUM> is provided that compares the value of the latch <NUM> and the count value of the second counter <NUM>. If equal, the output of comparator <NUM> goes high (or low) and may be used to reset the second counter. Also, the output signal of comparator provides the divided clock signal X*<NUM>R.

It is widely accepted that sine, cosine and tangent computations are necessary when controlling rotary machines, but according to various embodiments a rotation pulse-to-angle conversions is provided.

Referring to <FIG>, a first application <NUM> of the period divider <NUM> shown in <FIG> is provided. As mentioned above, an unknown frequency M, for example of a motor or other rotary machine <NUM>, is provided to the period divider <NUM>. The circuit <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> measures the period of rotation, and create a clock <NUM> that is a fixed multiple of the rotational frequency. Typically, this might be one clock per degree of rotation (that is, times <NUM>), or any convenient multiple. The system may be applied to motor systems or to systems like AC power lines with a frequency of <NUM> or <NUM> or any other unknown frequency signal.

With reference to the <FIG>, the system <NUM> requires <NUM> inputs. The unknown frequency input, for example motor-pulse, supplies a reference indicating in case of a motor <NUM> that the motor <NUM> has turned one revolution. Such a signal can be obtained for example from a Hall-effect sensor or optical interrupter as will be discussed in more detail below. Some applications may supply more than one pulse per revolution, and for discussion we take this as M cps (cycles per second). The other input is a fixed clock source <NUM> of any convenient frequency, as long as it is much faster than the expected output signal. For example, a <NUM> RPM motor produces an input of <NUM> cps, and if the machine is set to multiply by <NUM> (one clock per degree of rotation), the output will be <NUM>. The clock source of a <NUM> clock signal <NUM> is almost 1000x faster, so is adequate.

As mentioned above, the first counter can be actually two counters <NUM> and <NUM> according to some embodiments. Counter <NUM> advances with each clock pulse, and is illustrated having R bits for a modulo <NUM>R count. The counter <NUM> could be any modulo, like <NUM> or <NUM>, and for discussion we say that counter <NUM> has modulo R. Counter <NUM> holds P bits and advances every time counter <NUM> rolls over. Taken together, these counters <NUM>, <NUM> count the number of clock pulses required for <NUM> revolution of the motor. With each revolution, the present value of counter <NUM> is captured in the latch <NUM>, and the entire first counter <NUM>, <NUM> is reset to zero. Mathematically, the latch <NUM> receives a value which is the total number of clock pulses per revolution divided by R, updated with every cycle of the unknown frequency. The size of the counter <NUM> (value of P) should be chosen to prevent counter overflow knowing M and the clock frequency. Simultaneously, the second counter <NUM> advances with each clock pulse, and counts until it reaches a value equal to the latched value. When equal, the equality logic <NUM> emits a single pulse and the second counter <NUM> resets to zero. As will be appreciated, the second counter <NUM> will do this a total of R times before the latched value changes, and so there will be R equality pulses emitted for each cycle of the unknown signal, for example the motor rotation signal. Thus, the goal of producing at the output <NUM> a clock train R times faster than the motor index pulse has been achieved, and the new clock train will change frequency as often as the motor speed changes, albeit one cycle later. The latency can be improved by configuring the motor to produce many pulses per revolution, and reducing R proportionately.

Also shown in <FIG> is a third counter <NUM>, a user-value register <NUM> for storing a value UV, and an SR latch <NUM>. This represents logic that is similar to a conventional timer with PWM arrangement, except with the added ability to reset the third counter <NUM> with every cycle of the unknown signal from source <NUM>. Since the third counter <NUM> is clocked R times per revolution, the counter value will advance from zero to (R-<NUM>) within each cycle of the unknown signal. In case the unknown signal is provided by a motor <NUM>, assuming that the motor speed is relatively constant, the counter will be equal to the user value at a rotation angle of <NUM>*(UV /R) degrees after the index pulse. It is highly significant that the user value UV is proportional to degrees, independent of the motor speed. This allows UV to represent an angle directly, without the sine, cosine or tangent computations normally required for conversion from the fixed-time measurements of traditional timers and PWMs to angular measurements (or vice versa). For AC power system, a value of UV=<NUM> (degrees) would produce the same angular index regardless of whether a <NUM>, <NUM> or even <NUM> power system is being used.

<FIG> shows an example with a motor <NUM> comprising, for example, a sensor <NUM>, for example a Hall sensor or optical sensor, capable of generating a pulse with each rotation of the motor shaft. This signal is used as the unknown frequency signal and fed to the period divider of <FIG> and the additional logic discussed in the embodiment of <FIG>. Here, the reset signal generated by comparator logic <NUM> is only used to clock counter <NUM>. Flip-flop <NUM> comprises output <NUM> which provides for a user controlled pulse width modulation signal which can be directly controlled by a value proportional to the rotation degree.

The arrangements shown in the figures can be preferably realized within a microcontroller. To this end, a flexible timer comparator unit may be provided that allows for the shown arrangements. To this end, latch <NUM> may be formed by a capture unit coupled with a first counter and programmable routing may be provided that allows comparing the various values as shown in <FIG>. For example, control registers within the microcontroller may allow to assign inputs of digital comparators to be assigned to timers or capture latches. Moreover, the microcontroller may include programmable logic, such as configurable logic cells that provide for combinatorial logic or various types of flip-flops or latches such as D flip-flop, JK flip-flop or SR latches. Such microcontrollers are manufactured by Applicant for example in the PIC10F32x and PIC1xF150X family.

<FIG> shows an exemplary microcontroller <NUM> designed to be able to be programmed to form the functional units as shown in <FIG>, <FIG>, and <FIG>. Microcontroller <NUM> comprises a central processing unit <NUM> connected with an internal bus <NUM>. Various peripherals such as timers <NUM>, a capture compare unit <NUM> and configurable logic cells <NUM> may be available and coupled with the internal bus <NUM>. In addition, each peripheral may have programmable glue logic that allows to route internal signals to its various inputs, for example, internal or external signals may clock a timer. Two timers may be programmable to form a single concatenated timer, timer values may be coupled with inputs of the capture/compare unit, etc. Alternatively a central programmable internal routing logic <NUM> may be provided that allows for the same function namely to assign the various internal or external signals to various inputs/outputs of the peripheral devices. The various peripherals may have special function registers that allow the selection of the various input/output signals. Even if a programmable internal routing logic <NUM> is provided, such special function registers may be provided to control the unit <NUM> wherein the special function registers may be associated with the respective peripheral unit. Thus, the unit <NUM> may not be visible to a user as a separate peripheral. Thus, without any additional hardware, a period divider and/or additional logic as discussed above can be formed within the microcontroller <NUM> under program control.

<FIG> shows an example of a modulo counter with a variable modulo. To this end, a modulo register <NUM> is provided which can be programmed to contain the modulo value. A modulo comparator <NUM> compares the value of LSB counter <NUM> with the value of the modulo register <NUM> and generates a pulse each time the values are equal. This pulse is used to reset LSB counter <NUM> and clock MSB counter <NUM>. The modulo register <NUM> can be, for example, programmed to store a value of <NUM> or <NUM> or any other suitable value for dividing the period of the unknown frequency.

<FIG> shows an angular timer <NUM> according to the invention for integration within a microcontroller. The primary output of the angular timer is the angle clock, at_angle_clock (<FIG>, <FIG>). In the basic operating mode, the angle clock has a frequency which is a multiple of signal_in. Other modes provide other features. The angle clock may be output on an I/<NUM> pin, or used as the timebase for other device timers.

The angle clock is used within this module <NUM> to generate the angle data value, at_angle[<NUM>:<NUM>], which can be read by software, used by capture and compare logic, or routed to other system CCP or PWM devices. An interrupt is signaled for each angle clock pulse. The module <NUM> also measures the period of the input signal. The measured period is compared to a setpoint value (ATxSTPT) to produce an error value (ATxERR).

The basic timer is shown in <FIG>, and period timer and angle counter details are elaborated in <FIG> and <FIG>, respectively. As will be apparent to a person skilled in the art, various elements of the period measurement and angle generator are also shown in <FIG>.

There are two types of input to module <NUM> as shown in <FIG>: the primary input ATSIG, and the capture logic input signals at_capture[x]. All signal and capture inputs are synchronized to the module clock using edge-detection logic similar to that shown in <FIG>. The missing pulse detector is illustrated in <FIG>. The logic compares the current period counter value with the latched value from the previous cycle (ATxPER), creating a signed difference. When the difference is equal to the ATxMISS register, a missing pulse is declared. The at_missed_pulse output is pulsed in all ATMD modes, with a corresponding interrupt.

When missing pulse detection is disabled in the ATMD mode register, every input pulse is considered the "end of period", and a period clock pulse is generated.

When missing pulse detection is enabled, the period clock is generated only after the missing pulse counter and ATxMISS register are equal, and the period latch update is not performed. All other input pulses latch period data.

It is allowed that a negative value can be set in ATxMISS register, the low byte must be written last; the upper byte is shadowed to guarantee atomic updates. Note, the missing pulse delay is measured in time (clock cycles) and not in degrees, because the period counter is used as the reference. Generally speaking, the missing pulse detector only fires once, and then requires a legitimate input edge to reset itself. This is an automatic behavior, because the period counter will max-out at FFFF and not again be equal to ATxMISS.

As shown in <FIG>, the user may enter a setpoint value in register ATxSTPT. The setpoint is subtracted from the measured period register ATxPER to produce register ATxERR.

An embodiment of an interrupt logic for generating an interrupt is shown in <FIG>. An embodiment of the compare and capture logic is illustrated in <FIG>, these features provide:.

According to an embodiment, when writing register ATxCCy, the low byte must be written last; the upper byte is shadowed to guarantee atomic updates.

The following section describes the operation in the single-pulse per revolution mode.

The basic operation is illustrated in <FIG>. As shown in <FIG>, the angular timer includes two divider chains, and both measure the period of the input signal.

The first chain (<FIG>) divides clock_in by the user-specified ATxRES value stored in the respective register. The resulting clock (clock_in/ATRES) is used to clock a counter. At the end of the input period (that is, the next active edge of signal_in), the value given by Equation <NUM> is latched into register ATxPER , and an interrupt is signaled (except when inhibited).

At the same time, the second chain (<FIG>) divides clock_in by register ATxPER, which holds the value measured in the previous cycle. The resulting clock (clock_in/ATPER) clocks the counter which may be read as ATxANG. By the same reasoning used for ATxPER, the angle counter (if theoretically sampled at the end of the period) will be as shown in Equation <NUM>.

Comparing Equation <NUM> and Equation <NUM> will show that ATxANG should count from zero to a value equal to ATxRES during the ATSIG period. Therefore, the clock to the ATANG counter can be seen to have a frequency of F(signal) ·A TRES, which is the required angle clock.

Note that, if the input period changes, the angle clock period will not change until the next cycle. It follows that, at the end of a cycle, the value in ATxANG may be more or less than ATxRES. Realize also that the ATxANG counter is not required for the generation of at_angle_clock. The counter is a module feature that allows for the capture and compare logic, and for the user to monitor instantaneous input angle.

When ATSIG represents the rotation of a machine or the AC mains, the input is understood to provide <NUM> active edge every <NUM> degrees. Since the angle clock equally divides the signal period, the clock also divides the <NUM> degree period of rotation, and each clock pulse marks a fixed angle of that rotation, AR (Equation <NUM>).

ATxANG is cleared to zero at the start of the rotation (that is, at the at_period_clk pulse), and then counts up throughout the cycle, so the value of the counter is linearly related to the instantaneous phase angle as shown in Equation <NUM>.

A timing example is shown in <FIG>, with ATxRES = <NUM>, making an angle clock pulse every <NUM>/<NUM> = <NUM> degrees.

The value of ATRES determines the resolution of the period measurement and strongly affects the timing of the angle clock at the end of each revolution. When ATRES is small, ATxPER will count to a high value. ATxPER truncates the actual period value, so the inherent accuracy is +<NUM>/-<NUM> counts, multiplied by ATRES (because period is measured in increments of ATRES). Counting to a high ATxPER means the error is a smaller percentage of the total. When ATRES is large (say, <NUM>), the value in ATxPER will be small, and the truncation will be a significant error source. The truncation error accumulates in the angle pulse position, with each arriving more early than its predecessors. If ATRES is large, the last period clock could be early by many clocks. The practical issue here is that reading ATxANG and applying Equation <NUM>-<NUM> can often produce a value that is > <NUM>°.

A small ATxRES is advantageous for accuracy, but may not meet system requirements. The figure-of-merit of the system is defined as the minimum expected ATxPER value, and Equation <NUM> may be rewritten as Equation <NUM>. It is recommended that for good operation, select clock_in and ATxRES to give FOM > <NUM>.

As Equation <NUM> shows, a high-frequency clock_in will produce higher counts, and lower percentage error, at the expense of higher system power. If ATxPER overflows, the ATPOV bit will be set in a control register, and the value of ATxPER will not be updated (it follows that ATVALID may remain unset until the 3rd signal cycle).

When the signal at ATSIG is lost, the period counter will overflow and ATPOV becomes <NUM>. However, there is no period interrupt, and the value in ATxPER is not updated, so the angle clock frequency will not change. Eventually even ATxANG will overflow, and ATVALID will become <NUM>. Note, the missing pulse detector should be used to detect loss of input and create an interrupt. The time-out value will be (a) guaranteed, and (b) much shorter than can be achieved by waiting for ATxANG overflow.

The angle clock output is not accurate until the input period has been correctly sampled, which requires at least two complete input cycles (see the example in.

Accordingly, the angle clock is gated off while ATVALID = O, the angle counter will not advance, and no angle interrupt will occur. ATVALID is held at O whenever ATEN= O or ATxRES = O, or becomes O because of:
any reset (including cfg_at_en = <NUM>),
any write to ATxRES (Register <NUM>-<NUM> ),
angle counter overflow, or
freeze (freeze= <NUM>).

ATVALID becomes <NUM> upon the third (<NUM>rd) active input edge of the signal that latches ATxPER. While ATVALID=<NUM>, the following features are inhibited:.

Also, while ATVALID = O, every input edge captures the period duration, ignoring the missing pulse detector, so that a baseline measurement can be established. In other words, when the system is just starting up, every input cycle is captured into ATxPER no matter which ATMD is selected.

The operating modes are summarized in <FIG>.

The motor sensor or zero-cross detector provides exactly one pulse for each revolution as shown in <FIG>. Every ATSIG resets the Period and Angle counters, and the period is measured with each input cycle.

ATRES is set to produce the required angular resolution. This is the basic timing mode described above. The at_missed_pulse output and associated interrupt are active, but have no effect on operation or the other module outputs.

The motor sensor provides more than one pulse for each revolution. For the case shown in <FIG>, the motor sensor pulses twice for each revolution, at a known angular difference. The first pulse is assumed as the "top dead center" (TDC) reference, and the <NUM>nd pulse is used to measure the (partial) period.

The signal pattern of <FIG> is typically taken from the flywheel of an internal combustion engine. It is not uncommon to have more than <NUM> teeth on flywheel, and a pulse appears for all-but-<NUM> tooth gap at the final tooth. The period counter measures the tooth-to-tooth duration except at the gap. The first pulse after the gap signals TDC.

While ATVALID = <NUM>, all input edges update ATxPER, and the missing pulse detector is ignored in order to establish a baseline period measurement:
Because so many pulses are occurring on ATSIG, the value of ATRES must be set fairly low to achieve a suitable FOM. A reasonable value may be less than <NUM>. Equation <NUM> is restated as Equation <NUM> to include the effect of the teeth. ATRES must also be small because ATxANG will count up to the value of ATRES · TEETH, which must remain below <NUM> (<NUM> bits), even when the motor speed is slowing.

This mode is identical to ATMD = <NUM>, except that the value in ATxMISS is not used. The missing pulse timeout is one half of the current measured period, as shown in the timing diagram of <FIG>, and will track changing motor speed. I Note: The value in ATxMISS is not changed.

This mode is identical to ATMD = <NUM>, except that the value in ATxMISS is not used. The missing pulse timeout is one half of the current measured period, as shown in the timing diagram <FIG>, and will track changing motor speed. Note: The value in ATxMISS is not changed.

The primary output of the module is the angle clock, at_angle_clock. Most applications will also require the period clock as a "zero" or "top dead center" reference.

To simplify device logic, the module includes the angle counter, which uses both signals. This counter is illustrated in <FIG> and described above.

The compare registers of <FIG> generate an output signal at specified values of ATxANG. Given a required phase angle, use Equation <NUM> or Equation <NUM> and solve for the value of ATxANG that represents that angle. Three applications of the compare outputs are illustrated.

When ATxRES = <NUM>, the capture/compare feature can be interpreted as percentage of a cycle. If the period-input signal is applied to a capture input, and the capture polarity is falling edge (<FIG>), the captured value will indicate the duty-cycle of the input signal. The missing pulse detector can indicate if the input has been lost. This application will work regardless of the input frequency, so long as it is relatively constant and not DC. It is also immune to oscillator calibration errors.

Claim 1:
An angular timer peripheral comprising two divider chains configured to both measure the period of a rotational input signal (signal_in) of unknown frequency, wherein the rotational input signal (signal_in) comprises a series of index pulses per rotation wherein at least one pulse is missing to indicate a position;
wherein the first divider chain comprises:
an interval measurement unit (<NUM>) configured to determine an interval time of an interval defined by succeeding pulses of the input signal (singal_in) by a counter (<NUM>, <NUM>) receiving a system clock (clk_in) and comprising a latch (ATxPER) configured to store said measured interval time value; and
a missing pulse detector operable to create a signed difference by comparing the measured interval time value latched from the previous cycle and stored in said latch (ATxPER) with the current interval counter value and to compare the signed difference with a parameter stored in a register (ATxMISS) to determine whether a pulse is missing in the input signal (signal_in), wherein the parameter stored in said register (ATxMISS) is defined by the previously measured period value and a predetermined factor by which the previously measured interval must be exceeded, wherein the missing pulse detector comprises logic for outputting a signal (at_missed_pulse) indicating a missing pulse;
and wherein the second divider chain comprises:
an angle generator unit configured to deliver at its output a signal (at angle clock) having a frequency which is a multiple of the frequency of the rotational input signal (signal in), whereby the angle generator unit comprises a counter receiving a clock signal defined by the system clock (elk in) divided by the value held in said latch (ATxPER) from the previous cycle of the input signal.