Patent Description:
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system.

<CIT> discloses that a high-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described.

<CIT> discloses that a row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

Memory systems are prevalent in modern electronic devices. It is important that memory systems operate in an accurate and reliable manner when data is stored or retrieved.

<FIG> depicts exemplary prior art memory system <NUM>. Array <NUM> comprises a plurality of memory cells arranged in rows and columns. Each row is coupled to one of a plurality of word lines <NUM>, and each column is coupled to one of a plurality of bit lines <NUM>. Array <NUM> is accessed by row decoder <NUM>, which selects a word line and thereby selects a row, and column decoder <NUM>, which selects a bit line and thereby selects a column. The memory cells can be volatile memory cells (such as DRAM or SRAM cells) or non-volatile memory cells (such as flash memory cells).

In this example, row decoder <NUM> and column decoder <NUM> each receive Address A, which is the address in array <NUM> that is selected for a read or write (program) operation. Address A comprises row address component <NUM> and column address component <NUM>. For example, if Address A comprises <NUM> bits [b0:b7], row address component <NUM> might comprise the first four bits [b0:b3] and column address component <NUM> might comprises the last four bits [b4:b7], or vice-versa. In the alternative, row address component <NUM> and column address component <NUM> might be derived from Address A using a decoding algorithm.

Row decoder <NUM> receives and decodes row address component <NUM>, which results in one of a plurality of word lines <NUM> being asserted by row decoder <NUM>. If row address component <NUM> is m bits, then there will be <NUM>m word lines <NUM>.

Column decoder <NUM> receives and decodes column address component <NUM>. During a read operation, column decoder <NUM> also receives signals from all bit lines <NUM> in array <NUM>. Column decoder <NUM> decodes bit lines <NUM> using the column address component <NUM> to select a particular column, and the value sensed from that column is provided as Output. During a write (program) operation, column decoder <NUM> receives Input and applies it to a bit line selected by the decoding action in response to the column address component. If column address component <NUM> is n bits, then there will be <NUM>n bit lines <NUM>. In some examples column decoding is accomplished by multiplexing.

In this manner, row address component <NUM> and column address component <NUM> select a particular memory cell for a read or write (program) operation.

Due to imperfections in material or random environmental disturbances, an address fault might occur during a read or write (program) operation. Specifically, the types of address faults that might occur include:.

For example, if address A corresponds to word line <NUM>, an address fault might cause word line <NUM> to be selected instead (due to a bit flip of the second bit). Similarly, if address A corresponds to bit line <NUM>, an address fault might cause two bit lines, such as bit lines <NUM> and <NUM> to be selected instead. A person of ordinary skill in the art will appreciate that if an address fault is not detected or corrected, an erroneous read or write/program operation will occur.

<FIG> depicts a prior art solution to the address fault problem. Memory system <NUM> comprises the same components as memory system <NUM> in <FIG>, as well as ROM row encoder <NUM>, ROM column encoder <NUM>, and comparator <NUM>. ROM row encoder <NUM> comprises one row of ROM cells for each row in array <NUM>, and ROM column encoder <NUM> comprises one row of ROM cells for each column in array <NUM>. The purpose of ROM row encoder <NUM> and ROM column encoder <NUM> is to provide additional data that can be used to identify address faults.

ROM row encoder <NUM> receives all of word lines <NUM> in <FIG>, i.e., the decoded row address component <NUM>, each word line corresponding to a row in ROM row encoder <NUM>, and when a particular row is selected in array <NUM>, a corresponding row is selected in ROM row encoder <NUM>, and data <NUM> is output to comparator <NUM>.

ROM column encoder <NUM> receives decoded column signals from column decoder <NUM> that can identify a selected column, and when a particular column is selected in array <NUM>, a corresponding row is selected in ROM column encoder <NUM>, and data <NUM> is output to comparator <NUM>.

In this design, ROM row encoder <NUM> has been programmed to output a value that includes the row address component associated with the selected row, and ROM column encoder <NUM> has been programmed to output a value that includes the column address component associated with the selected column. For example, in a situation where no address fault has occurred, if row address component <NUM> is "<NUM>", then ROM row encoder <NUM> will have a corresponding output that includes the bits "<NUM>" in output <NUM>, and if column address component <NUM> is "<NUM>," then ROM column encoder <NUM> will have a corresponding output that includes the bits "<NUM>" in output <NUM>.

One drawback of the prior art design is that ROM row encoder <NUM> and ROM column encoder <NUM> require significant die space. <FIG> depicts prior art ROM encoder <NUM>, which can be used for ROM encoder row <NUM> or ROM column encoder <NUM>. For simplicity, in this example, ROM encoder <NUM> contains four rows corresponding to word lines [WL0:WL3] in array <NUM>, which in turn correspond to address bits [A1:A0]. A person of ordinary skill in the art that ROM encoder <NUM> can comprise a much larger number of rows and columns.

By design, instead of encoding address bits [A1:A0] in only two bit lines, ROM encoder <NUM> also includes complementary bits for those address bits. In this example, the bits [B1:B0] contain the bits corresponding to address bits [A1:A0] and therefore can be compared directly against address bits [A1:A0] by comparator <NUM>. Bit B3 is the complement of bit B1, and bit B2 is the complement of bit B0. Storing complementary bits in addition to the address bits themselves enables the system to robustly identify any address fault that occurs. In the particular configuration shown in <FIG>, the corresponding asserted word line and output for each address bit [A1, A0] combination will be:.

With reference again to <FIG>, applying the example of Table <NUM>, comparator <NUM> compares bits B1 and B0 from output <NUM> with row address component <NUM>, specifically bits A1 and A0. Comparator <NUM> also compares bits B3 and B2 from output <NUM> with the inverse of bits B1 and B0. Similar comparisons are done with the output <NUM> of ROM column encoder <NUM> and column address component <NUM>. If all four comparisons match, then there has been no address fault, and flag <NUM> has a value indicating no address fault (e.g., "<NUM>"). If one or more of the four comparisons do not match, then there has been an address fault, and flag <NUM> has a value indicating an address fault (e.g., "<NUM>").

Table <NUM> contains examples of the detection of address fault using the output of ROM encoder <NUM> based on the input of address bits [<NUM>, <NUM>].

As can be seen, <NUM> switches are required in this design to encode data for two address bits [Al, AO]. More generally, the number of switches required in ROM encoder <NUM> is equal to: (number of possible word lines) x (number of bits in address), which in this example is <NUM> x <NUM> = <NUM>. Here, each switch is implemented with an NMOS or PMOS transistor. These switches utilize a significant amount of die space.

What is needed is an improved address fault detection system that can detect address faults while utilizing fewer components and less die space than prior art designs.

The present invention is defined in the independent claims <NUM> and <NUM>. Preferred embodiments are defined in dependent claims <NUM>-<NUM>.

Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault.

In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address.

Only embodiments including all the features of independent claim <NUM> or of independent claim <NUM> fall under the scope of protection of the present invention.

<FIG> depicts hierarchical ROM encoder system <NUM>. ROM encoder system <NUM> comprises a two-level hierarchy of ROM encoders, specifically, ROM encoder <NUM> and ROM encoder <NUM>. ROM encoder system <NUM> further comprises logic block <NUM> comprising a set of OR gates. In this example, ROM encoder system <NUM> contains <NUM> word lines corresponding to a <NUM>-bit row or column address [A3:A0]. A person of ordinary skill in the art will appreciate that ROM encoder system <NUM> can be constructed with a greater number of word lines corresponding to a greater number of bits in a row or column address, or lesser number of word lines corresponding to a lesser number of bits in a row or column address.

Each row in ROM encoder <NUM> corresponds to one of the word lines <NUM> in array <NUM> in <FIG>, here shown as word lines [WL0:WL15]. Logic block <NUM> receives word lines <NUM> as well. Logic block <NUM> comprises individual OR gates, such as OR gate <NUM>-<NUM> and OR gate <NUM>-<NUM>. In this example, each OR gate receives four word lines and performs an "OR" function on those four word lines. Instead of <NUM>-input OR gates, logic block <NUM> instead could utilize OR gates of other numbers of inputs. The output of each OR gate (a logic block output) is coupled to a respective row in ROM encoder <NUM>. Thus, whereas the inputs to ROM encoder <NUM> are <NUM> word lines [WL0:WL15], the inputs to ROM encoder <NUM> are <NUM> lines containing the result of the OR operations (WL0 or WL1 or WL2 or WL3), (WL4, WL5, WL6, or WL7), (WL8, WL9, WL10, or WL11), and (WL12, WL13, WL14, and WL15).

In this example, ROM Encoder <NUM> receives all <NUM> wordlines (WL0 to WL15) and stores the same bit pattern every <NUM> rows, which correspond to the least <NUM> significant bits, [A1:A0] in the address, using the same bit pattern shown in <FIG>. For instance, the bit pattern stored in WL0 to WL3 are identical to the bit pattern stored in WL4 to WL7. This is because each <NUM>-row grouping stores values associated with the <NUM> least significant bits of the address.

ROM encoder <NUM> stores the encoding for the <NUM> most significant bits, [A3:A2]. Those <NUM> bits essentially indicate which of the <NUM>-word line groupings has been selected. output of the respective OR gates <NUM>-<NUM>, <NUM>-<NUM>, without limitation, of logic block <NUM>, are a decoding for the <NUM> most significant bits (A[<NUM>:<NUM>] in this example). That is, the four signals received by ROM encoder <NUM> represents the four possible combinations for A[<NUM>:<NUM>]. For example, if A3=<NUM> and A2=<NUM>, then one of word lines WL0, WL1, WL2, and WL3 will be selected, and the output of OR gate <NUM>-<NUM> will be "<NUM>", which will assert the row in ROM encoder <NUM> attached to the output of OR gate <NUM>-<NUM>, and so forth.

Hierarchical ROM encoder system <NUM> also comprises logic (not shown, but shown in subsequent figures) that is used to compare the outputs of ROM encoder <NUM> and ROM encoder <NUM> with the address, A, where the output of ROM encoder <NUM> contains the two least significant bits of the address and their complements, and the output of ROM encoder <NUM> reflects the two most significant bits of the address and their complements. The logic also compares the stored complements with the inverse of the stored address portions.

<FIG> and <FIG> depict the use of hierarchical ROM encoder system <NUM> in a larger memory system.

In <FIG>, memory system <NUM> comprises array <NUM>, row decoder <NUM>, and hierarchical ROM encoder system <NUM>, which here is shown as further comprising comparator <NUM>, comparator <NUM>, OR gate <NUM>, and flag <NUM> (which is a row address fault detection signal).

During operation, ROM encoder <NUM> outputs a first output in response to its asserted row or rows, and ROM encoder <NUM> outputs a second output in response to its asserted row or rows in response to the signals receives from logic block <NUM>. Comparator <NUM> compares the first output against a first portion of row address component <NUM>, and comparator <NUM> compares the second output against a second portion of row address component <NUM>. In one example, comparator <NUM> also compares the complement portion of the first output against the inverse of the address portion of the first output, and comparator <NUM> also compares the complement portion of the second output against the inverse of the address portion of the second output. The results of comparator <NUM> and <NUM> undergo an OR function by OR gate <NUM> to generate flag <NUM>. A first value of flag <NUM> (e.g., "<NUM>") indicates a row address fault, and a second value (e.g., "<NUM>") indicates no row address fault.

<FIG> depicts the same mechanism described in <FIG> but for the column decoder <NUM> instead of row decoder <NUM>. Memory system <NUM> comprises array <NUM> and further comprises column decoder <NUM> and hierarchical ROM encoder system <NUM>', which here is shown as further comprising comparator <NUM>', comparator <NUM>', OR gate <NUM>', and flag <NUM>' (which is a column address fault detection signal).

During operation, ROM encoder <NUM>' outputs a first output in response to its asserted row or rows, and ROM encoder <NUM>' outputs a second output in response to its asserted row or rows in response to the signals receives from logic block <NUM>'. Comparator <NUM>' compares the first output against a first portion of column address component <NUM>, and comparator <NUM>' compares the second output against a second portion of column address component <NUM>'. In one example comparator <NUM>' also compares the complement portion of the first output against the inverse of the address portion of the first output, and comparator <NUM>' also compares the complement portion of the second output against the inverse of the address portion of the second output. The results of comparator <NUM>' and <NUM>' undergo an OR function by OR gate <NUM>' to generate flag <NUM>'. A first value of flag <NUM>' (e.g., "<NUM>") indicates a column address fault, and a second value (e.g., "<NUM>") indicates no column address fault.

In the example of <FIG> or <FIG>, ROM encoders <NUM> and <NUM>' each requires <NUM> switches, ROM encoders <NUM> and <NUM>' each requires <NUM> switches, and logic blocks <NUM> and <NUM>' each requires <NUM> switches to create the four OR gates, for a total of <NUM> switches in each of <FIG> and <FIG>. The same implementation using a single ROM encoder requires <NUM> switches for detecting row address faults and <NUM> switches for detecting column address faults, so for an example of <NUM> rows, there is not yet any savings in die space. However, for <NUM> rows, hierarchical ROM encoder systems <NUM> and <NUM>' each requires <NUM> switches compared to <NUM> switches for each of two ROM encoders <NUM>, which is a savings in die space. The savings increases as the number of rows increases thereafter, as shown below in Table <NUM>.

An example of how the output of ROM encoders <NUM> and <NUM> detects an address fault is illustrated in Table <NUM>:.

<FIG> and <FIG> depict memory system <NUM>.

In <FIG>, memory system <NUM> comprises array <NUM>, hierarchical ROM encoder system <NUM>, and row decoder <NUM>. Hierarchical ROM Encoder System <NUM> comprises a three-level hierarchy of ROM encoders, specifically, ROM encoder <NUM>, ROM encoder <NUM>, and ROM encoder <NUM>. Hierarchical ROM encoder system <NUM> further comprises logic block <NUM> (comprising OR gates), logic block <NUM> (comprising OR gates), comparator <NUM>, comparator <NUM>, comparator <NUM>, OR gate <NUM>, and flag <NUM>.

In <FIG>, memory system <NUM> comprises array <NUM> and further comprises hierarchical ROM encoder system <NUM>', and column decoder <NUM>. Hierarchical ROM Encoder System <NUM>' comprises a three-level hierarchy of ROM encoders, specifically, ROM encoder <NUM>', ROM encoder <NUM>', and ROM encoder <NUM>'. Hierarchical ROM encoder system <NUM>' further comprises logic block <NUM>' (comprising OR gates), logic block <NUM>' (comprising OR gates), comparator <NUM>', comparator <NUM>', comparator <NUM>', OR gate <NUM>', and flag <NUM>'.

Hierarchical ROM encoder systems <NUM> and <NUM>' operate in the same way as hierarchical ROM encoder systems <NUM> and <NUM>', respectively, except that a third level is added. Logic blocks <NUM> and <NUM>' receive a multi-bit output from ROM encoder <NUM> and <NUM>', respectively, and perform an OR operation on sets of four bits to generate a logic block output, which then serves as the input to ROM encoder <NUM> and <NUM>', respectively, which generates a third output in response to its input. Thus, ROM encoders <NUM> and <NUM>' contain one-fourth the number of inputs and rows as ROM encoders <NUM> and <NUM>', respectively, and ROM encoders <NUM> and <NUM>' contain one-fourth the number of inputs and rows as ROM encoders <NUM> and <NUM>', respectively.

During operation, ROM encoders <NUM> and <NUM>', respectively, output a first output in response to its asserted row or rows, ROM encoders <NUM> and <NUM>', respectively, output a second output in response to its asserted row or rows, and ROM encoders <NUM> and <NUM>' output a third output in response to its asserted row or rows. Comparators <NUM> and <NUM>' compare the first output against a first portion of row address component <NUM> and column address component <NUM>, respectively, comparators <NUM> and <NUM>' compare the second output against a second portion of row address component <NUM> and column address component <NUM>, respectively, and comparators <NUM> and <NUM>' compare the third output against a third portion of row address component <NUM> and column address component <NUM>, respectively. The results of comparators <NUM>, <NUM>, and <NUM> undergo an OR function by OR gate <NUM> to generate flag <NUM>, which is a row address fault detection signal, and the results of comparators <NUM>', <NUM>', and <NUM>' undergo an OR function by OR gate <NUM>' to generate flag <NUM>', which is a column address fault detection signal. A first value of flag <NUM>' (e.g., "l") indicates an address fault, and a second value (e.g., "<NUM>") indicates no address fault.

<FIG> and <FIG>, not forming part of the invention, depict memory system <NUM>. In <FIG>, memory system <NUM> comprises array <NUM>, hierarchical ROM encoder system <NUM>, and row decoder <NUM>. In <FIG>, memory system <NUM> comprises array <NUM> and further comprises hierarchical ROM encoder system <NUM>' and column decoder <NUM>. Hierarchical ROM encoder system <NUM> comprises a two- level hierarchy of ROM encoders, specifically, ROM encoder <NUM> and ROM encoder <NUM>, and hierarchical encoder system <NUM>' comprises a two-level hierarchy of ROM encoders, specifically, ROM encoder <NUM>' and ROM encoder <NUM>'. Hierarchical ROM encoder system <NUM> further comprises comparator <NUM>, comparator <NUM>, OR gate <NUM>, and flag <NUM>, and hierarchical ROM encoder system <NUM>' further comprises comparator <NUM>', comparator <NUM>', OR gate <NUM>', and flag <NUM>'. Notably, unlike hierarchical ROM encoder system <NUM> and <NUM>', a separate logic block is not required between the two ROM encoders. This is because ROM encoder <NUM> instead receives its inputs from row decoder <NUM> and ROM encoder <NUM>' receives its inputs from column decoder <NUM><NUM>, which performs a separate encoding function to replace the OR gates of logic block <NUM> in memory system <NUM> or logic blocks <NUM> and/or <NUM> in memory system <NUM>.

With reference to <FIG>, not forming part of the invention, during operation, ROM encoder <NUM> outputs a first output in response to its asserted row or rows, and ROM encoder <NUM> outputs a second output in response to its asserted row or rows. Comparator <NUM> compares the first output against a first portion of row address component <NUM> (or column address component <NUM>), and comparator <NUM> compares the second output against a second portion of row address component <NUM> (or column address component <NUM>). The results of comparator <NUM> and <NUM> undergo an OR function by OR gate <NUM> to generate flag <NUM>. A first value of flag <NUM> (e.g., "l") indicates a row address fault, and a second value (e.g., "<NUM>") indicates no row address fault.

Similarly, with reference to <FIG>, not forming part of the invention, ROM encoder <NUM>' outputs a first output in response to its asserted row or rows, and ROM encoder <NUM>' outputs a second output in response to its asserted row or rows. Comparator <NUM>' compares the first output against a first portion of column address component <NUM>, and comparator <NUM>' compares the second output against a second portion of column address component <NUM>. The results of comparator <NUM>' and <NUM>' undergo an OR function by OR gate <NUM>' to generate flag <NUM>'. A first value of flag <NUM>' (e.g., "l") indicates a column address fault, and a second value (e.g., "<NUM>") indicates no column address fault.

The total amount of switches/transistors needed for each design is summarized in Table <NUM>:.

In <FIG>, memory system <NUM> comprises array <NUM>, row decoder <NUM>, and hierarchical ROM encoder system <NUM>. In <FIG>, memory system <NUM> comprises array <NUM> and further comprises column decoder <NUM> and hierarchical ROM encoder system <NUM>'.

Hierarchical ROM encoder system <NUM> comprises ROM encoder <NUM>, logic block <NUM> (comprising NOR gates), ROM encoder <NUM>, logic block <NUM> (comprising NAND gates), ROM encoder <NUM>, comparator <NUM>, comparator <NUM>, comparator <NUM>, OR gate <NUM>, and flag <NUM> (a row address fault detection signal). Similarly, hierarchical ROM encoder system <NUM>' comprises ROM encoder <NUM>', logic block <NUM>' (comprising NOR gates), ROM encoder <NUM>', logic block <NUM>' (comprising NAND gates), ROM encoder <NUM>', comparator <NUM>', comparator <NUM>', comparator <NUM>', OR gate <NUM>', and flag <NUM>' (a column address fault detection signal).

Hierarchical ROM encoder systems <NUM> and <NUM>' are similar to hierarchical ROM encoder systems <NUM> and <NUM>' in <FIG> and <FIG>, respectively, except that logic block <NUM> and logic block <NUM>' comprise NOR gates, and logic blocks <NUM> and <NUM>' comprise NAND gates, which can reduce number of switches required compared to using logic blocks <NUM> and <NUM>' comprising OR gates and logic blocks <NUM> and <NUM>' comprising OR gates, since NOR gates and NAND gates require fewer switches than OR gates. In <FIG> and <FIG>, due to the change in logic blocks, the switches in ROM encoders <NUM> and <NUM> and <NUM>' and <NUM>' are formed of NMOS transistors, and the switches in ROM encoders <NUM> and <NUM>' are formed of PMOS transistors so that the correct logic is performed in selecting the correct row in each encoder.

With reference to <FIG>, during operation, ROM encoder <NUM> outputs a first output in response to its asserted row or rows, ROM encoder <NUM> outputs a second output in response to its asserted row or rows, and ROM encoder <NUM> outputs a third output in response to its asserted row or rows. Comparator <NUM> compares the first output against a first portion of row address component <NUM>, comparator <NUM> compares the second output against a second portion of row address component <NUM>, and comparator <NUM> compares the third output against a third portion of row address component <NUM>. The results of comparators <NUM>, <NUM>, and <NUM> undergo an OR function by OR gate <NUM> to generate flag <NUM>, which is a row address fault detection signal. A first value of flag <NUM> (e.g., "<NUM>") indicates a row address fault, and a second value (e.g., "<NUM>") indicates no row address fault.

Similarly, with reference to <FIG>, during operation, ROM encoder <NUM>' outputs a first output in response to its asserted row or rows, ROM encoder <NUM>' outputs a second output in response to its asserted row or rows, and ROM encoder <NUM>' outputs a third output in response to its asserted row or rows. Comparator <NUM>' compares the first output against a first portion of column address component <NUM>, comparator <NUM>' compares the second output against a second portion of column address component <NUM>, and comparator <NUM>' compares the third output against a third portion of row address component <NUM> (or column address component <NUM>). The results of comparators <NUM>', <NUM>', and <NUM>' undergo an OR function by OR gate <NUM>' to generate flag <NUM>', which is a column address fault detection signal. A first value of flag <NUM>' (e.g., "<NUM>") indicates a column address fault, and a second value (e.g., "<NUM>") indicates no column address fault.

A person of ordinary skill in the art will appreciate that a hierarchical ROM encoder system can be built with more than <NUM> levels (e.g., n levels) using the concepts described herein.

Claim 1:
A memory system (<NUM>, <NUM>), comprising:
an array (<NUM>) of memory cells arranged in rows and columns;
a row decoder (<NUM>) for receiving a row address component and asserting one of a plurality of word lines comprising <NUM> or more word lines, each word line coupled to a row in the array; and
a hierarchical ROM encoder system (<NUM>, <NUM>), comprising:
a first ROM encoder (<NUM>, <NUM>) for receiving the plurality of word lines and generating a first output;
a first logic block (<NUM>, <NUM>) for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output;
a second ROM encoder (<NUM>, <NUM>) for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs;
a first comparator (<NUM>, <NUM>) for comparing the first output and a first part of the row address component;
a second comparator (<NUM>, <NUM>) for comparing the second output and a second part of the row address component; and
a gate (<NUM>, <NUM>) for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator.