Patent Description:
Magnetoresistive random access memory (MRAM) is a type of memory device containing an array of MRAM cells that store data using their resistance values instead of electronic charges. Generally, each MRAM cell includes a magnetic tunnel junction (MTJ) structure. The MTJ structure may have adjustable resistance to represent a logic state "<NUM>" or "<NUM>. " The MTJ structure typically includes a stack of magnetic layers having a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric, e.g., an insulating tunneling layer. A top electrode and a bottom electrode are utilized to sandwich the MTJ structure so electric current may flow between the top and the bottom electrode.

One ferromagnetic layer, e.g., a reference layer, is characterized by a magnetization with a fixed direction. The other ferromagnetic layer, e.g., a storage layer, is characterized by a magnetization with a direction that is varied upon writing of the device, such as by applying a magnetic field. In some devices, an insulator material, such as a dielectric oxide layer, may be formed as a thin tunneling barrier layer sandwiched between the ferromagnetic layers. The layers are typically deposited sequentially as overlying blanketed films. The ferromagnetic layers and the insulator material are subsequently patterned by various etching processes in which one or more layers are removed, either partially or totally, in order to form a device feature.

When the respective magnetizations of the reference layer and the storage layer are antiparallel, a resistance of the magnetic tunnel junction is high having a resistance value Rmax corresponding to a high logic state "<NUM>". On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction is low, namely having a resistance value Rmin corresponding to a low logic state "<NUM>". A logic state of a MRAM cell is read by comparing its resistance value to a reference resistance value Rref, which is derived from a reference cell or a group of reference cells and represents an in-between resistance value between that of the high logic state "<NUM>" and the low logic state "<NUM>". <CIT> relates to a bottom pinned SOT-MRAM bit structure. An underlayer is formed on a substrate including a metal pad. Further, a first ferromagnetic layer, a barrier layer, a second ferromagnetic layer, and SOT layers are formed. <CIT> relates to shared source line architectures of perpendicular hybrid spin-torque transfer (STT) and spin-orbit torque (SOT) magnetic random access memory. <CIT> relates to a magnetic random access memory device having a magnetic tunnel junction.

Spin-transfer-torque magnetic random access memory (STT MRAM) and spin-orbit-torque magnetic random access memory (SOT MRAM) are different chip architectures that each has its own electrical performance and energy efficiency. A demand for hybrid and integrated spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) has recently increased due to its combined benefits. However, how to fabricate SOT-STT MRAMs with desired production yield and well integrated film scheme for the magnetic tunnel junction (MTJ) structure remain a challenge.

Therefore, there is a need in the art for improved methods and apparatus for fabricating MTJ structures for MRAM applications.

The present disclosure describes methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures along with a back end interconnection structure on a substrate for MRAM applications, particularly for hydride spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one aspect, an interconnection structure according to independent claim <NUM> is provided. An interconnection structure includes at least three magnetic tunnel junction structures disposed on a substrate. A first magnetic tunnel junction structure of the at least three magnetic tunnel junction structures comprises a patterned film stack comprising a first ferromagnetic layer, a tunneling barrier layer and a second ferromagnetic layer disposed on and contacting a top surface of a first lower interconnection structure, wherein the first ferromagnetic layer and the second ferromagnetic layer sandwich the tunneling barrier layer. The first magnetic tunnel junction structure further comprises a hardmask layer disposed on the first ferromagnetic layer, the hardmask layer forming a barrier to etching of the patterned film stack. The interconnection structure comprises a spin orbit torque (SOT) layer having a bottommost surface disposed on and contacting a top surface (<NUM>) of the hardmask layer, wherein the SOT layer is electrically conductive, and multiple back end structure disposed on the spin orbit torque (SOT) layer.

In another aspect, a method of forming an interconnection structure according to the independent method claim <NUM> is provided. A method includes forming a film stack having a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer on a substrate, forming a patterned hardmask layer on the film stack, patterning the film stack using the patterning hardmask layer as an etching mask layer, forming a first insulation material to cover the patterned hardmask layer and the film stack on the substrate, polishing the first insulation material until a top surface of the hardmask layer is exposed, forming a spin orbit torque (SOT) layer on the top surface of the hardmask layer, and forming a back end interconnection structure on the spin orbit torque (SOT) layer.

In another embodiment, an interconnection structure for a memory device includes multiple magnetic tunnel junction structures connected to a SOT layer, wherein the magnetic tunnel junction structures have a capping layer connecting the SOT layer fabricated from a material the same from the SOT layer, and a dual damascene back end structure connected to the SOT layer.

Embodiments of the disclosure generally provide apparatus and methods for forming a MTJ structure and a back end interconnection structure electrically connected to the MTJ structure disposed on a substrate for MRAM applications. The embodiments of the disclosure may be used in spin-transfer-torque magnetic random access memory (STT MRAM), spin-orbit-torque magnetic random access memory (SOT MRAM), and/or the hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. While patterning the film stack for forming the MTJ structure, a hardmask is utilized. Such hardmask layer may be the same material of a spin orbit torque (SOT) layer disposed on the MTJ structure. In some examples, the hardmask layer may also be served as the spin orbit torque (SOT) layer when the MTJ structure is patterned and formed. After the MTJ structure and the SOT layer is formed thereon, a back end (e.g., single damascene or dual damascene) interconnection structure may be formed on the SOT layer so that the back end interconnection structure is in electrical communication to the MTJ structure. A chemical mechanical polishing process (CMP) may be utilized while forming the MTJ structure as well as the back end interconnection structure. The MTJ structure as well as the back end interconnection structure may be integratedly formed in a cluster processing system without transferring the substrate out of the system and without breaking vacuum. In some examples, multiple MTJ structures may be connected to the SOT layer that is in further electrical connection to the back end (e.g., single damascene or dual damascene) interconnection structure.

<FIG> is a schematic, top plan view of an exemplary cluster processing system <NUM> that includes one or more of the processing chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> that are incorporated and integrated therein. In one embodiment, the cluster processing system <NUM> may be a Centura® or Endura® integrated processing system, commercially available from Applied Materials, Inc. , located in Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from the disclosure.

The cluster processing system <NUM> includes a vacuum-tight processing platform <NUM>, a factory interface <NUM>, and a system controller <NUM>. The platform <NUM> includes a plurality of processing chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and at least one load-lock chamber <NUM> that is coupled to a vacuum substrate transfer chamber <NUM>. Two load lock chambers <NUM> are shown in <FIG>. The factory interface <NUM> is coupled to the transfer chamber <NUM> by the load lock chambers <NUM>.

In one embodiment, the factory interface <NUM> comprises at least one docking station <NUM> and at least one factory interface robot <NUM> to facilitate transfer of substrates. The docking station <NUM> is configured to accept one or more front opening unified pod (FOUP). Two FOUPS 106A-B are shown in the embodiment of <FIG>. The factory interface robot <NUM> having a blade <NUM> disposed on one end of the robot <NUM> is configured to transfer the substrate from the factory interface <NUM> to the processing platform <NUM> for processing through the load lock chambers <NUM>. Optionally, one or more metrology stations <NUM> may be connected to a terminal <NUM> of the factory interface <NUM> to facilitate measurement of the substrate from the FOUPS 106A-B.

Each of the load lock chambers <NUM> have a first port coupled to the factory interface <NUM> and a second port coupled to the transfer chamber <NUM>. The load lock chambers <NUM> are coupled to a pressure control system (not shown) which pumps down and vents the load lock chambers <NUM> to facilitate passing the substrate between the vacuum environment of the transfer chamber <NUM> and the substantially ambient (e.g., atmospheric) environment of the factory interface <NUM>.

The transfer chamber <NUM> has a vacuum robot <NUM> disposed therein. The vacuum robot <NUM> has a blade <NUM> capable of transferring substrates <NUM> among the load lock chambers <NUM>, the metrology system <NUM> and the processing chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>.

In one embodiment of the cluster processing system <NUM>, the cluster processing system <NUM> may include one or more processing chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, which may be a deposition chamber (e.g., physical vapor deposition chamber, chemical vapor deposition, or other deposition chambers), annealing chamber (e.g., high pressure annealing chamber, RTP chamber, laser anneal chamber), etch chamber, cleaning chamber, curing chamber, lithographic exposure chamber, or other similar type of semiconductor processing chambers. In some embodiments of the cluster processing system <NUM>, one or more of processing chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, the transfer chamber <NUM>, the factory interface <NUM> and/or at least one of the load lock chambers <NUM>.

The system controller <NUM> is coupled to the cluster processing system <NUM>. The system controller <NUM>, which may include the computing device <NUM> or be included within the computing device <NUM>, controls the operation of the cluster processing system <NUM> using a direct control of the process chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the cluster processing system <NUM>. Alternatively, the system controller <NUM> may control the computers (or controllers) associated with the process chambers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the cluster processing system <NUM>. In operation, the system controller <NUM> also enables data collection and feedback from the respective chambers to optimize performance of the cluster processing system <NUM>.

The system controller <NUM>, much like the computing device <NUM> described above, generally includes a central processing unit (CPU) <NUM>, a memory <NUM>, and support circuit <NUM>. The CPU <NUM> may be one of any form of a general purpose computer processor that can be used in an industrial setting. The support circuits <NUM> are conventionally coupled to the CPU <NUM> and may comprise cache, clock circuits, input/output subsystems, power supplies, and the like. The software routines transform the CPU <NUM> into a specific purpose computer (controller) <NUM>. The software routines may also be stored and/or executed by a second controller (not shown) that is located remotely from the cluster processing system <NUM>.

<FIG> depicts a plan view of another example of a cluster processing system <NUM> that the methods described herein may be practiced. One processing system that may be adapted to benefit from the disclosure is a <NUM> or <NUM> PRODUCER® processing system, commercially available from Applied Materials, Inc. , of Santa Clara, California. The cluster processing system <NUM> generally includes a front platform <NUM> where substrate cassettes <NUM> included in FOUPs <NUM> are supported and substrates are loaded into and unloaded from a loadlock chamber <NUM>, a transfer chamber <NUM> housing a substrate handler <NUM> and a series of tandem processing chambers <NUM> mounted on the transfer chamber <NUM>.

Each of the tandem processing chambers <NUM> includes two process regions for processing the substrates. The two process regions share a common supply of gases, common pressure control, and common process gas exhaust/pumping system. Modular design of the system enables rapid conversion from one configuration to any other. The arrangement and combination of chambers may be altered for purposes of performing specific process steps. Any of the tandem processing chambers <NUM> can include a lid according to aspects of the disclosure as described below that includes one or more chamber configurations. It is noted that the cluster processing system <NUM> may be configured to perform a deposition process, etching process, curing processes, lithographic exposure process or heating/annealing process as needed.

In one implementation, the cluster processing system <NUM> can be adapted with one or more of the tandem processing chambers having supporting chamber hardware known to accommodate various other known processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, etching, curing, lithographic exposure or heating/annealing process and the like. For example, the cluster processing system <NUM> can be configured with one of the processing chambers <NUM> as a chemical vapor deposition processing chamber or a physical vapor deposition chamber for forming a passivation layer or a metal containing dielectric layers, metal layers or insulating materials formed on the substrates. Such a configuration can enhance research and development fabrication utilization and, if desired, substantially eliminate exposure of films as etched to atmosphere.

A controller <NUM>, including a central processing unit (CPU) <NUM>, a memory <NUM>, and support circuits <NUM>, is coupled to the various components of the cluster processing system <NUM> to facilitate control of the processes of the present disclosure. The memory <NUM> can be any computer-readable medium, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote to the cluster processing system <NUM> or CPU <NUM>. The support circuits <NUM> are coupled to the CPU <NUM> for supporting the CPU in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. A software routine or a series of program instructions stored in the memory <NUM>, when executed by the CPU <NUM>, executes the tandem processing chambers <NUM>.

<FIG> depicts a flow diagram illustrating a process <NUM> for manufacturing MTJ structures and back end interconnection structures on a substrate for MRAM applications according to one embodiment of the present disclosure. It is noted that the process <NUM> for manufacturing MTJ structures and back end interconnection structures may be utilized in spin-transfer-torque magnetic random access memory (STT MRAM), spin-orbit-torque magnetic random access memory (SOT MRAM), and/or the hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications, particularly in hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. <FIG> are schematic cross-sectional views of an interconnection structure <NUM> formed on a substrate <NUM> at various stages of the process of <FIG>. It is contemplated that the process <NUM> may be performed in suitable processing chambers, including deposition chambers, etching chambers or other suitable processing chambers incorporated in the cluster processing systems <NUM> or <NUM> depicted in <FIG> and <FIG>. It is also noted that the process <NUM> may be performed in suitable processing chambers, including those from other manufacturers.

The process <NUM> begins at operation <NUM> by providing a substrate, such as the substrate <NUM> having a first interconnection structure <NUM> formed in a first insulating structure <NUM>, as shown in <FIG>. The first interconnection structure <NUM> and the first insulating structure <NUM> may be formed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. In one embodiment, the substrate <NUM> comprises metal or glass, silicon, dielectric bulk material and metal alloys or composite glass, crystalline silicon (e.g., Si<<NUM>> or Si<<NUM>>), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate <NUM> may have various dimensions, such as <NUM>, <NUM>, <NUM> or other diameter, as well as, being a rectangular or square panel. Unless otherwise noted, examples described herein are conducted on substrates with a <NUM> diameter, a <NUM> diameter, or a <NUM> diameter substrate. In one embodiment, the substrate <NUM>, as shown in <FIG>, includes the first interconnection structure <NUM> formed in the first insulating structure <NUM> disposed on the substrate <NUM>.

The first insulating structure <NUM> may comprise a dielectric material, such as SiN, SiCN, SiO<NUM>, SiON, SiC, amorphous carbon, SiOC or other suitable low dielectric constant material and the like. The first interconnection structure <NUM> includes a metal containing material, such as aluminum, tungsten, copper, nickel, and the like. In one example, the first insulating structure <NUM> includes a low dielectric constant dielectric material, such as SiOC, and the first interconnection structure <NUM> includes copper.

At operation <NUM>, a film stack <NUM> and a hardmask layer <NUM> are disposed on the substrate <NUM>, as shown in <FIG>. The film stack <NUM> and the hardmask layer <NUM> may be formed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. The film stack <NUM> further includes a first ferromagnetic layer <NUM> and a second ferromagnetic layer <NUM> sandwiching a tunneling barrier layer <NUM>. Though the film stack <NUM> described in <FIG> only includes three layers, it is noted that additional or multiple film layers can be further formed in the film stack <NUM> as needed. One of the examples of the additional or multiple film layers formed in the film stack <NUM> is further described below with reference to <FIG>. The tunneling barrier layer <NUM> may be an oxide barrier layer in the case of a tunnel junction magnetoresistive (TMR) sensor or a conductive layer in the case of a giant magnetoresistive (GMR) sensor. When the film stack <NUM> is configured to form a TMR sensor, then the tunneling barrier layer <NUM> may comprise MgO, HfO<NUM>, TiO<NUM>, TaOx, Al<NUM>O<NUM>, or other suitable materials. In the embodiment depicted in <FIG>, the tunneling barrier layer <NUM> may comprise MgO having a thickness of about <NUM> to about <NUM> Angstroms, such about <NUM> Angstroms.

The first and second ferromagnetic layers <NUM>, <NUM> may be a metal containing material or a magnetic material, such as Mo, Ir, Ru, Ta, MgO, Hf, CoFe, CoFeB and the like. It is noted that the first and second ferromagnetic layers <NUM>, <NUM> may be fabricated from the same or different materials as needed.

The hardmask layer <NUM> is disposed on the film stack <NUM> and will be later utilized as an etching mask layer during the following patterning and/or etching process. The hardmask layer <NUM> is formed from a material that is similar to or the same as a spin-orbit-torque (SOT) layer <NUM> (shown in <FIG>), which will be later formed thereon. In one example, the hardmask layer <NUM> is fabricated from CoFeB, MgO, Ta, W, Pt, CuBi, Mo, Ru, alloys thereof, or combinations thereof.

At operation <NUM>, a patterning process, e.g., an etching process, is first performed to pattern the hardmask layer <NUM>, forming an opening area <NUM> in the hardmask layer <NUM>, as shown in <FIG>. The first patterning process may be performed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. The opening area <NUM> formed in the hardmask layer <NUM> expose a portion of the film stack <NUM> for patterning so as to form a magnetic tunnel junction (MTJ) structure <NUM> (shown in <FIG>) with a desired dimension from the film stack <NUM>.

At operation <NUM>, a second patterning process is performed to pattern (e.g., etch) the film stack <NUM> exposed by the patterned hardmask layer <NUM> to form a magnetic tunnel junction (MTJ) structure <NUM>, as shown in <FIG>, until the underlying first insulating material <NUM> is exposed. The second patterning process may be performed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. It is noted that the patterned hardmask layer <NUM> is intended to be left and remained on the film stack <NUM>, forming as part of the magnetic tunnel junction (MTJ) structure <NUM> after the patterning process performed at operation <NUM>. Thus, no additional ash or stripping process is required to remove the hardmask layer <NUM> after the second patterning process. The second patterning process for patterning the film stack <NUM> may include several steps or different recipes configured to supply different gas mixtures or etchants to etch different layers in accordance with the materials included in each layer.

During patterning, an etching gas mixture or several gas mixtures with different etching species are sequentially supplied into the substrate surface to remove the portion of the film stack <NUM> exposed by the patterned hardmask layer <NUM> from the substrate <NUM>.

The end point of the patterning process at operation <NUM> may be controlled by time or other suitable method. For example, the patterning process may be terminated after performing for between about <NUM> seconds and about <NUM> minutes until the underlying first insulating material <NUM> is exposed, as shown in <FIG>. The patterning process may be terminated by determination from an endpoint detector, such as an OES detector or other suitable detector as needed.

It is noted that although the profile of the magnetic tunnel junction (MTJ) structure <NUM> as formed after patterning the film stack <NUM> has a tapered sidewalls, it is noted that the magnetic tunnel junction (MTJ) structure <NUM> may have substantially vertical sidewall profiles or any suitable sidewall profiles with desired slopes as needed.

At operation <NUM>, after the patterning process, a deposition process is performed to form a second insulating structure <NUM> on the magnetic tunnel junction (MTJ) structure <NUM> (e.g., including the patterned hardmask layer <NUM> and the patterned film stack <NUM>), as shown in <FIG>. The second insulating structure <NUM> may be formed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. The second insulating structure <NUM> is formed having a sufficient thickness to cover the magnetic tunnel junction (MTJ) structure <NUM>. The second insulating structure <NUM> may be a dielectric layer formed by a deposition process performed after the patterning process at operation <NUM>. The second insulating structure <NUM> may be the same or similar to the first insulating structure <NUM>. In one example, the second insulating structure <NUM> includes a low dielectric constant material comprising SiOC.

At operation <NUM>, a chemical mechanical polishing process is performed to polish away the excess second insulating structure <NUM> so as to expose a top surface <NUM> of the magnetic tunnel junction (MTJ) structure <NUM> (e.g., a top surface <NUM> of the patterned hardmask layer <NUM>), as shown in <FIG>, so that the top surface <NUM> of the patterned hardmask layer <NUM> is substantially coplanar with the second insulating structure <NUM>. The CMP process as performed may remove the excess second insulating structure <NUM> without adversely damaging or over-polishing the nearby materials when the magnetic tunnel junction (MTJ) structure <NUM> is exposed. By using a relatively low polishing downforce and slow polishing rate, the second insulating structure <NUM> may be removed without damaging or over polishing away material from the magnetic tunnel junction (MTJ) structure <NUM>.

The chemical mechanical polishing process may remove or polish the second insulating structure <NUM> by using a fluid supplied during the polishing process, or by DI water. A relatively soft polishing pad, such as a pad having elasticity greater <NUM>% may be used to during the chemical mechanical polishing process. During polishing, as the polishing pad selected has a relatively soft surface, thus, slurry or other chemical fluid may be eliminated as needed. In one example, DI water may be utilized during the chemical mechanical polishing process. The chemical mechanical polishing process is followed by a cleaning process as needed to enhance the cleanliness of the substrate surface.

At operation <NUM>, a third insulating structure <NUM> is formed on the magnetic tunnel junction (MTJ) structure <NUM> and the second insulating structure <NUM>, as shown in <FIG>. The third insulating structure <NUM> may be formed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. Similarly, the third insulating structure <NUM> may be formed from any suitable deposition techniques, such as CVD, ALD, PVD, spin-coating, spray coating or any suitable deposition processes. The third insulating structure <NUM> may be the same or similar to the first or second insulating structure <NUM>, <NUM>. In one example, the third insulating structure <NUM> includes a low dielectric constant material comprising SiOC.

At operation <NUM>, another patterning process is performed to form an opening <NUM> in the third insulating structure <NUM> to expose the top surface <NUM> of the magnetic tunnel junction (MTJ) structure <NUM>, as shown in <FIG>. The pattering process may be performed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. One or more patterning masks (not shown) may be utilized to assist forming the opening <NUM> in the third insulating structure <NUM>. The patterning process is performed to pattern the third insulating structure <NUM> until the top surface <NUM> of the magnetic tunnel junction (MTJ) structure <NUM> is exposed.

At operation <NUM>, a deposition process is performed to form a spin orbit torque (SOT) layer <NUM> on the substrate, filling the opening <NUM> defined in and above the third insulating structure <NUM>, as shown in <FIG>. The deposition process may be performed in one or more of the processing chambers incorporated in the cluster processing system <NUM> or <NUM> depicted in <FIG> and <FIG>. The material of the spin orbit torque (SOT) layer <NUM> is selected to be similar or the same as the hardmask layer <NUM> so as to promote the electrical performance of the magnetic tunnel junction (MTJ) structure <NUM>. Furthermore, as the material of the spin orbit torque (SOT) layer <NUM> and the hardmask layer <NUM> are similar or the same, the manufacturing concerns or complexity may be reduced as the adhesion control at the interface between the spin orbit torque (SOT) layer <NUM> and the hardmask layer <NUM> is relatively easy and compatible. The hardmask layer <NUM> remained in the magnetic tunnel junction (MTJ) structure <NUM> may also serve as a capping layer to provide a good electrical contact to the spin orbit torque (SOT) layer <NUM>. In one embodiment, the spin orbit torque (SOT) layer <NUM> is fabricated from Ta, Ru, MgO, W, Pt, CuBi, Mo, or combinations thereof.

At operation <NUM>, a chemical mechanical polishing process is further performed to polish away the excess spin orbit torque (SOT) layer <NUM> so as to have a top surface <NUM> of the spin orbit torque (SOT) layer <NUM> substantially coplanar with a top surface <NUM> of the third insulating structure <NUM>, as shown in <FIG>. The CMP process as performed may remove the excess spin orbit torque (SOT) layer <NUM> without adversely damaging or over-polishing the nearby materials so that the excess spin orbit torque (SOT) layer <NUM> can be filled in the third insulating structure <NUM> with the desired dimension to provide electrical connection to the underlying magnetic tunnel junction (MTJ) structure <NUM>. By using a relatively low polishing downforce and slow polishing rate, the excess spin orbit torque (SOT) layer <NUM> may be removed, without damaging or over polishing away material from the magnetic tunnel junction (MTJ) structure <NUM> and the third insulating structure <NUM>.

After the SOT layer <NUM> is formed in the third insulating structure <NUM>, an additional interconnection structure <NUM> is formed above the spin orbit torque (SOT) layer <NUM> to provide electrical connection and/or communication to the magnetic tunnel junction (MTJ) structure <NUM>, as shown in <FIG>. The additional interconnection structure <NUM> is also formed in a fourth insulating structure <NUM> to form a back end structure that has electrical contact and communication to the magnetic tunnel junction (MTJ) structure <NUM>. The additional interconnection structure <NUM> formed in the fourth insulating structure <NUM> is a single damascene structure. It is noted that the additional interconnection structures may be formed in other forms, such as dual damascene structure or other suitable structures.

<FIG> depicts another example of an interconnection structure <NUM> formed on the substrate <NUM>. Similar to the interconnection structure <NUM> depicted in <FIG>, the interconnection structure <NUM> includes the first interconnection structure <NUM> formed in the first insulating structure <NUM>, the magnetic tunnel junction (MTJ) structure <NUM> formed on the first interconnection structure <NUM> and a SOT layer <NUM> formed on the magnetic tunnel junction (MTJ) structure <NUM>. However, the SOT layer <NUM> in this example as shown in <FIG> has a relatively longer width that allows additional two upper interconnection structures 504a, 504b formed thereon. The two upper interconnection structures 504a, 504b each has a first conductive line 506a, 506b connecting to the SOT layer <NUM> while a second conductive line 508a, 508b connecting to two lower interconnection structures 502a, 502b. The upper interconnection structures 504a, 504b as utilized here are dual damascene structures. The two upper interconnection structures 504a, 504b are in direct contact and in electrical connection/communication with the two lower interconnection structures 502a, 502b through the second conductive line 508a, 508b. The first interconnection structure <NUM> and the magnetic tunnel junction (MTJ) structure <NUM> may be vertically interposed between the two upper interconnection structures 504a, 504b and the two lower interconnection structures 502a, 502b, as shown in <FIG>.

<FIG> depicts yet another example of an interconnection structure <NUM> formed on the substrate <NUM>. The interconnection structure <NUM> comprises multiple, such as three, magnetic tunnel junction (MTJ) structures 452a, 452b, 452c each formed on a lower interconnection structure 602a, 602b, 602c. The SOT layer <NUM> has a relatively long width so as to allow additional two upper interconnection structures 640a, 640b formed on the SOT layer <NUM>. In this example, the upper interconnection structures 640a, 640b are not in direct contact with the lower interconnection structures 602a, 602b, 602c. Instead, the upper interconnection structures 640a, 640b is in electrical connection/communication with the lower interconnection structures 602a, 602b, 602c through the SOT layer <NUM> and the three magnetic tunnel junction (MTJ) structures 452a, 452b, 452c interposed therebetween. By utilizing the multiple magnetic tunnel junction (MTJ) structures 452a, 452b, 452c and the interconnection structures 602a, 602b, 602c, 640a, 640b, the electrical performance may be enhanced and device densities may be increased.

<FIG> depicts another example of a magnetic tunnel junction (MTJ) <NUM>. The magnetic tunnel junction (MTJ) <NUM> may be utilized as the magnetic tunnel junction (MTJ) <NUM> depicted in <FIG>, <FIG> and <FIG> as well. The magnetic tunnel junction (MTJ) <NUM> includes the film stack <NUM> depicted above with the first ferromagnetic layer <NUM> and the second ferromagnetic layer <NUM> sandwiching the tunneling barrier layer <NUM>. In additional to the film stack <NUM>, a seed layer <NUM> may be formed in a bottom of the magnetic tunnel junction (MTJ) <NUM>. The materials may be utilized to form the seed layer <NUM> including NiCr, Pt, Cr, CoFeB, Ta, Ru, TaN, alloys or combinations thereof. A pinned layer <NUM> may be formed on the seed layer <NUM>. The pinned layer <NUM> may comprise one or more of several types of pinned layers, such as a simple pinned, antiparallel pinned, self-pinned or antiferromagnetic pinned sensor. In one example depicted in <FIG>, the pinned layer <NUM> includes multiple layers, such as four layers. It is noted that the number of the pinned layer <NUM> may be any number as needed. The pinned layer <NUM> may be constructed of several magnetic materials such as a metal alloy with dopants, such as boron dopants, oxygen dopants or other suitable materials. Metal alloys may be a nickel containing material, platinum containing material, Ru containing material, a cobalt containing material, tantalum containing materials and palladium containing materials. Suitable examples of the magnetic materials that may comprise the pinned layer <NUM> include Ru, Ta, Co, Pt, Ni, TaN, NiFeOx, NiFeB, CoFeOxB, CoFeB, CoFe, NiOxB, CoBOx, FeBOx, CoFeNiB, CoPt, CoPd, TaOx and the like.

An Ruderman-Kittel-Kasuya-Yosida (RKKY) layer <NUM> (also called a coupling layer) may be disposed on the pinned layer <NUM> below the film stack <NUM>. The RKKY layer <NUM> may be formed to control spin directions in the magnetic tunnel junction (MTJ) <NUM>. The materials utilized to fabricate the RKKY layer <NUM> include Ir, Ru, Ta, W, Mo, alloys thereof, or combinations thereof.

A capping layer <NUM> may be formed on the film stack <NUM>. In the example depicted above, the capping layer <NUM> may be the patterned hardmask layer <NUM> described above with reference to <FIG>, <FIG> and <FIG>. In some examples, additional capping layers may be formed on the film stack <NUM>, on the patterned hardmask layer <NUM> or other suitable positions in the magnetic tunnel junction (MTJ) <NUM> as needed. Suitable examples of the capping layer <NUM> (or the patterned hardmask layer <NUM>) include one or more layers of at one or more of CoFeB, MgO, Ta, W, Pt, CuBi, Mo, Ru, alloys thereof and combinations thereof. In one example, the film stack <NUM> in total includes multiple layers including TaN, NiCr, Co, Ni, Ir, Co or Ni, Mo, CoFeB, MgO, CoFeB, Mo, CoFeB, MgO, CoFeB, Mo and Ru layers.

In the example depicted in <FIG>, all these layers or film stack <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be formed by any suitable techniques, such as CVD, PVD, ALD, spin-coating, spray coating, and any suitable manners. One example of systems that may be used to form these layers includes CENTURA®, PRECISION <NUM>® and PRODUCER® deposition systems, all available from Applied Materials Inc. , Santa Clara, California, or from other manufactures. It is contemplated that other processing system, including those available from other manufacturers, may be adapted to practice the disclosure. It is noted that all these layers and film stack <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in the magnetic tunnel junction (MTJ) <NUM> may be formed in one or more processing chambers incorporated in the cluster processing system <NUM>, <NUM> depicted in <FIG> and <FIG>.

Claim 1:
An interconnection structure (<NUM>) comprising:
at least three magnetic tunnel junction structures (<NUM>, 452a, 452b, 452c) disposed on a substrate (<NUM>), a first magnetic tunnel junction structure of the at least three magnetic tunnel junction structures (<NUM>, 452a, 452b, 452c) comprising:
a patterned film stack (<NUM>) comprising a first ferromagnetic layer (<NUM>), a tunneling barrier layer (<NUM>) and a second ferromagnetic layer (<NUM>) disposed on and contacting a top surface of a first lower interconnection structure (<NUM>), wherein the first ferromagnetic layer (<NUM>) and the second ferromagnetic layer (<NUM>) sandwich the tunneling barrier layer (<NUM>); and
a patterned hardmask layer (<NUM>) disposed on the first ferromagnetic layer (<NUM>), the patterned hardmask layer (<NUM>) is configured to form a barrier to etching of the patterned film stack;
a spin orbit torque (SOT) layer (<NUM>) having a bottommost surface disposed on and contacting a top surface (<NUM>) of the patterned hardmask layer, wherein the SOT layer (<NUM>) is electrically conductive; and
multiple back end structures (640a, 640b) disposed on the SOT layer (<NUM>).