Patent Description:
Numerous embodiments of analog neural memory arrays are disclosed. Synapsis weights are stored in differential cell pairs in an array. Power consumption is substantially constant from bit line to bit line within the array when cells are being read. Weight mapping is performed adaptively for optimal performance in power and noise.

<CIT> discloses that in an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values in pairs of floating gate transistors.

<CIT> discloses system and methods for a vector-by-matrix multiplier (VMM) module having a three-dimensional memory matrix of nonvolatile memory devices each having a charge storage, an activation input, a signal input and an output signal in a range that is based on a stored charge and an input signal during assertion of the activation signal.

<CIT> discloses that improved STT MRAM source line configurations are provided.

<CIT> discloses that the present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells.

<CIT> discloses that numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

<CIT> discloses that numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.

<CIT> discloses that first and second bit lines are arranged on one side of each sense amplifier while third and fourth bit lines are arranged on the other side thereof.

<CIT> discloses that the present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits.

<CIT> discloses a nonvolatile memory device including a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line.

<CIT> discloses a layout of a non-volatile flash memory and a formation method for the same.

<CIT> discloses a semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes the artificial neural network adaptive to inputs and capable of learning. Typically, artificial neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical artificial neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, published as <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.

Examples of different non-volatile memory cells that can be used in VMMs will now be discussed.

Various types of known non-volatile memory cells can be used in the VMM arrays. For example, <CIT> ("the '<NUM> patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the drain region <NUM> towards the source region <NUM> (source line terminal). The electrons will accelerate and become energized (heated) when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM> in the channel region next to the drain region <NUM>, and erasing is performed using by Fowler-Nordheim electron tunneling from floating gate <NUM> to substrate <NUM>. The read operations operate in a similar manner to that described previously for memory cell <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

<FIG> depicts twin split-gate memory cell <NUM>. Twin split-gate memory cell <NUM> comprises a pair of memory cells (A on the left and B on the right), wherein each of the memory cells comprise a floating gate (FGA, FGB) <NUM> disposed over and insulated from the substrate <NUM>, a control gate <NUM> (CGA, CGB) disposed over and insulated from the floating gate <NUM>, an erase gate <NUM> (EG) disposed adjacent to and insulated from the floating and control gates <NUM>/<NUM> and disposed over and insulated from the substrate <NUM>, where the erase gate is created with a T shape such that a top corner of each control gate CGA, CGB faces the respective inside corner of the T shaped erase gate to improve erase efficiency, and a drain region <NUM> (DRA, DRB) in the substrate adjacent the floating gate <NUM> (with a bit line contact <NUM> (BLA, BLB) connected to the respective drain diffusion regions <NUM> (DRA, DRB). The memory cells are formed as pairs of memory cells sharing a common erase gate <NUM>. This cell design differs from that the memory cells discussed above with reference to <FIG> at least in that it lacks a source region under the erase gate EG, lacks a select gate (also referred to as a word line), and lacks a channel region for each memory cell. Instead, a single continuous channel region <NUM> extends under both memory cells (i.e. extends from the drain region <NUM> of one memory cell to the drain region <NUM> of the other memory cell). To read or program one memory cell, the control gate <NUM> of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate <NUM> there between (e.g. to read or program cell A, the voltage on FGB is raised via voltage coupling from CGB to turn on the channel region portion under FGB). Erasing is performed using Fowler Nordheim electron tunneling from floating gate 20A and/or floating gate 20B to erase gate <NUM>. Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM>.

Table No. <NUM> depicts typical voltage ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations. Cell A (FG,CGA,BLA) is selected for read, program, and erase operation.

In order to utilize the memory arrays comprising one of the types of non-volatile memory cells described above in an artificial neural network, in one embodiment, two modifications are made.

In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state or from a fully erased state to a fully programmed state, independently and with minimal disturbance of other memory cells. This means the cell storage is analog or at the very least can store one of many discrete values (such as <NUM> or <NUM> different values), which allows for very precise and individual tuning of all the cells in the memory array, and which makes the memory array ideal for storing and making finely tuned synapsis weights of the neural network.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and other volatile synapse cells, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

The purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. The synapses CB2 going from layer S <NUM> to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of <NUM> pixel.

<FIG> is a block diagram of a system that can be used for that purpose. VMM system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> comprises VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of non-volatile memory cell array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level (e.g., current, voltage, or charge), binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

Here, the inputs to VMM array <NUM> are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array <NUM> emerges on the source lines (SLO, SL1).

As described herein for neural networks, the non-volatile memory cells of VMM array <NUM> are preferably configured to operate in a sub-threshold region.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in sub-threshold region: <MAT> where <MAT>
where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>.

Here, wp is w of a reference or peripheral memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: Vg= n*Vt*log [Ids/wp*Io].

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely <MAT> <MAT> <MAT> Here, wa = w of each memory cell in the memory array and wp is w of a reference or peripheral memory cell.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> <MAT> i.e. weight W in the linear region is proportional to (Vgs-Vth).

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> W α (Vgs-Vth)<NUM>, i.e. weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.

Second, memory array <NUM> effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 - BLN, and will be the input to the next layer or input to the final layer. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the output emerges on the bitlines (BL0 - BLN) during a read operation.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased and the sequence of partial programming operations restarted. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

The input to the VMM arrays can be an analog level, a binary level, timing pulses, or digital bits and the output can be an analog level, a binary level, timing pulses, or digital bits (in this case an output ADC is needed to convert output analog level current or voltage into digital bits).

For each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> or more cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W = W+ - W-). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells.

One drawback of prior art arrays of non-volatile memory cells is that there is a large variance in source impedance of the array and along array output lines (such as bit lines), and a consequent variance in precision and power consumption, depending on which cell and its state is selected for a read, program, or erase operation. Another drawback is that it may be susceptible to noise.

What is needed is an improved VMM system that has a lower susceptibility to noise.

What is further needed is an improved VMM system that has a substantially constant source impedance of the array during an operation (read, program, or erase) regardless of which cell or cells are selected.

What is further needed is an improved VMM system that has a substantially constant power consumption during an operation (read, program, or erase) regardless of which cell or cells are selected.

The present invention is defined in independent claim <NUM>. Preferred aspects are defined in dependent claims <NUM>-<NUM>. In the following description only embodiments or examples comprising all the features of independent claim <NUM> fall under the conferred scope of protection. Numerous embodiments of analog neural memory arrays are disclosed Each memory cell in the array has an approximately constant source impedance when that cell is being operated. Power consumption is substantially constant from bit line to bit line within the array when cells are being read. Weight weight mapping is performed adaptively for optimal performance in power and noise.

<FIG> depicts a block diagram of VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, row decoders <NUM>, high voltage decoders <NUM>, column decoders <NUM>, bit line drivers <NUM>, input circuit <NUM>, output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. VMM system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. VMM system <NUM> further comprises algorithm controller <NUM>, analog circuitry <NUM>, control logic <NUM>, and test control logic <NUM>. The systems and methods described below can be implemented in VMM system <NUM>.

Input circuit <NUM> may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), DTC (digital to time converter), AAC (analog to analog converter, such as current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. Input circuit <NUM> may implement normalization, scaling functions, or arithmetic functions. Input circuit <NUM> may implement a temperature compensation function on the input such as modulate the output voltage/current/time/pulse(s) as a function of temperature. Input circuit <NUM> may implement activation function such as ReLU or sigmoid.

Output circuit <NUM> may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as current to voltage converter), ATC (analog to time converter), APC (analog to pulse(s) converter), or any other type of converter. Output circuit <NUM> may implement activation function such as ReLU or sigmoid. Output circuit <NUM> may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) on the neuron outputs, which are the outputs of VMM array <NUM>. Output circuit <NUM> may implement a temperature compensation function on the neuron outputs (such as voltage/current/time/pulse(s) ) or array outputs (such as bitline outputs) such as to keep power consumption of the VMM array <NUM> approximately constant or to improve precision of the VMM array <NUM> (neuron) outputs such as by keeping the I-V slope approximately the same.

<FIG> depicts prior art VMM system <NUM>. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>, exemplary bit line switch 1803a, 1803b, 1803c, 1803d (which connects bit lines to sensing circuitry), exemplary dummy bit line switch 1804a, 1804b, 1804c, 1004d (which couples to a low bias level such as ground (or near ground) level in read), and exemplary dummy cells <NUM> and <NUM> (source line pull down cells). Bit line switch 1803a is coupled to a column of cells, including cells <NUM> and <NUM>, that are used to store data in VMM system <NUM>. Dummy bit line switch 1804a, 1804b, 1804c, <NUM> are each coupled to a column (bitline) of cells that are dummy cells are not used to store data in VMM system <NUM>. This dummy bitline, which can also be referred to as a source line pulldown bitline, is used as a source line pull down during read operations, meaning that it is used to pull the source line to a low bias level, such as ground (or near ground), through the dummy cells in the dummy bitline. It is to be noted that dummy bit line switch 1804a, 1804b, 1804c, <NUM> and bit line switch 1803a, 1803b, 1803c, 1803d both appear on the same end of the array, i.e. they all appear at a common end of the column of cells to which they coupled, and are thus are arrayed in a single row.

One drawback of VMM system <NUM> is that the input impedance for each cell varies greatly due to the length of the electrical path through the relevant bit line switch, the cell itself, and the relevant dummy bit line switch. For example, <FIG> shows the electrical path through bit line switch <NUM>, cell <NUM>, dummy cell <NUM>, and dummy bit line switch <NUM>. Similarly, Figure 18C shows the electrical path through bit line switch <NUM>, vertical metal bitline <NUM>, cell <NUM>, dummy cell <NUM>, vertical metal bitline <NUM>, and dummy bit line switch <NUM>. As can be seen, the path through cell <NUM> traverses a significantly larger length of bit line and dummy bit line, which is associated with a higher capacitance and higher resistance. This results in cell <NUM> having a greater parasitic impedance in the bit line or source line than cell <NUM> in <FIG>. This variability is a drawback, for instance, because it results in a variance in the precision of the cell output as applied to read or verify (for program/erase tuning cycles) cells depending on their location within the array.

<FIG> depicts VMM system <NUM>, which improves upon prior art VMM system <NUM>. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>; exemplary bit line switches 1903a, 1903b, 1903c, and 1903d, which connect the bit lines to sensing circuitry; exemplary dummy cells <NUM> and <NUM>, which can serve as source line pull down cells; and exemplary dummy bit line switches 1904a, 1904b, 1904c, and 1904d. As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation, and the other end connects to dummy cells <NUM> and <NUM> that are used as a source line pull down. As can be seen, exemplary dummy bit line switch 1904a and the other dummy bit line switches are located on the opposite end of the array from bit line switch 1903a and the other bit line switches.

The benefit of this design can be seen in <FIG> and 19C. In <FIG>, cell <NUM> is selected for reading, and in Figure 19C, cell <NUM> is selected for reading.

<FIG> depicts the electrical path through bit line switch <NUM>, cell <NUM>, dummy cell <NUM> (source line pull down cell), vertical metal bit line <NUM>, and dummy bit line switch <NUM> (which couples to a low level such as ground during a read operation). Figure 19C depicts the electrical path through bit line switch <NUM>, vertical metal line <NUM>, cell <NUM>, dummy cell <NUM> (source line pull down cell), and dummy bit line switch <NUM>. The paths are substantially the same in terms of interconnect length, which is true for all cells in VMM system <NUM>. As a result, the impedance of the bit line impedance plus source line impedance of each cell is substantially the same, which means that the variance in the amount of parasitic voltage drop drawn during a read or verify operation of each cell in the array is substantially the same.

<FIG> depicts VMM system <NUM> with a global source line pulldown bitline. VMM system <NUM> is similar to VMM system <NUM>, except that: the dummy bit lines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pulldown line to pull memory cell source lines to ground level during read or verify); the dummy bit line switches, such as dummy bit line switch <NUM> and <NUM>, are connected or coupled to a common ground, labeled ARYGND (array ground); and the source lines are coupled together to source line switch <NUM>, which selectively pulls the source lines to ground. These changes further decrease the variance in parasitic impedance for each cell in the array during a read or verify operation.

In another embodiment, dummy rows can be utilized between rows as physical barriers to avoid FG-FG coupling (of two adjacent cells) between rows.

<FIG> depicts VMM system <NUM>. In some embodiments, the weights, W, stored in a VMM are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In VMM system <NUM>, half of the bit lines are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-. The W- lines are interspersed among the W+ lines in an alternating fashion. The subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits <NUM> and <NUM>. The output of a W+ line and the output of a W- line are combined together to give effectively W = W+ - W- for each pair of (W+, W-) cells for all pairs of (W+, W-) lines. Optionally, dummy bitlines and source line pulldown bitlines, such as those shown in <FIG> and <FIG>, can be used in VMM system <NUM> to avoid FG-FG coupling (of two adjacent cells) and/or to reduce IR voltage drop in the source line during a read or verify operation.

<FIG> depicts another embodiment. In VMM system <NUM>, positive weights W+ are implemented in first array <NUM> and negative weights W- are implemented in a second array <NUM>, separate from the first array, and the resulting weights are appropriately combined together by summation circuits <NUM>. Optionally, dummy bitlines and source line pulldown bitlines, such as those shown in <FIG> and <FIG>, can be used in VMM system <NUM> to avoid FG-FG coupling and/or to reduce IR voltage drop in the source line during a read or verify operation.

VMM systems can be designed such that W+ and W- pairs are placed within the array in a manner that reduces FG to FG coupling or distributes power consumption in a more even fashion across the array and the output circuits. This is described below with reference to Tables <NUM> and <NUM>. Additional details regarding the FG to FG coupling phenomena are found in <CIT> by the same assignee, and titled "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network".

Table 10A shows an exemplary physical layout of an arrangement of two pairs of (W+, W-) bit lines. One pair is BL0 and BL1, and a second pair is BL2 and BL3. In this example, <NUM> rows are coupled to source line pulldown bit line BLPWDN. BLPWDN is placed between each pair of (W+, W-) bit lines to prevent coupling (e.g., FG to FG coupling) between one pair of (W+, W-) bit lines with another pair of (W+, W-) bit lines. BLPWDN therefore serves as a physical barrier between pairs of (W+, W-) bit lines.

Table 10B shows different exemplary weight combination. A '<NUM>' means that the cell is used and has a real output value, and a '<NUM>' means the cell is not used and has no value or no significant output value.

Table 11A shows another array embodiment of a physical arrangement of (w+, w-) pair lines BL0/<NUM> and BL2/<NUM> falling under the scope of protection of the annexed claims <NUM>-<NUM>. The array includes redundant lines BL01 and BL23 and source line pulldown bit lines BLPWDN. Redundant bitline BL01 is used to re-map values from the pair BL0/<NUM>, and redundant bit line BL23 is used to re-map values from the pair BL2/<NUM>, which will be shown in later Tables.

Table 11B shows an example where the distributed weight values do not need re-mapping, basically there is no adjacent '<NUM>' between adjacent bit lines.

Table 11C shows an example where distributed weights needs to be re-mapped. Here, there are adjacent '<NUM>'s in BL1 and BL2, which causes adjacent bit line coupling. The values therefore are re-mapped as shown in Table 11D, resulting in no adjacent '<NUM>' values between any adjacent bit lines. In addition, by re-mapping, the total current along the bit line is now reduced, which leads to a more precise value in that bit line, which also leads to more distributed power consumption along the bit lines. Optionally, additional bitlines (BL01, BL23) optionally can be used to act as redundant columns.

Tables 11E and 11F depict another embodiments of remapping noisy cells (or defective cells) into the redundant columns such as BL01, BL23 in Table 11E or BLOB and BL1B in Table 11F.

Table <NUM> shows an embodiment of a physical arrangement of an array that is suitable for <FIG>. Since each bitline has either a positive weight or a negative weight, a dummy bitline acting as source line pull down or a real dummy bitline (not used, e.g., deeply or partially programmed or partially erased) and physical barrier to avoid FG-FG coupling is needed for each bit line.

In another embodiment, a tuning bit line coupled to a column of cells is adjacent to a target bitline coupled to a column of cells, and the tuning bit line cells are used to tune the target bitline cells to desired target values during a programming operation using the FG-FG coupling between adjacent cells. Optionally, a source line pull down bitline can be used on the side of the target bit line opposite the side adjacent to the tuning bitline.

Alterative embodiments for mapping noisy or defective cells can be implemented where such cells are designated as non-used cells, meaning they are to be (deeply) programed to not contribute any value to the neuron output.

Alternative embodiments for identifying fast cells (which are cells that can be programmed to reach a certain value faster than a typical cell) can be implemented, where fast cells are identified and undergo a more precise tuning algorithm to not overshoot the target during a programming operation.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises redundant array <NUM> that can be included in any of the VMM arrays discussed thus far. Redundant array <NUM> can be used as redundancy to replace defective columns if any of the columns attached to bit line switches are deemed defective. The redundant array can have its own redundant array (neuron) outputs (e.g., bit lines), and/or redundant write and verify circuits, and/or ADC circuits for redundancy purpose. For example, when redundancy is needed, the output of the redundant ADC will replace the output of the ADC of the bad bit line. Redundant array <NUM> can also be used for weight mapping such as described in Tables 10A and 10B to achieve a relatively even power distribution among bit lines.

<FIG> depicts VMM system <NUM>, which comprises array <NUM>, array <NUM>, column multiplexors <NUM>, local bit lines LBL 2305a-d, global bit lines GBL <NUM> and <NUM>, and dummy bit line switches 2305a - 2305d. The column multiplexors <NUM> are used to select the respective top local bit line <NUM> of the array <NUM> or bottom local bit line <NUM> of the array <NUM> into the global bit line <NUM>. In one embodiment, the (metal) global bit line <NUM> has the same number of lines as number of the local bit lines, e.g. <NUM> or <NUM>. In another embodiment, the global bit line <NUM> has only one (metal) line per N number of local bit lines, such as one global bit line per <NUM> or <NUM> local bit lines. The column multiplexors <NUM> can multiplex an adjacent global bit line (such as GBL <NUM>) into a global bit line of interest (such as GBL <NUM>) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line of interest (GBL <NUM>).

Various output circuits will now be described that can be used with any of the VMM systems described herein.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises array <NUM>; shift registers (SRs) <NUM>; digital-to-analog converters (DAC) <NUM>, which receives the input from the SRs <NUM> and output an equivalent (analog or pseudo-analog) level or information (e.g., voltage/timing); summer circuits <NUM>; analog-to-digital converters (ADC) <NUM>; and bit line switches (not shown). Dummy bit lines and dummy bit line switches are present but not shown. As shown, ADC circuits can be combined together to create a single ADC with greater precision (i.e., greater number of bits).

Summer circuits <NUM> can include the circuits that are shown in <FIG>. It may include circuits for normalization, scaling, arithmetic operations (e.g., addition, subtraction), activation, or statistical rounding, without limitation.

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable resistor, which comprises current source <NUM>-<NUM>,. , <NUM>-n drawing current Ineu(<NUM>),. , Ineu(n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier <NUM>, variable holding capacitor <NUM>, and variable resistor <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout = R2503 * (Ineu(<NUM>) +. + Ineu(n)), which is proportional to the sum of the currents Ineu(<NUM>),. The holding capacitor <NUM> is used to hold the output voltage when switch <NUM> is open. This holding output voltage is used, for example, for conversion into digital bits by an ADC circuit.

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable capacitor (basically an integrator), which comprises current source <NUM>-<NUM>,. , <NUM>-n drawing current Ineu(<NUM>),. Ineu (n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier <NUM>, variable capacitor <NUM>, and switch <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout <NUM> = (Ineu(<NUM>) +,. ,+ Ineu(n))*integration time/C2603, which is proportional to the sum of the currents Ineu(<NUM>),.

<FIG> depicts voltage summer <NUM> adjustable by variable capacitors (i.e., a switch cap SC circuit), which comprises switches <NUM> and <NUM>, variable capacitors <NUM> and <NUM>, operational amplifier <NUM>, variable capacitor <NUM>, and switch S1 <NUM>. When switch <NUM> is closed, input VinO is provided to operational amplifier <NUM>. When switch <NUM> is closed, input Vin1 is provided to operational amplifier <NUM>. Optionally, switches <NUM> and <NUM> are not closed at the same time. Operational amplifier <NUM> generates an output Vout, that is an amplified version of the input (either VinO and/or Vin1, depending on which switch is closed among switches <NUM> and <NUM>). That is Vout = Cin/Cout * (Vin), Cin is C2703 or C2704, Cout is C2706. For example Vout = Cin/Cout * ∑ (Vinx), Cin = C2703 = C2704, where Vinx can be either VinO or Vin1. In one embodiment, VinO is a W+ voltage and Vin1 is a W-voltage, and voltage summer <NUM> adds them together ( W+ - W-, by enabling appropriately polarity of the switches) to generate output voltage Vout.

<FIG> depicts voltage summer <NUM>, which comprises switches <NUM> (S1), <NUM> (S3), <NUM> (S2) and <NUM> (S4), variable input capacitor <NUM>, operational amplifier <NUM>, variable feedback capacitor <NUM>, and switch <NUM> (S5). In one embodiment, VinO is a W+ voltage and Vin1 is a W- voltage, and voltage summer <NUM> adds them together to generate output voltage Vout ( W+ - W-, by enabling appropriately polarity of the switches).

For Input = VinO: when switch <NUM> and <NUM> are closed and switches <NUM>, <NUM> and <NUM> are opened, input VinO is provided to top terminal of the capacitor <NUM>, whose bottom terminal is connected to VREF. Then switch <NUM> is open and switch <NUM> is closed to transfer the charge from the capacitor <NUM> into the feedback capacitor <NUM>. Basically then the output VOUT = (C2758/C2756) * VinO (for case of with VREF =<NUM> as example).

For Input = Vin1: when switches <NUM>, <NUM>, and <NUM> are closed and switches <NUM>, <NUM> and <NUM> are opened, both terminals of the capacitor <NUM> are discharged to VREF. Then switch <NUM> is opened and switch <NUM> is closed, charging the bottom terminal of the capacitor <NUM> to Vin1, which in turn charges up the feedback capacitor <NUM> to VOUT = -(C2758/C2756) * Vin1 (for case of VREF=<NUM>).

Hence, if the sequence described above for Vin1 input is implemented after the sequence described above for VinO is implemented, VOUT = (C2758/C2756) * (Vin <NUM> - Vin1), for case of VREF=<NUM> as example. This is used for example to realize W = W+ - W-.

Each ADC as shown in <FIG> can be configured to combine with next ADC for higher bit implementation with appropriate design of the ADC.

With reference again to <FIG>, inputs to and outputs from the VMM array <NUM> can be in digital or analog form. For example:.

In the embodiments that involve sequential operation of the arrays, power is more evenly distributed.

In the embodiments that utilize the neuron (bit line) binary index method, power consumption is reduced in in the array since each cell coupled to the bit line only contains binary levels, the <NUM>^n level is accomplished by the summer circuit.

<FIG> depict output circuits that can be used for summer circuits <NUM> and analog-to-digital converters <NUM> in <FIG>.

<FIG> depicts output circuit <NUM>, which comprises analog-to-digital converter <NUM>, which receives neuron output <NUM> and outputs output digital bits <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and analog-to-digital converter <NUM>, which together receive neuron output <NUM> and generates outputs <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and converter <NUM>, which together receive neuron output <NUM> and generates outputs <NUM>.

Neuron output circuit <NUM> or <NUM> can, for example, perform summing, scaling, normalization, or arithmetic operations, without limitation. Converter <NUM>, for example, can perform ADC, PDC, AAC, or APC operation, without limitation.

<FIG> depicts neuron output circuit <NUM>, which comprises adjustable (scaling) current source <NUM> and adjustable (scaling) current source <NUM>, which together generate output iOUT, which is the neuron output. This circuit can perform a summation of a positive weight, W+, and a negative weight, W-, i.e., W = W+ - W-, and up or down scaling of the output neuron current (through adjustment of the adjustable current sources <NUM> and <NUM>) at the same time. That is, IW+ is a scaled version of W+, and IW- is a scaled version of W-.

<FIG> depicts configurable serial analog-to-digital converter <NUM>. It includes integrator <NUM> which integrates the neuron output current into the integrating capacitor <NUM> (Cint).

In one embodiment, VRAMP <NUM> is provided to the inverting input of comparator <NUM>. The digital output (count value) <NUM> is produced by ramping VRAMP <NUM> until the comparator <NUM> switches polarity, with counter <NUM> counting clock pulses from the beginning of the ramp.

In another embodiment, VREF <NUM> is provided to the inverting input of comparator <NUM>. VC <NUM> is ramped down by ramp current <NUM> (IREF) until VOUT <NUM> reaches VREF <NUM>, at which point the EC <NUM> signal disables the count of counter <NUM>. The (n-bit) ADC <NUM> is configurable to have a lower precision (fewer than n bits) or a higher precision (more than n bits), depending on the target application. The configurability of precision is done by configuring the capacitance of capacitor <NUM>, the current <NUM> (IREF), the ramping rate of VRAMP <NUM>, or the clocking frequency of clock <NUM>, without limitation.

In another embodiment, the ADC circuit of a VMM array is configured to have a precision lower than n bits and the ADC circuits of another VMM array is configured to have high a precision greater than bits.

In another embodiment, one instance of serial ADC circuit <NUM> of one neuron circuit is configured to combine with another instance of serial ADC circuit <NUM> of the next neuron circuit to produce an ADC circuit with higher than n-bit precision, such as by combining the integrating capacitor <NUM> of the two instances of serial ADC circuits <NUM>.

<FIG> depicts a configurable neuron SAR (successive approximation register) analog-to-digital converter <NUM>. This circuit is a successive approximation converter that bases on charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) <NUM>, op-amp/comparator <NUM>, and SAR logic and register <NUM>. As shown GndV <NUM> is a low voltage reference level, for example ground level. SAR logic and register <NUM> provides digital outputs <NUM>.

<FIG> depicts a configurable neuron combo SAR analog-to-digital converter circuit <NUM>. This circuit combines two n-bit ADCs from two neuron circuits into one to achieve higher precision than n-bits, for example for a <NUM>-bit ADC for one neuron circuit, this circuit can achieve > <NUM>-bit precision such as <NUM>-bit ADC precision by combining two <NUM>-bit ADCs. The combo circuit topology is equivalent to a split cap (bridge-capacitor (cap) or attention cap) SAR ADC circuit, for example a <NUM>-bit 4C-4C SAR ADC resulted by combining two adjacent <NUM>-bit 4C SAR ADC circuits. A bridge circuit <NUM> (Csplit) is used to accomplish this, the capacitance of this circuit is = (total number of CDAC cap unit / total number of CDAC cap unit -<NUM>).

<FIG> depicts a pipelined SAR ADC circuit <NUM> that can be used to combine with the next SAR ADC to increase the number of bits in a pipelined fashion. SAR ADC circuit <NUM> comprises binary CDAC (DAC basing on capacitors) <NUM>, op-amp/comparator <NUM>, op-amp/comparator <NUM>, SAR logic and register <NUM>. As shown GndV <NUM> is a low voltage reference level, for example ground level. SAR logic and register <NUM> provides digital outputs <NUM>. Vin is in the input voltage, VREF is a reference voltage, and GndV is a ground voltage. Vresidue is generated by capacitor <NUM> and is provided as an input to the next stage of an SAR ADC.

Additional implementation details regarding configurable output neurons (such as configurable neuron ADC) circuits can be found in <CIT> by the same assignee, and titled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network".

It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" or "physically adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed there between), "mounted to" includes "directly mounted to" (no intermediate materials, elements or space disposed there between) and "indirectly mounted to" (intermediate.

materials, elements or spaced disposed there between), and "electrically coupled" includes "directly electrically coupled to" (no intermediate materials or elements there between that electrically connect the elements together) and "indirectly electrically coupled to" (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

Claim 1:
An analog neural memory system comprising:
an array of non-volatile split gate or stacked gate flash memory cells, wherein the cells are arranged in rows (row0 - row3) and columns,
the memory cells of each row are coupled to a respective common source line (SLO, SL1);
the columns are arranged in groups of two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)), wherein within each pair of physically adjacent columns, one column comprises cells storing positive weight values and the other column comprises cells storing negative weight values, wherein adjacent cells in a row within each pair of physically adjacent columns are configured to store differential weight bits,
the array further comprising two redundant columns (BL01, BL23), one on each side of each group of two physically adjacent pairs of physically adjacent columns,
wherein the system is configured to remap the weight bits of each physically adjacent column (BL1, BL2) of the two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)) to the corresponding redundant column resulting in no adjacent "<NUM>" weight bits between any physically adjacent column of the group;
the array further comprising two dummy cell columns configured to operate as source line pull down bit lines (BLPWDN), one on each side of each redundant column of the group, wherein each column of the two physically adjacent pairs of physically adjacent columns is coupled to bit line switches (<NUM>) on a first side of the array and the two dummy cell columns are coupled to dummy bit line switches (<NUM>) on a second side of the array opposite the first side, wherein each dummy cell column is configured to connect memory cell source lines to ground through the dummy bit line switch (<NUM>); and
the system further comprising a summer configured for generating a first sum of an output (W+) from a first bit line and generating a second sum of an output (W-) from a second bit line and outputting a difference between the first sum and the second sum (W = (W+) - (W-)).