Patent Description:
Some types of RAM store a bit of information by varying the state of the electrical resistance across the RAM cell. These resistive RAM (ReRAM) modules include a memristor element located between two electrodes. By introducing a voltage to the memristor element, a pattern of conductive defects can be created in the memristor element. This pattern is often referred to as a conductive filament and can be controlled to switch the memristor element between high- and low-resistance states.

The present invention provides a method of forming a resistive RAM module. The method comprises applying a set of seed pillars to a surface of a layer of the resistive RAM module. The seed pillars are applied perpendicular to the surface. The layer comprises a source electrode embedded in an inter-layer dielectric. The method also comprises depositing nitride on the sidewalls of the seed pillars such that nitride accumulation creates a set of nitride borders that surround the seed pillars. Each nitride border in the set partially overlaps at least two other nitride borders such that a gap is formed in the center of the nitride borders. The method also comprises depositing an intermediate electrode on top of the source electrode and in the gap. The method also comprises removing the seed pillars. The method also comprises depositing a memristor element on the intermediate electrode and depositing a sink electrode on the memristor element.

The present invention also provides a corresponding computer program product. The computer program product comprises a computer readable storage medium that has program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform the above method of forming a resistive RAM module. Preferably, the present invention provides a computer program product, wherein the intermediate electrode has a concave closed-curve profile. Preferably, the present invention provides a computer program product, wherein the memristor element shares the concave closed-curve profile. Preferably, the present invention provides a computer program product, wherein the sink electrode forms a negative pattern of the concave closed-curve profile. Preferably, the present invention provides a computer program product, wherein the concave closed-curve profile has six points.

<CIT> describes a method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, which may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. <CIT> describes a method for fabricating a semiconductor device including a resistive memory cell having a single fin which includes concurrently forming a vertical transistor and a resistive element on a base substrate, including forming a first gate structure corresponding to a gate of the vertical transistor and a second gate structure corresponding to an electrode of the resistive element, forming a top source/drain layer on a fin formed on a bottom source/drain layer disposed on the base substrate, and forming a plurality of contacts. <CIT> describes a method of fabricating a solid state electrolytes memory device. An insulator layer is formed on a substrate. A conductive layer is formed on the insulator layer. At least two openings partially overlapped and capable of communicating with each other are formed in the conductive layer, so that the conductive layer forms at least a pair of tip electrodes. Thereafter, solid state electrolytes are filled in the openings. <CIT> describes a sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) which may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall. <CIT> illustrates a method for fabricating a FET with a hybrid gate spacer between a gate mandrel and a source/drain semiconductor; and <CIT> discloses a method of formation of RRAM cells being arranged between higher bottom electrodes and top electrodes, respectively and in an alternating manner.

Random access memory (referred to herein as "RAM") is a form of computer storage in which information can be stored for fast retrieval by another computer component, such as a processor. RAM, for example, is found in the cache memory of many processors and is used as the main memory in many computer systems. The structure of RAM and process by which RAM stores information varies based on the form of RAM used. For example, RAM used in processor cache sometimes the form of a six-transistor memory cell, whereas RAM used in system memory sometimes takes the form of a transistor-capacitor cell. In typical RAM formats, a cell can store one bit of information, and the state of the cell (e.g., charged or not charged) can be used to set the bit on or off (also referred to as setting the bit to "true" or "false," to "<NUM>" or "<NUM>," and some others).

In resistive RAM (referred to herein as "ReRAM") for example, a memory cell takes the form of a dielectric solid-state material, sometimes referred to as a "memristor" or "memristor element. " For example, a ReRAM module sometimes takes the form of an oxide layer that is placed between two electrodes (sometimes referred to as a "source" electrode and a "sink" electrode, a "bottom" electrode and a "top" electrode, or a "word line" electrode and a "bit line" electrode) in a memory stack. While typically nonconductive, allowing oxide defects to form in this oxide layer can cause the resistance of the material to change, becoming electrically conductive. These oxide defects are sometimes referred to as "oxygen vacancies," and describe locations of oxide bonds at which the oxygen has been removed (typically migrated to other portions of the oxide layer). Once these defects are formed in a continuous path (sometimes referred to as a "filament" or "conductive filament") between two ends of the memristor, the electrical resistance between those two ends can drop significantly. Further, when an electric field of a particular voltage is subsequently applied to the memristor, the oxygen that was previously removed from the oxide-bond locations (i.e., the oxygen vacancy locations in the filament) can migrate back to the previous oxide-bond locations. When this happens, the "filament" is deformed, and the electrical resistances between those two ends of the memristor increase significantly again. This process is reversible. Thus, by applying electrical fields of particular voltages to the memristor, the memristor can be switched between a state of high resistance and a state of low resistance.

Thus, in ReRAM, an electrical charge can be applied to the memory module in order to switch the electrical resistance of the module between a first resistance value (sometimes referred to as "high resistance" and a second resistance value (sometimes referred to as "low resistance"). The state of the module can be taken advantage of to store information. For example, by setting each state to either a <NUM> or <NUM> (for example, setting the high-resistance state to "<NUM>" and the low-resistance stage to "<NUM>"), the state of that memristor can be used to store one bit of information.

Unlike some other types of RAM, ReRAM is considered non-volatile, meaning that it does not lose its stored information when it is not powered. In other words, the state of ReRAM (high resistance or low resistance) is stable when power is shut off from the computer system. For this reason, ReRAM has potential benefits in longer-term storage, such as a replacement (or supplement) to hard disk drives and solid-state drives. If successfully applied in long-term storage, ReRAM could offer significant storage boosts to computer systems due to ReRAM's low read latency and high write speed as compared with other long-term storage solutions.

However, difficulties in forming ReRAM can make utilizing ReRAM in storage systems difficult, if not completely unfeasible. For example, as discussed, in order for ReRAM to be formed, a sufficient voltage must be applied across the ReRAM module to form a continuous path of oxide defects (i.e., a conductive filament). This "sufficient voltage" is sometimes referred to as a formation voltage.

However, while the application of the formation voltage can be controlled, the precise location of the oxide defects that form as a result of the formation voltage can be very difficult to control. The random formation of a filament can cause variance in the resistance of the ReRAM device. In very large binary memory structures (e.g., memory chips with a relatively high amount of space between each memory cell on a bit line, a word line, or both), this may be unlikely to cause issues as the resistance variances of the on and off states are sufficiently far apart to discern with sensing circuitry.

In these large memory structures, memristor elements are also often large and isolated from other switching elements. Thus, even in ReRAM modules in which the chance of filament formation is relatively equal in all areas of the memristor element, the chance of the filament being formed at the very edge of the memristor is low. However, as memory structures, ReRAM modules, and memristor elements shrink, the distance between the center of the memristor element and the very edge of the memristor element also shrinks. Thus, the chances that a filament forms at the very edge of the memristor increases. As a result, variance in the resistance between the on and off states in these smaller ReRAM structures can be significant in smaller memory structures. In some instances, ReRAM filaments can form with a resistance that is between the "fully on" and "fully off" states. These partially formed states need to be controllably programmed in the application of artificial intelligence employed by a ReRAM array constituting a neural network. ReRAM devices without controllable filament formation will induce variance in the resistance of the partial states, which may require additional circuitry to sense or correct.

For example, aa filament that is formed close to the edge of a memristor element may be at higher-than-normal risk of leakage to other elements of the memory structures. Specifically, if a conductive filament is formed very close to the edge of a memristor, a portion of the filament may be close enough to a conductive material outside the memristor to form a conductive path to that conductive material. This may effectively result in a short between one end of the conductive filament and the conductive material, which may prevent the memristor from switching from a high-resistance state to a low-resistance state. In other words, the ReRAM device may be difficult to control at normal switching voltages, or may even be completely nonfunctional. As ReRAM devices become smaller, the chance of a filament forming near the edge of the memristor element increases. Thus, there is a growing need to control the location of the filament formation with greater precision.

Finally, the process of forming a conductive filament in a typical ReRAM memory structure can require a high formation voltage. Unfortunately, the formation voltage for a typical ReRAM module is often significantly higher than the voltage that is necessary to switch the ReRAM between resistance states after the conductive filament is formed. For example, a typical ReRAM module may be designed to operate at similar voltages as other memory systems (e.g., <NUM> volts). However, forming the conductive filament in such a ReRAM module may require over <NUM> volts (i.e., the formation voltage) to be applied to the ReRAM module. Further, applying this formation voltage typically requires applying the voltage through the same pathways as the voltage by which the ReRAM is switched between states when used in a system (for example, through a bit line and word line). In other words, the formation voltage must, in some applications, be applied through the final circuit design of the ReRAM module and the associated connections to the system.

Unfortunately, applying a formation voltage (e.g., 4V) through a circuit that is only designed to handle a memory switching voltage (e.g., <NUM>. 2V) can cause damage to the circuit. For example, in a typical complementary metal oxide semiconductor (sometimes referred to as "CMOS") system, applying a voltage that is significantly higher than the voltage for which the circuit is designed could cause a short to form between the gate and the conducting channel, or across the conducting channel between the source and the drain. In cutting-edge systems with very small components, high voltage can also damage contacts and wires.

To address some of the above issues, some embodiments of the present disclosure control the location of the formation of a conductive filament in a memristor element by forming an intermediate electrode electrically between a source electrode and a sink electrode. A memristor element may be formed electrically between the intermediate electrode and the sink electrode. As used herein, the term "electrically between" refers not necessarily to an element's physical location, but the positions of a set of elements with respect to current flowing between those elements. For example, an intermediate electrode is considered electrically between a source electrode and sink electrode if a current flowing from the source electrode to the sink electrode typically passes from the source electrode and through the intermediate electrode before passing to the sink electrode. Thus, applying a voltage across the source electrode and the sink electrode would cause the same voltage to be present across the intermediate electrode and the sink electrode, which are separated by the memristor element. If this voltage is of sufficient strength, oxygen deficiencies may begin to form in the memristor element, leading to the formation of a conductive channel.

The intermediate electrode may exhibit a closed-curve cross-section profile with one or more point. A point on a closed-curve cross-section profile (sometimes also referred to herein as a "closed curve profile" or just a "profile") typically occurs where two different curves meet (similar to, for example, the corner of a square or triangle, the point on a star, the point on a teardrop shape, or the bottom point on a "heart" shape). At these points, exposure of the memristor to the electric field caused by the voltage may be higher than elsewhere. As a result, oxygen deficiencies may be more likely to form at the points, causing the conductive filament to be more likely to form there as well. In this way, the location of the formation of the conductive filament can be controlled. This may enable the protection of the filament from leaking to other structures outside the memristor element.

The curves that make up the closed-curve profile of the intermediate electrode may be convex, concave, or straight. Thus, in some embodiments, the closed-curve profile may be a concave closed-curve profile in which one or more of the curves that make up the profile is concave. In such a profile, if two concave curves meet at a point, the cross-section profile (and thus, the electrode material) at that point may be particularly narrow. This may result in the exposure to the electric field being significantly higher at that point, and thus a conductive filament may be significantly more likely to form there as well.

Further, because the exposure to the electric field may be increased at the narrow points on the intermediate electrode, a conductive filament may form near those points at lower formation voltages. As noted earlier, the formation voltage of typical memristor elements is often higher than the voltage at which a memory structure is designed to operate. For this reason, reducing the voltage that is applied to the memory structure during the formation of a conductive filament may avoid damaging other components of the memory structure that are not designed to withstand those higher voltages.

<FIG> depicts an abstract cross-section side view of a resistive RAM module <NUM> with an intermediate electrode <NUM> with a concave closed-curve profile (illustrated in the view of <FIG>). Intermediate electrode <NUM> is electrically between source electrode <NUM> and sink electrode <NUM>. Source electrode <NUM> is patterned on substrate layer <NUM> with interlayer dielectric <NUM>. Intermediate electrode <NUM> is patterned on source electrode <NUM> and is embedded within insulating layer <NUM>. Source electrode <NUM>, intermediate electrode <NUM>, and sink electrode <NUM> may be composed of, for example, titanium, titanium nitride, tungsten, or other conductive materials.

Memristor element <NUM> is electrically between intermediate electrode <NUM> and sink electrode <NUM>. Memristor element <NUM> may be a metal oxide with insulative properties, such as hafnium oxide. In the presence of a sufficient voltage across intermediate electrode <NUM> and sink electrode <NUM>, oxide defects may begin to form in memristor element <NUM>, creating a conductive filament.

<FIG> depicts an abstract top view of resistive RAM module <NUM>. As illustrated in <FIG>, the concave closed-curve profile of intermediate electrode <NUM> results in four narrow points (e.g., point <NUM>), similar to a <NUM>-point star. As will be discussed below, this profile can be used to control the formation of a conductive filament to one of four locations in memristor element <NUM>. As is also visible in <FIG>, the closed-curve profile of intermediate electrode <NUM> is shared by memristor element <NUM>, which was patterned onto intermediate electrode <NUM>.

Finally, sink electrode <NUM> was patterned onto memristor element <NUM>, causing the shape of sink electrode <NUM> to form a negative pattern of the concave closed-curve profile shared by intermediate electrode <NUM> and memristor element <NUM>. This results in sink electrode <NUM> curving around and surrounding the narrow points of intermediate electrode <NUM>, increasing the current through memristor element <NUM> at those areas when a voltage is applied across intermediate electrode <NUM> and sink electrode <NUM>. This increased current is likely to lead to a greater number of oxide defects during the application of the voltage, which in turn increases the likelihood of a formation of a conductive filament at the four narrow points.

For example, the effects of a formation voltage may be significantly greater at point <NUM> than at area <NUM>. In other words, the current that flows through memristor element <NUM> during application of a formation voltage may be higher at point <NUM> than at area. As a result, oxide defects may be more likely to form across the memristor element at point <NUM> than across the memristor element at area <NUM>. Further, in some embodiments, the increased current at point <NUM> may actually make it possible to form a conductive filament at point <NUM> at a lower formation voltage than would normally be required with typical memristor element topologies. In some instances, this lower formation voltage may result in the current that passes through the memristor element at area <NUM> to be insufficient to cause oxide defects. The resulting infeasibility of forming oxide defects at area <NUM> causes the location of the conductive filament even more controllable.

<FIG> illustrates an example result of applying a formation voltage across intermediate electrode <NUM> and sink electrode <NUM> at point <NUM>. Specifically, <FIG> depicts an abstract close-up top view of a conductive filament <NUM> formed across memristor element <NUM> between intermediate electrode <NUM> and sink electrode <NUM>. Conductive filament <NUM> is a collection of oxide defects (illustrated as small white circles) that have collected at the same place in memristor element <NUM>. As a result, a small path of conductivity has formed between intermediate electrode <NUM> and sink electrode <NUM>. If the voltage is continuously applied, current will continue to flow through conductive filament <NUM>, a greater number of oxide defects will form on filament <NUM>, causing it to grow and the resistance across memristor element <NUM> at filament <NUM> to decrease. Once the filament has reached a target size and resistance, the application of the formation voltage can be terminated. At this point, application of a switching voltage across intermediate electrode <NUM> and sink electrode <NUM> should cause conductive filament <NUM> to switch between a low resistance state (for example, as shown in <FIG>) and a high resistance state, in which the oxide defects are replaced with oxide bonds.

It is of note that, while the profile in <FIG> feature a closed curve with only concave curves, some embodiments of the disclosure may feature an intermediate electrode with one or more curves of different shapes. For example, in some embodiments an intermediate electrode may feature a polygon profile (e.g., a square, triangle, or rectangle) in which all curves are straight line segments. Some embodiments of the present disclosure may feature a profile in which the curves are convex. And some embodiments of the present disclosure may feature a profile that comprises a mixture of two or all of convex curves, concave curves, and straight "curves" (i.e., straight line segments). In these profiles, the points at which two curves meet are likely to increase exposure to the electric field, and thus focus the formation of the conductive filament. However, a narrower point (such as a point at which two concave curves meet) may significantly increase that exposure, and thus may be more effective at focusing the formation of the conductive filament.

For the reasons discussed in <FIG>, therefore, patterning an electrode with a concave closed-curve profile in a ReRAM module can significantly increase the control of the location of a conductive filament formed in that module. Further, the increased current at the narrow points of such an electrode during the application of a formation voltage may permit lower formation voltages to be used, lowering the risk of damage to other structures in the memory module.

However, patterning an electrode with a concave closed-curve profile, such as the <NUM>-point example illustrated in <FIG>, may be difficult with typical process flows. Thus, some embodiments of the present disclosure illustrate a process flow for forming a memory cell with an electrode with a concave closed-loop profile.

<FIG>, for example, illustrate a process flow according to the present invention by which a <NUM>-point electrode (such as intermediate electrode <NUM>) could be formed in a ReRAM module. <FIG> depicts a side view of a first stage of forming ReRAM module <NUM> in which source electrode <NUM> is formed on semiconductor substrate <NUM> with interlayer dielectric <NUM>. Similarly, <FIG> depicts a top view of the first stage of forming ReRAM module <NUM>. The orientation of source electrode <NUM> is visible in <FIG>, as is inter-layer dielectric <NUM>. Further, the position from which ReRAM module <NUM> is viewed in <FIG> is also provided by perspective line <NUM>. In some embodiments, source electrode <NUM> may be part of a larger "bit line" electrode or a "word line" electrode. Suitable electrode materials for source electrode <NUM> include, but are not limited to, metals such as titanium (Ti) and/or tungsten (W). In another embodiment, source electrode <NUM> can include a metal nitride (for example, titanium nitride, tantalum nitride, titanium aluminum nitride, or tungsten nitride), or a metal-semiconductor compound (for example, a metal silicide), or a combination including at least one of the foregoing. The metal silicide can include nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, erbium silicide, or a combination including at least one of the foregoing.

<FIG> depict a side view and top view of a second stage of forming ReRAM module <NUM>. In this stage, an oxide layer <NUM> is deposited on top of source electrode <NUM> and interlayer dielectric <NUM>. As such, source electrode <NUM> and interlayer dielectric are temporarily covered by oxide layer <NUM>. For clarity, <FIG> illustrates the position of source electrode <NUM> under oxide layer <NUM> as a dotted line.

<FIG> depict a side view and top view of a third stage of forming ReRAM module <NUM>. In this stage, circular hardmask deposits <NUM>, <NUM>, <NUM>, and <NUM> are deposited upon oxide layer <NUM>. In some embodiments, hardmask deposits <NUM> - <NUM> may be a nitride hardmask. While hardmask deposits <NUM> - <NUM> are presented in <FIG> as circular, in some embodiments other shapes may be used. As illustrated, hardmask deposits <NUM> - <NUM> surround a location that is centered on source electrode <NUM>. As will be discussed in <FIG>, the shape of these hardmask deposits may impact the shape of seed pillars in and nitride accumulations on those seed pillars.

<FIG> depict a side view and a top view of a fourth stage of forming ReRAM module <NUM>. In this stage, most of oxide layer <NUM> has been removed, but the oxide material underneath hardmask deposits <NUM> - <NUM> remains. This oxide material forms four seed pillars that correspond to the four hardmask deposits in number, location, and shape. As illustrated, the four seed pillars are cylinders with a radius that matches the radius of hardmask deposits <NUM> - <NUM>. Only two (seed pillars <NUM> and <NUM>) are visible in <FIG>. All four seed pillars are covered by hardmask deposits <NUM> - <NUM> in <FIG>.

<FIG> depict a side view and a top view of a fifth stage of forming ReRAM module <NUM>. In this stage, a bottom nitride layer <NUM> has been applied to the top surfaces of interlayer dielectric <NUM> and source electrode <NUM>. Further, an accumulation of nitride on the sidewalls of the four seed pillars (including hardmask deposits <NUM> - <NUM>) has formed four nitride borders <NUM>, <NUM>, <NUM>, and <NUM>. Nitride borders <NUM> - <NUM>, as illustrated, take the form of nitride rings because the four seed pillars that formed nitride borders <NUM> - <NUM> have a circular cross-section profile. However, other shapes of nitride borders could be created by adjusting the shape of the seed pillars. For example, if a seed pillar had a square cross-section profile, the nitride border of that seed pillar would have an octagon shape. If a seed pillar had a closed curve profile with convex sides, a nitride border on that seed pillar may have a similar profile.

Nitride borders <NUM> - <NUM> have a radius that is large enough to cause nitride borders <NUM> - <NUM> to partially overlap. As a result, nitride borders <NUM> - <NUM> effectively form a single structure with gap <NUM> between them. As illustrated by <FIG>, gap <NUM> has a concave closed-curve profile with four points when viewed from above. Of note, it would be possible to vary the shape of gap <NUM> by varying the shape of the four seed pillars and thus the profile of one or more of nitride borders <NUM> - <NUM>. For example, if all four seed pillars had a same square shape but maintained their square position, all nitride borders <NUM> - <NUM> would have an octagon profile. The gap between nitride borders <NUM> - <NUM> would be formed by one diagonal side of each octagon, causing gap <NUM> to have a square profile.

<FIG> depict a side view and a top view of a sixth stage of forming ReRAM module <NUM>. In this stage, bottom nitride layer <NUM> has been removed. This may have been performed by, for example, a top-down reactive ion etching process. As a result, excess nitride from the top of nitride borders <NUM> - <NUM> has also been removed, exposing some of hardmask deposits <NUM> - <NUM>. Of note, removing bottom nitride layer <NUM> has exposed the portion of source electrode <NUM> that is beneath gap <NUM>. As a result, the portion of source electrode <NUM> that is visible beneath gap <NUM> has a four-point, concave, closed-curve profile that matches the profile of gap <NUM>.

<FIG> depict a side view and a top view of a seventh stage of forming ReRAM module <NUM>. In this stage, intermediate electrode <NUM> has been inserted into gap <NUM> between nitride borders <NUM> - <NUM>. The materials out of which intermediate electrode <NUM> may be formed may be the same as the materials out of which source electrode <NUM> may be formed (e.g., metals such as Ti, or W; metal nitrides such as titanium nitride, and tantalum nitride; or a metal-semiconductor compound such as a metal silicide).

In some embodiments, intermediate electrode <NUM> can include a stack of thin conductive layers and thick metal layer. The stack of conductive layer can include a stack structure of metal nitride (for example, titanium nitride, tantalum nitride, or tungsten nitride), an aluminum-containing alloy (for example, TiAl, TiAlC, TaAl, TaAlC), titanium, tantalum, or a combination including at least one of the foregoing. Specifically, intermediate electrode <NUM> can include a stack structure of titanium nitride and TiAlC. The metal layer can include titanium, tantalum, tungsten, molybdenum, platinum, hafnium, copper, aluminum, gold, nickel, iridium or a combination including at least one of the foregoing; specifically, tungsten. The electrode material for intermediate electrode <NUM> can be deposited using a process such as CVD, ALD, PVD, sputtering, evaporation, and electrochemical plating.

Intermediate electrode <NUM> is depicted in <FIG> as dotted line <NUM>, because intermediate electrode <NUM> is located behind nitride borders <NUM> and <NUM> from the perspective shown in <FIG>. In other words, intermediate electrode <NUM> is not directly visible from <FIG>. However, in <FIG>, the top of intermediate electrode <NUM> is visible. As a result of forming within gap <NUM>, intermediate electrode <NUM> is not only formed directly on top of electrode <NUM>, but also has a four-point, concave, closed-curve profile that matches the profile of gap <NUM>. Of note, intermediate electrode <NUM> is illustrated as being slightly shorter than nitride borders <NUM> - <NUM>. This is not strictly required; in some embodiments, intermediate electrode <NUM> could be as tall as nitride borders <NUM> - <NUM> or even as tall as hardmask deposits <NUM> - <NUM>. However, portions of intermediate electrode <NUM> that form outside of gap <NUM> may need to be removed with an etching process in order to prevent future shorts between intermediate electrode <NUM> and a sink electrode.

<FIG> depict a side view and a top view of an eighth stage of forming ReRAM module <NUM>. In this stage, nitride borders <NUM> - <NUM>, hardmask deposits <NUM> - <NUM>, and seed pillars <NUM>, <NUM>, and the two unnumbered seed pillars have all been etched off source electrode <NUM> and interlayer dielectric <NUM>. This has exposed intermediate electrode <NUM>, as illustrated in <FIG>.

<FIG> depict a side view and a top view of a ninth stage of forming ReRAM module <NUM>. In this stage, an insulating layer <NUM> (e.g., an oxide layer) has been formed over source electrode <NUM> and over the bottom portion of intermediate electrode <NUM>. In some embodiments, the insulating layer <NUM> is a high-k dielectric. In some embodiments, the insulating layer <NUM> is a transitional metal oxide. Examples of materials that can be suitable for ReRAM dielectric include NiOX, TayOX, TiOX, HfOX, TayOX, WOX, ZrOX, AlyOX, SrTiOX, or a combination comprising at least one of the foregoing. Conformal deposition processes include, but are not limited to, CVD, ALD, and PVD. According to an exemplary embodiment, the insulating layer <NUM> can have a thickness of <NUM> to <NUM> nanometers, specifically, <NUM> to <NUM> nanometers, more specifically, <NUM> to <NUM> nanometers. This insulating layer <NUM> may serve to insulate source electrode <NUM> from other conductive portions of ReRAM module <NUM>. In other words, current that is flowing through source electrode <NUM> may only flow to other portions of ReRAM module <NUM> through intermediate electrode <NUM>. In the interest of clarity, the portions of intermediate electrode <NUM> and source electrode <NUM> that are covered by insulating layer <NUM> have been illustrated here by dotted lines.

<FIG> depict a side view and a top view of a tenth stage of forming ReRAM module <NUM>. In this stage, memristor element <NUM> has been deposited over insulating layer <NUM> and intermediate electrode <NUM>. As such, intermediate electrode <NUM> is completely covered by memristor element <NUM> both from the top-view perspective of <FIG> and also from the side-view perspective of <FIG> (the origin of which is indicated by perspective line <NUM>). Because memristor element <NUM> is applied to intermediate electrode <NUM>, memristor element <NUM> shares the four-point concave closed-curve profile of intermediate electrode <NUM>, as is illustrated in <FIG>.

Memristor element <NUM> may be a metal oxide with insulative properties, such as hafnium oxide or tungsten trioxide. However, other resistive switching materials may also be used. For example, rather than a metal oxide, another metal chalcogen, such as a metal sulfide, may be used. These metal chalogens typically form switching materials of <NUM> nominal thickness. However, in some embodiments memristor element <NUM> could be formed of thinner switching materials, such as hexagonal boron nitride (h-BN), molybdenum disulfide (MoS<NUM>) or tungsten disulfide (WS<NUM>).

Once again in the interest of clarity, the portions of intermediate electrode <NUM> and source electrode <NUM> that are covered by insulating layer <NUM> or memristor element <NUM> have been illustrated here by dotted lines.

<FIG> depict a side view and a top view of an eleventh stage of forming ReRAM module <NUM>. Of note, the perspective from which the side view of <FIG> is illustrated is different than in previous figure views. As shown by perspective line <NUM> in <FIG> illustrates a side cross-section view of ReRAM module <NUM>. As such, even though intermediate electrode <NUM> is completely covered by memristor element <NUM>, it is visible in <FIG>. In the eleventh stage of forming ReRAM module <NUM>, sink electrode <NUM> is deposited on memristor element <NUM>. Suitable electrode materials for sink electrode <NUM> include, but are not limited to, metals such as titanium (Ti), titanium nitride (TiN) and/or tungsten (W). In another embodiment, sink electrode <NUM> can include a metal nitride (for example, titanium nitride, tantalum nitride, titanium aluminum nitride, or tungsten nitride), or a metal-semiconductor compound (for example, a metal silicide), or a combination including at least one of the foregoing. The metal silicide can include nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, erbium silicide, or a combination including at least one of the foregoing. Sink electrode <NUM> may be part of an eventual bit line electrode for several memory cells in ReRAM module <NUM>. This deposition places memristor element <NUM> electrically between intermediate electrode <NUM> and sink electrode <NUM>, enabling a potential conductive filament formation through memristor element <NUM>.

<FIG> depict a side view and a top view of twelfth stage of forming ReRAM module <NUM>. In the twelfth stage, intermediate electrode <NUM> and memristor element <NUM> have been recessed within sink electrode <NUM>. Further, an insulating nitride cap <NUM> has been formed in the resulting recess on top of intermediate electrode and memristor element <NUM>. This may help to prevent shorts from forming between intermediate electrode <NUM> and sink electrode <NUM> at the top of intermediate electrode. These shorts could occur, for example, if memristor element <NUM> does not cover the top of intermediate electrode <NUM> and if memristor element <NUM> were particularly thin near the top. Insulating nitride cap <NUM> may not be required for proper functioning of ReRAM module <NUM>, therefore, but may prevent potential failures.

In the twelfth stage of forming ReRAM module <NUM>, some of sink electrode <NUM> has been etched away, forming a line that is perpendicular to source electrode <NUM>. This may enable sink electrode <NUM> to serve as a bit line for ReRAM module <NUM> in combination with source electrode <NUM> serving as a word line for ReRAM module <NUM>. As illustrated, an insulating layer <NUM> (e.g., a dielectric layer) has been formed on ReRAM module <NUM> where portions of sink electrode <NUM> were removed.

After the twelfth stage of forming ReRAM module <NUM>, a formation voltage could be applied between source electrode <NUM> and sink electrode <NUM>. Through the application of this formation voltage, a conductive filament could be formed in one of the four narrow points of memristor element <NUM>. As such, the concave closed-loop profile of intermediate electrode <NUM> and memristor element <NUM> can be taken advantage of to control the location of the conductive filament, preventing potential filament failures. A discussion and presentation of such a conductive filament formation is provided by <FIG>.

As discussed in relation to <FIG>, some embodiments of the present disclosure can take the form of a process for forming a ReRAM module. Thus, for the purposes of understanding, <FIG> presents an example method <NUM> of forming a resistive RAM (ReRAM) module with an intermediate electrode with a concave closed-curve profile, in accordance with some embodiments of the present disclosure.

Method <NUM> begins in block <NUM>, in which seed pillars are applied to a module. In some embodiments, the seed pillars may be applied to a source electrode or an insulating layer into which that source electrode is embedded. Applying these seed pillars may, for example, take the form of applying a layer of oxide to the source electrode and insulating layer, applying hardmask deposits to the top of the oxide layer, and etching away the oxide that is not beneath the hardmask deposits. As discussed in relation to <FIG>, this may cause the seed pillars to take the form of pillars below the hardmask deposits that share the same cross-section profile as the hardmask deposits. As such, the hardmask deposits may be positioned such that a portion of a source electrode is located directly in the center between the hardmask deposits, resulting in the seed pillar surrounding that portion of the source electrode. In some embodiments, one or more of the hardmask deposits may have a circular profile, causing the corresponding seed pillars to share that circular profile (i.e., forming seed pillar cylinders).

Method <NUM> then proceeds to block <NUM> in which an accumulation of nitride is applied to the sidewalls of the seed pillars. This may result in a formation of nitride borders around the seed pillars that overlap, creating a gap between the nitride borders. In some embodiments, one or more nitride borders may be formed on seed pillars with a circular profile, causing nitride borders to take the form of nitride rings. Example nitride rings are depicted in <FIG> and <FIG>.

Method <NUM> then proceeds to block <NUM> in which a source electrode at the bottom of the gap between the seed pillars and nitride accumulation. Exposing the source electrode may include etching away a top layer of the nitride accumulation that formed on the top of the source electrode (and other portion of the ReRAM module). Exposing the source electrode after application of nitride is illustrated in <FIG>.

Method <NUM> then proceeds to block <NUM> in which an intermediate electrode is applied on top of the source electrode in a way that fills much of, or all of, the gap between the accumulation of nitride. This intermediate electrode may be composed, for example of titanium, titanium nitride, tungsten, or other conductive materials that are resistant to etching.

This may result in an intermediate electrode that has a top-down cross-section profile that is similar to or the same as the top-down cross-section profile of the gap between the nitride accumulation. For example, the intermediate electrode may have a concave closed-curve profile with several narrow points. Such a profile is illustrated in <FIG>, <FIG>, <FIG>.

Method <NUM> then proceeds to block <NUM>, in which the accumulated nitride and seed pillars (including the hardmask deposits) are removed from the ReRAM module. This may be performed, for example, with a reactive ion etching process that is not sufficient to remove the intermediate electrode.

Once the nitride and seed pillars are removed, method <NUM> proceeds to block <NUM>, in which a memristor element is applied to the intermediate electrode. This memristor element may be composed of hafnium oxide or other metal oxide with insulative properties. As a result of these insulative properties, current may not conduct through the memristor element when a conductive filament is formed through the memristor. Further, because this memristor element should have a concave, closed-curve profile that is similar to the profile of the intermediate electrode, it should also have at least one narrow point near a narrow point on the intermediate electrode. This may cause the conductive filament to be far more likely to form in the narrow point.

In some embodiments, block <NUM> may also include applying an insulating layer to the ReRAM module prior to applying the memristor element. This may prevent potential shorts between the source electrode (on which the intermediate electrode is formed) and the memristor element. In other words, the insulating layer may prevent any current from the source electrode from flowing to the memristor element except through the intermediate electrode.

Once the memristor element is applied to the intermediate electrode in block <NUM>, method <NUM> proceeds to block <NUM> in which a sink electrode is applied to the memristor element. This causes memristor element to be electrically between the intermediate electrode and the sink electrode. Because current from the source electrode should flow to the memristor element through the intermediate electrode, this also should result in a voltage applied across the source electrode and the sink electrode to create a current through the memristor element. If this current is sufficiently large (i.e., if the voltage across the source electrode and the sink electrode is sufficiently high), a conductive filament may then form across the memristor element.

In some embodiments, block <NUM> may include recessing the memristor element and intermediate electrode. This would cause the sink electrode to be slightly taller (with respect to the bottom of the ReRAM module) than both the memristor element and intermediate electrode. This could also enable the deposition of nitride on top of the memristor element and intermediate electrode. This nitride cap may prevent unintentional shorts between the top of the intermediate electrode and the top of the sink electrode. In other words, it may force any current between the intermediate electrode and the sink electrode to flow through a conductive filament in the memristor element.

In the embodiments disclosed in <FIG> and <FIG>, intermediate electrodes with a four-point concave closed-curve profile are illustrated. However, some embodiments of the present disclosure may utilize intermediate electrodes with concave closed-curve profiles with other numbers of narrow points. As described above, the increased current at the narrow points at which the intermediate electrode, memristor element, and sink electrode interface with each other cause a conductive filament to be more likely to form at those narrow points. However, the number of narrow points is not vital to the invention.

For example, <FIG> depicts a top view of an example set of nitride rings <NUM> - <NUM> that could be used in accordance with some embodiments of the present disclosure to form an intermediate electrode with a concave closed-curve profile with three points. In <FIG>, a set of seed pillars <NUM>, <NUM>, and <NUM> surround a section of a source electrode <NUM>. Nitride rings <NUM> - <NUM> are applied to the sidewalls of those seed pillars <NUM> - <NUM> such that nitride rings <NUM> - <NUM> partially overlap, creating a gap <NUM> in the center of seed pillars <NUM> - <NUM> and nitride rings <NUM> - <NUM>. Because three seed pillars are used herein, gap <NUM> has a three-point concave closed-curve profile. If an intermediate electrode were deposited into gap <NUM>, then, it could be formed with three narrow points.

As another example, <FIG> depicts a top view of an example set of nitride rings <NUM> - <NUM> that could be used in accordance with some embodiments of the present disclosure to form an intermediate electrode with a concave closed-curve profile with six points. The partial overlap of nitride rings <NUM> - <NUM> creates a gap <NUM> above source electrode <NUM>. By filling that gap with an intermediate electrode, an electrode with a six-point, concave, closed-curve profile could be formed.

Of note, <FIG>, <FIG> illustrate that embodiments of the present disclosure can include nitride borders of different thicknesses and different amounts of overlap. Further, the positions of the seed pillars in each of <FIG>, <FIG> are different, illustrating that embodiments of the present disclosure can include different positions of seed pillars and nitride borders. These properties could be altered in other embodiments to create gaps between the nitride borders of different shapes and sizes, which may be used to create intermediate electrodes of different shapes and sizes. Further, as discussed above, by altering the shapes of hardmask deposits that are used to create seed pillars, the shapes of seed pillars on which the nitride borders accumulate can be customized. This can in turn affect the accumulation of nitride on the seed pillars, which affects the shape of those nitride borders. This may be used to customize the shape of an intermediate electrode formed in a gap between those nitride borders.

<FIG> depicts the representative major components of an example Computer System <NUM> that may be used in accordance with embodiments of the present disclosure. The particular components depicted are presented for the purpose of example only and are not necessarily the only such variations. The Computer System <NUM> may include a Processor <NUM>, Memory <NUM>, an Input/Output Interface (also referred to herein as I/O or I/O Interface) <NUM>, and a Main Bus <NUM>. The Main Bus <NUM> may provide communication pathways for the other components of the Computer System <NUM>. In some embodiments, the Main Bus <NUM> may connect to other components such as a specialized digital signal processor (not depicted).

The Processor <NUM> of the Computer System <NUM> may include one or more CPUs <NUM>. The Processor <NUM> may additionally include one or more memory buffers or caches (not depicted) that provide temporary storage of instructions and data for the CPU <NUM>. The CPU <NUM> may perform instructions on input provided from the caches or from the Memory <NUM> and output the result to caches or the Memory <NUM>. The CPU <NUM> may include one or more circuits configured to perform one or methods consistent with embodiments of the present disclosure. In some embodiments, the Computer System <NUM> may contain multiple Processors <NUM> typical of a relatively large system. In other embodiments, however, the Computer System <NUM> may contain a single processor with a singular CPU <NUM>.

The Memory <NUM> of the Computer System <NUM> may include a Memory Controller <NUM> and one or more memory modules for temporarily or permanently storing data (not depicted). In some embodiments, the Memory <NUM> may include a random-access semiconductor memory, storage device, or storage medium (either volatile or non-volatile) for storing data and programs. The Memory Controller <NUM> may communicate with the Processor <NUM>, facilitating storage and retrieval of information in the memory modules. The Memory Controller <NUM> may communicate with the I/O Interface <NUM>, facilitating storage and retrieval of input or output in the memory modules. In some embodiments, the memory modules may be dual in-line memory modules.

The I/O Interface <NUM> may include an I/O Bus <NUM>, a Terminal Interface <NUM>, a Storage Interface <NUM>, an I/O Device Interface <NUM>, and a Network Interface <NUM>. The I/O Interface <NUM> may connect the Main Bus <NUM> to the I/O Bus <NUM>. The I/O Interface <NUM> may direct instructions and data from the Processor <NUM> and Memory <NUM> to the various interfaces of the I/O Bus <NUM>. The I/O Interface <NUM> may also direct instructions and data from the various interfaces of the I/O Bus <NUM> to the Processor <NUM> and Memory <NUM>. The various interfaces may include the Terminal Interface <NUM>, the Storage Interface <NUM>, the I/O Device Interface <NUM>, and the Network Interface <NUM>. In some embodiments, the various interfaces may include a subset of the aforementioned interfaces (e.g., an embedded computer system in an industrial application may not include the Terminal Interface <NUM> and the Storage Interface <NUM>).

Logic modules throughout the Computer System <NUM> - including but not limited to the Memory <NUM>, the Processor <NUM>, and the I/O Interface <NUM> - may communicate failures and changes to one or more components to a hypervisor or operating system (not depicted). The hypervisor or the operating system may allocate the various resources available in the Computer System <NUM> and track the location of data in Memory <NUM> and of processes assigned to various CPUs <NUM>. In embodiments that combine or rearrange elements, aspects of the logic modules' capabilities may be combined or redistributed. These variations would be apparent to one skilled in the art.

Claim 1:
A method (<NUM>) of forming a ReRAM module (<NUM>), the method comprising:
(<NUM>) applying a set of seed pillars (<NUM>, <NUM>) to a surface of a layer of the ReRAM module (<NUM>), wherein the seed pillars (<NUM>, <NUM>) are perpendicular to the surface and wherein the layer comprises a source electrode (<NUM>) embedded in an inter-layer dielectric (<NUM>);
(<NUM>) depositing nitride on the sidewalls of the seed pillars (<NUM>, <NUM>), such that nitride accumulation creates a set of nitride borders (<NUM>, <NUM>, <NUM>, <NUM>) that surround the seed pillars, wherein each nitride border in the set partially overlaps at least two other nitride borders such that a gap (<NUM>) is formed in the center of the nitride borders;
(<NUM>) depositing an intermediate electrode (<NUM>) on top of the source electrode and in the gap (<NUM>);
(<NUM>) removing the nitride and the seed pillars (<NUM>, <NUM>);
(<NUM>) depositing a memristor element (<NUM>) on the intermediate electrode (<NUM>); and
(<NUM>) depositing a sink electrode (<NUM>) on the memristor element (<NUM>).