Patent Description:
One or more embodiments may be applied to manufacturing leadframes for semiconductor devices such as integrated circuits (ICs), for instance.

Various technologies are currently available for manufacturing leadframes/substrates for various types of semiconductor devices such as QFN (Quad Flat No-lead), LGA (Land Grid Array), BGA (Ball Grid Array) semiconductor devices.

So-called "coreless" leadframe technology facilitates using a leadframe as it is, that is without tape apport.

Solutions currently referred to as MIS (Molded Interconnect Solutions) are exemplary of devices to which coreless leadframe technology may apply.

Essentially, MIS is a leadframe manufacturing technology similar to BGA laminate technology using a molding compound as the core.

Such a technology facilitates achieving fine inner lead tip pitch (<NUM>/<NUM> micron, for instance) which is highly desirable for flip-chip applications.

It is noted that such arrangements may exhibit relatively low yield at manufacturing with costs of about <NUM>-<NUM>% in excess of "standard" taped leadframes.

Additionally, certain conventional solutions may exhibit drawbacks related, for instance, to possible warpage (in the case of a metal carrier and a film mold, for instance).

In the case of MIS technology, notable leadframe warpage may be observed after assembly steps involving a thermal budget such as, for instance:.

Document <CIT> discloses an integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.

An object of one or more embodiments is to overcome the drawbacks discussed in the foregoing.

According to one or more embodiments, such drawbacks can be overcome by resorting to a method having the features set forth in claim <NUM> that follows.

The claims are an integral part of the technical disclosure of embodiments as provided herein.

One or more embodiments may offer one or more of the following advantages:.

One or more embodiments may use laser direct structuring (LDS) technology in order to create vias and lines with the capability of replacing a metallic frame by metallization of vias and lines.

It will be appreciated that, for the sake of clarity and ease of representation, the various figures may not be drawn to a same scale.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

The designation "leadframe" (or "lead frame") is currently used (see for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame which provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip to other electrical components or contacts.

Laser Direct Structuring (LDS) is a laser-based machining technique now widely used in various sectors of the industrial and consumer electronics markets, for instance for high-performance antenna integration, where an antenna design can be directly formed onto a molded plastic part.

In an exemplary process, molded parts can be produced with commercially available resins which include additives suitable for the LDS process; a broad range of resins such as polymer resins like PC, PC/ABS, ABS, LCP are currently available for that purpose.

In LDS, a laser beam can be used to transfer a desired electrically-conductive pattern on the plastic molding, which is then subjected to metallization (for instance via electroless plating with copper or other metals) to finalize the desired conductive pattern.

One or more embodiments as exemplified herein involve the recognition that LDS facilitates providing electrically-conductive formations such as vias and lines in a molding compound, without further manufacturing steps and with a high flexibility in the shapes which can be obtained.

One or more embodiments can be applied to various types of semiconductor devices such as (by way of nonlimiting examples) those semiconductor devices currently referred to as a QFN or QFN-mr, these being acronyms for Quad Flat Pack No-lead and Multirow Quad Flat Pack No-lead.

Such devices may include leadframes with so-called routed leads, namely electrically-conductive formations (leads) which from an outline location extend inwardly in the direction of a semiconductor chip or die.

One or more embodiments may facilitate achieving a reduced (fine) lead tip pitch at the inner (proximal) ends of the leads, that is the ends of the leads towards the semiconductor chip.

<FIG> are exemplary of possible acts in embodiments which may facilitate producing a leadframe (for instance for any one of the various types of semiconductor devices discussed in the foregoing) using LDS technology.

<FIG> is exemplary of forming (in a manner known per se to those of skill in the art) a substrate or layer <NUM> (a laminate core, for instance) of LDS material.

Any known LDS material (such as, for instance, a polymer resin like PC, PC/ABS, ABS, LCP including additives suitable for the LDS process) may be used advantageously in embodiments.

<FIG> is exemplary of an act of structuring the substrate <NUM> of <FIG> at the "bottom" or "back" surface thereof, designated 10a.

Such structuring may involve forming by LDS processing (that is, laser beam machining as schematically indicated at L) a first pattern of electrically-conductive formations <NUM>, <NUM>.

<FIG> is exemplary of an act of structuring the substrate <NUM> of <FIG> at the "top" or "front" surface thereof, designated 10b.

Such structuring (possibly, but not necessarily, performed after overturning the substrate <NUM>) may involve forming, again by LDS processing (that is, laser beam machining L), a second pattern of electrically-conductive formations <NUM>, <NUM>.

Those of skill in the art will appreciate that both the first pattern and the second pattern of electrically-conductive formations <NUM>, <NUM> and <NUM>, <NUM> can be provided according to any of a virtually boundless variety of possible patterns as desired, by also taking advantage of the intrinsic flexibility LDS laser beam processing.

For instance, <FIG> and <FIG> are exemplary of the possibility of performing the acts of <FIG> on strip-like material, virtually of indefinite length, to provide (simultaneously) a plurality of lead frames with longitudinal electrically-conductive formations <NUM>, <NUM> extending along the sides of the strip-like material.

<FIG> is exemplary of laser processing (drilling by laser beam L) the substrate <NUM> having the front and back surfaces 10a, 10b structured as discussed previously to open vias <NUM> extending at desired locations between the electrically-conductive formations of the two patterns <NUM>, <NUM> over the two surfaces 10a, 10b.

<FIG> is exemplary of similar processing (e.g. laser drilling) possibly applied to the structure of <FIG> in those embodiments where, as exemplified in <FIG> and <FIG>, the acts of <FIG> are performed on strip-like material, to provide indexing holes <NUM> (essentially openings at a given pitch) in the longitudinal electrically-conductive formations <NUM>, <NUM> or "rails" extending along the sides of the strip-like material.

<FIG> is exemplary of the possibility of growing conductive material (metal such as copper - Cu, for instance) onto the structured paths provided via laser processing of the LDS material as exemplified in <FIG>.

Electroless/electrolytic growth as exemplified by EE in <FIG> may be used for that purpose, that is in order to improve (via growth of copper, for instance) the conductivity of the traces/holes formed in the LDS material by laser processing.

Electroless processing (optionally preceding electrolytic processing) may facilitate a thicker metal growth.

Also, in those embodiments where a high (Cu, for instance) metal growth is not a desired feature, electroless alone (that is without electrolytic plating) can be used.

It is noted that the conductive formations (traces, for instance) formed with laser processing of LDS material may have a thickness, and thus a conductivity, insufficient for certain applications, such as power devices, for instance: indeed few microns of LDS material may be ablated in the laser activation process (and possibly more in the case of drilling), with the treated material possibly having activated particles (chromium, for instance) at its surface.

Also, while exemplified in relief in the figures for simplicity and ease of understanding, the laser-treated surface portions of the LDS material may not be in relief, but rather recessed.

Those of skill in the art will thus appreciate that passing from an "intermediate" structure obtained (solely) via laser activation to a resulting final structure may involve such a step as exemplified in <FIG>, that is forming e.g. electroplated conductive formations.

<FIG> is exemplary of an (optional) plating act PT which may be applied with otherwise conventional means in order to provide plated conductive formations over the leads at the bottom side 10a and/or over the lead tips at the top side 10b: see, for instance <NUM>' (material complying with surface mount soldering, for instance) and <NUM> (these may be pads or bumps for wire/ribbon bonding or the like) in <FIG>.

Figures from 1A to <NUM> are thus exemplary of a possible manufacturing sequence of an exemplary leadframe including acts of: strip molding (<FIG>), bottom laser structuring (<FIG>), top laser structuring (<FIG>), vias generation connecting the two top/bottom layers (<FIG>), opening of indexing holes (or any other feature as desired) on top/bottom rails (<FIG>), forming conductive material onto the traces, holes, and so on obtained by laser structuring (<FIG>), top/bottom layer metallization (<FIG>).

For instance, in an act as exemplified in <FIG>, all traces, holes obtained by laser structuring (see <FIG>, for example) may be electroless plated - for less than <NUM> micron thickness, for instance - or electroplated - up to <NUM> microns thickness - in case of high current devices, for instance.

<FIG> and <FIG> are exemplary of a possible result of acts as exemplified in <FIG> in a plan view from the top or front side 10b (<FIG>) and from the bottom or back surface 10a (<FIG>).

As discussed, <FIG> and <FIG> are exemplary of the possibility of performing the acts of <FIG> on strip-like material, virtually of indefinite length, to provide a plurality of lead frames to be finally "singulated" (before or after die attachment).

Such an an act of singulation may be facilitated by using the indexing holes <NUM> in the longitudinal electrically-conductive formations <NUM>, <NUM> or "rails".

Indeed, such leadframe rails <NUM>, <NUM> may contain features (such as holes <NUM>) which facilitate leadframe indexing and/or unit location into assembly equipment. They can also contain identification codes (2D Codes) and "fiducials" (such as crosses, L shapes,. ) which facilitates properly locating the path of the sawing blade during package singulation.

<FIG> are exemplary of the possibility of applying processing as discussed in connection with the previous figures both to "mono-thickness" substrates <NUM> and to "dual-thickness" or "multiple-thickness" substrates, for instance having a mesa-like cross sectional profile with a central portion upstanding in comparison with the longitudinal sides of the strip-like structure exemplified in <FIG> and <FIG>. One or more embodiments as exemplified herein may thus apply to device structure based on a copper dual layer or multiple layer.

<FIG> is exemplary of a leadframe adapted to be produced as exemplified herein.

A single leadframe is exemplified for simplicity showing the presence of a (central) die-mounting area at the top or front surface 10b where a semiconductor die or chip can be attached (by any technique known for that purpose to those of skill in the art as discussed by way of example in the introductory portion of the description) as indicated in dashed lines at C.

As exemplified in <FIG>, the pattern of electrically-conductive formations <NUM> may provide an array of routing leads suited to provide electrical coupling of the semiconductor die or chip with contact pads accessible from outside a device package. A possible outline of such a package (which may be provided by any technique known for that purpose to those of skill in the art, for instance by molding an epoxy molding compound) is indicated by P in <FIG>.

Electrical coupling of the semiconductor die or chip may be via conventional techniques such as wire bonding, stud bumps or the like.

Whatever the option(s) adopted for that purpose, such coupling may take advantage of the provision of contact formations as indicated by <NUM> in <FIG>.

<FIG> also exemplifies the possible presence of contact lands or bumps as indicated by <NUM>' which do not come down to any electrically-conductive formations <NUM> at the top or front surface 10b but rather correspond to vias <NUM> formed through the substrate <NUM> coming down to electrically-conductive formations <NUM> at the bottom or back surface 10a.

One or more embodiments as exemplified herein thus adopt laser direct structuring (LDS) processing in order to create electrically-conductive formations such as vias and lines of various types with metallization of vias and lines adapted to replace a metallic frame.

<FIG> is exemplary of a "real-world" example providing a leadframe including an array of leads extending between a die-mounting region for mounting a semiconductor chip or die C and the periphery of a substrate <NUM> of an LDS material. As exemplified in <FIG>, one or more of these leads may have a generally flared shape with a narrow "proximal" tip facing the die mounting area C and a width (and thus areal cross-sectional area) gradually increasing in a "distal" direction away from the die mounting area towards for periphery of the substrate <NUM>.

As noted, final singulation of a lead frame (as exemplified by arrows S in <FIG>) may take place with the die or chip C already attached thereon, possibly with die or chip already electrically coupled and packaged as discussed previously.

One or more embodiments facilitate providing a device structure with or without plated conductive formations (die pads, for instance) on both sides of the leadframe.

One or more embodiments may adopt LDS structuring in order to create electrically-conductive formations such as vias and lines with metallization of vias and lines adapted to replace a metallic frame such as conventional leadframes.

A method of manufacturing leadframes for semiconductor devices as exemplified herein comprises:.

A method as exemplified herein may comprise applying laser beam processing to said substrate to provide electrically-conductive vias coupled to at least one of the electrically-conductive formations in said first pattern of electrically-conductive formations and at least one of the electrically-conductive formations in said second pattern of electrically-conductive formations (see, for instance <NUM> in <FIG>).

A method as exemplified herein may comprise forming (see EE in <FIG>, for instance) electrically-conductive material onto said first pattern of electrically-conductive formations, said second pattern of electrically-conductive formations and said electrically-conductive vias provided by applying laser beam processing to said substrate.

In a method as exemplified herein, said forming electrically-conductive material may comprise electroless and/or electrolytic growth (for instance, electroless plus electrolytic) of electrically-conductive material, such as metal like copper.

A method as exemplified herein may comprise forming plated contact formations (see, for instance P; <NUM>', <NUM> in <FIG>) over said first pattern of electrically-conductive formations and/or said second pattern of electrically-conductive formations (optionally, as exemplified in <FIG>, this may occur "on top" of, that is onto, the electrically-conductive material formed as exemplified in <FIG>).

A method as exemplified herein may comprise:.

A method as exemplified herein may comprise providing, optionally by laser beam drilling of said strip-like laminar substrate, indexing apertures (for instance, <NUM>) sidewise of said strip-like laminar substrate, said indexing apertures providing reference markers in applying singulation to said strip-like laminar substrate.

Claim 1:
A method of manufacturing leadframes for semiconductor devices, the method comprising:
- providing a laminar substrate (<NUM>) of laser direct structuring material, the laminar substrate comprising first (10a) and second (10b) opposed surfaces,
- applying laser beam processing (L) to said substrate (<NUM>) to provide a first pattern of electrically-conductive formations (<NUM>, <NUM>) at the first surface (10a) of said substrate (<NUM>), a second pattern of electrically-conductive formations (<NUM>, <NUM>) at the second surface (10b) of said substrate (<NUM>), and electrically-conductive vias (<NUM>) through said substrate (<NUM>) between the first surface (10a) of said substrate (<NUM>) and the second surface (10b) of said substrate (<NUM>), the electrically-conductive vias (<NUM>) coupled to at least one (<NUM>, <NUM>) of the electrically-conductive formations in said first pattern of electrically-conductive formations and said second pattern of electrically-conductive formations.