Patent Description:
The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations.

<CIT> discloses a memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

<CIT> discloses high precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial networks.

Non-volatile memory devices are well known in the art. See for example <CIT>, which discloses a four-gate memory cell configuration, and which is incorporated herein by reference for all purposes. Specifically, <FIG> of the present application illustrates a split gate memory cell <NUM> with spaced apart source and drain regions <NUM>/<NUM> formed in a silicon semiconductor substrate <NUM>. The source region <NUM> can be referred to as a source line SL (because it commonly is connected to other source regions for other memory cells in the same row or column), and the drain region <NUM> is commonly connected to a bit line by a bit line contact <NUM>. A channel region <NUM> of the substrate is defined between the source/drain regions <NUM>/<NUM>. A floating gate <NUM> is disposed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM> (and partially vertically over and insulated from the source region <NUM>). A control gate <NUM> is disposed vertically over and insulated from the floating gate <NUM>. A select gate <NUM> is disposed vertically over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>. An erase gate <NUM> is disposed vertically over and insulated from the source region <NUM> and is laterally adjacent to the floating gate <NUM>. A plurality of such memory cells can be arranged in rows and columns to form a memory cell array.

Various combinations of voltages are applied to the control gate <NUM>, select gate <NUM>, erase gate <NUM> and/or source and drain regions <NUM>/<NUM>, to program the split gate memory cell <NUM> (i.e., inject electrons onto the floating gate), to erase the split gate memory cell <NUM> (i.e., remove electrons from the floating gate), and to read the split gate memory cell <NUM> (i.e., measure or detect the conductivity of the channel region <NUM> to determine the programming state of the floating gate <NUM>).

Split gate memory cell <NUM> can be operated in a digital manner, where the split gate memory cell <NUM> is set to one of only two possible states: a programmed state and an erased state. The split gate memory cell <NUM> is erased by placing a high positive voltage on the erase gate <NUM>, and optionally a negative voltage on the control gate <NUM>, to induce tunneling of electrons from the floating gate <NUM> to the erase gate <NUM> (leaving the floating gate <NUM> in a more positively charged state - the erased state). Split gate memory cell <NUM> can be programmed by placing positive voltages on the control gate <NUM>, erase gate <NUM>, select gate <NUM> and source region <NUM>, and a current on drain region <NUM>. Electrons will then flow along the channel region <NUM> from the drain region <NUM> toward the source region <NUM>, with electrons becoming accelerated and heated whereby some of them are injected onto the floating gate <NUM> by hot-electron injection (leaving the floating gate <NUM> in a more negatively charged state - the programmed state). Split gate memory cell <NUM> can be read by placing positive voltages on the select gate <NUM> (turning on the portion of channel region <NUM> under the select gate <NUM>) and drain region <NUM> (and optionally on the erase gate <NUM> and/or the control gate <NUM>), and sensing current flow through the channel region <NUM>. If the floating gate <NUM> is positively charged (i.e. split gate memory cell <NUM> is erased), the split gate memory cell <NUM> will turn on, and electrical current will flow from drain region <NUM> to source region <NUM> (i.e. the split gate memory cell <NUM> is sensed to be in its erased "<NUM>" state based on sensed current flow). If the floating gate <NUM> is negatively charged (i.e. split gate memory cell <NUM> is programmed), the portion of channel region <NUM> under the floating gate <NUM> is turned off, thereby preventing appreciable current flow (i.e., the split gate memory cell <NUM> is sensed to be in its programmed "<NUM>" state based on no, or minimal, current flow).

Table <NUM> provides non-limiting examples of erase, program and read voltages for typical digital operation of the split gate memory cell, where Vcc is power supply voltage or another positive voltage such as <NUM> V.

Split gate memory cell <NUM> can alternately be operated in an analog manner where the memory state (i.e. the amount of charge, such as the number of electrons, on the floating gate <NUM>) of the split gate memory cell <NUM> can be tuned to anywhere from a fully erased state (minimum number of electrons on the floating gate <NUM>) to a fully programmed state (maximum number of electrons on the floating gate <NUM>), or just to a portion of this range by varying one or several programming voltages, for example, one can use various control gate <NUM> (CG) programming voltages for analog programming. This means the split gate memory cell <NUM> storage is analog, which allows for very precise and individual tuning of each split gate memory cell <NUM> in the array of split gate memory cells <NUM>. Alternatively, the split gate memory cell <NUM> could be operated as an MLC (multilevel cell) where it is configured to be programmed to one of many discrete values (such as <NUM> or <NUM> different values). In the case of analog or MLC programming, the programming voltages are applied for a limited time, or as a series of pulses, until the desired programming state is achieved. In the case of multiple programming pulses, intervening read operations between programming pulses can be used to determine if the desired programming state has been achieved (in which case programming ceases) or has not been achieved (in which case programming continues).

Split gate memory cell <NUM> operated in an analog manner or as an MLC may be more sensitive to noise and read current instabilities which can adversely affect the accuracy of the split gate memory cell <NUM>. One source of read current instability in analog non-volatile memory devices is the capture and emission of electrons by oxide traps located at the interface and near-interface between the gate oxide and memory cell channel region. The gate oxide is the insulation layer that separates the floating gate <NUM> from the channel region <NUM> of substrate <NUM>. When an electron is captured on an interface trap, it reduces the channel conductivity during a read operation, and thus increases the threshold voltage Vt of the split gate memory cell <NUM> (i.e., the minimum voltage on the control gate <NUM> needed to turn on the channel region <NUM> of the split gate memory cell <NUM> to produce a predetermined target current, <NUM>µA being an example). When the control gate voltage is at or above the threshold voltage Vt, a conducting path is created between the source region <NUM> and the drain region <NUM>, and a current of at least the predetermined target current flows. When the control gate voltage is below the threshold voltage Vt, a conducting path is not created, and any current between the source region <NUM> and the drain region <NUM> is considered sub-threshold or leakage current. An electron captured on an interface trap can be emitted from the interface trap, which decreases threshold voltage Vt of the memory cell, and thus increases the channel conductivity during a read operation. These single-electron events of electron capture and emission by interface traps appear as read current noise and are referred to as random telegraph noise (RTN). In general, RTN produced by a single interface trap is characterized by two states: a lower Vt state (and higher read current state) when an electron is emitted from the interface trap and a higher Vt state (and lower read current state) when an electron is captured by the interface trap. As described above, the instability of the split gate memory cell <NUM> during read can be characterized either by the threshold voltage Vt, i.e. the control gate voltage corresponding to the predetermined target current or by memory cell current under given read voltage conditions. The present examples are particularly described in relation to memory cell read instability as threshold voltage Vt , however the use of memory cell current under given read voltages are specifically contemplated.

There is a small but not insignificant percentage of memory cells, such as split gate memory cells <NUM>, within an array of memory cells, that exhibit intolerable amounts of RTN for those applications where very high read accuracy is required. Memory cells that are prone to RTN increase the risk that some analog data stored in the array of memory cells will be corrupted at least to some extent, because electron emission from the interface trap by such memory cells after programing will undesirably decrease the threshold voltage Vt of the memory cell (and therefore undesirably increase channel conductivity during a read operation), thus providing an inaccurate read of the desired original memory cell program state. Similarly, electron capture by such memory cells after programing will undesirably increase the threshold voltage Vt of the memory cell (and therefore undesirably decrease channel conductivity during a read operation), thus providing an inaccurate read of the desired original memory cell program state. Therefore, there is a need to address RTN in analog and MLC non-volatile memory devices to compensate for post-program RTN.

The aforementioned problems and needs are addressed by a memory device according to independent claim <NUM> and a method of programing a memory device according to independent claim <NUM>. Preferred aspects of the invention are defined in dependent claims <NUM>-<NUM> and <NUM>-<NUM>.

Only examples or embodiments comprising all the features of at least one of the independent claims <NUM>, <NUM> fall under the scope of protection of the present invention.

The present example(s) technique for reducing the effects of RTN for arrays of non-volatile memory cells, particularly those that include split gate memory cells <NUM> of the type of <FIG>, although the techniques are not limited to such memory cells. Specifically, the non-volatile memory cells are logically divided into memory cell groups, each memory cell group comprising two or more memory cells, where each memory cell group is treated as a single cell for storing user data. Within each memory cell group, only the non-volatile memory cell exhibiting the lowest RTN is used to store user data, while the rest of the non-volatile memory cells of the memory cell group are deeply programmed to effectively screen them out, i.e. so that they do not contribute to the output of the memory cell group during subsequent read operations.

The memory cell grouping, screening and programming are implemented as part of the configuration of the control circuitry <NUM>, which controls the various device elements of the memory array, which can be better understood from the architecture of an example memory device as illustrated in <FIG>. The memory device includes an array <NUM> of the split gate memory cells <NUM>, which can be segregated into two separate planes (Plane A 52a and Plane B 52b). The split gate memory cells <NUM> can be of the type shown in <FIG>, arranged in a plurality of rows and columns in the semiconductor substrate <NUM>, and thus formed on a single chip. Adjacent to the array <NUM> of split gate memory cells <NUM>, and included in the memory device, are an address decoder (e.g. XDEC <NUM>), source line drivers (e.g. SLDRV <NUM>), a column decoder (e.g. YMUX <NUM>), a high voltage row decoder (e.g. HVDEC <NUM>) and a bit line controller (e.g. BLINHCTL <NUM>), which are used to decode addresses and supply the various voltages to the gates and regions of the split gate memory cells <NUM> during read, program, and erase operations for selected split gate memory cells <NUM> of the array <NUM>. Column decoder <NUM> includes a sense amplifier containing circuitry for measuring the currents on the bit lines during a read operation. Control circuitry <NUM> is configured to control the various device elements to implement each operation (program, erase, read) on selected split gate memory cells <NUM> of the array <NUM> as described herein. Charge pump CHRGPMP <NUM> provides the various voltages used to read, program and erase the selected split gate memory cells <NUM> of the array <NUM> under the control of control circuitry <NUM>. The control circuitry <NUM> is configured to operate the memory device to program, erase and read the selected split gate memory cells <NUM> of the array <NUM>. As part of these operations, the control circuitry <NUM> can be provided with access to the incoming user data which is data to be programmed to the memory cells, along with program, erase and read commands provided on the same or different lines. Data read from the array <NUM>, i.e. from selected split gate memory cells <NUM> of the array <NUM>, is provided as outgoing data. The control circuitry <NUM> includes, or is provided access to, a separate memory such as random access memory (RAM) <NUM> for storing voltage values as described further below.

Control circuitry <NUM> implements the memory cell grouping, screening and programming described herein. Thus, control circuitry <NUM> may be loaded with software, i.e. non-transitory electronically readable instructions, or firmware, to perform the methods described below in relation to <FIG>, thereby being configured. Control circuity <NUM> may be implemented by a microcontroller, dedicated circuitry, a processor, or a combination thereof.

In accordance with the examples herein, the split gate memory cells <NUM> of the array <NUM> are logically divided into memory cell groups <NUM> of N cells in each memory cell group <NUM>, where N is an integer greater than or equal to two. <FIG> illustrates four memory cell groups <NUM> each having two memory cells <NUM> (i.e., N=<NUM>), however the number of memory cell groups <NUM> and the value of N can be different.

Before describing the grouping and screening of memory cells, the basics of memory cell programming is described first.

Memory cell programming involves programming the memory cell to a particular programming state using programming voltage pulses, with intervening read operations to measure a threshold voltage parameter (i.e., a minimum voltage applied to the split gate memory cell <NUM> to achieve a predetermined level of source/drain current, referred to as a target current Itarget) for the split gate memory cell <NUM>. The threshold voltage parameter is a control gate threshold voltage Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate <NUM>. Specifically, the control gate threshold voltage Vtcg is the voltage placed on the control gate <NUM> that results in the channel region <NUM> being a conducting path, and therefore results in a read current through the channel of the predetermined level of source/drain current, i.e., the target current Itarget (e.g., <NUM>µA) to consider the split gate memory cell <NUM> turned on when the read potentials of a read operation are applied to the select gate <NUM> and drain region <NUM>. The control gate threshold voltage Vtcg varies as a function of programming state of the split gate memory cell <NUM>, but it is desired that once the split gate memory cell <NUM> is programmed to a particular programming state, any variation of control gate threshold voltage Vtcg over time be below a predetermined amount.

Memory cell programming is illustrated as Steps <NUM>-<NUM> in <FIG>, which is implemented to program a split gate memory cell <NUM> to a specific desired programming state so that it has a target control gate threshold voltage Vtcgtarget that is associated with that specific desired programming state. The technique begins in Step <NUM> with control circuitry <NUM> programming a selected split gate memory cell <NUM> of array <NUM>. As described above, the analog programming operation involves applying programming voltages to the selected split gate memory cell <NUM> for a limited time (i.e., in at least one pulse), which results in injecting electrons onto the floating gate <NUM>. In the programming of Step <NUM>, the voltage Vcg, provided from SLDRV <NUM>, applied to the control gate <NUM> has a control gate program voltage Vcgprogram. In Step <NUM>, a read operation is performed by control circuitry <NUM> which involves applying read voltages from SLDRV <NUM> to the selected split gate memory cell <NUM>, according to Table <NUM>, and measuring, with column decoder <NUM> and bit line controller <NUM>, the current flowing through the channel region <NUM> of the selected split gate memory cell <NUM>, Iread. In this read operation, the voltage Vcg applied to the control gate <NUM> is the target control gate threshold voltage Vtcgtarget. In Step <NUM>, it is determined from the read operation of Step <NUM> whether or not the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcgtarget (i.e., whether the read current Iread measured by column decoder <NUM> and bit line controller <NUM> is less than or equal to the target current Itarget, where Iread equal to the target current Itarget is indicative of the control gate threshold voltage Vtcg of the memory cell reaching the target control gate threshold voltage Vtcgtarget). If the determination is no (i.e., that the control gate threshold voltage Vtcg is not greater than or equal to the target control gate threshold voltage Vtcgtarget i.e., that the read current Iread is not less than or equal to the target current Itarget), then in Step <NUM> the control gate program voltage Vcgprogram used for programming is increased relative to that used in the previous Step <NUM> programming of the memory cell, and then Step <NUM> is repeated using the increased control gate program voltage Vcgprogram. Thus, in a first iteration of Step <NUM>, a first program voltage is applied to the gate of the memory cell, and in a second iteration of Step <NUM>, responsive to Step <NUM>, a second program voltage is applied to the gate of the memory cell, where the second program voltage is greater than the first program voltage. Steps <NUM>-<NUM> are repeated, in order, by control circuitry <NUM>, until it is determined in Step <NUM> that the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcgtarget (i.e., that the read current Iread is less than or equal to the target current Itarget). At that point, the memory cell is considered programmed to its desired programming state (i.e. to its target control gate threshold voltage Vtcgtarget).

However, if the programmed memory cell exhibits RTN after programming is completed, then electron(s) captured on interface trap(s) contribute to the measured control gate threshold voltage Vtcg of the memory cell. If/when the electron(s) are emitted from the interface trap(s) after programming is completed, then the control gate threshold voltage Vtcg could drop by more than ΔVtcgmax below the target control gate threshold voltage Vtcgtarget, where ΔVtcgmax is the maximum tolerable read error in terms of control gate threshold voltage Vtcg variation. A control gate threshold voltage drop by more than ΔVtcgmax is considered to be an intolerable error during subsequent read operations. Similarly, if/when the electron(s) are captured on the interface trap(s) after programming is completed, then the control gate threshold voltage Vtcg could increase by more than ΔVtcgmax above the target control gate threshold voltage Vtcgtarget. A control gate threshold voltage increase by more than ΔVtcgmax is considered to be an intolerable error during subsequent read operations. The cells with intolerable error behavior can be assigned for screening. Therefore, memory cell grouping and screening is performed beginning with Step <NUM> in <FIG>. In Step <NUM>, the split gate memory cells <NUM> of array <NUM> are logically divided into memory cell groups <NUM> of N cells in each memory cell group <NUM>, where N is an integer greater than or equal to two. The N split gate memory cells <NUM> in each memory cell group <NUM> can be adjacent to each other in the same column, or adjacent to each other in the same row, or not be adjacent to each other.

For each memory cell group <NUM>, the N memory split gate memory cells <NUM> of the memory cell group <NUM> are programmed to a particular program state (Step <NUM>), i.e. as described above in relation to Steps <NUM> - <NUM>. Thus, steps <NUM> - <NUM> may be performed before, or after, step <NUM>, without limitation. In step <NUM>, the N split gate memory cells <NUM> of the memory cell group <NUM> are each read multiple times. In Step <NUM>, the split gate memory cell <NUM> in the memory cell group <NUM> with the lowest read variance is identified. Read variance for each split gate memory cell <NUM> can be variations in read current Iread and/or variations in control gate threshold voltage Vtcg exhibited between the multiple read operations performed on the split gate memory cell <NUM> in Step <NUM>. It is the split gate memory cell <NUM> in the memory cell group <NUM> with the lowest variation in Iread and/or in Vtcg that is identified in Step <NUM>.

In step <NUM>, the split gate memory cells <NUM> in the memory cell group <NUM> not identified in Step <NUM>, i.e. all of the other split gate memory cells in the memory cell group <NUM>, are deeply programmed (i.e., programmed with a high number of electrons, well beyond the chosen MLC or analog operating range for storing user data, so that these deeply programmed split gate memory cells <NUM> do not contribute to any detected current from the memory cell group <NUM> (or any other memory cell group <NUM>) during subsequent read operations of the split gate memory cell <NUM> in the memory cell group <NUM> (or in any other memory cell group <NUM>) that is used to store user data, because the deeply programmed state of the floating gate with the high number of electrons effectively turns off the underlying channel region <NUM> and prevents current flow). Those skilled in the art will recognize that the operating range and the number of rows in the array <NUM> which contribute to read current differ from product to product. As a result, a specific value for deep programming is implementation dependent. The larger the number of memory cells <NUM> per row, the lower Iread should be for deeply programmed memory cells <NUM>, to prevent their combined contribution to an overall read current for the row. In one example, deep programming of memory cells <NUM> that are to be screened out is performed rapidly, i.e. by one programming pulse and without verification, to save time, and programming voltages for deep screening will be the same for all screened memory cells <NUM>.

In Step <NUM>, the one split gate memory cell <NUM> identified in Step <NUM> is programmed with user data (e.g., as described above with respect to <FIG>). Step <NUM> may require first erasing the one split gate memory cell <NUM> identified in Step <NUM> prior to programing it with user data. Steps <NUM>-<NUM> are performed for each of the memory cell groups <NUM> in the array to be programmed with user data.

In order to read the data from each of the memory cell groups <NUM>, all split gate memory cells <NUM> in the memory cell group <NUM> are selected, but only the split gate memory cell <NUM> identified in Step <NUM> and programmed in Step <NUM> for that memory cell group <NUM> contributes to read current in a data read operation. The other split gate memory cells <NUM> in the memory cell group <NUM> do not contribute current to the read operation because they are deeply programmed. As such, only the split gate memory cell <NUM> in the memory cell group <NUM> identified to have the lowest read variance, and thus the lowest RTN, is used to store user data and to provide the data in any read operations. The other split gate memory cells <NUM> in the memory cell group <NUM> are effectively screened out, thus suppressing any RTN that might otherwise result if the split gate memory cells <NUM> in the memory cell group <NUM> exhibiting higher read variances were used to store user data and/or contribute to the data read operation. The above described memory cell grouping and screening reduces the effect of RTN on analog program and reading accuracy.

The above described technique has many advantages. First, it effectively screens out the split gate memory cells <NUM> exhibiting greater RTN. Second, it avoids having to screen out all the split gate memory cells <NUM> in a given column or row simply because a single noisy split gate memory cell <NUM> is found in the column or row (i.e., by replacing the column or row with a redundancy column or row as is known in the prior art where redundant (spare) rows and/or columns are provided and utilized to replace any row or column that contains a noisy memory cell). Third, while screening out all but one split gate memory cell <NUM> in each memory cell group <NUM> reduces the effective density of usable memory cells in the array, that density reduction is partially or even completely compensated for by the improved accuracy of the analog programming for the less noisy split gate memory cells <NUM> and thus an ability to allocate more possible program levels of read current Iread (or control gate threshold voltage Vtcg) for a given operation range. For example, if N=<NUM> (i.e., two memory cells in each memory cell group), if the improved programming accuracy allows for twice as many possible program states for the one split gate memory cell <NUM> characterized by lower RTN, then twice as many bits can be programmed using the one split gate memory cell <NUM>, thus providing the same memory density as a memory array using all the split gate memory cells <NUM> at half the possible program states per split gate memory cell <NUM>. Therefore, using twice as many program states per split gate memory cell <NUM> compared to a conventional array results in better read-out stability and reliability over time due to reduced RTN across the memory array.

Claim 1:
A memory device, comprising:
a memory array (<NUM>) arranged in a plurality of rows and columns including
a plurality of memory cell groups (<NUM>), where each of the memory cell groups includes N non-volatile memory cells (<NUM>), where N is an integer greater than or equal to <NUM>; and
a control circuitry (<NUM>) that is configured to, for each of the memory cell groups:
program each of the non-volatile memory cells in the memory cell group to a particular program state,
perform multiple read operations on each of the non-volatile memory cells in the memory cell group,
identify one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations,
deeply program all except the identified one of the non-volatile memory cells in the memory cell group with a high number of electrons well beyond a chosen operating range for storing user data, so that the non-volatile memory cells in the memory cell group do not contribute to any detected current during read operations, except the identified one non-volatile memory cell, and
program the one identified non-volatile memory cell in the memory cell group with user data such that each memory cell group is configured to operate as a single memory cell for storing user data.