Patent Description:
The present disclosure relates to the field of ray detection technologies, and in particular to a flat panel detector. The document <CIT> is a relevant prior art.

An X-ray flat panel detector is an X-ray detector with a photoelectric conversion array as its core. Under X-ray irradiation, the scintillator or phosphor layer of the detector converts X-ray photons into visible light. The visible light is then transformed by the array having a photoelectric conversion function into an image electrical signal, and the image electrical signal undergoes transmission and analog-to-digital conversion by peripheral circuits, thereby obtaining a digitized image.

A flat panel detector is provided by an embodiment of the disclosure, which comprises a substrate and a plurality of photodiodes on the substrate. The flat panel detector further comprises a signal line connected to a photodiode of the plurality of photodiodes to provide a bias voltage to the photodiode, and a second transparent conductive layer on a side of the photodiode of the plurality of photodiodes close to the signal line, an orthographic projection of the second transparent conductive layer on the substrate is located within an orthographic projection of the photodiode on the substrate. The flat panel detector further comprises a plurality of gate scanning lines, a plurality of data lines and a thin film transistor on the substrate, the thin film transistor is electrically connected to a gate scanning line of the plurality of gate scanning line and a data line of the plurality of data line and the photodiode, respectively. The flat panel detector further comprises a first transparent conductive layer arranged on a side of the plurality of photodiodes away from the substrate, and an orthographic projection of the first transparent conductive layer on the substrate at least partially overlaps an orthographic projection of each photodiode of the plurality of photodiodes on the substrate. The signal line is disposed between the first transparent conductive layer and the photodiode, the first transparent conductive layer is in direct contact with the signal line. The first transparent conductive layer comprises a plurality of conductive patterns, the plurality of conductive patterns are connected together by conductive connection sections, or the first transparent conductive layer comprises an opening corresponding to the thin film transistor, an orthographic projection of the opening on the substrate overlaps an orthographic projection of the thin film transistor on the substrate.

In some embodiments, the orthographic projection of the first transparent conductive layer on the substrate covers orthographic projections of the plurality of photodiodes on the substrate.

In some embodiments, the first transparent conductive layer is configured to be electrically connected to a constant voltage source.

In some embodiments, the flat panel detector comprises a passivation layer between the first transparent conductive layer and the signal line.

In some embodiments, the plurality of gate scanning lines and the plurality of data lines intersect each other to form a plurality of photosensitive regions arranged in an array. The plurality of conductive patterns are located within the plurality of photosensitive regions respectively, each photosensitive region comprises at least one photodiode of the plurality of the photodiodes, an orthographic projection of each conductive pattern of the plurality of conductive patterns on the substrate at least partially overlaps an orthographic projection of the at least one photodiode within a corresponding photosensitive region on the substrate.

In some embodiments, an orthographic projection of the signal line on the substrate covers an orthographic projection of an active layer of the thin film transistor on the substrate.

In some embodiments, the substrate comprises a bonding region, the flat panel detector further comprises a conduction pattern in the bonding region, the conduction pattern is formed of a same material in a same layer as the first transparent conductive layer.

Another embodiment of the disclosure provides a method for manufacturing the flat panel detector according to the above embodiment, comprising: forming the photodiode on the substrate, and forming the first transparent conductive layer on the substrate on which the photodiode is formed.

In some embodiments, the method further comprises: forming a signal line connected to the photodiode on the substrate, the signal line being configured to provide a working voltage to the photodiode, and forming the first transparent conductive layer on the signal line.

In some embodiments, the signal line is in direct contact with the first transparent conductive layer.

In some embodiments, the method further comprises: forming a passivation layer on the signal line prior to forming the first transparent conductive layer.

In some embodiments, the substrate comprises a bonding region, the method further comprises: forming the first transparent conductive layer and forming a conduction pattern in the bonding region during a single patterning process.

Some embodiments of the disclosure have been summarized above. In the absence of contradiction and conflict, the above-described embodiments and the features in these embodiments may be combined in different ways to obtain other different embodiments, and these other embodiments also fall within the scope of the present application.

In order to more clearly illustrate the technical solutions of embodiments herein, the drawings for describing the embodiments will be briefly described below. The drawings below merely illustrate some embodiments of the present disclosure, and one of ordinary skill in the art can obtain other drawings based on these drawings without inventive efforts.

The technical solutions in embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the present disclosure. The described embodiments are only a part of possible embodiments of the disclosure, rather than all of them. All other embodiments obtained by one of ordinary skill in the art based on the embodiments herein without inventive efforts shall fall within the scope of the application.

<FIG> illustrates the structure of a flat panel detector provided by an embodiment of the disclosure. As shown in <FIG>, each photosensitive region (i.e., the region formed by gate scanning lines <NUM> and data lines <NUM>, which is similar to a pixel region of a liquid crystal display) of the flat panel detector comprises a photodiode <NUM> and a thin film transistor <NUM>. A gate of the thin film transistor <NUM> is connected to a gate scanning line <NUM> of the flat panel detector, a drain of the thin film transistor <NUM> is connected to a data line <NUM> of the flat panel detector, a source of the thin film transistor <NUM> is connected to the photodiode <NUM>, and one end of the data line <NUM> is electrically connected to a data driving circuit <NUM>.

The flat panel detector controls the on/off state of the thin film transistor <NUM> through a scan driving circuit <NUM>. When the thin film transistor <NUM> is turned on, the photocurrent signal generated by the photodiode <NUM> is read by the data driving circuit <NUM> through the data line <NUM> connected to the thin film transistor <NUM>. Collection of the photocurrent signal is accomplished by controlling the timing of the signal on the gate scanning line <NUM>, that is, the photocurrent signal generated by the photodiode <NUM> is collected by controlling the on/off state of the thin film transistor <NUM>.

<FIG> is a partial sectional view of an amorphous silicon flat panel detector provided by an example of the disclosure. As shown in <FIG>, the main structure of the flat panel detector comprises a substrate <NUM>, a photodiode <NUM> and a thin film transistor <NUM> on the substrate <NUM>, a planarization layer <NUM> covering the photodiode <NUM> and the thin film transistor <NUM>, and a scintillation layer <NUM> on the planarization layer <NUM>. The photodiode <NUM> may comprise an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer. The thin film transistor <NUM> comprises a gate, a gate insulating layer, an active layer, a source and a drain. The drain of the thin film transistor is connected to the N-type semiconductor layer of the photodiode. X-rays are modulated by an object to be detected, the modulated X-rays are converted into visible light by the scintillation layer <NUM>, and the visible light is absorbed by the photodiode <NUM> and converted into charge carriers. The charge carriers may be stored in a storage capacitor or the photodiode's own capacitor, forming a charge image. The scan driving circuit <NUM> can sequentially turn on each row of thin film transistors <NUM> to output the charge image to the data driving circuit <NUM> in a row-by-row manner. The charge image transmitted through each thin film transistor <NUM> corresponds to a amount of incident X-rays, thus the amount of X-rays received by each photosensitive region can be judged by determining the amount of charges in each photosensitive region.

For the above-described flat panel detector of the disclosure, inventors of the application have realized that the flat panel detector described above does not have a counter substrate, and on the top of the flat panel detector is a thin passivation layer as a protective layer. As a result, such a flat panel detector is highly susceptible to external static electricity, so that the acquired images may be abnormal.

In view of this, a flat panel detector according to another embodiment of the disclosure comprises a substrate, and a plurality of photodiodes on the substrate. The flat panel detector further comprises a first transparent conductive layer disposed on a side of the photodiode away from the substrate, and an orthographic projection of the first transparent conductive layer on the substrate at least partially overlaps an orthographic projection of each photodiode among the plurality of photodiodes on the substrate. That is, at least a portion of the first transparent conductive layer is directly above the photodiode along the thickness direction (vertical direction) of the flat panel detector. The first transparent conductive layer may be electrically connected to a fixed potential (e.g., reference potential, etc.) when the flat panel detector is in operation. The electrostatic charges over the photodiode can be conducted or transferred via the first transparent conductive layer, thereby preventing the electrostatic charges from affecting the photodiodes and thus affecting the detection accuracy of the flat panel detector. In addition, since the first transparent conductive layer is light transmissive, it does not affect the transmission of light to the photodiodes. The flat panel detector provided by the embodiment will be specifically described below by way of specific examples.

A flat panel detector according to an embodiment of the present disclosure, as shown in <FIG>, comprises a substrate <NUM>, a plurality of photodiodes <NUM> on the substrate <NUM>, and a signal line <NUM> disposed on a side of the photodiode <NUM> away from the substrate <NUM> and connected to the photodiode <NUM>. The flat panel detector further comprises a first transparent conductive layer <NUM> disposed on a side of the photodiode <NUM> away from the substrate <NUM>, and an orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> at least partially overlaps an orthographic projection of the photodiode <NUM> on the substrate <NUM>.

In an embodiment, the signal line <NUM> is configured to provide a bias voltage signal to photodiode <NUM>, for example, the signal line <NUM> is electrically connected to a voltage source providing a constant negative voltage. In some embodiments, in order to enhance the optical signal reception of the photodiode <NUM>, as shown in <FIG>, a second transparent conductive layer <NUM> is disposed on a side of the photodiode <NUM> close to the signal line <NUM> to increase the electrically contacting area between the signal line <NUM> and the photodiode <NUM>.

In the embodiment of <FIG>, the first transparent conductive layer <NUM> and the signal line <NUM> are both disposed on a side of the photodiode <NUM> away from the substrate <NUM>, but the relative positions between the first transparent conductive layer <NUM> and the signal line <NUM> are not limited. As shown in <FIG>, the first transparent conductive layer <NUM> may be disposed on a side of the signal line <NUM> away from the photodiode <NUM>, or the signal line <NUM> may be disposed on a side of the first transparent conductive layer <NUM> away from the photodiode <NUM>. The first transparent conductive layer <NUM> and the signal line <NUM> may be directly connected, and an interlayer insulating layer may also be present therebetween. The structure of <FIG> is merely an example.

According to an embodiment of the disclosure, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> at least partially overlaps the orthographic projection of a single photodiode <NUM> on the substrate <NUM>. That is, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> may partially overlap the orthographic projection of the photodiode <NUM> on the substrate <NUM>, or the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> may include the orthographic projection of the photodiode <NUM> on the substrate <NUM>, or the orthographic projection of the photodiode <NUM> on the substrate <NUM> may include the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM>.

As to the material of the first transparent conductive layer <NUM>, a conductive material whose transmittance of light in the PIN operating band is <NUM>% or more may be selected, for example, a transparent conductive material may be employed, which may be, for example, IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), AZO (Al Zinc Oxide), IFO (Indium F Oxide), and the like.

In some embodiments, the first transparent conductive layer <NUM> may comprise a plurality of conductive patterns in one-to-one correspondence with the plurality of photodiodes. The orthographic projection of each conductive pattern on the substrate at least partially overlaps the orthographic projection of a corresponding photodiode among the plurality of photodiodes on the substrate. Alternatively, in a further embodiment, the first transparent conductive layer <NUM> may be a planar integral structure corresponding to all of the photodiodes <NUM>. For the flat panel detector provided by the embodiment of the present disclosure, the first transparent conductive layer <NUM> is disposed on a side of the photodiode <NUM> away from the substrate <NUM>, so that during the operation of the flat panel detector, the first transparent conductive layer <NUM> having a certain potential is able to isolate external static electricity from the photodiode <NUM> while not affecting visible light being irradiated onto the photodiode <NUM>, which can mitigate the influence of external static electricity on the photodiode <NUM>, improve the antistatic ability of the flat panel detector, and ensure the yield of acquired images.

In some embodiments, in order to enable the first transparent conductive layer <NUM> to minimize the influence of external static electricity on the photodiode <NUM>, as shown in <FIG>, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> covers the orthographic projection of the photodiode <NUM> on the substrate <NUM>. In the case where the first transparent conductive layer <NUM> is disposed between the signal line <NUM> and the photodiode <NUM>, the signal line <NUM> may be electrically connected to the photodiode <NUM> through the first transparent conductive layer <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, a signal line <NUM> is disposed between the first transparent conductive layer <NUM> and the photodiode <NUM>. That is, the first transparent conductive layer <NUM> is disposed on a side of the signal line <NUM> away from the photodiode <NUM>, and other interlayer structures may be disposed therebetween, or they may be in direct contact with each other. In the embodiments of <FIG> or <FIG>, by disposing the signal line <NUM> between the first transparent conductive layer <NUM> and the photodiode <NUM>, on the one hand, the first transparent conductive layer <NUM> can protect the signal line <NUM>, and on the other hand, it is not necessary to form a via hole in the first transparent conductive layer <NUM>, which is advantageous to complete coverage of the photodiode <NUM> by the first transparent conductive layer <NUM>.

In some embodiments, as shown in <FIG>, a passivation layer <NUM> is disposed between the first transparent conductive layer <NUM> and the signal line <NUM>. By disposing the passivation layer <NUM> between the first transparent conductive layer <NUM> and the signal line <NUM>, the signal line can be fully protected, and it is beneficial to achieve a planar surface of the flat panel detector. In some embodiments, as shown in <FIG> or <FIG>, the first transparent conductive layer <NUM> is directly disposed on the surface of the signal line <NUM>. That is to say, after the signal line <NUM> is formed, the first transparent conductive layer <NUM> is formed without preparing the passivation layer <NUM>. This can prevent the signal line <NUM> from being over etched under the influence of process fluctuations when the passivation layer <NUM> is being formed, which will lead to a problem that the image quality is affected by the signal fluctuation on the signal line <NUM>. In addition, the first transparent conductive layer <NUM> is disposed on the surface of the signal line <NUM>, so signal lines <NUM> for the photodiodes of different columns and different rows may be electrically connected to each other through the first transparent conductive layer <NUM>, which can reduce the total impedance of the signal lines of the flat panel detector, thereby decreasing the voltage drop on the signal line, reducing the differences between the working voltages received by the photodiodes at different positions in the flat panel detector, and achieving compensation for the working voltage signal on the signal line <NUM>. On the other hand, the first transparent conductive layer <NUM> can serve to protect the signal line <NUM>, so that the stability of the signal on the signal line <NUM> can be improved. Furthermore, since the first transparent conductive layer <NUM> is in direct contact with the signal line <NUM>, the potential of the first transparent conductive layer is the same as the potential of the signal line <NUM>, there is no need for an individual signal source to provide a signal to the first transparent conductive layer <NUM>, which simplifies the structure of the flat panel detector.

In some embodiments, as shown in <FIG>, the first transparent conductive layer <NUM> comprises a plurality of conductive patterns <NUM>, each of which corresponds to a photodiode <NUM>. The plurality of conductive patterns <NUM> are connected by conductive connection sections <NUM>.

<FIG> illustrates a structural view of a flat panel detector not provided with the first transparent conductive layer <NUM>. <FIG> illustrates a view of a flat panel detector provided with the first transparent conductive layer <NUM>. In the example of <FIG>, one conductive pattern <NUM> corresponds to one photodiode <NUM>. In a further embodiment, one conductive pattern <NUM> may correspond to a plurality of photodiodes <NUM>. As shown in <FIG>, the coverage region of the conductive connection section <NUM> intersects with the coverage region of the gate scanning line <NUM> or the data line <NUM>. In order to avoid formation of a parasitic capacitance between the conductive connection section <NUM> and the gate scanning line <NUM> or the data line <NUM>, which in turn affects the accuracy of the signal in the photodiode <NUM>, the overlapping area between the conductive connection section <NUM> and the gate scanning line <NUM> or the data line <NUM> should be reduced as much as possible while ensuring connections between the conductive patterns <NUM>.

The conductive connection sections <NUM> make it possible that the plurality of conductive patterns <NUM> of the flat panel detector are connected together to form an entirety. As shown in <FIG>, it is not the case that a conductive connection section <NUM> has to be disposed between any two adjacent conductive patterns <NUM>, it is just required that the disposed conductive connection sections <NUM> enable the plurality of conductive patterns <NUM> in the flat panel detector to be connected together. Of course, in order to ensure the stability of the connection, more conductive connection sections <NUM> may be disposed. The shapes and the arrangement of the conductive connection sections <NUM> shown in <FIG> are merely illustrative and are not intended to limit the present application.

The plurality of conductive patterns <NUM> are connected together by the conductive connection sections <NUM>, so the conductive patterns <NUM> in the entire flat panel detector may receive the same voltage signal. In case the conductive patterns <NUM> are disposed on the signal line <NUM>, a plurality of signal lines <NUM> in different columns and different rows are electrically connected to each other via the conductive patterns <NUM>. As described above, this provides compensation for the voltage signals on the signal lines <NUM> to improve uniformity of the signals on the signal lines <NUM> at different positions of the flat panel detector, thereby improving the quality of acquired images.

In some embodiments, as shown in <FIG>, a thin film transistor <NUM> connected to the photodiode <NUM>, a gate scanning line <NUM> and a data line <NUM> connected to the thin film transistor <NUM> are arranged on the substrate <NUM>. A plurality of gate scanning lines <NUM> and a plurality of data lines <NUM> intersect each other to form a plurality of photosensitive regions arranged in an array, and the conductive patterns <NUM> are located in the photosensitive regions. In <FIG>, a bottom gate type thin film transistor is illustrated as an example, but this does not limit the scope of the present application.

In some embodiments, each of the conductive patterns <NUM> corresponds to each photodiode <NUM>, the conductive pattern <NUM> is located within the photosensitive region, and the conductive patterns do not overlap the gate scanning lines <NUM> or the data lines <NUM>.

In some embodiments, as shown in <FIG>, the thin film transistor <NUM> comprises a gate <NUM>, a source <NUM>, and a drain <NUM>. None of the orthographic projection of the gate <NUM>, the orthographic projection of the source <NUM> and the orthographic projection of the drain <NUM> on the substrate <NUM> overlaps the orthographic projections of the conductive patterns <NUM> on the substrate <NUM>. That is, the thin film transistor <NUM> is outside the photosensitive region. As shown in <FIG>, in the thickness direction of the flat panel detector, the first transparent conductive layer <NUM> is not disposed directly above the gate <NUM>, the source <NUM>, and the drain <NUM> of the thin film transistor <NUM>, that is, the conductive patterns <NUM> are not directly above the thin film transistor <NUM>. As a result, the influence of the conductive patterns <NUM> on the performance of the thin film transistor <NUM> can be avoided or reduced. In other words, the orthographic projections of the conductive patterns <NUM> on the substrate <NUM> cover the orthographic projections of the photodiodes <NUM> on the substrate <NUM>, but does not cover the orthographic projections of the gate <NUM>, the source <NUM>, and the drain <NUM> of the thin film transistor <NUM> on the substrate <NUM>.

In some embodiments, as shown in <FIG>, the signal line <NUM> does not shield the active layer of the thin film transistor <NUM> to simplify the layout of the signal line <NUM>. Alternatively, in some embodiments, as shown in <FIG>, the orthographic projection of signal line <NUM> on the substrate <NUM> covers the orthographic projection of active layer <NUM> of thin film transistor <NUM> on the substrate <NUM> such that the active layer <NUM> is shielded by the signal line <NUM> so as to prevent the active layer <NUM> from generating carriers due to illumination.

According to a further embodiment of the disclosure, the signal line <NUM> does not shield the active layer of the thin film transistor <NUM>, and the flat panel detector comprises a light shielding layer <NUM>. As shown in <FIG>, the light shielding layer <NUM> is disposed above the active layer <NUM>, preventing the active layer <NUM> from generating carriers due to illumination. Moreover, a second transparent conductive layer <NUM> is arranged on a side of the photodiode <NUM> close to the signal line <NUM>, and the second transparent conductive layer <NUM> exposes a portion of the photodiode <NUM>, that is, the orthographic projection of the second transparent conductive layer <NUM> on the substrate <NUM> is within the orthographic projection of the photodiode <NUM> on the substrate, thereby reducing or avoiding the occurrence of edge leakage current of the photodiode.

In some embodiments, the substrate <NUM> of the flat panel detector comprises a bonding region, and the flat panel detector further comprises a conduction pattern in the bonding region. The conduction pattern and the first transparent conductive layer <NUM> may be formed of the same material in the same layer. Related signal transmission lines (e.g., gate lines, data lines, etc.) in the flat panel detector may be electrically connected to external circuits (e.g., an integrated circuit chip) via the bonding region to provide necessary control signals for the electrical components on the substrate <NUM> and to analyze and process the electrical signals collected by the flat panel detector. The aforementioned signal transmission lines may extend to the bonding region, the bonding region may include conduction patterns corresponding to the aforementioned signal transmission lines, and the conduction patterns may be located above and electrically connected to the signal transmission lines. The conduction patterns in the bonding region may be exposed, so that the external circuits can be easily connected to the conduction patterns, thereby realizing electrical connections between the external circuits and the signal transmission lines. In addition, the conduction patterns can also provide protection for the signal transmission lines. For example, <FIG> illustrates an example of a schematic sectional view in which a bonding region is added on the basis of <FIG>. As shown in <FIG>, a gate line <NUM> electrically connected to the gate of the thin film transistor is formed in the bonding region of the substrate <NUM>, an insulating layer and a conduction pattern <NUM> are formed over the gate line <NUM>, and the conduction pattern <NUM> is electrically connected to the gate line through a via hole <NUM>. Thus, an external circuit may be electrically connected to the gate line in the flat panel detector via the conduction pattern <NUM> to provide a control signal for the gate line.

In an embodiment of the disclosure, the first transparent conductive layer <NUM> and the conduction pattern in the bonding region are formed of the same material. Therefore, the first transparent conductive layer <NUM> and the conduction pattern in the bonding region may be formed in the same patterning process. Without increasing the number of mask processes, it is only necessary to change the pattern of the mask plate, which can simplify the manufacturing process of the flat panel detector.

As previously described, in some embodiments, the first transparent conductive layer may be a continuous planar conductive layer that covers all of the photosensitive regions of the flat panel detector. <FIG> illustrates an example in which the first transparent conductive layer <NUM> covers all of the photosensitive regions of the flat panel detector. In a further embodiment, a plurality of openings corresponding to the thin film transistors may be formed in the continuous planar conductive layer. For example, as shown in <FIG>, the orthographic projection of an opening <NUM> on the substrate overlaps the orthographic projection of a corresponding thin film transistor on the substrate.

Another embodiment of the disclosure further provides a method for manufacturing a flat panel detector, as shown in <FIG>, comprising the following steps.

S10, forming a photodiode <NUM> on a substrate <NUM>.

S20, forming a first transparent conductive layer <NUM> on the substrate <NUM> on which the photodiode <NUM> is formed, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> at least partially overlaps the orthographic projection of the photodiode <NUM> on the substrate <NUM>.

In some embodiments, step S20 comprises: S201, forming a signal line <NUM> connected to the photodiode <NUM> on the substrate <NUM> on which the photodiode <NUM> is formed, the signal line <NUM> being configured to provide a working voltage to the photodiode; S202, forming the first transparent conductive layer <NUM> on the substrate <NUM> on which the signal line <NUM> is formed. That is, after the photodiode <NUM> is formed, the signal line <NUM> is formed first, and the first transparent conductive layer <NUM> is then formed.

In some embodiments, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> covers the orthographic projection of the photodiode <NUM> on the substrate <NUM>.

In some embodiments, the first transparent conductive layer <NUM> is formed after a passivation layer <NUM> is formed on the substrate <NUM> on which the signal line <NUM> is formed.

In some embodiments, the substrate further comprises a bonding region, In order to further simplify the manufacturing process, a conduction pattern is formed in the bonding region while the first transparent conductive layer <NUM> is being formed, and the conduction pattern and the first transparent conductive layer are formed during the same patterning process. That is, the first transparent conductive layer <NUM> and the conduction pattern of the bonding region are formed synchronously.

The method for manufacturing a flat panel detector provided by the embodiment of the disclosure will be described below by way of specific examples.

The process of manufacturing the flat panel detector as shown in <FIG> may comprise the following steps.

S100, forming a thin film transistor <NUM> on the substrate <NUM>.

By way of example, step S100 comprises: S110, forming a gate on the substrate <NUM>. S120, forming a gate insulating layer on the substrate <NUM> on which the gate is formed. S120, forming an active layer on the substrate <NUM> on which the gate insulating layer is formed. S <NUM>, forming a source and a drain on the substrate <NUM> on which the active layer is formed.

S200, forming a photodiode <NUM> on the substrate <NUM> on which the thin film transistor <NUM> is formed.

As an example, step S200 comprises: S210, forming an N-type semiconductor layer on the substrate <NUM> on which the thin film transistor <NUM> is formed. S220, forming an intrinsic semiconductor layer on the substrate <NUM> on which the N-type semiconductor layer is formed. S230, forming a P-type semiconductor layer on the substrate <NUM> on which the intrinsic semiconductor layer is formed. S300, forming a planarization layer <NUM> on the substrate <NUM> on which the photodiode <NUM> is formed. S400, forming a signal line <NUM> on the substrate <NUM> on which the planarization layer <NUM> is formed. S500, forming a passivation layer <NUM> on the substrate <NUM> on which the signal line <NUM> is formed. S600, forming a first transparent conductive layer <NUM> on the substrate <NUM> on which the passivation layer <NUM> is formed, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> covering the orthographic projection of the photodiode <NUM> on the substrate <NUM>. S700, forming a scintillation layer <NUM> on the substrate <NUM> on which the first transparent conductive layer <NUM> is formed.

S300, forming a planarization layer <NUM> on the substrate <NUM> on which the photodiode <NUM> is formed.

S400, forming a signal line <NUM> on the substrate <NUM> on which the planarization layer <NUM> is formed.

S500, forming a first transparent conductive layer <NUM> on the substrate <NUM> on which the signal line <NUM> is formed, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> covering the orthographic projection of the photodiode <NUM> on the substrate <NUM>. Alternatively, S500', forming a first transparent conductive layer <NUM> and a conduction pattern synchronously on the substrate <NUM> on which the signal line <NUM> is formed, the orthographic projection of the first transparent conductive layer <NUM> on the substrate <NUM> covering the orthographic projection of the photodiode <NUM> on the substrate <NUM>, the first transparent conductive layer <NUM> being located in the photosensitive region, and the conduction pattern being located in the bonding region.

S600, forming a scintillation layer <NUM> on the substrate <NUM> on which the first transparent conductive layer <NUM> is formed.

Of course, it is also possible to dispose an insulating layer or a passivation layer between layers as needed.

Claim 1:
A flat panel detector, comprising a substrate (<NUM>) and a plurality of photodiodes (<NUM>) on the substrate (<NUM>),
wherein the flat panel detector further comprises a signal line (<NUM>) connected to a photodiode (<NUM>) of the plurality of photodiodes (<NUM>) to provide a bias voltage to the photodiode (<NUM>), and a second transparent conductive layer (<NUM>) on a side of the photodiode (<NUM>) of the plurality of photodiodes (<NUM>) close to the signal line (<NUM>), an orthographic projection of the second transparent conductive layer (<NUM>) on the substrate (<NUM>) is located within an orthographic projection of the photodiode (<NUM>) on the substrate (<NUM>),
wherein the flat panel detector further comprises a plurality of gate scanning lines (<NUM>), a plurality of data lines (<NUM>) and a thin film transistor (<NUM>) on the substrate (<NUM>), the thin film transistor (<NUM>) is electrically connected to a gate scanning line (<NUM>) of the plurality of gate scanning line (<NUM>) and a data line (<NUM>) of the plurality of data line (<NUM>) and the photodiode (<NUM>), respectively,
characterized in that, the flat panel detector further comprises a first transparent conductive layer (<NUM>) arranged on a side of the plurality of photodiodes (<NUM>) away from the substrate (<NUM>), an orthographic projection of the first transparent conductive layer (<NUM>) on the substrate (<NUM>) at least partially overlaps an orthographic projection of each photodiode (<NUM>) of the plurality of photodiodes on the substrate (<NUM>),
wherein the signal line (<NUM>) is disposed between the first transparent conductive layer (<NUM>) and the photodiode (<NUM>), the first transparent conductive layer (<NUM>) is in direct contact with the signal line (<NUM>),
wherein the first transparent conductive layer (<NUM>) comprises a plurality of conductive patterns (<NUM>), the plurality of conductive patterns (<NUM>) are connected together by conductive connection sections (<NUM>), or the first transparent conductive layer (<NUM>) comprises an opening (<NUM>) corresponding to the thin film transistor (<NUM>), an orthographic projection of the opening (<NUM>) on the substrate (<NUM>) overlaps an orthographic projection of the thin film transistor (<NUM>) on the substrate (<NUM>).