Patent Description:
The disclosure relates to the technical field of semiconductors, in particular to a memory and a method for manufacturing the same.

With the continuous development of semiconductor technology and storage technology, electronic devices are developing towards miniaturization and integration. A dynamic random access memory (DRAM) is widely used in various electronic devices because of its high storage density and fast reading and writing speed. The dynamic random access memory is generally composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The capacitor stores data information, and the transistor controls reading and writing of the data information in the capacitor. However, in the existing structure, the width of a word line is small and the resistance of the word line is large, which makes the manufacture of the memory difficult and the performance poor.

Background may be found in <CIT>, and <CIT>.

The present application is defined in appended independent claim <NUM> to which reference should be made. Advantageous features are set out in the appended dependent claims <NUM>-<NUM>.

With the miniaturization of the size of integrated circuits, it is more difficult to manufacture a memory. With the decreases of the pitch between adjacent word lines, defects are easily to appear in the word lines during manufacturing, which affects the performance of the memory. In view of the above, the embodiments of the disclosure provide a method for manufacturing a memory, in which a substrate is provided, and active pillars are formed on the substrate. A plurality of bit lines are formed in the substrate, and each bit line includes a plurality of straight line segments connected end to end in sequence. Adjacent straight line segments have an included angle therebetween. Each straight line segment of each bit line is electrically connected with at least two active pillars, so that the plurality of active pillars are staggered on the substrate, which can improve the density of the active pillars and increase the width of the gate, thereby improving the performance of the memory. Meanwhile, the bending number of each bit line is reduced, which is convenient for the manufacture of the memory.

In order to make the above-mentioned objects, features and advantages of the embodiments of the disclosure more apparent and understandable, the technical solutions in the embodiments of the disclosure will be clearly and completely described with reference to the drawings in the embodiments of the disclosure. Apparently, the described embodiments are only a part of the embodiments of the disclosure, but not all of them. Based on the embodiments in the disclosure, any other embodiments obtained by those of ordinary skill in the art without making creative efforts are within the scope of protection of the disclosure.

Referring to <FIG>, it is a flowchart of a method for manufacturing a memory in an embodiment of the disclosure. The method includes the following operations.

At S100, a substrate is provided, in which a plurality of bit lines arranged at intervals are formed in the substrate. Each bit line includes a plurality of straight line segments connected end to end in sequence, and adjacent line segments have an included angle therebetween.

The substrate is used for providing a support, and may be a semiconductor substrate. The material of the semiconductor substrate may be one or more of silicon, germanium, silicon germanium, silicon carbide, Silicon on Insulator (SOI), Germanium on Insulator (GOI) or the like.

The plurality of bit lines <NUM> arranged at intervals are formed in a substrate (referring to <FIG>). Each bit line <NUM> includes a plurality of straight line segments connected end to end in sequence and adjacent line segments have an included angle therebetween, so that each bit line <NUM> is in a zigzag type.

Specifically, the plurality of straight line segments included by each bit line <NUM> include a plurality of first straight line segments <NUM> extending in a second direction (direction Y1 shown in <FIG>) and a plurality of second straight line segments <NUM> extending in a third direction ( direction Y2 shown in <FIG>). Each second line segment <NUM> is connected with two adjacent first straight line segments <NUM>, so that each bit line <NUM> is in form of a wavy polyline to make full use of the space of the substrate. Exemplarily, the included angle formed by the second direction and the third direction may be <NUM>° to <NUM>°, for example <NUM>°.

At S200, a plurality of active pillars arranged at intervals and a plurality of insulating layers arranged at intervals are formed on the substrate. Each straight line segment of each bit line is electrically connected with at least two active pillars. The insulating layers extend along a first direction and cover the outer peripheral surfaces of the active pillars.

Referring to <FIG>, the plurality of active pillars <NUM> and the plurality of insulating layers <NUM> are formed on the substrate <NUM>. In order to distinguish elements in the drawing, the active pillars <NUM> are filled with patterns in a top view in the embodiments of the disclosure. The top view is a partial view of the memory, for example, the view of a partial area enclosed by dashed lines in <FIG>. The plurality of active pillars <NUM> are arranged at intervals, and each straight line segment of each bit line <NUM> (referring to <FIG>) is electrically connected with at least two active pillars <NUM>. For example, the active pillars <NUM> are in contact with the corresponding bit line <NUM> to achieve the electrical connection between the active pillars <NUM> and the bit line <NUM>. By electrically connecting multiple active pillars <NUM> with each straight line segment, it is avoided that each bit line <NUM> needs to be bent once every time it passes through one active pillar <NUM>, thereby reducing the bending number of each bit line <NUM> and reducing the manufacturing difficulty of the bit line <NUM>.

In some possible embodiments, the bit line <NUM> covers the orthographic projections of multiple active pillars <NUM> on the substrate <NUM>. By this arrangement, the entire bottom surface of the active pillar <NUM> is in contact with the bit line <NUM>, and thus contact area between the active pillar <NUM> and the bit line <NUM> is large, thereby reducing the contact resistance between the active pillar <NUM> and the bit line <NUM>.

The active pillars <NUM> are used to form a source region, a drain region, and a channel region located between the source region and the drain region. The source region, drain region and channel region are arranged in a direction perpendicular to the substrate <NUM>, and one of the source region and drain region is in contact with the substrate <NUM>. The material of an active area may be a semiconductor material. Exemplarily, the material of the active pillar <NUM> may be the same as or different from the material of the substrate <NUM>. The substrate <NUM> and the active pillars <NUM> located on the substrate <NUM> are formed by etching the semiconductor material, in which the bit lines <NUM> are embedded bit lines.

In a possible embodiment, taking a plane parallel to the substrate <NUM> as a cross section, multiple active pillars <NUM> are arranged in a hexagonal close-packed structure. The hexagonal close-packed structure can be seen in <FIG>. Each seven active pillars <NUM> is regarded as a group, in which the centers of six active pillars <NUM> enclose into a virtual hexagon, i.e. the centers of the six active pillars <NUM> are respectively located at the six vertices of the virtual hexagon, and the center of the seventh active pillar <NUM> is located at the center of the virtual hexagon. Taking the plane parallel to the substrate as a cross section, the cross section of the active pillar <NUM> may not be in a shape of circular, which does not affect the arrangement of the plurality of active pillars <NUM>.

By this arrangement, the density of the active pillars <NUM> can be increased. When capacitors on the active pillars <NUM> are also arranged in the hexagonal close-packed structure, on the one hand, the density of the capacitors can be increased, thereby increasing the density of memories; on the other hand, the capacitor can be directly on the active pillar <NUM>, without arranging a capacitor contact pad to transition the formation between the capacitor and the active pillar <NUM>, thereby reducing the complexity of manufacturing the memory. For example, when the active pillars <NUM> are arranged in a square structure, it is necessary to manufacture capacitor contact pads on the active pillars <NUM>, so as to arrange the capacitors in the hexagonal close-packed structure.

Still referring to <FIG>, the plurality of insulating layers <NUM> are arranged at intervals, extend in the first direction (direction X shown in <FIG>) and cover on the outer peripheral surfaces of the active pillars <NUM>. As shown in <FIG>, each insulating layer <NUM> corresponds to at least one active area located in the first direction and covers on the outer peripheral surface of at least one active area. The material of the insulating layer <NUM> may be silicon oxide, silicon nitride, silicon oxynitride or the like.

Specifically, as shown in <FIG>, each insulating layer <NUM> includes a first surrounding portion <NUM> and a first connecting portion <NUM>. The first surrounding portion <NUM> is shown as an area surrounded by dashed lines in <FIG>, covers on the outer peripheral surface of the active pillar <NUM>. The first connecting portion <NUM> is connected with two adjacent first surrounding portions <NUM> and extends in the first direction. That is, the first surrounding portion <NUM> corresponds to the active pillar <NUM>, and surrounds the entire circumference of the active pillar <NUM>, and the first connecting portion <NUM> is connected with two adjacent first surrounding portions <NUM> in the first direction.

At S300, a first support layer is formed by filling between adjacent insulating layers.

Referring to <FIG>, the first support layer <NUM> is formed between adjacent insulating layers <NUM> by a deposition process. The first support layer <NUM> fills up the space between adjacent insulating layers <NUM>. For example, the space between adjacent insulating layers <NUM> is filled by a process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or the like, to form the first support layer <NUM>.

As shown in <FIG> and <FIG>, the surface facing away from the substrate <NUM>, of the first support layer <NUM> may be flush with the surface facing away from the substrate <NUM>, of the insulating layer <NUM>. That is, the top surface of the first support layer <NUM> is flush with the top surface of the insulating layer <NUM>. The material of the first support layer <NUM> may be silicon oxide, silicon nitride or silicon oxynitride, and is different from the material of the insulating layer <NUM>, so as to reduce the damage to the first support layer <NUM> when the insulating layer is subsequently removed. Exemplarily, the material of the insulating layer <NUM> is silicon oxide (e.g., SiO<NUM>), and the material of the first support layer <NUM> is silicon nitride (e.g., Si<NUM>N<NUM>).

At S400, part away from the substrate, of the insulating layer is removed to form a filling space which exposes part of the outer peripheral surface of the active pillar.

Referring to <FIG>, part away from the substrate <NUM>, of the insulating layer <NUM> is removed. For example, this part of the insulating layer <NUM> is removed by etching. As shown in <FIG> and <FIG>, the middle part and upper part of the insulating layer <NUM> are removed to retain the lower part of the insulating layer <NUM>. A filling space <NUM> is formed after part of the insulating layer <NUM> is removed. The filling space <NUM> exposes the outer peripheral surface of the active pillar <NUM>. Specifically, the filling space <NUM> exposes the outer peripheral surface of the channel region, so as to form a dielectric layer <NUM> and a conductive layer <NUM> on the outer peripheral surface of the channel region.

At S500, a dielectric layer and a conductive layer are formed between parts exposed in the filling space and close to the substrate, of the active pillars to form a word line.

Referring to <FIG>, the dielectric layer <NUM> is formed on part, exposed in the filling space <NUM> and close to the substrate <NUM>, of the outer peripheral surface of the active pillar <NUM>, and a conductive layer <NUM> is formed on the outer peripheral surface of the dielectric layer <NUM>. The conductive layer <NUM> is formed by filling between the dielectric layer <NUM> and the first support layer <NUM>. The conductive layer <NUM> and the dielectric layer <NUM> form a word line. The dielectric layer <NUM> and the conductive layer <NUM> surrounding the outer peripheral surface of the dielectric layer <NUM> form a gate. That is, the gate is part of the word line <NUM>. The word line <NUM> extends in the first direction. Specifically, the dielectric layer <NUM> may be an oxide layer, and forms a gate oxide layer. The material of the conductive layer <NUM> may be a metal, and the conductive layer <NUM> surrounding the outer peripheral surface of the dielectric layer <NUM> forms a gate conductive layer.

In some possible embodiments, the included angle between the second direction and the first direction shown in <FIG> is <NUM>°, the included angle between the third direction and the first direction is <NUM>°. A first pitch between adjacent word lines <NUM> is equal to a second pitch between adjacent bit lines <NUM>. By this arrangement, it is convenient to form the plurality of active pillars <NUM> arranged in the hexagonal close-packed structure (referring to <FIG>), reducing the difficulty of manufacturing the active pillars <NUM> arranged in the hexagonal close-packed structure.

In some possible embodiments, forming the dielectric layer and the conductive layer between the active pillars exposed in the filling space and close to the substrate to form the word line (S500) may include the following operations.

At S501, part exposed in the filling space and close to the substrate, of the outer peripheral surface of the active pillar is at least removed to thin the active pillar and enlarge the filling space.

As shown in <FIG> and <FIG>, part exposed in the filling space <NUM> and close to the substrate <NUM>, of the outer peripheral surface of the active pillar <NUM> is at least removed to thin the active pillar <NUM> and enlarge the filling space <NUM>, thereby increasing the space for forming a gate and improving the forming quality of the gate.

Exemplarily, all the part exposed in the filling space <NUM>, of the active pillar <NUM> is etched by a process such as wet etching, so that all the outer peripheral surface of the active pillar <NUM> exposed in the filling space <NUM> is etched to thin the active pillar <NUM> and increase the volume of the filling space <NUM>. Thinning the active pillar <NUM> means that the radial distance of the active pillar <NUM> is reduced, i.e. the diameter of the active pillar <NUM> is reduced after etching. Taking the plane parallel to the substrate <NUM> as a cross section, the etched active pillar <NUM> is in the region of the active pillar <NUM> before etching.

At S502, the dielectric layer is formed on part close to the substrate of the outer peripheral surface of the active pillar. There is a gap between the dielectric layer and the first support layer.

As shown in <FIG> and <FIG>, the dielectric layer <NUM> is formed on part exposed in the filling space <NUM> and close to the substrate <NUM>, of the outer peripheral surface of the active pillar <NUM>. That is, the dielectric layer <NUM> is formed on the outer peripheral surface of the active pillar <NUM> located at the lower part of the filling space <NUM>, circumferentially surrounds and covers this part of the active pillar <NUM>. There is no contact between the dielectric layer <NUM> and the first support layer <NUM> to provide a space required for forming the conductive layer <NUM>.

In some possible embodiments, the material of the active pillar <NUM> is silicon, and the material of the dielectric layer <NUM> is silicon oxide. The dielectric layer <NUM> is grown on the outer peripheral surface, exposed in the filling space <NUM>, of the active pillar <NUM> by a thermal oxidation process. The dielectric layer <NUM> located on part away from the substrate <NUM>, of the active pillar <NUM> is then removed, to retain the dielectric layer <NUM> located on part close to the substrate <NUM>, of the active pillar <NUM>.

In other possible embodiments, the dielectric layer <NUM> is formed on the outer peripheral surface exposed in the filling space <NUM>, of the active pillar <NUM> by a deposition process. Then, the dielectric layer <NUM> located on part away from the substrate <NUM>, the active pillar <NUM> is removed by etching with controlling the parameters in the etching process, to retain the required dielectric layer <NUM>.

At S503, the conductive layer is formed on the outer peripheral surface of the dielectric layer, and fills between the dielectric layer and the first support layer.

Still referring to <FIG> and <FIG>, the conductive layer <NUM> is formed on the outer peripheral surface of the dielectric layer <NUM> by depositing, and fills between the dielectric layer <NUM> and the first support layer <NUM>. That is, the conductive layer <NUM> fills up the space between the dielectric layer <NUM> and the first support layer <NUM>. The conductive layer <NUM> includes a second surrounding portion <NUM> surrounding the dielectric layer <NUM> and a second connecting portion <NUM> connecting adjacent second surrounding portions <NUM>. The second surrounding portion <NUM> is shown as an area surrounded by dotted lines in <FIG>. The second surrounding portion <NUM> and the dielectric layer <NUM> constitute a gate. The conductive layer <NUM> and the dielectric layer <NUM> constitute the word line <NUM> (referring to <FIG>), that is, part of the word line <NUM> serves as the gate.

It should be noted that the conductive layer <NUM> further includes an extension portion connected to the outer side of the second surrounding portion <NUM> located at outermost side, in which the outer side refers to one side of the outermost second surrounding portion <NUM> away from other second surrounding portions <NUM>. Exemplarily, the left side of the second surrounding portion <NUM> located at the leftmost side is connected with one extension portion and the right side thereof is connected with the second connecting portion <NUM>; the right side of the second surrounding portion <NUM> located at the rightmost side is connected with one extension portion, and the left side thereof is connected with the second connecting portion <NUM>. By arranging the extension portions, the conductive layer <NUM> can be connected with a peripheral circuit, thereby realizing the control function of the word line <NUM>.

Specially, the formation of the conductive layer <NUM> filling between the dielectric layer <NUM> and the first support layer <NUM>, on the outer peripheral surface of the dielectric layer <NUM> may include the following operations.

An initial conductive layer is deposited in the enlarged filling space <NUM>. The initial conductive layer fills between the dielectric layer <NUM> and the first support layer <NUM> and covers the dielectric layer <NUM>. The initial conductive layer is deposited between the dielectric layer <NUM> and the first support layer <NUM>, and also covers the dielectric layer <NUM>. For example, the initial conductive layer fills up the enlarged filling space <NUM>.

After the initial conductive layer is formed, the initial conductive layer located on the dielectric layer <NUM> is removed to expose the dielectric layer <NUM>, while the remaining part of the initial conductive layer forms the conductive layer <NUM>. The surface facing away from the substrate <NUM>, of the conductive layer <NUM> is flush with the surface facing away from the substrate <NUM>, of the dielectric layer <NUM>. Referring to <FIG> and <FIG>, the initial conductive layer located on the side facing away from the substrate <NUM> of the dielectric layer <NUM> is removed by an etching process, and the remaining part of the initial conductive layer forms the conductive layer <NUM>. The upper surface of the conductive layer <NUM> is flush with the upper surface of the dielectric layer <NUM>. That is, the required conductive layer <NUM> is formed by depositing and etching back.

To sum up, according to the method for manufacturing a memory in the embodiments of the disclosure, each bit line <NUM> in the substrate <NUM> includes the plurality of straight line segments connected end to end in sequence, and the adjacent straight line segments have the included angle therebetween. By forming the plurality of active pillars <NUM> arranged at intervals on the substrate <NUM>, the density of the active pillars <NUM> can be improved by arranging the plurality of active pillars <NUM> in the staggered manner on the substrate <NUM>, thereby improving the performance of the memory. At least two active pillars <NUM> are electrically connected to each straight line segment of each bit line <NUM>, thereby reducing the bending number of each bit line <NUM> and facilitating the manufacture of the memory. In addition, the insulating layer <NUM> covers the outer peripheral surface of the active pillar <NUM>. After removing part of the insulating layer <NUM>, the dielectric layer <NUM> and the conductive layer <NUM> are formed between the exposed active pillars <NUM>. The dielectric layer <NUM> and the conductive layer <NUM> constitute the gate, and the plurality of active pillars <NUM> are staggered on the substrate <NUM>, which increases the width of the gate in the radial direction of the active pillar <NUM>, improves the forming quality of the gate, reduces the resistance of the gate and further improves the performance of the memory.

In some possible embodiments, referring to <FIG>, the operation (S200) that the plurality of active pillars arranged at intervals and the plurality of insulating layers arranged at intervals are formed on the substrate, in which each straight line segment of each bit line is electrically connected with at least two active pillars, and the insulating layers extend along the first direction and cover the outer peripheral surfaces of the active pillars, may include the following operations.

At S201, a plurality of active lines arranged at intervals are formed on the substrate. Each active line corresponds to and is electrically connected one bit line.

Specifically, referring to <FIG>, <FIG> and <FIG>, the plurality of active lines <NUM> arranged at intervals are formed by an etching process, in which the plurality of active lines <NUM> are parallel to each other. Each active line <NUM> corresponds to one bit line <NUM> and is electrically connected to the corresponding bit line <NUM> to achieve the electrical connection between the active line <NUM> and the bit line <NUM>.

Exemplarily, each active line <NUM> includes a plurality of first active segments extending in the second direction, and a plurality of second active segments extending in the third direction. One second active segment is connected with two adjacent first active segments. The first active segment corresponds to and is in contact with the first straight line segment of the bit line <NUM>, and the second active segment corresponds to and is in contact with the second straight line segment of the bit line <NUM>.

At S202, an initial insulating layer is formed on the substrate, and fills between adjacent active lines.

Still referring to <FIG> and <FIG>, an initial insulating layer <NUM> is deposited on the substrate <NUM>, and fills between the active lines <NUM> to isolate the active lines <NUM> from each other. Specifically, the initial insulating layer <NUM> is deposited to fill between and cover the active lines <NUM>. Then, the initial insulating layer <NUM> located on the active lines <NUM> is removed by etching to expose the active lines <NUM>.

At S203, part of the initial insulating layer and part of each active line are removed to form a plurality of first grooves arranged at intervals. The first grooves divide each active line into multiple active pillars. The remaining part of the initial insulating layer forms part of the first surrounding portion, and the first connecting portion connecting the first surrounding portion.

Referring to <FIG>, the initial insulating layer <NUM> and the active lines <NUM> are etched to form the plurality of first grooves <NUM> arranged at intervals. The first grooves <NUM> extend in the first direction, and divide each active line <NUM> into multiple active pillars <NUM>.

Specifically, part of the initial insulating layer <NUM> and part of the active line <NUM> are removed to form a plurality of initial grooves <NUM> arranged at intervals and extending in the first direction. As shown in <FIG>, the initial groove <NUM> exposes the substrate <NUM>, and has a substantially constant width equal in the first direction.

After the initial grooves <NUM> are formed, part exposed in the initial grooves <NUM> of the initial insulating layer <NUM> is removed to thin the initial insulating layer <NUM> located between adjacent initial grooves <NUM> to form the first grooves <NUM>. As shown in <FIG>, the initial insulating layer <NUM> exposed in the initial groove <NUM> is etched to thin the initial insulating layer <NUM>. The thinned initial insulating layer <NUM> forms the first connecting portion <NUM> (referring to <FIG>) and part of the first surrounding portion <NUM>. The surface area exposed in the initial grooves <NUM>, of the active pillar <NUM> is increased, and the enlarged initial grooves <NUM> serve as the first grooves <NUM>.

In some possible embodiments, as shown in <FIG>, taking the plane parallel to the substrate as a cross section, the cross section of the active pillar <NUM> is in a quadrilaterallike shape. For example, the cross section of the active pillar <NUM> is in a shape of a parallelogram or a rhombus. After the operation that the part exposed in the initial grooves <NUM>, of the initial insulating layer <NUM> is removed to thin the initial insulating layer <NUM> located between adjacent initial grooves <NUM> to form the first grooves <NUM>, the method further include an operation of removing part exposed in the first groove <NUM> of the active pillar <NUM> to fillet-transition the outer peripheral surface of the active pillar <NUM>.

Specifically, the active pillar <NUM> exposed in the first groove <NUM> is etched by a wet etching with an alkaline solution, so that the outer peripheral surface of each active pillar <NUM> is fillet-transitioned. As shown in <FIG>, the active pillar <NUM> is an approximate cylinder or an elliptic cylinder. The alkaline solution may be a potassium hydroxide solution or a SC1 solution. This solution has a faster reaction rate at sharp corners, which can make the corners of the active pillar <NUM> with the quadrilateral cross-sectional shape rounded, and make the dielectric layer <NUM> and the conductive layer <NUM> formed subsequently more uniform, improving the quality of the structure formed subsequently.

At S204, part of the first surrounding portion is formed on the outer peripheral surface exposed in the first groove, of the active pillar.

Specifically, part of the first surrounding portion <NUM> is formed on the outer peripheral surface of the active pillar <NUM> by a thermal oxidation process. The first surrounding portion <NUM> covering the outer peripheral surface of the active pillar <NUM> is formed by this operation and the previous operation.

In some possible embodiments, the method further includes an operation of forming a second support layer covering the conductive layer in the remaining part of the filling space, after the dielectric layer and the conductive layer are formed between the active pillars exposed in the filling space and close to the substrate to form the word line (S500).

Referring to <FIG>, the second support layer <NUM> is deposited on the conductive layer <NUM> and the dielectric layer <NUM> to insulate and isolate the conductive layer <NUM>. The second support layer <NUM> fills up the remaining part of the filling space <NUM>, and the surface away from the substrate <NUM>, of the active pillar <NUM> is exposed.

The material of the second support layer <NUM> may be the same as the material of the first support layer <NUM>, so that the second support layer <NUM> is integrated with the first support layer <NUM>, reducing or avoiding delamination or separation between the second support layer <NUM> and the first support layer <NUM>. The surface facing away from the substrate <NUM>, of the second support layer <NUM> may be flush with the surface facing away from the substrate <NUM>, of the first support layer <NUM>. By this arrangement, the first support layer <NUM> and the second support layer <NUM> form a flat surface, which is convenient for manufacturing other structures thereon.

In some possible embodiments, the method further includes an operation of, on each active pillar, forming a capacitor electrically connected to this active pillar, the capacitor being aligned with this corresponding active pillar, after the dielectric layer and the conductive layer are formed between the active pillars exposed in the filling space and close to the substrate to form the word line (S500).

Exemplarily, the bottom surface of the capacitor is in contact with and aligned with the top surface of the active pillar <NUM>, which realizes the electric connection between the capacitor and the active pillar <NUM> on the one hand, and ensures the contact area between the capacitor and the active pillar <NUM> on the other hand, thereby reducing the contact resistance between the capacitor and the active pillar <NUM>.

Embodiments of the disclosure also provide a memory. Referring to <FIG>, and <FIG> to <FIG>, the memory includes a substrate <NUM>, an active pillar <NUM>, an insulating layer <NUM>, a dielectric layer <NUM>, a conductive layer <NUM>, and a support layer. The substrate <NUM> is used for providing support, and may be a semiconductor substrate. The material of the semiconductor substrate may be one or more of silicon, germanium, silicon germanium, silicon carbide, Silicon on Insulator (SOI), Germanium on Insulator (GOI), or the like.

A plurality of bit lines <NUM> arranged at intervals are formed in the substrate <NUM> (referring to <FIG>). Each bit line <NUM> includes a plurality of straight line segments connected end to end in sequence, and adjacent line segments have an included angle therebetween, so that each bit line <NUM> is in a type of a zigzag line. Specifically, the plurality of straight line segments included by each bit line <NUM> include a plurality of first straight line segments <NUM> extending in a second direction and a plurality of second straight line segments <NUM> extending in a third direction. One second straight line segment <NUM> connects two first straight line segments <NUM> adjacent to this one second straight line segment, so that each bit line <NUM> is in form of a wavy polyline to make full use of the space of the substrate. Exemplarily, the included angle formed by the first direction and the second direction may be <NUM>° to <NUM>°, for example <NUM>°.

The plurality of active pillars <NUM> are formed on the substrate <NUM> and arranged at intervals. Each straight line segment of each bit line <NUM> is electrically connected with at least two active pillars <NUM>. For example, the active pillar <NUM> is in contact with the bit line <NUM> to achieve the electrical connection between the active pillar <NUM> and the bit line <NUM>. By electrically connecting multiple active pillars <NUM> with each straight line segment, it is avoided that each bit line <NUM> needs to be bent once every time it passes through one active pillar <NUM>, thereby reducing the bending number of each bit line <NUM> and reducing the manufacturing difficulty of the bit line <NUM>.

In some possible embodiments, the bit line <NUM> covers the orthographic projections of multiple active pillars <NUM> on the substrate <NUM>. By this arrangement, the entire bottom surface of the active pillar <NUM> is in contact with the bit line <NUM>, and the contact area between the active pillar <NUM> and the bit line <NUM> is large, thereby reducing the contact resistance between the active pillar <NUM> and the bit line <NUM>.

In other possible embodiments, taking the plane parallel to the substrate <NUM> as a cross section, multiple of active pillars <NUM> are arranged in a hexagonal close-packed structure. As shown in <FIG>, each seven active pillars <NUM> is regarded as a group, in which the centers of six active pillars <NUM> enclose into a virtual hexagon, i.e. the centers of the six active pillars <NUM> are respectively located at the six vertices of the virtual hexagon, and the center of the seventh active pillar <NUM> is located at the center of the virtual hexagon.

By this arrangement, the density of the active pillars <NUM> can be increased. When capacitors on the active pillars <NUM> are also arranged in the hexagonal close-packed structure, on the one hand, the density of the capacitors can be increased, thereby increasing the density of memories; on the other hand, the capacitor can be directly on the active pillar <NUM> without arranging a capacitor contact pad to transition the formation between the capacitor and the active pillar <NUM>, thereby reducing the complexity of manufacturing the memory. For example, when the active pillars <NUM> are arranged in a square structure, it is necessary to manufacture capacitor contact pads on the active pillars <NUM>, so as to arrange the capacitors in a hexagonal close-packed structure.

A plurality of insulating layers <NUM> are also formed on the substrate <NUM>, arranged at intervals and extend in the first direction. Each insulating layer <NUM> covers the outer peripheral surface of the lower region of the active pillar <NUM> in its extension direction. The lower region of the active pillar <NUM> refers to a region of the active pillar <NUM> close to the substrate <NUM>.

The dielectric layer <NUM> is formed on the outer peripheral surface of the middle region of the active pillar <NUM>. That is, the dielectric layer <NUM> covers the outer peripheral surface of the middle region of the active pillar <NUM>. A plurality of conductive layers <NUM> arranged at intervals are provided on the insulating layer <NUM>. A conductive layer <NUM> extends in the first direction and covers the outer peripheral surface of the dielectric layer <NUM>. The conductive layer <NUM> and the dielectric layer <NUM> form a word line.

In some possible embodiments, as shown in <FIG>, the included angle between the second direction and the first direction is <NUM>°, the included angle between the third direction and the first direction is <NUM>°, and a first pitch between adjacent word lines <NUM> is equal to a second pitch between adjacent bit lines <NUM>. By this arrangement, it is convenient to form the plurality of active pillars arranged in the hexagonal close-packed structure, reducing the difficulty of manufacturing the active pillars arranged in the hexagonal close-packed structure.

The support layer fills between the insulating layers <NUM>, between the conductive layers <NUM>, and between upper regions of the active pillars <NUM>. The support layer isolates each insulating layer <NUM>, each conductive layer <NUM>, and each active pillar <NUM>. Specifically, the support layer includes a first support layer <NUM> and a second support layer <NUM>. The first support layer <NUM> fills between the insulating layers <NUM>, between the conductive layers <NUM>, and extends between the upper regions of the active pillars <NUM>. The second support layer <NUM> fills between the first support layer <NUM> and the upper region of the active pillar <NUM>.

In the memory of the embodiments of the disclosure, each bit line <NUM> in the substrate <NUM> includes the plurality of straight line segments connected end to end in sequence, and adjacent straight line segments have the included angle therebetween. By forming the plurality of active pillars <NUM> that are arranged at intervals on the substrate <NUM> and staggered on the substrate <NUM>, the density of the active pillars <NUM> can be improved, which improves the performance of the memory. Each straight line segment of each bit line <NUM> is electrically connected with at least two active pillars <NUM>, which reduces the bending number of of each bit line <NUM> and facilitates the manufacture of the memory. In addition, the dielectric layer <NUM> and part of the conductive layer <NUM> form the gate covering the outer peripheral surface of the active pillar <NUM>, and the plurality of active pillars <NUM> are staggered on the substrate <NUM>, which increases the width of the gate in the radial direction of the active pillar <NUM>, thereby improving the forming quality of the gate, reducing the resistance of the gate and further improving the performance of the memory.

In this specification, embodiments or implementation modes are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments may be referred to each other.

In the description of this specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of this disclosure. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a proper manner.

Claim 1:
A method for manufacturing a memory, comprising:
providing a substrate (<NUM>), wherein a plurality of bit lines (<NUM>) arranged at intervals are formed in the substrate (<NUM>), each bit line (<NUM>) comprises a plurality of straight line segments (<NUM>, <NUM>) connected end to end in sequence, and adjacent straight line segments (<NUM>, <NUM>) have an included angle therebetween;
forming a plurality of active pillars (<NUM>) arranged at intervals and a plurality of insulating layers (<NUM>) arranged at intervals on the substrate (<NUM>), wherein each straight line segment (<NUM>, <NUM>) of each bit line (<NUM>) is electrically connected with at least two active pillars (<NUM>), and each insulating layer (<NUM>) extends in a first direction and covers an outer peripheral surface of the active pillar (<NUM>); characterized in that the method further comprises:
filling a first support layer (<NUM>) between adjacent insulating layers (<NUM>);
removing part away from the substrate (<NUM>), of the insulating layer (<NUM>) to form a filling space (<NUM>), wherein the filling space (<NUM>) exposes part of the outer peripheral surface of the active pillar (<NUM>); and
forming a dielectric layer (<NUM>) and a conductive layer (<NUM>) between parts exposed in the filling space (<NUM>) and close to the substrate (<NUM>), of the active pillars (<NUM>) to form a word line (<NUM>).