Patent Description:
A storage device refers to a device, which stores data under control of a host device, such as a computer, a smartphone, a smart pad, or the like. The storage device includes a device, which stores data on a magnetic disk, such as a hard disk drive (HDD), or a device, which stores data in a semiconductor memory, in particular, a nonvolatile memory, such as a solid state drive (SSD) or a memory card.

The nonvolatile memory includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc..

The degree of integration of the storage device and a volume thereof continues to increase as semiconductor manufacturing technologies advance. A high degree of integration of the storage device enables reduced costs necessary to manufacture the storage device. However, the high degree of integration of the storage device also causes scale-down and a structural change of the storage device. For example, damage to data stored in the storage device may occur, thereby decreasing the reliability of the storage device. Accordingly, there is a continuous demand for improving the reliability of the storage device. <CIT> discloses a nonvolatile memory which includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. <CIT> an apparatus including a processor for sending a first command to a memory to instruct storage of data in a Single-Level Cell (SLC) area of the memory if a function requiring high-speed storage of large amounts of data is selected.

The present invention provides a storage device according to the appended claims. Embodiments of the concepts in the present disclosure provide a storage device and a computing device capable of preventing an error from occurring in memory blocks of a buffer area due to frequent erase operations when some memory blocks are used as the buffer area.

According to an embodiment, a storage device includes a nonvolatile memory device, the nonvolatile memory device comprising a plurality of memory blocks, the plurality of memory blocks comprising first memory blocks configured to store data received from a host device and second memory blocks configured as a buffer area for writing the data received from the host device to the first memory blocks, and a controller that determines that a period of time between a time of erasing data stored in the second memory blocks of the buffer area from the second memory blocks and a current time exceeds a predetermined time, and writes the data received from the host device to the second memory blocks of the buffer area based on determining that the period of time exceeds the predetermined time.

According to an embodiment, a storage device includes a nonvolatile memory device, the nonvolatile memory device comprising a plurality of memory blocks configured as a user area comprising first memory blocks among the plurality of memory blocks and a buffer area comprising second memory blocks among the plurality of memory blocks, and a controller that receives a write command to write data to the nonvolatile memory device, the write command comprising a turbo write command of a turbo write operation to write the data into the user area through the buffer area, writes the data to the nonvolatile memory device through the buffer area according to the turbo write operation of the turbo write command based on identifying that a size of the data does not exceed an available buffer size of the buffer area, the available buffer size of the buffer area comprising a size of available memory blocks among the second memory blocks of which a period of time between a time of erasing stored data stored in the available memory blocks of the buffer area from the available memory blocks and a current time exceeds a predetermined time, and writes the data to the nonvolatile memory device according to a normal write operation of a normal write command to write the data directly into the user area based on identifying that the size of the data exceeds the available size of the buffer.

According to an embodiment, a computing device includes a storage device, the storage device comprising a user area comprising first memory blocks among memory blocks of the storage device and a buffer area comprising second memory blocks among the memory blocks of the storage device, the storage device configured to output an available size of the buffer area, the available buffer size of the buffer area comprising a size of available memory blocks among the second memory blocks of which a period of time between a time of erasing stored data stored in the available memory blocks of the buffer area from the available memory blocks and a current time exceeds a predetermined time, and a processor that transmits to the storage device a turbo write request to perform a turbo write operation to store data having a size less than or equal to the available buffer size in the user area via the buffer area and transmits to the storage device a normal write request to perform a normal write operation to store data having a size greater than the available buffer size directly into the user area.

The storage device the nonvolatile memory device may comprise: a plurality of memory blocks configured as a user area comprising first memory blocks among the plurality of memory blocks and a buffer area comprising second memory blocks among the plurality of memory blocks.

The controller may be configured to: receive a write command to write data to the nonvolatile memory device, the write command comprising a turbo write command of a turbo write operation to write the data into the user area through the buffer area.

The controller may be configured to: write the data to the nonvolatile memory device through the buffer area according to the turbo write operation of the turbo write command based on identifying that a size of the data does not exceed an available buffer size of the buffer area, the available buffer size of the buffer area comprising a size of available memory blocks among the second memory blocks of which a period of time between a time of erasing stored data stored in the available memory blocks of the buffer area from the available memory blocks and a current time exceeds a predetermined time.

The controller may be configured to: write the data to the nonvolatile memory device according to a normal write operation of a normal write command to write the data directly into the user area based on identifying that the size of the data exceeds the available size of the buffer area.

The present disclosure also provides a computing device comprising: the storage device according to any aspect or embodiment as disclosed herein.

The above and other objects and features of the concepts will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

Below, embodiments may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the concepts described herein.

<FIG> illustrates a storage device <NUM> according to an embodiment. Referring to <FIG>, the storage device <NUM> may include a nonvolatile memory device <NUM> and a controller <NUM>.

The nonvolatile memory device <NUM> is configured to perform a write operation, a read operation, and an erase operation under control of the controller <NUM>. The nonvolatile memory device <NUM> may include a plurality of memory blocks that are configured to store data. For example, the nonvolatile memory device <NUM> may include first to twentieth memory blocks BLK1 to BLK20. However, the number of memory blocks included in the nonvolatile memory device <NUM> is merely an example, and the nonvolatile memory device <NUM> may include any number of memory blocks.

The nonvolatile memory device <NUM> may perform the erase operation in the unit of a memory block. For example, the nonvolatile memory device <NUM> may independently erase the first to twentieth memory blocks BLK1 to BLK20 under control of the controller <NUM>.

Each of the first to twentieth memory blocks BLK1 to BLK20 may include a plurality of memory cells. The nonvolatile memory device <NUM> may perform the write operation and the read operation in a unit smaller than a memory block. For example, under control of the controller <NUM>, the nonvolatile memory device <NUM> may select some of memory cells of a certain memory block and may perform the write operation or the read operation on the selected memory cells.

The controller <NUM> may control the nonvolatile memory device <NUM> under control of an external host device. For example, the controller <NUM> may direct the nonvolatile memory device <NUM> to perform the read operation, the write operation, or the erase operation. The controller <NUM> may set, partition, or otherwise configure a portion of the first to twentieth memory blocks BLK1 to BLK20 of the nonvolatile memory device <NUM> as a user area <NUM> and may utilize the remaining portion thereof as a buffer area <NUM>.

For example, the controller <NUM> may select the first to sixteenth memory blocks BLK1 to BLK16 as the user area <NUM> and may select the seventeenth to twentieth memory blocks BLK17 to BLK20 as the buffer area <NUM>. The controller <NUM> may provide a storage space of the first to sixteenth memory blocks BLK1 to BLK16 of the user area <NUM> to the external host device.

The controller <NUM> may provide a storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> as a buffer of the user area <NUM>. For example, the controller <NUM> may not provide the storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> to be accessible for storage to the external host device. It will be appreciated that the ratio of buffer area <NUM> to user area <NUM> and/or number of buffer area <NUM> memory blocks may be any desired.

The controller <NUM> may include a buffer size block <NUM>, a migration block <NUM>, a memory interface block <NUM>, and a host interface block <NUM>. The buffer size block <NUM>, the migration block <NUM>, the memory interface block <NUM>, and the host interface block <NUM> may be modules of the controller <NUM> configured to execute operations of the controller <NUM>.

The buffer size block <NUM> may identify a currently usable capacity of the storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM>. For example, the controller <NUM> may identify storage space available in the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM>, in which data is not written, as an available buffer size. The identification of the storage space available in the buffer area may be in response to a request of the external host device or carried out periodically.

The migration block <NUM> may migrate valid data written into the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> to the user area <NUM>. The migration of valid data may be carried out in response to a request of the external host device or after a predetermined at an idle time. The data that are migrated from the buffer area <NUM> to the user area <NUM> may be invalidated in the buffer area <NUM> and may be identified as invalid or dirty data. Invalid data may be data which has been previously read and/or migrated from the memory block and requires erasing. The invalid data may be redundant data.

In response to a request of the external host device or in compliance with an internal schedule, the memory interface block <NUM> may provide a command, an address, or data to the nonvolatile memory device <NUM> such that the nonvolatile memory device <NUM> performs the write operation, the read operation, or the erase operation.

The host interface block <NUM> may receive various requests from the external host device. The host interface block <NUM> may parse requests received from the external host device. Based on a result of the parsing, the host interface block <NUM> may control the nonvolatile memory device <NUM> or may provide information to the external host device. For example, the host interface block <NUM> may provide the available buffer size identified by the buffer size block <NUM> to the external host device.

<FIG> illustrates a method of operating the storage device <NUM> according to an embodiment. Referring to <FIG> and <FIG>, in operation S <NUM>, the host interface block <NUM> of the controller <NUM> may receive a command CMD, an address ADDR, and data DATA from the external host device. For example, the command CMD may be a write command, a read command, or an erase command.

The address ADDR may indicate a location where the data DATA is to be stored. For example, the location where data DATA is to be stored may be a location on the user area <NUM> of the nonvolatile memory device <NUM>. The data DATA may be write data that the external host device intends to write into the nonvolatile memory device <NUM>.

In operation S120, the memory interface block <NUM> of the controller <NUM> may write the data DATA into the buffer area <NUM>. For example, a location on the buffer area <NUM>, at which the data DATA will be written, may be unrelated to the address ADDR at which the data DATA will ultimately be written in the user area <NUM>. The nonvolatile memory device <NUM> may write the data DATA by using memory cells of the buffer area <NUM> as single level cells SLC, thus improving a speed of writing the data to the nonvolatile memory device <NUM>.

In operation S130, when a migration request is received from the external host device or at an idle time when a request from the external host device does not exist, the migration block <NUM> of the controller <NUM> may initiate data migration. Under control of the migration block <NUM>, the controller <NUM> may migrate (or move) data written into the buffer area <NUM> to the location on the user area <NUM> indicated by the address ADDR.

For example, the memory interface block <NUM> of the controller <NUM> may transmit a read command and an address of the buffer area <NUM> to the nonvolatile memory device <NUM> and may read the data DATA written into the buffer area <NUM>. Afterwards, the memory interface block <NUM> of the controller <NUM> may transmit a write command and the address ADDR to the nonvolatile memory device <NUM> and may write the data DATA into the user area <NUM>.

In operation S140, the buffer size block <NUM> of the controller <NUM> may detect (or identify) the available buffer size of the buffer area <NUM> based on a reuse time, when a request is received from the external host device or periodically (or at a certain period). The reuse time may relate to a time at which a memory block may be reused. The reuse time may be defined in relation to a previous erase time. That is, the reuse time may be a time after the previous erase operation.

For example, the data DATA of the buffer area <NUM> may be invalidated by moving the data DATA from the buffer area <NUM> to the user area <NUM> in operation S130. Memory blocks of the buffer area <NUM>, which stored the data DATA, may be invalid memory blocks.

The buffer size block <NUM> may identify a capacity of memory blocks, in which an erase operation is currently possible and data are able to be written, from among the invalid memory blocks of the buffer area <NUM>, as the available buffer size. The available buffer size may not coincide with the total capacity of the invalid memory blocks of the buffer area <NUM>. The buffer size block <NUM> may determine whether any of the invalid memory blocks is included in the available buffer size and any is not included in the available buffer size, by using the reuse time.

In operation S150, the host interface block <NUM> of the controller <NUM> may report to the external host device on the available buffer size. Operation S140 and operation S150 may be sequentially performed in response to a request of the host device that requests the available buffer size.

<FIG> illustrates a method of identifying an available buffer size according to an embodiment. Referring to <FIG>, in operation S141, the buffer size block <NUM> may determine whether a time (e.g., an elapsed time) that elapses after a certain invalid memory block of the seventeenth to twentieth memory blocks BLK17 to BLK20 in the buffer area <NUM> is erased is greater than the reuse time.

When the elapsed time is greater than the reuse time, in operation S142, the certain invalid memory block may be identified as an available memory block that is available for storing data in the buffer area <NUM>. A capacity of the invalid memory block marked as available may be included in calculation of the available buffer size. When the elapsed time is not greater than the reuse time, in operation S143, the invalid memory block may be identified as an unavailable memory block that is unavailable for storing data in the buffer area <NUM>. The capacity of the invalid memory block marked as unavailable may not be included in calculation of the available buffer size.

In general, a memory cell, for example, a flash memory cell has a structure in which a body, a tunneling insulating layer, an information storage layer, a blocking insulating layer, and a control gate are stacked. In the write operation, a high voltage is applied to the control gate, and a low voltage is applied to the body. According to this write bias condition, charges of the body are injected into the information storage layer through the tunneling insulating layer. This injection of the charges may make a threshold voltage of a memory cell high.

In the erase operation, the low voltage is applied to the control gate, and the high voltage is applied to the body. According to this erase bias condition, charges of the information storage layer are pulled off and transferred to the body through the tunneling insulating layer. This transfer of the charges may lower a threshold voltage of a memory cell.

When the write operation or the erase operation is performed, some charges may be trapped in the tunneling insulating layer or the blocking insulating layer. The charges that are trapped in the tunneling insulating layer or the blocking insulating layer are discharged over time. That is, the charges trapped in the tunneling insulating layer or the blocking insulating layer may have an influence on a threshold voltage of a memory cell immediately after the write operation or the erase operation is performed.

When the charges that are trapped in the tunneling insulating layer or the blocking insulating layer are discharged over time, the threshold voltage of the memory cell may change due to presence of the trapped charges. The process in which the charges that are trapped in the tunneling insulating layer or the blocking insulating layer are discharged may be considered as the memory cell is cured or stabilized.

When the write operation and the erase operation are performed on a certain memory block, the curing or stabilization may cause a first change in threshold voltages of memory cells in the certain memory block as much as a first level. In the case that the erase operation or the write operation is again performed before the curing or stabilization of the certain memory block is completed, in addition to the first change in threshold voltages caused in the previous erase and write operations, the current write and erase operations accompanying the curing or stabilization may cause a second change in threshold voltages.

As such, the first change and the second change are accumulated, thereby causing a greater change in the threshold voltages of the memory cells. As the change in the threshold voltages of the memory cells increases (or as a shift of the threshold voltages of the memory cells becomes greater), the probability that an uncorrectable error occurs in data written into the certain memory block may also increase.

In particular, as an example considering the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM>, in the case that the limited number of memory blocks are used to store a single bit per memory cell, the probability that the erase operation and the write operation are triggered before the curing or stabilization is completed may be with regard to the memory blocks BLK17 to BLK20 of the buffer area <NUM>.

For example, before the curing or stabilization of the buffer area <NUM> is completed, the external host device may intend to write data into the buffer area <NUM>, to migrate the written data to the user area <NUM>, and to further write any other data into the buffer area <NUM>.

The storage device <NUM> according to an embodiment may include a memory block, of which the elapsed time after erase is greater than the reuse time, from among the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> in the available buffer size. For example, the elapsed time may be a time over which charges that are trapped in the tunneling insulating layer or the blocking insulating layer are likely to be discharged over time. The elapsed time may be a predetermined time against which availability or unavailability of the memory block is judged. The storage device <NUM> may exclude a memory block, of which the elapsed time after erase is not greater than the reuse time, from the available buffer size. Accordingly, a memory block in which charges that are trapped in the tunneling insulating layer or the blocking insulating layer may not have been discharged over time is not be included in the calculation of the available buffer size.

The reuse time may be determined based on a time when the seventeenth to twentieth memory blocks BLK17 to BLK20 are cured or stabilized. Such memory blocks may be indicated as available memory blocks. That is, the storage device <NUM> may support a fast write operation by using the buffer area <NUM> for those memory blocks indicated as available and may secure the curing or stabilization of the buffer area <NUM> for those memory blocks indicated as unavailable, and thus, the reliability of the storage device <NUM> is improved.

<FIG> illustrate how the storage device <NUM> manages the buffer area <NUM> based on the reuse time. <FIG> illustrates a state of a storage device before storing in the buffer area <NUM>. Referring to <FIG>, the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> may be invalid memory blocks storing invalid data INV.

The buffer size block <NUM> may manage a time stamp TS of each of the seventeenth to twentieth memory blocks BLK17 to BLK20. The time stamp TS may indicate a time when each of the seventeenth to twentieth memory blocks BLK17 to BLK20 is previously erased. It is assumed that the curing or stabilization of the seventeenth to twentieth memory blocks BLK17 to BLK20 is completed. That is, the time stamp TS of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 and an elapsed time calculated from a current time may be greater than the reuse time. Therefore, the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> may be indicated as available memory blocks.

The buffer size block <NUM> may further manage the available buffer size. Because the curing or stabilization of the seventeenth to twentieth memory blocks BLK17 to BLK20 is completed, the available buffer size may be "<NUM>" (meaning a size of four memory blocks). However, the available buffer size is not limited to the number of memory blocks. The available buffer size may be expressed by a capacity of data to be actually written, such as B, KB, MB, GB, or TB.

<FIG> illustrates a state of a storage device in which data are written into a portion of the buffer area <NUM>. The host interface block <NUM> of the controller <NUM> may receive a first command CMD1, a first address ADDR1, and first data DATA1 from the external host device. The first command CMD1 may be a write command. The first address ADDR1 may correspond to, for example, memory block thirteen BLK13 of the user area <NUM>.

In operation S211, the memory interface block <NUM> of the controller <NUM> may transmit an erase command and an address indicating the seventeenth and eighteenth memory blocks BLK17 and BLK18 of the buffer area <NUM> to the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may erase the seventeenth and eighteenth memory blocks BLK17 and BLK18.

In operation S212, when the seventeenth and eighteenth memory blocks BLK17 and BLK18 are erased, the buffer size block <NUM> may generate a first time stamp TS1 of a time when the seventeenth and eighteenth memory blocks BLK17 and BLK18 are erased and may record the first time stamp TS1 in association with the seventeenth and eighteenth memory blocks BLK17 and BLK18. For example, the buffer size block <NUM> may store the time stamp TS in association with the corresponding memory block in a lookup table, a register, or any other storage mechanism.

In operation S213, the memory interface block <NUM> of the controller <NUM> may transmit a write command, an address indicating the seventeenth and eighteenth memory blocks BLK17 and BLK18 of the buffer area <NUM>, and the first data DATA1 to the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may write the first data DATA1 into the seventeenth and eighteenth memory blocks BLK17 and BLK18. The seventeenth and eighteenth memory blocks BLK17 and BLK18 may be indicated as valid memory blocks storing valid data VAL.

In operation S214, because the seventeenth and eighteenth memory blocks BLK17 and BLK18 become valid memory blocks, the buffer size block <NUM> may decrease the available buffer size. For example, the available buffer size may decrease to "<NUM>" corresponding to only the nineteenth and twentieth memory blocks BLK19 and BLK20 being invalid memory blocks that are available.

<FIG> illustrates a state of a storage device in which data are written into a remainder of the buffer area <NUM>. The host interface block <NUM> of the controller <NUM> may receive a second command CMD2, a second address ADDR2, and second data DATA2 from the external host device. The second command CMD2 may be a write command. The second address ADDR2 may correspond to, for example, the fourteenth memory block BLK14 of the user area <NUM>.

In operation S221, the memory interface block <NUM> of the controller <NUM> may transmit an erase command and an address indicating the nineteenth and twentieth memory blocks BLK19 and BLK20 of the buffer area <NUM> to the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may erase the nineteenth and twentieth memory blocks BLK19 and BLK20.

In operation S222, when the nineteenth and twentieth memory blocks BLK19 and BLK20 are erased, the buffer size block <NUM> may generate a second time stamp TS2 of when the nineteenth and twentieth memory blocks BLK19 and BLK20 are erased and may record the second time stamp TS2 in association with the nineteenth and twentieth memory blocks BLK19 and BLK20.

In operation S223, the memory interface block <NUM> of the controller <NUM> may transmit a write command, an address indicating the nineteenth and twentieth memory blocks BLK19 and BLK20 of the buffer area <NUM>, and the second data DATA2 to the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may write the second data DATA2 into the nineteenth and twentieth memory blocks BLK19 and BLK20. The nineteenth and twentieth memory blocks BLK19 and BLK20 may be valid memory blocks storing valid data VAL.

In operation S224, because the nineteenth and twentieth memory blocks BLK19 and BLK20 become valid memory blocks, the buffer size block <NUM> may decrease the available buffer size. For example, because all memory blocks of the buffer area <NUM> are valid memory blocks, the available buffer size may decrease to "<NUM>.

<FIG> illustrates a state of a storage device in which data written into the buffer area <NUM> is migrated to the user area <NUM>. Referring to <FIG>, the migration block <NUM> of the controller <NUM> may initiate a migration operation in response to a request of the external host device or at an idle time when a command from the external host device does not exist.

In operation S231, the memory interface block <NUM> may transmit a read command and an address indicating the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> to the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may read the first data DATA1 from the seventeenth and eighteenth memory blocks BLK17 and BLK18 and may read the second data DATA2 from the nineteenth and twentieth memory blocks BLK19 and BLK20. The nonvolatile memory device <NUM> may transmit the first data DATA1 and the second data DATA2 to the controller <NUM>.

In operation S232, the memory interface block <NUM> may transmit a write command, the first address ADDR1 indicating the thirteenth memory block BLK13, and the first data DATA1 to the nonvolatile memory device <NUM>. Also, the memory interface block <NUM> may transmit a write command, the second address ADDR2 indicating the fourteenth memory block BLK14, and the second data DATA2 to the nonvolatile memory device <NUM>.

The nonvolatile memory device <NUM> may write the first data DATA1 into the thirteenth memory block BLK13 and may write the second data DATA2 into the fourteenth memory block BLK14. For example, the memory interface block <NUM> may utilize memory cells of the thirteenth and fourteenth memory blocks BLK13 and BLK14 of the user area <NUM> as multi-level cells MLC.

However, the memory cells of the user area <NUM> are not limited to multi-level cells MLC. The memory cells of the user area <NUM> may be utilized as triple level cells TLC or quadruple level cells QLC.

As the first data DATA1 and the second data DATA2 migrate, the first data DATA1 and the second data DATA2 written into the buffer area <NUM> are invalidated. The seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area <NUM> may be invalid memory blocks storing invalid data INV. The thirteenth and fourteenth memory blocks BLK13 and BLK14 of the user area <NUM> may be valid memory blocks storing valid data VAL.

In operation S233 and operation S234, in response to a request of the external host device or in compliance with an internal schedule (e.g., periodically or when a certain condition is satisfied), the buffer size block <NUM> may compare a time stamp of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 (following an erase of blocks BLK17 to BLK20) with a current time and may determine the available buffer size based on a result of the comparison.

For example, in operation S233, the seventeenth and eighteenth memory blocks BLK17 and BLK18 have the first time stamp TS1. A difference between the first time stamp TS1 and the current time, that is, an elapsed time ET1 of the seventeenth and eighteenth memory blocks BLK17 and BLK18 may be greater than the reuse time. Thus, the memory blocks BLK17 and BLK18 may be indicated as available.

In contrast, in operation S234, the nineteenth and twentieth memory blocks BLK19 and BLK20 have the second time stamp TS2. A difference between the second time stamp TS2 and the current time, that is, an elapsed time ET2 of the nineteenth and twentieth memory blocks BLK19 and BLK20 may be not greater than the reuse time. Thus, the memory blocks BLK19 and BLK20 may be indicated as unavailable.

The buffer size block <NUM> may identify the seventeenth and eighteenth memory blocks BLK17 and BLK18 as available memory blocks of the buffer area <NUM> and may identify the nineteenth and twentieth memory blocks BLK19 and BLK20 as unavailable memory blocks of the buffer area <NUM>. Accordingly, the number of invalid memory blocks of the buffer area <NUM> may be "<NUM>"; however, in operation S235, the available buffer size identified by the buffer size block <NUM> may be "<NUM>.

In operation S236, the host interface block <NUM> may report the available buffer size to the external host device. For example, the identification and report of the available buffer size may be performed in response to one identical command or different, separate commands, which are provided from the external host device.

<FIG> illustrates a state of a storage device which determines an available buffer size. Referring to <FIG>, in response to a request of the external host device or in compliance with an internal schedule (e.g., periodically or when a certain condition is satisfied), the buffer size block <NUM> may compare a time stamp of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 with a current time and may determine an available buffer size based on a result of the comparison.

For example, in operation S241, the nineteenth and twentieth memory blocks BLK19 and BLK20 have the second time stamp TS2. A difference between the second time stamp TS2 and the current time, that is, an elapsed time ET2 of the nineteenth and twentieth memory blocks BLK19 and BLK20 may be greater than the reuse time.

The nineteenth and twentieth memory blocks BLK19 and BLK20 may be identified as available memory blocks of the buffer area <NUM>. Accordingly, in operation S242, the available buffer size identified by the buffer size block <NUM> may be "<NUM>.

In operation S243, the host interface block <NUM> may report the available buffer size to the external host device. For example, the identification and report of the available buffer size may be performed in response to one identical command or different, separate commands, which are provided from the external host device.

<FIG> illustrates a method of the storage device <NUM> performing write operations for the user area <NUM> and the buffer area <NUM>. Referring to <FIG> and <FIG>, in operation S310, the host interface block <NUM> of the controller <NUM> may receive the command CMD, the address ADDR, and the data DATA from the external host device. The command CMD may be a write command. The address ADDR may indicate a certain storage location of the user area <NUM>.

In operation S320, the host interface block <NUM> may determine whether the received command CMD is a turbo write command. When the received command CMD is the turbo write command, in operation S330 and operation S340, the controller <NUM> may perform a turbo write operation of writing the data DATA relatively quickly.

For example, in operation S330, the memory interface block <NUM> may write the received data DATA into the buffer area <NUM>. Because the memory cells of the buffer area <NUM> are used as single level cells SLC, a speed at which the data DATA are written may be relatively fast. Afterwards, in operation S340, in response to a request of the external host device or at an idle time, the memory interface block <NUM> may migrate the data DATA written into the buffer area <NUM> to the user area <NUM> based on the address ADDR.

When it is determined in operation S320 that the received write command is not the turbo write command, that is, the received write command is a typical/normal write command, operation S350 is performed. In operation S350, the controller <NUM> may perform a normal write operation of writing the data DATA to memory, which may be slower than the turbo write operation. The memory interface block <NUM> may directly write the data DATA into the user area <NUM> based on the address ADDR, without using the buffer area <NUM>.

That is, the storage device <NUM> may allow the host device to select the turbo write operation that uses the buffer area <NUM> and the normal write operation that does not use the buffer area <NUM>. When a large amount of write data is generated, for example in the case of storing image data, the external host device may select the turbo write operation to perform fast data processing. When the small amount of write data is generated, for example in the case of storing document data, the external host device may select the normal write operation to allow a margin for a resource of the buffer area <NUM>. Alternatively, the storage device <NUM> may control whether to select the turbo write operation and the normal write operation, based on the available size of the buffer area <NUM> and the size of the data DATA. If the size of the data DATA is less than the available size of the buffer, then the storage device <NUM> may perform a turbo write operation. If the size of the data DATA is greater than the available size of the buffer, then the storage device may perform a normal write operation. Alternatively, if the size of the data DATA is greater than the available size of the buffer, then the storage device may split the data DATA, and perform a turbo write operation on a portion of the data DATA and a normal write operation on a portion of the data DATA, as will described with respect to <FIG>.

<FIG> illustrates a storage device <NUM> according to an embodiment. Referring to <FIG>, the storage device <NUM> includes a nonvolatile memory device <NUM>, a controller <NUM>, and a random access memory <NUM>.

As described with reference to <FIG>, the nonvolatile memory device <NUM> may include a user area <NUM> and a buffer area <NUM>. As described with reference to <FIG>, the controller <NUM> may include a buffer size block <NUM>, a migration block <NUM>, a memory interface block <NUM>, and a host interface block <NUM>. In addition, the controller <NUM> may further include a memory controller <NUM>.

The memory controller <NUM> may be configured to control the random access memory <NUM>. The storage device <NUM> may use the random access memory <NUM> as a buffer between the nonvolatile memory device <NUM> and the external host device. The controller <NUM> may store data received from the external host device into the random access memory <NUM>.

The controller <NUM> may write data stored in the random access memory <NUM> into the nonvolatile memory device <NUM>. In this case, as described with reference to <FIG>, the controller <NUM> may select one of the turbo write operation and the normal write operation. The buffer size block <NUM> may identify the available buffer size of the buffer area <NUM> as described with reference to <FIG>.

The controller <NUM> may not provide the available buffer size to the external host device and may internally use the available buffer size. The controller <NUM> may refer to the available buffer size when writing the write data stored in the random access memory <NUM> into the buffer area <NUM> through the turbo write operation. For example, the controller <NUM> may write data, the size of which is less than or equal to the available buffer size, into the buffer area <NUM> through the turbo write operation.

The controller <NUM> may store data read from the nonvolatile memory device <NUM> into the random access memory <NUM>. The controller <NUM> may transmit the data stored in the random access memory <NUM> to the external host device.

<FIG> illustrates a computing device <NUM> according to an embodiment. Referring to <FIG>, the computing device <NUM> may be implemented as a mobile device such as a smartphone, a smart pad, or a notebook computer, or a fixed device such as a computer, a workstation, or a server.

The computing device <NUM> includes a processor <NUM>, a random access memory <NUM>, a modem <NUM>, a user interface <NUM>, and a storage device <NUM>. The processor <NUM> may execute an operating system necessary to drive the computing device <NUM>, and various applications executable on the operating system. The processor <NUM> may be a host device of the storage device <NUM>.

For example, the processor <NUM> may read program codes of the operating system and the applications from the storage device <NUM> and may store the loaded codes into the random access memory <NUM>. The processor <NUM> may execute the operating system and the applications by executing the codes stored in the random access memory <NUM>. The processor <NUM> may include a central processing unit (CPU) or an application processor (AP).

The random access memory <NUM> may be used as a system memory or a working memory of the computing device <NUM>. The random access memory <NUM> may store various codes to be executed by the processor <NUM>. The random access memory <NUM> may store user data that are generated by the operating system or the applications of the processor <NUM>.

The random access memory <NUM> may store data received from an external device through the modem <NUM> or data to be transmitted to the external device through the modem <NUM>. The random access memory <NUM> may store data input from an external user through the user interface <NUM> or data to be output to the external user through the user interface <NUM>.

The random access memory <NUM> may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc..

The modem <NUM> is a communication interface configured to perform wired or wireless communication with an external device. The modem <NUM> may communicate with the external device based on at least one of various standards such as Ethernet, long term evolution (LTE), <NUM>th generation (<NUM>) mobile communication, wireless-fidelity Bluetooth, and near field communication (NFC).

The user interface <NUM> is configured to exchange information with the user. The user interface <NUM> may include user input devices, which are able to receive information from a user, such as a keyboard, a mouse, a touch pad, a touch panel, a microphone. The user interface <NUM> may include user output devices, which are able to provide information to the user, such as a monitor, a beam projector, a speaker, and a motor.

The storage device <NUM> may be used to store the codes of the operating system and the applications, and user data. The storage device <NUM> may be a disk and may include the storage device <NUM> described with reference to <FIG>. The storage device <NUM> may identify memory blocks, of which the elapsed time after erase is greater than the reuse time, from among invalid memory blocks of the buffer area <NUM> or <NUM> as an available buffer.

As described with reference to <FIG>, the storage device <NUM> may identify the available buffer size and may report to the processor <NUM> on the available buffer size. The processor <NUM> may select one of the turbo write operation and the normal write operation, based on the available buffer size. The processor <NUM> may write data into the storage device <NUM> through the selected write operation.

As described with reference to <FIG>, the storage device <NUM> may not separately report to the processor <NUM> on the available buffer size. The processor <NUM> may request a write operation from the storage device <NUM> without separation of the turbo write operation and the normal write operation.

The storage device <NUM> may store write data into the random access memory <NUM>. When writing the data stored in the random access memory <NUM> into the nonvolatile memory device <NUM>, the storage device <NUM> may select one of the turbo write operation and the normal write operation based on the available buffer size.

<FIG> illustrates a method of storing data performed between the processor <NUM> and the storage device <NUM>. In <FIG>, the storage device <NUM> includes the storage device <NUM> described with reference to <FIG>. Referring to <FIG>, <FIG>, and <FIG>, in operation S410 and operation S412, the processor <NUM> and the storage device <NUM> may perform a provisioning operation.

For example, in operation S410, the processor <NUM> may request provisioning of the buffer area <NUM> from the storage device <NUM>. The request of operation S410 may be performed by using a query request UFS protocol information unit (UPIU) based on a universal flash storage (UFS). The processor <NUM> may transmit a write descriptor query request UPIU to the storage device <NUM>.

The write descriptor query request UPIU may include mode information, size information, and logical unit (LU) information. The mode information may indicate a way to generate the buffer area <NUM> and may include a reduction mode and a non-reduction mode.

The size information may include information about the size of the buffer area <NUM>. The LU information may indicate whether all LUs share the buffer area <NUM> in a state that the buffer area <NUM> is implemented with one LU of the storage device <NUM> or whether the buffer area <NUM> is implemented in each of LUs of the storage device <NUM>. In operation S412, the storage device <NUM> may transmit a response UPIU to the processor <NUM>. For example, the response UPIU may include an available buffer size of a buffer area.

<FIG> illustrate diagrams in which a provisioning operation is performed. For example, <FIG> illustrates a diagram in which a buffer area is allocated in a reduction mode when the storage device <NUM> does not have an overprovision (OP) area.

Referring to <FIG> and <FIG>, a storage space of the storage device <NUM> may be divided into a meta area and a user area. The meta area may be used for the storage device <NUM> to store metadata (e.g., a mapping table of logical addresses and physical addresses) necessary to manage the storage device <NUM>. The meta area may not be accessible to the external host device (e.g., the processor <NUM>).

The user area may be an area that the storage device <NUM> is accessible to the processor <NUM> and may be accessed for the processor <NUM> to write data. When the computing device <NUM> is initialized (or booted up), the storage device <NUM> may provide capacity information of the user area to the processor <NUM>.

In the provisioning operation S410, the processor <NUM> may provide size information of the buffer area to the storage device <NUM>. The storage device <NUM> may allocate an area, which corresponds to the size information, of the user area for the buffer area. That is, in the reduction mode, the size of the user area may be decreased to be smaller than an original size when the provisioning operation is performed. The buffer area may be allocated to be equal in size to the decrement of the user area.

The size of the buffer area may be fixed. Memory blocks that are selected as the buffer area may be physically fixed. That is, when rebooting and re-provisioning are performed, previously selected memory blocks may be consistently selected as the buffer area. According to the example of <FIG>, a user area, which is allocated to write data, of the storage device <NUM> may decrease, while a buffer area supporting the turbo write operation may be stably secured.

<FIG> illustrates a diagram in which a buffer area is allocated in the non-reduction mode when the storage device <NUM> does not have an overprovision (OP) area. Referring to <FIG> and <FIG>, in the provisioning operation, size information may include a maximum size of a buffer area. The size of the buffer area may vary with the size information.

The storage device <NUM> may provide an original size of a user area to the processor <NUM>. The storage device <NUM> may adaptively or dynamically allocate a buffer area within the user area. For example, the storage device <NUM> may allocate memory blocks of the user area, in which data are not written, as the buffer area.

When data written in the user area do not exist, the storage device <NUM> may allocate the buffer area to have the maximum size. As data are written into the user area, the storage device <NUM> may decrease the size of the buffer area. For example, as a filling rate of the user area increases, the storage device <NUM> may decrease the size of the buffer area.

The buffer area may decrease to the minimum size of the size information. For example, the minimum size may be automatically determined by the storage device <NUM>. As a filling rate of the user area decreases, the storage device <NUM> may increase the size of the buffer area. The storage device <NUM> may adaptively or dynamically select memory blocks to be included in the buffer area.

For example, the storage device <NUM> may adaptively select memory blocks to be included in the buffer area with reference to the age or degree of usage of the storage device <NUM> and the number of program/erase cycles of each of memory blocks. Memory blocks having the low (or high) degree of usage or the small (or large) number of program/erase cycles may be included in the buffer area.

The storage device <NUM> may differently manage a certain memory block, based on whether the certain memory block is included in the buffer area. For example, the storage device <NUM> may manage parameters such as a read count and the number of program/erase cycles of a memory block and may manage data by using the parameters.

The storage device <NUM> may differently set a weight to be applied to a read count and a weight to be applied to the number of program/erase cycles, based on whether a certain memory block is included in the buffer area. For example, a smaller (or greater) weight may be applied to a read count of a memory block belonging to the buffer area, and a smaller (or greater) weight may be applied to the number of program/erase cycles of the memory block belonging to the buffer area.

As described with reference to <FIG>, the processor <NUM> may select the non-reduction mode to perform the provisioning operation, thus effectively utilizing the original size of the user area of the storage device <NUM>.

<FIG> illustrates a diagram in which a buffer area is allocated in a reduction mode when the storage device <NUM> has an overprovision (OP) area. Referring to <FIG> and <FIG>, the storage device <NUM> may have an overprovision area in addition to a meta area and a user area.

The overprovision area may be a storage space that is provided to improve the performance of the storage device <NUM>. For example, in the case that free memory blocks in which data are not written exist, when a garbage collection operation or a read reclaim operation is performed on data written in the user area, the garbage collection operation and the read reclaim operation may be more quickly performed.

The storage device <NUM> may provide the user area to the external host device, and may integrally leverage the user area and the overprovision area to write and manage user data.

In the provisioning operation S410, the storage device <NUM> may fixedly allocate a portion of the user area or the overprovision area for a buffer area. A portion of the buffer area may be included in the overprovision area, and a remainder of the buffer area may be included in the user area. Accordingly, the user area or the overprovision area may have an original size or a decreased size.

<FIG> illustrates a diagram in which a buffer area is allocated in a non-reduction mode when the storage device <NUM> has an overprovision (OP) area. Referring to <FIG> and <FIG>, the storage device <NUM> may have an overprovision area in addition to a meta area and a user area.

In the provisioning operation S410, the storage device <NUM> may maintain original sizes of the user area or the overprovision area. The storage device <NUM> may dynamically allocate the user area or the overprovision area for a buffer area. A portion of the buffer area may be included in the overprovision area, and a remainder of the buffer area may be included in the user area.

Returning to <FIG>, in operation S420 and operation S422, the processor <NUM> and the storage device <NUM> may perform the turbo write operation. For example, in operation S420, the processor <NUM> may request the turbo write operation from the storage device <NUM>.

For example, the request for the turbo write operation may use a write command UPIU based on the UFS. The write command UPIU may be identified as the request for the turbo write operation by setting a group number of the write command UPIU to a certain value, for example, "0x11. " The storage device <NUM> may write data into the buffer area <NUM> in response to the write command UPIU having the group number of "0x11. " In operation S422, the storage device <NUM> may transmit the response UPIU to the processor <NUM>.

In operation S430 and operation S432, the processor <NUM> and the storage device <NUM> may perform the normal write operation. For example, in operation S430, the processor <NUM> may request the normal write operation from the storage device <NUM>.

For example, the request for the normal write operation may use the write command UPIU based on the UFS. The storage device <NUM> may write data into the user area <NUM> in response to the write command UPIU. In operation S432, the storage device <NUM> may transmit the response UPIU to the processor <NUM>.

In operation S440, the processor <NUM> and the storage device <NUM> may perform a migration operation or may set the migration operation. For example, in operation S440, the processor <NUM> may request the migration operation from the storage device <NUM>. The request for the migration operation may be performed by using the query request UPIU based on the UFS.

For example, the processor <NUM> may transmit a set flag query request UPIU to the storage device <NUM>. The set flag query request UPIU may include flush information or hibernation information. When the set flag query request UPIU includes the flush information, the storage device <NUM> may perform the migration operation, which is described with reference to <FIG>, in response to the set flag query request UPIU.

When the set flag query request UPIU includes the hibernation information, the storage device <NUM> may change migration settings. For example, in response to the set flag query request UPIU, the storage device <NUM> may change the migration settings such that the migration operation is autonomously performed in the hibernation mode or such that the autonomous migration operation is not performed.

In operation S442, the storage device <NUM> may transmit the response UPIU to the processor <NUM>. For example, the response UPIU may include the available buffer size. That is, when the migration operation is completed, the storage device <NUM> may identify the available buffer size and may report to the processor <NUM> on the available buffer size.

In operation S450 and operation S452, the processor <NUM> and the storage device <NUM> may perform a buffer size query operation. For example, in operation S450, the processor <NUM> may query to the storage device <NUM> to obtain the buffer size. The query about the buffer size may be performed by using a query request based on the UFS.

For example, the processor <NUM> may transmit a read attributes query request UPIU to the storage device <NUM>. In operation S452, the storage device <NUM> may transmit the response UPIU to the processor <NUM>. The response UPIU may include the available buffer size. For example, in response to the read attributes query request UPIU, the storage device <NUM> may identify the available buffer size and may provide an indication of the available buffer size to the processor <NUM>.

In an embodiment, as described with reference to <FIG>, when the storage device <NUM> includes the random access memory <NUM>, the turbo write operation, the normal write operation, and the migration operation that are described with reference to <FIG> may be autonomously performed by the controller <NUM>. As described with reference to <FIG>, the storage device <NUM> may perform the provisioning operation in response to a request of the processor <NUM>. The buffer size query operation may be omitted.

<FIG> illustrates a method of the processor <NUM> writing data into the storage device <NUM>. Referring to <FIG>, <FIG>, and <FIG>, in operation S510, the processor <NUM> may determine whether data to be written requires the turbo write operation. For example, when data to be written require a write operation for a large amount of data, such as video data, the processor <NUM> may determine that the data to be written requires the turbo write operation.

When the data to be written requires the turbo write operation, in operation S520, the processor <NUM> may determine whether the size of the data to be written is greater than the available buffer size. When the size of the data to be written is not greater than the available buffer size, in operation S530, the processor <NUM> may perform the turbo write operation of writing data into the buffer area <NUM>.

When the size of the data to be written is greater than the available buffer size, in operation S540, the processor <NUM> may divide the data into a turbo portion and a normal portion. In operation S550, the processor <NUM> may perform the turbo write operation of writing the turbo portion of the data into the buffer area <NUM>.

In operation S560, the processor <NUM> may perform the normal write operation of writing the normal portion of the data into the user area <NUM>. That is, the processor <NUM> may split the data to be written and may write the split portions into the storage device <NUM> through the turbo write operation and the normal write operation.

When it is determined in operation S510 that the data to be written do not require the turbo write operation, in operation S570, the processor <NUM> may perform the normal write operation of writing the data into the user area <NUM> of the storage device <NUM>.

As described with reference to <FIG>, when the storage device <NUM> includes the random access memory <NUM>, the method described with reference to <FIG> may be autonomously performed by the controller <NUM>.

<FIG> illustrates a method of the computing device <NUM> changing a size of a buffer area. Referring to <FIG>, <FIG>, and <FIG>, in operation S610, the computing device <NUM> may perform booting when power is supplied and provisioning, as described above. For example, the processor <NUM> may perform the provisioning operation with the storage device <NUM>, based on the size of the buffer area of the existing provisioning settings. Afterwards, the computing device <NUM> may execute an operating system and applications under control of a user.

In operation S620, the computing device <NUM> may receive a buffer area change input. For example, the computing device <NUM> may receive the buffer area change input from the user through the user interface <NUM>. In operation S630, in response to the buffer area change input, the processor <NUM> may update the size of the buffer area of the provisioning settings.

Afterwards, in operation S640, the computing device <NUM> may again perform booting and provisioning. For example, the processor <NUM> may perform the provisioning operation with the storage device <NUM>, based on the size of the buffer area of the updated provisioning settings.

As described above, the computing device <NUM> may change the size of the buffer area, based on an input of the user. Changing the size of the buffer area may accompany rebooting and re-provisioning. As the change of the size of the buffer area is permitted, the computing device <NUM> may provide greater flexibility to the user.

When the size of the buffer area increases, an existing memory block that has been used as the user area may be utilized as the buffer area. When the size of the buffer area decreases, an existing memory block that has been utilized as the buffer area may be used as the user area.

As described above, components of the storage device <NUM> or <NUM> and the computing device <NUM> are described by using the terms "first," "second," "third," and the like. However, the terms "first," "second," "third," and the like may be used to distinguish components from each other and do not limit the descriptions thereof. For example, the terms "first," "second," "third," and the like do not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments are described by using blocks and modules. The blocks and modules may be implemented with various hardware devices, such as an integrated circuit, an application certain IC (ASCI), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks and modules may include circuits enrolled as circuits or semiconductor elements in an integrated circuit.

Claim 1:
A storage device (<NUM>) comprising:
a nonvolatile memory device (<NUM>) including a plurality of memory blocks; and
a controller (<NUM>) configured to use some memory blocks of the plurality of memory blocks as a buffer area (<NUM>),
wherein memory blocks storing invalid data from among the some memory blocks are invalid memory blocks (BLK17-<NUM>), and characterised in that the controller is further configured to:
identify memory blocks, of which an elapsed time after erase is greater than a reuse time, from among the invalid memory blocks as available memory blocks of the buffer area; and
provide an available buffer size to an external host device, the available buffer size indicating a number and/or capacity of the available memory blocks,
wherein the reuse time is a predetermined time against which the availability or unavailability of the memory block is judged on the basis of a time over which charges that are trapped as a result of an erase operation in a tunneling insulating layer or a blocking insulating layer of a memory cell of the memory block are discharged so as to lower the threshold voltage prior to the block being made available.