Patent Description:
Display apparatuses have been used for various purposes. Also, since the thickness and weight of the display apparatuses have been reduced, a utilization range of the display apparatuses has increased. <CIT> relates to a display apparatus having a hole in the display area. <CIT> relates to an organic light emitting display having a touch sensor.

According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>. According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

While such terms as "first," "second," etc., may be used to describe various components, such components are not be limited to the above terms. The above terms are used only to distinguish one component from another.

In the present specification, it is to be understood that the terms "including," "having," and "comprising" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.

<FIG> illustrates a perspective view of a display apparatus <NUM> according to an embodiment.

Referring to <FIG>, the display apparatus <NUM> may include a display area DA that emits light and a non-display area NDA that does not emit light. The non-display area NDA may be adjacent to the display area DA. The display apparatus <NUM> may provide a predetermined image via light emitted from a plurality of pixels arranged in the display area DA.

The display apparatus <NUM> may include an opening area OA that is at least partially surrounded by the display area DA. As an embodiment, <FIG> shows that the opening area OA is entirely surrounded by the display area DA. An intermediate area in which pixels are not arranged may be provided between the opening area OA and the display area DA. The display area DA may be surrounded by an outer area (or peripheral area) in which pixels are not provided. The intermediate area and the outer area are respective non-display areas, in which pixels are not provided. Hereinafter, the intermediate area and the outer area are described respectively as a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may entirely surround the opening area OA, and the display area DA may entirely surround the first non-display area NDA1. The second non-display area NDA2 may entirely surround the display area DA. The first non-display area NDA1 and the second non-display area NDA2 may be collectively referred to as a non-display area NDA.

Hereinafter, according to an embodiment, the display apparatus is described as an organic light-emitting display apparatus. In some implementations, the display apparatus <NUM> may be an inorganic light-emitting display, a quantum dot light-emitting display, etc..

<FIG> shows that one opening area OA is provided, and that the opening area OA has a circular shape. In some implementations, two or more opening areas OA may be provided, and each opening area OA may have various shapes such as a circular shape, an elliptic shape, a polygonal shape, a star shape, a diamond shape, etc..

<FIG> illustrates a cross-sectional view of the display apparatus <NUM> according to the embodiment, taken along a line II-II' of <FIG>.

Referring to <FIG>, the display apparatus <NUM> may include a display panel <NUM>, an input sensing layer <NUM> on the display panel <NUM>, and an optical functional layer <NUM>, which may be covered by a window <NUM>. The display apparatus <NUM> may be, for example, one of various electronic devices such as a mobile phone, a laptop computer, a smart watch, etc..

The display panel <NUM> may display images. The display panel <NUM> may include pixels arranged in the display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light-emitting diode, an inorganic light-emitting diode, a quantum-dot light-emitting diode, etc..

The input sensing layer <NUM> may obtain coordinate information generated according to an external input, e.g., a touch event. The input sensing layer <NUM> may include a sensing electrode (or touch electrode) and trace lines connected to the sensing electrode. The input sensing layer <NUM> may be arranged on the display panel <NUM>. The input sensing layer <NUM> may sense an external input by a mutual capacitance method and/or a self-capacitance method.

The input sensing layer <NUM> may be directly arranged on the display panel <NUM> or may be separately formed and then bonded to the display panel <NUM> via an adhesive layer such as an optical clear adhesive (OCA). For example, the input sensing layer <NUM> may be arranged successively after a process of forming the display panel <NUM>. In this case, the adhesive layer may be omitted between the input sensing layer <NUM> and the display panel <NUM>. <FIG> shows an embodiment in which the input sensing layer <NUM> is arranged between the display panel <NUM> and the optical functional layer <NUM>. In some implementations, the input sensing layer <NUM> may be arranged on the optical functional layer <NUM>.

The optical functional layer <NUM> may include an anti-reflection layer. The anti-reflection layer may reduce a reflectivity of light incident to the display panel <NUM> from outside (external light) via the window <NUM>. The anti-reflection layer may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type. The retarder may include a λ/<NUM> retarder and/or a λ/<NUM> retarder. The polarizer may be of a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film. The liquid crystal coating type polarizer may include liquid crystals arranged in a predetermined orientation. The retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as a base layer of the anti-reflection layer.

As another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged considering a color of light emitted from each of the pixels in the display panel <NUM>. As another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers. First reflected light and second reflected light that are respectively reflected by the first reflective layer and the second reflective layer may be destructively interfered with each other, and accordingly a reflectivity of external light may be reduced.

The optical functional layer <NUM> may include a lens layer. The lens layer may improve the light-emitting efficiency of light emitted from the display panel <NUM> or may reduce color difference. The lens layer may include a layer having a concave or a convex lens shape and/or may include a plurality of layers having different refractive indices. The optical functional layer <NUM> may include both the anti-reflection layer and the lens layer or may include either the anti-reflection layer or the lens layer.

The display panel <NUM>, the input sensing layer <NUM>, and the optical functional layer <NUM> may each include an opening. Regarding this, <FIG> shows that the display panel <NUM>, the input sensing layer <NUM>, and the optical functional layer <NUM> respectively include first to third openings <NUM>, <NUM>, and <NUM> that overlap with one another. The first opening <NUM> passes from a top surface to a bottom surface of the display panel <NUM>. The second opening <NUM> passes from a top surface to a bottom surface of the input sensing layer <NUM>. The third opening <NUM> passes from a top surface to a bottom surface of optical functional layer <NUM>. The first to third openings <NUM>, <NUM>, and <NUM> may be located to correspond to the opening area OA. As another embodiment, at least one of the display panel <NUM>, the input sensing layer <NUM>, or the optical functional layer <NUM> may not include an opening. For example, the opening may be omitted from one or two elements selected from the display panel <NUM>, the input sensing layer <NUM>, and the optical functional layer <NUM>. The term "opening area OA" may indicate an area in which at least one of the first to third openings <NUM>, <NUM>, or <NUM> of the display panel <NUM>, the input sensing layer <NUM>, or the optical functional layer <NUM> is located. For example, in the specification, the opening area OA may be an area in which the first opening <NUM> of the display panel <NUM> is located.

The opening area OA may be a kind of component area (e.g., a sensor region, a camera region, a speaker region, etc.) in which a component <NUM> for adding various functions to the display apparatus <NUM> is located. The component <NUM> may be located in the first to third openings <NUM>, <NUM>, and <NUM> as indicated by a solid line in <FIG>. In some implementations, the component <NUM> may be arranged under the display panel <NUM> as indicated by a dashed line. In this case, the opening may be omitted from one or more of the display panel <NUM>, the input sensing layer <NUM>, and the optical functional layer <NUM>. As an embodiment, when the display panel <NUM> does not include an opening, at least one of elements of the display panel <NUM>, wherein the elements are located in the opening area OA and will be described later with reference to <FIG>, etc., includes a hole or an opening corresponding to the opening area OA and the other elements may be present. As an embodiment, when the display panel <NUM> does not include an opening, a component <NUM> that does not have to have a relatively high transmittance, e.g., an infrared ray (IR) sensor, etc., may be arranged in the opening area OA.

The component <NUM> may include an electronic element. For example, the component <NUM> may be an electronic element that uses light or sound. For example, the electronic element may include a sensor using light, such as an IR sensor, a camera capturing an image by receiving light, a sensor for outputting and sensing light or sound to measure a distance or recognize a fingerprint, a small-sized lamp illuminating light, a speaker for outputting sound, etc. The electronic element using light may use light of various wavelength bands such as visible light, IR light, ultraviolet (UV) rays, etc. In some embodiments, the opening area OA may be considered as a transmission area through which light and/or sound output from the component <NUM> or proceeding towards the electronic element may pass from the outside.

In an embodiment, when the display apparatus <NUM> is used in a smart watch or an instrument panel for a vehicle, the component <NUM> may include a member having a clock needle or a needle indicating predetermined information (e.g., vehicle velocity, etc.). When the display apparatus <NUM> includes a clock needle or an instrument panel for a vehicle, the component <NUM> may be exposed to outside after penetrating through the window <NUM>, and the window <NUM> may include an opening corresponding to the opening area OA.

The component <NUM> may include element(s) related to functions of the display panel <NUM> as described above or may include element(s) such as an accessory that increases an aesthetic sense of the display panel <NUM>. For example, a layer including an OCA, etc. may be located between the window <NUM> and the optical functional layer <NUM>.

<FIG> illustrates a plan view of the display panel <NUM> according to the embodiment. <FIG> is an equivalent circuit diagram of a pixel in the display panel <NUM>.

Referring to <FIG>, the display panel <NUM> may include the opening area OA, the display area DA and the first and second non-display areas NDA1 and NDA2. <FIG> includes a substrate <NUM> in the display panel <NUM>. For example, it may be appreciated that the substrate <NUM> includes the opening area OA, the display area DA, and the first and second non-display areas NDA1 and NDA2.

The display panel <NUM> includes a plurality of pixels P arranged in the display area DA. Each of the pixels P includes a pixel circuit PC and a display element connected to the pixel circuit PC, e.g., an organic light-emitting diode OLED. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light via the organic light-emitting diode OLED, or may emit red light, green light, blue light, or white light via the organic light-emitting diode OLED.

The second thin film transistor T2 is a switching thin film transistor and is connected to a scan line SL and a data line DL. The second thin film transistor T2 may transfer a data voltage input from the data line DL to the first thin film transistor T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and a driving voltage line PL and may store a voltage corresponding to a difference between a voltage transferred from the second thin film transistor T2 and a first power voltage ELVDD supplied to the driving voltage line PL.

The first thin film transistor T1 is a driving thin film transistor connected to the driving voltage line PL and the storage capacitor Cst. The first thin film transistor T1 may control a driving current flowing in the organic light-emitting diode OLED from the driving voltage line PL, corresponding to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a predetermined luminance according to the driving current. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may be supplied with a second power voltage ELVSS.

<FIG> illustrates that the pixel circuit PC includes two thin film transistors and one storage capacitor, as an example. The number of thin film transistors and the number of storage capacitors may vary depending on a design of the pixel circuit PC.

Referring back to <FIG>, the first non-display area NDA1 may surround the opening area OA. The first non-display area NDA1 is an area in which a display element such as an organic light-emitting diode that emits light is not present. Trace lines for providing signals to the pixels P around the opening area OA may pass through the first non-display area NDA1. The second non-display area NDA2 may include a scan driver <NUM> for providing each pixel P with a scan signal, a data driver <NUM> for providing each pixel P with a data signal, and a main power line for supplying first and second power voltages. <FIG> shows that the data driver <NUM> is arranged adjacent to a side of the substrate <NUM>, as an example. In some implementations, the data driver <NUM> may be arranged on a flexible printed circuit board (FPCB) that is electrically connected to a pad arranged at a side of the display panel <NUM>.

<FIG> illustrates a plan view showing a portion of the display panel <NUM> and the signal lines located in the first non-display area NDA1, according to the embodiment.

Referring to <FIG>, the pixels P may be arranged in the display area DA around the opening area OA, and the first non-display area NDA1 may be located between the opening area OA and the display area DA.

The pixels P may be apart from one another on the plane around the opening area OA. For example, two pixels P may be spaced apart from each other with the opening area OA therebetween. As shown in <FIG> the pixels P may be arranged above and under the opening area OA (for example, space apart in the y direction) or may be arranged on left and right sides of the opening area OA (for example, spaced apart in the x direction).

Among the signal lines supplying signals to the pixels P, the signal lines adjacent to the opening area OA may detour (or bypass) around the opening area OA. Some of the data lines DL passing through the display area DA may extend in a y-axis direction to provide data signals to the pixels P arranged above and under the opening area OA. These data lines DL may detour along an edge of the opening area OA in the first non-display area NDA1. Some of the scan lines SL passing through the display area DA may extend in an x-axis direction to provide scan signals to the pixels P arranged on left and right sides of the opening area OA. These scan lines SL may detour along an edge of the opening area OA in the first non-display area NDA1.

<FIG> illustrates a plan view showing a portion of the display panel <NUM> and grooves located in the first non-display area NDA1, according to an embodiment.

Referring to <FIG>, one or more grooves may be located in the first non-display area NDA1 between the opening area OA and the display area DA. As an example, <FIG> shows three grooves G located between the opening area OA and the display area DA.

The grooves G may be formed in loop (or ring) shapes entirely surrounding the opening area OA in the plane in the first non-display area NDA1. A radius of each groove G from a center C of the opening area OA on the plane may be greater than that of the opening area OA. The grooves G may be spaced apart from one another.

Referring to <FIG> and <FIG>, the grooves G may be closer to the opening area OA than the arched portions of the data line DL and/or the scan line SL that detour around the edge of the opening area OA.

<FIG> illustrates a cross-sectional view taken along a line VII-VII' of <FIG> of the display panel <NUM> according to the embodiment.

Referring to <FIG>, the pixel circuit PC and the organic light-emitting diode OLED electrically connected to the pixel circuit PC may be arranged in the display area DA. The pixel circuit PC is arranged on the substrate <NUM> and the organic light-emitting diode OLED may be located on the pixel circuit PC. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst on the substrate <NUM>. A pixel electrode <NUM> may be electrically connected to the thin film transistor TFT and the storage capacitor Cst.

The substrate <NUM> may include a polymer resin or a glass material. In one embodiment, the substrate <NUM> may include a polymer resin such as a polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc. In this case, the substrate <NUM> may be flexible. The substrate <NUM> may include a glass material mainly containing SiO<NUM> or a resin such as reinforced plastic. In this case, the substrate <NUM> may be rigid. The substrate <NUM> may have a stack structure including a polymer resin layer and a barrier layer on the polymer resin layer to improve the flexibility of the substrate <NUM>. The barrier layer may include silicon nitride (SiNx, x><NUM>), silicon oxynitride (SiON), silicon oxide (SiOx, x><NUM>), etc..

A buffer layer <NUM> may be on the substrate <NUM> in order to help prevent impurities from infiltrating into a semiconductor layer Act of the thin film transistor TFT. The buffer layer <NUM> may include an inorganic insulating material such as SiNx, SiON, and SiOx and may have a single-layered or multi-layered structure including the inorganic insulating material.

The pixel circuit PC may be arranged on the buffer layer <NUM>. The pixel circuit PC may include the thin film transistor TFT and the storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The thin film transistor TFT shown in <FIG> may correspond to the driving thin film transistor described above with reference to <FIG>. <FIG> shows the thin film transistor TFT as being a top gate-type transistor in which the gate electrode GE is over the semiconductor layer Act with a gate insulating layer <NUM> provided therebetween. In some implementations, the thin film transistor TFT may be a bottom gate-type transistor.

The semiconductor layer Act may include polysilicon. In some implementations, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode GE may include a low-resistive metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The gate electrode GE may have a single-layered structure or a multi-layered structure.

The gate insulating layer <NUM> may be between the semiconductor layer Act and the gate electrode GE and may include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer <NUM> may have a single-layered structure or a multi-layered structure including the above materials.

The source electrode SE and the drain electrode DE may include a highly conductive material. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, Ti, etc. The source electrode SE and the drain electrode DE may have a single-layered structure or a multi-layered structure including the above materials. As an embodiment, the source electrode SE and the drain electrode DE may have a multi-layered structure including Ti/Al/Ti.

The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other in the z direction with a first interlayer insulating layer <NUM> provided therebetween. The storage capacitor Cst may overlap the thin film transistor TFT. Regarding this, <FIG> shows a structure in which the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In some implementations, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer <NUM>.

The first and second interlayer insulating layers <NUM> and <NUM> may each include inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first and second interlayer insulating layers <NUM> and <NUM> may have a single-layered structure or a multi-layered structure including the above materials.

The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by a planarized insulating layer <NUM>. The planarized insulating layer <NUM> may have a flat upper surface. The planarized insulating layer <NUM> may include a general-purpose polymer (e.g., polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative having phenol groups, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluoride-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or blends thereof. For example, the planarized insulating layer <NUM> may include polyimide. In some implementations, the planarized insulating layer <NUM> may include an inorganic insulating material, or inorganic and organic insulating materials.

The pixel electrode <NUM> may be formed on the planarized insulating layer <NUM>. The pixel electrode <NUM> may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide, or aluminum zinc oxide (AZO). In some implementations, the pixel electrode <NUM> may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In some implementations, the pixel electrode <NUM> may further include a layer including ITO, IZO, ZnO, or In<NUM>O<NUM> on and/or under the reflective layer.

A pixel defining layer <NUM> may be formed on the pixel electrode <NUM>. The pixel defining layer <NUM> may include an opening exposing an upper surface of the pixel electrode <NUM> while covering edges of the pixel electrode <NUM>. The pixel defining layer <NUM> may include an organic insulating material. In some implementations, the pixel defining layer <NUM> may include an inorganic insulating material such as SiNx, SiON, or SiOx. In some implementations, the pixel defining layer <NUM> may include an organic insulating material and an inorganic insulating material.

An intermediate layer <NUM> may include an emission layer 222b. The intermediate layer <NUM> may include a first functional layer 222a under the emission layer 222b and/or a second functional layer 222c on the emission layer 222b. The emission layer 222b may include a polymer or low-molecular weight organic material to emit a predetermined color light.

The first functional layer 222a may have a single-layered structure or a multi-layered structure. For example, when the first functional layer 222a includes a polymer material, the first functional layer 222a may include a hole transport layer (HTL) having a single-layered structure. The hole transport layer HTL may include poly-(<NUM>,<NUM>)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a low-molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and an HTL.

The second functional layer 222c is optional. For example, when the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c may be formed. The second functional layer 222c may have a single-layered structure or a multi-layered structure. The second functional layer 222c may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The emission layer 222b of the intermediate layer <NUM> may be arranged in all pixels of the display area DA. The emission layer 222b may contact an upper surface of the pixel electrode <NUM> that is exposed through the opening in the pixel defining layer <NUM>. Unlike the emission layer 222b, the first and second functional layers 222a and 222c of the intermediate layer <NUM> may be arranged in the first non-display area NDA1 (see <FIG>, etc.), as well as the display area DA of <FIG>.

The opposite electrode <NUM> may include a conductive material having a low work function. For example, the opposite electrode <NUM> may include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. In some implementations, the opposite electrode <NUM> may further include a layer including ITO, IZO, ZnO, or In<NUM>O<NUM> on the (semi-)transparent layer including the above material. The opposite electrode <NUM> may be formed in the first non-display area NDA1, as well as in the display area DA. The intermediate layer <NUM> and the opposite electrode <NUM> may be formed by a thermal evaporation method.

A capping layer <NUM> may be located on the opposite electrode <NUM>. For example, the capping layer <NUM> may include LiF and may be formed by a thermal evaporation method. In some implementations, the capping layer <NUM> may include an inorganic insulating material such as SiOx, SiNx, and SiON. In some implementations, the capping layer <NUM> may be omitted.

A spacer <NUM> may be formed on the pixel defining layer <NUM>. In some implementations, the spacer <NUM> may include an organic insulating material such as polyimide. In some implementations, the spacer <NUM> may include an inorganic insulating material such as SiNx and SiOx. In some implementations, the spacer <NUM> may include an organic insulating material and an inorganic insulating material.

In some implementations, the spacer <NUM> may include a material that is different from that included in the pixel defining layer <NUM>. In some implementations, the spacer <NUM> may include a material that is the same as that included in the pixel defining layer <NUM>. In this case, the pixel defining layer <NUM> and the spacer <NUM> may be manufactured together through a mask process using a half-tone mask, etc. As an embodiment, the pixel defining layer <NUM> and the spacer <NUM> may include polyimide.

The organic light-emitting diode OLED may be covered by a thin film encapsulation layer <NUM>. The thin film encapsulation layer <NUM> may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. A stacking order and the number of organic and inorganic encapsulation layers may vary. For example, as shown in <FIG> the thin film encapsulation layer <NUM> may include first and second inorganic encapsulation layers <NUM> and <NUM> and an organic encapsulation layer <NUM> disposed between the first and second inorganic encapsulation layers <NUM> and <NUM>.

The first and second inorganic encapsulation layers <NUM> and <NUM> may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first and second inorganic encapsulation layers <NUM> and <NUM> may be manufactured by chemical vapor deposition (CVD). The organic encapsulation layer <NUM> may include a polymer-based material. The polymer-based material may include a silicon-based resin, an acryl-based resin, an epoxy-based resin, polyimide, polyethylene, etc..

The input sensing layer <NUM> may be arranged on the display panel <NUM>. As an example, the input sensing layer <NUM> may be directly formed on the display panel <NUM> and may contact the thin film encapsulation layer <NUM>, as shown in <FIG>.

<FIG> illustrates a plan view of the input sensing layer <NUM> according to an embodiment. <FIG> illustrates a portion of the input sensing layer <NUM> that corresponds to the display area DA shown in <FIG>.

Referring to <FIG>, the input sensing layer <NUM> may include first sensing electrodes SP1 and second sensing electrodes SP2 located in the display area DA. The first sensing electrodes SP1 may be arranged in an x-axis direction and the second sensing electrodes SP2 are arranged in a y-axis direction intersecting with the first sensing electrodes SP1. The first sensing electrodes SP1 and the second sensing electrodes SP2 may intersect each other perpendicularly.

The first sensing electrodes SP1 and the second sensing electrodes SP2 may be arranged so that corners thereof are adjacent to each other. The first sensing electrodes SP1 may be electrically connected to one another via first connecting electrodes CP1, and the second sensing electrodes SP2 may be electrically connected to one another via second connecting electrodes CP2.

<FIG> and <FIG> illustrate plan views of a first conductive layer <NUM> and a second conductive layer <NUM> in an input sensing layer <NUM> according to an embodiment. <FIG> illustrates a cross-sectional view of an input sensing layer according to an embodiment, taken along a line VIII-VIII' of <FIG>.

Referring to <FIG> and <FIG>, the first sensing electrodes SP1 and the second sensing electrodes SP2 may be arranged on the same layer. The first conductive layer <NUM> may include the first connecting electrodes CP1 (see <FIG>), and the second conductive layer <NUM> may include the first sensing electrodes SP1, the second sensing electrodes SP2, and the second connecting electrodes CP2 (see <FIG>).

The second sensing electrodes SP2 may be connected to one another via the second connecting electrodes CP2 arranged at the same layer as the second sensing electrodes SP2. The first sensing electrodes SP1 are arranged in the x-axis direction and may be connected to one another via the first connecting electrodes CP1, which are arranged in a different layer from that of the first sensing electrodes SP1.

Referring to <FIG>, a second insulating layer <NUM> may be arranged between the first conductive layer <NUM> and the second conductive layer <NUM>. The first sensing electrodes SP1 arranged in the second conductive layer <NUM> may be connected to the first connecting electrodes CP1 arranged in the first conductive layer <NUM> via contact holes CNT in the second insulating layer <NUM>. The second conductive layer <NUM> may be covered by a third insulating layer <NUM>, and a first insulating layer <NUM> may be arranged under the first conductive layer <NUM>. The first and second insulating layers <NUM> and <NUM> may include an inorganic insulating layer such as SiNx or an organic insulating layer. The third insulating layer <NUM> may include an organic insulating layer or an inorganic insulating layer. The first and second conductive layers <NUM> and <NUM> may each include a metal layer or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al, or an alloy thereof, and may have a single-layered or multi-layered structure. The transparent conductive layer may include a transparent conductive oxide material such as ITO, IZO, ZnO, ITZO, etc. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nano-wires, graphene, etc..

<FIG> shows that the first insulating layer <NUM> is arranged between the thin film encapsulation layer <NUM> and the first conductive layer <NUM>. In some implementations, the first insulating layer <NUM> may be omitted and the first conductive layer <NUM> may be located directly on the thin film encapsulation layer <NUM>.

<FIG> and <FIG> illustrate plan views of a first conductive layer <NUM> and a second conductive layer <NUM> in an input sensing layer according to another embodiment, and <FIG> illustrate a cross-sectional view of the input sensing layer according to another embodiment, taken along a line VIII-VIII' of <FIG>.

Referring to <FIG> and <FIG>, the first conductive layer <NUM> includes the first sensing electrodes SP1 and the first connecting electrodes CP1 for connecting the first sensing electrodes SP1. The second conductive layer <NUM> includes the second sensing electrodes SP2 and the second connecting electrodes CP2 for connecting the second sensing electrodes SP2. The first conductive layer <NUM> may further include second auxiliary sensing electrodes S-SP2 that are connected to the second sensing electrodes SP2, and the second conductive layer <NUM> may further include first auxiliary sensing electrodes S-SP1 that are connected to the first sensing electrodes SP1. In some implementations, the first auxiliary sensing electrodes S-SP1 and the second auxiliary sensing electrodes S-SP2 may be omitted.

Referring to the enlarged view of <FIG>, each of the first sensing electrodes SP1 may have a mesh structure including a plurality of holes H. Each of the holes H may overlap a light-emission area P-E of the pixel P. Although not shown in the drawings, the second sensing electrodes SP2, the first auxiliary sensing electrodes S-SP1, and the second auxiliary sensing electrodes S-SP2 may each have a mesh structure including a plurality of holes respectively corresponding to the light-emission areas P-E of the pixels, as shown in the enlarged view of <FIG>.

Referring to <FIG>, the first auxiliary sensing electrode S-SP1 may be connected to the first sensing electrode SP1 via the contact hole CNT in the second insulating layer <NUM>. Through the above configuration, resistance of the first sensing electrode SP1 may be reduced. Likewise, the second sensing electrode SP2 may be connected to the second auxiliary sensing electrode S-SP2 via the contact hole in the second insulating layer <NUM>. The first and second insulating layers <NUM> and <NUM> may include an inorganic insulating layer or an organic insulating layer such as SiNx, and the third insulating layer <NUM> may include an organic insulating material or an inorganic insulating material. The first and second conductive layers <NUM> and <NUM> may each include a metal layer or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al, or an alloy thereof, and may have a single-layered or multi-layered structure including the above-stated metal. The transparent conductive layer may include a transparent conductive oxide material or graphene, as described above.

<FIG> and <FIG> illustrate plan views of a first conductive layer <NUM> and a second conductive layer <NUM> in an input sensing layer according to another embodiment, and <FIG> illustrates a cross-sectional view of the input sensing layer according to another embodiment, taken along a line VIII-VIII' of <FIG>.

Referring to <FIG> and <FIG>, the first conductive layer <NUM> may include the first sensing electrodes SP1 and the first connecting electrodes CP1 for connecting the first sensing electrodes SP1. The second conductive layer <NUM> may include the second sensing electrodes SP2 and the second connecting electrodes CP2 for connecting the second sensing electrodes SP2.

Referring to <FIG>, the second insulating layer <NUM> may be arranged between the first conductive layer <NUM> and the second conductive layer <NUM>. The second insulating layer <NUM> may not include an additional contact hole, and the first and second sensing electrodes SP1 and SP2 may be electrically insulated from each other with the second insulating layer <NUM> provided therebetween. The second conductive layer <NUM> may be covered by the third insulating layer <NUM>. The first insulating layer <NUM> including an inorganic material or an organic material may be further provided under the first conductive layer <NUM>. The second and third insulating layers <NUM> and <NUM> may include organic insulating layers. In another embodiment, the second and third insulating layers <NUM> and <NUM> may include an inorganic insulating layer or both the organic and inorganic insulating layers. The first and second conductive layers <NUM> and <NUM> may each include a metal layer or a transparent conductive layer. The metal layer may include Mo, Mg, Ag, Ti, Cu, Al, or an alloy thereof, and may have a single-layered structure or a multi-layered structure including the above-stated metal. The transparent conductive layer may include a transparent conductive oxide material such as ITO, IZO, ZnO, ITZO, etc. The transparent conductive layer may include a conductive polymer such as PEDOT, metal nano-wires, graphene, etc..

<FIG> illustrates a cross-sectional view of the display panel <NUM> according to the embodiment, taken along a line XII-XII' of <FIG>, <FIG> and <FIG> illustrate cross-sectional views showing excerpts of a region XIII and a region XIV of <FIG>, <FIG> illustrates a plan view of the planarization layer <NUM> around the opening area OA in the display panel <NUM> according to the embodiment, and <FIG> illustrates a cross-sectional view of a display panel according to another embodiment.

Referring to <FIG>, the display panel <NUM> may include the opening area OA, the display area DA, and the first non-display area NDA1 between the opening area OA and the display area DA. The display panel <NUM> may include a first opening <NUM> corresponding to the opening area OA.

In the display area DA, the pixel circuit PC on the substrate <NUM>, the pixel electrode <NUM> connected to the pixel circuit PC, and the intermediate layer <NUM> and the opposite electrode <NUM> sequentially stacked on the pixel electrode <NUM> may be included.

The substrate <NUM> may have a multi-layered structure. For example, the substrate <NUM> may include a first base layer <NUM>, a first barrier layer <NUM>, a second base layer <NUM>, and a second barrier layer <NUM> that are sequentially stacked in the stated order.

The first and second base layers <NUM> and <NUM> may each include a polymer resin. For example, the first and second base layers <NUM> and <NUM> may include a polymer resin such as a PES, PAR, PEI, PEN, PET, PPS, PI, PC, TAC, CAP, etc. The polymer resin may be transparent.

The first and second barrier layers <NUM> and <NUM> may help prevent infiltration of external impurities. The first and second barrier layers <NUM> and <NUM> may each have a single-layered structure or a multi-layered structure including an inorganic material such as SiNx and/or SiOx.

The pixel circuit PC may be arranged on the substrate <NUM>. The pixel circuit PC may include a thin film transistor, a storage capacitor, etc. The organic light-emitting diode OLED including the pixel electrode <NUM>, the emission layer of the intermediate layer <NUM>, and the opposite electrode <NUM> may emit predetermined light. The OLED may be covered by the thin film encapsulation layer <NUM>. Elements arranged in the display area DA may be the same as those described above with reference to <FIG>.

Referring to the first non-display area NDA1 of <FIG>, the first non-display area NDA1 may include a first sub non-display area SNDA1 relatively closer to the display area DA and a second sub non-display area SNDA2 relatively closer to the opening area OA or the first opening <NUM>.

The first sub non-display area SNDA1 may be a region where the signal lines, e.g., the data lines DL described above with reference to <FIG> pass through. In this regard, the data lines DL shown in <FIG> may detour around the opening area OA. The first sub non-display area SNDA1 may be a wiring region or a detouring or bypassing region through which the data lines DL pass.

The data lines DL may be alternately arranged with an insulating layer provided therebetween, as shown in <FIG>. In some implementations, the data lines DL may be arranged on the same insulating layer (e.g., the second interlayer insulating layer <NUM>). When the data lines DL that are adjacent to each other are arranged respectively on and under the insulating layer (e.g., the second interlayer insulating layer <NUM>), a gap (pitch) between the data lines DL adjacent to each other may be reduced and a width of the first non-display area NDA1 may be reduced. <FIG> shows that the data lines DL are located in the first sub non-display area SNDA1. The scan lines (SL, <FIG>) that detour around the opening area OA as described above with reference to <FIG> may be located in the first sub non-display area SNDA1.

The second sub non-display area SNDA2 is a groove area in which grooves are arranged. The number of grooves may vary. For example, <FIG> shows five grooves located in the second sub non-display area SNDA2.

Each of the grooves G may be formed in a multi-layered structure including a first layer and a second layer which have different materials from each other. For example, the grooves G may be formed in a sub-layer of the substrate <NUM>, as shown in <FIG>.

Referring to <FIG> and <FIG>, the grooves G may be formed by partially removing the second barrier layer <NUM> and the second base layer <NUM>. A hole H2 penetrating through the second barrier layer <NUM> and a recess R1 formed in the second base layer <NUM> may be spatially connected to each other to form the groove G. The second base layer <NUM> may correspond to the first layer and the second barrier layer <NUM> may correspond to the second layer in the multi-layered structure described above.

In a process of forming the groove G, the buffer layer <NUM> on the second barrier layer <NUM> may be partially removed with the second barrier layer <NUM> to form the hole H2. Herein, the buffer layer <NUM> and the second barrier layer <NUM> are described as separate elements from each other, but in some implementations, the buffer layer <NUM> on the substrate <NUM> may be a sub-layer of the second barrier layer <NUM> having the multi-layered structure.

In the groove G, a width of a portion passing through the second barrier layer <NUM>, e.g., the hole H2, may be less than a width of a portion passing through the second base layer <NUM>, e.g., the recess R1. A width W2 (or diameter) of the hole H2 may be less than a width W1 (or diameter) of the recess R1, and the groove G may have an undercut cross-section.

A side surface of the second barrier layer <NUM>, which defines the hole H2, may protrude toward a center of the groove G more than a side surface of the second base layer <NUM>, which defines the recess R1. Protruding portions of the second barrier layer <NUM> toward the center of the groove G may form a pair of eaves (or a pair of protruding tips or tips, PT). The buffer layer <NUM> may also form a pair of eaves, together with the second barrier layer <NUM>.

The groove G may be formed before forming the intermediate layer <NUM>. A part <NUM>' of the intermediate layer <NUM>, e.g., first and/or second functional layers 222a and 222c extending to the first non-display area NDA1, may be disconnected in the groove G. Likewise, the opposite electrode <NUM> and the capping layer <NUM> including LiF may be disconnected in the groove G. A length ℓ of each of the pair of tips PT may be less than <NUM>. In one embodiment, the length ℓ may be about <NUM> to about <NUM>, or may be about <NUM> to about <NUM>.

In <FIG> and <FIG>, a bottom surface of the groove G is shown as being located on a virtual plane that is between a bottom surface and an upper surface of the second base layer <NUM>. In some implementations, the bottom surface of the groove G may be located on the same plane as that of the bottom surface of the second base layer <NUM>. For example, in an etching process for forming the groove G, a depth dp of the recess R1 may be substantially equal to a thickness t of the second base layer <NUM>. In this case, the bottom surface of the groove G may be on the same plane as the bottom surface of the second base layer <NUM>. The depth dp of the recess R1 may be equal to or greater than <NUM>. For example, the depth dp of the recess R1 may be equal to or greater than <NUM>. Or the depth dp of the recess R1 may be equal to or greater than <NUM>. When the depth dp of the recess R1 is equal to the thickness t of the second base layer <NUM>, the recess R1 may be a hole that penetrates through the second base layer <NUM>.

The thin film encapsulation layer <NUM> may extend to cover the first non-display area NDA1 as shown in <FIG>. For example, the first and second inorganic encapsulation layers <NUM> and <NUM> may extend to the first non-display area NDA1. The first and second inorganic encapsulation layers <NUM> and <NUM> may be formed by chemical vapor deposition (CVD), etc. and may have a step coverage that is relatively superior to that of the part <NUM>' in the intermediate layer <NUM> or the opposite electrode <NUM>. Therefore, the first and second inorganic encapsulation layers <NUM> and <NUM> may be continuously formed without being disconnected in the groove G. The first inorganic encapsulation layer <NUM> may cover an inner surface of the groove G. The first and second inorganic encapsulation layers <NUM> and <NUM> may have different thickness from each other. For example, the first inorganic encapsulation layer <NUM> may have a thickness of about <NUM> and the second inorganic encapsulation layer <NUM> may have a thickness of about <NUM>. For example, the thickness of the second inorganic encapsulation layer <NUM> may be less than that of the first inorganic encapsulation layer <NUM>.

<FIG> and <FIG> show a structure in which the capping layer <NUM> including LiF is disconnected in the groove G. In some implementations, when the capping layer <NUM> includes an inorganic material such as SiNx, SiOx, and SiON, the capping layer <NUM> may continuously cover the inner surface of the groove G without being disconnected in the groove G, similar to the first inorganic encapsulation layer <NUM>.

As shown in <FIG>, the organic encapsulation layer <NUM> may cover the display area DA, and an end 320E thereof may be located at one side of a first barrier wall <NUM>. The organic encapsulation layer <NUM> may be formed by applying a monomer and hardening the monomer. A flow of the monomer may be controlled by the first barrier wall <NUM> and a thickness of the organic encapsulation layer <NUM> may be also controlled by the first barrier wall <NUM>. When the organic encapsulation layer <NUM>, e.g., the end 320E of the organic encapsulation layer <NUM>, is spaced apart from the opening area OA, external moisture infiltrating through the first opening <NUM> may not proceed to the organic light-emitting diode OLED in the display area DA.

An organic material layer 320A may be spaced a predetermined distance from the organic encapsulation layer <NUM> and may be arranged adjacent to the opening area OA and/or the first opening <NUM>. The organic material layer 320A may be formed in the same process as that of forming the organic encapsulation layer <NUM> and may include the same material as that of the organic encapsulation layer <NUM>. Similarly, the flow of monomer may be controlled by the first barrier wall <NUM> in the process of forming the organic encapsulation layer <NUM>. The organic material layer 320A may be adjusted by a second barrier wall <NUM>, and an end 320AE of the organic material layer 320A may be located at one side of the second barrier wall <NUM>. As shown in <FIG>, the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may be located on the first non-display area NDA1 in contact with each other. If a contact area between the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> were to be equal to or greater than a certain value, the first and second inorganic encapsulation layers <NUM> and <NUM> or adjacent layers, e.g., a planarization layer <NUM> that will be described later, could be lifted/ exfoliated due to the stress on the first and second inorganic encapsulation layers <NUM> and <NUM>. However, according to the embodiment, the organic material layer 320A may be arranged between the first and second inorganic encapsulation layers <NUM> and <NUM>, and thus the above-described exfoliating of layers may be avoided. When the organic material layer 320A is located apart from the organic encapsulation layer <NUM>, the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> may contact each other in an area (or region) between the end 320E of the organic encapsulation layer <NUM> and an end 320AE of the organic material layer 320A.

The planarization layer <NUM> may be arranged in the first non-display area NDA1. The planarization layer <NUM> may include an organic insulating layer. The planarization layer <NUM> may include a polymer-based material. For example, the planarization layer <NUM> may include a silicon-based resin, an acryl-based resin, an epoxy-based resin, PI, polyethylene, etc. The polymer-based material may be transparent. In one embodiment, the planarization layer <NUM> may include a material different from that included in the organic encapsulation layer <NUM>. For example, the organic encapsulation layer <NUM> may include a silicon-based resin, and the planarization layer <NUM> may include an acryl-based resin. In another embodiment, the organic encapsulation layer <NUM> and the planarization layer <NUM> may include the same material.

The planarization layer <NUM> may cover at least one groove G located in the first non-display area NDA1. The planarization layer <NUM> may at least cover a region of the first non-display area NDA1 that is not covered by the organic encapsulation layer <NUM>, to increase flatness of the display panel <NUM> around the opening area OA. Therefore, separation or lifting-off of the input sensing layer <NUM> (see <FIG>) and/or the optical functional layer <NUM> (see <FIG>) arranged on the display panel <NUM> may be minimized or prevented. The planarization layer <NUM> may partially overlap the organic encapsulation layer <NUM>. An end of the planarization layer <NUM>, e.g., a first end 720E1 that is adjacent to the display area DA, may be located on the organic encapsulation layer <NUM> in the first non-display area NDA1. The first end 720E1 of the planarization layer <NUM> may be closer to the opening area OA than a light-emitting area (e.g., opening of the pixel defining layer) of a pixel that is closest to the first non-display area NDA1. Regarding this, <FIG> shows that the first end 720E1 of the planarization layer <NUM> may be located between the first sub non-display area SNDA1 and the light-emitting area of the pixel closest to the first non-display area NDA1. In some implementations, the first end 720E1 of the planarization layer <NUM> may be located in the first sub non-display area SNDA1 so that the planarization layer <NUM> may partially cover the data lines DL located in the first sub non-display area SNDA1. In some implementations, the first end 720E1 of the planarization layer <NUM> may be located between the first sub non-display area SNDA1 and the second sub non-display area SNDA2 so as not to cover the data lines DL located in the first sub non-display area SNDA1.

The planarization layer <NUM> may be formed on the first non-display area NDA1 through exposure and development processes, etc. In some of the processes for forming the planarization layer <NUM> (e.g., cleaning processes), if external impurities, e.g., moisture, were to proceed in a lateral direction (e.g., a direction parallel to an xy plane) of the display panel <NUM>, the organic light-emitting diode OLED of the display area DA could be damaged. However, according to the one or more embodiments, the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may be arranged under and on the planarization layer <NUM>, and thus, moisture infiltration during and after the process of forming the planarization layer <NUM> may be prevented or minimized.

The first inorganic insulating layer <NUM> may be located directly under the planarization layer <NUM>, and the second inorganic insulating layer <NUM> may be located directly on the planarization layer <NUM>. Each of the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may include an inorganic insulating material such as SiOx, SiNx, and SiON. The first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may include the same material as each other or different materials from each other. The second inorganic insulating layer <NUM> may have a thickness that is greater than that of the first inorganic insulating layer <NUM>. In some implementations, the thickness of the second inorganic insulating layer <NUM> may be equal to or less than that of the first inorganic insulating layer <NUM>.

The first inorganic insulating layer <NUM> may directly contact the thin film encapsulation layer <NUM>. For example, the first inorganic insulating layer <NUM> may directly contact an upper surface of the second inorganic encapsulation layer <NUM>. The first inorganic insulating layer <NUM> may include a material that is the same as or different from that of the second inorganic encapsulation layer <NUM>. In one embodiment, the first inorganic insulating layer <NUM> and the second inorganic encapsulation layer <NUM> may include the same material, e.g., SiNx. Even when the first inorganic insulating layer <NUM> and the second inorganic encapsulation layer <NUM> both include SiNx, the first inorganic insulating layer <NUM> and the second inorganic encapsulation layer <NUM> may be respectively formed in separate processes, and detailed composition ratios thereof (e.g., content ratio between silicon and nitrogen) may vary. An interface may be between the first inorganic insulating layer <NUM> and the second inorganic encapsulation layer <NUM>. The first inorganic insulating layer <NUM> may have a thickness that is less than that of the second inorganic encapsulation layer <NUM>.

The planarization layer <NUM> may include a first portion 720A and a second portion 720B that are separated from each other based on the first barrier wall <NUM>. Referring to <FIG> and <FIG>, when the first portion 720A and the second portion 720B are separated from each other, the planarization layer <NUM> may include a hole <NUM> between the first portion 720A and the second portion 720B. When the planarization layer <NUM> includes the hole <NUM>, a contact region between inorganic insulating materials may be generated partially in the first non-display area NDA1. For example, on the first barrier wall <NUM> corresponding to the hole <NUM> of the planarization layer <NUM>, the first inorganic encapsulation layer <NUM>, the second inorganic encapsulation layer <NUM>, the first inorganic insulating layer <NUM>, and the second inorganic insulating layer <NUM> may be sequentially stacked in contact with one another.

The first barrier wall <NUM> may include multiple layers. For example, as shown in <FIG>, the first barrier wall <NUM> may include inorganic layers IL1, IL2, and IL3, and organic layers OL1 and OL2. The organic layers OL1 and OL2 may entirely cover the inorganic layers IL1, IL2, and IL3. For example, the organic layers OL1 and OL2 may cover upper and side surfaces of a stack of the inorganic layers IL1, IL2, and IL3. The inorganic layers IL1, IL2, and IL3 may respectively include materials that are the same as those of the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>. The organic layers OL1 and OL2 may respectively include materials that are the same as those of the planarized insulating layer <NUM> and the pixel defining layer <NUM>. some implementations, the number of layers included in the first barrier wall <NUM> may be greater than or less than the number of layers shown in <FIG>.

A first upper insulating layer <NUM> and a second upper insulating layer <NUM> may be arranged on the second inorganic insulating layer <NUM>. The second upper insulating layer <NUM> may include a material that is the same as that of the third insulating layer <NUM> in the input sensing layer <NUM> described above with reference to <FIG>. The second upper insulating layer <NUM> may be integrally formed with the third insulating layer <NUM>. The first upper insulating layer <NUM> may include the same material as that of the second insulating layer <NUM> in the input sensing layer <NUM> and may be integrally formed with the second insulating layer <NUM>. In an embodiment, the first upper insulating layer <NUM> may include an inorganic insulating material and the second upper insulating layer <NUM> may include an organic insulating material. The second inorganic insulating layer <NUM> may be integrally formed with the substrate <NUM> to cover the display area DA and the first non-display area NDA1. The second inorganic insulating layer <NUM> may be considered as a part of the second insulating layer <NUM> including a plurality of sub-layers. The first inorganic insulating layer <NUM> arranged under the second inorganic insulating layer <NUM> may include the same material as that of the first insulating layer <NUM> in the input sensing layer <NUM> and may be integrally formed with the first insulating layer <NUM>. According to an embodiment, the second inorganic insulating layer <NUM> and the first upper insulating layer <NUM> may be formed integrally with the sub-layers of the second insulating layer <NUM> in the input sensing layer <NUM>, and the first inorganic insulating layer <NUM> may be integrally formed with the first insulating layer <NUM> of the input sensing layer <NUM>. In this case, the second inorganic insulating layer <NUM> and the first upper insulating layer <NUM> may include materials that are different from or the same as each other. Even when the second inorganic insulating layer <NUM> and the first upper insulating layer <NUM> include the same material (e.g., SiNx), the second inorganic insulating layer <NUM> and the first upper insulating layer <NUM> may be formed in separate processes. Therefore, the second inorganic insulating layer <NUM> and the first upper insulating layer <NUM> may have different composition ratios between silicon and nitrogen and may have an interface therebetween. In some implementations, the first upper insulating layer <NUM> may be integrally formed with the second insulating layer <NUM> of the input sensing layer <NUM>, and the second inorganic insulating layer <NUM> may be integrally formed with the first insulating layer <NUM> of the input sensing layer <NUM>.

The cross-sectional structure shown in <FIG> may be appreciated as a structure surrounding the first opening <NUM> and the opening area OA. For example, the grooves G between the opening area OA and the display area DA may have loop shapes surrounding the first opening <NUM> and the opening area OA, as described above with reference to <FIG>. Likewise, the planarization layer <NUM> of <FIG> may have a loop shape surrounding the first opening <NUM> and the opening area OA, as shown in <FIG>.

Referring to <FIG>, the planarization layer <NUM> may have a loop shape surrounding the opening area OA. The hole <NUM> of the planarization layer <NUM> also has a loop shape surrounding the first opening <NUM> and the opening area OA, and the first portion 720A and the second portion 720B separated from each other based on the hole <NUM> may each have a loop shape. The first and second barrier walls <NUM> and <NUM> may also have the loop shapes surrounding the first opening <NUM> and the opening area OA.

The first opening <NUM> of the display panel <NUM> may be formed by performing a cutting or scribing process after forming the above-stated components and the layers on the substrate <NUM>. For example, the cross-sectional structure of <FIG> may be understood as a cross-section of the display panel <NUM> manufactured by performing a cutting or scribing process along a first line SCL1. End portions of the layers on the substrate <NUM> may be located on the same vertical line as that of an end 100E of the substrate <NUM>, wherein the end 100E defines the first opening <NUM>. For example, an end 710E of the first inorganic insulating layer <NUM>, a second end 720E2 of the planarization layer <NUM>, and an end 730E of the second inorganic insulating layer <NUM> may be located on the same vertical line as that of an end 100E of the substrate <NUM>, which defines an opening <NUM> in the substrate <NUM>. Likewise, ends of the first and second inorganic encapsulation layers <NUM> and <NUM>, the organic material layer 320A, and the first and second upper insulating layers <NUM> and <NUM> may be located on the same vertical line as that of the end 100E of the substrate <NUM>.

A region from the first line SCL1 to an n-th line SCLn shown in <FIG> may be appreciated as a region CA, in which the cutting or scribing process is performed during manufacturing of the display panel. That is, the cutting or scribing process may be performed along one of the first to n-th lines SCL1 to SCLn, and a cross-sectional structure thereof may correspond to the structure of the display panel according to the embodiment(s). <FIG> may correspond to a cross-sectional structure of the display panel <NUM>, on which the cutting or scribing process is performed along the n-th line SCLn.

<FIG> illustrates a plan view showing the first and second inorganic encapsulation layers <NUM> and <NUM> and the first and second inorganic insulating layers <NUM> and <NUM> in the display panel <NUM> according to the embodiment. <FIG> illustrates a cross-sectional view taken along a line XVIII-XVIII' of <FIG>.

Referring to <FIG>, the first and second inorganic encapsulation layers <NUM> and <NUM> may be located on the substrate <NUM> and may entirely cover the display area DA. Also, as described above with reference to <FIG>, etc., the first and second inorganic encapsulation layers <NUM> and <NUM> may entirely cover the first non-display area NDA1 and may partially cover the second non-display area NDA2. On the plane of <FIG>, the first and second inorganic encapsulation layers <NUM> and <NUM> may include edges located on the substantially same vertical lines as those of a left edge, a right edge, and an upper edge of the substrate <NUM>. Edges 310E and 330E of the first and second inorganic encapsulation layers <NUM> and <NUM>, which are adjacent to a pad portion PAD, may be spaced a predetermined distance from the pad portion PAD. For example, the edges 310E and 330E of the first and second inorganic encapsulation layers <NUM> and <NUM> may partially surround the pad portion PAD.

The first and second inorganic insulating layers <NUM> and <NUM> may entirely cover the display area DA and the first non-display area NDA1 of the substrate <NUM> and may partially cover the second non-display area NDA2. An area of a portion in the second non-display area NDA2 where the portion is covered by the first and second inorganic insulating layers <NUM> and <NUM>, may be greater than that of a portion in the second non-display area NDA2, where the portion is covered by the first and second inorganic encapsulation layers <NUM> and <NUM>. In one embodiment, the edges 310E and 330E of the first and second inorganic encapsulation layers <NUM> and <NUM> adjacent to the pad portion PAD may be respectively spaced a predetermined distance from the pad portion PAD, but the first and second inorganic insulating layers <NUM> and <NUM> may cover a remaining portion of the second non-display area NDA2, except for holes <NUM> and <NUM>, which expose a plurality of pads included in the pad portion PAD. Referring to <FIG>, the first and second inorganic insulating layers <NUM> and <NUM> may further extend toward the pad portion PAD beyond the edges 310E and 330E of the first and second inorganic encapsulation layers <NUM> and <NUM>. When the first and second inorganic insulating layers <NUM> and <NUM> further extend as described above, impurities such as moisture may be hindered or prevented from proceeding towards the display area DA along a direction in parallel with the upper surface of the substrate <NUM> during some of the processes (e.g., cleaning process) of forming the planarization layer <NUM> described above with reference to <FIG>.

<FIG> and <FIG> illustrate cross-sectional views of display panels <NUM>' and <NUM>" according to other embodiments. In the above description with reference to <FIG>, the planarization layer <NUM> may include the hole <NUM> and may be arranged as an island in the first non-display area NDA1. In the display panels <NUM>' and <NUM>" of <FIG> and <FIG>, components except for the structure of the planarization layer <NUM> are the same as those of <FIG>, and hereinafter differences will be described.

Referring to <FIG>, the planarization layer <NUM> may be arranged in the first non-display area NDA1 and may not include a hole. For example, the planarization layer <NUM> may entirely cover the first non-display area NDA1. The first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may not contact each other in the first non-display area NDA1. For example, since the planarization layer <NUM> having a loop shape may be located in the first non-display area NDA1 similar to the example illustrated with reference to <FIG>, the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may contact each other in a region where the planarization layer <NUM> is not arranged. When the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> cover the display area DA and the second non-display area NDA2 as described above with reference to <FIG>, the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may contact each other in the display area DA and/or the second non-display area NDA2. In some implementations, when a first end 720E1 of the planarization layer <NUM> is located in the second sub non-display area SNDA2, the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may contact each other in the first sub non-display area SNDA1.

In <FIG>, the planarization layer <NUM> may be arranged in the first non-display area NDA1. In some implementations, the planarization layer <NUM> may extend to the display area DA as shown in <FIG>. The planarization layer <NUM> may include a polymer-based transparent material. In this case, the first inorganic insulating layer <NUM> and the second inorganic insulating layer <NUM> may not contact each other in the first non-display area NDA1 and the display area DA, but only contact each other in the second non-display area NDA2.

Cross-sectional structures respectively shown in <FIG> and <FIG> may be understood as cross-sections of the display panels <NUM>' and <NUM>" manufactured by performing the cutting or scribing process along the first line SCL1. In another embodiment, a region from the first line SCL1 to the n-th line SCLn shown in <FIG> and <FIG> may correspond to a region CA in which the cutting or scribing process is performed during processes of manufacturing the display panel. The cutting or scribing process may be performed along one of the first to n-th lines SCL1 to SCLn, and the cross-sectional structure according to the process may correspond to the structure of the display panel according to the embodiment(s).

As discussed, embodiments provide a display according to the appended claims.

By way of summation and review, in a display apparatus, various functions attached to or linked to the display apparatus may be added while increasing a display area. In order to add various functions to a display apparatus while increasing the display area, an opening may be provided in a display area. However, there is a risk that in a display apparatus including an opening, a film or a layer may be exfoliated or separated around the opening according to structures of the opening and elements arranged around the opening.

One or more embodiments include a display panel, in which an opening having an improved quality is provided,.

One or more embodiments provide the display panel and apparatus including the opening area and/or an opening. The display panel and apparatus may protect display elements against the moisture infiltrating along a direction parallel to the upper surface of the substrate in the display panel (for example, in a lateral direction).

Claim 1:
A display panel (<NUM>), comprising:
a substrate (<NUM>) including an opening area (OA), a display area (DA), and a first non-display area (NDA1), the first non-display area being between the opening area and the display area;
a plurality of display elements arranged in the display area;
a thin film encapsulation layer (<NUM>) that covers the display elements, the thin film encapsulation layer including an inorganic encapsulation layer (<NUM>, <NUM>) and an organic encapsulation layer (<NUM>);
a groove (G) in the first non-display area;
a barrier wall (<NUM>) in the first non-display area;
a planarization layer (<NUM>) in the first non-display area, the planarization layer covering the groove;
a first inorganic insulating layer (<NUM>) under the planarization layer such that the first inorganic insulating layer is between the planarization layer and the substrate; and
a second inorganic insulating layer (<NUM>) over the planarization layer,
wherein the thin film encapsulation layer (<NUM>) is under the first inorganic insulating layer (<NUM>) such that the thin film encapsulation layer is between the first inorganic insulating layer and the substrate (<NUM>), and
wherein in a first region of the first non-display area (NDA1) corresponding to the barrier wall (<NUM>), the second inorganic insulating layer (<NUM>) directly contacts an upper surface of the first inorganic insulating layer (<NUM>), and the first inorganic insulating layer (<NUM>) directly contacts an upper surface of the inorganic encapsulation layer (<NUM>).