Patent Description:
A conventionally known imaging device including a solid-state imaging element has a three-line sensor structure including RGB pixels or a four-line sensor structure capable of reading invisible light such as infrared light in addition to visible light such as RGB.

On the other hand, Patent Literature <NUM> discloses a technique of reducing data transfer speed. In this technique, an image readout signal is converted into digital data, speed conversion is performed using a RAM (random access memory), and then, the data is transferred with LVDS (Low Voltage Differential Signaling).

In the conventional four-line sensor, however, it is considered that the image data for four colors is transferred as image signals to a signal processing IC in a subsequent stage through a dedicated transmission line, and when there are many IF signals between a sensor IC and the signal processing IC, restriction occurs in mounting the ICs, which is a problem.

In addition, in order to handle the image data with four colors, simply, it is only necessary to increase the number of systems. In Patent Literature <NUM>, six systems are used. However, to handle the image data of RGB * <NUM> bits, providing five systems of LVDS data lanes at minimum is enough; therefore, even in a case of handling three or more colors, it is desirable that all the data can be transferred in the five systems. Moreover, increasing the number of lanes results in the restriction when the IC is mounted, which is a problem.

The present invention has been made in view of the above circumstances, and an object is to transfer data at low cost without increasing the number of lanes.

A signal processing device includes a data writing unit, a speed converting unit including memory, a channel number converting unit, and a plurality of serial data transferring unit. The data writing unit is configured to write data of m channels into a memory. The channel number converting unit is configured to output the data read from the memory as data of n channels, where m is larger than n. The plurality of serial data transferring unit is configured to transfer the data of the n channels to a processing device in a subsequent stage. The speed converting unit is configured to cause data reading speed from the memory to be larger as compared to data writing speed into the memory, and to convert data of different numbers of channels m1 and m2 as the data of the m channels into the data of the n channels, and thereby to control the frequency of reading the data from the memory to be the same.

According to an aspect of the present invention, the occurrence of the restriction in mounting the ICs can be suppressed at low cost.

Embodiments of a signal processing device, an imaging device, a reading device, an image forming device, and a signal processing method are hereinafter described in detail with reference to the accompanying drawings.

<FIG> is a diagram illustrating a structure of one example of an image forming device <NUM> according to a first embodiment. In <FIG>, the image forming device <NUM> is a generally called multifunction peripheral having at least two functions among a copying function, a printer function, a scanner function, and a facsimile function.

The image forming device <NUM> includes an image reading device <NUM>, which is a reading device, and an ADF (Automatic Document Feeder) <NUM>, and also includes an image forming unit <NUM> below them. As for the image forming unit <NUM>, an internal structure with an external cover detached therefrom is illustrated in order to describe the internal structure.

The ADF <NUM> is a document supporting unit that positions a document containing an image to be read at a reading position. The ADF <NUM> automatically conveys the document on a mount table to the reading position. The image reading device <NUM> reads the document conveyed by the ADF <NUM> at the predetermined reading position. In addition, the image reading device <NUM> includes a contact glass, which is the document supporting unit to have the document thereon, on an upper surface thereof, and reads the document on the contact glass corresponding to the reading position. Specifically, the image reading device <NUM> is a scanner including a light source, an optical system, and a solid-state imaging element such as a CMOS image sensor inside. The image reading device <NUM> reads the reflection light from the document illuminated with the light source using the solid-state imaging element through the optical system.

The image forming unit <NUM> includes a manual paper feeding roller <NUM> to which recording paper is fed by hand, and a recording paper supplying unit <NUM> that supplies the recording paper. The recording paper supplying unit <NUM> has a mechanism that feeds the recording paper from a recording paper feeding cassette 107a with multiple stages. The supplied recording paper is sent to a secondary transfer belt <NUM> through a registration roller <NUM>.

On the recording paper conveyed on the secondary transfer belt <NUM>, a toner image on an intermediate transfer belt <NUM> is transferred at a transfer unit <NUM>.

In addition, the image forming unit <NUM> includes an optical writing device <NUM>, a tandem system image forming unit (Y, M, C, K) <NUM>, the intermediate transfer belt <NUM>, the aforementioned secondary transfer belt <NUM>, and the like. Through the image formation process by the image forming unit <NUM>, the image written by the optical writing device <NUM> can be formed on the intermediate transfer belt <NUM> as the toner image.

Specifically, the image forming unit (Y, M, C, K) <NUM> includes four photoconductor drums (Y, M, C, K) in a manner that the photoconductor drums are rotatable. Around each photoconductor drum, an image forming element <NUM> is provided. The image forming element <NUM> includes a charging roller, a developing device, a primary transfer roller, a cleaner unit, and a static eliminator. In each photoconductor drum, the image forming element <NUM> functions and the image on the photoconductor drum is transferred onto the intermediate transfer belt <NUM> by each primary transfer roller.

The intermediate transfer belt <NUM> is disposed at a nip between each photoconductor drum and each primary transfer roller with a tension applied by a driving roller and a driven roller. The toner image that is transferred by the primary transfer to the intermediate transfer belt <NUM> is transferred by the secondary transfer onto the recording paper on the secondary transfer belt <NUM> by a secondary transfer device as the intermediate transfer belt <NUM> runs. The recording paper is conveyed to a fixing device <NUM> as the secondary transfer belt <NUM> runs, and the toner image is fixed on the recording paper as a color image. After that, the recording paper is discharged to a paper ejection tray outside the machine. In a case of duplex printing, the recording paper is turned over by an inverting mechanism <NUM> and the inverted recording paper is sent onto the secondary transfer belt <NUM>.

Note that the image forming unit <NUM> is not limited to forming the image by an electrophotography method as described above, and may form the image by an inkjet method.

Next, the image reading device <NUM> is described.

<FIG> is a cross-sectional view illustrating an example of a structure of the image reading device <NUM>. As illustrated in <FIG>, the image reading device <NUM> includes a sensor board <NUM> including an imaging device <NUM>, a lens unit <NUM>, a first carriage <NUM>, and a second carriage <NUM> inside a main body <NUM>. The first carriage <NUM> includes a light source <NUM>, which is an LED (Light-Emitting Diode), and a mirror <NUM>. The second carriage <NUM> includes mirrors <NUM> and <NUM>. The image reading device <NUM> also has a contact glass <NUM> and a reference white board <NUM> on an upper surface thereof.

In the reading operation, the image reading device <NUM> causes the light source <NUM> to emit light upward while moving the first carriage <NUM> and the second carriage <NUM> from a standby position (home position) in a sub-scanning direction (A-direction). Then, the first carriage <NUM> and the second carriage <NUM> form an image with the reflection light from a document <NUM> on the imaging device <NUM> through the lens unit <NUM>.

The image reading device <NUM> sets the reference by reading the reflection light from the reference white board <NUM> when the power is turned on, for example. That is to say, the image reading device <NUM> moves the first carriage <NUM> right below the reference white board <NUM>, turns on the light source <NUM>, and causes the reflection light from the reference white board <NUM> to form the image on the imaging device <NUM>; thus, gain control is performed.

In the imaging device <NUM> (see <FIG>), pixels for converting the quantity of incident light into electric signals are arranged. The pixels are arranged in matrix, and the electric signals obtained from the pixels are transferred to a signal processing unit <NUM> (see <FIG>) in a subsequent stage in a predetermined order for every certain time (pixel readout signals). On each pixel, a filter that transmits light with a particular wavelength is disposed. In the imaging device <NUM> according to the present embodiment, each signal obtained from the pixel group where the same filter is disposed is called a channel.

<FIG> is a block diagram illustrating electric connection of each unit in the image reading device <NUM>. As illustrated in <FIG>, the image reading device <NUM> includes an image processing unit <NUM>, a control unit <NUM>, and a light source driving unit <NUM> in addition to the imaging device <NUM> and the light source <NUM> described above. The light source driving unit <NUM> drives the light source <NUM>.

The imaging device <NUM> includes a solid-state imaging element <NUM> and the signal processing unit <NUM> corresponding to a signal processing device. The solid-state imaging element <NUM> is a sensor for a reduction optical system, and for example, a CMOS image sensor or the like. The solid-state imaging element <NUM> includes a pixel array <NUM>. The pixel array <NUM> includes a number of photodiodes (PDs) arranged in matrix to form the pixels, and transfers photoelectric conversion results to the signal processing unit <NUM> in the subsequent stage in a predetermined order.

The signal processing unit <NUM> includes a gain control unit (amplifier), an offset control unit, an A/D conversion unit (ADC circuit), and the like. The signal processing unit <NUM> performs gain control, offset control, A/D conversion, and the like for the image signals (R/G/B/NIR) output from the solid-state imaging element <NUM>.

The control unit <NUM> controls the setting of each unit of the light source driving unit <NUM>, the solid-state imaging element <NUM>, the signal processing unit <NUM>, and the image processing unit <NUM>.

The image processing unit <NUM> performs various image processes.

Next, a circuit structure of each of the signal processing unit <NUM> and the image processing unit <NUM> is described in detail.

Here, <FIG> is a diagram illustrating a circuit structure example of the signal processing unit <NUM> and the image processing unit <NUM> in the image reading device <NUM>.

In the present embodiment, each of m and n is an integer of <NUM> or more satisfying m > n. In the description of the present embodiment, the image data acquired by the solid-state imaging element <NUM> is processed; however, the signal processing device with the structure according to the present invention is not limited to the case of handling the image data only.

As illustrated in <FIG>, the signal processing unit <NUM> includes ADC circuits <NUM>, a speed conversion circuit <NUM> corresponding to a data writing unit and a speed converting unit, a channel number conversion circuit <NUM> corresponding to a channel number converting unit, a data transfer clock generation circuit <NUM>, a mapping circuit <NUM>, a parallel-serial circuit <NUM>, a data transfer circuit <NUM>, a data storage clock generation circuit <NUM>, a control register <NUM>, and the like. The control register <NUM> stores various settings therein through the control unit <NUM>.

As illustrated in <FIG>, in the signal processing unit <NUM>, the ADC circuits <NUM> convert pixel readout signals (A1 to Am) obtained for every channel from the solid-state imaging element <NUM> into digital data (DI1 to DIm) with <NUM> bits. The DI1 to DIm signals resulting from the conversion are written in the speed conversion circuit <NUM> in synchronization with a speed conversion circuit writing clock (WCLK) with the same frequency as a pixel readout frequency. Note that WCLK is generated by the data storage clock generation circuit <NUM>.

The data written in the memory of the speed conversion circuit <NUM> is read out in synchronization with a speed conversion circuit readout clock (RCLK). Note that RCLK is generated by a data transfer clock generation circuit <NUM> that generates a data transfer clock (SERCLK).

The data (DO1 to DOm) of m channels and <NUM> bits that is read from the memory in the speed conversion circuit <NUM> is converted into data of n channels (D1 to Dn) with <NUM> bits that synchronizes with MCLK by the channel number conversion circuit <NUM>. Note that MCLK is generated by the data transfer clock generation circuit <NUM> that generates the data transfer clock (SERCLK).

Here, the channel number conversion circuit <NUM> included in the signal processing unit <NUM> is described in detail. <FIG> is a diagram illustrating one example of a structure of the channel number conversion circuit <NUM> included in the signal processing unit <NUM>. Here, m is four and n is three. As illustrated in <FIG>, the channel number conversion circuit <NUM> includes a data reordering unit <NUM>, a process selection register <NUM>, and a selector <NUM>. In the channel number conversion circuit <NUM>, the data reordering unit <NUM> reorders the four-channel image data (DO1 to DO4) read out from the speed conversion circuit <NUM> to generate the three-channel image data (D1 to D3).

The selector <NUM> selectively outputs the three-channel image data (D1 to D3) to be output to the subsequent stage by the control through the process selection register <NUM>.

Note that the channel number conversion circuit <NUM> may have a function of selecting a part of the multiple-channel image data that is input and outputs the selected image data without reordering the data. For example, in a case where just the predetermined three-channel image data (DO1 to DO3) is required in the image processing unit <NUM>, the predetermined three-channel image data may be output by bypassing the data reordering unit <NUM> as illustrated in <FIG>. Thus, just by the setting of the process selection register <NUM>, the three-channel or four-channel image data transfer switching becomes possible in one device without the necessity of changing the circuits or switching the transmission line.

The data (D1 to Dn) converted by the channel number conversion circuit <NUM> is transferred to the image processing unit <NUM> through the mapping circuit <NUM>, the parallel-serial circuit <NUM>, and the data transfer circuit <NUM> in the subsequent stage. The mapping circuit <NUM> performs a mapping process on the data (D1 to Dn) converted by the channel number conversion circuit <NUM>, and for example, obtains five systems of MA to ME signals with <NUM> bits. The parallel-serial circuit <NUM> performs parallel-serial conversion on the MA to ME signals, and obtains SA to SE signals synchronizing with the SERCLK signal. Moreover, the image processing unit <NUM> generates a transfer data synchronizing clock SCK for carrying out the serial-parallel conversion. Therefore, the channel number conversion circuit <NUM>, the mapping circuit <NUM>, the parallel-serial circuit <NUM>, and the data transfer circuit <NUM> achieve a data transferring unit.

On the other hand, as illustrated in <FIG>, the image processing unit <NUM> includes a data transfer circuit <NUM>, a serial-parallel circuit <NUM>, a mapping circuit <NUM>, a channel number conversion circuit <NUM>, a memory <NUM>, various image processing circuits <NUM>, an image process clock generation circuit <NUM>, and the like.

As illustrated in <FIG>, in the image processing unit <NUM>, the channel number conversion circuit <NUM> converts the data of n channels and <NUM> bits, which has been transmitted through the serial-parallel circuit <NUM> and the mapping circuit <NUM> in the subsequent stage, into data of m channels and <NUM> bits (PI1 to PIm) and writes the data into the memory <NUM> that is provided for the m channels using the clock (PCLK) synchronizing with the clock that is transferred together with the data through the data transfer circuit <NUM>. The process in the various image processing circuits <NUM> after the memory is read out in the image processing unit <NUM> is performed in synchronization with the clock (SCLK) generated by the image process clock generation circuit <NUM>.

Note that in the subsequent description, as one example, the number of channels m of input data from the solid-state imaging element <NUM> is four and the number of channels n of data transfer is three. Note that m is not limited to four and n is not limited to three.

Next, the data process in the signal processing unit <NUM> is described in detail. Here, <FIG> is a timing chart illustrating one example of the data process in the signal processing unit <NUM>. In the example illustrated in <FIG>, the four-channel image data is processed in the signal processing unit <NUM>.

Note that in <FIG>, the details ranging from the output of the solid-state imaging element <NUM> to the process of generating the digital data by the ADC circuit <NUM> are omitted.

As illustrated in <FIG>, the output (DI1 to DI4) from the ADC circuit <NUM> is written in the speed conversion circuit <NUM> in synchronization with WCLK. The image data readout from the speed conversion circuit <NUM> is performed in synchronization with the clock RCLK different from WCLK. When the frequency of writing in and reading from the speed conversion circuit <NUM> is the same, the readout from the speed conversion circuit <NUM> overtakes the writing in the speed conversion circuit <NUM>. Thus, it is necessary to write in the speed conversion circuit <NUM> in advance, and a large-scaled speed conversion circuit is mounted. The clock generation circuit (data storage clock generation circuit <NUM>) for writing in the speed conversion circuit <NUM> and the clock generation circuit (data transfer clock generation circuit <NUM>) for reading from the speed conversion circuit <NUM> are provided separately, so that the frequencies of WCLK, and RCLK and MCLK are made independently controllable by the control unit <NUM> as appropriate, which is described below. Thus, the circuit scale of the speed conversion circuit <NUM> that is necessary in the present invention can be minimized.

As illustrated in <FIG>, the frequencies of WCLK, and RCLK and MCLK are made independently controllable by the control unit <NUM>, so that the data transfer speed can be set as appropriate regardless of the number of image data channels to handle.

That is to say, the clock generation circuit (data storage clock generation circuit <NUM>) for writing in the speed conversion circuit <NUM> and the clock generation circuit (data transfer clock generation circuit <NUM>) for reading from the speed conversion circuit <NUM> are provided separately, so that the speed of reading from the speed conversion circuit <NUM> can be made higher than the speed of writing in the speed conversion circuit <NUM> and thus, the number of channels can be reduced. In the case of generating the writing and reading clocks in one clock generation circuit, the readout is late and therefore, many memory circuits are required.

In the example of converting the image data for four channels illustrated in <FIG> into three channels, the data for three channels that is transferred per clock MCLK is the data for three pixels obtained from one desired channel among the four-channel image data that is input to the channel number conversion circuit <NUM>. Thus, in all the data transfer periods, the data to transfer is selected without the transfer of the invalid image data; therefore, the invalid pixel data is not multiplied in the entire clocks and all the necessary data can be transferred with the minimum clocks. Note that in the case of transferring the data for every two pixels in one clock MCLK, for example, the loss for one pixel occurs in every clock.

Note that, in the timing chart in <FIG>, the signal processing unit <NUM> controls RCLK used to read from the speed conversion circuit <NUM> such that the frequency of RCLK is equal to the frequency of MCLK but only three pulses are generated among four pulses. It is only necessary that RCLK can read out at such a speed that the speed difference between writing and reading can be absorbed, and for example, the clock with the frequency equal to the frequency of WCLK synchronizing with MCLK may be used.

In a case where the number of channels m of the input data from the solid-state imaging element <NUM> is four and the number of channels n of the data transfer is three, MCLK is generated in the clock generation circuit (data transfer clock generation circuit <NUM>) that is different from the clock generation circuit (data storage clock generation circuit <NUM>) that generates WCLK. The frequency of MCLK is <NUM>/<NUM> times (m/n times) the frequency of WCLK. When the frequency of MCLK is <NUM>/<NUM> times the frequency of WCLK, the writing bit rate and the reading bit rate become equal and the number of stages in the memory (circuit scale) of the speed conversion circuit can be reduced. Thus, the writing in the speed conversion circuit <NUM>, the reading from the speed conversion circuit <NUM>, and the data transfer can be performed efficiently and the size of the speed conversion circuit <NUM> can be minimized.

In the signal processing unit <NUM> where the speed conversion circuit <NUM> with a large scale can be mounted, the frequency ratio between MCLK and WCLK may be set freely. For example, the frequency of MCLK may be equal to or more than <NUM>/<NUM> times the frequency of WCLK. By causing the data transfer frequency to be higher in this manner, the data transfer can be performed in a short time. When the frequency of MCLK is equal to or more than <NUM>/<NUM> times (m/n times) the frequency of WCLK, the power consumption can be reduced by turning off the data transfer circuit <NUM> in the case where the data transfer is not performed (except the valid data transfer period), for example. Even in the case of processing the different number of channels m, the data transfer frequency can be unified and the transmission route design or the noise countermeasure component can be made common.

Moreover, the frequency of MCLK may be equal to or less than <NUM>/<NUM> times (m/n times) the frequency of WCLK. In this case, the data transfer frequency can be reduced. The high transfer frequency results in the electromagnetic noise (EMI noise) in the transmission route, the deterioration in transmission signal quality, or the increase in consumption power; therefore, causing the frequency of MCLK to be equal to or less than <NUM>/<NUM> times the frequency of WCLK is effective to suppress these problems. Even in the case of processing the different number of channels m, the data transfer frequency can be unified and the transmission route design or the noise countermeasure component can be made common.

In the case of transferring the image data for four channels or three channels in the signal processing unit <NUM> with the structure that can process the image data for four channels, the control unit <NUM> controls so that the transfer frequency becomes equal regardless of the number of channels included in the data to transfer. That is to say, the data transfer frequency is made the same at the four-color data transfer and the three-color data transfer.

In other words, when the digital data with different numbers of channels m1 and m2 as the digital data of m channels is converted into the data of n channels, the speed conversion circuit readout frequency is controlled to be the same. Thus, since the data transfer frequency can be set to be a constant frequency regardless of the number of image channels m to handle, it is possible to handle the reflection or the dull shape of waveform to be considered in the design of the transmission line in consideration of just the limited frequency. It is only necessary that the EMI countermeasure components and the like are applicable to just a particular frequency and the number of steps in the design and the mount cost can be reduced.

Next, the data process in the image processing unit <NUM> is described in detail.

Here, <FIG> is a timing chart illustrating one example of the data process in the image processing unit <NUM>. In the example illustrated in <FIG>, the image data for four channels is processed in the image processing unit <NUM>.

As illustrated in <FIG>, in the image processing unit <NUM>, the serial-parallel circuit <NUM> performs serial-parallel conversion on the signal that is transferred through the data transfer circuit <NUM>, and then the mapping circuit <NUM> performs a process opposite to the mapping performed in the signal processing unit <NUM>; thus, signals with three channels P1 to P3 with <NUM> bits are obtained. The image data formed of P1 to P3 is converted into signals with four channels by the channel number conversion circuit <NUM>. The data is reordered to become opposite to the order obtained at the channel number conversion in the signal processing unit <NUM>.

As illustrated in <FIG>, the image data for four channels includes one unnecessary image data among four data and the unnecessary image data is not written in the memory <NUM>. The image data read from the memory <NUM> does not include the unnecessary image data, and the image data for four channels obtained in the signal processing unit <NUM> is demodulated directly.

In the present embodiment, the number of channels m of the input data is four and the number of channels n of the data transfer is three. Specifically, in another possible structure of each channel, the input channels may be the image data for three colors of visible light R/G/B and the image data obtained from invisible light such as near-infrared light (NIR). In this case, if the invisible light image is required, the number of input channels is four and if not required, the number of input channels is three.

According to the structure in the present embodiment, for the data transfer from the signal processing unit <NUM> to the image processing unit <NUM>, the data transfer lanes for three channels may be provided regardless of whether the invisible light image needs to be acquired.

According to the present embodiment, the solid-state imaging element <NUM> transfers the image data for m channels to the image processing unit <NUM> through the data transfer circuit <NUM> for n channels, so that the data transfer becomes possible with the same circuit structure as that in transfer of the data of n channels. Therefore, it is unnecessary to provide another transmission route for transferring the data of m channels and the additional increase of the mount area or components can be prevented. Accordingly, the number of lanes is not increased and the data can be transferred at low cost.

Since the on-board structure that is necessary for the data transfer is the same regardless of the readout channel, the imaging device capable of the image data transfer in a manner that the readout of the visible light (three colors of RGB) and readout of the image by lighting the visible light and the invisible light at the same time (RGB + NIR) are performed in one circuit structure can be achieved.

Moreover, for example, even an imaging device reads the visible light and the invisible light (m-color reading device), when the imaging device that does not require the invisible image information, changing to the data transfer speed equivalent to in the n-color reading device can be made by only setting; thus, the consumption can be reduced.

In the present embodiment, the data transfer circuits <NUM> and <NUM> between the signal processing unit <NUM> and the image processing unit <NUM> are not limited to particular circuits; however, the data transfer may be performed using a low-amplitude differential signal outputting unit such as LVDS (Low Voltage Differential Signaling) or VbyOne (registered trademark). By employing the differential signal output as above, the noise resistance is improved and thus, it is effective when the data transfer frequency is high and the long-distance transmission is performed.

The signal processing unit <NUM> in the image reading device <NUM> according to the second embodiment is different from that in the first embodiment in that the number of channels for writing in the speed conversion circuit <NUM> is restricted. In the second embodiment, the description of the same part as in the first embodiment is omitted and the point different from the first embodiment is described.

<FIG> is a diagram illustrating a circuit structure example of the signal processing unit <NUM> and the image processing unit <NUM> in the image reading device <NUM> according to the second embodiment.

As illustrated in <FIG>, in a case where the signal processing unit <NUM> that can process the image data for m channels (for example, four channels) requires just the image data for n channels (for example, three channels), the writing in the speed conversion circuit <NUM> is restricted only to the image data for n channels, not the entire m channels.

Specifically, the signal processing unit <NUM> in the image reading device <NUM> stores, in the speed conversion circuit <NUM>, just the digital data about the n channels that are less than or equal to the m channels selected from the digital data of the m channels that is input to the speed conversion circuit <NUM>.

By acquiring the image data while reducing the number of channels in this manner, the access to (writing in) the speed conversion circuit <NUM> can be reduced. Thus, the number of writing accesses to the speed conversion circuit <NUM> can be reduced and the consumption power can be reduced.

The signal processing unit <NUM> in the image reading device <NUM> according to the third embodiment is different from that in the first embodiment in that the number of channels for reading from the speed conversion circuit <NUM> is restricted. In the third embodiment, the description of the same part as in the first embodiment is omitted and the point different from the first embodiment is described.

<FIG> is a diagram illustrating a circuit structure example of the signal processing unit <NUM> and the image processing unit <NUM> in the image reading device <NUM> according to the third embodiment.

As illustrated in <FIG>, in a case where the signal processing unit <NUM> that can process the image data for m channels (for example, four channels) requires just the image data for n channels (for example, three channels), the reading from the speed conversion circuit <NUM> is restricted only to the image data for n channels, not the entire m channels.

Specifically, the signal processing unit <NUM> in the image reading device <NUM> reads out just the digital data about the n channels that are less than or equal to the m channels selected from the digital data of the m channels that is stored in the speed conversion circuit <NUM>.

By acquiring the image data while reducing the number of channels in this manner, the access to (readout from) the speed conversion circuit <NUM> can be reduced. Thus, the number of reading accesses from the speed conversion circuit <NUM> can be reduced and the consumption power can be reduced.

The signal processing unit <NUM> in the image reading device <NUM> according to the fourth embodiment is different from that in the first embodiment to the third embodiment in that the data is selected and output sequentially in each channel for each pixel in every channel as the data for n channels (for example, three channels) that is transferred per MCLK clock. In the description of the fourth embodiment, the description of the same parts as those of the first embodiment to the third embodiment is omitted and the point different from the first embodiment to the third embodiment is described.

<FIG> is a timing chart illustrating one example of the data process in the signal processing unit <NUM> according to the fourth embodiment. In the example illustrated in <FIG> in which the image data for four channels is converted into three channels, the data is selected and output sequentially for each pixel in every one of the m channels as the data for three channels that is transferred per MCLK clock. More specifically, in one MCLK clock period, for example, the data is transferred in the order of (channel <NUM>, channel <NUM>, channel <NUM>), (channel <NUM>, channel <NUM>, channel <NUM>), (channel <NUM>, channel <NUM>, channel <NUM>), and (channel <NUM>, channel <NUM>, channel <NUM>). In all the data transfer periods, the data to transfer is selected while the invalid image data is not transferred. Thus, in the entire clocks, the invalid pixel data is not multiplied and therefore, all the data can be transferred with the minimum clocks. Note that in the case of transferring the data for two pixels in one MCLK clock, the loss for one pixel occurs in every clock.

The signal processing unit <NUM> in the image reading device <NUM> according to the fifth embodiment is different from that in the first embodiment to the fourth embodiment in that the number of channels for writing in the speed conversion circuit <NUM> is larger than the number of channels for reading from the speed conversion circuit <NUM>. In the description of the fifth embodiment, the description of the same parts as those of the first embodiment to the fourth embodiment is omitted and the point different from the first embodiment to the fourth embodiment is described.

<FIG> is a timing chart illustrating one example of the data process in the signal processing unit <NUM> according to the fifth embodiment. In the first embodiment, etc., the writing in the speed conversion circuit <NUM> and the reading from the speed conversion circuit <NUM> are performed by the same number of channels. In the present embodiment, the number of channels for reading from the speed conversion circuit <NUM> (for example, three channels) is smaller than the number of channels for writing in the speed conversion circuit <NUM> (for example, four channels) as illustrated in <FIG>.

In the structure of the present embodiment, RCLK for reading the speed conversion circuit and MCLK for transferring the data are also the same clock.

In this structure, by the readout control for the speed conversion circuit <NUM>, for example, the image data for four channels is written at one time and at the readout, the data storage address in which the data is written is designated so that the image data for three channels can be read out. Thus, the readout from the speed conversion circuit and the channel number conversion can be performed at the same time. In this case, the channel number conversion after the readout from the speed conversion circuit is unnecessary.

The image processing unit <NUM> according to the sixth embodiment is different from that in the first embodiment to the fifth embodiment in that the pixel array <NUM> and the signal processing unit <NUM> are provided as one element of the solid-state imaging element <NUM>. In the description of the sixth embodiment, the description of the same parts as those of the first embodiment to the fifth embodiment is omitted and the point different from the first embodiment to the fifth embodiment is described.

<FIG> is a diagram illustrating a circuit structure example of the image reading device <NUM> according to the sixth embodiment. As illustrated in <FIG>, in the image reading device <NUM>, the imaging device <NUM> includes the pixel array <NUM> and the signal processing unit <NUM> as one element of the solid-state imaging element <NUM>.

In this manner, the pixel array <NUM> that converts the input light into the electric signals and the signal processing unit <NUM> that converts the output signal of the pixel array <NUM> into the digital data are made into one chip as the solid-state imaging element <NUM>. Thus, the wiring on the board that connects the pixel array <NUM> and the signal processing unit <NUM> or the circuit used to exchange the signals become unnecessary. In particular, in the image reading device <NUM> that acquires the image data at high speed, the signals that control the pixel array <NUM> and the signal processing unit <NUM> also need to be operated at high speed, and the board needs to have the layout in consideration of the crosstalk of the control signals on the board and the like. By forming one chip as described in the present embodiment, the restriction at the layout on the board is reduced.

The structures of the embodiments described above can be carried out in combination with each other as appropriate unless contradicting each other.

Claim 1:
A signal processing device (<NUM>) comprising:
a speed converting unit (<NUM>) including a memory;
a data writing unit (<NUM>) configured to write data of m channels into the memory;
the speed converting unit (<NUM>) being configured to cause data reading speed from the memory to be larger as compared to data writing speed into the memory,
a channel number converting unit (<NUM>) configured to output the data read from the memory as data of n channels, m being larger than n;
a plurality of serial data transferring units (SA-SE) configured to transfer the data of the n channels to a processing device (<NUM>) in a subsequent stage,
the speed converting unit (<NUM>) is configured to convert data of different numbers of channels m1 and m2 as the data of the m channels into the data of the n channels, and thereby to control the frequency of reading the data from the memory to be the same.