Patent Description:
The use of compression at the page level to create memory hierarchy or tiers, such as in a Linux ZSWAP implementation, is becoming increasingly important. During memory page swaps, instead of sending swapped pages out to disk, they are compressed and stored in memory. The idea is to increase the effective memory capacity while achieving better performance than swapping directly to a slower memory tier. The ideal performance goal is to maximize the memory savings via page compression while minimizing the performance impacts to applications when compared to systems that utilize large memory capacity but with no compression. The key requirement to achieving this, of course, is low latency compression and decompression.

Typically, systems that utilize compression at the page level tend to use relatively lightweight compression algorithms such as Lempel-Ziv-Oberhumer (LZO). This class of algorithms has the advantage of higher speed at the cost of reduced compression. Studies have shown that the use of software-based LZO typically yields a modest amount (~<NUM>%) of memory savings. Other more aggressive algorithms, such as Deflate, offer better compression ratios but suffer from increased compression and decompression latencies. These more aggressive algorithms also tend to make software-based implementation difficult. Any optimization that can improve the latencies associated with compression/decompression operations is therefore highly desirable.

<CIT> relates to methods, computer readable media, and systems for scalable dictionary-based compression. For example, a method for scalable dictionary-based compression includes the steps of receiving, by a processor, a request to retrieve a value stored in a first granule among a plurality of granules and determining, by the processor, that each of the values of the first granule has a uniform value based on a first compression state information (CSI), which corresponds with the first granule. Each granule in the plurality of granules is associated with a plurality of memory locations of a memory for storing a plurality of values, and each of the plurality of granules is associated with corresponding CSI. In response to determining that each of the values in the first granule has a uniform value, the processor determines whether the uniform value is present in a global table or a local table based on the first CSI. If the uniform value is associated with the global table, the processor retrieves the uniform value from the global table using an index associated with the first CSI. If the uniform value is associated with the local table, the processor retrieves the uniform value from the local table using an index associated with the first CSI.

Embodiments of apparatus and method for detecting constant value(s) in a data block during the compression of that data block are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention.

For clarity, individual components in the Figures herein may be referred to by their labels in the Figures, rather than by a particular reference number.

In typical memory usage, a significant number of the memory pages, also referred to herein as memory blocks or data blocks, are comprised of repeat instances of the same bit sequence (e.g., a constant value). For example, a typical memory page of <NUM> bytes (4KB) can include <NUM> (<NUM>) instances of the same constant byte (e.g., 0x00 or 0xFF). Because of their repetitive nature, performing compression and/or decompression on these memory pages use up valuable resources that could otherwise be saved.

Embodiments of the present invention advantageously improves the compression and decompression performance for memory page with minimal area cost and design complexity. For example, an accelerator that performs compression operation may be augmented with a new constant detect functionality. During a compression operation, such as Deflate compression or any nested compression method, the input data block or stream is checked to see if it contains the same constant value over and over. An indication is then associated with the data block based on the result. For example, an aggregate field in a completion record may be updated with the result of the check. Thereafter, the OS or system software can check that field and intelligently decide whether to keep the compressed data block or to represent it with meta-data signaling a constant data block. The constant detection feature may be enabled across multiple jobs via save/restore state.

According to an embodiment, instead of compressing a constant data block with a compression algorithm and storing them in memory, a few extra bits of metadata is maintained in a data structure to identify these data blocks as special blocks of constants which can be regenerated from much less stored data. This not only decreases the latency associated with compression and decompression, but also improves the compressibility as less memory footprint is required for storage.

According to an embodiment, a constant detect functionality is added to augment the compression operations performed by a hardware accelerator. For example, a check may be performed on an input data block or data stream to see if it is made up of repeat instances of the same constant, which can be a bit string of any specified length (e.g., byte (<NUM>-bits), word (<NUM>-bits), doubleword (<NUM>-bits), etc.). If the data block is comprised of only repeat instances of the same constant, it is considered a constant data block. Conversely, if the data block includes values other than the same constant, it is not a constant data block.

The check for repeating constants in a data block, according to an embodiment, is performed separately from its compression. Accordingly, the check may be performed at any time before, after, or during the compression of the data block. In some embodiments, the result of the check is provided as supplemental information associated with the data block and is usable by the operating system (OS) or other system software/hardware to control subsequent operations (e.g., storage, decompression, etc.) associated therewith. For example, according to an embodiment, if the result of the constant detection indicates that the data block is not a constant data block, the compression operations proceed as normal and the compressed data block is stored to the memory hierarchy (e.g., system memory or cache). On the other hand, if the result indicates that the data block is a constant data block, information (e.g., metadata) may be associated or attached to the data block to signal to the OS and/or other system software/hardware that the compressed form of the data block may be discarded to save or free up memory space. In addition, metadata may be stored in a data structure (e.g., a directory or an input buffer) to be used later for regenerating the data block. In some situations, the result of the check may even cause compression operation to be aborted.

In one embodiment, instead of issuing separate jobs for compressing the data block and checking for constant(s), which incurs additional latency, the constant detection of the data block is performed automatically and concurrently with the compression of the data block. That is, responsive to a request to compress a data block, a hardware accelerator conducts both the constant check operations and compression operations on the data block, and outputs a compressed data block as well as the result of the constant check. The outputted compressed data block and result may be stored in the memory hierarchy or other storage locations. The operating system and/or other system software/hardware may subsequently use this result to determine whether to keep or discard the compressed data block.

<FIG> illustrates an exemplary processor on which embodiments of the invention may be implemented. CPU <NUM> may include one or more processor cores. The details of a single processor core ("Core <NUM>") are illustrated in <FIG> for simplicity. It will be understood, however, that each core shown in <FIG> may have the same or similar set of components as Core <NUM>. For example, each core may include dedicated Level <NUM> (L1) cache <NUM> and Level <NUM> (L2) cache <NUM> for caching instructions and data according to a specified cache management policy. The L1 cache <NUM> may additionally include an instruction cache <NUM> for storing instructions and a data cache <NUM> for storing data. The instructions and data stored within the various processor caches are managed at the granularity of cache lines which may be a fixed size (e.g., <NUM>, <NUM>, <NUM> Bytes in length). Data may be stored temporarily in register file <NUM> during the execution of instructions. Register file <NUM> may include general purpose registers (GPRs), vector registers, mask registers, etc. Each processor core further includes an instruction fetch unit <NUM> for fetching instructions from main memory <NUM> and/or a shared Level <NUM> (L3) cache <NUM>; a decoder or decode unit <NUM> for decoding the instructions (e.g., decoding program instructions into micro-operatons or "uops"); an execution unit <NUM> for executing the instructions; and a writeback unit <NUM> for retiring instructions and writing back results.

The instruction fetch unit <NUM> may include various well known components including a next instruction pointer <NUM> for storing the address of the next instruction to be fetched from memory <NUM> (or one of the caches); an instruction translation look-aside buffer (ITLB) <NUM> for storing a map of recently used virtual-to-physical instruction addresses to improve the speed of address translation; a branch prediction unit <NUM> for speculatively predicting instruction branch addresses; and branch target buffers (BTBs) <NUM> for storing branch addresses and target addresses. Once fetched, instructions are streamed to the remaining stages of the instruction pipeline including the decode unit <NUM>, the execution unit <NUM>, and the writeback unit <NUM>. The structure and function of each of these units is well understood by those of ordinary skill in the art and will not be described here in detail to avoid obscuring the pertinent aspects of the different embodiments of the invention.

The processor core may include an accelerator <NUM> for performing compression and decompression operations. The accelerator <NUM> may be implemented in hardware, software, or a combination thereof, and may be communicatively coupled to cores <NUM>-N and the system memory <NUM> via the interconnect <NUM>. In operation, the accelerator <NUM> may receive a data block and responsively generate a compressed data block by performing compression operations on the data block in accordance to a compression algorithm such as LZO, Deflate, or any nested compression method. In addition, the accelerator <NUM> may perform decompression operations on a compressed data block to generate an uncompressed data block.

<FIG> illustrates another exemplary processor on which embodiments of the present invention may be implemented. In <FIG>, one or more cores of processor <NUM> may each include its own accelerator <NUM> to perform the compression and/or decompression operations described herein. The accelerator <NUM> may be implemented instead of, or in addition to, the accelerator <NUM> of <FIG>.

<FIG> illustrates various memory operations implemented in a processor, such as processor <NUM> from <FIG> and <FIG>. A memory copy operation <NUM> is used to copy a memory page from memory to cache or vice versa. It may also be used to copy a memory page from a memory or cache to another location within the same memory or cache. A compress operation <NUM> takes a memory page from memory or cache, compresses it, and stores the resulting compressed page to a location within the memory or cache. An associated decompression operation <NUM> takes a compressed page from memory or cache, decompresses it and stores the decompressed result to a location within the memory or cache. Additional operations such as decryption <NUM> and filtering <NUM> may also be performed with the decompression operation <NUM>. The memory operations may also include various other specialized operations <NUM> that are performed on pages from the memory or cache.

<FIG> illustrates an embodiment of the constant detection operation/functionality in relation to the other memory operations. Specifically, the constant detection operation <NUM> is performed separately and alongside the compression operation <NUM>. It may be performed on memory pages from either the memory or cache. The output from the constant detection operation <NUM> may be stored to the memory or cache, and/or provided to supplement the compression operation <NUM>, as detailed further below.

<FIG> illustrate various operations of an accelerator according to embodiments of the present invention. One skilled in the art will recognize that some elements are intentionally omitted so as not to obscure the key aspects. Other elements, while illustrated, may be optional and thus can be omitted to accommodate the desired implementation. Reference numbers that are shared across multiple figures are used to denote the same element or similar elements. In <FIG>, operations associated with the compression and/or decompression of a non-constant data block are illustrated. In contrast, <FIG> and <FIG> illustrate the compression and/or decompression operations of a constant data block.

Referring now to <FIG>, an accelerator <NUM> may include compression circuitry <NUM>, constant-detection circuitry <NUM>, fill circuitry <NUM>, decompression circuitry <NUM>, and controller circuitry <NUM>. According to an embodiment, some of the circuitries (e.g., compression circuitry or decompression circuitry) and the operations associated therewith may be implemented by separate accelerators. An input data block <NUM>, such as a memory page, is received by the accelerator <NUM> to be compressed. The input data block <NUM> may be identified by a job descriptor or job request to be processed by the accelerator <NUM>. The job descriptor may be issued by, for example, one of the processor cores <NUM>-N illustrated in <FIG>, or from the memory controller <NUM>. As noted above, the input data block <NUM> is a non-constant data block which means it is not comprised of a repeating constant. The input data block <NUM> received by the accelerator is processed by the compression circuitry <NUM> to generate a compressed data block <NUM>. In one embodiment, the input data block <NUM> is compressed according to a particular compression algorithm (e.g., LZO or Deflate) specified by the job descriptor. Alternatively, no compression algorithm is specified and the input data block <NUM> is compressed via the default compression algorithm implemented by the accelerator.

Next, the compressed block <NUM> is stored in a location in the memory hierarchy <NUM> such as the system memory <NUM> or one of the caches <NUM> or <NUM> of <FIG>. As part of completing the compression operations on the input data block <NUM>, according to an embodiment, a completion record <NUM> is generated. The completion record may include various information such as the memory address associated with data block <NUM> and/or the storage location of compressed block <NUM>. According to an embodiment, the completion record <NUM> may also include a constant block field or aggregate field to indicate whether the data block associated with the completion record is a constant data block. The field may be initialized or set to a default value indicating that the associated data block is not a constant data block. The completion record <NUM>, or information contained therein, may be stored in directory <NUM> of memory hierarchy <NUM>. In some embodiments, completion record <NUM> may be stored instead in a data structure outside of the memory hierarchy (not shown). <FIG> illustrates the details of a job descriptor <NUM> and a completion record <NUM> according to an embodiment. The constant block field or aggregate field may be implemented in one of the unused portions of the completion record <NUM> and/or an existing field.

Concurrently with the performance of the compression operations by the compression circuitry <NUM>, according to an embodiment, the input data block <NUM> is received and checked by the constant-detection circuitry <NUM> to determine whether it is a constant data block. The result of that check is provided to the controller circuitry <NUM>. In one embodiment, when the result indicates that the input data block <NUM> is not a constant data block, no further action is taken. Alternatively, the controller circuitry <NUM> may update record <NUM> to indicate that the compressed data block <NUM> is a not a constant data block. In some embodiments, the controller circuitry <NUM> updates the completion record generated by the compression circuitry <NUM> prior to it being stored to the directory <NUM>.

Thereafter, a request for data (i.e. data block <NUM>) is issued by the OS or an application. The requested may specify the requested data via a memory address, which is used to perform a lookup in directory <NUM> to find a matching record or entry. If the memory address in the request matches the memory address in the record associated with data block <NUM>, the constant block field is checked to see if the requested data is a constant data block. When the field indicates that data block <NUM> is not a constant data block, the compressed data block <NUM> is retrieved (i.e. read from memory) and sent to the accelerator <NUM>. Accordingly, the decompression circuitry <NUM> performs decompression operation on the compressed data block <NUM> to generate output data block <NUM> which is used to fill the request.

<FIG> illustrate the operations of compressing and decompressing a constant data block by an accelerator in accordance with an embodiment. As illustrated, input data block <NUM> is received by the accelerator <NUM> to be compressed. Input data block <NUM>, in this case, is a constant data block. That is, it is comprised of a repeating bit sequence (e.g., a constant byte, word, or doubleword, etc.). Similar to the description above with respect to <FIG>, the input data block <NUM> may be identified by a job descriptor or job request sent to the accelerator <NUM> by one of the processor cores <NUM>-N or by the memory controller <NUM>. The input data block <NUM> is received and compressed by the compression circuitry <NUM> in accordance with a compression algorithm (e.g., LZO or deflate) to generate a compressed data block <NUM>. The compressed data block <NUM> is then stored to the memory hierarchy <NUM> and a completion record <NUM> associated with the compressed block <NUM> is generated. The completion record <NUM>, or information contained therein, is stored to the directory <NUM> or another data structure. Information stored in the completion record may include the memory address associated with the input data block <NUM>, the location of the compressed data block <NUM>, and/or an indication of whether the input data block <NUM> is a constant data block. In some embodiments, the constant value associated with the constant data block is also stored in the completion record <NUM>.

Concurrently with the performance of the compression operations by the compression circuitry <NUM>, according to an embodiment, the input data block <NUM> is received and checked by the constant-detection circuitry <NUM> to determine whether it is a constant data block. The result of the check is provided to the controller circuitry <NUM>. In the case of data block <NUM>, the result indicates that it is a constant data block and, in response, the controller circuitry <NUM> updates completion record <NUM> accordingly. For example, the constant data field of record <NUM> may be updated to a value indicating that the data block <NUM> is a constant data block. Alternatively, or in addition to, an indication that the data block <NUM> is a constant data block is attached to, or otherwise associated with, the input data block <NUM> itself.

Irrespective of how the indication is attached or associated with the input data block <NUM>, the indication is usable by the OS or system hardware/software to decide how to handle the compressed block <NUM>. For example, the OS may cause the compressed data block <NUM> to be discarded or evicted from the memory hierarchy <NUM>, or otherwise overwritten by other data. In some cases, the OS may simply ignore the indication and handle the compressed data block <NUM> as normal, as if it was generated from a non-constant data block.

After the compression and constant-detect operations are performed on data block <NUM>, a request for data for data block <NUM> may subsequently be issued by the OS or an application. Responsive to the request, a lookup is performed in directory <NUM> to find record <NUM> associated with data block <NUM>. The constant block field of record <NUM> is checked to see if data block <NUM> is a constant data block. Since data block <NUM> is a constant data block, a request is sent to the accelerator <NUM> to generate the requested data block from a constant. For example, the constant that is stored in record <NUM> may be provided to the fill circuitry <NUM> of accelerator <NUM> which uses it to generate the output data block <NUM>. For example, if the constant value is a byte value, the fill circuitry may generate a data block (e.g. a 4KB memory page) by filling it with multiple (e.g., <NUM>) instances of the byte value. Alternatively, the OS/software may decide to ignore the indication that data block <NUM> is a constant data block. In such case, the compressed block <NUM> is provided to the decompression circuitry <NUM> of the accelerator <NUM> and decompressed with the appropriate decompression algorithm/method to generate output data block <NUM>, as indicated by the dashed arrows.

<FIG> is a block diagram illustrating the operations associated with compressing/decompressing a constant data block according to another embodiment. As with <FIG>, an input constant data block <NUM> is received by the accelerator <NUM> to be compressed in accordance with a compression algorithm. Concurrently with the compression operations, the input data block <NUM> is checked by the constant-detection circuitry <NUM> to see if it is a constant data block. The result of the check is provided to the controller circuitry <NUM>.

Next, because the result indicates that the input data block <NUM> is a constant data block, the controller circuitry <NUM> then queries the compression circuitry to determine whether the compression of input data block <NUM> has completed. Depending on the compression algorithm used, the compression operations may include multiple stages. For example, in the case of Deflate compression, there is at least a first stage, in which Huffman code/tree is generated, and a second stage, in which the data block is compressed based on the generated Huffman code/tree. If the input data block <NUM> is found to be a constant data block before all of the compression operations (stages) have finished, the controller circuitry may instruct the compression circuitry <NUM> to abort any remaining compression operations (stages). In one embodiment, the compression circuitry <NUM> may receive the result of the constant detection directly from the controller circuitry <NUM> or the constant detection circuitry <NUM>. Based on the result, the compression circuitry <NUM> may automatically abort any compression operations still outstanding. In some embodiments, the compression circuitry <NUM> may pause after completing a certain number of operations or after specific stages to wait for the result of the constant detection. For example, In the case of Deflate compression, the compression circuitry <NUM> may pause after completing the first stage to wait for the result from the constant detection before deciding whether to continue or abort the second stage.

According to some embodiments, in addition to instructing the compression circuitry <NUM> to abort compression, the controller circuitry <NUM> may update record <NUM> in directory <NUM> to associate the data block <NUM> with an indication of constant block. As noted above, a field in record <NUM> may be updated to indicate that data block <NUM> is a constant data block.

Thereafter, when data block <NUM> is requested, the OS and/or software perform a lookup in the directory <NUM> and determine from record <NUM> that the requested data block is a constant data block. According to an embodiment, the OS and/or software then request the accelerator <NUM> to generate the requested data block from the constant value associated with data block <NUM>. The constant value may be provided in the request to the accelerator <NUM> or may be looked up from another source (e.g., an input buffer or directory <NUM>). Accordingly, the fill circuitry <NUM> of accelerator <NUM> generates the output data block <NUM> using the constant value. For example, the fill circuitry <NUM> may fill a data block (e.g., a 4KB page) with multiple (e.g., <NUM>) instances of the constant value. It is worth noting that since the compression of data block <NUM> was aborted, there is no compressed data block stored in the memory hierarchy <NUM>. As such, unlike the operations illustrated in <FIG>, the output data block <NUM> in <FIG> can only be generated from the constant value.

According to an embodiment, a field such as an aggregate field in the completion record is used to indicate whether a data block is a constant data block. In one embodiment, the aggregate field is initially written as "<NUM>". When the constant detect functionality is enabled, the aggregate "sum" will be written as "<NUM>" if all of the bytes in the input data block are the same. Otherwise, the aggregate "sum" is written as "<NUM>" if any of the input bytes are different. The data being compared is the input to the Deflate compression or zero-compression zcomp if nested compression is enabled. In one embodiment, if the input block is of zero size, it is considered "all the same" and thus the aggregate "sum" will be written as "<NUM>". Note that while the completion record may show that all of the bytes in the input data block are the same byte, the actual value of the byte may not necessarily be stored in the completion record but is looked up from another source, such as an input buffer. In one embodiment, the constant detection functionality is always enabled.

In some embodiments, the compression operations and/or the constant detection operations performed on a data block are be divided into multiple dependent jobs, where each job operates on a respective portion of the data block. To enable the constate detection across multiple jobs, a data structure (state structure) may be used to pass the state of the constant detection between different jobs. For example, the state of the constant detection may need to be passed from the end of job N to the start of the next job N+<NUM>. In order to do so, a data structure accessible by the different jobs may be used to store the state of the constant detection. <FIG> illustrate the exemplary fields for preserving the partial state of the constant detection operations between multiple jobs in accordance with an embodiment. The data structure may include a reference value field <NUM>, a reference value valid field (valid field) <NUM>, and/or a differing value already seen field (seen field) <NUM>. The reference value field <NUM>, as the name suggests, stores the reference value (i.e. the constant) against which all other values in the data block are compared. The size of the field is dependent on the size of the reference value. If the constant detection is implemented to check for a constant byte, then the reference value field simply stores the first byte of the input data block or stream. As for the valid field <NUM>, it stores an indication of whether the value (e.g., a constant byte) stored in the reference value field <NUM> is valid. For example, at the start of the check, the valid field <NUM> is not set. Then, as the first value (byte) of the data block is stored into the reference value field <NUM>, the valid field <NUM> is set to indicate the constant detection operations may begin to use the reference value to compare against subsequent values. The seen field <NUM> stores an indication of whether a value other than the reference value has been detected in the data block or any portion thereof. A set value indicates that the input data block is not a constant data block.

Table <NUM> illustrate the possible interpretations of various combinations of the valid field <NUM> and seen field <NUM>. If the valid field and the seen field are both unset (e.g., "<NUM>"), it means the reference byte value should be ignored and that no value has been previously seen. This scenario may occur during initialization before any constant detection operations are performed. When the valid field <NUM> is set (e.g., "<NUM>") while the seen field is not set (e.g., "<NUM>"), it signals that the reference value is valid and that all the values checked so far are all equal to the reference value. In other words, the constant detection is in progress and all portions of the data block up to now contain instances of the reference value. In one embodiment, when a value other than the reference value is detected, the seen field <NUM> is changed to a set bit ("<NUM>") and the bit in the valid field <NUM> is cleared ("<NUM>"). In addition, the reference value field <NUM> may be cleared out. Thus, a set seen field <NUM> signifies that at least one value other than the reference value has been detected in the data block. Accordingly, when a subsequent job sees a set seen field <NUM>, the job may simply abort to save on resources. While the reference value is often referred to herein as a byte, it may also include other sizes based on the desired implementation. For example, the reference value field <NUM> may be extended to contain a reference word (<NUM> bits) or doubleword (<NUM> bits), etc. In such implementations, the constant detection performed on a 4KB data block may check for <NUM> instances of a reference word or for <NUM> instances of a reference doubleword. Thus, different embodiments of the constant detection function may be implemented to check for constants of different sizes. According to an embodiment, if the size of the data block is not an integral multiple of the size of the reference value, an error may be generated, and the constant detection operations aborted.

<FIG> is a flow diagram illustrating operations associated with compression and constant detection of a data block according to an embodiment. Method <NUM> may be implemented in any of the systems described herein. For example, method <NUM> may be implemented in an accelerator such as accelerator <NUM> from <FIG>. Method <NUM> begins at the Start block. At <NUM> an input data block is received. The input data block may be either a constant data block or a non-constant data block. At <NUM>, the input data block is compressed to generate a compressed data block and checked for repeating constants. The compression of the data block and the check for repeating constants is, according to an embodiment, performed concurrently and in parallel. For example, the input data block may be compressed via the compression circuitry while at the same time a copy of the input data block is checked by the constant detection circuitry for repeating constants. At <NUM>, a determination is made on whether the input data block is a constant data block. That is, whether the input data block is comprised solely of repeat instances of a constant value (i.e. a repeating bit string). If the input data block is not a constant data block, then, at <NUM>, the compressed data block is stored to the memory hierarchy such as the system memory or the cache. However, if the input data block is found to be a constant data block at <NUM>, then at <NUM>, the input data block and/or the compressed data block is associated with a constant block indication. As detailed above, in one embodiment, an indication may be stored in the completion record that was generated from the compression of the input data block. Next, at <NUM>, the compressed data block is stored to the memory hierarchy.

<FIG> is a flow diagram illustrating operations associated the compression and constant detection of a data block according to an embodiment. Method <NUM> may be implemented in any of the systems described herein. Specifically, method <NUM> may be implemented in any accelerator capable of performing compression operations, such as accelerator <NUM> from <FIG>. Method <NUM> begins at the "START" block. At <NUM> an input data block is received. The input data block may be either a constant data block or a non-constant data block. At <NUM>, one or more compression operations are performed on the input data block. At the same time, one or more constant detection operations are also performed on the input data block to checked for repeating constants. According to an embodiment, the compression operations are performed concurrently with, but separately from, the constant detection operations. For example, an accelerator may include separate compression logic/circuitry and constant detection logic/circuitry to perform these operations. At <NUM>, a determination is made on whether the input data block is a constant data block. As noted above, an input data block is a constant data block if it is comprised solely of repeat instances of a constant value (i.e. a repeating bit string). If the input data block is not a constant data block, then at <NUM>, a compressed data block generated from compression operations is stored to the memory hierarchy, such as the system memory or the cache. If, however, the input data block is determined to be a constant data block at <NUM>, then at <NUM>, a determination is made on whether the compression operations performed on the input data block has been completed. If compression operations are already completed, then the compressed data block is stored at <NUM>. On the other hand, if the compression operations have not yet been completed, then the compression operation is aborted. For example, some compression algorithms, such as Deflate, perform compression in multiple stages. If the input data block is determined to be a constant data block before all of the compression stages have completed, then any remaining stages yet to be performed are aborted at <NUM>.

Turning now to <FIG>, which illustrates a flow diagram of the operations associated with decompressing a data block according to an embodiment. Method <NUM> may be implemented in any of the systems described herein. Specifically, method <NUM> may be implemented in any accelerator capable of performing decompression and/or fill operations, such as accelerator <NUM> from <FIG>. Method <NUM> begins at the "START" block. At <NUM>, a request for a data block is detected. At <NUM>, a determination is made on whether the requested data block is a constant data block. In one embodiment, this is determined by looking up the status of the requested data block. For example, the memory address of the requested data block may be used to look up a directory (e.g., director <NUM>) to obtain a record (e.g., <NUM> or <NUM>) associated with the requested data block. The record, according to an embodiment, contains a field indicating whether the associated data block is a constant data block. At <NUM>, if the requested data block is not a constant data block, a compressed version of the requested data block is retrieved and decompressed to generate the requested data block. However, if the requested data block is indeed a constant data block, such that it is made up of multiple instances of a constant value, then at GGQ08, that constant value is used to generate the requested data block. In one embodiment, the constant value is provided by the record obtained from the directory during the lookup. A fill circuitry may fill a buffer with repeat instances of the constant value to generate the requested data block. Irrespective of how the requested data block is generated, it is outputted to fulfill the data request at <NUM>.

<FIG> illustrate examples of constant and non-constant data blocks according to an embodiment. Each of the rows shown in <FIG> represents a data block. As noted above, each data block may be a memory page. While a typical size of a memory page is 4KB, other size (e.g., 8KB, 16Kb, etc.) may also be used depending on the desired implementation. As defined herein, a constant data block is comprised of a repeating bit sequence of a specific size whereas a non-constant data block is not. To illustrate, data block <NUM> is an example of a constant data block because it is made up of repeat instances of the constant byte 0x00 (bit sequence "<NUM>"). Similarly, data blocks <NUM> and <NUM> contain repeating instances of the constant byte 0x11 (bit sequence "<NUM>") and 0x96 (bit sequence "<NUM>"), respectively. As such, they are also constant data blocks. In contrast, data block <NUM> comprises 0xAA (bit sequence "<NUM>") in the first byte, 0x55 (Bit sequence <NUM>) in the second byte, 0xAA ("<NUM>") again in the third byte, 0x55 ("<NUM>") again in the fourth byte, and so on. Since data block <NUM> contains more than one byte value (0xAA and Ox55), it is not a constant data block even though some of the byte values are repeating. It is worth noting that data block <NUM> may be considered a constant word block, since the first word value 0xAA55 is repeated throughout the data block <NUM>.

<FIG> is a flow diagram illustrating an embodiment of the constant-detection operation. Method <NUM> may be performed by constant detection circuitry <NUM> of <FIG>. At <NUM>, an input stream on which constant-detection is to be performed is detected. As described above, the constant detection on a data block may be divided into multiple jobs. Thus, the input stream referred to here may be the entire data block or only a portion of it (e.g., 1KB portion of a 4KB block). To implement constant detection across multiple jobs, fields in a state structure are used to preserve the various states/progress of the detection. The details of these fields are described above with respect to <FIG>. At <NUM>, a determination is made on whether the seen field in the state structure has been set. If so, then at <NUM>, the constant detection is aborted because more than one constant value has already been found in the data block. If the seen field is not set, the valid field is checked next at <NUM>. If the valid field has not been set, then at <NUM>, the valid field is set and a reference value is stored into the reference value field of the state structure. If the constant detection is implemented to check for constant bytes, then the first byte of the input stream is stored into the reference value field. If the constant detection is configured to check for constant words, then the first word of the input stream is stored, and so on. At <NUM>, a check is performed to see if the current value (e.g., the first byte of the input stream) is the only value left to be checked. If so, then the constant detection is complete. On the other hand, if more values remain to be checked, the next value (e.g., the next byte) is set as the current value at <NUM> and compared with the reference value at <NUM>. Returning to <NUM>, if the valid field is already set, then the operation proceeds straight to <NUM> without having to set the reference value field. If the current value is the same as the reference value, then at <NUM> the current value is checked again to see if it is the last value in the input stream to be checked, and if so, the constant detection is complete. However, if, at <NUM>, the current value is found to be different from the reference value, this indicates that the input stream contains more than one constant value and thus fails the constant data block. As such, at <NUM>, the seen field is set so as to notify any subsequent constant check operations that more than one constant value has already been detected. Optionally, at <NUM>, the valid field and/or the reference value field in the state structure are cleared.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

<FIG> shows processor core <NUM> including a front end hardware <NUM> coupled to an execution engine hardware <NUM>, and both are coupled to a memory hardware <NUM>.

The front end hardware <NUM> includes a branch prediction hardware <NUM> coupled to an instruction cache hardware <NUM>, which is coupled to an instruction translation lookaside buffer (TLB) <NUM>, which is coupled to an instruction fetch hardware <NUM>, which is coupled to a decode hardware <NUM>. The decode hardware <NUM> (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode hardware <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core <NUM> includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode hardware <NUM> or otherwise within the front end hardware <NUM>). The decode hardware <NUM> is coupled to a rename/allocator hardware <NUM> in the execution engine hardware <NUM>.

The execution engine hardware <NUM> includes the rename/allocator hardware <NUM> coupled to a retirement hardware <NUM> and a set of one or more scheduler hardware <NUM>. The scheduler hardware <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler hardware <NUM> is coupled to the physical register file(s) hardware <NUM>. Each of the physical register file(s) hardware <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) hardware <NUM> comprises a vector registers hardware, a write mask registers hardware, and a scalar registers hardware. This register hardware may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) hardware <NUM> is overlapped by the retirement hardware <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement hardware <NUM> and the physical register file(s) hardware <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution hardware <NUM> and a set of one or more memory access hardware <NUM>. The execution hardware <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution hardware dedicated to specific functions or sets of functions, other embodiments may include only one execution hardware or multiple execution hardware that all perform all functions. The scheduler hardware <NUM>, physical register file(s) hardware <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler hardware, physical register file(s) hardware, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access hardware <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access hardware <NUM> is coupled to the memory hardware <NUM>, which includes a data TLB hardware <NUM> coupled to a data cache hardware <NUM> coupled to a level <NUM> (L2) cache hardware <NUM>. In one exemplary embodiment, the memory access hardware <NUM> may include a load hardware, a store address hardware, and a store data hardware, each of which is coupled to the data TLB hardware <NUM> in the memory hardware <NUM>. The instruction cache hardware <NUM> is further coupled to a level <NUM> (L2) cache hardware <NUM> in the memory hardware <NUM>. The L2 cache hardware <NUM> is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline <NUM> as follows: <NUM>) the instruction fetch <NUM> performs the fetch and length decoding stages <NUM> and <NUM>; <NUM>) the decode hardware <NUM> performs the decode stage <NUM>; <NUM>) the rename/allocator hardware <NUM> performs the allocation stage <NUM> and renaming stage <NUM>; <NUM>) the scheduler hardware <NUM> performs the schedule stage <NUM>; <NUM>) the physical register file(s) hardware <NUM> and the memory hardware <NUM> perform the register read/memory read stage <NUM>; the execution cluster <NUM> perform the execute stage <NUM>; <NUM>) the memory hardware <NUM> and the physical register file(s) hardware <NUM> perform the write back/memory write stage <NUM>; <NUM>) various hardware may be involved in the exception handling stage <NUM>; and <NUM>) the retirement hardware <NUM> and the physical register file(s) hardware <NUM> perform the commit stage <NUM>.

In one embodiment, the core <NUM> includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2, and/or some form of the generic vector friendly instruction format (U=<NUM> and/or U=<NUM>), described below), thereby allowing the operations used by many multimedia applications to be performed using packed data.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache hardware <NUM>/<NUM> and a shared L2 cache hardware <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 1202A, a system agent <NUM>, a set of one or more bus controller hardware <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 1202A-N, a set of one or more integrated memory controller hardware <NUM> in the system agent hardware <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 1202A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 1202A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 1202A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache hardware <NUM>, and external memory (not shown) coupled to the set of integrated memory controller hardware <NUM>. The set of shared cache hardware <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect hardware <NUM> interconnects the integrated graphics logic <NUM>, the set of shared cache hardware <NUM>, and the system agent hardware <NUM>/integrated memory controller hardware <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such hardware. In one embodiment, coherency is maintained between one or more cache hardware <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 1202A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 1202A-N. The system agent hardware <NUM> may include for example a power control unit (PCU) and a display hardware. The PCU may be or include logic and components needed for regulating the power state of the cores 1202A-N and the integrated graphics logic <NUM>. The display hardware is for driving one or more externally connected displays.

The cores 1202A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1202A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set. In one embodiment, the cores 1202A-N are heterogeneous and include both the "small" cores and "big" cores described below.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> is couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface, or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) hardware <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller hardware point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) hardware), field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage hardware <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> in order to avoid obscuring other aspects of <FIG>.

Thus, the CL <NUM>, <NUM> include integrated memory controller hardware and include I/O control logic.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect hardware <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 1202A-N and shared cache hardware <NUM>; a system agent hardware <NUM>; a bus controller hardware <NUM>; an integrated memory controller hardware <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) hardware <NUM>; a direct memory access (DMA) hardware <NUM>; and a display hardware <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using an x86 compiler <NUM> to generate x86 binary code <NUM> that may be natively executed by a processor with at least one x86 instruction set core <NUM>. The processor with at least one x86 instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler <NUM> represents a compiler that is operable to generate x86 binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one x86 instruction set core <NUM> (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter <NUM> is used to convert the x86 binary code <NUM> into code that may be natively executed by the processor without an x86 instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code <NUM>.

Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.

In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

An embodiment is an implementation or example of the inventions. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments.

Claim 1:
A method (<NUM>, <NUM>, <NUM>) comprising:
performing compression operations on a memory block (<NUM>, <NUM>);
determining that the memory block is a constant data block comprised of only repeat instances of a constant value (<NUM>, <NUM>, <NUM>), wherein the determination (<NUM>, <NUM>, <NUM>) is performed concurrently with the compression operations on the memory block (<NUM>, <NUM>); and
associating a first indication with the memory block (<NUM>) based on the determination (<NUM>, <NUM>, <NUM>),
characterised in that
the first indication is used for controlling whether to abort the compression operations (<NUM>) or whether to discard a compressed memory block generated from the compression operations,
wherein the method (<NUM>) further comprises responsive to a request for the memory block (<NUM>), generating a copy of the memory block using the constant value when the memory block is associated with the first indication (<NUM>), and
wherein the compression operations are performed based on a DEFLATE or a Lempel-Ziv-Oberhumer, LZO, compression scheme.