Patent Description:
Page tables are data structures used by modem processor-based devices to provide virtual memory functionality. A page table provides page table entries that store mappings between virtual memory addresses and corresponding physical memory addresses (i.e., addresses of memory locations in a system memory). When a processor-based device needs to translate a virtual memory address into a physical memory address, the processor-based device accesses the page table to locate the page table entry associated with the virtual memory address, and then reads the corresponding physical memory address from the page table entry. Recently accessed mappings may also be cached by the processor-based device in a translation lookaside buffer (TLB) for subsequent reuse without the need to repeat the translation process. By using page tables to implement virtual memory functionality, the processor-based device enables software processes to access secure memory spaces that are isolated from one another, and that together may be conceptually larger than the available physical memory.

A multilevel page table is a page table variant that makes use of multiple page tables organized into a hierarchical data structure. To translate a virtual memory address using a multilevel page table, a hardware element provided by the processor-based device and known as a "page table walker" performs a "page table walk. " In the first step of the page table walk, the page table walker uses a base address pointing to the highest-level page table in the multilevel page table, and applies the topmost set of bits of the virtual memory address as an index to access a page table entry in the highest-level page table. That page table entry provides a pointer to a next-lower page table, which the page table walker uses in combination with a next-lower set of bits of the virtual memory address to access a page table entry in the next-lower page table. The page table entry in the next-lower page table contains a pointer to another next-lower page table, and so on. The page table at the lowest level of the multilevel page table provides a pointer to a physical memory page, which is used in combination with the bottommost set of bits of the virtual memory address to determine the physical memory address corresponding to the virtual memory address.

In some scenarios, it may be desirable to enable a software process to modify the contents of the page tables themselves (e.g., to update a physical memory address stored in a page table entry of a page table, or to modify access permissions on a corresponding memory page, as non-limiting examples). To do so, the software process seeking to modify the page table entry must first acquire the physical memory address of that page table entry within the system memory. One approach to obtaining the physical memory address of a page table entry involves recursive mapping of each page table of a multilevel page table, such that the last page table entry (i.e., the page table entry with the highest index associated with the virtual memory address) of each page table stores a pointer to that page table. Before the software process executes a memory access operation on the page table entry, the software process first performs a right bit shift on the virtual memory address, and populates the upper bits of the virtual memory address with ones (<NUM>). The page table walker then performs a conventional page table walk using the shifted virtual memory address. Because the topmost set of bits of the virtual memory address that are used as an index into the highest-level page table are all ones (<NUM>), the page table entry that is accessed first by the page table walker is the last page table entry in the highest-level page table, which merely points back to the highest-level page table. As a result, the page table walker, which is conventionally configured to traverse a specified number of levels of the multilevel page table when performing a page table walk, will end its page table walk one level "early," and will return the physical memory address of the page table entry in the lowest-level page table instead of a physical memory address in the system memory.

While recursive mapping does provide a solution that allows a memory access instruction to access the page table entry itself, this approach does have disadvantages. In particular, recursive mapping requires a dedicated page table entry in each page table of the multilevel page table, which reduces the number of page table entries available for address translation. Additionally, while the recursive page table accesses performed by the page table walker may be cached in a TLB, the cached recursive mappings are usable only for subsequent recursive mappings, which can result in decreased efficiency.

Accordingly, a more efficient mechanism for obtaining physical memory addresses for page table entries in a multilevel page table is desirable. <CIT> describes a memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker.

Exemplary embodiments disclosed herein include optimizing access to page table entries in processor-based devices. In this regard, in one exemplary embodiment, an instruction decode stage of an execution pipeline of a processor-based device receives a memory access instruction (e.g., a memory load instruction, a memory store instruction, or a memory read/modify/write instruction, as non-limiting examples) that includes a virtual memory address. A page table walker circuit of the processor-based device determines, based on the memory access instruction, a number T of page table walk levels to traverse, where T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. In some embodiments, the memory access instruction may provide a traverse indicator that explicitly specifies the number T of page table walk levels to traverse, while some embodiments may provide that the number T of page table walk levels to traverse may be determined based on a count of recursive traversals indicated by the virtual memory address. The page table walker next performs a page table walk of T page table walk levels of the multilevel page table, and identifies a physical memory address corresponding to a page table entry of the Tth page table walk level. The processor-based device then performs a memory access operation indicated by the memory access instruction using the physical memory address.

In another exemplary embodiment, a processor-based device is provided. The processor-based device includes a system memory that comprises a multilevel page table made up of a plurality of page tables, each page table comprising a plurality of page table entries. The processor-based device further includes a processing element (PE) that comprises an execution pipeline comprising an instruction decode stage, and a page table walker circuit. The PE is configured to receive, using the instruction decode stage, a memory access instruction comprising a virtual memory address. The PE is further configured to determine, using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. The PE is also configured to perform, using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table. The PE is additionally configured to identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level. The PE is further configured to perform a memory access operation indicated by the memory access instruction using the physical memory address.

In another exemplary embodiment, a method for optimizing access to page table entries is provided. The method comprises receiving, by an instruction decode stage of an execution pipeline of a processing element (PE) of a processor-based device, a memory access instruction comprising a virtual memory address. The method further comprises determining, by a page table walker circuit of the PE based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. The method also comprises performing, by the page table walker circuit of the PE based on the virtual memory address, a page table walk of T page table walk levels of a multilevel page table. The method additionally comprises identifying, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level. The method further comprises performing a memory access operation indicated by the memory access instruction using the physical memory address.

In another exemplary embodiment, a non-transitory computer-readable medium is provided, the computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to receive a memory access instruction comprising a virtual memory address. The computer-executable instructions further cause the processor to determine, based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. The computer-executable instructions also cause the processor to perform, based on the virtual memory address, a page table walk of T page table walk levels of a multilevel page table. The computer-executable instructions additionally cause the processor to identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level. The computer-executable instructions further cause the processor to perform a memory access operation indicated by the memory access instruction using the physical memory address.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional embodiments thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several embodiments of the disclosure, and together with the description serve to explain the principles of the disclosure.

Exemplary embodiments disclosed herein include optimizing access to page table entries in processor-based devices. In one exemplary embodiment, an instruction decode stage of an execution pipeline of a processor-based device receives a memory access instruction (e.g., a memory load instruction, a memory store instruction, or a memory read/modify/write instruction, as non-limiting examples) that includes a virtual memory address. A page table walker circuit of the processor-based device determines, based on the memory access instruction, a number T of page table walk levels to traverse, where T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. In some embodiments, the memory access instruction may provide a traverse indicator that explicitly specifies the number T of page table walk levels to traverse, while some embodiments may provide that the number T of page table walk levels to traverse may be determined based on a count of recursive traversals indicated by the virtual memory address. The page table walker next performs a page table walk of T page table walk levels of the multilevel page table, and identifies a physical memory address corresponding to a page table entry of the Tth page table walk level. The processor-based device then performs a memory access operation indicated by the memory access instruction using the physical memory address.

In this regard, <FIG> illustrates an exemplary processor-based device <NUM> that provides a processing element (PE) <NUM> for processing executable instructions. The PE <NUM> may comprise a central processing unit (CPU) having one or more processor cores, or may comprise an individual processor core comprising a logical execution unit and associated caches and functional units. The PE <NUM> of <FIG> includes an execution pipeline <NUM> that is configured to execute an instruction stream comprising computer-executable instructions. In the example of <FIG>, the execution pipeline <NUM> includes an instruction fetch stage <NUM> for retrieving instructions for execution, an instruction decode stage <NUM> for translating fetched instructions into control signals for instruction execution, and an instruction execute stage <NUM> for actually performing instruction execution. It is to be understood that some embodiments of the processor-based device <NUM> may comprise multiple PEs <NUM> rather than the single PE <NUM> shown in the example of <FIG>, and further that some embodiments of the PE <NUM> may include fewer or more stages within the execution pipeline <NUM> than those illustrated in the example of <FIG>.

The PE <NUM> of <FIG> is communicatively coupled to a system memory <NUM>, which stores a multilevel page table <NUM> comprising a plurality of page tables <NUM>(<NUM>)-<NUM>(P) for use in virtual-to-physical address translation. The PE <NUM> of <FIG> also includes a page table walker circuit <NUM> that embodies logic for performing page table walks on the multilevel page table <NUM> to translate virtual memory addresses into physical memory addresses. Some embodiments of the PE <NUM> further include a translation lookaside buffer (TLB) <NUM> for caching recent translations of virtual memory addresses to physical memory addresses for subsequent reuse. The structure and functionality of the multilevel page table <NUM> and the page table walker circuit <NUM> for performing virtual-to-physical address translation is discussed in greater detail below with respect to <FIG>.

The processor-based device <NUM> of <FIG> and the constituent elements thereof may encompass any one of known digital logic elements, semiconductor circuits, processing cores, and/or memory structures, among other elements, or combinations thereof. Embodiments described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor sockets or packages. It is to be understood that some embodiments of the processor-based device <NUM> may include elements in addition to those illustrated in <FIG>. For example, the PE <NUM> may further include one or more instruction caches, unified caches, memory controllers, interconnect buses, and/or additional memory devices, caches, and/or controller circuits.

As discussed above, circumstances may arise in which it is desirable to allow a software process being executed by the PE <NUM> to modify the contents of the page tables <NUM>(<NUM>)-<NUM>(P) of the multilevel page table <NUM>. As non-limiting examples, the software process may need to update a physical memory address stored in a page table entry of one of the page tables <NUM>(<NUM>)-<NUM>(P), or may need to modify access permissions on a corresponding memory page. To modify a page table entry, a physical memory address of the page table entry itself within the system memory <NUM> must first be determined. Existing solutions for enabling software processes to access page table entries may involve recursively mapping each of the page tables <NUM>(<NUM>)-<NUM>(P) of the multilevel page table <NUM>, such that the last page table entry (i.e., the page table entry with the highest index associated with the virtual memory address) of each of the page tables <NUM>(<NUM>)-<NUM>(P) stores a pointer to that page table <NUM>(<NUM>)-<NUM>(P). However, recursive mapping requires a dedicated page table entry in each of the page tables <NUM>(<NUM>)-<NUM>(P) of the multilevel page table <NUM>, which reduces the number of page table entries available for address translation. Additionally, while recursive page table accesses performed by the page table walker circuit <NUM> may be cached in the TLB <NUM>, the cached recursive mappings are usable only for subsequent recursive mappings, which can result in decreased efficiency.

In this regard, the PE <NUM> is configured to provide optimized access to page table entries in processor-based devices. In an exemplary embodiment, the instruction decode stage <NUM> of the execution pipeline <NUM> receives a memory access instruction <NUM>. The memory access instruction <NUM> includes a virtual memory address <NUM>, and, in some embodiments, may be a memory load instruction, a memory store instruction, or a memory read/modify/write instruction, as non-limiting examples. The page table walker circuit <NUM> determines, based on the memory access instruction <NUM>, a number T of page table walk levels to traverse, where T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address <NUM>. In some embodiments, the memory access instruction <NUM> may provide a traverse indicator <NUM> that explicitly specifies the number T of page table walk levels to traverse. The traverse indicator <NUM> may comprise an immediate value operand, or may comprise a register operand indicating a register that stores the number T of page table walk levels to traverse. According to some embodiments, the number T of page table walk levels to traverse may be determined automatically based on a count of recursive traversals indicated by the virtual memory address <NUM>.

The page table walker circuit <NUM> then performs a page table walk of T page table walk levels of the multilevel page table <NUM>, and identifies a physical memory address corresponding to a page table entry of the Tth page table walk level. The PE <NUM> performs a memory access operation indicated by the memory access instruction <NUM> using the physical memory address returned by the page table walker circuit <NUM> (e.g., by executing the memory access instruction <NUM> using the instruction execute stage <NUM>). In embodiments in which the memory access instruction <NUM> is a memory load instruction or a memory read/modify/write instruction, performing the memory access operation may include returning a content of a memory location indicated by the physical memory address. Embodiments in which the memory access instruction <NUM> is a memory store instruction or a memory read/modify/write instruction may provide that performing the memory access operation includes writing store data to a memory location indicated by the physical memory address.

Some embodiments of the PE <NUM> in which the number T of page table walk levels to traverse may be determined automatically may further provide an optimization selection indicator <NUM> to enable selective activation of the optimized page table access feature described herein. In such embodiments, after receiving the memory access instruction <NUM> by the instruction decode stage <NUM> of the execution pipeline <NUM>, the PE <NUM> determines whether the optimization selection indicator <NUM> is in a set state. If so, the operations described above for determining the number T of page table walk levels to traverse and performing the page table walk of T page table walk levels of the multilevel page table <NUM> are carried out. If the optimization selection indicator <NUM> is not in a set state, the page table walker circuit <NUM> performs a page table walk in conventional fashion.

To provide a more detailed description of the structure and functionality of the multilevel page table <NUM> both in conventional use and in providing optimized access to page table entries, <FIG> is provided. As seen in <FIG>, the virtual memory address <NUM> of <FIG> is being used to traverse the page tables <NUM>(<NUM>)-<NUM>(<NUM>) (i.e., the page tables <NUM>(<NUM>)-<NUM>(P) where P=<NUM>, in this example) of the multilevel page table <NUM> of <FIG>. In the example of <FIG>, the virtual memory address <NUM> comprises <NUM> bits that are relevant for virtual memory address translation. The virtual memory address <NUM> is divided into four (<NUM>) bit sets <NUM>, <NUM>, <NUM>, and <NUM> of nine (<NUM>) bits each, and one (<NUM>) bit set <NUM> comprising the lowest <NUM> bits of the virtual memory address <NUM>. Each of the bits sets <NUM>, <NUM>, <NUM>, and <NUM> are used as indices into the corresponding page tables <NUM>(<NUM>)-<NUM>(<NUM>), while the bit set <NUM> is used as an offset into a memory page <NUM> containing the memory location <NUM> that ultimately corresponds to the virtual memory address <NUM>.

In conventional operation, the page table walker circuit <NUM> performs a page table walk that traverses four (<NUM>) page table walk levels to translate the virtual memory address <NUM> into a corresponding physical memory address. First, the page table walker circuit <NUM> retrieves a base address <NUM> indicating the physical memory address of the page table <NUM>(<NUM>). The base address <NUM> is then added to the value of the bit set <NUM> of the virtual memory address <NUM> to generate a physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>). This is considered the first page table walk level traversed by the page table walker circuit <NUM>.

Once the physical memory address of the page table entry <NUM> is determined, the page table walker circuit <NUM> accesses the physical memory address <NUM> stored in the page table entry <NUM>, which points to the next page table <NUM>(<NUM>) in the multilevel page table <NUM>. The physical memory address <NUM> is then added to the value of the bit set <NUM> of the virtual memory address <NUM> to generate a physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>). These operations constitute the second page table walk level traversed by the page table walker circuit <NUM>. The page table walk continues in similar fashion, with the third page table walk level using the physical memory address <NUM> stored in the page table entry <NUM> and the bit set <NUM> to generate the physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>), and the fourth page table walk level using the physical memory address <NUM> stored in the page table entry <NUM> and the bit set <NUM> to generate the physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>). Finally, the page table walker circuit <NUM> uses the physical memory address <NUM> stored in the page table entry <NUM>, in combination with the bit set <NUM> of the virtual memory address <NUM>, to generate a physical memory address that represents the translation of the virtual memory address <NUM>, and that points to the memory location <NUM> in the memory page <NUM>.

In the conventional example described above, the page table walker circuit <NUM> performs a page table walk of four (<NUM>) page table walk levels to translate the virtual memory address <NUM> into the physical memory address of the memory location <NUM>. However, embodiments of the PE <NUM> of <FIG> for optimizing access to page table entries allows for a fewer number of page table walk levels to be performed, which enables software processes to obtain physical memory addresses of the page table entries of the page tables <NUM>(<NUM>)-<NUM>(P) of the multilevel page table <NUM> used to perform translation of the virtual memory address <NUM>. For example, to obtain the physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>), only two (<NUM>) page table walk levels need to be traversed: one to use the base address <NUM> and the bit set <NUM> to determine the physical memory address of the page table entry <NUM> of the page table <NUM>(<NUM>), and one to use the physical memory address <NUM> stored in the page table entry <NUM> along with the bit set <NUM> to determine the physical memory address of the page table entry <NUM>. Accordingly, executing the memory access instruction <NUM> of <FIG> while specifying two (<NUM>) page table walk levels (e.g., explicitly using the traverse indicator <NUM>, or implicitly by the virtual memory address <NUM> indicating recursive traversals) results in the physical memory address of the page table entry <NUM> being used for the memory access operation.

As noted above, the memory access instruction <NUM> of <FIG> may be a memory load instruction, a memory store instruction, or a memory read/modify/write instruction, as non-limiting examples. In this regard, <FIG> illustrate an exemplary memory load instruction, an exemplary memory store instruction, and an exemplary read/modify/write instruction, respectively, corresponding to the memory access instruction <NUM> of <FIG>. In <FIG>, a memory load instruction <NUM>, corresponding to the memory access instruction <NUM> of <FIG> in some embodiments, includes a virtual memory address <NUM> corresponding to the virtual memory address <NUM> of <FIG>. In some embodiments, the memory load instruction <NUM> may also include a traverse indicator <NUM> corresponding in functionality to the traverse indicator <NUM> of <FIG>.

Similarly, in <FIG>, a memory store instruction <NUM>, which according to some embodiments may correspond to the memory access instruction <NUM> of <FIG>, provides a virtual memory address <NUM> and a traverse indicator <NUM> corresponding to the virtual memory address <NUM> and the traverse indicator <NUM>, respectively, of <FIG>. The memory store instruction <NUM> further includes store data <NUM>, representing data to be written to the memory location indicated by the physical memory address resulting from the page table walk of the T page table walk levels of the multilevel page table <NUM> described above with respect to <FIG> and <FIG>. In some embodiments, the store data <NUM> may comprise an immediate value to be written to the memory location, or may comprise a register operand indicating a register that stores data to be written to the memory location.

<FIG> illustrates a memory read/modify/write instruction <NUM>, which may correspond to the memory access instruction <NUM> of <FIG> in some embodiments. Like the memory store instruction <NUM>, the memory read/modify/write instruction <NUM> provides a virtual memory address <NUM> and a traverse indicator <NUM> corresponding to the virtual memory address <NUM> and the traverse indicator <NUM>, respectively, of <FIG>. The memory read/modify/write instruction <NUM> also includes store data <NUM>, which represents data to be written to the memory location indicated by the physical memory address resulting from the page table walk of the T page table walk levels of the multilevel page table <NUM> described above with respect to <FIG> and <FIG>. The store data <NUM> according to some embodiments may comprise an immediate value to be written to the memory location, or may comprise a register operand indicating a register that stores data to be written to the memory location.

It is to be understood that the memory load instruction <NUM>, the memory store instruction <NUM>, and the memory read/modify/write instruction <NUM> in some embodiments may each be implemented within the PE <NUM> as dedicated instructions with unique opcodes provided by an instruction set architecture (ISA) of the PE <NUM>. Alternatively or additionally, the memory load instruction <NUM>, the memory store instruction <NUM>, and/or the memory read/modify/write instruction <NUM> may be conventional memory access instructions to which additional operands and/or opcode bits are added to accomplish the functionality described herein.

<FIG> and <FIG> illustrate exemplary operations <NUM> for optimizing access to page table entries by the processor-based device <NUM> of <FIG>. For the sake of clarity, elements of <FIG> and <FIG> are referenced in describing <FIG> and <FIG>. The operations <NUM> in <FIG>, according to some embodiments, begin with the instruction decode stage <NUM> of the execution pipeline <NUM> of the PE <NUM> of the processor-based device <NUM> receiving the memory access instruction <NUM> comprising the virtual memory address <NUM> (block <NUM>). In embodiments in which the PE <NUM> provides the optimization selection indicator <NUM>, the page table walker circuit <NUM> may determine whether the optimization selection indicator <NUM> of the PE <NUM> is in a set state (block <NUM>). If not, the page table walker circuit <NUM> performs a conventional page table walk (block <NUM>).

However, if the PE <NUM> determines at decision block <NUM> that the optimization selection indicator <NUM> is in a set state, or if the PE <NUM> does not provide the optimization selection indicator <NUM>, the page table walker circuit <NUM> of the PE <NUM> determines, based on the memory access instruction <NUM>, the number T of page table walk levels to traverse, wherein T is greater than zero (<NUM>) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address <NUM> (block <NUM>). In some embodiments, the operations of block <NUM> for determining the number T of page table walk levels to traverse may be based on the traverse indicator <NUM> (block <NUM>). Some embodiments may provide that the operations of block <NUM> for determining the number T of page table walk levels to traverse may be based on a count of one or more recursive traversals indicated by the virtual memory address <NUM> (block <NUM>). Processing then resumes at block <NUM> of <FIG>.

Referring now to <FIG>, the page table walker circuit <NUM> of the PE <NUM> next performs, based on the virtual memory address <NUM>, a page table walk of T page table walk levels of the multilevel page table <NUM> (block <NUM>). According to some embodiments, the TLB <NUM> may cache the page table walk of the T page table walk levels of the multilevel page table <NUM> (block <NUM>). In such embodiments, the operations of block <NUM> for performing the page table walk of the T page table walk levels of the multilevel page table <NUM> may involve accessing a previously cached page table walk in the TLB <NUM> in response to a hit on the TLB <NUM>. The page table walker circuit <NUM> then identifies, based on the page table walk, a physical memory address corresponding to a page table entry (such as the page table entry <NUM> of <FIG>) of the Tth page table walk level (block <NUM>). The PE <NUM> performs a memory access operation indicated by the memory access instruction <NUM> using the physical memory address (block <NUM>). In some embodiments in which the memory access instruction <NUM> is the memory load instruction <NUM> of <FIG> or the memory read/modify/write instruction <NUM> of <FIG>, the operations of block <NUM> for performing the memory access operation may include returning a content of a memory location indicated by the physical memory address (block <NUM>). Some embodiments in which the memory access instruction <NUM> is the memory store instruction <NUM> of <FIG> or the memory read/modify/write instruction <NUM> of <FIG> may provide that the operations of block <NUM> for performing the memory access operation may include writing the store data <NUM> to a memory location indicated by the physical memory address (block <NUM>).

<FIG> is a block diagram of an exemplary processor-based device <NUM>, such as the processor-based device <NUM> of <FIG>, that provides optimized access to page table entries. The processor-based device <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based device <NUM> includes a processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like, and may correspond to the PE <NUM> of <FIG>. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions and an instruction processing circuit <NUM>. Fetched or prefetched instructions from a memory, such as from a system memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution.

The processor <NUM> and the system memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based device <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the system memory <NUM> as an example of a peripheral device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the system memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The system memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the system memory <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based device <NUM> in <FIG> may include a set of instructions <NUM> that may be encoded with the reach-based explicit consumer naming model to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the system memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the system memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes the computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions <NUM>. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software process.

The embodiments disclosed herein may be provided as a computer program product, or software process, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.), and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Claim 1:
A processor-based device (<NUM>), comprising:
a system memory (<NUM>) comprising a multilevel page table (<NUM>) comprising a plurality of page tables (<NUM>(<NUM>)-<NUM>(P)), each page table comprising a plurality of page table entries (<NUM>, <NUM>, <NUM>, <NUM>); and
a processing element, PE, (<NUM>) comprising:
an execution pipeline (<NUM>) comprising an instruction decode stage (<NUM>); and
a page table walker circuit (<NUM>);
the PE configured to:
receive (<NUM>), using the instruction decode stage, a memory access instruction (<NUM>) comprising a virtual memory address (<NUM>) and a traverse indicator that indicates the number T of page table walk levels to traverse;
determine (<NUM>), using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse based on the traverse indicator, wherein T is greater than zero and less than or equal to a number of page table walk levels required to fully translate the virtual memory address;
perform (<NUM>), using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table;
identify (<NUM>), based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and
perform (<NUM>) a memory access operation indicated by the memory access instruction using the physical memory address.