Patent Description:
Many currently used infrared sensor chip assemblies include silicon readout integrated circuits (ROIC) that are hybridized to mercury cadmium tellurium (HgCdTe) detector arrays using indium (In) bumps. Problems with such assemblies exist, however, in that these indium bumps tend to fail as a result of their inability to survive the large number of thermal cycles required for the assembly processes due to the coefficient of thermal expansion (CTE) mismatch between silicon (Si) and the HgCdTe.

While previous attempts to address these problems have been attempted, none are completely useful or satisfactory. For example, for indium bump (IB) focal plane arrays (FPAs), the approach has been to attempt to CTE match the ROIC to a detector by adhesively bonding titanium (Ti) and silicon (Si) shims to the back of a sensor chip assembly (SCA) after dicing and hybridization. While this approach can be effective, it is an expensive die-level process and is performed manually by skilled labor.

As another example, for heterogeneous three-dimensional (3D) integration, approaches include epitaxial growth of Ill-V semiconductor materials, such as gallium nitride (GaN), on a silicon (Si) substrate using buffer layers to provide the lattice match, or ultrasonically bonding a bonded completed III-V die to a silicon (Si) circuit. In both of these cases, III-V layers can tend to cause degraded performance due to stress associated with CTE mismatches between the III-V devices and silicon (Si) substrates.

<CIT> discloses an integrated circuit assembly that includes a silicon thin film circuit bonded to a substrate of a material selected to provide the assembly with an effective thermal expansion characteristic that approximately matches that of another device, such as HgCdTe detector. A first method for manufacturing the assembly includes the steps of forming a desired circuit in a thin layer of silicon on a silicon substrate of a bonded silicon wafer. The thin silicon layer including the circuit is then bonded to the selected substrate material. Thereafter the silicon substrate is removed and the resulting assembly may be mated to the device. A second method employs a two stage transfer technique wherein the processed thin silicon layer is bonded to a first, temporary substrate; the silicon substrate is removed; a second, permanent substrate is attached; and the first substrate is removed. The second substrate is comprised of a material selected for providing the assembly with a coefficient of thermal expansion that is matched to the material of the device.

According to one embodiment, a method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material as defined in claims <NUM> to <NUM>.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

As will be discussed below, a coefficient of thermal expansion (CTE) matched readout integrated circuit (ROIC) is produced at a wafer level before hybridization to thereby increase yield and decrease costs. The method of production can also be used to produce oxide bonded three-dimensional (3D) ICs using mixed semiconductor materials as in true heterogeneous devices.

With reference to <FIG>, a wafer manufacturing foundry <NUM> is provided remotely from a processing plant <NUM>. The wafer manufacturing foundry <NUM> is configured and equipped to manufacture standard complementary-metal-oxide-semiconductor (CMOS) wafers <NUM>, for example, which can be shipped to the processing plant <NUM> for further processing as will be described below. While the wafer manufacturing foundry <NUM> is illustrated and described herein as being remote and separate from the processing plant <NUM>, it is to be understood that this is not necessary and that the two features can be provided in a single element. Even then, however, the manufacturing processes used to produce the CMOS wafers <NUM> are separate and distinct from the further processing that is described below.

With reference to <FIG>, a method of transferring an integrated circuit (IC) onto an alternative substrate at a wafer level to enable CTE matching is provided. While it is understood that the method is executable in the processing plant <NUM> relative to various types of wafers including, for example, the CMOS wafers <NUM> produced in the wafer manufacturing foundry <NUM> (each shown in <FIG>), the following description will relate only to the cases where the method is executed in the processing plant <NUM> relative to the CMOS wafers <NUM> produced in the wafer manufacturing foundry <NUM>. This is done for clarity and brevity and should not be considered as limiting the following description or claims in any way.

As shown in <FIG>, each one of the CMOS wafers <NUM> includes a circuit layer <NUM> and a substrate <NUM>. The circuit layer <NUM> is substantially planarized and may include various circuit elements, traces and CMOS devices. The circuit layer <NUM> may be approximately <NUM> thick and has a body <NUM>, a first major surface <NUM> on a first side of the body <NUM> and a second major surface <NUM> on a second side of the body <NUM> opposite the first side of the body <NUM>. The substrate <NUM> is affixed or bonded to the first major surface <NUM>.

As shown in <FIG>, a wafer-level handle (or simply handle) <NUM> is temporarily bonded to the second major surface <NUM> of the circuit layer <NUM>. The handle <NUM> may be formed of any suitable, somewhat rigid material including, but not limited to, metallic materials, ceramic materials and organic or inorganic dielectric, semiconductor or conductive materials. The handle <NUM> can be flat and have a uniform thickness and may be, but is not required to be, planarized. In any case, the handle <NUM> should generally conform to the topography of the second major surface <NUM>. The temporary bond between the handle <NUM> and the second major surface <NUM> may be provided by way of adhesive bonding using a thermoplastic adhesive.

As shown in <FIG>, according to the present invention, all or a substantial portion (e.g., ~<NUM>% or a majority) of the substrate <NUM> is removed. The removal of the substantial portion of the substrate <NUM> can be accomplished or conducted by way of etching, grinding and polishing or, more particularly, by way of a grinding of the bulk of the material of the substrate <NUM> stopping at a depth of approximately 10X the grit size from the desired final thickness and then polishing the last bits of the material of the substrate <NUM> away from the circuit layer <NUM>. In any case, the removal of the substantial portion of the substrate <NUM> serves to completely expose the first major surface <NUM> or, as shown in <FIG>, to nearly completely expose the first major surface <NUM> through a thin layer of substrate remainder <NUM>. In accordance with embodiments, the thin layer of the substrate remainder <NUM> (if it exists) is substantially thinner than the circuit layer <NUM> even where the circuit layer <NUM> is approximately ~<NUM> thick. As an example, for a modern complementary-metal-oxide-semiconductor (CMOS) process, the wafer would be thinned so that the thickness of the substrate remainder would be <NUM> or less.

Although <FIG> illustrate that the substrate <NUM> can be completely removed or that a substantial portion of the substrate <NUM> can be removed with only a thin layer of substrate remainder <NUM> remaining, the following description will relate to the former case for purposes of clarity and brevity.

As shown in <FIG>, an adhesive <NUM> is applied to the first major surface <NUM> of the circuit layer <NUM> that is now exposed as a result of the removal of the substrate <NUM>. In accordance with the present invention and, as shown in <FIG>, the adhesive <NUM> includes bonding oxide that is deposited (e.g., by physical vapor deposition or PVD) onto the first major surface <NUM> up to a first thickness T1 and then polished (e.g., by chemical mechanical polishing or CMP) down to a second thickness T2. The first thickness T1 may be approximately <NUM>-<NUM> and the second thickness T2 may be approximately <NUM>-<NUM>.

As shown in <FIG>, a wafer-level second substrate (or simply new or second substrate) <NUM> is bonded to the first major surface <NUM> of the circuit layer <NUM> (and any thin layer of substrate remainder <NUM> that remains on the first major surface <NUM>) using low-temperature oxide bonding (i.e., with the deposited and polished bonding oxide or adhesive <NUM>). The second substrate <NUM> may be approximately <NUM>µπ<IMG> thick and may be provided as or with a plasma activated oxide surface. The second substrate <NUM> material can be an aluminum oxide, Sapphire or ceramic. In the particular and exemplary case of the second substrate <NUM> being formed of Sapphire and/or other similar materials, the second substrate <NUM> effectively functions as a thermal matching substrate.

As used herein, a thermal matching substrate may be any substrate that, when bonded to the circuit layer <NUM>, alters the rate of thermal expansion of the circuit layer <NUM> in a desirable manner. In other words, the thermal matching substrate may include any material suitable for bonding to the circuit layer <NUM> and having a CTE that is different than the CTE of the circuit layer <NUM>. In certain embodiments, the thermal matching substrate can be a substrate that forms a composite-semiconductor structure having a desired rate of thermal expansion. This desired rate of thermal expansion may be substantially equal to the rate of thermal expansion of a substrate to which the circuit layer <NUM> is to be hybridized.

The second substrate <NUM>, acting as a thermal matching substrate, may have a CTE that is greater than the CTE of the circuit layer <NUM>. As a result, when the second substrate <NUM> is bonded to the circuit layer <NUM> (and a balancing substrate that may also be present), the second substrate <NUM> causes the circuit layer <NUM> to expand and contract at a greater rate in response to temperature changes. Alternatively, the second substrate <NUM> may have a CTE that is smaller than the CTE of the circuit layer <NUM>. As a result, when the second substrate <NUM> is bonded to the circuit layer <NUM> (and the balancing substrate that may also be present), the second substrate <NUM> causes the circuit layer <NUM> to expand and contract at a slower rate in response to temperature changes. Here the, balancing substrate (not shown) may be any substrate that, when bonded to the second substrate <NUM>, reduces or eliminates warping of the resulting composite-semiconductor structure of the second substrate <NUM> and the circuit layer <NUM> without substantially impacting the effective CTE of the composite-semiconductor structure.

In any case, <FIG> illustrates a wafer level integrated circuit (IC) transfer enabling structure <NUM>. The structure <NUM> includes the circuit layer <NUM> having the first major surface <NUM> and the second major surface <NUM> opposite the first major surface <NUM>, a potentially very thin or non-existing substrate remainder <NUM> (not shown in <FIG>) that is substantially thinner than the circuit layer <NUM> affixed to the first major surface <NUM>, the handle <NUM> being temporarily bonded to the second major surface <NUM> and a second (e.g., Sapphire) substrate <NUM>. The second substrate <NUM> is bonded to the first major surface <NUM> (and any thin layer of substrate remainder <NUM>) with the adhesive <NUM>.

With reference to <FIG>, once the second substrate <NUM> is bonded to the first major surface <NUM> of the circuit layer <NUM>, the handle <NUM> is removed leaving the second major surface <NUM> exposed and the circuit layer <NUM> permanently bonded to the second substrate <NUM>.

In accordance with further embodiments and, with reference to <FIG>, the circuit layer <NUM> to which the second substrate <NUM> is permanently bonded forms a hybridization ready structure <NUM> that is ready to be hybridized to a detector array. As such, as shown in <FIG>, a device <NUM> is formed by hybridizing the circuit layer <NUM> (with the second substrate <NUM>) to a thermally matched second substrate <NUM> using interconnects <NUM> that are deposited on the second major surface <NUM> of the circuit layer <NUM> and on complementary surface <NUM> of the second substrate <NUM>. The second substrate <NUM> may be provided, for example, as a detector array and as such includes an array of photo-electric elements therein. At least one or more of the interconnects <NUM> may be formed of indium (as in the case of indium bumps) and/or other similar materials (e.g., tin, lead, bismuth alloy or any other suitable conductive material).

The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

For comparison, <CIT> describes a CTE matching method where the CTE matching material is atomically bonded between two layers of semiconductor in order to adjust a composite material CTE to match another layer. In this case, the semiconductor layers are relatively thin and the CTE matching material is insufficiently stiff whereby a three layer structure is used to prevent the resulting structure from warping during temperature excursions. The description provided above, however, relates to cases in which the semiconductor layer (i.e., the circuit layer <NUM>) is relatively thin (e.g., approximately <NUM>) and the CTE matching substrate (i.e., the second substrate <NUM>) is relatively thick (e.g., approximately <NUM>). This significant thickness difference allows the CTE matching substrate to be highly resistant to warping so that warping effects in the resulting composite structure are effectively insignificant.

Claim 1:
A method of transferring an integrated circuit, IC, onto an alternative substrate at a wafer level to enable coefficient of thermal expansion, CTE, matching for a circuit layer to a different material,
the method being executed on a wafer (<NUM>) with a circuit layer (<NUM>), a first major surface (<NUM>) of the circuit layer, a second major surface (<NUM>) of the circuit layer opposite the first major surface, and a substrate (<NUM>) affixed to the first major surface,
the method comprising:
temporarily bonding a handle (<NUM>) to the second major surface (<NUM>);
removing all the substrate (<NUM>) to expose the first major surface (<NUM>), or removing a substantial portion of the substrate (<NUM>) to leave a thin layer of substrate remainder (<NUM>);
bonding a second substrate (<NUM>) to the first major surface (<NUM>), or to the thin layer of substrate remainder (<NUM>) that remains on the first major surface (<NUM>), wherein bonding the second substrate to the first major surface (<NUM>), or to the thin layer of substrate remainder (<NUM>) that remains on the first major surface (<NUM>), comprises:
depositing a bonding material comprising bonding oxide (<NUM>) onto the first major surface (<NUM>), or to the thin layer of substrate remainder (<NUM>) that remains on the first major surface (<NUM>), up to a first thickness T1; and
then polishing the bonding material (<NUM>) down to a second thickness T2;
removing the handle (<NUM>) from the second major surface (<NUM>); and
subsequently hybridizing the circuit layer (<NUM>) to a thermally matched additional substrate (<NUM>) using interconnects (<NUM>) that are deposited on the second major surface (<NUM>) of the circuit layer (<NUM>) and on a complimentary surface (<NUM>) of the additional substrate (<NUM>).