Patent Description:
In recent years, as conventional energy resources such as petroleum and coal are expected to be depleted, interest in alternative energy replacing these energy resources is on the rise. Of these, solar cells are attracting considerable attention as next generation cells which convert solar energy into electrical energy.

Such a solar cell may be manufactured by forming various layers and electrodes according to design. Solar cell efficiency may be determined according to design of various layers and electrodes. Low efficiency should be overcome in order to commercialize solar cells. Various layers and electrodes should be designed so that efficiency of solar cells can be maximized. <CIT> discloses a solar cell comprising a semiconductor substrate, a tunneling layer, a first conductive area on the tunneling layer, a second conductive type area on the tunneling layer, a trench between the first and second conductive type areas and a dielectric layer filling the trench. <CIT> discloses a method wherein a barrier area between first and second conductive type implanted regions is obtained thanks to two masks that are designed to be non-overlapping and to guarantee a gap between said implanted regions.

In the disclosure of document <CIT>, a mask and an etch step are used to form a trench between a first conductive type area and a second conductive type area. An insulating region is thereafter deposited in the trench.

In the process disclosed in document <CIT>, a trench and a dielectric layer filling the trench are also provided between the first and second conductive type areas.

<CIT> discloses a rear contacted heterojunction intrinsic thin layer solar cell comprising a silicon substrate, a passivating layer, a thin intrinsic amorphous silicon layer, an emitter layer, a base layer and a separation layer, wherein the adjacent regions of the emitter layer and the separating layer and adjacent regions of the baser layer and the separating layer are partially laterally overlapping in such a way that, in an overlapping area, at least a portion of the separating layer is located closer to the substrate than an overlapping portion of the respective one of the emitter layer and the base layer. <CIT> discloses a back contact type solar cell where an insulation pattern for insulating conductive regions of opposite conductive types from each other is formed before forming the conductive regions by using an inkjet printing method.

A method for manufacturing a solar cell according to the present invention is defined in the claims. One object is to provide a method for manufacturing a solar cell which is capable of improving reliability and maximizing efficiency.

The method for manufacturing a solar cell includes forming a tunneling layer on one surface of a semiconductor substrate, forming a semiconductor layer on the tunneling layer, and doping the semiconductor layer with a first conductive type dopant and a second conductive type dopant to form a first conductive type area and a second conductive type area separated from each other via a barrier area.

The solar cell obtained according to the method of the present invention includes the barrier area interposed between the first conductive type area and the second conductive type area disposed on one surface (for example, back surface) of the semiconductor substrate. As a result, shunt caused by undesired short between the first conductive type area and the second conductive type area can be prevented. In addition, the barrier area prevents connection between the first and second conductive type areas to undesired impurity layers, when alignment of the first and second electrodes connected to the first and second conductive type areas, respectively, is not reasonable. As a result, opening voltage and fill factor of the solar cell are improved and efficiency and power of the solar cell can be thus increased. The method for manufacturing a solar cell according to the present embodiment enables formation of the solar cell having a structure in a simple method.

As a result, properties and production efficiency of the solar cell can be improved.

Reference will now be made in detail to a process for manufacturing a solar cell according to an embodiment of the present invention, and also to examples that are useful for understanding the present invention, examples of which are illustrated in the accompanying drawings. The present invention is not limited to the embodiment and the embodiment may be modified into various forms. In the drawings, parts unrelated to the description may not be illustrated for clear and brief description of the present disclosure, and the same reference numbers may be used throughout the specification to refer to the same or considerably similar parts. In the drawings, the thickness or size may be exaggerated or reduced for more clear description. In addition, the size or area of each constituent element is not limited to that illustrated in the drawings.

It will be further understood that, throughout this specification, when one element is referred to as "comprising" another element, the term "comprising" specifies the presence of another element but does not preclude the presence of other additional elements, unless context clearly indicates otherwise. In addition, it will be understood that when one element such as a layer, a film, a region or a plate is referred to as being "on" another element, the one element may be directly on the another element, and one or more intervening elements may also be present. In contrast, when one element such as a layer, a film, a region or a plate is referred to as being "directly on" another element, one or more intervening elements are not present.

Hereinafter, a solar cell according to an example useful for understanding the present invention will be described in detail with reference to the annexed drawings.

<FIG> is a sectional view of a solar cell according to an example useful for understanding the present invention. Referring to <FIG>, the solar cell <NUM> according to the example includes a semiconductor substrate <NUM>, a tunneling layer <NUM> formed on one surface (for example, back surface) of the semiconductor substrate <NUM>, and a first conductive type area <NUM>, a second conductive type area <NUM> and a barrier area <NUM> formed on the tunneling layer <NUM>. In this case, the first conductive type area <NUM> and the second conductive type area <NUM> are spaced from each other via the barrier area <NUM>. The solar cell <NUM> further includes first and second electrodes <NUM> and <NUM> which are connected to first and second conductive type areas <NUM> and <NUM>, respectively, and collect carriers. In addition, an anti-reflective film <NUM> may be further formed on another surface of the semiconductor substrate <NUM>. This configuration will be described in detail.

The semiconductor substrate <NUM> may include a base area <NUM> containing a low doping concentration of first conductive type dopant.

The semiconductor substrate <NUM> may, for example, include a crystalline semiconductor (for example, crystalline silicon) containing a first conductive-type dopant. The crystalline semiconductor may be monocrystalline silicon, and the first conductive-type dopant may be, for example, an n-type or p-type dopant. That is, the first conductive-type dopant may be an n-type impurity such as a Group V element including phosphorous (P), arsenic (As), bismuth (Bi), antimony (Sb) or the like. Alternatively, the first conductive-type dopant may be a p-type impurity such as a Group III element including boron (B), aluminum (Al), gallium (Ga), indium (In) or the like.

The base area <NUM> may have an n-type impurity as the first conductive-type dopant. As a result, the second conductive type area <NUM> forming a tunnel junction through the tunneling layer <NUM> with the base area <NUM> may be a p-type. As a result, the first conductive type area <NUM> serving as an emitter causing photoelectric transformation through junction with the base area <NUM> may be widely formed and, as a result, holes having movement speed lower than electrons can be efficiently collected. Electrons created by photoelectric effect are collected by a first electrode <NUM> when light is emitted to the tunnel junction, and holes are moved toward the front surface of the semiconductor substrate <NUM> and are then collected by a second electrode <NUM>. As a result, electric energy is generated, but the present invention is not limited thereto, and the base area <NUM> and the first conductive type area <NUM> may be a p-type while the second conductive type area <NUM> may be an n-type.

The front surface of the semiconductor substrate <NUM> is textured to have irregularities having a shape such as a pyramidal shape. When surface roughness is increased due to irregularities formed on the front surface of the semiconductor substrate <NUM> through such texturing, reflection of light incident through the front surface of the semiconductor substrate <NUM> can be reduced. Accordingly, an amount of light which reaches the tunnel junction formed by the semiconductor substrate <NUM> and the second conductive type area <NUM> is increased and light loss can thus be minimized.

In addition, the back surface of the semiconductor substrate <NUM> may be a smooth and even surface having a surface roughness lower than the front surface, obtained through mirror polishing or the like. As a result, light which passes through the semiconductor substrate <NUM> and travels toward the back surface thereof is reflected at the back surface and travels toward the semiconductor substrate <NUM> again. When tunnel junction is formed through the tunneling layer <NUM> on the back surface of the semiconductor substrate <NUM>, as in the present example, properties of the solar cell <NUM> may be greatly changed according to properties of the semiconductor substrate <NUM>. For this reason, irregularities obtained by texturing are not formed on the back surface of the semiconductor substrate <NUM>, but the present invention is not limited thereto and a variety of modifications are possible. A front surface field layer <NUM> may be formed on the front surface of the semiconductor substrate <NUM> (that is, on the base area <NUM>). The front surface field layer <NUM> is an area where the first conductive-type dopant is doped at a concentration higher than the semiconductor substrate <NUM> and performs similar functions to a back surface field (BSF) layer. That is, the front surface field layer <NUM> prevents electrons and holes 'separated by incident light from being recombined and then decay on the front surface of the semiconductor substrate <NUM>. The front surface field layer <NUM> may be omitted. This example will be described in more detail with reference to <FIG>.

In addition, an anti-reflective film <NUM> may be formed on the front surface field layer <NUM>. The anti-reflective film <NUM> may be entirely formed over the front surface of the semiconductor substrate <NUM>. The anti-reflective film <NUM> decreases reflectivity of light incident upon the front surface of the semiconductor substrate <NUM> and passivates defects present on the surface or in the bulk of the front surface field layer <NUM>. The decrease in reflectivity of light incident upon the front surface of the semiconductor substrate <NUM> causes an increase in amount of light reaching the tunnel junction. Accordingly, short current (Isc) of the solar cell <NUM> can be increased. In addition, the anti-reflective film <NUM> passivates defects, removes recombination sites of minority carriers and thus increases open-circuit voltage (Voc) of the solar cell <NUM>. As such, the anti-reflective film <NUM> increases open-circuit voltage and short current of the solar cell <NUM>, thus improving conversion efficiency of the solar cell <NUM>.

The anti-reflective film <NUM> may be formed of a variety of materials. For example, the anti-reflective film <NUM> may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, MgF<NUM>, ZnS, TiO<NUM> and CeO<NUM>, or a multilayer film including a combination of two or more thereof, but the present disclosure is not limited thereto and the anti-reflective film <NUM> may include a variety of materials.

In the present example, a tunneling layer <NUM> is formed on the back surface of the semiconductor substrate <NUM>. The tunneling layer <NUM> improves interface properties of the back surface of the semiconductor substrate <NUM> and enables produced carriers to be efficiently transferred through tunneling effect. The tunneling layer <NUM> may include a variety of materials enabling tunneling of carriers and examples of the materials include oxides, nitrides and conductive polymers. The tunneling layer <NUM> may be entirely formed on the back surface of the semiconductor substrate <NUM>. Accordingly, the tunneling layer <NUM> entirely passivates the back surface of the semiconductor substrate <NUM> and can be easily formed without additional patterning.

A thickness of the tunneling layer <NUM> may be <NUM> or less so that the tunneling layer <NUM> sufficiently exhibits a tunneling effect, or may be <NUM> to <NUM> (for example, <NUM> to <NUM>). When the thickness of the tunneling layer <NUM> exceeds <NUM>, tunneling is not efficiently performed and the solar cell <NUM> may not operate, and when the thickness of the tunneling layer <NUM> is less than <NUM>, there may be difficulty in formation of the tunneling layer <NUM> with desired qualities. In order to further improve the tunneling effect, the thickness of the tunneling layer <NUM> may be <NUM> to <NUM>, but the present invention is not limited thereto and the thickness of the tunneling layer <NUM> may be changed.

In addition, a first conductive type area <NUM> having a first conductive type dopant, a second conductive type area <NUM> having a second conductive type dopant, and a barrier area <NUM> formed between the first conductive type area <NUM> and the second conductive type area <NUM> are formed on the tunneling layer <NUM>.

The first conductive type area <NUM> may include a semiconductor (for example, silicon) having the same conductive type as the semiconductor substrate <NUM>. The first conductive type area <NUM> may have a crystalline structure different from the base area <NUM> so that it is easily formed by a variety of methods such as deposition. For example, the first conductive type area <NUM> may be easily formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon or the like with a first conductive type dopant. The first conductive type dopant may be any dopant having the same conductive type as the semiconductor substrate <NUM>. That is, when the first conductive type dopant is an n-type dopant, a Group V element such as phosphorus (P), arsenic (As), bismuth (Bi) or antimony (Sb) may be used. When the first conductive type dopant is a p-type dopant, a Group III element such as boron (B), aluminum (Al), gallium (Ga) or indium (In) may be used. The first conductive type area <NUM> forms a back surface field structure and thereby functions to prevent carrier loss through recombination on the surface of the semiconductor substrate <NUM>. In addition, the first conductive type area <NUM> also functions to reduce contact resistance in a portion thereof contacting the first electrode <NUM>.

The second conductive type area <NUM> may include a semiconductor (for example, silicon) having a conductive type opposite to the semiconductor substrate <NUM>. The second conductive type area <NUM> may have a crystalline structure different from the base area <NUM> so that it is easily formed by a variety of methods such as deposition. For example, the second conductive type area <NUM> may be easily formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon or the like with a second conductive type dopant by a variety of methods such as deposition or printing. In this case, the second conductive type dopant may be any impurity having a conductive type opposite to the semiconductor substrate <NUM>. That is, when the second conductive type dopant is a p-type dopant, a Group III element such as boron (B), aluminum (Al), gallium (Ga) or indium (In) may be used. When the second conductive type dopant is an n-type dopant, a Group V element such as phosphorus (P), arsenic (As), bismuth (Bi) or antimony (Sb) may be used. The second conductive type area <NUM> forms a tunnel junction with the semiconductor substrate <NUM> through the tunneling layer <NUM>, thus substantially contributing to photoelectric transformation.

In addition, the barrier area <NUM> is disposed between the first conductive type area <NUM> and the second conductive type area <NUM> and separates the first conductive type area <NUM> from the second conductive type area <NUM>. When the first conductive type area <NUM> contacts the second conductive type area <NUM>, shunt is generated and performance of the solar cell <NUM> is deteriorated. Accordingly, in the present example, the barrier area <NUM> is interposed between the first conductive type dopant <NUM> and the second conductive type area <NUM>, thereby preventing unnecessary shunt.

The barrier area <NUM> may include a variety of materials for substantially insulating the first conductive type area <NUM> from the second conductive type area <NUM> and may be between the first and second conductive type areas <NUM> and <NUM>. The barrier area <NUM> may include an intrinsic semiconductor. In this case, the first and second conductive type areas <NUM> and <NUM>, and the barrier area <NUM> are flush with one another and may include an identical semiconductor material (for example, amorphous silicon, microcrystalline silicon or polycrystalline silicon). In this case, a semiconductor layer (represented by reference number "<NUM>" in <FIG>, the same will be applied below) including a semiconductor material is formed, a portion of the semiconductor layer <NUM> is doped with a first conductive type dopant to form a first conductive type area <NUM>, another portion of the semiconductor layer <NUM> is doped with a second conductive type dopant to form a second conductive type area <NUM>, and a portion of the semiconductor layer <NUM> in which the first and second conductive type areas <NUM> and <NUM> are not formed constitutes the barrier area <NUM>, thereby manufacturing the solar cell. That is, the formation methods of the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM> are simplified. This will be described in more detail in description associated with the manufacturing method later.

In the drawing, the barrier area <NUM> and the first and second conductive type areas <NUM> and <NUM> are formed simultaneously and have a substantially identical thickness.

Here, an area of the second conductive type area <NUM> having a conductive type different from the base area <NUM> may be greater than an area of the first conductive type area <NUM> having the same conductive type as the base area <NUM>. As a result, a tunnel junction formed through the tunneling layer <NUM> between the semiconductor substrate <NUM> and the second conductive type area <NUM> can be widely formed. In addition, as described above, when the base area <NUM> and the first conductive type area <NUM> have an n-conductive type and the second conductive type area <NUM> has a p-conductive type, holes having a low movement speed can be efficiently collected. Plane shapes of the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM> will be described in more detail with reference to <FIG> later. An insulating layer <NUM> may be formed on the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM>. The insulating layer <NUM> prevents undesired connection between the first and second conductive type areas <NUM> and <NUM> and an improper electrode connection (that is, the second electrode <NUM> in case of the first conductive type area <NUM>, and the first electrode <NUM> in case of the second conductive type area <NUM>) and passivates the first and second conductive type areas <NUM> and <NUM>. The insulating layer <NUM> includes a first opening <NUM> exposing the first conductive type area <NUM> and a second opening <NUM> exposing the second conductive type area <NUM>.

The insulating layer <NUM> may have a thickness greater than the tunneling layer <NUM>. As a result, insulating and passivation properties can be improved. The insulating layer <NUM> may be composed of a variety of insulating materials (for example, oxide or nitride). For example, the insulating layer <NUM> may have a structure of a single film selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, Al<NUM>O<NUM>, MgF<NUM>, ZnS, TiO<NUM> and CeO<NUM>, or a structure of a multilayer film including a combination of two or more thereof, but the present disclosure is not limited thereto and the insulating layer <NUM> may include a variety of materials.

The first electrode <NUM> passes through the first opening <NUM> of the insulating layer <NUM> and is connected to the first conductive type area <NUM>, and the second electrode <NUM> passes through the second opening <NUM> of the insulating layer <NUM> and is connected to the second conductive type area <NUM>. The first and second electrodes <NUM> and <NUM> may include a variety of metal materials. In addition, the first and second electrodes <NUM> and <NUM> may have a variety of plane shapes which are not electrically connected to each other and are connected to the first conductive type area <NUM> and the second conductive type area <NUM>, respectively, to collect produced carriers and transport the same to the outside. That is, the present disclosure is not limited to the plane shapes of the first and second electrodes <NUM> and <NUM>. Hereinafter, the plane shapes of the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM> will be described in detail with reference to <FIG> is a partial back plan view illustrating the solar cell <NUM> according to an example useful for understanding the present invention. The shapes of the first and second electrodes <NUM> and <NUM> shown in <FIG> is provided only as an example and the present disclosure is not limited thereto. That is, as shown in <FIG>, a plurality of first and second electrodes <NUM> and <NUM> are alternately disposed such that the first and second electrodes <NUM> and <NUM> are spaced from each other by a predetermined distance. The first electrodes <NUM> shown in <FIG> correspond to branch portions 42a of the first electrode <NUM> shown in <FIG>. The second electrodes <NUM> shown in <FIG> correspond to branch portions 44a shown in <FIG>. Although not separately shown in <FIG>, as shown in <FIG>, the first and second electrodes <NUM> and <NUM> may further include stem portions 42b and 44b connecting the branch portions 42a and 44a, respectively, at a side. However, as described above, the present disclosure is not limited thereto and shape, connection configuration or the like of the first and second electrodes <NUM> and <NUM> may be varied.

Referring to <FIG>, as described above, in the solar cell <NUM> according to the present example, the first conductive type area <NUM> is formed to have an area smaller than the second conductive type area <NUM>.

For this purpose, in the present example, a plurality of first conductive type areas <NUM> have an island shape and are spaced from one another. An area of the first conductive type areas <NUM> are minimized and the first conductive type areas <NUM> are entirely disposed over the semiconductor substrate <NUM>. The first conductive type area <NUM> efficiently prevents surface recombination and maximizes an area of the second conductive type area <NUM>, but the present invention is not limited thereto and the first conductive type area <NUM> may have a variety of shapes capable of minimizing the area of the first conductive type area <NUM>.

In addition, the first conductive type area <NUM> having a circular shape is exemplarily shown in the drawing, but the present disclosure is not limited thereto. Accordingly, the first conductive type area <NUM> may have a plane shape including an oval or a polygon, for example, a triangle, rectangle or hexagon.

A ratio of a total area of the first conductive type area <NUM> to a total area of the solar cell <NUM> may be <NUM>% to <NUM>% (more preferably <NUM>% to <NUM>%). When the ratio of the total area of the first conductive type area <NUM> is less than <NUM>%, contact between the first conductive type area <NUM> and the first electrode <NUM> is not accurately formed and contact resistance between the first conductive type area <NUM> and the first electrode <NUM> may thus be increased. When the area ratio exceeds <NUM>%, the area of the second conductive type area <NUM> is decreased and efficiency of the solar cell <NUM> is thus deteriorated, as described above. The area ratio is preferably <NUM>% to <NUM>% in consideration of efficiency of the solar cell.

The first conductive type area <NUM> may be respectively surrounded by the barrier area <NUM>. For example, when the first conductive type area <NUM> has a circular shape, the barrier area <NUM> may have a loop or ring shape. That is, the barrier area <NUM> surrounds the first conductive type area <NUM> to separate the first conductive type area <NUM> from the second conductive type area <NUM> and thereby prevents generation of undesired shunt. The drawing illustrates a case in which the barrier area <NUM> entirely surrounds the first conductive type area <NUM> and fundamentally prevents generation of shunt. However, the present disclosure is not limited thereto and the barrier area <NUM> may surround only a portion of a periphery of the first conductive type area <NUM>. In this case, the barrier area <NUM> is interposed between the first conductive type area <NUM> and the second conductive type area <NUM> and functions to separate the first conductive type area <NUM> from the second conductive type area <NUM>. For this reason, the barrier area <NUM> has a minimal width, enabling separation between the first and second conductive type areas <NUM> and <NUM>. That is, a width T1 of the barrier area <NUM> may be smaller than a width T2 of the first conductive type area <NUM> having a smaller area. Here, the width T2 of the first conductive type area <NUM> may be varied according to the shape of the first conductive type area <NUM>. When the first conductive type area <NUM> has a circular shape as shown in the drawing, the width T2 of the first conductive type area <NUM> is defined by a diameter and when the first conductive type area <NUM> has a polygonal shape, the width T2 of the first conductive type area <NUM> is defined by a long width. As a result, only undesired shunt of the first conductive type area <NUM> and the second conductive type area <NUM> can be prevented through a minimal area.

Here, the width T1 of the barrier area <NUM> may be <NUM> to <NUM>. When the width T1 of the barrier area <NUM> is less than <NUM> µm, the effect of electrically insulating the first and second conductive type areas <NUM> and <NUM> may be insufficient and when the width T1 of the barrier area <NUM> exceeds <NUM> µm, a ratio of a region (that is, a region corresponding to the barrier area <NUM>) not greatly contributing to photoelectric transformation is increased and efficiency of the solar cell <NUM> is thus deteriorated. In consideration of insulating effect and efficiency of the solar cell <NUM>, the width T1 of the barrier area <NUM> may be <NUM> µm to <NUM> µm.

For example, a ratio of a total area of the barrier area <NUM> to a total area of the solar cell <NUM> may be <NUM>% to <NUM>%. When the ratio is less than <NUM>%, it may be difficult to form the barrier area <NUM>. When the ratio exceeds <NUM>%, a ratio of a region (that is, a region corresponding to the barrier area <NUM>) not greatly contributing to photoelectric transformation is increased and a ratio of the first and second conductive areas <NUM> and <NUM> is decreased. And thus, efficiency of the solar cell <NUM> may be deteriorated. The width T2 of the first conductive type area <NUM> may be <NUM> µm to <NUM>,<NUM> µm. When the width T2 of the first conductive type area <NUM> is less than <NUM> µm, electrical connection between the first conductive type area <NUM> and the first electrode <NUM> may be not efficiently formed and when the width T2 exceeds <NUM>,<NUM> µm, an area of the second conductive type area <NUM> is decreased or a distance between the first conductive type areas <NUM> is increased. In consideration of connection to the first electrode <NUM>, area ratio or the like, the width T2 of the first conductive type area <NUM> may be <NUM> µm to <NUM> µm.

The first and second openings <NUM> and <NUM> formed in the insulating layer <NUM> may be formed to have different shapes in consideration of shapes of the first and second conductive type areas <NUM> and <NUM>. That is, a plurality of first openings <NUM> may be spaced from one another while being formed in regions corresponding to the first conductive type areas <NUM> and the second opening <NUM> may extend lengthwise. This is based on the configuration that the first electrode <NUM> is disposed on both the first conductive type area <NUM> and the second conductive type area <NUM>, while the second electrode <NUM> is disposed only on the second conductive type area <NUM>. That is, the first opening <NUM> is formed in a portion of the insulating layer <NUM> on the first conductive type area <NUM> and the first opening <NUM> connects the first electrode <NUM> to the first conductive type area <NUM>. In addition, the first opening <NUM> is not formed in a portion of the insulating layer <NUM> on the second conductive type area <NUM> to maintain insulation between the first electrode <NUM> and the second conductive type area <NUM>. Because the second electrode <NUM> is formed only on the second conductive type area <NUM>, the second opening <NUM> is formed to have a shape the same as or similar to the second electrode <NUM> such that the second electrode <NUM> entirely contacts the second conductive type area <NUM>.

As described above, the solar cell <NUM> according to the example includes the barrier area <NUM> interposed between the first conductive type area <NUM> and the second conductive type area <NUM> disposed on one surface (for example, back surface) of the semiconductor substrate <NUM>. As a result, shunt caused by undesired short between the first conductive type area <NUM> and the second conductive type area <NUM> can be prevented. In addition, the barrier area <NUM> prevents connection between the first and second conductive type areas <NUM> and <NUM> and undesired impurity layers, when alignment of the first and second electrodes <NUM> and <NUM> connected to the first and second conductive type areas <NUM> and <NUM>, respectively, is not reasonable. As a result, opening voltage and fill factor of the solar cell <NUM> are improved, and efficiency and power of the solar cell <NUM> can be thus increased. In the present example, the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM> are simultaneously formed in a single process, thereby obtaining the solar cell <NUM> with an improved structure through a simple process. This will be described in more detail with reference to <FIG>. Hereinafter, details of the description given above may not be mentioned and only the difference from the description above may be described in detail. <FIG> are sectional views illustrating a method for manufacturing the solar cell according to an embodiment of the present invention. First, as shown in <FIG>, a semiconductor substrate <NUM> including a base area <NUM> having a first conductive- type dopant is prepared during preparation of the substrate. In the present embodiment, the semiconductor substrate <NUM> may include silicon having an n-type impurity. Examples of the n-type impurity include Group V elements such as phosphorous (P), arsenic (As), bismuth (Bi) and antimony (Sb). The front surface of the semiconductor substrate <NUM> is textured so that the front surface has irregularities and the back surface of the semiconductor substrate <NUM> is subjected to treatment such as mirror polishing so that the back surface of the semiconductor substrate <NUM> has a lower surface roughness than the front surface thereof.

Wet or dry texturing may be used as the texturing of the front surface of the semiconductor substrate <NUM>. Wet texturing may be carried out by dipping the semiconductor substrate <NUM> in a texturing solution and has an advantage of short process time. Dry texturing is a process of cutting the surface of the semiconductor substrate <NUM> using a diamond drill, laser or the like and enables formation of uniform irregularities, but disadvantageously has long process time and may cause damage to the semiconductor substrate <NUM>. Alternatively, the semiconductor substrate <NUM> may be textured by reactive ion etching (RIE) or the like. As such, the semiconductor substrate <NUM> may be textured by a variety of methods. In addition, the back surface of the semiconductor substrate <NUM> may be treated by a known mirror surface polishing method.

Next, as shown in <FIG>, a tunneling layer <NUM> is formed on the back surface of the semiconductor substrate <NUM>. The tunneling layer <NUM> may be formed by a method such as thermal growth or deposition (for example, plasma-enhanced chemical vapor deposition chemical (PECVD), atomic layer deposition (ALD)) or the like, but the present invention is not limited thereto and the tunneling layer <NUM> may be formed by a variety of methods.

Next, as shown in <FIG>, a semiconductor layer <NUM> is formed on the tunneling layer <NUM>. The semiconductor layer <NUM> includes a microcrystalline, amorphous or polycrystalline semiconductor. The semiconductor layer <NUM> may be formed by a method, for example, thermal growth, deposition (for example, plasma-enhanced chemical vapor deposition chemical (PECVD)) or the like, but the present invention is not limited thereto and the semiconductor layer <NUM> may be formed by a variety of methods.

Next, as shown in <FIG>, a plurality of first conductive type areas <NUM>, a plurality of second conductive type areas <NUM> and a plurality of barrier areas <NUM> are formed on the semiconductor layer <NUM>. This will be described in more detail.

That is, as shown in <FIG>, a first doping layer <NUM> is formed in regions corresponding to the first conductive type areas <NUM>. The first doping layer <NUM> may include various layers including a first conductive type dopant and may be phosphorous silicate glass (PSG). The first doping layer <NUM> can be easily formed using phosphorous silicate glass (PSG). The first doping layer <NUM> may include a plurality of doping portions corresponding to the first conductive type areas <NUM>. The doping portions may have island shapes corresponding to the second conductive type areas <NUM>.

The first doping layer <NUM> may be formed to have a shape corresponding to the first conductive type area <NUM> on the semiconductor layer <NUM> using a mask. Alternatively, the first doping layer <NUM> may be formed to have a shape corresponding to the first conductive type area <NUM> on the semiconductor layer <NUM> by a method such as ink-jetting or screen printing. Alternatively, the first doping layer <NUM> may be formed by entirely forming a material for forming the first doping layer <NUM> on the semiconductor layer <NUM>, and removing regions where the first conductive type areas <NUM> are not formed using an etching solution, an etching paste or the like.

Next, as shown in <FIG>, an undoped layer <NUM> is formed such that the undoped layer <NUM> covers the first doping layer <NUM> and a portion of the semiconductor layer <NUM> adjacent thereto. The undoped layer <NUM> includes a material not including the first and second conductive type areas. For example, the undoped layer <NUM> may include silicate or an insulating film. The undoped layer <NUM> may include a plurality of portions respectively corresponding to the doping portions of the first doping layer <NUM> and covering areas greater than the doping portions of the first doping layer <NUM>.

The undoped layer <NUM> may be formed to have a desired shape using a mask on the semiconductor layer <NUM>. Alternatively, the undoped layer <NUM> may be formed on the semiconductor layer <NUM> by a method such as ink-jetting or screen printing. Alternatively, the undoped layer <NUM> may be formed by entirely forming a material for forming the undoped layer <NUM> over the first doping layer <NUM> and the semiconductor layer <NUM>, and removing undesired regions using an etching solution, an etching paste or the like.

Next, as shown in <FIG>, a second doping layer <NUM> are formed on the undoped layer <NUM> and the semiconductor layer <NUM>. The second doping layer <NUM> may include a variety of layers including a second conductive type dopant and may be boron silicate glass (BSG). The second doping layer <NUM> can be easily formed using boron silicate glass. The second doping layer <NUM> may be entirely formed to cover the undoped layer <NUM> and the semiconductor layer <NUM>.

Next, as shown in <FIG>, the first conductive type dopant in the first doping layer <NUM> is diffused into the semiconductor layer <NUM> by thermal treatment to form a plurality of first conductive type areas <NUM>, and the second conductive type dopant in the second doping layer <NUM> is diffused into the semiconductor layer <NUM> to form a plurality of second conductive type areas <NUM>. Portions adjacent to the undoped layer <NUM> and interposed between the first conductive type area <NUM> and the second conductive type area <NUM> are not doped and the semiconductor layer <NUM> remains unremoved to constitute a plurality of barrier areas <NUM>. As a result, each barrier area <NUM> is interposed between the first conductive type area <NUM> and the second conductive type area <NUM>, while separating the first conductive type area <NUM> from the second conductive type area <NUM>.

The first doping layer <NUM>, the undoped layer <NUM> and the second doping layer <NUM> are removed. The removal may be carried out using well-known various methods. For example, the first doping layer <NUM>, the undoped layer <NUM> and the second doping layer <NUM> are removed by immersing in diluted HF and then cleaning with water, but the present invention is not limited thereto.

Next, as shown in <FIG>, an insulating layer <NUM> is formed on the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM>. The insulating layer <NUM> may be formed by a variety of methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating, but the present invention is not limited thereto and various methods may be used.

Next, as shown in <FIG>, a front surface field layer <NUM> and an anti-reflective film <NUM> are formed on the front surface of the semiconductor substrate <NUM>.

The front surface field layer <NUM> may be formed by doping a first conductive type dopant. For example, the front surface field layer <NUM> may be formed by doping the semiconductor substrate <NUM> with a first conductive type dopant by a variety of methods such as ion implantation or thermal diffusion.

The anti-reflective film <NUM> may be formed by a variety of methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating.

Next, as shown in <FIG>, openings <NUM> and <NUM> exposing the first and second conductive type areas <NUM> and <NUM> are formed and as shown in <FIG>, first and second electrodes <NUM> and <NUM> electrically connected to the first and second conductive type areas <NUM> and <NUM>, respectively, are formed. In this case, for example, the first and second electrodes <NUM> and <NUM> may be formed in the opening by a variety of methods such as coating or deposition.

In another embodiment, the first and second electrodes <NUM> and <NUM> may be formed by applying a paste for forming the first electrode onto the insulating layer <NUM> by screen printing or the like and then performing fire through, laser firing contact or the like thereon. In this case, because the openings <NUM> and <NUM> are formed during formation of the first and second electrodes <NUM> and <NUM>, a process (process of <FIG>) of separately forming openings <NUM> and <NUM> is not required.

According to the present embodiment, the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM> are simultaneously formed by a simple process including forming the semiconductor layer <NUM> and then doping a portion thereof with an impurity, thereby simplifying manufacturing method of the solar cell <NUM> and improving production efficiency. In particular, the first doping layer <NUM> and the undoped layer <NUM>, each including a plurality of portions, are formed and the second doping layer <NUM> is then formed over the entire surface including the resulting structure, thereby minimizing the number of patterning operations and simultaneously forming the first and second conductive type areas <NUM> and <NUM> and the barrier area <NUM>. Accordingly, production efficiency can be greatly improved.

Unlike the present embodiment, when the first and second conductive type areas are separated by etching portions between the first and second conductive type areas, a portion of the semiconductor substrate is etched and is thus exposed to the outside. As a result, the semiconductor substrate is damaged and properties of solar cell are deteriorated. In order to prevent these problems, an additional passivation layer should be formed in a portion of the semiconductor substrate exposed to the outside. As a result, qualities and production efficiency of solar cells are deteriorated.

An embodiment in which the tunneling layer <NUM>, the first and second conductive type areas <NUM> and <NUM>, the barrier area <NUM> and the insulating layer <NUM> are formed, the front surface field layer <NUM> and anti-reflective film <NUM> are formed, and the first and second electrodes <NUM> and <NUM> are formed is given in the embodiment described above, but the present invention is not limited thereto. Accordingly, a formation order of the tunneling layer <NUM>, the first and second conductive type areas <NUM> and <NUM>, the barrier area <NUM>, the insulating layer <NUM>, the front surface field layer <NUM>, the anti-reflective film <NUM>, and the first and second electrodes <NUM> and <NUM> may be varied.

Hereinafter, a method for manufacturing the solar cell according to another embodiment will be described in more detail with reference to <FIG> and <FIG>. Details of contents the same as or similar to the description given above may not be mentioned and only the difference from the description above may be described in detail.

<FIG> is a back surface plan view illustrating a solar cell according to an example useful for understanding the present invention. For clear and brief illustration, the insulating layer <NUM> is not shown in <FIG>.

Referring to <FIG>, the first conductive type area <NUM> may include a first stem portion 32a formed along a first edge (upper edge in the drawing) of the semiconductor substrate <NUM> and a plurality of first branch portions 32b which extend from the first stem portion 32a toward a second edge (lower edge in the drawing) opposite to the first edge. The plurality of first branch portions 32b are aligned to be parallel to each other to have a shape of a stripe pattern. The second conductive type area <NUM> may include a second stem portion 34a formed along the second edge of the semiconductor substrate <NUM> and a plurality of second branch portions 32b which extend between the first branch portions 32b toward the first edge from the second stem portion 34a. The plurality of second branch portions 34b are aligned to be parallel to each other to have a shape of a stripe pattern. The first branch portions 32b of the first conductive type area <NUM> and the second branch portions 34b of the second conductive type area <NUM> may be alternately disposed. Though this configuration, a junction area can be increased and carriers can be entirely collected. In addition, the barrier area <NUM> may be formed between the first conductive type area <NUM> and the second conductive type area <NUM>.

As described above, an area of the first conductive type area <NUM> may be smaller than an area of the second conductive type area <NUM>. For example, the area of the first and second conductive type areas <NUM> and <NUM> can be controlled by changing the first and second stem portions 32a and 34a and/or the first and second branch portions 32b and 34b of the first and second conductive type areas <NUM> and <NUM>.

The first electrode <NUM> includes a stem portion 42a formed in a region corresponding to the first stem portion 32a of the first conductive type area <NUM>, and a branch portion 42b formed in a region corresponding to the branch portion 32b of the first conductive type area <NUM>. Similarly, the second electrode <NUM> may include a stem portion 44a in a region corresponding to the second stem portion 34a of the second conductive type area <NUM>, and a branch portion 44b formed in a region corresponding to the branch portion 34b of the second conductive type area <NUM>, but the present disclosure is not limited thereto and the first electrode <NUM> and the second electrode <NUM> may have a variety of plane shapes.

It is exemplified that the first conductive type area has the first stem portion 32a, the second conductive type area has the second stem portion 34a, the first electrode <NUM> has the stem portion 42a, and the second electrode <NUM> has the stem portion 44a. However, the present disclosure is not limited thereto, and the first and second stem portions 32a and 34a, and the stem portions 42a and 44a are not necessary. Therefore, the first and/or second stem portions 32a and 34a, and/or the stem portions 42a and 44a may be not formed or may be not included. In this case, each of the first and second conductive type areas <NUM> and <NUM> consisting of the first and second branch portions 32b and 34b has a stripe pattern, and the barrier area <NUM> has a shape of a stripe pattern between the branch portion 32b of the first conductive type area <NUM> and the branch portion 32b of the second conductive type area <NUM>.

For example, a ratio of a total area of the first conductive type area <NUM> to a total area of the solar cell <NUM> may be <NUM>% to <NUM>% (more preferably <NUM>% to <NUM>%). When the ratio of the total area of the first conductive type area <NUM> is less than <NUM>%, contact between the first conductive type area <NUM> and the first electrode <NUM> is not accurately formed and contact resistance between the first conductive type area <NUM> and the first electrode <NUM> may thus be increased. When the area ratio exceeds <NUM>%, the area of the first conductive type area <NUM> is decreased and efficiency of the solar cell <NUM> is thus deteriorated, as described above. The area ratio is preferably <NUM>% to <NUM>% in consideration of efficiency of the solar cell.

The width of each of the first branch portions 32b having the stripe pattern may be <NUM> µm to <NUM>,<NUM> µm. When the width of the first branch portions 32b is less than <NUM> µm, electrical connection between the first conductive type area <NUM> and the first electrode <NUM> may be not efficiently formed. When the width exceeds <NUM>,<NUM> µm, an area of the second conductive type area <NUM> is decreased or a distance between the first conductive type areas <NUM> is increased. In consideration of connection to the first electrode <NUM>, area ratio or the like, the width of each of the first branch portions 32b <NUM> may be <NUM> to <NUM>. When the first branch portions 32b has the stripe pattern, the first branch portions 32b can be stably connected to the first electrode <NUM>, compared with the first conductive type having a dot shape shown in <FIG>.

<FIG> is a sectional view illustrating a solar cell according to, another example useful for understanding the present invention.

Referring to the solar cell illustrated in <FIG>, the semiconductor substrate <NUM> includes only the base area <NUM> and does not include an additional front surface field layer (represented by reference numeral "<NUM>" in <FIG>, the same will be applied below). Instead, a field effect-forming layer <NUM> which contacts the base area <NUM> of the semiconductor substrate <NUM> and has a fixed charge is formed. Similar to the front surface field layer <NUM>, the field effect-forming layer <NUM> generates a certain field effect and thereby prevents surface recombination. The field effect-forming layer <NUM> may be composed of aluminum oxide having a negative charge, or silicon oxide or silicon nitride having a positive charge or the like. Although not additionally shown, an additional anti-reflective film (represented by reference numeral "<NUM>" in <FIG>) may be further formed on the field effect-forming layer <NUM>.

As such, the semiconductor substrate <NUM> does not include an additional doping area and includes only a base area <NUM>. As a result, a process of forming the additional doping area is eliminated and the overall process is thus simplified. During doping to form the additional doping area, deterioration in properties of the solar cell <NUM> caused by damage to the semiconductor substrate <NUM> can be prevented.

Here, an amount of fixed charges of the field effect-forming layer <NUM> is for example <NUM> X <NUM><NUM>/cm<NUM> to <NUM> X <NUM><NUM> /cm<NUM>. The amount of the fixed charges is a level enabling generation of the field effect in the semiconductor substrate <NUM> not including the doping area. More specifically, in consideration of the field effect, the amount of fixed charges may be <NUM> X <NUM><NUM>/cm<NUM> to <NUM> X <NUM><NUM>/cm<NUM>, but the present invention is not limited thereto and the amount of fixed charges may be varied.

Claim 1:
A method for manufacturing a solar cell (<NUM>) comprising:
- forming a tunneling layer (<NUM>) on one surface of a semiconductor substrate (<NUM>);
- forming a semiconductor layer (<NUM>) on the tunneling layer (<NUM>); and
- doping the semiconductor layer (<NUM>) with a first conductive type dopant and a second conductive type dopant to form a first conductive type area (<NUM>) and a second conductive type area (<NUM>) separated from each other via a barrier area (<NUM>) wherein the doping of the semiconductor layer (<NUM>) comprises:
- forming a first doping layer (<NUM>) including the first conductive type dopant on the semiconductor layer, in an area corresponding to the first conductive type area (<NUM>);
- forming an undoped layer (<NUM>) on the first doping layer (<NUM>) and on a portion of the semiconductor layer adjacent to the first doping layer;
- forming a second doping layer (<NUM>) including the second conductive type dopant on the undoped layer (<NUM>) and the semiconductor layer (<NUM>), so as to entirely cover the undoped layer (<NUM>) and the semiconductor layer (<NUM>); and
- diffusing the first conductive type dopant and the second conductive type dopant into the semiconductor layer to simultaneously form the first conductive type area (<NUM>), the second conductive type area (<NUM>) and the barrier area (<NUM>),
- wherein, in the diffusion, a portion of the semiconductor layer (<NUM>) into which the first conductive type dopant is diffused constitutes the first conductive type area (<NUM>), a portion of the semiconductor layer into which the second conductive type dopant is diffused constitutes the second conductive type area (<NUM>), and an undoped portion between the first conductive type area and the second conductive type area constitutes the barrier area (<NUM>).