Patent Description:
Embodiments of the present disclosure relate to a display device.

A display device is a device for visually displaying data (e.g., images). Such a display device includes a substrate partitioned into a display area and a non-display area. In the display area, a plurality of pixels are arranged on the substrate, and in the non-display area, a plurality of pads and the like are arranged on the substrate. A flexible film (COF film) equipped with a driving circuit or the like is attached to the plurality of pads to transmit driving signals to the pixels.

The flexible film includes a plurality of leads coupled with the plurality of pads, and the respective leads may be bonded to the pads, which are separated from each other. The bonding may be performed by an ultrasonic bonding process. When each of the leads of the flexible film is coupled to (e.g., connected to) the pad by the ultrasonic bonding, stress is applied to the interface of the pads. In this case, if stress generated between the lead and the pad contacting each other is not sufficient, defective bonding may occur.

<CIT> discloses a display device comprising a display area including pixels, a non-display area around the display area, a substrate, and a plurality of data lines connecting the pixels to a data driver located in the non-display area. <CIT>, <CIT> and <CIT> deal with OLED display devices including a pad region. <CIT> concerns a display device and a manufacturing method that may minimize an occurrence of a defect in the display device.

The present invention is defined in claim <NUM>, which is capable of increasing the bonding reliability of pads.

In the present invention the surface of the insulating layer does conformally reflect a step due to the plurality of first conductive patterns, and the concave and convex portions of the surface of the second conductive pattern are conformally reflected by the surface of the insulating layer.

In an exemplary embodiment, the insulating layer may include an inorganic insulating material.

In an exemplary embodiment, the plurality of first conductive patterns and the second conductive pattern may include different materials from each other (e.g., the plurality of first conductive patterns may include a material that is different from that of the second conductive pattern).

In an exemplary embodiment, the plurality of first conductive patterns may include molybdenum (Mo), and the second conductive pattern may include aluminum (Al).

In an exemplary embodiment, a width of the convex portion of the second conductive pattern is greater than a width of the convex portion of the insulating layer corresponding thereto in a second direction, and a width of the convex portion of the insulating layer is greater than a width of the first conductive pattern corresponding thereto in the second direction.

In an exemplary embodiment, a width of the concave portion of the second conductive pattern may be smaller than a width of the concave portion of the insulating layer corresponding thereto in the second direction, and a width of the concave portion of the insulating layer is smaller than a width of a non-layout space of the first conductive pattern corresponding thereto in the second direction.

In an exemplary embodiment, the insulating layer includes at least one contact hole, and each of the first conductive patterns may be electrically coupled to (e.g., electrically connected to) the second conductive pattern through the contact hole.

In an exemplary embodiment, the display device may further comprise a second insulating layer and a plurality of third conductive patterns sequentially disposed between the plurality of first conductive patterns and the insulating layer, wherein the plurality of third conductive patterns overlap the plurality of first conductive patterns in a thickness direction.

In an exemplary embodiment, the insulating layer may include an inorganic insulating material, each of the plurality of first conductive patterns and the plurality of third conductive patterns includes molybdenum (Mo), and the second conductive pattern includes aluminum (Al).

In an exemplary embodiment, the second conductive pattern may extend in a second direction, each of the plurality of first conductive patterns extends in a first direction perpendicular (e.g., substantially perpendicular) to the second direction, and the plurality of first conductive patterns are arranged in the second direction.

In an exemplary embodiment, the second conductive pattern may extend in a second direction, and the plurality of first conductive patterns have an island shape and are arranged along the first direction and a second direction perpendicular (e.g., substantially perpendicular) to the first direction.

In an exemplary embodiment, the second conductive pattern may extend in a second direction, each of the plurality of first conductive patterns extends in a zigzag shape along a second direction perpendicular (e.g., substantially perpendicular) to the first direction, and the plurality of first conductive patterns are arranged along the first direction.

In an exemplary embodiment, the second conductive pattern may extend in a second direction, each of the plurality of first conductive patterns extends in a zigzag shape along the first direction, and the plurality of first conductive patterns are arranged along a second direction perpendicular (e.g., substantially perpendicular) to the first direction.

The second conductive patternis integrally formed, and does extend outward from both ends of the plurality of first conductive patterns to completely cover the plurality of first conductive patterns.

In an exemplary embodiment, the display device may further comprise a first film attached onto the substrate in the non-display area, wherein the first film includes a second terminal ultrasonically bonded to the first terminal.

In an exemplary embodiment, the display device may further comprise a circuit substrate attached to the first film, wherein the first film further includes a third terminal spaced from the second terminal, and the circuit substrate includes a fourth terminal ultrasonically bonded to the third terminal.

The above and other aspects and features of embodiments of the present disclosure will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which:.

The features of the subject matter of the present disclosure, and methods for achieving those features, will be apparent by referring to the embodiments to be described in more detail herein with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed hereinafter, but can be implemented in diverse forms. The matters defined in the description, such as the detailed construction and elements, are details provided to assist those of ordinary skill in the art in a comprehensive understanding of the subject matter of the present disclosure, and the present disclosure is only defined by the scope of the appended claims.

Where an element is described as being related to another element such as being "on" another element or "located on" a different layer or a layer, includes both a case where an element is located directly on another element or a layer and a case where an element is located on another element via another layer or still another element. In contrast, where an element is described as being is related to another element such as being "directly on" another element or "located directly on" a different layer or a layer, indicates a case where an element is located on another element or a layer with no intervening element or layer therebetween.

Throughout the present disclosure, the same reference numerals are used for the same or similar parts.

Hereinafter, embodiments of the present disclosure will be described with reference to the attached drawings.

<FIG> is a plan view of a display device according to an embodiment, and <FIG> is an enlarged plan view of the display panel of <FIG>.

A display device <NUM>, which is a device for displaying a moving image or a still image, may be used as a display screen for various suitable products such as televisions, notebook computers, monitors, billboards, and internet of things, as well as portable electronic appliances such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigators, and ultra mobile PCs.

Referring to <FIG>, the display device <NUM> includes a display area DA for displaying an image and a non-display area NA disposed around the display area DA. The display area DA may have a rectangular shape having vertical corners or a rectangular shape having rounded corners in a plan view. The planar shape of the display area DA is not limited to a rectangle, and the display area DA may have a circular shape, an elliptical shape, or various other suitable shapes.

The non-display area NA is disposed around the display area DA. The non-display area NA may be disposed adjacent to both short sides of the display area DA. Moreover, the non-display area NA may be disposed adjacent to both long sides as well as both short sides of the display area DA, and may surround all sides of the display area DA. For example, the non-display area NA may constitute a frame of the display area DA.

The display device <NUM> may include a display panel <NUM> for displaying an image.

For example, the display panel <NUM> may be an organic light emitting display panel. In the following embodiments, there is exemplified a case where an organic light emitting display panel is applied as a display panel, but the present disclosure is not limited thereto, and other types (or kinds) of display panels such as a liquid crystal display panel, a quantum nano emitting display panel, a micro-LED, a field emission display panel, and an electrophoretic display panel may be applied as the display panel.

The display panel <NUM> includes a plurality of pixels. The plurality of pixels may be arranged in the display area DA. The display panel <NUM> may include a panel pad area PA_P disposed in the non-display area NA. The panel pad area PA_P is located at one side of the display area DA in the non-display area NA. For example, as shown in <FIG>, the panel pad area PA_P may be disposed adjacent to the lower side of the display area DA along a second direction DR2. The width of the non-display area NA (lower side of the display area in the drawing) in the second direction DR2 where the panel pad area PA_P is located may be greater than the width of the other non-display area NA (upper side, left side, or right side of the display area in the drawing) in the first direction DR1 and/or the second direction DR2 where the panel pad area PA_P is not located.

As shown in <FIG>, a plurality of panel pad terminals PE_P may be arranged in the panel pad area PA_P. The plurality of panel pad terminals PE_P may be arranged in a row in one direction. For example, the plurality of panel pad terminals PE_P may be arranged in a first direction DR1 perpendicular to the second direction DR2. Although it is shown in the drawings that the panel pad area PA_P includes one row of panel pad terminals PE_P, the present disclosure is not limited thereto, and the panel pad area PA_P may include two or more rows spaced apart from each other in the second direction DR2. Each of the panel pad terminal PE_P may be coupled to (e.g., connected to) a wiring extending from the display area DA. Further, each of the panel pad terminals PE_P may be electrically coupled to (e.g., electrically connected to) a data driving integrated circuit to be described later. Each of the panel pad terminals PE_P may have a surface concave-convex shape. Since the panel pad terminal PE_P has a surface concave-convex shape, bonding reliability between the panel pad terminal PE_P and the COF film <NUM> may be increased. Additional details thereof will be further described herein below.

In an embodiment, the data driving integrated circuit may be formed in the form of a data driving chip D_IC. The data driving chip D_IC may be attached to a plastic substrate or a glass substrate by a chip on plastic (COP) method or a chip on glass (COG) method. Hereinafter, a case where a chip on film (COF) method, in which the data driving chip D_IC is attached to a display panel through a flexible film, is applied will be mainly described.

When the chip on film (COF) method is applied, as shown in <FIG>, the COF film <NUM> including the data driving chip D_IC may be attached to the panel pad area PA_P of the display panel <NUM>. In an embodiment, one end of the COF film <NUM> in the second direction DR2 may be attached to the panel pad area PA_P of the display panel <NUM>. Meanwhile, a PCB (Printed Circuit Board) substrate <NUM> may be attached to the other end of the COF film <NUM> in the second direction DR2. Additional details of the COF film <NUM> and the PCB substrate <NUM> will be further described herein below.

<FIG> is a plan view of the COF film of <FIG>.

As shown in <FIG>, the COF film <NUM> may include a base film <NUM>, and a data driving chip D_IC, a plurality of input lead terminals PE_ILB, and a plurality of output lead terminals PE_OLB, which are disposed on the base film <NUM>. Each of the plurality of input lead terminals PE_ILB and each of the plurality of output lead terminals PE_OLB is coupled (i.e. electrically connected) to the data driving chip D_IC.

The base film <NUM> may serve to support the elements disposed on the base film <NUM>, and may include a soft material. For example, the base film <NUM> may include polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacryalte (PMMA), triacetylcellulose (TAC), or cycloolefin polymer (COP).

The data driving chip D_IC may be disposed on one region of the base film <NUM>, for example, in the center of the base film <NUM>. The data driving chip D_IC may function to receive a video signal applied from the PCB substrate <NUM>, convert the video signal into a data signal in the form of an analog voltage, and transmit the data signal to a pixel.

The plurality of output lead terminals PE_OLB may be arranged on one end of the base film <NUM> in the second direction DR2. The output lead terminals PE_OLB may be arranged in a row in one direction. For example, the output lead terminals PE_OLB may be arranged in parallel (e.g., substantially in parallel) to each other in the first direction DR1. Although it is shown in the drawings that the output lead terminals PE_OLB are arranged in a single row, the present disclosure is not limited thereto, and the output lead terminals PE_OLB may be arranged in a plurality of rows spaced apart in the second direction DR2. The output lead terminal PE_OLB may be attached to a panel pad area PA_P of the display panel <NUM> by, for example, ultrasonic bonding.

The plurality of input lead terminals PE_ILB may be arranged on the other end of the base film <NUM> opposed to the end on which the output lead terminals PE_OLB are arranged. The input lead terminals PE_ILB may be arranged in a row in one direction. For example, the input lead terminals PE_ILB may be arranged in parallel (e.g., substantially in parallel) to each other in the first direction DR1. Although it is shown in the drawings that the input lead terminals PE_ILB are arranged in a single row, the present disclosure is not limited thereto, and the input lead terminals PE_ILB may be arranged in a plurality of rows spaced apart in the second direction DR2. The input lead terminal PE_ILB may be attached to a PCB pad area PA_B of the PCB substrate <NUM> by, for example, ultrasonic bonding.

The size of each of the output lead terminals PE_OLB and the input lead terminals PE_ILB may be smaller than that of the panel pad terminal PE_P or the PCB pad terminal (refer to <FIG> 'PE_B'). However, the present disclosure is not limited thereto, and the size of each of the output lead terminals PE_OLB and the input lead terminals PE_ILB may be equal to or larger than that of the panel pad terminal PE_P or the PCB pad terminal.

The materials of the plurality of output lead terminals PE_OLB and the input lead terminals PE_ILB are not particularly limited as long as they are materials capable of easily bonding with the panel pad terminals PE_P and the PCB pad terminals (refer to <FIG> 'PE_B'). For example, the output lead terminals PE_OLB and the input lead terminals PE_ILB may be formed of at least one of gold (Au), nickel (Ni), and tin (Sn). The plurality of output lead terminals PE_OLB and the input lead terminals PE_ILB may have a single film structure or laminate film structure formed of the above materials.

Each of the output lead terminals PE_OLB of the COF film <NUM> may be directly bonded and coupled to (e.g., connected to) each of the panel pad terminals PE_P of the display panel <NUM>. Further, each of the input lead terminals PE_ILB may be directly bonded and coupled to (e.g., connected to) each of the PCB pad terminals PE_B of the PCB substrate <NUM>. In an embodiment, the output lead terminal PE_OLB and the input lead terminal PE_ILB of the COF film <NUM> may be electrically coupled to (e.g., electrically connected to) the panel pad terminals PE_P and the PCB pad terminals (refer to 'PE_B' in <FIG>) of the PCB substrate <NUM> without interposing another layer or configuration. This direct coupling (e.g., direct connecting) may be accomplished through ultrasonic bonding. Ultrasonic bonding will be described in more detail with reference to <FIG> after describing the structure of the PCB substrate <NUM> and the structure of the panel pad terminal PE_P.

<FIG> is a plan view of the PCB substrate of <FIG>, and <FIG> is a cross-sectional view taken along line V-V' of <FIG>.

As shown in <FIG>, the PCB substrate <NUM> may include a base substrate <NUM> and a plurality of PCB pad terminals PE_B disposed on the base substrate <NUM>.

The base substrate <NUM> may serve to support the elements disposed on the base substrate <NUM>. The base substrate <NUM> may be a rigid substrate including a material such as glass or quartz, but the present disclosure is not limited thereto. The base substrate <NUM> may be a flexible substrate including a soft material. When the base substrate <NUM> is a flexible substrate, the base substrate <NUM> may include polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacryalte (PMMA), triacetylcellulose (TAC), or cycloolefin polymer (COP).

A PCB pad area PA_B may be disposed in one region on the base substrate <NUM>. The plurality of PCB pad terminals PE_B may be arranged in the PCB pad area PA_B. The plurality of PCB pad terminals PE_B may be arranged in a single row in one direction. The PCB pad terminals PE_B may also be arranged in a plurality of rows.

The PCB pad terminal PE_B may include a PCB conductive pattern CP_B disposed on the base substrate <NUM>, as shown in <FIG>. The PCB conductive pattern CP_B may include an integrally formed PCB conductive electrode <NUM>. The PCB conductive electrode <NUM> may be made of one of copper (Cu), tin (Sn), gold (Au), and nickel (Ni), and may be formed of a single film or a multilayer film.

Each of the PCB pad terminals PE_B of the PCB substrate <NUM> may be electrically coupled to (e.g., electrically connected to) each of the input lead terminals PE_ILB of the above-described COF film <NUM>. Each of the PCB pad terminals PE_B and each of the input lead terminals PE_ILB may be ultrasonically bonded. In some embodiments, the PCB pad terminal PE_B, similarly to the panel pad terminal PE_P, may have a surface concave-convex shape. When the PCB pad terminal PE_B has a surface concave-convex shape, the bonding reliability of the PCB substrate <NUM> and the COF film <NUM> may be increased. Contents related to this will be described later with reference to <FIG> <FIG>.

Hereinafter, the cross-sectional structures of the pixel and pad area of the display panel <NUM> will be described in more detail.

<FIG> is a cross-sectional view of a display panel according to an embodiment. <FIG> shows a cross-sectional shape of a pixel and a pad region taken along the second direction of <FIG>.

Referring to <FIG>, the display panel <NUM> includes a base substrate <NUM>, and a plurality of conductive layers, a plurality of insulating layers, and an organic light emitting layer, which are disposed on the base substrate <NUM>.

For example, the base substrate <NUM> may serve as a support for the respective layers disposed thereon. The base substrate <NUM> may be disposed over the display area DA and the non-display area NA. The base substrate <NUM> may include a polymer material having an insulating function. Examples of the polymer material may include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. The base substrate <NUM> may be a flexible substrate capable of bending, folding, rolling, or the like. An example of the material constituting the flexible substrate is polyimide (PI), but is not limited thereto. The base substrate <NUM> may be a rigid substrate made of glass, quartz or the like.

A buffer layer <NUM> may be disposed on the base substrate <NUM>. The buffer layer <NUM> may be disposed over the entire display area DA and non-display area NA. The buffer layer <NUM> may prevent or reduce the diffusion of impurity ions, may prevent or reduce the penetration of moisture or external air, and may perform a surface planarization function. The buffer layer <NUM> may cover most of the display area DA and the non-display area NA of the base substrate <NUM>. The buffer layer <NUM> may include silicon nitride, silicon oxide, or silicon oxynitride.

A semiconductor layer <NUM> may be disposed on the buffer layer <NUM>. The semiconductor layer <NUM> constitutes a channel of a thin film transistor. The semiconductor layer <NUM> is disposed in each pixel of the display area DA, and may be disposed in the non-display area NA in some cases.

The semiconductor layer <NUM> may include a source/drain region and an active region. The semiconductor layer <NUM> may include polycrystalline silicon. The polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method may include, but are not limited to, rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS). Impurity ions (p-type impurity ions in the case of a PMOS transistor) may be doped in a region (source/drain region) coupled to (e.g., connected to) the source/drain electrodes <NUM> and <NUM> of a thin film transistor TFT in the semiconductor layer <NUM>. Trivalent dopants such as boron (B) may be used as p-type impurity (ions). In another embodiment, the semiconductor layer <NUM> may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. Examples of the oxide semiconductor may include two-component compounds (ABx), three-component compounds (ABxCy), and four-component compounds (ABxCyDz), each containing at least one of zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). In an embodiment, the semiconductor layer <NUM> may include ITZO (an oxide including indium, tin, and titanium) or IGZO (an oxide including indium, gallium, and tin).

A first insulating layer <NUM> may be disposed on the semiconductor layer <NUM>. The first insulating layer <NUM> may be disposed over the entire surface of the base substrate <NUM> including the display area DA and the non-display area NA.

The first insulating layer <NUM> may be a gate insulating film having a gate insulating function.

The first insulating layer <NUM> may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. They may be used alone or in combination with two or more.

A first gate conductive layer <NUM> may be disposed on the first insulating layer <NUM>. In an embodiment, the first gate conductive layer <NUM> may include a gate electrode <NUM> of a thin film transistor TFT, a first electrode <NUM> of a storage capacitor Cst, and a first pad conductive pattern CP1. In addition, the first gate conductive layer <NUM> may further include a scanning signal line for transmitting a scanning signal to the gate electrode <NUM>.

The first pad conductive pattern CP1 may include a plurality of conductive electrodes <NUM>. The conductive electrodes <NUM> may be disposed to be spaced apart from each other in the second direction. The buffer layer <NUM> may be exposed through an area where the first pad conductive pattern CP1 is not disposed. In an embodiment, the shape of the panel pad terminal PE_P may be changed depending on whether or not the first pad conductive pattern CP1 is disposed. Contents related to this will be described in more detail with reference to <FIG>.

The gate electrode <NUM> of the thin film transistor TFT, the first electrode <NUM> of the storage capacitor Cst, and the first pad conductive pattern CP1 may be formed of the same (e.g., substantially the same) material under the same (e.g., substantially the same) process. For example, the first gate conductive layer <NUM> may include at least one selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Although it is shown in the drawings that the first gate conductive layer <NUM> is a single-layer film, in some cases, the first gate conductive layer <NUM> may be a multi-layer film. In this case, the multi-layer film of the first gate conductive layer <NUM> may be formed of a laminate film of different metals among the above-described metals.

A second insulating layer <NUM> may be disposed on the first gate conductive layer <NUM>. The second insulating layer <NUM> may be disposed over the entire surface of the base substrate <NUM> including the display area DA and the non-display area NA. The second insulating layer <NUM> may isolate the first gate conductive layer <NUM> from the second gate conductive layer <NUM>. The second insulating layer <NUM> may be an interlayer insulating film.

The second insulating layer <NUM> may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. The second insulating layer <NUM> made of an inorganic insulating material may conformally reflect a lower step.

A second gate conductive layer <NUM> may be disposed on the second insulating layer <NUM>. The second gate conductive layer <NUM> may include a second electrode <NUM> of the storage capacitor Cst. The second electrode <NUM> of the storage capacitor Cst may overlap the first electrode <NUM> with the second insulating layer <NUM> interposed therebetween. For example, the first electrode <NUM> and the second electrode <NUM> may constitute the storage capacitor Cst having the second insulating layer <NUM> as a dielectric film.

The second gate conductive layer <NUM> may include at least one selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). In an embodiment, the second gate conductive layer <NUM> may be made of the same (e.g., substantially the same) material as the above-described first gate conductive layer <NUM>. Although it is shown in the drawings that the second gate conductive layer <NUM> is a single-layer film, in some cases, the second gate conductive layer <NUM> may be a multi-layer film.

A third insulating layer <NUM> is disposed on the second gate conductive layer <NUM>. The third insulating layer <NUM> may isolate the second gate conductive layer <NUM> from a first source/drain conductive layer <NUM>.

Meanwhile, although it is exemplified in the present embodiment that the second insulating layer <NUM> is disposed on the first pad conductive pattern CP1 in the panel pad area PA_P and the third insulating layer <NUM> is not disposed in the panel pad area PA_P, the present disclosure is not limited thereto. For example, the third insulating layer <NUM> is disposed over the entire surface of the display area DA and the non-display area NA including the panel pad area PA_P, and may be disposed on the second insulating layer <NUM> and the first pad conductive pattern CP1. In this case, the second insulating layer <NUM> may be omitted in the non-display area NA, and the third insulating layer <NUM> may be disposed directly on the first pad conductive pattern CP1.

The third insulating layer <NUM> may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

A first source/drain conductive layer <NUM> may be disposed on the third insulating layer <NUM>. In an embodiment, the first source/drain conductive layer <NUM> may include a source electrode <NUM>, a drain electrode <NUM> and a power supply voltage electrode <NUM> of a thin film transistor (TFT), and a second pad conductive pattern CP2. The source electrode <NUM> and drain electrode <NUM> of the thin film transistor (TFT) may be electrically coupled to (e.g., electrically connected to) the source region and drain region of the semiconductor layer <NUM> through a contact hole penetrating the third insulating layer <NUM>, the second insulating layer <NUM>, and the first insulating layer <NUM>, respectively.

The second pad conductive pattern CP2 may be disposed on the second insulating layer <NUM> of the panel pad area PA_P. The second pad conductive pattern CP2 may conformally reflect a lower step. For example, the second pad conductive pattern CP2 may include an area overlapping the first pad conductive pattern CP1 having a step to include surface unevenness, and an area not overlapping this first pad conductive pattern CP1, and in this case, the second pad conductive pattern CP2 may conformally reflect the step of the first pad conductive pattern CP1, and thus, the area overlapping the first pad conductive pattern CP1 may protrude in a thickness direction by the thickness of the first pad conductive pattern CP1 as compared with the area where first pad conductive pattern CP1 is not disposed. Accordingly, the upper surface of the second pad conductive pattern CP2 in the panel pad terminal PE_P may include a concave portion and a convex portion.

A first via layer <NUM> and the like are laminated on the first source/drain conductive layer <NUM>. In an embodiment, the layers on the first source/drain conductive layer <NUM> are not disposed in the panel pad area PA_P of the non-display area DA and thus, may expose the second pad conductive pattern CP2. Each of the output lead terminals PE_OLB of the COF film <NUM> may be coupled to (e.g., connected to) the upper surface of the exposed first pad conductive pattern CP1.

The first source/drain conductive layer <NUM> may include at least one selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first source/drain conductive layer <NUM> may be a single film as shown in the drawing. However, the present disclosure is not limited thereto, and the first source/drain conductive layer <NUM> may be a multi-layer film. For example, the first source/drain conductive layer <NUM> may have a laminate structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, or Ti/Cu.

The first via layer <NUM> may be disposed on the first source/drain conductive layer <NUM>. The first via layer <NUM> may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

A second source/drain conductive layer <NUM> may be disposed on the first via layer <NUM>. The second source/drain conductive layer <NUM> may include a data signal line <NUM>, a connection electrode <NUM>, and a power supply voltage line <NUM>. The data signal line <NUM> may be electrically coupled to (e.g., electrically connected to) the source electrode <NUM> of the thin film transistor TFT through a first contact hole penetrating the first via layer <NUM>. The connection electrode <NUM> may be electrically coupled to (e.g., electrically connected to) the drain electrode <NUM> of the thin film transistor TFT through a second contact hole penetrating the first via layer <NUM>. The power supply voltage line <NUM> may be electrically coupled to (e.g., electrically connected to) the power supply voltage electrode <NUM> through a third contact hole penetrating the first via hole <NUM>.

In an embodiment, it is exemplified that the second source/drain conductive layer <NUM> is not disposed in the panel pad area PA_P of the non-display area NA. However, in some embodiments, the second source/drain conductive layer <NUM> may be disposed in the panel pad area PA_P of the non-display area NA. Contents related to this will be described later.

The second source/drain conductive layer <NUM> may include at least one selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second source/drain conductive layer <NUM> may be a single film. However, the present disclosure is not limited thereto, and the second source/drain conductive layer <NUM> may be a multi-layer film. For example, the second source/drain conductive layer <NUM> may have a laminate structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, or Ti/Cu.

A second via layer <NUM> may be disposed on the second source/drain conductive layer <NUM>. The second via layer <NUM> may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

An anode electrode ANO is disposed on the second via layer <NUM>. The anode electrode ANO may be coupled to (e.g., connected to) the connection electrode <NUM> through a contact hole penetrating the second via layer <NUM>, and may be electrically coupled to (e.g., electrically connected to) the drain electrode <NUM> of the thin film transistor (TFT) through the second contact hole.

A pixel defining layer <NUM> may be disposed on the anode electrode ANO. The pixel defining layer <NUM> may include an opening exposing the anode electrode ANO. The pixel defining layer <NUM> may be made of an organic insulating material or an inorganic insulating material. In an embodiment, the pixel defining layer <NUM> may include a material such as a photoresist, a polyimide resin, an acrylic resin, a silicon compound, or a polyacrylic resin.

An organic layer EL may be disposed on the upper surface of the anode electrode ANO and in the opening of the pixel defining layer <NUM>. Although it is shown in the drawing that the organic layer EL is disposed only in the opening of the pixel defining layer <NUM>, the present disclosure is not limited thereto, and the organic layer EL may be disposed to extend from the opening of the pixel defining layer <NUM> to the upper surface of the pixel defining layer <NUM>.

The organic layer EL may include an organic light emitting layer EL1, a hole injection/transporting layer EL2, and an electron injection/transporting layer EL3. Although it is illustrated in the drawing that each of the hole injection/transporting layer EL2 and the electron injection/transporting layer EL3 is a single layer, each of the hole injection/transporting layer EL2 and the electron injection/transporting layer EL3 may be a laminate of a plurality of layers. Further, at least one of the hole injection/transporting layer EL2 and the electron injection/transporting layer EL3 may be a common layer disposed over a plurality of pixels.

A cathode electrode CAT is disposed on the organic EL layer and the pixel defining layer <NUM>. The cathode electrode CAT may be a common electrode disposed over a plurality of pixels.

A thin film encapsulating layer <NUM> is disposed on the organic layer EL. The thin film encapsulating layer <NUM> may cover an organic light emitting element OLED. The thin film encapsulating layer <NUM> may be a laminate film where inorganic films and organic films are alternately laminated. For example, the thin film encapsulating layer <NUM> may include a first inorganic film <NUM>, an organic film <NUM>, and a second inorganic film <NUM>, which are sequentially laminated.

Hereinafter, a structure of one panel pad terminal PE_P of the panel pad area PA_P according to an embodiment will be described in more detail.

<FIG> is an enlarged plan view of one panel pad terminal of <FIG>, and <FIG> is a cross-sectional view taken along lines VIII-VIII' and IX-IX' of <FIG>.

As described above, the first pad conductive pattern CP1 may be disposed on the buffer layer <NUM>. The first pad conductive pattern CP1 may include a plurality of conductive electrodes <NUM> disposed to be spaced apart from each other in the second direction DR2. The plurality of conductive electrodes <NUM> disposed to be spaced apart from each other in the second direction DR2 may be formed by floating on the buffer layer <NUM> without being coupled to (e.g., connected to) the display area DA of the display panel <NUM> through wirings.

The buffer layer <NUM> may be exposed through an area where the first pad conductive pattern CP1 is not disposed. One panel pad terminal PE_P may include an area where the first pad conductive pattern CP1 is disposed and an area where the first pad conductive pattern CP1 is not disposed. The area where the first pad conductive pattern CP1 is disposed may protrude by the thickness of the first pad conductive pattern CP1 as compared with the area where first pad conductive pattern CP1 is not disposed, so as to form a convex portion. Conversely, the area where the first pad conductive pattern CP1 is not disposed may recessed by the thickness of the first pad conductive pattern CP1 as compared with the convex portion, so as to form a concave portion. For example, the first pad conductive pattern CP1 may have a surface concave-convex shape in which steps are repeatedly arranged.

The second insulating layer <NUM> may be integrally formed and disposed on the first pad conductive pattern CP1 and/or the exposed upper surface of the first pad conductive pattern CP1. The second insulating layer <NUM> may cover the first pad conductive pattern CP1. The second insulating layer <NUM> may have a uniform (e.g., substantially uniform) thickness over the first pad conductive pattern CP1 and/or over the exposed upper surface of the first pad conductive pattern CP1. However, the present disclosure is not limited thereto, and the thickness of the second insulating layer <NUM> disposed in the area where the first pad conductive pattern CP1 is not disposed may be greater than the thickness of the second insulating layer <NUM> disposed in the area where the first pad conductive pattern CP1 is disposed. The second insulating layer <NUM> may be larger in size than the first pad conductive pattern CP1 and the second pad conductive pattern CP2. For example, the second insulating layer <NUM> may extend outward from the first pad conductive pattern CP1 and the second pad conductive pattern CP2.

As described above, since the second insulating layer <NUM> is formed of an inorganic insulating material and conformally reflects a lower step, the surface of the second insulating layer <NUM> may have a concavo-convex shape by reflecting a surface step according to the presence or absence of the first pad conductive pattern CP1.

The second pad conductive pattern CP2 may be disposed on the second insulating layer <NUM>. The second pad conductive pattern CP2 may include a region bonded to each of the output lead terminals PE_OLB of the above-described COF film <NUM>. The second pad conductive pattern CP2, unlike the first pad conductive pattern CP1, may be brought into electrical contact with the display area DA of the display panel <NUM>.

The second pad conductive pattern CP2 may be integrally formed. The second pad conductive pattern CP2 may cover an area where the first pad conductive pattern CP1 is disposed. For example, the second pad conductive pattern CP2 may cover all fragments of first pad conductive patterns CP1 on the first pad conductive pattern CP1.

The second pad conductive pattern CP2 may have a set (e.g., predetermined) concavo-convex shape. As described above, since the second pad conductive pattern CP2 is formed of a conductive material and conformally reflects a lower step, the surface of the second pad conductive pattern CP2 may have various suitable concavo-convex shapes by reflecting a surface step according to the presence or absence of the first pad conductive pattern CP1.

In some embodiments, the upper surface of the second pad conductive pattern CP2 in the area where the first pad conductive pattern CP1 is disposed has a step corresponding to the thickness of the first pad conductive electrode <NUM> as compared with the area where the first pad conductive pattern CP1 is not disposed. For example, the area where the first pad conductive pattern CP1 is disposed in the second pad conductive pattern CP2 protrudes by the thickness of the first pad conductive pattern CP1 as compared with the area where the first pad conductive pattern CP1 is not disposed, so as to form a convex portion. Further, the area where the first pad conductive pattern CP1 is not disposed is recessed by the thickness of the first pad conductive pattern CP1 as compared with the convex portion, so as to form a concave portion.

However, due to the structure where the first pad conductive pattern CP1, the second insulating layer <NUM>, and the second pad conductive pattern CP2 are sequentially laminated, the difference in thickness between the convex portion and the concave portion of the second pad conductive pattern CP2 may be smaller than the difference in thickness between the convex portion and the concave portion of the second insulating layer <NUM> and the thickness of the first pad conductive pattern CP1. Moreover, the difference in thickness between the convex portion and the concave portion of the second insulating layer <NUM> may be smaller than the thickness of the first pad conductive pattern CP1.

Further, in the structure where the first pad conductive pattern CP1, the second insulating layer <NUM>, and the second pad conductive pattern CP2 are sequentially laminated, the width of the convex portion of the second pad conductive pattern CP2 may be greater than the width of the first pad conductive pattern CP1 and the width of the convex portion of the second insulating layer <NUM> along the second direction DR2. Moreover, the width of the convex portion of the second insulating layer <NUM> may be greater than the width of the first pad conductive pattern CP1 along the second direction DR2.

Unlike this, the width of the concave portion of the second conductive pattern CP2 may be smaller than the width of the concave portion of the second insulating layer <NUM> in the second direction DR2, and the width of the concave portion of the second insulating layer <NUM> may be smaller than the distance between two adjacent first conductive patterns CP1 in the second direction DR2.

Hereinafter, an ultrasonic bonding process of the panel pad terminal PE_P and the lead terminal of the COF film <NUM> and an effect due to the concave-convex structure of the panel pad terminal PE_P according to an embodiment will be described.

<FIG> are cross-sectional views illustrating the bonding steps of the panel pad terminal and the output lead terminal of <FIG>.

Referring to <FIG>, when the output lead terminal PE_OLB of the COF film <NUM> is placed on the panel pad terminal PE_P of the display panel <NUM> and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, a frictional force is generated at the interface to cause partial melting, and concurrently (e.g., simultaneously), the respective components may be diffused toward each other. For example, the components included in the output lead terminal PE_OLB of the COF film <NUM> may be partially diffused into the panel pad terminal PE_P, and the components included in the panel pad terminal PE_P may be partially diffused into the output lead terminal PE_OLB of the COF film <NUM>. As a result, the panel pad terminal PE_P may have an area where the components included in the output lead terminal PE_OLB of the COF film <NUM> are diffused, and the output lead terminal PE_OLB of the COF film <NUM> may have an area where the components included in the panel pad terminal PE_P are diffused.

As shown in <FIG>, in an area 144b where the components of the output lead terminal PE_OLB of the panel pad terminal PE_P are the output lead terminal PE_OLB and the panel pad terminal PE_P may be directly coupled to (e.g., directly connected to) each other while being in contact with each other. The interface between the directly coupled (e.g., directly connected) output lead terminal PE_OLB and panel pad terminal PE_P may have a non-flat shape through melting and solidification. Further, with the mutual diffusion of the components, alloys of different materials from each other may be formed at the interface.

However, when the output lead terminal PE_OLB of the COF film <NUM> is placed on the panel pad terminal PE_P of the display panel <NUM> and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if an insufficient or unsuitable frictional force is generated between the panel pad terminal PE_P and the output lead terminal PE_OLB, the bonding reliability between the display panel <NUM> and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the display panel <NUM> and the COF film <NUM> may be improved. For example, as described in the present embodiment, when the surface of the panel pad terminal PE_P includes concave and convex portions, stress applied to the interface between the panel pad terminal PE_P and the output lead terminal PE_OLB, for example, stress applied to the convex portion of the panel pad terminal PE_P, increases, and thus, the panel pad terminal PE_P and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

Meanwhile, in the above embodiment, although it is exemplified that the panel pad terminal PE_P includes a first pad conductive pattern CP1 made of a first gate conductive layer <NUM> and a second pad conductive pattern CP2 made of a first source/drain conductive layer <NUM>, the present disclosure is not limited thereto.

For example, the first pad conductive pattern CP1 may be formed of the first gate conductive layer <NUM>, the second pad conductive pattern CP2 may be formed of the second gate conductive layer <NUM>, and the second insulating layer <NUM> may be disposed between the first pad conductive pattern CP1 and the second pad conductive pattern CP2.

As another example, the first pad conductive pattern CP1 may be formed of the first gate conductive layer <NUM>, the second pad conductive pattern CP2 may be formed of a second source/drain conductive layer <NUM>, and the second insulating layer <NUM> and/or the third insulating layer <NUM> may be disposed between the first pad conductive pattern CP1 and the second pad conductive pattern CP2.

As another example, the first pad conductive pattern CP1 may be formed of the first gate conductive layer <NUM>, the second pad conductive pattern CP2 may be formed of a laminate structure of the second gate conductive layer <NUM> and the first source/drain electrode layer <NUM>, and the second insulating layer <NUM> may be disposed therebetween. In this case, the third insulating layer <NUM> may be further disposed between the second gate conductive layer <NUM> and the first source/drain electrode layer <NUM>, but the present disclosure is not limited thereto.

As another example, the first pad conductive pattern CP1 may be formed of the first gate conductive layer <NUM>, the second pad conductive pattern CP2 may be formed of a laminate structure of the second gate conductive layer <NUM> and the second source/drain electrode layer <NUM>, and the second insulating layer <NUM> may be disposed therebetween. In this case, the third insulating layer <NUM> may be further disposed between the second gate conductive layer <NUM> and the first source/drain electrode layer <NUM>, but the present disclosure is not limited thereto.

As another example, the first pad conductive pattern CP1 may be formed of the first gate conductive layer <NUM>, the second pad conductive pattern CP2 may be formed of a laminate structure of the first source/drain electrode layer <NUM> and the second source/drain electrode layer <NUM>, and the second insulating layer <NUM> and/or the third insulating layer <NUM> may be disposed between the first pad conductive pattern CP1 and the second pad conductive pattern CP2. In this case, the second pad conductive pattern CP2 may further include the second gate conductive layer <NUM> between the first source/drain electrode layers <NUM>, but the present disclosure is not limited thereto.

As another example, the first pad conductive pattern CP1 may be formed of the second gate conductive layer <NUM>, and the above-described various suitable modifications of the second pad conductive pattern CP2 may be applied.

The panel pad terminal PE_P may be formed of a combination of various other suitable conductive layers.

Hereinafter, other embodiments will be described. In the following embodiments, the same features as those in the previously described embodiments are referred to with the same reference numerals, and a redundant description thereof will not be repeated here or will be simplified.

<FIG> is a cross-sectional view of a panel pad terminal according to another embodiment.

Referring to <FIG>, a panel pad terminal PE_Pa according to another embodiment is different from the embodiment of <FIG> in that the panel pad terminal PE_Pa further includes a contact hole CNT through which a second insulating layer 112a electrically couples (e.g., electrically connects) the first pad conductive pattern CP1 and the second pad conductive pattern CP2.

In some embodiments, a second insulating layer 112_1 may include an area exposed on the first pad conductive pattern CP1. The exposed area may be a contact hole CNT through which the first pad conductive pattern CP1 and the second pad conductive pattern CP2 are electrically coupled to (e.g., electrically connected to) each other. Although the contact hole CNT may be smaller than the width of the upper surface of the first pad conductive pattern CP1, the present disclosure is not limited thereto, and the contact hole CNT may be equal to or larger than the width of the upper surface of the first pad conductive pattern CP1.

Even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on a panel pad terminal PE_Pa and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if sufficient or suitable frictional force is not generated between the panel pad terminal PE_Pa and the output lead terminal PE_OLB, the bonding reliability between a display panel 100and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the panel pad terminal PE_Pa and the output lead terminal PE_OLB may be improved. For example, as described in the present embodiment, when the surface of the panel pad terminal PE_Pa includes concave and convex portion, stress applied to the interface between the panel pad terminal PE_Pa and the output lead terminal PE_OLB, for example, stress applied to the convex portion of the panel pad terminal PE_Pa, increases to increase a frictional force at the convex portion, and thus, the panel pad terminal PE_Pa and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

<FIG> are a plan view and a cross-sectional view, respectively, of a panel pad terminal according to another embodiment.

Referring to <FIG>, the panel pad terminal PE_P_1 according to the present embodiment is different from the embodiment of <FIG> in that a first pad conductive pattern CP1_1 includes conductive electrodes 123_1 separated from each other in the first direction DR1 and the second direction DR2, respectively.

In some embodiments, in the panel pad terminal PE_P_1 according to the present embodiment, the first pad conductive pattern CP1_1 includes conductive electrodes 123_1 separated from each other in the first direction DR1 and the second direction DR2, respectively.

Even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on the panel pad terminal PE_P_1 and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if sufficient or suitable frictional force is not generated between the panel pad terminal PE_P_1 and the output lead terminal PE_OLB, the bonding reliability between the display panel 100_1 and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the panel pad terminal PE_P_1 and the output lead terminal PE_OLB may be improved. For example, as described in the present embodiment, when the surface of the panel pad terminal PE_P_1 includes concave and convex portions, stress applied to the interface between the panel pad terminal PE_P_1 and the output lead terminal PE_OLB, for example, stress applied to the convex portion of the panel pad terminal PE_P_1, increases to increase a frictional force at the convex portion, and thus, the panel pad terminal PE_P_1 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

<FIG> are a plan view and a cross-sectional view, respectively, of a panel pad terminal according to still another embodiment.

Referring to <FIG>, a panel pad terminal PE_P_2 according to still another embodiment is configured such that a first pad conductive pattern CP1_2 includes conductive electrodes 123_2 that may extend substantially in the first direction DR1 and may extend in oblique directions, for example, upper and lower diagonal directions of the first direction DR1 and the second direction DR2. When the first pad conductive pattern CP1_2 extends in such an extending direction, a shape swinging in different directions of the second direction DR2 while extending in the first direction DR1 as a whole may be formed. The swinging shape may also be referred to as a zigzag shape.

In some embodiments, the panel pad terminal PE_P_2 according to the present embodiment receives greater stress from the area protruding in the second direction DR2 and the area recessed in the second direction DR2 at the time of bonding the panel pad terminal PE_P_2 to the output lead terminal PE_OLB of the COF film <NUM> vibrating in the second direction DR2 by ultrasonic vibration, and thus, sufficient or suitable frictional force to reach the melting point may be generated.

Even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on the panel pad terminal PE_P_2 and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if sufficient or suitable frictional force is not generated between the panel pad terminal PE_P_2 and the output lead terminal PE_OLB, the bonding reliability between a display panel 100_2 and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the panel pad terminal PE_P_2 and the output lead terminal PE_OLB may be improved. For example, as described in the present embodiment, when the surface of the panel pad terminal PE_P_2 includes concave and convex portions, stress applied to the interface between the panel pad terminal PE_P_2 and the output lead terminal PE_OLB, for example, stress applied to the convex portion of the panel pad terminal PE_P_2, increases to increase a frictional force at the convex portion, and thus, the panel pad terminal PE_P_2 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

Referring to <FIG>, a panel pad terminal PE_P_3 according to the present embodiment is different from the embodiment of <FIG> in that a first pad conductive pattern CP1_3 is configured to allow the protruding areas and recessed areas in the first direction DR1 to be repeated.

A panel pad terminal PE_P_3 according to still another embodiment is configured such that a first pad conductive pattern CP1_3 may extend substantially in the first direction DR1 and may extend in oblique directions, for example, left and right diagonal directions of the first direction DR1 and the second direction DR2. When the first pad conductive pattern CP1_3 extends in such an extending direction, a shape swinging in different directions of the first direction DR1 while extending in the second direction DR2 as a whole may be formed. The swinging shape may be referred to as a zigzag shape.

In some embodiments, the panel pad terminal PE_P_3 according to the present embodiment may be bonded to the output lead terminal PE_OLB of the COF film <NUM> vibrating in the second direction DR2 by ultrasonic vibration. In this case, the panel pad terminal PE_P_3 has the first pad conductive pattern CP1_3 extending in the second direction, thereby enlarging the bonding area with the output lead terminal PE_OLB. Moreover, the panel pad terminal PE_P_3 receives greater stress from the area protruding in the second direction DR2 and the area recessed in the second direction DR2, and thus, sufficient or suitable frictional force to reach the melting point may be generated.

Thus, the panel pad terminal PE_P_3 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween and the bonding reliability of the COF film <NUM> may be improved.

<FIG> are plan views, and <FIG> are cross-sectional views, of a PCB pad terminal of a PCB substrate to which substantially the same structure as modification examples of the panel pad terminal is applied.

Referring to <FIG> and <FIG>, a PCB pad terminal PE_B according to other embodiments is different from the embodiment of <FIG> in that the PCB pad terminal PE_B includes a concave-convex structure including various suitable modifications.

In some embodiments, when an input lead terminal PE_ILB of the COF film <NUM> is placed on a PCB pad terminal PE_B of a PCB substrate <NUM> and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, a frictional force is generated at the interface to cause partial melting, and concurrently (e.g., simultaneously), the respective components may be diffused toward each other. For example, the components included in the input lead terminal PE_ILB of the COF film <NUM> may be partially diffused into the PCB pad terminal PE_B, and the components included in the PCB pad terminal PE_B may be partially diffused into the input lead terminal PE_ILB of the COF film <NUM>. As a result, the PCB pad terminal PE_B may have an area where the components included in the input lead terminal PE_ILB of the COF film <NUM> are diffused, and the input lead terminal PE_ILB of the COF film <NUM> may have an area where the components included in the PCB pad terminal PE_B are diffused.

In an area where the components of the input lead terminal PE_ILB of the PCB pad terminal PE_B are diffused and an area where the components of the PCB pad terminal PE_B of the input lead terminal PE_ILB are diffused, the input lead terminal PE_ILB and the PCB pad terminal PE_B may be directly coupled to (e.g., directly connected to) each other while being in contact with each other. The interface between the directly coupled (e.g., the directly connected) input lead terminal PE_ILB and PCB pad terminal PE_B may have a non-flat shape through melting and solidification. Further, with the mutual diffusion of the components, alloys of different materials from each other may be formed at the interface.

However, when the input lead terminal PE_ILB of the COF film <NUM> is placed on the PCB pad terminal PE_B and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if an insufficient or unsuitable frictional force is generated between the PCB pad terminal PE_B and the input lead terminal PE_ILB, the bonding reliability between the PCB substrate <NUM> and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the PCB pad terminal PE_B and the input lead terminal PE_ILB may be improved. For example, as described in the present embodiment, when the surface of the PCB pad terminal PE_B includes concave and convex portions, stress applied to the interface between the PCB pad terminal PE_B and the input lead terminal PE_ILB, for example, stress applied to the convex portion of the PCB pad terminal PE_B, increases to increase a frictional force at the convex portion, and thus, the PCB pad terminal PE_B and the input lead terminal PE_ILB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

<FIG> is a cross-sectional view of a display panel according to another embodiment.

Referring to <FIG>, a display panel 100_4 according to another embodiment is different from the embodiment of <FIG> in that the display panel 100_4 further includes a third pad conductive pattern CP3 on the second insulating layer <NUM>.

In some embodiments, the display panel 100_4 according to the present embodiment may further include a third pad conductive pattern CP3 on the second insulating layer <NUM>. The third pad conductive pattern CP3 may be formed of the second gate conductive layer <NUM>. The third pad conductive pattern CP3 may include a conductive electrode <NUM>. Although it is shown in the drawing that the conductive electrode <NUM> of the third pad conductive pattern CP3 is disposed to be separated in the second direction, the present disclosure is not limited thereto and the third pad conductive pattern CP3 may be integrally formed on the second insulating layer <NUM>. Further, although it is exemplified in the present embodiment that the second insulating layer <NUM> is disposed between the first pad conductive pattern CP1 and the third pad conductive pattern CP3, the present disclosure is not limited thereto, and the second insulating layer <NUM> may be omitted.

The second pad conductive pattern CP2 may have a set (e.g., predetermined) concavo-convex shape. For example, in an area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are disposed, the upper surface of the second pad conductive pattern CP2 has a step corresponding to the thickness of the first pad conductive electrode <NUM> and the third pad conductive electrode <NUM> as compared with an area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are not disposed. For example, the area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are disposed in the second pad conductive pattern CP2 is recessed by the thickness of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 as compared with the area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are not disposed, so as to form a concave portion. Therefore, the second pad conductive pattern CP2 may have a set (e.g., predetermined) concavo-convex shape due to the shapes of the first pad conductive pattern CP1 and the third pad conductive pattern CP3. Moreover, since the concave portions and convex portions of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are repeatedly arranged alternately in one direction, the second pad conductive pattern CP2 may have repetitive concave-convex structures.

Even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on a panel pad terminal PE_P_4 and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, if sufficient or suitable frictional force is not generated between the panel pad terminal PE_P_4 and the output lead terminal PE_OLB, the bonding reliability between a display panel 100_4 and the COF film <NUM> may be deteriorated.

However, according to the present embodiment, the bonding reliability between the panel pad terminal PE_P_4 and the output lead terminal PE_OLB may be improved. For example, as described in the present embodiment, when the surface of the panel pad terminal PE_P_4 includes concave and convex portions, stress applied to the interface between the panel pad terminal PE_P_4 and the output lead terminal PE_OLB, for example, stress applied to the convex portion of the panel pad terminal PE_P_4, increases to increase the frictional force at the convex portion, and thus, the panel pad terminal PE_P_4 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

<FIG> is a cross-sectional view of a display panel according to still another embodiment.

Referring to <FIG>, a display panel 100_5 according to still another embodiment is different from the embodiment of <FIG> in that the display panel 100_5 further includes a fourth pad conductive pattern CP4 on the second pad conductive pattern CP2.

In some embodiments, the fourth pad conductive pattern CP4 may be integrally formed on the second pad conductive pattern CP2. Further, the fourth pad conductive pattern CP4 may be formed of the second source/drain conductive layer <NUM>.

The fourth pad conductive pattern CP4 may have a set (e.g., predetermined) concavo-convex shape. For example, in an area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are disposed, the upper surface of the fourth pad conductive pattern CP4 has a step corresponding to the thickness of the first pad conductive electrode <NUM> and the third pad conductive electrode <NUM> as compared with an area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are not disposed. In some embodiments, the area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are disposed in the fourth pad conductive pattern CP4 protrudes by the thickness of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 as compared with the area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are not disposed, so as to form a convex portion. Further, the area where the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are not disposed is recessed by the thickness of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 as compared with the convex portion, so as to form a concave portion. Therefore, the fourth pad conductive pattern CP4 may have a set (e.g., predetermined) concavo-convex shape due to the shapes of the first pad conductive pattern CP1 and the third pad conductive pattern CP3. Moreover, since the concave portions and convex portions of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 are repeatedly arranged alternately in one direction, the fourth pad conductive pattern CP4 may have repetitive concave-convex structures.

Therefore, even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on a panel pad terminal PE_P_5 and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, the panel pad terminal PE_P_5 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

Referring to <FIG>, a display panel 100_6 according to still another embodiment is different from the embodiment of <FIG> in that the second pad conductive pattern CP2 includes a plurality of conductive electrodes 144_1 spaced apart from each other in the second direction.

In some embodiments, in the display panel 100_6 according to the present embodiment, the second pad conductive pattern CP2 may include a plurality of conductive electrodes 144_1 spaced apart from each other in the second direction.

Even in the present embodiment, the fourth pad conductive pattern CP4 may have a set (e.g., predetermined) concavo-convex shape. For example, in an area where the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are disposed, the upper surface of the fourth pad conductive pattern CP4 has a step corresponding to the thickness of the first pad conductive electrode <NUM>, third pad conductive electrode <NUM> and second pad conductive electrode 144_1 as compared with an area where the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are not disposed. For example, the area where the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are disposed in the fourth pad conductive pattern CP4 protrudes by the thickness of the first pad conductive pattern CP1 to the third pad conductive pattern CP3 as compared with the area where the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are not disposed, so as to form a convex portion. Further, the area where the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are not disposed is recessed by the thickness of the first pad conductive pattern CP1 and the third pad conductive pattern CP3 as compared with the convex portion, so as to form a concave portion. Therefore, the fourth pad conductive pattern CP4 may have a set (e.g., predetermined) concavo-convex shape due to the shapes of the first pad conductive pattern CP1 to the third pad conductive pattern CP3. Moreover, since the concave portions and convex portions of the first pad conductive pattern CP1 to the third pad conductive pattern CP3 are repeatedly arranged alternately in one direction, the second pad conductive pattern CP4 may have repetitive concave-convex structures.

Even in the present embodiment, when the output lead terminal PE_OLB of the COF film <NUM> is placed on a panel pad terminal PE_P_4 and ultrasonic processing is performed under a constant (e.g., substantially constant) pressure, the panel pad terminal PE_P_4 and the output lead terminal PE_OLB are well melted to easily perform the connection therebetween. Therefore, the bonding reliability of the COF film <NUM> may be improved.

As described above, according to embodiments of the present disclosure, it is possible to provide a display device having high bonding reliability.

Claim 1:
A display device (<NUM>) comprising:
a display area (DA);
a non-display area (NA) around the display area (DA);
a substrate (<NUM>); and
a first connection terminal (PE_P, PE_P_1, PE_P_2, PE_P_3, PE_P_4) in the non-display area (NA) on the substrate (<NUM>),
wherein the first connection terminal (PE_P, PE_P_1, PE_P_2, PE_P_3, PE_P_4) comprises:
a plurality of first conductive patterns (CP1, CP1_1, CP1_2, CP1_3) spaced apart from each other,
a first insulating layer (<NUM>) covering each of the plurality of first conductive patterns (CP1, CP1_1, CP1_2, CP1_3), and conformally provided on the plurality of first conductive patterns and the substrate; and
a second conductive pattern (CP2) conformally provided on the first insulating layer (<NUM>),
wherein
the second conductive pattern (CP2) completely covers the plurality of first conductive patterns (CP1, CP1_1, CP1_2, CP1_3) and comprises concave and convex portions on a surface thereof, wherein the convex and concave portions are as seen from above,
wherein the convex portion of the surface of the second conductive pattern (CP2) completely overlaps each of the first conductive patterns (CP1, CP1_1, CP1_2, CP1_3), and the concave portion of the surface of the second conductive pattern (CP2) overlaps an area where each of the first conductive patterns (CP1, CP1_1, CP1_2, CP1_3) is not disposed and does not overlap any of the first conductive patterns (CP1, CP1_1, CP1_2, CP1_3).