Patent Description:
Over the past few decades, the size of transistors has been continuously scaled down in order to increase performance and reduce power consumption, leading to better electronic devices that are able to do more useful, important, and valuable things faster, more clearly, and more efficiently.

Semiconductor-on-insulator (SOI) technology is an attractive candidate to push forward the frontiers imposed by Moore's law. Fully depleted SOI (FDSOI) techniques in particular may provide promising technologies that allow the fabrication of semiconductor devices at technology nodes of <NUM> and beyond. Aside from FDSOI techniques allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, the fabrication processes employed in FDSOI techniques are comparatively simple and actually represent a low-risk evolution of conventional planar bulk CMOS techniques.

<CIT> Aldescribes a transistor having various levels of threshold voltages. <CIT> describes a semiconductor structure including a transistor over a ground plane over an N-doped well, with STI regions on the side of the transistor structure, the STI regions separating landing areas for terminals formed in the well. Further prior art is described in <CIT>.

Semiconductor structures are provided for a fully depleted silicon-on-insulator (FDSOI) transistor. An embodiment of a semiconductor structure is provided. The semiconductor structure comprises a semiconductor substrate; a floating N-type well region (<NUM>) over the semiconductor substrate (<NUM>); an undoped layer (125a, 125b) over the semiconductor substrate (<NUM>) and in contact with the N-type well region (<NUM>) wherein the undoped layer (125a, 125b) is not doped with impurities or is a light doping P-well region; a fully depleted silicon-on-insulator, FDSOI, transistor (<NUM>) formed over the N-type well region (<NUM>), comprising: a buried oxide layer (<NUM>) over the N-type well region (<NUM>); a source region (220b) over the buried oxide layer (<NUM>); a drain region (220a) over the buried oxide layer (<NUM>); a silicon-on-insulator, SOI, layer (<NUM>) over the buried oxide layer (<NUM>) and between the source and drain regions (220a); and a metal gate (<NUM>) over the SOI layer (<NUM>); a first shallow trench isolation, STI, region (150b) over the undoped layer (125a, 125b); a first P-type doped region (140a) over the undoped layer (125a, 125b), wherein the first P-type doped region (140a) is separated from the drain region (220a) of the FDSOI transistor (<NUM>) by the first STI region (150b); and a first interconnection element (<NUM>10a) over the first P-type doped region (140a) and configured to connect the first P-type doped region (140a) and the undoped layer to a ground.

The embodiments described above and described herein below may be combined.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

<FIG> shows a cross-sectional view of a semiconductor structure 10A according to an example, not falling under the scope of the claimed invention. An N-type well region <NUM> is formed on a semiconductor substrate <NUM>. The semiconductor substrate <NUM> may be made of silicon or other semiconductor materials, and the semiconductor substrate <NUM> is a P-type substrate. A fully depleted silicon-on-insulator (FDSOI) transistor <NUM> is formed over the N-type well region <NUM>. A buried oxide (BOX) layer <NUM> is formed over the N-type well region <NUM>. In some embodiments, the BOX layer <NUM> may be formed of SiO2, SiN, or combination. The N-type doped regions 220a and 220b are formed over the BOX layer <NUM>. A silicon-on-insulator (SOI) layer <NUM> is formed over the BOX layer <NUM> and between the N-type doped regions 220a and 220b. A metal gate <NUM> is formed over the SOI layer <NUM>. The N-type doped regions 220a and 220b form the drain and source regions of the FDSOI transistor <NUM>, respectively. Furthermore, a channel of the FDSOI transistor <NUM> is formed between the N-type doped regions 220a and 220b and below the metal gate <NUM>. In order to simplify the description, other features of the FDSOI transistor <NUM>, such as gate dielectric layer and so on, are omitted. In some embodiments, a heavy doping N-type well region is formed between the N-type well region <NUM> and the semiconductor substrate <NUM>.

In <FIG>, the N-type doped regions 130a and 130b are formed over the N-type well region <NUM>. The N-type doped region 130a is separated from the N-type doped region 220a (i.e., the drain region of the FDSOI transistor <NUM>) by a shallow trench isolation (STI) region 150c, and the N-type doped region 130b is separated from the N-type doped region 220b (i.e., the source region of the FDSOI transistor <NUM>) by a STI region 150d. The STI regions 150c and 150d are formed over the N-type well region <NUM>. The N-type doped regions 130a and 130b are the pick-up regions for the N-type well region <NUM>. The depth D1 of the STI regions 150c and 150d is greater than the depth D2 of the N-type doped regions 130a and 130b. Furthermore, the depth D2 of the N-type doped regions 130a and 130b is greater than the depth D3 of the N-type doped regions 220a and 220b.

The STI regions 150a and 150b and the P-type doped region 140a are formed over the semiconductor substrate <NUM>. In some embodiments, a P-type well region (not shown) is formed over the semiconductor substrate <NUM>, and the STI regions 150a and 150b and the P-type doped region 140a are formed over the P-type well region on the right side of the N-type well region <NUM>. The STI region 150b is in contact with the N-type well region <NUM> and the N-type doped region 130a. The P-type doped region 140a is separated from the N-type doped region 130a by the STI region 150b, and the P-type doped region 140a is disposed between the STI regions 150a and 150b. The P-type doped region 140a has the same depth as the N-type doped region 130a, i.e., the depth D1. Similarly, the STI regions 150e and 150f and the P-type doped region 140b are formed over the semiconductor substrate <NUM>. In some embodiments, a P-type well region (not shown) is formed over the semiconductor substrate <NUM>, and the STI regions 150e and 150f and the P-type doped region 140b are formed over the P-type well region on the left side of the N-type well region <NUM>. The STI region 150e is in contact with the N-type well region <NUM> and the N-type doped region 130b. The P-type doped region 140b is separated from the N-type doped region 130b by the STI region 150e, and the P-type doped region 140b is disposed between the STI regions 150e and 150f. The P-type doped region 140b has the same depth as the N-type doped region 130b, i.e., the depth D1. The P-type doped regions 140a and 140b are the pick-up regions for the semiconductor substrate <NUM>.

In <FIG>, a plurality of interconnect layers are formed over the N-type doped regions 130a and 130b, and the P-type doped regions 140a and 140b. The contacts 310a through 310d are the interconnect elements of a first interconnect layer. For example, the contact 310a is formed on the P-type doped region 140a, the contact 310b is formed on the N-type doped region 130a, the contact 310c is formed on the N-type doped region 130b, and the contact 310d is formed on the P-type doped region 140b.

The vias 320a through 320d are the interconnect elements of a second interconnect layer over the first interconnect layer. For example, the via 320a is formed on the contact 310a, the via 320b is formed on the contact 310b, the via 320c is formed on the contact 310c, and the via 320d is formed on the contact 310d. Furthermore, the metals 330a through 330d are the interconnect elements of a third interconnect layer over the second interconnect layer. For example, the metal 330a is formed on the via 320a, the metal 330b is formed on the via 320b, the metal 330c is formed on the via 320c, and metal 330d is formed on the via 320d.

In the semiconductor structure 10A, a parasitic capacitor C1 is formed by the N-type doped region 220a, the BOX layer <NUM> and the N-type well region <NUM>. In some embodiments, the parasitic capacitor C1 is adjacent to the STI region 150c. Furthermore, the semiconductor substrate <NUM> and the N-type well region <NUM> form a PN junction to operate as a parasitic diode DD. Therefore, a parasitic path PATH1 including the parasitic capacitor C1 and the parasitic diode DD is formed between the N-type well region 220a and the P-type well region 140a. In some embodiments, the parasitic diode DD is adjacent to the STI region 150b. Similarly, a parasitic capacitor (not shown) is formed by the N-type doped region 220b, the BOX layer <NUM> and the N-type well region <NUM>. Furthermore, the semiconductor substrate <NUM> and the N-type well region <NUM> form a PN junction to operate as a parasitic diode (not shown) that is adjacent to the STI region 150e, thus another parasitic path (not shown) is formed between the N-type well region 220b and the P-type well region 310d. In order to simplify the description, only the path PATH1 is illustrated below.

In some embodiments, figure of merit (FOM) is an insertion loss for the FDSOI transistor <NUM> used as a switch. Furthermore, the FOM of the FDSOI transistor <NUM> is mainly obtained according to the following equation: <MAT> where Ron represent the on-resistance of the FDSOI transistor <NUM>, and Coff represent the parasitic capacitor of the FDSOI transistor <NUM>. In some embodiments, the parasitic capacitor of the FDSOI transistor <NUM> is dominated from the drain capacitors of the FDSOI transistor <NUM>. For the FDSOI transistor <NUM>, the drain capacitors are parasitic capacitors. In some embodiments, the drain capacitors include a drain-gate capacitor Cdg, a drain-source capacitor Cds, and a drain-bulk capacitor Cdb. The capacitance value of the drain capacitors is mainly determined by the drain-bulk capacitor Cdb.

In <FIG>, the anode of the parasitic diode DD is coupled to a ground VSS through the P-type doped region 140a, the contact 310a, the via 320a and the metal 330b. Thus, the parasitic diode DD will not be forward biased. Similarly, the P-type doped region 140b, the contact 310d, the via 320d and the metal 330d are coupled to the ground VSS. Furthermore, the N-type doped region 130a is floating, i.e., no signal or power line is connected to the metal 330b, the via 320b and the contact 310b. Similarly, the N-type doped region 130b is floating, i.e., no signal or power line is connected to the metal 330c, the via 320c and the contact 310c.

In the semiconductor structure 10A, because no signal is applied to the N-type well region <NUM> through the N-type doped regions 130a and 130b, the N-type well region <NUM> is floating. Thus, N-type doped region 130a is high impedance for the parasitic capacitor C1, and the parasitic capacitor C1 is coupled to the ground VSS through the parasitic diode DD, the P-type doped region 140a, the contact 310a, the via 320a and the metal 330a. In other words, the capacitor C1 and an equivalent capacitor of the parasitic diode DD are coupled in serial between the drain region of the FDSOI transistor <NUM> and the ground VSS. In general, capacitors coupled in series will reduce the capacitance of the capacitors coupled in series. Thus, the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> is obtained by connecting the parasitic capacitor C1 and the equivalent capacitor of the parasitic diode DD in series, and the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> has less capacitance than the parasitic capacitor C1. Therefore, the FDSOI transistor <NUM> of the semiconductor structure 10A has less FOM and less insertion loss.

<FIG> shows a cross-sectional view of a semiconductor structure 10B according to an example, not falling under the scope of the claimed invention. The configuration of the semiconductor structure 10B is similar to the semiconductor structure 10A of <FIG>, and the difference between the semiconductor structure 10A of <FIG> and the semiconductor structure 10B of <FIG> is that no interconnect elements (e.g., the contacts 310b and 310c, the vias 320b and 320c and the metals 330b and 330c of <FIG>) are formed on the N-type doped regions 130a and 130b in the semiconductor structure 10B.

<FIG> shows a cross-sectional view of a semiconductor structure 10C according to an embodiment of the invention. The configuration of the semiconductor structure 10C is similar to the semiconductor structure 10A of <FIG>, and the difference between the semiconductor structure 10A of <FIG> and the semiconductor structure 10C of <FIG> is that an undoped layer 125a/125b is formed over the semiconductor substrate <NUM> in <FIG>. Furthermore, the STI regions 150a and 150b and the P-type doped region 140a are formed over a first region of the undoped layer 125a, and the STI regions 150d and 150e and the P-type doped region 140b are formed over the a second region of undoped layer 125b. The undoped layer 125a/125b is used to provide high isolation (or high impedance) for the parasitic capacitor C1. In some embodiments, the undoped layer 125a /125b is not doped with impurities. An equivalent capacitor of the first region the undoped layer 125a is coupled to the parasitic capacitor C1. Thus, the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> has less capacitance than the parasitic capacitor C1. Therefore, the FDSOI transistor <NUM> of the semiconductor structure 10C has less FOM and less insertion loss.

In some embodiments, the undoped layer 125a/125b is a light doping P-type well region. Thus, the first region of the undoped layer 125a and the N-type well region <NUM> form a PN junction to operate as a parasitic diode DD. As described above, the capacitor C1 and an equivalent capacitor of the parasitic diode DD are coupled in serial between the drain region of the FDSOI transistor <NUM> and the ground VSS. In general, capacitors coupled in series will reduce the capacitance of the capacitors coupled in series. Thus, the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> is obtained by connecting the parasitic capacitor C1 and an equivalent capacitor of the parasitic diode DD in series, and the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> has less capacitance than the parasitic capacitor C1. Therefore, the FDSOI transistor <NUM> of the semiconductor structure 10C has less FOM and less insertion loss.

<FIG> shows a cross-sectional view of a semiconductor structure 10D according to an embodiment of the invention. The configuration of the semiconductor structure 10B is similar to the semiconductor structure 10C of <FIG>, and the difference between the semiconductor structure 10C of <FIG> and the semiconductor structure 10D of <FIG> is that no interconnect elements (e.g., the contacts 310b and 310c, the vias 320b and 320c and the metals 330b and 330c of <FIG>) are formed on the N-type doped regions 130a and 130b in the semiconductor structure 10D.

<FIG> shows a cross-sectional view of a semiconductor structure 10E according to an embodiment of the invention. The configuration of the semiconductor structure 10B is similar to the semiconductor structure 10C of <FIG>, and the difference between the semiconductor structure 10C of <FIG> and the semiconductor structure 10E of <FIG> is that no pick-up regions for the N-type well region <NUM> is present in <FIG>. Compared with the semiconductor structure 10C of <FIG>, no STI regions 150c and 150d and no N-type doped regions 130a and 130b are formed over the N-type well region <NUM>. Thus, the area of the N-type well region <NUM> is decreased in the semiconductor structure 10E, and the area of the FDSOI transistor <NUM> is also decreased. In the semiconductor structure 10E, the N-type doped region 220a (i.e., the drain region of the FDSOI transistor <NUM>) is separated from the P-type doped region 140a by a STI region 150b, and the N-type doped region 220b (i.e., the source region of the FDSOI transistor <NUM>) is separated from the P-type doped region 140b by a STI region 150e.

The undoped layer 125a/125b is formed over the semiconductor substrate <NUM>, and the N-type well region <NUM> is formed over the semiconductor substrate <NUM> and between the first region of the undoped layer 125a and the second region of the undoped layer 125b. In some embodiments, the N-type well region <NUM> is surrounded by the undoped layer 125a/125b. Furthermore, the N-type well region <NUM> is contact with the undoped layer 125a/125b. As described above, the undoped layer 125a/125b is used to provide high isolation (or high impedance) for the parasitic capacitor C1. In some embodiments, the undoped layer 125a/125b is not doped with impurities. An equivalent capacitor of the first region of the undoped layer 125a is coupled to the parasitic capacitor C1. Thus, the drain-bulk capacitor Cdb of the FDSOI transistor <NUM> has less capacitance than the parasitic capacitor C1. Therefore, the FDSOI transistor <NUM> of the semiconductor structure 10C has less FOM and less insertion loss.

In <FIG>, one side of the STI region 150b is in contact with the source region of the FDSOI transistor <NUM>, the buried oxide layer <NUM> and the N-type well region <NUM>. Furthermore, the opposite side of the STI region 150b is in contact with the P-type doped region 140a and the first region of the undoped layer 125a. Similarly, one side of the STI region 150e is in contact with the source region of the FDSOI transistor <NUM>, the buried oxide layer <NUM> and the N-type well region <NUM>, and the opposite side of the STI region 150e is in contact with the P-type doped region 140b and the second region of the undoped layer 125b.

Claim 1:
A semiconductor structure (10A-E), comprising:
a semiconductor substrate (<NUM>);
a floating N-type well region (<NUM>) over the semiconductor substrate (<NUM>);
an undoped layer (125a, 125b) over the semiconductor substrate (<NUM>) and in contact with the N-type well region (<NUM>) wherein the undoped layer (125a, 125b) is not doped with impurities or is a light doping P-well region;
a fully depleted silicon-on-insulator, FDSOI, transistor (<NUM>) formed over the N-type well region (<NUM>), comprising:
a buried oxide layer (<NUM>) over the N-type well region (<NUM>);
a source region (220b) over the buried oxide layer (<NUM>);
a drain region (220a) over the buried oxide layer (<NUM>);
a silicon-on-insulator, SOI, layer (<NUM>) over the buried oxide layer (<NUM>) and between the source and drain regions (220a); and
a metal gate (<NUM>) over the SOI layer (<NUM>);
a first shallow trench isolation, STI, region (150b) over the undoped layer (125a, 125b);
a first P-type doped region (140a) over the undoped layer (125a, 125b), wherein the first P-type doped region (140a) is separated from the drain region (220a) of the FDSOI transistor (<NUM>) by the first STI region (150b); and
a first interconnection element (310a) over the first P-type doped region (140a) and configured to connect the first P-type doped region (140a) and the undoped layer to a ground.