Patent Description:
During operation, computer programs may allocate memory to various objects in order to perform operations involved in executing the programs. When computer programs fail to de-allocate memory from objects that are no longer used, available memory reduces unnecessarily, which may have a negative impact on performance and may lead to system failures (e.g., when no additional memory is available). While programs such as managed runtime applications may use "garbage collectors" to automatically reclaim memory that is no longer being used, there remains considerable room for improvement. For example, traditional garbage collectors may have a negative impact on performance in terms of processor usage, unpredicted pauses in user interfaces, additional power consumption (e.g., reduced battery life), and so forth.

<CIT> describes a method and system that are provided for allowing a profiler to communicate with a virtual machine without regard to the specific implementation of the virtual machine. All object allocations occur in a given heap arena even when there are a plurality of arenas. The Create-System-Thread function causes thread object allocation and thread start events to be issued. An JVMPI_EVENT_ARENA_DELETE is sent when a heap arena is deleted. All objects residing in this arena are freed. This event is issued in the thread suspended mode.

The object to be solved is to enhance performance in terms of processor usage, unpredicted pauses in user interfaces and additional power consumption. The object is achieved by the present invention in the aspects of a semiconductor apparatus, a computer readable storage medium and a method having the features of the independent claims. Additional features for advantageous embodiments are provided in the dependent claims.

Turning now to <FIG>, an allocation space <NUM> (20a-20e) is shown after threads are created. In an embodiment, the allocation space <NUM> is part of a heap memory that is used to conduct dynamic memory allocation during run-time operation of a computer program that creates and terminates (e.g., destroys) threads. The heap memory may also include other memory space (not shown) such as, for example, large object space (e.g., storing relatively large primitive arrays and/or string arrays), image space (e.g., storing executable files, resource files, etc.), shared space (e.g., storing objects shared by multiple processes), non-moving space (e.g., storing long-lived objects), and so forth. In one example, the allocation space <NUM> stores relatively short-lived objects that might be targeted during a garbage collection process. Moreover, the threads may correspond to user interface activities that provide rich special effects and cause the short-lived objects to consume a relatively large amount of memory.

In the illustrated example, the allocation space <NUM> includes a first region 20a ("Region <NUM>"), a second region 20b ("Region <NUM>"), a third region 20c ("Region <NUM>"), a fourth region 20d ("Region <NUM>"), and a fifth region 20e ("Region <NUM>"). The number of regions shown is for discussion purposes only and may vary depending on the circumstances. Regions of the illustrated allocation space <NUM> are individually dedicated to specific threads and/or activities. For example, the second region 20b and the third region 20c may be dedicated to a first thread ("Thread <NUM>"), the fourth region 20d might be dedicated to a second thread ("Thread <NUM>"), and so forth. In an embodiment, the objects in the second region 20b and the third region 20c may be shared between functions associated with the first thread without conducting extra copy operations. Similarly, the objects in the fourth region 20d may be shared between functions associated with the second thread without conducting extra copy operations. As will be discussed in greater detail, the illustrated solution enables performance to be enhanced.

<FIG> shows a flow diagram <NUM> in which a memory allocator (e.g., framework layer runtime manager) detects a function <NUM> (callback method "onCreate()") that will create a new thread. In the illustrated example, the memory allocator triggers the dedication of a memory region to the thread by issuing a first command <NUM> ("StartMemoryRegionO"). When the application calls the function <NUM>, all objects (e.g., "Object a", "Object b") associated with the new thread will be allocated to the dedicated memory region. In addition to calling the function <NUM>, the memory allocator may set a flag in the calling thread object to activate thread based allocation. In an embodiment, the memory allocator also maps the thread to the dedicated memory region. Table I below shows an example of such a mapping.

When the function <NUM> is done allocating objects, the illustrated memory allocator issues a second command <NUM> ("StopMemoryRegion()") to discontinue dedicating objects to the memory region in question. The memory allocator may also clear the flag in the calling thread object to deactivate the thread based allocation in response to the termination of the thread. In an embodiment, the memory allocator also clears the appropriate thread-to-region table mapping entries. An example of pseudocode to implement the first command <NUM> and the second command <NUM> is shown below. StartMemoryRegionO {
threadId = GetThreadId();
SetActivityModeAllocate(threadId);
regionId = AllocateNewRegion();
Record in the table with threadId and regionId;
}
StopMemoryRegion() {
threadId = GetThreadId();
UnsetActivityMode Allocate (threadId);
}.

If the size of the selected region is insufficient, an additional unused region may be dedicated to the objects associated with the thread. In an embodiment, the memory allocator checks whether the thread is under thread allocation mode. If not, the memory allocator may switch to a normal allocation mode. Otherwise, the memory allocator searches the table to find the specific region identifier and attempts to allocate the object in the designated region. If the region is full, the memory allocator may allocate another region for the thread and update the table correspondingly. An example of pseudocode to implement the selection of an additional region is shown below. AllocateObject() {
threadId = GetThreadId();
checkActivityMode(threadId);
If not true:
//Origin code path to allocate objects else:
regionid = FindRegionID(threadid);
Allocate Obj ect(regionid);
If not enough space:
newRegionId = AllocateNewRegion();
Update the newRegionId to the table
AllocateObject(newRegionid);
}.

With continuing reference to <FIG> and <FIG>, termination of a thread may trigger a reclamation of all regions dedicated to the thread. For example, the termination of Thread <NUM> results in all objects in the second region 20b and the third region 20c being reclaimed. In an embodiment, the termination of the thread is detected based on high level (e.g., upper layer) information from the application. Of particular note is that garbage collector (GC) operations such as a pause phase in which all other threads are paused (e.g., to permit the GC to collect a root object set and determine which regions are to be reclaimed), are bypassed. Other GC operations such as a copy phase in which the GC scans all living objects starting from the root set and copies those objects to an unused region (e.g., destination region), are also bypassed in the illustrated solution. Indeed, if the thread produces only short-lived objects, the frequency of executing GC operations may approach zero. Accordingly, performance is enhanced in terms of processor usage, unpredicted pauses in user interfaces, additional power consumption (e.g., reduced battery life), and so forth.

<FIG> shows a flow diagram <NUM> in which the memory allocator detects a function <NUM> (callback method "onDestroyO") that will terminate an existing thread. In an embodiment, the function <NUM> results from too many applications running in the background, the application being closed and removed from an active application list, and so forth. In the illustrated example, the memory allocator triggers the reclamation of one or more memory regions that are dedicated to the thread by issuing a command <NUM> ("ReclaimMemoryRegionO"). When the application calls the function <NUM>, all memory regions that are dedicated to the thread will be reclaimed. In an embodiment, the memory allocator locates the selected regions for the thread by searching a table such as, for example, Table I for the appropriate thread identifier. The regions may be reclaimed one at a time. An example of pseudocode to implement the command <NUM> is shown below. ReclaimMemoryRegionO {
threadid = GetThreadId();
allRegionIds = FindAllRegionIDs(threadid);
For each id in allRegionIds:
FreeRegion(id);
}
<FIG> shows a method <NUM> of managing memory. The method <NUM> may generally be implemented in a memory allocator such as, for example, the aforementioned memory allocator (<FIG>). More particularly, the method <NUM> may be implemented as one or more modules in a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality hardware logic using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

For example, computer program code to carry out operations shown in the method <NUM> may be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state-setting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and/or other structural components that are native to hardware (e.g., host processor, central processing unit/CPU, microcontroller, etc.).

Illustrated processing block <NUM> detects the initiation of a thread, where a first memory region is dedicated to objects associated with the thread at block <NUM>. In an embodiment, block <NUM> includes activating thread based allocation and mapping the thread to the first memory region. A determination may be made at block <NUM> as to whether a termination of the thread has been initiated. If not, the illustrated method <NUM> repeats block <NUM>. Of particular note is that the objects associated with the same thread are expected to have a similar lifecycle. Accordingly, upon detection of the thread termination, block <NUM> conducts a first reclamation of the first memory region in response to termination of the thread. In an embodiment, the method <NUM> further includes deactivating thread based allocation in response to the termination of the thread and unmapping the thread from the first memory region. The first memory region is a heap region and the first reclamation bypasses a pause phase and a copy phase of a garbage collection process with respect to the heap region.

Additionally, the thread may correspond to a user interface (UI) activity. The method <NUM> may therefore enhance performance in terms of processor usage, unpredicted pauses in user interfaces, additional power consumption (e.g., reduced battery life), and so forth.

The illustrated method <NUM> may be used for native applications such as, for example, C or C++ applications, as well as for managed runtime applications having garbage collectors, which automatically reclaim memory that is no longer being used. The managed runtime applications may include, but are not limited to, for example, HTML5 (Hypertext Markup Language <NUM>, e.g., HTML <NUM>, W3C Recommendation, <NUM> December <NUM>), JAVASCRIPT, C# (e.g., C# <NUM>, MICROSOFT Corp. , May <NUM>, <NUM>), Ruby (e.g., Ruby <NUM>. Matsumoto, April <NUM>, <NUM>), Perl (e.g., Perl <NUM>. <NUM>, Perl. org, April <NUM>, <NUM>), Python (e.g., Python <NUM>. <NUM>, Python Software Foundation, March <NUM>, <NUM>), JAVA (e.g., JAVA <NUM>, ORACLE Corp. , March <NUM>, <NUM>), etc..

<FIG> shows another method <NUM> of managing memory. The method <NUM> may generally be implemented in a memory allocator such as, for example, the aforementioned memory allocator (<FIG>). More particularly, the method <NUM> may be implemented as one or more modules in a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLAs, FPGAs, CPLDs, in fixed-functionality hardware logic using circuit technology such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

Illustrated processing block <NUM> determines whether the first memory region is full. If so, a second memory region may be dedicated at block <NUM> to the objects associated with the thread. Additionally, a determination may be made at block <NUM> as to whether a termination of the thread has been initiated. If not, the illustrated method <NUM> repeats block <NUM>. Upon detection of the thread termination, block <NUM> conducts a second reclamation of the second memory region in response to termination of the thread. Accordingly, the method <NUM> further enhances performance by supporting threads that allocate a relatively large number of obj ects (e.g., much larger than a stack, and therefore eliminating concerns over a stack overflow).

Turning now to <FIG>, a performance-enhanced computing system <NUM> is shown. The system <NUM> may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television/TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), robotic <NUM> functionality (e.g., autonomous robot), etc., or any combination thereof. In the illustrated example, the system <NUM> includes a host processor <NUM> (e.g., central processing unit/CPU) having an integrated memory controller (IMC) <NUM> that is coupled to a system memory <NUM>.

The illustrated system <NUM> also includes an input output (IO) module <NUM> implemented together with the host processor <NUM> and a graphics processor <NUM> on a semiconductor die <NUM> as a system on chip (SoC). The illustrated IO module <NUM> communicates with, for example, a display <NUM> (e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), a network controller <NUM> (e.g., wired and/or wireless NIC), and mass storage <NUM> (e.g., hard disk drive/HDD, optical disk, solid state drive/SSD, flash memory).

In an embodiment, the host processor <NUM> and/or the IO module <NUM> execute program instructions <NUM> retrieved from the system memory <NUM> and/or the mass storage <NUM> to perform one or more aspects of the method <NUM> (<FIG>) and/or the method <NUM> (<FIG>), already discussed. Thus, execution of the illustrated instructions <NUM> may cause the computing system <NUM> to detect a creation of a thread, dedicate a first memory region in the system memory <NUM> to objects associated with the thread, and conduct a first reclamation of the first memory region in response to a termination of the thread. The first memory region is a heap region and the first reclamation bypasses at least a pause phase and a copy phase of a garbage collection process with respect to the heap region. Additionally, the thread may correspond to a UI activity (e.g., of a high performance game application) that causes the objects to be short-lived and to consume a relatively large amount of the system memory <NUM>. In such a case the illustrated display <NUM> visually presents information associated with the UI activity.

As already noted, GC operations such as a pause phase in which all other threads are paused (e.g., to permit the GC to collect the root object set and determine which regions are to be reclaimed), are bypassed. Other GC operations such as a copy phase in which the GC scans all living objects starting from the root set and copies those objects to an unused region (e.g., destination region), are also bypassed in the illustrated solution. Accordingly, the performance of the computing system <NUM> is enhanced in terms of processor usage, unpredicted pauses in user interfaces, additional power consumption (e.g., reduced battery life), and so forth.

<FIG> shows a semiconductor apparatus <NUM> (e.g., chip, die, package). The illustrated apparatus <NUM> includes one or more substrates <NUM> (e.g., silicon, sapphire, gallium arsenide) and logic <NUM> (e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s) <NUM>. In an embodiment, the logic <NUM> implements one or more aspects of method <NUM> (<FIG>) and/or the method <NUM> (<FIG>), already discussed. Thus, the logic <NUM> may detect a creation of a thread, dedicate a first memory region to objects associated with the thread, and conduct a first reclamation of the first memory region in response to a termination of the thread. The first memory region is a heap region and the first reclamation bypasses (e.g., avoids) at least a pause phase and a copy phase of a garbage collection process with respect to the heap region. The performance of the apparatus <NUM> is therefore enhanced in terms of processor usage, unpredicted pauses in user interfaces, additional power consumption (e.g., reduced battery life), and so forth.

The logic <NUM> may be implemented at least partly in configurable logic or fixed-functionality hardware logic. In one example, the logic <NUM> includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) <NUM>. Thus, the interface between the logic <NUM> and the substrate(s) <NUM> may not be an abrupt junction. The logic <NUM> may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s) <NUM>.

<FIG> illustrates a processor core <NUM> according to one embodiment. The processor core <NUM> may be the core for any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core <NUM> is illustrated in <FIG>, a processing element may alternatively include more than one of the processor core <NUM> illustrated in <FIG>. The processor core <NUM> may be a single-threaded core or, for at least one embodiment, the processor core <NUM> may be multithreaded in that it may include more than one hardware thread context (or "logical processor") per core.

<FIG> also illustrates a memory <NUM> coupled to the processor core <NUM>. The memory <NUM> may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory <NUM> may include one or more code <NUM> instruction(s) to be executed by the processor core <NUM>, wherein the code <NUM> may implement method <NUM> (<FIG>) and/or the method <NUM> (<FIG>), already discussed. The processor core <NUM> follows a program sequence of instructions indicated by the code <NUM>. Each instruction may enter a front end portion <NUM> and be processed by one or more decoders <NUM>. The decoder <NUM> may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion <NUM> also includes register renaming logic <NUM> and scheduling logic <NUM>, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

The processor core <NUM> is shown including execution logic <NUM> having a set of execution units <NUM>-<NUM> through <NUM>-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic <NUM> performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back end logic <NUM> retires the instructions of the code <NUM>. In one embodiment, the processor core <NUM> allows out of order execution but requires in order retirement of instructions. Retirement logic <NUM> may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core <NUM> is transformed during execution of the code <NUM>, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic <NUM>, and any registers (not shown) modified by the execution logic <NUM>.

Although not illustrated in <FIG>, a processing element may include other elements on chip with the processor core <NUM>. For example, a processing element may include memory control logic along with the processor core <NUM>. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.

Referring now to <FIG>, shown is a block diagram of a computing system <NUM> embodiment in accordance with an embodiment. Shown in <FIG> is a multiprocessor system <NUM> that includes a first processing element <NUM> and a second processing element <NUM>. While two processing elements <NUM> and <NUM> are shown, it is to be understood that an embodiment of the system <NUM> may also include only one such processing element.

The system <NUM> is illustrated as a point-to-point interconnect system, wherein the first processing element <NUM> and the second processing element <NUM> are coupled via a point-to-point interconnect <NUM>. It should be understood that any or all of the interconnects illustrated in <FIG> may be implemented as a multi-drop bus rather than point-to-point interconnect.

As shown in <FIG>, each of processing elements <NUM> and <NUM> may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with <FIG>.

Each processing element <NUM>, <NUM> may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory <NUM>, <NUM> for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

While shown with only two processing elements <NUM>, <NUM>, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements <NUM>, <NUM> may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor <NUM>, additional processor(s) that are heterogeneous or asymmetric to processor a first processor <NUM>, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements <NUM>, <NUM> in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements <NUM>, <NUM>. For at least one embodiment, the various processing elements <NUM>, <NUM> may reside in the same die package.

The first processing element <NUM> may further include memory controller logic (MC) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, the second processing element <NUM> may include a MC <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MC's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors. While the MC <NUM> and <NUM> is illustrated as integrated into the processing elements <NUM>, <NUM>, for alternative embodiments the MC logic may be discrete logic outside the processing elements <NUM>, <NUM> rather than integrated therein.

The first processing element <NUM> and the second processing element <NUM> may be coupled to an I/O subsystem <NUM> via P-P interconnects <NUM><NUM>, respectively. As shown in <FIG>, the I/O subsystem <NUM> includes P-P interfaces <NUM> and <NUM>. Furthermore, I/O subsystem <NUM> includes an interface <NUM> to couple I/O subsystem <NUM> with a high performance graphics engine <NUM>. In one embodiment, bus <NUM> may be used to couple the graphics engine <NUM> to the I/O subsystem <NUM>. Alternately, a point-to-point interconnect may couple these components.

In turn, I/O subsystem <NUM> may be coupled to a first bus <NUM> via an interface <NUM>. In one embodiment, the first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.

As shown in <FIG>, various I/O devices <NUM> (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus <NUM>, along with a bus bridge <NUM> which may couple the first bus <NUM> to a second bus <NUM>. In one embodiment, the second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to the second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication device(s) <NUM>, and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. The illustrated code <NUM> may implement the method <NUM> (<FIG>) and/or the method <NUM> (<FIG>), already discussed, and may be similar to the code <NUM> (<FIG>), already discussed. Further, an audio I/O <NUM> may be coupled to second bus <NUM> and a battery <NUM> may supply power to the computing system <NUM>.

Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or another such communication topology. Also, the elements of <FIG> may alternatively be partitioned using more or fewer integrated chips than shown in <FIG>.

Thus, technology described herein packs an activity and the objects created by the activity into a single object bundle and reclaims memory consumed by the objects all at once (e.g., and without invoking a GC thread). The technology may apply to any language and may focus on the reclamation of all objects sharing a similar lifetime. Moreover, the technology may not place any additional burden on application developers (e.g., all modifications may be made in the managed runtime framework layer). The technology is also transparent to users (e.g., no negative impact on the user experience) and supports the sharing of objects between functions without extra copying operations (e.g., as in threaded memory allocators and/or resource allocation is initialization/RAII solutions).

Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

Claim 1:
A semiconductor apparatus (<NUM>) comprising:
one or more substrates (<NUM>); and
logic (<NUM>) coupled to the one or more substrates (<NUM>), wherein the logic (<NUM>) is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic (<NUM>) coupled to the one or more substrates (<NUM>) to:
detect a creation of a thread;
dedicate a first memory region to objects associated with the thread, wherein the first memory region is a heap region; characterised in that the logic is further configured to:
conduct a first reclamation of the first memory region in response to a termination of the thread, wherein the first reclamation is to bypass a pause phase and a copy phase of a garbage collection process with respect to the heap region.