Patent Description:
Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and speed in comparison to alternative types of memory.

Presently, DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures. Accordingly, it would be desirable to develop new memory cell configurations suitable for incorporation into highly-integrated modern memory architectures.

Another prior art memory cell configuration, alternative to the 1T-1C configuration, is a configuration which utilizes two capacitors in combination with two transistors. Such configuration may be referred to as a 2T-2C memory cell. A 2T-2C memory cell is schematically illustrated in <FIG> as a memory cell <NUM>. The two transistors of the memory cell are labeled as T1 and T2, and the two capacitors are labeled as CAP-<NUM> and CAP-<NUM>.

A source/drain region of the first transistor T1 connects with a node of the first capacitor (CAP-<NUM>), and the other source/drain region of T1 connects with a first comparative bitline (BL-<NUM>). A gate of T1 connects with a wordline (WL). A source/drain region of the second transistor T2 connects with a node of the second capacitor (CAP-<NUM>), and the other source/drain region of T2 connects with a second comparative bitline BL-<NUM>. A gate of T2 connects with the wordline (WL). Each of the first and second capacitors (CAP-<NUM> and CAP-<NUM>) has a node electrically coupled with a common plate (CP). The common plate may be coupled with any suitable voltage, such as a voltage within a range of from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP < VCC). In some applications the common plate is at a voltage of about one-half VCC (i.e., about VCC/<NUM>).

The comparative bitlines BL-<NUM> and BL-<NUM> extend to circuitry <NUM> which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell <NUM>. An advantage of the 2T-2C memory cell is that a memory state may be ascertained by comparing the electrical properties of the two comparative bitlines BL-<NUM> and BL-<NUM> to one another. Accordingly, a reference bitline associated with prior art memory (for instance, 1T-1C memory) may be omitted.

<CIT> relates to a semiconductor device that includes a word line, a capacitor line, a first bit line, a second bit line, and a first transistor and a second transistor each of which includes a gate, a source, and a drain. The first transistor and the second transistor at least partly overlap with each other, and the gates of the first transistor and the second transistor are connected to the word line. A capacitor is formed between at least part of the capacitor line and each of the drains of the first transistor and the second transistor. The first bit line is connected to the source of the first transistor, and the second bit line is connected to the source of the second transistor.

It would be desirable to develop 2T-2C configurations suitable for incorporation into highly-integrated modern memory architectures.

Some embodiments include 2T-2C configurations in which two or more components are vertically stacked relative to one another in order to increase integration. The 2T-2C configurations described herein may be utilized in DRAM (dynamic random access memory) and/or other types of memory. Among the possible advantages of 2T-2C memory cells relative to conventional 1T-1C memory cells are elimination of a reference bitline (as described above in the "Background" section) and doubling of the magnitude of a sense signal. Additionally, since both plates of a capacitor cell may be electrically floating in a non-accessed data state, some mechanisms of "disturb" (e.g., crosstalk between adjacent memory cells of a memory array) may be reduced or eliminated. Example embodiment 2T-2C memory configurations are described below with reference to <FIG>.

<FIG> shows a region of a memory array <NUM> comprising example 2T-2C memory cells. Specifically, a pair of adjacent memory cells <NUM> and 12a are illustrated. A dashed line <NUM> demarcates an approximate boundary of the memory cell <NUM>. The memory cells <NUM> and 12a are substantially identical to one another, with the term "substantially identical" meaning that the memory cells are identical to within reasonable tolerances of fabrication and measurement.

The illustrated portion of memory array <NUM> is supported by a base <NUM>. The base <NUM> may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications the base <NUM> may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. The base <NUM> is shown to be spaced from components of array <NUM> to indicate that other circuitry or components may be between array <NUM> and the base. An interlayer insulating film may intervene between the base <NUM> and the array <NUM>. The interlayer insulating film may comprise, for example, silicon oxide.

The adjacent memory cells <NUM> and 12a are in a common column as one another within the memory array (i.e., are along a common bitline). The memory cells <NUM> and 12a are shown along comparative bitlines BL-<NUM> and BL-<NUM>, and the comparative bitlines BL-<NUM> and BL-<NUM> together function as a bitline of the memory array. The comparative bitlines BL-<NUM> and BL-<NUM> are electrically coupled with circuitry <NUM> of the type described above with reference to <FIG>. Circuitry <NUM> may be in any suitable location relative to array <NUM>, and may be, for example, between array <NUM> and base <NUM>, laterally offset from array <NUM>, etc. Circuitry <NUM> may be further incorporated into the base <NUM> as a sense amplifier together with other electrical circuits that may be used to access to the array <NUM> to read or write data from or into the array <NUM>. In applications where an interlayer insulating film intervenes between the array <NUM> and the base <NUM>, a plurality of vias may be formed in the interlayer insulating film to electrically connect wordlines WL-<NUM> and WL-<NUM> and bitlines BL-<NUM> and BL-<NUM> of the array <NUM> to the circuits such as the sense amplifiers <NUM> that are formed in the base <NUM>. The bitline BL-<NUM> may be located on the interlayer insulating film.

The memory cell <NUM> comprises first and second transistors T1 and T2, and comprises first and second capacitors CAP-<NUM> and CAP-<NUM> between the first and second transistors.

The first capacitor CAP-<NUM> comprises a first conductive node <NUM>, a second conductive node <NUM>, and a first capacitor dielectric material <NUM> between the first and second conductive nodes. Similarly, the second capacitor CAP-<NUM> comprises a third conductive node <NUM>, a fourth conductive node <NUM>, and second capacitor dielectric material <NUM> between the third and fourth conductive nodes.

The conductive materials of the first, second, third and fourth nodes <NUM>, <NUM>, <NUM> and <NUM> may be any suitable conductive materials, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc. Some or all of the nodes <NUM>, <NUM>, <NUM> and <NUM> may comprise the same composition as one another, or may comprise different compositions relative to one another.

The capacitor dielectric materials <NUM> and <NUM> may comprise any suitable composition (e.g., non-ferroelectric material, ferroelectric material and magnetic material) or combination of compositions. In some embodiments the capacitor dielectric materials may comprise non-ferroelectric material and may, for example, consist of one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. In some embodiments the capacitor dielectric materials may comprise ferroelectric material. For instance, the capacitor dielectric materials may comprise, consist essentially of, or consist of one or more materials selected from the group consisting of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and having dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, niobium, strontium, and a rare earth element. In some embodiments the capacitor dielectric materials <NUM> and <NUM> may comprise a same composition as one another, and in other embodiments may comprise different compositions relative to one another.

In the shown embodiment the first and third conductive nodes <NUM> and <NUM> are container-shaped outer nodes, and the second and fourth conductive nodes <NUM> and <NUM> are inner nodes which extend into the container-shaped outer nodes. In other embodiments the first and third conductive nodes <NUM> and <NUM> may be container-shaped nodes, and the second and fourth conductive nodes <NUM> and <NUM> may surround inner and outer surfaces of the container-shaped nodes. In other embodiments the first and third conductive nodes <NUM> and <NUM> may be pillar-shaped inner nodes, and the second and fourth conductive nodes <NUM> and <NUM> may be container-shaped outer nodes which surround outer surfaces of the pillar-shaped inner nodes. In other embodiments the first and third conductive nodes <NUM> and <NUM> may have other configurations, and the second and fourth nodes <NUM> and <NUM> may also have other configurations.

The second and fourth conductive nodes <NUM> and <NUM> are electrically coupled with a common plate (CP) structure <NUM>. In the illustrated embodiment the conductive nodes <NUM> and <NUM> share a common composition with structure <NUM>. In other embodiments the structure <NUM> may comprise a different composition as compared to the conductive nodes <NUM> and <NUM>. Structure <NUM> may comprise any suitable conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc..

The first and second capacitors, CAP-<NUM> and CAP-<NUM>, are vertically displaced relative to one another, with the second capacitor CAP-<NUM> being above the first capacitor CAP-<NUM>. The first transistor T1 is between the first capacitor CAP-<NUM> and the first comparative bitline BL-<NUM>, and the second transistor T2 is between the second capacitor CAP-<NUM> and the second comparative bitline BL-<NUM>.

In the shown embodiment a first semiconductor pillar <NUM> extends upwardly from the first comparative bitline BL-<NUM> to the first conductive (or outer conductive) node <NUM> of the first capacitor CAP-<NUM>, and the first transistor T1 is along such first semiconductor pillar <NUM>. The first transistor T1 has a first conductive transistor gate <NUM> which is spaced from the semiconductor pillar <NUM> by gate dielectric material <NUM>. The first transistor T1 has a first channel region <NUM> within semiconductor pillar <NUM> and along the gate dielectric material <NUM>, and has first and second source/drain regions <NUM> and <NUM> within the semiconductor pillar and on opposing sides of the channel region <NUM>. The first source/drain region <NUM> is electrically coupled with the first conductive node <NUM> of first capacitor CAP-<NUM>, and the second source/drain region <NUM> is electrically coupled with the first comparative bitline BL-<NUM>. In the shown embodiment the first source/drain region <NUM> extends to the first conductive node <NUM> of the first capacitor CAP-<NUM>. In other embodiments the first source/drain region <NUM> may extend to an electrical interconnect which in turn extends to the first conductive node <NUM> of the first capacitor CAP-<NUM>. Also, in the shown embodiment the second source/drain region <NUM> extends to the first comparative bitline BL-<NUM>. In other embodiments the second source/drain region <NUM> may extend to an electrical interconnect which in turn extends to the first comparative bitline BL-<NUM>.

The semiconductor pillar <NUM> may comprise any suitable semiconductor materials including, for example, one or both of silicon and germanium. The source/drain regions <NUM>/<NUM> and channel region <NUM> may be doped with any suitable dopants. In some embodiments the source/drain regions <NUM>/<NUM> may be n-type majority doped, and in other embodiments may be p-type majority doped.

A second semiconductor pillar <NUM> extends downwardly from the second comparative bitline BL-<NUM> to the outer node <NUM> of the second capacitor CAP-<NUM>, and the second transistor T2 is along such second semiconductor pillar <NUM>. The second transistor T2 has a second conductive transistor gate <NUM> which is spaced from the semiconductor pillar <NUM> by gate dielectric material <NUM>. The second transistor T2 has a second channel region <NUM> within the semiconductor pillar <NUM> and along the gate dielectric material <NUM>, and has third and fourth source/drain regions <NUM> and <NUM> within the semiconductor pillar and on opposing sides of the channel region <NUM>. The third source/drain region <NUM> is electrically coupled with the third conductive node <NUM> of second capacitor CAP-<NUM>, and the fourth source/drain region <NUM> is electrically coupled with the second comparative bitline BL-<NUM>. In the shown embodiment the third source/drain region <NUM> extends to the third conductive node <NUM> of the second capacitor CAP-<NUM>. In other embodiments the third source/drain region <NUM> may extend to an electrical interconnect which in turn extends to the third conductive node <NUM> of the second capacitor CAP-<NUM>. Also, in the shown embodiment the fourth source/drain region <NUM> extends to the second comparative bitline BL-<NUM>. In other embodiments the fourth source/drain region <NUM> may extend to an electrical interconnect which in turn extends to the second comparative bitline BL-<NUM>.

The conductive gates <NUM> and <NUM> of the first and second transistors T1 and T2 are electrically coupled with a first wordline WL-<NUM>. Such first wordline WL-<NUM> may extend in and out of the page relative to the cross-section section of <FIG>.

The memory cell 12a is similar to memory cell <NUM>, and comprises first and second capacitors CAP-1a and CAP-2a together with first and second transistors T1a and T2a. The first and second transistors comprise conductive gates 30a and 42a which are electrically coupled with a second wordline WL-<NUM>. Accordingly, the second memory cell 12a is along a different row (i.e. wordline) than the first memory cell <NUM> within the memory array <NUM>.

The wordlines (WL-<NUM> and WL-<NUM>) and comparative bitlines (BL-<NUM> and BL-<NUM>) may comprise any suitable electrically conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc. The wordlines and comparative bitlines may comprise the same composition as one another, or may comprise different compositions relative to one another.

Insulative material <NUM> is shown to surround the various components of memory cells <NUM> and 12a. Such insulative material may comprise any suitable composition or combination of compositions; including, for example, one or more of silicon dioxide, silicon nitride, borophosphosilicate glass, spin-on dielectric, etc. Although insulative material <NUM> is shown as a single homogeneous material, in other embodiments the insulative material may include two or more discrete insulative compositions.

In the illustrated embodiment of <FIG> the common plate structure <NUM> is a rail extending horizontally along the column defined by the comparative bitlines BL-<NUM> and BL-<NUM>. Such rail is shared by the memory cells <NUM> and 12a, as well as by all other memory cells along such column. In other embodiments the common plate structure may be subdivided into a plurality of separate common plate structures. For instance, <FIG> shows a portion of an example embodiment memory array <NUM> in which the rail <NUM> of <FIG> is replaced by a plurality of common plate structures <NUM>, 54a, etc., with such common plate structures being in one-to-one correspondence with the memory cells <NUM>, 12a, etc. of the memory array.

In the illustrated embodiments of <FIG> and <FIG> the first and second transistors T1 and T2 of the memory cell <NUM> are vertically displaced relative to one another, as are the first and second capacitors CAP-<NUM> and CAP-<NUM>. Further, the first and second capacitors, and first and second transistors, are in a common vertical plane as one another (i.e., are vertically stacked one atop another).

<FIG> shows a portion of a memory array <NUM> comprising a pair of memory cells <NUM> and 12b, with the cell <NUM> being vertically stacked over the cell 12b. A dashed line <NUM> demarcates an approximate boundary of the memory cell <NUM>.

The illustrated portion of memory array <NUM> is supported by a base <NUM>.

Comparative bitlines BL-<NUM> and BL-<NUM> are between the memory cells <NUM> and 12b, and extend in and out of the page relative to the cross-section of <FIG>. The comparative bitlines BL-<NUM> and BL-<NUM> are electrically coupled with circuitry <NUM> of the type described above with reference to <FIG>. The comparative bitlines BL-<NUM> and BL-<NUM> are shared by the memory cells <NUM> and 12b.

The memory cell <NUM> comprises first and second transistors T1 and T2 which are laterally displaced relative to one another. The memory cell <NUM> comprises the first capacitor CAP-<NUM> above the first transistor T1, and comprises the second capacitor CAP-<NUM> above the second transistor T2.

The first capacitor CAP-<NUM> comprises the first conductive node <NUM>, second conductive node <NUM>, and first capacitor dielectric material <NUM>; and the second capacitor CAP-<NUM> comprises the third conductive node <NUM>, fourth conductive node <NUM>, and second capacitor dielectric material <NUM>.

The second and fourth conductive nodes <NUM> and <NUM> are electrically coupled with a common plate (CP) structure <NUM> provided above the first and second capacitors CAP-<NUM> and CAP-<NUM>. In the illustrated embodiment the conductive nodes <NUM> and <NUM> share a common composition with structure <NUM>. In other embodiments the structure <NUM> may comprise a different composition as compared to the conductive nodes <NUM> and <NUM>. The structure <NUM> may comprise any suitable conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc..

The first and second capacitors CAP-<NUM> and CAP-<NUM> are laterally displaced relative to one another, and in the shown embodiment are in a same horizontal plane as one another (i.e., are horizontally aligned with one another).

The first transistor T1 is between the first capacitor CAP-<NUM> and the first comparative bitline BL-<NUM>, and the second transistor T2 is between the second capacitor CAP-<NUM> and the second comparative bitline BL-<NUM>. In the shown embodiment the first and second transistors (T1 and T2) are in a common horizontal plane as one another, and the wordline WL-<NUM> extends along such horizontal plane and comprises the gates <NUM> and <NUM> of the first and second transistors.

The first semiconductor pillar <NUM> extends upwardly from the first comparative bitline BL-<NUM> to the first conductive (or outer conductive) node <NUM> of the first capacitor CAP-<NUM>, and the first transistor T1 is along such first semiconductor pillar <NUM>. The second semiconductor pillar <NUM> extends upwardly from the second comparative bitline BL-<NUM> to the second conductive (or outer conductive) node <NUM> of the second capacitor CAP-<NUM>, and the second transistor T2 is along such second semiconductor pillar <NUM>.

The first transistor T1 includes the gate dielectric material <NUM>, the first channel region <NUM>, and the first and second source/drain regions <NUM> and <NUM>. The first source/drain region <NUM> is electrically coupled with the first conductive node <NUM> of first capacitor CAP-<NUM>, and the second source/drain region <NUM> is electrically coupled with the first comparative bitline BL-<NUM>.

The second transistor T2 includes the gate dielectric material <NUM>, the second channel region <NUM>, and the third and fourth source/drain regions <NUM> and <NUM>. The third source/drain region <NUM> is electrically coupled with the third conductive node <NUM> of second capacitor CAP-<NUM>, and the fourth source/drain region <NUM> is electrically coupled with the second comparative bitline BL-<NUM>.

The memory cell 12b is similar to memory cell <NUM>, and comprises first and second capacitors CAP-1b and CAP-2b together with first and second transistors T1b and T2b. The first and second transistors comprise conductive gates 30b and 42b which are electrically coupled with a second wordline WL-<NUM>. The second and fourth conductive nodes (or inner conductive nodes) 16b and 22b of the first and second capacitors CAP-1b and CAP-2b are electrically coupled with a common plate structure 58b provided beneath the capacitors CAP-1b and CAP-2b.

In the illustrated embodiment the first and second comparative bitlines BL-<NUM> and BL-<NUM> are in a common horizontal plane as one another. An axis <NUM> extending through the comparative bitlines BL-<NUM> and BL-<NUM> may be considered to define a mirror plane. The memory cell 12b may be considered to be a substantially mirror image of the memory cell <NUM> across the mirror plane. The term "substantially mirror image" is utilized to indicate that the memory cell 12b may be a mirror image of the memory cell <NUM> to within reasonable tolerances of fabrication and measurement.

In some embodiments the configuration of <FIG> and <FIG> may be considered to comprise memory cells within 4F<NUM> architecture, and the configuration of <FIG> may be considered to comprise memory cells within 8F<NUM> architecture.

In the illustrated embodiment of <FIG> the first and second comparative bitlines BL-<NUM> and BL-<NUM> are shared by the memory cells <NUM> and 12b. In other embodiments an electrically conductive rail at common plate voltage may be shared by memory cells which are vertically disposed on opposing sides of the rail from one another, with <FIG> illustrating an example of such other embodiments.

<FIG> shows a portion of a memory array <NUM> comprising a pair of memory cells <NUM> and 12c, with the cell <NUM> being vertically stacked over the cell 12c. A dashed line <NUM> demarcates an approximate boundary of the memory cell <NUM>.

A horizontally-extending rail <NUM> is between the memory cells <NUM> and 12c, and extends along the cross-section of <FIG>. The rail <NUM> has a voltage corresponding to the common plate (CP), and is shared by the memory cells <NUM> and 12c. In some embodiments the rail may be referred to as a common plate structure.

The memory cell <NUM> comprises first and second transistors T1 and T2 which are laterally displaced relative to one another. The memory cell <NUM> comprises the first capacitor CAP-<NUM> below the first transistor T1, and comprises the second capacitor CAP-<NUM> below the second transistor T2.

The second and fourth conductive nodes <NUM> and <NUM> are electrically coupled with the rail <NUM>. In the illustrated embodiment the conductive nodes <NUM> and <NUM> share a common composition with the rail <NUM>. In other embodiments the rail <NUM> may comprise a different composition as compared to the conductive nodes <NUM> and <NUM>. The rail <NUM> may comprise any suitable conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal-containing compositions (e.g., metal nitride, metal carbide, metal silicide, etc.), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc..

The first and second capacitors CAP-<NUM> and CAP-<NUM> are laterally displaced relative to one another, with the second capacitor CAP-<NUM> being in a same horizontal plane as the first capacitor CAP-<NUM>. The first transistor T1 is between the first capacitor CAP-<NUM> and a first comparative bitline BL-<NUM>, and the second transistor T2 is between the second capacitor CAP-<NUM> and a second comparative bitline BL-<NUM>. The first and second comparative bitlines BL-<NUM> and BL-<NUM> extend in and out of the page relative to the cross-section of <FIG>.

In the shown embodiment the first and second transistors T1 and T2 are in a common horizontal plane as one another, and the wordline WL-<NUM> extends along such horizontal plane and comprises the gates <NUM> and <NUM> of the first and second transistors.

The first semiconductor pillar <NUM> extends downwardly from the first comparative bitline BL-<NUM> to the first conductive (or outer conductive) node <NUM> of the first capacitor CAP-<NUM>, and the first transistor T1 is along such first semiconductor pillar <NUM>. The second semiconductor pillar <NUM> extends downwardly from the second comparative bitline BL-<NUM> to the third conductive (or outer conductive) node <NUM> of the second capacitor CAP-<NUM>, and the second transistor T2 is along such second semiconductor pillar <NUM>.

The memory cell 12c is similar to memory cell <NUM>, and comprises first and second capacitors CAP-1c and CAP-2c together with first and second transistors T1c and T2c. The first and second transistors T1c and T2c comprise conductive gates 30c and 42c which are electrically coupled with a second wordline WL-<NUM>. The second and fourth (or inner conductive) nodes 16c and 22c of the first and second capacitors CAP-1b and CAP-2b are electrically coupled with the rail <NUM>.

An axis <NUM> extending along the rail <NUM> may be considered to define a mirror plane. The memory cell 12c may be considered to be a substantially mirror image of the memory cell <NUM> across the mirror plane. The term "substantially mirror image" is utilized to indicate that the memory cell 12c may be a mirror image of the memory cell <NUM> to within reasonable tolerances of fabrication and measurement.

In the illustrated embodiment the first comparative bitline BL-<NUM> of memory cell <NUM> (i.e., the comparative bitline BL-<NUM> above wordline WL-<NUM>) and the first comparative bitline of memory cell 12c (i.e., the comparative bitline BL-<NUM> below wordline WL-<NUM>) are electrically coupled to one another; and the second comparative bitline BL-<NUM> of memory cell <NUM> (i.e., the comparative bitline BL-<NUM> above wordline WL-<NUM>) and the second comparative bitline of memory cell 12c (i.e., the comparative bitline BL-<NUM> below wordline WL-<NUM>) are electrically coupled to one another. Electrical properties of the coupled comparative bitlines BL-<NUM> are compared with those of the coupled comparative bitlines BL-<NUM> with circuitry <NUM> of the type described above with reference to <FIG>.

In some embodiments the configuration of <FIG> may be considered to comprise memory cells within 8F<NUM> architecture.

The structures and architectures described above may be incorporated into memory (e.g., DRAM, MRAM, FERAM, etc.) and/or otherwise may be utilized in electronic systems. Such electronic systems may be any of a broad range of systems, such as, for example, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

Both of the terms "dielectric" and "electrically insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "electrically insulative" in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

Claim 1:
A memory cell (<NUM>) having a 2T-2C configuration, the memory cell (<NUM>) comprising:
a first transistor (T1) comprising a first vertically extending pillar (<NUM>) having a first channel region (<NUM>)
therein and gate material (<NUM>) extending vertically along the first channel region (<NUM>), the first vertically extending pillar (<NUM>) extending to a first comparative bitline (BL-<NUM>);
a second transistor (T2) comprising a second vertically extending pillar (<NUM>) having a second channel region (<NUM>) therein and gate material (<NUM>) extending vertically along the second channel region (<NUM>), the second vertically extending pillar (<NUM>) extending to a second comparative bitline (BL-<NUM>);
a first capacitor (CAP-<NUM>) vertically displaced relative to the first transistor (T1), the first capacitor (CAP-<NUM>) having a first node (<NUM>) electrically coupled with a source/drain region (<NUM>) of the first transistor (T1), having a second node (<NUM>) electrically coupled with a common plate structure (<NUM>), and having a first capacitor dielectric material (<NUM>) between the first (<NUM>) and second nodes (<NUM>);
a second capacitor (CAP-<NUM>) vertically displaced relative to the second transistor (T2), the second capacitor (CAP-<NUM>) having a third node (<NUM>) electrically coupled with a source/drain region (<NUM>) of the second transistor (T2), having a fourth node (<NUM>) electrically coupled with the common plate structure (<NUM>), and having a second capacitor dielectric material (<NUM>) between the third and fourth nodes (<NUM>, <NUM>); and
characterised in that
the first and second transistors (T1, T2), and the first and second capacitors (CAP-<NUM>, CAP-<NUM>), are all vertically stacked one atop another.