Patent Description:
The following relates generally to a system that includes at least one memory device and more specifically to the architecture of three-dimensional memory devices and methods regarding the same.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic <NUM> or a logic <NUM>. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and others. Memory devices may be volatile or non-volatile.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Solutions for saving space in the memory array, increasing the memory cell density, or decreasing overall power usage of the memory array with three-dimensional vertical architecture may be desired.

<CIT> relates to a non-volatile memory that uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

<CIT> relates to a plurality of alternating stacks laterally spaced apart by line trenches that are provided over a substrate. Each alternating stack includes respective word lines and respective dielectric material layers. An alternating sequence of vertical bit lines and inter-bit-line cavities is formed within each of the line trenches. Resistive memory material layers including resistive memory elements are provided at intersection regions between the word lines and the vertical bit lines. Air gaps are formed by removing at least a predominant portion of each of the dielectric material layers selective to the word lines, the vertical bit lines, and the resistive memory material layers, thereby forming a plurality of alternating stacks of the word lines and air gaps. A dielectric isolation layer including vertically-extending voids can be formed over the plurality of alternating stacks in the inter-bit-line cavities.

The invention provides a method as recited in claim <NUM>. Further advantageous features are set out in the dependent claims.

The present disclosure relates to three-dimensional (3D) vertical self-selecting memory arrays with an increased density of memory cells, and methods of processing the same. The memory arrays may include an arrangement of conductive contacts and openings through alternative layers of conductive materials and insulative material that may decrease the spacing between the memory cells while maintaining a dielectric thickness to sustain the voltage to be applied to the memory array.

In some examples, a 3D memory array may include a substrate with a plurality of contacts arranged in a pattern (e.g., a geometric pattern) and a first dielectric material formed on the substrate. A plurality of planes of a conductive material may be separated by one another by a second dielectric material and formed on the substrate material. The planes of conductive material may be examples of word lines.

During manufacturing of such a memory array, a trench may be formed in a shape that separates odd and even WL line planes to create "comb" structures (e.g., structures that look like a tool with fingers and space between the fingers). The trench may any geometric configuration and include odd and even groups of fingers of the comb facing one another at a fixed distance. In some examples, the trench may be formed in a serpentine shape. The trench may divide each plane of conductive material into two sections or two plates. Each place of conductive material may be an example of a word line plate. In some examples, inside the trench, the planes of the conductive material may be etched in such a way that the dielectric materials and the conductive materials form a plurality of recesses, where each recess may be configured to receive a storage element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) may be deposited in the trench and, in some cases, the sacrificial layer fills the recesses. An insulative material may be deposited in the trench on top of the sacrificial layer. The sacrificial layer and the insulative layer may form a serpentine shape. In some examples, other geometric configurations of the trench are contemplated.

Portions of the sacrificial layer and the insulative may be removed to form openings. The openings may expose portions of the substrate, the plurality of conductive contacts, and portions of the conductive materials and dielectric materials. A storage element material (e.g., the chalcogenide material) is deposited in the openings. The storage element material may fill the recesses formed by the dielectric materials and the conductive materials. The storage element material may be partially removed from the openings such that only the storage element materials in the recesses remain.

Conductive pillars may be formed in the openings that include the storage element materials in the recesses. The conductive pillars may be examples of a digit lines. The conductive pillars may be arranged to extend (e.g., substantially perpendicular) to the planes of the conductive material and the substrate. Each conductive pillar may be coupled with a different conductive contact. The pillars may be formed of a barrier material and a conductive material.

Such configurations of a memory array and the methods of manufacturing may allow a higher-density of memory cells relative to previous solutions. Each memory cell (e.g., storage element material) may be recessed inside opposite sides of the conductive pillar to ensure the cell isolation. Such a configuration may allow for a tighter control of cell thickness and dimension with respect to some previous solutions. Each plane of conductive material that intersects the conductive pillar may form two memory cells addressed by a first word line plate in the plane and a second word line plate in the plane. Each conductive pillar may be decoded by a transistor positioned at the bottom or top of the memory array. The transistor may be an example of a digit line selector formed in a regular matrix.

Features of the disclosure are initially described in the context of a general memory array as described with reference to <FIG>. Features of the present invention are described in the context of different views of 3D memory arrays during processing steps as described with reference to <FIG>. These and other features are further illustrated by and described with reference to flowcharts as described with references to <FIG>.

<FIG> illustrates an example of a 3D memory array <NUM>. Memory array <NUM> includes a first array or deck <NUM> of memory cells that is positioned above a substrate <NUM> and a second array or deck <NUM> of memory cells on top of the first array or deck <NUM>.

Memory array <NUM> includes word lines <NUM> and digit lines <NUM>. Memory cells of the first deck <NUM> and the second deck <NUM> each may have one or more self-selecting memory cells. Although some elements included in <FIG> are labeled with a numeric indicator, other corresponding elements are not labeled, though they are the same or would be understood to be similar.

A stack of memory cells includes a first dielectric material <NUM>, a storage element material <NUM> (e.g., chalcogenide material), a second dielectric material <NUM>, a storage element material <NUM> (e.g., chalcogenide material), and a third dielectric material <NUM>. The self-selecting memory cells of the first deck <NUM> and second deck <NUM> may, in some examples, have common conductive lines such that corresponding self-selecting memory cells of each deck <NUM> and <NUM> may share digit lines <NUM> or word lines <NUM>.

A memory cell may be programmed by providing an electric pulse to the cell, which may include a memory storage element. The pulse may be provided via a first access line (e.g., word line <NUM>) or a second access line (e.g., digit line <NUM>), or a combination thereof. In some cases, upon providing the pulse, ions may migrate within the memory storage element, depending on the polarity of the memory cell. Thus, a concentration of ions relative to the first side or the second side of the memory storage element may be based at least in part on a polarity of a voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements may cause ions to be more crowded at portions of an element having more area. Certain portions of the memory storage element may have a higher resistivity and thus may give rise to a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of the self-selecting memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. This disclosure also includes other examples of mechanisms of the self-selecting memory cell for achieving the results described herein.

The architecture of memory array <NUM> may be referred to as a cross-point architecture, in some cases, in which a memory cell is formed at a topological cross-point between a word line <NUM> and a digit line <NUM>. Such a cross-point architecture may offer relatively high-density data storage with lower production costs compared to other memory architectures. For example, the cross-point architecture may have memory cells with a reduced area and, resultantly, an increased memory cell density compared to other architectures.

While the example of <FIG> shows two decks <NUM> and <NUM>, other configurations are possible. In some examples, a single memory deck of self-selecting memory cells may be constructed above a substrate <NUM>, which may be referred to as a two-dimensional memory. In some examples, a three or four memory decks of memory cells may be configured in a similar manner in a three-dimensional cross point architecture.

The memory array <NUM> may include a substrate <NUM> with a plurality of contacts arranged in a grid or staggered pattern. In some cases, the plurality of contacts may extend through the substrate and couple with an access line of the memory array <NUM>. The memory array <NUM> may include a plurality of planes of a conductive material separated by one another by a second insulative material formed on the first insulative material on the substrate material. Each of the plurality of planes of the conductive material may include a plurality of recesses formed therein. The plurality of planes, for example, word line plates, may be obtained by a replacement process by using a sacrificial layer (e.g., a conformal layer) for etching during a stack deposition processing step, removing the conformal layer after cell definition and replacing the conformal layer with a more conductive material.

An insulative material may be formed in a serpentine shape through the second insulative material and the conductive material. A plurality of conductive pillars may be arranged in openings to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate. Each respective one of the plurality of conductive pillars may be coupled to a different one of the conductive contacts.

In some examples, the decks <NUM> and <NUM> may include chalcogenide material configured to store logic states. For example, the memory cells of the decks <NUM> and <NUM> may be examples of self-selecting memory cells. A chalcogenide material may be formed in the plurality of recesses such that the chalcogenide material in each respective one of the plurality of recesses is at least partially in contact with one of the plurality of conductive pillars.

<FIG> illustrates a bottom view of a 3D memory array <NUM>-a in accordance with examples or embodiments of the invention as disclosed herein. The memory array <NUM>-a includes a plurality of conductive contacts <NUM> formed in a substrate <NUM> that extend through the substrate <NUM> and couple with an access line of the memory array <NUM>. For example, the substrate <NUM> may be a dielectric material, such as a dielectric film, or a semiconductor substrate, according to the invention.

A single conductive contact of the plurality of conductive contacts <NUM> may be configured to couple any single vertical pillar with a transistor (not shown). The plurality of conductive contacts <NUM> may be arranged in a grid pattern. In some examples, a respective one of the plurality of conductive contacts <NUM> may be surrounded by up to eight other conductive contacts <NUM>. In some examples, the plurality of conductive contacts <NUM> may be arranged in a staggered pattern or a hexagonal pattern. For example, a respective one of the plurality of conductive contacts <NUM> may be surrounded by up to six other conductive contacts <NUM> (see <FIG>).

<FIG> illustrates a side view of a 3D memory array <NUM>-b in accordance with examples or embodiments of the invention as disclosed herein. The memory array <NUM>-b includes a plurality of conductive contacts <NUM> formed in the substrate <NUM>. The memory array <NUM>-b also includes a plurality of stacked planes of an insulative material <NUM> and a plurality of stacked planes of a conductive material <NUM> (e.g., word lines planes or word line plates). The stacked planes of conductive material <NUM> may be separated in a z-direction (e.g., separated vertically) from one another by the plurality of planes of the insulative material <NUM>. A first plane (e.g., a bottom plane) of the second insulative material <NUM> is formed (e.g., deposited) on the plane of the substrate <NUM>, and then a plane of the conductive material <NUM> is formed on the first plane of the second insulative material <NUM>. A layer of the first insulative material <NUM> is deposited on the substrate <NUM>. The conductive material <NUM> may be a layer of conductive carbon or other conductive layer compatible with active materials. The conductive material <NUM> may include conductive layers separated by active material through a protective barrier. The conductive material <NUM> may be configured to function as at least one word line plate. The conductive material <NUM> and the insulative material <NUM> form a plurality of layers, such as alternating layers.

Additional planes of the second insulative material <NUM> are formed on the conductive material <NUM> in an alternating manner as illustrated in <FIG>. The second insulative material <NUM> is a dielectric material, such as a dielectric film or layer. The second insulative material <NUM> and the substrate <NUM> may be the same type of insulative material.

Each respective one of the plurality of planes of the conductive material <NUM> is at (e.g., form) a different level of the 3D memory array <NUM>-b. Individual planes of material that form memory cells may be referred to as a deck of the 3D memory array <NUM>-b. The conductive material <NUM> may comprise (e.g., be formed of) a metallic (or semi-metallic) material or a semiconductor material such as a doped polysilicon material, among others. The conductive material <NUM> may be a plane of conductive carbon.

Six planes of the conductive material <NUM> and seven planes of the second insulative material <NUM> are shown in <FIG>. The seventh plane of the second insulative material <NUM> may be a topmost layer of the 3D memory array <NUM>-b. The quantity of planes of the conductive material <NUM> and the second insulative material <NUM> are not limited to the quantities illustrated in <FIG>. The conductive material <NUM> and the second insulative material <NUM> may be arranged into more than six decks or less than six decks.

<FIG> illustrates various views of 3D memory arrays <NUM>-c, <NUM>-d, <NUM>-e, and <NUM>-f during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples or embodiments of the invention as disclosed herein. Specifically, in <FIG>, a process of forming even and odd word line planes is shown.

<FIG> illustrates a top view of a 3D memory array <NUM>-c, which may be a memory array <NUM>-b illustrated in <FIG> after a trench <NUM> is formed. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-d along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-e along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-f along section line A-A' during a process step subsequent to what is illustrated in <FIG> illustrates a top view of a 3D memory array <NUM>-f of section line B-B' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrate a series of steps or processes that may be performed to form a stacked memory device.

<FIG> illustrates forming the trench <NUM> through the alternating planes of conductive material <NUM> (shown in <FIG>) and the second insulative material <NUM> (shown in <FIG>) of memory array <NUM>-c. The trench <NUM> exposes the substrate <NUM> (previously shown in <FIG>) and the conductive contacts <NUM> (previously shown in <FIG>) at the bottom of the trench <NUM>.

The trench <NUM> may be etched from top to bottom and etched in a serpentine-shape. For instance, the trench <NUM> may pass over a row of the conductive contacts <NUM> in a first direction (e.g., from left to right) and then pass over an adjacent row of the conductive contacts <NUM> in a second direction that is opposite to the first direction (e.g., from right to left). With reference to the example of <FIG>, the trench <NUM> passes over a first row of the conductive contacts <NUM> from left to right, then "turns" and passes over the next (second) row of conductive contacts <NUM> (adjacent to the first row) from right to left. The trench <NUM> "turns" again and passes over the next (third) row of conductive contacts <NUM> (adjacent to the second row) from left to right. The trench <NUM> "turns" again and passes over the next (fourth) row of conductive contacts <NUM> (adjacent to the third row) from right to left and then "turns" again and passes over the next (fifth) row of conductive contacts <NUM> at the bottom of <FIG> (adjacent to the fourth row) from left to right.

The trench <NUM> bifurcates each plane of the conductive material <NUM> into at least two portions: a first portion <NUM> and a second portion <NUM>. Each portion of a plane of the conductive material <NUM> may be a different access line (e.g., even word line or odd word line) of a deck. The first portion <NUM> may be a first access line of a deck of the 3D memory array <NUM>-c and the second portion <NUM> may be a second access line of the same deck of the 3D memory array <NUM>-c. The extension of the fingers forming the even or odd planes may be defined based on the resistivity of an electrode used and by the level of current delivery requested. Specifically, the depth of the recesses is defined depending on the thickness desired for the memory cell.

<FIG> illustrates forming a plurality of recesses <NUM> in the conductive material <NUM> in each of the planes of memory array <NUM>-d. For example, a selective etching operation may be performed to form the plurality of recesses <NUM> in sidewalls <NUM> and <NUM> of the trench <NUM> in an isotropic way. The trench <NUM> includes a first sidewall <NUM> spaced apart from a second sidewall <NUM>, where a first portion <NUM> of the first sidewall <NUM> formed by the first insulative material <NUM> is spaced apart from a first portion <NUM> of the second sidewall <NUM> formed by the first insulative material <NUM> by a first distance. A second portion <NUM> of the first sidewall <NUM> formed by the first conductive material <NUM> is spaced apart from a second portion <NUM> of the second sidewall <NUM> formed by the first conductive material <NUM> by a second distance greater than the first distance. Portions of sidewalls <NUM> and <NUM> of the trench <NUM> formed by the first conductive material <NUM> are recessed relative to portions of the sidewalls <NUM> and <NUM> of the trench <NUM> formed by the first insulative material <NUM>.

The etching operations may include one or more vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process) or combinations thereof. For example, a vertical etching process may be performed to vertically etch the trench <NUM> and a horizontal etching process may be used to form at least one recess <NUM> in at least one conductive material <NUM>. The etching parameters may be selected such that the conductive material <NUM>, for example, is etched faster than the second insulative material <NUM>.

<FIG> illustrates forming a conformal material <NUM> (e.g., a sacrificial material or sacrificial layer). The conformal material <NUM> is deposited into the trench <NUM> of memory array <NUM>-e. The conformal material <NUM> is formed in the recesses <NUM> (shown in <FIG>) by conformally depositing the conformal material <NUM>. The conformal material <NUM> contacts a first sidewall <NUM>, a second sidewall <NUM>, and a bottom wall <NUM> of trench <NUM>. Although <FIG> shows the conformal material <NUM> formed on the sidewalls of the trench <NUM> (e.g., on the surfaces of the second insulative material <NUM> and the conductive materials <NUM> in different layers facing into the trench <NUM>) during formation of the conformal material <NUM> in the plurality of recesses <NUM>, examples are not so limited. For example, the conformal material <NUM> may be confined to only the plurality of recesses <NUM> in the conductive materials <NUM> in different layers in some cases. In some cases, the conformal material <NUM> may be referred to as a conformal layer or a sacrificial layer.

In some cases, an etching operation may be performed subsequent to forming the conformal material <NUM>. In the etching operation, the conformal material <NUM> may be etched to form an opening or trench <NUM>. The etch operation may result in the surfaces of the conformal material <NUM> (e.g., the surfaces facing the trench <NUM>) being spaced apart from the surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>). In some cases, the etch operation may result in the surfaces of the conformal material <NUM> (e.g., the surfaces facing the trench <NUM>) being approximately coplanar with surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>), and thereby forming a continuous sidewall of trench. The etching operations described herein may be vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process). For example, a vertical etching process may be performed to vertically etch the trench <NUM> and a horizontal etching process may be used to form at least one recess in the first conductive material <NUM>.

<FIG> illustrates depositing a dielectric material <NUM> in the trench <NUM> on top of the conformal material <NUM> of the memory array <NUM>-f. The dielectric material <NUM> contacts the conformal material <NUM>. The dielectric material <NUM> and the conformal material <NUM> cooperate to fill the trench <NUM>. In some cases, the dielectric material <NUM> may be an example of an insulative material. In some examples, the conformal material <NUM> may be etched back selectively to form a co-planar surface with the dielectric material <NUM>. The depth of the recession may be defined depending on a desired thickness.

<FIG> illustrates a top view of an example 3D memory array <NUM>-f after the dielectric material <NUM> is deposited (as shown in <FIG>). In <FIG>, the conformal material <NUM> formed in the trench <NUM> and the dielectric material <NUM> bifurcate each plane of the conductive material <NUM> into a first portion <NUM> and a second portion <NUM>.

<FIG> illustrates various views of 3D memory arrays <NUM>-g, <NUM>-h, <NUM>-i, and <NUM>-j, during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples and embodiments of the invention as disclosed herein. Specifically, <FIG> illustrate processes for forming memory cells in the memory array <NUM>-f illustrated in <FIG>.

<FIG> illustrates a top view of a memory array <NUM>-g, which may be a memory array <NUM>-f illustrated in <FIG> after formation of openings <NUM>. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-h along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-i along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-j along section line A-A' during a process step subsequent to what is illustrated in <FIG> illustrates a top view of the 3D memory array <NUM>-j of section line B-B' during a process step subsequent to what is illustrated in <FIG>.

<FIG> illustrates a top view through any one of the planes of the conductive material <NUM> of the memory array <NUM>-g. A plurality of openings <NUM> in trench <NUM> are formed by etching away a portion of the dielectric material <NUM> and/or the conformal material <NUM>. The openings <NUM> are intended to be positioned in alignment with the plurality of conductive contacts <NUM> so that forming the openings <NUM> exposes at least a portion of a plurality of conductive contacts <NUM> (shown in <FIG>) extending through the substrate <NUM> (shown in <FIG>). The etching process may be a vertical etching process. The etching operation does not etch away all portions of the conformal material <NUM>, for example, where the plurality of openings <NUM> are not formed.

<FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-h in accordance with an example or embodiment of the invention. As shown in <FIG>, a plurality of recesses <NUM> is formed in the conductive material <NUM> in each of the planes. For example, a selective etching operation may be performed to form the plurality of recesses <NUM> in a full or partially isotropic way. The etching chemistry may be selected to selectively reach a conductive material <NUM>. The conductive contacts <NUM> may be exposed by forming the openings <NUM> in in the trench <NUM>.

<FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-i in accordance with an example or embodiment of the invention. As shown in <FIG>, a storage element material <NUM> is formed in the plurality of recesses <NUM> by conformally depositing the storage element material <NUM> into the trench <NUM>. The storage element material <NUM> is deposited to contact sidewalls <NUM> and <NUM> and a bottom wall <NUM> of the trench <NUM> exposed by the etching of the conformal material <NUM>. When the storage element material <NUM> contacts the bottom wall <NUM> of the trench <NUM>, the storage element material <NUM> covers the exposed conductive contacts <NUM>.

The storage element material <NUM> is a chalcogenide material, such as a chalcogenide alloy and/or glass, that may serve as a self-selecting storage element material (e.g., a material that may serve as both a select device and a storage element). The storage element material <NUM> may be responsive to an applied voltage, such as a program pulse. For an applied voltage that is less than a threshold voltage, the storage element material <NUM> may remain in an electrically nonconductive state (e.g., an "off" state). Alternatively, responsive to an applied voltage that is greater than the threshold voltage, the storage element material <NUM> may enter an electrically conductive state (e.g., an "on" state).

The storage element material <NUM> may be programmed to a target state by applying a pulse (e.g., a programming pulse) that satisfies a programming threshold. The amplitude, shape, or other characteristics of the programming pulse may be configured to cause the storage element material <NUM> to exhibit the target state. For example, after applying the programming pulse, the ions of the storage element material <NUM> may be redistributed throughout the storage element, thereby altering a resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the storage element material <NUM> may vary based on applying the programming pulse.

The state stored by the storage element material <NUM> may be sensed, detected, or read by applying read pulse to the storage element material <NUM>. The amplitude, shape, or other characteristics of the read pulse may be configured to allow a sense component to determine what state is stored on the storage element material <NUM>. For example, in some cases, the amplitude of the read pulse is configured to be at a level that the storage element material <NUM> will be in an "on" state (e.g., current is conducted through the material) for a first state but will be in an "off" state (e.g., little to no current is conducted through the material) for a second state.

In some cases, the polarity of the pulse (whether programming or read) applied to the storage element material <NUM> may affect the outcomes of the operation being performed. For example, if the storage element material <NUM> stores a first state, a read pulse of a first polarity may result in the storage element material <NUM> exhibiting an "on" state while a read pulse of a second polarity may result in the storage element material <NUM> exhibiting an "off" state. This may occur because of the asymmetrical distributions of ions or other material in the storage element material <NUM> when it is storing a state. Similar principles apply to programming pulses and other pulses or voltages.

Examples of chalcogenide materials that may serve as the storage element material <NUM> include indium(In)-antimony(Sb)-tellurium(Te) (IST) materials, such as In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, etc., and germanium(Ge)- antimony(Sb)-tellurium(Te) (GST) materials, such as Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, or etc., among other chalcogenide materials, including, for instance, alloys that do not change phase during the operation (e.g., selenium-based chalcogenide alloys). Further, the chalcogenide material may include minor concentrations of other dopant materials. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), Sulphur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. In some examples, the chalcogenide material may be a chalcogenide glass or amorphous chalcogenide material. In some example, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG-alloy. In some examples, SAG-alloy may include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, the chalcogenide glass may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms. In some examples, conductivity may be controlled through doping using various chemical species. For example, doping may include incorporating a Group <NUM> (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group <NUM> (tin (Sn), carbon (C), silicon (Si), etc.) element into the composition.

<FIG> illustrates a cross-sectional view of a 3D memory array <NUM>-j in accordance with an example or embodiment of the invention. An etching operation is performed subsequent to forming the storage element material <NUM> so that surfaces of the storage element material <NUM> (e.g., the surfaces facing into the trench <NUM>) are approximately coplanar with surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>) as illustrated in <FIG>. The etching of the storage element material <NUM> may form a continuous sidewall and remove the top layer <NUM> (shown in <FIG>) of the storage element material <NUM>, whereby cells of the storage element material <NUM> are formed in the recesses only. In each recess, each cell of the storage element material <NUM> contacts a single conductive material <NUM> (e.g., a single conductive material <NUM> located adjacent to the cell of the storage element material <NUM>) and at least two dielectric layers (e.g. a top dielectric layer and a bottom dielectric layer located on top of the cell of the storage element material <NUM> and on bottom of the cell of the storage element material <NUM>), as shown in <FIG>. The etching of the storage element material <NUM> provides a configuration in which the storage element material cells <NUM> are separated from one another. The etching of the storage element material <NUM> may also expose the conductive contacts <NUM> in the substrate <NUM>. According to the present invention, portions of conformal material are located on either side of the cell of the storage element material <NUM> (as shown in <FIG>).

<FIG> illustrates a top view of a 3D memory array <NUM>-j in accordance with an example or embodiment of the invention. As illustrated in <FIG>, the conformal material <NUM> and the storage element material <NUM> formed in the trench <NUM> bifurcate each plane of the conductive material <NUM> into a first portion <NUM> and a second portion <NUM>. Each portion of a plane may be an example of a word line plate.

<FIG> illustrates various views of 3D memory arrays <NUM>-k,<NUM>-l, and <NUM>-m during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples or embodiments of the invention as disclosed herein. Specifically, <FIG> illustrate processes of filling the openings <NUM> after the recessed self-selecting memory cells are formed.

<FIG> illustrates a top view of a memory array <NUM>-k, which may be a memory array <NUM>-j illustrated in <FIG> after formation of recessed self-selecting memory cells. <FIG> is a top view of a memory array <NUM>-l through any one of the planes of the conductive material <NUM> illustrated in <FIG> during a processing step that is subsequent to what is illustrated in <FIG> illustrates a cross-sectional view a 3D memory array <NUM>-m along section line A-A' during a processing step that is subsequent to what is illustrated in <FIG>.

<FIG> illustrates a top view of a memory array <NUM>-k where a barrier material <NUM> is deposited into the openings <NUM> of the trench <NUM>. In some implementations, the barrier material <NUM> contacts at least one portion of the first insulative material <NUM> (not shown), the second insulative material <NUM> (not shown), and the storage element material <NUM>. In some examples, the barrier material <NUM> is compatible with an active material. In some examples, the barrier material <NUM> may be a conductive material, or a barrier layer with a conductive material. The barrier layer may comprise aluminum oxide, for example. In some examples, an etching operation may be performed to make room for conductive material to be deposited into the trench <NUM>. In some cases, the barrier material <NUM> may be referred to as a barrier layer.

<FIG> illustrates a top view of a memory array <NUM>-l where a conductive material <NUM> is deposited into the openings <NUM> of the trench <NUM>. A conductive material <NUM> is deposited in the opening <NUM> to form a conductive pillar <NUM>. The conductive pillar <NUM> includes the barrier material <NUM> and the conductive material <NUM>. The conductive pillar <NUM> is formed in contact with the storage element material <NUM> on the sidewalls <NUM> and <NUM> (shown in <FIG>) of the trench <NUM>. The conductive pillar <NUM> comprises the same material as the conductive material <NUM>. The conductive pillar <NUM> may be a digit line. The conductive pillar <NUM> may be a cylinder. Although <FIG> illustrates the conductive pillar <NUM> as a solid pillar, in some examples the conductive pillar <NUM> may be a hollow cylinder or toroidal (e.g., a tube). The conductive pillar <NUM> may comprise a metallic (or semi-metallic) material or a semiconductor material such as a doped polysilicon material, among others. However, other metallic, semi-metallic, or semiconductor materials may be used.

The conductive pillars <NUM> formed in each respective one of the plurality of openings <NUM> are arranged to extend substantially orthogonal to the alternating planes of the conductive material <NUM> and the second insulative material <NUM> (not shown). The storage element material <NUM> and the conductive pillar <NUM> formed in each respective one of the plurality of openings <NUM> are formed in a substantially square shape. However, examples and embodiments of the invention of the present disclosure are not limited to exact or quasi-exact square shapes. For instance, the storage element material <NUM> and the conductive pillar <NUM> may be formed in any shape, including circles or oval shapes, for instance.

<FIG> illustrates a side view of a 3D memory array <NUM>-m in accordance with an example or embodiment of the invention. As illustrated in <FIG>, a capping layer <NUM> (e.g., an insulative material, such as a dielectric layer) is deposited to cap the conductive pillars <NUM> of memory array <NUM>-l.

The memory array <NUM>-m may include a plurality of vertical stacks. Each respective stack may include the conductive pillar <NUM>, a conductive contact <NUM> coupled to the conductive pillar <NUM>, the storage element material <NUM> formed in contact with the first portion <NUM> and the conductive pillar <NUM>, and the storage element material <NUM> formed in contact with the second portion <NUM> and the conductive pillar <NUM>.

The conductive pillar <NUM> may be in contact with the conductive contact <NUM> and the first insulative material <NUM>, and in contact with the storage element material <NUM> formed in the recesses <NUM>. In some cases, the storage element material <NUM> formed in each respective recess <NUM> is formed partially (e.g., not completely) around the conductive pillar <NUM>.

Although not shown in <FIG> for clarity and so as not to obscure examples or embodiments of the invention, other materials may be formed before, after, and/or between the storage element material <NUM>, and/or the conductive pillar <NUM>, for example, to form adhesion layers or barriers against interdiffusion of materials and/or to mitigate composition mixing.

<FIG> illustrates various views of 3D memory arrays <NUM>-a and <NUM>-b, which may be 3D memory arrays <NUM>-a through <NUM>-m processed in <FIG>, in accordance with examples or embodiments of the invention as disclosed herein. The memory arrays <NUM>-a and <NUM>-b include similar features as memory array <NUM> described with reference to <FIG>. A plurality of openings <NUM> is formed through the alternating planes of the conductive material <NUM> and the second insulative material <NUM> (not shown), and the dielectric material <NUM> in the trench <NUM>. As shown, the diameter of the plurality of openings <NUM> is approximately the same as the width of the trench <NUM>. The diameter of the plurality of openings <NUM> may be greater than the width of the trench <NUM>.

Each of the plurality of openings <NUM> may be approximately concentric with a different respective one of the conductive contacts <NUM>. As shown in <FIG>, the pillars <NUM> are circular and formed over and coupled to the plurality of contacts in geometric pattern in respective openings <NUM>. As illustrated in <FIG>, the openings <NUM> may be square.

The plurality of openings <NUM> has a staggered (e.g., hexagonal) arrangement of the conductive contacts <NUM> (not shown). For example, a respective one of the plurality of conductive contacts <NUM> may be surrounded by six other conductive contacts <NUM>.

A staggered pattern refers to any pattern where positions of objects (e.g., contacts, openings, or pillars) in a first row are offset from positions of objects (e.g., contacts, openings, or pillars) in a second row adjacent to the first row in a given direction. For example, a staggered pattern may have objects (e.g., contacts, openings, or pillars) adjacent to one another in the x-direction (e.g., rows), but not in the y-direction (e.g., columns). For instance, as illustrated in <FIG>, the plurality of conductive contacts <NUM> are adjacent to each other and in line with each other in an x-direction. However, the plurality of conductive contacts <NUM> are not adjacent to each other in the y-direction. The plurality of conductive contacts <NUM> are in line with each other in the x-direction and the plurality of conductive contacts <NUM> alternate (e.g., skip) rows in the y-direction. Although, <FIG> show spacing that is approximately the same between the conductive contacts <NUM> throughout the substrate <NUM>, examples or embodiments of the invention are not so limited. For example, the spacing between the conductive contacts <NUM> may vary throughout the substrate <NUM>.

<FIG> shows that the 3D memory array includes a plurality of storage element materials <NUM>, each comprising a chalcogenide material positioned between at least one of the word line plates, at least one circular pillar <NUM>, and at least one dielectric material <NUM>. Depending on the decoding optimization, the pillars <NUM> may be coupled to a plurality of selectors positioned at a top, a bottom, or both a top and a bottom (e.g., below or above the plurality of word line plates) of the 3D memory array <NUM>.

<FIG> illustrates various views of 3D memory arrays <NUM>, which may be 3D memory arrays <NUM>-a through <NUM>-m processed in <FIG>, in accordance with examples or embodiments of the invention as disclosed herein. A plurality of openings <NUM> is formed through the alternating planes of the conductive material <NUM> and the second insulative material <NUM>, and the dielectric material <NUM> in the trench <NUM>. As shown, the diameter of the plurality of openings <NUM> is approximately the same as the width of the trench <NUM>. The diameter of the plurality of openings <NUM> may be greater than the width of the trench <NUM>.

Each of the plurality of openings <NUM> may be approximately concentric with a different respective one of the conductive contacts <NUM>. As shown in <FIG>, the pillars <NUM> are rectangular oblique and formed over and coupled to the plurality of contacts in geometric pattern in respective openings <NUM>.

The plurality of openings <NUM> has a staggered (e.g., hexagonal) arrangement of the conductive contacts <NUM>. For example, a respective one of the plurality of conductive contacts <NUM> may be surrounded by six other conductive contacts <NUM>.

As used herein, "a staggered pattern" refers to a plurality of conductive contacts that are adjacent to one another one direction but not in another direction. For example, a staggered pattern may have objects (e.g., contacts, openings, or pillars) adjacent to one another in the x-direction (e.g., rows), but not in the y-direction (e.g., columns).

For instance, as illustrated in <FIG>, the plurality of conductive contacts <NUM> are adjacent to each other and in line with each other in an x-direction. However, the plurality of conductive contacts <NUM> are not adjacent to each other in the y-direction. The plurality of conductive contacts <NUM> are in line with each other in the x-direction and the plurality of conductive contacts <NUM> alternate (e.g., skip) rows in the y-direction. Although, <FIG> show a spacing that is approximately the same between the conductive contacts <NUM>-a throughout the substrate <NUM>, examples or embodiments of the invention in accordance with the present disclosure are not so limited. For example, the spacing between the conductive contacts <NUM>-a may vary throughout the substrate <NUM>.

<FIG> shows that the 3D memory array includes a plurality of storage element materials <NUM>, each comprising a chalcogenide material positioned between at least one of the word line plates, at least one rectangular oblique pillar <NUM>, and at least one dielectric material <NUM>.

Depending on the decoding optimization, the pillars <NUM> may be coupled to a plurality of selectors positioned at a top, a bottom, or both a top and a bottom (e.g., below or above the plurality of word line plates) of the 3D memory arrays <NUM>. Spatially related terms, including but not limited to, "top," "bottom," "lower," "upper," "beneath," "below," "above," etc., if used herein, are utilized for ease of description to describe spatial relationships of an element(s) to another. Such spatially related terms encompass different orientations of the device in addition to the particular orientations depicted in the figures and described herein. For example, if a structure depicted in the figures is turned over or flipped over, portions previously described as below or beneath other elements would then be above or over those other elements.

<FIG> shows a flowchart illustrating a method <NUM> that supports architecture of three-dimensional memory device and methods regarding the same in accordance with aspects of the present disclosure. The operations of method <NUM> may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At <NUM>, the method <NUM> includes forming a trench through a first dielectric layer, a first conductive layer, and a second dielectric layer, the trench exposing a substrate and dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes depositing a conformal material that contacts a first sidewall and a second sidewall of the trench. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming an opening over a contact extending through the substrate by etching a portion of the conformal material. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes depositing, into the opening, a chalcogenide material configured to store information in contact with a sidewall and a bottom wall of the opening exposed by the etching. The operations of <NUM> may be performed according to the methods described herein.

In some examples, an apparatus as described herein may perform a method or methods, such as the method <NUM>. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a trench through a first dielectric layer, a first conductive layer, and a second dielectric layer, the trench exposing a substrate and dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver, depositing a conformal material that contacts a first sidewall and a second sidewall of the trench, forming an opening over a contact extending through the substrate by etching a portion of the conformal material, and depositing, into the opening, a chalcogenide material configured to store information in contact with a sidewall and a bottom wall of the opening exposed by the etching.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for depositing a dielectric material in the trench that contacts the conformal material, where forming the opening includes etching a portion of the dielectric material. Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming a set of contacts extending through the substrate, the set of contacts may be associated with a set of digit lines, forming the first dielectric layer on the substrate, forming the first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate, and forming the second dielectric layer on the first conductive layer, where forming the trench may be based on forming the second dielectric layer.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for etching a portion of the chalcogenide material to form a continuous sidewall of the opening, and depositing a barrier material into the opening that contacts the continuous sidewall of the opening. In some examples of the method <NUM> and the apparatus described herein, the chalcogenide material includes a first wall contacting the first conductive layer, a second wall contacting the first dielectric layer, a third wall contacting the second dielectric layer, and a fourth wall contacting the barrier material. In some examples of the method <NUM> and the apparatus described herein, the barrier material contacts at least one portion of the first dielectric layer, the second dielectric layer, and the chalcogenide material.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for etching the barrier material to expose the contact, and depositing a conductive material into the opening that contacts the barrier material and the contact. Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming a second dielectric material over the second dielectric layer and the conductive material.

In some examples of the method <NUM> and the apparatus described herein, the conductive material may be configured as a digit line. In some examples of the method <NUM> and the apparatus described herein, forming the trench through the first dielectric layer may include operations, features, means, or instructions for performing a vertical etching process to vertically etch the trench, and performing a horizontal etching process after the vertical etching process to form at least one recess in the first conductive layer. In some examples of the method <NUM> and the apparatus described herein, the vertical etching process includes an anisotropic etching process or a dry etching process or a combination thereof. In some examples of the method <NUM> and the apparatus described herein, the horizontal etching process includes an isotropic etching process.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming a set of openings over a set of contacts extending through the substrate, and filling the set of openings with a barrier material. Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming the trench exposes at least a portion of a set of contacts extending through the substrate.

In some examples of the method <NUM> and the apparatus described herein, the trench extends through the first conductive layer in a serpentine shape. In some examples of the method <NUM> and the apparatus described herein, the trench including the first sidewall spaced apart from the second sidewall, where a first portion of the first sidewall formed by the first dielectric layer may be spaced apart from a first portion of the second sidewall formed by the first dielectric layer by a first distance, and a second portion of the first sidewall formed by the first conductive layer may be spaced apart from a second portion of the second sidewall formed by the first conductive layer by a second distance greater than the first distance.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for portions of sidewalls of the trench formed by the first conductive layer may be recessed relative to portions of sidewalls of the trench formed by the first dielectric layer. In some examples of the method <NUM> and the apparatus described herein, the chalcogenide material includes a storage element for a self-selecting memory cell.

Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming a second conductive layer on the second dielectric layer, the second conductive layer configured as at least one word line plate, and forming a third dielectric layer on the second conductive layer, where forming the trench may be based on forming the third dielectric layer. In some examples of the method <NUM> and the apparatus described herein, an array of memory cells associated with the first conductive layer and the second conductive layer includes a three-dimensional array of memory cells.

At <NUM>, the method <NUM> includes forming a set of contacts extending through the substrate, the set of contacts is associated with a set of digit lines. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming the first dielectric layer on the substrate. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming the first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming the second dielectric layer on the first conductive layer, where forming the trench is based on forming the second dielectric layer. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes etching a portion of the chalcogenide material to form a continuous sidewall of the opening. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes depositing a barrier material into the opening that contacts the continuous sidewall of the opening. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming a set of contacts associated with a set of digit lines extending through a substrate. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming a first dielectric layer on the substrate. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming a first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming a second dielectric layer on the first conductive layer. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming at least one trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the at least one trench dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes depositing a conformal material to contact a first sidewall, a second sidewall, and a bottom wall of each of the set of trenches. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes forming a circular opening in each of the set of trenches over a contact of the set of contacts by etching a portion of the conformal material. The operations of <NUM> may be performed according to the methods described herein.

At <NUM>, the method <NUM> includes depositing, into the circular opening, a chalcogenide material that contacts surfaces of the first sidewall, the second sidewall, and the bottom wall in each of the set of trenches, the chalcogenide material configured to store information. The operations of <NUM> may be performed according to the methods described herein.

In some examples, an apparatus as described herein may perform a method or methods, such as the method <NUM>. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a set of contacts associated with a set of digit lines extending through a substrate, forming a first dielectric layer on the substrate, forming a first conductive layer on the first dielectric layer, the first conductive layer configured as at least one word line plate, forming a second dielectric layer on the first conductive layer, forming at least one trench through the first dielectric layer, the first conductive layer, and the second dielectric layer, the at least one trench dividing the first conductive layer into a first portion associated with a first word line driver and a second portion associated with a second word line driver, depositing a conformal material to contact a first sidewall, a second sidewall, and a bottom wall of each of the set of trenches, forming a circular opening in each of the set of trenches over a contact of the set of contacts by etching a portion of the conformal material, and depositing, into the circular opening, a chalcogenide material that contacts surfaces of the first sidewall, the second sidewall, and the bottom wall in each of a set of trenches, the chalcogenide material configured to store information. Some examples of the method <NUM> and the apparatus described herein may further include operations, features, means, or instructions for forming a set of pillars over the set of contacts in a hexagonal pattern, and coupling the set of pillars with a set of selectors positioned in at least at one of a top and a bottom of an apparatus.

Furthermore, portions from two or more of the methods may be combined.

As used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly coupled with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that may, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term "coupling" refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. When a component, such as a controller, couples' other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term "isolated" refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The term "layer" used herein refers to a stratum or sheet of a geometrical structure. each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration. Those skilled in the art will, however, recognize that the layers are three-dimensional in nature.

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to achieve the advantages of the characteristic.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory array.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a fieldeffect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavilydoped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are signals), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

" The detailed description includes specific details to providing an understanding of the described techniques. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

For example, due to the nature of software, functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these.

Claim 1:
A method, comprising:
forming a trench (<NUM>) through a first dielectric layer (<NUM>), a first conductive layer (<NUM>), and a second dielectric layer (<NUM>), the trench (<NUM>) exposing a semiconductor substrate (<NUM>) and dividing the first conductive layer (<NUM>) into a first portion (<NUM>) associated with a first word line driver and a second portion (<NUM>) associated with a second word line driver;
depositing a conformal material (<NUM>) that contacts a first sidewall (<NUM>) and a second sidewall (<NUM>) of the trench (<NUM>) such that the conformal material is formed in a plurality of recesses (<NUM>) in the first conductive layer;
forming an opening (<NUM>) over a contact (<NUM>) extending through the semiconductor substrate (<NUM>) by etching a portion of the conformal material (<NUM>); and
depositing, into the opening, a chalcogenide material (<NUM>) configured to store information, the chalcogenide material in contact with a sidewall (<NUM>, <NUM>) and a bottom wall (<NUM>) of the opening (<NUM>) and deposited so as to fill the recesses exposed by the etching, such that the conformal material fills the recesses on either side of the chalcogenide material that are not exposed by the etching.