Patent Description:
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like.

Information is stored by programming different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic <NUM> or a logic <NUM>. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and others. Memory devices may be volatile or non-volatile. <CIT> relates to a non-volatile memory using PCM cells in a 3D vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in recessed regions of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining the word line recess in which the PCM material is placed improves stability of the resistance state of the memory cells. <CIT> relates to a 3D RRAM array which is segmented into blocks. A hook-up region between two blocks comprises staggered contact plugs for connecting stacked word line combs. <CIT> relates to a three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned at different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Improving memory devices, generally, may include increasing memory cell density, increasing read/write speed, increasing reliability, increasing data retention, reducing power.

consumption, or reducing manufacturing costs, among other metrics. Solutions for saving space in the memory array, increasing the memory cell density, or decreasing overall power usage of the memory array with three-dimensional vertical architecture may be desired.

The present disclosure relates to three-dimensional (3D) vertical self-selecting memory arrays with an increased density of memory cells and a reduced power consumption, and methods of manufacturing the same. The memory arrays may include an arrangement of conductive contacts and openings through alternative layers of conductive materials and insulative material that may decrease the spacing between the memory cells while maintaining a dielectric thickness to sustain the voltage to be applied to the memory array.

In some examples, a 3D memory array may include a substrate with a plurality of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulative material (e.g., a dielectric material) formed on the substrate. A plurality of planes of a conductive material may be separated from one another by a second insulative material (e.g., a dielectric material) and formed on the substrate material. The planes of conductive material may be examples of word lines.

During manufacturing of such a memory array, a trench may be formed in a shape that separates odd and even word line planes to create "comb" structures (e.g., structures that look like a tool with fingers and space between the fingers). The trench may have any geometric configuration and include odd and even groups of fingers of the comb facing one another at a fixed distance. In some examples, the trench may be formed in a serpentine shape. The trench may divide each plane of conductive material into two sections or two plates. Each place of conductive material may be an example of a word line plate. In some examples, inside the trench, the planes of the conductive material may be etched in such a way that the dielectric materials and the conductive materials form a plurality of recesses, where each recess may be configured to receive a storage element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) may be deposited in the trench and, in some cases, the sacrificial layer fills the recesses. An insulative material may be deposited in the trench on top of the sacrificial layer. The sacrificial layer and the insulative layer may form a serpentine shape. In some examples, other geometric configurations of the trench are contemplated. In some examples, at least one particular separation trench may be formed to be filled with an insulation material (e.g., a dielectric material), so that the memory array is divided into several portions, each of which includes a certain number of digit lines which will be formed later, and word lines at one side of the separation trench are separated from word lines at the other side of the separation trench electrically.

Portions of the sacrificial layer and the insulative may be removed to form openings. The openings may expose portions of the substrate, the plurality of conductive contacts, and portions of the conductive materials and dielectric materials. A storage element material (e.g., the chalcogenide material) may be deposited in the openings. The storage element material may fill the recesses formed by the dielectric materials and the conductive materials. The storage element material may be partially removed from the openings such that only the storage element materials in the recesses remain.

Conductive pillars may be formed in the openings that include the storage element materials in the recesses. The conductive pillars may be examples of digit lines. The conductive pillars may be arranged to extend (e.g., substantially perpendicular) to the planes of the conductive material and the substrate. Each conductive pillar may be coupled with a different conductive contact. The pillars may be formed of a barrier material and a conductive material.

Such configurations of a memory array and the methods of manufacturing may allow a higher-density of memory cells and a reduced power consumption relative to previous solutions. Each memory cell (e.g., storage element material) may be recessed inside opposite sides of the conductive pillar to ensure the cell isolation. Such a configuration may allow for a tighter control of cell thickness and dimension with respect to some previous solutions. Each plane of conductive material that intersects the conductive pillar may form two memory cells addressed by a first word line plate in the plane and a second word line plate in the plane. Each conductive pillar may be decoded by a transistor positioned at the bottom or top of the memory array. The transistor may be an example of a digit line selector formed in a regular matrix.

Features of the disclosure are initially described in the context of a memory array as described with reference to <FIG>. Features of the disclosure are described in the context of different views of example 3D memory arrays during manufacturing steps as described with reference to <FIG>. These and other features of the disclosure are further illustrated by and described with reference to flowcharts that relate to vertical 3D memory array architecture as described with references to <FIG> and <FIG>. These and other features of the disclosure are further described in the context of an example 3D memory device with reference to <FIG>.

<FIG> illustrates an example of a 3D memory array <NUM> in accordance with aspects of the present disclosure. Memory array <NUM> may include a first array or deck <NUM> of memory cells that is positioned above a substrate <NUM> and a second array or deck <NUM> of memory cells on top of the first array or deck <NUM>.

Memory array <NUM> may include word lines <NUM> and digit lines <NUM>. Memory cells of the first deck <NUM> and the second deck <NUM> each may have one or more self-selecting memory cells. Although some elements included in <FIG> are labeled with a numeric indicator, other corresponding elements are not labeled, though they are the same or would be understood to be similar.

A stack of memory cells may include a first dielectric material <NUM>, a storage element material <NUM> (e.g., chalcogenide material), a second dielectric material <NUM>, a storage element material <NUM> (e.g., chalcogenide material), and a third dielectric material <NUM>. The self-selecting memory cells of the first deck <NUM> and second deck <NUM> may, in some examples, have common conductive lines such that corresponding self-selecting memory cells of each deck <NUM> and <NUM> may share digit lines <NUM> or word lines <NUM>.

In some examples, a memory cell may be programmed by providing an electric pulse to the cell, which may include a memory storage element. The pulse may be provided via a first access line (e.g., word line <NUM>) or a second access line (e.g., digit line <NUM>), or a combination thereof. In some cases, upon providing the pulse, ions may migrate within the memory storage element, depending on the polarity of the memory cell. Thus, a concentration of ions relative to the first side or the second side of the memory storage element may be based at least in part on a polarity of a voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements may cause ions to be more crowded at portions of an element having more area. Certain portions of the memory storage element may have a higher resistivity and thus may give rise to a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of the self-selecting memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. This disclosure also includes other examples of mechanisms of the self-selecting memory cell for achieving the results described herein.

The architecture of memory array <NUM> may be referred to as a cross-point architecture, in some cases, in which a memory cell is formed at a topological cross-point between a word line <NUM> and a digit line <NUM>. Such a cross-point architecture may offer relatively high-density data storage with lower production costs compared to other memory architectures. For example, the cross-point architecture may have memory cells with a reduced area and, resultantly, an increased memory cell density compared to other architectures.

While the example of <FIG> shows two memory decks <NUM> and <NUM>, other configurations are possible. In some examples, a single memory deck of self-selecting memory cells may be constructed above a substrate <NUM>, which may be referred to as a two-dimensional memory. In some examples, a three or four memory decks of memory cells may be configured in a similar manner in a three-dimensional cross point architecture.

The memory array <NUM> may include a substrate <NUM> with a plurality of contacts arranged in a grid or staggered pattern. In some cases, the plurality of contacts may extend through the substrate and couple with an access line of the memory array <NUM>. The memory array <NUM> may include a plurality of planes of a conductive material separated from one another by a second insulative material formed on the first insulative material on the substrate material. Each of the plurality of planes of the conductive material may include a plurality of recesses formed therein. The plurality of planes, for example, word line plates, may be obtained by a replacement process by using a sacrificial layer (e.g., a conformal layer) for etching during a stack deposition processing step, removing the conformal layer after cell definition and replacing the conformal layer with a more conductive material.

An insulative material may be formed in a serpentine shape through the second insulative material and the conductive material. A plurality of conductive pillars may be arranged in openings to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate. Each respective one of the plurality of conductive pillars may be coupled to a different one of the conductive contacts.

In some examples, the memory decks <NUM> and <NUM> may include chalcogenide material configured to store logic states. For example, the memory cells of the memory decks <NUM> and <NUM> may be examples of self-selecting memory cells. A chalcogenide material may be formed in the plurality of recesses such that the chalcogenide material in each respective one of the plurality of recesses is at least partially in contact with one of the plurality of conductive pillars.

<FIG> illustrates a bottom view of an example 3D memory array <NUM>-a in accordance with examples as disclosed herein. The memory array <NUM>-a includes a plurality of conductive contacts <NUM> formed in a substrate <NUM> and extending through the substrate <NUM> and coupled with an access line of the memory array <NUM>. For example, the substrate <NUM> may be a dielectric material, such as a dielectric film.

A single conductive contact of the plurality of conductive contacts <NUM> may be configured to couple any single vertical pillar with a transistor (not shown). The plurality of conductive contacts <NUM> may be arranged in a grid pattern. In some examples, a respective one of the plurality of conductive contacts <NUM> may be surrounded by up to eight other conductive contacts <NUM>. In some examples, the plurality of conductive contacts <NUM> may be arranged in a staggered pattern or a hexagonal pattern. For example, a respective one of the plurality of conductive contacts <NUM> may be surrounded by up to six other conductive contacts <NUM> (see <FIG> and <FIG>).

<FIG> illustrates a side view of an example 3D memory array <NUM>-b in accordance with examples as disclosed herein. The memory array <NUM>-b includes a plurality of conductive contacts <NUM> formed in the substrate <NUM>, a plurality of stacked planes of an insulative material <NUM> and a plurality of stacked planes of a conductive material <NUM> (e.g., word lines planes or word line plates). The stacked planes of conductive material <NUM> are separated in a z-direction (e.g., separated vertically) from one another by the plurality of planes of the insulative material <NUM>. For example, a first plane (e.g., a bottom plane) of the second insulative material <NUM> may be formed (e.g., deposited) on the plane of the substrate <NUM>, and then a plane of the conductive material <NUM> may be formed on the first plane of the second insulative material <NUM>. In some examples, a layer of the first insulative material <NUM> may be deposited on the substrate <NUM>. In some examples, the conductive material <NUM> may be a layer of conductive carbon or other conductive layer compatible with active materials. In some examples, the conductive material <NUM> may include conductive layers separated by active material through a protective barrier. The conductive material <NUM> is configured to function as at least one word line plate. In some examples, the conductive material <NUM> and the insulative material <NUM> form a plurality of layers, such as alternating layers.

Additional planes of the second insulative material <NUM> are formed on the conductive material <NUM> in an alternating manner as illustrated in <FIG>. The second insulative material <NUM> may be a dielectric material, such as a dielectric film or layer. In some examples, the second insulative material <NUM> and the substrate <NUM> may be the same type of insulative material. Examples of the insulative materials disclosed herein include, but are not limited to dielectric materials, such as silicon oxide.

Each respective one of the plurality of planes of the conductive material <NUM> may be at (e.g., form) a different level of the 3D memory array <NUM>-b. Individual planes of material that form memory cells may be referred to as a deck of the 3D memory array <NUM>-b. The conductive material <NUM> may comprise (e.g., be formed of) a metallic (or semi-metallic) material or a semiconductor material such as a doped polysilicon material, among others. In some examples, the conductive material <NUM> may be a plane of conductive carbon.

Six planes of the conductive material <NUM> and seven planes of the second insulative material <NUM> are shown in <FIG>. The seventh plane of the second insulative material <NUM> may be a topmost layer of the 3D memory array <NUM>-b. The quantity of planes of the conductive material <NUM> and the second insulative material <NUM> are not limited to the quantities illustrated in <FIG>. The conductive material <NUM> and the second insulative material <NUM> may be arranged into more than six decks or less than six decks.

<FIG> illustrates various views of example 3D memory arrays <NUM>-c, <NUM>-d, <NUM>-e, and <NUM>-f during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples as disclosed herein. Specifically, in <FIG>, a process of forming even and odd word line planes is shown.

<FIG> illustrates a top view of an example 3D memory array <NUM>-c, which may be an example of the memory array <NUM>-b illustrated in <FIG> after a trench <NUM> is formed. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-d along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-e along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-f along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a top view of an example 3D memory array <NUM>-f of section line B-B' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrate a series of steps or processes that may be performed to form a stacked memory device.

<FIG> illustrates forming the trench <NUM> through the alternating planes of conductive material <NUM> (shown in <FIG>) and the second insulative material <NUM> (shown in <FIG>) of memory array <NUM>-c. The trench <NUM> exposes the substrate <NUM> (previously shown in <FIG> and <FIG>) and the conductive contacts <NUM> (previously shown in <FIG> and <FIG>) at the bottom of the trench <NUM>.

The trench <NUM> is etched from top to bottom and etched in a serpentine shape. For instance, the trench <NUM> may pass over a row of the conductive contacts <NUM> in a first direction (e.g., from left to right) and then pass over an adjacent row of the conductive contacts <NUM> in a second direction that is opposite to the first direction (e.g., from right to left). With reference to the example of <FIG>, the trench <NUM> passes over a first row of the conductive contacts <NUM> from left to right, then "turns" and passes over the next (second) row of conductive contacts <NUM> (adjacent to the first row) from right to left. The trench <NUM> "turns" again and passes over the next (third) row of conductive contacts <NUM> (adjacent to the second row) from left to right. The trench <NUM> "turns" again and passes over the next (fourth) row of conductive contacts <NUM> (adjacent to the third row) from right to left and then "turns" again and passes over the next (fifth) row of conductive contacts <NUM> at the bottom of <FIG> (adjacent to the fourth row) from left to right.

The trench <NUM> bifurcates each plane of the conductive material <NUM> into at least two portions: a first portion <NUM> and a second portion <NUM>. Each portion of a plane of the conductive material <NUM> is a different access line (e.g., even word line or odd word line) of a deck. For example, the first portion <NUM> is a first access line of a deck of the 3D memory array <NUM>-c and the second portion <NUM> is a second access line of the same deck of the 3D memory array <NUM>-c. The extension of the fingers forming the even or odd planes may be defined based on the resistivity of an electrode used and by the level of current delivery requested. Specifically, the depth of the recesses is defined depending on the thickness desired for the memory cell.

<FIG> illustrates forming a plurality of recesses <NUM> in the conductive material <NUM> in each of the planes of memory array <NUM>-d. For example, a selective etching operation may be performed to form the plurality of recesses <NUM> in sidewalls <NUM> and <NUM> of the trench <NUM> in an isotropic way. In some examples, the trench <NUM> includes a first sidewall <NUM> spaced apart from a second sidewall <NUM>, where a first portion <NUM> of the first sidewall <NUM> formed by the first insulative material <NUM> is spaced apart from a first portion <NUM> of the second sidewall <NUM> formed by the first insulative material <NUM> by a first distance. A second portion <NUM> of the first sidewall <NUM> formed by the first conductive material <NUM> may be spaced apart from a second portion <NUM> of the second sidewall <NUM> formed by the first conductive material <NUM> by a second distance greater than the first distance. In some examples, portions of sidewalls <NUM> and <NUM> of the trench <NUM> formed by the first conductive material <NUM> are recessed relative to portions of the sidewalls <NUM> and <NUM> of the trench <NUM> formed by the first insulative material <NUM>.

The etching operations may include one or more vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process) or combinations thereof. For example, a vertical etching process may be performed to vertically etch the trench <NUM> and a horizontal etching process may be used to form at least one recess <NUM> in at least one conductive material <NUM>. The etching parameters may be selected such that the conductive material <NUM>, for example, is etched faster than the second insulative material <NUM>.

<FIG> illustrates forming a conformal material <NUM> (e.g., a sacrificial material or sacrificial layer). The conformal material <NUM> is deposited into the trench <NUM> of memory array <NUM>-e. The conformal material <NUM> may be formed in the recesses <NUM> (shown in <FIG>) by conformally depositing the conformal material <NUM>. The conformal material <NUM> contacts a first sidewall <NUM>, a second sidewall <NUM>, and a bottom wall <NUM> of each trench <NUM>. Although <FIG> shows that the conformal material <NUM> is formed on the sidewalls of the trench <NUM> (e.g., on the surfaces of the second insulative material <NUM> and the conductive materials <NUM> in different layers facing into the trench <NUM>) during formation of the conformal material <NUM> in the plurality of recesses <NUM>, examples are not so limited. For example, the conformal material <NUM> may be confined to only the plurality of recesses <NUM> in the conductive materials <NUM> in different layers in some cases. In some cases, the conformal material <NUM> may be referred to as a conformal layer or a sacrificial layer.

In some cases, an etching operation may be performed subsequent to forming the conformal material <NUM>. In the etching operation, the conformal material <NUM> may be etched to form an opening or trench <NUM>. The etch operation may result in the surfaces of the conformal material <NUM> (e.g., the surfaces facing the trench <NUM>) being spaced apart from the surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>). In some cases, the etch operation may result in the surfaces of the conformal material <NUM> (e.g., the surfaces facing the trench <NUM>) being approximately coplanar with surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>), and thereby forming a continuous sidewall of trench. The etching operations described herein may be vertical etching processes (e.g., an anisotropic etching process or a dry etching process, or a combination thereof) or horizontal etching processes (e.g., an isotropic etching process). For example, a vertical etching process may be performed to vertically etch the trench <NUM> and a horizontal etching process may be used to form at least one recess in the first conductive material <NUM>.

<FIG> illustrates depositing a dielectric material <NUM> in the trench <NUM> on top of the conformal material <NUM> of the memory array <NUM>-f. The dielectric material <NUM> contacts the conformal material <NUM>. The dielectric material <NUM> and the conformal material <NUM> may cooperate to fill the trench <NUM>. In some cases, the dielectric material <NUM> may be an example of an insulative material. In some examples, the conformal material <NUM> may be etched back selectively to form a co-planar surface with the dielectric material <NUM>. The depth of the recession may be defined depending on a desired thickness.

<FIG> illustrates a top view of an example 3D memory array <NUM>-f after the dielectric material <NUM> is deposited (as shown in <FIG>), in accordance with an example of the present disclosure. In <FIG>, the conformal material <NUM> formed in the trench <NUM> and the dielectric material <NUM> bifurcates each plane of the conductive material <NUM> into a first portion <NUM> and a second portion <NUM>.

<FIG> illustrates various views of example 3D memory arrays <NUM>-g, <NUM>-h, <NUM>-i, and <NUM>-j, during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples as disclosed herein. Specifically, <FIG> illustrate processes for forming memory cells in the memory array <NUM>-f illustrated in <FIG> and <FIG>.

<FIG> illustrates a top view of a memory array <NUM>-g, which may be an example of the memory array <NUM>-f illustrated in <FIG> after formation of openings <NUM>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-h along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-i along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-j along section line A-A' during a process step subsequent to what is illustrated in <FIG>. <FIG> illustrates a top view of the example 3D memory array <NUM>-j of section line B-B' during a process step subsequent to what is illustrated in <FIG>.

<FIG> illustrates a top view through any one of the planes of the conductive material <NUM> of the memory array <NUM>-g. A plurality of openings <NUM> in a trench <NUM> is formed by etching away a portion of the dielectric material <NUM> and/or the conformal material <NUM>. The openings <NUM> are intended to be positioned in alignment with the plurality of conductive contacts <NUM> so that forming the openings <NUM> exposes at least a portion of a plurality of conductive contacts <NUM> (shown in <FIG>) extending through the substrate <NUM> (shown in <FIG>). The etching process may be a vertical etching process. In some examples, the etching operation may not etch away all portions of the conformal material <NUM>, for example, where the plurality of openings <NUM> are not formed.

<FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-h in accordance with an example of the present disclosure. As shown in <FIG>, a plurality of recesses <NUM> is formed in the conductive material <NUM> in each of the planes. For example, a selective etching operation may be performed to form the plurality of recesses <NUM> in a full or partially isotropic way. The etching chemistry may be selected to selectively reach a conductive material <NUM>. The conductive contacts <NUM> may be exposed by forming the openings <NUM> in the trench <NUM>.

<FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-i in accordance with an example of the present disclosure. As shown in <FIG>, a storage element material <NUM> is formed in the plurality of recesses <NUM> by conformally depositing the storage element material <NUM> into the trench <NUM>. The storage element material <NUM> may be deposited to contact sidewalls <NUM> and <NUM> and a bottom wall <NUM> of the trench <NUM> exposed by the etching of the conformal material <NUM>. When the storage element material <NUM> contacts the bottom wall <NUM> of the trench <NUM>, the storage element material <NUM> covers the exposed conductive contacts <NUM>.

The storage element material <NUM> may be an example of a chalcogenide material, such as a chalcogenide alloy and/or glass, that may serve as a self-selecting storage element material (e.g., a material that may serve as both a select device and a storage element). For example, the storage element material <NUM> may be responsive to an applied voltage, such as a program pulse. For an applied voltage that is less than a threshold voltage, the storage element material <NUM> may remain in an electrically nonconductive state (e.g., an "off" state). Alternatively, responsive to an applied voltage that is greater than the threshold voltage, the storage element material <NUM> may enter an electrically conductive state (e.g., an "on" state).

The storage element material <NUM> may be programmed to a target state by applying a pulse (e.g., a programming pulse) that satisfies a programming threshold. The amplitude, shape, or other characteristics of the programming pulse may be configured to cause the storage element material <NUM> to exhibit the target state. For example, after applying the programming pulse, the ions of the storage element material <NUM> may be redistributed throughout the storage element, thereby altering a resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the storage element material <NUM> may vary based on applying the programming pulse.

The state stored by the storage element material <NUM> may be sensed, detected, or read by applying read pulse to the storage element material <NUM>. The amplitude, shape, or other characteristics of the read pulse may be configured to allow a sense component to determine what state is stored on the storage element material <NUM>. For example, in some cases, the amplitude of the read pulse is configured to be at a level that the storage element material <NUM> will be in an "on" state (e.g., current is conducted through the material) for a first state but will be in an "off" state (e.g., little to no current is conducted through the material) for a second state.

In some cases, the polarity of the pulse (whether programming or read) applied to the storage element material <NUM> may affect the outcomes of the operation being performed. For example, if the storage element material <NUM> stores a first state, a read pulse of a first polarity may result in the storage element material <NUM> exhibiting an "on" state while a read pulse of a second polarity may result in the storage element material <NUM> exhibiting an "off" state. This may occur because of the asymmetrical distributions of ions or other material in the storage element material <NUM> when it is storing a state. Similar principles apply to programming pulses and other pulses or voltages.

Examples of chalcogenide materials that may serve as the storage element material <NUM> include indium(In)-antimony(Sb)-tellurium(Te) (IST) materials, such as In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, etc., and germanium(Ge)-antimony(Sb)-tellurium(Te) (GST) materials, such as Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, or etc., among other chalcogenide materials, including, for instance, alloys that do not change phase during the operation (e.g., selenium-based chalcogenide alloys). Further, the chalcogenide material may include minor concentrations of other dopant materials. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), Sulphur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. In some examples, the chalcogenide material may be a chalcogenide glass or amorphous chalcogenide material. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG-alloy. In some examples, SAG-alloy may include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, the chalcogenide glass may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms. In some examples, conductivity may be controlled through doping using various chemical species. For example, doping may include incorporating a Group <NUM> (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group <NUM> (tin (Sn), carbon (C), silicon (Si), etc.) element into the composition.

<FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-j in accordance with an example of the present disclosure. An etching operation may be performed subsequent to forming the storage element material <NUM> so that surfaces of the storage element material <NUM> (e.g., the surfaces facing into the trench <NUM>) are approximately coplanar with surfaces of the second insulative material <NUM> (e.g., the surfaces facing into the trench <NUM>) as illustrated in <FIG>. The etching of the storage element material <NUM> may form a continuous sidewall and remove the top layer <NUM> (shown in <FIG>) of the storage element material <NUM>, whereby cells of the storage element material <NUM> are formed in the recesses only. In each recess, each cell of the storage element material <NUM> contacts a single conductive material <NUM> (e.g., a single conductive material <NUM> located adjacent to the cell of the storage element material <NUM>) and at least two dielectric layers (e.g., a top dielectric layer and a bottom dielectric layer located on top of the cell of the storage element material <NUM> and on bottom of the cell of the storage element material <NUM>), as shown in <FIG>. The etching of the storage element material <NUM> may provide a configuration in which the storage element material <NUM> are separated from one another. The etching of the storage element material <NUM> may also expose the conductive contacts <NUM> in the substrate <NUM>. In some examples, portion of sacrificial material may be located on either side of the cell of the storage element material <NUM> (as shown in <FIG>).

<FIG> illustrates a top view of an example 3D memory array <NUM>-j in accordance with an example of the present disclosure. As illustrated in <FIG>, the conformal material <NUM> and the storage element material <NUM> formed in the trench <NUM> bifurcate each plane of the conductive material <NUM> into a first portion <NUM> and a second portion <NUM>. Each portion of a plane is an example of a word line plate.

<FIG> illustrates various views of example 3D memory arrays <NUM>-k, <NUM>-l, and <NUM>-m, during a series of steps or processes that may be performed to form a stacked memory device, in accordance with examples as disclosed herein. Specifically, <FIG> illustrate processes of filling the openings <NUM> after the recessed self-selecting memory cells are formed.

<FIG> illustrates a top view of a memory array <NUM>-k, which may be an example of the memory array <NUM>-j illustrated in <FIG> after formation of recessed self-selecting memory cells. <FIG> is a top view of a memory array <NUM>-l through any one of the planes of the conductive material <NUM> illustrated in <FIG> during a processing step that is subsequent to what is illustrated in <FIG>. <FIG> illustrates a cross-sectional view of an example 3D memory array <NUM>-m along section line A-A' during a processing step that is subsequent to what is illustrated in <FIG>.

<FIG> illustrates a top view of a memory array <NUM>-k where a barrier material <NUM> is deposited into the openings <NUM> of the trench <NUM>. In some implementations, the barrier material <NUM> contacts at least one portion of the first insulative material <NUM> (not shown), the second insulative material <NUM> (not shown), and the storage element material <NUM>. In some examples, the barrier material <NUM> is compatible with an active material. In some examples, the barrier material <NUM> may be a conductive material, or a barrier layer with a conductive material. The barrier layer may comprise aluminum oxide, for example. In some examples, an etching operation may be performed to make room for conductive material to be deposited into the trench <NUM>. In some cases, the barrier material <NUM> may be referred to as a barrier layer.

<FIG> illustrates a top view of a memory array <NUM>-l where a conductive material <NUM> is deposited into the openings <NUM> of the trench <NUM>. A conductive material <NUM> is deposited in the opening <NUM> to form a conductive pillar <NUM>. The conductive pillar <NUM> may include the barrier material <NUM> and the conductive material <NUM>. The conductive pillar <NUM> is in contact with the storage element material <NUM> on the sidewalls <NUM> and <NUM> (shown in <FIG>) of the trench <NUM>. In some examples, the conductive pillar <NUM> may comprise the same material as the conductive material <NUM>. The conductive pillar <NUM> is a digit line. The conductive pillar <NUM> may be a cylinder. Although <FIG> illustrates the conductive pillar <NUM> as a solid pillar, in some examples the conductive pillar <NUM> may be a hollow cylinder or toroidal (e.g., a tube). The conductive pillar <NUM> may comprise a metallic (or semi-metallic) material or a semiconductor material such as a doped polysilicon material, among others. However, other metallic, semi-metallic, or semiconductor materials may be used.

The conductive pillars <NUM> formed in each respective one of the plurality of openings <NUM> are arranged to extend substantially orthogonal to the alternating planes of the conductive material <NUM> and the second insulative material <NUM> (not shown). The storage element material <NUM> and the conductive pillar <NUM> formed in each respective one of the plurality of openings <NUM> are formed in a substantially square shape. However, examples of the present disclosure are not limited to exact or quasi-exact square shapes. For instance, the storage element material <NUM> and the conductive pillar <NUM> may formed in any shape, including circles or oval shapes, for instance.

<FIG> illustrates a side view of an example 3D memory array <NUM>-m in accordance with an example of the present disclosure. As illustrated in <FIG>, a capping layer <NUM> (e.g., an insulative material, such as a dielectric layer) may be deposited to cap the conductive pillars <NUM> of memory array <NUM>-l.

The memory array <NUM>-m includes a plurality of vertical stacks. Each respective stack may include the conductive pillar <NUM>, a conductive contact <NUM> coupled to the conductive pillar <NUM>, the storage element material <NUM> formed in contact with the first portion <NUM> and the conductive pillar <NUM>, and the storage element material <NUM> formed in contact with the second portion <NUM> and the conductive pillar <NUM>.

The conductive pillar <NUM> is in contact with the conductive contact <NUM> and the first insulative material <NUM>, and in contact with the storage element material <NUM> formed in the recesses <NUM>. In some cases, the storage element material <NUM> formed in each respective recess <NUM> is formed partially (e.g., not completely) around the conductive pillar <NUM>.

Although not shown in <FIG> for clarity and so as not to obscure examples of the present disclosure, other materials may be formed before, after, and/or between the storage element material <NUM>, and/or the conductive pillar <NUM>, for example, to form adhesion layers or barriers against interdiffusion of materials and/or to mitigate composition mixing.

<FIG>illustrates various views of example 3D memory arrays <NUM>-a and <NUM>-b, which may be examples of the 3D memory arrays <NUM>-a through <NUM>-m processed in <FIG>, in accordance with examples as disclosed herein. The memory arrays <NUM>-a and <NUM>-b may include similar features as memory arrays <NUM>-a through <NUM>-m described with reference to <FIG>. A plurality of openings <NUM> may be formed through the alternating planes of the conductive material <NUM> and the second insulative material <NUM> (not shown), and the dielectric material <NUM> in the trench <NUM>. As shown, the diameter of the plurality of openings <NUM> is approximately the same width of the trench <NUM>. In some examples, the diameter of the plurality of openings <NUM> may be greater than the width of the trench <NUM>.

Each of the plurality of openings <NUM> may be approximately concentric with a different respective one of the conductive contacts <NUM>. As shown in <FIG> and <FIG>, the pillars <NUM> are circular and formed over and coupled to the plurality of contacts in geometric pattern in respective openings <NUM>. In some examples, such as illustrated in <FIG>, the openings <NUM> may be square.

The plurality of openings <NUM> may have the staggered (e.g., hexagonal) arrangement of the conductive contacts <NUM> (not shown). For example, a respective one of the plurality of conductive contacts <NUM> may be surrounded by six other conductive contacts <NUM>.

A staggered pattern may refer to any pattern where positions of objects (e.g., contacts, openings, or pillars) in a first row are offset from positions of objects (e.g., contacts, openings, or pillars) in a second row adjacent to the first row in a given direction. For example, a staggered pattern may have objects (e.g., contacts, openings, or pillars) adjacent to one another in the x-direction (e.g., rows), but not in the y-direction (e.g., columns). For instance, as illustrated in <FIG> and <FIG>, the plurality of conductive contacts <NUM> are adjacent to each other and in line with each other in an x-direction. However, the plurality of conductive contacts <NUM> are not adjacent to each other in the y-direction. The plurality of conductive contacts <NUM> are in line with each other in the x-direction and the plurality of conductive contacts <NUM> alternate (e.g., skip) rows in the y-direction. Although, <FIG> and <FIG> show spacing that is approximately the same between the conductive contacts <NUM> throughout the substrate <NUM>, examples in accordance with the present disclosure are not so limited. For example, the spacing between the conductive contacts <NUM> may vary throughout the substrate <NUM>.

<FIG> shows that a 3D memory array <NUM>-b may include a plurality of storage element materials <NUM>, each comprising a chalcogenide material positioned between at least one of the word line plates, at least one circular pillar <NUM>, and at least one dielectric material <NUM>. In some examples, depending on the decoding optimization, the pillars <NUM> may be coupled to a plurality of selectors positioned at a top, a bottom, or both a top and a bottom (e.g., below or above the plurality of word line plates) of the 3D memory array <NUM>-b.

<FIG>illustrates various views of example 3D memory arrays <NUM>-a, <NUM>-b, and <NUM>-c, which may be examples of the 3D memory arrays <NUM>-a through <NUM>-m processed in <FIG> and the 3D memory arrays <NUM>-a through <NUM>-b processed in <FIG>, in accordance with examples as disclosed herein. The memory arrays <NUM>-a, <NUM>-b, and <NUM>-c include similar features as memory arrays <NUM>-a through <NUM>-m described with reference to <FIG> and memory arrays <NUM>-a through <NUM>-b described with reference to <FIG>. A particular separation trench <NUM>', which is filled with an insulation material or a dielectric material, is formed between two sub-arrays (e.g., a first sub-array <NUM>-a1 and a second sub-array <NUM>-a2), such that the first sub-array <NUM>-a1 and the second sub-array <NUM>-a2 are separated from each other electrically. The memory array <NUM>-a includes a plurality of word line plates separated from one another by respective dielectric layers (refer to the side view of the memory array shown in <FIG>). The plurality of word line plates includes several sets of word lines. In the first sub-array <NUM>-a1, a first set of word lines is separated from a second set of word lines by a dielectric material extending in a serpentine shape. In the second sub-array <NUM>-a2, a third set of word lines is separated from a fourth set of word lines by a dielectric material extending in a serpentine shape. The first set of word lines and the second set of word lines are separated from the third set of word lines and the fourth set of word lines by the particular separation trench <NUM>'. Only one particular separation trench <NUM>' is shown in <FIG>, which is for a purpose of illustration. The quantities of the particular separation trench <NUM>' and the sub-arrays <NUM>-a1 and <NUM>-a2 are not limited to the quantities illustrated in <FIG>. Several separation trenches <NUM>' may be formed in a 3D memory array as needed.

With the separation trench <NUM>' filled with an insulation material or a dielectric material, which may also be called as a separation layer, a power consumption of a 3D memory array may be further reduced while meeting a storage class memory (SCM) specification. Compared to a 3D memory array in which a plurality of sub-arrays are coupled with each other, a 3D memory array with serval separation layers interposed, a corresponding capacitance value may drop down and the power consumption may also be further reduced without increasing decoding burden.

As shown in <FIG>, in some examples, after forming the trench <NUM> in a serpentine shape in the 3D memory array <NUM>-a, a particular portion of the trench <NUM> may be selected as the particular separation trench <NUM>', which is used to divide the 3D memory array <NUM>-a into the first sub-array <NUM>-a1 and the second sub-array <NUM>-a2. In some examples, the particular separation trench <NUM>' may be subjected to a further etch operation so that the two sub-arrays on both sides of the particular separation trench <NUM>' are separated completely. In some examples, during the subsequent processing steps, the particular separation trench <NUM>' may be filled only with the insulative material or dielectric material, without any other material such as a storage element material or a conductive material formed therein. In some examples, a particular portion may be determined from the serpentine trench <NUM> as the separation trench <NUM>' every certain number of word lines.

In addition to the forming method of the separation trench <NUM>' (or the separation layer <NUM>'), two other different methods may be used. In one example, a plurality of sub-arrays may be formed on a same substrate by the processing steps described with reference to <FIG>, and wherein several separation layers <NUM>' may be deposited on one side a or both sides of a sub-array in an extending direction of the serpentine shaped trench <NUM> so that the plurality of sub-arrays are separated from each other electrically. In another example, after forming a 3D memory array as mentioned in the embodiments described with reference to <FIG>, according to the dimension of the memory array, a certain number of separation trenches <NUM>' may be formed along a plane parallel to both a digit line and a word line to cut the memory array into a plurality of sub-arrays, and wherein an etch operation may be performed on the memory array to form the separation trenches <NUM>'.

<FIG> and <FIG> illustrate that a position where a particular separation trench <NUM>' (or a separation layer <NUM>') is formed may be adjusted according to the dimension of 3D memory array. For example, a cross-sectional area of the memory array shown in <FIG> may be <NUM> × <NUM>. When the 3D memory array is formed based on example pitches (e.g., a pitch of about <NUM> in x direction and a pitch of about <NUM> in y direction) of adjacent pillars shown in <FIG> illustrating exemplary dimensions related to an example 3D memory array in accordance with example as disclosed herein, the 3D memory array may contain <NUM>×<NUM> pillars. In this case, eight separation layers <NUM>' may be formed in the 3D memory array to divide the 3D memory array into eight portions, each of which may contain <NUM>×<NUM> pillars.

In some examples, because of the insertion of the separation layers <NUM>', the corresponding capacitance value may drop down to 2pF, and the first order computation of the energy ( <MAT>) needed to charge the word line is about 15pF/bit. In addition, the dividing of the 3D memory array on pillars thereof may allow the decoding circuitry under array (CuA) optimization, for example minimizing the number of pillar decoders, sense amplifier or the like, while SCM requirements can be met due to the memory array segmentation at a higher level (i.e., the word line cutting due to the insertion of the separation layers).

In some examples, depending on the decoding optimization, the pillars <NUM> may be coupled to a plurality of selectors positioned at a top, a bottom, or both a top and a bottom (e.g., below or above the plurality of word line plates) of the 3D memory arrays. Spatially related terms, including but not limited to, "top," "bottom," "lower," "upper," "beneath," "below," "above," etc., if used herein, are utilized for ease of description to describe spatial relationships of an element(s) to another. Such spatially related terms encompass different orientations of the device in addition to the particular orientations depicted in the figures and described herein. For example, if a structure depicted in the figures is turned over or flipped over, portions previously described as below or beneath other elements would then be above or over those other elements.

<FIG> shows a flowchart illustrating a method <NUM> for manufacturing a 3D memory array in accordance with aspects of the present disclosure. The operations of method <NUM> may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At S905, the method <NUM> includes forming a plurality of conductive contacts extending through a substrate, and each contact is associated with a respective one of a plurality of digit lines. The operations of S905 may be performed according to the method described herein.

At S910, the method <NUM> includes forming a plurality of conductive layers separated from one another with a respective one of a plurality of dielectric layers, and wherein the plurality of conductive layers is configured as word lines. The operations of S910 may be performed according to the method described herein.

At S915, the method <NUM> includes forming a serpentine trench through the plurality of conductive layers and the plurality of dielectric layers, the serpentine trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines. The operations of S915 may be performed according to the method described herein.

At S920, the method <NUM> includes treating at least one particular portion of the serpentine trench to form at least one separation trench so that parts of the memory array on both sides of the at least one separation trench are separated from one another. The operations of S920 may be performed according to the method described herein.

At S925, the method <NUM> includes filling the at least one separation trench with an insulation material to separate word lines at one side of the at least one separation trench from word lines at the other side of the at least one separation trench electrically. The operations of S925 may be performed according to the method described herein.

At S930, the method <NUM> includes forming, in remaining portions of the serpentine trench, a conformal material, a dielectric material, a storage element material, and the digit lines so that a respective storage element is surrounded by a respective word line, a respective digit line, the conformal material, and respective dielectric layers. The operations of S930 may be performed according to the method described herein.

Furthermore, the step of forming, in remaining portions of the serpentine trench, a conformal material, a dielectric material, a storage element material, and the digit lines may further comprise depositing the conformal material in remaining portions of the serpentine trench, depositing the dielectric material on the conformal material, forming an opening over a respective conductive contact by etching a portion of the conformal material and the dielectric material, depositing the storage element material into the opening, treating the storage element material so that sidewalls of the plurality of dielectric layers and the storage element material are coplanar, and depositing a conductive material into the opening to form the digit line.

In some examples, an apparatus as described herein may perform a method, such as the method <NUM>. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a plurality of conductive contacts extending through a substrate, and each contact is associated with a respective one of a plurality of digit lines.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for forming a plurality of conductive layers separated from one another with a respective one of a plurality of dielectric layers, and wherein the plurality of conductive layers is configured as word lines.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for forming a serpentine trench through the plurality of conductive layers and the plurality of dielectric layers, the serpentine trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for treating at least one particular portion of the serpentine trench to form at least one separation trench so that parts of the memory array on both sides of the at least one separation trench are separated from one another.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for filling the at least one separation trench with an insulation material to separate word lines at one side of the at least one separation trench from word lines at the other side of the at least one separation trench electrically.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for forming, in remaining portions of the serpentine trench, a conformal material, a dielectric material, a storage element material, and the digit lines so that a respective storage element is surrounded by a respective word line, a respective digit line, the conformal material, and respective dielectric layers.

Some examples of the apparatus described herein may further include operations, features, means, or instructions for depositing the conformal material in remaining portions of the serpentine trench, depositing the dielectric material on the conformal material, forming an opening over a respective conductive contact by etching a portion of the conformal material and the dielectric material, depositing the storage element material into the opening, treating the storage element material so that sidewalls of the plurality of dielectric layers and the storage element material are coplanar, and depositing a conductive material into the opening to form the digit line.

At S1010, the method <NUM> includes forming a plurality of conductive contacts extending through a substrate, and wherein each conductive contract is associated with a respective one of a plurality of digit lines. The operations of S1010 may be performed according to the method described herein.

At S1030, the method <NUM> includes forming a plurality of conductive layers separated from one another with a respective one of a plurality of dielectric layers, and wherein the plurality of conductive layers is configured as word lines. The operations of S1030 may be performed according to the method described herein.

At S1050, the method <NUM> includes forming a serpentine trench through the plurality of conductive layers and the plurality of dielectric layers, the serpentine trench exposing the substrate and dividing the plurality of conductive layers into a first set of word lines and a second set of word lines. The operations of S1050 may be performed according to the method described herein.

At S1070, the method <NUM> includes forming, in the serpentine trench, a conformal material, a dielectric material, a storage element material, and the digit lines so that a respective storage element is surrounded by a respective word line, a respective digit line, the conformal material, and respective dielectric layers. The operations of S1070 may be performed according to the method described herein.

At S1090, the method <NUM> includes cutting the vertical 3D memory array at a particular position along a plane parallel to both a word line and a digit line so that the vertical 3D memory array is divided into a several portions separated from one another electrically, and wherein each of the portions includes a certain number of digit lines. The operations of S1090 may be performed according to the method described herein.

Furthermore, the step of forming, in the serpentine trench, a conformal material, a dielectric material, a storage element material, and the digit lines may comprise depositing the conformal material in the serpentine trench, depositing the dielectric material on the conformal layer, forming an opening over a respective conductive contact by etching a portion of the conformal material and the dielectric material, depositing the storage element material into the opening, treating the storage element material so that sidewalls of the plurality of dielectric layers and the storage element material are coplanar, and depositing a conductive material into the opening to form the digit line.

Furthermore, portions from two or more of the methods may be combined.

<FIG> is a block diagram of an apparatus in the form of a memory device <NUM> in accordance with examples as disclosed herein. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dies, a module or modules, a device or devices, or a system or systems, for example. As shown in <FIG>, the memory device <NUM> includes a 3D memory array <NUM> analogous to the 3D memory array <NUM>-l, <NUM>-b, and/or <NUM>-a previously described in connection with <FIG>, <FIG>, and <FIG>, respectively. Although <FIG> shows a single 3D memory array <NUM> for clarity and so as not to obscure embodiments of the present disclosure, the memory device <NUM> may include any number of the 3D memory array <NUM>.

As shown in <FIG>, the memory device <NUM> can include decoding circuitry <NUM> coupled to the 3D memory array <NUM>. The decoding circuitry <NUM> can be included on the same physical device (e.g., the same die) as the 3D memory array <NUM>. The decoding circuitry <NUM> can be included on a separate physical device that is communicatively coupled to the physical device that includes the 3D memory array <NUM>.

The decoding circuitry <NUM> can receive and decode address signals to access the memory cells as mentioned above with reference to <FIG> of the 3D memory array <NUM> during program and/or sense operations performed on the 3D memory array <NUM>. For example, the decoding circuitry <NUM> can include portions of decoder circuitry for use in selecting a particular memory cell of the 3D memory array <NUM> to access during a program or sense operation. For instance, a first portion of the decoder circuitry can be used to select a word line and a second portion of the decoder circuitry can be used to select a digit line.

The embodiment illustrated in <FIG> can include additional circuitry, logic, and/or components not illustrated so as not to obscure embodiments of the present disclosure. For example, the memory device <NUM> can include a controller to send commands to perform operation on the 3D memory array <NUM>, such as operations to sense (e.g., read), program (e.g., write), move, and/or erase data, among other operations. Further, the memory device <NUM> can include address circuitry to latch address signals provided over input/output (I/O) connectors through I/O circuitry. Further, the memory device <NUM> can include a main memory, such as, for instance, a DRAM or SDRAM, that is separate from and/or in addition to the memory array <NUM>.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

For example, due to the nature of software, functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these.

Claim 1:
A vertical 3D memory device (<NUM>), comprising:
a substrate (<NUM>) including a plurality of conductive contacts (<NUM>) each coupled with a respective one of a plurality of digit lines (<NUM>);
a plurality of word line plates (<NUM>) separated from one another by respective dielectric layers (<NUM>) on the substrate, the plurality of word line plates including at least a first set of word lines (<NUM>) separated from at least a second set of word lines (<NUM>) by a dielectric material (<NUM>) extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines by a dielectric material extending in a serpentine shape;
at least one separation layer (<NUM>') separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and
a plurality of storage elements (<NUM>) each formed in a respective one of a plurality of recesses (<NUM>) such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material (<NUM>) formed on a sidewall of a word line facing a respective digit line.