Patent Description:
New universal serial bus (USB) power-delivery (PD) and Type-C specifications have been released that enable delivery of higher electrical power over new USB cables and connectors. The intent for this technology is to create a universal power plug for laptops, tablets and other devices that may require more than a 5V power supply.

The USB-PD specification defines a communication link between ports connected via a USB-PD cable and connectors. The communication is designed to be half-duplex and packet-based. The packets contain various information that enables the source port and sink ports to communicate and negotiate the voltage and current the source port will provide to the sink port. The ports can negotiate to switch roles (i.e., the source port to become the sink port and vice versa).

The underlying communication in the USB PD specification is Biphase Mark Coding (BMC). The USB-PD communication goes over a different wire (e.g., the secondary Cable Connection (CC2) wire) rather than the USB data wires. For USB Type-C cables up to <NUM> W of power can be delivered even without USB PD messaging by controlling the DC voltage on the CC pin.

<FIG> shows a block diagram of a known USB PD system <NUM> after downstream facing port/source (DFP) <NUM> to upstream facing port/sink (UFP) <NUM> attachment via a cable <NUM> that utilizes BMC signaling for PD. The DFP <NUM> is shown implemented with a resistive pull-up (shown as Rp) to its CC pin, which can also be a current source. A power supply <NUM> supplies power to the Vbus line that is received across the load (or power sink) <NUM> via the cable <NUM>. A DC voltage on the CC line is established by the Rp on one end of the cable <NUM> and a resistive pull-down shown as Rd between the CC pin and ground on the other end of the cable. The power supply is shown as a <NUM>. 3V DC supply coupling through RP and Rd. There are other lines that may be present in the cables shown as data lines that are not relevant to this Disclosure.

Some battery-operated mobile devices utilize more than one USB Type-C receptacle and the USB PD protocol. Some systems also implement the Type-C and PD capabilities using an analog frontend or port controller coupled to a microcontroller (or other processor) that acts as a master in the PD system. In typical scenarios the port controller is a slave to the microcontroller, where the microcontroller tells the port controller when to turn on or off any power-path switch or input/output pin typically referred to as a general-purpose input/output (GPIO) pin. The microcontroller may use the same Inter Integrated Circuit Communications (I2C) bus to control multiple (e.g., <NUM>) port controllers.

There are cases where such a load's <NUM> battery is removed or drained of any charge. This is referred to herein as the dead-battery scenario. In the dead-battery scenario, the PD system <NUM> needs a way to receive power from the VBUS pin of one (and only one) of its Type-C receptacles (or connectors). The port controller connects the VBUS pin of the Type-C receptacle into the power system of the device so that it can begin functioning properly. This means that the port controller needs to take some autonomous action in the dead-battery scenario. The port controller detects this dead-battery scenario by the presence or absence of VDD at its VDD supply pin. If no voltage is applied to the VDD supply pin which is typically directly connected to a positive DC power supply (e.g., <NUM> V), but power is applied to the VPWR pin of the port controller, then the port controller operates as if it is in a system with a dead-battery.

In some system architectures there are first and second port controllers in a system architecture where both port controllers are driving a power-path switch for the same power-path. The power-path is designed so that only one port's power-path switch may be closed, where the design intends for "collisions" to be avoided. Collisions may be avoided by coupling the respective port controllers so that they recognize each other and the first port controller that can provide power to the power system sink takes control of supplying power. Known system architectures having first and second port controllers and at least one power-path switch coupling to a power path sink (load device) typically use current sources and voltage detectors to measure the voltage level to avoid collisions. discloses charging a provider/consumer with a dead battery via USB power delivery.

Disclosed embodiments recognize known power delivery (PD) systems with a first port controller and a second port controller that have current sources and voltage detectors to measure the voltage level can sometimes avoid port controller collisions where more than one port controller is in control at any given time. However, such PD systems lack robustness and do not guarantee collisions will not take place, particularly when their master controller is unresponsive. Although the master controller (sometimes called an embedded controller) is designed to avoid collisions when it is responsive, if the master controller is unresponsive (e.g., the system battery is dead) so that both port controllers have their associated power-path switches closed at the same time, then the port controller with the power supply providing the smaller magnitude voltage connected to the port controller having a larger magnitude voltage may be damaged due to the resulting reverse current.

Disclosed PD systems include a system architecture and the port controllers implementing a disclosed dead-battery control (DBC) algorithm that enables cooperation between the port controllers so that when their master defined herein as an external process such as run by a microcontroller is unresponsive (e.g., the system's battery is dead) collisions still are avoided. The coupling between the port controllers can be such that during a dead-battery event they recognize each other and the first of the respective port controllers that can provide power to the power system sink takes control and exclusively provides power to the power sink.

The drawings are not necessarily drawn to scale. Some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

If a first device "couples" to a second device, that connection can be through a direct electrical connection where only parasitics are in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal, but may adjust its current level, voltage level and/or power level.

<FIG> shows an example PD system <NUM> where each port controller shown as first port controller <NUM> and second port controller <NUM> includes a state-machine <NUM>, and has a gate driver pin shown as GDN for driving control nodes of a different power-path switch 215a, 215b, according to a disclosed embodiment. The DBC mechanism uses the level on the port controllers' input/output pin referred herein as a general purpose IO (GPIO) pin that are shown herein as GPIO4 pins which in <FIG> are directly coupled to one another. Because of this direct coupling, during a DB event the port controllers recognize each other and the first of the respective port controllers that can provide power to the power system sink takes control and exclusively provides power to the power sink.

The DBC mechanism resides in the port controllers <NUM>, <NUM> and uses the port controllers' GPIO pins shown as GPIO4 pins to ensure that only one power-path switch is connected to the power system sink <NUM> at any given time. The power-path switches 215a, 215b can comprise N-channel MOSFET(s), where the GDN pin can directly control the voltage level on the gate of the N-channel MOSFET(s). Alternatively, a GPIO (not GPIO4) can control a load switch IC or a gate driver pin can control a P-channel MOSFET. A further alternative is a low voltage GPIO pin for driving a P-channel MOSFET which then drives an N-channel MOSFET. The port controllers <NUM>, <NUM> are each shown including an internal pull-up block <NUM>, such as comprising a large resistor, connected between the GPIO4 pins and DVDD (which is shown as an internally regulated voltage). A "large resistor" is defined herein as being at least <NUM> kohms, such as being <NUM> kohms.

PD system <NUM> includes a processor <NUM> shown as a µcontroller that is the master of an Inter Integrated Circuit Communications (I2C) bus <NUM> which provides I2C master signals to the I2C slave pins of the respective port controllers <NUM> and <NUM>. A unique I2C slave address is hard coded into the respective port controllers <NUM>, <NUM>, such as by pulling an input pin shown as the AD pin differently. Port controllers <NUM> is shown having its AD pin grounded, while port controller <NUM> is shown having its AD pin connected to ground through as resistor shown as RAD. PD system <NUM> receives power shown as VBUS from the VBUS pins of the Type-C receptacles (receptacles) <NUM>, <NUM> that is also coupled an input node of the power-path switches 215a and 215b. VPWR is a pin on the port controllers <NUM>, <NUM>, the receptacles <NUM>, <NUM> are shown having a VBUS pin, and the port controllers <NUM>, <NUM> are also shown having a VBUS pin. The VPWR and VBUS pins of the port controllers <NUM>, <NUM> are shown tied together, although they can be separate pins for separate connections. Disclosed port controllers can be implemented as integrated circuits (ICs) on a substrate having a semiconductor surface, shown as substrate <NUM>, typically a silicon substrate with an optional silicon epitaxial layer.

Based on the state of their MODE pins, with the MODE pin of port controller <NUM> shown coupled to a <NUM> V power supply and MODE pin of port controllers <NUM> coupled to ground, the port controllers <NUM> and <NUM> in this embodiment turn on their GDN pin in the DB scenario. The biasing difference for the respective MODE pins shown (or some other MODE pin biasing difference, or a bias difference to the AD pins) is to ensure that the respective port controllers <NUM>, <NUM> do not use the same timings to avoid turning on their respective GDN pins at the same time which can cause collisions. As described below, the MODE pin or AD pin bias gives each port controller its unique I2C address and this in turn sets the timings by determining a unique tCycle values for each port controller <NUM>, <NUM>. Accordingly, in contrast to that shown in <FIG> (and <FIG> described below), the controller's <NUM>, <NUM> AD pins can be pulled differently to provide different hard coded I2C slave addresses, with the respective MODE pins biased the same on both port controllers <NUM> and <NUM>.

There is no direct relation between GPIO4 and MODE pins so that one can have one without the other. If the VBUS and VPWR pins of only receptacle <NUM> associated with port controller <NUM> is powered, but not VDD, then that power on the VBUS/ VPWR pins is routed into the power system sink <NUM> via power-path switch 215a.

However, as noted above, a potential exists for a collision if both receptacles <NUM>, <NUM> have power on their VBUS pins and their processor <NUM> is unresponsive. Therefore, it is recognized it can be important that both port controllers <NUM> and <NUM> not have their GDN pins both turned on at the same time in the dead-battery scenario. To enable the two port controllers <NUM> and <NUM> to coordinate (synchronize) the closing (i.e., turning on) of their GDN pins so that only <NUM> GDN pin is on at most at any given time, in PD system <NUM> the port controllers <NUM>, <NUM> are directly coupled together via a wire referred to as a DBC wire <NUM> that is shown positioned to connect together the GPIO4 pins of port controllers <NUM> and <NUM>. Although it is also possible for the DBC wire <NUM> to be replaced by a wireless connection by adding a wireless transceiver for each port controller, a wireless transceiver is likely to more complicated than the port controller.

A state-machine <NUM> is shown implemented inside each port controller <NUM>, <NUM> that uses the signal on the DBC wire <NUM> to coordinate the two port controllers <NUM>, <NUM> so that only one of the port controllers <NUM> and <NUM> is on (GDN pin turned on) at any given time. The state machine <NUM> or other components of disclosed port controllers can be implemented in hardware or a suitable combination of hardware and software, and can utilize one or more integrated circuits (ICs) built on a substrate <NUM> that has at least a semiconductor surface. As noted above, the substrate <NUM> may comprise silicon, such as bulk silicon or silicon epi on a bulk silicon substrate. The substrate may also comprise other materials, such as elementary semiconductors besides silicon including germanium. The substrate may also comprise a compound semiconductor.

As used herein and by way of example and not by limitation, "hardware" can include a combination of discrete components, an integrated circuit, an application-specific integrated circuit, a field programmable gate array, a general purpose processing or server platform, or other suitable hardware. As used herein and by way of example and not by limitation, "software" can include one or more objects, agents, threads, lines of code, subroutines, separate software applications, one or more lines of code or other suitable software structures operating in one or more software applications or on one or more processors, or other suitable software structures. In one example embodiment, software can include one or more lines of code or other suitable software structures operating in a general purpose software application, such as an operating system, and one or more lines of code or other suitable software structures operating in a specific purpose software application.

<FIG> is a PD system <NUM> schematic embodiment where the DBC mechanism is implemented by a state machine shown as <NUM>' without the port controller's <NUM>', <NUM>' GPIO4 pins directly connected together as in PD system <NUM> described above, according to an example embodiment. Instead, for PD system <NUM> the port controller's <NUM>', <NUM>' VPWR pin is connected through a resistor <NUM> to the VBUS output pin of a receptacles <NUM> and <NUM>, and the GPIO4 pin from one of the port controllers <NUM>', <NUM>' is connected to a gate of a MOSFET <NUM> (shown as P-channel MOSFETs) for allowing its GPIO4 pin to connect to VPWR pin of the other port controller <NUM>', <NUM>'. The cross-connection of GPIO4 and VPWR pins through the MOSFET <NUM> functions to pull the VPWR pin low of one port controller when the GPIO4 pin of the other port controller is low.

The MOSFET <NUM> is added because the GPIO4 pin may not be able tolerate the high voltage that the VPWR pin may see during operation, so that the GPIO4 pin instead drives the gate of MOSFET <NUM> and the drain of the MOSFET <NUM> is connected to the VPWR pin (and source of the MOSFET <NUM> to DVDD). It is noted that in the DB scenario VDD will typically be at ground potential. For PD system <NUM> as with PD system <NUM> it is the first of the respective port controllers <NUM>', <NUM>' that can provide power to the power system sink which takes control.

The resistor's <NUM> value utilized can depend on several considerations. The resistor <NUM> should be small enough so that when the current is flowing through there is not a significant voltage drop across so that the voltage at the VPWR pin is rendered too small. The resistor <NUM> should also be large enough so that it does not draw more than about 500mA. So assuming the port controller draws 1mA through the VPWR pin a resistance for resistor <NUM> of about <NUM> ohms will keep the IR drop in normal operation below 100mV, and the current through the resistor <NUM> when GPIO4 pin is pulled low will be roughly 50mA. The power dissipated in the resistor <NUM> will be about <NUM>.

An example port controller coordination method <NUM> is illustrated in <FIG> which utilizes a disclosed port controller(s) having a state-machine <NUM> within a system arrangement such PD system <NUM> shown in <FIG> described above having port controllers <NUM> and <NUM>. In step <NUM> the port controller first enters the DB scenario because it's VBUS and VPWR pins if tied together (or more generally implemented with one of these pins) have been sensed to be high and VDD shown biased at a nominal <NUM> volts is sensed to be low. Step <NUM> comprises the port controller pulling up on its GPIO pin shown as a GPIO4 pin through a large resistance shown as provided by the internal pull-up block <NUM> in <FIG>.

Step <NUM> comprises the port controller starting a timer set for time period T1 (T1 timer) and monitoring its GPIO4 pin for the time period T1. If the GPIO4 pin is pulled low indicating that another port controller is supplying power to the power system sink (load) at any time during T1 then the port controller either resets so that the port controller goes to sleep (shuts off all internal circuitry and places itself in a low-current standby mode to conserve power) for some time, then starts method <NUM> over again where the state machine can either return to step <NUM> if GPIO4 is low or go into a low-power state for a short time then return to step <NUM>. Alternatively, the state machine can continue to monitor its GPIO4 pin until it is not pulled low for at least the duration T1. If the GPIO4 pin was not low for at least time T1 so that the T1 timer expires (step <NUM>), then in step <NUM> another timer tGlobal starts counting up from zero.

Next, in step <NUM> the GPIO4 pin is pulled low for a time tPulse and a tPulse timer is started. After a time of tPulse has elapsed, the tPulse timer expires in step <NUM>, and in step <NUM> the GPIO4 pin is released (pulled low) and given a time tPause timed by a tPause timer to rise to the pullup voltage. In step <NUM> the tPause timer expires. Then in step <NUM> the GPIO4 pin is monitored for a time tCycle and a tCycle timer started, and if the GPIO4 pin goes low at any time while being monitored in this state indicating the other port controller is currently supplying power to the power system sink, the port controller either resets and returns to the beginning of method <NUM> (i.e., after going to sleep to save power for some time) or as shown in <FIG> returns to step <NUM> including turning off its gate driver pin (in case it was turned on prior).

After a time of tCycle elapses if the tGlobal timer is greater than a time T2 shown as step <NUM>, then the GDN pin is turned on in step <NUM> which results in its associated power path switch 215a or 215b closing so that the power on its VBUS pin is supplied to the power system sink (or load) <NUM>. Otherwise if in step <NUM> tGlobal is found to be less than T2 and the tGlobal timer expires the method returns to step <NUM> where the GPIO4 pin is pulsed low again and the tPulse timer is again started. Following step <NUM> (GDN gate driver pin turned on) the method again returns to step <NUM> where the GPIO4 pin is pulsed low again and the tPulse timer is started.

The time tCycle used in step <NUM> is unique for each port controller <NUM> and <NUM> to guarantee collisions are avoided, since each port controller can have a unique I2C slave address in this system (e.g., set by the bias applied to the MODE or AD pins) that is used to determine unique tCycle values for each port controller to hard code the I2C slave address into the port controllers. Each port controller can use the same respective values for tPulse, tPause, T1, tGlobal, and T2. The difference between each tCycle time for the respective port controllers should be larger than the time required for the DBC wire <NUM> to rise to its high voltage level after being pulled low. Larger values of the time tPulse make implementations easier, but require a longer time before the GDN pin will be turned on. The time T1 should be longer than the longest value of tCycle plus tPulse. The time T2 provides extra margin against any practical issues such as both port controllers starting their first pulse at exactly the same time and may be set to the same value as T1.

For PD system <NUM>, the state-machine <NUM>' functions largely the same as port controller coordination method <NUM> for port controllers <NUM> and <NUM> in PD system <NUM> described above relative to <FIG> except for PD system <NUM> there is no need for the state machine <NUM>' to monitor its GPIO4 pin. Accordingly, in step <NUM> there is no need for the state machine <NUM>' to monitor the GPIO4 pin, just delay for T1. When GPIO4 pin would have been pulled low in step <NUM> in method <NUM>, the VPWR pin would be pulled low instead which will cause the port controller to reset. Likewise in step <NUM> there is no need to monitor the GPIO4 pin.

The port controller may also only enter into the DB scenario as described above if the power source it is connected to via the receptacle is able to provide sufficient power for the system. An example power source is an AC/DC power supply that is connected through the receptacle. For example, some USB Type-C downward facing ports are only capable of supplying about 900mA. In some systems that the available power is not sufficient, the port controllers in those systems may be connected to a downward facing port capable of supplying <NUM> A or <NUM> A before pulling GPIO4 low or turning on its gate driver pin. In such systems when less than <NUM> A (or some other minimum threshold current level) is available from the power source the port controller can go to sleep for a short time and then retry since the attached power source (e.g. an adaptor connected through the receptacle) can increase the current it is advertising (providing) at any time.

Disclosed port controllers in one particular application may be embodied as a <NUM>-V to <NUM>-V High-Efficiency Adjustable Power-Limiting Hot-Swap Controller With Current Monitor and Overvoltage Protection that has a gate driver pin for driving the gate(s) of N-channel MOSFETs for external power-path switches. Other example applications include notebook/laptop computers with multiple USB Type-C ports. One particular example port controller includes two pins for controlling the external N-channel MOSFETs (of power-path switches), Over Voltage Protection (OVP) and Over Current Protection (OCP) protection, and a USB PD physical layer.

Claim 1:
A port controller (<NUM>), comprising:
an input/output IO pin (GPIO4) coupleable to an IO pin of an other port controller (<NUM>);
a receptacle supply pin configured to receive power from a voltage bus (VBUS) of a receptacle (<NUM>);
a VDD supply pin coupleable to a VDD supply;
a gate driver pin (GDN) configured to drive a control node of a power path switch (215a), the power path switch (215a) comprising an output coupled to a power system sink (<NUM>);
a control input (I2C) for coupling to a control output of a processor (<NUM>) which serves as a master;
the port controller (<NUM>) comprising a state machine (<NUM>) configured to perform a dead-battery control DBC algorithm upon sensing a dead-battery DB condition, the DB condition comprising sensing a voltage on said receptacle supply pin and a lack of voltage on said VDD supply pin, said DBC algorithm configured to enable the communication with the other port controller (<NUM>) to directly communicate with the other port controller (<NUM>) via the IO pin (GPIO4) so that only one port controller (<NUM>, <NUM>) takes control to provide power to the power system sink (<NUM>);
the DBC algorithm comprising: sending a control signal to turn on said gate driver pin (GDN) to close said power path switch (215a) to exclusively provide said power from the voltage bus (VBUS) to said power system sink (<NUM>).