Patent Description:
The data rate of high-speed signal links determines system performance of all kinds of devices, ranging from smart phones to super computers. Generational changes of devices involves the increase of data rates of signal links. One example bottleneck is that most (if not all) signal links depend on an open eye diagram to function correctly. A voltage comparator/slicer determines the received bit value between logic ○ and <NUM> by comparing the sampled voltage at a certain timing point to a reference voltage.

Thus this mechanism requires the eye diagram be open with a certain amount of margin. There are numerous factors, including jitter, noise, crosstalk, channel bandwidth/filtering, etc. that can shrink the eye diagram. When the eye diagram is closed or the margin is insufficient, the receiver will fail to recover the correct data that are transferred. Currently, various equalization (EQ) schemes are used to improve the eye diagram, including transmitter linear EQ (TXLE), continuous time linear EQ (CTLE), and decision feedback EQ (DFE). These EQ schemes can improve the data rate by some amount but will fail when the degrading factors are too severe or the data rate is further increased.

Document <CIT> discloses a waveform equalizer using a neural network.

Document <CIT> discloses a waveform equalizer apparatus formed of neural network, and method of designing same.

Document <CIT> discloses a procedure for equalizing distorted data signals.

Examples of receiver apparatuses and systems are detailed as follows. Features of the present disclosure are recited.

According to one aspect of the present disclosure, a receiver apparatus configured to receive a data waveform (<NUM>) from across a data link (<NUM>), the receiver apparatus (<NUM>) comprising: a neural network circuit (<NUM>) to: receive a data waveform from the data link; sample the data waveform at a plurality of timing locations of the data waveform; and determine a single bit value (<NUM>) for the data waveform based on the sample of the waveform form the plurality of timing locations, wherein the neural network circuit comprises a plurality of delay circuits (<NUM>) to delay the data waveform, the plurality of delay circuits comprising: a first delay circuit (302c) in series with a second delay circuit (302b, 302a); wherein the neural network circuit comprises a first sampling element (<NUM>) at an input to the first delay circuit, a second sampling input element (304c) at an output of the first delay circuit, and a third sampling element (304b, 304a) at an output of the second delay circuit; and the receiver apparatus further comprising a plurality of activation function circuit elements (<NUM>) to apply an activation function to one or more samples of the data waveform; and the receiver apparatus further comprising an output summer circuit (<NUM>), wherein each of the plurality of activation function circuit elements is coupled to the output summer circuit, the output summer circuit is to sum the outputs of each of the plurality of activation function circuit elements and is to output the single bit value representative of an interested bit from the data waveform.

In some examples, the receiver apparatus can also include a clock recovery circuit element to recover a clock signal received with the data waveform and output the clock signal to the neural network circuit, the neural network circuit may be configured to use the clock signal to delay the waveform.

According to one aspect of the present disclosure, a system comprising: a data transmitter (<NUM>) to transmit a data waveform (<NUM>); a data receiver (<NUM>) to receive a data waveform from the data transmitter; and a data link (<NUM>) coupling the data transmitter with the data receiver; the data receiver comprising: a neural network circuit (<NUM>) to: receive a data waveform from the data link; the neural network circuit further is characterized in that to sample the data waveform at a plurality of timing locations of the data waveform; and determine a single bit value (<NUM>) for the data waveform based on the sample of the waveform form the plurality of timing locations, wherein the neural network circuit comprises a plurality of delay circuits (<NUM>) to delay the data waveform, the plurality of delay circuits comprising: a first delay circuit (302c) in series with a second delay circuit (302b, 302a); wherein the neural network circuit comprises a first sampling element (<NUM>) at an input to the first delay circuit, a second sampling element (304c) at an output of the first delay circuit, and a third sampling element (304b, 304a) at an output of the second delay circuit the system further comprising a plurality of activation function circuit elements (<NUM>) to apply an activation function to one or more samples of the data waveform; and the system further comprising an output summer circuit (<NUM>), wherein each of the plurality of activation function circuit elements is coupled to the output summer circuit, the output summer circuit is to sum the outputs of each of the plurality of activation function circuit elements and is to output the single bit value representative of an interested bit from the data waveform.

In some examples, the system, can also include a clock recovery circuit element to recover a clock signal received with the data waveform and output the clock signal to the neural network circuit, the neural network circuit configured to use the clock signal to delay the waveform.

In some examples, the system, wherein the data link may comprise a high speed data link.

The invention provides subject-matter as defined in the independent claims, Preferred embodiments thereof are defined in the dependent claims.

In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present disclosure.

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a 'green technology' future balanced with performance considerations.

As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the disclosure described herein.

This disclosure describes a receiver architecture that uses a neural network-based interpreter circuit that does not depend on an eye diagram for resolving a received bit value.

<FIG> is a schematic block diagram of a system <NUM> that includes a transmitter and receiver coupled by a high speed data link in accordance with embodiments of the present disclosure. The transmitter <NUM> includes a waveform generator <NUM> that can output a waveform representative of data to be transmitted across the high speed data link <NUM>. The transmitter <NUM> also includes a transmission (TX) buffer <NUM> for buffering data transmitted from the transmitter <NUM>. The receiver <NUM> includes a neural network interpreter circuit <NUM>. In embodiments, neural network (NN) circuit <NUM>, which is referred to herein as an NN interpreter <NUM>, is used to replace the EQ mechanism. The NN interpreter <NUM> takes the received voltage waveform as an input. The waveform is sampled at multiple timing points in a few unit intervals (UI) adjacent to the interested bit (i.e., unit intervals both before and after the interested bit), and directly determines the logic value of the interested bit. The use of the NN interpreter facilitates bit resolution even when the eye diagram is completely closed with the traditional EQ mechanism.

Turning briefly to <FIG> is an example graphical illustration of a waveform <NUM> illustrating sampling points <NUM> of the waveform and an example interested bit <NUM> in accordance with embodiments of the present disclosure. The interested bit <NUM> of waveform <NUM> is located in a unit interval spanning <NUM> and <NUM> UIs. The waveform can be sampled at <NUM> points using adjacent bits spanning UI <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>, as well as sampling points at the interested bit between <NUM>-<NUM>.

The input waveform <NUM> is sampled at different unit intervals adjacent to the interested bit <NUM>. Samples are taken at a predetermined number of UIs before and after the interested bit <NUM>, and the interested bit <NUM> is also sampled. The sampling makes use of a clock that is associated with the incoming waveform. The input to the NN interpreter <NUM> includes sampled voltage values of the waveform received by the receiver <NUM>. The NN interpreter <NUM> outputs the logic value of the interested bit (e.g., a <NUM> or a <NUM>). The NN interpreter <NUM> can provide better performance than the EQ mechanism because the NN interpreter <NUM> determines each logic bit value from multiple samples in the input waveform, whereas the EQ mechanism relies on a slicer to sample the voltage at a single timing point for each bit. Compared to the traditional EQ mechanism, the NN interpreter is more immune to jitter, noise, and TX/RX nonlinearity, and thus can achieve much higher data rate.

<FIG> is a schematic block diagram of a synchronous system <NUM> that transmits a data waveform separately from a corresponding clock signal over a high speed data link in accordance with embodiments of the present disclosure. In system <NUM>, the data and associated synchronized clock are transmitted separately across the high speed data link <NUM>. The NN interpreter <NUM> can receive the data waveform and the clock signal as separate inputs into the NN interpreter <NUM>. <FIG> is a schematic block diagram of an asynchronous system <NUM> wherein the data and clock signals are transmitted over a single high speed data link <NUM> in accordance with embodiments of the present disclosure. In system <NUM>, the receiver <NUM> uses a clock recovery circuit element <NUM> that is configured to extract the clock signal from the data stream and inputs the clock signal to the NN interpreter <NUM>. The NN interpreter <NUM> uses the received clock signal to determining sampling points near the interested bit as well as the interested bit location.

The receiver <NUM> uses the NN interpolator <NUM> to recover the data symbols directly from the received signal. The neural network circuitry essentially handles a pattern recognition problem for determining the bit value based on neighboring voltage values across a set of unit intervals sampled from the waveform. Time-domain voltage waveforms are used as an example in this document but this disclosure also contemplates being applied to other forms of signals as well.

<FIG> is a schematic diagram of an example neural network interpreter circuit <NUM> in accordance with embodiments of the present disclosure. The NN interpreter circuit <NUM> includes one or more delay circuit elements 302a-302c. The delay circuit elements can be implemented as a complementary metal oxide semiconductor (CMOS) circuit or other type of circuit element. The number of delay circuit elements can depend on the number of samples from the waveform are desired. For example, the number of delay circuit elements 302a-302c can equal m-<NUM>, where m is the number of samples from the waveform desired for the neural network input. The multiple samples from the input waveform are obtained from the series of analog delay blocks 302a-302c, which are labeled with "T. " The delay blocks are a chain of delay components. The delay components provide voltage sampling points from an input waveform. The waveform propagates through the delay chain. Waveform samples are taken at each point represented by I<NUM>. The time delay of each block is one mth of the unit interval, and m is the number of samples per UI.

The input waveform can be sampled at sampling elements 304a-<NUM> (I1-Im). The samples can undergo gain through gain elements <NUM>. Each gain element can include gain multipliers. One example implementation of the gain element is to use a multiplying digital-to-analog converter (MDAC), whose output is the product of the analog input voltage and one or more multiplication coefficients determined through training. For a <NUM>-bit MDAC with differential current output, current output is most convenient for the successive summer circuits, which will convert the current into voltage. In case a voltage output is necessary, a current-voltage converter can be added as the output stage. The implementation of the neural network in CMOS process is also existing technology. The training is done by using a certain number of bit patterns. For applications in typical signal links used in computer systems, like memory and high-speed differential interfaces, the training process only needs to be done once at factory before the product is shipped.

The activation layer of the NN interpreter <NUM> includes one or more activation layer circuit elements 308a-308n (H1-Hn) that each include two aspects: first, an activation function is applied to the input from the gain branches from each sampling point; second, the inputs, after the activation function is applied, as summed by a summer circuit element. An example activation function implemented using a hardware circuit element can include a CMOS very large scale integrated (VLSI) Hyperbolic Tangent Function circuit element. Other types of hardware implemented activation functions can also be used. The output of each activation layer element can be provided to a single output element <NUM>, which sums the outputs by a summer circuit element.

Advantages facilitated by the present disclosure are readily apparent to those of skill in the art. Among the advantages are:.

<FIG> is a process flow diagram <NUM> for resolving a bit value based on sampling adjacent bits using a neural network circuit in accordance with embodiments of the present disclosure. A data waveform can be received by a neural network-based circuit (NN interpreter) at a receiver from across a data link (<NUM>). A clock signal can also be received at the NN interpreter (<NUM>). The clock signal can be part of the data waveform, in which case the clock signal can be recovered by a recovery circuit, or the clock signal can be sent separately from the data waveform. The data waveform can be sampled by propagating the data waveform through a delay circuit (<NUM>). The delay circuit can include a plurality of delay circuit blocks that allow for sampling the waveform at different timing points (or sampling points) across the waveform. The delay circuit blocks can make use of the received clock signal to align the timing of the delay circuit blocks with the waveform.

The waveform voltage or current can be sampled at the interested bit and at neighboring bits (<NUM>). The waveform can be sampled at several timing points per unit interval (e.g., multiple sampling points per bit). A gain can be applied for each sampling point (<NUM>). The gain coefficients can be determined based on an initial training of the NN interpreter. The training is done by using a certain number of bit patterns. For applications in typical signal links used in computer systems, like memory and high-speed differential interfaces, the training process only needs to be done once at factory before the product is shipped.

At an activation layer of circuitry, each gain-modified sample is received by an activation function circuit, which is a circuit element that can apply an activation function to the received samples (<NUM>). There are N activation circuits and M samples. Each of the N activation circuits receives each of the M samples, and each of the M samples undergoes a gain via a gain branch interconnecting each M sample to each N activation circuit. The gain coefficients for each of the M samples can be different or the same, and each gain coefficient is determined through training. The received samples upon which activation function are applied are then summed by a summer circuit (<NUM>). All of the summed activation function-applied samples are summed as an output, the output representing a resolved bit for the interested bit (<NUM>).

Referring to <FIG>, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor <NUM> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor <NUM>, in one embodiment, includes at least two cores-core <NUM> and <NUM>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <NUM> may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor <NUM>, as illustrated in <FIG>, includes two cores-core <NUM> and <NUM>. Here, core <NUM> and <NUM> are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core <NUM> includes an out-of-order processor core, while core <NUM> includes an in-order processor core. However, cores <NUM> and <NUM> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core <NUM> are described in further detail below, as the units in core <NUM> operate in a similar manner in the depicted embodiment.

As depicted, core <NUM> includes two hardware threads 501a and 501b, which may also be referred to as hardware thread slots 501a and 501b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <NUM> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 501a, a second thread is associated with architecture state registers 501b, a third thread may be associated with architecture state registers 502a, and a fourth thread may be associated with architecture state registers 502b. Here, each of the architecture state registers (501a, 501b, 502a, and 502b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 501a are replicated in architecture state registers 501b, so individual architecture states/contexts are capable of being stored for logical processor 501a and logical processor 501b. In core <NUM>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <NUM> may also be replicated for threads 501a and 501b. Some resources, such as re-order buffers in reorder/retirement unit <NUM>, ILTB <NUM>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <NUM>, execution unit(s) <NUM>, and portions of out-of-order unit <NUM> are potentially fully shared.

Processor <NUM> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <FIG>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <NUM> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <NUM> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <NUM> to store address translation entries for instructions.

Core <NUM> further includes decode module <NUM> coupled to fetch unit <NUM> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 501a, 501b, respectively. Usually core <NUM> is associated with a first ISA, which defines/specifies instructions executable on processor <NUM>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <NUM> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders <NUM>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <NUM>, the architecture or core <NUM> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders <NUM>, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders <NUM> recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block <NUM> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 501a and 501b are potentially capable of out-of-order execution, where allocator and renamer block <NUM> also reserves other resources, such as reorder buffers to track instruction results. Unit <NUM> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <NUM>. Reorder/retirement unit <NUM> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block <NUM>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) <NUM> are coupled to execution unit(s) <NUM>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores <NUM> and <NUM> share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface <NUM>. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache-last cache in the memory hierarchy on processor <NUM>-such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache-a type of instruction cache-instead may be coupled after decoder <NUM> to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor <NUM> also includes on-chip interface module <NUM>. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor <NUM>. In this scenario, on-chip interface <NUM> is to communicate with devices external to processor <NUM>, such as system memory <NUM>, a chipset (often including a memory controller hub to connect to memory <NUM> and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus <NUM> may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory <NUM> may be dedicated to processor <NUM> or shared with other devices in a system. Common examples of types of memory <NUM> include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device <NUM> may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor <NUM>. For example in one embodiment, a memory controller hub is on the same package and/or die with processor <NUM>. Here, a portion of the core (an on-core portion) <NUM> includes one or more controller(s) for interfacing with other devices such as memory <NUM> or a graphics device <NUM>. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface <NUM> includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link <NUM> for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory <NUM>, graphics processor <NUM>, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor <NUM> is capable of executing a compiler, optimization, and/or translator code <NUM> to compile, translate, and/or optimize application code <NUM> to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (<NUM>) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (<NUM>) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (<NUM>) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (<NUM>) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (<NUM>) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (<NUM>) a combination thereof.

One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot- Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.

Referring to <FIG>, an embodiment of a fabric composed of point-to-point Links that interconnect a set of components is illustrated. System <NUM> includes processor <NUM> and system memory <NUM> coupled to controller hub <NUM>. Processor <NUM> includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor <NUM> is coupled to controller hub <NUM> through front-side bus (FSB) <NUM>. In one embodiment, FSB <NUM> is a serial point-to-point interconnect as described below. In another embodiment, link <NUM> includes a serial, differential interconnect architecture that is compliant with different interconnect standard.

System memory <NUM> includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system <NUM>. System memory <NUM> is coupled to controller hub <NUM> through memory interface <NUM>. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub <NUM> is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub <NUM> include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor <NUM>, while controller <NUM> is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex <NUM>.

Here, controller hub <NUM> is coupled to switch/bridge <NUM> through serial link <NUM>. Input/output modules <NUM> and <NUM>, which may also be referred to as interfaces/ports <NUM> and <NUM>, include/implement a layered protocol stack to provide communication between controller hub <NUM> and switch <NUM>. In one embodiment, multiple devices are capable of being coupled to switch <NUM>.

Switch/bridge <NUM> routes packets/messages from device <NUM> upstream, i.e. up a hierarchy towards a root complex, to controller hub <NUM> and downstream, i.e. down a hierarchy away from a root controller, from processor <NUM> or system memory <NUM> to device <NUM>. Switch <NUM>, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device <NUM> includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device <NUM> may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

Graphics accelerator <NUM> is also coupled to controller hub <NUM> through serial link <NUM>. In one embodiment, graphics accelerator <NUM> is coupled to an MCH, which is coupled to an ICH. Switch <NUM>, and accordingly I/O device <NUM>, is then coupled to the ICH. I/O modules <NUM> and <NUM> are also to implement a layered protocol stack to communicate between graphics accelerator <NUM> and controller hub <NUM>. Similar to the MCH discussion above, a graphics controller or the graphics accelerator <NUM> itself may be integrated in processor <NUM>.

Turning to <FIG> an embodiment of a layered protocol stack is illustrated. Layered protocol stack <NUM> includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCie stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below in reference to <FIG> are in relation to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack <NUM> is a PCIe protocol stack including transaction layer <NUM>, link layer <NUM>, and physical layer <NUM>. An interface, such as interfaces <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, may be represented as communication protocol stack <NUM>. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction Layer <NUM> and Data Link Layer <NUM> to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer <NUM> representation to the Data Link Layer <NUM> representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer <NUM> of the receiving device.

In one embodiment, transaction layer <NUM> is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer <NUM> and physical layer <NUM>. In this regard, a primary responsibility of the transaction layer <NUM> is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer <NUM> typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.

In addition PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in Transaction Layer <NUM>. An external device at the opposite end of the link, such as controller hub <NUM> in <FIG>, counts the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. An advantage of a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a <NUM>-bit address, or a long address format, such as <NUM>-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, transaction layer <NUM> assembles packet header/payload <NUM>. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.

Quickly referring to <FIG>, an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor <NUM> is a mechanism for carrying transaction information. In this regard, transaction descriptor <NUM> supports identification of transactions in a system. Other potential uses include tracking modifications of default transaction ordering and association of transaction with channels.

Transaction descriptor <NUM> includes global identifier field <NUM>, attributes field <NUM> and channel identifier field <NUM>. In the illustrated example, global identifier field <NUM> is depicted comprising local transaction identifier field <NUM> and source identifier field <NUM>. In one embodiment, global transaction identifier <NUM> is unique for all outstanding requests.

According to one implementation, local transaction identifier field <NUM> is a field generated by a requesting agent, and it is unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier <NUM> uniquely identifies the requestor agent within a PCIe hierarchy. Accordingly, together with source ID <NUM>, local transaction identifier <NUM> field provides global identification of a transaction within a hierarchy domain.

Attributes field <NUM> specifies characteristics and relationships of the transaction. In this regard, attributes field <NUM> is potentially used to provide additional information that allows modification of the default handling of transactions. In one embodiment, attributes field <NUM> includes priority field <NUM>, reserved field <NUM>, ordering field <NUM>, and no-snoop field <NUM>. Here, priority sub-field <NUM> may be modified by an initiator to assign a priority to the transaction. Reserved attribute field <NUM> is left reserved for future, or vendor-defined usage. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.

In this example, ordering attribute field <NUM> is used to supply optional information conveying the type of ordering that may modify default ordering rules. According to one example implementation, an ordering attribute of "<NUM>" denotes default ordering rules are to apply, wherein an ordering attribute of "<NUM>" denotes relaxed ordering, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field <NUM> is utilized to determine if transactions are snooped. As shown, channel ID Field <NUM> identifies a channel that a transaction is associated with.

Link layer <NUM>, also referred to as data link layer <NUM>, acts as an intermediate stage between transaction layer <NUM> and the physical layer <NUM>. In one embodiment, a responsibility of the data link layer <NUM> is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer <NUM> accepts TLPs assembled by the Transaction Layer <NUM>, applies packet sequence identifier <NUM>, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC <NUM>, and submits the modified TLPs to the Physical Layer <NUM> for transmission across a physical to an external device.

In one embodiment, physical layer <NUM> includes logical sub block <NUM> and electrical sub-block <NUM> to physically transmit a packet to an external device. Here, logical sub-block <NUM> is responsible for the "digital" functions of Physical Layer <NUM>. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block <NUM>, and a receiver section to identify and prepare received information before passing it to the Link Layer <NUM>.

Physical block <NUM> includes a transmitter and a receiver. The transmitter is supplied by logical sub-block <NUM> with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block <NUM>. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames <NUM>. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although transaction layer <NUM>, link layer <NUM>, and physical layer <NUM> are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, an port/interface that is represented as a layered protocol includes: (<NUM>) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

Referring next to <FIG>, an embodiment of a PCIe serial point to point fabric is illustrated. Although an embodiment of a PCIe serial point-to-point link is illustrated, a serial point-to-point link is not so limited, as it includes any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe link includes two, low-voltage, differentially driven signal pairs: a transmit pair <NUM>/<NUM> and a receive pair <NUM>/<NUM>. Accordingly, device <NUM> includes transmission logic <NUM> to transmit data to device <NUM> and receiving logic <NUM> to receive data from device <NUM>. In other words, two transmitting paths, i.e. paths <NUM> and <NUM>, and two receiving paths, i.e. paths <NUM> and <NUM>, are included in a PCIe link.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device <NUM> and device <NUM>, is referred to as a link, such as link <NUM>. A link may support one lane - each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as1, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or wider.

A differential pair refers to two transmission paths, such as lines <NUM> and <NUM>, to transmit differential signals. As an example, when line <NUM> toggles from a low voltage level to a high voltage level, i.e. a rising edge, line <NUM> drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.

Note that the apparatus', methods', and systems described above may be implemented in any electronic device or system as aforementioned. As specific illustrations, the figures below provide exemplary systems for utilizing the disclosure as described herein. As the systems below are described in more detail, a number of different interconnects are disclosed, described, and revisited from the discussion above. And as is readily apparent, the advances described above may be applied to any of those interconnects, fabrics, or architectures.

Referring now to <FIG>, shown is a block diagram of an embodiment of a multicore processor. As shown in the embodiment of <FIG>, processor <NUM> includes multiple domains. Specifically, a core domain <NUM> includes a plurality of cores 1030A-1030N, a graphics domain <NUM> includes one or more graphics engines having a media engine <NUM>, and a system agent domain <NUM>.

In various embodiments, system agent domain <NUM> handles power control events and power management, such that individual units of domains <NUM> and <NUM> (e.g. cores and/or graphics engines) are independently controllable to dynamically operate at an appropriate power mode/level (e.g. active, turbo, sleep, hibernate, deep sleep, or other Advanced Configuration Power Interface like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains <NUM> and <NUM> may operate at different voltage and/or power, and furthermore the individual units within the domains each potentially operate at an independent frequency and voltage. Note that while only shown with three domains, understand the scope of the present disclosure is not limited in this regard and additional domains may be present in other embodiments.

As shown, each core <NUM> further includes low level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory that is formed of a plurality of units or slices of a last level cache (LLC) 1040A-1040N; these LLCs often include storage and cache controller functionality and are shared amongst the cores, as well as potentially among the graphics engine too.

As seen, a ring interconnect <NUM> couples the cores together, and provides interconnection between the core domain <NUM>, graphics domain <NUM> and system agent circuitry <NUM>, via a plurality of ring stops 1052A-1052N, each at a coupling between a core and LLC slice. As seen in <FIG>, interconnect <NUM> is used to carry various information, including.

As further depicted, system agent domain <NUM> includes display engine <NUM> which is to provide control of and an interface to an associated display. System agent domain <NUM> may include other units, such as: an integrated memory controller <NUM> that provides for an interface to a system memory (e.g., a DRAM implemented with multiple DIMMs; coherence logic <NUM> to perform memory coherence operations. Multiple interfaces may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) <NUM> interface is provided as well as one or more PCie™ interfaces <NUM>. The display engine and these interfaces typically couple to memory via a PCie™ bridge <NUM>. Still further, to provide for communications between other agents, such as additional processors or other circuitry, one or more other interfaces (e.g. an Intel® Quick Path Interconnect (QPI) fabric) may be provided.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.

Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase 'to' or 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a <NUM> or a <NUM> during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a <NUM> or <NUM>. Instead, the logic gate is one coupled in some manner that during operation the <NUM> or <NUM> output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases 'capable of/to,' and or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as <NUM>'s and <NUM>'s, which simply represents binary logic states. For example, a <NUM> refers to a high logic level and <NUM> refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of <NUM> and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magnetooptical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure.

Claim 1:
A receiver apparatus configured to receive a data waveform (<NUM>) from across a data link (<NUM>), the receiver apparatus (<NUM>) comprising:
a neural network circuit (<NUM>) to:
receive a data waveform from the data link;
sample the data waveform at a plurality of timing locations of the data waveform; and
determine a single bit value (<NUM>) for the data waveform based on the sample of the waveform form the plurality of timing locations,
wherein the neural network circuit comprises a plurality of delay circuits (<NUM>) to delay the data waveform, the plurality of delay circuits comprising:
a first delay circuit (302c) in series with a second delay circuit (302b, 302a); wherein the neural network circuit comprises a first sampling element (<NUM>) at an input to the first delay circuit, a second sampling element (304c) at an output of the first delay circuit, and a third sampling element (304b, 304a) at an output of the second delay circuit; and
the receiver apparatus further comprising a plurality of activation function circuit elements (<NUM>) to apply an activation function to one or more samples of the data waveform; and
the receiver apparatus further comprising an output summer circuit (<NUM>), wherein each of the plurality of activation function circuit elements is coupled to the output summer circuit, the output summer circuit is to sum the outputs of each of the plurality of activation function circuit elements and is to output the single bit value representative of an interested bit from the data waveform.