Patent Description:
In one example, a circuit includes first, second, and third switch assemblies, a buffer, and a bulk biasing circuit. The first switch assembly has a first input node and a first output node. The second switch assembly has a second input node and a second output node. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node. The third output node is coupled to the first output node. The third switch assembly includes a first transistor that includes a bulk. The buffer has a buffer input and a buffer output. The buffer input is coupled to the first output node, and the buffer output is coupled to the third switch assembly. The bulk biasing circuit is coupled to the bulk of the first transistor. The bulk biasing circuit is configured to bias the bulk of the first transistor at a first bias voltage responsive to a voltage on the input node being above a first voltage level, and to bias the bulk of the first transistor at a second bias voltage responsive to the voltage on the input node being below a second voltage level.

A multiplexer may include a number of independent channels that pass data from respective inputs to a single output, and, in a sensing application, the multiplexer may pass data from a set of sensors coupled to the inputs to a processor coupled to the output. Control signals from a multiplexer controller enable one of the channels, while those channels corresponding to sensors not intending to be processed by a sensor processing system at a given point in time are disabled. Each channel of the multiplexer comprises solid-state switches (transistors) that are used to enable and disable the channel. When a transistor is "on," current can be conducted through the transistor. When a transistor is "off," the principal conducting pathway (e.g., the channel in a metal oxide semiconductor field effect transistor) is off and generally does not conduct current. However, leakage current may conduct through the transistor when the transistor is off.

In many applications, transistor leakage current is not problematic. In other applications, however, leakage current can be a problem. For example, in the application noted above in which multiple sensors are coupled to a processing system through a multiplexer, even when the transistors are off for a channel that has been disabled, leakage current can still flow through that channel's transistors. If the sensor connected to that channel has a large output impedance, even a small amount of leakage current can cause a significant voltage to develop across the sensor due to the sensor's large output impedance. The voltage undesirably produced in the disabled channel can modify (e.g., add to) the voltage produced by the sensor whose channel is enabled, thereby undesirably altering the sensor signal intended to be processed.

The examples described herein are directed to a multiplexer in which each channel of the multiplexer includes multiple metal oxide semiconductor field effect transistors (MOS transistors). One or more of the multiplexer's channels biases the bulk of at least one of its MOS transistors to reduce the leakage current that might otherwise be present for a low amplitude voltage generated by the sensor on the channel that is enabled. Further, a buffer is provided whose input coupled to the output of the multiplexer. The output of the buffer is coupled to one or more of the multiplexer's channels. When a given channel is off, rather than grounding an internal node of the given channel, the internal node is coupled to the multiplexer's output voltage level via the buffer. As such, the drain-to-source potential difference across a MOS transistor in each "off" channel is approximately <NUM> V and thus very little, if any leakage current will flow between the drain and source of the transistor.

<FIG> shows an example of a system <NUM> comprising a multiplexer ("mux") circuit <NUM> coupled to an operational amplifier ("op amp") <NUM>. The mux circuit <NUM> comprises multiple channels. In this example, the mux circuit <NUM> includes five channels shown at <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Each channel is coupled to a respective input, and the inputs of channels <NUM>-<NUM> are designated inp1, inp2, inp3, inp4, and inp5, respectively. A device such as a sensor can be connected to each channel input. In this example, five sensors (S1, S2, S3, S4, S5) can be coupled to the op amp <NUM> through the mux circuit <NUM>. Via control signals from a mux controller <NUM> (in response to a channel selection signal <NUM>) to the mux circuit <NUM>, one channel at a time is enabled (on), and the remaining four channels are disabled (off). The signal from the sensor whose channel is enabled is provided through the mux circuit <NUM> to node N1 and thus to the non-inverting (+) input of the op amp <NUM>. The op-amp <NUM> has its output connected to its inverting (-) input, and thus the op-amp <NUM> is configured for unity gain. Other configurations of the op-amp (e.g., gain greater than <NUM>) are possible as well. The output from the op-amp <NUM> is coupled to a processing system <NUM> to process the op-amp's output signal. The processing system <NUM> may include a microprocessor, a filter, or other types of processing electronics.

The mux circuit <NUM> includes a switch assembly for each channel. Channel <NUM> has switch assembly <NUM>, and channels <NUM>-<NUM> have switch assemblies <NUM>-<NUM>, respectively. Input inp1 can be coupled to node N1 when switch assembly <NUM> is "on". Similarly, any of inputs inp2-inp5 can be coupled to node N1 when their respective switch assemblies <NUM>-<NUM> are on. Node N1 is connected to the op amp's non-inverting input. In this example, only one switch assembly <NUM>-<NUM> is turned on at a time, and the remaining switch assemblies are turned off.

In the example of <FIG>, each switch assembly <NUM>-<NUM> comprises three switches S1, S2, and S3. S1 and S2 are connected in series between their associated channel input and node N1. The mux controller <NUM> generates the control signals to the switches S1-S3 of the switch assemblies <NUM>-<NUM> to turn on or off each respective switch. The node between S1 and S2 is designated node N2. S3 of each switch assembly is coupled between node N2 and ground. When S3 is on, the respective node N2 is coupled to the ground potential. To turn a switch assembly on and thereby enable the channel, its switches S1 and S2 are turned on and its switch S3 is turned off. To turn a switch assembly off and thereby disable the channel, its switches S1 and S2 are turned off and its switch S3 is turned on. As shown in the example of <FIG>, S1 and S2 of switch assembly <NUM> are on and the corresponding switch S3 is off. S1 and S2 of the remaining four switch assemblies <NUM>-<NUM> are off, and their switches S3 are on. As such, channel <NUM> is enabled in this example, and channels <NUM>-<NUM> are off.

Even when a channel's switch assembly is configured to be off (its S1 and S2 are off, and its S3 is on), leakage current can still flow through S2. Leakage currents Ileak1, Ileak2, Ileak3, and Ileak4 are shown in <FIG> to represent the leakage current through S2 of off switch assemblies <NUM>-<NUM>. Part of the reason for the leakage current stems from the fact that the channel that is on (channel <NUM> in this example) provides the voltage from its input inp1 through switch assembly <NUM> to node N1, and all of the switch assemblies <NUM>-<NUM> are coupled to node N1 as shown. Thus, the voltage on node N1 from channel <NUM> is also provided to one terminal of S2 of the four off switch assemblies <NUM>-<NUM>. As the output impedance of a sensor connected to a channel input can be relatively high (e.g., hundreds of mega-ohms), even a small amount of leakage current can generate a voltage across the output impedance of that channel. The voltage due to leakage current from an off channel is additive (or subtractive depending on the direction of the leakage current) to the voltage generated by the sensor from the on channel, and thus distorts that sensor's signal.

<FIG> shows an example implementation of switch S2 of each of the switch assemblies <NUM>-<NUM>. The reason for the leakage current can be identified through a description of <FIG>. Referring to <FIG>, S2 of each switch assembly <NUM>-<NUM> includes a p-type MOS (PMOS) transistor MP1 coupled to an n-type MOS (NMOS) transistor MN1. The drains of MP1 and MN1 are connected together at node N1, and the sources of MP1 and MN1 are connected together at node N2. The gates of MP1 and MN1 are driven by control signals to turn the transistors of S2 on and off. To turn S2 on, both MP1 and MN1 are turned on. To turn S2 off, both MP1 and MN1 are turned off. In the example configuration shown in <FIG>, the gate of MN1 is driven by a low (e.g., ground) control signal, and the gate of MP1 is driven by a high control signal (shown as Vdda, which is a supply voltage). With the gate of MN1 driven low and the gate of MP1 driven high, both MP1 and MN1 are off. As such, <FIG> shows the off state for S2.

A MOS transistor has parasitic bulk diodes. <FIG> shows a drain-to-bulk diode D1 and a bulk-to-source diode D2 of MP1. As described above, the voltage on node N1 is driven by the sensor whose switch assembly is on. S2 in <FIG> represents an S2 switch of a switch assembly that is off. The voltage labeled Vin represents the voltage on node N1 from a sensor of another channel that is on (e.g., channel <NUM>). Node N2 of S2 in <FIG> receives the ground potential through S3 (which is on) of the respective switch assembly. The bulk of S2's MP1 is biased to Vdda.

S2 has multiple sources of leakage current when S2 is off. First, when Vin is <NUM> V (e.g., the voltage from the sensor coupled to the on-channel <NUM>), D1 is reverse biased, thereby causing a current Ib1 to flow through D1. As such, the leakage current Ileak (when Vin is low, e.g. <NUM> V) is equal to -Ib1 + Idsn (Idsn is the leakage current through MN1). However, Idsn may be substantially smaller than Ib1, and thus Ileak is approximately equal to -Ib1. Second, when Vin is higher (e.g., Vdda), Ileak is equal to the sum of the drain-to-source leakage currents of MP1 and MN1 (Idsp + Idsn). Both Idsp and Idsn are proportional to Vin (e.g., the larger is Vin, the larger will be Idsp and Idsn). Some examples described herein reduce the leakage current Ileak through S2 of the switch assemblies, when such switch assemblies are off, by the use of a buffer (e.g., buffer <NUM> in <FIG> and buffer <NUM> in <FIG>) as well as a bulk biasing circuit <NUM> (<FIG>).

<FIG> shows an example of a system <NUM> including mux circuit <NUM>, op amp <NUM>, and a buffer <NUM>. The sensors S1-S5, mux controller <NUM>, and processing system <NUM> are not shown for simplicity. The architecture of system <NUM> is largely the same as that of system <NUM> of <FIG>, except for the inclusion of buffer <NUM>. In system <NUM> of <FIG>, each switch S3 is coupled between its respective node N2 and ground. When S3 is on in <FIG>, the respective node N2 is grounded. Grounding node N2 results in leakage current through the MP1 and MN1 transistors of S2 when node N1 is of a sufficiently high voltage relative to ground. Buffer <NUM> of <FIG> is coupled between node N1 and switches S3 of switch assemblies <NUM>-<NUM> at node N3. The buffer <NUM> is configured for unity gain, and thus the buffer's output voltage (node N3) is equal to its input voltage (node N1). The voltage on N1 is approximately equal to the voltage produced by the sensor whose switch assembly is on (switch assembly <NUM> in the example of <FIG>). As such, the voltage on N3 also is equal to the voltage on N1.

In the example of <FIG>, N2 is coupled to ground when S3 is turned on. By grounding N2, a large enough drain-to-source voltage develops across MP1 and MN1 to cause leakage currents Idsp and Idsn to flow through MP1 and MN1. In <FIG>, instead of grounding N2 in switch assemblies <NUM>-<NUM>, N2 is coupled N3, which has approximately the same voltage as on N1. As such, a much lower drain-to-source voltage (approximately <NUM> V) develops across MP1 and MN1 for S2 of switch assemblies <NUM>-<NUM>. Advantageously, when channel <NUM> is enabled and channels <NUM>-<NUM> are disabled much lower leakage current results through MP1 and MN1 of S2 of switch assemblies <NUM>-<NUM> by the use of buffer <NUM> when Vin is significantly greater than <NUM> V (as might be caused by the use of enabled channel <NUM>).

Because buffer <NUM> drives all of switches S3 of switch assemblies <NUM>, <NUM>, <NUM>, and <NUM>, buffer <NUM> is sized to be large enough to power all four switches S3 of switch assemblies <NUM>, <NUM>, <NUM>, and <NUM>.

<FIG> shows an example system <NUM> including a mux circuit <NUM>, op amp <NUM>, buffer <NUM>, switch assembly <NUM>, and switch S4. The sensors S1-S5, mux controller <NUM>, and processing system <NUM> are not shown for simplicity. Mux circuit <NUM> has an architecture similar to that of mux circuit <NUM> described above. Mux circuit <NUM> includes switch assemblies <NUM>-<NUM>. The node interconnecting all switches S2 of switch assemblies <NUM>-<NUM> is labeled N4 in <FIG>. Switch assembly <NUM> is coupled between node N4 and the output of buffer <NUM>. Switch assembly <NUM> has a similar architecture as that of switch assemblies <NUM>-<NUM>. Switch assembly <NUM> includes switches S5, S6, and S7 as shown. Switches S5 and S6 are coupled in series between nodes N1 and N4. The node between S5 and S6 is designated the intermediate node (INT). S7 is coupled between INT and the output of buffer <NUM>.

Buffer <NUM> generates an output voltage which is approximately equal to its input voltage (voltage on node N1). Buffer <NUM> in <FIG> drives switch assembly <NUM>, rather than directly driving switch assemblies <NUM>-<NUM>. As a result of driving one switch assembly <NUM>, buffer <NUM> can have a lower output current requirement and thus be smaller than buffer <NUM> of <FIG>.

When switch assembly <NUM> is to be on (as is the case in the example of <FIG>), switch assemblies <NUM>-<NUM> and <NUM> are turned off, and switch S4 is turned on. S4 is coupled between node N4 and ground. By turning S4 on, node N4 is grounded. Little or no leakage current flows through switch assemblies <NUM>-<NUM> as well as <NUM> when switch assembly <NUM> is enabled and switch assemblies <NUM>-<NUM>, <NUM> are off. Buffer <NUM> provides the same benefit to switch assembly <NUM> to reduce its leakage current as described above regarding buffer <NUM>. If any of inputs inp2-inp4 are to be used, then the switch assembly of that particular input is turned on, and the remaining switch assemblies from among switch assemblies <NUM>-<NUM> as well as S4 are turned off and switch assembly <NUM> is turned on.

<FIG> shows an example implementation of buffer <NUM> (or <NUM>) coupled to an input stage <NUM> of op amp <NUM>. The input stage <NUM> includes transistors M1-M5. In this example input stage, M1, M2, and M5 are PMOS transistors, and M3 and M4 are NMOS transistors. M5 is a current source device, whose gate is biased at a voltage labeled BIAS1 and produces a tail current, Itail. M1 and M2 comprise a differential transistor pair. The sources of M1 and M2 are connected together and to the drain of M5. The positive (+) input of op amp <NUM> is coupled to the gate of M1 and is designated IN_P. The negative (-) input of op amp <NUM> is coupled to the gate of M2 and is designated IN_M. The gates of transistors M3 and M4 are biased at a voltage labeled BIAS2.

The buffer <NUM> comprises transistors M6, M7, and M8. M6 and M8 in this example comprise PMOS transistors, and M7 comprises an NMOS transistor. The gate of M8 is biased a voltage labeled BIAS3, and the source of M8 is connected to the supply voltage, Vdda. In one example, BIAS3 equals BIAS1. The drain of M8 is connected to the source of M6 and to node N5. As such, the M8 drain and M6 source are connected to the op amp input stage <NUM> at node N5. The drains of M6 and M7 are connected together and to the gate of M6 at node N6. Node N6 represents the output of the buffer <NUM>, which is connected to node N3 in <FIG> and, in the case of buffer <NUM>, to switch S3 of switch assembly <NUM> in <FIG>. The gate of M7 is biased at a voltage labeled BIAS4, and the source of M7 is connected to ground. In one example, BIAS4 equals BIAS2.

The current through M8 is labeled I1. Current I1 is a function, in part, of the size of M8 (ratio of its channel width (W) to channel length (L)) and the gate-to-source voltage (Vgs) of M8. The source of M8 is tied to Vdda, and the gate of M8 is BIAS3. As such, BIAS3 and the ratio of channel width to length of M8 define the magnitude of current I1. If BIAS3 equals BIAS1, I1 will be one-sixteenth Itail if W/L of M8 is one-sixteenth W/L of M5. In one example, BIAS3 and the channel width to length ratio of M8 result in a magnitude of I1 that is one-sixteenth the magnitude of Itail, and that fraction can be different than one-sixteenth in other examples. Further, the ratio of channel width to length of M6 is one-eighth the size of the ratio of channel width to length of M1 or M2 (which are themselves of equal size). The sources of M1, M2, and M6 are connected together at node N5. The current density through M6 is the same as that of M1 and M2. Accordingly, while I1 through M6 is Itail/<NUM>, W/L of M6 is one-eighth the W/L of M1 or M2. Due to the output of the op amp <NUM> being connected to its negative input (IN_M) as shown in <FIG>, IN_P remains generally equal to IN_M. Because the source voltage of M6 is equal to the source voltage of M1 and M2, and the current densities are the same, the gate voltage of M6 will be equal to the gate voltages IN_P or IN_M of M1 and M2, respectively. As such, the output voltage of buffer <NUM> on node N6 will be approximately equal to IN_P.

As described above regarding <FIG>, when Vin is a relatively low voltage, if the bulk of the MP1 transistor is biased at the supply voltage (Vdda), the drain-to-bulk parasitic diode D1 of switches S2 of the switch assemblies <NUM>-<NUM> are reversed biased, thereby causing a leakage current to flow through each such switch S2.

<FIG> shows a system <NUM> in which the bulk of the PMOS transistors of the switches S2 is biased at a voltage lower than Vdda when Vin is a low voltage.

The example system <NUM> in <FIG> includes the input stage <NUM> of op amp <NUM>, the buffer <NUM>, a bulk biasing circuit <NUM>, switches S1, S2, and S4, and switch assembly <NUM>. ISRC1 in buffer <NUM> represents M8 in <FIG>. In this example, switch S6 of switch assembly <NUM> comprises transistors M10 and M11. Further, switch S5 comprises transistors M12 and M13. Switch assembly <NUM> is shown in its off state, and thus switch S7 is on. S7 is shown in its symbolic form. In some implementations, S7 comprises a single transistor or a pair of PMOS/NMOS transistors. M10 and M12 comprise PMOS transistors, and M11 and M13 comprise NMOS transistors. The sources of M10 and M11 are connected together, and connect to the IN_P input (gate of M1) of the op amp's input stage <NUM>. The drains of M10 and M11 are connected together at node INT. S7 is shown in its closed (on) state to couple INT to the output of the buffer <NUM> (node N6). The sources of M12 and M13 are also connected to INT. The drains of M12 and M13 are connected together at node N4, which is provided to the switch assemblies <NUM>-<NUM> as shown in <FIG>. Switch S4 is coupled between node N4 and ground, and is closed (on) when switch assembly <NUM> is off. When switch assembly <NUM> is off, S5 and S6 are off. For S5 and S6 to be off, the gates of PMOS transistors M10 and M12 are provided with the supply voltage (Vdda) as shown, and NMOS transistors M11 and M13 are provided with a ground voltage as shown.

S1 comprises transistors M14 and M15, and S2 comprises transistors M16 and M17. In this example, M14 and M16 comprise PMOS transistors, and M15 and M17 comprise NMOS transistors. The drains of M15 and M16 are connected together at the input inp1 of channel <NUM>. The sources of M16 and M17 are connected together at node N1 to which the gate of M1 within the op amp's input stage <NUM> is connected. The configuration of <FIG> illustrates switch assembly <NUM> in its on state, and thus the gates of PMOS transistors M14 and M16 are grounded to turn on M14 and M16, and the gates of NMOS transistors M15 and M17 receive the supply voltage, Vdda, to turn on M15 and M17. Further, switch S3 (<FIG>) of switch assembly <NUM> is turned off, and thus node N2 is not pulled to ground. S3 is not shown in <FIG>.

Example bulk biasing circuit <NUM> includes transistors M18 and M19. In this implementation, M18 and M19 are PMOS transistors. The source of M18 is connected to Vdda, and the drain of M18 is connected to the source of M19 at node N7. The drain of M19 is connected to ground. The bulk of M19 is connected to M19's source. With M19 configured as a source-follower, current I2 flows in the branch from Vdda through M18 and M19 to ground. The voltage on the source of M19 is one threshold voltage (approximately <NUM> V) above the gate voltage of M19. The signal on the gate of M19 is the voltage on node N1. The voltage on N1 will be low when switch assembly <NUM> is on (S1 and S2 are on) and the voltage on inp1 is low, Current I2 flows through M19 resulting in the voltage on the source of M19 being approximately <NUM> V greater than its gate voltage (N1). Node N7 is coupled to the bulks of M1 and M2 within the op amp's input stage and to the bulk of M10 within switch S6, as well as the bulk of M16 of S2 within switch assembly <NUM>. The corresponding bulk of PMOS transistor of S2 of the other switch assemblies <NUM>-<NUM> also may be coupled to node N7 as well. The voltage on node N7 is used to bias the bulks of M1 M2, and M10. When the input inp1 is low enough so as to turn on M10, the voltage on node N7 will be pulled down to approximately <NUM> V above the voltage on inp1, and thus the bulks of M1, M2, and M10 are biased to a voltage much lower than Vdda (e.g., <NUM> V). With the bulk of M10 biased to a voltage substantially lower than Vdda, the bulk-to-source parasitic diode D3 of M10 will be biased with a voltage much closer to <NUM> V than if the bulk of M10 were biased to Vdda. With D3 biased to <NUM> V, or a relatively small voltage, the leakage current through D3 will be much smaller than would be the case if D3 were biased by a larger voltage. By biasing the bulk of PMOS M10 within switch assembly <NUM> to a lower voltage when the voltage on inp1 is small (than when inp1 has a larger voltage), the leakage current through switch assembly <NUM> is reduced compared to persistently biasing the bulk of M10 at Vdda.

Claim 1:
A multiplexer circuit, comprising:
a first switch assembly (<NUM>) having a first input node and a first output node, wherein the first input node is connected to a first multiplexer input;
a second switch assembly (<NUM>) having a second input node and a second output node, wherein the second input node is connected to a second multiplexer input;
a third switch assembly (<NUM>) having a third input node, a fourth input node, and a third output node, the third input node coupled to the second output node, and the third output node coupled to the first output node;
an operational amplifier (<NUM>) having an input stage and a multiplexer output, wherein the input stage is connected to the first output node and to the third output node; and
a buffer (<NUM>) having a buffer input and a buffer output, the buffer input coupled to the input stage of the operational amplifier (<NUM>), and the buffer output coupled to the third switch assembly (<NUM>);
wherein the third switch assembly (<NUM>) is adapted to switch on or off a connection between the third input node and the third output node and the buffer output is connected to the fourth input node to provide a voltage bias to the connection to reduce a leakage current if the third switch assembly (<NUM>) is off.