Patent Description:
The disclosure relates to the technical field of semiconductor manufacturing, and particularly, to a memory and a method for forming the same.

A dynamic random access memory (DRAM) is a semiconductor apparatus commonly used in electronic devices, such as a computer. It is composed of a plurality of memory cells. Each memory cell usually includes a transistor and a capacitor. A gate of the transistor is electrically connected to a word line, a source is electrically connected to a bit line, and a drain is electrically connected to the capacitor. A word line voltage applied on the word line can control on and off of the transistor, such that data information stored in the capacitor can be read or the data information can be written into the capacitor through the bit line.

With the size of memories, such as the DRAM, being decreased, gate structures in a memory have developed to gate all around (GAA) structures with smaller occupied area, and the memory has also developed from a two-dimensional structure to a three-dimensional structure. However, in a three-dimensional memory, the thickness uniformity between adjacent gate layers is poor, and materials as options for a barrier layer configured to isolate the adjacent gate layers is relatively less due to the limitations of the preparation process and the like, for example, the material of a barrier layer is generally silicon oxide, which reduces the performance of the memory and is not conductive to the simplification of the memory manufacturing process and the reduction of the memory manufacturing cost.

Therefore, urgent technical problems to be solved at present may reside in how to reduce the thickness difference between different gate layers in a memory, improve the selection flexibility of a material for the barrier layers, improve the isolation effect between adjacent gate layers, and reduce the capacitive coupling effect between adjacent gate layers, so as to improve the performance of the memory.

Background may be found in <CIT>, which discloses a method for forming a memory comprising a GAA structure.

The present application is defined in appended independent claim <NUM>, defining a method for forming a memory and to which reference should be made.

Specific embodiments of a method for forming a memory and a memory manufactured according to said method are provided by the disclosure and described in detail below with reference to the accompanying drawings.

A specific embodiment of the disclosure provides a memory manufactured according to the present invention. <FIG> illustrates a flowchart of a method for forming a memory in a specific embodiment of the disclosure. <FIG> illustrates a schematic diagram of a top view of a memory formed by a specific embodiment of the disclosure. <FIG> illustrate schematic diagrams of sectional views of main processes during forming the memory of a specific embodiment of the disclosure. 3Q illustrate schematic diagrams of sectional views of main processes during forming a semiconductor device from fives directions of direction a-a', direction b-b', direction c-c', direction d-d', and direction e-e' shown in <FIG>, so as to clearly show the process for forming the semiconductor device. The semiconductor device in the present specific embodiment may be, but is not limited to, a DRAM. As shown in <FIG>, <FIG>, and <FIG> to <FIG>, the method for forming a memory includes the following operations.

At S11, a substrate <NUM> and a semiconductor layer located on the substrate <NUM> are formed.

In some embodiments, the operation that a substrate <NUM> and a semiconductor layer located on the substrate <NUM> are formed includes the following specific operations.

A first sub-semiconductor layer <NUM> and a second sub-semiconductor layer <NUM> are alternately deposited on a top surface of the substrate <NUM> in a direction perpendicular to the top surface of the substrate <NUM> to form the semiconductor layer, as shown in <FIG>.

The substrate <NUM> may be, but is not limited to, a silicon substrate. The present specific embodiment is described by taking the silicon substrate as the substrate <NUM> as an example. In other examples, the substrate <NUM> may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. After that, first sub-semiconductor layers <NUM> and second sub-semiconductor layers <NUM> are alternately deposited on the top surface of the substrate <NUM> in the direction perpendicular to the top surface of the substrate <NUM> by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, so as to form the semiconductor layer with a superlattice stack structure, so as to further improve the storage density of the memory.

In some embodiments, the material of the first sub-barrier layer <NUM> may be Si, and the material of the second sub-barrier layers <NUM> may be SiGe.

At S12, the semiconductor layer is patterned to form a plurality of first isolation structures. Part of the semiconductor layer retained between two adjacent ones of the first isolation structures forms channel regions. Each first isolation structure includes a first through hole <NUM> and a second through hole <NUM> penetrating through the semiconductor layer in a direction perpendicular to a top surface of the substrate <NUM>, and a first isolation pillar <NUM> formed by the semiconductor layer retained between the first through hole <NUM> and the second through hole <NUM>, as shown in <FIG>.

In some embodiments, the operation that the semiconductor layer is patterned includes the following specific operation.

The semiconductor layer is etched to form a plurality of first isolation structures that extend in a first direction and are parallel to one another. Each of the first isolation structures includes the first isolation pillar <NUM>, the first through hole <NUM> and the second through hole <NUM>, in which the first through hole <NUM> and the second through hole <NUM> are arranged on two opposite sides of the first isolation pillar37 and extend in a second direction. The first sub-semiconductor layers <NUM> retained between two adjacent first isolation structures form channel regions. The first direction is the direction parallel to the top surface of the substrate <NUM>. The second direction is the direction parallel to the top surface of the substrate <NUM> and intersects the first direction.

Specifically, the semiconductor layer may be etched in the direction perpendicular to the top surface of the substrate <NUM> by a self-aligned double patterning (SADP) process or a self-aligned quardruple patterning (SAQP) process in combination with a dry etching process. When a plurality of active pillars <NUM> (a plurality of the active pillars <NUM> are parallel to each other and are arranged at intervals) that extend in a first direction (for example, e-e' in <FIG> and FIG. 3Q) are formed, the first isolation structures configured to isolating adjacent active pillars <NUM> are formed. Each first isolation structure includes a first through hole <NUM>, a first isolation pillar <NUM>, and a second through hole <NUM> arranged in sequence in a second direction (for example, b-b' in <FIG> and FIG. The active pillar <NUM> includes the first sub-semiconductor layers <NUM> and the second sub-semiconductor layers <NUM> that are alternately stacked in the direction perpendicular to the top surface of the substrate <NUM>. The first sub-semiconductor layers <NUM> in the active pillar <NUM> form channel regions. A plurality of the first isolation structures are parallel to each other, and are arranged at intervals in the second direction. Both the first through hole <NUM> and the second through hole <NUM> are configured to form gate layers subsequently, and the first isolation pillar <NUM> located between the first through hole <NUM> and the second through hole <NUM> is configured to form a barrier layer of the two adjacent gate layers subsequently.

In some embodiments, the inside diameter of the first through hole <NUM> is equal to that of the second through hole <NUM> in the second direction (for example, b-b' in <FIG> and FIG.

In particular, both the first through hole <NUM> and the second through hole <NUM> are configured to subsequently form gate layers, and the first isolation pillar <NUM> located between the first through hole <NUM> and the second through hole <NUM> is configured to subsequently form a barrier layer of the two adjacent gate layers. The thickness difference between the gate layers subsequently formed in the first through hole <NUM> and the second through hole <NUM> can be reduced by controlling the inside diameter of the first through hole <NUM> to be equal to that of the second through hole <NUM> when the semiconductor layer is etched to form the active pillars <NUM>. According to the present invention, the thickness of the gate layer formed in the first through hole <NUM> is made equal to that of the gate layer formed in the second through hole <NUM>, which avoids the thickness fluctuation caused by the etching difference when gate metal layers are formed by using an etching process, thereby further improving the thickness uniformity of the gate layers in the memory, and improving the electrical performance of the memory.

In order to increase the spaces for forming GAA structures subsequently to further simplify a manufacturing process of the memory, in some embodiments, the width of the first isolation pillar <NUM> is less than that of the channel region in the second direction.

In some embodiments, the semiconductor layer includes a first region <NUM>, and a second region <NUM> arranged at an outer side of the first region <NUM> in the first direction. The operation that the semiconductor layer is etched includes the following specific operations.

The first region and the second region of the semiconductor layer are etched, a plurality of the first isolation structures and a plurality of the channel regions are formed in the first region, and simultaneously a plurality of second isolation structures are formed in the second region. The semiconductor layer retained between two adjacent second isolation structures forms virtual channel regions. Each second isolation structure includes a fourth through hole <NUM> and a fifth through hole <NUM> both penetrating through the semiconductor layer in the direction perpendicular to the top surface of the substrate <NUM>, and a second isolation pillar <NUM> formed by the semiconductor layer retained between the fourth through hole <NUM> and the fifth through hole <NUM>, as shown in <FIG>.

Particularly, as shown in <FIG>, the semiconductor layer includes a first region <NUM>, a second region <NUM> arranged at an outer side of the first region <NUM> in the first direction (for example, e-e' in <FIG> and FIG. 3Q), and a third region <NUM> arranged at an outer side of the first region <NUM> in the first direction (for example, e-e' in <FIG> and FIG. The first region <NUM> is located between the second region <NUM> and the third region <NUM>. For example, the first region <NUM> may be a transistor region, the second region <NUM> may be a capacitor region, the third region <NUM> may be a bit line region (for example, a step-type bit line structure region), and the first region <NUM> is electrically connected to both the second region <NUM> and the third region <NUM>.

The second region <NUM> of the semiconductor layer is etched while etching the first region <NUM> of the semiconductor layer to form the active pillar <NUM>, so as to form a plurality of the virtual active pillars <NUM> extending in the first direction (for example, e-e' in <FIG> and FIG. 3Q) in the second region <NUM> when the active pillars <NUM> and the first isolation structures are formed in the first region <NUM> at the same time. The plurality of virtual active pillars <NUM> are parallel to one another and are arranged at intervals in a third direction (for example, d-d' in <FIG> and FIG. A second isolation structure is formed between two adjacent ones of the virtual active pillars <NUM>. Each second isolation structure includes a fourth through hole <NUM>, a second isolation pillar <NUM>, and a fifth through hole <NUM> arranged in sequence in the third direction. The virtual active pillar <NUM> includes the first sub-semiconductor layers <NUM> and the second sub-semiconductor layers <NUM> that are alternately stacked in the direction perpendicular to the top surface of the substrate <NUM>. The first sub-semiconductor layers <NUM> in the virtual active pillar <NUM> form the virtual channel regions.

At S13, a first filling layer <NUM> that fills the first through hole <NUM> and the second through hole <NUM> is formed, as shown in <FIG>.

Particularly, an oxide material (for example, silicon dioxide) may be deposited in the first through hole <NUM> and the second through hole <NUM> and on the top surface of the semiconductor layer by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, and the first filling layer <NUM> is formed by a chemical-mechanical polishing (CMP) process. There is a relatively large etching selectivity between the material of the first filling layer <NUM> and the material of the semiconductor layer, so that part of the semiconductor layer can be selectively removed subsequently. In some embodiments, both the etching selectivity between the first filling layer <NUM> and the first sub-semiconductor layer <NUM> and the etch selectivity between the first filling layer <NUM> and the second sub-semiconductor layer <NUM> are greater than <NUM>.

At S14, the first isolation pillar <NUM> is removed to form a third through hole <NUM> located in the first filling layer <NUM>, as shown in <FIG>.

In some embodiments, the operation that the third through hole <NUM> located in the first filling layers <NUM> is formed includes the following specific operations.

The first filling layer <NUM> located on the top surface of the first region <NUM> of the semiconductor layer is etched to form a first opening <NUM> exposing the first isolation pillar <NUM>, as shown in <FIG>.

The first isolation pillar <NUM> is removed along the first opening <NUM> to form the third through hole <NUM> in the first region <NUM>, as shown in <FIG>.

Particularly, after the first filling layer <NUM> is formed, a patterning process may be performed on the first filling layer <NUM> by using a photoetching process, so as to form the first opening <NUM> exposing the top surface of the first isolation pillar <NUM> in the first filling layer <NUM>, as shown in <FIG>. After that, the first isolation pillar <NUM> is subjected to the self-aligned etching along the first opening <NUM>, and the third through hole <NUM> is formed after the first isolation pillar <NUM> is completely removed, as shown in <FIG>. In the present specific embodiment, both the etching selectivity between the first filling layer <NUM> and the first sub-semiconductor layer <NUM> and the etching selectivity between the first filling layer <NUM> and the second sub-semiconductor layer <NUM> are controlled to be greater than <NUM>, so that the first filling layer <NUM> is not damaged when the first isolation pillar <NUM> is removed. Therefore, the thickness uniformity of the gate layers later formed in the first through hole <NUM> and the second through hole <NUM> can be improved.

In order to guarantee that the first isolation pillar <NUM> is fully removed, in some embodiments, the width of the first opening <NUM> is greater than or equal to the width of the first isolation pillar <NUM> in the second direction.

At S15, a barrier layer <NUM> that fills up the third through hole <NUM> is formed, as shown in <FIG>.

In some embodiments, the operation that the barrier layer <NUM> that fills up the third through hole <NUM> is formed includes the following specific operation.

An insulating material is deposited in the third through hole <NUM> along the first opening <NUM> to form the barrier layer <NUM> in the first region <NUM>.

Particularly, an insulating material such as nitride (for example, silicon nitride) or the like may be deposited into the third through hole <NUM> along the first opening <NUM> by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, so as to form the barrier layer <NUM> for electrically isolating the adjacent gate layers. After that, both of the first filling layer <NUM> and the barrier layer <NUM> that remain on the top surface of the semiconductor layer are removed by a CMP process, so as to expose the top surface of the semiconductor layer. After that, an insulating material such as an oxide (for example, silicon dioxide) or the like is deposited on the top surface of the first region <NUM> of the semiconductor layer and the top surface of the barrier layer <NUM> to form a first covering layer <NUM> that covers the top surface of the first region <NUM> of the semiconductor layer and the top surface of the barrier layer <NUM>, as shown in <FIG>.

At S16, the first filling layer <NUM> is removed to expose the channel regions <NUM>, as shown in <FIG>.

In some embodiments, before exposing the channel regions <NUM>, the method further includes the following operation.

A support layer <NUM> is formed in the second region <NUM> of the semiconductor layer, as shown in <FIG>.

Particularly, in order to prevent toppling or collapse during exposing the channel regions <NUM>, before exposing the channel regions <NUM>, a support layer <NUM> is formed in the second region <NUM> connected to the first region <NUM> first, so as to support the first region <NUM>, thereby improving the structural stability of the first region <NUM>.

In some embodiments, the operation that the support layer <NUM> is formed in the second region <NUM> of the semiconductor layer includes the following specific operations.

A second filling layer <NUM> that fills up the fourth through hole <NUM> and the fifth through hole <NUM> and covers the top surface of the second region <NUM> is formed, as shown in <FIG>.

The second isolation pillar <NUM> is removed to form a sixth through hole <NUM> in the second filling layer <NUM>, as shown in <FIG>.

A first sacrificial layer <NUM> is formed in the sixth through hole <NUM>, as shown in <FIG>.

The second filling layer <NUM> is removed from the fourth through hole <NUM> and the fifth through hole <NUM>, so as to expose the fourth through hole <NUM> and the fifth through hole <NUM>.

Part of the second sub-semiconductor layers <NUM> located in the second region <NUM> are removed along the fourth through hole <NUM> and the fifth through hole <NUM>, so as to form a first gap region located between two adjacent ones of the first sub-semiconductor layers <NUM>.

A dielectric material is filled in the fourth through hole <NUM>, the fifth through hole <NUM>, and the first gap region to form the support layer <NUM>, as shown in <FIG>.

Particularly, an oxide material (for example, silicon dioxide) may be deposited in the fourth through hole <NUM> and the fifth through hole <NUM> and may cover the top surface of the second region <NUM> of the semiconductor layer by an atomic layer deposition process, so as to form the second filling layer <NUM>, as shown in <FIG>. In some embodiments, the operation of filling the fourth through hole <NUM> and the fifth through hole <NUM> may be performed simultaneously with the operation of filling the first through hole <NUM> and the second through hole <NUM>. That is, the first filling layer <NUM> and the second filling layer <NUM> are formed simultaneously. After the second filling layer <NUM> is formed, the second filling layer <NUM> is patterned, and a second opening <NUM> that exposes the top surface of the second isolation pillar <NUM> is formed in the second filling layer <NUM>, as shown in <FIG>. After that, the second isolation pillar <NUM> is subjected to self-aligned removal along the second opening <NUM> to form the sixth through hole <NUM> in the second filling layer <NUM>, as shown in <FIG>. Then, an insulating dielectric material such as nitride (for example, silicon nitride) or the like is deposited into the sixth through hole <NUM> along the second opening <NUM> to form a first sacrificial layer <NUM>. After both of the second filling layer and retained first sacrificial layer <NUM> that are on the top surface of the second region of the semiconductor layer are removed through CMP, an insulating material such as an oxide (for example, silicon dioxide) or the like is deposited on the top surface of the second region <NUM> of the semiconductor layer and the top surface of the first sacrificial layer <NUM> to form a second covering layer <NUM> that covers the top surface of the second region <NUM> of the semiconductor layer and the top surface of the first sacrificial layer <NUM>, as shown in <FIG>. Then, the second filling layer <NUM> is removed by etching, so as to expose the fourth through hole <NUM> and the fifth through hole <NUM>. Part of the second sub-semiconductor layers <NUM> located in the second region <NUM> are removed along the fourth through hole <NUM> and the fifth through hole <NUM>, so as to form first gap regions each located between two adjacent ones of the first sub-semiconductor layers <NUM>. After that, after a dielectric material such as nitride (for example, silicon nitride) or the like is filled in the fourth through hole <NUM>, the fifth through hole <NUM>, and the first gap regions to form the support layer <NUM>, as shown in <FIG>.

In some embodiments, the operation that the channel regions <NUM> are exposed includes the following specific operations.

The first filling layer <NUM> located in the first through hole <NUM> and the second through hole <NUM> is removed to expose the first through hole <NUM> and the second through hole <NUM>.

The second sub-semiconductor layers <NUM> located in the first region <NUM> are removed along the first through hole <NUM> and the second through hole <NUM>, so as to form second gap regions <NUM> each located between two adjacent ones of the first sub-semiconductor layers <NUM>.

A second sacrificial layer <NUM> that fills up the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> is formed, as shown in <FIG>.

The second sacrificial layer <NUM> is removed to expose the channel regions <NUM>, the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM>, as shown in <FIG>.

Particularly, the first filling layer <NUM> located in the first through hole <NUM> and the second through hole <NUM> and covering the top surface of the first region of the semiconductor layer is removed by an etching process first, so as to expose the first through hole <NUM> and the second through hole <NUM>. Then, the second sub-semiconductor layers <NUM> located in the first region <NUM> are removed along the first through hole <NUM> and the second through hole <NUM> by a wet etching process, so as to form second gap regions <NUM> each located between two adjacent ones of the first sub-semiconductor layers <NUM>. In order to simultaneously form the isolation layer located in the third region <NUM> (for example, bit line isolation layer configured to electrically isolate two adjacent ones of the bit lines), after the second gap regions <NUM> are formed, the second sacrificial layer <NUM> that fills up the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> and covers the third region <NUM> of the semiconductor layer is formed first rather than performing a process for forming the gate layers directly, as shown in <FIG>. The second sacrificial layer <NUM> is configured to form the isolation layers in the third region <NUM>. After that, the second sacrificial layer <NUM> located in the first region <NUM> is removed to expose the channel regions <NUM>, the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM>, as shown in <FIG>.

At S17, a gate layer <NUM> that covers the surfaces of the channel regions <NUM> is formed, as shown in <FIG>.

In some embodiments, the operation that the gate layer <NUM> that covers the surfaces of the channel regions <NUM> includes the following specific operation.

The gate layer <NUM> that fills the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> is formed.

In some embodiments, the operation that the gate layer <NUM> that fills the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> includes the following specific operations.

The gate dielectric layers <NUM> that cover the surfaces of the channel regions <NUM> are formed.

The gate layer <NUM> that fills the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> and covers the surfaces of the gate dielectric layers <NUM> is formed, as shown in <FIG>.

In some embodiments, the material of the first sub-semiconductor layer <NUM> is silicone. The operation that the gate dielectric layers <NUM> that cover the surfaces of the channel regions <NUM> includes the following specific operation.

The surfaces of the channel regions <NUM> are oxidized in situ to form the gate dielectric layers <NUM>.

Taking the material of the first sub-semiconductor layer <NUM> being silicon as an example for describing below. For example, after the structure as shown in <FIG> is formed, the surfaces of the channel regions <NUM> are oxidized in situ by using an in-situ oxidation process (for example, an in-situ steam generation process), so as to form the gate dielectric layers <NUM>. After that, a conductive material such as tungsten is deposited along the first through hole <NUM> and the second through hole <NUM> by an atomic layer deposition process, so as to form the gate layer <NUM> that fills the first through hole <NUM>, the second through hole <NUM>, and the second gap regions <NUM> and covers the surfaces of the gate dielectric layers <NUM>, as shown in <FIG>.

In some embodiments, the barrier layer <NUM> is a single-layer structure. In some other embodiments, the operation that the barrier layer <NUM> that fills the third through hole <NUM> is formed includes the following operations.

A first sub-barrier layer <NUM> that fills the third through hole <NUM> is formed.

The first sub-barrier layer <NUM> is etched to form an etching hole extending in the direction perpendicular to the top surface of the substrate <NUM>.

A second barrier layer <NUM> is formed in the etching hole.

In some embodiments, the material of the second sub-barrier layer <NUM> is a nitride material, and the material of the first sub-barrier layer <NUM> is an oxide material.

In some embodiments, the second sub-barrier layer <NUM> is located inside the first sub-barrier layer <NUM>.

Particularly, the third through hole <NUM> is formed through a self-aligned etching process before forming the gate layer <NUM>, and the barrier layer <NUM> is formed by filling the third through hole <NUM>, so that the choice of materials for the barrier layer <NUM> is expanded, and the barrier layer with a multi-layer structure can also be formed Therefore, the electrical isolation performance of the barrier layer is improved, meanwhile, the parasitic capacitance inside the barrier layer is reduced. The material of the first sub-barrier layer <NUM> may be, but is not limited to, a nitride (for example, silicon nitride) material, and the material of the second sub-barrier layer <NUM> is an oxide (for example, silicon dioxide) material. <FIG> illustrates a structural schematic diagram of a memory including a first sub-barrier layer <NUM> and a second sub-barrier layer <NUM>.

In another embodiment, the barrier layer may further include a first sub-barrier layer and a second sub-barrier layer located between two adjacent ones of the gate layers <NUM> and arranged in the second direction b-b', and the material of the first sub-barrier layer is different from that of the second sub-barrier layer.

The present specific embodiment further provides a memory. <FIG> illustrates a schematic diagram of a sectional view of a memory in the specific embodiment of the disclosure. <FIG> illustrates a schematic diagram of another sectional view of the memory in the specific embodiment of the disclosure. The memory provided by the present specific embodiment may be formed by the method for forming a memory as shown in <FIG>, <FIG>, and <FIG> to <FIG>. As shown in <FIG>, <FIG>, <FIG>, and <FIG>, the memory includes a substrate <NUM>, a plurality of channel region groups <NUM>, a plurality of barrier layers <NUM> and a plurality of gate layers <NUM>.

The channel region groups <NUM> are located above the substrate <NUM>. In the direction parallel to the top surface of the substrate <NUM>, the plurality of channel region groups <NUM> are arranged in parallel. Each of the channel region groups <NUM> includes a plurality of channel regions <NUM> arranged in parallel in the direction perpendicular to the top surface of the substrate <NUM>.

The barrier layers <NUM> are located above the substrate <NUM>, and each of the barrier layers <NUM> is located between two adjacent ones of the channel region groups <NUM>.

The gate layers <NUM> are located above the substrate <NUM>. Each of the gate layers <NUM> is at least located between one barrier layer <NUM> and one channel region group <NUM>, and covers the surfaces of all channel regions <NUM> in the channel region group <NUM>. The thicknesses of the gate layers <NUM> located on two opposite sides of one of the barrier layers <NUM> are equal.

In some embodiments, the barrier layers <NUM> have a single-layer structure, as shown in <FIG>.

Or, the barrier layers <NUM> have a multi-layer structure.

In some embodiments, each of the barrier layers <NUM> includes: a first sub-barrier layer <NUM> and a second sub-barrier layer <NUM>.

The first sub-barrier layer <NUM> extends in the direction perpendicular to the top surface of the substrate <NUM> and covers the surface of one gate layer <NUM>.

The second sub-barrier layer <NUM> extends in the direction perpendicular to the top surface of the substrate <NUM> and is sandwiched in the first sub-barrier layer <NUM>, as shown in <FIG>.

In some embodiments, the material of the first sub-barrier layer <NUM> is a nitride material, and the material of the second sub-barrier layer is an oxide material.

In some embodiments, each of the gate layers may <NUM> include: a first part <NUM> and a second part <NUM>.

The first part <NUM> extends in the direction perpendicular to the top surface of the substrate <NUM>, and continuously covers the side walls of all of the channel regions <NUM> in a same channel region group <NUM>. The thicknesses of the first parts <NUM> of two gate layers <NUM> located on the two opposite sides of one barrier layer <NUM> are equal.

The second part <NUM> is connected to the first part <NUM>, and is located between two adjacent channel regions <NUM> in the same channel region group <NUM>.

In some embodiments, the memory further includes gate dielectric layers <NUM>.

The gate dielectric layers <NUM> cover the surfaces of the channel regions <NUM>, and the gate layers <NUM> cover the surfaces of the gate dielectric layers <NUM>.

In some embodiments, the memory further includes source areas, drain sources, capacitors, and bit lines.

A source area and a drain area are arranged on two opposite sides <NUM> of one channel region.

A capacitor is connected to the drain area.

A bit line is connected to the source area.

According to the memory and the method for forming the memory provided by some embodiments of the present specific implementation mode, a first isolation structure between adjacent active pillars is formed while etching the semiconductor layer to form the active pillars, and the first isolation structure includes a first through hole, a second through hole, and a first isolation pillar located between the first through hole and the second through hole. Then, the first isolation structure is etched to form the barrier layer by self-aligned exposure before forming the gate layer, so that the choice of materials for the barrier layer is expanded, the manufacturing process of the memory is simplified, and it is helpful to improve the isolation effect between adjacent gate layers and reduce the capacitive coupling effect between adjacent gate layers. Moreover, according to some embodiments of the disclosure, the first isolation structure including the first isolation pillar is formed while the active pillars are formed by etching, and the barrier layer is formed by a self-aligned process subsequently, which avoids an error produced by photoetching alignment, thereby reducing the thickness difference between adjacent gate layers, and improving the thickness uniformity among a plurality of gate layers in the memory.

Claim 1:
A method for forming a memory, comprising:
forming a substrate (<NUM>) and a semiconductor layer located on the substrate (<NUM>);
patterning the semiconductor layer to form a plurality of first isolation structures, wherein part of the semiconductor layer retained between two adjacent ones of the first isolation structures forms channel regions (<NUM>), wherein each of the first isolation structures comprises a first through hole (<NUM>) and a second through hole (<NUM>) penetrating through the semiconductor layer in a direction perpendicular to a top surface of the substrate (<NUM>), and a first isolation pillar (<NUM>) formed by the semiconductor layer retained between the first through hole (<NUM>) and the second through hole (<NUM>);
forming a first filling layer (<NUM>) that fills up the first through hole (<NUM>) and the second through hole (<NUM>);
removing the first isolation pillar (<NUM>) to form a third through hole (<NUM>) located in the first filling layer (<NUM>);
forming a barrier layer (<NUM>) that fills up the third through hole (<NUM>);
exposing the channel regions (<NUM>) by removing the first filling layer (<NUM>); and
forming a gate layer (<NUM>) that covers surfaces of the channel regions (<NUM>); and
thicknesses of the gate layer (<NUM>) located on two opposite sides of the barrier layer (<NUM>) being equal.