Patent Description:
The invention relates generally to automation systems and equipment, such as electric motor drives, and particularly to techniques for flexibly communicating with functional circuits coupled to control circuitry in such systems.

A wide range of systems in industry and other applications call for automated control by driving loads, such as electric motors. Industrial automation equipment provides for such needs, and may be adapted to particular settings to sense and provide feedback of key system parameters, for closed loop control of motors and other loads. In motor drives, for example, sophisticated control circuitry allows for implementation of control schemes that produce variable frequency output to drive motors at desired speeds. Many ancillary devices and circuits may be interfaced with the control circuitry to accomplish different control tasks and strategies. In certain currently available motor drives, for example, functional circuits may be connected to master control circuits to provide data necessary for system functions and control functions. As these functional circuits become more sophisticated, it is becoming apparent that different interface protocols, speeds, and physical hardware are required to adapt control circuitry to a wide range of power ratings. Further, as equipment becomes available, improvements in speeds and capabilities need to be accommodated while allowing certain existing or legacy circuits to continue to be offered and functional.

Current technologies do not, however, permit this flexibility. There is a keen need for new approaches to communication both within such equipment and between the equipment and peripheral devices. The need is particularly acute in the field of industrial automation where real or near real time demands are made by control requirements. <CIT> provides a motor drive that includes a control circuit or board and a one or more functional circuits or option boards coupled to the control board. A pod chassis includes a one or more backplanes, which generally support and provide the physical interconnect between the control board and various option boards. The pod <NUM> may have two (or more) backplanes. In an example, three dedicated serial buses are provided on each backplane. To ensure synchronization, regardless of the clock timing of each option board, each signal has a data acquisition interval and a transfer interval. By providing a data acquisition window, the control board is ensured of receiving all data from the option boards in the pod. <CIT> discloses that an industrial controller has an I/O scanner that scans I/O modules at differing rates depending on the intrinsic bandwidth of the controlled process variable. It is therefore the object of the present invention to provide an improved system for providing data communication between a control circuitry and functional circuits.

A system comprises converter circuitry to convert incoming three-phase power to DC power, inverter circuitry to convert the DC power to three-phase controlled frequency AC power to drive a motor, and control circuitry coupled to the inverter circuitry and configured to apply control signals to the inverter circuitry for conversion of the DC power to the controlled frequency AC power. A plurality of functional circuits are each configured to carry out a control, monitoring, or feedback operation with respect to a driven motor or load. A physical backplane provides data communication between the control circuitry and the functional circuits, the physical backplane having separate and independent conductive data lines for each functional circuit.

As functional circuits become more sophisticated, it is becoming apparent that different interface protocols, speeds, and physical hardware are required to adapt control circuitry to a wide range of power ratings. Further, as equipment becomes available, improvements in speeds and capabilities need to be accommodated while allowing certain existing or legacy circuits to continue to be offered and functional.

With the foregoing in mind, <FIG> illustrates an example industrial automation system <NUM> for performing automation tasks and utilizing novel communication techniques as disclosed here. The automation system <NUM> illustrated comprises a motor drive designed to drive an electric motor <NUM> at controlled speeds. The drive may regulate output of the motor <NUM> in terms of speed, torque, power, or a combination of such parameters. In a practical application, the motor <NUM> would be coupled to a load to be driven to carry out industrial automation tasks (e.g., a pump, conveyor, transmission equipment, and so forth). The system may be part of a larger automation system that automates entire groups of tasks, such as for manufacturing, material handling, mining, or any other useful application. Further, the system may be in physical, data, and logical communication with other systems and components by networks, both wired and wireless, at a single location or at dispersed locations in an organization.

In the illustrated embodiment, the motor <NUM> is driven by power received from a grid or source <NUM>. An embodiment of a power structure <NUM> is illustrated in <FIG>. The grid <NUM> may comprise the electric power grid of a location or region, or any other suitable source of power may be called upon. The illustrated embodiment makes use of three phase power that is applied to power conversion circuitry <NUM>, although a single phase embodiment may be conceived by anyone skilled in the art. The power conversion circuitry <NUM>, also known as a rectifier, converts the three-phase power to direct current (DC) power. The power conversion circuitry <NUM> may comprise passive elements that do not require control, or may be designed for active control of power conversion. If active, power structure control signals <NUM> may control the power conversion circuitry <NUM> for proper modulation of power. After rectification, all phases of the incoming power are combined to provide DC power to a direct current bus <NUM>. Other components such as inductors, resistors, and capacitors may be included in the DC bus for smoothing the rectified DC voltage waveform.

The DC power from the bus is applied to inverter circuitry <NUM> where it is converted to controlled frequency alternating current (AC) output, in this case three-phase output. The inverter circuitry <NUM> may comprise various physical and electrical configurations, such as based upon an array of power electronic switches, such as insulated-gate bipolar transistors (IGBTs). By controlling the gate signals to such switches, a synthesized waveform may be output at the desired frequency for driving the motor <NUM>. In the illustrated embodiment, within the inverter <NUM>, for each phase, two IGBTs <NUM> are coupled in series, collector to emitter, between the high side and low side of the DC bus <NUM>. Three of these transistor pairs are coupled in parallel to the DC bus <NUM>, for a total of six transistors <NUM>. Power structure control signals <NUM> cause the transistors <NUM> to rapidly close and open, resulting in a three phase waveform output across three terminals. It should be noted that although the power structure <NUM> is illustrated as including the power conversion circuitry <NUM>, DC bus <NUM>, and inverter circuitry <NUM>, some components may be passive or unnecessary in certain applications. In such a case, the power structure <NUM> is to include those controlled components through which electrical power is modulated.

The motor <NUM> and drive circuitry may be designed for any suitable power rating, often referred to by the frame size of the motor. The present techniques are not limited to any particular power rating or range. Moreover, the circuitry disclosed may be designed for starting, driving, braking, and any suitable control of the motor <NUM>. In some applications, for example, dynamic braking is not provided, while in others the inverter <NUM> and power conversion circuitry <NUM> cooperate to provide such a dynamic braking. Further, the circuitry may be designed with more than one power module, such as multiple power converters <NUM> and/or inverters <NUM>, which operate in parallel to provide higher power and output ratings.

The circuitry used to control the power conversion circuitry <NUM> and inversion circuitry <NUM> may include a range of peripherals <NUM> as illustrated in <FIG>. In this approach, the power conversion circuitry <NUM> and the inverter circuitry <NUM> may themselves be considered as peripherals <NUM>, and other peripherals may include precharge circuits, additional conversion circuits, additional inverter circuits, a power layer interface (PLI), and so forth. All of the circuitry operates under the control of control circuitry <NUM>. The control circuitry <NUM>, as discussed below, typically carries out predefined control routines, or those defined by an operator, based upon parameters set during commissioning of the equipment and/or parameters sensed and fed back to the control circuitry during operation.

The control circuitry <NUM> may generally comprise one or more circuit boards which may be mounted in a framework with other circuit boards. This framework comprises a pod for mounting circuit boards within, and also houses a physical backplane <NUM> that allows independent communication via separate and independent data communication lines <NUM>. The physical backplane <NUM> may be a multilayer printed circuit board (PCB), and is dedicated for functional circuit data transmission, but does not process signals. The control circuit board <NUM> may be directly connected to this backplane <NUM>, such as via on dashboard traces, tabs, extensions, cables, and so forth. Each independent data line <NUM> allows for communication with a functional circuit <NUM>, sometimes referred to as an option board. These functional circuits <NUM> may carry out a wide range of operations, including detecting and feeding back parameters (e.g. currents, voltages, and speeds), regulating certain operations based on loads and conditions, and so forth.

The functional circuits <NUM> may comprise profiles that may be stored in the functional circuit, in the control circuit board <NUM>, or in any other memory device associated with the system. Such profiles are described, for example, in <CIT> and entitled Motor Controller having Integrated Communications Configurations. Moreover, the functional circuits <NUM> may have different data exchange rate capabilities adapted to their functions. As discussed below, the use of independent data communication lines <NUM> in the physical backplane <NUM>, and an adaptable technique for determining protocols and data rates allow for the use of different functional circuits <NUM> having such different rates. Additionally, the use of independent data communication lines <NUM> allow functional circuit <NUM> to each operate at its optimum rate instead of requiring each to run at a common rate, which may be suboptimal for functional circuits with faster capabilities. This approach allows for the design of a wide range of functional circuits <NUM> and continuously improved and evolved functional circuits, while allowing the system to operate with existing or legacy circuits that may have reduced capabilities for data exchange rates.

The control circuitry <NUM> additionally employs a high speed interface (HSI) <NUM> to transfer control, feedback, and other signals to power stage circuitry <NUM>. The power stage circuitry <NUM> communicates with peripherals <NUM> such as the inverter circuitry <NUM> via communication lines <NUM>. These communication lines <NUM> transfer control, feedback, and other signals between peripherals <NUM> such as inverter circuitry <NUM> and the power stage circuitry <NUM>, and thus the control circuitry.

A somewhat more detailed view of the control circuitry and a physical backplane is illustrated in <FIG>. Certain of the components that may be included in the control circuitry <NUM> for the communications functions disclosed include a processor <NUM>, memory <NUM>, and an option bus <NUM> to allow communications with the physical backplane <NUM> and/or other auxiliary devices. Additionally, the control circuitry <NUM> may include independent communications controllers for fiber optics, Ethernet, serial, or other communicating means. These additional communications may be used for user input, output to displays, transfer of signals to other computing systems, and/or control to or from auxiliary controllers. The control circuitry <NUM> will typically include one or more processors <NUM>, which may be any suitable types, such as field programmable gate arrays, multi-core processors, or any other suitable processing circuits. The processors <NUM> are coupled to memory circuitry <NUM> that stores a range of configuration routines, operating routines, settings, and so forth. Here again, the memory circuitry <NUM> may be of any suitable type, including volatile and non-volatile memory. Among the many routines stored in the memory <NUM> are protocols and images for using the HSI <NUM> between the control circuitry <NUM> and the power stage circuitry <NUM>. It should be noted, that these HSI protocols and images may also be stored in the power stage circuitry <NUM>.

The processors <NUM> are also connected to an option bus <NUM> to allow communications with the physical backplane <NUM> and/or other auxiliary devices. The option bus <NUM> manages communications to and from the functional circuits <NUM> via one or more physical backplanes <NUM>. One embodiment, as depicted in <FIG>, includes two physical backplanes <NUM>, each connecting three functional circuits <NUM>, to the option bus <NUM> of the control circuitry <NUM>.

<FIG> illustrates exemplary logic <NUM> for implementing independently determined communications via the physical backplane <NUM> and its independent communication lines <NUM> discussed above. At step <NUM>, the functional circuit <NUM> is connected via its separate independent communication line <NUM> on the physical backplane <NUM>. At step <NUM> a profile for the functional circuit <NUM> is detected or created. The use of the profile allows for functional circuits <NUM> to be properly detected and automatically interfaced with the control circuitry <NUM>. The profile may be provided on the functional circuit <NUM>, in memory of the control circuitry <NUM>, or may be created. During the power up evaluation, the control and system event signals for the functional circuits <NUM> remain at a default speed. The automatic self-identification process allows for communication parameters to be determined for each individual functional circuit <NUM> to communicate data over its independent line <NUM> on the physical backplane <NUM> as indicated at step <NUM>. It is contemplated that different functional circuits <NUM> will, in any particular application, communicate differently over its independent line <NUM> of the physical backplane <NUM> based upon its capabilities and its profile. In general, the capabilities and communication parameters, particularly the interrupt intervals and data rates, will depend upon the nature of the data exchanged with the control circuitry <NUM>. At step <NUM>, then, the communications parameters selected are then implemented for all communications between the functional circuits <NUM> and the control circuitry <NUM>.

In the present embodiment, the option bus <NUM> provides an interface between the control circuitry <NUM> and functional circuits <NUM> via a drive peripheral interface (DPI) and a high speed serial interface (SI). The drive peripheral interface is based on controller area network (CAN) technology, and is a standard configuration, messaging, and flash file transfer mechanism. The addition of a high speed serial or other high speed interface allows fast transfer of time critical input/output data which cannot be accomplished over a drive peripheral interface. The interfaces may be accomplished using peripheral component interconnect (PCI) connections on the physical backplane <NUM>. Additional connections located directly on the control circuitry <NUM> or backplane <NUM> may also be managed by the option bus <NUM>, for example connections to a human interface module (HIM), a remote drive peripheral interface (<NUM>-pin MiniDIN), or an insulating displacement contact (IDC) connection. Connections managed by the option bus <NUM> also have an assignment of port identification. Each connection may have a specific media access control identification (MACID) to identify the functional circuit <NUM> to the control circuitry <NUM>. These functional circuits may include auxiliary power supplies, network communication cards, encoder interface cards, safety cards, or other input/output cards.

The retention of the device peripheral interface allows for the continued use of legacy functional circuits <NUM>. However, each connection on the backplane <NUM> will additionally have one or more dedicated serial interface channels connecting the functional circuit <NUM> directly to the option bus <NUM> on the control circuitry <NUM>. These independent serial channels allow independent event triggers, for example control and system, to request data transfers independent of each other, and independent of other functional circuits. The control and system events may be separately triggered by the control circuitry, and may be triggered differently for each functional circuit, thus allowing smaller event intervals to improve the performance of functional circuits capable of faster speeds, or for functional circuits operating at slower speeds, but having smaller amounts of information to send. Tailoring the event intervals to each functional circuit allows the optimum performance for each functional circuit.

In the present embodiment, clock performance ranges from <NUM> to <NUM> depending on the capabilities of the functional circuit <NUM>. The control and system event intervals, however, are triggered by the option bus <NUM> or control circuitry <NUM>. Many of the current functional circuits are configured to use <NUM> event intervals. However, implementing independent serial channels in the communication lines <NUM> allows for higher performance functional circuits <NUM> to have shorter event intervals, for example <NUM> or <NUM>, while concurrently running legacy functional circuits at a slower rate. Thus, the control circuitry <NUM>, may communicate with each functional circuit <NUM> at the optimal performance for each device.

In previous embodiments, such as the backplane and control circuitry of patent no. <CIT>, the event signals driven by the control circuitry were triggered at a fixed rate. The event signals could be triggered at one of a plurality of intervals, but once set, the interval did not change and was set the same for each functional circuit. The serial channels allowed different data transfer rates for each functional circuit, as each functional circuit supplied the data rate clock, but the event signals triggered by the control circuitry was not variable across the functional circuits.

The present embodiment, however, allows different event signal intervals for each functional circuit. In order to maintain compatibility with functional circuits <NUM> that require longer event intervals, the control and/or system event signals triggered by the option bus <NUM> or control circuitry <NUM> default to a <NUM> interval during startup and login of the functional circuits. Once profiles are established, the option bus <NUM> or control circuitry <NUM> may shorten or lengthen the control and/or system event intervals for individual functional circuits <NUM> to <NUM> or <NUM> depending on the data transfer characteristics of each functional circuit.

Similarly, the control circuitry <NUM> connects to a power stage circuitry <NUM> via the HSI <NUM>, and thus to peripheral devices <NUM>, while maintaining optimal speed. Different protocols, for example the HSI protocol and HSI Lite protocol, may be implemented across the HSI <NUM> based on required communication speeds and signal processing methodology. An appropriate image may also be chosen to allow proper control signals to be communicated to the power stage circuitry <NUM>. It should also be noted, that the protocol and image selection may be combined as a single image or protocol implementation. In the illustrated volume, the HSI <NUM>, utilizing the HSI protocol, comprises a four lane low voltage differential signal (LVDS) communication structure, each with a data rate of up to <NUM> Mbps (<NUM> operating via DDR). This structure can provide the <NUM> lanes in a dual two-lane configuration or a single four-lane configuration for bi-directional operation. In a presently contemplated embodiment the interface allows five classes of signals in its definition, including a power class, a safety class, a system class, a communications class, and a non-volatile storage class. The different protocols and images stored in the memory <NUM> allow the control circuitry <NUM> to interface with multiple different power stage circuitry <NUM> over the HSI <NUM>, and may be chosen automatically by the control circuitry. <FIG> illustrates exemplary logic <NUM> for selecting and implementing the communication protocol. Once the control circuitry <NUM> is connected to the power stage circuitry <NUM> via the HSI <NUM>, a unique resistor, positioned in a conductor pin line to produce a corresponding unique voltage, is detected at step <NUM>. Alternative embodiments may allow for digital indication of the desired protocol, or any other automated indication based upon or describing the capabilities of the connected device. Based upon the detected voltage, in the concurrent steps <NUM> and <NUM> respectively, the processor accesses either the HSI protocol or the HSI Lite protocol for implementation with the connected device, and accesses the proper image. It should be noted that not all connected devices need use the same protocol, and there may be a plurality of protocols from which to select. The protocol and image are then implemented at step <NUM>.

As stated above, the connector pin voltage determines the protocols and images selected based on the power stage circuitry <NUM> connected. These power stage circuitry <NUM> may be for low, medium, or high power motor drives, and may also be used in single or multi-drive applications. Another embodiment may be a panel mount power stage circuitry <NUM> that utilizes the HSI Lite protocol. The HSI Lite protocol may be configured for digital isolated negative bus reference (NBR), such as for non-differential signal communication (e.g., where optoisolators may add delay to data transfer). The HSI Lite protocol may utilize the same connector pinouts as the HSI protocol and may also operate as a bi-directional four lane interface, but as a single-ended <NUM> communication link for slower performance over the HSI. This variant has a reduced data transfer rate of <NUM> Mbps, and may be used for low power and panel mount systems.

For the higher performance motor drive products, the HSI protocol is used. In a contemplated embodiment, the HSI communications protocol may serve as a primary interface to a multi-drive product for communications between the control circuitry <NUM> and the power stage circuitry <NUM> (power structure optics, communicating to power devices for converting the power from AC to DC and/or from DC to AC). This may operate at <NUM> per lane, for example, and the <NUM> lanes mentioned above may implement bi-directional low voltage differential (LVD) signals.

In this embodiment, the HSI <NUM> provides communication between the control circuitry <NUM> and a specific power stage circuitry <NUM> illustrated in <FIG> as a "Smart FIB" (fiber interface board) <NUM>. The Smart FIB <NUM> is configured as a high power multi-drive power stage circuitry, but may be adapted for other solutions. The term "Smart FIB" is intended to denote that the power stage circuitry <NUM> provides communication between the control circuitry <NUM> and any desired peripherals <NUM> via multiple independent fiber-optic or conductive communication lines <NUM> (e.g. fiber optic cables, metallic wires, circuit board lines, etc.). The term is also intended to denote that the Smart FIB <NUM> has dynamic interval communications with connected peripherals <NUM> and automatically selects between multiple available protocols, depending upon the configuration and capabilities of each connected peripheral. This has the effect of allowing each connected peripheral <NUM> to operate at an optimal clock speed independent of the other connected peripherals. This clock speed may effect data acquisition rate, data transfer rate and/or both.

In one embodiment, the automatic detection and configuration of communications between the control circuitry <NUM> and peripherals <NUM> connected via fiber optics cables <NUM> to the Smart FIB <NUM> may provide for changes to the HSI protocol and/or to communications over the fiber optic lines. These changes may include, for example, interval rates, synchronization of communications to peripherals and firmware control loops, scalable capabilities to choose different rates, changes "on the fly" to accommodate communication protocol determination without shutting down (power cycling) any of the connected devices, changes in rates and communication protocols for the entire drive, when desired, and changes for faster response in some configurations.

The Smart FIB <NUM> may also include one or more processors <NUM> and one or more modules for memory <NUM>. Like on the control circuitry <NUM>, the memory <NUM> on the Smart FIB <NUM> may retain protocols for communication between the Smart FIB and peripherals <NUM>, including communications routines, settings, timing, and so forth. Furthermore, the Smart FIB utilizes a bandwidth manager to manage communications with one or more connected peripherals <NUM>. Similar to the option bus <NUM> of the control circuitry <NUM>, the bandwidth manager initializes all peripherals <NUM> at the same base clock speed. Based on the capabilities of each peripheral device <NUM>, each device may then be clocked at the optimal clock speed for that device.

Additionally, the Smart FIB <NUM> includes safety circuitry <NUM> configured to perform safety analysis and/or functions for the peripherals <NUM>, for example the inverter <NUM>. The safety circuitry <NUM> may also interface with a safety functional circuit <NUM>, attached to the backplane <NUM>, directly over the HSI <NUM>. General power stage circuitry <NUM> that may be connected via the HSI <NUM> to the control circuitry <NUM> may have its own safety circuitry <NUM>. The safety circuitry <NUM> is located on the power stage circuitry <NUM> instead of the control circuitry <NUM> to maintain the control circuitry's compatibility with each power stage circuitry.

In the present embodiment, the Smart FIB <NUM> includes eleven expansion interfaces <NUM>. When in operation, these expansion interfaces <NUM> may be fitted with a transceiver card <NUM> that connects one or more fiber optic lines <NUM> to the Smart FIB <NUM>. Each transceiver card <NUM> can support two fiber optic lines <NUM>, or four when peripherals <NUM> are in a daisy chain topology, thus allowing twenty-two peripheral devices (forty-four when daisy chained) to be connected to the Smart FIB <NUM>. This arrangement of expansion cards allows for a low cost and flexible solution for expanding the number of fiber optic communication lines <NUM>. The physical connections of both the transceiver card <NUM> to the Smart FIB <NUM> and the fiber communication lines <NUM> to the transceiver cards include retaining features such as clips and/or screws.

The interface between the Smart FIB <NUM> and the transceiver card <NUM> is a <NUM> low voltage differential signal bi-directional peripheral component interconnect express (PCle) connection. The transceiver card <NUM> transfers data through the fiber optic cables <NUM> using a Manchester Encoded communication protocol with an embedded clock signal. Additionally, the transceiver card may include a flash over fiber (FOF) capability to provide further control of the peripheral devices <NUM>. A flash over fiber capability allows updates of software and firmware to be implemented via the fiber communication lines <NUM> to the peripheral devices <NUM> from the control circuitry <NUM> via the Smart FIB <NUM>. The components within or immediately connected to the Smart FIB <NUM> are described as inherent or separate components, however, as can be appreciated by anyone skilled in the art, inherent components could be made separate and separate components such as a transceiver card <NUM> could be integrated inherently into the Smart FIB in another embodiment.

As discussed above, the Smart FIB <NUM> can automatically detect, configure, and implement data transfer protocols and rates between the control circuitry <NUM> and any peripheral devices <NUM>. <FIG>, <FIG>, and <FIG> illustrate examples of such configurable data transfer protocols including message intervals, message allocation windows, and so forth. <FIG> illustrates a data exchange protocol <NUM> designed to operate at A <NUM> message interval, while <FIG> illustrates a similar protocol designed to operate at a <NUM> message interval, and <FIG> illustrates a similar protocol designed to operate at a <NUM> message interval. As seen in the figures, and as labeled in <FIG>, each message interval may be broken down into segments <NUM>, each of which may be allocated for specific data transfer and data type. In the illustrated embodiments, each interval is broken into downstream communications <NUM> and upstream communications <NUM>. These divisions are further broken into communications via the HSI <NUM>, as indicated by reference numeral <NUM> (that is, between the control circuitry <NUM> and the Smart FIB <NUM>) and communications via the fiber optics lines <NUM>, as indicated by reference numeral <NUM> (that is, between the Smart FIB and the peripherals <NUM>), then again via the fiber optics lines, as indicated by reference numeral <NUM>, and finally again via the HSI, as indicated by reference numeral <NUM>. Within each of these schemes, specific data allocations may be made as indicated by reference <NUM>. Moreover, it may be observed that time shifting of certain data allocations in each successive HSI-to-fiber and fiber-to-HSI transfer may be implemented to provide for transfer via the Smart FIB <NUM>, as indicated generally by reference numeral <NUM> in <FIG>.

The devices described herein are configured to work together, however it should be noted that the devices may be adapted to work in other implementations with or without other devices from this disclosure. While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art, such as combining devices, separating components of a device, or both.

Claim 1:
A motor drive (<NUM>) for controlling three-phase controlled frequency AC power for driving a motor, the motor drive comprising:
converter circuitry (<NUM>) to convert incoming three-phase power to DC power;
inverter circuitry (<NUM>) to convert the DC power to the three-phase controlled frequency AC power to drive the motor (<NUM>);
a plurality of functional circuits (<NUM>) each configured to carry out a control, monitoring, or feedback operation with respect to a driven motor or load;
control circuitry (<NUM>) coupled to the inverter circuitry (<NUM>) and configured to:
receive feedback signals,
apply control signals to the inverter circuitry (<NUM>) for conversion of the DC power to the three-phase controlled frequency AC power, and
supply variable control events and/or system events to the functional circuits (<NUM>);
an option bus (<NUM>) configured to manage communications to and from the functional circuits (<NUM>) via one or more physical backplanes (<NUM>); and
the one or more physical backplanes (<NUM>) providing data communication between the control circuitry (<NUM>) and the functional circuits (<NUM>);
wherein the one or more physical backplanes (<NUM>) have separate and independent conductive data lines (<NUM>) for each functional circuit (<NUM>), thus allowing data transfer between the control circuitry (<NUM>) and each functional circuit (<NUM>) at different data transfer rates,
wherein the one or more physical backplanes (<NUM>) comprise one or more dedicated functional circuit support boards configured for data transmission only,
characterized in that
the control circuitry (<NUM>) employs different control event intervals and/or system event intervals with each functional circuit (<NUM>),
wherein the different control event intervals and/or system event intervals are triggered by the option bus (<NUM>) or the control circuitry (<NUM>), and
wherein the control circuitry (<NUM>) chooses clock rates, and thus data transfer rates, for each respective functional circuit based on the optimal performance for each respective functional circuit.