Patent Description:
Non-volatile memories have been widely used in a variety of electronic products. After the supplied power is interrupted, the data stored in the non-volatile memory is still retained. The non-volatile memory comprises an array structure with plural non-volatile memory cells. Each non-volatile memory cell comprises a floating gate transistor.

<FIG> is a schematic equivalent circuit diagram of a conventional single-poly non-volatile memory cell. For example, the erasable programmable single-poly non-volatile memory is disclosed in <CIT>. For succinctness, the single-poly non-volatile memory cell is referred hereinafter as a memory cell.

As shown in <FIG>, the conventional memory cell comprises a select transistor Ms, a floating gate transistor MF and a metal-oxide-semiconductor capacitor CMOS. The metal-oxide-semiconductor capacitor CMOS is also referred as a MOS capacitor. Since the memory cells comprises two transistors and one capacitor, the memory cell is referred as a 2T1C cell.

The select transistor Ms and the floating gate transistor MF are constructed in an N-well region. The select transistor Ms and the floating gate transistor MF are p-type transistors. The MOS capacitor CMOS is an n-type transistor. The n-type transistor is formed in a P-well region. The two drain/source terminals are connected with each other. Consequently, the n-type transistor is formed as the MOS capacitor CMOS. The N-well region receives an N-well voltage VNW. The P-well region receives a P-well voltage VPW. That is, the body terminal of the select transistor Ms and the body terminal of the floating gate transistor MF receives the N-well voltage VNW1, and the body terminal of the n-type transistor receives the P-well voltage VPW.

Please refer to <FIG> again. The first drain/source terminal of the select transistor Ms is connected with a source line to receive a source line voltage VSL. The gate terminal of the select transistor Ms is connected with a select gate line to receive a select gate voltage VSG. The first drain/source terminal of the floating gate transistor MF is connected with the second drain/source terminal of the select transistor Ms. The second drain/source terminal of the floating gate transistor MF is connected with a bit line to receive a bit line voltage VBL. The first terminal of the MOS capacitor CMOS is connected with a floating gate <NUM> of the floating gate transistor MF. The second terminal of the MOS capacitor CMOS is connected with an erase line to receive an erase line voltage VEL.

By providing proper bias voltages as the select gate voltage VSG, the source line voltage VSL, the bit line voltage VBL, the erase line voltage VEL, the N-well voltage VNW and the P-well voltage VPW, a program action, an erase action or a read action can be selectively performed on the memory cell.

When the program action is performed, hot carriers (e.g., electrons) are selectively injected into the floating gate of the floating gate transistor MF or not. For example, if hot carriers (e.g., electrons) are not injected into the floating gate of the floating gate transistor MF, the memory cell is programmed to a first storage state. Whereas, if hot carriers (e.g., electrons) are injected into the floating gate of the floating gate transistor MF, the memory cell is programmed to a second storage state.

When the erase action is performed, the hot carriers stored in the floating gate of the floating gate transistor MF are ejected to the erase line EL through the MOS capacitor CMOS. Consequently, the memory cell is in the first storage state.

When the read action is performed, the storage state of the memory cell is determined to be the first storage state or the second storage state according to the magnitude of a read current generated by the memory cell.

When the program action is performed, the source line voltage VSL is a program voltage VPP (e.g., about <NUM> V). When the erase action is performed, the erase line voltage VEL is an erase voltage VEE (e.g., <NUM> V). When the read action is performed, the source line voltage VSL is a read voltage VPP (e.g., about <NUM> V). In other words, the erase voltage VEE is the largest among the above bias voltages.

<FIG> is a schematic circuit diagram illustrating the architecture of a conventional non-volatile memory. The non-volatile memory comprises an array structure, a word line driver <NUM>, a bit line driver <NUM> and an erase line driver <NUM>.

As shown in <FIG>, the array structure comprises plural memory cells c<NUM>∼cMN, which are arranged in an M×N array, wherein M and N are positive integers. The array structure also comprises a source line SL, M word lines WL<NUM>~WLM, M erase lines EL<NUM>~ELM and N bit lines BL<NUM>~BLN. The structure and internal relationship of each of the memory cells c<NUM>∼cMN are similar to those of the memory cell as shown in <FIG>, and not redundantly described herein. For succinctness, only the structure of the memory cell c11 will be described as follows. In the memory cell c11, the first drain/source terminal of the select transistor Ms is connected with the source line SL, the gate terminal of the select transistor Ms is connected with the word line WL1. The second drain/source terminal of the floating gate transistor MF is connected with the bit line BL1, and the second terminal of the capacitor CMOS is connected with the erase line EL1.

Please refer to the array structure of <FIG> again. The N memory cells c<NUM>∼c1N in the first row are all connected with the source line SL, the word line WL<NUM> and the erase line EL<NUM>. Moreover, the memory cells c<NUM>∼c1N in the first row are connected with the corresponding N bit lines BL<NUM>∼BLN, respectively. Similarly, the N memory cells c<NUM>∼c2N in the second row are all connected with the source line SL, the word line WL<NUM> and the erase line EL<NUM>. Moreover, the memory cells c<NUM>∼c2N in the second row are connected with the corresponding N bit lines BL<NUM>∼BLN, respectively. The rest may be deduced by analog. Similarly, the N memory cells cM1∼cMN in the M-th row are all connected with the source line SL, the word line WLM and the erase line ELM. Moreover, the memory cells cM1∼cMN in the M-th row are connected with the corresponding N bit lines BL<NUM>~BLN, respectively.

The word line driver <NUM> is connected with the M word lines WL<NUM>~WL<NUM> of the array structure. According to the select signal S<NUM>, the word line driver <NUM> activates one of the M word lines WL<NUM>∼WLM. For example, the word line driver <NUM> actives the word line WL1 according to the select signal S<NUM>.

Meanwhile, the word line driver <NUM> provides an on voltage VON to the word line WL<NUM>, and the word line driver <NUM> provides an off voltage VOFF to the other word line WL<NUM>∼WLM. For example, the on voltage VON is <NUM> V, the off voltage VOFF is <NUM> V. In other words, the word line driver <NUM> selects one row of the array structure as a selected row according to the select signal S<NUM>.

The bit line driver <NUM> is connected with the N bit lines BL<NUM>~BLN of the array structure. According to the select signal S<NUM>, the bit line driver <NUM> activates one of the bit lines BL<NUM>∼BLN to determine a selected cell in the selected row.

The erase line driver <NUM> is connected with the M erase lines EL<NUM>~ELM of the array structure. According to the select signal S<NUM>, the erase line driver <NUM> provides various voltages to the M erase lines EL<NUM>~ELM when the program action, the erase action or the read action is performed. For example, during the erase action, the erase line driver <NUM> actives the erase line EL<NUM> according to the select signal S<NUM>. Meanwhile, the erase line driver <NUM> provides an erase voltage VEE to the erase line EL<NUM>, and the erase line driver <NUM> provides a ground voltage (<NUM> V) to the other erase lines EL<NUM>∼ELM.

<FIG> schematically illustrates the bias voltages for performing the erase action on the conventional non-volatile memory. For example, when the erase action is performed on the memory cell C<NUM>∼C1N in the first row of the array structure, the word line driver <NUM> actives the word line WL<NUM> according to the select signal S<NUM>, and the erase driver <NUM> actives the erase line EL<NUM> according to the select signal S<NUM>. Consequently, the first row of the array structure is served as the selected row.

Meanwhile, the source line SL receives the ground voltage (<NUM> V). The word line driver <NUM> provides the on voltage VON to the word line WL<NUM>, and the word line driver <NUM> provides the off voltage VOFF to the other word lines WL<NUM>∼WLM. The erase line driver <NUM> provides the erase voltage VEE to the erase line EL<NUM>, and the erase line driver <NUM> provides the ground voltage (<NUM> V) to the other erase line EL<NUM>∼ELM. Moreover, the bit line driver <NUM> provides the ground voltage (<NUM> V) to the N bit lines BL<NUM>∼BLN.

Please refer to <FIG> again. In the array structure, the unselected erase lines EL<NUM>∼ELM receive the ground voltage (<NUM> V), and the unselected word lines WL<NUM>∼WLM receive the off voltage VOFF. Consequently, the storage states of the memory cells C<NUM>∼CMN in the unselected rows are not changed.

The first row of the array structure is the selected row. In the memory cell C<NUM>, the hot carriers (e.g., electrons) stored in the floating gate transistor are ejected to the erase line EL<NUM> from the floating gate through the capacitor CMOS. Consequently, the memory cell c<NUM> is changed from the second storage state to the first storage state. Similarly, the memory cell C1N is changed from the second storage state to the first storage state. Moreover, since the memory cell c<NUM> is originally in the first storage state, it means that no hot carriers are stored in the floating gate transistor of the memory cell c<NUM>. Consequently, the memory cell c<NUM> is maintained in the first storage state.

As mentioned above, after the erase action is completed, the storage state of each of the memory cells c<NUM>∼c1N in the selected row (i.e., the first row) is in the first storage state. In the first storage state, no hot carriers are stored in the floating gate transistors of the corresponding memory cells.

When the erase action is performed on the non-volatile memory, the erase voltage VEE is transmitted from the erase line driver <NUM> to the erase line of the selected row according to the selected signal S<NUM>. Generally, the erase line driver <NUM> comprises plural electronic components. In addition, plural switching paths are defined by the plural electronic components collaboratively. The switching paths of the erase line driver <NUM> are controlled according to the select signal S<NUM>. Consequently, the erase voltage VEE can be transmitted to the erase line of the selected row. For example, as shown in <FIG>, the switching path <NUM> is turned on according to the select signal S<NUM> during the erase action. Consequently, the erase voltage VEE can be transmitted to the erase line EL<NUM> of the selected row through the switching path <NUM>.

During the erase action, the erase voltage VEE is transmitted through the switching path <NUM> of the erase line driver <NUM>. Consequently, the electronic components connected with the switching path <NUM> and the erase line EL1 may be subjected to the highest voltage stress. For example, if the erase voltage VEE is <NUM> V, the electronic components connected with the switching path <NUM> and the erase line EL1 are possibly subjected to the voltage stress of <NUM> V. If any of the electronic components connected with the switching path <NUM> and the erase line EL1 is damaged by the voltage stress, the non-volatile memory cannot be operated normally.

The <CIT> discloses a programming and verifying method for a multi-level memory cell array includes following steps. In a first step, a first row of the multi-level memory cell array is set as a selected row, and A is set as <NUM>. In a second step, memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are programmed to the A-th storage state. In a third step, if A is not equal to X, <NUM> is added to X and the second step is performed again. In a fourth step, if A is equal to X, the program cycle is ended. In the second step, the first-portion memory cells of the selected row are subjected to plural write actions and plural verification actions until all of the first-portion memory cells reach the A-th storage state.

The <CIT> discloses an erasable programmable single-poly nonvolatile memory. The erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

The <CIT> discloses a non-volatile semiconductor memory device and an electric device with the same. The non-volatile semiconductor memory device includes a cell array having electrically rewritable and non-volatile memory cells disposed at the respective intersections of word liens and bit lines intersecting each other; a row decoder circuit for selectively driving a word line of the cell array; a sense amplifier circuit disposed in communication with the cell array for data reading and writing; and a controller for executing sequence control of data write and erase, wherein in a data erase cycle controlled by the controller to erase memory cells disposed along at least one selected word line of the cell array, an adjacent/non-selected word line which is non-selected and adjacent to the selected word line in non-selected words lines in the cell array is precharged to a first erase-inhibition voltage, while the remaining non-selected word lines are precharged to a second erase-inhibition.

The <CIT> discloses a memory device having enhanced programming and/or erase characteristics. The semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.

An embodiment of the present invention provides an array structure of a non-volatile memory. The array structure includes a first memory cell. The first memory cell includes a first select transistor, a first floating gate transistor, a first capacitor, a first switching transistor and a second capacitor. A first drain/source terminal of the first select transistor is connected with a source line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first floating gate transistor is connected with a second drain/source terminal of the first select transistor. A second drain/source terminal of the first floating gate transistor is connected with a first bit line. A first terminal of the first capacitor is connected with a floating gate of the first floating gate transistor. A second terminal of the first capacitor is connected with a first erase node. A first drain/source terminal of the first switching transistor is connected with the first erase node. A second drain/source terminal of the first switching transistor is connected with a first erase line. A gate terminal of the first switching transistor is connected with a control line. A first terminal of the second capacitor is connected with the first erase node. A second terminal of the second capacitor is connected with a first boost line.

Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:.

The present invention provides a memory cell and an array structure of a non-volatile memory and associated control method. The memory cell has a novel architecture. When an erase action is operated on the memory cell, it is not necessary for an erase line driver to provide an erase voltage to the memory cell. Even if the erase voltage is not provided to the memory cell, the hot carriers (e.g., electrons) can be ejected from the memory cell.

<FIG> is a schematic equivalent circuit diagram illustrating a non-volatile memory cell of a non-volatile memory according to an embodiment of the present invention. The non-volatile memory cell is also referred to as a memory cell. As shown in <FIG>, the memory cell further comprises a select transistor Ms, a floating gate transistor MF, a switching transistor Msw, a capacitor C<NUM> and a capacitor C<NUM>. That is, the memory cell can be referred as a 3T2C memory cell.

The first drain/source terminal of the select transistor Ms is connected with a source line SL. The gate terminal of the select transistor Ms is connected with a word line WL. The first drain/source terminal of the floating gate transistor MF is connected with the second drain/source terminal of the select transistor Ms. The second drain/source terminal of the floating gate transistor MF is connected with a bit line BL. The first terminal of the capacitor C<NUM> is connected with a floating gate <NUM> of the floating gate transistor MF. The second terminal of the capacitor C<NUM> is connected with an erase node EN. The first terminal of the capacitor C<NUM> is connected with the erase node EN. The second terminal of the capacitor C<NUM> is connected with a boost line BSTL. The first drain/source terminal of the switching transistor Msw is connected with the erase node EN. The second drain/source terminal of the switching transistor Ms is connected with an erase line EL. The gate terminal of the switching transistor Msw is connected with a control line CL.

In an embodiment, the select transistor Ms and the floating gate transistor MF are p-type transistors, and the switching transistor Msw is an n-type transistor. Moreover, the capacitors C<NUM> and C<NUM> are MOS capacitors. It is noted that the types of these transistors are not restricted. For example, in another embodiment, the select transistor Ms and the floating gate transistor MF are n-type transistors, and the switching transistor Msw is a p-type transistor. Alternatively, the select transistor Ms, the floating gate transistor MF and the switching transistor Msw are all p-type transistors, or the select transistor Ms, the floating gate transistor MF and the switching transistor Msw are all n-type transistors. Similarly, the types of the capacitors are not restricted. For example, in another embodiment, the capacitors C<NUM> and C<NUM> are plate capacitors).

By providing proper bias voltages to the source line SL, the word line WL, the bit line BL, the boost line BSTL, the erase line EL and the control line CL, a program action, a program inhibition action, an erase action or a read action can be selectively performed on the memory cell. The operations of the memory cell will be described in more details as follows.

When the program action is performed, hot carriers are injected into the floating gate <NUM> of the floating gate transistor MF. When the program inhibition action is performed, hot carriers are not injected into the floating gate <NUM> of the floating gate transistor MF. For example, if hot carriers are not injected into the floating gate <NUM> of the floating gate transistor MF, the memory cell is maintained in a first storage state. Whereas, if hot carriers are injected into the floating gate <NUM> of the floating gate transistor MF, the memory cell is programmed to a second storage state.

<FIG> is a schematic circuit diagram illustrating the bias voltages for controlling the memory cell to be in a second storage state according to the embodiment of the present invention. During the program action, the source line SL receives a program voltage VPP, the bit line BL receives a ground voltage (<NUM> V), the boost line BSTL receives the ground voltage (<NUM> V), the erases line EL receives the program voltage VPP, the word line WL receives an on voltage VON, and the control line CL receives a control voltage VCTRL1. For example, the program voltage VPP is <NUM> V, and the on voltage VON is equal to the ground voltage (<NUM> V). Moreover, the control voltage VCTRL1 is <NUM> V.

Please refer to <FIG> again. The control line CL receives the control voltage VCTRL1. Consequently, the switching transistor Msw is turned on, and the program voltage VPP is transmitted to the erase node EN. Moreover, the word line WL receives the on voltage VON. Consequently, the select transistor Ms is turned on, and a program current IP generated by the memory cell flows from the source line SL to the bit line BL. When the program current IP flows through the channel region of the floating gate transistor MF, hot carriers (e.g., electrons) are injected into the floating gate <NUM> of the floating gate transistor MF from the channel region of the floating gate transistor MF. Consequently, the storage state of the memory cell is changed from the first storage state to the second storage state.

<FIG> is a schematic circuit diagram illustrating the bias voltages for controlling the memory cell to be in the first storage state according to the embodiment of the present invention. During the program inhibition action, the source line SL receives the program voltage VPP, the bit line BL receives the ground voltage (<NUM> V), the boost line BSTL receives the ground voltage (<NUM> V), the erase line EL receives the program voltage VPP, the word line WL receives an off voltage VOFF, and control line CL receives the control voltage VCTRL1. For example, the off voltage VOFF is <NUM> V.

Since the word line WL receives the off voltage VOFF, the select transistor MS is turned off. Consequently, the memory cell does not generate the program current IP. Under this circumstance, no hot carriers are injected into the floating gate <NUM> of the floating gate transistor MF. Consequently, the memory cell is maintained in the first storage state.

In some other embodiments, the bias voltages to be provided to the memory cell may be varied such that the memory cell does not generate the program current IP. In other words, the memory cell is maintained in the first storage state. For example, during the program inhibition action, the source line SL receives the program voltage VPP, the bit line BL receives the program voltage VPP, the boost line BSTL receives the ground voltage (<NUM> V), the erase line EL receives the program voltage VPP, the word line WL receives the on voltage VON, and the control line CL receives the control voltage VCTRL1. That is, both of the source line SL and the bit line BL receive the program voltage VPP. Consequently, regardless of whether the word line WL receives the on voltage VON or the off voltage VOFF, the memory cell does not generate the program current IP.

<FIG> is a schematic circuit diagram illustrating the bias voltages for performing a read action on the memory cell according to the embodiment of the present invention. During the read action, the storage state of the memory cell is determined according to the result of judging whether hot carriers are stored in the floating gate transistor MF. During the read action, a voltage difference is provided between the source line SL and bit line BL. The voltage difference is a read voltage VR.

As shown in <FIG>, the source line SL receives the read voltage VR, the bit line BL receives the ground voltage (<NUM> V) or a low voltage (e.g. <NUM> V) lower than the read voltage VR, the boost line BSTL receives the ground voltage (<NUM> V), the erase line EL receives the ground voltage (<NUM> V), the word line WL receives the on voltage VON, and the control line CL receives a control voltage VCTRL2 to turn on the switching transistor Msw, such that the ground voltage is transmitted to the erase node EN and the erase node is not floating, such that the read action can be performed normally. For example, the control voltage VCTRL2 is <NUM> V, and the read voltage VR is <NUM> V.

In another embodiment, during the read action, the source line may receive a first read voltage VR1, the first bit line may receive a second read voltage VR2 lower than the first read voltage VR1, the first erase line receives a third read voltage VR3. For example, a bias voltage (VR1) of <NUM> V is provided to the source line SL, a bias voltage (VR2) of <NUM> V is provided to the bit line BL, and a bias voltage (VR3) of <NUM> V is provided to the erase line EL. Consequently, the voltage difference between the source line SL and the bit line BL is equal to the read voltage VR (i.e., <NUM> V).

Please refer to <FIG> again. Since the word line WL receives the on voltage VON, the select transistor Ms is turned on, and a read current IR generated by the memory cell flows from the source line SL to the bit line BL. Moreover, according to the magnitude of the read current IR, the storage state of the memory cell is determined. For example, in case that hot carriers are stored in the floating gate transistor MF, the magnitude of the read current IR of the memory cell is higher. Whereas, in case that no hot carriers are stored in the floating gate transistor MF, the magnitude of the read current IR of the memory cell is very low (or nearly zero). Moreover, a sensing circuit (not shown) is provided to judge the storage state of the memory cell according to the magnitude of the read current IR and a reference current IREF.

For example, the sensing circuit (not shown) receives the reference current IREF and the read current IR. If the magnitude of the read current IR is lower than the magnitude of the reference current IREF, the sensing circuit judges that the memory cell is in the first storage state. Whereas, if the magnitude of the read current IR is higher than the reference current IREF, the sensing circuit judges that the memory cell is in the second storage state.

In the above embodiment of the present invention, the memory cell further comprises the switching transistor Msw and the capacitor C2 in comparison with the conventional memory cell. The switching transistor Msw is connected between the erase node EN and the erase line EL. The capacitor C<NUM> is connected between the erase node EN and the boost line BSTL. Consequently, during the erase action, the memory cell can withstand a lower voltage stress. The operations of the memory cell during the erase action will be described in more details as follows.

<FIG> is a schematic circuit diagram illustrating the bias voltages for performing an erase action on the memory cell in a pre-charge phase of an erase cycle. <FIG> is a schematic circuit diagram illustrating the bias voltages for performing the erase action on the memory cell in an erase phase of the erase cycle. <FIG> is a schematic timing waveform diagram illustrating associated signals of the memory cell when the erase action is performed. The erase cycle contains a pre-charge phase PHPRE and an erase phase PHERS. It is assumed that the memory cell is in the second storage state before the erase action is performed. That is, hot carriers (e.g., electrons) are stored in the floating gate of the floating gate transistor MF.

Please refer to <FIG>. The time interval between the time point to and the time point tB is the pre-charge phase PHPRE of the erase cycle. In the pre-charge phase PHPRE, the source line SL receives the ground voltage (<NUM> V), the bit line BL receives the ground voltage (<NUM> V), the word line WL receives the on voltage VON, the boost line BSTL receives the ground voltage (<NUM> V), the erase line EL receives a pre-charge voltage VPRE, and the control line CL receives the control voltage VCTRL1. Moreover, the magnitude of the control voltage VCTRL1 is equal to the magnitude of the pre-charge voltage VPRE, and the magnitude of the pre-charge voltage VPRE is lower than the magnitude of the erase voltage VEE. For example, each of the control voltage VCTRL1 and the pre-charge voltage VPRE is <NUM> V, and the erase voltage VEE is <NUM> V.

Since the word line WL receives the on voltage VON, the select transistor Ms is turned on. Consequently, the voltage at each of the first drain/source terminal and the second drain/source terminal of the floating gate transistor MF is the ground voltage (<NUM> V). Moreover, since the control line CL receives the control voltage VCTRL1, the switching transistor Msw is turned on, and the pre-charge voltage VPRE is transmitted to the erase node EN. Obviously, in the pre-charge phase PHPRE, the voltage at the erase node EN is equal to the pre-charge voltage VPRE, and the magnitude of the pre-charge VPRE is lower than the magnitude of the erase voltage VEE. Consequently, the hot carriers are still stored in the floating gate of the floating gate transistor MF, and the hot carriers are unable be ejected from the floating gate.

Please refer to <FIG>. The time interval between the time point tB and the time point tc is the erase phase PHERS of the erase cycle. In the erase phase PHERS, the source line SL receives the ground voltage (<NUM> V), the bit line BL receives the ground voltage (<NUM> V), the word line WL receives the on voltage VON, the boost line BSTL receives a boost voltage VBST, the erase line EL receives the pre-charge voltage VPRE, and the control line CL receives the control voltage VCTRL1. The magnitude of the boost voltage VBST is lower than the magnitude of the erase voltage VEE. However, the sum of the pre-charge voltage VPRE and the boost voltage VBST is higher than or equal to the magnitude of the erase voltage VEE. For example, the boost voltage VBST is <NUM> V.

At the time point tB, the boost line BSTL is increased from the ground voltage (<NUM> V) to the boost voltage VBST. Moreover, the boost voltage VBST is coupled to the erase node EN through the capacitor C<NUM>. Consequently, the voltage at the erase node EN is increased by a voltage increment from the pre-charge voltage VPRE. The voltage increment is approximately equal to the boost voltage VBST. Consequently, the voltage at the erase node EN is approximately equal to the sum of the pre-charge voltage VPRE and the boost voltage VBST and equal to the erase voltage VEE. That is, VEE=VPRE+VBST. That is, in the erase phase PHERS, the voltage at the erase node EN is boosted to the erase voltage VEE.

When the voltage at the erase node EN is boosted to the erase voltage VEE, the voltage at the first drain/source terminal of the switching transistor Msw is equal to the erase voltage VEE (e.g., <NUM> V), the voltage at the gate terminal of the switching transistor Msw is equal to the control voltage VCTRL1 (e.g., <NUM> V), and the voltage at the second drain/source terminal of the switching transistor Msw is equal to the pre-charge voltage VPRE (e.g., <NUM> V). Consequently, the switching transistor Msw is turned off. Meanwhile, the erase node EN is in a floating state, and the voltage at the erase node EN is maintained at the erase voltage VEE.

Moreover, since the voltage at the erase node EN is equal to the erase voltage VEE, the hot carriers stored in the floating gate transistor MF are ejected from the floating gate to the erase node EN. Consequently, the storage state of the memory cell is changed from the second storage state to the first storage state.

As mentioned above, the voltage at the erase node EN can reach the highest erase voltage VEE only in the erase phase PHERS of the erase cycle. However, the other conductor lines (e.g., the erase line EL and the boost line BSTL) cannot receive the highest erase voltage VEE. In other words, all of the electronic components connected with the erase line EL and the boost line BSTL will not be subjected to the highest voltage stress. Consequently, these electronic components will not be damaged easily.

<FIG> is a schematic circuit diagram illustrating the architecture of the non-volatile memory according to an embodiment of the present invention. The non-volatile memory comprises an array structure, a word line driver <NUM>, a bit line driver <NUM>, a boost line driver <NUM> and an erase line driver <NUM>.

The array structure comprises plural memory cells c<NUM>∼cMN, which are arranged in an M×N array, wherein M and N are positive integers. The array structure also comprises a source line SL, a control line CL, M word lines WL<NUM>~WLM, M boost lines BSTL<NUM>~BSTLM, N bit lines BL<NUM>∼BLN and M erase lines EL<NUM>~ELM. The structure and internal relationship of each of the memory cells c<NUM>∼cMN are similar to those of the memory cell as shown in <FIG>, and not redundantly described herein. For succinctness, only the structure of the memory cell c<NUM> will be described as follows. In the memory cell C<NUM>, the first drain/source terminal of the select transistor Ms is connected with the source line SL. The gate terminal of the select transistor Ms is connected with the word line WL<NUM>. The second drain/source terminal of the floating gate transistor MF is connected with the bit line BL<NUM>. The second terminal of the switching transistor Msw is connected with the erase line EL<NUM>. The gate terminal of the switching transistor Msw is connected with the control line CL. The second terminal of the capacitor C2 is connected with the boost line BSTL1.

In the array structure, the N memory cells c<NUM>∼c1N in the first row are all connected with the source line SL, the control line CL, the word line WL<NUM> and the boost line BSTL<NUM>. Moreover, the memory cells c<NUM>∼c1N in the first row are connected with the corresponding N bit lines BL<NUM>∼BLN and the N erase lines EL<NUM>~ELN, respectively. Similarly, the N memory cells c<NUM>∼c2N in the second row are all connected with the source line SL, the control line CL, the word line WL<NUM> and the boost line BSTL<NUM>. Moreover, the memory cells c<NUM>∼c2N in the second row are connected with the corresponding N bit lines BL<NUM>∼BLN and erase lines EL<NUM>~ELN, respectively. The rest may be deduced by analog. Similarly, the N memory cells cM1∼cMN in the M-th row are all connected with the source line SL, the control line CL, the word line WLM and the boost line BSTLM. Moreover, the N memory cells cM1∼cMN in the M-th row are connected with the corresponding N bit lines BL<NUM>∼BLN and erase lines EL<NUM>~ELN, respectively.

The word line driver <NUM> is connected with the M word lines WL<NUM>~WLM of the array structure. According to the select signal S<NUM>, the word line driver <NUM> activates one of the M word lines WL<NUM>~WLM. For example, the word line driver <NUM> actives the word line WL<NUM> according to the select signal S<NUM>. At this time, the word line driver <NUM> provides an on voltage VON to the word line WL<NUM>, and the word line driver <NUM> provides an off voltages VOFF to the other word line WL<NUM>∼WLM. For example, the on voltage VON is <NUM> V, and the off voltage VOFF is <NUM> V. In other words, the word line driver <NUM> selects one row of the array structure as a selected row according to the select signal S<NUM>.

The bit line driver <NUM> is connected with the N bit lines BL<NUM>∼BLN of the array structure. According to the select signal S<NUM>, the bit line driver <NUM> activates one of the bit lines BL<NUM>∼BLN to determine a selected cell in the selected row.

The boost line driver <NUM> is connected with the M boost lines BSTL<NUM>~BSTLM of the array structure. According to the select signal S<NUM>, the boost line driver <NUM> provides various voltages to the M boost lines BSTL<NUM>~BSTLM when the program action, the erase action or the read action is performed. For example, during the erase action, the boost line driver <NUM> actives the boost line BSTL<NUM> according to the select signal S<NUM>. Meanwhile, the boost line driver <NUM> provides a boost voltage VBST to the boost line BSTL<NUM>, and the boost line driver <NUM> provides the ground voltage (<NUM> V) to the other boost lines BSTL<NUM>∼BSTLM.

The erase line driver <NUM> is connected with the N erase line EL<NUM>∼ELN of the array structure. According to the select signal S<NUM>, the erase line driver <NUM> provides various voltages to the N erase lines EL<NUM>∼ELN when the program action, the erase action or the read action is performed. For example, during the erase action, the erase line driver <NUM> actives the erase line EL<NUM> according to the select signal S<NUM>. Meanwhile, the erase line driver <NUM> provides a pre-charge voltage VPRE to the erase line EL<NUM>, and the erase line driver <NUM> provides the ground voltage (<NUM> V) to the other erase lines EL<NUM>~ELN.

By providing proper bias voltages to the source line SL, the control line CL, the M word lines WL<NUM>~WLM, the N bit lines BL<NUM>∼BLN, the M boost lines BSTL<NUM>~BSTLM and the N erase line EL<NUM>∼ELN, a program action, a program inhibition action, an erase action or a read action can be selectively performed on the memory cell. The operations of the non-volatile memory of the present invention will be described in more details by taking the memory cell c<NUM> as an example.

<FIG> schematically illustrates the bias voltages for performing the program action on the selected memory cell of the array structure according to the embodiment of the present invention. During the program action, the source line SL receives a program voltage VPP, the control line CL receives a control voltage VCTRL1, the word line WL<NUM> receives an on voltage VON, the word lines WL<NUM>~WLM receive an off voltage VOFF, the bit line BL<NUM> receives the ground voltage (<NUM> V), the bit lines BL<NUM> ~BLN receive the program voltage VPP, the boost lines BSTL<NUM>~BSTLM receive the ground voltage (<NUM> V), the erase line EL<NUM> receives the program voltage VPP, and the erase lines EL<NUM>~ELN receive the ground voltage (<NUM> V). For example, the program voltage VPP is <NUM> V, the on voltage VON is equal to the ground voltage (<NUM> V), the off voltage VOFF is <NUM> V, and the control voltage VCTRL1 is <NUM> V.

Moreover, since the word line WL1 and the bit line BL1 are activated, the first row is the selected row, and the other rows are the unselected rows. In the array structure, the memory cells C<NUM>∼CMN are unselected memory cells. In addition, the memory cell c<NUM> in the selected row is the selected memory cell, and the other memory cells C<NUM>∼C1N in the selected row are the unselected memory cells.

In the unselected memory cells C<NUM>~C1N of the first row, the source line SL and the bit lines BL<NUM>~BLN receive the program voltage VPP. Consequently, the unselected memory cells C<NUM>∼C1N in the first row cannot generate the program current. That is, the unselected memory cells C<NUM>∼C1N are subjected to a program inhibition action, and their storage states are not changed. For example, the unselected memory cell C<NUM>∼C1N are maintained in the first storage state.

In the unselected memory cells C<NUM>∼CMN of the other rows, the word lines WL<NUM>∼WLM receive the off voltage VOFF. Consequently, the unselected memory cells C<NUM>∼CMN of the other rows cannot generate the program current. That is, the unselected memory cells C<NUM>∼CMN are subjected to the program inhibition action, and their storage states are not changed. For example, the unselected memory cells C<NUM>∼CMN are maintained in the first storage state.

Please refer to <FIG> again. In the selected memory cell C<NUM> of the first row, the word line WL<NUM> receives the on voltage VON, the source line SL receives the program voltage VPP, the bit line BL<NUM> receives the ground voltage (<NUM> V), the control line CL receives the control voltage VCTRL1, the boost line BSTL<NUM> receives the ground voltage (<NUM> V), and the erase line EL<NUM> receives the program voltage VPP. Consequently, the switching transistor MSW is turned on, and the program voltage VPP is transmitted to the erase node EN. Moreover, the select transistor Ms is turned on, and thus the memory cell generates a program current IP. The program current IP flows from the source line SL to the bit line BL<NUM>. When the program current IP flows through a channel region of the floating gate transistor MF, hot carriers (e.g., electrons) are injected into the floating gate terminal from the channel region of the floating gate transistor MF. Consequently, the storage state of the memory cell is changed from the first storage state to the second storage state.

<FIG> schematically illustrates the bias voltages for performing the read action on the selected memory cell of the array structure. During the read action, the source line SL receives a read voltage VR, the control line CL receives a control voltage VCTRL2, the word line WL<NUM> receives the on voltage VON, the word lines WL<NUM>∼WLM receive the off voltage VOFF, the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the boost lines BSTL<NUM>~BSTLM receive the ground voltage (<NUM> V), and the erase lines EL<NUM> ∼ELN receive the ground voltage (<NUM> V). For example, the read voltage VR is <NUM> V, and the control voltage VCTRL2 is <NUM> V.

Moreover, since the word line WL<NUM> is activated, the first row is the selected row, and the other rows are the unselected rows. In addition, the memory cells C<NUM>∼CMN in the unselected row do not generate the read current.

Please refer to <FIG> again. In the selected row of the first row, the word line WL<NUM> receives the on voltage VON, the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the source line SL receives the read voltage VR, the control line CL receives the control voltage VCTRL2, the boost line BSTL<NUM> receives the ground voltage (<NUM> V), and the erase lines EL<NUM>∼ELN receive the ground voltage (<NUM> V). Consequently, the memory c<NUM>∼c1N generate the read currents IR1∼IRN, respectively. The read currents IR1∼IRN flow to the corresponding bit lines BL<NUM>~BLN, respectively.

Moreover, according to the magnitudes of the read current IR1~IRN, the storage states of the memory cell c<NUM>∼c1N are determined. For example, since hot carriers are stored in the memory cell C<NUM>, the read current IR1 generated by the memory cell C<NUM> is higher. A sensing circuit (not shown) judges that the memory cell C<NUM> is in the second storage state. Moreover, since no hot carriers are stored in the memory cell C<NUM>, the read current IR1 generated by the memory cell C<NUM> is lower (or nearly zero). The sensing circuit judges that the memory cell C<NUM> is in the first storage state.

<FIG> schematically illustrates the bias voltages for performing the erase action on the selected memory cell of the array structure according to the embodiment of the present invention in the pre-charge phase of the erase cycle. <FIG> schematically illustrates the bias voltages for performing the erase action on the selected memory cell of the array structure according to the embodiment of the present invention in the erase phase of the erase cycle.

Please refer to <FIG>. In the pre-charge phase of the erase cycle, the source line SL receives the ground voltage (<NUM> V), the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the word line WL<NUM> receives the on voltage VON, the word lines WL<NUM>∼WLM receive the off voltage VOFF, the control line CL receives the control voltage VCTRL1, the boost lines BSTL<NUM>~BSTLM receive the ground voltage (<NUM> V), the erase line EL<NUM> receives a pre-charge voltage VPRE, and the erase lines EL<NUM>~ELN receive the ground voltage (<NUM> V). For example, the pre-charge voltage VPRE is <NUM> V.

Moreover, since the word line WL<NUM> and erase line EL<NUM> are activated, the first row is the selected row, and the other rows are the unselected rows. In the array structure, the memory cells C<NUM>∼CMN in the unselected rows are unselected memory cells. In addition, the memory cell C<NUM> in the selected row is the selected memory cell, and the other memory cells C<NUM>∼C1N in the selected row are the unselected memory cells.

Please refer to <FIG> again. In the memory cell C<NUM> of the first row, the erase line EL<NUM> receives the pre-charge voltage VPRE. Consequently, the voltage at the erase line EN is equal to the pre-charge voltage VPRE. In addition, in the memory cells C<NUM>∼C1N of the first row, the erase lines EL<NUM>~ELN receive the ground voltage (<NUM> V). Consequently, the voltage at the corresponding erase node of the memory cells C<NUM>∼C1N is equal to the ground voltage (<NUM> V). Similarly, in the memory cell C<NUM> of the second row, the voltage at the erase node is equal to the pre-charge voltage VPRE. In the memory cells C<NUM>~C2N of the second row, the voltage of the corresponding erase node EN is equal to the ground voltage (<NUM> V). The rest may be deduced by analog. Similarly, in the memory cell CM1 of the M-th row, the voltage at the erase node is equal to the pre-charge voltage VPRE. In the memory cells CM2∼CMN of the M-th row, the voltage at the corresponding erase node EN is equal to the ground voltage (<NUM> V).

Please refer to <FIG> for bit erase operation. In the erase phase of the erase cycle, the source line SL receives the ground voltage (<NUM> V), the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the word line WL<NUM> receives the on voltage VON, the word lines WL<NUM>∼WLM receive the off voltage VOFF, the control line CL receives the control voltage VCTRL1, the boost line BSTL<NUM> receives a boost voltage VBST, the boost lines BSTL<NUM>∼BSTLM receive the ground voltage (<NUM> V), the erase line EL<NUM> receives the pre-charge voltage VPRE, and the erase lines EL<NUM> ∼ELN receive the ground voltage (<NUM> V). For example, the boost voltage VBST is <NUM> V.

Please refer to <FIG> again. In the selected memory cell C<NUM> of the first row, since the boost line BSTL<NUM> receives the boost voltage VBST. Consequently, the voltage at the erase node EN of the selected memory cell C<NUM> is boosted to the erase voltage VEE. That is, VEE=VPRE+VBST. Moreover, since the switching transistor Msw is turned off, the voltage at the erase node EN is maintained at the erase voltage VEE. Consequently, the hot carriers are ejected from the floating gate of the floating gate transistor MF to the erase node EN through the capacitor C<NUM>. Under this circumstance, the storage state of the selected memory cell C<NUM> is changed to the first storage state.

In the unselected memory cells C<NUM>∼C1N of the first row, the voltage at the erase node is boosted from the ground voltage (<NUM> V) to the boost voltage VBST. Because the gates of the switching transistors Msw receive the control voltage VCTRL1, the switching transistors Msw are still turned on and the voltages at the erase node EN nodes are further discharged from the boost voltage VBST to ground voltage (<NUM> V). Since the ground voltage (<NUM> V) is lower than the magnitude of the erase voltage VEE, hot carriers in the unselected memory cells C<NUM>∼C1N are not ejected from the floating gates of the corresponding floating gate transistors. In other words, the unselected memory cells C<NUM>∼C1N are subjected the erase inhibition. Consequently, the storage states of the unselected memory cells C<NUM>∼C1N are not changed.

Moreover, the boost lines BSTL<NUM>∼BSTLM still receive the ground voltage (<NUM> V) for bit erase operation. Consequently, like the situation of <FIG>, the voltages at the erase nodes EN of the unselected memory cells C<NUM>∼CMN in the unselected rows (i.e., the second row to the M-th row) are not changed. In other words, the memory cells C<NUM>∼CMN of the unselected rows are subjected to the erase inhibition. Consequently, the storage states of the memory cells C<NUM>∼CMN are not changed.

As mentioned above, by providing proper bias voltages as the source line SL, the control line CL, the M word lines WL<NUM>~WLM, the N bit lines BL<NUM>∼BLN, the M boost lines BSTL<NUM>~BSTLM and the N erase line EL<NUM>∼ELN, the program action, the program inhibition action, the erase action or the read action can be selectively performed on the memory cell.

In accordance with the technology of the present invention, the erase action can be performed on a single memory cell (the bit erase operation). Moreover, the erase action can be performed on plural memory cells in a row. The associated operations will be described as follows.

<FIG> schematically illustrates the bias voltages for performing the erase action on the memory cells in the selected row of the array structure according to the embodiment of the present invention in the pre-charge phase of the erase cycle. <FIG> schematically illustrates the bias voltages for performing the erase action on the memory cells in the selected row of the array structure according to the embodiment of the present invention in the erase phase of the erase cycle.

Please refer to <FIG>. In the pre-charge phase of the erase cycle, the source line SL receives the ground voltage (<NUM> V), the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the word line WL<NUM> receives the on voltage VON, the word lines WL<NUM>∼WLM receive the off voltage VOFF, the control line CL receives the control voltage VCTRL1, the boost lines BSTL<NUM>~BSTLM receive the ground voltage (<NUM> V), and the erase lines EL<NUM>∼ELN receive the pre-charge voltage VPRE.

As shown in <FIG>, all of the switching transistors in the memory cells c<NUM>∼cMN are turned on in the pre-charge phase. Consequently, the voltage at each of the erase nodes of the memory cells c<NUM>∼cMN is equal to the pre-charge voltage VPRE.

Please refer to <FIG>. In some embodiments, compared with <FIG> and <FIG>, the erase action can be simultaneously performed on N memory cells C<NUM>∼C1N in the same selected row. In the erase phase of the erase cycle, the source line SL receives the ground voltage (<NUM> V), the bit lines BL<NUM>∼BLN receive the ground voltage (<NUM> V), the word line WL<NUM> receives the on voltage VON, the word lines WL<NUM>∼WLM receive the off voltage VOFF, the control line CL receives the control voltage VCTRL1, the boost line BSTL<NUM> receives the boost voltage VBST, the boost lines BSTL<NUM>∼BSTLM receive the ground voltage (<NUM> V), and the N erase lines EL<NUM>∼ELN receive the pre-charge voltage VPRE for performing the erase operation on N memory cells.

As shown in <FIG>, the first row is the selected row. Since the boost line BSTL<NUM> receives the boost voltage VBST, the voltage at each of the erase nodes in the selected memory cells C<NUM>∼C1N is boosted to the erase voltage VEE. That is, VEE=VPRE+VBST. Consequently, in each of the memory cells C<NUM>∼C1N in the selected row, hot carriers are ejected from the floating gate to the floating gate transistor MF to the erase node EN through the capacitor C<NUM>. Consequently, each of the memory cells C<NUM>∼C1N in the selected row is changed to the first storage state.

In the unselected rows, the voltage at the erase node of each memory cell is maintained at the pre-charge voltage VPRE. Consequently, hot carriers are not ejected from the floating gates of the floating gate transistor MF in the memory cells C<NUM>∼CMN of the unselected rows. In other words, the memory cells C<NUM>∼CMN are subjected to the erase inhibition. Consequently, the storage states of the memory cells C<NUM>∼CMN are not changed.

Please refer to <FIG>. Of course, in the erase phase of the erase cycle, the boost voltage VBST is transmitted from the boost line driver <NUM> to the M boost lines BSTL simultaneously. Under this circumstance, all of the memory cells c<NUM>∼cMN in the array structure are subjected to the erase action. Consequently, the storage state of each of the memory cells c<NUM>∼cMN is changed to the first storage state.

From the above descriptions, the present invention provides a memory cell and an array structure of a non-volatile memory. The memory cell has a novel structure. When the erase action is performed on the non-volatile memory, the erase line driver <NUM> provides the pre-charge voltage VPRE, and the boost line driver <NUM> provides the boost voltage VBST. Moreover, the magnitude of the pre-charge voltage VPRE and the magnitude of the boost voltage VBST are lower than the magnitude of the erase voltage VEE, and the sum of the pre-charge voltage VPRE and the boost voltage VBST is higher than or equal to the erase voltage VEE. Due to the special design of the memory cell, the highest erase voltage VEE will not be transmitted through the switching paths of the erase line driver <NUM> and the boost line driver <NUM> during the erase action. In other words, all of the electronic components connected with the erase line driver <NUM> and the boost line driver <NUM> will not be subjected to the highest voltage stress. Consequently, these electronic components will not be damaged easily.

Claim 1:
An array structure of a non-volatile memory, the array structure comprising a first memory cell, wherein the first memory cell comprises:
a first select transistor (Ms), wherein a first drain/source terminal of the first select transistor (Ms) is connected with a source line (SL), and a gate terminal of the first select transistor (Ms) is connected with a first word line (WL);
a first floating gate transistor (MF), wherein a first drain/source terminal of the first floating gate transistor (MF) is connected with a second drain/source terminal of the first select transistor (Ms), and a second drain/source terminal of the first floating gate transistor (MF) is connected with a first bit line (BL);and
a first capacitor (C<NUM>), wherein a first terminal of the first capacitor (C<NUM>) is connected with a floating gate (<NUM>) of the first floating gate transistor (MF), and a second terminal of the first capacitor (C<NUM>) is connected with a first erase node (EN); characterized in that the first memory cell further comprises:
a first switching transistor (Msw), wherein a first drain/source terminal of the first switching transistor (Msw) is connected with the first erase node (EN), a second drain/source terminal of the first switching transistor (Msw) is connected with a first erase line (EL), and a gate terminal of the first switching transistor (Msw) is connected with a control line (CL); and
a second capacitor (C<NUM>), wherein a first terminal of the second capacitor (C<NUM>) is connected with the first erase node (EN), and a second terminal of the second capacitor (C<NUM>) is connected with a first boost line (BSTL).