Patent Description:
Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since their integration is a key factor in determining product prices, increased integration is especially required. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by the level of a fine pattern forming technology. However, the extremely expensive process equipment needed to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. Thus, semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed.

<CIT> discloses a three-dimensional (3D) non-volatile memory array having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line.

<CIT> discloses methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer.

<CIT> discloses a nonvolatile semiconductor memory device includes a memory cell array. The memory cell array includes conducting layers, semiconductor layers, variable resistance films, and first wirings. The conducting layers are laminated in a first direction perpendicular to a substrate, and extend in a second direction parallel to the substrate. The semiconductor layers extend in the first direction. The variable resistance films are disposed at intersection points of the conducting layers and the semiconductor layers. Each first wiring is opposed to the semiconductor layer via a gate insulating film. The first wirings extend in the first direction. Each variable resistance film has a first thickness at a first part. The first thickness is in a direction from the conducting layers to the semiconductor layer. The variable resistance film has a second thickness at a second part. The second part is far from the substrate more than the first part. The second thickness is smaller than the first thickness.

<CIT> discloses a semiconductor memory device including first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

An example embodiment provides a variable resistance memory device with improved reliability and increased integration density.

The invention provides a variable resistance memory device according to claim <NUM>.

Example embodiments of the invention and examples not according to the claimed invention will now be described more fully with reference to the accompanying drawings, in which some examples and example embodiments are shown.

As used herein, expressions such as "at least one of" and "one of" when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, both "at least one of A, B, or C" and "A, B, and C" means either A, B, C or any combination thereof.

While the term "same," "equal" or "identical" is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±<NUM>%).

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "about" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes.

<FIG> is a block diagram schematically illustrating a variable resistance memory device according to an example embodiment. <FIG> is a schematic circuit diagram illustrating a variable resistance memory device according to an example embodiment.

Referring to <FIG>, a variable resistance memory device may include a memory cell array <NUM>, a voltage generator <NUM>, a row decoder <NUM>, an input/output circuit <NUM>, and a control logic <NUM>. The memory cell array <NUM> may include a plurality of memory cells, which are disposed at intersections of word lines WL1-WLm and bit lines BL1-BLn, respectively. The memory cell array <NUM> may include a nonvolatile memory cell. Data in the nonvolatile memory cell may be retained, even when a power voltage is not supplied to the memory cell array <NUM>.

The memory cell array <NUM> may be connected to the word lines WL1-WLm and the bit lines BL1-BLn. Further, the memory cell array <NUM> may be connected to one or more string selection lines SSL and one or more common source lines CSL and may include a plurality of portions, each of which is operated as a block, a page, or a cell string.

The voltage generator <NUM> may be configured to generate word line voltages V1-Vi. The word line voltages V1-Vi may be provided to the row decoder <NUM>. Signals, which will be used for program, read, and erase operations, may be applied to the memory cell array <NUM> through the bit lines BL1-BLn. Data to be programmed may be provided to the memory cell array <NUM> through the input/output circuit <NUM>, and readout data may be provided to the outside (e.g., a memory controller) through the input/output circuit <NUM>. The control logic <NUM> may be configured to provide various control signals, which are associated with operations of the memory device, to the row decoder <NUM> and the voltage generator <NUM>.

The word line voltages V1-Vi may be provided to the string selection line SSL, the word lines WL1-WLm, and the common source line CSL, depending on a result of a decoding operation of the row decoder <NUM>. For example, the word line voltages V1-Vi may include a string selection voltage, a word line voltage, and a ground selection voltage. The string selection voltage may be provided to one or more string selection lines SSL, the word line voltage may be provided to one or more word lines WL1-WLm, and the ground selection voltage may be provided to one or more common source lines CSL.

Referring to <FIG>, the variable resistance memory device may include the word lines WL1-WLm, the bit lines BL1-BLn, the common source line CSL, and the cell strings CS. The word lines WL1-WLm and the bit lines BL1-BLn may be extended in two different directions to cross each other. The word lines WL1-WLm may be extended in a first direction D1, and the bit lines BL1-BLn may be extended in a second direction D2.

The cell strings CS may be connected in parallel to each of the bit lines BL1-BLn. The cell strings CS may be connected in common to the common source line CSL. That is, the cell strings CS may be disposed between the bit lines BL1-BLn and the common source line CSL. Each of the cell strings CS may include unit memory cells UM which are located at vertically various levels. The unit memory cells UM may be arranged in a third direction D3, which is not parallel to extension directions of the word and bit lines WL1-WLm and BL1-BLn. Each of the unit memory cells UM may include a variable resistor. The unit memory cells UM, which are included in different ones of the cell strings CS and are located at the same vertical level, may be connected in common to one of the word lines WL1-WLm. A resistance of each of the unit memory cells UM may be changed by electric signals, which are provided through corresponding ones of the word and bit lines WL1-WLm and BL1-BLn. In addition, each of the unit memory cells UM may output a resistance value through corresponding ones of the word and bit lines WL1-WLm and BL1-BLn.

<FIG> is a perspective view illustrating a variable resistance memory device according to an example. <FIG> and <FIG> are sectional views which are taken along lines I-I' and II-II' of <FIG>, respectively, to illustrate a variable resistance memory device according to an example.

Referring to <FIG>, <FIG>, and <FIG>, a semiconductor device according to an example may include a substrate <NUM>, stacks ST on the substrate <NUM>, conductive lines CL connected to the stacks ST, vertical structures VS penetrating the stacks ST, and bit lines BL connected to the vertical structures VS.

The substrate <NUM> may include a cell array region CAR and a connection region CNR, which are arranged in the first direction D1. The cell strings CS described with reference to <FIG> may be formed on the cell array region CAR. Interconnection lines, which connect the word lines WL1-WLm or the cell strings CS to the decoders, may be formed on the connection region CNR. The substrate <NUM> may have a top surface, which is extended in the first and second directions D1 and D2 that are perpendicular to each other. The substrate <NUM> may have a specific conductivity type and may include the common source line CSL described with reference to <FIG>. For example, the substrate <NUM> may be configured to receive a ground voltage and to supply the ground voltage to the vertical structures VS. The substrate <NUM> may be formed of or include a semiconductor material. The substrate <NUM> may be formed of or include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium gallium arsenic (InGaAs), or aluminum gallium arsenic (AlGaAs). The substrate <NUM> may be formed of or include a doped semiconductor material of a first conductivity type and/or an undoped or intrinsic semiconductor material. The first conductivity type may be, for example, n-type. The substrate <NUM> may have one of polycrystalline, amorphous, and single-crystalline structures.

The stacks ST may be disposed on the substrate <NUM>. The stacks ST may extend in the first direction D1 and parallel to each other and may be spaced apart from each other in the second direction D2. Each of the stacks ST may be placed on the cell array region CAR and the connection region CNR. The stacks ST may have a stepwise structure on the connection region CNR. The stacks ST may have pads PAD located at different vertical levels.

Each of the stacks ST may include conductive sheets <NUM> and insulating sheets <NUM>, which are stacked in a direction perpendicular to the top surface of the substrate <NUM>. The conductive sheets <NUM> and the insulating sheets <NUM> may be alternately disposed in the third direction D3. A space between the stacks ST may be filled with a separation structure SS, as shown in <FIG>. The separation structure SS may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The separation structure SS may separate the conductive sheets <NUM>, which are provided in one of the stacks ST, from the conductive sheets <NUM>, which are provided in a neighboring one of the stacks ST, and in this case, the stacks ST may be independently controlled. Hereinafter, a variable resistance memory device according to an example will be described in more detail with reference to one of the stacks ST.

The conductive sheets <NUM> may be formed of or include a two-dimensional material containing carbon atoms. The conductive sheets <NUM> may be formed of or include graphene. For example, the conductive sheets <NUM> may include a polycyclic aromatic molecule, in which a plurality of carbon atoms are connected by covalent bonds. The carbon atoms, which are included in the graphene and are connected by covalent bonds, may have one of pentagon, hexagon, and heptagon rings as the basic repeating unit. The conductive sheets <NUM> may include at least one single-atomic-layered graphene, in which carbon atoms are connected by covalent bonds (e.g., sp<NUM> bonding) to form a single atomic layer. The single-atomic-layered graphene may have a thickness ranging from <NUM> to <NUM>. In an example embodiment, the conductive sheets <NUM> may include a mono-layered graphene, in which graphene is provided in a single-atomic-layered structure. In an example embodiment, the conductive sheets <NUM> may include one of a dual-layered graphene, which contains two layers of single-atomic-layered graphene, and a triple-layered graphene, which contains three layers of single-atomic-layered graphene. The conductive sheets <NUM> may have a thickness ranging from <NUM> to <NUM>.

The insulating sheets <NUM> may be formed of or include hexagonal boron nitride (h-BN). The hexagonal boron nitride may be a material that has a two-dimensional structure and includes boron and nitrogen atoms arranged in the form of a hexagonal ring. The hexagonal boron nitride may have a lattice constant that is close to the graphene. The bonding between the boron and nitrogen atoms in the hexagonal boron nitride may be a sp<NUM> covalent bond. The insulating sheets <NUM> may include at least one single-atomic-layered hexagonal boron nitride provided in the form of a single atomic layer. In an example embodiment, the insulating sheets <NUM> may include a plurality of single-atomic-layered hexagonal boron nitrides.

The insulating sheets <NUM> may be located at the uppermost and lowermost levels of the stack ST. That is, the stack ST may have a top surface STu and a bottom surface STI that are defined by the insulating sheets <NUM>. The insulating sheets <NUM> may be provided such that each of the conductive sheets <NUM> is interposed between a pair of insulating sheets of the insulating sheets <NUM> in a vertical direction. On the cell array region CAR, the insulating sheets <NUM> may not expose surfaces of the conductive sheets <NUM> other than the side surfaces. For example, the uppermost one of the insulating sheets <NUM> may be placed on a top surface of the uppermost one of the conductive sheets <NUM>. The lowermost one of the insulating sheets <NUM> may be placed under a bottom surface of the lowermost one of the conductive sheets <NUM>. The insulating sheets <NUM> may have the same thickness, regardless of vertical positions thereof. The conductive sheets <NUM> may have the same thickness, regardless of vertical positions thereof. In an example embodiment, the thicknesses of the insulating sheets <NUM> may be equal to the thicknesses of the conductive sheets <NUM>. For example, the insulating sheets <NUM> may have a thickness ranging from <NUM> to <NUM>.

A lower insulating layer <NUM> may be provided between the top surface of the substrate <NUM> and the bottom surface STI of the stack ST. In other words, the stack ST may be spaced apart from the substrate <NUM> with the lower insulating layer <NUM> interposed therebetween. The lower insulating layer <NUM> may not cover the entire top surface of the substrate <NUM>. A width of the lower insulating layer <NUM> in the second direction D2 may be equal to that of the stack ST, as shown in <FIG>, and the lower insulating layer <NUM> may provide isolation between the bottom surface of the stack ST and the top surface of the substrate <NUM>. The lower insulating layer <NUM> may be formed of or include at least one of, for example, silicon oxide or silicon oxynitride. A thickness of the lower insulating layer <NUM> may be larger than a thickness of the conductive sheet <NUM> and a thickness of the insulating sheet <NUM>.

An upper insulating layer <NUM> may be provided on the top surface STu of the stack ST. A width of the upper insulating layer <NUM> in the second direction D2 may be equal to that of the stack ST. The upper insulating layer <NUM> may fully cover the top surface of the stack ST (e.g., a top surface of the uppermost insulating pattern <NUM>). The upper insulating layer <NUM> may be formed of or include at least one of, for example, silicon oxide or silicon oxynitride. A thickness of the upper insulating layer <NUM> may be thicker than the thickness of the conductive sheet <NUM> and the thickness of the insulating sheet <NUM>.

The upper and lower insulating layers <NUM> and <NUM> may have an oxygen concentration that is higher than the insulating sheets <NUM>. For example, the insulating sheets <NUM> might not include an oxygen atom. The insulating sheets <NUM> may block or prevent the upper and lower insulating layers <NUM> and <NUM> from being in contact with the conductive sheets <NUM> and thus may prevent oxygen atoms in the upper and lower insulating layers <NUM> and <NUM> from infiltrating into the graphene in the conductive sheets <NUM>.

<FIG> are enlarged sectional views illustrating portions (e.g., 'A1' and 'A2' of <FIG>) of a variable resistance memory device according to an example.

Referring to <FIG> and <FIG>, the lowermost insulating sheet 220a of the insulating sheets <NUM> may be positioned between a top surface 102u of the lower insulating layer <NUM> and a bottom surface of the lowermost conductive sheet 210a. The top surface 102u of the lower insulating layer <NUM> may have a non-uniform surface roughness. The lowermost insulating sheet 220a may cover the top surface 102u of the lower insulating layer <NUM> and to mitigate or prevent deterioration in electric characteristics of the conductive sheets <NUM>, which may be caused by the nonuniform surface of the lower insulating layer <NUM>. A top surface 220au of the lowermost insulating sheet 220a may have a surface roughness that is lower than the top surface 102u of the lower insulating layer <NUM> and a bottom surface of the lowermost insulating sheet 220a. The lowermost conductive sheet 210a may be directly disposed on the top surface 220au of the lowermost insulating sheet 220a. Because the conductive sheets <NUM> are directly disposed on a surface of a low surface roughness, charge mobility (e.g., electron mobility) of the variable resistance memory device may be improved.

Referring to <FIG> and <FIG>, the uppermost insulating sheet 220b of the insulating sheets <NUM> may be positioned between a bottom surface <NUM> of the upper insulating layer <NUM> and a top surface of the uppermost conductive sheet 210b. A bottom surface 220bl of the uppermost insulating sheet 220b may have a surface roughness that is lower than the bottom surface <NUM> of the upper insulating layer <NUM> and a top surface of the uppermost insulating sheet 220b. The uppermost conductive sheet 210b may be directly disposed on the bottom surface 220bl of the uppermost insulating sheet 220b.

Referring back to <FIG>, <FIG>, and <FIG>, vertical structures VS may be provided in vertical holes VH, which vertically penetrate the stack ST. The vertical structures VS may be disposed on the cell array region CAR of the substrate <NUM>. The vertical structures VS may penetrate the upper insulating layer <NUM>, the stack ST, and the lower insulating layer <NUM> and may be connected to the substrate <NUM>. In an example embodiment, the vertical structures VS penetrating each stack ST may be arranged in the first direction D1. Each of the vertical structures VS may include a resistance varying layer <NUM>, a conductive pattern <NUM>, and a gapfill insulating pattern <NUM>.

The resistance varying layer <NUM> may be positioned between the conductive pattern <NUM> and an inner side surface of the stack ST defining the vertical hole VH. The resistance varying layer <NUM> may vertically extend to cover an outer side surface of the conductive pattern <NUM>. The resistance varying layer <NUM> may cover the inner side surface of the stack ST defining the vertical hole VH. The resistance varying layer <NUM> may be in contact with side surfaces of the conductive sheets <NUM> and side surfaces of the insulating sheets <NUM>, which are exposed through the inner side surface of the stack ST defining the vertical hole VH. In an example embodiment, the resistance varying layer <NUM> may have a pipe shape. The resistance varying layer <NUM> may be configured to have an electric resistance that can be changed by electric signals applied to a conductive line CL and the bit line BL. For example, the resistance varying layer <NUM> may be changed from a low resistance state to a high resistance state or from a high resistance state to a low resistance state, depending on voltages applied to the conductive sheet <NUM> and the conductive pattern <NUM>. The resistance varying layer <NUM> includes carbon nanotubes (CNT). The carbon nanotubes of the resistance varying layer <NUM> are electrically connected to at least one of the conductive sheet <NUM> and the conductive pattern <NUM>. A change in resistance of the resistance varying layer <NUM> may be achieved by displacement of carbon nanotubes in the resistance varying layer <NUM>. The carbon nanotubes of the resistance varying layer <NUM> may include one of a single-walled carbon nanotube (SWCNT) and a double-walled carbon nanotube (DWCNT). A change in resistance of the resistance varying layer <NUM> will be described in more detail with reference to <FIG> and <FIG>.

<FIG> and <FIG> are enlarged sectional views illustrating portions (e.g., 'B1' and 'B2' of <FIG>) of a variable resistance memory device according to an example.

Referring to <FIG>, <FIG>, and <FIG>, a thickness of the resistance varying layer <NUM> may increase as a distance to the substrate <NUM> decreases. The thickness of the resistance varying layer <NUM> may mean a horizontal distance between an outer side surface of the resistance varying layer <NUM>, which faces an inner side surface of the stack ST defining the vertical hole VH, and an inner side surface of the resistance varying layer <NUM>, which faces the conductive pattern <NUM>. For example, as shown in <FIG> and <FIG>, a thickness of the resistance varying layer <NUM> in the first direction D1 may gradually increase as a distance to the substrate <NUM> decreases. A thickness t2 of a bottom end of the resistance varying layer <NUM> may be larger than a thickness t1 of a top end of the resistance varying layer <NUM>.

The conductive pattern <NUM> may be vertically extended in the vertical hole VH and may be electrically connected to the bit line BL through a bit line contact plug BCP. The conductive pattern <NUM> may conformally cover the inner side surface of the resistance varying layer <NUM>. The conductive pattern <NUM> may have a uniform thickness, unlike the thickness of the resistance varying layer <NUM>. The conductive pattern <NUM> may cover the top surface of the substrate <NUM> and may be in direct contact with the top surface of the substrate <NUM>. The conductive pattern <NUM> may be provided in a half-opened shape with open top end and closed bottom end. The conductive pattern <NUM> may include graphene. In an example embodiment, the conductive pattern <NUM> may include a mono-layered graphene containing one single-atomic-layered graphene. In an example embodiment, the conductive pattern <NUM> may include one of a dual-layered graphene, which contains two layers of single-atomic-layered graphene, and a triple-layered graphene, which contains three layers of single-atomic-layered graphene.

The gapfill insulating pattern <NUM> may be vertically extended, in the vertical hole VH. The gapfill insulating pattern <NUM> may fill a remaining portion of the vertical hole VH which is partially filled with the resistance varying layer <NUM> and the conductive pattern <NUM>. The gapfill insulating pattern <NUM> may cover an inner side surface of the conductive pattern <NUM>. A top end of the gapfill insulating pattern <NUM> may be located at the same level as a top end of the resistance varying layer <NUM> and a top end of the conductive pattern <NUM>. The top end of the gapfill insulating pattern <NUM> may be covered with the bit line contact plug BCP. The gapfill insulating pattern <NUM> may be formed of or include at least one of, for example, silicon oxide or silicon nitride. A width of the gapfill insulating pattern <NUM> may decrease as a distance to the substrate <NUM> decreases. For example, a width w1 of the top end of the gapfill insulating pattern <NUM> may be larger than a width w2 of a bottom end of the gapfill insulating pattern <NUM>.

<FIG> and <FIG> are enlarged sectional views, each of which illustrates a portion 'C' of <FIG>.

Referring to <FIG> and <FIG>, the resistance varying layer <NUM> may include first carbon nanotubes CNT1, which are adjacent to an inner side surface VHs of the stack ST defining the vertical hole VH, and second carbon nanotubes CNT2, which are adjacent to a side surface <NUM> of the conductive pattern <NUM>. The first carbon nanotubes CNT1 may be attached to side surfaces of the conductive sheets <NUM> and the insulating sheets <NUM>. Some of the first carbon nanotubes CNT1 may be electrically connected to the conductive sheets <NUM>. The second carbon nanotubes CNT2 may be attached to the side surface <NUM> of the conductive pattern <NUM> and may be electrically connected to the conductive pattern <NUM>. Some of the first carbon nanotubes CNT1 may be on side surfaces of the insulating sheets <NUM> and may be electrically disconnected from the conductive sheets <NUM> and the conductive pattern <NUM>.

An electric resistance (hereinafter, resistance) of the resistance varying layer <NUM> may be locally controlled, based on the disposition and connection of the first and second carbon nanotubes CNT1 and CNT2. For example, some of the first and second carbon nanotubes CNT1 and CNT2, which are located between the conductive sheets <NUM> and the conductive pattern <NUM>, may be connected to or disconnected from each other, and this may be used to control a resistance of the resistance varying layer <NUM> in a horizontal direction. For example, the first carbon nanotubes CNT1, which are electrically connected to a first conductive sheet 210_1 of the conductive sheet <NUM>, may be electrically disconnected from the second carbon nanotubes CNT2. By contrast, the first carbon nanotubes CNT1, which are electrically connected to a second conductive sheet 210_2 of the conductive sheet <NUM>, may be electrically connected to some of the second carbon nanotubes CNT2. Thus, a resistance between the second conductive sheet 210_2 and the conductive pattern <NUM> may be smaller than a resistance between the first conductive sheet 210_1 and the conductive pattern <NUM>.

Referring to <FIG>, <FIG>, and <FIG>, the variable resistance memory device according to an example may be configured to execute a data write operation through localized control of the resistance of the resistance varying layer <NUM>. Data in the variable resistance memory device may be determined by measuring a resistance between each of the conductive sheets <NUM> and the conductive pattern <NUM>.

The data writing operation on the resistance varying layer <NUM> may include a set operation of bringing the first and second carbon nanotubes CNT1 and CNT2, which are separated from each other, into contact with each other and a reset operation of separating the first and second carbon nanotubes CNT1 and CNT2, which are in contact with each other. In an example embodiment, the set and reset operations may be independently performed between each of the conductive sheets <NUM> and the conductive pattern <NUM>.

The set operation may include applying the ground voltage to the conductive pattern <NUM> and selectively applying a set voltage to the conductive sheet <NUM> to be set. For example, the set voltage may be selectively applied to the second conductive sheet 210_2. The first carbon nanotubes CNT1, which are electrically connected to the second conductive sheet 210_2, may come close to the second carbon nanotubes CNT2 adjacent thereto by an electrostatic force produced by the set voltage. The first and second carbon nanotubes CNT1 and CNT2, which are sufficiently close to each other by the electrostatic force, may contact each other by the van der Waals force. The first and second carbon nanotubes CNT1 and CNT2 may be bent by an electrostatic force and a van der Waals force, as shown in <FIG>.

The reset operation may include applying the ground voltage to one of the conductive pattern <NUM> and the conductive sheet <NUM> and repeatedly producing a potential difference between the conductive pattern <NUM> and the conductive sheet <NUM>. Voltages, which are applied to the conductive pattern <NUM> and the conductive sheet <NUM>, respectively, may cause a charge variation in the first and second carbon nanotubes CNT1 and CNT2. The repetition of the charge variation may lead to mechanical oscillation of the first and second carbon nanotubes CNT1 and CNT2 and thus may separate the first and second carbon nanotubes CNT1 and CNT2 from each other. In this case, the first and second carbon nanotubes CNT1 and CNT2, which are bent by the electrostatic force and the van der Waals force, may be restored to their original (e.g., unbent) states by their own elastic forces.

The voltages for the set and reset operations may be determined depending on an elastic modulus of the carbon nanotubes. In the case where the carbon nanotubes are prepared to have a proper elastic modulus, it may be possible to improve electric reliability in the set and reset operations. In an example embodiment, each of the first and second carbon nanotubes CNT1 and CNT2 may include one of a single-walled carbon nanotube (SWCNT) and a double-walled carbon nanotube (DWCNT).

Referring back to <FIG>, <FIG>, and <FIG>, a first interlayer insulating layer <NUM> and a second interlayer insulating layer <NUM> may be sequentially stacked on the upper insulating layer <NUM>. The first interlayer insulating layer <NUM> may cover a top surface of the upper insulating layer <NUM> and may cover a portion of a top surface of the vertical structure VS. The first interlayer insulating layer <NUM> may cover a portion (e.g., a top portion) of a side surface of the separation structure SS. A top surface of the first interlayer insulating layer <NUM> may be located at the same vertical level as a top surface of the separation structure SS. The second interlayer insulating layer <NUM> may cover the top surface of the first interlayer insulating layer <NUM> and the top surface of the separation structure SS. The first and second interlayer insulating layers <NUM> and <NUM> may be formed of or include at least one of, for example, silicon oxide, silicon oxynitride, or silicon nitride. In an example embodiment, the first and second interlayer insulating layers <NUM> and <NUM> may be formed of or include the same material, and there may be no observable interface therebetween.

The bit lines BL may be provided on the stack ST of the cell array region CAR. In an example embodiment, the bit lines BL may be located on the top surface STu of the stack ST. The bit lines BL may be connected to the vertical structure VS through bit line contact plugs BCP, which are formed to penetrate the first and second interlayer insulating layers <NUM> and <NUM>. The bit line contact plugs BCP may electrically connect the bit lines BL to the conductive pattern <NUM>. Each of the bit line contact plugs BCP may fully cover a top surface of the gapfill insulating pattern <NUM> and to at least partially cover a top surface of the conductive pattern <NUM>. The bit lines BL may be arranged in the first direction D1 and may be extended in the second direction D2 and parallel to each other. Each of the bit lines BL may be connected in common to corresponding vertical structures VS penetrating different ones of the stacks ST, respectively.

Referring back to <FIG>, the conductive lines CL may be provided on the connection region CNR and may overlap the stack ST. In an example embodiment, the conductive lines CL may be extended in the first direction D1. The conductive lines CL may be connected to the conductive sheets <NUM> of the stack ST through word line contact plugs WCP, which vertically extend. Each of the conductive lines CL may be connected to a corresponding one of the conductive sheets <NUM> in a one-to-one manner. Each of the conductive sheets <NUM> may receive an operation voltage independently through a corresponding one of the conductive lines CL. In an example embodiment, the conductive lines CL may be located at the same level, and the word line contact plugs WCP may have various lengths, depending on vertical positions of the conductive sheets <NUM> connected thereto.

For example, each of the conductive sheets <NUM> may have a partially exposed top surface on the connection region CNR, and the pads PAD of the stack ST may be defined by the exposed top surfaces of the conductive sheets <NUM>. Each of the conductive lines CL may be electrically connected to a corresponding one of the pads PAD through the word line contact plug WCP. <FIG> illustrates an example, in which two conductive lines CL and two word line contact plugs WCP are provided, but the numbers of the conductive lines CL and the word line contact plugs WCP are not limited to this example. For example, the numbers of the conductive lines CL and the word line contact plugs WCP, which are provided in the variable resistance memory device, may be equal to the number of the pads PAD.

<FIG> is a perspective view illustrating a cell array region of a variable resistance memory device not in accordance with the claimed invention. For concise description, previously described elements may be identified by the same reference numbers without repeating overlapping descriptions thereof.

Referring to <FIG>, the bit lines BL may be placed below the bottom surfaces STI of the stack ST. For example, a first lower interlayer insulating layer <NUM> may be provided on the top surface of the substrate <NUM>. The first lower interlayer insulating layer <NUM> may cover the entire top surface of the substrate <NUM>. The bit lines BL may be arranged in the first direction D1 on a top surface of the first lower interlayer insulating layer <NUM> and may be extended in the second direction D2 and parallel to each other. The bit lines BL may be covered with a second lower interlayer insulating layer <NUM>. The first and second lower interlayer insulating layers <NUM> and <NUM> may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The first and second lower interlayer insulating layers <NUM> and <NUM> may be formed of the same material, and there may be no observable interface therebetween.

The bit line contact plug BCP may penetrate the second lower interlayer insulating layer <NUM> and to electrically connect the bit line BL to the conductive pattern <NUM>. The bit line contact plug BCP may be provided between a top surface of the bit line BL and a bottom end of the conductive pattern <NUM> and extend in the third direction D3 and be in direct contact with the bottom end of the conductive pattern <NUM>.

<FIG> is a sectional view illustrating a variable resistance memory device according to an example embodiment. <FIG> is an enlarged sectional view illustrating a portion 'D' of <FIG>. For concise description, previously described elements may be identified by the same reference numbers without repeating overlapping descriptions thereof.

Referring to <FIG> and <FIG>, the resistance varying layer <NUM> has protruding portions PP which horizontally extend toward side surfaces <NUM> of the insulating sheets <NUM>. The side surface <NUM> of the conductive pattern <NUM> are farther from the side surfaces <NUM> of the insulating sheets <NUM> than from side surfaces <NUM> of the conductive sheets <NUM>. That is, the side surfaces <NUM> of the insulating sheets <NUM> are recessed in a direction away from the side surface <NUM> of the conductive pattern <NUM>. The side surfaces <NUM> of the insulating sheets <NUM> are located between a vertically-adjacent pair of the conductive sheets <NUM> or between a top surface 210u and a bottom surface <NUM> thereof. The protruding portion PP of the resistance varying layer <NUM> may fill a space between the top and bottom surfaces 210u and 210I of the conductive sheets <NUM>. The protruding portion PP may be in direct contact with the top and bottom surfaces 210u and 210I of the conductive sheets <NUM> and the side surfaces <NUM> of the insulating sheets <NUM>. A vertical thickness of the protruding portion PP may be the same as or substantially equal to a vertical thickness of the insulating sheet <NUM>.

That is, the side surfaces <NUM> of the conductive sheets <NUM> protrude in a direction from the side surfaces <NUM> of the insulating sheets <NUM> toward the side surface <NUM> of the conductive pattern <NUM>. Portions of the top and bottom surfaces 210u and <NUM> of the conductive sheets <NUM> may not be covered with the insulating sheets <NUM>. Thus, a contact area between the conductive sheets <NUM> and carbon nanotubes in the resistance varying layer <NUM> may be increased. Meanwhile, because a distance between the side surfaces <NUM> of the insulating sheets <NUM> and the side surface <NUM> of the conductive pattern <NUM> is increased, it may be possible to mitigate or prevent a short circuit from being undesirably formed between the carbon nanotubes in the resistance varying layer <NUM>. Accordingly, it may be possible to improve electric reliability of the variable resistance memory device.

<FIG> and <FIG> are sectional views illustrating a variable resistance memory device according to an example. For concise description, previously described elements may be identified by the same reference numbers without repeating overlapping descriptions thereof, and features, which are different from those of the variable resistance memory device described with reference to <FIG>, will be described below.

Referring to <FIG>, the resistance varying layer <NUM> may have a uniform thickness. The resistance varying layer <NUM> may conformally cover the inner side surface VHs of the stack defining the vertical hole VH. The gapfill insulating pattern <NUM> may have a constant width, regardless of a distance to the substrate <NUM>. A width of a top end of the gapfill insulating pattern <NUM> may be equal to a width of a bottom end thereof. For example, the gapfill insulating pattern <NUM> may have a cylindrical shape.

Referring to <FIG>, the vertical structure VS may be composed of the resistance varying layer <NUM> and the conductive pattern <NUM>. In other words, the vertical structure VS need not include the gapfill insulating pattern <NUM> described with reference to <FIG>.

For example, the resistance varying layer <NUM> may cover the inner side surface of the stack ST defining the vertical hole VH. The resistance varying layer <NUM> may have an increasing thickness as a distance to the substrate <NUM> decreases. The conductive pattern <NUM> may fully fill a remaining portion of the vertical hole VH, which is partially filled with the resistance varying layer <NUM>. A width of the conductive pattern <NUM> may decrease as a distance to the substrate <NUM> decreases.

<FIG> are sectional views illustrating a method of fabricating a variable resistance memory device, according to an example.

Referring to <FIG>, the lower insulating layer <NUM> may be formed on the substrate <NUM>. In an example embodiment, the substrate <NUM> may be formed of or include a semiconductor material that is doped to have a first conductivity type. The first conductivity type may be, for example, n-type. The lower insulating layer <NUM> may be formed by performing a chemical vapor deposition (CVD) process on the top surface of the substrate <NUM>. The lower insulating layer <NUM> may be formed of or include at least one of, for example, silicon oxide or silicon oxynitride.

A mold structure MS may be formed by repeatedly stacking the insulating sheets <NUM> and the conductive sheets <NUM> on the lower insulating layer <NUM>. The insulating sheets <NUM> and the conductive sheets <NUM> may be alternately formed. The insulating sheets <NUM> may include bottom and top insulating sheets corresponding to the lowermost and uppermost portions of the mold structure MS, respectively. The conductive sheets <NUM> may be formed between a pair of the insulating sheets <NUM>, which are vertically adjacent to each other.

For example, the insulating sheet <NUM> may be formed on the lower insulating layer <NUM> through a mechanical transfer process or a chemical vapor deposition process. The mechanical transfer process may include attaching a previously-prepared hexagonal boron nitride sheet to the lower insulating layer <NUM>. The chemical vapor deposition process may include directly growing a hexagonal boron nitride sheet on the lower insulating layer <NUM> using a source material containing nitrogen (N) and boron (B). The source material may include at least one of, for example, NH<NUM>, N<NUM>, BH<NUM>, BF<NUM>, BCl<NUM>, B<NUM>H<NUM>, (CH<NUM>CH<NUM>)<NUM>B, (CH<NUM>)<NUM>B, H<NUM>NBH<NUM>, or (BH)<NUM>(NH)<NUM>. The conductive sheets <NUM> may be directly formed on the insulating sheet <NUM>. The formation of the conductive sheets <NUM> may include growing graphene on the insulating sheet <NUM> using a chemical vapor deposition process. The insulating sheets <NUM> and the conductive sheets <NUM> may be alternately formed to form the mold structure MS.

Referring to <FIG>, the upper insulating layer <NUM> may be formed on the mold structure MS, and then, the vertical holes VH may be formed to penetrate the upper insulating layer <NUM>, the mold structure MS, and the lower insulating layer <NUM>. The formation of the vertical holes VH may include forming a mask pattern on the upper insulating layer <NUM> and performing a reactive ion etching (RIE) process.

Referring to <FIG>, a preliminary resistance varying layer 320p may be formed on the upper insulating layer <NUM>. The preliminary resistance varying layer 320p may be formed to cover the inner side surfaces of the mold structure MS defining the vertical holes VH and the top surface of the upper insulating layer <NUM>. The preliminary resistance varying layer 320p may include one of a single-walled carbon nanotube (SWCNT) and a double-walled carbon nanotube (DWCNT). In an example embodiment, the formation of the preliminary resistance varying layer 320p may include directly providing carbon nanotubes on the top surface of the upper insulating layer <NUM> and the inner side surfaces of the vertical holes VH using a spin coating process. The carbon nanotubes, which are provided on the top surface of the upper insulating layer <NUM> and the inner side surfaces of the mold structure MS defining the vertical holes VH, may be attached to exposed surfaces of the upper insulating layer <NUM> and the mold structure MS defining the vertical holes VH by a van der Waals force. In an example embodiment, the formation of the preliminary resistance varying layer 320p may include supplying a composite material, in which carbon nanotubes are scattered, onto the upper insulating layer <NUM> using a spin coating process and drying the composite material.

Referring to <FIG> and <FIG>, the vertical structures VS may be formed by sequentially forming the conductive pattern <NUM> and the gapfill insulating pattern <NUM> in the vertical holes VH. For example, a conductive layer may be formed to conformally cover the preliminary resistance varying layer 320p. The forming of the conductive layer may include growing graphene on a surface of the preliminary resistance varying layer 320p using a chemical vapor deposition process. An insulating layer may be formed to fill a remaining portion of the vertical hole VH, which is partially filled with the preliminary resistance varying layer 320p and the conductive layer. The insulating layer may include at least one of, for example, silicon oxide or silicon oxynitride and may be formed by a chemical vapor deposition process. Thereafter, a planarization process may be performed to expose the top surface of the upper insulating layer <NUM>. During the planarization process, the preliminary resistance varying layer 320p, the conductive layer, and the insulating layer may be partially removed to form vertical the vertical structures VS, which are provided in the respective vertical holes VH and are isolated from each other.

Referring to <FIG> and <FIG>, the first interlayer insulating layer <NUM> may be formed on the upper insulating layer <NUM>. The first interlayer insulating layer <NUM> may be thickly formed using a chemical vapor deposition process. A patterning process may be performed on the mold structure MS to form the stacks ST. The patterning process may include forming a mask pattern on the first interlayer insulating layer <NUM> and performing an etching process. The etching process may include a reactive ion etching process. The stacks ST may be spaced apart from each other in the second direction D2 by a trench, which is formed by a patterning process and is interposed between the stacks ST. Before forming the stacks ST from the mold structure MS, a trimming process may be performed to form a staircase structure in a portion of the mold structure MS. The staircase structure may be formed on the connection region CNR, as shown in <FIG>.

Referring back to <FIG> and <FIG>, the separation structure SS may be formed to fill the trench between the stacks ST. The second interlayer insulating layer <NUM> may be formed to cover top surfaces of the first interlayer insulating layer <NUM> and the separation structure SS. Thereafter, the bit line contact plug BCP, the word line contact plug WCP, the bit lines BL, and the conductive lines CL may be formed.

<FIG> is a schematic circuit diagram illustrating a variable resistance memory device according to an example embodiment. <FIG> is a sectional view illustrating a variable resistance memory device according to an example. For concise description, previously described elements may be identified by the same reference numbers without repeating overlapping descriptions thereof.

Referring to <FIG>, the variable resistance memory device may include selection transistors STR, which are provided between the common source line CSL and the cell string CS. For example, the selection transistors STR may be ground selection transistors, which are used to connect or disconnect the cell strings CS to or from the common source line CSL applied with the ground voltage. The selection transistors STR, which are connected to the cell strings CS, respectively, may be connected in common to a selection line SL.

Referring to <FIG>, a lower interlayer insulating layer <NUM> may be provided on the top surface of the substrate <NUM>. The lower interlayer insulating layer <NUM> may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

A lower conductive line <NUM> may be provided on a top surface of the lower interlayer insulating layer <NUM>. A top surface of the lower conductive line <NUM> may be covered with the lower insulating layer <NUM>. The lower conductive line <NUM> may be the selection line SL described with reference to <FIG>. A thickness of the lower conductive line <NUM> may be larger than a thickness of the conductive sheet <NUM> and a thickness of the insulating sheets <NUM>. The lower conductive line <NUM> may be formed of or include at least one of, for example, doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, and aluminum), conductive metal nitrides (e.g., titanium nitride and tantalum nitride), or transition metals (e.g., titanium and tantalum).

A lower semiconductor pattern <NUM> may penetrate the lower insulating layer <NUM>, the lower interlayer insulating layer <NUM>, and the lower conductive line <NUM> and may be connected to the substrate <NUM>. The lower semiconductor pattern <NUM> may be electrically connected to the conductive pattern <NUM> of the vertical structure VS. The lower semiconductor pattern <NUM> may include a pillar-shaped epitaxial layer, which is grown from the substrate <NUM>. The lower semiconductor pattern <NUM> may be formed of or include silicon (Si). Alternatively, the lower semiconductor pattern <NUM> may include at least one of germanium (Ge), silicon germanium (SiGe), III-V semiconductor compounds, and/or II-VI semiconductor compounds. A gate insulating layer <NUM> may be disposed on a portion of a side surface of the lower semiconductor pattern <NUM>. The gate insulating layer <NUM> may be disposed between the lower conductive line <NUM> and the lower semiconductor pattern <NUM>. The gate insulating layer <NUM> may include a silicon oxide layer (e.g., a thermal oxide layer). The gate insulating layer <NUM> may have a rounded side surface. The lower semiconductor pattern <NUM>, the gate insulating layer <NUM>, and the lower conductive line <NUM> may constitute the selection transistor STR described with reference to <FIG>.

<FIG> is a perspective view illustrating a variable resistance memory device not in accordance with the invention. <FIG> is a sectional view taken along a line III-III' of <FIG>.

Referring to <FIG> and <FIG>, a variable resistance memory device may include a lower insulating sheet <NUM>, a lower conductive layer <NUM>, a resistance varying layer <NUM>, an upper conductive layer <NUM>, an upper insulating sheet <NUM>, and a penetration structure PS.

The lower and upper conductive layers <NUM> and <NUM> may be disposed to be vertically spaced apart from each other. The lower and upper conductive layers <NUM> and <NUM> may be formed of or include a two-dimensional material containing carbon atoms. For example, the lower and upper conductive layers <NUM> and <NUM> may be formed of or include graphene. Each of the lower and upper conductive layers <NUM> and <NUM> may include a mono-layered graphene containing one graphene sheet. In an example, each of the lower and upper conductive layers <NUM> and <NUM> may include one of a dual-layered graphene, which contains two graphene sheets, and a triple-layered graphene, which contains three graphene sheets.

The resistance varying layer <NUM> may be located between the lower and upper conductive layers <NUM> and <NUM>. The resistance varying layer <NUM> may include carbon nanotubes (CNT). The carbon nanotubes of the resistance varying layer <NUM> may include one of a single-walled carbon nanotube (SWCNT) or a double-walled carbon nanotube (DWCNT).

The penetration structure PS may be extended in the first direction D1 to penetrate the resistance varying layer <NUM>. The penetration structure PS may include an insulating pillar <NUM>, an insulating sheet <NUM>, and a conductive sheet <NUM>. The insulating pillar <NUM> may be a bar-shaped pattern extended in the first direction D1. The insulating pillar <NUM> may have rounded corners. The rounded corners of the insulating pillar <NUM> may be formed by forming the insulating pillar <NUM> with sharp corners and performing an isotropic etching process on the insulating pillar <NUM>. The insulating pillar <NUM> may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

The insulating sheet <NUM> may be formed of or include hexagonal boron nitride (h-BN). The insulating sheet <NUM> may include at least one single-atomic-layered hexagonal boron nitride provided in the form of a single atomic layer. In an example, the insulating sheet <NUM> may include a plurality of single-atomic-layered hexagonal boron nitrides.

The conductive sheet <NUM> may be formed of or include a two-dimensional material containing carbon atoms. The conductive sheet <NUM> may include graphene. The conductive sheet <NUM> may include one of a dual-layered graphene, which contains two layers of single-atomic-layered graphene, and a triple-layered graphene, which contains three layers of single-atomic-layered graphene.

<FIG> is an enlarged sectional view illustrating a portion 'E' of <FIG>.

Referring to <FIG> and <FIG>, the insulating sheet <NUM> may have a first surface 432i and a second surface 432o, which are provided to face the insulating pillar <NUM> and the conductive sheet <NUM>, respectively. The second surface 432o may have a surface roughness that is lower than the first surface 432i.

The resistance varying layer <NUM> may include third carbon nanotubes CNT3 and fourth carbon nanotubes CNT4. The third carbon nanotubes CNT3 may be attached to the conductive sheet <NUM> and may be electrically connected to the conductive sheet <NUM>. Some of the fourth carbon nanotubes CNT4 may be attached to the upper conductive layer <NUM> and may be electrically connected to the upper conductive layer <NUM>. Although not shown, others of the fourth carbon nanotubes CNT4 may be attached to the lower conductive layer <NUM> and may be electrically connected to the lower conductive layer <NUM>. Resistance of the resistance varying layer <NUM> may vary depending on voltages, which are applied to the conductive sheet <NUM>, the upper conductive layer <NUM>, and the lower conductive layer <NUM>. The resistance of the resistance varying layer <NUM> may be locally adjusted depending on a change in disposition and connection of the third and fourth carbon nanotubes CNT3 and CNT4. The disposition and connection of the third and fourth carbon nanotubes CNT3 and CNT4 may be changed in an analogous manner to that described with reference to <FIG> and <FIG>.

Data may be written in the variable resistance memory device by locally controlling the resistance of the resistance varying layer <NUM>. Data in the variable resistance memory device may be determined by measuring a resistance between the upper conductive layer <NUM> and the conductive sheet <NUM> or a resistance between the lower conductive layer <NUM> and the conductive sheet <NUM>.

According to an example embodiment, a resistance varying layer includes carbon nanotube. A resistance of the resistance varying layer may be locally changed by a mechanical change or deformation of the carbon nanotube, and the carbon nanotube may be restored to its original (e.g., undeformed) state by its own elastic force. This may make it possible to realize a variable resistance memory device with improved endurance.

Any functional blocks shown in the figures and described above may be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

Claim 1:
A variable resistance memory device, comprising:
a stack (ST) including insulating sheets (<NUM>) and conductive sheets (<NUM>), which are alternatingly stacked on a substrate (<NUM>), the stack including a vertical hole (VH) vertically penetrating therethrough;
a bit line (BL) on the stack (ST);
a conductive pattern (<NUM>) electrically connected to the bit line (BL) and vertically extending in the vertical hole (VH); and
a resistance varying layer (<NUM>) between the conductive pattern (<NUM>) and an inner side surface of the stack (ST) defining the vertical hole (VH),
wherein the resistance varying layer (<NUM>) comprises a first carbon nanotube (CNT1) electrically connected to one of the conductive sheets (<NUM>), and a second carbon nanotube (CNT2) electrically connected to the conductive pattern (<NUM>);
wherein the resistance varying layer (<NUM>) comprises a protruding portion (PP) protruding toward side surfaces (<NUM>) of the insulating sheets (<NUM>); and
wherein the resistance varying layer (<NUM>) has an increasing thickness as a distance to the substrate (<NUM>) decreases.