Patent Description:
The disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same.

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is consisted of a plurality of memory cells, and each of the memory cells usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage applied on the word line can control the turn-on and turn-off of the transistor, so that data information stored in the capacitor can be read from or written into the capacitor through the bit line. Background may be found in <CIT>.

With the continuous development of semiconductor chips, the critical dimension of semiconductor chips is shrinking. However, due to the limitation of the structure of a lithography machine itself, there is a limit to the size reduction of a lithography pattern on semiconductor chips. Therefore, semiconductor devices such as a DRAM with three-dimensional structure came into being. However, the existing semiconductor devices still have some problems, such as large internal coupling capacitance effect, as such the yield of semiconductor devices has a space to be further improved.

Therefore, how to further reduce the coupling capacitance effect inside semiconductor devices, so as to improve the electrical properties of the semiconductor devices, is an urgent technical problem to be solved at present.

The present invention is defined in appended independent claims <NUM> and <NUM> to which reference should be made.

Specific embodiments of the semiconductor device and the method for forming the same provided by the disclosure will be described in detail below with reference to the drawings.

The specific embodiments provide a semiconductor device. <FIG> is a structural top view of a semiconductor device of the specific embodiment of the disclosure; <FIG> is a schematic cross-sectional view of <FIG> at location AA; and <FIG> is a partial three-dimensional structure diagram of a semiconductor device of a specific embodiment of the disclosure. As shown in <FIG>, <FIG> and <FIG>, the semiconductor device includes a substrate, a memory structure and a peripheral structure.

The substrate <NUM> includes a memory region <NUM> and a peripheral region <NUM> located at an outer side of the memory region <NUM>.

The memory structure is located above the memory region <NUM> and includes a memory array and a plurality of signal lines, in which the memory array at least includes a plurality of memory cells spaced apart from each other along a first direction D1, and the signal lines are electrically connected with the memory cells, where the first direction D1 is perpendicular to a top surface of the substrate <NUM>.

The peripheral structure is located above the peripheral region <NUM> and includes peripheral stacked layers <NUM>, peripheral circuits located above the peripheral stacked layers <NUM>, and a plurality of peripheral leads located above the peripheral circuits. One end of each of the peripheral leads is electrically connected with one of the peripheral circuits, and the other end is electrically connected with one of the signal lines.

Specifically, the substrate <NUM> may be, but is not limited to a silicon substrate. The present embodiment is described by taking a silicon substrate as the substrate <NUM> as an example. In other embodiments, the substrate <NUM> may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate <NUM> supports device structures on its surface. In an example, the peripheral region <NUM> is located at an outer side of the memory region <NUM> along a second direction D2 parallel to the top surface of the substrate <NUM>, as shown in <FIG> and <FIG>. In other examples, a plurality of the memory regions <NUM> may be arranged around the periphery of the peripheral region <NUM>, thereby further improving the integration of the semiconductor device. The top surface of the substrate <NUM> refers to the surface of the substrate <NUM> facing the memory structure and the peripheral structure.

In an example, the top surfaces of the signal lines (e.g. the word lines <NUM> and/or the bit lines <NUM> in <FIG> and <FIG>) are electrically connected to the peripheral leads, and the bottom surfaces of the peripheral leads are electrically connected to the peripheral circuits in direct contact. The peripheral circuits in the peripheral structure are electrically connected to the signal lines in the memory structure through the peripheral leads (e.g. the first peripheral leads <NUM> and/or the second peripheral leads <NUM> in <FIG> and <FIG>), thereby transmitting external control signals to the memory cells to realize operations of the memory cells, such as reading, writing, and erasing. Herein, the peripheral circuit may be, but is not limited to, a CMOS circuit. In the specific embodiments, the peripheral circuits in the peripheral structure are arranged above the peripheral stacked layers <NUM>, thereby reducing the height difference between the peripheral circuits and the top surfaces of the signal lines, so that the length of the peripheral leads, which are electrically connected the peripheral circuits and the signal lines, along the first direction D1 is reduced. Therefore, the facing area between the adjacent peripheral leads is reduced, and thus the coupling capacitance effect between the adjacent peripheral leads is reduced, thereby realizing the improvement of the electrical performance of the semiconductor device. In addition, in the embodiments, the peripheral circuits are formed above the peripheral stacked layers <NUM>, so that the requirements of the peripheral structure on the substrate <NUM> is reduced, and the selection range of the substrate <NUM> is expanded, thereby contributing to further improving the performance of the semiconductor device and improving the yield of semiconductor devices.

In an embodiment, the semiconductor device further includes a third isolation layer <NUM> on the substrate <NUM>. The third isolation layer <NUM> is located between the memory structure and the peripheral structure for isolating the memory structure and the peripheral structure. The top surface of the third isolation layer <NUM> is above the top surface of the memory array, and the top surface of the third isolation layer <NUM> is flush with or higher than the top surfaces of the signal lines. The semiconductor device also includes a dielectric layer <NUM> covering the memory structure, the peripheral structure and the third isolation layer <NUM>, and the dielectric layer <NUM> is planarized to facilitate the formation of subsequent metal interconnect layers or other device structures.

In some embodiments, the peripheral stacked layers <NUM> include first semiconductor layers <NUM> and second semiconductor layers <NUM> alternately stacked along the first direction D1. The peripheral structure further includes a first isolation layer <NUM> located between the peripheral stacked layers <NUM> and the peripheral circuits.

In some embodiments, each of the peripheral circuits includes a peripheral substrate and a peripheral electrode.

The peripheral substrate <NUM> includes a peripheral active area, and the top surface of the peripheral substrate <NUM> is flush with or higher than the top surface of the memory array.

The peripheral electrode <NUM> is located above the peripheral active area, and one end of a peripheral lead is electrically connected with the peripheral electrode <NUM>, and the other end is electrically connected with a signal line.

Specifically, the peripheral structure includes the peripheral stacked layers <NUM>, the first isolation layer <NUM> and the peripheral circuits stacked in sequence along the first direction D1. The first isolation layer <NUM> is used for electrically isolating the peripheral stacked layers and the peripheral circuits. In order to simplify the manufacturing process of the semiconductor device, in an embodiment, the material of the first semiconductor layer <NUM> is Si, and the material of the second semiconductor layer <NUM> is SiGe. The material of the first isolation layer <NUM> may be, but is not limited to, an oxide material (e.g. silicon dioxide). The peripheral circuit includes a peripheral transistor including a peripheral active area (e.g. including a peripheral channel region, a peripheral source region, and a peripheral drain region) located in the peripheral substrate <NUM> and a peripheral electrode (e.g. including a peripheral gate electrode, a peripheral source electrode, and a peripheral drain electrode) located above the peripheral active area. one peripheral lead is electrically connected to the peripheral gate electrode, the peripheral source electrode or the peripheral drain electrode among the peripheral electrodes.

In order to enhance the electrical properties of the peripheral structure, in some embodiments, the peripheral substrate <NUM> is a fully depleted silicon-on-insulator substrate, a partly depleted silicon-on-insulator substrate, or a metal oxide semiconductor substrate. In an example, the metal oxide semiconductor substrate may be selected from InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, or a combination thereof, in which <NUM> < x < <NUM>, <NUM> < y < <NUM>, <NUM> < z < <NUM>.

In some embodiments, the signal lines extend along the first direction D1 and are electrically connected to a plurality of the memory cells, which are spaced apart from each other along the first direction D1.

The top surface of the peripheral substrate <NUM> is flush with the top surfaces of the signal lines.

In some embodiments, the peripheral region <NUM> is arranged at an outer side of the memory region <NUM> along a second direction D2. The memory structure further includes signal line plugs extending along the first direction D1 and electrically connected with the signal lines in contact. The peripheral leads extend along the first direction D1, and the length of the peripheral leads in the first direction D1 is less than or equal to the length of the signal line plugs in the first direction D1. The semiconductor device further includes connecting bridges.

The connecting bridges are located above the memory structure and the peripheral structure and extend in the second direction D2. One end of one of the connecting bridges is electrically connected with one signal line plug in contact and the other end is electrically connected with one peripheral lead in contact. The second direction D2 is parallel to the top surface of the substrate.

For example, the signal line plug extends along the first direction D1, and the bottom surface of the signal line plug is electrically connected in direct contact with the signal line, and the top surface of the signal line plug is electrically connected in direct contact with the connecting bridge. The peripheral lead also extend along the first direction D1, and the bottom surface of the peripheral lead is electrically connected in direct contact with the peripheral circuit, and the top surfaces of the peripheral lead is electrically connected in direct contact with the connecting bridge. The connecting bridge is above the third isolation layer <NUM>, and the projection of the connecting bridge on the top surface of the substrate <NUM> extends from the memory region <NUM> to the peripheral region <NUM>. Disposing the top surface of the peripheral substrate flush with the top surfaces of the signal lines extending in the first direction D1 allows the length of the peripheral leads in the first direction D1 to be less than or equal to the length of the signal line plugs in the first direction D1, so that the coupling capacitance effect between adjacent peripheral leads can be further reduced, and the peripheral leads and the signal line plugs can be simultaneously formed, thereby further simplifying the manufacturing process of the semiconductor device.

In some embodiments, the signal lines include a plurality of first signal lines spaced apart from each other along the first direction D1. In two adjacent ones of the first signal lines along the first direction D1, the length of one of the two first signal lines closer to the substrate <NUM> along the third direction D3 is larger than the length of the other of the two first signal lines along the third direction D3. The third direction D3 is parallel to the top surface of the substrate <NUM>.

The peripheral circuits include a plurality of first peripheral circuits <NUM> spaced apart from each other along the third direction D3, and the peripheral leads include a plurality of first peripheral leads <NUM> spaced apart from each other along the third direction D3. One ends of the first peripheral leads <NUM> are electrically connected to the first peripheral circuits <NUM> in one-to-one correspondence, and the other ends are electrically connected to the first signal lines in one-to-one correspondence.

In some embodiments, the signal lines include a plurality of second signal lines spaced apart from each other along the third direction D3, and top surfaces of the plurality of second signal lines are flush.

The peripheral circuits include a plurality of second peripheral circuits <NUM> spaced apart from each other along the third direction D3, and the peripheral leads include a plurality of second peripheral leads <NUM> spaced apart from each other along the third direction D3. One ends of the second peripheral leads <NUM> are electrically connected to the second peripheral circuits <NUM> in one-to-one correspondence, and the other ends are electrically connected to the second signal lines in one-to-one correspondence.

In some embodiments, the first signal lines are word lines and the second signal lines are bit lines.

Alternatively, the first signal lines are bit lines and the second signal lines are word lines.

It is taken as an example for description that, the first signal lines are word lines, the second signal lines are bit lines, the connecting bridges include first connecting bridges and second connecting bridges, and the signal line plugs include first signal line plugs and second signal line plugs. As shown in <FIG> and <FIG>, the memory array includes a plurality of the memory cells arranged in an array along the first direction D1 and the third direction D3. Each of the memory cells includes a transistor and a capacitor <NUM> electrically connected to the transistor. The transistor includes a channel region <NUM>, a source region <NUM> and a drain region <NUM>, in which the source region <NUM> and the drain region <NUM> are respectively arranged on opposite sides of the channel region <NUM> along the second direction D2, and the drain region <NUM> is electrically connected to the capacitor <NUM>. Interlayer isolation layers <NUM> are also provided between adjacent memory cells for electrically isolating any adjacent memory cells. A plurality of word lines <NUM> are spaced apart from each other along the first direction D1, and each of the word lines <NUM> extends along the third direction D3 and continuously covers a plurality of the channel regions spaced apart from each other along the third direction D3, thereby forming a horizontal word line structure. In an embodiment, a gate dielectric layer is also provided between the word line <NUM> and the channel region. The end of each word line <NUM> extending out of the memory array is for electrically connecting in contact with a corresponding first signal line plug <NUM>. The ends of a plurality of the word lines <NUM> extending out of the memory array form a stepped structure so that the plurality of the word lines <NUM> are electrically connected in contact with the plurality of the first signal line plugs <NUM> in one-to-one correspondence. The stepped structure refers to, of two adjacent ones of the word lines <NUM> along the first direction D1, the length of one of the two word lines <NUM> closer to the substrate <NUM> along the third direction D3 is greater than the length of the other of the two word lines <NUM> along the third direction D3. For example, one word line <NUM> closer the substrate <NUM> along the third direction D3 has a length greater than that of another word line <NUM> along the third direction D3. The bottom surface of each first signal line plug <NUM> is electrically connected in contact with each word line <NUM>, and the top surface of each first signal line plug is electrically connected in contact with each first connecting bridge <NUM>. The bottom surface of each first peripheral lead <NUM> is electrically connected in contact with each first peripheral circuit <NUM>, and the top surface of each first peripheral lead is electrically connected in contact with each first connecting bridge <NUM>.

A plurality of bit lines <NUM> are spaced apart from each other along the third direction D3, and each of the bit lines <NUM> extends along the first direction D1 and is continuously connected in contact with a plurality of the source regions <NUM> spaced apart from each other along the first direction D1. The top surfaces of the plurality of bit lines <NUM> are flush, which helps to simplify not only the forming process of the bit lines, but also the forming process of the second signal line plugs <NUM>. The bottom surface of each second signal line plug <NUM> is electrically connected in contact with each bit line <NUM>, and the top surface of each second signal line plug is electrically connected in contact with each second connecting bridge <NUM>. The bottom surface of each second peripheral lead <NUM> is electrically connected in contact with each second peripheral circuit <NUM>, and the top surface of each second peripheral lead is electrically connected in contact with each second connecting bridge <NUM>. Herein, the length of the second peripheral leads <NUM> and the length of the first peripheral leads <NUM> in the first direction D1 can be the same, so that the second peripheral leads <NUM> and the first peripheral leads <NUM> can be formed synchronously, thereby further simplifying the forming process of the semiconductor device.

The above is only an example for description and in other embodiments, the first signal lines may be bit lines and the second signal lines may be word lines.

In some embodiments, the substrate <NUM> includes a plurality of the memory regions <NUM> at outer sides of the peripheral region <NUM>, and the memory structure is located above each of the memory regions <NUM>.

The peripheral region <NUM> includes a plurality of the peripheral structures and a second isolation layer <NUM> located between two adjacent ones of the peripheral structures. The plurality of peripheral structures and the plurality of memory structures are electrically connected in one-to-one correspondence.

For example, the substrate <NUM> includes the peripheral region <NUM> and two memory regions <NUM> arranged on opposite sides of the peripheral region <NUM> along the second direction D2, that is, the two memory regions <NUM> share one peripheral region <NUM>, thereby improving the utilization of the surface space of the substrate <NUM> and further improving the integration of the semiconductor device. Each of the memory regions <NUM> is provided with one memory structure, and the peripheral region <NUM> is provided with two peripheral structures that are electrically connected to the two memory structures in one-to-one correspondence, and are electrically isolated by the second isolation layer <NUM> in order to avoid signal crosstalk. In an embodiment, the material of the second isolation layer <NUM> may be a nitride material (e.g. silicon nitride).

In an embodiment, the memory structure further includes support layers <NUM>. The support layers <NUM> extend along the first direction D1 and penetrate the memory array along the first direction D1 for supporting the memory array to improve the structural stability of the memory array.

The specific embodiments further provide a method for forming a semiconductor device. <FIG> is a flow chat of a method for forming a semiconductor device of a specific embodiment of the disclosure; and <FIG> are structural cross-sectional diagrams showing main processes for forming a semiconductor device in specific embodiments of the disclosure. The structure of the semiconductor device formed in the specific embodiments can be seen in <FIG>, <FIG> and <FIG>. As shown in <FIG>, the method for forming a semiconductor device includes the following operations.

In S31, a substrate <NUM> including a memory region <NUM> and a peripheral region <NUM> located at an outer side of the memory region <NUM> is provided, as shown in <FIG>.

Specifically, the substrate <NUM> may be, but is not limited to a silicon substrate and the present embodiment is described by taking a silicon substrate as the substrate <NUM> as an example. In other embodiments, the substrate <NUM> may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. In an embodiment, a plurality of the memory regions <NUM> and peripheral regions <NUM> located between two adjacent ones of the memory regions <NUM> may be defined on the substrate <NUM>.

In S32, a memory structure is formed in the memory region <NUM> and a peripheral structure is formed in the peripheral region <NUM>, in which the memory structure includes a memory array and a plurality of signal lines, the memory array at least includes a plurality of memory cells spaced apart from each other along a first direction D1, and the signal lines are electrically connected with the memory cells, where the first direction D1 is perpendicular to a top surface of the substrate <NUM>; the peripheral structure includes peripheral stacked layers <NUM>, peripheral circuits located above the peripheral stacked layers <NUM>, and a plurality of peripheral leads located above the peripheral circuits, and one end of each of the peripheral leads is electrically connected with one of the peripheral circuits, and the other end is electrically connected with one of the signal lines.

In some embodiments, the specific operations for forming the memory structure in the memory region <NUM> and forming the peripheral structure in the peripheral region <NUM> includes the following operations.

Initial stacked layers <NUM> covering the memory region <NUM> and the peripheral region <NUM> are formed on a surface of the substrate <NUM>, and the initial stacked layers <NUM> includes first semiconductor layers <NUM> and second semiconductor layers <NUM> alternately stacked along the first direction D1.

All the second semiconductor layers <NUM> in the memory region <NUM> are removed, and the topmost second semiconductor layer <NUM> in the peripheral region <NUM> is removed, as such, the first semiconductor layers <NUM> in the memory region <NUM> is exposed, and a first trench <NUM> is formed in the peripheral region <NUM>, and the initial stacked layers <NUM> retained below the first trench <NUM> serve as the peripheral stacked layers, as shown in <FIG>.

The memory cells and the signal lines are formed in the memory region <NUM>, and the peripheral circuits are formed above the peripheral stacked layers in the peripheral region <NUM>.

Interlayer isolation layers <NUM> are formed between the memory cells and a first isolation layer <NUM> is formed in the first trench as shown in <FIG>.

The signal lines and the peripheral circuits are electrically connected.

In some embodiments, the specific operations for removing all the second semiconductor layers <NUM> in the memory region <NUM>, and removing the topmost second semiconductor layer <NUM> in the peripheral region <NUM> includes the following operations.

A third isolation layer <NUM> is formed in the initial stacked layers <NUM> between the memory region <NUM> and the peripheral region <NUM>, and a support layer <NUM> is formed in the initial stacked layers <NUM> in the memory region <NUM>, in which the third isolation layer <NUM> and the support layer <NUM> penetrate the initial stacked layers <NUM> along the first direction D1, as shown in <FIG>.

The second semiconductor layers <NUM> in the initial stacked layers <NUM> of the memory region <NUM> are removed to expose the first semiconductor layers <NUM> in the memory region <NUM>.

The topmost second semiconductor layer <NUM> of the initial stacked layers <NUM> is removed in the peripheral region <NUM> to form the first trench <NUM> in the peripheral region <NUM>. The initial stacked layers <NUM> retained below the first trench <NUM> serve as the peripheral stacked layers, the first semiconductor layer <NUM> retained above the first trench <NUM> serves as the peripheral substrate <NUM>.

In some embodiments, the substrate <NUM> includes a plurality of the memory regions <NUM> at outer sides of the peripheral region <NUM>. The specific operations for forming the memory cells and the signal lines in the memory regions <NUM> and forming the peripheral circuits above the peripheral stacked layers in the peripheral region further includes the following operations.

The memory cells and the signal lines are formed in each memory region <NUM>.

A plurality of peripheral circuits are formed above the peripheral stacked layers of the peripheral region and a second isolation layer <NUM> is formed between adjacent peripheral circuits.

Hereinafter, it is taken as an example for description that the substrate <NUM> includes a peripheral region <NUM> and two memory regions <NUM> arranged on opposite sides of the peripheral region <NUM> in the second direction D2. For example, the first semiconductors <NUM> and the second semiconductor layers <NUM> alternately stacked along the first direction D1 may be formed on the surface of the substrate <NUM> by epitaxial growth, to form the initial stacked layers <NUM> having a superlattice stacked structure, and the initial stacked layers <NUM> continuously cover the memory regions <NUM> and the peripheral region <NUM>. The specific number of layers of the first semiconductor layers and the second semiconductor layers alternately stacked in the initial stacked layers <NUM> can be selected by those skilled in the art according to the actual requirements. The greater the number of layers of the first semiconductor layers and the second semiconductor layers alternately stacked, the greater the storage capacity of the formed semiconductor device. In an embodiment, the material of the first semiconductor layers <NUM> is Si, and the material of the second semiconductor layers <NUM> is SiGe.

Third isolation holes located between each of the memory regions <NUM> and the peripheral region <NUM> and support holes located in each of the memory regions <NUM> may be formed in the initial stacked layers <NUM> by photolithography. Next, an insulating dielectric material such as a nitride (e.g. silicon nitride) is filled in the third isolation holes and the support holes, such that the third isolation layers <NUM> penetrating the initial stacked layers <NUM> in the first direction D1 are formed in the third isolation layers, and the support layers <NUM> penetrating the initial stacked layers <NUM> in the first direction D1 are formed in the support holes. The third isolation layers <NUM> are used to isolate each of the memory regions <NUM> from the peripheral region <NUM>. On one hand, the support layers <NUM> are used for supporting the initial stacked layers <NUM> to avoid tilting or collapse in the subsequent process of removing the second semiconductor layers <NUM>. On the other hand, the support layers <NUM> are used for defining a transistor region, a capacitor region and a signal line region (e.g. a bit line region) in the initial stacked layers <NUM> in each memory region <NUM>. Subsequently, the second semiconductor layers <NUM> in the initial stacked layers <NUM> of the memory regions <NUM> may be removed by wet etching, and a first gap between every two adjacent first semiconductor layers <NUM> is formed in each memory region <NUM>. Next, an insulating dielectric material, such as an oxide (e.g., silicon dioxide) is deposited in the first gaps by atomic layer deposition to form the interlayer isolation layers <NUM>, as shown in <FIG>.

Subsequently, after forming a first barrier layer <NUM> covering the top surface of the initial stacked layers <NUM> in each memory region <NUM>, the topmost second semiconductor layer <NUM> of the initial stacked layers <NUM> in the peripheral region <NUM> is removed, and thus the first trench <NUM> is formed in the peripheral region <NUM>. The first trench <NUM> divides the initial stacked layers <NUM> in the peripheral region <NUM> into a top first semiconductor layer <NUM> above the first trench <NUM> and initial peripheral stacked layers below the first trench <NUM>, as shown in <FIG>. Next, an insulating dielectric material, such as an oxide (e.g. silicon dioxide) is filled in the first trench <NUM> to form the initial first isolation layer. The initial stacked layers <NUM> in the peripheral region <NUM> are etched to form a second isolation hole exposing the substrate <NUM>. An insulating dielectric material, such as a nitride (e.g. silicon nitride) is filled in the second isolation hole to form a second isolation layer <NUM>. The second isolation layer <NUM> divides the initial stacked layers <NUM> into two groups of peripheral stacked layers, divides the initial first isolation layer into two first isolation layers <NUM>, and divides the top first semiconductor layer <NUM> into two peripheral substrates <NUM> at the same time, as shown in <FIG>. Then, the first barrier layers <NUM> are removed.

In some embodiments, the peripheral region <NUM> is arranged at an outer side of the memory region <NUM> along the second direction D2 parallel to the top surface of the substrate <NUM>. The signal lines include first signal lines. The specific operations for forming the memory cells and the signal lines in the memory region <NUM> and forming the peripheral circuits above the peripheral stacked layers in the peripheral region includes the following operations.

Transistors of the memory cells are formed in the memory region <NUM>, and a plurality of the transistors are arranged in an array along the first direction D1 and a third direction D3, where the third direction D3 is parallel to the top surface of the substrate <NUM>, and the third direction D3 intersects with the second direction D2.

A plurality of first signal lines spaced apart from each other along the first direction D1 are formed, each of the first signal lines extends along the third direction D3 and is electrically connected to a plurality the transistors spaced apart from each other along the third direction D3 in one-to-one correspondence, and in two adjacent ones of the first signal lines along the first direction D1, one of the two first signal lines closer to the substrate <NUM> along the third direction D3 has a length larger than that of the other of the two first signal lines along the third direction, where the third direction D3 is parallel to the top surface of the substrate <NUM>.

A plurality of first peripheral circuits <NUM> spaced apart from each other along the third direction D3 are formed in the peripheral substrate <NUM>.

In some embodiments, the signal lines further include second signal lines. The specific operations for forming the memory cells and the signal lines in the memory region <NUM> and forming the peripheral circuits above the peripheral stacked layers in the peripheral region <NUM> further includes the following operations.

A plurality of the second signal lines spaced apart from each other along the third direction D3 are formed, in which the second signal lines extend along the first direction D1 and are electrically connected to a plurality of the transistors spaced apart from each other along the first direction D1 in one-to-one correspondence.

A plurality of second peripheral circuits <NUM> spaced apart from each other along the third direction D3 are formed in the peripheral substrate <NUM>.

In some embodiments, the specific operation for forming a plurality of the second signal lines spaced apart from each other along the third direction d3 includes the following operation.

A plurality of the second signal lines spaced apart from each other along the third direction D3 are formed, in which top surfaces of the second signal lines are flush with a top surface of the peripheral substrate <NUM>.

Hereinafter, it is taken as an example for description that the first signal lines are bit lines and the second signal lines are word lines. For example, a second barrier layer <NUM> covering the peripheral substrate <NUM> is formed, and then doping ions are implanted into the first semiconductor layers <NUM> of the transistor region to form a plurality of the transistors which are arranged in an array along the first direction D1 and the third direction D3. Each of the transistors includes a memory channel region <NUM>, and a memory source region <NUM> and a memory drain region <NUM> arranged on opposite sides of the memory channel region <NUM> along the second direction D2. Thereafter, a word line material (for example, a conductive material such as tungsten or TiN) is deposited on the transistor region to form a plurality of word lines <NUM> spaced apart from each other along the first direction D1. Each word lines <NUM> extends along the third direction D3 and continuously covers a plurality of the memory channel regions <NUM> that are spaced apart from each other along the third direction D3. The end of each word line <NUM> extends out of the memory array. Ends of the plurality of the word lines <NUM> extending out of the memory array are etched to form a stepped structure. The stepped structure refers to, in two adjacent ones of the word lines <NUM> along the first direction D1, the length of one of the two word lines <NUM> closer to the substrate <NUM> along the third direction D3 is greater than the length of the other of the two word lines <NUM> along the third direction D3. Next, the first semiconductor layers <NUM> remaining in the bit line region are removed to form bit line through holes exposing the substrate <NUM>. A conductive material such as tungsten is filled in the bit line through holes to form the bit lines <NUM>, as shown in <FIG>. The plurality of bit lines <NUM> are spaced apart from each other along the third direction D3, and each of the bit lines <NUM> is continuously connected in contact with the plurality of the memory source regions <NUM> spaced apart from each other along the first direction D1.

After the transistors, the bit lines <NUM>, and the word lines <NUM> are formed, the second barrier layer <NUM> is removed, and the peripheral substrate <NUM> is treated, such as doped or the like, and elements such as peripheral electrodes <NUM> are formed on the peripheral substrate <NUM>, to form the first peripheral circuits <NUM> and the second peripheral circuits <NUM>, as shown in <FIG> and <FIG>.

In some embodiments, before connecting the signal lines and the peripheral circuits electrically, the following operation is further included.

Capacitors <NUM> of the memory cells are formed in the memory region <NUM>, and the capacitors are electrically connected with the transistors.

Specifically, after the peripheral circuits are formed, a third barrier layer <NUM> is formed, covering the top surfaces of the peripheral circuits and the top surface of the formed memory structure, as shown in <FIG>. Thereafter, a capacitor <NUM> connected with the memory drain region <NUM> of each transistor is formed in the memory region <NUM>. After the third barrier layer <NUM> is removed, a structure as shown in <FIG> is obtained. In the specific embodiments, the capacitors <NUM> are formed after the peripheral circuits are formed, so that damage to the capacitors <NUM> caused by the forming process of the peripheral circuits is avoided.

In some embodiments, the specific operations for connecting the signal lines and the peripheral circuits electrically include the following operations.

First signal line plugs <NUM> electrically connected to the first signal lines, first peripheral leads <NUM> electrically connected to the first peripheral circuits <NUM>, second signal line plugs <NUM> electrically connected to the second signal lines, and second peripheral leads <NUM> electrically connected to the second peripheral circuits <NUM> are formed at the same time.

First connecting bridges <NUM> for electrically connecting the first signal line plugs <NUM> and the first peripheral leads <NUM> are formed, and second connecting bridges <NUM> for electrically connecting the second signal line plugs <NUM> and the second peripheral leads <NUM> are simultaneously formed, as shown in <FIG>, <FIG> and <FIG>.

Specifically, the first signal line plugs <NUM>, the first peripheral leads <NUM>, the second signal line plugs <NUM>, and the second peripheral leads <NUM> can be formed synchronously by etching and filling processes. Herein, the materials of the first signal line plugs <NUM>, the first peripheral leads <NUM>, the second signal line plugs <NUM>, and the second peripheral leads <NUM> may all be tungsten. The materials of the first connecting bridges <NUM> and the second connecting bridges <NUM> may both be copper.

Claim 1:
A semiconductor device with three-dimensional structure, comprising:
a substrate (<NUM>) comprising a memory region (<NUM>) and a peripheral region (<NUM>) located at an outer side of the memory region (<NUM>);
a memory structure located above the memory region (<NUM>) and comprising a memory array and a plurality of signal lines (<NUM>, <NUM>), the memory array at least comprising a plurality of memory cells spaced apart from each other along a first direction, and the signal lines (<NUM>, <NUM>) being electrically connected with the memory cells, wherein the first direction is perpendicular to a top surface of the substrate (<NUM>), wherein the signal lines (<NUM>, <NUM>) comprise first signal lines (<NUM>) and second signal lines (<NUM>), first signal line plugs (<NUM>) are electrically connected to the first signal lines (<NUM>), second signal line plugs (<NUM>) are electrically connected to the second signal lines (<NUM>);
a peripheral structure located above the peripheral region (<NUM>) and comprising peripheral stacked layers (<NUM>), peripheral circuits (<NUM>, <NUM>) located above the peripheral stacked layers (<NUM>), and a plurality of peripheral leads (<NUM>, <NUM>) located above the peripheral circuits (<NUM>, <NUM>), one end of one of the peripheral leads (<NUM>, <NUM>) being electrically connected with each of the peripheral circuits (<NUM>, <NUM>), and the other end being electrically connected with one of the signal lines (<NUM>, <NUM>), wherein the peripheral circuits (<NUM>, <NUM>) comprise first peripheral circuits (<NUM>) and second peripheral circuits (<NUM>), peripheral leads (<NUM>, <NUM>) comprise first peripheral leads (<NUM>) and second peripheral leads (<NUM>), first peripheral leads (<NUM>) are electrically connected to the first peripheral circuits (<NUM>), second peripheral leads (<NUM>) are electrically connected to the second peripheral circuits (<NUM>);
characterized by further comprising:
first connecting bridges (<NUM>) electrically connecting the first signal line plugs (<NUM>) and the first peripheral leads (<NUM>), and second connecting bridges (<NUM>) parallel to the first connecting bridges (<NUM>) electrically connecting the second signal line plugs (<NUM>) and the second peripheral leads (<NUM>).