Patent Description:
Memory is one type of integrated circuitry, and is used in electronic systems for storing data. Integrated memory is usually fabricated in one or more arrays of individual memory cells. The memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a "<NUM>" or a "<NUM>". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

An example memory is dynamic random access memory (DRAM). The DRAM unit cells may each comprise a capacitor in combination with a transistor. Charge stored on the capacitors of the DRAM unit cells may correspond to memory bits.

There is a continuing goal to improve architectural layouts of integrated circuit structures in an effort to maintain (or even improve) device performance, while achieving ever higher levels of integration. It is desired to develop improved architectures, and improved devices. It would be desirable for the improved devices to be suitable for utilization in memory and/or in other integrated circuitry. It is further desired to develop methods for fabricating the improved devices and architectures.

<CIT> discloses a method and structure for forming on-chip high quality capacitors with ETSOI transistors.

<CIT> discloses a memory array comprising vertically-alternating tiers of insulative material and memory cells.

<CIT> discloses a memory array comprising vertically alternating tiers of insulative material and memory cells.

<CIT> discloses a multi-die stack package.

<CIT> relates to a semiconductor device which can store data even when power is not supplied in a data storing time and which does not have a limitation on the number of writing operations. The semiconductor device includes a transistor and a capacitor. The transistor includes a first oxide semiconductor layer, a source electrode and a drain electrode which are in contact with the first oxide semiconductor layer, a gate electrode overlapping with the first oxide semiconductor layer, and a gate insulating layer between the first oxide semiconductor layer and the gate electrode. The capacitor includes the source electrode or the drain electrode, a second oxide semiconductor layer in contact with the source electrode or the drain electrode, and a capacitor electrode in contact with the second oxide semiconductor layer.

Some embodiments include integrated devices having capacitors and transistors, with the capacitors being horizontally offset from the transistors. The integrated devices may be vertically stacked one atop another in an integrated assembly. In some embodiments, the integrated devices may be memory cells of a DRAM array. Some embodiments include methods of forming integrated devices which have capacitors horizontally offset from transistors, and some embodiments include methods of forming architectures which comprise vertically-stacked tiers of such integrated devices. Example embodiments are described with reference to <FIG>.

Referring to <FIG>, a device <NUM> is illustrated to comprise a transistor <NUM> and a capacitor <NUM>.

The transistor <NUM> includes a gate <NUM>, and a semiconductor material <NUM> adjacent the gate. The semiconductor material <NUM> includes a channel region <NUM>. The channel region <NUM> is not visible in <FIG>, as it is under a portion of the gate <NUM>; but an approximate location of the channel region is diagrammatically illustrated with a dashed arrow. The semiconductor material <NUM> also includes a first source/drain region <NUM> on one side of the channel region <NUM>, and a second source/drain region <NUM> on an opposing side of the channel region from the first source/drain region <NUM>.

The transistor gate <NUM> comprises conductive material <NUM>. Such conductive material may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

The semiconductor material <NUM> may comprise any suitable composition or combination of compositions; such as, for example, one or more of silicon, germanium, III/V materials (e.g., gallium phosphide), semiconductor oxides, etc. The source/drain regions <NUM> and <NUM> may comprise conductively-doped regions. The channel region <NUM> may be doped to an appropriate level to achieve a desired threshold voltage.

The capacitor <NUM> comprises a first electrode <NUM> and a second electrode <NUM>. The electrodes <NUM> and <NUM> are spaced from one another, and dielectric material would be between the first and second electrodes. The dielectric material is not shown in <FIG> in order to simplify the drawing, but would be similar to the dielectric material <NUM> described below with reference to <FIG>.

The electrodes <NUM> and <NUM> comprise conductive materials <NUM> and <NUM>, respectively. Such conductive materials may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The conductive materials <NUM> and <NUM> may be the same as one another in some embodiments, and may be different from one another in other embodiments.

In some embodiments, the electrodes <NUM> and <NUM> may be respectively referred to as a bottom electrode and a top electrode, a storage node electrode and a plate electrode, a bottom plate and a top plate, etc..

The second source/drain region <NUM> is coupled with the first electrode <NUM> of the capacitor <NUM>; and in the illustrated embodiment is directly against the first electrode <NUM>.

A bitline <NUM> extends through the device <NUM>, and is coupled with the first source/drain region <NUM>. In the illustrated embodiment, the first source/drain region <NUM> is directly against the bitline <NUM>.

The bitline <NUM> comprises conductive material <NUM>. The conductive material <NUM> may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

A wordline <NUM> is coupled with the gate <NUM>. In some embodiments, the device <NUM> may correspond to a memory cell, and may be one of many memory cells of a memory array (for instance, a DRAM array). The memory cell <NUM> may be addressed (i.e., read from/written to) utilizing the wordline <NUM> and the bitline <NUM>.

The device <NUM> may comprise numerous insulative materials which are not shown in the diagram of <FIG> in order to simplify the drawing. For instance, the capacitor dielectric material (i.e., the material <NUM> shown in <FIG>) has already been mentioned. Also, gate dielectric material would be provided between the gate and the channel region <NUM> (example gate dielectric material is shown in <FIG> as material <NUM>). Further, insulative materials would be provided to surround the device <NUM>, and to isolate the bitline <NUM> from the capacitor <NUM>. For instance, <FIG> shows insulative material <NUM> provided between the bitline <NUM> and the capacitor <NUM>, and shows insulative material <NUM> over the transistor <NUM> and the capacitor <NUM>.

The insulative materials <NUM> and <NUM> may comprise any suitable composition(s); and in some embodiments may comprise one or more of silicon dioxide, silicon nitride, high-k oxides (with high-k meaning a dielectric constant greater than that of silicon dioxide), etc. The insulative materials <NUM> and <NUM> may be the same composition as one another in some embodiments, and may be different compositions relative to one another in other embodiments. Further, in some embodiments either or both of the materials <NUM> and <NUM> may comprise two or more different materials, rather than the single homogeneous materials illustrated in <FIG>.

In some embodiments, the bitline <NUM> may have a different configuration than shown in <FIG>. Specifically, <FIG> shows the bitline <NUM> configured to be substantially circular along a horizontal cross-section through the bitline. In other embodiments, the bitline may be polygonal, square, rectangular, elliptical, etc. <FIG> shows a configuration in which the bitline <NUM> is crescent-shaped along a horizontal cross-section through the bitline. The crescent-shaped bitline is along an insulative material <NUM>. Such insulative material may comprise, for example, any of the compositions discussed above with reference to <FIG> for the insulative materials <NUM> and <NUM>. In some embodiments, the insulative material <NUM> may be the same as one or both of the insulative materials <NUM> and <NUM>.

The gate <NUM> of <FIG> and <FIG> is illustrated to be in a configuration which brackets the channel region <NUM> within semiconductor material <NUM>. In other embodiments or examples, the gate <NUM> may have a different configuration. For instance, <FIG> shows a configuration in which the gate <NUM> is primarily over the channel region <NUM>, and <FIG> shows a configuration in which the gate <NUM> is primarily under the channel region <NUM>. Accordingly, <FIG> and <FIG> show configurations according to some embodiments, in which the gate <NUM> is along one side of the channel region <NUM>, rather than being along two opposing sides of the channel region (i.e., rather than bracketing the channel region).

The devices <NUM> of <FIG> have the capacitor <NUM> horizontally-offset relative to the transistor <NUM>. Also, all of the devices are substantially circular along horizontal cross-sections through the devices (with the term "substantially circular" meaning circular to within reasonable tolerances of fabrication and measurement). The devices may have other shapes in other embodiments, as discussed in more detail below with reference to <FIG>.

The devices <NUM> of <FIG> may be utilized as memory cells within memory arrays. For instance, <FIG>, shows an example memory array <NUM> comprising memory cells 10a-f having the configuration of the device <NUM> of <FIG>. Each memory cell comprises a capacitor (e.g., the capacitors 14a-c visible in <FIG>) coupled with an associated transistor (e.g., the transistors 12a-12c visible in <FIG>). The capacitors are vertically-stacked one atop another along levels <NUM>, <NUM> and <NUM>. The level <NUM> comprises the memory cells 10a and 10d; the level <NUM> comprises the memory cells 10b and 10e; and the level <NUM> comprises the memory cells 10c and 10f. Insulative materials are not shown in <FIG> in order to simplify the drawing, but it is to be understood that insulative materials analogous those described above with reference to <FIG> and <FIG> (e.g., capacitor dielectric material, gate dielectric material, etc.) would be provided.

The capacitors comprise the first electrodes (for instance, the electrodes 22a, 22b and 22c) and the second electrodes (for instance, the electrodes 24a, 24b and 24c). In the illustrated embodiment, the second electrodes along each vertical stack are comprised by a single common plate. Accordingly, the electrodes 24a, 24b and 24c are within a common plate labeled 24a/24b/24c; and the electrodes 24d, 24e and 24f are within a common plate labeled 24d/24e/24f. The common plates 24a/24b/24c and 24d/24e/24f may be coupled with one another in some embodiments, and may be held at any suitable voltage (i.e., ground, Vcc/<NUM>, etc.).

Wordlines (e.g., access lines, etc.) 36a-f extend horizontally, and are coupled with transistor gates of the memory cells 10a-f (the transistor gates are not labeled in <FIG>, but would be analogous to the transistor gate <NUM> of <FIG>).

Digit lines (e.g. bitlines, senses lines, etc.) extend vertically and are coupled with source/drain regions of the memory cells 10a-f (the source/drain regions are not labeled in <FIG>, but the digit lines would be coupled to source/drain regions analogous to the source/drain region <NUM> of <FIG>).

Each memory cell 10a-f may be uniquely addressed through a combination of one of the digit lines (32a, 32b), and one of the wordlines (36a-f). In some embodiments, the wordlines may be considered to extend along rows of the array of memory cells, and the digit lines may be considered to extend along columns of the array of memory cells.

<FIG> shows a region of the memory array <NUM>, and the memory array may comprise numerous other memory cells besides the illustrated six memory cells 10a-f. The memory array may extend vertically above and below the illustrated region, and may extend laterally to the left and right of the illustrated region, as well as into and out of the page relative to the illustrated region. The memory array may comprise any suitable number of memory cells; and in some embodiments may comprise hundreds, thousands, millions, billions, etc., of memory cells.

The memory cells within each level (e.g., the levels <NUM>, <NUM> and <NUM>) may be substantially identical to one another (with the term "substantially identical" meaning identical to within reasonable tolerances of fabrication and measurement). Further, at least some of the memory cells within one vertical level (e.g., level <NUM>) may be substantially identical to memory cells within another vertical level (e.g., level <NUM>). In some embodiments, all of the memory cells within one vertical level may be substantially identical to all of the memory cells within another vertical level. In some embodiments, all of the memory cells within all of the vertical levels may be substantially identical to one another.

In some embodiments, at least some of the memory cells within one vertical level may not be substantially identical to at least some of the memory cells within another vertical level. Such may enable different vertical levels to be tailored for different applications. Differences between the memory cells in one vertical level relative to the memory cells in another vertical level may provide different performance characteristics amongst transistors of the memory cells (such as, for example, differences in one or more of effective gate width, effective gate length, threshold voltage, on-current, off-current, etc.) and/or different performance characteristics amongst capacitors of the memory cells (such as, for example, differences in capacitance).

In some embodiments, differences in performance characteristics amongst transistors of the memory cells may be achieved by providing different semiconductor material within one level as compared to another level (e.g., the semiconductor material 18a may be different relative to the semiconductor material 18b); with the differences between the semiconductor materials being differences in composition, differences in thickness, and/or differences in any other suitable physical characteristics. Alternatively, or additionally, differences in performance characteristics between one level and another may be achieved by providing different dopants and/or dopant concentrations within the semiconductor material of one level as compared to the semiconductor material of another level (e.g., by providing different dopant and/or dopant concentrations within the semiconductor material 18a as compared to the semiconductor material 18b). Differences in performance characteristics amongst capacitors of different levels may be achieved by, for example, forming the electrodes to be of different shapes amongst the capacitors, utilizing different materials for capacitor dielectric amongst the capacitors and/or by utilizing different thicknesses of capacitor dielectric amongst the capacitors.

<FIG> shows another view of a region of the memory array <NUM>, and shows a pair of adjacent rows <NUM> and <NUM> along the level <NUM>. Insulative materials are not shown in <FIG> in order to simplify the drawing, but it is to be understood that insulative materials analogous those described above with reference to <FIG> and <FIG> (e.g., capacitor dielectric material, gate dielectric material, etc.) would be provided.

The row <NUM> comprises memory cells 10a, <NUM> and <NUM>; and the row <NUM> comprises memory cells 10d, 10i, 10j and <NUM>. The embodiment of <FIG> illustrates one example arrangement of digit lines (32a-f), and wordlines (36a and 36d) relative to the memory cells. Other arrangements may be utilized in other embodiments.

Although the memory cells (i.e., devices) of <FIG> are illustrated to be substantially circular along horizontal cross-sections through the memory cells, it is to be understood that in other embodiments the memory cells may have other configurations. For instance, <FIG> shows a top view of a memory cell <NUM> in a configuration in which the memory cell has a polygonal shape along a horizontal cross-section through the memory cell. In the illustrated embodiment, the memory cell is substantially square along the horizontal cross-section through the memory cell. In other embodiments, the memory cell may have any other suitable shape.

Insulative materials are not shown in <FIG> in order to simplify the drawing, but it is to be understood that insulative materials analogous those described above with reference to <FIG> and <FIG> (e.g., capacitor dielectric material, gate dielectric material, etc.) would be provided.

The devices <NUM> of <FIG> may be fabricated with any suitable processing. In some embodiments, the devices are fabricated by providing holes through a stack of materials. The transistors are formed along a side of the holes, and the capacitors are formed along other sides of the holes. <FIG> shows a top view of a construction <NUM> illustrating example locations <NUM> for holes <NUM> (only some which are labeled) utilized during fabrication devices. The holes <NUM> are lined with a material <NUM>, which is described in more detail below with reference to <FIG>. <FIG> also shows locations <NUM> where slits will be formed for fabrication of the transistor gates and wordlines, and shows locations <NUM> where slits will be formed for fabrication of the capacitors. The construction <NUM> of <FIG> is provided to provide the reader with an overview of an example method for fabricating an array of devices (e.g., the example devices <NUM> of <FIG>) in accordance with an example embodiment. In other embodiments, the devices may be fabricated utilizing other constructions.

An example method for fabricating devices analogous to the device <NUM> of <FIG> is described with reference to <FIG> and <FIG>. The views of <FIG> are along the cross-sections Z-Z of <FIG>, respectively; and the views of <FIG> are along the lines X-X of <FIG>, respectively. It is to be understood that the example method of <FIG> and <FIG> may be modified to fabricate any of the devices of <FIG>, or analogous devices.

Referring to <FIG> and <FIG>, an assembly <NUM> comprises a stack <NUM> of first levels <NUM> and second levels <NUM>. The levels <NUM> and <NUM> alternate with one another along a vertical direction.

The first levels <NUM> may comprise insulative material <NUM>, and may be referred to as insulative levels. The insulative material <NUM> may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon nitride. The insulative material <NUM> of first levels <NUM> may be the same as that described above with reference to <FIG>.

The second levels <NUM> comprise sacrificial material <NUM>. The sacrificial material <NUM> is a material selectively removable relative to the insulative material <NUM>. In some embodiments, the sacrificial material <NUM> may comprise, consist essentially of, or consist of silicon dioxide. For instance, the sacrificial material <NUM> may comprise silicon dioxide which is effectively not doped with boron, phosphorus, or other dopants. Such sacrificial material may be referred to as a non-doped silicate glass (NSG). It may be difficult to have absolutely no dopant within silicate glass, and thus the NSG is referred to as being "effectively not doped". In some embodiments, the dopant level of the NSG may be less than or equal to about <NUM><NUM> atoms/cm<NUM>.

The second levels <NUM> may be referred to as device levels, since integrated devices are eventually formed within the second levels <NUM>.

An insulative panel <NUM> extends through the stack <NUM>. The insulative panel <NUM> comprises an insulative material <NUM>. The material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise a same composition as the insulative material <NUM>. For instance, the materials <NUM> and <NUM> may both comprise, consist essentially of, or consist of silicon nitride in some embodiments. The panel <NUM> may be utilized to define edges of capacitors at processing stages described below with reference to <FIG> and <FIG>. In some embodiments, such edges may be defined without utilization of the panel <NUM>; and accordingly the panel <NUM> may be omitted.

The stack <NUM> is supported by a base <NUM>. The base <NUM> may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base <NUM> may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base <NUM> may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc..

A gap is provided between the stack <NUM> and the base <NUM> to indicate that there may be other materials, components, etc., provided between the stack <NUM> and the base <NUM> in some embodiments. Alternatively, the stack <NUM> may be provided directly against an upper surface of the base <NUM>.

Referring to <FIG> and <FIG>, an opening <NUM> is formed through the stack <NUM>. The opening <NUM> may be referred to as a first opening, and may be representative of a plurality of openings formed through the stack <NUM> (a plurality of openings <NUM> is shown in <FIG>, and discussed above). Only a single opening <NUM> is shown in the views of <FIG> and <FIG> in order to simplify the drawings, but it is to be understood that such opening may be one of a large number of substantially identical openings formed through the stack.

Referring to <FIG> and <FIG>, the sacrificial material <NUM> is recessed relative to the insulative material <NUM> to form cavities <NUM>.

Referring to <FIG> and <FIG>, sacrificial materials <NUM> and <NUM> are formed within the cavities <NUM>, and then an insulative liner <NUM> is formed along a peripheral boundary of the opening <NUM>. In the illustrated embodiment, a layer of the first material <NUM> is provided between a pair of layers of the second material <NUM> within each of the cavities <NUM>.

The sacrificial materials <NUM> and <NUM> may comprise any suitable compositions or combinations of compositions. It can be desired that the second sacrificial material <NUM> be selectively removable relative to the first sacrificial material <NUM>. In some embodiments, the sacrificial material <NUM> may comprise, consist essentially of, or consist of NSG, and may be the same as the sacrificial material <NUM>. The sacrificial material <NUM> may comprise a doped silicate glass; and in some embodiments may comprise, consist essentially of, or consist of phosphosilicate glass. The doped silicate glass comprises a higher concentration of dopant (e.g., phosphorus) than the NSG, and in some embodiments may comprise a dopant concentration of at least about <NUM><NUM> atoms/cm<NUM>.

The liner <NUM> comprises an insulative material <NUM>. The material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

Referring to <FIG>, construction <NUM> is shown at a processing stage subsequent to that of <FIG>. A second opening <NUM> is formed overlapping a region of the first opening <NUM>, and the second opening <NUM> is filled with a digit line template <NUM>. The digit line template <NUM> extends vertically through the stack <NUM>. In the illustrated embodiment, the digit line template comprises two materials <NUM> and <NUM>. The material <NUM> may comprise any of the insulative compositions described above with reference to <FIG>. The material <NUM> is a sacrificial material, and in some embodiments may comprise, consist essentially of, or consist of phosphosilicate glass. The illustrated digit line template <NUM> comprising the two materials <NUM> and <NUM> will ultimately form a digit line <NUM> having the configuration shown in <FIG> as being crescent-shaped along a horizontal cross-section. In other embodiments, the digit line template <NUM> may comprise only the sacrificial material <NUM>, and may be utilized to form a digit line <NUM> having the configuration shown in <FIG> as being circular shaped along a horizontal cross-section. Alternatively, the sacrificial material <NUM> may be in any other suitable shape for forming a desired digit line configuration.

Referring to <FIG> and <FIG>, a slit <NUM> is formed along a first side <NUM> of the opening <NUM>. The slit <NUM> penetrates through the materials <NUM>, <NUM> and <NUM>.

Referring to <FIG> and <FIG>, the sacrificial material <NUM> is removed from along the slit <NUM> to form horizontally-extending voids <NUM>. Such removal may be accomplished by passing appropriate etchant into the slit <NUM>, and utilizing a timed etch to remove a desired amount of the sacrificial material <NUM>. The voids <NUM> may be formed to extend about halfway around opening <NUM>. Such is diagrammatically illustrated in the top view of <FIG> utilizing a dashed line <NUM> to illustrate approximate lateral boundaries (i.e., edges) of the voids <NUM> within the stack <NUM>. The voids <NUM> will be along the left side (the first side <NUM>) of the opening <NUM>, and remaining portions of the sacrificial material <NUM> will be along the right side of the opening <NUM>. Such right side of the opening may be referred to as a second side <NUM>.

In some embodiments, the sacrificial material <NUM> of the digit line template <NUM> may comprise a same composition as the sacrificial material <NUM> (e.g., both may comprise phosphosilicate glass). Accordingly, the sacrificial material <NUM> of the digit line template <NUM> may be removed simultaneously with the removal of the sacrificial material <NUM> to leave a void <NUM>.

Referring to <FIG> and <FIG>, semiconductor material <NUM> is provided within the horizontally-extending voids <NUM> (<FIG>), and such semiconductor material replaces the sacrificial material <NUM> which had been removed to form such voids. The semiconductor material <NUM> may abut the sacrificial material <NUM> along the edges of the previous voids <NUM> (with such edges being diagrammatically illustrated as being approximately along a location of the dashed line <NUM> of <FIG> shows a region along the edge within one of the levels <NUM> of stack <NUM>, and shows the semiconductor material <NUM> directly against the sacrificial material <NUM>.

The void <NUM> (<FIG>) may be filled with conductive material <NUM> to form the digit line <NUM>. In some embodiments, the conductive material may comprise conductively-doped silicon and/or metal. A region of the semiconductor material <NUM> may be directly against the conductive material <NUM>. <FIG> shows a region within one of the levels <NUM> of stack <NUM> where the semiconductor material <NUM> contacts the conductive material <NUM>.

In some embodiments, construction <NUM> may be heated or otherwise operably processed to cause out-diffusion of phosphorus from phosphosilicate glass of sacrificial material <NUM> into the semiconductor material <NUM> to form the first source/drain region <NUM>; and to cause out-diffusion from conductively-doped semiconductor material of the digit line <NUM> into the semiconductor material <NUM> to form the second source/drain region <NUM>.

Although the semiconductor material <NUM> is shown to be the same in all of the vertically-stacked levels <NUM>, in other embodiments the semiconductor material within one of the vertically-stacked levels <NUM> may be different than that within another of the vertically-stacked levels <NUM>. Such may enable fabrication of vertically-stacked transistor devices having different performance characteristics relative to one another; with the vertically-stacked transistor devices being shown in <FIG> as devices 12a and 12b.

Referring to <FIG> and <FIG>, the sacrificial material <NUM> is removed from along the first side <NUM> of the opening <NUM>, together with a portion of the semiconductor material <NUM>, to leave cavities <NUM>. Such removal may be accomplished by flowing one or more suitable etchants into the slit <NUM>.

Referring to <FIG> and <FIG>, gate dielectric material <NUM> is deposited within the voids <NUM>. The gate dielectric material <NUM> may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

Referring to <FIG> and <FIG>, gate material <NUM> and wordline material <NUM> are formed within the voids <NUM> (<FIG>). The gate material <NUM> and wordline material <NUM> may comprise any suitable compositions, and may be the same as one another or different from one another. In some embodiments, the gate material <NUM> may comprise, consist essentially of, or consist of tungsten; and the wordline material <NUM> may comprise a conductive material to which the tungsten may be selectively etched. For instance, in some embodiments the wordline material <NUM> may comprise, consist essentially of, or consist of titanium nitride.

The gate material <NUM> forms transistor gates <NUM>.

The gate dielectric material <NUM>, semiconductor material <NUM> and gate material <NUM> together form transistor devices 12a and 12b along the first side <NUM> of the opening <NUM>. The semiconductor material <NUM> comprises the channel regions <NUM> extending along the gates <NUM>, and also comprises the source/drain regions <NUM> and <NUM> (shown in <FIG> and <FIG>, but not visible in <FIG> and <FIG>).

Referring to <FIG> and <FIG>, insulative material <NUM> and conductive material <NUM> are formed within the slit <NUM> (<FIG> and <FIG>). The insulative material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride, etc. The insulative material <NUM> may be a same composition as the insulative material <NUM> in some embodiments.

The conductive material <NUM> may comprise any suitable composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The conductive material <NUM> may form wordlines 36a and 36b extending in and out of the page relative to the cross-section of <FIG>. In some embodiments, the conductive material <NUM> may be a same composition as the conductive material <NUM>, and in other embodiments the conductive materials <NUM> and <NUM> may comprise different compositions relative to one another.

A slit <NUM> is formed along the second side <NUM> of the opening <NUM>. The slit <NUM> extends through the first and second levels <NUM> and <NUM>, and in the illustrated embodiment is formed along a side of the panel <NUM>.

Referring to <FIG> and <FIG>, materials <NUM> and <NUM> are removed from along the right side <NUM> of opening <NUM> to form voids <NUM>. In the illustrated embodiment, the material <NUM> is thinned to leave liners <NUM> of the material <NUM> along upper and lower regions of the voids <NUM>.

Referring to <FIG> and <FIG>, the first electrode material <NUM> is formed within the voids <NUM> and patterned into the first electrodes 22a and 22b. Sacrificial material <NUM> is provided within the voids <NUM> and along the electrode material <NUM> to assist in the patterning of the electrode material <NUM> into the configuration of the first electrodes 22a and 22b. The sacrificial material <NUM> may comprise any suitable composition(s), and in some embodiments may comprise an oxide formed at sufficiently low temperature such that components associated with circuitry of the assembly <NUM> are not degraded.

The voids <NUM> extend about halfway around the opening <NUM>, and the dashed line <NUM> is provided to show approximate edges of the voids <NUM>. <FIG> shows a region along one of the levels <NUM>, and shows the electrode 22a directly contacting semiconductor material <NUM> of the transistor 12a. The region of the semiconductor material <NUM> which contacts the electrode 22a comprises the first source/drain region <NUM>.

Referring to <FIG> and <FIG>, the sacrificial material <NUM> (<FIG>) is removed. Subsequently, capacitor dielectric material <NUM> is formed along the electrodes 22a and 22b, and then the electrode material <NUM> is formed along the capacitor dielectric material <NUM>.

The capacitor dielectric material <NUM> may comprise any suitable composition(s); such as, for example, one or more of silicon dioxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, other high-k materials (with high-k meaning a dielectric constant greater than that of silicon dioxide), etc..

The electrode material <NUM> forms second electrodes 24a and 24b. In the illustrated embodiment, the second electrodes 24a and 24b are electrically coupled to one another in that the conductive material <NUM> forms a common conductive plate extending across both of the capacitors.

The electrodes 22a and 24a, together with the dielectric material <NUM> therebetween, form the capacitor 14a; and the electrodes 22b and 24b, together with the dielectric material <NUM> therebetween, form the capacitor 14b.

The transistor 12a and the capacitor 14a together form a device 10a along one of the device levels <NUM>, and the transistor 12b and the capacitor 14b together form a device 10b along another of the device levels <NUM>. The devices 10a and 10b are vertically offset relative to one another (i.e., are vertically stacked).

In some embodiments, the opening <NUM> may be representative of a plurality of openings, as discussed above. In such embodiments, the devices 10a and 10b may be representative of a plurality of devices that may be formed relative to each of the openings. Such devices may be memory devices, and may form memory arrays; such as, for example, arrays <NUM> of the type described above with reference to <FIG> and <FIG>. Each of the memory devices within the memory arrays may be uniquely addressed through a combination of a wordline and a digit line, as discussed above relative to the memory arrays <NUM> of <FIG> and <FIG>.

In the embodiment of <FIG>, each device (for instance, device 10a) comprises a transistor (e.g., transistor 12a) coupled with an associated capacitor (e.g., capacitor 14a). The capacitor is horizontally offset from the transistor; and both the transistor and the associated capacitor are within a single device level <NUM>. The devices may be within a memory array <NUM> of the type described above with reference to <FIG>. Wordlines (e.g., wordlines 36a, 36b) extend along the device levels <NUM> and are coupled with gates of the transistors 12a, 12b; and digit lines (e.g., digit line <NUM>) extend vertically through the device levels are coupled with source/drain regions of the transistors 12a, 12b.

In some embodiments, each of the devices (e.g., devices 10a, 10b) of <FIG> may be considered to be between a first insulative level <NUM> below the device, and a second insulative level <NUM> above the device.

<FIG> shows the insulative level <NUM> above device 10a being labeled as a level 74a, and shows the insulative level <NUM> below device 10a being labeled as level 74b. The level 74a has a bottom surface <NUM>, and the level 74b has a top surface <NUM>. The capacitor of the device 10a (i.e., capacitor 14a) has an uppermost surface <NUM> and a lowermost surface <NUM>; and the transistor of the device 10a (i.e., transistor 12a) has an uppermost surface <NUM> and a lowermost surface <NUM>. The uppermost surfaces <NUM> and <NUM> of the transistor 12a and the capacitor 14a are at about a same elevational level as one another beneath the bottom surface <NUM> of upper insulative level 74a; and the lowermost surfaces <NUM> and <NUM> of the transistor 12a and the capacitor 14a are at about a same elevational level as one another above the upper surface <NUM> of the lower insulative level 74b.

In some embodiments, the capacitor 14a may have a lowermost surface <NUM> which is at least as far below the lowermost surface <NUM> of the insulative level 74a as the lowermost surface <NUM> of the transistor 12a, and may have an uppermost surface <NUM> which is at least as far above the uppermost surface <NUM> of the insulative level 74b has the uppermost surface <NUM> of the transistor 12a. If the top surface of the capacitor is no lower than the top surface of the transistor, and if the bottom surface of the capacitor is also no higher than the bottom surface of the transistor, then the transistor 12a and the capacitor 14a may be considered to be in the same planar level as one another (i.e., if the vertical dimension of the transistor is vertically coextensive with the vertical dimension of the capacitor, or vertically sandwiched between the upper and lower surfaces of the capacitor). Alternatively, the transistor 12a and the capacitor 14a may be considered to be in the same planar level as one another if the top surface of the transistor is no lower than the top surface of the capacitor, and the bottom surface of the transistor is no higher than the bottom surface of the transistor (i.e., if the vertical dimension of the capacitor is vertically coextensive with the vertical dimension of the transistor, or vertically sandwiched between the upper and lower surfaces of the transistor).

It is to be understood that the invention described herein may be applicable to numerous circuit designs, including, but not limited to memory arrays. Example circuits may include layouts which may have pillars and/or other structures associated, with, for example, transistors, isolation, gates, capacitors, etc. The example circuits may include multiple layers in one or more tier stacks. Example circuits may be one large connected structure, or may be multiple separated structures (e.g., multiple individual thin substrates).

The structures discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

The terms "dielectric" and "insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "insulative" (or "electrically insulative") in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being "on" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as "extending vertically" to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Claim 1:
An assembly (<NUM>) comprising:
a first insulative level (<NUM>) over a semiconductor base (<NUM>);
a second insulative level (<NUM>) over the first insulative level (<NUM>); and
a device (10a) between the first and second insulative levels (<NUM>); the device (10a) including a transistor (12a) coupled with a capacitor (14a), the transistor (12a) comprising a single continuous structure of semiconductor material (<NUM>) comprising: a channel region (<NUM>), a first source/drain region (<NUM>) on one side of the channel region (<NUM>), and a second source/drain region (<NUM>) on an opposing side of the channel region (<NUM>) from the first source/drain region (<NUM>), the transistor further comprising a gate along the channel region (<NUM>); the assembly further comprising a bitline (<NUM>) extending vertically through the device (10a) and coupled with the first source/drain region (<NUM>) of the transistor; the capacitor (14a) being horizontally offset relative to the transistor (12a); the capacitor (14a) and the transistor (12a) being in a same planar level as one another; the gate (<NUM>) being proximate the channel region (<NUM>), and the gate (<NUM>) being either under the channel region (<NUM>) or over the channel region (<NUM>).