Patent Description:
Further, the invention relates to a method for synchronizing a periodic high frequency power signal and an external reference signal according to claim <NUM>. The device and the method can be used, for example, in radio-frequency power supplies.

Radio-frequency power supplies are commonly found in industry to generate and control plasma inside dedicated plasma processing chambers for etching or for deposition of material from or to a substrate (production of semiconductor memory chips, thin film displays and thin film photovoltaic cells are examples of industrial goods requiring or benefiting from plasma etching and plasma deposition processes). Radio-frequency power supplies are also used to generate lasers, to power medical diagnostic equipment (magnetic resonance imaging for example), and to accelerate particles in research laboratories, to name just a few other applications.

The development of components for digital signal processing is steadily improving. More and more applications of processing signals in the radio frequency (RF) range are moving from the analog to the digital domain.

A frequency synthesizer, as a common signal generator, has been widely applied in many technical areas. Related researches have more and more requirements for the accuracy and stability of the frequency synthesizer, especially in the field of high frequency signal generators. With the development of signal generator technology, digital circuits have entered the field of signal synthesis, and the way of signal synthesis has made rapid progress, many signal synthesis methods have been designed. Modern synthetic signal methods include direct analog frequency synthesis, phase-locked frequency synthesis and direct digital frequency synthesis.

Phase-locked frequency synthesis uses one or more standard frequency sources to generate a large number of harmonics or combined frequencies by mixing and dividing harmonic generators. Then, the phase-locked loop (PLL) is used to lock the frequency of a voltage controlled oscillator (VCO) to a certain harmonic or combination frequency. The required frequency output is indirectly generated by the voltage-controlled oscillator.

A phase locked loop (PLL) is used to lock the output frequency of the voltage controlled oscillator (VCO) with the desired input frequency by constantly comparing the phase of the input frequency with that of the output frequency of the VCO. Further, the PLL is used to generate a signal, modulate or demodulate it. Basically the output frequency of the voltage controlled oscillator is constantly adjusted until it matches with the input frequency. The disadvantage of this method is its slow response to frequency changes.

In high-frequency applications, especially in such applications for carrying out a plasma process, there are further drawbacks regarding the generation of high-frequency signals. The jitter between the output signal and the sampling rate during a high-frequency measurement should be minimised in order to maximise the measurement or signal accuracy.

Usually, an external reference is directly connected to the frequency synthesizer input, for example a Direct Digital Synthesizer (DDS). Then, the frequency of this external reference has to be adapted by frequency dividing. Further, up-conversion of the frequency by using frequency multiplication was limited by the DDS-system's internal multiplication. Additionally, in this modus-operandi it was not possible to add a constant frequency offset. Therefore, the phase locked loop would mainly comprise analogue components. This made it difficult to reconfigure such a system at runtime.

Further, very fast analog-to-digital converters (ADC) are typically used regarding the generation of high-frequency signals. Disadvantageously, such very fast ADCs are very expensive.

<CIT> discloses an RF power-supply for driving a gas-discharge laser having a plurality of power oscillators phase-locked to a common reference oscillator. A digital control signal input to a digital oscillator circuit is controlled by a phase error signal from a phase control circuit.

<CIT> discloses a phase-locked loop (PLL) circuit used in a filter-thickness measuring device, wherein the PLL circuit is used as a frequency measurement circuit. Furthermore, a phase comparator for detecting a phase difference between a first signal and a second signal, a first oscillating circuit for supplying the phase comparator with a reference signal as the first signal, and a direct digital synthesizer (DDS) as a second oscillating circuit for outputting a signal according to an output of the phase comparator are provided.

<CIT> discloses a method for reducing phase noise in transmitted digital signals. Determining a phase error between two clock signals may be carried out by using counter values.

<CIT> discloses a method for setting the free-running frequency of a voltage-controlled oscillator (VCO) using a counter to count the VCO output pulses.

<CIT> discloses a device for generating a plurality of high-frequency signals. The device includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency is supplied.

Further devices or methods regarding frequency synthesizing in phase locked loops are known from <CIT> or <CIT>.

Object of the invention is to provide a device and a method improving frequency controlling by reducing the frequency converting time and ensuring low jitter of the generated high frequency output.

A further object of the present invention is to operate very fast processes by improving the structure and components of the circuitry related to synchronizing signals to save costs.

According to a first aspect of the invention this object is solved by a device for synchronizing a periodic high frequency power signal and an external reference signal, in accordance with the subject-matter of appended independent claim <NUM>, comprising a phase control circuit, a digital oscillator circuit, which is connected to the phase control circuit, and wherein the digital oscillator circuit comprises means for generating the periodic high frequency power signal dependent on the control signal from the phase control circuit , and wherein the phase control circuit is configured to determine a phase difference of the periodic high frequency power signal and the external reference signal.

It is understood that an "external reference signal" in this patent application is any available periodic signal, which has a well-defined and time-invariant frequency and which can therefore be used as a reference for frequency and time.

This allows a faster synchronization regarding a constant phase and /or frequency relationship of internal signals to external clock signals using the inventive device. This device can advantageously be used to synchronize the RF output or CEX (short term for common exciter). Further, the constant reference output of the inventive device can be advantageously used as a reference input to synchronize another unit like a RF generator or RF amplifier.

Further, this synchronization allows improving the digital phase locked loop based on a fixed phase relationship if the reference input and internal signal are configured to work at the same frequency. Alternatively, a fixed frequency ratio of the reference input and the internal signals can be achieved.

Furthermore, this device advantageously allows a faster and broader frequency up-conversion and/or down-conversion of the reference signal frequency.

Further, this allows controlling the frequency or phase of the internally generated signal faster using a frequency tuning word (FTW). A FTW is a parameter, which is proportional to the output of the DDS.

According to the invention the device further comprises an analog-to-digital converter, which is connected to the digital oscillator circuit. The analog-to-digital converter comprises an output, which comprises a digital control signal. The digital oscillator circuit further comprises a signal processing circuit, which is connected to the analog-to-digital converter. The signal processing circuit is configured to regulate a frequency tuning word dependent on a value of the digital control signal, wherein the value of the digital control signal is in relation to a preset reference value range of the digital control signal. The phase control circuit comprises a phase detector comprising means for determining a phase difference of the periodic high frequency power signal and the external reference signal.

This allows reducing the drifting of the output phase of the generated signal faster and more efficiently by driving the output signal of the digital oscillator in the opposite direction so as to reduce the error signal caused by the drifted output phase. Thus, the output phase of the generated high frequency power signal is locked to the phase at the other input signal, which is the reference signal.

Further, using an analog-to digital converter (ADC) allows to match the bandwidth and required signal-to-noise-ratio (SNR) of the signal to be digitized in an advantageous way. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then per the Nyquist-Shannon sampling theorem, a perfect reconstruction of the digitized signal is possible.

According to the invention, the signal processing circuit comprises an activation circuit for activating a frequency tuning word. The activation circuit is activated in case the value of the digital control signal is outside a preset reference value range. The preset reference value range of the digital control signal may be preset between <NUM>,<NUM> to <NUM>,<NUM> of the reference value, preferably between <NUM>,<NUM> to <NUM>,<NUM> of the reference value.

This allows a faster tuning of the frequency tuning word. Further, this allows a more effective fine tuning because the "fine frequency tuning word" is advantageously kept in a safe or working area for driving the digital oscillator.

In a second embodiment according to the first aspect of the invention the device further comprises a loop filter connected between the phase detector and the analog-to-digital converter.

This allows to advantageously determine disturbances; such as changes in the reference frequency or phase. Using a loop filter allows a faster lock time, lock-up time or settling time of the phase locked loop (PLL).

In a third embodiment according to the first aspect of the invention the device further comprises a signal processing circuit, which is connected to the phase control circuit. The signal processing circuit comprises means for determining a phase difference of the periodic high frequency power signal and the external reference signal. The phase control circuit comprises a first counter and a second counter.

In a fourth embodiment according to the first aspect of the invention the means for determining a phase difference are configured to calculate the counting difference of the two counters for determining the phase difference.

In a fifth embodiment according to the first aspect of the invention the means for determining a phase difference are further configured to calculate the counting difference of the two counters at the rising edge of a clock signal to be selected.

In a sixth embodiment according to the first aspect of the invention the digital oscillator circuit comprises a digital-to-analog converter, which is connected to the digital oscillator circuit. The output of the digital-to-analog converter has the periodic high frequency power signal.

This allows to advantageously produce an efficiently modulated output that can be similarly filtered to produce a smoothly varying output signal.

In a seventh embodiment according to the first aspect of the invention the digital oscillator circuit and the digital-to-analog converter are located on a dedicated chip or are separated.

In an eighth embodiment according to the first aspect of the invention the digital oscillator circuit further comprises a direct digital synthesizer circuit.

In a ninth embodiment according to the first aspect of the invention the direct digital synthesizer circuit comprises a phase accumulator and a sine look up table.

In a tenth embodiment according to the first aspect of the invention at least the signal processing circuit is located on a programmable logical circuit.

In an eleventh embodiment according to the first aspect of the invention the programmable logical circuit is a field programmable gate array (FPGA) or a System on Chip (SoC) or an application-specific integrated circuit (ASIC).

In a twelfth embodiment according to the first aspect of the invention the generated high frequency power signal has a frequency equal or smaller than <NUM>, preferably between <NUM> and <NUM>.

In a thirteenth embodiment according to the first aspect of the invention the periodic high power frequency signal is a square-, triangular-, or sinusoidal signal.

According to a second aspect of the invention a method for synchronizing a periodic high frequency power signal and an external reference signal in accordance with appended independent method claim <NUM> comprises the steps of determining a phase difference of the periodic high frequency power signal and the external reference signal, regulating a frequency tuning word dependent on a value of the digital control signal, wherein the value of the digital control signal is in relation to a preset reference value range of the digital control signal, generating the periodic high frequency power signal at a digital oscillator circuit, routing the periodic high frequency power signal to a phase control circuit for synchronizing the two signals.

This allows a faster synchronization regarding a constant phase and /or frequency relationship of internal signals to external clock signals using the inventive method. Using the method allows synchronizing the RF output or CEX (short term for common exciter).

Further, this synchronization allows improving the digital phase locked loop based on a fixed phase relationship if the reference input and internal signal are configured to work at the same frequency.

Furthermore, this method advantageously allows a faster and broader frequency up-conversion and/or down-conversion of the reference signal frequency.

Further, this allows to faster controlling the frequency or phase of the internally generated signal using the frequency tuning word (FTW).

In a first embodiment according to the second aspect of the invention the method comprises the further step, wherein the preset reference value range of the digital control signal is preset between <NUM>,<NUM> to <NUM>,<NUM> of the reference value, preferably between <NUM>,<NUM> to <NUM>,<NUM> of the reference value.

According to the invention, the method comprises the step of activating a frequency tuning word at an activation circuit, in case a value of the digital control signal is outside a preset reference value range.

According to a third embodiment according to the second aspect of the invention the method for synchronizing a periodic high frequency power signal and an external reference signal, wherein a phase control circuit comprises a first counter and a second counter, further comprises the steps of determining a phase difference of the periodic high frequency power signal and the external reference signal by calculating a counting difference of the two counters, generating a frequency tuning word, which is routed to a digital oscillator circuit, generating the periodic high frequency power signal at a digital oscillator circuit dependent on the frequency tuning word, routing the periodic high frequency power signal to a phase control circuit for synchronizing the two signals.

In a fourth embodiment according to the second aspect of the invention the method comprises the further step of determining the phase difference of the periodic high frequency power signal and an external reference signal by calculating the counting difference of the two counters at the rising edge of a clock signal to be selected.

The invention will be described below with reference to different exemplary embodiments explained in detail in the following drawings.

<FIG> depicts a schematic diagram of an embodiment of the invention comprising a phase control circuit <NUM> and a digital oscillator circuit <NUM>. The output of the digital oscillator circuit <NUM> has a periodic high frequency power signal <NUM>. The digital oscillator circuit <NUM> is connected to the phase control circuit <NUM> and comprises means for generating the periodic high frequency power signal <NUM>, which is dependent on the control signal <NUM> from the phase control circuit <NUM>.

The phase control circuit <NUM> has one output and two inputs. The output has the control signal <NUM>. One input has an external reference signal <NUM> and the other input has the periodic high frequency power signal <NUM>. The signal <NUM> is looped back from the output of the circuit <NUM>. Such a loop is generally called a feedback or control loop or a phase locked loop (PLL).

Generally, a phase locked loop (PLL) is a control loop that synchronizes an oscillator in frequency and phase with an input signal. If the two signals are synchronized, the phase shift between the two is a fixed value. If there is a phase shift between the two signals that does not correspond to the fixed value, the oscillator is re-adjusted until the phase shift again corresponds to this value.

As shown in <FIG> the PLL consists of a phase control circuit <NUM> and a digital oscillator circuit <NUM>. The schematic diagram in <FIG> shows how these circuits or elements are connected in order to form a PLL.

<FIG> depicts schematically a further embodiment of the invention comprising the phase control circuit <NUM> and the digital oscillator circuit <NUM>. The phase control circuit <NUM> comprises a phase detector 100a. The device further comprises an optional loop filter <NUM> and an analog-to digital converter <NUM>. The digital oscillator circuit <NUM> comprises a signal processing circuit <NUM>, a direct digital synthesizer circuit <NUM> and a digital-to analog-converter <NUM>. The schematic diagram in <FIG> shows how these elements are connected in order to form a PLL.

The phase detector 100a compares the two input signals <NUM>, <NUM>, for example an external reference signal <NUM> and a high frequency power signal <NUM>. The signal <NUM> is generated by the digital oscillator circuit <NUM> and looped back to one of the inputs of the phase detector 100a.

Based on the comparison of the two signals <NUM>, <NUM>, the phase detector 100a produces an error signal <NUM>. The signal <NUM> is proportional to the phase difference of the two signals <NUM>, <NUM>. The phase difference is performed by a combination of flip-flop components of the phase detector 100a. Optionally, the error signal <NUM> can further be low-pass filtered using a so called loop filter <NUM>. The error signal <NUM> is used to drive the digital oscillator circuit <NUM>, which creates the output signal <NUM>. This output <NUM> is fed back to one of the inputs of the phase detector, producing a feedback loop or a so called phase locked loop (PLL). As an option, the generated high frequency power signal <NUM> can be fed back through an optional divider of the phase control circuit <NUM> (not shown in <FIG>).

For example, if the output phase of the generated signal <NUM> drifts, the error signal <NUM> will increase, driving the signal <NUM> of the digital oscillator <NUM> in the opposite direction so as to reduce the error. Thus, the output phase of the generated high frequency power signal <NUM> is locked to the phase at the other input signal, which is the reference signal <NUM>.

As shown in <FIG> a loop filter <NUM> or PLL loop filter <NUM> is connected between the phase detector 100a and the analog-to-digital converter <NUM>. The loop filter optionally can be configured as a low pass filter.

One function of the loop filter <NUM> is to determine disturbances, such as changes in the reference frequency or phase. Further, when specifying a loop filter the following points should be considered like the range over which the loop can achieve lock (pull-in range, lock range or capture range) or how fast the loop achieves lock time, lock-up time or settling time. Depending on the application, this may require one or more of the following: a simple proportion like gain or attenuation, an integral like a low pass filter and/or a derivative like high pass filter.

The second function of the loop filter <NUM> is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output, that is then applied to one of the inputs of the oscillator circuit <NUM>.

The analog-to-digital converter <NUM> (ADC) converts a continuous-time and continuous-amplitude analog signal <NUM> to a digital control signal <NUM>, which can be discrete-time and/or discrete-amplitude. The conversion involves quantization of the input, which can cause some amount of error or noise. Further, instead of continuously performing the conversion, an ADC <NUM> optionally converts periodically, sampling the input, limiting the allowable bandwidth of the input signal. The ADC <NUM> is characterized by its bandwidth and signal-to-noise ratio (SNR). The bandwidth of an ADC is given by its sampling rate.

The direct digital synthesizer circuit <NUM> generates a periodical signal y(t) <NUM>, which for example is sinusoidal. The circuit <NUM> comprises two parts. One part is for example an angle counter. This counter generates the angle θy(t) of the signal y(t). It is essentially a counter that counts in the range of <NUM> to 2π. On each clock cycle, the circuit <NUM> increments its counter by an amount equal to the value of the loop filter output. That is, θy(t) = θy(t-<NUM>) + εloop(t). Thus the loop filter output represents the change in the digital oscillator output's angle and can be written as εloop(t) = Δθy(t). Once the PLL has converged, the ideal loop filter output will be εloop(t) = Δθy (t) = Δθx = 2πfxdΔt where Δt represents the amount of time between samples. In other words, once the PLL has converged, the rate of change of the locally generated angle θy (t) will equal the rate of the change of the received signal angle θx (t).

The circuit <NUM> comprises as a second part the digital signal generator, which is a sine lookup table that outputs the sine or cosine of its input signal. By connecting the output of the angle counter to the digital signal generator, the circuit <NUM> is able to generate the output signal y(t) = cos(θy(t)). In practice, the loop filter integrator is often preloaded with an estimate of Δθx(t) so that the locally generated signal y(t) starts out near the frequency of x(t).

The DDS circuit <NUM> as shown in <FIG> is a combination of a phase-accumulator with following addition of a phase-offset and a sine-lookup-table (LUT) (not shown in <FIG>). The amplitude of the signal can be controlled via a multiplication of a (varying) factor with the output of the sine-LUT.

The digital oscillator circuit <NUM> further comprises a signal processing circuit <NUM>, which is connected to the digital-to-analog converter <NUM> and the direct digital synthesizer circuit <NUM>. The signal processing circuit <NUM> comprises an activation circuit <NUM> for activating a frequency tuning word <NUM> (FTW).

The activation circuit <NUM> comprises logical components 145a, 145b and 145c, which are used for activating a coarse tuning of the frequency tuning word <NUM>. These logical components may include one or more adding components, one or more differentiator components, one or more integrator components, "Tresh & Activate components" or any other logical component or number of logical components.

In case the loop filter <NUM> clips at GND/VCC the regulation of the frequency tuning word would be inactive. To avoid this effect a certain level or reference value is specified and also configured or pre-set as a reference value in the ADC <NUM>. If a certain value or level of the reference value at the ADC output is reached an Integrator 145c is activated. This pulls a "coarse FTW" 14b at an adding component <NUM> to a value in relation to the pre-set reference value so that the tuning of the "fine FTW" 14a can work in a safe area.

The signal processing circuit <NUM>, especially the activation circuit <NUM>, activates a more or less precise tuning dependent on the deviation regarding a preset reference value or reference ADC value or maximum ADC value. The deviation can be specified by a range between a low and a maximum level of the preset reference value or maximum value of the ADC output.

The activation circuit <NUM> is activated in case the actual value <NUM> at the output of the ADC or the digital control signal <NUM> is outside a pre-set range regarding the reference value. For example, if the actual value <NUM> is below or above this range the coarse tuning is activated by the activation circuit <NUM>. For example, the range can be defined as between <NUM>,<NUM> of the preset reference value or preset maximum ADC value as a first activation level and <NUM>,<NUM> of the preset reference value or preset maximum reference value as a second activation level. Optionally, the range is specified between <NUM>,<NUM> of the preset reference value or preset maximum ADC value as a first activation level and <NUM>,<NUM> of the preset reference value or preset maximum reference value as a second activation level.

The activation of the coarse tuning is dependent on the digital control signal <NUM> of the ADC <NUM> or the ADC value <NUM>, which is transmitted from of the analog-to-digital converter <NUM> to the input of the digital oscillator circuit <NUM>.

Optionally, the device may comprise a divider (not shown), which is usually located in the feedback path of the PLL. As an example, the divider (dividing by <NUM> or any other natural division factor) can be used to generate a fraction or a multiple of the generated signal <NUM> or the reference signal <NUM>.

As shown in <FIG> the device also comprises a digital-to-analog converter <NUM>. The digital-to-analog converter <NUM> (DAC) is an element that converts a digital signal into an analog signal, for example a high frequency power signal <NUM>. A DAC <NUM> converts an abstract number into a physical quantity e.g., a voltage. In particular, DACs are often used to convert finite-precision time series data to a continually varying physical signal.

An ideal DAC converts the abstract numbers into a conceptual sequence of impulses that are then processed by a reconstruction filter using some form of interpolation to fill in data between the impulses. A conventional practical DAC converts the numbers into a piecewise constant function made up of a sequence of rectangular functions that is modeled with the zero-order hold.

<FIG> depicts schematically a further embodiment of the invention comprising the phase control circuit <NUM> and the digital oscillator circuit <NUM>. The phase control circuit <NUM> comprises a first counter <NUM> and a second counter <NUM>. The digital oscillator circuit <NUM> comprises a signal processing circuit <NUM>, a direct digital synthesizer circuit <NUM> and a digital-to analog-converter <NUM>. The schematic diagram in <FIG> shows how these elements are connected in order to form a PLL.

The direct digital synthesizer circuit <NUM> in <FIG> corresponds to the direct digital synthesizer circuit <NUM> in <FIG>. The same applies to the digital-to-analog converter <NUM>, <NUM> in <FIG> and <FIG>.

The function of the direct digital synthesizer circuit <NUM> is explained as follows: The circuit <NUM> comprises a phase accumulator and a sine look up table (LUT) (Both not shown), optionally further or other digital components can be used. The accumulator itself first outputs a number p of the word width P at its output, which corresponds to the current phase of the waveform on the circle. In general, P < N is selected. This is followed by mapping the number p to the desired sample w of the waveform with the word width W. The waveform is digitally stored in a memory with 2P samples. The current value p forms the address for this memory and is thus mapped to the desired waveform. The waveform can be arbitrary, but mostly the sine or cosine form is used.

The resulting sampled values must then be converted to the desired waveform using a digital-to-analog converter <NUM> of the word width W. Depending on the number (P) and word width (W) of the sampled values, a very pure signal spectrum can be created.

The phase control circuit <NUM> compares the two input signals <NUM>, <NUM>, for example an external reference signal <NUM> and a high frequency power signal <NUM>. The signal <NUM> is generated by the digital oscillator circuit <NUM> and looped back to one of the inputs of the phase control circuit <NUM>.

Different to the phase control circuit <NUM> in <FIG> the phase control circuit <NUM> shown in <FIG> comprises two counters <NUM>, <NUM> for comparing the phase difference of the two signals <NUM>, <NUM>. Each counter is configured to count frequency and phase The phase difference is determined by calculating the counting difference of the two counters <NUM>, <NUM> by using means <NUM>, <NUM> and <NUM> of the signal processing circuit <NUM>.

The external reference signal <NUM> and the looped backed high frequency power signal <NUM> are fed to the differentiator component <NUM>.

The first counter <NUM> and the second counter <NUM> each divide the frequency of the signals by a natural division factor and so each counter allows the generation of fraction/multiples of the input signals.

Claim 1:
Device for synchronizing a periodic high frequency signal (<NUM>) and an external reference signal (<NUM>), comprising
a phase control circuit (<NUM>, <NUM>) configured to determine a phase difference of the periodic high frequency signal (<NUM>) and the external reference signal (<NUM>),
an analog-to-digital converter (<NUM>) having an input connected to an output of the phase control circuit (<NUM>, <NUM>),
a digital oscillator circuit (<NUM>, <NUM>), having an input connected to an output of the analog-to-digital converter (<NUM>) configured to provide a digital control signal (<NUM>),
and wherein the digital oscillator circuit (<NUM>, <NUM>) comprises means for generating the periodic high frequency signal (<NUM>) dependent on the digital control signal (<NUM>), further comprises a signal processing circuit (<NUM>), having an input connected to the analog-to-digital converter (<NUM>) and an output connected to the digital synthesizer circuit (<NUM>), and
wherein
the signal processing circuit (<NUM>) is configured to regulate a frequency tuning word (<NUM>) provided at the output of the signal processing circuit (<NUM>) dependent on a value of the digital control signal (<NUM>),
characterized in that
the signal processing circuit (<NUM>) comprises an activation circuit (<NUM>) configured to activate a coarse tuning of the frequency tuning word in case the value of the digital control signal (<NUM>) is outside a pre-set reference value range.